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-rw-r--r--Device/ST/STM32F1xx/Include/stm32f100xb.h6821
-rw-r--r--Device/ST/STM32F1xx/Include/stm32f100xe.h7434
-rw-r--r--Device/ST/STM32F1xx/Include/stm32f101x6.h6152
-rw-r--r--Device/ST/STM32F1xx/Include/stm32f101xb.h6281
-rw-r--r--Device/ST/STM32F1xx/Include/stm32f101xe.h7281
-rw-r--r--Device/ST/STM32F1xx/Include/stm32f101xg.h7514
-rw-r--r--Device/ST/STM32F1xx/Include/stm32f102x6.h7285
-rw-r--r--Device/ST/STM32F1xx/Include/stm32f102xb.h7405
-rw-r--r--Device/ST/STM32F1xx/Include/stm32f103x6.h10944
-rw-r--r--Device/ST/STM32F1xx/Include/stm32f103xb.h11073
-rw-r--r--Device/ST/STM32F1xx/Include/stm32f103xe.h12199
-rw-r--r--Device/ST/STM32F1xx/Include/stm32f103xg.h12383
-rw-r--r--Device/ST/STM32F1xx/Include/stm32f105xc.h15138
-rw-r--r--Device/ST/STM32F1xx/Include/stm32f107xc.h16051
-rw-r--r--Device/ST/STM32F1xx/Include/stm32f1xx.h238
-rw-r--r--Device/ST/STM32F1xx/Include/system_stm32f1xx.h116
-rw-r--r--Device/ST/STM32F4xx/Include/stm32f401xc.h4805
-rw-r--r--Device/ST/STM32F4xx/Include/stm32f401xe.h4805
-rw-r--r--Device/ST/STM32F4xx/Include/stm32f405xx.h7491
-rw-r--r--Device/ST/STM32F4xx/Include/stm32f407xx.h8140
-rw-r--r--Device/ST/STM32F4xx/Include/stm32f410cx.h3997
-rw-r--r--Device/ST/STM32F4xx/Include/stm32f410rx.h4001
-rw-r--r--Device/ST/STM32F4xx/Include/stm32f410tx.h3967
-rw-r--r--Device/ST/STM32F4xx/Include/stm32f411xe.h4830
-rw-r--r--Device/ST/STM32F4xx/Include/stm32f412cx.h6743
-rw-r--r--Device/ST/STM32F4xx/Include/stm32f412rx.h7388
-rw-r--r--Device/ST/STM32F4xx/Include/stm32f412vx.h7387
-rw-r--r--Device/ST/STM32F4xx/Include/stm32f412zx.h7389
-rw-r--r--Device/ST/STM32F4xx/Include/stm32f415xx.h7684
-rw-r--r--Device/ST/STM32F4xx/Include/stm32f417xx.h8328
-rw-r--r--Device/ST/STM32F4xx/Include/stm32f427xx.h8901
-rw-r--r--Device/ST/STM32F4xx/Include/stm32f429xx.h9118
-rw-r--r--Device/ST/STM32F4xx/Include/stm32f437xx.h9093
-rw-r--r--Device/ST/STM32F4xx/Include/stm32f439xx.h9306
-rw-r--r--Device/ST/STM32F4xx/Include/stm32f446xx.h8301
-rw-r--r--Device/ST/STM32F4xx/Include/stm32f469xx.h10250
-rw-r--r--Device/ST/STM32F4xx/Include/stm32f479xx.h10441
-rw-r--r--Device/ST/STM32F4xx/Include/stm32f4xx.h264
-rw-r--r--Device/ST/STM32F4xx/Include/system_stm32f4xx.h122
-rw-r--r--Include/arm_common_tables.h136
-rw-r--r--Include/arm_const_structs.h79
-rw-r--r--Include/arm_math.h7154
-rw-r--r--Include/cmsis_armcc.h734
-rw-r--r--Include/cmsis_armcc_V6.h1800
-rw-r--r--Include/cmsis_gcc.h1373
-rw-r--r--Include/core_cm0.h798
-rw-r--r--Include/core_cm0plus.h914
-rw-r--r--Include/core_cm3.h1763
-rw-r--r--Include/core_cm4.h1937
-rw-r--r--Include/core_cm7.h2512
-rw-r--r--Include/core_cmFunc.h87
-rw-r--r--Include/core_cmInstr.h87
-rw-r--r--Include/core_cmSimd.h96
-rw-r--r--Include/core_sc000.h926
-rw-r--r--Include/core_sc300.h1745
55 files changed, 309207 insertions, 0 deletions
diff --git a/Device/ST/STM32F1xx/Include/stm32f100xb.h b/Device/ST/STM32F1xx/Include/stm32f100xb.h
new file mode 100644
index 0000000..dd0027b
--- /dev/null
+++ b/Device/ST/STM32F1xx/Include/stm32f100xb.h
@@ -0,0 +1,6821 @@
+/**
+ ******************************************************************************
+ * @file stm32f100xb.h
+ * @author MCD Application Team
+ * @version V4.1.0
+ * @date 29-April-2016
+ * @brief CMSIS Cortex-M3 Device Peripheral Access Layer Header File.
+ * This file contains all the peripheral register's definitions, bits
+ * definitions and memory mapping for STM32F1xx devices.
+ *
+ * This file contains:
+ * - Data structures and the address mapping for all peripherals
+ * - Peripheral's registers declarations and bits definition
+ * - Macros to access peripheral’s registers hardware
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+
+/** @addtogroup CMSIS
+ * @{
+ */
+
+/** @addtogroup stm32f100xb
+ * @{
+ */
+
+#ifndef __STM32F100xB_H
+#define __STM32F100xB_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/** @addtogroup Configuration_section_for_CMSIS
+ * @{
+ */
+/**
+ * @brief Configuration of the Cortex-M3 Processor and Core Peripherals
+ */
+ #define __MPU_PRESENT 0 /*!< Other STM32 devices does not provide an MPU */
+#define __CM3_REV 0x0200 /*!< Core Revision r2p0 */
+#define __NVIC_PRIO_BITS 4 /*!< STM32 uses 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
+
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_interrupt_number_definition
+ * @{
+ */
+
+/**
+ * @brief STM32F10x Interrupt Number Definition, according to the selected device
+ * in @ref Library_configuration_section
+ */
+
+ /*!< Interrupt Number Definition */
+typedef enum
+{
+/****** Cortex-M3 Processor Exceptions Numbers ***************************************************/
+ NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
+ HardFault_IRQn = -13, /*!< 3 Cortex-M3 Hard Fault Interrupt */
+ MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */
+ BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */
+ UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */
+ SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */
+ DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */
+ PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */
+ SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */
+
+/****** STM32 specific Interrupt Numbers *********************************************************/
+ WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
+ PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */
+ TAMPER_IRQn = 2, /*!< Tamper Interrupt */
+ RTC_IRQn = 3, /*!< RTC global Interrupt */
+ FLASH_IRQn = 4, /*!< FLASH global Interrupt */
+ RCC_IRQn = 5, /*!< RCC global Interrupt */
+ EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */
+ EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */
+ EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */
+ EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */
+ EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */
+ DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 global Interrupt */
+ DMA1_Channel2_IRQn = 12, /*!< DMA1 Channel 2 global Interrupt */
+ DMA1_Channel3_IRQn = 13, /*!< DMA1 Channel 3 global Interrupt */
+ DMA1_Channel4_IRQn = 14, /*!< DMA1 Channel 4 global Interrupt */
+ DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 global Interrupt */
+ DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 global Interrupt */
+ DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 global Interrupt */
+ ADC1_IRQn = 18, /*!< ADC1 global Interrupt */
+ EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
+ TIM1_BRK_TIM15_IRQn = 24, /*!< TIM1 Break and TIM15 Interrupts */
+ TIM1_UP_TIM16_IRQn = 25, /*!< TIM1 Update and TIM16 Interrupts */
+ TIM1_TRG_COM_TIM17_IRQn = 26, /*!< TIM1 Trigger and Commutation and TIM17 Interrupt */
+ TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
+ TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
+ TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
+ TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
+ I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
+ I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
+ I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
+ I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
+ SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
+ SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
+ USART1_IRQn = 37, /*!< USART1 global Interrupt */
+ USART2_IRQn = 38, /*!< USART2 global Interrupt */
+ USART3_IRQn = 39, /*!< USART3 global Interrupt */
+ EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
+ RTC_Alarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */
+ CEC_IRQn = 42, /*!< HDMI-CEC Interrupt */
+ TIM6_DAC_IRQn = 54, /*!< TIM6 and DAC underrun Interrupt */
+ TIM7_IRQn = 55, /*!< TIM7 global Interrupt */
+} IRQn_Type;
+
+
+/**
+ * @}
+ */
+
+#include "core_cm3.h"
+#include "system_stm32f1xx.h"
+#include <stdint.h>
+
+/** @addtogroup Peripheral_registers_structures
+ * @{
+ */
+
+/**
+ * @brief Analog to Digital Converter
+ */
+
+typedef struct
+{
+ __IO uint32_t SR;
+ __IO uint32_t CR1;
+ __IO uint32_t CR2;
+ __IO uint32_t SMPR1;
+ __IO uint32_t SMPR2;
+ __IO uint32_t JOFR1;
+ __IO uint32_t JOFR2;
+ __IO uint32_t JOFR3;
+ __IO uint32_t JOFR4;
+ __IO uint32_t HTR;
+ __IO uint32_t LTR;
+ __IO uint32_t SQR1;
+ __IO uint32_t SQR2;
+ __IO uint32_t SQR3;
+ __IO uint32_t JSQR;
+ __IO uint32_t JDR1;
+ __IO uint32_t JDR2;
+ __IO uint32_t JDR3;
+ __IO uint32_t JDR4;
+ __IO uint32_t DR;
+} ADC_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t SR; /*!< ADC status register, used for ADC multimode (bits common to several ADC instances). Address offset: ADC1 base address */
+ __IO uint32_t CR1; /*!< ADC control register 1, used for ADC multimode (bits common to several ADC instances). Address offset: ADC1 base address + 0x04 */
+ __IO uint32_t CR2; /*!< ADC control register 2, used for ADC multimode (bits common to several ADC instances). Address offset: ADC1 base address + 0x08 */
+ uint32_t RESERVED[16];
+ __IO uint32_t DR; /*!< ADC data register, used for ADC multimode (bits common to several ADC instances). Address offset: ADC1 base address + 0x4C */
+} ADC_Common_TypeDef;
+
+/**
+ * @brief Backup Registers
+ */
+
+typedef struct
+{
+ uint32_t RESERVED0;
+ __IO uint32_t DR1;
+ __IO uint32_t DR2;
+ __IO uint32_t DR3;
+ __IO uint32_t DR4;
+ __IO uint32_t DR5;
+ __IO uint32_t DR6;
+ __IO uint32_t DR7;
+ __IO uint32_t DR8;
+ __IO uint32_t DR9;
+ __IO uint32_t DR10;
+ __IO uint32_t RTCCR;
+ __IO uint32_t CR;
+ __IO uint32_t CSR;
+} BKP_TypeDef;
+
+
+/**
+ * @brief Consumer Electronics Control (CEC)
+ */
+typedef struct
+{
+ __IO uint32_t CFGR;
+ __IO uint32_t OAR;
+ __IO uint32_t PRES;
+ __IO uint32_t ESR;
+ __IO uint32_t CSR;
+ __IO uint32_t TXD;
+ __IO uint32_t RXD;
+} CEC_TypeDef;
+
+/**
+ * @brief CRC calculation unit
+ */
+
+typedef struct
+{
+ __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
+ __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
+ uint8_t RESERVED0; /*!< Reserved, Address offset: 0x05 */
+ uint16_t RESERVED1; /*!< Reserved, Address offset: 0x06 */
+ __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
+} CRC_TypeDef;
+
+/**
+ * @brief Digital to Analog Converter
+ */
+
+typedef struct
+{
+ __IO uint32_t CR;
+ __IO uint32_t SWTRIGR;
+ __IO uint32_t DHR12R1;
+ __IO uint32_t DHR12L1;
+ __IO uint32_t DHR8R1;
+ __IO uint32_t DHR12R2;
+ __IO uint32_t DHR12L2;
+ __IO uint32_t DHR8R2;
+ __IO uint32_t DHR12RD;
+ __IO uint32_t DHR12LD;
+ __IO uint32_t DHR8RD;
+ __IO uint32_t DOR1;
+ __IO uint32_t DOR2;
+ __IO uint32_t SR;
+} DAC_TypeDef;
+
+/**
+ * @brief Debug MCU
+ */
+
+typedef struct
+{
+ __IO uint32_t IDCODE;
+ __IO uint32_t CR;
+}DBGMCU_TypeDef;
+
+/**
+ * @brief DMA Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t CCR;
+ __IO uint32_t CNDTR;
+ __IO uint32_t CPAR;
+ __IO uint32_t CMAR;
+} DMA_Channel_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t ISR;
+ __IO uint32_t IFCR;
+} DMA_TypeDef;
+
+
+
+/**
+ * @brief External Interrupt/Event Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t IMR;
+ __IO uint32_t EMR;
+ __IO uint32_t RTSR;
+ __IO uint32_t FTSR;
+ __IO uint32_t SWIER;
+ __IO uint32_t PR;
+} EXTI_TypeDef;
+
+/**
+ * @brief FLASH Registers
+ */
+
+typedef struct
+{
+ __IO uint32_t ACR;
+ __IO uint32_t KEYR;
+ __IO uint32_t OPTKEYR;
+ __IO uint32_t SR;
+ __IO uint32_t CR;
+ __IO uint32_t AR;
+ __IO uint32_t RESERVED;
+ __IO uint32_t OBR;
+ __IO uint32_t WRPR;
+} FLASH_TypeDef;
+
+/**
+ * @brief Option Bytes Registers
+ */
+
+typedef struct
+{
+ __IO uint16_t RDP;
+ __IO uint16_t USER;
+ __IO uint16_t Data0;
+ __IO uint16_t Data1;
+ __IO uint16_t WRP0;
+ __IO uint16_t WRP1;
+ __IO uint16_t WRP2;
+ __IO uint16_t WRP3;
+} OB_TypeDef;
+
+/**
+ * @brief General Purpose I/O
+ */
+
+typedef struct
+{
+ __IO uint32_t CRL;
+ __IO uint32_t CRH;
+ __IO uint32_t IDR;
+ __IO uint32_t ODR;
+ __IO uint32_t BSRR;
+ __IO uint32_t BRR;
+ __IO uint32_t LCKR;
+} GPIO_TypeDef;
+
+/**
+ * @brief Alternate Function I/O
+ */
+
+typedef struct
+{
+ __IO uint32_t EVCR;
+ __IO uint32_t MAPR;
+ __IO uint32_t EXTICR[4];
+ uint32_t RESERVED0;
+ __IO uint32_t MAPR2;
+} AFIO_TypeDef;
+/**
+ * @brief Inter Integrated Circuit Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t CR1;
+ __IO uint32_t CR2;
+ __IO uint32_t OAR1;
+ __IO uint32_t OAR2;
+ __IO uint32_t DR;
+ __IO uint32_t SR1;
+ __IO uint32_t SR2;
+ __IO uint32_t CCR;
+ __IO uint32_t TRISE;
+} I2C_TypeDef;
+
+/**
+ * @brief Independent WATCHDOG
+ */
+
+typedef struct
+{
+ __IO uint32_t KR; /*!< Key register, Address offset: 0x00 */
+ __IO uint32_t PR; /*!< Prescaler register, Address offset: 0x04 */
+ __IO uint32_t RLR; /*!< Reload register, Address offset: 0x08 */
+ __IO uint32_t SR; /*!< Status register, Address offset: 0x0C */
+} IWDG_TypeDef;
+
+/**
+ * @brief Power Control
+ */
+
+typedef struct
+{
+ __IO uint32_t CR;
+ __IO uint32_t CSR;
+} PWR_TypeDef;
+
+/**
+ * @brief Reset and Clock Control
+ */
+
+typedef struct
+{
+ __IO uint32_t CR;
+ __IO uint32_t CFGR;
+ __IO uint32_t CIR;
+ __IO uint32_t APB2RSTR;
+ __IO uint32_t APB1RSTR;
+ __IO uint32_t AHBENR;
+ __IO uint32_t APB2ENR;
+ __IO uint32_t APB1ENR;
+ __IO uint32_t BDCR;
+ __IO uint32_t CSR;
+
+
+ uint32_t RESERVED0;
+ __IO uint32_t CFGR2;
+} RCC_TypeDef;
+
+/**
+ * @brief Real-Time Clock
+ */
+
+typedef struct
+{
+ __IO uint32_t CRH;
+ __IO uint32_t CRL;
+ __IO uint32_t PRLH;
+ __IO uint32_t PRLL;
+ __IO uint32_t DIVH;
+ __IO uint32_t DIVL;
+ __IO uint32_t CNTH;
+ __IO uint32_t CNTL;
+ __IO uint32_t ALRH;
+ __IO uint32_t ALRL;
+} RTC_TypeDef;
+
+/**
+ * @brief SD host Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t POWER;
+ __IO uint32_t CLKCR;
+ __IO uint32_t ARG;
+ __IO uint32_t CMD;
+ __I uint32_t RESPCMD;
+ __I uint32_t RESP1;
+ __I uint32_t RESP2;
+ __I uint32_t RESP3;
+ __I uint32_t RESP4;
+ __IO uint32_t DTIMER;
+ __IO uint32_t DLEN;
+ __IO uint32_t DCTRL;
+ __I uint32_t DCOUNT;
+ __I uint32_t STA;
+ __IO uint32_t ICR;
+ __IO uint32_t MASK;
+ uint32_t RESERVED0[2];
+ __I uint32_t FIFOCNT;
+ uint32_t RESERVED1[13];
+ __IO uint32_t FIFO;
+} SDIO_TypeDef;
+
+/**
+ * @brief Serial Peripheral Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t CR1;
+ __IO uint32_t CR2;
+ __IO uint32_t SR;
+ __IO uint32_t DR;
+ __IO uint32_t CRCPR;
+ __IO uint32_t RXCRCR;
+ __IO uint32_t TXCRCR;
+} SPI_TypeDef;
+
+/**
+ * @brief TIM Timers
+ */
+typedef struct
+{
+ __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
+ __IO uint32_t SMCR; /*!< TIM slave Mode Control register, Address offset: 0x08 */
+ __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
+ __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
+ __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
+ __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
+ __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
+ __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
+ __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
+ __IO uint32_t PSC; /*!< TIM prescaler register, Address offset: 0x28 */
+ __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
+ __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */
+ __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
+ __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
+ __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
+ __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
+ __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
+ __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
+ __IO uint32_t DMAR; /*!< TIM DMA address for full transfer register, Address offset: 0x4C */
+ __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */
+}TIM_TypeDef;
+
+
+/**
+ * @brief Universal Synchronous Asynchronous Receiver Transmitter
+ */
+
+typedef struct
+{
+ __IO uint32_t SR; /*!< USART Status register, Address offset: 0x00 */
+ __IO uint32_t DR; /*!< USART Data register, Address offset: 0x04 */
+ __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x08 */
+ __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x0C */
+ __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x10 */
+ __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x14 */
+ __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x18 */
+} USART_TypeDef;
+
+
+
+/**
+ * @brief Window WATCHDOG
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
+ __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
+ __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
+} WWDG_TypeDef;
+
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_memory_map
+ * @{
+ */
+
+
+#define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH base address in the alias region */
+#define FLASH_BANK1_END ((uint32_t)0x0801FFFF) /*!< FLASH END address of bank1 */
+#define SRAM_BASE ((uint32_t)0x20000000) /*!< SRAM base address in the alias region */
+#define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */
+
+#define SRAM_BB_BASE ((uint32_t)0x22000000) /*!< SRAM base address in the bit-band region */
+#define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */
+
+
+/*!< Peripheral memory map */
+#define APB1PERIPH_BASE PERIPH_BASE
+#define APB2PERIPH_BASE (PERIPH_BASE + 0x10000)
+#define AHBPERIPH_BASE (PERIPH_BASE + 0x20000)
+
+#define TIM2_BASE (APB1PERIPH_BASE + 0x0000)
+#define TIM3_BASE (APB1PERIPH_BASE + 0x0400)
+#define TIM4_BASE (APB1PERIPH_BASE + 0x0800)
+#define TIM6_BASE (APB1PERIPH_BASE + 0x1000)
+#define TIM7_BASE (APB1PERIPH_BASE + 0x1400)
+#define RTC_BASE (APB1PERIPH_BASE + 0x2800)
+#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00)
+#define IWDG_BASE (APB1PERIPH_BASE + 0x3000)
+#define SPI2_BASE (APB1PERIPH_BASE + 0x3800)
+#define USART2_BASE (APB1PERIPH_BASE + 0x4400)
+#define USART3_BASE (APB1PERIPH_BASE + 0x4800)
+#define I2C1_BASE (APB1PERIPH_BASE + 0x5400)
+#define I2C2_BASE (APB1PERIPH_BASE + 0x5800)
+#define BKP_BASE (APB1PERIPH_BASE + 0x6C00)
+#define PWR_BASE (APB1PERIPH_BASE + 0x7000)
+#define DAC_BASE (APB1PERIPH_BASE + 0x7400)
+#define CEC_BASE (APB1PERIPH_BASE + 0x7800)
+#define AFIO_BASE (APB2PERIPH_BASE + 0x0000)
+#define EXTI_BASE (APB2PERIPH_BASE + 0x0400)
+#define GPIOA_BASE (APB2PERIPH_BASE + 0x0800)
+#define GPIOB_BASE (APB2PERIPH_BASE + 0x0C00)
+#define GPIOC_BASE (APB2PERIPH_BASE + 0x1000)
+#define GPIOD_BASE (APB2PERIPH_BASE + 0x1400)
+#define GPIOE_BASE (APB2PERIPH_BASE + 0x1800)
+#define ADC1_BASE (APB2PERIPH_BASE + 0x2400)
+#define TIM1_BASE (APB2PERIPH_BASE + 0x2C00)
+#define SPI1_BASE (APB2PERIPH_BASE + 0x3000)
+#define USART1_BASE (APB2PERIPH_BASE + 0x3800)
+#define TIM15_BASE (APB2PERIPH_BASE + 0x4000)
+#define TIM16_BASE (APB2PERIPH_BASE + 0x4400)
+#define TIM17_BASE (APB2PERIPH_BASE + 0x4800)
+
+#define SDIO_BASE (PERIPH_BASE + 0x18000)
+
+#define DMA1_BASE (AHBPERIPH_BASE + 0x0000)
+#define DMA1_Channel1_BASE (AHBPERIPH_BASE + 0x0008)
+#define DMA1_Channel2_BASE (AHBPERIPH_BASE + 0x001C)
+#define DMA1_Channel3_BASE (AHBPERIPH_BASE + 0x0030)
+#define DMA1_Channel4_BASE (AHBPERIPH_BASE + 0x0044)
+#define DMA1_Channel5_BASE (AHBPERIPH_BASE + 0x0058)
+#define DMA1_Channel6_BASE (AHBPERIPH_BASE + 0x006C)
+#define DMA1_Channel7_BASE (AHBPERIPH_BASE + 0x0080)
+#define RCC_BASE (AHBPERIPH_BASE + 0x1000)
+#define CRC_BASE (AHBPERIPH_BASE + 0x3000)
+
+#define FLASH_R_BASE (AHBPERIPH_BASE + 0x2000) /*!< Flash registers base address */
+#define FLASHSIZE_BASE ((uint32_t)0x1FFFF7E0) /*!< FLASH Size register base address */
+#define UID_BASE ((uint32_t)0x1FFFF7E8) /*!< Unique device ID register base address */
+#define OB_BASE ((uint32_t)0x1FFFF800) /*!< Flash Option Bytes base address */
+
+
+
+#define DBGMCU_BASE ((uint32_t)0xE0042000) /*!< Debug MCU registers base address */
+
+
+
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_declaration
+ * @{
+ */
+
+#define TIM2 ((TIM_TypeDef *) TIM2_BASE)
+#define TIM3 ((TIM_TypeDef *) TIM3_BASE)
+#define TIM4 ((TIM_TypeDef *) TIM4_BASE)
+#define TIM6 ((TIM_TypeDef *) TIM6_BASE)
+#define TIM7 ((TIM_TypeDef *) TIM7_BASE)
+#define RTC ((RTC_TypeDef *) RTC_BASE)
+#define WWDG ((WWDG_TypeDef *) WWDG_BASE)
+#define IWDG ((IWDG_TypeDef *) IWDG_BASE)
+#define SPI2 ((SPI_TypeDef *) SPI2_BASE)
+#define USART2 ((USART_TypeDef *) USART2_BASE)
+#define USART3 ((USART_TypeDef *) USART3_BASE)
+#define I2C1 ((I2C_TypeDef *) I2C1_BASE)
+#define I2C2 ((I2C_TypeDef *) I2C2_BASE)
+#define BKP ((BKP_TypeDef *) BKP_BASE)
+#define PWR ((PWR_TypeDef *) PWR_BASE)
+#define DAC ((DAC_TypeDef *) DAC_BASE)
+#define CEC ((CEC_TypeDef *) CEC_BASE)
+#define AFIO ((AFIO_TypeDef *) AFIO_BASE)
+#define EXTI ((EXTI_TypeDef *) EXTI_BASE)
+#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
+#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
+#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
+#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
+#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
+#define ADC1 ((ADC_TypeDef *) ADC1_BASE)
+#define ADC1_COMMON ((ADC_Common_TypeDef *) ADC1_BASE)
+#define TIM1 ((TIM_TypeDef *) TIM1_BASE)
+#define SPI1 ((SPI_TypeDef *) SPI1_BASE)
+#define USART1 ((USART_TypeDef *) USART1_BASE)
+#define TIM15 ((TIM_TypeDef *) TIM15_BASE)
+#define TIM16 ((TIM_TypeDef *) TIM16_BASE)
+#define TIM17 ((TIM_TypeDef *) TIM17_BASE)
+#define SDIO ((SDIO_TypeDef *) SDIO_BASE)
+#define DMA1 ((DMA_TypeDef *) DMA1_BASE)
+#define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
+#define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
+#define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
+#define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
+#define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
+#define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
+#define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
+#define RCC ((RCC_TypeDef *) RCC_BASE)
+#define CRC ((CRC_TypeDef *) CRC_BASE)
+#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
+#define OB ((OB_TypeDef *) OB_BASE)
+#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
+
+
+/**
+ * @}
+ */
+
+/** @addtogroup Exported_constants
+ * @{
+ */
+
+ /** @addtogroup Peripheral_Registers_Bits_Definition
+ * @{
+ */
+
+/******************************************************************************/
+/* Peripheral Registers_Bits_Definition */
+/******************************************************************************/
+
+/******************************************************************************/
+/* */
+/* CRC calculation unit (CRC) */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for CRC_DR register *********************/
+#define CRC_DR_DR_Pos (0U)
+#define CRC_DR_DR_Msk (0xFFFFFFFFU << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */
+#define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */
+
+/******************* Bit definition for CRC_IDR register ********************/
+#define CRC_IDR_IDR_Pos (0U)
+#define CRC_IDR_IDR_Msk (0xFFU << CRC_IDR_IDR_Pos) /*!< 0x000000FF */
+#define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 8-bit data register bits */
+
+/******************** Bit definition for CRC_CR register ********************/
+#define CRC_CR_RESET_Pos (0U)
+#define CRC_CR_RESET_Msk (0x1U << CRC_CR_RESET_Pos) /*!< 0x00000001 */
+#define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET bit */
+
+/******************************************************************************/
+/* */
+/* Power Control */
+/* */
+/******************************************************************************/
+
+/******************** Bit definition for PWR_CR register ********************/
+#define PWR_CR_LPDS_Pos (0U)
+#define PWR_CR_LPDS_Msk (0x1U << PWR_CR_LPDS_Pos) /*!< 0x00000001 */
+#define PWR_CR_LPDS PWR_CR_LPDS_Msk /*!< Low-Power Deepsleep */
+#define PWR_CR_PDDS_Pos (1U)
+#define PWR_CR_PDDS_Msk (0x1U << PWR_CR_PDDS_Pos) /*!< 0x00000002 */
+#define PWR_CR_PDDS PWR_CR_PDDS_Msk /*!< Power Down Deepsleep */
+#define PWR_CR_CWUF_Pos (2U)
+#define PWR_CR_CWUF_Msk (0x1U << PWR_CR_CWUF_Pos) /*!< 0x00000004 */
+#define PWR_CR_CWUF PWR_CR_CWUF_Msk /*!< Clear Wakeup Flag */
+#define PWR_CR_CSBF_Pos (3U)
+#define PWR_CR_CSBF_Msk (0x1U << PWR_CR_CSBF_Pos) /*!< 0x00000008 */
+#define PWR_CR_CSBF PWR_CR_CSBF_Msk /*!< Clear Standby Flag */
+#define PWR_CR_PVDE_Pos (4U)
+#define PWR_CR_PVDE_Msk (0x1U << PWR_CR_PVDE_Pos) /*!< 0x00000010 */
+#define PWR_CR_PVDE PWR_CR_PVDE_Msk /*!< Power Voltage Detector Enable */
+
+#define PWR_CR_PLS_Pos (5U)
+#define PWR_CR_PLS_Msk (0x7U << PWR_CR_PLS_Pos) /*!< 0x000000E0 */
+#define PWR_CR_PLS PWR_CR_PLS_Msk /*!< PLS[2:0] bits (PVD Level Selection) */
+#define PWR_CR_PLS_0 (0x1U << PWR_CR_PLS_Pos) /*!< 0x00000020 */
+#define PWR_CR_PLS_1 (0x2U << PWR_CR_PLS_Pos) /*!< 0x00000040 */
+#define PWR_CR_PLS_2 (0x4U << PWR_CR_PLS_Pos) /*!< 0x00000080 */
+
+/*!< PVD level configuration */
+#define PWR_CR_PLS_2V2 ((uint32_t)0x00000000) /*!< PVD level 2.2V */
+#define PWR_CR_PLS_2V3 ((uint32_t)0x00000020) /*!< PVD level 2.3V */
+#define PWR_CR_PLS_2V4 ((uint32_t)0x00000040) /*!< PVD level 2.4V */
+#define PWR_CR_PLS_2V5 ((uint32_t)0x00000060) /*!< PVD level 2.5V */
+#define PWR_CR_PLS_2V6 ((uint32_t)0x00000080) /*!< PVD level 2.6V */
+#define PWR_CR_PLS_2V7 ((uint32_t)0x000000A0) /*!< PVD level 2.7V */
+#define PWR_CR_PLS_2V8 ((uint32_t)0x000000C0) /*!< PVD level 2.8V */
+#define PWR_CR_PLS_2V9 ((uint32_t)0x000000E0) /*!< PVD level 2.9V */
+
+#define PWR_CR_DBP_Pos (8U)
+#define PWR_CR_DBP_Msk (0x1U << PWR_CR_DBP_Pos) /*!< 0x00000100 */
+#define PWR_CR_DBP PWR_CR_DBP_Msk /*!< Disable Backup Domain write protection */
+
+
+/******************* Bit definition for PWR_CSR register ********************/
+#define PWR_CSR_WUF_Pos (0U)
+#define PWR_CSR_WUF_Msk (0x1U << PWR_CSR_WUF_Pos) /*!< 0x00000001 */
+#define PWR_CSR_WUF PWR_CSR_WUF_Msk /*!< Wakeup Flag */
+#define PWR_CSR_SBF_Pos (1U)
+#define PWR_CSR_SBF_Msk (0x1U << PWR_CSR_SBF_Pos) /*!< 0x00000002 */
+#define PWR_CSR_SBF PWR_CSR_SBF_Msk /*!< Standby Flag */
+#define PWR_CSR_PVDO_Pos (2U)
+#define PWR_CSR_PVDO_Msk (0x1U << PWR_CSR_PVDO_Pos) /*!< 0x00000004 */
+#define PWR_CSR_PVDO PWR_CSR_PVDO_Msk /*!< PVD Output */
+#define PWR_CSR_EWUP_Pos (8U)
+#define PWR_CSR_EWUP_Msk (0x1U << PWR_CSR_EWUP_Pos) /*!< 0x00000100 */
+#define PWR_CSR_EWUP PWR_CSR_EWUP_Msk /*!< Enable WKUP pin */
+
+/******************************************************************************/
+/* */
+/* Backup registers */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for BKP_DR1 register ********************/
+#define BKP_DR1_D_Pos (0U)
+#define BKP_DR1_D_Msk (0xFFFFU << BKP_DR1_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR1_D BKP_DR1_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR2 register ********************/
+#define BKP_DR2_D_Pos (0U)
+#define BKP_DR2_D_Msk (0xFFFFU << BKP_DR2_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR2_D BKP_DR2_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR3 register ********************/
+#define BKP_DR3_D_Pos (0U)
+#define BKP_DR3_D_Msk (0xFFFFU << BKP_DR3_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR3_D BKP_DR3_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR4 register ********************/
+#define BKP_DR4_D_Pos (0U)
+#define BKP_DR4_D_Msk (0xFFFFU << BKP_DR4_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR4_D BKP_DR4_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR5 register ********************/
+#define BKP_DR5_D_Pos (0U)
+#define BKP_DR5_D_Msk (0xFFFFU << BKP_DR5_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR5_D BKP_DR5_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR6 register ********************/
+#define BKP_DR6_D_Pos (0U)
+#define BKP_DR6_D_Msk (0xFFFFU << BKP_DR6_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR6_D BKP_DR6_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR7 register ********************/
+#define BKP_DR7_D_Pos (0U)
+#define BKP_DR7_D_Msk (0xFFFFU << BKP_DR7_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR7_D BKP_DR7_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR8 register ********************/
+#define BKP_DR8_D_Pos (0U)
+#define BKP_DR8_D_Msk (0xFFFFU << BKP_DR8_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR8_D BKP_DR8_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR9 register ********************/
+#define BKP_DR9_D_Pos (0U)
+#define BKP_DR9_D_Msk (0xFFFFU << BKP_DR9_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR9_D BKP_DR9_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR10 register *******************/
+#define BKP_DR10_D_Pos (0U)
+#define BKP_DR10_D_Msk (0xFFFFU << BKP_DR10_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR10_D BKP_DR10_D_Msk /*!< Backup data */
+
+#define RTC_BKP_NUMBER 10
+
+/****************** Bit definition for BKP_RTCCR register *******************/
+#define BKP_RTCCR_CAL_Pos (0U)
+#define BKP_RTCCR_CAL_Msk (0x7FU << BKP_RTCCR_CAL_Pos) /*!< 0x0000007F */
+#define BKP_RTCCR_CAL BKP_RTCCR_CAL_Msk /*!< Calibration value */
+#define BKP_RTCCR_CCO_Pos (7U)
+#define BKP_RTCCR_CCO_Msk (0x1U << BKP_RTCCR_CCO_Pos) /*!< 0x00000080 */
+#define BKP_RTCCR_CCO BKP_RTCCR_CCO_Msk /*!< Calibration Clock Output */
+#define BKP_RTCCR_ASOE_Pos (8U)
+#define BKP_RTCCR_ASOE_Msk (0x1U << BKP_RTCCR_ASOE_Pos) /*!< 0x00000100 */
+#define BKP_RTCCR_ASOE BKP_RTCCR_ASOE_Msk /*!< Alarm or Second Output Enable */
+#define BKP_RTCCR_ASOS_Pos (9U)
+#define BKP_RTCCR_ASOS_Msk (0x1U << BKP_RTCCR_ASOS_Pos) /*!< 0x00000200 */
+#define BKP_RTCCR_ASOS BKP_RTCCR_ASOS_Msk /*!< Alarm or Second Output Selection */
+
+/******************** Bit definition for BKP_CR register ********************/
+#define BKP_CR_TPE_Pos (0U)
+#define BKP_CR_TPE_Msk (0x1U << BKP_CR_TPE_Pos) /*!< 0x00000001 */
+#define BKP_CR_TPE BKP_CR_TPE_Msk /*!< TAMPER pin enable */
+#define BKP_CR_TPAL_Pos (1U)
+#define BKP_CR_TPAL_Msk (0x1U << BKP_CR_TPAL_Pos) /*!< 0x00000002 */
+#define BKP_CR_TPAL BKP_CR_TPAL_Msk /*!< TAMPER pin active level */
+
+/******************* Bit definition for BKP_CSR register ********************/
+#define BKP_CSR_CTE_Pos (0U)
+#define BKP_CSR_CTE_Msk (0x1U << BKP_CSR_CTE_Pos) /*!< 0x00000001 */
+#define BKP_CSR_CTE BKP_CSR_CTE_Msk /*!< Clear Tamper event */
+#define BKP_CSR_CTI_Pos (1U)
+#define BKP_CSR_CTI_Msk (0x1U << BKP_CSR_CTI_Pos) /*!< 0x00000002 */
+#define BKP_CSR_CTI BKP_CSR_CTI_Msk /*!< Clear Tamper Interrupt */
+#define BKP_CSR_TPIE_Pos (2U)
+#define BKP_CSR_TPIE_Msk (0x1U << BKP_CSR_TPIE_Pos) /*!< 0x00000004 */
+#define BKP_CSR_TPIE BKP_CSR_TPIE_Msk /*!< TAMPER Pin interrupt enable */
+#define BKP_CSR_TEF_Pos (8U)
+#define BKP_CSR_TEF_Msk (0x1U << BKP_CSR_TEF_Pos) /*!< 0x00000100 */
+#define BKP_CSR_TEF BKP_CSR_TEF_Msk /*!< Tamper Event Flag */
+#define BKP_CSR_TIF_Pos (9U)
+#define BKP_CSR_TIF_Msk (0x1U << BKP_CSR_TIF_Pos) /*!< 0x00000200 */
+#define BKP_CSR_TIF BKP_CSR_TIF_Msk /*!< Tamper Interrupt Flag */
+
+/******************************************************************************/
+/* */
+/* Reset and Clock Control */
+/* */
+/******************************************************************************/
+
+/******************** Bit definition for RCC_CR register ********************/
+#define RCC_CR_HSION_Pos (0U)
+#define RCC_CR_HSION_Msk (0x1U << RCC_CR_HSION_Pos) /*!< 0x00000001 */
+#define RCC_CR_HSION RCC_CR_HSION_Msk /*!< Internal High Speed clock enable */
+#define RCC_CR_HSIRDY_Pos (1U)
+#define RCC_CR_HSIRDY_Msk (0x1U << RCC_CR_HSIRDY_Pos) /*!< 0x00000002 */
+#define RCC_CR_HSIRDY RCC_CR_HSIRDY_Msk /*!< Internal High Speed clock ready flag */
+#define RCC_CR_HSITRIM_Pos (3U)
+#define RCC_CR_HSITRIM_Msk (0x1FU << RCC_CR_HSITRIM_Pos) /*!< 0x000000F8 */
+#define RCC_CR_HSITRIM RCC_CR_HSITRIM_Msk /*!< Internal High Speed clock trimming */
+#define RCC_CR_HSICAL_Pos (8U)
+#define RCC_CR_HSICAL_Msk (0xFFU << RCC_CR_HSICAL_Pos) /*!< 0x0000FF00 */
+#define RCC_CR_HSICAL RCC_CR_HSICAL_Msk /*!< Internal High Speed clock Calibration */
+#define RCC_CR_HSEON_Pos (16U)
+#define RCC_CR_HSEON_Msk (0x1U << RCC_CR_HSEON_Pos) /*!< 0x00010000 */
+#define RCC_CR_HSEON RCC_CR_HSEON_Msk /*!< External High Speed clock enable */
+#define RCC_CR_HSERDY_Pos (17U)
+#define RCC_CR_HSERDY_Msk (0x1U << RCC_CR_HSERDY_Pos) /*!< 0x00020000 */
+#define RCC_CR_HSERDY RCC_CR_HSERDY_Msk /*!< External High Speed clock ready flag */
+#define RCC_CR_HSEBYP_Pos (18U)
+#define RCC_CR_HSEBYP_Msk (0x1U << RCC_CR_HSEBYP_Pos) /*!< 0x00040000 */
+#define RCC_CR_HSEBYP RCC_CR_HSEBYP_Msk /*!< External High Speed clock Bypass */
+#define RCC_CR_CSSON_Pos (19U)
+#define RCC_CR_CSSON_Msk (0x1U << RCC_CR_CSSON_Pos) /*!< 0x00080000 */
+#define RCC_CR_CSSON RCC_CR_CSSON_Msk /*!< Clock Security System enable */
+#define RCC_CR_PLLON_Pos (24U)
+#define RCC_CR_PLLON_Msk (0x1U << RCC_CR_PLLON_Pos) /*!< 0x01000000 */
+#define RCC_CR_PLLON RCC_CR_PLLON_Msk /*!< PLL enable */
+#define RCC_CR_PLLRDY_Pos (25U)
+#define RCC_CR_PLLRDY_Msk (0x1U << RCC_CR_PLLRDY_Pos) /*!< 0x02000000 */
+#define RCC_CR_PLLRDY RCC_CR_PLLRDY_Msk /*!< PLL clock ready flag */
+
+
+/******************* Bit definition for RCC_CFGR register *******************/
+/*!< SW configuration */
+#define RCC_CFGR_SW_Pos (0U)
+#define RCC_CFGR_SW_Msk (0x3U << RCC_CFGR_SW_Pos) /*!< 0x00000003 */
+#define RCC_CFGR_SW RCC_CFGR_SW_Msk /*!< SW[1:0] bits (System clock Switch) */
+#define RCC_CFGR_SW_0 (0x1U << RCC_CFGR_SW_Pos) /*!< 0x00000001 */
+#define RCC_CFGR_SW_1 (0x2U << RCC_CFGR_SW_Pos) /*!< 0x00000002 */
+
+#define RCC_CFGR_SW_HSI ((uint32_t)0x00000000) /*!< HSI selected as system clock */
+#define RCC_CFGR_SW_HSE ((uint32_t)0x00000001) /*!< HSE selected as system clock */
+#define RCC_CFGR_SW_PLL ((uint32_t)0x00000002) /*!< PLL selected as system clock */
+
+/*!< SWS configuration */
+#define RCC_CFGR_SWS_Pos (2U)
+#define RCC_CFGR_SWS_Msk (0x3U << RCC_CFGR_SWS_Pos) /*!< 0x0000000C */
+#define RCC_CFGR_SWS RCC_CFGR_SWS_Msk /*!< SWS[1:0] bits (System Clock Switch Status) */
+#define RCC_CFGR_SWS_0 (0x1U << RCC_CFGR_SWS_Pos) /*!< 0x00000004 */
+#define RCC_CFGR_SWS_1 (0x2U << RCC_CFGR_SWS_Pos) /*!< 0x00000008 */
+
+#define RCC_CFGR_SWS_HSI ((uint32_t)0x00000000) /*!< HSI oscillator used as system clock */
+#define RCC_CFGR_SWS_HSE ((uint32_t)0x00000004) /*!< HSE oscillator used as system clock */
+#define RCC_CFGR_SWS_PLL ((uint32_t)0x00000008) /*!< PLL used as system clock */
+
+/*!< HPRE configuration */
+#define RCC_CFGR_HPRE_Pos (4U)
+#define RCC_CFGR_HPRE_Msk (0xFU << RCC_CFGR_HPRE_Pos) /*!< 0x000000F0 */
+#define RCC_CFGR_HPRE RCC_CFGR_HPRE_Msk /*!< HPRE[3:0] bits (AHB prescaler) */
+#define RCC_CFGR_HPRE_0 (0x1U << RCC_CFGR_HPRE_Pos) /*!< 0x00000010 */
+#define RCC_CFGR_HPRE_1 (0x2U << RCC_CFGR_HPRE_Pos) /*!< 0x00000020 */
+#define RCC_CFGR_HPRE_2 (0x4U << RCC_CFGR_HPRE_Pos) /*!< 0x00000040 */
+#define RCC_CFGR_HPRE_3 (0x8U << RCC_CFGR_HPRE_Pos) /*!< 0x00000080 */
+
+#define RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000) /*!< SYSCLK not divided */
+#define RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080) /*!< SYSCLK divided by 2 */
+#define RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090) /*!< SYSCLK divided by 4 */
+#define RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0) /*!< SYSCLK divided by 8 */
+#define RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0) /*!< SYSCLK divided by 16 */
+#define RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0) /*!< SYSCLK divided by 64 */
+#define RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0) /*!< SYSCLK divided by 128 */
+#define RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0) /*!< SYSCLK divided by 256 */
+#define RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0) /*!< SYSCLK divided by 512 */
+
+/*!< PPRE1 configuration */
+#define RCC_CFGR_PPRE1_Pos (8U)
+#define RCC_CFGR_PPRE1_Msk (0x7U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000700 */
+#define RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_Msk /*!< PRE1[2:0] bits (APB1 prescaler) */
+#define RCC_CFGR_PPRE1_0 (0x1U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000100 */
+#define RCC_CFGR_PPRE1_1 (0x2U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000200 */
+#define RCC_CFGR_PPRE1_2 (0x4U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000400 */
+
+#define RCC_CFGR_PPRE1_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */
+#define RCC_CFGR_PPRE1_DIV2 ((uint32_t)0x00000400) /*!< HCLK divided by 2 */
+#define RCC_CFGR_PPRE1_DIV4 ((uint32_t)0x00000500) /*!< HCLK divided by 4 */
+#define RCC_CFGR_PPRE1_DIV8 ((uint32_t)0x00000600) /*!< HCLK divided by 8 */
+#define RCC_CFGR_PPRE1_DIV16 ((uint32_t)0x00000700) /*!< HCLK divided by 16 */
+
+/*!< PPRE2 configuration */
+#define RCC_CFGR_PPRE2_Pos (11U)
+#define RCC_CFGR_PPRE2_Msk (0x7U << RCC_CFGR_PPRE2_Pos) /*!< 0x00003800 */
+#define RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_Msk /*!< PRE2[2:0] bits (APB2 prescaler) */
+#define RCC_CFGR_PPRE2_0 (0x1U << RCC_CFGR_PPRE2_Pos) /*!< 0x00000800 */
+#define RCC_CFGR_PPRE2_1 (0x2U << RCC_CFGR_PPRE2_Pos) /*!< 0x00001000 */
+#define RCC_CFGR_PPRE2_2 (0x4U << RCC_CFGR_PPRE2_Pos) /*!< 0x00002000 */
+
+#define RCC_CFGR_PPRE2_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */
+#define RCC_CFGR_PPRE2_DIV2 ((uint32_t)0x00002000) /*!< HCLK divided by 2 */
+#define RCC_CFGR_PPRE2_DIV4 ((uint32_t)0x00002800) /*!< HCLK divided by 4 */
+#define RCC_CFGR_PPRE2_DIV8 ((uint32_t)0x00003000) /*!< HCLK divided by 8 */
+#define RCC_CFGR_PPRE2_DIV16 ((uint32_t)0x00003800) /*!< HCLK divided by 16 */
+
+/*!< ADCPPRE configuration */
+#define RCC_CFGR_ADCPRE_Pos (14U)
+#define RCC_CFGR_ADCPRE_Msk (0x3U << RCC_CFGR_ADCPRE_Pos) /*!< 0x0000C000 */
+#define RCC_CFGR_ADCPRE RCC_CFGR_ADCPRE_Msk /*!< ADCPRE[1:0] bits (ADC prescaler) */
+#define RCC_CFGR_ADCPRE_0 (0x1U << RCC_CFGR_ADCPRE_Pos) /*!< 0x00004000 */
+#define RCC_CFGR_ADCPRE_1 (0x2U << RCC_CFGR_ADCPRE_Pos) /*!< 0x00008000 */
+
+#define RCC_CFGR_ADCPRE_DIV2 ((uint32_t)0x00000000) /*!< PCLK2 divided by 2 */
+#define RCC_CFGR_ADCPRE_DIV4 ((uint32_t)0x00004000) /*!< PCLK2 divided by 4 */
+#define RCC_CFGR_ADCPRE_DIV6 ((uint32_t)0x00008000) /*!< PCLK2 divided by 6 */
+#define RCC_CFGR_ADCPRE_DIV8 ((uint32_t)0x0000C000) /*!< PCLK2 divided by 8 */
+
+#define RCC_CFGR_PLLSRC_Pos (16U)
+#define RCC_CFGR_PLLSRC_Msk (0x1U << RCC_CFGR_PLLSRC_Pos) /*!< 0x00010000 */
+#define RCC_CFGR_PLLSRC RCC_CFGR_PLLSRC_Msk /*!< PLL entry clock source */
+
+#define RCC_CFGR_PLLXTPRE_Pos (17U)
+#define RCC_CFGR_PLLXTPRE_Msk (0x1U << RCC_CFGR_PLLXTPRE_Pos) /*!< 0x00020000 */
+#define RCC_CFGR_PLLXTPRE RCC_CFGR_PLLXTPRE_Msk /*!< HSE divider for PLL entry */
+
+/*!< PLLMUL configuration */
+#define RCC_CFGR_PLLMULL_Pos (18U)
+#define RCC_CFGR_PLLMULL_Msk (0xFU << RCC_CFGR_PLLMULL_Pos) /*!< 0x003C0000 */
+#define RCC_CFGR_PLLMULL RCC_CFGR_PLLMULL_Msk /*!< PLLMUL[3:0] bits (PLL multiplication factor) */
+#define RCC_CFGR_PLLMULL_0 (0x1U << RCC_CFGR_PLLMULL_Pos) /*!< 0x00040000 */
+#define RCC_CFGR_PLLMULL_1 (0x2U << RCC_CFGR_PLLMULL_Pos) /*!< 0x00080000 */
+#define RCC_CFGR_PLLMULL_2 (0x4U << RCC_CFGR_PLLMULL_Pos) /*!< 0x00100000 */
+#define RCC_CFGR_PLLMULL_3 (0x8U << RCC_CFGR_PLLMULL_Pos) /*!< 0x00200000 */
+
+#define RCC_CFGR_PLLXTPRE_PREDIV1 ((uint32_t)0x00000000) /*!< PREDIV1 clock not divided for PLL entry */
+#define RCC_CFGR_PLLXTPRE_PREDIV1_DIV2 ((uint32_t)0x00020000) /*!< PREDIV1 clock divided by 2 for PLL entry */
+
+#define RCC_CFGR_PLLMULL2 ((uint32_t)0x00000000) /*!< PLL input clock*2 */
+#define RCC_CFGR_PLLMULL3_Pos (18U)
+#define RCC_CFGR_PLLMULL3_Msk (0x1U << RCC_CFGR_PLLMULL3_Pos) /*!< 0x00040000 */
+#define RCC_CFGR_PLLMULL3 RCC_CFGR_PLLMULL3_Msk /*!< PLL input clock*3 */
+#define RCC_CFGR_PLLMULL4_Pos (19U)
+#define RCC_CFGR_PLLMULL4_Msk (0x1U << RCC_CFGR_PLLMULL4_Pos) /*!< 0x00080000 */
+#define RCC_CFGR_PLLMULL4 RCC_CFGR_PLLMULL4_Msk /*!< PLL input clock*4 */
+#define RCC_CFGR_PLLMULL5_Pos (18U)
+#define RCC_CFGR_PLLMULL5_Msk (0x3U << RCC_CFGR_PLLMULL5_Pos) /*!< 0x000C0000 */
+#define RCC_CFGR_PLLMULL5 RCC_CFGR_PLLMULL5_Msk /*!< PLL input clock*5 */
+#define RCC_CFGR_PLLMULL6_Pos (20U)
+#define RCC_CFGR_PLLMULL6_Msk (0x1U << RCC_CFGR_PLLMULL6_Pos) /*!< 0x00100000 */
+#define RCC_CFGR_PLLMULL6 RCC_CFGR_PLLMULL6_Msk /*!< PLL input clock*6 */
+#define RCC_CFGR_PLLMULL7_Pos (18U)
+#define RCC_CFGR_PLLMULL7_Msk (0x5U << RCC_CFGR_PLLMULL7_Pos) /*!< 0x00140000 */
+#define RCC_CFGR_PLLMULL7 RCC_CFGR_PLLMULL7_Msk /*!< PLL input clock*7 */
+#define RCC_CFGR_PLLMULL8_Pos (19U)
+#define RCC_CFGR_PLLMULL8_Msk (0x3U << RCC_CFGR_PLLMULL8_Pos) /*!< 0x00180000 */
+#define RCC_CFGR_PLLMULL8 RCC_CFGR_PLLMULL8_Msk /*!< PLL input clock*8 */
+#define RCC_CFGR_PLLMULL9_Pos (18U)
+#define RCC_CFGR_PLLMULL9_Msk (0x7U << RCC_CFGR_PLLMULL9_Pos) /*!< 0x001C0000 */
+#define RCC_CFGR_PLLMULL9 RCC_CFGR_PLLMULL9_Msk /*!< PLL input clock*9 */
+#define RCC_CFGR_PLLMULL10_Pos (21U)
+#define RCC_CFGR_PLLMULL10_Msk (0x1U << RCC_CFGR_PLLMULL10_Pos) /*!< 0x00200000 */
+#define RCC_CFGR_PLLMULL10 RCC_CFGR_PLLMULL10_Msk /*!< PLL input clock10 */
+#define RCC_CFGR_PLLMULL11_Pos (18U)
+#define RCC_CFGR_PLLMULL11_Msk (0x9U << RCC_CFGR_PLLMULL11_Pos) /*!< 0x00240000 */
+#define RCC_CFGR_PLLMULL11 RCC_CFGR_PLLMULL11_Msk /*!< PLL input clock*11 */
+#define RCC_CFGR_PLLMULL12_Pos (19U)
+#define RCC_CFGR_PLLMULL12_Msk (0x5U << RCC_CFGR_PLLMULL12_Pos) /*!< 0x00280000 */
+#define RCC_CFGR_PLLMULL12 RCC_CFGR_PLLMULL12_Msk /*!< PLL input clock*12 */
+#define RCC_CFGR_PLLMULL13_Pos (18U)
+#define RCC_CFGR_PLLMULL13_Msk (0xBU << RCC_CFGR_PLLMULL13_Pos) /*!< 0x002C0000 */
+#define RCC_CFGR_PLLMULL13 RCC_CFGR_PLLMULL13_Msk /*!< PLL input clock*13 */
+#define RCC_CFGR_PLLMULL14_Pos (20U)
+#define RCC_CFGR_PLLMULL14_Msk (0x3U << RCC_CFGR_PLLMULL14_Pos) /*!< 0x00300000 */
+#define RCC_CFGR_PLLMULL14 RCC_CFGR_PLLMULL14_Msk /*!< PLL input clock*14 */
+#define RCC_CFGR_PLLMULL15_Pos (18U)
+#define RCC_CFGR_PLLMULL15_Msk (0xDU << RCC_CFGR_PLLMULL15_Pos) /*!< 0x00340000 */
+#define RCC_CFGR_PLLMULL15 RCC_CFGR_PLLMULL15_Msk /*!< PLL input clock*15 */
+#define RCC_CFGR_PLLMULL16_Pos (19U)
+#define RCC_CFGR_PLLMULL16_Msk (0x7U << RCC_CFGR_PLLMULL16_Pos) /*!< 0x00380000 */
+#define RCC_CFGR_PLLMULL16 RCC_CFGR_PLLMULL16_Msk /*!< PLL input clock*16 */
+
+/*!< MCO configuration */
+#define RCC_CFGR_MCO_Pos (24U)
+#define RCC_CFGR_MCO_Msk (0x7U << RCC_CFGR_MCO_Pos) /*!< 0x07000000 */
+#define RCC_CFGR_MCO RCC_CFGR_MCO_Msk /*!< MCO[2:0] bits (Microcontroller Clock Output) */
+#define RCC_CFGR_MCO_0 (0x1U << RCC_CFGR_MCO_Pos) /*!< 0x01000000 */
+#define RCC_CFGR_MCO_1 (0x2U << RCC_CFGR_MCO_Pos) /*!< 0x02000000 */
+#define RCC_CFGR_MCO_2 (0x4U << RCC_CFGR_MCO_Pos) /*!< 0x04000000 */
+
+#define RCC_CFGR_MCO_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */
+#define RCC_CFGR_MCO_SYSCLK ((uint32_t)0x04000000) /*!< System clock selected as MCO source */
+#define RCC_CFGR_MCO_HSI ((uint32_t)0x05000000) /*!< HSI clock selected as MCO source */
+#define RCC_CFGR_MCO_HSE ((uint32_t)0x06000000) /*!< HSE clock selected as MCO source */
+#define RCC_CFGR_MCO_PLLCLK_DIV2 ((uint32_t)0x07000000) /*!< PLL clock divided by 2 selected as MCO source */
+
+ /* Reference defines */
+ #define RCC_CFGR_MCOSEL RCC_CFGR_MCO
+ #define RCC_CFGR_MCOSEL_0 RCC_CFGR_MCO_0
+ #define RCC_CFGR_MCOSEL_1 RCC_CFGR_MCO_1
+ #define RCC_CFGR_MCOSEL_2 RCC_CFGR_MCO_2
+ #define RCC_CFGR_MCOSEL_NOCLOCK RCC_CFGR_MCO_NOCLOCK
+ #define RCC_CFGR_MCOSEL_SYSCLK RCC_CFGR_MCO_SYSCLK
+ #define RCC_CFGR_MCOSEL_HSI RCC_CFGR_MCO_HSI
+ #define RCC_CFGR_MCOSEL_HSE RCC_CFGR_MCO_HSE
+ #define RCC_CFGR_MCOSEL_PLL_DIV2 RCC_CFGR_MCO_PLLCLK_DIV2
+
+/*!<****************** Bit definition for RCC_CIR register ********************/
+#define RCC_CIR_LSIRDYF_Pos (0U)
+#define RCC_CIR_LSIRDYF_Msk (0x1U << RCC_CIR_LSIRDYF_Pos) /*!< 0x00000001 */
+#define RCC_CIR_LSIRDYF RCC_CIR_LSIRDYF_Msk /*!< LSI Ready Interrupt flag */
+#define RCC_CIR_LSERDYF_Pos (1U)
+#define RCC_CIR_LSERDYF_Msk (0x1U << RCC_CIR_LSERDYF_Pos) /*!< 0x00000002 */
+#define RCC_CIR_LSERDYF RCC_CIR_LSERDYF_Msk /*!< LSE Ready Interrupt flag */
+#define RCC_CIR_HSIRDYF_Pos (2U)
+#define RCC_CIR_HSIRDYF_Msk (0x1U << RCC_CIR_HSIRDYF_Pos) /*!< 0x00000004 */
+#define RCC_CIR_HSIRDYF RCC_CIR_HSIRDYF_Msk /*!< HSI Ready Interrupt flag */
+#define RCC_CIR_HSERDYF_Pos (3U)
+#define RCC_CIR_HSERDYF_Msk (0x1U << RCC_CIR_HSERDYF_Pos) /*!< 0x00000008 */
+#define RCC_CIR_HSERDYF RCC_CIR_HSERDYF_Msk /*!< HSE Ready Interrupt flag */
+#define RCC_CIR_PLLRDYF_Pos (4U)
+#define RCC_CIR_PLLRDYF_Msk (0x1U << RCC_CIR_PLLRDYF_Pos) /*!< 0x00000010 */
+#define RCC_CIR_PLLRDYF RCC_CIR_PLLRDYF_Msk /*!< PLL Ready Interrupt flag */
+#define RCC_CIR_CSSF_Pos (7U)
+#define RCC_CIR_CSSF_Msk (0x1U << RCC_CIR_CSSF_Pos) /*!< 0x00000080 */
+#define RCC_CIR_CSSF RCC_CIR_CSSF_Msk /*!< Clock Security System Interrupt flag */
+#define RCC_CIR_LSIRDYIE_Pos (8U)
+#define RCC_CIR_LSIRDYIE_Msk (0x1U << RCC_CIR_LSIRDYIE_Pos) /*!< 0x00000100 */
+#define RCC_CIR_LSIRDYIE RCC_CIR_LSIRDYIE_Msk /*!< LSI Ready Interrupt Enable */
+#define RCC_CIR_LSERDYIE_Pos (9U)
+#define RCC_CIR_LSERDYIE_Msk (0x1U << RCC_CIR_LSERDYIE_Pos) /*!< 0x00000200 */
+#define RCC_CIR_LSERDYIE RCC_CIR_LSERDYIE_Msk /*!< LSE Ready Interrupt Enable */
+#define RCC_CIR_HSIRDYIE_Pos (10U)
+#define RCC_CIR_HSIRDYIE_Msk (0x1U << RCC_CIR_HSIRDYIE_Pos) /*!< 0x00000400 */
+#define RCC_CIR_HSIRDYIE RCC_CIR_HSIRDYIE_Msk /*!< HSI Ready Interrupt Enable */
+#define RCC_CIR_HSERDYIE_Pos (11U)
+#define RCC_CIR_HSERDYIE_Msk (0x1U << RCC_CIR_HSERDYIE_Pos) /*!< 0x00000800 */
+#define RCC_CIR_HSERDYIE RCC_CIR_HSERDYIE_Msk /*!< HSE Ready Interrupt Enable */
+#define RCC_CIR_PLLRDYIE_Pos (12U)
+#define RCC_CIR_PLLRDYIE_Msk (0x1U << RCC_CIR_PLLRDYIE_Pos) /*!< 0x00001000 */
+#define RCC_CIR_PLLRDYIE RCC_CIR_PLLRDYIE_Msk /*!< PLL Ready Interrupt Enable */
+#define RCC_CIR_LSIRDYC_Pos (16U)
+#define RCC_CIR_LSIRDYC_Msk (0x1U << RCC_CIR_LSIRDYC_Pos) /*!< 0x00010000 */
+#define RCC_CIR_LSIRDYC RCC_CIR_LSIRDYC_Msk /*!< LSI Ready Interrupt Clear */
+#define RCC_CIR_LSERDYC_Pos (17U)
+#define RCC_CIR_LSERDYC_Msk (0x1U << RCC_CIR_LSERDYC_Pos) /*!< 0x00020000 */
+#define RCC_CIR_LSERDYC RCC_CIR_LSERDYC_Msk /*!< LSE Ready Interrupt Clear */
+#define RCC_CIR_HSIRDYC_Pos (18U)
+#define RCC_CIR_HSIRDYC_Msk (0x1U << RCC_CIR_HSIRDYC_Pos) /*!< 0x00040000 */
+#define RCC_CIR_HSIRDYC RCC_CIR_HSIRDYC_Msk /*!< HSI Ready Interrupt Clear */
+#define RCC_CIR_HSERDYC_Pos (19U)
+#define RCC_CIR_HSERDYC_Msk (0x1U << RCC_CIR_HSERDYC_Pos) /*!< 0x00080000 */
+#define RCC_CIR_HSERDYC RCC_CIR_HSERDYC_Msk /*!< HSE Ready Interrupt Clear */
+#define RCC_CIR_PLLRDYC_Pos (20U)
+#define RCC_CIR_PLLRDYC_Msk (0x1U << RCC_CIR_PLLRDYC_Pos) /*!< 0x00100000 */
+#define RCC_CIR_PLLRDYC RCC_CIR_PLLRDYC_Msk /*!< PLL Ready Interrupt Clear */
+#define RCC_CIR_CSSC_Pos (23U)
+#define RCC_CIR_CSSC_Msk (0x1U << RCC_CIR_CSSC_Pos) /*!< 0x00800000 */
+#define RCC_CIR_CSSC RCC_CIR_CSSC_Msk /*!< Clock Security System Interrupt Clear */
+
+
+/***************** Bit definition for RCC_APB2RSTR register *****************/
+#define RCC_APB2RSTR_AFIORST_Pos (0U)
+#define RCC_APB2RSTR_AFIORST_Msk (0x1U << RCC_APB2RSTR_AFIORST_Pos) /*!< 0x00000001 */
+#define RCC_APB2RSTR_AFIORST RCC_APB2RSTR_AFIORST_Msk /*!< Alternate Function I/O reset */
+#define RCC_APB2RSTR_IOPARST_Pos (2U)
+#define RCC_APB2RSTR_IOPARST_Msk (0x1U << RCC_APB2RSTR_IOPARST_Pos) /*!< 0x00000004 */
+#define RCC_APB2RSTR_IOPARST RCC_APB2RSTR_IOPARST_Msk /*!< I/O port A reset */
+#define RCC_APB2RSTR_IOPBRST_Pos (3U)
+#define RCC_APB2RSTR_IOPBRST_Msk (0x1U << RCC_APB2RSTR_IOPBRST_Pos) /*!< 0x00000008 */
+#define RCC_APB2RSTR_IOPBRST RCC_APB2RSTR_IOPBRST_Msk /*!< I/O port B reset */
+#define RCC_APB2RSTR_IOPCRST_Pos (4U)
+#define RCC_APB2RSTR_IOPCRST_Msk (0x1U << RCC_APB2RSTR_IOPCRST_Pos) /*!< 0x00000010 */
+#define RCC_APB2RSTR_IOPCRST RCC_APB2RSTR_IOPCRST_Msk /*!< I/O port C reset */
+#define RCC_APB2RSTR_IOPDRST_Pos (5U)
+#define RCC_APB2RSTR_IOPDRST_Msk (0x1U << RCC_APB2RSTR_IOPDRST_Pos) /*!< 0x00000020 */
+#define RCC_APB2RSTR_IOPDRST RCC_APB2RSTR_IOPDRST_Msk /*!< I/O port D reset */
+#define RCC_APB2RSTR_ADC1RST_Pos (9U)
+#define RCC_APB2RSTR_ADC1RST_Msk (0x1U << RCC_APB2RSTR_ADC1RST_Pos) /*!< 0x00000200 */
+#define RCC_APB2RSTR_ADC1RST RCC_APB2RSTR_ADC1RST_Msk /*!< ADC 1 interface reset */
+
+
+#define RCC_APB2RSTR_TIM1RST_Pos (11U)
+#define RCC_APB2RSTR_TIM1RST_Msk (0x1U << RCC_APB2RSTR_TIM1RST_Pos) /*!< 0x00000800 */
+#define RCC_APB2RSTR_TIM1RST RCC_APB2RSTR_TIM1RST_Msk /*!< TIM1 Timer reset */
+#define RCC_APB2RSTR_SPI1RST_Pos (12U)
+#define RCC_APB2RSTR_SPI1RST_Msk (0x1U << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */
+#define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk /*!< SPI 1 reset */
+#define RCC_APB2RSTR_USART1RST_Pos (14U)
+#define RCC_APB2RSTR_USART1RST_Msk (0x1U << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00004000 */
+#define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk /*!< USART1 reset */
+
+#define RCC_APB2RSTR_TIM15RST_Pos (16U)
+#define RCC_APB2RSTR_TIM15RST_Msk (0x1U << RCC_APB2RSTR_TIM15RST_Pos) /*!< 0x00010000 */
+#define RCC_APB2RSTR_TIM15RST RCC_APB2RSTR_TIM15RST_Msk /*!< TIM15 Timer reset */
+#define RCC_APB2RSTR_TIM16RST_Pos (17U)
+#define RCC_APB2RSTR_TIM16RST_Msk (0x1U << RCC_APB2RSTR_TIM16RST_Pos) /*!< 0x00020000 */
+#define RCC_APB2RSTR_TIM16RST RCC_APB2RSTR_TIM16RST_Msk /*!< TIM16 Timer reset */
+#define RCC_APB2RSTR_TIM17RST_Pos (18U)
+#define RCC_APB2RSTR_TIM17RST_Msk (0x1U << RCC_APB2RSTR_TIM17RST_Pos) /*!< 0x00040000 */
+#define RCC_APB2RSTR_TIM17RST RCC_APB2RSTR_TIM17RST_Msk /*!< TIM17 Timer reset */
+
+#define RCC_APB2RSTR_IOPERST_Pos (6U)
+#define RCC_APB2RSTR_IOPERST_Msk (0x1U << RCC_APB2RSTR_IOPERST_Pos) /*!< 0x00000040 */
+#define RCC_APB2RSTR_IOPERST RCC_APB2RSTR_IOPERST_Msk /*!< I/O port E reset */
+
+
+
+
+/***************** Bit definition for RCC_APB1RSTR register *****************/
+#define RCC_APB1RSTR_TIM2RST_Pos (0U)
+#define RCC_APB1RSTR_TIM2RST_Msk (0x1U << RCC_APB1RSTR_TIM2RST_Pos) /*!< 0x00000001 */
+#define RCC_APB1RSTR_TIM2RST RCC_APB1RSTR_TIM2RST_Msk /*!< Timer 2 reset */
+#define RCC_APB1RSTR_TIM3RST_Pos (1U)
+#define RCC_APB1RSTR_TIM3RST_Msk (0x1U << RCC_APB1RSTR_TIM3RST_Pos) /*!< 0x00000002 */
+#define RCC_APB1RSTR_TIM3RST RCC_APB1RSTR_TIM3RST_Msk /*!< Timer 3 reset */
+#define RCC_APB1RSTR_WWDGRST_Pos (11U)
+#define RCC_APB1RSTR_WWDGRST_Msk (0x1U << RCC_APB1RSTR_WWDGRST_Pos) /*!< 0x00000800 */
+#define RCC_APB1RSTR_WWDGRST RCC_APB1RSTR_WWDGRST_Msk /*!< Window Watchdog reset */
+#define RCC_APB1RSTR_USART2RST_Pos (17U)
+#define RCC_APB1RSTR_USART2RST_Msk (0x1U << RCC_APB1RSTR_USART2RST_Pos) /*!< 0x00020000 */
+#define RCC_APB1RSTR_USART2RST RCC_APB1RSTR_USART2RST_Msk /*!< USART 2 reset */
+#define RCC_APB1RSTR_I2C1RST_Pos (21U)
+#define RCC_APB1RSTR_I2C1RST_Msk (0x1U << RCC_APB1RSTR_I2C1RST_Pos) /*!< 0x00200000 */
+#define RCC_APB1RSTR_I2C1RST RCC_APB1RSTR_I2C1RST_Msk /*!< I2C 1 reset */
+
+
+#define RCC_APB1RSTR_BKPRST_Pos (27U)
+#define RCC_APB1RSTR_BKPRST_Msk (0x1U << RCC_APB1RSTR_BKPRST_Pos) /*!< 0x08000000 */
+#define RCC_APB1RSTR_BKPRST RCC_APB1RSTR_BKPRST_Msk /*!< Backup interface reset */
+#define RCC_APB1RSTR_PWRRST_Pos (28U)
+#define RCC_APB1RSTR_PWRRST_Msk (0x1U << RCC_APB1RSTR_PWRRST_Pos) /*!< 0x10000000 */
+#define RCC_APB1RSTR_PWRRST RCC_APB1RSTR_PWRRST_Msk /*!< Power interface reset */
+
+#define RCC_APB1RSTR_TIM4RST_Pos (2U)
+#define RCC_APB1RSTR_TIM4RST_Msk (0x1U << RCC_APB1RSTR_TIM4RST_Pos) /*!< 0x00000004 */
+#define RCC_APB1RSTR_TIM4RST RCC_APB1RSTR_TIM4RST_Msk /*!< Timer 4 reset */
+#define RCC_APB1RSTR_SPI2RST_Pos (14U)
+#define RCC_APB1RSTR_SPI2RST_Msk (0x1U << RCC_APB1RSTR_SPI2RST_Pos) /*!< 0x00004000 */
+#define RCC_APB1RSTR_SPI2RST RCC_APB1RSTR_SPI2RST_Msk /*!< SPI 2 reset */
+#define RCC_APB1RSTR_USART3RST_Pos (18U)
+#define RCC_APB1RSTR_USART3RST_Msk (0x1U << RCC_APB1RSTR_USART3RST_Pos) /*!< 0x00040000 */
+#define RCC_APB1RSTR_USART3RST RCC_APB1RSTR_USART3RST_Msk /*!< USART 3 reset */
+#define RCC_APB1RSTR_I2C2RST_Pos (22U)
+#define RCC_APB1RSTR_I2C2RST_Msk (0x1U << RCC_APB1RSTR_I2C2RST_Pos) /*!< 0x00400000 */
+#define RCC_APB1RSTR_I2C2RST RCC_APB1RSTR_I2C2RST_Msk /*!< I2C 2 reset */
+
+
+
+#define RCC_APB1RSTR_TIM6RST_Pos (4U)
+#define RCC_APB1RSTR_TIM6RST_Msk (0x1U << RCC_APB1RSTR_TIM6RST_Pos) /*!< 0x00000010 */
+#define RCC_APB1RSTR_TIM6RST RCC_APB1RSTR_TIM6RST_Msk /*!< Timer 6 reset */
+#define RCC_APB1RSTR_TIM7RST_Pos (5U)
+#define RCC_APB1RSTR_TIM7RST_Msk (0x1U << RCC_APB1RSTR_TIM7RST_Pos) /*!< 0x00000020 */
+#define RCC_APB1RSTR_TIM7RST RCC_APB1RSTR_TIM7RST_Msk /*!< Timer 7 reset */
+#define RCC_APB1RSTR_CECRST_Pos (30U)
+#define RCC_APB1RSTR_CECRST_Msk (0x1U << RCC_APB1RSTR_CECRST_Pos) /*!< 0x40000000 */
+#define RCC_APB1RSTR_CECRST RCC_APB1RSTR_CECRST_Msk /*!< CEC interface reset */
+
+
+
+#define RCC_APB1RSTR_DACRST_Pos (29U)
+#define RCC_APB1RSTR_DACRST_Msk (0x1U << RCC_APB1RSTR_DACRST_Pos) /*!< 0x20000000 */
+#define RCC_APB1RSTR_DACRST RCC_APB1RSTR_DACRST_Msk /*!< DAC interface reset */
+
+/****************** Bit definition for RCC_AHBENR register ******************/
+#define RCC_AHBENR_DMA1EN_Pos (0U)
+#define RCC_AHBENR_DMA1EN_Msk (0x1U << RCC_AHBENR_DMA1EN_Pos) /*!< 0x00000001 */
+#define RCC_AHBENR_DMA1EN RCC_AHBENR_DMA1EN_Msk /*!< DMA1 clock enable */
+#define RCC_AHBENR_SRAMEN_Pos (2U)
+#define RCC_AHBENR_SRAMEN_Msk (0x1U << RCC_AHBENR_SRAMEN_Pos) /*!< 0x00000004 */
+#define RCC_AHBENR_SRAMEN RCC_AHBENR_SRAMEN_Msk /*!< SRAM interface clock enable */
+#define RCC_AHBENR_FLITFEN_Pos (4U)
+#define RCC_AHBENR_FLITFEN_Msk (0x1U << RCC_AHBENR_FLITFEN_Pos) /*!< 0x00000010 */
+#define RCC_AHBENR_FLITFEN RCC_AHBENR_FLITFEN_Msk /*!< FLITF clock enable */
+#define RCC_AHBENR_CRCEN_Pos (6U)
+#define RCC_AHBENR_CRCEN_Msk (0x1U << RCC_AHBENR_CRCEN_Pos) /*!< 0x00000040 */
+#define RCC_AHBENR_CRCEN RCC_AHBENR_CRCEN_Msk /*!< CRC clock enable */
+
+
+
+
+/****************** Bit definition for RCC_APB2ENR register *****************/
+#define RCC_APB2ENR_AFIOEN_Pos (0U)
+#define RCC_APB2ENR_AFIOEN_Msk (0x1U << RCC_APB2ENR_AFIOEN_Pos) /*!< 0x00000001 */
+#define RCC_APB2ENR_AFIOEN RCC_APB2ENR_AFIOEN_Msk /*!< Alternate Function I/O clock enable */
+#define RCC_APB2ENR_IOPAEN_Pos (2U)
+#define RCC_APB2ENR_IOPAEN_Msk (0x1U << RCC_APB2ENR_IOPAEN_Pos) /*!< 0x00000004 */
+#define RCC_APB2ENR_IOPAEN RCC_APB2ENR_IOPAEN_Msk /*!< I/O port A clock enable */
+#define RCC_APB2ENR_IOPBEN_Pos (3U)
+#define RCC_APB2ENR_IOPBEN_Msk (0x1U << RCC_APB2ENR_IOPBEN_Pos) /*!< 0x00000008 */
+#define RCC_APB2ENR_IOPBEN RCC_APB2ENR_IOPBEN_Msk /*!< I/O port B clock enable */
+#define RCC_APB2ENR_IOPCEN_Pos (4U)
+#define RCC_APB2ENR_IOPCEN_Msk (0x1U << RCC_APB2ENR_IOPCEN_Pos) /*!< 0x00000010 */
+#define RCC_APB2ENR_IOPCEN RCC_APB2ENR_IOPCEN_Msk /*!< I/O port C clock enable */
+#define RCC_APB2ENR_IOPDEN_Pos (5U)
+#define RCC_APB2ENR_IOPDEN_Msk (0x1U << RCC_APB2ENR_IOPDEN_Pos) /*!< 0x00000020 */
+#define RCC_APB2ENR_IOPDEN RCC_APB2ENR_IOPDEN_Msk /*!< I/O port D clock enable */
+#define RCC_APB2ENR_ADC1EN_Pos (9U)
+#define RCC_APB2ENR_ADC1EN_Msk (0x1U << RCC_APB2ENR_ADC1EN_Pos) /*!< 0x00000200 */
+#define RCC_APB2ENR_ADC1EN RCC_APB2ENR_ADC1EN_Msk /*!< ADC 1 interface clock enable */
+
+
+#define RCC_APB2ENR_TIM1EN_Pos (11U)
+#define RCC_APB2ENR_TIM1EN_Msk (0x1U << RCC_APB2ENR_TIM1EN_Pos) /*!< 0x00000800 */
+#define RCC_APB2ENR_TIM1EN RCC_APB2ENR_TIM1EN_Msk /*!< TIM1 Timer clock enable */
+#define RCC_APB2ENR_SPI1EN_Pos (12U)
+#define RCC_APB2ENR_SPI1EN_Msk (0x1U << RCC_APB2ENR_SPI1EN_Pos) /*!< 0x00001000 */
+#define RCC_APB2ENR_SPI1EN RCC_APB2ENR_SPI1EN_Msk /*!< SPI 1 clock enable */
+#define RCC_APB2ENR_USART1EN_Pos (14U)
+#define RCC_APB2ENR_USART1EN_Msk (0x1U << RCC_APB2ENR_USART1EN_Pos) /*!< 0x00004000 */
+#define RCC_APB2ENR_USART1EN RCC_APB2ENR_USART1EN_Msk /*!< USART1 clock enable */
+
+#define RCC_APB2ENR_TIM15EN_Pos (16U)
+#define RCC_APB2ENR_TIM15EN_Msk (0x1U << RCC_APB2ENR_TIM15EN_Pos) /*!< 0x00010000 */
+#define RCC_APB2ENR_TIM15EN RCC_APB2ENR_TIM15EN_Msk /*!< TIM15 Timer clock enable */
+#define RCC_APB2ENR_TIM16EN_Pos (17U)
+#define RCC_APB2ENR_TIM16EN_Msk (0x1U << RCC_APB2ENR_TIM16EN_Pos) /*!< 0x00020000 */
+#define RCC_APB2ENR_TIM16EN RCC_APB2ENR_TIM16EN_Msk /*!< TIM16 Timer clock enable */
+#define RCC_APB2ENR_TIM17EN_Pos (18U)
+#define RCC_APB2ENR_TIM17EN_Msk (0x1U << RCC_APB2ENR_TIM17EN_Pos) /*!< 0x00040000 */
+#define RCC_APB2ENR_TIM17EN RCC_APB2ENR_TIM17EN_Msk /*!< TIM17 Timer clock enable */
+
+#define RCC_APB2ENR_IOPEEN_Pos (6U)
+#define RCC_APB2ENR_IOPEEN_Msk (0x1U << RCC_APB2ENR_IOPEEN_Pos) /*!< 0x00000040 */
+#define RCC_APB2ENR_IOPEEN RCC_APB2ENR_IOPEEN_Msk /*!< I/O port E clock enable */
+
+
+
+
+/***************** Bit definition for RCC_APB1ENR register ******************/
+#define RCC_APB1ENR_TIM2EN_Pos (0U)
+#define RCC_APB1ENR_TIM2EN_Msk (0x1U << RCC_APB1ENR_TIM2EN_Pos) /*!< 0x00000001 */
+#define RCC_APB1ENR_TIM2EN RCC_APB1ENR_TIM2EN_Msk /*!< Timer 2 clock enabled*/
+#define RCC_APB1ENR_TIM3EN_Pos (1U)
+#define RCC_APB1ENR_TIM3EN_Msk (0x1U << RCC_APB1ENR_TIM3EN_Pos) /*!< 0x00000002 */
+#define RCC_APB1ENR_TIM3EN RCC_APB1ENR_TIM3EN_Msk /*!< Timer 3 clock enable */
+#define RCC_APB1ENR_WWDGEN_Pos (11U)
+#define RCC_APB1ENR_WWDGEN_Msk (0x1U << RCC_APB1ENR_WWDGEN_Pos) /*!< 0x00000800 */
+#define RCC_APB1ENR_WWDGEN RCC_APB1ENR_WWDGEN_Msk /*!< Window Watchdog clock enable */
+#define RCC_APB1ENR_USART2EN_Pos (17U)
+#define RCC_APB1ENR_USART2EN_Msk (0x1U << RCC_APB1ENR_USART2EN_Pos) /*!< 0x00020000 */
+#define RCC_APB1ENR_USART2EN RCC_APB1ENR_USART2EN_Msk /*!< USART 2 clock enable */
+#define RCC_APB1ENR_I2C1EN_Pos (21U)
+#define RCC_APB1ENR_I2C1EN_Msk (0x1U << RCC_APB1ENR_I2C1EN_Pos) /*!< 0x00200000 */
+#define RCC_APB1ENR_I2C1EN RCC_APB1ENR_I2C1EN_Msk /*!< I2C 1 clock enable */
+
+
+#define RCC_APB1ENR_BKPEN_Pos (27U)
+#define RCC_APB1ENR_BKPEN_Msk (0x1U << RCC_APB1ENR_BKPEN_Pos) /*!< 0x08000000 */
+#define RCC_APB1ENR_BKPEN RCC_APB1ENR_BKPEN_Msk /*!< Backup interface clock enable */
+#define RCC_APB1ENR_PWREN_Pos (28U)
+#define RCC_APB1ENR_PWREN_Msk (0x1U << RCC_APB1ENR_PWREN_Pos) /*!< 0x10000000 */
+#define RCC_APB1ENR_PWREN RCC_APB1ENR_PWREN_Msk /*!< Power interface clock enable */
+
+#define RCC_APB1ENR_TIM4EN_Pos (2U)
+#define RCC_APB1ENR_TIM4EN_Msk (0x1U << RCC_APB1ENR_TIM4EN_Pos) /*!< 0x00000004 */
+#define RCC_APB1ENR_TIM4EN RCC_APB1ENR_TIM4EN_Msk /*!< Timer 4 clock enable */
+#define RCC_APB1ENR_SPI2EN_Pos (14U)
+#define RCC_APB1ENR_SPI2EN_Msk (0x1U << RCC_APB1ENR_SPI2EN_Pos) /*!< 0x00004000 */
+#define RCC_APB1ENR_SPI2EN RCC_APB1ENR_SPI2EN_Msk /*!< SPI 2 clock enable */
+#define RCC_APB1ENR_USART3EN_Pos (18U)
+#define RCC_APB1ENR_USART3EN_Msk (0x1U << RCC_APB1ENR_USART3EN_Pos) /*!< 0x00040000 */
+#define RCC_APB1ENR_USART3EN RCC_APB1ENR_USART3EN_Msk /*!< USART 3 clock enable */
+#define RCC_APB1ENR_I2C2EN_Pos (22U)
+#define RCC_APB1ENR_I2C2EN_Msk (0x1U << RCC_APB1ENR_I2C2EN_Pos) /*!< 0x00400000 */
+#define RCC_APB1ENR_I2C2EN RCC_APB1ENR_I2C2EN_Msk /*!< I2C 2 clock enable */
+
+
+
+#define RCC_APB1ENR_TIM6EN_Pos (4U)
+#define RCC_APB1ENR_TIM6EN_Msk (0x1U << RCC_APB1ENR_TIM6EN_Pos) /*!< 0x00000010 */
+#define RCC_APB1ENR_TIM6EN RCC_APB1ENR_TIM6EN_Msk /*!< Timer 6 clock enable */
+#define RCC_APB1ENR_TIM7EN_Pos (5U)
+#define RCC_APB1ENR_TIM7EN_Msk (0x1U << RCC_APB1ENR_TIM7EN_Pos) /*!< 0x00000020 */
+#define RCC_APB1ENR_TIM7EN RCC_APB1ENR_TIM7EN_Msk /*!< Timer 7 clock enable */
+#define RCC_APB1ENR_CECEN_Pos (30U)
+#define RCC_APB1ENR_CECEN_Msk (0x1U << RCC_APB1ENR_CECEN_Pos) /*!< 0x40000000 */
+#define RCC_APB1ENR_CECEN RCC_APB1ENR_CECEN_Msk /*!< CEC interface clock enable */
+
+
+
+#define RCC_APB1ENR_DACEN_Pos (29U)
+#define RCC_APB1ENR_DACEN_Msk (0x1U << RCC_APB1ENR_DACEN_Pos) /*!< 0x20000000 */
+#define RCC_APB1ENR_DACEN RCC_APB1ENR_DACEN_Msk /*!< DAC interface clock enable */
+
+/******************* Bit definition for RCC_BDCR register *******************/
+#define RCC_BDCR_LSEON_Pos (0U)
+#define RCC_BDCR_LSEON_Msk (0x1U << RCC_BDCR_LSEON_Pos) /*!< 0x00000001 */
+#define RCC_BDCR_LSEON RCC_BDCR_LSEON_Msk /*!< External Low Speed oscillator enable */
+#define RCC_BDCR_LSERDY_Pos (1U)
+#define RCC_BDCR_LSERDY_Msk (0x1U << RCC_BDCR_LSERDY_Pos) /*!< 0x00000002 */
+#define RCC_BDCR_LSERDY RCC_BDCR_LSERDY_Msk /*!< External Low Speed oscillator Ready */
+#define RCC_BDCR_LSEBYP_Pos (2U)
+#define RCC_BDCR_LSEBYP_Msk (0x1U << RCC_BDCR_LSEBYP_Pos) /*!< 0x00000004 */
+#define RCC_BDCR_LSEBYP RCC_BDCR_LSEBYP_Msk /*!< External Low Speed oscillator Bypass */
+
+#define RCC_BDCR_RTCSEL_Pos (8U)
+#define RCC_BDCR_RTCSEL_Msk (0x3U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000300 */
+#define RCC_BDCR_RTCSEL RCC_BDCR_RTCSEL_Msk /*!< RTCSEL[1:0] bits (RTC clock source selection) */
+#define RCC_BDCR_RTCSEL_0 (0x1U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000100 */
+#define RCC_BDCR_RTCSEL_1 (0x2U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000200 */
+
+/*!< RTC congiguration */
+#define RCC_BDCR_RTCSEL_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */
+#define RCC_BDCR_RTCSEL_LSE ((uint32_t)0x00000100) /*!< LSE oscillator clock used as RTC clock */
+#define RCC_BDCR_RTCSEL_LSI ((uint32_t)0x00000200) /*!< LSI oscillator clock used as RTC clock */
+#define RCC_BDCR_RTCSEL_HSE ((uint32_t)0x00000300) /*!< HSE oscillator clock divided by 128 used as RTC clock */
+
+#define RCC_BDCR_RTCEN_Pos (15U)
+#define RCC_BDCR_RTCEN_Msk (0x1U << RCC_BDCR_RTCEN_Pos) /*!< 0x00008000 */
+#define RCC_BDCR_RTCEN RCC_BDCR_RTCEN_Msk /*!< RTC clock enable */
+#define RCC_BDCR_BDRST_Pos (16U)
+#define RCC_BDCR_BDRST_Msk (0x1U << RCC_BDCR_BDRST_Pos) /*!< 0x00010000 */
+#define RCC_BDCR_BDRST RCC_BDCR_BDRST_Msk /*!< Backup domain software reset */
+
+/******************* Bit definition for RCC_CSR register ********************/
+#define RCC_CSR_LSION_Pos (0U)
+#define RCC_CSR_LSION_Msk (0x1U << RCC_CSR_LSION_Pos) /*!< 0x00000001 */
+#define RCC_CSR_LSION RCC_CSR_LSION_Msk /*!< Internal Low Speed oscillator enable */
+#define RCC_CSR_LSIRDY_Pos (1U)
+#define RCC_CSR_LSIRDY_Msk (0x1U << RCC_CSR_LSIRDY_Pos) /*!< 0x00000002 */
+#define RCC_CSR_LSIRDY RCC_CSR_LSIRDY_Msk /*!< Internal Low Speed oscillator Ready */
+#define RCC_CSR_RMVF_Pos (24U)
+#define RCC_CSR_RMVF_Msk (0x1U << RCC_CSR_RMVF_Pos) /*!< 0x01000000 */
+#define RCC_CSR_RMVF RCC_CSR_RMVF_Msk /*!< Remove reset flag */
+#define RCC_CSR_PINRSTF_Pos (26U)
+#define RCC_CSR_PINRSTF_Msk (0x1U << RCC_CSR_PINRSTF_Pos) /*!< 0x04000000 */
+#define RCC_CSR_PINRSTF RCC_CSR_PINRSTF_Msk /*!< PIN reset flag */
+#define RCC_CSR_PORRSTF_Pos (27U)
+#define RCC_CSR_PORRSTF_Msk (0x1U << RCC_CSR_PORRSTF_Pos) /*!< 0x08000000 */
+#define RCC_CSR_PORRSTF RCC_CSR_PORRSTF_Msk /*!< POR/PDR reset flag */
+#define RCC_CSR_SFTRSTF_Pos (28U)
+#define RCC_CSR_SFTRSTF_Msk (0x1U << RCC_CSR_SFTRSTF_Pos) /*!< 0x10000000 */
+#define RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF_Msk /*!< Software Reset flag */
+#define RCC_CSR_IWDGRSTF_Pos (29U)
+#define RCC_CSR_IWDGRSTF_Msk (0x1U << RCC_CSR_IWDGRSTF_Pos) /*!< 0x20000000 */
+#define RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF_Msk /*!< Independent Watchdog reset flag */
+#define RCC_CSR_WWDGRSTF_Pos (30U)
+#define RCC_CSR_WWDGRSTF_Msk (0x1U << RCC_CSR_WWDGRSTF_Pos) /*!< 0x40000000 */
+#define RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF_Msk /*!< Window watchdog reset flag */
+#define RCC_CSR_LPWRRSTF_Pos (31U)
+#define RCC_CSR_LPWRRSTF_Msk (0x1U << RCC_CSR_LPWRRSTF_Pos) /*!< 0x80000000 */
+#define RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF_Msk /*!< Low-Power reset flag */
+
+
+/******************* Bit definition for RCC_CFGR2 register ******************/
+/*!< PREDIV1 configuration */
+#define RCC_CFGR2_PREDIV1_Pos (0U)
+#define RCC_CFGR2_PREDIV1_Msk (0xFU << RCC_CFGR2_PREDIV1_Pos) /*!< 0x0000000F */
+#define RCC_CFGR2_PREDIV1 RCC_CFGR2_PREDIV1_Msk /*!< PREDIV1[3:0] bits */
+#define RCC_CFGR2_PREDIV1_0 (0x1U << RCC_CFGR2_PREDIV1_Pos) /*!< 0x00000001 */
+#define RCC_CFGR2_PREDIV1_1 (0x2U << RCC_CFGR2_PREDIV1_Pos) /*!< 0x00000002 */
+#define RCC_CFGR2_PREDIV1_2 (0x4U << RCC_CFGR2_PREDIV1_Pos) /*!< 0x00000004 */
+#define RCC_CFGR2_PREDIV1_3 (0x8U << RCC_CFGR2_PREDIV1_Pos) /*!< 0x00000008 */
+
+#define RCC_CFGR2_PREDIV1_DIV1 ((uint32_t)0x00000000) /*!< PREDIV1 input clock not divided */
+#define RCC_CFGR2_PREDIV1_DIV2_Pos (0U)
+#define RCC_CFGR2_PREDIV1_DIV2_Msk (0x1U << RCC_CFGR2_PREDIV1_DIV2_Pos) /*!< 0x00000001 */
+#define RCC_CFGR2_PREDIV1_DIV2 RCC_CFGR2_PREDIV1_DIV2_Msk /*!< PREDIV1 input clock divided by 2 */
+#define RCC_CFGR2_PREDIV1_DIV3_Pos (1U)
+#define RCC_CFGR2_PREDIV1_DIV3_Msk (0x1U << RCC_CFGR2_PREDIV1_DIV3_Pos) /*!< 0x00000002 */
+#define RCC_CFGR2_PREDIV1_DIV3 RCC_CFGR2_PREDIV1_DIV3_Msk /*!< PREDIV1 input clock divided by 3 */
+#define RCC_CFGR2_PREDIV1_DIV4_Pos (0U)
+#define RCC_CFGR2_PREDIV1_DIV4_Msk (0x3U << RCC_CFGR2_PREDIV1_DIV4_Pos) /*!< 0x00000003 */
+#define RCC_CFGR2_PREDIV1_DIV4 RCC_CFGR2_PREDIV1_DIV4_Msk /*!< PREDIV1 input clock divided by 4 */
+#define RCC_CFGR2_PREDIV1_DIV5_Pos (2U)
+#define RCC_CFGR2_PREDIV1_DIV5_Msk (0x1U << RCC_CFGR2_PREDIV1_DIV5_Pos) /*!< 0x00000004 */
+#define RCC_CFGR2_PREDIV1_DIV5 RCC_CFGR2_PREDIV1_DIV5_Msk /*!< PREDIV1 input clock divided by 5 */
+#define RCC_CFGR2_PREDIV1_DIV6_Pos (0U)
+#define RCC_CFGR2_PREDIV1_DIV6_Msk (0x5U << RCC_CFGR2_PREDIV1_DIV6_Pos) /*!< 0x00000005 */
+#define RCC_CFGR2_PREDIV1_DIV6 RCC_CFGR2_PREDIV1_DIV6_Msk /*!< PREDIV1 input clock divided by 6 */
+#define RCC_CFGR2_PREDIV1_DIV7_Pos (1U)
+#define RCC_CFGR2_PREDIV1_DIV7_Msk (0x3U << RCC_CFGR2_PREDIV1_DIV7_Pos) /*!< 0x00000006 */
+#define RCC_CFGR2_PREDIV1_DIV7 RCC_CFGR2_PREDIV1_DIV7_Msk /*!< PREDIV1 input clock divided by 7 */
+#define RCC_CFGR2_PREDIV1_DIV8_Pos (0U)
+#define RCC_CFGR2_PREDIV1_DIV8_Msk (0x7U << RCC_CFGR2_PREDIV1_DIV8_Pos) /*!< 0x00000007 */
+#define RCC_CFGR2_PREDIV1_DIV8 RCC_CFGR2_PREDIV1_DIV8_Msk /*!< PREDIV1 input clock divided by 8 */
+#define RCC_CFGR2_PREDIV1_DIV9_Pos (3U)
+#define RCC_CFGR2_PREDIV1_DIV9_Msk (0x1U << RCC_CFGR2_PREDIV1_DIV9_Pos) /*!< 0x00000008 */
+#define RCC_CFGR2_PREDIV1_DIV9 RCC_CFGR2_PREDIV1_DIV9_Msk /*!< PREDIV1 input clock divided by 9 */
+#define RCC_CFGR2_PREDIV1_DIV10_Pos (0U)
+#define RCC_CFGR2_PREDIV1_DIV10_Msk (0x9U << RCC_CFGR2_PREDIV1_DIV10_Pos) /*!< 0x00000009 */
+#define RCC_CFGR2_PREDIV1_DIV10 RCC_CFGR2_PREDIV1_DIV10_Msk /*!< PREDIV1 input clock divided by 10 */
+#define RCC_CFGR2_PREDIV1_DIV11_Pos (1U)
+#define RCC_CFGR2_PREDIV1_DIV11_Msk (0x5U << RCC_CFGR2_PREDIV1_DIV11_Pos) /*!< 0x0000000A */
+#define RCC_CFGR2_PREDIV1_DIV11 RCC_CFGR2_PREDIV1_DIV11_Msk /*!< PREDIV1 input clock divided by 11 */
+#define RCC_CFGR2_PREDIV1_DIV12_Pos (0U)
+#define RCC_CFGR2_PREDIV1_DIV12_Msk (0xBU << RCC_CFGR2_PREDIV1_DIV12_Pos) /*!< 0x0000000B */
+#define RCC_CFGR2_PREDIV1_DIV12 RCC_CFGR2_PREDIV1_DIV12_Msk /*!< PREDIV1 input clock divided by 12 */
+#define RCC_CFGR2_PREDIV1_DIV13_Pos (2U)
+#define RCC_CFGR2_PREDIV1_DIV13_Msk (0x3U << RCC_CFGR2_PREDIV1_DIV13_Pos) /*!< 0x0000000C */
+#define RCC_CFGR2_PREDIV1_DIV13 RCC_CFGR2_PREDIV1_DIV13_Msk /*!< PREDIV1 input clock divided by 13 */
+#define RCC_CFGR2_PREDIV1_DIV14_Pos (0U)
+#define RCC_CFGR2_PREDIV1_DIV14_Msk (0xDU << RCC_CFGR2_PREDIV1_DIV14_Pos) /*!< 0x0000000D */
+#define RCC_CFGR2_PREDIV1_DIV14 RCC_CFGR2_PREDIV1_DIV14_Msk /*!< PREDIV1 input clock divided by 14 */
+#define RCC_CFGR2_PREDIV1_DIV15_Pos (1U)
+#define RCC_CFGR2_PREDIV1_DIV15_Msk (0x7U << RCC_CFGR2_PREDIV1_DIV15_Pos) /*!< 0x0000000E */
+#define RCC_CFGR2_PREDIV1_DIV15 RCC_CFGR2_PREDIV1_DIV15_Msk /*!< PREDIV1 input clock divided by 15 */
+#define RCC_CFGR2_PREDIV1_DIV16_Pos (0U)
+#define RCC_CFGR2_PREDIV1_DIV16_Msk (0xFU << RCC_CFGR2_PREDIV1_DIV16_Pos) /*!< 0x0000000F */
+#define RCC_CFGR2_PREDIV1_DIV16 RCC_CFGR2_PREDIV1_DIV16_Msk /*!< PREDIV1 input clock divided by 16 */
+
+/******************************************************************************/
+/* */
+/* General Purpose and Alternate Function I/O */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for GPIO_CRL register *******************/
+#define GPIO_CRL_MODE_Pos (0U)
+#define GPIO_CRL_MODE_Msk (0x33333333U << GPIO_CRL_MODE_Pos) /*!< 0x33333333 */
+#define GPIO_CRL_MODE GPIO_CRL_MODE_Msk /*!< Port x mode bits */
+
+#define GPIO_CRL_MODE0_Pos (0U)
+#define GPIO_CRL_MODE0_Msk (0x3U << GPIO_CRL_MODE0_Pos) /*!< 0x00000003 */
+#define GPIO_CRL_MODE0 GPIO_CRL_MODE0_Msk /*!< MODE0[1:0] bits (Port x mode bits, pin 0) */
+#define GPIO_CRL_MODE0_0 (0x1U << GPIO_CRL_MODE0_Pos) /*!< 0x00000001 */
+#define GPIO_CRL_MODE0_1 (0x2U << GPIO_CRL_MODE0_Pos) /*!< 0x00000002 */
+
+#define GPIO_CRL_MODE1_Pos (4U)
+#define GPIO_CRL_MODE1_Msk (0x3U << GPIO_CRL_MODE1_Pos) /*!< 0x00000030 */
+#define GPIO_CRL_MODE1 GPIO_CRL_MODE1_Msk /*!< MODE1[1:0] bits (Port x mode bits, pin 1) */
+#define GPIO_CRL_MODE1_0 (0x1U << GPIO_CRL_MODE1_Pos) /*!< 0x00000010 */
+#define GPIO_CRL_MODE1_1 (0x2U << GPIO_CRL_MODE1_Pos) /*!< 0x00000020 */
+
+#define GPIO_CRL_MODE2_Pos (8U)
+#define GPIO_CRL_MODE2_Msk (0x3U << GPIO_CRL_MODE2_Pos) /*!< 0x00000300 */
+#define GPIO_CRL_MODE2 GPIO_CRL_MODE2_Msk /*!< MODE2[1:0] bits (Port x mode bits, pin 2) */
+#define GPIO_CRL_MODE2_0 (0x1U << GPIO_CRL_MODE2_Pos) /*!< 0x00000100 */
+#define GPIO_CRL_MODE2_1 (0x2U << GPIO_CRL_MODE2_Pos) /*!< 0x00000200 */
+
+#define GPIO_CRL_MODE3_Pos (12U)
+#define GPIO_CRL_MODE3_Msk (0x3U << GPIO_CRL_MODE3_Pos) /*!< 0x00003000 */
+#define GPIO_CRL_MODE3 GPIO_CRL_MODE3_Msk /*!< MODE3[1:0] bits (Port x mode bits, pin 3) */
+#define GPIO_CRL_MODE3_0 (0x1U << GPIO_CRL_MODE3_Pos) /*!< 0x00001000 */
+#define GPIO_CRL_MODE3_1 (0x2U << GPIO_CRL_MODE3_Pos) /*!< 0x00002000 */
+
+#define GPIO_CRL_MODE4_Pos (16U)
+#define GPIO_CRL_MODE4_Msk (0x3U << GPIO_CRL_MODE4_Pos) /*!< 0x00030000 */
+#define GPIO_CRL_MODE4 GPIO_CRL_MODE4_Msk /*!< MODE4[1:0] bits (Port x mode bits, pin 4) */
+#define GPIO_CRL_MODE4_0 (0x1U << GPIO_CRL_MODE4_Pos) /*!< 0x00010000 */
+#define GPIO_CRL_MODE4_1 (0x2U << GPIO_CRL_MODE4_Pos) /*!< 0x00020000 */
+
+#define GPIO_CRL_MODE5_Pos (20U)
+#define GPIO_CRL_MODE5_Msk (0x3U << GPIO_CRL_MODE5_Pos) /*!< 0x00300000 */
+#define GPIO_CRL_MODE5 GPIO_CRL_MODE5_Msk /*!< MODE5[1:0] bits (Port x mode bits, pin 5) */
+#define GPIO_CRL_MODE5_0 (0x1U << GPIO_CRL_MODE5_Pos) /*!< 0x00100000 */
+#define GPIO_CRL_MODE5_1 (0x2U << GPIO_CRL_MODE5_Pos) /*!< 0x00200000 */
+
+#define GPIO_CRL_MODE6_Pos (24U)
+#define GPIO_CRL_MODE6_Msk (0x3U << GPIO_CRL_MODE6_Pos) /*!< 0x03000000 */
+#define GPIO_CRL_MODE6 GPIO_CRL_MODE6_Msk /*!< MODE6[1:0] bits (Port x mode bits, pin 6) */
+#define GPIO_CRL_MODE6_0 (0x1U << GPIO_CRL_MODE6_Pos) /*!< 0x01000000 */
+#define GPIO_CRL_MODE6_1 (0x2U << GPIO_CRL_MODE6_Pos) /*!< 0x02000000 */
+
+#define GPIO_CRL_MODE7_Pos (28U)
+#define GPIO_CRL_MODE7_Msk (0x3U << GPIO_CRL_MODE7_Pos) /*!< 0x30000000 */
+#define GPIO_CRL_MODE7 GPIO_CRL_MODE7_Msk /*!< MODE7[1:0] bits (Port x mode bits, pin 7) */
+#define GPIO_CRL_MODE7_0 (0x1U << GPIO_CRL_MODE7_Pos) /*!< 0x10000000 */
+#define GPIO_CRL_MODE7_1 (0x2U << GPIO_CRL_MODE7_Pos) /*!< 0x20000000 */
+
+#define GPIO_CRL_CNF_Pos (2U)
+#define GPIO_CRL_CNF_Msk (0x33333333U << GPIO_CRL_CNF_Pos) /*!< 0xCCCCCCCC */
+#define GPIO_CRL_CNF GPIO_CRL_CNF_Msk /*!< Port x configuration bits */
+
+#define GPIO_CRL_CNF0_Pos (2U)
+#define GPIO_CRL_CNF0_Msk (0x3U << GPIO_CRL_CNF0_Pos) /*!< 0x0000000C */
+#define GPIO_CRL_CNF0 GPIO_CRL_CNF0_Msk /*!< CNF0[1:0] bits (Port x configuration bits, pin 0) */
+#define GPIO_CRL_CNF0_0 (0x1U << GPIO_CRL_CNF0_Pos) /*!< 0x00000004 */
+#define GPIO_CRL_CNF0_1 (0x2U << GPIO_CRL_CNF0_Pos) /*!< 0x00000008 */
+
+#define GPIO_CRL_CNF1_Pos (6U)
+#define GPIO_CRL_CNF1_Msk (0x3U << GPIO_CRL_CNF1_Pos) /*!< 0x000000C0 */
+#define GPIO_CRL_CNF1 GPIO_CRL_CNF1_Msk /*!< CNF1[1:0] bits (Port x configuration bits, pin 1) */
+#define GPIO_CRL_CNF1_0 (0x1U << GPIO_CRL_CNF1_Pos) /*!< 0x00000040 */
+#define GPIO_CRL_CNF1_1 (0x2U << GPIO_CRL_CNF1_Pos) /*!< 0x00000080 */
+
+#define GPIO_CRL_CNF2_Pos (10U)
+#define GPIO_CRL_CNF2_Msk (0x3U << GPIO_CRL_CNF2_Pos) /*!< 0x00000C00 */
+#define GPIO_CRL_CNF2 GPIO_CRL_CNF2_Msk /*!< CNF2[1:0] bits (Port x configuration bits, pin 2) */
+#define GPIO_CRL_CNF2_0 (0x1U << GPIO_CRL_CNF2_Pos) /*!< 0x00000400 */
+#define GPIO_CRL_CNF2_1 (0x2U << GPIO_CRL_CNF2_Pos) /*!< 0x00000800 */
+
+#define GPIO_CRL_CNF3_Pos (14U)
+#define GPIO_CRL_CNF3_Msk (0x3U << GPIO_CRL_CNF3_Pos) /*!< 0x0000C000 */
+#define GPIO_CRL_CNF3 GPIO_CRL_CNF3_Msk /*!< CNF3[1:0] bits (Port x configuration bits, pin 3) */
+#define GPIO_CRL_CNF3_0 (0x1U << GPIO_CRL_CNF3_Pos) /*!< 0x00004000 */
+#define GPIO_CRL_CNF3_1 (0x2U << GPIO_CRL_CNF3_Pos) /*!< 0x00008000 */
+
+#define GPIO_CRL_CNF4_Pos (18U)
+#define GPIO_CRL_CNF4_Msk (0x3U << GPIO_CRL_CNF4_Pos) /*!< 0x000C0000 */
+#define GPIO_CRL_CNF4 GPIO_CRL_CNF4_Msk /*!< CNF4[1:0] bits (Port x configuration bits, pin 4) */
+#define GPIO_CRL_CNF4_0 (0x1U << GPIO_CRL_CNF4_Pos) /*!< 0x00040000 */
+#define GPIO_CRL_CNF4_1 (0x2U << GPIO_CRL_CNF4_Pos) /*!< 0x00080000 */
+
+#define GPIO_CRL_CNF5_Pos (22U)
+#define GPIO_CRL_CNF5_Msk (0x3U << GPIO_CRL_CNF5_Pos) /*!< 0x00C00000 */
+#define GPIO_CRL_CNF5 GPIO_CRL_CNF5_Msk /*!< CNF5[1:0] bits (Port x configuration bits, pin 5) */
+#define GPIO_CRL_CNF5_0 (0x1U << GPIO_CRL_CNF5_Pos) /*!< 0x00400000 */
+#define GPIO_CRL_CNF5_1 (0x2U << GPIO_CRL_CNF5_Pos) /*!< 0x00800000 */
+
+#define GPIO_CRL_CNF6_Pos (26U)
+#define GPIO_CRL_CNF6_Msk (0x3U << GPIO_CRL_CNF6_Pos) /*!< 0x0C000000 */
+#define GPIO_CRL_CNF6 GPIO_CRL_CNF6_Msk /*!< CNF6[1:0] bits (Port x configuration bits, pin 6) */
+#define GPIO_CRL_CNF6_0 (0x1U << GPIO_CRL_CNF6_Pos) /*!< 0x04000000 */
+#define GPIO_CRL_CNF6_1 (0x2U << GPIO_CRL_CNF6_Pos) /*!< 0x08000000 */
+
+#define GPIO_CRL_CNF7_Pos (30U)
+#define GPIO_CRL_CNF7_Msk (0x3U << GPIO_CRL_CNF7_Pos) /*!< 0xC0000000 */
+#define GPIO_CRL_CNF7 GPIO_CRL_CNF7_Msk /*!< CNF7[1:0] bits (Port x configuration bits, pin 7) */
+#define GPIO_CRL_CNF7_0 (0x1U << GPIO_CRL_CNF7_Pos) /*!< 0x40000000 */
+#define GPIO_CRL_CNF7_1 (0x2U << GPIO_CRL_CNF7_Pos) /*!< 0x80000000 */
+
+/******************* Bit definition for GPIO_CRH register *******************/
+#define GPIO_CRH_MODE_Pos (0U)
+#define GPIO_CRH_MODE_Msk (0x33333333U << GPIO_CRH_MODE_Pos) /*!< 0x33333333 */
+#define GPIO_CRH_MODE GPIO_CRH_MODE_Msk /*!< Port x mode bits */
+
+#define GPIO_CRH_MODE8_Pos (0U)
+#define GPIO_CRH_MODE8_Msk (0x3U << GPIO_CRH_MODE8_Pos) /*!< 0x00000003 */
+#define GPIO_CRH_MODE8 GPIO_CRH_MODE8_Msk /*!< MODE8[1:0] bits (Port x mode bits, pin 8) */
+#define GPIO_CRH_MODE8_0 (0x1U << GPIO_CRH_MODE8_Pos) /*!< 0x00000001 */
+#define GPIO_CRH_MODE8_1 (0x2U << GPIO_CRH_MODE8_Pos) /*!< 0x00000002 */
+
+#define GPIO_CRH_MODE9_Pos (4U)
+#define GPIO_CRH_MODE9_Msk (0x3U << GPIO_CRH_MODE9_Pos) /*!< 0x00000030 */
+#define GPIO_CRH_MODE9 GPIO_CRH_MODE9_Msk /*!< MODE9[1:0] bits (Port x mode bits, pin 9) */
+#define GPIO_CRH_MODE9_0 (0x1U << GPIO_CRH_MODE9_Pos) /*!< 0x00000010 */
+#define GPIO_CRH_MODE9_1 (0x2U << GPIO_CRH_MODE9_Pos) /*!< 0x00000020 */
+
+#define GPIO_CRH_MODE10_Pos (8U)
+#define GPIO_CRH_MODE10_Msk (0x3U << GPIO_CRH_MODE10_Pos) /*!< 0x00000300 */
+#define GPIO_CRH_MODE10 GPIO_CRH_MODE10_Msk /*!< MODE10[1:0] bits (Port x mode bits, pin 10) */
+#define GPIO_CRH_MODE10_0 (0x1U << GPIO_CRH_MODE10_Pos) /*!< 0x00000100 */
+#define GPIO_CRH_MODE10_1 (0x2U << GPIO_CRH_MODE10_Pos) /*!< 0x00000200 */
+
+#define GPIO_CRH_MODE11_Pos (12U)
+#define GPIO_CRH_MODE11_Msk (0x3U << GPIO_CRH_MODE11_Pos) /*!< 0x00003000 */
+#define GPIO_CRH_MODE11 GPIO_CRH_MODE11_Msk /*!< MODE11[1:0] bits (Port x mode bits, pin 11) */
+#define GPIO_CRH_MODE11_0 (0x1U << GPIO_CRH_MODE11_Pos) /*!< 0x00001000 */
+#define GPIO_CRH_MODE11_1 (0x2U << GPIO_CRH_MODE11_Pos) /*!< 0x00002000 */
+
+#define GPIO_CRH_MODE12_Pos (16U)
+#define GPIO_CRH_MODE12_Msk (0x3U << GPIO_CRH_MODE12_Pos) /*!< 0x00030000 */
+#define GPIO_CRH_MODE12 GPIO_CRH_MODE12_Msk /*!< MODE12[1:0] bits (Port x mode bits, pin 12) */
+#define GPIO_CRH_MODE12_0 (0x1U << GPIO_CRH_MODE12_Pos) /*!< 0x00010000 */
+#define GPIO_CRH_MODE12_1 (0x2U << GPIO_CRH_MODE12_Pos) /*!< 0x00020000 */
+
+#define GPIO_CRH_MODE13_Pos (20U)
+#define GPIO_CRH_MODE13_Msk (0x3U << GPIO_CRH_MODE13_Pos) /*!< 0x00300000 */
+#define GPIO_CRH_MODE13 GPIO_CRH_MODE13_Msk /*!< MODE13[1:0] bits (Port x mode bits, pin 13) */
+#define GPIO_CRH_MODE13_0 (0x1U << GPIO_CRH_MODE13_Pos) /*!< 0x00100000 */
+#define GPIO_CRH_MODE13_1 (0x2U << GPIO_CRH_MODE13_Pos) /*!< 0x00200000 */
+
+#define GPIO_CRH_MODE14_Pos (24U)
+#define GPIO_CRH_MODE14_Msk (0x3U << GPIO_CRH_MODE14_Pos) /*!< 0x03000000 */
+#define GPIO_CRH_MODE14 GPIO_CRH_MODE14_Msk /*!< MODE14[1:0] bits (Port x mode bits, pin 14) */
+#define GPIO_CRH_MODE14_0 (0x1U << GPIO_CRH_MODE14_Pos) /*!< 0x01000000 */
+#define GPIO_CRH_MODE14_1 (0x2U << GPIO_CRH_MODE14_Pos) /*!< 0x02000000 */
+
+#define GPIO_CRH_MODE15_Pos (28U)
+#define GPIO_CRH_MODE15_Msk (0x3U << GPIO_CRH_MODE15_Pos) /*!< 0x30000000 */
+#define GPIO_CRH_MODE15 GPIO_CRH_MODE15_Msk /*!< MODE15[1:0] bits (Port x mode bits, pin 15) */
+#define GPIO_CRH_MODE15_0 (0x1U << GPIO_CRH_MODE15_Pos) /*!< 0x10000000 */
+#define GPIO_CRH_MODE15_1 (0x2U << GPIO_CRH_MODE15_Pos) /*!< 0x20000000 */
+
+#define GPIO_CRH_CNF_Pos (2U)
+#define GPIO_CRH_CNF_Msk (0x33333333U << GPIO_CRH_CNF_Pos) /*!< 0xCCCCCCCC */
+#define GPIO_CRH_CNF GPIO_CRH_CNF_Msk /*!< Port x configuration bits */
+
+#define GPIO_CRH_CNF8_Pos (2U)
+#define GPIO_CRH_CNF8_Msk (0x3U << GPIO_CRH_CNF8_Pos) /*!< 0x0000000C */
+#define GPIO_CRH_CNF8 GPIO_CRH_CNF8_Msk /*!< CNF8[1:0] bits (Port x configuration bits, pin 8) */
+#define GPIO_CRH_CNF8_0 (0x1U << GPIO_CRH_CNF8_Pos) /*!< 0x00000004 */
+#define GPIO_CRH_CNF8_1 (0x2U << GPIO_CRH_CNF8_Pos) /*!< 0x00000008 */
+
+#define GPIO_CRH_CNF9_Pos (6U)
+#define GPIO_CRH_CNF9_Msk (0x3U << GPIO_CRH_CNF9_Pos) /*!< 0x000000C0 */
+#define GPIO_CRH_CNF9 GPIO_CRH_CNF9_Msk /*!< CNF9[1:0] bits (Port x configuration bits, pin 9) */
+#define GPIO_CRH_CNF9_0 (0x1U << GPIO_CRH_CNF9_Pos) /*!< 0x00000040 */
+#define GPIO_CRH_CNF9_1 (0x2U << GPIO_CRH_CNF9_Pos) /*!< 0x00000080 */
+
+#define GPIO_CRH_CNF10_Pos (10U)
+#define GPIO_CRH_CNF10_Msk (0x3U << GPIO_CRH_CNF10_Pos) /*!< 0x00000C00 */
+#define GPIO_CRH_CNF10 GPIO_CRH_CNF10_Msk /*!< CNF10[1:0] bits (Port x configuration bits, pin 10) */
+#define GPIO_CRH_CNF10_0 (0x1U << GPIO_CRH_CNF10_Pos) /*!< 0x00000400 */
+#define GPIO_CRH_CNF10_1 (0x2U << GPIO_CRH_CNF10_Pos) /*!< 0x00000800 */
+
+#define GPIO_CRH_CNF11_Pos (14U)
+#define GPIO_CRH_CNF11_Msk (0x3U << GPIO_CRH_CNF11_Pos) /*!< 0x0000C000 */
+#define GPIO_CRH_CNF11 GPIO_CRH_CNF11_Msk /*!< CNF11[1:0] bits (Port x configuration bits, pin 11) */
+#define GPIO_CRH_CNF11_0 (0x1U << GPIO_CRH_CNF11_Pos) /*!< 0x00004000 */
+#define GPIO_CRH_CNF11_1 (0x2U << GPIO_CRH_CNF11_Pos) /*!< 0x00008000 */
+
+#define GPIO_CRH_CNF12_Pos (18U)
+#define GPIO_CRH_CNF12_Msk (0x3U << GPIO_CRH_CNF12_Pos) /*!< 0x000C0000 */
+#define GPIO_CRH_CNF12 GPIO_CRH_CNF12_Msk /*!< CNF12[1:0] bits (Port x configuration bits, pin 12) */
+#define GPIO_CRH_CNF12_0 (0x1U << GPIO_CRH_CNF12_Pos) /*!< 0x00040000 */
+#define GPIO_CRH_CNF12_1 (0x2U << GPIO_CRH_CNF12_Pos) /*!< 0x00080000 */
+
+#define GPIO_CRH_CNF13_Pos (22U)
+#define GPIO_CRH_CNF13_Msk (0x3U << GPIO_CRH_CNF13_Pos) /*!< 0x00C00000 */
+#define GPIO_CRH_CNF13 GPIO_CRH_CNF13_Msk /*!< CNF13[1:0] bits (Port x configuration bits, pin 13) */
+#define GPIO_CRH_CNF13_0 (0x1U << GPIO_CRH_CNF13_Pos) /*!< 0x00400000 */
+#define GPIO_CRH_CNF13_1 (0x2U << GPIO_CRH_CNF13_Pos) /*!< 0x00800000 */
+
+#define GPIO_CRH_CNF14_Pos (26U)
+#define GPIO_CRH_CNF14_Msk (0x3U << GPIO_CRH_CNF14_Pos) /*!< 0x0C000000 */
+#define GPIO_CRH_CNF14 GPIO_CRH_CNF14_Msk /*!< CNF14[1:0] bits (Port x configuration bits, pin 14) */
+#define GPIO_CRH_CNF14_0 (0x1U << GPIO_CRH_CNF14_Pos) /*!< 0x04000000 */
+#define GPIO_CRH_CNF14_1 (0x2U << GPIO_CRH_CNF14_Pos) /*!< 0x08000000 */
+
+#define GPIO_CRH_CNF15_Pos (30U)
+#define GPIO_CRH_CNF15_Msk (0x3U << GPIO_CRH_CNF15_Pos) /*!< 0xC0000000 */
+#define GPIO_CRH_CNF15 GPIO_CRH_CNF15_Msk /*!< CNF15[1:0] bits (Port x configuration bits, pin 15) */
+#define GPIO_CRH_CNF15_0 (0x1U << GPIO_CRH_CNF15_Pos) /*!< 0x40000000 */
+#define GPIO_CRH_CNF15_1 (0x2U << GPIO_CRH_CNF15_Pos) /*!< 0x80000000 */
+
+/*!<****************** Bit definition for GPIO_IDR register *******************/
+#define GPIO_IDR_IDR0_Pos (0U)
+#define GPIO_IDR_IDR0_Msk (0x1U << GPIO_IDR_IDR0_Pos) /*!< 0x00000001 */
+#define GPIO_IDR_IDR0 GPIO_IDR_IDR0_Msk /*!< Port input data, bit 0 */
+#define GPIO_IDR_IDR1_Pos (1U)
+#define GPIO_IDR_IDR1_Msk (0x1U << GPIO_IDR_IDR1_Pos) /*!< 0x00000002 */
+#define GPIO_IDR_IDR1 GPIO_IDR_IDR1_Msk /*!< Port input data, bit 1 */
+#define GPIO_IDR_IDR2_Pos (2U)
+#define GPIO_IDR_IDR2_Msk (0x1U << GPIO_IDR_IDR2_Pos) /*!< 0x00000004 */
+#define GPIO_IDR_IDR2 GPIO_IDR_IDR2_Msk /*!< Port input data, bit 2 */
+#define GPIO_IDR_IDR3_Pos (3U)
+#define GPIO_IDR_IDR3_Msk (0x1U << GPIO_IDR_IDR3_Pos) /*!< 0x00000008 */
+#define GPIO_IDR_IDR3 GPIO_IDR_IDR3_Msk /*!< Port input data, bit 3 */
+#define GPIO_IDR_IDR4_Pos (4U)
+#define GPIO_IDR_IDR4_Msk (0x1U << GPIO_IDR_IDR4_Pos) /*!< 0x00000010 */
+#define GPIO_IDR_IDR4 GPIO_IDR_IDR4_Msk /*!< Port input data, bit 4 */
+#define GPIO_IDR_IDR5_Pos (5U)
+#define GPIO_IDR_IDR5_Msk (0x1U << GPIO_IDR_IDR5_Pos) /*!< 0x00000020 */
+#define GPIO_IDR_IDR5 GPIO_IDR_IDR5_Msk /*!< Port input data, bit 5 */
+#define GPIO_IDR_IDR6_Pos (6U)
+#define GPIO_IDR_IDR6_Msk (0x1U << GPIO_IDR_IDR6_Pos) /*!< 0x00000040 */
+#define GPIO_IDR_IDR6 GPIO_IDR_IDR6_Msk /*!< Port input data, bit 6 */
+#define GPIO_IDR_IDR7_Pos (7U)
+#define GPIO_IDR_IDR7_Msk (0x1U << GPIO_IDR_IDR7_Pos) /*!< 0x00000080 */
+#define GPIO_IDR_IDR7 GPIO_IDR_IDR7_Msk /*!< Port input data, bit 7 */
+#define GPIO_IDR_IDR8_Pos (8U)
+#define GPIO_IDR_IDR8_Msk (0x1U << GPIO_IDR_IDR8_Pos) /*!< 0x00000100 */
+#define GPIO_IDR_IDR8 GPIO_IDR_IDR8_Msk /*!< Port input data, bit 8 */
+#define GPIO_IDR_IDR9_Pos (9U)
+#define GPIO_IDR_IDR9_Msk (0x1U << GPIO_IDR_IDR9_Pos) /*!< 0x00000200 */
+#define GPIO_IDR_IDR9 GPIO_IDR_IDR9_Msk /*!< Port input data, bit 9 */
+#define GPIO_IDR_IDR10_Pos (10U)
+#define GPIO_IDR_IDR10_Msk (0x1U << GPIO_IDR_IDR10_Pos) /*!< 0x00000400 */
+#define GPIO_IDR_IDR10 GPIO_IDR_IDR10_Msk /*!< Port input data, bit 10 */
+#define GPIO_IDR_IDR11_Pos (11U)
+#define GPIO_IDR_IDR11_Msk (0x1U << GPIO_IDR_IDR11_Pos) /*!< 0x00000800 */
+#define GPIO_IDR_IDR11 GPIO_IDR_IDR11_Msk /*!< Port input data, bit 11 */
+#define GPIO_IDR_IDR12_Pos (12U)
+#define GPIO_IDR_IDR12_Msk (0x1U << GPIO_IDR_IDR12_Pos) /*!< 0x00001000 */
+#define GPIO_IDR_IDR12 GPIO_IDR_IDR12_Msk /*!< Port input data, bit 12 */
+#define GPIO_IDR_IDR13_Pos (13U)
+#define GPIO_IDR_IDR13_Msk (0x1U << GPIO_IDR_IDR13_Pos) /*!< 0x00002000 */
+#define GPIO_IDR_IDR13 GPIO_IDR_IDR13_Msk /*!< Port input data, bit 13 */
+#define GPIO_IDR_IDR14_Pos (14U)
+#define GPIO_IDR_IDR14_Msk (0x1U << GPIO_IDR_IDR14_Pos) /*!< 0x00004000 */
+#define GPIO_IDR_IDR14 GPIO_IDR_IDR14_Msk /*!< Port input data, bit 14 */
+#define GPIO_IDR_IDR15_Pos (15U)
+#define GPIO_IDR_IDR15_Msk (0x1U << GPIO_IDR_IDR15_Pos) /*!< 0x00008000 */
+#define GPIO_IDR_IDR15 GPIO_IDR_IDR15_Msk /*!< Port input data, bit 15 */
+
+/******************* Bit definition for GPIO_ODR register *******************/
+#define GPIO_ODR_ODR0_Pos (0U)
+#define GPIO_ODR_ODR0_Msk (0x1U << GPIO_ODR_ODR0_Pos) /*!< 0x00000001 */
+#define GPIO_ODR_ODR0 GPIO_ODR_ODR0_Msk /*!< Port output data, bit 0 */
+#define GPIO_ODR_ODR1_Pos (1U)
+#define GPIO_ODR_ODR1_Msk (0x1U << GPIO_ODR_ODR1_Pos) /*!< 0x00000002 */
+#define GPIO_ODR_ODR1 GPIO_ODR_ODR1_Msk /*!< Port output data, bit 1 */
+#define GPIO_ODR_ODR2_Pos (2U)
+#define GPIO_ODR_ODR2_Msk (0x1U << GPIO_ODR_ODR2_Pos) /*!< 0x00000004 */
+#define GPIO_ODR_ODR2 GPIO_ODR_ODR2_Msk /*!< Port output data, bit 2 */
+#define GPIO_ODR_ODR3_Pos (3U)
+#define GPIO_ODR_ODR3_Msk (0x1U << GPIO_ODR_ODR3_Pos) /*!< 0x00000008 */
+#define GPIO_ODR_ODR3 GPIO_ODR_ODR3_Msk /*!< Port output data, bit 3 */
+#define GPIO_ODR_ODR4_Pos (4U)
+#define GPIO_ODR_ODR4_Msk (0x1U << GPIO_ODR_ODR4_Pos) /*!< 0x00000010 */
+#define GPIO_ODR_ODR4 GPIO_ODR_ODR4_Msk /*!< Port output data, bit 4 */
+#define GPIO_ODR_ODR5_Pos (5U)
+#define GPIO_ODR_ODR5_Msk (0x1U << GPIO_ODR_ODR5_Pos) /*!< 0x00000020 */
+#define GPIO_ODR_ODR5 GPIO_ODR_ODR5_Msk /*!< Port output data, bit 5 */
+#define GPIO_ODR_ODR6_Pos (6U)
+#define GPIO_ODR_ODR6_Msk (0x1U << GPIO_ODR_ODR6_Pos) /*!< 0x00000040 */
+#define GPIO_ODR_ODR6 GPIO_ODR_ODR6_Msk /*!< Port output data, bit 6 */
+#define GPIO_ODR_ODR7_Pos (7U)
+#define GPIO_ODR_ODR7_Msk (0x1U << GPIO_ODR_ODR7_Pos) /*!< 0x00000080 */
+#define GPIO_ODR_ODR7 GPIO_ODR_ODR7_Msk /*!< Port output data, bit 7 */
+#define GPIO_ODR_ODR8_Pos (8U)
+#define GPIO_ODR_ODR8_Msk (0x1U << GPIO_ODR_ODR8_Pos) /*!< 0x00000100 */
+#define GPIO_ODR_ODR8 GPIO_ODR_ODR8_Msk /*!< Port output data, bit 8 */
+#define GPIO_ODR_ODR9_Pos (9U)
+#define GPIO_ODR_ODR9_Msk (0x1U << GPIO_ODR_ODR9_Pos) /*!< 0x00000200 */
+#define GPIO_ODR_ODR9 GPIO_ODR_ODR9_Msk /*!< Port output data, bit 9 */
+#define GPIO_ODR_ODR10_Pos (10U)
+#define GPIO_ODR_ODR10_Msk (0x1U << GPIO_ODR_ODR10_Pos) /*!< 0x00000400 */
+#define GPIO_ODR_ODR10 GPIO_ODR_ODR10_Msk /*!< Port output data, bit 10 */
+#define GPIO_ODR_ODR11_Pos (11U)
+#define GPIO_ODR_ODR11_Msk (0x1U << GPIO_ODR_ODR11_Pos) /*!< 0x00000800 */
+#define GPIO_ODR_ODR11 GPIO_ODR_ODR11_Msk /*!< Port output data, bit 11 */
+#define GPIO_ODR_ODR12_Pos (12U)
+#define GPIO_ODR_ODR12_Msk (0x1U << GPIO_ODR_ODR12_Pos) /*!< 0x00001000 */
+#define GPIO_ODR_ODR12 GPIO_ODR_ODR12_Msk /*!< Port output data, bit 12 */
+#define GPIO_ODR_ODR13_Pos (13U)
+#define GPIO_ODR_ODR13_Msk (0x1U << GPIO_ODR_ODR13_Pos) /*!< 0x00002000 */
+#define GPIO_ODR_ODR13 GPIO_ODR_ODR13_Msk /*!< Port output data, bit 13 */
+#define GPIO_ODR_ODR14_Pos (14U)
+#define GPIO_ODR_ODR14_Msk (0x1U << GPIO_ODR_ODR14_Pos) /*!< 0x00004000 */
+#define GPIO_ODR_ODR14 GPIO_ODR_ODR14_Msk /*!< Port output data, bit 14 */
+#define GPIO_ODR_ODR15_Pos (15U)
+#define GPIO_ODR_ODR15_Msk (0x1U << GPIO_ODR_ODR15_Pos) /*!< 0x00008000 */
+#define GPIO_ODR_ODR15 GPIO_ODR_ODR15_Msk /*!< Port output data, bit 15 */
+
+/****************** Bit definition for GPIO_BSRR register *******************/
+#define GPIO_BSRR_BS0_Pos (0U)
+#define GPIO_BSRR_BS0_Msk (0x1U << GPIO_BSRR_BS0_Pos) /*!< 0x00000001 */
+#define GPIO_BSRR_BS0 GPIO_BSRR_BS0_Msk /*!< Port x Set bit 0 */
+#define GPIO_BSRR_BS1_Pos (1U)
+#define GPIO_BSRR_BS1_Msk (0x1U << GPIO_BSRR_BS1_Pos) /*!< 0x00000002 */
+#define GPIO_BSRR_BS1 GPIO_BSRR_BS1_Msk /*!< Port x Set bit 1 */
+#define GPIO_BSRR_BS2_Pos (2U)
+#define GPIO_BSRR_BS2_Msk (0x1U << GPIO_BSRR_BS2_Pos) /*!< 0x00000004 */
+#define GPIO_BSRR_BS2 GPIO_BSRR_BS2_Msk /*!< Port x Set bit 2 */
+#define GPIO_BSRR_BS3_Pos (3U)
+#define GPIO_BSRR_BS3_Msk (0x1U << GPIO_BSRR_BS3_Pos) /*!< 0x00000008 */
+#define GPIO_BSRR_BS3 GPIO_BSRR_BS3_Msk /*!< Port x Set bit 3 */
+#define GPIO_BSRR_BS4_Pos (4U)
+#define GPIO_BSRR_BS4_Msk (0x1U << GPIO_BSRR_BS4_Pos) /*!< 0x00000010 */
+#define GPIO_BSRR_BS4 GPIO_BSRR_BS4_Msk /*!< Port x Set bit 4 */
+#define GPIO_BSRR_BS5_Pos (5U)
+#define GPIO_BSRR_BS5_Msk (0x1U << GPIO_BSRR_BS5_Pos) /*!< 0x00000020 */
+#define GPIO_BSRR_BS5 GPIO_BSRR_BS5_Msk /*!< Port x Set bit 5 */
+#define GPIO_BSRR_BS6_Pos (6U)
+#define GPIO_BSRR_BS6_Msk (0x1U << GPIO_BSRR_BS6_Pos) /*!< 0x00000040 */
+#define GPIO_BSRR_BS6 GPIO_BSRR_BS6_Msk /*!< Port x Set bit 6 */
+#define GPIO_BSRR_BS7_Pos (7U)
+#define GPIO_BSRR_BS7_Msk (0x1U << GPIO_BSRR_BS7_Pos) /*!< 0x00000080 */
+#define GPIO_BSRR_BS7 GPIO_BSRR_BS7_Msk /*!< Port x Set bit 7 */
+#define GPIO_BSRR_BS8_Pos (8U)
+#define GPIO_BSRR_BS8_Msk (0x1U << GPIO_BSRR_BS8_Pos) /*!< 0x00000100 */
+#define GPIO_BSRR_BS8 GPIO_BSRR_BS8_Msk /*!< Port x Set bit 8 */
+#define GPIO_BSRR_BS9_Pos (9U)
+#define GPIO_BSRR_BS9_Msk (0x1U << GPIO_BSRR_BS9_Pos) /*!< 0x00000200 */
+#define GPIO_BSRR_BS9 GPIO_BSRR_BS9_Msk /*!< Port x Set bit 9 */
+#define GPIO_BSRR_BS10_Pos (10U)
+#define GPIO_BSRR_BS10_Msk (0x1U << GPIO_BSRR_BS10_Pos) /*!< 0x00000400 */
+#define GPIO_BSRR_BS10 GPIO_BSRR_BS10_Msk /*!< Port x Set bit 10 */
+#define GPIO_BSRR_BS11_Pos (11U)
+#define GPIO_BSRR_BS11_Msk (0x1U << GPIO_BSRR_BS11_Pos) /*!< 0x00000800 */
+#define GPIO_BSRR_BS11 GPIO_BSRR_BS11_Msk /*!< Port x Set bit 11 */
+#define GPIO_BSRR_BS12_Pos (12U)
+#define GPIO_BSRR_BS12_Msk (0x1U << GPIO_BSRR_BS12_Pos) /*!< 0x00001000 */
+#define GPIO_BSRR_BS12 GPIO_BSRR_BS12_Msk /*!< Port x Set bit 12 */
+#define GPIO_BSRR_BS13_Pos (13U)
+#define GPIO_BSRR_BS13_Msk (0x1U << GPIO_BSRR_BS13_Pos) /*!< 0x00002000 */
+#define GPIO_BSRR_BS13 GPIO_BSRR_BS13_Msk /*!< Port x Set bit 13 */
+#define GPIO_BSRR_BS14_Pos (14U)
+#define GPIO_BSRR_BS14_Msk (0x1U << GPIO_BSRR_BS14_Pos) /*!< 0x00004000 */
+#define GPIO_BSRR_BS14 GPIO_BSRR_BS14_Msk /*!< Port x Set bit 14 */
+#define GPIO_BSRR_BS15_Pos (15U)
+#define GPIO_BSRR_BS15_Msk (0x1U << GPIO_BSRR_BS15_Pos) /*!< 0x00008000 */
+#define GPIO_BSRR_BS15 GPIO_BSRR_BS15_Msk /*!< Port x Set bit 15 */
+
+#define GPIO_BSRR_BR0_Pos (16U)
+#define GPIO_BSRR_BR0_Msk (0x1U << GPIO_BSRR_BR0_Pos) /*!< 0x00010000 */
+#define GPIO_BSRR_BR0 GPIO_BSRR_BR0_Msk /*!< Port x Reset bit 0 */
+#define GPIO_BSRR_BR1_Pos (17U)
+#define GPIO_BSRR_BR1_Msk (0x1U << GPIO_BSRR_BR1_Pos) /*!< 0x00020000 */
+#define GPIO_BSRR_BR1 GPIO_BSRR_BR1_Msk /*!< Port x Reset bit 1 */
+#define GPIO_BSRR_BR2_Pos (18U)
+#define GPIO_BSRR_BR2_Msk (0x1U << GPIO_BSRR_BR2_Pos) /*!< 0x00040000 */
+#define GPIO_BSRR_BR2 GPIO_BSRR_BR2_Msk /*!< Port x Reset bit 2 */
+#define GPIO_BSRR_BR3_Pos (19U)
+#define GPIO_BSRR_BR3_Msk (0x1U << GPIO_BSRR_BR3_Pos) /*!< 0x00080000 */
+#define GPIO_BSRR_BR3 GPIO_BSRR_BR3_Msk /*!< Port x Reset bit 3 */
+#define GPIO_BSRR_BR4_Pos (20U)
+#define GPIO_BSRR_BR4_Msk (0x1U << GPIO_BSRR_BR4_Pos) /*!< 0x00100000 */
+#define GPIO_BSRR_BR4 GPIO_BSRR_BR4_Msk /*!< Port x Reset bit 4 */
+#define GPIO_BSRR_BR5_Pos (21U)
+#define GPIO_BSRR_BR5_Msk (0x1U << GPIO_BSRR_BR5_Pos) /*!< 0x00200000 */
+#define GPIO_BSRR_BR5 GPIO_BSRR_BR5_Msk /*!< Port x Reset bit 5 */
+#define GPIO_BSRR_BR6_Pos (22U)
+#define GPIO_BSRR_BR6_Msk (0x1U << GPIO_BSRR_BR6_Pos) /*!< 0x00400000 */
+#define GPIO_BSRR_BR6 GPIO_BSRR_BR6_Msk /*!< Port x Reset bit 6 */
+#define GPIO_BSRR_BR7_Pos (23U)
+#define GPIO_BSRR_BR7_Msk (0x1U << GPIO_BSRR_BR7_Pos) /*!< 0x00800000 */
+#define GPIO_BSRR_BR7 GPIO_BSRR_BR7_Msk /*!< Port x Reset bit 7 */
+#define GPIO_BSRR_BR8_Pos (24U)
+#define GPIO_BSRR_BR8_Msk (0x1U << GPIO_BSRR_BR8_Pos) /*!< 0x01000000 */
+#define GPIO_BSRR_BR8 GPIO_BSRR_BR8_Msk /*!< Port x Reset bit 8 */
+#define GPIO_BSRR_BR9_Pos (25U)
+#define GPIO_BSRR_BR9_Msk (0x1U << GPIO_BSRR_BR9_Pos) /*!< 0x02000000 */
+#define GPIO_BSRR_BR9 GPIO_BSRR_BR9_Msk /*!< Port x Reset bit 9 */
+#define GPIO_BSRR_BR10_Pos (26U)
+#define GPIO_BSRR_BR10_Msk (0x1U << GPIO_BSRR_BR10_Pos) /*!< 0x04000000 */
+#define GPIO_BSRR_BR10 GPIO_BSRR_BR10_Msk /*!< Port x Reset bit 10 */
+#define GPIO_BSRR_BR11_Pos (27U)
+#define GPIO_BSRR_BR11_Msk (0x1U << GPIO_BSRR_BR11_Pos) /*!< 0x08000000 */
+#define GPIO_BSRR_BR11 GPIO_BSRR_BR11_Msk /*!< Port x Reset bit 11 */
+#define GPIO_BSRR_BR12_Pos (28U)
+#define GPIO_BSRR_BR12_Msk (0x1U << GPIO_BSRR_BR12_Pos) /*!< 0x10000000 */
+#define GPIO_BSRR_BR12 GPIO_BSRR_BR12_Msk /*!< Port x Reset bit 12 */
+#define GPIO_BSRR_BR13_Pos (29U)
+#define GPIO_BSRR_BR13_Msk (0x1U << GPIO_BSRR_BR13_Pos) /*!< 0x20000000 */
+#define GPIO_BSRR_BR13 GPIO_BSRR_BR13_Msk /*!< Port x Reset bit 13 */
+#define GPIO_BSRR_BR14_Pos (30U)
+#define GPIO_BSRR_BR14_Msk (0x1U << GPIO_BSRR_BR14_Pos) /*!< 0x40000000 */
+#define GPIO_BSRR_BR14 GPIO_BSRR_BR14_Msk /*!< Port x Reset bit 14 */
+#define GPIO_BSRR_BR15_Pos (31U)
+#define GPIO_BSRR_BR15_Msk (0x1U << GPIO_BSRR_BR15_Pos) /*!< 0x80000000 */
+#define GPIO_BSRR_BR15 GPIO_BSRR_BR15_Msk /*!< Port x Reset bit 15 */
+
+/******************* Bit definition for GPIO_BRR register *******************/
+#define GPIO_BRR_BR0_Pos (0U)
+#define GPIO_BRR_BR0_Msk (0x1U << GPIO_BRR_BR0_Pos) /*!< 0x00000001 */
+#define GPIO_BRR_BR0 GPIO_BRR_BR0_Msk /*!< Port x Reset bit 0 */
+#define GPIO_BRR_BR1_Pos (1U)
+#define GPIO_BRR_BR1_Msk (0x1U << GPIO_BRR_BR1_Pos) /*!< 0x00000002 */
+#define GPIO_BRR_BR1 GPIO_BRR_BR1_Msk /*!< Port x Reset bit 1 */
+#define GPIO_BRR_BR2_Pos (2U)
+#define GPIO_BRR_BR2_Msk (0x1U << GPIO_BRR_BR2_Pos) /*!< 0x00000004 */
+#define GPIO_BRR_BR2 GPIO_BRR_BR2_Msk /*!< Port x Reset bit 2 */
+#define GPIO_BRR_BR3_Pos (3U)
+#define GPIO_BRR_BR3_Msk (0x1U << GPIO_BRR_BR3_Pos) /*!< 0x00000008 */
+#define GPIO_BRR_BR3 GPIO_BRR_BR3_Msk /*!< Port x Reset bit 3 */
+#define GPIO_BRR_BR4_Pos (4U)
+#define GPIO_BRR_BR4_Msk (0x1U << GPIO_BRR_BR4_Pos) /*!< 0x00000010 */
+#define GPIO_BRR_BR4 GPIO_BRR_BR4_Msk /*!< Port x Reset bit 4 */
+#define GPIO_BRR_BR5_Pos (5U)
+#define GPIO_BRR_BR5_Msk (0x1U << GPIO_BRR_BR5_Pos) /*!< 0x00000020 */
+#define GPIO_BRR_BR5 GPIO_BRR_BR5_Msk /*!< Port x Reset bit 5 */
+#define GPIO_BRR_BR6_Pos (6U)
+#define GPIO_BRR_BR6_Msk (0x1U << GPIO_BRR_BR6_Pos) /*!< 0x00000040 */
+#define GPIO_BRR_BR6 GPIO_BRR_BR6_Msk /*!< Port x Reset bit 6 */
+#define GPIO_BRR_BR7_Pos (7U)
+#define GPIO_BRR_BR7_Msk (0x1U << GPIO_BRR_BR7_Pos) /*!< 0x00000080 */
+#define GPIO_BRR_BR7 GPIO_BRR_BR7_Msk /*!< Port x Reset bit 7 */
+#define GPIO_BRR_BR8_Pos (8U)
+#define GPIO_BRR_BR8_Msk (0x1U << GPIO_BRR_BR8_Pos) /*!< 0x00000100 */
+#define GPIO_BRR_BR8 GPIO_BRR_BR8_Msk /*!< Port x Reset bit 8 */
+#define GPIO_BRR_BR9_Pos (9U)
+#define GPIO_BRR_BR9_Msk (0x1U << GPIO_BRR_BR9_Pos) /*!< 0x00000200 */
+#define GPIO_BRR_BR9 GPIO_BRR_BR9_Msk /*!< Port x Reset bit 9 */
+#define GPIO_BRR_BR10_Pos (10U)
+#define GPIO_BRR_BR10_Msk (0x1U << GPIO_BRR_BR10_Pos) /*!< 0x00000400 */
+#define GPIO_BRR_BR10 GPIO_BRR_BR10_Msk /*!< Port x Reset bit 10 */
+#define GPIO_BRR_BR11_Pos (11U)
+#define GPIO_BRR_BR11_Msk (0x1U << GPIO_BRR_BR11_Pos) /*!< 0x00000800 */
+#define GPIO_BRR_BR11 GPIO_BRR_BR11_Msk /*!< Port x Reset bit 11 */
+#define GPIO_BRR_BR12_Pos (12U)
+#define GPIO_BRR_BR12_Msk (0x1U << GPIO_BRR_BR12_Pos) /*!< 0x00001000 */
+#define GPIO_BRR_BR12 GPIO_BRR_BR12_Msk /*!< Port x Reset bit 12 */
+#define GPIO_BRR_BR13_Pos (13U)
+#define GPIO_BRR_BR13_Msk (0x1U << GPIO_BRR_BR13_Pos) /*!< 0x00002000 */
+#define GPIO_BRR_BR13 GPIO_BRR_BR13_Msk /*!< Port x Reset bit 13 */
+#define GPIO_BRR_BR14_Pos (14U)
+#define GPIO_BRR_BR14_Msk (0x1U << GPIO_BRR_BR14_Pos) /*!< 0x00004000 */
+#define GPIO_BRR_BR14 GPIO_BRR_BR14_Msk /*!< Port x Reset bit 14 */
+#define GPIO_BRR_BR15_Pos (15U)
+#define GPIO_BRR_BR15_Msk (0x1U << GPIO_BRR_BR15_Pos) /*!< 0x00008000 */
+#define GPIO_BRR_BR15 GPIO_BRR_BR15_Msk /*!< Port x Reset bit 15 */
+
+/****************** Bit definition for GPIO_LCKR register *******************/
+#define GPIO_LCKR_LCK0_Pos (0U)
+#define GPIO_LCKR_LCK0_Msk (0x1U << GPIO_LCKR_LCK0_Pos) /*!< 0x00000001 */
+#define GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk /*!< Port x Lock bit 0 */
+#define GPIO_LCKR_LCK1_Pos (1U)
+#define GPIO_LCKR_LCK1_Msk (0x1U << GPIO_LCKR_LCK1_Pos) /*!< 0x00000002 */
+#define GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk /*!< Port x Lock bit 1 */
+#define GPIO_LCKR_LCK2_Pos (2U)
+#define GPIO_LCKR_LCK2_Msk (0x1U << GPIO_LCKR_LCK2_Pos) /*!< 0x00000004 */
+#define GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk /*!< Port x Lock bit 2 */
+#define GPIO_LCKR_LCK3_Pos (3U)
+#define GPIO_LCKR_LCK3_Msk (0x1U << GPIO_LCKR_LCK3_Pos) /*!< 0x00000008 */
+#define GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk /*!< Port x Lock bit 3 */
+#define GPIO_LCKR_LCK4_Pos (4U)
+#define GPIO_LCKR_LCK4_Msk (0x1U << GPIO_LCKR_LCK4_Pos) /*!< 0x00000010 */
+#define GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk /*!< Port x Lock bit 4 */
+#define GPIO_LCKR_LCK5_Pos (5U)
+#define GPIO_LCKR_LCK5_Msk (0x1U << GPIO_LCKR_LCK5_Pos) /*!< 0x00000020 */
+#define GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk /*!< Port x Lock bit 5 */
+#define GPIO_LCKR_LCK6_Pos (6U)
+#define GPIO_LCKR_LCK6_Msk (0x1U << GPIO_LCKR_LCK6_Pos) /*!< 0x00000040 */
+#define GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk /*!< Port x Lock bit 6 */
+#define GPIO_LCKR_LCK7_Pos (7U)
+#define GPIO_LCKR_LCK7_Msk (0x1U << GPIO_LCKR_LCK7_Pos) /*!< 0x00000080 */
+#define GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk /*!< Port x Lock bit 7 */
+#define GPIO_LCKR_LCK8_Pos (8U)
+#define GPIO_LCKR_LCK8_Msk (0x1U << GPIO_LCKR_LCK8_Pos) /*!< 0x00000100 */
+#define GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk /*!< Port x Lock bit 8 */
+#define GPIO_LCKR_LCK9_Pos (9U)
+#define GPIO_LCKR_LCK9_Msk (0x1U << GPIO_LCKR_LCK9_Pos) /*!< 0x00000200 */
+#define GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk /*!< Port x Lock bit 9 */
+#define GPIO_LCKR_LCK10_Pos (10U)
+#define GPIO_LCKR_LCK10_Msk (0x1U << GPIO_LCKR_LCK10_Pos) /*!< 0x00000400 */
+#define GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk /*!< Port x Lock bit 10 */
+#define GPIO_LCKR_LCK11_Pos (11U)
+#define GPIO_LCKR_LCK11_Msk (0x1U << GPIO_LCKR_LCK11_Pos) /*!< 0x00000800 */
+#define GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk /*!< Port x Lock bit 11 */
+#define GPIO_LCKR_LCK12_Pos (12U)
+#define GPIO_LCKR_LCK12_Msk (0x1U << GPIO_LCKR_LCK12_Pos) /*!< 0x00001000 */
+#define GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk /*!< Port x Lock bit 12 */
+#define GPIO_LCKR_LCK13_Pos (13U)
+#define GPIO_LCKR_LCK13_Msk (0x1U << GPIO_LCKR_LCK13_Pos) /*!< 0x00002000 */
+#define GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk /*!< Port x Lock bit 13 */
+#define GPIO_LCKR_LCK14_Pos (14U)
+#define GPIO_LCKR_LCK14_Msk (0x1U << GPIO_LCKR_LCK14_Pos) /*!< 0x00004000 */
+#define GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk /*!< Port x Lock bit 14 */
+#define GPIO_LCKR_LCK15_Pos (15U)
+#define GPIO_LCKR_LCK15_Msk (0x1U << GPIO_LCKR_LCK15_Pos) /*!< 0x00008000 */
+#define GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk /*!< Port x Lock bit 15 */
+#define GPIO_LCKR_LCKK_Pos (16U)
+#define GPIO_LCKR_LCKK_Msk (0x1U << GPIO_LCKR_LCKK_Pos) /*!< 0x00010000 */
+#define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk /*!< Lock key */
+
+/*----------------------------------------------------------------------------*/
+
+/****************** Bit definition for AFIO_EVCR register *******************/
+#define AFIO_EVCR_PIN_Pos (0U)
+#define AFIO_EVCR_PIN_Msk (0xFU << AFIO_EVCR_PIN_Pos) /*!< 0x0000000F */
+#define AFIO_EVCR_PIN AFIO_EVCR_PIN_Msk /*!< PIN[3:0] bits (Pin selection) */
+#define AFIO_EVCR_PIN_0 (0x1U << AFIO_EVCR_PIN_Pos) /*!< 0x00000001 */
+#define AFIO_EVCR_PIN_1 (0x2U << AFIO_EVCR_PIN_Pos) /*!< 0x00000002 */
+#define AFIO_EVCR_PIN_2 (0x4U << AFIO_EVCR_PIN_Pos) /*!< 0x00000004 */
+#define AFIO_EVCR_PIN_3 (0x8U << AFIO_EVCR_PIN_Pos) /*!< 0x00000008 */
+
+/*!< PIN configuration */
+#define AFIO_EVCR_PIN_PX0 ((uint32_t)0x00000000) /*!< Pin 0 selected */
+#define AFIO_EVCR_PIN_PX1_Pos (0U)
+#define AFIO_EVCR_PIN_PX1_Msk (0x1U << AFIO_EVCR_PIN_PX1_Pos) /*!< 0x00000001 */
+#define AFIO_EVCR_PIN_PX1 AFIO_EVCR_PIN_PX1_Msk /*!< Pin 1 selected */
+#define AFIO_EVCR_PIN_PX2_Pos (1U)
+#define AFIO_EVCR_PIN_PX2_Msk (0x1U << AFIO_EVCR_PIN_PX2_Pos) /*!< 0x00000002 */
+#define AFIO_EVCR_PIN_PX2 AFIO_EVCR_PIN_PX2_Msk /*!< Pin 2 selected */
+#define AFIO_EVCR_PIN_PX3_Pos (0U)
+#define AFIO_EVCR_PIN_PX3_Msk (0x3U << AFIO_EVCR_PIN_PX3_Pos) /*!< 0x00000003 */
+#define AFIO_EVCR_PIN_PX3 AFIO_EVCR_PIN_PX3_Msk /*!< Pin 3 selected */
+#define AFIO_EVCR_PIN_PX4_Pos (2U)
+#define AFIO_EVCR_PIN_PX4_Msk (0x1U << AFIO_EVCR_PIN_PX4_Pos) /*!< 0x00000004 */
+#define AFIO_EVCR_PIN_PX4 AFIO_EVCR_PIN_PX4_Msk /*!< Pin 4 selected */
+#define AFIO_EVCR_PIN_PX5_Pos (0U)
+#define AFIO_EVCR_PIN_PX5_Msk (0x5U << AFIO_EVCR_PIN_PX5_Pos) /*!< 0x00000005 */
+#define AFIO_EVCR_PIN_PX5 AFIO_EVCR_PIN_PX5_Msk /*!< Pin 5 selected */
+#define AFIO_EVCR_PIN_PX6_Pos (1U)
+#define AFIO_EVCR_PIN_PX6_Msk (0x3U << AFIO_EVCR_PIN_PX6_Pos) /*!< 0x00000006 */
+#define AFIO_EVCR_PIN_PX6 AFIO_EVCR_PIN_PX6_Msk /*!< Pin 6 selected */
+#define AFIO_EVCR_PIN_PX7_Pos (0U)
+#define AFIO_EVCR_PIN_PX7_Msk (0x7U << AFIO_EVCR_PIN_PX7_Pos) /*!< 0x00000007 */
+#define AFIO_EVCR_PIN_PX7 AFIO_EVCR_PIN_PX7_Msk /*!< Pin 7 selected */
+#define AFIO_EVCR_PIN_PX8_Pos (3U)
+#define AFIO_EVCR_PIN_PX8_Msk (0x1U << AFIO_EVCR_PIN_PX8_Pos) /*!< 0x00000008 */
+#define AFIO_EVCR_PIN_PX8 AFIO_EVCR_PIN_PX8_Msk /*!< Pin 8 selected */
+#define AFIO_EVCR_PIN_PX9_Pos (0U)
+#define AFIO_EVCR_PIN_PX9_Msk (0x9U << AFIO_EVCR_PIN_PX9_Pos) /*!< 0x00000009 */
+#define AFIO_EVCR_PIN_PX9 AFIO_EVCR_PIN_PX9_Msk /*!< Pin 9 selected */
+#define AFIO_EVCR_PIN_PX10_Pos (1U)
+#define AFIO_EVCR_PIN_PX10_Msk (0x5U << AFIO_EVCR_PIN_PX10_Pos) /*!< 0x0000000A */
+#define AFIO_EVCR_PIN_PX10 AFIO_EVCR_PIN_PX10_Msk /*!< Pin 10 selected */
+#define AFIO_EVCR_PIN_PX11_Pos (0U)
+#define AFIO_EVCR_PIN_PX11_Msk (0xBU << AFIO_EVCR_PIN_PX11_Pos) /*!< 0x0000000B */
+#define AFIO_EVCR_PIN_PX11 AFIO_EVCR_PIN_PX11_Msk /*!< Pin 11 selected */
+#define AFIO_EVCR_PIN_PX12_Pos (2U)
+#define AFIO_EVCR_PIN_PX12_Msk (0x3U << AFIO_EVCR_PIN_PX12_Pos) /*!< 0x0000000C */
+#define AFIO_EVCR_PIN_PX12 AFIO_EVCR_PIN_PX12_Msk /*!< Pin 12 selected */
+#define AFIO_EVCR_PIN_PX13_Pos (0U)
+#define AFIO_EVCR_PIN_PX13_Msk (0xDU << AFIO_EVCR_PIN_PX13_Pos) /*!< 0x0000000D */
+#define AFIO_EVCR_PIN_PX13 AFIO_EVCR_PIN_PX13_Msk /*!< Pin 13 selected */
+#define AFIO_EVCR_PIN_PX14_Pos (1U)
+#define AFIO_EVCR_PIN_PX14_Msk (0x7U << AFIO_EVCR_PIN_PX14_Pos) /*!< 0x0000000E */
+#define AFIO_EVCR_PIN_PX14 AFIO_EVCR_PIN_PX14_Msk /*!< Pin 14 selected */
+#define AFIO_EVCR_PIN_PX15_Pos (0U)
+#define AFIO_EVCR_PIN_PX15_Msk (0xFU << AFIO_EVCR_PIN_PX15_Pos) /*!< 0x0000000F */
+#define AFIO_EVCR_PIN_PX15 AFIO_EVCR_PIN_PX15_Msk /*!< Pin 15 selected */
+
+#define AFIO_EVCR_PORT_Pos (4U)
+#define AFIO_EVCR_PORT_Msk (0x7U << AFIO_EVCR_PORT_Pos) /*!< 0x00000070 */
+#define AFIO_EVCR_PORT AFIO_EVCR_PORT_Msk /*!< PORT[2:0] bits (Port selection) */
+#define AFIO_EVCR_PORT_0 (0x1U << AFIO_EVCR_PORT_Pos) /*!< 0x00000010 */
+#define AFIO_EVCR_PORT_1 (0x2U << AFIO_EVCR_PORT_Pos) /*!< 0x00000020 */
+#define AFIO_EVCR_PORT_2 (0x4U << AFIO_EVCR_PORT_Pos) /*!< 0x00000040 */
+
+/*!< PORT configuration */
+#define AFIO_EVCR_PORT_PA ((uint32_t)0x00000000) /*!< Port A selected */
+#define AFIO_EVCR_PORT_PB_Pos (4U)
+#define AFIO_EVCR_PORT_PB_Msk (0x1U << AFIO_EVCR_PORT_PB_Pos) /*!< 0x00000010 */
+#define AFIO_EVCR_PORT_PB AFIO_EVCR_PORT_PB_Msk /*!< Port B selected */
+#define AFIO_EVCR_PORT_PC_Pos (5U)
+#define AFIO_EVCR_PORT_PC_Msk (0x1U << AFIO_EVCR_PORT_PC_Pos) /*!< 0x00000020 */
+#define AFIO_EVCR_PORT_PC AFIO_EVCR_PORT_PC_Msk /*!< Port C selected */
+#define AFIO_EVCR_PORT_PD_Pos (4U)
+#define AFIO_EVCR_PORT_PD_Msk (0x3U << AFIO_EVCR_PORT_PD_Pos) /*!< 0x00000030 */
+#define AFIO_EVCR_PORT_PD AFIO_EVCR_PORT_PD_Msk /*!< Port D selected */
+#define AFIO_EVCR_PORT_PE_Pos (6U)
+#define AFIO_EVCR_PORT_PE_Msk (0x1U << AFIO_EVCR_PORT_PE_Pos) /*!< 0x00000040 */
+#define AFIO_EVCR_PORT_PE AFIO_EVCR_PORT_PE_Msk /*!< Port E selected */
+
+#define AFIO_EVCR_EVOE_Pos (7U)
+#define AFIO_EVCR_EVOE_Msk (0x1U << AFIO_EVCR_EVOE_Pos) /*!< 0x00000080 */
+#define AFIO_EVCR_EVOE AFIO_EVCR_EVOE_Msk /*!< Event Output Enable */
+
+/****************** Bit definition for AFIO_MAPR register *******************/
+#define AFIO_MAPR_SPI1_REMAP_Pos (0U)
+#define AFIO_MAPR_SPI1_REMAP_Msk (0x1U << AFIO_MAPR_SPI1_REMAP_Pos) /*!< 0x00000001 */
+#define AFIO_MAPR_SPI1_REMAP AFIO_MAPR_SPI1_REMAP_Msk /*!< SPI1 remapping */
+#define AFIO_MAPR_I2C1_REMAP_Pos (1U)
+#define AFIO_MAPR_I2C1_REMAP_Msk (0x1U << AFIO_MAPR_I2C1_REMAP_Pos) /*!< 0x00000002 */
+#define AFIO_MAPR_I2C1_REMAP AFIO_MAPR_I2C1_REMAP_Msk /*!< I2C1 remapping */
+#define AFIO_MAPR_USART1_REMAP_Pos (2U)
+#define AFIO_MAPR_USART1_REMAP_Msk (0x1U << AFIO_MAPR_USART1_REMAP_Pos) /*!< 0x00000004 */
+#define AFIO_MAPR_USART1_REMAP AFIO_MAPR_USART1_REMAP_Msk /*!< USART1 remapping */
+#define AFIO_MAPR_USART2_REMAP_Pos (3U)
+#define AFIO_MAPR_USART2_REMAP_Msk (0x1U << AFIO_MAPR_USART2_REMAP_Pos) /*!< 0x00000008 */
+#define AFIO_MAPR_USART2_REMAP AFIO_MAPR_USART2_REMAP_Msk /*!< USART2 remapping */
+
+#define AFIO_MAPR_USART3_REMAP_Pos (4U)
+#define AFIO_MAPR_USART3_REMAP_Msk (0x3U << AFIO_MAPR_USART3_REMAP_Pos) /*!< 0x00000030 */
+#define AFIO_MAPR_USART3_REMAP AFIO_MAPR_USART3_REMAP_Msk /*!< USART3_REMAP[1:0] bits (USART3 remapping) */
+#define AFIO_MAPR_USART3_REMAP_0 (0x1U << AFIO_MAPR_USART3_REMAP_Pos) /*!< 0x00000010 */
+#define AFIO_MAPR_USART3_REMAP_1 (0x2U << AFIO_MAPR_USART3_REMAP_Pos) /*!< 0x00000020 */
+
+/* USART3_REMAP configuration */
+#define AFIO_MAPR_USART3_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14) */
+#define AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Pos (4U)
+#define AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Msk (0x1U << AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Pos) /*!< 0x00000010 */
+#define AFIO_MAPR_USART3_REMAP_PARTIALREMAP AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Msk /*!< Partial remap (TX/PC10, RX/PC11, CK/PC12, CTS/PB13, RTS/PB14) */
+#define AFIO_MAPR_USART3_REMAP_FULLREMAP_Pos (4U)
+#define AFIO_MAPR_USART3_REMAP_FULLREMAP_Msk (0x3U << AFIO_MAPR_USART3_REMAP_FULLREMAP_Pos) /*!< 0x00000030 */
+#define AFIO_MAPR_USART3_REMAP_FULLREMAP AFIO_MAPR_USART3_REMAP_FULLREMAP_Msk /*!< Full remap (TX/PD8, RX/PD9, CK/PD10, CTS/PD11, RTS/PD12) */
+
+#define AFIO_MAPR_TIM1_REMAP_Pos (6U)
+#define AFIO_MAPR_TIM1_REMAP_Msk (0x3U << AFIO_MAPR_TIM1_REMAP_Pos) /*!< 0x000000C0 */
+#define AFIO_MAPR_TIM1_REMAP AFIO_MAPR_TIM1_REMAP_Msk /*!< TIM1_REMAP[1:0] bits (TIM1 remapping) */
+#define AFIO_MAPR_TIM1_REMAP_0 (0x1U << AFIO_MAPR_TIM1_REMAP_Pos) /*!< 0x00000040 */
+#define AFIO_MAPR_TIM1_REMAP_1 (0x2U << AFIO_MAPR_TIM1_REMAP_Pos) /*!< 0x00000080 */
+
+/*!< TIM1_REMAP configuration */
+#define AFIO_MAPR_TIM1_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15) */
+#define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Pos (6U)
+#define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Msk (0x1U << AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Pos) /*!< 0x00000040 */
+#define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Msk /*!< Partial remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PA6, CH1N/PA7, CH2N/PB0, CH3N/PB1) */
+#define AFIO_MAPR_TIM1_REMAP_FULLREMAP_Pos (6U)
+#define AFIO_MAPR_TIM1_REMAP_FULLREMAP_Msk (0x3U << AFIO_MAPR_TIM1_REMAP_FULLREMAP_Pos) /*!< 0x000000C0 */
+#define AFIO_MAPR_TIM1_REMAP_FULLREMAP AFIO_MAPR_TIM1_REMAP_FULLREMAP_Msk /*!< Full remap (ETR/PE7, CH1/PE9, CH2/PE11, CH3/PE13, CH4/PE14, BKIN/PE15, CH1N/PE8, CH2N/PE10, CH3N/PE12) */
+
+#define AFIO_MAPR_TIM2_REMAP_Pos (8U)
+#define AFIO_MAPR_TIM2_REMAP_Msk (0x3U << AFIO_MAPR_TIM2_REMAP_Pos) /*!< 0x00000300 */
+#define AFIO_MAPR_TIM2_REMAP AFIO_MAPR_TIM2_REMAP_Msk /*!< TIM2_REMAP[1:0] bits (TIM2 remapping) */
+#define AFIO_MAPR_TIM2_REMAP_0 (0x1U << AFIO_MAPR_TIM2_REMAP_Pos) /*!< 0x00000100 */
+#define AFIO_MAPR_TIM2_REMAP_1 (0x2U << AFIO_MAPR_TIM2_REMAP_Pos) /*!< 0x00000200 */
+
+/*!< TIM2_REMAP configuration */
+#define AFIO_MAPR_TIM2_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3) */
+#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Pos (8U)
+#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Msk (0x1U << AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Pos) /*!< 0x00000100 */
+#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1 AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Msk /*!< Partial remap (CH1/ETR/PA15, CH2/PB3, CH3/PA2, CH4/PA3) */
+#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2_Pos (9U)
+#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2_Msk (0x1U << AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2_Pos) /*!< 0x00000200 */
+#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2 AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2_Msk /*!< Partial remap (CH1/ETR/PA0, CH2/PA1, CH3/PB10, CH4/PB11) */
+#define AFIO_MAPR_TIM2_REMAP_FULLREMAP_Pos (8U)
+#define AFIO_MAPR_TIM2_REMAP_FULLREMAP_Msk (0x3U << AFIO_MAPR_TIM2_REMAP_FULLREMAP_Pos) /*!< 0x00000300 */
+#define AFIO_MAPR_TIM2_REMAP_FULLREMAP AFIO_MAPR_TIM2_REMAP_FULLREMAP_Msk /*!< Full remap (CH1/ETR/PA15, CH2/PB3, CH3/PB10, CH4/PB11) */
+
+#define AFIO_MAPR_TIM3_REMAP_Pos (10U)
+#define AFIO_MAPR_TIM3_REMAP_Msk (0x3U << AFIO_MAPR_TIM3_REMAP_Pos) /*!< 0x00000C00 */
+#define AFIO_MAPR_TIM3_REMAP AFIO_MAPR_TIM3_REMAP_Msk /*!< TIM3_REMAP[1:0] bits (TIM3 remapping) */
+#define AFIO_MAPR_TIM3_REMAP_0 (0x1U << AFIO_MAPR_TIM3_REMAP_Pos) /*!< 0x00000400 */
+#define AFIO_MAPR_TIM3_REMAP_1 (0x2U << AFIO_MAPR_TIM3_REMAP_Pos) /*!< 0x00000800 */
+
+/*!< TIM3_REMAP configuration */
+#define AFIO_MAPR_TIM3_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1) */
+#define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Pos (11U)
+#define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Msk (0x1U << AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Pos) /*!< 0x00000800 */
+#define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Msk /*!< Partial remap (CH1/PB4, CH2/PB5, CH3/PB0, CH4/PB1) */
+#define AFIO_MAPR_TIM3_REMAP_FULLREMAP_Pos (10U)
+#define AFIO_MAPR_TIM3_REMAP_FULLREMAP_Msk (0x3U << AFIO_MAPR_TIM3_REMAP_FULLREMAP_Pos) /*!< 0x00000C00 */
+#define AFIO_MAPR_TIM3_REMAP_FULLREMAP AFIO_MAPR_TIM3_REMAP_FULLREMAP_Msk /*!< Full remap (CH1/PC6, CH2/PC7, CH3/PC8, CH4/PC9) */
+
+#define AFIO_MAPR_TIM4_REMAP_Pos (12U)
+#define AFIO_MAPR_TIM4_REMAP_Msk (0x1U << AFIO_MAPR_TIM4_REMAP_Pos) /*!< 0x00001000 */
+#define AFIO_MAPR_TIM4_REMAP AFIO_MAPR_TIM4_REMAP_Msk /*!< TIM4_REMAP bit (TIM4 remapping) */
+
+
+#define AFIO_MAPR_PD01_REMAP_Pos (15U)
+#define AFIO_MAPR_PD01_REMAP_Msk (0x1U << AFIO_MAPR_PD01_REMAP_Pos) /*!< 0x00008000 */
+#define AFIO_MAPR_PD01_REMAP AFIO_MAPR_PD01_REMAP_Msk /*!< Port D0/Port D1 mapping on OSC_IN/OSC_OUT */
+
+/*!< SWJ_CFG configuration */
+#define AFIO_MAPR_SWJ_CFG_Pos (24U)
+#define AFIO_MAPR_SWJ_CFG_Msk (0x7U << AFIO_MAPR_SWJ_CFG_Pos) /*!< 0x07000000 */
+#define AFIO_MAPR_SWJ_CFG AFIO_MAPR_SWJ_CFG_Msk /*!< SWJ_CFG[2:0] bits (Serial Wire JTAG configuration) */
+#define AFIO_MAPR_SWJ_CFG_0 (0x1U << AFIO_MAPR_SWJ_CFG_Pos) /*!< 0x01000000 */
+#define AFIO_MAPR_SWJ_CFG_1 (0x2U << AFIO_MAPR_SWJ_CFG_Pos) /*!< 0x02000000 */
+#define AFIO_MAPR_SWJ_CFG_2 (0x4U << AFIO_MAPR_SWJ_CFG_Pos) /*!< 0x04000000 */
+
+#define AFIO_MAPR_SWJ_CFG_RESET ((uint32_t)0x00000000) /*!< Full SWJ (JTAG-DP + SW-DP) : Reset State */
+#define AFIO_MAPR_SWJ_CFG_NOJNTRST_Pos (24U)
+#define AFIO_MAPR_SWJ_CFG_NOJNTRST_Msk (0x1U << AFIO_MAPR_SWJ_CFG_NOJNTRST_Pos) /*!< 0x01000000 */
+#define AFIO_MAPR_SWJ_CFG_NOJNTRST AFIO_MAPR_SWJ_CFG_NOJNTRST_Msk /*!< Full SWJ (JTAG-DP + SW-DP) but without JNTRST */
+#define AFIO_MAPR_SWJ_CFG_JTAGDISABLE_Pos (25U)
+#define AFIO_MAPR_SWJ_CFG_JTAGDISABLE_Msk (0x1U << AFIO_MAPR_SWJ_CFG_JTAGDISABLE_Pos) /*!< 0x02000000 */
+#define AFIO_MAPR_SWJ_CFG_JTAGDISABLE AFIO_MAPR_SWJ_CFG_JTAGDISABLE_Msk /*!< JTAG-DP Disabled and SW-DP Enabled */
+#define AFIO_MAPR_SWJ_CFG_DISABLE_Pos (26U)
+#define AFIO_MAPR_SWJ_CFG_DISABLE_Msk (0x1U << AFIO_MAPR_SWJ_CFG_DISABLE_Pos) /*!< 0x04000000 */
+#define AFIO_MAPR_SWJ_CFG_DISABLE AFIO_MAPR_SWJ_CFG_DISABLE_Msk /*!< JTAG-DP Disabled and SW-DP Disabled */
+
+
+/***************** Bit definition for AFIO_EXTICR1 register *****************/
+#define AFIO_EXTICR1_EXTI0_Pos (0U)
+#define AFIO_EXTICR1_EXTI0_Msk (0xFU << AFIO_EXTICR1_EXTI0_Pos) /*!< 0x0000000F */
+#define AFIO_EXTICR1_EXTI0 AFIO_EXTICR1_EXTI0_Msk /*!< EXTI 0 configuration */
+#define AFIO_EXTICR1_EXTI1_Pos (4U)
+#define AFIO_EXTICR1_EXTI1_Msk (0xFU << AFIO_EXTICR1_EXTI1_Pos) /*!< 0x000000F0 */
+#define AFIO_EXTICR1_EXTI1 AFIO_EXTICR1_EXTI1_Msk /*!< EXTI 1 configuration */
+#define AFIO_EXTICR1_EXTI2_Pos (8U)
+#define AFIO_EXTICR1_EXTI2_Msk (0xFU << AFIO_EXTICR1_EXTI2_Pos) /*!< 0x00000F00 */
+#define AFIO_EXTICR1_EXTI2 AFIO_EXTICR1_EXTI2_Msk /*!< EXTI 2 configuration */
+#define AFIO_EXTICR1_EXTI3_Pos (12U)
+#define AFIO_EXTICR1_EXTI3_Msk (0xFU << AFIO_EXTICR1_EXTI3_Pos) /*!< 0x0000F000 */
+#define AFIO_EXTICR1_EXTI3 AFIO_EXTICR1_EXTI3_Msk /*!< EXTI 3 configuration */
+
+/*!< EXTI0 configuration */
+#define AFIO_EXTICR1_EXTI0_PA ((uint32_t)0x00000000) /*!< PA[0] pin */
+#define AFIO_EXTICR1_EXTI0_PB_Pos (0U)
+#define AFIO_EXTICR1_EXTI0_PB_Msk (0x1U << AFIO_EXTICR1_EXTI0_PB_Pos) /*!< 0x00000001 */
+#define AFIO_EXTICR1_EXTI0_PB AFIO_EXTICR1_EXTI0_PB_Msk /*!< PB[0] pin */
+#define AFIO_EXTICR1_EXTI0_PC_Pos (1U)
+#define AFIO_EXTICR1_EXTI0_PC_Msk (0x1U << AFIO_EXTICR1_EXTI0_PC_Pos) /*!< 0x00000002 */
+#define AFIO_EXTICR1_EXTI0_PC AFIO_EXTICR1_EXTI0_PC_Msk /*!< PC[0] pin */
+#define AFIO_EXTICR1_EXTI0_PD_Pos (0U)
+#define AFIO_EXTICR1_EXTI0_PD_Msk (0x3U << AFIO_EXTICR1_EXTI0_PD_Pos) /*!< 0x00000003 */
+#define AFIO_EXTICR1_EXTI0_PD AFIO_EXTICR1_EXTI0_PD_Msk /*!< PD[0] pin */
+#define AFIO_EXTICR1_EXTI0_PE_Pos (2U)
+#define AFIO_EXTICR1_EXTI0_PE_Msk (0x1U << AFIO_EXTICR1_EXTI0_PE_Pos) /*!< 0x00000004 */
+#define AFIO_EXTICR1_EXTI0_PE AFIO_EXTICR1_EXTI0_PE_Msk /*!< PE[0] pin */
+#define AFIO_EXTICR1_EXTI0_PF_Pos (0U)
+#define AFIO_EXTICR1_EXTI0_PF_Msk (0x5U << AFIO_EXTICR1_EXTI0_PF_Pos) /*!< 0x00000005 */
+#define AFIO_EXTICR1_EXTI0_PF AFIO_EXTICR1_EXTI0_PF_Msk /*!< PF[0] pin */
+#define AFIO_EXTICR1_EXTI0_PG_Pos (1U)
+#define AFIO_EXTICR1_EXTI0_PG_Msk (0x3U << AFIO_EXTICR1_EXTI0_PG_Pos) /*!< 0x00000006 */
+#define AFIO_EXTICR1_EXTI0_PG AFIO_EXTICR1_EXTI0_PG_Msk /*!< PG[0] pin */
+
+/*!< EXTI1 configuration */
+#define AFIO_EXTICR1_EXTI1_PA ((uint32_t)0x00000000) /*!< PA[1] pin */
+#define AFIO_EXTICR1_EXTI1_PB_Pos (4U)
+#define AFIO_EXTICR1_EXTI1_PB_Msk (0x1U << AFIO_EXTICR1_EXTI1_PB_Pos) /*!< 0x00000010 */
+#define AFIO_EXTICR1_EXTI1_PB AFIO_EXTICR1_EXTI1_PB_Msk /*!< PB[1] pin */
+#define AFIO_EXTICR1_EXTI1_PC_Pos (5U)
+#define AFIO_EXTICR1_EXTI1_PC_Msk (0x1U << AFIO_EXTICR1_EXTI1_PC_Pos) /*!< 0x00000020 */
+#define AFIO_EXTICR1_EXTI1_PC AFIO_EXTICR1_EXTI1_PC_Msk /*!< PC[1] pin */
+#define AFIO_EXTICR1_EXTI1_PD_Pos (4U)
+#define AFIO_EXTICR1_EXTI1_PD_Msk (0x3U << AFIO_EXTICR1_EXTI1_PD_Pos) /*!< 0x00000030 */
+#define AFIO_EXTICR1_EXTI1_PD AFIO_EXTICR1_EXTI1_PD_Msk /*!< PD[1] pin */
+#define AFIO_EXTICR1_EXTI1_PE_Pos (6U)
+#define AFIO_EXTICR1_EXTI1_PE_Msk (0x1U << AFIO_EXTICR1_EXTI1_PE_Pos) /*!< 0x00000040 */
+#define AFIO_EXTICR1_EXTI1_PE AFIO_EXTICR1_EXTI1_PE_Msk /*!< PE[1] pin */
+#define AFIO_EXTICR1_EXTI1_PF_Pos (4U)
+#define AFIO_EXTICR1_EXTI1_PF_Msk (0x5U << AFIO_EXTICR1_EXTI1_PF_Pos) /*!< 0x00000050 */
+#define AFIO_EXTICR1_EXTI1_PF AFIO_EXTICR1_EXTI1_PF_Msk /*!< PF[1] pin */
+#define AFIO_EXTICR1_EXTI1_PG_Pos (5U)
+#define AFIO_EXTICR1_EXTI1_PG_Msk (0x3U << AFIO_EXTICR1_EXTI1_PG_Pos) /*!< 0x00000060 */
+#define AFIO_EXTICR1_EXTI1_PG AFIO_EXTICR1_EXTI1_PG_Msk /*!< PG[1] pin */
+
+/*!< EXTI2 configuration */
+#define AFIO_EXTICR1_EXTI2_PA ((uint32_t)0x00000000) /*!< PA[2] pin */
+#define AFIO_EXTICR1_EXTI2_PB_Pos (8U)
+#define AFIO_EXTICR1_EXTI2_PB_Msk (0x1U << AFIO_EXTICR1_EXTI2_PB_Pos) /*!< 0x00000100 */
+#define AFIO_EXTICR1_EXTI2_PB AFIO_EXTICR1_EXTI2_PB_Msk /*!< PB[2] pin */
+#define AFIO_EXTICR1_EXTI2_PC_Pos (9U)
+#define AFIO_EXTICR1_EXTI2_PC_Msk (0x1U << AFIO_EXTICR1_EXTI2_PC_Pos) /*!< 0x00000200 */
+#define AFIO_EXTICR1_EXTI2_PC AFIO_EXTICR1_EXTI2_PC_Msk /*!< PC[2] pin */
+#define AFIO_EXTICR1_EXTI2_PD_Pos (8U)
+#define AFIO_EXTICR1_EXTI2_PD_Msk (0x3U << AFIO_EXTICR1_EXTI2_PD_Pos) /*!< 0x00000300 */
+#define AFIO_EXTICR1_EXTI2_PD AFIO_EXTICR1_EXTI2_PD_Msk /*!< PD[2] pin */
+#define AFIO_EXTICR1_EXTI2_PE_Pos (10U)
+#define AFIO_EXTICR1_EXTI2_PE_Msk (0x1U << AFIO_EXTICR1_EXTI2_PE_Pos) /*!< 0x00000400 */
+#define AFIO_EXTICR1_EXTI2_PE AFIO_EXTICR1_EXTI2_PE_Msk /*!< PE[2] pin */
+#define AFIO_EXTICR1_EXTI2_PF_Pos (8U)
+#define AFIO_EXTICR1_EXTI2_PF_Msk (0x5U << AFIO_EXTICR1_EXTI2_PF_Pos) /*!< 0x00000500 */
+#define AFIO_EXTICR1_EXTI2_PF AFIO_EXTICR1_EXTI2_PF_Msk /*!< PF[2] pin */
+#define AFIO_EXTICR1_EXTI2_PG_Pos (9U)
+#define AFIO_EXTICR1_EXTI2_PG_Msk (0x3U << AFIO_EXTICR1_EXTI2_PG_Pos) /*!< 0x00000600 */
+#define AFIO_EXTICR1_EXTI2_PG AFIO_EXTICR1_EXTI2_PG_Msk /*!< PG[2] pin */
+
+/*!< EXTI3 configuration */
+#define AFIO_EXTICR1_EXTI3_PA ((uint32_t)0x00000000) /*!< PA[3] pin */
+#define AFIO_EXTICR1_EXTI3_PB_Pos (12U)
+#define AFIO_EXTICR1_EXTI3_PB_Msk (0x1U << AFIO_EXTICR1_EXTI3_PB_Pos) /*!< 0x00001000 */
+#define AFIO_EXTICR1_EXTI3_PB AFIO_EXTICR1_EXTI3_PB_Msk /*!< PB[3] pin */
+#define AFIO_EXTICR1_EXTI3_PC_Pos (13U)
+#define AFIO_EXTICR1_EXTI3_PC_Msk (0x1U << AFIO_EXTICR1_EXTI3_PC_Pos) /*!< 0x00002000 */
+#define AFIO_EXTICR1_EXTI3_PC AFIO_EXTICR1_EXTI3_PC_Msk /*!< PC[3] pin */
+#define AFIO_EXTICR1_EXTI3_PD_Pos (12U)
+#define AFIO_EXTICR1_EXTI3_PD_Msk (0x3U << AFIO_EXTICR1_EXTI3_PD_Pos) /*!< 0x00003000 */
+#define AFIO_EXTICR1_EXTI3_PD AFIO_EXTICR1_EXTI3_PD_Msk /*!< PD[3] pin */
+#define AFIO_EXTICR1_EXTI3_PE_Pos (14U)
+#define AFIO_EXTICR1_EXTI3_PE_Msk (0x1U << AFIO_EXTICR1_EXTI3_PE_Pos) /*!< 0x00004000 */
+#define AFIO_EXTICR1_EXTI3_PE AFIO_EXTICR1_EXTI3_PE_Msk /*!< PE[3] pin */
+#define AFIO_EXTICR1_EXTI3_PF_Pos (12U)
+#define AFIO_EXTICR1_EXTI3_PF_Msk (0x5U << AFIO_EXTICR1_EXTI3_PF_Pos) /*!< 0x00005000 */
+#define AFIO_EXTICR1_EXTI3_PF AFIO_EXTICR1_EXTI3_PF_Msk /*!< PF[3] pin */
+#define AFIO_EXTICR1_EXTI3_PG_Pos (13U)
+#define AFIO_EXTICR1_EXTI3_PG_Msk (0x3U << AFIO_EXTICR1_EXTI3_PG_Pos) /*!< 0x00006000 */
+#define AFIO_EXTICR1_EXTI3_PG AFIO_EXTICR1_EXTI3_PG_Msk /*!< PG[3] pin */
+
+/***************** Bit definition for AFIO_EXTICR2 register *****************/
+#define AFIO_EXTICR2_EXTI4_Pos (0U)
+#define AFIO_EXTICR2_EXTI4_Msk (0xFU << AFIO_EXTICR2_EXTI4_Pos) /*!< 0x0000000F */
+#define AFIO_EXTICR2_EXTI4 AFIO_EXTICR2_EXTI4_Msk /*!< EXTI 4 configuration */
+#define AFIO_EXTICR2_EXTI5_Pos (4U)
+#define AFIO_EXTICR2_EXTI5_Msk (0xFU << AFIO_EXTICR2_EXTI5_Pos) /*!< 0x000000F0 */
+#define AFIO_EXTICR2_EXTI5 AFIO_EXTICR2_EXTI5_Msk /*!< EXTI 5 configuration */
+#define AFIO_EXTICR2_EXTI6_Pos (8U)
+#define AFIO_EXTICR2_EXTI6_Msk (0xFU << AFIO_EXTICR2_EXTI6_Pos) /*!< 0x00000F00 */
+#define AFIO_EXTICR2_EXTI6 AFIO_EXTICR2_EXTI6_Msk /*!< EXTI 6 configuration */
+#define AFIO_EXTICR2_EXTI7_Pos (12U)
+#define AFIO_EXTICR2_EXTI7_Msk (0xFU << AFIO_EXTICR2_EXTI7_Pos) /*!< 0x0000F000 */
+#define AFIO_EXTICR2_EXTI7 AFIO_EXTICR2_EXTI7_Msk /*!< EXTI 7 configuration */
+
+/*!< EXTI4 configuration */
+#define AFIO_EXTICR2_EXTI4_PA ((uint32_t)0x00000000) /*!< PA[4] pin */
+#define AFIO_EXTICR2_EXTI4_PB_Pos (0U)
+#define AFIO_EXTICR2_EXTI4_PB_Msk (0x1U << AFIO_EXTICR2_EXTI4_PB_Pos) /*!< 0x00000001 */
+#define AFIO_EXTICR2_EXTI4_PB AFIO_EXTICR2_EXTI4_PB_Msk /*!< PB[4] pin */
+#define AFIO_EXTICR2_EXTI4_PC_Pos (1U)
+#define AFIO_EXTICR2_EXTI4_PC_Msk (0x1U << AFIO_EXTICR2_EXTI4_PC_Pos) /*!< 0x00000002 */
+#define AFIO_EXTICR2_EXTI4_PC AFIO_EXTICR2_EXTI4_PC_Msk /*!< PC[4] pin */
+#define AFIO_EXTICR2_EXTI4_PD_Pos (0U)
+#define AFIO_EXTICR2_EXTI4_PD_Msk (0x3U << AFIO_EXTICR2_EXTI4_PD_Pos) /*!< 0x00000003 */
+#define AFIO_EXTICR2_EXTI4_PD AFIO_EXTICR2_EXTI4_PD_Msk /*!< PD[4] pin */
+#define AFIO_EXTICR2_EXTI4_PE_Pos (2U)
+#define AFIO_EXTICR2_EXTI4_PE_Msk (0x1U << AFIO_EXTICR2_EXTI4_PE_Pos) /*!< 0x00000004 */
+#define AFIO_EXTICR2_EXTI4_PE AFIO_EXTICR2_EXTI4_PE_Msk /*!< PE[4] pin */
+#define AFIO_EXTICR2_EXTI4_PF_Pos (0U)
+#define AFIO_EXTICR2_EXTI4_PF_Msk (0x5U << AFIO_EXTICR2_EXTI4_PF_Pos) /*!< 0x00000005 */
+#define AFIO_EXTICR2_EXTI4_PF AFIO_EXTICR2_EXTI4_PF_Msk /*!< PF[4] pin */
+#define AFIO_EXTICR2_EXTI4_PG_Pos (1U)
+#define AFIO_EXTICR2_EXTI4_PG_Msk (0x3U << AFIO_EXTICR2_EXTI4_PG_Pos) /*!< 0x00000006 */
+#define AFIO_EXTICR2_EXTI4_PG AFIO_EXTICR2_EXTI4_PG_Msk /*!< PG[4] pin */
+
+/* EXTI5 configuration */
+#define AFIO_EXTICR2_EXTI5_PA ((uint32_t)0x00000000) /*!< PA[5] pin */
+#define AFIO_EXTICR2_EXTI5_PB_Pos (4U)
+#define AFIO_EXTICR2_EXTI5_PB_Msk (0x1U << AFIO_EXTICR2_EXTI5_PB_Pos) /*!< 0x00000010 */
+#define AFIO_EXTICR2_EXTI5_PB AFIO_EXTICR2_EXTI5_PB_Msk /*!< PB[5] pin */
+#define AFIO_EXTICR2_EXTI5_PC_Pos (5U)
+#define AFIO_EXTICR2_EXTI5_PC_Msk (0x1U << AFIO_EXTICR2_EXTI5_PC_Pos) /*!< 0x00000020 */
+#define AFIO_EXTICR2_EXTI5_PC AFIO_EXTICR2_EXTI5_PC_Msk /*!< PC[5] pin */
+#define AFIO_EXTICR2_EXTI5_PD_Pos (4U)
+#define AFIO_EXTICR2_EXTI5_PD_Msk (0x3U << AFIO_EXTICR2_EXTI5_PD_Pos) /*!< 0x00000030 */
+#define AFIO_EXTICR2_EXTI5_PD AFIO_EXTICR2_EXTI5_PD_Msk /*!< PD[5] pin */
+#define AFIO_EXTICR2_EXTI5_PE_Pos (6U)
+#define AFIO_EXTICR2_EXTI5_PE_Msk (0x1U << AFIO_EXTICR2_EXTI5_PE_Pos) /*!< 0x00000040 */
+#define AFIO_EXTICR2_EXTI5_PE AFIO_EXTICR2_EXTI5_PE_Msk /*!< PE[5] pin */
+#define AFIO_EXTICR2_EXTI5_PF_Pos (4U)
+#define AFIO_EXTICR2_EXTI5_PF_Msk (0x5U << AFIO_EXTICR2_EXTI5_PF_Pos) /*!< 0x00000050 */
+#define AFIO_EXTICR2_EXTI5_PF AFIO_EXTICR2_EXTI5_PF_Msk /*!< PF[5] pin */
+#define AFIO_EXTICR2_EXTI5_PG_Pos (5U)
+#define AFIO_EXTICR2_EXTI5_PG_Msk (0x3U << AFIO_EXTICR2_EXTI5_PG_Pos) /*!< 0x00000060 */
+#define AFIO_EXTICR2_EXTI5_PG AFIO_EXTICR2_EXTI5_PG_Msk /*!< PG[5] pin */
+
+/*!< EXTI6 configuration */
+#define AFIO_EXTICR2_EXTI6_PA ((uint32_t)0x00000000) /*!< PA[6] pin */
+#define AFIO_EXTICR2_EXTI6_PB_Pos (8U)
+#define AFIO_EXTICR2_EXTI6_PB_Msk (0x1U << AFIO_EXTICR2_EXTI6_PB_Pos) /*!< 0x00000100 */
+#define AFIO_EXTICR2_EXTI6_PB AFIO_EXTICR2_EXTI6_PB_Msk /*!< PB[6] pin */
+#define AFIO_EXTICR2_EXTI6_PC_Pos (9U)
+#define AFIO_EXTICR2_EXTI6_PC_Msk (0x1U << AFIO_EXTICR2_EXTI6_PC_Pos) /*!< 0x00000200 */
+#define AFIO_EXTICR2_EXTI6_PC AFIO_EXTICR2_EXTI6_PC_Msk /*!< PC[6] pin */
+#define AFIO_EXTICR2_EXTI6_PD_Pos (8U)
+#define AFIO_EXTICR2_EXTI6_PD_Msk (0x3U << AFIO_EXTICR2_EXTI6_PD_Pos) /*!< 0x00000300 */
+#define AFIO_EXTICR2_EXTI6_PD AFIO_EXTICR2_EXTI6_PD_Msk /*!< PD[6] pin */
+#define AFIO_EXTICR2_EXTI6_PE_Pos (10U)
+#define AFIO_EXTICR2_EXTI6_PE_Msk (0x1U << AFIO_EXTICR2_EXTI6_PE_Pos) /*!< 0x00000400 */
+#define AFIO_EXTICR2_EXTI6_PE AFIO_EXTICR2_EXTI6_PE_Msk /*!< PE[6] pin */
+#define AFIO_EXTICR2_EXTI6_PF_Pos (8U)
+#define AFIO_EXTICR2_EXTI6_PF_Msk (0x5U << AFIO_EXTICR2_EXTI6_PF_Pos) /*!< 0x00000500 */
+#define AFIO_EXTICR2_EXTI6_PF AFIO_EXTICR2_EXTI6_PF_Msk /*!< PF[6] pin */
+#define AFIO_EXTICR2_EXTI6_PG_Pos (9U)
+#define AFIO_EXTICR2_EXTI6_PG_Msk (0x3U << AFIO_EXTICR2_EXTI6_PG_Pos) /*!< 0x00000600 */
+#define AFIO_EXTICR2_EXTI6_PG AFIO_EXTICR2_EXTI6_PG_Msk /*!< PG[6] pin */
+
+/*!< EXTI7 configuration */
+#define AFIO_EXTICR2_EXTI7_PA ((uint32_t)0x00000000) /*!< PA[7] pin */
+#define AFIO_EXTICR2_EXTI7_PB_Pos (12U)
+#define AFIO_EXTICR2_EXTI7_PB_Msk (0x1U << AFIO_EXTICR2_EXTI7_PB_Pos) /*!< 0x00001000 */
+#define AFIO_EXTICR2_EXTI7_PB AFIO_EXTICR2_EXTI7_PB_Msk /*!< PB[7] pin */
+#define AFIO_EXTICR2_EXTI7_PC_Pos (13U)
+#define AFIO_EXTICR2_EXTI7_PC_Msk (0x1U << AFIO_EXTICR2_EXTI7_PC_Pos) /*!< 0x00002000 */
+#define AFIO_EXTICR2_EXTI7_PC AFIO_EXTICR2_EXTI7_PC_Msk /*!< PC[7] pin */
+#define AFIO_EXTICR2_EXTI7_PD_Pos (12U)
+#define AFIO_EXTICR2_EXTI7_PD_Msk (0x3U << AFIO_EXTICR2_EXTI7_PD_Pos) /*!< 0x00003000 */
+#define AFIO_EXTICR2_EXTI7_PD AFIO_EXTICR2_EXTI7_PD_Msk /*!< PD[7] pin */
+#define AFIO_EXTICR2_EXTI7_PE_Pos (14U)
+#define AFIO_EXTICR2_EXTI7_PE_Msk (0x1U << AFIO_EXTICR2_EXTI7_PE_Pos) /*!< 0x00004000 */
+#define AFIO_EXTICR2_EXTI7_PE AFIO_EXTICR2_EXTI7_PE_Msk /*!< PE[7] pin */
+#define AFIO_EXTICR2_EXTI7_PF_Pos (12U)
+#define AFIO_EXTICR2_EXTI7_PF_Msk (0x5U << AFIO_EXTICR2_EXTI7_PF_Pos) /*!< 0x00005000 */
+#define AFIO_EXTICR2_EXTI7_PF AFIO_EXTICR2_EXTI7_PF_Msk /*!< PF[7] pin */
+#define AFIO_EXTICR2_EXTI7_PG_Pos (13U)
+#define AFIO_EXTICR2_EXTI7_PG_Msk (0x3U << AFIO_EXTICR2_EXTI7_PG_Pos) /*!< 0x00006000 */
+#define AFIO_EXTICR2_EXTI7_PG AFIO_EXTICR2_EXTI7_PG_Msk /*!< PG[7] pin */
+
+/***************** Bit definition for AFIO_EXTICR3 register *****************/
+#define AFIO_EXTICR3_EXTI8_Pos (0U)
+#define AFIO_EXTICR3_EXTI8_Msk (0xFU << AFIO_EXTICR3_EXTI8_Pos) /*!< 0x0000000F */
+#define AFIO_EXTICR3_EXTI8 AFIO_EXTICR3_EXTI8_Msk /*!< EXTI 8 configuration */
+#define AFIO_EXTICR3_EXTI9_Pos (4U)
+#define AFIO_EXTICR3_EXTI9_Msk (0xFU << AFIO_EXTICR3_EXTI9_Pos) /*!< 0x000000F0 */
+#define AFIO_EXTICR3_EXTI9 AFIO_EXTICR3_EXTI9_Msk /*!< EXTI 9 configuration */
+#define AFIO_EXTICR3_EXTI10_Pos (8U)
+#define AFIO_EXTICR3_EXTI10_Msk (0xFU << AFIO_EXTICR3_EXTI10_Pos) /*!< 0x00000F00 */
+#define AFIO_EXTICR3_EXTI10 AFIO_EXTICR3_EXTI10_Msk /*!< EXTI 10 configuration */
+#define AFIO_EXTICR3_EXTI11_Pos (12U)
+#define AFIO_EXTICR3_EXTI11_Msk (0xFU << AFIO_EXTICR3_EXTI11_Pos) /*!< 0x0000F000 */
+#define AFIO_EXTICR3_EXTI11 AFIO_EXTICR3_EXTI11_Msk /*!< EXTI 11 configuration */
+
+/*!< EXTI8 configuration */
+#define AFIO_EXTICR3_EXTI8_PA ((uint32_t)0x00000000) /*!< PA[8] pin */
+#define AFIO_EXTICR3_EXTI8_PB_Pos (0U)
+#define AFIO_EXTICR3_EXTI8_PB_Msk (0x1U << AFIO_EXTICR3_EXTI8_PB_Pos) /*!< 0x00000001 */
+#define AFIO_EXTICR3_EXTI8_PB AFIO_EXTICR3_EXTI8_PB_Msk /*!< PB[8] pin */
+#define AFIO_EXTICR3_EXTI8_PC_Pos (1U)
+#define AFIO_EXTICR3_EXTI8_PC_Msk (0x1U << AFIO_EXTICR3_EXTI8_PC_Pos) /*!< 0x00000002 */
+#define AFIO_EXTICR3_EXTI8_PC AFIO_EXTICR3_EXTI8_PC_Msk /*!< PC[8] pin */
+#define AFIO_EXTICR3_EXTI8_PD_Pos (0U)
+#define AFIO_EXTICR3_EXTI8_PD_Msk (0x3U << AFIO_EXTICR3_EXTI8_PD_Pos) /*!< 0x00000003 */
+#define AFIO_EXTICR3_EXTI8_PD AFIO_EXTICR3_EXTI8_PD_Msk /*!< PD[8] pin */
+#define AFIO_EXTICR3_EXTI8_PE_Pos (2U)
+#define AFIO_EXTICR3_EXTI8_PE_Msk (0x1U << AFIO_EXTICR3_EXTI8_PE_Pos) /*!< 0x00000004 */
+#define AFIO_EXTICR3_EXTI8_PE AFIO_EXTICR3_EXTI8_PE_Msk /*!< PE[8] pin */
+#define AFIO_EXTICR3_EXTI8_PF_Pos (0U)
+#define AFIO_EXTICR3_EXTI8_PF_Msk (0x5U << AFIO_EXTICR3_EXTI8_PF_Pos) /*!< 0x00000005 */
+#define AFIO_EXTICR3_EXTI8_PF AFIO_EXTICR3_EXTI8_PF_Msk /*!< PF[8] pin */
+#define AFIO_EXTICR3_EXTI8_PG_Pos (1U)
+#define AFIO_EXTICR3_EXTI8_PG_Msk (0x3U << AFIO_EXTICR3_EXTI8_PG_Pos) /*!< 0x00000006 */
+#define AFIO_EXTICR3_EXTI8_PG AFIO_EXTICR3_EXTI8_PG_Msk /*!< PG[8] pin */
+
+/*!< EXTI9 configuration */
+#define AFIO_EXTICR3_EXTI9_PA ((uint32_t)0x00000000) /*!< PA[9] pin */
+#define AFIO_EXTICR3_EXTI9_PB_Pos (4U)
+#define AFIO_EXTICR3_EXTI9_PB_Msk (0x1U << AFIO_EXTICR3_EXTI9_PB_Pos) /*!< 0x00000010 */
+#define AFIO_EXTICR3_EXTI9_PB AFIO_EXTICR3_EXTI9_PB_Msk /*!< PB[9] pin */
+#define AFIO_EXTICR3_EXTI9_PC_Pos (5U)
+#define AFIO_EXTICR3_EXTI9_PC_Msk (0x1U << AFIO_EXTICR3_EXTI9_PC_Pos) /*!< 0x00000020 */
+#define AFIO_EXTICR3_EXTI9_PC AFIO_EXTICR3_EXTI9_PC_Msk /*!< PC[9] pin */
+#define AFIO_EXTICR3_EXTI9_PD_Pos (4U)
+#define AFIO_EXTICR3_EXTI9_PD_Msk (0x3U << AFIO_EXTICR3_EXTI9_PD_Pos) /*!< 0x00000030 */
+#define AFIO_EXTICR3_EXTI9_PD AFIO_EXTICR3_EXTI9_PD_Msk /*!< PD[9] pin */
+#define AFIO_EXTICR3_EXTI9_PE_Pos (6U)
+#define AFIO_EXTICR3_EXTI9_PE_Msk (0x1U << AFIO_EXTICR3_EXTI9_PE_Pos) /*!< 0x00000040 */
+#define AFIO_EXTICR3_EXTI9_PE AFIO_EXTICR3_EXTI9_PE_Msk /*!< PE[9] pin */
+#define AFIO_EXTICR3_EXTI9_PF_Pos (4U)
+#define AFIO_EXTICR3_EXTI9_PF_Msk (0x5U << AFIO_EXTICR3_EXTI9_PF_Pos) /*!< 0x00000050 */
+#define AFIO_EXTICR3_EXTI9_PF AFIO_EXTICR3_EXTI9_PF_Msk /*!< PF[9] pin */
+#define AFIO_EXTICR3_EXTI9_PG_Pos (5U)
+#define AFIO_EXTICR3_EXTI9_PG_Msk (0x3U << AFIO_EXTICR3_EXTI9_PG_Pos) /*!< 0x00000060 */
+#define AFIO_EXTICR3_EXTI9_PG AFIO_EXTICR3_EXTI9_PG_Msk /*!< PG[9] pin */
+
+/*!< EXTI10 configuration */
+#define AFIO_EXTICR3_EXTI10_PA ((uint32_t)0x00000000) /*!< PA[10] pin */
+#define AFIO_EXTICR3_EXTI10_PB_Pos (8U)
+#define AFIO_EXTICR3_EXTI10_PB_Msk (0x1U << AFIO_EXTICR3_EXTI10_PB_Pos) /*!< 0x00000100 */
+#define AFIO_EXTICR3_EXTI10_PB AFIO_EXTICR3_EXTI10_PB_Msk /*!< PB[10] pin */
+#define AFIO_EXTICR3_EXTI10_PC_Pos (9U)
+#define AFIO_EXTICR3_EXTI10_PC_Msk (0x1U << AFIO_EXTICR3_EXTI10_PC_Pos) /*!< 0x00000200 */
+#define AFIO_EXTICR3_EXTI10_PC AFIO_EXTICR3_EXTI10_PC_Msk /*!< PC[10] pin */
+#define AFIO_EXTICR3_EXTI10_PD_Pos (8U)
+#define AFIO_EXTICR3_EXTI10_PD_Msk (0x3U << AFIO_EXTICR3_EXTI10_PD_Pos) /*!< 0x00000300 */
+#define AFIO_EXTICR3_EXTI10_PD AFIO_EXTICR3_EXTI10_PD_Msk /*!< PD[10] pin */
+#define AFIO_EXTICR3_EXTI10_PE_Pos (10U)
+#define AFIO_EXTICR3_EXTI10_PE_Msk (0x1U << AFIO_EXTICR3_EXTI10_PE_Pos) /*!< 0x00000400 */
+#define AFIO_EXTICR3_EXTI10_PE AFIO_EXTICR3_EXTI10_PE_Msk /*!< PE[10] pin */
+#define AFIO_EXTICR3_EXTI10_PF_Pos (8U)
+#define AFIO_EXTICR3_EXTI10_PF_Msk (0x5U << AFIO_EXTICR3_EXTI10_PF_Pos) /*!< 0x00000500 */
+#define AFIO_EXTICR3_EXTI10_PF AFIO_EXTICR3_EXTI10_PF_Msk /*!< PF[10] pin */
+#define AFIO_EXTICR3_EXTI10_PG_Pos (9U)
+#define AFIO_EXTICR3_EXTI10_PG_Msk (0x3U << AFIO_EXTICR3_EXTI10_PG_Pos) /*!< 0x00000600 */
+#define AFIO_EXTICR3_EXTI10_PG AFIO_EXTICR3_EXTI10_PG_Msk /*!< PG[10] pin */
+
+/*!< EXTI11 configuration */
+#define AFIO_EXTICR3_EXTI11_PA ((uint32_t)0x00000000) /*!< PA[11] pin */
+#define AFIO_EXTICR3_EXTI11_PB_Pos (12U)
+#define AFIO_EXTICR3_EXTI11_PB_Msk (0x1U << AFIO_EXTICR3_EXTI11_PB_Pos) /*!< 0x00001000 */
+#define AFIO_EXTICR3_EXTI11_PB AFIO_EXTICR3_EXTI11_PB_Msk /*!< PB[11] pin */
+#define AFIO_EXTICR3_EXTI11_PC_Pos (13U)
+#define AFIO_EXTICR3_EXTI11_PC_Msk (0x1U << AFIO_EXTICR3_EXTI11_PC_Pos) /*!< 0x00002000 */
+#define AFIO_EXTICR3_EXTI11_PC AFIO_EXTICR3_EXTI11_PC_Msk /*!< PC[11] pin */
+#define AFIO_EXTICR3_EXTI11_PD_Pos (12U)
+#define AFIO_EXTICR3_EXTI11_PD_Msk (0x3U << AFIO_EXTICR3_EXTI11_PD_Pos) /*!< 0x00003000 */
+#define AFIO_EXTICR3_EXTI11_PD AFIO_EXTICR3_EXTI11_PD_Msk /*!< PD[11] pin */
+#define AFIO_EXTICR3_EXTI11_PE_Pos (14U)
+#define AFIO_EXTICR3_EXTI11_PE_Msk (0x1U << AFIO_EXTICR3_EXTI11_PE_Pos) /*!< 0x00004000 */
+#define AFIO_EXTICR3_EXTI11_PE AFIO_EXTICR3_EXTI11_PE_Msk /*!< PE[11] pin */
+#define AFIO_EXTICR3_EXTI11_PF_Pos (12U)
+#define AFIO_EXTICR3_EXTI11_PF_Msk (0x5U << AFIO_EXTICR3_EXTI11_PF_Pos) /*!< 0x00005000 */
+#define AFIO_EXTICR3_EXTI11_PF AFIO_EXTICR3_EXTI11_PF_Msk /*!< PF[11] pin */
+#define AFIO_EXTICR3_EXTI11_PG_Pos (13U)
+#define AFIO_EXTICR3_EXTI11_PG_Msk (0x3U << AFIO_EXTICR3_EXTI11_PG_Pos) /*!< 0x00006000 */
+#define AFIO_EXTICR3_EXTI11_PG AFIO_EXTICR3_EXTI11_PG_Msk /*!< PG[11] pin */
+
+/***************** Bit definition for AFIO_EXTICR4 register *****************/
+#define AFIO_EXTICR4_EXTI12_Pos (0U)
+#define AFIO_EXTICR4_EXTI12_Msk (0xFU << AFIO_EXTICR4_EXTI12_Pos) /*!< 0x0000000F */
+#define AFIO_EXTICR4_EXTI12 AFIO_EXTICR4_EXTI12_Msk /*!< EXTI 12 configuration */
+#define AFIO_EXTICR4_EXTI13_Pos (4U)
+#define AFIO_EXTICR4_EXTI13_Msk (0xFU << AFIO_EXTICR4_EXTI13_Pos) /*!< 0x000000F0 */
+#define AFIO_EXTICR4_EXTI13 AFIO_EXTICR4_EXTI13_Msk /*!< EXTI 13 configuration */
+#define AFIO_EXTICR4_EXTI14_Pos (8U)
+#define AFIO_EXTICR4_EXTI14_Msk (0xFU << AFIO_EXTICR4_EXTI14_Pos) /*!< 0x00000F00 */
+#define AFIO_EXTICR4_EXTI14 AFIO_EXTICR4_EXTI14_Msk /*!< EXTI 14 configuration */
+#define AFIO_EXTICR4_EXTI15_Pos (12U)
+#define AFIO_EXTICR4_EXTI15_Msk (0xFU << AFIO_EXTICR4_EXTI15_Pos) /*!< 0x0000F000 */
+#define AFIO_EXTICR4_EXTI15 AFIO_EXTICR4_EXTI15_Msk /*!< EXTI 15 configuration */
+
+/* EXTI12 configuration */
+#define AFIO_EXTICR4_EXTI12_PA ((uint32_t)0x00000000) /*!< PA[12] pin */
+#define AFIO_EXTICR4_EXTI12_PB_Pos (0U)
+#define AFIO_EXTICR4_EXTI12_PB_Msk (0x1U << AFIO_EXTICR4_EXTI12_PB_Pos) /*!< 0x00000001 */
+#define AFIO_EXTICR4_EXTI12_PB AFIO_EXTICR4_EXTI12_PB_Msk /*!< PB[12] pin */
+#define AFIO_EXTICR4_EXTI12_PC_Pos (1U)
+#define AFIO_EXTICR4_EXTI12_PC_Msk (0x1U << AFIO_EXTICR4_EXTI12_PC_Pos) /*!< 0x00000002 */
+#define AFIO_EXTICR4_EXTI12_PC AFIO_EXTICR4_EXTI12_PC_Msk /*!< PC[12] pin */
+#define AFIO_EXTICR4_EXTI12_PD_Pos (0U)
+#define AFIO_EXTICR4_EXTI12_PD_Msk (0x3U << AFIO_EXTICR4_EXTI12_PD_Pos) /*!< 0x00000003 */
+#define AFIO_EXTICR4_EXTI12_PD AFIO_EXTICR4_EXTI12_PD_Msk /*!< PD[12] pin */
+#define AFIO_EXTICR4_EXTI12_PE_Pos (2U)
+#define AFIO_EXTICR4_EXTI12_PE_Msk (0x1U << AFIO_EXTICR4_EXTI12_PE_Pos) /*!< 0x00000004 */
+#define AFIO_EXTICR4_EXTI12_PE AFIO_EXTICR4_EXTI12_PE_Msk /*!< PE[12] pin */
+#define AFIO_EXTICR4_EXTI12_PF_Pos (0U)
+#define AFIO_EXTICR4_EXTI12_PF_Msk (0x5U << AFIO_EXTICR4_EXTI12_PF_Pos) /*!< 0x00000005 */
+#define AFIO_EXTICR4_EXTI12_PF AFIO_EXTICR4_EXTI12_PF_Msk /*!< PF[12] pin */
+#define AFIO_EXTICR4_EXTI12_PG_Pos (1U)
+#define AFIO_EXTICR4_EXTI12_PG_Msk (0x3U << AFIO_EXTICR4_EXTI12_PG_Pos) /*!< 0x00000006 */
+#define AFIO_EXTICR4_EXTI12_PG AFIO_EXTICR4_EXTI12_PG_Msk /*!< PG[12] pin */
+
+/* EXTI13 configuration */
+#define AFIO_EXTICR4_EXTI13_PA ((uint32_t)0x00000000) /*!< PA[13] pin */
+#define AFIO_EXTICR4_EXTI13_PB_Pos (4U)
+#define AFIO_EXTICR4_EXTI13_PB_Msk (0x1U << AFIO_EXTICR4_EXTI13_PB_Pos) /*!< 0x00000010 */
+#define AFIO_EXTICR4_EXTI13_PB AFIO_EXTICR4_EXTI13_PB_Msk /*!< PB[13] pin */
+#define AFIO_EXTICR4_EXTI13_PC_Pos (5U)
+#define AFIO_EXTICR4_EXTI13_PC_Msk (0x1U << AFIO_EXTICR4_EXTI13_PC_Pos) /*!< 0x00000020 */
+#define AFIO_EXTICR4_EXTI13_PC AFIO_EXTICR4_EXTI13_PC_Msk /*!< PC[13] pin */
+#define AFIO_EXTICR4_EXTI13_PD_Pos (4U)
+#define AFIO_EXTICR4_EXTI13_PD_Msk (0x3U << AFIO_EXTICR4_EXTI13_PD_Pos) /*!< 0x00000030 */
+#define AFIO_EXTICR4_EXTI13_PD AFIO_EXTICR4_EXTI13_PD_Msk /*!< PD[13] pin */
+#define AFIO_EXTICR4_EXTI13_PE_Pos (6U)
+#define AFIO_EXTICR4_EXTI13_PE_Msk (0x1U << AFIO_EXTICR4_EXTI13_PE_Pos) /*!< 0x00000040 */
+#define AFIO_EXTICR4_EXTI13_PE AFIO_EXTICR4_EXTI13_PE_Msk /*!< PE[13] pin */
+#define AFIO_EXTICR4_EXTI13_PF_Pos (4U)
+#define AFIO_EXTICR4_EXTI13_PF_Msk (0x5U << AFIO_EXTICR4_EXTI13_PF_Pos) /*!< 0x00000050 */
+#define AFIO_EXTICR4_EXTI13_PF AFIO_EXTICR4_EXTI13_PF_Msk /*!< PF[13] pin */
+#define AFIO_EXTICR4_EXTI13_PG_Pos (5U)
+#define AFIO_EXTICR4_EXTI13_PG_Msk (0x3U << AFIO_EXTICR4_EXTI13_PG_Pos) /*!< 0x00000060 */
+#define AFIO_EXTICR4_EXTI13_PG AFIO_EXTICR4_EXTI13_PG_Msk /*!< PG[13] pin */
+
+/*!< EXTI14 configuration */
+#define AFIO_EXTICR4_EXTI14_PA ((uint32_t)0x00000000) /*!< PA[14] pin */
+#define AFIO_EXTICR4_EXTI14_PB_Pos (8U)
+#define AFIO_EXTICR4_EXTI14_PB_Msk (0x1U << AFIO_EXTICR4_EXTI14_PB_Pos) /*!< 0x00000100 */
+#define AFIO_EXTICR4_EXTI14_PB AFIO_EXTICR4_EXTI14_PB_Msk /*!< PB[14] pin */
+#define AFIO_EXTICR4_EXTI14_PC_Pos (9U)
+#define AFIO_EXTICR4_EXTI14_PC_Msk (0x1U << AFIO_EXTICR4_EXTI14_PC_Pos) /*!< 0x00000200 */
+#define AFIO_EXTICR4_EXTI14_PC AFIO_EXTICR4_EXTI14_PC_Msk /*!< PC[14] pin */
+#define AFIO_EXTICR4_EXTI14_PD_Pos (8U)
+#define AFIO_EXTICR4_EXTI14_PD_Msk (0x3U << AFIO_EXTICR4_EXTI14_PD_Pos) /*!< 0x00000300 */
+#define AFIO_EXTICR4_EXTI14_PD AFIO_EXTICR4_EXTI14_PD_Msk /*!< PD[14] pin */
+#define AFIO_EXTICR4_EXTI14_PE_Pos (10U)
+#define AFIO_EXTICR4_EXTI14_PE_Msk (0x1U << AFIO_EXTICR4_EXTI14_PE_Pos) /*!< 0x00000400 */
+#define AFIO_EXTICR4_EXTI14_PE AFIO_EXTICR4_EXTI14_PE_Msk /*!< PE[14] pin */
+#define AFIO_EXTICR4_EXTI14_PF_Pos (8U)
+#define AFIO_EXTICR4_EXTI14_PF_Msk (0x5U << AFIO_EXTICR4_EXTI14_PF_Pos) /*!< 0x00000500 */
+#define AFIO_EXTICR4_EXTI14_PF AFIO_EXTICR4_EXTI14_PF_Msk /*!< PF[14] pin */
+#define AFIO_EXTICR4_EXTI14_PG_Pos (9U)
+#define AFIO_EXTICR4_EXTI14_PG_Msk (0x3U << AFIO_EXTICR4_EXTI14_PG_Pos) /*!< 0x00000600 */
+#define AFIO_EXTICR4_EXTI14_PG AFIO_EXTICR4_EXTI14_PG_Msk /*!< PG[14] pin */
+
+/*!< EXTI15 configuration */
+#define AFIO_EXTICR4_EXTI15_PA ((uint32_t)0x00000000) /*!< PA[15] pin */
+#define AFIO_EXTICR4_EXTI15_PB_Pos (12U)
+#define AFIO_EXTICR4_EXTI15_PB_Msk (0x1U << AFIO_EXTICR4_EXTI15_PB_Pos) /*!< 0x00001000 */
+#define AFIO_EXTICR4_EXTI15_PB AFIO_EXTICR4_EXTI15_PB_Msk /*!< PB[15] pin */
+#define AFIO_EXTICR4_EXTI15_PC_Pos (13U)
+#define AFIO_EXTICR4_EXTI15_PC_Msk (0x1U << AFIO_EXTICR4_EXTI15_PC_Pos) /*!< 0x00002000 */
+#define AFIO_EXTICR4_EXTI15_PC AFIO_EXTICR4_EXTI15_PC_Msk /*!< PC[15] pin */
+#define AFIO_EXTICR4_EXTI15_PD_Pos (12U)
+#define AFIO_EXTICR4_EXTI15_PD_Msk (0x3U << AFIO_EXTICR4_EXTI15_PD_Pos) /*!< 0x00003000 */
+#define AFIO_EXTICR4_EXTI15_PD AFIO_EXTICR4_EXTI15_PD_Msk /*!< PD[15] pin */
+#define AFIO_EXTICR4_EXTI15_PE_Pos (14U)
+#define AFIO_EXTICR4_EXTI15_PE_Msk (0x1U << AFIO_EXTICR4_EXTI15_PE_Pos) /*!< 0x00004000 */
+#define AFIO_EXTICR4_EXTI15_PE AFIO_EXTICR4_EXTI15_PE_Msk /*!< PE[15] pin */
+#define AFIO_EXTICR4_EXTI15_PF_Pos (12U)
+#define AFIO_EXTICR4_EXTI15_PF_Msk (0x5U << AFIO_EXTICR4_EXTI15_PF_Pos) /*!< 0x00005000 */
+#define AFIO_EXTICR4_EXTI15_PF AFIO_EXTICR4_EXTI15_PF_Msk /*!< PF[15] pin */
+#define AFIO_EXTICR4_EXTI15_PG_Pos (13U)
+#define AFIO_EXTICR4_EXTI15_PG_Msk (0x3U << AFIO_EXTICR4_EXTI15_PG_Pos) /*!< 0x00006000 */
+#define AFIO_EXTICR4_EXTI15_PG AFIO_EXTICR4_EXTI15_PG_Msk /*!< PG[15] pin */
+
+/****************** Bit definition for AFIO_MAPR2 register ******************/
+#define AFIO_MAPR2_TIM15_REMAP_Pos (0U)
+#define AFIO_MAPR2_TIM15_REMAP_Msk (0x1U << AFIO_MAPR2_TIM15_REMAP_Pos) /*!< 0x00000001 */
+#define AFIO_MAPR2_TIM15_REMAP AFIO_MAPR2_TIM15_REMAP_Msk /*!< TIM15 remapping */
+#define AFIO_MAPR2_TIM16_REMAP_Pos (1U)
+#define AFIO_MAPR2_TIM16_REMAP_Msk (0x1U << AFIO_MAPR2_TIM16_REMAP_Pos) /*!< 0x00000002 */
+#define AFIO_MAPR2_TIM16_REMAP AFIO_MAPR2_TIM16_REMAP_Msk /*!< TIM16 remapping */
+#define AFIO_MAPR2_TIM17_REMAP_Pos (2U)
+#define AFIO_MAPR2_TIM17_REMAP_Msk (0x1U << AFIO_MAPR2_TIM17_REMAP_Pos) /*!< 0x00000004 */
+#define AFIO_MAPR2_TIM17_REMAP AFIO_MAPR2_TIM17_REMAP_Msk /*!< TIM17 remapping */
+#define AFIO_MAPR2_CEC_REMAP_Pos (3U)
+#define AFIO_MAPR2_CEC_REMAP_Msk (0x1U << AFIO_MAPR2_CEC_REMAP_Pos) /*!< 0x00000008 */
+#define AFIO_MAPR2_CEC_REMAP AFIO_MAPR2_CEC_REMAP_Msk /*!< CEC remapping */
+#define AFIO_MAPR2_TIM1_DMA_REMAP_Pos (4U)
+#define AFIO_MAPR2_TIM1_DMA_REMAP_Msk (0x1U << AFIO_MAPR2_TIM1_DMA_REMAP_Pos) /*!< 0x00000010 */
+#define AFIO_MAPR2_TIM1_DMA_REMAP AFIO_MAPR2_TIM1_DMA_REMAP_Msk /*!< TIM1_DMA remapping */
+
+#define AFIO_MAPR2_TIM67_DAC_DMA_REMAP_Pos (11U)
+#define AFIO_MAPR2_TIM67_DAC_DMA_REMAP_Msk (0x1U << AFIO_MAPR2_TIM67_DAC_DMA_REMAP_Pos) /*!< 0x00000800 */
+#define AFIO_MAPR2_TIM67_DAC_DMA_REMAP AFIO_MAPR2_TIM67_DAC_DMA_REMAP_Msk /*!< TIM6/TIM7 and DAC DMA remapping */
+
+
+/******************************************************************************/
+/* */
+/* SystemTick */
+/* */
+/******************************************************************************/
+
+/***************** Bit definition for SysTick_CTRL register *****************/
+#define SysTick_CTRL_ENABLE ((uint32_t)0x00000001) /*!< Counter enable */
+#define SysTick_CTRL_TICKINT ((uint32_t)0x00000002) /*!< Counting down to 0 pends the SysTick handler */
+#define SysTick_CTRL_CLKSOURCE ((uint32_t)0x00000004) /*!< Clock source */
+#define SysTick_CTRL_COUNTFLAG ((uint32_t)0x00010000) /*!< Count Flag */
+
+/***************** Bit definition for SysTick_LOAD register *****************/
+#define SysTick_LOAD_RELOAD ((uint32_t)0x00FFFFFF) /*!< Value to load into the SysTick Current Value Register when the counter reaches 0 */
+
+/***************** Bit definition for SysTick_VAL register ******************/
+#define SysTick_VAL_CURRENT ((uint32_t)0x00FFFFFF) /*!< Current value at the time the register is accessed */
+
+/***************** Bit definition for SysTick_CALIB register ****************/
+#define SysTick_CALIB_TENMS ((uint32_t)0x00FFFFFF) /*!< Reload value to use for 10ms timing */
+#define SysTick_CALIB_SKEW ((uint32_t)0x40000000) /*!< Calibration value is not exactly 10 ms */
+#define SysTick_CALIB_NOREF ((uint32_t)0x80000000) /*!< The reference clock is not provided */
+
+/******************************************************************************/
+/* */
+/* Nested Vectored Interrupt Controller */
+/* */
+/******************************************************************************/
+
+/****************** Bit definition for NVIC_ISER register *******************/
+#define NVIC_ISER_SETENA_Pos (0U)
+#define NVIC_ISER_SETENA_Msk (0xFFFFFFFFU << NVIC_ISER_SETENA_Pos) /*!< 0xFFFFFFFF */
+#define NVIC_ISER_SETENA NVIC_ISER_SETENA_Msk /*!< Interrupt set enable bits */
+#define NVIC_ISER_SETENA_0 (0x00000001U << NVIC_ISER_SETENA_Pos) /*!< 0x00000001 */
+#define NVIC_ISER_SETENA_1 (0x00000002U << NVIC_ISER_SETENA_Pos) /*!< 0x00000002 */
+#define NVIC_ISER_SETENA_2 (0x00000004U << NVIC_ISER_SETENA_Pos) /*!< 0x00000004 */
+#define NVIC_ISER_SETENA_3 (0x00000008U << NVIC_ISER_SETENA_Pos) /*!< 0x00000008 */
+#define NVIC_ISER_SETENA_4 (0x00000010U << NVIC_ISER_SETENA_Pos) /*!< 0x00000010 */
+#define NVIC_ISER_SETENA_5 (0x00000020U << NVIC_ISER_SETENA_Pos) /*!< 0x00000020 */
+#define NVIC_ISER_SETENA_6 (0x00000040U << NVIC_ISER_SETENA_Pos) /*!< 0x00000040 */
+#define NVIC_ISER_SETENA_7 (0x00000080U << NVIC_ISER_SETENA_Pos) /*!< 0x00000080 */
+#define NVIC_ISER_SETENA_8 (0x00000100U << NVIC_ISER_SETENA_Pos) /*!< 0x00000100 */
+#define NVIC_ISER_SETENA_9 (0x00000200U << NVIC_ISER_SETENA_Pos) /*!< 0x00000200 */
+#define NVIC_ISER_SETENA_10 (0x00000400U << NVIC_ISER_SETENA_Pos) /*!< 0x00000400 */
+#define NVIC_ISER_SETENA_11 (0x00000800U << NVIC_ISER_SETENA_Pos) /*!< 0x00000800 */
+#define NVIC_ISER_SETENA_12 (0x00001000U << NVIC_ISER_SETENA_Pos) /*!< 0x00001000 */
+#define NVIC_ISER_SETENA_13 (0x00002000U << NVIC_ISER_SETENA_Pos) /*!< 0x00002000 */
+#define NVIC_ISER_SETENA_14 (0x00004000U << NVIC_ISER_SETENA_Pos) /*!< 0x00004000 */
+#define NVIC_ISER_SETENA_15 (0x00008000U << NVIC_ISER_SETENA_Pos) /*!< 0x00008000 */
+#define NVIC_ISER_SETENA_16 (0x00010000U << NVIC_ISER_SETENA_Pos) /*!< 0x00010000 */
+#define NVIC_ISER_SETENA_17 (0x00020000U << NVIC_ISER_SETENA_Pos) /*!< 0x00020000 */
+#define NVIC_ISER_SETENA_18 (0x00040000U << NVIC_ISER_SETENA_Pos) /*!< 0x00040000 */
+#define NVIC_ISER_SETENA_19 (0x00080000U << NVIC_ISER_SETENA_Pos) /*!< 0x00080000 */
+#define NVIC_ISER_SETENA_20 (0x00100000U << NVIC_ISER_SETENA_Pos) /*!< 0x00100000 */
+#define NVIC_ISER_SETENA_21 (0x00200000U << NVIC_ISER_SETENA_Pos) /*!< 0x00200000 */
+#define NVIC_ISER_SETENA_22 (0x00400000U << NVIC_ISER_SETENA_Pos) /*!< 0x00400000 */
+#define NVIC_ISER_SETENA_23 (0x00800000U << NVIC_ISER_SETENA_Pos) /*!< 0x00800000 */
+#define NVIC_ISER_SETENA_24 (0x01000000U << NVIC_ISER_SETENA_Pos) /*!< 0x01000000 */
+#define NVIC_ISER_SETENA_25 (0x02000000U << NVIC_ISER_SETENA_Pos) /*!< 0x02000000 */
+#define NVIC_ISER_SETENA_26 (0x04000000U << NVIC_ISER_SETENA_Pos) /*!< 0x04000000 */
+#define NVIC_ISER_SETENA_27 (0x08000000U << NVIC_ISER_SETENA_Pos) /*!< 0x08000000 */
+#define NVIC_ISER_SETENA_28 (0x10000000U << NVIC_ISER_SETENA_Pos) /*!< 0x10000000 */
+#define NVIC_ISER_SETENA_29 (0x20000000U << NVIC_ISER_SETENA_Pos) /*!< 0x20000000 */
+#define NVIC_ISER_SETENA_30 (0x40000000U << NVIC_ISER_SETENA_Pos) /*!< 0x40000000 */
+#define NVIC_ISER_SETENA_31 (0x80000000U << NVIC_ISER_SETENA_Pos) /*!< 0x80000000 */
+
+/****************** Bit definition for NVIC_ICER register *******************/
+#define NVIC_ICER_CLRENA_Pos (0U)
+#define NVIC_ICER_CLRENA_Msk (0xFFFFFFFFU << NVIC_ICER_CLRENA_Pos) /*!< 0xFFFFFFFF */
+#define NVIC_ICER_CLRENA NVIC_ICER_CLRENA_Msk /*!< Interrupt clear-enable bits */
+#define NVIC_ICER_CLRENA_0 (0x00000001U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000001 */
+#define NVIC_ICER_CLRENA_1 (0x00000002U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000002 */
+#define NVIC_ICER_CLRENA_2 (0x00000004U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000004 */
+#define NVIC_ICER_CLRENA_3 (0x00000008U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000008 */
+#define NVIC_ICER_CLRENA_4 (0x00000010U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000010 */
+#define NVIC_ICER_CLRENA_5 (0x00000020U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000020 */
+#define NVIC_ICER_CLRENA_6 (0x00000040U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000040 */
+#define NVIC_ICER_CLRENA_7 (0x00000080U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000080 */
+#define NVIC_ICER_CLRENA_8 (0x00000100U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000100 */
+#define NVIC_ICER_CLRENA_9 (0x00000200U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000200 */
+#define NVIC_ICER_CLRENA_10 (0x00000400U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000400 */
+#define NVIC_ICER_CLRENA_11 (0x00000800U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000800 */
+#define NVIC_ICER_CLRENA_12 (0x00001000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00001000 */
+#define NVIC_ICER_CLRENA_13 (0x00002000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00002000 */
+#define NVIC_ICER_CLRENA_14 (0x00004000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00004000 */
+#define NVIC_ICER_CLRENA_15 (0x00008000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00008000 */
+#define NVIC_ICER_CLRENA_16 (0x00010000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00010000 */
+#define NVIC_ICER_CLRENA_17 (0x00020000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00020000 */
+#define NVIC_ICER_CLRENA_18 (0x00040000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00040000 */
+#define NVIC_ICER_CLRENA_19 (0x00080000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00080000 */
+#define NVIC_ICER_CLRENA_20 (0x00100000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00100000 */
+#define NVIC_ICER_CLRENA_21 (0x00200000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00200000 */
+#define NVIC_ICER_CLRENA_22 (0x00400000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00400000 */
+#define NVIC_ICER_CLRENA_23 (0x00800000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00800000 */
+#define NVIC_ICER_CLRENA_24 (0x01000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x01000000 */
+#define NVIC_ICER_CLRENA_25 (0x02000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x02000000 */
+#define NVIC_ICER_CLRENA_26 (0x04000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x04000000 */
+#define NVIC_ICER_CLRENA_27 (0x08000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x08000000 */
+#define NVIC_ICER_CLRENA_28 (0x10000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x10000000 */
+#define NVIC_ICER_CLRENA_29 (0x20000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x20000000 */
+#define NVIC_ICER_CLRENA_30 (0x40000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x40000000 */
+#define NVIC_ICER_CLRENA_31 (0x80000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x80000000 */
+
+/****************** Bit definition for NVIC_ISPR register *******************/
+#define NVIC_ISPR_SETPEND_Pos (0U)
+#define NVIC_ISPR_SETPEND_Msk (0xFFFFFFFFU << NVIC_ISPR_SETPEND_Pos) /*!< 0xFFFFFFFF */
+#define NVIC_ISPR_SETPEND NVIC_ISPR_SETPEND_Msk /*!< Interrupt set-pending bits */
+#define NVIC_ISPR_SETPEND_0 (0x00000001U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000001 */
+#define NVIC_ISPR_SETPEND_1 (0x00000002U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000002 */
+#define NVIC_ISPR_SETPEND_2 (0x00000004U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000004 */
+#define NVIC_ISPR_SETPEND_3 (0x00000008U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000008 */
+#define NVIC_ISPR_SETPEND_4 (0x00000010U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000010 */
+#define NVIC_ISPR_SETPEND_5 (0x00000020U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000020 */
+#define NVIC_ISPR_SETPEND_6 (0x00000040U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000040 */
+#define NVIC_ISPR_SETPEND_7 (0x00000080U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000080 */
+#define NVIC_ISPR_SETPEND_8 (0x00000100U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000100 */
+#define NVIC_ISPR_SETPEND_9 (0x00000200U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000200 */
+#define NVIC_ISPR_SETPEND_10 (0x00000400U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000400 */
+#define NVIC_ISPR_SETPEND_11 (0x00000800U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000800 */
+#define NVIC_ISPR_SETPEND_12 (0x00001000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00001000 */
+#define NVIC_ISPR_SETPEND_13 (0x00002000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00002000 */
+#define NVIC_ISPR_SETPEND_14 (0x00004000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00004000 */
+#define NVIC_ISPR_SETPEND_15 (0x00008000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00008000 */
+#define NVIC_ISPR_SETPEND_16 (0x00010000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00010000 */
+#define NVIC_ISPR_SETPEND_17 (0x00020000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00020000 */
+#define NVIC_ISPR_SETPEND_18 (0x00040000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00040000 */
+#define NVIC_ISPR_SETPEND_19 (0x00080000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00080000 */
+#define NVIC_ISPR_SETPEND_20 (0x00100000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00100000 */
+#define NVIC_ISPR_SETPEND_21 (0x00200000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00200000 */
+#define NVIC_ISPR_SETPEND_22 (0x00400000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00400000 */
+#define NVIC_ISPR_SETPEND_23 (0x00800000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00800000 */
+#define NVIC_ISPR_SETPEND_24 (0x01000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x01000000 */
+#define NVIC_ISPR_SETPEND_25 (0x02000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x02000000 */
+#define NVIC_ISPR_SETPEND_26 (0x04000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x04000000 */
+#define NVIC_ISPR_SETPEND_27 (0x08000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x08000000 */
+#define NVIC_ISPR_SETPEND_28 (0x10000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x10000000 */
+#define NVIC_ISPR_SETPEND_29 (0x20000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x20000000 */
+#define NVIC_ISPR_SETPEND_30 (0x40000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x40000000 */
+#define NVIC_ISPR_SETPEND_31 (0x80000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x80000000 */
+
+/****************** Bit definition for NVIC_ICPR register *******************/
+#define NVIC_ICPR_CLRPEND_Pos (0U)
+#define NVIC_ICPR_CLRPEND_Msk (0xFFFFFFFFU << NVIC_ICPR_CLRPEND_Pos) /*!< 0xFFFFFFFF */
+#define NVIC_ICPR_CLRPEND NVIC_ICPR_CLRPEND_Msk /*!< Interrupt clear-pending bits */
+#define NVIC_ICPR_CLRPEND_0 (0x00000001U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000001 */
+#define NVIC_ICPR_CLRPEND_1 (0x00000002U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000002 */
+#define NVIC_ICPR_CLRPEND_2 (0x00000004U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000004 */
+#define NVIC_ICPR_CLRPEND_3 (0x00000008U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000008 */
+#define NVIC_ICPR_CLRPEND_4 (0x00000010U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000010 */
+#define NVIC_ICPR_CLRPEND_5 (0x00000020U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000020 */
+#define NVIC_ICPR_CLRPEND_6 (0x00000040U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000040 */
+#define NVIC_ICPR_CLRPEND_7 (0x00000080U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000080 */
+#define NVIC_ICPR_CLRPEND_8 (0x00000100U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000100 */
+#define NVIC_ICPR_CLRPEND_9 (0x00000200U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000200 */
+#define NVIC_ICPR_CLRPEND_10 (0x00000400U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000400 */
+#define NVIC_ICPR_CLRPEND_11 (0x00000800U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000800 */
+#define NVIC_ICPR_CLRPEND_12 (0x00001000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00001000 */
+#define NVIC_ICPR_CLRPEND_13 (0x00002000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00002000 */
+#define NVIC_ICPR_CLRPEND_14 (0x00004000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00004000 */
+#define NVIC_ICPR_CLRPEND_15 (0x00008000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00008000 */
+#define NVIC_ICPR_CLRPEND_16 (0x00010000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00010000 */
+#define NVIC_ICPR_CLRPEND_17 (0x00020000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00020000 */
+#define NVIC_ICPR_CLRPEND_18 (0x00040000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00040000 */
+#define NVIC_ICPR_CLRPEND_19 (0x00080000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00080000 */
+#define NVIC_ICPR_CLRPEND_20 (0x00100000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00100000 */
+#define NVIC_ICPR_CLRPEND_21 (0x00200000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00200000 */
+#define NVIC_ICPR_CLRPEND_22 (0x00400000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00400000 */
+#define NVIC_ICPR_CLRPEND_23 (0x00800000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00800000 */
+#define NVIC_ICPR_CLRPEND_24 (0x01000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x01000000 */
+#define NVIC_ICPR_CLRPEND_25 (0x02000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x02000000 */
+#define NVIC_ICPR_CLRPEND_26 (0x04000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x04000000 */
+#define NVIC_ICPR_CLRPEND_27 (0x08000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x08000000 */
+#define NVIC_ICPR_CLRPEND_28 (0x10000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x10000000 */
+#define NVIC_ICPR_CLRPEND_29 (0x20000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x20000000 */
+#define NVIC_ICPR_CLRPEND_30 (0x40000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x40000000 */
+#define NVIC_ICPR_CLRPEND_31 (0x80000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x80000000 */
+
+/****************** Bit definition for NVIC_IABR register *******************/
+#define NVIC_IABR_ACTIVE_Pos (0U)
+#define NVIC_IABR_ACTIVE_Msk (0xFFFFFFFFU << NVIC_IABR_ACTIVE_Pos) /*!< 0xFFFFFFFF */
+#define NVIC_IABR_ACTIVE NVIC_IABR_ACTIVE_Msk /*!< Interrupt active flags */
+#define NVIC_IABR_ACTIVE_0 (0x00000001U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000001 */
+#define NVIC_IABR_ACTIVE_1 (0x00000002U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000002 */
+#define NVIC_IABR_ACTIVE_2 (0x00000004U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000004 */
+#define NVIC_IABR_ACTIVE_3 (0x00000008U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000008 */
+#define NVIC_IABR_ACTIVE_4 (0x00000010U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000010 */
+#define NVIC_IABR_ACTIVE_5 (0x00000020U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000020 */
+#define NVIC_IABR_ACTIVE_6 (0x00000040U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000040 */
+#define NVIC_IABR_ACTIVE_7 (0x00000080U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000080 */
+#define NVIC_IABR_ACTIVE_8 (0x00000100U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000100 */
+#define NVIC_IABR_ACTIVE_9 (0x00000200U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000200 */
+#define NVIC_IABR_ACTIVE_10 (0x00000400U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000400 */
+#define NVIC_IABR_ACTIVE_11 (0x00000800U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000800 */
+#define NVIC_IABR_ACTIVE_12 (0x00001000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00001000 */
+#define NVIC_IABR_ACTIVE_13 (0x00002000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00002000 */
+#define NVIC_IABR_ACTIVE_14 (0x00004000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00004000 */
+#define NVIC_IABR_ACTIVE_15 (0x00008000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00008000 */
+#define NVIC_IABR_ACTIVE_16 (0x00010000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00010000 */
+#define NVIC_IABR_ACTIVE_17 (0x00020000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00020000 */
+#define NVIC_IABR_ACTIVE_18 (0x00040000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00040000 */
+#define NVIC_IABR_ACTIVE_19 (0x00080000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00080000 */
+#define NVIC_IABR_ACTIVE_20 (0x00100000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00100000 */
+#define NVIC_IABR_ACTIVE_21 (0x00200000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00200000 */
+#define NVIC_IABR_ACTIVE_22 (0x00400000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00400000 */
+#define NVIC_IABR_ACTIVE_23 (0x00800000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00800000 */
+#define NVIC_IABR_ACTIVE_24 (0x01000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x01000000 */
+#define NVIC_IABR_ACTIVE_25 (0x02000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x02000000 */
+#define NVIC_IABR_ACTIVE_26 (0x04000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x04000000 */
+#define NVIC_IABR_ACTIVE_27 (0x08000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x08000000 */
+#define NVIC_IABR_ACTIVE_28 (0x10000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x10000000 */
+#define NVIC_IABR_ACTIVE_29 (0x20000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x20000000 */
+#define NVIC_IABR_ACTIVE_30 (0x40000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x40000000 */
+#define NVIC_IABR_ACTIVE_31 (0x80000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x80000000 */
+
+/****************** Bit definition for NVIC_PRI0 register *******************/
+#define NVIC_IPR0_PRI_0 ((uint32_t)0x000000FF) /*!< Priority of interrupt 0 */
+#define NVIC_IPR0_PRI_1 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 1 */
+#define NVIC_IPR0_PRI_2 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 2 */
+#define NVIC_IPR0_PRI_3 ((uint32_t)0xFF000000) /*!< Priority of interrupt 3 */
+
+/****************** Bit definition for NVIC_PRI1 register *******************/
+#define NVIC_IPR1_PRI_4 ((uint32_t)0x000000FF) /*!< Priority of interrupt 4 */
+#define NVIC_IPR1_PRI_5 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 5 */
+#define NVIC_IPR1_PRI_6 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 6 */
+#define NVIC_IPR1_PRI_7 ((uint32_t)0xFF000000) /*!< Priority of interrupt 7 */
+
+/****************** Bit definition for NVIC_PRI2 register *******************/
+#define NVIC_IPR2_PRI_8 ((uint32_t)0x000000FF) /*!< Priority of interrupt 8 */
+#define NVIC_IPR2_PRI_9 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 9 */
+#define NVIC_IPR2_PRI_10 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 10 */
+#define NVIC_IPR2_PRI_11 ((uint32_t)0xFF000000) /*!< Priority of interrupt 11 */
+
+/****************** Bit definition for NVIC_PRI3 register *******************/
+#define NVIC_IPR3_PRI_12 ((uint32_t)0x000000FF) /*!< Priority of interrupt 12 */
+#define NVIC_IPR3_PRI_13 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 13 */
+#define NVIC_IPR3_PRI_14 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 14 */
+#define NVIC_IPR3_PRI_15 ((uint32_t)0xFF000000) /*!< Priority of interrupt 15 */
+
+/****************** Bit definition for NVIC_PRI4 register *******************/
+#define NVIC_IPR4_PRI_16 ((uint32_t)0x000000FF) /*!< Priority of interrupt 16 */
+#define NVIC_IPR4_PRI_17 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 17 */
+#define NVIC_IPR4_PRI_18 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 18 */
+#define NVIC_IPR4_PRI_19 ((uint32_t)0xFF000000) /*!< Priority of interrupt 19 */
+
+/****************** Bit definition for NVIC_PRI5 register *******************/
+#define NVIC_IPR5_PRI_20 ((uint32_t)0x000000FF) /*!< Priority of interrupt 20 */
+#define NVIC_IPR5_PRI_21 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 21 */
+#define NVIC_IPR5_PRI_22 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 22 */
+#define NVIC_IPR5_PRI_23 ((uint32_t)0xFF000000) /*!< Priority of interrupt 23 */
+
+/****************** Bit definition for NVIC_PRI6 register *******************/
+#define NVIC_IPR6_PRI_24 ((uint32_t)0x000000FF) /*!< Priority of interrupt 24 */
+#define NVIC_IPR6_PRI_25 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 25 */
+#define NVIC_IPR6_PRI_26 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 26 */
+#define NVIC_IPR6_PRI_27 ((uint32_t)0xFF000000) /*!< Priority of interrupt 27 */
+
+/****************** Bit definition for NVIC_PRI7 register *******************/
+#define NVIC_IPR7_PRI_28 ((uint32_t)0x000000FF) /*!< Priority of interrupt 28 */
+#define NVIC_IPR7_PRI_29 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 29 */
+#define NVIC_IPR7_PRI_30 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 30 */
+#define NVIC_IPR7_PRI_31 ((uint32_t)0xFF000000) /*!< Priority of interrupt 31 */
+
+/****************** Bit definition for SCB_CPUID register *******************/
+#define SCB_CPUID_REVISION ((uint32_t)0x0000000F) /*!< Implementation defined revision number */
+#define SCB_CPUID_PARTNO ((uint32_t)0x0000FFF0) /*!< Number of processor within family */
+#define SCB_CPUID_Constant ((uint32_t)0x000F0000) /*!< Reads as 0x0F */
+#define SCB_CPUID_VARIANT ((uint32_t)0x00F00000) /*!< Implementation defined variant number */
+#define SCB_CPUID_IMPLEMENTER ((uint32_t)0xFF000000) /*!< Implementer code. ARM is 0x41 */
+
+/******************* Bit definition for SCB_ICSR register *******************/
+#define SCB_ICSR_VECTACTIVE ((uint32_t)0x000001FF) /*!< Active ISR number field */
+#define SCB_ICSR_RETTOBASE ((uint32_t)0x00000800) /*!< All active exceptions minus the IPSR_current_exception yields the empty set */
+#define SCB_ICSR_VECTPENDING ((uint32_t)0x003FF000) /*!< Pending ISR number field */
+#define SCB_ICSR_ISRPENDING ((uint32_t)0x00400000) /*!< Interrupt pending flag */
+#define SCB_ICSR_ISRPREEMPT ((uint32_t)0x00800000) /*!< It indicates that a pending interrupt becomes active in the next running cycle */
+#define SCB_ICSR_PENDSTCLR ((uint32_t)0x02000000) /*!< Clear pending SysTick bit */
+#define SCB_ICSR_PENDSTSET ((uint32_t)0x04000000) /*!< Set pending SysTick bit */
+#define SCB_ICSR_PENDSVCLR ((uint32_t)0x08000000) /*!< Clear pending pendSV bit */
+#define SCB_ICSR_PENDSVSET ((uint32_t)0x10000000) /*!< Set pending pendSV bit */
+#define SCB_ICSR_NMIPENDSET ((uint32_t)0x80000000) /*!< Set pending NMI bit */
+
+/******************* Bit definition for SCB_VTOR register *******************/
+#define SCB_VTOR_TBLOFF ((uint32_t)0x1FFFFF80) /*!< Vector table base offset field */
+#define SCB_VTOR_TBLBASE ((uint32_t)0x20000000) /*!< Table base in code(0) or RAM(1) */
+
+/*!<***************** Bit definition for SCB_AIRCR register *******************/
+#define SCB_AIRCR_VECTRESET ((uint32_t)0x00000001) /*!< System Reset bit */
+#define SCB_AIRCR_VECTCLRACTIVE ((uint32_t)0x00000002) /*!< Clear active vector bit */
+#define SCB_AIRCR_SYSRESETREQ ((uint32_t)0x00000004) /*!< Requests chip control logic to generate a reset */
+
+#define SCB_AIRCR_PRIGROUP ((uint32_t)0x00000700) /*!< PRIGROUP[2:0] bits (Priority group) */
+#define SCB_AIRCR_PRIGROUP_0 ((uint32_t)0x00000100) /*!< Bit 0 */
+#define SCB_AIRCR_PRIGROUP_1 ((uint32_t)0x00000200) /*!< Bit 1 */
+#define SCB_AIRCR_PRIGROUP_2 ((uint32_t)0x00000400) /*!< Bit 2 */
+
+/* prority group configuration */
+#define SCB_AIRCR_PRIGROUP0 ((uint32_t)0x00000000) /*!< Priority group=0 (7 bits of pre-emption priority, 1 bit of subpriority) */
+#define SCB_AIRCR_PRIGROUP1 ((uint32_t)0x00000100) /*!< Priority group=1 (6 bits of pre-emption priority, 2 bits of subpriority) */
+#define SCB_AIRCR_PRIGROUP2 ((uint32_t)0x00000200) /*!< Priority group=2 (5 bits of pre-emption priority, 3 bits of subpriority) */
+#define SCB_AIRCR_PRIGROUP3 ((uint32_t)0x00000300) /*!< Priority group=3 (4 bits of pre-emption priority, 4 bits of subpriority) */
+#define SCB_AIRCR_PRIGROUP4 ((uint32_t)0x00000400) /*!< Priority group=4 (3 bits of pre-emption priority, 5 bits of subpriority) */
+#define SCB_AIRCR_PRIGROUP5 ((uint32_t)0x00000500) /*!< Priority group=5 (2 bits of pre-emption priority, 6 bits of subpriority) */
+#define SCB_AIRCR_PRIGROUP6 ((uint32_t)0x00000600) /*!< Priority group=6 (1 bit of pre-emption priority, 7 bits of subpriority) */
+#define SCB_AIRCR_PRIGROUP7 ((uint32_t)0x00000700) /*!< Priority group=7 (no pre-emption priority, 8 bits of subpriority) */
+
+#define SCB_AIRCR_ENDIANESS ((uint32_t)0x00008000) /*!< Data endianness bit */
+#define SCB_AIRCR_VECTKEY ((uint32_t)0xFFFF0000) /*!< Register key (VECTKEY) - Reads as 0xFA05 (VECTKEYSTAT) */
+
+/******************* Bit definition for SCB_SCR register ********************/
+#define SCB_SCR_SLEEPONEXIT ((uint32_t)0x00000002) /*!< Sleep on exit bit */
+#define SCB_SCR_SLEEPDEEP ((uint32_t)0x00000004) /*!< Sleep deep bit */
+#define SCB_SCR_SEVONPEND ((uint32_t)0x00000010) /*!< Wake up from WFE */
+
+/******************** Bit definition for SCB_CCR register *******************/
+#define SCB_CCR_NONBASETHRDENA ((uint32_t)0x00000001) /*!< Thread mode can be entered from any level in Handler mode by controlled return value */
+#define SCB_CCR_USERSETMPEND ((uint32_t)0x00000002) /*!< Enables user code to write the Software Trigger Interrupt register to trigger (pend) a Main exception */
+#define SCB_CCR_UNALIGN_TRP ((uint32_t)0x00000008) /*!< Trap for unaligned access */
+#define SCB_CCR_DIV_0_TRP ((uint32_t)0x00000010) /*!< Trap on Divide by 0 */
+#define SCB_CCR_BFHFNMIGN ((uint32_t)0x00000100) /*!< Handlers running at priority -1 and -2 */
+#define SCB_CCR_STKALIGN ((uint32_t)0x00000200) /*!< On exception entry, the SP used prior to the exception is adjusted to be 8-byte aligned */
+
+/******************* Bit definition for SCB_SHPR register ********************/
+#define SCB_SHPR_PRI_N_Pos (0U)
+#define SCB_SHPR_PRI_N_Msk (0xFFU << SCB_SHPR_PRI_N_Pos) /*!< 0x000000FF */
+#define SCB_SHPR_PRI_N SCB_SHPR_PRI_N_Msk /*!< Priority of system handler 4,8, and 12. Mem Manage, reserved and Debug Monitor */
+#define SCB_SHPR_PRI_N1_Pos (8U)
+#define SCB_SHPR_PRI_N1_Msk (0xFFU << SCB_SHPR_PRI_N1_Pos) /*!< 0x0000FF00 */
+#define SCB_SHPR_PRI_N1 SCB_SHPR_PRI_N1_Msk /*!< Priority of system handler 5,9, and 13. Bus Fault, reserved and reserved */
+#define SCB_SHPR_PRI_N2_Pos (16U)
+#define SCB_SHPR_PRI_N2_Msk (0xFFU << SCB_SHPR_PRI_N2_Pos) /*!< 0x00FF0000 */
+#define SCB_SHPR_PRI_N2 SCB_SHPR_PRI_N2_Msk /*!< Priority of system handler 6,10, and 14. Usage Fault, reserved and PendSV */
+#define SCB_SHPR_PRI_N3_Pos (24U)
+#define SCB_SHPR_PRI_N3_Msk (0xFFU << SCB_SHPR_PRI_N3_Pos) /*!< 0xFF000000 */
+#define SCB_SHPR_PRI_N3 SCB_SHPR_PRI_N3_Msk /*!< Priority of system handler 7,11, and 15. Reserved, SVCall and SysTick */
+
+/****************** Bit definition for SCB_SHCSR register *******************/
+#define SCB_SHCSR_MEMFAULTACT ((uint32_t)0x00000001) /*!< MemManage is active */
+#define SCB_SHCSR_BUSFAULTACT ((uint32_t)0x00000002) /*!< BusFault is active */
+#define SCB_SHCSR_USGFAULTACT ((uint32_t)0x00000008) /*!< UsageFault is active */
+#define SCB_SHCSR_SVCALLACT ((uint32_t)0x00000080) /*!< SVCall is active */
+#define SCB_SHCSR_MONITORACT ((uint32_t)0x00000100) /*!< Monitor is active */
+#define SCB_SHCSR_PENDSVACT ((uint32_t)0x00000400) /*!< PendSV is active */
+#define SCB_SHCSR_SYSTICKACT ((uint32_t)0x00000800) /*!< SysTick is active */
+#define SCB_SHCSR_USGFAULTPENDED ((uint32_t)0x00001000) /*!< Usage Fault is pended */
+#define SCB_SHCSR_MEMFAULTPENDED ((uint32_t)0x00002000) /*!< MemManage is pended */
+#define SCB_SHCSR_BUSFAULTPENDED ((uint32_t)0x00004000) /*!< Bus Fault is pended */
+#define SCB_SHCSR_SVCALLPENDED ((uint32_t)0x00008000) /*!< SVCall is pended */
+#define SCB_SHCSR_MEMFAULTENA ((uint32_t)0x00010000) /*!< MemManage enable */
+#define SCB_SHCSR_BUSFAULTENA ((uint32_t)0x00020000) /*!< Bus Fault enable */
+#define SCB_SHCSR_USGFAULTENA ((uint32_t)0x00040000) /*!< UsageFault enable */
+
+/******************* Bit definition for SCB_CFSR register *******************/
+/*!< MFSR */
+#define SCB_CFSR_IACCVIOL_Pos (0U)
+#define SCB_CFSR_IACCVIOL_Msk (0x1U << SCB_CFSR_IACCVIOL_Pos) /*!< 0x00000001 */
+#define SCB_CFSR_IACCVIOL SCB_CFSR_IACCVIOL_Msk /*!< Instruction access violation */
+#define SCB_CFSR_DACCVIOL_Pos (1U)
+#define SCB_CFSR_DACCVIOL_Msk (0x1U << SCB_CFSR_DACCVIOL_Pos) /*!< 0x00000002 */
+#define SCB_CFSR_DACCVIOL SCB_CFSR_DACCVIOL_Msk /*!< Data access violation */
+#define SCB_CFSR_MUNSTKERR_Pos (3U)
+#define SCB_CFSR_MUNSTKERR_Msk (0x1U << SCB_CFSR_MUNSTKERR_Pos) /*!< 0x00000008 */
+#define SCB_CFSR_MUNSTKERR SCB_CFSR_MUNSTKERR_Msk /*!< Unstacking error */
+#define SCB_CFSR_MSTKERR_Pos (4U)
+#define SCB_CFSR_MSTKERR_Msk (0x1U << SCB_CFSR_MSTKERR_Pos) /*!< 0x00000010 */
+#define SCB_CFSR_MSTKERR SCB_CFSR_MSTKERR_Msk /*!< Stacking error */
+#define SCB_CFSR_MMARVALID_Pos (7U)
+#define SCB_CFSR_MMARVALID_Msk (0x1U << SCB_CFSR_MMARVALID_Pos) /*!< 0x00000080 */
+#define SCB_CFSR_MMARVALID SCB_CFSR_MMARVALID_Msk /*!< Memory Manage Address Register address valid flag */
+/*!< BFSR */
+#define SCB_CFSR_IBUSERR_Pos (8U)
+#define SCB_CFSR_IBUSERR_Msk (0x1U << SCB_CFSR_IBUSERR_Pos) /*!< 0x00000100 */
+#define SCB_CFSR_IBUSERR SCB_CFSR_IBUSERR_Msk /*!< Instruction bus error flag */
+#define SCB_CFSR_PRECISERR_Pos (9U)
+#define SCB_CFSR_PRECISERR_Msk (0x1U << SCB_CFSR_PRECISERR_Pos) /*!< 0x00000200 */
+#define SCB_CFSR_PRECISERR SCB_CFSR_PRECISERR_Msk /*!< Precise data bus error */
+#define SCB_CFSR_IMPRECISERR_Pos (10U)
+#define SCB_CFSR_IMPRECISERR_Msk (0x1U << SCB_CFSR_IMPRECISERR_Pos) /*!< 0x00000400 */
+#define SCB_CFSR_IMPRECISERR SCB_CFSR_IMPRECISERR_Msk /*!< Imprecise data bus error */
+#define SCB_CFSR_UNSTKERR_Pos (11U)
+#define SCB_CFSR_UNSTKERR_Msk (0x1U << SCB_CFSR_UNSTKERR_Pos) /*!< 0x00000800 */
+#define SCB_CFSR_UNSTKERR SCB_CFSR_UNSTKERR_Msk /*!< Unstacking error */
+#define SCB_CFSR_STKERR_Pos (12U)
+#define SCB_CFSR_STKERR_Msk (0x1U << SCB_CFSR_STKERR_Pos) /*!< 0x00001000 */
+#define SCB_CFSR_STKERR SCB_CFSR_STKERR_Msk /*!< Stacking error */
+#define SCB_CFSR_BFARVALID_Pos (15U)
+#define SCB_CFSR_BFARVALID_Msk (0x1U << SCB_CFSR_BFARVALID_Pos) /*!< 0x00008000 */
+#define SCB_CFSR_BFARVALID SCB_CFSR_BFARVALID_Msk /*!< Bus Fault Address Register address valid flag */
+/*!< UFSR */
+#define SCB_CFSR_UNDEFINSTR_Pos (16U)
+#define SCB_CFSR_UNDEFINSTR_Msk (0x1U << SCB_CFSR_UNDEFINSTR_Pos) /*!< 0x00010000 */
+#define SCB_CFSR_UNDEFINSTR SCB_CFSR_UNDEFINSTR_Msk /*!< The processor attempt to execute an undefined instruction */
+#define SCB_CFSR_INVSTATE_Pos (17U)
+#define SCB_CFSR_INVSTATE_Msk (0x1U << SCB_CFSR_INVSTATE_Pos) /*!< 0x00020000 */
+#define SCB_CFSR_INVSTATE SCB_CFSR_INVSTATE_Msk /*!< Invalid combination of EPSR and instruction */
+#define SCB_CFSR_INVPC_Pos (18U)
+#define SCB_CFSR_INVPC_Msk (0x1U << SCB_CFSR_INVPC_Pos) /*!< 0x00040000 */
+#define SCB_CFSR_INVPC SCB_CFSR_INVPC_Msk /*!< Attempt to load EXC_RETURN into pc illegally */
+#define SCB_CFSR_NOCP_Pos (19U)
+#define SCB_CFSR_NOCP_Msk (0x1U << SCB_CFSR_NOCP_Pos) /*!< 0x00080000 */
+#define SCB_CFSR_NOCP SCB_CFSR_NOCP_Msk /*!< Attempt to use a coprocessor instruction */
+#define SCB_CFSR_UNALIGNED_Pos (24U)
+#define SCB_CFSR_UNALIGNED_Msk (0x1U << SCB_CFSR_UNALIGNED_Pos) /*!< 0x01000000 */
+#define SCB_CFSR_UNALIGNED SCB_CFSR_UNALIGNED_Msk /*!< Fault occurs when there is an attempt to make an unaligned memory access */
+#define SCB_CFSR_DIVBYZERO_Pos (25U)
+#define SCB_CFSR_DIVBYZERO_Msk (0x1U << SCB_CFSR_DIVBYZERO_Pos) /*!< 0x02000000 */
+#define SCB_CFSR_DIVBYZERO SCB_CFSR_DIVBYZERO_Msk /*!< Fault occurs when SDIV or DIV instruction is used with a divisor of 0 */
+
+/******************* Bit definition for SCB_HFSR register *******************/
+#define SCB_HFSR_VECTTBL ((uint32_t)0x00000002) /*!< Fault occurs because of vector table read on exception processing */
+#define SCB_HFSR_FORCED ((uint32_t)0x40000000) /*!< Hard Fault activated when a configurable Fault was received and cannot activate */
+#define SCB_HFSR_DEBUGEVT ((uint32_t)0x80000000) /*!< Fault related to debug */
+
+/******************* Bit definition for SCB_DFSR register *******************/
+#define SCB_DFSR_HALTED ((uint32_t)0x00000001) /*!< Halt request flag */
+#define SCB_DFSR_BKPT ((uint32_t)0x00000002) /*!< BKPT flag */
+#define SCB_DFSR_DWTTRAP ((uint32_t)0x00000004) /*!< Data Watchpoint and Trace (DWT) flag */
+#define SCB_DFSR_VCATCH ((uint32_t)0x00000008) /*!< Vector catch flag */
+#define SCB_DFSR_EXTERNAL ((uint32_t)0x00000010) /*!< External debug request flag */
+
+/******************* Bit definition for SCB_MMFAR register ******************/
+#define SCB_MMFAR_ADDRESS_Pos (0U)
+#define SCB_MMFAR_ADDRESS_Msk (0xFFFFFFFFU << SCB_MMFAR_ADDRESS_Pos) /*!< 0xFFFFFFFF */
+#define SCB_MMFAR_ADDRESS SCB_MMFAR_ADDRESS_Msk /*!< Mem Manage fault address field */
+
+/******************* Bit definition for SCB_BFAR register *******************/
+#define SCB_BFAR_ADDRESS_Pos (0U)
+#define SCB_BFAR_ADDRESS_Msk (0xFFFFFFFFU << SCB_BFAR_ADDRESS_Pos) /*!< 0xFFFFFFFF */
+#define SCB_BFAR_ADDRESS SCB_BFAR_ADDRESS_Msk /*!< Bus fault address field */
+
+/******************* Bit definition for SCB_afsr register *******************/
+#define SCB_AFSR_IMPDEF_Pos (0U)
+#define SCB_AFSR_IMPDEF_Msk (0xFFFFFFFFU << SCB_AFSR_IMPDEF_Pos) /*!< 0xFFFFFFFF */
+#define SCB_AFSR_IMPDEF SCB_AFSR_IMPDEF_Msk /*!< Implementation defined */
+
+/******************************************************************************/
+/* */
+/* External Interrupt/Event Controller */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for EXTI_IMR register *******************/
+#define EXTI_IMR_MR0_Pos (0U)
+#define EXTI_IMR_MR0_Msk (0x1U << EXTI_IMR_MR0_Pos) /*!< 0x00000001 */
+#define EXTI_IMR_MR0 EXTI_IMR_MR0_Msk /*!< Interrupt Mask on line 0 */
+#define EXTI_IMR_MR1_Pos (1U)
+#define EXTI_IMR_MR1_Msk (0x1U << EXTI_IMR_MR1_Pos) /*!< 0x00000002 */
+#define EXTI_IMR_MR1 EXTI_IMR_MR1_Msk /*!< Interrupt Mask on line 1 */
+#define EXTI_IMR_MR2_Pos (2U)
+#define EXTI_IMR_MR2_Msk (0x1U << EXTI_IMR_MR2_Pos) /*!< 0x00000004 */
+#define EXTI_IMR_MR2 EXTI_IMR_MR2_Msk /*!< Interrupt Mask on line 2 */
+#define EXTI_IMR_MR3_Pos (3U)
+#define EXTI_IMR_MR3_Msk (0x1U << EXTI_IMR_MR3_Pos) /*!< 0x00000008 */
+#define EXTI_IMR_MR3 EXTI_IMR_MR3_Msk /*!< Interrupt Mask on line 3 */
+#define EXTI_IMR_MR4_Pos (4U)
+#define EXTI_IMR_MR4_Msk (0x1U << EXTI_IMR_MR4_Pos) /*!< 0x00000010 */
+#define EXTI_IMR_MR4 EXTI_IMR_MR4_Msk /*!< Interrupt Mask on line 4 */
+#define EXTI_IMR_MR5_Pos (5U)
+#define EXTI_IMR_MR5_Msk (0x1U << EXTI_IMR_MR5_Pos) /*!< 0x00000020 */
+#define EXTI_IMR_MR5 EXTI_IMR_MR5_Msk /*!< Interrupt Mask on line 5 */
+#define EXTI_IMR_MR6_Pos (6U)
+#define EXTI_IMR_MR6_Msk (0x1U << EXTI_IMR_MR6_Pos) /*!< 0x00000040 */
+#define EXTI_IMR_MR6 EXTI_IMR_MR6_Msk /*!< Interrupt Mask on line 6 */
+#define EXTI_IMR_MR7_Pos (7U)
+#define EXTI_IMR_MR7_Msk (0x1U << EXTI_IMR_MR7_Pos) /*!< 0x00000080 */
+#define EXTI_IMR_MR7 EXTI_IMR_MR7_Msk /*!< Interrupt Mask on line 7 */
+#define EXTI_IMR_MR8_Pos (8U)
+#define EXTI_IMR_MR8_Msk (0x1U << EXTI_IMR_MR8_Pos) /*!< 0x00000100 */
+#define EXTI_IMR_MR8 EXTI_IMR_MR8_Msk /*!< Interrupt Mask on line 8 */
+#define EXTI_IMR_MR9_Pos (9U)
+#define EXTI_IMR_MR9_Msk (0x1U << EXTI_IMR_MR9_Pos) /*!< 0x00000200 */
+#define EXTI_IMR_MR9 EXTI_IMR_MR9_Msk /*!< Interrupt Mask on line 9 */
+#define EXTI_IMR_MR10_Pos (10U)
+#define EXTI_IMR_MR10_Msk (0x1U << EXTI_IMR_MR10_Pos) /*!< 0x00000400 */
+#define EXTI_IMR_MR10 EXTI_IMR_MR10_Msk /*!< Interrupt Mask on line 10 */
+#define EXTI_IMR_MR11_Pos (11U)
+#define EXTI_IMR_MR11_Msk (0x1U << EXTI_IMR_MR11_Pos) /*!< 0x00000800 */
+#define EXTI_IMR_MR11 EXTI_IMR_MR11_Msk /*!< Interrupt Mask on line 11 */
+#define EXTI_IMR_MR12_Pos (12U)
+#define EXTI_IMR_MR12_Msk (0x1U << EXTI_IMR_MR12_Pos) /*!< 0x00001000 */
+#define EXTI_IMR_MR12 EXTI_IMR_MR12_Msk /*!< Interrupt Mask on line 12 */
+#define EXTI_IMR_MR13_Pos (13U)
+#define EXTI_IMR_MR13_Msk (0x1U << EXTI_IMR_MR13_Pos) /*!< 0x00002000 */
+#define EXTI_IMR_MR13 EXTI_IMR_MR13_Msk /*!< Interrupt Mask on line 13 */
+#define EXTI_IMR_MR14_Pos (14U)
+#define EXTI_IMR_MR14_Msk (0x1U << EXTI_IMR_MR14_Pos) /*!< 0x00004000 */
+#define EXTI_IMR_MR14 EXTI_IMR_MR14_Msk /*!< Interrupt Mask on line 14 */
+#define EXTI_IMR_MR15_Pos (15U)
+#define EXTI_IMR_MR15_Msk (0x1U << EXTI_IMR_MR15_Pos) /*!< 0x00008000 */
+#define EXTI_IMR_MR15 EXTI_IMR_MR15_Msk /*!< Interrupt Mask on line 15 */
+#define EXTI_IMR_MR16_Pos (16U)
+#define EXTI_IMR_MR16_Msk (0x1U << EXTI_IMR_MR16_Pos) /*!< 0x00010000 */
+#define EXTI_IMR_MR16 EXTI_IMR_MR16_Msk /*!< Interrupt Mask on line 16 */
+#define EXTI_IMR_MR17_Pos (17U)
+#define EXTI_IMR_MR17_Msk (0x1U << EXTI_IMR_MR17_Pos) /*!< 0x00020000 */
+#define EXTI_IMR_MR17 EXTI_IMR_MR17_Msk /*!< Interrupt Mask on line 17 */
+#define EXTI_IMR_MR18_Pos (18U)
+#define EXTI_IMR_MR18_Msk (0x1U << EXTI_IMR_MR18_Pos) /*!< 0x00040000 */
+#define EXTI_IMR_MR18 EXTI_IMR_MR18_Msk /*!< Interrupt Mask on line 18 */
+#define EXTI_IMR_MR19_Pos (19U)
+#define EXTI_IMR_MR19_Msk (0x1U << EXTI_IMR_MR19_Pos) /*!< 0x00080000 */
+#define EXTI_IMR_MR19 EXTI_IMR_MR19_Msk /*!< Interrupt Mask on line 19 */
+
+/* References Defines */
+#define EXTI_IMR_IM0 EXTI_IMR_MR0
+#define EXTI_IMR_IM1 EXTI_IMR_MR1
+#define EXTI_IMR_IM2 EXTI_IMR_MR2
+#define EXTI_IMR_IM3 EXTI_IMR_MR3
+#define EXTI_IMR_IM4 EXTI_IMR_MR4
+#define EXTI_IMR_IM5 EXTI_IMR_MR5
+#define EXTI_IMR_IM6 EXTI_IMR_MR6
+#define EXTI_IMR_IM7 EXTI_IMR_MR7
+#define EXTI_IMR_IM8 EXTI_IMR_MR8
+#define EXTI_IMR_IM9 EXTI_IMR_MR9
+#define EXTI_IMR_IM10 EXTI_IMR_MR10
+#define EXTI_IMR_IM11 EXTI_IMR_MR11
+#define EXTI_IMR_IM12 EXTI_IMR_MR12
+#define EXTI_IMR_IM13 EXTI_IMR_MR13
+#define EXTI_IMR_IM14 EXTI_IMR_MR14
+#define EXTI_IMR_IM15 EXTI_IMR_MR15
+#define EXTI_IMR_IM16 EXTI_IMR_MR16
+#define EXTI_IMR_IM17 EXTI_IMR_MR17
+#define EXTI_IMR_IM18 EXTI_IMR_MR18
+#define EXTI_IMR_IM19 EXTI_IMR_MR19
+
+/******************* Bit definition for EXTI_EMR register *******************/
+#define EXTI_EMR_MR0_Pos (0U)
+#define EXTI_EMR_MR0_Msk (0x1U << EXTI_EMR_MR0_Pos) /*!< 0x00000001 */
+#define EXTI_EMR_MR0 EXTI_EMR_MR0_Msk /*!< Event Mask on line 0 */
+#define EXTI_EMR_MR1_Pos (1U)
+#define EXTI_EMR_MR1_Msk (0x1U << EXTI_EMR_MR1_Pos) /*!< 0x00000002 */
+#define EXTI_EMR_MR1 EXTI_EMR_MR1_Msk /*!< Event Mask on line 1 */
+#define EXTI_EMR_MR2_Pos (2U)
+#define EXTI_EMR_MR2_Msk (0x1U << EXTI_EMR_MR2_Pos) /*!< 0x00000004 */
+#define EXTI_EMR_MR2 EXTI_EMR_MR2_Msk /*!< Event Mask on line 2 */
+#define EXTI_EMR_MR3_Pos (3U)
+#define EXTI_EMR_MR3_Msk (0x1U << EXTI_EMR_MR3_Pos) /*!< 0x00000008 */
+#define EXTI_EMR_MR3 EXTI_EMR_MR3_Msk /*!< Event Mask on line 3 */
+#define EXTI_EMR_MR4_Pos (4U)
+#define EXTI_EMR_MR4_Msk (0x1U << EXTI_EMR_MR4_Pos) /*!< 0x00000010 */
+#define EXTI_EMR_MR4 EXTI_EMR_MR4_Msk /*!< Event Mask on line 4 */
+#define EXTI_EMR_MR5_Pos (5U)
+#define EXTI_EMR_MR5_Msk (0x1U << EXTI_EMR_MR5_Pos) /*!< 0x00000020 */
+#define EXTI_EMR_MR5 EXTI_EMR_MR5_Msk /*!< Event Mask on line 5 */
+#define EXTI_EMR_MR6_Pos (6U)
+#define EXTI_EMR_MR6_Msk (0x1U << EXTI_EMR_MR6_Pos) /*!< 0x00000040 */
+#define EXTI_EMR_MR6 EXTI_EMR_MR6_Msk /*!< Event Mask on line 6 */
+#define EXTI_EMR_MR7_Pos (7U)
+#define EXTI_EMR_MR7_Msk (0x1U << EXTI_EMR_MR7_Pos) /*!< 0x00000080 */
+#define EXTI_EMR_MR7 EXTI_EMR_MR7_Msk /*!< Event Mask on line 7 */
+#define EXTI_EMR_MR8_Pos (8U)
+#define EXTI_EMR_MR8_Msk (0x1U << EXTI_EMR_MR8_Pos) /*!< 0x00000100 */
+#define EXTI_EMR_MR8 EXTI_EMR_MR8_Msk /*!< Event Mask on line 8 */
+#define EXTI_EMR_MR9_Pos (9U)
+#define EXTI_EMR_MR9_Msk (0x1U << EXTI_EMR_MR9_Pos) /*!< 0x00000200 */
+#define EXTI_EMR_MR9 EXTI_EMR_MR9_Msk /*!< Event Mask on line 9 */
+#define EXTI_EMR_MR10_Pos (10U)
+#define EXTI_EMR_MR10_Msk (0x1U << EXTI_EMR_MR10_Pos) /*!< 0x00000400 */
+#define EXTI_EMR_MR10 EXTI_EMR_MR10_Msk /*!< Event Mask on line 10 */
+#define EXTI_EMR_MR11_Pos (11U)
+#define EXTI_EMR_MR11_Msk (0x1U << EXTI_EMR_MR11_Pos) /*!< 0x00000800 */
+#define EXTI_EMR_MR11 EXTI_EMR_MR11_Msk /*!< Event Mask on line 11 */
+#define EXTI_EMR_MR12_Pos (12U)
+#define EXTI_EMR_MR12_Msk (0x1U << EXTI_EMR_MR12_Pos) /*!< 0x00001000 */
+#define EXTI_EMR_MR12 EXTI_EMR_MR12_Msk /*!< Event Mask on line 12 */
+#define EXTI_EMR_MR13_Pos (13U)
+#define EXTI_EMR_MR13_Msk (0x1U << EXTI_EMR_MR13_Pos) /*!< 0x00002000 */
+#define EXTI_EMR_MR13 EXTI_EMR_MR13_Msk /*!< Event Mask on line 13 */
+#define EXTI_EMR_MR14_Pos (14U)
+#define EXTI_EMR_MR14_Msk (0x1U << EXTI_EMR_MR14_Pos) /*!< 0x00004000 */
+#define EXTI_EMR_MR14 EXTI_EMR_MR14_Msk /*!< Event Mask on line 14 */
+#define EXTI_EMR_MR15_Pos (15U)
+#define EXTI_EMR_MR15_Msk (0x1U << EXTI_EMR_MR15_Pos) /*!< 0x00008000 */
+#define EXTI_EMR_MR15 EXTI_EMR_MR15_Msk /*!< Event Mask on line 15 */
+#define EXTI_EMR_MR16_Pos (16U)
+#define EXTI_EMR_MR16_Msk (0x1U << EXTI_EMR_MR16_Pos) /*!< 0x00010000 */
+#define EXTI_EMR_MR16 EXTI_EMR_MR16_Msk /*!< Event Mask on line 16 */
+#define EXTI_EMR_MR17_Pos (17U)
+#define EXTI_EMR_MR17_Msk (0x1U << EXTI_EMR_MR17_Pos) /*!< 0x00020000 */
+#define EXTI_EMR_MR17 EXTI_EMR_MR17_Msk /*!< Event Mask on line 17 */
+#define EXTI_EMR_MR18_Pos (18U)
+#define EXTI_EMR_MR18_Msk (0x1U << EXTI_EMR_MR18_Pos) /*!< 0x00040000 */
+#define EXTI_EMR_MR18 EXTI_EMR_MR18_Msk /*!< Event Mask on line 18 */
+#define EXTI_EMR_MR19_Pos (19U)
+#define EXTI_EMR_MR19_Msk (0x1U << EXTI_EMR_MR19_Pos) /*!< 0x00080000 */
+#define EXTI_EMR_MR19 EXTI_EMR_MR19_Msk /*!< Event Mask on line 19 */
+
+/* References Defines */
+#define EXTI_EMR_EM0 EXTI_EMR_MR0
+#define EXTI_EMR_EM1 EXTI_EMR_MR1
+#define EXTI_EMR_EM2 EXTI_EMR_MR2
+#define EXTI_EMR_EM3 EXTI_EMR_MR3
+#define EXTI_EMR_EM4 EXTI_EMR_MR4
+#define EXTI_EMR_EM5 EXTI_EMR_MR5
+#define EXTI_EMR_EM6 EXTI_EMR_MR6
+#define EXTI_EMR_EM7 EXTI_EMR_MR7
+#define EXTI_EMR_EM8 EXTI_EMR_MR8
+#define EXTI_EMR_EM9 EXTI_EMR_MR9
+#define EXTI_EMR_EM10 EXTI_EMR_MR10
+#define EXTI_EMR_EM11 EXTI_EMR_MR11
+#define EXTI_EMR_EM12 EXTI_EMR_MR12
+#define EXTI_EMR_EM13 EXTI_EMR_MR13
+#define EXTI_EMR_EM14 EXTI_EMR_MR14
+#define EXTI_EMR_EM15 EXTI_EMR_MR15
+#define EXTI_EMR_EM16 EXTI_EMR_MR16
+#define EXTI_EMR_EM17 EXTI_EMR_MR17
+#define EXTI_EMR_EM18 EXTI_EMR_MR18
+#define EXTI_EMR_EM19 EXTI_EMR_MR19
+
+/****************** Bit definition for EXTI_RTSR register *******************/
+#define EXTI_RTSR_TR0_Pos (0U)
+#define EXTI_RTSR_TR0_Msk (0x1U << EXTI_RTSR_TR0_Pos) /*!< 0x00000001 */
+#define EXTI_RTSR_TR0 EXTI_RTSR_TR0_Msk /*!< Rising trigger event configuration bit of line 0 */
+#define EXTI_RTSR_TR1_Pos (1U)
+#define EXTI_RTSR_TR1_Msk (0x1U << EXTI_RTSR_TR1_Pos) /*!< 0x00000002 */
+#define EXTI_RTSR_TR1 EXTI_RTSR_TR1_Msk /*!< Rising trigger event configuration bit of line 1 */
+#define EXTI_RTSR_TR2_Pos (2U)
+#define EXTI_RTSR_TR2_Msk (0x1U << EXTI_RTSR_TR2_Pos) /*!< 0x00000004 */
+#define EXTI_RTSR_TR2 EXTI_RTSR_TR2_Msk /*!< Rising trigger event configuration bit of line 2 */
+#define EXTI_RTSR_TR3_Pos (3U)
+#define EXTI_RTSR_TR3_Msk (0x1U << EXTI_RTSR_TR3_Pos) /*!< 0x00000008 */
+#define EXTI_RTSR_TR3 EXTI_RTSR_TR3_Msk /*!< Rising trigger event configuration bit of line 3 */
+#define EXTI_RTSR_TR4_Pos (4U)
+#define EXTI_RTSR_TR4_Msk (0x1U << EXTI_RTSR_TR4_Pos) /*!< 0x00000010 */
+#define EXTI_RTSR_TR4 EXTI_RTSR_TR4_Msk /*!< Rising trigger event configuration bit of line 4 */
+#define EXTI_RTSR_TR5_Pos (5U)
+#define EXTI_RTSR_TR5_Msk (0x1U << EXTI_RTSR_TR5_Pos) /*!< 0x00000020 */
+#define EXTI_RTSR_TR5 EXTI_RTSR_TR5_Msk /*!< Rising trigger event configuration bit of line 5 */
+#define EXTI_RTSR_TR6_Pos (6U)
+#define EXTI_RTSR_TR6_Msk (0x1U << EXTI_RTSR_TR6_Pos) /*!< 0x00000040 */
+#define EXTI_RTSR_TR6 EXTI_RTSR_TR6_Msk /*!< Rising trigger event configuration bit of line 6 */
+#define EXTI_RTSR_TR7_Pos (7U)
+#define EXTI_RTSR_TR7_Msk (0x1U << EXTI_RTSR_TR7_Pos) /*!< 0x00000080 */
+#define EXTI_RTSR_TR7 EXTI_RTSR_TR7_Msk /*!< Rising trigger event configuration bit of line 7 */
+#define EXTI_RTSR_TR8_Pos (8U)
+#define EXTI_RTSR_TR8_Msk (0x1U << EXTI_RTSR_TR8_Pos) /*!< 0x00000100 */
+#define EXTI_RTSR_TR8 EXTI_RTSR_TR8_Msk /*!< Rising trigger event configuration bit of line 8 */
+#define EXTI_RTSR_TR9_Pos (9U)
+#define EXTI_RTSR_TR9_Msk (0x1U << EXTI_RTSR_TR9_Pos) /*!< 0x00000200 */
+#define EXTI_RTSR_TR9 EXTI_RTSR_TR9_Msk /*!< Rising trigger event configuration bit of line 9 */
+#define EXTI_RTSR_TR10_Pos (10U)
+#define EXTI_RTSR_TR10_Msk (0x1U << EXTI_RTSR_TR10_Pos) /*!< 0x00000400 */
+#define EXTI_RTSR_TR10 EXTI_RTSR_TR10_Msk /*!< Rising trigger event configuration bit of line 10 */
+#define EXTI_RTSR_TR11_Pos (11U)
+#define EXTI_RTSR_TR11_Msk (0x1U << EXTI_RTSR_TR11_Pos) /*!< 0x00000800 */
+#define EXTI_RTSR_TR11 EXTI_RTSR_TR11_Msk /*!< Rising trigger event configuration bit of line 11 */
+#define EXTI_RTSR_TR12_Pos (12U)
+#define EXTI_RTSR_TR12_Msk (0x1U << EXTI_RTSR_TR12_Pos) /*!< 0x00001000 */
+#define EXTI_RTSR_TR12 EXTI_RTSR_TR12_Msk /*!< Rising trigger event configuration bit of line 12 */
+#define EXTI_RTSR_TR13_Pos (13U)
+#define EXTI_RTSR_TR13_Msk (0x1U << EXTI_RTSR_TR13_Pos) /*!< 0x00002000 */
+#define EXTI_RTSR_TR13 EXTI_RTSR_TR13_Msk /*!< Rising trigger event configuration bit of line 13 */
+#define EXTI_RTSR_TR14_Pos (14U)
+#define EXTI_RTSR_TR14_Msk (0x1U << EXTI_RTSR_TR14_Pos) /*!< 0x00004000 */
+#define EXTI_RTSR_TR14 EXTI_RTSR_TR14_Msk /*!< Rising trigger event configuration bit of line 14 */
+#define EXTI_RTSR_TR15_Pos (15U)
+#define EXTI_RTSR_TR15_Msk (0x1U << EXTI_RTSR_TR15_Pos) /*!< 0x00008000 */
+#define EXTI_RTSR_TR15 EXTI_RTSR_TR15_Msk /*!< Rising trigger event configuration bit of line 15 */
+#define EXTI_RTSR_TR16_Pos (16U)
+#define EXTI_RTSR_TR16_Msk (0x1U << EXTI_RTSR_TR16_Pos) /*!< 0x00010000 */
+#define EXTI_RTSR_TR16 EXTI_RTSR_TR16_Msk /*!< Rising trigger event configuration bit of line 16 */
+#define EXTI_RTSR_TR17_Pos (17U)
+#define EXTI_RTSR_TR17_Msk (0x1U << EXTI_RTSR_TR17_Pos) /*!< 0x00020000 */
+#define EXTI_RTSR_TR17 EXTI_RTSR_TR17_Msk /*!< Rising trigger event configuration bit of line 17 */
+#define EXTI_RTSR_TR18_Pos (18U)
+#define EXTI_RTSR_TR18_Msk (0x1U << EXTI_RTSR_TR18_Pos) /*!< 0x00040000 */
+#define EXTI_RTSR_TR18 EXTI_RTSR_TR18_Msk /*!< Rising trigger event configuration bit of line 18 */
+#define EXTI_RTSR_TR19_Pos (19U)
+#define EXTI_RTSR_TR19_Msk (0x1U << EXTI_RTSR_TR19_Pos) /*!< 0x00080000 */
+#define EXTI_RTSR_TR19 EXTI_RTSR_TR19_Msk /*!< Rising trigger event configuration bit of line 19 */
+
+/* References Defines */
+#define EXTI_RTSR_RT0 EXTI_RTSR_TR0
+#define EXTI_RTSR_RT1 EXTI_RTSR_TR1
+#define EXTI_RTSR_RT2 EXTI_RTSR_TR2
+#define EXTI_RTSR_RT3 EXTI_RTSR_TR3
+#define EXTI_RTSR_RT4 EXTI_RTSR_TR4
+#define EXTI_RTSR_RT5 EXTI_RTSR_TR5
+#define EXTI_RTSR_RT6 EXTI_RTSR_TR6
+#define EXTI_RTSR_RT7 EXTI_RTSR_TR7
+#define EXTI_RTSR_RT8 EXTI_RTSR_TR8
+#define EXTI_RTSR_RT9 EXTI_RTSR_TR9
+#define EXTI_RTSR_RT10 EXTI_RTSR_TR10
+#define EXTI_RTSR_RT11 EXTI_RTSR_TR11
+#define EXTI_RTSR_RT12 EXTI_RTSR_TR12
+#define EXTI_RTSR_RT13 EXTI_RTSR_TR13
+#define EXTI_RTSR_RT14 EXTI_RTSR_TR14
+#define EXTI_RTSR_RT15 EXTI_RTSR_TR15
+#define EXTI_RTSR_RT16 EXTI_RTSR_TR16
+#define EXTI_RTSR_RT17 EXTI_RTSR_TR17
+#define EXTI_RTSR_RT18 EXTI_RTSR_TR18
+#define EXTI_RTSR_RT19 EXTI_RTSR_TR19
+
+/****************** Bit definition for EXTI_FTSR register *******************/
+#define EXTI_FTSR_TR0_Pos (0U)
+#define EXTI_FTSR_TR0_Msk (0x1U << EXTI_FTSR_TR0_Pos) /*!< 0x00000001 */
+#define EXTI_FTSR_TR0 EXTI_FTSR_TR0_Msk /*!< Falling trigger event configuration bit of line 0 */
+#define EXTI_FTSR_TR1_Pos (1U)
+#define EXTI_FTSR_TR1_Msk (0x1U << EXTI_FTSR_TR1_Pos) /*!< 0x00000002 */
+#define EXTI_FTSR_TR1 EXTI_FTSR_TR1_Msk /*!< Falling trigger event configuration bit of line 1 */
+#define EXTI_FTSR_TR2_Pos (2U)
+#define EXTI_FTSR_TR2_Msk (0x1U << EXTI_FTSR_TR2_Pos) /*!< 0x00000004 */
+#define EXTI_FTSR_TR2 EXTI_FTSR_TR2_Msk /*!< Falling trigger event configuration bit of line 2 */
+#define EXTI_FTSR_TR3_Pos (3U)
+#define EXTI_FTSR_TR3_Msk (0x1U << EXTI_FTSR_TR3_Pos) /*!< 0x00000008 */
+#define EXTI_FTSR_TR3 EXTI_FTSR_TR3_Msk /*!< Falling trigger event configuration bit of line 3 */
+#define EXTI_FTSR_TR4_Pos (4U)
+#define EXTI_FTSR_TR4_Msk (0x1U << EXTI_FTSR_TR4_Pos) /*!< 0x00000010 */
+#define EXTI_FTSR_TR4 EXTI_FTSR_TR4_Msk /*!< Falling trigger event configuration bit of line 4 */
+#define EXTI_FTSR_TR5_Pos (5U)
+#define EXTI_FTSR_TR5_Msk (0x1U << EXTI_FTSR_TR5_Pos) /*!< 0x00000020 */
+#define EXTI_FTSR_TR5 EXTI_FTSR_TR5_Msk /*!< Falling trigger event configuration bit of line 5 */
+#define EXTI_FTSR_TR6_Pos (6U)
+#define EXTI_FTSR_TR6_Msk (0x1U << EXTI_FTSR_TR6_Pos) /*!< 0x00000040 */
+#define EXTI_FTSR_TR6 EXTI_FTSR_TR6_Msk /*!< Falling trigger event configuration bit of line 6 */
+#define EXTI_FTSR_TR7_Pos (7U)
+#define EXTI_FTSR_TR7_Msk (0x1U << EXTI_FTSR_TR7_Pos) /*!< 0x00000080 */
+#define EXTI_FTSR_TR7 EXTI_FTSR_TR7_Msk /*!< Falling trigger event configuration bit of line 7 */
+#define EXTI_FTSR_TR8_Pos (8U)
+#define EXTI_FTSR_TR8_Msk (0x1U << EXTI_FTSR_TR8_Pos) /*!< 0x00000100 */
+#define EXTI_FTSR_TR8 EXTI_FTSR_TR8_Msk /*!< Falling trigger event configuration bit of line 8 */
+#define EXTI_FTSR_TR9_Pos (9U)
+#define EXTI_FTSR_TR9_Msk (0x1U << EXTI_FTSR_TR9_Pos) /*!< 0x00000200 */
+#define EXTI_FTSR_TR9 EXTI_FTSR_TR9_Msk /*!< Falling trigger event configuration bit of line 9 */
+#define EXTI_FTSR_TR10_Pos (10U)
+#define EXTI_FTSR_TR10_Msk (0x1U << EXTI_FTSR_TR10_Pos) /*!< 0x00000400 */
+#define EXTI_FTSR_TR10 EXTI_FTSR_TR10_Msk /*!< Falling trigger event configuration bit of line 10 */
+#define EXTI_FTSR_TR11_Pos (11U)
+#define EXTI_FTSR_TR11_Msk (0x1U << EXTI_FTSR_TR11_Pos) /*!< 0x00000800 */
+#define EXTI_FTSR_TR11 EXTI_FTSR_TR11_Msk /*!< Falling trigger event configuration bit of line 11 */
+#define EXTI_FTSR_TR12_Pos (12U)
+#define EXTI_FTSR_TR12_Msk (0x1U << EXTI_FTSR_TR12_Pos) /*!< 0x00001000 */
+#define EXTI_FTSR_TR12 EXTI_FTSR_TR12_Msk /*!< Falling trigger event configuration bit of line 12 */
+#define EXTI_FTSR_TR13_Pos (13U)
+#define EXTI_FTSR_TR13_Msk (0x1U << EXTI_FTSR_TR13_Pos) /*!< 0x00002000 */
+#define EXTI_FTSR_TR13 EXTI_FTSR_TR13_Msk /*!< Falling trigger event configuration bit of line 13 */
+#define EXTI_FTSR_TR14_Pos (14U)
+#define EXTI_FTSR_TR14_Msk (0x1U << EXTI_FTSR_TR14_Pos) /*!< 0x00004000 */
+#define EXTI_FTSR_TR14 EXTI_FTSR_TR14_Msk /*!< Falling trigger event configuration bit of line 14 */
+#define EXTI_FTSR_TR15_Pos (15U)
+#define EXTI_FTSR_TR15_Msk (0x1U << EXTI_FTSR_TR15_Pos) /*!< 0x00008000 */
+#define EXTI_FTSR_TR15 EXTI_FTSR_TR15_Msk /*!< Falling trigger event configuration bit of line 15 */
+#define EXTI_FTSR_TR16_Pos (16U)
+#define EXTI_FTSR_TR16_Msk (0x1U << EXTI_FTSR_TR16_Pos) /*!< 0x00010000 */
+#define EXTI_FTSR_TR16 EXTI_FTSR_TR16_Msk /*!< Falling trigger event configuration bit of line 16 */
+#define EXTI_FTSR_TR17_Pos (17U)
+#define EXTI_FTSR_TR17_Msk (0x1U << EXTI_FTSR_TR17_Pos) /*!< 0x00020000 */
+#define EXTI_FTSR_TR17 EXTI_FTSR_TR17_Msk /*!< Falling trigger event configuration bit of line 17 */
+#define EXTI_FTSR_TR18_Pos (18U)
+#define EXTI_FTSR_TR18_Msk (0x1U << EXTI_FTSR_TR18_Pos) /*!< 0x00040000 */
+#define EXTI_FTSR_TR18 EXTI_FTSR_TR18_Msk /*!< Falling trigger event configuration bit of line 18 */
+#define EXTI_FTSR_TR19_Pos (19U)
+#define EXTI_FTSR_TR19_Msk (0x1U << EXTI_FTSR_TR19_Pos) /*!< 0x00080000 */
+#define EXTI_FTSR_TR19 EXTI_FTSR_TR19_Msk /*!< Falling trigger event configuration bit of line 19 */
+
+/* References Defines */
+#define EXTI_FTSR_FT0 EXTI_FTSR_TR0
+#define EXTI_FTSR_FT1 EXTI_FTSR_TR1
+#define EXTI_FTSR_FT2 EXTI_FTSR_TR2
+#define EXTI_FTSR_FT3 EXTI_FTSR_TR3
+#define EXTI_FTSR_FT4 EXTI_FTSR_TR4
+#define EXTI_FTSR_FT5 EXTI_FTSR_TR5
+#define EXTI_FTSR_FT6 EXTI_FTSR_TR6
+#define EXTI_FTSR_FT7 EXTI_FTSR_TR7
+#define EXTI_FTSR_FT8 EXTI_FTSR_TR8
+#define EXTI_FTSR_FT9 EXTI_FTSR_TR9
+#define EXTI_FTSR_FT10 EXTI_FTSR_TR10
+#define EXTI_FTSR_FT11 EXTI_FTSR_TR11
+#define EXTI_FTSR_FT12 EXTI_FTSR_TR12
+#define EXTI_FTSR_FT13 EXTI_FTSR_TR13
+#define EXTI_FTSR_FT14 EXTI_FTSR_TR14
+#define EXTI_FTSR_FT15 EXTI_FTSR_TR15
+#define EXTI_FTSR_FT16 EXTI_FTSR_TR16
+#define EXTI_FTSR_FT17 EXTI_FTSR_TR17
+#define EXTI_FTSR_FT18 EXTI_FTSR_TR18
+#define EXTI_FTSR_FT19 EXTI_FTSR_TR19
+
+/****************** Bit definition for EXTI_SWIER register ******************/
+#define EXTI_SWIER_SWIER0_Pos (0U)
+#define EXTI_SWIER_SWIER0_Msk (0x1U << EXTI_SWIER_SWIER0_Pos) /*!< 0x00000001 */
+#define EXTI_SWIER_SWIER0 EXTI_SWIER_SWIER0_Msk /*!< Software Interrupt on line 0 */
+#define EXTI_SWIER_SWIER1_Pos (1U)
+#define EXTI_SWIER_SWIER1_Msk (0x1U << EXTI_SWIER_SWIER1_Pos) /*!< 0x00000002 */
+#define EXTI_SWIER_SWIER1 EXTI_SWIER_SWIER1_Msk /*!< Software Interrupt on line 1 */
+#define EXTI_SWIER_SWIER2_Pos (2U)
+#define EXTI_SWIER_SWIER2_Msk (0x1U << EXTI_SWIER_SWIER2_Pos) /*!< 0x00000004 */
+#define EXTI_SWIER_SWIER2 EXTI_SWIER_SWIER2_Msk /*!< Software Interrupt on line 2 */
+#define EXTI_SWIER_SWIER3_Pos (3U)
+#define EXTI_SWIER_SWIER3_Msk (0x1U << EXTI_SWIER_SWIER3_Pos) /*!< 0x00000008 */
+#define EXTI_SWIER_SWIER3 EXTI_SWIER_SWIER3_Msk /*!< Software Interrupt on line 3 */
+#define EXTI_SWIER_SWIER4_Pos (4U)
+#define EXTI_SWIER_SWIER4_Msk (0x1U << EXTI_SWIER_SWIER4_Pos) /*!< 0x00000010 */
+#define EXTI_SWIER_SWIER4 EXTI_SWIER_SWIER4_Msk /*!< Software Interrupt on line 4 */
+#define EXTI_SWIER_SWIER5_Pos (5U)
+#define EXTI_SWIER_SWIER5_Msk (0x1U << EXTI_SWIER_SWIER5_Pos) /*!< 0x00000020 */
+#define EXTI_SWIER_SWIER5 EXTI_SWIER_SWIER5_Msk /*!< Software Interrupt on line 5 */
+#define EXTI_SWIER_SWIER6_Pos (6U)
+#define EXTI_SWIER_SWIER6_Msk (0x1U << EXTI_SWIER_SWIER6_Pos) /*!< 0x00000040 */
+#define EXTI_SWIER_SWIER6 EXTI_SWIER_SWIER6_Msk /*!< Software Interrupt on line 6 */
+#define EXTI_SWIER_SWIER7_Pos (7U)
+#define EXTI_SWIER_SWIER7_Msk (0x1U << EXTI_SWIER_SWIER7_Pos) /*!< 0x00000080 */
+#define EXTI_SWIER_SWIER7 EXTI_SWIER_SWIER7_Msk /*!< Software Interrupt on line 7 */
+#define EXTI_SWIER_SWIER8_Pos (8U)
+#define EXTI_SWIER_SWIER8_Msk (0x1U << EXTI_SWIER_SWIER8_Pos) /*!< 0x00000100 */
+#define EXTI_SWIER_SWIER8 EXTI_SWIER_SWIER8_Msk /*!< Software Interrupt on line 8 */
+#define EXTI_SWIER_SWIER9_Pos (9U)
+#define EXTI_SWIER_SWIER9_Msk (0x1U << EXTI_SWIER_SWIER9_Pos) /*!< 0x00000200 */
+#define EXTI_SWIER_SWIER9 EXTI_SWIER_SWIER9_Msk /*!< Software Interrupt on line 9 */
+#define EXTI_SWIER_SWIER10_Pos (10U)
+#define EXTI_SWIER_SWIER10_Msk (0x1U << EXTI_SWIER_SWIER10_Pos) /*!< 0x00000400 */
+#define EXTI_SWIER_SWIER10 EXTI_SWIER_SWIER10_Msk /*!< Software Interrupt on line 10 */
+#define EXTI_SWIER_SWIER11_Pos (11U)
+#define EXTI_SWIER_SWIER11_Msk (0x1U << EXTI_SWIER_SWIER11_Pos) /*!< 0x00000800 */
+#define EXTI_SWIER_SWIER11 EXTI_SWIER_SWIER11_Msk /*!< Software Interrupt on line 11 */
+#define EXTI_SWIER_SWIER12_Pos (12U)
+#define EXTI_SWIER_SWIER12_Msk (0x1U << EXTI_SWIER_SWIER12_Pos) /*!< 0x00001000 */
+#define EXTI_SWIER_SWIER12 EXTI_SWIER_SWIER12_Msk /*!< Software Interrupt on line 12 */
+#define EXTI_SWIER_SWIER13_Pos (13U)
+#define EXTI_SWIER_SWIER13_Msk (0x1U << EXTI_SWIER_SWIER13_Pos) /*!< 0x00002000 */
+#define EXTI_SWIER_SWIER13 EXTI_SWIER_SWIER13_Msk /*!< Software Interrupt on line 13 */
+#define EXTI_SWIER_SWIER14_Pos (14U)
+#define EXTI_SWIER_SWIER14_Msk (0x1U << EXTI_SWIER_SWIER14_Pos) /*!< 0x00004000 */
+#define EXTI_SWIER_SWIER14 EXTI_SWIER_SWIER14_Msk /*!< Software Interrupt on line 14 */
+#define EXTI_SWIER_SWIER15_Pos (15U)
+#define EXTI_SWIER_SWIER15_Msk (0x1U << EXTI_SWIER_SWIER15_Pos) /*!< 0x00008000 */
+#define EXTI_SWIER_SWIER15 EXTI_SWIER_SWIER15_Msk /*!< Software Interrupt on line 15 */
+#define EXTI_SWIER_SWIER16_Pos (16U)
+#define EXTI_SWIER_SWIER16_Msk (0x1U << EXTI_SWIER_SWIER16_Pos) /*!< 0x00010000 */
+#define EXTI_SWIER_SWIER16 EXTI_SWIER_SWIER16_Msk /*!< Software Interrupt on line 16 */
+#define EXTI_SWIER_SWIER17_Pos (17U)
+#define EXTI_SWIER_SWIER17_Msk (0x1U << EXTI_SWIER_SWIER17_Pos) /*!< 0x00020000 */
+#define EXTI_SWIER_SWIER17 EXTI_SWIER_SWIER17_Msk /*!< Software Interrupt on line 17 */
+#define EXTI_SWIER_SWIER18_Pos (18U)
+#define EXTI_SWIER_SWIER18_Msk (0x1U << EXTI_SWIER_SWIER18_Pos) /*!< 0x00040000 */
+#define EXTI_SWIER_SWIER18 EXTI_SWIER_SWIER18_Msk /*!< Software Interrupt on line 18 */
+#define EXTI_SWIER_SWIER19_Pos (19U)
+#define EXTI_SWIER_SWIER19_Msk (0x1U << EXTI_SWIER_SWIER19_Pos) /*!< 0x00080000 */
+#define EXTI_SWIER_SWIER19 EXTI_SWIER_SWIER19_Msk /*!< Software Interrupt on line 19 */
+
+/* References Defines */
+#define EXTI_SWIER_SWI0 EXTI_SWIER_SWIER0
+#define EXTI_SWIER_SWI1 EXTI_SWIER_SWIER1
+#define EXTI_SWIER_SWI2 EXTI_SWIER_SWIER2
+#define EXTI_SWIER_SWI3 EXTI_SWIER_SWIER3
+#define EXTI_SWIER_SWI4 EXTI_SWIER_SWIER4
+#define EXTI_SWIER_SWI5 EXTI_SWIER_SWIER5
+#define EXTI_SWIER_SWI6 EXTI_SWIER_SWIER6
+#define EXTI_SWIER_SWI7 EXTI_SWIER_SWIER7
+#define EXTI_SWIER_SWI8 EXTI_SWIER_SWIER8
+#define EXTI_SWIER_SWI9 EXTI_SWIER_SWIER9
+#define EXTI_SWIER_SWI10 EXTI_SWIER_SWIER10
+#define EXTI_SWIER_SWI11 EXTI_SWIER_SWIER11
+#define EXTI_SWIER_SWI12 EXTI_SWIER_SWIER12
+#define EXTI_SWIER_SWI13 EXTI_SWIER_SWIER13
+#define EXTI_SWIER_SWI14 EXTI_SWIER_SWIER14
+#define EXTI_SWIER_SWI15 EXTI_SWIER_SWIER15
+#define EXTI_SWIER_SWI16 EXTI_SWIER_SWIER16
+#define EXTI_SWIER_SWI17 EXTI_SWIER_SWIER17
+#define EXTI_SWIER_SWI18 EXTI_SWIER_SWIER18
+#define EXTI_SWIER_SWI19 EXTI_SWIER_SWIER19
+
+/******************* Bit definition for EXTI_PR register ********************/
+#define EXTI_PR_PR0_Pos (0U)
+#define EXTI_PR_PR0_Msk (0x1U << EXTI_PR_PR0_Pos) /*!< 0x00000001 */
+#define EXTI_PR_PR0 EXTI_PR_PR0_Msk /*!< Pending bit for line 0 */
+#define EXTI_PR_PR1_Pos (1U)
+#define EXTI_PR_PR1_Msk (0x1U << EXTI_PR_PR1_Pos) /*!< 0x00000002 */
+#define EXTI_PR_PR1 EXTI_PR_PR1_Msk /*!< Pending bit for line 1 */
+#define EXTI_PR_PR2_Pos (2U)
+#define EXTI_PR_PR2_Msk (0x1U << EXTI_PR_PR2_Pos) /*!< 0x00000004 */
+#define EXTI_PR_PR2 EXTI_PR_PR2_Msk /*!< Pending bit for line 2 */
+#define EXTI_PR_PR3_Pos (3U)
+#define EXTI_PR_PR3_Msk (0x1U << EXTI_PR_PR3_Pos) /*!< 0x00000008 */
+#define EXTI_PR_PR3 EXTI_PR_PR3_Msk /*!< Pending bit for line 3 */
+#define EXTI_PR_PR4_Pos (4U)
+#define EXTI_PR_PR4_Msk (0x1U << EXTI_PR_PR4_Pos) /*!< 0x00000010 */
+#define EXTI_PR_PR4 EXTI_PR_PR4_Msk /*!< Pending bit for line 4 */
+#define EXTI_PR_PR5_Pos (5U)
+#define EXTI_PR_PR5_Msk (0x1U << EXTI_PR_PR5_Pos) /*!< 0x00000020 */
+#define EXTI_PR_PR5 EXTI_PR_PR5_Msk /*!< Pending bit for line 5 */
+#define EXTI_PR_PR6_Pos (6U)
+#define EXTI_PR_PR6_Msk (0x1U << EXTI_PR_PR6_Pos) /*!< 0x00000040 */
+#define EXTI_PR_PR6 EXTI_PR_PR6_Msk /*!< Pending bit for line 6 */
+#define EXTI_PR_PR7_Pos (7U)
+#define EXTI_PR_PR7_Msk (0x1U << EXTI_PR_PR7_Pos) /*!< 0x00000080 */
+#define EXTI_PR_PR7 EXTI_PR_PR7_Msk /*!< Pending bit for line 7 */
+#define EXTI_PR_PR8_Pos (8U)
+#define EXTI_PR_PR8_Msk (0x1U << EXTI_PR_PR8_Pos) /*!< 0x00000100 */
+#define EXTI_PR_PR8 EXTI_PR_PR8_Msk /*!< Pending bit for line 8 */
+#define EXTI_PR_PR9_Pos (9U)
+#define EXTI_PR_PR9_Msk (0x1U << EXTI_PR_PR9_Pos) /*!< 0x00000200 */
+#define EXTI_PR_PR9 EXTI_PR_PR9_Msk /*!< Pending bit for line 9 */
+#define EXTI_PR_PR10_Pos (10U)
+#define EXTI_PR_PR10_Msk (0x1U << EXTI_PR_PR10_Pos) /*!< 0x00000400 */
+#define EXTI_PR_PR10 EXTI_PR_PR10_Msk /*!< Pending bit for line 10 */
+#define EXTI_PR_PR11_Pos (11U)
+#define EXTI_PR_PR11_Msk (0x1U << EXTI_PR_PR11_Pos) /*!< 0x00000800 */
+#define EXTI_PR_PR11 EXTI_PR_PR11_Msk /*!< Pending bit for line 11 */
+#define EXTI_PR_PR12_Pos (12U)
+#define EXTI_PR_PR12_Msk (0x1U << EXTI_PR_PR12_Pos) /*!< 0x00001000 */
+#define EXTI_PR_PR12 EXTI_PR_PR12_Msk /*!< Pending bit for line 12 */
+#define EXTI_PR_PR13_Pos (13U)
+#define EXTI_PR_PR13_Msk (0x1U << EXTI_PR_PR13_Pos) /*!< 0x00002000 */
+#define EXTI_PR_PR13 EXTI_PR_PR13_Msk /*!< Pending bit for line 13 */
+#define EXTI_PR_PR14_Pos (14U)
+#define EXTI_PR_PR14_Msk (0x1U << EXTI_PR_PR14_Pos) /*!< 0x00004000 */
+#define EXTI_PR_PR14 EXTI_PR_PR14_Msk /*!< Pending bit for line 14 */
+#define EXTI_PR_PR15_Pos (15U)
+#define EXTI_PR_PR15_Msk (0x1U << EXTI_PR_PR15_Pos) /*!< 0x00008000 */
+#define EXTI_PR_PR15 EXTI_PR_PR15_Msk /*!< Pending bit for line 15 */
+#define EXTI_PR_PR16_Pos (16U)
+#define EXTI_PR_PR16_Msk (0x1U << EXTI_PR_PR16_Pos) /*!< 0x00010000 */
+#define EXTI_PR_PR16 EXTI_PR_PR16_Msk /*!< Pending bit for line 16 */
+#define EXTI_PR_PR17_Pos (17U)
+#define EXTI_PR_PR17_Msk (0x1U << EXTI_PR_PR17_Pos) /*!< 0x00020000 */
+#define EXTI_PR_PR17 EXTI_PR_PR17_Msk /*!< Pending bit for line 17 */
+#define EXTI_PR_PR18_Pos (18U)
+#define EXTI_PR_PR18_Msk (0x1U << EXTI_PR_PR18_Pos) /*!< 0x00040000 */
+#define EXTI_PR_PR18 EXTI_PR_PR18_Msk /*!< Pending bit for line 18 */
+#define EXTI_PR_PR19_Pos (19U)
+#define EXTI_PR_PR19_Msk (0x1U << EXTI_PR_PR19_Pos) /*!< 0x00080000 */
+#define EXTI_PR_PR19 EXTI_PR_PR19_Msk /*!< Pending bit for line 19 */
+
+/* References Defines */
+#define EXTI_PR_PIF0 EXTI_PR_PR0
+#define EXTI_PR_PIF1 EXTI_PR_PR1
+#define EXTI_PR_PIF2 EXTI_PR_PR2
+#define EXTI_PR_PIF3 EXTI_PR_PR3
+#define EXTI_PR_PIF4 EXTI_PR_PR4
+#define EXTI_PR_PIF5 EXTI_PR_PR5
+#define EXTI_PR_PIF6 EXTI_PR_PR6
+#define EXTI_PR_PIF7 EXTI_PR_PR7
+#define EXTI_PR_PIF8 EXTI_PR_PR8
+#define EXTI_PR_PIF9 EXTI_PR_PR9
+#define EXTI_PR_PIF10 EXTI_PR_PR10
+#define EXTI_PR_PIF11 EXTI_PR_PR11
+#define EXTI_PR_PIF12 EXTI_PR_PR12
+#define EXTI_PR_PIF13 EXTI_PR_PR13
+#define EXTI_PR_PIF14 EXTI_PR_PR14
+#define EXTI_PR_PIF15 EXTI_PR_PR15
+#define EXTI_PR_PIF16 EXTI_PR_PR16
+#define EXTI_PR_PIF17 EXTI_PR_PR17
+#define EXTI_PR_PIF18 EXTI_PR_PR18
+#define EXTI_PR_PIF19 EXTI_PR_PR19
+
+/******************************************************************************/
+/* */
+/* DMA Controller */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for DMA_ISR register ********************/
+#define DMA_ISR_GIF1_Pos (0U)
+#define DMA_ISR_GIF1_Msk (0x1U << DMA_ISR_GIF1_Pos) /*!< 0x00000001 */
+#define DMA_ISR_GIF1 DMA_ISR_GIF1_Msk /*!< Channel 1 Global interrupt flag */
+#define DMA_ISR_TCIF1_Pos (1U)
+#define DMA_ISR_TCIF1_Msk (0x1U << DMA_ISR_TCIF1_Pos) /*!< 0x00000002 */
+#define DMA_ISR_TCIF1 DMA_ISR_TCIF1_Msk /*!< Channel 1 Transfer Complete flag */
+#define DMA_ISR_HTIF1_Pos (2U)
+#define DMA_ISR_HTIF1_Msk (0x1U << DMA_ISR_HTIF1_Pos) /*!< 0x00000004 */
+#define DMA_ISR_HTIF1 DMA_ISR_HTIF1_Msk /*!< Channel 1 Half Transfer flag */
+#define DMA_ISR_TEIF1_Pos (3U)
+#define DMA_ISR_TEIF1_Msk (0x1U << DMA_ISR_TEIF1_Pos) /*!< 0x00000008 */
+#define DMA_ISR_TEIF1 DMA_ISR_TEIF1_Msk /*!< Channel 1 Transfer Error flag */
+#define DMA_ISR_GIF2_Pos (4U)
+#define DMA_ISR_GIF2_Msk (0x1U << DMA_ISR_GIF2_Pos) /*!< 0x00000010 */
+#define DMA_ISR_GIF2 DMA_ISR_GIF2_Msk /*!< Channel 2 Global interrupt flag */
+#define DMA_ISR_TCIF2_Pos (5U)
+#define DMA_ISR_TCIF2_Msk (0x1U << DMA_ISR_TCIF2_Pos) /*!< 0x00000020 */
+#define DMA_ISR_TCIF2 DMA_ISR_TCIF2_Msk /*!< Channel 2 Transfer Complete flag */
+#define DMA_ISR_HTIF2_Pos (6U)
+#define DMA_ISR_HTIF2_Msk (0x1U << DMA_ISR_HTIF2_Pos) /*!< 0x00000040 */
+#define DMA_ISR_HTIF2 DMA_ISR_HTIF2_Msk /*!< Channel 2 Half Transfer flag */
+#define DMA_ISR_TEIF2_Pos (7U)
+#define DMA_ISR_TEIF2_Msk (0x1U << DMA_ISR_TEIF2_Pos) /*!< 0x00000080 */
+#define DMA_ISR_TEIF2 DMA_ISR_TEIF2_Msk /*!< Channel 2 Transfer Error flag */
+#define DMA_ISR_GIF3_Pos (8U)
+#define DMA_ISR_GIF3_Msk (0x1U << DMA_ISR_GIF3_Pos) /*!< 0x00000100 */
+#define DMA_ISR_GIF3 DMA_ISR_GIF3_Msk /*!< Channel 3 Global interrupt flag */
+#define DMA_ISR_TCIF3_Pos (9U)
+#define DMA_ISR_TCIF3_Msk (0x1U << DMA_ISR_TCIF3_Pos) /*!< 0x00000200 */
+#define DMA_ISR_TCIF3 DMA_ISR_TCIF3_Msk /*!< Channel 3 Transfer Complete flag */
+#define DMA_ISR_HTIF3_Pos (10U)
+#define DMA_ISR_HTIF3_Msk (0x1U << DMA_ISR_HTIF3_Pos) /*!< 0x00000400 */
+#define DMA_ISR_HTIF3 DMA_ISR_HTIF3_Msk /*!< Channel 3 Half Transfer flag */
+#define DMA_ISR_TEIF3_Pos (11U)
+#define DMA_ISR_TEIF3_Msk (0x1U << DMA_ISR_TEIF3_Pos) /*!< 0x00000800 */
+#define DMA_ISR_TEIF3 DMA_ISR_TEIF3_Msk /*!< Channel 3 Transfer Error flag */
+#define DMA_ISR_GIF4_Pos (12U)
+#define DMA_ISR_GIF4_Msk (0x1U << DMA_ISR_GIF4_Pos) /*!< 0x00001000 */
+#define DMA_ISR_GIF4 DMA_ISR_GIF4_Msk /*!< Channel 4 Global interrupt flag */
+#define DMA_ISR_TCIF4_Pos (13U)
+#define DMA_ISR_TCIF4_Msk (0x1U << DMA_ISR_TCIF4_Pos) /*!< 0x00002000 */
+#define DMA_ISR_TCIF4 DMA_ISR_TCIF4_Msk /*!< Channel 4 Transfer Complete flag */
+#define DMA_ISR_HTIF4_Pos (14U)
+#define DMA_ISR_HTIF4_Msk (0x1U << DMA_ISR_HTIF4_Pos) /*!< 0x00004000 */
+#define DMA_ISR_HTIF4 DMA_ISR_HTIF4_Msk /*!< Channel 4 Half Transfer flag */
+#define DMA_ISR_TEIF4_Pos (15U)
+#define DMA_ISR_TEIF4_Msk (0x1U << DMA_ISR_TEIF4_Pos) /*!< 0x00008000 */
+#define DMA_ISR_TEIF4 DMA_ISR_TEIF4_Msk /*!< Channel 4 Transfer Error flag */
+#define DMA_ISR_GIF5_Pos (16U)
+#define DMA_ISR_GIF5_Msk (0x1U << DMA_ISR_GIF5_Pos) /*!< 0x00010000 */
+#define DMA_ISR_GIF5 DMA_ISR_GIF5_Msk /*!< Channel 5 Global interrupt flag */
+#define DMA_ISR_TCIF5_Pos (17U)
+#define DMA_ISR_TCIF5_Msk (0x1U << DMA_ISR_TCIF5_Pos) /*!< 0x00020000 */
+#define DMA_ISR_TCIF5 DMA_ISR_TCIF5_Msk /*!< Channel 5 Transfer Complete flag */
+#define DMA_ISR_HTIF5_Pos (18U)
+#define DMA_ISR_HTIF5_Msk (0x1U << DMA_ISR_HTIF5_Pos) /*!< 0x00040000 */
+#define DMA_ISR_HTIF5 DMA_ISR_HTIF5_Msk /*!< Channel 5 Half Transfer flag */
+#define DMA_ISR_TEIF5_Pos (19U)
+#define DMA_ISR_TEIF5_Msk (0x1U << DMA_ISR_TEIF5_Pos) /*!< 0x00080000 */
+#define DMA_ISR_TEIF5 DMA_ISR_TEIF5_Msk /*!< Channel 5 Transfer Error flag */
+#define DMA_ISR_GIF6_Pos (20U)
+#define DMA_ISR_GIF6_Msk (0x1U << DMA_ISR_GIF6_Pos) /*!< 0x00100000 */
+#define DMA_ISR_GIF6 DMA_ISR_GIF6_Msk /*!< Channel 6 Global interrupt flag */
+#define DMA_ISR_TCIF6_Pos (21U)
+#define DMA_ISR_TCIF6_Msk (0x1U << DMA_ISR_TCIF6_Pos) /*!< 0x00200000 */
+#define DMA_ISR_TCIF6 DMA_ISR_TCIF6_Msk /*!< Channel 6 Transfer Complete flag */
+#define DMA_ISR_HTIF6_Pos (22U)
+#define DMA_ISR_HTIF6_Msk (0x1U << DMA_ISR_HTIF6_Pos) /*!< 0x00400000 */
+#define DMA_ISR_HTIF6 DMA_ISR_HTIF6_Msk /*!< Channel 6 Half Transfer flag */
+#define DMA_ISR_TEIF6_Pos (23U)
+#define DMA_ISR_TEIF6_Msk (0x1U << DMA_ISR_TEIF6_Pos) /*!< 0x00800000 */
+#define DMA_ISR_TEIF6 DMA_ISR_TEIF6_Msk /*!< Channel 6 Transfer Error flag */
+#define DMA_ISR_GIF7_Pos (24U)
+#define DMA_ISR_GIF7_Msk (0x1U << DMA_ISR_GIF7_Pos) /*!< 0x01000000 */
+#define DMA_ISR_GIF7 DMA_ISR_GIF7_Msk /*!< Channel 7 Global interrupt flag */
+#define DMA_ISR_TCIF7_Pos (25U)
+#define DMA_ISR_TCIF7_Msk (0x1U << DMA_ISR_TCIF7_Pos) /*!< 0x02000000 */
+#define DMA_ISR_TCIF7 DMA_ISR_TCIF7_Msk /*!< Channel 7 Transfer Complete flag */
+#define DMA_ISR_HTIF7_Pos (26U)
+#define DMA_ISR_HTIF7_Msk (0x1U << DMA_ISR_HTIF7_Pos) /*!< 0x04000000 */
+#define DMA_ISR_HTIF7 DMA_ISR_HTIF7_Msk /*!< Channel 7 Half Transfer flag */
+#define DMA_ISR_TEIF7_Pos (27U)
+#define DMA_ISR_TEIF7_Msk (0x1U << DMA_ISR_TEIF7_Pos) /*!< 0x08000000 */
+#define DMA_ISR_TEIF7 DMA_ISR_TEIF7_Msk /*!< Channel 7 Transfer Error flag */
+
+/******************* Bit definition for DMA_IFCR register *******************/
+#define DMA_IFCR_CGIF1_Pos (0U)
+#define DMA_IFCR_CGIF1_Msk (0x1U << DMA_IFCR_CGIF1_Pos) /*!< 0x00000001 */
+#define DMA_IFCR_CGIF1 DMA_IFCR_CGIF1_Msk /*!< Channel 1 Global interrupt clear */
+#define DMA_IFCR_CTCIF1_Pos (1U)
+#define DMA_IFCR_CTCIF1_Msk (0x1U << DMA_IFCR_CTCIF1_Pos) /*!< 0x00000002 */
+#define DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF1_Msk /*!< Channel 1 Transfer Complete clear */
+#define DMA_IFCR_CHTIF1_Pos (2U)
+#define DMA_IFCR_CHTIF1_Msk (0x1U << DMA_IFCR_CHTIF1_Pos) /*!< 0x00000004 */
+#define DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF1_Msk /*!< Channel 1 Half Transfer clear */
+#define DMA_IFCR_CTEIF1_Pos (3U)
+#define DMA_IFCR_CTEIF1_Msk (0x1U << DMA_IFCR_CTEIF1_Pos) /*!< 0x00000008 */
+#define DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF1_Msk /*!< Channel 1 Transfer Error clear */
+#define DMA_IFCR_CGIF2_Pos (4U)
+#define DMA_IFCR_CGIF2_Msk (0x1U << DMA_IFCR_CGIF2_Pos) /*!< 0x00000010 */
+#define DMA_IFCR_CGIF2 DMA_IFCR_CGIF2_Msk /*!< Channel 2 Global interrupt clear */
+#define DMA_IFCR_CTCIF2_Pos (5U)
+#define DMA_IFCR_CTCIF2_Msk (0x1U << DMA_IFCR_CTCIF2_Pos) /*!< 0x00000020 */
+#define DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF2_Msk /*!< Channel 2 Transfer Complete clear */
+#define DMA_IFCR_CHTIF2_Pos (6U)
+#define DMA_IFCR_CHTIF2_Msk (0x1U << DMA_IFCR_CHTIF2_Pos) /*!< 0x00000040 */
+#define DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF2_Msk /*!< Channel 2 Half Transfer clear */
+#define DMA_IFCR_CTEIF2_Pos (7U)
+#define DMA_IFCR_CTEIF2_Msk (0x1U << DMA_IFCR_CTEIF2_Pos) /*!< 0x00000080 */
+#define DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF2_Msk /*!< Channel 2 Transfer Error clear */
+#define DMA_IFCR_CGIF3_Pos (8U)
+#define DMA_IFCR_CGIF3_Msk (0x1U << DMA_IFCR_CGIF3_Pos) /*!< 0x00000100 */
+#define DMA_IFCR_CGIF3 DMA_IFCR_CGIF3_Msk /*!< Channel 3 Global interrupt clear */
+#define DMA_IFCR_CTCIF3_Pos (9U)
+#define DMA_IFCR_CTCIF3_Msk (0x1U << DMA_IFCR_CTCIF3_Pos) /*!< 0x00000200 */
+#define DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF3_Msk /*!< Channel 3 Transfer Complete clear */
+#define DMA_IFCR_CHTIF3_Pos (10U)
+#define DMA_IFCR_CHTIF3_Msk (0x1U << DMA_IFCR_CHTIF3_Pos) /*!< 0x00000400 */
+#define DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF3_Msk /*!< Channel 3 Half Transfer clear */
+#define DMA_IFCR_CTEIF3_Pos (11U)
+#define DMA_IFCR_CTEIF3_Msk (0x1U << DMA_IFCR_CTEIF3_Pos) /*!< 0x00000800 */
+#define DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF3_Msk /*!< Channel 3 Transfer Error clear */
+#define DMA_IFCR_CGIF4_Pos (12U)
+#define DMA_IFCR_CGIF4_Msk (0x1U << DMA_IFCR_CGIF4_Pos) /*!< 0x00001000 */
+#define DMA_IFCR_CGIF4 DMA_IFCR_CGIF4_Msk /*!< Channel 4 Global interrupt clear */
+#define DMA_IFCR_CTCIF4_Pos (13U)
+#define DMA_IFCR_CTCIF4_Msk (0x1U << DMA_IFCR_CTCIF4_Pos) /*!< 0x00002000 */
+#define DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF4_Msk /*!< Channel 4 Transfer Complete clear */
+#define DMA_IFCR_CHTIF4_Pos (14U)
+#define DMA_IFCR_CHTIF4_Msk (0x1U << DMA_IFCR_CHTIF4_Pos) /*!< 0x00004000 */
+#define DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF4_Msk /*!< Channel 4 Half Transfer clear */
+#define DMA_IFCR_CTEIF4_Pos (15U)
+#define DMA_IFCR_CTEIF4_Msk (0x1U << DMA_IFCR_CTEIF4_Pos) /*!< 0x00008000 */
+#define DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF4_Msk /*!< Channel 4 Transfer Error clear */
+#define DMA_IFCR_CGIF5_Pos (16U)
+#define DMA_IFCR_CGIF5_Msk (0x1U << DMA_IFCR_CGIF5_Pos) /*!< 0x00010000 */
+#define DMA_IFCR_CGIF5 DMA_IFCR_CGIF5_Msk /*!< Channel 5 Global interrupt clear */
+#define DMA_IFCR_CTCIF5_Pos (17U)
+#define DMA_IFCR_CTCIF5_Msk (0x1U << DMA_IFCR_CTCIF5_Pos) /*!< 0x00020000 */
+#define DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF5_Msk /*!< Channel 5 Transfer Complete clear */
+#define DMA_IFCR_CHTIF5_Pos (18U)
+#define DMA_IFCR_CHTIF5_Msk (0x1U << DMA_IFCR_CHTIF5_Pos) /*!< 0x00040000 */
+#define DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5_Msk /*!< Channel 5 Half Transfer clear */
+#define DMA_IFCR_CTEIF5_Pos (19U)
+#define DMA_IFCR_CTEIF5_Msk (0x1U << DMA_IFCR_CTEIF5_Pos) /*!< 0x00080000 */
+#define DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF5_Msk /*!< Channel 5 Transfer Error clear */
+#define DMA_IFCR_CGIF6_Pos (20U)
+#define DMA_IFCR_CGIF6_Msk (0x1U << DMA_IFCR_CGIF6_Pos) /*!< 0x00100000 */
+#define DMA_IFCR_CGIF6 DMA_IFCR_CGIF6_Msk /*!< Channel 6 Global interrupt clear */
+#define DMA_IFCR_CTCIF6_Pos (21U)
+#define DMA_IFCR_CTCIF6_Msk (0x1U << DMA_IFCR_CTCIF6_Pos) /*!< 0x00200000 */
+#define DMA_IFCR_CTCIF6 DMA_IFCR_CTCIF6_Msk /*!< Channel 6 Transfer Complete clear */
+#define DMA_IFCR_CHTIF6_Pos (22U)
+#define DMA_IFCR_CHTIF6_Msk (0x1U << DMA_IFCR_CHTIF6_Pos) /*!< 0x00400000 */
+#define DMA_IFCR_CHTIF6 DMA_IFCR_CHTIF6_Msk /*!< Channel 6 Half Transfer clear */
+#define DMA_IFCR_CTEIF6_Pos (23U)
+#define DMA_IFCR_CTEIF6_Msk (0x1U << DMA_IFCR_CTEIF6_Pos) /*!< 0x00800000 */
+#define DMA_IFCR_CTEIF6 DMA_IFCR_CTEIF6_Msk /*!< Channel 6 Transfer Error clear */
+#define DMA_IFCR_CGIF7_Pos (24U)
+#define DMA_IFCR_CGIF7_Msk (0x1U << DMA_IFCR_CGIF7_Pos) /*!< 0x01000000 */
+#define DMA_IFCR_CGIF7 DMA_IFCR_CGIF7_Msk /*!< Channel 7 Global interrupt clear */
+#define DMA_IFCR_CTCIF7_Pos (25U)
+#define DMA_IFCR_CTCIF7_Msk (0x1U << DMA_IFCR_CTCIF7_Pos) /*!< 0x02000000 */
+#define DMA_IFCR_CTCIF7 DMA_IFCR_CTCIF7_Msk /*!< Channel 7 Transfer Complete clear */
+#define DMA_IFCR_CHTIF7_Pos (26U)
+#define DMA_IFCR_CHTIF7_Msk (0x1U << DMA_IFCR_CHTIF7_Pos) /*!< 0x04000000 */
+#define DMA_IFCR_CHTIF7 DMA_IFCR_CHTIF7_Msk /*!< Channel 7 Half Transfer clear */
+#define DMA_IFCR_CTEIF7_Pos (27U)
+#define DMA_IFCR_CTEIF7_Msk (0x1U << DMA_IFCR_CTEIF7_Pos) /*!< 0x08000000 */
+#define DMA_IFCR_CTEIF7 DMA_IFCR_CTEIF7_Msk /*!< Channel 7 Transfer Error clear */
+
+/******************* Bit definition for DMA_CCR register *******************/
+#define DMA_CCR_EN_Pos (0U)
+#define DMA_CCR_EN_Msk (0x1U << DMA_CCR_EN_Pos) /*!< 0x00000001 */
+#define DMA_CCR_EN DMA_CCR_EN_Msk /*!< Channel enable */
+#define DMA_CCR_TCIE_Pos (1U)
+#define DMA_CCR_TCIE_Msk (0x1U << DMA_CCR_TCIE_Pos) /*!< 0x00000002 */
+#define DMA_CCR_TCIE DMA_CCR_TCIE_Msk /*!< Transfer complete interrupt enable */
+#define DMA_CCR_HTIE_Pos (2U)
+#define DMA_CCR_HTIE_Msk (0x1U << DMA_CCR_HTIE_Pos) /*!< 0x00000004 */
+#define DMA_CCR_HTIE DMA_CCR_HTIE_Msk /*!< Half Transfer interrupt enable */
+#define DMA_CCR_TEIE_Pos (3U)
+#define DMA_CCR_TEIE_Msk (0x1U << DMA_CCR_TEIE_Pos) /*!< 0x00000008 */
+#define DMA_CCR_TEIE DMA_CCR_TEIE_Msk /*!< Transfer error interrupt enable */
+#define DMA_CCR_DIR_Pos (4U)
+#define DMA_CCR_DIR_Msk (0x1U << DMA_CCR_DIR_Pos) /*!< 0x00000010 */
+#define DMA_CCR_DIR DMA_CCR_DIR_Msk /*!< Data transfer direction */
+#define DMA_CCR_CIRC_Pos (5U)
+#define DMA_CCR_CIRC_Msk (0x1U << DMA_CCR_CIRC_Pos) /*!< 0x00000020 */
+#define DMA_CCR_CIRC DMA_CCR_CIRC_Msk /*!< Circular mode */
+#define DMA_CCR_PINC_Pos (6U)
+#define DMA_CCR_PINC_Msk (0x1U << DMA_CCR_PINC_Pos) /*!< 0x00000040 */
+#define DMA_CCR_PINC DMA_CCR_PINC_Msk /*!< Peripheral increment mode */
+#define DMA_CCR_MINC_Pos (7U)
+#define DMA_CCR_MINC_Msk (0x1U << DMA_CCR_MINC_Pos) /*!< 0x00000080 */
+#define DMA_CCR_MINC DMA_CCR_MINC_Msk /*!< Memory increment mode */
+
+#define DMA_CCR_PSIZE_Pos (8U)
+#define DMA_CCR_PSIZE_Msk (0x3U << DMA_CCR_PSIZE_Pos) /*!< 0x00000300 */
+#define DMA_CCR_PSIZE DMA_CCR_PSIZE_Msk /*!< PSIZE[1:0] bits (Peripheral size) */
+#define DMA_CCR_PSIZE_0 (0x1U << DMA_CCR_PSIZE_Pos) /*!< 0x00000100 */
+#define DMA_CCR_PSIZE_1 (0x2U << DMA_CCR_PSIZE_Pos) /*!< 0x00000200 */
+
+#define DMA_CCR_MSIZE_Pos (10U)
+#define DMA_CCR_MSIZE_Msk (0x3U << DMA_CCR_MSIZE_Pos) /*!< 0x00000C00 */
+#define DMA_CCR_MSIZE DMA_CCR_MSIZE_Msk /*!< MSIZE[1:0] bits (Memory size) */
+#define DMA_CCR_MSIZE_0 (0x1U << DMA_CCR_MSIZE_Pos) /*!< 0x00000400 */
+#define DMA_CCR_MSIZE_1 (0x2U << DMA_CCR_MSIZE_Pos) /*!< 0x00000800 */
+
+#define DMA_CCR_PL_Pos (12U)
+#define DMA_CCR_PL_Msk (0x3U << DMA_CCR_PL_Pos) /*!< 0x00003000 */
+#define DMA_CCR_PL DMA_CCR_PL_Msk /*!< PL[1:0] bits(Channel Priority level) */
+#define DMA_CCR_PL_0 (0x1U << DMA_CCR_PL_Pos) /*!< 0x00001000 */
+#define DMA_CCR_PL_1 (0x2U << DMA_CCR_PL_Pos) /*!< 0x00002000 */
+
+#define DMA_CCR_MEM2MEM_Pos (14U)
+#define DMA_CCR_MEM2MEM_Msk (0x1U << DMA_CCR_MEM2MEM_Pos) /*!< 0x00004000 */
+#define DMA_CCR_MEM2MEM DMA_CCR_MEM2MEM_Msk /*!< Memory to memory mode */
+
+/****************** Bit definition for DMA_CNDTR register ******************/
+#define DMA_CNDTR_NDT_Pos (0U)
+#define DMA_CNDTR_NDT_Msk (0xFFFFU << DMA_CNDTR_NDT_Pos) /*!< 0x0000FFFF */
+#define DMA_CNDTR_NDT DMA_CNDTR_NDT_Msk /*!< Number of data to Transfer */
+
+/****************** Bit definition for DMA_CPAR register *******************/
+#define DMA_CPAR_PA_Pos (0U)
+#define DMA_CPAR_PA_Msk (0xFFFFFFFFU << DMA_CPAR_PA_Pos) /*!< 0xFFFFFFFF */
+#define DMA_CPAR_PA DMA_CPAR_PA_Msk /*!< Peripheral Address */
+
+/****************** Bit definition for DMA_CMAR register *******************/
+#define DMA_CMAR_MA_Pos (0U)
+#define DMA_CMAR_MA_Msk (0xFFFFFFFFU << DMA_CMAR_MA_Pos) /*!< 0xFFFFFFFF */
+#define DMA_CMAR_MA DMA_CMAR_MA_Msk /*!< Memory Address */
+
+/******************************************************************************/
+/* */
+/* Analog to Digital Converter (ADC) */
+/* */
+/******************************************************************************/
+
+/*
+ * @brief Specific device feature definitions (not present on all devices in the STM32F1 family)
+ */
+/* Note: No specific macro feature on this device */
+
+/******************** Bit definition for ADC_SR register ********************/
+#define ADC_SR_AWD_Pos (0U)
+#define ADC_SR_AWD_Msk (0x1U << ADC_SR_AWD_Pos) /*!< 0x00000001 */
+#define ADC_SR_AWD ADC_SR_AWD_Msk /*!< ADC analog watchdog 1 flag */
+#define ADC_SR_EOS_Pos (1U)
+#define ADC_SR_EOS_Msk (0x1U << ADC_SR_EOS_Pos) /*!< 0x00000002 */
+#define ADC_SR_EOS ADC_SR_EOS_Msk /*!< ADC group regular end of sequence conversions flag */
+#define ADC_SR_JEOS_Pos (2U)
+#define ADC_SR_JEOS_Msk (0x1U << ADC_SR_JEOS_Pos) /*!< 0x00000004 */
+#define ADC_SR_JEOS ADC_SR_JEOS_Msk /*!< ADC group injected end of sequence conversions flag */
+#define ADC_SR_JSTRT_Pos (3U)
+#define ADC_SR_JSTRT_Msk (0x1U << ADC_SR_JSTRT_Pos) /*!< 0x00000008 */
+#define ADC_SR_JSTRT ADC_SR_JSTRT_Msk /*!< ADC group injected conversion start flag */
+#define ADC_SR_STRT_Pos (4U)
+#define ADC_SR_STRT_Msk (0x1U << ADC_SR_STRT_Pos) /*!< 0x00000010 */
+#define ADC_SR_STRT ADC_SR_STRT_Msk /*!< ADC group regular conversion start flag */
+
+/* Legacy defines */
+#define ADC_SR_EOC (ADC_SR_EOS)
+#define ADC_SR_JEOC (ADC_SR_JEOS)
+
+/******************* Bit definition for ADC_CR1 register ********************/
+#define ADC_CR1_AWDCH_Pos (0U)
+#define ADC_CR1_AWDCH_Msk (0x1FU << ADC_CR1_AWDCH_Pos) /*!< 0x0000001F */
+#define ADC_CR1_AWDCH ADC_CR1_AWDCH_Msk /*!< ADC analog watchdog 1 monitored channel selection */
+#define ADC_CR1_AWDCH_0 (0x01U << ADC_CR1_AWDCH_Pos) /*!< 0x00000001 */
+#define ADC_CR1_AWDCH_1 (0x02U << ADC_CR1_AWDCH_Pos) /*!< 0x00000002 */
+#define ADC_CR1_AWDCH_2 (0x04U << ADC_CR1_AWDCH_Pos) /*!< 0x00000004 */
+#define ADC_CR1_AWDCH_3 (0x08U << ADC_CR1_AWDCH_Pos) /*!< 0x00000008 */
+#define ADC_CR1_AWDCH_4 (0x10U << ADC_CR1_AWDCH_Pos) /*!< 0x00000010 */
+
+#define ADC_CR1_EOSIE_Pos (5U)
+#define ADC_CR1_EOSIE_Msk (0x1U << ADC_CR1_EOSIE_Pos) /*!< 0x00000020 */
+#define ADC_CR1_EOSIE ADC_CR1_EOSIE_Msk /*!< ADC group regular end of sequence conversions interrupt */
+#define ADC_CR1_AWDIE_Pos (6U)
+#define ADC_CR1_AWDIE_Msk (0x1U << ADC_CR1_AWDIE_Pos) /*!< 0x00000040 */
+#define ADC_CR1_AWDIE ADC_CR1_AWDIE_Msk /*!< ADC analog watchdog 1 interrupt */
+#define ADC_CR1_JEOSIE_Pos (7U)
+#define ADC_CR1_JEOSIE_Msk (0x1U << ADC_CR1_JEOSIE_Pos) /*!< 0x00000080 */
+#define ADC_CR1_JEOSIE ADC_CR1_JEOSIE_Msk /*!< ADC group injected end of sequence conversions interrupt */
+#define ADC_CR1_SCAN_Pos (8U)
+#define ADC_CR1_SCAN_Msk (0x1U << ADC_CR1_SCAN_Pos) /*!< 0x00000100 */
+#define ADC_CR1_SCAN ADC_CR1_SCAN_Msk /*!< ADC scan mode */
+#define ADC_CR1_AWDSGL_Pos (9U)
+#define ADC_CR1_AWDSGL_Msk (0x1U << ADC_CR1_AWDSGL_Pos) /*!< 0x00000200 */
+#define ADC_CR1_AWDSGL ADC_CR1_AWDSGL_Msk /*!< ADC analog watchdog 1 monitoring a single channel or all channels */
+#define ADC_CR1_JAUTO_Pos (10U)
+#define ADC_CR1_JAUTO_Msk (0x1U << ADC_CR1_JAUTO_Pos) /*!< 0x00000400 */
+#define ADC_CR1_JAUTO ADC_CR1_JAUTO_Msk /*!< ADC group injected automatic trigger mode */
+#define ADC_CR1_DISCEN_Pos (11U)
+#define ADC_CR1_DISCEN_Msk (0x1U << ADC_CR1_DISCEN_Pos) /*!< 0x00000800 */
+#define ADC_CR1_DISCEN ADC_CR1_DISCEN_Msk /*!< ADC group regular sequencer discontinuous mode */
+#define ADC_CR1_JDISCEN_Pos (12U)
+#define ADC_CR1_JDISCEN_Msk (0x1U << ADC_CR1_JDISCEN_Pos) /*!< 0x00001000 */
+#define ADC_CR1_JDISCEN ADC_CR1_JDISCEN_Msk /*!< ADC group injected sequencer discontinuous mode */
+
+#define ADC_CR1_DISCNUM_Pos (13U)
+#define ADC_CR1_DISCNUM_Msk (0x7U << ADC_CR1_DISCNUM_Pos) /*!< 0x0000E000 */
+#define ADC_CR1_DISCNUM ADC_CR1_DISCNUM_Msk /*!< ADC group regular sequencer discontinuous number of ranks */
+#define ADC_CR1_DISCNUM_0 (0x1U << ADC_CR1_DISCNUM_Pos) /*!< 0x00002000 */
+#define ADC_CR1_DISCNUM_1 (0x2U << ADC_CR1_DISCNUM_Pos) /*!< 0x00004000 */
+#define ADC_CR1_DISCNUM_2 (0x4U << ADC_CR1_DISCNUM_Pos) /*!< 0x00008000 */
+
+#define ADC_CR1_JAWDEN_Pos (22U)
+#define ADC_CR1_JAWDEN_Msk (0x1U << ADC_CR1_JAWDEN_Pos) /*!< 0x00400000 */
+#define ADC_CR1_JAWDEN ADC_CR1_JAWDEN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group injected */
+#define ADC_CR1_AWDEN_Pos (23U)
+#define ADC_CR1_AWDEN_Msk (0x1U << ADC_CR1_AWDEN_Pos) /*!< 0x00800000 */
+#define ADC_CR1_AWDEN ADC_CR1_AWDEN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group regular */
+
+/* Legacy defines */
+#define ADC_CR1_EOCIE (ADC_CR1_EOSIE)
+#define ADC_CR1_JEOCIE (ADC_CR1_JEOSIE)
+
+/******************* Bit definition for ADC_CR2 register ********************/
+#define ADC_CR2_ADON_Pos (0U)
+#define ADC_CR2_ADON_Msk (0x1U << ADC_CR2_ADON_Pos) /*!< 0x00000001 */
+#define ADC_CR2_ADON ADC_CR2_ADON_Msk /*!< ADC enable */
+#define ADC_CR2_CONT_Pos (1U)
+#define ADC_CR2_CONT_Msk (0x1U << ADC_CR2_CONT_Pos) /*!< 0x00000002 */
+#define ADC_CR2_CONT ADC_CR2_CONT_Msk /*!< ADC group regular continuous conversion mode */
+#define ADC_CR2_CAL_Pos (2U)
+#define ADC_CR2_CAL_Msk (0x1U << ADC_CR2_CAL_Pos) /*!< 0x00000004 */
+#define ADC_CR2_CAL ADC_CR2_CAL_Msk /*!< ADC calibration start */
+#define ADC_CR2_RSTCAL_Pos (3U)
+#define ADC_CR2_RSTCAL_Msk (0x1U << ADC_CR2_RSTCAL_Pos) /*!< 0x00000008 */
+#define ADC_CR2_RSTCAL ADC_CR2_RSTCAL_Msk /*!< ADC calibration reset */
+#define ADC_CR2_DMA_Pos (8U)
+#define ADC_CR2_DMA_Msk (0x1U << ADC_CR2_DMA_Pos) /*!< 0x00000100 */
+#define ADC_CR2_DMA ADC_CR2_DMA_Msk /*!< ADC DMA transfer enable */
+#define ADC_CR2_ALIGN_Pos (11U)
+#define ADC_CR2_ALIGN_Msk (0x1U << ADC_CR2_ALIGN_Pos) /*!< 0x00000800 */
+#define ADC_CR2_ALIGN ADC_CR2_ALIGN_Msk /*!< ADC data alignement */
+
+#define ADC_CR2_JEXTSEL_Pos (12U)
+#define ADC_CR2_JEXTSEL_Msk (0x7U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00007000 */
+#define ADC_CR2_JEXTSEL ADC_CR2_JEXTSEL_Msk /*!< ADC group injected external trigger source */
+#define ADC_CR2_JEXTSEL_0 (0x1U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00001000 */
+#define ADC_CR2_JEXTSEL_1 (0x2U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00002000 */
+#define ADC_CR2_JEXTSEL_2 (0x4U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00004000 */
+
+#define ADC_CR2_JEXTTRIG_Pos (15U)
+#define ADC_CR2_JEXTTRIG_Msk (0x1U << ADC_CR2_JEXTTRIG_Pos) /*!< 0x00008000 */
+#define ADC_CR2_JEXTTRIG ADC_CR2_JEXTTRIG_Msk /*!< ADC group injected external trigger enable */
+
+#define ADC_CR2_EXTSEL_Pos (17U)
+#define ADC_CR2_EXTSEL_Msk (0x7U << ADC_CR2_EXTSEL_Pos) /*!< 0x000E0000 */
+#define ADC_CR2_EXTSEL ADC_CR2_EXTSEL_Msk /*!< ADC group regular external trigger source */
+#define ADC_CR2_EXTSEL_0 (0x1U << ADC_CR2_EXTSEL_Pos) /*!< 0x00020000 */
+#define ADC_CR2_EXTSEL_1 (0x2U << ADC_CR2_EXTSEL_Pos) /*!< 0x00040000 */
+#define ADC_CR2_EXTSEL_2 (0x4U << ADC_CR2_EXTSEL_Pos) /*!< 0x00080000 */
+
+#define ADC_CR2_EXTTRIG_Pos (20U)
+#define ADC_CR2_EXTTRIG_Msk (0x1U << ADC_CR2_EXTTRIG_Pos) /*!< 0x00100000 */
+#define ADC_CR2_EXTTRIG ADC_CR2_EXTTRIG_Msk /*!< ADC group regular external trigger enable */
+#define ADC_CR2_JSWSTART_Pos (21U)
+#define ADC_CR2_JSWSTART_Msk (0x1U << ADC_CR2_JSWSTART_Pos) /*!< 0x00200000 */
+#define ADC_CR2_JSWSTART ADC_CR2_JSWSTART_Msk /*!< ADC group injected conversion start */
+#define ADC_CR2_SWSTART_Pos (22U)
+#define ADC_CR2_SWSTART_Msk (0x1U << ADC_CR2_SWSTART_Pos) /*!< 0x00400000 */
+#define ADC_CR2_SWSTART ADC_CR2_SWSTART_Msk /*!< ADC group regular conversion start */
+#define ADC_CR2_TSVREFE_Pos (23U)
+#define ADC_CR2_TSVREFE_Msk (0x1U << ADC_CR2_TSVREFE_Pos) /*!< 0x00800000 */
+#define ADC_CR2_TSVREFE ADC_CR2_TSVREFE_Msk /*!< ADC internal path to VrefInt and temperature sensor enable */
+
+/****************** Bit definition for ADC_SMPR1 register *******************/
+#define ADC_SMPR1_SMP10_Pos (0U)
+#define ADC_SMPR1_SMP10_Msk (0x7U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000007 */
+#define ADC_SMPR1_SMP10 ADC_SMPR1_SMP10_Msk /*!< ADC channel 10 sampling time selection */
+#define ADC_SMPR1_SMP10_0 (0x1U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000001 */
+#define ADC_SMPR1_SMP10_1 (0x2U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000002 */
+#define ADC_SMPR1_SMP10_2 (0x4U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000004 */
+
+#define ADC_SMPR1_SMP11_Pos (3U)
+#define ADC_SMPR1_SMP11_Msk (0x7U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000038 */
+#define ADC_SMPR1_SMP11 ADC_SMPR1_SMP11_Msk /*!< ADC channel 11 sampling time selection */
+#define ADC_SMPR1_SMP11_0 (0x1U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000008 */
+#define ADC_SMPR1_SMP11_1 (0x2U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000010 */
+#define ADC_SMPR1_SMP11_2 (0x4U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000020 */
+
+#define ADC_SMPR1_SMP12_Pos (6U)
+#define ADC_SMPR1_SMP12_Msk (0x7U << ADC_SMPR1_SMP12_Pos) /*!< 0x000001C0 */
+#define ADC_SMPR1_SMP12 ADC_SMPR1_SMP12_Msk /*!< ADC channel 12 sampling time selection */
+#define ADC_SMPR1_SMP12_0 (0x1U << ADC_SMPR1_SMP12_Pos) /*!< 0x00000040 */
+#define ADC_SMPR1_SMP12_1 (0x2U << ADC_SMPR1_SMP12_Pos) /*!< 0x00000080 */
+#define ADC_SMPR1_SMP12_2 (0x4U << ADC_SMPR1_SMP12_Pos) /*!< 0x00000100 */
+
+#define ADC_SMPR1_SMP13_Pos (9U)
+#define ADC_SMPR1_SMP13_Msk (0x7U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000E00 */
+#define ADC_SMPR1_SMP13 ADC_SMPR1_SMP13_Msk /*!< ADC channel 13 sampling time selection */
+#define ADC_SMPR1_SMP13_0 (0x1U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000200 */
+#define ADC_SMPR1_SMP13_1 (0x2U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000400 */
+#define ADC_SMPR1_SMP13_2 (0x4U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000800 */
+
+#define ADC_SMPR1_SMP14_Pos (12U)
+#define ADC_SMPR1_SMP14_Msk (0x7U << ADC_SMPR1_SMP14_Pos) /*!< 0x00007000 */
+#define ADC_SMPR1_SMP14 ADC_SMPR1_SMP14_Msk /*!< ADC channel 14 sampling time selection */
+#define ADC_SMPR1_SMP14_0 (0x1U << ADC_SMPR1_SMP14_Pos) /*!< 0x00001000 */
+#define ADC_SMPR1_SMP14_1 (0x2U << ADC_SMPR1_SMP14_Pos) /*!< 0x00002000 */
+#define ADC_SMPR1_SMP14_2 (0x4U << ADC_SMPR1_SMP14_Pos) /*!< 0x00004000 */
+
+#define ADC_SMPR1_SMP15_Pos (15U)
+#define ADC_SMPR1_SMP15_Msk (0x7U << ADC_SMPR1_SMP15_Pos) /*!< 0x00038000 */
+#define ADC_SMPR1_SMP15 ADC_SMPR1_SMP15_Msk /*!< ADC channel 15 sampling time selection */
+#define ADC_SMPR1_SMP15_0 (0x1U << ADC_SMPR1_SMP15_Pos) /*!< 0x00008000 */
+#define ADC_SMPR1_SMP15_1 (0x2U << ADC_SMPR1_SMP15_Pos) /*!< 0x00010000 */
+#define ADC_SMPR1_SMP15_2 (0x4U << ADC_SMPR1_SMP15_Pos) /*!< 0x00020000 */
+
+#define ADC_SMPR1_SMP16_Pos (18U)
+#define ADC_SMPR1_SMP16_Msk (0x7U << ADC_SMPR1_SMP16_Pos) /*!< 0x001C0000 */
+#define ADC_SMPR1_SMP16 ADC_SMPR1_SMP16_Msk /*!< ADC channel 16 sampling time selection */
+#define ADC_SMPR1_SMP16_0 (0x1U << ADC_SMPR1_SMP16_Pos) /*!< 0x00040000 */
+#define ADC_SMPR1_SMP16_1 (0x2U << ADC_SMPR1_SMP16_Pos) /*!< 0x00080000 */
+#define ADC_SMPR1_SMP16_2 (0x4U << ADC_SMPR1_SMP16_Pos) /*!< 0x00100000 */
+
+#define ADC_SMPR1_SMP17_Pos (21U)
+#define ADC_SMPR1_SMP17_Msk (0x7U << ADC_SMPR1_SMP17_Pos) /*!< 0x00E00000 */
+#define ADC_SMPR1_SMP17 ADC_SMPR1_SMP17_Msk /*!< ADC channel 17 sampling time selection */
+#define ADC_SMPR1_SMP17_0 (0x1U << ADC_SMPR1_SMP17_Pos) /*!< 0x00200000 */
+#define ADC_SMPR1_SMP17_1 (0x2U << ADC_SMPR1_SMP17_Pos) /*!< 0x00400000 */
+#define ADC_SMPR1_SMP17_2 (0x4U << ADC_SMPR1_SMP17_Pos) /*!< 0x00800000 */
+
+/****************** Bit definition for ADC_SMPR2 register *******************/
+#define ADC_SMPR2_SMP0_Pos (0U)
+#define ADC_SMPR2_SMP0_Msk (0x7U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000007 */
+#define ADC_SMPR2_SMP0 ADC_SMPR2_SMP0_Msk /*!< ADC channel 0 sampling time selection */
+#define ADC_SMPR2_SMP0_0 (0x1U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000001 */
+#define ADC_SMPR2_SMP0_1 (0x2U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000002 */
+#define ADC_SMPR2_SMP0_2 (0x4U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000004 */
+
+#define ADC_SMPR2_SMP1_Pos (3U)
+#define ADC_SMPR2_SMP1_Msk (0x7U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000038 */
+#define ADC_SMPR2_SMP1 ADC_SMPR2_SMP1_Msk /*!< ADC channel 1 sampling time selection */
+#define ADC_SMPR2_SMP1_0 (0x1U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000008 */
+#define ADC_SMPR2_SMP1_1 (0x2U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000010 */
+#define ADC_SMPR2_SMP1_2 (0x4U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000020 */
+
+#define ADC_SMPR2_SMP2_Pos (6U)
+#define ADC_SMPR2_SMP2_Msk (0x7U << ADC_SMPR2_SMP2_Pos) /*!< 0x000001C0 */
+#define ADC_SMPR2_SMP2 ADC_SMPR2_SMP2_Msk /*!< ADC channel 2 sampling time selection */
+#define ADC_SMPR2_SMP2_0 (0x1U << ADC_SMPR2_SMP2_Pos) /*!< 0x00000040 */
+#define ADC_SMPR2_SMP2_1 (0x2U << ADC_SMPR2_SMP2_Pos) /*!< 0x00000080 */
+#define ADC_SMPR2_SMP2_2 (0x4U << ADC_SMPR2_SMP2_Pos) /*!< 0x00000100 */
+
+#define ADC_SMPR2_SMP3_Pos (9U)
+#define ADC_SMPR2_SMP3_Msk (0x7U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000E00 */
+#define ADC_SMPR2_SMP3 ADC_SMPR2_SMP3_Msk /*!< ADC channel 3 sampling time selection */
+#define ADC_SMPR2_SMP3_0 (0x1U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000200 */
+#define ADC_SMPR2_SMP3_1 (0x2U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000400 */
+#define ADC_SMPR2_SMP3_2 (0x4U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000800 */
+
+#define ADC_SMPR2_SMP4_Pos (12U)
+#define ADC_SMPR2_SMP4_Msk (0x7U << ADC_SMPR2_SMP4_Pos) /*!< 0x00007000 */
+#define ADC_SMPR2_SMP4 ADC_SMPR2_SMP4_Msk /*!< ADC channel 4 sampling time selection */
+#define ADC_SMPR2_SMP4_0 (0x1U << ADC_SMPR2_SMP4_Pos) /*!< 0x00001000 */
+#define ADC_SMPR2_SMP4_1 (0x2U << ADC_SMPR2_SMP4_Pos) /*!< 0x00002000 */
+#define ADC_SMPR2_SMP4_2 (0x4U << ADC_SMPR2_SMP4_Pos) /*!< 0x00004000 */
+
+#define ADC_SMPR2_SMP5_Pos (15U)
+#define ADC_SMPR2_SMP5_Msk (0x7U << ADC_SMPR2_SMP5_Pos) /*!< 0x00038000 */
+#define ADC_SMPR2_SMP5 ADC_SMPR2_SMP5_Msk /*!< ADC channel 5 sampling time selection */
+#define ADC_SMPR2_SMP5_0 (0x1U << ADC_SMPR2_SMP5_Pos) /*!< 0x00008000 */
+#define ADC_SMPR2_SMP5_1 (0x2U << ADC_SMPR2_SMP5_Pos) /*!< 0x00010000 */
+#define ADC_SMPR2_SMP5_2 (0x4U << ADC_SMPR2_SMP5_Pos) /*!< 0x00020000 */
+
+#define ADC_SMPR2_SMP6_Pos (18U)
+#define ADC_SMPR2_SMP6_Msk (0x7U << ADC_SMPR2_SMP6_Pos) /*!< 0x001C0000 */
+#define ADC_SMPR2_SMP6 ADC_SMPR2_SMP6_Msk /*!< ADC channel 6 sampling time selection */
+#define ADC_SMPR2_SMP6_0 (0x1U << ADC_SMPR2_SMP6_Pos) /*!< 0x00040000 */
+#define ADC_SMPR2_SMP6_1 (0x2U << ADC_SMPR2_SMP6_Pos) /*!< 0x00080000 */
+#define ADC_SMPR2_SMP6_2 (0x4U << ADC_SMPR2_SMP6_Pos) /*!< 0x00100000 */
+
+#define ADC_SMPR2_SMP7_Pos (21U)
+#define ADC_SMPR2_SMP7_Msk (0x7U << ADC_SMPR2_SMP7_Pos) /*!< 0x00E00000 */
+#define ADC_SMPR2_SMP7 ADC_SMPR2_SMP7_Msk /*!< ADC channel 7 sampling time selection */
+#define ADC_SMPR2_SMP7_0 (0x1U << ADC_SMPR2_SMP7_Pos) /*!< 0x00200000 */
+#define ADC_SMPR2_SMP7_1 (0x2U << ADC_SMPR2_SMP7_Pos) /*!< 0x00400000 */
+#define ADC_SMPR2_SMP7_2 (0x4U << ADC_SMPR2_SMP7_Pos) /*!< 0x00800000 */
+
+#define ADC_SMPR2_SMP8_Pos (24U)
+#define ADC_SMPR2_SMP8_Msk (0x7U << ADC_SMPR2_SMP8_Pos) /*!< 0x07000000 */
+#define ADC_SMPR2_SMP8 ADC_SMPR2_SMP8_Msk /*!< ADC channel 8 sampling time selection */
+#define ADC_SMPR2_SMP8_0 (0x1U << ADC_SMPR2_SMP8_Pos) /*!< 0x01000000 */
+#define ADC_SMPR2_SMP8_1 (0x2U << ADC_SMPR2_SMP8_Pos) /*!< 0x02000000 */
+#define ADC_SMPR2_SMP8_2 (0x4U << ADC_SMPR2_SMP8_Pos) /*!< 0x04000000 */
+
+#define ADC_SMPR2_SMP9_Pos (27U)
+#define ADC_SMPR2_SMP9_Msk (0x7U << ADC_SMPR2_SMP9_Pos) /*!< 0x38000000 */
+#define ADC_SMPR2_SMP9 ADC_SMPR2_SMP9_Msk /*!< ADC channel 9 sampling time selection */
+#define ADC_SMPR2_SMP9_0 (0x1U << ADC_SMPR2_SMP9_Pos) /*!< 0x08000000 */
+#define ADC_SMPR2_SMP9_1 (0x2U << ADC_SMPR2_SMP9_Pos) /*!< 0x10000000 */
+#define ADC_SMPR2_SMP9_2 (0x4U << ADC_SMPR2_SMP9_Pos) /*!< 0x20000000 */
+
+/****************** Bit definition for ADC_JOFR1 register *******************/
+#define ADC_JOFR1_JOFFSET1_Pos (0U)
+#define ADC_JOFR1_JOFFSET1_Msk (0xFFFU << ADC_JOFR1_JOFFSET1_Pos) /*!< 0x00000FFF */
+#define ADC_JOFR1_JOFFSET1 ADC_JOFR1_JOFFSET1_Msk /*!< ADC group injected sequencer rank 1 offset value */
+
+/****************** Bit definition for ADC_JOFR2 register *******************/
+#define ADC_JOFR2_JOFFSET2_Pos (0U)
+#define ADC_JOFR2_JOFFSET2_Msk (0xFFFU << ADC_JOFR2_JOFFSET2_Pos) /*!< 0x00000FFF */
+#define ADC_JOFR2_JOFFSET2 ADC_JOFR2_JOFFSET2_Msk /*!< ADC group injected sequencer rank 2 offset value */
+
+/****************** Bit definition for ADC_JOFR3 register *******************/
+#define ADC_JOFR3_JOFFSET3_Pos (0U)
+#define ADC_JOFR3_JOFFSET3_Msk (0xFFFU << ADC_JOFR3_JOFFSET3_Pos) /*!< 0x00000FFF */
+#define ADC_JOFR3_JOFFSET3 ADC_JOFR3_JOFFSET3_Msk /*!< ADC group injected sequencer rank 3 offset value */
+
+/****************** Bit definition for ADC_JOFR4 register *******************/
+#define ADC_JOFR4_JOFFSET4_Pos (0U)
+#define ADC_JOFR4_JOFFSET4_Msk (0xFFFU << ADC_JOFR4_JOFFSET4_Pos) /*!< 0x00000FFF */
+#define ADC_JOFR4_JOFFSET4 ADC_JOFR4_JOFFSET4_Msk /*!< ADC group injected sequencer rank 4 offset value */
+
+/******************* Bit definition for ADC_HTR register ********************/
+#define ADC_HTR_HT_Pos (0U)
+#define ADC_HTR_HT_Msk (0xFFFU << ADC_HTR_HT_Pos) /*!< 0x00000FFF */
+#define ADC_HTR_HT ADC_HTR_HT_Msk /*!< ADC analog watchdog 1 threshold high */
+
+/******************* Bit definition for ADC_LTR register ********************/
+#define ADC_LTR_LT_Pos (0U)
+#define ADC_LTR_LT_Msk (0xFFFU << ADC_LTR_LT_Pos) /*!< 0x00000FFF */
+#define ADC_LTR_LT ADC_LTR_LT_Msk /*!< ADC analog watchdog 1 threshold low */
+
+/******************* Bit definition for ADC_SQR1 register *******************/
+#define ADC_SQR1_SQ13_Pos (0U)
+#define ADC_SQR1_SQ13_Msk (0x1FU << ADC_SQR1_SQ13_Pos) /*!< 0x0000001F */
+#define ADC_SQR1_SQ13 ADC_SQR1_SQ13_Msk /*!< ADC group regular sequencer rank 13 */
+#define ADC_SQR1_SQ13_0 (0x01U << ADC_SQR1_SQ13_Pos) /*!< 0x00000001 */
+#define ADC_SQR1_SQ13_1 (0x02U << ADC_SQR1_SQ13_Pos) /*!< 0x00000002 */
+#define ADC_SQR1_SQ13_2 (0x04U << ADC_SQR1_SQ13_Pos) /*!< 0x00000004 */
+#define ADC_SQR1_SQ13_3 (0x08U << ADC_SQR1_SQ13_Pos) /*!< 0x00000008 */
+#define ADC_SQR1_SQ13_4 (0x10U << ADC_SQR1_SQ13_Pos) /*!< 0x00000010 */
+
+#define ADC_SQR1_SQ14_Pos (5U)
+#define ADC_SQR1_SQ14_Msk (0x1FU << ADC_SQR1_SQ14_Pos) /*!< 0x000003E0 */
+#define ADC_SQR1_SQ14 ADC_SQR1_SQ14_Msk /*!< ADC group regular sequencer rank 14 */
+#define ADC_SQR1_SQ14_0 (0x01U << ADC_SQR1_SQ14_Pos) /*!< 0x00000020 */
+#define ADC_SQR1_SQ14_1 (0x02U << ADC_SQR1_SQ14_Pos) /*!< 0x00000040 */
+#define ADC_SQR1_SQ14_2 (0x04U << ADC_SQR1_SQ14_Pos) /*!< 0x00000080 */
+#define ADC_SQR1_SQ14_3 (0x08U << ADC_SQR1_SQ14_Pos) /*!< 0x00000100 */
+#define ADC_SQR1_SQ14_4 (0x10U << ADC_SQR1_SQ14_Pos) /*!< 0x00000200 */
+
+#define ADC_SQR1_SQ15_Pos (10U)
+#define ADC_SQR1_SQ15_Msk (0x1FU << ADC_SQR1_SQ15_Pos) /*!< 0x00007C00 */
+#define ADC_SQR1_SQ15 ADC_SQR1_SQ15_Msk /*!< ADC group regular sequencer rank 15 */
+#define ADC_SQR1_SQ15_0 (0x01U << ADC_SQR1_SQ15_Pos) /*!< 0x00000400 */
+#define ADC_SQR1_SQ15_1 (0x02U << ADC_SQR1_SQ15_Pos) /*!< 0x00000800 */
+#define ADC_SQR1_SQ15_2 (0x04U << ADC_SQR1_SQ15_Pos) /*!< 0x00001000 */
+#define ADC_SQR1_SQ15_3 (0x08U << ADC_SQR1_SQ15_Pos) /*!< 0x00002000 */
+#define ADC_SQR1_SQ15_4 (0x10U << ADC_SQR1_SQ15_Pos) /*!< 0x00004000 */
+
+#define ADC_SQR1_SQ16_Pos (15U)
+#define ADC_SQR1_SQ16_Msk (0x1FU << ADC_SQR1_SQ16_Pos) /*!< 0x000F8000 */
+#define ADC_SQR1_SQ16 ADC_SQR1_SQ16_Msk /*!< ADC group regular sequencer rank 16 */
+#define ADC_SQR1_SQ16_0 (0x01U << ADC_SQR1_SQ16_Pos) /*!< 0x00008000 */
+#define ADC_SQR1_SQ16_1 (0x02U << ADC_SQR1_SQ16_Pos) /*!< 0x00010000 */
+#define ADC_SQR1_SQ16_2 (0x04U << ADC_SQR1_SQ16_Pos) /*!< 0x00020000 */
+#define ADC_SQR1_SQ16_3 (0x08U << ADC_SQR1_SQ16_Pos) /*!< 0x00040000 */
+#define ADC_SQR1_SQ16_4 (0x10U << ADC_SQR1_SQ16_Pos) /*!< 0x00080000 */
+
+#define ADC_SQR1_L_Pos (20U)
+#define ADC_SQR1_L_Msk (0xFU << ADC_SQR1_L_Pos) /*!< 0x00F00000 */
+#define ADC_SQR1_L ADC_SQR1_L_Msk /*!< ADC group regular sequencer scan length */
+#define ADC_SQR1_L_0 (0x1U << ADC_SQR1_L_Pos) /*!< 0x00100000 */
+#define ADC_SQR1_L_1 (0x2U << ADC_SQR1_L_Pos) /*!< 0x00200000 */
+#define ADC_SQR1_L_2 (0x4U << ADC_SQR1_L_Pos) /*!< 0x00400000 */
+#define ADC_SQR1_L_3 (0x8U << ADC_SQR1_L_Pos) /*!< 0x00800000 */
+
+/******************* Bit definition for ADC_SQR2 register *******************/
+#define ADC_SQR2_SQ7_Pos (0U)
+#define ADC_SQR2_SQ7_Msk (0x1FU << ADC_SQR2_SQ7_Pos) /*!< 0x0000001F */
+#define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk /*!< ADC group regular sequencer rank 7 */
+#define ADC_SQR2_SQ7_0 (0x01U << ADC_SQR2_SQ7_Pos) /*!< 0x00000001 */
+#define ADC_SQR2_SQ7_1 (0x02U << ADC_SQR2_SQ7_Pos) /*!< 0x00000002 */
+#define ADC_SQR2_SQ7_2 (0x04U << ADC_SQR2_SQ7_Pos) /*!< 0x00000004 */
+#define ADC_SQR2_SQ7_3 (0x08U << ADC_SQR2_SQ7_Pos) /*!< 0x00000008 */
+#define ADC_SQR2_SQ7_4 (0x10U << ADC_SQR2_SQ7_Pos) /*!< 0x00000010 */
+
+#define ADC_SQR2_SQ8_Pos (5U)
+#define ADC_SQR2_SQ8_Msk (0x1FU << ADC_SQR2_SQ8_Pos) /*!< 0x000003E0 */
+#define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk /*!< ADC group regular sequencer rank 8 */
+#define ADC_SQR2_SQ8_0 (0x01U << ADC_SQR2_SQ8_Pos) /*!< 0x00000020 */
+#define ADC_SQR2_SQ8_1 (0x02U << ADC_SQR2_SQ8_Pos) /*!< 0x00000040 */
+#define ADC_SQR2_SQ8_2 (0x04U << ADC_SQR2_SQ8_Pos) /*!< 0x00000080 */
+#define ADC_SQR2_SQ8_3 (0x08U << ADC_SQR2_SQ8_Pos) /*!< 0x00000100 */
+#define ADC_SQR2_SQ8_4 (0x10U << ADC_SQR2_SQ8_Pos) /*!< 0x00000200 */
+
+#define ADC_SQR2_SQ9_Pos (10U)
+#define ADC_SQR2_SQ9_Msk (0x1FU << ADC_SQR2_SQ9_Pos) /*!< 0x00007C00 */
+#define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk /*!< ADC group regular sequencer rank 9 */
+#define ADC_SQR2_SQ9_0 (0x01U << ADC_SQR2_SQ9_Pos) /*!< 0x00000400 */
+#define ADC_SQR2_SQ9_1 (0x02U << ADC_SQR2_SQ9_Pos) /*!< 0x00000800 */
+#define ADC_SQR2_SQ9_2 (0x04U << ADC_SQR2_SQ9_Pos) /*!< 0x00001000 */
+#define ADC_SQR2_SQ9_3 (0x08U << ADC_SQR2_SQ9_Pos) /*!< 0x00002000 */
+#define ADC_SQR2_SQ9_4 (0x10U << ADC_SQR2_SQ9_Pos) /*!< 0x00004000 */
+
+#define ADC_SQR2_SQ10_Pos (15U)
+#define ADC_SQR2_SQ10_Msk (0x1FU << ADC_SQR2_SQ10_Pos) /*!< 0x000F8000 */
+#define ADC_SQR2_SQ10 ADC_SQR2_SQ10_Msk /*!< ADC group regular sequencer rank 10 */
+#define ADC_SQR2_SQ10_0 (0x01U << ADC_SQR2_SQ10_Pos) /*!< 0x00008000 */
+#define ADC_SQR2_SQ10_1 (0x02U << ADC_SQR2_SQ10_Pos) /*!< 0x00010000 */
+#define ADC_SQR2_SQ10_2 (0x04U << ADC_SQR2_SQ10_Pos) /*!< 0x00020000 */
+#define ADC_SQR2_SQ10_3 (0x08U << ADC_SQR2_SQ10_Pos) /*!< 0x00040000 */
+#define ADC_SQR2_SQ10_4 (0x10U << ADC_SQR2_SQ10_Pos) /*!< 0x00080000 */
+
+#define ADC_SQR2_SQ11_Pos (20U)
+#define ADC_SQR2_SQ11_Msk (0x1FU << ADC_SQR2_SQ11_Pos) /*!< 0x01F00000 */
+#define ADC_SQR2_SQ11 ADC_SQR2_SQ11_Msk /*!< ADC group regular sequencer rank 1 */
+#define ADC_SQR2_SQ11_0 (0x01U << ADC_SQR2_SQ11_Pos) /*!< 0x00100000 */
+#define ADC_SQR2_SQ11_1 (0x02U << ADC_SQR2_SQ11_Pos) /*!< 0x00200000 */
+#define ADC_SQR2_SQ11_2 (0x04U << ADC_SQR2_SQ11_Pos) /*!< 0x00400000 */
+#define ADC_SQR2_SQ11_3 (0x08U << ADC_SQR2_SQ11_Pos) /*!< 0x00800000 */
+#define ADC_SQR2_SQ11_4 (0x10U << ADC_SQR2_SQ11_Pos) /*!< 0x01000000 */
+
+#define ADC_SQR2_SQ12_Pos (25U)
+#define ADC_SQR2_SQ12_Msk (0x1FU << ADC_SQR2_SQ12_Pos) /*!< 0x3E000000 */
+#define ADC_SQR2_SQ12 ADC_SQR2_SQ12_Msk /*!< ADC group regular sequencer rank 12 */
+#define ADC_SQR2_SQ12_0 (0x01U << ADC_SQR2_SQ12_Pos) /*!< 0x02000000 */
+#define ADC_SQR2_SQ12_1 (0x02U << ADC_SQR2_SQ12_Pos) /*!< 0x04000000 */
+#define ADC_SQR2_SQ12_2 (0x04U << ADC_SQR2_SQ12_Pos) /*!< 0x08000000 */
+#define ADC_SQR2_SQ12_3 (0x08U << ADC_SQR2_SQ12_Pos) /*!< 0x10000000 */
+#define ADC_SQR2_SQ12_4 (0x10U << ADC_SQR2_SQ12_Pos) /*!< 0x20000000 */
+
+/******************* Bit definition for ADC_SQR3 register *******************/
+#define ADC_SQR3_SQ1_Pos (0U)
+#define ADC_SQR3_SQ1_Msk (0x1FU << ADC_SQR3_SQ1_Pos) /*!< 0x0000001F */
+#define ADC_SQR3_SQ1 ADC_SQR3_SQ1_Msk /*!< ADC group regular sequencer rank 1 */
+#define ADC_SQR3_SQ1_0 (0x01U << ADC_SQR3_SQ1_Pos) /*!< 0x00000001 */
+#define ADC_SQR3_SQ1_1 (0x02U << ADC_SQR3_SQ1_Pos) /*!< 0x00000002 */
+#define ADC_SQR3_SQ1_2 (0x04U << ADC_SQR3_SQ1_Pos) /*!< 0x00000004 */
+#define ADC_SQR3_SQ1_3 (0x08U << ADC_SQR3_SQ1_Pos) /*!< 0x00000008 */
+#define ADC_SQR3_SQ1_4 (0x10U << ADC_SQR3_SQ1_Pos) /*!< 0x00000010 */
+
+#define ADC_SQR3_SQ2_Pos (5U)
+#define ADC_SQR3_SQ2_Msk (0x1FU << ADC_SQR3_SQ2_Pos) /*!< 0x000003E0 */
+#define ADC_SQR3_SQ2 ADC_SQR3_SQ2_Msk /*!< ADC group regular sequencer rank 2 */
+#define ADC_SQR3_SQ2_0 (0x01U << ADC_SQR3_SQ2_Pos) /*!< 0x00000020 */
+#define ADC_SQR3_SQ2_1 (0x02U << ADC_SQR3_SQ2_Pos) /*!< 0x00000040 */
+#define ADC_SQR3_SQ2_2 (0x04U << ADC_SQR3_SQ2_Pos) /*!< 0x00000080 */
+#define ADC_SQR3_SQ2_3 (0x08U << ADC_SQR3_SQ2_Pos) /*!< 0x00000100 */
+#define ADC_SQR3_SQ2_4 (0x10U << ADC_SQR3_SQ2_Pos) /*!< 0x00000200 */
+
+#define ADC_SQR3_SQ3_Pos (10U)
+#define ADC_SQR3_SQ3_Msk (0x1FU << ADC_SQR3_SQ3_Pos) /*!< 0x00007C00 */
+#define ADC_SQR3_SQ3 ADC_SQR3_SQ3_Msk /*!< ADC group regular sequencer rank 3 */
+#define ADC_SQR3_SQ3_0 (0x01U << ADC_SQR3_SQ3_Pos) /*!< 0x00000400 */
+#define ADC_SQR3_SQ3_1 (0x02U << ADC_SQR3_SQ3_Pos) /*!< 0x00000800 */
+#define ADC_SQR3_SQ3_2 (0x04U << ADC_SQR3_SQ3_Pos) /*!< 0x00001000 */
+#define ADC_SQR3_SQ3_3 (0x08U << ADC_SQR3_SQ3_Pos) /*!< 0x00002000 */
+#define ADC_SQR3_SQ3_4 (0x10U << ADC_SQR3_SQ3_Pos) /*!< 0x00004000 */
+
+#define ADC_SQR3_SQ4_Pos (15U)
+#define ADC_SQR3_SQ4_Msk (0x1FU << ADC_SQR3_SQ4_Pos) /*!< 0x000F8000 */
+#define ADC_SQR3_SQ4 ADC_SQR3_SQ4_Msk /*!< ADC group regular sequencer rank 4 */
+#define ADC_SQR3_SQ4_0 (0x01U << ADC_SQR3_SQ4_Pos) /*!< 0x00008000 */
+#define ADC_SQR3_SQ4_1 (0x02U << ADC_SQR3_SQ4_Pos) /*!< 0x00010000 */
+#define ADC_SQR3_SQ4_2 (0x04U << ADC_SQR3_SQ4_Pos) /*!< 0x00020000 */
+#define ADC_SQR3_SQ4_3 (0x08U << ADC_SQR3_SQ4_Pos) /*!< 0x00040000 */
+#define ADC_SQR3_SQ4_4 (0x10U << ADC_SQR3_SQ4_Pos) /*!< 0x00080000 */
+
+#define ADC_SQR3_SQ5_Pos (20U)
+#define ADC_SQR3_SQ5_Msk (0x1FU << ADC_SQR3_SQ5_Pos) /*!< 0x01F00000 */
+#define ADC_SQR3_SQ5 ADC_SQR3_SQ5_Msk /*!< ADC group regular sequencer rank 5 */
+#define ADC_SQR3_SQ5_0 (0x01U << ADC_SQR3_SQ5_Pos) /*!< 0x00100000 */
+#define ADC_SQR3_SQ5_1 (0x02U << ADC_SQR3_SQ5_Pos) /*!< 0x00200000 */
+#define ADC_SQR3_SQ5_2 (0x04U << ADC_SQR3_SQ5_Pos) /*!< 0x00400000 */
+#define ADC_SQR3_SQ5_3 (0x08U << ADC_SQR3_SQ5_Pos) /*!< 0x00800000 */
+#define ADC_SQR3_SQ5_4 (0x10U << ADC_SQR3_SQ5_Pos) /*!< 0x01000000 */
+
+#define ADC_SQR3_SQ6_Pos (25U)
+#define ADC_SQR3_SQ6_Msk (0x1FU << ADC_SQR3_SQ6_Pos) /*!< 0x3E000000 */
+#define ADC_SQR3_SQ6 ADC_SQR3_SQ6_Msk /*!< ADC group regular sequencer rank 6 */
+#define ADC_SQR3_SQ6_0 (0x01U << ADC_SQR3_SQ6_Pos) /*!< 0x02000000 */
+#define ADC_SQR3_SQ6_1 (0x02U << ADC_SQR3_SQ6_Pos) /*!< 0x04000000 */
+#define ADC_SQR3_SQ6_2 (0x04U << ADC_SQR3_SQ6_Pos) /*!< 0x08000000 */
+#define ADC_SQR3_SQ6_3 (0x08U << ADC_SQR3_SQ6_Pos) /*!< 0x10000000 */
+#define ADC_SQR3_SQ6_4 (0x10U << ADC_SQR3_SQ6_Pos) /*!< 0x20000000 */
+
+/******************* Bit definition for ADC_JSQR register *******************/
+#define ADC_JSQR_JSQ1_Pos (0U)
+#define ADC_JSQR_JSQ1_Msk (0x1FU << ADC_JSQR_JSQ1_Pos) /*!< 0x0000001F */
+#define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!< ADC group injected sequencer rank 1 */
+#define ADC_JSQR_JSQ1_0 (0x01U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000001 */
+#define ADC_JSQR_JSQ1_1 (0x02U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000002 */
+#define ADC_JSQR_JSQ1_2 (0x04U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000004 */
+#define ADC_JSQR_JSQ1_3 (0x08U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000008 */
+#define ADC_JSQR_JSQ1_4 (0x10U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000010 */
+
+#define ADC_JSQR_JSQ2_Pos (5U)
+#define ADC_JSQR_JSQ2_Msk (0x1FU << ADC_JSQR_JSQ2_Pos) /*!< 0x000003E0 */
+#define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!< ADC group injected sequencer rank 2 */
+#define ADC_JSQR_JSQ2_0 (0x01U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000020 */
+#define ADC_JSQR_JSQ2_1 (0x02U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000040 */
+#define ADC_JSQR_JSQ2_2 (0x04U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000080 */
+#define ADC_JSQR_JSQ2_3 (0x08U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000100 */
+#define ADC_JSQR_JSQ2_4 (0x10U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000200 */
+
+#define ADC_JSQR_JSQ3_Pos (10U)
+#define ADC_JSQR_JSQ3_Msk (0x1FU << ADC_JSQR_JSQ3_Pos) /*!< 0x00007C00 */
+#define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!< ADC group injected sequencer rank 3 */
+#define ADC_JSQR_JSQ3_0 (0x01U << ADC_JSQR_JSQ3_Pos) /*!< 0x00000400 */
+#define ADC_JSQR_JSQ3_1 (0x02U << ADC_JSQR_JSQ3_Pos) /*!< 0x00000800 */
+#define ADC_JSQR_JSQ3_2 (0x04U << ADC_JSQR_JSQ3_Pos) /*!< 0x00001000 */
+#define ADC_JSQR_JSQ3_3 (0x08U << ADC_JSQR_JSQ3_Pos) /*!< 0x00002000 */
+#define ADC_JSQR_JSQ3_4 (0x10U << ADC_JSQR_JSQ3_Pos) /*!< 0x00004000 */
+
+#define ADC_JSQR_JSQ4_Pos (15U)
+#define ADC_JSQR_JSQ4_Msk (0x1FU << ADC_JSQR_JSQ4_Pos) /*!< 0x000F8000 */
+#define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!< ADC group injected sequencer rank 4 */
+#define ADC_JSQR_JSQ4_0 (0x01U << ADC_JSQR_JSQ4_Pos) /*!< 0x00008000 */
+#define ADC_JSQR_JSQ4_1 (0x02U << ADC_JSQR_JSQ4_Pos) /*!< 0x00010000 */
+#define ADC_JSQR_JSQ4_2 (0x04U << ADC_JSQR_JSQ4_Pos) /*!< 0x00020000 */
+#define ADC_JSQR_JSQ4_3 (0x08U << ADC_JSQR_JSQ4_Pos) /*!< 0x00040000 */
+#define ADC_JSQR_JSQ4_4 (0x10U << ADC_JSQR_JSQ4_Pos) /*!< 0x00080000 */
+
+#define ADC_JSQR_JL_Pos (20U)
+#define ADC_JSQR_JL_Msk (0x3U << ADC_JSQR_JL_Pos) /*!< 0x00300000 */
+#define ADC_JSQR_JL ADC_JSQR_JL_Msk /*!< ADC group injected sequencer scan length */
+#define ADC_JSQR_JL_0 (0x1U << ADC_JSQR_JL_Pos) /*!< 0x00100000 */
+#define ADC_JSQR_JL_1 (0x2U << ADC_JSQR_JL_Pos) /*!< 0x00200000 */
+
+/******************* Bit definition for ADC_JDR1 register *******************/
+#define ADC_JDR1_JDATA_Pos (0U)
+#define ADC_JDR1_JDATA_Msk (0xFFFFU << ADC_JDR1_JDATA_Pos) /*!< 0x0000FFFF */
+#define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!< ADC group injected sequencer rank 1 conversion data */
+
+/******************* Bit definition for ADC_JDR2 register *******************/
+#define ADC_JDR2_JDATA_Pos (0U)
+#define ADC_JDR2_JDATA_Msk (0xFFFFU << ADC_JDR2_JDATA_Pos) /*!< 0x0000FFFF */
+#define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!< ADC group injected sequencer rank 2 conversion data */
+
+/******************* Bit definition for ADC_JDR3 register *******************/
+#define ADC_JDR3_JDATA_Pos (0U)
+#define ADC_JDR3_JDATA_Msk (0xFFFFU << ADC_JDR3_JDATA_Pos) /*!< 0x0000FFFF */
+#define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!< ADC group injected sequencer rank 3 conversion data */
+
+/******************* Bit definition for ADC_JDR4 register *******************/
+#define ADC_JDR4_JDATA_Pos (0U)
+#define ADC_JDR4_JDATA_Msk (0xFFFFU << ADC_JDR4_JDATA_Pos) /*!< 0x0000FFFF */
+#define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!< ADC group injected sequencer rank 4 conversion data */
+
+/******************** Bit definition for ADC_DR register ********************/
+#define ADC_DR_DATA_Pos (0U)
+#define ADC_DR_DATA_Msk (0xFFFFU << ADC_DR_DATA_Pos) /*!< 0x0000FFFF */
+#define ADC_DR_DATA ADC_DR_DATA_Msk /*!< ADC group regular conversion data */
+/******************************************************************************/
+/* */
+/* Digital to Analog Converter */
+/* */
+/******************************************************************************/
+
+/******************** Bit definition for DAC_CR register ********************/
+#define DAC_CR_EN1_Pos (0U)
+#define DAC_CR_EN1_Msk (0x1U << DAC_CR_EN1_Pos) /*!< 0x00000001 */
+#define DAC_CR_EN1 DAC_CR_EN1_Msk /*!< DAC channel1 enable */
+#define DAC_CR_BOFF1_Pos (1U)
+#define DAC_CR_BOFF1_Msk (0x1U << DAC_CR_BOFF1_Pos) /*!< 0x00000002 */
+#define DAC_CR_BOFF1 DAC_CR_BOFF1_Msk /*!< DAC channel1 output buffer disable */
+#define DAC_CR_TEN1_Pos (2U)
+#define DAC_CR_TEN1_Msk (0x1U << DAC_CR_TEN1_Pos) /*!< 0x00000004 */
+#define DAC_CR_TEN1 DAC_CR_TEN1_Msk /*!< DAC channel1 Trigger enable */
+
+#define DAC_CR_TSEL1_Pos (3U)
+#define DAC_CR_TSEL1_Msk (0x7U << DAC_CR_TSEL1_Pos) /*!< 0x00000038 */
+#define DAC_CR_TSEL1 DAC_CR_TSEL1_Msk /*!< TSEL1[2:0] (DAC channel1 Trigger selection) */
+#define DAC_CR_TSEL1_0 (0x1U << DAC_CR_TSEL1_Pos) /*!< 0x00000008 */
+#define DAC_CR_TSEL1_1 (0x2U << DAC_CR_TSEL1_Pos) /*!< 0x00000010 */
+#define DAC_CR_TSEL1_2 (0x4U << DAC_CR_TSEL1_Pos) /*!< 0x00000020 */
+
+#define DAC_CR_WAVE1_Pos (6U)
+#define DAC_CR_WAVE1_Msk (0x3U << DAC_CR_WAVE1_Pos) /*!< 0x000000C0 */
+#define DAC_CR_WAVE1 DAC_CR_WAVE1_Msk /*!< WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
+#define DAC_CR_WAVE1_0 (0x1U << DAC_CR_WAVE1_Pos) /*!< 0x00000040 */
+#define DAC_CR_WAVE1_1 (0x2U << DAC_CR_WAVE1_Pos) /*!< 0x00000080 */
+
+#define DAC_CR_MAMP1_Pos (8U)
+#define DAC_CR_MAMP1_Msk (0xFU << DAC_CR_MAMP1_Pos) /*!< 0x00000F00 */
+#define DAC_CR_MAMP1 DAC_CR_MAMP1_Msk /*!< MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
+#define DAC_CR_MAMP1_0 (0x1U << DAC_CR_MAMP1_Pos) /*!< 0x00000100 */
+#define DAC_CR_MAMP1_1 (0x2U << DAC_CR_MAMP1_Pos) /*!< 0x00000200 */
+#define DAC_CR_MAMP1_2 (0x4U << DAC_CR_MAMP1_Pos) /*!< 0x00000400 */
+#define DAC_CR_MAMP1_3 (0x8U << DAC_CR_MAMP1_Pos) /*!< 0x00000800 */
+
+#define DAC_CR_DMAEN1_Pos (12U)
+#define DAC_CR_DMAEN1_Msk (0x1U << DAC_CR_DMAEN1_Pos) /*!< 0x00001000 */
+#define DAC_CR_DMAEN1 DAC_CR_DMAEN1_Msk /*!< DAC channel1 DMA enable */
+#define DAC_CR_EN2_Pos (16U)
+#define DAC_CR_EN2_Msk (0x1U << DAC_CR_EN2_Pos) /*!< 0x00010000 */
+#define DAC_CR_EN2 DAC_CR_EN2_Msk /*!< DAC channel2 enable */
+#define DAC_CR_BOFF2_Pos (17U)
+#define DAC_CR_BOFF2_Msk (0x1U << DAC_CR_BOFF2_Pos) /*!< 0x00020000 */
+#define DAC_CR_BOFF2 DAC_CR_BOFF2_Msk /*!< DAC channel2 output buffer disable */
+#define DAC_CR_TEN2_Pos (18U)
+#define DAC_CR_TEN2_Msk (0x1U << DAC_CR_TEN2_Pos) /*!< 0x00040000 */
+#define DAC_CR_TEN2 DAC_CR_TEN2_Msk /*!< DAC channel2 Trigger enable */
+
+#define DAC_CR_TSEL2_Pos (19U)
+#define DAC_CR_TSEL2_Msk (0x7U << DAC_CR_TSEL2_Pos) /*!< 0x00380000 */
+#define DAC_CR_TSEL2 DAC_CR_TSEL2_Msk /*!< TSEL2[2:0] (DAC channel2 Trigger selection) */
+#define DAC_CR_TSEL2_0 (0x1U << DAC_CR_TSEL2_Pos) /*!< 0x00080000 */
+#define DAC_CR_TSEL2_1 (0x2U << DAC_CR_TSEL2_Pos) /*!< 0x00100000 */
+#define DAC_CR_TSEL2_2 (0x4U << DAC_CR_TSEL2_Pos) /*!< 0x00200000 */
+
+#define DAC_CR_WAVE2_Pos (22U)
+#define DAC_CR_WAVE2_Msk (0x3U << DAC_CR_WAVE2_Pos) /*!< 0x00C00000 */
+#define DAC_CR_WAVE2 DAC_CR_WAVE2_Msk /*!< WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
+#define DAC_CR_WAVE2_0 (0x1U << DAC_CR_WAVE2_Pos) /*!< 0x00400000 */
+#define DAC_CR_WAVE2_1 (0x2U << DAC_CR_WAVE2_Pos) /*!< 0x00800000 */
+
+#define DAC_CR_MAMP2_Pos (24U)
+#define DAC_CR_MAMP2_Msk (0xFU << DAC_CR_MAMP2_Pos) /*!< 0x0F000000 */
+#define DAC_CR_MAMP2 DAC_CR_MAMP2_Msk /*!< MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
+#define DAC_CR_MAMP2_0 (0x1U << DAC_CR_MAMP2_Pos) /*!< 0x01000000 */
+#define DAC_CR_MAMP2_1 (0x2U << DAC_CR_MAMP2_Pos) /*!< 0x02000000 */
+#define DAC_CR_MAMP2_2 (0x4U << DAC_CR_MAMP2_Pos) /*!< 0x04000000 */
+#define DAC_CR_MAMP2_3 (0x8U << DAC_CR_MAMP2_Pos) /*!< 0x08000000 */
+
+#define DAC_CR_DMAEN2_Pos (28U)
+#define DAC_CR_DMAEN2_Msk (0x1U << DAC_CR_DMAEN2_Pos) /*!< 0x10000000 */
+#define DAC_CR_DMAEN2 DAC_CR_DMAEN2_Msk /*!< DAC channel2 DMA enabled */
+
+#define DAC_CR_DMAUDRIE1_Pos (13U)
+#define DAC_CR_DMAUDRIE1_Msk (0x1U << DAC_CR_DMAUDRIE1_Pos) /*!< 0x00002000 */
+#define DAC_CR_DMAUDRIE1 DAC_CR_DMAUDRIE1_Msk /*!< DAC channel1 DMA underrun interrupt enable */
+#define DAC_CR_DMAUDRIE2_Pos (29U)
+#define DAC_CR_DMAUDRIE2_Msk (0x1U << DAC_CR_DMAUDRIE2_Pos) /*!< 0x20000000 */
+#define DAC_CR_DMAUDRIE2 DAC_CR_DMAUDRIE2_Msk /*!< DAC channel2 DMA underrun interrupt enable */
+
+/***************** Bit definition for DAC_SWTRIGR register ******************/
+#define DAC_SWTRIGR_SWTRIG1_Pos (0U)
+#define DAC_SWTRIGR_SWTRIG1_Msk (0x1U << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */
+#define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /*!< DAC channel1 software trigger */
+#define DAC_SWTRIGR_SWTRIG2_Pos (1U)
+#define DAC_SWTRIGR_SWTRIG2_Msk (0x1U << DAC_SWTRIGR_SWTRIG2_Pos) /*!< 0x00000002 */
+#define DAC_SWTRIGR_SWTRIG2 DAC_SWTRIGR_SWTRIG2_Msk /*!< DAC channel2 software trigger */
+
+/***************** Bit definition for DAC_DHR12R1 register ******************/
+#define DAC_DHR12R1_DACC1DHR_Pos (0U)
+#define DAC_DHR12R1_DACC1DHR_Msk (0xFFFU << DAC_DHR12R1_DACC1DHR_Pos) /*!< 0x00000FFF */
+#define DAC_DHR12R1_DACC1DHR DAC_DHR12R1_DACC1DHR_Msk /*!< DAC channel1 12-bit Right aligned data */
+
+/***************** Bit definition for DAC_DHR12L1 register ******************/
+#define DAC_DHR12L1_DACC1DHR_Pos (4U)
+#define DAC_DHR12L1_DACC1DHR_Msk (0xFFFU << DAC_DHR12L1_DACC1DHR_Pos) /*!< 0x0000FFF0 */
+#define DAC_DHR12L1_DACC1DHR DAC_DHR12L1_DACC1DHR_Msk /*!< DAC channel1 12-bit Left aligned data */
+
+/****************** Bit definition for DAC_DHR8R1 register ******************/
+#define DAC_DHR8R1_DACC1DHR_Pos (0U)
+#define DAC_DHR8R1_DACC1DHR_Msk (0xFFU << DAC_DHR8R1_DACC1DHR_Pos) /*!< 0x000000FF */
+#define DAC_DHR8R1_DACC1DHR DAC_DHR8R1_DACC1DHR_Msk /*!< DAC channel1 8-bit Right aligned data */
+
+/***************** Bit definition for DAC_DHR12R2 register ******************/
+#define DAC_DHR12R2_DACC2DHR_Pos (0U)
+#define DAC_DHR12R2_DACC2DHR_Msk (0xFFFU << DAC_DHR12R2_DACC2DHR_Pos) /*!< 0x00000FFF */
+#define DAC_DHR12R2_DACC2DHR DAC_DHR12R2_DACC2DHR_Msk /*!< DAC channel2 12-bit Right aligned data */
+
+/***************** Bit definition for DAC_DHR12L2 register ******************/
+#define DAC_DHR12L2_DACC2DHR_Pos (4U)
+#define DAC_DHR12L2_DACC2DHR_Msk (0xFFFU << DAC_DHR12L2_DACC2DHR_Pos) /*!< 0x0000FFF0 */
+#define DAC_DHR12L2_DACC2DHR DAC_DHR12L2_DACC2DHR_Msk /*!< DAC channel2 12-bit Left aligned data */
+
+/****************** Bit definition for DAC_DHR8R2 register ******************/
+#define DAC_DHR8R2_DACC2DHR_Pos (0U)
+#define DAC_DHR8R2_DACC2DHR_Msk (0xFFU << DAC_DHR8R2_DACC2DHR_Pos) /*!< 0x000000FF */
+#define DAC_DHR8R2_DACC2DHR DAC_DHR8R2_DACC2DHR_Msk /*!< DAC channel2 8-bit Right aligned data */
+
+/***************** Bit definition for DAC_DHR12RD register ******************/
+#define DAC_DHR12RD_DACC1DHR_Pos (0U)
+#define DAC_DHR12RD_DACC1DHR_Msk (0xFFFU << DAC_DHR12RD_DACC1DHR_Pos) /*!< 0x00000FFF */
+#define DAC_DHR12RD_DACC1DHR DAC_DHR12RD_DACC1DHR_Msk /*!< DAC channel1 12-bit Right aligned data */
+#define DAC_DHR12RD_DACC2DHR_Pos (16U)
+#define DAC_DHR12RD_DACC2DHR_Msk (0xFFFU << DAC_DHR12RD_DACC2DHR_Pos) /*!< 0x0FFF0000 */
+#define DAC_DHR12RD_DACC2DHR DAC_DHR12RD_DACC2DHR_Msk /*!< DAC channel2 12-bit Right aligned data */
+
+/***************** Bit definition for DAC_DHR12LD register ******************/
+#define DAC_DHR12LD_DACC1DHR_Pos (4U)
+#define DAC_DHR12LD_DACC1DHR_Msk (0xFFFU << DAC_DHR12LD_DACC1DHR_Pos) /*!< 0x0000FFF0 */
+#define DAC_DHR12LD_DACC1DHR DAC_DHR12LD_DACC1DHR_Msk /*!< DAC channel1 12-bit Left aligned data */
+#define DAC_DHR12LD_DACC2DHR_Pos (20U)
+#define DAC_DHR12LD_DACC2DHR_Msk (0xFFFU << DAC_DHR12LD_DACC2DHR_Pos) /*!< 0xFFF00000 */
+#define DAC_DHR12LD_DACC2DHR DAC_DHR12LD_DACC2DHR_Msk /*!< DAC channel2 12-bit Left aligned data */
+
+/****************** Bit definition for DAC_DHR8RD register ******************/
+#define DAC_DHR8RD_DACC1DHR_Pos (0U)
+#define DAC_DHR8RD_DACC1DHR_Msk (0xFFU << DAC_DHR8RD_DACC1DHR_Pos) /*!< 0x000000FF */
+#define DAC_DHR8RD_DACC1DHR DAC_DHR8RD_DACC1DHR_Msk /*!< DAC channel1 8-bit Right aligned data */
+#define DAC_DHR8RD_DACC2DHR_Pos (8U)
+#define DAC_DHR8RD_DACC2DHR_Msk (0xFFU << DAC_DHR8RD_DACC2DHR_Pos) /*!< 0x0000FF00 */
+#define DAC_DHR8RD_DACC2DHR DAC_DHR8RD_DACC2DHR_Msk /*!< DAC channel2 8-bit Right aligned data */
+
+/******************* Bit definition for DAC_DOR1 register *******************/
+#define DAC_DOR1_DACC1DOR_Pos (0U)
+#define DAC_DOR1_DACC1DOR_Msk (0xFFFU << DAC_DOR1_DACC1DOR_Pos) /*!< 0x00000FFF */
+#define DAC_DOR1_DACC1DOR DAC_DOR1_DACC1DOR_Msk /*!< DAC channel1 data output */
+
+/******************* Bit definition for DAC_DOR2 register *******************/
+#define DAC_DOR2_DACC2DOR_Pos (0U)
+#define DAC_DOR2_DACC2DOR_Msk (0xFFFU << DAC_DOR2_DACC2DOR_Pos) /*!< 0x00000FFF */
+#define DAC_DOR2_DACC2DOR DAC_DOR2_DACC2DOR_Msk /*!< DAC channel2 data output */
+
+/******************** Bit definition for DAC_SR register ********************/
+#define DAC_SR_DMAUDR1_Pos (13U)
+#define DAC_SR_DMAUDR1_Msk (0x1U << DAC_SR_DMAUDR1_Pos) /*!< 0x00002000 */
+#define DAC_SR_DMAUDR1 DAC_SR_DMAUDR1_Msk /*!< DAC channel1 DMA underrun flag */
+#define DAC_SR_DMAUDR2_Pos (29U)
+#define DAC_SR_DMAUDR2_Msk (0x1U << DAC_SR_DMAUDR2_Pos) /*!< 0x20000000 */
+#define DAC_SR_DMAUDR2 DAC_SR_DMAUDR2_Msk /*!< DAC channel2 DMA underrun flag */
+
+/******************************************************************************/
+/* */
+/* CEC */
+/* */
+/******************************************************************************/
+/******************** Bit definition for CEC_CFGR register ******************/
+#define CEC_CFGR_PE_Pos (0U)
+#define CEC_CFGR_PE_Msk (0x1U << CEC_CFGR_PE_Pos) /*!< 0x00000001 */
+#define CEC_CFGR_PE CEC_CFGR_PE_Msk /*!< Peripheral Enable */
+#define CEC_CFGR_IE_Pos (1U)
+#define CEC_CFGR_IE_Msk (0x1U << CEC_CFGR_IE_Pos) /*!< 0x00000002 */
+#define CEC_CFGR_IE CEC_CFGR_IE_Msk /*!< Interrupt Enable */
+#define CEC_CFGR_BTEM_Pos (2U)
+#define CEC_CFGR_BTEM_Msk (0x1U << CEC_CFGR_BTEM_Pos) /*!< 0x00000004 */
+#define CEC_CFGR_BTEM CEC_CFGR_BTEM_Msk /*!< Bit Timing Error Mode */
+#define CEC_CFGR_BPEM_Pos (3U)
+#define CEC_CFGR_BPEM_Msk (0x1U << CEC_CFGR_BPEM_Pos) /*!< 0x00000008 */
+#define CEC_CFGR_BPEM CEC_CFGR_BPEM_Msk /*!< Bit Period Error Mode */
+
+/******************** Bit definition for CEC_OAR register ******************/
+#define CEC_OAR_OA_Pos (0U)
+#define CEC_OAR_OA_Msk (0xFU << CEC_OAR_OA_Pos) /*!< 0x0000000F */
+#define CEC_OAR_OA CEC_OAR_OA_Msk /*!< OA[3:0]: Own Address */
+#define CEC_OAR_OA_0 (0x1U << CEC_OAR_OA_Pos) /*!< 0x00000001 */
+#define CEC_OAR_OA_1 (0x2U << CEC_OAR_OA_Pos) /*!< 0x00000002 */
+#define CEC_OAR_OA_2 (0x4U << CEC_OAR_OA_Pos) /*!< 0x00000004 */
+#define CEC_OAR_OA_3 (0x8U << CEC_OAR_OA_Pos) /*!< 0x00000008 */
+
+/******************** Bit definition for CEC_PRES register ******************/
+#define CEC_PRES_PRES_Pos (0U)
+#define CEC_PRES_PRES_Msk (0x3FFFU << CEC_PRES_PRES_Pos) /*!< 0x00003FFF */
+#define CEC_PRES_PRES CEC_PRES_PRES_Msk /*!< Prescaler Counter Value */
+
+/******************** Bit definition for CEC_ESR register ******************/
+#define CEC_ESR_BTE_Pos (0U)
+#define CEC_ESR_BTE_Msk (0x1U << CEC_ESR_BTE_Pos) /*!< 0x00000001 */
+#define CEC_ESR_BTE CEC_ESR_BTE_Msk /*!< Bit Timing Error */
+#define CEC_ESR_BPE_Pos (1U)
+#define CEC_ESR_BPE_Msk (0x1U << CEC_ESR_BPE_Pos) /*!< 0x00000002 */
+#define CEC_ESR_BPE CEC_ESR_BPE_Msk /*!< Bit Period Error */
+#define CEC_ESR_RBTFE_Pos (2U)
+#define CEC_ESR_RBTFE_Msk (0x1U << CEC_ESR_RBTFE_Pos) /*!< 0x00000004 */
+#define CEC_ESR_RBTFE CEC_ESR_RBTFE_Msk /*!< Rx Block Transfer Finished Error */
+#define CEC_ESR_SBE_Pos (3U)
+#define CEC_ESR_SBE_Msk (0x1U << CEC_ESR_SBE_Pos) /*!< 0x00000008 */
+#define CEC_ESR_SBE CEC_ESR_SBE_Msk /*!< Start Bit Error */
+#define CEC_ESR_ACKE_Pos (4U)
+#define CEC_ESR_ACKE_Msk (0x1U << CEC_ESR_ACKE_Pos) /*!< 0x00000010 */
+#define CEC_ESR_ACKE CEC_ESR_ACKE_Msk /*!< Block Acknowledge Error */
+#define CEC_ESR_LINE_Pos (5U)
+#define CEC_ESR_LINE_Msk (0x1U << CEC_ESR_LINE_Pos) /*!< 0x00000020 */
+#define CEC_ESR_LINE CEC_ESR_LINE_Msk /*!< Line Error */
+#define CEC_ESR_TBTFE_Pos (6U)
+#define CEC_ESR_TBTFE_Msk (0x1U << CEC_ESR_TBTFE_Pos) /*!< 0x00000040 */
+#define CEC_ESR_TBTFE CEC_ESR_TBTFE_Msk /*!< Tx Block Transfer Finished Error */
+
+/******************** Bit definition for CEC_CSR register ******************/
+#define CEC_CSR_TSOM_Pos (0U)
+#define CEC_CSR_TSOM_Msk (0x1U << CEC_CSR_TSOM_Pos) /*!< 0x00000001 */
+#define CEC_CSR_TSOM CEC_CSR_TSOM_Msk /*!< Tx Start Of Message */
+#define CEC_CSR_TEOM_Pos (1U)
+#define CEC_CSR_TEOM_Msk (0x1U << CEC_CSR_TEOM_Pos) /*!< 0x00000002 */
+#define CEC_CSR_TEOM CEC_CSR_TEOM_Msk /*!< Tx End Of Message */
+#define CEC_CSR_TERR_Pos (2U)
+#define CEC_CSR_TERR_Msk (0x1U << CEC_CSR_TERR_Pos) /*!< 0x00000004 */
+#define CEC_CSR_TERR CEC_CSR_TERR_Msk /*!< Tx Error */
+#define CEC_CSR_TBTRF_Pos (3U)
+#define CEC_CSR_TBTRF_Msk (0x1U << CEC_CSR_TBTRF_Pos) /*!< 0x00000008 */
+#define CEC_CSR_TBTRF CEC_CSR_TBTRF_Msk /*!< Tx Byte Transfer Request or Block Transfer Finished */
+#define CEC_CSR_RSOM_Pos (4U)
+#define CEC_CSR_RSOM_Msk (0x1U << CEC_CSR_RSOM_Pos) /*!< 0x00000010 */
+#define CEC_CSR_RSOM CEC_CSR_RSOM_Msk /*!< Rx Start Of Message */
+#define CEC_CSR_REOM_Pos (5U)
+#define CEC_CSR_REOM_Msk (0x1U << CEC_CSR_REOM_Pos) /*!< 0x00000020 */
+#define CEC_CSR_REOM CEC_CSR_REOM_Msk /*!< Rx End Of Message */
+#define CEC_CSR_RERR_Pos (6U)
+#define CEC_CSR_RERR_Msk (0x1U << CEC_CSR_RERR_Pos) /*!< 0x00000040 */
+#define CEC_CSR_RERR CEC_CSR_RERR_Msk /*!< Rx Error */
+#define CEC_CSR_RBTF_Pos (7U)
+#define CEC_CSR_RBTF_Msk (0x1U << CEC_CSR_RBTF_Pos) /*!< 0x00000080 */
+#define CEC_CSR_RBTF CEC_CSR_RBTF_Msk /*!< Rx Block Transfer Finished */
+
+/******************** Bit definition for CEC_TXD register ******************/
+#define CEC_TXD_TXD_Pos (0U)
+#define CEC_TXD_TXD_Msk (0xFFU << CEC_TXD_TXD_Pos) /*!< 0x000000FF */
+#define CEC_TXD_TXD CEC_TXD_TXD_Msk /*!< Tx Data register */
+
+/******************** Bit definition for CEC_RXD register ******************/
+#define CEC_RXD_RXD_Pos (0U)
+#define CEC_RXD_RXD_Msk (0xFFU << CEC_RXD_RXD_Pos) /*!< 0x000000FF */
+#define CEC_RXD_RXD CEC_RXD_RXD_Msk /*!< Rx Data register */
+
+/*****************************************************************************/
+/* */
+/* Timers (TIM) */
+/* */
+/*****************************************************************************/
+/******************* Bit definition for TIM_CR1 register *******************/
+#define TIM_CR1_CEN_Pos (0U)
+#define TIM_CR1_CEN_Msk (0x1U << TIM_CR1_CEN_Pos) /*!< 0x00000001 */
+#define TIM_CR1_CEN TIM_CR1_CEN_Msk /*!<Counter enable */
+#define TIM_CR1_UDIS_Pos (1U)
+#define TIM_CR1_UDIS_Msk (0x1U << TIM_CR1_UDIS_Pos) /*!< 0x00000002 */
+#define TIM_CR1_UDIS TIM_CR1_UDIS_Msk /*!<Update disable */
+#define TIM_CR1_URS_Pos (2U)
+#define TIM_CR1_URS_Msk (0x1U << TIM_CR1_URS_Pos) /*!< 0x00000004 */
+#define TIM_CR1_URS TIM_CR1_URS_Msk /*!<Update request source */
+#define TIM_CR1_OPM_Pos (3U)
+#define TIM_CR1_OPM_Msk (0x1U << TIM_CR1_OPM_Pos) /*!< 0x00000008 */
+#define TIM_CR1_OPM TIM_CR1_OPM_Msk /*!<One pulse mode */
+#define TIM_CR1_DIR_Pos (4U)
+#define TIM_CR1_DIR_Msk (0x1U << TIM_CR1_DIR_Pos) /*!< 0x00000010 */
+#define TIM_CR1_DIR TIM_CR1_DIR_Msk /*!<Direction */
+
+#define TIM_CR1_CMS_Pos (5U)
+#define TIM_CR1_CMS_Msk (0x3U << TIM_CR1_CMS_Pos) /*!< 0x00000060 */
+#define TIM_CR1_CMS TIM_CR1_CMS_Msk /*!<CMS[1:0] bits (Center-aligned mode selection) */
+#define TIM_CR1_CMS_0 (0x1U << TIM_CR1_CMS_Pos) /*!< 0x00000020 */
+#define TIM_CR1_CMS_1 (0x2U << TIM_CR1_CMS_Pos) /*!< 0x00000040 */
+
+#define TIM_CR1_ARPE_Pos (7U)
+#define TIM_CR1_ARPE_Msk (0x1U << TIM_CR1_ARPE_Pos) /*!< 0x00000080 */
+#define TIM_CR1_ARPE TIM_CR1_ARPE_Msk /*!<Auto-reload preload enable */
+
+#define TIM_CR1_CKD_Pos (8U)
+#define TIM_CR1_CKD_Msk (0x3U << TIM_CR1_CKD_Pos) /*!< 0x00000300 */
+#define TIM_CR1_CKD TIM_CR1_CKD_Msk /*!<CKD[1:0] bits (clock division) */
+#define TIM_CR1_CKD_0 (0x1U << TIM_CR1_CKD_Pos) /*!< 0x00000100 */
+#define TIM_CR1_CKD_1 (0x2U << TIM_CR1_CKD_Pos) /*!< 0x00000200 */
+
+/******************* Bit definition for TIM_CR2 register *******************/
+#define TIM_CR2_CCPC_Pos (0U)
+#define TIM_CR2_CCPC_Msk (0x1U << TIM_CR2_CCPC_Pos) /*!< 0x00000001 */
+#define TIM_CR2_CCPC TIM_CR2_CCPC_Msk /*!<Capture/Compare Preloaded Control */
+#define TIM_CR2_CCUS_Pos (2U)
+#define TIM_CR2_CCUS_Msk (0x1U << TIM_CR2_CCUS_Pos) /*!< 0x00000004 */
+#define TIM_CR2_CCUS TIM_CR2_CCUS_Msk /*!<Capture/Compare Control Update Selection */
+#define TIM_CR2_CCDS_Pos (3U)
+#define TIM_CR2_CCDS_Msk (0x1U << TIM_CR2_CCDS_Pos) /*!< 0x00000008 */
+#define TIM_CR2_CCDS TIM_CR2_CCDS_Msk /*!<Capture/Compare DMA Selection */
+
+#define TIM_CR2_MMS_Pos (4U)
+#define TIM_CR2_MMS_Msk (0x7U << TIM_CR2_MMS_Pos) /*!< 0x00000070 */
+#define TIM_CR2_MMS TIM_CR2_MMS_Msk /*!<MMS[2:0] bits (Master Mode Selection) */
+#define TIM_CR2_MMS_0 (0x1U << TIM_CR2_MMS_Pos) /*!< 0x00000010 */
+#define TIM_CR2_MMS_1 (0x2U << TIM_CR2_MMS_Pos) /*!< 0x00000020 */
+#define TIM_CR2_MMS_2 (0x4U << TIM_CR2_MMS_Pos) /*!< 0x00000040 */
+
+#define TIM_CR2_TI1S_Pos (7U)
+#define TIM_CR2_TI1S_Msk (0x1U << TIM_CR2_TI1S_Pos) /*!< 0x00000080 */
+#define TIM_CR2_TI1S TIM_CR2_TI1S_Msk /*!<TI1 Selection */
+#define TIM_CR2_OIS1_Pos (8U)
+#define TIM_CR2_OIS1_Msk (0x1U << TIM_CR2_OIS1_Pos) /*!< 0x00000100 */
+#define TIM_CR2_OIS1 TIM_CR2_OIS1_Msk /*!<Output Idle state 1 (OC1 output) */
+#define TIM_CR2_OIS1N_Pos (9U)
+#define TIM_CR2_OIS1N_Msk (0x1U << TIM_CR2_OIS1N_Pos) /*!< 0x00000200 */
+#define TIM_CR2_OIS1N TIM_CR2_OIS1N_Msk /*!<Output Idle state 1 (OC1N output) */
+#define TIM_CR2_OIS2_Pos (10U)
+#define TIM_CR2_OIS2_Msk (0x1U << TIM_CR2_OIS2_Pos) /*!< 0x00000400 */
+#define TIM_CR2_OIS2 TIM_CR2_OIS2_Msk /*!<Output Idle state 2 (OC2 output) */
+#define TIM_CR2_OIS2N_Pos (11U)
+#define TIM_CR2_OIS2N_Msk (0x1U << TIM_CR2_OIS2N_Pos) /*!< 0x00000800 */
+#define TIM_CR2_OIS2N TIM_CR2_OIS2N_Msk /*!<Output Idle state 2 (OC2N output) */
+#define TIM_CR2_OIS3_Pos (12U)
+#define TIM_CR2_OIS3_Msk (0x1U << TIM_CR2_OIS3_Pos) /*!< 0x00001000 */
+#define TIM_CR2_OIS3 TIM_CR2_OIS3_Msk /*!<Output Idle state 3 (OC3 output) */
+#define TIM_CR2_OIS3N_Pos (13U)
+#define TIM_CR2_OIS3N_Msk (0x1U << TIM_CR2_OIS3N_Pos) /*!< 0x00002000 */
+#define TIM_CR2_OIS3N TIM_CR2_OIS3N_Msk /*!<Output Idle state 3 (OC3N output) */
+#define TIM_CR2_OIS4_Pos (14U)
+#define TIM_CR2_OIS4_Msk (0x1U << TIM_CR2_OIS4_Pos) /*!< 0x00004000 */
+#define TIM_CR2_OIS4 TIM_CR2_OIS4_Msk /*!<Output Idle state 4 (OC4 output) */
+
+/******************* Bit definition for TIM_SMCR register ******************/
+#define TIM_SMCR_SMS_Pos (0U)
+#define TIM_SMCR_SMS_Msk (0x7U << TIM_SMCR_SMS_Pos) /*!< 0x00000007 */
+#define TIM_SMCR_SMS TIM_SMCR_SMS_Msk /*!<SMS[2:0] bits (Slave mode selection) */
+#define TIM_SMCR_SMS_0 (0x1U << TIM_SMCR_SMS_Pos) /*!< 0x00000001 */
+#define TIM_SMCR_SMS_1 (0x2U << TIM_SMCR_SMS_Pos) /*!< 0x00000002 */
+#define TIM_SMCR_SMS_2 (0x4U << TIM_SMCR_SMS_Pos) /*!< 0x00000004 */
+
+#define TIM_SMCR_OCCS_Pos (3U)
+#define TIM_SMCR_OCCS_Msk (0x1U << TIM_SMCR_OCCS_Pos) /*!< 0x00000008 */
+#define TIM_SMCR_OCCS TIM_SMCR_OCCS_Msk /*!< OCREF clear selection */
+
+#define TIM_SMCR_TS_Pos (4U)
+#define TIM_SMCR_TS_Msk (0x7U << TIM_SMCR_TS_Pos) /*!< 0x00000070 */
+#define TIM_SMCR_TS TIM_SMCR_TS_Msk /*!<TS[2:0] bits (Trigger selection) */
+#define TIM_SMCR_TS_0 (0x1U << TIM_SMCR_TS_Pos) /*!< 0x00000010 */
+#define TIM_SMCR_TS_1 (0x2U << TIM_SMCR_TS_Pos) /*!< 0x00000020 */
+#define TIM_SMCR_TS_2 (0x4U << TIM_SMCR_TS_Pos) /*!< 0x00000040 */
+
+#define TIM_SMCR_MSM_Pos (7U)
+#define TIM_SMCR_MSM_Msk (0x1U << TIM_SMCR_MSM_Pos) /*!< 0x00000080 */
+#define TIM_SMCR_MSM TIM_SMCR_MSM_Msk /*!<Master/slave mode */
+
+#define TIM_SMCR_ETF_Pos (8U)
+#define TIM_SMCR_ETF_Msk (0xFU << TIM_SMCR_ETF_Pos) /*!< 0x00000F00 */
+#define TIM_SMCR_ETF TIM_SMCR_ETF_Msk /*!<ETF[3:0] bits (External trigger filter) */
+#define TIM_SMCR_ETF_0 (0x1U << TIM_SMCR_ETF_Pos) /*!< 0x00000100 */
+#define TIM_SMCR_ETF_1 (0x2U << TIM_SMCR_ETF_Pos) /*!< 0x00000200 */
+#define TIM_SMCR_ETF_2 (0x4U << TIM_SMCR_ETF_Pos) /*!< 0x00000400 */
+#define TIM_SMCR_ETF_3 (0x8U << TIM_SMCR_ETF_Pos) /*!< 0x00000800 */
+
+#define TIM_SMCR_ETPS_Pos (12U)
+#define TIM_SMCR_ETPS_Msk (0x3U << TIM_SMCR_ETPS_Pos) /*!< 0x00003000 */
+#define TIM_SMCR_ETPS TIM_SMCR_ETPS_Msk /*!<ETPS[1:0] bits (External trigger prescaler) */
+#define TIM_SMCR_ETPS_0 (0x1U << TIM_SMCR_ETPS_Pos) /*!< 0x00001000 */
+#define TIM_SMCR_ETPS_1 (0x2U << TIM_SMCR_ETPS_Pos) /*!< 0x00002000 */
+
+#define TIM_SMCR_ECE_Pos (14U)
+#define TIM_SMCR_ECE_Msk (0x1U << TIM_SMCR_ECE_Pos) /*!< 0x00004000 */
+#define TIM_SMCR_ECE TIM_SMCR_ECE_Msk /*!<External clock enable */
+#define TIM_SMCR_ETP_Pos (15U)
+#define TIM_SMCR_ETP_Msk (0x1U << TIM_SMCR_ETP_Pos) /*!< 0x00008000 */
+#define TIM_SMCR_ETP TIM_SMCR_ETP_Msk /*!<External trigger polarity */
+
+/******************* Bit definition for TIM_DIER register ******************/
+#define TIM_DIER_UIE_Pos (0U)
+#define TIM_DIER_UIE_Msk (0x1U << TIM_DIER_UIE_Pos) /*!< 0x00000001 */
+#define TIM_DIER_UIE TIM_DIER_UIE_Msk /*!<Update interrupt enable */
+#define TIM_DIER_CC1IE_Pos (1U)
+#define TIM_DIER_CC1IE_Msk (0x1U << TIM_DIER_CC1IE_Pos) /*!< 0x00000002 */
+#define TIM_DIER_CC1IE TIM_DIER_CC1IE_Msk /*!<Capture/Compare 1 interrupt enable */
+#define TIM_DIER_CC2IE_Pos (2U)
+#define TIM_DIER_CC2IE_Msk (0x1U << TIM_DIER_CC2IE_Pos) /*!< 0x00000004 */
+#define TIM_DIER_CC2IE TIM_DIER_CC2IE_Msk /*!<Capture/Compare 2 interrupt enable */
+#define TIM_DIER_CC3IE_Pos (3U)
+#define TIM_DIER_CC3IE_Msk (0x1U << TIM_DIER_CC3IE_Pos) /*!< 0x00000008 */
+#define TIM_DIER_CC3IE TIM_DIER_CC3IE_Msk /*!<Capture/Compare 3 interrupt enable */
+#define TIM_DIER_CC4IE_Pos (4U)
+#define TIM_DIER_CC4IE_Msk (0x1U << TIM_DIER_CC4IE_Pos) /*!< 0x00000010 */
+#define TIM_DIER_CC4IE TIM_DIER_CC4IE_Msk /*!<Capture/Compare 4 interrupt enable */
+#define TIM_DIER_COMIE_Pos (5U)
+#define TIM_DIER_COMIE_Msk (0x1U << TIM_DIER_COMIE_Pos) /*!< 0x00000020 */
+#define TIM_DIER_COMIE TIM_DIER_COMIE_Msk /*!<COM interrupt enable */
+#define TIM_DIER_TIE_Pos (6U)
+#define TIM_DIER_TIE_Msk (0x1U << TIM_DIER_TIE_Pos) /*!< 0x00000040 */
+#define TIM_DIER_TIE TIM_DIER_TIE_Msk /*!<Trigger interrupt enable */
+#define TIM_DIER_BIE_Pos (7U)
+#define TIM_DIER_BIE_Msk (0x1U << TIM_DIER_BIE_Pos) /*!< 0x00000080 */
+#define TIM_DIER_BIE TIM_DIER_BIE_Msk /*!<Break interrupt enable */
+#define TIM_DIER_UDE_Pos (8U)
+#define TIM_DIER_UDE_Msk (0x1U << TIM_DIER_UDE_Pos) /*!< 0x00000100 */
+#define TIM_DIER_UDE TIM_DIER_UDE_Msk /*!<Update DMA request enable */
+#define TIM_DIER_CC1DE_Pos (9U)
+#define TIM_DIER_CC1DE_Msk (0x1U << TIM_DIER_CC1DE_Pos) /*!< 0x00000200 */
+#define TIM_DIER_CC1DE TIM_DIER_CC1DE_Msk /*!<Capture/Compare 1 DMA request enable */
+#define TIM_DIER_CC2DE_Pos (10U)
+#define TIM_DIER_CC2DE_Msk (0x1U << TIM_DIER_CC2DE_Pos) /*!< 0x00000400 */
+#define TIM_DIER_CC2DE TIM_DIER_CC2DE_Msk /*!<Capture/Compare 2 DMA request enable */
+#define TIM_DIER_CC3DE_Pos (11U)
+#define TIM_DIER_CC3DE_Msk (0x1U << TIM_DIER_CC3DE_Pos) /*!< 0x00000800 */
+#define TIM_DIER_CC3DE TIM_DIER_CC3DE_Msk /*!<Capture/Compare 3 DMA request enable */
+#define TIM_DIER_CC4DE_Pos (12U)
+#define TIM_DIER_CC4DE_Msk (0x1U << TIM_DIER_CC4DE_Pos) /*!< 0x00001000 */
+#define TIM_DIER_CC4DE TIM_DIER_CC4DE_Msk /*!<Capture/Compare 4 DMA request enable */
+#define TIM_DIER_COMDE_Pos (13U)
+#define TIM_DIER_COMDE_Msk (0x1U << TIM_DIER_COMDE_Pos) /*!< 0x00002000 */
+#define TIM_DIER_COMDE TIM_DIER_COMDE_Msk /*!<COM DMA request enable */
+#define TIM_DIER_TDE_Pos (14U)
+#define TIM_DIER_TDE_Msk (0x1U << TIM_DIER_TDE_Pos) /*!< 0x00004000 */
+#define TIM_DIER_TDE TIM_DIER_TDE_Msk /*!<Trigger DMA request enable */
+
+/******************** Bit definition for TIM_SR register *******************/
+#define TIM_SR_UIF_Pos (0U)
+#define TIM_SR_UIF_Msk (0x1U << TIM_SR_UIF_Pos) /*!< 0x00000001 */
+#define TIM_SR_UIF TIM_SR_UIF_Msk /*!<Update interrupt Flag */
+#define TIM_SR_CC1IF_Pos (1U)
+#define TIM_SR_CC1IF_Msk (0x1U << TIM_SR_CC1IF_Pos) /*!< 0x00000002 */
+#define TIM_SR_CC1IF TIM_SR_CC1IF_Msk /*!<Capture/Compare 1 interrupt Flag */
+#define TIM_SR_CC2IF_Pos (2U)
+#define TIM_SR_CC2IF_Msk (0x1U << TIM_SR_CC2IF_Pos) /*!< 0x00000004 */
+#define TIM_SR_CC2IF TIM_SR_CC2IF_Msk /*!<Capture/Compare 2 interrupt Flag */
+#define TIM_SR_CC3IF_Pos (3U)
+#define TIM_SR_CC3IF_Msk (0x1U << TIM_SR_CC3IF_Pos) /*!< 0x00000008 */
+#define TIM_SR_CC3IF TIM_SR_CC3IF_Msk /*!<Capture/Compare 3 interrupt Flag */
+#define TIM_SR_CC4IF_Pos (4U)
+#define TIM_SR_CC4IF_Msk (0x1U << TIM_SR_CC4IF_Pos) /*!< 0x00000010 */
+#define TIM_SR_CC4IF TIM_SR_CC4IF_Msk /*!<Capture/Compare 4 interrupt Flag */
+#define TIM_SR_COMIF_Pos (5U)
+#define TIM_SR_COMIF_Msk (0x1U << TIM_SR_COMIF_Pos) /*!< 0x00000020 */
+#define TIM_SR_COMIF TIM_SR_COMIF_Msk /*!<COM interrupt Flag */
+#define TIM_SR_TIF_Pos (6U)
+#define TIM_SR_TIF_Msk (0x1U << TIM_SR_TIF_Pos) /*!< 0x00000040 */
+#define TIM_SR_TIF TIM_SR_TIF_Msk /*!<Trigger interrupt Flag */
+#define TIM_SR_BIF_Pos (7U)
+#define TIM_SR_BIF_Msk (0x1U << TIM_SR_BIF_Pos) /*!< 0x00000080 */
+#define TIM_SR_BIF TIM_SR_BIF_Msk /*!<Break interrupt Flag */
+#define TIM_SR_CC1OF_Pos (9U)
+#define TIM_SR_CC1OF_Msk (0x1U << TIM_SR_CC1OF_Pos) /*!< 0x00000200 */
+#define TIM_SR_CC1OF TIM_SR_CC1OF_Msk /*!<Capture/Compare 1 Overcapture Flag */
+#define TIM_SR_CC2OF_Pos (10U)
+#define TIM_SR_CC2OF_Msk (0x1U << TIM_SR_CC2OF_Pos) /*!< 0x00000400 */
+#define TIM_SR_CC2OF TIM_SR_CC2OF_Msk /*!<Capture/Compare 2 Overcapture Flag */
+#define TIM_SR_CC3OF_Pos (11U)
+#define TIM_SR_CC3OF_Msk (0x1U << TIM_SR_CC3OF_Pos) /*!< 0x00000800 */
+#define TIM_SR_CC3OF TIM_SR_CC3OF_Msk /*!<Capture/Compare 3 Overcapture Flag */
+#define TIM_SR_CC4OF_Pos (12U)
+#define TIM_SR_CC4OF_Msk (0x1U << TIM_SR_CC4OF_Pos) /*!< 0x00001000 */
+#define TIM_SR_CC4OF TIM_SR_CC4OF_Msk /*!<Capture/Compare 4 Overcapture Flag */
+
+/******************* Bit definition for TIM_EGR register *******************/
+#define TIM_EGR_UG_Pos (0U)
+#define TIM_EGR_UG_Msk (0x1U << TIM_EGR_UG_Pos) /*!< 0x00000001 */
+#define TIM_EGR_UG TIM_EGR_UG_Msk /*!<Update Generation */
+#define TIM_EGR_CC1G_Pos (1U)
+#define TIM_EGR_CC1G_Msk (0x1U << TIM_EGR_CC1G_Pos) /*!< 0x00000002 */
+#define TIM_EGR_CC1G TIM_EGR_CC1G_Msk /*!<Capture/Compare 1 Generation */
+#define TIM_EGR_CC2G_Pos (2U)
+#define TIM_EGR_CC2G_Msk (0x1U << TIM_EGR_CC2G_Pos) /*!< 0x00000004 */
+#define TIM_EGR_CC2G TIM_EGR_CC2G_Msk /*!<Capture/Compare 2 Generation */
+#define TIM_EGR_CC3G_Pos (3U)
+#define TIM_EGR_CC3G_Msk (0x1U << TIM_EGR_CC3G_Pos) /*!< 0x00000008 */
+#define TIM_EGR_CC3G TIM_EGR_CC3G_Msk /*!<Capture/Compare 3 Generation */
+#define TIM_EGR_CC4G_Pos (4U)
+#define TIM_EGR_CC4G_Msk (0x1U << TIM_EGR_CC4G_Pos) /*!< 0x00000010 */
+#define TIM_EGR_CC4G TIM_EGR_CC4G_Msk /*!<Capture/Compare 4 Generation */
+#define TIM_EGR_COMG_Pos (5U)
+#define TIM_EGR_COMG_Msk (0x1U << TIM_EGR_COMG_Pos) /*!< 0x00000020 */
+#define TIM_EGR_COMG TIM_EGR_COMG_Msk /*!<Capture/Compare Control Update Generation */
+#define TIM_EGR_TG_Pos (6U)
+#define TIM_EGR_TG_Msk (0x1U << TIM_EGR_TG_Pos) /*!< 0x00000040 */
+#define TIM_EGR_TG TIM_EGR_TG_Msk /*!<Trigger Generation */
+#define TIM_EGR_BG_Pos (7U)
+#define TIM_EGR_BG_Msk (0x1U << TIM_EGR_BG_Pos) /*!< 0x00000080 */
+#define TIM_EGR_BG TIM_EGR_BG_Msk /*!<Break Generation */
+
+/****************** Bit definition for TIM_CCMR1 register ******************/
+#define TIM_CCMR1_CC1S_Pos (0U)
+#define TIM_CCMR1_CC1S_Msk (0x3U << TIM_CCMR1_CC1S_Pos) /*!< 0x00000003 */
+#define TIM_CCMR1_CC1S TIM_CCMR1_CC1S_Msk /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
+#define TIM_CCMR1_CC1S_0 (0x1U << TIM_CCMR1_CC1S_Pos) /*!< 0x00000001 */
+#define TIM_CCMR1_CC1S_1 (0x2U << TIM_CCMR1_CC1S_Pos) /*!< 0x00000002 */
+
+#define TIM_CCMR1_OC1FE_Pos (2U)
+#define TIM_CCMR1_OC1FE_Msk (0x1U << TIM_CCMR1_OC1FE_Pos) /*!< 0x00000004 */
+#define TIM_CCMR1_OC1FE TIM_CCMR1_OC1FE_Msk /*!<Output Compare 1 Fast enable */
+#define TIM_CCMR1_OC1PE_Pos (3U)
+#define TIM_CCMR1_OC1PE_Msk (0x1U << TIM_CCMR1_OC1PE_Pos) /*!< 0x00000008 */
+#define TIM_CCMR1_OC1PE TIM_CCMR1_OC1PE_Msk /*!<Output Compare 1 Preload enable */
+
+#define TIM_CCMR1_OC1M_Pos (4U)
+#define TIM_CCMR1_OC1M_Msk (0x7U << TIM_CCMR1_OC1M_Pos) /*!< 0x00000070 */
+#define TIM_CCMR1_OC1M TIM_CCMR1_OC1M_Msk /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
+#define TIM_CCMR1_OC1M_0 (0x1U << TIM_CCMR1_OC1M_Pos) /*!< 0x00000010 */
+#define TIM_CCMR1_OC1M_1 (0x2U << TIM_CCMR1_OC1M_Pos) /*!< 0x00000020 */
+#define TIM_CCMR1_OC1M_2 (0x4U << TIM_CCMR1_OC1M_Pos) /*!< 0x00000040 */
+
+#define TIM_CCMR1_OC1CE_Pos (7U)
+#define TIM_CCMR1_OC1CE_Msk (0x1U << TIM_CCMR1_OC1CE_Pos) /*!< 0x00000080 */
+#define TIM_CCMR1_OC1CE TIM_CCMR1_OC1CE_Msk /*!<Output Compare 1Clear Enable */
+
+#define TIM_CCMR1_CC2S_Pos (8U)
+#define TIM_CCMR1_CC2S_Msk (0x3U << TIM_CCMR1_CC2S_Pos) /*!< 0x00000300 */
+#define TIM_CCMR1_CC2S TIM_CCMR1_CC2S_Msk /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
+#define TIM_CCMR1_CC2S_0 (0x1U << TIM_CCMR1_CC2S_Pos) /*!< 0x00000100 */
+#define TIM_CCMR1_CC2S_1 (0x2U << TIM_CCMR1_CC2S_Pos) /*!< 0x00000200 */
+
+#define TIM_CCMR1_OC2FE_Pos (10U)
+#define TIM_CCMR1_OC2FE_Msk (0x1U << TIM_CCMR1_OC2FE_Pos) /*!< 0x00000400 */
+#define TIM_CCMR1_OC2FE TIM_CCMR1_OC2FE_Msk /*!<Output Compare 2 Fast enable */
+#define TIM_CCMR1_OC2PE_Pos (11U)
+#define TIM_CCMR1_OC2PE_Msk (0x1U << TIM_CCMR1_OC2PE_Pos) /*!< 0x00000800 */
+#define TIM_CCMR1_OC2PE TIM_CCMR1_OC2PE_Msk /*!<Output Compare 2 Preload enable */
+
+#define TIM_CCMR1_OC2M_Pos (12U)
+#define TIM_CCMR1_OC2M_Msk (0x7U << TIM_CCMR1_OC2M_Pos) /*!< 0x00007000 */
+#define TIM_CCMR1_OC2M TIM_CCMR1_OC2M_Msk /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
+#define TIM_CCMR1_OC2M_0 (0x1U << TIM_CCMR1_OC2M_Pos) /*!< 0x00001000 */
+#define TIM_CCMR1_OC2M_1 (0x2U << TIM_CCMR1_OC2M_Pos) /*!< 0x00002000 */
+#define TIM_CCMR1_OC2M_2 (0x4U << TIM_CCMR1_OC2M_Pos) /*!< 0x00004000 */
+
+#define TIM_CCMR1_OC2CE_Pos (15U)
+#define TIM_CCMR1_OC2CE_Msk (0x1U << TIM_CCMR1_OC2CE_Pos) /*!< 0x00008000 */
+#define TIM_CCMR1_OC2CE TIM_CCMR1_OC2CE_Msk /*!<Output Compare 2 Clear Enable */
+
+/*---------------------------------------------------------------------------*/
+
+#define TIM_CCMR1_IC1PSC_Pos (2U)
+#define TIM_CCMR1_IC1PSC_Msk (0x3U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x0000000C */
+#define TIM_CCMR1_IC1PSC TIM_CCMR1_IC1PSC_Msk /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
+#define TIM_CCMR1_IC1PSC_0 (0x1U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x00000004 */
+#define TIM_CCMR1_IC1PSC_1 (0x2U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x00000008 */
+
+#define TIM_CCMR1_IC1F_Pos (4U)
+#define TIM_CCMR1_IC1F_Msk (0xFU << TIM_CCMR1_IC1F_Pos) /*!< 0x000000F0 */
+#define TIM_CCMR1_IC1F TIM_CCMR1_IC1F_Msk /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
+#define TIM_CCMR1_IC1F_0 (0x1U << TIM_CCMR1_IC1F_Pos) /*!< 0x00000010 */
+#define TIM_CCMR1_IC1F_1 (0x2U << TIM_CCMR1_IC1F_Pos) /*!< 0x00000020 */
+#define TIM_CCMR1_IC1F_2 (0x4U << TIM_CCMR1_IC1F_Pos) /*!< 0x00000040 */
+#define TIM_CCMR1_IC1F_3 (0x8U << TIM_CCMR1_IC1F_Pos) /*!< 0x00000080 */
+
+#define TIM_CCMR1_IC2PSC_Pos (10U)
+#define TIM_CCMR1_IC2PSC_Msk (0x3U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000C00 */
+#define TIM_CCMR1_IC2PSC TIM_CCMR1_IC2PSC_Msk /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
+#define TIM_CCMR1_IC2PSC_0 (0x1U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000400 */
+#define TIM_CCMR1_IC2PSC_1 (0x2U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000800 */
+
+#define TIM_CCMR1_IC2F_Pos (12U)
+#define TIM_CCMR1_IC2F_Msk (0xFU << TIM_CCMR1_IC2F_Pos) /*!< 0x0000F000 */
+#define TIM_CCMR1_IC2F TIM_CCMR1_IC2F_Msk /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
+#define TIM_CCMR1_IC2F_0 (0x1U << TIM_CCMR1_IC2F_Pos) /*!< 0x00001000 */
+#define TIM_CCMR1_IC2F_1 (0x2U << TIM_CCMR1_IC2F_Pos) /*!< 0x00002000 */
+#define TIM_CCMR1_IC2F_2 (0x4U << TIM_CCMR1_IC2F_Pos) /*!< 0x00004000 */
+#define TIM_CCMR1_IC2F_3 (0x8U << TIM_CCMR1_IC2F_Pos) /*!< 0x00008000 */
+
+/****************** Bit definition for TIM_CCMR2 register ******************/
+#define TIM_CCMR2_CC3S_Pos (0U)
+#define TIM_CCMR2_CC3S_Msk (0x3U << TIM_CCMR2_CC3S_Pos) /*!< 0x00000003 */
+#define TIM_CCMR2_CC3S TIM_CCMR2_CC3S_Msk /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
+#define TIM_CCMR2_CC3S_0 (0x1U << TIM_CCMR2_CC3S_Pos) /*!< 0x00000001 */
+#define TIM_CCMR2_CC3S_1 (0x2U << TIM_CCMR2_CC3S_Pos) /*!< 0x00000002 */
+
+#define TIM_CCMR2_OC3FE_Pos (2U)
+#define TIM_CCMR2_OC3FE_Msk (0x1U << TIM_CCMR2_OC3FE_Pos) /*!< 0x00000004 */
+#define TIM_CCMR2_OC3FE TIM_CCMR2_OC3FE_Msk /*!<Output Compare 3 Fast enable */
+#define TIM_CCMR2_OC3PE_Pos (3U)
+#define TIM_CCMR2_OC3PE_Msk (0x1U << TIM_CCMR2_OC3PE_Pos) /*!< 0x00000008 */
+#define TIM_CCMR2_OC3PE TIM_CCMR2_OC3PE_Msk /*!<Output Compare 3 Preload enable */
+
+#define TIM_CCMR2_OC3M_Pos (4U)
+#define TIM_CCMR2_OC3M_Msk (0x7U << TIM_CCMR2_OC3M_Pos) /*!< 0x00000070 */
+#define TIM_CCMR2_OC3M TIM_CCMR2_OC3M_Msk /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
+#define TIM_CCMR2_OC3M_0 (0x1U << TIM_CCMR2_OC3M_Pos) /*!< 0x00000010 */
+#define TIM_CCMR2_OC3M_1 (0x2U << TIM_CCMR2_OC3M_Pos) /*!< 0x00000020 */
+#define TIM_CCMR2_OC3M_2 (0x4U << TIM_CCMR2_OC3M_Pos) /*!< 0x00000040 */
+
+#define TIM_CCMR2_OC3CE_Pos (7U)
+#define TIM_CCMR2_OC3CE_Msk (0x1U << TIM_CCMR2_OC3CE_Pos) /*!< 0x00000080 */
+#define TIM_CCMR2_OC3CE TIM_CCMR2_OC3CE_Msk /*!<Output Compare 3 Clear Enable */
+
+#define TIM_CCMR2_CC4S_Pos (8U)
+#define TIM_CCMR2_CC4S_Msk (0x3U << TIM_CCMR2_CC4S_Pos) /*!< 0x00000300 */
+#define TIM_CCMR2_CC4S TIM_CCMR2_CC4S_Msk /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
+#define TIM_CCMR2_CC4S_0 (0x1U << TIM_CCMR2_CC4S_Pos) /*!< 0x00000100 */
+#define TIM_CCMR2_CC4S_1 (0x2U << TIM_CCMR2_CC4S_Pos) /*!< 0x00000200 */
+
+#define TIM_CCMR2_OC4FE_Pos (10U)
+#define TIM_CCMR2_OC4FE_Msk (0x1U << TIM_CCMR2_OC4FE_Pos) /*!< 0x00000400 */
+#define TIM_CCMR2_OC4FE TIM_CCMR2_OC4FE_Msk /*!<Output Compare 4 Fast enable */
+#define TIM_CCMR2_OC4PE_Pos (11U)
+#define TIM_CCMR2_OC4PE_Msk (0x1U << TIM_CCMR2_OC4PE_Pos) /*!< 0x00000800 */
+#define TIM_CCMR2_OC4PE TIM_CCMR2_OC4PE_Msk /*!<Output Compare 4 Preload enable */
+
+#define TIM_CCMR2_OC4M_Pos (12U)
+#define TIM_CCMR2_OC4M_Msk (0x7U << TIM_CCMR2_OC4M_Pos) /*!< 0x00007000 */
+#define TIM_CCMR2_OC4M TIM_CCMR2_OC4M_Msk /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
+#define TIM_CCMR2_OC4M_0 (0x1U << TIM_CCMR2_OC4M_Pos) /*!< 0x00001000 */
+#define TIM_CCMR2_OC4M_1 (0x2U << TIM_CCMR2_OC4M_Pos) /*!< 0x00002000 */
+#define TIM_CCMR2_OC4M_2 (0x4U << TIM_CCMR2_OC4M_Pos) /*!< 0x00004000 */
+
+#define TIM_CCMR2_OC4CE_Pos (15U)
+#define TIM_CCMR2_OC4CE_Msk (0x1U << TIM_CCMR2_OC4CE_Pos) /*!< 0x00008000 */
+#define TIM_CCMR2_OC4CE TIM_CCMR2_OC4CE_Msk /*!<Output Compare 4 Clear Enable */
+
+/*---------------------------------------------------------------------------*/
+
+#define TIM_CCMR2_IC3PSC_Pos (2U)
+#define TIM_CCMR2_IC3PSC_Msk (0x3U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x0000000C */
+#define TIM_CCMR2_IC3PSC TIM_CCMR2_IC3PSC_Msk /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
+#define TIM_CCMR2_IC3PSC_0 (0x1U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x00000004 */
+#define TIM_CCMR2_IC3PSC_1 (0x2U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x00000008 */
+
+#define TIM_CCMR2_IC3F_Pos (4U)
+#define TIM_CCMR2_IC3F_Msk (0xFU << TIM_CCMR2_IC3F_Pos) /*!< 0x000000F0 */
+#define TIM_CCMR2_IC3F TIM_CCMR2_IC3F_Msk /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
+#define TIM_CCMR2_IC3F_0 (0x1U << TIM_CCMR2_IC3F_Pos) /*!< 0x00000010 */
+#define TIM_CCMR2_IC3F_1 (0x2U << TIM_CCMR2_IC3F_Pos) /*!< 0x00000020 */
+#define TIM_CCMR2_IC3F_2 (0x4U << TIM_CCMR2_IC3F_Pos) /*!< 0x00000040 */
+#define TIM_CCMR2_IC3F_3 (0x8U << TIM_CCMR2_IC3F_Pos) /*!< 0x00000080 */
+
+#define TIM_CCMR2_IC4PSC_Pos (10U)
+#define TIM_CCMR2_IC4PSC_Msk (0x3U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000C00 */
+#define TIM_CCMR2_IC4PSC TIM_CCMR2_IC4PSC_Msk /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
+#define TIM_CCMR2_IC4PSC_0 (0x1U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000400 */
+#define TIM_CCMR2_IC4PSC_1 (0x2U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000800 */
+
+#define TIM_CCMR2_IC4F_Pos (12U)
+#define TIM_CCMR2_IC4F_Msk (0xFU << TIM_CCMR2_IC4F_Pos) /*!< 0x0000F000 */
+#define TIM_CCMR2_IC4F TIM_CCMR2_IC4F_Msk /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
+#define TIM_CCMR2_IC4F_0 (0x1U << TIM_CCMR2_IC4F_Pos) /*!< 0x00001000 */
+#define TIM_CCMR2_IC4F_1 (0x2U << TIM_CCMR2_IC4F_Pos) /*!< 0x00002000 */
+#define TIM_CCMR2_IC4F_2 (0x4U << TIM_CCMR2_IC4F_Pos) /*!< 0x00004000 */
+#define TIM_CCMR2_IC4F_3 (0x8U << TIM_CCMR2_IC4F_Pos) /*!< 0x00008000 */
+
+/******************* Bit definition for TIM_CCER register ******************/
+#define TIM_CCER_CC1E_Pos (0U)
+#define TIM_CCER_CC1E_Msk (0x1U << TIM_CCER_CC1E_Pos) /*!< 0x00000001 */
+#define TIM_CCER_CC1E TIM_CCER_CC1E_Msk /*!<Capture/Compare 1 output enable */
+#define TIM_CCER_CC1P_Pos (1U)
+#define TIM_CCER_CC1P_Msk (0x1U << TIM_CCER_CC1P_Pos) /*!< 0x00000002 */
+#define TIM_CCER_CC1P TIM_CCER_CC1P_Msk /*!<Capture/Compare 1 output Polarity */
+#define TIM_CCER_CC1NE_Pos (2U)
+#define TIM_CCER_CC1NE_Msk (0x1U << TIM_CCER_CC1NE_Pos) /*!< 0x00000004 */
+#define TIM_CCER_CC1NE TIM_CCER_CC1NE_Msk /*!<Capture/Compare 1 Complementary output enable */
+#define TIM_CCER_CC1NP_Pos (3U)
+#define TIM_CCER_CC1NP_Msk (0x1U << TIM_CCER_CC1NP_Pos) /*!< 0x00000008 */
+#define TIM_CCER_CC1NP TIM_CCER_CC1NP_Msk /*!<Capture/Compare 1 Complementary output Polarity */
+#define TIM_CCER_CC2E_Pos (4U)
+#define TIM_CCER_CC2E_Msk (0x1U << TIM_CCER_CC2E_Pos) /*!< 0x00000010 */
+#define TIM_CCER_CC2E TIM_CCER_CC2E_Msk /*!<Capture/Compare 2 output enable */
+#define TIM_CCER_CC2P_Pos (5U)
+#define TIM_CCER_CC2P_Msk (0x1U << TIM_CCER_CC2P_Pos) /*!< 0x00000020 */
+#define TIM_CCER_CC2P TIM_CCER_CC2P_Msk /*!<Capture/Compare 2 output Polarity */
+#define TIM_CCER_CC2NE_Pos (6U)
+#define TIM_CCER_CC2NE_Msk (0x1U << TIM_CCER_CC2NE_Pos) /*!< 0x00000040 */
+#define TIM_CCER_CC2NE TIM_CCER_CC2NE_Msk /*!<Capture/Compare 2 Complementary output enable */
+#define TIM_CCER_CC2NP_Pos (7U)
+#define TIM_CCER_CC2NP_Msk (0x1U << TIM_CCER_CC2NP_Pos) /*!< 0x00000080 */
+#define TIM_CCER_CC2NP TIM_CCER_CC2NP_Msk /*!<Capture/Compare 2 Complementary output Polarity */
+#define TIM_CCER_CC3E_Pos (8U)
+#define TIM_CCER_CC3E_Msk (0x1U << TIM_CCER_CC3E_Pos) /*!< 0x00000100 */
+#define TIM_CCER_CC3E TIM_CCER_CC3E_Msk /*!<Capture/Compare 3 output enable */
+#define TIM_CCER_CC3P_Pos (9U)
+#define TIM_CCER_CC3P_Msk (0x1U << TIM_CCER_CC3P_Pos) /*!< 0x00000200 */
+#define TIM_CCER_CC3P TIM_CCER_CC3P_Msk /*!<Capture/Compare 3 output Polarity */
+#define TIM_CCER_CC3NE_Pos (10U)
+#define TIM_CCER_CC3NE_Msk (0x1U << TIM_CCER_CC3NE_Pos) /*!< 0x00000400 */
+#define TIM_CCER_CC3NE TIM_CCER_CC3NE_Msk /*!<Capture/Compare 3 Complementary output enable */
+#define TIM_CCER_CC3NP_Pos (11U)
+#define TIM_CCER_CC3NP_Msk (0x1U << TIM_CCER_CC3NP_Pos) /*!< 0x00000800 */
+#define TIM_CCER_CC3NP TIM_CCER_CC3NP_Msk /*!<Capture/Compare 3 Complementary output Polarity */
+#define TIM_CCER_CC4E_Pos (12U)
+#define TIM_CCER_CC4E_Msk (0x1U << TIM_CCER_CC4E_Pos) /*!< 0x00001000 */
+#define TIM_CCER_CC4E TIM_CCER_CC4E_Msk /*!<Capture/Compare 4 output enable */
+#define TIM_CCER_CC4P_Pos (13U)
+#define TIM_CCER_CC4P_Msk (0x1U << TIM_CCER_CC4P_Pos) /*!< 0x00002000 */
+#define TIM_CCER_CC4P TIM_CCER_CC4P_Msk /*!<Capture/Compare 4 output Polarity */
+#define TIM_CCER_CC4NP_Pos (15U)
+#define TIM_CCER_CC4NP_Msk (0x1U << TIM_CCER_CC4NP_Pos) /*!< 0x00008000 */
+#define TIM_CCER_CC4NP TIM_CCER_CC4NP_Msk /*!<Capture/Compare 4 Complementary output Polarity */
+
+/******************* Bit definition for TIM_CNT register *******************/
+#define TIM_CNT_CNT_Pos (0U)
+#define TIM_CNT_CNT_Msk (0xFFFFFFFFU << TIM_CNT_CNT_Pos) /*!< 0xFFFFFFFF */
+#define TIM_CNT_CNT TIM_CNT_CNT_Msk /*!<Counter Value */
+
+/******************* Bit definition for TIM_PSC register *******************/
+#define TIM_PSC_PSC_Pos (0U)
+#define TIM_PSC_PSC_Msk (0xFFFFU << TIM_PSC_PSC_Pos) /*!< 0x0000FFFF */
+#define TIM_PSC_PSC TIM_PSC_PSC_Msk /*!<Prescaler Value */
+
+/******************* Bit definition for TIM_ARR register *******************/
+#define TIM_ARR_ARR_Pos (0U)
+#define TIM_ARR_ARR_Msk (0xFFFFFFFFU << TIM_ARR_ARR_Pos) /*!< 0xFFFFFFFF */
+#define TIM_ARR_ARR TIM_ARR_ARR_Msk /*!<actual auto-reload Value */
+
+/******************* Bit definition for TIM_RCR register *******************/
+#define TIM_RCR_REP_Pos (0U)
+#define TIM_RCR_REP_Msk (0xFFU << TIM_RCR_REP_Pos) /*!< 0x000000FF */
+#define TIM_RCR_REP TIM_RCR_REP_Msk /*!<Repetition Counter Value */
+
+/******************* Bit definition for TIM_CCR1 register ******************/
+#define TIM_CCR1_CCR1_Pos (0U)
+#define TIM_CCR1_CCR1_Msk (0xFFFFU << TIM_CCR1_CCR1_Pos) /*!< 0x0000FFFF */
+#define TIM_CCR1_CCR1 TIM_CCR1_CCR1_Msk /*!<Capture/Compare 1 Value */
+
+/******************* Bit definition for TIM_CCR2 register ******************/
+#define TIM_CCR2_CCR2_Pos (0U)
+#define TIM_CCR2_CCR2_Msk (0xFFFFU << TIM_CCR2_CCR2_Pos) /*!< 0x0000FFFF */
+#define TIM_CCR2_CCR2 TIM_CCR2_CCR2_Msk /*!<Capture/Compare 2 Value */
+
+/******************* Bit definition for TIM_CCR3 register ******************/
+#define TIM_CCR3_CCR3_Pos (0U)
+#define TIM_CCR3_CCR3_Msk (0xFFFFU << TIM_CCR3_CCR3_Pos) /*!< 0x0000FFFF */
+#define TIM_CCR3_CCR3 TIM_CCR3_CCR3_Msk /*!<Capture/Compare 3 Value */
+
+/******************* Bit definition for TIM_CCR4 register ******************/
+#define TIM_CCR4_CCR4_Pos (0U)
+#define TIM_CCR4_CCR4_Msk (0xFFFFU << TIM_CCR4_CCR4_Pos) /*!< 0x0000FFFF */
+#define TIM_CCR4_CCR4 TIM_CCR4_CCR4_Msk /*!<Capture/Compare 4 Value */
+
+/******************* Bit definition for TIM_BDTR register ******************/
+#define TIM_BDTR_DTG_Pos (0U)
+#define TIM_BDTR_DTG_Msk (0xFFU << TIM_BDTR_DTG_Pos) /*!< 0x000000FF */
+#define TIM_BDTR_DTG TIM_BDTR_DTG_Msk /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
+#define TIM_BDTR_DTG_0 (0x01U << TIM_BDTR_DTG_Pos) /*!< 0x00000001 */
+#define TIM_BDTR_DTG_1 (0x02U << TIM_BDTR_DTG_Pos) /*!< 0x00000002 */
+#define TIM_BDTR_DTG_2 (0x04U << TIM_BDTR_DTG_Pos) /*!< 0x00000004 */
+#define TIM_BDTR_DTG_3 (0x08U << TIM_BDTR_DTG_Pos) /*!< 0x00000008 */
+#define TIM_BDTR_DTG_4 (0x10U << TIM_BDTR_DTG_Pos) /*!< 0x00000010 */
+#define TIM_BDTR_DTG_5 (0x20U << TIM_BDTR_DTG_Pos) /*!< 0x00000020 */
+#define TIM_BDTR_DTG_6 (0x40U << TIM_BDTR_DTG_Pos) /*!< 0x00000040 */
+#define TIM_BDTR_DTG_7 (0x80U << TIM_BDTR_DTG_Pos) /*!< 0x00000080 */
+
+#define TIM_BDTR_LOCK_Pos (8U)
+#define TIM_BDTR_LOCK_Msk (0x3U << TIM_BDTR_LOCK_Pos) /*!< 0x00000300 */
+#define TIM_BDTR_LOCK TIM_BDTR_LOCK_Msk /*!<LOCK[1:0] bits (Lock Configuration) */
+#define TIM_BDTR_LOCK_0 (0x1U << TIM_BDTR_LOCK_Pos) /*!< 0x00000100 */
+#define TIM_BDTR_LOCK_1 (0x2U << TIM_BDTR_LOCK_Pos) /*!< 0x00000200 */
+
+#define TIM_BDTR_OSSI_Pos (10U)
+#define TIM_BDTR_OSSI_Msk (0x1U << TIM_BDTR_OSSI_Pos) /*!< 0x00000400 */
+#define TIM_BDTR_OSSI TIM_BDTR_OSSI_Msk /*!<Off-State Selection for Idle mode */
+#define TIM_BDTR_OSSR_Pos (11U)
+#define TIM_BDTR_OSSR_Msk (0x1U << TIM_BDTR_OSSR_Pos) /*!< 0x00000800 */
+#define TIM_BDTR_OSSR TIM_BDTR_OSSR_Msk /*!<Off-State Selection for Run mode */
+#define TIM_BDTR_BKE_Pos (12U)
+#define TIM_BDTR_BKE_Msk (0x1U << TIM_BDTR_BKE_Pos) /*!< 0x00001000 */
+#define TIM_BDTR_BKE TIM_BDTR_BKE_Msk /*!<Break enable */
+#define TIM_BDTR_BKP_Pos (13U)
+#define TIM_BDTR_BKP_Msk (0x1U << TIM_BDTR_BKP_Pos) /*!< 0x00002000 */
+#define TIM_BDTR_BKP TIM_BDTR_BKP_Msk /*!<Break Polarity */
+#define TIM_BDTR_AOE_Pos (14U)
+#define TIM_BDTR_AOE_Msk (0x1U << TIM_BDTR_AOE_Pos) /*!< 0x00004000 */
+#define TIM_BDTR_AOE TIM_BDTR_AOE_Msk /*!<Automatic Output enable */
+#define TIM_BDTR_MOE_Pos (15U)
+#define TIM_BDTR_MOE_Msk (0x1U << TIM_BDTR_MOE_Pos) /*!< 0x00008000 */
+#define TIM_BDTR_MOE TIM_BDTR_MOE_Msk /*!<Main Output enable */
+
+/******************* Bit definition for TIM_DCR register *******************/
+#define TIM_DCR_DBA_Pos (0U)
+#define TIM_DCR_DBA_Msk (0x1FU << TIM_DCR_DBA_Pos) /*!< 0x0000001F */
+#define TIM_DCR_DBA TIM_DCR_DBA_Msk /*!<DBA[4:0] bits (DMA Base Address) */
+#define TIM_DCR_DBA_0 (0x01U << TIM_DCR_DBA_Pos) /*!< 0x00000001 */
+#define TIM_DCR_DBA_1 (0x02U << TIM_DCR_DBA_Pos) /*!< 0x00000002 */
+#define TIM_DCR_DBA_2 (0x04U << TIM_DCR_DBA_Pos) /*!< 0x00000004 */
+#define TIM_DCR_DBA_3 (0x08U << TIM_DCR_DBA_Pos) /*!< 0x00000008 */
+#define TIM_DCR_DBA_4 (0x10U << TIM_DCR_DBA_Pos) /*!< 0x00000010 */
+
+#define TIM_DCR_DBL_Pos (8U)
+#define TIM_DCR_DBL_Msk (0x1FU << TIM_DCR_DBL_Pos) /*!< 0x00001F00 */
+#define TIM_DCR_DBL TIM_DCR_DBL_Msk /*!<DBL[4:0] bits (DMA Burst Length) */
+#define TIM_DCR_DBL_0 (0x01U << TIM_DCR_DBL_Pos) /*!< 0x00000100 */
+#define TIM_DCR_DBL_1 (0x02U << TIM_DCR_DBL_Pos) /*!< 0x00000200 */
+#define TIM_DCR_DBL_2 (0x04U << TIM_DCR_DBL_Pos) /*!< 0x00000400 */
+#define TIM_DCR_DBL_3 (0x08U << TIM_DCR_DBL_Pos) /*!< 0x00000800 */
+#define TIM_DCR_DBL_4 (0x10U << TIM_DCR_DBL_Pos) /*!< 0x00001000 */
+
+/******************* Bit definition for TIM_DMAR register ******************/
+#define TIM_DMAR_DMAB_Pos (0U)
+#define TIM_DMAR_DMAB_Msk (0xFFFFU << TIM_DMAR_DMAB_Pos) /*!< 0x0000FFFF */
+#define TIM_DMAR_DMAB TIM_DMAR_DMAB_Msk /*!<DMA register for burst accesses */
+
+/******************* Bit definition for TIM_OR register ********************/
+
+/******************************************************************************/
+/* */
+/* Real-Time Clock */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for RTC_CRH register ********************/
+#define RTC_CRH_SECIE_Pos (0U)
+#define RTC_CRH_SECIE_Msk (0x1U << RTC_CRH_SECIE_Pos) /*!< 0x00000001 */
+#define RTC_CRH_SECIE RTC_CRH_SECIE_Msk /*!< Second Interrupt Enable */
+#define RTC_CRH_ALRIE_Pos (1U)
+#define RTC_CRH_ALRIE_Msk (0x1U << RTC_CRH_ALRIE_Pos) /*!< 0x00000002 */
+#define RTC_CRH_ALRIE RTC_CRH_ALRIE_Msk /*!< Alarm Interrupt Enable */
+#define RTC_CRH_OWIE_Pos (2U)
+#define RTC_CRH_OWIE_Msk (0x1U << RTC_CRH_OWIE_Pos) /*!< 0x00000004 */
+#define RTC_CRH_OWIE RTC_CRH_OWIE_Msk /*!< OverfloW Interrupt Enable */
+
+/******************* Bit definition for RTC_CRL register ********************/
+#define RTC_CRL_SECF_Pos (0U)
+#define RTC_CRL_SECF_Msk (0x1U << RTC_CRL_SECF_Pos) /*!< 0x00000001 */
+#define RTC_CRL_SECF RTC_CRL_SECF_Msk /*!< Second Flag */
+#define RTC_CRL_ALRF_Pos (1U)
+#define RTC_CRL_ALRF_Msk (0x1U << RTC_CRL_ALRF_Pos) /*!< 0x00000002 */
+#define RTC_CRL_ALRF RTC_CRL_ALRF_Msk /*!< Alarm Flag */
+#define RTC_CRL_OWF_Pos (2U)
+#define RTC_CRL_OWF_Msk (0x1U << RTC_CRL_OWF_Pos) /*!< 0x00000004 */
+#define RTC_CRL_OWF RTC_CRL_OWF_Msk /*!< OverfloW Flag */
+#define RTC_CRL_RSF_Pos (3U)
+#define RTC_CRL_RSF_Msk (0x1U << RTC_CRL_RSF_Pos) /*!< 0x00000008 */
+#define RTC_CRL_RSF RTC_CRL_RSF_Msk /*!< Registers Synchronized Flag */
+#define RTC_CRL_CNF_Pos (4U)
+#define RTC_CRL_CNF_Msk (0x1U << RTC_CRL_CNF_Pos) /*!< 0x00000010 */
+#define RTC_CRL_CNF RTC_CRL_CNF_Msk /*!< Configuration Flag */
+#define RTC_CRL_RTOFF_Pos (5U)
+#define RTC_CRL_RTOFF_Msk (0x1U << RTC_CRL_RTOFF_Pos) /*!< 0x00000020 */
+#define RTC_CRL_RTOFF RTC_CRL_RTOFF_Msk /*!< RTC operation OFF */
+
+/******************* Bit definition for RTC_PRLH register *******************/
+#define RTC_PRLH_PRL_Pos (0U)
+#define RTC_PRLH_PRL_Msk (0xFU << RTC_PRLH_PRL_Pos) /*!< 0x0000000F */
+#define RTC_PRLH_PRL RTC_PRLH_PRL_Msk /*!< RTC Prescaler Reload Value High */
+
+/******************* Bit definition for RTC_PRLL register *******************/
+#define RTC_PRLL_PRL_Pos (0U)
+#define RTC_PRLL_PRL_Msk (0xFFFFU << RTC_PRLL_PRL_Pos) /*!< 0x0000FFFF */
+#define RTC_PRLL_PRL RTC_PRLL_PRL_Msk /*!< RTC Prescaler Reload Value Low */
+
+/******************* Bit definition for RTC_DIVH register *******************/
+#define RTC_DIVH_RTC_DIV_Pos (0U)
+#define RTC_DIVH_RTC_DIV_Msk (0xFU << RTC_DIVH_RTC_DIV_Pos) /*!< 0x0000000F */
+#define RTC_DIVH_RTC_DIV RTC_DIVH_RTC_DIV_Msk /*!< RTC Clock Divider High */
+
+/******************* Bit definition for RTC_DIVL register *******************/
+#define RTC_DIVL_RTC_DIV_Pos (0U)
+#define RTC_DIVL_RTC_DIV_Msk (0xFFFFU << RTC_DIVL_RTC_DIV_Pos) /*!< 0x0000FFFF */
+#define RTC_DIVL_RTC_DIV RTC_DIVL_RTC_DIV_Msk /*!< RTC Clock Divider Low */
+
+/******************* Bit definition for RTC_CNTH register *******************/
+#define RTC_CNTH_RTC_CNT_Pos (0U)
+#define RTC_CNTH_RTC_CNT_Msk (0xFFFFU << RTC_CNTH_RTC_CNT_Pos) /*!< 0x0000FFFF */
+#define RTC_CNTH_RTC_CNT RTC_CNTH_RTC_CNT_Msk /*!< RTC Counter High */
+
+/******************* Bit definition for RTC_CNTL register *******************/
+#define RTC_CNTL_RTC_CNT_Pos (0U)
+#define RTC_CNTL_RTC_CNT_Msk (0xFFFFU << RTC_CNTL_RTC_CNT_Pos) /*!< 0x0000FFFF */
+#define RTC_CNTL_RTC_CNT RTC_CNTL_RTC_CNT_Msk /*!< RTC Counter Low */
+
+/******************* Bit definition for RTC_ALRH register *******************/
+#define RTC_ALRH_RTC_ALR_Pos (0U)
+#define RTC_ALRH_RTC_ALR_Msk (0xFFFFU << RTC_ALRH_RTC_ALR_Pos) /*!< 0x0000FFFF */
+#define RTC_ALRH_RTC_ALR RTC_ALRH_RTC_ALR_Msk /*!< RTC Alarm High */
+
+/******************* Bit definition for RTC_ALRL register *******************/
+#define RTC_ALRL_RTC_ALR_Pos (0U)
+#define RTC_ALRL_RTC_ALR_Msk (0xFFFFU << RTC_ALRL_RTC_ALR_Pos) /*!< 0x0000FFFF */
+#define RTC_ALRL_RTC_ALR RTC_ALRL_RTC_ALR_Msk /*!< RTC Alarm Low */
+
+/******************************************************************************/
+/* */
+/* Independent WATCHDOG (IWDG) */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for IWDG_KR register ********************/
+#define IWDG_KR_KEY_Pos (0U)
+#define IWDG_KR_KEY_Msk (0xFFFFU << IWDG_KR_KEY_Pos) /*!< 0x0000FFFF */
+#define IWDG_KR_KEY IWDG_KR_KEY_Msk /*!< Key value (write only, read 0000h) */
+
+/******************* Bit definition for IWDG_PR register ********************/
+#define IWDG_PR_PR_Pos (0U)
+#define IWDG_PR_PR_Msk (0x7U << IWDG_PR_PR_Pos) /*!< 0x00000007 */
+#define IWDG_PR_PR IWDG_PR_PR_Msk /*!< PR[2:0] (Prescaler divider) */
+#define IWDG_PR_PR_0 (0x1U << IWDG_PR_PR_Pos) /*!< 0x00000001 */
+#define IWDG_PR_PR_1 (0x2U << IWDG_PR_PR_Pos) /*!< 0x00000002 */
+#define IWDG_PR_PR_2 (0x4U << IWDG_PR_PR_Pos) /*!< 0x00000004 */
+
+/******************* Bit definition for IWDG_RLR register *******************/
+#define IWDG_RLR_RL_Pos (0U)
+#define IWDG_RLR_RL_Msk (0xFFFU << IWDG_RLR_RL_Pos) /*!< 0x00000FFF */
+#define IWDG_RLR_RL IWDG_RLR_RL_Msk /*!< Watchdog counter reload value */
+
+/******************* Bit definition for IWDG_SR register ********************/
+#define IWDG_SR_PVU_Pos (0U)
+#define IWDG_SR_PVU_Msk (0x1U << IWDG_SR_PVU_Pos) /*!< 0x00000001 */
+#define IWDG_SR_PVU IWDG_SR_PVU_Msk /*!< Watchdog prescaler value update */
+#define IWDG_SR_RVU_Pos (1U)
+#define IWDG_SR_RVU_Msk (0x1U << IWDG_SR_RVU_Pos) /*!< 0x00000002 */
+#define IWDG_SR_RVU IWDG_SR_RVU_Msk /*!< Watchdog counter reload value update */
+
+/******************************************************************************/
+/* */
+/* Window WATCHDOG (WWDG) */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for WWDG_CR register ********************/
+#define WWDG_CR_T_Pos (0U)
+#define WWDG_CR_T_Msk (0x7FU << WWDG_CR_T_Pos) /*!< 0x0000007F */
+#define WWDG_CR_T WWDG_CR_T_Msk /*!< T[6:0] bits (7-Bit counter (MSB to LSB)) */
+#define WWDG_CR_T_0 (0x01U << WWDG_CR_T_Pos) /*!< 0x00000001 */
+#define WWDG_CR_T_1 (0x02U << WWDG_CR_T_Pos) /*!< 0x00000002 */
+#define WWDG_CR_T_2 (0x04U << WWDG_CR_T_Pos) /*!< 0x00000004 */
+#define WWDG_CR_T_3 (0x08U << WWDG_CR_T_Pos) /*!< 0x00000008 */
+#define WWDG_CR_T_4 (0x10U << WWDG_CR_T_Pos) /*!< 0x00000010 */
+#define WWDG_CR_T_5 (0x20U << WWDG_CR_T_Pos) /*!< 0x00000020 */
+#define WWDG_CR_T_6 (0x40U << WWDG_CR_T_Pos) /*!< 0x00000040 */
+
+/* Legacy defines */
+#define WWDG_CR_T0 WWDG_CR_T_0
+#define WWDG_CR_T1 WWDG_CR_T_1
+#define WWDG_CR_T2 WWDG_CR_T_2
+#define WWDG_CR_T3 WWDG_CR_T_3
+#define WWDG_CR_T4 WWDG_CR_T_4
+#define WWDG_CR_T5 WWDG_CR_T_5
+#define WWDG_CR_T6 WWDG_CR_T_6
+
+#define WWDG_CR_WDGA_Pos (7U)
+#define WWDG_CR_WDGA_Msk (0x1U << WWDG_CR_WDGA_Pos) /*!< 0x00000080 */
+#define WWDG_CR_WDGA WWDG_CR_WDGA_Msk /*!< Activation bit */
+
+/******************* Bit definition for WWDG_CFR register *******************/
+#define WWDG_CFR_W_Pos (0U)
+#define WWDG_CFR_W_Msk (0x7FU << WWDG_CFR_W_Pos) /*!< 0x0000007F */
+#define WWDG_CFR_W WWDG_CFR_W_Msk /*!< W[6:0] bits (7-bit window value) */
+#define WWDG_CFR_W_0 (0x01U << WWDG_CFR_W_Pos) /*!< 0x00000001 */
+#define WWDG_CFR_W_1 (0x02U << WWDG_CFR_W_Pos) /*!< 0x00000002 */
+#define WWDG_CFR_W_2 (0x04U << WWDG_CFR_W_Pos) /*!< 0x00000004 */
+#define WWDG_CFR_W_3 (0x08U << WWDG_CFR_W_Pos) /*!< 0x00000008 */
+#define WWDG_CFR_W_4 (0x10U << WWDG_CFR_W_Pos) /*!< 0x00000010 */
+#define WWDG_CFR_W_5 (0x20U << WWDG_CFR_W_Pos) /*!< 0x00000020 */
+#define WWDG_CFR_W_6 (0x40U << WWDG_CFR_W_Pos) /*!< 0x00000040 */
+
+/* Legacy defines */
+#define WWDG_CFR_W0 WWDG_CFR_W_0
+#define WWDG_CFR_W1 WWDG_CFR_W_1
+#define WWDG_CFR_W2 WWDG_CFR_W_2
+#define WWDG_CFR_W3 WWDG_CFR_W_3
+#define WWDG_CFR_W4 WWDG_CFR_W_4
+#define WWDG_CFR_W5 WWDG_CFR_W_5
+#define WWDG_CFR_W6 WWDG_CFR_W_6
+
+#define WWDG_CFR_WDGTB_Pos (7U)
+#define WWDG_CFR_WDGTB_Msk (0x3U << WWDG_CFR_WDGTB_Pos) /*!< 0x00000180 */
+#define WWDG_CFR_WDGTB WWDG_CFR_WDGTB_Msk /*!< WDGTB[1:0] bits (Timer Base) */
+#define WWDG_CFR_WDGTB_0 (0x1U << WWDG_CFR_WDGTB_Pos) /*!< 0x00000080 */
+#define WWDG_CFR_WDGTB_1 (0x2U << WWDG_CFR_WDGTB_Pos) /*!< 0x00000100 */
+
+/* Legacy defines */
+#define WWDG_CFR_WDGTB0 WWDG_CFR_WDGTB_0
+#define WWDG_CFR_WDGTB1 WWDG_CFR_WDGTB_1
+
+#define WWDG_CFR_EWI_Pos (9U)
+#define WWDG_CFR_EWI_Msk (0x1U << WWDG_CFR_EWI_Pos) /*!< 0x00000200 */
+#define WWDG_CFR_EWI WWDG_CFR_EWI_Msk /*!< Early Wakeup Interrupt */
+
+/******************* Bit definition for WWDG_SR register ********************/
+#define WWDG_SR_EWIF_Pos (0U)
+#define WWDG_SR_EWIF_Msk (0x1U << WWDG_SR_EWIF_Pos) /*!< 0x00000001 */
+#define WWDG_SR_EWIF WWDG_SR_EWIF_Msk /*!< Early Wakeup Interrupt Flag */
+
+
+/******************************************************************************/
+/* */
+/* SD host Interface */
+/* */
+/******************************************************************************/
+
+/****************** Bit definition for SDIO_POWER register ******************/
+#define SDIO_POWER_PWRCTRL_Pos (0U)
+#define SDIO_POWER_PWRCTRL_Msk (0x3U << SDIO_POWER_PWRCTRL_Pos) /*!< 0x00000003 */
+#define SDIO_POWER_PWRCTRL SDIO_POWER_PWRCTRL_Msk /*!< PWRCTRL[1:0] bits (Power supply control bits) */
+#define SDIO_POWER_PWRCTRL_0 (0x1U << SDIO_POWER_PWRCTRL_Pos) /*!< 0x01 */
+#define SDIO_POWER_PWRCTRL_1 (0x2U << SDIO_POWER_PWRCTRL_Pos) /*!< 0x02 */
+
+/****************** Bit definition for SDIO_CLKCR register ******************/
+#define SDIO_CLKCR_CLKDIV_Pos (0U)
+#define SDIO_CLKCR_CLKDIV_Msk (0xFFU << SDIO_CLKCR_CLKDIV_Pos) /*!< 0x000000FF */
+#define SDIO_CLKCR_CLKDIV SDIO_CLKCR_CLKDIV_Msk /*!< Clock divide factor */
+#define SDIO_CLKCR_CLKEN_Pos (8U)
+#define SDIO_CLKCR_CLKEN_Msk (0x1U << SDIO_CLKCR_CLKEN_Pos) /*!< 0x00000100 */
+#define SDIO_CLKCR_CLKEN SDIO_CLKCR_CLKEN_Msk /*!< Clock enable bit */
+#define SDIO_CLKCR_PWRSAV_Pos (9U)
+#define SDIO_CLKCR_PWRSAV_Msk (0x1U << SDIO_CLKCR_PWRSAV_Pos) /*!< 0x00000200 */
+#define SDIO_CLKCR_PWRSAV SDIO_CLKCR_PWRSAV_Msk /*!< Power saving configuration bit */
+#define SDIO_CLKCR_BYPASS_Pos (10U)
+#define SDIO_CLKCR_BYPASS_Msk (0x1U << SDIO_CLKCR_BYPASS_Pos) /*!< 0x00000400 */
+#define SDIO_CLKCR_BYPASS SDIO_CLKCR_BYPASS_Msk /*!< Clock divider bypass enable bit */
+
+#define SDIO_CLKCR_WIDBUS_Pos (11U)
+#define SDIO_CLKCR_WIDBUS_Msk (0x3U << SDIO_CLKCR_WIDBUS_Pos) /*!< 0x00001800 */
+#define SDIO_CLKCR_WIDBUS SDIO_CLKCR_WIDBUS_Msk /*!< WIDBUS[1:0] bits (Wide bus mode enable bit) */
+#define SDIO_CLKCR_WIDBUS_0 (0x1U << SDIO_CLKCR_WIDBUS_Pos) /*!< 0x0800 */
+#define SDIO_CLKCR_WIDBUS_1 (0x2U << SDIO_CLKCR_WIDBUS_Pos) /*!< 0x1000 */
+
+#define SDIO_CLKCR_NEGEDGE_Pos (13U)
+#define SDIO_CLKCR_NEGEDGE_Msk (0x1U << SDIO_CLKCR_NEGEDGE_Pos) /*!< 0x00002000 */
+#define SDIO_CLKCR_NEGEDGE SDIO_CLKCR_NEGEDGE_Msk /*!< SDIO_CK dephasing selection bit */
+#define SDIO_CLKCR_HWFC_EN_Pos (14U)
+#define SDIO_CLKCR_HWFC_EN_Msk (0x1U << SDIO_CLKCR_HWFC_EN_Pos) /*!< 0x00004000 */
+#define SDIO_CLKCR_HWFC_EN SDIO_CLKCR_HWFC_EN_Msk /*!< HW Flow Control enable */
+
+/******************* Bit definition for SDIO_ARG register *******************/
+#define SDIO_ARG_CMDARG_Pos (0U)
+#define SDIO_ARG_CMDARG_Msk (0xFFFFFFFFU << SDIO_ARG_CMDARG_Pos) /*!< 0xFFFFFFFF */
+#define SDIO_ARG_CMDARG SDIO_ARG_CMDARG_Msk /*!< Command argument */
+
+/******************* Bit definition for SDIO_CMD register *******************/
+#define SDIO_CMD_CMDINDEX_Pos (0U)
+#define SDIO_CMD_CMDINDEX_Msk (0x3FU << SDIO_CMD_CMDINDEX_Pos) /*!< 0x0000003F */
+#define SDIO_CMD_CMDINDEX SDIO_CMD_CMDINDEX_Msk /*!< Command Index */
+
+#define SDIO_CMD_WAITRESP_Pos (6U)
+#define SDIO_CMD_WAITRESP_Msk (0x3U << SDIO_CMD_WAITRESP_Pos) /*!< 0x000000C0 */
+#define SDIO_CMD_WAITRESP SDIO_CMD_WAITRESP_Msk /*!< WAITRESP[1:0] bits (Wait for response bits) */
+#define SDIO_CMD_WAITRESP_0 (0x1U << SDIO_CMD_WAITRESP_Pos) /*!< 0x0040 */
+#define SDIO_CMD_WAITRESP_1 (0x2U << SDIO_CMD_WAITRESP_Pos) /*!< 0x0080 */
+
+#define SDIO_CMD_WAITINT_Pos (8U)
+#define SDIO_CMD_WAITINT_Msk (0x1U << SDIO_CMD_WAITINT_Pos) /*!< 0x00000100 */
+#define SDIO_CMD_WAITINT SDIO_CMD_WAITINT_Msk /*!< CPSM Waits for Interrupt Request */
+#define SDIO_CMD_WAITPEND_Pos (9U)
+#define SDIO_CMD_WAITPEND_Msk (0x1U << SDIO_CMD_WAITPEND_Pos) /*!< 0x00000200 */
+#define SDIO_CMD_WAITPEND SDIO_CMD_WAITPEND_Msk /*!< CPSM Waits for ends of data transfer (CmdPend internal signal) */
+#define SDIO_CMD_CPSMEN_Pos (10U)
+#define SDIO_CMD_CPSMEN_Msk (0x1U << SDIO_CMD_CPSMEN_Pos) /*!< 0x00000400 */
+#define SDIO_CMD_CPSMEN SDIO_CMD_CPSMEN_Msk /*!< Command path state machine (CPSM) Enable bit */
+#define SDIO_CMD_SDIOSUSPEND_Pos (11U)
+#define SDIO_CMD_SDIOSUSPEND_Msk (0x1U << SDIO_CMD_SDIOSUSPEND_Pos) /*!< 0x00000800 */
+#define SDIO_CMD_SDIOSUSPEND SDIO_CMD_SDIOSUSPEND_Msk /*!< SD I/O suspend command */
+#define SDIO_CMD_ENCMDCOMPL_Pos (12U)
+#define SDIO_CMD_ENCMDCOMPL_Msk (0x1U << SDIO_CMD_ENCMDCOMPL_Pos) /*!< 0x00001000 */
+#define SDIO_CMD_ENCMDCOMPL SDIO_CMD_ENCMDCOMPL_Msk /*!< Enable CMD completion */
+#define SDIO_CMD_NIEN_Pos (13U)
+#define SDIO_CMD_NIEN_Msk (0x1U << SDIO_CMD_NIEN_Pos) /*!< 0x00002000 */
+#define SDIO_CMD_NIEN SDIO_CMD_NIEN_Msk /*!< Not Interrupt Enable */
+#define SDIO_CMD_CEATACMD_Pos (14U)
+#define SDIO_CMD_CEATACMD_Msk (0x1U << SDIO_CMD_CEATACMD_Pos) /*!< 0x00004000 */
+#define SDIO_CMD_CEATACMD SDIO_CMD_CEATACMD_Msk /*!< CE-ATA command */
+
+/***************** Bit definition for SDIO_RESPCMD register *****************/
+#define SDIO_RESPCMD_RESPCMD_Pos (0U)
+#define SDIO_RESPCMD_RESPCMD_Msk (0x3FU << SDIO_RESPCMD_RESPCMD_Pos) /*!< 0x0000003F */
+#define SDIO_RESPCMD_RESPCMD SDIO_RESPCMD_RESPCMD_Msk /*!< Response command index */
+
+/****************** Bit definition for SDIO_RESP0 register ******************/
+#define SDIO_RESP0_CARDSTATUS0_Pos (0U)
+#define SDIO_RESP0_CARDSTATUS0_Msk (0xFFFFFFFFU << SDIO_RESP0_CARDSTATUS0_Pos) /*!< 0xFFFFFFFF */
+#define SDIO_RESP0_CARDSTATUS0 SDIO_RESP0_CARDSTATUS0_Msk /*!< Card Status */
+
+/****************** Bit definition for SDIO_RESP1 register ******************/
+#define SDIO_RESP1_CARDSTATUS1_Pos (0U)
+#define SDIO_RESP1_CARDSTATUS1_Msk (0xFFFFFFFFU << SDIO_RESP1_CARDSTATUS1_Pos) /*!< 0xFFFFFFFF */
+#define SDIO_RESP1_CARDSTATUS1 SDIO_RESP1_CARDSTATUS1_Msk /*!< Card Status */
+
+/****************** Bit definition for SDIO_RESP2 register ******************/
+#define SDIO_RESP2_CARDSTATUS2_Pos (0U)
+#define SDIO_RESP2_CARDSTATUS2_Msk (0xFFFFFFFFU << SDIO_RESP2_CARDSTATUS2_Pos) /*!< 0xFFFFFFFF */
+#define SDIO_RESP2_CARDSTATUS2 SDIO_RESP2_CARDSTATUS2_Msk /*!< Card Status */
+
+/****************** Bit definition for SDIO_RESP3 register ******************/
+#define SDIO_RESP3_CARDSTATUS3_Pos (0U)
+#define SDIO_RESP3_CARDSTATUS3_Msk (0xFFFFFFFFU << SDIO_RESP3_CARDSTATUS3_Pos) /*!< 0xFFFFFFFF */
+#define SDIO_RESP3_CARDSTATUS3 SDIO_RESP3_CARDSTATUS3_Msk /*!< Card Status */
+
+/****************** Bit definition for SDIO_RESP4 register ******************/
+#define SDIO_RESP4_CARDSTATUS4_Pos (0U)
+#define SDIO_RESP4_CARDSTATUS4_Msk (0xFFFFFFFFU << SDIO_RESP4_CARDSTATUS4_Pos) /*!< 0xFFFFFFFF */
+#define SDIO_RESP4_CARDSTATUS4 SDIO_RESP4_CARDSTATUS4_Msk /*!< Card Status */
+
+/****************** Bit definition for SDIO_DTIMER register *****************/
+#define SDIO_DTIMER_DATATIME_Pos (0U)
+#define SDIO_DTIMER_DATATIME_Msk (0xFFFFFFFFU << SDIO_DTIMER_DATATIME_Pos) /*!< 0xFFFFFFFF */
+#define SDIO_DTIMER_DATATIME SDIO_DTIMER_DATATIME_Msk /*!< Data timeout period. */
+
+/****************** Bit definition for SDIO_DLEN register *******************/
+#define SDIO_DLEN_DATALENGTH_Pos (0U)
+#define SDIO_DLEN_DATALENGTH_Msk (0x1FFFFFFU << SDIO_DLEN_DATALENGTH_Pos) /*!< 0x01FFFFFF */
+#define SDIO_DLEN_DATALENGTH SDIO_DLEN_DATALENGTH_Msk /*!< Data length value */
+
+/****************** Bit definition for SDIO_DCTRL register ******************/
+#define SDIO_DCTRL_DTEN_Pos (0U)
+#define SDIO_DCTRL_DTEN_Msk (0x1U << SDIO_DCTRL_DTEN_Pos) /*!< 0x00000001 */
+#define SDIO_DCTRL_DTEN SDIO_DCTRL_DTEN_Msk /*!< Data transfer enabled bit */
+#define SDIO_DCTRL_DTDIR_Pos (1U)
+#define SDIO_DCTRL_DTDIR_Msk (0x1U << SDIO_DCTRL_DTDIR_Pos) /*!< 0x00000002 */
+#define SDIO_DCTRL_DTDIR SDIO_DCTRL_DTDIR_Msk /*!< Data transfer direction selection */
+#define SDIO_DCTRL_DTMODE_Pos (2U)
+#define SDIO_DCTRL_DTMODE_Msk (0x1U << SDIO_DCTRL_DTMODE_Pos) /*!< 0x00000004 */
+#define SDIO_DCTRL_DTMODE SDIO_DCTRL_DTMODE_Msk /*!< Data transfer mode selection */
+#define SDIO_DCTRL_DMAEN_Pos (3U)
+#define SDIO_DCTRL_DMAEN_Msk (0x1U << SDIO_DCTRL_DMAEN_Pos) /*!< 0x00000008 */
+#define SDIO_DCTRL_DMAEN SDIO_DCTRL_DMAEN_Msk /*!< DMA enabled bit */
+
+#define SDIO_DCTRL_DBLOCKSIZE_Pos (4U)
+#define SDIO_DCTRL_DBLOCKSIZE_Msk (0xFU << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x000000F0 */
+#define SDIO_DCTRL_DBLOCKSIZE SDIO_DCTRL_DBLOCKSIZE_Msk /*!< DBLOCKSIZE[3:0] bits (Data block size) */
+#define SDIO_DCTRL_DBLOCKSIZE_0 (0x1U << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0010 */
+#define SDIO_DCTRL_DBLOCKSIZE_1 (0x2U << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0020 */
+#define SDIO_DCTRL_DBLOCKSIZE_2 (0x4U << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0040 */
+#define SDIO_DCTRL_DBLOCKSIZE_3 (0x8U << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0080 */
+
+#define SDIO_DCTRL_RWSTART_Pos (8U)
+#define SDIO_DCTRL_RWSTART_Msk (0x1U << SDIO_DCTRL_RWSTART_Pos) /*!< 0x00000100 */
+#define SDIO_DCTRL_RWSTART SDIO_DCTRL_RWSTART_Msk /*!< Read wait start */
+#define SDIO_DCTRL_RWSTOP_Pos (9U)
+#define SDIO_DCTRL_RWSTOP_Msk (0x1U << SDIO_DCTRL_RWSTOP_Pos) /*!< 0x00000200 */
+#define SDIO_DCTRL_RWSTOP SDIO_DCTRL_RWSTOP_Msk /*!< Read wait stop */
+#define SDIO_DCTRL_RWMOD_Pos (10U)
+#define SDIO_DCTRL_RWMOD_Msk (0x1U << SDIO_DCTRL_RWMOD_Pos) /*!< 0x00000400 */
+#define SDIO_DCTRL_RWMOD SDIO_DCTRL_RWMOD_Msk /*!< Read wait mode */
+#define SDIO_DCTRL_SDIOEN_Pos (11U)
+#define SDIO_DCTRL_SDIOEN_Msk (0x1U << SDIO_DCTRL_SDIOEN_Pos) /*!< 0x00000800 */
+#define SDIO_DCTRL_SDIOEN SDIO_DCTRL_SDIOEN_Msk /*!< SD I/O enable functions */
+
+/****************** Bit definition for SDIO_DCOUNT register *****************/
+#define SDIO_DCOUNT_DATACOUNT_Pos (0U)
+#define SDIO_DCOUNT_DATACOUNT_Msk (0x1FFFFFFU << SDIO_DCOUNT_DATACOUNT_Pos) /*!< 0x01FFFFFF */
+#define SDIO_DCOUNT_DATACOUNT SDIO_DCOUNT_DATACOUNT_Msk /*!< Data count value */
+
+/****************** Bit definition for SDIO_STA register ********************/
+#define SDIO_STA_CCRCFAIL_Pos (0U)
+#define SDIO_STA_CCRCFAIL_Msk (0x1U << SDIO_STA_CCRCFAIL_Pos) /*!< 0x00000001 */
+#define SDIO_STA_CCRCFAIL SDIO_STA_CCRCFAIL_Msk /*!< Command response received (CRC check failed) */
+#define SDIO_STA_DCRCFAIL_Pos (1U)
+#define SDIO_STA_DCRCFAIL_Msk (0x1U << SDIO_STA_DCRCFAIL_Pos) /*!< 0x00000002 */
+#define SDIO_STA_DCRCFAIL SDIO_STA_DCRCFAIL_Msk /*!< Data block sent/received (CRC check failed) */
+#define SDIO_STA_CTIMEOUT_Pos (2U)
+#define SDIO_STA_CTIMEOUT_Msk (0x1U << SDIO_STA_CTIMEOUT_Pos) /*!< 0x00000004 */
+#define SDIO_STA_CTIMEOUT SDIO_STA_CTIMEOUT_Msk /*!< Command response timeout */
+#define SDIO_STA_DTIMEOUT_Pos (3U)
+#define SDIO_STA_DTIMEOUT_Msk (0x1U << SDIO_STA_DTIMEOUT_Pos) /*!< 0x00000008 */
+#define SDIO_STA_DTIMEOUT SDIO_STA_DTIMEOUT_Msk /*!< Data timeout */
+#define SDIO_STA_TXUNDERR_Pos (4U)
+#define SDIO_STA_TXUNDERR_Msk (0x1U << SDIO_STA_TXUNDERR_Pos) /*!< 0x00000010 */
+#define SDIO_STA_TXUNDERR SDIO_STA_TXUNDERR_Msk /*!< Transmit FIFO underrun error */
+#define SDIO_STA_RXOVERR_Pos (5U)
+#define SDIO_STA_RXOVERR_Msk (0x1U << SDIO_STA_RXOVERR_Pos) /*!< 0x00000020 */
+#define SDIO_STA_RXOVERR SDIO_STA_RXOVERR_Msk /*!< Received FIFO overrun error */
+#define SDIO_STA_CMDREND_Pos (6U)
+#define SDIO_STA_CMDREND_Msk (0x1U << SDIO_STA_CMDREND_Pos) /*!< 0x00000040 */
+#define SDIO_STA_CMDREND SDIO_STA_CMDREND_Msk /*!< Command response received (CRC check passed) */
+#define SDIO_STA_CMDSENT_Pos (7U)
+#define SDIO_STA_CMDSENT_Msk (0x1U << SDIO_STA_CMDSENT_Pos) /*!< 0x00000080 */
+#define SDIO_STA_CMDSENT SDIO_STA_CMDSENT_Msk /*!< Command sent (no response required) */
+#define SDIO_STA_DATAEND_Pos (8U)
+#define SDIO_STA_DATAEND_Msk (0x1U << SDIO_STA_DATAEND_Pos) /*!< 0x00000100 */
+#define SDIO_STA_DATAEND SDIO_STA_DATAEND_Msk /*!< Data end (data counter, SDIDCOUNT, is zero) */
+#define SDIO_STA_STBITERR_Pos (9U)
+#define SDIO_STA_STBITERR_Msk (0x1U << SDIO_STA_STBITERR_Pos) /*!< 0x00000200 */
+#define SDIO_STA_STBITERR SDIO_STA_STBITERR_Msk /*!< Start bit not detected on all data signals in wide bus mode */
+#define SDIO_STA_DBCKEND_Pos (10U)
+#define SDIO_STA_DBCKEND_Msk (0x1U << SDIO_STA_DBCKEND_Pos) /*!< 0x00000400 */
+#define SDIO_STA_DBCKEND SDIO_STA_DBCKEND_Msk /*!< Data block sent/received (CRC check passed) */
+#define SDIO_STA_CMDACT_Pos (11U)
+#define SDIO_STA_CMDACT_Msk (0x1U << SDIO_STA_CMDACT_Pos) /*!< 0x00000800 */
+#define SDIO_STA_CMDACT SDIO_STA_CMDACT_Msk /*!< Command transfer in progress */
+#define SDIO_STA_TXACT_Pos (12U)
+#define SDIO_STA_TXACT_Msk (0x1U << SDIO_STA_TXACT_Pos) /*!< 0x00001000 */
+#define SDIO_STA_TXACT SDIO_STA_TXACT_Msk /*!< Data transmit in progress */
+#define SDIO_STA_RXACT_Pos (13U)
+#define SDIO_STA_RXACT_Msk (0x1U << SDIO_STA_RXACT_Pos) /*!< 0x00002000 */
+#define SDIO_STA_RXACT SDIO_STA_RXACT_Msk /*!< Data receive in progress */
+#define SDIO_STA_TXFIFOHE_Pos (14U)
+#define SDIO_STA_TXFIFOHE_Msk (0x1U << SDIO_STA_TXFIFOHE_Pos) /*!< 0x00004000 */
+#define SDIO_STA_TXFIFOHE SDIO_STA_TXFIFOHE_Msk /*!< Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
+#define SDIO_STA_RXFIFOHF_Pos (15U)
+#define SDIO_STA_RXFIFOHF_Msk (0x1U << SDIO_STA_RXFIFOHF_Pos) /*!< 0x00008000 */
+#define SDIO_STA_RXFIFOHF SDIO_STA_RXFIFOHF_Msk /*!< Receive FIFO Half Full: there are at least 8 words in the FIFO */
+#define SDIO_STA_TXFIFOF_Pos (16U)
+#define SDIO_STA_TXFIFOF_Msk (0x1U << SDIO_STA_TXFIFOF_Pos) /*!< 0x00010000 */
+#define SDIO_STA_TXFIFOF SDIO_STA_TXFIFOF_Msk /*!< Transmit FIFO full */
+#define SDIO_STA_RXFIFOF_Pos (17U)
+#define SDIO_STA_RXFIFOF_Msk (0x1U << SDIO_STA_RXFIFOF_Pos) /*!< 0x00020000 */
+#define SDIO_STA_RXFIFOF SDIO_STA_RXFIFOF_Msk /*!< Receive FIFO full */
+#define SDIO_STA_TXFIFOE_Pos (18U)
+#define SDIO_STA_TXFIFOE_Msk (0x1U << SDIO_STA_TXFIFOE_Pos) /*!< 0x00040000 */
+#define SDIO_STA_TXFIFOE SDIO_STA_TXFIFOE_Msk /*!< Transmit FIFO empty */
+#define SDIO_STA_RXFIFOE_Pos (19U)
+#define SDIO_STA_RXFIFOE_Msk (0x1U << SDIO_STA_RXFIFOE_Pos) /*!< 0x00080000 */
+#define SDIO_STA_RXFIFOE SDIO_STA_RXFIFOE_Msk /*!< Receive FIFO empty */
+#define SDIO_STA_TXDAVL_Pos (20U)
+#define SDIO_STA_TXDAVL_Msk (0x1U << SDIO_STA_TXDAVL_Pos) /*!< 0x00100000 */
+#define SDIO_STA_TXDAVL SDIO_STA_TXDAVL_Msk /*!< Data available in transmit FIFO */
+#define SDIO_STA_RXDAVL_Pos (21U)
+#define SDIO_STA_RXDAVL_Msk (0x1U << SDIO_STA_RXDAVL_Pos) /*!< 0x00200000 */
+#define SDIO_STA_RXDAVL SDIO_STA_RXDAVL_Msk /*!< Data available in receive FIFO */
+#define SDIO_STA_SDIOIT_Pos (22U)
+#define SDIO_STA_SDIOIT_Msk (0x1U << SDIO_STA_SDIOIT_Pos) /*!< 0x00400000 */
+#define SDIO_STA_SDIOIT SDIO_STA_SDIOIT_Msk /*!< SDIO interrupt received */
+#define SDIO_STA_CEATAEND_Pos (23U)
+#define SDIO_STA_CEATAEND_Msk (0x1U << SDIO_STA_CEATAEND_Pos) /*!< 0x00800000 */
+#define SDIO_STA_CEATAEND SDIO_STA_CEATAEND_Msk /*!< CE-ATA command completion signal received for CMD61 */
+
+/******************* Bit definition for SDIO_ICR register *******************/
+#define SDIO_ICR_CCRCFAILC_Pos (0U)
+#define SDIO_ICR_CCRCFAILC_Msk (0x1U << SDIO_ICR_CCRCFAILC_Pos) /*!< 0x00000001 */
+#define SDIO_ICR_CCRCFAILC SDIO_ICR_CCRCFAILC_Msk /*!< CCRCFAIL flag clear bit */
+#define SDIO_ICR_DCRCFAILC_Pos (1U)
+#define SDIO_ICR_DCRCFAILC_Msk (0x1U << SDIO_ICR_DCRCFAILC_Pos) /*!< 0x00000002 */
+#define SDIO_ICR_DCRCFAILC SDIO_ICR_DCRCFAILC_Msk /*!< DCRCFAIL flag clear bit */
+#define SDIO_ICR_CTIMEOUTC_Pos (2U)
+#define SDIO_ICR_CTIMEOUTC_Msk (0x1U << SDIO_ICR_CTIMEOUTC_Pos) /*!< 0x00000004 */
+#define SDIO_ICR_CTIMEOUTC SDIO_ICR_CTIMEOUTC_Msk /*!< CTIMEOUT flag clear bit */
+#define SDIO_ICR_DTIMEOUTC_Pos (3U)
+#define SDIO_ICR_DTIMEOUTC_Msk (0x1U << SDIO_ICR_DTIMEOUTC_Pos) /*!< 0x00000008 */
+#define SDIO_ICR_DTIMEOUTC SDIO_ICR_DTIMEOUTC_Msk /*!< DTIMEOUT flag clear bit */
+#define SDIO_ICR_TXUNDERRC_Pos (4U)
+#define SDIO_ICR_TXUNDERRC_Msk (0x1U << SDIO_ICR_TXUNDERRC_Pos) /*!< 0x00000010 */
+#define SDIO_ICR_TXUNDERRC SDIO_ICR_TXUNDERRC_Msk /*!< TXUNDERR flag clear bit */
+#define SDIO_ICR_RXOVERRC_Pos (5U)
+#define SDIO_ICR_RXOVERRC_Msk (0x1U << SDIO_ICR_RXOVERRC_Pos) /*!< 0x00000020 */
+#define SDIO_ICR_RXOVERRC SDIO_ICR_RXOVERRC_Msk /*!< RXOVERR flag clear bit */
+#define SDIO_ICR_CMDRENDC_Pos (6U)
+#define SDIO_ICR_CMDRENDC_Msk (0x1U << SDIO_ICR_CMDRENDC_Pos) /*!< 0x00000040 */
+#define SDIO_ICR_CMDRENDC SDIO_ICR_CMDRENDC_Msk /*!< CMDREND flag clear bit */
+#define SDIO_ICR_CMDSENTC_Pos (7U)
+#define SDIO_ICR_CMDSENTC_Msk (0x1U << SDIO_ICR_CMDSENTC_Pos) /*!< 0x00000080 */
+#define SDIO_ICR_CMDSENTC SDIO_ICR_CMDSENTC_Msk /*!< CMDSENT flag clear bit */
+#define SDIO_ICR_DATAENDC_Pos (8U)
+#define SDIO_ICR_DATAENDC_Msk (0x1U << SDIO_ICR_DATAENDC_Pos) /*!< 0x00000100 */
+#define SDIO_ICR_DATAENDC SDIO_ICR_DATAENDC_Msk /*!< DATAEND flag clear bit */
+#define SDIO_ICR_STBITERRC_Pos (9U)
+#define SDIO_ICR_STBITERRC_Msk (0x1U << SDIO_ICR_STBITERRC_Pos) /*!< 0x00000200 */
+#define SDIO_ICR_STBITERRC SDIO_ICR_STBITERRC_Msk /*!< STBITERR flag clear bit */
+#define SDIO_ICR_DBCKENDC_Pos (10U)
+#define SDIO_ICR_DBCKENDC_Msk (0x1U << SDIO_ICR_DBCKENDC_Pos) /*!< 0x00000400 */
+#define SDIO_ICR_DBCKENDC SDIO_ICR_DBCKENDC_Msk /*!< DBCKEND flag clear bit */
+#define SDIO_ICR_SDIOITC_Pos (22U)
+#define SDIO_ICR_SDIOITC_Msk (0x1U << SDIO_ICR_SDIOITC_Pos) /*!< 0x00400000 */
+#define SDIO_ICR_SDIOITC SDIO_ICR_SDIOITC_Msk /*!< SDIOIT flag clear bit */
+#define SDIO_ICR_CEATAENDC_Pos (23U)
+#define SDIO_ICR_CEATAENDC_Msk (0x1U << SDIO_ICR_CEATAENDC_Pos) /*!< 0x00800000 */
+#define SDIO_ICR_CEATAENDC SDIO_ICR_CEATAENDC_Msk /*!< CEATAEND flag clear bit */
+
+/****************** Bit definition for SDIO_MASK register *******************/
+#define SDIO_MASK_CCRCFAILIE_Pos (0U)
+#define SDIO_MASK_CCRCFAILIE_Msk (0x1U << SDIO_MASK_CCRCFAILIE_Pos) /*!< 0x00000001 */
+#define SDIO_MASK_CCRCFAILIE SDIO_MASK_CCRCFAILIE_Msk /*!< Command CRC Fail Interrupt Enable */
+#define SDIO_MASK_DCRCFAILIE_Pos (1U)
+#define SDIO_MASK_DCRCFAILIE_Msk (0x1U << SDIO_MASK_DCRCFAILIE_Pos) /*!< 0x00000002 */
+#define SDIO_MASK_DCRCFAILIE SDIO_MASK_DCRCFAILIE_Msk /*!< Data CRC Fail Interrupt Enable */
+#define SDIO_MASK_CTIMEOUTIE_Pos (2U)
+#define SDIO_MASK_CTIMEOUTIE_Msk (0x1U << SDIO_MASK_CTIMEOUTIE_Pos) /*!< 0x00000004 */
+#define SDIO_MASK_CTIMEOUTIE SDIO_MASK_CTIMEOUTIE_Msk /*!< Command TimeOut Interrupt Enable */
+#define SDIO_MASK_DTIMEOUTIE_Pos (3U)
+#define SDIO_MASK_DTIMEOUTIE_Msk (0x1U << SDIO_MASK_DTIMEOUTIE_Pos) /*!< 0x00000008 */
+#define SDIO_MASK_DTIMEOUTIE SDIO_MASK_DTIMEOUTIE_Msk /*!< Data TimeOut Interrupt Enable */
+#define SDIO_MASK_TXUNDERRIE_Pos (4U)
+#define SDIO_MASK_TXUNDERRIE_Msk (0x1U << SDIO_MASK_TXUNDERRIE_Pos) /*!< 0x00000010 */
+#define SDIO_MASK_TXUNDERRIE SDIO_MASK_TXUNDERRIE_Msk /*!< Tx FIFO UnderRun Error Interrupt Enable */
+#define SDIO_MASK_RXOVERRIE_Pos (5U)
+#define SDIO_MASK_RXOVERRIE_Msk (0x1U << SDIO_MASK_RXOVERRIE_Pos) /*!< 0x00000020 */
+#define SDIO_MASK_RXOVERRIE SDIO_MASK_RXOVERRIE_Msk /*!< Rx FIFO OverRun Error Interrupt Enable */
+#define SDIO_MASK_CMDRENDIE_Pos (6U)
+#define SDIO_MASK_CMDRENDIE_Msk (0x1U << SDIO_MASK_CMDRENDIE_Pos) /*!< 0x00000040 */
+#define SDIO_MASK_CMDRENDIE SDIO_MASK_CMDRENDIE_Msk /*!< Command Response Received Interrupt Enable */
+#define SDIO_MASK_CMDSENTIE_Pos (7U)
+#define SDIO_MASK_CMDSENTIE_Msk (0x1U << SDIO_MASK_CMDSENTIE_Pos) /*!< 0x00000080 */
+#define SDIO_MASK_CMDSENTIE SDIO_MASK_CMDSENTIE_Msk /*!< Command Sent Interrupt Enable */
+#define SDIO_MASK_DATAENDIE_Pos (8U)
+#define SDIO_MASK_DATAENDIE_Msk (0x1U << SDIO_MASK_DATAENDIE_Pos) /*!< 0x00000100 */
+#define SDIO_MASK_DATAENDIE SDIO_MASK_DATAENDIE_Msk /*!< Data End Interrupt Enable */
+#define SDIO_MASK_STBITERRIE_Pos (9U)
+#define SDIO_MASK_STBITERRIE_Msk (0x1U << SDIO_MASK_STBITERRIE_Pos) /*!< 0x00000200 */
+#define SDIO_MASK_STBITERRIE SDIO_MASK_STBITERRIE_Msk /*!< Start Bit Error Interrupt Enable */
+#define SDIO_MASK_DBCKENDIE_Pos (10U)
+#define SDIO_MASK_DBCKENDIE_Msk (0x1U << SDIO_MASK_DBCKENDIE_Pos) /*!< 0x00000400 */
+#define SDIO_MASK_DBCKENDIE SDIO_MASK_DBCKENDIE_Msk /*!< Data Block End Interrupt Enable */
+#define SDIO_MASK_CMDACTIE_Pos (11U)
+#define SDIO_MASK_CMDACTIE_Msk (0x1U << SDIO_MASK_CMDACTIE_Pos) /*!< 0x00000800 */
+#define SDIO_MASK_CMDACTIE SDIO_MASK_CMDACTIE_Msk /*!< Command Acting Interrupt Enable */
+#define SDIO_MASK_TXACTIE_Pos (12U)
+#define SDIO_MASK_TXACTIE_Msk (0x1U << SDIO_MASK_TXACTIE_Pos) /*!< 0x00001000 */
+#define SDIO_MASK_TXACTIE SDIO_MASK_TXACTIE_Msk /*!< Data Transmit Acting Interrupt Enable */
+#define SDIO_MASK_RXACTIE_Pos (13U)
+#define SDIO_MASK_RXACTIE_Msk (0x1U << SDIO_MASK_RXACTIE_Pos) /*!< 0x00002000 */
+#define SDIO_MASK_RXACTIE SDIO_MASK_RXACTIE_Msk /*!< Data receive acting interrupt enabled */
+#define SDIO_MASK_TXFIFOHEIE_Pos (14U)
+#define SDIO_MASK_TXFIFOHEIE_Msk (0x1U << SDIO_MASK_TXFIFOHEIE_Pos) /*!< 0x00004000 */
+#define SDIO_MASK_TXFIFOHEIE SDIO_MASK_TXFIFOHEIE_Msk /*!< Tx FIFO Half Empty interrupt Enable */
+#define SDIO_MASK_RXFIFOHFIE_Pos (15U)
+#define SDIO_MASK_RXFIFOHFIE_Msk (0x1U << SDIO_MASK_RXFIFOHFIE_Pos) /*!< 0x00008000 */
+#define SDIO_MASK_RXFIFOHFIE SDIO_MASK_RXFIFOHFIE_Msk /*!< Rx FIFO Half Full interrupt Enable */
+#define SDIO_MASK_TXFIFOFIE_Pos (16U)
+#define SDIO_MASK_TXFIFOFIE_Msk (0x1U << SDIO_MASK_TXFIFOFIE_Pos) /*!< 0x00010000 */
+#define SDIO_MASK_TXFIFOFIE SDIO_MASK_TXFIFOFIE_Msk /*!< Tx FIFO Full interrupt Enable */
+#define SDIO_MASK_RXFIFOFIE_Pos (17U)
+#define SDIO_MASK_RXFIFOFIE_Msk (0x1U << SDIO_MASK_RXFIFOFIE_Pos) /*!< 0x00020000 */
+#define SDIO_MASK_RXFIFOFIE SDIO_MASK_RXFIFOFIE_Msk /*!< Rx FIFO Full interrupt Enable */
+#define SDIO_MASK_TXFIFOEIE_Pos (18U)
+#define SDIO_MASK_TXFIFOEIE_Msk (0x1U << SDIO_MASK_TXFIFOEIE_Pos) /*!< 0x00040000 */
+#define SDIO_MASK_TXFIFOEIE SDIO_MASK_TXFIFOEIE_Msk /*!< Tx FIFO Empty interrupt Enable */
+#define SDIO_MASK_RXFIFOEIE_Pos (19U)
+#define SDIO_MASK_RXFIFOEIE_Msk (0x1U << SDIO_MASK_RXFIFOEIE_Pos) /*!< 0x00080000 */
+#define SDIO_MASK_RXFIFOEIE SDIO_MASK_RXFIFOEIE_Msk /*!< Rx FIFO Empty interrupt Enable */
+#define SDIO_MASK_TXDAVLIE_Pos (20U)
+#define SDIO_MASK_TXDAVLIE_Msk (0x1U << SDIO_MASK_TXDAVLIE_Pos) /*!< 0x00100000 */
+#define SDIO_MASK_TXDAVLIE SDIO_MASK_TXDAVLIE_Msk /*!< Data available in Tx FIFO interrupt Enable */
+#define SDIO_MASK_RXDAVLIE_Pos (21U)
+#define SDIO_MASK_RXDAVLIE_Msk (0x1U << SDIO_MASK_RXDAVLIE_Pos) /*!< 0x00200000 */
+#define SDIO_MASK_RXDAVLIE SDIO_MASK_RXDAVLIE_Msk /*!< Data available in Rx FIFO interrupt Enable */
+#define SDIO_MASK_SDIOITIE_Pos (22U)
+#define SDIO_MASK_SDIOITIE_Msk (0x1U << SDIO_MASK_SDIOITIE_Pos) /*!< 0x00400000 */
+#define SDIO_MASK_SDIOITIE SDIO_MASK_SDIOITIE_Msk /*!< SDIO Mode Interrupt Received interrupt Enable */
+#define SDIO_MASK_CEATAENDIE_Pos (23U)
+#define SDIO_MASK_CEATAENDIE_Msk (0x1U << SDIO_MASK_CEATAENDIE_Pos) /*!< 0x00800000 */
+#define SDIO_MASK_CEATAENDIE SDIO_MASK_CEATAENDIE_Msk /*!< CE-ATA command completion signal received Interrupt Enable */
+
+/***************** Bit definition for SDIO_FIFOCNT register *****************/
+#define SDIO_FIFOCNT_FIFOCOUNT_Pos (0U)
+#define SDIO_FIFOCNT_FIFOCOUNT_Msk (0xFFFFFFU << SDIO_FIFOCNT_FIFOCOUNT_Pos) /*!< 0x00FFFFFF */
+#define SDIO_FIFOCNT_FIFOCOUNT SDIO_FIFOCNT_FIFOCOUNT_Msk /*!< Remaining number of words to be written to or read from the FIFO */
+
+/****************** Bit definition for SDIO_FIFO register *******************/
+#define SDIO_FIFO_FIFODATA_Pos (0U)
+#define SDIO_FIFO_FIFODATA_Msk (0xFFFFFFFFU << SDIO_FIFO_FIFODATA_Pos) /*!< 0xFFFFFFFF */
+#define SDIO_FIFO_FIFODATA SDIO_FIFO_FIFODATA_Msk /*!< Receive and transmit FIFO data */
+
+
+
+/******************************************************************************/
+/* */
+/* Serial Peripheral Interface */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for SPI_CR1 register ********************/
+#define SPI_CR1_CPHA_Pos (0U)
+#define SPI_CR1_CPHA_Msk (0x1U << SPI_CR1_CPHA_Pos) /*!< 0x00000001 */
+#define SPI_CR1_CPHA SPI_CR1_CPHA_Msk /*!< Clock Phase */
+#define SPI_CR1_CPOL_Pos (1U)
+#define SPI_CR1_CPOL_Msk (0x1U << SPI_CR1_CPOL_Pos) /*!< 0x00000002 */
+#define SPI_CR1_CPOL SPI_CR1_CPOL_Msk /*!< Clock Polarity */
+#define SPI_CR1_MSTR_Pos (2U)
+#define SPI_CR1_MSTR_Msk (0x1U << SPI_CR1_MSTR_Pos) /*!< 0x00000004 */
+#define SPI_CR1_MSTR SPI_CR1_MSTR_Msk /*!< Master Selection */
+
+#define SPI_CR1_BR_Pos (3U)
+#define SPI_CR1_BR_Msk (0x7U << SPI_CR1_BR_Pos) /*!< 0x00000038 */
+#define SPI_CR1_BR SPI_CR1_BR_Msk /*!< BR[2:0] bits (Baud Rate Control) */
+#define SPI_CR1_BR_0 (0x1U << SPI_CR1_BR_Pos) /*!< 0x00000008 */
+#define SPI_CR1_BR_1 (0x2U << SPI_CR1_BR_Pos) /*!< 0x00000010 */
+#define SPI_CR1_BR_2 (0x4U << SPI_CR1_BR_Pos) /*!< 0x00000020 */
+
+#define SPI_CR1_SPE_Pos (6U)
+#define SPI_CR1_SPE_Msk (0x1U << SPI_CR1_SPE_Pos) /*!< 0x00000040 */
+#define SPI_CR1_SPE SPI_CR1_SPE_Msk /*!< SPI Enable */
+#define SPI_CR1_LSBFIRST_Pos (7U)
+#define SPI_CR1_LSBFIRST_Msk (0x1U << SPI_CR1_LSBFIRST_Pos) /*!< 0x00000080 */
+#define SPI_CR1_LSBFIRST SPI_CR1_LSBFIRST_Msk /*!< Frame Format */
+#define SPI_CR1_SSI_Pos (8U)
+#define SPI_CR1_SSI_Msk (0x1U << SPI_CR1_SSI_Pos) /*!< 0x00000100 */
+#define SPI_CR1_SSI SPI_CR1_SSI_Msk /*!< Internal slave select */
+#define SPI_CR1_SSM_Pos (9U)
+#define SPI_CR1_SSM_Msk (0x1U << SPI_CR1_SSM_Pos) /*!< 0x00000200 */
+#define SPI_CR1_SSM SPI_CR1_SSM_Msk /*!< Software slave management */
+#define SPI_CR1_RXONLY_Pos (10U)
+#define SPI_CR1_RXONLY_Msk (0x1U << SPI_CR1_RXONLY_Pos) /*!< 0x00000400 */
+#define SPI_CR1_RXONLY SPI_CR1_RXONLY_Msk /*!< Receive only */
+#define SPI_CR1_DFF_Pos (11U)
+#define SPI_CR1_DFF_Msk (0x1U << SPI_CR1_DFF_Pos) /*!< 0x00000800 */
+#define SPI_CR1_DFF SPI_CR1_DFF_Msk /*!< Data Frame Format */
+#define SPI_CR1_CRCNEXT_Pos (12U)
+#define SPI_CR1_CRCNEXT_Msk (0x1U << SPI_CR1_CRCNEXT_Pos) /*!< 0x00001000 */
+#define SPI_CR1_CRCNEXT SPI_CR1_CRCNEXT_Msk /*!< Transmit CRC next */
+#define SPI_CR1_CRCEN_Pos (13U)
+#define SPI_CR1_CRCEN_Msk (0x1U << SPI_CR1_CRCEN_Pos) /*!< 0x00002000 */
+#define SPI_CR1_CRCEN SPI_CR1_CRCEN_Msk /*!< Hardware CRC calculation enable */
+#define SPI_CR1_BIDIOE_Pos (14U)
+#define SPI_CR1_BIDIOE_Msk (0x1U << SPI_CR1_BIDIOE_Pos) /*!< 0x00004000 */
+#define SPI_CR1_BIDIOE SPI_CR1_BIDIOE_Msk /*!< Output enable in bidirectional mode */
+#define SPI_CR1_BIDIMODE_Pos (15U)
+#define SPI_CR1_BIDIMODE_Msk (0x1U << SPI_CR1_BIDIMODE_Pos) /*!< 0x00008000 */
+#define SPI_CR1_BIDIMODE SPI_CR1_BIDIMODE_Msk /*!< Bidirectional data mode enable */
+
+/******************* Bit definition for SPI_CR2 register ********************/
+#define SPI_CR2_RXDMAEN_Pos (0U)
+#define SPI_CR2_RXDMAEN_Msk (0x1U << SPI_CR2_RXDMAEN_Pos) /*!< 0x00000001 */
+#define SPI_CR2_RXDMAEN SPI_CR2_RXDMAEN_Msk /*!< Rx Buffer DMA Enable */
+#define SPI_CR2_TXDMAEN_Pos (1U)
+#define SPI_CR2_TXDMAEN_Msk (0x1U << SPI_CR2_TXDMAEN_Pos) /*!< 0x00000002 */
+#define SPI_CR2_TXDMAEN SPI_CR2_TXDMAEN_Msk /*!< Tx Buffer DMA Enable */
+#define SPI_CR2_SSOE_Pos (2U)
+#define SPI_CR2_SSOE_Msk (0x1U << SPI_CR2_SSOE_Pos) /*!< 0x00000004 */
+#define SPI_CR2_SSOE SPI_CR2_SSOE_Msk /*!< SS Output Enable */
+#define SPI_CR2_ERRIE_Pos (5U)
+#define SPI_CR2_ERRIE_Msk (0x1U << SPI_CR2_ERRIE_Pos) /*!< 0x00000020 */
+#define SPI_CR2_ERRIE SPI_CR2_ERRIE_Msk /*!< Error Interrupt Enable */
+#define SPI_CR2_RXNEIE_Pos (6U)
+#define SPI_CR2_RXNEIE_Msk (0x1U << SPI_CR2_RXNEIE_Pos) /*!< 0x00000040 */
+#define SPI_CR2_RXNEIE SPI_CR2_RXNEIE_Msk /*!< RX buffer Not Empty Interrupt Enable */
+#define SPI_CR2_TXEIE_Pos (7U)
+#define SPI_CR2_TXEIE_Msk (0x1U << SPI_CR2_TXEIE_Pos) /*!< 0x00000080 */
+#define SPI_CR2_TXEIE SPI_CR2_TXEIE_Msk /*!< Tx buffer Empty Interrupt Enable */
+
+/******************** Bit definition for SPI_SR register ********************/
+#define SPI_SR_RXNE_Pos (0U)
+#define SPI_SR_RXNE_Msk (0x1U << SPI_SR_RXNE_Pos) /*!< 0x00000001 */
+#define SPI_SR_RXNE SPI_SR_RXNE_Msk /*!< Receive buffer Not Empty */
+#define SPI_SR_TXE_Pos (1U)
+#define SPI_SR_TXE_Msk (0x1U << SPI_SR_TXE_Pos) /*!< 0x00000002 */
+#define SPI_SR_TXE SPI_SR_TXE_Msk /*!< Transmit buffer Empty */
+#define SPI_SR_CHSIDE_Pos (2U)
+#define SPI_SR_CHSIDE_Msk (0x1U << SPI_SR_CHSIDE_Pos) /*!< 0x00000004 */
+#define SPI_SR_CHSIDE SPI_SR_CHSIDE_Msk /*!< Channel side */
+#define SPI_SR_UDR_Pos (3U)
+#define SPI_SR_UDR_Msk (0x1U << SPI_SR_UDR_Pos) /*!< 0x00000008 */
+#define SPI_SR_UDR SPI_SR_UDR_Msk /*!< Underrun flag */
+#define SPI_SR_CRCERR_Pos (4U)
+#define SPI_SR_CRCERR_Msk (0x1U << SPI_SR_CRCERR_Pos) /*!< 0x00000010 */
+#define SPI_SR_CRCERR SPI_SR_CRCERR_Msk /*!< CRC Error flag */
+#define SPI_SR_MODF_Pos (5U)
+#define SPI_SR_MODF_Msk (0x1U << SPI_SR_MODF_Pos) /*!< 0x00000020 */
+#define SPI_SR_MODF SPI_SR_MODF_Msk /*!< Mode fault */
+#define SPI_SR_OVR_Pos (6U)
+#define SPI_SR_OVR_Msk (0x1U << SPI_SR_OVR_Pos) /*!< 0x00000040 */
+#define SPI_SR_OVR SPI_SR_OVR_Msk /*!< Overrun flag */
+#define SPI_SR_BSY_Pos (7U)
+#define SPI_SR_BSY_Msk (0x1U << SPI_SR_BSY_Pos) /*!< 0x00000080 */
+#define SPI_SR_BSY SPI_SR_BSY_Msk /*!< Busy flag */
+
+/******************** Bit definition for SPI_DR register ********************/
+#define SPI_DR_DR_Pos (0U)
+#define SPI_DR_DR_Msk (0xFFFFU << SPI_DR_DR_Pos) /*!< 0x0000FFFF */
+#define SPI_DR_DR SPI_DR_DR_Msk /*!< Data Register */
+
+/******************* Bit definition for SPI_CRCPR register ******************/
+#define SPI_CRCPR_CRCPOLY_Pos (0U)
+#define SPI_CRCPR_CRCPOLY_Msk (0xFFFFU << SPI_CRCPR_CRCPOLY_Pos) /*!< 0x0000FFFF */
+#define SPI_CRCPR_CRCPOLY SPI_CRCPR_CRCPOLY_Msk /*!< CRC polynomial register */
+
+/****************** Bit definition for SPI_RXCRCR register ******************/
+#define SPI_RXCRCR_RXCRC_Pos (0U)
+#define SPI_RXCRCR_RXCRC_Msk (0xFFFFU << SPI_RXCRCR_RXCRC_Pos) /*!< 0x0000FFFF */
+#define SPI_RXCRCR_RXCRC SPI_RXCRCR_RXCRC_Msk /*!< Rx CRC Register */
+
+/****************** Bit definition for SPI_TXCRCR register ******************/
+#define SPI_TXCRCR_TXCRC_Pos (0U)
+#define SPI_TXCRCR_TXCRC_Msk (0xFFFFU << SPI_TXCRCR_TXCRC_Pos) /*!< 0x0000FFFF */
+#define SPI_TXCRCR_TXCRC SPI_TXCRCR_TXCRC_Msk /*!< Tx CRC Register */
+
+
+
+/******************************************************************************/
+/* */
+/* Inter-integrated Circuit Interface */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for I2C_CR1 register ********************/
+#define I2C_CR1_PE_Pos (0U)
+#define I2C_CR1_PE_Msk (0x1U << I2C_CR1_PE_Pos) /*!< 0x00000001 */
+#define I2C_CR1_PE I2C_CR1_PE_Msk /*!< Peripheral Enable */
+#define I2C_CR1_SMBUS_Pos (1U)
+#define I2C_CR1_SMBUS_Msk (0x1U << I2C_CR1_SMBUS_Pos) /*!< 0x00000002 */
+#define I2C_CR1_SMBUS I2C_CR1_SMBUS_Msk /*!< SMBus Mode */
+#define I2C_CR1_SMBTYPE_Pos (3U)
+#define I2C_CR1_SMBTYPE_Msk (0x1U << I2C_CR1_SMBTYPE_Pos) /*!< 0x00000008 */
+#define I2C_CR1_SMBTYPE I2C_CR1_SMBTYPE_Msk /*!< SMBus Type */
+#define I2C_CR1_ENARP_Pos (4U)
+#define I2C_CR1_ENARP_Msk (0x1U << I2C_CR1_ENARP_Pos) /*!< 0x00000010 */
+#define I2C_CR1_ENARP I2C_CR1_ENARP_Msk /*!< ARP Enable */
+#define I2C_CR1_ENPEC_Pos (5U)
+#define I2C_CR1_ENPEC_Msk (0x1U << I2C_CR1_ENPEC_Pos) /*!< 0x00000020 */
+#define I2C_CR1_ENPEC I2C_CR1_ENPEC_Msk /*!< PEC Enable */
+#define I2C_CR1_ENGC_Pos (6U)
+#define I2C_CR1_ENGC_Msk (0x1U << I2C_CR1_ENGC_Pos) /*!< 0x00000040 */
+#define I2C_CR1_ENGC I2C_CR1_ENGC_Msk /*!< General Call Enable */
+#define I2C_CR1_NOSTRETCH_Pos (7U)
+#define I2C_CR1_NOSTRETCH_Msk (0x1U << I2C_CR1_NOSTRETCH_Pos) /*!< 0x00000080 */
+#define I2C_CR1_NOSTRETCH I2C_CR1_NOSTRETCH_Msk /*!< Clock Stretching Disable (Slave mode) */
+#define I2C_CR1_START_Pos (8U)
+#define I2C_CR1_START_Msk (0x1U << I2C_CR1_START_Pos) /*!< 0x00000100 */
+#define I2C_CR1_START I2C_CR1_START_Msk /*!< Start Generation */
+#define I2C_CR1_STOP_Pos (9U)
+#define I2C_CR1_STOP_Msk (0x1U << I2C_CR1_STOP_Pos) /*!< 0x00000200 */
+#define I2C_CR1_STOP I2C_CR1_STOP_Msk /*!< Stop Generation */
+#define I2C_CR1_ACK_Pos (10U)
+#define I2C_CR1_ACK_Msk (0x1U << I2C_CR1_ACK_Pos) /*!< 0x00000400 */
+#define I2C_CR1_ACK I2C_CR1_ACK_Msk /*!< Acknowledge Enable */
+#define I2C_CR1_POS_Pos (11U)
+#define I2C_CR1_POS_Msk (0x1U << I2C_CR1_POS_Pos) /*!< 0x00000800 */
+#define I2C_CR1_POS I2C_CR1_POS_Msk /*!< Acknowledge/PEC Position (for data reception) */
+#define I2C_CR1_PEC_Pos (12U)
+#define I2C_CR1_PEC_Msk (0x1U << I2C_CR1_PEC_Pos) /*!< 0x00001000 */
+#define I2C_CR1_PEC I2C_CR1_PEC_Msk /*!< Packet Error Checking */
+#define I2C_CR1_ALERT_Pos (13U)
+#define I2C_CR1_ALERT_Msk (0x1U << I2C_CR1_ALERT_Pos) /*!< 0x00002000 */
+#define I2C_CR1_ALERT I2C_CR1_ALERT_Msk /*!< SMBus Alert */
+#define I2C_CR1_SWRST_Pos (15U)
+#define I2C_CR1_SWRST_Msk (0x1U << I2C_CR1_SWRST_Pos) /*!< 0x00008000 */
+#define I2C_CR1_SWRST I2C_CR1_SWRST_Msk /*!< Software Reset */
+
+/******************* Bit definition for I2C_CR2 register ********************/
+#define I2C_CR2_FREQ_Pos (0U)
+#define I2C_CR2_FREQ_Msk (0x3FU << I2C_CR2_FREQ_Pos) /*!< 0x0000003F */
+#define I2C_CR2_FREQ I2C_CR2_FREQ_Msk /*!< FREQ[5:0] bits (Peripheral Clock Frequency) */
+#define I2C_CR2_FREQ_0 (0x01U << I2C_CR2_FREQ_Pos) /*!< 0x00000001 */
+#define I2C_CR2_FREQ_1 (0x02U << I2C_CR2_FREQ_Pos) /*!< 0x00000002 */
+#define I2C_CR2_FREQ_2 (0x04U << I2C_CR2_FREQ_Pos) /*!< 0x00000004 */
+#define I2C_CR2_FREQ_3 (0x08U << I2C_CR2_FREQ_Pos) /*!< 0x00000008 */
+#define I2C_CR2_FREQ_4 (0x10U << I2C_CR2_FREQ_Pos) /*!< 0x00000010 */
+#define I2C_CR2_FREQ_5 (0x20U << I2C_CR2_FREQ_Pos) /*!< 0x00000020 */
+
+#define I2C_CR2_ITERREN_Pos (8U)
+#define I2C_CR2_ITERREN_Msk (0x1U << I2C_CR2_ITERREN_Pos) /*!< 0x00000100 */
+#define I2C_CR2_ITERREN I2C_CR2_ITERREN_Msk /*!< Error Interrupt Enable */
+#define I2C_CR2_ITEVTEN_Pos (9U)
+#define I2C_CR2_ITEVTEN_Msk (0x1U << I2C_CR2_ITEVTEN_Pos) /*!< 0x00000200 */
+#define I2C_CR2_ITEVTEN I2C_CR2_ITEVTEN_Msk /*!< Event Interrupt Enable */
+#define I2C_CR2_ITBUFEN_Pos (10U)
+#define I2C_CR2_ITBUFEN_Msk (0x1U << I2C_CR2_ITBUFEN_Pos) /*!< 0x00000400 */
+#define I2C_CR2_ITBUFEN I2C_CR2_ITBUFEN_Msk /*!< Buffer Interrupt Enable */
+#define I2C_CR2_DMAEN_Pos (11U)
+#define I2C_CR2_DMAEN_Msk (0x1U << I2C_CR2_DMAEN_Pos) /*!< 0x00000800 */
+#define I2C_CR2_DMAEN I2C_CR2_DMAEN_Msk /*!< DMA Requests Enable */
+#define I2C_CR2_LAST_Pos (12U)
+#define I2C_CR2_LAST_Msk (0x1U << I2C_CR2_LAST_Pos) /*!< 0x00001000 */
+#define I2C_CR2_LAST I2C_CR2_LAST_Msk /*!< DMA Last Transfer */
+
+/******************* Bit definition for I2C_OAR1 register *******************/
+#define I2C_OAR1_ADD1_7 ((uint32_t)0x000000FE) /*!< Interface Address */
+#define I2C_OAR1_ADD8_9 ((uint32_t)0x00000300) /*!< Interface Address */
+
+#define I2C_OAR1_ADD0_Pos (0U)
+#define I2C_OAR1_ADD0_Msk (0x1U << I2C_OAR1_ADD0_Pos) /*!< 0x00000001 */
+#define I2C_OAR1_ADD0 I2C_OAR1_ADD0_Msk /*!< Bit 0 */
+#define I2C_OAR1_ADD1_Pos (1U)
+#define I2C_OAR1_ADD1_Msk (0x1U << I2C_OAR1_ADD1_Pos) /*!< 0x00000002 */
+#define I2C_OAR1_ADD1 I2C_OAR1_ADD1_Msk /*!< Bit 1 */
+#define I2C_OAR1_ADD2_Pos (2U)
+#define I2C_OAR1_ADD2_Msk (0x1U << I2C_OAR1_ADD2_Pos) /*!< 0x00000004 */
+#define I2C_OAR1_ADD2 I2C_OAR1_ADD2_Msk /*!< Bit 2 */
+#define I2C_OAR1_ADD3_Pos (3U)
+#define I2C_OAR1_ADD3_Msk (0x1U << I2C_OAR1_ADD3_Pos) /*!< 0x00000008 */
+#define I2C_OAR1_ADD3 I2C_OAR1_ADD3_Msk /*!< Bit 3 */
+#define I2C_OAR1_ADD4_Pos (4U)
+#define I2C_OAR1_ADD4_Msk (0x1U << I2C_OAR1_ADD4_Pos) /*!< 0x00000010 */
+#define I2C_OAR1_ADD4 I2C_OAR1_ADD4_Msk /*!< Bit 4 */
+#define I2C_OAR1_ADD5_Pos (5U)
+#define I2C_OAR1_ADD5_Msk (0x1U << I2C_OAR1_ADD5_Pos) /*!< 0x00000020 */
+#define I2C_OAR1_ADD5 I2C_OAR1_ADD5_Msk /*!< Bit 5 */
+#define I2C_OAR1_ADD6_Pos (6U)
+#define I2C_OAR1_ADD6_Msk (0x1U << I2C_OAR1_ADD6_Pos) /*!< 0x00000040 */
+#define I2C_OAR1_ADD6 I2C_OAR1_ADD6_Msk /*!< Bit 6 */
+#define I2C_OAR1_ADD7_Pos (7U)
+#define I2C_OAR1_ADD7_Msk (0x1U << I2C_OAR1_ADD7_Pos) /*!< 0x00000080 */
+#define I2C_OAR1_ADD7 I2C_OAR1_ADD7_Msk /*!< Bit 7 */
+#define I2C_OAR1_ADD8_Pos (8U)
+#define I2C_OAR1_ADD8_Msk (0x1U << I2C_OAR1_ADD8_Pos) /*!< 0x00000100 */
+#define I2C_OAR1_ADD8 I2C_OAR1_ADD8_Msk /*!< Bit 8 */
+#define I2C_OAR1_ADD9_Pos (9U)
+#define I2C_OAR1_ADD9_Msk (0x1U << I2C_OAR1_ADD9_Pos) /*!< 0x00000200 */
+#define I2C_OAR1_ADD9 I2C_OAR1_ADD9_Msk /*!< Bit 9 */
+
+#define I2C_OAR1_ADDMODE_Pos (15U)
+#define I2C_OAR1_ADDMODE_Msk (0x1U << I2C_OAR1_ADDMODE_Pos) /*!< 0x00008000 */
+#define I2C_OAR1_ADDMODE I2C_OAR1_ADDMODE_Msk /*!< Addressing Mode (Slave mode) */
+
+/******************* Bit definition for I2C_OAR2 register *******************/
+#define I2C_OAR2_ENDUAL_Pos (0U)
+#define I2C_OAR2_ENDUAL_Msk (0x1U << I2C_OAR2_ENDUAL_Pos) /*!< 0x00000001 */
+#define I2C_OAR2_ENDUAL I2C_OAR2_ENDUAL_Msk /*!< Dual addressing mode enable */
+#define I2C_OAR2_ADD2_Pos (1U)
+#define I2C_OAR2_ADD2_Msk (0x7FU << I2C_OAR2_ADD2_Pos) /*!< 0x000000FE */
+#define I2C_OAR2_ADD2 I2C_OAR2_ADD2_Msk /*!< Interface address */
+
+/******************* Bit definition for I2C_SR1 register ********************/
+#define I2C_SR1_SB_Pos (0U)
+#define I2C_SR1_SB_Msk (0x1U << I2C_SR1_SB_Pos) /*!< 0x00000001 */
+#define I2C_SR1_SB I2C_SR1_SB_Msk /*!< Start Bit (Master mode) */
+#define I2C_SR1_ADDR_Pos (1U)
+#define I2C_SR1_ADDR_Msk (0x1U << I2C_SR1_ADDR_Pos) /*!< 0x00000002 */
+#define I2C_SR1_ADDR I2C_SR1_ADDR_Msk /*!< Address sent (master mode)/matched (slave mode) */
+#define I2C_SR1_BTF_Pos (2U)
+#define I2C_SR1_BTF_Msk (0x1U << I2C_SR1_BTF_Pos) /*!< 0x00000004 */
+#define I2C_SR1_BTF I2C_SR1_BTF_Msk /*!< Byte Transfer Finished */
+#define I2C_SR1_ADD10_Pos (3U)
+#define I2C_SR1_ADD10_Msk (0x1U << I2C_SR1_ADD10_Pos) /*!< 0x00000008 */
+#define I2C_SR1_ADD10 I2C_SR1_ADD10_Msk /*!< 10-bit header sent (Master mode) */
+#define I2C_SR1_STOPF_Pos (4U)
+#define I2C_SR1_STOPF_Msk (0x1U << I2C_SR1_STOPF_Pos) /*!< 0x00000010 */
+#define I2C_SR1_STOPF I2C_SR1_STOPF_Msk /*!< Stop detection (Slave mode) */
+#define I2C_SR1_RXNE_Pos (6U)
+#define I2C_SR1_RXNE_Msk (0x1U << I2C_SR1_RXNE_Pos) /*!< 0x00000040 */
+#define I2C_SR1_RXNE I2C_SR1_RXNE_Msk /*!< Data Register not Empty (receivers) */
+#define I2C_SR1_TXE_Pos (7U)
+#define I2C_SR1_TXE_Msk (0x1U << I2C_SR1_TXE_Pos) /*!< 0x00000080 */
+#define I2C_SR1_TXE I2C_SR1_TXE_Msk /*!< Data Register Empty (transmitters) */
+#define I2C_SR1_BERR_Pos (8U)
+#define I2C_SR1_BERR_Msk (0x1U << I2C_SR1_BERR_Pos) /*!< 0x00000100 */
+#define I2C_SR1_BERR I2C_SR1_BERR_Msk /*!< Bus Error */
+#define I2C_SR1_ARLO_Pos (9U)
+#define I2C_SR1_ARLO_Msk (0x1U << I2C_SR1_ARLO_Pos) /*!< 0x00000200 */
+#define I2C_SR1_ARLO I2C_SR1_ARLO_Msk /*!< Arbitration Lost (master mode) */
+#define I2C_SR1_AF_Pos (10U)
+#define I2C_SR1_AF_Msk (0x1U << I2C_SR1_AF_Pos) /*!< 0x00000400 */
+#define I2C_SR1_AF I2C_SR1_AF_Msk /*!< Acknowledge Failure */
+#define I2C_SR1_OVR_Pos (11U)
+#define I2C_SR1_OVR_Msk (0x1U << I2C_SR1_OVR_Pos) /*!< 0x00000800 */
+#define I2C_SR1_OVR I2C_SR1_OVR_Msk /*!< Overrun/Underrun */
+#define I2C_SR1_PECERR_Pos (12U)
+#define I2C_SR1_PECERR_Msk (0x1U << I2C_SR1_PECERR_Pos) /*!< 0x00001000 */
+#define I2C_SR1_PECERR I2C_SR1_PECERR_Msk /*!< PEC Error in reception */
+#define I2C_SR1_TIMEOUT_Pos (14U)
+#define I2C_SR1_TIMEOUT_Msk (0x1U << I2C_SR1_TIMEOUT_Pos) /*!< 0x00004000 */
+#define I2C_SR1_TIMEOUT I2C_SR1_TIMEOUT_Msk /*!< Timeout or Tlow Error */
+#define I2C_SR1_SMBALERT_Pos (15U)
+#define I2C_SR1_SMBALERT_Msk (0x1U << I2C_SR1_SMBALERT_Pos) /*!< 0x00008000 */
+#define I2C_SR1_SMBALERT I2C_SR1_SMBALERT_Msk /*!< SMBus Alert */
+
+/******************* Bit definition for I2C_SR2 register ********************/
+#define I2C_SR2_MSL_Pos (0U)
+#define I2C_SR2_MSL_Msk (0x1U << I2C_SR2_MSL_Pos) /*!< 0x00000001 */
+#define I2C_SR2_MSL I2C_SR2_MSL_Msk /*!< Master/Slave */
+#define I2C_SR2_BUSY_Pos (1U)
+#define I2C_SR2_BUSY_Msk (0x1U << I2C_SR2_BUSY_Pos) /*!< 0x00000002 */
+#define I2C_SR2_BUSY I2C_SR2_BUSY_Msk /*!< Bus Busy */
+#define I2C_SR2_TRA_Pos (2U)
+#define I2C_SR2_TRA_Msk (0x1U << I2C_SR2_TRA_Pos) /*!< 0x00000004 */
+#define I2C_SR2_TRA I2C_SR2_TRA_Msk /*!< Transmitter/Receiver */
+#define I2C_SR2_GENCALL_Pos (4U)
+#define I2C_SR2_GENCALL_Msk (0x1U << I2C_SR2_GENCALL_Pos) /*!< 0x00000010 */
+#define I2C_SR2_GENCALL I2C_SR2_GENCALL_Msk /*!< General Call Address (Slave mode) */
+#define I2C_SR2_SMBDEFAULT_Pos (5U)
+#define I2C_SR2_SMBDEFAULT_Msk (0x1U << I2C_SR2_SMBDEFAULT_Pos) /*!< 0x00000020 */
+#define I2C_SR2_SMBDEFAULT I2C_SR2_SMBDEFAULT_Msk /*!< SMBus Device Default Address (Slave mode) */
+#define I2C_SR2_SMBHOST_Pos (6U)
+#define I2C_SR2_SMBHOST_Msk (0x1U << I2C_SR2_SMBHOST_Pos) /*!< 0x00000040 */
+#define I2C_SR2_SMBHOST I2C_SR2_SMBHOST_Msk /*!< SMBus Host Header (Slave mode) */
+#define I2C_SR2_DUALF_Pos (7U)
+#define I2C_SR2_DUALF_Msk (0x1U << I2C_SR2_DUALF_Pos) /*!< 0x00000080 */
+#define I2C_SR2_DUALF I2C_SR2_DUALF_Msk /*!< Dual Flag (Slave mode) */
+#define I2C_SR2_PEC_Pos (8U)
+#define I2C_SR2_PEC_Msk (0xFFU << I2C_SR2_PEC_Pos) /*!< 0x0000FF00 */
+#define I2C_SR2_PEC I2C_SR2_PEC_Msk /*!< Packet Error Checking Register */
+
+/******************* Bit definition for I2C_CCR register ********************/
+#define I2C_CCR_CCR_Pos (0U)
+#define I2C_CCR_CCR_Msk (0xFFFU << I2C_CCR_CCR_Pos) /*!< 0x00000FFF */
+#define I2C_CCR_CCR I2C_CCR_CCR_Msk /*!< Clock Control Register in Fast/Standard mode (Master mode) */
+#define I2C_CCR_DUTY_Pos (14U)
+#define I2C_CCR_DUTY_Msk (0x1U << I2C_CCR_DUTY_Pos) /*!< 0x00004000 */
+#define I2C_CCR_DUTY I2C_CCR_DUTY_Msk /*!< Fast Mode Duty Cycle */
+#define I2C_CCR_FS_Pos (15U)
+#define I2C_CCR_FS_Msk (0x1U << I2C_CCR_FS_Pos) /*!< 0x00008000 */
+#define I2C_CCR_FS I2C_CCR_FS_Msk /*!< I2C Master Mode Selection */
+
+/****************** Bit definition for I2C_TRISE register *******************/
+#define I2C_TRISE_TRISE_Pos (0U)
+#define I2C_TRISE_TRISE_Msk (0x3FU << I2C_TRISE_TRISE_Pos) /*!< 0x0000003F */
+#define I2C_TRISE_TRISE I2C_TRISE_TRISE_Msk /*!< Maximum Rise Time in Fast/Standard mode (Master mode) */
+
+/******************************************************************************/
+/* */
+/* Universal Synchronous Asynchronous Receiver Transmitter */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for USART_SR register *******************/
+#define USART_SR_PE_Pos (0U)
+#define USART_SR_PE_Msk (0x1U << USART_SR_PE_Pos) /*!< 0x00000001 */
+#define USART_SR_PE USART_SR_PE_Msk /*!< Parity Error */
+#define USART_SR_FE_Pos (1U)
+#define USART_SR_FE_Msk (0x1U << USART_SR_FE_Pos) /*!< 0x00000002 */
+#define USART_SR_FE USART_SR_FE_Msk /*!< Framing Error */
+#define USART_SR_NE_Pos (2U)
+#define USART_SR_NE_Msk (0x1U << USART_SR_NE_Pos) /*!< 0x00000004 */
+#define USART_SR_NE USART_SR_NE_Msk /*!< Noise Error Flag */
+#define USART_SR_ORE_Pos (3U)
+#define USART_SR_ORE_Msk (0x1U << USART_SR_ORE_Pos) /*!< 0x00000008 */
+#define USART_SR_ORE USART_SR_ORE_Msk /*!< OverRun Error */
+#define USART_SR_IDLE_Pos (4U)
+#define USART_SR_IDLE_Msk (0x1U << USART_SR_IDLE_Pos) /*!< 0x00000010 */
+#define USART_SR_IDLE USART_SR_IDLE_Msk /*!< IDLE line detected */
+#define USART_SR_RXNE_Pos (5U)
+#define USART_SR_RXNE_Msk (0x1U << USART_SR_RXNE_Pos) /*!< 0x00000020 */
+#define USART_SR_RXNE USART_SR_RXNE_Msk /*!< Read Data Register Not Empty */
+#define USART_SR_TC_Pos (6U)
+#define USART_SR_TC_Msk (0x1U << USART_SR_TC_Pos) /*!< 0x00000040 */
+#define USART_SR_TC USART_SR_TC_Msk /*!< Transmission Complete */
+#define USART_SR_TXE_Pos (7U)
+#define USART_SR_TXE_Msk (0x1U << USART_SR_TXE_Pos) /*!< 0x00000080 */
+#define USART_SR_TXE USART_SR_TXE_Msk /*!< Transmit Data Register Empty */
+#define USART_SR_LBD_Pos (8U)
+#define USART_SR_LBD_Msk (0x1U << USART_SR_LBD_Pos) /*!< 0x00000100 */
+#define USART_SR_LBD USART_SR_LBD_Msk /*!< LIN Break Detection Flag */
+#define USART_SR_CTS_Pos (9U)
+#define USART_SR_CTS_Msk (0x1U << USART_SR_CTS_Pos) /*!< 0x00000200 */
+#define USART_SR_CTS USART_SR_CTS_Msk /*!< CTS Flag */
+
+/******************* Bit definition for USART_DR register *******************/
+#define USART_DR_DR_Pos (0U)
+#define USART_DR_DR_Msk (0x1FFU << USART_DR_DR_Pos) /*!< 0x000001FF */
+#define USART_DR_DR USART_DR_DR_Msk /*!< Data value */
+
+/****************** Bit definition for USART_BRR register *******************/
+#define USART_BRR_DIV_Fraction_Pos (0U)
+#define USART_BRR_DIV_Fraction_Msk (0xFU << USART_BRR_DIV_Fraction_Pos) /*!< 0x0000000F */
+#define USART_BRR_DIV_Fraction USART_BRR_DIV_Fraction_Msk /*!< Fraction of USARTDIV */
+#define USART_BRR_DIV_Mantissa_Pos (4U)
+#define USART_BRR_DIV_Mantissa_Msk (0xFFFU << USART_BRR_DIV_Mantissa_Pos) /*!< 0x0000FFF0 */
+#define USART_BRR_DIV_Mantissa USART_BRR_DIV_Mantissa_Msk /*!< Mantissa of USARTDIV */
+
+/****************** Bit definition for USART_CR1 register *******************/
+#define USART_CR1_SBK_Pos (0U)
+#define USART_CR1_SBK_Msk (0x1U << USART_CR1_SBK_Pos) /*!< 0x00000001 */
+#define USART_CR1_SBK USART_CR1_SBK_Msk /*!< Send Break */
+#define USART_CR1_RWU_Pos (1U)
+#define USART_CR1_RWU_Msk (0x1U << USART_CR1_RWU_Pos) /*!< 0x00000002 */
+#define USART_CR1_RWU USART_CR1_RWU_Msk /*!< Receiver wakeup */
+#define USART_CR1_RE_Pos (2U)
+#define USART_CR1_RE_Msk (0x1U << USART_CR1_RE_Pos) /*!< 0x00000004 */
+#define USART_CR1_RE USART_CR1_RE_Msk /*!< Receiver Enable */
+#define USART_CR1_TE_Pos (3U)
+#define USART_CR1_TE_Msk (0x1U << USART_CR1_TE_Pos) /*!< 0x00000008 */
+#define USART_CR1_TE USART_CR1_TE_Msk /*!< Transmitter Enable */
+#define USART_CR1_IDLEIE_Pos (4U)
+#define USART_CR1_IDLEIE_Msk (0x1U << USART_CR1_IDLEIE_Pos) /*!< 0x00000010 */
+#define USART_CR1_IDLEIE USART_CR1_IDLEIE_Msk /*!< IDLE Interrupt Enable */
+#define USART_CR1_RXNEIE_Pos (5U)
+#define USART_CR1_RXNEIE_Msk (0x1U << USART_CR1_RXNEIE_Pos) /*!< 0x00000020 */
+#define USART_CR1_RXNEIE USART_CR1_RXNEIE_Msk /*!< RXNE Interrupt Enable */
+#define USART_CR1_TCIE_Pos (6U)
+#define USART_CR1_TCIE_Msk (0x1U << USART_CR1_TCIE_Pos) /*!< 0x00000040 */
+#define USART_CR1_TCIE USART_CR1_TCIE_Msk /*!< Transmission Complete Interrupt Enable */
+#define USART_CR1_TXEIE_Pos (7U)
+#define USART_CR1_TXEIE_Msk (0x1U << USART_CR1_TXEIE_Pos) /*!< 0x00000080 */
+#define USART_CR1_TXEIE USART_CR1_TXEIE_Msk /*!< PE Interrupt Enable */
+#define USART_CR1_PEIE_Pos (8U)
+#define USART_CR1_PEIE_Msk (0x1U << USART_CR1_PEIE_Pos) /*!< 0x00000100 */
+#define USART_CR1_PEIE USART_CR1_PEIE_Msk /*!< PE Interrupt Enable */
+#define USART_CR1_PS_Pos (9U)
+#define USART_CR1_PS_Msk (0x1U << USART_CR1_PS_Pos) /*!< 0x00000200 */
+#define USART_CR1_PS USART_CR1_PS_Msk /*!< Parity Selection */
+#define USART_CR1_PCE_Pos (10U)
+#define USART_CR1_PCE_Msk (0x1U << USART_CR1_PCE_Pos) /*!< 0x00000400 */
+#define USART_CR1_PCE USART_CR1_PCE_Msk /*!< Parity Control Enable */
+#define USART_CR1_WAKE_Pos (11U)
+#define USART_CR1_WAKE_Msk (0x1U << USART_CR1_WAKE_Pos) /*!< 0x00000800 */
+#define USART_CR1_WAKE USART_CR1_WAKE_Msk /*!< Wakeup method */
+#define USART_CR1_M_Pos (12U)
+#define USART_CR1_M_Msk (0x1U << USART_CR1_M_Pos) /*!< 0x00001000 */
+#define USART_CR1_M USART_CR1_M_Msk /*!< Word length */
+#define USART_CR1_UE_Pos (13U)
+#define USART_CR1_UE_Msk (0x1U << USART_CR1_UE_Pos) /*!< 0x00002000 */
+#define USART_CR1_UE USART_CR1_UE_Msk /*!< USART Enable */
+
+/****************** Bit definition for USART_CR2 register *******************/
+#define USART_CR2_ADD_Pos (0U)
+#define USART_CR2_ADD_Msk (0xFU << USART_CR2_ADD_Pos) /*!< 0x0000000F */
+#define USART_CR2_ADD USART_CR2_ADD_Msk /*!< Address of the USART node */
+#define USART_CR2_LBDL_Pos (5U)
+#define USART_CR2_LBDL_Msk (0x1U << USART_CR2_LBDL_Pos) /*!< 0x00000020 */
+#define USART_CR2_LBDL USART_CR2_LBDL_Msk /*!< LIN Break Detection Length */
+#define USART_CR2_LBDIE_Pos (6U)
+#define USART_CR2_LBDIE_Msk (0x1U << USART_CR2_LBDIE_Pos) /*!< 0x00000040 */
+#define USART_CR2_LBDIE USART_CR2_LBDIE_Msk /*!< LIN Break Detection Interrupt Enable */
+#define USART_CR2_LBCL_Pos (8U)
+#define USART_CR2_LBCL_Msk (0x1U << USART_CR2_LBCL_Pos) /*!< 0x00000100 */
+#define USART_CR2_LBCL USART_CR2_LBCL_Msk /*!< Last Bit Clock pulse */
+#define USART_CR2_CPHA_Pos (9U)
+#define USART_CR2_CPHA_Msk (0x1U << USART_CR2_CPHA_Pos) /*!< 0x00000200 */
+#define USART_CR2_CPHA USART_CR2_CPHA_Msk /*!< Clock Phase */
+#define USART_CR2_CPOL_Pos (10U)
+#define USART_CR2_CPOL_Msk (0x1U << USART_CR2_CPOL_Pos) /*!< 0x00000400 */
+#define USART_CR2_CPOL USART_CR2_CPOL_Msk /*!< Clock Polarity */
+#define USART_CR2_CLKEN_Pos (11U)
+#define USART_CR2_CLKEN_Msk (0x1U << USART_CR2_CLKEN_Pos) /*!< 0x00000800 */
+#define USART_CR2_CLKEN USART_CR2_CLKEN_Msk /*!< Clock Enable */
+
+#define USART_CR2_STOP_Pos (12U)
+#define USART_CR2_STOP_Msk (0x3U << USART_CR2_STOP_Pos) /*!< 0x00003000 */
+#define USART_CR2_STOP USART_CR2_STOP_Msk /*!< STOP[1:0] bits (STOP bits) */
+#define USART_CR2_STOP_0 (0x1U << USART_CR2_STOP_Pos) /*!< 0x00001000 */
+#define USART_CR2_STOP_1 (0x2U << USART_CR2_STOP_Pos) /*!< 0x00002000 */
+
+#define USART_CR2_LINEN_Pos (14U)
+#define USART_CR2_LINEN_Msk (0x1U << USART_CR2_LINEN_Pos) /*!< 0x00004000 */
+#define USART_CR2_LINEN USART_CR2_LINEN_Msk /*!< LIN mode enable */
+
+/****************** Bit definition for USART_CR3 register *******************/
+#define USART_CR3_EIE_Pos (0U)
+#define USART_CR3_EIE_Msk (0x1U << USART_CR3_EIE_Pos) /*!< 0x00000001 */
+#define USART_CR3_EIE USART_CR3_EIE_Msk /*!< Error Interrupt Enable */
+#define USART_CR3_IREN_Pos (1U)
+#define USART_CR3_IREN_Msk (0x1U << USART_CR3_IREN_Pos) /*!< 0x00000002 */
+#define USART_CR3_IREN USART_CR3_IREN_Msk /*!< IrDA mode Enable */
+#define USART_CR3_IRLP_Pos (2U)
+#define USART_CR3_IRLP_Msk (0x1U << USART_CR3_IRLP_Pos) /*!< 0x00000004 */
+#define USART_CR3_IRLP USART_CR3_IRLP_Msk /*!< IrDA Low-Power */
+#define USART_CR3_HDSEL_Pos (3U)
+#define USART_CR3_HDSEL_Msk (0x1U << USART_CR3_HDSEL_Pos) /*!< 0x00000008 */
+#define USART_CR3_HDSEL USART_CR3_HDSEL_Msk /*!< Half-Duplex Selection */
+#define USART_CR3_NACK_Pos (4U)
+#define USART_CR3_NACK_Msk (0x1U << USART_CR3_NACK_Pos) /*!< 0x00000010 */
+#define USART_CR3_NACK USART_CR3_NACK_Msk /*!< Smartcard NACK enable */
+#define USART_CR3_SCEN_Pos (5U)
+#define USART_CR3_SCEN_Msk (0x1U << USART_CR3_SCEN_Pos) /*!< 0x00000020 */
+#define USART_CR3_SCEN USART_CR3_SCEN_Msk /*!< Smartcard mode enable */
+#define USART_CR3_DMAR_Pos (6U)
+#define USART_CR3_DMAR_Msk (0x1U << USART_CR3_DMAR_Pos) /*!< 0x00000040 */
+#define USART_CR3_DMAR USART_CR3_DMAR_Msk /*!< DMA Enable Receiver */
+#define USART_CR3_DMAT_Pos (7U)
+#define USART_CR3_DMAT_Msk (0x1U << USART_CR3_DMAT_Pos) /*!< 0x00000080 */
+#define USART_CR3_DMAT USART_CR3_DMAT_Msk /*!< DMA Enable Transmitter */
+#define USART_CR3_RTSE_Pos (8U)
+#define USART_CR3_RTSE_Msk (0x1U << USART_CR3_RTSE_Pos) /*!< 0x00000100 */
+#define USART_CR3_RTSE USART_CR3_RTSE_Msk /*!< RTS Enable */
+#define USART_CR3_CTSE_Pos (9U)
+#define USART_CR3_CTSE_Msk (0x1U << USART_CR3_CTSE_Pos) /*!< 0x00000200 */
+#define USART_CR3_CTSE USART_CR3_CTSE_Msk /*!< CTS Enable */
+#define USART_CR3_CTSIE_Pos (10U)
+#define USART_CR3_CTSIE_Msk (0x1U << USART_CR3_CTSIE_Pos) /*!< 0x00000400 */
+#define USART_CR3_CTSIE USART_CR3_CTSIE_Msk /*!< CTS Interrupt Enable */
+
+/****************** Bit definition for USART_GTPR register ******************/
+#define USART_GTPR_PSC_Pos (0U)
+#define USART_GTPR_PSC_Msk (0xFFU << USART_GTPR_PSC_Pos) /*!< 0x000000FF */
+#define USART_GTPR_PSC USART_GTPR_PSC_Msk /*!< PSC[7:0] bits (Prescaler value) */
+#define USART_GTPR_PSC_0 (0x01U << USART_GTPR_PSC_Pos) /*!< 0x00000001 */
+#define USART_GTPR_PSC_1 (0x02U << USART_GTPR_PSC_Pos) /*!< 0x00000002 */
+#define USART_GTPR_PSC_2 (0x04U << USART_GTPR_PSC_Pos) /*!< 0x00000004 */
+#define USART_GTPR_PSC_3 (0x08U << USART_GTPR_PSC_Pos) /*!< 0x00000008 */
+#define USART_GTPR_PSC_4 (0x10U << USART_GTPR_PSC_Pos) /*!< 0x00000010 */
+#define USART_GTPR_PSC_5 (0x20U << USART_GTPR_PSC_Pos) /*!< 0x00000020 */
+#define USART_GTPR_PSC_6 (0x40U << USART_GTPR_PSC_Pos) /*!< 0x00000040 */
+#define USART_GTPR_PSC_7 (0x80U << USART_GTPR_PSC_Pos) /*!< 0x00000080 */
+
+#define USART_GTPR_GT_Pos (8U)
+#define USART_GTPR_GT_Msk (0xFFU << USART_GTPR_GT_Pos) /*!< 0x0000FF00 */
+#define USART_GTPR_GT USART_GTPR_GT_Msk /*!< Guard time value */
+
+/******************************************************************************/
+/* */
+/* Debug MCU */
+/* */
+/******************************************************************************/
+
+/**************** Bit definition for DBGMCU_IDCODE register *****************/
+#define DBGMCU_IDCODE_DEV_ID_Pos (0U)
+#define DBGMCU_IDCODE_DEV_ID_Msk (0xFFFU << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */
+#define DBGMCU_IDCODE_DEV_ID DBGMCU_IDCODE_DEV_ID_Msk /*!< Device Identifier */
+
+#define DBGMCU_IDCODE_REV_ID_Pos (16U)
+#define DBGMCU_IDCODE_REV_ID_Msk (0xFFFFU << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */
+#define DBGMCU_IDCODE_REV_ID DBGMCU_IDCODE_REV_ID_Msk /*!< REV_ID[15:0] bits (Revision Identifier) */
+#define DBGMCU_IDCODE_REV_ID_0 (0x0001U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00010000 */
+#define DBGMCU_IDCODE_REV_ID_1 (0x0002U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00020000 */
+#define DBGMCU_IDCODE_REV_ID_2 (0x0004U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00040000 */
+#define DBGMCU_IDCODE_REV_ID_3 (0x0008U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00080000 */
+#define DBGMCU_IDCODE_REV_ID_4 (0x0010U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00100000 */
+#define DBGMCU_IDCODE_REV_ID_5 (0x0020U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00200000 */
+#define DBGMCU_IDCODE_REV_ID_6 (0x0040U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00400000 */
+#define DBGMCU_IDCODE_REV_ID_7 (0x0080U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00800000 */
+#define DBGMCU_IDCODE_REV_ID_8 (0x0100U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x01000000 */
+#define DBGMCU_IDCODE_REV_ID_9 (0x0200U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x02000000 */
+#define DBGMCU_IDCODE_REV_ID_10 (0x0400U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x04000000 */
+#define DBGMCU_IDCODE_REV_ID_11 (0x0800U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x08000000 */
+#define DBGMCU_IDCODE_REV_ID_12 (0x1000U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x10000000 */
+#define DBGMCU_IDCODE_REV_ID_13 (0x2000U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x20000000 */
+#define DBGMCU_IDCODE_REV_ID_14 (0x4000U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x40000000 */
+#define DBGMCU_IDCODE_REV_ID_15 (0x8000U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x80000000 */
+
+/****************** Bit definition for DBGMCU_CR register *******************/
+#define DBGMCU_CR_DBG_SLEEP_Pos (0U)
+#define DBGMCU_CR_DBG_SLEEP_Msk (0x1U << DBGMCU_CR_DBG_SLEEP_Pos) /*!< 0x00000001 */
+#define DBGMCU_CR_DBG_SLEEP DBGMCU_CR_DBG_SLEEP_Msk /*!< Debug Sleep Mode */
+#define DBGMCU_CR_DBG_STOP_Pos (1U)
+#define DBGMCU_CR_DBG_STOP_Msk (0x1U << DBGMCU_CR_DBG_STOP_Pos) /*!< 0x00000002 */
+#define DBGMCU_CR_DBG_STOP DBGMCU_CR_DBG_STOP_Msk /*!< Debug Stop Mode */
+#define DBGMCU_CR_DBG_STANDBY_Pos (2U)
+#define DBGMCU_CR_DBG_STANDBY_Msk (0x1U << DBGMCU_CR_DBG_STANDBY_Pos) /*!< 0x00000004 */
+#define DBGMCU_CR_DBG_STANDBY DBGMCU_CR_DBG_STANDBY_Msk /*!< Debug Standby mode */
+#define DBGMCU_CR_TRACE_IOEN_Pos (5U)
+#define DBGMCU_CR_TRACE_IOEN_Msk (0x1U << DBGMCU_CR_TRACE_IOEN_Pos) /*!< 0x00000020 */
+#define DBGMCU_CR_TRACE_IOEN DBGMCU_CR_TRACE_IOEN_Msk /*!< Trace Pin Assignment Control */
+
+#define DBGMCU_CR_TRACE_MODE_Pos (6U)
+#define DBGMCU_CR_TRACE_MODE_Msk (0x3U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x000000C0 */
+#define DBGMCU_CR_TRACE_MODE DBGMCU_CR_TRACE_MODE_Msk /*!< TRACE_MODE[1:0] bits (Trace Pin Assignment Control) */
+#define DBGMCU_CR_TRACE_MODE_0 (0x1U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000040 */
+#define DBGMCU_CR_TRACE_MODE_1 (0x2U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000080 */
+
+#define DBGMCU_CR_DBG_IWDG_STOP_Pos (8U)
+#define DBGMCU_CR_DBG_IWDG_STOP_Msk (0x1U << DBGMCU_CR_DBG_IWDG_STOP_Pos) /*!< 0x00000100 */
+#define DBGMCU_CR_DBG_IWDG_STOP DBGMCU_CR_DBG_IWDG_STOP_Msk /*!< Debug Independent Watchdog stopped when Core is halted */
+#define DBGMCU_CR_DBG_WWDG_STOP_Pos (9U)
+#define DBGMCU_CR_DBG_WWDG_STOP_Msk (0x1U << DBGMCU_CR_DBG_WWDG_STOP_Pos) /*!< 0x00000200 */
+#define DBGMCU_CR_DBG_WWDG_STOP DBGMCU_CR_DBG_WWDG_STOP_Msk /*!< Debug Window Watchdog stopped when Core is halted */
+#define DBGMCU_CR_DBG_TIM1_STOP_Pos (10U)
+#define DBGMCU_CR_DBG_TIM1_STOP_Msk (0x1U << DBGMCU_CR_DBG_TIM1_STOP_Pos) /*!< 0x00000400 */
+#define DBGMCU_CR_DBG_TIM1_STOP DBGMCU_CR_DBG_TIM1_STOP_Msk /*!< TIM1 counter stopped when core is halted */
+#define DBGMCU_CR_DBG_TIM2_STOP_Pos (11U)
+#define DBGMCU_CR_DBG_TIM2_STOP_Msk (0x1U << DBGMCU_CR_DBG_TIM2_STOP_Pos) /*!< 0x00000800 */
+#define DBGMCU_CR_DBG_TIM2_STOP DBGMCU_CR_DBG_TIM2_STOP_Msk /*!< TIM2 counter stopped when core is halted */
+#define DBGMCU_CR_DBG_TIM3_STOP_Pos (12U)
+#define DBGMCU_CR_DBG_TIM3_STOP_Msk (0x1U << DBGMCU_CR_DBG_TIM3_STOP_Pos) /*!< 0x00001000 */
+#define DBGMCU_CR_DBG_TIM3_STOP DBGMCU_CR_DBG_TIM3_STOP_Msk /*!< TIM3 counter stopped when core is halted */
+#define DBGMCU_CR_DBG_TIM4_STOP_Pos (13U)
+#define DBGMCU_CR_DBG_TIM4_STOP_Msk (0x1U << DBGMCU_CR_DBG_TIM4_STOP_Pos) /*!< 0x00002000 */
+#define DBGMCU_CR_DBG_TIM4_STOP DBGMCU_CR_DBG_TIM4_STOP_Msk /*!< TIM4 counter stopped when core is halted */
+#define DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT_Pos (15U)
+#define DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT_Msk (0x1U << DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT_Pos) /*!< 0x00008000 */
+#define DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT_Msk /*!< SMBUS timeout mode stopped when Core is halted */
+#define DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT_Pos (16U)
+#define DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT_Msk (0x1U << DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT_Pos) /*!< 0x00010000 */
+#define DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT_Msk /*!< SMBUS timeout mode stopped when Core is halted */
+#define DBGMCU_CR_DBG_TIM15_STOP_Pos (22U)
+#define DBGMCU_CR_DBG_TIM15_STOP_Msk (0x1U << DBGMCU_CR_DBG_TIM15_STOP_Pos) /*!< 0x00400000 */
+#define DBGMCU_CR_DBG_TIM15_STOP DBGMCU_CR_DBG_TIM15_STOP_Msk /*!< Debug TIM15 stopped when Core is halted */
+#define DBGMCU_CR_DBG_TIM16_STOP_Pos (23U)
+#define DBGMCU_CR_DBG_TIM16_STOP_Msk (0x1U << DBGMCU_CR_DBG_TIM16_STOP_Pos) /*!< 0x00800000 */
+#define DBGMCU_CR_DBG_TIM16_STOP DBGMCU_CR_DBG_TIM16_STOP_Msk /*!< Debug TIM16 stopped when Core is halted */
+#define DBGMCU_CR_DBG_TIM17_STOP_Pos (24U)
+#define DBGMCU_CR_DBG_TIM17_STOP_Msk (0x1U << DBGMCU_CR_DBG_TIM17_STOP_Pos) /*!< 0x01000000 */
+#define DBGMCU_CR_DBG_TIM17_STOP DBGMCU_CR_DBG_TIM17_STOP_Msk /*!< Debug TIM17 stopped when Core is halted */
+
+/******************************************************************************/
+/* */
+/* FLASH and Option Bytes Registers */
+/* */
+/******************************************************************************/
+/******************* Bit definition for FLASH_ACR register ******************/
+#define FLASH_ACR_HLFCYA_Pos (3U)
+#define FLASH_ACR_HLFCYA_Msk (0x1U << FLASH_ACR_HLFCYA_Pos) /*!< 0x00000008 */
+#define FLASH_ACR_HLFCYA FLASH_ACR_HLFCYA_Msk /*!< Flash Half Cycle Access Enable */
+
+/****************** Bit definition for FLASH_KEYR register ******************/
+#define FLASH_KEYR_FKEYR_Pos (0U)
+#define FLASH_KEYR_FKEYR_Msk (0xFFFFFFFFU << FLASH_KEYR_FKEYR_Pos) /*!< 0xFFFFFFFF */
+#define FLASH_KEYR_FKEYR FLASH_KEYR_FKEYR_Msk /*!< FPEC Key */
+
+#define RDP_KEY_Pos (0U)
+#define RDP_KEY_Msk (0xA5U << RDP_KEY_Pos) /*!< 0x000000A5 */
+#define RDP_KEY RDP_KEY_Msk /*!< RDP Key */
+#define FLASH_KEY1_Pos (0U)
+#define FLASH_KEY1_Msk (0x45670123U << FLASH_KEY1_Pos) /*!< 0x45670123 */
+#define FLASH_KEY1 FLASH_KEY1_Msk /*!< FPEC Key1 */
+#define FLASH_KEY2_Pos (0U)
+#define FLASH_KEY2_Msk (0xCDEF89ABU << FLASH_KEY2_Pos) /*!< 0xCDEF89AB */
+#define FLASH_KEY2 FLASH_KEY2_Msk /*!< FPEC Key2 */
+
+/***************** Bit definition for FLASH_OPTKEYR register ****************/
+#define FLASH_OPTKEYR_OPTKEYR_Pos (0U)
+#define FLASH_OPTKEYR_OPTKEYR_Msk (0xFFFFFFFFU << FLASH_OPTKEYR_OPTKEYR_Pos) /*!< 0xFFFFFFFF */
+#define FLASH_OPTKEYR_OPTKEYR FLASH_OPTKEYR_OPTKEYR_Msk /*!< Option Byte Key */
+
+#define FLASH_OPTKEY1 FLASH_KEY1 /*!< Option Byte Key1 */
+#define FLASH_OPTKEY2 FLASH_KEY2 /*!< Option Byte Key2 */
+
+/****************** Bit definition for FLASH_SR register ********************/
+#define FLASH_SR_BSY_Pos (0U)
+#define FLASH_SR_BSY_Msk (0x1U << FLASH_SR_BSY_Pos) /*!< 0x00000001 */
+#define FLASH_SR_BSY FLASH_SR_BSY_Msk /*!< Busy */
+#define FLASH_SR_PGERR_Pos (2U)
+#define FLASH_SR_PGERR_Msk (0x1U << FLASH_SR_PGERR_Pos) /*!< 0x00000004 */
+#define FLASH_SR_PGERR FLASH_SR_PGERR_Msk /*!< Programming Error */
+#define FLASH_SR_WRPRTERR_Pos (4U)
+#define FLASH_SR_WRPRTERR_Msk (0x1U << FLASH_SR_WRPRTERR_Pos) /*!< 0x00000010 */
+#define FLASH_SR_WRPRTERR FLASH_SR_WRPRTERR_Msk /*!< Write Protection Error */
+#define FLASH_SR_EOP_Pos (5U)
+#define FLASH_SR_EOP_Msk (0x1U << FLASH_SR_EOP_Pos) /*!< 0x00000020 */
+#define FLASH_SR_EOP FLASH_SR_EOP_Msk /*!< End of operation */
+
+/******************* Bit definition for FLASH_CR register *******************/
+#define FLASH_CR_PG_Pos (0U)
+#define FLASH_CR_PG_Msk (0x1U << FLASH_CR_PG_Pos) /*!< 0x00000001 */
+#define FLASH_CR_PG FLASH_CR_PG_Msk /*!< Programming */
+#define FLASH_CR_PER_Pos (1U)
+#define FLASH_CR_PER_Msk (0x1U << FLASH_CR_PER_Pos) /*!< 0x00000002 */
+#define FLASH_CR_PER FLASH_CR_PER_Msk /*!< Page Erase */
+#define FLASH_CR_MER_Pos (2U)
+#define FLASH_CR_MER_Msk (0x1U << FLASH_CR_MER_Pos) /*!< 0x00000004 */
+#define FLASH_CR_MER FLASH_CR_MER_Msk /*!< Mass Erase */
+#define FLASH_CR_OPTPG_Pos (4U)
+#define FLASH_CR_OPTPG_Msk (0x1U << FLASH_CR_OPTPG_Pos) /*!< 0x00000010 */
+#define FLASH_CR_OPTPG FLASH_CR_OPTPG_Msk /*!< Option Byte Programming */
+#define FLASH_CR_OPTER_Pos (5U)
+#define FLASH_CR_OPTER_Msk (0x1U << FLASH_CR_OPTER_Pos) /*!< 0x00000020 */
+#define FLASH_CR_OPTER FLASH_CR_OPTER_Msk /*!< Option Byte Erase */
+#define FLASH_CR_STRT_Pos (6U)
+#define FLASH_CR_STRT_Msk (0x1U << FLASH_CR_STRT_Pos) /*!< 0x00000040 */
+#define FLASH_CR_STRT FLASH_CR_STRT_Msk /*!< Start */
+#define FLASH_CR_LOCK_Pos (7U)
+#define FLASH_CR_LOCK_Msk (0x1U << FLASH_CR_LOCK_Pos) /*!< 0x00000080 */
+#define FLASH_CR_LOCK FLASH_CR_LOCK_Msk /*!< Lock */
+#define FLASH_CR_OPTWRE_Pos (9U)
+#define FLASH_CR_OPTWRE_Msk (0x1U << FLASH_CR_OPTWRE_Pos) /*!< 0x00000200 */
+#define FLASH_CR_OPTWRE FLASH_CR_OPTWRE_Msk /*!< Option Bytes Write Enable */
+#define FLASH_CR_ERRIE_Pos (10U)
+#define FLASH_CR_ERRIE_Msk (0x1U << FLASH_CR_ERRIE_Pos) /*!< 0x00000400 */
+#define FLASH_CR_ERRIE FLASH_CR_ERRIE_Msk /*!< Error Interrupt Enable */
+#define FLASH_CR_EOPIE_Pos (12U)
+#define FLASH_CR_EOPIE_Msk (0x1U << FLASH_CR_EOPIE_Pos) /*!< 0x00001000 */
+#define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk /*!< End of operation interrupt enable */
+
+/******************* Bit definition for FLASH_AR register *******************/
+#define FLASH_AR_FAR_Pos (0U)
+#define FLASH_AR_FAR_Msk (0xFFFFFFFFU << FLASH_AR_FAR_Pos) /*!< 0xFFFFFFFF */
+#define FLASH_AR_FAR FLASH_AR_FAR_Msk /*!< Flash Address */
+
+/****************** Bit definition for FLASH_OBR register *******************/
+#define FLASH_OBR_OPTERR_Pos (0U)
+#define FLASH_OBR_OPTERR_Msk (0x1U << FLASH_OBR_OPTERR_Pos) /*!< 0x00000001 */
+#define FLASH_OBR_OPTERR FLASH_OBR_OPTERR_Msk /*!< Option Byte Error */
+#define FLASH_OBR_RDPRT_Pos (1U)
+#define FLASH_OBR_RDPRT_Msk (0x1U << FLASH_OBR_RDPRT_Pos) /*!< 0x00000002 */
+#define FLASH_OBR_RDPRT FLASH_OBR_RDPRT_Msk /*!< Read protection */
+
+#define FLASH_OBR_IWDG_SW_Pos (2U)
+#define FLASH_OBR_IWDG_SW_Msk (0x1U << FLASH_OBR_IWDG_SW_Pos) /*!< 0x00000004 */
+#define FLASH_OBR_IWDG_SW FLASH_OBR_IWDG_SW_Msk /*!< IWDG SW */
+#define FLASH_OBR_nRST_STOP_Pos (3U)
+#define FLASH_OBR_nRST_STOP_Msk (0x1U << FLASH_OBR_nRST_STOP_Pos) /*!< 0x00000008 */
+#define FLASH_OBR_nRST_STOP FLASH_OBR_nRST_STOP_Msk /*!< nRST_STOP */
+#define FLASH_OBR_nRST_STDBY_Pos (4U)
+#define FLASH_OBR_nRST_STDBY_Msk (0x1U << FLASH_OBR_nRST_STDBY_Pos) /*!< 0x00000010 */
+#define FLASH_OBR_nRST_STDBY FLASH_OBR_nRST_STDBY_Msk /*!< nRST_STDBY */
+#define FLASH_OBR_USER_Pos (2U)
+#define FLASH_OBR_USER_Msk (0x7U << FLASH_OBR_USER_Pos) /*!< 0x0000001C */
+#define FLASH_OBR_USER FLASH_OBR_USER_Msk /*!< User Option Bytes */
+#define FLASH_OBR_DATA0_Pos (10U)
+#define FLASH_OBR_DATA0_Msk (0xFFU << FLASH_OBR_DATA0_Pos) /*!< 0x0003FC00 */
+#define FLASH_OBR_DATA0 FLASH_OBR_DATA0_Msk /*!< Data0 */
+#define FLASH_OBR_DATA1_Pos (18U)
+#define FLASH_OBR_DATA1_Msk (0xFFU << FLASH_OBR_DATA1_Pos) /*!< 0x03FC0000 */
+#define FLASH_OBR_DATA1 FLASH_OBR_DATA1_Msk /*!< Data1 */
+
+/****************** Bit definition for FLASH_WRPR register ******************/
+#define FLASH_WRPR_WRP_Pos (0U)
+#define FLASH_WRPR_WRP_Msk (0xFFFFFFFFU << FLASH_WRPR_WRP_Pos) /*!< 0xFFFFFFFF */
+#define FLASH_WRPR_WRP FLASH_WRPR_WRP_Msk /*!< Write Protect */
+
+/*----------------------------------------------------------------------------*/
+
+/****************** Bit definition for FLASH_RDP register *******************/
+#define FLASH_RDP_RDP_Pos (0U)
+#define FLASH_RDP_RDP_Msk (0xFFU << FLASH_RDP_RDP_Pos) /*!< 0x000000FF */
+#define FLASH_RDP_RDP FLASH_RDP_RDP_Msk /*!< Read protection option byte */
+#define FLASH_RDP_nRDP_Pos (8U)
+#define FLASH_RDP_nRDP_Msk (0xFFU << FLASH_RDP_nRDP_Pos) /*!< 0x0000FF00 */
+#define FLASH_RDP_nRDP FLASH_RDP_nRDP_Msk /*!< Read protection complemented option byte */
+
+/****************** Bit definition for FLASH_USER register ******************/
+#define FLASH_USER_USER_Pos (16U)
+#define FLASH_USER_USER_Msk (0xFFU << FLASH_USER_USER_Pos) /*!< 0x00FF0000 */
+#define FLASH_USER_USER FLASH_USER_USER_Msk /*!< User option byte */
+#define FLASH_USER_nUSER_Pos (24U)
+#define FLASH_USER_nUSER_Msk (0xFFU << FLASH_USER_nUSER_Pos) /*!< 0xFF000000 */
+#define FLASH_USER_nUSER FLASH_USER_nUSER_Msk /*!< User complemented option byte */
+
+/****************** Bit definition for FLASH_Data0 register *****************/
+#define FLASH_DATA0_DATA0_Pos (0U)
+#define FLASH_DATA0_DATA0_Msk (0xFFU << FLASH_DATA0_DATA0_Pos) /*!< 0x000000FF */
+#define FLASH_DATA0_DATA0 FLASH_DATA0_DATA0_Msk /*!< User data storage option byte */
+#define FLASH_DATA0_nDATA0_Pos (8U)
+#define FLASH_DATA0_nDATA0_Msk (0xFFU << FLASH_DATA0_nDATA0_Pos) /*!< 0x0000FF00 */
+#define FLASH_DATA0_nDATA0 FLASH_DATA0_nDATA0_Msk /*!< User data storage complemented option byte */
+
+/****************** Bit definition for FLASH_Data1 register *****************/
+#define FLASH_DATA1_DATA1_Pos (16U)
+#define FLASH_DATA1_DATA1_Msk (0xFFU << FLASH_DATA1_DATA1_Pos) /*!< 0x00FF0000 */
+#define FLASH_DATA1_DATA1 FLASH_DATA1_DATA1_Msk /*!< User data storage option byte */
+#define FLASH_DATA1_nDATA1_Pos (24U)
+#define FLASH_DATA1_nDATA1_Msk (0xFFU << FLASH_DATA1_nDATA1_Pos) /*!< 0xFF000000 */
+#define FLASH_DATA1_nDATA1 FLASH_DATA1_nDATA1_Msk /*!< User data storage complemented option byte */
+
+/****************** Bit definition for FLASH_WRP0 register ******************/
+#define FLASH_WRP0_WRP0_Pos (0U)
+#define FLASH_WRP0_WRP0_Msk (0xFFU << FLASH_WRP0_WRP0_Pos) /*!< 0x000000FF */
+#define FLASH_WRP0_WRP0 FLASH_WRP0_WRP0_Msk /*!< Flash memory write protection option bytes */
+#define FLASH_WRP0_nWRP0_Pos (8U)
+#define FLASH_WRP0_nWRP0_Msk (0xFFU << FLASH_WRP0_nWRP0_Pos) /*!< 0x0000FF00 */
+#define FLASH_WRP0_nWRP0 FLASH_WRP0_nWRP0_Msk /*!< Flash memory write protection complemented option bytes */
+
+/****************** Bit definition for FLASH_WRP1 register ******************/
+#define FLASH_WRP1_WRP1_Pos (16U)
+#define FLASH_WRP1_WRP1_Msk (0xFFU << FLASH_WRP1_WRP1_Pos) /*!< 0x00FF0000 */
+#define FLASH_WRP1_WRP1 FLASH_WRP1_WRP1_Msk /*!< Flash memory write protection option bytes */
+#define FLASH_WRP1_nWRP1_Pos (24U)
+#define FLASH_WRP1_nWRP1_Msk (0xFFU << FLASH_WRP1_nWRP1_Pos) /*!< 0xFF000000 */
+#define FLASH_WRP1_nWRP1 FLASH_WRP1_nWRP1_Msk /*!< Flash memory write protection complemented option bytes */
+
+/****************** Bit definition for FLASH_WRP2 register ******************/
+#define FLASH_WRP2_WRP2_Pos (0U)
+#define FLASH_WRP2_WRP2_Msk (0xFFU << FLASH_WRP2_WRP2_Pos) /*!< 0x000000FF */
+#define FLASH_WRP2_WRP2 FLASH_WRP2_WRP2_Msk /*!< Flash memory write protection option bytes */
+#define FLASH_WRP2_nWRP2_Pos (8U)
+#define FLASH_WRP2_nWRP2_Msk (0xFFU << FLASH_WRP2_nWRP2_Pos) /*!< 0x0000FF00 */
+#define FLASH_WRP2_nWRP2 FLASH_WRP2_nWRP2_Msk /*!< Flash memory write protection complemented option bytes */
+
+/****************** Bit definition for FLASH_WRP3 register ******************/
+#define FLASH_WRP3_WRP3_Pos (16U)
+#define FLASH_WRP3_WRP3_Msk (0xFFU << FLASH_WRP3_WRP3_Pos) /*!< 0x00FF0000 */
+#define FLASH_WRP3_WRP3 FLASH_WRP3_WRP3_Msk /*!< Flash memory write protection option bytes */
+#define FLASH_WRP3_nWRP3_Pos (24U)
+#define FLASH_WRP3_nWRP3_Msk (0xFFU << FLASH_WRP3_nWRP3_Pos) /*!< 0xFF000000 */
+#define FLASH_WRP3_nWRP3 FLASH_WRP3_nWRP3_Msk /*!< Flash memory write protection complemented option bytes */
+
+
+
+/**
+ * @}
+*/
+
+/**
+ * @}
+*/
+
+/** @addtogroup Exported_macro
+ * @{
+ */
+
+/****************************** ADC Instances *********************************/
+#define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1))
+
+#define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC1_COMMON)
+
+#define IS_ADC_DMA_CAPABILITY_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
+
+/****************************** CEC Instances *********************************/
+#define IS_CEC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CEC)
+
+/****************************** CRC Instances *********************************/
+#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
+
+/****************************** DAC Instances *********************************/
+#define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC)
+
+/****************************** DMA Instances *********************************/
+#define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \
+ ((INSTANCE) == DMA1_Channel2) || \
+ ((INSTANCE) == DMA1_Channel3) || \
+ ((INSTANCE) == DMA1_Channel4) || \
+ ((INSTANCE) == DMA1_Channel5) || \
+ ((INSTANCE) == DMA1_Channel6) || \
+ ((INSTANCE) == DMA1_Channel7))
+
+/******************************* GPIO Instances *******************************/
+#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
+ ((INSTANCE) == GPIOB) || \
+ ((INSTANCE) == GPIOC) || \
+ ((INSTANCE) == GPIOD) || \
+ ((INSTANCE) == GPIOE))
+
+/**************************** GPIO Alternate Function Instances ***************/
+#define IS_GPIO_AF_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
+
+/**************************** GPIO Lock Instances *****************************/
+#define IS_GPIO_LOCK_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
+
+/******************************** I2C Instances *******************************/
+#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
+ ((INSTANCE) == I2C2))
+
+/****************************** IWDG Instances ********************************/
+#define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
+
+/******************************** SPI Instances *******************************/
+#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
+ ((INSTANCE) == SPI2))
+
+/****************************** START TIM Instances ***************************/
+/****************************** TIM Instances *********************************/
+#define IS_TIM_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM6) || \
+ ((INSTANCE) == TIM7) || \
+ ((INSTANCE) == TIM15) || \
+ ((INSTANCE) == TIM16) || \
+ ((INSTANCE) == TIM17))
+
+#define IS_TIM_CC1_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM15) || \
+ ((INSTANCE) == TIM16) || \
+ ((INSTANCE) == TIM17))
+
+#define IS_TIM_CC2_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM15))
+
+#define IS_TIM_CC3_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4))
+
+#define IS_TIM_CC4_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4))
+
+#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4))
+
+#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4))
+
+#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM15))
+
+#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM15))
+
+#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4))
+
+#define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4))
+
+#define IS_TIM_XOR_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4))
+
+#define IS_TIM_MASTER_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM6) || \
+ ((INSTANCE) == TIM7) || \
+ ((INSTANCE) == TIM15))
+
+#define IS_TIM_SLAVE_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM15))
+
+#define IS_TIM_DMABURST_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM15) || \
+ ((INSTANCE) == TIM16) || \
+ ((INSTANCE) == TIM17))
+
+#define IS_TIM_BREAK_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM15) || \
+ ((INSTANCE) == TIM16) || \
+ ((INSTANCE) == TIM17))
+
+#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
+ ((((INSTANCE) == TIM1) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM2) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM3) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM4) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM15) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2))) \
+ || \
+ (((INSTANCE) == TIM16) && \
+ (((CHANNEL) == TIM_CHANNEL_1))) \
+ || \
+ (((INSTANCE) == TIM17) && \
+ (((CHANNEL) == TIM_CHANNEL_1))))
+
+#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
+ ((((INSTANCE) == TIM1) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3))) \
+ || \
+ (((INSTANCE) == TIM15) && \
+ ((CHANNEL) == TIM_CHANNEL_1)) \
+ || \
+ (((INSTANCE) == TIM16) && \
+ ((CHANNEL) == TIM_CHANNEL_1)) \
+ || \
+ (((INSTANCE) == TIM17) && \
+ ((CHANNEL) == TIM_CHANNEL_1)))
+
+#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4))
+
+#define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM15) || \
+ ((INSTANCE) == TIM16) || \
+ ((INSTANCE) == TIM17))
+
+#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM15) || \
+ ((INSTANCE) == TIM16) || \
+ ((INSTANCE) == TIM17))
+
+#define IS_TIM_DMA_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM6) || \
+ ((INSTANCE) == TIM7) || \
+ ((INSTANCE) == TIM15) || \
+ ((INSTANCE) == TIM16) || \
+ ((INSTANCE) == TIM17))
+
+#define IS_TIM_DMA_CC_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM15) || \
+ ((INSTANCE) == TIM16) || \
+ ((INSTANCE) == TIM17))
+
+#define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM15) || \
+ ((INSTANCE) == TIM16) || \
+ ((INSTANCE) == TIM17))
+
+/****************************** END TIM Instances *****************************/
+
+
+/******************** USART Instances : Synchronous mode **********************/
+#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3))
+
+/******************** UART Instances : Asynchronous mode **********************/
+#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3))
+
+/******************** UART Instances : Half-Duplex mode **********************/
+#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3))
+
+/******************** UART Instances : LIN mode **********************/
+#define IS_UART_LIN_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3))
+
+/****************** UART Instances : Hardware Flow control ********************/
+#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3))
+
+/********************* UART Instances : Smard card mode ***********************/
+#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3))
+
+/*********************** UART Instances : IRDA mode ***************************/
+#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3))
+
+/***************** UART Instances : Multi-Processor mode **********************/
+#define IS_UART_MULTIPROCESSOR_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3))
+
+/***************** UART Instances : DMA mode available **********************/
+#define IS_UART_DMA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3))
+
+/****************************** RTC Instances *********************************/
+#define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
+
+/**************************** WWDG Instances *****************************/
+#define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
+
+
+
+
+
+/**
+ * @}
+*/
+/******************************************************************************/
+/* For a painless codes migration between the STM32F1xx device product */
+/* lines, the aliases defined below are put in place to overcome the */
+/* differences in the interrupt handlers and IRQn definitions. */
+/* No need to update developed interrupt code when moving across */
+/* product lines within the same STM32F1 Family */
+/******************************************************************************/
+
+/* Aliases for __IRQn */
+#define ADC1_2_IRQn ADC1_IRQn
+#define USBWakeUp_IRQn CEC_IRQn
+#define OTG_FS_WKUP_IRQn CEC_IRQn
+#define TIM1_BRK_IRQn TIM1_BRK_TIM15_IRQn
+#define TIM1_BRK_TIM9_IRQn TIM1_BRK_TIM15_IRQn
+#define TIM9_IRQn TIM1_BRK_TIM15_IRQn
+#define TIM1_TRG_COM_TIM11_IRQn TIM1_TRG_COM_TIM17_IRQn
+#define TIM1_TRG_COM_IRQn TIM1_TRG_COM_TIM17_IRQn
+#define TIM11_IRQn TIM1_TRG_COM_TIM17_IRQn
+#define TIM1_UP_IRQn TIM1_UP_TIM16_IRQn
+#define TIM10_IRQn TIM1_UP_TIM16_IRQn
+#define TIM1_UP_TIM10_IRQn TIM1_UP_TIM16_IRQn
+#define TIM6_IRQn TIM6_DAC_IRQn
+
+
+/* Aliases for __IRQHandler */
+#define ADC1_2_IRQHandler ADC1_IRQHandler
+#define USBWakeUp_IRQHandler CEC_IRQHandler
+#define OTG_FS_WKUP_IRQHandler CEC_IRQHandler
+#define TIM1_BRK_IRQHandler TIM1_BRK_TIM15_IRQHandler
+#define TIM1_BRK_TIM9_IRQHandler TIM1_BRK_TIM15_IRQHandler
+#define TIM9_IRQHandler TIM1_BRK_TIM15_IRQHandler
+#define TIM1_TRG_COM_TIM11_IRQHandler TIM1_TRG_COM_TIM17_IRQHandler
+#define TIM1_TRG_COM_IRQHandler TIM1_TRG_COM_TIM17_IRQHandler
+#define TIM11_IRQHandler TIM1_TRG_COM_TIM17_IRQHandler
+#define TIM1_UP_IRQHandler TIM1_UP_TIM16_IRQHandler
+#define TIM10_IRQHandler TIM1_UP_TIM16_IRQHandler
+#define TIM1_UP_TIM10_IRQHandler TIM1_UP_TIM16_IRQHandler
+#define TIM6_IRQHandler TIM6_DAC_IRQHandler
+
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+
+#ifdef __cplusplus
+ }
+#endif /* __cplusplus */
+
+#endif /* __STM32F100xB_H */
+
+
+
+ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Device/ST/STM32F1xx/Include/stm32f100xe.h b/Device/ST/STM32F1xx/Include/stm32f100xe.h
new file mode 100644
index 0000000..68012d3
--- /dev/null
+++ b/Device/ST/STM32F1xx/Include/stm32f100xe.h
@@ -0,0 +1,7434 @@
+/**
+ ******************************************************************************
+ * @file stm32f100xe.h
+ * @author MCD Application Team
+ * @version V4.1.0
+ * @date 29-April-2016
+ * @brief CMSIS Cortex-M3 Device Peripheral Access Layer Header File.
+ * This file contains all the peripheral register's definitions, bits
+ * definitions and memory mapping for STM32F1xx devices.
+ *
+ * This file contains:
+ * - Data structures and the address mapping for all peripherals
+ * - Peripheral's registers declarations and bits definition
+ * - Macros to access peripheral’s registers hardware
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+
+/** @addtogroup CMSIS
+ * @{
+ */
+
+/** @addtogroup stm32f100xe
+ * @{
+ */
+
+#ifndef __STM32F100xE_H
+#define __STM32F100xE_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/** @addtogroup Configuration_section_for_CMSIS
+ * @{
+ */
+/**
+ * @brief Configuration of the Cortex-M3 Processor and Core Peripherals
+ */
+ #define __MPU_PRESENT 0 /*!< Other STM32 devices does not provide an MPU */
+#define __CM3_REV 0x0200 /*!< Core Revision r2p0 */
+#define __NVIC_PRIO_BITS 4 /*!< STM32 uses 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
+
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_interrupt_number_definition
+ * @{
+ */
+
+/**
+ * @brief STM32F10x Interrupt Number Definition, according to the selected device
+ * in @ref Library_configuration_section
+ */
+
+ /*!< Interrupt Number Definition */
+typedef enum
+{
+/****** Cortex-M3 Processor Exceptions Numbers ***************************************************/
+ NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
+ HardFault_IRQn = -13, /*!< 3 Cortex-M3 Hard Fault Interrupt */
+ MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */
+ BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */
+ UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */
+ SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */
+ DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */
+ PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */
+ SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */
+
+/****** STM32 specific Interrupt Numbers *********************************************************/
+ WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
+ PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */
+ TAMPER_IRQn = 2, /*!< Tamper Interrupt */
+ RTC_IRQn = 3, /*!< RTC global Interrupt */
+ FLASH_IRQn = 4, /*!< FLASH global Interrupt */
+ RCC_IRQn = 5, /*!< RCC global Interrupt */
+ EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */
+ EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */
+ EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */
+ EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */
+ EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */
+ DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 global Interrupt */
+ DMA1_Channel2_IRQn = 12, /*!< DMA1 Channel 2 global Interrupt */
+ DMA1_Channel3_IRQn = 13, /*!< DMA1 Channel 3 global Interrupt */
+ DMA1_Channel4_IRQn = 14, /*!< DMA1 Channel 4 global Interrupt */
+ DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 global Interrupt */
+ DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 global Interrupt */
+ DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 global Interrupt */
+ ADC1_IRQn = 18, /*!< ADC1 global Interrupt */
+ EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
+ TIM1_BRK_TIM15_IRQn = 24, /*!< TIM1 Break and TIM15 Interrupts */
+ TIM1_UP_TIM16_IRQn = 25, /*!< TIM1 Update and TIM16 Interrupts */
+ TIM1_TRG_COM_TIM17_IRQn = 26, /*!< TIM1 Trigger and Commutation and TIM17 Interrupt */
+ TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
+ TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
+ TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
+ TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
+ I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
+ I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
+ I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
+ I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
+ SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
+ SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
+ USART1_IRQn = 37, /*!< USART1 global Interrupt */
+ USART2_IRQn = 38, /*!< USART2 global Interrupt */
+ USART3_IRQn = 39, /*!< USART3 global Interrupt */
+ EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
+ RTC_Alarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */
+ CEC_IRQn = 42, /*!< HDMI-CEC Interrupt */
+ TIM12_IRQn = 43, /*!< TIM12 global Interrupt */
+ TIM13_IRQn = 44, /*!< TIM13 global Interrupt */
+ TIM14_IRQn = 45, /*!< TIM14 global Interrupt */
+ TIM5_IRQn = 50, /*!< TIM5 global Interrupt */
+ SPI3_IRQn = 51, /*!< SPI3 global Interrupt */
+ UART4_IRQn = 52, /*!< UART4 global Interrupt */
+ UART5_IRQn = 53, /*!< UART5 global Interrupt */
+ TIM6_DAC_IRQn = 54, /*!< TIM6 and DAC underrun Interrupt */
+ TIM7_IRQn = 55, /*!< TIM7 global Interrupt */
+ DMA2_Channel1_IRQn = 56, /*!< DMA2 Channel 1 global Interrupt */
+ DMA2_Channel2_IRQn = 57, /*!< DMA2 Channel 2 global Interrupt */
+ DMA2_Channel3_IRQn = 58, /*!< DMA2 Channel 3 global Interrupt */
+ DMA2_Channel4_5_IRQn = 59, /*!< DMA2 Channel 4 and Channel 5 global Interrupt */
+ DMA2_Channel4_IRQn = 59, /*!< DMA2 Channel 4 global Interrupt */
+ DMA2_Channel5_IRQn = 60 /*!< DMA2 Channel 5 global Interrupt (DMA2 Channel 5 is
+ mapped at position 60 only if the MISC_REMAP bit in
+ the AFIO_MAPR2 register is set) */
+} IRQn_Type;
+
+
+/**
+ * @}
+ */
+
+#include "core_cm3.h"
+#include "system_stm32f1xx.h"
+#include <stdint.h>
+
+/** @addtogroup Peripheral_registers_structures
+ * @{
+ */
+
+/**
+ * @brief Analog to Digital Converter
+ */
+
+typedef struct
+{
+ __IO uint32_t SR;
+ __IO uint32_t CR1;
+ __IO uint32_t CR2;
+ __IO uint32_t SMPR1;
+ __IO uint32_t SMPR2;
+ __IO uint32_t JOFR1;
+ __IO uint32_t JOFR2;
+ __IO uint32_t JOFR3;
+ __IO uint32_t JOFR4;
+ __IO uint32_t HTR;
+ __IO uint32_t LTR;
+ __IO uint32_t SQR1;
+ __IO uint32_t SQR2;
+ __IO uint32_t SQR3;
+ __IO uint32_t JSQR;
+ __IO uint32_t JDR1;
+ __IO uint32_t JDR2;
+ __IO uint32_t JDR3;
+ __IO uint32_t JDR4;
+ __IO uint32_t DR;
+} ADC_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t SR; /*!< ADC status register, used for ADC multimode (bits common to several ADC instances). Address offset: ADC1 base address */
+ __IO uint32_t CR1; /*!< ADC control register 1, used for ADC multimode (bits common to several ADC instances). Address offset: ADC1 base address + 0x04 */
+ __IO uint32_t CR2; /*!< ADC control register 2, used for ADC multimode (bits common to several ADC instances). Address offset: ADC1 base address + 0x08 */
+ uint32_t RESERVED[16];
+ __IO uint32_t DR; /*!< ADC data register, used for ADC multimode (bits common to several ADC instances). Address offset: ADC1 base address + 0x4C */
+} ADC_Common_TypeDef;
+
+/**
+ * @brief Backup Registers
+ */
+
+typedef struct
+{
+ uint32_t RESERVED0;
+ __IO uint32_t DR1;
+ __IO uint32_t DR2;
+ __IO uint32_t DR3;
+ __IO uint32_t DR4;
+ __IO uint32_t DR5;
+ __IO uint32_t DR6;
+ __IO uint32_t DR7;
+ __IO uint32_t DR8;
+ __IO uint32_t DR9;
+ __IO uint32_t DR10;
+ __IO uint32_t RTCCR;
+ __IO uint32_t CR;
+ __IO uint32_t CSR;
+ uint32_t RESERVED13[2];
+ __IO uint32_t DR11;
+ __IO uint32_t DR12;
+ __IO uint32_t DR13;
+ __IO uint32_t DR14;
+ __IO uint32_t DR15;
+ __IO uint32_t DR16;
+ __IO uint32_t DR17;
+ __IO uint32_t DR18;
+ __IO uint32_t DR19;
+ __IO uint32_t DR20;
+ __IO uint32_t DR21;
+ __IO uint32_t DR22;
+ __IO uint32_t DR23;
+ __IO uint32_t DR24;
+ __IO uint32_t DR25;
+ __IO uint32_t DR26;
+ __IO uint32_t DR27;
+ __IO uint32_t DR28;
+ __IO uint32_t DR29;
+ __IO uint32_t DR30;
+ __IO uint32_t DR31;
+ __IO uint32_t DR32;
+ __IO uint32_t DR33;
+ __IO uint32_t DR34;
+ __IO uint32_t DR35;
+ __IO uint32_t DR36;
+ __IO uint32_t DR37;
+ __IO uint32_t DR38;
+ __IO uint32_t DR39;
+ __IO uint32_t DR40;
+ __IO uint32_t DR41;
+ __IO uint32_t DR42;
+} BKP_TypeDef;
+
+
+/**
+ * @brief Consumer Electronics Control (CEC)
+ */
+typedef struct
+{
+ __IO uint32_t CFGR;
+ __IO uint32_t OAR;
+ __IO uint32_t PRES;
+ __IO uint32_t ESR;
+ __IO uint32_t CSR;
+ __IO uint32_t TXD;
+ __IO uint32_t RXD;
+} CEC_TypeDef;
+
+/**
+ * @brief CRC calculation unit
+ */
+
+typedef struct
+{
+ __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
+ __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
+ uint8_t RESERVED0; /*!< Reserved, Address offset: 0x05 */
+ uint16_t RESERVED1; /*!< Reserved, Address offset: 0x06 */
+ __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
+} CRC_TypeDef;
+
+/**
+ * @brief Digital to Analog Converter
+ */
+
+typedef struct
+{
+ __IO uint32_t CR;
+ __IO uint32_t SWTRIGR;
+ __IO uint32_t DHR12R1;
+ __IO uint32_t DHR12L1;
+ __IO uint32_t DHR8R1;
+ __IO uint32_t DHR12R2;
+ __IO uint32_t DHR12L2;
+ __IO uint32_t DHR8R2;
+ __IO uint32_t DHR12RD;
+ __IO uint32_t DHR12LD;
+ __IO uint32_t DHR8RD;
+ __IO uint32_t DOR1;
+ __IO uint32_t DOR2;
+ __IO uint32_t SR;
+} DAC_TypeDef;
+
+/**
+ * @brief Debug MCU
+ */
+
+typedef struct
+{
+ __IO uint32_t IDCODE;
+ __IO uint32_t CR;
+}DBGMCU_TypeDef;
+
+/**
+ * @brief DMA Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t CCR;
+ __IO uint32_t CNDTR;
+ __IO uint32_t CPAR;
+ __IO uint32_t CMAR;
+} DMA_Channel_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t ISR;
+ __IO uint32_t IFCR;
+} DMA_TypeDef;
+
+
+
+/**
+ * @brief External Interrupt/Event Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t IMR;
+ __IO uint32_t EMR;
+ __IO uint32_t RTSR;
+ __IO uint32_t FTSR;
+ __IO uint32_t SWIER;
+ __IO uint32_t PR;
+} EXTI_TypeDef;
+
+/**
+ * @brief FLASH Registers
+ */
+
+typedef struct
+{
+ __IO uint32_t ACR;
+ __IO uint32_t KEYR;
+ __IO uint32_t OPTKEYR;
+ __IO uint32_t SR;
+ __IO uint32_t CR;
+ __IO uint32_t AR;
+ __IO uint32_t RESERVED;
+ __IO uint32_t OBR;
+ __IO uint32_t WRPR;
+} FLASH_TypeDef;
+
+/**
+ * @brief Option Bytes Registers
+ */
+
+typedef struct
+{
+ __IO uint16_t RDP;
+ __IO uint16_t USER;
+ __IO uint16_t Data0;
+ __IO uint16_t Data1;
+ __IO uint16_t WRP0;
+ __IO uint16_t WRP1;
+ __IO uint16_t WRP2;
+ __IO uint16_t WRP3;
+} OB_TypeDef;
+
+/**
+ * @brief Flexible Static Memory Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t BTCR[8];
+} FSMC_Bank1_TypeDef;
+
+/**
+ * @brief Flexible Static Memory Controller Bank1E
+ */
+
+typedef struct
+{
+ __IO uint32_t BWTR[7];
+} FSMC_Bank1E_TypeDef;
+
+/**
+ * @brief General Purpose I/O
+ */
+
+typedef struct
+{
+ __IO uint32_t CRL;
+ __IO uint32_t CRH;
+ __IO uint32_t IDR;
+ __IO uint32_t ODR;
+ __IO uint32_t BSRR;
+ __IO uint32_t BRR;
+ __IO uint32_t LCKR;
+} GPIO_TypeDef;
+
+/**
+ * @brief Alternate Function I/O
+ */
+
+typedef struct
+{
+ __IO uint32_t EVCR;
+ __IO uint32_t MAPR;
+ __IO uint32_t EXTICR[4];
+ uint32_t RESERVED0;
+ __IO uint32_t MAPR2;
+} AFIO_TypeDef;
+/**
+ * @brief Inter Integrated Circuit Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t CR1;
+ __IO uint32_t CR2;
+ __IO uint32_t OAR1;
+ __IO uint32_t OAR2;
+ __IO uint32_t DR;
+ __IO uint32_t SR1;
+ __IO uint32_t SR2;
+ __IO uint32_t CCR;
+ __IO uint32_t TRISE;
+} I2C_TypeDef;
+
+/**
+ * @brief Independent WATCHDOG
+ */
+
+typedef struct
+{
+ __IO uint32_t KR; /*!< Key register, Address offset: 0x00 */
+ __IO uint32_t PR; /*!< Prescaler register, Address offset: 0x04 */
+ __IO uint32_t RLR; /*!< Reload register, Address offset: 0x08 */
+ __IO uint32_t SR; /*!< Status register, Address offset: 0x0C */
+} IWDG_TypeDef;
+
+/**
+ * @brief Power Control
+ */
+
+typedef struct
+{
+ __IO uint32_t CR;
+ __IO uint32_t CSR;
+} PWR_TypeDef;
+
+/**
+ * @brief Reset and Clock Control
+ */
+
+typedef struct
+{
+ __IO uint32_t CR;
+ __IO uint32_t CFGR;
+ __IO uint32_t CIR;
+ __IO uint32_t APB2RSTR;
+ __IO uint32_t APB1RSTR;
+ __IO uint32_t AHBENR;
+ __IO uint32_t APB2ENR;
+ __IO uint32_t APB1ENR;
+ __IO uint32_t BDCR;
+ __IO uint32_t CSR;
+
+
+ uint32_t RESERVED0;
+ __IO uint32_t CFGR2;
+} RCC_TypeDef;
+
+/**
+ * @brief Real-Time Clock
+ */
+
+typedef struct
+{
+ __IO uint32_t CRH;
+ __IO uint32_t CRL;
+ __IO uint32_t PRLH;
+ __IO uint32_t PRLL;
+ __IO uint32_t DIVH;
+ __IO uint32_t DIVL;
+ __IO uint32_t CNTH;
+ __IO uint32_t CNTL;
+ __IO uint32_t ALRH;
+ __IO uint32_t ALRL;
+} RTC_TypeDef;
+
+/**
+ * @brief SD host Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t POWER;
+ __IO uint32_t CLKCR;
+ __IO uint32_t ARG;
+ __IO uint32_t CMD;
+ __I uint32_t RESPCMD;
+ __I uint32_t RESP1;
+ __I uint32_t RESP2;
+ __I uint32_t RESP3;
+ __I uint32_t RESP4;
+ __IO uint32_t DTIMER;
+ __IO uint32_t DLEN;
+ __IO uint32_t DCTRL;
+ __I uint32_t DCOUNT;
+ __I uint32_t STA;
+ __IO uint32_t ICR;
+ __IO uint32_t MASK;
+ uint32_t RESERVED0[2];
+ __I uint32_t FIFOCNT;
+ uint32_t RESERVED1[13];
+ __IO uint32_t FIFO;
+} SDIO_TypeDef;
+
+/**
+ * @brief Serial Peripheral Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t CR1;
+ __IO uint32_t CR2;
+ __IO uint32_t SR;
+ __IO uint32_t DR;
+ __IO uint32_t CRCPR;
+ __IO uint32_t RXCRCR;
+ __IO uint32_t TXCRCR;
+} SPI_TypeDef;
+
+/**
+ * @brief TIM Timers
+ */
+typedef struct
+{
+ __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
+ __IO uint32_t SMCR; /*!< TIM slave Mode Control register, Address offset: 0x08 */
+ __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
+ __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
+ __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
+ __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
+ __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
+ __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
+ __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
+ __IO uint32_t PSC; /*!< TIM prescaler register, Address offset: 0x28 */
+ __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
+ __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */
+ __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
+ __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
+ __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
+ __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
+ __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
+ __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
+ __IO uint32_t DMAR; /*!< TIM DMA address for full transfer register, Address offset: 0x4C */
+ __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */
+}TIM_TypeDef;
+
+
+/**
+ * @brief Universal Synchronous Asynchronous Receiver Transmitter
+ */
+
+typedef struct
+{
+ __IO uint32_t SR; /*!< USART Status register, Address offset: 0x00 */
+ __IO uint32_t DR; /*!< USART Data register, Address offset: 0x04 */
+ __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x08 */
+ __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x0C */
+ __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x10 */
+ __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x14 */
+ __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x18 */
+} USART_TypeDef;
+
+
+
+/**
+ * @brief Window WATCHDOG
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
+ __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
+ __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
+} WWDG_TypeDef;
+
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_memory_map
+ * @{
+ */
+
+
+#define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH base address in the alias region */
+#define FLASH_BANK1_END ((uint32_t)0x0807FFFF) /*!< FLASH END address of bank1 */
+#define SRAM_BASE ((uint32_t)0x20000000) /*!< SRAM base address in the alias region */
+#define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */
+
+#define SRAM_BB_BASE ((uint32_t)0x22000000) /*!< SRAM base address in the bit-band region */
+#define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */
+
+#define FSMC_BASE ((uint32_t)0x60000000) /*!< FSMC base address */
+#define FSMC_R_BASE ((uint32_t)0xA0000000) /*!< FSMC registers base address */
+
+/*!< Peripheral memory map */
+#define APB1PERIPH_BASE PERIPH_BASE
+#define APB2PERIPH_BASE (PERIPH_BASE + 0x10000)
+#define AHBPERIPH_BASE (PERIPH_BASE + 0x20000)
+
+#define TIM2_BASE (APB1PERIPH_BASE + 0x0000)
+#define TIM3_BASE (APB1PERIPH_BASE + 0x0400)
+#define TIM4_BASE (APB1PERIPH_BASE + 0x0800)
+#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00)
+#define TIM6_BASE (APB1PERIPH_BASE + 0x1000)
+#define TIM7_BASE (APB1PERIPH_BASE + 0x1400)
+#define TIM12_BASE (APB1PERIPH_BASE + 0x1800)
+#define TIM13_BASE (APB1PERIPH_BASE + 0x1C00)
+#define TIM14_BASE (APB1PERIPH_BASE + 0x2000)
+#define RTC_BASE (APB1PERIPH_BASE + 0x2800)
+#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00)
+#define IWDG_BASE (APB1PERIPH_BASE + 0x3000)
+#define SPI2_BASE (APB1PERIPH_BASE + 0x3800)
+#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00)
+#define USART2_BASE (APB1PERIPH_BASE + 0x4400)
+#define USART3_BASE (APB1PERIPH_BASE + 0x4800)
+#define UART4_BASE (APB1PERIPH_BASE + 0x4C00)
+#define UART5_BASE (APB1PERIPH_BASE + 0x5000)
+#define I2C1_BASE (APB1PERIPH_BASE + 0x5400)
+#define I2C2_BASE (APB1PERIPH_BASE + 0x5800)
+#define BKP_BASE (APB1PERIPH_BASE + 0x6C00)
+#define PWR_BASE (APB1PERIPH_BASE + 0x7000)
+#define DAC_BASE (APB1PERIPH_BASE + 0x7400)
+#define CEC_BASE (APB1PERIPH_BASE + 0x7800)
+#define AFIO_BASE (APB2PERIPH_BASE + 0x0000)
+#define EXTI_BASE (APB2PERIPH_BASE + 0x0400)
+#define GPIOA_BASE (APB2PERIPH_BASE + 0x0800)
+#define GPIOB_BASE (APB2PERIPH_BASE + 0x0C00)
+#define GPIOC_BASE (APB2PERIPH_BASE + 0x1000)
+#define GPIOD_BASE (APB2PERIPH_BASE + 0x1400)
+#define GPIOE_BASE (APB2PERIPH_BASE + 0x1800)
+#define GPIOF_BASE (APB2PERIPH_BASE + 0x1C00)
+#define GPIOG_BASE (APB2PERIPH_BASE + 0x2000)
+#define ADC1_BASE (APB2PERIPH_BASE + 0x2400)
+#define TIM1_BASE (APB2PERIPH_BASE + 0x2C00)
+#define SPI1_BASE (APB2PERIPH_BASE + 0x3000)
+#define USART1_BASE (APB2PERIPH_BASE + 0x3800)
+#define TIM15_BASE (APB2PERIPH_BASE + 0x4000)
+#define TIM16_BASE (APB2PERIPH_BASE + 0x4400)
+#define TIM17_BASE (APB2PERIPH_BASE + 0x4800)
+
+#define SDIO_BASE (PERIPH_BASE + 0x18000)
+
+#define DMA1_BASE (AHBPERIPH_BASE + 0x0000)
+#define DMA1_Channel1_BASE (AHBPERIPH_BASE + 0x0008)
+#define DMA1_Channel2_BASE (AHBPERIPH_BASE + 0x001C)
+#define DMA1_Channel3_BASE (AHBPERIPH_BASE + 0x0030)
+#define DMA1_Channel4_BASE (AHBPERIPH_BASE + 0x0044)
+#define DMA1_Channel5_BASE (AHBPERIPH_BASE + 0x0058)
+#define DMA1_Channel6_BASE (AHBPERIPH_BASE + 0x006C)
+#define DMA1_Channel7_BASE (AHBPERIPH_BASE + 0x0080)
+#define DMA2_BASE (AHBPERIPH_BASE + 0x0400)
+#define DMA2_Channel1_BASE (AHBPERIPH_BASE + 0x0408)
+#define DMA2_Channel2_BASE (AHBPERIPH_BASE + 0x041C)
+#define DMA2_Channel3_BASE (AHBPERIPH_BASE + 0x0430)
+#define DMA2_Channel4_BASE (AHBPERIPH_BASE + 0x0444)
+#define DMA2_Channel5_BASE (AHBPERIPH_BASE + 0x0458)
+#define RCC_BASE (AHBPERIPH_BASE + 0x1000)
+#define CRC_BASE (AHBPERIPH_BASE + 0x3000)
+
+#define FLASH_R_BASE (AHBPERIPH_BASE + 0x2000) /*!< Flash registers base address */
+#define FLASHSIZE_BASE ((uint32_t)0x1FFFF7E0) /*!< FLASH Size register base address */
+#define UID_BASE ((uint32_t)0x1FFFF7E8) /*!< Unique device ID register base address */
+#define OB_BASE ((uint32_t)0x1FFFF800) /*!< Flash Option Bytes base address */
+
+
+#define FSMC_BANK1 (FSMC_BASE) /*!< FSMC Bank1 base address */
+#define FSMC_BANK1_1 (FSMC_BANK1) /*!< FSMC Bank1_1 base address */
+#define FSMC_BANK1_2 (FSMC_BANK1 + 0x04000000) /*!< FSMC Bank1_2 base address */
+#define FSMC_BANK1_3 (FSMC_BANK1 + 0x08000000) /*!< FSMC Bank1_3 base address */
+#define FSMC_BANK1_4 (FSMC_BANK1 + 0x0C000000) /*!< FSMC Bank1_4 base address */
+
+
+#define FSMC_BANK1_R_BASE (FSMC_R_BASE + 0x0000) /*!< FSMC Bank1 registers base address */
+#define FSMC_BANK1E_R_BASE (FSMC_R_BASE + 0x0104) /*!< FSMC Bank1E registers base address */
+
+#define DBGMCU_BASE ((uint32_t)0xE0042000) /*!< Debug MCU registers base address */
+
+
+
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_declaration
+ * @{
+ */
+
+#define TIM2 ((TIM_TypeDef *) TIM2_BASE)
+#define TIM3 ((TIM_TypeDef *) TIM3_BASE)
+#define TIM4 ((TIM_TypeDef *) TIM4_BASE)
+#define TIM5 ((TIM_TypeDef *) TIM5_BASE)
+#define TIM6 ((TIM_TypeDef *) TIM6_BASE)
+#define TIM7 ((TIM_TypeDef *) TIM7_BASE)
+#define TIM12 ((TIM_TypeDef *) TIM12_BASE)
+#define TIM13 ((TIM_TypeDef *) TIM13_BASE)
+#define TIM14 ((TIM_TypeDef *) TIM14_BASE)
+#define RTC ((RTC_TypeDef *) RTC_BASE)
+#define WWDG ((WWDG_TypeDef *) WWDG_BASE)
+#define IWDG ((IWDG_TypeDef *) IWDG_BASE)
+#define SPI2 ((SPI_TypeDef *) SPI2_BASE)
+#define SPI3 ((SPI_TypeDef *) SPI3_BASE)
+#define USART2 ((USART_TypeDef *) USART2_BASE)
+#define USART3 ((USART_TypeDef *) USART3_BASE)
+#define UART4 ((USART_TypeDef *) UART4_BASE)
+#define UART5 ((USART_TypeDef *) UART5_BASE)
+#define I2C1 ((I2C_TypeDef *) I2C1_BASE)
+#define I2C2 ((I2C_TypeDef *) I2C2_BASE)
+#define BKP ((BKP_TypeDef *) BKP_BASE)
+#define PWR ((PWR_TypeDef *) PWR_BASE)
+#define DAC ((DAC_TypeDef *) DAC_BASE)
+#define CEC ((CEC_TypeDef *) CEC_BASE)
+#define AFIO ((AFIO_TypeDef *) AFIO_BASE)
+#define EXTI ((EXTI_TypeDef *) EXTI_BASE)
+#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
+#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
+#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
+#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
+#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
+#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
+#define GPIOG ((GPIO_TypeDef *) GPIOG_BASE)
+#define ADC1 ((ADC_TypeDef *) ADC1_BASE)
+#define ADC1_COMMON ((ADC_Common_TypeDef *) ADC1_BASE)
+#define TIM1 ((TIM_TypeDef *) TIM1_BASE)
+#define SPI1 ((SPI_TypeDef *) SPI1_BASE)
+#define USART1 ((USART_TypeDef *) USART1_BASE)
+#define TIM15 ((TIM_TypeDef *) TIM15_BASE)
+#define TIM16 ((TIM_TypeDef *) TIM16_BASE)
+#define TIM17 ((TIM_TypeDef *) TIM17_BASE)
+#define SDIO ((SDIO_TypeDef *) SDIO_BASE)
+#define DMA1 ((DMA_TypeDef *) DMA1_BASE)
+#define DMA2 ((DMA_TypeDef *) DMA2_BASE)
+#define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
+#define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
+#define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
+#define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
+#define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
+#define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
+#define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
+#define DMA2_Channel1 ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE)
+#define DMA2_Channel2 ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE)
+#define DMA2_Channel3 ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE)
+#define DMA2_Channel4 ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE)
+#define DMA2_Channel5 ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE)
+#define RCC ((RCC_TypeDef *) RCC_BASE)
+#define CRC ((CRC_TypeDef *) CRC_BASE)
+#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
+#define OB ((OB_TypeDef *) OB_BASE)
+#define FSMC_Bank1 ((FSMC_Bank1_TypeDef *) FSMC_BANK1_R_BASE)
+#define FSMC_Bank1E ((FSMC_Bank1E_TypeDef *) FSMC_BANK1E_R_BASE)
+#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
+
+
+/**
+ * @}
+ */
+
+/** @addtogroup Exported_constants
+ * @{
+ */
+
+ /** @addtogroup Peripheral_Registers_Bits_Definition
+ * @{
+ */
+
+/******************************************************************************/
+/* Peripheral Registers_Bits_Definition */
+/******************************************************************************/
+
+/******************************************************************************/
+/* */
+/* CRC calculation unit (CRC) */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for CRC_DR register *********************/
+#define CRC_DR_DR_Pos (0U)
+#define CRC_DR_DR_Msk (0xFFFFFFFFU << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */
+#define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */
+
+/******************* Bit definition for CRC_IDR register ********************/
+#define CRC_IDR_IDR_Pos (0U)
+#define CRC_IDR_IDR_Msk (0xFFU << CRC_IDR_IDR_Pos) /*!< 0x000000FF */
+#define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 8-bit data register bits */
+
+/******************** Bit definition for CRC_CR register ********************/
+#define CRC_CR_RESET_Pos (0U)
+#define CRC_CR_RESET_Msk (0x1U << CRC_CR_RESET_Pos) /*!< 0x00000001 */
+#define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET bit */
+
+/******************************************************************************/
+/* */
+/* Power Control */
+/* */
+/******************************************************************************/
+
+/******************** Bit definition for PWR_CR register ********************/
+#define PWR_CR_LPDS_Pos (0U)
+#define PWR_CR_LPDS_Msk (0x1U << PWR_CR_LPDS_Pos) /*!< 0x00000001 */
+#define PWR_CR_LPDS PWR_CR_LPDS_Msk /*!< Low-Power Deepsleep */
+#define PWR_CR_PDDS_Pos (1U)
+#define PWR_CR_PDDS_Msk (0x1U << PWR_CR_PDDS_Pos) /*!< 0x00000002 */
+#define PWR_CR_PDDS PWR_CR_PDDS_Msk /*!< Power Down Deepsleep */
+#define PWR_CR_CWUF_Pos (2U)
+#define PWR_CR_CWUF_Msk (0x1U << PWR_CR_CWUF_Pos) /*!< 0x00000004 */
+#define PWR_CR_CWUF PWR_CR_CWUF_Msk /*!< Clear Wakeup Flag */
+#define PWR_CR_CSBF_Pos (3U)
+#define PWR_CR_CSBF_Msk (0x1U << PWR_CR_CSBF_Pos) /*!< 0x00000008 */
+#define PWR_CR_CSBF PWR_CR_CSBF_Msk /*!< Clear Standby Flag */
+#define PWR_CR_PVDE_Pos (4U)
+#define PWR_CR_PVDE_Msk (0x1U << PWR_CR_PVDE_Pos) /*!< 0x00000010 */
+#define PWR_CR_PVDE PWR_CR_PVDE_Msk /*!< Power Voltage Detector Enable */
+
+#define PWR_CR_PLS_Pos (5U)
+#define PWR_CR_PLS_Msk (0x7U << PWR_CR_PLS_Pos) /*!< 0x000000E0 */
+#define PWR_CR_PLS PWR_CR_PLS_Msk /*!< PLS[2:0] bits (PVD Level Selection) */
+#define PWR_CR_PLS_0 (0x1U << PWR_CR_PLS_Pos) /*!< 0x00000020 */
+#define PWR_CR_PLS_1 (0x2U << PWR_CR_PLS_Pos) /*!< 0x00000040 */
+#define PWR_CR_PLS_2 (0x4U << PWR_CR_PLS_Pos) /*!< 0x00000080 */
+
+/*!< PVD level configuration */
+#define PWR_CR_PLS_2V2 ((uint32_t)0x00000000) /*!< PVD level 2.2V */
+#define PWR_CR_PLS_2V3 ((uint32_t)0x00000020) /*!< PVD level 2.3V */
+#define PWR_CR_PLS_2V4 ((uint32_t)0x00000040) /*!< PVD level 2.4V */
+#define PWR_CR_PLS_2V5 ((uint32_t)0x00000060) /*!< PVD level 2.5V */
+#define PWR_CR_PLS_2V6 ((uint32_t)0x00000080) /*!< PVD level 2.6V */
+#define PWR_CR_PLS_2V7 ((uint32_t)0x000000A0) /*!< PVD level 2.7V */
+#define PWR_CR_PLS_2V8 ((uint32_t)0x000000C0) /*!< PVD level 2.8V */
+#define PWR_CR_PLS_2V9 ((uint32_t)0x000000E0) /*!< PVD level 2.9V */
+
+#define PWR_CR_DBP_Pos (8U)
+#define PWR_CR_DBP_Msk (0x1U << PWR_CR_DBP_Pos) /*!< 0x00000100 */
+#define PWR_CR_DBP PWR_CR_DBP_Msk /*!< Disable Backup Domain write protection */
+
+
+/******************* Bit definition for PWR_CSR register ********************/
+#define PWR_CSR_WUF_Pos (0U)
+#define PWR_CSR_WUF_Msk (0x1U << PWR_CSR_WUF_Pos) /*!< 0x00000001 */
+#define PWR_CSR_WUF PWR_CSR_WUF_Msk /*!< Wakeup Flag */
+#define PWR_CSR_SBF_Pos (1U)
+#define PWR_CSR_SBF_Msk (0x1U << PWR_CSR_SBF_Pos) /*!< 0x00000002 */
+#define PWR_CSR_SBF PWR_CSR_SBF_Msk /*!< Standby Flag */
+#define PWR_CSR_PVDO_Pos (2U)
+#define PWR_CSR_PVDO_Msk (0x1U << PWR_CSR_PVDO_Pos) /*!< 0x00000004 */
+#define PWR_CSR_PVDO PWR_CSR_PVDO_Msk /*!< PVD Output */
+#define PWR_CSR_EWUP_Pos (8U)
+#define PWR_CSR_EWUP_Msk (0x1U << PWR_CSR_EWUP_Pos) /*!< 0x00000100 */
+#define PWR_CSR_EWUP PWR_CSR_EWUP_Msk /*!< Enable WKUP pin */
+
+/******************************************************************************/
+/* */
+/* Backup registers */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for BKP_DR1 register ********************/
+#define BKP_DR1_D_Pos (0U)
+#define BKP_DR1_D_Msk (0xFFFFU << BKP_DR1_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR1_D BKP_DR1_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR2 register ********************/
+#define BKP_DR2_D_Pos (0U)
+#define BKP_DR2_D_Msk (0xFFFFU << BKP_DR2_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR2_D BKP_DR2_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR3 register ********************/
+#define BKP_DR3_D_Pos (0U)
+#define BKP_DR3_D_Msk (0xFFFFU << BKP_DR3_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR3_D BKP_DR3_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR4 register ********************/
+#define BKP_DR4_D_Pos (0U)
+#define BKP_DR4_D_Msk (0xFFFFU << BKP_DR4_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR4_D BKP_DR4_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR5 register ********************/
+#define BKP_DR5_D_Pos (0U)
+#define BKP_DR5_D_Msk (0xFFFFU << BKP_DR5_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR5_D BKP_DR5_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR6 register ********************/
+#define BKP_DR6_D_Pos (0U)
+#define BKP_DR6_D_Msk (0xFFFFU << BKP_DR6_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR6_D BKP_DR6_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR7 register ********************/
+#define BKP_DR7_D_Pos (0U)
+#define BKP_DR7_D_Msk (0xFFFFU << BKP_DR7_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR7_D BKP_DR7_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR8 register ********************/
+#define BKP_DR8_D_Pos (0U)
+#define BKP_DR8_D_Msk (0xFFFFU << BKP_DR8_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR8_D BKP_DR8_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR9 register ********************/
+#define BKP_DR9_D_Pos (0U)
+#define BKP_DR9_D_Msk (0xFFFFU << BKP_DR9_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR9_D BKP_DR9_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR10 register *******************/
+#define BKP_DR10_D_Pos (0U)
+#define BKP_DR10_D_Msk (0xFFFFU << BKP_DR10_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR10_D BKP_DR10_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR11 register *******************/
+#define BKP_DR11_D_Pos (0U)
+#define BKP_DR11_D_Msk (0xFFFFU << BKP_DR11_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR11_D BKP_DR11_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR12 register *******************/
+#define BKP_DR12_D_Pos (0U)
+#define BKP_DR12_D_Msk (0xFFFFU << BKP_DR12_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR12_D BKP_DR12_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR13 register *******************/
+#define BKP_DR13_D_Pos (0U)
+#define BKP_DR13_D_Msk (0xFFFFU << BKP_DR13_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR13_D BKP_DR13_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR14 register *******************/
+#define BKP_DR14_D_Pos (0U)
+#define BKP_DR14_D_Msk (0xFFFFU << BKP_DR14_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR14_D BKP_DR14_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR15 register *******************/
+#define BKP_DR15_D_Pos (0U)
+#define BKP_DR15_D_Msk (0xFFFFU << BKP_DR15_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR15_D BKP_DR15_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR16 register *******************/
+#define BKP_DR16_D_Pos (0U)
+#define BKP_DR16_D_Msk (0xFFFFU << BKP_DR16_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR16_D BKP_DR16_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR17 register *******************/
+#define BKP_DR17_D_Pos (0U)
+#define BKP_DR17_D_Msk (0xFFFFU << BKP_DR17_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR17_D BKP_DR17_D_Msk /*!< Backup data */
+
+/****************** Bit definition for BKP_DR18 register ********************/
+#define BKP_DR18_D_Pos (0U)
+#define BKP_DR18_D_Msk (0xFFFFU << BKP_DR18_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR18_D BKP_DR18_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR19 register *******************/
+#define BKP_DR19_D_Pos (0U)
+#define BKP_DR19_D_Msk (0xFFFFU << BKP_DR19_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR19_D BKP_DR19_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR20 register *******************/
+#define BKP_DR20_D_Pos (0U)
+#define BKP_DR20_D_Msk (0xFFFFU << BKP_DR20_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR20_D BKP_DR20_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR21 register *******************/
+#define BKP_DR21_D_Pos (0U)
+#define BKP_DR21_D_Msk (0xFFFFU << BKP_DR21_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR21_D BKP_DR21_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR22 register *******************/
+#define BKP_DR22_D_Pos (0U)
+#define BKP_DR22_D_Msk (0xFFFFU << BKP_DR22_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR22_D BKP_DR22_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR23 register *******************/
+#define BKP_DR23_D_Pos (0U)
+#define BKP_DR23_D_Msk (0xFFFFU << BKP_DR23_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR23_D BKP_DR23_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR24 register *******************/
+#define BKP_DR24_D_Pos (0U)
+#define BKP_DR24_D_Msk (0xFFFFU << BKP_DR24_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR24_D BKP_DR24_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR25 register *******************/
+#define BKP_DR25_D_Pos (0U)
+#define BKP_DR25_D_Msk (0xFFFFU << BKP_DR25_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR25_D BKP_DR25_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR26 register *******************/
+#define BKP_DR26_D_Pos (0U)
+#define BKP_DR26_D_Msk (0xFFFFU << BKP_DR26_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR26_D BKP_DR26_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR27 register *******************/
+#define BKP_DR27_D_Pos (0U)
+#define BKP_DR27_D_Msk (0xFFFFU << BKP_DR27_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR27_D BKP_DR27_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR28 register *******************/
+#define BKP_DR28_D_Pos (0U)
+#define BKP_DR28_D_Msk (0xFFFFU << BKP_DR28_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR28_D BKP_DR28_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR29 register *******************/
+#define BKP_DR29_D_Pos (0U)
+#define BKP_DR29_D_Msk (0xFFFFU << BKP_DR29_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR29_D BKP_DR29_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR30 register *******************/
+#define BKP_DR30_D_Pos (0U)
+#define BKP_DR30_D_Msk (0xFFFFU << BKP_DR30_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR30_D BKP_DR30_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR31 register *******************/
+#define BKP_DR31_D_Pos (0U)
+#define BKP_DR31_D_Msk (0xFFFFU << BKP_DR31_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR31_D BKP_DR31_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR32 register *******************/
+#define BKP_DR32_D_Pos (0U)
+#define BKP_DR32_D_Msk (0xFFFFU << BKP_DR32_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR32_D BKP_DR32_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR33 register *******************/
+#define BKP_DR33_D_Pos (0U)
+#define BKP_DR33_D_Msk (0xFFFFU << BKP_DR33_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR33_D BKP_DR33_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR34 register *******************/
+#define BKP_DR34_D_Pos (0U)
+#define BKP_DR34_D_Msk (0xFFFFU << BKP_DR34_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR34_D BKP_DR34_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR35 register *******************/
+#define BKP_DR35_D_Pos (0U)
+#define BKP_DR35_D_Msk (0xFFFFU << BKP_DR35_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR35_D BKP_DR35_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR36 register *******************/
+#define BKP_DR36_D_Pos (0U)
+#define BKP_DR36_D_Msk (0xFFFFU << BKP_DR36_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR36_D BKP_DR36_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR37 register *******************/
+#define BKP_DR37_D_Pos (0U)
+#define BKP_DR37_D_Msk (0xFFFFU << BKP_DR37_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR37_D BKP_DR37_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR38 register *******************/
+#define BKP_DR38_D_Pos (0U)
+#define BKP_DR38_D_Msk (0xFFFFU << BKP_DR38_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR38_D BKP_DR38_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR39 register *******************/
+#define BKP_DR39_D_Pos (0U)
+#define BKP_DR39_D_Msk (0xFFFFU << BKP_DR39_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR39_D BKP_DR39_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR40 register *******************/
+#define BKP_DR40_D_Pos (0U)
+#define BKP_DR40_D_Msk (0xFFFFU << BKP_DR40_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR40_D BKP_DR40_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR41 register *******************/
+#define BKP_DR41_D_Pos (0U)
+#define BKP_DR41_D_Msk (0xFFFFU << BKP_DR41_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR41_D BKP_DR41_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR42 register *******************/
+#define BKP_DR42_D_Pos (0U)
+#define BKP_DR42_D_Msk (0xFFFFU << BKP_DR42_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR42_D BKP_DR42_D_Msk /*!< Backup data */
+
+#define RTC_BKP_NUMBER 42
+
+/****************** Bit definition for BKP_RTCCR register *******************/
+#define BKP_RTCCR_CAL_Pos (0U)
+#define BKP_RTCCR_CAL_Msk (0x7FU << BKP_RTCCR_CAL_Pos) /*!< 0x0000007F */
+#define BKP_RTCCR_CAL BKP_RTCCR_CAL_Msk /*!< Calibration value */
+#define BKP_RTCCR_CCO_Pos (7U)
+#define BKP_RTCCR_CCO_Msk (0x1U << BKP_RTCCR_CCO_Pos) /*!< 0x00000080 */
+#define BKP_RTCCR_CCO BKP_RTCCR_CCO_Msk /*!< Calibration Clock Output */
+#define BKP_RTCCR_ASOE_Pos (8U)
+#define BKP_RTCCR_ASOE_Msk (0x1U << BKP_RTCCR_ASOE_Pos) /*!< 0x00000100 */
+#define BKP_RTCCR_ASOE BKP_RTCCR_ASOE_Msk /*!< Alarm or Second Output Enable */
+#define BKP_RTCCR_ASOS_Pos (9U)
+#define BKP_RTCCR_ASOS_Msk (0x1U << BKP_RTCCR_ASOS_Pos) /*!< 0x00000200 */
+#define BKP_RTCCR_ASOS BKP_RTCCR_ASOS_Msk /*!< Alarm or Second Output Selection */
+
+/******************** Bit definition for BKP_CR register ********************/
+#define BKP_CR_TPE_Pos (0U)
+#define BKP_CR_TPE_Msk (0x1U << BKP_CR_TPE_Pos) /*!< 0x00000001 */
+#define BKP_CR_TPE BKP_CR_TPE_Msk /*!< TAMPER pin enable */
+#define BKP_CR_TPAL_Pos (1U)
+#define BKP_CR_TPAL_Msk (0x1U << BKP_CR_TPAL_Pos) /*!< 0x00000002 */
+#define BKP_CR_TPAL BKP_CR_TPAL_Msk /*!< TAMPER pin active level */
+
+/******************* Bit definition for BKP_CSR register ********************/
+#define BKP_CSR_CTE_Pos (0U)
+#define BKP_CSR_CTE_Msk (0x1U << BKP_CSR_CTE_Pos) /*!< 0x00000001 */
+#define BKP_CSR_CTE BKP_CSR_CTE_Msk /*!< Clear Tamper event */
+#define BKP_CSR_CTI_Pos (1U)
+#define BKP_CSR_CTI_Msk (0x1U << BKP_CSR_CTI_Pos) /*!< 0x00000002 */
+#define BKP_CSR_CTI BKP_CSR_CTI_Msk /*!< Clear Tamper Interrupt */
+#define BKP_CSR_TPIE_Pos (2U)
+#define BKP_CSR_TPIE_Msk (0x1U << BKP_CSR_TPIE_Pos) /*!< 0x00000004 */
+#define BKP_CSR_TPIE BKP_CSR_TPIE_Msk /*!< TAMPER Pin interrupt enable */
+#define BKP_CSR_TEF_Pos (8U)
+#define BKP_CSR_TEF_Msk (0x1U << BKP_CSR_TEF_Pos) /*!< 0x00000100 */
+#define BKP_CSR_TEF BKP_CSR_TEF_Msk /*!< Tamper Event Flag */
+#define BKP_CSR_TIF_Pos (9U)
+#define BKP_CSR_TIF_Msk (0x1U << BKP_CSR_TIF_Pos) /*!< 0x00000200 */
+#define BKP_CSR_TIF BKP_CSR_TIF_Msk /*!< Tamper Interrupt Flag */
+
+/******************************************************************************/
+/* */
+/* Reset and Clock Control */
+/* */
+/******************************************************************************/
+
+/******************** Bit definition for RCC_CR register ********************/
+#define RCC_CR_HSION_Pos (0U)
+#define RCC_CR_HSION_Msk (0x1U << RCC_CR_HSION_Pos) /*!< 0x00000001 */
+#define RCC_CR_HSION RCC_CR_HSION_Msk /*!< Internal High Speed clock enable */
+#define RCC_CR_HSIRDY_Pos (1U)
+#define RCC_CR_HSIRDY_Msk (0x1U << RCC_CR_HSIRDY_Pos) /*!< 0x00000002 */
+#define RCC_CR_HSIRDY RCC_CR_HSIRDY_Msk /*!< Internal High Speed clock ready flag */
+#define RCC_CR_HSITRIM_Pos (3U)
+#define RCC_CR_HSITRIM_Msk (0x1FU << RCC_CR_HSITRIM_Pos) /*!< 0x000000F8 */
+#define RCC_CR_HSITRIM RCC_CR_HSITRIM_Msk /*!< Internal High Speed clock trimming */
+#define RCC_CR_HSICAL_Pos (8U)
+#define RCC_CR_HSICAL_Msk (0xFFU << RCC_CR_HSICAL_Pos) /*!< 0x0000FF00 */
+#define RCC_CR_HSICAL RCC_CR_HSICAL_Msk /*!< Internal High Speed clock Calibration */
+#define RCC_CR_HSEON_Pos (16U)
+#define RCC_CR_HSEON_Msk (0x1U << RCC_CR_HSEON_Pos) /*!< 0x00010000 */
+#define RCC_CR_HSEON RCC_CR_HSEON_Msk /*!< External High Speed clock enable */
+#define RCC_CR_HSERDY_Pos (17U)
+#define RCC_CR_HSERDY_Msk (0x1U << RCC_CR_HSERDY_Pos) /*!< 0x00020000 */
+#define RCC_CR_HSERDY RCC_CR_HSERDY_Msk /*!< External High Speed clock ready flag */
+#define RCC_CR_HSEBYP_Pos (18U)
+#define RCC_CR_HSEBYP_Msk (0x1U << RCC_CR_HSEBYP_Pos) /*!< 0x00040000 */
+#define RCC_CR_HSEBYP RCC_CR_HSEBYP_Msk /*!< External High Speed clock Bypass */
+#define RCC_CR_CSSON_Pos (19U)
+#define RCC_CR_CSSON_Msk (0x1U << RCC_CR_CSSON_Pos) /*!< 0x00080000 */
+#define RCC_CR_CSSON RCC_CR_CSSON_Msk /*!< Clock Security System enable */
+#define RCC_CR_PLLON_Pos (24U)
+#define RCC_CR_PLLON_Msk (0x1U << RCC_CR_PLLON_Pos) /*!< 0x01000000 */
+#define RCC_CR_PLLON RCC_CR_PLLON_Msk /*!< PLL enable */
+#define RCC_CR_PLLRDY_Pos (25U)
+#define RCC_CR_PLLRDY_Msk (0x1U << RCC_CR_PLLRDY_Pos) /*!< 0x02000000 */
+#define RCC_CR_PLLRDY RCC_CR_PLLRDY_Msk /*!< PLL clock ready flag */
+
+
+/******************* Bit definition for RCC_CFGR register *******************/
+/*!< SW configuration */
+#define RCC_CFGR_SW_Pos (0U)
+#define RCC_CFGR_SW_Msk (0x3U << RCC_CFGR_SW_Pos) /*!< 0x00000003 */
+#define RCC_CFGR_SW RCC_CFGR_SW_Msk /*!< SW[1:0] bits (System clock Switch) */
+#define RCC_CFGR_SW_0 (0x1U << RCC_CFGR_SW_Pos) /*!< 0x00000001 */
+#define RCC_CFGR_SW_1 (0x2U << RCC_CFGR_SW_Pos) /*!< 0x00000002 */
+
+#define RCC_CFGR_SW_HSI ((uint32_t)0x00000000) /*!< HSI selected as system clock */
+#define RCC_CFGR_SW_HSE ((uint32_t)0x00000001) /*!< HSE selected as system clock */
+#define RCC_CFGR_SW_PLL ((uint32_t)0x00000002) /*!< PLL selected as system clock */
+
+/*!< SWS configuration */
+#define RCC_CFGR_SWS_Pos (2U)
+#define RCC_CFGR_SWS_Msk (0x3U << RCC_CFGR_SWS_Pos) /*!< 0x0000000C */
+#define RCC_CFGR_SWS RCC_CFGR_SWS_Msk /*!< SWS[1:0] bits (System Clock Switch Status) */
+#define RCC_CFGR_SWS_0 (0x1U << RCC_CFGR_SWS_Pos) /*!< 0x00000004 */
+#define RCC_CFGR_SWS_1 (0x2U << RCC_CFGR_SWS_Pos) /*!< 0x00000008 */
+
+#define RCC_CFGR_SWS_HSI ((uint32_t)0x00000000) /*!< HSI oscillator used as system clock */
+#define RCC_CFGR_SWS_HSE ((uint32_t)0x00000004) /*!< HSE oscillator used as system clock */
+#define RCC_CFGR_SWS_PLL ((uint32_t)0x00000008) /*!< PLL used as system clock */
+
+/*!< HPRE configuration */
+#define RCC_CFGR_HPRE_Pos (4U)
+#define RCC_CFGR_HPRE_Msk (0xFU << RCC_CFGR_HPRE_Pos) /*!< 0x000000F0 */
+#define RCC_CFGR_HPRE RCC_CFGR_HPRE_Msk /*!< HPRE[3:0] bits (AHB prescaler) */
+#define RCC_CFGR_HPRE_0 (0x1U << RCC_CFGR_HPRE_Pos) /*!< 0x00000010 */
+#define RCC_CFGR_HPRE_1 (0x2U << RCC_CFGR_HPRE_Pos) /*!< 0x00000020 */
+#define RCC_CFGR_HPRE_2 (0x4U << RCC_CFGR_HPRE_Pos) /*!< 0x00000040 */
+#define RCC_CFGR_HPRE_3 (0x8U << RCC_CFGR_HPRE_Pos) /*!< 0x00000080 */
+
+#define RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000) /*!< SYSCLK not divided */
+#define RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080) /*!< SYSCLK divided by 2 */
+#define RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090) /*!< SYSCLK divided by 4 */
+#define RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0) /*!< SYSCLK divided by 8 */
+#define RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0) /*!< SYSCLK divided by 16 */
+#define RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0) /*!< SYSCLK divided by 64 */
+#define RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0) /*!< SYSCLK divided by 128 */
+#define RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0) /*!< SYSCLK divided by 256 */
+#define RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0) /*!< SYSCLK divided by 512 */
+
+/*!< PPRE1 configuration */
+#define RCC_CFGR_PPRE1_Pos (8U)
+#define RCC_CFGR_PPRE1_Msk (0x7U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000700 */
+#define RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_Msk /*!< PRE1[2:0] bits (APB1 prescaler) */
+#define RCC_CFGR_PPRE1_0 (0x1U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000100 */
+#define RCC_CFGR_PPRE1_1 (0x2U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000200 */
+#define RCC_CFGR_PPRE1_2 (0x4U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000400 */
+
+#define RCC_CFGR_PPRE1_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */
+#define RCC_CFGR_PPRE1_DIV2 ((uint32_t)0x00000400) /*!< HCLK divided by 2 */
+#define RCC_CFGR_PPRE1_DIV4 ((uint32_t)0x00000500) /*!< HCLK divided by 4 */
+#define RCC_CFGR_PPRE1_DIV8 ((uint32_t)0x00000600) /*!< HCLK divided by 8 */
+#define RCC_CFGR_PPRE1_DIV16 ((uint32_t)0x00000700) /*!< HCLK divided by 16 */
+
+/*!< PPRE2 configuration */
+#define RCC_CFGR_PPRE2_Pos (11U)
+#define RCC_CFGR_PPRE2_Msk (0x7U << RCC_CFGR_PPRE2_Pos) /*!< 0x00003800 */
+#define RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_Msk /*!< PRE2[2:0] bits (APB2 prescaler) */
+#define RCC_CFGR_PPRE2_0 (0x1U << RCC_CFGR_PPRE2_Pos) /*!< 0x00000800 */
+#define RCC_CFGR_PPRE2_1 (0x2U << RCC_CFGR_PPRE2_Pos) /*!< 0x00001000 */
+#define RCC_CFGR_PPRE2_2 (0x4U << RCC_CFGR_PPRE2_Pos) /*!< 0x00002000 */
+
+#define RCC_CFGR_PPRE2_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */
+#define RCC_CFGR_PPRE2_DIV2 ((uint32_t)0x00002000) /*!< HCLK divided by 2 */
+#define RCC_CFGR_PPRE2_DIV4 ((uint32_t)0x00002800) /*!< HCLK divided by 4 */
+#define RCC_CFGR_PPRE2_DIV8 ((uint32_t)0x00003000) /*!< HCLK divided by 8 */
+#define RCC_CFGR_PPRE2_DIV16 ((uint32_t)0x00003800) /*!< HCLK divided by 16 */
+
+/*!< ADCPPRE configuration */
+#define RCC_CFGR_ADCPRE_Pos (14U)
+#define RCC_CFGR_ADCPRE_Msk (0x3U << RCC_CFGR_ADCPRE_Pos) /*!< 0x0000C000 */
+#define RCC_CFGR_ADCPRE RCC_CFGR_ADCPRE_Msk /*!< ADCPRE[1:0] bits (ADC prescaler) */
+#define RCC_CFGR_ADCPRE_0 (0x1U << RCC_CFGR_ADCPRE_Pos) /*!< 0x00004000 */
+#define RCC_CFGR_ADCPRE_1 (0x2U << RCC_CFGR_ADCPRE_Pos) /*!< 0x00008000 */
+
+#define RCC_CFGR_ADCPRE_DIV2 ((uint32_t)0x00000000) /*!< PCLK2 divided by 2 */
+#define RCC_CFGR_ADCPRE_DIV4 ((uint32_t)0x00004000) /*!< PCLK2 divided by 4 */
+#define RCC_CFGR_ADCPRE_DIV6 ((uint32_t)0x00008000) /*!< PCLK2 divided by 6 */
+#define RCC_CFGR_ADCPRE_DIV8 ((uint32_t)0x0000C000) /*!< PCLK2 divided by 8 */
+
+#define RCC_CFGR_PLLSRC_Pos (16U)
+#define RCC_CFGR_PLLSRC_Msk (0x1U << RCC_CFGR_PLLSRC_Pos) /*!< 0x00010000 */
+#define RCC_CFGR_PLLSRC RCC_CFGR_PLLSRC_Msk /*!< PLL entry clock source */
+
+#define RCC_CFGR_PLLXTPRE_Pos (17U)
+#define RCC_CFGR_PLLXTPRE_Msk (0x1U << RCC_CFGR_PLLXTPRE_Pos) /*!< 0x00020000 */
+#define RCC_CFGR_PLLXTPRE RCC_CFGR_PLLXTPRE_Msk /*!< HSE divider for PLL entry */
+
+/*!< PLLMUL configuration */
+#define RCC_CFGR_PLLMULL_Pos (18U)
+#define RCC_CFGR_PLLMULL_Msk (0xFU << RCC_CFGR_PLLMULL_Pos) /*!< 0x003C0000 */
+#define RCC_CFGR_PLLMULL RCC_CFGR_PLLMULL_Msk /*!< PLLMUL[3:0] bits (PLL multiplication factor) */
+#define RCC_CFGR_PLLMULL_0 (0x1U << RCC_CFGR_PLLMULL_Pos) /*!< 0x00040000 */
+#define RCC_CFGR_PLLMULL_1 (0x2U << RCC_CFGR_PLLMULL_Pos) /*!< 0x00080000 */
+#define RCC_CFGR_PLLMULL_2 (0x4U << RCC_CFGR_PLLMULL_Pos) /*!< 0x00100000 */
+#define RCC_CFGR_PLLMULL_3 (0x8U << RCC_CFGR_PLLMULL_Pos) /*!< 0x00200000 */
+
+#define RCC_CFGR_PLLXTPRE_PREDIV1 ((uint32_t)0x00000000) /*!< PREDIV1 clock not divided for PLL entry */
+#define RCC_CFGR_PLLXTPRE_PREDIV1_DIV2 ((uint32_t)0x00020000) /*!< PREDIV1 clock divided by 2 for PLL entry */
+
+#define RCC_CFGR_PLLMULL2 ((uint32_t)0x00000000) /*!< PLL input clock*2 */
+#define RCC_CFGR_PLLMULL3_Pos (18U)
+#define RCC_CFGR_PLLMULL3_Msk (0x1U << RCC_CFGR_PLLMULL3_Pos) /*!< 0x00040000 */
+#define RCC_CFGR_PLLMULL3 RCC_CFGR_PLLMULL3_Msk /*!< PLL input clock*3 */
+#define RCC_CFGR_PLLMULL4_Pos (19U)
+#define RCC_CFGR_PLLMULL4_Msk (0x1U << RCC_CFGR_PLLMULL4_Pos) /*!< 0x00080000 */
+#define RCC_CFGR_PLLMULL4 RCC_CFGR_PLLMULL4_Msk /*!< PLL input clock*4 */
+#define RCC_CFGR_PLLMULL5_Pos (18U)
+#define RCC_CFGR_PLLMULL5_Msk (0x3U << RCC_CFGR_PLLMULL5_Pos) /*!< 0x000C0000 */
+#define RCC_CFGR_PLLMULL5 RCC_CFGR_PLLMULL5_Msk /*!< PLL input clock*5 */
+#define RCC_CFGR_PLLMULL6_Pos (20U)
+#define RCC_CFGR_PLLMULL6_Msk (0x1U << RCC_CFGR_PLLMULL6_Pos) /*!< 0x00100000 */
+#define RCC_CFGR_PLLMULL6 RCC_CFGR_PLLMULL6_Msk /*!< PLL input clock*6 */
+#define RCC_CFGR_PLLMULL7_Pos (18U)
+#define RCC_CFGR_PLLMULL7_Msk (0x5U << RCC_CFGR_PLLMULL7_Pos) /*!< 0x00140000 */
+#define RCC_CFGR_PLLMULL7 RCC_CFGR_PLLMULL7_Msk /*!< PLL input clock*7 */
+#define RCC_CFGR_PLLMULL8_Pos (19U)
+#define RCC_CFGR_PLLMULL8_Msk (0x3U << RCC_CFGR_PLLMULL8_Pos) /*!< 0x00180000 */
+#define RCC_CFGR_PLLMULL8 RCC_CFGR_PLLMULL8_Msk /*!< PLL input clock*8 */
+#define RCC_CFGR_PLLMULL9_Pos (18U)
+#define RCC_CFGR_PLLMULL9_Msk (0x7U << RCC_CFGR_PLLMULL9_Pos) /*!< 0x001C0000 */
+#define RCC_CFGR_PLLMULL9 RCC_CFGR_PLLMULL9_Msk /*!< PLL input clock*9 */
+#define RCC_CFGR_PLLMULL10_Pos (21U)
+#define RCC_CFGR_PLLMULL10_Msk (0x1U << RCC_CFGR_PLLMULL10_Pos) /*!< 0x00200000 */
+#define RCC_CFGR_PLLMULL10 RCC_CFGR_PLLMULL10_Msk /*!< PLL input clock10 */
+#define RCC_CFGR_PLLMULL11_Pos (18U)
+#define RCC_CFGR_PLLMULL11_Msk (0x9U << RCC_CFGR_PLLMULL11_Pos) /*!< 0x00240000 */
+#define RCC_CFGR_PLLMULL11 RCC_CFGR_PLLMULL11_Msk /*!< PLL input clock*11 */
+#define RCC_CFGR_PLLMULL12_Pos (19U)
+#define RCC_CFGR_PLLMULL12_Msk (0x5U << RCC_CFGR_PLLMULL12_Pos) /*!< 0x00280000 */
+#define RCC_CFGR_PLLMULL12 RCC_CFGR_PLLMULL12_Msk /*!< PLL input clock*12 */
+#define RCC_CFGR_PLLMULL13_Pos (18U)
+#define RCC_CFGR_PLLMULL13_Msk (0xBU << RCC_CFGR_PLLMULL13_Pos) /*!< 0x002C0000 */
+#define RCC_CFGR_PLLMULL13 RCC_CFGR_PLLMULL13_Msk /*!< PLL input clock*13 */
+#define RCC_CFGR_PLLMULL14_Pos (20U)
+#define RCC_CFGR_PLLMULL14_Msk (0x3U << RCC_CFGR_PLLMULL14_Pos) /*!< 0x00300000 */
+#define RCC_CFGR_PLLMULL14 RCC_CFGR_PLLMULL14_Msk /*!< PLL input clock*14 */
+#define RCC_CFGR_PLLMULL15_Pos (18U)
+#define RCC_CFGR_PLLMULL15_Msk (0xDU << RCC_CFGR_PLLMULL15_Pos) /*!< 0x00340000 */
+#define RCC_CFGR_PLLMULL15 RCC_CFGR_PLLMULL15_Msk /*!< PLL input clock*15 */
+#define RCC_CFGR_PLLMULL16_Pos (19U)
+#define RCC_CFGR_PLLMULL16_Msk (0x7U << RCC_CFGR_PLLMULL16_Pos) /*!< 0x00380000 */
+#define RCC_CFGR_PLLMULL16 RCC_CFGR_PLLMULL16_Msk /*!< PLL input clock*16 */
+
+/*!< MCO configuration */
+#define RCC_CFGR_MCO_Pos (24U)
+#define RCC_CFGR_MCO_Msk (0x7U << RCC_CFGR_MCO_Pos) /*!< 0x07000000 */
+#define RCC_CFGR_MCO RCC_CFGR_MCO_Msk /*!< MCO[2:0] bits (Microcontroller Clock Output) */
+#define RCC_CFGR_MCO_0 (0x1U << RCC_CFGR_MCO_Pos) /*!< 0x01000000 */
+#define RCC_CFGR_MCO_1 (0x2U << RCC_CFGR_MCO_Pos) /*!< 0x02000000 */
+#define RCC_CFGR_MCO_2 (0x4U << RCC_CFGR_MCO_Pos) /*!< 0x04000000 */
+
+#define RCC_CFGR_MCO_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */
+#define RCC_CFGR_MCO_SYSCLK ((uint32_t)0x04000000) /*!< System clock selected as MCO source */
+#define RCC_CFGR_MCO_HSI ((uint32_t)0x05000000) /*!< HSI clock selected as MCO source */
+#define RCC_CFGR_MCO_HSE ((uint32_t)0x06000000) /*!< HSE clock selected as MCO source */
+#define RCC_CFGR_MCO_PLLCLK_DIV2 ((uint32_t)0x07000000) /*!< PLL clock divided by 2 selected as MCO source */
+
+ /* Reference defines */
+ #define RCC_CFGR_MCOSEL RCC_CFGR_MCO
+ #define RCC_CFGR_MCOSEL_0 RCC_CFGR_MCO_0
+ #define RCC_CFGR_MCOSEL_1 RCC_CFGR_MCO_1
+ #define RCC_CFGR_MCOSEL_2 RCC_CFGR_MCO_2
+ #define RCC_CFGR_MCOSEL_NOCLOCK RCC_CFGR_MCO_NOCLOCK
+ #define RCC_CFGR_MCOSEL_SYSCLK RCC_CFGR_MCO_SYSCLK
+ #define RCC_CFGR_MCOSEL_HSI RCC_CFGR_MCO_HSI
+ #define RCC_CFGR_MCOSEL_HSE RCC_CFGR_MCO_HSE
+ #define RCC_CFGR_MCOSEL_PLL_DIV2 RCC_CFGR_MCO_PLLCLK_DIV2
+
+/*!<****************** Bit definition for RCC_CIR register ********************/
+#define RCC_CIR_LSIRDYF_Pos (0U)
+#define RCC_CIR_LSIRDYF_Msk (0x1U << RCC_CIR_LSIRDYF_Pos) /*!< 0x00000001 */
+#define RCC_CIR_LSIRDYF RCC_CIR_LSIRDYF_Msk /*!< LSI Ready Interrupt flag */
+#define RCC_CIR_LSERDYF_Pos (1U)
+#define RCC_CIR_LSERDYF_Msk (0x1U << RCC_CIR_LSERDYF_Pos) /*!< 0x00000002 */
+#define RCC_CIR_LSERDYF RCC_CIR_LSERDYF_Msk /*!< LSE Ready Interrupt flag */
+#define RCC_CIR_HSIRDYF_Pos (2U)
+#define RCC_CIR_HSIRDYF_Msk (0x1U << RCC_CIR_HSIRDYF_Pos) /*!< 0x00000004 */
+#define RCC_CIR_HSIRDYF RCC_CIR_HSIRDYF_Msk /*!< HSI Ready Interrupt flag */
+#define RCC_CIR_HSERDYF_Pos (3U)
+#define RCC_CIR_HSERDYF_Msk (0x1U << RCC_CIR_HSERDYF_Pos) /*!< 0x00000008 */
+#define RCC_CIR_HSERDYF RCC_CIR_HSERDYF_Msk /*!< HSE Ready Interrupt flag */
+#define RCC_CIR_PLLRDYF_Pos (4U)
+#define RCC_CIR_PLLRDYF_Msk (0x1U << RCC_CIR_PLLRDYF_Pos) /*!< 0x00000010 */
+#define RCC_CIR_PLLRDYF RCC_CIR_PLLRDYF_Msk /*!< PLL Ready Interrupt flag */
+#define RCC_CIR_CSSF_Pos (7U)
+#define RCC_CIR_CSSF_Msk (0x1U << RCC_CIR_CSSF_Pos) /*!< 0x00000080 */
+#define RCC_CIR_CSSF RCC_CIR_CSSF_Msk /*!< Clock Security System Interrupt flag */
+#define RCC_CIR_LSIRDYIE_Pos (8U)
+#define RCC_CIR_LSIRDYIE_Msk (0x1U << RCC_CIR_LSIRDYIE_Pos) /*!< 0x00000100 */
+#define RCC_CIR_LSIRDYIE RCC_CIR_LSIRDYIE_Msk /*!< LSI Ready Interrupt Enable */
+#define RCC_CIR_LSERDYIE_Pos (9U)
+#define RCC_CIR_LSERDYIE_Msk (0x1U << RCC_CIR_LSERDYIE_Pos) /*!< 0x00000200 */
+#define RCC_CIR_LSERDYIE RCC_CIR_LSERDYIE_Msk /*!< LSE Ready Interrupt Enable */
+#define RCC_CIR_HSIRDYIE_Pos (10U)
+#define RCC_CIR_HSIRDYIE_Msk (0x1U << RCC_CIR_HSIRDYIE_Pos) /*!< 0x00000400 */
+#define RCC_CIR_HSIRDYIE RCC_CIR_HSIRDYIE_Msk /*!< HSI Ready Interrupt Enable */
+#define RCC_CIR_HSERDYIE_Pos (11U)
+#define RCC_CIR_HSERDYIE_Msk (0x1U << RCC_CIR_HSERDYIE_Pos) /*!< 0x00000800 */
+#define RCC_CIR_HSERDYIE RCC_CIR_HSERDYIE_Msk /*!< HSE Ready Interrupt Enable */
+#define RCC_CIR_PLLRDYIE_Pos (12U)
+#define RCC_CIR_PLLRDYIE_Msk (0x1U << RCC_CIR_PLLRDYIE_Pos) /*!< 0x00001000 */
+#define RCC_CIR_PLLRDYIE RCC_CIR_PLLRDYIE_Msk /*!< PLL Ready Interrupt Enable */
+#define RCC_CIR_LSIRDYC_Pos (16U)
+#define RCC_CIR_LSIRDYC_Msk (0x1U << RCC_CIR_LSIRDYC_Pos) /*!< 0x00010000 */
+#define RCC_CIR_LSIRDYC RCC_CIR_LSIRDYC_Msk /*!< LSI Ready Interrupt Clear */
+#define RCC_CIR_LSERDYC_Pos (17U)
+#define RCC_CIR_LSERDYC_Msk (0x1U << RCC_CIR_LSERDYC_Pos) /*!< 0x00020000 */
+#define RCC_CIR_LSERDYC RCC_CIR_LSERDYC_Msk /*!< LSE Ready Interrupt Clear */
+#define RCC_CIR_HSIRDYC_Pos (18U)
+#define RCC_CIR_HSIRDYC_Msk (0x1U << RCC_CIR_HSIRDYC_Pos) /*!< 0x00040000 */
+#define RCC_CIR_HSIRDYC RCC_CIR_HSIRDYC_Msk /*!< HSI Ready Interrupt Clear */
+#define RCC_CIR_HSERDYC_Pos (19U)
+#define RCC_CIR_HSERDYC_Msk (0x1U << RCC_CIR_HSERDYC_Pos) /*!< 0x00080000 */
+#define RCC_CIR_HSERDYC RCC_CIR_HSERDYC_Msk /*!< HSE Ready Interrupt Clear */
+#define RCC_CIR_PLLRDYC_Pos (20U)
+#define RCC_CIR_PLLRDYC_Msk (0x1U << RCC_CIR_PLLRDYC_Pos) /*!< 0x00100000 */
+#define RCC_CIR_PLLRDYC RCC_CIR_PLLRDYC_Msk /*!< PLL Ready Interrupt Clear */
+#define RCC_CIR_CSSC_Pos (23U)
+#define RCC_CIR_CSSC_Msk (0x1U << RCC_CIR_CSSC_Pos) /*!< 0x00800000 */
+#define RCC_CIR_CSSC RCC_CIR_CSSC_Msk /*!< Clock Security System Interrupt Clear */
+
+
+/***************** Bit definition for RCC_APB2RSTR register *****************/
+#define RCC_APB2RSTR_AFIORST_Pos (0U)
+#define RCC_APB2RSTR_AFIORST_Msk (0x1U << RCC_APB2RSTR_AFIORST_Pos) /*!< 0x00000001 */
+#define RCC_APB2RSTR_AFIORST RCC_APB2RSTR_AFIORST_Msk /*!< Alternate Function I/O reset */
+#define RCC_APB2RSTR_IOPARST_Pos (2U)
+#define RCC_APB2RSTR_IOPARST_Msk (0x1U << RCC_APB2RSTR_IOPARST_Pos) /*!< 0x00000004 */
+#define RCC_APB2RSTR_IOPARST RCC_APB2RSTR_IOPARST_Msk /*!< I/O port A reset */
+#define RCC_APB2RSTR_IOPBRST_Pos (3U)
+#define RCC_APB2RSTR_IOPBRST_Msk (0x1U << RCC_APB2RSTR_IOPBRST_Pos) /*!< 0x00000008 */
+#define RCC_APB2RSTR_IOPBRST RCC_APB2RSTR_IOPBRST_Msk /*!< I/O port B reset */
+#define RCC_APB2RSTR_IOPCRST_Pos (4U)
+#define RCC_APB2RSTR_IOPCRST_Msk (0x1U << RCC_APB2RSTR_IOPCRST_Pos) /*!< 0x00000010 */
+#define RCC_APB2RSTR_IOPCRST RCC_APB2RSTR_IOPCRST_Msk /*!< I/O port C reset */
+#define RCC_APB2RSTR_IOPDRST_Pos (5U)
+#define RCC_APB2RSTR_IOPDRST_Msk (0x1U << RCC_APB2RSTR_IOPDRST_Pos) /*!< 0x00000020 */
+#define RCC_APB2RSTR_IOPDRST RCC_APB2RSTR_IOPDRST_Msk /*!< I/O port D reset */
+#define RCC_APB2RSTR_ADC1RST_Pos (9U)
+#define RCC_APB2RSTR_ADC1RST_Msk (0x1U << RCC_APB2RSTR_ADC1RST_Pos) /*!< 0x00000200 */
+#define RCC_APB2RSTR_ADC1RST RCC_APB2RSTR_ADC1RST_Msk /*!< ADC 1 interface reset */
+
+
+#define RCC_APB2RSTR_TIM1RST_Pos (11U)
+#define RCC_APB2RSTR_TIM1RST_Msk (0x1U << RCC_APB2RSTR_TIM1RST_Pos) /*!< 0x00000800 */
+#define RCC_APB2RSTR_TIM1RST RCC_APB2RSTR_TIM1RST_Msk /*!< TIM1 Timer reset */
+#define RCC_APB2RSTR_SPI1RST_Pos (12U)
+#define RCC_APB2RSTR_SPI1RST_Msk (0x1U << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */
+#define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk /*!< SPI 1 reset */
+#define RCC_APB2RSTR_USART1RST_Pos (14U)
+#define RCC_APB2RSTR_USART1RST_Msk (0x1U << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00004000 */
+#define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk /*!< USART1 reset */
+
+#define RCC_APB2RSTR_TIM15RST_Pos (16U)
+#define RCC_APB2RSTR_TIM15RST_Msk (0x1U << RCC_APB2RSTR_TIM15RST_Pos) /*!< 0x00010000 */
+#define RCC_APB2RSTR_TIM15RST RCC_APB2RSTR_TIM15RST_Msk /*!< TIM15 Timer reset */
+#define RCC_APB2RSTR_TIM16RST_Pos (17U)
+#define RCC_APB2RSTR_TIM16RST_Msk (0x1U << RCC_APB2RSTR_TIM16RST_Pos) /*!< 0x00020000 */
+#define RCC_APB2RSTR_TIM16RST RCC_APB2RSTR_TIM16RST_Msk /*!< TIM16 Timer reset */
+#define RCC_APB2RSTR_TIM17RST_Pos (18U)
+#define RCC_APB2RSTR_TIM17RST_Msk (0x1U << RCC_APB2RSTR_TIM17RST_Pos) /*!< 0x00040000 */
+#define RCC_APB2RSTR_TIM17RST RCC_APB2RSTR_TIM17RST_Msk /*!< TIM17 Timer reset */
+
+#define RCC_APB2RSTR_IOPERST_Pos (6U)
+#define RCC_APB2RSTR_IOPERST_Msk (0x1U << RCC_APB2RSTR_IOPERST_Pos) /*!< 0x00000040 */
+#define RCC_APB2RSTR_IOPERST RCC_APB2RSTR_IOPERST_Msk /*!< I/O port E reset */
+
+
+#define RCC_APB2RSTR_IOPFRST_Pos (7U)
+#define RCC_APB2RSTR_IOPFRST_Msk (0x1U << RCC_APB2RSTR_IOPFRST_Pos) /*!< 0x00000080 */
+#define RCC_APB2RSTR_IOPFRST RCC_APB2RSTR_IOPFRST_Msk /*!< I/O port F reset */
+#define RCC_APB2RSTR_IOPGRST_Pos (8U)
+#define RCC_APB2RSTR_IOPGRST_Msk (0x1U << RCC_APB2RSTR_IOPGRST_Pos) /*!< 0x00000100 */
+#define RCC_APB2RSTR_IOPGRST RCC_APB2RSTR_IOPGRST_Msk /*!< I/O port G reset */
+
+
+/***************** Bit definition for RCC_APB1RSTR register *****************/
+#define RCC_APB1RSTR_TIM2RST_Pos (0U)
+#define RCC_APB1RSTR_TIM2RST_Msk (0x1U << RCC_APB1RSTR_TIM2RST_Pos) /*!< 0x00000001 */
+#define RCC_APB1RSTR_TIM2RST RCC_APB1RSTR_TIM2RST_Msk /*!< Timer 2 reset */
+#define RCC_APB1RSTR_TIM3RST_Pos (1U)
+#define RCC_APB1RSTR_TIM3RST_Msk (0x1U << RCC_APB1RSTR_TIM3RST_Pos) /*!< 0x00000002 */
+#define RCC_APB1RSTR_TIM3RST RCC_APB1RSTR_TIM3RST_Msk /*!< Timer 3 reset */
+#define RCC_APB1RSTR_WWDGRST_Pos (11U)
+#define RCC_APB1RSTR_WWDGRST_Msk (0x1U << RCC_APB1RSTR_WWDGRST_Pos) /*!< 0x00000800 */
+#define RCC_APB1RSTR_WWDGRST RCC_APB1RSTR_WWDGRST_Msk /*!< Window Watchdog reset */
+#define RCC_APB1RSTR_USART2RST_Pos (17U)
+#define RCC_APB1RSTR_USART2RST_Msk (0x1U << RCC_APB1RSTR_USART2RST_Pos) /*!< 0x00020000 */
+#define RCC_APB1RSTR_USART2RST RCC_APB1RSTR_USART2RST_Msk /*!< USART 2 reset */
+#define RCC_APB1RSTR_I2C1RST_Pos (21U)
+#define RCC_APB1RSTR_I2C1RST_Msk (0x1U << RCC_APB1RSTR_I2C1RST_Pos) /*!< 0x00200000 */
+#define RCC_APB1RSTR_I2C1RST RCC_APB1RSTR_I2C1RST_Msk /*!< I2C 1 reset */
+
+
+#define RCC_APB1RSTR_BKPRST_Pos (27U)
+#define RCC_APB1RSTR_BKPRST_Msk (0x1U << RCC_APB1RSTR_BKPRST_Pos) /*!< 0x08000000 */
+#define RCC_APB1RSTR_BKPRST RCC_APB1RSTR_BKPRST_Msk /*!< Backup interface reset */
+#define RCC_APB1RSTR_PWRRST_Pos (28U)
+#define RCC_APB1RSTR_PWRRST_Msk (0x1U << RCC_APB1RSTR_PWRRST_Pos) /*!< 0x10000000 */
+#define RCC_APB1RSTR_PWRRST RCC_APB1RSTR_PWRRST_Msk /*!< Power interface reset */
+
+#define RCC_APB1RSTR_TIM4RST_Pos (2U)
+#define RCC_APB1RSTR_TIM4RST_Msk (0x1U << RCC_APB1RSTR_TIM4RST_Pos) /*!< 0x00000004 */
+#define RCC_APB1RSTR_TIM4RST RCC_APB1RSTR_TIM4RST_Msk /*!< Timer 4 reset */
+#define RCC_APB1RSTR_SPI2RST_Pos (14U)
+#define RCC_APB1RSTR_SPI2RST_Msk (0x1U << RCC_APB1RSTR_SPI2RST_Pos) /*!< 0x00004000 */
+#define RCC_APB1RSTR_SPI2RST RCC_APB1RSTR_SPI2RST_Msk /*!< SPI 2 reset */
+#define RCC_APB1RSTR_USART3RST_Pos (18U)
+#define RCC_APB1RSTR_USART3RST_Msk (0x1U << RCC_APB1RSTR_USART3RST_Pos) /*!< 0x00040000 */
+#define RCC_APB1RSTR_USART3RST RCC_APB1RSTR_USART3RST_Msk /*!< USART 3 reset */
+#define RCC_APB1RSTR_I2C2RST_Pos (22U)
+#define RCC_APB1RSTR_I2C2RST_Msk (0x1U << RCC_APB1RSTR_I2C2RST_Pos) /*!< 0x00400000 */
+#define RCC_APB1RSTR_I2C2RST RCC_APB1RSTR_I2C2RST_Msk /*!< I2C 2 reset */
+
+
+
+#define RCC_APB1RSTR_TIM6RST_Pos (4U)
+#define RCC_APB1RSTR_TIM6RST_Msk (0x1U << RCC_APB1RSTR_TIM6RST_Pos) /*!< 0x00000010 */
+#define RCC_APB1RSTR_TIM6RST RCC_APB1RSTR_TIM6RST_Msk /*!< Timer 6 reset */
+#define RCC_APB1RSTR_TIM7RST_Pos (5U)
+#define RCC_APB1RSTR_TIM7RST_Msk (0x1U << RCC_APB1RSTR_TIM7RST_Pos) /*!< 0x00000020 */
+#define RCC_APB1RSTR_TIM7RST RCC_APB1RSTR_TIM7RST_Msk /*!< Timer 7 reset */
+#define RCC_APB1RSTR_CECRST_Pos (30U)
+#define RCC_APB1RSTR_CECRST_Msk (0x1U << RCC_APB1RSTR_CECRST_Pos) /*!< 0x40000000 */
+#define RCC_APB1RSTR_CECRST RCC_APB1RSTR_CECRST_Msk /*!< CEC interface reset */
+
+#define RCC_APB1RSTR_TIM5RST_Pos (3U)
+#define RCC_APB1RSTR_TIM5RST_Msk (0x1U << RCC_APB1RSTR_TIM5RST_Pos) /*!< 0x00000008 */
+#define RCC_APB1RSTR_TIM5RST RCC_APB1RSTR_TIM5RST_Msk /*!< Timer 5 reset */
+#define RCC_APB1RSTR_TIM12RST_Pos (6U)
+#define RCC_APB1RSTR_TIM12RST_Msk (0x1U << RCC_APB1RSTR_TIM12RST_Pos) /*!< 0x00000040 */
+#define RCC_APB1RSTR_TIM12RST RCC_APB1RSTR_TIM12RST_Msk /*!< TIM12 Timer reset */
+#define RCC_APB1RSTR_TIM13RST_Pos (7U)
+#define RCC_APB1RSTR_TIM13RST_Msk (0x1U << RCC_APB1RSTR_TIM13RST_Pos) /*!< 0x00000080 */
+#define RCC_APB1RSTR_TIM13RST RCC_APB1RSTR_TIM13RST_Msk /*!< TIM13 Timer reset */
+#define RCC_APB1RSTR_TIM14RST_Pos (8U)
+#define RCC_APB1RSTR_TIM14RST_Msk (0x1U << RCC_APB1RSTR_TIM14RST_Pos) /*!< 0x00000100 */
+#define RCC_APB1RSTR_TIM14RST RCC_APB1RSTR_TIM14RST_Msk /*!< TIM14 Timer reset */
+#define RCC_APB1RSTR_SPI3RST_Pos (15U)
+#define RCC_APB1RSTR_SPI3RST_Msk (0x1U << RCC_APB1RSTR_SPI3RST_Pos) /*!< 0x00008000 */
+#define RCC_APB1RSTR_SPI3RST RCC_APB1RSTR_SPI3RST_Msk /*!< SPI 3 reset */
+#define RCC_APB1RSTR_UART4RST_Pos (19U)
+#define RCC_APB1RSTR_UART4RST_Msk (0x1U << RCC_APB1RSTR_UART4RST_Pos) /*!< 0x00080000 */
+#define RCC_APB1RSTR_UART4RST RCC_APB1RSTR_UART4RST_Msk /*!< UART 4 reset */
+#define RCC_APB1RSTR_UART5RST_Pos (20U)
+#define RCC_APB1RSTR_UART5RST_Msk (0x1U << RCC_APB1RSTR_UART5RST_Pos) /*!< 0x00100000 */
+#define RCC_APB1RSTR_UART5RST RCC_APB1RSTR_UART5RST_Msk /*!< UART 5 reset */
+
+
+#define RCC_APB1RSTR_DACRST_Pos (29U)
+#define RCC_APB1RSTR_DACRST_Msk (0x1U << RCC_APB1RSTR_DACRST_Pos) /*!< 0x20000000 */
+#define RCC_APB1RSTR_DACRST RCC_APB1RSTR_DACRST_Msk /*!< DAC interface reset */
+
+/****************** Bit definition for RCC_AHBENR register ******************/
+#define RCC_AHBENR_DMA1EN_Pos (0U)
+#define RCC_AHBENR_DMA1EN_Msk (0x1U << RCC_AHBENR_DMA1EN_Pos) /*!< 0x00000001 */
+#define RCC_AHBENR_DMA1EN RCC_AHBENR_DMA1EN_Msk /*!< DMA1 clock enable */
+#define RCC_AHBENR_SRAMEN_Pos (2U)
+#define RCC_AHBENR_SRAMEN_Msk (0x1U << RCC_AHBENR_SRAMEN_Pos) /*!< 0x00000004 */
+#define RCC_AHBENR_SRAMEN RCC_AHBENR_SRAMEN_Msk /*!< SRAM interface clock enable */
+#define RCC_AHBENR_FLITFEN_Pos (4U)
+#define RCC_AHBENR_FLITFEN_Msk (0x1U << RCC_AHBENR_FLITFEN_Pos) /*!< 0x00000010 */
+#define RCC_AHBENR_FLITFEN RCC_AHBENR_FLITFEN_Msk /*!< FLITF clock enable */
+#define RCC_AHBENR_CRCEN_Pos (6U)
+#define RCC_AHBENR_CRCEN_Msk (0x1U << RCC_AHBENR_CRCEN_Pos) /*!< 0x00000040 */
+#define RCC_AHBENR_CRCEN RCC_AHBENR_CRCEN_Msk /*!< CRC clock enable */
+
+#define RCC_AHBENR_DMA2EN_Pos (1U)
+#define RCC_AHBENR_DMA2EN_Msk (0x1U << RCC_AHBENR_DMA2EN_Pos) /*!< 0x00000002 */
+#define RCC_AHBENR_DMA2EN RCC_AHBENR_DMA2EN_Msk /*!< DMA2 clock enable */
+
+#define RCC_AHBENR_FSMCEN_Pos (8U)
+#define RCC_AHBENR_FSMCEN_Msk (0x1U << RCC_AHBENR_FSMCEN_Pos) /*!< 0x00000100 */
+#define RCC_AHBENR_FSMCEN RCC_AHBENR_FSMCEN_Msk /*!< FSMC clock enable */
+
+
+/****************** Bit definition for RCC_APB2ENR register *****************/
+#define RCC_APB2ENR_AFIOEN_Pos (0U)
+#define RCC_APB2ENR_AFIOEN_Msk (0x1U << RCC_APB2ENR_AFIOEN_Pos) /*!< 0x00000001 */
+#define RCC_APB2ENR_AFIOEN RCC_APB2ENR_AFIOEN_Msk /*!< Alternate Function I/O clock enable */
+#define RCC_APB2ENR_IOPAEN_Pos (2U)
+#define RCC_APB2ENR_IOPAEN_Msk (0x1U << RCC_APB2ENR_IOPAEN_Pos) /*!< 0x00000004 */
+#define RCC_APB2ENR_IOPAEN RCC_APB2ENR_IOPAEN_Msk /*!< I/O port A clock enable */
+#define RCC_APB2ENR_IOPBEN_Pos (3U)
+#define RCC_APB2ENR_IOPBEN_Msk (0x1U << RCC_APB2ENR_IOPBEN_Pos) /*!< 0x00000008 */
+#define RCC_APB2ENR_IOPBEN RCC_APB2ENR_IOPBEN_Msk /*!< I/O port B clock enable */
+#define RCC_APB2ENR_IOPCEN_Pos (4U)
+#define RCC_APB2ENR_IOPCEN_Msk (0x1U << RCC_APB2ENR_IOPCEN_Pos) /*!< 0x00000010 */
+#define RCC_APB2ENR_IOPCEN RCC_APB2ENR_IOPCEN_Msk /*!< I/O port C clock enable */
+#define RCC_APB2ENR_IOPDEN_Pos (5U)
+#define RCC_APB2ENR_IOPDEN_Msk (0x1U << RCC_APB2ENR_IOPDEN_Pos) /*!< 0x00000020 */
+#define RCC_APB2ENR_IOPDEN RCC_APB2ENR_IOPDEN_Msk /*!< I/O port D clock enable */
+#define RCC_APB2ENR_ADC1EN_Pos (9U)
+#define RCC_APB2ENR_ADC1EN_Msk (0x1U << RCC_APB2ENR_ADC1EN_Pos) /*!< 0x00000200 */
+#define RCC_APB2ENR_ADC1EN RCC_APB2ENR_ADC1EN_Msk /*!< ADC 1 interface clock enable */
+
+
+#define RCC_APB2ENR_TIM1EN_Pos (11U)
+#define RCC_APB2ENR_TIM1EN_Msk (0x1U << RCC_APB2ENR_TIM1EN_Pos) /*!< 0x00000800 */
+#define RCC_APB2ENR_TIM1EN RCC_APB2ENR_TIM1EN_Msk /*!< TIM1 Timer clock enable */
+#define RCC_APB2ENR_SPI1EN_Pos (12U)
+#define RCC_APB2ENR_SPI1EN_Msk (0x1U << RCC_APB2ENR_SPI1EN_Pos) /*!< 0x00001000 */
+#define RCC_APB2ENR_SPI1EN RCC_APB2ENR_SPI1EN_Msk /*!< SPI 1 clock enable */
+#define RCC_APB2ENR_USART1EN_Pos (14U)
+#define RCC_APB2ENR_USART1EN_Msk (0x1U << RCC_APB2ENR_USART1EN_Pos) /*!< 0x00004000 */
+#define RCC_APB2ENR_USART1EN RCC_APB2ENR_USART1EN_Msk /*!< USART1 clock enable */
+
+#define RCC_APB2ENR_TIM15EN_Pos (16U)
+#define RCC_APB2ENR_TIM15EN_Msk (0x1U << RCC_APB2ENR_TIM15EN_Pos) /*!< 0x00010000 */
+#define RCC_APB2ENR_TIM15EN RCC_APB2ENR_TIM15EN_Msk /*!< TIM15 Timer clock enable */
+#define RCC_APB2ENR_TIM16EN_Pos (17U)
+#define RCC_APB2ENR_TIM16EN_Msk (0x1U << RCC_APB2ENR_TIM16EN_Pos) /*!< 0x00020000 */
+#define RCC_APB2ENR_TIM16EN RCC_APB2ENR_TIM16EN_Msk /*!< TIM16 Timer clock enable */
+#define RCC_APB2ENR_TIM17EN_Pos (18U)
+#define RCC_APB2ENR_TIM17EN_Msk (0x1U << RCC_APB2ENR_TIM17EN_Pos) /*!< 0x00040000 */
+#define RCC_APB2ENR_TIM17EN RCC_APB2ENR_TIM17EN_Msk /*!< TIM17 Timer clock enable */
+
+#define RCC_APB2ENR_IOPEEN_Pos (6U)
+#define RCC_APB2ENR_IOPEEN_Msk (0x1U << RCC_APB2ENR_IOPEEN_Pos) /*!< 0x00000040 */
+#define RCC_APB2ENR_IOPEEN RCC_APB2ENR_IOPEEN_Msk /*!< I/O port E clock enable */
+
+
+#define RCC_APB2ENR_IOPFEN_Pos (7U)
+#define RCC_APB2ENR_IOPFEN_Msk (0x1U << RCC_APB2ENR_IOPFEN_Pos) /*!< 0x00000080 */
+#define RCC_APB2ENR_IOPFEN RCC_APB2ENR_IOPFEN_Msk /*!< I/O port F clock enable */
+#define RCC_APB2ENR_IOPGEN_Pos (8U)
+#define RCC_APB2ENR_IOPGEN_Msk (0x1U << RCC_APB2ENR_IOPGEN_Pos) /*!< 0x00000100 */
+#define RCC_APB2ENR_IOPGEN RCC_APB2ENR_IOPGEN_Msk /*!< I/O port G clock enable */
+
+
+/***************** Bit definition for RCC_APB1ENR register ******************/
+#define RCC_APB1ENR_TIM2EN_Pos (0U)
+#define RCC_APB1ENR_TIM2EN_Msk (0x1U << RCC_APB1ENR_TIM2EN_Pos) /*!< 0x00000001 */
+#define RCC_APB1ENR_TIM2EN RCC_APB1ENR_TIM2EN_Msk /*!< Timer 2 clock enabled*/
+#define RCC_APB1ENR_TIM3EN_Pos (1U)
+#define RCC_APB1ENR_TIM3EN_Msk (0x1U << RCC_APB1ENR_TIM3EN_Pos) /*!< 0x00000002 */
+#define RCC_APB1ENR_TIM3EN RCC_APB1ENR_TIM3EN_Msk /*!< Timer 3 clock enable */
+#define RCC_APB1ENR_WWDGEN_Pos (11U)
+#define RCC_APB1ENR_WWDGEN_Msk (0x1U << RCC_APB1ENR_WWDGEN_Pos) /*!< 0x00000800 */
+#define RCC_APB1ENR_WWDGEN RCC_APB1ENR_WWDGEN_Msk /*!< Window Watchdog clock enable */
+#define RCC_APB1ENR_USART2EN_Pos (17U)
+#define RCC_APB1ENR_USART2EN_Msk (0x1U << RCC_APB1ENR_USART2EN_Pos) /*!< 0x00020000 */
+#define RCC_APB1ENR_USART2EN RCC_APB1ENR_USART2EN_Msk /*!< USART 2 clock enable */
+#define RCC_APB1ENR_I2C1EN_Pos (21U)
+#define RCC_APB1ENR_I2C1EN_Msk (0x1U << RCC_APB1ENR_I2C1EN_Pos) /*!< 0x00200000 */
+#define RCC_APB1ENR_I2C1EN RCC_APB1ENR_I2C1EN_Msk /*!< I2C 1 clock enable */
+
+
+#define RCC_APB1ENR_BKPEN_Pos (27U)
+#define RCC_APB1ENR_BKPEN_Msk (0x1U << RCC_APB1ENR_BKPEN_Pos) /*!< 0x08000000 */
+#define RCC_APB1ENR_BKPEN RCC_APB1ENR_BKPEN_Msk /*!< Backup interface clock enable */
+#define RCC_APB1ENR_PWREN_Pos (28U)
+#define RCC_APB1ENR_PWREN_Msk (0x1U << RCC_APB1ENR_PWREN_Pos) /*!< 0x10000000 */
+#define RCC_APB1ENR_PWREN RCC_APB1ENR_PWREN_Msk /*!< Power interface clock enable */
+
+#define RCC_APB1ENR_TIM4EN_Pos (2U)
+#define RCC_APB1ENR_TIM4EN_Msk (0x1U << RCC_APB1ENR_TIM4EN_Pos) /*!< 0x00000004 */
+#define RCC_APB1ENR_TIM4EN RCC_APB1ENR_TIM4EN_Msk /*!< Timer 4 clock enable */
+#define RCC_APB1ENR_SPI2EN_Pos (14U)
+#define RCC_APB1ENR_SPI2EN_Msk (0x1U << RCC_APB1ENR_SPI2EN_Pos) /*!< 0x00004000 */
+#define RCC_APB1ENR_SPI2EN RCC_APB1ENR_SPI2EN_Msk /*!< SPI 2 clock enable */
+#define RCC_APB1ENR_USART3EN_Pos (18U)
+#define RCC_APB1ENR_USART3EN_Msk (0x1U << RCC_APB1ENR_USART3EN_Pos) /*!< 0x00040000 */
+#define RCC_APB1ENR_USART3EN RCC_APB1ENR_USART3EN_Msk /*!< USART 3 clock enable */
+#define RCC_APB1ENR_I2C2EN_Pos (22U)
+#define RCC_APB1ENR_I2C2EN_Msk (0x1U << RCC_APB1ENR_I2C2EN_Pos) /*!< 0x00400000 */
+#define RCC_APB1ENR_I2C2EN RCC_APB1ENR_I2C2EN_Msk /*!< I2C 2 clock enable */
+
+
+
+#define RCC_APB1ENR_TIM6EN_Pos (4U)
+#define RCC_APB1ENR_TIM6EN_Msk (0x1U << RCC_APB1ENR_TIM6EN_Pos) /*!< 0x00000010 */
+#define RCC_APB1ENR_TIM6EN RCC_APB1ENR_TIM6EN_Msk /*!< Timer 6 clock enable */
+#define RCC_APB1ENR_TIM7EN_Pos (5U)
+#define RCC_APB1ENR_TIM7EN_Msk (0x1U << RCC_APB1ENR_TIM7EN_Pos) /*!< 0x00000020 */
+#define RCC_APB1ENR_TIM7EN RCC_APB1ENR_TIM7EN_Msk /*!< Timer 7 clock enable */
+#define RCC_APB1ENR_CECEN_Pos (30U)
+#define RCC_APB1ENR_CECEN_Msk (0x1U << RCC_APB1ENR_CECEN_Pos) /*!< 0x40000000 */
+#define RCC_APB1ENR_CECEN RCC_APB1ENR_CECEN_Msk /*!< CEC interface clock enable */
+
+#define RCC_APB1ENR_TIM5EN_Pos (3U)
+#define RCC_APB1ENR_TIM5EN_Msk (0x1U << RCC_APB1ENR_TIM5EN_Pos) /*!< 0x00000008 */
+#define RCC_APB1ENR_TIM5EN RCC_APB1ENR_TIM5EN_Msk /*!< Timer 5 clock enable */
+#define RCC_APB1ENR_TIM12EN_Pos (6U)
+#define RCC_APB1ENR_TIM12EN_Msk (0x1U << RCC_APB1ENR_TIM12EN_Pos) /*!< 0x00000040 */
+#define RCC_APB1ENR_TIM12EN RCC_APB1ENR_TIM12EN_Msk /*!< TIM12 Timer clock enable */
+#define RCC_APB1ENR_TIM13EN_Pos (7U)
+#define RCC_APB1ENR_TIM13EN_Msk (0x1U << RCC_APB1ENR_TIM13EN_Pos) /*!< 0x00000080 */
+#define RCC_APB1ENR_TIM13EN RCC_APB1ENR_TIM13EN_Msk /*!< TIM13 Timer clock enable */
+#define RCC_APB1ENR_TIM14EN_Pos (8U)
+#define RCC_APB1ENR_TIM14EN_Msk (0x1U << RCC_APB1ENR_TIM14EN_Pos) /*!< 0x00000100 */
+#define RCC_APB1ENR_TIM14EN RCC_APB1ENR_TIM14EN_Msk /*!< TIM14 Timer clock enable */
+#define RCC_APB1ENR_SPI3EN_Pos (15U)
+#define RCC_APB1ENR_SPI3EN_Msk (0x1U << RCC_APB1ENR_SPI3EN_Pos) /*!< 0x00008000 */
+#define RCC_APB1ENR_SPI3EN RCC_APB1ENR_SPI3EN_Msk /*!< SPI 3 clock enable */
+#define RCC_APB1ENR_UART4EN_Pos (19U)
+#define RCC_APB1ENR_UART4EN_Msk (0x1U << RCC_APB1ENR_UART4EN_Pos) /*!< 0x00080000 */
+#define RCC_APB1ENR_UART4EN RCC_APB1ENR_UART4EN_Msk /*!< UART 4 clock enable */
+#define RCC_APB1ENR_UART5EN_Pos (20U)
+#define RCC_APB1ENR_UART5EN_Msk (0x1U << RCC_APB1ENR_UART5EN_Pos) /*!< 0x00100000 */
+#define RCC_APB1ENR_UART5EN RCC_APB1ENR_UART5EN_Msk /*!< UART 5 clock enable */
+
+
+#define RCC_APB1ENR_DACEN_Pos (29U)
+#define RCC_APB1ENR_DACEN_Msk (0x1U << RCC_APB1ENR_DACEN_Pos) /*!< 0x20000000 */
+#define RCC_APB1ENR_DACEN RCC_APB1ENR_DACEN_Msk /*!< DAC interface clock enable */
+
+/******************* Bit definition for RCC_BDCR register *******************/
+#define RCC_BDCR_LSEON_Pos (0U)
+#define RCC_BDCR_LSEON_Msk (0x1U << RCC_BDCR_LSEON_Pos) /*!< 0x00000001 */
+#define RCC_BDCR_LSEON RCC_BDCR_LSEON_Msk /*!< External Low Speed oscillator enable */
+#define RCC_BDCR_LSERDY_Pos (1U)
+#define RCC_BDCR_LSERDY_Msk (0x1U << RCC_BDCR_LSERDY_Pos) /*!< 0x00000002 */
+#define RCC_BDCR_LSERDY RCC_BDCR_LSERDY_Msk /*!< External Low Speed oscillator Ready */
+#define RCC_BDCR_LSEBYP_Pos (2U)
+#define RCC_BDCR_LSEBYP_Msk (0x1U << RCC_BDCR_LSEBYP_Pos) /*!< 0x00000004 */
+#define RCC_BDCR_LSEBYP RCC_BDCR_LSEBYP_Msk /*!< External Low Speed oscillator Bypass */
+
+#define RCC_BDCR_RTCSEL_Pos (8U)
+#define RCC_BDCR_RTCSEL_Msk (0x3U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000300 */
+#define RCC_BDCR_RTCSEL RCC_BDCR_RTCSEL_Msk /*!< RTCSEL[1:0] bits (RTC clock source selection) */
+#define RCC_BDCR_RTCSEL_0 (0x1U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000100 */
+#define RCC_BDCR_RTCSEL_1 (0x2U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000200 */
+
+/*!< RTC congiguration */
+#define RCC_BDCR_RTCSEL_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */
+#define RCC_BDCR_RTCSEL_LSE ((uint32_t)0x00000100) /*!< LSE oscillator clock used as RTC clock */
+#define RCC_BDCR_RTCSEL_LSI ((uint32_t)0x00000200) /*!< LSI oscillator clock used as RTC clock */
+#define RCC_BDCR_RTCSEL_HSE ((uint32_t)0x00000300) /*!< HSE oscillator clock divided by 128 used as RTC clock */
+
+#define RCC_BDCR_RTCEN_Pos (15U)
+#define RCC_BDCR_RTCEN_Msk (0x1U << RCC_BDCR_RTCEN_Pos) /*!< 0x00008000 */
+#define RCC_BDCR_RTCEN RCC_BDCR_RTCEN_Msk /*!< RTC clock enable */
+#define RCC_BDCR_BDRST_Pos (16U)
+#define RCC_BDCR_BDRST_Msk (0x1U << RCC_BDCR_BDRST_Pos) /*!< 0x00010000 */
+#define RCC_BDCR_BDRST RCC_BDCR_BDRST_Msk /*!< Backup domain software reset */
+
+/******************* Bit definition for RCC_CSR register ********************/
+#define RCC_CSR_LSION_Pos (0U)
+#define RCC_CSR_LSION_Msk (0x1U << RCC_CSR_LSION_Pos) /*!< 0x00000001 */
+#define RCC_CSR_LSION RCC_CSR_LSION_Msk /*!< Internal Low Speed oscillator enable */
+#define RCC_CSR_LSIRDY_Pos (1U)
+#define RCC_CSR_LSIRDY_Msk (0x1U << RCC_CSR_LSIRDY_Pos) /*!< 0x00000002 */
+#define RCC_CSR_LSIRDY RCC_CSR_LSIRDY_Msk /*!< Internal Low Speed oscillator Ready */
+#define RCC_CSR_RMVF_Pos (24U)
+#define RCC_CSR_RMVF_Msk (0x1U << RCC_CSR_RMVF_Pos) /*!< 0x01000000 */
+#define RCC_CSR_RMVF RCC_CSR_RMVF_Msk /*!< Remove reset flag */
+#define RCC_CSR_PINRSTF_Pos (26U)
+#define RCC_CSR_PINRSTF_Msk (0x1U << RCC_CSR_PINRSTF_Pos) /*!< 0x04000000 */
+#define RCC_CSR_PINRSTF RCC_CSR_PINRSTF_Msk /*!< PIN reset flag */
+#define RCC_CSR_PORRSTF_Pos (27U)
+#define RCC_CSR_PORRSTF_Msk (0x1U << RCC_CSR_PORRSTF_Pos) /*!< 0x08000000 */
+#define RCC_CSR_PORRSTF RCC_CSR_PORRSTF_Msk /*!< POR/PDR reset flag */
+#define RCC_CSR_SFTRSTF_Pos (28U)
+#define RCC_CSR_SFTRSTF_Msk (0x1U << RCC_CSR_SFTRSTF_Pos) /*!< 0x10000000 */
+#define RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF_Msk /*!< Software Reset flag */
+#define RCC_CSR_IWDGRSTF_Pos (29U)
+#define RCC_CSR_IWDGRSTF_Msk (0x1U << RCC_CSR_IWDGRSTF_Pos) /*!< 0x20000000 */
+#define RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF_Msk /*!< Independent Watchdog reset flag */
+#define RCC_CSR_WWDGRSTF_Pos (30U)
+#define RCC_CSR_WWDGRSTF_Msk (0x1U << RCC_CSR_WWDGRSTF_Pos) /*!< 0x40000000 */
+#define RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF_Msk /*!< Window watchdog reset flag */
+#define RCC_CSR_LPWRRSTF_Pos (31U)
+#define RCC_CSR_LPWRRSTF_Msk (0x1U << RCC_CSR_LPWRRSTF_Pos) /*!< 0x80000000 */
+#define RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF_Msk /*!< Low-Power reset flag */
+
+
+/******************* Bit definition for RCC_CFGR2 register ******************/
+/*!< PREDIV1 configuration */
+#define RCC_CFGR2_PREDIV1_Pos (0U)
+#define RCC_CFGR2_PREDIV1_Msk (0xFU << RCC_CFGR2_PREDIV1_Pos) /*!< 0x0000000F */
+#define RCC_CFGR2_PREDIV1 RCC_CFGR2_PREDIV1_Msk /*!< PREDIV1[3:0] bits */
+#define RCC_CFGR2_PREDIV1_0 (0x1U << RCC_CFGR2_PREDIV1_Pos) /*!< 0x00000001 */
+#define RCC_CFGR2_PREDIV1_1 (0x2U << RCC_CFGR2_PREDIV1_Pos) /*!< 0x00000002 */
+#define RCC_CFGR2_PREDIV1_2 (0x4U << RCC_CFGR2_PREDIV1_Pos) /*!< 0x00000004 */
+#define RCC_CFGR2_PREDIV1_3 (0x8U << RCC_CFGR2_PREDIV1_Pos) /*!< 0x00000008 */
+
+#define RCC_CFGR2_PREDIV1_DIV1 ((uint32_t)0x00000000) /*!< PREDIV1 input clock not divided */
+#define RCC_CFGR2_PREDIV1_DIV2_Pos (0U)
+#define RCC_CFGR2_PREDIV1_DIV2_Msk (0x1U << RCC_CFGR2_PREDIV1_DIV2_Pos) /*!< 0x00000001 */
+#define RCC_CFGR2_PREDIV1_DIV2 RCC_CFGR2_PREDIV1_DIV2_Msk /*!< PREDIV1 input clock divided by 2 */
+#define RCC_CFGR2_PREDIV1_DIV3_Pos (1U)
+#define RCC_CFGR2_PREDIV1_DIV3_Msk (0x1U << RCC_CFGR2_PREDIV1_DIV3_Pos) /*!< 0x00000002 */
+#define RCC_CFGR2_PREDIV1_DIV3 RCC_CFGR2_PREDIV1_DIV3_Msk /*!< PREDIV1 input clock divided by 3 */
+#define RCC_CFGR2_PREDIV1_DIV4_Pos (0U)
+#define RCC_CFGR2_PREDIV1_DIV4_Msk (0x3U << RCC_CFGR2_PREDIV1_DIV4_Pos) /*!< 0x00000003 */
+#define RCC_CFGR2_PREDIV1_DIV4 RCC_CFGR2_PREDIV1_DIV4_Msk /*!< PREDIV1 input clock divided by 4 */
+#define RCC_CFGR2_PREDIV1_DIV5_Pos (2U)
+#define RCC_CFGR2_PREDIV1_DIV5_Msk (0x1U << RCC_CFGR2_PREDIV1_DIV5_Pos) /*!< 0x00000004 */
+#define RCC_CFGR2_PREDIV1_DIV5 RCC_CFGR2_PREDIV1_DIV5_Msk /*!< PREDIV1 input clock divided by 5 */
+#define RCC_CFGR2_PREDIV1_DIV6_Pos (0U)
+#define RCC_CFGR2_PREDIV1_DIV6_Msk (0x5U << RCC_CFGR2_PREDIV1_DIV6_Pos) /*!< 0x00000005 */
+#define RCC_CFGR2_PREDIV1_DIV6 RCC_CFGR2_PREDIV1_DIV6_Msk /*!< PREDIV1 input clock divided by 6 */
+#define RCC_CFGR2_PREDIV1_DIV7_Pos (1U)
+#define RCC_CFGR2_PREDIV1_DIV7_Msk (0x3U << RCC_CFGR2_PREDIV1_DIV7_Pos) /*!< 0x00000006 */
+#define RCC_CFGR2_PREDIV1_DIV7 RCC_CFGR2_PREDIV1_DIV7_Msk /*!< PREDIV1 input clock divided by 7 */
+#define RCC_CFGR2_PREDIV1_DIV8_Pos (0U)
+#define RCC_CFGR2_PREDIV1_DIV8_Msk (0x7U << RCC_CFGR2_PREDIV1_DIV8_Pos) /*!< 0x00000007 */
+#define RCC_CFGR2_PREDIV1_DIV8 RCC_CFGR2_PREDIV1_DIV8_Msk /*!< PREDIV1 input clock divided by 8 */
+#define RCC_CFGR2_PREDIV1_DIV9_Pos (3U)
+#define RCC_CFGR2_PREDIV1_DIV9_Msk (0x1U << RCC_CFGR2_PREDIV1_DIV9_Pos) /*!< 0x00000008 */
+#define RCC_CFGR2_PREDIV1_DIV9 RCC_CFGR2_PREDIV1_DIV9_Msk /*!< PREDIV1 input clock divided by 9 */
+#define RCC_CFGR2_PREDIV1_DIV10_Pos (0U)
+#define RCC_CFGR2_PREDIV1_DIV10_Msk (0x9U << RCC_CFGR2_PREDIV1_DIV10_Pos) /*!< 0x00000009 */
+#define RCC_CFGR2_PREDIV1_DIV10 RCC_CFGR2_PREDIV1_DIV10_Msk /*!< PREDIV1 input clock divided by 10 */
+#define RCC_CFGR2_PREDIV1_DIV11_Pos (1U)
+#define RCC_CFGR2_PREDIV1_DIV11_Msk (0x5U << RCC_CFGR2_PREDIV1_DIV11_Pos) /*!< 0x0000000A */
+#define RCC_CFGR2_PREDIV1_DIV11 RCC_CFGR2_PREDIV1_DIV11_Msk /*!< PREDIV1 input clock divided by 11 */
+#define RCC_CFGR2_PREDIV1_DIV12_Pos (0U)
+#define RCC_CFGR2_PREDIV1_DIV12_Msk (0xBU << RCC_CFGR2_PREDIV1_DIV12_Pos) /*!< 0x0000000B */
+#define RCC_CFGR2_PREDIV1_DIV12 RCC_CFGR2_PREDIV1_DIV12_Msk /*!< PREDIV1 input clock divided by 12 */
+#define RCC_CFGR2_PREDIV1_DIV13_Pos (2U)
+#define RCC_CFGR2_PREDIV1_DIV13_Msk (0x3U << RCC_CFGR2_PREDIV1_DIV13_Pos) /*!< 0x0000000C */
+#define RCC_CFGR2_PREDIV1_DIV13 RCC_CFGR2_PREDIV1_DIV13_Msk /*!< PREDIV1 input clock divided by 13 */
+#define RCC_CFGR2_PREDIV1_DIV14_Pos (0U)
+#define RCC_CFGR2_PREDIV1_DIV14_Msk (0xDU << RCC_CFGR2_PREDIV1_DIV14_Pos) /*!< 0x0000000D */
+#define RCC_CFGR2_PREDIV1_DIV14 RCC_CFGR2_PREDIV1_DIV14_Msk /*!< PREDIV1 input clock divided by 14 */
+#define RCC_CFGR2_PREDIV1_DIV15_Pos (1U)
+#define RCC_CFGR2_PREDIV1_DIV15_Msk (0x7U << RCC_CFGR2_PREDIV1_DIV15_Pos) /*!< 0x0000000E */
+#define RCC_CFGR2_PREDIV1_DIV15 RCC_CFGR2_PREDIV1_DIV15_Msk /*!< PREDIV1 input clock divided by 15 */
+#define RCC_CFGR2_PREDIV1_DIV16_Pos (0U)
+#define RCC_CFGR2_PREDIV1_DIV16_Msk (0xFU << RCC_CFGR2_PREDIV1_DIV16_Pos) /*!< 0x0000000F */
+#define RCC_CFGR2_PREDIV1_DIV16 RCC_CFGR2_PREDIV1_DIV16_Msk /*!< PREDIV1 input clock divided by 16 */
+
+/******************************************************************************/
+/* */
+/* General Purpose and Alternate Function I/O */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for GPIO_CRL register *******************/
+#define GPIO_CRL_MODE_Pos (0U)
+#define GPIO_CRL_MODE_Msk (0x33333333U << GPIO_CRL_MODE_Pos) /*!< 0x33333333 */
+#define GPIO_CRL_MODE GPIO_CRL_MODE_Msk /*!< Port x mode bits */
+
+#define GPIO_CRL_MODE0_Pos (0U)
+#define GPIO_CRL_MODE0_Msk (0x3U << GPIO_CRL_MODE0_Pos) /*!< 0x00000003 */
+#define GPIO_CRL_MODE0 GPIO_CRL_MODE0_Msk /*!< MODE0[1:0] bits (Port x mode bits, pin 0) */
+#define GPIO_CRL_MODE0_0 (0x1U << GPIO_CRL_MODE0_Pos) /*!< 0x00000001 */
+#define GPIO_CRL_MODE0_1 (0x2U << GPIO_CRL_MODE0_Pos) /*!< 0x00000002 */
+
+#define GPIO_CRL_MODE1_Pos (4U)
+#define GPIO_CRL_MODE1_Msk (0x3U << GPIO_CRL_MODE1_Pos) /*!< 0x00000030 */
+#define GPIO_CRL_MODE1 GPIO_CRL_MODE1_Msk /*!< MODE1[1:0] bits (Port x mode bits, pin 1) */
+#define GPIO_CRL_MODE1_0 (0x1U << GPIO_CRL_MODE1_Pos) /*!< 0x00000010 */
+#define GPIO_CRL_MODE1_1 (0x2U << GPIO_CRL_MODE1_Pos) /*!< 0x00000020 */
+
+#define GPIO_CRL_MODE2_Pos (8U)
+#define GPIO_CRL_MODE2_Msk (0x3U << GPIO_CRL_MODE2_Pos) /*!< 0x00000300 */
+#define GPIO_CRL_MODE2 GPIO_CRL_MODE2_Msk /*!< MODE2[1:0] bits (Port x mode bits, pin 2) */
+#define GPIO_CRL_MODE2_0 (0x1U << GPIO_CRL_MODE2_Pos) /*!< 0x00000100 */
+#define GPIO_CRL_MODE2_1 (0x2U << GPIO_CRL_MODE2_Pos) /*!< 0x00000200 */
+
+#define GPIO_CRL_MODE3_Pos (12U)
+#define GPIO_CRL_MODE3_Msk (0x3U << GPIO_CRL_MODE3_Pos) /*!< 0x00003000 */
+#define GPIO_CRL_MODE3 GPIO_CRL_MODE3_Msk /*!< MODE3[1:0] bits (Port x mode bits, pin 3) */
+#define GPIO_CRL_MODE3_0 (0x1U << GPIO_CRL_MODE3_Pos) /*!< 0x00001000 */
+#define GPIO_CRL_MODE3_1 (0x2U << GPIO_CRL_MODE3_Pos) /*!< 0x00002000 */
+
+#define GPIO_CRL_MODE4_Pos (16U)
+#define GPIO_CRL_MODE4_Msk (0x3U << GPIO_CRL_MODE4_Pos) /*!< 0x00030000 */
+#define GPIO_CRL_MODE4 GPIO_CRL_MODE4_Msk /*!< MODE4[1:0] bits (Port x mode bits, pin 4) */
+#define GPIO_CRL_MODE4_0 (0x1U << GPIO_CRL_MODE4_Pos) /*!< 0x00010000 */
+#define GPIO_CRL_MODE4_1 (0x2U << GPIO_CRL_MODE4_Pos) /*!< 0x00020000 */
+
+#define GPIO_CRL_MODE5_Pos (20U)
+#define GPIO_CRL_MODE5_Msk (0x3U << GPIO_CRL_MODE5_Pos) /*!< 0x00300000 */
+#define GPIO_CRL_MODE5 GPIO_CRL_MODE5_Msk /*!< MODE5[1:0] bits (Port x mode bits, pin 5) */
+#define GPIO_CRL_MODE5_0 (0x1U << GPIO_CRL_MODE5_Pos) /*!< 0x00100000 */
+#define GPIO_CRL_MODE5_1 (0x2U << GPIO_CRL_MODE5_Pos) /*!< 0x00200000 */
+
+#define GPIO_CRL_MODE6_Pos (24U)
+#define GPIO_CRL_MODE6_Msk (0x3U << GPIO_CRL_MODE6_Pos) /*!< 0x03000000 */
+#define GPIO_CRL_MODE6 GPIO_CRL_MODE6_Msk /*!< MODE6[1:0] bits (Port x mode bits, pin 6) */
+#define GPIO_CRL_MODE6_0 (0x1U << GPIO_CRL_MODE6_Pos) /*!< 0x01000000 */
+#define GPIO_CRL_MODE6_1 (0x2U << GPIO_CRL_MODE6_Pos) /*!< 0x02000000 */
+
+#define GPIO_CRL_MODE7_Pos (28U)
+#define GPIO_CRL_MODE7_Msk (0x3U << GPIO_CRL_MODE7_Pos) /*!< 0x30000000 */
+#define GPIO_CRL_MODE7 GPIO_CRL_MODE7_Msk /*!< MODE7[1:0] bits (Port x mode bits, pin 7) */
+#define GPIO_CRL_MODE7_0 (0x1U << GPIO_CRL_MODE7_Pos) /*!< 0x10000000 */
+#define GPIO_CRL_MODE7_1 (0x2U << GPIO_CRL_MODE7_Pos) /*!< 0x20000000 */
+
+#define GPIO_CRL_CNF_Pos (2U)
+#define GPIO_CRL_CNF_Msk (0x33333333U << GPIO_CRL_CNF_Pos) /*!< 0xCCCCCCCC */
+#define GPIO_CRL_CNF GPIO_CRL_CNF_Msk /*!< Port x configuration bits */
+
+#define GPIO_CRL_CNF0_Pos (2U)
+#define GPIO_CRL_CNF0_Msk (0x3U << GPIO_CRL_CNF0_Pos) /*!< 0x0000000C */
+#define GPIO_CRL_CNF0 GPIO_CRL_CNF0_Msk /*!< CNF0[1:0] bits (Port x configuration bits, pin 0) */
+#define GPIO_CRL_CNF0_0 (0x1U << GPIO_CRL_CNF0_Pos) /*!< 0x00000004 */
+#define GPIO_CRL_CNF0_1 (0x2U << GPIO_CRL_CNF0_Pos) /*!< 0x00000008 */
+
+#define GPIO_CRL_CNF1_Pos (6U)
+#define GPIO_CRL_CNF1_Msk (0x3U << GPIO_CRL_CNF1_Pos) /*!< 0x000000C0 */
+#define GPIO_CRL_CNF1 GPIO_CRL_CNF1_Msk /*!< CNF1[1:0] bits (Port x configuration bits, pin 1) */
+#define GPIO_CRL_CNF1_0 (0x1U << GPIO_CRL_CNF1_Pos) /*!< 0x00000040 */
+#define GPIO_CRL_CNF1_1 (0x2U << GPIO_CRL_CNF1_Pos) /*!< 0x00000080 */
+
+#define GPIO_CRL_CNF2_Pos (10U)
+#define GPIO_CRL_CNF2_Msk (0x3U << GPIO_CRL_CNF2_Pos) /*!< 0x00000C00 */
+#define GPIO_CRL_CNF2 GPIO_CRL_CNF2_Msk /*!< CNF2[1:0] bits (Port x configuration bits, pin 2) */
+#define GPIO_CRL_CNF2_0 (0x1U << GPIO_CRL_CNF2_Pos) /*!< 0x00000400 */
+#define GPIO_CRL_CNF2_1 (0x2U << GPIO_CRL_CNF2_Pos) /*!< 0x00000800 */
+
+#define GPIO_CRL_CNF3_Pos (14U)
+#define GPIO_CRL_CNF3_Msk (0x3U << GPIO_CRL_CNF3_Pos) /*!< 0x0000C000 */
+#define GPIO_CRL_CNF3 GPIO_CRL_CNF3_Msk /*!< CNF3[1:0] bits (Port x configuration bits, pin 3) */
+#define GPIO_CRL_CNF3_0 (0x1U << GPIO_CRL_CNF3_Pos) /*!< 0x00004000 */
+#define GPIO_CRL_CNF3_1 (0x2U << GPIO_CRL_CNF3_Pos) /*!< 0x00008000 */
+
+#define GPIO_CRL_CNF4_Pos (18U)
+#define GPIO_CRL_CNF4_Msk (0x3U << GPIO_CRL_CNF4_Pos) /*!< 0x000C0000 */
+#define GPIO_CRL_CNF4 GPIO_CRL_CNF4_Msk /*!< CNF4[1:0] bits (Port x configuration bits, pin 4) */
+#define GPIO_CRL_CNF4_0 (0x1U << GPIO_CRL_CNF4_Pos) /*!< 0x00040000 */
+#define GPIO_CRL_CNF4_1 (0x2U << GPIO_CRL_CNF4_Pos) /*!< 0x00080000 */
+
+#define GPIO_CRL_CNF5_Pos (22U)
+#define GPIO_CRL_CNF5_Msk (0x3U << GPIO_CRL_CNF5_Pos) /*!< 0x00C00000 */
+#define GPIO_CRL_CNF5 GPIO_CRL_CNF5_Msk /*!< CNF5[1:0] bits (Port x configuration bits, pin 5) */
+#define GPIO_CRL_CNF5_0 (0x1U << GPIO_CRL_CNF5_Pos) /*!< 0x00400000 */
+#define GPIO_CRL_CNF5_1 (0x2U << GPIO_CRL_CNF5_Pos) /*!< 0x00800000 */
+
+#define GPIO_CRL_CNF6_Pos (26U)
+#define GPIO_CRL_CNF6_Msk (0x3U << GPIO_CRL_CNF6_Pos) /*!< 0x0C000000 */
+#define GPIO_CRL_CNF6 GPIO_CRL_CNF6_Msk /*!< CNF6[1:0] bits (Port x configuration bits, pin 6) */
+#define GPIO_CRL_CNF6_0 (0x1U << GPIO_CRL_CNF6_Pos) /*!< 0x04000000 */
+#define GPIO_CRL_CNF6_1 (0x2U << GPIO_CRL_CNF6_Pos) /*!< 0x08000000 */
+
+#define GPIO_CRL_CNF7_Pos (30U)
+#define GPIO_CRL_CNF7_Msk (0x3U << GPIO_CRL_CNF7_Pos) /*!< 0xC0000000 */
+#define GPIO_CRL_CNF7 GPIO_CRL_CNF7_Msk /*!< CNF7[1:0] bits (Port x configuration bits, pin 7) */
+#define GPIO_CRL_CNF7_0 (0x1U << GPIO_CRL_CNF7_Pos) /*!< 0x40000000 */
+#define GPIO_CRL_CNF7_1 (0x2U << GPIO_CRL_CNF7_Pos) /*!< 0x80000000 */
+
+/******************* Bit definition for GPIO_CRH register *******************/
+#define GPIO_CRH_MODE_Pos (0U)
+#define GPIO_CRH_MODE_Msk (0x33333333U << GPIO_CRH_MODE_Pos) /*!< 0x33333333 */
+#define GPIO_CRH_MODE GPIO_CRH_MODE_Msk /*!< Port x mode bits */
+
+#define GPIO_CRH_MODE8_Pos (0U)
+#define GPIO_CRH_MODE8_Msk (0x3U << GPIO_CRH_MODE8_Pos) /*!< 0x00000003 */
+#define GPIO_CRH_MODE8 GPIO_CRH_MODE8_Msk /*!< MODE8[1:0] bits (Port x mode bits, pin 8) */
+#define GPIO_CRH_MODE8_0 (0x1U << GPIO_CRH_MODE8_Pos) /*!< 0x00000001 */
+#define GPIO_CRH_MODE8_1 (0x2U << GPIO_CRH_MODE8_Pos) /*!< 0x00000002 */
+
+#define GPIO_CRH_MODE9_Pos (4U)
+#define GPIO_CRH_MODE9_Msk (0x3U << GPIO_CRH_MODE9_Pos) /*!< 0x00000030 */
+#define GPIO_CRH_MODE9 GPIO_CRH_MODE9_Msk /*!< MODE9[1:0] bits (Port x mode bits, pin 9) */
+#define GPIO_CRH_MODE9_0 (0x1U << GPIO_CRH_MODE9_Pos) /*!< 0x00000010 */
+#define GPIO_CRH_MODE9_1 (0x2U << GPIO_CRH_MODE9_Pos) /*!< 0x00000020 */
+
+#define GPIO_CRH_MODE10_Pos (8U)
+#define GPIO_CRH_MODE10_Msk (0x3U << GPIO_CRH_MODE10_Pos) /*!< 0x00000300 */
+#define GPIO_CRH_MODE10 GPIO_CRH_MODE10_Msk /*!< MODE10[1:0] bits (Port x mode bits, pin 10) */
+#define GPIO_CRH_MODE10_0 (0x1U << GPIO_CRH_MODE10_Pos) /*!< 0x00000100 */
+#define GPIO_CRH_MODE10_1 (0x2U << GPIO_CRH_MODE10_Pos) /*!< 0x00000200 */
+
+#define GPIO_CRH_MODE11_Pos (12U)
+#define GPIO_CRH_MODE11_Msk (0x3U << GPIO_CRH_MODE11_Pos) /*!< 0x00003000 */
+#define GPIO_CRH_MODE11 GPIO_CRH_MODE11_Msk /*!< MODE11[1:0] bits (Port x mode bits, pin 11) */
+#define GPIO_CRH_MODE11_0 (0x1U << GPIO_CRH_MODE11_Pos) /*!< 0x00001000 */
+#define GPIO_CRH_MODE11_1 (0x2U << GPIO_CRH_MODE11_Pos) /*!< 0x00002000 */
+
+#define GPIO_CRH_MODE12_Pos (16U)
+#define GPIO_CRH_MODE12_Msk (0x3U << GPIO_CRH_MODE12_Pos) /*!< 0x00030000 */
+#define GPIO_CRH_MODE12 GPIO_CRH_MODE12_Msk /*!< MODE12[1:0] bits (Port x mode bits, pin 12) */
+#define GPIO_CRH_MODE12_0 (0x1U << GPIO_CRH_MODE12_Pos) /*!< 0x00010000 */
+#define GPIO_CRH_MODE12_1 (0x2U << GPIO_CRH_MODE12_Pos) /*!< 0x00020000 */
+
+#define GPIO_CRH_MODE13_Pos (20U)
+#define GPIO_CRH_MODE13_Msk (0x3U << GPIO_CRH_MODE13_Pos) /*!< 0x00300000 */
+#define GPIO_CRH_MODE13 GPIO_CRH_MODE13_Msk /*!< MODE13[1:0] bits (Port x mode bits, pin 13) */
+#define GPIO_CRH_MODE13_0 (0x1U << GPIO_CRH_MODE13_Pos) /*!< 0x00100000 */
+#define GPIO_CRH_MODE13_1 (0x2U << GPIO_CRH_MODE13_Pos) /*!< 0x00200000 */
+
+#define GPIO_CRH_MODE14_Pos (24U)
+#define GPIO_CRH_MODE14_Msk (0x3U << GPIO_CRH_MODE14_Pos) /*!< 0x03000000 */
+#define GPIO_CRH_MODE14 GPIO_CRH_MODE14_Msk /*!< MODE14[1:0] bits (Port x mode bits, pin 14) */
+#define GPIO_CRH_MODE14_0 (0x1U << GPIO_CRH_MODE14_Pos) /*!< 0x01000000 */
+#define GPIO_CRH_MODE14_1 (0x2U << GPIO_CRH_MODE14_Pos) /*!< 0x02000000 */
+
+#define GPIO_CRH_MODE15_Pos (28U)
+#define GPIO_CRH_MODE15_Msk (0x3U << GPIO_CRH_MODE15_Pos) /*!< 0x30000000 */
+#define GPIO_CRH_MODE15 GPIO_CRH_MODE15_Msk /*!< MODE15[1:0] bits (Port x mode bits, pin 15) */
+#define GPIO_CRH_MODE15_0 (0x1U << GPIO_CRH_MODE15_Pos) /*!< 0x10000000 */
+#define GPIO_CRH_MODE15_1 (0x2U << GPIO_CRH_MODE15_Pos) /*!< 0x20000000 */
+
+#define GPIO_CRH_CNF_Pos (2U)
+#define GPIO_CRH_CNF_Msk (0x33333333U << GPIO_CRH_CNF_Pos) /*!< 0xCCCCCCCC */
+#define GPIO_CRH_CNF GPIO_CRH_CNF_Msk /*!< Port x configuration bits */
+
+#define GPIO_CRH_CNF8_Pos (2U)
+#define GPIO_CRH_CNF8_Msk (0x3U << GPIO_CRH_CNF8_Pos) /*!< 0x0000000C */
+#define GPIO_CRH_CNF8 GPIO_CRH_CNF8_Msk /*!< CNF8[1:0] bits (Port x configuration bits, pin 8) */
+#define GPIO_CRH_CNF8_0 (0x1U << GPIO_CRH_CNF8_Pos) /*!< 0x00000004 */
+#define GPIO_CRH_CNF8_1 (0x2U << GPIO_CRH_CNF8_Pos) /*!< 0x00000008 */
+
+#define GPIO_CRH_CNF9_Pos (6U)
+#define GPIO_CRH_CNF9_Msk (0x3U << GPIO_CRH_CNF9_Pos) /*!< 0x000000C0 */
+#define GPIO_CRH_CNF9 GPIO_CRH_CNF9_Msk /*!< CNF9[1:0] bits (Port x configuration bits, pin 9) */
+#define GPIO_CRH_CNF9_0 (0x1U << GPIO_CRH_CNF9_Pos) /*!< 0x00000040 */
+#define GPIO_CRH_CNF9_1 (0x2U << GPIO_CRH_CNF9_Pos) /*!< 0x00000080 */
+
+#define GPIO_CRH_CNF10_Pos (10U)
+#define GPIO_CRH_CNF10_Msk (0x3U << GPIO_CRH_CNF10_Pos) /*!< 0x00000C00 */
+#define GPIO_CRH_CNF10 GPIO_CRH_CNF10_Msk /*!< CNF10[1:0] bits (Port x configuration bits, pin 10) */
+#define GPIO_CRH_CNF10_0 (0x1U << GPIO_CRH_CNF10_Pos) /*!< 0x00000400 */
+#define GPIO_CRH_CNF10_1 (0x2U << GPIO_CRH_CNF10_Pos) /*!< 0x00000800 */
+
+#define GPIO_CRH_CNF11_Pos (14U)
+#define GPIO_CRH_CNF11_Msk (0x3U << GPIO_CRH_CNF11_Pos) /*!< 0x0000C000 */
+#define GPIO_CRH_CNF11 GPIO_CRH_CNF11_Msk /*!< CNF11[1:0] bits (Port x configuration bits, pin 11) */
+#define GPIO_CRH_CNF11_0 (0x1U << GPIO_CRH_CNF11_Pos) /*!< 0x00004000 */
+#define GPIO_CRH_CNF11_1 (0x2U << GPIO_CRH_CNF11_Pos) /*!< 0x00008000 */
+
+#define GPIO_CRH_CNF12_Pos (18U)
+#define GPIO_CRH_CNF12_Msk (0x3U << GPIO_CRH_CNF12_Pos) /*!< 0x000C0000 */
+#define GPIO_CRH_CNF12 GPIO_CRH_CNF12_Msk /*!< CNF12[1:0] bits (Port x configuration bits, pin 12) */
+#define GPIO_CRH_CNF12_0 (0x1U << GPIO_CRH_CNF12_Pos) /*!< 0x00040000 */
+#define GPIO_CRH_CNF12_1 (0x2U << GPIO_CRH_CNF12_Pos) /*!< 0x00080000 */
+
+#define GPIO_CRH_CNF13_Pos (22U)
+#define GPIO_CRH_CNF13_Msk (0x3U << GPIO_CRH_CNF13_Pos) /*!< 0x00C00000 */
+#define GPIO_CRH_CNF13 GPIO_CRH_CNF13_Msk /*!< CNF13[1:0] bits (Port x configuration bits, pin 13) */
+#define GPIO_CRH_CNF13_0 (0x1U << GPIO_CRH_CNF13_Pos) /*!< 0x00400000 */
+#define GPIO_CRH_CNF13_1 (0x2U << GPIO_CRH_CNF13_Pos) /*!< 0x00800000 */
+
+#define GPIO_CRH_CNF14_Pos (26U)
+#define GPIO_CRH_CNF14_Msk (0x3U << GPIO_CRH_CNF14_Pos) /*!< 0x0C000000 */
+#define GPIO_CRH_CNF14 GPIO_CRH_CNF14_Msk /*!< CNF14[1:0] bits (Port x configuration bits, pin 14) */
+#define GPIO_CRH_CNF14_0 (0x1U << GPIO_CRH_CNF14_Pos) /*!< 0x04000000 */
+#define GPIO_CRH_CNF14_1 (0x2U << GPIO_CRH_CNF14_Pos) /*!< 0x08000000 */
+
+#define GPIO_CRH_CNF15_Pos (30U)
+#define GPIO_CRH_CNF15_Msk (0x3U << GPIO_CRH_CNF15_Pos) /*!< 0xC0000000 */
+#define GPIO_CRH_CNF15 GPIO_CRH_CNF15_Msk /*!< CNF15[1:0] bits (Port x configuration bits, pin 15) */
+#define GPIO_CRH_CNF15_0 (0x1U << GPIO_CRH_CNF15_Pos) /*!< 0x40000000 */
+#define GPIO_CRH_CNF15_1 (0x2U << GPIO_CRH_CNF15_Pos) /*!< 0x80000000 */
+
+/*!<****************** Bit definition for GPIO_IDR register *******************/
+#define GPIO_IDR_IDR0_Pos (0U)
+#define GPIO_IDR_IDR0_Msk (0x1U << GPIO_IDR_IDR0_Pos) /*!< 0x00000001 */
+#define GPIO_IDR_IDR0 GPIO_IDR_IDR0_Msk /*!< Port input data, bit 0 */
+#define GPIO_IDR_IDR1_Pos (1U)
+#define GPIO_IDR_IDR1_Msk (0x1U << GPIO_IDR_IDR1_Pos) /*!< 0x00000002 */
+#define GPIO_IDR_IDR1 GPIO_IDR_IDR1_Msk /*!< Port input data, bit 1 */
+#define GPIO_IDR_IDR2_Pos (2U)
+#define GPIO_IDR_IDR2_Msk (0x1U << GPIO_IDR_IDR2_Pos) /*!< 0x00000004 */
+#define GPIO_IDR_IDR2 GPIO_IDR_IDR2_Msk /*!< Port input data, bit 2 */
+#define GPIO_IDR_IDR3_Pos (3U)
+#define GPIO_IDR_IDR3_Msk (0x1U << GPIO_IDR_IDR3_Pos) /*!< 0x00000008 */
+#define GPIO_IDR_IDR3 GPIO_IDR_IDR3_Msk /*!< Port input data, bit 3 */
+#define GPIO_IDR_IDR4_Pos (4U)
+#define GPIO_IDR_IDR4_Msk (0x1U << GPIO_IDR_IDR4_Pos) /*!< 0x00000010 */
+#define GPIO_IDR_IDR4 GPIO_IDR_IDR4_Msk /*!< Port input data, bit 4 */
+#define GPIO_IDR_IDR5_Pos (5U)
+#define GPIO_IDR_IDR5_Msk (0x1U << GPIO_IDR_IDR5_Pos) /*!< 0x00000020 */
+#define GPIO_IDR_IDR5 GPIO_IDR_IDR5_Msk /*!< Port input data, bit 5 */
+#define GPIO_IDR_IDR6_Pos (6U)
+#define GPIO_IDR_IDR6_Msk (0x1U << GPIO_IDR_IDR6_Pos) /*!< 0x00000040 */
+#define GPIO_IDR_IDR6 GPIO_IDR_IDR6_Msk /*!< Port input data, bit 6 */
+#define GPIO_IDR_IDR7_Pos (7U)
+#define GPIO_IDR_IDR7_Msk (0x1U << GPIO_IDR_IDR7_Pos) /*!< 0x00000080 */
+#define GPIO_IDR_IDR7 GPIO_IDR_IDR7_Msk /*!< Port input data, bit 7 */
+#define GPIO_IDR_IDR8_Pos (8U)
+#define GPIO_IDR_IDR8_Msk (0x1U << GPIO_IDR_IDR8_Pos) /*!< 0x00000100 */
+#define GPIO_IDR_IDR8 GPIO_IDR_IDR8_Msk /*!< Port input data, bit 8 */
+#define GPIO_IDR_IDR9_Pos (9U)
+#define GPIO_IDR_IDR9_Msk (0x1U << GPIO_IDR_IDR9_Pos) /*!< 0x00000200 */
+#define GPIO_IDR_IDR9 GPIO_IDR_IDR9_Msk /*!< Port input data, bit 9 */
+#define GPIO_IDR_IDR10_Pos (10U)
+#define GPIO_IDR_IDR10_Msk (0x1U << GPIO_IDR_IDR10_Pos) /*!< 0x00000400 */
+#define GPIO_IDR_IDR10 GPIO_IDR_IDR10_Msk /*!< Port input data, bit 10 */
+#define GPIO_IDR_IDR11_Pos (11U)
+#define GPIO_IDR_IDR11_Msk (0x1U << GPIO_IDR_IDR11_Pos) /*!< 0x00000800 */
+#define GPIO_IDR_IDR11 GPIO_IDR_IDR11_Msk /*!< Port input data, bit 11 */
+#define GPIO_IDR_IDR12_Pos (12U)
+#define GPIO_IDR_IDR12_Msk (0x1U << GPIO_IDR_IDR12_Pos) /*!< 0x00001000 */
+#define GPIO_IDR_IDR12 GPIO_IDR_IDR12_Msk /*!< Port input data, bit 12 */
+#define GPIO_IDR_IDR13_Pos (13U)
+#define GPIO_IDR_IDR13_Msk (0x1U << GPIO_IDR_IDR13_Pos) /*!< 0x00002000 */
+#define GPIO_IDR_IDR13 GPIO_IDR_IDR13_Msk /*!< Port input data, bit 13 */
+#define GPIO_IDR_IDR14_Pos (14U)
+#define GPIO_IDR_IDR14_Msk (0x1U << GPIO_IDR_IDR14_Pos) /*!< 0x00004000 */
+#define GPIO_IDR_IDR14 GPIO_IDR_IDR14_Msk /*!< Port input data, bit 14 */
+#define GPIO_IDR_IDR15_Pos (15U)
+#define GPIO_IDR_IDR15_Msk (0x1U << GPIO_IDR_IDR15_Pos) /*!< 0x00008000 */
+#define GPIO_IDR_IDR15 GPIO_IDR_IDR15_Msk /*!< Port input data, bit 15 */
+
+/******************* Bit definition for GPIO_ODR register *******************/
+#define GPIO_ODR_ODR0_Pos (0U)
+#define GPIO_ODR_ODR0_Msk (0x1U << GPIO_ODR_ODR0_Pos) /*!< 0x00000001 */
+#define GPIO_ODR_ODR0 GPIO_ODR_ODR0_Msk /*!< Port output data, bit 0 */
+#define GPIO_ODR_ODR1_Pos (1U)
+#define GPIO_ODR_ODR1_Msk (0x1U << GPIO_ODR_ODR1_Pos) /*!< 0x00000002 */
+#define GPIO_ODR_ODR1 GPIO_ODR_ODR1_Msk /*!< Port output data, bit 1 */
+#define GPIO_ODR_ODR2_Pos (2U)
+#define GPIO_ODR_ODR2_Msk (0x1U << GPIO_ODR_ODR2_Pos) /*!< 0x00000004 */
+#define GPIO_ODR_ODR2 GPIO_ODR_ODR2_Msk /*!< Port output data, bit 2 */
+#define GPIO_ODR_ODR3_Pos (3U)
+#define GPIO_ODR_ODR3_Msk (0x1U << GPIO_ODR_ODR3_Pos) /*!< 0x00000008 */
+#define GPIO_ODR_ODR3 GPIO_ODR_ODR3_Msk /*!< Port output data, bit 3 */
+#define GPIO_ODR_ODR4_Pos (4U)
+#define GPIO_ODR_ODR4_Msk (0x1U << GPIO_ODR_ODR4_Pos) /*!< 0x00000010 */
+#define GPIO_ODR_ODR4 GPIO_ODR_ODR4_Msk /*!< Port output data, bit 4 */
+#define GPIO_ODR_ODR5_Pos (5U)
+#define GPIO_ODR_ODR5_Msk (0x1U << GPIO_ODR_ODR5_Pos) /*!< 0x00000020 */
+#define GPIO_ODR_ODR5 GPIO_ODR_ODR5_Msk /*!< Port output data, bit 5 */
+#define GPIO_ODR_ODR6_Pos (6U)
+#define GPIO_ODR_ODR6_Msk (0x1U << GPIO_ODR_ODR6_Pos) /*!< 0x00000040 */
+#define GPIO_ODR_ODR6 GPIO_ODR_ODR6_Msk /*!< Port output data, bit 6 */
+#define GPIO_ODR_ODR7_Pos (7U)
+#define GPIO_ODR_ODR7_Msk (0x1U << GPIO_ODR_ODR7_Pos) /*!< 0x00000080 */
+#define GPIO_ODR_ODR7 GPIO_ODR_ODR7_Msk /*!< Port output data, bit 7 */
+#define GPIO_ODR_ODR8_Pos (8U)
+#define GPIO_ODR_ODR8_Msk (0x1U << GPIO_ODR_ODR8_Pos) /*!< 0x00000100 */
+#define GPIO_ODR_ODR8 GPIO_ODR_ODR8_Msk /*!< Port output data, bit 8 */
+#define GPIO_ODR_ODR9_Pos (9U)
+#define GPIO_ODR_ODR9_Msk (0x1U << GPIO_ODR_ODR9_Pos) /*!< 0x00000200 */
+#define GPIO_ODR_ODR9 GPIO_ODR_ODR9_Msk /*!< Port output data, bit 9 */
+#define GPIO_ODR_ODR10_Pos (10U)
+#define GPIO_ODR_ODR10_Msk (0x1U << GPIO_ODR_ODR10_Pos) /*!< 0x00000400 */
+#define GPIO_ODR_ODR10 GPIO_ODR_ODR10_Msk /*!< Port output data, bit 10 */
+#define GPIO_ODR_ODR11_Pos (11U)
+#define GPIO_ODR_ODR11_Msk (0x1U << GPIO_ODR_ODR11_Pos) /*!< 0x00000800 */
+#define GPIO_ODR_ODR11 GPIO_ODR_ODR11_Msk /*!< Port output data, bit 11 */
+#define GPIO_ODR_ODR12_Pos (12U)
+#define GPIO_ODR_ODR12_Msk (0x1U << GPIO_ODR_ODR12_Pos) /*!< 0x00001000 */
+#define GPIO_ODR_ODR12 GPIO_ODR_ODR12_Msk /*!< Port output data, bit 12 */
+#define GPIO_ODR_ODR13_Pos (13U)
+#define GPIO_ODR_ODR13_Msk (0x1U << GPIO_ODR_ODR13_Pos) /*!< 0x00002000 */
+#define GPIO_ODR_ODR13 GPIO_ODR_ODR13_Msk /*!< Port output data, bit 13 */
+#define GPIO_ODR_ODR14_Pos (14U)
+#define GPIO_ODR_ODR14_Msk (0x1U << GPIO_ODR_ODR14_Pos) /*!< 0x00004000 */
+#define GPIO_ODR_ODR14 GPIO_ODR_ODR14_Msk /*!< Port output data, bit 14 */
+#define GPIO_ODR_ODR15_Pos (15U)
+#define GPIO_ODR_ODR15_Msk (0x1U << GPIO_ODR_ODR15_Pos) /*!< 0x00008000 */
+#define GPIO_ODR_ODR15 GPIO_ODR_ODR15_Msk /*!< Port output data, bit 15 */
+
+/****************** Bit definition for GPIO_BSRR register *******************/
+#define GPIO_BSRR_BS0_Pos (0U)
+#define GPIO_BSRR_BS0_Msk (0x1U << GPIO_BSRR_BS0_Pos) /*!< 0x00000001 */
+#define GPIO_BSRR_BS0 GPIO_BSRR_BS0_Msk /*!< Port x Set bit 0 */
+#define GPIO_BSRR_BS1_Pos (1U)
+#define GPIO_BSRR_BS1_Msk (0x1U << GPIO_BSRR_BS1_Pos) /*!< 0x00000002 */
+#define GPIO_BSRR_BS1 GPIO_BSRR_BS1_Msk /*!< Port x Set bit 1 */
+#define GPIO_BSRR_BS2_Pos (2U)
+#define GPIO_BSRR_BS2_Msk (0x1U << GPIO_BSRR_BS2_Pos) /*!< 0x00000004 */
+#define GPIO_BSRR_BS2 GPIO_BSRR_BS2_Msk /*!< Port x Set bit 2 */
+#define GPIO_BSRR_BS3_Pos (3U)
+#define GPIO_BSRR_BS3_Msk (0x1U << GPIO_BSRR_BS3_Pos) /*!< 0x00000008 */
+#define GPIO_BSRR_BS3 GPIO_BSRR_BS3_Msk /*!< Port x Set bit 3 */
+#define GPIO_BSRR_BS4_Pos (4U)
+#define GPIO_BSRR_BS4_Msk (0x1U << GPIO_BSRR_BS4_Pos) /*!< 0x00000010 */
+#define GPIO_BSRR_BS4 GPIO_BSRR_BS4_Msk /*!< Port x Set bit 4 */
+#define GPIO_BSRR_BS5_Pos (5U)
+#define GPIO_BSRR_BS5_Msk (0x1U << GPIO_BSRR_BS5_Pos) /*!< 0x00000020 */
+#define GPIO_BSRR_BS5 GPIO_BSRR_BS5_Msk /*!< Port x Set bit 5 */
+#define GPIO_BSRR_BS6_Pos (6U)
+#define GPIO_BSRR_BS6_Msk (0x1U << GPIO_BSRR_BS6_Pos) /*!< 0x00000040 */
+#define GPIO_BSRR_BS6 GPIO_BSRR_BS6_Msk /*!< Port x Set bit 6 */
+#define GPIO_BSRR_BS7_Pos (7U)
+#define GPIO_BSRR_BS7_Msk (0x1U << GPIO_BSRR_BS7_Pos) /*!< 0x00000080 */
+#define GPIO_BSRR_BS7 GPIO_BSRR_BS7_Msk /*!< Port x Set bit 7 */
+#define GPIO_BSRR_BS8_Pos (8U)
+#define GPIO_BSRR_BS8_Msk (0x1U << GPIO_BSRR_BS8_Pos) /*!< 0x00000100 */
+#define GPIO_BSRR_BS8 GPIO_BSRR_BS8_Msk /*!< Port x Set bit 8 */
+#define GPIO_BSRR_BS9_Pos (9U)
+#define GPIO_BSRR_BS9_Msk (0x1U << GPIO_BSRR_BS9_Pos) /*!< 0x00000200 */
+#define GPIO_BSRR_BS9 GPIO_BSRR_BS9_Msk /*!< Port x Set bit 9 */
+#define GPIO_BSRR_BS10_Pos (10U)
+#define GPIO_BSRR_BS10_Msk (0x1U << GPIO_BSRR_BS10_Pos) /*!< 0x00000400 */
+#define GPIO_BSRR_BS10 GPIO_BSRR_BS10_Msk /*!< Port x Set bit 10 */
+#define GPIO_BSRR_BS11_Pos (11U)
+#define GPIO_BSRR_BS11_Msk (0x1U << GPIO_BSRR_BS11_Pos) /*!< 0x00000800 */
+#define GPIO_BSRR_BS11 GPIO_BSRR_BS11_Msk /*!< Port x Set bit 11 */
+#define GPIO_BSRR_BS12_Pos (12U)
+#define GPIO_BSRR_BS12_Msk (0x1U << GPIO_BSRR_BS12_Pos) /*!< 0x00001000 */
+#define GPIO_BSRR_BS12 GPIO_BSRR_BS12_Msk /*!< Port x Set bit 12 */
+#define GPIO_BSRR_BS13_Pos (13U)
+#define GPIO_BSRR_BS13_Msk (0x1U << GPIO_BSRR_BS13_Pos) /*!< 0x00002000 */
+#define GPIO_BSRR_BS13 GPIO_BSRR_BS13_Msk /*!< Port x Set bit 13 */
+#define GPIO_BSRR_BS14_Pos (14U)
+#define GPIO_BSRR_BS14_Msk (0x1U << GPIO_BSRR_BS14_Pos) /*!< 0x00004000 */
+#define GPIO_BSRR_BS14 GPIO_BSRR_BS14_Msk /*!< Port x Set bit 14 */
+#define GPIO_BSRR_BS15_Pos (15U)
+#define GPIO_BSRR_BS15_Msk (0x1U << GPIO_BSRR_BS15_Pos) /*!< 0x00008000 */
+#define GPIO_BSRR_BS15 GPIO_BSRR_BS15_Msk /*!< Port x Set bit 15 */
+
+#define GPIO_BSRR_BR0_Pos (16U)
+#define GPIO_BSRR_BR0_Msk (0x1U << GPIO_BSRR_BR0_Pos) /*!< 0x00010000 */
+#define GPIO_BSRR_BR0 GPIO_BSRR_BR0_Msk /*!< Port x Reset bit 0 */
+#define GPIO_BSRR_BR1_Pos (17U)
+#define GPIO_BSRR_BR1_Msk (0x1U << GPIO_BSRR_BR1_Pos) /*!< 0x00020000 */
+#define GPIO_BSRR_BR1 GPIO_BSRR_BR1_Msk /*!< Port x Reset bit 1 */
+#define GPIO_BSRR_BR2_Pos (18U)
+#define GPIO_BSRR_BR2_Msk (0x1U << GPIO_BSRR_BR2_Pos) /*!< 0x00040000 */
+#define GPIO_BSRR_BR2 GPIO_BSRR_BR2_Msk /*!< Port x Reset bit 2 */
+#define GPIO_BSRR_BR3_Pos (19U)
+#define GPIO_BSRR_BR3_Msk (0x1U << GPIO_BSRR_BR3_Pos) /*!< 0x00080000 */
+#define GPIO_BSRR_BR3 GPIO_BSRR_BR3_Msk /*!< Port x Reset bit 3 */
+#define GPIO_BSRR_BR4_Pos (20U)
+#define GPIO_BSRR_BR4_Msk (0x1U << GPIO_BSRR_BR4_Pos) /*!< 0x00100000 */
+#define GPIO_BSRR_BR4 GPIO_BSRR_BR4_Msk /*!< Port x Reset bit 4 */
+#define GPIO_BSRR_BR5_Pos (21U)
+#define GPIO_BSRR_BR5_Msk (0x1U << GPIO_BSRR_BR5_Pos) /*!< 0x00200000 */
+#define GPIO_BSRR_BR5 GPIO_BSRR_BR5_Msk /*!< Port x Reset bit 5 */
+#define GPIO_BSRR_BR6_Pos (22U)
+#define GPIO_BSRR_BR6_Msk (0x1U << GPIO_BSRR_BR6_Pos) /*!< 0x00400000 */
+#define GPIO_BSRR_BR6 GPIO_BSRR_BR6_Msk /*!< Port x Reset bit 6 */
+#define GPIO_BSRR_BR7_Pos (23U)
+#define GPIO_BSRR_BR7_Msk (0x1U << GPIO_BSRR_BR7_Pos) /*!< 0x00800000 */
+#define GPIO_BSRR_BR7 GPIO_BSRR_BR7_Msk /*!< Port x Reset bit 7 */
+#define GPIO_BSRR_BR8_Pos (24U)
+#define GPIO_BSRR_BR8_Msk (0x1U << GPIO_BSRR_BR8_Pos) /*!< 0x01000000 */
+#define GPIO_BSRR_BR8 GPIO_BSRR_BR8_Msk /*!< Port x Reset bit 8 */
+#define GPIO_BSRR_BR9_Pos (25U)
+#define GPIO_BSRR_BR9_Msk (0x1U << GPIO_BSRR_BR9_Pos) /*!< 0x02000000 */
+#define GPIO_BSRR_BR9 GPIO_BSRR_BR9_Msk /*!< Port x Reset bit 9 */
+#define GPIO_BSRR_BR10_Pos (26U)
+#define GPIO_BSRR_BR10_Msk (0x1U << GPIO_BSRR_BR10_Pos) /*!< 0x04000000 */
+#define GPIO_BSRR_BR10 GPIO_BSRR_BR10_Msk /*!< Port x Reset bit 10 */
+#define GPIO_BSRR_BR11_Pos (27U)
+#define GPIO_BSRR_BR11_Msk (0x1U << GPIO_BSRR_BR11_Pos) /*!< 0x08000000 */
+#define GPIO_BSRR_BR11 GPIO_BSRR_BR11_Msk /*!< Port x Reset bit 11 */
+#define GPIO_BSRR_BR12_Pos (28U)
+#define GPIO_BSRR_BR12_Msk (0x1U << GPIO_BSRR_BR12_Pos) /*!< 0x10000000 */
+#define GPIO_BSRR_BR12 GPIO_BSRR_BR12_Msk /*!< Port x Reset bit 12 */
+#define GPIO_BSRR_BR13_Pos (29U)
+#define GPIO_BSRR_BR13_Msk (0x1U << GPIO_BSRR_BR13_Pos) /*!< 0x20000000 */
+#define GPIO_BSRR_BR13 GPIO_BSRR_BR13_Msk /*!< Port x Reset bit 13 */
+#define GPIO_BSRR_BR14_Pos (30U)
+#define GPIO_BSRR_BR14_Msk (0x1U << GPIO_BSRR_BR14_Pos) /*!< 0x40000000 */
+#define GPIO_BSRR_BR14 GPIO_BSRR_BR14_Msk /*!< Port x Reset bit 14 */
+#define GPIO_BSRR_BR15_Pos (31U)
+#define GPIO_BSRR_BR15_Msk (0x1U << GPIO_BSRR_BR15_Pos) /*!< 0x80000000 */
+#define GPIO_BSRR_BR15 GPIO_BSRR_BR15_Msk /*!< Port x Reset bit 15 */
+
+/******************* Bit definition for GPIO_BRR register *******************/
+#define GPIO_BRR_BR0_Pos (0U)
+#define GPIO_BRR_BR0_Msk (0x1U << GPIO_BRR_BR0_Pos) /*!< 0x00000001 */
+#define GPIO_BRR_BR0 GPIO_BRR_BR0_Msk /*!< Port x Reset bit 0 */
+#define GPIO_BRR_BR1_Pos (1U)
+#define GPIO_BRR_BR1_Msk (0x1U << GPIO_BRR_BR1_Pos) /*!< 0x00000002 */
+#define GPIO_BRR_BR1 GPIO_BRR_BR1_Msk /*!< Port x Reset bit 1 */
+#define GPIO_BRR_BR2_Pos (2U)
+#define GPIO_BRR_BR2_Msk (0x1U << GPIO_BRR_BR2_Pos) /*!< 0x00000004 */
+#define GPIO_BRR_BR2 GPIO_BRR_BR2_Msk /*!< Port x Reset bit 2 */
+#define GPIO_BRR_BR3_Pos (3U)
+#define GPIO_BRR_BR3_Msk (0x1U << GPIO_BRR_BR3_Pos) /*!< 0x00000008 */
+#define GPIO_BRR_BR3 GPIO_BRR_BR3_Msk /*!< Port x Reset bit 3 */
+#define GPIO_BRR_BR4_Pos (4U)
+#define GPIO_BRR_BR4_Msk (0x1U << GPIO_BRR_BR4_Pos) /*!< 0x00000010 */
+#define GPIO_BRR_BR4 GPIO_BRR_BR4_Msk /*!< Port x Reset bit 4 */
+#define GPIO_BRR_BR5_Pos (5U)
+#define GPIO_BRR_BR5_Msk (0x1U << GPIO_BRR_BR5_Pos) /*!< 0x00000020 */
+#define GPIO_BRR_BR5 GPIO_BRR_BR5_Msk /*!< Port x Reset bit 5 */
+#define GPIO_BRR_BR6_Pos (6U)
+#define GPIO_BRR_BR6_Msk (0x1U << GPIO_BRR_BR6_Pos) /*!< 0x00000040 */
+#define GPIO_BRR_BR6 GPIO_BRR_BR6_Msk /*!< Port x Reset bit 6 */
+#define GPIO_BRR_BR7_Pos (7U)
+#define GPIO_BRR_BR7_Msk (0x1U << GPIO_BRR_BR7_Pos) /*!< 0x00000080 */
+#define GPIO_BRR_BR7 GPIO_BRR_BR7_Msk /*!< Port x Reset bit 7 */
+#define GPIO_BRR_BR8_Pos (8U)
+#define GPIO_BRR_BR8_Msk (0x1U << GPIO_BRR_BR8_Pos) /*!< 0x00000100 */
+#define GPIO_BRR_BR8 GPIO_BRR_BR8_Msk /*!< Port x Reset bit 8 */
+#define GPIO_BRR_BR9_Pos (9U)
+#define GPIO_BRR_BR9_Msk (0x1U << GPIO_BRR_BR9_Pos) /*!< 0x00000200 */
+#define GPIO_BRR_BR9 GPIO_BRR_BR9_Msk /*!< Port x Reset bit 9 */
+#define GPIO_BRR_BR10_Pos (10U)
+#define GPIO_BRR_BR10_Msk (0x1U << GPIO_BRR_BR10_Pos) /*!< 0x00000400 */
+#define GPIO_BRR_BR10 GPIO_BRR_BR10_Msk /*!< Port x Reset bit 10 */
+#define GPIO_BRR_BR11_Pos (11U)
+#define GPIO_BRR_BR11_Msk (0x1U << GPIO_BRR_BR11_Pos) /*!< 0x00000800 */
+#define GPIO_BRR_BR11 GPIO_BRR_BR11_Msk /*!< Port x Reset bit 11 */
+#define GPIO_BRR_BR12_Pos (12U)
+#define GPIO_BRR_BR12_Msk (0x1U << GPIO_BRR_BR12_Pos) /*!< 0x00001000 */
+#define GPIO_BRR_BR12 GPIO_BRR_BR12_Msk /*!< Port x Reset bit 12 */
+#define GPIO_BRR_BR13_Pos (13U)
+#define GPIO_BRR_BR13_Msk (0x1U << GPIO_BRR_BR13_Pos) /*!< 0x00002000 */
+#define GPIO_BRR_BR13 GPIO_BRR_BR13_Msk /*!< Port x Reset bit 13 */
+#define GPIO_BRR_BR14_Pos (14U)
+#define GPIO_BRR_BR14_Msk (0x1U << GPIO_BRR_BR14_Pos) /*!< 0x00004000 */
+#define GPIO_BRR_BR14 GPIO_BRR_BR14_Msk /*!< Port x Reset bit 14 */
+#define GPIO_BRR_BR15_Pos (15U)
+#define GPIO_BRR_BR15_Msk (0x1U << GPIO_BRR_BR15_Pos) /*!< 0x00008000 */
+#define GPIO_BRR_BR15 GPIO_BRR_BR15_Msk /*!< Port x Reset bit 15 */
+
+/****************** Bit definition for GPIO_LCKR register *******************/
+#define GPIO_LCKR_LCK0_Pos (0U)
+#define GPIO_LCKR_LCK0_Msk (0x1U << GPIO_LCKR_LCK0_Pos) /*!< 0x00000001 */
+#define GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk /*!< Port x Lock bit 0 */
+#define GPIO_LCKR_LCK1_Pos (1U)
+#define GPIO_LCKR_LCK1_Msk (0x1U << GPIO_LCKR_LCK1_Pos) /*!< 0x00000002 */
+#define GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk /*!< Port x Lock bit 1 */
+#define GPIO_LCKR_LCK2_Pos (2U)
+#define GPIO_LCKR_LCK2_Msk (0x1U << GPIO_LCKR_LCK2_Pos) /*!< 0x00000004 */
+#define GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk /*!< Port x Lock bit 2 */
+#define GPIO_LCKR_LCK3_Pos (3U)
+#define GPIO_LCKR_LCK3_Msk (0x1U << GPIO_LCKR_LCK3_Pos) /*!< 0x00000008 */
+#define GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk /*!< Port x Lock bit 3 */
+#define GPIO_LCKR_LCK4_Pos (4U)
+#define GPIO_LCKR_LCK4_Msk (0x1U << GPIO_LCKR_LCK4_Pos) /*!< 0x00000010 */
+#define GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk /*!< Port x Lock bit 4 */
+#define GPIO_LCKR_LCK5_Pos (5U)
+#define GPIO_LCKR_LCK5_Msk (0x1U << GPIO_LCKR_LCK5_Pos) /*!< 0x00000020 */
+#define GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk /*!< Port x Lock bit 5 */
+#define GPIO_LCKR_LCK6_Pos (6U)
+#define GPIO_LCKR_LCK6_Msk (0x1U << GPIO_LCKR_LCK6_Pos) /*!< 0x00000040 */
+#define GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk /*!< Port x Lock bit 6 */
+#define GPIO_LCKR_LCK7_Pos (7U)
+#define GPIO_LCKR_LCK7_Msk (0x1U << GPIO_LCKR_LCK7_Pos) /*!< 0x00000080 */
+#define GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk /*!< Port x Lock bit 7 */
+#define GPIO_LCKR_LCK8_Pos (8U)
+#define GPIO_LCKR_LCK8_Msk (0x1U << GPIO_LCKR_LCK8_Pos) /*!< 0x00000100 */
+#define GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk /*!< Port x Lock bit 8 */
+#define GPIO_LCKR_LCK9_Pos (9U)
+#define GPIO_LCKR_LCK9_Msk (0x1U << GPIO_LCKR_LCK9_Pos) /*!< 0x00000200 */
+#define GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk /*!< Port x Lock bit 9 */
+#define GPIO_LCKR_LCK10_Pos (10U)
+#define GPIO_LCKR_LCK10_Msk (0x1U << GPIO_LCKR_LCK10_Pos) /*!< 0x00000400 */
+#define GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk /*!< Port x Lock bit 10 */
+#define GPIO_LCKR_LCK11_Pos (11U)
+#define GPIO_LCKR_LCK11_Msk (0x1U << GPIO_LCKR_LCK11_Pos) /*!< 0x00000800 */
+#define GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk /*!< Port x Lock bit 11 */
+#define GPIO_LCKR_LCK12_Pos (12U)
+#define GPIO_LCKR_LCK12_Msk (0x1U << GPIO_LCKR_LCK12_Pos) /*!< 0x00001000 */
+#define GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk /*!< Port x Lock bit 12 */
+#define GPIO_LCKR_LCK13_Pos (13U)
+#define GPIO_LCKR_LCK13_Msk (0x1U << GPIO_LCKR_LCK13_Pos) /*!< 0x00002000 */
+#define GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk /*!< Port x Lock bit 13 */
+#define GPIO_LCKR_LCK14_Pos (14U)
+#define GPIO_LCKR_LCK14_Msk (0x1U << GPIO_LCKR_LCK14_Pos) /*!< 0x00004000 */
+#define GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk /*!< Port x Lock bit 14 */
+#define GPIO_LCKR_LCK15_Pos (15U)
+#define GPIO_LCKR_LCK15_Msk (0x1U << GPIO_LCKR_LCK15_Pos) /*!< 0x00008000 */
+#define GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk /*!< Port x Lock bit 15 */
+#define GPIO_LCKR_LCKK_Pos (16U)
+#define GPIO_LCKR_LCKK_Msk (0x1U << GPIO_LCKR_LCKK_Pos) /*!< 0x00010000 */
+#define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk /*!< Lock key */
+
+/*----------------------------------------------------------------------------*/
+
+/****************** Bit definition for AFIO_EVCR register *******************/
+#define AFIO_EVCR_PIN_Pos (0U)
+#define AFIO_EVCR_PIN_Msk (0xFU << AFIO_EVCR_PIN_Pos) /*!< 0x0000000F */
+#define AFIO_EVCR_PIN AFIO_EVCR_PIN_Msk /*!< PIN[3:0] bits (Pin selection) */
+#define AFIO_EVCR_PIN_0 (0x1U << AFIO_EVCR_PIN_Pos) /*!< 0x00000001 */
+#define AFIO_EVCR_PIN_1 (0x2U << AFIO_EVCR_PIN_Pos) /*!< 0x00000002 */
+#define AFIO_EVCR_PIN_2 (0x4U << AFIO_EVCR_PIN_Pos) /*!< 0x00000004 */
+#define AFIO_EVCR_PIN_3 (0x8U << AFIO_EVCR_PIN_Pos) /*!< 0x00000008 */
+
+/*!< PIN configuration */
+#define AFIO_EVCR_PIN_PX0 ((uint32_t)0x00000000) /*!< Pin 0 selected */
+#define AFIO_EVCR_PIN_PX1_Pos (0U)
+#define AFIO_EVCR_PIN_PX1_Msk (0x1U << AFIO_EVCR_PIN_PX1_Pos) /*!< 0x00000001 */
+#define AFIO_EVCR_PIN_PX1 AFIO_EVCR_PIN_PX1_Msk /*!< Pin 1 selected */
+#define AFIO_EVCR_PIN_PX2_Pos (1U)
+#define AFIO_EVCR_PIN_PX2_Msk (0x1U << AFIO_EVCR_PIN_PX2_Pos) /*!< 0x00000002 */
+#define AFIO_EVCR_PIN_PX2 AFIO_EVCR_PIN_PX2_Msk /*!< Pin 2 selected */
+#define AFIO_EVCR_PIN_PX3_Pos (0U)
+#define AFIO_EVCR_PIN_PX3_Msk (0x3U << AFIO_EVCR_PIN_PX3_Pos) /*!< 0x00000003 */
+#define AFIO_EVCR_PIN_PX3 AFIO_EVCR_PIN_PX3_Msk /*!< Pin 3 selected */
+#define AFIO_EVCR_PIN_PX4_Pos (2U)
+#define AFIO_EVCR_PIN_PX4_Msk (0x1U << AFIO_EVCR_PIN_PX4_Pos) /*!< 0x00000004 */
+#define AFIO_EVCR_PIN_PX4 AFIO_EVCR_PIN_PX4_Msk /*!< Pin 4 selected */
+#define AFIO_EVCR_PIN_PX5_Pos (0U)
+#define AFIO_EVCR_PIN_PX5_Msk (0x5U << AFIO_EVCR_PIN_PX5_Pos) /*!< 0x00000005 */
+#define AFIO_EVCR_PIN_PX5 AFIO_EVCR_PIN_PX5_Msk /*!< Pin 5 selected */
+#define AFIO_EVCR_PIN_PX6_Pos (1U)
+#define AFIO_EVCR_PIN_PX6_Msk (0x3U << AFIO_EVCR_PIN_PX6_Pos) /*!< 0x00000006 */
+#define AFIO_EVCR_PIN_PX6 AFIO_EVCR_PIN_PX6_Msk /*!< Pin 6 selected */
+#define AFIO_EVCR_PIN_PX7_Pos (0U)
+#define AFIO_EVCR_PIN_PX7_Msk (0x7U << AFIO_EVCR_PIN_PX7_Pos) /*!< 0x00000007 */
+#define AFIO_EVCR_PIN_PX7 AFIO_EVCR_PIN_PX7_Msk /*!< Pin 7 selected */
+#define AFIO_EVCR_PIN_PX8_Pos (3U)
+#define AFIO_EVCR_PIN_PX8_Msk (0x1U << AFIO_EVCR_PIN_PX8_Pos) /*!< 0x00000008 */
+#define AFIO_EVCR_PIN_PX8 AFIO_EVCR_PIN_PX8_Msk /*!< Pin 8 selected */
+#define AFIO_EVCR_PIN_PX9_Pos (0U)
+#define AFIO_EVCR_PIN_PX9_Msk (0x9U << AFIO_EVCR_PIN_PX9_Pos) /*!< 0x00000009 */
+#define AFIO_EVCR_PIN_PX9 AFIO_EVCR_PIN_PX9_Msk /*!< Pin 9 selected */
+#define AFIO_EVCR_PIN_PX10_Pos (1U)
+#define AFIO_EVCR_PIN_PX10_Msk (0x5U << AFIO_EVCR_PIN_PX10_Pos) /*!< 0x0000000A */
+#define AFIO_EVCR_PIN_PX10 AFIO_EVCR_PIN_PX10_Msk /*!< Pin 10 selected */
+#define AFIO_EVCR_PIN_PX11_Pos (0U)
+#define AFIO_EVCR_PIN_PX11_Msk (0xBU << AFIO_EVCR_PIN_PX11_Pos) /*!< 0x0000000B */
+#define AFIO_EVCR_PIN_PX11 AFIO_EVCR_PIN_PX11_Msk /*!< Pin 11 selected */
+#define AFIO_EVCR_PIN_PX12_Pos (2U)
+#define AFIO_EVCR_PIN_PX12_Msk (0x3U << AFIO_EVCR_PIN_PX12_Pos) /*!< 0x0000000C */
+#define AFIO_EVCR_PIN_PX12 AFIO_EVCR_PIN_PX12_Msk /*!< Pin 12 selected */
+#define AFIO_EVCR_PIN_PX13_Pos (0U)
+#define AFIO_EVCR_PIN_PX13_Msk (0xDU << AFIO_EVCR_PIN_PX13_Pos) /*!< 0x0000000D */
+#define AFIO_EVCR_PIN_PX13 AFIO_EVCR_PIN_PX13_Msk /*!< Pin 13 selected */
+#define AFIO_EVCR_PIN_PX14_Pos (1U)
+#define AFIO_EVCR_PIN_PX14_Msk (0x7U << AFIO_EVCR_PIN_PX14_Pos) /*!< 0x0000000E */
+#define AFIO_EVCR_PIN_PX14 AFIO_EVCR_PIN_PX14_Msk /*!< Pin 14 selected */
+#define AFIO_EVCR_PIN_PX15_Pos (0U)
+#define AFIO_EVCR_PIN_PX15_Msk (0xFU << AFIO_EVCR_PIN_PX15_Pos) /*!< 0x0000000F */
+#define AFIO_EVCR_PIN_PX15 AFIO_EVCR_PIN_PX15_Msk /*!< Pin 15 selected */
+
+#define AFIO_EVCR_PORT_Pos (4U)
+#define AFIO_EVCR_PORT_Msk (0x7U << AFIO_EVCR_PORT_Pos) /*!< 0x00000070 */
+#define AFIO_EVCR_PORT AFIO_EVCR_PORT_Msk /*!< PORT[2:0] bits (Port selection) */
+#define AFIO_EVCR_PORT_0 (0x1U << AFIO_EVCR_PORT_Pos) /*!< 0x00000010 */
+#define AFIO_EVCR_PORT_1 (0x2U << AFIO_EVCR_PORT_Pos) /*!< 0x00000020 */
+#define AFIO_EVCR_PORT_2 (0x4U << AFIO_EVCR_PORT_Pos) /*!< 0x00000040 */
+
+/*!< PORT configuration */
+#define AFIO_EVCR_PORT_PA ((uint32_t)0x00000000) /*!< Port A selected */
+#define AFIO_EVCR_PORT_PB_Pos (4U)
+#define AFIO_EVCR_PORT_PB_Msk (0x1U << AFIO_EVCR_PORT_PB_Pos) /*!< 0x00000010 */
+#define AFIO_EVCR_PORT_PB AFIO_EVCR_PORT_PB_Msk /*!< Port B selected */
+#define AFIO_EVCR_PORT_PC_Pos (5U)
+#define AFIO_EVCR_PORT_PC_Msk (0x1U << AFIO_EVCR_PORT_PC_Pos) /*!< 0x00000020 */
+#define AFIO_EVCR_PORT_PC AFIO_EVCR_PORT_PC_Msk /*!< Port C selected */
+#define AFIO_EVCR_PORT_PD_Pos (4U)
+#define AFIO_EVCR_PORT_PD_Msk (0x3U << AFIO_EVCR_PORT_PD_Pos) /*!< 0x00000030 */
+#define AFIO_EVCR_PORT_PD AFIO_EVCR_PORT_PD_Msk /*!< Port D selected */
+#define AFIO_EVCR_PORT_PE_Pos (6U)
+#define AFIO_EVCR_PORT_PE_Msk (0x1U << AFIO_EVCR_PORT_PE_Pos) /*!< 0x00000040 */
+#define AFIO_EVCR_PORT_PE AFIO_EVCR_PORT_PE_Msk /*!< Port E selected */
+
+#define AFIO_EVCR_EVOE_Pos (7U)
+#define AFIO_EVCR_EVOE_Msk (0x1U << AFIO_EVCR_EVOE_Pos) /*!< 0x00000080 */
+#define AFIO_EVCR_EVOE AFIO_EVCR_EVOE_Msk /*!< Event Output Enable */
+
+/****************** Bit definition for AFIO_MAPR register *******************/
+#define AFIO_MAPR_SPI1_REMAP_Pos (0U)
+#define AFIO_MAPR_SPI1_REMAP_Msk (0x1U << AFIO_MAPR_SPI1_REMAP_Pos) /*!< 0x00000001 */
+#define AFIO_MAPR_SPI1_REMAP AFIO_MAPR_SPI1_REMAP_Msk /*!< SPI1 remapping */
+#define AFIO_MAPR_I2C1_REMAP_Pos (1U)
+#define AFIO_MAPR_I2C1_REMAP_Msk (0x1U << AFIO_MAPR_I2C1_REMAP_Pos) /*!< 0x00000002 */
+#define AFIO_MAPR_I2C1_REMAP AFIO_MAPR_I2C1_REMAP_Msk /*!< I2C1 remapping */
+#define AFIO_MAPR_USART1_REMAP_Pos (2U)
+#define AFIO_MAPR_USART1_REMAP_Msk (0x1U << AFIO_MAPR_USART1_REMAP_Pos) /*!< 0x00000004 */
+#define AFIO_MAPR_USART1_REMAP AFIO_MAPR_USART1_REMAP_Msk /*!< USART1 remapping */
+#define AFIO_MAPR_USART2_REMAP_Pos (3U)
+#define AFIO_MAPR_USART2_REMAP_Msk (0x1U << AFIO_MAPR_USART2_REMAP_Pos) /*!< 0x00000008 */
+#define AFIO_MAPR_USART2_REMAP AFIO_MAPR_USART2_REMAP_Msk /*!< USART2 remapping */
+
+#define AFIO_MAPR_USART3_REMAP_Pos (4U)
+#define AFIO_MAPR_USART3_REMAP_Msk (0x3U << AFIO_MAPR_USART3_REMAP_Pos) /*!< 0x00000030 */
+#define AFIO_MAPR_USART3_REMAP AFIO_MAPR_USART3_REMAP_Msk /*!< USART3_REMAP[1:0] bits (USART3 remapping) */
+#define AFIO_MAPR_USART3_REMAP_0 (0x1U << AFIO_MAPR_USART3_REMAP_Pos) /*!< 0x00000010 */
+#define AFIO_MAPR_USART3_REMAP_1 (0x2U << AFIO_MAPR_USART3_REMAP_Pos) /*!< 0x00000020 */
+
+/* USART3_REMAP configuration */
+#define AFIO_MAPR_USART3_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14) */
+#define AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Pos (4U)
+#define AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Msk (0x1U << AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Pos) /*!< 0x00000010 */
+#define AFIO_MAPR_USART3_REMAP_PARTIALREMAP AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Msk /*!< Partial remap (TX/PC10, RX/PC11, CK/PC12, CTS/PB13, RTS/PB14) */
+#define AFIO_MAPR_USART3_REMAP_FULLREMAP_Pos (4U)
+#define AFIO_MAPR_USART3_REMAP_FULLREMAP_Msk (0x3U << AFIO_MAPR_USART3_REMAP_FULLREMAP_Pos) /*!< 0x00000030 */
+#define AFIO_MAPR_USART3_REMAP_FULLREMAP AFIO_MAPR_USART3_REMAP_FULLREMAP_Msk /*!< Full remap (TX/PD8, RX/PD9, CK/PD10, CTS/PD11, RTS/PD12) */
+
+#define AFIO_MAPR_TIM1_REMAP_Pos (6U)
+#define AFIO_MAPR_TIM1_REMAP_Msk (0x3U << AFIO_MAPR_TIM1_REMAP_Pos) /*!< 0x000000C0 */
+#define AFIO_MAPR_TIM1_REMAP AFIO_MAPR_TIM1_REMAP_Msk /*!< TIM1_REMAP[1:0] bits (TIM1 remapping) */
+#define AFIO_MAPR_TIM1_REMAP_0 (0x1U << AFIO_MAPR_TIM1_REMAP_Pos) /*!< 0x00000040 */
+#define AFIO_MAPR_TIM1_REMAP_1 (0x2U << AFIO_MAPR_TIM1_REMAP_Pos) /*!< 0x00000080 */
+
+/*!< TIM1_REMAP configuration */
+#define AFIO_MAPR_TIM1_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15) */
+#define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Pos (6U)
+#define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Msk (0x1U << AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Pos) /*!< 0x00000040 */
+#define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Msk /*!< Partial remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PA6, CH1N/PA7, CH2N/PB0, CH3N/PB1) */
+#define AFIO_MAPR_TIM1_REMAP_FULLREMAP_Pos (6U)
+#define AFIO_MAPR_TIM1_REMAP_FULLREMAP_Msk (0x3U << AFIO_MAPR_TIM1_REMAP_FULLREMAP_Pos) /*!< 0x000000C0 */
+#define AFIO_MAPR_TIM1_REMAP_FULLREMAP AFIO_MAPR_TIM1_REMAP_FULLREMAP_Msk /*!< Full remap (ETR/PE7, CH1/PE9, CH2/PE11, CH3/PE13, CH4/PE14, BKIN/PE15, CH1N/PE8, CH2N/PE10, CH3N/PE12) */
+
+#define AFIO_MAPR_TIM2_REMAP_Pos (8U)
+#define AFIO_MAPR_TIM2_REMAP_Msk (0x3U << AFIO_MAPR_TIM2_REMAP_Pos) /*!< 0x00000300 */
+#define AFIO_MAPR_TIM2_REMAP AFIO_MAPR_TIM2_REMAP_Msk /*!< TIM2_REMAP[1:0] bits (TIM2 remapping) */
+#define AFIO_MAPR_TIM2_REMAP_0 (0x1U << AFIO_MAPR_TIM2_REMAP_Pos) /*!< 0x00000100 */
+#define AFIO_MAPR_TIM2_REMAP_1 (0x2U << AFIO_MAPR_TIM2_REMAP_Pos) /*!< 0x00000200 */
+
+/*!< TIM2_REMAP configuration */
+#define AFIO_MAPR_TIM2_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3) */
+#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Pos (8U)
+#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Msk (0x1U << AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Pos) /*!< 0x00000100 */
+#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1 AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Msk /*!< Partial remap (CH1/ETR/PA15, CH2/PB3, CH3/PA2, CH4/PA3) */
+#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2_Pos (9U)
+#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2_Msk (0x1U << AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2_Pos) /*!< 0x00000200 */
+#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2 AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2_Msk /*!< Partial remap (CH1/ETR/PA0, CH2/PA1, CH3/PB10, CH4/PB11) */
+#define AFIO_MAPR_TIM2_REMAP_FULLREMAP_Pos (8U)
+#define AFIO_MAPR_TIM2_REMAP_FULLREMAP_Msk (0x3U << AFIO_MAPR_TIM2_REMAP_FULLREMAP_Pos) /*!< 0x00000300 */
+#define AFIO_MAPR_TIM2_REMAP_FULLREMAP AFIO_MAPR_TIM2_REMAP_FULLREMAP_Msk /*!< Full remap (CH1/ETR/PA15, CH2/PB3, CH3/PB10, CH4/PB11) */
+
+#define AFIO_MAPR_TIM3_REMAP_Pos (10U)
+#define AFIO_MAPR_TIM3_REMAP_Msk (0x3U << AFIO_MAPR_TIM3_REMAP_Pos) /*!< 0x00000C00 */
+#define AFIO_MAPR_TIM3_REMAP AFIO_MAPR_TIM3_REMAP_Msk /*!< TIM3_REMAP[1:0] bits (TIM3 remapping) */
+#define AFIO_MAPR_TIM3_REMAP_0 (0x1U << AFIO_MAPR_TIM3_REMAP_Pos) /*!< 0x00000400 */
+#define AFIO_MAPR_TIM3_REMAP_1 (0x2U << AFIO_MAPR_TIM3_REMAP_Pos) /*!< 0x00000800 */
+
+/*!< TIM3_REMAP configuration */
+#define AFIO_MAPR_TIM3_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1) */
+#define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Pos (11U)
+#define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Msk (0x1U << AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Pos) /*!< 0x00000800 */
+#define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Msk /*!< Partial remap (CH1/PB4, CH2/PB5, CH3/PB0, CH4/PB1) */
+#define AFIO_MAPR_TIM3_REMAP_FULLREMAP_Pos (10U)
+#define AFIO_MAPR_TIM3_REMAP_FULLREMAP_Msk (0x3U << AFIO_MAPR_TIM3_REMAP_FULLREMAP_Pos) /*!< 0x00000C00 */
+#define AFIO_MAPR_TIM3_REMAP_FULLREMAP AFIO_MAPR_TIM3_REMAP_FULLREMAP_Msk /*!< Full remap (CH1/PC6, CH2/PC7, CH3/PC8, CH4/PC9) */
+
+#define AFIO_MAPR_TIM4_REMAP_Pos (12U)
+#define AFIO_MAPR_TIM4_REMAP_Msk (0x1U << AFIO_MAPR_TIM4_REMAP_Pos) /*!< 0x00001000 */
+#define AFIO_MAPR_TIM4_REMAP AFIO_MAPR_TIM4_REMAP_Msk /*!< TIM4_REMAP bit (TIM4 remapping) */
+
+
+#define AFIO_MAPR_PD01_REMAP_Pos (15U)
+#define AFIO_MAPR_PD01_REMAP_Msk (0x1U << AFIO_MAPR_PD01_REMAP_Pos) /*!< 0x00008000 */
+#define AFIO_MAPR_PD01_REMAP AFIO_MAPR_PD01_REMAP_Msk /*!< Port D0/Port D1 mapping on OSC_IN/OSC_OUT */
+#define AFIO_MAPR_TIM5CH4_IREMAP_Pos (16U)
+#define AFIO_MAPR_TIM5CH4_IREMAP_Msk (0x1U << AFIO_MAPR_TIM5CH4_IREMAP_Pos) /*!< 0x00010000 */
+#define AFIO_MAPR_TIM5CH4_IREMAP AFIO_MAPR_TIM5CH4_IREMAP_Msk /*!< TIM5 Channel4 Internal Remap */
+
+/*!< SWJ_CFG configuration */
+#define AFIO_MAPR_SWJ_CFG_Pos (24U)
+#define AFIO_MAPR_SWJ_CFG_Msk (0x7U << AFIO_MAPR_SWJ_CFG_Pos) /*!< 0x07000000 */
+#define AFIO_MAPR_SWJ_CFG AFIO_MAPR_SWJ_CFG_Msk /*!< SWJ_CFG[2:0] bits (Serial Wire JTAG configuration) */
+#define AFIO_MAPR_SWJ_CFG_0 (0x1U << AFIO_MAPR_SWJ_CFG_Pos) /*!< 0x01000000 */
+#define AFIO_MAPR_SWJ_CFG_1 (0x2U << AFIO_MAPR_SWJ_CFG_Pos) /*!< 0x02000000 */
+#define AFIO_MAPR_SWJ_CFG_2 (0x4U << AFIO_MAPR_SWJ_CFG_Pos) /*!< 0x04000000 */
+
+#define AFIO_MAPR_SWJ_CFG_RESET ((uint32_t)0x00000000) /*!< Full SWJ (JTAG-DP + SW-DP) : Reset State */
+#define AFIO_MAPR_SWJ_CFG_NOJNTRST_Pos (24U)
+#define AFIO_MAPR_SWJ_CFG_NOJNTRST_Msk (0x1U << AFIO_MAPR_SWJ_CFG_NOJNTRST_Pos) /*!< 0x01000000 */
+#define AFIO_MAPR_SWJ_CFG_NOJNTRST AFIO_MAPR_SWJ_CFG_NOJNTRST_Msk /*!< Full SWJ (JTAG-DP + SW-DP) but without JNTRST */
+#define AFIO_MAPR_SWJ_CFG_JTAGDISABLE_Pos (25U)
+#define AFIO_MAPR_SWJ_CFG_JTAGDISABLE_Msk (0x1U << AFIO_MAPR_SWJ_CFG_JTAGDISABLE_Pos) /*!< 0x02000000 */
+#define AFIO_MAPR_SWJ_CFG_JTAGDISABLE AFIO_MAPR_SWJ_CFG_JTAGDISABLE_Msk /*!< JTAG-DP Disabled and SW-DP Enabled */
+#define AFIO_MAPR_SWJ_CFG_DISABLE_Pos (26U)
+#define AFIO_MAPR_SWJ_CFG_DISABLE_Msk (0x1U << AFIO_MAPR_SWJ_CFG_DISABLE_Pos) /*!< 0x04000000 */
+#define AFIO_MAPR_SWJ_CFG_DISABLE AFIO_MAPR_SWJ_CFG_DISABLE_Msk /*!< JTAG-DP Disabled and SW-DP Disabled */
+
+
+/***************** Bit definition for AFIO_EXTICR1 register *****************/
+#define AFIO_EXTICR1_EXTI0_Pos (0U)
+#define AFIO_EXTICR1_EXTI0_Msk (0xFU << AFIO_EXTICR1_EXTI0_Pos) /*!< 0x0000000F */
+#define AFIO_EXTICR1_EXTI0 AFIO_EXTICR1_EXTI0_Msk /*!< EXTI 0 configuration */
+#define AFIO_EXTICR1_EXTI1_Pos (4U)
+#define AFIO_EXTICR1_EXTI1_Msk (0xFU << AFIO_EXTICR1_EXTI1_Pos) /*!< 0x000000F0 */
+#define AFIO_EXTICR1_EXTI1 AFIO_EXTICR1_EXTI1_Msk /*!< EXTI 1 configuration */
+#define AFIO_EXTICR1_EXTI2_Pos (8U)
+#define AFIO_EXTICR1_EXTI2_Msk (0xFU << AFIO_EXTICR1_EXTI2_Pos) /*!< 0x00000F00 */
+#define AFIO_EXTICR1_EXTI2 AFIO_EXTICR1_EXTI2_Msk /*!< EXTI 2 configuration */
+#define AFIO_EXTICR1_EXTI3_Pos (12U)
+#define AFIO_EXTICR1_EXTI3_Msk (0xFU << AFIO_EXTICR1_EXTI3_Pos) /*!< 0x0000F000 */
+#define AFIO_EXTICR1_EXTI3 AFIO_EXTICR1_EXTI3_Msk /*!< EXTI 3 configuration */
+
+/*!< EXTI0 configuration */
+#define AFIO_EXTICR1_EXTI0_PA ((uint32_t)0x00000000) /*!< PA[0] pin */
+#define AFIO_EXTICR1_EXTI0_PB_Pos (0U)
+#define AFIO_EXTICR1_EXTI0_PB_Msk (0x1U << AFIO_EXTICR1_EXTI0_PB_Pos) /*!< 0x00000001 */
+#define AFIO_EXTICR1_EXTI0_PB AFIO_EXTICR1_EXTI0_PB_Msk /*!< PB[0] pin */
+#define AFIO_EXTICR1_EXTI0_PC_Pos (1U)
+#define AFIO_EXTICR1_EXTI0_PC_Msk (0x1U << AFIO_EXTICR1_EXTI0_PC_Pos) /*!< 0x00000002 */
+#define AFIO_EXTICR1_EXTI0_PC AFIO_EXTICR1_EXTI0_PC_Msk /*!< PC[0] pin */
+#define AFIO_EXTICR1_EXTI0_PD_Pos (0U)
+#define AFIO_EXTICR1_EXTI0_PD_Msk (0x3U << AFIO_EXTICR1_EXTI0_PD_Pos) /*!< 0x00000003 */
+#define AFIO_EXTICR1_EXTI0_PD AFIO_EXTICR1_EXTI0_PD_Msk /*!< PD[0] pin */
+#define AFIO_EXTICR1_EXTI0_PE_Pos (2U)
+#define AFIO_EXTICR1_EXTI0_PE_Msk (0x1U << AFIO_EXTICR1_EXTI0_PE_Pos) /*!< 0x00000004 */
+#define AFIO_EXTICR1_EXTI0_PE AFIO_EXTICR1_EXTI0_PE_Msk /*!< PE[0] pin */
+#define AFIO_EXTICR1_EXTI0_PF_Pos (0U)
+#define AFIO_EXTICR1_EXTI0_PF_Msk (0x5U << AFIO_EXTICR1_EXTI0_PF_Pos) /*!< 0x00000005 */
+#define AFIO_EXTICR1_EXTI0_PF AFIO_EXTICR1_EXTI0_PF_Msk /*!< PF[0] pin */
+#define AFIO_EXTICR1_EXTI0_PG_Pos (1U)
+#define AFIO_EXTICR1_EXTI0_PG_Msk (0x3U << AFIO_EXTICR1_EXTI0_PG_Pos) /*!< 0x00000006 */
+#define AFIO_EXTICR1_EXTI0_PG AFIO_EXTICR1_EXTI0_PG_Msk /*!< PG[0] pin */
+
+/*!< EXTI1 configuration */
+#define AFIO_EXTICR1_EXTI1_PA ((uint32_t)0x00000000) /*!< PA[1] pin */
+#define AFIO_EXTICR1_EXTI1_PB_Pos (4U)
+#define AFIO_EXTICR1_EXTI1_PB_Msk (0x1U << AFIO_EXTICR1_EXTI1_PB_Pos) /*!< 0x00000010 */
+#define AFIO_EXTICR1_EXTI1_PB AFIO_EXTICR1_EXTI1_PB_Msk /*!< PB[1] pin */
+#define AFIO_EXTICR1_EXTI1_PC_Pos (5U)
+#define AFIO_EXTICR1_EXTI1_PC_Msk (0x1U << AFIO_EXTICR1_EXTI1_PC_Pos) /*!< 0x00000020 */
+#define AFIO_EXTICR1_EXTI1_PC AFIO_EXTICR1_EXTI1_PC_Msk /*!< PC[1] pin */
+#define AFIO_EXTICR1_EXTI1_PD_Pos (4U)
+#define AFIO_EXTICR1_EXTI1_PD_Msk (0x3U << AFIO_EXTICR1_EXTI1_PD_Pos) /*!< 0x00000030 */
+#define AFIO_EXTICR1_EXTI1_PD AFIO_EXTICR1_EXTI1_PD_Msk /*!< PD[1] pin */
+#define AFIO_EXTICR1_EXTI1_PE_Pos (6U)
+#define AFIO_EXTICR1_EXTI1_PE_Msk (0x1U << AFIO_EXTICR1_EXTI1_PE_Pos) /*!< 0x00000040 */
+#define AFIO_EXTICR1_EXTI1_PE AFIO_EXTICR1_EXTI1_PE_Msk /*!< PE[1] pin */
+#define AFIO_EXTICR1_EXTI1_PF_Pos (4U)
+#define AFIO_EXTICR1_EXTI1_PF_Msk (0x5U << AFIO_EXTICR1_EXTI1_PF_Pos) /*!< 0x00000050 */
+#define AFIO_EXTICR1_EXTI1_PF AFIO_EXTICR1_EXTI1_PF_Msk /*!< PF[1] pin */
+#define AFIO_EXTICR1_EXTI1_PG_Pos (5U)
+#define AFIO_EXTICR1_EXTI1_PG_Msk (0x3U << AFIO_EXTICR1_EXTI1_PG_Pos) /*!< 0x00000060 */
+#define AFIO_EXTICR1_EXTI1_PG AFIO_EXTICR1_EXTI1_PG_Msk /*!< PG[1] pin */
+
+/*!< EXTI2 configuration */
+#define AFIO_EXTICR1_EXTI2_PA ((uint32_t)0x00000000) /*!< PA[2] pin */
+#define AFIO_EXTICR1_EXTI2_PB_Pos (8U)
+#define AFIO_EXTICR1_EXTI2_PB_Msk (0x1U << AFIO_EXTICR1_EXTI2_PB_Pos) /*!< 0x00000100 */
+#define AFIO_EXTICR1_EXTI2_PB AFIO_EXTICR1_EXTI2_PB_Msk /*!< PB[2] pin */
+#define AFIO_EXTICR1_EXTI2_PC_Pos (9U)
+#define AFIO_EXTICR1_EXTI2_PC_Msk (0x1U << AFIO_EXTICR1_EXTI2_PC_Pos) /*!< 0x00000200 */
+#define AFIO_EXTICR1_EXTI2_PC AFIO_EXTICR1_EXTI2_PC_Msk /*!< PC[2] pin */
+#define AFIO_EXTICR1_EXTI2_PD_Pos (8U)
+#define AFIO_EXTICR1_EXTI2_PD_Msk (0x3U << AFIO_EXTICR1_EXTI2_PD_Pos) /*!< 0x00000300 */
+#define AFIO_EXTICR1_EXTI2_PD AFIO_EXTICR1_EXTI2_PD_Msk /*!< PD[2] pin */
+#define AFIO_EXTICR1_EXTI2_PE_Pos (10U)
+#define AFIO_EXTICR1_EXTI2_PE_Msk (0x1U << AFIO_EXTICR1_EXTI2_PE_Pos) /*!< 0x00000400 */
+#define AFIO_EXTICR1_EXTI2_PE AFIO_EXTICR1_EXTI2_PE_Msk /*!< PE[2] pin */
+#define AFIO_EXTICR1_EXTI2_PF_Pos (8U)
+#define AFIO_EXTICR1_EXTI2_PF_Msk (0x5U << AFIO_EXTICR1_EXTI2_PF_Pos) /*!< 0x00000500 */
+#define AFIO_EXTICR1_EXTI2_PF AFIO_EXTICR1_EXTI2_PF_Msk /*!< PF[2] pin */
+#define AFIO_EXTICR1_EXTI2_PG_Pos (9U)
+#define AFIO_EXTICR1_EXTI2_PG_Msk (0x3U << AFIO_EXTICR1_EXTI2_PG_Pos) /*!< 0x00000600 */
+#define AFIO_EXTICR1_EXTI2_PG AFIO_EXTICR1_EXTI2_PG_Msk /*!< PG[2] pin */
+
+/*!< EXTI3 configuration */
+#define AFIO_EXTICR1_EXTI3_PA ((uint32_t)0x00000000) /*!< PA[3] pin */
+#define AFIO_EXTICR1_EXTI3_PB_Pos (12U)
+#define AFIO_EXTICR1_EXTI3_PB_Msk (0x1U << AFIO_EXTICR1_EXTI3_PB_Pos) /*!< 0x00001000 */
+#define AFIO_EXTICR1_EXTI3_PB AFIO_EXTICR1_EXTI3_PB_Msk /*!< PB[3] pin */
+#define AFIO_EXTICR1_EXTI3_PC_Pos (13U)
+#define AFIO_EXTICR1_EXTI3_PC_Msk (0x1U << AFIO_EXTICR1_EXTI3_PC_Pos) /*!< 0x00002000 */
+#define AFIO_EXTICR1_EXTI3_PC AFIO_EXTICR1_EXTI3_PC_Msk /*!< PC[3] pin */
+#define AFIO_EXTICR1_EXTI3_PD_Pos (12U)
+#define AFIO_EXTICR1_EXTI3_PD_Msk (0x3U << AFIO_EXTICR1_EXTI3_PD_Pos) /*!< 0x00003000 */
+#define AFIO_EXTICR1_EXTI3_PD AFIO_EXTICR1_EXTI3_PD_Msk /*!< PD[3] pin */
+#define AFIO_EXTICR1_EXTI3_PE_Pos (14U)
+#define AFIO_EXTICR1_EXTI3_PE_Msk (0x1U << AFIO_EXTICR1_EXTI3_PE_Pos) /*!< 0x00004000 */
+#define AFIO_EXTICR1_EXTI3_PE AFIO_EXTICR1_EXTI3_PE_Msk /*!< PE[3] pin */
+#define AFIO_EXTICR1_EXTI3_PF_Pos (12U)
+#define AFIO_EXTICR1_EXTI3_PF_Msk (0x5U << AFIO_EXTICR1_EXTI3_PF_Pos) /*!< 0x00005000 */
+#define AFIO_EXTICR1_EXTI3_PF AFIO_EXTICR1_EXTI3_PF_Msk /*!< PF[3] pin */
+#define AFIO_EXTICR1_EXTI3_PG_Pos (13U)
+#define AFIO_EXTICR1_EXTI3_PG_Msk (0x3U << AFIO_EXTICR1_EXTI3_PG_Pos) /*!< 0x00006000 */
+#define AFIO_EXTICR1_EXTI3_PG AFIO_EXTICR1_EXTI3_PG_Msk /*!< PG[3] pin */
+
+/***************** Bit definition for AFIO_EXTICR2 register *****************/
+#define AFIO_EXTICR2_EXTI4_Pos (0U)
+#define AFIO_EXTICR2_EXTI4_Msk (0xFU << AFIO_EXTICR2_EXTI4_Pos) /*!< 0x0000000F */
+#define AFIO_EXTICR2_EXTI4 AFIO_EXTICR2_EXTI4_Msk /*!< EXTI 4 configuration */
+#define AFIO_EXTICR2_EXTI5_Pos (4U)
+#define AFIO_EXTICR2_EXTI5_Msk (0xFU << AFIO_EXTICR2_EXTI5_Pos) /*!< 0x000000F0 */
+#define AFIO_EXTICR2_EXTI5 AFIO_EXTICR2_EXTI5_Msk /*!< EXTI 5 configuration */
+#define AFIO_EXTICR2_EXTI6_Pos (8U)
+#define AFIO_EXTICR2_EXTI6_Msk (0xFU << AFIO_EXTICR2_EXTI6_Pos) /*!< 0x00000F00 */
+#define AFIO_EXTICR2_EXTI6 AFIO_EXTICR2_EXTI6_Msk /*!< EXTI 6 configuration */
+#define AFIO_EXTICR2_EXTI7_Pos (12U)
+#define AFIO_EXTICR2_EXTI7_Msk (0xFU << AFIO_EXTICR2_EXTI7_Pos) /*!< 0x0000F000 */
+#define AFIO_EXTICR2_EXTI7 AFIO_EXTICR2_EXTI7_Msk /*!< EXTI 7 configuration */
+
+/*!< EXTI4 configuration */
+#define AFIO_EXTICR2_EXTI4_PA ((uint32_t)0x00000000) /*!< PA[4] pin */
+#define AFIO_EXTICR2_EXTI4_PB_Pos (0U)
+#define AFIO_EXTICR2_EXTI4_PB_Msk (0x1U << AFIO_EXTICR2_EXTI4_PB_Pos) /*!< 0x00000001 */
+#define AFIO_EXTICR2_EXTI4_PB AFIO_EXTICR2_EXTI4_PB_Msk /*!< PB[4] pin */
+#define AFIO_EXTICR2_EXTI4_PC_Pos (1U)
+#define AFIO_EXTICR2_EXTI4_PC_Msk (0x1U << AFIO_EXTICR2_EXTI4_PC_Pos) /*!< 0x00000002 */
+#define AFIO_EXTICR2_EXTI4_PC AFIO_EXTICR2_EXTI4_PC_Msk /*!< PC[4] pin */
+#define AFIO_EXTICR2_EXTI4_PD_Pos (0U)
+#define AFIO_EXTICR2_EXTI4_PD_Msk (0x3U << AFIO_EXTICR2_EXTI4_PD_Pos) /*!< 0x00000003 */
+#define AFIO_EXTICR2_EXTI4_PD AFIO_EXTICR2_EXTI4_PD_Msk /*!< PD[4] pin */
+#define AFIO_EXTICR2_EXTI4_PE_Pos (2U)
+#define AFIO_EXTICR2_EXTI4_PE_Msk (0x1U << AFIO_EXTICR2_EXTI4_PE_Pos) /*!< 0x00000004 */
+#define AFIO_EXTICR2_EXTI4_PE AFIO_EXTICR2_EXTI4_PE_Msk /*!< PE[4] pin */
+#define AFIO_EXTICR2_EXTI4_PF_Pos (0U)
+#define AFIO_EXTICR2_EXTI4_PF_Msk (0x5U << AFIO_EXTICR2_EXTI4_PF_Pos) /*!< 0x00000005 */
+#define AFIO_EXTICR2_EXTI4_PF AFIO_EXTICR2_EXTI4_PF_Msk /*!< PF[4] pin */
+#define AFIO_EXTICR2_EXTI4_PG_Pos (1U)
+#define AFIO_EXTICR2_EXTI4_PG_Msk (0x3U << AFIO_EXTICR2_EXTI4_PG_Pos) /*!< 0x00000006 */
+#define AFIO_EXTICR2_EXTI4_PG AFIO_EXTICR2_EXTI4_PG_Msk /*!< PG[4] pin */
+
+/* EXTI5 configuration */
+#define AFIO_EXTICR2_EXTI5_PA ((uint32_t)0x00000000) /*!< PA[5] pin */
+#define AFIO_EXTICR2_EXTI5_PB_Pos (4U)
+#define AFIO_EXTICR2_EXTI5_PB_Msk (0x1U << AFIO_EXTICR2_EXTI5_PB_Pos) /*!< 0x00000010 */
+#define AFIO_EXTICR2_EXTI5_PB AFIO_EXTICR2_EXTI5_PB_Msk /*!< PB[5] pin */
+#define AFIO_EXTICR2_EXTI5_PC_Pos (5U)
+#define AFIO_EXTICR2_EXTI5_PC_Msk (0x1U << AFIO_EXTICR2_EXTI5_PC_Pos) /*!< 0x00000020 */
+#define AFIO_EXTICR2_EXTI5_PC AFIO_EXTICR2_EXTI5_PC_Msk /*!< PC[5] pin */
+#define AFIO_EXTICR2_EXTI5_PD_Pos (4U)
+#define AFIO_EXTICR2_EXTI5_PD_Msk (0x3U << AFIO_EXTICR2_EXTI5_PD_Pos) /*!< 0x00000030 */
+#define AFIO_EXTICR2_EXTI5_PD AFIO_EXTICR2_EXTI5_PD_Msk /*!< PD[5] pin */
+#define AFIO_EXTICR2_EXTI5_PE_Pos (6U)
+#define AFIO_EXTICR2_EXTI5_PE_Msk (0x1U << AFIO_EXTICR2_EXTI5_PE_Pos) /*!< 0x00000040 */
+#define AFIO_EXTICR2_EXTI5_PE AFIO_EXTICR2_EXTI5_PE_Msk /*!< PE[5] pin */
+#define AFIO_EXTICR2_EXTI5_PF_Pos (4U)
+#define AFIO_EXTICR2_EXTI5_PF_Msk (0x5U << AFIO_EXTICR2_EXTI5_PF_Pos) /*!< 0x00000050 */
+#define AFIO_EXTICR2_EXTI5_PF AFIO_EXTICR2_EXTI5_PF_Msk /*!< PF[5] pin */
+#define AFIO_EXTICR2_EXTI5_PG_Pos (5U)
+#define AFIO_EXTICR2_EXTI5_PG_Msk (0x3U << AFIO_EXTICR2_EXTI5_PG_Pos) /*!< 0x00000060 */
+#define AFIO_EXTICR2_EXTI5_PG AFIO_EXTICR2_EXTI5_PG_Msk /*!< PG[5] pin */
+
+/*!< EXTI6 configuration */
+#define AFIO_EXTICR2_EXTI6_PA ((uint32_t)0x00000000) /*!< PA[6] pin */
+#define AFIO_EXTICR2_EXTI6_PB_Pos (8U)
+#define AFIO_EXTICR2_EXTI6_PB_Msk (0x1U << AFIO_EXTICR2_EXTI6_PB_Pos) /*!< 0x00000100 */
+#define AFIO_EXTICR2_EXTI6_PB AFIO_EXTICR2_EXTI6_PB_Msk /*!< PB[6] pin */
+#define AFIO_EXTICR2_EXTI6_PC_Pos (9U)
+#define AFIO_EXTICR2_EXTI6_PC_Msk (0x1U << AFIO_EXTICR2_EXTI6_PC_Pos) /*!< 0x00000200 */
+#define AFIO_EXTICR2_EXTI6_PC AFIO_EXTICR2_EXTI6_PC_Msk /*!< PC[6] pin */
+#define AFIO_EXTICR2_EXTI6_PD_Pos (8U)
+#define AFIO_EXTICR2_EXTI6_PD_Msk (0x3U << AFIO_EXTICR2_EXTI6_PD_Pos) /*!< 0x00000300 */
+#define AFIO_EXTICR2_EXTI6_PD AFIO_EXTICR2_EXTI6_PD_Msk /*!< PD[6] pin */
+#define AFIO_EXTICR2_EXTI6_PE_Pos (10U)
+#define AFIO_EXTICR2_EXTI6_PE_Msk (0x1U << AFIO_EXTICR2_EXTI6_PE_Pos) /*!< 0x00000400 */
+#define AFIO_EXTICR2_EXTI6_PE AFIO_EXTICR2_EXTI6_PE_Msk /*!< PE[6] pin */
+#define AFIO_EXTICR2_EXTI6_PF_Pos (8U)
+#define AFIO_EXTICR2_EXTI6_PF_Msk (0x5U << AFIO_EXTICR2_EXTI6_PF_Pos) /*!< 0x00000500 */
+#define AFIO_EXTICR2_EXTI6_PF AFIO_EXTICR2_EXTI6_PF_Msk /*!< PF[6] pin */
+#define AFIO_EXTICR2_EXTI6_PG_Pos (9U)
+#define AFIO_EXTICR2_EXTI6_PG_Msk (0x3U << AFIO_EXTICR2_EXTI6_PG_Pos) /*!< 0x00000600 */
+#define AFIO_EXTICR2_EXTI6_PG AFIO_EXTICR2_EXTI6_PG_Msk /*!< PG[6] pin */
+
+/*!< EXTI7 configuration */
+#define AFIO_EXTICR2_EXTI7_PA ((uint32_t)0x00000000) /*!< PA[7] pin */
+#define AFIO_EXTICR2_EXTI7_PB_Pos (12U)
+#define AFIO_EXTICR2_EXTI7_PB_Msk (0x1U << AFIO_EXTICR2_EXTI7_PB_Pos) /*!< 0x00001000 */
+#define AFIO_EXTICR2_EXTI7_PB AFIO_EXTICR2_EXTI7_PB_Msk /*!< PB[7] pin */
+#define AFIO_EXTICR2_EXTI7_PC_Pos (13U)
+#define AFIO_EXTICR2_EXTI7_PC_Msk (0x1U << AFIO_EXTICR2_EXTI7_PC_Pos) /*!< 0x00002000 */
+#define AFIO_EXTICR2_EXTI7_PC AFIO_EXTICR2_EXTI7_PC_Msk /*!< PC[7] pin */
+#define AFIO_EXTICR2_EXTI7_PD_Pos (12U)
+#define AFIO_EXTICR2_EXTI7_PD_Msk (0x3U << AFIO_EXTICR2_EXTI7_PD_Pos) /*!< 0x00003000 */
+#define AFIO_EXTICR2_EXTI7_PD AFIO_EXTICR2_EXTI7_PD_Msk /*!< PD[7] pin */
+#define AFIO_EXTICR2_EXTI7_PE_Pos (14U)
+#define AFIO_EXTICR2_EXTI7_PE_Msk (0x1U << AFIO_EXTICR2_EXTI7_PE_Pos) /*!< 0x00004000 */
+#define AFIO_EXTICR2_EXTI7_PE AFIO_EXTICR2_EXTI7_PE_Msk /*!< PE[7] pin */
+#define AFIO_EXTICR2_EXTI7_PF_Pos (12U)
+#define AFIO_EXTICR2_EXTI7_PF_Msk (0x5U << AFIO_EXTICR2_EXTI7_PF_Pos) /*!< 0x00005000 */
+#define AFIO_EXTICR2_EXTI7_PF AFIO_EXTICR2_EXTI7_PF_Msk /*!< PF[7] pin */
+#define AFIO_EXTICR2_EXTI7_PG_Pos (13U)
+#define AFIO_EXTICR2_EXTI7_PG_Msk (0x3U << AFIO_EXTICR2_EXTI7_PG_Pos) /*!< 0x00006000 */
+#define AFIO_EXTICR2_EXTI7_PG AFIO_EXTICR2_EXTI7_PG_Msk /*!< PG[7] pin */
+
+/***************** Bit definition for AFIO_EXTICR3 register *****************/
+#define AFIO_EXTICR3_EXTI8_Pos (0U)
+#define AFIO_EXTICR3_EXTI8_Msk (0xFU << AFIO_EXTICR3_EXTI8_Pos) /*!< 0x0000000F */
+#define AFIO_EXTICR3_EXTI8 AFIO_EXTICR3_EXTI8_Msk /*!< EXTI 8 configuration */
+#define AFIO_EXTICR3_EXTI9_Pos (4U)
+#define AFIO_EXTICR3_EXTI9_Msk (0xFU << AFIO_EXTICR3_EXTI9_Pos) /*!< 0x000000F0 */
+#define AFIO_EXTICR3_EXTI9 AFIO_EXTICR3_EXTI9_Msk /*!< EXTI 9 configuration */
+#define AFIO_EXTICR3_EXTI10_Pos (8U)
+#define AFIO_EXTICR3_EXTI10_Msk (0xFU << AFIO_EXTICR3_EXTI10_Pos) /*!< 0x00000F00 */
+#define AFIO_EXTICR3_EXTI10 AFIO_EXTICR3_EXTI10_Msk /*!< EXTI 10 configuration */
+#define AFIO_EXTICR3_EXTI11_Pos (12U)
+#define AFIO_EXTICR3_EXTI11_Msk (0xFU << AFIO_EXTICR3_EXTI11_Pos) /*!< 0x0000F000 */
+#define AFIO_EXTICR3_EXTI11 AFIO_EXTICR3_EXTI11_Msk /*!< EXTI 11 configuration */
+
+/*!< EXTI8 configuration */
+#define AFIO_EXTICR3_EXTI8_PA ((uint32_t)0x00000000) /*!< PA[8] pin */
+#define AFIO_EXTICR3_EXTI8_PB_Pos (0U)
+#define AFIO_EXTICR3_EXTI8_PB_Msk (0x1U << AFIO_EXTICR3_EXTI8_PB_Pos) /*!< 0x00000001 */
+#define AFIO_EXTICR3_EXTI8_PB AFIO_EXTICR3_EXTI8_PB_Msk /*!< PB[8] pin */
+#define AFIO_EXTICR3_EXTI8_PC_Pos (1U)
+#define AFIO_EXTICR3_EXTI8_PC_Msk (0x1U << AFIO_EXTICR3_EXTI8_PC_Pos) /*!< 0x00000002 */
+#define AFIO_EXTICR3_EXTI8_PC AFIO_EXTICR3_EXTI8_PC_Msk /*!< PC[8] pin */
+#define AFIO_EXTICR3_EXTI8_PD_Pos (0U)
+#define AFIO_EXTICR3_EXTI8_PD_Msk (0x3U << AFIO_EXTICR3_EXTI8_PD_Pos) /*!< 0x00000003 */
+#define AFIO_EXTICR3_EXTI8_PD AFIO_EXTICR3_EXTI8_PD_Msk /*!< PD[8] pin */
+#define AFIO_EXTICR3_EXTI8_PE_Pos (2U)
+#define AFIO_EXTICR3_EXTI8_PE_Msk (0x1U << AFIO_EXTICR3_EXTI8_PE_Pos) /*!< 0x00000004 */
+#define AFIO_EXTICR3_EXTI8_PE AFIO_EXTICR3_EXTI8_PE_Msk /*!< PE[8] pin */
+#define AFIO_EXTICR3_EXTI8_PF_Pos (0U)
+#define AFIO_EXTICR3_EXTI8_PF_Msk (0x5U << AFIO_EXTICR3_EXTI8_PF_Pos) /*!< 0x00000005 */
+#define AFIO_EXTICR3_EXTI8_PF AFIO_EXTICR3_EXTI8_PF_Msk /*!< PF[8] pin */
+#define AFIO_EXTICR3_EXTI8_PG_Pos (1U)
+#define AFIO_EXTICR3_EXTI8_PG_Msk (0x3U << AFIO_EXTICR3_EXTI8_PG_Pos) /*!< 0x00000006 */
+#define AFIO_EXTICR3_EXTI8_PG AFIO_EXTICR3_EXTI8_PG_Msk /*!< PG[8] pin */
+
+/*!< EXTI9 configuration */
+#define AFIO_EXTICR3_EXTI9_PA ((uint32_t)0x00000000) /*!< PA[9] pin */
+#define AFIO_EXTICR3_EXTI9_PB_Pos (4U)
+#define AFIO_EXTICR3_EXTI9_PB_Msk (0x1U << AFIO_EXTICR3_EXTI9_PB_Pos) /*!< 0x00000010 */
+#define AFIO_EXTICR3_EXTI9_PB AFIO_EXTICR3_EXTI9_PB_Msk /*!< PB[9] pin */
+#define AFIO_EXTICR3_EXTI9_PC_Pos (5U)
+#define AFIO_EXTICR3_EXTI9_PC_Msk (0x1U << AFIO_EXTICR3_EXTI9_PC_Pos) /*!< 0x00000020 */
+#define AFIO_EXTICR3_EXTI9_PC AFIO_EXTICR3_EXTI9_PC_Msk /*!< PC[9] pin */
+#define AFIO_EXTICR3_EXTI9_PD_Pos (4U)
+#define AFIO_EXTICR3_EXTI9_PD_Msk (0x3U << AFIO_EXTICR3_EXTI9_PD_Pos) /*!< 0x00000030 */
+#define AFIO_EXTICR3_EXTI9_PD AFIO_EXTICR3_EXTI9_PD_Msk /*!< PD[9] pin */
+#define AFIO_EXTICR3_EXTI9_PE_Pos (6U)
+#define AFIO_EXTICR3_EXTI9_PE_Msk (0x1U << AFIO_EXTICR3_EXTI9_PE_Pos) /*!< 0x00000040 */
+#define AFIO_EXTICR3_EXTI9_PE AFIO_EXTICR3_EXTI9_PE_Msk /*!< PE[9] pin */
+#define AFIO_EXTICR3_EXTI9_PF_Pos (4U)
+#define AFIO_EXTICR3_EXTI9_PF_Msk (0x5U << AFIO_EXTICR3_EXTI9_PF_Pos) /*!< 0x00000050 */
+#define AFIO_EXTICR3_EXTI9_PF AFIO_EXTICR3_EXTI9_PF_Msk /*!< PF[9] pin */
+#define AFIO_EXTICR3_EXTI9_PG_Pos (5U)
+#define AFIO_EXTICR3_EXTI9_PG_Msk (0x3U << AFIO_EXTICR3_EXTI9_PG_Pos) /*!< 0x00000060 */
+#define AFIO_EXTICR3_EXTI9_PG AFIO_EXTICR3_EXTI9_PG_Msk /*!< PG[9] pin */
+
+/*!< EXTI10 configuration */
+#define AFIO_EXTICR3_EXTI10_PA ((uint32_t)0x00000000) /*!< PA[10] pin */
+#define AFIO_EXTICR3_EXTI10_PB_Pos (8U)
+#define AFIO_EXTICR3_EXTI10_PB_Msk (0x1U << AFIO_EXTICR3_EXTI10_PB_Pos) /*!< 0x00000100 */
+#define AFIO_EXTICR3_EXTI10_PB AFIO_EXTICR3_EXTI10_PB_Msk /*!< PB[10] pin */
+#define AFIO_EXTICR3_EXTI10_PC_Pos (9U)
+#define AFIO_EXTICR3_EXTI10_PC_Msk (0x1U << AFIO_EXTICR3_EXTI10_PC_Pos) /*!< 0x00000200 */
+#define AFIO_EXTICR3_EXTI10_PC AFIO_EXTICR3_EXTI10_PC_Msk /*!< PC[10] pin */
+#define AFIO_EXTICR3_EXTI10_PD_Pos (8U)
+#define AFIO_EXTICR3_EXTI10_PD_Msk (0x3U << AFIO_EXTICR3_EXTI10_PD_Pos) /*!< 0x00000300 */
+#define AFIO_EXTICR3_EXTI10_PD AFIO_EXTICR3_EXTI10_PD_Msk /*!< PD[10] pin */
+#define AFIO_EXTICR3_EXTI10_PE_Pos (10U)
+#define AFIO_EXTICR3_EXTI10_PE_Msk (0x1U << AFIO_EXTICR3_EXTI10_PE_Pos) /*!< 0x00000400 */
+#define AFIO_EXTICR3_EXTI10_PE AFIO_EXTICR3_EXTI10_PE_Msk /*!< PE[10] pin */
+#define AFIO_EXTICR3_EXTI10_PF_Pos (8U)
+#define AFIO_EXTICR3_EXTI10_PF_Msk (0x5U << AFIO_EXTICR3_EXTI10_PF_Pos) /*!< 0x00000500 */
+#define AFIO_EXTICR3_EXTI10_PF AFIO_EXTICR3_EXTI10_PF_Msk /*!< PF[10] pin */
+#define AFIO_EXTICR3_EXTI10_PG_Pos (9U)
+#define AFIO_EXTICR3_EXTI10_PG_Msk (0x3U << AFIO_EXTICR3_EXTI10_PG_Pos) /*!< 0x00000600 */
+#define AFIO_EXTICR3_EXTI10_PG AFIO_EXTICR3_EXTI10_PG_Msk /*!< PG[10] pin */
+
+/*!< EXTI11 configuration */
+#define AFIO_EXTICR3_EXTI11_PA ((uint32_t)0x00000000) /*!< PA[11] pin */
+#define AFIO_EXTICR3_EXTI11_PB_Pos (12U)
+#define AFIO_EXTICR3_EXTI11_PB_Msk (0x1U << AFIO_EXTICR3_EXTI11_PB_Pos) /*!< 0x00001000 */
+#define AFIO_EXTICR3_EXTI11_PB AFIO_EXTICR3_EXTI11_PB_Msk /*!< PB[11] pin */
+#define AFIO_EXTICR3_EXTI11_PC_Pos (13U)
+#define AFIO_EXTICR3_EXTI11_PC_Msk (0x1U << AFIO_EXTICR3_EXTI11_PC_Pos) /*!< 0x00002000 */
+#define AFIO_EXTICR3_EXTI11_PC AFIO_EXTICR3_EXTI11_PC_Msk /*!< PC[11] pin */
+#define AFIO_EXTICR3_EXTI11_PD_Pos (12U)
+#define AFIO_EXTICR3_EXTI11_PD_Msk (0x3U << AFIO_EXTICR3_EXTI11_PD_Pos) /*!< 0x00003000 */
+#define AFIO_EXTICR3_EXTI11_PD AFIO_EXTICR3_EXTI11_PD_Msk /*!< PD[11] pin */
+#define AFIO_EXTICR3_EXTI11_PE_Pos (14U)
+#define AFIO_EXTICR3_EXTI11_PE_Msk (0x1U << AFIO_EXTICR3_EXTI11_PE_Pos) /*!< 0x00004000 */
+#define AFIO_EXTICR3_EXTI11_PE AFIO_EXTICR3_EXTI11_PE_Msk /*!< PE[11] pin */
+#define AFIO_EXTICR3_EXTI11_PF_Pos (12U)
+#define AFIO_EXTICR3_EXTI11_PF_Msk (0x5U << AFIO_EXTICR3_EXTI11_PF_Pos) /*!< 0x00005000 */
+#define AFIO_EXTICR3_EXTI11_PF AFIO_EXTICR3_EXTI11_PF_Msk /*!< PF[11] pin */
+#define AFIO_EXTICR3_EXTI11_PG_Pos (13U)
+#define AFIO_EXTICR3_EXTI11_PG_Msk (0x3U << AFIO_EXTICR3_EXTI11_PG_Pos) /*!< 0x00006000 */
+#define AFIO_EXTICR3_EXTI11_PG AFIO_EXTICR3_EXTI11_PG_Msk /*!< PG[11] pin */
+
+/***************** Bit definition for AFIO_EXTICR4 register *****************/
+#define AFIO_EXTICR4_EXTI12_Pos (0U)
+#define AFIO_EXTICR4_EXTI12_Msk (0xFU << AFIO_EXTICR4_EXTI12_Pos) /*!< 0x0000000F */
+#define AFIO_EXTICR4_EXTI12 AFIO_EXTICR4_EXTI12_Msk /*!< EXTI 12 configuration */
+#define AFIO_EXTICR4_EXTI13_Pos (4U)
+#define AFIO_EXTICR4_EXTI13_Msk (0xFU << AFIO_EXTICR4_EXTI13_Pos) /*!< 0x000000F0 */
+#define AFIO_EXTICR4_EXTI13 AFIO_EXTICR4_EXTI13_Msk /*!< EXTI 13 configuration */
+#define AFIO_EXTICR4_EXTI14_Pos (8U)
+#define AFIO_EXTICR4_EXTI14_Msk (0xFU << AFIO_EXTICR4_EXTI14_Pos) /*!< 0x00000F00 */
+#define AFIO_EXTICR4_EXTI14 AFIO_EXTICR4_EXTI14_Msk /*!< EXTI 14 configuration */
+#define AFIO_EXTICR4_EXTI15_Pos (12U)
+#define AFIO_EXTICR4_EXTI15_Msk (0xFU << AFIO_EXTICR4_EXTI15_Pos) /*!< 0x0000F000 */
+#define AFIO_EXTICR4_EXTI15 AFIO_EXTICR4_EXTI15_Msk /*!< EXTI 15 configuration */
+
+/* EXTI12 configuration */
+#define AFIO_EXTICR4_EXTI12_PA ((uint32_t)0x00000000) /*!< PA[12] pin */
+#define AFIO_EXTICR4_EXTI12_PB_Pos (0U)
+#define AFIO_EXTICR4_EXTI12_PB_Msk (0x1U << AFIO_EXTICR4_EXTI12_PB_Pos) /*!< 0x00000001 */
+#define AFIO_EXTICR4_EXTI12_PB AFIO_EXTICR4_EXTI12_PB_Msk /*!< PB[12] pin */
+#define AFIO_EXTICR4_EXTI12_PC_Pos (1U)
+#define AFIO_EXTICR4_EXTI12_PC_Msk (0x1U << AFIO_EXTICR4_EXTI12_PC_Pos) /*!< 0x00000002 */
+#define AFIO_EXTICR4_EXTI12_PC AFIO_EXTICR4_EXTI12_PC_Msk /*!< PC[12] pin */
+#define AFIO_EXTICR4_EXTI12_PD_Pos (0U)
+#define AFIO_EXTICR4_EXTI12_PD_Msk (0x3U << AFIO_EXTICR4_EXTI12_PD_Pos) /*!< 0x00000003 */
+#define AFIO_EXTICR4_EXTI12_PD AFIO_EXTICR4_EXTI12_PD_Msk /*!< PD[12] pin */
+#define AFIO_EXTICR4_EXTI12_PE_Pos (2U)
+#define AFIO_EXTICR4_EXTI12_PE_Msk (0x1U << AFIO_EXTICR4_EXTI12_PE_Pos) /*!< 0x00000004 */
+#define AFIO_EXTICR4_EXTI12_PE AFIO_EXTICR4_EXTI12_PE_Msk /*!< PE[12] pin */
+#define AFIO_EXTICR4_EXTI12_PF_Pos (0U)
+#define AFIO_EXTICR4_EXTI12_PF_Msk (0x5U << AFIO_EXTICR4_EXTI12_PF_Pos) /*!< 0x00000005 */
+#define AFIO_EXTICR4_EXTI12_PF AFIO_EXTICR4_EXTI12_PF_Msk /*!< PF[12] pin */
+#define AFIO_EXTICR4_EXTI12_PG_Pos (1U)
+#define AFIO_EXTICR4_EXTI12_PG_Msk (0x3U << AFIO_EXTICR4_EXTI12_PG_Pos) /*!< 0x00000006 */
+#define AFIO_EXTICR4_EXTI12_PG AFIO_EXTICR4_EXTI12_PG_Msk /*!< PG[12] pin */
+
+/* EXTI13 configuration */
+#define AFIO_EXTICR4_EXTI13_PA ((uint32_t)0x00000000) /*!< PA[13] pin */
+#define AFIO_EXTICR4_EXTI13_PB_Pos (4U)
+#define AFIO_EXTICR4_EXTI13_PB_Msk (0x1U << AFIO_EXTICR4_EXTI13_PB_Pos) /*!< 0x00000010 */
+#define AFIO_EXTICR4_EXTI13_PB AFIO_EXTICR4_EXTI13_PB_Msk /*!< PB[13] pin */
+#define AFIO_EXTICR4_EXTI13_PC_Pos (5U)
+#define AFIO_EXTICR4_EXTI13_PC_Msk (0x1U << AFIO_EXTICR4_EXTI13_PC_Pos) /*!< 0x00000020 */
+#define AFIO_EXTICR4_EXTI13_PC AFIO_EXTICR4_EXTI13_PC_Msk /*!< PC[13] pin */
+#define AFIO_EXTICR4_EXTI13_PD_Pos (4U)
+#define AFIO_EXTICR4_EXTI13_PD_Msk (0x3U << AFIO_EXTICR4_EXTI13_PD_Pos) /*!< 0x00000030 */
+#define AFIO_EXTICR4_EXTI13_PD AFIO_EXTICR4_EXTI13_PD_Msk /*!< PD[13] pin */
+#define AFIO_EXTICR4_EXTI13_PE_Pos (6U)
+#define AFIO_EXTICR4_EXTI13_PE_Msk (0x1U << AFIO_EXTICR4_EXTI13_PE_Pos) /*!< 0x00000040 */
+#define AFIO_EXTICR4_EXTI13_PE AFIO_EXTICR4_EXTI13_PE_Msk /*!< PE[13] pin */
+#define AFIO_EXTICR4_EXTI13_PF_Pos (4U)
+#define AFIO_EXTICR4_EXTI13_PF_Msk (0x5U << AFIO_EXTICR4_EXTI13_PF_Pos) /*!< 0x00000050 */
+#define AFIO_EXTICR4_EXTI13_PF AFIO_EXTICR4_EXTI13_PF_Msk /*!< PF[13] pin */
+#define AFIO_EXTICR4_EXTI13_PG_Pos (5U)
+#define AFIO_EXTICR4_EXTI13_PG_Msk (0x3U << AFIO_EXTICR4_EXTI13_PG_Pos) /*!< 0x00000060 */
+#define AFIO_EXTICR4_EXTI13_PG AFIO_EXTICR4_EXTI13_PG_Msk /*!< PG[13] pin */
+
+/*!< EXTI14 configuration */
+#define AFIO_EXTICR4_EXTI14_PA ((uint32_t)0x00000000) /*!< PA[14] pin */
+#define AFIO_EXTICR4_EXTI14_PB_Pos (8U)
+#define AFIO_EXTICR4_EXTI14_PB_Msk (0x1U << AFIO_EXTICR4_EXTI14_PB_Pos) /*!< 0x00000100 */
+#define AFIO_EXTICR4_EXTI14_PB AFIO_EXTICR4_EXTI14_PB_Msk /*!< PB[14] pin */
+#define AFIO_EXTICR4_EXTI14_PC_Pos (9U)
+#define AFIO_EXTICR4_EXTI14_PC_Msk (0x1U << AFIO_EXTICR4_EXTI14_PC_Pos) /*!< 0x00000200 */
+#define AFIO_EXTICR4_EXTI14_PC AFIO_EXTICR4_EXTI14_PC_Msk /*!< PC[14] pin */
+#define AFIO_EXTICR4_EXTI14_PD_Pos (8U)
+#define AFIO_EXTICR4_EXTI14_PD_Msk (0x3U << AFIO_EXTICR4_EXTI14_PD_Pos) /*!< 0x00000300 */
+#define AFIO_EXTICR4_EXTI14_PD AFIO_EXTICR4_EXTI14_PD_Msk /*!< PD[14] pin */
+#define AFIO_EXTICR4_EXTI14_PE_Pos (10U)
+#define AFIO_EXTICR4_EXTI14_PE_Msk (0x1U << AFIO_EXTICR4_EXTI14_PE_Pos) /*!< 0x00000400 */
+#define AFIO_EXTICR4_EXTI14_PE AFIO_EXTICR4_EXTI14_PE_Msk /*!< PE[14] pin */
+#define AFIO_EXTICR4_EXTI14_PF_Pos (8U)
+#define AFIO_EXTICR4_EXTI14_PF_Msk (0x5U << AFIO_EXTICR4_EXTI14_PF_Pos) /*!< 0x00000500 */
+#define AFIO_EXTICR4_EXTI14_PF AFIO_EXTICR4_EXTI14_PF_Msk /*!< PF[14] pin */
+#define AFIO_EXTICR4_EXTI14_PG_Pos (9U)
+#define AFIO_EXTICR4_EXTI14_PG_Msk (0x3U << AFIO_EXTICR4_EXTI14_PG_Pos) /*!< 0x00000600 */
+#define AFIO_EXTICR4_EXTI14_PG AFIO_EXTICR4_EXTI14_PG_Msk /*!< PG[14] pin */
+
+/*!< EXTI15 configuration */
+#define AFIO_EXTICR4_EXTI15_PA ((uint32_t)0x00000000) /*!< PA[15] pin */
+#define AFIO_EXTICR4_EXTI15_PB_Pos (12U)
+#define AFIO_EXTICR4_EXTI15_PB_Msk (0x1U << AFIO_EXTICR4_EXTI15_PB_Pos) /*!< 0x00001000 */
+#define AFIO_EXTICR4_EXTI15_PB AFIO_EXTICR4_EXTI15_PB_Msk /*!< PB[15] pin */
+#define AFIO_EXTICR4_EXTI15_PC_Pos (13U)
+#define AFIO_EXTICR4_EXTI15_PC_Msk (0x1U << AFIO_EXTICR4_EXTI15_PC_Pos) /*!< 0x00002000 */
+#define AFIO_EXTICR4_EXTI15_PC AFIO_EXTICR4_EXTI15_PC_Msk /*!< PC[15] pin */
+#define AFIO_EXTICR4_EXTI15_PD_Pos (12U)
+#define AFIO_EXTICR4_EXTI15_PD_Msk (0x3U << AFIO_EXTICR4_EXTI15_PD_Pos) /*!< 0x00003000 */
+#define AFIO_EXTICR4_EXTI15_PD AFIO_EXTICR4_EXTI15_PD_Msk /*!< PD[15] pin */
+#define AFIO_EXTICR4_EXTI15_PE_Pos (14U)
+#define AFIO_EXTICR4_EXTI15_PE_Msk (0x1U << AFIO_EXTICR4_EXTI15_PE_Pos) /*!< 0x00004000 */
+#define AFIO_EXTICR4_EXTI15_PE AFIO_EXTICR4_EXTI15_PE_Msk /*!< PE[15] pin */
+#define AFIO_EXTICR4_EXTI15_PF_Pos (12U)
+#define AFIO_EXTICR4_EXTI15_PF_Msk (0x5U << AFIO_EXTICR4_EXTI15_PF_Pos) /*!< 0x00005000 */
+#define AFIO_EXTICR4_EXTI15_PF AFIO_EXTICR4_EXTI15_PF_Msk /*!< PF[15] pin */
+#define AFIO_EXTICR4_EXTI15_PG_Pos (13U)
+#define AFIO_EXTICR4_EXTI15_PG_Msk (0x3U << AFIO_EXTICR4_EXTI15_PG_Pos) /*!< 0x00006000 */
+#define AFIO_EXTICR4_EXTI15_PG AFIO_EXTICR4_EXTI15_PG_Msk /*!< PG[15] pin */
+
+/****************** Bit definition for AFIO_MAPR2 register ******************/
+#define AFIO_MAPR2_TIM15_REMAP_Pos (0U)
+#define AFIO_MAPR2_TIM15_REMAP_Msk (0x1U << AFIO_MAPR2_TIM15_REMAP_Pos) /*!< 0x00000001 */
+#define AFIO_MAPR2_TIM15_REMAP AFIO_MAPR2_TIM15_REMAP_Msk /*!< TIM15 remapping */
+#define AFIO_MAPR2_TIM16_REMAP_Pos (1U)
+#define AFIO_MAPR2_TIM16_REMAP_Msk (0x1U << AFIO_MAPR2_TIM16_REMAP_Pos) /*!< 0x00000002 */
+#define AFIO_MAPR2_TIM16_REMAP AFIO_MAPR2_TIM16_REMAP_Msk /*!< TIM16 remapping */
+#define AFIO_MAPR2_TIM17_REMAP_Pos (2U)
+#define AFIO_MAPR2_TIM17_REMAP_Msk (0x1U << AFIO_MAPR2_TIM17_REMAP_Pos) /*!< 0x00000004 */
+#define AFIO_MAPR2_TIM17_REMAP AFIO_MAPR2_TIM17_REMAP_Msk /*!< TIM17 remapping */
+#define AFIO_MAPR2_CEC_REMAP_Pos (3U)
+#define AFIO_MAPR2_CEC_REMAP_Msk (0x1U << AFIO_MAPR2_CEC_REMAP_Pos) /*!< 0x00000008 */
+#define AFIO_MAPR2_CEC_REMAP AFIO_MAPR2_CEC_REMAP_Msk /*!< CEC remapping */
+#define AFIO_MAPR2_TIM1_DMA_REMAP_Pos (4U)
+#define AFIO_MAPR2_TIM1_DMA_REMAP_Msk (0x1U << AFIO_MAPR2_TIM1_DMA_REMAP_Pos) /*!< 0x00000010 */
+#define AFIO_MAPR2_TIM1_DMA_REMAP AFIO_MAPR2_TIM1_DMA_REMAP_Msk /*!< TIM1_DMA remapping */
+
+#define AFIO_MAPR2_TIM13_REMAP_Pos (8U)
+#define AFIO_MAPR2_TIM13_REMAP_Msk (0x1U << AFIO_MAPR2_TIM13_REMAP_Pos) /*!< 0x00000100 */
+#define AFIO_MAPR2_TIM13_REMAP AFIO_MAPR2_TIM13_REMAP_Msk /*!< TIM13 remapping */
+#define AFIO_MAPR2_TIM14_REMAP_Pos (9U)
+#define AFIO_MAPR2_TIM14_REMAP_Msk (0x1U << AFIO_MAPR2_TIM14_REMAP_Pos) /*!< 0x00000200 */
+#define AFIO_MAPR2_TIM14_REMAP AFIO_MAPR2_TIM14_REMAP_Msk /*!< TIM14 remapping */
+#define AFIO_MAPR2_TIM67_DAC_DMA_REMAP_Pos (11U)
+#define AFIO_MAPR2_TIM67_DAC_DMA_REMAP_Msk (0x1U << AFIO_MAPR2_TIM67_DAC_DMA_REMAP_Pos) /*!< 0x00000800 */
+#define AFIO_MAPR2_TIM67_DAC_DMA_REMAP AFIO_MAPR2_TIM67_DAC_DMA_REMAP_Msk /*!< TIM6/TIM7 and DAC DMA remapping */
+#define AFIO_MAPR2_TIM12_REMAP_Pos (12U)
+#define AFIO_MAPR2_TIM12_REMAP_Msk (0x1U << AFIO_MAPR2_TIM12_REMAP_Pos) /*!< 0x00001000 */
+#define AFIO_MAPR2_TIM12_REMAP AFIO_MAPR2_TIM12_REMAP_Msk /*!< TIM12 remapping */
+#define AFIO_MAPR2_MISC_REMAP_Pos (13U)
+#define AFIO_MAPR2_MISC_REMAP_Msk (0x1U << AFIO_MAPR2_MISC_REMAP_Pos) /*!< 0x00002000 */
+#define AFIO_MAPR2_MISC_REMAP AFIO_MAPR2_MISC_REMAP_Msk /*!< Miscellaneous remapping */
+
+#define AFIO_MAPR2_FSMC_NADV_REMAP_Pos (10U)
+#define AFIO_MAPR2_FSMC_NADV_REMAP_Msk (0x1U << AFIO_MAPR2_FSMC_NADV_REMAP_Pos) /*!< 0x00000400 */
+#define AFIO_MAPR2_FSMC_NADV_REMAP AFIO_MAPR2_FSMC_NADV_REMAP_Msk /*!< FSMC NADV remapping */
+
+/******************************************************************************/
+/* */
+/* SystemTick */
+/* */
+/******************************************************************************/
+
+/***************** Bit definition for SysTick_CTRL register *****************/
+#define SysTick_CTRL_ENABLE ((uint32_t)0x00000001) /*!< Counter enable */
+#define SysTick_CTRL_TICKINT ((uint32_t)0x00000002) /*!< Counting down to 0 pends the SysTick handler */
+#define SysTick_CTRL_CLKSOURCE ((uint32_t)0x00000004) /*!< Clock source */
+#define SysTick_CTRL_COUNTFLAG ((uint32_t)0x00010000) /*!< Count Flag */
+
+/***************** Bit definition for SysTick_LOAD register *****************/
+#define SysTick_LOAD_RELOAD ((uint32_t)0x00FFFFFF) /*!< Value to load into the SysTick Current Value Register when the counter reaches 0 */
+
+/***************** Bit definition for SysTick_VAL register ******************/
+#define SysTick_VAL_CURRENT ((uint32_t)0x00FFFFFF) /*!< Current value at the time the register is accessed */
+
+/***************** Bit definition for SysTick_CALIB register ****************/
+#define SysTick_CALIB_TENMS ((uint32_t)0x00FFFFFF) /*!< Reload value to use for 10ms timing */
+#define SysTick_CALIB_SKEW ((uint32_t)0x40000000) /*!< Calibration value is not exactly 10 ms */
+#define SysTick_CALIB_NOREF ((uint32_t)0x80000000) /*!< The reference clock is not provided */
+
+/******************************************************************************/
+/* */
+/* Nested Vectored Interrupt Controller */
+/* */
+/******************************************************************************/
+
+/****************** Bit definition for NVIC_ISER register *******************/
+#define NVIC_ISER_SETENA_Pos (0U)
+#define NVIC_ISER_SETENA_Msk (0xFFFFFFFFU << NVIC_ISER_SETENA_Pos) /*!< 0xFFFFFFFF */
+#define NVIC_ISER_SETENA NVIC_ISER_SETENA_Msk /*!< Interrupt set enable bits */
+#define NVIC_ISER_SETENA_0 (0x00000001U << NVIC_ISER_SETENA_Pos) /*!< 0x00000001 */
+#define NVIC_ISER_SETENA_1 (0x00000002U << NVIC_ISER_SETENA_Pos) /*!< 0x00000002 */
+#define NVIC_ISER_SETENA_2 (0x00000004U << NVIC_ISER_SETENA_Pos) /*!< 0x00000004 */
+#define NVIC_ISER_SETENA_3 (0x00000008U << NVIC_ISER_SETENA_Pos) /*!< 0x00000008 */
+#define NVIC_ISER_SETENA_4 (0x00000010U << NVIC_ISER_SETENA_Pos) /*!< 0x00000010 */
+#define NVIC_ISER_SETENA_5 (0x00000020U << NVIC_ISER_SETENA_Pos) /*!< 0x00000020 */
+#define NVIC_ISER_SETENA_6 (0x00000040U << NVIC_ISER_SETENA_Pos) /*!< 0x00000040 */
+#define NVIC_ISER_SETENA_7 (0x00000080U << NVIC_ISER_SETENA_Pos) /*!< 0x00000080 */
+#define NVIC_ISER_SETENA_8 (0x00000100U << NVIC_ISER_SETENA_Pos) /*!< 0x00000100 */
+#define NVIC_ISER_SETENA_9 (0x00000200U << NVIC_ISER_SETENA_Pos) /*!< 0x00000200 */
+#define NVIC_ISER_SETENA_10 (0x00000400U << NVIC_ISER_SETENA_Pos) /*!< 0x00000400 */
+#define NVIC_ISER_SETENA_11 (0x00000800U << NVIC_ISER_SETENA_Pos) /*!< 0x00000800 */
+#define NVIC_ISER_SETENA_12 (0x00001000U << NVIC_ISER_SETENA_Pos) /*!< 0x00001000 */
+#define NVIC_ISER_SETENA_13 (0x00002000U << NVIC_ISER_SETENA_Pos) /*!< 0x00002000 */
+#define NVIC_ISER_SETENA_14 (0x00004000U << NVIC_ISER_SETENA_Pos) /*!< 0x00004000 */
+#define NVIC_ISER_SETENA_15 (0x00008000U << NVIC_ISER_SETENA_Pos) /*!< 0x00008000 */
+#define NVIC_ISER_SETENA_16 (0x00010000U << NVIC_ISER_SETENA_Pos) /*!< 0x00010000 */
+#define NVIC_ISER_SETENA_17 (0x00020000U << NVIC_ISER_SETENA_Pos) /*!< 0x00020000 */
+#define NVIC_ISER_SETENA_18 (0x00040000U << NVIC_ISER_SETENA_Pos) /*!< 0x00040000 */
+#define NVIC_ISER_SETENA_19 (0x00080000U << NVIC_ISER_SETENA_Pos) /*!< 0x00080000 */
+#define NVIC_ISER_SETENA_20 (0x00100000U << NVIC_ISER_SETENA_Pos) /*!< 0x00100000 */
+#define NVIC_ISER_SETENA_21 (0x00200000U << NVIC_ISER_SETENA_Pos) /*!< 0x00200000 */
+#define NVIC_ISER_SETENA_22 (0x00400000U << NVIC_ISER_SETENA_Pos) /*!< 0x00400000 */
+#define NVIC_ISER_SETENA_23 (0x00800000U << NVIC_ISER_SETENA_Pos) /*!< 0x00800000 */
+#define NVIC_ISER_SETENA_24 (0x01000000U << NVIC_ISER_SETENA_Pos) /*!< 0x01000000 */
+#define NVIC_ISER_SETENA_25 (0x02000000U << NVIC_ISER_SETENA_Pos) /*!< 0x02000000 */
+#define NVIC_ISER_SETENA_26 (0x04000000U << NVIC_ISER_SETENA_Pos) /*!< 0x04000000 */
+#define NVIC_ISER_SETENA_27 (0x08000000U << NVIC_ISER_SETENA_Pos) /*!< 0x08000000 */
+#define NVIC_ISER_SETENA_28 (0x10000000U << NVIC_ISER_SETENA_Pos) /*!< 0x10000000 */
+#define NVIC_ISER_SETENA_29 (0x20000000U << NVIC_ISER_SETENA_Pos) /*!< 0x20000000 */
+#define NVIC_ISER_SETENA_30 (0x40000000U << NVIC_ISER_SETENA_Pos) /*!< 0x40000000 */
+#define NVIC_ISER_SETENA_31 (0x80000000U << NVIC_ISER_SETENA_Pos) /*!< 0x80000000 */
+
+/****************** Bit definition for NVIC_ICER register *******************/
+#define NVIC_ICER_CLRENA_Pos (0U)
+#define NVIC_ICER_CLRENA_Msk (0xFFFFFFFFU << NVIC_ICER_CLRENA_Pos) /*!< 0xFFFFFFFF */
+#define NVIC_ICER_CLRENA NVIC_ICER_CLRENA_Msk /*!< Interrupt clear-enable bits */
+#define NVIC_ICER_CLRENA_0 (0x00000001U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000001 */
+#define NVIC_ICER_CLRENA_1 (0x00000002U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000002 */
+#define NVIC_ICER_CLRENA_2 (0x00000004U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000004 */
+#define NVIC_ICER_CLRENA_3 (0x00000008U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000008 */
+#define NVIC_ICER_CLRENA_4 (0x00000010U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000010 */
+#define NVIC_ICER_CLRENA_5 (0x00000020U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000020 */
+#define NVIC_ICER_CLRENA_6 (0x00000040U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000040 */
+#define NVIC_ICER_CLRENA_7 (0x00000080U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000080 */
+#define NVIC_ICER_CLRENA_8 (0x00000100U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000100 */
+#define NVIC_ICER_CLRENA_9 (0x00000200U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000200 */
+#define NVIC_ICER_CLRENA_10 (0x00000400U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000400 */
+#define NVIC_ICER_CLRENA_11 (0x00000800U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000800 */
+#define NVIC_ICER_CLRENA_12 (0x00001000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00001000 */
+#define NVIC_ICER_CLRENA_13 (0x00002000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00002000 */
+#define NVIC_ICER_CLRENA_14 (0x00004000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00004000 */
+#define NVIC_ICER_CLRENA_15 (0x00008000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00008000 */
+#define NVIC_ICER_CLRENA_16 (0x00010000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00010000 */
+#define NVIC_ICER_CLRENA_17 (0x00020000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00020000 */
+#define NVIC_ICER_CLRENA_18 (0x00040000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00040000 */
+#define NVIC_ICER_CLRENA_19 (0x00080000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00080000 */
+#define NVIC_ICER_CLRENA_20 (0x00100000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00100000 */
+#define NVIC_ICER_CLRENA_21 (0x00200000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00200000 */
+#define NVIC_ICER_CLRENA_22 (0x00400000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00400000 */
+#define NVIC_ICER_CLRENA_23 (0x00800000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00800000 */
+#define NVIC_ICER_CLRENA_24 (0x01000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x01000000 */
+#define NVIC_ICER_CLRENA_25 (0x02000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x02000000 */
+#define NVIC_ICER_CLRENA_26 (0x04000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x04000000 */
+#define NVIC_ICER_CLRENA_27 (0x08000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x08000000 */
+#define NVIC_ICER_CLRENA_28 (0x10000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x10000000 */
+#define NVIC_ICER_CLRENA_29 (0x20000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x20000000 */
+#define NVIC_ICER_CLRENA_30 (0x40000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x40000000 */
+#define NVIC_ICER_CLRENA_31 (0x80000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x80000000 */
+
+/****************** Bit definition for NVIC_ISPR register *******************/
+#define NVIC_ISPR_SETPEND_Pos (0U)
+#define NVIC_ISPR_SETPEND_Msk (0xFFFFFFFFU << NVIC_ISPR_SETPEND_Pos) /*!< 0xFFFFFFFF */
+#define NVIC_ISPR_SETPEND NVIC_ISPR_SETPEND_Msk /*!< Interrupt set-pending bits */
+#define NVIC_ISPR_SETPEND_0 (0x00000001U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000001 */
+#define NVIC_ISPR_SETPEND_1 (0x00000002U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000002 */
+#define NVIC_ISPR_SETPEND_2 (0x00000004U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000004 */
+#define NVIC_ISPR_SETPEND_3 (0x00000008U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000008 */
+#define NVIC_ISPR_SETPEND_4 (0x00000010U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000010 */
+#define NVIC_ISPR_SETPEND_5 (0x00000020U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000020 */
+#define NVIC_ISPR_SETPEND_6 (0x00000040U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000040 */
+#define NVIC_ISPR_SETPEND_7 (0x00000080U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000080 */
+#define NVIC_ISPR_SETPEND_8 (0x00000100U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000100 */
+#define NVIC_ISPR_SETPEND_9 (0x00000200U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000200 */
+#define NVIC_ISPR_SETPEND_10 (0x00000400U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000400 */
+#define NVIC_ISPR_SETPEND_11 (0x00000800U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000800 */
+#define NVIC_ISPR_SETPEND_12 (0x00001000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00001000 */
+#define NVIC_ISPR_SETPEND_13 (0x00002000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00002000 */
+#define NVIC_ISPR_SETPEND_14 (0x00004000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00004000 */
+#define NVIC_ISPR_SETPEND_15 (0x00008000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00008000 */
+#define NVIC_ISPR_SETPEND_16 (0x00010000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00010000 */
+#define NVIC_ISPR_SETPEND_17 (0x00020000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00020000 */
+#define NVIC_ISPR_SETPEND_18 (0x00040000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00040000 */
+#define NVIC_ISPR_SETPEND_19 (0x00080000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00080000 */
+#define NVIC_ISPR_SETPEND_20 (0x00100000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00100000 */
+#define NVIC_ISPR_SETPEND_21 (0x00200000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00200000 */
+#define NVIC_ISPR_SETPEND_22 (0x00400000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00400000 */
+#define NVIC_ISPR_SETPEND_23 (0x00800000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00800000 */
+#define NVIC_ISPR_SETPEND_24 (0x01000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x01000000 */
+#define NVIC_ISPR_SETPEND_25 (0x02000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x02000000 */
+#define NVIC_ISPR_SETPEND_26 (0x04000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x04000000 */
+#define NVIC_ISPR_SETPEND_27 (0x08000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x08000000 */
+#define NVIC_ISPR_SETPEND_28 (0x10000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x10000000 */
+#define NVIC_ISPR_SETPEND_29 (0x20000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x20000000 */
+#define NVIC_ISPR_SETPEND_30 (0x40000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x40000000 */
+#define NVIC_ISPR_SETPEND_31 (0x80000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x80000000 */
+
+/****************** Bit definition for NVIC_ICPR register *******************/
+#define NVIC_ICPR_CLRPEND_Pos (0U)
+#define NVIC_ICPR_CLRPEND_Msk (0xFFFFFFFFU << NVIC_ICPR_CLRPEND_Pos) /*!< 0xFFFFFFFF */
+#define NVIC_ICPR_CLRPEND NVIC_ICPR_CLRPEND_Msk /*!< Interrupt clear-pending bits */
+#define NVIC_ICPR_CLRPEND_0 (0x00000001U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000001 */
+#define NVIC_ICPR_CLRPEND_1 (0x00000002U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000002 */
+#define NVIC_ICPR_CLRPEND_2 (0x00000004U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000004 */
+#define NVIC_ICPR_CLRPEND_3 (0x00000008U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000008 */
+#define NVIC_ICPR_CLRPEND_4 (0x00000010U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000010 */
+#define NVIC_ICPR_CLRPEND_5 (0x00000020U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000020 */
+#define NVIC_ICPR_CLRPEND_6 (0x00000040U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000040 */
+#define NVIC_ICPR_CLRPEND_7 (0x00000080U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000080 */
+#define NVIC_ICPR_CLRPEND_8 (0x00000100U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000100 */
+#define NVIC_ICPR_CLRPEND_9 (0x00000200U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000200 */
+#define NVIC_ICPR_CLRPEND_10 (0x00000400U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000400 */
+#define NVIC_ICPR_CLRPEND_11 (0x00000800U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000800 */
+#define NVIC_ICPR_CLRPEND_12 (0x00001000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00001000 */
+#define NVIC_ICPR_CLRPEND_13 (0x00002000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00002000 */
+#define NVIC_ICPR_CLRPEND_14 (0x00004000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00004000 */
+#define NVIC_ICPR_CLRPEND_15 (0x00008000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00008000 */
+#define NVIC_ICPR_CLRPEND_16 (0x00010000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00010000 */
+#define NVIC_ICPR_CLRPEND_17 (0x00020000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00020000 */
+#define NVIC_ICPR_CLRPEND_18 (0x00040000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00040000 */
+#define NVIC_ICPR_CLRPEND_19 (0x00080000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00080000 */
+#define NVIC_ICPR_CLRPEND_20 (0x00100000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00100000 */
+#define NVIC_ICPR_CLRPEND_21 (0x00200000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00200000 */
+#define NVIC_ICPR_CLRPEND_22 (0x00400000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00400000 */
+#define NVIC_ICPR_CLRPEND_23 (0x00800000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00800000 */
+#define NVIC_ICPR_CLRPEND_24 (0x01000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x01000000 */
+#define NVIC_ICPR_CLRPEND_25 (0x02000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x02000000 */
+#define NVIC_ICPR_CLRPEND_26 (0x04000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x04000000 */
+#define NVIC_ICPR_CLRPEND_27 (0x08000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x08000000 */
+#define NVIC_ICPR_CLRPEND_28 (0x10000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x10000000 */
+#define NVIC_ICPR_CLRPEND_29 (0x20000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x20000000 */
+#define NVIC_ICPR_CLRPEND_30 (0x40000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x40000000 */
+#define NVIC_ICPR_CLRPEND_31 (0x80000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x80000000 */
+
+/****************** Bit definition for NVIC_IABR register *******************/
+#define NVIC_IABR_ACTIVE_Pos (0U)
+#define NVIC_IABR_ACTIVE_Msk (0xFFFFFFFFU << NVIC_IABR_ACTIVE_Pos) /*!< 0xFFFFFFFF */
+#define NVIC_IABR_ACTIVE NVIC_IABR_ACTIVE_Msk /*!< Interrupt active flags */
+#define NVIC_IABR_ACTIVE_0 (0x00000001U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000001 */
+#define NVIC_IABR_ACTIVE_1 (0x00000002U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000002 */
+#define NVIC_IABR_ACTIVE_2 (0x00000004U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000004 */
+#define NVIC_IABR_ACTIVE_3 (0x00000008U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000008 */
+#define NVIC_IABR_ACTIVE_4 (0x00000010U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000010 */
+#define NVIC_IABR_ACTIVE_5 (0x00000020U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000020 */
+#define NVIC_IABR_ACTIVE_6 (0x00000040U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000040 */
+#define NVIC_IABR_ACTIVE_7 (0x00000080U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000080 */
+#define NVIC_IABR_ACTIVE_8 (0x00000100U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000100 */
+#define NVIC_IABR_ACTIVE_9 (0x00000200U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000200 */
+#define NVIC_IABR_ACTIVE_10 (0x00000400U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000400 */
+#define NVIC_IABR_ACTIVE_11 (0x00000800U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000800 */
+#define NVIC_IABR_ACTIVE_12 (0x00001000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00001000 */
+#define NVIC_IABR_ACTIVE_13 (0x00002000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00002000 */
+#define NVIC_IABR_ACTIVE_14 (0x00004000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00004000 */
+#define NVIC_IABR_ACTIVE_15 (0x00008000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00008000 */
+#define NVIC_IABR_ACTIVE_16 (0x00010000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00010000 */
+#define NVIC_IABR_ACTIVE_17 (0x00020000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00020000 */
+#define NVIC_IABR_ACTIVE_18 (0x00040000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00040000 */
+#define NVIC_IABR_ACTIVE_19 (0x00080000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00080000 */
+#define NVIC_IABR_ACTIVE_20 (0x00100000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00100000 */
+#define NVIC_IABR_ACTIVE_21 (0x00200000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00200000 */
+#define NVIC_IABR_ACTIVE_22 (0x00400000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00400000 */
+#define NVIC_IABR_ACTIVE_23 (0x00800000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00800000 */
+#define NVIC_IABR_ACTIVE_24 (0x01000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x01000000 */
+#define NVIC_IABR_ACTIVE_25 (0x02000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x02000000 */
+#define NVIC_IABR_ACTIVE_26 (0x04000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x04000000 */
+#define NVIC_IABR_ACTIVE_27 (0x08000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x08000000 */
+#define NVIC_IABR_ACTIVE_28 (0x10000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x10000000 */
+#define NVIC_IABR_ACTIVE_29 (0x20000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x20000000 */
+#define NVIC_IABR_ACTIVE_30 (0x40000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x40000000 */
+#define NVIC_IABR_ACTIVE_31 (0x80000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x80000000 */
+
+/****************** Bit definition for NVIC_PRI0 register *******************/
+#define NVIC_IPR0_PRI_0 ((uint32_t)0x000000FF) /*!< Priority of interrupt 0 */
+#define NVIC_IPR0_PRI_1 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 1 */
+#define NVIC_IPR0_PRI_2 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 2 */
+#define NVIC_IPR0_PRI_3 ((uint32_t)0xFF000000) /*!< Priority of interrupt 3 */
+
+/****************** Bit definition for NVIC_PRI1 register *******************/
+#define NVIC_IPR1_PRI_4 ((uint32_t)0x000000FF) /*!< Priority of interrupt 4 */
+#define NVIC_IPR1_PRI_5 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 5 */
+#define NVIC_IPR1_PRI_6 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 6 */
+#define NVIC_IPR1_PRI_7 ((uint32_t)0xFF000000) /*!< Priority of interrupt 7 */
+
+/****************** Bit definition for NVIC_PRI2 register *******************/
+#define NVIC_IPR2_PRI_8 ((uint32_t)0x000000FF) /*!< Priority of interrupt 8 */
+#define NVIC_IPR2_PRI_9 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 9 */
+#define NVIC_IPR2_PRI_10 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 10 */
+#define NVIC_IPR2_PRI_11 ((uint32_t)0xFF000000) /*!< Priority of interrupt 11 */
+
+/****************** Bit definition for NVIC_PRI3 register *******************/
+#define NVIC_IPR3_PRI_12 ((uint32_t)0x000000FF) /*!< Priority of interrupt 12 */
+#define NVIC_IPR3_PRI_13 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 13 */
+#define NVIC_IPR3_PRI_14 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 14 */
+#define NVIC_IPR3_PRI_15 ((uint32_t)0xFF000000) /*!< Priority of interrupt 15 */
+
+/****************** Bit definition for NVIC_PRI4 register *******************/
+#define NVIC_IPR4_PRI_16 ((uint32_t)0x000000FF) /*!< Priority of interrupt 16 */
+#define NVIC_IPR4_PRI_17 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 17 */
+#define NVIC_IPR4_PRI_18 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 18 */
+#define NVIC_IPR4_PRI_19 ((uint32_t)0xFF000000) /*!< Priority of interrupt 19 */
+
+/****************** Bit definition for NVIC_PRI5 register *******************/
+#define NVIC_IPR5_PRI_20 ((uint32_t)0x000000FF) /*!< Priority of interrupt 20 */
+#define NVIC_IPR5_PRI_21 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 21 */
+#define NVIC_IPR5_PRI_22 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 22 */
+#define NVIC_IPR5_PRI_23 ((uint32_t)0xFF000000) /*!< Priority of interrupt 23 */
+
+/****************** Bit definition for NVIC_PRI6 register *******************/
+#define NVIC_IPR6_PRI_24 ((uint32_t)0x000000FF) /*!< Priority of interrupt 24 */
+#define NVIC_IPR6_PRI_25 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 25 */
+#define NVIC_IPR6_PRI_26 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 26 */
+#define NVIC_IPR6_PRI_27 ((uint32_t)0xFF000000) /*!< Priority of interrupt 27 */
+
+/****************** Bit definition for NVIC_PRI7 register *******************/
+#define NVIC_IPR7_PRI_28 ((uint32_t)0x000000FF) /*!< Priority of interrupt 28 */
+#define NVIC_IPR7_PRI_29 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 29 */
+#define NVIC_IPR7_PRI_30 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 30 */
+#define NVIC_IPR7_PRI_31 ((uint32_t)0xFF000000) /*!< Priority of interrupt 31 */
+
+/****************** Bit definition for SCB_CPUID register *******************/
+#define SCB_CPUID_REVISION ((uint32_t)0x0000000F) /*!< Implementation defined revision number */
+#define SCB_CPUID_PARTNO ((uint32_t)0x0000FFF0) /*!< Number of processor within family */
+#define SCB_CPUID_Constant ((uint32_t)0x000F0000) /*!< Reads as 0x0F */
+#define SCB_CPUID_VARIANT ((uint32_t)0x00F00000) /*!< Implementation defined variant number */
+#define SCB_CPUID_IMPLEMENTER ((uint32_t)0xFF000000) /*!< Implementer code. ARM is 0x41 */
+
+/******************* Bit definition for SCB_ICSR register *******************/
+#define SCB_ICSR_VECTACTIVE ((uint32_t)0x000001FF) /*!< Active ISR number field */
+#define SCB_ICSR_RETTOBASE ((uint32_t)0x00000800) /*!< All active exceptions minus the IPSR_current_exception yields the empty set */
+#define SCB_ICSR_VECTPENDING ((uint32_t)0x003FF000) /*!< Pending ISR number field */
+#define SCB_ICSR_ISRPENDING ((uint32_t)0x00400000) /*!< Interrupt pending flag */
+#define SCB_ICSR_ISRPREEMPT ((uint32_t)0x00800000) /*!< It indicates that a pending interrupt becomes active in the next running cycle */
+#define SCB_ICSR_PENDSTCLR ((uint32_t)0x02000000) /*!< Clear pending SysTick bit */
+#define SCB_ICSR_PENDSTSET ((uint32_t)0x04000000) /*!< Set pending SysTick bit */
+#define SCB_ICSR_PENDSVCLR ((uint32_t)0x08000000) /*!< Clear pending pendSV bit */
+#define SCB_ICSR_PENDSVSET ((uint32_t)0x10000000) /*!< Set pending pendSV bit */
+#define SCB_ICSR_NMIPENDSET ((uint32_t)0x80000000) /*!< Set pending NMI bit */
+
+/******************* Bit definition for SCB_VTOR register *******************/
+#define SCB_VTOR_TBLOFF ((uint32_t)0x1FFFFF80) /*!< Vector table base offset field */
+#define SCB_VTOR_TBLBASE ((uint32_t)0x20000000) /*!< Table base in code(0) or RAM(1) */
+
+/*!<***************** Bit definition for SCB_AIRCR register *******************/
+#define SCB_AIRCR_VECTRESET ((uint32_t)0x00000001) /*!< System Reset bit */
+#define SCB_AIRCR_VECTCLRACTIVE ((uint32_t)0x00000002) /*!< Clear active vector bit */
+#define SCB_AIRCR_SYSRESETREQ ((uint32_t)0x00000004) /*!< Requests chip control logic to generate a reset */
+
+#define SCB_AIRCR_PRIGROUP ((uint32_t)0x00000700) /*!< PRIGROUP[2:0] bits (Priority group) */
+#define SCB_AIRCR_PRIGROUP_0 ((uint32_t)0x00000100) /*!< Bit 0 */
+#define SCB_AIRCR_PRIGROUP_1 ((uint32_t)0x00000200) /*!< Bit 1 */
+#define SCB_AIRCR_PRIGROUP_2 ((uint32_t)0x00000400) /*!< Bit 2 */
+
+/* prority group configuration */
+#define SCB_AIRCR_PRIGROUP0 ((uint32_t)0x00000000) /*!< Priority group=0 (7 bits of pre-emption priority, 1 bit of subpriority) */
+#define SCB_AIRCR_PRIGROUP1 ((uint32_t)0x00000100) /*!< Priority group=1 (6 bits of pre-emption priority, 2 bits of subpriority) */
+#define SCB_AIRCR_PRIGROUP2 ((uint32_t)0x00000200) /*!< Priority group=2 (5 bits of pre-emption priority, 3 bits of subpriority) */
+#define SCB_AIRCR_PRIGROUP3 ((uint32_t)0x00000300) /*!< Priority group=3 (4 bits of pre-emption priority, 4 bits of subpriority) */
+#define SCB_AIRCR_PRIGROUP4 ((uint32_t)0x00000400) /*!< Priority group=4 (3 bits of pre-emption priority, 5 bits of subpriority) */
+#define SCB_AIRCR_PRIGROUP5 ((uint32_t)0x00000500) /*!< Priority group=5 (2 bits of pre-emption priority, 6 bits of subpriority) */
+#define SCB_AIRCR_PRIGROUP6 ((uint32_t)0x00000600) /*!< Priority group=6 (1 bit of pre-emption priority, 7 bits of subpriority) */
+#define SCB_AIRCR_PRIGROUP7 ((uint32_t)0x00000700) /*!< Priority group=7 (no pre-emption priority, 8 bits of subpriority) */
+
+#define SCB_AIRCR_ENDIANESS ((uint32_t)0x00008000) /*!< Data endianness bit */
+#define SCB_AIRCR_VECTKEY ((uint32_t)0xFFFF0000) /*!< Register key (VECTKEY) - Reads as 0xFA05 (VECTKEYSTAT) */
+
+/******************* Bit definition for SCB_SCR register ********************/
+#define SCB_SCR_SLEEPONEXIT ((uint32_t)0x00000002) /*!< Sleep on exit bit */
+#define SCB_SCR_SLEEPDEEP ((uint32_t)0x00000004) /*!< Sleep deep bit */
+#define SCB_SCR_SEVONPEND ((uint32_t)0x00000010) /*!< Wake up from WFE */
+
+/******************** Bit definition for SCB_CCR register *******************/
+#define SCB_CCR_NONBASETHRDENA ((uint32_t)0x00000001) /*!< Thread mode can be entered from any level in Handler mode by controlled return value */
+#define SCB_CCR_USERSETMPEND ((uint32_t)0x00000002) /*!< Enables user code to write the Software Trigger Interrupt register to trigger (pend) a Main exception */
+#define SCB_CCR_UNALIGN_TRP ((uint32_t)0x00000008) /*!< Trap for unaligned access */
+#define SCB_CCR_DIV_0_TRP ((uint32_t)0x00000010) /*!< Trap on Divide by 0 */
+#define SCB_CCR_BFHFNMIGN ((uint32_t)0x00000100) /*!< Handlers running at priority -1 and -2 */
+#define SCB_CCR_STKALIGN ((uint32_t)0x00000200) /*!< On exception entry, the SP used prior to the exception is adjusted to be 8-byte aligned */
+
+/******************* Bit definition for SCB_SHPR register ********************/
+#define SCB_SHPR_PRI_N_Pos (0U)
+#define SCB_SHPR_PRI_N_Msk (0xFFU << SCB_SHPR_PRI_N_Pos) /*!< 0x000000FF */
+#define SCB_SHPR_PRI_N SCB_SHPR_PRI_N_Msk /*!< Priority of system handler 4,8, and 12. Mem Manage, reserved and Debug Monitor */
+#define SCB_SHPR_PRI_N1_Pos (8U)
+#define SCB_SHPR_PRI_N1_Msk (0xFFU << SCB_SHPR_PRI_N1_Pos) /*!< 0x0000FF00 */
+#define SCB_SHPR_PRI_N1 SCB_SHPR_PRI_N1_Msk /*!< Priority of system handler 5,9, and 13. Bus Fault, reserved and reserved */
+#define SCB_SHPR_PRI_N2_Pos (16U)
+#define SCB_SHPR_PRI_N2_Msk (0xFFU << SCB_SHPR_PRI_N2_Pos) /*!< 0x00FF0000 */
+#define SCB_SHPR_PRI_N2 SCB_SHPR_PRI_N2_Msk /*!< Priority of system handler 6,10, and 14. Usage Fault, reserved and PendSV */
+#define SCB_SHPR_PRI_N3_Pos (24U)
+#define SCB_SHPR_PRI_N3_Msk (0xFFU << SCB_SHPR_PRI_N3_Pos) /*!< 0xFF000000 */
+#define SCB_SHPR_PRI_N3 SCB_SHPR_PRI_N3_Msk /*!< Priority of system handler 7,11, and 15. Reserved, SVCall and SysTick */
+
+/****************** Bit definition for SCB_SHCSR register *******************/
+#define SCB_SHCSR_MEMFAULTACT ((uint32_t)0x00000001) /*!< MemManage is active */
+#define SCB_SHCSR_BUSFAULTACT ((uint32_t)0x00000002) /*!< BusFault is active */
+#define SCB_SHCSR_USGFAULTACT ((uint32_t)0x00000008) /*!< UsageFault is active */
+#define SCB_SHCSR_SVCALLACT ((uint32_t)0x00000080) /*!< SVCall is active */
+#define SCB_SHCSR_MONITORACT ((uint32_t)0x00000100) /*!< Monitor is active */
+#define SCB_SHCSR_PENDSVACT ((uint32_t)0x00000400) /*!< PendSV is active */
+#define SCB_SHCSR_SYSTICKACT ((uint32_t)0x00000800) /*!< SysTick is active */
+#define SCB_SHCSR_USGFAULTPENDED ((uint32_t)0x00001000) /*!< Usage Fault is pended */
+#define SCB_SHCSR_MEMFAULTPENDED ((uint32_t)0x00002000) /*!< MemManage is pended */
+#define SCB_SHCSR_BUSFAULTPENDED ((uint32_t)0x00004000) /*!< Bus Fault is pended */
+#define SCB_SHCSR_SVCALLPENDED ((uint32_t)0x00008000) /*!< SVCall is pended */
+#define SCB_SHCSR_MEMFAULTENA ((uint32_t)0x00010000) /*!< MemManage enable */
+#define SCB_SHCSR_BUSFAULTENA ((uint32_t)0x00020000) /*!< Bus Fault enable */
+#define SCB_SHCSR_USGFAULTENA ((uint32_t)0x00040000) /*!< UsageFault enable */
+
+/******************* Bit definition for SCB_CFSR register *******************/
+/*!< MFSR */
+#define SCB_CFSR_IACCVIOL_Pos (0U)
+#define SCB_CFSR_IACCVIOL_Msk (0x1U << SCB_CFSR_IACCVIOL_Pos) /*!< 0x00000001 */
+#define SCB_CFSR_IACCVIOL SCB_CFSR_IACCVIOL_Msk /*!< Instruction access violation */
+#define SCB_CFSR_DACCVIOL_Pos (1U)
+#define SCB_CFSR_DACCVIOL_Msk (0x1U << SCB_CFSR_DACCVIOL_Pos) /*!< 0x00000002 */
+#define SCB_CFSR_DACCVIOL SCB_CFSR_DACCVIOL_Msk /*!< Data access violation */
+#define SCB_CFSR_MUNSTKERR_Pos (3U)
+#define SCB_CFSR_MUNSTKERR_Msk (0x1U << SCB_CFSR_MUNSTKERR_Pos) /*!< 0x00000008 */
+#define SCB_CFSR_MUNSTKERR SCB_CFSR_MUNSTKERR_Msk /*!< Unstacking error */
+#define SCB_CFSR_MSTKERR_Pos (4U)
+#define SCB_CFSR_MSTKERR_Msk (0x1U << SCB_CFSR_MSTKERR_Pos) /*!< 0x00000010 */
+#define SCB_CFSR_MSTKERR SCB_CFSR_MSTKERR_Msk /*!< Stacking error */
+#define SCB_CFSR_MMARVALID_Pos (7U)
+#define SCB_CFSR_MMARVALID_Msk (0x1U << SCB_CFSR_MMARVALID_Pos) /*!< 0x00000080 */
+#define SCB_CFSR_MMARVALID SCB_CFSR_MMARVALID_Msk /*!< Memory Manage Address Register address valid flag */
+/*!< BFSR */
+#define SCB_CFSR_IBUSERR_Pos (8U)
+#define SCB_CFSR_IBUSERR_Msk (0x1U << SCB_CFSR_IBUSERR_Pos) /*!< 0x00000100 */
+#define SCB_CFSR_IBUSERR SCB_CFSR_IBUSERR_Msk /*!< Instruction bus error flag */
+#define SCB_CFSR_PRECISERR_Pos (9U)
+#define SCB_CFSR_PRECISERR_Msk (0x1U << SCB_CFSR_PRECISERR_Pos) /*!< 0x00000200 */
+#define SCB_CFSR_PRECISERR SCB_CFSR_PRECISERR_Msk /*!< Precise data bus error */
+#define SCB_CFSR_IMPRECISERR_Pos (10U)
+#define SCB_CFSR_IMPRECISERR_Msk (0x1U << SCB_CFSR_IMPRECISERR_Pos) /*!< 0x00000400 */
+#define SCB_CFSR_IMPRECISERR SCB_CFSR_IMPRECISERR_Msk /*!< Imprecise data bus error */
+#define SCB_CFSR_UNSTKERR_Pos (11U)
+#define SCB_CFSR_UNSTKERR_Msk (0x1U << SCB_CFSR_UNSTKERR_Pos) /*!< 0x00000800 */
+#define SCB_CFSR_UNSTKERR SCB_CFSR_UNSTKERR_Msk /*!< Unstacking error */
+#define SCB_CFSR_STKERR_Pos (12U)
+#define SCB_CFSR_STKERR_Msk (0x1U << SCB_CFSR_STKERR_Pos) /*!< 0x00001000 */
+#define SCB_CFSR_STKERR SCB_CFSR_STKERR_Msk /*!< Stacking error */
+#define SCB_CFSR_BFARVALID_Pos (15U)
+#define SCB_CFSR_BFARVALID_Msk (0x1U << SCB_CFSR_BFARVALID_Pos) /*!< 0x00008000 */
+#define SCB_CFSR_BFARVALID SCB_CFSR_BFARVALID_Msk /*!< Bus Fault Address Register address valid flag */
+/*!< UFSR */
+#define SCB_CFSR_UNDEFINSTR_Pos (16U)
+#define SCB_CFSR_UNDEFINSTR_Msk (0x1U << SCB_CFSR_UNDEFINSTR_Pos) /*!< 0x00010000 */
+#define SCB_CFSR_UNDEFINSTR SCB_CFSR_UNDEFINSTR_Msk /*!< The processor attempt to execute an undefined instruction */
+#define SCB_CFSR_INVSTATE_Pos (17U)
+#define SCB_CFSR_INVSTATE_Msk (0x1U << SCB_CFSR_INVSTATE_Pos) /*!< 0x00020000 */
+#define SCB_CFSR_INVSTATE SCB_CFSR_INVSTATE_Msk /*!< Invalid combination of EPSR and instruction */
+#define SCB_CFSR_INVPC_Pos (18U)
+#define SCB_CFSR_INVPC_Msk (0x1U << SCB_CFSR_INVPC_Pos) /*!< 0x00040000 */
+#define SCB_CFSR_INVPC SCB_CFSR_INVPC_Msk /*!< Attempt to load EXC_RETURN into pc illegally */
+#define SCB_CFSR_NOCP_Pos (19U)
+#define SCB_CFSR_NOCP_Msk (0x1U << SCB_CFSR_NOCP_Pos) /*!< 0x00080000 */
+#define SCB_CFSR_NOCP SCB_CFSR_NOCP_Msk /*!< Attempt to use a coprocessor instruction */
+#define SCB_CFSR_UNALIGNED_Pos (24U)
+#define SCB_CFSR_UNALIGNED_Msk (0x1U << SCB_CFSR_UNALIGNED_Pos) /*!< 0x01000000 */
+#define SCB_CFSR_UNALIGNED SCB_CFSR_UNALIGNED_Msk /*!< Fault occurs when there is an attempt to make an unaligned memory access */
+#define SCB_CFSR_DIVBYZERO_Pos (25U)
+#define SCB_CFSR_DIVBYZERO_Msk (0x1U << SCB_CFSR_DIVBYZERO_Pos) /*!< 0x02000000 */
+#define SCB_CFSR_DIVBYZERO SCB_CFSR_DIVBYZERO_Msk /*!< Fault occurs when SDIV or DIV instruction is used with a divisor of 0 */
+
+/******************* Bit definition for SCB_HFSR register *******************/
+#define SCB_HFSR_VECTTBL ((uint32_t)0x00000002) /*!< Fault occurs because of vector table read on exception processing */
+#define SCB_HFSR_FORCED ((uint32_t)0x40000000) /*!< Hard Fault activated when a configurable Fault was received and cannot activate */
+#define SCB_HFSR_DEBUGEVT ((uint32_t)0x80000000) /*!< Fault related to debug */
+
+/******************* Bit definition for SCB_DFSR register *******************/
+#define SCB_DFSR_HALTED ((uint32_t)0x00000001) /*!< Halt request flag */
+#define SCB_DFSR_BKPT ((uint32_t)0x00000002) /*!< BKPT flag */
+#define SCB_DFSR_DWTTRAP ((uint32_t)0x00000004) /*!< Data Watchpoint and Trace (DWT) flag */
+#define SCB_DFSR_VCATCH ((uint32_t)0x00000008) /*!< Vector catch flag */
+#define SCB_DFSR_EXTERNAL ((uint32_t)0x00000010) /*!< External debug request flag */
+
+/******************* Bit definition for SCB_MMFAR register ******************/
+#define SCB_MMFAR_ADDRESS_Pos (0U)
+#define SCB_MMFAR_ADDRESS_Msk (0xFFFFFFFFU << SCB_MMFAR_ADDRESS_Pos) /*!< 0xFFFFFFFF */
+#define SCB_MMFAR_ADDRESS SCB_MMFAR_ADDRESS_Msk /*!< Mem Manage fault address field */
+
+/******************* Bit definition for SCB_BFAR register *******************/
+#define SCB_BFAR_ADDRESS_Pos (0U)
+#define SCB_BFAR_ADDRESS_Msk (0xFFFFFFFFU << SCB_BFAR_ADDRESS_Pos) /*!< 0xFFFFFFFF */
+#define SCB_BFAR_ADDRESS SCB_BFAR_ADDRESS_Msk /*!< Bus fault address field */
+
+/******************* Bit definition for SCB_afsr register *******************/
+#define SCB_AFSR_IMPDEF_Pos (0U)
+#define SCB_AFSR_IMPDEF_Msk (0xFFFFFFFFU << SCB_AFSR_IMPDEF_Pos) /*!< 0xFFFFFFFF */
+#define SCB_AFSR_IMPDEF SCB_AFSR_IMPDEF_Msk /*!< Implementation defined */
+
+/******************************************************************************/
+/* */
+/* External Interrupt/Event Controller */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for EXTI_IMR register *******************/
+#define EXTI_IMR_MR0_Pos (0U)
+#define EXTI_IMR_MR0_Msk (0x1U << EXTI_IMR_MR0_Pos) /*!< 0x00000001 */
+#define EXTI_IMR_MR0 EXTI_IMR_MR0_Msk /*!< Interrupt Mask on line 0 */
+#define EXTI_IMR_MR1_Pos (1U)
+#define EXTI_IMR_MR1_Msk (0x1U << EXTI_IMR_MR1_Pos) /*!< 0x00000002 */
+#define EXTI_IMR_MR1 EXTI_IMR_MR1_Msk /*!< Interrupt Mask on line 1 */
+#define EXTI_IMR_MR2_Pos (2U)
+#define EXTI_IMR_MR2_Msk (0x1U << EXTI_IMR_MR2_Pos) /*!< 0x00000004 */
+#define EXTI_IMR_MR2 EXTI_IMR_MR2_Msk /*!< Interrupt Mask on line 2 */
+#define EXTI_IMR_MR3_Pos (3U)
+#define EXTI_IMR_MR3_Msk (0x1U << EXTI_IMR_MR3_Pos) /*!< 0x00000008 */
+#define EXTI_IMR_MR3 EXTI_IMR_MR3_Msk /*!< Interrupt Mask on line 3 */
+#define EXTI_IMR_MR4_Pos (4U)
+#define EXTI_IMR_MR4_Msk (0x1U << EXTI_IMR_MR4_Pos) /*!< 0x00000010 */
+#define EXTI_IMR_MR4 EXTI_IMR_MR4_Msk /*!< Interrupt Mask on line 4 */
+#define EXTI_IMR_MR5_Pos (5U)
+#define EXTI_IMR_MR5_Msk (0x1U << EXTI_IMR_MR5_Pos) /*!< 0x00000020 */
+#define EXTI_IMR_MR5 EXTI_IMR_MR5_Msk /*!< Interrupt Mask on line 5 */
+#define EXTI_IMR_MR6_Pos (6U)
+#define EXTI_IMR_MR6_Msk (0x1U << EXTI_IMR_MR6_Pos) /*!< 0x00000040 */
+#define EXTI_IMR_MR6 EXTI_IMR_MR6_Msk /*!< Interrupt Mask on line 6 */
+#define EXTI_IMR_MR7_Pos (7U)
+#define EXTI_IMR_MR7_Msk (0x1U << EXTI_IMR_MR7_Pos) /*!< 0x00000080 */
+#define EXTI_IMR_MR7 EXTI_IMR_MR7_Msk /*!< Interrupt Mask on line 7 */
+#define EXTI_IMR_MR8_Pos (8U)
+#define EXTI_IMR_MR8_Msk (0x1U << EXTI_IMR_MR8_Pos) /*!< 0x00000100 */
+#define EXTI_IMR_MR8 EXTI_IMR_MR8_Msk /*!< Interrupt Mask on line 8 */
+#define EXTI_IMR_MR9_Pos (9U)
+#define EXTI_IMR_MR9_Msk (0x1U << EXTI_IMR_MR9_Pos) /*!< 0x00000200 */
+#define EXTI_IMR_MR9 EXTI_IMR_MR9_Msk /*!< Interrupt Mask on line 9 */
+#define EXTI_IMR_MR10_Pos (10U)
+#define EXTI_IMR_MR10_Msk (0x1U << EXTI_IMR_MR10_Pos) /*!< 0x00000400 */
+#define EXTI_IMR_MR10 EXTI_IMR_MR10_Msk /*!< Interrupt Mask on line 10 */
+#define EXTI_IMR_MR11_Pos (11U)
+#define EXTI_IMR_MR11_Msk (0x1U << EXTI_IMR_MR11_Pos) /*!< 0x00000800 */
+#define EXTI_IMR_MR11 EXTI_IMR_MR11_Msk /*!< Interrupt Mask on line 11 */
+#define EXTI_IMR_MR12_Pos (12U)
+#define EXTI_IMR_MR12_Msk (0x1U << EXTI_IMR_MR12_Pos) /*!< 0x00001000 */
+#define EXTI_IMR_MR12 EXTI_IMR_MR12_Msk /*!< Interrupt Mask on line 12 */
+#define EXTI_IMR_MR13_Pos (13U)
+#define EXTI_IMR_MR13_Msk (0x1U << EXTI_IMR_MR13_Pos) /*!< 0x00002000 */
+#define EXTI_IMR_MR13 EXTI_IMR_MR13_Msk /*!< Interrupt Mask on line 13 */
+#define EXTI_IMR_MR14_Pos (14U)
+#define EXTI_IMR_MR14_Msk (0x1U << EXTI_IMR_MR14_Pos) /*!< 0x00004000 */
+#define EXTI_IMR_MR14 EXTI_IMR_MR14_Msk /*!< Interrupt Mask on line 14 */
+#define EXTI_IMR_MR15_Pos (15U)
+#define EXTI_IMR_MR15_Msk (0x1U << EXTI_IMR_MR15_Pos) /*!< 0x00008000 */
+#define EXTI_IMR_MR15 EXTI_IMR_MR15_Msk /*!< Interrupt Mask on line 15 */
+#define EXTI_IMR_MR16_Pos (16U)
+#define EXTI_IMR_MR16_Msk (0x1U << EXTI_IMR_MR16_Pos) /*!< 0x00010000 */
+#define EXTI_IMR_MR16 EXTI_IMR_MR16_Msk /*!< Interrupt Mask on line 16 */
+#define EXTI_IMR_MR17_Pos (17U)
+#define EXTI_IMR_MR17_Msk (0x1U << EXTI_IMR_MR17_Pos) /*!< 0x00020000 */
+#define EXTI_IMR_MR17 EXTI_IMR_MR17_Msk /*!< Interrupt Mask on line 17 */
+#define EXTI_IMR_MR18_Pos (18U)
+#define EXTI_IMR_MR18_Msk (0x1U << EXTI_IMR_MR18_Pos) /*!< 0x00040000 */
+#define EXTI_IMR_MR18 EXTI_IMR_MR18_Msk /*!< Interrupt Mask on line 18 */
+#define EXTI_IMR_MR19_Pos (19U)
+#define EXTI_IMR_MR19_Msk (0x1U << EXTI_IMR_MR19_Pos) /*!< 0x00080000 */
+#define EXTI_IMR_MR19 EXTI_IMR_MR19_Msk /*!< Interrupt Mask on line 19 */
+
+/* References Defines */
+#define EXTI_IMR_IM0 EXTI_IMR_MR0
+#define EXTI_IMR_IM1 EXTI_IMR_MR1
+#define EXTI_IMR_IM2 EXTI_IMR_MR2
+#define EXTI_IMR_IM3 EXTI_IMR_MR3
+#define EXTI_IMR_IM4 EXTI_IMR_MR4
+#define EXTI_IMR_IM5 EXTI_IMR_MR5
+#define EXTI_IMR_IM6 EXTI_IMR_MR6
+#define EXTI_IMR_IM7 EXTI_IMR_MR7
+#define EXTI_IMR_IM8 EXTI_IMR_MR8
+#define EXTI_IMR_IM9 EXTI_IMR_MR9
+#define EXTI_IMR_IM10 EXTI_IMR_MR10
+#define EXTI_IMR_IM11 EXTI_IMR_MR11
+#define EXTI_IMR_IM12 EXTI_IMR_MR12
+#define EXTI_IMR_IM13 EXTI_IMR_MR13
+#define EXTI_IMR_IM14 EXTI_IMR_MR14
+#define EXTI_IMR_IM15 EXTI_IMR_MR15
+#define EXTI_IMR_IM16 EXTI_IMR_MR16
+#define EXTI_IMR_IM17 EXTI_IMR_MR17
+#define EXTI_IMR_IM18 EXTI_IMR_MR18
+#define EXTI_IMR_IM19 EXTI_IMR_MR19
+
+/******************* Bit definition for EXTI_EMR register *******************/
+#define EXTI_EMR_MR0_Pos (0U)
+#define EXTI_EMR_MR0_Msk (0x1U << EXTI_EMR_MR0_Pos) /*!< 0x00000001 */
+#define EXTI_EMR_MR0 EXTI_EMR_MR0_Msk /*!< Event Mask on line 0 */
+#define EXTI_EMR_MR1_Pos (1U)
+#define EXTI_EMR_MR1_Msk (0x1U << EXTI_EMR_MR1_Pos) /*!< 0x00000002 */
+#define EXTI_EMR_MR1 EXTI_EMR_MR1_Msk /*!< Event Mask on line 1 */
+#define EXTI_EMR_MR2_Pos (2U)
+#define EXTI_EMR_MR2_Msk (0x1U << EXTI_EMR_MR2_Pos) /*!< 0x00000004 */
+#define EXTI_EMR_MR2 EXTI_EMR_MR2_Msk /*!< Event Mask on line 2 */
+#define EXTI_EMR_MR3_Pos (3U)
+#define EXTI_EMR_MR3_Msk (0x1U << EXTI_EMR_MR3_Pos) /*!< 0x00000008 */
+#define EXTI_EMR_MR3 EXTI_EMR_MR3_Msk /*!< Event Mask on line 3 */
+#define EXTI_EMR_MR4_Pos (4U)
+#define EXTI_EMR_MR4_Msk (0x1U << EXTI_EMR_MR4_Pos) /*!< 0x00000010 */
+#define EXTI_EMR_MR4 EXTI_EMR_MR4_Msk /*!< Event Mask on line 4 */
+#define EXTI_EMR_MR5_Pos (5U)
+#define EXTI_EMR_MR5_Msk (0x1U << EXTI_EMR_MR5_Pos) /*!< 0x00000020 */
+#define EXTI_EMR_MR5 EXTI_EMR_MR5_Msk /*!< Event Mask on line 5 */
+#define EXTI_EMR_MR6_Pos (6U)
+#define EXTI_EMR_MR6_Msk (0x1U << EXTI_EMR_MR6_Pos) /*!< 0x00000040 */
+#define EXTI_EMR_MR6 EXTI_EMR_MR6_Msk /*!< Event Mask on line 6 */
+#define EXTI_EMR_MR7_Pos (7U)
+#define EXTI_EMR_MR7_Msk (0x1U << EXTI_EMR_MR7_Pos) /*!< 0x00000080 */
+#define EXTI_EMR_MR7 EXTI_EMR_MR7_Msk /*!< Event Mask on line 7 */
+#define EXTI_EMR_MR8_Pos (8U)
+#define EXTI_EMR_MR8_Msk (0x1U << EXTI_EMR_MR8_Pos) /*!< 0x00000100 */
+#define EXTI_EMR_MR8 EXTI_EMR_MR8_Msk /*!< Event Mask on line 8 */
+#define EXTI_EMR_MR9_Pos (9U)
+#define EXTI_EMR_MR9_Msk (0x1U << EXTI_EMR_MR9_Pos) /*!< 0x00000200 */
+#define EXTI_EMR_MR9 EXTI_EMR_MR9_Msk /*!< Event Mask on line 9 */
+#define EXTI_EMR_MR10_Pos (10U)
+#define EXTI_EMR_MR10_Msk (0x1U << EXTI_EMR_MR10_Pos) /*!< 0x00000400 */
+#define EXTI_EMR_MR10 EXTI_EMR_MR10_Msk /*!< Event Mask on line 10 */
+#define EXTI_EMR_MR11_Pos (11U)
+#define EXTI_EMR_MR11_Msk (0x1U << EXTI_EMR_MR11_Pos) /*!< 0x00000800 */
+#define EXTI_EMR_MR11 EXTI_EMR_MR11_Msk /*!< Event Mask on line 11 */
+#define EXTI_EMR_MR12_Pos (12U)
+#define EXTI_EMR_MR12_Msk (0x1U << EXTI_EMR_MR12_Pos) /*!< 0x00001000 */
+#define EXTI_EMR_MR12 EXTI_EMR_MR12_Msk /*!< Event Mask on line 12 */
+#define EXTI_EMR_MR13_Pos (13U)
+#define EXTI_EMR_MR13_Msk (0x1U << EXTI_EMR_MR13_Pos) /*!< 0x00002000 */
+#define EXTI_EMR_MR13 EXTI_EMR_MR13_Msk /*!< Event Mask on line 13 */
+#define EXTI_EMR_MR14_Pos (14U)
+#define EXTI_EMR_MR14_Msk (0x1U << EXTI_EMR_MR14_Pos) /*!< 0x00004000 */
+#define EXTI_EMR_MR14 EXTI_EMR_MR14_Msk /*!< Event Mask on line 14 */
+#define EXTI_EMR_MR15_Pos (15U)
+#define EXTI_EMR_MR15_Msk (0x1U << EXTI_EMR_MR15_Pos) /*!< 0x00008000 */
+#define EXTI_EMR_MR15 EXTI_EMR_MR15_Msk /*!< Event Mask on line 15 */
+#define EXTI_EMR_MR16_Pos (16U)
+#define EXTI_EMR_MR16_Msk (0x1U << EXTI_EMR_MR16_Pos) /*!< 0x00010000 */
+#define EXTI_EMR_MR16 EXTI_EMR_MR16_Msk /*!< Event Mask on line 16 */
+#define EXTI_EMR_MR17_Pos (17U)
+#define EXTI_EMR_MR17_Msk (0x1U << EXTI_EMR_MR17_Pos) /*!< 0x00020000 */
+#define EXTI_EMR_MR17 EXTI_EMR_MR17_Msk /*!< Event Mask on line 17 */
+#define EXTI_EMR_MR18_Pos (18U)
+#define EXTI_EMR_MR18_Msk (0x1U << EXTI_EMR_MR18_Pos) /*!< 0x00040000 */
+#define EXTI_EMR_MR18 EXTI_EMR_MR18_Msk /*!< Event Mask on line 18 */
+#define EXTI_EMR_MR19_Pos (19U)
+#define EXTI_EMR_MR19_Msk (0x1U << EXTI_EMR_MR19_Pos) /*!< 0x00080000 */
+#define EXTI_EMR_MR19 EXTI_EMR_MR19_Msk /*!< Event Mask on line 19 */
+
+/* References Defines */
+#define EXTI_EMR_EM0 EXTI_EMR_MR0
+#define EXTI_EMR_EM1 EXTI_EMR_MR1
+#define EXTI_EMR_EM2 EXTI_EMR_MR2
+#define EXTI_EMR_EM3 EXTI_EMR_MR3
+#define EXTI_EMR_EM4 EXTI_EMR_MR4
+#define EXTI_EMR_EM5 EXTI_EMR_MR5
+#define EXTI_EMR_EM6 EXTI_EMR_MR6
+#define EXTI_EMR_EM7 EXTI_EMR_MR7
+#define EXTI_EMR_EM8 EXTI_EMR_MR8
+#define EXTI_EMR_EM9 EXTI_EMR_MR9
+#define EXTI_EMR_EM10 EXTI_EMR_MR10
+#define EXTI_EMR_EM11 EXTI_EMR_MR11
+#define EXTI_EMR_EM12 EXTI_EMR_MR12
+#define EXTI_EMR_EM13 EXTI_EMR_MR13
+#define EXTI_EMR_EM14 EXTI_EMR_MR14
+#define EXTI_EMR_EM15 EXTI_EMR_MR15
+#define EXTI_EMR_EM16 EXTI_EMR_MR16
+#define EXTI_EMR_EM17 EXTI_EMR_MR17
+#define EXTI_EMR_EM18 EXTI_EMR_MR18
+#define EXTI_EMR_EM19 EXTI_EMR_MR19
+
+/****************** Bit definition for EXTI_RTSR register *******************/
+#define EXTI_RTSR_TR0_Pos (0U)
+#define EXTI_RTSR_TR0_Msk (0x1U << EXTI_RTSR_TR0_Pos) /*!< 0x00000001 */
+#define EXTI_RTSR_TR0 EXTI_RTSR_TR0_Msk /*!< Rising trigger event configuration bit of line 0 */
+#define EXTI_RTSR_TR1_Pos (1U)
+#define EXTI_RTSR_TR1_Msk (0x1U << EXTI_RTSR_TR1_Pos) /*!< 0x00000002 */
+#define EXTI_RTSR_TR1 EXTI_RTSR_TR1_Msk /*!< Rising trigger event configuration bit of line 1 */
+#define EXTI_RTSR_TR2_Pos (2U)
+#define EXTI_RTSR_TR2_Msk (0x1U << EXTI_RTSR_TR2_Pos) /*!< 0x00000004 */
+#define EXTI_RTSR_TR2 EXTI_RTSR_TR2_Msk /*!< Rising trigger event configuration bit of line 2 */
+#define EXTI_RTSR_TR3_Pos (3U)
+#define EXTI_RTSR_TR3_Msk (0x1U << EXTI_RTSR_TR3_Pos) /*!< 0x00000008 */
+#define EXTI_RTSR_TR3 EXTI_RTSR_TR3_Msk /*!< Rising trigger event configuration bit of line 3 */
+#define EXTI_RTSR_TR4_Pos (4U)
+#define EXTI_RTSR_TR4_Msk (0x1U << EXTI_RTSR_TR4_Pos) /*!< 0x00000010 */
+#define EXTI_RTSR_TR4 EXTI_RTSR_TR4_Msk /*!< Rising trigger event configuration bit of line 4 */
+#define EXTI_RTSR_TR5_Pos (5U)
+#define EXTI_RTSR_TR5_Msk (0x1U << EXTI_RTSR_TR5_Pos) /*!< 0x00000020 */
+#define EXTI_RTSR_TR5 EXTI_RTSR_TR5_Msk /*!< Rising trigger event configuration bit of line 5 */
+#define EXTI_RTSR_TR6_Pos (6U)
+#define EXTI_RTSR_TR6_Msk (0x1U << EXTI_RTSR_TR6_Pos) /*!< 0x00000040 */
+#define EXTI_RTSR_TR6 EXTI_RTSR_TR6_Msk /*!< Rising trigger event configuration bit of line 6 */
+#define EXTI_RTSR_TR7_Pos (7U)
+#define EXTI_RTSR_TR7_Msk (0x1U << EXTI_RTSR_TR7_Pos) /*!< 0x00000080 */
+#define EXTI_RTSR_TR7 EXTI_RTSR_TR7_Msk /*!< Rising trigger event configuration bit of line 7 */
+#define EXTI_RTSR_TR8_Pos (8U)
+#define EXTI_RTSR_TR8_Msk (0x1U << EXTI_RTSR_TR8_Pos) /*!< 0x00000100 */
+#define EXTI_RTSR_TR8 EXTI_RTSR_TR8_Msk /*!< Rising trigger event configuration bit of line 8 */
+#define EXTI_RTSR_TR9_Pos (9U)
+#define EXTI_RTSR_TR9_Msk (0x1U << EXTI_RTSR_TR9_Pos) /*!< 0x00000200 */
+#define EXTI_RTSR_TR9 EXTI_RTSR_TR9_Msk /*!< Rising trigger event configuration bit of line 9 */
+#define EXTI_RTSR_TR10_Pos (10U)
+#define EXTI_RTSR_TR10_Msk (0x1U << EXTI_RTSR_TR10_Pos) /*!< 0x00000400 */
+#define EXTI_RTSR_TR10 EXTI_RTSR_TR10_Msk /*!< Rising trigger event configuration bit of line 10 */
+#define EXTI_RTSR_TR11_Pos (11U)
+#define EXTI_RTSR_TR11_Msk (0x1U << EXTI_RTSR_TR11_Pos) /*!< 0x00000800 */
+#define EXTI_RTSR_TR11 EXTI_RTSR_TR11_Msk /*!< Rising trigger event configuration bit of line 11 */
+#define EXTI_RTSR_TR12_Pos (12U)
+#define EXTI_RTSR_TR12_Msk (0x1U << EXTI_RTSR_TR12_Pos) /*!< 0x00001000 */
+#define EXTI_RTSR_TR12 EXTI_RTSR_TR12_Msk /*!< Rising trigger event configuration bit of line 12 */
+#define EXTI_RTSR_TR13_Pos (13U)
+#define EXTI_RTSR_TR13_Msk (0x1U << EXTI_RTSR_TR13_Pos) /*!< 0x00002000 */
+#define EXTI_RTSR_TR13 EXTI_RTSR_TR13_Msk /*!< Rising trigger event configuration bit of line 13 */
+#define EXTI_RTSR_TR14_Pos (14U)
+#define EXTI_RTSR_TR14_Msk (0x1U << EXTI_RTSR_TR14_Pos) /*!< 0x00004000 */
+#define EXTI_RTSR_TR14 EXTI_RTSR_TR14_Msk /*!< Rising trigger event configuration bit of line 14 */
+#define EXTI_RTSR_TR15_Pos (15U)
+#define EXTI_RTSR_TR15_Msk (0x1U << EXTI_RTSR_TR15_Pos) /*!< 0x00008000 */
+#define EXTI_RTSR_TR15 EXTI_RTSR_TR15_Msk /*!< Rising trigger event configuration bit of line 15 */
+#define EXTI_RTSR_TR16_Pos (16U)
+#define EXTI_RTSR_TR16_Msk (0x1U << EXTI_RTSR_TR16_Pos) /*!< 0x00010000 */
+#define EXTI_RTSR_TR16 EXTI_RTSR_TR16_Msk /*!< Rising trigger event configuration bit of line 16 */
+#define EXTI_RTSR_TR17_Pos (17U)
+#define EXTI_RTSR_TR17_Msk (0x1U << EXTI_RTSR_TR17_Pos) /*!< 0x00020000 */
+#define EXTI_RTSR_TR17 EXTI_RTSR_TR17_Msk /*!< Rising trigger event configuration bit of line 17 */
+#define EXTI_RTSR_TR18_Pos (18U)
+#define EXTI_RTSR_TR18_Msk (0x1U << EXTI_RTSR_TR18_Pos) /*!< 0x00040000 */
+#define EXTI_RTSR_TR18 EXTI_RTSR_TR18_Msk /*!< Rising trigger event configuration bit of line 18 */
+#define EXTI_RTSR_TR19_Pos (19U)
+#define EXTI_RTSR_TR19_Msk (0x1U << EXTI_RTSR_TR19_Pos) /*!< 0x00080000 */
+#define EXTI_RTSR_TR19 EXTI_RTSR_TR19_Msk /*!< Rising trigger event configuration bit of line 19 */
+
+/* References Defines */
+#define EXTI_RTSR_RT0 EXTI_RTSR_TR0
+#define EXTI_RTSR_RT1 EXTI_RTSR_TR1
+#define EXTI_RTSR_RT2 EXTI_RTSR_TR2
+#define EXTI_RTSR_RT3 EXTI_RTSR_TR3
+#define EXTI_RTSR_RT4 EXTI_RTSR_TR4
+#define EXTI_RTSR_RT5 EXTI_RTSR_TR5
+#define EXTI_RTSR_RT6 EXTI_RTSR_TR6
+#define EXTI_RTSR_RT7 EXTI_RTSR_TR7
+#define EXTI_RTSR_RT8 EXTI_RTSR_TR8
+#define EXTI_RTSR_RT9 EXTI_RTSR_TR9
+#define EXTI_RTSR_RT10 EXTI_RTSR_TR10
+#define EXTI_RTSR_RT11 EXTI_RTSR_TR11
+#define EXTI_RTSR_RT12 EXTI_RTSR_TR12
+#define EXTI_RTSR_RT13 EXTI_RTSR_TR13
+#define EXTI_RTSR_RT14 EXTI_RTSR_TR14
+#define EXTI_RTSR_RT15 EXTI_RTSR_TR15
+#define EXTI_RTSR_RT16 EXTI_RTSR_TR16
+#define EXTI_RTSR_RT17 EXTI_RTSR_TR17
+#define EXTI_RTSR_RT18 EXTI_RTSR_TR18
+#define EXTI_RTSR_RT19 EXTI_RTSR_TR19
+
+/****************** Bit definition for EXTI_FTSR register *******************/
+#define EXTI_FTSR_TR0_Pos (0U)
+#define EXTI_FTSR_TR0_Msk (0x1U << EXTI_FTSR_TR0_Pos) /*!< 0x00000001 */
+#define EXTI_FTSR_TR0 EXTI_FTSR_TR0_Msk /*!< Falling trigger event configuration bit of line 0 */
+#define EXTI_FTSR_TR1_Pos (1U)
+#define EXTI_FTSR_TR1_Msk (0x1U << EXTI_FTSR_TR1_Pos) /*!< 0x00000002 */
+#define EXTI_FTSR_TR1 EXTI_FTSR_TR1_Msk /*!< Falling trigger event configuration bit of line 1 */
+#define EXTI_FTSR_TR2_Pos (2U)
+#define EXTI_FTSR_TR2_Msk (0x1U << EXTI_FTSR_TR2_Pos) /*!< 0x00000004 */
+#define EXTI_FTSR_TR2 EXTI_FTSR_TR2_Msk /*!< Falling trigger event configuration bit of line 2 */
+#define EXTI_FTSR_TR3_Pos (3U)
+#define EXTI_FTSR_TR3_Msk (0x1U << EXTI_FTSR_TR3_Pos) /*!< 0x00000008 */
+#define EXTI_FTSR_TR3 EXTI_FTSR_TR3_Msk /*!< Falling trigger event configuration bit of line 3 */
+#define EXTI_FTSR_TR4_Pos (4U)
+#define EXTI_FTSR_TR4_Msk (0x1U << EXTI_FTSR_TR4_Pos) /*!< 0x00000010 */
+#define EXTI_FTSR_TR4 EXTI_FTSR_TR4_Msk /*!< Falling trigger event configuration bit of line 4 */
+#define EXTI_FTSR_TR5_Pos (5U)
+#define EXTI_FTSR_TR5_Msk (0x1U << EXTI_FTSR_TR5_Pos) /*!< 0x00000020 */
+#define EXTI_FTSR_TR5 EXTI_FTSR_TR5_Msk /*!< Falling trigger event configuration bit of line 5 */
+#define EXTI_FTSR_TR6_Pos (6U)
+#define EXTI_FTSR_TR6_Msk (0x1U << EXTI_FTSR_TR6_Pos) /*!< 0x00000040 */
+#define EXTI_FTSR_TR6 EXTI_FTSR_TR6_Msk /*!< Falling trigger event configuration bit of line 6 */
+#define EXTI_FTSR_TR7_Pos (7U)
+#define EXTI_FTSR_TR7_Msk (0x1U << EXTI_FTSR_TR7_Pos) /*!< 0x00000080 */
+#define EXTI_FTSR_TR7 EXTI_FTSR_TR7_Msk /*!< Falling trigger event configuration bit of line 7 */
+#define EXTI_FTSR_TR8_Pos (8U)
+#define EXTI_FTSR_TR8_Msk (0x1U << EXTI_FTSR_TR8_Pos) /*!< 0x00000100 */
+#define EXTI_FTSR_TR8 EXTI_FTSR_TR8_Msk /*!< Falling trigger event configuration bit of line 8 */
+#define EXTI_FTSR_TR9_Pos (9U)
+#define EXTI_FTSR_TR9_Msk (0x1U << EXTI_FTSR_TR9_Pos) /*!< 0x00000200 */
+#define EXTI_FTSR_TR9 EXTI_FTSR_TR9_Msk /*!< Falling trigger event configuration bit of line 9 */
+#define EXTI_FTSR_TR10_Pos (10U)
+#define EXTI_FTSR_TR10_Msk (0x1U << EXTI_FTSR_TR10_Pos) /*!< 0x00000400 */
+#define EXTI_FTSR_TR10 EXTI_FTSR_TR10_Msk /*!< Falling trigger event configuration bit of line 10 */
+#define EXTI_FTSR_TR11_Pos (11U)
+#define EXTI_FTSR_TR11_Msk (0x1U << EXTI_FTSR_TR11_Pos) /*!< 0x00000800 */
+#define EXTI_FTSR_TR11 EXTI_FTSR_TR11_Msk /*!< Falling trigger event configuration bit of line 11 */
+#define EXTI_FTSR_TR12_Pos (12U)
+#define EXTI_FTSR_TR12_Msk (0x1U << EXTI_FTSR_TR12_Pos) /*!< 0x00001000 */
+#define EXTI_FTSR_TR12 EXTI_FTSR_TR12_Msk /*!< Falling trigger event configuration bit of line 12 */
+#define EXTI_FTSR_TR13_Pos (13U)
+#define EXTI_FTSR_TR13_Msk (0x1U << EXTI_FTSR_TR13_Pos) /*!< 0x00002000 */
+#define EXTI_FTSR_TR13 EXTI_FTSR_TR13_Msk /*!< Falling trigger event configuration bit of line 13 */
+#define EXTI_FTSR_TR14_Pos (14U)
+#define EXTI_FTSR_TR14_Msk (0x1U << EXTI_FTSR_TR14_Pos) /*!< 0x00004000 */
+#define EXTI_FTSR_TR14 EXTI_FTSR_TR14_Msk /*!< Falling trigger event configuration bit of line 14 */
+#define EXTI_FTSR_TR15_Pos (15U)
+#define EXTI_FTSR_TR15_Msk (0x1U << EXTI_FTSR_TR15_Pos) /*!< 0x00008000 */
+#define EXTI_FTSR_TR15 EXTI_FTSR_TR15_Msk /*!< Falling trigger event configuration bit of line 15 */
+#define EXTI_FTSR_TR16_Pos (16U)
+#define EXTI_FTSR_TR16_Msk (0x1U << EXTI_FTSR_TR16_Pos) /*!< 0x00010000 */
+#define EXTI_FTSR_TR16 EXTI_FTSR_TR16_Msk /*!< Falling trigger event configuration bit of line 16 */
+#define EXTI_FTSR_TR17_Pos (17U)
+#define EXTI_FTSR_TR17_Msk (0x1U << EXTI_FTSR_TR17_Pos) /*!< 0x00020000 */
+#define EXTI_FTSR_TR17 EXTI_FTSR_TR17_Msk /*!< Falling trigger event configuration bit of line 17 */
+#define EXTI_FTSR_TR18_Pos (18U)
+#define EXTI_FTSR_TR18_Msk (0x1U << EXTI_FTSR_TR18_Pos) /*!< 0x00040000 */
+#define EXTI_FTSR_TR18 EXTI_FTSR_TR18_Msk /*!< Falling trigger event configuration bit of line 18 */
+#define EXTI_FTSR_TR19_Pos (19U)
+#define EXTI_FTSR_TR19_Msk (0x1U << EXTI_FTSR_TR19_Pos) /*!< 0x00080000 */
+#define EXTI_FTSR_TR19 EXTI_FTSR_TR19_Msk /*!< Falling trigger event configuration bit of line 19 */
+
+/* References Defines */
+#define EXTI_FTSR_FT0 EXTI_FTSR_TR0
+#define EXTI_FTSR_FT1 EXTI_FTSR_TR1
+#define EXTI_FTSR_FT2 EXTI_FTSR_TR2
+#define EXTI_FTSR_FT3 EXTI_FTSR_TR3
+#define EXTI_FTSR_FT4 EXTI_FTSR_TR4
+#define EXTI_FTSR_FT5 EXTI_FTSR_TR5
+#define EXTI_FTSR_FT6 EXTI_FTSR_TR6
+#define EXTI_FTSR_FT7 EXTI_FTSR_TR7
+#define EXTI_FTSR_FT8 EXTI_FTSR_TR8
+#define EXTI_FTSR_FT9 EXTI_FTSR_TR9
+#define EXTI_FTSR_FT10 EXTI_FTSR_TR10
+#define EXTI_FTSR_FT11 EXTI_FTSR_TR11
+#define EXTI_FTSR_FT12 EXTI_FTSR_TR12
+#define EXTI_FTSR_FT13 EXTI_FTSR_TR13
+#define EXTI_FTSR_FT14 EXTI_FTSR_TR14
+#define EXTI_FTSR_FT15 EXTI_FTSR_TR15
+#define EXTI_FTSR_FT16 EXTI_FTSR_TR16
+#define EXTI_FTSR_FT17 EXTI_FTSR_TR17
+#define EXTI_FTSR_FT18 EXTI_FTSR_TR18
+#define EXTI_FTSR_FT19 EXTI_FTSR_TR19
+
+/****************** Bit definition for EXTI_SWIER register ******************/
+#define EXTI_SWIER_SWIER0_Pos (0U)
+#define EXTI_SWIER_SWIER0_Msk (0x1U << EXTI_SWIER_SWIER0_Pos) /*!< 0x00000001 */
+#define EXTI_SWIER_SWIER0 EXTI_SWIER_SWIER0_Msk /*!< Software Interrupt on line 0 */
+#define EXTI_SWIER_SWIER1_Pos (1U)
+#define EXTI_SWIER_SWIER1_Msk (0x1U << EXTI_SWIER_SWIER1_Pos) /*!< 0x00000002 */
+#define EXTI_SWIER_SWIER1 EXTI_SWIER_SWIER1_Msk /*!< Software Interrupt on line 1 */
+#define EXTI_SWIER_SWIER2_Pos (2U)
+#define EXTI_SWIER_SWIER2_Msk (0x1U << EXTI_SWIER_SWIER2_Pos) /*!< 0x00000004 */
+#define EXTI_SWIER_SWIER2 EXTI_SWIER_SWIER2_Msk /*!< Software Interrupt on line 2 */
+#define EXTI_SWIER_SWIER3_Pos (3U)
+#define EXTI_SWIER_SWIER3_Msk (0x1U << EXTI_SWIER_SWIER3_Pos) /*!< 0x00000008 */
+#define EXTI_SWIER_SWIER3 EXTI_SWIER_SWIER3_Msk /*!< Software Interrupt on line 3 */
+#define EXTI_SWIER_SWIER4_Pos (4U)
+#define EXTI_SWIER_SWIER4_Msk (0x1U << EXTI_SWIER_SWIER4_Pos) /*!< 0x00000010 */
+#define EXTI_SWIER_SWIER4 EXTI_SWIER_SWIER4_Msk /*!< Software Interrupt on line 4 */
+#define EXTI_SWIER_SWIER5_Pos (5U)
+#define EXTI_SWIER_SWIER5_Msk (0x1U << EXTI_SWIER_SWIER5_Pos) /*!< 0x00000020 */
+#define EXTI_SWIER_SWIER5 EXTI_SWIER_SWIER5_Msk /*!< Software Interrupt on line 5 */
+#define EXTI_SWIER_SWIER6_Pos (6U)
+#define EXTI_SWIER_SWIER6_Msk (0x1U << EXTI_SWIER_SWIER6_Pos) /*!< 0x00000040 */
+#define EXTI_SWIER_SWIER6 EXTI_SWIER_SWIER6_Msk /*!< Software Interrupt on line 6 */
+#define EXTI_SWIER_SWIER7_Pos (7U)
+#define EXTI_SWIER_SWIER7_Msk (0x1U << EXTI_SWIER_SWIER7_Pos) /*!< 0x00000080 */
+#define EXTI_SWIER_SWIER7 EXTI_SWIER_SWIER7_Msk /*!< Software Interrupt on line 7 */
+#define EXTI_SWIER_SWIER8_Pos (8U)
+#define EXTI_SWIER_SWIER8_Msk (0x1U << EXTI_SWIER_SWIER8_Pos) /*!< 0x00000100 */
+#define EXTI_SWIER_SWIER8 EXTI_SWIER_SWIER8_Msk /*!< Software Interrupt on line 8 */
+#define EXTI_SWIER_SWIER9_Pos (9U)
+#define EXTI_SWIER_SWIER9_Msk (0x1U << EXTI_SWIER_SWIER9_Pos) /*!< 0x00000200 */
+#define EXTI_SWIER_SWIER9 EXTI_SWIER_SWIER9_Msk /*!< Software Interrupt on line 9 */
+#define EXTI_SWIER_SWIER10_Pos (10U)
+#define EXTI_SWIER_SWIER10_Msk (0x1U << EXTI_SWIER_SWIER10_Pos) /*!< 0x00000400 */
+#define EXTI_SWIER_SWIER10 EXTI_SWIER_SWIER10_Msk /*!< Software Interrupt on line 10 */
+#define EXTI_SWIER_SWIER11_Pos (11U)
+#define EXTI_SWIER_SWIER11_Msk (0x1U << EXTI_SWIER_SWIER11_Pos) /*!< 0x00000800 */
+#define EXTI_SWIER_SWIER11 EXTI_SWIER_SWIER11_Msk /*!< Software Interrupt on line 11 */
+#define EXTI_SWIER_SWIER12_Pos (12U)
+#define EXTI_SWIER_SWIER12_Msk (0x1U << EXTI_SWIER_SWIER12_Pos) /*!< 0x00001000 */
+#define EXTI_SWIER_SWIER12 EXTI_SWIER_SWIER12_Msk /*!< Software Interrupt on line 12 */
+#define EXTI_SWIER_SWIER13_Pos (13U)
+#define EXTI_SWIER_SWIER13_Msk (0x1U << EXTI_SWIER_SWIER13_Pos) /*!< 0x00002000 */
+#define EXTI_SWIER_SWIER13 EXTI_SWIER_SWIER13_Msk /*!< Software Interrupt on line 13 */
+#define EXTI_SWIER_SWIER14_Pos (14U)
+#define EXTI_SWIER_SWIER14_Msk (0x1U << EXTI_SWIER_SWIER14_Pos) /*!< 0x00004000 */
+#define EXTI_SWIER_SWIER14 EXTI_SWIER_SWIER14_Msk /*!< Software Interrupt on line 14 */
+#define EXTI_SWIER_SWIER15_Pos (15U)
+#define EXTI_SWIER_SWIER15_Msk (0x1U << EXTI_SWIER_SWIER15_Pos) /*!< 0x00008000 */
+#define EXTI_SWIER_SWIER15 EXTI_SWIER_SWIER15_Msk /*!< Software Interrupt on line 15 */
+#define EXTI_SWIER_SWIER16_Pos (16U)
+#define EXTI_SWIER_SWIER16_Msk (0x1U << EXTI_SWIER_SWIER16_Pos) /*!< 0x00010000 */
+#define EXTI_SWIER_SWIER16 EXTI_SWIER_SWIER16_Msk /*!< Software Interrupt on line 16 */
+#define EXTI_SWIER_SWIER17_Pos (17U)
+#define EXTI_SWIER_SWIER17_Msk (0x1U << EXTI_SWIER_SWIER17_Pos) /*!< 0x00020000 */
+#define EXTI_SWIER_SWIER17 EXTI_SWIER_SWIER17_Msk /*!< Software Interrupt on line 17 */
+#define EXTI_SWIER_SWIER18_Pos (18U)
+#define EXTI_SWIER_SWIER18_Msk (0x1U << EXTI_SWIER_SWIER18_Pos) /*!< 0x00040000 */
+#define EXTI_SWIER_SWIER18 EXTI_SWIER_SWIER18_Msk /*!< Software Interrupt on line 18 */
+#define EXTI_SWIER_SWIER19_Pos (19U)
+#define EXTI_SWIER_SWIER19_Msk (0x1U << EXTI_SWIER_SWIER19_Pos) /*!< 0x00080000 */
+#define EXTI_SWIER_SWIER19 EXTI_SWIER_SWIER19_Msk /*!< Software Interrupt on line 19 */
+
+/* References Defines */
+#define EXTI_SWIER_SWI0 EXTI_SWIER_SWIER0
+#define EXTI_SWIER_SWI1 EXTI_SWIER_SWIER1
+#define EXTI_SWIER_SWI2 EXTI_SWIER_SWIER2
+#define EXTI_SWIER_SWI3 EXTI_SWIER_SWIER3
+#define EXTI_SWIER_SWI4 EXTI_SWIER_SWIER4
+#define EXTI_SWIER_SWI5 EXTI_SWIER_SWIER5
+#define EXTI_SWIER_SWI6 EXTI_SWIER_SWIER6
+#define EXTI_SWIER_SWI7 EXTI_SWIER_SWIER7
+#define EXTI_SWIER_SWI8 EXTI_SWIER_SWIER8
+#define EXTI_SWIER_SWI9 EXTI_SWIER_SWIER9
+#define EXTI_SWIER_SWI10 EXTI_SWIER_SWIER10
+#define EXTI_SWIER_SWI11 EXTI_SWIER_SWIER11
+#define EXTI_SWIER_SWI12 EXTI_SWIER_SWIER12
+#define EXTI_SWIER_SWI13 EXTI_SWIER_SWIER13
+#define EXTI_SWIER_SWI14 EXTI_SWIER_SWIER14
+#define EXTI_SWIER_SWI15 EXTI_SWIER_SWIER15
+#define EXTI_SWIER_SWI16 EXTI_SWIER_SWIER16
+#define EXTI_SWIER_SWI17 EXTI_SWIER_SWIER17
+#define EXTI_SWIER_SWI18 EXTI_SWIER_SWIER18
+#define EXTI_SWIER_SWI19 EXTI_SWIER_SWIER19
+
+/******************* Bit definition for EXTI_PR register ********************/
+#define EXTI_PR_PR0_Pos (0U)
+#define EXTI_PR_PR0_Msk (0x1U << EXTI_PR_PR0_Pos) /*!< 0x00000001 */
+#define EXTI_PR_PR0 EXTI_PR_PR0_Msk /*!< Pending bit for line 0 */
+#define EXTI_PR_PR1_Pos (1U)
+#define EXTI_PR_PR1_Msk (0x1U << EXTI_PR_PR1_Pos) /*!< 0x00000002 */
+#define EXTI_PR_PR1 EXTI_PR_PR1_Msk /*!< Pending bit for line 1 */
+#define EXTI_PR_PR2_Pos (2U)
+#define EXTI_PR_PR2_Msk (0x1U << EXTI_PR_PR2_Pos) /*!< 0x00000004 */
+#define EXTI_PR_PR2 EXTI_PR_PR2_Msk /*!< Pending bit for line 2 */
+#define EXTI_PR_PR3_Pos (3U)
+#define EXTI_PR_PR3_Msk (0x1U << EXTI_PR_PR3_Pos) /*!< 0x00000008 */
+#define EXTI_PR_PR3 EXTI_PR_PR3_Msk /*!< Pending bit for line 3 */
+#define EXTI_PR_PR4_Pos (4U)
+#define EXTI_PR_PR4_Msk (0x1U << EXTI_PR_PR4_Pos) /*!< 0x00000010 */
+#define EXTI_PR_PR4 EXTI_PR_PR4_Msk /*!< Pending bit for line 4 */
+#define EXTI_PR_PR5_Pos (5U)
+#define EXTI_PR_PR5_Msk (0x1U << EXTI_PR_PR5_Pos) /*!< 0x00000020 */
+#define EXTI_PR_PR5 EXTI_PR_PR5_Msk /*!< Pending bit for line 5 */
+#define EXTI_PR_PR6_Pos (6U)
+#define EXTI_PR_PR6_Msk (0x1U << EXTI_PR_PR6_Pos) /*!< 0x00000040 */
+#define EXTI_PR_PR6 EXTI_PR_PR6_Msk /*!< Pending bit for line 6 */
+#define EXTI_PR_PR7_Pos (7U)
+#define EXTI_PR_PR7_Msk (0x1U << EXTI_PR_PR7_Pos) /*!< 0x00000080 */
+#define EXTI_PR_PR7 EXTI_PR_PR7_Msk /*!< Pending bit for line 7 */
+#define EXTI_PR_PR8_Pos (8U)
+#define EXTI_PR_PR8_Msk (0x1U << EXTI_PR_PR8_Pos) /*!< 0x00000100 */
+#define EXTI_PR_PR8 EXTI_PR_PR8_Msk /*!< Pending bit for line 8 */
+#define EXTI_PR_PR9_Pos (9U)
+#define EXTI_PR_PR9_Msk (0x1U << EXTI_PR_PR9_Pos) /*!< 0x00000200 */
+#define EXTI_PR_PR9 EXTI_PR_PR9_Msk /*!< Pending bit for line 9 */
+#define EXTI_PR_PR10_Pos (10U)
+#define EXTI_PR_PR10_Msk (0x1U << EXTI_PR_PR10_Pos) /*!< 0x00000400 */
+#define EXTI_PR_PR10 EXTI_PR_PR10_Msk /*!< Pending bit for line 10 */
+#define EXTI_PR_PR11_Pos (11U)
+#define EXTI_PR_PR11_Msk (0x1U << EXTI_PR_PR11_Pos) /*!< 0x00000800 */
+#define EXTI_PR_PR11 EXTI_PR_PR11_Msk /*!< Pending bit for line 11 */
+#define EXTI_PR_PR12_Pos (12U)
+#define EXTI_PR_PR12_Msk (0x1U << EXTI_PR_PR12_Pos) /*!< 0x00001000 */
+#define EXTI_PR_PR12 EXTI_PR_PR12_Msk /*!< Pending bit for line 12 */
+#define EXTI_PR_PR13_Pos (13U)
+#define EXTI_PR_PR13_Msk (0x1U << EXTI_PR_PR13_Pos) /*!< 0x00002000 */
+#define EXTI_PR_PR13 EXTI_PR_PR13_Msk /*!< Pending bit for line 13 */
+#define EXTI_PR_PR14_Pos (14U)
+#define EXTI_PR_PR14_Msk (0x1U << EXTI_PR_PR14_Pos) /*!< 0x00004000 */
+#define EXTI_PR_PR14 EXTI_PR_PR14_Msk /*!< Pending bit for line 14 */
+#define EXTI_PR_PR15_Pos (15U)
+#define EXTI_PR_PR15_Msk (0x1U << EXTI_PR_PR15_Pos) /*!< 0x00008000 */
+#define EXTI_PR_PR15 EXTI_PR_PR15_Msk /*!< Pending bit for line 15 */
+#define EXTI_PR_PR16_Pos (16U)
+#define EXTI_PR_PR16_Msk (0x1U << EXTI_PR_PR16_Pos) /*!< 0x00010000 */
+#define EXTI_PR_PR16 EXTI_PR_PR16_Msk /*!< Pending bit for line 16 */
+#define EXTI_PR_PR17_Pos (17U)
+#define EXTI_PR_PR17_Msk (0x1U << EXTI_PR_PR17_Pos) /*!< 0x00020000 */
+#define EXTI_PR_PR17 EXTI_PR_PR17_Msk /*!< Pending bit for line 17 */
+#define EXTI_PR_PR18_Pos (18U)
+#define EXTI_PR_PR18_Msk (0x1U << EXTI_PR_PR18_Pos) /*!< 0x00040000 */
+#define EXTI_PR_PR18 EXTI_PR_PR18_Msk /*!< Pending bit for line 18 */
+#define EXTI_PR_PR19_Pos (19U)
+#define EXTI_PR_PR19_Msk (0x1U << EXTI_PR_PR19_Pos) /*!< 0x00080000 */
+#define EXTI_PR_PR19 EXTI_PR_PR19_Msk /*!< Pending bit for line 19 */
+
+/* References Defines */
+#define EXTI_PR_PIF0 EXTI_PR_PR0
+#define EXTI_PR_PIF1 EXTI_PR_PR1
+#define EXTI_PR_PIF2 EXTI_PR_PR2
+#define EXTI_PR_PIF3 EXTI_PR_PR3
+#define EXTI_PR_PIF4 EXTI_PR_PR4
+#define EXTI_PR_PIF5 EXTI_PR_PR5
+#define EXTI_PR_PIF6 EXTI_PR_PR6
+#define EXTI_PR_PIF7 EXTI_PR_PR7
+#define EXTI_PR_PIF8 EXTI_PR_PR8
+#define EXTI_PR_PIF9 EXTI_PR_PR9
+#define EXTI_PR_PIF10 EXTI_PR_PR10
+#define EXTI_PR_PIF11 EXTI_PR_PR11
+#define EXTI_PR_PIF12 EXTI_PR_PR12
+#define EXTI_PR_PIF13 EXTI_PR_PR13
+#define EXTI_PR_PIF14 EXTI_PR_PR14
+#define EXTI_PR_PIF15 EXTI_PR_PR15
+#define EXTI_PR_PIF16 EXTI_PR_PR16
+#define EXTI_PR_PIF17 EXTI_PR_PR17
+#define EXTI_PR_PIF18 EXTI_PR_PR18
+#define EXTI_PR_PIF19 EXTI_PR_PR19
+
+/******************************************************************************/
+/* */
+/* DMA Controller */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for DMA_ISR register ********************/
+#define DMA_ISR_GIF1_Pos (0U)
+#define DMA_ISR_GIF1_Msk (0x1U << DMA_ISR_GIF1_Pos) /*!< 0x00000001 */
+#define DMA_ISR_GIF1 DMA_ISR_GIF1_Msk /*!< Channel 1 Global interrupt flag */
+#define DMA_ISR_TCIF1_Pos (1U)
+#define DMA_ISR_TCIF1_Msk (0x1U << DMA_ISR_TCIF1_Pos) /*!< 0x00000002 */
+#define DMA_ISR_TCIF1 DMA_ISR_TCIF1_Msk /*!< Channel 1 Transfer Complete flag */
+#define DMA_ISR_HTIF1_Pos (2U)
+#define DMA_ISR_HTIF1_Msk (0x1U << DMA_ISR_HTIF1_Pos) /*!< 0x00000004 */
+#define DMA_ISR_HTIF1 DMA_ISR_HTIF1_Msk /*!< Channel 1 Half Transfer flag */
+#define DMA_ISR_TEIF1_Pos (3U)
+#define DMA_ISR_TEIF1_Msk (0x1U << DMA_ISR_TEIF1_Pos) /*!< 0x00000008 */
+#define DMA_ISR_TEIF1 DMA_ISR_TEIF1_Msk /*!< Channel 1 Transfer Error flag */
+#define DMA_ISR_GIF2_Pos (4U)
+#define DMA_ISR_GIF2_Msk (0x1U << DMA_ISR_GIF2_Pos) /*!< 0x00000010 */
+#define DMA_ISR_GIF2 DMA_ISR_GIF2_Msk /*!< Channel 2 Global interrupt flag */
+#define DMA_ISR_TCIF2_Pos (5U)
+#define DMA_ISR_TCIF2_Msk (0x1U << DMA_ISR_TCIF2_Pos) /*!< 0x00000020 */
+#define DMA_ISR_TCIF2 DMA_ISR_TCIF2_Msk /*!< Channel 2 Transfer Complete flag */
+#define DMA_ISR_HTIF2_Pos (6U)
+#define DMA_ISR_HTIF2_Msk (0x1U << DMA_ISR_HTIF2_Pos) /*!< 0x00000040 */
+#define DMA_ISR_HTIF2 DMA_ISR_HTIF2_Msk /*!< Channel 2 Half Transfer flag */
+#define DMA_ISR_TEIF2_Pos (7U)
+#define DMA_ISR_TEIF2_Msk (0x1U << DMA_ISR_TEIF2_Pos) /*!< 0x00000080 */
+#define DMA_ISR_TEIF2 DMA_ISR_TEIF2_Msk /*!< Channel 2 Transfer Error flag */
+#define DMA_ISR_GIF3_Pos (8U)
+#define DMA_ISR_GIF3_Msk (0x1U << DMA_ISR_GIF3_Pos) /*!< 0x00000100 */
+#define DMA_ISR_GIF3 DMA_ISR_GIF3_Msk /*!< Channel 3 Global interrupt flag */
+#define DMA_ISR_TCIF3_Pos (9U)
+#define DMA_ISR_TCIF3_Msk (0x1U << DMA_ISR_TCIF3_Pos) /*!< 0x00000200 */
+#define DMA_ISR_TCIF3 DMA_ISR_TCIF3_Msk /*!< Channel 3 Transfer Complete flag */
+#define DMA_ISR_HTIF3_Pos (10U)
+#define DMA_ISR_HTIF3_Msk (0x1U << DMA_ISR_HTIF3_Pos) /*!< 0x00000400 */
+#define DMA_ISR_HTIF3 DMA_ISR_HTIF3_Msk /*!< Channel 3 Half Transfer flag */
+#define DMA_ISR_TEIF3_Pos (11U)
+#define DMA_ISR_TEIF3_Msk (0x1U << DMA_ISR_TEIF3_Pos) /*!< 0x00000800 */
+#define DMA_ISR_TEIF3 DMA_ISR_TEIF3_Msk /*!< Channel 3 Transfer Error flag */
+#define DMA_ISR_GIF4_Pos (12U)
+#define DMA_ISR_GIF4_Msk (0x1U << DMA_ISR_GIF4_Pos) /*!< 0x00001000 */
+#define DMA_ISR_GIF4 DMA_ISR_GIF4_Msk /*!< Channel 4 Global interrupt flag */
+#define DMA_ISR_TCIF4_Pos (13U)
+#define DMA_ISR_TCIF4_Msk (0x1U << DMA_ISR_TCIF4_Pos) /*!< 0x00002000 */
+#define DMA_ISR_TCIF4 DMA_ISR_TCIF4_Msk /*!< Channel 4 Transfer Complete flag */
+#define DMA_ISR_HTIF4_Pos (14U)
+#define DMA_ISR_HTIF4_Msk (0x1U << DMA_ISR_HTIF4_Pos) /*!< 0x00004000 */
+#define DMA_ISR_HTIF4 DMA_ISR_HTIF4_Msk /*!< Channel 4 Half Transfer flag */
+#define DMA_ISR_TEIF4_Pos (15U)
+#define DMA_ISR_TEIF4_Msk (0x1U << DMA_ISR_TEIF4_Pos) /*!< 0x00008000 */
+#define DMA_ISR_TEIF4 DMA_ISR_TEIF4_Msk /*!< Channel 4 Transfer Error flag */
+#define DMA_ISR_GIF5_Pos (16U)
+#define DMA_ISR_GIF5_Msk (0x1U << DMA_ISR_GIF5_Pos) /*!< 0x00010000 */
+#define DMA_ISR_GIF5 DMA_ISR_GIF5_Msk /*!< Channel 5 Global interrupt flag */
+#define DMA_ISR_TCIF5_Pos (17U)
+#define DMA_ISR_TCIF5_Msk (0x1U << DMA_ISR_TCIF5_Pos) /*!< 0x00020000 */
+#define DMA_ISR_TCIF5 DMA_ISR_TCIF5_Msk /*!< Channel 5 Transfer Complete flag */
+#define DMA_ISR_HTIF5_Pos (18U)
+#define DMA_ISR_HTIF5_Msk (0x1U << DMA_ISR_HTIF5_Pos) /*!< 0x00040000 */
+#define DMA_ISR_HTIF5 DMA_ISR_HTIF5_Msk /*!< Channel 5 Half Transfer flag */
+#define DMA_ISR_TEIF5_Pos (19U)
+#define DMA_ISR_TEIF5_Msk (0x1U << DMA_ISR_TEIF5_Pos) /*!< 0x00080000 */
+#define DMA_ISR_TEIF5 DMA_ISR_TEIF5_Msk /*!< Channel 5 Transfer Error flag */
+#define DMA_ISR_GIF6_Pos (20U)
+#define DMA_ISR_GIF6_Msk (0x1U << DMA_ISR_GIF6_Pos) /*!< 0x00100000 */
+#define DMA_ISR_GIF6 DMA_ISR_GIF6_Msk /*!< Channel 6 Global interrupt flag */
+#define DMA_ISR_TCIF6_Pos (21U)
+#define DMA_ISR_TCIF6_Msk (0x1U << DMA_ISR_TCIF6_Pos) /*!< 0x00200000 */
+#define DMA_ISR_TCIF6 DMA_ISR_TCIF6_Msk /*!< Channel 6 Transfer Complete flag */
+#define DMA_ISR_HTIF6_Pos (22U)
+#define DMA_ISR_HTIF6_Msk (0x1U << DMA_ISR_HTIF6_Pos) /*!< 0x00400000 */
+#define DMA_ISR_HTIF6 DMA_ISR_HTIF6_Msk /*!< Channel 6 Half Transfer flag */
+#define DMA_ISR_TEIF6_Pos (23U)
+#define DMA_ISR_TEIF6_Msk (0x1U << DMA_ISR_TEIF6_Pos) /*!< 0x00800000 */
+#define DMA_ISR_TEIF6 DMA_ISR_TEIF6_Msk /*!< Channel 6 Transfer Error flag */
+#define DMA_ISR_GIF7_Pos (24U)
+#define DMA_ISR_GIF7_Msk (0x1U << DMA_ISR_GIF7_Pos) /*!< 0x01000000 */
+#define DMA_ISR_GIF7 DMA_ISR_GIF7_Msk /*!< Channel 7 Global interrupt flag */
+#define DMA_ISR_TCIF7_Pos (25U)
+#define DMA_ISR_TCIF7_Msk (0x1U << DMA_ISR_TCIF7_Pos) /*!< 0x02000000 */
+#define DMA_ISR_TCIF7 DMA_ISR_TCIF7_Msk /*!< Channel 7 Transfer Complete flag */
+#define DMA_ISR_HTIF7_Pos (26U)
+#define DMA_ISR_HTIF7_Msk (0x1U << DMA_ISR_HTIF7_Pos) /*!< 0x04000000 */
+#define DMA_ISR_HTIF7 DMA_ISR_HTIF7_Msk /*!< Channel 7 Half Transfer flag */
+#define DMA_ISR_TEIF7_Pos (27U)
+#define DMA_ISR_TEIF7_Msk (0x1U << DMA_ISR_TEIF7_Pos) /*!< 0x08000000 */
+#define DMA_ISR_TEIF7 DMA_ISR_TEIF7_Msk /*!< Channel 7 Transfer Error flag */
+
+/******************* Bit definition for DMA_IFCR register *******************/
+#define DMA_IFCR_CGIF1_Pos (0U)
+#define DMA_IFCR_CGIF1_Msk (0x1U << DMA_IFCR_CGIF1_Pos) /*!< 0x00000001 */
+#define DMA_IFCR_CGIF1 DMA_IFCR_CGIF1_Msk /*!< Channel 1 Global interrupt clear */
+#define DMA_IFCR_CTCIF1_Pos (1U)
+#define DMA_IFCR_CTCIF1_Msk (0x1U << DMA_IFCR_CTCIF1_Pos) /*!< 0x00000002 */
+#define DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF1_Msk /*!< Channel 1 Transfer Complete clear */
+#define DMA_IFCR_CHTIF1_Pos (2U)
+#define DMA_IFCR_CHTIF1_Msk (0x1U << DMA_IFCR_CHTIF1_Pos) /*!< 0x00000004 */
+#define DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF1_Msk /*!< Channel 1 Half Transfer clear */
+#define DMA_IFCR_CTEIF1_Pos (3U)
+#define DMA_IFCR_CTEIF1_Msk (0x1U << DMA_IFCR_CTEIF1_Pos) /*!< 0x00000008 */
+#define DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF1_Msk /*!< Channel 1 Transfer Error clear */
+#define DMA_IFCR_CGIF2_Pos (4U)
+#define DMA_IFCR_CGIF2_Msk (0x1U << DMA_IFCR_CGIF2_Pos) /*!< 0x00000010 */
+#define DMA_IFCR_CGIF2 DMA_IFCR_CGIF2_Msk /*!< Channel 2 Global interrupt clear */
+#define DMA_IFCR_CTCIF2_Pos (5U)
+#define DMA_IFCR_CTCIF2_Msk (0x1U << DMA_IFCR_CTCIF2_Pos) /*!< 0x00000020 */
+#define DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF2_Msk /*!< Channel 2 Transfer Complete clear */
+#define DMA_IFCR_CHTIF2_Pos (6U)
+#define DMA_IFCR_CHTIF2_Msk (0x1U << DMA_IFCR_CHTIF2_Pos) /*!< 0x00000040 */
+#define DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF2_Msk /*!< Channel 2 Half Transfer clear */
+#define DMA_IFCR_CTEIF2_Pos (7U)
+#define DMA_IFCR_CTEIF2_Msk (0x1U << DMA_IFCR_CTEIF2_Pos) /*!< 0x00000080 */
+#define DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF2_Msk /*!< Channel 2 Transfer Error clear */
+#define DMA_IFCR_CGIF3_Pos (8U)
+#define DMA_IFCR_CGIF3_Msk (0x1U << DMA_IFCR_CGIF3_Pos) /*!< 0x00000100 */
+#define DMA_IFCR_CGIF3 DMA_IFCR_CGIF3_Msk /*!< Channel 3 Global interrupt clear */
+#define DMA_IFCR_CTCIF3_Pos (9U)
+#define DMA_IFCR_CTCIF3_Msk (0x1U << DMA_IFCR_CTCIF3_Pos) /*!< 0x00000200 */
+#define DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF3_Msk /*!< Channel 3 Transfer Complete clear */
+#define DMA_IFCR_CHTIF3_Pos (10U)
+#define DMA_IFCR_CHTIF3_Msk (0x1U << DMA_IFCR_CHTIF3_Pos) /*!< 0x00000400 */
+#define DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF3_Msk /*!< Channel 3 Half Transfer clear */
+#define DMA_IFCR_CTEIF3_Pos (11U)
+#define DMA_IFCR_CTEIF3_Msk (0x1U << DMA_IFCR_CTEIF3_Pos) /*!< 0x00000800 */
+#define DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF3_Msk /*!< Channel 3 Transfer Error clear */
+#define DMA_IFCR_CGIF4_Pos (12U)
+#define DMA_IFCR_CGIF4_Msk (0x1U << DMA_IFCR_CGIF4_Pos) /*!< 0x00001000 */
+#define DMA_IFCR_CGIF4 DMA_IFCR_CGIF4_Msk /*!< Channel 4 Global interrupt clear */
+#define DMA_IFCR_CTCIF4_Pos (13U)
+#define DMA_IFCR_CTCIF4_Msk (0x1U << DMA_IFCR_CTCIF4_Pos) /*!< 0x00002000 */
+#define DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF4_Msk /*!< Channel 4 Transfer Complete clear */
+#define DMA_IFCR_CHTIF4_Pos (14U)
+#define DMA_IFCR_CHTIF4_Msk (0x1U << DMA_IFCR_CHTIF4_Pos) /*!< 0x00004000 */
+#define DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF4_Msk /*!< Channel 4 Half Transfer clear */
+#define DMA_IFCR_CTEIF4_Pos (15U)
+#define DMA_IFCR_CTEIF4_Msk (0x1U << DMA_IFCR_CTEIF4_Pos) /*!< 0x00008000 */
+#define DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF4_Msk /*!< Channel 4 Transfer Error clear */
+#define DMA_IFCR_CGIF5_Pos (16U)
+#define DMA_IFCR_CGIF5_Msk (0x1U << DMA_IFCR_CGIF5_Pos) /*!< 0x00010000 */
+#define DMA_IFCR_CGIF5 DMA_IFCR_CGIF5_Msk /*!< Channel 5 Global interrupt clear */
+#define DMA_IFCR_CTCIF5_Pos (17U)
+#define DMA_IFCR_CTCIF5_Msk (0x1U << DMA_IFCR_CTCIF5_Pos) /*!< 0x00020000 */
+#define DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF5_Msk /*!< Channel 5 Transfer Complete clear */
+#define DMA_IFCR_CHTIF5_Pos (18U)
+#define DMA_IFCR_CHTIF5_Msk (0x1U << DMA_IFCR_CHTIF5_Pos) /*!< 0x00040000 */
+#define DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5_Msk /*!< Channel 5 Half Transfer clear */
+#define DMA_IFCR_CTEIF5_Pos (19U)
+#define DMA_IFCR_CTEIF5_Msk (0x1U << DMA_IFCR_CTEIF5_Pos) /*!< 0x00080000 */
+#define DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF5_Msk /*!< Channel 5 Transfer Error clear */
+#define DMA_IFCR_CGIF6_Pos (20U)
+#define DMA_IFCR_CGIF6_Msk (0x1U << DMA_IFCR_CGIF6_Pos) /*!< 0x00100000 */
+#define DMA_IFCR_CGIF6 DMA_IFCR_CGIF6_Msk /*!< Channel 6 Global interrupt clear */
+#define DMA_IFCR_CTCIF6_Pos (21U)
+#define DMA_IFCR_CTCIF6_Msk (0x1U << DMA_IFCR_CTCIF6_Pos) /*!< 0x00200000 */
+#define DMA_IFCR_CTCIF6 DMA_IFCR_CTCIF6_Msk /*!< Channel 6 Transfer Complete clear */
+#define DMA_IFCR_CHTIF6_Pos (22U)
+#define DMA_IFCR_CHTIF6_Msk (0x1U << DMA_IFCR_CHTIF6_Pos) /*!< 0x00400000 */
+#define DMA_IFCR_CHTIF6 DMA_IFCR_CHTIF6_Msk /*!< Channel 6 Half Transfer clear */
+#define DMA_IFCR_CTEIF6_Pos (23U)
+#define DMA_IFCR_CTEIF6_Msk (0x1U << DMA_IFCR_CTEIF6_Pos) /*!< 0x00800000 */
+#define DMA_IFCR_CTEIF6 DMA_IFCR_CTEIF6_Msk /*!< Channel 6 Transfer Error clear */
+#define DMA_IFCR_CGIF7_Pos (24U)
+#define DMA_IFCR_CGIF7_Msk (0x1U << DMA_IFCR_CGIF7_Pos) /*!< 0x01000000 */
+#define DMA_IFCR_CGIF7 DMA_IFCR_CGIF7_Msk /*!< Channel 7 Global interrupt clear */
+#define DMA_IFCR_CTCIF7_Pos (25U)
+#define DMA_IFCR_CTCIF7_Msk (0x1U << DMA_IFCR_CTCIF7_Pos) /*!< 0x02000000 */
+#define DMA_IFCR_CTCIF7 DMA_IFCR_CTCIF7_Msk /*!< Channel 7 Transfer Complete clear */
+#define DMA_IFCR_CHTIF7_Pos (26U)
+#define DMA_IFCR_CHTIF7_Msk (0x1U << DMA_IFCR_CHTIF7_Pos) /*!< 0x04000000 */
+#define DMA_IFCR_CHTIF7 DMA_IFCR_CHTIF7_Msk /*!< Channel 7 Half Transfer clear */
+#define DMA_IFCR_CTEIF7_Pos (27U)
+#define DMA_IFCR_CTEIF7_Msk (0x1U << DMA_IFCR_CTEIF7_Pos) /*!< 0x08000000 */
+#define DMA_IFCR_CTEIF7 DMA_IFCR_CTEIF7_Msk /*!< Channel 7 Transfer Error clear */
+
+/******************* Bit definition for DMA_CCR register *******************/
+#define DMA_CCR_EN_Pos (0U)
+#define DMA_CCR_EN_Msk (0x1U << DMA_CCR_EN_Pos) /*!< 0x00000001 */
+#define DMA_CCR_EN DMA_CCR_EN_Msk /*!< Channel enable */
+#define DMA_CCR_TCIE_Pos (1U)
+#define DMA_CCR_TCIE_Msk (0x1U << DMA_CCR_TCIE_Pos) /*!< 0x00000002 */
+#define DMA_CCR_TCIE DMA_CCR_TCIE_Msk /*!< Transfer complete interrupt enable */
+#define DMA_CCR_HTIE_Pos (2U)
+#define DMA_CCR_HTIE_Msk (0x1U << DMA_CCR_HTIE_Pos) /*!< 0x00000004 */
+#define DMA_CCR_HTIE DMA_CCR_HTIE_Msk /*!< Half Transfer interrupt enable */
+#define DMA_CCR_TEIE_Pos (3U)
+#define DMA_CCR_TEIE_Msk (0x1U << DMA_CCR_TEIE_Pos) /*!< 0x00000008 */
+#define DMA_CCR_TEIE DMA_CCR_TEIE_Msk /*!< Transfer error interrupt enable */
+#define DMA_CCR_DIR_Pos (4U)
+#define DMA_CCR_DIR_Msk (0x1U << DMA_CCR_DIR_Pos) /*!< 0x00000010 */
+#define DMA_CCR_DIR DMA_CCR_DIR_Msk /*!< Data transfer direction */
+#define DMA_CCR_CIRC_Pos (5U)
+#define DMA_CCR_CIRC_Msk (0x1U << DMA_CCR_CIRC_Pos) /*!< 0x00000020 */
+#define DMA_CCR_CIRC DMA_CCR_CIRC_Msk /*!< Circular mode */
+#define DMA_CCR_PINC_Pos (6U)
+#define DMA_CCR_PINC_Msk (0x1U << DMA_CCR_PINC_Pos) /*!< 0x00000040 */
+#define DMA_CCR_PINC DMA_CCR_PINC_Msk /*!< Peripheral increment mode */
+#define DMA_CCR_MINC_Pos (7U)
+#define DMA_CCR_MINC_Msk (0x1U << DMA_CCR_MINC_Pos) /*!< 0x00000080 */
+#define DMA_CCR_MINC DMA_CCR_MINC_Msk /*!< Memory increment mode */
+
+#define DMA_CCR_PSIZE_Pos (8U)
+#define DMA_CCR_PSIZE_Msk (0x3U << DMA_CCR_PSIZE_Pos) /*!< 0x00000300 */
+#define DMA_CCR_PSIZE DMA_CCR_PSIZE_Msk /*!< PSIZE[1:0] bits (Peripheral size) */
+#define DMA_CCR_PSIZE_0 (0x1U << DMA_CCR_PSIZE_Pos) /*!< 0x00000100 */
+#define DMA_CCR_PSIZE_1 (0x2U << DMA_CCR_PSIZE_Pos) /*!< 0x00000200 */
+
+#define DMA_CCR_MSIZE_Pos (10U)
+#define DMA_CCR_MSIZE_Msk (0x3U << DMA_CCR_MSIZE_Pos) /*!< 0x00000C00 */
+#define DMA_CCR_MSIZE DMA_CCR_MSIZE_Msk /*!< MSIZE[1:0] bits (Memory size) */
+#define DMA_CCR_MSIZE_0 (0x1U << DMA_CCR_MSIZE_Pos) /*!< 0x00000400 */
+#define DMA_CCR_MSIZE_1 (0x2U << DMA_CCR_MSIZE_Pos) /*!< 0x00000800 */
+
+#define DMA_CCR_PL_Pos (12U)
+#define DMA_CCR_PL_Msk (0x3U << DMA_CCR_PL_Pos) /*!< 0x00003000 */
+#define DMA_CCR_PL DMA_CCR_PL_Msk /*!< PL[1:0] bits(Channel Priority level) */
+#define DMA_CCR_PL_0 (0x1U << DMA_CCR_PL_Pos) /*!< 0x00001000 */
+#define DMA_CCR_PL_1 (0x2U << DMA_CCR_PL_Pos) /*!< 0x00002000 */
+
+#define DMA_CCR_MEM2MEM_Pos (14U)
+#define DMA_CCR_MEM2MEM_Msk (0x1U << DMA_CCR_MEM2MEM_Pos) /*!< 0x00004000 */
+#define DMA_CCR_MEM2MEM DMA_CCR_MEM2MEM_Msk /*!< Memory to memory mode */
+
+/****************** Bit definition for DMA_CNDTR register ******************/
+#define DMA_CNDTR_NDT_Pos (0U)
+#define DMA_CNDTR_NDT_Msk (0xFFFFU << DMA_CNDTR_NDT_Pos) /*!< 0x0000FFFF */
+#define DMA_CNDTR_NDT DMA_CNDTR_NDT_Msk /*!< Number of data to Transfer */
+
+/****************** Bit definition for DMA_CPAR register *******************/
+#define DMA_CPAR_PA_Pos (0U)
+#define DMA_CPAR_PA_Msk (0xFFFFFFFFU << DMA_CPAR_PA_Pos) /*!< 0xFFFFFFFF */
+#define DMA_CPAR_PA DMA_CPAR_PA_Msk /*!< Peripheral Address */
+
+/****************** Bit definition for DMA_CMAR register *******************/
+#define DMA_CMAR_MA_Pos (0U)
+#define DMA_CMAR_MA_Msk (0xFFFFFFFFU << DMA_CMAR_MA_Pos) /*!< 0xFFFFFFFF */
+#define DMA_CMAR_MA DMA_CMAR_MA_Msk /*!< Memory Address */
+
+/******************************************************************************/
+/* */
+/* Analog to Digital Converter (ADC) */
+/* */
+/******************************************************************************/
+
+/*
+ * @brief Specific device feature definitions (not present on all devices in the STM32F1 family)
+ */
+/* Note: No specific macro feature on this device */
+
+/******************** Bit definition for ADC_SR register ********************/
+#define ADC_SR_AWD_Pos (0U)
+#define ADC_SR_AWD_Msk (0x1U << ADC_SR_AWD_Pos) /*!< 0x00000001 */
+#define ADC_SR_AWD ADC_SR_AWD_Msk /*!< ADC analog watchdog 1 flag */
+#define ADC_SR_EOS_Pos (1U)
+#define ADC_SR_EOS_Msk (0x1U << ADC_SR_EOS_Pos) /*!< 0x00000002 */
+#define ADC_SR_EOS ADC_SR_EOS_Msk /*!< ADC group regular end of sequence conversions flag */
+#define ADC_SR_JEOS_Pos (2U)
+#define ADC_SR_JEOS_Msk (0x1U << ADC_SR_JEOS_Pos) /*!< 0x00000004 */
+#define ADC_SR_JEOS ADC_SR_JEOS_Msk /*!< ADC group injected end of sequence conversions flag */
+#define ADC_SR_JSTRT_Pos (3U)
+#define ADC_SR_JSTRT_Msk (0x1U << ADC_SR_JSTRT_Pos) /*!< 0x00000008 */
+#define ADC_SR_JSTRT ADC_SR_JSTRT_Msk /*!< ADC group injected conversion start flag */
+#define ADC_SR_STRT_Pos (4U)
+#define ADC_SR_STRT_Msk (0x1U << ADC_SR_STRT_Pos) /*!< 0x00000010 */
+#define ADC_SR_STRT ADC_SR_STRT_Msk /*!< ADC group regular conversion start flag */
+
+/* Legacy defines */
+#define ADC_SR_EOC (ADC_SR_EOS)
+#define ADC_SR_JEOC (ADC_SR_JEOS)
+
+/******************* Bit definition for ADC_CR1 register ********************/
+#define ADC_CR1_AWDCH_Pos (0U)
+#define ADC_CR1_AWDCH_Msk (0x1FU << ADC_CR1_AWDCH_Pos) /*!< 0x0000001F */
+#define ADC_CR1_AWDCH ADC_CR1_AWDCH_Msk /*!< ADC analog watchdog 1 monitored channel selection */
+#define ADC_CR1_AWDCH_0 (0x01U << ADC_CR1_AWDCH_Pos) /*!< 0x00000001 */
+#define ADC_CR1_AWDCH_1 (0x02U << ADC_CR1_AWDCH_Pos) /*!< 0x00000002 */
+#define ADC_CR1_AWDCH_2 (0x04U << ADC_CR1_AWDCH_Pos) /*!< 0x00000004 */
+#define ADC_CR1_AWDCH_3 (0x08U << ADC_CR1_AWDCH_Pos) /*!< 0x00000008 */
+#define ADC_CR1_AWDCH_4 (0x10U << ADC_CR1_AWDCH_Pos) /*!< 0x00000010 */
+
+#define ADC_CR1_EOSIE_Pos (5U)
+#define ADC_CR1_EOSIE_Msk (0x1U << ADC_CR1_EOSIE_Pos) /*!< 0x00000020 */
+#define ADC_CR1_EOSIE ADC_CR1_EOSIE_Msk /*!< ADC group regular end of sequence conversions interrupt */
+#define ADC_CR1_AWDIE_Pos (6U)
+#define ADC_CR1_AWDIE_Msk (0x1U << ADC_CR1_AWDIE_Pos) /*!< 0x00000040 */
+#define ADC_CR1_AWDIE ADC_CR1_AWDIE_Msk /*!< ADC analog watchdog 1 interrupt */
+#define ADC_CR1_JEOSIE_Pos (7U)
+#define ADC_CR1_JEOSIE_Msk (0x1U << ADC_CR1_JEOSIE_Pos) /*!< 0x00000080 */
+#define ADC_CR1_JEOSIE ADC_CR1_JEOSIE_Msk /*!< ADC group injected end of sequence conversions interrupt */
+#define ADC_CR1_SCAN_Pos (8U)
+#define ADC_CR1_SCAN_Msk (0x1U << ADC_CR1_SCAN_Pos) /*!< 0x00000100 */
+#define ADC_CR1_SCAN ADC_CR1_SCAN_Msk /*!< ADC scan mode */
+#define ADC_CR1_AWDSGL_Pos (9U)
+#define ADC_CR1_AWDSGL_Msk (0x1U << ADC_CR1_AWDSGL_Pos) /*!< 0x00000200 */
+#define ADC_CR1_AWDSGL ADC_CR1_AWDSGL_Msk /*!< ADC analog watchdog 1 monitoring a single channel or all channels */
+#define ADC_CR1_JAUTO_Pos (10U)
+#define ADC_CR1_JAUTO_Msk (0x1U << ADC_CR1_JAUTO_Pos) /*!< 0x00000400 */
+#define ADC_CR1_JAUTO ADC_CR1_JAUTO_Msk /*!< ADC group injected automatic trigger mode */
+#define ADC_CR1_DISCEN_Pos (11U)
+#define ADC_CR1_DISCEN_Msk (0x1U << ADC_CR1_DISCEN_Pos) /*!< 0x00000800 */
+#define ADC_CR1_DISCEN ADC_CR1_DISCEN_Msk /*!< ADC group regular sequencer discontinuous mode */
+#define ADC_CR1_JDISCEN_Pos (12U)
+#define ADC_CR1_JDISCEN_Msk (0x1U << ADC_CR1_JDISCEN_Pos) /*!< 0x00001000 */
+#define ADC_CR1_JDISCEN ADC_CR1_JDISCEN_Msk /*!< ADC group injected sequencer discontinuous mode */
+
+#define ADC_CR1_DISCNUM_Pos (13U)
+#define ADC_CR1_DISCNUM_Msk (0x7U << ADC_CR1_DISCNUM_Pos) /*!< 0x0000E000 */
+#define ADC_CR1_DISCNUM ADC_CR1_DISCNUM_Msk /*!< ADC group regular sequencer discontinuous number of ranks */
+#define ADC_CR1_DISCNUM_0 (0x1U << ADC_CR1_DISCNUM_Pos) /*!< 0x00002000 */
+#define ADC_CR1_DISCNUM_1 (0x2U << ADC_CR1_DISCNUM_Pos) /*!< 0x00004000 */
+#define ADC_CR1_DISCNUM_2 (0x4U << ADC_CR1_DISCNUM_Pos) /*!< 0x00008000 */
+
+#define ADC_CR1_JAWDEN_Pos (22U)
+#define ADC_CR1_JAWDEN_Msk (0x1U << ADC_CR1_JAWDEN_Pos) /*!< 0x00400000 */
+#define ADC_CR1_JAWDEN ADC_CR1_JAWDEN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group injected */
+#define ADC_CR1_AWDEN_Pos (23U)
+#define ADC_CR1_AWDEN_Msk (0x1U << ADC_CR1_AWDEN_Pos) /*!< 0x00800000 */
+#define ADC_CR1_AWDEN ADC_CR1_AWDEN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group regular */
+
+/* Legacy defines */
+#define ADC_CR1_EOCIE (ADC_CR1_EOSIE)
+#define ADC_CR1_JEOCIE (ADC_CR1_JEOSIE)
+
+/******************* Bit definition for ADC_CR2 register ********************/
+#define ADC_CR2_ADON_Pos (0U)
+#define ADC_CR2_ADON_Msk (0x1U << ADC_CR2_ADON_Pos) /*!< 0x00000001 */
+#define ADC_CR2_ADON ADC_CR2_ADON_Msk /*!< ADC enable */
+#define ADC_CR2_CONT_Pos (1U)
+#define ADC_CR2_CONT_Msk (0x1U << ADC_CR2_CONT_Pos) /*!< 0x00000002 */
+#define ADC_CR2_CONT ADC_CR2_CONT_Msk /*!< ADC group regular continuous conversion mode */
+#define ADC_CR2_CAL_Pos (2U)
+#define ADC_CR2_CAL_Msk (0x1U << ADC_CR2_CAL_Pos) /*!< 0x00000004 */
+#define ADC_CR2_CAL ADC_CR2_CAL_Msk /*!< ADC calibration start */
+#define ADC_CR2_RSTCAL_Pos (3U)
+#define ADC_CR2_RSTCAL_Msk (0x1U << ADC_CR2_RSTCAL_Pos) /*!< 0x00000008 */
+#define ADC_CR2_RSTCAL ADC_CR2_RSTCAL_Msk /*!< ADC calibration reset */
+#define ADC_CR2_DMA_Pos (8U)
+#define ADC_CR2_DMA_Msk (0x1U << ADC_CR2_DMA_Pos) /*!< 0x00000100 */
+#define ADC_CR2_DMA ADC_CR2_DMA_Msk /*!< ADC DMA transfer enable */
+#define ADC_CR2_ALIGN_Pos (11U)
+#define ADC_CR2_ALIGN_Msk (0x1U << ADC_CR2_ALIGN_Pos) /*!< 0x00000800 */
+#define ADC_CR2_ALIGN ADC_CR2_ALIGN_Msk /*!< ADC data alignement */
+
+#define ADC_CR2_JEXTSEL_Pos (12U)
+#define ADC_CR2_JEXTSEL_Msk (0x7U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00007000 */
+#define ADC_CR2_JEXTSEL ADC_CR2_JEXTSEL_Msk /*!< ADC group injected external trigger source */
+#define ADC_CR2_JEXTSEL_0 (0x1U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00001000 */
+#define ADC_CR2_JEXTSEL_1 (0x2U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00002000 */
+#define ADC_CR2_JEXTSEL_2 (0x4U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00004000 */
+
+#define ADC_CR2_JEXTTRIG_Pos (15U)
+#define ADC_CR2_JEXTTRIG_Msk (0x1U << ADC_CR2_JEXTTRIG_Pos) /*!< 0x00008000 */
+#define ADC_CR2_JEXTTRIG ADC_CR2_JEXTTRIG_Msk /*!< ADC group injected external trigger enable */
+
+#define ADC_CR2_EXTSEL_Pos (17U)
+#define ADC_CR2_EXTSEL_Msk (0x7U << ADC_CR2_EXTSEL_Pos) /*!< 0x000E0000 */
+#define ADC_CR2_EXTSEL ADC_CR2_EXTSEL_Msk /*!< ADC group regular external trigger source */
+#define ADC_CR2_EXTSEL_0 (0x1U << ADC_CR2_EXTSEL_Pos) /*!< 0x00020000 */
+#define ADC_CR2_EXTSEL_1 (0x2U << ADC_CR2_EXTSEL_Pos) /*!< 0x00040000 */
+#define ADC_CR2_EXTSEL_2 (0x4U << ADC_CR2_EXTSEL_Pos) /*!< 0x00080000 */
+
+#define ADC_CR2_EXTTRIG_Pos (20U)
+#define ADC_CR2_EXTTRIG_Msk (0x1U << ADC_CR2_EXTTRIG_Pos) /*!< 0x00100000 */
+#define ADC_CR2_EXTTRIG ADC_CR2_EXTTRIG_Msk /*!< ADC group regular external trigger enable */
+#define ADC_CR2_JSWSTART_Pos (21U)
+#define ADC_CR2_JSWSTART_Msk (0x1U << ADC_CR2_JSWSTART_Pos) /*!< 0x00200000 */
+#define ADC_CR2_JSWSTART ADC_CR2_JSWSTART_Msk /*!< ADC group injected conversion start */
+#define ADC_CR2_SWSTART_Pos (22U)
+#define ADC_CR2_SWSTART_Msk (0x1U << ADC_CR2_SWSTART_Pos) /*!< 0x00400000 */
+#define ADC_CR2_SWSTART ADC_CR2_SWSTART_Msk /*!< ADC group regular conversion start */
+#define ADC_CR2_TSVREFE_Pos (23U)
+#define ADC_CR2_TSVREFE_Msk (0x1U << ADC_CR2_TSVREFE_Pos) /*!< 0x00800000 */
+#define ADC_CR2_TSVREFE ADC_CR2_TSVREFE_Msk /*!< ADC internal path to VrefInt and temperature sensor enable */
+
+/****************** Bit definition for ADC_SMPR1 register *******************/
+#define ADC_SMPR1_SMP10_Pos (0U)
+#define ADC_SMPR1_SMP10_Msk (0x7U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000007 */
+#define ADC_SMPR1_SMP10 ADC_SMPR1_SMP10_Msk /*!< ADC channel 10 sampling time selection */
+#define ADC_SMPR1_SMP10_0 (0x1U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000001 */
+#define ADC_SMPR1_SMP10_1 (0x2U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000002 */
+#define ADC_SMPR1_SMP10_2 (0x4U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000004 */
+
+#define ADC_SMPR1_SMP11_Pos (3U)
+#define ADC_SMPR1_SMP11_Msk (0x7U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000038 */
+#define ADC_SMPR1_SMP11 ADC_SMPR1_SMP11_Msk /*!< ADC channel 11 sampling time selection */
+#define ADC_SMPR1_SMP11_0 (0x1U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000008 */
+#define ADC_SMPR1_SMP11_1 (0x2U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000010 */
+#define ADC_SMPR1_SMP11_2 (0x4U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000020 */
+
+#define ADC_SMPR1_SMP12_Pos (6U)
+#define ADC_SMPR1_SMP12_Msk (0x7U << ADC_SMPR1_SMP12_Pos) /*!< 0x000001C0 */
+#define ADC_SMPR1_SMP12 ADC_SMPR1_SMP12_Msk /*!< ADC channel 12 sampling time selection */
+#define ADC_SMPR1_SMP12_0 (0x1U << ADC_SMPR1_SMP12_Pos) /*!< 0x00000040 */
+#define ADC_SMPR1_SMP12_1 (0x2U << ADC_SMPR1_SMP12_Pos) /*!< 0x00000080 */
+#define ADC_SMPR1_SMP12_2 (0x4U << ADC_SMPR1_SMP12_Pos) /*!< 0x00000100 */
+
+#define ADC_SMPR1_SMP13_Pos (9U)
+#define ADC_SMPR1_SMP13_Msk (0x7U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000E00 */
+#define ADC_SMPR1_SMP13 ADC_SMPR1_SMP13_Msk /*!< ADC channel 13 sampling time selection */
+#define ADC_SMPR1_SMP13_0 (0x1U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000200 */
+#define ADC_SMPR1_SMP13_1 (0x2U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000400 */
+#define ADC_SMPR1_SMP13_2 (0x4U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000800 */
+
+#define ADC_SMPR1_SMP14_Pos (12U)
+#define ADC_SMPR1_SMP14_Msk (0x7U << ADC_SMPR1_SMP14_Pos) /*!< 0x00007000 */
+#define ADC_SMPR1_SMP14 ADC_SMPR1_SMP14_Msk /*!< ADC channel 14 sampling time selection */
+#define ADC_SMPR1_SMP14_0 (0x1U << ADC_SMPR1_SMP14_Pos) /*!< 0x00001000 */
+#define ADC_SMPR1_SMP14_1 (0x2U << ADC_SMPR1_SMP14_Pos) /*!< 0x00002000 */
+#define ADC_SMPR1_SMP14_2 (0x4U << ADC_SMPR1_SMP14_Pos) /*!< 0x00004000 */
+
+#define ADC_SMPR1_SMP15_Pos (15U)
+#define ADC_SMPR1_SMP15_Msk (0x7U << ADC_SMPR1_SMP15_Pos) /*!< 0x00038000 */
+#define ADC_SMPR1_SMP15 ADC_SMPR1_SMP15_Msk /*!< ADC channel 15 sampling time selection */
+#define ADC_SMPR1_SMP15_0 (0x1U << ADC_SMPR1_SMP15_Pos) /*!< 0x00008000 */
+#define ADC_SMPR1_SMP15_1 (0x2U << ADC_SMPR1_SMP15_Pos) /*!< 0x00010000 */
+#define ADC_SMPR1_SMP15_2 (0x4U << ADC_SMPR1_SMP15_Pos) /*!< 0x00020000 */
+
+#define ADC_SMPR1_SMP16_Pos (18U)
+#define ADC_SMPR1_SMP16_Msk (0x7U << ADC_SMPR1_SMP16_Pos) /*!< 0x001C0000 */
+#define ADC_SMPR1_SMP16 ADC_SMPR1_SMP16_Msk /*!< ADC channel 16 sampling time selection */
+#define ADC_SMPR1_SMP16_0 (0x1U << ADC_SMPR1_SMP16_Pos) /*!< 0x00040000 */
+#define ADC_SMPR1_SMP16_1 (0x2U << ADC_SMPR1_SMP16_Pos) /*!< 0x00080000 */
+#define ADC_SMPR1_SMP16_2 (0x4U << ADC_SMPR1_SMP16_Pos) /*!< 0x00100000 */
+
+#define ADC_SMPR1_SMP17_Pos (21U)
+#define ADC_SMPR1_SMP17_Msk (0x7U << ADC_SMPR1_SMP17_Pos) /*!< 0x00E00000 */
+#define ADC_SMPR1_SMP17 ADC_SMPR1_SMP17_Msk /*!< ADC channel 17 sampling time selection */
+#define ADC_SMPR1_SMP17_0 (0x1U << ADC_SMPR1_SMP17_Pos) /*!< 0x00200000 */
+#define ADC_SMPR1_SMP17_1 (0x2U << ADC_SMPR1_SMP17_Pos) /*!< 0x00400000 */
+#define ADC_SMPR1_SMP17_2 (0x4U << ADC_SMPR1_SMP17_Pos) /*!< 0x00800000 */
+
+/****************** Bit definition for ADC_SMPR2 register *******************/
+#define ADC_SMPR2_SMP0_Pos (0U)
+#define ADC_SMPR2_SMP0_Msk (0x7U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000007 */
+#define ADC_SMPR2_SMP0 ADC_SMPR2_SMP0_Msk /*!< ADC channel 0 sampling time selection */
+#define ADC_SMPR2_SMP0_0 (0x1U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000001 */
+#define ADC_SMPR2_SMP0_1 (0x2U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000002 */
+#define ADC_SMPR2_SMP0_2 (0x4U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000004 */
+
+#define ADC_SMPR2_SMP1_Pos (3U)
+#define ADC_SMPR2_SMP1_Msk (0x7U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000038 */
+#define ADC_SMPR2_SMP1 ADC_SMPR2_SMP1_Msk /*!< ADC channel 1 sampling time selection */
+#define ADC_SMPR2_SMP1_0 (0x1U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000008 */
+#define ADC_SMPR2_SMP1_1 (0x2U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000010 */
+#define ADC_SMPR2_SMP1_2 (0x4U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000020 */
+
+#define ADC_SMPR2_SMP2_Pos (6U)
+#define ADC_SMPR2_SMP2_Msk (0x7U << ADC_SMPR2_SMP2_Pos) /*!< 0x000001C0 */
+#define ADC_SMPR2_SMP2 ADC_SMPR2_SMP2_Msk /*!< ADC channel 2 sampling time selection */
+#define ADC_SMPR2_SMP2_0 (0x1U << ADC_SMPR2_SMP2_Pos) /*!< 0x00000040 */
+#define ADC_SMPR2_SMP2_1 (0x2U << ADC_SMPR2_SMP2_Pos) /*!< 0x00000080 */
+#define ADC_SMPR2_SMP2_2 (0x4U << ADC_SMPR2_SMP2_Pos) /*!< 0x00000100 */
+
+#define ADC_SMPR2_SMP3_Pos (9U)
+#define ADC_SMPR2_SMP3_Msk (0x7U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000E00 */
+#define ADC_SMPR2_SMP3 ADC_SMPR2_SMP3_Msk /*!< ADC channel 3 sampling time selection */
+#define ADC_SMPR2_SMP3_0 (0x1U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000200 */
+#define ADC_SMPR2_SMP3_1 (0x2U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000400 */
+#define ADC_SMPR2_SMP3_2 (0x4U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000800 */
+
+#define ADC_SMPR2_SMP4_Pos (12U)
+#define ADC_SMPR2_SMP4_Msk (0x7U << ADC_SMPR2_SMP4_Pos) /*!< 0x00007000 */
+#define ADC_SMPR2_SMP4 ADC_SMPR2_SMP4_Msk /*!< ADC channel 4 sampling time selection */
+#define ADC_SMPR2_SMP4_0 (0x1U << ADC_SMPR2_SMP4_Pos) /*!< 0x00001000 */
+#define ADC_SMPR2_SMP4_1 (0x2U << ADC_SMPR2_SMP4_Pos) /*!< 0x00002000 */
+#define ADC_SMPR2_SMP4_2 (0x4U << ADC_SMPR2_SMP4_Pos) /*!< 0x00004000 */
+
+#define ADC_SMPR2_SMP5_Pos (15U)
+#define ADC_SMPR2_SMP5_Msk (0x7U << ADC_SMPR2_SMP5_Pos) /*!< 0x00038000 */
+#define ADC_SMPR2_SMP5 ADC_SMPR2_SMP5_Msk /*!< ADC channel 5 sampling time selection */
+#define ADC_SMPR2_SMP5_0 (0x1U << ADC_SMPR2_SMP5_Pos) /*!< 0x00008000 */
+#define ADC_SMPR2_SMP5_1 (0x2U << ADC_SMPR2_SMP5_Pos) /*!< 0x00010000 */
+#define ADC_SMPR2_SMP5_2 (0x4U << ADC_SMPR2_SMP5_Pos) /*!< 0x00020000 */
+
+#define ADC_SMPR2_SMP6_Pos (18U)
+#define ADC_SMPR2_SMP6_Msk (0x7U << ADC_SMPR2_SMP6_Pos) /*!< 0x001C0000 */
+#define ADC_SMPR2_SMP6 ADC_SMPR2_SMP6_Msk /*!< ADC channel 6 sampling time selection */
+#define ADC_SMPR2_SMP6_0 (0x1U << ADC_SMPR2_SMP6_Pos) /*!< 0x00040000 */
+#define ADC_SMPR2_SMP6_1 (0x2U << ADC_SMPR2_SMP6_Pos) /*!< 0x00080000 */
+#define ADC_SMPR2_SMP6_2 (0x4U << ADC_SMPR2_SMP6_Pos) /*!< 0x00100000 */
+
+#define ADC_SMPR2_SMP7_Pos (21U)
+#define ADC_SMPR2_SMP7_Msk (0x7U << ADC_SMPR2_SMP7_Pos) /*!< 0x00E00000 */
+#define ADC_SMPR2_SMP7 ADC_SMPR2_SMP7_Msk /*!< ADC channel 7 sampling time selection */
+#define ADC_SMPR2_SMP7_0 (0x1U << ADC_SMPR2_SMP7_Pos) /*!< 0x00200000 */
+#define ADC_SMPR2_SMP7_1 (0x2U << ADC_SMPR2_SMP7_Pos) /*!< 0x00400000 */
+#define ADC_SMPR2_SMP7_2 (0x4U << ADC_SMPR2_SMP7_Pos) /*!< 0x00800000 */
+
+#define ADC_SMPR2_SMP8_Pos (24U)
+#define ADC_SMPR2_SMP8_Msk (0x7U << ADC_SMPR2_SMP8_Pos) /*!< 0x07000000 */
+#define ADC_SMPR2_SMP8 ADC_SMPR2_SMP8_Msk /*!< ADC channel 8 sampling time selection */
+#define ADC_SMPR2_SMP8_0 (0x1U << ADC_SMPR2_SMP8_Pos) /*!< 0x01000000 */
+#define ADC_SMPR2_SMP8_1 (0x2U << ADC_SMPR2_SMP8_Pos) /*!< 0x02000000 */
+#define ADC_SMPR2_SMP8_2 (0x4U << ADC_SMPR2_SMP8_Pos) /*!< 0x04000000 */
+
+#define ADC_SMPR2_SMP9_Pos (27U)
+#define ADC_SMPR2_SMP9_Msk (0x7U << ADC_SMPR2_SMP9_Pos) /*!< 0x38000000 */
+#define ADC_SMPR2_SMP9 ADC_SMPR2_SMP9_Msk /*!< ADC channel 9 sampling time selection */
+#define ADC_SMPR2_SMP9_0 (0x1U << ADC_SMPR2_SMP9_Pos) /*!< 0x08000000 */
+#define ADC_SMPR2_SMP9_1 (0x2U << ADC_SMPR2_SMP9_Pos) /*!< 0x10000000 */
+#define ADC_SMPR2_SMP9_2 (0x4U << ADC_SMPR2_SMP9_Pos) /*!< 0x20000000 */
+
+/****************** Bit definition for ADC_JOFR1 register *******************/
+#define ADC_JOFR1_JOFFSET1_Pos (0U)
+#define ADC_JOFR1_JOFFSET1_Msk (0xFFFU << ADC_JOFR1_JOFFSET1_Pos) /*!< 0x00000FFF */
+#define ADC_JOFR1_JOFFSET1 ADC_JOFR1_JOFFSET1_Msk /*!< ADC group injected sequencer rank 1 offset value */
+
+/****************** Bit definition for ADC_JOFR2 register *******************/
+#define ADC_JOFR2_JOFFSET2_Pos (0U)
+#define ADC_JOFR2_JOFFSET2_Msk (0xFFFU << ADC_JOFR2_JOFFSET2_Pos) /*!< 0x00000FFF */
+#define ADC_JOFR2_JOFFSET2 ADC_JOFR2_JOFFSET2_Msk /*!< ADC group injected sequencer rank 2 offset value */
+
+/****************** Bit definition for ADC_JOFR3 register *******************/
+#define ADC_JOFR3_JOFFSET3_Pos (0U)
+#define ADC_JOFR3_JOFFSET3_Msk (0xFFFU << ADC_JOFR3_JOFFSET3_Pos) /*!< 0x00000FFF */
+#define ADC_JOFR3_JOFFSET3 ADC_JOFR3_JOFFSET3_Msk /*!< ADC group injected sequencer rank 3 offset value */
+
+/****************** Bit definition for ADC_JOFR4 register *******************/
+#define ADC_JOFR4_JOFFSET4_Pos (0U)
+#define ADC_JOFR4_JOFFSET4_Msk (0xFFFU << ADC_JOFR4_JOFFSET4_Pos) /*!< 0x00000FFF */
+#define ADC_JOFR4_JOFFSET4 ADC_JOFR4_JOFFSET4_Msk /*!< ADC group injected sequencer rank 4 offset value */
+
+/******************* Bit definition for ADC_HTR register ********************/
+#define ADC_HTR_HT_Pos (0U)
+#define ADC_HTR_HT_Msk (0xFFFU << ADC_HTR_HT_Pos) /*!< 0x00000FFF */
+#define ADC_HTR_HT ADC_HTR_HT_Msk /*!< ADC analog watchdog 1 threshold high */
+
+/******************* Bit definition for ADC_LTR register ********************/
+#define ADC_LTR_LT_Pos (0U)
+#define ADC_LTR_LT_Msk (0xFFFU << ADC_LTR_LT_Pos) /*!< 0x00000FFF */
+#define ADC_LTR_LT ADC_LTR_LT_Msk /*!< ADC analog watchdog 1 threshold low */
+
+/******************* Bit definition for ADC_SQR1 register *******************/
+#define ADC_SQR1_SQ13_Pos (0U)
+#define ADC_SQR1_SQ13_Msk (0x1FU << ADC_SQR1_SQ13_Pos) /*!< 0x0000001F */
+#define ADC_SQR1_SQ13 ADC_SQR1_SQ13_Msk /*!< ADC group regular sequencer rank 13 */
+#define ADC_SQR1_SQ13_0 (0x01U << ADC_SQR1_SQ13_Pos) /*!< 0x00000001 */
+#define ADC_SQR1_SQ13_1 (0x02U << ADC_SQR1_SQ13_Pos) /*!< 0x00000002 */
+#define ADC_SQR1_SQ13_2 (0x04U << ADC_SQR1_SQ13_Pos) /*!< 0x00000004 */
+#define ADC_SQR1_SQ13_3 (0x08U << ADC_SQR1_SQ13_Pos) /*!< 0x00000008 */
+#define ADC_SQR1_SQ13_4 (0x10U << ADC_SQR1_SQ13_Pos) /*!< 0x00000010 */
+
+#define ADC_SQR1_SQ14_Pos (5U)
+#define ADC_SQR1_SQ14_Msk (0x1FU << ADC_SQR1_SQ14_Pos) /*!< 0x000003E0 */
+#define ADC_SQR1_SQ14 ADC_SQR1_SQ14_Msk /*!< ADC group regular sequencer rank 14 */
+#define ADC_SQR1_SQ14_0 (0x01U << ADC_SQR1_SQ14_Pos) /*!< 0x00000020 */
+#define ADC_SQR1_SQ14_1 (0x02U << ADC_SQR1_SQ14_Pos) /*!< 0x00000040 */
+#define ADC_SQR1_SQ14_2 (0x04U << ADC_SQR1_SQ14_Pos) /*!< 0x00000080 */
+#define ADC_SQR1_SQ14_3 (0x08U << ADC_SQR1_SQ14_Pos) /*!< 0x00000100 */
+#define ADC_SQR1_SQ14_4 (0x10U << ADC_SQR1_SQ14_Pos) /*!< 0x00000200 */
+
+#define ADC_SQR1_SQ15_Pos (10U)
+#define ADC_SQR1_SQ15_Msk (0x1FU << ADC_SQR1_SQ15_Pos) /*!< 0x00007C00 */
+#define ADC_SQR1_SQ15 ADC_SQR1_SQ15_Msk /*!< ADC group regular sequencer rank 15 */
+#define ADC_SQR1_SQ15_0 (0x01U << ADC_SQR1_SQ15_Pos) /*!< 0x00000400 */
+#define ADC_SQR1_SQ15_1 (0x02U << ADC_SQR1_SQ15_Pos) /*!< 0x00000800 */
+#define ADC_SQR1_SQ15_2 (0x04U << ADC_SQR1_SQ15_Pos) /*!< 0x00001000 */
+#define ADC_SQR1_SQ15_3 (0x08U << ADC_SQR1_SQ15_Pos) /*!< 0x00002000 */
+#define ADC_SQR1_SQ15_4 (0x10U << ADC_SQR1_SQ15_Pos) /*!< 0x00004000 */
+
+#define ADC_SQR1_SQ16_Pos (15U)
+#define ADC_SQR1_SQ16_Msk (0x1FU << ADC_SQR1_SQ16_Pos) /*!< 0x000F8000 */
+#define ADC_SQR1_SQ16 ADC_SQR1_SQ16_Msk /*!< ADC group regular sequencer rank 16 */
+#define ADC_SQR1_SQ16_0 (0x01U << ADC_SQR1_SQ16_Pos) /*!< 0x00008000 */
+#define ADC_SQR1_SQ16_1 (0x02U << ADC_SQR1_SQ16_Pos) /*!< 0x00010000 */
+#define ADC_SQR1_SQ16_2 (0x04U << ADC_SQR1_SQ16_Pos) /*!< 0x00020000 */
+#define ADC_SQR1_SQ16_3 (0x08U << ADC_SQR1_SQ16_Pos) /*!< 0x00040000 */
+#define ADC_SQR1_SQ16_4 (0x10U << ADC_SQR1_SQ16_Pos) /*!< 0x00080000 */
+
+#define ADC_SQR1_L_Pos (20U)
+#define ADC_SQR1_L_Msk (0xFU << ADC_SQR1_L_Pos) /*!< 0x00F00000 */
+#define ADC_SQR1_L ADC_SQR1_L_Msk /*!< ADC group regular sequencer scan length */
+#define ADC_SQR1_L_0 (0x1U << ADC_SQR1_L_Pos) /*!< 0x00100000 */
+#define ADC_SQR1_L_1 (0x2U << ADC_SQR1_L_Pos) /*!< 0x00200000 */
+#define ADC_SQR1_L_2 (0x4U << ADC_SQR1_L_Pos) /*!< 0x00400000 */
+#define ADC_SQR1_L_3 (0x8U << ADC_SQR1_L_Pos) /*!< 0x00800000 */
+
+/******************* Bit definition for ADC_SQR2 register *******************/
+#define ADC_SQR2_SQ7_Pos (0U)
+#define ADC_SQR2_SQ7_Msk (0x1FU << ADC_SQR2_SQ7_Pos) /*!< 0x0000001F */
+#define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk /*!< ADC group regular sequencer rank 7 */
+#define ADC_SQR2_SQ7_0 (0x01U << ADC_SQR2_SQ7_Pos) /*!< 0x00000001 */
+#define ADC_SQR2_SQ7_1 (0x02U << ADC_SQR2_SQ7_Pos) /*!< 0x00000002 */
+#define ADC_SQR2_SQ7_2 (0x04U << ADC_SQR2_SQ7_Pos) /*!< 0x00000004 */
+#define ADC_SQR2_SQ7_3 (0x08U << ADC_SQR2_SQ7_Pos) /*!< 0x00000008 */
+#define ADC_SQR2_SQ7_4 (0x10U << ADC_SQR2_SQ7_Pos) /*!< 0x00000010 */
+
+#define ADC_SQR2_SQ8_Pos (5U)
+#define ADC_SQR2_SQ8_Msk (0x1FU << ADC_SQR2_SQ8_Pos) /*!< 0x000003E0 */
+#define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk /*!< ADC group regular sequencer rank 8 */
+#define ADC_SQR2_SQ8_0 (0x01U << ADC_SQR2_SQ8_Pos) /*!< 0x00000020 */
+#define ADC_SQR2_SQ8_1 (0x02U << ADC_SQR2_SQ8_Pos) /*!< 0x00000040 */
+#define ADC_SQR2_SQ8_2 (0x04U << ADC_SQR2_SQ8_Pos) /*!< 0x00000080 */
+#define ADC_SQR2_SQ8_3 (0x08U << ADC_SQR2_SQ8_Pos) /*!< 0x00000100 */
+#define ADC_SQR2_SQ8_4 (0x10U << ADC_SQR2_SQ8_Pos) /*!< 0x00000200 */
+
+#define ADC_SQR2_SQ9_Pos (10U)
+#define ADC_SQR2_SQ9_Msk (0x1FU << ADC_SQR2_SQ9_Pos) /*!< 0x00007C00 */
+#define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk /*!< ADC group regular sequencer rank 9 */
+#define ADC_SQR2_SQ9_0 (0x01U << ADC_SQR2_SQ9_Pos) /*!< 0x00000400 */
+#define ADC_SQR2_SQ9_1 (0x02U << ADC_SQR2_SQ9_Pos) /*!< 0x00000800 */
+#define ADC_SQR2_SQ9_2 (0x04U << ADC_SQR2_SQ9_Pos) /*!< 0x00001000 */
+#define ADC_SQR2_SQ9_3 (0x08U << ADC_SQR2_SQ9_Pos) /*!< 0x00002000 */
+#define ADC_SQR2_SQ9_4 (0x10U << ADC_SQR2_SQ9_Pos) /*!< 0x00004000 */
+
+#define ADC_SQR2_SQ10_Pos (15U)
+#define ADC_SQR2_SQ10_Msk (0x1FU << ADC_SQR2_SQ10_Pos) /*!< 0x000F8000 */
+#define ADC_SQR2_SQ10 ADC_SQR2_SQ10_Msk /*!< ADC group regular sequencer rank 10 */
+#define ADC_SQR2_SQ10_0 (0x01U << ADC_SQR2_SQ10_Pos) /*!< 0x00008000 */
+#define ADC_SQR2_SQ10_1 (0x02U << ADC_SQR2_SQ10_Pos) /*!< 0x00010000 */
+#define ADC_SQR2_SQ10_2 (0x04U << ADC_SQR2_SQ10_Pos) /*!< 0x00020000 */
+#define ADC_SQR2_SQ10_3 (0x08U << ADC_SQR2_SQ10_Pos) /*!< 0x00040000 */
+#define ADC_SQR2_SQ10_4 (0x10U << ADC_SQR2_SQ10_Pos) /*!< 0x00080000 */
+
+#define ADC_SQR2_SQ11_Pos (20U)
+#define ADC_SQR2_SQ11_Msk (0x1FU << ADC_SQR2_SQ11_Pos) /*!< 0x01F00000 */
+#define ADC_SQR2_SQ11 ADC_SQR2_SQ11_Msk /*!< ADC group regular sequencer rank 1 */
+#define ADC_SQR2_SQ11_0 (0x01U << ADC_SQR2_SQ11_Pos) /*!< 0x00100000 */
+#define ADC_SQR2_SQ11_1 (0x02U << ADC_SQR2_SQ11_Pos) /*!< 0x00200000 */
+#define ADC_SQR2_SQ11_2 (0x04U << ADC_SQR2_SQ11_Pos) /*!< 0x00400000 */
+#define ADC_SQR2_SQ11_3 (0x08U << ADC_SQR2_SQ11_Pos) /*!< 0x00800000 */
+#define ADC_SQR2_SQ11_4 (0x10U << ADC_SQR2_SQ11_Pos) /*!< 0x01000000 */
+
+#define ADC_SQR2_SQ12_Pos (25U)
+#define ADC_SQR2_SQ12_Msk (0x1FU << ADC_SQR2_SQ12_Pos) /*!< 0x3E000000 */
+#define ADC_SQR2_SQ12 ADC_SQR2_SQ12_Msk /*!< ADC group regular sequencer rank 12 */
+#define ADC_SQR2_SQ12_0 (0x01U << ADC_SQR2_SQ12_Pos) /*!< 0x02000000 */
+#define ADC_SQR2_SQ12_1 (0x02U << ADC_SQR2_SQ12_Pos) /*!< 0x04000000 */
+#define ADC_SQR2_SQ12_2 (0x04U << ADC_SQR2_SQ12_Pos) /*!< 0x08000000 */
+#define ADC_SQR2_SQ12_3 (0x08U << ADC_SQR2_SQ12_Pos) /*!< 0x10000000 */
+#define ADC_SQR2_SQ12_4 (0x10U << ADC_SQR2_SQ12_Pos) /*!< 0x20000000 */
+
+/******************* Bit definition for ADC_SQR3 register *******************/
+#define ADC_SQR3_SQ1_Pos (0U)
+#define ADC_SQR3_SQ1_Msk (0x1FU << ADC_SQR3_SQ1_Pos) /*!< 0x0000001F */
+#define ADC_SQR3_SQ1 ADC_SQR3_SQ1_Msk /*!< ADC group regular sequencer rank 1 */
+#define ADC_SQR3_SQ1_0 (0x01U << ADC_SQR3_SQ1_Pos) /*!< 0x00000001 */
+#define ADC_SQR3_SQ1_1 (0x02U << ADC_SQR3_SQ1_Pos) /*!< 0x00000002 */
+#define ADC_SQR3_SQ1_2 (0x04U << ADC_SQR3_SQ1_Pos) /*!< 0x00000004 */
+#define ADC_SQR3_SQ1_3 (0x08U << ADC_SQR3_SQ1_Pos) /*!< 0x00000008 */
+#define ADC_SQR3_SQ1_4 (0x10U << ADC_SQR3_SQ1_Pos) /*!< 0x00000010 */
+
+#define ADC_SQR3_SQ2_Pos (5U)
+#define ADC_SQR3_SQ2_Msk (0x1FU << ADC_SQR3_SQ2_Pos) /*!< 0x000003E0 */
+#define ADC_SQR3_SQ2 ADC_SQR3_SQ2_Msk /*!< ADC group regular sequencer rank 2 */
+#define ADC_SQR3_SQ2_0 (0x01U << ADC_SQR3_SQ2_Pos) /*!< 0x00000020 */
+#define ADC_SQR3_SQ2_1 (0x02U << ADC_SQR3_SQ2_Pos) /*!< 0x00000040 */
+#define ADC_SQR3_SQ2_2 (0x04U << ADC_SQR3_SQ2_Pos) /*!< 0x00000080 */
+#define ADC_SQR3_SQ2_3 (0x08U << ADC_SQR3_SQ2_Pos) /*!< 0x00000100 */
+#define ADC_SQR3_SQ2_4 (0x10U << ADC_SQR3_SQ2_Pos) /*!< 0x00000200 */
+
+#define ADC_SQR3_SQ3_Pos (10U)
+#define ADC_SQR3_SQ3_Msk (0x1FU << ADC_SQR3_SQ3_Pos) /*!< 0x00007C00 */
+#define ADC_SQR3_SQ3 ADC_SQR3_SQ3_Msk /*!< ADC group regular sequencer rank 3 */
+#define ADC_SQR3_SQ3_0 (0x01U << ADC_SQR3_SQ3_Pos) /*!< 0x00000400 */
+#define ADC_SQR3_SQ3_1 (0x02U << ADC_SQR3_SQ3_Pos) /*!< 0x00000800 */
+#define ADC_SQR3_SQ3_2 (0x04U << ADC_SQR3_SQ3_Pos) /*!< 0x00001000 */
+#define ADC_SQR3_SQ3_3 (0x08U << ADC_SQR3_SQ3_Pos) /*!< 0x00002000 */
+#define ADC_SQR3_SQ3_4 (0x10U << ADC_SQR3_SQ3_Pos) /*!< 0x00004000 */
+
+#define ADC_SQR3_SQ4_Pos (15U)
+#define ADC_SQR3_SQ4_Msk (0x1FU << ADC_SQR3_SQ4_Pos) /*!< 0x000F8000 */
+#define ADC_SQR3_SQ4 ADC_SQR3_SQ4_Msk /*!< ADC group regular sequencer rank 4 */
+#define ADC_SQR3_SQ4_0 (0x01U << ADC_SQR3_SQ4_Pos) /*!< 0x00008000 */
+#define ADC_SQR3_SQ4_1 (0x02U << ADC_SQR3_SQ4_Pos) /*!< 0x00010000 */
+#define ADC_SQR3_SQ4_2 (0x04U << ADC_SQR3_SQ4_Pos) /*!< 0x00020000 */
+#define ADC_SQR3_SQ4_3 (0x08U << ADC_SQR3_SQ4_Pos) /*!< 0x00040000 */
+#define ADC_SQR3_SQ4_4 (0x10U << ADC_SQR3_SQ4_Pos) /*!< 0x00080000 */
+
+#define ADC_SQR3_SQ5_Pos (20U)
+#define ADC_SQR3_SQ5_Msk (0x1FU << ADC_SQR3_SQ5_Pos) /*!< 0x01F00000 */
+#define ADC_SQR3_SQ5 ADC_SQR3_SQ5_Msk /*!< ADC group regular sequencer rank 5 */
+#define ADC_SQR3_SQ5_0 (0x01U << ADC_SQR3_SQ5_Pos) /*!< 0x00100000 */
+#define ADC_SQR3_SQ5_1 (0x02U << ADC_SQR3_SQ5_Pos) /*!< 0x00200000 */
+#define ADC_SQR3_SQ5_2 (0x04U << ADC_SQR3_SQ5_Pos) /*!< 0x00400000 */
+#define ADC_SQR3_SQ5_3 (0x08U << ADC_SQR3_SQ5_Pos) /*!< 0x00800000 */
+#define ADC_SQR3_SQ5_4 (0x10U << ADC_SQR3_SQ5_Pos) /*!< 0x01000000 */
+
+#define ADC_SQR3_SQ6_Pos (25U)
+#define ADC_SQR3_SQ6_Msk (0x1FU << ADC_SQR3_SQ6_Pos) /*!< 0x3E000000 */
+#define ADC_SQR3_SQ6 ADC_SQR3_SQ6_Msk /*!< ADC group regular sequencer rank 6 */
+#define ADC_SQR3_SQ6_0 (0x01U << ADC_SQR3_SQ6_Pos) /*!< 0x02000000 */
+#define ADC_SQR3_SQ6_1 (0x02U << ADC_SQR3_SQ6_Pos) /*!< 0x04000000 */
+#define ADC_SQR3_SQ6_2 (0x04U << ADC_SQR3_SQ6_Pos) /*!< 0x08000000 */
+#define ADC_SQR3_SQ6_3 (0x08U << ADC_SQR3_SQ6_Pos) /*!< 0x10000000 */
+#define ADC_SQR3_SQ6_4 (0x10U << ADC_SQR3_SQ6_Pos) /*!< 0x20000000 */
+
+/******************* Bit definition for ADC_JSQR register *******************/
+#define ADC_JSQR_JSQ1_Pos (0U)
+#define ADC_JSQR_JSQ1_Msk (0x1FU << ADC_JSQR_JSQ1_Pos) /*!< 0x0000001F */
+#define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!< ADC group injected sequencer rank 1 */
+#define ADC_JSQR_JSQ1_0 (0x01U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000001 */
+#define ADC_JSQR_JSQ1_1 (0x02U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000002 */
+#define ADC_JSQR_JSQ1_2 (0x04U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000004 */
+#define ADC_JSQR_JSQ1_3 (0x08U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000008 */
+#define ADC_JSQR_JSQ1_4 (0x10U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000010 */
+
+#define ADC_JSQR_JSQ2_Pos (5U)
+#define ADC_JSQR_JSQ2_Msk (0x1FU << ADC_JSQR_JSQ2_Pos) /*!< 0x000003E0 */
+#define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!< ADC group injected sequencer rank 2 */
+#define ADC_JSQR_JSQ2_0 (0x01U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000020 */
+#define ADC_JSQR_JSQ2_1 (0x02U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000040 */
+#define ADC_JSQR_JSQ2_2 (0x04U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000080 */
+#define ADC_JSQR_JSQ2_3 (0x08U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000100 */
+#define ADC_JSQR_JSQ2_4 (0x10U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000200 */
+
+#define ADC_JSQR_JSQ3_Pos (10U)
+#define ADC_JSQR_JSQ3_Msk (0x1FU << ADC_JSQR_JSQ3_Pos) /*!< 0x00007C00 */
+#define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!< ADC group injected sequencer rank 3 */
+#define ADC_JSQR_JSQ3_0 (0x01U << ADC_JSQR_JSQ3_Pos) /*!< 0x00000400 */
+#define ADC_JSQR_JSQ3_1 (0x02U << ADC_JSQR_JSQ3_Pos) /*!< 0x00000800 */
+#define ADC_JSQR_JSQ3_2 (0x04U << ADC_JSQR_JSQ3_Pos) /*!< 0x00001000 */
+#define ADC_JSQR_JSQ3_3 (0x08U << ADC_JSQR_JSQ3_Pos) /*!< 0x00002000 */
+#define ADC_JSQR_JSQ3_4 (0x10U << ADC_JSQR_JSQ3_Pos) /*!< 0x00004000 */
+
+#define ADC_JSQR_JSQ4_Pos (15U)
+#define ADC_JSQR_JSQ4_Msk (0x1FU << ADC_JSQR_JSQ4_Pos) /*!< 0x000F8000 */
+#define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!< ADC group injected sequencer rank 4 */
+#define ADC_JSQR_JSQ4_0 (0x01U << ADC_JSQR_JSQ4_Pos) /*!< 0x00008000 */
+#define ADC_JSQR_JSQ4_1 (0x02U << ADC_JSQR_JSQ4_Pos) /*!< 0x00010000 */
+#define ADC_JSQR_JSQ4_2 (0x04U << ADC_JSQR_JSQ4_Pos) /*!< 0x00020000 */
+#define ADC_JSQR_JSQ4_3 (0x08U << ADC_JSQR_JSQ4_Pos) /*!< 0x00040000 */
+#define ADC_JSQR_JSQ4_4 (0x10U << ADC_JSQR_JSQ4_Pos) /*!< 0x00080000 */
+
+#define ADC_JSQR_JL_Pos (20U)
+#define ADC_JSQR_JL_Msk (0x3U << ADC_JSQR_JL_Pos) /*!< 0x00300000 */
+#define ADC_JSQR_JL ADC_JSQR_JL_Msk /*!< ADC group injected sequencer scan length */
+#define ADC_JSQR_JL_0 (0x1U << ADC_JSQR_JL_Pos) /*!< 0x00100000 */
+#define ADC_JSQR_JL_1 (0x2U << ADC_JSQR_JL_Pos) /*!< 0x00200000 */
+
+/******************* Bit definition for ADC_JDR1 register *******************/
+#define ADC_JDR1_JDATA_Pos (0U)
+#define ADC_JDR1_JDATA_Msk (0xFFFFU << ADC_JDR1_JDATA_Pos) /*!< 0x0000FFFF */
+#define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!< ADC group injected sequencer rank 1 conversion data */
+
+/******************* Bit definition for ADC_JDR2 register *******************/
+#define ADC_JDR2_JDATA_Pos (0U)
+#define ADC_JDR2_JDATA_Msk (0xFFFFU << ADC_JDR2_JDATA_Pos) /*!< 0x0000FFFF */
+#define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!< ADC group injected sequencer rank 2 conversion data */
+
+/******************* Bit definition for ADC_JDR3 register *******************/
+#define ADC_JDR3_JDATA_Pos (0U)
+#define ADC_JDR3_JDATA_Msk (0xFFFFU << ADC_JDR3_JDATA_Pos) /*!< 0x0000FFFF */
+#define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!< ADC group injected sequencer rank 3 conversion data */
+
+/******************* Bit definition for ADC_JDR4 register *******************/
+#define ADC_JDR4_JDATA_Pos (0U)
+#define ADC_JDR4_JDATA_Msk (0xFFFFU << ADC_JDR4_JDATA_Pos) /*!< 0x0000FFFF */
+#define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!< ADC group injected sequencer rank 4 conversion data */
+
+/******************** Bit definition for ADC_DR register ********************/
+#define ADC_DR_DATA_Pos (0U)
+#define ADC_DR_DATA_Msk (0xFFFFU << ADC_DR_DATA_Pos) /*!< 0x0000FFFF */
+#define ADC_DR_DATA ADC_DR_DATA_Msk /*!< ADC group regular conversion data */
+/******************************************************************************/
+/* */
+/* Digital to Analog Converter */
+/* */
+/******************************************************************************/
+
+/******************** Bit definition for DAC_CR register ********************/
+#define DAC_CR_EN1_Pos (0U)
+#define DAC_CR_EN1_Msk (0x1U << DAC_CR_EN1_Pos) /*!< 0x00000001 */
+#define DAC_CR_EN1 DAC_CR_EN1_Msk /*!< DAC channel1 enable */
+#define DAC_CR_BOFF1_Pos (1U)
+#define DAC_CR_BOFF1_Msk (0x1U << DAC_CR_BOFF1_Pos) /*!< 0x00000002 */
+#define DAC_CR_BOFF1 DAC_CR_BOFF1_Msk /*!< DAC channel1 output buffer disable */
+#define DAC_CR_TEN1_Pos (2U)
+#define DAC_CR_TEN1_Msk (0x1U << DAC_CR_TEN1_Pos) /*!< 0x00000004 */
+#define DAC_CR_TEN1 DAC_CR_TEN1_Msk /*!< DAC channel1 Trigger enable */
+
+#define DAC_CR_TSEL1_Pos (3U)
+#define DAC_CR_TSEL1_Msk (0x7U << DAC_CR_TSEL1_Pos) /*!< 0x00000038 */
+#define DAC_CR_TSEL1 DAC_CR_TSEL1_Msk /*!< TSEL1[2:0] (DAC channel1 Trigger selection) */
+#define DAC_CR_TSEL1_0 (0x1U << DAC_CR_TSEL1_Pos) /*!< 0x00000008 */
+#define DAC_CR_TSEL1_1 (0x2U << DAC_CR_TSEL1_Pos) /*!< 0x00000010 */
+#define DAC_CR_TSEL1_2 (0x4U << DAC_CR_TSEL1_Pos) /*!< 0x00000020 */
+
+#define DAC_CR_WAVE1_Pos (6U)
+#define DAC_CR_WAVE1_Msk (0x3U << DAC_CR_WAVE1_Pos) /*!< 0x000000C0 */
+#define DAC_CR_WAVE1 DAC_CR_WAVE1_Msk /*!< WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
+#define DAC_CR_WAVE1_0 (0x1U << DAC_CR_WAVE1_Pos) /*!< 0x00000040 */
+#define DAC_CR_WAVE1_1 (0x2U << DAC_CR_WAVE1_Pos) /*!< 0x00000080 */
+
+#define DAC_CR_MAMP1_Pos (8U)
+#define DAC_CR_MAMP1_Msk (0xFU << DAC_CR_MAMP1_Pos) /*!< 0x00000F00 */
+#define DAC_CR_MAMP1 DAC_CR_MAMP1_Msk /*!< MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
+#define DAC_CR_MAMP1_0 (0x1U << DAC_CR_MAMP1_Pos) /*!< 0x00000100 */
+#define DAC_CR_MAMP1_1 (0x2U << DAC_CR_MAMP1_Pos) /*!< 0x00000200 */
+#define DAC_CR_MAMP1_2 (0x4U << DAC_CR_MAMP1_Pos) /*!< 0x00000400 */
+#define DAC_CR_MAMP1_3 (0x8U << DAC_CR_MAMP1_Pos) /*!< 0x00000800 */
+
+#define DAC_CR_DMAEN1_Pos (12U)
+#define DAC_CR_DMAEN1_Msk (0x1U << DAC_CR_DMAEN1_Pos) /*!< 0x00001000 */
+#define DAC_CR_DMAEN1 DAC_CR_DMAEN1_Msk /*!< DAC channel1 DMA enable */
+#define DAC_CR_EN2_Pos (16U)
+#define DAC_CR_EN2_Msk (0x1U << DAC_CR_EN2_Pos) /*!< 0x00010000 */
+#define DAC_CR_EN2 DAC_CR_EN2_Msk /*!< DAC channel2 enable */
+#define DAC_CR_BOFF2_Pos (17U)
+#define DAC_CR_BOFF2_Msk (0x1U << DAC_CR_BOFF2_Pos) /*!< 0x00020000 */
+#define DAC_CR_BOFF2 DAC_CR_BOFF2_Msk /*!< DAC channel2 output buffer disable */
+#define DAC_CR_TEN2_Pos (18U)
+#define DAC_CR_TEN2_Msk (0x1U << DAC_CR_TEN2_Pos) /*!< 0x00040000 */
+#define DAC_CR_TEN2 DAC_CR_TEN2_Msk /*!< DAC channel2 Trigger enable */
+
+#define DAC_CR_TSEL2_Pos (19U)
+#define DAC_CR_TSEL2_Msk (0x7U << DAC_CR_TSEL2_Pos) /*!< 0x00380000 */
+#define DAC_CR_TSEL2 DAC_CR_TSEL2_Msk /*!< TSEL2[2:0] (DAC channel2 Trigger selection) */
+#define DAC_CR_TSEL2_0 (0x1U << DAC_CR_TSEL2_Pos) /*!< 0x00080000 */
+#define DAC_CR_TSEL2_1 (0x2U << DAC_CR_TSEL2_Pos) /*!< 0x00100000 */
+#define DAC_CR_TSEL2_2 (0x4U << DAC_CR_TSEL2_Pos) /*!< 0x00200000 */
+
+#define DAC_CR_WAVE2_Pos (22U)
+#define DAC_CR_WAVE2_Msk (0x3U << DAC_CR_WAVE2_Pos) /*!< 0x00C00000 */
+#define DAC_CR_WAVE2 DAC_CR_WAVE2_Msk /*!< WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
+#define DAC_CR_WAVE2_0 (0x1U << DAC_CR_WAVE2_Pos) /*!< 0x00400000 */
+#define DAC_CR_WAVE2_1 (0x2U << DAC_CR_WAVE2_Pos) /*!< 0x00800000 */
+
+#define DAC_CR_MAMP2_Pos (24U)
+#define DAC_CR_MAMP2_Msk (0xFU << DAC_CR_MAMP2_Pos) /*!< 0x0F000000 */
+#define DAC_CR_MAMP2 DAC_CR_MAMP2_Msk /*!< MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
+#define DAC_CR_MAMP2_0 (0x1U << DAC_CR_MAMP2_Pos) /*!< 0x01000000 */
+#define DAC_CR_MAMP2_1 (0x2U << DAC_CR_MAMP2_Pos) /*!< 0x02000000 */
+#define DAC_CR_MAMP2_2 (0x4U << DAC_CR_MAMP2_Pos) /*!< 0x04000000 */
+#define DAC_CR_MAMP2_3 (0x8U << DAC_CR_MAMP2_Pos) /*!< 0x08000000 */
+
+#define DAC_CR_DMAEN2_Pos (28U)
+#define DAC_CR_DMAEN2_Msk (0x1U << DAC_CR_DMAEN2_Pos) /*!< 0x10000000 */
+#define DAC_CR_DMAEN2 DAC_CR_DMAEN2_Msk /*!< DAC channel2 DMA enabled */
+
+#define DAC_CR_DMAUDRIE1_Pos (13U)
+#define DAC_CR_DMAUDRIE1_Msk (0x1U << DAC_CR_DMAUDRIE1_Pos) /*!< 0x00002000 */
+#define DAC_CR_DMAUDRIE1 DAC_CR_DMAUDRIE1_Msk /*!< DAC channel1 DMA underrun interrupt enable */
+#define DAC_CR_DMAUDRIE2_Pos (29U)
+#define DAC_CR_DMAUDRIE2_Msk (0x1U << DAC_CR_DMAUDRIE2_Pos) /*!< 0x20000000 */
+#define DAC_CR_DMAUDRIE2 DAC_CR_DMAUDRIE2_Msk /*!< DAC channel2 DMA underrun interrupt enable */
+
+/***************** Bit definition for DAC_SWTRIGR register ******************/
+#define DAC_SWTRIGR_SWTRIG1_Pos (0U)
+#define DAC_SWTRIGR_SWTRIG1_Msk (0x1U << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */
+#define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /*!< DAC channel1 software trigger */
+#define DAC_SWTRIGR_SWTRIG2_Pos (1U)
+#define DAC_SWTRIGR_SWTRIG2_Msk (0x1U << DAC_SWTRIGR_SWTRIG2_Pos) /*!< 0x00000002 */
+#define DAC_SWTRIGR_SWTRIG2 DAC_SWTRIGR_SWTRIG2_Msk /*!< DAC channel2 software trigger */
+
+/***************** Bit definition for DAC_DHR12R1 register ******************/
+#define DAC_DHR12R1_DACC1DHR_Pos (0U)
+#define DAC_DHR12R1_DACC1DHR_Msk (0xFFFU << DAC_DHR12R1_DACC1DHR_Pos) /*!< 0x00000FFF */
+#define DAC_DHR12R1_DACC1DHR DAC_DHR12R1_DACC1DHR_Msk /*!< DAC channel1 12-bit Right aligned data */
+
+/***************** Bit definition for DAC_DHR12L1 register ******************/
+#define DAC_DHR12L1_DACC1DHR_Pos (4U)
+#define DAC_DHR12L1_DACC1DHR_Msk (0xFFFU << DAC_DHR12L1_DACC1DHR_Pos) /*!< 0x0000FFF0 */
+#define DAC_DHR12L1_DACC1DHR DAC_DHR12L1_DACC1DHR_Msk /*!< DAC channel1 12-bit Left aligned data */
+
+/****************** Bit definition for DAC_DHR8R1 register ******************/
+#define DAC_DHR8R1_DACC1DHR_Pos (0U)
+#define DAC_DHR8R1_DACC1DHR_Msk (0xFFU << DAC_DHR8R1_DACC1DHR_Pos) /*!< 0x000000FF */
+#define DAC_DHR8R1_DACC1DHR DAC_DHR8R1_DACC1DHR_Msk /*!< DAC channel1 8-bit Right aligned data */
+
+/***************** Bit definition for DAC_DHR12R2 register ******************/
+#define DAC_DHR12R2_DACC2DHR_Pos (0U)
+#define DAC_DHR12R2_DACC2DHR_Msk (0xFFFU << DAC_DHR12R2_DACC2DHR_Pos) /*!< 0x00000FFF */
+#define DAC_DHR12R2_DACC2DHR DAC_DHR12R2_DACC2DHR_Msk /*!< DAC channel2 12-bit Right aligned data */
+
+/***************** Bit definition for DAC_DHR12L2 register ******************/
+#define DAC_DHR12L2_DACC2DHR_Pos (4U)
+#define DAC_DHR12L2_DACC2DHR_Msk (0xFFFU << DAC_DHR12L2_DACC2DHR_Pos) /*!< 0x0000FFF0 */
+#define DAC_DHR12L2_DACC2DHR DAC_DHR12L2_DACC2DHR_Msk /*!< DAC channel2 12-bit Left aligned data */
+
+/****************** Bit definition for DAC_DHR8R2 register ******************/
+#define DAC_DHR8R2_DACC2DHR_Pos (0U)
+#define DAC_DHR8R2_DACC2DHR_Msk (0xFFU << DAC_DHR8R2_DACC2DHR_Pos) /*!< 0x000000FF */
+#define DAC_DHR8R2_DACC2DHR DAC_DHR8R2_DACC2DHR_Msk /*!< DAC channel2 8-bit Right aligned data */
+
+/***************** Bit definition for DAC_DHR12RD register ******************/
+#define DAC_DHR12RD_DACC1DHR_Pos (0U)
+#define DAC_DHR12RD_DACC1DHR_Msk (0xFFFU << DAC_DHR12RD_DACC1DHR_Pos) /*!< 0x00000FFF */
+#define DAC_DHR12RD_DACC1DHR DAC_DHR12RD_DACC1DHR_Msk /*!< DAC channel1 12-bit Right aligned data */
+#define DAC_DHR12RD_DACC2DHR_Pos (16U)
+#define DAC_DHR12RD_DACC2DHR_Msk (0xFFFU << DAC_DHR12RD_DACC2DHR_Pos) /*!< 0x0FFF0000 */
+#define DAC_DHR12RD_DACC2DHR DAC_DHR12RD_DACC2DHR_Msk /*!< DAC channel2 12-bit Right aligned data */
+
+/***************** Bit definition for DAC_DHR12LD register ******************/
+#define DAC_DHR12LD_DACC1DHR_Pos (4U)
+#define DAC_DHR12LD_DACC1DHR_Msk (0xFFFU << DAC_DHR12LD_DACC1DHR_Pos) /*!< 0x0000FFF0 */
+#define DAC_DHR12LD_DACC1DHR DAC_DHR12LD_DACC1DHR_Msk /*!< DAC channel1 12-bit Left aligned data */
+#define DAC_DHR12LD_DACC2DHR_Pos (20U)
+#define DAC_DHR12LD_DACC2DHR_Msk (0xFFFU << DAC_DHR12LD_DACC2DHR_Pos) /*!< 0xFFF00000 */
+#define DAC_DHR12LD_DACC2DHR DAC_DHR12LD_DACC2DHR_Msk /*!< DAC channel2 12-bit Left aligned data */
+
+/****************** Bit definition for DAC_DHR8RD register ******************/
+#define DAC_DHR8RD_DACC1DHR_Pos (0U)
+#define DAC_DHR8RD_DACC1DHR_Msk (0xFFU << DAC_DHR8RD_DACC1DHR_Pos) /*!< 0x000000FF */
+#define DAC_DHR8RD_DACC1DHR DAC_DHR8RD_DACC1DHR_Msk /*!< DAC channel1 8-bit Right aligned data */
+#define DAC_DHR8RD_DACC2DHR_Pos (8U)
+#define DAC_DHR8RD_DACC2DHR_Msk (0xFFU << DAC_DHR8RD_DACC2DHR_Pos) /*!< 0x0000FF00 */
+#define DAC_DHR8RD_DACC2DHR DAC_DHR8RD_DACC2DHR_Msk /*!< DAC channel2 8-bit Right aligned data */
+
+/******************* Bit definition for DAC_DOR1 register *******************/
+#define DAC_DOR1_DACC1DOR_Pos (0U)
+#define DAC_DOR1_DACC1DOR_Msk (0xFFFU << DAC_DOR1_DACC1DOR_Pos) /*!< 0x00000FFF */
+#define DAC_DOR1_DACC1DOR DAC_DOR1_DACC1DOR_Msk /*!< DAC channel1 data output */
+
+/******************* Bit definition for DAC_DOR2 register *******************/
+#define DAC_DOR2_DACC2DOR_Pos (0U)
+#define DAC_DOR2_DACC2DOR_Msk (0xFFFU << DAC_DOR2_DACC2DOR_Pos) /*!< 0x00000FFF */
+#define DAC_DOR2_DACC2DOR DAC_DOR2_DACC2DOR_Msk /*!< DAC channel2 data output */
+
+/******************** Bit definition for DAC_SR register ********************/
+#define DAC_SR_DMAUDR1_Pos (13U)
+#define DAC_SR_DMAUDR1_Msk (0x1U << DAC_SR_DMAUDR1_Pos) /*!< 0x00002000 */
+#define DAC_SR_DMAUDR1 DAC_SR_DMAUDR1_Msk /*!< DAC channel1 DMA underrun flag */
+#define DAC_SR_DMAUDR2_Pos (29U)
+#define DAC_SR_DMAUDR2_Msk (0x1U << DAC_SR_DMAUDR2_Pos) /*!< 0x20000000 */
+#define DAC_SR_DMAUDR2 DAC_SR_DMAUDR2_Msk /*!< DAC channel2 DMA underrun flag */
+
+/******************************************************************************/
+/* */
+/* CEC */
+/* */
+/******************************************************************************/
+/******************** Bit definition for CEC_CFGR register ******************/
+#define CEC_CFGR_PE_Pos (0U)
+#define CEC_CFGR_PE_Msk (0x1U << CEC_CFGR_PE_Pos) /*!< 0x00000001 */
+#define CEC_CFGR_PE CEC_CFGR_PE_Msk /*!< Peripheral Enable */
+#define CEC_CFGR_IE_Pos (1U)
+#define CEC_CFGR_IE_Msk (0x1U << CEC_CFGR_IE_Pos) /*!< 0x00000002 */
+#define CEC_CFGR_IE CEC_CFGR_IE_Msk /*!< Interrupt Enable */
+#define CEC_CFGR_BTEM_Pos (2U)
+#define CEC_CFGR_BTEM_Msk (0x1U << CEC_CFGR_BTEM_Pos) /*!< 0x00000004 */
+#define CEC_CFGR_BTEM CEC_CFGR_BTEM_Msk /*!< Bit Timing Error Mode */
+#define CEC_CFGR_BPEM_Pos (3U)
+#define CEC_CFGR_BPEM_Msk (0x1U << CEC_CFGR_BPEM_Pos) /*!< 0x00000008 */
+#define CEC_CFGR_BPEM CEC_CFGR_BPEM_Msk /*!< Bit Period Error Mode */
+
+/******************** Bit definition for CEC_OAR register ******************/
+#define CEC_OAR_OA_Pos (0U)
+#define CEC_OAR_OA_Msk (0xFU << CEC_OAR_OA_Pos) /*!< 0x0000000F */
+#define CEC_OAR_OA CEC_OAR_OA_Msk /*!< OA[3:0]: Own Address */
+#define CEC_OAR_OA_0 (0x1U << CEC_OAR_OA_Pos) /*!< 0x00000001 */
+#define CEC_OAR_OA_1 (0x2U << CEC_OAR_OA_Pos) /*!< 0x00000002 */
+#define CEC_OAR_OA_2 (0x4U << CEC_OAR_OA_Pos) /*!< 0x00000004 */
+#define CEC_OAR_OA_3 (0x8U << CEC_OAR_OA_Pos) /*!< 0x00000008 */
+
+/******************** Bit definition for CEC_PRES register ******************/
+#define CEC_PRES_PRES_Pos (0U)
+#define CEC_PRES_PRES_Msk (0x3FFFU << CEC_PRES_PRES_Pos) /*!< 0x00003FFF */
+#define CEC_PRES_PRES CEC_PRES_PRES_Msk /*!< Prescaler Counter Value */
+
+/******************** Bit definition for CEC_ESR register ******************/
+#define CEC_ESR_BTE_Pos (0U)
+#define CEC_ESR_BTE_Msk (0x1U << CEC_ESR_BTE_Pos) /*!< 0x00000001 */
+#define CEC_ESR_BTE CEC_ESR_BTE_Msk /*!< Bit Timing Error */
+#define CEC_ESR_BPE_Pos (1U)
+#define CEC_ESR_BPE_Msk (0x1U << CEC_ESR_BPE_Pos) /*!< 0x00000002 */
+#define CEC_ESR_BPE CEC_ESR_BPE_Msk /*!< Bit Period Error */
+#define CEC_ESR_RBTFE_Pos (2U)
+#define CEC_ESR_RBTFE_Msk (0x1U << CEC_ESR_RBTFE_Pos) /*!< 0x00000004 */
+#define CEC_ESR_RBTFE CEC_ESR_RBTFE_Msk /*!< Rx Block Transfer Finished Error */
+#define CEC_ESR_SBE_Pos (3U)
+#define CEC_ESR_SBE_Msk (0x1U << CEC_ESR_SBE_Pos) /*!< 0x00000008 */
+#define CEC_ESR_SBE CEC_ESR_SBE_Msk /*!< Start Bit Error */
+#define CEC_ESR_ACKE_Pos (4U)
+#define CEC_ESR_ACKE_Msk (0x1U << CEC_ESR_ACKE_Pos) /*!< 0x00000010 */
+#define CEC_ESR_ACKE CEC_ESR_ACKE_Msk /*!< Block Acknowledge Error */
+#define CEC_ESR_LINE_Pos (5U)
+#define CEC_ESR_LINE_Msk (0x1U << CEC_ESR_LINE_Pos) /*!< 0x00000020 */
+#define CEC_ESR_LINE CEC_ESR_LINE_Msk /*!< Line Error */
+#define CEC_ESR_TBTFE_Pos (6U)
+#define CEC_ESR_TBTFE_Msk (0x1U << CEC_ESR_TBTFE_Pos) /*!< 0x00000040 */
+#define CEC_ESR_TBTFE CEC_ESR_TBTFE_Msk /*!< Tx Block Transfer Finished Error */
+
+/******************** Bit definition for CEC_CSR register ******************/
+#define CEC_CSR_TSOM_Pos (0U)
+#define CEC_CSR_TSOM_Msk (0x1U << CEC_CSR_TSOM_Pos) /*!< 0x00000001 */
+#define CEC_CSR_TSOM CEC_CSR_TSOM_Msk /*!< Tx Start Of Message */
+#define CEC_CSR_TEOM_Pos (1U)
+#define CEC_CSR_TEOM_Msk (0x1U << CEC_CSR_TEOM_Pos) /*!< 0x00000002 */
+#define CEC_CSR_TEOM CEC_CSR_TEOM_Msk /*!< Tx End Of Message */
+#define CEC_CSR_TERR_Pos (2U)
+#define CEC_CSR_TERR_Msk (0x1U << CEC_CSR_TERR_Pos) /*!< 0x00000004 */
+#define CEC_CSR_TERR CEC_CSR_TERR_Msk /*!< Tx Error */
+#define CEC_CSR_TBTRF_Pos (3U)
+#define CEC_CSR_TBTRF_Msk (0x1U << CEC_CSR_TBTRF_Pos) /*!< 0x00000008 */
+#define CEC_CSR_TBTRF CEC_CSR_TBTRF_Msk /*!< Tx Byte Transfer Request or Block Transfer Finished */
+#define CEC_CSR_RSOM_Pos (4U)
+#define CEC_CSR_RSOM_Msk (0x1U << CEC_CSR_RSOM_Pos) /*!< 0x00000010 */
+#define CEC_CSR_RSOM CEC_CSR_RSOM_Msk /*!< Rx Start Of Message */
+#define CEC_CSR_REOM_Pos (5U)
+#define CEC_CSR_REOM_Msk (0x1U << CEC_CSR_REOM_Pos) /*!< 0x00000020 */
+#define CEC_CSR_REOM CEC_CSR_REOM_Msk /*!< Rx End Of Message */
+#define CEC_CSR_RERR_Pos (6U)
+#define CEC_CSR_RERR_Msk (0x1U << CEC_CSR_RERR_Pos) /*!< 0x00000040 */
+#define CEC_CSR_RERR CEC_CSR_RERR_Msk /*!< Rx Error */
+#define CEC_CSR_RBTF_Pos (7U)
+#define CEC_CSR_RBTF_Msk (0x1U << CEC_CSR_RBTF_Pos) /*!< 0x00000080 */
+#define CEC_CSR_RBTF CEC_CSR_RBTF_Msk /*!< Rx Block Transfer Finished */
+
+/******************** Bit definition for CEC_TXD register ******************/
+#define CEC_TXD_TXD_Pos (0U)
+#define CEC_TXD_TXD_Msk (0xFFU << CEC_TXD_TXD_Pos) /*!< 0x000000FF */
+#define CEC_TXD_TXD CEC_TXD_TXD_Msk /*!< Tx Data register */
+
+/******************** Bit definition for CEC_RXD register ******************/
+#define CEC_RXD_RXD_Pos (0U)
+#define CEC_RXD_RXD_Msk (0xFFU << CEC_RXD_RXD_Pos) /*!< 0x000000FF */
+#define CEC_RXD_RXD CEC_RXD_RXD_Msk /*!< Rx Data register */
+
+/*****************************************************************************/
+/* */
+/* Timers (TIM) */
+/* */
+/*****************************************************************************/
+/******************* Bit definition for TIM_CR1 register *******************/
+#define TIM_CR1_CEN_Pos (0U)
+#define TIM_CR1_CEN_Msk (0x1U << TIM_CR1_CEN_Pos) /*!< 0x00000001 */
+#define TIM_CR1_CEN TIM_CR1_CEN_Msk /*!<Counter enable */
+#define TIM_CR1_UDIS_Pos (1U)
+#define TIM_CR1_UDIS_Msk (0x1U << TIM_CR1_UDIS_Pos) /*!< 0x00000002 */
+#define TIM_CR1_UDIS TIM_CR1_UDIS_Msk /*!<Update disable */
+#define TIM_CR1_URS_Pos (2U)
+#define TIM_CR1_URS_Msk (0x1U << TIM_CR1_URS_Pos) /*!< 0x00000004 */
+#define TIM_CR1_URS TIM_CR1_URS_Msk /*!<Update request source */
+#define TIM_CR1_OPM_Pos (3U)
+#define TIM_CR1_OPM_Msk (0x1U << TIM_CR1_OPM_Pos) /*!< 0x00000008 */
+#define TIM_CR1_OPM TIM_CR1_OPM_Msk /*!<One pulse mode */
+#define TIM_CR1_DIR_Pos (4U)
+#define TIM_CR1_DIR_Msk (0x1U << TIM_CR1_DIR_Pos) /*!< 0x00000010 */
+#define TIM_CR1_DIR TIM_CR1_DIR_Msk /*!<Direction */
+
+#define TIM_CR1_CMS_Pos (5U)
+#define TIM_CR1_CMS_Msk (0x3U << TIM_CR1_CMS_Pos) /*!< 0x00000060 */
+#define TIM_CR1_CMS TIM_CR1_CMS_Msk /*!<CMS[1:0] bits (Center-aligned mode selection) */
+#define TIM_CR1_CMS_0 (0x1U << TIM_CR1_CMS_Pos) /*!< 0x00000020 */
+#define TIM_CR1_CMS_1 (0x2U << TIM_CR1_CMS_Pos) /*!< 0x00000040 */
+
+#define TIM_CR1_ARPE_Pos (7U)
+#define TIM_CR1_ARPE_Msk (0x1U << TIM_CR1_ARPE_Pos) /*!< 0x00000080 */
+#define TIM_CR1_ARPE TIM_CR1_ARPE_Msk /*!<Auto-reload preload enable */
+
+#define TIM_CR1_CKD_Pos (8U)
+#define TIM_CR1_CKD_Msk (0x3U << TIM_CR1_CKD_Pos) /*!< 0x00000300 */
+#define TIM_CR1_CKD TIM_CR1_CKD_Msk /*!<CKD[1:0] bits (clock division) */
+#define TIM_CR1_CKD_0 (0x1U << TIM_CR1_CKD_Pos) /*!< 0x00000100 */
+#define TIM_CR1_CKD_1 (0x2U << TIM_CR1_CKD_Pos) /*!< 0x00000200 */
+
+/******************* Bit definition for TIM_CR2 register *******************/
+#define TIM_CR2_CCPC_Pos (0U)
+#define TIM_CR2_CCPC_Msk (0x1U << TIM_CR2_CCPC_Pos) /*!< 0x00000001 */
+#define TIM_CR2_CCPC TIM_CR2_CCPC_Msk /*!<Capture/Compare Preloaded Control */
+#define TIM_CR2_CCUS_Pos (2U)
+#define TIM_CR2_CCUS_Msk (0x1U << TIM_CR2_CCUS_Pos) /*!< 0x00000004 */
+#define TIM_CR2_CCUS TIM_CR2_CCUS_Msk /*!<Capture/Compare Control Update Selection */
+#define TIM_CR2_CCDS_Pos (3U)
+#define TIM_CR2_CCDS_Msk (0x1U << TIM_CR2_CCDS_Pos) /*!< 0x00000008 */
+#define TIM_CR2_CCDS TIM_CR2_CCDS_Msk /*!<Capture/Compare DMA Selection */
+
+#define TIM_CR2_MMS_Pos (4U)
+#define TIM_CR2_MMS_Msk (0x7U << TIM_CR2_MMS_Pos) /*!< 0x00000070 */
+#define TIM_CR2_MMS TIM_CR2_MMS_Msk /*!<MMS[2:0] bits (Master Mode Selection) */
+#define TIM_CR2_MMS_0 (0x1U << TIM_CR2_MMS_Pos) /*!< 0x00000010 */
+#define TIM_CR2_MMS_1 (0x2U << TIM_CR2_MMS_Pos) /*!< 0x00000020 */
+#define TIM_CR2_MMS_2 (0x4U << TIM_CR2_MMS_Pos) /*!< 0x00000040 */
+
+#define TIM_CR2_TI1S_Pos (7U)
+#define TIM_CR2_TI1S_Msk (0x1U << TIM_CR2_TI1S_Pos) /*!< 0x00000080 */
+#define TIM_CR2_TI1S TIM_CR2_TI1S_Msk /*!<TI1 Selection */
+#define TIM_CR2_OIS1_Pos (8U)
+#define TIM_CR2_OIS1_Msk (0x1U << TIM_CR2_OIS1_Pos) /*!< 0x00000100 */
+#define TIM_CR2_OIS1 TIM_CR2_OIS1_Msk /*!<Output Idle state 1 (OC1 output) */
+#define TIM_CR2_OIS1N_Pos (9U)
+#define TIM_CR2_OIS1N_Msk (0x1U << TIM_CR2_OIS1N_Pos) /*!< 0x00000200 */
+#define TIM_CR2_OIS1N TIM_CR2_OIS1N_Msk /*!<Output Idle state 1 (OC1N output) */
+#define TIM_CR2_OIS2_Pos (10U)
+#define TIM_CR2_OIS2_Msk (0x1U << TIM_CR2_OIS2_Pos) /*!< 0x00000400 */
+#define TIM_CR2_OIS2 TIM_CR2_OIS2_Msk /*!<Output Idle state 2 (OC2 output) */
+#define TIM_CR2_OIS2N_Pos (11U)
+#define TIM_CR2_OIS2N_Msk (0x1U << TIM_CR2_OIS2N_Pos) /*!< 0x00000800 */
+#define TIM_CR2_OIS2N TIM_CR2_OIS2N_Msk /*!<Output Idle state 2 (OC2N output) */
+#define TIM_CR2_OIS3_Pos (12U)
+#define TIM_CR2_OIS3_Msk (0x1U << TIM_CR2_OIS3_Pos) /*!< 0x00001000 */
+#define TIM_CR2_OIS3 TIM_CR2_OIS3_Msk /*!<Output Idle state 3 (OC3 output) */
+#define TIM_CR2_OIS3N_Pos (13U)
+#define TIM_CR2_OIS3N_Msk (0x1U << TIM_CR2_OIS3N_Pos) /*!< 0x00002000 */
+#define TIM_CR2_OIS3N TIM_CR2_OIS3N_Msk /*!<Output Idle state 3 (OC3N output) */
+#define TIM_CR2_OIS4_Pos (14U)
+#define TIM_CR2_OIS4_Msk (0x1U << TIM_CR2_OIS4_Pos) /*!< 0x00004000 */
+#define TIM_CR2_OIS4 TIM_CR2_OIS4_Msk /*!<Output Idle state 4 (OC4 output) */
+
+/******************* Bit definition for TIM_SMCR register ******************/
+#define TIM_SMCR_SMS_Pos (0U)
+#define TIM_SMCR_SMS_Msk (0x7U << TIM_SMCR_SMS_Pos) /*!< 0x00000007 */
+#define TIM_SMCR_SMS TIM_SMCR_SMS_Msk /*!<SMS[2:0] bits (Slave mode selection) */
+#define TIM_SMCR_SMS_0 (0x1U << TIM_SMCR_SMS_Pos) /*!< 0x00000001 */
+#define TIM_SMCR_SMS_1 (0x2U << TIM_SMCR_SMS_Pos) /*!< 0x00000002 */
+#define TIM_SMCR_SMS_2 (0x4U << TIM_SMCR_SMS_Pos) /*!< 0x00000004 */
+
+#define TIM_SMCR_OCCS_Pos (3U)
+#define TIM_SMCR_OCCS_Msk (0x1U << TIM_SMCR_OCCS_Pos) /*!< 0x00000008 */
+#define TIM_SMCR_OCCS TIM_SMCR_OCCS_Msk /*!< OCREF clear selection */
+
+#define TIM_SMCR_TS_Pos (4U)
+#define TIM_SMCR_TS_Msk (0x7U << TIM_SMCR_TS_Pos) /*!< 0x00000070 */
+#define TIM_SMCR_TS TIM_SMCR_TS_Msk /*!<TS[2:0] bits (Trigger selection) */
+#define TIM_SMCR_TS_0 (0x1U << TIM_SMCR_TS_Pos) /*!< 0x00000010 */
+#define TIM_SMCR_TS_1 (0x2U << TIM_SMCR_TS_Pos) /*!< 0x00000020 */
+#define TIM_SMCR_TS_2 (0x4U << TIM_SMCR_TS_Pos) /*!< 0x00000040 */
+
+#define TIM_SMCR_MSM_Pos (7U)
+#define TIM_SMCR_MSM_Msk (0x1U << TIM_SMCR_MSM_Pos) /*!< 0x00000080 */
+#define TIM_SMCR_MSM TIM_SMCR_MSM_Msk /*!<Master/slave mode */
+
+#define TIM_SMCR_ETF_Pos (8U)
+#define TIM_SMCR_ETF_Msk (0xFU << TIM_SMCR_ETF_Pos) /*!< 0x00000F00 */
+#define TIM_SMCR_ETF TIM_SMCR_ETF_Msk /*!<ETF[3:0] bits (External trigger filter) */
+#define TIM_SMCR_ETF_0 (0x1U << TIM_SMCR_ETF_Pos) /*!< 0x00000100 */
+#define TIM_SMCR_ETF_1 (0x2U << TIM_SMCR_ETF_Pos) /*!< 0x00000200 */
+#define TIM_SMCR_ETF_2 (0x4U << TIM_SMCR_ETF_Pos) /*!< 0x00000400 */
+#define TIM_SMCR_ETF_3 (0x8U << TIM_SMCR_ETF_Pos) /*!< 0x00000800 */
+
+#define TIM_SMCR_ETPS_Pos (12U)
+#define TIM_SMCR_ETPS_Msk (0x3U << TIM_SMCR_ETPS_Pos) /*!< 0x00003000 */
+#define TIM_SMCR_ETPS TIM_SMCR_ETPS_Msk /*!<ETPS[1:0] bits (External trigger prescaler) */
+#define TIM_SMCR_ETPS_0 (0x1U << TIM_SMCR_ETPS_Pos) /*!< 0x00001000 */
+#define TIM_SMCR_ETPS_1 (0x2U << TIM_SMCR_ETPS_Pos) /*!< 0x00002000 */
+
+#define TIM_SMCR_ECE_Pos (14U)
+#define TIM_SMCR_ECE_Msk (0x1U << TIM_SMCR_ECE_Pos) /*!< 0x00004000 */
+#define TIM_SMCR_ECE TIM_SMCR_ECE_Msk /*!<External clock enable */
+#define TIM_SMCR_ETP_Pos (15U)
+#define TIM_SMCR_ETP_Msk (0x1U << TIM_SMCR_ETP_Pos) /*!< 0x00008000 */
+#define TIM_SMCR_ETP TIM_SMCR_ETP_Msk /*!<External trigger polarity */
+
+/******************* Bit definition for TIM_DIER register ******************/
+#define TIM_DIER_UIE_Pos (0U)
+#define TIM_DIER_UIE_Msk (0x1U << TIM_DIER_UIE_Pos) /*!< 0x00000001 */
+#define TIM_DIER_UIE TIM_DIER_UIE_Msk /*!<Update interrupt enable */
+#define TIM_DIER_CC1IE_Pos (1U)
+#define TIM_DIER_CC1IE_Msk (0x1U << TIM_DIER_CC1IE_Pos) /*!< 0x00000002 */
+#define TIM_DIER_CC1IE TIM_DIER_CC1IE_Msk /*!<Capture/Compare 1 interrupt enable */
+#define TIM_DIER_CC2IE_Pos (2U)
+#define TIM_DIER_CC2IE_Msk (0x1U << TIM_DIER_CC2IE_Pos) /*!< 0x00000004 */
+#define TIM_DIER_CC2IE TIM_DIER_CC2IE_Msk /*!<Capture/Compare 2 interrupt enable */
+#define TIM_DIER_CC3IE_Pos (3U)
+#define TIM_DIER_CC3IE_Msk (0x1U << TIM_DIER_CC3IE_Pos) /*!< 0x00000008 */
+#define TIM_DIER_CC3IE TIM_DIER_CC3IE_Msk /*!<Capture/Compare 3 interrupt enable */
+#define TIM_DIER_CC4IE_Pos (4U)
+#define TIM_DIER_CC4IE_Msk (0x1U << TIM_DIER_CC4IE_Pos) /*!< 0x00000010 */
+#define TIM_DIER_CC4IE TIM_DIER_CC4IE_Msk /*!<Capture/Compare 4 interrupt enable */
+#define TIM_DIER_COMIE_Pos (5U)
+#define TIM_DIER_COMIE_Msk (0x1U << TIM_DIER_COMIE_Pos) /*!< 0x00000020 */
+#define TIM_DIER_COMIE TIM_DIER_COMIE_Msk /*!<COM interrupt enable */
+#define TIM_DIER_TIE_Pos (6U)
+#define TIM_DIER_TIE_Msk (0x1U << TIM_DIER_TIE_Pos) /*!< 0x00000040 */
+#define TIM_DIER_TIE TIM_DIER_TIE_Msk /*!<Trigger interrupt enable */
+#define TIM_DIER_BIE_Pos (7U)
+#define TIM_DIER_BIE_Msk (0x1U << TIM_DIER_BIE_Pos) /*!< 0x00000080 */
+#define TIM_DIER_BIE TIM_DIER_BIE_Msk /*!<Break interrupt enable */
+#define TIM_DIER_UDE_Pos (8U)
+#define TIM_DIER_UDE_Msk (0x1U << TIM_DIER_UDE_Pos) /*!< 0x00000100 */
+#define TIM_DIER_UDE TIM_DIER_UDE_Msk /*!<Update DMA request enable */
+#define TIM_DIER_CC1DE_Pos (9U)
+#define TIM_DIER_CC1DE_Msk (0x1U << TIM_DIER_CC1DE_Pos) /*!< 0x00000200 */
+#define TIM_DIER_CC1DE TIM_DIER_CC1DE_Msk /*!<Capture/Compare 1 DMA request enable */
+#define TIM_DIER_CC2DE_Pos (10U)
+#define TIM_DIER_CC2DE_Msk (0x1U << TIM_DIER_CC2DE_Pos) /*!< 0x00000400 */
+#define TIM_DIER_CC2DE TIM_DIER_CC2DE_Msk /*!<Capture/Compare 2 DMA request enable */
+#define TIM_DIER_CC3DE_Pos (11U)
+#define TIM_DIER_CC3DE_Msk (0x1U << TIM_DIER_CC3DE_Pos) /*!< 0x00000800 */
+#define TIM_DIER_CC3DE TIM_DIER_CC3DE_Msk /*!<Capture/Compare 3 DMA request enable */
+#define TIM_DIER_CC4DE_Pos (12U)
+#define TIM_DIER_CC4DE_Msk (0x1U << TIM_DIER_CC4DE_Pos) /*!< 0x00001000 */
+#define TIM_DIER_CC4DE TIM_DIER_CC4DE_Msk /*!<Capture/Compare 4 DMA request enable */
+#define TIM_DIER_COMDE_Pos (13U)
+#define TIM_DIER_COMDE_Msk (0x1U << TIM_DIER_COMDE_Pos) /*!< 0x00002000 */
+#define TIM_DIER_COMDE TIM_DIER_COMDE_Msk /*!<COM DMA request enable */
+#define TIM_DIER_TDE_Pos (14U)
+#define TIM_DIER_TDE_Msk (0x1U << TIM_DIER_TDE_Pos) /*!< 0x00004000 */
+#define TIM_DIER_TDE TIM_DIER_TDE_Msk /*!<Trigger DMA request enable */
+
+/******************** Bit definition for TIM_SR register *******************/
+#define TIM_SR_UIF_Pos (0U)
+#define TIM_SR_UIF_Msk (0x1U << TIM_SR_UIF_Pos) /*!< 0x00000001 */
+#define TIM_SR_UIF TIM_SR_UIF_Msk /*!<Update interrupt Flag */
+#define TIM_SR_CC1IF_Pos (1U)
+#define TIM_SR_CC1IF_Msk (0x1U << TIM_SR_CC1IF_Pos) /*!< 0x00000002 */
+#define TIM_SR_CC1IF TIM_SR_CC1IF_Msk /*!<Capture/Compare 1 interrupt Flag */
+#define TIM_SR_CC2IF_Pos (2U)
+#define TIM_SR_CC2IF_Msk (0x1U << TIM_SR_CC2IF_Pos) /*!< 0x00000004 */
+#define TIM_SR_CC2IF TIM_SR_CC2IF_Msk /*!<Capture/Compare 2 interrupt Flag */
+#define TIM_SR_CC3IF_Pos (3U)
+#define TIM_SR_CC3IF_Msk (0x1U << TIM_SR_CC3IF_Pos) /*!< 0x00000008 */
+#define TIM_SR_CC3IF TIM_SR_CC3IF_Msk /*!<Capture/Compare 3 interrupt Flag */
+#define TIM_SR_CC4IF_Pos (4U)
+#define TIM_SR_CC4IF_Msk (0x1U << TIM_SR_CC4IF_Pos) /*!< 0x00000010 */
+#define TIM_SR_CC4IF TIM_SR_CC4IF_Msk /*!<Capture/Compare 4 interrupt Flag */
+#define TIM_SR_COMIF_Pos (5U)
+#define TIM_SR_COMIF_Msk (0x1U << TIM_SR_COMIF_Pos) /*!< 0x00000020 */
+#define TIM_SR_COMIF TIM_SR_COMIF_Msk /*!<COM interrupt Flag */
+#define TIM_SR_TIF_Pos (6U)
+#define TIM_SR_TIF_Msk (0x1U << TIM_SR_TIF_Pos) /*!< 0x00000040 */
+#define TIM_SR_TIF TIM_SR_TIF_Msk /*!<Trigger interrupt Flag */
+#define TIM_SR_BIF_Pos (7U)
+#define TIM_SR_BIF_Msk (0x1U << TIM_SR_BIF_Pos) /*!< 0x00000080 */
+#define TIM_SR_BIF TIM_SR_BIF_Msk /*!<Break interrupt Flag */
+#define TIM_SR_CC1OF_Pos (9U)
+#define TIM_SR_CC1OF_Msk (0x1U << TIM_SR_CC1OF_Pos) /*!< 0x00000200 */
+#define TIM_SR_CC1OF TIM_SR_CC1OF_Msk /*!<Capture/Compare 1 Overcapture Flag */
+#define TIM_SR_CC2OF_Pos (10U)
+#define TIM_SR_CC2OF_Msk (0x1U << TIM_SR_CC2OF_Pos) /*!< 0x00000400 */
+#define TIM_SR_CC2OF TIM_SR_CC2OF_Msk /*!<Capture/Compare 2 Overcapture Flag */
+#define TIM_SR_CC3OF_Pos (11U)
+#define TIM_SR_CC3OF_Msk (0x1U << TIM_SR_CC3OF_Pos) /*!< 0x00000800 */
+#define TIM_SR_CC3OF TIM_SR_CC3OF_Msk /*!<Capture/Compare 3 Overcapture Flag */
+#define TIM_SR_CC4OF_Pos (12U)
+#define TIM_SR_CC4OF_Msk (0x1U << TIM_SR_CC4OF_Pos) /*!< 0x00001000 */
+#define TIM_SR_CC4OF TIM_SR_CC4OF_Msk /*!<Capture/Compare 4 Overcapture Flag */
+
+/******************* Bit definition for TIM_EGR register *******************/
+#define TIM_EGR_UG_Pos (0U)
+#define TIM_EGR_UG_Msk (0x1U << TIM_EGR_UG_Pos) /*!< 0x00000001 */
+#define TIM_EGR_UG TIM_EGR_UG_Msk /*!<Update Generation */
+#define TIM_EGR_CC1G_Pos (1U)
+#define TIM_EGR_CC1G_Msk (0x1U << TIM_EGR_CC1G_Pos) /*!< 0x00000002 */
+#define TIM_EGR_CC1G TIM_EGR_CC1G_Msk /*!<Capture/Compare 1 Generation */
+#define TIM_EGR_CC2G_Pos (2U)
+#define TIM_EGR_CC2G_Msk (0x1U << TIM_EGR_CC2G_Pos) /*!< 0x00000004 */
+#define TIM_EGR_CC2G TIM_EGR_CC2G_Msk /*!<Capture/Compare 2 Generation */
+#define TIM_EGR_CC3G_Pos (3U)
+#define TIM_EGR_CC3G_Msk (0x1U << TIM_EGR_CC3G_Pos) /*!< 0x00000008 */
+#define TIM_EGR_CC3G TIM_EGR_CC3G_Msk /*!<Capture/Compare 3 Generation */
+#define TIM_EGR_CC4G_Pos (4U)
+#define TIM_EGR_CC4G_Msk (0x1U << TIM_EGR_CC4G_Pos) /*!< 0x00000010 */
+#define TIM_EGR_CC4G TIM_EGR_CC4G_Msk /*!<Capture/Compare 4 Generation */
+#define TIM_EGR_COMG_Pos (5U)
+#define TIM_EGR_COMG_Msk (0x1U << TIM_EGR_COMG_Pos) /*!< 0x00000020 */
+#define TIM_EGR_COMG TIM_EGR_COMG_Msk /*!<Capture/Compare Control Update Generation */
+#define TIM_EGR_TG_Pos (6U)
+#define TIM_EGR_TG_Msk (0x1U << TIM_EGR_TG_Pos) /*!< 0x00000040 */
+#define TIM_EGR_TG TIM_EGR_TG_Msk /*!<Trigger Generation */
+#define TIM_EGR_BG_Pos (7U)
+#define TIM_EGR_BG_Msk (0x1U << TIM_EGR_BG_Pos) /*!< 0x00000080 */
+#define TIM_EGR_BG TIM_EGR_BG_Msk /*!<Break Generation */
+
+/****************** Bit definition for TIM_CCMR1 register ******************/
+#define TIM_CCMR1_CC1S_Pos (0U)
+#define TIM_CCMR1_CC1S_Msk (0x3U << TIM_CCMR1_CC1S_Pos) /*!< 0x00000003 */
+#define TIM_CCMR1_CC1S TIM_CCMR1_CC1S_Msk /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
+#define TIM_CCMR1_CC1S_0 (0x1U << TIM_CCMR1_CC1S_Pos) /*!< 0x00000001 */
+#define TIM_CCMR1_CC1S_1 (0x2U << TIM_CCMR1_CC1S_Pos) /*!< 0x00000002 */
+
+#define TIM_CCMR1_OC1FE_Pos (2U)
+#define TIM_CCMR1_OC1FE_Msk (0x1U << TIM_CCMR1_OC1FE_Pos) /*!< 0x00000004 */
+#define TIM_CCMR1_OC1FE TIM_CCMR1_OC1FE_Msk /*!<Output Compare 1 Fast enable */
+#define TIM_CCMR1_OC1PE_Pos (3U)
+#define TIM_CCMR1_OC1PE_Msk (0x1U << TIM_CCMR1_OC1PE_Pos) /*!< 0x00000008 */
+#define TIM_CCMR1_OC1PE TIM_CCMR1_OC1PE_Msk /*!<Output Compare 1 Preload enable */
+
+#define TIM_CCMR1_OC1M_Pos (4U)
+#define TIM_CCMR1_OC1M_Msk (0x7U << TIM_CCMR1_OC1M_Pos) /*!< 0x00000070 */
+#define TIM_CCMR1_OC1M TIM_CCMR1_OC1M_Msk /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
+#define TIM_CCMR1_OC1M_0 (0x1U << TIM_CCMR1_OC1M_Pos) /*!< 0x00000010 */
+#define TIM_CCMR1_OC1M_1 (0x2U << TIM_CCMR1_OC1M_Pos) /*!< 0x00000020 */
+#define TIM_CCMR1_OC1M_2 (0x4U << TIM_CCMR1_OC1M_Pos) /*!< 0x00000040 */
+
+#define TIM_CCMR1_OC1CE_Pos (7U)
+#define TIM_CCMR1_OC1CE_Msk (0x1U << TIM_CCMR1_OC1CE_Pos) /*!< 0x00000080 */
+#define TIM_CCMR1_OC1CE TIM_CCMR1_OC1CE_Msk /*!<Output Compare 1Clear Enable */
+
+#define TIM_CCMR1_CC2S_Pos (8U)
+#define TIM_CCMR1_CC2S_Msk (0x3U << TIM_CCMR1_CC2S_Pos) /*!< 0x00000300 */
+#define TIM_CCMR1_CC2S TIM_CCMR1_CC2S_Msk /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
+#define TIM_CCMR1_CC2S_0 (0x1U << TIM_CCMR1_CC2S_Pos) /*!< 0x00000100 */
+#define TIM_CCMR1_CC2S_1 (0x2U << TIM_CCMR1_CC2S_Pos) /*!< 0x00000200 */
+
+#define TIM_CCMR1_OC2FE_Pos (10U)
+#define TIM_CCMR1_OC2FE_Msk (0x1U << TIM_CCMR1_OC2FE_Pos) /*!< 0x00000400 */
+#define TIM_CCMR1_OC2FE TIM_CCMR1_OC2FE_Msk /*!<Output Compare 2 Fast enable */
+#define TIM_CCMR1_OC2PE_Pos (11U)
+#define TIM_CCMR1_OC2PE_Msk (0x1U << TIM_CCMR1_OC2PE_Pos) /*!< 0x00000800 */
+#define TIM_CCMR1_OC2PE TIM_CCMR1_OC2PE_Msk /*!<Output Compare 2 Preload enable */
+
+#define TIM_CCMR1_OC2M_Pos (12U)
+#define TIM_CCMR1_OC2M_Msk (0x7U << TIM_CCMR1_OC2M_Pos) /*!< 0x00007000 */
+#define TIM_CCMR1_OC2M TIM_CCMR1_OC2M_Msk /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
+#define TIM_CCMR1_OC2M_0 (0x1U << TIM_CCMR1_OC2M_Pos) /*!< 0x00001000 */
+#define TIM_CCMR1_OC2M_1 (0x2U << TIM_CCMR1_OC2M_Pos) /*!< 0x00002000 */
+#define TIM_CCMR1_OC2M_2 (0x4U << TIM_CCMR1_OC2M_Pos) /*!< 0x00004000 */
+
+#define TIM_CCMR1_OC2CE_Pos (15U)
+#define TIM_CCMR1_OC2CE_Msk (0x1U << TIM_CCMR1_OC2CE_Pos) /*!< 0x00008000 */
+#define TIM_CCMR1_OC2CE TIM_CCMR1_OC2CE_Msk /*!<Output Compare 2 Clear Enable */
+
+/*---------------------------------------------------------------------------*/
+
+#define TIM_CCMR1_IC1PSC_Pos (2U)
+#define TIM_CCMR1_IC1PSC_Msk (0x3U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x0000000C */
+#define TIM_CCMR1_IC1PSC TIM_CCMR1_IC1PSC_Msk /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
+#define TIM_CCMR1_IC1PSC_0 (0x1U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x00000004 */
+#define TIM_CCMR1_IC1PSC_1 (0x2U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x00000008 */
+
+#define TIM_CCMR1_IC1F_Pos (4U)
+#define TIM_CCMR1_IC1F_Msk (0xFU << TIM_CCMR1_IC1F_Pos) /*!< 0x000000F0 */
+#define TIM_CCMR1_IC1F TIM_CCMR1_IC1F_Msk /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
+#define TIM_CCMR1_IC1F_0 (0x1U << TIM_CCMR1_IC1F_Pos) /*!< 0x00000010 */
+#define TIM_CCMR1_IC1F_1 (0x2U << TIM_CCMR1_IC1F_Pos) /*!< 0x00000020 */
+#define TIM_CCMR1_IC1F_2 (0x4U << TIM_CCMR1_IC1F_Pos) /*!< 0x00000040 */
+#define TIM_CCMR1_IC1F_3 (0x8U << TIM_CCMR1_IC1F_Pos) /*!< 0x00000080 */
+
+#define TIM_CCMR1_IC2PSC_Pos (10U)
+#define TIM_CCMR1_IC2PSC_Msk (0x3U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000C00 */
+#define TIM_CCMR1_IC2PSC TIM_CCMR1_IC2PSC_Msk /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
+#define TIM_CCMR1_IC2PSC_0 (0x1U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000400 */
+#define TIM_CCMR1_IC2PSC_1 (0x2U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000800 */
+
+#define TIM_CCMR1_IC2F_Pos (12U)
+#define TIM_CCMR1_IC2F_Msk (0xFU << TIM_CCMR1_IC2F_Pos) /*!< 0x0000F000 */
+#define TIM_CCMR1_IC2F TIM_CCMR1_IC2F_Msk /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
+#define TIM_CCMR1_IC2F_0 (0x1U << TIM_CCMR1_IC2F_Pos) /*!< 0x00001000 */
+#define TIM_CCMR1_IC2F_1 (0x2U << TIM_CCMR1_IC2F_Pos) /*!< 0x00002000 */
+#define TIM_CCMR1_IC2F_2 (0x4U << TIM_CCMR1_IC2F_Pos) /*!< 0x00004000 */
+#define TIM_CCMR1_IC2F_3 (0x8U << TIM_CCMR1_IC2F_Pos) /*!< 0x00008000 */
+
+/****************** Bit definition for TIM_CCMR2 register ******************/
+#define TIM_CCMR2_CC3S_Pos (0U)
+#define TIM_CCMR2_CC3S_Msk (0x3U << TIM_CCMR2_CC3S_Pos) /*!< 0x00000003 */
+#define TIM_CCMR2_CC3S TIM_CCMR2_CC3S_Msk /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
+#define TIM_CCMR2_CC3S_0 (0x1U << TIM_CCMR2_CC3S_Pos) /*!< 0x00000001 */
+#define TIM_CCMR2_CC3S_1 (0x2U << TIM_CCMR2_CC3S_Pos) /*!< 0x00000002 */
+
+#define TIM_CCMR2_OC3FE_Pos (2U)
+#define TIM_CCMR2_OC3FE_Msk (0x1U << TIM_CCMR2_OC3FE_Pos) /*!< 0x00000004 */
+#define TIM_CCMR2_OC3FE TIM_CCMR2_OC3FE_Msk /*!<Output Compare 3 Fast enable */
+#define TIM_CCMR2_OC3PE_Pos (3U)
+#define TIM_CCMR2_OC3PE_Msk (0x1U << TIM_CCMR2_OC3PE_Pos) /*!< 0x00000008 */
+#define TIM_CCMR2_OC3PE TIM_CCMR2_OC3PE_Msk /*!<Output Compare 3 Preload enable */
+
+#define TIM_CCMR2_OC3M_Pos (4U)
+#define TIM_CCMR2_OC3M_Msk (0x7U << TIM_CCMR2_OC3M_Pos) /*!< 0x00000070 */
+#define TIM_CCMR2_OC3M TIM_CCMR2_OC3M_Msk /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
+#define TIM_CCMR2_OC3M_0 (0x1U << TIM_CCMR2_OC3M_Pos) /*!< 0x00000010 */
+#define TIM_CCMR2_OC3M_1 (0x2U << TIM_CCMR2_OC3M_Pos) /*!< 0x00000020 */
+#define TIM_CCMR2_OC3M_2 (0x4U << TIM_CCMR2_OC3M_Pos) /*!< 0x00000040 */
+
+#define TIM_CCMR2_OC3CE_Pos (7U)
+#define TIM_CCMR2_OC3CE_Msk (0x1U << TIM_CCMR2_OC3CE_Pos) /*!< 0x00000080 */
+#define TIM_CCMR2_OC3CE TIM_CCMR2_OC3CE_Msk /*!<Output Compare 3 Clear Enable */
+
+#define TIM_CCMR2_CC4S_Pos (8U)
+#define TIM_CCMR2_CC4S_Msk (0x3U << TIM_CCMR2_CC4S_Pos) /*!< 0x00000300 */
+#define TIM_CCMR2_CC4S TIM_CCMR2_CC4S_Msk /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
+#define TIM_CCMR2_CC4S_0 (0x1U << TIM_CCMR2_CC4S_Pos) /*!< 0x00000100 */
+#define TIM_CCMR2_CC4S_1 (0x2U << TIM_CCMR2_CC4S_Pos) /*!< 0x00000200 */
+
+#define TIM_CCMR2_OC4FE_Pos (10U)
+#define TIM_CCMR2_OC4FE_Msk (0x1U << TIM_CCMR2_OC4FE_Pos) /*!< 0x00000400 */
+#define TIM_CCMR2_OC4FE TIM_CCMR2_OC4FE_Msk /*!<Output Compare 4 Fast enable */
+#define TIM_CCMR2_OC4PE_Pos (11U)
+#define TIM_CCMR2_OC4PE_Msk (0x1U << TIM_CCMR2_OC4PE_Pos) /*!< 0x00000800 */
+#define TIM_CCMR2_OC4PE TIM_CCMR2_OC4PE_Msk /*!<Output Compare 4 Preload enable */
+
+#define TIM_CCMR2_OC4M_Pos (12U)
+#define TIM_CCMR2_OC4M_Msk (0x7U << TIM_CCMR2_OC4M_Pos) /*!< 0x00007000 */
+#define TIM_CCMR2_OC4M TIM_CCMR2_OC4M_Msk /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
+#define TIM_CCMR2_OC4M_0 (0x1U << TIM_CCMR2_OC4M_Pos) /*!< 0x00001000 */
+#define TIM_CCMR2_OC4M_1 (0x2U << TIM_CCMR2_OC4M_Pos) /*!< 0x00002000 */
+#define TIM_CCMR2_OC4M_2 (0x4U << TIM_CCMR2_OC4M_Pos) /*!< 0x00004000 */
+
+#define TIM_CCMR2_OC4CE_Pos (15U)
+#define TIM_CCMR2_OC4CE_Msk (0x1U << TIM_CCMR2_OC4CE_Pos) /*!< 0x00008000 */
+#define TIM_CCMR2_OC4CE TIM_CCMR2_OC4CE_Msk /*!<Output Compare 4 Clear Enable */
+
+/*---------------------------------------------------------------------------*/
+
+#define TIM_CCMR2_IC3PSC_Pos (2U)
+#define TIM_CCMR2_IC3PSC_Msk (0x3U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x0000000C */
+#define TIM_CCMR2_IC3PSC TIM_CCMR2_IC3PSC_Msk /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
+#define TIM_CCMR2_IC3PSC_0 (0x1U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x00000004 */
+#define TIM_CCMR2_IC3PSC_1 (0x2U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x00000008 */
+
+#define TIM_CCMR2_IC3F_Pos (4U)
+#define TIM_CCMR2_IC3F_Msk (0xFU << TIM_CCMR2_IC3F_Pos) /*!< 0x000000F0 */
+#define TIM_CCMR2_IC3F TIM_CCMR2_IC3F_Msk /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
+#define TIM_CCMR2_IC3F_0 (0x1U << TIM_CCMR2_IC3F_Pos) /*!< 0x00000010 */
+#define TIM_CCMR2_IC3F_1 (0x2U << TIM_CCMR2_IC3F_Pos) /*!< 0x00000020 */
+#define TIM_CCMR2_IC3F_2 (0x4U << TIM_CCMR2_IC3F_Pos) /*!< 0x00000040 */
+#define TIM_CCMR2_IC3F_3 (0x8U << TIM_CCMR2_IC3F_Pos) /*!< 0x00000080 */
+
+#define TIM_CCMR2_IC4PSC_Pos (10U)
+#define TIM_CCMR2_IC4PSC_Msk (0x3U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000C00 */
+#define TIM_CCMR2_IC4PSC TIM_CCMR2_IC4PSC_Msk /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
+#define TIM_CCMR2_IC4PSC_0 (0x1U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000400 */
+#define TIM_CCMR2_IC4PSC_1 (0x2U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000800 */
+
+#define TIM_CCMR2_IC4F_Pos (12U)
+#define TIM_CCMR2_IC4F_Msk (0xFU << TIM_CCMR2_IC4F_Pos) /*!< 0x0000F000 */
+#define TIM_CCMR2_IC4F TIM_CCMR2_IC4F_Msk /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
+#define TIM_CCMR2_IC4F_0 (0x1U << TIM_CCMR2_IC4F_Pos) /*!< 0x00001000 */
+#define TIM_CCMR2_IC4F_1 (0x2U << TIM_CCMR2_IC4F_Pos) /*!< 0x00002000 */
+#define TIM_CCMR2_IC4F_2 (0x4U << TIM_CCMR2_IC4F_Pos) /*!< 0x00004000 */
+#define TIM_CCMR2_IC4F_3 (0x8U << TIM_CCMR2_IC4F_Pos) /*!< 0x00008000 */
+
+/******************* Bit definition for TIM_CCER register ******************/
+#define TIM_CCER_CC1E_Pos (0U)
+#define TIM_CCER_CC1E_Msk (0x1U << TIM_CCER_CC1E_Pos) /*!< 0x00000001 */
+#define TIM_CCER_CC1E TIM_CCER_CC1E_Msk /*!<Capture/Compare 1 output enable */
+#define TIM_CCER_CC1P_Pos (1U)
+#define TIM_CCER_CC1P_Msk (0x1U << TIM_CCER_CC1P_Pos) /*!< 0x00000002 */
+#define TIM_CCER_CC1P TIM_CCER_CC1P_Msk /*!<Capture/Compare 1 output Polarity */
+#define TIM_CCER_CC1NE_Pos (2U)
+#define TIM_CCER_CC1NE_Msk (0x1U << TIM_CCER_CC1NE_Pos) /*!< 0x00000004 */
+#define TIM_CCER_CC1NE TIM_CCER_CC1NE_Msk /*!<Capture/Compare 1 Complementary output enable */
+#define TIM_CCER_CC1NP_Pos (3U)
+#define TIM_CCER_CC1NP_Msk (0x1U << TIM_CCER_CC1NP_Pos) /*!< 0x00000008 */
+#define TIM_CCER_CC1NP TIM_CCER_CC1NP_Msk /*!<Capture/Compare 1 Complementary output Polarity */
+#define TIM_CCER_CC2E_Pos (4U)
+#define TIM_CCER_CC2E_Msk (0x1U << TIM_CCER_CC2E_Pos) /*!< 0x00000010 */
+#define TIM_CCER_CC2E TIM_CCER_CC2E_Msk /*!<Capture/Compare 2 output enable */
+#define TIM_CCER_CC2P_Pos (5U)
+#define TIM_CCER_CC2P_Msk (0x1U << TIM_CCER_CC2P_Pos) /*!< 0x00000020 */
+#define TIM_CCER_CC2P TIM_CCER_CC2P_Msk /*!<Capture/Compare 2 output Polarity */
+#define TIM_CCER_CC2NE_Pos (6U)
+#define TIM_CCER_CC2NE_Msk (0x1U << TIM_CCER_CC2NE_Pos) /*!< 0x00000040 */
+#define TIM_CCER_CC2NE TIM_CCER_CC2NE_Msk /*!<Capture/Compare 2 Complementary output enable */
+#define TIM_CCER_CC2NP_Pos (7U)
+#define TIM_CCER_CC2NP_Msk (0x1U << TIM_CCER_CC2NP_Pos) /*!< 0x00000080 */
+#define TIM_CCER_CC2NP TIM_CCER_CC2NP_Msk /*!<Capture/Compare 2 Complementary output Polarity */
+#define TIM_CCER_CC3E_Pos (8U)
+#define TIM_CCER_CC3E_Msk (0x1U << TIM_CCER_CC3E_Pos) /*!< 0x00000100 */
+#define TIM_CCER_CC3E TIM_CCER_CC3E_Msk /*!<Capture/Compare 3 output enable */
+#define TIM_CCER_CC3P_Pos (9U)
+#define TIM_CCER_CC3P_Msk (0x1U << TIM_CCER_CC3P_Pos) /*!< 0x00000200 */
+#define TIM_CCER_CC3P TIM_CCER_CC3P_Msk /*!<Capture/Compare 3 output Polarity */
+#define TIM_CCER_CC3NE_Pos (10U)
+#define TIM_CCER_CC3NE_Msk (0x1U << TIM_CCER_CC3NE_Pos) /*!< 0x00000400 */
+#define TIM_CCER_CC3NE TIM_CCER_CC3NE_Msk /*!<Capture/Compare 3 Complementary output enable */
+#define TIM_CCER_CC3NP_Pos (11U)
+#define TIM_CCER_CC3NP_Msk (0x1U << TIM_CCER_CC3NP_Pos) /*!< 0x00000800 */
+#define TIM_CCER_CC3NP TIM_CCER_CC3NP_Msk /*!<Capture/Compare 3 Complementary output Polarity */
+#define TIM_CCER_CC4E_Pos (12U)
+#define TIM_CCER_CC4E_Msk (0x1U << TIM_CCER_CC4E_Pos) /*!< 0x00001000 */
+#define TIM_CCER_CC4E TIM_CCER_CC4E_Msk /*!<Capture/Compare 4 output enable */
+#define TIM_CCER_CC4P_Pos (13U)
+#define TIM_CCER_CC4P_Msk (0x1U << TIM_CCER_CC4P_Pos) /*!< 0x00002000 */
+#define TIM_CCER_CC4P TIM_CCER_CC4P_Msk /*!<Capture/Compare 4 output Polarity */
+#define TIM_CCER_CC4NP_Pos (15U)
+#define TIM_CCER_CC4NP_Msk (0x1U << TIM_CCER_CC4NP_Pos) /*!< 0x00008000 */
+#define TIM_CCER_CC4NP TIM_CCER_CC4NP_Msk /*!<Capture/Compare 4 Complementary output Polarity */
+
+/******************* Bit definition for TIM_CNT register *******************/
+#define TIM_CNT_CNT_Pos (0U)
+#define TIM_CNT_CNT_Msk (0xFFFFFFFFU << TIM_CNT_CNT_Pos) /*!< 0xFFFFFFFF */
+#define TIM_CNT_CNT TIM_CNT_CNT_Msk /*!<Counter Value */
+
+/******************* Bit definition for TIM_PSC register *******************/
+#define TIM_PSC_PSC_Pos (0U)
+#define TIM_PSC_PSC_Msk (0xFFFFU << TIM_PSC_PSC_Pos) /*!< 0x0000FFFF */
+#define TIM_PSC_PSC TIM_PSC_PSC_Msk /*!<Prescaler Value */
+
+/******************* Bit definition for TIM_ARR register *******************/
+#define TIM_ARR_ARR_Pos (0U)
+#define TIM_ARR_ARR_Msk (0xFFFFFFFFU << TIM_ARR_ARR_Pos) /*!< 0xFFFFFFFF */
+#define TIM_ARR_ARR TIM_ARR_ARR_Msk /*!<actual auto-reload Value */
+
+/******************* Bit definition for TIM_RCR register *******************/
+#define TIM_RCR_REP_Pos (0U)
+#define TIM_RCR_REP_Msk (0xFFU << TIM_RCR_REP_Pos) /*!< 0x000000FF */
+#define TIM_RCR_REP TIM_RCR_REP_Msk /*!<Repetition Counter Value */
+
+/******************* Bit definition for TIM_CCR1 register ******************/
+#define TIM_CCR1_CCR1_Pos (0U)
+#define TIM_CCR1_CCR1_Msk (0xFFFFU << TIM_CCR1_CCR1_Pos) /*!< 0x0000FFFF */
+#define TIM_CCR1_CCR1 TIM_CCR1_CCR1_Msk /*!<Capture/Compare 1 Value */
+
+/******************* Bit definition for TIM_CCR2 register ******************/
+#define TIM_CCR2_CCR2_Pos (0U)
+#define TIM_CCR2_CCR2_Msk (0xFFFFU << TIM_CCR2_CCR2_Pos) /*!< 0x0000FFFF */
+#define TIM_CCR2_CCR2 TIM_CCR2_CCR2_Msk /*!<Capture/Compare 2 Value */
+
+/******************* Bit definition for TIM_CCR3 register ******************/
+#define TIM_CCR3_CCR3_Pos (0U)
+#define TIM_CCR3_CCR3_Msk (0xFFFFU << TIM_CCR3_CCR3_Pos) /*!< 0x0000FFFF */
+#define TIM_CCR3_CCR3 TIM_CCR3_CCR3_Msk /*!<Capture/Compare 3 Value */
+
+/******************* Bit definition for TIM_CCR4 register ******************/
+#define TIM_CCR4_CCR4_Pos (0U)
+#define TIM_CCR4_CCR4_Msk (0xFFFFU << TIM_CCR4_CCR4_Pos) /*!< 0x0000FFFF */
+#define TIM_CCR4_CCR4 TIM_CCR4_CCR4_Msk /*!<Capture/Compare 4 Value */
+
+/******************* Bit definition for TIM_BDTR register ******************/
+#define TIM_BDTR_DTG_Pos (0U)
+#define TIM_BDTR_DTG_Msk (0xFFU << TIM_BDTR_DTG_Pos) /*!< 0x000000FF */
+#define TIM_BDTR_DTG TIM_BDTR_DTG_Msk /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
+#define TIM_BDTR_DTG_0 (0x01U << TIM_BDTR_DTG_Pos) /*!< 0x00000001 */
+#define TIM_BDTR_DTG_1 (0x02U << TIM_BDTR_DTG_Pos) /*!< 0x00000002 */
+#define TIM_BDTR_DTG_2 (0x04U << TIM_BDTR_DTG_Pos) /*!< 0x00000004 */
+#define TIM_BDTR_DTG_3 (0x08U << TIM_BDTR_DTG_Pos) /*!< 0x00000008 */
+#define TIM_BDTR_DTG_4 (0x10U << TIM_BDTR_DTG_Pos) /*!< 0x00000010 */
+#define TIM_BDTR_DTG_5 (0x20U << TIM_BDTR_DTG_Pos) /*!< 0x00000020 */
+#define TIM_BDTR_DTG_6 (0x40U << TIM_BDTR_DTG_Pos) /*!< 0x00000040 */
+#define TIM_BDTR_DTG_7 (0x80U << TIM_BDTR_DTG_Pos) /*!< 0x00000080 */
+
+#define TIM_BDTR_LOCK_Pos (8U)
+#define TIM_BDTR_LOCK_Msk (0x3U << TIM_BDTR_LOCK_Pos) /*!< 0x00000300 */
+#define TIM_BDTR_LOCK TIM_BDTR_LOCK_Msk /*!<LOCK[1:0] bits (Lock Configuration) */
+#define TIM_BDTR_LOCK_0 (0x1U << TIM_BDTR_LOCK_Pos) /*!< 0x00000100 */
+#define TIM_BDTR_LOCK_1 (0x2U << TIM_BDTR_LOCK_Pos) /*!< 0x00000200 */
+
+#define TIM_BDTR_OSSI_Pos (10U)
+#define TIM_BDTR_OSSI_Msk (0x1U << TIM_BDTR_OSSI_Pos) /*!< 0x00000400 */
+#define TIM_BDTR_OSSI TIM_BDTR_OSSI_Msk /*!<Off-State Selection for Idle mode */
+#define TIM_BDTR_OSSR_Pos (11U)
+#define TIM_BDTR_OSSR_Msk (0x1U << TIM_BDTR_OSSR_Pos) /*!< 0x00000800 */
+#define TIM_BDTR_OSSR TIM_BDTR_OSSR_Msk /*!<Off-State Selection for Run mode */
+#define TIM_BDTR_BKE_Pos (12U)
+#define TIM_BDTR_BKE_Msk (0x1U << TIM_BDTR_BKE_Pos) /*!< 0x00001000 */
+#define TIM_BDTR_BKE TIM_BDTR_BKE_Msk /*!<Break enable */
+#define TIM_BDTR_BKP_Pos (13U)
+#define TIM_BDTR_BKP_Msk (0x1U << TIM_BDTR_BKP_Pos) /*!< 0x00002000 */
+#define TIM_BDTR_BKP TIM_BDTR_BKP_Msk /*!<Break Polarity */
+#define TIM_BDTR_AOE_Pos (14U)
+#define TIM_BDTR_AOE_Msk (0x1U << TIM_BDTR_AOE_Pos) /*!< 0x00004000 */
+#define TIM_BDTR_AOE TIM_BDTR_AOE_Msk /*!<Automatic Output enable */
+#define TIM_BDTR_MOE_Pos (15U)
+#define TIM_BDTR_MOE_Msk (0x1U << TIM_BDTR_MOE_Pos) /*!< 0x00008000 */
+#define TIM_BDTR_MOE TIM_BDTR_MOE_Msk /*!<Main Output enable */
+
+/******************* Bit definition for TIM_DCR register *******************/
+#define TIM_DCR_DBA_Pos (0U)
+#define TIM_DCR_DBA_Msk (0x1FU << TIM_DCR_DBA_Pos) /*!< 0x0000001F */
+#define TIM_DCR_DBA TIM_DCR_DBA_Msk /*!<DBA[4:0] bits (DMA Base Address) */
+#define TIM_DCR_DBA_0 (0x01U << TIM_DCR_DBA_Pos) /*!< 0x00000001 */
+#define TIM_DCR_DBA_1 (0x02U << TIM_DCR_DBA_Pos) /*!< 0x00000002 */
+#define TIM_DCR_DBA_2 (0x04U << TIM_DCR_DBA_Pos) /*!< 0x00000004 */
+#define TIM_DCR_DBA_3 (0x08U << TIM_DCR_DBA_Pos) /*!< 0x00000008 */
+#define TIM_DCR_DBA_4 (0x10U << TIM_DCR_DBA_Pos) /*!< 0x00000010 */
+
+#define TIM_DCR_DBL_Pos (8U)
+#define TIM_DCR_DBL_Msk (0x1FU << TIM_DCR_DBL_Pos) /*!< 0x00001F00 */
+#define TIM_DCR_DBL TIM_DCR_DBL_Msk /*!<DBL[4:0] bits (DMA Burst Length) */
+#define TIM_DCR_DBL_0 (0x01U << TIM_DCR_DBL_Pos) /*!< 0x00000100 */
+#define TIM_DCR_DBL_1 (0x02U << TIM_DCR_DBL_Pos) /*!< 0x00000200 */
+#define TIM_DCR_DBL_2 (0x04U << TIM_DCR_DBL_Pos) /*!< 0x00000400 */
+#define TIM_DCR_DBL_3 (0x08U << TIM_DCR_DBL_Pos) /*!< 0x00000800 */
+#define TIM_DCR_DBL_4 (0x10U << TIM_DCR_DBL_Pos) /*!< 0x00001000 */
+
+/******************* Bit definition for TIM_DMAR register ******************/
+#define TIM_DMAR_DMAB_Pos (0U)
+#define TIM_DMAR_DMAB_Msk (0xFFFFU << TIM_DMAR_DMAB_Pos) /*!< 0x0000FFFF */
+#define TIM_DMAR_DMAB TIM_DMAR_DMAB_Msk /*!<DMA register for burst accesses */
+
+/******************* Bit definition for TIM_OR register ********************/
+
+/******************************************************************************/
+/* */
+/* Real-Time Clock */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for RTC_CRH register ********************/
+#define RTC_CRH_SECIE_Pos (0U)
+#define RTC_CRH_SECIE_Msk (0x1U << RTC_CRH_SECIE_Pos) /*!< 0x00000001 */
+#define RTC_CRH_SECIE RTC_CRH_SECIE_Msk /*!< Second Interrupt Enable */
+#define RTC_CRH_ALRIE_Pos (1U)
+#define RTC_CRH_ALRIE_Msk (0x1U << RTC_CRH_ALRIE_Pos) /*!< 0x00000002 */
+#define RTC_CRH_ALRIE RTC_CRH_ALRIE_Msk /*!< Alarm Interrupt Enable */
+#define RTC_CRH_OWIE_Pos (2U)
+#define RTC_CRH_OWIE_Msk (0x1U << RTC_CRH_OWIE_Pos) /*!< 0x00000004 */
+#define RTC_CRH_OWIE RTC_CRH_OWIE_Msk /*!< OverfloW Interrupt Enable */
+
+/******************* Bit definition for RTC_CRL register ********************/
+#define RTC_CRL_SECF_Pos (0U)
+#define RTC_CRL_SECF_Msk (0x1U << RTC_CRL_SECF_Pos) /*!< 0x00000001 */
+#define RTC_CRL_SECF RTC_CRL_SECF_Msk /*!< Second Flag */
+#define RTC_CRL_ALRF_Pos (1U)
+#define RTC_CRL_ALRF_Msk (0x1U << RTC_CRL_ALRF_Pos) /*!< 0x00000002 */
+#define RTC_CRL_ALRF RTC_CRL_ALRF_Msk /*!< Alarm Flag */
+#define RTC_CRL_OWF_Pos (2U)
+#define RTC_CRL_OWF_Msk (0x1U << RTC_CRL_OWF_Pos) /*!< 0x00000004 */
+#define RTC_CRL_OWF RTC_CRL_OWF_Msk /*!< OverfloW Flag */
+#define RTC_CRL_RSF_Pos (3U)
+#define RTC_CRL_RSF_Msk (0x1U << RTC_CRL_RSF_Pos) /*!< 0x00000008 */
+#define RTC_CRL_RSF RTC_CRL_RSF_Msk /*!< Registers Synchronized Flag */
+#define RTC_CRL_CNF_Pos (4U)
+#define RTC_CRL_CNF_Msk (0x1U << RTC_CRL_CNF_Pos) /*!< 0x00000010 */
+#define RTC_CRL_CNF RTC_CRL_CNF_Msk /*!< Configuration Flag */
+#define RTC_CRL_RTOFF_Pos (5U)
+#define RTC_CRL_RTOFF_Msk (0x1U << RTC_CRL_RTOFF_Pos) /*!< 0x00000020 */
+#define RTC_CRL_RTOFF RTC_CRL_RTOFF_Msk /*!< RTC operation OFF */
+
+/******************* Bit definition for RTC_PRLH register *******************/
+#define RTC_PRLH_PRL_Pos (0U)
+#define RTC_PRLH_PRL_Msk (0xFU << RTC_PRLH_PRL_Pos) /*!< 0x0000000F */
+#define RTC_PRLH_PRL RTC_PRLH_PRL_Msk /*!< RTC Prescaler Reload Value High */
+
+/******************* Bit definition for RTC_PRLL register *******************/
+#define RTC_PRLL_PRL_Pos (0U)
+#define RTC_PRLL_PRL_Msk (0xFFFFU << RTC_PRLL_PRL_Pos) /*!< 0x0000FFFF */
+#define RTC_PRLL_PRL RTC_PRLL_PRL_Msk /*!< RTC Prescaler Reload Value Low */
+
+/******************* Bit definition for RTC_DIVH register *******************/
+#define RTC_DIVH_RTC_DIV_Pos (0U)
+#define RTC_DIVH_RTC_DIV_Msk (0xFU << RTC_DIVH_RTC_DIV_Pos) /*!< 0x0000000F */
+#define RTC_DIVH_RTC_DIV RTC_DIVH_RTC_DIV_Msk /*!< RTC Clock Divider High */
+
+/******************* Bit definition for RTC_DIVL register *******************/
+#define RTC_DIVL_RTC_DIV_Pos (0U)
+#define RTC_DIVL_RTC_DIV_Msk (0xFFFFU << RTC_DIVL_RTC_DIV_Pos) /*!< 0x0000FFFF */
+#define RTC_DIVL_RTC_DIV RTC_DIVL_RTC_DIV_Msk /*!< RTC Clock Divider Low */
+
+/******************* Bit definition for RTC_CNTH register *******************/
+#define RTC_CNTH_RTC_CNT_Pos (0U)
+#define RTC_CNTH_RTC_CNT_Msk (0xFFFFU << RTC_CNTH_RTC_CNT_Pos) /*!< 0x0000FFFF */
+#define RTC_CNTH_RTC_CNT RTC_CNTH_RTC_CNT_Msk /*!< RTC Counter High */
+
+/******************* Bit definition for RTC_CNTL register *******************/
+#define RTC_CNTL_RTC_CNT_Pos (0U)
+#define RTC_CNTL_RTC_CNT_Msk (0xFFFFU << RTC_CNTL_RTC_CNT_Pos) /*!< 0x0000FFFF */
+#define RTC_CNTL_RTC_CNT RTC_CNTL_RTC_CNT_Msk /*!< RTC Counter Low */
+
+/******************* Bit definition for RTC_ALRH register *******************/
+#define RTC_ALRH_RTC_ALR_Pos (0U)
+#define RTC_ALRH_RTC_ALR_Msk (0xFFFFU << RTC_ALRH_RTC_ALR_Pos) /*!< 0x0000FFFF */
+#define RTC_ALRH_RTC_ALR RTC_ALRH_RTC_ALR_Msk /*!< RTC Alarm High */
+
+/******************* Bit definition for RTC_ALRL register *******************/
+#define RTC_ALRL_RTC_ALR_Pos (0U)
+#define RTC_ALRL_RTC_ALR_Msk (0xFFFFU << RTC_ALRL_RTC_ALR_Pos) /*!< 0x0000FFFF */
+#define RTC_ALRL_RTC_ALR RTC_ALRL_RTC_ALR_Msk /*!< RTC Alarm Low */
+
+/******************************************************************************/
+/* */
+/* Independent WATCHDOG (IWDG) */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for IWDG_KR register ********************/
+#define IWDG_KR_KEY_Pos (0U)
+#define IWDG_KR_KEY_Msk (0xFFFFU << IWDG_KR_KEY_Pos) /*!< 0x0000FFFF */
+#define IWDG_KR_KEY IWDG_KR_KEY_Msk /*!< Key value (write only, read 0000h) */
+
+/******************* Bit definition for IWDG_PR register ********************/
+#define IWDG_PR_PR_Pos (0U)
+#define IWDG_PR_PR_Msk (0x7U << IWDG_PR_PR_Pos) /*!< 0x00000007 */
+#define IWDG_PR_PR IWDG_PR_PR_Msk /*!< PR[2:0] (Prescaler divider) */
+#define IWDG_PR_PR_0 (0x1U << IWDG_PR_PR_Pos) /*!< 0x00000001 */
+#define IWDG_PR_PR_1 (0x2U << IWDG_PR_PR_Pos) /*!< 0x00000002 */
+#define IWDG_PR_PR_2 (0x4U << IWDG_PR_PR_Pos) /*!< 0x00000004 */
+
+/******************* Bit definition for IWDG_RLR register *******************/
+#define IWDG_RLR_RL_Pos (0U)
+#define IWDG_RLR_RL_Msk (0xFFFU << IWDG_RLR_RL_Pos) /*!< 0x00000FFF */
+#define IWDG_RLR_RL IWDG_RLR_RL_Msk /*!< Watchdog counter reload value */
+
+/******************* Bit definition for IWDG_SR register ********************/
+#define IWDG_SR_PVU_Pos (0U)
+#define IWDG_SR_PVU_Msk (0x1U << IWDG_SR_PVU_Pos) /*!< 0x00000001 */
+#define IWDG_SR_PVU IWDG_SR_PVU_Msk /*!< Watchdog prescaler value update */
+#define IWDG_SR_RVU_Pos (1U)
+#define IWDG_SR_RVU_Msk (0x1U << IWDG_SR_RVU_Pos) /*!< 0x00000002 */
+#define IWDG_SR_RVU IWDG_SR_RVU_Msk /*!< Watchdog counter reload value update */
+
+/******************************************************************************/
+/* */
+/* Window WATCHDOG (WWDG) */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for WWDG_CR register ********************/
+#define WWDG_CR_T_Pos (0U)
+#define WWDG_CR_T_Msk (0x7FU << WWDG_CR_T_Pos) /*!< 0x0000007F */
+#define WWDG_CR_T WWDG_CR_T_Msk /*!< T[6:0] bits (7-Bit counter (MSB to LSB)) */
+#define WWDG_CR_T_0 (0x01U << WWDG_CR_T_Pos) /*!< 0x00000001 */
+#define WWDG_CR_T_1 (0x02U << WWDG_CR_T_Pos) /*!< 0x00000002 */
+#define WWDG_CR_T_2 (0x04U << WWDG_CR_T_Pos) /*!< 0x00000004 */
+#define WWDG_CR_T_3 (0x08U << WWDG_CR_T_Pos) /*!< 0x00000008 */
+#define WWDG_CR_T_4 (0x10U << WWDG_CR_T_Pos) /*!< 0x00000010 */
+#define WWDG_CR_T_5 (0x20U << WWDG_CR_T_Pos) /*!< 0x00000020 */
+#define WWDG_CR_T_6 (0x40U << WWDG_CR_T_Pos) /*!< 0x00000040 */
+
+/* Legacy defines */
+#define WWDG_CR_T0 WWDG_CR_T_0
+#define WWDG_CR_T1 WWDG_CR_T_1
+#define WWDG_CR_T2 WWDG_CR_T_2
+#define WWDG_CR_T3 WWDG_CR_T_3
+#define WWDG_CR_T4 WWDG_CR_T_4
+#define WWDG_CR_T5 WWDG_CR_T_5
+#define WWDG_CR_T6 WWDG_CR_T_6
+
+#define WWDG_CR_WDGA_Pos (7U)
+#define WWDG_CR_WDGA_Msk (0x1U << WWDG_CR_WDGA_Pos) /*!< 0x00000080 */
+#define WWDG_CR_WDGA WWDG_CR_WDGA_Msk /*!< Activation bit */
+
+/******************* Bit definition for WWDG_CFR register *******************/
+#define WWDG_CFR_W_Pos (0U)
+#define WWDG_CFR_W_Msk (0x7FU << WWDG_CFR_W_Pos) /*!< 0x0000007F */
+#define WWDG_CFR_W WWDG_CFR_W_Msk /*!< W[6:0] bits (7-bit window value) */
+#define WWDG_CFR_W_0 (0x01U << WWDG_CFR_W_Pos) /*!< 0x00000001 */
+#define WWDG_CFR_W_1 (0x02U << WWDG_CFR_W_Pos) /*!< 0x00000002 */
+#define WWDG_CFR_W_2 (0x04U << WWDG_CFR_W_Pos) /*!< 0x00000004 */
+#define WWDG_CFR_W_3 (0x08U << WWDG_CFR_W_Pos) /*!< 0x00000008 */
+#define WWDG_CFR_W_4 (0x10U << WWDG_CFR_W_Pos) /*!< 0x00000010 */
+#define WWDG_CFR_W_5 (0x20U << WWDG_CFR_W_Pos) /*!< 0x00000020 */
+#define WWDG_CFR_W_6 (0x40U << WWDG_CFR_W_Pos) /*!< 0x00000040 */
+
+/* Legacy defines */
+#define WWDG_CFR_W0 WWDG_CFR_W_0
+#define WWDG_CFR_W1 WWDG_CFR_W_1
+#define WWDG_CFR_W2 WWDG_CFR_W_2
+#define WWDG_CFR_W3 WWDG_CFR_W_3
+#define WWDG_CFR_W4 WWDG_CFR_W_4
+#define WWDG_CFR_W5 WWDG_CFR_W_5
+#define WWDG_CFR_W6 WWDG_CFR_W_6
+
+#define WWDG_CFR_WDGTB_Pos (7U)
+#define WWDG_CFR_WDGTB_Msk (0x3U << WWDG_CFR_WDGTB_Pos) /*!< 0x00000180 */
+#define WWDG_CFR_WDGTB WWDG_CFR_WDGTB_Msk /*!< WDGTB[1:0] bits (Timer Base) */
+#define WWDG_CFR_WDGTB_0 (0x1U << WWDG_CFR_WDGTB_Pos) /*!< 0x00000080 */
+#define WWDG_CFR_WDGTB_1 (0x2U << WWDG_CFR_WDGTB_Pos) /*!< 0x00000100 */
+
+/* Legacy defines */
+#define WWDG_CFR_WDGTB0 WWDG_CFR_WDGTB_0
+#define WWDG_CFR_WDGTB1 WWDG_CFR_WDGTB_1
+
+#define WWDG_CFR_EWI_Pos (9U)
+#define WWDG_CFR_EWI_Msk (0x1U << WWDG_CFR_EWI_Pos) /*!< 0x00000200 */
+#define WWDG_CFR_EWI WWDG_CFR_EWI_Msk /*!< Early Wakeup Interrupt */
+
+/******************* Bit definition for WWDG_SR register ********************/
+#define WWDG_SR_EWIF_Pos (0U)
+#define WWDG_SR_EWIF_Msk (0x1U << WWDG_SR_EWIF_Pos) /*!< 0x00000001 */
+#define WWDG_SR_EWIF WWDG_SR_EWIF_Msk /*!< Early Wakeup Interrupt Flag */
+
+/******************************************************************************/
+/* */
+/* Flexible Static Memory Controller */
+/* */
+/******************************************************************************/
+
+/****************** Bit definition for FSMC_BCRx (x=1..4) register **********/
+#define FSMC_BCRx_MBKEN_Pos (0U)
+#define FSMC_BCRx_MBKEN_Msk (0x1U << FSMC_BCRx_MBKEN_Pos) /*!< 0x00000001 */
+#define FSMC_BCRx_MBKEN FSMC_BCRx_MBKEN_Msk /*!< Memory bank enable bit */
+#define FSMC_BCRx_MUXEN_Pos (1U)
+#define FSMC_BCRx_MUXEN_Msk (0x1U << FSMC_BCRx_MUXEN_Pos) /*!< 0x00000002 */
+#define FSMC_BCRx_MUXEN FSMC_BCRx_MUXEN_Msk /*!< Address/data multiplexing enable bit */
+
+#define FSMC_BCRx_MTYP_Pos (2U)
+#define FSMC_BCRx_MTYP_Msk (0x3U << FSMC_BCRx_MTYP_Pos) /*!< 0x0000000C */
+#define FSMC_BCRx_MTYP FSMC_BCRx_MTYP_Msk /*!< MTYP[1:0] bits (Memory type) */
+#define FSMC_BCRx_MTYP_0 (0x1U << FSMC_BCRx_MTYP_Pos) /*!< 0x00000004 */
+#define FSMC_BCRx_MTYP_1 (0x2U << FSMC_BCRx_MTYP_Pos) /*!< 0x00000008 */
+
+#define FSMC_BCRx_MWID_Pos (4U)
+#define FSMC_BCRx_MWID_Msk (0x3U << FSMC_BCRx_MWID_Pos) /*!< 0x00000030 */
+#define FSMC_BCRx_MWID FSMC_BCRx_MWID_Msk /*!< MWID[1:0] bits (Memory data bus width) */
+#define FSMC_BCRx_MWID_0 (0x1U << FSMC_BCRx_MWID_Pos) /*!< 0x00000010 */
+#define FSMC_BCRx_MWID_1 (0x2U << FSMC_BCRx_MWID_Pos) /*!< 0x00000020 */
+
+#define FSMC_BCRx_FACCEN_Pos (6U)
+#define FSMC_BCRx_FACCEN_Msk (0x1U << FSMC_BCRx_FACCEN_Pos) /*!< 0x00000040 */
+#define FSMC_BCRx_FACCEN FSMC_BCRx_FACCEN_Msk /*!< Flash access enable */
+#define FSMC_BCRx_BURSTEN_Pos (8U)
+#define FSMC_BCRx_BURSTEN_Msk (0x1U << FSMC_BCRx_BURSTEN_Pos) /*!< 0x00000100 */
+#define FSMC_BCRx_BURSTEN FSMC_BCRx_BURSTEN_Msk /*!< Burst enable bit */
+#define FSMC_BCRx_WAITPOL_Pos (9U)
+#define FSMC_BCRx_WAITPOL_Msk (0x1U << FSMC_BCRx_WAITPOL_Pos) /*!< 0x00000200 */
+#define FSMC_BCRx_WAITPOL FSMC_BCRx_WAITPOL_Msk /*!< Wait signal polarity bit */
+#define FSMC_BCRx_WRAPMOD_Pos (10U)
+#define FSMC_BCRx_WRAPMOD_Msk (0x1U << FSMC_BCRx_WRAPMOD_Pos) /*!< 0x00000400 */
+#define FSMC_BCRx_WRAPMOD FSMC_BCRx_WRAPMOD_Msk /*!< Wrapped burst mode support */
+#define FSMC_BCRx_WAITCFG_Pos (11U)
+#define FSMC_BCRx_WAITCFG_Msk (0x1U << FSMC_BCRx_WAITCFG_Pos) /*!< 0x00000800 */
+#define FSMC_BCRx_WAITCFG FSMC_BCRx_WAITCFG_Msk /*!< Wait timing configuration */
+#define FSMC_BCRx_WREN_Pos (12U)
+#define FSMC_BCRx_WREN_Msk (0x1U << FSMC_BCRx_WREN_Pos) /*!< 0x00001000 */
+#define FSMC_BCRx_WREN FSMC_BCRx_WREN_Msk /*!< Write enable bit */
+#define FSMC_BCRx_WAITEN_Pos (13U)
+#define FSMC_BCRx_WAITEN_Msk (0x1U << FSMC_BCRx_WAITEN_Pos) /*!< 0x00002000 */
+#define FSMC_BCRx_WAITEN FSMC_BCRx_WAITEN_Msk /*!< Wait enable bit */
+#define FSMC_BCRx_EXTMOD_Pos (14U)
+#define FSMC_BCRx_EXTMOD_Msk (0x1U << FSMC_BCRx_EXTMOD_Pos) /*!< 0x00004000 */
+#define FSMC_BCRx_EXTMOD FSMC_BCRx_EXTMOD_Msk /*!< Extended mode enable */
+#define FSMC_BCRx_ASYNCWAIT_Pos (15U)
+#define FSMC_BCRx_ASYNCWAIT_Msk (0x1U << FSMC_BCRx_ASYNCWAIT_Pos) /*!< 0x00008000 */
+#define FSMC_BCRx_ASYNCWAIT FSMC_BCRx_ASYNCWAIT_Msk /*!< Asynchronous wait */
+#define FSMC_BCRx_CBURSTRW_Pos (19U)
+#define FSMC_BCRx_CBURSTRW_Msk (0x1U << FSMC_BCRx_CBURSTRW_Pos) /*!< 0x00080000 */
+#define FSMC_BCRx_CBURSTRW FSMC_BCRx_CBURSTRW_Msk /*!< Write burst enable */
+
+/****************** Bit definition for FSMC_BTRx (x=1..4) register ******/
+#define FSMC_BTRx_ADDSET_Pos (0U)
+#define FSMC_BTRx_ADDSET_Msk (0xFU << FSMC_BTRx_ADDSET_Pos) /*!< 0x0000000F */
+#define FSMC_BTRx_ADDSET FSMC_BTRx_ADDSET_Msk /*!< ADDSET[3:0] bits (Address setup phase duration) */
+#define FSMC_BTRx_ADDSET_0 (0x1U << FSMC_BTRx_ADDSET_Pos) /*!< 0x00000001 */
+#define FSMC_BTRx_ADDSET_1 (0x2U << FSMC_BTRx_ADDSET_Pos) /*!< 0x00000002 */
+#define FSMC_BTRx_ADDSET_2 (0x4U << FSMC_BTRx_ADDSET_Pos) /*!< 0x00000004 */
+#define FSMC_BTRx_ADDSET_3 (0x8U << FSMC_BTRx_ADDSET_Pos) /*!< 0x00000008 */
+
+#define FSMC_BTRx_ADDHLD_Pos (4U)
+#define FSMC_BTRx_ADDHLD_Msk (0xFU << FSMC_BTRx_ADDHLD_Pos) /*!< 0x000000F0 */
+#define FSMC_BTRx_ADDHLD FSMC_BTRx_ADDHLD_Msk /*!< ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FSMC_BTRx_ADDHLD_0 (0x1U << FSMC_BTRx_ADDHLD_Pos) /*!< 0x00000010 */
+#define FSMC_BTRx_ADDHLD_1 (0x2U << FSMC_BTRx_ADDHLD_Pos) /*!< 0x00000020 */
+#define FSMC_BTRx_ADDHLD_2 (0x4U << FSMC_BTRx_ADDHLD_Pos) /*!< 0x00000040 */
+#define FSMC_BTRx_ADDHLD_3 (0x8U << FSMC_BTRx_ADDHLD_Pos) /*!< 0x00000080 */
+
+#define FSMC_BTRx_DATAST_Pos (8U)
+#define FSMC_BTRx_DATAST_Msk (0xFFU << FSMC_BTRx_DATAST_Pos) /*!< 0x0000FF00 */
+#define FSMC_BTRx_DATAST FSMC_BTRx_DATAST_Msk /*!< DATAST [3:0] bits (Data-phase duration) */
+#define FSMC_BTRx_DATAST_0 (0x01U << FSMC_BTRx_DATAST_Pos) /*!< 0x00000100 */
+#define FSMC_BTRx_DATAST_1 (0x02U << FSMC_BTRx_DATAST_Pos) /*!< 0x00000200 */
+#define FSMC_BTRx_DATAST_2 (0x04U << FSMC_BTRx_DATAST_Pos) /*!< 0x00000400 */
+#define FSMC_BTRx_DATAST_3 (0x08U << FSMC_BTRx_DATAST_Pos) /*!< 0x00000800 */
+#define FSMC_BTRx_DATAST_4 (0x10U << FSMC_BTRx_DATAST_Pos) /*!< 0x00001000 */
+#define FSMC_BTRx_DATAST_5 (0x20U << FSMC_BTRx_DATAST_Pos) /*!< 0x00002000 */
+#define FSMC_BTRx_DATAST_6 (0x40U << FSMC_BTRx_DATAST_Pos) /*!< 0x00004000 */
+#define FSMC_BTRx_DATAST_7 (0x80U << FSMC_BTRx_DATAST_Pos) /*!< 0x00008000 */
+
+#define FSMC_BTRx_BUSTURN_Pos (16U)
+#define FSMC_BTRx_BUSTURN_Msk (0xFU << FSMC_BTRx_BUSTURN_Pos) /*!< 0x000F0000 */
+#define FSMC_BTRx_BUSTURN FSMC_BTRx_BUSTURN_Msk /*!< BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define FSMC_BTRx_BUSTURN_0 (0x1U << FSMC_BTRx_BUSTURN_Pos) /*!< 0x00010000 */
+#define FSMC_BTRx_BUSTURN_1 (0x2U << FSMC_BTRx_BUSTURN_Pos) /*!< 0x00020000 */
+#define FSMC_BTRx_BUSTURN_2 (0x4U << FSMC_BTRx_BUSTURN_Pos) /*!< 0x00040000 */
+#define FSMC_BTRx_BUSTURN_3 (0x8U << FSMC_BTRx_BUSTURN_Pos) /*!< 0x00080000 */
+
+#define FSMC_BTRx_CLKDIV_Pos (20U)
+#define FSMC_BTRx_CLKDIV_Msk (0xFU << FSMC_BTRx_CLKDIV_Pos) /*!< 0x00F00000 */
+#define FSMC_BTRx_CLKDIV FSMC_BTRx_CLKDIV_Msk /*!< CLKDIV[3:0] bits (Clock divide ratio) */
+#define FSMC_BTRx_CLKDIV_0 (0x1U << FSMC_BTRx_CLKDIV_Pos) /*!< 0x00100000 */
+#define FSMC_BTRx_CLKDIV_1 (0x2U << FSMC_BTRx_CLKDIV_Pos) /*!< 0x00200000 */
+#define FSMC_BTRx_CLKDIV_2 (0x4U << FSMC_BTRx_CLKDIV_Pos) /*!< 0x00400000 */
+#define FSMC_BTRx_CLKDIV_3 (0x8U << FSMC_BTRx_CLKDIV_Pos) /*!< 0x00800000 */
+
+#define FSMC_BTRx_DATLAT_Pos (24U)
+#define FSMC_BTRx_DATLAT_Msk (0xFU << FSMC_BTRx_DATLAT_Pos) /*!< 0x0F000000 */
+#define FSMC_BTRx_DATLAT FSMC_BTRx_DATLAT_Msk /*!< DATLA[3:0] bits (Data latency) */
+#define FSMC_BTRx_DATLAT_0 (0x1U << FSMC_BTRx_DATLAT_Pos) /*!< 0x01000000 */
+#define FSMC_BTRx_DATLAT_1 (0x2U << FSMC_BTRx_DATLAT_Pos) /*!< 0x02000000 */
+#define FSMC_BTRx_DATLAT_2 (0x4U << FSMC_BTRx_DATLAT_Pos) /*!< 0x04000000 */
+#define FSMC_BTRx_DATLAT_3 (0x8U << FSMC_BTRx_DATLAT_Pos) /*!< 0x08000000 */
+
+#define FSMC_BTRx_ACCMOD_Pos (28U)
+#define FSMC_BTRx_ACCMOD_Msk (0x3U << FSMC_BTRx_ACCMOD_Pos) /*!< 0x30000000 */
+#define FSMC_BTRx_ACCMOD FSMC_BTRx_ACCMOD_Msk /*!< ACCMOD[1:0] bits (Access mode) */
+#define FSMC_BTRx_ACCMOD_0 (0x1U << FSMC_BTRx_ACCMOD_Pos) /*!< 0x10000000 */
+#define FSMC_BTRx_ACCMOD_1 (0x2U << FSMC_BTRx_ACCMOD_Pos) /*!< 0x20000000 */
+
+/****************** Bit definition for FSMC_BWTRx (x=1..4) register ******/
+#define FSMC_BWTRx_ADDSET_Pos (0U)
+#define FSMC_BWTRx_ADDSET_Msk (0xFU << FSMC_BWTRx_ADDSET_Pos) /*!< 0x0000000F */
+#define FSMC_BWTRx_ADDSET FSMC_BWTRx_ADDSET_Msk /*!< ADDSET[3:0] bits (Address setup phase duration) */
+#define FSMC_BWTRx_ADDSET_0 (0x1U << FSMC_BWTRx_ADDSET_Pos) /*!< 0x00000001 */
+#define FSMC_BWTRx_ADDSET_1 (0x2U << FSMC_BWTRx_ADDSET_Pos) /*!< 0x00000002 */
+#define FSMC_BWTRx_ADDSET_2 (0x4U << FSMC_BWTRx_ADDSET_Pos) /*!< 0x00000004 */
+#define FSMC_BWTRx_ADDSET_3 (0x8U << FSMC_BWTRx_ADDSET_Pos) /*!< 0x00000008 */
+
+#define FSMC_BWTRx_ADDHLD_Pos (4U)
+#define FSMC_BWTRx_ADDHLD_Msk (0xFU << FSMC_BWTRx_ADDHLD_Pos) /*!< 0x000000F0 */
+#define FSMC_BWTRx_ADDHLD FSMC_BWTRx_ADDHLD_Msk /*!< ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FSMC_BWTRx_ADDHLD_0 (0x1U << FSMC_BWTRx_ADDHLD_Pos) /*!< 0x00000010 */
+#define FSMC_BWTRx_ADDHLD_1 (0x2U << FSMC_BWTRx_ADDHLD_Pos) /*!< 0x00000020 */
+#define FSMC_BWTRx_ADDHLD_2 (0x4U << FSMC_BWTRx_ADDHLD_Pos) /*!< 0x00000040 */
+#define FSMC_BWTRx_ADDHLD_3 (0x8U << FSMC_BWTRx_ADDHLD_Pos) /*!< 0x00000080 */
+
+#define FSMC_BWTRx_DATAST_Pos (8U)
+#define FSMC_BWTRx_DATAST_Msk (0xFFU << FSMC_BWTRx_DATAST_Pos) /*!< 0x0000FF00 */
+#define FSMC_BWTRx_DATAST FSMC_BWTRx_DATAST_Msk /*!< DATAST [3:0] bits (Data-phase duration) */
+#define FSMC_BWTRx_DATAST_0 (0x01U << FSMC_BWTRx_DATAST_Pos) /*!< 0x00000100 */
+#define FSMC_BWTRx_DATAST_1 (0x02U << FSMC_BWTRx_DATAST_Pos) /*!< 0x00000200 */
+#define FSMC_BWTRx_DATAST_2 (0x04U << FSMC_BWTRx_DATAST_Pos) /*!< 0x00000400 */
+#define FSMC_BWTRx_DATAST_3 (0x08U << FSMC_BWTRx_DATAST_Pos) /*!< 0x00000800 */
+#define FSMC_BWTRx_DATAST_4 (0x10U << FSMC_BWTRx_DATAST_Pos) /*!< 0x00001000 */
+#define FSMC_BWTRx_DATAST_5 (0x20U << FSMC_BWTRx_DATAST_Pos) /*!< 0x00002000 */
+#define FSMC_BWTRx_DATAST_6 (0x40U << FSMC_BWTRx_DATAST_Pos) /*!< 0x00004000 */
+#define FSMC_BWTRx_DATAST_7 (0x80U << FSMC_BWTRx_DATAST_Pos) /*!< 0x00008000 */
+
+#define FSMC_BWTRx_CLKDIV_Pos (20U)
+#define FSMC_BWTRx_CLKDIV_Msk (0xFU << FSMC_BWTRx_CLKDIV_Pos) /*!< 0x00F00000 */
+#define FSMC_BWTRx_CLKDIV FSMC_BWTRx_CLKDIV_Msk /*!< CLKDIV[3:0] bits (Clock divide ratio) */
+#define FSMC_BWTRx_CLKDIV_0 (0x1U << FSMC_BWTRx_CLKDIV_Pos) /*!< 0x00100000 */
+#define FSMC_BWTRx_CLKDIV_1 (0x2U << FSMC_BWTRx_CLKDIV_Pos) /*!< 0x00200000 */
+#define FSMC_BWTRx_CLKDIV_2 (0x4U << FSMC_BWTRx_CLKDIV_Pos) /*!< 0x00400000 */
+#define FSMC_BWTRx_CLKDIV_3 (0x8U << FSMC_BWTRx_CLKDIV_Pos) /*!< 0x00800000 */
+
+#define FSMC_BWTRx_DATLAT_Pos (24U)
+#define FSMC_BWTRx_DATLAT_Msk (0xFU << FSMC_BWTRx_DATLAT_Pos) /*!< 0x0F000000 */
+#define FSMC_BWTRx_DATLAT FSMC_BWTRx_DATLAT_Msk /*!< DATLA[3:0] bits (Data latency) */
+#define FSMC_BWTRx_DATLAT_0 (0x1U << FSMC_BWTRx_DATLAT_Pos) /*!< 0x01000000 */
+#define FSMC_BWTRx_DATLAT_1 (0x2U << FSMC_BWTRx_DATLAT_Pos) /*!< 0x02000000 */
+#define FSMC_BWTRx_DATLAT_2 (0x4U << FSMC_BWTRx_DATLAT_Pos) /*!< 0x04000000 */
+#define FSMC_BWTRx_DATLAT_3 (0x8U << FSMC_BWTRx_DATLAT_Pos) /*!< 0x08000000 */
+
+#define FSMC_BWTRx_ACCMOD_Pos (28U)
+#define FSMC_BWTRx_ACCMOD_Msk (0x3U << FSMC_BWTRx_ACCMOD_Pos) /*!< 0x30000000 */
+#define FSMC_BWTRx_ACCMOD FSMC_BWTRx_ACCMOD_Msk /*!< ACCMOD[1:0] bits (Access mode) */
+#define FSMC_BWTRx_ACCMOD_0 (0x1U << FSMC_BWTRx_ACCMOD_Pos) /*!< 0x10000000 */
+#define FSMC_BWTRx_ACCMOD_1 (0x2U << FSMC_BWTRx_ACCMOD_Pos) /*!< 0x20000000 */
+
+
+/******************************************************************************/
+/* */
+/* SD host Interface */
+/* */
+/******************************************************************************/
+
+/****************** Bit definition for SDIO_POWER register ******************/
+#define SDIO_POWER_PWRCTRL_Pos (0U)
+#define SDIO_POWER_PWRCTRL_Msk (0x3U << SDIO_POWER_PWRCTRL_Pos) /*!< 0x00000003 */
+#define SDIO_POWER_PWRCTRL SDIO_POWER_PWRCTRL_Msk /*!< PWRCTRL[1:0] bits (Power supply control bits) */
+#define SDIO_POWER_PWRCTRL_0 (0x1U << SDIO_POWER_PWRCTRL_Pos) /*!< 0x01 */
+#define SDIO_POWER_PWRCTRL_1 (0x2U << SDIO_POWER_PWRCTRL_Pos) /*!< 0x02 */
+
+/****************** Bit definition for SDIO_CLKCR register ******************/
+#define SDIO_CLKCR_CLKDIV_Pos (0U)
+#define SDIO_CLKCR_CLKDIV_Msk (0xFFU << SDIO_CLKCR_CLKDIV_Pos) /*!< 0x000000FF */
+#define SDIO_CLKCR_CLKDIV SDIO_CLKCR_CLKDIV_Msk /*!< Clock divide factor */
+#define SDIO_CLKCR_CLKEN_Pos (8U)
+#define SDIO_CLKCR_CLKEN_Msk (0x1U << SDIO_CLKCR_CLKEN_Pos) /*!< 0x00000100 */
+#define SDIO_CLKCR_CLKEN SDIO_CLKCR_CLKEN_Msk /*!< Clock enable bit */
+#define SDIO_CLKCR_PWRSAV_Pos (9U)
+#define SDIO_CLKCR_PWRSAV_Msk (0x1U << SDIO_CLKCR_PWRSAV_Pos) /*!< 0x00000200 */
+#define SDIO_CLKCR_PWRSAV SDIO_CLKCR_PWRSAV_Msk /*!< Power saving configuration bit */
+#define SDIO_CLKCR_BYPASS_Pos (10U)
+#define SDIO_CLKCR_BYPASS_Msk (0x1U << SDIO_CLKCR_BYPASS_Pos) /*!< 0x00000400 */
+#define SDIO_CLKCR_BYPASS SDIO_CLKCR_BYPASS_Msk /*!< Clock divider bypass enable bit */
+
+#define SDIO_CLKCR_WIDBUS_Pos (11U)
+#define SDIO_CLKCR_WIDBUS_Msk (0x3U << SDIO_CLKCR_WIDBUS_Pos) /*!< 0x00001800 */
+#define SDIO_CLKCR_WIDBUS SDIO_CLKCR_WIDBUS_Msk /*!< WIDBUS[1:0] bits (Wide bus mode enable bit) */
+#define SDIO_CLKCR_WIDBUS_0 (0x1U << SDIO_CLKCR_WIDBUS_Pos) /*!< 0x0800 */
+#define SDIO_CLKCR_WIDBUS_1 (0x2U << SDIO_CLKCR_WIDBUS_Pos) /*!< 0x1000 */
+
+#define SDIO_CLKCR_NEGEDGE_Pos (13U)
+#define SDIO_CLKCR_NEGEDGE_Msk (0x1U << SDIO_CLKCR_NEGEDGE_Pos) /*!< 0x00002000 */
+#define SDIO_CLKCR_NEGEDGE SDIO_CLKCR_NEGEDGE_Msk /*!< SDIO_CK dephasing selection bit */
+#define SDIO_CLKCR_HWFC_EN_Pos (14U)
+#define SDIO_CLKCR_HWFC_EN_Msk (0x1U << SDIO_CLKCR_HWFC_EN_Pos) /*!< 0x00004000 */
+#define SDIO_CLKCR_HWFC_EN SDIO_CLKCR_HWFC_EN_Msk /*!< HW Flow Control enable */
+
+/******************* Bit definition for SDIO_ARG register *******************/
+#define SDIO_ARG_CMDARG_Pos (0U)
+#define SDIO_ARG_CMDARG_Msk (0xFFFFFFFFU << SDIO_ARG_CMDARG_Pos) /*!< 0xFFFFFFFF */
+#define SDIO_ARG_CMDARG SDIO_ARG_CMDARG_Msk /*!< Command argument */
+
+/******************* Bit definition for SDIO_CMD register *******************/
+#define SDIO_CMD_CMDINDEX_Pos (0U)
+#define SDIO_CMD_CMDINDEX_Msk (0x3FU << SDIO_CMD_CMDINDEX_Pos) /*!< 0x0000003F */
+#define SDIO_CMD_CMDINDEX SDIO_CMD_CMDINDEX_Msk /*!< Command Index */
+
+#define SDIO_CMD_WAITRESP_Pos (6U)
+#define SDIO_CMD_WAITRESP_Msk (0x3U << SDIO_CMD_WAITRESP_Pos) /*!< 0x000000C0 */
+#define SDIO_CMD_WAITRESP SDIO_CMD_WAITRESP_Msk /*!< WAITRESP[1:0] bits (Wait for response bits) */
+#define SDIO_CMD_WAITRESP_0 (0x1U << SDIO_CMD_WAITRESP_Pos) /*!< 0x0040 */
+#define SDIO_CMD_WAITRESP_1 (0x2U << SDIO_CMD_WAITRESP_Pos) /*!< 0x0080 */
+
+#define SDIO_CMD_WAITINT_Pos (8U)
+#define SDIO_CMD_WAITINT_Msk (0x1U << SDIO_CMD_WAITINT_Pos) /*!< 0x00000100 */
+#define SDIO_CMD_WAITINT SDIO_CMD_WAITINT_Msk /*!< CPSM Waits for Interrupt Request */
+#define SDIO_CMD_WAITPEND_Pos (9U)
+#define SDIO_CMD_WAITPEND_Msk (0x1U << SDIO_CMD_WAITPEND_Pos) /*!< 0x00000200 */
+#define SDIO_CMD_WAITPEND SDIO_CMD_WAITPEND_Msk /*!< CPSM Waits for ends of data transfer (CmdPend internal signal) */
+#define SDIO_CMD_CPSMEN_Pos (10U)
+#define SDIO_CMD_CPSMEN_Msk (0x1U << SDIO_CMD_CPSMEN_Pos) /*!< 0x00000400 */
+#define SDIO_CMD_CPSMEN SDIO_CMD_CPSMEN_Msk /*!< Command path state machine (CPSM) Enable bit */
+#define SDIO_CMD_SDIOSUSPEND_Pos (11U)
+#define SDIO_CMD_SDIOSUSPEND_Msk (0x1U << SDIO_CMD_SDIOSUSPEND_Pos) /*!< 0x00000800 */
+#define SDIO_CMD_SDIOSUSPEND SDIO_CMD_SDIOSUSPEND_Msk /*!< SD I/O suspend command */
+#define SDIO_CMD_ENCMDCOMPL_Pos (12U)
+#define SDIO_CMD_ENCMDCOMPL_Msk (0x1U << SDIO_CMD_ENCMDCOMPL_Pos) /*!< 0x00001000 */
+#define SDIO_CMD_ENCMDCOMPL SDIO_CMD_ENCMDCOMPL_Msk /*!< Enable CMD completion */
+#define SDIO_CMD_NIEN_Pos (13U)
+#define SDIO_CMD_NIEN_Msk (0x1U << SDIO_CMD_NIEN_Pos) /*!< 0x00002000 */
+#define SDIO_CMD_NIEN SDIO_CMD_NIEN_Msk /*!< Not Interrupt Enable */
+#define SDIO_CMD_CEATACMD_Pos (14U)
+#define SDIO_CMD_CEATACMD_Msk (0x1U << SDIO_CMD_CEATACMD_Pos) /*!< 0x00004000 */
+#define SDIO_CMD_CEATACMD SDIO_CMD_CEATACMD_Msk /*!< CE-ATA command */
+
+/***************** Bit definition for SDIO_RESPCMD register *****************/
+#define SDIO_RESPCMD_RESPCMD_Pos (0U)
+#define SDIO_RESPCMD_RESPCMD_Msk (0x3FU << SDIO_RESPCMD_RESPCMD_Pos) /*!< 0x0000003F */
+#define SDIO_RESPCMD_RESPCMD SDIO_RESPCMD_RESPCMD_Msk /*!< Response command index */
+
+/****************** Bit definition for SDIO_RESP0 register ******************/
+#define SDIO_RESP0_CARDSTATUS0_Pos (0U)
+#define SDIO_RESP0_CARDSTATUS0_Msk (0xFFFFFFFFU << SDIO_RESP0_CARDSTATUS0_Pos) /*!< 0xFFFFFFFF */
+#define SDIO_RESP0_CARDSTATUS0 SDIO_RESP0_CARDSTATUS0_Msk /*!< Card Status */
+
+/****************** Bit definition for SDIO_RESP1 register ******************/
+#define SDIO_RESP1_CARDSTATUS1_Pos (0U)
+#define SDIO_RESP1_CARDSTATUS1_Msk (0xFFFFFFFFU << SDIO_RESP1_CARDSTATUS1_Pos) /*!< 0xFFFFFFFF */
+#define SDIO_RESP1_CARDSTATUS1 SDIO_RESP1_CARDSTATUS1_Msk /*!< Card Status */
+
+/****************** Bit definition for SDIO_RESP2 register ******************/
+#define SDIO_RESP2_CARDSTATUS2_Pos (0U)
+#define SDIO_RESP2_CARDSTATUS2_Msk (0xFFFFFFFFU << SDIO_RESP2_CARDSTATUS2_Pos) /*!< 0xFFFFFFFF */
+#define SDIO_RESP2_CARDSTATUS2 SDIO_RESP2_CARDSTATUS2_Msk /*!< Card Status */
+
+/****************** Bit definition for SDIO_RESP3 register ******************/
+#define SDIO_RESP3_CARDSTATUS3_Pos (0U)
+#define SDIO_RESP3_CARDSTATUS3_Msk (0xFFFFFFFFU << SDIO_RESP3_CARDSTATUS3_Pos) /*!< 0xFFFFFFFF */
+#define SDIO_RESP3_CARDSTATUS3 SDIO_RESP3_CARDSTATUS3_Msk /*!< Card Status */
+
+/****************** Bit definition for SDIO_RESP4 register ******************/
+#define SDIO_RESP4_CARDSTATUS4_Pos (0U)
+#define SDIO_RESP4_CARDSTATUS4_Msk (0xFFFFFFFFU << SDIO_RESP4_CARDSTATUS4_Pos) /*!< 0xFFFFFFFF */
+#define SDIO_RESP4_CARDSTATUS4 SDIO_RESP4_CARDSTATUS4_Msk /*!< Card Status */
+
+/****************** Bit definition for SDIO_DTIMER register *****************/
+#define SDIO_DTIMER_DATATIME_Pos (0U)
+#define SDIO_DTIMER_DATATIME_Msk (0xFFFFFFFFU << SDIO_DTIMER_DATATIME_Pos) /*!< 0xFFFFFFFF */
+#define SDIO_DTIMER_DATATIME SDIO_DTIMER_DATATIME_Msk /*!< Data timeout period. */
+
+/****************** Bit definition for SDIO_DLEN register *******************/
+#define SDIO_DLEN_DATALENGTH_Pos (0U)
+#define SDIO_DLEN_DATALENGTH_Msk (0x1FFFFFFU << SDIO_DLEN_DATALENGTH_Pos) /*!< 0x01FFFFFF */
+#define SDIO_DLEN_DATALENGTH SDIO_DLEN_DATALENGTH_Msk /*!< Data length value */
+
+/****************** Bit definition for SDIO_DCTRL register ******************/
+#define SDIO_DCTRL_DTEN_Pos (0U)
+#define SDIO_DCTRL_DTEN_Msk (0x1U << SDIO_DCTRL_DTEN_Pos) /*!< 0x00000001 */
+#define SDIO_DCTRL_DTEN SDIO_DCTRL_DTEN_Msk /*!< Data transfer enabled bit */
+#define SDIO_DCTRL_DTDIR_Pos (1U)
+#define SDIO_DCTRL_DTDIR_Msk (0x1U << SDIO_DCTRL_DTDIR_Pos) /*!< 0x00000002 */
+#define SDIO_DCTRL_DTDIR SDIO_DCTRL_DTDIR_Msk /*!< Data transfer direction selection */
+#define SDIO_DCTRL_DTMODE_Pos (2U)
+#define SDIO_DCTRL_DTMODE_Msk (0x1U << SDIO_DCTRL_DTMODE_Pos) /*!< 0x00000004 */
+#define SDIO_DCTRL_DTMODE SDIO_DCTRL_DTMODE_Msk /*!< Data transfer mode selection */
+#define SDIO_DCTRL_DMAEN_Pos (3U)
+#define SDIO_DCTRL_DMAEN_Msk (0x1U << SDIO_DCTRL_DMAEN_Pos) /*!< 0x00000008 */
+#define SDIO_DCTRL_DMAEN SDIO_DCTRL_DMAEN_Msk /*!< DMA enabled bit */
+
+#define SDIO_DCTRL_DBLOCKSIZE_Pos (4U)
+#define SDIO_DCTRL_DBLOCKSIZE_Msk (0xFU << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x000000F0 */
+#define SDIO_DCTRL_DBLOCKSIZE SDIO_DCTRL_DBLOCKSIZE_Msk /*!< DBLOCKSIZE[3:0] bits (Data block size) */
+#define SDIO_DCTRL_DBLOCKSIZE_0 (0x1U << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0010 */
+#define SDIO_DCTRL_DBLOCKSIZE_1 (0x2U << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0020 */
+#define SDIO_DCTRL_DBLOCKSIZE_2 (0x4U << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0040 */
+#define SDIO_DCTRL_DBLOCKSIZE_3 (0x8U << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0080 */
+
+#define SDIO_DCTRL_RWSTART_Pos (8U)
+#define SDIO_DCTRL_RWSTART_Msk (0x1U << SDIO_DCTRL_RWSTART_Pos) /*!< 0x00000100 */
+#define SDIO_DCTRL_RWSTART SDIO_DCTRL_RWSTART_Msk /*!< Read wait start */
+#define SDIO_DCTRL_RWSTOP_Pos (9U)
+#define SDIO_DCTRL_RWSTOP_Msk (0x1U << SDIO_DCTRL_RWSTOP_Pos) /*!< 0x00000200 */
+#define SDIO_DCTRL_RWSTOP SDIO_DCTRL_RWSTOP_Msk /*!< Read wait stop */
+#define SDIO_DCTRL_RWMOD_Pos (10U)
+#define SDIO_DCTRL_RWMOD_Msk (0x1U << SDIO_DCTRL_RWMOD_Pos) /*!< 0x00000400 */
+#define SDIO_DCTRL_RWMOD SDIO_DCTRL_RWMOD_Msk /*!< Read wait mode */
+#define SDIO_DCTRL_SDIOEN_Pos (11U)
+#define SDIO_DCTRL_SDIOEN_Msk (0x1U << SDIO_DCTRL_SDIOEN_Pos) /*!< 0x00000800 */
+#define SDIO_DCTRL_SDIOEN SDIO_DCTRL_SDIOEN_Msk /*!< SD I/O enable functions */
+
+/****************** Bit definition for SDIO_DCOUNT register *****************/
+#define SDIO_DCOUNT_DATACOUNT_Pos (0U)
+#define SDIO_DCOUNT_DATACOUNT_Msk (0x1FFFFFFU << SDIO_DCOUNT_DATACOUNT_Pos) /*!< 0x01FFFFFF */
+#define SDIO_DCOUNT_DATACOUNT SDIO_DCOUNT_DATACOUNT_Msk /*!< Data count value */
+
+/****************** Bit definition for SDIO_STA register ********************/
+#define SDIO_STA_CCRCFAIL_Pos (0U)
+#define SDIO_STA_CCRCFAIL_Msk (0x1U << SDIO_STA_CCRCFAIL_Pos) /*!< 0x00000001 */
+#define SDIO_STA_CCRCFAIL SDIO_STA_CCRCFAIL_Msk /*!< Command response received (CRC check failed) */
+#define SDIO_STA_DCRCFAIL_Pos (1U)
+#define SDIO_STA_DCRCFAIL_Msk (0x1U << SDIO_STA_DCRCFAIL_Pos) /*!< 0x00000002 */
+#define SDIO_STA_DCRCFAIL SDIO_STA_DCRCFAIL_Msk /*!< Data block sent/received (CRC check failed) */
+#define SDIO_STA_CTIMEOUT_Pos (2U)
+#define SDIO_STA_CTIMEOUT_Msk (0x1U << SDIO_STA_CTIMEOUT_Pos) /*!< 0x00000004 */
+#define SDIO_STA_CTIMEOUT SDIO_STA_CTIMEOUT_Msk /*!< Command response timeout */
+#define SDIO_STA_DTIMEOUT_Pos (3U)
+#define SDIO_STA_DTIMEOUT_Msk (0x1U << SDIO_STA_DTIMEOUT_Pos) /*!< 0x00000008 */
+#define SDIO_STA_DTIMEOUT SDIO_STA_DTIMEOUT_Msk /*!< Data timeout */
+#define SDIO_STA_TXUNDERR_Pos (4U)
+#define SDIO_STA_TXUNDERR_Msk (0x1U << SDIO_STA_TXUNDERR_Pos) /*!< 0x00000010 */
+#define SDIO_STA_TXUNDERR SDIO_STA_TXUNDERR_Msk /*!< Transmit FIFO underrun error */
+#define SDIO_STA_RXOVERR_Pos (5U)
+#define SDIO_STA_RXOVERR_Msk (0x1U << SDIO_STA_RXOVERR_Pos) /*!< 0x00000020 */
+#define SDIO_STA_RXOVERR SDIO_STA_RXOVERR_Msk /*!< Received FIFO overrun error */
+#define SDIO_STA_CMDREND_Pos (6U)
+#define SDIO_STA_CMDREND_Msk (0x1U << SDIO_STA_CMDREND_Pos) /*!< 0x00000040 */
+#define SDIO_STA_CMDREND SDIO_STA_CMDREND_Msk /*!< Command response received (CRC check passed) */
+#define SDIO_STA_CMDSENT_Pos (7U)
+#define SDIO_STA_CMDSENT_Msk (0x1U << SDIO_STA_CMDSENT_Pos) /*!< 0x00000080 */
+#define SDIO_STA_CMDSENT SDIO_STA_CMDSENT_Msk /*!< Command sent (no response required) */
+#define SDIO_STA_DATAEND_Pos (8U)
+#define SDIO_STA_DATAEND_Msk (0x1U << SDIO_STA_DATAEND_Pos) /*!< 0x00000100 */
+#define SDIO_STA_DATAEND SDIO_STA_DATAEND_Msk /*!< Data end (data counter, SDIDCOUNT, is zero) */
+#define SDIO_STA_STBITERR_Pos (9U)
+#define SDIO_STA_STBITERR_Msk (0x1U << SDIO_STA_STBITERR_Pos) /*!< 0x00000200 */
+#define SDIO_STA_STBITERR SDIO_STA_STBITERR_Msk /*!< Start bit not detected on all data signals in wide bus mode */
+#define SDIO_STA_DBCKEND_Pos (10U)
+#define SDIO_STA_DBCKEND_Msk (0x1U << SDIO_STA_DBCKEND_Pos) /*!< 0x00000400 */
+#define SDIO_STA_DBCKEND SDIO_STA_DBCKEND_Msk /*!< Data block sent/received (CRC check passed) */
+#define SDIO_STA_CMDACT_Pos (11U)
+#define SDIO_STA_CMDACT_Msk (0x1U << SDIO_STA_CMDACT_Pos) /*!< 0x00000800 */
+#define SDIO_STA_CMDACT SDIO_STA_CMDACT_Msk /*!< Command transfer in progress */
+#define SDIO_STA_TXACT_Pos (12U)
+#define SDIO_STA_TXACT_Msk (0x1U << SDIO_STA_TXACT_Pos) /*!< 0x00001000 */
+#define SDIO_STA_TXACT SDIO_STA_TXACT_Msk /*!< Data transmit in progress */
+#define SDIO_STA_RXACT_Pos (13U)
+#define SDIO_STA_RXACT_Msk (0x1U << SDIO_STA_RXACT_Pos) /*!< 0x00002000 */
+#define SDIO_STA_RXACT SDIO_STA_RXACT_Msk /*!< Data receive in progress */
+#define SDIO_STA_TXFIFOHE_Pos (14U)
+#define SDIO_STA_TXFIFOHE_Msk (0x1U << SDIO_STA_TXFIFOHE_Pos) /*!< 0x00004000 */
+#define SDIO_STA_TXFIFOHE SDIO_STA_TXFIFOHE_Msk /*!< Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
+#define SDIO_STA_RXFIFOHF_Pos (15U)
+#define SDIO_STA_RXFIFOHF_Msk (0x1U << SDIO_STA_RXFIFOHF_Pos) /*!< 0x00008000 */
+#define SDIO_STA_RXFIFOHF SDIO_STA_RXFIFOHF_Msk /*!< Receive FIFO Half Full: there are at least 8 words in the FIFO */
+#define SDIO_STA_TXFIFOF_Pos (16U)
+#define SDIO_STA_TXFIFOF_Msk (0x1U << SDIO_STA_TXFIFOF_Pos) /*!< 0x00010000 */
+#define SDIO_STA_TXFIFOF SDIO_STA_TXFIFOF_Msk /*!< Transmit FIFO full */
+#define SDIO_STA_RXFIFOF_Pos (17U)
+#define SDIO_STA_RXFIFOF_Msk (0x1U << SDIO_STA_RXFIFOF_Pos) /*!< 0x00020000 */
+#define SDIO_STA_RXFIFOF SDIO_STA_RXFIFOF_Msk /*!< Receive FIFO full */
+#define SDIO_STA_TXFIFOE_Pos (18U)
+#define SDIO_STA_TXFIFOE_Msk (0x1U << SDIO_STA_TXFIFOE_Pos) /*!< 0x00040000 */
+#define SDIO_STA_TXFIFOE SDIO_STA_TXFIFOE_Msk /*!< Transmit FIFO empty */
+#define SDIO_STA_RXFIFOE_Pos (19U)
+#define SDIO_STA_RXFIFOE_Msk (0x1U << SDIO_STA_RXFIFOE_Pos) /*!< 0x00080000 */
+#define SDIO_STA_RXFIFOE SDIO_STA_RXFIFOE_Msk /*!< Receive FIFO empty */
+#define SDIO_STA_TXDAVL_Pos (20U)
+#define SDIO_STA_TXDAVL_Msk (0x1U << SDIO_STA_TXDAVL_Pos) /*!< 0x00100000 */
+#define SDIO_STA_TXDAVL SDIO_STA_TXDAVL_Msk /*!< Data available in transmit FIFO */
+#define SDIO_STA_RXDAVL_Pos (21U)
+#define SDIO_STA_RXDAVL_Msk (0x1U << SDIO_STA_RXDAVL_Pos) /*!< 0x00200000 */
+#define SDIO_STA_RXDAVL SDIO_STA_RXDAVL_Msk /*!< Data available in receive FIFO */
+#define SDIO_STA_SDIOIT_Pos (22U)
+#define SDIO_STA_SDIOIT_Msk (0x1U << SDIO_STA_SDIOIT_Pos) /*!< 0x00400000 */
+#define SDIO_STA_SDIOIT SDIO_STA_SDIOIT_Msk /*!< SDIO interrupt received */
+#define SDIO_STA_CEATAEND_Pos (23U)
+#define SDIO_STA_CEATAEND_Msk (0x1U << SDIO_STA_CEATAEND_Pos) /*!< 0x00800000 */
+#define SDIO_STA_CEATAEND SDIO_STA_CEATAEND_Msk /*!< CE-ATA command completion signal received for CMD61 */
+
+/******************* Bit definition for SDIO_ICR register *******************/
+#define SDIO_ICR_CCRCFAILC_Pos (0U)
+#define SDIO_ICR_CCRCFAILC_Msk (0x1U << SDIO_ICR_CCRCFAILC_Pos) /*!< 0x00000001 */
+#define SDIO_ICR_CCRCFAILC SDIO_ICR_CCRCFAILC_Msk /*!< CCRCFAIL flag clear bit */
+#define SDIO_ICR_DCRCFAILC_Pos (1U)
+#define SDIO_ICR_DCRCFAILC_Msk (0x1U << SDIO_ICR_DCRCFAILC_Pos) /*!< 0x00000002 */
+#define SDIO_ICR_DCRCFAILC SDIO_ICR_DCRCFAILC_Msk /*!< DCRCFAIL flag clear bit */
+#define SDIO_ICR_CTIMEOUTC_Pos (2U)
+#define SDIO_ICR_CTIMEOUTC_Msk (0x1U << SDIO_ICR_CTIMEOUTC_Pos) /*!< 0x00000004 */
+#define SDIO_ICR_CTIMEOUTC SDIO_ICR_CTIMEOUTC_Msk /*!< CTIMEOUT flag clear bit */
+#define SDIO_ICR_DTIMEOUTC_Pos (3U)
+#define SDIO_ICR_DTIMEOUTC_Msk (0x1U << SDIO_ICR_DTIMEOUTC_Pos) /*!< 0x00000008 */
+#define SDIO_ICR_DTIMEOUTC SDIO_ICR_DTIMEOUTC_Msk /*!< DTIMEOUT flag clear bit */
+#define SDIO_ICR_TXUNDERRC_Pos (4U)
+#define SDIO_ICR_TXUNDERRC_Msk (0x1U << SDIO_ICR_TXUNDERRC_Pos) /*!< 0x00000010 */
+#define SDIO_ICR_TXUNDERRC SDIO_ICR_TXUNDERRC_Msk /*!< TXUNDERR flag clear bit */
+#define SDIO_ICR_RXOVERRC_Pos (5U)
+#define SDIO_ICR_RXOVERRC_Msk (0x1U << SDIO_ICR_RXOVERRC_Pos) /*!< 0x00000020 */
+#define SDIO_ICR_RXOVERRC SDIO_ICR_RXOVERRC_Msk /*!< RXOVERR flag clear bit */
+#define SDIO_ICR_CMDRENDC_Pos (6U)
+#define SDIO_ICR_CMDRENDC_Msk (0x1U << SDIO_ICR_CMDRENDC_Pos) /*!< 0x00000040 */
+#define SDIO_ICR_CMDRENDC SDIO_ICR_CMDRENDC_Msk /*!< CMDREND flag clear bit */
+#define SDIO_ICR_CMDSENTC_Pos (7U)
+#define SDIO_ICR_CMDSENTC_Msk (0x1U << SDIO_ICR_CMDSENTC_Pos) /*!< 0x00000080 */
+#define SDIO_ICR_CMDSENTC SDIO_ICR_CMDSENTC_Msk /*!< CMDSENT flag clear bit */
+#define SDIO_ICR_DATAENDC_Pos (8U)
+#define SDIO_ICR_DATAENDC_Msk (0x1U << SDIO_ICR_DATAENDC_Pos) /*!< 0x00000100 */
+#define SDIO_ICR_DATAENDC SDIO_ICR_DATAENDC_Msk /*!< DATAEND flag clear bit */
+#define SDIO_ICR_STBITERRC_Pos (9U)
+#define SDIO_ICR_STBITERRC_Msk (0x1U << SDIO_ICR_STBITERRC_Pos) /*!< 0x00000200 */
+#define SDIO_ICR_STBITERRC SDIO_ICR_STBITERRC_Msk /*!< STBITERR flag clear bit */
+#define SDIO_ICR_DBCKENDC_Pos (10U)
+#define SDIO_ICR_DBCKENDC_Msk (0x1U << SDIO_ICR_DBCKENDC_Pos) /*!< 0x00000400 */
+#define SDIO_ICR_DBCKENDC SDIO_ICR_DBCKENDC_Msk /*!< DBCKEND flag clear bit */
+#define SDIO_ICR_SDIOITC_Pos (22U)
+#define SDIO_ICR_SDIOITC_Msk (0x1U << SDIO_ICR_SDIOITC_Pos) /*!< 0x00400000 */
+#define SDIO_ICR_SDIOITC SDIO_ICR_SDIOITC_Msk /*!< SDIOIT flag clear bit */
+#define SDIO_ICR_CEATAENDC_Pos (23U)
+#define SDIO_ICR_CEATAENDC_Msk (0x1U << SDIO_ICR_CEATAENDC_Pos) /*!< 0x00800000 */
+#define SDIO_ICR_CEATAENDC SDIO_ICR_CEATAENDC_Msk /*!< CEATAEND flag clear bit */
+
+/****************** Bit definition for SDIO_MASK register *******************/
+#define SDIO_MASK_CCRCFAILIE_Pos (0U)
+#define SDIO_MASK_CCRCFAILIE_Msk (0x1U << SDIO_MASK_CCRCFAILIE_Pos) /*!< 0x00000001 */
+#define SDIO_MASK_CCRCFAILIE SDIO_MASK_CCRCFAILIE_Msk /*!< Command CRC Fail Interrupt Enable */
+#define SDIO_MASK_DCRCFAILIE_Pos (1U)
+#define SDIO_MASK_DCRCFAILIE_Msk (0x1U << SDIO_MASK_DCRCFAILIE_Pos) /*!< 0x00000002 */
+#define SDIO_MASK_DCRCFAILIE SDIO_MASK_DCRCFAILIE_Msk /*!< Data CRC Fail Interrupt Enable */
+#define SDIO_MASK_CTIMEOUTIE_Pos (2U)
+#define SDIO_MASK_CTIMEOUTIE_Msk (0x1U << SDIO_MASK_CTIMEOUTIE_Pos) /*!< 0x00000004 */
+#define SDIO_MASK_CTIMEOUTIE SDIO_MASK_CTIMEOUTIE_Msk /*!< Command TimeOut Interrupt Enable */
+#define SDIO_MASK_DTIMEOUTIE_Pos (3U)
+#define SDIO_MASK_DTIMEOUTIE_Msk (0x1U << SDIO_MASK_DTIMEOUTIE_Pos) /*!< 0x00000008 */
+#define SDIO_MASK_DTIMEOUTIE SDIO_MASK_DTIMEOUTIE_Msk /*!< Data TimeOut Interrupt Enable */
+#define SDIO_MASK_TXUNDERRIE_Pos (4U)
+#define SDIO_MASK_TXUNDERRIE_Msk (0x1U << SDIO_MASK_TXUNDERRIE_Pos) /*!< 0x00000010 */
+#define SDIO_MASK_TXUNDERRIE SDIO_MASK_TXUNDERRIE_Msk /*!< Tx FIFO UnderRun Error Interrupt Enable */
+#define SDIO_MASK_RXOVERRIE_Pos (5U)
+#define SDIO_MASK_RXOVERRIE_Msk (0x1U << SDIO_MASK_RXOVERRIE_Pos) /*!< 0x00000020 */
+#define SDIO_MASK_RXOVERRIE SDIO_MASK_RXOVERRIE_Msk /*!< Rx FIFO OverRun Error Interrupt Enable */
+#define SDIO_MASK_CMDRENDIE_Pos (6U)
+#define SDIO_MASK_CMDRENDIE_Msk (0x1U << SDIO_MASK_CMDRENDIE_Pos) /*!< 0x00000040 */
+#define SDIO_MASK_CMDRENDIE SDIO_MASK_CMDRENDIE_Msk /*!< Command Response Received Interrupt Enable */
+#define SDIO_MASK_CMDSENTIE_Pos (7U)
+#define SDIO_MASK_CMDSENTIE_Msk (0x1U << SDIO_MASK_CMDSENTIE_Pos) /*!< 0x00000080 */
+#define SDIO_MASK_CMDSENTIE SDIO_MASK_CMDSENTIE_Msk /*!< Command Sent Interrupt Enable */
+#define SDIO_MASK_DATAENDIE_Pos (8U)
+#define SDIO_MASK_DATAENDIE_Msk (0x1U << SDIO_MASK_DATAENDIE_Pos) /*!< 0x00000100 */
+#define SDIO_MASK_DATAENDIE SDIO_MASK_DATAENDIE_Msk /*!< Data End Interrupt Enable */
+#define SDIO_MASK_STBITERRIE_Pos (9U)
+#define SDIO_MASK_STBITERRIE_Msk (0x1U << SDIO_MASK_STBITERRIE_Pos) /*!< 0x00000200 */
+#define SDIO_MASK_STBITERRIE SDIO_MASK_STBITERRIE_Msk /*!< Start Bit Error Interrupt Enable */
+#define SDIO_MASK_DBCKENDIE_Pos (10U)
+#define SDIO_MASK_DBCKENDIE_Msk (0x1U << SDIO_MASK_DBCKENDIE_Pos) /*!< 0x00000400 */
+#define SDIO_MASK_DBCKENDIE SDIO_MASK_DBCKENDIE_Msk /*!< Data Block End Interrupt Enable */
+#define SDIO_MASK_CMDACTIE_Pos (11U)
+#define SDIO_MASK_CMDACTIE_Msk (0x1U << SDIO_MASK_CMDACTIE_Pos) /*!< 0x00000800 */
+#define SDIO_MASK_CMDACTIE SDIO_MASK_CMDACTIE_Msk /*!< Command Acting Interrupt Enable */
+#define SDIO_MASK_TXACTIE_Pos (12U)
+#define SDIO_MASK_TXACTIE_Msk (0x1U << SDIO_MASK_TXACTIE_Pos) /*!< 0x00001000 */
+#define SDIO_MASK_TXACTIE SDIO_MASK_TXACTIE_Msk /*!< Data Transmit Acting Interrupt Enable */
+#define SDIO_MASK_RXACTIE_Pos (13U)
+#define SDIO_MASK_RXACTIE_Msk (0x1U << SDIO_MASK_RXACTIE_Pos) /*!< 0x00002000 */
+#define SDIO_MASK_RXACTIE SDIO_MASK_RXACTIE_Msk /*!< Data receive acting interrupt enabled */
+#define SDIO_MASK_TXFIFOHEIE_Pos (14U)
+#define SDIO_MASK_TXFIFOHEIE_Msk (0x1U << SDIO_MASK_TXFIFOHEIE_Pos) /*!< 0x00004000 */
+#define SDIO_MASK_TXFIFOHEIE SDIO_MASK_TXFIFOHEIE_Msk /*!< Tx FIFO Half Empty interrupt Enable */
+#define SDIO_MASK_RXFIFOHFIE_Pos (15U)
+#define SDIO_MASK_RXFIFOHFIE_Msk (0x1U << SDIO_MASK_RXFIFOHFIE_Pos) /*!< 0x00008000 */
+#define SDIO_MASK_RXFIFOHFIE SDIO_MASK_RXFIFOHFIE_Msk /*!< Rx FIFO Half Full interrupt Enable */
+#define SDIO_MASK_TXFIFOFIE_Pos (16U)
+#define SDIO_MASK_TXFIFOFIE_Msk (0x1U << SDIO_MASK_TXFIFOFIE_Pos) /*!< 0x00010000 */
+#define SDIO_MASK_TXFIFOFIE SDIO_MASK_TXFIFOFIE_Msk /*!< Tx FIFO Full interrupt Enable */
+#define SDIO_MASK_RXFIFOFIE_Pos (17U)
+#define SDIO_MASK_RXFIFOFIE_Msk (0x1U << SDIO_MASK_RXFIFOFIE_Pos) /*!< 0x00020000 */
+#define SDIO_MASK_RXFIFOFIE SDIO_MASK_RXFIFOFIE_Msk /*!< Rx FIFO Full interrupt Enable */
+#define SDIO_MASK_TXFIFOEIE_Pos (18U)
+#define SDIO_MASK_TXFIFOEIE_Msk (0x1U << SDIO_MASK_TXFIFOEIE_Pos) /*!< 0x00040000 */
+#define SDIO_MASK_TXFIFOEIE SDIO_MASK_TXFIFOEIE_Msk /*!< Tx FIFO Empty interrupt Enable */
+#define SDIO_MASK_RXFIFOEIE_Pos (19U)
+#define SDIO_MASK_RXFIFOEIE_Msk (0x1U << SDIO_MASK_RXFIFOEIE_Pos) /*!< 0x00080000 */
+#define SDIO_MASK_RXFIFOEIE SDIO_MASK_RXFIFOEIE_Msk /*!< Rx FIFO Empty interrupt Enable */
+#define SDIO_MASK_TXDAVLIE_Pos (20U)
+#define SDIO_MASK_TXDAVLIE_Msk (0x1U << SDIO_MASK_TXDAVLIE_Pos) /*!< 0x00100000 */
+#define SDIO_MASK_TXDAVLIE SDIO_MASK_TXDAVLIE_Msk /*!< Data available in Tx FIFO interrupt Enable */
+#define SDIO_MASK_RXDAVLIE_Pos (21U)
+#define SDIO_MASK_RXDAVLIE_Msk (0x1U << SDIO_MASK_RXDAVLIE_Pos) /*!< 0x00200000 */
+#define SDIO_MASK_RXDAVLIE SDIO_MASK_RXDAVLIE_Msk /*!< Data available in Rx FIFO interrupt Enable */
+#define SDIO_MASK_SDIOITIE_Pos (22U)
+#define SDIO_MASK_SDIOITIE_Msk (0x1U << SDIO_MASK_SDIOITIE_Pos) /*!< 0x00400000 */
+#define SDIO_MASK_SDIOITIE SDIO_MASK_SDIOITIE_Msk /*!< SDIO Mode Interrupt Received interrupt Enable */
+#define SDIO_MASK_CEATAENDIE_Pos (23U)
+#define SDIO_MASK_CEATAENDIE_Msk (0x1U << SDIO_MASK_CEATAENDIE_Pos) /*!< 0x00800000 */
+#define SDIO_MASK_CEATAENDIE SDIO_MASK_CEATAENDIE_Msk /*!< CE-ATA command completion signal received Interrupt Enable */
+
+/***************** Bit definition for SDIO_FIFOCNT register *****************/
+#define SDIO_FIFOCNT_FIFOCOUNT_Pos (0U)
+#define SDIO_FIFOCNT_FIFOCOUNT_Msk (0xFFFFFFU << SDIO_FIFOCNT_FIFOCOUNT_Pos) /*!< 0x00FFFFFF */
+#define SDIO_FIFOCNT_FIFOCOUNT SDIO_FIFOCNT_FIFOCOUNT_Msk /*!< Remaining number of words to be written to or read from the FIFO */
+
+/****************** Bit definition for SDIO_FIFO register *******************/
+#define SDIO_FIFO_FIFODATA_Pos (0U)
+#define SDIO_FIFO_FIFODATA_Msk (0xFFFFFFFFU << SDIO_FIFO_FIFODATA_Pos) /*!< 0xFFFFFFFF */
+#define SDIO_FIFO_FIFODATA SDIO_FIFO_FIFODATA_Msk /*!< Receive and transmit FIFO data */
+
+
+
+/******************************************************************************/
+/* */
+/* Serial Peripheral Interface */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for SPI_CR1 register ********************/
+#define SPI_CR1_CPHA_Pos (0U)
+#define SPI_CR1_CPHA_Msk (0x1U << SPI_CR1_CPHA_Pos) /*!< 0x00000001 */
+#define SPI_CR1_CPHA SPI_CR1_CPHA_Msk /*!< Clock Phase */
+#define SPI_CR1_CPOL_Pos (1U)
+#define SPI_CR1_CPOL_Msk (0x1U << SPI_CR1_CPOL_Pos) /*!< 0x00000002 */
+#define SPI_CR1_CPOL SPI_CR1_CPOL_Msk /*!< Clock Polarity */
+#define SPI_CR1_MSTR_Pos (2U)
+#define SPI_CR1_MSTR_Msk (0x1U << SPI_CR1_MSTR_Pos) /*!< 0x00000004 */
+#define SPI_CR1_MSTR SPI_CR1_MSTR_Msk /*!< Master Selection */
+
+#define SPI_CR1_BR_Pos (3U)
+#define SPI_CR1_BR_Msk (0x7U << SPI_CR1_BR_Pos) /*!< 0x00000038 */
+#define SPI_CR1_BR SPI_CR1_BR_Msk /*!< BR[2:0] bits (Baud Rate Control) */
+#define SPI_CR1_BR_0 (0x1U << SPI_CR1_BR_Pos) /*!< 0x00000008 */
+#define SPI_CR1_BR_1 (0x2U << SPI_CR1_BR_Pos) /*!< 0x00000010 */
+#define SPI_CR1_BR_2 (0x4U << SPI_CR1_BR_Pos) /*!< 0x00000020 */
+
+#define SPI_CR1_SPE_Pos (6U)
+#define SPI_CR1_SPE_Msk (0x1U << SPI_CR1_SPE_Pos) /*!< 0x00000040 */
+#define SPI_CR1_SPE SPI_CR1_SPE_Msk /*!< SPI Enable */
+#define SPI_CR1_LSBFIRST_Pos (7U)
+#define SPI_CR1_LSBFIRST_Msk (0x1U << SPI_CR1_LSBFIRST_Pos) /*!< 0x00000080 */
+#define SPI_CR1_LSBFIRST SPI_CR1_LSBFIRST_Msk /*!< Frame Format */
+#define SPI_CR1_SSI_Pos (8U)
+#define SPI_CR1_SSI_Msk (0x1U << SPI_CR1_SSI_Pos) /*!< 0x00000100 */
+#define SPI_CR1_SSI SPI_CR1_SSI_Msk /*!< Internal slave select */
+#define SPI_CR1_SSM_Pos (9U)
+#define SPI_CR1_SSM_Msk (0x1U << SPI_CR1_SSM_Pos) /*!< 0x00000200 */
+#define SPI_CR1_SSM SPI_CR1_SSM_Msk /*!< Software slave management */
+#define SPI_CR1_RXONLY_Pos (10U)
+#define SPI_CR1_RXONLY_Msk (0x1U << SPI_CR1_RXONLY_Pos) /*!< 0x00000400 */
+#define SPI_CR1_RXONLY SPI_CR1_RXONLY_Msk /*!< Receive only */
+#define SPI_CR1_DFF_Pos (11U)
+#define SPI_CR1_DFF_Msk (0x1U << SPI_CR1_DFF_Pos) /*!< 0x00000800 */
+#define SPI_CR1_DFF SPI_CR1_DFF_Msk /*!< Data Frame Format */
+#define SPI_CR1_CRCNEXT_Pos (12U)
+#define SPI_CR1_CRCNEXT_Msk (0x1U << SPI_CR1_CRCNEXT_Pos) /*!< 0x00001000 */
+#define SPI_CR1_CRCNEXT SPI_CR1_CRCNEXT_Msk /*!< Transmit CRC next */
+#define SPI_CR1_CRCEN_Pos (13U)
+#define SPI_CR1_CRCEN_Msk (0x1U << SPI_CR1_CRCEN_Pos) /*!< 0x00002000 */
+#define SPI_CR1_CRCEN SPI_CR1_CRCEN_Msk /*!< Hardware CRC calculation enable */
+#define SPI_CR1_BIDIOE_Pos (14U)
+#define SPI_CR1_BIDIOE_Msk (0x1U << SPI_CR1_BIDIOE_Pos) /*!< 0x00004000 */
+#define SPI_CR1_BIDIOE SPI_CR1_BIDIOE_Msk /*!< Output enable in bidirectional mode */
+#define SPI_CR1_BIDIMODE_Pos (15U)
+#define SPI_CR1_BIDIMODE_Msk (0x1U << SPI_CR1_BIDIMODE_Pos) /*!< 0x00008000 */
+#define SPI_CR1_BIDIMODE SPI_CR1_BIDIMODE_Msk /*!< Bidirectional data mode enable */
+
+/******************* Bit definition for SPI_CR2 register ********************/
+#define SPI_CR2_RXDMAEN_Pos (0U)
+#define SPI_CR2_RXDMAEN_Msk (0x1U << SPI_CR2_RXDMAEN_Pos) /*!< 0x00000001 */
+#define SPI_CR2_RXDMAEN SPI_CR2_RXDMAEN_Msk /*!< Rx Buffer DMA Enable */
+#define SPI_CR2_TXDMAEN_Pos (1U)
+#define SPI_CR2_TXDMAEN_Msk (0x1U << SPI_CR2_TXDMAEN_Pos) /*!< 0x00000002 */
+#define SPI_CR2_TXDMAEN SPI_CR2_TXDMAEN_Msk /*!< Tx Buffer DMA Enable */
+#define SPI_CR2_SSOE_Pos (2U)
+#define SPI_CR2_SSOE_Msk (0x1U << SPI_CR2_SSOE_Pos) /*!< 0x00000004 */
+#define SPI_CR2_SSOE SPI_CR2_SSOE_Msk /*!< SS Output Enable */
+#define SPI_CR2_ERRIE_Pos (5U)
+#define SPI_CR2_ERRIE_Msk (0x1U << SPI_CR2_ERRIE_Pos) /*!< 0x00000020 */
+#define SPI_CR2_ERRIE SPI_CR2_ERRIE_Msk /*!< Error Interrupt Enable */
+#define SPI_CR2_RXNEIE_Pos (6U)
+#define SPI_CR2_RXNEIE_Msk (0x1U << SPI_CR2_RXNEIE_Pos) /*!< 0x00000040 */
+#define SPI_CR2_RXNEIE SPI_CR2_RXNEIE_Msk /*!< RX buffer Not Empty Interrupt Enable */
+#define SPI_CR2_TXEIE_Pos (7U)
+#define SPI_CR2_TXEIE_Msk (0x1U << SPI_CR2_TXEIE_Pos) /*!< 0x00000080 */
+#define SPI_CR2_TXEIE SPI_CR2_TXEIE_Msk /*!< Tx buffer Empty Interrupt Enable */
+
+/******************** Bit definition for SPI_SR register ********************/
+#define SPI_SR_RXNE_Pos (0U)
+#define SPI_SR_RXNE_Msk (0x1U << SPI_SR_RXNE_Pos) /*!< 0x00000001 */
+#define SPI_SR_RXNE SPI_SR_RXNE_Msk /*!< Receive buffer Not Empty */
+#define SPI_SR_TXE_Pos (1U)
+#define SPI_SR_TXE_Msk (0x1U << SPI_SR_TXE_Pos) /*!< 0x00000002 */
+#define SPI_SR_TXE SPI_SR_TXE_Msk /*!< Transmit buffer Empty */
+#define SPI_SR_CHSIDE_Pos (2U)
+#define SPI_SR_CHSIDE_Msk (0x1U << SPI_SR_CHSIDE_Pos) /*!< 0x00000004 */
+#define SPI_SR_CHSIDE SPI_SR_CHSIDE_Msk /*!< Channel side */
+#define SPI_SR_UDR_Pos (3U)
+#define SPI_SR_UDR_Msk (0x1U << SPI_SR_UDR_Pos) /*!< 0x00000008 */
+#define SPI_SR_UDR SPI_SR_UDR_Msk /*!< Underrun flag */
+#define SPI_SR_CRCERR_Pos (4U)
+#define SPI_SR_CRCERR_Msk (0x1U << SPI_SR_CRCERR_Pos) /*!< 0x00000010 */
+#define SPI_SR_CRCERR SPI_SR_CRCERR_Msk /*!< CRC Error flag */
+#define SPI_SR_MODF_Pos (5U)
+#define SPI_SR_MODF_Msk (0x1U << SPI_SR_MODF_Pos) /*!< 0x00000020 */
+#define SPI_SR_MODF SPI_SR_MODF_Msk /*!< Mode fault */
+#define SPI_SR_OVR_Pos (6U)
+#define SPI_SR_OVR_Msk (0x1U << SPI_SR_OVR_Pos) /*!< 0x00000040 */
+#define SPI_SR_OVR SPI_SR_OVR_Msk /*!< Overrun flag */
+#define SPI_SR_BSY_Pos (7U)
+#define SPI_SR_BSY_Msk (0x1U << SPI_SR_BSY_Pos) /*!< 0x00000080 */
+#define SPI_SR_BSY SPI_SR_BSY_Msk /*!< Busy flag */
+
+/******************** Bit definition for SPI_DR register ********************/
+#define SPI_DR_DR_Pos (0U)
+#define SPI_DR_DR_Msk (0xFFFFU << SPI_DR_DR_Pos) /*!< 0x0000FFFF */
+#define SPI_DR_DR SPI_DR_DR_Msk /*!< Data Register */
+
+/******************* Bit definition for SPI_CRCPR register ******************/
+#define SPI_CRCPR_CRCPOLY_Pos (0U)
+#define SPI_CRCPR_CRCPOLY_Msk (0xFFFFU << SPI_CRCPR_CRCPOLY_Pos) /*!< 0x0000FFFF */
+#define SPI_CRCPR_CRCPOLY SPI_CRCPR_CRCPOLY_Msk /*!< CRC polynomial register */
+
+/****************** Bit definition for SPI_RXCRCR register ******************/
+#define SPI_RXCRCR_RXCRC_Pos (0U)
+#define SPI_RXCRCR_RXCRC_Msk (0xFFFFU << SPI_RXCRCR_RXCRC_Pos) /*!< 0x0000FFFF */
+#define SPI_RXCRCR_RXCRC SPI_RXCRCR_RXCRC_Msk /*!< Rx CRC Register */
+
+/****************** Bit definition for SPI_TXCRCR register ******************/
+#define SPI_TXCRCR_TXCRC_Pos (0U)
+#define SPI_TXCRCR_TXCRC_Msk (0xFFFFU << SPI_TXCRCR_TXCRC_Pos) /*!< 0x0000FFFF */
+#define SPI_TXCRCR_TXCRC SPI_TXCRCR_TXCRC_Msk /*!< Tx CRC Register */
+
+
+
+/******************************************************************************/
+/* */
+/* Inter-integrated Circuit Interface */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for I2C_CR1 register ********************/
+#define I2C_CR1_PE_Pos (0U)
+#define I2C_CR1_PE_Msk (0x1U << I2C_CR1_PE_Pos) /*!< 0x00000001 */
+#define I2C_CR1_PE I2C_CR1_PE_Msk /*!< Peripheral Enable */
+#define I2C_CR1_SMBUS_Pos (1U)
+#define I2C_CR1_SMBUS_Msk (0x1U << I2C_CR1_SMBUS_Pos) /*!< 0x00000002 */
+#define I2C_CR1_SMBUS I2C_CR1_SMBUS_Msk /*!< SMBus Mode */
+#define I2C_CR1_SMBTYPE_Pos (3U)
+#define I2C_CR1_SMBTYPE_Msk (0x1U << I2C_CR1_SMBTYPE_Pos) /*!< 0x00000008 */
+#define I2C_CR1_SMBTYPE I2C_CR1_SMBTYPE_Msk /*!< SMBus Type */
+#define I2C_CR1_ENARP_Pos (4U)
+#define I2C_CR1_ENARP_Msk (0x1U << I2C_CR1_ENARP_Pos) /*!< 0x00000010 */
+#define I2C_CR1_ENARP I2C_CR1_ENARP_Msk /*!< ARP Enable */
+#define I2C_CR1_ENPEC_Pos (5U)
+#define I2C_CR1_ENPEC_Msk (0x1U << I2C_CR1_ENPEC_Pos) /*!< 0x00000020 */
+#define I2C_CR1_ENPEC I2C_CR1_ENPEC_Msk /*!< PEC Enable */
+#define I2C_CR1_ENGC_Pos (6U)
+#define I2C_CR1_ENGC_Msk (0x1U << I2C_CR1_ENGC_Pos) /*!< 0x00000040 */
+#define I2C_CR1_ENGC I2C_CR1_ENGC_Msk /*!< General Call Enable */
+#define I2C_CR1_NOSTRETCH_Pos (7U)
+#define I2C_CR1_NOSTRETCH_Msk (0x1U << I2C_CR1_NOSTRETCH_Pos) /*!< 0x00000080 */
+#define I2C_CR1_NOSTRETCH I2C_CR1_NOSTRETCH_Msk /*!< Clock Stretching Disable (Slave mode) */
+#define I2C_CR1_START_Pos (8U)
+#define I2C_CR1_START_Msk (0x1U << I2C_CR1_START_Pos) /*!< 0x00000100 */
+#define I2C_CR1_START I2C_CR1_START_Msk /*!< Start Generation */
+#define I2C_CR1_STOP_Pos (9U)
+#define I2C_CR1_STOP_Msk (0x1U << I2C_CR1_STOP_Pos) /*!< 0x00000200 */
+#define I2C_CR1_STOP I2C_CR1_STOP_Msk /*!< Stop Generation */
+#define I2C_CR1_ACK_Pos (10U)
+#define I2C_CR1_ACK_Msk (0x1U << I2C_CR1_ACK_Pos) /*!< 0x00000400 */
+#define I2C_CR1_ACK I2C_CR1_ACK_Msk /*!< Acknowledge Enable */
+#define I2C_CR1_POS_Pos (11U)
+#define I2C_CR1_POS_Msk (0x1U << I2C_CR1_POS_Pos) /*!< 0x00000800 */
+#define I2C_CR1_POS I2C_CR1_POS_Msk /*!< Acknowledge/PEC Position (for data reception) */
+#define I2C_CR1_PEC_Pos (12U)
+#define I2C_CR1_PEC_Msk (0x1U << I2C_CR1_PEC_Pos) /*!< 0x00001000 */
+#define I2C_CR1_PEC I2C_CR1_PEC_Msk /*!< Packet Error Checking */
+#define I2C_CR1_ALERT_Pos (13U)
+#define I2C_CR1_ALERT_Msk (0x1U << I2C_CR1_ALERT_Pos) /*!< 0x00002000 */
+#define I2C_CR1_ALERT I2C_CR1_ALERT_Msk /*!< SMBus Alert */
+#define I2C_CR1_SWRST_Pos (15U)
+#define I2C_CR1_SWRST_Msk (0x1U << I2C_CR1_SWRST_Pos) /*!< 0x00008000 */
+#define I2C_CR1_SWRST I2C_CR1_SWRST_Msk /*!< Software Reset */
+
+/******************* Bit definition for I2C_CR2 register ********************/
+#define I2C_CR2_FREQ_Pos (0U)
+#define I2C_CR2_FREQ_Msk (0x3FU << I2C_CR2_FREQ_Pos) /*!< 0x0000003F */
+#define I2C_CR2_FREQ I2C_CR2_FREQ_Msk /*!< FREQ[5:0] bits (Peripheral Clock Frequency) */
+#define I2C_CR2_FREQ_0 (0x01U << I2C_CR2_FREQ_Pos) /*!< 0x00000001 */
+#define I2C_CR2_FREQ_1 (0x02U << I2C_CR2_FREQ_Pos) /*!< 0x00000002 */
+#define I2C_CR2_FREQ_2 (0x04U << I2C_CR2_FREQ_Pos) /*!< 0x00000004 */
+#define I2C_CR2_FREQ_3 (0x08U << I2C_CR2_FREQ_Pos) /*!< 0x00000008 */
+#define I2C_CR2_FREQ_4 (0x10U << I2C_CR2_FREQ_Pos) /*!< 0x00000010 */
+#define I2C_CR2_FREQ_5 (0x20U << I2C_CR2_FREQ_Pos) /*!< 0x00000020 */
+
+#define I2C_CR2_ITERREN_Pos (8U)
+#define I2C_CR2_ITERREN_Msk (0x1U << I2C_CR2_ITERREN_Pos) /*!< 0x00000100 */
+#define I2C_CR2_ITERREN I2C_CR2_ITERREN_Msk /*!< Error Interrupt Enable */
+#define I2C_CR2_ITEVTEN_Pos (9U)
+#define I2C_CR2_ITEVTEN_Msk (0x1U << I2C_CR2_ITEVTEN_Pos) /*!< 0x00000200 */
+#define I2C_CR2_ITEVTEN I2C_CR2_ITEVTEN_Msk /*!< Event Interrupt Enable */
+#define I2C_CR2_ITBUFEN_Pos (10U)
+#define I2C_CR2_ITBUFEN_Msk (0x1U << I2C_CR2_ITBUFEN_Pos) /*!< 0x00000400 */
+#define I2C_CR2_ITBUFEN I2C_CR2_ITBUFEN_Msk /*!< Buffer Interrupt Enable */
+#define I2C_CR2_DMAEN_Pos (11U)
+#define I2C_CR2_DMAEN_Msk (0x1U << I2C_CR2_DMAEN_Pos) /*!< 0x00000800 */
+#define I2C_CR2_DMAEN I2C_CR2_DMAEN_Msk /*!< DMA Requests Enable */
+#define I2C_CR2_LAST_Pos (12U)
+#define I2C_CR2_LAST_Msk (0x1U << I2C_CR2_LAST_Pos) /*!< 0x00001000 */
+#define I2C_CR2_LAST I2C_CR2_LAST_Msk /*!< DMA Last Transfer */
+
+/******************* Bit definition for I2C_OAR1 register *******************/
+#define I2C_OAR1_ADD1_7 ((uint32_t)0x000000FE) /*!< Interface Address */
+#define I2C_OAR1_ADD8_9 ((uint32_t)0x00000300) /*!< Interface Address */
+
+#define I2C_OAR1_ADD0_Pos (0U)
+#define I2C_OAR1_ADD0_Msk (0x1U << I2C_OAR1_ADD0_Pos) /*!< 0x00000001 */
+#define I2C_OAR1_ADD0 I2C_OAR1_ADD0_Msk /*!< Bit 0 */
+#define I2C_OAR1_ADD1_Pos (1U)
+#define I2C_OAR1_ADD1_Msk (0x1U << I2C_OAR1_ADD1_Pos) /*!< 0x00000002 */
+#define I2C_OAR1_ADD1 I2C_OAR1_ADD1_Msk /*!< Bit 1 */
+#define I2C_OAR1_ADD2_Pos (2U)
+#define I2C_OAR1_ADD2_Msk (0x1U << I2C_OAR1_ADD2_Pos) /*!< 0x00000004 */
+#define I2C_OAR1_ADD2 I2C_OAR1_ADD2_Msk /*!< Bit 2 */
+#define I2C_OAR1_ADD3_Pos (3U)
+#define I2C_OAR1_ADD3_Msk (0x1U << I2C_OAR1_ADD3_Pos) /*!< 0x00000008 */
+#define I2C_OAR1_ADD3 I2C_OAR1_ADD3_Msk /*!< Bit 3 */
+#define I2C_OAR1_ADD4_Pos (4U)
+#define I2C_OAR1_ADD4_Msk (0x1U << I2C_OAR1_ADD4_Pos) /*!< 0x00000010 */
+#define I2C_OAR1_ADD4 I2C_OAR1_ADD4_Msk /*!< Bit 4 */
+#define I2C_OAR1_ADD5_Pos (5U)
+#define I2C_OAR1_ADD5_Msk (0x1U << I2C_OAR1_ADD5_Pos) /*!< 0x00000020 */
+#define I2C_OAR1_ADD5 I2C_OAR1_ADD5_Msk /*!< Bit 5 */
+#define I2C_OAR1_ADD6_Pos (6U)
+#define I2C_OAR1_ADD6_Msk (0x1U << I2C_OAR1_ADD6_Pos) /*!< 0x00000040 */
+#define I2C_OAR1_ADD6 I2C_OAR1_ADD6_Msk /*!< Bit 6 */
+#define I2C_OAR1_ADD7_Pos (7U)
+#define I2C_OAR1_ADD7_Msk (0x1U << I2C_OAR1_ADD7_Pos) /*!< 0x00000080 */
+#define I2C_OAR1_ADD7 I2C_OAR1_ADD7_Msk /*!< Bit 7 */
+#define I2C_OAR1_ADD8_Pos (8U)
+#define I2C_OAR1_ADD8_Msk (0x1U << I2C_OAR1_ADD8_Pos) /*!< 0x00000100 */
+#define I2C_OAR1_ADD8 I2C_OAR1_ADD8_Msk /*!< Bit 8 */
+#define I2C_OAR1_ADD9_Pos (9U)
+#define I2C_OAR1_ADD9_Msk (0x1U << I2C_OAR1_ADD9_Pos) /*!< 0x00000200 */
+#define I2C_OAR1_ADD9 I2C_OAR1_ADD9_Msk /*!< Bit 9 */
+
+#define I2C_OAR1_ADDMODE_Pos (15U)
+#define I2C_OAR1_ADDMODE_Msk (0x1U << I2C_OAR1_ADDMODE_Pos) /*!< 0x00008000 */
+#define I2C_OAR1_ADDMODE I2C_OAR1_ADDMODE_Msk /*!< Addressing Mode (Slave mode) */
+
+/******************* Bit definition for I2C_OAR2 register *******************/
+#define I2C_OAR2_ENDUAL_Pos (0U)
+#define I2C_OAR2_ENDUAL_Msk (0x1U << I2C_OAR2_ENDUAL_Pos) /*!< 0x00000001 */
+#define I2C_OAR2_ENDUAL I2C_OAR2_ENDUAL_Msk /*!< Dual addressing mode enable */
+#define I2C_OAR2_ADD2_Pos (1U)
+#define I2C_OAR2_ADD2_Msk (0x7FU << I2C_OAR2_ADD2_Pos) /*!< 0x000000FE */
+#define I2C_OAR2_ADD2 I2C_OAR2_ADD2_Msk /*!< Interface address */
+
+/******************* Bit definition for I2C_SR1 register ********************/
+#define I2C_SR1_SB_Pos (0U)
+#define I2C_SR1_SB_Msk (0x1U << I2C_SR1_SB_Pos) /*!< 0x00000001 */
+#define I2C_SR1_SB I2C_SR1_SB_Msk /*!< Start Bit (Master mode) */
+#define I2C_SR1_ADDR_Pos (1U)
+#define I2C_SR1_ADDR_Msk (0x1U << I2C_SR1_ADDR_Pos) /*!< 0x00000002 */
+#define I2C_SR1_ADDR I2C_SR1_ADDR_Msk /*!< Address sent (master mode)/matched (slave mode) */
+#define I2C_SR1_BTF_Pos (2U)
+#define I2C_SR1_BTF_Msk (0x1U << I2C_SR1_BTF_Pos) /*!< 0x00000004 */
+#define I2C_SR1_BTF I2C_SR1_BTF_Msk /*!< Byte Transfer Finished */
+#define I2C_SR1_ADD10_Pos (3U)
+#define I2C_SR1_ADD10_Msk (0x1U << I2C_SR1_ADD10_Pos) /*!< 0x00000008 */
+#define I2C_SR1_ADD10 I2C_SR1_ADD10_Msk /*!< 10-bit header sent (Master mode) */
+#define I2C_SR1_STOPF_Pos (4U)
+#define I2C_SR1_STOPF_Msk (0x1U << I2C_SR1_STOPF_Pos) /*!< 0x00000010 */
+#define I2C_SR1_STOPF I2C_SR1_STOPF_Msk /*!< Stop detection (Slave mode) */
+#define I2C_SR1_RXNE_Pos (6U)
+#define I2C_SR1_RXNE_Msk (0x1U << I2C_SR1_RXNE_Pos) /*!< 0x00000040 */
+#define I2C_SR1_RXNE I2C_SR1_RXNE_Msk /*!< Data Register not Empty (receivers) */
+#define I2C_SR1_TXE_Pos (7U)
+#define I2C_SR1_TXE_Msk (0x1U << I2C_SR1_TXE_Pos) /*!< 0x00000080 */
+#define I2C_SR1_TXE I2C_SR1_TXE_Msk /*!< Data Register Empty (transmitters) */
+#define I2C_SR1_BERR_Pos (8U)
+#define I2C_SR1_BERR_Msk (0x1U << I2C_SR1_BERR_Pos) /*!< 0x00000100 */
+#define I2C_SR1_BERR I2C_SR1_BERR_Msk /*!< Bus Error */
+#define I2C_SR1_ARLO_Pos (9U)
+#define I2C_SR1_ARLO_Msk (0x1U << I2C_SR1_ARLO_Pos) /*!< 0x00000200 */
+#define I2C_SR1_ARLO I2C_SR1_ARLO_Msk /*!< Arbitration Lost (master mode) */
+#define I2C_SR1_AF_Pos (10U)
+#define I2C_SR1_AF_Msk (0x1U << I2C_SR1_AF_Pos) /*!< 0x00000400 */
+#define I2C_SR1_AF I2C_SR1_AF_Msk /*!< Acknowledge Failure */
+#define I2C_SR1_OVR_Pos (11U)
+#define I2C_SR1_OVR_Msk (0x1U << I2C_SR1_OVR_Pos) /*!< 0x00000800 */
+#define I2C_SR1_OVR I2C_SR1_OVR_Msk /*!< Overrun/Underrun */
+#define I2C_SR1_PECERR_Pos (12U)
+#define I2C_SR1_PECERR_Msk (0x1U << I2C_SR1_PECERR_Pos) /*!< 0x00001000 */
+#define I2C_SR1_PECERR I2C_SR1_PECERR_Msk /*!< PEC Error in reception */
+#define I2C_SR1_TIMEOUT_Pos (14U)
+#define I2C_SR1_TIMEOUT_Msk (0x1U << I2C_SR1_TIMEOUT_Pos) /*!< 0x00004000 */
+#define I2C_SR1_TIMEOUT I2C_SR1_TIMEOUT_Msk /*!< Timeout or Tlow Error */
+#define I2C_SR1_SMBALERT_Pos (15U)
+#define I2C_SR1_SMBALERT_Msk (0x1U << I2C_SR1_SMBALERT_Pos) /*!< 0x00008000 */
+#define I2C_SR1_SMBALERT I2C_SR1_SMBALERT_Msk /*!< SMBus Alert */
+
+/******************* Bit definition for I2C_SR2 register ********************/
+#define I2C_SR2_MSL_Pos (0U)
+#define I2C_SR2_MSL_Msk (0x1U << I2C_SR2_MSL_Pos) /*!< 0x00000001 */
+#define I2C_SR2_MSL I2C_SR2_MSL_Msk /*!< Master/Slave */
+#define I2C_SR2_BUSY_Pos (1U)
+#define I2C_SR2_BUSY_Msk (0x1U << I2C_SR2_BUSY_Pos) /*!< 0x00000002 */
+#define I2C_SR2_BUSY I2C_SR2_BUSY_Msk /*!< Bus Busy */
+#define I2C_SR2_TRA_Pos (2U)
+#define I2C_SR2_TRA_Msk (0x1U << I2C_SR2_TRA_Pos) /*!< 0x00000004 */
+#define I2C_SR2_TRA I2C_SR2_TRA_Msk /*!< Transmitter/Receiver */
+#define I2C_SR2_GENCALL_Pos (4U)
+#define I2C_SR2_GENCALL_Msk (0x1U << I2C_SR2_GENCALL_Pos) /*!< 0x00000010 */
+#define I2C_SR2_GENCALL I2C_SR2_GENCALL_Msk /*!< General Call Address (Slave mode) */
+#define I2C_SR2_SMBDEFAULT_Pos (5U)
+#define I2C_SR2_SMBDEFAULT_Msk (0x1U << I2C_SR2_SMBDEFAULT_Pos) /*!< 0x00000020 */
+#define I2C_SR2_SMBDEFAULT I2C_SR2_SMBDEFAULT_Msk /*!< SMBus Device Default Address (Slave mode) */
+#define I2C_SR2_SMBHOST_Pos (6U)
+#define I2C_SR2_SMBHOST_Msk (0x1U << I2C_SR2_SMBHOST_Pos) /*!< 0x00000040 */
+#define I2C_SR2_SMBHOST I2C_SR2_SMBHOST_Msk /*!< SMBus Host Header (Slave mode) */
+#define I2C_SR2_DUALF_Pos (7U)
+#define I2C_SR2_DUALF_Msk (0x1U << I2C_SR2_DUALF_Pos) /*!< 0x00000080 */
+#define I2C_SR2_DUALF I2C_SR2_DUALF_Msk /*!< Dual Flag (Slave mode) */
+#define I2C_SR2_PEC_Pos (8U)
+#define I2C_SR2_PEC_Msk (0xFFU << I2C_SR2_PEC_Pos) /*!< 0x0000FF00 */
+#define I2C_SR2_PEC I2C_SR2_PEC_Msk /*!< Packet Error Checking Register */
+
+/******************* Bit definition for I2C_CCR register ********************/
+#define I2C_CCR_CCR_Pos (0U)
+#define I2C_CCR_CCR_Msk (0xFFFU << I2C_CCR_CCR_Pos) /*!< 0x00000FFF */
+#define I2C_CCR_CCR I2C_CCR_CCR_Msk /*!< Clock Control Register in Fast/Standard mode (Master mode) */
+#define I2C_CCR_DUTY_Pos (14U)
+#define I2C_CCR_DUTY_Msk (0x1U << I2C_CCR_DUTY_Pos) /*!< 0x00004000 */
+#define I2C_CCR_DUTY I2C_CCR_DUTY_Msk /*!< Fast Mode Duty Cycle */
+#define I2C_CCR_FS_Pos (15U)
+#define I2C_CCR_FS_Msk (0x1U << I2C_CCR_FS_Pos) /*!< 0x00008000 */
+#define I2C_CCR_FS I2C_CCR_FS_Msk /*!< I2C Master Mode Selection */
+
+/****************** Bit definition for I2C_TRISE register *******************/
+#define I2C_TRISE_TRISE_Pos (0U)
+#define I2C_TRISE_TRISE_Msk (0x3FU << I2C_TRISE_TRISE_Pos) /*!< 0x0000003F */
+#define I2C_TRISE_TRISE I2C_TRISE_TRISE_Msk /*!< Maximum Rise Time in Fast/Standard mode (Master mode) */
+
+/******************************************************************************/
+/* */
+/* Universal Synchronous Asynchronous Receiver Transmitter */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for USART_SR register *******************/
+#define USART_SR_PE_Pos (0U)
+#define USART_SR_PE_Msk (0x1U << USART_SR_PE_Pos) /*!< 0x00000001 */
+#define USART_SR_PE USART_SR_PE_Msk /*!< Parity Error */
+#define USART_SR_FE_Pos (1U)
+#define USART_SR_FE_Msk (0x1U << USART_SR_FE_Pos) /*!< 0x00000002 */
+#define USART_SR_FE USART_SR_FE_Msk /*!< Framing Error */
+#define USART_SR_NE_Pos (2U)
+#define USART_SR_NE_Msk (0x1U << USART_SR_NE_Pos) /*!< 0x00000004 */
+#define USART_SR_NE USART_SR_NE_Msk /*!< Noise Error Flag */
+#define USART_SR_ORE_Pos (3U)
+#define USART_SR_ORE_Msk (0x1U << USART_SR_ORE_Pos) /*!< 0x00000008 */
+#define USART_SR_ORE USART_SR_ORE_Msk /*!< OverRun Error */
+#define USART_SR_IDLE_Pos (4U)
+#define USART_SR_IDLE_Msk (0x1U << USART_SR_IDLE_Pos) /*!< 0x00000010 */
+#define USART_SR_IDLE USART_SR_IDLE_Msk /*!< IDLE line detected */
+#define USART_SR_RXNE_Pos (5U)
+#define USART_SR_RXNE_Msk (0x1U << USART_SR_RXNE_Pos) /*!< 0x00000020 */
+#define USART_SR_RXNE USART_SR_RXNE_Msk /*!< Read Data Register Not Empty */
+#define USART_SR_TC_Pos (6U)
+#define USART_SR_TC_Msk (0x1U << USART_SR_TC_Pos) /*!< 0x00000040 */
+#define USART_SR_TC USART_SR_TC_Msk /*!< Transmission Complete */
+#define USART_SR_TXE_Pos (7U)
+#define USART_SR_TXE_Msk (0x1U << USART_SR_TXE_Pos) /*!< 0x00000080 */
+#define USART_SR_TXE USART_SR_TXE_Msk /*!< Transmit Data Register Empty */
+#define USART_SR_LBD_Pos (8U)
+#define USART_SR_LBD_Msk (0x1U << USART_SR_LBD_Pos) /*!< 0x00000100 */
+#define USART_SR_LBD USART_SR_LBD_Msk /*!< LIN Break Detection Flag */
+#define USART_SR_CTS_Pos (9U)
+#define USART_SR_CTS_Msk (0x1U << USART_SR_CTS_Pos) /*!< 0x00000200 */
+#define USART_SR_CTS USART_SR_CTS_Msk /*!< CTS Flag */
+
+/******************* Bit definition for USART_DR register *******************/
+#define USART_DR_DR_Pos (0U)
+#define USART_DR_DR_Msk (0x1FFU << USART_DR_DR_Pos) /*!< 0x000001FF */
+#define USART_DR_DR USART_DR_DR_Msk /*!< Data value */
+
+/****************** Bit definition for USART_BRR register *******************/
+#define USART_BRR_DIV_Fraction_Pos (0U)
+#define USART_BRR_DIV_Fraction_Msk (0xFU << USART_BRR_DIV_Fraction_Pos) /*!< 0x0000000F */
+#define USART_BRR_DIV_Fraction USART_BRR_DIV_Fraction_Msk /*!< Fraction of USARTDIV */
+#define USART_BRR_DIV_Mantissa_Pos (4U)
+#define USART_BRR_DIV_Mantissa_Msk (0xFFFU << USART_BRR_DIV_Mantissa_Pos) /*!< 0x0000FFF0 */
+#define USART_BRR_DIV_Mantissa USART_BRR_DIV_Mantissa_Msk /*!< Mantissa of USARTDIV */
+
+/****************** Bit definition for USART_CR1 register *******************/
+#define USART_CR1_SBK_Pos (0U)
+#define USART_CR1_SBK_Msk (0x1U << USART_CR1_SBK_Pos) /*!< 0x00000001 */
+#define USART_CR1_SBK USART_CR1_SBK_Msk /*!< Send Break */
+#define USART_CR1_RWU_Pos (1U)
+#define USART_CR1_RWU_Msk (0x1U << USART_CR1_RWU_Pos) /*!< 0x00000002 */
+#define USART_CR1_RWU USART_CR1_RWU_Msk /*!< Receiver wakeup */
+#define USART_CR1_RE_Pos (2U)
+#define USART_CR1_RE_Msk (0x1U << USART_CR1_RE_Pos) /*!< 0x00000004 */
+#define USART_CR1_RE USART_CR1_RE_Msk /*!< Receiver Enable */
+#define USART_CR1_TE_Pos (3U)
+#define USART_CR1_TE_Msk (0x1U << USART_CR1_TE_Pos) /*!< 0x00000008 */
+#define USART_CR1_TE USART_CR1_TE_Msk /*!< Transmitter Enable */
+#define USART_CR1_IDLEIE_Pos (4U)
+#define USART_CR1_IDLEIE_Msk (0x1U << USART_CR1_IDLEIE_Pos) /*!< 0x00000010 */
+#define USART_CR1_IDLEIE USART_CR1_IDLEIE_Msk /*!< IDLE Interrupt Enable */
+#define USART_CR1_RXNEIE_Pos (5U)
+#define USART_CR1_RXNEIE_Msk (0x1U << USART_CR1_RXNEIE_Pos) /*!< 0x00000020 */
+#define USART_CR1_RXNEIE USART_CR1_RXNEIE_Msk /*!< RXNE Interrupt Enable */
+#define USART_CR1_TCIE_Pos (6U)
+#define USART_CR1_TCIE_Msk (0x1U << USART_CR1_TCIE_Pos) /*!< 0x00000040 */
+#define USART_CR1_TCIE USART_CR1_TCIE_Msk /*!< Transmission Complete Interrupt Enable */
+#define USART_CR1_TXEIE_Pos (7U)
+#define USART_CR1_TXEIE_Msk (0x1U << USART_CR1_TXEIE_Pos) /*!< 0x00000080 */
+#define USART_CR1_TXEIE USART_CR1_TXEIE_Msk /*!< PE Interrupt Enable */
+#define USART_CR1_PEIE_Pos (8U)
+#define USART_CR1_PEIE_Msk (0x1U << USART_CR1_PEIE_Pos) /*!< 0x00000100 */
+#define USART_CR1_PEIE USART_CR1_PEIE_Msk /*!< PE Interrupt Enable */
+#define USART_CR1_PS_Pos (9U)
+#define USART_CR1_PS_Msk (0x1U << USART_CR1_PS_Pos) /*!< 0x00000200 */
+#define USART_CR1_PS USART_CR1_PS_Msk /*!< Parity Selection */
+#define USART_CR1_PCE_Pos (10U)
+#define USART_CR1_PCE_Msk (0x1U << USART_CR1_PCE_Pos) /*!< 0x00000400 */
+#define USART_CR1_PCE USART_CR1_PCE_Msk /*!< Parity Control Enable */
+#define USART_CR1_WAKE_Pos (11U)
+#define USART_CR1_WAKE_Msk (0x1U << USART_CR1_WAKE_Pos) /*!< 0x00000800 */
+#define USART_CR1_WAKE USART_CR1_WAKE_Msk /*!< Wakeup method */
+#define USART_CR1_M_Pos (12U)
+#define USART_CR1_M_Msk (0x1U << USART_CR1_M_Pos) /*!< 0x00001000 */
+#define USART_CR1_M USART_CR1_M_Msk /*!< Word length */
+#define USART_CR1_UE_Pos (13U)
+#define USART_CR1_UE_Msk (0x1U << USART_CR1_UE_Pos) /*!< 0x00002000 */
+#define USART_CR1_UE USART_CR1_UE_Msk /*!< USART Enable */
+
+/****************** Bit definition for USART_CR2 register *******************/
+#define USART_CR2_ADD_Pos (0U)
+#define USART_CR2_ADD_Msk (0xFU << USART_CR2_ADD_Pos) /*!< 0x0000000F */
+#define USART_CR2_ADD USART_CR2_ADD_Msk /*!< Address of the USART node */
+#define USART_CR2_LBDL_Pos (5U)
+#define USART_CR2_LBDL_Msk (0x1U << USART_CR2_LBDL_Pos) /*!< 0x00000020 */
+#define USART_CR2_LBDL USART_CR2_LBDL_Msk /*!< LIN Break Detection Length */
+#define USART_CR2_LBDIE_Pos (6U)
+#define USART_CR2_LBDIE_Msk (0x1U << USART_CR2_LBDIE_Pos) /*!< 0x00000040 */
+#define USART_CR2_LBDIE USART_CR2_LBDIE_Msk /*!< LIN Break Detection Interrupt Enable */
+#define USART_CR2_LBCL_Pos (8U)
+#define USART_CR2_LBCL_Msk (0x1U << USART_CR2_LBCL_Pos) /*!< 0x00000100 */
+#define USART_CR2_LBCL USART_CR2_LBCL_Msk /*!< Last Bit Clock pulse */
+#define USART_CR2_CPHA_Pos (9U)
+#define USART_CR2_CPHA_Msk (0x1U << USART_CR2_CPHA_Pos) /*!< 0x00000200 */
+#define USART_CR2_CPHA USART_CR2_CPHA_Msk /*!< Clock Phase */
+#define USART_CR2_CPOL_Pos (10U)
+#define USART_CR2_CPOL_Msk (0x1U << USART_CR2_CPOL_Pos) /*!< 0x00000400 */
+#define USART_CR2_CPOL USART_CR2_CPOL_Msk /*!< Clock Polarity */
+#define USART_CR2_CLKEN_Pos (11U)
+#define USART_CR2_CLKEN_Msk (0x1U << USART_CR2_CLKEN_Pos) /*!< 0x00000800 */
+#define USART_CR2_CLKEN USART_CR2_CLKEN_Msk /*!< Clock Enable */
+
+#define USART_CR2_STOP_Pos (12U)
+#define USART_CR2_STOP_Msk (0x3U << USART_CR2_STOP_Pos) /*!< 0x00003000 */
+#define USART_CR2_STOP USART_CR2_STOP_Msk /*!< STOP[1:0] bits (STOP bits) */
+#define USART_CR2_STOP_0 (0x1U << USART_CR2_STOP_Pos) /*!< 0x00001000 */
+#define USART_CR2_STOP_1 (0x2U << USART_CR2_STOP_Pos) /*!< 0x00002000 */
+
+#define USART_CR2_LINEN_Pos (14U)
+#define USART_CR2_LINEN_Msk (0x1U << USART_CR2_LINEN_Pos) /*!< 0x00004000 */
+#define USART_CR2_LINEN USART_CR2_LINEN_Msk /*!< LIN mode enable */
+
+/****************** Bit definition for USART_CR3 register *******************/
+#define USART_CR3_EIE_Pos (0U)
+#define USART_CR3_EIE_Msk (0x1U << USART_CR3_EIE_Pos) /*!< 0x00000001 */
+#define USART_CR3_EIE USART_CR3_EIE_Msk /*!< Error Interrupt Enable */
+#define USART_CR3_IREN_Pos (1U)
+#define USART_CR3_IREN_Msk (0x1U << USART_CR3_IREN_Pos) /*!< 0x00000002 */
+#define USART_CR3_IREN USART_CR3_IREN_Msk /*!< IrDA mode Enable */
+#define USART_CR3_IRLP_Pos (2U)
+#define USART_CR3_IRLP_Msk (0x1U << USART_CR3_IRLP_Pos) /*!< 0x00000004 */
+#define USART_CR3_IRLP USART_CR3_IRLP_Msk /*!< IrDA Low-Power */
+#define USART_CR3_HDSEL_Pos (3U)
+#define USART_CR3_HDSEL_Msk (0x1U << USART_CR3_HDSEL_Pos) /*!< 0x00000008 */
+#define USART_CR3_HDSEL USART_CR3_HDSEL_Msk /*!< Half-Duplex Selection */
+#define USART_CR3_NACK_Pos (4U)
+#define USART_CR3_NACK_Msk (0x1U << USART_CR3_NACK_Pos) /*!< 0x00000010 */
+#define USART_CR3_NACK USART_CR3_NACK_Msk /*!< Smartcard NACK enable */
+#define USART_CR3_SCEN_Pos (5U)
+#define USART_CR3_SCEN_Msk (0x1U << USART_CR3_SCEN_Pos) /*!< 0x00000020 */
+#define USART_CR3_SCEN USART_CR3_SCEN_Msk /*!< Smartcard mode enable */
+#define USART_CR3_DMAR_Pos (6U)
+#define USART_CR3_DMAR_Msk (0x1U << USART_CR3_DMAR_Pos) /*!< 0x00000040 */
+#define USART_CR3_DMAR USART_CR3_DMAR_Msk /*!< DMA Enable Receiver */
+#define USART_CR3_DMAT_Pos (7U)
+#define USART_CR3_DMAT_Msk (0x1U << USART_CR3_DMAT_Pos) /*!< 0x00000080 */
+#define USART_CR3_DMAT USART_CR3_DMAT_Msk /*!< DMA Enable Transmitter */
+#define USART_CR3_RTSE_Pos (8U)
+#define USART_CR3_RTSE_Msk (0x1U << USART_CR3_RTSE_Pos) /*!< 0x00000100 */
+#define USART_CR3_RTSE USART_CR3_RTSE_Msk /*!< RTS Enable */
+#define USART_CR3_CTSE_Pos (9U)
+#define USART_CR3_CTSE_Msk (0x1U << USART_CR3_CTSE_Pos) /*!< 0x00000200 */
+#define USART_CR3_CTSE USART_CR3_CTSE_Msk /*!< CTS Enable */
+#define USART_CR3_CTSIE_Pos (10U)
+#define USART_CR3_CTSIE_Msk (0x1U << USART_CR3_CTSIE_Pos) /*!< 0x00000400 */
+#define USART_CR3_CTSIE USART_CR3_CTSIE_Msk /*!< CTS Interrupt Enable */
+
+/****************** Bit definition for USART_GTPR register ******************/
+#define USART_GTPR_PSC_Pos (0U)
+#define USART_GTPR_PSC_Msk (0xFFU << USART_GTPR_PSC_Pos) /*!< 0x000000FF */
+#define USART_GTPR_PSC USART_GTPR_PSC_Msk /*!< PSC[7:0] bits (Prescaler value) */
+#define USART_GTPR_PSC_0 (0x01U << USART_GTPR_PSC_Pos) /*!< 0x00000001 */
+#define USART_GTPR_PSC_1 (0x02U << USART_GTPR_PSC_Pos) /*!< 0x00000002 */
+#define USART_GTPR_PSC_2 (0x04U << USART_GTPR_PSC_Pos) /*!< 0x00000004 */
+#define USART_GTPR_PSC_3 (0x08U << USART_GTPR_PSC_Pos) /*!< 0x00000008 */
+#define USART_GTPR_PSC_4 (0x10U << USART_GTPR_PSC_Pos) /*!< 0x00000010 */
+#define USART_GTPR_PSC_5 (0x20U << USART_GTPR_PSC_Pos) /*!< 0x00000020 */
+#define USART_GTPR_PSC_6 (0x40U << USART_GTPR_PSC_Pos) /*!< 0x00000040 */
+#define USART_GTPR_PSC_7 (0x80U << USART_GTPR_PSC_Pos) /*!< 0x00000080 */
+
+#define USART_GTPR_GT_Pos (8U)
+#define USART_GTPR_GT_Msk (0xFFU << USART_GTPR_GT_Pos) /*!< 0x0000FF00 */
+#define USART_GTPR_GT USART_GTPR_GT_Msk /*!< Guard time value */
+
+/******************************************************************************/
+/* */
+/* Debug MCU */
+/* */
+/******************************************************************************/
+
+/**************** Bit definition for DBGMCU_IDCODE register *****************/
+#define DBGMCU_IDCODE_DEV_ID_Pos (0U)
+#define DBGMCU_IDCODE_DEV_ID_Msk (0xFFFU << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */
+#define DBGMCU_IDCODE_DEV_ID DBGMCU_IDCODE_DEV_ID_Msk /*!< Device Identifier */
+
+#define DBGMCU_IDCODE_REV_ID_Pos (16U)
+#define DBGMCU_IDCODE_REV_ID_Msk (0xFFFFU << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */
+#define DBGMCU_IDCODE_REV_ID DBGMCU_IDCODE_REV_ID_Msk /*!< REV_ID[15:0] bits (Revision Identifier) */
+#define DBGMCU_IDCODE_REV_ID_0 (0x0001U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00010000 */
+#define DBGMCU_IDCODE_REV_ID_1 (0x0002U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00020000 */
+#define DBGMCU_IDCODE_REV_ID_2 (0x0004U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00040000 */
+#define DBGMCU_IDCODE_REV_ID_3 (0x0008U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00080000 */
+#define DBGMCU_IDCODE_REV_ID_4 (0x0010U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00100000 */
+#define DBGMCU_IDCODE_REV_ID_5 (0x0020U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00200000 */
+#define DBGMCU_IDCODE_REV_ID_6 (0x0040U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00400000 */
+#define DBGMCU_IDCODE_REV_ID_7 (0x0080U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00800000 */
+#define DBGMCU_IDCODE_REV_ID_8 (0x0100U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x01000000 */
+#define DBGMCU_IDCODE_REV_ID_9 (0x0200U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x02000000 */
+#define DBGMCU_IDCODE_REV_ID_10 (0x0400U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x04000000 */
+#define DBGMCU_IDCODE_REV_ID_11 (0x0800U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x08000000 */
+#define DBGMCU_IDCODE_REV_ID_12 (0x1000U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x10000000 */
+#define DBGMCU_IDCODE_REV_ID_13 (0x2000U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x20000000 */
+#define DBGMCU_IDCODE_REV_ID_14 (0x4000U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x40000000 */
+#define DBGMCU_IDCODE_REV_ID_15 (0x8000U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x80000000 */
+
+/****************** Bit definition for DBGMCU_CR register *******************/
+#define DBGMCU_CR_DBG_SLEEP_Pos (0U)
+#define DBGMCU_CR_DBG_SLEEP_Msk (0x1U << DBGMCU_CR_DBG_SLEEP_Pos) /*!< 0x00000001 */
+#define DBGMCU_CR_DBG_SLEEP DBGMCU_CR_DBG_SLEEP_Msk /*!< Debug Sleep Mode */
+#define DBGMCU_CR_DBG_STOP_Pos (1U)
+#define DBGMCU_CR_DBG_STOP_Msk (0x1U << DBGMCU_CR_DBG_STOP_Pos) /*!< 0x00000002 */
+#define DBGMCU_CR_DBG_STOP DBGMCU_CR_DBG_STOP_Msk /*!< Debug Stop Mode */
+#define DBGMCU_CR_DBG_STANDBY_Pos (2U)
+#define DBGMCU_CR_DBG_STANDBY_Msk (0x1U << DBGMCU_CR_DBG_STANDBY_Pos) /*!< 0x00000004 */
+#define DBGMCU_CR_DBG_STANDBY DBGMCU_CR_DBG_STANDBY_Msk /*!< Debug Standby mode */
+#define DBGMCU_CR_TRACE_IOEN_Pos (5U)
+#define DBGMCU_CR_TRACE_IOEN_Msk (0x1U << DBGMCU_CR_TRACE_IOEN_Pos) /*!< 0x00000020 */
+#define DBGMCU_CR_TRACE_IOEN DBGMCU_CR_TRACE_IOEN_Msk /*!< Trace Pin Assignment Control */
+
+#define DBGMCU_CR_TRACE_MODE_Pos (6U)
+#define DBGMCU_CR_TRACE_MODE_Msk (0x3U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x000000C0 */
+#define DBGMCU_CR_TRACE_MODE DBGMCU_CR_TRACE_MODE_Msk /*!< TRACE_MODE[1:0] bits (Trace Pin Assignment Control) */
+#define DBGMCU_CR_TRACE_MODE_0 (0x1U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000040 */
+#define DBGMCU_CR_TRACE_MODE_1 (0x2U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000080 */
+
+#define DBGMCU_CR_DBG_IWDG_STOP_Pos (8U)
+#define DBGMCU_CR_DBG_IWDG_STOP_Msk (0x1U << DBGMCU_CR_DBG_IWDG_STOP_Pos) /*!< 0x00000100 */
+#define DBGMCU_CR_DBG_IWDG_STOP DBGMCU_CR_DBG_IWDG_STOP_Msk /*!< Debug Independent Watchdog stopped when Core is halted */
+#define DBGMCU_CR_DBG_WWDG_STOP_Pos (9U)
+#define DBGMCU_CR_DBG_WWDG_STOP_Msk (0x1U << DBGMCU_CR_DBG_WWDG_STOP_Pos) /*!< 0x00000200 */
+#define DBGMCU_CR_DBG_WWDG_STOP DBGMCU_CR_DBG_WWDG_STOP_Msk /*!< Debug Window Watchdog stopped when Core is halted */
+#define DBGMCU_CR_DBG_TIM1_STOP_Pos (10U)
+#define DBGMCU_CR_DBG_TIM1_STOP_Msk (0x1U << DBGMCU_CR_DBG_TIM1_STOP_Pos) /*!< 0x00000400 */
+#define DBGMCU_CR_DBG_TIM1_STOP DBGMCU_CR_DBG_TIM1_STOP_Msk /*!< TIM1 counter stopped when core is halted */
+#define DBGMCU_CR_DBG_TIM2_STOP_Pos (11U)
+#define DBGMCU_CR_DBG_TIM2_STOP_Msk (0x1U << DBGMCU_CR_DBG_TIM2_STOP_Pos) /*!< 0x00000800 */
+#define DBGMCU_CR_DBG_TIM2_STOP DBGMCU_CR_DBG_TIM2_STOP_Msk /*!< TIM2 counter stopped when core is halted */
+#define DBGMCU_CR_DBG_TIM3_STOP_Pos (12U)
+#define DBGMCU_CR_DBG_TIM3_STOP_Msk (0x1U << DBGMCU_CR_DBG_TIM3_STOP_Pos) /*!< 0x00001000 */
+#define DBGMCU_CR_DBG_TIM3_STOP DBGMCU_CR_DBG_TIM3_STOP_Msk /*!< TIM3 counter stopped when core is halted */
+#define DBGMCU_CR_DBG_TIM4_STOP_Pos (13U)
+#define DBGMCU_CR_DBG_TIM4_STOP_Msk (0x1U << DBGMCU_CR_DBG_TIM4_STOP_Pos) /*!< 0x00002000 */
+#define DBGMCU_CR_DBG_TIM4_STOP DBGMCU_CR_DBG_TIM4_STOP_Msk /*!< TIM4 counter stopped when core is halted */
+#define DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT_Pos (15U)
+#define DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT_Msk (0x1U << DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT_Pos) /*!< 0x00008000 */
+#define DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT_Msk /*!< SMBUS timeout mode stopped when Core is halted */
+#define DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT_Pos (16U)
+#define DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT_Msk (0x1U << DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT_Pos) /*!< 0x00010000 */
+#define DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT_Msk /*!< SMBUS timeout mode stopped when Core is halted */
+#define DBGMCU_CR_DBG_TIM5_STOP_Pos (18U)
+#define DBGMCU_CR_DBG_TIM5_STOP_Msk (0x1U << DBGMCU_CR_DBG_TIM5_STOP_Pos) /*!< 0x00040000 */
+#define DBGMCU_CR_DBG_TIM5_STOP DBGMCU_CR_DBG_TIM5_STOP_Msk /*!< TIM5 counter stopped when core is halted */
+#define DBGMCU_CR_DBG_TIM6_STOP_Pos (19U)
+#define DBGMCU_CR_DBG_TIM6_STOP_Msk (0x1U << DBGMCU_CR_DBG_TIM6_STOP_Pos) /*!< 0x00080000 */
+#define DBGMCU_CR_DBG_TIM6_STOP DBGMCU_CR_DBG_TIM6_STOP_Msk /*!< TIM6 counter stopped when core is halted */
+#define DBGMCU_CR_DBG_TIM7_STOP_Pos (20U)
+#define DBGMCU_CR_DBG_TIM7_STOP_Msk (0x1U << DBGMCU_CR_DBG_TIM7_STOP_Pos) /*!< 0x00100000 */
+#define DBGMCU_CR_DBG_TIM7_STOP DBGMCU_CR_DBG_TIM7_STOP_Msk /*!< TIM7 counter stopped when core is halted */
+#define DBGMCU_CR_DBG_TIM15_STOP_Pos (22U)
+#define DBGMCU_CR_DBG_TIM15_STOP_Msk (0x1U << DBGMCU_CR_DBG_TIM15_STOP_Pos) /*!< 0x00400000 */
+#define DBGMCU_CR_DBG_TIM15_STOP DBGMCU_CR_DBG_TIM15_STOP_Msk /*!< Debug TIM15 stopped when Core is halted */
+#define DBGMCU_CR_DBG_TIM16_STOP_Pos (23U)
+#define DBGMCU_CR_DBG_TIM16_STOP_Msk (0x1U << DBGMCU_CR_DBG_TIM16_STOP_Pos) /*!< 0x00800000 */
+#define DBGMCU_CR_DBG_TIM16_STOP DBGMCU_CR_DBG_TIM16_STOP_Msk /*!< Debug TIM16 stopped when Core is halted */
+#define DBGMCU_CR_DBG_TIM17_STOP_Pos (24U)
+#define DBGMCU_CR_DBG_TIM17_STOP_Msk (0x1U << DBGMCU_CR_DBG_TIM17_STOP_Pos) /*!< 0x01000000 */
+#define DBGMCU_CR_DBG_TIM17_STOP DBGMCU_CR_DBG_TIM17_STOP_Msk /*!< Debug TIM17 stopped when Core is halted */
+#define DBGMCU_CR_DBG_TIM12_STOP_Pos (25U)
+#define DBGMCU_CR_DBG_TIM12_STOP_Msk (0x1U << DBGMCU_CR_DBG_TIM12_STOP_Pos) /*!< 0x02000000 */
+#define DBGMCU_CR_DBG_TIM12_STOP DBGMCU_CR_DBG_TIM12_STOP_Msk /*!< Debug TIM12 stopped when Core is halted */
+#define DBGMCU_CR_DBG_TIM13_STOP_Pos (26U)
+#define DBGMCU_CR_DBG_TIM13_STOP_Msk (0x1U << DBGMCU_CR_DBG_TIM13_STOP_Pos) /*!< 0x04000000 */
+#define DBGMCU_CR_DBG_TIM13_STOP DBGMCU_CR_DBG_TIM13_STOP_Msk /*!< Debug TIM13 stopped when Core is halted */
+#define DBGMCU_CR_DBG_TIM14_STOP_Pos (27U)
+#define DBGMCU_CR_DBG_TIM14_STOP_Msk (0x1U << DBGMCU_CR_DBG_TIM14_STOP_Pos) /*!< 0x08000000 */
+#define DBGMCU_CR_DBG_TIM14_STOP DBGMCU_CR_DBG_TIM14_STOP_Msk /*!< Debug TIM14 stopped when Core is halted */
+
+/******************************************************************************/
+/* */
+/* FLASH and Option Bytes Registers */
+/* */
+/******************************************************************************/
+/******************* Bit definition for FLASH_ACR register ******************/
+#define FLASH_ACR_HLFCYA_Pos (3U)
+#define FLASH_ACR_HLFCYA_Msk (0x1U << FLASH_ACR_HLFCYA_Pos) /*!< 0x00000008 */
+#define FLASH_ACR_HLFCYA FLASH_ACR_HLFCYA_Msk /*!< Flash Half Cycle Access Enable */
+
+/****************** Bit definition for FLASH_KEYR register ******************/
+#define FLASH_KEYR_FKEYR_Pos (0U)
+#define FLASH_KEYR_FKEYR_Msk (0xFFFFFFFFU << FLASH_KEYR_FKEYR_Pos) /*!< 0xFFFFFFFF */
+#define FLASH_KEYR_FKEYR FLASH_KEYR_FKEYR_Msk /*!< FPEC Key */
+
+#define RDP_KEY_Pos (0U)
+#define RDP_KEY_Msk (0xA5U << RDP_KEY_Pos) /*!< 0x000000A5 */
+#define RDP_KEY RDP_KEY_Msk /*!< RDP Key */
+#define FLASH_KEY1_Pos (0U)
+#define FLASH_KEY1_Msk (0x45670123U << FLASH_KEY1_Pos) /*!< 0x45670123 */
+#define FLASH_KEY1 FLASH_KEY1_Msk /*!< FPEC Key1 */
+#define FLASH_KEY2_Pos (0U)
+#define FLASH_KEY2_Msk (0xCDEF89ABU << FLASH_KEY2_Pos) /*!< 0xCDEF89AB */
+#define FLASH_KEY2 FLASH_KEY2_Msk /*!< FPEC Key2 */
+
+/***************** Bit definition for FLASH_OPTKEYR register ****************/
+#define FLASH_OPTKEYR_OPTKEYR_Pos (0U)
+#define FLASH_OPTKEYR_OPTKEYR_Msk (0xFFFFFFFFU << FLASH_OPTKEYR_OPTKEYR_Pos) /*!< 0xFFFFFFFF */
+#define FLASH_OPTKEYR_OPTKEYR FLASH_OPTKEYR_OPTKEYR_Msk /*!< Option Byte Key */
+
+#define FLASH_OPTKEY1 FLASH_KEY1 /*!< Option Byte Key1 */
+#define FLASH_OPTKEY2 FLASH_KEY2 /*!< Option Byte Key2 */
+
+/****************** Bit definition for FLASH_SR register ********************/
+#define FLASH_SR_BSY_Pos (0U)
+#define FLASH_SR_BSY_Msk (0x1U << FLASH_SR_BSY_Pos) /*!< 0x00000001 */
+#define FLASH_SR_BSY FLASH_SR_BSY_Msk /*!< Busy */
+#define FLASH_SR_PGERR_Pos (2U)
+#define FLASH_SR_PGERR_Msk (0x1U << FLASH_SR_PGERR_Pos) /*!< 0x00000004 */
+#define FLASH_SR_PGERR FLASH_SR_PGERR_Msk /*!< Programming Error */
+#define FLASH_SR_WRPRTERR_Pos (4U)
+#define FLASH_SR_WRPRTERR_Msk (0x1U << FLASH_SR_WRPRTERR_Pos) /*!< 0x00000010 */
+#define FLASH_SR_WRPRTERR FLASH_SR_WRPRTERR_Msk /*!< Write Protection Error */
+#define FLASH_SR_EOP_Pos (5U)
+#define FLASH_SR_EOP_Msk (0x1U << FLASH_SR_EOP_Pos) /*!< 0x00000020 */
+#define FLASH_SR_EOP FLASH_SR_EOP_Msk /*!< End of operation */
+
+/******************* Bit definition for FLASH_CR register *******************/
+#define FLASH_CR_PG_Pos (0U)
+#define FLASH_CR_PG_Msk (0x1U << FLASH_CR_PG_Pos) /*!< 0x00000001 */
+#define FLASH_CR_PG FLASH_CR_PG_Msk /*!< Programming */
+#define FLASH_CR_PER_Pos (1U)
+#define FLASH_CR_PER_Msk (0x1U << FLASH_CR_PER_Pos) /*!< 0x00000002 */
+#define FLASH_CR_PER FLASH_CR_PER_Msk /*!< Page Erase */
+#define FLASH_CR_MER_Pos (2U)
+#define FLASH_CR_MER_Msk (0x1U << FLASH_CR_MER_Pos) /*!< 0x00000004 */
+#define FLASH_CR_MER FLASH_CR_MER_Msk /*!< Mass Erase */
+#define FLASH_CR_OPTPG_Pos (4U)
+#define FLASH_CR_OPTPG_Msk (0x1U << FLASH_CR_OPTPG_Pos) /*!< 0x00000010 */
+#define FLASH_CR_OPTPG FLASH_CR_OPTPG_Msk /*!< Option Byte Programming */
+#define FLASH_CR_OPTER_Pos (5U)
+#define FLASH_CR_OPTER_Msk (0x1U << FLASH_CR_OPTER_Pos) /*!< 0x00000020 */
+#define FLASH_CR_OPTER FLASH_CR_OPTER_Msk /*!< Option Byte Erase */
+#define FLASH_CR_STRT_Pos (6U)
+#define FLASH_CR_STRT_Msk (0x1U << FLASH_CR_STRT_Pos) /*!< 0x00000040 */
+#define FLASH_CR_STRT FLASH_CR_STRT_Msk /*!< Start */
+#define FLASH_CR_LOCK_Pos (7U)
+#define FLASH_CR_LOCK_Msk (0x1U << FLASH_CR_LOCK_Pos) /*!< 0x00000080 */
+#define FLASH_CR_LOCK FLASH_CR_LOCK_Msk /*!< Lock */
+#define FLASH_CR_OPTWRE_Pos (9U)
+#define FLASH_CR_OPTWRE_Msk (0x1U << FLASH_CR_OPTWRE_Pos) /*!< 0x00000200 */
+#define FLASH_CR_OPTWRE FLASH_CR_OPTWRE_Msk /*!< Option Bytes Write Enable */
+#define FLASH_CR_ERRIE_Pos (10U)
+#define FLASH_CR_ERRIE_Msk (0x1U << FLASH_CR_ERRIE_Pos) /*!< 0x00000400 */
+#define FLASH_CR_ERRIE FLASH_CR_ERRIE_Msk /*!< Error Interrupt Enable */
+#define FLASH_CR_EOPIE_Pos (12U)
+#define FLASH_CR_EOPIE_Msk (0x1U << FLASH_CR_EOPIE_Pos) /*!< 0x00001000 */
+#define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk /*!< End of operation interrupt enable */
+
+/******************* Bit definition for FLASH_AR register *******************/
+#define FLASH_AR_FAR_Pos (0U)
+#define FLASH_AR_FAR_Msk (0xFFFFFFFFU << FLASH_AR_FAR_Pos) /*!< 0xFFFFFFFF */
+#define FLASH_AR_FAR FLASH_AR_FAR_Msk /*!< Flash Address */
+
+/****************** Bit definition for FLASH_OBR register *******************/
+#define FLASH_OBR_OPTERR_Pos (0U)
+#define FLASH_OBR_OPTERR_Msk (0x1U << FLASH_OBR_OPTERR_Pos) /*!< 0x00000001 */
+#define FLASH_OBR_OPTERR FLASH_OBR_OPTERR_Msk /*!< Option Byte Error */
+#define FLASH_OBR_RDPRT_Pos (1U)
+#define FLASH_OBR_RDPRT_Msk (0x1U << FLASH_OBR_RDPRT_Pos) /*!< 0x00000002 */
+#define FLASH_OBR_RDPRT FLASH_OBR_RDPRT_Msk /*!< Read protection */
+
+#define FLASH_OBR_IWDG_SW_Pos (2U)
+#define FLASH_OBR_IWDG_SW_Msk (0x1U << FLASH_OBR_IWDG_SW_Pos) /*!< 0x00000004 */
+#define FLASH_OBR_IWDG_SW FLASH_OBR_IWDG_SW_Msk /*!< IWDG SW */
+#define FLASH_OBR_nRST_STOP_Pos (3U)
+#define FLASH_OBR_nRST_STOP_Msk (0x1U << FLASH_OBR_nRST_STOP_Pos) /*!< 0x00000008 */
+#define FLASH_OBR_nRST_STOP FLASH_OBR_nRST_STOP_Msk /*!< nRST_STOP */
+#define FLASH_OBR_nRST_STDBY_Pos (4U)
+#define FLASH_OBR_nRST_STDBY_Msk (0x1U << FLASH_OBR_nRST_STDBY_Pos) /*!< 0x00000010 */
+#define FLASH_OBR_nRST_STDBY FLASH_OBR_nRST_STDBY_Msk /*!< nRST_STDBY */
+#define FLASH_OBR_USER_Pos (2U)
+#define FLASH_OBR_USER_Msk (0x7U << FLASH_OBR_USER_Pos) /*!< 0x0000001C */
+#define FLASH_OBR_USER FLASH_OBR_USER_Msk /*!< User Option Bytes */
+#define FLASH_OBR_DATA0_Pos (10U)
+#define FLASH_OBR_DATA0_Msk (0xFFU << FLASH_OBR_DATA0_Pos) /*!< 0x0003FC00 */
+#define FLASH_OBR_DATA0 FLASH_OBR_DATA0_Msk /*!< Data0 */
+#define FLASH_OBR_DATA1_Pos (18U)
+#define FLASH_OBR_DATA1_Msk (0xFFU << FLASH_OBR_DATA1_Pos) /*!< 0x03FC0000 */
+#define FLASH_OBR_DATA1 FLASH_OBR_DATA1_Msk /*!< Data1 */
+
+/****************** Bit definition for FLASH_WRPR register ******************/
+#define FLASH_WRPR_WRP_Pos (0U)
+#define FLASH_WRPR_WRP_Msk (0xFFFFFFFFU << FLASH_WRPR_WRP_Pos) /*!< 0xFFFFFFFF */
+#define FLASH_WRPR_WRP FLASH_WRPR_WRP_Msk /*!< Write Protect */
+
+/*----------------------------------------------------------------------------*/
+
+/****************** Bit definition for FLASH_RDP register *******************/
+#define FLASH_RDP_RDP_Pos (0U)
+#define FLASH_RDP_RDP_Msk (0xFFU << FLASH_RDP_RDP_Pos) /*!< 0x000000FF */
+#define FLASH_RDP_RDP FLASH_RDP_RDP_Msk /*!< Read protection option byte */
+#define FLASH_RDP_nRDP_Pos (8U)
+#define FLASH_RDP_nRDP_Msk (0xFFU << FLASH_RDP_nRDP_Pos) /*!< 0x0000FF00 */
+#define FLASH_RDP_nRDP FLASH_RDP_nRDP_Msk /*!< Read protection complemented option byte */
+
+/****************** Bit definition for FLASH_USER register ******************/
+#define FLASH_USER_USER_Pos (16U)
+#define FLASH_USER_USER_Msk (0xFFU << FLASH_USER_USER_Pos) /*!< 0x00FF0000 */
+#define FLASH_USER_USER FLASH_USER_USER_Msk /*!< User option byte */
+#define FLASH_USER_nUSER_Pos (24U)
+#define FLASH_USER_nUSER_Msk (0xFFU << FLASH_USER_nUSER_Pos) /*!< 0xFF000000 */
+#define FLASH_USER_nUSER FLASH_USER_nUSER_Msk /*!< User complemented option byte */
+
+/****************** Bit definition for FLASH_Data0 register *****************/
+#define FLASH_DATA0_DATA0_Pos (0U)
+#define FLASH_DATA0_DATA0_Msk (0xFFU << FLASH_DATA0_DATA0_Pos) /*!< 0x000000FF */
+#define FLASH_DATA0_DATA0 FLASH_DATA0_DATA0_Msk /*!< User data storage option byte */
+#define FLASH_DATA0_nDATA0_Pos (8U)
+#define FLASH_DATA0_nDATA0_Msk (0xFFU << FLASH_DATA0_nDATA0_Pos) /*!< 0x0000FF00 */
+#define FLASH_DATA0_nDATA0 FLASH_DATA0_nDATA0_Msk /*!< User data storage complemented option byte */
+
+/****************** Bit definition for FLASH_Data1 register *****************/
+#define FLASH_DATA1_DATA1_Pos (16U)
+#define FLASH_DATA1_DATA1_Msk (0xFFU << FLASH_DATA1_DATA1_Pos) /*!< 0x00FF0000 */
+#define FLASH_DATA1_DATA1 FLASH_DATA1_DATA1_Msk /*!< User data storage option byte */
+#define FLASH_DATA1_nDATA1_Pos (24U)
+#define FLASH_DATA1_nDATA1_Msk (0xFFU << FLASH_DATA1_nDATA1_Pos) /*!< 0xFF000000 */
+#define FLASH_DATA1_nDATA1 FLASH_DATA1_nDATA1_Msk /*!< User data storage complemented option byte */
+
+/****************** Bit definition for FLASH_WRP0 register ******************/
+#define FLASH_WRP0_WRP0_Pos (0U)
+#define FLASH_WRP0_WRP0_Msk (0xFFU << FLASH_WRP0_WRP0_Pos) /*!< 0x000000FF */
+#define FLASH_WRP0_WRP0 FLASH_WRP0_WRP0_Msk /*!< Flash memory write protection option bytes */
+#define FLASH_WRP0_nWRP0_Pos (8U)
+#define FLASH_WRP0_nWRP0_Msk (0xFFU << FLASH_WRP0_nWRP0_Pos) /*!< 0x0000FF00 */
+#define FLASH_WRP0_nWRP0 FLASH_WRP0_nWRP0_Msk /*!< Flash memory write protection complemented option bytes */
+
+/****************** Bit definition for FLASH_WRP1 register ******************/
+#define FLASH_WRP1_WRP1_Pos (16U)
+#define FLASH_WRP1_WRP1_Msk (0xFFU << FLASH_WRP1_WRP1_Pos) /*!< 0x00FF0000 */
+#define FLASH_WRP1_WRP1 FLASH_WRP1_WRP1_Msk /*!< Flash memory write protection option bytes */
+#define FLASH_WRP1_nWRP1_Pos (24U)
+#define FLASH_WRP1_nWRP1_Msk (0xFFU << FLASH_WRP1_nWRP1_Pos) /*!< 0xFF000000 */
+#define FLASH_WRP1_nWRP1 FLASH_WRP1_nWRP1_Msk /*!< Flash memory write protection complemented option bytes */
+
+/****************** Bit definition for FLASH_WRP2 register ******************/
+#define FLASH_WRP2_WRP2_Pos (0U)
+#define FLASH_WRP2_WRP2_Msk (0xFFU << FLASH_WRP2_WRP2_Pos) /*!< 0x000000FF */
+#define FLASH_WRP2_WRP2 FLASH_WRP2_WRP2_Msk /*!< Flash memory write protection option bytes */
+#define FLASH_WRP2_nWRP2_Pos (8U)
+#define FLASH_WRP2_nWRP2_Msk (0xFFU << FLASH_WRP2_nWRP2_Pos) /*!< 0x0000FF00 */
+#define FLASH_WRP2_nWRP2 FLASH_WRP2_nWRP2_Msk /*!< Flash memory write protection complemented option bytes */
+
+/****************** Bit definition for FLASH_WRP3 register ******************/
+#define FLASH_WRP3_WRP3_Pos (16U)
+#define FLASH_WRP3_WRP3_Msk (0xFFU << FLASH_WRP3_WRP3_Pos) /*!< 0x00FF0000 */
+#define FLASH_WRP3_WRP3 FLASH_WRP3_WRP3_Msk /*!< Flash memory write protection option bytes */
+#define FLASH_WRP3_nWRP3_Pos (24U)
+#define FLASH_WRP3_nWRP3_Msk (0xFFU << FLASH_WRP3_nWRP3_Pos) /*!< 0xFF000000 */
+#define FLASH_WRP3_nWRP3 FLASH_WRP3_nWRP3_Msk /*!< Flash memory write protection complemented option bytes */
+
+
+
+/**
+ * @}
+*/
+
+/**
+ * @}
+*/
+
+/** @addtogroup Exported_macro
+ * @{
+ */
+
+/****************************** ADC Instances *********************************/
+#define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1))
+
+#define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC1_COMMON)
+
+#define IS_ADC_DMA_CAPABILITY_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
+
+/****************************** CEC Instances *********************************/
+#define IS_CEC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CEC)
+
+/****************************** CRC Instances *********************************/
+#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
+
+/****************************** DAC Instances *********************************/
+#define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC)
+
+/****************************** DMA Instances *********************************/
+#define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \
+ ((INSTANCE) == DMA1_Channel2) || \
+ ((INSTANCE) == DMA1_Channel3) || \
+ ((INSTANCE) == DMA1_Channel4) || \
+ ((INSTANCE) == DMA1_Channel5) || \
+ ((INSTANCE) == DMA1_Channel6) || \
+ ((INSTANCE) == DMA1_Channel7) || \
+ ((INSTANCE) == DMA2_Channel1) || \
+ ((INSTANCE) == DMA2_Channel2) || \
+ ((INSTANCE) == DMA2_Channel3) || \
+ ((INSTANCE) == DMA2_Channel4) || \
+ ((INSTANCE) == DMA2_Channel5))
+
+/******************************* GPIO Instances *******************************/
+#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
+ ((INSTANCE) == GPIOB) || \
+ ((INSTANCE) == GPIOC) || \
+ ((INSTANCE) == GPIOD) || \
+ ((INSTANCE) == GPIOE) || \
+ ((INSTANCE) == GPIOF) || \
+ ((INSTANCE) == GPIOG))
+
+/**************************** GPIO Alternate Function Instances ***************/
+#define IS_GPIO_AF_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
+
+/**************************** GPIO Lock Instances *****************************/
+#define IS_GPIO_LOCK_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
+
+/******************************** I2C Instances *******************************/
+#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
+ ((INSTANCE) == I2C2))
+
+/****************************** IWDG Instances ********************************/
+#define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
+
+/******************************** SPI Instances *******************************/
+#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
+ ((INSTANCE) == SPI2) || \
+ ((INSTANCE) == SPI3))
+
+/****************************** START TIM Instances ***************************/
+/****************************** TIM Instances *********************************/
+#define IS_TIM_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM6) || \
+ ((INSTANCE) == TIM7) || \
+ ((INSTANCE) == TIM12) || \
+ ((INSTANCE) == TIM13) || \
+ ((INSTANCE) == TIM14) || \
+ ((INSTANCE) == TIM15) || \
+ ((INSTANCE) == TIM16) || \
+ ((INSTANCE) == TIM17))
+
+#define IS_TIM_CC1_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM12) || \
+ ((INSTANCE) == TIM13) || \
+ ((INSTANCE) == TIM14) || \
+ ((INSTANCE) == TIM15) || \
+ ((INSTANCE) == TIM16) || \
+ ((INSTANCE) == TIM17))
+
+#define IS_TIM_CC2_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM12) || \
+ ((INSTANCE) == TIM15))
+
+#define IS_TIM_CC3_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5))
+
+#define IS_TIM_CC4_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5))
+
+#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5))
+
+#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5))
+
+#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM12) || \
+ ((INSTANCE) == TIM15))
+
+#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM12) || \
+ ((INSTANCE) == TIM15))
+
+#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5))
+
+#define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5))
+
+#define IS_TIM_XOR_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5))
+
+#define IS_TIM_MASTER_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM6) || \
+ ((INSTANCE) == TIM7) || \
+ ((INSTANCE) == TIM12) || \
+ ((INSTANCE) == TIM15))
+
+#define IS_TIM_SLAVE_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM12) || \
+ ((INSTANCE) == TIM15))
+
+#define IS_TIM_DMABURST_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM15) || \
+ ((INSTANCE) == TIM16) || \
+ ((INSTANCE) == TIM17))
+
+#define IS_TIM_BREAK_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM15) || \
+ ((INSTANCE) == TIM16) || \
+ ((INSTANCE) == TIM17))
+
+#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
+ ((((INSTANCE) == TIM1) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM2) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM3) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM4) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM5) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM12) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2))) \
+ || \
+ (((INSTANCE) == TIM13) && \
+ (((CHANNEL) == TIM_CHANNEL_1))) \
+ || \
+ (((INSTANCE) == TIM14) && \
+ (((CHANNEL) == TIM_CHANNEL_1))) \
+ || \
+ (((INSTANCE) == TIM15) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2))) \
+ || \
+ (((INSTANCE) == TIM16) && \
+ (((CHANNEL) == TIM_CHANNEL_1))) \
+ || \
+ (((INSTANCE) == TIM17) && \
+ (((CHANNEL) == TIM_CHANNEL_1))))
+
+#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
+ ((((INSTANCE) == TIM1) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3))) \
+ || \
+ (((INSTANCE) == TIM15) && \
+ ((CHANNEL) == TIM_CHANNEL_1)) \
+ || \
+ (((INSTANCE) == TIM16) && \
+ ((CHANNEL) == TIM_CHANNEL_1)) \
+ || \
+ (((INSTANCE) == TIM17) && \
+ ((CHANNEL) == TIM_CHANNEL_1)))
+
+#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5))
+
+#define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM15) || \
+ ((INSTANCE) == TIM16) || \
+ ((INSTANCE) == TIM17))
+
+#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM12) || \
+ ((INSTANCE) == TIM13) || \
+ ((INSTANCE) == TIM14) || \
+ ((INSTANCE) == TIM15) || \
+ ((INSTANCE) == TIM16) || \
+ ((INSTANCE) == TIM17))
+
+#define IS_TIM_DMA_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM6) || \
+ ((INSTANCE) == TIM7) || \
+ ((INSTANCE) == TIM15) || \
+ ((INSTANCE) == TIM16) || \
+ ((INSTANCE) == TIM17))
+
+#define IS_TIM_DMA_CC_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM15) || \
+ ((INSTANCE) == TIM16) || \
+ ((INSTANCE) == TIM17))
+
+#define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM15) || \
+ ((INSTANCE) == TIM16) || \
+ ((INSTANCE) == TIM17))
+
+/****************************** END TIM Instances *****************************/
+
+
+/******************** USART Instances : Synchronous mode **********************/
+#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3))
+
+/******************** UART Instances : Asynchronous mode **********************/
+#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3) || \
+ ((INSTANCE) == UART4) || \
+ ((INSTANCE) == UART5))
+
+/******************** UART Instances : Half-Duplex mode **********************/
+#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3) || \
+ ((INSTANCE) == UART4) || \
+ ((INSTANCE) == UART5))
+
+/******************** UART Instances : LIN mode **********************/
+#define IS_UART_LIN_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3) || \
+ ((INSTANCE) == UART4) || \
+ ((INSTANCE) == UART5))
+
+/****************** UART Instances : Hardware Flow control ********************/
+#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3))
+
+/********************* UART Instances : Smard card mode ***********************/
+#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3))
+
+/*********************** UART Instances : IRDA mode ***************************/
+#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3) || \
+ ((INSTANCE) == UART4) || \
+ ((INSTANCE) == UART5))
+
+/***************** UART Instances : Multi-Processor mode **********************/
+#define IS_UART_MULTIPROCESSOR_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3) || \
+ ((INSTANCE) == UART4) || \
+ ((INSTANCE) == UART5))
+
+/***************** UART Instances : DMA mode available **********************/
+#define IS_UART_DMA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3) || \
+ ((INSTANCE) == UART4) || \
+ ((INSTANCE) == UART5))
+
+/****************************** RTC Instances *********************************/
+#define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
+
+/**************************** WWDG Instances *****************************/
+#define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
+
+
+
+
+
+/**
+ * @}
+*/
+/******************************************************************************/
+/* For a painless codes migration between the STM32F1xx device product */
+/* lines, the aliases defined below are put in place to overcome the */
+/* differences in the interrupt handlers and IRQn definitions. */
+/* No need to update developed interrupt code when moving across */
+/* product lines within the same STM32F1 Family */
+/******************************************************************************/
+
+/* Aliases for __IRQn */
+#define ADC1_2_IRQn ADC1_IRQn
+#define USBWakeUp_IRQn CEC_IRQn
+#define OTG_FS_WKUP_IRQn CEC_IRQn
+#define TIM8_BRK_TIM12_IRQn TIM12_IRQn
+#define TIM8_BRK_IRQn TIM12_IRQn
+#define TIM8_UP_IRQn TIM13_IRQn
+#define TIM8_UP_TIM13_IRQn TIM13_IRQn
+#define TIM8_TRG_COM_IRQn TIM14_IRQn
+#define TIM8_TRG_COM_TIM14_IRQn TIM14_IRQn
+#define TIM1_BRK_IRQn TIM1_BRK_TIM15_IRQn
+#define TIM9_IRQn TIM1_BRK_TIM15_IRQn
+#define TIM1_BRK_TIM9_IRQn TIM1_BRK_TIM15_IRQn
+#define TIM1_TRG_COM_TIM11_IRQn TIM1_TRG_COM_TIM17_IRQn
+#define TIM1_TRG_COM_IRQn TIM1_TRG_COM_TIM17_IRQn
+#define TIM11_IRQn TIM1_TRG_COM_TIM17_IRQn
+#define TIM10_IRQn TIM1_UP_TIM16_IRQn
+#define TIM1_UP_IRQn TIM1_UP_TIM16_IRQn
+#define TIM1_UP_TIM10_IRQn TIM1_UP_TIM16_IRQn
+#define TIM6_IRQn TIM6_DAC_IRQn
+
+
+/* Aliases for __IRQHandler */
+#define ADC1_2_IRQHandler ADC1_IRQHandler
+#define USBWakeUp_IRQHandler CEC_IRQHandler
+#define OTG_FS_WKUP_IRQHandler CEC_IRQHandler
+#define TIM8_BRK_TIM12_IRQHandler TIM12_IRQHandler
+#define TIM8_BRK_IRQHandler TIM12_IRQHandler
+#define TIM8_UP_IRQHandler TIM13_IRQHandler
+#define TIM8_UP_TIM13_IRQHandler TIM13_IRQHandler
+#define TIM8_TRG_COM_IRQHandler TIM14_IRQHandler
+#define TIM8_TRG_COM_TIM14_IRQHandler TIM14_IRQHandler
+#define TIM1_BRK_IRQHandler TIM1_BRK_TIM15_IRQHandler
+#define TIM9_IRQHandler TIM1_BRK_TIM15_IRQHandler
+#define TIM1_BRK_TIM9_IRQHandler TIM1_BRK_TIM15_IRQHandler
+#define TIM1_TRG_COM_TIM11_IRQHandler TIM1_TRG_COM_TIM17_IRQHandler
+#define TIM1_TRG_COM_IRQHandler TIM1_TRG_COM_TIM17_IRQHandler
+#define TIM11_IRQHandler TIM1_TRG_COM_TIM17_IRQHandler
+#define TIM10_IRQHandler TIM1_UP_TIM16_IRQHandler
+#define TIM1_UP_IRQHandler TIM1_UP_TIM16_IRQHandler
+#define TIM1_UP_TIM10_IRQHandler TIM1_UP_TIM16_IRQHandler
+#define TIM6_IRQHandler TIM6_DAC_IRQHandler
+
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+
+#ifdef __cplusplus
+ }
+#endif /* __cplusplus */
+
+#endif /* __STM32F100xE_H */
+
+
+
+ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Device/ST/STM32F1xx/Include/stm32f101x6.h b/Device/ST/STM32F1xx/Include/stm32f101x6.h
new file mode 100644
index 0000000..92b413d
--- /dev/null
+++ b/Device/ST/STM32F1xx/Include/stm32f101x6.h
@@ -0,0 +1,6152 @@
+/**
+ ******************************************************************************
+ * @file stm32f101x6.h
+ * @author MCD Application Team
+ * @version V4.1.0
+ * @date 29-April-2016
+ * @brief CMSIS Cortex-M3 Device Peripheral Access Layer Header File.
+ * This file contains all the peripheral register's definitions, bits
+ * definitions and memory mapping for STM32F1xx devices.
+ *
+ * This file contains:
+ * - Data structures and the address mapping for all peripherals
+ * - Peripheral's registers declarations and bits definition
+ * - Macros to access peripheral’s registers hardware
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+
+/** @addtogroup CMSIS
+ * @{
+ */
+
+/** @addtogroup stm32f101x6
+ * @{
+ */
+
+#ifndef __STM32F101x6_H
+#define __STM32F101x6_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/** @addtogroup Configuration_section_for_CMSIS
+ * @{
+ */
+/**
+ * @brief Configuration of the Cortex-M3 Processor and Core Peripherals
+ */
+ #define __MPU_PRESENT 0 /*!< Other STM32 devices does not provide an MPU */
+#define __CM3_REV 0x0200 /*!< Core Revision r2p0 */
+#define __NVIC_PRIO_BITS 4 /*!< STM32 uses 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
+
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_interrupt_number_definition
+ * @{
+ */
+
+/**
+ * @brief STM32F10x Interrupt Number Definition, according to the selected device
+ * in @ref Library_configuration_section
+ */
+
+ /*!< Interrupt Number Definition */
+typedef enum
+{
+/****** Cortex-M3 Processor Exceptions Numbers ***************************************************/
+ NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
+ HardFault_IRQn = -13, /*!< 3 Cortex-M3 Hard Fault Interrupt */
+ MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */
+ BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */
+ UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */
+ SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */
+ DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */
+ PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */
+ SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */
+
+/****** STM32 specific Interrupt Numbers *********************************************************/
+ WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
+ PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */
+ TAMPER_IRQn = 2, /*!< Tamper Interrupt */
+ RTC_IRQn = 3, /*!< RTC global Interrupt */
+ FLASH_IRQn = 4, /*!< FLASH global Interrupt */
+ RCC_IRQn = 5, /*!< RCC global Interrupt */
+ EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */
+ EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */
+ EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */
+ EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */
+ EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */
+ DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 global Interrupt */
+ DMA1_Channel2_IRQn = 12, /*!< DMA1 Channel 2 global Interrupt */
+ DMA1_Channel3_IRQn = 13, /*!< DMA1 Channel 3 global Interrupt */
+ DMA1_Channel4_IRQn = 14, /*!< DMA1 Channel 4 global Interrupt */
+ DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 global Interrupt */
+ DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 global Interrupt */
+ DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 global Interrupt */
+ ADC1_IRQn = 18, /*!< ADC1 global Interrupt */
+ EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
+ TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
+ TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
+ I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
+ I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
+ SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
+ USART1_IRQn = 37, /*!< USART1 global Interrupt */
+ USART2_IRQn = 38, /*!< USART2 global Interrupt */
+ EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
+ RTC_Alarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */
+} IRQn_Type;
+
+
+/**
+ * @}
+ */
+
+#include "core_cm3.h"
+#include "system_stm32f1xx.h"
+#include <stdint.h>
+
+/** @addtogroup Peripheral_registers_structures
+ * @{
+ */
+
+/**
+ * @brief Analog to Digital Converter
+ */
+
+typedef struct
+{
+ __IO uint32_t SR;
+ __IO uint32_t CR1;
+ __IO uint32_t CR2;
+ __IO uint32_t SMPR1;
+ __IO uint32_t SMPR2;
+ __IO uint32_t JOFR1;
+ __IO uint32_t JOFR2;
+ __IO uint32_t JOFR3;
+ __IO uint32_t JOFR4;
+ __IO uint32_t HTR;
+ __IO uint32_t LTR;
+ __IO uint32_t SQR1;
+ __IO uint32_t SQR2;
+ __IO uint32_t SQR3;
+ __IO uint32_t JSQR;
+ __IO uint32_t JDR1;
+ __IO uint32_t JDR2;
+ __IO uint32_t JDR3;
+ __IO uint32_t JDR4;
+ __IO uint32_t DR;
+} ADC_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t SR; /*!< ADC status register, used for ADC multimode (bits common to several ADC instances). Address offset: ADC1 base address */
+ __IO uint32_t CR1; /*!< ADC control register 1, used for ADC multimode (bits common to several ADC instances). Address offset: ADC1 base address + 0x04 */
+ __IO uint32_t CR2; /*!< ADC control register 2, used for ADC multimode (bits common to several ADC instances). Address offset: ADC1 base address + 0x08 */
+ uint32_t RESERVED[16];
+ __IO uint32_t DR; /*!< ADC data register, used for ADC multimode (bits common to several ADC instances). Address offset: ADC1 base address + 0x4C */
+} ADC_Common_TypeDef;
+
+/**
+ * @brief Backup Registers
+ */
+
+typedef struct
+{
+ uint32_t RESERVED0;
+ __IO uint32_t DR1;
+ __IO uint32_t DR2;
+ __IO uint32_t DR3;
+ __IO uint32_t DR4;
+ __IO uint32_t DR5;
+ __IO uint32_t DR6;
+ __IO uint32_t DR7;
+ __IO uint32_t DR8;
+ __IO uint32_t DR9;
+ __IO uint32_t DR10;
+ __IO uint32_t RTCCR;
+ __IO uint32_t CR;
+ __IO uint32_t CSR;
+} BKP_TypeDef;
+
+
+/**
+ * @brief CRC calculation unit
+ */
+
+typedef struct
+{
+ __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
+ __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
+ uint8_t RESERVED0; /*!< Reserved, Address offset: 0x05 */
+ uint16_t RESERVED1; /*!< Reserved, Address offset: 0x06 */
+ __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
+} CRC_TypeDef;
+
+
+/**
+ * @brief Debug MCU
+ */
+
+typedef struct
+{
+ __IO uint32_t IDCODE;
+ __IO uint32_t CR;
+}DBGMCU_TypeDef;
+
+/**
+ * @brief DMA Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t CCR;
+ __IO uint32_t CNDTR;
+ __IO uint32_t CPAR;
+ __IO uint32_t CMAR;
+} DMA_Channel_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t ISR;
+ __IO uint32_t IFCR;
+} DMA_TypeDef;
+
+
+
+/**
+ * @brief External Interrupt/Event Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t IMR;
+ __IO uint32_t EMR;
+ __IO uint32_t RTSR;
+ __IO uint32_t FTSR;
+ __IO uint32_t SWIER;
+ __IO uint32_t PR;
+} EXTI_TypeDef;
+
+/**
+ * @brief FLASH Registers
+ */
+
+typedef struct
+{
+ __IO uint32_t ACR;
+ __IO uint32_t KEYR;
+ __IO uint32_t OPTKEYR;
+ __IO uint32_t SR;
+ __IO uint32_t CR;
+ __IO uint32_t AR;
+ __IO uint32_t RESERVED;
+ __IO uint32_t OBR;
+ __IO uint32_t WRPR;
+} FLASH_TypeDef;
+
+/**
+ * @brief Option Bytes Registers
+ */
+
+typedef struct
+{
+ __IO uint16_t RDP;
+ __IO uint16_t USER;
+ __IO uint16_t Data0;
+ __IO uint16_t Data1;
+ __IO uint16_t WRP0;
+ __IO uint16_t WRP1;
+ __IO uint16_t WRP2;
+ __IO uint16_t WRP3;
+} OB_TypeDef;
+
+/**
+ * @brief General Purpose I/O
+ */
+
+typedef struct
+{
+ __IO uint32_t CRL;
+ __IO uint32_t CRH;
+ __IO uint32_t IDR;
+ __IO uint32_t ODR;
+ __IO uint32_t BSRR;
+ __IO uint32_t BRR;
+ __IO uint32_t LCKR;
+} GPIO_TypeDef;
+
+/**
+ * @brief Alternate Function I/O
+ */
+
+typedef struct
+{
+ __IO uint32_t EVCR;
+ __IO uint32_t MAPR;
+ __IO uint32_t EXTICR[4];
+ uint32_t RESERVED0;
+ __IO uint32_t MAPR2;
+} AFIO_TypeDef;
+/**
+ * @brief Inter Integrated Circuit Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t CR1;
+ __IO uint32_t CR2;
+ __IO uint32_t OAR1;
+ __IO uint32_t OAR2;
+ __IO uint32_t DR;
+ __IO uint32_t SR1;
+ __IO uint32_t SR2;
+ __IO uint32_t CCR;
+ __IO uint32_t TRISE;
+} I2C_TypeDef;
+
+/**
+ * @brief Independent WATCHDOG
+ */
+
+typedef struct
+{
+ __IO uint32_t KR; /*!< Key register, Address offset: 0x00 */
+ __IO uint32_t PR; /*!< Prescaler register, Address offset: 0x04 */
+ __IO uint32_t RLR; /*!< Reload register, Address offset: 0x08 */
+ __IO uint32_t SR; /*!< Status register, Address offset: 0x0C */
+} IWDG_TypeDef;
+
+/**
+ * @brief Power Control
+ */
+
+typedef struct
+{
+ __IO uint32_t CR;
+ __IO uint32_t CSR;
+} PWR_TypeDef;
+
+/**
+ * @brief Reset and Clock Control
+ */
+
+typedef struct
+{
+ __IO uint32_t CR;
+ __IO uint32_t CFGR;
+ __IO uint32_t CIR;
+ __IO uint32_t APB2RSTR;
+ __IO uint32_t APB1RSTR;
+ __IO uint32_t AHBENR;
+ __IO uint32_t APB2ENR;
+ __IO uint32_t APB1ENR;
+ __IO uint32_t BDCR;
+ __IO uint32_t CSR;
+
+
+} RCC_TypeDef;
+
+/**
+ * @brief Real-Time Clock
+ */
+
+typedef struct
+{
+ __IO uint32_t CRH;
+ __IO uint32_t CRL;
+ __IO uint32_t PRLH;
+ __IO uint32_t PRLL;
+ __IO uint32_t DIVH;
+ __IO uint32_t DIVL;
+ __IO uint32_t CNTH;
+ __IO uint32_t CNTL;
+ __IO uint32_t ALRH;
+ __IO uint32_t ALRL;
+} RTC_TypeDef;
+
+/**
+ * @brief SD host Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t POWER;
+ __IO uint32_t CLKCR;
+ __IO uint32_t ARG;
+ __IO uint32_t CMD;
+ __I uint32_t RESPCMD;
+ __I uint32_t RESP1;
+ __I uint32_t RESP2;
+ __I uint32_t RESP3;
+ __I uint32_t RESP4;
+ __IO uint32_t DTIMER;
+ __IO uint32_t DLEN;
+ __IO uint32_t DCTRL;
+ __I uint32_t DCOUNT;
+ __I uint32_t STA;
+ __IO uint32_t ICR;
+ __IO uint32_t MASK;
+ uint32_t RESERVED0[2];
+ __I uint32_t FIFOCNT;
+ uint32_t RESERVED1[13];
+ __IO uint32_t FIFO;
+} SDIO_TypeDef;
+
+/**
+ * @brief Serial Peripheral Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t CR1;
+ __IO uint32_t CR2;
+ __IO uint32_t SR;
+ __IO uint32_t DR;
+ __IO uint32_t CRCPR;
+ __IO uint32_t RXCRCR;
+ __IO uint32_t TXCRCR;
+ __IO uint32_t I2SCFGR;
+} SPI_TypeDef;
+
+/**
+ * @brief TIM Timers
+ */
+typedef struct
+{
+ __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
+ __IO uint32_t SMCR; /*!< TIM slave Mode Control register, Address offset: 0x08 */
+ __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
+ __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
+ __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
+ __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
+ __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
+ __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
+ __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
+ __IO uint32_t PSC; /*!< TIM prescaler register, Address offset: 0x28 */
+ __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
+ __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */
+ __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
+ __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
+ __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
+ __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
+ __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
+ __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
+ __IO uint32_t DMAR; /*!< TIM DMA address for full transfer register, Address offset: 0x4C */
+ __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */
+}TIM_TypeDef;
+
+
+/**
+ * @brief Universal Synchronous Asynchronous Receiver Transmitter
+ */
+
+typedef struct
+{
+ __IO uint32_t SR; /*!< USART Status register, Address offset: 0x00 */
+ __IO uint32_t DR; /*!< USART Data register, Address offset: 0x04 */
+ __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x08 */
+ __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x0C */
+ __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x10 */
+ __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x14 */
+ __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x18 */
+} USART_TypeDef;
+
+
+
+/**
+ * @brief Window WATCHDOG
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
+ __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
+ __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
+} WWDG_TypeDef;
+
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_memory_map
+ * @{
+ */
+
+
+#define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH base address in the alias region */
+#define FLASH_BANK1_END ((uint32_t)0x08007FFF) /*!< FLASH END address of bank1 */
+#define SRAM_BASE ((uint32_t)0x20000000) /*!< SRAM base address in the alias region */
+#define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */
+
+#define SRAM_BB_BASE ((uint32_t)0x22000000) /*!< SRAM base address in the bit-band region */
+#define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */
+
+
+/*!< Peripheral memory map */
+#define APB1PERIPH_BASE PERIPH_BASE
+#define APB2PERIPH_BASE (PERIPH_BASE + 0x10000)
+#define AHBPERIPH_BASE (PERIPH_BASE + 0x20000)
+
+#define TIM2_BASE (APB1PERIPH_BASE + 0x0000)
+#define TIM3_BASE (APB1PERIPH_BASE + 0x0400)
+#define RTC_BASE (APB1PERIPH_BASE + 0x2800)
+#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00)
+#define IWDG_BASE (APB1PERIPH_BASE + 0x3000)
+#define USART2_BASE (APB1PERIPH_BASE + 0x4400)
+#define I2C1_BASE (APB1PERIPH_BASE + 0x5400)
+#define BKP_BASE (APB1PERIPH_BASE + 0x6C00)
+#define PWR_BASE (APB1PERIPH_BASE + 0x7000)
+#define AFIO_BASE (APB2PERIPH_BASE + 0x0000)
+#define EXTI_BASE (APB2PERIPH_BASE + 0x0400)
+#define GPIOA_BASE (APB2PERIPH_BASE + 0x0800)
+#define GPIOB_BASE (APB2PERIPH_BASE + 0x0C00)
+#define GPIOC_BASE (APB2PERIPH_BASE + 0x1000)
+#define GPIOD_BASE (APB2PERIPH_BASE + 0x1400)
+#define ADC1_BASE (APB2PERIPH_BASE + 0x2400)
+#define SPI1_BASE (APB2PERIPH_BASE + 0x3000)
+#define USART1_BASE (APB2PERIPH_BASE + 0x3800)
+
+#define SDIO_BASE (PERIPH_BASE + 0x18000)
+
+#define DMA1_BASE (AHBPERIPH_BASE + 0x0000)
+#define DMA1_Channel1_BASE (AHBPERIPH_BASE + 0x0008)
+#define DMA1_Channel2_BASE (AHBPERIPH_BASE + 0x001C)
+#define DMA1_Channel3_BASE (AHBPERIPH_BASE + 0x0030)
+#define DMA1_Channel4_BASE (AHBPERIPH_BASE + 0x0044)
+#define DMA1_Channel5_BASE (AHBPERIPH_BASE + 0x0058)
+#define DMA1_Channel6_BASE (AHBPERIPH_BASE + 0x006C)
+#define DMA1_Channel7_BASE (AHBPERIPH_BASE + 0x0080)
+#define RCC_BASE (AHBPERIPH_BASE + 0x1000)
+#define CRC_BASE (AHBPERIPH_BASE + 0x3000)
+
+#define FLASH_R_BASE (AHBPERIPH_BASE + 0x2000) /*!< Flash registers base address */
+#define FLASHSIZE_BASE ((uint32_t)0x1FFFF7E0) /*!< FLASH Size register base address */
+#define UID_BASE ((uint32_t)0x1FFFF7E8) /*!< Unique device ID register base address */
+#define OB_BASE ((uint32_t)0x1FFFF800) /*!< Flash Option Bytes base address */
+
+
+
+#define DBGMCU_BASE ((uint32_t)0xE0042000) /*!< Debug MCU registers base address */
+
+
+
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_declaration
+ * @{
+ */
+
+#define TIM2 ((TIM_TypeDef *) TIM2_BASE)
+#define TIM3 ((TIM_TypeDef *) TIM3_BASE)
+#define RTC ((RTC_TypeDef *) RTC_BASE)
+#define WWDG ((WWDG_TypeDef *) WWDG_BASE)
+#define IWDG ((IWDG_TypeDef *) IWDG_BASE)
+#define USART2 ((USART_TypeDef *) USART2_BASE)
+#define I2C1 ((I2C_TypeDef *) I2C1_BASE)
+#define BKP ((BKP_TypeDef *) BKP_BASE)
+#define PWR ((PWR_TypeDef *) PWR_BASE)
+#define AFIO ((AFIO_TypeDef *) AFIO_BASE)
+#define EXTI ((EXTI_TypeDef *) EXTI_BASE)
+#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
+#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
+#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
+#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
+#define ADC1 ((ADC_TypeDef *) ADC1_BASE)
+#define ADC1_COMMON ((ADC_Common_TypeDef *) ADC1_BASE)
+#define SPI1 ((SPI_TypeDef *) SPI1_BASE)
+#define USART1 ((USART_TypeDef *) USART1_BASE)
+#define SDIO ((SDIO_TypeDef *) SDIO_BASE)
+#define DMA1 ((DMA_TypeDef *) DMA1_BASE)
+#define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
+#define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
+#define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
+#define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
+#define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
+#define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
+#define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
+#define RCC ((RCC_TypeDef *) RCC_BASE)
+#define CRC ((CRC_TypeDef *) CRC_BASE)
+#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
+#define OB ((OB_TypeDef *) OB_BASE)
+#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
+
+
+/**
+ * @}
+ */
+
+/** @addtogroup Exported_constants
+ * @{
+ */
+
+ /** @addtogroup Peripheral_Registers_Bits_Definition
+ * @{
+ */
+
+/******************************************************************************/
+/* Peripheral Registers_Bits_Definition */
+/******************************************************************************/
+
+/******************************************************************************/
+/* */
+/* CRC calculation unit (CRC) */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for CRC_DR register *********************/
+#define CRC_DR_DR_Pos (0U)
+#define CRC_DR_DR_Msk (0xFFFFFFFFU << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */
+#define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */
+
+/******************* Bit definition for CRC_IDR register ********************/
+#define CRC_IDR_IDR_Pos (0U)
+#define CRC_IDR_IDR_Msk (0xFFU << CRC_IDR_IDR_Pos) /*!< 0x000000FF */
+#define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 8-bit data register bits */
+
+/******************** Bit definition for CRC_CR register ********************/
+#define CRC_CR_RESET_Pos (0U)
+#define CRC_CR_RESET_Msk (0x1U << CRC_CR_RESET_Pos) /*!< 0x00000001 */
+#define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET bit */
+
+/******************************************************************************/
+/* */
+/* Power Control */
+/* */
+/******************************************************************************/
+
+/******************** Bit definition for PWR_CR register ********************/
+#define PWR_CR_LPDS_Pos (0U)
+#define PWR_CR_LPDS_Msk (0x1U << PWR_CR_LPDS_Pos) /*!< 0x00000001 */
+#define PWR_CR_LPDS PWR_CR_LPDS_Msk /*!< Low-Power Deepsleep */
+#define PWR_CR_PDDS_Pos (1U)
+#define PWR_CR_PDDS_Msk (0x1U << PWR_CR_PDDS_Pos) /*!< 0x00000002 */
+#define PWR_CR_PDDS PWR_CR_PDDS_Msk /*!< Power Down Deepsleep */
+#define PWR_CR_CWUF_Pos (2U)
+#define PWR_CR_CWUF_Msk (0x1U << PWR_CR_CWUF_Pos) /*!< 0x00000004 */
+#define PWR_CR_CWUF PWR_CR_CWUF_Msk /*!< Clear Wakeup Flag */
+#define PWR_CR_CSBF_Pos (3U)
+#define PWR_CR_CSBF_Msk (0x1U << PWR_CR_CSBF_Pos) /*!< 0x00000008 */
+#define PWR_CR_CSBF PWR_CR_CSBF_Msk /*!< Clear Standby Flag */
+#define PWR_CR_PVDE_Pos (4U)
+#define PWR_CR_PVDE_Msk (0x1U << PWR_CR_PVDE_Pos) /*!< 0x00000010 */
+#define PWR_CR_PVDE PWR_CR_PVDE_Msk /*!< Power Voltage Detector Enable */
+
+#define PWR_CR_PLS_Pos (5U)
+#define PWR_CR_PLS_Msk (0x7U << PWR_CR_PLS_Pos) /*!< 0x000000E0 */
+#define PWR_CR_PLS PWR_CR_PLS_Msk /*!< PLS[2:0] bits (PVD Level Selection) */
+#define PWR_CR_PLS_0 (0x1U << PWR_CR_PLS_Pos) /*!< 0x00000020 */
+#define PWR_CR_PLS_1 (0x2U << PWR_CR_PLS_Pos) /*!< 0x00000040 */
+#define PWR_CR_PLS_2 (0x4U << PWR_CR_PLS_Pos) /*!< 0x00000080 */
+
+/*!< PVD level configuration */
+#define PWR_CR_PLS_2V2 ((uint32_t)0x00000000) /*!< PVD level 2.2V */
+#define PWR_CR_PLS_2V3 ((uint32_t)0x00000020) /*!< PVD level 2.3V */
+#define PWR_CR_PLS_2V4 ((uint32_t)0x00000040) /*!< PVD level 2.4V */
+#define PWR_CR_PLS_2V5 ((uint32_t)0x00000060) /*!< PVD level 2.5V */
+#define PWR_CR_PLS_2V6 ((uint32_t)0x00000080) /*!< PVD level 2.6V */
+#define PWR_CR_PLS_2V7 ((uint32_t)0x000000A0) /*!< PVD level 2.7V */
+#define PWR_CR_PLS_2V8 ((uint32_t)0x000000C0) /*!< PVD level 2.8V */
+#define PWR_CR_PLS_2V9 ((uint32_t)0x000000E0) /*!< PVD level 2.9V */
+
+#define PWR_CR_DBP_Pos (8U)
+#define PWR_CR_DBP_Msk (0x1U << PWR_CR_DBP_Pos) /*!< 0x00000100 */
+#define PWR_CR_DBP PWR_CR_DBP_Msk /*!< Disable Backup Domain write protection */
+
+
+/******************* Bit definition for PWR_CSR register ********************/
+#define PWR_CSR_WUF_Pos (0U)
+#define PWR_CSR_WUF_Msk (0x1U << PWR_CSR_WUF_Pos) /*!< 0x00000001 */
+#define PWR_CSR_WUF PWR_CSR_WUF_Msk /*!< Wakeup Flag */
+#define PWR_CSR_SBF_Pos (1U)
+#define PWR_CSR_SBF_Msk (0x1U << PWR_CSR_SBF_Pos) /*!< 0x00000002 */
+#define PWR_CSR_SBF PWR_CSR_SBF_Msk /*!< Standby Flag */
+#define PWR_CSR_PVDO_Pos (2U)
+#define PWR_CSR_PVDO_Msk (0x1U << PWR_CSR_PVDO_Pos) /*!< 0x00000004 */
+#define PWR_CSR_PVDO PWR_CSR_PVDO_Msk /*!< PVD Output */
+#define PWR_CSR_EWUP_Pos (8U)
+#define PWR_CSR_EWUP_Msk (0x1U << PWR_CSR_EWUP_Pos) /*!< 0x00000100 */
+#define PWR_CSR_EWUP PWR_CSR_EWUP_Msk /*!< Enable WKUP pin */
+
+/******************************************************************************/
+/* */
+/* Backup registers */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for BKP_DR1 register ********************/
+#define BKP_DR1_D_Pos (0U)
+#define BKP_DR1_D_Msk (0xFFFFU << BKP_DR1_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR1_D BKP_DR1_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR2 register ********************/
+#define BKP_DR2_D_Pos (0U)
+#define BKP_DR2_D_Msk (0xFFFFU << BKP_DR2_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR2_D BKP_DR2_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR3 register ********************/
+#define BKP_DR3_D_Pos (0U)
+#define BKP_DR3_D_Msk (0xFFFFU << BKP_DR3_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR3_D BKP_DR3_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR4 register ********************/
+#define BKP_DR4_D_Pos (0U)
+#define BKP_DR4_D_Msk (0xFFFFU << BKP_DR4_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR4_D BKP_DR4_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR5 register ********************/
+#define BKP_DR5_D_Pos (0U)
+#define BKP_DR5_D_Msk (0xFFFFU << BKP_DR5_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR5_D BKP_DR5_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR6 register ********************/
+#define BKP_DR6_D_Pos (0U)
+#define BKP_DR6_D_Msk (0xFFFFU << BKP_DR6_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR6_D BKP_DR6_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR7 register ********************/
+#define BKP_DR7_D_Pos (0U)
+#define BKP_DR7_D_Msk (0xFFFFU << BKP_DR7_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR7_D BKP_DR7_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR8 register ********************/
+#define BKP_DR8_D_Pos (0U)
+#define BKP_DR8_D_Msk (0xFFFFU << BKP_DR8_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR8_D BKP_DR8_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR9 register ********************/
+#define BKP_DR9_D_Pos (0U)
+#define BKP_DR9_D_Msk (0xFFFFU << BKP_DR9_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR9_D BKP_DR9_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR10 register *******************/
+#define BKP_DR10_D_Pos (0U)
+#define BKP_DR10_D_Msk (0xFFFFU << BKP_DR10_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR10_D BKP_DR10_D_Msk /*!< Backup data */
+
+#define RTC_BKP_NUMBER 10
+
+/****************** Bit definition for BKP_RTCCR register *******************/
+#define BKP_RTCCR_CAL_Pos (0U)
+#define BKP_RTCCR_CAL_Msk (0x7FU << BKP_RTCCR_CAL_Pos) /*!< 0x0000007F */
+#define BKP_RTCCR_CAL BKP_RTCCR_CAL_Msk /*!< Calibration value */
+#define BKP_RTCCR_CCO_Pos (7U)
+#define BKP_RTCCR_CCO_Msk (0x1U << BKP_RTCCR_CCO_Pos) /*!< 0x00000080 */
+#define BKP_RTCCR_CCO BKP_RTCCR_CCO_Msk /*!< Calibration Clock Output */
+#define BKP_RTCCR_ASOE_Pos (8U)
+#define BKP_RTCCR_ASOE_Msk (0x1U << BKP_RTCCR_ASOE_Pos) /*!< 0x00000100 */
+#define BKP_RTCCR_ASOE BKP_RTCCR_ASOE_Msk /*!< Alarm or Second Output Enable */
+#define BKP_RTCCR_ASOS_Pos (9U)
+#define BKP_RTCCR_ASOS_Msk (0x1U << BKP_RTCCR_ASOS_Pos) /*!< 0x00000200 */
+#define BKP_RTCCR_ASOS BKP_RTCCR_ASOS_Msk /*!< Alarm or Second Output Selection */
+
+/******************** Bit definition for BKP_CR register ********************/
+#define BKP_CR_TPE_Pos (0U)
+#define BKP_CR_TPE_Msk (0x1U << BKP_CR_TPE_Pos) /*!< 0x00000001 */
+#define BKP_CR_TPE BKP_CR_TPE_Msk /*!< TAMPER pin enable */
+#define BKP_CR_TPAL_Pos (1U)
+#define BKP_CR_TPAL_Msk (0x1U << BKP_CR_TPAL_Pos) /*!< 0x00000002 */
+#define BKP_CR_TPAL BKP_CR_TPAL_Msk /*!< TAMPER pin active level */
+
+/******************* Bit definition for BKP_CSR register ********************/
+#define BKP_CSR_CTE_Pos (0U)
+#define BKP_CSR_CTE_Msk (0x1U << BKP_CSR_CTE_Pos) /*!< 0x00000001 */
+#define BKP_CSR_CTE BKP_CSR_CTE_Msk /*!< Clear Tamper event */
+#define BKP_CSR_CTI_Pos (1U)
+#define BKP_CSR_CTI_Msk (0x1U << BKP_CSR_CTI_Pos) /*!< 0x00000002 */
+#define BKP_CSR_CTI BKP_CSR_CTI_Msk /*!< Clear Tamper Interrupt */
+#define BKP_CSR_TPIE_Pos (2U)
+#define BKP_CSR_TPIE_Msk (0x1U << BKP_CSR_TPIE_Pos) /*!< 0x00000004 */
+#define BKP_CSR_TPIE BKP_CSR_TPIE_Msk /*!< TAMPER Pin interrupt enable */
+#define BKP_CSR_TEF_Pos (8U)
+#define BKP_CSR_TEF_Msk (0x1U << BKP_CSR_TEF_Pos) /*!< 0x00000100 */
+#define BKP_CSR_TEF BKP_CSR_TEF_Msk /*!< Tamper Event Flag */
+#define BKP_CSR_TIF_Pos (9U)
+#define BKP_CSR_TIF_Msk (0x1U << BKP_CSR_TIF_Pos) /*!< 0x00000200 */
+#define BKP_CSR_TIF BKP_CSR_TIF_Msk /*!< Tamper Interrupt Flag */
+
+/******************************************************************************/
+/* */
+/* Reset and Clock Control */
+/* */
+/******************************************************************************/
+
+/******************** Bit definition for RCC_CR register ********************/
+#define RCC_CR_HSION_Pos (0U)
+#define RCC_CR_HSION_Msk (0x1U << RCC_CR_HSION_Pos) /*!< 0x00000001 */
+#define RCC_CR_HSION RCC_CR_HSION_Msk /*!< Internal High Speed clock enable */
+#define RCC_CR_HSIRDY_Pos (1U)
+#define RCC_CR_HSIRDY_Msk (0x1U << RCC_CR_HSIRDY_Pos) /*!< 0x00000002 */
+#define RCC_CR_HSIRDY RCC_CR_HSIRDY_Msk /*!< Internal High Speed clock ready flag */
+#define RCC_CR_HSITRIM_Pos (3U)
+#define RCC_CR_HSITRIM_Msk (0x1FU << RCC_CR_HSITRIM_Pos) /*!< 0x000000F8 */
+#define RCC_CR_HSITRIM RCC_CR_HSITRIM_Msk /*!< Internal High Speed clock trimming */
+#define RCC_CR_HSICAL_Pos (8U)
+#define RCC_CR_HSICAL_Msk (0xFFU << RCC_CR_HSICAL_Pos) /*!< 0x0000FF00 */
+#define RCC_CR_HSICAL RCC_CR_HSICAL_Msk /*!< Internal High Speed clock Calibration */
+#define RCC_CR_HSEON_Pos (16U)
+#define RCC_CR_HSEON_Msk (0x1U << RCC_CR_HSEON_Pos) /*!< 0x00010000 */
+#define RCC_CR_HSEON RCC_CR_HSEON_Msk /*!< External High Speed clock enable */
+#define RCC_CR_HSERDY_Pos (17U)
+#define RCC_CR_HSERDY_Msk (0x1U << RCC_CR_HSERDY_Pos) /*!< 0x00020000 */
+#define RCC_CR_HSERDY RCC_CR_HSERDY_Msk /*!< External High Speed clock ready flag */
+#define RCC_CR_HSEBYP_Pos (18U)
+#define RCC_CR_HSEBYP_Msk (0x1U << RCC_CR_HSEBYP_Pos) /*!< 0x00040000 */
+#define RCC_CR_HSEBYP RCC_CR_HSEBYP_Msk /*!< External High Speed clock Bypass */
+#define RCC_CR_CSSON_Pos (19U)
+#define RCC_CR_CSSON_Msk (0x1U << RCC_CR_CSSON_Pos) /*!< 0x00080000 */
+#define RCC_CR_CSSON RCC_CR_CSSON_Msk /*!< Clock Security System enable */
+#define RCC_CR_PLLON_Pos (24U)
+#define RCC_CR_PLLON_Msk (0x1U << RCC_CR_PLLON_Pos) /*!< 0x01000000 */
+#define RCC_CR_PLLON RCC_CR_PLLON_Msk /*!< PLL enable */
+#define RCC_CR_PLLRDY_Pos (25U)
+#define RCC_CR_PLLRDY_Msk (0x1U << RCC_CR_PLLRDY_Pos) /*!< 0x02000000 */
+#define RCC_CR_PLLRDY RCC_CR_PLLRDY_Msk /*!< PLL clock ready flag */
+
+
+/******************* Bit definition for RCC_CFGR register *******************/
+/*!< SW configuration */
+#define RCC_CFGR_SW_Pos (0U)
+#define RCC_CFGR_SW_Msk (0x3U << RCC_CFGR_SW_Pos) /*!< 0x00000003 */
+#define RCC_CFGR_SW RCC_CFGR_SW_Msk /*!< SW[1:0] bits (System clock Switch) */
+#define RCC_CFGR_SW_0 (0x1U << RCC_CFGR_SW_Pos) /*!< 0x00000001 */
+#define RCC_CFGR_SW_1 (0x2U << RCC_CFGR_SW_Pos) /*!< 0x00000002 */
+
+#define RCC_CFGR_SW_HSI ((uint32_t)0x00000000) /*!< HSI selected as system clock */
+#define RCC_CFGR_SW_HSE ((uint32_t)0x00000001) /*!< HSE selected as system clock */
+#define RCC_CFGR_SW_PLL ((uint32_t)0x00000002) /*!< PLL selected as system clock */
+
+/*!< SWS configuration */
+#define RCC_CFGR_SWS_Pos (2U)
+#define RCC_CFGR_SWS_Msk (0x3U << RCC_CFGR_SWS_Pos) /*!< 0x0000000C */
+#define RCC_CFGR_SWS RCC_CFGR_SWS_Msk /*!< SWS[1:0] bits (System Clock Switch Status) */
+#define RCC_CFGR_SWS_0 (0x1U << RCC_CFGR_SWS_Pos) /*!< 0x00000004 */
+#define RCC_CFGR_SWS_1 (0x2U << RCC_CFGR_SWS_Pos) /*!< 0x00000008 */
+
+#define RCC_CFGR_SWS_HSI ((uint32_t)0x00000000) /*!< HSI oscillator used as system clock */
+#define RCC_CFGR_SWS_HSE ((uint32_t)0x00000004) /*!< HSE oscillator used as system clock */
+#define RCC_CFGR_SWS_PLL ((uint32_t)0x00000008) /*!< PLL used as system clock */
+
+/*!< HPRE configuration */
+#define RCC_CFGR_HPRE_Pos (4U)
+#define RCC_CFGR_HPRE_Msk (0xFU << RCC_CFGR_HPRE_Pos) /*!< 0x000000F0 */
+#define RCC_CFGR_HPRE RCC_CFGR_HPRE_Msk /*!< HPRE[3:0] bits (AHB prescaler) */
+#define RCC_CFGR_HPRE_0 (0x1U << RCC_CFGR_HPRE_Pos) /*!< 0x00000010 */
+#define RCC_CFGR_HPRE_1 (0x2U << RCC_CFGR_HPRE_Pos) /*!< 0x00000020 */
+#define RCC_CFGR_HPRE_2 (0x4U << RCC_CFGR_HPRE_Pos) /*!< 0x00000040 */
+#define RCC_CFGR_HPRE_3 (0x8U << RCC_CFGR_HPRE_Pos) /*!< 0x00000080 */
+
+#define RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000) /*!< SYSCLK not divided */
+#define RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080) /*!< SYSCLK divided by 2 */
+#define RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090) /*!< SYSCLK divided by 4 */
+#define RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0) /*!< SYSCLK divided by 8 */
+#define RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0) /*!< SYSCLK divided by 16 */
+#define RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0) /*!< SYSCLK divided by 64 */
+#define RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0) /*!< SYSCLK divided by 128 */
+#define RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0) /*!< SYSCLK divided by 256 */
+#define RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0) /*!< SYSCLK divided by 512 */
+
+/*!< PPRE1 configuration */
+#define RCC_CFGR_PPRE1_Pos (8U)
+#define RCC_CFGR_PPRE1_Msk (0x7U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000700 */
+#define RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_Msk /*!< PRE1[2:0] bits (APB1 prescaler) */
+#define RCC_CFGR_PPRE1_0 (0x1U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000100 */
+#define RCC_CFGR_PPRE1_1 (0x2U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000200 */
+#define RCC_CFGR_PPRE1_2 (0x4U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000400 */
+
+#define RCC_CFGR_PPRE1_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */
+#define RCC_CFGR_PPRE1_DIV2 ((uint32_t)0x00000400) /*!< HCLK divided by 2 */
+#define RCC_CFGR_PPRE1_DIV4 ((uint32_t)0x00000500) /*!< HCLK divided by 4 */
+#define RCC_CFGR_PPRE1_DIV8 ((uint32_t)0x00000600) /*!< HCLK divided by 8 */
+#define RCC_CFGR_PPRE1_DIV16 ((uint32_t)0x00000700) /*!< HCLK divided by 16 */
+
+/*!< PPRE2 configuration */
+#define RCC_CFGR_PPRE2_Pos (11U)
+#define RCC_CFGR_PPRE2_Msk (0x7U << RCC_CFGR_PPRE2_Pos) /*!< 0x00003800 */
+#define RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_Msk /*!< PRE2[2:0] bits (APB2 prescaler) */
+#define RCC_CFGR_PPRE2_0 (0x1U << RCC_CFGR_PPRE2_Pos) /*!< 0x00000800 */
+#define RCC_CFGR_PPRE2_1 (0x2U << RCC_CFGR_PPRE2_Pos) /*!< 0x00001000 */
+#define RCC_CFGR_PPRE2_2 (0x4U << RCC_CFGR_PPRE2_Pos) /*!< 0x00002000 */
+
+#define RCC_CFGR_PPRE2_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */
+#define RCC_CFGR_PPRE2_DIV2 ((uint32_t)0x00002000) /*!< HCLK divided by 2 */
+#define RCC_CFGR_PPRE2_DIV4 ((uint32_t)0x00002800) /*!< HCLK divided by 4 */
+#define RCC_CFGR_PPRE2_DIV8 ((uint32_t)0x00003000) /*!< HCLK divided by 8 */
+#define RCC_CFGR_PPRE2_DIV16 ((uint32_t)0x00003800) /*!< HCLK divided by 16 */
+
+/*!< ADCPPRE configuration */
+#define RCC_CFGR_ADCPRE_Pos (14U)
+#define RCC_CFGR_ADCPRE_Msk (0x3U << RCC_CFGR_ADCPRE_Pos) /*!< 0x0000C000 */
+#define RCC_CFGR_ADCPRE RCC_CFGR_ADCPRE_Msk /*!< ADCPRE[1:0] bits (ADC prescaler) */
+#define RCC_CFGR_ADCPRE_0 (0x1U << RCC_CFGR_ADCPRE_Pos) /*!< 0x00004000 */
+#define RCC_CFGR_ADCPRE_1 (0x2U << RCC_CFGR_ADCPRE_Pos) /*!< 0x00008000 */
+
+#define RCC_CFGR_ADCPRE_DIV2 ((uint32_t)0x00000000) /*!< PCLK2 divided by 2 */
+#define RCC_CFGR_ADCPRE_DIV4 ((uint32_t)0x00004000) /*!< PCLK2 divided by 4 */
+#define RCC_CFGR_ADCPRE_DIV6 ((uint32_t)0x00008000) /*!< PCLK2 divided by 6 */
+#define RCC_CFGR_ADCPRE_DIV8 ((uint32_t)0x0000C000) /*!< PCLK2 divided by 8 */
+
+#define RCC_CFGR_PLLSRC_Pos (16U)
+#define RCC_CFGR_PLLSRC_Msk (0x1U << RCC_CFGR_PLLSRC_Pos) /*!< 0x00010000 */
+#define RCC_CFGR_PLLSRC RCC_CFGR_PLLSRC_Msk /*!< PLL entry clock source */
+
+#define RCC_CFGR_PLLXTPRE_Pos (17U)
+#define RCC_CFGR_PLLXTPRE_Msk (0x1U << RCC_CFGR_PLLXTPRE_Pos) /*!< 0x00020000 */
+#define RCC_CFGR_PLLXTPRE RCC_CFGR_PLLXTPRE_Msk /*!< HSE divider for PLL entry */
+
+/*!< PLLMUL configuration */
+#define RCC_CFGR_PLLMULL_Pos (18U)
+#define RCC_CFGR_PLLMULL_Msk (0xFU << RCC_CFGR_PLLMULL_Pos) /*!< 0x003C0000 */
+#define RCC_CFGR_PLLMULL RCC_CFGR_PLLMULL_Msk /*!< PLLMUL[3:0] bits (PLL multiplication factor) */
+#define RCC_CFGR_PLLMULL_0 (0x1U << RCC_CFGR_PLLMULL_Pos) /*!< 0x00040000 */
+#define RCC_CFGR_PLLMULL_1 (0x2U << RCC_CFGR_PLLMULL_Pos) /*!< 0x00080000 */
+#define RCC_CFGR_PLLMULL_2 (0x4U << RCC_CFGR_PLLMULL_Pos) /*!< 0x00100000 */
+#define RCC_CFGR_PLLMULL_3 (0x8U << RCC_CFGR_PLLMULL_Pos) /*!< 0x00200000 */
+
+#define RCC_CFGR_PLLXTPRE_HSE ((uint32_t)0x00000000) /*!< HSE clock not divided for PLL entry */
+#define RCC_CFGR_PLLXTPRE_HSE_DIV2 ((uint32_t)0x00020000) /*!< HSE clock divided by 2 for PLL entry */
+
+#define RCC_CFGR_PLLMULL2 ((uint32_t)0x00000000) /*!< PLL input clock*2 */
+#define RCC_CFGR_PLLMULL3_Pos (18U)
+#define RCC_CFGR_PLLMULL3_Msk (0x1U << RCC_CFGR_PLLMULL3_Pos) /*!< 0x00040000 */
+#define RCC_CFGR_PLLMULL3 RCC_CFGR_PLLMULL3_Msk /*!< PLL input clock*3 */
+#define RCC_CFGR_PLLMULL4_Pos (19U)
+#define RCC_CFGR_PLLMULL4_Msk (0x1U << RCC_CFGR_PLLMULL4_Pos) /*!< 0x00080000 */
+#define RCC_CFGR_PLLMULL4 RCC_CFGR_PLLMULL4_Msk /*!< PLL input clock*4 */
+#define RCC_CFGR_PLLMULL5_Pos (18U)
+#define RCC_CFGR_PLLMULL5_Msk (0x3U << RCC_CFGR_PLLMULL5_Pos) /*!< 0x000C0000 */
+#define RCC_CFGR_PLLMULL5 RCC_CFGR_PLLMULL5_Msk /*!< PLL input clock*5 */
+#define RCC_CFGR_PLLMULL6_Pos (20U)
+#define RCC_CFGR_PLLMULL6_Msk (0x1U << RCC_CFGR_PLLMULL6_Pos) /*!< 0x00100000 */
+#define RCC_CFGR_PLLMULL6 RCC_CFGR_PLLMULL6_Msk /*!< PLL input clock*6 */
+#define RCC_CFGR_PLLMULL7_Pos (18U)
+#define RCC_CFGR_PLLMULL7_Msk (0x5U << RCC_CFGR_PLLMULL7_Pos) /*!< 0x00140000 */
+#define RCC_CFGR_PLLMULL7 RCC_CFGR_PLLMULL7_Msk /*!< PLL input clock*7 */
+#define RCC_CFGR_PLLMULL8_Pos (19U)
+#define RCC_CFGR_PLLMULL8_Msk (0x3U << RCC_CFGR_PLLMULL8_Pos) /*!< 0x00180000 */
+#define RCC_CFGR_PLLMULL8 RCC_CFGR_PLLMULL8_Msk /*!< PLL input clock*8 */
+#define RCC_CFGR_PLLMULL9_Pos (18U)
+#define RCC_CFGR_PLLMULL9_Msk (0x7U << RCC_CFGR_PLLMULL9_Pos) /*!< 0x001C0000 */
+#define RCC_CFGR_PLLMULL9 RCC_CFGR_PLLMULL9_Msk /*!< PLL input clock*9 */
+#define RCC_CFGR_PLLMULL10_Pos (21U)
+#define RCC_CFGR_PLLMULL10_Msk (0x1U << RCC_CFGR_PLLMULL10_Pos) /*!< 0x00200000 */
+#define RCC_CFGR_PLLMULL10 RCC_CFGR_PLLMULL10_Msk /*!< PLL input clock10 */
+#define RCC_CFGR_PLLMULL11_Pos (18U)
+#define RCC_CFGR_PLLMULL11_Msk (0x9U << RCC_CFGR_PLLMULL11_Pos) /*!< 0x00240000 */
+#define RCC_CFGR_PLLMULL11 RCC_CFGR_PLLMULL11_Msk /*!< PLL input clock*11 */
+#define RCC_CFGR_PLLMULL12_Pos (19U)
+#define RCC_CFGR_PLLMULL12_Msk (0x5U << RCC_CFGR_PLLMULL12_Pos) /*!< 0x00280000 */
+#define RCC_CFGR_PLLMULL12 RCC_CFGR_PLLMULL12_Msk /*!< PLL input clock*12 */
+#define RCC_CFGR_PLLMULL13_Pos (18U)
+#define RCC_CFGR_PLLMULL13_Msk (0xBU << RCC_CFGR_PLLMULL13_Pos) /*!< 0x002C0000 */
+#define RCC_CFGR_PLLMULL13 RCC_CFGR_PLLMULL13_Msk /*!< PLL input clock*13 */
+#define RCC_CFGR_PLLMULL14_Pos (20U)
+#define RCC_CFGR_PLLMULL14_Msk (0x3U << RCC_CFGR_PLLMULL14_Pos) /*!< 0x00300000 */
+#define RCC_CFGR_PLLMULL14 RCC_CFGR_PLLMULL14_Msk /*!< PLL input clock*14 */
+#define RCC_CFGR_PLLMULL15_Pos (18U)
+#define RCC_CFGR_PLLMULL15_Msk (0xDU << RCC_CFGR_PLLMULL15_Pos) /*!< 0x00340000 */
+#define RCC_CFGR_PLLMULL15 RCC_CFGR_PLLMULL15_Msk /*!< PLL input clock*15 */
+#define RCC_CFGR_PLLMULL16_Pos (19U)
+#define RCC_CFGR_PLLMULL16_Msk (0x7U << RCC_CFGR_PLLMULL16_Pos) /*!< 0x00380000 */
+#define RCC_CFGR_PLLMULL16 RCC_CFGR_PLLMULL16_Msk /*!< PLL input clock*16 */
+
+/*!< MCO configuration */
+#define RCC_CFGR_MCO_Pos (24U)
+#define RCC_CFGR_MCO_Msk (0x7U << RCC_CFGR_MCO_Pos) /*!< 0x07000000 */
+#define RCC_CFGR_MCO RCC_CFGR_MCO_Msk /*!< MCO[2:0] bits (Microcontroller Clock Output) */
+#define RCC_CFGR_MCO_0 (0x1U << RCC_CFGR_MCO_Pos) /*!< 0x01000000 */
+#define RCC_CFGR_MCO_1 (0x2U << RCC_CFGR_MCO_Pos) /*!< 0x02000000 */
+#define RCC_CFGR_MCO_2 (0x4U << RCC_CFGR_MCO_Pos) /*!< 0x04000000 */
+
+#define RCC_CFGR_MCO_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */
+#define RCC_CFGR_MCO_SYSCLK ((uint32_t)0x04000000) /*!< System clock selected as MCO source */
+#define RCC_CFGR_MCO_HSI ((uint32_t)0x05000000) /*!< HSI clock selected as MCO source */
+#define RCC_CFGR_MCO_HSE ((uint32_t)0x06000000) /*!< HSE clock selected as MCO source */
+#define RCC_CFGR_MCO_PLLCLK_DIV2 ((uint32_t)0x07000000) /*!< PLL clock divided by 2 selected as MCO source */
+
+ /* Reference defines */
+ #define RCC_CFGR_MCOSEL RCC_CFGR_MCO
+ #define RCC_CFGR_MCOSEL_0 RCC_CFGR_MCO_0
+ #define RCC_CFGR_MCOSEL_1 RCC_CFGR_MCO_1
+ #define RCC_CFGR_MCOSEL_2 RCC_CFGR_MCO_2
+ #define RCC_CFGR_MCOSEL_NOCLOCK RCC_CFGR_MCO_NOCLOCK
+ #define RCC_CFGR_MCOSEL_SYSCLK RCC_CFGR_MCO_SYSCLK
+ #define RCC_CFGR_MCOSEL_HSI RCC_CFGR_MCO_HSI
+ #define RCC_CFGR_MCOSEL_HSE RCC_CFGR_MCO_HSE
+ #define RCC_CFGR_MCOSEL_PLL_DIV2 RCC_CFGR_MCO_PLLCLK_DIV2
+
+/*!<****************** Bit definition for RCC_CIR register ********************/
+#define RCC_CIR_LSIRDYF_Pos (0U)
+#define RCC_CIR_LSIRDYF_Msk (0x1U << RCC_CIR_LSIRDYF_Pos) /*!< 0x00000001 */
+#define RCC_CIR_LSIRDYF RCC_CIR_LSIRDYF_Msk /*!< LSI Ready Interrupt flag */
+#define RCC_CIR_LSERDYF_Pos (1U)
+#define RCC_CIR_LSERDYF_Msk (0x1U << RCC_CIR_LSERDYF_Pos) /*!< 0x00000002 */
+#define RCC_CIR_LSERDYF RCC_CIR_LSERDYF_Msk /*!< LSE Ready Interrupt flag */
+#define RCC_CIR_HSIRDYF_Pos (2U)
+#define RCC_CIR_HSIRDYF_Msk (0x1U << RCC_CIR_HSIRDYF_Pos) /*!< 0x00000004 */
+#define RCC_CIR_HSIRDYF RCC_CIR_HSIRDYF_Msk /*!< HSI Ready Interrupt flag */
+#define RCC_CIR_HSERDYF_Pos (3U)
+#define RCC_CIR_HSERDYF_Msk (0x1U << RCC_CIR_HSERDYF_Pos) /*!< 0x00000008 */
+#define RCC_CIR_HSERDYF RCC_CIR_HSERDYF_Msk /*!< HSE Ready Interrupt flag */
+#define RCC_CIR_PLLRDYF_Pos (4U)
+#define RCC_CIR_PLLRDYF_Msk (0x1U << RCC_CIR_PLLRDYF_Pos) /*!< 0x00000010 */
+#define RCC_CIR_PLLRDYF RCC_CIR_PLLRDYF_Msk /*!< PLL Ready Interrupt flag */
+#define RCC_CIR_CSSF_Pos (7U)
+#define RCC_CIR_CSSF_Msk (0x1U << RCC_CIR_CSSF_Pos) /*!< 0x00000080 */
+#define RCC_CIR_CSSF RCC_CIR_CSSF_Msk /*!< Clock Security System Interrupt flag */
+#define RCC_CIR_LSIRDYIE_Pos (8U)
+#define RCC_CIR_LSIRDYIE_Msk (0x1U << RCC_CIR_LSIRDYIE_Pos) /*!< 0x00000100 */
+#define RCC_CIR_LSIRDYIE RCC_CIR_LSIRDYIE_Msk /*!< LSI Ready Interrupt Enable */
+#define RCC_CIR_LSERDYIE_Pos (9U)
+#define RCC_CIR_LSERDYIE_Msk (0x1U << RCC_CIR_LSERDYIE_Pos) /*!< 0x00000200 */
+#define RCC_CIR_LSERDYIE RCC_CIR_LSERDYIE_Msk /*!< LSE Ready Interrupt Enable */
+#define RCC_CIR_HSIRDYIE_Pos (10U)
+#define RCC_CIR_HSIRDYIE_Msk (0x1U << RCC_CIR_HSIRDYIE_Pos) /*!< 0x00000400 */
+#define RCC_CIR_HSIRDYIE RCC_CIR_HSIRDYIE_Msk /*!< HSI Ready Interrupt Enable */
+#define RCC_CIR_HSERDYIE_Pos (11U)
+#define RCC_CIR_HSERDYIE_Msk (0x1U << RCC_CIR_HSERDYIE_Pos) /*!< 0x00000800 */
+#define RCC_CIR_HSERDYIE RCC_CIR_HSERDYIE_Msk /*!< HSE Ready Interrupt Enable */
+#define RCC_CIR_PLLRDYIE_Pos (12U)
+#define RCC_CIR_PLLRDYIE_Msk (0x1U << RCC_CIR_PLLRDYIE_Pos) /*!< 0x00001000 */
+#define RCC_CIR_PLLRDYIE RCC_CIR_PLLRDYIE_Msk /*!< PLL Ready Interrupt Enable */
+#define RCC_CIR_LSIRDYC_Pos (16U)
+#define RCC_CIR_LSIRDYC_Msk (0x1U << RCC_CIR_LSIRDYC_Pos) /*!< 0x00010000 */
+#define RCC_CIR_LSIRDYC RCC_CIR_LSIRDYC_Msk /*!< LSI Ready Interrupt Clear */
+#define RCC_CIR_LSERDYC_Pos (17U)
+#define RCC_CIR_LSERDYC_Msk (0x1U << RCC_CIR_LSERDYC_Pos) /*!< 0x00020000 */
+#define RCC_CIR_LSERDYC RCC_CIR_LSERDYC_Msk /*!< LSE Ready Interrupt Clear */
+#define RCC_CIR_HSIRDYC_Pos (18U)
+#define RCC_CIR_HSIRDYC_Msk (0x1U << RCC_CIR_HSIRDYC_Pos) /*!< 0x00040000 */
+#define RCC_CIR_HSIRDYC RCC_CIR_HSIRDYC_Msk /*!< HSI Ready Interrupt Clear */
+#define RCC_CIR_HSERDYC_Pos (19U)
+#define RCC_CIR_HSERDYC_Msk (0x1U << RCC_CIR_HSERDYC_Pos) /*!< 0x00080000 */
+#define RCC_CIR_HSERDYC RCC_CIR_HSERDYC_Msk /*!< HSE Ready Interrupt Clear */
+#define RCC_CIR_PLLRDYC_Pos (20U)
+#define RCC_CIR_PLLRDYC_Msk (0x1U << RCC_CIR_PLLRDYC_Pos) /*!< 0x00100000 */
+#define RCC_CIR_PLLRDYC RCC_CIR_PLLRDYC_Msk /*!< PLL Ready Interrupt Clear */
+#define RCC_CIR_CSSC_Pos (23U)
+#define RCC_CIR_CSSC_Msk (0x1U << RCC_CIR_CSSC_Pos) /*!< 0x00800000 */
+#define RCC_CIR_CSSC RCC_CIR_CSSC_Msk /*!< Clock Security System Interrupt Clear */
+
+
+/***************** Bit definition for RCC_APB2RSTR register *****************/
+#define RCC_APB2RSTR_AFIORST_Pos (0U)
+#define RCC_APB2RSTR_AFIORST_Msk (0x1U << RCC_APB2RSTR_AFIORST_Pos) /*!< 0x00000001 */
+#define RCC_APB2RSTR_AFIORST RCC_APB2RSTR_AFIORST_Msk /*!< Alternate Function I/O reset */
+#define RCC_APB2RSTR_IOPARST_Pos (2U)
+#define RCC_APB2RSTR_IOPARST_Msk (0x1U << RCC_APB2RSTR_IOPARST_Pos) /*!< 0x00000004 */
+#define RCC_APB2RSTR_IOPARST RCC_APB2RSTR_IOPARST_Msk /*!< I/O port A reset */
+#define RCC_APB2RSTR_IOPBRST_Pos (3U)
+#define RCC_APB2RSTR_IOPBRST_Msk (0x1U << RCC_APB2RSTR_IOPBRST_Pos) /*!< 0x00000008 */
+#define RCC_APB2RSTR_IOPBRST RCC_APB2RSTR_IOPBRST_Msk /*!< I/O port B reset */
+#define RCC_APB2RSTR_IOPCRST_Pos (4U)
+#define RCC_APB2RSTR_IOPCRST_Msk (0x1U << RCC_APB2RSTR_IOPCRST_Pos) /*!< 0x00000010 */
+#define RCC_APB2RSTR_IOPCRST RCC_APB2RSTR_IOPCRST_Msk /*!< I/O port C reset */
+#define RCC_APB2RSTR_IOPDRST_Pos (5U)
+#define RCC_APB2RSTR_IOPDRST_Msk (0x1U << RCC_APB2RSTR_IOPDRST_Pos) /*!< 0x00000020 */
+#define RCC_APB2RSTR_IOPDRST RCC_APB2RSTR_IOPDRST_Msk /*!< I/O port D reset */
+#define RCC_APB2RSTR_ADC1RST_Pos (9U)
+#define RCC_APB2RSTR_ADC1RST_Msk (0x1U << RCC_APB2RSTR_ADC1RST_Pos) /*!< 0x00000200 */
+#define RCC_APB2RSTR_ADC1RST RCC_APB2RSTR_ADC1RST_Msk /*!< ADC 1 interface reset */
+
+
+#define RCC_APB2RSTR_TIM1RST_Pos (11U)
+#define RCC_APB2RSTR_TIM1RST_Msk (0x1U << RCC_APB2RSTR_TIM1RST_Pos) /*!< 0x00000800 */
+#define RCC_APB2RSTR_TIM1RST RCC_APB2RSTR_TIM1RST_Msk /*!< TIM1 Timer reset */
+#define RCC_APB2RSTR_SPI1RST_Pos (12U)
+#define RCC_APB2RSTR_SPI1RST_Msk (0x1U << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */
+#define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk /*!< SPI 1 reset */
+#define RCC_APB2RSTR_USART1RST_Pos (14U)
+#define RCC_APB2RSTR_USART1RST_Msk (0x1U << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00004000 */
+#define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk /*!< USART1 reset */
+
+
+
+
+
+
+/***************** Bit definition for RCC_APB1RSTR register *****************/
+#define RCC_APB1RSTR_TIM2RST_Pos (0U)
+#define RCC_APB1RSTR_TIM2RST_Msk (0x1U << RCC_APB1RSTR_TIM2RST_Pos) /*!< 0x00000001 */
+#define RCC_APB1RSTR_TIM2RST RCC_APB1RSTR_TIM2RST_Msk /*!< Timer 2 reset */
+#define RCC_APB1RSTR_TIM3RST_Pos (1U)
+#define RCC_APB1RSTR_TIM3RST_Msk (0x1U << RCC_APB1RSTR_TIM3RST_Pos) /*!< 0x00000002 */
+#define RCC_APB1RSTR_TIM3RST RCC_APB1RSTR_TIM3RST_Msk /*!< Timer 3 reset */
+#define RCC_APB1RSTR_WWDGRST_Pos (11U)
+#define RCC_APB1RSTR_WWDGRST_Msk (0x1U << RCC_APB1RSTR_WWDGRST_Pos) /*!< 0x00000800 */
+#define RCC_APB1RSTR_WWDGRST RCC_APB1RSTR_WWDGRST_Msk /*!< Window Watchdog reset */
+#define RCC_APB1RSTR_USART2RST_Pos (17U)
+#define RCC_APB1RSTR_USART2RST_Msk (0x1U << RCC_APB1RSTR_USART2RST_Pos) /*!< 0x00020000 */
+#define RCC_APB1RSTR_USART2RST RCC_APB1RSTR_USART2RST_Msk /*!< USART 2 reset */
+#define RCC_APB1RSTR_I2C1RST_Pos (21U)
+#define RCC_APB1RSTR_I2C1RST_Msk (0x1U << RCC_APB1RSTR_I2C1RST_Pos) /*!< 0x00200000 */
+#define RCC_APB1RSTR_I2C1RST RCC_APB1RSTR_I2C1RST_Msk /*!< I2C 1 reset */
+
+
+#define RCC_APB1RSTR_BKPRST_Pos (27U)
+#define RCC_APB1RSTR_BKPRST_Msk (0x1U << RCC_APB1RSTR_BKPRST_Pos) /*!< 0x08000000 */
+#define RCC_APB1RSTR_BKPRST RCC_APB1RSTR_BKPRST_Msk /*!< Backup interface reset */
+#define RCC_APB1RSTR_PWRRST_Pos (28U)
+#define RCC_APB1RSTR_PWRRST_Msk (0x1U << RCC_APB1RSTR_PWRRST_Pos) /*!< 0x10000000 */
+#define RCC_APB1RSTR_PWRRST RCC_APB1RSTR_PWRRST_Msk /*!< Power interface reset */
+
+
+
+
+
+
+
+
+/****************** Bit definition for RCC_AHBENR register ******************/
+#define RCC_AHBENR_DMA1EN_Pos (0U)
+#define RCC_AHBENR_DMA1EN_Msk (0x1U << RCC_AHBENR_DMA1EN_Pos) /*!< 0x00000001 */
+#define RCC_AHBENR_DMA1EN RCC_AHBENR_DMA1EN_Msk /*!< DMA1 clock enable */
+#define RCC_AHBENR_SRAMEN_Pos (2U)
+#define RCC_AHBENR_SRAMEN_Msk (0x1U << RCC_AHBENR_SRAMEN_Pos) /*!< 0x00000004 */
+#define RCC_AHBENR_SRAMEN RCC_AHBENR_SRAMEN_Msk /*!< SRAM interface clock enable */
+#define RCC_AHBENR_FLITFEN_Pos (4U)
+#define RCC_AHBENR_FLITFEN_Msk (0x1U << RCC_AHBENR_FLITFEN_Pos) /*!< 0x00000010 */
+#define RCC_AHBENR_FLITFEN RCC_AHBENR_FLITFEN_Msk /*!< FLITF clock enable */
+#define RCC_AHBENR_CRCEN_Pos (6U)
+#define RCC_AHBENR_CRCEN_Msk (0x1U << RCC_AHBENR_CRCEN_Pos) /*!< 0x00000040 */
+#define RCC_AHBENR_CRCEN RCC_AHBENR_CRCEN_Msk /*!< CRC clock enable */
+
+
+
+
+/****************** Bit definition for RCC_APB2ENR register *****************/
+#define RCC_APB2ENR_AFIOEN_Pos (0U)
+#define RCC_APB2ENR_AFIOEN_Msk (0x1U << RCC_APB2ENR_AFIOEN_Pos) /*!< 0x00000001 */
+#define RCC_APB2ENR_AFIOEN RCC_APB2ENR_AFIOEN_Msk /*!< Alternate Function I/O clock enable */
+#define RCC_APB2ENR_IOPAEN_Pos (2U)
+#define RCC_APB2ENR_IOPAEN_Msk (0x1U << RCC_APB2ENR_IOPAEN_Pos) /*!< 0x00000004 */
+#define RCC_APB2ENR_IOPAEN RCC_APB2ENR_IOPAEN_Msk /*!< I/O port A clock enable */
+#define RCC_APB2ENR_IOPBEN_Pos (3U)
+#define RCC_APB2ENR_IOPBEN_Msk (0x1U << RCC_APB2ENR_IOPBEN_Pos) /*!< 0x00000008 */
+#define RCC_APB2ENR_IOPBEN RCC_APB2ENR_IOPBEN_Msk /*!< I/O port B clock enable */
+#define RCC_APB2ENR_IOPCEN_Pos (4U)
+#define RCC_APB2ENR_IOPCEN_Msk (0x1U << RCC_APB2ENR_IOPCEN_Pos) /*!< 0x00000010 */
+#define RCC_APB2ENR_IOPCEN RCC_APB2ENR_IOPCEN_Msk /*!< I/O port C clock enable */
+#define RCC_APB2ENR_IOPDEN_Pos (5U)
+#define RCC_APB2ENR_IOPDEN_Msk (0x1U << RCC_APB2ENR_IOPDEN_Pos) /*!< 0x00000020 */
+#define RCC_APB2ENR_IOPDEN RCC_APB2ENR_IOPDEN_Msk /*!< I/O port D clock enable */
+#define RCC_APB2ENR_ADC1EN_Pos (9U)
+#define RCC_APB2ENR_ADC1EN_Msk (0x1U << RCC_APB2ENR_ADC1EN_Pos) /*!< 0x00000200 */
+#define RCC_APB2ENR_ADC1EN RCC_APB2ENR_ADC1EN_Msk /*!< ADC 1 interface clock enable */
+
+
+#define RCC_APB2ENR_TIM1EN_Pos (11U)
+#define RCC_APB2ENR_TIM1EN_Msk (0x1U << RCC_APB2ENR_TIM1EN_Pos) /*!< 0x00000800 */
+#define RCC_APB2ENR_TIM1EN RCC_APB2ENR_TIM1EN_Msk /*!< TIM1 Timer clock enable */
+#define RCC_APB2ENR_SPI1EN_Pos (12U)
+#define RCC_APB2ENR_SPI1EN_Msk (0x1U << RCC_APB2ENR_SPI1EN_Pos) /*!< 0x00001000 */
+#define RCC_APB2ENR_SPI1EN RCC_APB2ENR_SPI1EN_Msk /*!< SPI 1 clock enable */
+#define RCC_APB2ENR_USART1EN_Pos (14U)
+#define RCC_APB2ENR_USART1EN_Msk (0x1U << RCC_APB2ENR_USART1EN_Pos) /*!< 0x00004000 */
+#define RCC_APB2ENR_USART1EN RCC_APB2ENR_USART1EN_Msk /*!< USART1 clock enable */
+
+
+
+
+
+
+/***************** Bit definition for RCC_APB1ENR register ******************/
+#define RCC_APB1ENR_TIM2EN_Pos (0U)
+#define RCC_APB1ENR_TIM2EN_Msk (0x1U << RCC_APB1ENR_TIM2EN_Pos) /*!< 0x00000001 */
+#define RCC_APB1ENR_TIM2EN RCC_APB1ENR_TIM2EN_Msk /*!< Timer 2 clock enabled*/
+#define RCC_APB1ENR_TIM3EN_Pos (1U)
+#define RCC_APB1ENR_TIM3EN_Msk (0x1U << RCC_APB1ENR_TIM3EN_Pos) /*!< 0x00000002 */
+#define RCC_APB1ENR_TIM3EN RCC_APB1ENR_TIM3EN_Msk /*!< Timer 3 clock enable */
+#define RCC_APB1ENR_WWDGEN_Pos (11U)
+#define RCC_APB1ENR_WWDGEN_Msk (0x1U << RCC_APB1ENR_WWDGEN_Pos) /*!< 0x00000800 */
+#define RCC_APB1ENR_WWDGEN RCC_APB1ENR_WWDGEN_Msk /*!< Window Watchdog clock enable */
+#define RCC_APB1ENR_USART2EN_Pos (17U)
+#define RCC_APB1ENR_USART2EN_Msk (0x1U << RCC_APB1ENR_USART2EN_Pos) /*!< 0x00020000 */
+#define RCC_APB1ENR_USART2EN RCC_APB1ENR_USART2EN_Msk /*!< USART 2 clock enable */
+#define RCC_APB1ENR_I2C1EN_Pos (21U)
+#define RCC_APB1ENR_I2C1EN_Msk (0x1U << RCC_APB1ENR_I2C1EN_Pos) /*!< 0x00200000 */
+#define RCC_APB1ENR_I2C1EN RCC_APB1ENR_I2C1EN_Msk /*!< I2C 1 clock enable */
+
+
+#define RCC_APB1ENR_BKPEN_Pos (27U)
+#define RCC_APB1ENR_BKPEN_Msk (0x1U << RCC_APB1ENR_BKPEN_Pos) /*!< 0x08000000 */
+#define RCC_APB1ENR_BKPEN RCC_APB1ENR_BKPEN_Msk /*!< Backup interface clock enable */
+#define RCC_APB1ENR_PWREN_Pos (28U)
+#define RCC_APB1ENR_PWREN_Msk (0x1U << RCC_APB1ENR_PWREN_Pos) /*!< 0x10000000 */
+#define RCC_APB1ENR_PWREN RCC_APB1ENR_PWREN_Msk /*!< Power interface clock enable */
+
+
+
+
+
+
+
+
+/******************* Bit definition for RCC_BDCR register *******************/
+#define RCC_BDCR_LSEON_Pos (0U)
+#define RCC_BDCR_LSEON_Msk (0x1U << RCC_BDCR_LSEON_Pos) /*!< 0x00000001 */
+#define RCC_BDCR_LSEON RCC_BDCR_LSEON_Msk /*!< External Low Speed oscillator enable */
+#define RCC_BDCR_LSERDY_Pos (1U)
+#define RCC_BDCR_LSERDY_Msk (0x1U << RCC_BDCR_LSERDY_Pos) /*!< 0x00000002 */
+#define RCC_BDCR_LSERDY RCC_BDCR_LSERDY_Msk /*!< External Low Speed oscillator Ready */
+#define RCC_BDCR_LSEBYP_Pos (2U)
+#define RCC_BDCR_LSEBYP_Msk (0x1U << RCC_BDCR_LSEBYP_Pos) /*!< 0x00000004 */
+#define RCC_BDCR_LSEBYP RCC_BDCR_LSEBYP_Msk /*!< External Low Speed oscillator Bypass */
+
+#define RCC_BDCR_RTCSEL_Pos (8U)
+#define RCC_BDCR_RTCSEL_Msk (0x3U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000300 */
+#define RCC_BDCR_RTCSEL RCC_BDCR_RTCSEL_Msk /*!< RTCSEL[1:0] bits (RTC clock source selection) */
+#define RCC_BDCR_RTCSEL_0 (0x1U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000100 */
+#define RCC_BDCR_RTCSEL_1 (0x2U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000200 */
+
+/*!< RTC congiguration */
+#define RCC_BDCR_RTCSEL_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */
+#define RCC_BDCR_RTCSEL_LSE ((uint32_t)0x00000100) /*!< LSE oscillator clock used as RTC clock */
+#define RCC_BDCR_RTCSEL_LSI ((uint32_t)0x00000200) /*!< LSI oscillator clock used as RTC clock */
+#define RCC_BDCR_RTCSEL_HSE ((uint32_t)0x00000300) /*!< HSE oscillator clock divided by 128 used as RTC clock */
+
+#define RCC_BDCR_RTCEN_Pos (15U)
+#define RCC_BDCR_RTCEN_Msk (0x1U << RCC_BDCR_RTCEN_Pos) /*!< 0x00008000 */
+#define RCC_BDCR_RTCEN RCC_BDCR_RTCEN_Msk /*!< RTC clock enable */
+#define RCC_BDCR_BDRST_Pos (16U)
+#define RCC_BDCR_BDRST_Msk (0x1U << RCC_BDCR_BDRST_Pos) /*!< 0x00010000 */
+#define RCC_BDCR_BDRST RCC_BDCR_BDRST_Msk /*!< Backup domain software reset */
+
+/******************* Bit definition for RCC_CSR register ********************/
+#define RCC_CSR_LSION_Pos (0U)
+#define RCC_CSR_LSION_Msk (0x1U << RCC_CSR_LSION_Pos) /*!< 0x00000001 */
+#define RCC_CSR_LSION RCC_CSR_LSION_Msk /*!< Internal Low Speed oscillator enable */
+#define RCC_CSR_LSIRDY_Pos (1U)
+#define RCC_CSR_LSIRDY_Msk (0x1U << RCC_CSR_LSIRDY_Pos) /*!< 0x00000002 */
+#define RCC_CSR_LSIRDY RCC_CSR_LSIRDY_Msk /*!< Internal Low Speed oscillator Ready */
+#define RCC_CSR_RMVF_Pos (24U)
+#define RCC_CSR_RMVF_Msk (0x1U << RCC_CSR_RMVF_Pos) /*!< 0x01000000 */
+#define RCC_CSR_RMVF RCC_CSR_RMVF_Msk /*!< Remove reset flag */
+#define RCC_CSR_PINRSTF_Pos (26U)
+#define RCC_CSR_PINRSTF_Msk (0x1U << RCC_CSR_PINRSTF_Pos) /*!< 0x04000000 */
+#define RCC_CSR_PINRSTF RCC_CSR_PINRSTF_Msk /*!< PIN reset flag */
+#define RCC_CSR_PORRSTF_Pos (27U)
+#define RCC_CSR_PORRSTF_Msk (0x1U << RCC_CSR_PORRSTF_Pos) /*!< 0x08000000 */
+#define RCC_CSR_PORRSTF RCC_CSR_PORRSTF_Msk /*!< POR/PDR reset flag */
+#define RCC_CSR_SFTRSTF_Pos (28U)
+#define RCC_CSR_SFTRSTF_Msk (0x1U << RCC_CSR_SFTRSTF_Pos) /*!< 0x10000000 */
+#define RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF_Msk /*!< Software Reset flag */
+#define RCC_CSR_IWDGRSTF_Pos (29U)
+#define RCC_CSR_IWDGRSTF_Msk (0x1U << RCC_CSR_IWDGRSTF_Pos) /*!< 0x20000000 */
+#define RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF_Msk /*!< Independent Watchdog reset flag */
+#define RCC_CSR_WWDGRSTF_Pos (30U)
+#define RCC_CSR_WWDGRSTF_Msk (0x1U << RCC_CSR_WWDGRSTF_Pos) /*!< 0x40000000 */
+#define RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF_Msk /*!< Window watchdog reset flag */
+#define RCC_CSR_LPWRRSTF_Pos (31U)
+#define RCC_CSR_LPWRRSTF_Msk (0x1U << RCC_CSR_LPWRRSTF_Pos) /*!< 0x80000000 */
+#define RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF_Msk /*!< Low-Power reset flag */
+
+
+
+/******************************************************************************/
+/* */
+/* General Purpose and Alternate Function I/O */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for GPIO_CRL register *******************/
+#define GPIO_CRL_MODE_Pos (0U)
+#define GPIO_CRL_MODE_Msk (0x33333333U << GPIO_CRL_MODE_Pos) /*!< 0x33333333 */
+#define GPIO_CRL_MODE GPIO_CRL_MODE_Msk /*!< Port x mode bits */
+
+#define GPIO_CRL_MODE0_Pos (0U)
+#define GPIO_CRL_MODE0_Msk (0x3U << GPIO_CRL_MODE0_Pos) /*!< 0x00000003 */
+#define GPIO_CRL_MODE0 GPIO_CRL_MODE0_Msk /*!< MODE0[1:0] bits (Port x mode bits, pin 0) */
+#define GPIO_CRL_MODE0_0 (0x1U << GPIO_CRL_MODE0_Pos) /*!< 0x00000001 */
+#define GPIO_CRL_MODE0_1 (0x2U << GPIO_CRL_MODE0_Pos) /*!< 0x00000002 */
+
+#define GPIO_CRL_MODE1_Pos (4U)
+#define GPIO_CRL_MODE1_Msk (0x3U << GPIO_CRL_MODE1_Pos) /*!< 0x00000030 */
+#define GPIO_CRL_MODE1 GPIO_CRL_MODE1_Msk /*!< MODE1[1:0] bits (Port x mode bits, pin 1) */
+#define GPIO_CRL_MODE1_0 (0x1U << GPIO_CRL_MODE1_Pos) /*!< 0x00000010 */
+#define GPIO_CRL_MODE1_1 (0x2U << GPIO_CRL_MODE1_Pos) /*!< 0x00000020 */
+
+#define GPIO_CRL_MODE2_Pos (8U)
+#define GPIO_CRL_MODE2_Msk (0x3U << GPIO_CRL_MODE2_Pos) /*!< 0x00000300 */
+#define GPIO_CRL_MODE2 GPIO_CRL_MODE2_Msk /*!< MODE2[1:0] bits (Port x mode bits, pin 2) */
+#define GPIO_CRL_MODE2_0 (0x1U << GPIO_CRL_MODE2_Pos) /*!< 0x00000100 */
+#define GPIO_CRL_MODE2_1 (0x2U << GPIO_CRL_MODE2_Pos) /*!< 0x00000200 */
+
+#define GPIO_CRL_MODE3_Pos (12U)
+#define GPIO_CRL_MODE3_Msk (0x3U << GPIO_CRL_MODE3_Pos) /*!< 0x00003000 */
+#define GPIO_CRL_MODE3 GPIO_CRL_MODE3_Msk /*!< MODE3[1:0] bits (Port x mode bits, pin 3) */
+#define GPIO_CRL_MODE3_0 (0x1U << GPIO_CRL_MODE3_Pos) /*!< 0x00001000 */
+#define GPIO_CRL_MODE3_1 (0x2U << GPIO_CRL_MODE3_Pos) /*!< 0x00002000 */
+
+#define GPIO_CRL_MODE4_Pos (16U)
+#define GPIO_CRL_MODE4_Msk (0x3U << GPIO_CRL_MODE4_Pos) /*!< 0x00030000 */
+#define GPIO_CRL_MODE4 GPIO_CRL_MODE4_Msk /*!< MODE4[1:0] bits (Port x mode bits, pin 4) */
+#define GPIO_CRL_MODE4_0 (0x1U << GPIO_CRL_MODE4_Pos) /*!< 0x00010000 */
+#define GPIO_CRL_MODE4_1 (0x2U << GPIO_CRL_MODE4_Pos) /*!< 0x00020000 */
+
+#define GPIO_CRL_MODE5_Pos (20U)
+#define GPIO_CRL_MODE5_Msk (0x3U << GPIO_CRL_MODE5_Pos) /*!< 0x00300000 */
+#define GPIO_CRL_MODE5 GPIO_CRL_MODE5_Msk /*!< MODE5[1:0] bits (Port x mode bits, pin 5) */
+#define GPIO_CRL_MODE5_0 (0x1U << GPIO_CRL_MODE5_Pos) /*!< 0x00100000 */
+#define GPIO_CRL_MODE5_1 (0x2U << GPIO_CRL_MODE5_Pos) /*!< 0x00200000 */
+
+#define GPIO_CRL_MODE6_Pos (24U)
+#define GPIO_CRL_MODE6_Msk (0x3U << GPIO_CRL_MODE6_Pos) /*!< 0x03000000 */
+#define GPIO_CRL_MODE6 GPIO_CRL_MODE6_Msk /*!< MODE6[1:0] bits (Port x mode bits, pin 6) */
+#define GPIO_CRL_MODE6_0 (0x1U << GPIO_CRL_MODE6_Pos) /*!< 0x01000000 */
+#define GPIO_CRL_MODE6_1 (0x2U << GPIO_CRL_MODE6_Pos) /*!< 0x02000000 */
+
+#define GPIO_CRL_MODE7_Pos (28U)
+#define GPIO_CRL_MODE7_Msk (0x3U << GPIO_CRL_MODE7_Pos) /*!< 0x30000000 */
+#define GPIO_CRL_MODE7 GPIO_CRL_MODE7_Msk /*!< MODE7[1:0] bits (Port x mode bits, pin 7) */
+#define GPIO_CRL_MODE7_0 (0x1U << GPIO_CRL_MODE7_Pos) /*!< 0x10000000 */
+#define GPIO_CRL_MODE7_1 (0x2U << GPIO_CRL_MODE7_Pos) /*!< 0x20000000 */
+
+#define GPIO_CRL_CNF_Pos (2U)
+#define GPIO_CRL_CNF_Msk (0x33333333U << GPIO_CRL_CNF_Pos) /*!< 0xCCCCCCCC */
+#define GPIO_CRL_CNF GPIO_CRL_CNF_Msk /*!< Port x configuration bits */
+
+#define GPIO_CRL_CNF0_Pos (2U)
+#define GPIO_CRL_CNF0_Msk (0x3U << GPIO_CRL_CNF0_Pos) /*!< 0x0000000C */
+#define GPIO_CRL_CNF0 GPIO_CRL_CNF0_Msk /*!< CNF0[1:0] bits (Port x configuration bits, pin 0) */
+#define GPIO_CRL_CNF0_0 (0x1U << GPIO_CRL_CNF0_Pos) /*!< 0x00000004 */
+#define GPIO_CRL_CNF0_1 (0x2U << GPIO_CRL_CNF0_Pos) /*!< 0x00000008 */
+
+#define GPIO_CRL_CNF1_Pos (6U)
+#define GPIO_CRL_CNF1_Msk (0x3U << GPIO_CRL_CNF1_Pos) /*!< 0x000000C0 */
+#define GPIO_CRL_CNF1 GPIO_CRL_CNF1_Msk /*!< CNF1[1:0] bits (Port x configuration bits, pin 1) */
+#define GPIO_CRL_CNF1_0 (0x1U << GPIO_CRL_CNF1_Pos) /*!< 0x00000040 */
+#define GPIO_CRL_CNF1_1 (0x2U << GPIO_CRL_CNF1_Pos) /*!< 0x00000080 */
+
+#define GPIO_CRL_CNF2_Pos (10U)
+#define GPIO_CRL_CNF2_Msk (0x3U << GPIO_CRL_CNF2_Pos) /*!< 0x00000C00 */
+#define GPIO_CRL_CNF2 GPIO_CRL_CNF2_Msk /*!< CNF2[1:0] bits (Port x configuration bits, pin 2) */
+#define GPIO_CRL_CNF2_0 (0x1U << GPIO_CRL_CNF2_Pos) /*!< 0x00000400 */
+#define GPIO_CRL_CNF2_1 (0x2U << GPIO_CRL_CNF2_Pos) /*!< 0x00000800 */
+
+#define GPIO_CRL_CNF3_Pos (14U)
+#define GPIO_CRL_CNF3_Msk (0x3U << GPIO_CRL_CNF3_Pos) /*!< 0x0000C000 */
+#define GPIO_CRL_CNF3 GPIO_CRL_CNF3_Msk /*!< CNF3[1:0] bits (Port x configuration bits, pin 3) */
+#define GPIO_CRL_CNF3_0 (0x1U << GPIO_CRL_CNF3_Pos) /*!< 0x00004000 */
+#define GPIO_CRL_CNF3_1 (0x2U << GPIO_CRL_CNF3_Pos) /*!< 0x00008000 */
+
+#define GPIO_CRL_CNF4_Pos (18U)
+#define GPIO_CRL_CNF4_Msk (0x3U << GPIO_CRL_CNF4_Pos) /*!< 0x000C0000 */
+#define GPIO_CRL_CNF4 GPIO_CRL_CNF4_Msk /*!< CNF4[1:0] bits (Port x configuration bits, pin 4) */
+#define GPIO_CRL_CNF4_0 (0x1U << GPIO_CRL_CNF4_Pos) /*!< 0x00040000 */
+#define GPIO_CRL_CNF4_1 (0x2U << GPIO_CRL_CNF4_Pos) /*!< 0x00080000 */
+
+#define GPIO_CRL_CNF5_Pos (22U)
+#define GPIO_CRL_CNF5_Msk (0x3U << GPIO_CRL_CNF5_Pos) /*!< 0x00C00000 */
+#define GPIO_CRL_CNF5 GPIO_CRL_CNF5_Msk /*!< CNF5[1:0] bits (Port x configuration bits, pin 5) */
+#define GPIO_CRL_CNF5_0 (0x1U << GPIO_CRL_CNF5_Pos) /*!< 0x00400000 */
+#define GPIO_CRL_CNF5_1 (0x2U << GPIO_CRL_CNF5_Pos) /*!< 0x00800000 */
+
+#define GPIO_CRL_CNF6_Pos (26U)
+#define GPIO_CRL_CNF6_Msk (0x3U << GPIO_CRL_CNF6_Pos) /*!< 0x0C000000 */
+#define GPIO_CRL_CNF6 GPIO_CRL_CNF6_Msk /*!< CNF6[1:0] bits (Port x configuration bits, pin 6) */
+#define GPIO_CRL_CNF6_0 (0x1U << GPIO_CRL_CNF6_Pos) /*!< 0x04000000 */
+#define GPIO_CRL_CNF6_1 (0x2U << GPIO_CRL_CNF6_Pos) /*!< 0x08000000 */
+
+#define GPIO_CRL_CNF7_Pos (30U)
+#define GPIO_CRL_CNF7_Msk (0x3U << GPIO_CRL_CNF7_Pos) /*!< 0xC0000000 */
+#define GPIO_CRL_CNF7 GPIO_CRL_CNF7_Msk /*!< CNF7[1:0] bits (Port x configuration bits, pin 7) */
+#define GPIO_CRL_CNF7_0 (0x1U << GPIO_CRL_CNF7_Pos) /*!< 0x40000000 */
+#define GPIO_CRL_CNF7_1 (0x2U << GPIO_CRL_CNF7_Pos) /*!< 0x80000000 */
+
+/******************* Bit definition for GPIO_CRH register *******************/
+#define GPIO_CRH_MODE_Pos (0U)
+#define GPIO_CRH_MODE_Msk (0x33333333U << GPIO_CRH_MODE_Pos) /*!< 0x33333333 */
+#define GPIO_CRH_MODE GPIO_CRH_MODE_Msk /*!< Port x mode bits */
+
+#define GPIO_CRH_MODE8_Pos (0U)
+#define GPIO_CRH_MODE8_Msk (0x3U << GPIO_CRH_MODE8_Pos) /*!< 0x00000003 */
+#define GPIO_CRH_MODE8 GPIO_CRH_MODE8_Msk /*!< MODE8[1:0] bits (Port x mode bits, pin 8) */
+#define GPIO_CRH_MODE8_0 (0x1U << GPIO_CRH_MODE8_Pos) /*!< 0x00000001 */
+#define GPIO_CRH_MODE8_1 (0x2U << GPIO_CRH_MODE8_Pos) /*!< 0x00000002 */
+
+#define GPIO_CRH_MODE9_Pos (4U)
+#define GPIO_CRH_MODE9_Msk (0x3U << GPIO_CRH_MODE9_Pos) /*!< 0x00000030 */
+#define GPIO_CRH_MODE9 GPIO_CRH_MODE9_Msk /*!< MODE9[1:0] bits (Port x mode bits, pin 9) */
+#define GPIO_CRH_MODE9_0 (0x1U << GPIO_CRH_MODE9_Pos) /*!< 0x00000010 */
+#define GPIO_CRH_MODE9_1 (0x2U << GPIO_CRH_MODE9_Pos) /*!< 0x00000020 */
+
+#define GPIO_CRH_MODE10_Pos (8U)
+#define GPIO_CRH_MODE10_Msk (0x3U << GPIO_CRH_MODE10_Pos) /*!< 0x00000300 */
+#define GPIO_CRH_MODE10 GPIO_CRH_MODE10_Msk /*!< MODE10[1:0] bits (Port x mode bits, pin 10) */
+#define GPIO_CRH_MODE10_0 (0x1U << GPIO_CRH_MODE10_Pos) /*!< 0x00000100 */
+#define GPIO_CRH_MODE10_1 (0x2U << GPIO_CRH_MODE10_Pos) /*!< 0x00000200 */
+
+#define GPIO_CRH_MODE11_Pos (12U)
+#define GPIO_CRH_MODE11_Msk (0x3U << GPIO_CRH_MODE11_Pos) /*!< 0x00003000 */
+#define GPIO_CRH_MODE11 GPIO_CRH_MODE11_Msk /*!< MODE11[1:0] bits (Port x mode bits, pin 11) */
+#define GPIO_CRH_MODE11_0 (0x1U << GPIO_CRH_MODE11_Pos) /*!< 0x00001000 */
+#define GPIO_CRH_MODE11_1 (0x2U << GPIO_CRH_MODE11_Pos) /*!< 0x00002000 */
+
+#define GPIO_CRH_MODE12_Pos (16U)
+#define GPIO_CRH_MODE12_Msk (0x3U << GPIO_CRH_MODE12_Pos) /*!< 0x00030000 */
+#define GPIO_CRH_MODE12 GPIO_CRH_MODE12_Msk /*!< MODE12[1:0] bits (Port x mode bits, pin 12) */
+#define GPIO_CRH_MODE12_0 (0x1U << GPIO_CRH_MODE12_Pos) /*!< 0x00010000 */
+#define GPIO_CRH_MODE12_1 (0x2U << GPIO_CRH_MODE12_Pos) /*!< 0x00020000 */
+
+#define GPIO_CRH_MODE13_Pos (20U)
+#define GPIO_CRH_MODE13_Msk (0x3U << GPIO_CRH_MODE13_Pos) /*!< 0x00300000 */
+#define GPIO_CRH_MODE13 GPIO_CRH_MODE13_Msk /*!< MODE13[1:0] bits (Port x mode bits, pin 13) */
+#define GPIO_CRH_MODE13_0 (0x1U << GPIO_CRH_MODE13_Pos) /*!< 0x00100000 */
+#define GPIO_CRH_MODE13_1 (0x2U << GPIO_CRH_MODE13_Pos) /*!< 0x00200000 */
+
+#define GPIO_CRH_MODE14_Pos (24U)
+#define GPIO_CRH_MODE14_Msk (0x3U << GPIO_CRH_MODE14_Pos) /*!< 0x03000000 */
+#define GPIO_CRH_MODE14 GPIO_CRH_MODE14_Msk /*!< MODE14[1:0] bits (Port x mode bits, pin 14) */
+#define GPIO_CRH_MODE14_0 (0x1U << GPIO_CRH_MODE14_Pos) /*!< 0x01000000 */
+#define GPIO_CRH_MODE14_1 (0x2U << GPIO_CRH_MODE14_Pos) /*!< 0x02000000 */
+
+#define GPIO_CRH_MODE15_Pos (28U)
+#define GPIO_CRH_MODE15_Msk (0x3U << GPIO_CRH_MODE15_Pos) /*!< 0x30000000 */
+#define GPIO_CRH_MODE15 GPIO_CRH_MODE15_Msk /*!< MODE15[1:0] bits (Port x mode bits, pin 15) */
+#define GPIO_CRH_MODE15_0 (0x1U << GPIO_CRH_MODE15_Pos) /*!< 0x10000000 */
+#define GPIO_CRH_MODE15_1 (0x2U << GPIO_CRH_MODE15_Pos) /*!< 0x20000000 */
+
+#define GPIO_CRH_CNF_Pos (2U)
+#define GPIO_CRH_CNF_Msk (0x33333333U << GPIO_CRH_CNF_Pos) /*!< 0xCCCCCCCC */
+#define GPIO_CRH_CNF GPIO_CRH_CNF_Msk /*!< Port x configuration bits */
+
+#define GPIO_CRH_CNF8_Pos (2U)
+#define GPIO_CRH_CNF8_Msk (0x3U << GPIO_CRH_CNF8_Pos) /*!< 0x0000000C */
+#define GPIO_CRH_CNF8 GPIO_CRH_CNF8_Msk /*!< CNF8[1:0] bits (Port x configuration bits, pin 8) */
+#define GPIO_CRH_CNF8_0 (0x1U << GPIO_CRH_CNF8_Pos) /*!< 0x00000004 */
+#define GPIO_CRH_CNF8_1 (0x2U << GPIO_CRH_CNF8_Pos) /*!< 0x00000008 */
+
+#define GPIO_CRH_CNF9_Pos (6U)
+#define GPIO_CRH_CNF9_Msk (0x3U << GPIO_CRH_CNF9_Pos) /*!< 0x000000C0 */
+#define GPIO_CRH_CNF9 GPIO_CRH_CNF9_Msk /*!< CNF9[1:0] bits (Port x configuration bits, pin 9) */
+#define GPIO_CRH_CNF9_0 (0x1U << GPIO_CRH_CNF9_Pos) /*!< 0x00000040 */
+#define GPIO_CRH_CNF9_1 (0x2U << GPIO_CRH_CNF9_Pos) /*!< 0x00000080 */
+
+#define GPIO_CRH_CNF10_Pos (10U)
+#define GPIO_CRH_CNF10_Msk (0x3U << GPIO_CRH_CNF10_Pos) /*!< 0x00000C00 */
+#define GPIO_CRH_CNF10 GPIO_CRH_CNF10_Msk /*!< CNF10[1:0] bits (Port x configuration bits, pin 10) */
+#define GPIO_CRH_CNF10_0 (0x1U << GPIO_CRH_CNF10_Pos) /*!< 0x00000400 */
+#define GPIO_CRH_CNF10_1 (0x2U << GPIO_CRH_CNF10_Pos) /*!< 0x00000800 */
+
+#define GPIO_CRH_CNF11_Pos (14U)
+#define GPIO_CRH_CNF11_Msk (0x3U << GPIO_CRH_CNF11_Pos) /*!< 0x0000C000 */
+#define GPIO_CRH_CNF11 GPIO_CRH_CNF11_Msk /*!< CNF11[1:0] bits (Port x configuration bits, pin 11) */
+#define GPIO_CRH_CNF11_0 (0x1U << GPIO_CRH_CNF11_Pos) /*!< 0x00004000 */
+#define GPIO_CRH_CNF11_1 (0x2U << GPIO_CRH_CNF11_Pos) /*!< 0x00008000 */
+
+#define GPIO_CRH_CNF12_Pos (18U)
+#define GPIO_CRH_CNF12_Msk (0x3U << GPIO_CRH_CNF12_Pos) /*!< 0x000C0000 */
+#define GPIO_CRH_CNF12 GPIO_CRH_CNF12_Msk /*!< CNF12[1:0] bits (Port x configuration bits, pin 12) */
+#define GPIO_CRH_CNF12_0 (0x1U << GPIO_CRH_CNF12_Pos) /*!< 0x00040000 */
+#define GPIO_CRH_CNF12_1 (0x2U << GPIO_CRH_CNF12_Pos) /*!< 0x00080000 */
+
+#define GPIO_CRH_CNF13_Pos (22U)
+#define GPIO_CRH_CNF13_Msk (0x3U << GPIO_CRH_CNF13_Pos) /*!< 0x00C00000 */
+#define GPIO_CRH_CNF13 GPIO_CRH_CNF13_Msk /*!< CNF13[1:0] bits (Port x configuration bits, pin 13) */
+#define GPIO_CRH_CNF13_0 (0x1U << GPIO_CRH_CNF13_Pos) /*!< 0x00400000 */
+#define GPIO_CRH_CNF13_1 (0x2U << GPIO_CRH_CNF13_Pos) /*!< 0x00800000 */
+
+#define GPIO_CRH_CNF14_Pos (26U)
+#define GPIO_CRH_CNF14_Msk (0x3U << GPIO_CRH_CNF14_Pos) /*!< 0x0C000000 */
+#define GPIO_CRH_CNF14 GPIO_CRH_CNF14_Msk /*!< CNF14[1:0] bits (Port x configuration bits, pin 14) */
+#define GPIO_CRH_CNF14_0 (0x1U << GPIO_CRH_CNF14_Pos) /*!< 0x04000000 */
+#define GPIO_CRH_CNF14_1 (0x2U << GPIO_CRH_CNF14_Pos) /*!< 0x08000000 */
+
+#define GPIO_CRH_CNF15_Pos (30U)
+#define GPIO_CRH_CNF15_Msk (0x3U << GPIO_CRH_CNF15_Pos) /*!< 0xC0000000 */
+#define GPIO_CRH_CNF15 GPIO_CRH_CNF15_Msk /*!< CNF15[1:0] bits (Port x configuration bits, pin 15) */
+#define GPIO_CRH_CNF15_0 (0x1U << GPIO_CRH_CNF15_Pos) /*!< 0x40000000 */
+#define GPIO_CRH_CNF15_1 (0x2U << GPIO_CRH_CNF15_Pos) /*!< 0x80000000 */
+
+/*!<****************** Bit definition for GPIO_IDR register *******************/
+#define GPIO_IDR_IDR0_Pos (0U)
+#define GPIO_IDR_IDR0_Msk (0x1U << GPIO_IDR_IDR0_Pos) /*!< 0x00000001 */
+#define GPIO_IDR_IDR0 GPIO_IDR_IDR0_Msk /*!< Port input data, bit 0 */
+#define GPIO_IDR_IDR1_Pos (1U)
+#define GPIO_IDR_IDR1_Msk (0x1U << GPIO_IDR_IDR1_Pos) /*!< 0x00000002 */
+#define GPIO_IDR_IDR1 GPIO_IDR_IDR1_Msk /*!< Port input data, bit 1 */
+#define GPIO_IDR_IDR2_Pos (2U)
+#define GPIO_IDR_IDR2_Msk (0x1U << GPIO_IDR_IDR2_Pos) /*!< 0x00000004 */
+#define GPIO_IDR_IDR2 GPIO_IDR_IDR2_Msk /*!< Port input data, bit 2 */
+#define GPIO_IDR_IDR3_Pos (3U)
+#define GPIO_IDR_IDR3_Msk (0x1U << GPIO_IDR_IDR3_Pos) /*!< 0x00000008 */
+#define GPIO_IDR_IDR3 GPIO_IDR_IDR3_Msk /*!< Port input data, bit 3 */
+#define GPIO_IDR_IDR4_Pos (4U)
+#define GPIO_IDR_IDR4_Msk (0x1U << GPIO_IDR_IDR4_Pos) /*!< 0x00000010 */
+#define GPIO_IDR_IDR4 GPIO_IDR_IDR4_Msk /*!< Port input data, bit 4 */
+#define GPIO_IDR_IDR5_Pos (5U)
+#define GPIO_IDR_IDR5_Msk (0x1U << GPIO_IDR_IDR5_Pos) /*!< 0x00000020 */
+#define GPIO_IDR_IDR5 GPIO_IDR_IDR5_Msk /*!< Port input data, bit 5 */
+#define GPIO_IDR_IDR6_Pos (6U)
+#define GPIO_IDR_IDR6_Msk (0x1U << GPIO_IDR_IDR6_Pos) /*!< 0x00000040 */
+#define GPIO_IDR_IDR6 GPIO_IDR_IDR6_Msk /*!< Port input data, bit 6 */
+#define GPIO_IDR_IDR7_Pos (7U)
+#define GPIO_IDR_IDR7_Msk (0x1U << GPIO_IDR_IDR7_Pos) /*!< 0x00000080 */
+#define GPIO_IDR_IDR7 GPIO_IDR_IDR7_Msk /*!< Port input data, bit 7 */
+#define GPIO_IDR_IDR8_Pos (8U)
+#define GPIO_IDR_IDR8_Msk (0x1U << GPIO_IDR_IDR8_Pos) /*!< 0x00000100 */
+#define GPIO_IDR_IDR8 GPIO_IDR_IDR8_Msk /*!< Port input data, bit 8 */
+#define GPIO_IDR_IDR9_Pos (9U)
+#define GPIO_IDR_IDR9_Msk (0x1U << GPIO_IDR_IDR9_Pos) /*!< 0x00000200 */
+#define GPIO_IDR_IDR9 GPIO_IDR_IDR9_Msk /*!< Port input data, bit 9 */
+#define GPIO_IDR_IDR10_Pos (10U)
+#define GPIO_IDR_IDR10_Msk (0x1U << GPIO_IDR_IDR10_Pos) /*!< 0x00000400 */
+#define GPIO_IDR_IDR10 GPIO_IDR_IDR10_Msk /*!< Port input data, bit 10 */
+#define GPIO_IDR_IDR11_Pos (11U)
+#define GPIO_IDR_IDR11_Msk (0x1U << GPIO_IDR_IDR11_Pos) /*!< 0x00000800 */
+#define GPIO_IDR_IDR11 GPIO_IDR_IDR11_Msk /*!< Port input data, bit 11 */
+#define GPIO_IDR_IDR12_Pos (12U)
+#define GPIO_IDR_IDR12_Msk (0x1U << GPIO_IDR_IDR12_Pos) /*!< 0x00001000 */
+#define GPIO_IDR_IDR12 GPIO_IDR_IDR12_Msk /*!< Port input data, bit 12 */
+#define GPIO_IDR_IDR13_Pos (13U)
+#define GPIO_IDR_IDR13_Msk (0x1U << GPIO_IDR_IDR13_Pos) /*!< 0x00002000 */
+#define GPIO_IDR_IDR13 GPIO_IDR_IDR13_Msk /*!< Port input data, bit 13 */
+#define GPIO_IDR_IDR14_Pos (14U)
+#define GPIO_IDR_IDR14_Msk (0x1U << GPIO_IDR_IDR14_Pos) /*!< 0x00004000 */
+#define GPIO_IDR_IDR14 GPIO_IDR_IDR14_Msk /*!< Port input data, bit 14 */
+#define GPIO_IDR_IDR15_Pos (15U)
+#define GPIO_IDR_IDR15_Msk (0x1U << GPIO_IDR_IDR15_Pos) /*!< 0x00008000 */
+#define GPIO_IDR_IDR15 GPIO_IDR_IDR15_Msk /*!< Port input data, bit 15 */
+
+/******************* Bit definition for GPIO_ODR register *******************/
+#define GPIO_ODR_ODR0_Pos (0U)
+#define GPIO_ODR_ODR0_Msk (0x1U << GPIO_ODR_ODR0_Pos) /*!< 0x00000001 */
+#define GPIO_ODR_ODR0 GPIO_ODR_ODR0_Msk /*!< Port output data, bit 0 */
+#define GPIO_ODR_ODR1_Pos (1U)
+#define GPIO_ODR_ODR1_Msk (0x1U << GPIO_ODR_ODR1_Pos) /*!< 0x00000002 */
+#define GPIO_ODR_ODR1 GPIO_ODR_ODR1_Msk /*!< Port output data, bit 1 */
+#define GPIO_ODR_ODR2_Pos (2U)
+#define GPIO_ODR_ODR2_Msk (0x1U << GPIO_ODR_ODR2_Pos) /*!< 0x00000004 */
+#define GPIO_ODR_ODR2 GPIO_ODR_ODR2_Msk /*!< Port output data, bit 2 */
+#define GPIO_ODR_ODR3_Pos (3U)
+#define GPIO_ODR_ODR3_Msk (0x1U << GPIO_ODR_ODR3_Pos) /*!< 0x00000008 */
+#define GPIO_ODR_ODR3 GPIO_ODR_ODR3_Msk /*!< Port output data, bit 3 */
+#define GPIO_ODR_ODR4_Pos (4U)
+#define GPIO_ODR_ODR4_Msk (0x1U << GPIO_ODR_ODR4_Pos) /*!< 0x00000010 */
+#define GPIO_ODR_ODR4 GPIO_ODR_ODR4_Msk /*!< Port output data, bit 4 */
+#define GPIO_ODR_ODR5_Pos (5U)
+#define GPIO_ODR_ODR5_Msk (0x1U << GPIO_ODR_ODR5_Pos) /*!< 0x00000020 */
+#define GPIO_ODR_ODR5 GPIO_ODR_ODR5_Msk /*!< Port output data, bit 5 */
+#define GPIO_ODR_ODR6_Pos (6U)
+#define GPIO_ODR_ODR6_Msk (0x1U << GPIO_ODR_ODR6_Pos) /*!< 0x00000040 */
+#define GPIO_ODR_ODR6 GPIO_ODR_ODR6_Msk /*!< Port output data, bit 6 */
+#define GPIO_ODR_ODR7_Pos (7U)
+#define GPIO_ODR_ODR7_Msk (0x1U << GPIO_ODR_ODR7_Pos) /*!< 0x00000080 */
+#define GPIO_ODR_ODR7 GPIO_ODR_ODR7_Msk /*!< Port output data, bit 7 */
+#define GPIO_ODR_ODR8_Pos (8U)
+#define GPIO_ODR_ODR8_Msk (0x1U << GPIO_ODR_ODR8_Pos) /*!< 0x00000100 */
+#define GPIO_ODR_ODR8 GPIO_ODR_ODR8_Msk /*!< Port output data, bit 8 */
+#define GPIO_ODR_ODR9_Pos (9U)
+#define GPIO_ODR_ODR9_Msk (0x1U << GPIO_ODR_ODR9_Pos) /*!< 0x00000200 */
+#define GPIO_ODR_ODR9 GPIO_ODR_ODR9_Msk /*!< Port output data, bit 9 */
+#define GPIO_ODR_ODR10_Pos (10U)
+#define GPIO_ODR_ODR10_Msk (0x1U << GPIO_ODR_ODR10_Pos) /*!< 0x00000400 */
+#define GPIO_ODR_ODR10 GPIO_ODR_ODR10_Msk /*!< Port output data, bit 10 */
+#define GPIO_ODR_ODR11_Pos (11U)
+#define GPIO_ODR_ODR11_Msk (0x1U << GPIO_ODR_ODR11_Pos) /*!< 0x00000800 */
+#define GPIO_ODR_ODR11 GPIO_ODR_ODR11_Msk /*!< Port output data, bit 11 */
+#define GPIO_ODR_ODR12_Pos (12U)
+#define GPIO_ODR_ODR12_Msk (0x1U << GPIO_ODR_ODR12_Pos) /*!< 0x00001000 */
+#define GPIO_ODR_ODR12 GPIO_ODR_ODR12_Msk /*!< Port output data, bit 12 */
+#define GPIO_ODR_ODR13_Pos (13U)
+#define GPIO_ODR_ODR13_Msk (0x1U << GPIO_ODR_ODR13_Pos) /*!< 0x00002000 */
+#define GPIO_ODR_ODR13 GPIO_ODR_ODR13_Msk /*!< Port output data, bit 13 */
+#define GPIO_ODR_ODR14_Pos (14U)
+#define GPIO_ODR_ODR14_Msk (0x1U << GPIO_ODR_ODR14_Pos) /*!< 0x00004000 */
+#define GPIO_ODR_ODR14 GPIO_ODR_ODR14_Msk /*!< Port output data, bit 14 */
+#define GPIO_ODR_ODR15_Pos (15U)
+#define GPIO_ODR_ODR15_Msk (0x1U << GPIO_ODR_ODR15_Pos) /*!< 0x00008000 */
+#define GPIO_ODR_ODR15 GPIO_ODR_ODR15_Msk /*!< Port output data, bit 15 */
+
+/****************** Bit definition for GPIO_BSRR register *******************/
+#define GPIO_BSRR_BS0_Pos (0U)
+#define GPIO_BSRR_BS0_Msk (0x1U << GPIO_BSRR_BS0_Pos) /*!< 0x00000001 */
+#define GPIO_BSRR_BS0 GPIO_BSRR_BS0_Msk /*!< Port x Set bit 0 */
+#define GPIO_BSRR_BS1_Pos (1U)
+#define GPIO_BSRR_BS1_Msk (0x1U << GPIO_BSRR_BS1_Pos) /*!< 0x00000002 */
+#define GPIO_BSRR_BS1 GPIO_BSRR_BS1_Msk /*!< Port x Set bit 1 */
+#define GPIO_BSRR_BS2_Pos (2U)
+#define GPIO_BSRR_BS2_Msk (0x1U << GPIO_BSRR_BS2_Pos) /*!< 0x00000004 */
+#define GPIO_BSRR_BS2 GPIO_BSRR_BS2_Msk /*!< Port x Set bit 2 */
+#define GPIO_BSRR_BS3_Pos (3U)
+#define GPIO_BSRR_BS3_Msk (0x1U << GPIO_BSRR_BS3_Pos) /*!< 0x00000008 */
+#define GPIO_BSRR_BS3 GPIO_BSRR_BS3_Msk /*!< Port x Set bit 3 */
+#define GPIO_BSRR_BS4_Pos (4U)
+#define GPIO_BSRR_BS4_Msk (0x1U << GPIO_BSRR_BS4_Pos) /*!< 0x00000010 */
+#define GPIO_BSRR_BS4 GPIO_BSRR_BS4_Msk /*!< Port x Set bit 4 */
+#define GPIO_BSRR_BS5_Pos (5U)
+#define GPIO_BSRR_BS5_Msk (0x1U << GPIO_BSRR_BS5_Pos) /*!< 0x00000020 */
+#define GPIO_BSRR_BS5 GPIO_BSRR_BS5_Msk /*!< Port x Set bit 5 */
+#define GPIO_BSRR_BS6_Pos (6U)
+#define GPIO_BSRR_BS6_Msk (0x1U << GPIO_BSRR_BS6_Pos) /*!< 0x00000040 */
+#define GPIO_BSRR_BS6 GPIO_BSRR_BS6_Msk /*!< Port x Set bit 6 */
+#define GPIO_BSRR_BS7_Pos (7U)
+#define GPIO_BSRR_BS7_Msk (0x1U << GPIO_BSRR_BS7_Pos) /*!< 0x00000080 */
+#define GPIO_BSRR_BS7 GPIO_BSRR_BS7_Msk /*!< Port x Set bit 7 */
+#define GPIO_BSRR_BS8_Pos (8U)
+#define GPIO_BSRR_BS8_Msk (0x1U << GPIO_BSRR_BS8_Pos) /*!< 0x00000100 */
+#define GPIO_BSRR_BS8 GPIO_BSRR_BS8_Msk /*!< Port x Set bit 8 */
+#define GPIO_BSRR_BS9_Pos (9U)
+#define GPIO_BSRR_BS9_Msk (0x1U << GPIO_BSRR_BS9_Pos) /*!< 0x00000200 */
+#define GPIO_BSRR_BS9 GPIO_BSRR_BS9_Msk /*!< Port x Set bit 9 */
+#define GPIO_BSRR_BS10_Pos (10U)
+#define GPIO_BSRR_BS10_Msk (0x1U << GPIO_BSRR_BS10_Pos) /*!< 0x00000400 */
+#define GPIO_BSRR_BS10 GPIO_BSRR_BS10_Msk /*!< Port x Set bit 10 */
+#define GPIO_BSRR_BS11_Pos (11U)
+#define GPIO_BSRR_BS11_Msk (0x1U << GPIO_BSRR_BS11_Pos) /*!< 0x00000800 */
+#define GPIO_BSRR_BS11 GPIO_BSRR_BS11_Msk /*!< Port x Set bit 11 */
+#define GPIO_BSRR_BS12_Pos (12U)
+#define GPIO_BSRR_BS12_Msk (0x1U << GPIO_BSRR_BS12_Pos) /*!< 0x00001000 */
+#define GPIO_BSRR_BS12 GPIO_BSRR_BS12_Msk /*!< Port x Set bit 12 */
+#define GPIO_BSRR_BS13_Pos (13U)
+#define GPIO_BSRR_BS13_Msk (0x1U << GPIO_BSRR_BS13_Pos) /*!< 0x00002000 */
+#define GPIO_BSRR_BS13 GPIO_BSRR_BS13_Msk /*!< Port x Set bit 13 */
+#define GPIO_BSRR_BS14_Pos (14U)
+#define GPIO_BSRR_BS14_Msk (0x1U << GPIO_BSRR_BS14_Pos) /*!< 0x00004000 */
+#define GPIO_BSRR_BS14 GPIO_BSRR_BS14_Msk /*!< Port x Set bit 14 */
+#define GPIO_BSRR_BS15_Pos (15U)
+#define GPIO_BSRR_BS15_Msk (0x1U << GPIO_BSRR_BS15_Pos) /*!< 0x00008000 */
+#define GPIO_BSRR_BS15 GPIO_BSRR_BS15_Msk /*!< Port x Set bit 15 */
+
+#define GPIO_BSRR_BR0_Pos (16U)
+#define GPIO_BSRR_BR0_Msk (0x1U << GPIO_BSRR_BR0_Pos) /*!< 0x00010000 */
+#define GPIO_BSRR_BR0 GPIO_BSRR_BR0_Msk /*!< Port x Reset bit 0 */
+#define GPIO_BSRR_BR1_Pos (17U)
+#define GPIO_BSRR_BR1_Msk (0x1U << GPIO_BSRR_BR1_Pos) /*!< 0x00020000 */
+#define GPIO_BSRR_BR1 GPIO_BSRR_BR1_Msk /*!< Port x Reset bit 1 */
+#define GPIO_BSRR_BR2_Pos (18U)
+#define GPIO_BSRR_BR2_Msk (0x1U << GPIO_BSRR_BR2_Pos) /*!< 0x00040000 */
+#define GPIO_BSRR_BR2 GPIO_BSRR_BR2_Msk /*!< Port x Reset bit 2 */
+#define GPIO_BSRR_BR3_Pos (19U)
+#define GPIO_BSRR_BR3_Msk (0x1U << GPIO_BSRR_BR3_Pos) /*!< 0x00080000 */
+#define GPIO_BSRR_BR3 GPIO_BSRR_BR3_Msk /*!< Port x Reset bit 3 */
+#define GPIO_BSRR_BR4_Pos (20U)
+#define GPIO_BSRR_BR4_Msk (0x1U << GPIO_BSRR_BR4_Pos) /*!< 0x00100000 */
+#define GPIO_BSRR_BR4 GPIO_BSRR_BR4_Msk /*!< Port x Reset bit 4 */
+#define GPIO_BSRR_BR5_Pos (21U)
+#define GPIO_BSRR_BR5_Msk (0x1U << GPIO_BSRR_BR5_Pos) /*!< 0x00200000 */
+#define GPIO_BSRR_BR5 GPIO_BSRR_BR5_Msk /*!< Port x Reset bit 5 */
+#define GPIO_BSRR_BR6_Pos (22U)
+#define GPIO_BSRR_BR6_Msk (0x1U << GPIO_BSRR_BR6_Pos) /*!< 0x00400000 */
+#define GPIO_BSRR_BR6 GPIO_BSRR_BR6_Msk /*!< Port x Reset bit 6 */
+#define GPIO_BSRR_BR7_Pos (23U)
+#define GPIO_BSRR_BR7_Msk (0x1U << GPIO_BSRR_BR7_Pos) /*!< 0x00800000 */
+#define GPIO_BSRR_BR7 GPIO_BSRR_BR7_Msk /*!< Port x Reset bit 7 */
+#define GPIO_BSRR_BR8_Pos (24U)
+#define GPIO_BSRR_BR8_Msk (0x1U << GPIO_BSRR_BR8_Pos) /*!< 0x01000000 */
+#define GPIO_BSRR_BR8 GPIO_BSRR_BR8_Msk /*!< Port x Reset bit 8 */
+#define GPIO_BSRR_BR9_Pos (25U)
+#define GPIO_BSRR_BR9_Msk (0x1U << GPIO_BSRR_BR9_Pos) /*!< 0x02000000 */
+#define GPIO_BSRR_BR9 GPIO_BSRR_BR9_Msk /*!< Port x Reset bit 9 */
+#define GPIO_BSRR_BR10_Pos (26U)
+#define GPIO_BSRR_BR10_Msk (0x1U << GPIO_BSRR_BR10_Pos) /*!< 0x04000000 */
+#define GPIO_BSRR_BR10 GPIO_BSRR_BR10_Msk /*!< Port x Reset bit 10 */
+#define GPIO_BSRR_BR11_Pos (27U)
+#define GPIO_BSRR_BR11_Msk (0x1U << GPIO_BSRR_BR11_Pos) /*!< 0x08000000 */
+#define GPIO_BSRR_BR11 GPIO_BSRR_BR11_Msk /*!< Port x Reset bit 11 */
+#define GPIO_BSRR_BR12_Pos (28U)
+#define GPIO_BSRR_BR12_Msk (0x1U << GPIO_BSRR_BR12_Pos) /*!< 0x10000000 */
+#define GPIO_BSRR_BR12 GPIO_BSRR_BR12_Msk /*!< Port x Reset bit 12 */
+#define GPIO_BSRR_BR13_Pos (29U)
+#define GPIO_BSRR_BR13_Msk (0x1U << GPIO_BSRR_BR13_Pos) /*!< 0x20000000 */
+#define GPIO_BSRR_BR13 GPIO_BSRR_BR13_Msk /*!< Port x Reset bit 13 */
+#define GPIO_BSRR_BR14_Pos (30U)
+#define GPIO_BSRR_BR14_Msk (0x1U << GPIO_BSRR_BR14_Pos) /*!< 0x40000000 */
+#define GPIO_BSRR_BR14 GPIO_BSRR_BR14_Msk /*!< Port x Reset bit 14 */
+#define GPIO_BSRR_BR15_Pos (31U)
+#define GPIO_BSRR_BR15_Msk (0x1U << GPIO_BSRR_BR15_Pos) /*!< 0x80000000 */
+#define GPIO_BSRR_BR15 GPIO_BSRR_BR15_Msk /*!< Port x Reset bit 15 */
+
+/******************* Bit definition for GPIO_BRR register *******************/
+#define GPIO_BRR_BR0_Pos (0U)
+#define GPIO_BRR_BR0_Msk (0x1U << GPIO_BRR_BR0_Pos) /*!< 0x00000001 */
+#define GPIO_BRR_BR0 GPIO_BRR_BR0_Msk /*!< Port x Reset bit 0 */
+#define GPIO_BRR_BR1_Pos (1U)
+#define GPIO_BRR_BR1_Msk (0x1U << GPIO_BRR_BR1_Pos) /*!< 0x00000002 */
+#define GPIO_BRR_BR1 GPIO_BRR_BR1_Msk /*!< Port x Reset bit 1 */
+#define GPIO_BRR_BR2_Pos (2U)
+#define GPIO_BRR_BR2_Msk (0x1U << GPIO_BRR_BR2_Pos) /*!< 0x00000004 */
+#define GPIO_BRR_BR2 GPIO_BRR_BR2_Msk /*!< Port x Reset bit 2 */
+#define GPIO_BRR_BR3_Pos (3U)
+#define GPIO_BRR_BR3_Msk (0x1U << GPIO_BRR_BR3_Pos) /*!< 0x00000008 */
+#define GPIO_BRR_BR3 GPIO_BRR_BR3_Msk /*!< Port x Reset bit 3 */
+#define GPIO_BRR_BR4_Pos (4U)
+#define GPIO_BRR_BR4_Msk (0x1U << GPIO_BRR_BR4_Pos) /*!< 0x00000010 */
+#define GPIO_BRR_BR4 GPIO_BRR_BR4_Msk /*!< Port x Reset bit 4 */
+#define GPIO_BRR_BR5_Pos (5U)
+#define GPIO_BRR_BR5_Msk (0x1U << GPIO_BRR_BR5_Pos) /*!< 0x00000020 */
+#define GPIO_BRR_BR5 GPIO_BRR_BR5_Msk /*!< Port x Reset bit 5 */
+#define GPIO_BRR_BR6_Pos (6U)
+#define GPIO_BRR_BR6_Msk (0x1U << GPIO_BRR_BR6_Pos) /*!< 0x00000040 */
+#define GPIO_BRR_BR6 GPIO_BRR_BR6_Msk /*!< Port x Reset bit 6 */
+#define GPIO_BRR_BR7_Pos (7U)
+#define GPIO_BRR_BR7_Msk (0x1U << GPIO_BRR_BR7_Pos) /*!< 0x00000080 */
+#define GPIO_BRR_BR7 GPIO_BRR_BR7_Msk /*!< Port x Reset bit 7 */
+#define GPIO_BRR_BR8_Pos (8U)
+#define GPIO_BRR_BR8_Msk (0x1U << GPIO_BRR_BR8_Pos) /*!< 0x00000100 */
+#define GPIO_BRR_BR8 GPIO_BRR_BR8_Msk /*!< Port x Reset bit 8 */
+#define GPIO_BRR_BR9_Pos (9U)
+#define GPIO_BRR_BR9_Msk (0x1U << GPIO_BRR_BR9_Pos) /*!< 0x00000200 */
+#define GPIO_BRR_BR9 GPIO_BRR_BR9_Msk /*!< Port x Reset bit 9 */
+#define GPIO_BRR_BR10_Pos (10U)
+#define GPIO_BRR_BR10_Msk (0x1U << GPIO_BRR_BR10_Pos) /*!< 0x00000400 */
+#define GPIO_BRR_BR10 GPIO_BRR_BR10_Msk /*!< Port x Reset bit 10 */
+#define GPIO_BRR_BR11_Pos (11U)
+#define GPIO_BRR_BR11_Msk (0x1U << GPIO_BRR_BR11_Pos) /*!< 0x00000800 */
+#define GPIO_BRR_BR11 GPIO_BRR_BR11_Msk /*!< Port x Reset bit 11 */
+#define GPIO_BRR_BR12_Pos (12U)
+#define GPIO_BRR_BR12_Msk (0x1U << GPIO_BRR_BR12_Pos) /*!< 0x00001000 */
+#define GPIO_BRR_BR12 GPIO_BRR_BR12_Msk /*!< Port x Reset bit 12 */
+#define GPIO_BRR_BR13_Pos (13U)
+#define GPIO_BRR_BR13_Msk (0x1U << GPIO_BRR_BR13_Pos) /*!< 0x00002000 */
+#define GPIO_BRR_BR13 GPIO_BRR_BR13_Msk /*!< Port x Reset bit 13 */
+#define GPIO_BRR_BR14_Pos (14U)
+#define GPIO_BRR_BR14_Msk (0x1U << GPIO_BRR_BR14_Pos) /*!< 0x00004000 */
+#define GPIO_BRR_BR14 GPIO_BRR_BR14_Msk /*!< Port x Reset bit 14 */
+#define GPIO_BRR_BR15_Pos (15U)
+#define GPIO_BRR_BR15_Msk (0x1U << GPIO_BRR_BR15_Pos) /*!< 0x00008000 */
+#define GPIO_BRR_BR15 GPIO_BRR_BR15_Msk /*!< Port x Reset bit 15 */
+
+/****************** Bit definition for GPIO_LCKR register *******************/
+#define GPIO_LCKR_LCK0_Pos (0U)
+#define GPIO_LCKR_LCK0_Msk (0x1U << GPIO_LCKR_LCK0_Pos) /*!< 0x00000001 */
+#define GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk /*!< Port x Lock bit 0 */
+#define GPIO_LCKR_LCK1_Pos (1U)
+#define GPIO_LCKR_LCK1_Msk (0x1U << GPIO_LCKR_LCK1_Pos) /*!< 0x00000002 */
+#define GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk /*!< Port x Lock bit 1 */
+#define GPIO_LCKR_LCK2_Pos (2U)
+#define GPIO_LCKR_LCK2_Msk (0x1U << GPIO_LCKR_LCK2_Pos) /*!< 0x00000004 */
+#define GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk /*!< Port x Lock bit 2 */
+#define GPIO_LCKR_LCK3_Pos (3U)
+#define GPIO_LCKR_LCK3_Msk (0x1U << GPIO_LCKR_LCK3_Pos) /*!< 0x00000008 */
+#define GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk /*!< Port x Lock bit 3 */
+#define GPIO_LCKR_LCK4_Pos (4U)
+#define GPIO_LCKR_LCK4_Msk (0x1U << GPIO_LCKR_LCK4_Pos) /*!< 0x00000010 */
+#define GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk /*!< Port x Lock bit 4 */
+#define GPIO_LCKR_LCK5_Pos (5U)
+#define GPIO_LCKR_LCK5_Msk (0x1U << GPIO_LCKR_LCK5_Pos) /*!< 0x00000020 */
+#define GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk /*!< Port x Lock bit 5 */
+#define GPIO_LCKR_LCK6_Pos (6U)
+#define GPIO_LCKR_LCK6_Msk (0x1U << GPIO_LCKR_LCK6_Pos) /*!< 0x00000040 */
+#define GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk /*!< Port x Lock bit 6 */
+#define GPIO_LCKR_LCK7_Pos (7U)
+#define GPIO_LCKR_LCK7_Msk (0x1U << GPIO_LCKR_LCK7_Pos) /*!< 0x00000080 */
+#define GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk /*!< Port x Lock bit 7 */
+#define GPIO_LCKR_LCK8_Pos (8U)
+#define GPIO_LCKR_LCK8_Msk (0x1U << GPIO_LCKR_LCK8_Pos) /*!< 0x00000100 */
+#define GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk /*!< Port x Lock bit 8 */
+#define GPIO_LCKR_LCK9_Pos (9U)
+#define GPIO_LCKR_LCK9_Msk (0x1U << GPIO_LCKR_LCK9_Pos) /*!< 0x00000200 */
+#define GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk /*!< Port x Lock bit 9 */
+#define GPIO_LCKR_LCK10_Pos (10U)
+#define GPIO_LCKR_LCK10_Msk (0x1U << GPIO_LCKR_LCK10_Pos) /*!< 0x00000400 */
+#define GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk /*!< Port x Lock bit 10 */
+#define GPIO_LCKR_LCK11_Pos (11U)
+#define GPIO_LCKR_LCK11_Msk (0x1U << GPIO_LCKR_LCK11_Pos) /*!< 0x00000800 */
+#define GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk /*!< Port x Lock bit 11 */
+#define GPIO_LCKR_LCK12_Pos (12U)
+#define GPIO_LCKR_LCK12_Msk (0x1U << GPIO_LCKR_LCK12_Pos) /*!< 0x00001000 */
+#define GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk /*!< Port x Lock bit 12 */
+#define GPIO_LCKR_LCK13_Pos (13U)
+#define GPIO_LCKR_LCK13_Msk (0x1U << GPIO_LCKR_LCK13_Pos) /*!< 0x00002000 */
+#define GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk /*!< Port x Lock bit 13 */
+#define GPIO_LCKR_LCK14_Pos (14U)
+#define GPIO_LCKR_LCK14_Msk (0x1U << GPIO_LCKR_LCK14_Pos) /*!< 0x00004000 */
+#define GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk /*!< Port x Lock bit 14 */
+#define GPIO_LCKR_LCK15_Pos (15U)
+#define GPIO_LCKR_LCK15_Msk (0x1U << GPIO_LCKR_LCK15_Pos) /*!< 0x00008000 */
+#define GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk /*!< Port x Lock bit 15 */
+#define GPIO_LCKR_LCKK_Pos (16U)
+#define GPIO_LCKR_LCKK_Msk (0x1U << GPIO_LCKR_LCKK_Pos) /*!< 0x00010000 */
+#define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk /*!< Lock key */
+
+/*----------------------------------------------------------------------------*/
+
+/****************** Bit definition for AFIO_EVCR register *******************/
+#define AFIO_EVCR_PIN_Pos (0U)
+#define AFIO_EVCR_PIN_Msk (0xFU << AFIO_EVCR_PIN_Pos) /*!< 0x0000000F */
+#define AFIO_EVCR_PIN AFIO_EVCR_PIN_Msk /*!< PIN[3:0] bits (Pin selection) */
+#define AFIO_EVCR_PIN_0 (0x1U << AFIO_EVCR_PIN_Pos) /*!< 0x00000001 */
+#define AFIO_EVCR_PIN_1 (0x2U << AFIO_EVCR_PIN_Pos) /*!< 0x00000002 */
+#define AFIO_EVCR_PIN_2 (0x4U << AFIO_EVCR_PIN_Pos) /*!< 0x00000004 */
+#define AFIO_EVCR_PIN_3 (0x8U << AFIO_EVCR_PIN_Pos) /*!< 0x00000008 */
+
+/*!< PIN configuration */
+#define AFIO_EVCR_PIN_PX0 ((uint32_t)0x00000000) /*!< Pin 0 selected */
+#define AFIO_EVCR_PIN_PX1_Pos (0U)
+#define AFIO_EVCR_PIN_PX1_Msk (0x1U << AFIO_EVCR_PIN_PX1_Pos) /*!< 0x00000001 */
+#define AFIO_EVCR_PIN_PX1 AFIO_EVCR_PIN_PX1_Msk /*!< Pin 1 selected */
+#define AFIO_EVCR_PIN_PX2_Pos (1U)
+#define AFIO_EVCR_PIN_PX2_Msk (0x1U << AFIO_EVCR_PIN_PX2_Pos) /*!< 0x00000002 */
+#define AFIO_EVCR_PIN_PX2 AFIO_EVCR_PIN_PX2_Msk /*!< Pin 2 selected */
+#define AFIO_EVCR_PIN_PX3_Pos (0U)
+#define AFIO_EVCR_PIN_PX3_Msk (0x3U << AFIO_EVCR_PIN_PX3_Pos) /*!< 0x00000003 */
+#define AFIO_EVCR_PIN_PX3 AFIO_EVCR_PIN_PX3_Msk /*!< Pin 3 selected */
+#define AFIO_EVCR_PIN_PX4_Pos (2U)
+#define AFIO_EVCR_PIN_PX4_Msk (0x1U << AFIO_EVCR_PIN_PX4_Pos) /*!< 0x00000004 */
+#define AFIO_EVCR_PIN_PX4 AFIO_EVCR_PIN_PX4_Msk /*!< Pin 4 selected */
+#define AFIO_EVCR_PIN_PX5_Pos (0U)
+#define AFIO_EVCR_PIN_PX5_Msk (0x5U << AFIO_EVCR_PIN_PX5_Pos) /*!< 0x00000005 */
+#define AFIO_EVCR_PIN_PX5 AFIO_EVCR_PIN_PX5_Msk /*!< Pin 5 selected */
+#define AFIO_EVCR_PIN_PX6_Pos (1U)
+#define AFIO_EVCR_PIN_PX6_Msk (0x3U << AFIO_EVCR_PIN_PX6_Pos) /*!< 0x00000006 */
+#define AFIO_EVCR_PIN_PX6 AFIO_EVCR_PIN_PX6_Msk /*!< Pin 6 selected */
+#define AFIO_EVCR_PIN_PX7_Pos (0U)
+#define AFIO_EVCR_PIN_PX7_Msk (0x7U << AFIO_EVCR_PIN_PX7_Pos) /*!< 0x00000007 */
+#define AFIO_EVCR_PIN_PX7 AFIO_EVCR_PIN_PX7_Msk /*!< Pin 7 selected */
+#define AFIO_EVCR_PIN_PX8_Pos (3U)
+#define AFIO_EVCR_PIN_PX8_Msk (0x1U << AFIO_EVCR_PIN_PX8_Pos) /*!< 0x00000008 */
+#define AFIO_EVCR_PIN_PX8 AFIO_EVCR_PIN_PX8_Msk /*!< Pin 8 selected */
+#define AFIO_EVCR_PIN_PX9_Pos (0U)
+#define AFIO_EVCR_PIN_PX9_Msk (0x9U << AFIO_EVCR_PIN_PX9_Pos) /*!< 0x00000009 */
+#define AFIO_EVCR_PIN_PX9 AFIO_EVCR_PIN_PX9_Msk /*!< Pin 9 selected */
+#define AFIO_EVCR_PIN_PX10_Pos (1U)
+#define AFIO_EVCR_PIN_PX10_Msk (0x5U << AFIO_EVCR_PIN_PX10_Pos) /*!< 0x0000000A */
+#define AFIO_EVCR_PIN_PX10 AFIO_EVCR_PIN_PX10_Msk /*!< Pin 10 selected */
+#define AFIO_EVCR_PIN_PX11_Pos (0U)
+#define AFIO_EVCR_PIN_PX11_Msk (0xBU << AFIO_EVCR_PIN_PX11_Pos) /*!< 0x0000000B */
+#define AFIO_EVCR_PIN_PX11 AFIO_EVCR_PIN_PX11_Msk /*!< Pin 11 selected */
+#define AFIO_EVCR_PIN_PX12_Pos (2U)
+#define AFIO_EVCR_PIN_PX12_Msk (0x3U << AFIO_EVCR_PIN_PX12_Pos) /*!< 0x0000000C */
+#define AFIO_EVCR_PIN_PX12 AFIO_EVCR_PIN_PX12_Msk /*!< Pin 12 selected */
+#define AFIO_EVCR_PIN_PX13_Pos (0U)
+#define AFIO_EVCR_PIN_PX13_Msk (0xDU << AFIO_EVCR_PIN_PX13_Pos) /*!< 0x0000000D */
+#define AFIO_EVCR_PIN_PX13 AFIO_EVCR_PIN_PX13_Msk /*!< Pin 13 selected */
+#define AFIO_EVCR_PIN_PX14_Pos (1U)
+#define AFIO_EVCR_PIN_PX14_Msk (0x7U << AFIO_EVCR_PIN_PX14_Pos) /*!< 0x0000000E */
+#define AFIO_EVCR_PIN_PX14 AFIO_EVCR_PIN_PX14_Msk /*!< Pin 14 selected */
+#define AFIO_EVCR_PIN_PX15_Pos (0U)
+#define AFIO_EVCR_PIN_PX15_Msk (0xFU << AFIO_EVCR_PIN_PX15_Pos) /*!< 0x0000000F */
+#define AFIO_EVCR_PIN_PX15 AFIO_EVCR_PIN_PX15_Msk /*!< Pin 15 selected */
+
+#define AFIO_EVCR_PORT_Pos (4U)
+#define AFIO_EVCR_PORT_Msk (0x7U << AFIO_EVCR_PORT_Pos) /*!< 0x00000070 */
+#define AFIO_EVCR_PORT AFIO_EVCR_PORT_Msk /*!< PORT[2:0] bits (Port selection) */
+#define AFIO_EVCR_PORT_0 (0x1U << AFIO_EVCR_PORT_Pos) /*!< 0x00000010 */
+#define AFIO_EVCR_PORT_1 (0x2U << AFIO_EVCR_PORT_Pos) /*!< 0x00000020 */
+#define AFIO_EVCR_PORT_2 (0x4U << AFIO_EVCR_PORT_Pos) /*!< 0x00000040 */
+
+/*!< PORT configuration */
+#define AFIO_EVCR_PORT_PA ((uint32_t)0x00000000) /*!< Port A selected */
+#define AFIO_EVCR_PORT_PB_Pos (4U)
+#define AFIO_EVCR_PORT_PB_Msk (0x1U << AFIO_EVCR_PORT_PB_Pos) /*!< 0x00000010 */
+#define AFIO_EVCR_PORT_PB AFIO_EVCR_PORT_PB_Msk /*!< Port B selected */
+#define AFIO_EVCR_PORT_PC_Pos (5U)
+#define AFIO_EVCR_PORT_PC_Msk (0x1U << AFIO_EVCR_PORT_PC_Pos) /*!< 0x00000020 */
+#define AFIO_EVCR_PORT_PC AFIO_EVCR_PORT_PC_Msk /*!< Port C selected */
+#define AFIO_EVCR_PORT_PD_Pos (4U)
+#define AFIO_EVCR_PORT_PD_Msk (0x3U << AFIO_EVCR_PORT_PD_Pos) /*!< 0x00000030 */
+#define AFIO_EVCR_PORT_PD AFIO_EVCR_PORT_PD_Msk /*!< Port D selected */
+#define AFIO_EVCR_PORT_PE_Pos (6U)
+#define AFIO_EVCR_PORT_PE_Msk (0x1U << AFIO_EVCR_PORT_PE_Pos) /*!< 0x00000040 */
+#define AFIO_EVCR_PORT_PE AFIO_EVCR_PORT_PE_Msk /*!< Port E selected */
+
+#define AFIO_EVCR_EVOE_Pos (7U)
+#define AFIO_EVCR_EVOE_Msk (0x1U << AFIO_EVCR_EVOE_Pos) /*!< 0x00000080 */
+#define AFIO_EVCR_EVOE AFIO_EVCR_EVOE_Msk /*!< Event Output Enable */
+
+/****************** Bit definition for AFIO_MAPR register *******************/
+#define AFIO_MAPR_SPI1_REMAP_Pos (0U)
+#define AFIO_MAPR_SPI1_REMAP_Msk (0x1U << AFIO_MAPR_SPI1_REMAP_Pos) /*!< 0x00000001 */
+#define AFIO_MAPR_SPI1_REMAP AFIO_MAPR_SPI1_REMAP_Msk /*!< SPI1 remapping */
+#define AFIO_MAPR_I2C1_REMAP_Pos (1U)
+#define AFIO_MAPR_I2C1_REMAP_Msk (0x1U << AFIO_MAPR_I2C1_REMAP_Pos) /*!< 0x00000002 */
+#define AFIO_MAPR_I2C1_REMAP AFIO_MAPR_I2C1_REMAP_Msk /*!< I2C1 remapping */
+#define AFIO_MAPR_USART1_REMAP_Pos (2U)
+#define AFIO_MAPR_USART1_REMAP_Msk (0x1U << AFIO_MAPR_USART1_REMAP_Pos) /*!< 0x00000004 */
+#define AFIO_MAPR_USART1_REMAP AFIO_MAPR_USART1_REMAP_Msk /*!< USART1 remapping */
+#define AFIO_MAPR_USART2_REMAP_Pos (3U)
+#define AFIO_MAPR_USART2_REMAP_Msk (0x1U << AFIO_MAPR_USART2_REMAP_Pos) /*!< 0x00000008 */
+#define AFIO_MAPR_USART2_REMAP AFIO_MAPR_USART2_REMAP_Msk /*!< USART2 remapping */
+
+
+#define AFIO_MAPR_TIM1_REMAP_Pos (6U)
+#define AFIO_MAPR_TIM1_REMAP_Msk (0x3U << AFIO_MAPR_TIM1_REMAP_Pos) /*!< 0x000000C0 */
+#define AFIO_MAPR_TIM1_REMAP AFIO_MAPR_TIM1_REMAP_Msk /*!< TIM1_REMAP[1:0] bits (TIM1 remapping) */
+#define AFIO_MAPR_TIM1_REMAP_0 (0x1U << AFIO_MAPR_TIM1_REMAP_Pos) /*!< 0x00000040 */
+#define AFIO_MAPR_TIM1_REMAP_1 (0x2U << AFIO_MAPR_TIM1_REMAP_Pos) /*!< 0x00000080 */
+
+/*!< TIM1_REMAP configuration */
+#define AFIO_MAPR_TIM1_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15) */
+#define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Pos (6U)
+#define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Msk (0x1U << AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Pos) /*!< 0x00000040 */
+#define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Msk /*!< Partial remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PA6, CH1N/PA7, CH2N/PB0, CH3N/PB1) */
+#define AFIO_MAPR_TIM1_REMAP_FULLREMAP_Pos (6U)
+#define AFIO_MAPR_TIM1_REMAP_FULLREMAP_Msk (0x3U << AFIO_MAPR_TIM1_REMAP_FULLREMAP_Pos) /*!< 0x000000C0 */
+#define AFIO_MAPR_TIM1_REMAP_FULLREMAP AFIO_MAPR_TIM1_REMAP_FULLREMAP_Msk /*!< Full remap (ETR/PE7, CH1/PE9, CH2/PE11, CH3/PE13, CH4/PE14, BKIN/PE15, CH1N/PE8, CH2N/PE10, CH3N/PE12) */
+
+#define AFIO_MAPR_TIM2_REMAP_Pos (8U)
+#define AFIO_MAPR_TIM2_REMAP_Msk (0x3U << AFIO_MAPR_TIM2_REMAP_Pos) /*!< 0x00000300 */
+#define AFIO_MAPR_TIM2_REMAP AFIO_MAPR_TIM2_REMAP_Msk /*!< TIM2_REMAP[1:0] bits (TIM2 remapping) */
+#define AFIO_MAPR_TIM2_REMAP_0 (0x1U << AFIO_MAPR_TIM2_REMAP_Pos) /*!< 0x00000100 */
+#define AFIO_MAPR_TIM2_REMAP_1 (0x2U << AFIO_MAPR_TIM2_REMAP_Pos) /*!< 0x00000200 */
+
+/*!< TIM2_REMAP configuration */
+#define AFIO_MAPR_TIM2_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3) */
+#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Pos (8U)
+#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Msk (0x1U << AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Pos) /*!< 0x00000100 */
+#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1 AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Msk /*!< Partial remap (CH1/ETR/PA15, CH2/PB3, CH3/PA2, CH4/PA3) */
+#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2_Pos (9U)
+#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2_Msk (0x1U << AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2_Pos) /*!< 0x00000200 */
+#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2 AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2_Msk /*!< Partial remap (CH1/ETR/PA0, CH2/PA1, CH3/PB10, CH4/PB11) */
+#define AFIO_MAPR_TIM2_REMAP_FULLREMAP_Pos (8U)
+#define AFIO_MAPR_TIM2_REMAP_FULLREMAP_Msk (0x3U << AFIO_MAPR_TIM2_REMAP_FULLREMAP_Pos) /*!< 0x00000300 */
+#define AFIO_MAPR_TIM2_REMAP_FULLREMAP AFIO_MAPR_TIM2_REMAP_FULLREMAP_Msk /*!< Full remap (CH1/ETR/PA15, CH2/PB3, CH3/PB10, CH4/PB11) */
+
+#define AFIO_MAPR_TIM3_REMAP_Pos (10U)
+#define AFIO_MAPR_TIM3_REMAP_Msk (0x3U << AFIO_MAPR_TIM3_REMAP_Pos) /*!< 0x00000C00 */
+#define AFIO_MAPR_TIM3_REMAP AFIO_MAPR_TIM3_REMAP_Msk /*!< TIM3_REMAP[1:0] bits (TIM3 remapping) */
+#define AFIO_MAPR_TIM3_REMAP_0 (0x1U << AFIO_MAPR_TIM3_REMAP_Pos) /*!< 0x00000400 */
+#define AFIO_MAPR_TIM3_REMAP_1 (0x2U << AFIO_MAPR_TIM3_REMAP_Pos) /*!< 0x00000800 */
+
+/*!< TIM3_REMAP configuration */
+#define AFIO_MAPR_TIM3_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1) */
+#define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Pos (11U)
+#define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Msk (0x1U << AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Pos) /*!< 0x00000800 */
+#define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Msk /*!< Partial remap (CH1/PB4, CH2/PB5, CH3/PB0, CH4/PB1) */
+#define AFIO_MAPR_TIM3_REMAP_FULLREMAP_Pos (10U)
+#define AFIO_MAPR_TIM3_REMAP_FULLREMAP_Msk (0x3U << AFIO_MAPR_TIM3_REMAP_FULLREMAP_Pos) /*!< 0x00000C00 */
+#define AFIO_MAPR_TIM3_REMAP_FULLREMAP AFIO_MAPR_TIM3_REMAP_FULLREMAP_Msk /*!< Full remap (CH1/PC6, CH2/PC7, CH3/PC8, CH4/PC9) */
+
+
+
+#define AFIO_MAPR_PD01_REMAP_Pos (15U)
+#define AFIO_MAPR_PD01_REMAP_Msk (0x1U << AFIO_MAPR_PD01_REMAP_Pos) /*!< 0x00008000 */
+#define AFIO_MAPR_PD01_REMAP AFIO_MAPR_PD01_REMAP_Msk /*!< Port D0/Port D1 mapping on OSC_IN/OSC_OUT */
+
+/*!< SWJ_CFG configuration */
+#define AFIO_MAPR_SWJ_CFG_Pos (24U)
+#define AFIO_MAPR_SWJ_CFG_Msk (0x7U << AFIO_MAPR_SWJ_CFG_Pos) /*!< 0x07000000 */
+#define AFIO_MAPR_SWJ_CFG AFIO_MAPR_SWJ_CFG_Msk /*!< SWJ_CFG[2:0] bits (Serial Wire JTAG configuration) */
+#define AFIO_MAPR_SWJ_CFG_0 (0x1U << AFIO_MAPR_SWJ_CFG_Pos) /*!< 0x01000000 */
+#define AFIO_MAPR_SWJ_CFG_1 (0x2U << AFIO_MAPR_SWJ_CFG_Pos) /*!< 0x02000000 */
+#define AFIO_MAPR_SWJ_CFG_2 (0x4U << AFIO_MAPR_SWJ_CFG_Pos) /*!< 0x04000000 */
+
+#define AFIO_MAPR_SWJ_CFG_RESET ((uint32_t)0x00000000) /*!< Full SWJ (JTAG-DP + SW-DP) : Reset State */
+#define AFIO_MAPR_SWJ_CFG_NOJNTRST_Pos (24U)
+#define AFIO_MAPR_SWJ_CFG_NOJNTRST_Msk (0x1U << AFIO_MAPR_SWJ_CFG_NOJNTRST_Pos) /*!< 0x01000000 */
+#define AFIO_MAPR_SWJ_CFG_NOJNTRST AFIO_MAPR_SWJ_CFG_NOJNTRST_Msk /*!< Full SWJ (JTAG-DP + SW-DP) but without JNTRST */
+#define AFIO_MAPR_SWJ_CFG_JTAGDISABLE_Pos (25U)
+#define AFIO_MAPR_SWJ_CFG_JTAGDISABLE_Msk (0x1U << AFIO_MAPR_SWJ_CFG_JTAGDISABLE_Pos) /*!< 0x02000000 */
+#define AFIO_MAPR_SWJ_CFG_JTAGDISABLE AFIO_MAPR_SWJ_CFG_JTAGDISABLE_Msk /*!< JTAG-DP Disabled and SW-DP Enabled */
+#define AFIO_MAPR_SWJ_CFG_DISABLE_Pos (26U)
+#define AFIO_MAPR_SWJ_CFG_DISABLE_Msk (0x1U << AFIO_MAPR_SWJ_CFG_DISABLE_Pos) /*!< 0x04000000 */
+#define AFIO_MAPR_SWJ_CFG_DISABLE AFIO_MAPR_SWJ_CFG_DISABLE_Msk /*!< JTAG-DP Disabled and SW-DP Disabled */
+
+
+/***************** Bit definition for AFIO_EXTICR1 register *****************/
+#define AFIO_EXTICR1_EXTI0_Pos (0U)
+#define AFIO_EXTICR1_EXTI0_Msk (0xFU << AFIO_EXTICR1_EXTI0_Pos) /*!< 0x0000000F */
+#define AFIO_EXTICR1_EXTI0 AFIO_EXTICR1_EXTI0_Msk /*!< EXTI 0 configuration */
+#define AFIO_EXTICR1_EXTI1_Pos (4U)
+#define AFIO_EXTICR1_EXTI1_Msk (0xFU << AFIO_EXTICR1_EXTI1_Pos) /*!< 0x000000F0 */
+#define AFIO_EXTICR1_EXTI1 AFIO_EXTICR1_EXTI1_Msk /*!< EXTI 1 configuration */
+#define AFIO_EXTICR1_EXTI2_Pos (8U)
+#define AFIO_EXTICR1_EXTI2_Msk (0xFU << AFIO_EXTICR1_EXTI2_Pos) /*!< 0x00000F00 */
+#define AFIO_EXTICR1_EXTI2 AFIO_EXTICR1_EXTI2_Msk /*!< EXTI 2 configuration */
+#define AFIO_EXTICR1_EXTI3_Pos (12U)
+#define AFIO_EXTICR1_EXTI3_Msk (0xFU << AFIO_EXTICR1_EXTI3_Pos) /*!< 0x0000F000 */
+#define AFIO_EXTICR1_EXTI3 AFIO_EXTICR1_EXTI3_Msk /*!< EXTI 3 configuration */
+
+/*!< EXTI0 configuration */
+#define AFIO_EXTICR1_EXTI0_PA ((uint32_t)0x00000000) /*!< PA[0] pin */
+#define AFIO_EXTICR1_EXTI0_PB_Pos (0U)
+#define AFIO_EXTICR1_EXTI0_PB_Msk (0x1U << AFIO_EXTICR1_EXTI0_PB_Pos) /*!< 0x00000001 */
+#define AFIO_EXTICR1_EXTI0_PB AFIO_EXTICR1_EXTI0_PB_Msk /*!< PB[0] pin */
+#define AFIO_EXTICR1_EXTI0_PC_Pos (1U)
+#define AFIO_EXTICR1_EXTI0_PC_Msk (0x1U << AFIO_EXTICR1_EXTI0_PC_Pos) /*!< 0x00000002 */
+#define AFIO_EXTICR1_EXTI0_PC AFIO_EXTICR1_EXTI0_PC_Msk /*!< PC[0] pin */
+#define AFIO_EXTICR1_EXTI0_PD_Pos (0U)
+#define AFIO_EXTICR1_EXTI0_PD_Msk (0x3U << AFIO_EXTICR1_EXTI0_PD_Pos) /*!< 0x00000003 */
+#define AFIO_EXTICR1_EXTI0_PD AFIO_EXTICR1_EXTI0_PD_Msk /*!< PD[0] pin */
+#define AFIO_EXTICR1_EXTI0_PE_Pos (2U)
+#define AFIO_EXTICR1_EXTI0_PE_Msk (0x1U << AFIO_EXTICR1_EXTI0_PE_Pos) /*!< 0x00000004 */
+#define AFIO_EXTICR1_EXTI0_PE AFIO_EXTICR1_EXTI0_PE_Msk /*!< PE[0] pin */
+#define AFIO_EXTICR1_EXTI0_PF_Pos (0U)
+#define AFIO_EXTICR1_EXTI0_PF_Msk (0x5U << AFIO_EXTICR1_EXTI0_PF_Pos) /*!< 0x00000005 */
+#define AFIO_EXTICR1_EXTI0_PF AFIO_EXTICR1_EXTI0_PF_Msk /*!< PF[0] pin */
+#define AFIO_EXTICR1_EXTI0_PG_Pos (1U)
+#define AFIO_EXTICR1_EXTI0_PG_Msk (0x3U << AFIO_EXTICR1_EXTI0_PG_Pos) /*!< 0x00000006 */
+#define AFIO_EXTICR1_EXTI0_PG AFIO_EXTICR1_EXTI0_PG_Msk /*!< PG[0] pin */
+
+/*!< EXTI1 configuration */
+#define AFIO_EXTICR1_EXTI1_PA ((uint32_t)0x00000000) /*!< PA[1] pin */
+#define AFIO_EXTICR1_EXTI1_PB_Pos (4U)
+#define AFIO_EXTICR1_EXTI1_PB_Msk (0x1U << AFIO_EXTICR1_EXTI1_PB_Pos) /*!< 0x00000010 */
+#define AFIO_EXTICR1_EXTI1_PB AFIO_EXTICR1_EXTI1_PB_Msk /*!< PB[1] pin */
+#define AFIO_EXTICR1_EXTI1_PC_Pos (5U)
+#define AFIO_EXTICR1_EXTI1_PC_Msk (0x1U << AFIO_EXTICR1_EXTI1_PC_Pos) /*!< 0x00000020 */
+#define AFIO_EXTICR1_EXTI1_PC AFIO_EXTICR1_EXTI1_PC_Msk /*!< PC[1] pin */
+#define AFIO_EXTICR1_EXTI1_PD_Pos (4U)
+#define AFIO_EXTICR1_EXTI1_PD_Msk (0x3U << AFIO_EXTICR1_EXTI1_PD_Pos) /*!< 0x00000030 */
+#define AFIO_EXTICR1_EXTI1_PD AFIO_EXTICR1_EXTI1_PD_Msk /*!< PD[1] pin */
+#define AFIO_EXTICR1_EXTI1_PE_Pos (6U)
+#define AFIO_EXTICR1_EXTI1_PE_Msk (0x1U << AFIO_EXTICR1_EXTI1_PE_Pos) /*!< 0x00000040 */
+#define AFIO_EXTICR1_EXTI1_PE AFIO_EXTICR1_EXTI1_PE_Msk /*!< PE[1] pin */
+#define AFIO_EXTICR1_EXTI1_PF_Pos (4U)
+#define AFIO_EXTICR1_EXTI1_PF_Msk (0x5U << AFIO_EXTICR1_EXTI1_PF_Pos) /*!< 0x00000050 */
+#define AFIO_EXTICR1_EXTI1_PF AFIO_EXTICR1_EXTI1_PF_Msk /*!< PF[1] pin */
+#define AFIO_EXTICR1_EXTI1_PG_Pos (5U)
+#define AFIO_EXTICR1_EXTI1_PG_Msk (0x3U << AFIO_EXTICR1_EXTI1_PG_Pos) /*!< 0x00000060 */
+#define AFIO_EXTICR1_EXTI1_PG AFIO_EXTICR1_EXTI1_PG_Msk /*!< PG[1] pin */
+
+/*!< EXTI2 configuration */
+#define AFIO_EXTICR1_EXTI2_PA ((uint32_t)0x00000000) /*!< PA[2] pin */
+#define AFIO_EXTICR1_EXTI2_PB_Pos (8U)
+#define AFIO_EXTICR1_EXTI2_PB_Msk (0x1U << AFIO_EXTICR1_EXTI2_PB_Pos) /*!< 0x00000100 */
+#define AFIO_EXTICR1_EXTI2_PB AFIO_EXTICR1_EXTI2_PB_Msk /*!< PB[2] pin */
+#define AFIO_EXTICR1_EXTI2_PC_Pos (9U)
+#define AFIO_EXTICR1_EXTI2_PC_Msk (0x1U << AFIO_EXTICR1_EXTI2_PC_Pos) /*!< 0x00000200 */
+#define AFIO_EXTICR1_EXTI2_PC AFIO_EXTICR1_EXTI2_PC_Msk /*!< PC[2] pin */
+#define AFIO_EXTICR1_EXTI2_PD_Pos (8U)
+#define AFIO_EXTICR1_EXTI2_PD_Msk (0x3U << AFIO_EXTICR1_EXTI2_PD_Pos) /*!< 0x00000300 */
+#define AFIO_EXTICR1_EXTI2_PD AFIO_EXTICR1_EXTI2_PD_Msk /*!< PD[2] pin */
+#define AFIO_EXTICR1_EXTI2_PE_Pos (10U)
+#define AFIO_EXTICR1_EXTI2_PE_Msk (0x1U << AFIO_EXTICR1_EXTI2_PE_Pos) /*!< 0x00000400 */
+#define AFIO_EXTICR1_EXTI2_PE AFIO_EXTICR1_EXTI2_PE_Msk /*!< PE[2] pin */
+#define AFIO_EXTICR1_EXTI2_PF_Pos (8U)
+#define AFIO_EXTICR1_EXTI2_PF_Msk (0x5U << AFIO_EXTICR1_EXTI2_PF_Pos) /*!< 0x00000500 */
+#define AFIO_EXTICR1_EXTI2_PF AFIO_EXTICR1_EXTI2_PF_Msk /*!< PF[2] pin */
+#define AFIO_EXTICR1_EXTI2_PG_Pos (9U)
+#define AFIO_EXTICR1_EXTI2_PG_Msk (0x3U << AFIO_EXTICR1_EXTI2_PG_Pos) /*!< 0x00000600 */
+#define AFIO_EXTICR1_EXTI2_PG AFIO_EXTICR1_EXTI2_PG_Msk /*!< PG[2] pin */
+
+/*!< EXTI3 configuration */
+#define AFIO_EXTICR1_EXTI3_PA ((uint32_t)0x00000000) /*!< PA[3] pin */
+#define AFIO_EXTICR1_EXTI3_PB_Pos (12U)
+#define AFIO_EXTICR1_EXTI3_PB_Msk (0x1U << AFIO_EXTICR1_EXTI3_PB_Pos) /*!< 0x00001000 */
+#define AFIO_EXTICR1_EXTI3_PB AFIO_EXTICR1_EXTI3_PB_Msk /*!< PB[3] pin */
+#define AFIO_EXTICR1_EXTI3_PC_Pos (13U)
+#define AFIO_EXTICR1_EXTI3_PC_Msk (0x1U << AFIO_EXTICR1_EXTI3_PC_Pos) /*!< 0x00002000 */
+#define AFIO_EXTICR1_EXTI3_PC AFIO_EXTICR1_EXTI3_PC_Msk /*!< PC[3] pin */
+#define AFIO_EXTICR1_EXTI3_PD_Pos (12U)
+#define AFIO_EXTICR1_EXTI3_PD_Msk (0x3U << AFIO_EXTICR1_EXTI3_PD_Pos) /*!< 0x00003000 */
+#define AFIO_EXTICR1_EXTI3_PD AFIO_EXTICR1_EXTI3_PD_Msk /*!< PD[3] pin */
+#define AFIO_EXTICR1_EXTI3_PE_Pos (14U)
+#define AFIO_EXTICR1_EXTI3_PE_Msk (0x1U << AFIO_EXTICR1_EXTI3_PE_Pos) /*!< 0x00004000 */
+#define AFIO_EXTICR1_EXTI3_PE AFIO_EXTICR1_EXTI3_PE_Msk /*!< PE[3] pin */
+#define AFIO_EXTICR1_EXTI3_PF_Pos (12U)
+#define AFIO_EXTICR1_EXTI3_PF_Msk (0x5U << AFIO_EXTICR1_EXTI3_PF_Pos) /*!< 0x00005000 */
+#define AFIO_EXTICR1_EXTI3_PF AFIO_EXTICR1_EXTI3_PF_Msk /*!< PF[3] pin */
+#define AFIO_EXTICR1_EXTI3_PG_Pos (13U)
+#define AFIO_EXTICR1_EXTI3_PG_Msk (0x3U << AFIO_EXTICR1_EXTI3_PG_Pos) /*!< 0x00006000 */
+#define AFIO_EXTICR1_EXTI3_PG AFIO_EXTICR1_EXTI3_PG_Msk /*!< PG[3] pin */
+
+/***************** Bit definition for AFIO_EXTICR2 register *****************/
+#define AFIO_EXTICR2_EXTI4_Pos (0U)
+#define AFIO_EXTICR2_EXTI4_Msk (0xFU << AFIO_EXTICR2_EXTI4_Pos) /*!< 0x0000000F */
+#define AFIO_EXTICR2_EXTI4 AFIO_EXTICR2_EXTI4_Msk /*!< EXTI 4 configuration */
+#define AFIO_EXTICR2_EXTI5_Pos (4U)
+#define AFIO_EXTICR2_EXTI5_Msk (0xFU << AFIO_EXTICR2_EXTI5_Pos) /*!< 0x000000F0 */
+#define AFIO_EXTICR2_EXTI5 AFIO_EXTICR2_EXTI5_Msk /*!< EXTI 5 configuration */
+#define AFIO_EXTICR2_EXTI6_Pos (8U)
+#define AFIO_EXTICR2_EXTI6_Msk (0xFU << AFIO_EXTICR2_EXTI6_Pos) /*!< 0x00000F00 */
+#define AFIO_EXTICR2_EXTI6 AFIO_EXTICR2_EXTI6_Msk /*!< EXTI 6 configuration */
+#define AFIO_EXTICR2_EXTI7_Pos (12U)
+#define AFIO_EXTICR2_EXTI7_Msk (0xFU << AFIO_EXTICR2_EXTI7_Pos) /*!< 0x0000F000 */
+#define AFIO_EXTICR2_EXTI7 AFIO_EXTICR2_EXTI7_Msk /*!< EXTI 7 configuration */
+
+/*!< EXTI4 configuration */
+#define AFIO_EXTICR2_EXTI4_PA ((uint32_t)0x00000000) /*!< PA[4] pin */
+#define AFIO_EXTICR2_EXTI4_PB_Pos (0U)
+#define AFIO_EXTICR2_EXTI4_PB_Msk (0x1U << AFIO_EXTICR2_EXTI4_PB_Pos) /*!< 0x00000001 */
+#define AFIO_EXTICR2_EXTI4_PB AFIO_EXTICR2_EXTI4_PB_Msk /*!< PB[4] pin */
+#define AFIO_EXTICR2_EXTI4_PC_Pos (1U)
+#define AFIO_EXTICR2_EXTI4_PC_Msk (0x1U << AFIO_EXTICR2_EXTI4_PC_Pos) /*!< 0x00000002 */
+#define AFIO_EXTICR2_EXTI4_PC AFIO_EXTICR2_EXTI4_PC_Msk /*!< PC[4] pin */
+#define AFIO_EXTICR2_EXTI4_PD_Pos (0U)
+#define AFIO_EXTICR2_EXTI4_PD_Msk (0x3U << AFIO_EXTICR2_EXTI4_PD_Pos) /*!< 0x00000003 */
+#define AFIO_EXTICR2_EXTI4_PD AFIO_EXTICR2_EXTI4_PD_Msk /*!< PD[4] pin */
+#define AFIO_EXTICR2_EXTI4_PE_Pos (2U)
+#define AFIO_EXTICR2_EXTI4_PE_Msk (0x1U << AFIO_EXTICR2_EXTI4_PE_Pos) /*!< 0x00000004 */
+#define AFIO_EXTICR2_EXTI4_PE AFIO_EXTICR2_EXTI4_PE_Msk /*!< PE[4] pin */
+#define AFIO_EXTICR2_EXTI4_PF_Pos (0U)
+#define AFIO_EXTICR2_EXTI4_PF_Msk (0x5U << AFIO_EXTICR2_EXTI4_PF_Pos) /*!< 0x00000005 */
+#define AFIO_EXTICR2_EXTI4_PF AFIO_EXTICR2_EXTI4_PF_Msk /*!< PF[4] pin */
+#define AFIO_EXTICR2_EXTI4_PG_Pos (1U)
+#define AFIO_EXTICR2_EXTI4_PG_Msk (0x3U << AFIO_EXTICR2_EXTI4_PG_Pos) /*!< 0x00000006 */
+#define AFIO_EXTICR2_EXTI4_PG AFIO_EXTICR2_EXTI4_PG_Msk /*!< PG[4] pin */
+
+/* EXTI5 configuration */
+#define AFIO_EXTICR2_EXTI5_PA ((uint32_t)0x00000000) /*!< PA[5] pin */
+#define AFIO_EXTICR2_EXTI5_PB_Pos (4U)
+#define AFIO_EXTICR2_EXTI5_PB_Msk (0x1U << AFIO_EXTICR2_EXTI5_PB_Pos) /*!< 0x00000010 */
+#define AFIO_EXTICR2_EXTI5_PB AFIO_EXTICR2_EXTI5_PB_Msk /*!< PB[5] pin */
+#define AFIO_EXTICR2_EXTI5_PC_Pos (5U)
+#define AFIO_EXTICR2_EXTI5_PC_Msk (0x1U << AFIO_EXTICR2_EXTI5_PC_Pos) /*!< 0x00000020 */
+#define AFIO_EXTICR2_EXTI5_PC AFIO_EXTICR2_EXTI5_PC_Msk /*!< PC[5] pin */
+#define AFIO_EXTICR2_EXTI5_PD_Pos (4U)
+#define AFIO_EXTICR2_EXTI5_PD_Msk (0x3U << AFIO_EXTICR2_EXTI5_PD_Pos) /*!< 0x00000030 */
+#define AFIO_EXTICR2_EXTI5_PD AFIO_EXTICR2_EXTI5_PD_Msk /*!< PD[5] pin */
+#define AFIO_EXTICR2_EXTI5_PE_Pos (6U)
+#define AFIO_EXTICR2_EXTI5_PE_Msk (0x1U << AFIO_EXTICR2_EXTI5_PE_Pos) /*!< 0x00000040 */
+#define AFIO_EXTICR2_EXTI5_PE AFIO_EXTICR2_EXTI5_PE_Msk /*!< PE[5] pin */
+#define AFIO_EXTICR2_EXTI5_PF_Pos (4U)
+#define AFIO_EXTICR2_EXTI5_PF_Msk (0x5U << AFIO_EXTICR2_EXTI5_PF_Pos) /*!< 0x00000050 */
+#define AFIO_EXTICR2_EXTI5_PF AFIO_EXTICR2_EXTI5_PF_Msk /*!< PF[5] pin */
+#define AFIO_EXTICR2_EXTI5_PG_Pos (5U)
+#define AFIO_EXTICR2_EXTI5_PG_Msk (0x3U << AFIO_EXTICR2_EXTI5_PG_Pos) /*!< 0x00000060 */
+#define AFIO_EXTICR2_EXTI5_PG AFIO_EXTICR2_EXTI5_PG_Msk /*!< PG[5] pin */
+
+/*!< EXTI6 configuration */
+#define AFIO_EXTICR2_EXTI6_PA ((uint32_t)0x00000000) /*!< PA[6] pin */
+#define AFIO_EXTICR2_EXTI6_PB_Pos (8U)
+#define AFIO_EXTICR2_EXTI6_PB_Msk (0x1U << AFIO_EXTICR2_EXTI6_PB_Pos) /*!< 0x00000100 */
+#define AFIO_EXTICR2_EXTI6_PB AFIO_EXTICR2_EXTI6_PB_Msk /*!< PB[6] pin */
+#define AFIO_EXTICR2_EXTI6_PC_Pos (9U)
+#define AFIO_EXTICR2_EXTI6_PC_Msk (0x1U << AFIO_EXTICR2_EXTI6_PC_Pos) /*!< 0x00000200 */
+#define AFIO_EXTICR2_EXTI6_PC AFIO_EXTICR2_EXTI6_PC_Msk /*!< PC[6] pin */
+#define AFIO_EXTICR2_EXTI6_PD_Pos (8U)
+#define AFIO_EXTICR2_EXTI6_PD_Msk (0x3U << AFIO_EXTICR2_EXTI6_PD_Pos) /*!< 0x00000300 */
+#define AFIO_EXTICR2_EXTI6_PD AFIO_EXTICR2_EXTI6_PD_Msk /*!< PD[6] pin */
+#define AFIO_EXTICR2_EXTI6_PE_Pos (10U)
+#define AFIO_EXTICR2_EXTI6_PE_Msk (0x1U << AFIO_EXTICR2_EXTI6_PE_Pos) /*!< 0x00000400 */
+#define AFIO_EXTICR2_EXTI6_PE AFIO_EXTICR2_EXTI6_PE_Msk /*!< PE[6] pin */
+#define AFIO_EXTICR2_EXTI6_PF_Pos (8U)
+#define AFIO_EXTICR2_EXTI6_PF_Msk (0x5U << AFIO_EXTICR2_EXTI6_PF_Pos) /*!< 0x00000500 */
+#define AFIO_EXTICR2_EXTI6_PF AFIO_EXTICR2_EXTI6_PF_Msk /*!< PF[6] pin */
+#define AFIO_EXTICR2_EXTI6_PG_Pos (9U)
+#define AFIO_EXTICR2_EXTI6_PG_Msk (0x3U << AFIO_EXTICR2_EXTI6_PG_Pos) /*!< 0x00000600 */
+#define AFIO_EXTICR2_EXTI6_PG AFIO_EXTICR2_EXTI6_PG_Msk /*!< PG[6] pin */
+
+/*!< EXTI7 configuration */
+#define AFIO_EXTICR2_EXTI7_PA ((uint32_t)0x00000000) /*!< PA[7] pin */
+#define AFIO_EXTICR2_EXTI7_PB_Pos (12U)
+#define AFIO_EXTICR2_EXTI7_PB_Msk (0x1U << AFIO_EXTICR2_EXTI7_PB_Pos) /*!< 0x00001000 */
+#define AFIO_EXTICR2_EXTI7_PB AFIO_EXTICR2_EXTI7_PB_Msk /*!< PB[7] pin */
+#define AFIO_EXTICR2_EXTI7_PC_Pos (13U)
+#define AFIO_EXTICR2_EXTI7_PC_Msk (0x1U << AFIO_EXTICR2_EXTI7_PC_Pos) /*!< 0x00002000 */
+#define AFIO_EXTICR2_EXTI7_PC AFIO_EXTICR2_EXTI7_PC_Msk /*!< PC[7] pin */
+#define AFIO_EXTICR2_EXTI7_PD_Pos (12U)
+#define AFIO_EXTICR2_EXTI7_PD_Msk (0x3U << AFIO_EXTICR2_EXTI7_PD_Pos) /*!< 0x00003000 */
+#define AFIO_EXTICR2_EXTI7_PD AFIO_EXTICR2_EXTI7_PD_Msk /*!< PD[7] pin */
+#define AFIO_EXTICR2_EXTI7_PE_Pos (14U)
+#define AFIO_EXTICR2_EXTI7_PE_Msk (0x1U << AFIO_EXTICR2_EXTI7_PE_Pos) /*!< 0x00004000 */
+#define AFIO_EXTICR2_EXTI7_PE AFIO_EXTICR2_EXTI7_PE_Msk /*!< PE[7] pin */
+#define AFIO_EXTICR2_EXTI7_PF_Pos (12U)
+#define AFIO_EXTICR2_EXTI7_PF_Msk (0x5U << AFIO_EXTICR2_EXTI7_PF_Pos) /*!< 0x00005000 */
+#define AFIO_EXTICR2_EXTI7_PF AFIO_EXTICR2_EXTI7_PF_Msk /*!< PF[7] pin */
+#define AFIO_EXTICR2_EXTI7_PG_Pos (13U)
+#define AFIO_EXTICR2_EXTI7_PG_Msk (0x3U << AFIO_EXTICR2_EXTI7_PG_Pos) /*!< 0x00006000 */
+#define AFIO_EXTICR2_EXTI7_PG AFIO_EXTICR2_EXTI7_PG_Msk /*!< PG[7] pin */
+
+/***************** Bit definition for AFIO_EXTICR3 register *****************/
+#define AFIO_EXTICR3_EXTI8_Pos (0U)
+#define AFIO_EXTICR3_EXTI8_Msk (0xFU << AFIO_EXTICR3_EXTI8_Pos) /*!< 0x0000000F */
+#define AFIO_EXTICR3_EXTI8 AFIO_EXTICR3_EXTI8_Msk /*!< EXTI 8 configuration */
+#define AFIO_EXTICR3_EXTI9_Pos (4U)
+#define AFIO_EXTICR3_EXTI9_Msk (0xFU << AFIO_EXTICR3_EXTI9_Pos) /*!< 0x000000F0 */
+#define AFIO_EXTICR3_EXTI9 AFIO_EXTICR3_EXTI9_Msk /*!< EXTI 9 configuration */
+#define AFIO_EXTICR3_EXTI10_Pos (8U)
+#define AFIO_EXTICR3_EXTI10_Msk (0xFU << AFIO_EXTICR3_EXTI10_Pos) /*!< 0x00000F00 */
+#define AFIO_EXTICR3_EXTI10 AFIO_EXTICR3_EXTI10_Msk /*!< EXTI 10 configuration */
+#define AFIO_EXTICR3_EXTI11_Pos (12U)
+#define AFIO_EXTICR3_EXTI11_Msk (0xFU << AFIO_EXTICR3_EXTI11_Pos) /*!< 0x0000F000 */
+#define AFIO_EXTICR3_EXTI11 AFIO_EXTICR3_EXTI11_Msk /*!< EXTI 11 configuration */
+
+/*!< EXTI8 configuration */
+#define AFIO_EXTICR3_EXTI8_PA ((uint32_t)0x00000000) /*!< PA[8] pin */
+#define AFIO_EXTICR3_EXTI8_PB_Pos (0U)
+#define AFIO_EXTICR3_EXTI8_PB_Msk (0x1U << AFIO_EXTICR3_EXTI8_PB_Pos) /*!< 0x00000001 */
+#define AFIO_EXTICR3_EXTI8_PB AFIO_EXTICR3_EXTI8_PB_Msk /*!< PB[8] pin */
+#define AFIO_EXTICR3_EXTI8_PC_Pos (1U)
+#define AFIO_EXTICR3_EXTI8_PC_Msk (0x1U << AFIO_EXTICR3_EXTI8_PC_Pos) /*!< 0x00000002 */
+#define AFIO_EXTICR3_EXTI8_PC AFIO_EXTICR3_EXTI8_PC_Msk /*!< PC[8] pin */
+#define AFIO_EXTICR3_EXTI8_PD_Pos (0U)
+#define AFIO_EXTICR3_EXTI8_PD_Msk (0x3U << AFIO_EXTICR3_EXTI8_PD_Pos) /*!< 0x00000003 */
+#define AFIO_EXTICR3_EXTI8_PD AFIO_EXTICR3_EXTI8_PD_Msk /*!< PD[8] pin */
+#define AFIO_EXTICR3_EXTI8_PE_Pos (2U)
+#define AFIO_EXTICR3_EXTI8_PE_Msk (0x1U << AFIO_EXTICR3_EXTI8_PE_Pos) /*!< 0x00000004 */
+#define AFIO_EXTICR3_EXTI8_PE AFIO_EXTICR3_EXTI8_PE_Msk /*!< PE[8] pin */
+#define AFIO_EXTICR3_EXTI8_PF_Pos (0U)
+#define AFIO_EXTICR3_EXTI8_PF_Msk (0x5U << AFIO_EXTICR3_EXTI8_PF_Pos) /*!< 0x00000005 */
+#define AFIO_EXTICR3_EXTI8_PF AFIO_EXTICR3_EXTI8_PF_Msk /*!< PF[8] pin */
+#define AFIO_EXTICR3_EXTI8_PG_Pos (1U)
+#define AFIO_EXTICR3_EXTI8_PG_Msk (0x3U << AFIO_EXTICR3_EXTI8_PG_Pos) /*!< 0x00000006 */
+#define AFIO_EXTICR3_EXTI8_PG AFIO_EXTICR3_EXTI8_PG_Msk /*!< PG[8] pin */
+
+/*!< EXTI9 configuration */
+#define AFIO_EXTICR3_EXTI9_PA ((uint32_t)0x00000000) /*!< PA[9] pin */
+#define AFIO_EXTICR3_EXTI9_PB_Pos (4U)
+#define AFIO_EXTICR3_EXTI9_PB_Msk (0x1U << AFIO_EXTICR3_EXTI9_PB_Pos) /*!< 0x00000010 */
+#define AFIO_EXTICR3_EXTI9_PB AFIO_EXTICR3_EXTI9_PB_Msk /*!< PB[9] pin */
+#define AFIO_EXTICR3_EXTI9_PC_Pos (5U)
+#define AFIO_EXTICR3_EXTI9_PC_Msk (0x1U << AFIO_EXTICR3_EXTI9_PC_Pos) /*!< 0x00000020 */
+#define AFIO_EXTICR3_EXTI9_PC AFIO_EXTICR3_EXTI9_PC_Msk /*!< PC[9] pin */
+#define AFIO_EXTICR3_EXTI9_PD_Pos (4U)
+#define AFIO_EXTICR3_EXTI9_PD_Msk (0x3U << AFIO_EXTICR3_EXTI9_PD_Pos) /*!< 0x00000030 */
+#define AFIO_EXTICR3_EXTI9_PD AFIO_EXTICR3_EXTI9_PD_Msk /*!< PD[9] pin */
+#define AFIO_EXTICR3_EXTI9_PE_Pos (6U)
+#define AFIO_EXTICR3_EXTI9_PE_Msk (0x1U << AFIO_EXTICR3_EXTI9_PE_Pos) /*!< 0x00000040 */
+#define AFIO_EXTICR3_EXTI9_PE AFIO_EXTICR3_EXTI9_PE_Msk /*!< PE[9] pin */
+#define AFIO_EXTICR3_EXTI9_PF_Pos (4U)
+#define AFIO_EXTICR3_EXTI9_PF_Msk (0x5U << AFIO_EXTICR3_EXTI9_PF_Pos) /*!< 0x00000050 */
+#define AFIO_EXTICR3_EXTI9_PF AFIO_EXTICR3_EXTI9_PF_Msk /*!< PF[9] pin */
+#define AFIO_EXTICR3_EXTI9_PG_Pos (5U)
+#define AFIO_EXTICR3_EXTI9_PG_Msk (0x3U << AFIO_EXTICR3_EXTI9_PG_Pos) /*!< 0x00000060 */
+#define AFIO_EXTICR3_EXTI9_PG AFIO_EXTICR3_EXTI9_PG_Msk /*!< PG[9] pin */
+
+/*!< EXTI10 configuration */
+#define AFIO_EXTICR3_EXTI10_PA ((uint32_t)0x00000000) /*!< PA[10] pin */
+#define AFIO_EXTICR3_EXTI10_PB_Pos (8U)
+#define AFIO_EXTICR3_EXTI10_PB_Msk (0x1U << AFIO_EXTICR3_EXTI10_PB_Pos) /*!< 0x00000100 */
+#define AFIO_EXTICR3_EXTI10_PB AFIO_EXTICR3_EXTI10_PB_Msk /*!< PB[10] pin */
+#define AFIO_EXTICR3_EXTI10_PC_Pos (9U)
+#define AFIO_EXTICR3_EXTI10_PC_Msk (0x1U << AFIO_EXTICR3_EXTI10_PC_Pos) /*!< 0x00000200 */
+#define AFIO_EXTICR3_EXTI10_PC AFIO_EXTICR3_EXTI10_PC_Msk /*!< PC[10] pin */
+#define AFIO_EXTICR3_EXTI10_PD_Pos (8U)
+#define AFIO_EXTICR3_EXTI10_PD_Msk (0x3U << AFIO_EXTICR3_EXTI10_PD_Pos) /*!< 0x00000300 */
+#define AFIO_EXTICR3_EXTI10_PD AFIO_EXTICR3_EXTI10_PD_Msk /*!< PD[10] pin */
+#define AFIO_EXTICR3_EXTI10_PE_Pos (10U)
+#define AFIO_EXTICR3_EXTI10_PE_Msk (0x1U << AFIO_EXTICR3_EXTI10_PE_Pos) /*!< 0x00000400 */
+#define AFIO_EXTICR3_EXTI10_PE AFIO_EXTICR3_EXTI10_PE_Msk /*!< PE[10] pin */
+#define AFIO_EXTICR3_EXTI10_PF_Pos (8U)
+#define AFIO_EXTICR3_EXTI10_PF_Msk (0x5U << AFIO_EXTICR3_EXTI10_PF_Pos) /*!< 0x00000500 */
+#define AFIO_EXTICR3_EXTI10_PF AFIO_EXTICR3_EXTI10_PF_Msk /*!< PF[10] pin */
+#define AFIO_EXTICR3_EXTI10_PG_Pos (9U)
+#define AFIO_EXTICR3_EXTI10_PG_Msk (0x3U << AFIO_EXTICR3_EXTI10_PG_Pos) /*!< 0x00000600 */
+#define AFIO_EXTICR3_EXTI10_PG AFIO_EXTICR3_EXTI10_PG_Msk /*!< PG[10] pin */
+
+/*!< EXTI11 configuration */
+#define AFIO_EXTICR3_EXTI11_PA ((uint32_t)0x00000000) /*!< PA[11] pin */
+#define AFIO_EXTICR3_EXTI11_PB_Pos (12U)
+#define AFIO_EXTICR3_EXTI11_PB_Msk (0x1U << AFIO_EXTICR3_EXTI11_PB_Pos) /*!< 0x00001000 */
+#define AFIO_EXTICR3_EXTI11_PB AFIO_EXTICR3_EXTI11_PB_Msk /*!< PB[11] pin */
+#define AFIO_EXTICR3_EXTI11_PC_Pos (13U)
+#define AFIO_EXTICR3_EXTI11_PC_Msk (0x1U << AFIO_EXTICR3_EXTI11_PC_Pos) /*!< 0x00002000 */
+#define AFIO_EXTICR3_EXTI11_PC AFIO_EXTICR3_EXTI11_PC_Msk /*!< PC[11] pin */
+#define AFIO_EXTICR3_EXTI11_PD_Pos (12U)
+#define AFIO_EXTICR3_EXTI11_PD_Msk (0x3U << AFIO_EXTICR3_EXTI11_PD_Pos) /*!< 0x00003000 */
+#define AFIO_EXTICR3_EXTI11_PD AFIO_EXTICR3_EXTI11_PD_Msk /*!< PD[11] pin */
+#define AFIO_EXTICR3_EXTI11_PE_Pos (14U)
+#define AFIO_EXTICR3_EXTI11_PE_Msk (0x1U << AFIO_EXTICR3_EXTI11_PE_Pos) /*!< 0x00004000 */
+#define AFIO_EXTICR3_EXTI11_PE AFIO_EXTICR3_EXTI11_PE_Msk /*!< PE[11] pin */
+#define AFIO_EXTICR3_EXTI11_PF_Pos (12U)
+#define AFIO_EXTICR3_EXTI11_PF_Msk (0x5U << AFIO_EXTICR3_EXTI11_PF_Pos) /*!< 0x00005000 */
+#define AFIO_EXTICR3_EXTI11_PF AFIO_EXTICR3_EXTI11_PF_Msk /*!< PF[11] pin */
+#define AFIO_EXTICR3_EXTI11_PG_Pos (13U)
+#define AFIO_EXTICR3_EXTI11_PG_Msk (0x3U << AFIO_EXTICR3_EXTI11_PG_Pos) /*!< 0x00006000 */
+#define AFIO_EXTICR3_EXTI11_PG AFIO_EXTICR3_EXTI11_PG_Msk /*!< PG[11] pin */
+
+/***************** Bit definition for AFIO_EXTICR4 register *****************/
+#define AFIO_EXTICR4_EXTI12_Pos (0U)
+#define AFIO_EXTICR4_EXTI12_Msk (0xFU << AFIO_EXTICR4_EXTI12_Pos) /*!< 0x0000000F */
+#define AFIO_EXTICR4_EXTI12 AFIO_EXTICR4_EXTI12_Msk /*!< EXTI 12 configuration */
+#define AFIO_EXTICR4_EXTI13_Pos (4U)
+#define AFIO_EXTICR4_EXTI13_Msk (0xFU << AFIO_EXTICR4_EXTI13_Pos) /*!< 0x000000F0 */
+#define AFIO_EXTICR4_EXTI13 AFIO_EXTICR4_EXTI13_Msk /*!< EXTI 13 configuration */
+#define AFIO_EXTICR4_EXTI14_Pos (8U)
+#define AFIO_EXTICR4_EXTI14_Msk (0xFU << AFIO_EXTICR4_EXTI14_Pos) /*!< 0x00000F00 */
+#define AFIO_EXTICR4_EXTI14 AFIO_EXTICR4_EXTI14_Msk /*!< EXTI 14 configuration */
+#define AFIO_EXTICR4_EXTI15_Pos (12U)
+#define AFIO_EXTICR4_EXTI15_Msk (0xFU << AFIO_EXTICR4_EXTI15_Pos) /*!< 0x0000F000 */
+#define AFIO_EXTICR4_EXTI15 AFIO_EXTICR4_EXTI15_Msk /*!< EXTI 15 configuration */
+
+/* EXTI12 configuration */
+#define AFIO_EXTICR4_EXTI12_PA ((uint32_t)0x00000000) /*!< PA[12] pin */
+#define AFIO_EXTICR4_EXTI12_PB_Pos (0U)
+#define AFIO_EXTICR4_EXTI12_PB_Msk (0x1U << AFIO_EXTICR4_EXTI12_PB_Pos) /*!< 0x00000001 */
+#define AFIO_EXTICR4_EXTI12_PB AFIO_EXTICR4_EXTI12_PB_Msk /*!< PB[12] pin */
+#define AFIO_EXTICR4_EXTI12_PC_Pos (1U)
+#define AFIO_EXTICR4_EXTI12_PC_Msk (0x1U << AFIO_EXTICR4_EXTI12_PC_Pos) /*!< 0x00000002 */
+#define AFIO_EXTICR4_EXTI12_PC AFIO_EXTICR4_EXTI12_PC_Msk /*!< PC[12] pin */
+#define AFIO_EXTICR4_EXTI12_PD_Pos (0U)
+#define AFIO_EXTICR4_EXTI12_PD_Msk (0x3U << AFIO_EXTICR4_EXTI12_PD_Pos) /*!< 0x00000003 */
+#define AFIO_EXTICR4_EXTI12_PD AFIO_EXTICR4_EXTI12_PD_Msk /*!< PD[12] pin */
+#define AFIO_EXTICR4_EXTI12_PE_Pos (2U)
+#define AFIO_EXTICR4_EXTI12_PE_Msk (0x1U << AFIO_EXTICR4_EXTI12_PE_Pos) /*!< 0x00000004 */
+#define AFIO_EXTICR4_EXTI12_PE AFIO_EXTICR4_EXTI12_PE_Msk /*!< PE[12] pin */
+#define AFIO_EXTICR4_EXTI12_PF_Pos (0U)
+#define AFIO_EXTICR4_EXTI12_PF_Msk (0x5U << AFIO_EXTICR4_EXTI12_PF_Pos) /*!< 0x00000005 */
+#define AFIO_EXTICR4_EXTI12_PF AFIO_EXTICR4_EXTI12_PF_Msk /*!< PF[12] pin */
+#define AFIO_EXTICR4_EXTI12_PG_Pos (1U)
+#define AFIO_EXTICR4_EXTI12_PG_Msk (0x3U << AFIO_EXTICR4_EXTI12_PG_Pos) /*!< 0x00000006 */
+#define AFIO_EXTICR4_EXTI12_PG AFIO_EXTICR4_EXTI12_PG_Msk /*!< PG[12] pin */
+
+/* EXTI13 configuration */
+#define AFIO_EXTICR4_EXTI13_PA ((uint32_t)0x00000000) /*!< PA[13] pin */
+#define AFIO_EXTICR4_EXTI13_PB_Pos (4U)
+#define AFIO_EXTICR4_EXTI13_PB_Msk (0x1U << AFIO_EXTICR4_EXTI13_PB_Pos) /*!< 0x00000010 */
+#define AFIO_EXTICR4_EXTI13_PB AFIO_EXTICR4_EXTI13_PB_Msk /*!< PB[13] pin */
+#define AFIO_EXTICR4_EXTI13_PC_Pos (5U)
+#define AFIO_EXTICR4_EXTI13_PC_Msk (0x1U << AFIO_EXTICR4_EXTI13_PC_Pos) /*!< 0x00000020 */
+#define AFIO_EXTICR4_EXTI13_PC AFIO_EXTICR4_EXTI13_PC_Msk /*!< PC[13] pin */
+#define AFIO_EXTICR4_EXTI13_PD_Pos (4U)
+#define AFIO_EXTICR4_EXTI13_PD_Msk (0x3U << AFIO_EXTICR4_EXTI13_PD_Pos) /*!< 0x00000030 */
+#define AFIO_EXTICR4_EXTI13_PD AFIO_EXTICR4_EXTI13_PD_Msk /*!< PD[13] pin */
+#define AFIO_EXTICR4_EXTI13_PE_Pos (6U)
+#define AFIO_EXTICR4_EXTI13_PE_Msk (0x1U << AFIO_EXTICR4_EXTI13_PE_Pos) /*!< 0x00000040 */
+#define AFIO_EXTICR4_EXTI13_PE AFIO_EXTICR4_EXTI13_PE_Msk /*!< PE[13] pin */
+#define AFIO_EXTICR4_EXTI13_PF_Pos (4U)
+#define AFIO_EXTICR4_EXTI13_PF_Msk (0x5U << AFIO_EXTICR4_EXTI13_PF_Pos) /*!< 0x00000050 */
+#define AFIO_EXTICR4_EXTI13_PF AFIO_EXTICR4_EXTI13_PF_Msk /*!< PF[13] pin */
+#define AFIO_EXTICR4_EXTI13_PG_Pos (5U)
+#define AFIO_EXTICR4_EXTI13_PG_Msk (0x3U << AFIO_EXTICR4_EXTI13_PG_Pos) /*!< 0x00000060 */
+#define AFIO_EXTICR4_EXTI13_PG AFIO_EXTICR4_EXTI13_PG_Msk /*!< PG[13] pin */
+
+/*!< EXTI14 configuration */
+#define AFIO_EXTICR4_EXTI14_PA ((uint32_t)0x00000000) /*!< PA[14] pin */
+#define AFIO_EXTICR4_EXTI14_PB_Pos (8U)
+#define AFIO_EXTICR4_EXTI14_PB_Msk (0x1U << AFIO_EXTICR4_EXTI14_PB_Pos) /*!< 0x00000100 */
+#define AFIO_EXTICR4_EXTI14_PB AFIO_EXTICR4_EXTI14_PB_Msk /*!< PB[14] pin */
+#define AFIO_EXTICR4_EXTI14_PC_Pos (9U)
+#define AFIO_EXTICR4_EXTI14_PC_Msk (0x1U << AFIO_EXTICR4_EXTI14_PC_Pos) /*!< 0x00000200 */
+#define AFIO_EXTICR4_EXTI14_PC AFIO_EXTICR4_EXTI14_PC_Msk /*!< PC[14] pin */
+#define AFIO_EXTICR4_EXTI14_PD_Pos (8U)
+#define AFIO_EXTICR4_EXTI14_PD_Msk (0x3U << AFIO_EXTICR4_EXTI14_PD_Pos) /*!< 0x00000300 */
+#define AFIO_EXTICR4_EXTI14_PD AFIO_EXTICR4_EXTI14_PD_Msk /*!< PD[14] pin */
+#define AFIO_EXTICR4_EXTI14_PE_Pos (10U)
+#define AFIO_EXTICR4_EXTI14_PE_Msk (0x1U << AFIO_EXTICR4_EXTI14_PE_Pos) /*!< 0x00000400 */
+#define AFIO_EXTICR4_EXTI14_PE AFIO_EXTICR4_EXTI14_PE_Msk /*!< PE[14] pin */
+#define AFIO_EXTICR4_EXTI14_PF_Pos (8U)
+#define AFIO_EXTICR4_EXTI14_PF_Msk (0x5U << AFIO_EXTICR4_EXTI14_PF_Pos) /*!< 0x00000500 */
+#define AFIO_EXTICR4_EXTI14_PF AFIO_EXTICR4_EXTI14_PF_Msk /*!< PF[14] pin */
+#define AFIO_EXTICR4_EXTI14_PG_Pos (9U)
+#define AFIO_EXTICR4_EXTI14_PG_Msk (0x3U << AFIO_EXTICR4_EXTI14_PG_Pos) /*!< 0x00000600 */
+#define AFIO_EXTICR4_EXTI14_PG AFIO_EXTICR4_EXTI14_PG_Msk /*!< PG[14] pin */
+
+/*!< EXTI15 configuration */
+#define AFIO_EXTICR4_EXTI15_PA ((uint32_t)0x00000000) /*!< PA[15] pin */
+#define AFIO_EXTICR4_EXTI15_PB_Pos (12U)
+#define AFIO_EXTICR4_EXTI15_PB_Msk (0x1U << AFIO_EXTICR4_EXTI15_PB_Pos) /*!< 0x00001000 */
+#define AFIO_EXTICR4_EXTI15_PB AFIO_EXTICR4_EXTI15_PB_Msk /*!< PB[15] pin */
+#define AFIO_EXTICR4_EXTI15_PC_Pos (13U)
+#define AFIO_EXTICR4_EXTI15_PC_Msk (0x1U << AFIO_EXTICR4_EXTI15_PC_Pos) /*!< 0x00002000 */
+#define AFIO_EXTICR4_EXTI15_PC AFIO_EXTICR4_EXTI15_PC_Msk /*!< PC[15] pin */
+#define AFIO_EXTICR4_EXTI15_PD_Pos (12U)
+#define AFIO_EXTICR4_EXTI15_PD_Msk (0x3U << AFIO_EXTICR4_EXTI15_PD_Pos) /*!< 0x00003000 */
+#define AFIO_EXTICR4_EXTI15_PD AFIO_EXTICR4_EXTI15_PD_Msk /*!< PD[15] pin */
+#define AFIO_EXTICR4_EXTI15_PE_Pos (14U)
+#define AFIO_EXTICR4_EXTI15_PE_Msk (0x1U << AFIO_EXTICR4_EXTI15_PE_Pos) /*!< 0x00004000 */
+#define AFIO_EXTICR4_EXTI15_PE AFIO_EXTICR4_EXTI15_PE_Msk /*!< PE[15] pin */
+#define AFIO_EXTICR4_EXTI15_PF_Pos (12U)
+#define AFIO_EXTICR4_EXTI15_PF_Msk (0x5U << AFIO_EXTICR4_EXTI15_PF_Pos) /*!< 0x00005000 */
+#define AFIO_EXTICR4_EXTI15_PF AFIO_EXTICR4_EXTI15_PF_Msk /*!< PF[15] pin */
+#define AFIO_EXTICR4_EXTI15_PG_Pos (13U)
+#define AFIO_EXTICR4_EXTI15_PG_Msk (0x3U << AFIO_EXTICR4_EXTI15_PG_Pos) /*!< 0x00006000 */
+#define AFIO_EXTICR4_EXTI15_PG AFIO_EXTICR4_EXTI15_PG_Msk /*!< PG[15] pin */
+
+/****************** Bit definition for AFIO_MAPR2 register ******************/
+
+
+
+/******************************************************************************/
+/* */
+/* SystemTick */
+/* */
+/******************************************************************************/
+
+/***************** Bit definition for SysTick_CTRL register *****************/
+#define SysTick_CTRL_ENABLE ((uint32_t)0x00000001) /*!< Counter enable */
+#define SysTick_CTRL_TICKINT ((uint32_t)0x00000002) /*!< Counting down to 0 pends the SysTick handler */
+#define SysTick_CTRL_CLKSOURCE ((uint32_t)0x00000004) /*!< Clock source */
+#define SysTick_CTRL_COUNTFLAG ((uint32_t)0x00010000) /*!< Count Flag */
+
+/***************** Bit definition for SysTick_LOAD register *****************/
+#define SysTick_LOAD_RELOAD ((uint32_t)0x00FFFFFF) /*!< Value to load into the SysTick Current Value Register when the counter reaches 0 */
+
+/***************** Bit definition for SysTick_VAL register ******************/
+#define SysTick_VAL_CURRENT ((uint32_t)0x00FFFFFF) /*!< Current value at the time the register is accessed */
+
+/***************** Bit definition for SysTick_CALIB register ****************/
+#define SysTick_CALIB_TENMS ((uint32_t)0x00FFFFFF) /*!< Reload value to use for 10ms timing */
+#define SysTick_CALIB_SKEW ((uint32_t)0x40000000) /*!< Calibration value is not exactly 10 ms */
+#define SysTick_CALIB_NOREF ((uint32_t)0x80000000) /*!< The reference clock is not provided */
+
+/******************************************************************************/
+/* */
+/* Nested Vectored Interrupt Controller */
+/* */
+/******************************************************************************/
+
+/****************** Bit definition for NVIC_ISER register *******************/
+#define NVIC_ISER_SETENA_Pos (0U)
+#define NVIC_ISER_SETENA_Msk (0xFFFFFFFFU << NVIC_ISER_SETENA_Pos) /*!< 0xFFFFFFFF */
+#define NVIC_ISER_SETENA NVIC_ISER_SETENA_Msk /*!< Interrupt set enable bits */
+#define NVIC_ISER_SETENA_0 (0x00000001U << NVIC_ISER_SETENA_Pos) /*!< 0x00000001 */
+#define NVIC_ISER_SETENA_1 (0x00000002U << NVIC_ISER_SETENA_Pos) /*!< 0x00000002 */
+#define NVIC_ISER_SETENA_2 (0x00000004U << NVIC_ISER_SETENA_Pos) /*!< 0x00000004 */
+#define NVIC_ISER_SETENA_3 (0x00000008U << NVIC_ISER_SETENA_Pos) /*!< 0x00000008 */
+#define NVIC_ISER_SETENA_4 (0x00000010U << NVIC_ISER_SETENA_Pos) /*!< 0x00000010 */
+#define NVIC_ISER_SETENA_5 (0x00000020U << NVIC_ISER_SETENA_Pos) /*!< 0x00000020 */
+#define NVIC_ISER_SETENA_6 (0x00000040U << NVIC_ISER_SETENA_Pos) /*!< 0x00000040 */
+#define NVIC_ISER_SETENA_7 (0x00000080U << NVIC_ISER_SETENA_Pos) /*!< 0x00000080 */
+#define NVIC_ISER_SETENA_8 (0x00000100U << NVIC_ISER_SETENA_Pos) /*!< 0x00000100 */
+#define NVIC_ISER_SETENA_9 (0x00000200U << NVIC_ISER_SETENA_Pos) /*!< 0x00000200 */
+#define NVIC_ISER_SETENA_10 (0x00000400U << NVIC_ISER_SETENA_Pos) /*!< 0x00000400 */
+#define NVIC_ISER_SETENA_11 (0x00000800U << NVIC_ISER_SETENA_Pos) /*!< 0x00000800 */
+#define NVIC_ISER_SETENA_12 (0x00001000U << NVIC_ISER_SETENA_Pos) /*!< 0x00001000 */
+#define NVIC_ISER_SETENA_13 (0x00002000U << NVIC_ISER_SETENA_Pos) /*!< 0x00002000 */
+#define NVIC_ISER_SETENA_14 (0x00004000U << NVIC_ISER_SETENA_Pos) /*!< 0x00004000 */
+#define NVIC_ISER_SETENA_15 (0x00008000U << NVIC_ISER_SETENA_Pos) /*!< 0x00008000 */
+#define NVIC_ISER_SETENA_16 (0x00010000U << NVIC_ISER_SETENA_Pos) /*!< 0x00010000 */
+#define NVIC_ISER_SETENA_17 (0x00020000U << NVIC_ISER_SETENA_Pos) /*!< 0x00020000 */
+#define NVIC_ISER_SETENA_18 (0x00040000U << NVIC_ISER_SETENA_Pos) /*!< 0x00040000 */
+#define NVIC_ISER_SETENA_19 (0x00080000U << NVIC_ISER_SETENA_Pos) /*!< 0x00080000 */
+#define NVIC_ISER_SETENA_20 (0x00100000U << NVIC_ISER_SETENA_Pos) /*!< 0x00100000 */
+#define NVIC_ISER_SETENA_21 (0x00200000U << NVIC_ISER_SETENA_Pos) /*!< 0x00200000 */
+#define NVIC_ISER_SETENA_22 (0x00400000U << NVIC_ISER_SETENA_Pos) /*!< 0x00400000 */
+#define NVIC_ISER_SETENA_23 (0x00800000U << NVIC_ISER_SETENA_Pos) /*!< 0x00800000 */
+#define NVIC_ISER_SETENA_24 (0x01000000U << NVIC_ISER_SETENA_Pos) /*!< 0x01000000 */
+#define NVIC_ISER_SETENA_25 (0x02000000U << NVIC_ISER_SETENA_Pos) /*!< 0x02000000 */
+#define NVIC_ISER_SETENA_26 (0x04000000U << NVIC_ISER_SETENA_Pos) /*!< 0x04000000 */
+#define NVIC_ISER_SETENA_27 (0x08000000U << NVIC_ISER_SETENA_Pos) /*!< 0x08000000 */
+#define NVIC_ISER_SETENA_28 (0x10000000U << NVIC_ISER_SETENA_Pos) /*!< 0x10000000 */
+#define NVIC_ISER_SETENA_29 (0x20000000U << NVIC_ISER_SETENA_Pos) /*!< 0x20000000 */
+#define NVIC_ISER_SETENA_30 (0x40000000U << NVIC_ISER_SETENA_Pos) /*!< 0x40000000 */
+#define NVIC_ISER_SETENA_31 (0x80000000U << NVIC_ISER_SETENA_Pos) /*!< 0x80000000 */
+
+/****************** Bit definition for NVIC_ICER register *******************/
+#define NVIC_ICER_CLRENA_Pos (0U)
+#define NVIC_ICER_CLRENA_Msk (0xFFFFFFFFU << NVIC_ICER_CLRENA_Pos) /*!< 0xFFFFFFFF */
+#define NVIC_ICER_CLRENA NVIC_ICER_CLRENA_Msk /*!< Interrupt clear-enable bits */
+#define NVIC_ICER_CLRENA_0 (0x00000001U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000001 */
+#define NVIC_ICER_CLRENA_1 (0x00000002U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000002 */
+#define NVIC_ICER_CLRENA_2 (0x00000004U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000004 */
+#define NVIC_ICER_CLRENA_3 (0x00000008U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000008 */
+#define NVIC_ICER_CLRENA_4 (0x00000010U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000010 */
+#define NVIC_ICER_CLRENA_5 (0x00000020U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000020 */
+#define NVIC_ICER_CLRENA_6 (0x00000040U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000040 */
+#define NVIC_ICER_CLRENA_7 (0x00000080U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000080 */
+#define NVIC_ICER_CLRENA_8 (0x00000100U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000100 */
+#define NVIC_ICER_CLRENA_9 (0x00000200U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000200 */
+#define NVIC_ICER_CLRENA_10 (0x00000400U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000400 */
+#define NVIC_ICER_CLRENA_11 (0x00000800U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000800 */
+#define NVIC_ICER_CLRENA_12 (0x00001000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00001000 */
+#define NVIC_ICER_CLRENA_13 (0x00002000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00002000 */
+#define NVIC_ICER_CLRENA_14 (0x00004000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00004000 */
+#define NVIC_ICER_CLRENA_15 (0x00008000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00008000 */
+#define NVIC_ICER_CLRENA_16 (0x00010000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00010000 */
+#define NVIC_ICER_CLRENA_17 (0x00020000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00020000 */
+#define NVIC_ICER_CLRENA_18 (0x00040000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00040000 */
+#define NVIC_ICER_CLRENA_19 (0x00080000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00080000 */
+#define NVIC_ICER_CLRENA_20 (0x00100000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00100000 */
+#define NVIC_ICER_CLRENA_21 (0x00200000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00200000 */
+#define NVIC_ICER_CLRENA_22 (0x00400000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00400000 */
+#define NVIC_ICER_CLRENA_23 (0x00800000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00800000 */
+#define NVIC_ICER_CLRENA_24 (0x01000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x01000000 */
+#define NVIC_ICER_CLRENA_25 (0x02000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x02000000 */
+#define NVIC_ICER_CLRENA_26 (0x04000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x04000000 */
+#define NVIC_ICER_CLRENA_27 (0x08000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x08000000 */
+#define NVIC_ICER_CLRENA_28 (0x10000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x10000000 */
+#define NVIC_ICER_CLRENA_29 (0x20000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x20000000 */
+#define NVIC_ICER_CLRENA_30 (0x40000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x40000000 */
+#define NVIC_ICER_CLRENA_31 (0x80000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x80000000 */
+
+/****************** Bit definition for NVIC_ISPR register *******************/
+#define NVIC_ISPR_SETPEND_Pos (0U)
+#define NVIC_ISPR_SETPEND_Msk (0xFFFFFFFFU << NVIC_ISPR_SETPEND_Pos) /*!< 0xFFFFFFFF */
+#define NVIC_ISPR_SETPEND NVIC_ISPR_SETPEND_Msk /*!< Interrupt set-pending bits */
+#define NVIC_ISPR_SETPEND_0 (0x00000001U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000001 */
+#define NVIC_ISPR_SETPEND_1 (0x00000002U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000002 */
+#define NVIC_ISPR_SETPEND_2 (0x00000004U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000004 */
+#define NVIC_ISPR_SETPEND_3 (0x00000008U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000008 */
+#define NVIC_ISPR_SETPEND_4 (0x00000010U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000010 */
+#define NVIC_ISPR_SETPEND_5 (0x00000020U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000020 */
+#define NVIC_ISPR_SETPEND_6 (0x00000040U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000040 */
+#define NVIC_ISPR_SETPEND_7 (0x00000080U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000080 */
+#define NVIC_ISPR_SETPEND_8 (0x00000100U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000100 */
+#define NVIC_ISPR_SETPEND_9 (0x00000200U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000200 */
+#define NVIC_ISPR_SETPEND_10 (0x00000400U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000400 */
+#define NVIC_ISPR_SETPEND_11 (0x00000800U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000800 */
+#define NVIC_ISPR_SETPEND_12 (0x00001000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00001000 */
+#define NVIC_ISPR_SETPEND_13 (0x00002000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00002000 */
+#define NVIC_ISPR_SETPEND_14 (0x00004000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00004000 */
+#define NVIC_ISPR_SETPEND_15 (0x00008000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00008000 */
+#define NVIC_ISPR_SETPEND_16 (0x00010000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00010000 */
+#define NVIC_ISPR_SETPEND_17 (0x00020000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00020000 */
+#define NVIC_ISPR_SETPEND_18 (0x00040000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00040000 */
+#define NVIC_ISPR_SETPEND_19 (0x00080000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00080000 */
+#define NVIC_ISPR_SETPEND_20 (0x00100000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00100000 */
+#define NVIC_ISPR_SETPEND_21 (0x00200000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00200000 */
+#define NVIC_ISPR_SETPEND_22 (0x00400000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00400000 */
+#define NVIC_ISPR_SETPEND_23 (0x00800000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00800000 */
+#define NVIC_ISPR_SETPEND_24 (0x01000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x01000000 */
+#define NVIC_ISPR_SETPEND_25 (0x02000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x02000000 */
+#define NVIC_ISPR_SETPEND_26 (0x04000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x04000000 */
+#define NVIC_ISPR_SETPEND_27 (0x08000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x08000000 */
+#define NVIC_ISPR_SETPEND_28 (0x10000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x10000000 */
+#define NVIC_ISPR_SETPEND_29 (0x20000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x20000000 */
+#define NVIC_ISPR_SETPEND_30 (0x40000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x40000000 */
+#define NVIC_ISPR_SETPEND_31 (0x80000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x80000000 */
+
+/****************** Bit definition for NVIC_ICPR register *******************/
+#define NVIC_ICPR_CLRPEND_Pos (0U)
+#define NVIC_ICPR_CLRPEND_Msk (0xFFFFFFFFU << NVIC_ICPR_CLRPEND_Pos) /*!< 0xFFFFFFFF */
+#define NVIC_ICPR_CLRPEND NVIC_ICPR_CLRPEND_Msk /*!< Interrupt clear-pending bits */
+#define NVIC_ICPR_CLRPEND_0 (0x00000001U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000001 */
+#define NVIC_ICPR_CLRPEND_1 (0x00000002U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000002 */
+#define NVIC_ICPR_CLRPEND_2 (0x00000004U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000004 */
+#define NVIC_ICPR_CLRPEND_3 (0x00000008U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000008 */
+#define NVIC_ICPR_CLRPEND_4 (0x00000010U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000010 */
+#define NVIC_ICPR_CLRPEND_5 (0x00000020U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000020 */
+#define NVIC_ICPR_CLRPEND_6 (0x00000040U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000040 */
+#define NVIC_ICPR_CLRPEND_7 (0x00000080U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000080 */
+#define NVIC_ICPR_CLRPEND_8 (0x00000100U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000100 */
+#define NVIC_ICPR_CLRPEND_9 (0x00000200U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000200 */
+#define NVIC_ICPR_CLRPEND_10 (0x00000400U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000400 */
+#define NVIC_ICPR_CLRPEND_11 (0x00000800U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000800 */
+#define NVIC_ICPR_CLRPEND_12 (0x00001000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00001000 */
+#define NVIC_ICPR_CLRPEND_13 (0x00002000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00002000 */
+#define NVIC_ICPR_CLRPEND_14 (0x00004000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00004000 */
+#define NVIC_ICPR_CLRPEND_15 (0x00008000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00008000 */
+#define NVIC_ICPR_CLRPEND_16 (0x00010000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00010000 */
+#define NVIC_ICPR_CLRPEND_17 (0x00020000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00020000 */
+#define NVIC_ICPR_CLRPEND_18 (0x00040000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00040000 */
+#define NVIC_ICPR_CLRPEND_19 (0x00080000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00080000 */
+#define NVIC_ICPR_CLRPEND_20 (0x00100000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00100000 */
+#define NVIC_ICPR_CLRPEND_21 (0x00200000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00200000 */
+#define NVIC_ICPR_CLRPEND_22 (0x00400000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00400000 */
+#define NVIC_ICPR_CLRPEND_23 (0x00800000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00800000 */
+#define NVIC_ICPR_CLRPEND_24 (0x01000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x01000000 */
+#define NVIC_ICPR_CLRPEND_25 (0x02000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x02000000 */
+#define NVIC_ICPR_CLRPEND_26 (0x04000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x04000000 */
+#define NVIC_ICPR_CLRPEND_27 (0x08000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x08000000 */
+#define NVIC_ICPR_CLRPEND_28 (0x10000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x10000000 */
+#define NVIC_ICPR_CLRPEND_29 (0x20000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x20000000 */
+#define NVIC_ICPR_CLRPEND_30 (0x40000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x40000000 */
+#define NVIC_ICPR_CLRPEND_31 (0x80000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x80000000 */
+
+/****************** Bit definition for NVIC_IABR register *******************/
+#define NVIC_IABR_ACTIVE_Pos (0U)
+#define NVIC_IABR_ACTIVE_Msk (0xFFFFFFFFU << NVIC_IABR_ACTIVE_Pos) /*!< 0xFFFFFFFF */
+#define NVIC_IABR_ACTIVE NVIC_IABR_ACTIVE_Msk /*!< Interrupt active flags */
+#define NVIC_IABR_ACTIVE_0 (0x00000001U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000001 */
+#define NVIC_IABR_ACTIVE_1 (0x00000002U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000002 */
+#define NVIC_IABR_ACTIVE_2 (0x00000004U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000004 */
+#define NVIC_IABR_ACTIVE_3 (0x00000008U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000008 */
+#define NVIC_IABR_ACTIVE_4 (0x00000010U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000010 */
+#define NVIC_IABR_ACTIVE_5 (0x00000020U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000020 */
+#define NVIC_IABR_ACTIVE_6 (0x00000040U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000040 */
+#define NVIC_IABR_ACTIVE_7 (0x00000080U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000080 */
+#define NVIC_IABR_ACTIVE_8 (0x00000100U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000100 */
+#define NVIC_IABR_ACTIVE_9 (0x00000200U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000200 */
+#define NVIC_IABR_ACTIVE_10 (0x00000400U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000400 */
+#define NVIC_IABR_ACTIVE_11 (0x00000800U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000800 */
+#define NVIC_IABR_ACTIVE_12 (0x00001000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00001000 */
+#define NVIC_IABR_ACTIVE_13 (0x00002000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00002000 */
+#define NVIC_IABR_ACTIVE_14 (0x00004000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00004000 */
+#define NVIC_IABR_ACTIVE_15 (0x00008000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00008000 */
+#define NVIC_IABR_ACTIVE_16 (0x00010000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00010000 */
+#define NVIC_IABR_ACTIVE_17 (0x00020000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00020000 */
+#define NVIC_IABR_ACTIVE_18 (0x00040000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00040000 */
+#define NVIC_IABR_ACTIVE_19 (0x00080000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00080000 */
+#define NVIC_IABR_ACTIVE_20 (0x00100000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00100000 */
+#define NVIC_IABR_ACTIVE_21 (0x00200000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00200000 */
+#define NVIC_IABR_ACTIVE_22 (0x00400000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00400000 */
+#define NVIC_IABR_ACTIVE_23 (0x00800000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00800000 */
+#define NVIC_IABR_ACTIVE_24 (0x01000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x01000000 */
+#define NVIC_IABR_ACTIVE_25 (0x02000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x02000000 */
+#define NVIC_IABR_ACTIVE_26 (0x04000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x04000000 */
+#define NVIC_IABR_ACTIVE_27 (0x08000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x08000000 */
+#define NVIC_IABR_ACTIVE_28 (0x10000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x10000000 */
+#define NVIC_IABR_ACTIVE_29 (0x20000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x20000000 */
+#define NVIC_IABR_ACTIVE_30 (0x40000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x40000000 */
+#define NVIC_IABR_ACTIVE_31 (0x80000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x80000000 */
+
+/****************** Bit definition for NVIC_PRI0 register *******************/
+#define NVIC_IPR0_PRI_0 ((uint32_t)0x000000FF) /*!< Priority of interrupt 0 */
+#define NVIC_IPR0_PRI_1 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 1 */
+#define NVIC_IPR0_PRI_2 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 2 */
+#define NVIC_IPR0_PRI_3 ((uint32_t)0xFF000000) /*!< Priority of interrupt 3 */
+
+/****************** Bit definition for NVIC_PRI1 register *******************/
+#define NVIC_IPR1_PRI_4 ((uint32_t)0x000000FF) /*!< Priority of interrupt 4 */
+#define NVIC_IPR1_PRI_5 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 5 */
+#define NVIC_IPR1_PRI_6 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 6 */
+#define NVIC_IPR1_PRI_7 ((uint32_t)0xFF000000) /*!< Priority of interrupt 7 */
+
+/****************** Bit definition for NVIC_PRI2 register *******************/
+#define NVIC_IPR2_PRI_8 ((uint32_t)0x000000FF) /*!< Priority of interrupt 8 */
+#define NVIC_IPR2_PRI_9 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 9 */
+#define NVIC_IPR2_PRI_10 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 10 */
+#define NVIC_IPR2_PRI_11 ((uint32_t)0xFF000000) /*!< Priority of interrupt 11 */
+
+/****************** Bit definition for NVIC_PRI3 register *******************/
+#define NVIC_IPR3_PRI_12 ((uint32_t)0x000000FF) /*!< Priority of interrupt 12 */
+#define NVIC_IPR3_PRI_13 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 13 */
+#define NVIC_IPR3_PRI_14 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 14 */
+#define NVIC_IPR3_PRI_15 ((uint32_t)0xFF000000) /*!< Priority of interrupt 15 */
+
+/****************** Bit definition for NVIC_PRI4 register *******************/
+#define NVIC_IPR4_PRI_16 ((uint32_t)0x000000FF) /*!< Priority of interrupt 16 */
+#define NVIC_IPR4_PRI_17 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 17 */
+#define NVIC_IPR4_PRI_18 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 18 */
+#define NVIC_IPR4_PRI_19 ((uint32_t)0xFF000000) /*!< Priority of interrupt 19 */
+
+/****************** Bit definition for NVIC_PRI5 register *******************/
+#define NVIC_IPR5_PRI_20 ((uint32_t)0x000000FF) /*!< Priority of interrupt 20 */
+#define NVIC_IPR5_PRI_21 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 21 */
+#define NVIC_IPR5_PRI_22 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 22 */
+#define NVIC_IPR5_PRI_23 ((uint32_t)0xFF000000) /*!< Priority of interrupt 23 */
+
+/****************** Bit definition for NVIC_PRI6 register *******************/
+#define NVIC_IPR6_PRI_24 ((uint32_t)0x000000FF) /*!< Priority of interrupt 24 */
+#define NVIC_IPR6_PRI_25 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 25 */
+#define NVIC_IPR6_PRI_26 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 26 */
+#define NVIC_IPR6_PRI_27 ((uint32_t)0xFF000000) /*!< Priority of interrupt 27 */
+
+/****************** Bit definition for NVIC_PRI7 register *******************/
+#define NVIC_IPR7_PRI_28 ((uint32_t)0x000000FF) /*!< Priority of interrupt 28 */
+#define NVIC_IPR7_PRI_29 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 29 */
+#define NVIC_IPR7_PRI_30 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 30 */
+#define NVIC_IPR7_PRI_31 ((uint32_t)0xFF000000) /*!< Priority of interrupt 31 */
+
+/****************** Bit definition for SCB_CPUID register *******************/
+#define SCB_CPUID_REVISION ((uint32_t)0x0000000F) /*!< Implementation defined revision number */
+#define SCB_CPUID_PARTNO ((uint32_t)0x0000FFF0) /*!< Number of processor within family */
+#define SCB_CPUID_Constant ((uint32_t)0x000F0000) /*!< Reads as 0x0F */
+#define SCB_CPUID_VARIANT ((uint32_t)0x00F00000) /*!< Implementation defined variant number */
+#define SCB_CPUID_IMPLEMENTER ((uint32_t)0xFF000000) /*!< Implementer code. ARM is 0x41 */
+
+/******************* Bit definition for SCB_ICSR register *******************/
+#define SCB_ICSR_VECTACTIVE ((uint32_t)0x000001FF) /*!< Active ISR number field */
+#define SCB_ICSR_RETTOBASE ((uint32_t)0x00000800) /*!< All active exceptions minus the IPSR_current_exception yields the empty set */
+#define SCB_ICSR_VECTPENDING ((uint32_t)0x003FF000) /*!< Pending ISR number field */
+#define SCB_ICSR_ISRPENDING ((uint32_t)0x00400000) /*!< Interrupt pending flag */
+#define SCB_ICSR_ISRPREEMPT ((uint32_t)0x00800000) /*!< It indicates that a pending interrupt becomes active in the next running cycle */
+#define SCB_ICSR_PENDSTCLR ((uint32_t)0x02000000) /*!< Clear pending SysTick bit */
+#define SCB_ICSR_PENDSTSET ((uint32_t)0x04000000) /*!< Set pending SysTick bit */
+#define SCB_ICSR_PENDSVCLR ((uint32_t)0x08000000) /*!< Clear pending pendSV bit */
+#define SCB_ICSR_PENDSVSET ((uint32_t)0x10000000) /*!< Set pending pendSV bit */
+#define SCB_ICSR_NMIPENDSET ((uint32_t)0x80000000) /*!< Set pending NMI bit */
+
+/******************* Bit definition for SCB_VTOR register *******************/
+#define SCB_VTOR_TBLOFF ((uint32_t)0x1FFFFF80) /*!< Vector table base offset field */
+#define SCB_VTOR_TBLBASE ((uint32_t)0x20000000) /*!< Table base in code(0) or RAM(1) */
+
+/*!<***************** Bit definition for SCB_AIRCR register *******************/
+#define SCB_AIRCR_VECTRESET ((uint32_t)0x00000001) /*!< System Reset bit */
+#define SCB_AIRCR_VECTCLRACTIVE ((uint32_t)0x00000002) /*!< Clear active vector bit */
+#define SCB_AIRCR_SYSRESETREQ ((uint32_t)0x00000004) /*!< Requests chip control logic to generate a reset */
+
+#define SCB_AIRCR_PRIGROUP ((uint32_t)0x00000700) /*!< PRIGROUP[2:0] bits (Priority group) */
+#define SCB_AIRCR_PRIGROUP_0 ((uint32_t)0x00000100) /*!< Bit 0 */
+#define SCB_AIRCR_PRIGROUP_1 ((uint32_t)0x00000200) /*!< Bit 1 */
+#define SCB_AIRCR_PRIGROUP_2 ((uint32_t)0x00000400) /*!< Bit 2 */
+
+/* prority group configuration */
+#define SCB_AIRCR_PRIGROUP0 ((uint32_t)0x00000000) /*!< Priority group=0 (7 bits of pre-emption priority, 1 bit of subpriority) */
+#define SCB_AIRCR_PRIGROUP1 ((uint32_t)0x00000100) /*!< Priority group=1 (6 bits of pre-emption priority, 2 bits of subpriority) */
+#define SCB_AIRCR_PRIGROUP2 ((uint32_t)0x00000200) /*!< Priority group=2 (5 bits of pre-emption priority, 3 bits of subpriority) */
+#define SCB_AIRCR_PRIGROUP3 ((uint32_t)0x00000300) /*!< Priority group=3 (4 bits of pre-emption priority, 4 bits of subpriority) */
+#define SCB_AIRCR_PRIGROUP4 ((uint32_t)0x00000400) /*!< Priority group=4 (3 bits of pre-emption priority, 5 bits of subpriority) */
+#define SCB_AIRCR_PRIGROUP5 ((uint32_t)0x00000500) /*!< Priority group=5 (2 bits of pre-emption priority, 6 bits of subpriority) */
+#define SCB_AIRCR_PRIGROUP6 ((uint32_t)0x00000600) /*!< Priority group=6 (1 bit of pre-emption priority, 7 bits of subpriority) */
+#define SCB_AIRCR_PRIGROUP7 ((uint32_t)0x00000700) /*!< Priority group=7 (no pre-emption priority, 8 bits of subpriority) */
+
+#define SCB_AIRCR_ENDIANESS ((uint32_t)0x00008000) /*!< Data endianness bit */
+#define SCB_AIRCR_VECTKEY ((uint32_t)0xFFFF0000) /*!< Register key (VECTKEY) - Reads as 0xFA05 (VECTKEYSTAT) */
+
+/******************* Bit definition for SCB_SCR register ********************/
+#define SCB_SCR_SLEEPONEXIT ((uint32_t)0x00000002) /*!< Sleep on exit bit */
+#define SCB_SCR_SLEEPDEEP ((uint32_t)0x00000004) /*!< Sleep deep bit */
+#define SCB_SCR_SEVONPEND ((uint32_t)0x00000010) /*!< Wake up from WFE */
+
+/******************** Bit definition for SCB_CCR register *******************/
+#define SCB_CCR_NONBASETHRDENA ((uint32_t)0x00000001) /*!< Thread mode can be entered from any level in Handler mode by controlled return value */
+#define SCB_CCR_USERSETMPEND ((uint32_t)0x00000002) /*!< Enables user code to write the Software Trigger Interrupt register to trigger (pend) a Main exception */
+#define SCB_CCR_UNALIGN_TRP ((uint32_t)0x00000008) /*!< Trap for unaligned access */
+#define SCB_CCR_DIV_0_TRP ((uint32_t)0x00000010) /*!< Trap on Divide by 0 */
+#define SCB_CCR_BFHFNMIGN ((uint32_t)0x00000100) /*!< Handlers running at priority -1 and -2 */
+#define SCB_CCR_STKALIGN ((uint32_t)0x00000200) /*!< On exception entry, the SP used prior to the exception is adjusted to be 8-byte aligned */
+
+/******************* Bit definition for SCB_SHPR register ********************/
+#define SCB_SHPR_PRI_N_Pos (0U)
+#define SCB_SHPR_PRI_N_Msk (0xFFU << SCB_SHPR_PRI_N_Pos) /*!< 0x000000FF */
+#define SCB_SHPR_PRI_N SCB_SHPR_PRI_N_Msk /*!< Priority of system handler 4,8, and 12. Mem Manage, reserved and Debug Monitor */
+#define SCB_SHPR_PRI_N1_Pos (8U)
+#define SCB_SHPR_PRI_N1_Msk (0xFFU << SCB_SHPR_PRI_N1_Pos) /*!< 0x0000FF00 */
+#define SCB_SHPR_PRI_N1 SCB_SHPR_PRI_N1_Msk /*!< Priority of system handler 5,9, and 13. Bus Fault, reserved and reserved */
+#define SCB_SHPR_PRI_N2_Pos (16U)
+#define SCB_SHPR_PRI_N2_Msk (0xFFU << SCB_SHPR_PRI_N2_Pos) /*!< 0x00FF0000 */
+#define SCB_SHPR_PRI_N2 SCB_SHPR_PRI_N2_Msk /*!< Priority of system handler 6,10, and 14. Usage Fault, reserved and PendSV */
+#define SCB_SHPR_PRI_N3_Pos (24U)
+#define SCB_SHPR_PRI_N3_Msk (0xFFU << SCB_SHPR_PRI_N3_Pos) /*!< 0xFF000000 */
+#define SCB_SHPR_PRI_N3 SCB_SHPR_PRI_N3_Msk /*!< Priority of system handler 7,11, and 15. Reserved, SVCall and SysTick */
+
+/****************** Bit definition for SCB_SHCSR register *******************/
+#define SCB_SHCSR_MEMFAULTACT ((uint32_t)0x00000001) /*!< MemManage is active */
+#define SCB_SHCSR_BUSFAULTACT ((uint32_t)0x00000002) /*!< BusFault is active */
+#define SCB_SHCSR_USGFAULTACT ((uint32_t)0x00000008) /*!< UsageFault is active */
+#define SCB_SHCSR_SVCALLACT ((uint32_t)0x00000080) /*!< SVCall is active */
+#define SCB_SHCSR_MONITORACT ((uint32_t)0x00000100) /*!< Monitor is active */
+#define SCB_SHCSR_PENDSVACT ((uint32_t)0x00000400) /*!< PendSV is active */
+#define SCB_SHCSR_SYSTICKACT ((uint32_t)0x00000800) /*!< SysTick is active */
+#define SCB_SHCSR_USGFAULTPENDED ((uint32_t)0x00001000) /*!< Usage Fault is pended */
+#define SCB_SHCSR_MEMFAULTPENDED ((uint32_t)0x00002000) /*!< MemManage is pended */
+#define SCB_SHCSR_BUSFAULTPENDED ((uint32_t)0x00004000) /*!< Bus Fault is pended */
+#define SCB_SHCSR_SVCALLPENDED ((uint32_t)0x00008000) /*!< SVCall is pended */
+#define SCB_SHCSR_MEMFAULTENA ((uint32_t)0x00010000) /*!< MemManage enable */
+#define SCB_SHCSR_BUSFAULTENA ((uint32_t)0x00020000) /*!< Bus Fault enable */
+#define SCB_SHCSR_USGFAULTENA ((uint32_t)0x00040000) /*!< UsageFault enable */
+
+/******************* Bit definition for SCB_CFSR register *******************/
+/*!< MFSR */
+#define SCB_CFSR_IACCVIOL_Pos (0U)
+#define SCB_CFSR_IACCVIOL_Msk (0x1U << SCB_CFSR_IACCVIOL_Pos) /*!< 0x00000001 */
+#define SCB_CFSR_IACCVIOL SCB_CFSR_IACCVIOL_Msk /*!< Instruction access violation */
+#define SCB_CFSR_DACCVIOL_Pos (1U)
+#define SCB_CFSR_DACCVIOL_Msk (0x1U << SCB_CFSR_DACCVIOL_Pos) /*!< 0x00000002 */
+#define SCB_CFSR_DACCVIOL SCB_CFSR_DACCVIOL_Msk /*!< Data access violation */
+#define SCB_CFSR_MUNSTKERR_Pos (3U)
+#define SCB_CFSR_MUNSTKERR_Msk (0x1U << SCB_CFSR_MUNSTKERR_Pos) /*!< 0x00000008 */
+#define SCB_CFSR_MUNSTKERR SCB_CFSR_MUNSTKERR_Msk /*!< Unstacking error */
+#define SCB_CFSR_MSTKERR_Pos (4U)
+#define SCB_CFSR_MSTKERR_Msk (0x1U << SCB_CFSR_MSTKERR_Pos) /*!< 0x00000010 */
+#define SCB_CFSR_MSTKERR SCB_CFSR_MSTKERR_Msk /*!< Stacking error */
+#define SCB_CFSR_MMARVALID_Pos (7U)
+#define SCB_CFSR_MMARVALID_Msk (0x1U << SCB_CFSR_MMARVALID_Pos) /*!< 0x00000080 */
+#define SCB_CFSR_MMARVALID SCB_CFSR_MMARVALID_Msk /*!< Memory Manage Address Register address valid flag */
+/*!< BFSR */
+#define SCB_CFSR_IBUSERR_Pos (8U)
+#define SCB_CFSR_IBUSERR_Msk (0x1U << SCB_CFSR_IBUSERR_Pos) /*!< 0x00000100 */
+#define SCB_CFSR_IBUSERR SCB_CFSR_IBUSERR_Msk /*!< Instruction bus error flag */
+#define SCB_CFSR_PRECISERR_Pos (9U)
+#define SCB_CFSR_PRECISERR_Msk (0x1U << SCB_CFSR_PRECISERR_Pos) /*!< 0x00000200 */
+#define SCB_CFSR_PRECISERR SCB_CFSR_PRECISERR_Msk /*!< Precise data bus error */
+#define SCB_CFSR_IMPRECISERR_Pos (10U)
+#define SCB_CFSR_IMPRECISERR_Msk (0x1U << SCB_CFSR_IMPRECISERR_Pos) /*!< 0x00000400 */
+#define SCB_CFSR_IMPRECISERR SCB_CFSR_IMPRECISERR_Msk /*!< Imprecise data bus error */
+#define SCB_CFSR_UNSTKERR_Pos (11U)
+#define SCB_CFSR_UNSTKERR_Msk (0x1U << SCB_CFSR_UNSTKERR_Pos) /*!< 0x00000800 */
+#define SCB_CFSR_UNSTKERR SCB_CFSR_UNSTKERR_Msk /*!< Unstacking error */
+#define SCB_CFSR_STKERR_Pos (12U)
+#define SCB_CFSR_STKERR_Msk (0x1U << SCB_CFSR_STKERR_Pos) /*!< 0x00001000 */
+#define SCB_CFSR_STKERR SCB_CFSR_STKERR_Msk /*!< Stacking error */
+#define SCB_CFSR_BFARVALID_Pos (15U)
+#define SCB_CFSR_BFARVALID_Msk (0x1U << SCB_CFSR_BFARVALID_Pos) /*!< 0x00008000 */
+#define SCB_CFSR_BFARVALID SCB_CFSR_BFARVALID_Msk /*!< Bus Fault Address Register address valid flag */
+/*!< UFSR */
+#define SCB_CFSR_UNDEFINSTR_Pos (16U)
+#define SCB_CFSR_UNDEFINSTR_Msk (0x1U << SCB_CFSR_UNDEFINSTR_Pos) /*!< 0x00010000 */
+#define SCB_CFSR_UNDEFINSTR SCB_CFSR_UNDEFINSTR_Msk /*!< The processor attempt to execute an undefined instruction */
+#define SCB_CFSR_INVSTATE_Pos (17U)
+#define SCB_CFSR_INVSTATE_Msk (0x1U << SCB_CFSR_INVSTATE_Pos) /*!< 0x00020000 */
+#define SCB_CFSR_INVSTATE SCB_CFSR_INVSTATE_Msk /*!< Invalid combination of EPSR and instruction */
+#define SCB_CFSR_INVPC_Pos (18U)
+#define SCB_CFSR_INVPC_Msk (0x1U << SCB_CFSR_INVPC_Pos) /*!< 0x00040000 */
+#define SCB_CFSR_INVPC SCB_CFSR_INVPC_Msk /*!< Attempt to load EXC_RETURN into pc illegally */
+#define SCB_CFSR_NOCP_Pos (19U)
+#define SCB_CFSR_NOCP_Msk (0x1U << SCB_CFSR_NOCP_Pos) /*!< 0x00080000 */
+#define SCB_CFSR_NOCP SCB_CFSR_NOCP_Msk /*!< Attempt to use a coprocessor instruction */
+#define SCB_CFSR_UNALIGNED_Pos (24U)
+#define SCB_CFSR_UNALIGNED_Msk (0x1U << SCB_CFSR_UNALIGNED_Pos) /*!< 0x01000000 */
+#define SCB_CFSR_UNALIGNED SCB_CFSR_UNALIGNED_Msk /*!< Fault occurs when there is an attempt to make an unaligned memory access */
+#define SCB_CFSR_DIVBYZERO_Pos (25U)
+#define SCB_CFSR_DIVBYZERO_Msk (0x1U << SCB_CFSR_DIVBYZERO_Pos) /*!< 0x02000000 */
+#define SCB_CFSR_DIVBYZERO SCB_CFSR_DIVBYZERO_Msk /*!< Fault occurs when SDIV or DIV instruction is used with a divisor of 0 */
+
+/******************* Bit definition for SCB_HFSR register *******************/
+#define SCB_HFSR_VECTTBL ((uint32_t)0x00000002) /*!< Fault occurs because of vector table read on exception processing */
+#define SCB_HFSR_FORCED ((uint32_t)0x40000000) /*!< Hard Fault activated when a configurable Fault was received and cannot activate */
+#define SCB_HFSR_DEBUGEVT ((uint32_t)0x80000000) /*!< Fault related to debug */
+
+/******************* Bit definition for SCB_DFSR register *******************/
+#define SCB_DFSR_HALTED ((uint32_t)0x00000001) /*!< Halt request flag */
+#define SCB_DFSR_BKPT ((uint32_t)0x00000002) /*!< BKPT flag */
+#define SCB_DFSR_DWTTRAP ((uint32_t)0x00000004) /*!< Data Watchpoint and Trace (DWT) flag */
+#define SCB_DFSR_VCATCH ((uint32_t)0x00000008) /*!< Vector catch flag */
+#define SCB_DFSR_EXTERNAL ((uint32_t)0x00000010) /*!< External debug request flag */
+
+/******************* Bit definition for SCB_MMFAR register ******************/
+#define SCB_MMFAR_ADDRESS_Pos (0U)
+#define SCB_MMFAR_ADDRESS_Msk (0xFFFFFFFFU << SCB_MMFAR_ADDRESS_Pos) /*!< 0xFFFFFFFF */
+#define SCB_MMFAR_ADDRESS SCB_MMFAR_ADDRESS_Msk /*!< Mem Manage fault address field */
+
+/******************* Bit definition for SCB_BFAR register *******************/
+#define SCB_BFAR_ADDRESS_Pos (0U)
+#define SCB_BFAR_ADDRESS_Msk (0xFFFFFFFFU << SCB_BFAR_ADDRESS_Pos) /*!< 0xFFFFFFFF */
+#define SCB_BFAR_ADDRESS SCB_BFAR_ADDRESS_Msk /*!< Bus fault address field */
+
+/******************* Bit definition for SCB_afsr register *******************/
+#define SCB_AFSR_IMPDEF_Pos (0U)
+#define SCB_AFSR_IMPDEF_Msk (0xFFFFFFFFU << SCB_AFSR_IMPDEF_Pos) /*!< 0xFFFFFFFF */
+#define SCB_AFSR_IMPDEF SCB_AFSR_IMPDEF_Msk /*!< Implementation defined */
+
+/******************************************************************************/
+/* */
+/* External Interrupt/Event Controller */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for EXTI_IMR register *******************/
+#define EXTI_IMR_MR0_Pos (0U)
+#define EXTI_IMR_MR0_Msk (0x1U << EXTI_IMR_MR0_Pos) /*!< 0x00000001 */
+#define EXTI_IMR_MR0 EXTI_IMR_MR0_Msk /*!< Interrupt Mask on line 0 */
+#define EXTI_IMR_MR1_Pos (1U)
+#define EXTI_IMR_MR1_Msk (0x1U << EXTI_IMR_MR1_Pos) /*!< 0x00000002 */
+#define EXTI_IMR_MR1 EXTI_IMR_MR1_Msk /*!< Interrupt Mask on line 1 */
+#define EXTI_IMR_MR2_Pos (2U)
+#define EXTI_IMR_MR2_Msk (0x1U << EXTI_IMR_MR2_Pos) /*!< 0x00000004 */
+#define EXTI_IMR_MR2 EXTI_IMR_MR2_Msk /*!< Interrupt Mask on line 2 */
+#define EXTI_IMR_MR3_Pos (3U)
+#define EXTI_IMR_MR3_Msk (0x1U << EXTI_IMR_MR3_Pos) /*!< 0x00000008 */
+#define EXTI_IMR_MR3 EXTI_IMR_MR3_Msk /*!< Interrupt Mask on line 3 */
+#define EXTI_IMR_MR4_Pos (4U)
+#define EXTI_IMR_MR4_Msk (0x1U << EXTI_IMR_MR4_Pos) /*!< 0x00000010 */
+#define EXTI_IMR_MR4 EXTI_IMR_MR4_Msk /*!< Interrupt Mask on line 4 */
+#define EXTI_IMR_MR5_Pos (5U)
+#define EXTI_IMR_MR5_Msk (0x1U << EXTI_IMR_MR5_Pos) /*!< 0x00000020 */
+#define EXTI_IMR_MR5 EXTI_IMR_MR5_Msk /*!< Interrupt Mask on line 5 */
+#define EXTI_IMR_MR6_Pos (6U)
+#define EXTI_IMR_MR6_Msk (0x1U << EXTI_IMR_MR6_Pos) /*!< 0x00000040 */
+#define EXTI_IMR_MR6 EXTI_IMR_MR6_Msk /*!< Interrupt Mask on line 6 */
+#define EXTI_IMR_MR7_Pos (7U)
+#define EXTI_IMR_MR7_Msk (0x1U << EXTI_IMR_MR7_Pos) /*!< 0x00000080 */
+#define EXTI_IMR_MR7 EXTI_IMR_MR7_Msk /*!< Interrupt Mask on line 7 */
+#define EXTI_IMR_MR8_Pos (8U)
+#define EXTI_IMR_MR8_Msk (0x1U << EXTI_IMR_MR8_Pos) /*!< 0x00000100 */
+#define EXTI_IMR_MR8 EXTI_IMR_MR8_Msk /*!< Interrupt Mask on line 8 */
+#define EXTI_IMR_MR9_Pos (9U)
+#define EXTI_IMR_MR9_Msk (0x1U << EXTI_IMR_MR9_Pos) /*!< 0x00000200 */
+#define EXTI_IMR_MR9 EXTI_IMR_MR9_Msk /*!< Interrupt Mask on line 9 */
+#define EXTI_IMR_MR10_Pos (10U)
+#define EXTI_IMR_MR10_Msk (0x1U << EXTI_IMR_MR10_Pos) /*!< 0x00000400 */
+#define EXTI_IMR_MR10 EXTI_IMR_MR10_Msk /*!< Interrupt Mask on line 10 */
+#define EXTI_IMR_MR11_Pos (11U)
+#define EXTI_IMR_MR11_Msk (0x1U << EXTI_IMR_MR11_Pos) /*!< 0x00000800 */
+#define EXTI_IMR_MR11 EXTI_IMR_MR11_Msk /*!< Interrupt Mask on line 11 */
+#define EXTI_IMR_MR12_Pos (12U)
+#define EXTI_IMR_MR12_Msk (0x1U << EXTI_IMR_MR12_Pos) /*!< 0x00001000 */
+#define EXTI_IMR_MR12 EXTI_IMR_MR12_Msk /*!< Interrupt Mask on line 12 */
+#define EXTI_IMR_MR13_Pos (13U)
+#define EXTI_IMR_MR13_Msk (0x1U << EXTI_IMR_MR13_Pos) /*!< 0x00002000 */
+#define EXTI_IMR_MR13 EXTI_IMR_MR13_Msk /*!< Interrupt Mask on line 13 */
+#define EXTI_IMR_MR14_Pos (14U)
+#define EXTI_IMR_MR14_Msk (0x1U << EXTI_IMR_MR14_Pos) /*!< 0x00004000 */
+#define EXTI_IMR_MR14 EXTI_IMR_MR14_Msk /*!< Interrupt Mask on line 14 */
+#define EXTI_IMR_MR15_Pos (15U)
+#define EXTI_IMR_MR15_Msk (0x1U << EXTI_IMR_MR15_Pos) /*!< 0x00008000 */
+#define EXTI_IMR_MR15 EXTI_IMR_MR15_Msk /*!< Interrupt Mask on line 15 */
+#define EXTI_IMR_MR16_Pos (16U)
+#define EXTI_IMR_MR16_Msk (0x1U << EXTI_IMR_MR16_Pos) /*!< 0x00010000 */
+#define EXTI_IMR_MR16 EXTI_IMR_MR16_Msk /*!< Interrupt Mask on line 16 */
+#define EXTI_IMR_MR17_Pos (17U)
+#define EXTI_IMR_MR17_Msk (0x1U << EXTI_IMR_MR17_Pos) /*!< 0x00020000 */
+#define EXTI_IMR_MR17 EXTI_IMR_MR17_Msk /*!< Interrupt Mask on line 17 */
+#define EXTI_IMR_MR18_Pos (18U)
+#define EXTI_IMR_MR18_Msk (0x1U << EXTI_IMR_MR18_Pos) /*!< 0x00040000 */
+#define EXTI_IMR_MR18 EXTI_IMR_MR18_Msk /*!< Interrupt Mask on line 18 */
+#define EXTI_IMR_MR19_Pos (19U)
+#define EXTI_IMR_MR19_Msk (0x1U << EXTI_IMR_MR19_Pos) /*!< 0x00080000 */
+#define EXTI_IMR_MR19 EXTI_IMR_MR19_Msk /*!< Interrupt Mask on line 19 */
+
+/* References Defines */
+#define EXTI_IMR_IM0 EXTI_IMR_MR0
+#define EXTI_IMR_IM1 EXTI_IMR_MR1
+#define EXTI_IMR_IM2 EXTI_IMR_MR2
+#define EXTI_IMR_IM3 EXTI_IMR_MR3
+#define EXTI_IMR_IM4 EXTI_IMR_MR4
+#define EXTI_IMR_IM5 EXTI_IMR_MR5
+#define EXTI_IMR_IM6 EXTI_IMR_MR6
+#define EXTI_IMR_IM7 EXTI_IMR_MR7
+#define EXTI_IMR_IM8 EXTI_IMR_MR8
+#define EXTI_IMR_IM9 EXTI_IMR_MR9
+#define EXTI_IMR_IM10 EXTI_IMR_MR10
+#define EXTI_IMR_IM11 EXTI_IMR_MR11
+#define EXTI_IMR_IM12 EXTI_IMR_MR12
+#define EXTI_IMR_IM13 EXTI_IMR_MR13
+#define EXTI_IMR_IM14 EXTI_IMR_MR14
+#define EXTI_IMR_IM15 EXTI_IMR_MR15
+#define EXTI_IMR_IM16 EXTI_IMR_MR16
+#define EXTI_IMR_IM17 EXTI_IMR_MR17
+#define EXTI_IMR_IM18 EXTI_IMR_MR18
+#define EXTI_IMR_IM19 EXTI_IMR_MR19
+
+/******************* Bit definition for EXTI_EMR register *******************/
+#define EXTI_EMR_MR0_Pos (0U)
+#define EXTI_EMR_MR0_Msk (0x1U << EXTI_EMR_MR0_Pos) /*!< 0x00000001 */
+#define EXTI_EMR_MR0 EXTI_EMR_MR0_Msk /*!< Event Mask on line 0 */
+#define EXTI_EMR_MR1_Pos (1U)
+#define EXTI_EMR_MR1_Msk (0x1U << EXTI_EMR_MR1_Pos) /*!< 0x00000002 */
+#define EXTI_EMR_MR1 EXTI_EMR_MR1_Msk /*!< Event Mask on line 1 */
+#define EXTI_EMR_MR2_Pos (2U)
+#define EXTI_EMR_MR2_Msk (0x1U << EXTI_EMR_MR2_Pos) /*!< 0x00000004 */
+#define EXTI_EMR_MR2 EXTI_EMR_MR2_Msk /*!< Event Mask on line 2 */
+#define EXTI_EMR_MR3_Pos (3U)
+#define EXTI_EMR_MR3_Msk (0x1U << EXTI_EMR_MR3_Pos) /*!< 0x00000008 */
+#define EXTI_EMR_MR3 EXTI_EMR_MR3_Msk /*!< Event Mask on line 3 */
+#define EXTI_EMR_MR4_Pos (4U)
+#define EXTI_EMR_MR4_Msk (0x1U << EXTI_EMR_MR4_Pos) /*!< 0x00000010 */
+#define EXTI_EMR_MR4 EXTI_EMR_MR4_Msk /*!< Event Mask on line 4 */
+#define EXTI_EMR_MR5_Pos (5U)
+#define EXTI_EMR_MR5_Msk (0x1U << EXTI_EMR_MR5_Pos) /*!< 0x00000020 */
+#define EXTI_EMR_MR5 EXTI_EMR_MR5_Msk /*!< Event Mask on line 5 */
+#define EXTI_EMR_MR6_Pos (6U)
+#define EXTI_EMR_MR6_Msk (0x1U << EXTI_EMR_MR6_Pos) /*!< 0x00000040 */
+#define EXTI_EMR_MR6 EXTI_EMR_MR6_Msk /*!< Event Mask on line 6 */
+#define EXTI_EMR_MR7_Pos (7U)
+#define EXTI_EMR_MR7_Msk (0x1U << EXTI_EMR_MR7_Pos) /*!< 0x00000080 */
+#define EXTI_EMR_MR7 EXTI_EMR_MR7_Msk /*!< Event Mask on line 7 */
+#define EXTI_EMR_MR8_Pos (8U)
+#define EXTI_EMR_MR8_Msk (0x1U << EXTI_EMR_MR8_Pos) /*!< 0x00000100 */
+#define EXTI_EMR_MR8 EXTI_EMR_MR8_Msk /*!< Event Mask on line 8 */
+#define EXTI_EMR_MR9_Pos (9U)
+#define EXTI_EMR_MR9_Msk (0x1U << EXTI_EMR_MR9_Pos) /*!< 0x00000200 */
+#define EXTI_EMR_MR9 EXTI_EMR_MR9_Msk /*!< Event Mask on line 9 */
+#define EXTI_EMR_MR10_Pos (10U)
+#define EXTI_EMR_MR10_Msk (0x1U << EXTI_EMR_MR10_Pos) /*!< 0x00000400 */
+#define EXTI_EMR_MR10 EXTI_EMR_MR10_Msk /*!< Event Mask on line 10 */
+#define EXTI_EMR_MR11_Pos (11U)
+#define EXTI_EMR_MR11_Msk (0x1U << EXTI_EMR_MR11_Pos) /*!< 0x00000800 */
+#define EXTI_EMR_MR11 EXTI_EMR_MR11_Msk /*!< Event Mask on line 11 */
+#define EXTI_EMR_MR12_Pos (12U)
+#define EXTI_EMR_MR12_Msk (0x1U << EXTI_EMR_MR12_Pos) /*!< 0x00001000 */
+#define EXTI_EMR_MR12 EXTI_EMR_MR12_Msk /*!< Event Mask on line 12 */
+#define EXTI_EMR_MR13_Pos (13U)
+#define EXTI_EMR_MR13_Msk (0x1U << EXTI_EMR_MR13_Pos) /*!< 0x00002000 */
+#define EXTI_EMR_MR13 EXTI_EMR_MR13_Msk /*!< Event Mask on line 13 */
+#define EXTI_EMR_MR14_Pos (14U)
+#define EXTI_EMR_MR14_Msk (0x1U << EXTI_EMR_MR14_Pos) /*!< 0x00004000 */
+#define EXTI_EMR_MR14 EXTI_EMR_MR14_Msk /*!< Event Mask on line 14 */
+#define EXTI_EMR_MR15_Pos (15U)
+#define EXTI_EMR_MR15_Msk (0x1U << EXTI_EMR_MR15_Pos) /*!< 0x00008000 */
+#define EXTI_EMR_MR15 EXTI_EMR_MR15_Msk /*!< Event Mask on line 15 */
+#define EXTI_EMR_MR16_Pos (16U)
+#define EXTI_EMR_MR16_Msk (0x1U << EXTI_EMR_MR16_Pos) /*!< 0x00010000 */
+#define EXTI_EMR_MR16 EXTI_EMR_MR16_Msk /*!< Event Mask on line 16 */
+#define EXTI_EMR_MR17_Pos (17U)
+#define EXTI_EMR_MR17_Msk (0x1U << EXTI_EMR_MR17_Pos) /*!< 0x00020000 */
+#define EXTI_EMR_MR17 EXTI_EMR_MR17_Msk /*!< Event Mask on line 17 */
+#define EXTI_EMR_MR18_Pos (18U)
+#define EXTI_EMR_MR18_Msk (0x1U << EXTI_EMR_MR18_Pos) /*!< 0x00040000 */
+#define EXTI_EMR_MR18 EXTI_EMR_MR18_Msk /*!< Event Mask on line 18 */
+#define EXTI_EMR_MR19_Pos (19U)
+#define EXTI_EMR_MR19_Msk (0x1U << EXTI_EMR_MR19_Pos) /*!< 0x00080000 */
+#define EXTI_EMR_MR19 EXTI_EMR_MR19_Msk /*!< Event Mask on line 19 */
+
+/* References Defines */
+#define EXTI_EMR_EM0 EXTI_EMR_MR0
+#define EXTI_EMR_EM1 EXTI_EMR_MR1
+#define EXTI_EMR_EM2 EXTI_EMR_MR2
+#define EXTI_EMR_EM3 EXTI_EMR_MR3
+#define EXTI_EMR_EM4 EXTI_EMR_MR4
+#define EXTI_EMR_EM5 EXTI_EMR_MR5
+#define EXTI_EMR_EM6 EXTI_EMR_MR6
+#define EXTI_EMR_EM7 EXTI_EMR_MR7
+#define EXTI_EMR_EM8 EXTI_EMR_MR8
+#define EXTI_EMR_EM9 EXTI_EMR_MR9
+#define EXTI_EMR_EM10 EXTI_EMR_MR10
+#define EXTI_EMR_EM11 EXTI_EMR_MR11
+#define EXTI_EMR_EM12 EXTI_EMR_MR12
+#define EXTI_EMR_EM13 EXTI_EMR_MR13
+#define EXTI_EMR_EM14 EXTI_EMR_MR14
+#define EXTI_EMR_EM15 EXTI_EMR_MR15
+#define EXTI_EMR_EM16 EXTI_EMR_MR16
+#define EXTI_EMR_EM17 EXTI_EMR_MR17
+#define EXTI_EMR_EM18 EXTI_EMR_MR18
+#define EXTI_EMR_EM19 EXTI_EMR_MR19
+
+/****************** Bit definition for EXTI_RTSR register *******************/
+#define EXTI_RTSR_TR0_Pos (0U)
+#define EXTI_RTSR_TR0_Msk (0x1U << EXTI_RTSR_TR0_Pos) /*!< 0x00000001 */
+#define EXTI_RTSR_TR0 EXTI_RTSR_TR0_Msk /*!< Rising trigger event configuration bit of line 0 */
+#define EXTI_RTSR_TR1_Pos (1U)
+#define EXTI_RTSR_TR1_Msk (0x1U << EXTI_RTSR_TR1_Pos) /*!< 0x00000002 */
+#define EXTI_RTSR_TR1 EXTI_RTSR_TR1_Msk /*!< Rising trigger event configuration bit of line 1 */
+#define EXTI_RTSR_TR2_Pos (2U)
+#define EXTI_RTSR_TR2_Msk (0x1U << EXTI_RTSR_TR2_Pos) /*!< 0x00000004 */
+#define EXTI_RTSR_TR2 EXTI_RTSR_TR2_Msk /*!< Rising trigger event configuration bit of line 2 */
+#define EXTI_RTSR_TR3_Pos (3U)
+#define EXTI_RTSR_TR3_Msk (0x1U << EXTI_RTSR_TR3_Pos) /*!< 0x00000008 */
+#define EXTI_RTSR_TR3 EXTI_RTSR_TR3_Msk /*!< Rising trigger event configuration bit of line 3 */
+#define EXTI_RTSR_TR4_Pos (4U)
+#define EXTI_RTSR_TR4_Msk (0x1U << EXTI_RTSR_TR4_Pos) /*!< 0x00000010 */
+#define EXTI_RTSR_TR4 EXTI_RTSR_TR4_Msk /*!< Rising trigger event configuration bit of line 4 */
+#define EXTI_RTSR_TR5_Pos (5U)
+#define EXTI_RTSR_TR5_Msk (0x1U << EXTI_RTSR_TR5_Pos) /*!< 0x00000020 */
+#define EXTI_RTSR_TR5 EXTI_RTSR_TR5_Msk /*!< Rising trigger event configuration bit of line 5 */
+#define EXTI_RTSR_TR6_Pos (6U)
+#define EXTI_RTSR_TR6_Msk (0x1U << EXTI_RTSR_TR6_Pos) /*!< 0x00000040 */
+#define EXTI_RTSR_TR6 EXTI_RTSR_TR6_Msk /*!< Rising trigger event configuration bit of line 6 */
+#define EXTI_RTSR_TR7_Pos (7U)
+#define EXTI_RTSR_TR7_Msk (0x1U << EXTI_RTSR_TR7_Pos) /*!< 0x00000080 */
+#define EXTI_RTSR_TR7 EXTI_RTSR_TR7_Msk /*!< Rising trigger event configuration bit of line 7 */
+#define EXTI_RTSR_TR8_Pos (8U)
+#define EXTI_RTSR_TR8_Msk (0x1U << EXTI_RTSR_TR8_Pos) /*!< 0x00000100 */
+#define EXTI_RTSR_TR8 EXTI_RTSR_TR8_Msk /*!< Rising trigger event configuration bit of line 8 */
+#define EXTI_RTSR_TR9_Pos (9U)
+#define EXTI_RTSR_TR9_Msk (0x1U << EXTI_RTSR_TR9_Pos) /*!< 0x00000200 */
+#define EXTI_RTSR_TR9 EXTI_RTSR_TR9_Msk /*!< Rising trigger event configuration bit of line 9 */
+#define EXTI_RTSR_TR10_Pos (10U)
+#define EXTI_RTSR_TR10_Msk (0x1U << EXTI_RTSR_TR10_Pos) /*!< 0x00000400 */
+#define EXTI_RTSR_TR10 EXTI_RTSR_TR10_Msk /*!< Rising trigger event configuration bit of line 10 */
+#define EXTI_RTSR_TR11_Pos (11U)
+#define EXTI_RTSR_TR11_Msk (0x1U << EXTI_RTSR_TR11_Pos) /*!< 0x00000800 */
+#define EXTI_RTSR_TR11 EXTI_RTSR_TR11_Msk /*!< Rising trigger event configuration bit of line 11 */
+#define EXTI_RTSR_TR12_Pos (12U)
+#define EXTI_RTSR_TR12_Msk (0x1U << EXTI_RTSR_TR12_Pos) /*!< 0x00001000 */
+#define EXTI_RTSR_TR12 EXTI_RTSR_TR12_Msk /*!< Rising trigger event configuration bit of line 12 */
+#define EXTI_RTSR_TR13_Pos (13U)
+#define EXTI_RTSR_TR13_Msk (0x1U << EXTI_RTSR_TR13_Pos) /*!< 0x00002000 */
+#define EXTI_RTSR_TR13 EXTI_RTSR_TR13_Msk /*!< Rising trigger event configuration bit of line 13 */
+#define EXTI_RTSR_TR14_Pos (14U)
+#define EXTI_RTSR_TR14_Msk (0x1U << EXTI_RTSR_TR14_Pos) /*!< 0x00004000 */
+#define EXTI_RTSR_TR14 EXTI_RTSR_TR14_Msk /*!< Rising trigger event configuration bit of line 14 */
+#define EXTI_RTSR_TR15_Pos (15U)
+#define EXTI_RTSR_TR15_Msk (0x1U << EXTI_RTSR_TR15_Pos) /*!< 0x00008000 */
+#define EXTI_RTSR_TR15 EXTI_RTSR_TR15_Msk /*!< Rising trigger event configuration bit of line 15 */
+#define EXTI_RTSR_TR16_Pos (16U)
+#define EXTI_RTSR_TR16_Msk (0x1U << EXTI_RTSR_TR16_Pos) /*!< 0x00010000 */
+#define EXTI_RTSR_TR16 EXTI_RTSR_TR16_Msk /*!< Rising trigger event configuration bit of line 16 */
+#define EXTI_RTSR_TR17_Pos (17U)
+#define EXTI_RTSR_TR17_Msk (0x1U << EXTI_RTSR_TR17_Pos) /*!< 0x00020000 */
+#define EXTI_RTSR_TR17 EXTI_RTSR_TR17_Msk /*!< Rising trigger event configuration bit of line 17 */
+#define EXTI_RTSR_TR18_Pos (18U)
+#define EXTI_RTSR_TR18_Msk (0x1U << EXTI_RTSR_TR18_Pos) /*!< 0x00040000 */
+#define EXTI_RTSR_TR18 EXTI_RTSR_TR18_Msk /*!< Rising trigger event configuration bit of line 18 */
+#define EXTI_RTSR_TR19_Pos (19U)
+#define EXTI_RTSR_TR19_Msk (0x1U << EXTI_RTSR_TR19_Pos) /*!< 0x00080000 */
+#define EXTI_RTSR_TR19 EXTI_RTSR_TR19_Msk /*!< Rising trigger event configuration bit of line 19 */
+
+/* References Defines */
+#define EXTI_RTSR_RT0 EXTI_RTSR_TR0
+#define EXTI_RTSR_RT1 EXTI_RTSR_TR1
+#define EXTI_RTSR_RT2 EXTI_RTSR_TR2
+#define EXTI_RTSR_RT3 EXTI_RTSR_TR3
+#define EXTI_RTSR_RT4 EXTI_RTSR_TR4
+#define EXTI_RTSR_RT5 EXTI_RTSR_TR5
+#define EXTI_RTSR_RT6 EXTI_RTSR_TR6
+#define EXTI_RTSR_RT7 EXTI_RTSR_TR7
+#define EXTI_RTSR_RT8 EXTI_RTSR_TR8
+#define EXTI_RTSR_RT9 EXTI_RTSR_TR9
+#define EXTI_RTSR_RT10 EXTI_RTSR_TR10
+#define EXTI_RTSR_RT11 EXTI_RTSR_TR11
+#define EXTI_RTSR_RT12 EXTI_RTSR_TR12
+#define EXTI_RTSR_RT13 EXTI_RTSR_TR13
+#define EXTI_RTSR_RT14 EXTI_RTSR_TR14
+#define EXTI_RTSR_RT15 EXTI_RTSR_TR15
+#define EXTI_RTSR_RT16 EXTI_RTSR_TR16
+#define EXTI_RTSR_RT17 EXTI_RTSR_TR17
+#define EXTI_RTSR_RT18 EXTI_RTSR_TR18
+#define EXTI_RTSR_RT19 EXTI_RTSR_TR19
+
+/****************** Bit definition for EXTI_FTSR register *******************/
+#define EXTI_FTSR_TR0_Pos (0U)
+#define EXTI_FTSR_TR0_Msk (0x1U << EXTI_FTSR_TR0_Pos) /*!< 0x00000001 */
+#define EXTI_FTSR_TR0 EXTI_FTSR_TR0_Msk /*!< Falling trigger event configuration bit of line 0 */
+#define EXTI_FTSR_TR1_Pos (1U)
+#define EXTI_FTSR_TR1_Msk (0x1U << EXTI_FTSR_TR1_Pos) /*!< 0x00000002 */
+#define EXTI_FTSR_TR1 EXTI_FTSR_TR1_Msk /*!< Falling trigger event configuration bit of line 1 */
+#define EXTI_FTSR_TR2_Pos (2U)
+#define EXTI_FTSR_TR2_Msk (0x1U << EXTI_FTSR_TR2_Pos) /*!< 0x00000004 */
+#define EXTI_FTSR_TR2 EXTI_FTSR_TR2_Msk /*!< Falling trigger event configuration bit of line 2 */
+#define EXTI_FTSR_TR3_Pos (3U)
+#define EXTI_FTSR_TR3_Msk (0x1U << EXTI_FTSR_TR3_Pos) /*!< 0x00000008 */
+#define EXTI_FTSR_TR3 EXTI_FTSR_TR3_Msk /*!< Falling trigger event configuration bit of line 3 */
+#define EXTI_FTSR_TR4_Pos (4U)
+#define EXTI_FTSR_TR4_Msk (0x1U << EXTI_FTSR_TR4_Pos) /*!< 0x00000010 */
+#define EXTI_FTSR_TR4 EXTI_FTSR_TR4_Msk /*!< Falling trigger event configuration bit of line 4 */
+#define EXTI_FTSR_TR5_Pos (5U)
+#define EXTI_FTSR_TR5_Msk (0x1U << EXTI_FTSR_TR5_Pos) /*!< 0x00000020 */
+#define EXTI_FTSR_TR5 EXTI_FTSR_TR5_Msk /*!< Falling trigger event configuration bit of line 5 */
+#define EXTI_FTSR_TR6_Pos (6U)
+#define EXTI_FTSR_TR6_Msk (0x1U << EXTI_FTSR_TR6_Pos) /*!< 0x00000040 */
+#define EXTI_FTSR_TR6 EXTI_FTSR_TR6_Msk /*!< Falling trigger event configuration bit of line 6 */
+#define EXTI_FTSR_TR7_Pos (7U)
+#define EXTI_FTSR_TR7_Msk (0x1U << EXTI_FTSR_TR7_Pos) /*!< 0x00000080 */
+#define EXTI_FTSR_TR7 EXTI_FTSR_TR7_Msk /*!< Falling trigger event configuration bit of line 7 */
+#define EXTI_FTSR_TR8_Pos (8U)
+#define EXTI_FTSR_TR8_Msk (0x1U << EXTI_FTSR_TR8_Pos) /*!< 0x00000100 */
+#define EXTI_FTSR_TR8 EXTI_FTSR_TR8_Msk /*!< Falling trigger event configuration bit of line 8 */
+#define EXTI_FTSR_TR9_Pos (9U)
+#define EXTI_FTSR_TR9_Msk (0x1U << EXTI_FTSR_TR9_Pos) /*!< 0x00000200 */
+#define EXTI_FTSR_TR9 EXTI_FTSR_TR9_Msk /*!< Falling trigger event configuration bit of line 9 */
+#define EXTI_FTSR_TR10_Pos (10U)
+#define EXTI_FTSR_TR10_Msk (0x1U << EXTI_FTSR_TR10_Pos) /*!< 0x00000400 */
+#define EXTI_FTSR_TR10 EXTI_FTSR_TR10_Msk /*!< Falling trigger event configuration bit of line 10 */
+#define EXTI_FTSR_TR11_Pos (11U)
+#define EXTI_FTSR_TR11_Msk (0x1U << EXTI_FTSR_TR11_Pos) /*!< 0x00000800 */
+#define EXTI_FTSR_TR11 EXTI_FTSR_TR11_Msk /*!< Falling trigger event configuration bit of line 11 */
+#define EXTI_FTSR_TR12_Pos (12U)
+#define EXTI_FTSR_TR12_Msk (0x1U << EXTI_FTSR_TR12_Pos) /*!< 0x00001000 */
+#define EXTI_FTSR_TR12 EXTI_FTSR_TR12_Msk /*!< Falling trigger event configuration bit of line 12 */
+#define EXTI_FTSR_TR13_Pos (13U)
+#define EXTI_FTSR_TR13_Msk (0x1U << EXTI_FTSR_TR13_Pos) /*!< 0x00002000 */
+#define EXTI_FTSR_TR13 EXTI_FTSR_TR13_Msk /*!< Falling trigger event configuration bit of line 13 */
+#define EXTI_FTSR_TR14_Pos (14U)
+#define EXTI_FTSR_TR14_Msk (0x1U << EXTI_FTSR_TR14_Pos) /*!< 0x00004000 */
+#define EXTI_FTSR_TR14 EXTI_FTSR_TR14_Msk /*!< Falling trigger event configuration bit of line 14 */
+#define EXTI_FTSR_TR15_Pos (15U)
+#define EXTI_FTSR_TR15_Msk (0x1U << EXTI_FTSR_TR15_Pos) /*!< 0x00008000 */
+#define EXTI_FTSR_TR15 EXTI_FTSR_TR15_Msk /*!< Falling trigger event configuration bit of line 15 */
+#define EXTI_FTSR_TR16_Pos (16U)
+#define EXTI_FTSR_TR16_Msk (0x1U << EXTI_FTSR_TR16_Pos) /*!< 0x00010000 */
+#define EXTI_FTSR_TR16 EXTI_FTSR_TR16_Msk /*!< Falling trigger event configuration bit of line 16 */
+#define EXTI_FTSR_TR17_Pos (17U)
+#define EXTI_FTSR_TR17_Msk (0x1U << EXTI_FTSR_TR17_Pos) /*!< 0x00020000 */
+#define EXTI_FTSR_TR17 EXTI_FTSR_TR17_Msk /*!< Falling trigger event configuration bit of line 17 */
+#define EXTI_FTSR_TR18_Pos (18U)
+#define EXTI_FTSR_TR18_Msk (0x1U << EXTI_FTSR_TR18_Pos) /*!< 0x00040000 */
+#define EXTI_FTSR_TR18 EXTI_FTSR_TR18_Msk /*!< Falling trigger event configuration bit of line 18 */
+#define EXTI_FTSR_TR19_Pos (19U)
+#define EXTI_FTSR_TR19_Msk (0x1U << EXTI_FTSR_TR19_Pos) /*!< 0x00080000 */
+#define EXTI_FTSR_TR19 EXTI_FTSR_TR19_Msk /*!< Falling trigger event configuration bit of line 19 */
+
+/* References Defines */
+#define EXTI_FTSR_FT0 EXTI_FTSR_TR0
+#define EXTI_FTSR_FT1 EXTI_FTSR_TR1
+#define EXTI_FTSR_FT2 EXTI_FTSR_TR2
+#define EXTI_FTSR_FT3 EXTI_FTSR_TR3
+#define EXTI_FTSR_FT4 EXTI_FTSR_TR4
+#define EXTI_FTSR_FT5 EXTI_FTSR_TR5
+#define EXTI_FTSR_FT6 EXTI_FTSR_TR6
+#define EXTI_FTSR_FT7 EXTI_FTSR_TR7
+#define EXTI_FTSR_FT8 EXTI_FTSR_TR8
+#define EXTI_FTSR_FT9 EXTI_FTSR_TR9
+#define EXTI_FTSR_FT10 EXTI_FTSR_TR10
+#define EXTI_FTSR_FT11 EXTI_FTSR_TR11
+#define EXTI_FTSR_FT12 EXTI_FTSR_TR12
+#define EXTI_FTSR_FT13 EXTI_FTSR_TR13
+#define EXTI_FTSR_FT14 EXTI_FTSR_TR14
+#define EXTI_FTSR_FT15 EXTI_FTSR_TR15
+#define EXTI_FTSR_FT16 EXTI_FTSR_TR16
+#define EXTI_FTSR_FT17 EXTI_FTSR_TR17
+#define EXTI_FTSR_FT18 EXTI_FTSR_TR18
+#define EXTI_FTSR_FT19 EXTI_FTSR_TR19
+
+/****************** Bit definition for EXTI_SWIER register ******************/
+#define EXTI_SWIER_SWIER0_Pos (0U)
+#define EXTI_SWIER_SWIER0_Msk (0x1U << EXTI_SWIER_SWIER0_Pos) /*!< 0x00000001 */
+#define EXTI_SWIER_SWIER0 EXTI_SWIER_SWIER0_Msk /*!< Software Interrupt on line 0 */
+#define EXTI_SWIER_SWIER1_Pos (1U)
+#define EXTI_SWIER_SWIER1_Msk (0x1U << EXTI_SWIER_SWIER1_Pos) /*!< 0x00000002 */
+#define EXTI_SWIER_SWIER1 EXTI_SWIER_SWIER1_Msk /*!< Software Interrupt on line 1 */
+#define EXTI_SWIER_SWIER2_Pos (2U)
+#define EXTI_SWIER_SWIER2_Msk (0x1U << EXTI_SWIER_SWIER2_Pos) /*!< 0x00000004 */
+#define EXTI_SWIER_SWIER2 EXTI_SWIER_SWIER2_Msk /*!< Software Interrupt on line 2 */
+#define EXTI_SWIER_SWIER3_Pos (3U)
+#define EXTI_SWIER_SWIER3_Msk (0x1U << EXTI_SWIER_SWIER3_Pos) /*!< 0x00000008 */
+#define EXTI_SWIER_SWIER3 EXTI_SWIER_SWIER3_Msk /*!< Software Interrupt on line 3 */
+#define EXTI_SWIER_SWIER4_Pos (4U)
+#define EXTI_SWIER_SWIER4_Msk (0x1U << EXTI_SWIER_SWIER4_Pos) /*!< 0x00000010 */
+#define EXTI_SWIER_SWIER4 EXTI_SWIER_SWIER4_Msk /*!< Software Interrupt on line 4 */
+#define EXTI_SWIER_SWIER5_Pos (5U)
+#define EXTI_SWIER_SWIER5_Msk (0x1U << EXTI_SWIER_SWIER5_Pos) /*!< 0x00000020 */
+#define EXTI_SWIER_SWIER5 EXTI_SWIER_SWIER5_Msk /*!< Software Interrupt on line 5 */
+#define EXTI_SWIER_SWIER6_Pos (6U)
+#define EXTI_SWIER_SWIER6_Msk (0x1U << EXTI_SWIER_SWIER6_Pos) /*!< 0x00000040 */
+#define EXTI_SWIER_SWIER6 EXTI_SWIER_SWIER6_Msk /*!< Software Interrupt on line 6 */
+#define EXTI_SWIER_SWIER7_Pos (7U)
+#define EXTI_SWIER_SWIER7_Msk (0x1U << EXTI_SWIER_SWIER7_Pos) /*!< 0x00000080 */
+#define EXTI_SWIER_SWIER7 EXTI_SWIER_SWIER7_Msk /*!< Software Interrupt on line 7 */
+#define EXTI_SWIER_SWIER8_Pos (8U)
+#define EXTI_SWIER_SWIER8_Msk (0x1U << EXTI_SWIER_SWIER8_Pos) /*!< 0x00000100 */
+#define EXTI_SWIER_SWIER8 EXTI_SWIER_SWIER8_Msk /*!< Software Interrupt on line 8 */
+#define EXTI_SWIER_SWIER9_Pos (9U)
+#define EXTI_SWIER_SWIER9_Msk (0x1U << EXTI_SWIER_SWIER9_Pos) /*!< 0x00000200 */
+#define EXTI_SWIER_SWIER9 EXTI_SWIER_SWIER9_Msk /*!< Software Interrupt on line 9 */
+#define EXTI_SWIER_SWIER10_Pos (10U)
+#define EXTI_SWIER_SWIER10_Msk (0x1U << EXTI_SWIER_SWIER10_Pos) /*!< 0x00000400 */
+#define EXTI_SWIER_SWIER10 EXTI_SWIER_SWIER10_Msk /*!< Software Interrupt on line 10 */
+#define EXTI_SWIER_SWIER11_Pos (11U)
+#define EXTI_SWIER_SWIER11_Msk (0x1U << EXTI_SWIER_SWIER11_Pos) /*!< 0x00000800 */
+#define EXTI_SWIER_SWIER11 EXTI_SWIER_SWIER11_Msk /*!< Software Interrupt on line 11 */
+#define EXTI_SWIER_SWIER12_Pos (12U)
+#define EXTI_SWIER_SWIER12_Msk (0x1U << EXTI_SWIER_SWIER12_Pos) /*!< 0x00001000 */
+#define EXTI_SWIER_SWIER12 EXTI_SWIER_SWIER12_Msk /*!< Software Interrupt on line 12 */
+#define EXTI_SWIER_SWIER13_Pos (13U)
+#define EXTI_SWIER_SWIER13_Msk (0x1U << EXTI_SWIER_SWIER13_Pos) /*!< 0x00002000 */
+#define EXTI_SWIER_SWIER13 EXTI_SWIER_SWIER13_Msk /*!< Software Interrupt on line 13 */
+#define EXTI_SWIER_SWIER14_Pos (14U)
+#define EXTI_SWIER_SWIER14_Msk (0x1U << EXTI_SWIER_SWIER14_Pos) /*!< 0x00004000 */
+#define EXTI_SWIER_SWIER14 EXTI_SWIER_SWIER14_Msk /*!< Software Interrupt on line 14 */
+#define EXTI_SWIER_SWIER15_Pos (15U)
+#define EXTI_SWIER_SWIER15_Msk (0x1U << EXTI_SWIER_SWIER15_Pos) /*!< 0x00008000 */
+#define EXTI_SWIER_SWIER15 EXTI_SWIER_SWIER15_Msk /*!< Software Interrupt on line 15 */
+#define EXTI_SWIER_SWIER16_Pos (16U)
+#define EXTI_SWIER_SWIER16_Msk (0x1U << EXTI_SWIER_SWIER16_Pos) /*!< 0x00010000 */
+#define EXTI_SWIER_SWIER16 EXTI_SWIER_SWIER16_Msk /*!< Software Interrupt on line 16 */
+#define EXTI_SWIER_SWIER17_Pos (17U)
+#define EXTI_SWIER_SWIER17_Msk (0x1U << EXTI_SWIER_SWIER17_Pos) /*!< 0x00020000 */
+#define EXTI_SWIER_SWIER17 EXTI_SWIER_SWIER17_Msk /*!< Software Interrupt on line 17 */
+#define EXTI_SWIER_SWIER18_Pos (18U)
+#define EXTI_SWIER_SWIER18_Msk (0x1U << EXTI_SWIER_SWIER18_Pos) /*!< 0x00040000 */
+#define EXTI_SWIER_SWIER18 EXTI_SWIER_SWIER18_Msk /*!< Software Interrupt on line 18 */
+#define EXTI_SWIER_SWIER19_Pos (19U)
+#define EXTI_SWIER_SWIER19_Msk (0x1U << EXTI_SWIER_SWIER19_Pos) /*!< 0x00080000 */
+#define EXTI_SWIER_SWIER19 EXTI_SWIER_SWIER19_Msk /*!< Software Interrupt on line 19 */
+
+/* References Defines */
+#define EXTI_SWIER_SWI0 EXTI_SWIER_SWIER0
+#define EXTI_SWIER_SWI1 EXTI_SWIER_SWIER1
+#define EXTI_SWIER_SWI2 EXTI_SWIER_SWIER2
+#define EXTI_SWIER_SWI3 EXTI_SWIER_SWIER3
+#define EXTI_SWIER_SWI4 EXTI_SWIER_SWIER4
+#define EXTI_SWIER_SWI5 EXTI_SWIER_SWIER5
+#define EXTI_SWIER_SWI6 EXTI_SWIER_SWIER6
+#define EXTI_SWIER_SWI7 EXTI_SWIER_SWIER7
+#define EXTI_SWIER_SWI8 EXTI_SWIER_SWIER8
+#define EXTI_SWIER_SWI9 EXTI_SWIER_SWIER9
+#define EXTI_SWIER_SWI10 EXTI_SWIER_SWIER10
+#define EXTI_SWIER_SWI11 EXTI_SWIER_SWIER11
+#define EXTI_SWIER_SWI12 EXTI_SWIER_SWIER12
+#define EXTI_SWIER_SWI13 EXTI_SWIER_SWIER13
+#define EXTI_SWIER_SWI14 EXTI_SWIER_SWIER14
+#define EXTI_SWIER_SWI15 EXTI_SWIER_SWIER15
+#define EXTI_SWIER_SWI16 EXTI_SWIER_SWIER16
+#define EXTI_SWIER_SWI17 EXTI_SWIER_SWIER17
+#define EXTI_SWIER_SWI18 EXTI_SWIER_SWIER18
+#define EXTI_SWIER_SWI19 EXTI_SWIER_SWIER19
+
+/******************* Bit definition for EXTI_PR register ********************/
+#define EXTI_PR_PR0_Pos (0U)
+#define EXTI_PR_PR0_Msk (0x1U << EXTI_PR_PR0_Pos) /*!< 0x00000001 */
+#define EXTI_PR_PR0 EXTI_PR_PR0_Msk /*!< Pending bit for line 0 */
+#define EXTI_PR_PR1_Pos (1U)
+#define EXTI_PR_PR1_Msk (0x1U << EXTI_PR_PR1_Pos) /*!< 0x00000002 */
+#define EXTI_PR_PR1 EXTI_PR_PR1_Msk /*!< Pending bit for line 1 */
+#define EXTI_PR_PR2_Pos (2U)
+#define EXTI_PR_PR2_Msk (0x1U << EXTI_PR_PR2_Pos) /*!< 0x00000004 */
+#define EXTI_PR_PR2 EXTI_PR_PR2_Msk /*!< Pending bit for line 2 */
+#define EXTI_PR_PR3_Pos (3U)
+#define EXTI_PR_PR3_Msk (0x1U << EXTI_PR_PR3_Pos) /*!< 0x00000008 */
+#define EXTI_PR_PR3 EXTI_PR_PR3_Msk /*!< Pending bit for line 3 */
+#define EXTI_PR_PR4_Pos (4U)
+#define EXTI_PR_PR4_Msk (0x1U << EXTI_PR_PR4_Pos) /*!< 0x00000010 */
+#define EXTI_PR_PR4 EXTI_PR_PR4_Msk /*!< Pending bit for line 4 */
+#define EXTI_PR_PR5_Pos (5U)
+#define EXTI_PR_PR5_Msk (0x1U << EXTI_PR_PR5_Pos) /*!< 0x00000020 */
+#define EXTI_PR_PR5 EXTI_PR_PR5_Msk /*!< Pending bit for line 5 */
+#define EXTI_PR_PR6_Pos (6U)
+#define EXTI_PR_PR6_Msk (0x1U << EXTI_PR_PR6_Pos) /*!< 0x00000040 */
+#define EXTI_PR_PR6 EXTI_PR_PR6_Msk /*!< Pending bit for line 6 */
+#define EXTI_PR_PR7_Pos (7U)
+#define EXTI_PR_PR7_Msk (0x1U << EXTI_PR_PR7_Pos) /*!< 0x00000080 */
+#define EXTI_PR_PR7 EXTI_PR_PR7_Msk /*!< Pending bit for line 7 */
+#define EXTI_PR_PR8_Pos (8U)
+#define EXTI_PR_PR8_Msk (0x1U << EXTI_PR_PR8_Pos) /*!< 0x00000100 */
+#define EXTI_PR_PR8 EXTI_PR_PR8_Msk /*!< Pending bit for line 8 */
+#define EXTI_PR_PR9_Pos (9U)
+#define EXTI_PR_PR9_Msk (0x1U << EXTI_PR_PR9_Pos) /*!< 0x00000200 */
+#define EXTI_PR_PR9 EXTI_PR_PR9_Msk /*!< Pending bit for line 9 */
+#define EXTI_PR_PR10_Pos (10U)
+#define EXTI_PR_PR10_Msk (0x1U << EXTI_PR_PR10_Pos) /*!< 0x00000400 */
+#define EXTI_PR_PR10 EXTI_PR_PR10_Msk /*!< Pending bit for line 10 */
+#define EXTI_PR_PR11_Pos (11U)
+#define EXTI_PR_PR11_Msk (0x1U << EXTI_PR_PR11_Pos) /*!< 0x00000800 */
+#define EXTI_PR_PR11 EXTI_PR_PR11_Msk /*!< Pending bit for line 11 */
+#define EXTI_PR_PR12_Pos (12U)
+#define EXTI_PR_PR12_Msk (0x1U << EXTI_PR_PR12_Pos) /*!< 0x00001000 */
+#define EXTI_PR_PR12 EXTI_PR_PR12_Msk /*!< Pending bit for line 12 */
+#define EXTI_PR_PR13_Pos (13U)
+#define EXTI_PR_PR13_Msk (0x1U << EXTI_PR_PR13_Pos) /*!< 0x00002000 */
+#define EXTI_PR_PR13 EXTI_PR_PR13_Msk /*!< Pending bit for line 13 */
+#define EXTI_PR_PR14_Pos (14U)
+#define EXTI_PR_PR14_Msk (0x1U << EXTI_PR_PR14_Pos) /*!< 0x00004000 */
+#define EXTI_PR_PR14 EXTI_PR_PR14_Msk /*!< Pending bit for line 14 */
+#define EXTI_PR_PR15_Pos (15U)
+#define EXTI_PR_PR15_Msk (0x1U << EXTI_PR_PR15_Pos) /*!< 0x00008000 */
+#define EXTI_PR_PR15 EXTI_PR_PR15_Msk /*!< Pending bit for line 15 */
+#define EXTI_PR_PR16_Pos (16U)
+#define EXTI_PR_PR16_Msk (0x1U << EXTI_PR_PR16_Pos) /*!< 0x00010000 */
+#define EXTI_PR_PR16 EXTI_PR_PR16_Msk /*!< Pending bit for line 16 */
+#define EXTI_PR_PR17_Pos (17U)
+#define EXTI_PR_PR17_Msk (0x1U << EXTI_PR_PR17_Pos) /*!< 0x00020000 */
+#define EXTI_PR_PR17 EXTI_PR_PR17_Msk /*!< Pending bit for line 17 */
+#define EXTI_PR_PR18_Pos (18U)
+#define EXTI_PR_PR18_Msk (0x1U << EXTI_PR_PR18_Pos) /*!< 0x00040000 */
+#define EXTI_PR_PR18 EXTI_PR_PR18_Msk /*!< Pending bit for line 18 */
+#define EXTI_PR_PR19_Pos (19U)
+#define EXTI_PR_PR19_Msk (0x1U << EXTI_PR_PR19_Pos) /*!< 0x00080000 */
+#define EXTI_PR_PR19 EXTI_PR_PR19_Msk /*!< Pending bit for line 19 */
+
+/* References Defines */
+#define EXTI_PR_PIF0 EXTI_PR_PR0
+#define EXTI_PR_PIF1 EXTI_PR_PR1
+#define EXTI_PR_PIF2 EXTI_PR_PR2
+#define EXTI_PR_PIF3 EXTI_PR_PR3
+#define EXTI_PR_PIF4 EXTI_PR_PR4
+#define EXTI_PR_PIF5 EXTI_PR_PR5
+#define EXTI_PR_PIF6 EXTI_PR_PR6
+#define EXTI_PR_PIF7 EXTI_PR_PR7
+#define EXTI_PR_PIF8 EXTI_PR_PR8
+#define EXTI_PR_PIF9 EXTI_PR_PR9
+#define EXTI_PR_PIF10 EXTI_PR_PR10
+#define EXTI_PR_PIF11 EXTI_PR_PR11
+#define EXTI_PR_PIF12 EXTI_PR_PR12
+#define EXTI_PR_PIF13 EXTI_PR_PR13
+#define EXTI_PR_PIF14 EXTI_PR_PR14
+#define EXTI_PR_PIF15 EXTI_PR_PR15
+#define EXTI_PR_PIF16 EXTI_PR_PR16
+#define EXTI_PR_PIF17 EXTI_PR_PR17
+#define EXTI_PR_PIF18 EXTI_PR_PR18
+#define EXTI_PR_PIF19 EXTI_PR_PR19
+
+/******************************************************************************/
+/* */
+/* DMA Controller */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for DMA_ISR register ********************/
+#define DMA_ISR_GIF1_Pos (0U)
+#define DMA_ISR_GIF1_Msk (0x1U << DMA_ISR_GIF1_Pos) /*!< 0x00000001 */
+#define DMA_ISR_GIF1 DMA_ISR_GIF1_Msk /*!< Channel 1 Global interrupt flag */
+#define DMA_ISR_TCIF1_Pos (1U)
+#define DMA_ISR_TCIF1_Msk (0x1U << DMA_ISR_TCIF1_Pos) /*!< 0x00000002 */
+#define DMA_ISR_TCIF1 DMA_ISR_TCIF1_Msk /*!< Channel 1 Transfer Complete flag */
+#define DMA_ISR_HTIF1_Pos (2U)
+#define DMA_ISR_HTIF1_Msk (0x1U << DMA_ISR_HTIF1_Pos) /*!< 0x00000004 */
+#define DMA_ISR_HTIF1 DMA_ISR_HTIF1_Msk /*!< Channel 1 Half Transfer flag */
+#define DMA_ISR_TEIF1_Pos (3U)
+#define DMA_ISR_TEIF1_Msk (0x1U << DMA_ISR_TEIF1_Pos) /*!< 0x00000008 */
+#define DMA_ISR_TEIF1 DMA_ISR_TEIF1_Msk /*!< Channel 1 Transfer Error flag */
+#define DMA_ISR_GIF2_Pos (4U)
+#define DMA_ISR_GIF2_Msk (0x1U << DMA_ISR_GIF2_Pos) /*!< 0x00000010 */
+#define DMA_ISR_GIF2 DMA_ISR_GIF2_Msk /*!< Channel 2 Global interrupt flag */
+#define DMA_ISR_TCIF2_Pos (5U)
+#define DMA_ISR_TCIF2_Msk (0x1U << DMA_ISR_TCIF2_Pos) /*!< 0x00000020 */
+#define DMA_ISR_TCIF2 DMA_ISR_TCIF2_Msk /*!< Channel 2 Transfer Complete flag */
+#define DMA_ISR_HTIF2_Pos (6U)
+#define DMA_ISR_HTIF2_Msk (0x1U << DMA_ISR_HTIF2_Pos) /*!< 0x00000040 */
+#define DMA_ISR_HTIF2 DMA_ISR_HTIF2_Msk /*!< Channel 2 Half Transfer flag */
+#define DMA_ISR_TEIF2_Pos (7U)
+#define DMA_ISR_TEIF2_Msk (0x1U << DMA_ISR_TEIF2_Pos) /*!< 0x00000080 */
+#define DMA_ISR_TEIF2 DMA_ISR_TEIF2_Msk /*!< Channel 2 Transfer Error flag */
+#define DMA_ISR_GIF3_Pos (8U)
+#define DMA_ISR_GIF3_Msk (0x1U << DMA_ISR_GIF3_Pos) /*!< 0x00000100 */
+#define DMA_ISR_GIF3 DMA_ISR_GIF3_Msk /*!< Channel 3 Global interrupt flag */
+#define DMA_ISR_TCIF3_Pos (9U)
+#define DMA_ISR_TCIF3_Msk (0x1U << DMA_ISR_TCIF3_Pos) /*!< 0x00000200 */
+#define DMA_ISR_TCIF3 DMA_ISR_TCIF3_Msk /*!< Channel 3 Transfer Complete flag */
+#define DMA_ISR_HTIF3_Pos (10U)
+#define DMA_ISR_HTIF3_Msk (0x1U << DMA_ISR_HTIF3_Pos) /*!< 0x00000400 */
+#define DMA_ISR_HTIF3 DMA_ISR_HTIF3_Msk /*!< Channel 3 Half Transfer flag */
+#define DMA_ISR_TEIF3_Pos (11U)
+#define DMA_ISR_TEIF3_Msk (0x1U << DMA_ISR_TEIF3_Pos) /*!< 0x00000800 */
+#define DMA_ISR_TEIF3 DMA_ISR_TEIF3_Msk /*!< Channel 3 Transfer Error flag */
+#define DMA_ISR_GIF4_Pos (12U)
+#define DMA_ISR_GIF4_Msk (0x1U << DMA_ISR_GIF4_Pos) /*!< 0x00001000 */
+#define DMA_ISR_GIF4 DMA_ISR_GIF4_Msk /*!< Channel 4 Global interrupt flag */
+#define DMA_ISR_TCIF4_Pos (13U)
+#define DMA_ISR_TCIF4_Msk (0x1U << DMA_ISR_TCIF4_Pos) /*!< 0x00002000 */
+#define DMA_ISR_TCIF4 DMA_ISR_TCIF4_Msk /*!< Channel 4 Transfer Complete flag */
+#define DMA_ISR_HTIF4_Pos (14U)
+#define DMA_ISR_HTIF4_Msk (0x1U << DMA_ISR_HTIF4_Pos) /*!< 0x00004000 */
+#define DMA_ISR_HTIF4 DMA_ISR_HTIF4_Msk /*!< Channel 4 Half Transfer flag */
+#define DMA_ISR_TEIF4_Pos (15U)
+#define DMA_ISR_TEIF4_Msk (0x1U << DMA_ISR_TEIF4_Pos) /*!< 0x00008000 */
+#define DMA_ISR_TEIF4 DMA_ISR_TEIF4_Msk /*!< Channel 4 Transfer Error flag */
+#define DMA_ISR_GIF5_Pos (16U)
+#define DMA_ISR_GIF5_Msk (0x1U << DMA_ISR_GIF5_Pos) /*!< 0x00010000 */
+#define DMA_ISR_GIF5 DMA_ISR_GIF5_Msk /*!< Channel 5 Global interrupt flag */
+#define DMA_ISR_TCIF5_Pos (17U)
+#define DMA_ISR_TCIF5_Msk (0x1U << DMA_ISR_TCIF5_Pos) /*!< 0x00020000 */
+#define DMA_ISR_TCIF5 DMA_ISR_TCIF5_Msk /*!< Channel 5 Transfer Complete flag */
+#define DMA_ISR_HTIF5_Pos (18U)
+#define DMA_ISR_HTIF5_Msk (0x1U << DMA_ISR_HTIF5_Pos) /*!< 0x00040000 */
+#define DMA_ISR_HTIF5 DMA_ISR_HTIF5_Msk /*!< Channel 5 Half Transfer flag */
+#define DMA_ISR_TEIF5_Pos (19U)
+#define DMA_ISR_TEIF5_Msk (0x1U << DMA_ISR_TEIF5_Pos) /*!< 0x00080000 */
+#define DMA_ISR_TEIF5 DMA_ISR_TEIF5_Msk /*!< Channel 5 Transfer Error flag */
+#define DMA_ISR_GIF6_Pos (20U)
+#define DMA_ISR_GIF6_Msk (0x1U << DMA_ISR_GIF6_Pos) /*!< 0x00100000 */
+#define DMA_ISR_GIF6 DMA_ISR_GIF6_Msk /*!< Channel 6 Global interrupt flag */
+#define DMA_ISR_TCIF6_Pos (21U)
+#define DMA_ISR_TCIF6_Msk (0x1U << DMA_ISR_TCIF6_Pos) /*!< 0x00200000 */
+#define DMA_ISR_TCIF6 DMA_ISR_TCIF6_Msk /*!< Channel 6 Transfer Complete flag */
+#define DMA_ISR_HTIF6_Pos (22U)
+#define DMA_ISR_HTIF6_Msk (0x1U << DMA_ISR_HTIF6_Pos) /*!< 0x00400000 */
+#define DMA_ISR_HTIF6 DMA_ISR_HTIF6_Msk /*!< Channel 6 Half Transfer flag */
+#define DMA_ISR_TEIF6_Pos (23U)
+#define DMA_ISR_TEIF6_Msk (0x1U << DMA_ISR_TEIF6_Pos) /*!< 0x00800000 */
+#define DMA_ISR_TEIF6 DMA_ISR_TEIF6_Msk /*!< Channel 6 Transfer Error flag */
+#define DMA_ISR_GIF7_Pos (24U)
+#define DMA_ISR_GIF7_Msk (0x1U << DMA_ISR_GIF7_Pos) /*!< 0x01000000 */
+#define DMA_ISR_GIF7 DMA_ISR_GIF7_Msk /*!< Channel 7 Global interrupt flag */
+#define DMA_ISR_TCIF7_Pos (25U)
+#define DMA_ISR_TCIF7_Msk (0x1U << DMA_ISR_TCIF7_Pos) /*!< 0x02000000 */
+#define DMA_ISR_TCIF7 DMA_ISR_TCIF7_Msk /*!< Channel 7 Transfer Complete flag */
+#define DMA_ISR_HTIF7_Pos (26U)
+#define DMA_ISR_HTIF7_Msk (0x1U << DMA_ISR_HTIF7_Pos) /*!< 0x04000000 */
+#define DMA_ISR_HTIF7 DMA_ISR_HTIF7_Msk /*!< Channel 7 Half Transfer flag */
+#define DMA_ISR_TEIF7_Pos (27U)
+#define DMA_ISR_TEIF7_Msk (0x1U << DMA_ISR_TEIF7_Pos) /*!< 0x08000000 */
+#define DMA_ISR_TEIF7 DMA_ISR_TEIF7_Msk /*!< Channel 7 Transfer Error flag */
+
+/******************* Bit definition for DMA_IFCR register *******************/
+#define DMA_IFCR_CGIF1_Pos (0U)
+#define DMA_IFCR_CGIF1_Msk (0x1U << DMA_IFCR_CGIF1_Pos) /*!< 0x00000001 */
+#define DMA_IFCR_CGIF1 DMA_IFCR_CGIF1_Msk /*!< Channel 1 Global interrupt clear */
+#define DMA_IFCR_CTCIF1_Pos (1U)
+#define DMA_IFCR_CTCIF1_Msk (0x1U << DMA_IFCR_CTCIF1_Pos) /*!< 0x00000002 */
+#define DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF1_Msk /*!< Channel 1 Transfer Complete clear */
+#define DMA_IFCR_CHTIF1_Pos (2U)
+#define DMA_IFCR_CHTIF1_Msk (0x1U << DMA_IFCR_CHTIF1_Pos) /*!< 0x00000004 */
+#define DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF1_Msk /*!< Channel 1 Half Transfer clear */
+#define DMA_IFCR_CTEIF1_Pos (3U)
+#define DMA_IFCR_CTEIF1_Msk (0x1U << DMA_IFCR_CTEIF1_Pos) /*!< 0x00000008 */
+#define DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF1_Msk /*!< Channel 1 Transfer Error clear */
+#define DMA_IFCR_CGIF2_Pos (4U)
+#define DMA_IFCR_CGIF2_Msk (0x1U << DMA_IFCR_CGIF2_Pos) /*!< 0x00000010 */
+#define DMA_IFCR_CGIF2 DMA_IFCR_CGIF2_Msk /*!< Channel 2 Global interrupt clear */
+#define DMA_IFCR_CTCIF2_Pos (5U)
+#define DMA_IFCR_CTCIF2_Msk (0x1U << DMA_IFCR_CTCIF2_Pos) /*!< 0x00000020 */
+#define DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF2_Msk /*!< Channel 2 Transfer Complete clear */
+#define DMA_IFCR_CHTIF2_Pos (6U)
+#define DMA_IFCR_CHTIF2_Msk (0x1U << DMA_IFCR_CHTIF2_Pos) /*!< 0x00000040 */
+#define DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF2_Msk /*!< Channel 2 Half Transfer clear */
+#define DMA_IFCR_CTEIF2_Pos (7U)
+#define DMA_IFCR_CTEIF2_Msk (0x1U << DMA_IFCR_CTEIF2_Pos) /*!< 0x00000080 */
+#define DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF2_Msk /*!< Channel 2 Transfer Error clear */
+#define DMA_IFCR_CGIF3_Pos (8U)
+#define DMA_IFCR_CGIF3_Msk (0x1U << DMA_IFCR_CGIF3_Pos) /*!< 0x00000100 */
+#define DMA_IFCR_CGIF3 DMA_IFCR_CGIF3_Msk /*!< Channel 3 Global interrupt clear */
+#define DMA_IFCR_CTCIF3_Pos (9U)
+#define DMA_IFCR_CTCIF3_Msk (0x1U << DMA_IFCR_CTCIF3_Pos) /*!< 0x00000200 */
+#define DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF3_Msk /*!< Channel 3 Transfer Complete clear */
+#define DMA_IFCR_CHTIF3_Pos (10U)
+#define DMA_IFCR_CHTIF3_Msk (0x1U << DMA_IFCR_CHTIF3_Pos) /*!< 0x00000400 */
+#define DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF3_Msk /*!< Channel 3 Half Transfer clear */
+#define DMA_IFCR_CTEIF3_Pos (11U)
+#define DMA_IFCR_CTEIF3_Msk (0x1U << DMA_IFCR_CTEIF3_Pos) /*!< 0x00000800 */
+#define DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF3_Msk /*!< Channel 3 Transfer Error clear */
+#define DMA_IFCR_CGIF4_Pos (12U)
+#define DMA_IFCR_CGIF4_Msk (0x1U << DMA_IFCR_CGIF4_Pos) /*!< 0x00001000 */
+#define DMA_IFCR_CGIF4 DMA_IFCR_CGIF4_Msk /*!< Channel 4 Global interrupt clear */
+#define DMA_IFCR_CTCIF4_Pos (13U)
+#define DMA_IFCR_CTCIF4_Msk (0x1U << DMA_IFCR_CTCIF4_Pos) /*!< 0x00002000 */
+#define DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF4_Msk /*!< Channel 4 Transfer Complete clear */
+#define DMA_IFCR_CHTIF4_Pos (14U)
+#define DMA_IFCR_CHTIF4_Msk (0x1U << DMA_IFCR_CHTIF4_Pos) /*!< 0x00004000 */
+#define DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF4_Msk /*!< Channel 4 Half Transfer clear */
+#define DMA_IFCR_CTEIF4_Pos (15U)
+#define DMA_IFCR_CTEIF4_Msk (0x1U << DMA_IFCR_CTEIF4_Pos) /*!< 0x00008000 */
+#define DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF4_Msk /*!< Channel 4 Transfer Error clear */
+#define DMA_IFCR_CGIF5_Pos (16U)
+#define DMA_IFCR_CGIF5_Msk (0x1U << DMA_IFCR_CGIF5_Pos) /*!< 0x00010000 */
+#define DMA_IFCR_CGIF5 DMA_IFCR_CGIF5_Msk /*!< Channel 5 Global interrupt clear */
+#define DMA_IFCR_CTCIF5_Pos (17U)
+#define DMA_IFCR_CTCIF5_Msk (0x1U << DMA_IFCR_CTCIF5_Pos) /*!< 0x00020000 */
+#define DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF5_Msk /*!< Channel 5 Transfer Complete clear */
+#define DMA_IFCR_CHTIF5_Pos (18U)
+#define DMA_IFCR_CHTIF5_Msk (0x1U << DMA_IFCR_CHTIF5_Pos) /*!< 0x00040000 */
+#define DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5_Msk /*!< Channel 5 Half Transfer clear */
+#define DMA_IFCR_CTEIF5_Pos (19U)
+#define DMA_IFCR_CTEIF5_Msk (0x1U << DMA_IFCR_CTEIF5_Pos) /*!< 0x00080000 */
+#define DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF5_Msk /*!< Channel 5 Transfer Error clear */
+#define DMA_IFCR_CGIF6_Pos (20U)
+#define DMA_IFCR_CGIF6_Msk (0x1U << DMA_IFCR_CGIF6_Pos) /*!< 0x00100000 */
+#define DMA_IFCR_CGIF6 DMA_IFCR_CGIF6_Msk /*!< Channel 6 Global interrupt clear */
+#define DMA_IFCR_CTCIF6_Pos (21U)
+#define DMA_IFCR_CTCIF6_Msk (0x1U << DMA_IFCR_CTCIF6_Pos) /*!< 0x00200000 */
+#define DMA_IFCR_CTCIF6 DMA_IFCR_CTCIF6_Msk /*!< Channel 6 Transfer Complete clear */
+#define DMA_IFCR_CHTIF6_Pos (22U)
+#define DMA_IFCR_CHTIF6_Msk (0x1U << DMA_IFCR_CHTIF6_Pos) /*!< 0x00400000 */
+#define DMA_IFCR_CHTIF6 DMA_IFCR_CHTIF6_Msk /*!< Channel 6 Half Transfer clear */
+#define DMA_IFCR_CTEIF6_Pos (23U)
+#define DMA_IFCR_CTEIF6_Msk (0x1U << DMA_IFCR_CTEIF6_Pos) /*!< 0x00800000 */
+#define DMA_IFCR_CTEIF6 DMA_IFCR_CTEIF6_Msk /*!< Channel 6 Transfer Error clear */
+#define DMA_IFCR_CGIF7_Pos (24U)
+#define DMA_IFCR_CGIF7_Msk (0x1U << DMA_IFCR_CGIF7_Pos) /*!< 0x01000000 */
+#define DMA_IFCR_CGIF7 DMA_IFCR_CGIF7_Msk /*!< Channel 7 Global interrupt clear */
+#define DMA_IFCR_CTCIF7_Pos (25U)
+#define DMA_IFCR_CTCIF7_Msk (0x1U << DMA_IFCR_CTCIF7_Pos) /*!< 0x02000000 */
+#define DMA_IFCR_CTCIF7 DMA_IFCR_CTCIF7_Msk /*!< Channel 7 Transfer Complete clear */
+#define DMA_IFCR_CHTIF7_Pos (26U)
+#define DMA_IFCR_CHTIF7_Msk (0x1U << DMA_IFCR_CHTIF7_Pos) /*!< 0x04000000 */
+#define DMA_IFCR_CHTIF7 DMA_IFCR_CHTIF7_Msk /*!< Channel 7 Half Transfer clear */
+#define DMA_IFCR_CTEIF7_Pos (27U)
+#define DMA_IFCR_CTEIF7_Msk (0x1U << DMA_IFCR_CTEIF7_Pos) /*!< 0x08000000 */
+#define DMA_IFCR_CTEIF7 DMA_IFCR_CTEIF7_Msk /*!< Channel 7 Transfer Error clear */
+
+/******************* Bit definition for DMA_CCR register *******************/
+#define DMA_CCR_EN_Pos (0U)
+#define DMA_CCR_EN_Msk (0x1U << DMA_CCR_EN_Pos) /*!< 0x00000001 */
+#define DMA_CCR_EN DMA_CCR_EN_Msk /*!< Channel enable */
+#define DMA_CCR_TCIE_Pos (1U)
+#define DMA_CCR_TCIE_Msk (0x1U << DMA_CCR_TCIE_Pos) /*!< 0x00000002 */
+#define DMA_CCR_TCIE DMA_CCR_TCIE_Msk /*!< Transfer complete interrupt enable */
+#define DMA_CCR_HTIE_Pos (2U)
+#define DMA_CCR_HTIE_Msk (0x1U << DMA_CCR_HTIE_Pos) /*!< 0x00000004 */
+#define DMA_CCR_HTIE DMA_CCR_HTIE_Msk /*!< Half Transfer interrupt enable */
+#define DMA_CCR_TEIE_Pos (3U)
+#define DMA_CCR_TEIE_Msk (0x1U << DMA_CCR_TEIE_Pos) /*!< 0x00000008 */
+#define DMA_CCR_TEIE DMA_CCR_TEIE_Msk /*!< Transfer error interrupt enable */
+#define DMA_CCR_DIR_Pos (4U)
+#define DMA_CCR_DIR_Msk (0x1U << DMA_CCR_DIR_Pos) /*!< 0x00000010 */
+#define DMA_CCR_DIR DMA_CCR_DIR_Msk /*!< Data transfer direction */
+#define DMA_CCR_CIRC_Pos (5U)
+#define DMA_CCR_CIRC_Msk (0x1U << DMA_CCR_CIRC_Pos) /*!< 0x00000020 */
+#define DMA_CCR_CIRC DMA_CCR_CIRC_Msk /*!< Circular mode */
+#define DMA_CCR_PINC_Pos (6U)
+#define DMA_CCR_PINC_Msk (0x1U << DMA_CCR_PINC_Pos) /*!< 0x00000040 */
+#define DMA_CCR_PINC DMA_CCR_PINC_Msk /*!< Peripheral increment mode */
+#define DMA_CCR_MINC_Pos (7U)
+#define DMA_CCR_MINC_Msk (0x1U << DMA_CCR_MINC_Pos) /*!< 0x00000080 */
+#define DMA_CCR_MINC DMA_CCR_MINC_Msk /*!< Memory increment mode */
+
+#define DMA_CCR_PSIZE_Pos (8U)
+#define DMA_CCR_PSIZE_Msk (0x3U << DMA_CCR_PSIZE_Pos) /*!< 0x00000300 */
+#define DMA_CCR_PSIZE DMA_CCR_PSIZE_Msk /*!< PSIZE[1:0] bits (Peripheral size) */
+#define DMA_CCR_PSIZE_0 (0x1U << DMA_CCR_PSIZE_Pos) /*!< 0x00000100 */
+#define DMA_CCR_PSIZE_1 (0x2U << DMA_CCR_PSIZE_Pos) /*!< 0x00000200 */
+
+#define DMA_CCR_MSIZE_Pos (10U)
+#define DMA_CCR_MSIZE_Msk (0x3U << DMA_CCR_MSIZE_Pos) /*!< 0x00000C00 */
+#define DMA_CCR_MSIZE DMA_CCR_MSIZE_Msk /*!< MSIZE[1:0] bits (Memory size) */
+#define DMA_CCR_MSIZE_0 (0x1U << DMA_CCR_MSIZE_Pos) /*!< 0x00000400 */
+#define DMA_CCR_MSIZE_1 (0x2U << DMA_CCR_MSIZE_Pos) /*!< 0x00000800 */
+
+#define DMA_CCR_PL_Pos (12U)
+#define DMA_CCR_PL_Msk (0x3U << DMA_CCR_PL_Pos) /*!< 0x00003000 */
+#define DMA_CCR_PL DMA_CCR_PL_Msk /*!< PL[1:0] bits(Channel Priority level) */
+#define DMA_CCR_PL_0 (0x1U << DMA_CCR_PL_Pos) /*!< 0x00001000 */
+#define DMA_CCR_PL_1 (0x2U << DMA_CCR_PL_Pos) /*!< 0x00002000 */
+
+#define DMA_CCR_MEM2MEM_Pos (14U)
+#define DMA_CCR_MEM2MEM_Msk (0x1U << DMA_CCR_MEM2MEM_Pos) /*!< 0x00004000 */
+#define DMA_CCR_MEM2MEM DMA_CCR_MEM2MEM_Msk /*!< Memory to memory mode */
+
+/****************** Bit definition for DMA_CNDTR register ******************/
+#define DMA_CNDTR_NDT_Pos (0U)
+#define DMA_CNDTR_NDT_Msk (0xFFFFU << DMA_CNDTR_NDT_Pos) /*!< 0x0000FFFF */
+#define DMA_CNDTR_NDT DMA_CNDTR_NDT_Msk /*!< Number of data to Transfer */
+
+/****************** Bit definition for DMA_CPAR register *******************/
+#define DMA_CPAR_PA_Pos (0U)
+#define DMA_CPAR_PA_Msk (0xFFFFFFFFU << DMA_CPAR_PA_Pos) /*!< 0xFFFFFFFF */
+#define DMA_CPAR_PA DMA_CPAR_PA_Msk /*!< Peripheral Address */
+
+/****************** Bit definition for DMA_CMAR register *******************/
+#define DMA_CMAR_MA_Pos (0U)
+#define DMA_CMAR_MA_Msk (0xFFFFFFFFU << DMA_CMAR_MA_Pos) /*!< 0xFFFFFFFF */
+#define DMA_CMAR_MA DMA_CMAR_MA_Msk /*!< Memory Address */
+
+/******************************************************************************/
+/* */
+/* Analog to Digital Converter (ADC) */
+/* */
+/******************************************************************************/
+
+/*
+ * @brief Specific device feature definitions (not present on all devices in the STM32F1 family)
+ */
+/* Note: No specific macro feature on this device */
+
+/******************** Bit definition for ADC_SR register ********************/
+#define ADC_SR_AWD_Pos (0U)
+#define ADC_SR_AWD_Msk (0x1U << ADC_SR_AWD_Pos) /*!< 0x00000001 */
+#define ADC_SR_AWD ADC_SR_AWD_Msk /*!< ADC analog watchdog 1 flag */
+#define ADC_SR_EOS_Pos (1U)
+#define ADC_SR_EOS_Msk (0x1U << ADC_SR_EOS_Pos) /*!< 0x00000002 */
+#define ADC_SR_EOS ADC_SR_EOS_Msk /*!< ADC group regular end of sequence conversions flag */
+#define ADC_SR_JEOS_Pos (2U)
+#define ADC_SR_JEOS_Msk (0x1U << ADC_SR_JEOS_Pos) /*!< 0x00000004 */
+#define ADC_SR_JEOS ADC_SR_JEOS_Msk /*!< ADC group injected end of sequence conversions flag */
+#define ADC_SR_JSTRT_Pos (3U)
+#define ADC_SR_JSTRT_Msk (0x1U << ADC_SR_JSTRT_Pos) /*!< 0x00000008 */
+#define ADC_SR_JSTRT ADC_SR_JSTRT_Msk /*!< ADC group injected conversion start flag */
+#define ADC_SR_STRT_Pos (4U)
+#define ADC_SR_STRT_Msk (0x1U << ADC_SR_STRT_Pos) /*!< 0x00000010 */
+#define ADC_SR_STRT ADC_SR_STRT_Msk /*!< ADC group regular conversion start flag */
+
+/* Legacy defines */
+#define ADC_SR_EOC (ADC_SR_EOS)
+#define ADC_SR_JEOC (ADC_SR_JEOS)
+
+/******************* Bit definition for ADC_CR1 register ********************/
+#define ADC_CR1_AWDCH_Pos (0U)
+#define ADC_CR1_AWDCH_Msk (0x1FU << ADC_CR1_AWDCH_Pos) /*!< 0x0000001F */
+#define ADC_CR1_AWDCH ADC_CR1_AWDCH_Msk /*!< ADC analog watchdog 1 monitored channel selection */
+#define ADC_CR1_AWDCH_0 (0x01U << ADC_CR1_AWDCH_Pos) /*!< 0x00000001 */
+#define ADC_CR1_AWDCH_1 (0x02U << ADC_CR1_AWDCH_Pos) /*!< 0x00000002 */
+#define ADC_CR1_AWDCH_2 (0x04U << ADC_CR1_AWDCH_Pos) /*!< 0x00000004 */
+#define ADC_CR1_AWDCH_3 (0x08U << ADC_CR1_AWDCH_Pos) /*!< 0x00000008 */
+#define ADC_CR1_AWDCH_4 (0x10U << ADC_CR1_AWDCH_Pos) /*!< 0x00000010 */
+
+#define ADC_CR1_EOSIE_Pos (5U)
+#define ADC_CR1_EOSIE_Msk (0x1U << ADC_CR1_EOSIE_Pos) /*!< 0x00000020 */
+#define ADC_CR1_EOSIE ADC_CR1_EOSIE_Msk /*!< ADC group regular end of sequence conversions interrupt */
+#define ADC_CR1_AWDIE_Pos (6U)
+#define ADC_CR1_AWDIE_Msk (0x1U << ADC_CR1_AWDIE_Pos) /*!< 0x00000040 */
+#define ADC_CR1_AWDIE ADC_CR1_AWDIE_Msk /*!< ADC analog watchdog 1 interrupt */
+#define ADC_CR1_JEOSIE_Pos (7U)
+#define ADC_CR1_JEOSIE_Msk (0x1U << ADC_CR1_JEOSIE_Pos) /*!< 0x00000080 */
+#define ADC_CR1_JEOSIE ADC_CR1_JEOSIE_Msk /*!< ADC group injected end of sequence conversions interrupt */
+#define ADC_CR1_SCAN_Pos (8U)
+#define ADC_CR1_SCAN_Msk (0x1U << ADC_CR1_SCAN_Pos) /*!< 0x00000100 */
+#define ADC_CR1_SCAN ADC_CR1_SCAN_Msk /*!< ADC scan mode */
+#define ADC_CR1_AWDSGL_Pos (9U)
+#define ADC_CR1_AWDSGL_Msk (0x1U << ADC_CR1_AWDSGL_Pos) /*!< 0x00000200 */
+#define ADC_CR1_AWDSGL ADC_CR1_AWDSGL_Msk /*!< ADC analog watchdog 1 monitoring a single channel or all channels */
+#define ADC_CR1_JAUTO_Pos (10U)
+#define ADC_CR1_JAUTO_Msk (0x1U << ADC_CR1_JAUTO_Pos) /*!< 0x00000400 */
+#define ADC_CR1_JAUTO ADC_CR1_JAUTO_Msk /*!< ADC group injected automatic trigger mode */
+#define ADC_CR1_DISCEN_Pos (11U)
+#define ADC_CR1_DISCEN_Msk (0x1U << ADC_CR1_DISCEN_Pos) /*!< 0x00000800 */
+#define ADC_CR1_DISCEN ADC_CR1_DISCEN_Msk /*!< ADC group regular sequencer discontinuous mode */
+#define ADC_CR1_JDISCEN_Pos (12U)
+#define ADC_CR1_JDISCEN_Msk (0x1U << ADC_CR1_JDISCEN_Pos) /*!< 0x00001000 */
+#define ADC_CR1_JDISCEN ADC_CR1_JDISCEN_Msk /*!< ADC group injected sequencer discontinuous mode */
+
+#define ADC_CR1_DISCNUM_Pos (13U)
+#define ADC_CR1_DISCNUM_Msk (0x7U << ADC_CR1_DISCNUM_Pos) /*!< 0x0000E000 */
+#define ADC_CR1_DISCNUM ADC_CR1_DISCNUM_Msk /*!< ADC group regular sequencer discontinuous number of ranks */
+#define ADC_CR1_DISCNUM_0 (0x1U << ADC_CR1_DISCNUM_Pos) /*!< 0x00002000 */
+#define ADC_CR1_DISCNUM_1 (0x2U << ADC_CR1_DISCNUM_Pos) /*!< 0x00004000 */
+#define ADC_CR1_DISCNUM_2 (0x4U << ADC_CR1_DISCNUM_Pos) /*!< 0x00008000 */
+
+#define ADC_CR1_JAWDEN_Pos (22U)
+#define ADC_CR1_JAWDEN_Msk (0x1U << ADC_CR1_JAWDEN_Pos) /*!< 0x00400000 */
+#define ADC_CR1_JAWDEN ADC_CR1_JAWDEN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group injected */
+#define ADC_CR1_AWDEN_Pos (23U)
+#define ADC_CR1_AWDEN_Msk (0x1U << ADC_CR1_AWDEN_Pos) /*!< 0x00800000 */
+#define ADC_CR1_AWDEN ADC_CR1_AWDEN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group regular */
+
+/* Legacy defines */
+#define ADC_CR1_EOCIE (ADC_CR1_EOSIE)
+#define ADC_CR1_JEOCIE (ADC_CR1_JEOSIE)
+
+/******************* Bit definition for ADC_CR2 register ********************/
+#define ADC_CR2_ADON_Pos (0U)
+#define ADC_CR2_ADON_Msk (0x1U << ADC_CR2_ADON_Pos) /*!< 0x00000001 */
+#define ADC_CR2_ADON ADC_CR2_ADON_Msk /*!< ADC enable */
+#define ADC_CR2_CONT_Pos (1U)
+#define ADC_CR2_CONT_Msk (0x1U << ADC_CR2_CONT_Pos) /*!< 0x00000002 */
+#define ADC_CR2_CONT ADC_CR2_CONT_Msk /*!< ADC group regular continuous conversion mode */
+#define ADC_CR2_CAL_Pos (2U)
+#define ADC_CR2_CAL_Msk (0x1U << ADC_CR2_CAL_Pos) /*!< 0x00000004 */
+#define ADC_CR2_CAL ADC_CR2_CAL_Msk /*!< ADC calibration start */
+#define ADC_CR2_RSTCAL_Pos (3U)
+#define ADC_CR2_RSTCAL_Msk (0x1U << ADC_CR2_RSTCAL_Pos) /*!< 0x00000008 */
+#define ADC_CR2_RSTCAL ADC_CR2_RSTCAL_Msk /*!< ADC calibration reset */
+#define ADC_CR2_DMA_Pos (8U)
+#define ADC_CR2_DMA_Msk (0x1U << ADC_CR2_DMA_Pos) /*!< 0x00000100 */
+#define ADC_CR2_DMA ADC_CR2_DMA_Msk /*!< ADC DMA transfer enable */
+#define ADC_CR2_ALIGN_Pos (11U)
+#define ADC_CR2_ALIGN_Msk (0x1U << ADC_CR2_ALIGN_Pos) /*!< 0x00000800 */
+#define ADC_CR2_ALIGN ADC_CR2_ALIGN_Msk /*!< ADC data alignement */
+
+#define ADC_CR2_JEXTSEL_Pos (12U)
+#define ADC_CR2_JEXTSEL_Msk (0x7U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00007000 */
+#define ADC_CR2_JEXTSEL ADC_CR2_JEXTSEL_Msk /*!< ADC group injected external trigger source */
+#define ADC_CR2_JEXTSEL_0 (0x1U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00001000 */
+#define ADC_CR2_JEXTSEL_1 (0x2U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00002000 */
+#define ADC_CR2_JEXTSEL_2 (0x4U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00004000 */
+
+#define ADC_CR2_JEXTTRIG_Pos (15U)
+#define ADC_CR2_JEXTTRIG_Msk (0x1U << ADC_CR2_JEXTTRIG_Pos) /*!< 0x00008000 */
+#define ADC_CR2_JEXTTRIG ADC_CR2_JEXTTRIG_Msk /*!< ADC group injected external trigger enable */
+
+#define ADC_CR2_EXTSEL_Pos (17U)
+#define ADC_CR2_EXTSEL_Msk (0x7U << ADC_CR2_EXTSEL_Pos) /*!< 0x000E0000 */
+#define ADC_CR2_EXTSEL ADC_CR2_EXTSEL_Msk /*!< ADC group regular external trigger source */
+#define ADC_CR2_EXTSEL_0 (0x1U << ADC_CR2_EXTSEL_Pos) /*!< 0x00020000 */
+#define ADC_CR2_EXTSEL_1 (0x2U << ADC_CR2_EXTSEL_Pos) /*!< 0x00040000 */
+#define ADC_CR2_EXTSEL_2 (0x4U << ADC_CR2_EXTSEL_Pos) /*!< 0x00080000 */
+
+#define ADC_CR2_EXTTRIG_Pos (20U)
+#define ADC_CR2_EXTTRIG_Msk (0x1U << ADC_CR2_EXTTRIG_Pos) /*!< 0x00100000 */
+#define ADC_CR2_EXTTRIG ADC_CR2_EXTTRIG_Msk /*!< ADC group regular external trigger enable */
+#define ADC_CR2_JSWSTART_Pos (21U)
+#define ADC_CR2_JSWSTART_Msk (0x1U << ADC_CR2_JSWSTART_Pos) /*!< 0x00200000 */
+#define ADC_CR2_JSWSTART ADC_CR2_JSWSTART_Msk /*!< ADC group injected conversion start */
+#define ADC_CR2_SWSTART_Pos (22U)
+#define ADC_CR2_SWSTART_Msk (0x1U << ADC_CR2_SWSTART_Pos) /*!< 0x00400000 */
+#define ADC_CR2_SWSTART ADC_CR2_SWSTART_Msk /*!< ADC group regular conversion start */
+#define ADC_CR2_TSVREFE_Pos (23U)
+#define ADC_CR2_TSVREFE_Msk (0x1U << ADC_CR2_TSVREFE_Pos) /*!< 0x00800000 */
+#define ADC_CR2_TSVREFE ADC_CR2_TSVREFE_Msk /*!< ADC internal path to VrefInt and temperature sensor enable */
+
+/****************** Bit definition for ADC_SMPR1 register *******************/
+#define ADC_SMPR1_SMP10_Pos (0U)
+#define ADC_SMPR1_SMP10_Msk (0x7U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000007 */
+#define ADC_SMPR1_SMP10 ADC_SMPR1_SMP10_Msk /*!< ADC channel 10 sampling time selection */
+#define ADC_SMPR1_SMP10_0 (0x1U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000001 */
+#define ADC_SMPR1_SMP10_1 (0x2U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000002 */
+#define ADC_SMPR1_SMP10_2 (0x4U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000004 */
+
+#define ADC_SMPR1_SMP11_Pos (3U)
+#define ADC_SMPR1_SMP11_Msk (0x7U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000038 */
+#define ADC_SMPR1_SMP11 ADC_SMPR1_SMP11_Msk /*!< ADC channel 11 sampling time selection */
+#define ADC_SMPR1_SMP11_0 (0x1U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000008 */
+#define ADC_SMPR1_SMP11_1 (0x2U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000010 */
+#define ADC_SMPR1_SMP11_2 (0x4U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000020 */
+
+#define ADC_SMPR1_SMP12_Pos (6U)
+#define ADC_SMPR1_SMP12_Msk (0x7U << ADC_SMPR1_SMP12_Pos) /*!< 0x000001C0 */
+#define ADC_SMPR1_SMP12 ADC_SMPR1_SMP12_Msk /*!< ADC channel 12 sampling time selection */
+#define ADC_SMPR1_SMP12_0 (0x1U << ADC_SMPR1_SMP12_Pos) /*!< 0x00000040 */
+#define ADC_SMPR1_SMP12_1 (0x2U << ADC_SMPR1_SMP12_Pos) /*!< 0x00000080 */
+#define ADC_SMPR1_SMP12_2 (0x4U << ADC_SMPR1_SMP12_Pos) /*!< 0x00000100 */
+
+#define ADC_SMPR1_SMP13_Pos (9U)
+#define ADC_SMPR1_SMP13_Msk (0x7U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000E00 */
+#define ADC_SMPR1_SMP13 ADC_SMPR1_SMP13_Msk /*!< ADC channel 13 sampling time selection */
+#define ADC_SMPR1_SMP13_0 (0x1U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000200 */
+#define ADC_SMPR1_SMP13_1 (0x2U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000400 */
+#define ADC_SMPR1_SMP13_2 (0x4U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000800 */
+
+#define ADC_SMPR1_SMP14_Pos (12U)
+#define ADC_SMPR1_SMP14_Msk (0x7U << ADC_SMPR1_SMP14_Pos) /*!< 0x00007000 */
+#define ADC_SMPR1_SMP14 ADC_SMPR1_SMP14_Msk /*!< ADC channel 14 sampling time selection */
+#define ADC_SMPR1_SMP14_0 (0x1U << ADC_SMPR1_SMP14_Pos) /*!< 0x00001000 */
+#define ADC_SMPR1_SMP14_1 (0x2U << ADC_SMPR1_SMP14_Pos) /*!< 0x00002000 */
+#define ADC_SMPR1_SMP14_2 (0x4U << ADC_SMPR1_SMP14_Pos) /*!< 0x00004000 */
+
+#define ADC_SMPR1_SMP15_Pos (15U)
+#define ADC_SMPR1_SMP15_Msk (0x7U << ADC_SMPR1_SMP15_Pos) /*!< 0x00038000 */
+#define ADC_SMPR1_SMP15 ADC_SMPR1_SMP15_Msk /*!< ADC channel 15 sampling time selection */
+#define ADC_SMPR1_SMP15_0 (0x1U << ADC_SMPR1_SMP15_Pos) /*!< 0x00008000 */
+#define ADC_SMPR1_SMP15_1 (0x2U << ADC_SMPR1_SMP15_Pos) /*!< 0x00010000 */
+#define ADC_SMPR1_SMP15_2 (0x4U << ADC_SMPR1_SMP15_Pos) /*!< 0x00020000 */
+
+#define ADC_SMPR1_SMP16_Pos (18U)
+#define ADC_SMPR1_SMP16_Msk (0x7U << ADC_SMPR1_SMP16_Pos) /*!< 0x001C0000 */
+#define ADC_SMPR1_SMP16 ADC_SMPR1_SMP16_Msk /*!< ADC channel 16 sampling time selection */
+#define ADC_SMPR1_SMP16_0 (0x1U << ADC_SMPR1_SMP16_Pos) /*!< 0x00040000 */
+#define ADC_SMPR1_SMP16_1 (0x2U << ADC_SMPR1_SMP16_Pos) /*!< 0x00080000 */
+#define ADC_SMPR1_SMP16_2 (0x4U << ADC_SMPR1_SMP16_Pos) /*!< 0x00100000 */
+
+#define ADC_SMPR1_SMP17_Pos (21U)
+#define ADC_SMPR1_SMP17_Msk (0x7U << ADC_SMPR1_SMP17_Pos) /*!< 0x00E00000 */
+#define ADC_SMPR1_SMP17 ADC_SMPR1_SMP17_Msk /*!< ADC channel 17 sampling time selection */
+#define ADC_SMPR1_SMP17_0 (0x1U << ADC_SMPR1_SMP17_Pos) /*!< 0x00200000 */
+#define ADC_SMPR1_SMP17_1 (0x2U << ADC_SMPR1_SMP17_Pos) /*!< 0x00400000 */
+#define ADC_SMPR1_SMP17_2 (0x4U << ADC_SMPR1_SMP17_Pos) /*!< 0x00800000 */
+
+/****************** Bit definition for ADC_SMPR2 register *******************/
+#define ADC_SMPR2_SMP0_Pos (0U)
+#define ADC_SMPR2_SMP0_Msk (0x7U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000007 */
+#define ADC_SMPR2_SMP0 ADC_SMPR2_SMP0_Msk /*!< ADC channel 0 sampling time selection */
+#define ADC_SMPR2_SMP0_0 (0x1U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000001 */
+#define ADC_SMPR2_SMP0_1 (0x2U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000002 */
+#define ADC_SMPR2_SMP0_2 (0x4U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000004 */
+
+#define ADC_SMPR2_SMP1_Pos (3U)
+#define ADC_SMPR2_SMP1_Msk (0x7U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000038 */
+#define ADC_SMPR2_SMP1 ADC_SMPR2_SMP1_Msk /*!< ADC channel 1 sampling time selection */
+#define ADC_SMPR2_SMP1_0 (0x1U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000008 */
+#define ADC_SMPR2_SMP1_1 (0x2U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000010 */
+#define ADC_SMPR2_SMP1_2 (0x4U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000020 */
+
+#define ADC_SMPR2_SMP2_Pos (6U)
+#define ADC_SMPR2_SMP2_Msk (0x7U << ADC_SMPR2_SMP2_Pos) /*!< 0x000001C0 */
+#define ADC_SMPR2_SMP2 ADC_SMPR2_SMP2_Msk /*!< ADC channel 2 sampling time selection */
+#define ADC_SMPR2_SMP2_0 (0x1U << ADC_SMPR2_SMP2_Pos) /*!< 0x00000040 */
+#define ADC_SMPR2_SMP2_1 (0x2U << ADC_SMPR2_SMP2_Pos) /*!< 0x00000080 */
+#define ADC_SMPR2_SMP2_2 (0x4U << ADC_SMPR2_SMP2_Pos) /*!< 0x00000100 */
+
+#define ADC_SMPR2_SMP3_Pos (9U)
+#define ADC_SMPR2_SMP3_Msk (0x7U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000E00 */
+#define ADC_SMPR2_SMP3 ADC_SMPR2_SMP3_Msk /*!< ADC channel 3 sampling time selection */
+#define ADC_SMPR2_SMP3_0 (0x1U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000200 */
+#define ADC_SMPR2_SMP3_1 (0x2U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000400 */
+#define ADC_SMPR2_SMP3_2 (0x4U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000800 */
+
+#define ADC_SMPR2_SMP4_Pos (12U)
+#define ADC_SMPR2_SMP4_Msk (0x7U << ADC_SMPR2_SMP4_Pos) /*!< 0x00007000 */
+#define ADC_SMPR2_SMP4 ADC_SMPR2_SMP4_Msk /*!< ADC channel 4 sampling time selection */
+#define ADC_SMPR2_SMP4_0 (0x1U << ADC_SMPR2_SMP4_Pos) /*!< 0x00001000 */
+#define ADC_SMPR2_SMP4_1 (0x2U << ADC_SMPR2_SMP4_Pos) /*!< 0x00002000 */
+#define ADC_SMPR2_SMP4_2 (0x4U << ADC_SMPR2_SMP4_Pos) /*!< 0x00004000 */
+
+#define ADC_SMPR2_SMP5_Pos (15U)
+#define ADC_SMPR2_SMP5_Msk (0x7U << ADC_SMPR2_SMP5_Pos) /*!< 0x00038000 */
+#define ADC_SMPR2_SMP5 ADC_SMPR2_SMP5_Msk /*!< ADC channel 5 sampling time selection */
+#define ADC_SMPR2_SMP5_0 (0x1U << ADC_SMPR2_SMP5_Pos) /*!< 0x00008000 */
+#define ADC_SMPR2_SMP5_1 (0x2U << ADC_SMPR2_SMP5_Pos) /*!< 0x00010000 */
+#define ADC_SMPR2_SMP5_2 (0x4U << ADC_SMPR2_SMP5_Pos) /*!< 0x00020000 */
+
+#define ADC_SMPR2_SMP6_Pos (18U)
+#define ADC_SMPR2_SMP6_Msk (0x7U << ADC_SMPR2_SMP6_Pos) /*!< 0x001C0000 */
+#define ADC_SMPR2_SMP6 ADC_SMPR2_SMP6_Msk /*!< ADC channel 6 sampling time selection */
+#define ADC_SMPR2_SMP6_0 (0x1U << ADC_SMPR2_SMP6_Pos) /*!< 0x00040000 */
+#define ADC_SMPR2_SMP6_1 (0x2U << ADC_SMPR2_SMP6_Pos) /*!< 0x00080000 */
+#define ADC_SMPR2_SMP6_2 (0x4U << ADC_SMPR2_SMP6_Pos) /*!< 0x00100000 */
+
+#define ADC_SMPR2_SMP7_Pos (21U)
+#define ADC_SMPR2_SMP7_Msk (0x7U << ADC_SMPR2_SMP7_Pos) /*!< 0x00E00000 */
+#define ADC_SMPR2_SMP7 ADC_SMPR2_SMP7_Msk /*!< ADC channel 7 sampling time selection */
+#define ADC_SMPR2_SMP7_0 (0x1U << ADC_SMPR2_SMP7_Pos) /*!< 0x00200000 */
+#define ADC_SMPR2_SMP7_1 (0x2U << ADC_SMPR2_SMP7_Pos) /*!< 0x00400000 */
+#define ADC_SMPR2_SMP7_2 (0x4U << ADC_SMPR2_SMP7_Pos) /*!< 0x00800000 */
+
+#define ADC_SMPR2_SMP8_Pos (24U)
+#define ADC_SMPR2_SMP8_Msk (0x7U << ADC_SMPR2_SMP8_Pos) /*!< 0x07000000 */
+#define ADC_SMPR2_SMP8 ADC_SMPR2_SMP8_Msk /*!< ADC channel 8 sampling time selection */
+#define ADC_SMPR2_SMP8_0 (0x1U << ADC_SMPR2_SMP8_Pos) /*!< 0x01000000 */
+#define ADC_SMPR2_SMP8_1 (0x2U << ADC_SMPR2_SMP8_Pos) /*!< 0x02000000 */
+#define ADC_SMPR2_SMP8_2 (0x4U << ADC_SMPR2_SMP8_Pos) /*!< 0x04000000 */
+
+#define ADC_SMPR2_SMP9_Pos (27U)
+#define ADC_SMPR2_SMP9_Msk (0x7U << ADC_SMPR2_SMP9_Pos) /*!< 0x38000000 */
+#define ADC_SMPR2_SMP9 ADC_SMPR2_SMP9_Msk /*!< ADC channel 9 sampling time selection */
+#define ADC_SMPR2_SMP9_0 (0x1U << ADC_SMPR2_SMP9_Pos) /*!< 0x08000000 */
+#define ADC_SMPR2_SMP9_1 (0x2U << ADC_SMPR2_SMP9_Pos) /*!< 0x10000000 */
+#define ADC_SMPR2_SMP9_2 (0x4U << ADC_SMPR2_SMP9_Pos) /*!< 0x20000000 */
+
+/****************** Bit definition for ADC_JOFR1 register *******************/
+#define ADC_JOFR1_JOFFSET1_Pos (0U)
+#define ADC_JOFR1_JOFFSET1_Msk (0xFFFU << ADC_JOFR1_JOFFSET1_Pos) /*!< 0x00000FFF */
+#define ADC_JOFR1_JOFFSET1 ADC_JOFR1_JOFFSET1_Msk /*!< ADC group injected sequencer rank 1 offset value */
+
+/****************** Bit definition for ADC_JOFR2 register *******************/
+#define ADC_JOFR2_JOFFSET2_Pos (0U)
+#define ADC_JOFR2_JOFFSET2_Msk (0xFFFU << ADC_JOFR2_JOFFSET2_Pos) /*!< 0x00000FFF */
+#define ADC_JOFR2_JOFFSET2 ADC_JOFR2_JOFFSET2_Msk /*!< ADC group injected sequencer rank 2 offset value */
+
+/****************** Bit definition for ADC_JOFR3 register *******************/
+#define ADC_JOFR3_JOFFSET3_Pos (0U)
+#define ADC_JOFR3_JOFFSET3_Msk (0xFFFU << ADC_JOFR3_JOFFSET3_Pos) /*!< 0x00000FFF */
+#define ADC_JOFR3_JOFFSET3 ADC_JOFR3_JOFFSET3_Msk /*!< ADC group injected sequencer rank 3 offset value */
+
+/****************** Bit definition for ADC_JOFR4 register *******************/
+#define ADC_JOFR4_JOFFSET4_Pos (0U)
+#define ADC_JOFR4_JOFFSET4_Msk (0xFFFU << ADC_JOFR4_JOFFSET4_Pos) /*!< 0x00000FFF */
+#define ADC_JOFR4_JOFFSET4 ADC_JOFR4_JOFFSET4_Msk /*!< ADC group injected sequencer rank 4 offset value */
+
+/******************* Bit definition for ADC_HTR register ********************/
+#define ADC_HTR_HT_Pos (0U)
+#define ADC_HTR_HT_Msk (0xFFFU << ADC_HTR_HT_Pos) /*!< 0x00000FFF */
+#define ADC_HTR_HT ADC_HTR_HT_Msk /*!< ADC analog watchdog 1 threshold high */
+
+/******************* Bit definition for ADC_LTR register ********************/
+#define ADC_LTR_LT_Pos (0U)
+#define ADC_LTR_LT_Msk (0xFFFU << ADC_LTR_LT_Pos) /*!< 0x00000FFF */
+#define ADC_LTR_LT ADC_LTR_LT_Msk /*!< ADC analog watchdog 1 threshold low */
+
+/******************* Bit definition for ADC_SQR1 register *******************/
+#define ADC_SQR1_SQ13_Pos (0U)
+#define ADC_SQR1_SQ13_Msk (0x1FU << ADC_SQR1_SQ13_Pos) /*!< 0x0000001F */
+#define ADC_SQR1_SQ13 ADC_SQR1_SQ13_Msk /*!< ADC group regular sequencer rank 13 */
+#define ADC_SQR1_SQ13_0 (0x01U << ADC_SQR1_SQ13_Pos) /*!< 0x00000001 */
+#define ADC_SQR1_SQ13_1 (0x02U << ADC_SQR1_SQ13_Pos) /*!< 0x00000002 */
+#define ADC_SQR1_SQ13_2 (0x04U << ADC_SQR1_SQ13_Pos) /*!< 0x00000004 */
+#define ADC_SQR1_SQ13_3 (0x08U << ADC_SQR1_SQ13_Pos) /*!< 0x00000008 */
+#define ADC_SQR1_SQ13_4 (0x10U << ADC_SQR1_SQ13_Pos) /*!< 0x00000010 */
+
+#define ADC_SQR1_SQ14_Pos (5U)
+#define ADC_SQR1_SQ14_Msk (0x1FU << ADC_SQR1_SQ14_Pos) /*!< 0x000003E0 */
+#define ADC_SQR1_SQ14 ADC_SQR1_SQ14_Msk /*!< ADC group regular sequencer rank 14 */
+#define ADC_SQR1_SQ14_0 (0x01U << ADC_SQR1_SQ14_Pos) /*!< 0x00000020 */
+#define ADC_SQR1_SQ14_1 (0x02U << ADC_SQR1_SQ14_Pos) /*!< 0x00000040 */
+#define ADC_SQR1_SQ14_2 (0x04U << ADC_SQR1_SQ14_Pos) /*!< 0x00000080 */
+#define ADC_SQR1_SQ14_3 (0x08U << ADC_SQR1_SQ14_Pos) /*!< 0x00000100 */
+#define ADC_SQR1_SQ14_4 (0x10U << ADC_SQR1_SQ14_Pos) /*!< 0x00000200 */
+
+#define ADC_SQR1_SQ15_Pos (10U)
+#define ADC_SQR1_SQ15_Msk (0x1FU << ADC_SQR1_SQ15_Pos) /*!< 0x00007C00 */
+#define ADC_SQR1_SQ15 ADC_SQR1_SQ15_Msk /*!< ADC group regular sequencer rank 15 */
+#define ADC_SQR1_SQ15_0 (0x01U << ADC_SQR1_SQ15_Pos) /*!< 0x00000400 */
+#define ADC_SQR1_SQ15_1 (0x02U << ADC_SQR1_SQ15_Pos) /*!< 0x00000800 */
+#define ADC_SQR1_SQ15_2 (0x04U << ADC_SQR1_SQ15_Pos) /*!< 0x00001000 */
+#define ADC_SQR1_SQ15_3 (0x08U << ADC_SQR1_SQ15_Pos) /*!< 0x00002000 */
+#define ADC_SQR1_SQ15_4 (0x10U << ADC_SQR1_SQ15_Pos) /*!< 0x00004000 */
+
+#define ADC_SQR1_SQ16_Pos (15U)
+#define ADC_SQR1_SQ16_Msk (0x1FU << ADC_SQR1_SQ16_Pos) /*!< 0x000F8000 */
+#define ADC_SQR1_SQ16 ADC_SQR1_SQ16_Msk /*!< ADC group regular sequencer rank 16 */
+#define ADC_SQR1_SQ16_0 (0x01U << ADC_SQR1_SQ16_Pos) /*!< 0x00008000 */
+#define ADC_SQR1_SQ16_1 (0x02U << ADC_SQR1_SQ16_Pos) /*!< 0x00010000 */
+#define ADC_SQR1_SQ16_2 (0x04U << ADC_SQR1_SQ16_Pos) /*!< 0x00020000 */
+#define ADC_SQR1_SQ16_3 (0x08U << ADC_SQR1_SQ16_Pos) /*!< 0x00040000 */
+#define ADC_SQR1_SQ16_4 (0x10U << ADC_SQR1_SQ16_Pos) /*!< 0x00080000 */
+
+#define ADC_SQR1_L_Pos (20U)
+#define ADC_SQR1_L_Msk (0xFU << ADC_SQR1_L_Pos) /*!< 0x00F00000 */
+#define ADC_SQR1_L ADC_SQR1_L_Msk /*!< ADC group regular sequencer scan length */
+#define ADC_SQR1_L_0 (0x1U << ADC_SQR1_L_Pos) /*!< 0x00100000 */
+#define ADC_SQR1_L_1 (0x2U << ADC_SQR1_L_Pos) /*!< 0x00200000 */
+#define ADC_SQR1_L_2 (0x4U << ADC_SQR1_L_Pos) /*!< 0x00400000 */
+#define ADC_SQR1_L_3 (0x8U << ADC_SQR1_L_Pos) /*!< 0x00800000 */
+
+/******************* Bit definition for ADC_SQR2 register *******************/
+#define ADC_SQR2_SQ7_Pos (0U)
+#define ADC_SQR2_SQ7_Msk (0x1FU << ADC_SQR2_SQ7_Pos) /*!< 0x0000001F */
+#define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk /*!< ADC group regular sequencer rank 7 */
+#define ADC_SQR2_SQ7_0 (0x01U << ADC_SQR2_SQ7_Pos) /*!< 0x00000001 */
+#define ADC_SQR2_SQ7_1 (0x02U << ADC_SQR2_SQ7_Pos) /*!< 0x00000002 */
+#define ADC_SQR2_SQ7_2 (0x04U << ADC_SQR2_SQ7_Pos) /*!< 0x00000004 */
+#define ADC_SQR2_SQ7_3 (0x08U << ADC_SQR2_SQ7_Pos) /*!< 0x00000008 */
+#define ADC_SQR2_SQ7_4 (0x10U << ADC_SQR2_SQ7_Pos) /*!< 0x00000010 */
+
+#define ADC_SQR2_SQ8_Pos (5U)
+#define ADC_SQR2_SQ8_Msk (0x1FU << ADC_SQR2_SQ8_Pos) /*!< 0x000003E0 */
+#define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk /*!< ADC group regular sequencer rank 8 */
+#define ADC_SQR2_SQ8_0 (0x01U << ADC_SQR2_SQ8_Pos) /*!< 0x00000020 */
+#define ADC_SQR2_SQ8_1 (0x02U << ADC_SQR2_SQ8_Pos) /*!< 0x00000040 */
+#define ADC_SQR2_SQ8_2 (0x04U << ADC_SQR2_SQ8_Pos) /*!< 0x00000080 */
+#define ADC_SQR2_SQ8_3 (0x08U << ADC_SQR2_SQ8_Pos) /*!< 0x00000100 */
+#define ADC_SQR2_SQ8_4 (0x10U << ADC_SQR2_SQ8_Pos) /*!< 0x00000200 */
+
+#define ADC_SQR2_SQ9_Pos (10U)
+#define ADC_SQR2_SQ9_Msk (0x1FU << ADC_SQR2_SQ9_Pos) /*!< 0x00007C00 */
+#define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk /*!< ADC group regular sequencer rank 9 */
+#define ADC_SQR2_SQ9_0 (0x01U << ADC_SQR2_SQ9_Pos) /*!< 0x00000400 */
+#define ADC_SQR2_SQ9_1 (0x02U << ADC_SQR2_SQ9_Pos) /*!< 0x00000800 */
+#define ADC_SQR2_SQ9_2 (0x04U << ADC_SQR2_SQ9_Pos) /*!< 0x00001000 */
+#define ADC_SQR2_SQ9_3 (0x08U << ADC_SQR2_SQ9_Pos) /*!< 0x00002000 */
+#define ADC_SQR2_SQ9_4 (0x10U << ADC_SQR2_SQ9_Pos) /*!< 0x00004000 */
+
+#define ADC_SQR2_SQ10_Pos (15U)
+#define ADC_SQR2_SQ10_Msk (0x1FU << ADC_SQR2_SQ10_Pos) /*!< 0x000F8000 */
+#define ADC_SQR2_SQ10 ADC_SQR2_SQ10_Msk /*!< ADC group regular sequencer rank 10 */
+#define ADC_SQR2_SQ10_0 (0x01U << ADC_SQR2_SQ10_Pos) /*!< 0x00008000 */
+#define ADC_SQR2_SQ10_1 (0x02U << ADC_SQR2_SQ10_Pos) /*!< 0x00010000 */
+#define ADC_SQR2_SQ10_2 (0x04U << ADC_SQR2_SQ10_Pos) /*!< 0x00020000 */
+#define ADC_SQR2_SQ10_3 (0x08U << ADC_SQR2_SQ10_Pos) /*!< 0x00040000 */
+#define ADC_SQR2_SQ10_4 (0x10U << ADC_SQR2_SQ10_Pos) /*!< 0x00080000 */
+
+#define ADC_SQR2_SQ11_Pos (20U)
+#define ADC_SQR2_SQ11_Msk (0x1FU << ADC_SQR2_SQ11_Pos) /*!< 0x01F00000 */
+#define ADC_SQR2_SQ11 ADC_SQR2_SQ11_Msk /*!< ADC group regular sequencer rank 1 */
+#define ADC_SQR2_SQ11_0 (0x01U << ADC_SQR2_SQ11_Pos) /*!< 0x00100000 */
+#define ADC_SQR2_SQ11_1 (0x02U << ADC_SQR2_SQ11_Pos) /*!< 0x00200000 */
+#define ADC_SQR2_SQ11_2 (0x04U << ADC_SQR2_SQ11_Pos) /*!< 0x00400000 */
+#define ADC_SQR2_SQ11_3 (0x08U << ADC_SQR2_SQ11_Pos) /*!< 0x00800000 */
+#define ADC_SQR2_SQ11_4 (0x10U << ADC_SQR2_SQ11_Pos) /*!< 0x01000000 */
+
+#define ADC_SQR2_SQ12_Pos (25U)
+#define ADC_SQR2_SQ12_Msk (0x1FU << ADC_SQR2_SQ12_Pos) /*!< 0x3E000000 */
+#define ADC_SQR2_SQ12 ADC_SQR2_SQ12_Msk /*!< ADC group regular sequencer rank 12 */
+#define ADC_SQR2_SQ12_0 (0x01U << ADC_SQR2_SQ12_Pos) /*!< 0x02000000 */
+#define ADC_SQR2_SQ12_1 (0x02U << ADC_SQR2_SQ12_Pos) /*!< 0x04000000 */
+#define ADC_SQR2_SQ12_2 (0x04U << ADC_SQR2_SQ12_Pos) /*!< 0x08000000 */
+#define ADC_SQR2_SQ12_3 (0x08U << ADC_SQR2_SQ12_Pos) /*!< 0x10000000 */
+#define ADC_SQR2_SQ12_4 (0x10U << ADC_SQR2_SQ12_Pos) /*!< 0x20000000 */
+
+/******************* Bit definition for ADC_SQR3 register *******************/
+#define ADC_SQR3_SQ1_Pos (0U)
+#define ADC_SQR3_SQ1_Msk (0x1FU << ADC_SQR3_SQ1_Pos) /*!< 0x0000001F */
+#define ADC_SQR3_SQ1 ADC_SQR3_SQ1_Msk /*!< ADC group regular sequencer rank 1 */
+#define ADC_SQR3_SQ1_0 (0x01U << ADC_SQR3_SQ1_Pos) /*!< 0x00000001 */
+#define ADC_SQR3_SQ1_1 (0x02U << ADC_SQR3_SQ1_Pos) /*!< 0x00000002 */
+#define ADC_SQR3_SQ1_2 (0x04U << ADC_SQR3_SQ1_Pos) /*!< 0x00000004 */
+#define ADC_SQR3_SQ1_3 (0x08U << ADC_SQR3_SQ1_Pos) /*!< 0x00000008 */
+#define ADC_SQR3_SQ1_4 (0x10U << ADC_SQR3_SQ1_Pos) /*!< 0x00000010 */
+
+#define ADC_SQR3_SQ2_Pos (5U)
+#define ADC_SQR3_SQ2_Msk (0x1FU << ADC_SQR3_SQ2_Pos) /*!< 0x000003E0 */
+#define ADC_SQR3_SQ2 ADC_SQR3_SQ2_Msk /*!< ADC group regular sequencer rank 2 */
+#define ADC_SQR3_SQ2_0 (0x01U << ADC_SQR3_SQ2_Pos) /*!< 0x00000020 */
+#define ADC_SQR3_SQ2_1 (0x02U << ADC_SQR3_SQ2_Pos) /*!< 0x00000040 */
+#define ADC_SQR3_SQ2_2 (0x04U << ADC_SQR3_SQ2_Pos) /*!< 0x00000080 */
+#define ADC_SQR3_SQ2_3 (0x08U << ADC_SQR3_SQ2_Pos) /*!< 0x00000100 */
+#define ADC_SQR3_SQ2_4 (0x10U << ADC_SQR3_SQ2_Pos) /*!< 0x00000200 */
+
+#define ADC_SQR3_SQ3_Pos (10U)
+#define ADC_SQR3_SQ3_Msk (0x1FU << ADC_SQR3_SQ3_Pos) /*!< 0x00007C00 */
+#define ADC_SQR3_SQ3 ADC_SQR3_SQ3_Msk /*!< ADC group regular sequencer rank 3 */
+#define ADC_SQR3_SQ3_0 (0x01U << ADC_SQR3_SQ3_Pos) /*!< 0x00000400 */
+#define ADC_SQR3_SQ3_1 (0x02U << ADC_SQR3_SQ3_Pos) /*!< 0x00000800 */
+#define ADC_SQR3_SQ3_2 (0x04U << ADC_SQR3_SQ3_Pos) /*!< 0x00001000 */
+#define ADC_SQR3_SQ3_3 (0x08U << ADC_SQR3_SQ3_Pos) /*!< 0x00002000 */
+#define ADC_SQR3_SQ3_4 (0x10U << ADC_SQR3_SQ3_Pos) /*!< 0x00004000 */
+
+#define ADC_SQR3_SQ4_Pos (15U)
+#define ADC_SQR3_SQ4_Msk (0x1FU << ADC_SQR3_SQ4_Pos) /*!< 0x000F8000 */
+#define ADC_SQR3_SQ4 ADC_SQR3_SQ4_Msk /*!< ADC group regular sequencer rank 4 */
+#define ADC_SQR3_SQ4_0 (0x01U << ADC_SQR3_SQ4_Pos) /*!< 0x00008000 */
+#define ADC_SQR3_SQ4_1 (0x02U << ADC_SQR3_SQ4_Pos) /*!< 0x00010000 */
+#define ADC_SQR3_SQ4_2 (0x04U << ADC_SQR3_SQ4_Pos) /*!< 0x00020000 */
+#define ADC_SQR3_SQ4_3 (0x08U << ADC_SQR3_SQ4_Pos) /*!< 0x00040000 */
+#define ADC_SQR3_SQ4_4 (0x10U << ADC_SQR3_SQ4_Pos) /*!< 0x00080000 */
+
+#define ADC_SQR3_SQ5_Pos (20U)
+#define ADC_SQR3_SQ5_Msk (0x1FU << ADC_SQR3_SQ5_Pos) /*!< 0x01F00000 */
+#define ADC_SQR3_SQ5 ADC_SQR3_SQ5_Msk /*!< ADC group regular sequencer rank 5 */
+#define ADC_SQR3_SQ5_0 (0x01U << ADC_SQR3_SQ5_Pos) /*!< 0x00100000 */
+#define ADC_SQR3_SQ5_1 (0x02U << ADC_SQR3_SQ5_Pos) /*!< 0x00200000 */
+#define ADC_SQR3_SQ5_2 (0x04U << ADC_SQR3_SQ5_Pos) /*!< 0x00400000 */
+#define ADC_SQR3_SQ5_3 (0x08U << ADC_SQR3_SQ5_Pos) /*!< 0x00800000 */
+#define ADC_SQR3_SQ5_4 (0x10U << ADC_SQR3_SQ5_Pos) /*!< 0x01000000 */
+
+#define ADC_SQR3_SQ6_Pos (25U)
+#define ADC_SQR3_SQ6_Msk (0x1FU << ADC_SQR3_SQ6_Pos) /*!< 0x3E000000 */
+#define ADC_SQR3_SQ6 ADC_SQR3_SQ6_Msk /*!< ADC group regular sequencer rank 6 */
+#define ADC_SQR3_SQ6_0 (0x01U << ADC_SQR3_SQ6_Pos) /*!< 0x02000000 */
+#define ADC_SQR3_SQ6_1 (0x02U << ADC_SQR3_SQ6_Pos) /*!< 0x04000000 */
+#define ADC_SQR3_SQ6_2 (0x04U << ADC_SQR3_SQ6_Pos) /*!< 0x08000000 */
+#define ADC_SQR3_SQ6_3 (0x08U << ADC_SQR3_SQ6_Pos) /*!< 0x10000000 */
+#define ADC_SQR3_SQ6_4 (0x10U << ADC_SQR3_SQ6_Pos) /*!< 0x20000000 */
+
+/******************* Bit definition for ADC_JSQR register *******************/
+#define ADC_JSQR_JSQ1_Pos (0U)
+#define ADC_JSQR_JSQ1_Msk (0x1FU << ADC_JSQR_JSQ1_Pos) /*!< 0x0000001F */
+#define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!< ADC group injected sequencer rank 1 */
+#define ADC_JSQR_JSQ1_0 (0x01U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000001 */
+#define ADC_JSQR_JSQ1_1 (0x02U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000002 */
+#define ADC_JSQR_JSQ1_2 (0x04U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000004 */
+#define ADC_JSQR_JSQ1_3 (0x08U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000008 */
+#define ADC_JSQR_JSQ1_4 (0x10U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000010 */
+
+#define ADC_JSQR_JSQ2_Pos (5U)
+#define ADC_JSQR_JSQ2_Msk (0x1FU << ADC_JSQR_JSQ2_Pos) /*!< 0x000003E0 */
+#define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!< ADC group injected sequencer rank 2 */
+#define ADC_JSQR_JSQ2_0 (0x01U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000020 */
+#define ADC_JSQR_JSQ2_1 (0x02U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000040 */
+#define ADC_JSQR_JSQ2_2 (0x04U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000080 */
+#define ADC_JSQR_JSQ2_3 (0x08U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000100 */
+#define ADC_JSQR_JSQ2_4 (0x10U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000200 */
+
+#define ADC_JSQR_JSQ3_Pos (10U)
+#define ADC_JSQR_JSQ3_Msk (0x1FU << ADC_JSQR_JSQ3_Pos) /*!< 0x00007C00 */
+#define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!< ADC group injected sequencer rank 3 */
+#define ADC_JSQR_JSQ3_0 (0x01U << ADC_JSQR_JSQ3_Pos) /*!< 0x00000400 */
+#define ADC_JSQR_JSQ3_1 (0x02U << ADC_JSQR_JSQ3_Pos) /*!< 0x00000800 */
+#define ADC_JSQR_JSQ3_2 (0x04U << ADC_JSQR_JSQ3_Pos) /*!< 0x00001000 */
+#define ADC_JSQR_JSQ3_3 (0x08U << ADC_JSQR_JSQ3_Pos) /*!< 0x00002000 */
+#define ADC_JSQR_JSQ3_4 (0x10U << ADC_JSQR_JSQ3_Pos) /*!< 0x00004000 */
+
+#define ADC_JSQR_JSQ4_Pos (15U)
+#define ADC_JSQR_JSQ4_Msk (0x1FU << ADC_JSQR_JSQ4_Pos) /*!< 0x000F8000 */
+#define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!< ADC group injected sequencer rank 4 */
+#define ADC_JSQR_JSQ4_0 (0x01U << ADC_JSQR_JSQ4_Pos) /*!< 0x00008000 */
+#define ADC_JSQR_JSQ4_1 (0x02U << ADC_JSQR_JSQ4_Pos) /*!< 0x00010000 */
+#define ADC_JSQR_JSQ4_2 (0x04U << ADC_JSQR_JSQ4_Pos) /*!< 0x00020000 */
+#define ADC_JSQR_JSQ4_3 (0x08U << ADC_JSQR_JSQ4_Pos) /*!< 0x00040000 */
+#define ADC_JSQR_JSQ4_4 (0x10U << ADC_JSQR_JSQ4_Pos) /*!< 0x00080000 */
+
+#define ADC_JSQR_JL_Pos (20U)
+#define ADC_JSQR_JL_Msk (0x3U << ADC_JSQR_JL_Pos) /*!< 0x00300000 */
+#define ADC_JSQR_JL ADC_JSQR_JL_Msk /*!< ADC group injected sequencer scan length */
+#define ADC_JSQR_JL_0 (0x1U << ADC_JSQR_JL_Pos) /*!< 0x00100000 */
+#define ADC_JSQR_JL_1 (0x2U << ADC_JSQR_JL_Pos) /*!< 0x00200000 */
+
+/******************* Bit definition for ADC_JDR1 register *******************/
+#define ADC_JDR1_JDATA_Pos (0U)
+#define ADC_JDR1_JDATA_Msk (0xFFFFU << ADC_JDR1_JDATA_Pos) /*!< 0x0000FFFF */
+#define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!< ADC group injected sequencer rank 1 conversion data */
+
+/******************* Bit definition for ADC_JDR2 register *******************/
+#define ADC_JDR2_JDATA_Pos (0U)
+#define ADC_JDR2_JDATA_Msk (0xFFFFU << ADC_JDR2_JDATA_Pos) /*!< 0x0000FFFF */
+#define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!< ADC group injected sequencer rank 2 conversion data */
+
+/******************* Bit definition for ADC_JDR3 register *******************/
+#define ADC_JDR3_JDATA_Pos (0U)
+#define ADC_JDR3_JDATA_Msk (0xFFFFU << ADC_JDR3_JDATA_Pos) /*!< 0x0000FFFF */
+#define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!< ADC group injected sequencer rank 3 conversion data */
+
+/******************* Bit definition for ADC_JDR4 register *******************/
+#define ADC_JDR4_JDATA_Pos (0U)
+#define ADC_JDR4_JDATA_Msk (0xFFFFU << ADC_JDR4_JDATA_Pos) /*!< 0x0000FFFF */
+#define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!< ADC group injected sequencer rank 4 conversion data */
+
+/******************** Bit definition for ADC_DR register ********************/
+#define ADC_DR_DATA_Pos (0U)
+#define ADC_DR_DATA_Msk (0xFFFFU << ADC_DR_DATA_Pos) /*!< 0x0000FFFF */
+#define ADC_DR_DATA ADC_DR_DATA_Msk /*!< ADC group regular conversion data */
+
+
+/*****************************************************************************/
+/* */
+/* Timers (TIM) */
+/* */
+/*****************************************************************************/
+/******************* Bit definition for TIM_CR1 register *******************/
+#define TIM_CR1_CEN_Pos (0U)
+#define TIM_CR1_CEN_Msk (0x1U << TIM_CR1_CEN_Pos) /*!< 0x00000001 */
+#define TIM_CR1_CEN TIM_CR1_CEN_Msk /*!<Counter enable */
+#define TIM_CR1_UDIS_Pos (1U)
+#define TIM_CR1_UDIS_Msk (0x1U << TIM_CR1_UDIS_Pos) /*!< 0x00000002 */
+#define TIM_CR1_UDIS TIM_CR1_UDIS_Msk /*!<Update disable */
+#define TIM_CR1_URS_Pos (2U)
+#define TIM_CR1_URS_Msk (0x1U << TIM_CR1_URS_Pos) /*!< 0x00000004 */
+#define TIM_CR1_URS TIM_CR1_URS_Msk /*!<Update request source */
+#define TIM_CR1_OPM_Pos (3U)
+#define TIM_CR1_OPM_Msk (0x1U << TIM_CR1_OPM_Pos) /*!< 0x00000008 */
+#define TIM_CR1_OPM TIM_CR1_OPM_Msk /*!<One pulse mode */
+#define TIM_CR1_DIR_Pos (4U)
+#define TIM_CR1_DIR_Msk (0x1U << TIM_CR1_DIR_Pos) /*!< 0x00000010 */
+#define TIM_CR1_DIR TIM_CR1_DIR_Msk /*!<Direction */
+
+#define TIM_CR1_CMS_Pos (5U)
+#define TIM_CR1_CMS_Msk (0x3U << TIM_CR1_CMS_Pos) /*!< 0x00000060 */
+#define TIM_CR1_CMS TIM_CR1_CMS_Msk /*!<CMS[1:0] bits (Center-aligned mode selection) */
+#define TIM_CR1_CMS_0 (0x1U << TIM_CR1_CMS_Pos) /*!< 0x00000020 */
+#define TIM_CR1_CMS_1 (0x2U << TIM_CR1_CMS_Pos) /*!< 0x00000040 */
+
+#define TIM_CR1_ARPE_Pos (7U)
+#define TIM_CR1_ARPE_Msk (0x1U << TIM_CR1_ARPE_Pos) /*!< 0x00000080 */
+#define TIM_CR1_ARPE TIM_CR1_ARPE_Msk /*!<Auto-reload preload enable */
+
+#define TIM_CR1_CKD_Pos (8U)
+#define TIM_CR1_CKD_Msk (0x3U << TIM_CR1_CKD_Pos) /*!< 0x00000300 */
+#define TIM_CR1_CKD TIM_CR1_CKD_Msk /*!<CKD[1:0] bits (clock division) */
+#define TIM_CR1_CKD_0 (0x1U << TIM_CR1_CKD_Pos) /*!< 0x00000100 */
+#define TIM_CR1_CKD_1 (0x2U << TIM_CR1_CKD_Pos) /*!< 0x00000200 */
+
+/******************* Bit definition for TIM_CR2 register *******************/
+#define TIM_CR2_CCPC_Pos (0U)
+#define TIM_CR2_CCPC_Msk (0x1U << TIM_CR2_CCPC_Pos) /*!< 0x00000001 */
+#define TIM_CR2_CCPC TIM_CR2_CCPC_Msk /*!<Capture/Compare Preloaded Control */
+#define TIM_CR2_CCUS_Pos (2U)
+#define TIM_CR2_CCUS_Msk (0x1U << TIM_CR2_CCUS_Pos) /*!< 0x00000004 */
+#define TIM_CR2_CCUS TIM_CR2_CCUS_Msk /*!<Capture/Compare Control Update Selection */
+#define TIM_CR2_CCDS_Pos (3U)
+#define TIM_CR2_CCDS_Msk (0x1U << TIM_CR2_CCDS_Pos) /*!< 0x00000008 */
+#define TIM_CR2_CCDS TIM_CR2_CCDS_Msk /*!<Capture/Compare DMA Selection */
+
+#define TIM_CR2_MMS_Pos (4U)
+#define TIM_CR2_MMS_Msk (0x7U << TIM_CR2_MMS_Pos) /*!< 0x00000070 */
+#define TIM_CR2_MMS TIM_CR2_MMS_Msk /*!<MMS[2:0] bits (Master Mode Selection) */
+#define TIM_CR2_MMS_0 (0x1U << TIM_CR2_MMS_Pos) /*!< 0x00000010 */
+#define TIM_CR2_MMS_1 (0x2U << TIM_CR2_MMS_Pos) /*!< 0x00000020 */
+#define TIM_CR2_MMS_2 (0x4U << TIM_CR2_MMS_Pos) /*!< 0x00000040 */
+
+#define TIM_CR2_TI1S_Pos (7U)
+#define TIM_CR2_TI1S_Msk (0x1U << TIM_CR2_TI1S_Pos) /*!< 0x00000080 */
+#define TIM_CR2_TI1S TIM_CR2_TI1S_Msk /*!<TI1 Selection */
+#define TIM_CR2_OIS1_Pos (8U)
+#define TIM_CR2_OIS1_Msk (0x1U << TIM_CR2_OIS1_Pos) /*!< 0x00000100 */
+#define TIM_CR2_OIS1 TIM_CR2_OIS1_Msk /*!<Output Idle state 1 (OC1 output) */
+#define TIM_CR2_OIS1N_Pos (9U)
+#define TIM_CR2_OIS1N_Msk (0x1U << TIM_CR2_OIS1N_Pos) /*!< 0x00000200 */
+#define TIM_CR2_OIS1N TIM_CR2_OIS1N_Msk /*!<Output Idle state 1 (OC1N output) */
+#define TIM_CR2_OIS2_Pos (10U)
+#define TIM_CR2_OIS2_Msk (0x1U << TIM_CR2_OIS2_Pos) /*!< 0x00000400 */
+#define TIM_CR2_OIS2 TIM_CR2_OIS2_Msk /*!<Output Idle state 2 (OC2 output) */
+#define TIM_CR2_OIS2N_Pos (11U)
+#define TIM_CR2_OIS2N_Msk (0x1U << TIM_CR2_OIS2N_Pos) /*!< 0x00000800 */
+#define TIM_CR2_OIS2N TIM_CR2_OIS2N_Msk /*!<Output Idle state 2 (OC2N output) */
+#define TIM_CR2_OIS3_Pos (12U)
+#define TIM_CR2_OIS3_Msk (0x1U << TIM_CR2_OIS3_Pos) /*!< 0x00001000 */
+#define TIM_CR2_OIS3 TIM_CR2_OIS3_Msk /*!<Output Idle state 3 (OC3 output) */
+#define TIM_CR2_OIS3N_Pos (13U)
+#define TIM_CR2_OIS3N_Msk (0x1U << TIM_CR2_OIS3N_Pos) /*!< 0x00002000 */
+#define TIM_CR2_OIS3N TIM_CR2_OIS3N_Msk /*!<Output Idle state 3 (OC3N output) */
+#define TIM_CR2_OIS4_Pos (14U)
+#define TIM_CR2_OIS4_Msk (0x1U << TIM_CR2_OIS4_Pos) /*!< 0x00004000 */
+#define TIM_CR2_OIS4 TIM_CR2_OIS4_Msk /*!<Output Idle state 4 (OC4 output) */
+
+/******************* Bit definition for TIM_SMCR register ******************/
+#define TIM_SMCR_SMS_Pos (0U)
+#define TIM_SMCR_SMS_Msk (0x7U << TIM_SMCR_SMS_Pos) /*!< 0x00000007 */
+#define TIM_SMCR_SMS TIM_SMCR_SMS_Msk /*!<SMS[2:0] bits (Slave mode selection) */
+#define TIM_SMCR_SMS_0 (0x1U << TIM_SMCR_SMS_Pos) /*!< 0x00000001 */
+#define TIM_SMCR_SMS_1 (0x2U << TIM_SMCR_SMS_Pos) /*!< 0x00000002 */
+#define TIM_SMCR_SMS_2 (0x4U << TIM_SMCR_SMS_Pos) /*!< 0x00000004 */
+
+#define TIM_SMCR_OCCS_Pos (3U)
+#define TIM_SMCR_OCCS_Msk (0x1U << TIM_SMCR_OCCS_Pos) /*!< 0x00000008 */
+#define TIM_SMCR_OCCS TIM_SMCR_OCCS_Msk /*!< OCREF clear selection */
+
+#define TIM_SMCR_TS_Pos (4U)
+#define TIM_SMCR_TS_Msk (0x7U << TIM_SMCR_TS_Pos) /*!< 0x00000070 */
+#define TIM_SMCR_TS TIM_SMCR_TS_Msk /*!<TS[2:0] bits (Trigger selection) */
+#define TIM_SMCR_TS_0 (0x1U << TIM_SMCR_TS_Pos) /*!< 0x00000010 */
+#define TIM_SMCR_TS_1 (0x2U << TIM_SMCR_TS_Pos) /*!< 0x00000020 */
+#define TIM_SMCR_TS_2 (0x4U << TIM_SMCR_TS_Pos) /*!< 0x00000040 */
+
+#define TIM_SMCR_MSM_Pos (7U)
+#define TIM_SMCR_MSM_Msk (0x1U << TIM_SMCR_MSM_Pos) /*!< 0x00000080 */
+#define TIM_SMCR_MSM TIM_SMCR_MSM_Msk /*!<Master/slave mode */
+
+#define TIM_SMCR_ETF_Pos (8U)
+#define TIM_SMCR_ETF_Msk (0xFU << TIM_SMCR_ETF_Pos) /*!< 0x00000F00 */
+#define TIM_SMCR_ETF TIM_SMCR_ETF_Msk /*!<ETF[3:0] bits (External trigger filter) */
+#define TIM_SMCR_ETF_0 (0x1U << TIM_SMCR_ETF_Pos) /*!< 0x00000100 */
+#define TIM_SMCR_ETF_1 (0x2U << TIM_SMCR_ETF_Pos) /*!< 0x00000200 */
+#define TIM_SMCR_ETF_2 (0x4U << TIM_SMCR_ETF_Pos) /*!< 0x00000400 */
+#define TIM_SMCR_ETF_3 (0x8U << TIM_SMCR_ETF_Pos) /*!< 0x00000800 */
+
+#define TIM_SMCR_ETPS_Pos (12U)
+#define TIM_SMCR_ETPS_Msk (0x3U << TIM_SMCR_ETPS_Pos) /*!< 0x00003000 */
+#define TIM_SMCR_ETPS TIM_SMCR_ETPS_Msk /*!<ETPS[1:0] bits (External trigger prescaler) */
+#define TIM_SMCR_ETPS_0 (0x1U << TIM_SMCR_ETPS_Pos) /*!< 0x00001000 */
+#define TIM_SMCR_ETPS_1 (0x2U << TIM_SMCR_ETPS_Pos) /*!< 0x00002000 */
+
+#define TIM_SMCR_ECE_Pos (14U)
+#define TIM_SMCR_ECE_Msk (0x1U << TIM_SMCR_ECE_Pos) /*!< 0x00004000 */
+#define TIM_SMCR_ECE TIM_SMCR_ECE_Msk /*!<External clock enable */
+#define TIM_SMCR_ETP_Pos (15U)
+#define TIM_SMCR_ETP_Msk (0x1U << TIM_SMCR_ETP_Pos) /*!< 0x00008000 */
+#define TIM_SMCR_ETP TIM_SMCR_ETP_Msk /*!<External trigger polarity */
+
+/******************* Bit definition for TIM_DIER register ******************/
+#define TIM_DIER_UIE_Pos (0U)
+#define TIM_DIER_UIE_Msk (0x1U << TIM_DIER_UIE_Pos) /*!< 0x00000001 */
+#define TIM_DIER_UIE TIM_DIER_UIE_Msk /*!<Update interrupt enable */
+#define TIM_DIER_CC1IE_Pos (1U)
+#define TIM_DIER_CC1IE_Msk (0x1U << TIM_DIER_CC1IE_Pos) /*!< 0x00000002 */
+#define TIM_DIER_CC1IE TIM_DIER_CC1IE_Msk /*!<Capture/Compare 1 interrupt enable */
+#define TIM_DIER_CC2IE_Pos (2U)
+#define TIM_DIER_CC2IE_Msk (0x1U << TIM_DIER_CC2IE_Pos) /*!< 0x00000004 */
+#define TIM_DIER_CC2IE TIM_DIER_CC2IE_Msk /*!<Capture/Compare 2 interrupt enable */
+#define TIM_DIER_CC3IE_Pos (3U)
+#define TIM_DIER_CC3IE_Msk (0x1U << TIM_DIER_CC3IE_Pos) /*!< 0x00000008 */
+#define TIM_DIER_CC3IE TIM_DIER_CC3IE_Msk /*!<Capture/Compare 3 interrupt enable */
+#define TIM_DIER_CC4IE_Pos (4U)
+#define TIM_DIER_CC4IE_Msk (0x1U << TIM_DIER_CC4IE_Pos) /*!< 0x00000010 */
+#define TIM_DIER_CC4IE TIM_DIER_CC4IE_Msk /*!<Capture/Compare 4 interrupt enable */
+#define TIM_DIER_COMIE_Pos (5U)
+#define TIM_DIER_COMIE_Msk (0x1U << TIM_DIER_COMIE_Pos) /*!< 0x00000020 */
+#define TIM_DIER_COMIE TIM_DIER_COMIE_Msk /*!<COM interrupt enable */
+#define TIM_DIER_TIE_Pos (6U)
+#define TIM_DIER_TIE_Msk (0x1U << TIM_DIER_TIE_Pos) /*!< 0x00000040 */
+#define TIM_DIER_TIE TIM_DIER_TIE_Msk /*!<Trigger interrupt enable */
+#define TIM_DIER_BIE_Pos (7U)
+#define TIM_DIER_BIE_Msk (0x1U << TIM_DIER_BIE_Pos) /*!< 0x00000080 */
+#define TIM_DIER_BIE TIM_DIER_BIE_Msk /*!<Break interrupt enable */
+#define TIM_DIER_UDE_Pos (8U)
+#define TIM_DIER_UDE_Msk (0x1U << TIM_DIER_UDE_Pos) /*!< 0x00000100 */
+#define TIM_DIER_UDE TIM_DIER_UDE_Msk /*!<Update DMA request enable */
+#define TIM_DIER_CC1DE_Pos (9U)
+#define TIM_DIER_CC1DE_Msk (0x1U << TIM_DIER_CC1DE_Pos) /*!< 0x00000200 */
+#define TIM_DIER_CC1DE TIM_DIER_CC1DE_Msk /*!<Capture/Compare 1 DMA request enable */
+#define TIM_DIER_CC2DE_Pos (10U)
+#define TIM_DIER_CC2DE_Msk (0x1U << TIM_DIER_CC2DE_Pos) /*!< 0x00000400 */
+#define TIM_DIER_CC2DE TIM_DIER_CC2DE_Msk /*!<Capture/Compare 2 DMA request enable */
+#define TIM_DIER_CC3DE_Pos (11U)
+#define TIM_DIER_CC3DE_Msk (0x1U << TIM_DIER_CC3DE_Pos) /*!< 0x00000800 */
+#define TIM_DIER_CC3DE TIM_DIER_CC3DE_Msk /*!<Capture/Compare 3 DMA request enable */
+#define TIM_DIER_CC4DE_Pos (12U)
+#define TIM_DIER_CC4DE_Msk (0x1U << TIM_DIER_CC4DE_Pos) /*!< 0x00001000 */
+#define TIM_DIER_CC4DE TIM_DIER_CC4DE_Msk /*!<Capture/Compare 4 DMA request enable */
+#define TIM_DIER_COMDE_Pos (13U)
+#define TIM_DIER_COMDE_Msk (0x1U << TIM_DIER_COMDE_Pos) /*!< 0x00002000 */
+#define TIM_DIER_COMDE TIM_DIER_COMDE_Msk /*!<COM DMA request enable */
+#define TIM_DIER_TDE_Pos (14U)
+#define TIM_DIER_TDE_Msk (0x1U << TIM_DIER_TDE_Pos) /*!< 0x00004000 */
+#define TIM_DIER_TDE TIM_DIER_TDE_Msk /*!<Trigger DMA request enable */
+
+/******************** Bit definition for TIM_SR register *******************/
+#define TIM_SR_UIF_Pos (0U)
+#define TIM_SR_UIF_Msk (0x1U << TIM_SR_UIF_Pos) /*!< 0x00000001 */
+#define TIM_SR_UIF TIM_SR_UIF_Msk /*!<Update interrupt Flag */
+#define TIM_SR_CC1IF_Pos (1U)
+#define TIM_SR_CC1IF_Msk (0x1U << TIM_SR_CC1IF_Pos) /*!< 0x00000002 */
+#define TIM_SR_CC1IF TIM_SR_CC1IF_Msk /*!<Capture/Compare 1 interrupt Flag */
+#define TIM_SR_CC2IF_Pos (2U)
+#define TIM_SR_CC2IF_Msk (0x1U << TIM_SR_CC2IF_Pos) /*!< 0x00000004 */
+#define TIM_SR_CC2IF TIM_SR_CC2IF_Msk /*!<Capture/Compare 2 interrupt Flag */
+#define TIM_SR_CC3IF_Pos (3U)
+#define TIM_SR_CC3IF_Msk (0x1U << TIM_SR_CC3IF_Pos) /*!< 0x00000008 */
+#define TIM_SR_CC3IF TIM_SR_CC3IF_Msk /*!<Capture/Compare 3 interrupt Flag */
+#define TIM_SR_CC4IF_Pos (4U)
+#define TIM_SR_CC4IF_Msk (0x1U << TIM_SR_CC4IF_Pos) /*!< 0x00000010 */
+#define TIM_SR_CC4IF TIM_SR_CC4IF_Msk /*!<Capture/Compare 4 interrupt Flag */
+#define TIM_SR_COMIF_Pos (5U)
+#define TIM_SR_COMIF_Msk (0x1U << TIM_SR_COMIF_Pos) /*!< 0x00000020 */
+#define TIM_SR_COMIF TIM_SR_COMIF_Msk /*!<COM interrupt Flag */
+#define TIM_SR_TIF_Pos (6U)
+#define TIM_SR_TIF_Msk (0x1U << TIM_SR_TIF_Pos) /*!< 0x00000040 */
+#define TIM_SR_TIF TIM_SR_TIF_Msk /*!<Trigger interrupt Flag */
+#define TIM_SR_BIF_Pos (7U)
+#define TIM_SR_BIF_Msk (0x1U << TIM_SR_BIF_Pos) /*!< 0x00000080 */
+#define TIM_SR_BIF TIM_SR_BIF_Msk /*!<Break interrupt Flag */
+#define TIM_SR_CC1OF_Pos (9U)
+#define TIM_SR_CC1OF_Msk (0x1U << TIM_SR_CC1OF_Pos) /*!< 0x00000200 */
+#define TIM_SR_CC1OF TIM_SR_CC1OF_Msk /*!<Capture/Compare 1 Overcapture Flag */
+#define TIM_SR_CC2OF_Pos (10U)
+#define TIM_SR_CC2OF_Msk (0x1U << TIM_SR_CC2OF_Pos) /*!< 0x00000400 */
+#define TIM_SR_CC2OF TIM_SR_CC2OF_Msk /*!<Capture/Compare 2 Overcapture Flag */
+#define TIM_SR_CC3OF_Pos (11U)
+#define TIM_SR_CC3OF_Msk (0x1U << TIM_SR_CC3OF_Pos) /*!< 0x00000800 */
+#define TIM_SR_CC3OF TIM_SR_CC3OF_Msk /*!<Capture/Compare 3 Overcapture Flag */
+#define TIM_SR_CC4OF_Pos (12U)
+#define TIM_SR_CC4OF_Msk (0x1U << TIM_SR_CC4OF_Pos) /*!< 0x00001000 */
+#define TIM_SR_CC4OF TIM_SR_CC4OF_Msk /*!<Capture/Compare 4 Overcapture Flag */
+
+/******************* Bit definition for TIM_EGR register *******************/
+#define TIM_EGR_UG_Pos (0U)
+#define TIM_EGR_UG_Msk (0x1U << TIM_EGR_UG_Pos) /*!< 0x00000001 */
+#define TIM_EGR_UG TIM_EGR_UG_Msk /*!<Update Generation */
+#define TIM_EGR_CC1G_Pos (1U)
+#define TIM_EGR_CC1G_Msk (0x1U << TIM_EGR_CC1G_Pos) /*!< 0x00000002 */
+#define TIM_EGR_CC1G TIM_EGR_CC1G_Msk /*!<Capture/Compare 1 Generation */
+#define TIM_EGR_CC2G_Pos (2U)
+#define TIM_EGR_CC2G_Msk (0x1U << TIM_EGR_CC2G_Pos) /*!< 0x00000004 */
+#define TIM_EGR_CC2G TIM_EGR_CC2G_Msk /*!<Capture/Compare 2 Generation */
+#define TIM_EGR_CC3G_Pos (3U)
+#define TIM_EGR_CC3G_Msk (0x1U << TIM_EGR_CC3G_Pos) /*!< 0x00000008 */
+#define TIM_EGR_CC3G TIM_EGR_CC3G_Msk /*!<Capture/Compare 3 Generation */
+#define TIM_EGR_CC4G_Pos (4U)
+#define TIM_EGR_CC4G_Msk (0x1U << TIM_EGR_CC4G_Pos) /*!< 0x00000010 */
+#define TIM_EGR_CC4G TIM_EGR_CC4G_Msk /*!<Capture/Compare 4 Generation */
+#define TIM_EGR_COMG_Pos (5U)
+#define TIM_EGR_COMG_Msk (0x1U << TIM_EGR_COMG_Pos) /*!< 0x00000020 */
+#define TIM_EGR_COMG TIM_EGR_COMG_Msk /*!<Capture/Compare Control Update Generation */
+#define TIM_EGR_TG_Pos (6U)
+#define TIM_EGR_TG_Msk (0x1U << TIM_EGR_TG_Pos) /*!< 0x00000040 */
+#define TIM_EGR_TG TIM_EGR_TG_Msk /*!<Trigger Generation */
+#define TIM_EGR_BG_Pos (7U)
+#define TIM_EGR_BG_Msk (0x1U << TIM_EGR_BG_Pos) /*!< 0x00000080 */
+#define TIM_EGR_BG TIM_EGR_BG_Msk /*!<Break Generation */
+
+/****************** Bit definition for TIM_CCMR1 register ******************/
+#define TIM_CCMR1_CC1S_Pos (0U)
+#define TIM_CCMR1_CC1S_Msk (0x3U << TIM_CCMR1_CC1S_Pos) /*!< 0x00000003 */
+#define TIM_CCMR1_CC1S TIM_CCMR1_CC1S_Msk /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
+#define TIM_CCMR1_CC1S_0 (0x1U << TIM_CCMR1_CC1S_Pos) /*!< 0x00000001 */
+#define TIM_CCMR1_CC1S_1 (0x2U << TIM_CCMR1_CC1S_Pos) /*!< 0x00000002 */
+
+#define TIM_CCMR1_OC1FE_Pos (2U)
+#define TIM_CCMR1_OC1FE_Msk (0x1U << TIM_CCMR1_OC1FE_Pos) /*!< 0x00000004 */
+#define TIM_CCMR1_OC1FE TIM_CCMR1_OC1FE_Msk /*!<Output Compare 1 Fast enable */
+#define TIM_CCMR1_OC1PE_Pos (3U)
+#define TIM_CCMR1_OC1PE_Msk (0x1U << TIM_CCMR1_OC1PE_Pos) /*!< 0x00000008 */
+#define TIM_CCMR1_OC1PE TIM_CCMR1_OC1PE_Msk /*!<Output Compare 1 Preload enable */
+
+#define TIM_CCMR1_OC1M_Pos (4U)
+#define TIM_CCMR1_OC1M_Msk (0x7U << TIM_CCMR1_OC1M_Pos) /*!< 0x00000070 */
+#define TIM_CCMR1_OC1M TIM_CCMR1_OC1M_Msk /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
+#define TIM_CCMR1_OC1M_0 (0x1U << TIM_CCMR1_OC1M_Pos) /*!< 0x00000010 */
+#define TIM_CCMR1_OC1M_1 (0x2U << TIM_CCMR1_OC1M_Pos) /*!< 0x00000020 */
+#define TIM_CCMR1_OC1M_2 (0x4U << TIM_CCMR1_OC1M_Pos) /*!< 0x00000040 */
+
+#define TIM_CCMR1_OC1CE_Pos (7U)
+#define TIM_CCMR1_OC1CE_Msk (0x1U << TIM_CCMR1_OC1CE_Pos) /*!< 0x00000080 */
+#define TIM_CCMR1_OC1CE TIM_CCMR1_OC1CE_Msk /*!<Output Compare 1Clear Enable */
+
+#define TIM_CCMR1_CC2S_Pos (8U)
+#define TIM_CCMR1_CC2S_Msk (0x3U << TIM_CCMR1_CC2S_Pos) /*!< 0x00000300 */
+#define TIM_CCMR1_CC2S TIM_CCMR1_CC2S_Msk /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
+#define TIM_CCMR1_CC2S_0 (0x1U << TIM_CCMR1_CC2S_Pos) /*!< 0x00000100 */
+#define TIM_CCMR1_CC2S_1 (0x2U << TIM_CCMR1_CC2S_Pos) /*!< 0x00000200 */
+
+#define TIM_CCMR1_OC2FE_Pos (10U)
+#define TIM_CCMR1_OC2FE_Msk (0x1U << TIM_CCMR1_OC2FE_Pos) /*!< 0x00000400 */
+#define TIM_CCMR1_OC2FE TIM_CCMR1_OC2FE_Msk /*!<Output Compare 2 Fast enable */
+#define TIM_CCMR1_OC2PE_Pos (11U)
+#define TIM_CCMR1_OC2PE_Msk (0x1U << TIM_CCMR1_OC2PE_Pos) /*!< 0x00000800 */
+#define TIM_CCMR1_OC2PE TIM_CCMR1_OC2PE_Msk /*!<Output Compare 2 Preload enable */
+
+#define TIM_CCMR1_OC2M_Pos (12U)
+#define TIM_CCMR1_OC2M_Msk (0x7U << TIM_CCMR1_OC2M_Pos) /*!< 0x00007000 */
+#define TIM_CCMR1_OC2M TIM_CCMR1_OC2M_Msk /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
+#define TIM_CCMR1_OC2M_0 (0x1U << TIM_CCMR1_OC2M_Pos) /*!< 0x00001000 */
+#define TIM_CCMR1_OC2M_1 (0x2U << TIM_CCMR1_OC2M_Pos) /*!< 0x00002000 */
+#define TIM_CCMR1_OC2M_2 (0x4U << TIM_CCMR1_OC2M_Pos) /*!< 0x00004000 */
+
+#define TIM_CCMR1_OC2CE_Pos (15U)
+#define TIM_CCMR1_OC2CE_Msk (0x1U << TIM_CCMR1_OC2CE_Pos) /*!< 0x00008000 */
+#define TIM_CCMR1_OC2CE TIM_CCMR1_OC2CE_Msk /*!<Output Compare 2 Clear Enable */
+
+/*---------------------------------------------------------------------------*/
+
+#define TIM_CCMR1_IC1PSC_Pos (2U)
+#define TIM_CCMR1_IC1PSC_Msk (0x3U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x0000000C */
+#define TIM_CCMR1_IC1PSC TIM_CCMR1_IC1PSC_Msk /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
+#define TIM_CCMR1_IC1PSC_0 (0x1U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x00000004 */
+#define TIM_CCMR1_IC1PSC_1 (0x2U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x00000008 */
+
+#define TIM_CCMR1_IC1F_Pos (4U)
+#define TIM_CCMR1_IC1F_Msk (0xFU << TIM_CCMR1_IC1F_Pos) /*!< 0x000000F0 */
+#define TIM_CCMR1_IC1F TIM_CCMR1_IC1F_Msk /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
+#define TIM_CCMR1_IC1F_0 (0x1U << TIM_CCMR1_IC1F_Pos) /*!< 0x00000010 */
+#define TIM_CCMR1_IC1F_1 (0x2U << TIM_CCMR1_IC1F_Pos) /*!< 0x00000020 */
+#define TIM_CCMR1_IC1F_2 (0x4U << TIM_CCMR1_IC1F_Pos) /*!< 0x00000040 */
+#define TIM_CCMR1_IC1F_3 (0x8U << TIM_CCMR1_IC1F_Pos) /*!< 0x00000080 */
+
+#define TIM_CCMR1_IC2PSC_Pos (10U)
+#define TIM_CCMR1_IC2PSC_Msk (0x3U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000C00 */
+#define TIM_CCMR1_IC2PSC TIM_CCMR1_IC2PSC_Msk /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
+#define TIM_CCMR1_IC2PSC_0 (0x1U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000400 */
+#define TIM_CCMR1_IC2PSC_1 (0x2U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000800 */
+
+#define TIM_CCMR1_IC2F_Pos (12U)
+#define TIM_CCMR1_IC2F_Msk (0xFU << TIM_CCMR1_IC2F_Pos) /*!< 0x0000F000 */
+#define TIM_CCMR1_IC2F TIM_CCMR1_IC2F_Msk /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
+#define TIM_CCMR1_IC2F_0 (0x1U << TIM_CCMR1_IC2F_Pos) /*!< 0x00001000 */
+#define TIM_CCMR1_IC2F_1 (0x2U << TIM_CCMR1_IC2F_Pos) /*!< 0x00002000 */
+#define TIM_CCMR1_IC2F_2 (0x4U << TIM_CCMR1_IC2F_Pos) /*!< 0x00004000 */
+#define TIM_CCMR1_IC2F_3 (0x8U << TIM_CCMR1_IC2F_Pos) /*!< 0x00008000 */
+
+/****************** Bit definition for TIM_CCMR2 register ******************/
+#define TIM_CCMR2_CC3S_Pos (0U)
+#define TIM_CCMR2_CC3S_Msk (0x3U << TIM_CCMR2_CC3S_Pos) /*!< 0x00000003 */
+#define TIM_CCMR2_CC3S TIM_CCMR2_CC3S_Msk /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
+#define TIM_CCMR2_CC3S_0 (0x1U << TIM_CCMR2_CC3S_Pos) /*!< 0x00000001 */
+#define TIM_CCMR2_CC3S_1 (0x2U << TIM_CCMR2_CC3S_Pos) /*!< 0x00000002 */
+
+#define TIM_CCMR2_OC3FE_Pos (2U)
+#define TIM_CCMR2_OC3FE_Msk (0x1U << TIM_CCMR2_OC3FE_Pos) /*!< 0x00000004 */
+#define TIM_CCMR2_OC3FE TIM_CCMR2_OC3FE_Msk /*!<Output Compare 3 Fast enable */
+#define TIM_CCMR2_OC3PE_Pos (3U)
+#define TIM_CCMR2_OC3PE_Msk (0x1U << TIM_CCMR2_OC3PE_Pos) /*!< 0x00000008 */
+#define TIM_CCMR2_OC3PE TIM_CCMR2_OC3PE_Msk /*!<Output Compare 3 Preload enable */
+
+#define TIM_CCMR2_OC3M_Pos (4U)
+#define TIM_CCMR2_OC3M_Msk (0x7U << TIM_CCMR2_OC3M_Pos) /*!< 0x00000070 */
+#define TIM_CCMR2_OC3M TIM_CCMR2_OC3M_Msk /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
+#define TIM_CCMR2_OC3M_0 (0x1U << TIM_CCMR2_OC3M_Pos) /*!< 0x00000010 */
+#define TIM_CCMR2_OC3M_1 (0x2U << TIM_CCMR2_OC3M_Pos) /*!< 0x00000020 */
+#define TIM_CCMR2_OC3M_2 (0x4U << TIM_CCMR2_OC3M_Pos) /*!< 0x00000040 */
+
+#define TIM_CCMR2_OC3CE_Pos (7U)
+#define TIM_CCMR2_OC3CE_Msk (0x1U << TIM_CCMR2_OC3CE_Pos) /*!< 0x00000080 */
+#define TIM_CCMR2_OC3CE TIM_CCMR2_OC3CE_Msk /*!<Output Compare 3 Clear Enable */
+
+#define TIM_CCMR2_CC4S_Pos (8U)
+#define TIM_CCMR2_CC4S_Msk (0x3U << TIM_CCMR2_CC4S_Pos) /*!< 0x00000300 */
+#define TIM_CCMR2_CC4S TIM_CCMR2_CC4S_Msk /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
+#define TIM_CCMR2_CC4S_0 (0x1U << TIM_CCMR2_CC4S_Pos) /*!< 0x00000100 */
+#define TIM_CCMR2_CC4S_1 (0x2U << TIM_CCMR2_CC4S_Pos) /*!< 0x00000200 */
+
+#define TIM_CCMR2_OC4FE_Pos (10U)
+#define TIM_CCMR2_OC4FE_Msk (0x1U << TIM_CCMR2_OC4FE_Pos) /*!< 0x00000400 */
+#define TIM_CCMR2_OC4FE TIM_CCMR2_OC4FE_Msk /*!<Output Compare 4 Fast enable */
+#define TIM_CCMR2_OC4PE_Pos (11U)
+#define TIM_CCMR2_OC4PE_Msk (0x1U << TIM_CCMR2_OC4PE_Pos) /*!< 0x00000800 */
+#define TIM_CCMR2_OC4PE TIM_CCMR2_OC4PE_Msk /*!<Output Compare 4 Preload enable */
+
+#define TIM_CCMR2_OC4M_Pos (12U)
+#define TIM_CCMR2_OC4M_Msk (0x7U << TIM_CCMR2_OC4M_Pos) /*!< 0x00007000 */
+#define TIM_CCMR2_OC4M TIM_CCMR2_OC4M_Msk /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
+#define TIM_CCMR2_OC4M_0 (0x1U << TIM_CCMR2_OC4M_Pos) /*!< 0x00001000 */
+#define TIM_CCMR2_OC4M_1 (0x2U << TIM_CCMR2_OC4M_Pos) /*!< 0x00002000 */
+#define TIM_CCMR2_OC4M_2 (0x4U << TIM_CCMR2_OC4M_Pos) /*!< 0x00004000 */
+
+#define TIM_CCMR2_OC4CE_Pos (15U)
+#define TIM_CCMR2_OC4CE_Msk (0x1U << TIM_CCMR2_OC4CE_Pos) /*!< 0x00008000 */
+#define TIM_CCMR2_OC4CE TIM_CCMR2_OC4CE_Msk /*!<Output Compare 4 Clear Enable */
+
+/*---------------------------------------------------------------------------*/
+
+#define TIM_CCMR2_IC3PSC_Pos (2U)
+#define TIM_CCMR2_IC3PSC_Msk (0x3U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x0000000C */
+#define TIM_CCMR2_IC3PSC TIM_CCMR2_IC3PSC_Msk /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
+#define TIM_CCMR2_IC3PSC_0 (0x1U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x00000004 */
+#define TIM_CCMR2_IC3PSC_1 (0x2U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x00000008 */
+
+#define TIM_CCMR2_IC3F_Pos (4U)
+#define TIM_CCMR2_IC3F_Msk (0xFU << TIM_CCMR2_IC3F_Pos) /*!< 0x000000F0 */
+#define TIM_CCMR2_IC3F TIM_CCMR2_IC3F_Msk /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
+#define TIM_CCMR2_IC3F_0 (0x1U << TIM_CCMR2_IC3F_Pos) /*!< 0x00000010 */
+#define TIM_CCMR2_IC3F_1 (0x2U << TIM_CCMR2_IC3F_Pos) /*!< 0x00000020 */
+#define TIM_CCMR2_IC3F_2 (0x4U << TIM_CCMR2_IC3F_Pos) /*!< 0x00000040 */
+#define TIM_CCMR2_IC3F_3 (0x8U << TIM_CCMR2_IC3F_Pos) /*!< 0x00000080 */
+
+#define TIM_CCMR2_IC4PSC_Pos (10U)
+#define TIM_CCMR2_IC4PSC_Msk (0x3U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000C00 */
+#define TIM_CCMR2_IC4PSC TIM_CCMR2_IC4PSC_Msk /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
+#define TIM_CCMR2_IC4PSC_0 (0x1U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000400 */
+#define TIM_CCMR2_IC4PSC_1 (0x2U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000800 */
+
+#define TIM_CCMR2_IC4F_Pos (12U)
+#define TIM_CCMR2_IC4F_Msk (0xFU << TIM_CCMR2_IC4F_Pos) /*!< 0x0000F000 */
+#define TIM_CCMR2_IC4F TIM_CCMR2_IC4F_Msk /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
+#define TIM_CCMR2_IC4F_0 (0x1U << TIM_CCMR2_IC4F_Pos) /*!< 0x00001000 */
+#define TIM_CCMR2_IC4F_1 (0x2U << TIM_CCMR2_IC4F_Pos) /*!< 0x00002000 */
+#define TIM_CCMR2_IC4F_2 (0x4U << TIM_CCMR2_IC4F_Pos) /*!< 0x00004000 */
+#define TIM_CCMR2_IC4F_3 (0x8U << TIM_CCMR2_IC4F_Pos) /*!< 0x00008000 */
+
+/******************* Bit definition for TIM_CCER register ******************/
+#define TIM_CCER_CC1E_Pos (0U)
+#define TIM_CCER_CC1E_Msk (0x1U << TIM_CCER_CC1E_Pos) /*!< 0x00000001 */
+#define TIM_CCER_CC1E TIM_CCER_CC1E_Msk /*!<Capture/Compare 1 output enable */
+#define TIM_CCER_CC1P_Pos (1U)
+#define TIM_CCER_CC1P_Msk (0x1U << TIM_CCER_CC1P_Pos) /*!< 0x00000002 */
+#define TIM_CCER_CC1P TIM_CCER_CC1P_Msk /*!<Capture/Compare 1 output Polarity */
+#define TIM_CCER_CC1NE_Pos (2U)
+#define TIM_CCER_CC1NE_Msk (0x1U << TIM_CCER_CC1NE_Pos) /*!< 0x00000004 */
+#define TIM_CCER_CC1NE TIM_CCER_CC1NE_Msk /*!<Capture/Compare 1 Complementary output enable */
+#define TIM_CCER_CC1NP_Pos (3U)
+#define TIM_CCER_CC1NP_Msk (0x1U << TIM_CCER_CC1NP_Pos) /*!< 0x00000008 */
+#define TIM_CCER_CC1NP TIM_CCER_CC1NP_Msk /*!<Capture/Compare 1 Complementary output Polarity */
+#define TIM_CCER_CC2E_Pos (4U)
+#define TIM_CCER_CC2E_Msk (0x1U << TIM_CCER_CC2E_Pos) /*!< 0x00000010 */
+#define TIM_CCER_CC2E TIM_CCER_CC2E_Msk /*!<Capture/Compare 2 output enable */
+#define TIM_CCER_CC2P_Pos (5U)
+#define TIM_CCER_CC2P_Msk (0x1U << TIM_CCER_CC2P_Pos) /*!< 0x00000020 */
+#define TIM_CCER_CC2P TIM_CCER_CC2P_Msk /*!<Capture/Compare 2 output Polarity */
+#define TIM_CCER_CC2NE_Pos (6U)
+#define TIM_CCER_CC2NE_Msk (0x1U << TIM_CCER_CC2NE_Pos) /*!< 0x00000040 */
+#define TIM_CCER_CC2NE TIM_CCER_CC2NE_Msk /*!<Capture/Compare 2 Complementary output enable */
+#define TIM_CCER_CC2NP_Pos (7U)
+#define TIM_CCER_CC2NP_Msk (0x1U << TIM_CCER_CC2NP_Pos) /*!< 0x00000080 */
+#define TIM_CCER_CC2NP TIM_CCER_CC2NP_Msk /*!<Capture/Compare 2 Complementary output Polarity */
+#define TIM_CCER_CC3E_Pos (8U)
+#define TIM_CCER_CC3E_Msk (0x1U << TIM_CCER_CC3E_Pos) /*!< 0x00000100 */
+#define TIM_CCER_CC3E TIM_CCER_CC3E_Msk /*!<Capture/Compare 3 output enable */
+#define TIM_CCER_CC3P_Pos (9U)
+#define TIM_CCER_CC3P_Msk (0x1U << TIM_CCER_CC3P_Pos) /*!< 0x00000200 */
+#define TIM_CCER_CC3P TIM_CCER_CC3P_Msk /*!<Capture/Compare 3 output Polarity */
+#define TIM_CCER_CC3NE_Pos (10U)
+#define TIM_CCER_CC3NE_Msk (0x1U << TIM_CCER_CC3NE_Pos) /*!< 0x00000400 */
+#define TIM_CCER_CC3NE TIM_CCER_CC3NE_Msk /*!<Capture/Compare 3 Complementary output enable */
+#define TIM_CCER_CC3NP_Pos (11U)
+#define TIM_CCER_CC3NP_Msk (0x1U << TIM_CCER_CC3NP_Pos) /*!< 0x00000800 */
+#define TIM_CCER_CC3NP TIM_CCER_CC3NP_Msk /*!<Capture/Compare 3 Complementary output Polarity */
+#define TIM_CCER_CC4E_Pos (12U)
+#define TIM_CCER_CC4E_Msk (0x1U << TIM_CCER_CC4E_Pos) /*!< 0x00001000 */
+#define TIM_CCER_CC4E TIM_CCER_CC4E_Msk /*!<Capture/Compare 4 output enable */
+#define TIM_CCER_CC4P_Pos (13U)
+#define TIM_CCER_CC4P_Msk (0x1U << TIM_CCER_CC4P_Pos) /*!< 0x00002000 */
+#define TIM_CCER_CC4P TIM_CCER_CC4P_Msk /*!<Capture/Compare 4 output Polarity */
+#define TIM_CCER_CC4NP_Pos (15U)
+#define TIM_CCER_CC4NP_Msk (0x1U << TIM_CCER_CC4NP_Pos) /*!< 0x00008000 */
+#define TIM_CCER_CC4NP TIM_CCER_CC4NP_Msk /*!<Capture/Compare 4 Complementary output Polarity */
+
+/******************* Bit definition for TIM_CNT register *******************/
+#define TIM_CNT_CNT_Pos (0U)
+#define TIM_CNT_CNT_Msk (0xFFFFFFFFU << TIM_CNT_CNT_Pos) /*!< 0xFFFFFFFF */
+#define TIM_CNT_CNT TIM_CNT_CNT_Msk /*!<Counter Value */
+
+/******************* Bit definition for TIM_PSC register *******************/
+#define TIM_PSC_PSC_Pos (0U)
+#define TIM_PSC_PSC_Msk (0xFFFFU << TIM_PSC_PSC_Pos) /*!< 0x0000FFFF */
+#define TIM_PSC_PSC TIM_PSC_PSC_Msk /*!<Prescaler Value */
+
+/******************* Bit definition for TIM_ARR register *******************/
+#define TIM_ARR_ARR_Pos (0U)
+#define TIM_ARR_ARR_Msk (0xFFFFFFFFU << TIM_ARR_ARR_Pos) /*!< 0xFFFFFFFF */
+#define TIM_ARR_ARR TIM_ARR_ARR_Msk /*!<actual auto-reload Value */
+
+/******************* Bit definition for TIM_RCR register *******************/
+#define TIM_RCR_REP_Pos (0U)
+#define TIM_RCR_REP_Msk (0xFFU << TIM_RCR_REP_Pos) /*!< 0x000000FF */
+#define TIM_RCR_REP TIM_RCR_REP_Msk /*!<Repetition Counter Value */
+
+/******************* Bit definition for TIM_CCR1 register ******************/
+#define TIM_CCR1_CCR1_Pos (0U)
+#define TIM_CCR1_CCR1_Msk (0xFFFFU << TIM_CCR1_CCR1_Pos) /*!< 0x0000FFFF */
+#define TIM_CCR1_CCR1 TIM_CCR1_CCR1_Msk /*!<Capture/Compare 1 Value */
+
+/******************* Bit definition for TIM_CCR2 register ******************/
+#define TIM_CCR2_CCR2_Pos (0U)
+#define TIM_CCR2_CCR2_Msk (0xFFFFU << TIM_CCR2_CCR2_Pos) /*!< 0x0000FFFF */
+#define TIM_CCR2_CCR2 TIM_CCR2_CCR2_Msk /*!<Capture/Compare 2 Value */
+
+/******************* Bit definition for TIM_CCR3 register ******************/
+#define TIM_CCR3_CCR3_Pos (0U)
+#define TIM_CCR3_CCR3_Msk (0xFFFFU << TIM_CCR3_CCR3_Pos) /*!< 0x0000FFFF */
+#define TIM_CCR3_CCR3 TIM_CCR3_CCR3_Msk /*!<Capture/Compare 3 Value */
+
+/******************* Bit definition for TIM_CCR4 register ******************/
+#define TIM_CCR4_CCR4_Pos (0U)
+#define TIM_CCR4_CCR4_Msk (0xFFFFU << TIM_CCR4_CCR4_Pos) /*!< 0x0000FFFF */
+#define TIM_CCR4_CCR4 TIM_CCR4_CCR4_Msk /*!<Capture/Compare 4 Value */
+
+/******************* Bit definition for TIM_BDTR register ******************/
+#define TIM_BDTR_DTG_Pos (0U)
+#define TIM_BDTR_DTG_Msk (0xFFU << TIM_BDTR_DTG_Pos) /*!< 0x000000FF */
+#define TIM_BDTR_DTG TIM_BDTR_DTG_Msk /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
+#define TIM_BDTR_DTG_0 (0x01U << TIM_BDTR_DTG_Pos) /*!< 0x00000001 */
+#define TIM_BDTR_DTG_1 (0x02U << TIM_BDTR_DTG_Pos) /*!< 0x00000002 */
+#define TIM_BDTR_DTG_2 (0x04U << TIM_BDTR_DTG_Pos) /*!< 0x00000004 */
+#define TIM_BDTR_DTG_3 (0x08U << TIM_BDTR_DTG_Pos) /*!< 0x00000008 */
+#define TIM_BDTR_DTG_4 (0x10U << TIM_BDTR_DTG_Pos) /*!< 0x00000010 */
+#define TIM_BDTR_DTG_5 (0x20U << TIM_BDTR_DTG_Pos) /*!< 0x00000020 */
+#define TIM_BDTR_DTG_6 (0x40U << TIM_BDTR_DTG_Pos) /*!< 0x00000040 */
+#define TIM_BDTR_DTG_7 (0x80U << TIM_BDTR_DTG_Pos) /*!< 0x00000080 */
+
+#define TIM_BDTR_LOCK_Pos (8U)
+#define TIM_BDTR_LOCK_Msk (0x3U << TIM_BDTR_LOCK_Pos) /*!< 0x00000300 */
+#define TIM_BDTR_LOCK TIM_BDTR_LOCK_Msk /*!<LOCK[1:0] bits (Lock Configuration) */
+#define TIM_BDTR_LOCK_0 (0x1U << TIM_BDTR_LOCK_Pos) /*!< 0x00000100 */
+#define TIM_BDTR_LOCK_1 (0x2U << TIM_BDTR_LOCK_Pos) /*!< 0x00000200 */
+
+#define TIM_BDTR_OSSI_Pos (10U)
+#define TIM_BDTR_OSSI_Msk (0x1U << TIM_BDTR_OSSI_Pos) /*!< 0x00000400 */
+#define TIM_BDTR_OSSI TIM_BDTR_OSSI_Msk /*!<Off-State Selection for Idle mode */
+#define TIM_BDTR_OSSR_Pos (11U)
+#define TIM_BDTR_OSSR_Msk (0x1U << TIM_BDTR_OSSR_Pos) /*!< 0x00000800 */
+#define TIM_BDTR_OSSR TIM_BDTR_OSSR_Msk /*!<Off-State Selection for Run mode */
+#define TIM_BDTR_BKE_Pos (12U)
+#define TIM_BDTR_BKE_Msk (0x1U << TIM_BDTR_BKE_Pos) /*!< 0x00001000 */
+#define TIM_BDTR_BKE TIM_BDTR_BKE_Msk /*!<Break enable */
+#define TIM_BDTR_BKP_Pos (13U)
+#define TIM_BDTR_BKP_Msk (0x1U << TIM_BDTR_BKP_Pos) /*!< 0x00002000 */
+#define TIM_BDTR_BKP TIM_BDTR_BKP_Msk /*!<Break Polarity */
+#define TIM_BDTR_AOE_Pos (14U)
+#define TIM_BDTR_AOE_Msk (0x1U << TIM_BDTR_AOE_Pos) /*!< 0x00004000 */
+#define TIM_BDTR_AOE TIM_BDTR_AOE_Msk /*!<Automatic Output enable */
+#define TIM_BDTR_MOE_Pos (15U)
+#define TIM_BDTR_MOE_Msk (0x1U << TIM_BDTR_MOE_Pos) /*!< 0x00008000 */
+#define TIM_BDTR_MOE TIM_BDTR_MOE_Msk /*!<Main Output enable */
+
+/******************* Bit definition for TIM_DCR register *******************/
+#define TIM_DCR_DBA_Pos (0U)
+#define TIM_DCR_DBA_Msk (0x1FU << TIM_DCR_DBA_Pos) /*!< 0x0000001F */
+#define TIM_DCR_DBA TIM_DCR_DBA_Msk /*!<DBA[4:0] bits (DMA Base Address) */
+#define TIM_DCR_DBA_0 (0x01U << TIM_DCR_DBA_Pos) /*!< 0x00000001 */
+#define TIM_DCR_DBA_1 (0x02U << TIM_DCR_DBA_Pos) /*!< 0x00000002 */
+#define TIM_DCR_DBA_2 (0x04U << TIM_DCR_DBA_Pos) /*!< 0x00000004 */
+#define TIM_DCR_DBA_3 (0x08U << TIM_DCR_DBA_Pos) /*!< 0x00000008 */
+#define TIM_DCR_DBA_4 (0x10U << TIM_DCR_DBA_Pos) /*!< 0x00000010 */
+
+#define TIM_DCR_DBL_Pos (8U)
+#define TIM_DCR_DBL_Msk (0x1FU << TIM_DCR_DBL_Pos) /*!< 0x00001F00 */
+#define TIM_DCR_DBL TIM_DCR_DBL_Msk /*!<DBL[4:0] bits (DMA Burst Length) */
+#define TIM_DCR_DBL_0 (0x01U << TIM_DCR_DBL_Pos) /*!< 0x00000100 */
+#define TIM_DCR_DBL_1 (0x02U << TIM_DCR_DBL_Pos) /*!< 0x00000200 */
+#define TIM_DCR_DBL_2 (0x04U << TIM_DCR_DBL_Pos) /*!< 0x00000400 */
+#define TIM_DCR_DBL_3 (0x08U << TIM_DCR_DBL_Pos) /*!< 0x00000800 */
+#define TIM_DCR_DBL_4 (0x10U << TIM_DCR_DBL_Pos) /*!< 0x00001000 */
+
+/******************* Bit definition for TIM_DMAR register ******************/
+#define TIM_DMAR_DMAB_Pos (0U)
+#define TIM_DMAR_DMAB_Msk (0xFFFFU << TIM_DMAR_DMAB_Pos) /*!< 0x0000FFFF */
+#define TIM_DMAR_DMAB TIM_DMAR_DMAB_Msk /*!<DMA register for burst accesses */
+
+/******************* Bit definition for TIM_OR register ********************/
+
+/******************************************************************************/
+/* */
+/* Real-Time Clock */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for RTC_CRH register ********************/
+#define RTC_CRH_SECIE_Pos (0U)
+#define RTC_CRH_SECIE_Msk (0x1U << RTC_CRH_SECIE_Pos) /*!< 0x00000001 */
+#define RTC_CRH_SECIE RTC_CRH_SECIE_Msk /*!< Second Interrupt Enable */
+#define RTC_CRH_ALRIE_Pos (1U)
+#define RTC_CRH_ALRIE_Msk (0x1U << RTC_CRH_ALRIE_Pos) /*!< 0x00000002 */
+#define RTC_CRH_ALRIE RTC_CRH_ALRIE_Msk /*!< Alarm Interrupt Enable */
+#define RTC_CRH_OWIE_Pos (2U)
+#define RTC_CRH_OWIE_Msk (0x1U << RTC_CRH_OWIE_Pos) /*!< 0x00000004 */
+#define RTC_CRH_OWIE RTC_CRH_OWIE_Msk /*!< OverfloW Interrupt Enable */
+
+/******************* Bit definition for RTC_CRL register ********************/
+#define RTC_CRL_SECF_Pos (0U)
+#define RTC_CRL_SECF_Msk (0x1U << RTC_CRL_SECF_Pos) /*!< 0x00000001 */
+#define RTC_CRL_SECF RTC_CRL_SECF_Msk /*!< Second Flag */
+#define RTC_CRL_ALRF_Pos (1U)
+#define RTC_CRL_ALRF_Msk (0x1U << RTC_CRL_ALRF_Pos) /*!< 0x00000002 */
+#define RTC_CRL_ALRF RTC_CRL_ALRF_Msk /*!< Alarm Flag */
+#define RTC_CRL_OWF_Pos (2U)
+#define RTC_CRL_OWF_Msk (0x1U << RTC_CRL_OWF_Pos) /*!< 0x00000004 */
+#define RTC_CRL_OWF RTC_CRL_OWF_Msk /*!< OverfloW Flag */
+#define RTC_CRL_RSF_Pos (3U)
+#define RTC_CRL_RSF_Msk (0x1U << RTC_CRL_RSF_Pos) /*!< 0x00000008 */
+#define RTC_CRL_RSF RTC_CRL_RSF_Msk /*!< Registers Synchronized Flag */
+#define RTC_CRL_CNF_Pos (4U)
+#define RTC_CRL_CNF_Msk (0x1U << RTC_CRL_CNF_Pos) /*!< 0x00000010 */
+#define RTC_CRL_CNF RTC_CRL_CNF_Msk /*!< Configuration Flag */
+#define RTC_CRL_RTOFF_Pos (5U)
+#define RTC_CRL_RTOFF_Msk (0x1U << RTC_CRL_RTOFF_Pos) /*!< 0x00000020 */
+#define RTC_CRL_RTOFF RTC_CRL_RTOFF_Msk /*!< RTC operation OFF */
+
+/******************* Bit definition for RTC_PRLH register *******************/
+#define RTC_PRLH_PRL_Pos (0U)
+#define RTC_PRLH_PRL_Msk (0xFU << RTC_PRLH_PRL_Pos) /*!< 0x0000000F */
+#define RTC_PRLH_PRL RTC_PRLH_PRL_Msk /*!< RTC Prescaler Reload Value High */
+
+/******************* Bit definition for RTC_PRLL register *******************/
+#define RTC_PRLL_PRL_Pos (0U)
+#define RTC_PRLL_PRL_Msk (0xFFFFU << RTC_PRLL_PRL_Pos) /*!< 0x0000FFFF */
+#define RTC_PRLL_PRL RTC_PRLL_PRL_Msk /*!< RTC Prescaler Reload Value Low */
+
+/******************* Bit definition for RTC_DIVH register *******************/
+#define RTC_DIVH_RTC_DIV_Pos (0U)
+#define RTC_DIVH_RTC_DIV_Msk (0xFU << RTC_DIVH_RTC_DIV_Pos) /*!< 0x0000000F */
+#define RTC_DIVH_RTC_DIV RTC_DIVH_RTC_DIV_Msk /*!< RTC Clock Divider High */
+
+/******************* Bit definition for RTC_DIVL register *******************/
+#define RTC_DIVL_RTC_DIV_Pos (0U)
+#define RTC_DIVL_RTC_DIV_Msk (0xFFFFU << RTC_DIVL_RTC_DIV_Pos) /*!< 0x0000FFFF */
+#define RTC_DIVL_RTC_DIV RTC_DIVL_RTC_DIV_Msk /*!< RTC Clock Divider Low */
+
+/******************* Bit definition for RTC_CNTH register *******************/
+#define RTC_CNTH_RTC_CNT_Pos (0U)
+#define RTC_CNTH_RTC_CNT_Msk (0xFFFFU << RTC_CNTH_RTC_CNT_Pos) /*!< 0x0000FFFF */
+#define RTC_CNTH_RTC_CNT RTC_CNTH_RTC_CNT_Msk /*!< RTC Counter High */
+
+/******************* Bit definition for RTC_CNTL register *******************/
+#define RTC_CNTL_RTC_CNT_Pos (0U)
+#define RTC_CNTL_RTC_CNT_Msk (0xFFFFU << RTC_CNTL_RTC_CNT_Pos) /*!< 0x0000FFFF */
+#define RTC_CNTL_RTC_CNT RTC_CNTL_RTC_CNT_Msk /*!< RTC Counter Low */
+
+/******************* Bit definition for RTC_ALRH register *******************/
+#define RTC_ALRH_RTC_ALR_Pos (0U)
+#define RTC_ALRH_RTC_ALR_Msk (0xFFFFU << RTC_ALRH_RTC_ALR_Pos) /*!< 0x0000FFFF */
+#define RTC_ALRH_RTC_ALR RTC_ALRH_RTC_ALR_Msk /*!< RTC Alarm High */
+
+/******************* Bit definition for RTC_ALRL register *******************/
+#define RTC_ALRL_RTC_ALR_Pos (0U)
+#define RTC_ALRL_RTC_ALR_Msk (0xFFFFU << RTC_ALRL_RTC_ALR_Pos) /*!< 0x0000FFFF */
+#define RTC_ALRL_RTC_ALR RTC_ALRL_RTC_ALR_Msk /*!< RTC Alarm Low */
+
+/******************************************************************************/
+/* */
+/* Independent WATCHDOG (IWDG) */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for IWDG_KR register ********************/
+#define IWDG_KR_KEY_Pos (0U)
+#define IWDG_KR_KEY_Msk (0xFFFFU << IWDG_KR_KEY_Pos) /*!< 0x0000FFFF */
+#define IWDG_KR_KEY IWDG_KR_KEY_Msk /*!< Key value (write only, read 0000h) */
+
+/******************* Bit definition for IWDG_PR register ********************/
+#define IWDG_PR_PR_Pos (0U)
+#define IWDG_PR_PR_Msk (0x7U << IWDG_PR_PR_Pos) /*!< 0x00000007 */
+#define IWDG_PR_PR IWDG_PR_PR_Msk /*!< PR[2:0] (Prescaler divider) */
+#define IWDG_PR_PR_0 (0x1U << IWDG_PR_PR_Pos) /*!< 0x00000001 */
+#define IWDG_PR_PR_1 (0x2U << IWDG_PR_PR_Pos) /*!< 0x00000002 */
+#define IWDG_PR_PR_2 (0x4U << IWDG_PR_PR_Pos) /*!< 0x00000004 */
+
+/******************* Bit definition for IWDG_RLR register *******************/
+#define IWDG_RLR_RL_Pos (0U)
+#define IWDG_RLR_RL_Msk (0xFFFU << IWDG_RLR_RL_Pos) /*!< 0x00000FFF */
+#define IWDG_RLR_RL IWDG_RLR_RL_Msk /*!< Watchdog counter reload value */
+
+/******************* Bit definition for IWDG_SR register ********************/
+#define IWDG_SR_PVU_Pos (0U)
+#define IWDG_SR_PVU_Msk (0x1U << IWDG_SR_PVU_Pos) /*!< 0x00000001 */
+#define IWDG_SR_PVU IWDG_SR_PVU_Msk /*!< Watchdog prescaler value update */
+#define IWDG_SR_RVU_Pos (1U)
+#define IWDG_SR_RVU_Msk (0x1U << IWDG_SR_RVU_Pos) /*!< 0x00000002 */
+#define IWDG_SR_RVU IWDG_SR_RVU_Msk /*!< Watchdog counter reload value update */
+
+/******************************************************************************/
+/* */
+/* Window WATCHDOG (WWDG) */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for WWDG_CR register ********************/
+#define WWDG_CR_T_Pos (0U)
+#define WWDG_CR_T_Msk (0x7FU << WWDG_CR_T_Pos) /*!< 0x0000007F */
+#define WWDG_CR_T WWDG_CR_T_Msk /*!< T[6:0] bits (7-Bit counter (MSB to LSB)) */
+#define WWDG_CR_T_0 (0x01U << WWDG_CR_T_Pos) /*!< 0x00000001 */
+#define WWDG_CR_T_1 (0x02U << WWDG_CR_T_Pos) /*!< 0x00000002 */
+#define WWDG_CR_T_2 (0x04U << WWDG_CR_T_Pos) /*!< 0x00000004 */
+#define WWDG_CR_T_3 (0x08U << WWDG_CR_T_Pos) /*!< 0x00000008 */
+#define WWDG_CR_T_4 (0x10U << WWDG_CR_T_Pos) /*!< 0x00000010 */
+#define WWDG_CR_T_5 (0x20U << WWDG_CR_T_Pos) /*!< 0x00000020 */
+#define WWDG_CR_T_6 (0x40U << WWDG_CR_T_Pos) /*!< 0x00000040 */
+
+/* Legacy defines */
+#define WWDG_CR_T0 WWDG_CR_T_0
+#define WWDG_CR_T1 WWDG_CR_T_1
+#define WWDG_CR_T2 WWDG_CR_T_2
+#define WWDG_CR_T3 WWDG_CR_T_3
+#define WWDG_CR_T4 WWDG_CR_T_4
+#define WWDG_CR_T5 WWDG_CR_T_5
+#define WWDG_CR_T6 WWDG_CR_T_6
+
+#define WWDG_CR_WDGA_Pos (7U)
+#define WWDG_CR_WDGA_Msk (0x1U << WWDG_CR_WDGA_Pos) /*!< 0x00000080 */
+#define WWDG_CR_WDGA WWDG_CR_WDGA_Msk /*!< Activation bit */
+
+/******************* Bit definition for WWDG_CFR register *******************/
+#define WWDG_CFR_W_Pos (0U)
+#define WWDG_CFR_W_Msk (0x7FU << WWDG_CFR_W_Pos) /*!< 0x0000007F */
+#define WWDG_CFR_W WWDG_CFR_W_Msk /*!< W[6:0] bits (7-bit window value) */
+#define WWDG_CFR_W_0 (0x01U << WWDG_CFR_W_Pos) /*!< 0x00000001 */
+#define WWDG_CFR_W_1 (0x02U << WWDG_CFR_W_Pos) /*!< 0x00000002 */
+#define WWDG_CFR_W_2 (0x04U << WWDG_CFR_W_Pos) /*!< 0x00000004 */
+#define WWDG_CFR_W_3 (0x08U << WWDG_CFR_W_Pos) /*!< 0x00000008 */
+#define WWDG_CFR_W_4 (0x10U << WWDG_CFR_W_Pos) /*!< 0x00000010 */
+#define WWDG_CFR_W_5 (0x20U << WWDG_CFR_W_Pos) /*!< 0x00000020 */
+#define WWDG_CFR_W_6 (0x40U << WWDG_CFR_W_Pos) /*!< 0x00000040 */
+
+/* Legacy defines */
+#define WWDG_CFR_W0 WWDG_CFR_W_0
+#define WWDG_CFR_W1 WWDG_CFR_W_1
+#define WWDG_CFR_W2 WWDG_CFR_W_2
+#define WWDG_CFR_W3 WWDG_CFR_W_3
+#define WWDG_CFR_W4 WWDG_CFR_W_4
+#define WWDG_CFR_W5 WWDG_CFR_W_5
+#define WWDG_CFR_W6 WWDG_CFR_W_6
+
+#define WWDG_CFR_WDGTB_Pos (7U)
+#define WWDG_CFR_WDGTB_Msk (0x3U << WWDG_CFR_WDGTB_Pos) /*!< 0x00000180 */
+#define WWDG_CFR_WDGTB WWDG_CFR_WDGTB_Msk /*!< WDGTB[1:0] bits (Timer Base) */
+#define WWDG_CFR_WDGTB_0 (0x1U << WWDG_CFR_WDGTB_Pos) /*!< 0x00000080 */
+#define WWDG_CFR_WDGTB_1 (0x2U << WWDG_CFR_WDGTB_Pos) /*!< 0x00000100 */
+
+/* Legacy defines */
+#define WWDG_CFR_WDGTB0 WWDG_CFR_WDGTB_0
+#define WWDG_CFR_WDGTB1 WWDG_CFR_WDGTB_1
+
+#define WWDG_CFR_EWI_Pos (9U)
+#define WWDG_CFR_EWI_Msk (0x1U << WWDG_CFR_EWI_Pos) /*!< 0x00000200 */
+#define WWDG_CFR_EWI WWDG_CFR_EWI_Msk /*!< Early Wakeup Interrupt */
+
+/******************* Bit definition for WWDG_SR register ********************/
+#define WWDG_SR_EWIF_Pos (0U)
+#define WWDG_SR_EWIF_Msk (0x1U << WWDG_SR_EWIF_Pos) /*!< 0x00000001 */
+#define WWDG_SR_EWIF WWDG_SR_EWIF_Msk /*!< Early Wakeup Interrupt Flag */
+
+
+/******************************************************************************/
+/* */
+/* SD host Interface */
+/* */
+/******************************************************************************/
+
+/****************** Bit definition for SDIO_POWER register ******************/
+#define SDIO_POWER_PWRCTRL_Pos (0U)
+#define SDIO_POWER_PWRCTRL_Msk (0x3U << SDIO_POWER_PWRCTRL_Pos) /*!< 0x00000003 */
+#define SDIO_POWER_PWRCTRL SDIO_POWER_PWRCTRL_Msk /*!< PWRCTRL[1:0] bits (Power supply control bits) */
+#define SDIO_POWER_PWRCTRL_0 (0x1U << SDIO_POWER_PWRCTRL_Pos) /*!< 0x01 */
+#define SDIO_POWER_PWRCTRL_1 (0x2U << SDIO_POWER_PWRCTRL_Pos) /*!< 0x02 */
+
+/****************** Bit definition for SDIO_CLKCR register ******************/
+#define SDIO_CLKCR_CLKDIV_Pos (0U)
+#define SDIO_CLKCR_CLKDIV_Msk (0xFFU << SDIO_CLKCR_CLKDIV_Pos) /*!< 0x000000FF */
+#define SDIO_CLKCR_CLKDIV SDIO_CLKCR_CLKDIV_Msk /*!< Clock divide factor */
+#define SDIO_CLKCR_CLKEN_Pos (8U)
+#define SDIO_CLKCR_CLKEN_Msk (0x1U << SDIO_CLKCR_CLKEN_Pos) /*!< 0x00000100 */
+#define SDIO_CLKCR_CLKEN SDIO_CLKCR_CLKEN_Msk /*!< Clock enable bit */
+#define SDIO_CLKCR_PWRSAV_Pos (9U)
+#define SDIO_CLKCR_PWRSAV_Msk (0x1U << SDIO_CLKCR_PWRSAV_Pos) /*!< 0x00000200 */
+#define SDIO_CLKCR_PWRSAV SDIO_CLKCR_PWRSAV_Msk /*!< Power saving configuration bit */
+#define SDIO_CLKCR_BYPASS_Pos (10U)
+#define SDIO_CLKCR_BYPASS_Msk (0x1U << SDIO_CLKCR_BYPASS_Pos) /*!< 0x00000400 */
+#define SDIO_CLKCR_BYPASS SDIO_CLKCR_BYPASS_Msk /*!< Clock divider bypass enable bit */
+
+#define SDIO_CLKCR_WIDBUS_Pos (11U)
+#define SDIO_CLKCR_WIDBUS_Msk (0x3U << SDIO_CLKCR_WIDBUS_Pos) /*!< 0x00001800 */
+#define SDIO_CLKCR_WIDBUS SDIO_CLKCR_WIDBUS_Msk /*!< WIDBUS[1:0] bits (Wide bus mode enable bit) */
+#define SDIO_CLKCR_WIDBUS_0 (0x1U << SDIO_CLKCR_WIDBUS_Pos) /*!< 0x0800 */
+#define SDIO_CLKCR_WIDBUS_1 (0x2U << SDIO_CLKCR_WIDBUS_Pos) /*!< 0x1000 */
+
+#define SDIO_CLKCR_NEGEDGE_Pos (13U)
+#define SDIO_CLKCR_NEGEDGE_Msk (0x1U << SDIO_CLKCR_NEGEDGE_Pos) /*!< 0x00002000 */
+#define SDIO_CLKCR_NEGEDGE SDIO_CLKCR_NEGEDGE_Msk /*!< SDIO_CK dephasing selection bit */
+#define SDIO_CLKCR_HWFC_EN_Pos (14U)
+#define SDIO_CLKCR_HWFC_EN_Msk (0x1U << SDIO_CLKCR_HWFC_EN_Pos) /*!< 0x00004000 */
+#define SDIO_CLKCR_HWFC_EN SDIO_CLKCR_HWFC_EN_Msk /*!< HW Flow Control enable */
+
+/******************* Bit definition for SDIO_ARG register *******************/
+#define SDIO_ARG_CMDARG_Pos (0U)
+#define SDIO_ARG_CMDARG_Msk (0xFFFFFFFFU << SDIO_ARG_CMDARG_Pos) /*!< 0xFFFFFFFF */
+#define SDIO_ARG_CMDARG SDIO_ARG_CMDARG_Msk /*!< Command argument */
+
+/******************* Bit definition for SDIO_CMD register *******************/
+#define SDIO_CMD_CMDINDEX_Pos (0U)
+#define SDIO_CMD_CMDINDEX_Msk (0x3FU << SDIO_CMD_CMDINDEX_Pos) /*!< 0x0000003F */
+#define SDIO_CMD_CMDINDEX SDIO_CMD_CMDINDEX_Msk /*!< Command Index */
+
+#define SDIO_CMD_WAITRESP_Pos (6U)
+#define SDIO_CMD_WAITRESP_Msk (0x3U << SDIO_CMD_WAITRESP_Pos) /*!< 0x000000C0 */
+#define SDIO_CMD_WAITRESP SDIO_CMD_WAITRESP_Msk /*!< WAITRESP[1:0] bits (Wait for response bits) */
+#define SDIO_CMD_WAITRESP_0 (0x1U << SDIO_CMD_WAITRESP_Pos) /*!< 0x0040 */
+#define SDIO_CMD_WAITRESP_1 (0x2U << SDIO_CMD_WAITRESP_Pos) /*!< 0x0080 */
+
+#define SDIO_CMD_WAITINT_Pos (8U)
+#define SDIO_CMD_WAITINT_Msk (0x1U << SDIO_CMD_WAITINT_Pos) /*!< 0x00000100 */
+#define SDIO_CMD_WAITINT SDIO_CMD_WAITINT_Msk /*!< CPSM Waits for Interrupt Request */
+#define SDIO_CMD_WAITPEND_Pos (9U)
+#define SDIO_CMD_WAITPEND_Msk (0x1U << SDIO_CMD_WAITPEND_Pos) /*!< 0x00000200 */
+#define SDIO_CMD_WAITPEND SDIO_CMD_WAITPEND_Msk /*!< CPSM Waits for ends of data transfer (CmdPend internal signal) */
+#define SDIO_CMD_CPSMEN_Pos (10U)
+#define SDIO_CMD_CPSMEN_Msk (0x1U << SDIO_CMD_CPSMEN_Pos) /*!< 0x00000400 */
+#define SDIO_CMD_CPSMEN SDIO_CMD_CPSMEN_Msk /*!< Command path state machine (CPSM) Enable bit */
+#define SDIO_CMD_SDIOSUSPEND_Pos (11U)
+#define SDIO_CMD_SDIOSUSPEND_Msk (0x1U << SDIO_CMD_SDIOSUSPEND_Pos) /*!< 0x00000800 */
+#define SDIO_CMD_SDIOSUSPEND SDIO_CMD_SDIOSUSPEND_Msk /*!< SD I/O suspend command */
+#define SDIO_CMD_ENCMDCOMPL_Pos (12U)
+#define SDIO_CMD_ENCMDCOMPL_Msk (0x1U << SDIO_CMD_ENCMDCOMPL_Pos) /*!< 0x00001000 */
+#define SDIO_CMD_ENCMDCOMPL SDIO_CMD_ENCMDCOMPL_Msk /*!< Enable CMD completion */
+#define SDIO_CMD_NIEN_Pos (13U)
+#define SDIO_CMD_NIEN_Msk (0x1U << SDIO_CMD_NIEN_Pos) /*!< 0x00002000 */
+#define SDIO_CMD_NIEN SDIO_CMD_NIEN_Msk /*!< Not Interrupt Enable */
+#define SDIO_CMD_CEATACMD_Pos (14U)
+#define SDIO_CMD_CEATACMD_Msk (0x1U << SDIO_CMD_CEATACMD_Pos) /*!< 0x00004000 */
+#define SDIO_CMD_CEATACMD SDIO_CMD_CEATACMD_Msk /*!< CE-ATA command */
+
+/***************** Bit definition for SDIO_RESPCMD register *****************/
+#define SDIO_RESPCMD_RESPCMD_Pos (0U)
+#define SDIO_RESPCMD_RESPCMD_Msk (0x3FU << SDIO_RESPCMD_RESPCMD_Pos) /*!< 0x0000003F */
+#define SDIO_RESPCMD_RESPCMD SDIO_RESPCMD_RESPCMD_Msk /*!< Response command index */
+
+/****************** Bit definition for SDIO_RESP0 register ******************/
+#define SDIO_RESP0_CARDSTATUS0_Pos (0U)
+#define SDIO_RESP0_CARDSTATUS0_Msk (0xFFFFFFFFU << SDIO_RESP0_CARDSTATUS0_Pos) /*!< 0xFFFFFFFF */
+#define SDIO_RESP0_CARDSTATUS0 SDIO_RESP0_CARDSTATUS0_Msk /*!< Card Status */
+
+/****************** Bit definition for SDIO_RESP1 register ******************/
+#define SDIO_RESP1_CARDSTATUS1_Pos (0U)
+#define SDIO_RESP1_CARDSTATUS1_Msk (0xFFFFFFFFU << SDIO_RESP1_CARDSTATUS1_Pos) /*!< 0xFFFFFFFF */
+#define SDIO_RESP1_CARDSTATUS1 SDIO_RESP1_CARDSTATUS1_Msk /*!< Card Status */
+
+/****************** Bit definition for SDIO_RESP2 register ******************/
+#define SDIO_RESP2_CARDSTATUS2_Pos (0U)
+#define SDIO_RESP2_CARDSTATUS2_Msk (0xFFFFFFFFU << SDIO_RESP2_CARDSTATUS2_Pos) /*!< 0xFFFFFFFF */
+#define SDIO_RESP2_CARDSTATUS2 SDIO_RESP2_CARDSTATUS2_Msk /*!< Card Status */
+
+/****************** Bit definition for SDIO_RESP3 register ******************/
+#define SDIO_RESP3_CARDSTATUS3_Pos (0U)
+#define SDIO_RESP3_CARDSTATUS3_Msk (0xFFFFFFFFU << SDIO_RESP3_CARDSTATUS3_Pos) /*!< 0xFFFFFFFF */
+#define SDIO_RESP3_CARDSTATUS3 SDIO_RESP3_CARDSTATUS3_Msk /*!< Card Status */
+
+/****************** Bit definition for SDIO_RESP4 register ******************/
+#define SDIO_RESP4_CARDSTATUS4_Pos (0U)
+#define SDIO_RESP4_CARDSTATUS4_Msk (0xFFFFFFFFU << SDIO_RESP4_CARDSTATUS4_Pos) /*!< 0xFFFFFFFF */
+#define SDIO_RESP4_CARDSTATUS4 SDIO_RESP4_CARDSTATUS4_Msk /*!< Card Status */
+
+/****************** Bit definition for SDIO_DTIMER register *****************/
+#define SDIO_DTIMER_DATATIME_Pos (0U)
+#define SDIO_DTIMER_DATATIME_Msk (0xFFFFFFFFU << SDIO_DTIMER_DATATIME_Pos) /*!< 0xFFFFFFFF */
+#define SDIO_DTIMER_DATATIME SDIO_DTIMER_DATATIME_Msk /*!< Data timeout period. */
+
+/****************** Bit definition for SDIO_DLEN register *******************/
+#define SDIO_DLEN_DATALENGTH_Pos (0U)
+#define SDIO_DLEN_DATALENGTH_Msk (0x1FFFFFFU << SDIO_DLEN_DATALENGTH_Pos) /*!< 0x01FFFFFF */
+#define SDIO_DLEN_DATALENGTH SDIO_DLEN_DATALENGTH_Msk /*!< Data length value */
+
+/****************** Bit definition for SDIO_DCTRL register ******************/
+#define SDIO_DCTRL_DTEN_Pos (0U)
+#define SDIO_DCTRL_DTEN_Msk (0x1U << SDIO_DCTRL_DTEN_Pos) /*!< 0x00000001 */
+#define SDIO_DCTRL_DTEN SDIO_DCTRL_DTEN_Msk /*!< Data transfer enabled bit */
+#define SDIO_DCTRL_DTDIR_Pos (1U)
+#define SDIO_DCTRL_DTDIR_Msk (0x1U << SDIO_DCTRL_DTDIR_Pos) /*!< 0x00000002 */
+#define SDIO_DCTRL_DTDIR SDIO_DCTRL_DTDIR_Msk /*!< Data transfer direction selection */
+#define SDIO_DCTRL_DTMODE_Pos (2U)
+#define SDIO_DCTRL_DTMODE_Msk (0x1U << SDIO_DCTRL_DTMODE_Pos) /*!< 0x00000004 */
+#define SDIO_DCTRL_DTMODE SDIO_DCTRL_DTMODE_Msk /*!< Data transfer mode selection */
+#define SDIO_DCTRL_DMAEN_Pos (3U)
+#define SDIO_DCTRL_DMAEN_Msk (0x1U << SDIO_DCTRL_DMAEN_Pos) /*!< 0x00000008 */
+#define SDIO_DCTRL_DMAEN SDIO_DCTRL_DMAEN_Msk /*!< DMA enabled bit */
+
+#define SDIO_DCTRL_DBLOCKSIZE_Pos (4U)
+#define SDIO_DCTRL_DBLOCKSIZE_Msk (0xFU << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x000000F0 */
+#define SDIO_DCTRL_DBLOCKSIZE SDIO_DCTRL_DBLOCKSIZE_Msk /*!< DBLOCKSIZE[3:0] bits (Data block size) */
+#define SDIO_DCTRL_DBLOCKSIZE_0 (0x1U << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0010 */
+#define SDIO_DCTRL_DBLOCKSIZE_1 (0x2U << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0020 */
+#define SDIO_DCTRL_DBLOCKSIZE_2 (0x4U << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0040 */
+#define SDIO_DCTRL_DBLOCKSIZE_3 (0x8U << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0080 */
+
+#define SDIO_DCTRL_RWSTART_Pos (8U)
+#define SDIO_DCTRL_RWSTART_Msk (0x1U << SDIO_DCTRL_RWSTART_Pos) /*!< 0x00000100 */
+#define SDIO_DCTRL_RWSTART SDIO_DCTRL_RWSTART_Msk /*!< Read wait start */
+#define SDIO_DCTRL_RWSTOP_Pos (9U)
+#define SDIO_DCTRL_RWSTOP_Msk (0x1U << SDIO_DCTRL_RWSTOP_Pos) /*!< 0x00000200 */
+#define SDIO_DCTRL_RWSTOP SDIO_DCTRL_RWSTOP_Msk /*!< Read wait stop */
+#define SDIO_DCTRL_RWMOD_Pos (10U)
+#define SDIO_DCTRL_RWMOD_Msk (0x1U << SDIO_DCTRL_RWMOD_Pos) /*!< 0x00000400 */
+#define SDIO_DCTRL_RWMOD SDIO_DCTRL_RWMOD_Msk /*!< Read wait mode */
+#define SDIO_DCTRL_SDIOEN_Pos (11U)
+#define SDIO_DCTRL_SDIOEN_Msk (0x1U << SDIO_DCTRL_SDIOEN_Pos) /*!< 0x00000800 */
+#define SDIO_DCTRL_SDIOEN SDIO_DCTRL_SDIOEN_Msk /*!< SD I/O enable functions */
+
+/****************** Bit definition for SDIO_DCOUNT register *****************/
+#define SDIO_DCOUNT_DATACOUNT_Pos (0U)
+#define SDIO_DCOUNT_DATACOUNT_Msk (0x1FFFFFFU << SDIO_DCOUNT_DATACOUNT_Pos) /*!< 0x01FFFFFF */
+#define SDIO_DCOUNT_DATACOUNT SDIO_DCOUNT_DATACOUNT_Msk /*!< Data count value */
+
+/****************** Bit definition for SDIO_STA register ********************/
+#define SDIO_STA_CCRCFAIL_Pos (0U)
+#define SDIO_STA_CCRCFAIL_Msk (0x1U << SDIO_STA_CCRCFAIL_Pos) /*!< 0x00000001 */
+#define SDIO_STA_CCRCFAIL SDIO_STA_CCRCFAIL_Msk /*!< Command response received (CRC check failed) */
+#define SDIO_STA_DCRCFAIL_Pos (1U)
+#define SDIO_STA_DCRCFAIL_Msk (0x1U << SDIO_STA_DCRCFAIL_Pos) /*!< 0x00000002 */
+#define SDIO_STA_DCRCFAIL SDIO_STA_DCRCFAIL_Msk /*!< Data block sent/received (CRC check failed) */
+#define SDIO_STA_CTIMEOUT_Pos (2U)
+#define SDIO_STA_CTIMEOUT_Msk (0x1U << SDIO_STA_CTIMEOUT_Pos) /*!< 0x00000004 */
+#define SDIO_STA_CTIMEOUT SDIO_STA_CTIMEOUT_Msk /*!< Command response timeout */
+#define SDIO_STA_DTIMEOUT_Pos (3U)
+#define SDIO_STA_DTIMEOUT_Msk (0x1U << SDIO_STA_DTIMEOUT_Pos) /*!< 0x00000008 */
+#define SDIO_STA_DTIMEOUT SDIO_STA_DTIMEOUT_Msk /*!< Data timeout */
+#define SDIO_STA_TXUNDERR_Pos (4U)
+#define SDIO_STA_TXUNDERR_Msk (0x1U << SDIO_STA_TXUNDERR_Pos) /*!< 0x00000010 */
+#define SDIO_STA_TXUNDERR SDIO_STA_TXUNDERR_Msk /*!< Transmit FIFO underrun error */
+#define SDIO_STA_RXOVERR_Pos (5U)
+#define SDIO_STA_RXOVERR_Msk (0x1U << SDIO_STA_RXOVERR_Pos) /*!< 0x00000020 */
+#define SDIO_STA_RXOVERR SDIO_STA_RXOVERR_Msk /*!< Received FIFO overrun error */
+#define SDIO_STA_CMDREND_Pos (6U)
+#define SDIO_STA_CMDREND_Msk (0x1U << SDIO_STA_CMDREND_Pos) /*!< 0x00000040 */
+#define SDIO_STA_CMDREND SDIO_STA_CMDREND_Msk /*!< Command response received (CRC check passed) */
+#define SDIO_STA_CMDSENT_Pos (7U)
+#define SDIO_STA_CMDSENT_Msk (0x1U << SDIO_STA_CMDSENT_Pos) /*!< 0x00000080 */
+#define SDIO_STA_CMDSENT SDIO_STA_CMDSENT_Msk /*!< Command sent (no response required) */
+#define SDIO_STA_DATAEND_Pos (8U)
+#define SDIO_STA_DATAEND_Msk (0x1U << SDIO_STA_DATAEND_Pos) /*!< 0x00000100 */
+#define SDIO_STA_DATAEND SDIO_STA_DATAEND_Msk /*!< Data end (data counter, SDIDCOUNT, is zero) */
+#define SDIO_STA_STBITERR_Pos (9U)
+#define SDIO_STA_STBITERR_Msk (0x1U << SDIO_STA_STBITERR_Pos) /*!< 0x00000200 */
+#define SDIO_STA_STBITERR SDIO_STA_STBITERR_Msk /*!< Start bit not detected on all data signals in wide bus mode */
+#define SDIO_STA_DBCKEND_Pos (10U)
+#define SDIO_STA_DBCKEND_Msk (0x1U << SDIO_STA_DBCKEND_Pos) /*!< 0x00000400 */
+#define SDIO_STA_DBCKEND SDIO_STA_DBCKEND_Msk /*!< Data block sent/received (CRC check passed) */
+#define SDIO_STA_CMDACT_Pos (11U)
+#define SDIO_STA_CMDACT_Msk (0x1U << SDIO_STA_CMDACT_Pos) /*!< 0x00000800 */
+#define SDIO_STA_CMDACT SDIO_STA_CMDACT_Msk /*!< Command transfer in progress */
+#define SDIO_STA_TXACT_Pos (12U)
+#define SDIO_STA_TXACT_Msk (0x1U << SDIO_STA_TXACT_Pos) /*!< 0x00001000 */
+#define SDIO_STA_TXACT SDIO_STA_TXACT_Msk /*!< Data transmit in progress */
+#define SDIO_STA_RXACT_Pos (13U)
+#define SDIO_STA_RXACT_Msk (0x1U << SDIO_STA_RXACT_Pos) /*!< 0x00002000 */
+#define SDIO_STA_RXACT SDIO_STA_RXACT_Msk /*!< Data receive in progress */
+#define SDIO_STA_TXFIFOHE_Pos (14U)
+#define SDIO_STA_TXFIFOHE_Msk (0x1U << SDIO_STA_TXFIFOHE_Pos) /*!< 0x00004000 */
+#define SDIO_STA_TXFIFOHE SDIO_STA_TXFIFOHE_Msk /*!< Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
+#define SDIO_STA_RXFIFOHF_Pos (15U)
+#define SDIO_STA_RXFIFOHF_Msk (0x1U << SDIO_STA_RXFIFOHF_Pos) /*!< 0x00008000 */
+#define SDIO_STA_RXFIFOHF SDIO_STA_RXFIFOHF_Msk /*!< Receive FIFO Half Full: there are at least 8 words in the FIFO */
+#define SDIO_STA_TXFIFOF_Pos (16U)
+#define SDIO_STA_TXFIFOF_Msk (0x1U << SDIO_STA_TXFIFOF_Pos) /*!< 0x00010000 */
+#define SDIO_STA_TXFIFOF SDIO_STA_TXFIFOF_Msk /*!< Transmit FIFO full */
+#define SDIO_STA_RXFIFOF_Pos (17U)
+#define SDIO_STA_RXFIFOF_Msk (0x1U << SDIO_STA_RXFIFOF_Pos) /*!< 0x00020000 */
+#define SDIO_STA_RXFIFOF SDIO_STA_RXFIFOF_Msk /*!< Receive FIFO full */
+#define SDIO_STA_TXFIFOE_Pos (18U)
+#define SDIO_STA_TXFIFOE_Msk (0x1U << SDIO_STA_TXFIFOE_Pos) /*!< 0x00040000 */
+#define SDIO_STA_TXFIFOE SDIO_STA_TXFIFOE_Msk /*!< Transmit FIFO empty */
+#define SDIO_STA_RXFIFOE_Pos (19U)
+#define SDIO_STA_RXFIFOE_Msk (0x1U << SDIO_STA_RXFIFOE_Pos) /*!< 0x00080000 */
+#define SDIO_STA_RXFIFOE SDIO_STA_RXFIFOE_Msk /*!< Receive FIFO empty */
+#define SDIO_STA_TXDAVL_Pos (20U)
+#define SDIO_STA_TXDAVL_Msk (0x1U << SDIO_STA_TXDAVL_Pos) /*!< 0x00100000 */
+#define SDIO_STA_TXDAVL SDIO_STA_TXDAVL_Msk /*!< Data available in transmit FIFO */
+#define SDIO_STA_RXDAVL_Pos (21U)
+#define SDIO_STA_RXDAVL_Msk (0x1U << SDIO_STA_RXDAVL_Pos) /*!< 0x00200000 */
+#define SDIO_STA_RXDAVL SDIO_STA_RXDAVL_Msk /*!< Data available in receive FIFO */
+#define SDIO_STA_SDIOIT_Pos (22U)
+#define SDIO_STA_SDIOIT_Msk (0x1U << SDIO_STA_SDIOIT_Pos) /*!< 0x00400000 */
+#define SDIO_STA_SDIOIT SDIO_STA_SDIOIT_Msk /*!< SDIO interrupt received */
+#define SDIO_STA_CEATAEND_Pos (23U)
+#define SDIO_STA_CEATAEND_Msk (0x1U << SDIO_STA_CEATAEND_Pos) /*!< 0x00800000 */
+#define SDIO_STA_CEATAEND SDIO_STA_CEATAEND_Msk /*!< CE-ATA command completion signal received for CMD61 */
+
+/******************* Bit definition for SDIO_ICR register *******************/
+#define SDIO_ICR_CCRCFAILC_Pos (0U)
+#define SDIO_ICR_CCRCFAILC_Msk (0x1U << SDIO_ICR_CCRCFAILC_Pos) /*!< 0x00000001 */
+#define SDIO_ICR_CCRCFAILC SDIO_ICR_CCRCFAILC_Msk /*!< CCRCFAIL flag clear bit */
+#define SDIO_ICR_DCRCFAILC_Pos (1U)
+#define SDIO_ICR_DCRCFAILC_Msk (0x1U << SDIO_ICR_DCRCFAILC_Pos) /*!< 0x00000002 */
+#define SDIO_ICR_DCRCFAILC SDIO_ICR_DCRCFAILC_Msk /*!< DCRCFAIL flag clear bit */
+#define SDIO_ICR_CTIMEOUTC_Pos (2U)
+#define SDIO_ICR_CTIMEOUTC_Msk (0x1U << SDIO_ICR_CTIMEOUTC_Pos) /*!< 0x00000004 */
+#define SDIO_ICR_CTIMEOUTC SDIO_ICR_CTIMEOUTC_Msk /*!< CTIMEOUT flag clear bit */
+#define SDIO_ICR_DTIMEOUTC_Pos (3U)
+#define SDIO_ICR_DTIMEOUTC_Msk (0x1U << SDIO_ICR_DTIMEOUTC_Pos) /*!< 0x00000008 */
+#define SDIO_ICR_DTIMEOUTC SDIO_ICR_DTIMEOUTC_Msk /*!< DTIMEOUT flag clear bit */
+#define SDIO_ICR_TXUNDERRC_Pos (4U)
+#define SDIO_ICR_TXUNDERRC_Msk (0x1U << SDIO_ICR_TXUNDERRC_Pos) /*!< 0x00000010 */
+#define SDIO_ICR_TXUNDERRC SDIO_ICR_TXUNDERRC_Msk /*!< TXUNDERR flag clear bit */
+#define SDIO_ICR_RXOVERRC_Pos (5U)
+#define SDIO_ICR_RXOVERRC_Msk (0x1U << SDIO_ICR_RXOVERRC_Pos) /*!< 0x00000020 */
+#define SDIO_ICR_RXOVERRC SDIO_ICR_RXOVERRC_Msk /*!< RXOVERR flag clear bit */
+#define SDIO_ICR_CMDRENDC_Pos (6U)
+#define SDIO_ICR_CMDRENDC_Msk (0x1U << SDIO_ICR_CMDRENDC_Pos) /*!< 0x00000040 */
+#define SDIO_ICR_CMDRENDC SDIO_ICR_CMDRENDC_Msk /*!< CMDREND flag clear bit */
+#define SDIO_ICR_CMDSENTC_Pos (7U)
+#define SDIO_ICR_CMDSENTC_Msk (0x1U << SDIO_ICR_CMDSENTC_Pos) /*!< 0x00000080 */
+#define SDIO_ICR_CMDSENTC SDIO_ICR_CMDSENTC_Msk /*!< CMDSENT flag clear bit */
+#define SDIO_ICR_DATAENDC_Pos (8U)
+#define SDIO_ICR_DATAENDC_Msk (0x1U << SDIO_ICR_DATAENDC_Pos) /*!< 0x00000100 */
+#define SDIO_ICR_DATAENDC SDIO_ICR_DATAENDC_Msk /*!< DATAEND flag clear bit */
+#define SDIO_ICR_STBITERRC_Pos (9U)
+#define SDIO_ICR_STBITERRC_Msk (0x1U << SDIO_ICR_STBITERRC_Pos) /*!< 0x00000200 */
+#define SDIO_ICR_STBITERRC SDIO_ICR_STBITERRC_Msk /*!< STBITERR flag clear bit */
+#define SDIO_ICR_DBCKENDC_Pos (10U)
+#define SDIO_ICR_DBCKENDC_Msk (0x1U << SDIO_ICR_DBCKENDC_Pos) /*!< 0x00000400 */
+#define SDIO_ICR_DBCKENDC SDIO_ICR_DBCKENDC_Msk /*!< DBCKEND flag clear bit */
+#define SDIO_ICR_SDIOITC_Pos (22U)
+#define SDIO_ICR_SDIOITC_Msk (0x1U << SDIO_ICR_SDIOITC_Pos) /*!< 0x00400000 */
+#define SDIO_ICR_SDIOITC SDIO_ICR_SDIOITC_Msk /*!< SDIOIT flag clear bit */
+#define SDIO_ICR_CEATAENDC_Pos (23U)
+#define SDIO_ICR_CEATAENDC_Msk (0x1U << SDIO_ICR_CEATAENDC_Pos) /*!< 0x00800000 */
+#define SDIO_ICR_CEATAENDC SDIO_ICR_CEATAENDC_Msk /*!< CEATAEND flag clear bit */
+
+/****************** Bit definition for SDIO_MASK register *******************/
+#define SDIO_MASK_CCRCFAILIE_Pos (0U)
+#define SDIO_MASK_CCRCFAILIE_Msk (0x1U << SDIO_MASK_CCRCFAILIE_Pos) /*!< 0x00000001 */
+#define SDIO_MASK_CCRCFAILIE SDIO_MASK_CCRCFAILIE_Msk /*!< Command CRC Fail Interrupt Enable */
+#define SDIO_MASK_DCRCFAILIE_Pos (1U)
+#define SDIO_MASK_DCRCFAILIE_Msk (0x1U << SDIO_MASK_DCRCFAILIE_Pos) /*!< 0x00000002 */
+#define SDIO_MASK_DCRCFAILIE SDIO_MASK_DCRCFAILIE_Msk /*!< Data CRC Fail Interrupt Enable */
+#define SDIO_MASK_CTIMEOUTIE_Pos (2U)
+#define SDIO_MASK_CTIMEOUTIE_Msk (0x1U << SDIO_MASK_CTIMEOUTIE_Pos) /*!< 0x00000004 */
+#define SDIO_MASK_CTIMEOUTIE SDIO_MASK_CTIMEOUTIE_Msk /*!< Command TimeOut Interrupt Enable */
+#define SDIO_MASK_DTIMEOUTIE_Pos (3U)
+#define SDIO_MASK_DTIMEOUTIE_Msk (0x1U << SDIO_MASK_DTIMEOUTIE_Pos) /*!< 0x00000008 */
+#define SDIO_MASK_DTIMEOUTIE SDIO_MASK_DTIMEOUTIE_Msk /*!< Data TimeOut Interrupt Enable */
+#define SDIO_MASK_TXUNDERRIE_Pos (4U)
+#define SDIO_MASK_TXUNDERRIE_Msk (0x1U << SDIO_MASK_TXUNDERRIE_Pos) /*!< 0x00000010 */
+#define SDIO_MASK_TXUNDERRIE SDIO_MASK_TXUNDERRIE_Msk /*!< Tx FIFO UnderRun Error Interrupt Enable */
+#define SDIO_MASK_RXOVERRIE_Pos (5U)
+#define SDIO_MASK_RXOVERRIE_Msk (0x1U << SDIO_MASK_RXOVERRIE_Pos) /*!< 0x00000020 */
+#define SDIO_MASK_RXOVERRIE SDIO_MASK_RXOVERRIE_Msk /*!< Rx FIFO OverRun Error Interrupt Enable */
+#define SDIO_MASK_CMDRENDIE_Pos (6U)
+#define SDIO_MASK_CMDRENDIE_Msk (0x1U << SDIO_MASK_CMDRENDIE_Pos) /*!< 0x00000040 */
+#define SDIO_MASK_CMDRENDIE SDIO_MASK_CMDRENDIE_Msk /*!< Command Response Received Interrupt Enable */
+#define SDIO_MASK_CMDSENTIE_Pos (7U)
+#define SDIO_MASK_CMDSENTIE_Msk (0x1U << SDIO_MASK_CMDSENTIE_Pos) /*!< 0x00000080 */
+#define SDIO_MASK_CMDSENTIE SDIO_MASK_CMDSENTIE_Msk /*!< Command Sent Interrupt Enable */
+#define SDIO_MASK_DATAENDIE_Pos (8U)
+#define SDIO_MASK_DATAENDIE_Msk (0x1U << SDIO_MASK_DATAENDIE_Pos) /*!< 0x00000100 */
+#define SDIO_MASK_DATAENDIE SDIO_MASK_DATAENDIE_Msk /*!< Data End Interrupt Enable */
+#define SDIO_MASK_STBITERRIE_Pos (9U)
+#define SDIO_MASK_STBITERRIE_Msk (0x1U << SDIO_MASK_STBITERRIE_Pos) /*!< 0x00000200 */
+#define SDIO_MASK_STBITERRIE SDIO_MASK_STBITERRIE_Msk /*!< Start Bit Error Interrupt Enable */
+#define SDIO_MASK_DBCKENDIE_Pos (10U)
+#define SDIO_MASK_DBCKENDIE_Msk (0x1U << SDIO_MASK_DBCKENDIE_Pos) /*!< 0x00000400 */
+#define SDIO_MASK_DBCKENDIE SDIO_MASK_DBCKENDIE_Msk /*!< Data Block End Interrupt Enable */
+#define SDIO_MASK_CMDACTIE_Pos (11U)
+#define SDIO_MASK_CMDACTIE_Msk (0x1U << SDIO_MASK_CMDACTIE_Pos) /*!< 0x00000800 */
+#define SDIO_MASK_CMDACTIE SDIO_MASK_CMDACTIE_Msk /*!< Command Acting Interrupt Enable */
+#define SDIO_MASK_TXACTIE_Pos (12U)
+#define SDIO_MASK_TXACTIE_Msk (0x1U << SDIO_MASK_TXACTIE_Pos) /*!< 0x00001000 */
+#define SDIO_MASK_TXACTIE SDIO_MASK_TXACTIE_Msk /*!< Data Transmit Acting Interrupt Enable */
+#define SDIO_MASK_RXACTIE_Pos (13U)
+#define SDIO_MASK_RXACTIE_Msk (0x1U << SDIO_MASK_RXACTIE_Pos) /*!< 0x00002000 */
+#define SDIO_MASK_RXACTIE SDIO_MASK_RXACTIE_Msk /*!< Data receive acting interrupt enabled */
+#define SDIO_MASK_TXFIFOHEIE_Pos (14U)
+#define SDIO_MASK_TXFIFOHEIE_Msk (0x1U << SDIO_MASK_TXFIFOHEIE_Pos) /*!< 0x00004000 */
+#define SDIO_MASK_TXFIFOHEIE SDIO_MASK_TXFIFOHEIE_Msk /*!< Tx FIFO Half Empty interrupt Enable */
+#define SDIO_MASK_RXFIFOHFIE_Pos (15U)
+#define SDIO_MASK_RXFIFOHFIE_Msk (0x1U << SDIO_MASK_RXFIFOHFIE_Pos) /*!< 0x00008000 */
+#define SDIO_MASK_RXFIFOHFIE SDIO_MASK_RXFIFOHFIE_Msk /*!< Rx FIFO Half Full interrupt Enable */
+#define SDIO_MASK_TXFIFOFIE_Pos (16U)
+#define SDIO_MASK_TXFIFOFIE_Msk (0x1U << SDIO_MASK_TXFIFOFIE_Pos) /*!< 0x00010000 */
+#define SDIO_MASK_TXFIFOFIE SDIO_MASK_TXFIFOFIE_Msk /*!< Tx FIFO Full interrupt Enable */
+#define SDIO_MASK_RXFIFOFIE_Pos (17U)
+#define SDIO_MASK_RXFIFOFIE_Msk (0x1U << SDIO_MASK_RXFIFOFIE_Pos) /*!< 0x00020000 */
+#define SDIO_MASK_RXFIFOFIE SDIO_MASK_RXFIFOFIE_Msk /*!< Rx FIFO Full interrupt Enable */
+#define SDIO_MASK_TXFIFOEIE_Pos (18U)
+#define SDIO_MASK_TXFIFOEIE_Msk (0x1U << SDIO_MASK_TXFIFOEIE_Pos) /*!< 0x00040000 */
+#define SDIO_MASK_TXFIFOEIE SDIO_MASK_TXFIFOEIE_Msk /*!< Tx FIFO Empty interrupt Enable */
+#define SDIO_MASK_RXFIFOEIE_Pos (19U)
+#define SDIO_MASK_RXFIFOEIE_Msk (0x1U << SDIO_MASK_RXFIFOEIE_Pos) /*!< 0x00080000 */
+#define SDIO_MASK_RXFIFOEIE SDIO_MASK_RXFIFOEIE_Msk /*!< Rx FIFO Empty interrupt Enable */
+#define SDIO_MASK_TXDAVLIE_Pos (20U)
+#define SDIO_MASK_TXDAVLIE_Msk (0x1U << SDIO_MASK_TXDAVLIE_Pos) /*!< 0x00100000 */
+#define SDIO_MASK_TXDAVLIE SDIO_MASK_TXDAVLIE_Msk /*!< Data available in Tx FIFO interrupt Enable */
+#define SDIO_MASK_RXDAVLIE_Pos (21U)
+#define SDIO_MASK_RXDAVLIE_Msk (0x1U << SDIO_MASK_RXDAVLIE_Pos) /*!< 0x00200000 */
+#define SDIO_MASK_RXDAVLIE SDIO_MASK_RXDAVLIE_Msk /*!< Data available in Rx FIFO interrupt Enable */
+#define SDIO_MASK_SDIOITIE_Pos (22U)
+#define SDIO_MASK_SDIOITIE_Msk (0x1U << SDIO_MASK_SDIOITIE_Pos) /*!< 0x00400000 */
+#define SDIO_MASK_SDIOITIE SDIO_MASK_SDIOITIE_Msk /*!< SDIO Mode Interrupt Received interrupt Enable */
+#define SDIO_MASK_CEATAENDIE_Pos (23U)
+#define SDIO_MASK_CEATAENDIE_Msk (0x1U << SDIO_MASK_CEATAENDIE_Pos) /*!< 0x00800000 */
+#define SDIO_MASK_CEATAENDIE SDIO_MASK_CEATAENDIE_Msk /*!< CE-ATA command completion signal received Interrupt Enable */
+
+/***************** Bit definition for SDIO_FIFOCNT register *****************/
+#define SDIO_FIFOCNT_FIFOCOUNT_Pos (0U)
+#define SDIO_FIFOCNT_FIFOCOUNT_Msk (0xFFFFFFU << SDIO_FIFOCNT_FIFOCOUNT_Pos) /*!< 0x00FFFFFF */
+#define SDIO_FIFOCNT_FIFOCOUNT SDIO_FIFOCNT_FIFOCOUNT_Msk /*!< Remaining number of words to be written to or read from the FIFO */
+
+/****************** Bit definition for SDIO_FIFO register *******************/
+#define SDIO_FIFO_FIFODATA_Pos (0U)
+#define SDIO_FIFO_FIFODATA_Msk (0xFFFFFFFFU << SDIO_FIFO_FIFODATA_Pos) /*!< 0xFFFFFFFF */
+#define SDIO_FIFO_FIFODATA SDIO_FIFO_FIFODATA_Msk /*!< Receive and transmit FIFO data */
+
+
+
+/******************************************************************************/
+/* */
+/* Serial Peripheral Interface */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for SPI_CR1 register ********************/
+#define SPI_CR1_CPHA_Pos (0U)
+#define SPI_CR1_CPHA_Msk (0x1U << SPI_CR1_CPHA_Pos) /*!< 0x00000001 */
+#define SPI_CR1_CPHA SPI_CR1_CPHA_Msk /*!< Clock Phase */
+#define SPI_CR1_CPOL_Pos (1U)
+#define SPI_CR1_CPOL_Msk (0x1U << SPI_CR1_CPOL_Pos) /*!< 0x00000002 */
+#define SPI_CR1_CPOL SPI_CR1_CPOL_Msk /*!< Clock Polarity */
+#define SPI_CR1_MSTR_Pos (2U)
+#define SPI_CR1_MSTR_Msk (0x1U << SPI_CR1_MSTR_Pos) /*!< 0x00000004 */
+#define SPI_CR1_MSTR SPI_CR1_MSTR_Msk /*!< Master Selection */
+
+#define SPI_CR1_BR_Pos (3U)
+#define SPI_CR1_BR_Msk (0x7U << SPI_CR1_BR_Pos) /*!< 0x00000038 */
+#define SPI_CR1_BR SPI_CR1_BR_Msk /*!< BR[2:0] bits (Baud Rate Control) */
+#define SPI_CR1_BR_0 (0x1U << SPI_CR1_BR_Pos) /*!< 0x00000008 */
+#define SPI_CR1_BR_1 (0x2U << SPI_CR1_BR_Pos) /*!< 0x00000010 */
+#define SPI_CR1_BR_2 (0x4U << SPI_CR1_BR_Pos) /*!< 0x00000020 */
+
+#define SPI_CR1_SPE_Pos (6U)
+#define SPI_CR1_SPE_Msk (0x1U << SPI_CR1_SPE_Pos) /*!< 0x00000040 */
+#define SPI_CR1_SPE SPI_CR1_SPE_Msk /*!< SPI Enable */
+#define SPI_CR1_LSBFIRST_Pos (7U)
+#define SPI_CR1_LSBFIRST_Msk (0x1U << SPI_CR1_LSBFIRST_Pos) /*!< 0x00000080 */
+#define SPI_CR1_LSBFIRST SPI_CR1_LSBFIRST_Msk /*!< Frame Format */
+#define SPI_CR1_SSI_Pos (8U)
+#define SPI_CR1_SSI_Msk (0x1U << SPI_CR1_SSI_Pos) /*!< 0x00000100 */
+#define SPI_CR1_SSI SPI_CR1_SSI_Msk /*!< Internal slave select */
+#define SPI_CR1_SSM_Pos (9U)
+#define SPI_CR1_SSM_Msk (0x1U << SPI_CR1_SSM_Pos) /*!< 0x00000200 */
+#define SPI_CR1_SSM SPI_CR1_SSM_Msk /*!< Software slave management */
+#define SPI_CR1_RXONLY_Pos (10U)
+#define SPI_CR1_RXONLY_Msk (0x1U << SPI_CR1_RXONLY_Pos) /*!< 0x00000400 */
+#define SPI_CR1_RXONLY SPI_CR1_RXONLY_Msk /*!< Receive only */
+#define SPI_CR1_DFF_Pos (11U)
+#define SPI_CR1_DFF_Msk (0x1U << SPI_CR1_DFF_Pos) /*!< 0x00000800 */
+#define SPI_CR1_DFF SPI_CR1_DFF_Msk /*!< Data Frame Format */
+#define SPI_CR1_CRCNEXT_Pos (12U)
+#define SPI_CR1_CRCNEXT_Msk (0x1U << SPI_CR1_CRCNEXT_Pos) /*!< 0x00001000 */
+#define SPI_CR1_CRCNEXT SPI_CR1_CRCNEXT_Msk /*!< Transmit CRC next */
+#define SPI_CR1_CRCEN_Pos (13U)
+#define SPI_CR1_CRCEN_Msk (0x1U << SPI_CR1_CRCEN_Pos) /*!< 0x00002000 */
+#define SPI_CR1_CRCEN SPI_CR1_CRCEN_Msk /*!< Hardware CRC calculation enable */
+#define SPI_CR1_BIDIOE_Pos (14U)
+#define SPI_CR1_BIDIOE_Msk (0x1U << SPI_CR1_BIDIOE_Pos) /*!< 0x00004000 */
+#define SPI_CR1_BIDIOE SPI_CR1_BIDIOE_Msk /*!< Output enable in bidirectional mode */
+#define SPI_CR1_BIDIMODE_Pos (15U)
+#define SPI_CR1_BIDIMODE_Msk (0x1U << SPI_CR1_BIDIMODE_Pos) /*!< 0x00008000 */
+#define SPI_CR1_BIDIMODE SPI_CR1_BIDIMODE_Msk /*!< Bidirectional data mode enable */
+
+/******************* Bit definition for SPI_CR2 register ********************/
+#define SPI_CR2_RXDMAEN_Pos (0U)
+#define SPI_CR2_RXDMAEN_Msk (0x1U << SPI_CR2_RXDMAEN_Pos) /*!< 0x00000001 */
+#define SPI_CR2_RXDMAEN SPI_CR2_RXDMAEN_Msk /*!< Rx Buffer DMA Enable */
+#define SPI_CR2_TXDMAEN_Pos (1U)
+#define SPI_CR2_TXDMAEN_Msk (0x1U << SPI_CR2_TXDMAEN_Pos) /*!< 0x00000002 */
+#define SPI_CR2_TXDMAEN SPI_CR2_TXDMAEN_Msk /*!< Tx Buffer DMA Enable */
+#define SPI_CR2_SSOE_Pos (2U)
+#define SPI_CR2_SSOE_Msk (0x1U << SPI_CR2_SSOE_Pos) /*!< 0x00000004 */
+#define SPI_CR2_SSOE SPI_CR2_SSOE_Msk /*!< SS Output Enable */
+#define SPI_CR2_ERRIE_Pos (5U)
+#define SPI_CR2_ERRIE_Msk (0x1U << SPI_CR2_ERRIE_Pos) /*!< 0x00000020 */
+#define SPI_CR2_ERRIE SPI_CR2_ERRIE_Msk /*!< Error Interrupt Enable */
+#define SPI_CR2_RXNEIE_Pos (6U)
+#define SPI_CR2_RXNEIE_Msk (0x1U << SPI_CR2_RXNEIE_Pos) /*!< 0x00000040 */
+#define SPI_CR2_RXNEIE SPI_CR2_RXNEIE_Msk /*!< RX buffer Not Empty Interrupt Enable */
+#define SPI_CR2_TXEIE_Pos (7U)
+#define SPI_CR2_TXEIE_Msk (0x1U << SPI_CR2_TXEIE_Pos) /*!< 0x00000080 */
+#define SPI_CR2_TXEIE SPI_CR2_TXEIE_Msk /*!< Tx buffer Empty Interrupt Enable */
+
+/******************** Bit definition for SPI_SR register ********************/
+#define SPI_SR_RXNE_Pos (0U)
+#define SPI_SR_RXNE_Msk (0x1U << SPI_SR_RXNE_Pos) /*!< 0x00000001 */
+#define SPI_SR_RXNE SPI_SR_RXNE_Msk /*!< Receive buffer Not Empty */
+#define SPI_SR_TXE_Pos (1U)
+#define SPI_SR_TXE_Msk (0x1U << SPI_SR_TXE_Pos) /*!< 0x00000002 */
+#define SPI_SR_TXE SPI_SR_TXE_Msk /*!< Transmit buffer Empty */
+#define SPI_SR_CHSIDE_Pos (2U)
+#define SPI_SR_CHSIDE_Msk (0x1U << SPI_SR_CHSIDE_Pos) /*!< 0x00000004 */
+#define SPI_SR_CHSIDE SPI_SR_CHSIDE_Msk /*!< Channel side */
+#define SPI_SR_UDR_Pos (3U)
+#define SPI_SR_UDR_Msk (0x1U << SPI_SR_UDR_Pos) /*!< 0x00000008 */
+#define SPI_SR_UDR SPI_SR_UDR_Msk /*!< Underrun flag */
+#define SPI_SR_CRCERR_Pos (4U)
+#define SPI_SR_CRCERR_Msk (0x1U << SPI_SR_CRCERR_Pos) /*!< 0x00000010 */
+#define SPI_SR_CRCERR SPI_SR_CRCERR_Msk /*!< CRC Error flag */
+#define SPI_SR_MODF_Pos (5U)
+#define SPI_SR_MODF_Msk (0x1U << SPI_SR_MODF_Pos) /*!< 0x00000020 */
+#define SPI_SR_MODF SPI_SR_MODF_Msk /*!< Mode fault */
+#define SPI_SR_OVR_Pos (6U)
+#define SPI_SR_OVR_Msk (0x1U << SPI_SR_OVR_Pos) /*!< 0x00000040 */
+#define SPI_SR_OVR SPI_SR_OVR_Msk /*!< Overrun flag */
+#define SPI_SR_BSY_Pos (7U)
+#define SPI_SR_BSY_Msk (0x1U << SPI_SR_BSY_Pos) /*!< 0x00000080 */
+#define SPI_SR_BSY SPI_SR_BSY_Msk /*!< Busy flag */
+
+/******************** Bit definition for SPI_DR register ********************/
+#define SPI_DR_DR_Pos (0U)
+#define SPI_DR_DR_Msk (0xFFFFU << SPI_DR_DR_Pos) /*!< 0x0000FFFF */
+#define SPI_DR_DR SPI_DR_DR_Msk /*!< Data Register */
+
+/******************* Bit definition for SPI_CRCPR register ******************/
+#define SPI_CRCPR_CRCPOLY_Pos (0U)
+#define SPI_CRCPR_CRCPOLY_Msk (0xFFFFU << SPI_CRCPR_CRCPOLY_Pos) /*!< 0x0000FFFF */
+#define SPI_CRCPR_CRCPOLY SPI_CRCPR_CRCPOLY_Msk /*!< CRC polynomial register */
+
+/****************** Bit definition for SPI_RXCRCR register ******************/
+#define SPI_RXCRCR_RXCRC_Pos (0U)
+#define SPI_RXCRCR_RXCRC_Msk (0xFFFFU << SPI_RXCRCR_RXCRC_Pos) /*!< 0x0000FFFF */
+#define SPI_RXCRCR_RXCRC SPI_RXCRCR_RXCRC_Msk /*!< Rx CRC Register */
+
+/****************** Bit definition for SPI_TXCRCR register ******************/
+#define SPI_TXCRCR_TXCRC_Pos (0U)
+#define SPI_TXCRCR_TXCRC_Msk (0xFFFFU << SPI_TXCRCR_TXCRC_Pos) /*!< 0x0000FFFF */
+#define SPI_TXCRCR_TXCRC SPI_TXCRCR_TXCRC_Msk /*!< Tx CRC Register */
+
+/****************** Bit definition for SPI_I2SCFGR register *****************/
+#define SPI_I2SCFGR_I2SMOD_Pos (11U)
+#define SPI_I2SCFGR_I2SMOD_Msk (0x1U << SPI_I2SCFGR_I2SMOD_Pos) /*!< 0x00000800 */
+#define SPI_I2SCFGR_I2SMOD SPI_I2SCFGR_I2SMOD_Msk /*!< I2S mode selection */
+
+
+/******************************************************************************/
+/* */
+/* Inter-integrated Circuit Interface */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for I2C_CR1 register ********************/
+#define I2C_CR1_PE_Pos (0U)
+#define I2C_CR1_PE_Msk (0x1U << I2C_CR1_PE_Pos) /*!< 0x00000001 */
+#define I2C_CR1_PE I2C_CR1_PE_Msk /*!< Peripheral Enable */
+#define I2C_CR1_SMBUS_Pos (1U)
+#define I2C_CR1_SMBUS_Msk (0x1U << I2C_CR1_SMBUS_Pos) /*!< 0x00000002 */
+#define I2C_CR1_SMBUS I2C_CR1_SMBUS_Msk /*!< SMBus Mode */
+#define I2C_CR1_SMBTYPE_Pos (3U)
+#define I2C_CR1_SMBTYPE_Msk (0x1U << I2C_CR1_SMBTYPE_Pos) /*!< 0x00000008 */
+#define I2C_CR1_SMBTYPE I2C_CR1_SMBTYPE_Msk /*!< SMBus Type */
+#define I2C_CR1_ENARP_Pos (4U)
+#define I2C_CR1_ENARP_Msk (0x1U << I2C_CR1_ENARP_Pos) /*!< 0x00000010 */
+#define I2C_CR1_ENARP I2C_CR1_ENARP_Msk /*!< ARP Enable */
+#define I2C_CR1_ENPEC_Pos (5U)
+#define I2C_CR1_ENPEC_Msk (0x1U << I2C_CR1_ENPEC_Pos) /*!< 0x00000020 */
+#define I2C_CR1_ENPEC I2C_CR1_ENPEC_Msk /*!< PEC Enable */
+#define I2C_CR1_ENGC_Pos (6U)
+#define I2C_CR1_ENGC_Msk (0x1U << I2C_CR1_ENGC_Pos) /*!< 0x00000040 */
+#define I2C_CR1_ENGC I2C_CR1_ENGC_Msk /*!< General Call Enable */
+#define I2C_CR1_NOSTRETCH_Pos (7U)
+#define I2C_CR1_NOSTRETCH_Msk (0x1U << I2C_CR1_NOSTRETCH_Pos) /*!< 0x00000080 */
+#define I2C_CR1_NOSTRETCH I2C_CR1_NOSTRETCH_Msk /*!< Clock Stretching Disable (Slave mode) */
+#define I2C_CR1_START_Pos (8U)
+#define I2C_CR1_START_Msk (0x1U << I2C_CR1_START_Pos) /*!< 0x00000100 */
+#define I2C_CR1_START I2C_CR1_START_Msk /*!< Start Generation */
+#define I2C_CR1_STOP_Pos (9U)
+#define I2C_CR1_STOP_Msk (0x1U << I2C_CR1_STOP_Pos) /*!< 0x00000200 */
+#define I2C_CR1_STOP I2C_CR1_STOP_Msk /*!< Stop Generation */
+#define I2C_CR1_ACK_Pos (10U)
+#define I2C_CR1_ACK_Msk (0x1U << I2C_CR1_ACK_Pos) /*!< 0x00000400 */
+#define I2C_CR1_ACK I2C_CR1_ACK_Msk /*!< Acknowledge Enable */
+#define I2C_CR1_POS_Pos (11U)
+#define I2C_CR1_POS_Msk (0x1U << I2C_CR1_POS_Pos) /*!< 0x00000800 */
+#define I2C_CR1_POS I2C_CR1_POS_Msk /*!< Acknowledge/PEC Position (for data reception) */
+#define I2C_CR1_PEC_Pos (12U)
+#define I2C_CR1_PEC_Msk (0x1U << I2C_CR1_PEC_Pos) /*!< 0x00001000 */
+#define I2C_CR1_PEC I2C_CR1_PEC_Msk /*!< Packet Error Checking */
+#define I2C_CR1_ALERT_Pos (13U)
+#define I2C_CR1_ALERT_Msk (0x1U << I2C_CR1_ALERT_Pos) /*!< 0x00002000 */
+#define I2C_CR1_ALERT I2C_CR1_ALERT_Msk /*!< SMBus Alert */
+#define I2C_CR1_SWRST_Pos (15U)
+#define I2C_CR1_SWRST_Msk (0x1U << I2C_CR1_SWRST_Pos) /*!< 0x00008000 */
+#define I2C_CR1_SWRST I2C_CR1_SWRST_Msk /*!< Software Reset */
+
+/******************* Bit definition for I2C_CR2 register ********************/
+#define I2C_CR2_FREQ_Pos (0U)
+#define I2C_CR2_FREQ_Msk (0x3FU << I2C_CR2_FREQ_Pos) /*!< 0x0000003F */
+#define I2C_CR2_FREQ I2C_CR2_FREQ_Msk /*!< FREQ[5:0] bits (Peripheral Clock Frequency) */
+#define I2C_CR2_FREQ_0 (0x01U << I2C_CR2_FREQ_Pos) /*!< 0x00000001 */
+#define I2C_CR2_FREQ_1 (0x02U << I2C_CR2_FREQ_Pos) /*!< 0x00000002 */
+#define I2C_CR2_FREQ_2 (0x04U << I2C_CR2_FREQ_Pos) /*!< 0x00000004 */
+#define I2C_CR2_FREQ_3 (0x08U << I2C_CR2_FREQ_Pos) /*!< 0x00000008 */
+#define I2C_CR2_FREQ_4 (0x10U << I2C_CR2_FREQ_Pos) /*!< 0x00000010 */
+#define I2C_CR2_FREQ_5 (0x20U << I2C_CR2_FREQ_Pos) /*!< 0x00000020 */
+
+#define I2C_CR2_ITERREN_Pos (8U)
+#define I2C_CR2_ITERREN_Msk (0x1U << I2C_CR2_ITERREN_Pos) /*!< 0x00000100 */
+#define I2C_CR2_ITERREN I2C_CR2_ITERREN_Msk /*!< Error Interrupt Enable */
+#define I2C_CR2_ITEVTEN_Pos (9U)
+#define I2C_CR2_ITEVTEN_Msk (0x1U << I2C_CR2_ITEVTEN_Pos) /*!< 0x00000200 */
+#define I2C_CR2_ITEVTEN I2C_CR2_ITEVTEN_Msk /*!< Event Interrupt Enable */
+#define I2C_CR2_ITBUFEN_Pos (10U)
+#define I2C_CR2_ITBUFEN_Msk (0x1U << I2C_CR2_ITBUFEN_Pos) /*!< 0x00000400 */
+#define I2C_CR2_ITBUFEN I2C_CR2_ITBUFEN_Msk /*!< Buffer Interrupt Enable */
+#define I2C_CR2_DMAEN_Pos (11U)
+#define I2C_CR2_DMAEN_Msk (0x1U << I2C_CR2_DMAEN_Pos) /*!< 0x00000800 */
+#define I2C_CR2_DMAEN I2C_CR2_DMAEN_Msk /*!< DMA Requests Enable */
+#define I2C_CR2_LAST_Pos (12U)
+#define I2C_CR2_LAST_Msk (0x1U << I2C_CR2_LAST_Pos) /*!< 0x00001000 */
+#define I2C_CR2_LAST I2C_CR2_LAST_Msk /*!< DMA Last Transfer */
+
+/******************* Bit definition for I2C_OAR1 register *******************/
+#define I2C_OAR1_ADD1_7 ((uint32_t)0x000000FE) /*!< Interface Address */
+#define I2C_OAR1_ADD8_9 ((uint32_t)0x00000300) /*!< Interface Address */
+
+#define I2C_OAR1_ADD0_Pos (0U)
+#define I2C_OAR1_ADD0_Msk (0x1U << I2C_OAR1_ADD0_Pos) /*!< 0x00000001 */
+#define I2C_OAR1_ADD0 I2C_OAR1_ADD0_Msk /*!< Bit 0 */
+#define I2C_OAR1_ADD1_Pos (1U)
+#define I2C_OAR1_ADD1_Msk (0x1U << I2C_OAR1_ADD1_Pos) /*!< 0x00000002 */
+#define I2C_OAR1_ADD1 I2C_OAR1_ADD1_Msk /*!< Bit 1 */
+#define I2C_OAR1_ADD2_Pos (2U)
+#define I2C_OAR1_ADD2_Msk (0x1U << I2C_OAR1_ADD2_Pos) /*!< 0x00000004 */
+#define I2C_OAR1_ADD2 I2C_OAR1_ADD2_Msk /*!< Bit 2 */
+#define I2C_OAR1_ADD3_Pos (3U)
+#define I2C_OAR1_ADD3_Msk (0x1U << I2C_OAR1_ADD3_Pos) /*!< 0x00000008 */
+#define I2C_OAR1_ADD3 I2C_OAR1_ADD3_Msk /*!< Bit 3 */
+#define I2C_OAR1_ADD4_Pos (4U)
+#define I2C_OAR1_ADD4_Msk (0x1U << I2C_OAR1_ADD4_Pos) /*!< 0x00000010 */
+#define I2C_OAR1_ADD4 I2C_OAR1_ADD4_Msk /*!< Bit 4 */
+#define I2C_OAR1_ADD5_Pos (5U)
+#define I2C_OAR1_ADD5_Msk (0x1U << I2C_OAR1_ADD5_Pos) /*!< 0x00000020 */
+#define I2C_OAR1_ADD5 I2C_OAR1_ADD5_Msk /*!< Bit 5 */
+#define I2C_OAR1_ADD6_Pos (6U)
+#define I2C_OAR1_ADD6_Msk (0x1U << I2C_OAR1_ADD6_Pos) /*!< 0x00000040 */
+#define I2C_OAR1_ADD6 I2C_OAR1_ADD6_Msk /*!< Bit 6 */
+#define I2C_OAR1_ADD7_Pos (7U)
+#define I2C_OAR1_ADD7_Msk (0x1U << I2C_OAR1_ADD7_Pos) /*!< 0x00000080 */
+#define I2C_OAR1_ADD7 I2C_OAR1_ADD7_Msk /*!< Bit 7 */
+#define I2C_OAR1_ADD8_Pos (8U)
+#define I2C_OAR1_ADD8_Msk (0x1U << I2C_OAR1_ADD8_Pos) /*!< 0x00000100 */
+#define I2C_OAR1_ADD8 I2C_OAR1_ADD8_Msk /*!< Bit 8 */
+#define I2C_OAR1_ADD9_Pos (9U)
+#define I2C_OAR1_ADD9_Msk (0x1U << I2C_OAR1_ADD9_Pos) /*!< 0x00000200 */
+#define I2C_OAR1_ADD9 I2C_OAR1_ADD9_Msk /*!< Bit 9 */
+
+#define I2C_OAR1_ADDMODE_Pos (15U)
+#define I2C_OAR1_ADDMODE_Msk (0x1U << I2C_OAR1_ADDMODE_Pos) /*!< 0x00008000 */
+#define I2C_OAR1_ADDMODE I2C_OAR1_ADDMODE_Msk /*!< Addressing Mode (Slave mode) */
+
+/******************* Bit definition for I2C_OAR2 register *******************/
+#define I2C_OAR2_ENDUAL_Pos (0U)
+#define I2C_OAR2_ENDUAL_Msk (0x1U << I2C_OAR2_ENDUAL_Pos) /*!< 0x00000001 */
+#define I2C_OAR2_ENDUAL I2C_OAR2_ENDUAL_Msk /*!< Dual addressing mode enable */
+#define I2C_OAR2_ADD2_Pos (1U)
+#define I2C_OAR2_ADD2_Msk (0x7FU << I2C_OAR2_ADD2_Pos) /*!< 0x000000FE */
+#define I2C_OAR2_ADD2 I2C_OAR2_ADD2_Msk /*!< Interface address */
+
+/******************* Bit definition for I2C_SR1 register ********************/
+#define I2C_SR1_SB_Pos (0U)
+#define I2C_SR1_SB_Msk (0x1U << I2C_SR1_SB_Pos) /*!< 0x00000001 */
+#define I2C_SR1_SB I2C_SR1_SB_Msk /*!< Start Bit (Master mode) */
+#define I2C_SR1_ADDR_Pos (1U)
+#define I2C_SR1_ADDR_Msk (0x1U << I2C_SR1_ADDR_Pos) /*!< 0x00000002 */
+#define I2C_SR1_ADDR I2C_SR1_ADDR_Msk /*!< Address sent (master mode)/matched (slave mode) */
+#define I2C_SR1_BTF_Pos (2U)
+#define I2C_SR1_BTF_Msk (0x1U << I2C_SR1_BTF_Pos) /*!< 0x00000004 */
+#define I2C_SR1_BTF I2C_SR1_BTF_Msk /*!< Byte Transfer Finished */
+#define I2C_SR1_ADD10_Pos (3U)
+#define I2C_SR1_ADD10_Msk (0x1U << I2C_SR1_ADD10_Pos) /*!< 0x00000008 */
+#define I2C_SR1_ADD10 I2C_SR1_ADD10_Msk /*!< 10-bit header sent (Master mode) */
+#define I2C_SR1_STOPF_Pos (4U)
+#define I2C_SR1_STOPF_Msk (0x1U << I2C_SR1_STOPF_Pos) /*!< 0x00000010 */
+#define I2C_SR1_STOPF I2C_SR1_STOPF_Msk /*!< Stop detection (Slave mode) */
+#define I2C_SR1_RXNE_Pos (6U)
+#define I2C_SR1_RXNE_Msk (0x1U << I2C_SR1_RXNE_Pos) /*!< 0x00000040 */
+#define I2C_SR1_RXNE I2C_SR1_RXNE_Msk /*!< Data Register not Empty (receivers) */
+#define I2C_SR1_TXE_Pos (7U)
+#define I2C_SR1_TXE_Msk (0x1U << I2C_SR1_TXE_Pos) /*!< 0x00000080 */
+#define I2C_SR1_TXE I2C_SR1_TXE_Msk /*!< Data Register Empty (transmitters) */
+#define I2C_SR1_BERR_Pos (8U)
+#define I2C_SR1_BERR_Msk (0x1U << I2C_SR1_BERR_Pos) /*!< 0x00000100 */
+#define I2C_SR1_BERR I2C_SR1_BERR_Msk /*!< Bus Error */
+#define I2C_SR1_ARLO_Pos (9U)
+#define I2C_SR1_ARLO_Msk (0x1U << I2C_SR1_ARLO_Pos) /*!< 0x00000200 */
+#define I2C_SR1_ARLO I2C_SR1_ARLO_Msk /*!< Arbitration Lost (master mode) */
+#define I2C_SR1_AF_Pos (10U)
+#define I2C_SR1_AF_Msk (0x1U << I2C_SR1_AF_Pos) /*!< 0x00000400 */
+#define I2C_SR1_AF I2C_SR1_AF_Msk /*!< Acknowledge Failure */
+#define I2C_SR1_OVR_Pos (11U)
+#define I2C_SR1_OVR_Msk (0x1U << I2C_SR1_OVR_Pos) /*!< 0x00000800 */
+#define I2C_SR1_OVR I2C_SR1_OVR_Msk /*!< Overrun/Underrun */
+#define I2C_SR1_PECERR_Pos (12U)
+#define I2C_SR1_PECERR_Msk (0x1U << I2C_SR1_PECERR_Pos) /*!< 0x00001000 */
+#define I2C_SR1_PECERR I2C_SR1_PECERR_Msk /*!< PEC Error in reception */
+#define I2C_SR1_TIMEOUT_Pos (14U)
+#define I2C_SR1_TIMEOUT_Msk (0x1U << I2C_SR1_TIMEOUT_Pos) /*!< 0x00004000 */
+#define I2C_SR1_TIMEOUT I2C_SR1_TIMEOUT_Msk /*!< Timeout or Tlow Error */
+#define I2C_SR1_SMBALERT_Pos (15U)
+#define I2C_SR1_SMBALERT_Msk (0x1U << I2C_SR1_SMBALERT_Pos) /*!< 0x00008000 */
+#define I2C_SR1_SMBALERT I2C_SR1_SMBALERT_Msk /*!< SMBus Alert */
+
+/******************* Bit definition for I2C_SR2 register ********************/
+#define I2C_SR2_MSL_Pos (0U)
+#define I2C_SR2_MSL_Msk (0x1U << I2C_SR2_MSL_Pos) /*!< 0x00000001 */
+#define I2C_SR2_MSL I2C_SR2_MSL_Msk /*!< Master/Slave */
+#define I2C_SR2_BUSY_Pos (1U)
+#define I2C_SR2_BUSY_Msk (0x1U << I2C_SR2_BUSY_Pos) /*!< 0x00000002 */
+#define I2C_SR2_BUSY I2C_SR2_BUSY_Msk /*!< Bus Busy */
+#define I2C_SR2_TRA_Pos (2U)
+#define I2C_SR2_TRA_Msk (0x1U << I2C_SR2_TRA_Pos) /*!< 0x00000004 */
+#define I2C_SR2_TRA I2C_SR2_TRA_Msk /*!< Transmitter/Receiver */
+#define I2C_SR2_GENCALL_Pos (4U)
+#define I2C_SR2_GENCALL_Msk (0x1U << I2C_SR2_GENCALL_Pos) /*!< 0x00000010 */
+#define I2C_SR2_GENCALL I2C_SR2_GENCALL_Msk /*!< General Call Address (Slave mode) */
+#define I2C_SR2_SMBDEFAULT_Pos (5U)
+#define I2C_SR2_SMBDEFAULT_Msk (0x1U << I2C_SR2_SMBDEFAULT_Pos) /*!< 0x00000020 */
+#define I2C_SR2_SMBDEFAULT I2C_SR2_SMBDEFAULT_Msk /*!< SMBus Device Default Address (Slave mode) */
+#define I2C_SR2_SMBHOST_Pos (6U)
+#define I2C_SR2_SMBHOST_Msk (0x1U << I2C_SR2_SMBHOST_Pos) /*!< 0x00000040 */
+#define I2C_SR2_SMBHOST I2C_SR2_SMBHOST_Msk /*!< SMBus Host Header (Slave mode) */
+#define I2C_SR2_DUALF_Pos (7U)
+#define I2C_SR2_DUALF_Msk (0x1U << I2C_SR2_DUALF_Pos) /*!< 0x00000080 */
+#define I2C_SR2_DUALF I2C_SR2_DUALF_Msk /*!< Dual Flag (Slave mode) */
+#define I2C_SR2_PEC_Pos (8U)
+#define I2C_SR2_PEC_Msk (0xFFU << I2C_SR2_PEC_Pos) /*!< 0x0000FF00 */
+#define I2C_SR2_PEC I2C_SR2_PEC_Msk /*!< Packet Error Checking Register */
+
+/******************* Bit definition for I2C_CCR register ********************/
+#define I2C_CCR_CCR_Pos (0U)
+#define I2C_CCR_CCR_Msk (0xFFFU << I2C_CCR_CCR_Pos) /*!< 0x00000FFF */
+#define I2C_CCR_CCR I2C_CCR_CCR_Msk /*!< Clock Control Register in Fast/Standard mode (Master mode) */
+#define I2C_CCR_DUTY_Pos (14U)
+#define I2C_CCR_DUTY_Msk (0x1U << I2C_CCR_DUTY_Pos) /*!< 0x00004000 */
+#define I2C_CCR_DUTY I2C_CCR_DUTY_Msk /*!< Fast Mode Duty Cycle */
+#define I2C_CCR_FS_Pos (15U)
+#define I2C_CCR_FS_Msk (0x1U << I2C_CCR_FS_Pos) /*!< 0x00008000 */
+#define I2C_CCR_FS I2C_CCR_FS_Msk /*!< I2C Master Mode Selection */
+
+/****************** Bit definition for I2C_TRISE register *******************/
+#define I2C_TRISE_TRISE_Pos (0U)
+#define I2C_TRISE_TRISE_Msk (0x3FU << I2C_TRISE_TRISE_Pos) /*!< 0x0000003F */
+#define I2C_TRISE_TRISE I2C_TRISE_TRISE_Msk /*!< Maximum Rise Time in Fast/Standard mode (Master mode) */
+
+/******************************************************************************/
+/* */
+/* Universal Synchronous Asynchronous Receiver Transmitter */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for USART_SR register *******************/
+#define USART_SR_PE_Pos (0U)
+#define USART_SR_PE_Msk (0x1U << USART_SR_PE_Pos) /*!< 0x00000001 */
+#define USART_SR_PE USART_SR_PE_Msk /*!< Parity Error */
+#define USART_SR_FE_Pos (1U)
+#define USART_SR_FE_Msk (0x1U << USART_SR_FE_Pos) /*!< 0x00000002 */
+#define USART_SR_FE USART_SR_FE_Msk /*!< Framing Error */
+#define USART_SR_NE_Pos (2U)
+#define USART_SR_NE_Msk (0x1U << USART_SR_NE_Pos) /*!< 0x00000004 */
+#define USART_SR_NE USART_SR_NE_Msk /*!< Noise Error Flag */
+#define USART_SR_ORE_Pos (3U)
+#define USART_SR_ORE_Msk (0x1U << USART_SR_ORE_Pos) /*!< 0x00000008 */
+#define USART_SR_ORE USART_SR_ORE_Msk /*!< OverRun Error */
+#define USART_SR_IDLE_Pos (4U)
+#define USART_SR_IDLE_Msk (0x1U << USART_SR_IDLE_Pos) /*!< 0x00000010 */
+#define USART_SR_IDLE USART_SR_IDLE_Msk /*!< IDLE line detected */
+#define USART_SR_RXNE_Pos (5U)
+#define USART_SR_RXNE_Msk (0x1U << USART_SR_RXNE_Pos) /*!< 0x00000020 */
+#define USART_SR_RXNE USART_SR_RXNE_Msk /*!< Read Data Register Not Empty */
+#define USART_SR_TC_Pos (6U)
+#define USART_SR_TC_Msk (0x1U << USART_SR_TC_Pos) /*!< 0x00000040 */
+#define USART_SR_TC USART_SR_TC_Msk /*!< Transmission Complete */
+#define USART_SR_TXE_Pos (7U)
+#define USART_SR_TXE_Msk (0x1U << USART_SR_TXE_Pos) /*!< 0x00000080 */
+#define USART_SR_TXE USART_SR_TXE_Msk /*!< Transmit Data Register Empty */
+#define USART_SR_LBD_Pos (8U)
+#define USART_SR_LBD_Msk (0x1U << USART_SR_LBD_Pos) /*!< 0x00000100 */
+#define USART_SR_LBD USART_SR_LBD_Msk /*!< LIN Break Detection Flag */
+#define USART_SR_CTS_Pos (9U)
+#define USART_SR_CTS_Msk (0x1U << USART_SR_CTS_Pos) /*!< 0x00000200 */
+#define USART_SR_CTS USART_SR_CTS_Msk /*!< CTS Flag */
+
+/******************* Bit definition for USART_DR register *******************/
+#define USART_DR_DR_Pos (0U)
+#define USART_DR_DR_Msk (0x1FFU << USART_DR_DR_Pos) /*!< 0x000001FF */
+#define USART_DR_DR USART_DR_DR_Msk /*!< Data value */
+
+/****************** Bit definition for USART_BRR register *******************/
+#define USART_BRR_DIV_Fraction_Pos (0U)
+#define USART_BRR_DIV_Fraction_Msk (0xFU << USART_BRR_DIV_Fraction_Pos) /*!< 0x0000000F */
+#define USART_BRR_DIV_Fraction USART_BRR_DIV_Fraction_Msk /*!< Fraction of USARTDIV */
+#define USART_BRR_DIV_Mantissa_Pos (4U)
+#define USART_BRR_DIV_Mantissa_Msk (0xFFFU << USART_BRR_DIV_Mantissa_Pos) /*!< 0x0000FFF0 */
+#define USART_BRR_DIV_Mantissa USART_BRR_DIV_Mantissa_Msk /*!< Mantissa of USARTDIV */
+
+/****************** Bit definition for USART_CR1 register *******************/
+#define USART_CR1_SBK_Pos (0U)
+#define USART_CR1_SBK_Msk (0x1U << USART_CR1_SBK_Pos) /*!< 0x00000001 */
+#define USART_CR1_SBK USART_CR1_SBK_Msk /*!< Send Break */
+#define USART_CR1_RWU_Pos (1U)
+#define USART_CR1_RWU_Msk (0x1U << USART_CR1_RWU_Pos) /*!< 0x00000002 */
+#define USART_CR1_RWU USART_CR1_RWU_Msk /*!< Receiver wakeup */
+#define USART_CR1_RE_Pos (2U)
+#define USART_CR1_RE_Msk (0x1U << USART_CR1_RE_Pos) /*!< 0x00000004 */
+#define USART_CR1_RE USART_CR1_RE_Msk /*!< Receiver Enable */
+#define USART_CR1_TE_Pos (3U)
+#define USART_CR1_TE_Msk (0x1U << USART_CR1_TE_Pos) /*!< 0x00000008 */
+#define USART_CR1_TE USART_CR1_TE_Msk /*!< Transmitter Enable */
+#define USART_CR1_IDLEIE_Pos (4U)
+#define USART_CR1_IDLEIE_Msk (0x1U << USART_CR1_IDLEIE_Pos) /*!< 0x00000010 */
+#define USART_CR1_IDLEIE USART_CR1_IDLEIE_Msk /*!< IDLE Interrupt Enable */
+#define USART_CR1_RXNEIE_Pos (5U)
+#define USART_CR1_RXNEIE_Msk (0x1U << USART_CR1_RXNEIE_Pos) /*!< 0x00000020 */
+#define USART_CR1_RXNEIE USART_CR1_RXNEIE_Msk /*!< RXNE Interrupt Enable */
+#define USART_CR1_TCIE_Pos (6U)
+#define USART_CR1_TCIE_Msk (0x1U << USART_CR1_TCIE_Pos) /*!< 0x00000040 */
+#define USART_CR1_TCIE USART_CR1_TCIE_Msk /*!< Transmission Complete Interrupt Enable */
+#define USART_CR1_TXEIE_Pos (7U)
+#define USART_CR1_TXEIE_Msk (0x1U << USART_CR1_TXEIE_Pos) /*!< 0x00000080 */
+#define USART_CR1_TXEIE USART_CR1_TXEIE_Msk /*!< PE Interrupt Enable */
+#define USART_CR1_PEIE_Pos (8U)
+#define USART_CR1_PEIE_Msk (0x1U << USART_CR1_PEIE_Pos) /*!< 0x00000100 */
+#define USART_CR1_PEIE USART_CR1_PEIE_Msk /*!< PE Interrupt Enable */
+#define USART_CR1_PS_Pos (9U)
+#define USART_CR1_PS_Msk (0x1U << USART_CR1_PS_Pos) /*!< 0x00000200 */
+#define USART_CR1_PS USART_CR1_PS_Msk /*!< Parity Selection */
+#define USART_CR1_PCE_Pos (10U)
+#define USART_CR1_PCE_Msk (0x1U << USART_CR1_PCE_Pos) /*!< 0x00000400 */
+#define USART_CR1_PCE USART_CR1_PCE_Msk /*!< Parity Control Enable */
+#define USART_CR1_WAKE_Pos (11U)
+#define USART_CR1_WAKE_Msk (0x1U << USART_CR1_WAKE_Pos) /*!< 0x00000800 */
+#define USART_CR1_WAKE USART_CR1_WAKE_Msk /*!< Wakeup method */
+#define USART_CR1_M_Pos (12U)
+#define USART_CR1_M_Msk (0x1U << USART_CR1_M_Pos) /*!< 0x00001000 */
+#define USART_CR1_M USART_CR1_M_Msk /*!< Word length */
+#define USART_CR1_UE_Pos (13U)
+#define USART_CR1_UE_Msk (0x1U << USART_CR1_UE_Pos) /*!< 0x00002000 */
+#define USART_CR1_UE USART_CR1_UE_Msk /*!< USART Enable */
+
+/****************** Bit definition for USART_CR2 register *******************/
+#define USART_CR2_ADD_Pos (0U)
+#define USART_CR2_ADD_Msk (0xFU << USART_CR2_ADD_Pos) /*!< 0x0000000F */
+#define USART_CR2_ADD USART_CR2_ADD_Msk /*!< Address of the USART node */
+#define USART_CR2_LBDL_Pos (5U)
+#define USART_CR2_LBDL_Msk (0x1U << USART_CR2_LBDL_Pos) /*!< 0x00000020 */
+#define USART_CR2_LBDL USART_CR2_LBDL_Msk /*!< LIN Break Detection Length */
+#define USART_CR2_LBDIE_Pos (6U)
+#define USART_CR2_LBDIE_Msk (0x1U << USART_CR2_LBDIE_Pos) /*!< 0x00000040 */
+#define USART_CR2_LBDIE USART_CR2_LBDIE_Msk /*!< LIN Break Detection Interrupt Enable */
+#define USART_CR2_LBCL_Pos (8U)
+#define USART_CR2_LBCL_Msk (0x1U << USART_CR2_LBCL_Pos) /*!< 0x00000100 */
+#define USART_CR2_LBCL USART_CR2_LBCL_Msk /*!< Last Bit Clock pulse */
+#define USART_CR2_CPHA_Pos (9U)
+#define USART_CR2_CPHA_Msk (0x1U << USART_CR2_CPHA_Pos) /*!< 0x00000200 */
+#define USART_CR2_CPHA USART_CR2_CPHA_Msk /*!< Clock Phase */
+#define USART_CR2_CPOL_Pos (10U)
+#define USART_CR2_CPOL_Msk (0x1U << USART_CR2_CPOL_Pos) /*!< 0x00000400 */
+#define USART_CR2_CPOL USART_CR2_CPOL_Msk /*!< Clock Polarity */
+#define USART_CR2_CLKEN_Pos (11U)
+#define USART_CR2_CLKEN_Msk (0x1U << USART_CR2_CLKEN_Pos) /*!< 0x00000800 */
+#define USART_CR2_CLKEN USART_CR2_CLKEN_Msk /*!< Clock Enable */
+
+#define USART_CR2_STOP_Pos (12U)
+#define USART_CR2_STOP_Msk (0x3U << USART_CR2_STOP_Pos) /*!< 0x00003000 */
+#define USART_CR2_STOP USART_CR2_STOP_Msk /*!< STOP[1:0] bits (STOP bits) */
+#define USART_CR2_STOP_0 (0x1U << USART_CR2_STOP_Pos) /*!< 0x00001000 */
+#define USART_CR2_STOP_1 (0x2U << USART_CR2_STOP_Pos) /*!< 0x00002000 */
+
+#define USART_CR2_LINEN_Pos (14U)
+#define USART_CR2_LINEN_Msk (0x1U << USART_CR2_LINEN_Pos) /*!< 0x00004000 */
+#define USART_CR2_LINEN USART_CR2_LINEN_Msk /*!< LIN mode enable */
+
+/****************** Bit definition for USART_CR3 register *******************/
+#define USART_CR3_EIE_Pos (0U)
+#define USART_CR3_EIE_Msk (0x1U << USART_CR3_EIE_Pos) /*!< 0x00000001 */
+#define USART_CR3_EIE USART_CR3_EIE_Msk /*!< Error Interrupt Enable */
+#define USART_CR3_IREN_Pos (1U)
+#define USART_CR3_IREN_Msk (0x1U << USART_CR3_IREN_Pos) /*!< 0x00000002 */
+#define USART_CR3_IREN USART_CR3_IREN_Msk /*!< IrDA mode Enable */
+#define USART_CR3_IRLP_Pos (2U)
+#define USART_CR3_IRLP_Msk (0x1U << USART_CR3_IRLP_Pos) /*!< 0x00000004 */
+#define USART_CR3_IRLP USART_CR3_IRLP_Msk /*!< IrDA Low-Power */
+#define USART_CR3_HDSEL_Pos (3U)
+#define USART_CR3_HDSEL_Msk (0x1U << USART_CR3_HDSEL_Pos) /*!< 0x00000008 */
+#define USART_CR3_HDSEL USART_CR3_HDSEL_Msk /*!< Half-Duplex Selection */
+#define USART_CR3_NACK_Pos (4U)
+#define USART_CR3_NACK_Msk (0x1U << USART_CR3_NACK_Pos) /*!< 0x00000010 */
+#define USART_CR3_NACK USART_CR3_NACK_Msk /*!< Smartcard NACK enable */
+#define USART_CR3_SCEN_Pos (5U)
+#define USART_CR3_SCEN_Msk (0x1U << USART_CR3_SCEN_Pos) /*!< 0x00000020 */
+#define USART_CR3_SCEN USART_CR3_SCEN_Msk /*!< Smartcard mode enable */
+#define USART_CR3_DMAR_Pos (6U)
+#define USART_CR3_DMAR_Msk (0x1U << USART_CR3_DMAR_Pos) /*!< 0x00000040 */
+#define USART_CR3_DMAR USART_CR3_DMAR_Msk /*!< DMA Enable Receiver */
+#define USART_CR3_DMAT_Pos (7U)
+#define USART_CR3_DMAT_Msk (0x1U << USART_CR3_DMAT_Pos) /*!< 0x00000080 */
+#define USART_CR3_DMAT USART_CR3_DMAT_Msk /*!< DMA Enable Transmitter */
+#define USART_CR3_RTSE_Pos (8U)
+#define USART_CR3_RTSE_Msk (0x1U << USART_CR3_RTSE_Pos) /*!< 0x00000100 */
+#define USART_CR3_RTSE USART_CR3_RTSE_Msk /*!< RTS Enable */
+#define USART_CR3_CTSE_Pos (9U)
+#define USART_CR3_CTSE_Msk (0x1U << USART_CR3_CTSE_Pos) /*!< 0x00000200 */
+#define USART_CR3_CTSE USART_CR3_CTSE_Msk /*!< CTS Enable */
+#define USART_CR3_CTSIE_Pos (10U)
+#define USART_CR3_CTSIE_Msk (0x1U << USART_CR3_CTSIE_Pos) /*!< 0x00000400 */
+#define USART_CR3_CTSIE USART_CR3_CTSIE_Msk /*!< CTS Interrupt Enable */
+
+/****************** Bit definition for USART_GTPR register ******************/
+#define USART_GTPR_PSC_Pos (0U)
+#define USART_GTPR_PSC_Msk (0xFFU << USART_GTPR_PSC_Pos) /*!< 0x000000FF */
+#define USART_GTPR_PSC USART_GTPR_PSC_Msk /*!< PSC[7:0] bits (Prescaler value) */
+#define USART_GTPR_PSC_0 (0x01U << USART_GTPR_PSC_Pos) /*!< 0x00000001 */
+#define USART_GTPR_PSC_1 (0x02U << USART_GTPR_PSC_Pos) /*!< 0x00000002 */
+#define USART_GTPR_PSC_2 (0x04U << USART_GTPR_PSC_Pos) /*!< 0x00000004 */
+#define USART_GTPR_PSC_3 (0x08U << USART_GTPR_PSC_Pos) /*!< 0x00000008 */
+#define USART_GTPR_PSC_4 (0x10U << USART_GTPR_PSC_Pos) /*!< 0x00000010 */
+#define USART_GTPR_PSC_5 (0x20U << USART_GTPR_PSC_Pos) /*!< 0x00000020 */
+#define USART_GTPR_PSC_6 (0x40U << USART_GTPR_PSC_Pos) /*!< 0x00000040 */
+#define USART_GTPR_PSC_7 (0x80U << USART_GTPR_PSC_Pos) /*!< 0x00000080 */
+
+#define USART_GTPR_GT_Pos (8U)
+#define USART_GTPR_GT_Msk (0xFFU << USART_GTPR_GT_Pos) /*!< 0x0000FF00 */
+#define USART_GTPR_GT USART_GTPR_GT_Msk /*!< Guard time value */
+
+/******************************************************************************/
+/* */
+/* Debug MCU */
+/* */
+/******************************************************************************/
+
+/**************** Bit definition for DBGMCU_IDCODE register *****************/
+#define DBGMCU_IDCODE_DEV_ID_Pos (0U)
+#define DBGMCU_IDCODE_DEV_ID_Msk (0xFFFU << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */
+#define DBGMCU_IDCODE_DEV_ID DBGMCU_IDCODE_DEV_ID_Msk /*!< Device Identifier */
+
+#define DBGMCU_IDCODE_REV_ID_Pos (16U)
+#define DBGMCU_IDCODE_REV_ID_Msk (0xFFFFU << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */
+#define DBGMCU_IDCODE_REV_ID DBGMCU_IDCODE_REV_ID_Msk /*!< REV_ID[15:0] bits (Revision Identifier) */
+#define DBGMCU_IDCODE_REV_ID_0 (0x0001U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00010000 */
+#define DBGMCU_IDCODE_REV_ID_1 (0x0002U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00020000 */
+#define DBGMCU_IDCODE_REV_ID_2 (0x0004U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00040000 */
+#define DBGMCU_IDCODE_REV_ID_3 (0x0008U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00080000 */
+#define DBGMCU_IDCODE_REV_ID_4 (0x0010U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00100000 */
+#define DBGMCU_IDCODE_REV_ID_5 (0x0020U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00200000 */
+#define DBGMCU_IDCODE_REV_ID_6 (0x0040U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00400000 */
+#define DBGMCU_IDCODE_REV_ID_7 (0x0080U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00800000 */
+#define DBGMCU_IDCODE_REV_ID_8 (0x0100U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x01000000 */
+#define DBGMCU_IDCODE_REV_ID_9 (0x0200U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x02000000 */
+#define DBGMCU_IDCODE_REV_ID_10 (0x0400U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x04000000 */
+#define DBGMCU_IDCODE_REV_ID_11 (0x0800U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x08000000 */
+#define DBGMCU_IDCODE_REV_ID_12 (0x1000U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x10000000 */
+#define DBGMCU_IDCODE_REV_ID_13 (0x2000U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x20000000 */
+#define DBGMCU_IDCODE_REV_ID_14 (0x4000U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x40000000 */
+#define DBGMCU_IDCODE_REV_ID_15 (0x8000U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x80000000 */
+
+/****************** Bit definition for DBGMCU_CR register *******************/
+#define DBGMCU_CR_DBG_SLEEP_Pos (0U)
+#define DBGMCU_CR_DBG_SLEEP_Msk (0x1U << DBGMCU_CR_DBG_SLEEP_Pos) /*!< 0x00000001 */
+#define DBGMCU_CR_DBG_SLEEP DBGMCU_CR_DBG_SLEEP_Msk /*!< Debug Sleep Mode */
+#define DBGMCU_CR_DBG_STOP_Pos (1U)
+#define DBGMCU_CR_DBG_STOP_Msk (0x1U << DBGMCU_CR_DBG_STOP_Pos) /*!< 0x00000002 */
+#define DBGMCU_CR_DBG_STOP DBGMCU_CR_DBG_STOP_Msk /*!< Debug Stop Mode */
+#define DBGMCU_CR_DBG_STANDBY_Pos (2U)
+#define DBGMCU_CR_DBG_STANDBY_Msk (0x1U << DBGMCU_CR_DBG_STANDBY_Pos) /*!< 0x00000004 */
+#define DBGMCU_CR_DBG_STANDBY DBGMCU_CR_DBG_STANDBY_Msk /*!< Debug Standby mode */
+#define DBGMCU_CR_TRACE_IOEN_Pos (5U)
+#define DBGMCU_CR_TRACE_IOEN_Msk (0x1U << DBGMCU_CR_TRACE_IOEN_Pos) /*!< 0x00000020 */
+#define DBGMCU_CR_TRACE_IOEN DBGMCU_CR_TRACE_IOEN_Msk /*!< Trace Pin Assignment Control */
+
+#define DBGMCU_CR_TRACE_MODE_Pos (6U)
+#define DBGMCU_CR_TRACE_MODE_Msk (0x3U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x000000C0 */
+#define DBGMCU_CR_TRACE_MODE DBGMCU_CR_TRACE_MODE_Msk /*!< TRACE_MODE[1:0] bits (Trace Pin Assignment Control) */
+#define DBGMCU_CR_TRACE_MODE_0 (0x1U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000040 */
+#define DBGMCU_CR_TRACE_MODE_1 (0x2U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000080 */
+
+#define DBGMCU_CR_DBG_IWDG_STOP_Pos (8U)
+#define DBGMCU_CR_DBG_IWDG_STOP_Msk (0x1U << DBGMCU_CR_DBG_IWDG_STOP_Pos) /*!< 0x00000100 */
+#define DBGMCU_CR_DBG_IWDG_STOP DBGMCU_CR_DBG_IWDG_STOP_Msk /*!< Debug Independent Watchdog stopped when Core is halted */
+#define DBGMCU_CR_DBG_WWDG_STOP_Pos (9U)
+#define DBGMCU_CR_DBG_WWDG_STOP_Msk (0x1U << DBGMCU_CR_DBG_WWDG_STOP_Pos) /*!< 0x00000200 */
+#define DBGMCU_CR_DBG_WWDG_STOP DBGMCU_CR_DBG_WWDG_STOP_Msk /*!< Debug Window Watchdog stopped when Core is halted */
+#define DBGMCU_CR_DBG_TIM2_STOP_Pos (11U)
+#define DBGMCU_CR_DBG_TIM2_STOP_Msk (0x1U << DBGMCU_CR_DBG_TIM2_STOP_Pos) /*!< 0x00000800 */
+#define DBGMCU_CR_DBG_TIM2_STOP DBGMCU_CR_DBG_TIM2_STOP_Msk /*!< TIM2 counter stopped when core is halted */
+#define DBGMCU_CR_DBG_TIM3_STOP_Pos (12U)
+#define DBGMCU_CR_DBG_TIM3_STOP_Msk (0x1U << DBGMCU_CR_DBG_TIM3_STOP_Pos) /*!< 0x00001000 */
+#define DBGMCU_CR_DBG_TIM3_STOP DBGMCU_CR_DBG_TIM3_STOP_Msk /*!< TIM3 counter stopped when core is halted */
+#define DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT_Pos (15U)
+#define DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT_Msk (0x1U << DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT_Pos) /*!< 0x00008000 */
+#define DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT_Msk /*!< SMBUS timeout mode stopped when Core is halted */
+
+/******************************************************************************/
+/* */
+/* FLASH and Option Bytes Registers */
+/* */
+/******************************************************************************/
+/******************* Bit definition for FLASH_ACR register ******************/
+#define FLASH_ACR_LATENCY_Pos (0U)
+#define FLASH_ACR_LATENCY_Msk (0x7U << FLASH_ACR_LATENCY_Pos) /*!< 0x00000007 */
+#define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk /*!< LATENCY[2:0] bits (Latency) */
+#define FLASH_ACR_LATENCY_0 (0x1U << FLASH_ACR_LATENCY_Pos) /*!< 0x00000001 */
+#define FLASH_ACR_LATENCY_1 (0x2U << FLASH_ACR_LATENCY_Pos) /*!< 0x00000002 */
+#define FLASH_ACR_LATENCY_2 (0x4U << FLASH_ACR_LATENCY_Pos) /*!< 0x00000004 */
+
+#define FLASH_ACR_HLFCYA_Pos (3U)
+#define FLASH_ACR_HLFCYA_Msk (0x1U << FLASH_ACR_HLFCYA_Pos) /*!< 0x00000008 */
+#define FLASH_ACR_HLFCYA FLASH_ACR_HLFCYA_Msk /*!< Flash Half Cycle Access Enable */
+#define FLASH_ACR_PRFTBE_Pos (4U)
+#define FLASH_ACR_PRFTBE_Msk (0x1U << FLASH_ACR_PRFTBE_Pos) /*!< 0x00000010 */
+#define FLASH_ACR_PRFTBE FLASH_ACR_PRFTBE_Msk /*!< Prefetch Buffer Enable */
+#define FLASH_ACR_PRFTBS_Pos (5U)
+#define FLASH_ACR_PRFTBS_Msk (0x1U << FLASH_ACR_PRFTBS_Pos) /*!< 0x00000020 */
+#define FLASH_ACR_PRFTBS FLASH_ACR_PRFTBS_Msk /*!< Prefetch Buffer Status */
+
+/****************** Bit definition for FLASH_KEYR register ******************/
+#define FLASH_KEYR_FKEYR_Pos (0U)
+#define FLASH_KEYR_FKEYR_Msk (0xFFFFFFFFU << FLASH_KEYR_FKEYR_Pos) /*!< 0xFFFFFFFF */
+#define FLASH_KEYR_FKEYR FLASH_KEYR_FKEYR_Msk /*!< FPEC Key */
+
+#define RDP_KEY_Pos (0U)
+#define RDP_KEY_Msk (0xA5U << RDP_KEY_Pos) /*!< 0x000000A5 */
+#define RDP_KEY RDP_KEY_Msk /*!< RDP Key */
+#define FLASH_KEY1_Pos (0U)
+#define FLASH_KEY1_Msk (0x45670123U << FLASH_KEY1_Pos) /*!< 0x45670123 */
+#define FLASH_KEY1 FLASH_KEY1_Msk /*!< FPEC Key1 */
+#define FLASH_KEY2_Pos (0U)
+#define FLASH_KEY2_Msk (0xCDEF89ABU << FLASH_KEY2_Pos) /*!< 0xCDEF89AB */
+#define FLASH_KEY2 FLASH_KEY2_Msk /*!< FPEC Key2 */
+
+/***************** Bit definition for FLASH_OPTKEYR register ****************/
+#define FLASH_OPTKEYR_OPTKEYR_Pos (0U)
+#define FLASH_OPTKEYR_OPTKEYR_Msk (0xFFFFFFFFU << FLASH_OPTKEYR_OPTKEYR_Pos) /*!< 0xFFFFFFFF */
+#define FLASH_OPTKEYR_OPTKEYR FLASH_OPTKEYR_OPTKEYR_Msk /*!< Option Byte Key */
+
+#define FLASH_OPTKEY1 FLASH_KEY1 /*!< Option Byte Key1 */
+#define FLASH_OPTKEY2 FLASH_KEY2 /*!< Option Byte Key2 */
+
+/****************** Bit definition for FLASH_SR register ********************/
+#define FLASH_SR_BSY_Pos (0U)
+#define FLASH_SR_BSY_Msk (0x1U << FLASH_SR_BSY_Pos) /*!< 0x00000001 */
+#define FLASH_SR_BSY FLASH_SR_BSY_Msk /*!< Busy */
+#define FLASH_SR_PGERR_Pos (2U)
+#define FLASH_SR_PGERR_Msk (0x1U << FLASH_SR_PGERR_Pos) /*!< 0x00000004 */
+#define FLASH_SR_PGERR FLASH_SR_PGERR_Msk /*!< Programming Error */
+#define FLASH_SR_WRPRTERR_Pos (4U)
+#define FLASH_SR_WRPRTERR_Msk (0x1U << FLASH_SR_WRPRTERR_Pos) /*!< 0x00000010 */
+#define FLASH_SR_WRPRTERR FLASH_SR_WRPRTERR_Msk /*!< Write Protection Error */
+#define FLASH_SR_EOP_Pos (5U)
+#define FLASH_SR_EOP_Msk (0x1U << FLASH_SR_EOP_Pos) /*!< 0x00000020 */
+#define FLASH_SR_EOP FLASH_SR_EOP_Msk /*!< End of operation */
+
+/******************* Bit definition for FLASH_CR register *******************/
+#define FLASH_CR_PG_Pos (0U)
+#define FLASH_CR_PG_Msk (0x1U << FLASH_CR_PG_Pos) /*!< 0x00000001 */
+#define FLASH_CR_PG FLASH_CR_PG_Msk /*!< Programming */
+#define FLASH_CR_PER_Pos (1U)
+#define FLASH_CR_PER_Msk (0x1U << FLASH_CR_PER_Pos) /*!< 0x00000002 */
+#define FLASH_CR_PER FLASH_CR_PER_Msk /*!< Page Erase */
+#define FLASH_CR_MER_Pos (2U)
+#define FLASH_CR_MER_Msk (0x1U << FLASH_CR_MER_Pos) /*!< 0x00000004 */
+#define FLASH_CR_MER FLASH_CR_MER_Msk /*!< Mass Erase */
+#define FLASH_CR_OPTPG_Pos (4U)
+#define FLASH_CR_OPTPG_Msk (0x1U << FLASH_CR_OPTPG_Pos) /*!< 0x00000010 */
+#define FLASH_CR_OPTPG FLASH_CR_OPTPG_Msk /*!< Option Byte Programming */
+#define FLASH_CR_OPTER_Pos (5U)
+#define FLASH_CR_OPTER_Msk (0x1U << FLASH_CR_OPTER_Pos) /*!< 0x00000020 */
+#define FLASH_CR_OPTER FLASH_CR_OPTER_Msk /*!< Option Byte Erase */
+#define FLASH_CR_STRT_Pos (6U)
+#define FLASH_CR_STRT_Msk (0x1U << FLASH_CR_STRT_Pos) /*!< 0x00000040 */
+#define FLASH_CR_STRT FLASH_CR_STRT_Msk /*!< Start */
+#define FLASH_CR_LOCK_Pos (7U)
+#define FLASH_CR_LOCK_Msk (0x1U << FLASH_CR_LOCK_Pos) /*!< 0x00000080 */
+#define FLASH_CR_LOCK FLASH_CR_LOCK_Msk /*!< Lock */
+#define FLASH_CR_OPTWRE_Pos (9U)
+#define FLASH_CR_OPTWRE_Msk (0x1U << FLASH_CR_OPTWRE_Pos) /*!< 0x00000200 */
+#define FLASH_CR_OPTWRE FLASH_CR_OPTWRE_Msk /*!< Option Bytes Write Enable */
+#define FLASH_CR_ERRIE_Pos (10U)
+#define FLASH_CR_ERRIE_Msk (0x1U << FLASH_CR_ERRIE_Pos) /*!< 0x00000400 */
+#define FLASH_CR_ERRIE FLASH_CR_ERRIE_Msk /*!< Error Interrupt Enable */
+#define FLASH_CR_EOPIE_Pos (12U)
+#define FLASH_CR_EOPIE_Msk (0x1U << FLASH_CR_EOPIE_Pos) /*!< 0x00001000 */
+#define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk /*!< End of operation interrupt enable */
+
+/******************* Bit definition for FLASH_AR register *******************/
+#define FLASH_AR_FAR_Pos (0U)
+#define FLASH_AR_FAR_Msk (0xFFFFFFFFU << FLASH_AR_FAR_Pos) /*!< 0xFFFFFFFF */
+#define FLASH_AR_FAR FLASH_AR_FAR_Msk /*!< Flash Address */
+
+/****************** Bit definition for FLASH_OBR register *******************/
+#define FLASH_OBR_OPTERR_Pos (0U)
+#define FLASH_OBR_OPTERR_Msk (0x1U << FLASH_OBR_OPTERR_Pos) /*!< 0x00000001 */
+#define FLASH_OBR_OPTERR FLASH_OBR_OPTERR_Msk /*!< Option Byte Error */
+#define FLASH_OBR_RDPRT_Pos (1U)
+#define FLASH_OBR_RDPRT_Msk (0x1U << FLASH_OBR_RDPRT_Pos) /*!< 0x00000002 */
+#define FLASH_OBR_RDPRT FLASH_OBR_RDPRT_Msk /*!< Read protection */
+
+#define FLASH_OBR_IWDG_SW_Pos (2U)
+#define FLASH_OBR_IWDG_SW_Msk (0x1U << FLASH_OBR_IWDG_SW_Pos) /*!< 0x00000004 */
+#define FLASH_OBR_IWDG_SW FLASH_OBR_IWDG_SW_Msk /*!< IWDG SW */
+#define FLASH_OBR_nRST_STOP_Pos (3U)
+#define FLASH_OBR_nRST_STOP_Msk (0x1U << FLASH_OBR_nRST_STOP_Pos) /*!< 0x00000008 */
+#define FLASH_OBR_nRST_STOP FLASH_OBR_nRST_STOP_Msk /*!< nRST_STOP */
+#define FLASH_OBR_nRST_STDBY_Pos (4U)
+#define FLASH_OBR_nRST_STDBY_Msk (0x1U << FLASH_OBR_nRST_STDBY_Pos) /*!< 0x00000010 */
+#define FLASH_OBR_nRST_STDBY FLASH_OBR_nRST_STDBY_Msk /*!< nRST_STDBY */
+#define FLASH_OBR_USER_Pos (2U)
+#define FLASH_OBR_USER_Msk (0x7U << FLASH_OBR_USER_Pos) /*!< 0x0000001C */
+#define FLASH_OBR_USER FLASH_OBR_USER_Msk /*!< User Option Bytes */
+#define FLASH_OBR_DATA0_Pos (10U)
+#define FLASH_OBR_DATA0_Msk (0xFFU << FLASH_OBR_DATA0_Pos) /*!< 0x0003FC00 */
+#define FLASH_OBR_DATA0 FLASH_OBR_DATA0_Msk /*!< Data0 */
+#define FLASH_OBR_DATA1_Pos (18U)
+#define FLASH_OBR_DATA1_Msk (0xFFU << FLASH_OBR_DATA1_Pos) /*!< 0x03FC0000 */
+#define FLASH_OBR_DATA1 FLASH_OBR_DATA1_Msk /*!< Data1 */
+
+/****************** Bit definition for FLASH_WRPR register ******************/
+#define FLASH_WRPR_WRP_Pos (0U)
+#define FLASH_WRPR_WRP_Msk (0xFFFFFFFFU << FLASH_WRPR_WRP_Pos) /*!< 0xFFFFFFFF */
+#define FLASH_WRPR_WRP FLASH_WRPR_WRP_Msk /*!< Write Protect */
+
+/*----------------------------------------------------------------------------*/
+
+/****************** Bit definition for FLASH_RDP register *******************/
+#define FLASH_RDP_RDP_Pos (0U)
+#define FLASH_RDP_RDP_Msk (0xFFU << FLASH_RDP_RDP_Pos) /*!< 0x000000FF */
+#define FLASH_RDP_RDP FLASH_RDP_RDP_Msk /*!< Read protection option byte */
+#define FLASH_RDP_nRDP_Pos (8U)
+#define FLASH_RDP_nRDP_Msk (0xFFU << FLASH_RDP_nRDP_Pos) /*!< 0x0000FF00 */
+#define FLASH_RDP_nRDP FLASH_RDP_nRDP_Msk /*!< Read protection complemented option byte */
+
+/****************** Bit definition for FLASH_USER register ******************/
+#define FLASH_USER_USER_Pos (16U)
+#define FLASH_USER_USER_Msk (0xFFU << FLASH_USER_USER_Pos) /*!< 0x00FF0000 */
+#define FLASH_USER_USER FLASH_USER_USER_Msk /*!< User option byte */
+#define FLASH_USER_nUSER_Pos (24U)
+#define FLASH_USER_nUSER_Msk (0xFFU << FLASH_USER_nUSER_Pos) /*!< 0xFF000000 */
+#define FLASH_USER_nUSER FLASH_USER_nUSER_Msk /*!< User complemented option byte */
+
+/****************** Bit definition for FLASH_Data0 register *****************/
+#define FLASH_DATA0_DATA0_Pos (0U)
+#define FLASH_DATA0_DATA0_Msk (0xFFU << FLASH_DATA0_DATA0_Pos) /*!< 0x000000FF */
+#define FLASH_DATA0_DATA0 FLASH_DATA0_DATA0_Msk /*!< User data storage option byte */
+#define FLASH_DATA0_nDATA0_Pos (8U)
+#define FLASH_DATA0_nDATA0_Msk (0xFFU << FLASH_DATA0_nDATA0_Pos) /*!< 0x0000FF00 */
+#define FLASH_DATA0_nDATA0 FLASH_DATA0_nDATA0_Msk /*!< User data storage complemented option byte */
+
+/****************** Bit definition for FLASH_Data1 register *****************/
+#define FLASH_DATA1_DATA1_Pos (16U)
+#define FLASH_DATA1_DATA1_Msk (0xFFU << FLASH_DATA1_DATA1_Pos) /*!< 0x00FF0000 */
+#define FLASH_DATA1_DATA1 FLASH_DATA1_DATA1_Msk /*!< User data storage option byte */
+#define FLASH_DATA1_nDATA1_Pos (24U)
+#define FLASH_DATA1_nDATA1_Msk (0xFFU << FLASH_DATA1_nDATA1_Pos) /*!< 0xFF000000 */
+#define FLASH_DATA1_nDATA1 FLASH_DATA1_nDATA1_Msk /*!< User data storage complemented option byte */
+
+/****************** Bit definition for FLASH_WRP0 register ******************/
+#define FLASH_WRP0_WRP0_Pos (0U)
+#define FLASH_WRP0_WRP0_Msk (0xFFU << FLASH_WRP0_WRP0_Pos) /*!< 0x000000FF */
+#define FLASH_WRP0_WRP0 FLASH_WRP0_WRP0_Msk /*!< Flash memory write protection option bytes */
+#define FLASH_WRP0_nWRP0_Pos (8U)
+#define FLASH_WRP0_nWRP0_Msk (0xFFU << FLASH_WRP0_nWRP0_Pos) /*!< 0x0000FF00 */
+#define FLASH_WRP0_nWRP0 FLASH_WRP0_nWRP0_Msk /*!< Flash memory write protection complemented option bytes */
+
+
+
+/**
+ * @}
+*/
+
+/**
+ * @}
+*/
+
+/** @addtogroup Exported_macro
+ * @{
+ */
+
+/****************************** ADC Instances *********************************/
+#define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1))
+
+#define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC1_COMMON)
+
+#define IS_ADC_DMA_CAPABILITY_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
+
+/****************************** CRC Instances *********************************/
+#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
+
+/****************************** DAC Instances *********************************/
+
+/****************************** DMA Instances *********************************/
+#define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \
+ ((INSTANCE) == DMA1_Channel2) || \
+ ((INSTANCE) == DMA1_Channel3) || \
+ ((INSTANCE) == DMA1_Channel4) || \
+ ((INSTANCE) == DMA1_Channel5) || \
+ ((INSTANCE) == DMA1_Channel6) || \
+ ((INSTANCE) == DMA1_Channel7))
+
+/******************************* GPIO Instances *******************************/
+#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
+ ((INSTANCE) == GPIOB) || \
+ ((INSTANCE) == GPIOC) || \
+ ((INSTANCE) == GPIOD))
+
+/**************************** GPIO Alternate Function Instances ***************/
+#define IS_GPIO_AF_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
+
+/**************************** GPIO Lock Instances *****************************/
+#define IS_GPIO_LOCK_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
+
+/******************************** I2C Instances *******************************/
+#define IS_I2C_ALL_INSTANCE(INSTANCE) ((INSTANCE) == I2C1)
+
+/****************************** IWDG Instances ********************************/
+#define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
+
+/******************************** SPI Instances *******************************/
+#define IS_SPI_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SPI1)
+
+/****************************** START TIM Instances ***************************/
+/****************************** TIM Instances *********************************/
+#define IS_TIM_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3))
+
+#define IS_TIM_CC1_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3))
+
+#define IS_TIM_CC2_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3))
+
+#define IS_TIM_CC3_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3))
+
+#define IS_TIM_CC4_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3))
+
+#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3))
+
+#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3))
+
+#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3))
+
+#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3))
+
+#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3))
+
+#define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3))
+
+#define IS_TIM_XOR_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3))
+
+#define IS_TIM_MASTER_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3))
+
+#define IS_TIM_SLAVE_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3))
+
+#define IS_TIM_DMABURST_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3))
+
+#define IS_TIM_BREAK_INSTANCE(INSTANCE) (0)
+
+#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
+ ((((INSTANCE) == TIM2) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM3) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))))
+
+#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) (0)
+
+#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3))
+
+#define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE) (0)
+
+#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3))
+
+#define IS_TIM_DMA_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3))
+
+#define IS_TIM_DMA_CC_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3))
+
+#define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) (0)
+
+/****************************** END TIM Instances *****************************/
+
+
+/******************** USART Instances : Synchronous mode **********************/
+#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2))
+
+/******************** UART Instances : Asynchronous mode **********************/
+#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) )
+
+/******************** UART Instances : Half-Duplex mode **********************/
+#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) )
+
+/******************** UART Instances : LIN mode **********************/
+#define IS_UART_LIN_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) )
+
+/****************** UART Instances : Hardware Flow control ********************/
+#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) )
+
+/********************* UART Instances : Smard card mode ***********************/
+#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) )
+
+/*********************** UART Instances : IRDA mode ***************************/
+#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) )
+
+/***************** UART Instances : Multi-Processor mode **********************/
+#define IS_UART_MULTIPROCESSOR_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) )
+
+/***************** UART Instances : DMA mode available **********************/
+#define IS_UART_DMA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) )
+
+/****************************** RTC Instances *********************************/
+#define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
+
+/**************************** WWDG Instances *****************************/
+#define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
+
+
+
+
+
+/**
+ * @}
+*/
+/******************************************************************************/
+/* For a painless codes migration between the STM32F1xx device product */
+/* lines, the aliases defined below are put in place to overcome the */
+/* differences in the interrupt handlers and IRQn definitions. */
+/* No need to update developed interrupt code when moving across */
+/* product lines within the same STM32F1 Family */
+/******************************************************************************/
+
+/* Aliases for __IRQn */
+#define ADC1_2_IRQn ADC1_IRQn
+
+
+/* Aliases for __IRQHandler */
+#define ADC1_2_IRQHandler ADC1_IRQHandler
+
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+
+#ifdef __cplusplus
+ }
+#endif /* __cplusplus */
+
+#endif /* __STM32F101x6_H */
+
+
+
+ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Device/ST/STM32F1xx/Include/stm32f101xb.h b/Device/ST/STM32F1xx/Include/stm32f101xb.h
new file mode 100644
index 0000000..2909876
--- /dev/null
+++ b/Device/ST/STM32F1xx/Include/stm32f101xb.h
@@ -0,0 +1,6281 @@
+/**
+ ******************************************************************************
+ * @file stm32f101xb.h
+ * @author MCD Application Team
+ * @version V4.1.0
+ * @date 29-April-2016
+ * @brief CMSIS Cortex-M3 Device Peripheral Access Layer Header File.
+ * This file contains all the peripheral register's definitions, bits
+ * definitions and memory mapping for STM32F1xx devices.
+ *
+ * This file contains:
+ * - Data structures and the address mapping for all peripherals
+ * - Peripheral's registers declarations and bits definition
+ * - Macros to access peripheral’s registers hardware
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+
+/** @addtogroup CMSIS
+ * @{
+ */
+
+/** @addtogroup stm32f101xb
+ * @{
+ */
+
+#ifndef __STM32F101xB_H
+#define __STM32F101xB_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/** @addtogroup Configuration_section_for_CMSIS
+ * @{
+ */
+/**
+ * @brief Configuration of the Cortex-M3 Processor and Core Peripherals
+ */
+ #define __MPU_PRESENT 0 /*!< Other STM32 devices does not provide an MPU */
+#define __CM3_REV 0x0200 /*!< Core Revision r2p0 */
+#define __NVIC_PRIO_BITS 4 /*!< STM32 uses 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
+
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_interrupt_number_definition
+ * @{
+ */
+
+/**
+ * @brief STM32F10x Interrupt Number Definition, according to the selected device
+ * in @ref Library_configuration_section
+ */
+
+ /*!< Interrupt Number Definition */
+typedef enum
+{
+/****** Cortex-M3 Processor Exceptions Numbers ***************************************************/
+ NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
+ HardFault_IRQn = -13, /*!< 3 Cortex-M3 Hard Fault Interrupt */
+ MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */
+ BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */
+ UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */
+ SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */
+ DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */
+ PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */
+ SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */
+
+/****** STM32 specific Interrupt Numbers *********************************************************/
+ WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
+ PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */
+ TAMPER_IRQn = 2, /*!< Tamper Interrupt */
+ RTC_IRQn = 3, /*!< RTC global Interrupt */
+ FLASH_IRQn = 4, /*!< FLASH global Interrupt */
+ RCC_IRQn = 5, /*!< RCC global Interrupt */
+ EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */
+ EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */
+ EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */
+ EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */
+ EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */
+ DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 global Interrupt */
+ DMA1_Channel2_IRQn = 12, /*!< DMA1 Channel 2 global Interrupt */
+ DMA1_Channel3_IRQn = 13, /*!< DMA1 Channel 3 global Interrupt */
+ DMA1_Channel4_IRQn = 14, /*!< DMA1 Channel 4 global Interrupt */
+ DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 global Interrupt */
+ DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 global Interrupt */
+ DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 global Interrupt */
+ ADC1_IRQn = 18, /*!< ADC1 global Interrupt */
+ EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
+ TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
+ TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
+ TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
+ I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
+ I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
+ I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
+ I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
+ SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
+ SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
+ USART1_IRQn = 37, /*!< USART1 global Interrupt */
+ USART2_IRQn = 38, /*!< USART2 global Interrupt */
+ USART3_IRQn = 39, /*!< USART3 global Interrupt */
+ EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
+ RTC_Alarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */
+} IRQn_Type;
+
+
+/**
+ * @}
+ */
+
+#include "core_cm3.h"
+#include "system_stm32f1xx.h"
+#include <stdint.h>
+
+/** @addtogroup Peripheral_registers_structures
+ * @{
+ */
+
+/**
+ * @brief Analog to Digital Converter
+ */
+
+typedef struct
+{
+ __IO uint32_t SR;
+ __IO uint32_t CR1;
+ __IO uint32_t CR2;
+ __IO uint32_t SMPR1;
+ __IO uint32_t SMPR2;
+ __IO uint32_t JOFR1;
+ __IO uint32_t JOFR2;
+ __IO uint32_t JOFR3;
+ __IO uint32_t JOFR4;
+ __IO uint32_t HTR;
+ __IO uint32_t LTR;
+ __IO uint32_t SQR1;
+ __IO uint32_t SQR2;
+ __IO uint32_t SQR3;
+ __IO uint32_t JSQR;
+ __IO uint32_t JDR1;
+ __IO uint32_t JDR2;
+ __IO uint32_t JDR3;
+ __IO uint32_t JDR4;
+ __IO uint32_t DR;
+} ADC_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t SR; /*!< ADC status register, used for ADC multimode (bits common to several ADC instances). Address offset: ADC1 base address */
+ __IO uint32_t CR1; /*!< ADC control register 1, used for ADC multimode (bits common to several ADC instances). Address offset: ADC1 base address + 0x04 */
+ __IO uint32_t CR2; /*!< ADC control register 2, used for ADC multimode (bits common to several ADC instances). Address offset: ADC1 base address + 0x08 */
+ uint32_t RESERVED[16];
+ __IO uint32_t DR; /*!< ADC data register, used for ADC multimode (bits common to several ADC instances). Address offset: ADC1 base address + 0x4C */
+} ADC_Common_TypeDef;
+
+/**
+ * @brief Backup Registers
+ */
+
+typedef struct
+{
+ uint32_t RESERVED0;
+ __IO uint32_t DR1;
+ __IO uint32_t DR2;
+ __IO uint32_t DR3;
+ __IO uint32_t DR4;
+ __IO uint32_t DR5;
+ __IO uint32_t DR6;
+ __IO uint32_t DR7;
+ __IO uint32_t DR8;
+ __IO uint32_t DR9;
+ __IO uint32_t DR10;
+ __IO uint32_t RTCCR;
+ __IO uint32_t CR;
+ __IO uint32_t CSR;
+} BKP_TypeDef;
+
+
+/**
+ * @brief CRC calculation unit
+ */
+
+typedef struct
+{
+ __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
+ __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
+ uint8_t RESERVED0; /*!< Reserved, Address offset: 0x05 */
+ uint16_t RESERVED1; /*!< Reserved, Address offset: 0x06 */
+ __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
+} CRC_TypeDef;
+
+
+/**
+ * @brief Debug MCU
+ */
+
+typedef struct
+{
+ __IO uint32_t IDCODE;
+ __IO uint32_t CR;
+}DBGMCU_TypeDef;
+
+/**
+ * @brief DMA Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t CCR;
+ __IO uint32_t CNDTR;
+ __IO uint32_t CPAR;
+ __IO uint32_t CMAR;
+} DMA_Channel_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t ISR;
+ __IO uint32_t IFCR;
+} DMA_TypeDef;
+
+
+
+/**
+ * @brief External Interrupt/Event Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t IMR;
+ __IO uint32_t EMR;
+ __IO uint32_t RTSR;
+ __IO uint32_t FTSR;
+ __IO uint32_t SWIER;
+ __IO uint32_t PR;
+} EXTI_TypeDef;
+
+/**
+ * @brief FLASH Registers
+ */
+
+typedef struct
+{
+ __IO uint32_t ACR;
+ __IO uint32_t KEYR;
+ __IO uint32_t OPTKEYR;
+ __IO uint32_t SR;
+ __IO uint32_t CR;
+ __IO uint32_t AR;
+ __IO uint32_t RESERVED;
+ __IO uint32_t OBR;
+ __IO uint32_t WRPR;
+} FLASH_TypeDef;
+
+/**
+ * @brief Option Bytes Registers
+ */
+
+typedef struct
+{
+ __IO uint16_t RDP;
+ __IO uint16_t USER;
+ __IO uint16_t Data0;
+ __IO uint16_t Data1;
+ __IO uint16_t WRP0;
+ __IO uint16_t WRP1;
+ __IO uint16_t WRP2;
+ __IO uint16_t WRP3;
+} OB_TypeDef;
+
+/**
+ * @brief General Purpose I/O
+ */
+
+typedef struct
+{
+ __IO uint32_t CRL;
+ __IO uint32_t CRH;
+ __IO uint32_t IDR;
+ __IO uint32_t ODR;
+ __IO uint32_t BSRR;
+ __IO uint32_t BRR;
+ __IO uint32_t LCKR;
+} GPIO_TypeDef;
+
+/**
+ * @brief Alternate Function I/O
+ */
+
+typedef struct
+{
+ __IO uint32_t EVCR;
+ __IO uint32_t MAPR;
+ __IO uint32_t EXTICR[4];
+ uint32_t RESERVED0;
+ __IO uint32_t MAPR2;
+} AFIO_TypeDef;
+/**
+ * @brief Inter Integrated Circuit Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t CR1;
+ __IO uint32_t CR2;
+ __IO uint32_t OAR1;
+ __IO uint32_t OAR2;
+ __IO uint32_t DR;
+ __IO uint32_t SR1;
+ __IO uint32_t SR2;
+ __IO uint32_t CCR;
+ __IO uint32_t TRISE;
+} I2C_TypeDef;
+
+/**
+ * @brief Independent WATCHDOG
+ */
+
+typedef struct
+{
+ __IO uint32_t KR; /*!< Key register, Address offset: 0x00 */
+ __IO uint32_t PR; /*!< Prescaler register, Address offset: 0x04 */
+ __IO uint32_t RLR; /*!< Reload register, Address offset: 0x08 */
+ __IO uint32_t SR; /*!< Status register, Address offset: 0x0C */
+} IWDG_TypeDef;
+
+/**
+ * @brief Power Control
+ */
+
+typedef struct
+{
+ __IO uint32_t CR;
+ __IO uint32_t CSR;
+} PWR_TypeDef;
+
+/**
+ * @brief Reset and Clock Control
+ */
+
+typedef struct
+{
+ __IO uint32_t CR;
+ __IO uint32_t CFGR;
+ __IO uint32_t CIR;
+ __IO uint32_t APB2RSTR;
+ __IO uint32_t APB1RSTR;
+ __IO uint32_t AHBENR;
+ __IO uint32_t APB2ENR;
+ __IO uint32_t APB1ENR;
+ __IO uint32_t BDCR;
+ __IO uint32_t CSR;
+
+
+} RCC_TypeDef;
+
+/**
+ * @brief Real-Time Clock
+ */
+
+typedef struct
+{
+ __IO uint32_t CRH;
+ __IO uint32_t CRL;
+ __IO uint32_t PRLH;
+ __IO uint32_t PRLL;
+ __IO uint32_t DIVH;
+ __IO uint32_t DIVL;
+ __IO uint32_t CNTH;
+ __IO uint32_t CNTL;
+ __IO uint32_t ALRH;
+ __IO uint32_t ALRL;
+} RTC_TypeDef;
+
+/**
+ * @brief SD host Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t POWER;
+ __IO uint32_t CLKCR;
+ __IO uint32_t ARG;
+ __IO uint32_t CMD;
+ __I uint32_t RESPCMD;
+ __I uint32_t RESP1;
+ __I uint32_t RESP2;
+ __I uint32_t RESP3;
+ __I uint32_t RESP4;
+ __IO uint32_t DTIMER;
+ __IO uint32_t DLEN;
+ __IO uint32_t DCTRL;
+ __I uint32_t DCOUNT;
+ __I uint32_t STA;
+ __IO uint32_t ICR;
+ __IO uint32_t MASK;
+ uint32_t RESERVED0[2];
+ __I uint32_t FIFOCNT;
+ uint32_t RESERVED1[13];
+ __IO uint32_t FIFO;
+} SDIO_TypeDef;
+
+/**
+ * @brief Serial Peripheral Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t CR1;
+ __IO uint32_t CR2;
+ __IO uint32_t SR;
+ __IO uint32_t DR;
+ __IO uint32_t CRCPR;
+ __IO uint32_t RXCRCR;
+ __IO uint32_t TXCRCR;
+ __IO uint32_t I2SCFGR;
+} SPI_TypeDef;
+
+/**
+ * @brief TIM Timers
+ */
+typedef struct
+{
+ __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
+ __IO uint32_t SMCR; /*!< TIM slave Mode Control register, Address offset: 0x08 */
+ __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
+ __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
+ __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
+ __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
+ __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
+ __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
+ __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
+ __IO uint32_t PSC; /*!< TIM prescaler register, Address offset: 0x28 */
+ __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
+ __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */
+ __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
+ __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
+ __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
+ __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
+ __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
+ __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
+ __IO uint32_t DMAR; /*!< TIM DMA address for full transfer register, Address offset: 0x4C */
+ __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */
+}TIM_TypeDef;
+
+
+/**
+ * @brief Universal Synchronous Asynchronous Receiver Transmitter
+ */
+
+typedef struct
+{
+ __IO uint32_t SR; /*!< USART Status register, Address offset: 0x00 */
+ __IO uint32_t DR; /*!< USART Data register, Address offset: 0x04 */
+ __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x08 */
+ __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x0C */
+ __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x10 */
+ __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x14 */
+ __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x18 */
+} USART_TypeDef;
+
+
+
+/**
+ * @brief Window WATCHDOG
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
+ __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
+ __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
+} WWDG_TypeDef;
+
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_memory_map
+ * @{
+ */
+
+
+#define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH base address in the alias region */
+#define FLASH_BANK1_END ((uint32_t)0x0801FFFF) /*!< FLASH END address of bank1 */
+#define SRAM_BASE ((uint32_t)0x20000000) /*!< SRAM base address in the alias region */
+#define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */
+
+#define SRAM_BB_BASE ((uint32_t)0x22000000) /*!< SRAM base address in the bit-band region */
+#define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */
+
+
+/*!< Peripheral memory map */
+#define APB1PERIPH_BASE PERIPH_BASE
+#define APB2PERIPH_BASE (PERIPH_BASE + 0x10000)
+#define AHBPERIPH_BASE (PERIPH_BASE + 0x20000)
+
+#define TIM2_BASE (APB1PERIPH_BASE + 0x0000)
+#define TIM3_BASE (APB1PERIPH_BASE + 0x0400)
+#define TIM4_BASE (APB1PERIPH_BASE + 0x0800)
+#define RTC_BASE (APB1PERIPH_BASE + 0x2800)
+#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00)
+#define IWDG_BASE (APB1PERIPH_BASE + 0x3000)
+#define SPI2_BASE (APB1PERIPH_BASE + 0x3800)
+#define USART2_BASE (APB1PERIPH_BASE + 0x4400)
+#define USART3_BASE (APB1PERIPH_BASE + 0x4800)
+#define I2C1_BASE (APB1PERIPH_BASE + 0x5400)
+#define I2C2_BASE (APB1PERIPH_BASE + 0x5800)
+#define BKP_BASE (APB1PERIPH_BASE + 0x6C00)
+#define PWR_BASE (APB1PERIPH_BASE + 0x7000)
+#define AFIO_BASE (APB2PERIPH_BASE + 0x0000)
+#define EXTI_BASE (APB2PERIPH_BASE + 0x0400)
+#define GPIOA_BASE (APB2PERIPH_BASE + 0x0800)
+#define GPIOB_BASE (APB2PERIPH_BASE + 0x0C00)
+#define GPIOC_BASE (APB2PERIPH_BASE + 0x1000)
+#define GPIOD_BASE (APB2PERIPH_BASE + 0x1400)
+#define GPIOE_BASE (APB2PERIPH_BASE + 0x1800)
+#define ADC1_BASE (APB2PERIPH_BASE + 0x2400)
+#define SPI1_BASE (APB2PERIPH_BASE + 0x3000)
+#define USART1_BASE (APB2PERIPH_BASE + 0x3800)
+
+#define SDIO_BASE (PERIPH_BASE + 0x18000)
+
+#define DMA1_BASE (AHBPERIPH_BASE + 0x0000)
+#define DMA1_Channel1_BASE (AHBPERIPH_BASE + 0x0008)
+#define DMA1_Channel2_BASE (AHBPERIPH_BASE + 0x001C)
+#define DMA1_Channel3_BASE (AHBPERIPH_BASE + 0x0030)
+#define DMA1_Channel4_BASE (AHBPERIPH_BASE + 0x0044)
+#define DMA1_Channel5_BASE (AHBPERIPH_BASE + 0x0058)
+#define DMA1_Channel6_BASE (AHBPERIPH_BASE + 0x006C)
+#define DMA1_Channel7_BASE (AHBPERIPH_BASE + 0x0080)
+#define RCC_BASE (AHBPERIPH_BASE + 0x1000)
+#define CRC_BASE (AHBPERIPH_BASE + 0x3000)
+
+#define FLASH_R_BASE (AHBPERIPH_BASE + 0x2000) /*!< Flash registers base address */
+#define FLASHSIZE_BASE ((uint32_t)0x1FFFF7E0) /*!< FLASH Size register base address */
+#define UID_BASE ((uint32_t)0x1FFFF7E8) /*!< Unique device ID register base address */
+#define OB_BASE ((uint32_t)0x1FFFF800) /*!< Flash Option Bytes base address */
+
+
+
+#define DBGMCU_BASE ((uint32_t)0xE0042000) /*!< Debug MCU registers base address */
+
+
+
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_declaration
+ * @{
+ */
+
+#define TIM2 ((TIM_TypeDef *) TIM2_BASE)
+#define TIM3 ((TIM_TypeDef *) TIM3_BASE)
+#define TIM4 ((TIM_TypeDef *) TIM4_BASE)
+#define RTC ((RTC_TypeDef *) RTC_BASE)
+#define WWDG ((WWDG_TypeDef *) WWDG_BASE)
+#define IWDG ((IWDG_TypeDef *) IWDG_BASE)
+#define SPI2 ((SPI_TypeDef *) SPI2_BASE)
+#define USART2 ((USART_TypeDef *) USART2_BASE)
+#define USART3 ((USART_TypeDef *) USART3_BASE)
+#define I2C1 ((I2C_TypeDef *) I2C1_BASE)
+#define I2C2 ((I2C_TypeDef *) I2C2_BASE)
+#define BKP ((BKP_TypeDef *) BKP_BASE)
+#define PWR ((PWR_TypeDef *) PWR_BASE)
+#define AFIO ((AFIO_TypeDef *) AFIO_BASE)
+#define EXTI ((EXTI_TypeDef *) EXTI_BASE)
+#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
+#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
+#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
+#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
+#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
+#define ADC1 ((ADC_TypeDef *) ADC1_BASE)
+#define ADC1_COMMON ((ADC_Common_TypeDef *) ADC1_BASE)
+#define SPI1 ((SPI_TypeDef *) SPI1_BASE)
+#define USART1 ((USART_TypeDef *) USART1_BASE)
+#define SDIO ((SDIO_TypeDef *) SDIO_BASE)
+#define DMA1 ((DMA_TypeDef *) DMA1_BASE)
+#define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
+#define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
+#define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
+#define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
+#define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
+#define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
+#define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
+#define RCC ((RCC_TypeDef *) RCC_BASE)
+#define CRC ((CRC_TypeDef *) CRC_BASE)
+#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
+#define OB ((OB_TypeDef *) OB_BASE)
+#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
+
+
+/**
+ * @}
+ */
+
+/** @addtogroup Exported_constants
+ * @{
+ */
+
+ /** @addtogroup Peripheral_Registers_Bits_Definition
+ * @{
+ */
+
+/******************************************************************************/
+/* Peripheral Registers_Bits_Definition */
+/******************************************************************************/
+
+/******************************************************************************/
+/* */
+/* CRC calculation unit (CRC) */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for CRC_DR register *********************/
+#define CRC_DR_DR_Pos (0U)
+#define CRC_DR_DR_Msk (0xFFFFFFFFU << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */
+#define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */
+
+/******************* Bit definition for CRC_IDR register ********************/
+#define CRC_IDR_IDR_Pos (0U)
+#define CRC_IDR_IDR_Msk (0xFFU << CRC_IDR_IDR_Pos) /*!< 0x000000FF */
+#define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 8-bit data register bits */
+
+/******************** Bit definition for CRC_CR register ********************/
+#define CRC_CR_RESET_Pos (0U)
+#define CRC_CR_RESET_Msk (0x1U << CRC_CR_RESET_Pos) /*!< 0x00000001 */
+#define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET bit */
+
+/******************************************************************************/
+/* */
+/* Power Control */
+/* */
+/******************************************************************************/
+
+/******************** Bit definition for PWR_CR register ********************/
+#define PWR_CR_LPDS_Pos (0U)
+#define PWR_CR_LPDS_Msk (0x1U << PWR_CR_LPDS_Pos) /*!< 0x00000001 */
+#define PWR_CR_LPDS PWR_CR_LPDS_Msk /*!< Low-Power Deepsleep */
+#define PWR_CR_PDDS_Pos (1U)
+#define PWR_CR_PDDS_Msk (0x1U << PWR_CR_PDDS_Pos) /*!< 0x00000002 */
+#define PWR_CR_PDDS PWR_CR_PDDS_Msk /*!< Power Down Deepsleep */
+#define PWR_CR_CWUF_Pos (2U)
+#define PWR_CR_CWUF_Msk (0x1U << PWR_CR_CWUF_Pos) /*!< 0x00000004 */
+#define PWR_CR_CWUF PWR_CR_CWUF_Msk /*!< Clear Wakeup Flag */
+#define PWR_CR_CSBF_Pos (3U)
+#define PWR_CR_CSBF_Msk (0x1U << PWR_CR_CSBF_Pos) /*!< 0x00000008 */
+#define PWR_CR_CSBF PWR_CR_CSBF_Msk /*!< Clear Standby Flag */
+#define PWR_CR_PVDE_Pos (4U)
+#define PWR_CR_PVDE_Msk (0x1U << PWR_CR_PVDE_Pos) /*!< 0x00000010 */
+#define PWR_CR_PVDE PWR_CR_PVDE_Msk /*!< Power Voltage Detector Enable */
+
+#define PWR_CR_PLS_Pos (5U)
+#define PWR_CR_PLS_Msk (0x7U << PWR_CR_PLS_Pos) /*!< 0x000000E0 */
+#define PWR_CR_PLS PWR_CR_PLS_Msk /*!< PLS[2:0] bits (PVD Level Selection) */
+#define PWR_CR_PLS_0 (0x1U << PWR_CR_PLS_Pos) /*!< 0x00000020 */
+#define PWR_CR_PLS_1 (0x2U << PWR_CR_PLS_Pos) /*!< 0x00000040 */
+#define PWR_CR_PLS_2 (0x4U << PWR_CR_PLS_Pos) /*!< 0x00000080 */
+
+/*!< PVD level configuration */
+#define PWR_CR_PLS_2V2 ((uint32_t)0x00000000) /*!< PVD level 2.2V */
+#define PWR_CR_PLS_2V3 ((uint32_t)0x00000020) /*!< PVD level 2.3V */
+#define PWR_CR_PLS_2V4 ((uint32_t)0x00000040) /*!< PVD level 2.4V */
+#define PWR_CR_PLS_2V5 ((uint32_t)0x00000060) /*!< PVD level 2.5V */
+#define PWR_CR_PLS_2V6 ((uint32_t)0x00000080) /*!< PVD level 2.6V */
+#define PWR_CR_PLS_2V7 ((uint32_t)0x000000A0) /*!< PVD level 2.7V */
+#define PWR_CR_PLS_2V8 ((uint32_t)0x000000C0) /*!< PVD level 2.8V */
+#define PWR_CR_PLS_2V9 ((uint32_t)0x000000E0) /*!< PVD level 2.9V */
+
+#define PWR_CR_DBP_Pos (8U)
+#define PWR_CR_DBP_Msk (0x1U << PWR_CR_DBP_Pos) /*!< 0x00000100 */
+#define PWR_CR_DBP PWR_CR_DBP_Msk /*!< Disable Backup Domain write protection */
+
+
+/******************* Bit definition for PWR_CSR register ********************/
+#define PWR_CSR_WUF_Pos (0U)
+#define PWR_CSR_WUF_Msk (0x1U << PWR_CSR_WUF_Pos) /*!< 0x00000001 */
+#define PWR_CSR_WUF PWR_CSR_WUF_Msk /*!< Wakeup Flag */
+#define PWR_CSR_SBF_Pos (1U)
+#define PWR_CSR_SBF_Msk (0x1U << PWR_CSR_SBF_Pos) /*!< 0x00000002 */
+#define PWR_CSR_SBF PWR_CSR_SBF_Msk /*!< Standby Flag */
+#define PWR_CSR_PVDO_Pos (2U)
+#define PWR_CSR_PVDO_Msk (0x1U << PWR_CSR_PVDO_Pos) /*!< 0x00000004 */
+#define PWR_CSR_PVDO PWR_CSR_PVDO_Msk /*!< PVD Output */
+#define PWR_CSR_EWUP_Pos (8U)
+#define PWR_CSR_EWUP_Msk (0x1U << PWR_CSR_EWUP_Pos) /*!< 0x00000100 */
+#define PWR_CSR_EWUP PWR_CSR_EWUP_Msk /*!< Enable WKUP pin */
+
+/******************************************************************************/
+/* */
+/* Backup registers */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for BKP_DR1 register ********************/
+#define BKP_DR1_D_Pos (0U)
+#define BKP_DR1_D_Msk (0xFFFFU << BKP_DR1_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR1_D BKP_DR1_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR2 register ********************/
+#define BKP_DR2_D_Pos (0U)
+#define BKP_DR2_D_Msk (0xFFFFU << BKP_DR2_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR2_D BKP_DR2_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR3 register ********************/
+#define BKP_DR3_D_Pos (0U)
+#define BKP_DR3_D_Msk (0xFFFFU << BKP_DR3_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR3_D BKP_DR3_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR4 register ********************/
+#define BKP_DR4_D_Pos (0U)
+#define BKP_DR4_D_Msk (0xFFFFU << BKP_DR4_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR4_D BKP_DR4_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR5 register ********************/
+#define BKP_DR5_D_Pos (0U)
+#define BKP_DR5_D_Msk (0xFFFFU << BKP_DR5_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR5_D BKP_DR5_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR6 register ********************/
+#define BKP_DR6_D_Pos (0U)
+#define BKP_DR6_D_Msk (0xFFFFU << BKP_DR6_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR6_D BKP_DR6_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR7 register ********************/
+#define BKP_DR7_D_Pos (0U)
+#define BKP_DR7_D_Msk (0xFFFFU << BKP_DR7_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR7_D BKP_DR7_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR8 register ********************/
+#define BKP_DR8_D_Pos (0U)
+#define BKP_DR8_D_Msk (0xFFFFU << BKP_DR8_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR8_D BKP_DR8_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR9 register ********************/
+#define BKP_DR9_D_Pos (0U)
+#define BKP_DR9_D_Msk (0xFFFFU << BKP_DR9_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR9_D BKP_DR9_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR10 register *******************/
+#define BKP_DR10_D_Pos (0U)
+#define BKP_DR10_D_Msk (0xFFFFU << BKP_DR10_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR10_D BKP_DR10_D_Msk /*!< Backup data */
+
+#define RTC_BKP_NUMBER 10
+
+/****************** Bit definition for BKP_RTCCR register *******************/
+#define BKP_RTCCR_CAL_Pos (0U)
+#define BKP_RTCCR_CAL_Msk (0x7FU << BKP_RTCCR_CAL_Pos) /*!< 0x0000007F */
+#define BKP_RTCCR_CAL BKP_RTCCR_CAL_Msk /*!< Calibration value */
+#define BKP_RTCCR_CCO_Pos (7U)
+#define BKP_RTCCR_CCO_Msk (0x1U << BKP_RTCCR_CCO_Pos) /*!< 0x00000080 */
+#define BKP_RTCCR_CCO BKP_RTCCR_CCO_Msk /*!< Calibration Clock Output */
+#define BKP_RTCCR_ASOE_Pos (8U)
+#define BKP_RTCCR_ASOE_Msk (0x1U << BKP_RTCCR_ASOE_Pos) /*!< 0x00000100 */
+#define BKP_RTCCR_ASOE BKP_RTCCR_ASOE_Msk /*!< Alarm or Second Output Enable */
+#define BKP_RTCCR_ASOS_Pos (9U)
+#define BKP_RTCCR_ASOS_Msk (0x1U << BKP_RTCCR_ASOS_Pos) /*!< 0x00000200 */
+#define BKP_RTCCR_ASOS BKP_RTCCR_ASOS_Msk /*!< Alarm or Second Output Selection */
+
+/******************** Bit definition for BKP_CR register ********************/
+#define BKP_CR_TPE_Pos (0U)
+#define BKP_CR_TPE_Msk (0x1U << BKP_CR_TPE_Pos) /*!< 0x00000001 */
+#define BKP_CR_TPE BKP_CR_TPE_Msk /*!< TAMPER pin enable */
+#define BKP_CR_TPAL_Pos (1U)
+#define BKP_CR_TPAL_Msk (0x1U << BKP_CR_TPAL_Pos) /*!< 0x00000002 */
+#define BKP_CR_TPAL BKP_CR_TPAL_Msk /*!< TAMPER pin active level */
+
+/******************* Bit definition for BKP_CSR register ********************/
+#define BKP_CSR_CTE_Pos (0U)
+#define BKP_CSR_CTE_Msk (0x1U << BKP_CSR_CTE_Pos) /*!< 0x00000001 */
+#define BKP_CSR_CTE BKP_CSR_CTE_Msk /*!< Clear Tamper event */
+#define BKP_CSR_CTI_Pos (1U)
+#define BKP_CSR_CTI_Msk (0x1U << BKP_CSR_CTI_Pos) /*!< 0x00000002 */
+#define BKP_CSR_CTI BKP_CSR_CTI_Msk /*!< Clear Tamper Interrupt */
+#define BKP_CSR_TPIE_Pos (2U)
+#define BKP_CSR_TPIE_Msk (0x1U << BKP_CSR_TPIE_Pos) /*!< 0x00000004 */
+#define BKP_CSR_TPIE BKP_CSR_TPIE_Msk /*!< TAMPER Pin interrupt enable */
+#define BKP_CSR_TEF_Pos (8U)
+#define BKP_CSR_TEF_Msk (0x1U << BKP_CSR_TEF_Pos) /*!< 0x00000100 */
+#define BKP_CSR_TEF BKP_CSR_TEF_Msk /*!< Tamper Event Flag */
+#define BKP_CSR_TIF_Pos (9U)
+#define BKP_CSR_TIF_Msk (0x1U << BKP_CSR_TIF_Pos) /*!< 0x00000200 */
+#define BKP_CSR_TIF BKP_CSR_TIF_Msk /*!< Tamper Interrupt Flag */
+
+/******************************************************************************/
+/* */
+/* Reset and Clock Control */
+/* */
+/******************************************************************************/
+
+/******************** Bit definition for RCC_CR register ********************/
+#define RCC_CR_HSION_Pos (0U)
+#define RCC_CR_HSION_Msk (0x1U << RCC_CR_HSION_Pos) /*!< 0x00000001 */
+#define RCC_CR_HSION RCC_CR_HSION_Msk /*!< Internal High Speed clock enable */
+#define RCC_CR_HSIRDY_Pos (1U)
+#define RCC_CR_HSIRDY_Msk (0x1U << RCC_CR_HSIRDY_Pos) /*!< 0x00000002 */
+#define RCC_CR_HSIRDY RCC_CR_HSIRDY_Msk /*!< Internal High Speed clock ready flag */
+#define RCC_CR_HSITRIM_Pos (3U)
+#define RCC_CR_HSITRIM_Msk (0x1FU << RCC_CR_HSITRIM_Pos) /*!< 0x000000F8 */
+#define RCC_CR_HSITRIM RCC_CR_HSITRIM_Msk /*!< Internal High Speed clock trimming */
+#define RCC_CR_HSICAL_Pos (8U)
+#define RCC_CR_HSICAL_Msk (0xFFU << RCC_CR_HSICAL_Pos) /*!< 0x0000FF00 */
+#define RCC_CR_HSICAL RCC_CR_HSICAL_Msk /*!< Internal High Speed clock Calibration */
+#define RCC_CR_HSEON_Pos (16U)
+#define RCC_CR_HSEON_Msk (0x1U << RCC_CR_HSEON_Pos) /*!< 0x00010000 */
+#define RCC_CR_HSEON RCC_CR_HSEON_Msk /*!< External High Speed clock enable */
+#define RCC_CR_HSERDY_Pos (17U)
+#define RCC_CR_HSERDY_Msk (0x1U << RCC_CR_HSERDY_Pos) /*!< 0x00020000 */
+#define RCC_CR_HSERDY RCC_CR_HSERDY_Msk /*!< External High Speed clock ready flag */
+#define RCC_CR_HSEBYP_Pos (18U)
+#define RCC_CR_HSEBYP_Msk (0x1U << RCC_CR_HSEBYP_Pos) /*!< 0x00040000 */
+#define RCC_CR_HSEBYP RCC_CR_HSEBYP_Msk /*!< External High Speed clock Bypass */
+#define RCC_CR_CSSON_Pos (19U)
+#define RCC_CR_CSSON_Msk (0x1U << RCC_CR_CSSON_Pos) /*!< 0x00080000 */
+#define RCC_CR_CSSON RCC_CR_CSSON_Msk /*!< Clock Security System enable */
+#define RCC_CR_PLLON_Pos (24U)
+#define RCC_CR_PLLON_Msk (0x1U << RCC_CR_PLLON_Pos) /*!< 0x01000000 */
+#define RCC_CR_PLLON RCC_CR_PLLON_Msk /*!< PLL enable */
+#define RCC_CR_PLLRDY_Pos (25U)
+#define RCC_CR_PLLRDY_Msk (0x1U << RCC_CR_PLLRDY_Pos) /*!< 0x02000000 */
+#define RCC_CR_PLLRDY RCC_CR_PLLRDY_Msk /*!< PLL clock ready flag */
+
+
+/******************* Bit definition for RCC_CFGR register *******************/
+/*!< SW configuration */
+#define RCC_CFGR_SW_Pos (0U)
+#define RCC_CFGR_SW_Msk (0x3U << RCC_CFGR_SW_Pos) /*!< 0x00000003 */
+#define RCC_CFGR_SW RCC_CFGR_SW_Msk /*!< SW[1:0] bits (System clock Switch) */
+#define RCC_CFGR_SW_0 (0x1U << RCC_CFGR_SW_Pos) /*!< 0x00000001 */
+#define RCC_CFGR_SW_1 (0x2U << RCC_CFGR_SW_Pos) /*!< 0x00000002 */
+
+#define RCC_CFGR_SW_HSI ((uint32_t)0x00000000) /*!< HSI selected as system clock */
+#define RCC_CFGR_SW_HSE ((uint32_t)0x00000001) /*!< HSE selected as system clock */
+#define RCC_CFGR_SW_PLL ((uint32_t)0x00000002) /*!< PLL selected as system clock */
+
+/*!< SWS configuration */
+#define RCC_CFGR_SWS_Pos (2U)
+#define RCC_CFGR_SWS_Msk (0x3U << RCC_CFGR_SWS_Pos) /*!< 0x0000000C */
+#define RCC_CFGR_SWS RCC_CFGR_SWS_Msk /*!< SWS[1:0] bits (System Clock Switch Status) */
+#define RCC_CFGR_SWS_0 (0x1U << RCC_CFGR_SWS_Pos) /*!< 0x00000004 */
+#define RCC_CFGR_SWS_1 (0x2U << RCC_CFGR_SWS_Pos) /*!< 0x00000008 */
+
+#define RCC_CFGR_SWS_HSI ((uint32_t)0x00000000) /*!< HSI oscillator used as system clock */
+#define RCC_CFGR_SWS_HSE ((uint32_t)0x00000004) /*!< HSE oscillator used as system clock */
+#define RCC_CFGR_SWS_PLL ((uint32_t)0x00000008) /*!< PLL used as system clock */
+
+/*!< HPRE configuration */
+#define RCC_CFGR_HPRE_Pos (4U)
+#define RCC_CFGR_HPRE_Msk (0xFU << RCC_CFGR_HPRE_Pos) /*!< 0x000000F0 */
+#define RCC_CFGR_HPRE RCC_CFGR_HPRE_Msk /*!< HPRE[3:0] bits (AHB prescaler) */
+#define RCC_CFGR_HPRE_0 (0x1U << RCC_CFGR_HPRE_Pos) /*!< 0x00000010 */
+#define RCC_CFGR_HPRE_1 (0x2U << RCC_CFGR_HPRE_Pos) /*!< 0x00000020 */
+#define RCC_CFGR_HPRE_2 (0x4U << RCC_CFGR_HPRE_Pos) /*!< 0x00000040 */
+#define RCC_CFGR_HPRE_3 (0x8U << RCC_CFGR_HPRE_Pos) /*!< 0x00000080 */
+
+#define RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000) /*!< SYSCLK not divided */
+#define RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080) /*!< SYSCLK divided by 2 */
+#define RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090) /*!< SYSCLK divided by 4 */
+#define RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0) /*!< SYSCLK divided by 8 */
+#define RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0) /*!< SYSCLK divided by 16 */
+#define RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0) /*!< SYSCLK divided by 64 */
+#define RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0) /*!< SYSCLK divided by 128 */
+#define RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0) /*!< SYSCLK divided by 256 */
+#define RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0) /*!< SYSCLK divided by 512 */
+
+/*!< PPRE1 configuration */
+#define RCC_CFGR_PPRE1_Pos (8U)
+#define RCC_CFGR_PPRE1_Msk (0x7U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000700 */
+#define RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_Msk /*!< PRE1[2:0] bits (APB1 prescaler) */
+#define RCC_CFGR_PPRE1_0 (0x1U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000100 */
+#define RCC_CFGR_PPRE1_1 (0x2U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000200 */
+#define RCC_CFGR_PPRE1_2 (0x4U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000400 */
+
+#define RCC_CFGR_PPRE1_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */
+#define RCC_CFGR_PPRE1_DIV2 ((uint32_t)0x00000400) /*!< HCLK divided by 2 */
+#define RCC_CFGR_PPRE1_DIV4 ((uint32_t)0x00000500) /*!< HCLK divided by 4 */
+#define RCC_CFGR_PPRE1_DIV8 ((uint32_t)0x00000600) /*!< HCLK divided by 8 */
+#define RCC_CFGR_PPRE1_DIV16 ((uint32_t)0x00000700) /*!< HCLK divided by 16 */
+
+/*!< PPRE2 configuration */
+#define RCC_CFGR_PPRE2_Pos (11U)
+#define RCC_CFGR_PPRE2_Msk (0x7U << RCC_CFGR_PPRE2_Pos) /*!< 0x00003800 */
+#define RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_Msk /*!< PRE2[2:0] bits (APB2 prescaler) */
+#define RCC_CFGR_PPRE2_0 (0x1U << RCC_CFGR_PPRE2_Pos) /*!< 0x00000800 */
+#define RCC_CFGR_PPRE2_1 (0x2U << RCC_CFGR_PPRE2_Pos) /*!< 0x00001000 */
+#define RCC_CFGR_PPRE2_2 (0x4U << RCC_CFGR_PPRE2_Pos) /*!< 0x00002000 */
+
+#define RCC_CFGR_PPRE2_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */
+#define RCC_CFGR_PPRE2_DIV2 ((uint32_t)0x00002000) /*!< HCLK divided by 2 */
+#define RCC_CFGR_PPRE2_DIV4 ((uint32_t)0x00002800) /*!< HCLK divided by 4 */
+#define RCC_CFGR_PPRE2_DIV8 ((uint32_t)0x00003000) /*!< HCLK divided by 8 */
+#define RCC_CFGR_PPRE2_DIV16 ((uint32_t)0x00003800) /*!< HCLK divided by 16 */
+
+/*!< ADCPPRE configuration */
+#define RCC_CFGR_ADCPRE_Pos (14U)
+#define RCC_CFGR_ADCPRE_Msk (0x3U << RCC_CFGR_ADCPRE_Pos) /*!< 0x0000C000 */
+#define RCC_CFGR_ADCPRE RCC_CFGR_ADCPRE_Msk /*!< ADCPRE[1:0] bits (ADC prescaler) */
+#define RCC_CFGR_ADCPRE_0 (0x1U << RCC_CFGR_ADCPRE_Pos) /*!< 0x00004000 */
+#define RCC_CFGR_ADCPRE_1 (0x2U << RCC_CFGR_ADCPRE_Pos) /*!< 0x00008000 */
+
+#define RCC_CFGR_ADCPRE_DIV2 ((uint32_t)0x00000000) /*!< PCLK2 divided by 2 */
+#define RCC_CFGR_ADCPRE_DIV4 ((uint32_t)0x00004000) /*!< PCLK2 divided by 4 */
+#define RCC_CFGR_ADCPRE_DIV6 ((uint32_t)0x00008000) /*!< PCLK2 divided by 6 */
+#define RCC_CFGR_ADCPRE_DIV8 ((uint32_t)0x0000C000) /*!< PCLK2 divided by 8 */
+
+#define RCC_CFGR_PLLSRC_Pos (16U)
+#define RCC_CFGR_PLLSRC_Msk (0x1U << RCC_CFGR_PLLSRC_Pos) /*!< 0x00010000 */
+#define RCC_CFGR_PLLSRC RCC_CFGR_PLLSRC_Msk /*!< PLL entry clock source */
+
+#define RCC_CFGR_PLLXTPRE_Pos (17U)
+#define RCC_CFGR_PLLXTPRE_Msk (0x1U << RCC_CFGR_PLLXTPRE_Pos) /*!< 0x00020000 */
+#define RCC_CFGR_PLLXTPRE RCC_CFGR_PLLXTPRE_Msk /*!< HSE divider for PLL entry */
+
+/*!< PLLMUL configuration */
+#define RCC_CFGR_PLLMULL_Pos (18U)
+#define RCC_CFGR_PLLMULL_Msk (0xFU << RCC_CFGR_PLLMULL_Pos) /*!< 0x003C0000 */
+#define RCC_CFGR_PLLMULL RCC_CFGR_PLLMULL_Msk /*!< PLLMUL[3:0] bits (PLL multiplication factor) */
+#define RCC_CFGR_PLLMULL_0 (0x1U << RCC_CFGR_PLLMULL_Pos) /*!< 0x00040000 */
+#define RCC_CFGR_PLLMULL_1 (0x2U << RCC_CFGR_PLLMULL_Pos) /*!< 0x00080000 */
+#define RCC_CFGR_PLLMULL_2 (0x4U << RCC_CFGR_PLLMULL_Pos) /*!< 0x00100000 */
+#define RCC_CFGR_PLLMULL_3 (0x8U << RCC_CFGR_PLLMULL_Pos) /*!< 0x00200000 */
+
+#define RCC_CFGR_PLLXTPRE_HSE ((uint32_t)0x00000000) /*!< HSE clock not divided for PLL entry */
+#define RCC_CFGR_PLLXTPRE_HSE_DIV2 ((uint32_t)0x00020000) /*!< HSE clock divided by 2 for PLL entry */
+
+#define RCC_CFGR_PLLMULL2 ((uint32_t)0x00000000) /*!< PLL input clock*2 */
+#define RCC_CFGR_PLLMULL3_Pos (18U)
+#define RCC_CFGR_PLLMULL3_Msk (0x1U << RCC_CFGR_PLLMULL3_Pos) /*!< 0x00040000 */
+#define RCC_CFGR_PLLMULL3 RCC_CFGR_PLLMULL3_Msk /*!< PLL input clock*3 */
+#define RCC_CFGR_PLLMULL4_Pos (19U)
+#define RCC_CFGR_PLLMULL4_Msk (0x1U << RCC_CFGR_PLLMULL4_Pos) /*!< 0x00080000 */
+#define RCC_CFGR_PLLMULL4 RCC_CFGR_PLLMULL4_Msk /*!< PLL input clock*4 */
+#define RCC_CFGR_PLLMULL5_Pos (18U)
+#define RCC_CFGR_PLLMULL5_Msk (0x3U << RCC_CFGR_PLLMULL5_Pos) /*!< 0x000C0000 */
+#define RCC_CFGR_PLLMULL5 RCC_CFGR_PLLMULL5_Msk /*!< PLL input clock*5 */
+#define RCC_CFGR_PLLMULL6_Pos (20U)
+#define RCC_CFGR_PLLMULL6_Msk (0x1U << RCC_CFGR_PLLMULL6_Pos) /*!< 0x00100000 */
+#define RCC_CFGR_PLLMULL6 RCC_CFGR_PLLMULL6_Msk /*!< PLL input clock*6 */
+#define RCC_CFGR_PLLMULL7_Pos (18U)
+#define RCC_CFGR_PLLMULL7_Msk (0x5U << RCC_CFGR_PLLMULL7_Pos) /*!< 0x00140000 */
+#define RCC_CFGR_PLLMULL7 RCC_CFGR_PLLMULL7_Msk /*!< PLL input clock*7 */
+#define RCC_CFGR_PLLMULL8_Pos (19U)
+#define RCC_CFGR_PLLMULL8_Msk (0x3U << RCC_CFGR_PLLMULL8_Pos) /*!< 0x00180000 */
+#define RCC_CFGR_PLLMULL8 RCC_CFGR_PLLMULL8_Msk /*!< PLL input clock*8 */
+#define RCC_CFGR_PLLMULL9_Pos (18U)
+#define RCC_CFGR_PLLMULL9_Msk (0x7U << RCC_CFGR_PLLMULL9_Pos) /*!< 0x001C0000 */
+#define RCC_CFGR_PLLMULL9 RCC_CFGR_PLLMULL9_Msk /*!< PLL input clock*9 */
+#define RCC_CFGR_PLLMULL10_Pos (21U)
+#define RCC_CFGR_PLLMULL10_Msk (0x1U << RCC_CFGR_PLLMULL10_Pos) /*!< 0x00200000 */
+#define RCC_CFGR_PLLMULL10 RCC_CFGR_PLLMULL10_Msk /*!< PLL input clock10 */
+#define RCC_CFGR_PLLMULL11_Pos (18U)
+#define RCC_CFGR_PLLMULL11_Msk (0x9U << RCC_CFGR_PLLMULL11_Pos) /*!< 0x00240000 */
+#define RCC_CFGR_PLLMULL11 RCC_CFGR_PLLMULL11_Msk /*!< PLL input clock*11 */
+#define RCC_CFGR_PLLMULL12_Pos (19U)
+#define RCC_CFGR_PLLMULL12_Msk (0x5U << RCC_CFGR_PLLMULL12_Pos) /*!< 0x00280000 */
+#define RCC_CFGR_PLLMULL12 RCC_CFGR_PLLMULL12_Msk /*!< PLL input clock*12 */
+#define RCC_CFGR_PLLMULL13_Pos (18U)
+#define RCC_CFGR_PLLMULL13_Msk (0xBU << RCC_CFGR_PLLMULL13_Pos) /*!< 0x002C0000 */
+#define RCC_CFGR_PLLMULL13 RCC_CFGR_PLLMULL13_Msk /*!< PLL input clock*13 */
+#define RCC_CFGR_PLLMULL14_Pos (20U)
+#define RCC_CFGR_PLLMULL14_Msk (0x3U << RCC_CFGR_PLLMULL14_Pos) /*!< 0x00300000 */
+#define RCC_CFGR_PLLMULL14 RCC_CFGR_PLLMULL14_Msk /*!< PLL input clock*14 */
+#define RCC_CFGR_PLLMULL15_Pos (18U)
+#define RCC_CFGR_PLLMULL15_Msk (0xDU << RCC_CFGR_PLLMULL15_Pos) /*!< 0x00340000 */
+#define RCC_CFGR_PLLMULL15 RCC_CFGR_PLLMULL15_Msk /*!< PLL input clock*15 */
+#define RCC_CFGR_PLLMULL16_Pos (19U)
+#define RCC_CFGR_PLLMULL16_Msk (0x7U << RCC_CFGR_PLLMULL16_Pos) /*!< 0x00380000 */
+#define RCC_CFGR_PLLMULL16 RCC_CFGR_PLLMULL16_Msk /*!< PLL input clock*16 */
+
+/*!< MCO configuration */
+#define RCC_CFGR_MCO_Pos (24U)
+#define RCC_CFGR_MCO_Msk (0x7U << RCC_CFGR_MCO_Pos) /*!< 0x07000000 */
+#define RCC_CFGR_MCO RCC_CFGR_MCO_Msk /*!< MCO[2:0] bits (Microcontroller Clock Output) */
+#define RCC_CFGR_MCO_0 (0x1U << RCC_CFGR_MCO_Pos) /*!< 0x01000000 */
+#define RCC_CFGR_MCO_1 (0x2U << RCC_CFGR_MCO_Pos) /*!< 0x02000000 */
+#define RCC_CFGR_MCO_2 (0x4U << RCC_CFGR_MCO_Pos) /*!< 0x04000000 */
+
+#define RCC_CFGR_MCO_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */
+#define RCC_CFGR_MCO_SYSCLK ((uint32_t)0x04000000) /*!< System clock selected as MCO source */
+#define RCC_CFGR_MCO_HSI ((uint32_t)0x05000000) /*!< HSI clock selected as MCO source */
+#define RCC_CFGR_MCO_HSE ((uint32_t)0x06000000) /*!< HSE clock selected as MCO source */
+#define RCC_CFGR_MCO_PLLCLK_DIV2 ((uint32_t)0x07000000) /*!< PLL clock divided by 2 selected as MCO source */
+
+ /* Reference defines */
+ #define RCC_CFGR_MCOSEL RCC_CFGR_MCO
+ #define RCC_CFGR_MCOSEL_0 RCC_CFGR_MCO_0
+ #define RCC_CFGR_MCOSEL_1 RCC_CFGR_MCO_1
+ #define RCC_CFGR_MCOSEL_2 RCC_CFGR_MCO_2
+ #define RCC_CFGR_MCOSEL_NOCLOCK RCC_CFGR_MCO_NOCLOCK
+ #define RCC_CFGR_MCOSEL_SYSCLK RCC_CFGR_MCO_SYSCLK
+ #define RCC_CFGR_MCOSEL_HSI RCC_CFGR_MCO_HSI
+ #define RCC_CFGR_MCOSEL_HSE RCC_CFGR_MCO_HSE
+ #define RCC_CFGR_MCOSEL_PLL_DIV2 RCC_CFGR_MCO_PLLCLK_DIV2
+
+/*!<****************** Bit definition for RCC_CIR register ********************/
+#define RCC_CIR_LSIRDYF_Pos (0U)
+#define RCC_CIR_LSIRDYF_Msk (0x1U << RCC_CIR_LSIRDYF_Pos) /*!< 0x00000001 */
+#define RCC_CIR_LSIRDYF RCC_CIR_LSIRDYF_Msk /*!< LSI Ready Interrupt flag */
+#define RCC_CIR_LSERDYF_Pos (1U)
+#define RCC_CIR_LSERDYF_Msk (0x1U << RCC_CIR_LSERDYF_Pos) /*!< 0x00000002 */
+#define RCC_CIR_LSERDYF RCC_CIR_LSERDYF_Msk /*!< LSE Ready Interrupt flag */
+#define RCC_CIR_HSIRDYF_Pos (2U)
+#define RCC_CIR_HSIRDYF_Msk (0x1U << RCC_CIR_HSIRDYF_Pos) /*!< 0x00000004 */
+#define RCC_CIR_HSIRDYF RCC_CIR_HSIRDYF_Msk /*!< HSI Ready Interrupt flag */
+#define RCC_CIR_HSERDYF_Pos (3U)
+#define RCC_CIR_HSERDYF_Msk (0x1U << RCC_CIR_HSERDYF_Pos) /*!< 0x00000008 */
+#define RCC_CIR_HSERDYF RCC_CIR_HSERDYF_Msk /*!< HSE Ready Interrupt flag */
+#define RCC_CIR_PLLRDYF_Pos (4U)
+#define RCC_CIR_PLLRDYF_Msk (0x1U << RCC_CIR_PLLRDYF_Pos) /*!< 0x00000010 */
+#define RCC_CIR_PLLRDYF RCC_CIR_PLLRDYF_Msk /*!< PLL Ready Interrupt flag */
+#define RCC_CIR_CSSF_Pos (7U)
+#define RCC_CIR_CSSF_Msk (0x1U << RCC_CIR_CSSF_Pos) /*!< 0x00000080 */
+#define RCC_CIR_CSSF RCC_CIR_CSSF_Msk /*!< Clock Security System Interrupt flag */
+#define RCC_CIR_LSIRDYIE_Pos (8U)
+#define RCC_CIR_LSIRDYIE_Msk (0x1U << RCC_CIR_LSIRDYIE_Pos) /*!< 0x00000100 */
+#define RCC_CIR_LSIRDYIE RCC_CIR_LSIRDYIE_Msk /*!< LSI Ready Interrupt Enable */
+#define RCC_CIR_LSERDYIE_Pos (9U)
+#define RCC_CIR_LSERDYIE_Msk (0x1U << RCC_CIR_LSERDYIE_Pos) /*!< 0x00000200 */
+#define RCC_CIR_LSERDYIE RCC_CIR_LSERDYIE_Msk /*!< LSE Ready Interrupt Enable */
+#define RCC_CIR_HSIRDYIE_Pos (10U)
+#define RCC_CIR_HSIRDYIE_Msk (0x1U << RCC_CIR_HSIRDYIE_Pos) /*!< 0x00000400 */
+#define RCC_CIR_HSIRDYIE RCC_CIR_HSIRDYIE_Msk /*!< HSI Ready Interrupt Enable */
+#define RCC_CIR_HSERDYIE_Pos (11U)
+#define RCC_CIR_HSERDYIE_Msk (0x1U << RCC_CIR_HSERDYIE_Pos) /*!< 0x00000800 */
+#define RCC_CIR_HSERDYIE RCC_CIR_HSERDYIE_Msk /*!< HSE Ready Interrupt Enable */
+#define RCC_CIR_PLLRDYIE_Pos (12U)
+#define RCC_CIR_PLLRDYIE_Msk (0x1U << RCC_CIR_PLLRDYIE_Pos) /*!< 0x00001000 */
+#define RCC_CIR_PLLRDYIE RCC_CIR_PLLRDYIE_Msk /*!< PLL Ready Interrupt Enable */
+#define RCC_CIR_LSIRDYC_Pos (16U)
+#define RCC_CIR_LSIRDYC_Msk (0x1U << RCC_CIR_LSIRDYC_Pos) /*!< 0x00010000 */
+#define RCC_CIR_LSIRDYC RCC_CIR_LSIRDYC_Msk /*!< LSI Ready Interrupt Clear */
+#define RCC_CIR_LSERDYC_Pos (17U)
+#define RCC_CIR_LSERDYC_Msk (0x1U << RCC_CIR_LSERDYC_Pos) /*!< 0x00020000 */
+#define RCC_CIR_LSERDYC RCC_CIR_LSERDYC_Msk /*!< LSE Ready Interrupt Clear */
+#define RCC_CIR_HSIRDYC_Pos (18U)
+#define RCC_CIR_HSIRDYC_Msk (0x1U << RCC_CIR_HSIRDYC_Pos) /*!< 0x00040000 */
+#define RCC_CIR_HSIRDYC RCC_CIR_HSIRDYC_Msk /*!< HSI Ready Interrupt Clear */
+#define RCC_CIR_HSERDYC_Pos (19U)
+#define RCC_CIR_HSERDYC_Msk (0x1U << RCC_CIR_HSERDYC_Pos) /*!< 0x00080000 */
+#define RCC_CIR_HSERDYC RCC_CIR_HSERDYC_Msk /*!< HSE Ready Interrupt Clear */
+#define RCC_CIR_PLLRDYC_Pos (20U)
+#define RCC_CIR_PLLRDYC_Msk (0x1U << RCC_CIR_PLLRDYC_Pos) /*!< 0x00100000 */
+#define RCC_CIR_PLLRDYC RCC_CIR_PLLRDYC_Msk /*!< PLL Ready Interrupt Clear */
+#define RCC_CIR_CSSC_Pos (23U)
+#define RCC_CIR_CSSC_Msk (0x1U << RCC_CIR_CSSC_Pos) /*!< 0x00800000 */
+#define RCC_CIR_CSSC RCC_CIR_CSSC_Msk /*!< Clock Security System Interrupt Clear */
+
+
+/***************** Bit definition for RCC_APB2RSTR register *****************/
+#define RCC_APB2RSTR_AFIORST_Pos (0U)
+#define RCC_APB2RSTR_AFIORST_Msk (0x1U << RCC_APB2RSTR_AFIORST_Pos) /*!< 0x00000001 */
+#define RCC_APB2RSTR_AFIORST RCC_APB2RSTR_AFIORST_Msk /*!< Alternate Function I/O reset */
+#define RCC_APB2RSTR_IOPARST_Pos (2U)
+#define RCC_APB2RSTR_IOPARST_Msk (0x1U << RCC_APB2RSTR_IOPARST_Pos) /*!< 0x00000004 */
+#define RCC_APB2RSTR_IOPARST RCC_APB2RSTR_IOPARST_Msk /*!< I/O port A reset */
+#define RCC_APB2RSTR_IOPBRST_Pos (3U)
+#define RCC_APB2RSTR_IOPBRST_Msk (0x1U << RCC_APB2RSTR_IOPBRST_Pos) /*!< 0x00000008 */
+#define RCC_APB2RSTR_IOPBRST RCC_APB2RSTR_IOPBRST_Msk /*!< I/O port B reset */
+#define RCC_APB2RSTR_IOPCRST_Pos (4U)
+#define RCC_APB2RSTR_IOPCRST_Msk (0x1U << RCC_APB2RSTR_IOPCRST_Pos) /*!< 0x00000010 */
+#define RCC_APB2RSTR_IOPCRST RCC_APB2RSTR_IOPCRST_Msk /*!< I/O port C reset */
+#define RCC_APB2RSTR_IOPDRST_Pos (5U)
+#define RCC_APB2RSTR_IOPDRST_Msk (0x1U << RCC_APB2RSTR_IOPDRST_Pos) /*!< 0x00000020 */
+#define RCC_APB2RSTR_IOPDRST RCC_APB2RSTR_IOPDRST_Msk /*!< I/O port D reset */
+#define RCC_APB2RSTR_ADC1RST_Pos (9U)
+#define RCC_APB2RSTR_ADC1RST_Msk (0x1U << RCC_APB2RSTR_ADC1RST_Pos) /*!< 0x00000200 */
+#define RCC_APB2RSTR_ADC1RST RCC_APB2RSTR_ADC1RST_Msk /*!< ADC 1 interface reset */
+
+
+#define RCC_APB2RSTR_TIM1RST_Pos (11U)
+#define RCC_APB2RSTR_TIM1RST_Msk (0x1U << RCC_APB2RSTR_TIM1RST_Pos) /*!< 0x00000800 */
+#define RCC_APB2RSTR_TIM1RST RCC_APB2RSTR_TIM1RST_Msk /*!< TIM1 Timer reset */
+#define RCC_APB2RSTR_SPI1RST_Pos (12U)
+#define RCC_APB2RSTR_SPI1RST_Msk (0x1U << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */
+#define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk /*!< SPI 1 reset */
+#define RCC_APB2RSTR_USART1RST_Pos (14U)
+#define RCC_APB2RSTR_USART1RST_Msk (0x1U << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00004000 */
+#define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk /*!< USART1 reset */
+
+
+#define RCC_APB2RSTR_IOPERST_Pos (6U)
+#define RCC_APB2RSTR_IOPERST_Msk (0x1U << RCC_APB2RSTR_IOPERST_Pos) /*!< 0x00000040 */
+#define RCC_APB2RSTR_IOPERST RCC_APB2RSTR_IOPERST_Msk /*!< I/O port E reset */
+
+
+
+
+/***************** Bit definition for RCC_APB1RSTR register *****************/
+#define RCC_APB1RSTR_TIM2RST_Pos (0U)
+#define RCC_APB1RSTR_TIM2RST_Msk (0x1U << RCC_APB1RSTR_TIM2RST_Pos) /*!< 0x00000001 */
+#define RCC_APB1RSTR_TIM2RST RCC_APB1RSTR_TIM2RST_Msk /*!< Timer 2 reset */
+#define RCC_APB1RSTR_TIM3RST_Pos (1U)
+#define RCC_APB1RSTR_TIM3RST_Msk (0x1U << RCC_APB1RSTR_TIM3RST_Pos) /*!< 0x00000002 */
+#define RCC_APB1RSTR_TIM3RST RCC_APB1RSTR_TIM3RST_Msk /*!< Timer 3 reset */
+#define RCC_APB1RSTR_WWDGRST_Pos (11U)
+#define RCC_APB1RSTR_WWDGRST_Msk (0x1U << RCC_APB1RSTR_WWDGRST_Pos) /*!< 0x00000800 */
+#define RCC_APB1RSTR_WWDGRST RCC_APB1RSTR_WWDGRST_Msk /*!< Window Watchdog reset */
+#define RCC_APB1RSTR_USART2RST_Pos (17U)
+#define RCC_APB1RSTR_USART2RST_Msk (0x1U << RCC_APB1RSTR_USART2RST_Pos) /*!< 0x00020000 */
+#define RCC_APB1RSTR_USART2RST RCC_APB1RSTR_USART2RST_Msk /*!< USART 2 reset */
+#define RCC_APB1RSTR_I2C1RST_Pos (21U)
+#define RCC_APB1RSTR_I2C1RST_Msk (0x1U << RCC_APB1RSTR_I2C1RST_Pos) /*!< 0x00200000 */
+#define RCC_APB1RSTR_I2C1RST RCC_APB1RSTR_I2C1RST_Msk /*!< I2C 1 reset */
+
+
+#define RCC_APB1RSTR_BKPRST_Pos (27U)
+#define RCC_APB1RSTR_BKPRST_Msk (0x1U << RCC_APB1RSTR_BKPRST_Pos) /*!< 0x08000000 */
+#define RCC_APB1RSTR_BKPRST RCC_APB1RSTR_BKPRST_Msk /*!< Backup interface reset */
+#define RCC_APB1RSTR_PWRRST_Pos (28U)
+#define RCC_APB1RSTR_PWRRST_Msk (0x1U << RCC_APB1RSTR_PWRRST_Pos) /*!< 0x10000000 */
+#define RCC_APB1RSTR_PWRRST RCC_APB1RSTR_PWRRST_Msk /*!< Power interface reset */
+
+#define RCC_APB1RSTR_TIM4RST_Pos (2U)
+#define RCC_APB1RSTR_TIM4RST_Msk (0x1U << RCC_APB1RSTR_TIM4RST_Pos) /*!< 0x00000004 */
+#define RCC_APB1RSTR_TIM4RST RCC_APB1RSTR_TIM4RST_Msk /*!< Timer 4 reset */
+#define RCC_APB1RSTR_SPI2RST_Pos (14U)
+#define RCC_APB1RSTR_SPI2RST_Msk (0x1U << RCC_APB1RSTR_SPI2RST_Pos) /*!< 0x00004000 */
+#define RCC_APB1RSTR_SPI2RST RCC_APB1RSTR_SPI2RST_Msk /*!< SPI 2 reset */
+#define RCC_APB1RSTR_USART3RST_Pos (18U)
+#define RCC_APB1RSTR_USART3RST_Msk (0x1U << RCC_APB1RSTR_USART3RST_Pos) /*!< 0x00040000 */
+#define RCC_APB1RSTR_USART3RST RCC_APB1RSTR_USART3RST_Msk /*!< USART 3 reset */
+#define RCC_APB1RSTR_I2C2RST_Pos (22U)
+#define RCC_APB1RSTR_I2C2RST_Msk (0x1U << RCC_APB1RSTR_I2C2RST_Pos) /*!< 0x00400000 */
+#define RCC_APB1RSTR_I2C2RST RCC_APB1RSTR_I2C2RST_Msk /*!< I2C 2 reset */
+
+
+
+
+
+
+
+/****************** Bit definition for RCC_AHBENR register ******************/
+#define RCC_AHBENR_DMA1EN_Pos (0U)
+#define RCC_AHBENR_DMA1EN_Msk (0x1U << RCC_AHBENR_DMA1EN_Pos) /*!< 0x00000001 */
+#define RCC_AHBENR_DMA1EN RCC_AHBENR_DMA1EN_Msk /*!< DMA1 clock enable */
+#define RCC_AHBENR_SRAMEN_Pos (2U)
+#define RCC_AHBENR_SRAMEN_Msk (0x1U << RCC_AHBENR_SRAMEN_Pos) /*!< 0x00000004 */
+#define RCC_AHBENR_SRAMEN RCC_AHBENR_SRAMEN_Msk /*!< SRAM interface clock enable */
+#define RCC_AHBENR_FLITFEN_Pos (4U)
+#define RCC_AHBENR_FLITFEN_Msk (0x1U << RCC_AHBENR_FLITFEN_Pos) /*!< 0x00000010 */
+#define RCC_AHBENR_FLITFEN RCC_AHBENR_FLITFEN_Msk /*!< FLITF clock enable */
+#define RCC_AHBENR_CRCEN_Pos (6U)
+#define RCC_AHBENR_CRCEN_Msk (0x1U << RCC_AHBENR_CRCEN_Pos) /*!< 0x00000040 */
+#define RCC_AHBENR_CRCEN RCC_AHBENR_CRCEN_Msk /*!< CRC clock enable */
+
+
+
+
+/****************** Bit definition for RCC_APB2ENR register *****************/
+#define RCC_APB2ENR_AFIOEN_Pos (0U)
+#define RCC_APB2ENR_AFIOEN_Msk (0x1U << RCC_APB2ENR_AFIOEN_Pos) /*!< 0x00000001 */
+#define RCC_APB2ENR_AFIOEN RCC_APB2ENR_AFIOEN_Msk /*!< Alternate Function I/O clock enable */
+#define RCC_APB2ENR_IOPAEN_Pos (2U)
+#define RCC_APB2ENR_IOPAEN_Msk (0x1U << RCC_APB2ENR_IOPAEN_Pos) /*!< 0x00000004 */
+#define RCC_APB2ENR_IOPAEN RCC_APB2ENR_IOPAEN_Msk /*!< I/O port A clock enable */
+#define RCC_APB2ENR_IOPBEN_Pos (3U)
+#define RCC_APB2ENR_IOPBEN_Msk (0x1U << RCC_APB2ENR_IOPBEN_Pos) /*!< 0x00000008 */
+#define RCC_APB2ENR_IOPBEN RCC_APB2ENR_IOPBEN_Msk /*!< I/O port B clock enable */
+#define RCC_APB2ENR_IOPCEN_Pos (4U)
+#define RCC_APB2ENR_IOPCEN_Msk (0x1U << RCC_APB2ENR_IOPCEN_Pos) /*!< 0x00000010 */
+#define RCC_APB2ENR_IOPCEN RCC_APB2ENR_IOPCEN_Msk /*!< I/O port C clock enable */
+#define RCC_APB2ENR_IOPDEN_Pos (5U)
+#define RCC_APB2ENR_IOPDEN_Msk (0x1U << RCC_APB2ENR_IOPDEN_Pos) /*!< 0x00000020 */
+#define RCC_APB2ENR_IOPDEN RCC_APB2ENR_IOPDEN_Msk /*!< I/O port D clock enable */
+#define RCC_APB2ENR_ADC1EN_Pos (9U)
+#define RCC_APB2ENR_ADC1EN_Msk (0x1U << RCC_APB2ENR_ADC1EN_Pos) /*!< 0x00000200 */
+#define RCC_APB2ENR_ADC1EN RCC_APB2ENR_ADC1EN_Msk /*!< ADC 1 interface clock enable */
+
+
+#define RCC_APB2ENR_TIM1EN_Pos (11U)
+#define RCC_APB2ENR_TIM1EN_Msk (0x1U << RCC_APB2ENR_TIM1EN_Pos) /*!< 0x00000800 */
+#define RCC_APB2ENR_TIM1EN RCC_APB2ENR_TIM1EN_Msk /*!< TIM1 Timer clock enable */
+#define RCC_APB2ENR_SPI1EN_Pos (12U)
+#define RCC_APB2ENR_SPI1EN_Msk (0x1U << RCC_APB2ENR_SPI1EN_Pos) /*!< 0x00001000 */
+#define RCC_APB2ENR_SPI1EN RCC_APB2ENR_SPI1EN_Msk /*!< SPI 1 clock enable */
+#define RCC_APB2ENR_USART1EN_Pos (14U)
+#define RCC_APB2ENR_USART1EN_Msk (0x1U << RCC_APB2ENR_USART1EN_Pos) /*!< 0x00004000 */
+#define RCC_APB2ENR_USART1EN RCC_APB2ENR_USART1EN_Msk /*!< USART1 clock enable */
+
+
+#define RCC_APB2ENR_IOPEEN_Pos (6U)
+#define RCC_APB2ENR_IOPEEN_Msk (0x1U << RCC_APB2ENR_IOPEEN_Pos) /*!< 0x00000040 */
+#define RCC_APB2ENR_IOPEEN RCC_APB2ENR_IOPEEN_Msk /*!< I/O port E clock enable */
+
+
+
+
+/***************** Bit definition for RCC_APB1ENR register ******************/
+#define RCC_APB1ENR_TIM2EN_Pos (0U)
+#define RCC_APB1ENR_TIM2EN_Msk (0x1U << RCC_APB1ENR_TIM2EN_Pos) /*!< 0x00000001 */
+#define RCC_APB1ENR_TIM2EN RCC_APB1ENR_TIM2EN_Msk /*!< Timer 2 clock enabled*/
+#define RCC_APB1ENR_TIM3EN_Pos (1U)
+#define RCC_APB1ENR_TIM3EN_Msk (0x1U << RCC_APB1ENR_TIM3EN_Pos) /*!< 0x00000002 */
+#define RCC_APB1ENR_TIM3EN RCC_APB1ENR_TIM3EN_Msk /*!< Timer 3 clock enable */
+#define RCC_APB1ENR_WWDGEN_Pos (11U)
+#define RCC_APB1ENR_WWDGEN_Msk (0x1U << RCC_APB1ENR_WWDGEN_Pos) /*!< 0x00000800 */
+#define RCC_APB1ENR_WWDGEN RCC_APB1ENR_WWDGEN_Msk /*!< Window Watchdog clock enable */
+#define RCC_APB1ENR_USART2EN_Pos (17U)
+#define RCC_APB1ENR_USART2EN_Msk (0x1U << RCC_APB1ENR_USART2EN_Pos) /*!< 0x00020000 */
+#define RCC_APB1ENR_USART2EN RCC_APB1ENR_USART2EN_Msk /*!< USART 2 clock enable */
+#define RCC_APB1ENR_I2C1EN_Pos (21U)
+#define RCC_APB1ENR_I2C1EN_Msk (0x1U << RCC_APB1ENR_I2C1EN_Pos) /*!< 0x00200000 */
+#define RCC_APB1ENR_I2C1EN RCC_APB1ENR_I2C1EN_Msk /*!< I2C 1 clock enable */
+
+
+#define RCC_APB1ENR_BKPEN_Pos (27U)
+#define RCC_APB1ENR_BKPEN_Msk (0x1U << RCC_APB1ENR_BKPEN_Pos) /*!< 0x08000000 */
+#define RCC_APB1ENR_BKPEN RCC_APB1ENR_BKPEN_Msk /*!< Backup interface clock enable */
+#define RCC_APB1ENR_PWREN_Pos (28U)
+#define RCC_APB1ENR_PWREN_Msk (0x1U << RCC_APB1ENR_PWREN_Pos) /*!< 0x10000000 */
+#define RCC_APB1ENR_PWREN RCC_APB1ENR_PWREN_Msk /*!< Power interface clock enable */
+
+#define RCC_APB1ENR_TIM4EN_Pos (2U)
+#define RCC_APB1ENR_TIM4EN_Msk (0x1U << RCC_APB1ENR_TIM4EN_Pos) /*!< 0x00000004 */
+#define RCC_APB1ENR_TIM4EN RCC_APB1ENR_TIM4EN_Msk /*!< Timer 4 clock enable */
+#define RCC_APB1ENR_SPI2EN_Pos (14U)
+#define RCC_APB1ENR_SPI2EN_Msk (0x1U << RCC_APB1ENR_SPI2EN_Pos) /*!< 0x00004000 */
+#define RCC_APB1ENR_SPI2EN RCC_APB1ENR_SPI2EN_Msk /*!< SPI 2 clock enable */
+#define RCC_APB1ENR_USART3EN_Pos (18U)
+#define RCC_APB1ENR_USART3EN_Msk (0x1U << RCC_APB1ENR_USART3EN_Pos) /*!< 0x00040000 */
+#define RCC_APB1ENR_USART3EN RCC_APB1ENR_USART3EN_Msk /*!< USART 3 clock enable */
+#define RCC_APB1ENR_I2C2EN_Pos (22U)
+#define RCC_APB1ENR_I2C2EN_Msk (0x1U << RCC_APB1ENR_I2C2EN_Pos) /*!< 0x00400000 */
+#define RCC_APB1ENR_I2C2EN RCC_APB1ENR_I2C2EN_Msk /*!< I2C 2 clock enable */
+
+
+
+
+
+
+
+/******************* Bit definition for RCC_BDCR register *******************/
+#define RCC_BDCR_LSEON_Pos (0U)
+#define RCC_BDCR_LSEON_Msk (0x1U << RCC_BDCR_LSEON_Pos) /*!< 0x00000001 */
+#define RCC_BDCR_LSEON RCC_BDCR_LSEON_Msk /*!< External Low Speed oscillator enable */
+#define RCC_BDCR_LSERDY_Pos (1U)
+#define RCC_BDCR_LSERDY_Msk (0x1U << RCC_BDCR_LSERDY_Pos) /*!< 0x00000002 */
+#define RCC_BDCR_LSERDY RCC_BDCR_LSERDY_Msk /*!< External Low Speed oscillator Ready */
+#define RCC_BDCR_LSEBYP_Pos (2U)
+#define RCC_BDCR_LSEBYP_Msk (0x1U << RCC_BDCR_LSEBYP_Pos) /*!< 0x00000004 */
+#define RCC_BDCR_LSEBYP RCC_BDCR_LSEBYP_Msk /*!< External Low Speed oscillator Bypass */
+
+#define RCC_BDCR_RTCSEL_Pos (8U)
+#define RCC_BDCR_RTCSEL_Msk (0x3U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000300 */
+#define RCC_BDCR_RTCSEL RCC_BDCR_RTCSEL_Msk /*!< RTCSEL[1:0] bits (RTC clock source selection) */
+#define RCC_BDCR_RTCSEL_0 (0x1U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000100 */
+#define RCC_BDCR_RTCSEL_1 (0x2U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000200 */
+
+/*!< RTC congiguration */
+#define RCC_BDCR_RTCSEL_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */
+#define RCC_BDCR_RTCSEL_LSE ((uint32_t)0x00000100) /*!< LSE oscillator clock used as RTC clock */
+#define RCC_BDCR_RTCSEL_LSI ((uint32_t)0x00000200) /*!< LSI oscillator clock used as RTC clock */
+#define RCC_BDCR_RTCSEL_HSE ((uint32_t)0x00000300) /*!< HSE oscillator clock divided by 128 used as RTC clock */
+
+#define RCC_BDCR_RTCEN_Pos (15U)
+#define RCC_BDCR_RTCEN_Msk (0x1U << RCC_BDCR_RTCEN_Pos) /*!< 0x00008000 */
+#define RCC_BDCR_RTCEN RCC_BDCR_RTCEN_Msk /*!< RTC clock enable */
+#define RCC_BDCR_BDRST_Pos (16U)
+#define RCC_BDCR_BDRST_Msk (0x1U << RCC_BDCR_BDRST_Pos) /*!< 0x00010000 */
+#define RCC_BDCR_BDRST RCC_BDCR_BDRST_Msk /*!< Backup domain software reset */
+
+/******************* Bit definition for RCC_CSR register ********************/
+#define RCC_CSR_LSION_Pos (0U)
+#define RCC_CSR_LSION_Msk (0x1U << RCC_CSR_LSION_Pos) /*!< 0x00000001 */
+#define RCC_CSR_LSION RCC_CSR_LSION_Msk /*!< Internal Low Speed oscillator enable */
+#define RCC_CSR_LSIRDY_Pos (1U)
+#define RCC_CSR_LSIRDY_Msk (0x1U << RCC_CSR_LSIRDY_Pos) /*!< 0x00000002 */
+#define RCC_CSR_LSIRDY RCC_CSR_LSIRDY_Msk /*!< Internal Low Speed oscillator Ready */
+#define RCC_CSR_RMVF_Pos (24U)
+#define RCC_CSR_RMVF_Msk (0x1U << RCC_CSR_RMVF_Pos) /*!< 0x01000000 */
+#define RCC_CSR_RMVF RCC_CSR_RMVF_Msk /*!< Remove reset flag */
+#define RCC_CSR_PINRSTF_Pos (26U)
+#define RCC_CSR_PINRSTF_Msk (0x1U << RCC_CSR_PINRSTF_Pos) /*!< 0x04000000 */
+#define RCC_CSR_PINRSTF RCC_CSR_PINRSTF_Msk /*!< PIN reset flag */
+#define RCC_CSR_PORRSTF_Pos (27U)
+#define RCC_CSR_PORRSTF_Msk (0x1U << RCC_CSR_PORRSTF_Pos) /*!< 0x08000000 */
+#define RCC_CSR_PORRSTF RCC_CSR_PORRSTF_Msk /*!< POR/PDR reset flag */
+#define RCC_CSR_SFTRSTF_Pos (28U)
+#define RCC_CSR_SFTRSTF_Msk (0x1U << RCC_CSR_SFTRSTF_Pos) /*!< 0x10000000 */
+#define RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF_Msk /*!< Software Reset flag */
+#define RCC_CSR_IWDGRSTF_Pos (29U)
+#define RCC_CSR_IWDGRSTF_Msk (0x1U << RCC_CSR_IWDGRSTF_Pos) /*!< 0x20000000 */
+#define RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF_Msk /*!< Independent Watchdog reset flag */
+#define RCC_CSR_WWDGRSTF_Pos (30U)
+#define RCC_CSR_WWDGRSTF_Msk (0x1U << RCC_CSR_WWDGRSTF_Pos) /*!< 0x40000000 */
+#define RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF_Msk /*!< Window watchdog reset flag */
+#define RCC_CSR_LPWRRSTF_Pos (31U)
+#define RCC_CSR_LPWRRSTF_Msk (0x1U << RCC_CSR_LPWRRSTF_Pos) /*!< 0x80000000 */
+#define RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF_Msk /*!< Low-Power reset flag */
+
+
+
+/******************************************************************************/
+/* */
+/* General Purpose and Alternate Function I/O */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for GPIO_CRL register *******************/
+#define GPIO_CRL_MODE_Pos (0U)
+#define GPIO_CRL_MODE_Msk (0x33333333U << GPIO_CRL_MODE_Pos) /*!< 0x33333333 */
+#define GPIO_CRL_MODE GPIO_CRL_MODE_Msk /*!< Port x mode bits */
+
+#define GPIO_CRL_MODE0_Pos (0U)
+#define GPIO_CRL_MODE0_Msk (0x3U << GPIO_CRL_MODE0_Pos) /*!< 0x00000003 */
+#define GPIO_CRL_MODE0 GPIO_CRL_MODE0_Msk /*!< MODE0[1:0] bits (Port x mode bits, pin 0) */
+#define GPIO_CRL_MODE0_0 (0x1U << GPIO_CRL_MODE0_Pos) /*!< 0x00000001 */
+#define GPIO_CRL_MODE0_1 (0x2U << GPIO_CRL_MODE0_Pos) /*!< 0x00000002 */
+
+#define GPIO_CRL_MODE1_Pos (4U)
+#define GPIO_CRL_MODE1_Msk (0x3U << GPIO_CRL_MODE1_Pos) /*!< 0x00000030 */
+#define GPIO_CRL_MODE1 GPIO_CRL_MODE1_Msk /*!< MODE1[1:0] bits (Port x mode bits, pin 1) */
+#define GPIO_CRL_MODE1_0 (0x1U << GPIO_CRL_MODE1_Pos) /*!< 0x00000010 */
+#define GPIO_CRL_MODE1_1 (0x2U << GPIO_CRL_MODE1_Pos) /*!< 0x00000020 */
+
+#define GPIO_CRL_MODE2_Pos (8U)
+#define GPIO_CRL_MODE2_Msk (0x3U << GPIO_CRL_MODE2_Pos) /*!< 0x00000300 */
+#define GPIO_CRL_MODE2 GPIO_CRL_MODE2_Msk /*!< MODE2[1:0] bits (Port x mode bits, pin 2) */
+#define GPIO_CRL_MODE2_0 (0x1U << GPIO_CRL_MODE2_Pos) /*!< 0x00000100 */
+#define GPIO_CRL_MODE2_1 (0x2U << GPIO_CRL_MODE2_Pos) /*!< 0x00000200 */
+
+#define GPIO_CRL_MODE3_Pos (12U)
+#define GPIO_CRL_MODE3_Msk (0x3U << GPIO_CRL_MODE3_Pos) /*!< 0x00003000 */
+#define GPIO_CRL_MODE3 GPIO_CRL_MODE3_Msk /*!< MODE3[1:0] bits (Port x mode bits, pin 3) */
+#define GPIO_CRL_MODE3_0 (0x1U << GPIO_CRL_MODE3_Pos) /*!< 0x00001000 */
+#define GPIO_CRL_MODE3_1 (0x2U << GPIO_CRL_MODE3_Pos) /*!< 0x00002000 */
+
+#define GPIO_CRL_MODE4_Pos (16U)
+#define GPIO_CRL_MODE4_Msk (0x3U << GPIO_CRL_MODE4_Pos) /*!< 0x00030000 */
+#define GPIO_CRL_MODE4 GPIO_CRL_MODE4_Msk /*!< MODE4[1:0] bits (Port x mode bits, pin 4) */
+#define GPIO_CRL_MODE4_0 (0x1U << GPIO_CRL_MODE4_Pos) /*!< 0x00010000 */
+#define GPIO_CRL_MODE4_1 (0x2U << GPIO_CRL_MODE4_Pos) /*!< 0x00020000 */
+
+#define GPIO_CRL_MODE5_Pos (20U)
+#define GPIO_CRL_MODE5_Msk (0x3U << GPIO_CRL_MODE5_Pos) /*!< 0x00300000 */
+#define GPIO_CRL_MODE5 GPIO_CRL_MODE5_Msk /*!< MODE5[1:0] bits (Port x mode bits, pin 5) */
+#define GPIO_CRL_MODE5_0 (0x1U << GPIO_CRL_MODE5_Pos) /*!< 0x00100000 */
+#define GPIO_CRL_MODE5_1 (0x2U << GPIO_CRL_MODE5_Pos) /*!< 0x00200000 */
+
+#define GPIO_CRL_MODE6_Pos (24U)
+#define GPIO_CRL_MODE6_Msk (0x3U << GPIO_CRL_MODE6_Pos) /*!< 0x03000000 */
+#define GPIO_CRL_MODE6 GPIO_CRL_MODE6_Msk /*!< MODE6[1:0] bits (Port x mode bits, pin 6) */
+#define GPIO_CRL_MODE6_0 (0x1U << GPIO_CRL_MODE6_Pos) /*!< 0x01000000 */
+#define GPIO_CRL_MODE6_1 (0x2U << GPIO_CRL_MODE6_Pos) /*!< 0x02000000 */
+
+#define GPIO_CRL_MODE7_Pos (28U)
+#define GPIO_CRL_MODE7_Msk (0x3U << GPIO_CRL_MODE7_Pos) /*!< 0x30000000 */
+#define GPIO_CRL_MODE7 GPIO_CRL_MODE7_Msk /*!< MODE7[1:0] bits (Port x mode bits, pin 7) */
+#define GPIO_CRL_MODE7_0 (0x1U << GPIO_CRL_MODE7_Pos) /*!< 0x10000000 */
+#define GPIO_CRL_MODE7_1 (0x2U << GPIO_CRL_MODE7_Pos) /*!< 0x20000000 */
+
+#define GPIO_CRL_CNF_Pos (2U)
+#define GPIO_CRL_CNF_Msk (0x33333333U << GPIO_CRL_CNF_Pos) /*!< 0xCCCCCCCC */
+#define GPIO_CRL_CNF GPIO_CRL_CNF_Msk /*!< Port x configuration bits */
+
+#define GPIO_CRL_CNF0_Pos (2U)
+#define GPIO_CRL_CNF0_Msk (0x3U << GPIO_CRL_CNF0_Pos) /*!< 0x0000000C */
+#define GPIO_CRL_CNF0 GPIO_CRL_CNF0_Msk /*!< CNF0[1:0] bits (Port x configuration bits, pin 0) */
+#define GPIO_CRL_CNF0_0 (0x1U << GPIO_CRL_CNF0_Pos) /*!< 0x00000004 */
+#define GPIO_CRL_CNF0_1 (0x2U << GPIO_CRL_CNF0_Pos) /*!< 0x00000008 */
+
+#define GPIO_CRL_CNF1_Pos (6U)
+#define GPIO_CRL_CNF1_Msk (0x3U << GPIO_CRL_CNF1_Pos) /*!< 0x000000C0 */
+#define GPIO_CRL_CNF1 GPIO_CRL_CNF1_Msk /*!< CNF1[1:0] bits (Port x configuration bits, pin 1) */
+#define GPIO_CRL_CNF1_0 (0x1U << GPIO_CRL_CNF1_Pos) /*!< 0x00000040 */
+#define GPIO_CRL_CNF1_1 (0x2U << GPIO_CRL_CNF1_Pos) /*!< 0x00000080 */
+
+#define GPIO_CRL_CNF2_Pos (10U)
+#define GPIO_CRL_CNF2_Msk (0x3U << GPIO_CRL_CNF2_Pos) /*!< 0x00000C00 */
+#define GPIO_CRL_CNF2 GPIO_CRL_CNF2_Msk /*!< CNF2[1:0] bits (Port x configuration bits, pin 2) */
+#define GPIO_CRL_CNF2_0 (0x1U << GPIO_CRL_CNF2_Pos) /*!< 0x00000400 */
+#define GPIO_CRL_CNF2_1 (0x2U << GPIO_CRL_CNF2_Pos) /*!< 0x00000800 */
+
+#define GPIO_CRL_CNF3_Pos (14U)
+#define GPIO_CRL_CNF3_Msk (0x3U << GPIO_CRL_CNF3_Pos) /*!< 0x0000C000 */
+#define GPIO_CRL_CNF3 GPIO_CRL_CNF3_Msk /*!< CNF3[1:0] bits (Port x configuration bits, pin 3) */
+#define GPIO_CRL_CNF3_0 (0x1U << GPIO_CRL_CNF3_Pos) /*!< 0x00004000 */
+#define GPIO_CRL_CNF3_1 (0x2U << GPIO_CRL_CNF3_Pos) /*!< 0x00008000 */
+
+#define GPIO_CRL_CNF4_Pos (18U)
+#define GPIO_CRL_CNF4_Msk (0x3U << GPIO_CRL_CNF4_Pos) /*!< 0x000C0000 */
+#define GPIO_CRL_CNF4 GPIO_CRL_CNF4_Msk /*!< CNF4[1:0] bits (Port x configuration bits, pin 4) */
+#define GPIO_CRL_CNF4_0 (0x1U << GPIO_CRL_CNF4_Pos) /*!< 0x00040000 */
+#define GPIO_CRL_CNF4_1 (0x2U << GPIO_CRL_CNF4_Pos) /*!< 0x00080000 */
+
+#define GPIO_CRL_CNF5_Pos (22U)
+#define GPIO_CRL_CNF5_Msk (0x3U << GPIO_CRL_CNF5_Pos) /*!< 0x00C00000 */
+#define GPIO_CRL_CNF5 GPIO_CRL_CNF5_Msk /*!< CNF5[1:0] bits (Port x configuration bits, pin 5) */
+#define GPIO_CRL_CNF5_0 (0x1U << GPIO_CRL_CNF5_Pos) /*!< 0x00400000 */
+#define GPIO_CRL_CNF5_1 (0x2U << GPIO_CRL_CNF5_Pos) /*!< 0x00800000 */
+
+#define GPIO_CRL_CNF6_Pos (26U)
+#define GPIO_CRL_CNF6_Msk (0x3U << GPIO_CRL_CNF6_Pos) /*!< 0x0C000000 */
+#define GPIO_CRL_CNF6 GPIO_CRL_CNF6_Msk /*!< CNF6[1:0] bits (Port x configuration bits, pin 6) */
+#define GPIO_CRL_CNF6_0 (0x1U << GPIO_CRL_CNF6_Pos) /*!< 0x04000000 */
+#define GPIO_CRL_CNF6_1 (0x2U << GPIO_CRL_CNF6_Pos) /*!< 0x08000000 */
+
+#define GPIO_CRL_CNF7_Pos (30U)
+#define GPIO_CRL_CNF7_Msk (0x3U << GPIO_CRL_CNF7_Pos) /*!< 0xC0000000 */
+#define GPIO_CRL_CNF7 GPIO_CRL_CNF7_Msk /*!< CNF7[1:0] bits (Port x configuration bits, pin 7) */
+#define GPIO_CRL_CNF7_0 (0x1U << GPIO_CRL_CNF7_Pos) /*!< 0x40000000 */
+#define GPIO_CRL_CNF7_1 (0x2U << GPIO_CRL_CNF7_Pos) /*!< 0x80000000 */
+
+/******************* Bit definition for GPIO_CRH register *******************/
+#define GPIO_CRH_MODE_Pos (0U)
+#define GPIO_CRH_MODE_Msk (0x33333333U << GPIO_CRH_MODE_Pos) /*!< 0x33333333 */
+#define GPIO_CRH_MODE GPIO_CRH_MODE_Msk /*!< Port x mode bits */
+
+#define GPIO_CRH_MODE8_Pos (0U)
+#define GPIO_CRH_MODE8_Msk (0x3U << GPIO_CRH_MODE8_Pos) /*!< 0x00000003 */
+#define GPIO_CRH_MODE8 GPIO_CRH_MODE8_Msk /*!< MODE8[1:0] bits (Port x mode bits, pin 8) */
+#define GPIO_CRH_MODE8_0 (0x1U << GPIO_CRH_MODE8_Pos) /*!< 0x00000001 */
+#define GPIO_CRH_MODE8_1 (0x2U << GPIO_CRH_MODE8_Pos) /*!< 0x00000002 */
+
+#define GPIO_CRH_MODE9_Pos (4U)
+#define GPIO_CRH_MODE9_Msk (0x3U << GPIO_CRH_MODE9_Pos) /*!< 0x00000030 */
+#define GPIO_CRH_MODE9 GPIO_CRH_MODE9_Msk /*!< MODE9[1:0] bits (Port x mode bits, pin 9) */
+#define GPIO_CRH_MODE9_0 (0x1U << GPIO_CRH_MODE9_Pos) /*!< 0x00000010 */
+#define GPIO_CRH_MODE9_1 (0x2U << GPIO_CRH_MODE9_Pos) /*!< 0x00000020 */
+
+#define GPIO_CRH_MODE10_Pos (8U)
+#define GPIO_CRH_MODE10_Msk (0x3U << GPIO_CRH_MODE10_Pos) /*!< 0x00000300 */
+#define GPIO_CRH_MODE10 GPIO_CRH_MODE10_Msk /*!< MODE10[1:0] bits (Port x mode bits, pin 10) */
+#define GPIO_CRH_MODE10_0 (0x1U << GPIO_CRH_MODE10_Pos) /*!< 0x00000100 */
+#define GPIO_CRH_MODE10_1 (0x2U << GPIO_CRH_MODE10_Pos) /*!< 0x00000200 */
+
+#define GPIO_CRH_MODE11_Pos (12U)
+#define GPIO_CRH_MODE11_Msk (0x3U << GPIO_CRH_MODE11_Pos) /*!< 0x00003000 */
+#define GPIO_CRH_MODE11 GPIO_CRH_MODE11_Msk /*!< MODE11[1:0] bits (Port x mode bits, pin 11) */
+#define GPIO_CRH_MODE11_0 (0x1U << GPIO_CRH_MODE11_Pos) /*!< 0x00001000 */
+#define GPIO_CRH_MODE11_1 (0x2U << GPIO_CRH_MODE11_Pos) /*!< 0x00002000 */
+
+#define GPIO_CRH_MODE12_Pos (16U)
+#define GPIO_CRH_MODE12_Msk (0x3U << GPIO_CRH_MODE12_Pos) /*!< 0x00030000 */
+#define GPIO_CRH_MODE12 GPIO_CRH_MODE12_Msk /*!< MODE12[1:0] bits (Port x mode bits, pin 12) */
+#define GPIO_CRH_MODE12_0 (0x1U << GPIO_CRH_MODE12_Pos) /*!< 0x00010000 */
+#define GPIO_CRH_MODE12_1 (0x2U << GPIO_CRH_MODE12_Pos) /*!< 0x00020000 */
+
+#define GPIO_CRH_MODE13_Pos (20U)
+#define GPIO_CRH_MODE13_Msk (0x3U << GPIO_CRH_MODE13_Pos) /*!< 0x00300000 */
+#define GPIO_CRH_MODE13 GPIO_CRH_MODE13_Msk /*!< MODE13[1:0] bits (Port x mode bits, pin 13) */
+#define GPIO_CRH_MODE13_0 (0x1U << GPIO_CRH_MODE13_Pos) /*!< 0x00100000 */
+#define GPIO_CRH_MODE13_1 (0x2U << GPIO_CRH_MODE13_Pos) /*!< 0x00200000 */
+
+#define GPIO_CRH_MODE14_Pos (24U)
+#define GPIO_CRH_MODE14_Msk (0x3U << GPIO_CRH_MODE14_Pos) /*!< 0x03000000 */
+#define GPIO_CRH_MODE14 GPIO_CRH_MODE14_Msk /*!< MODE14[1:0] bits (Port x mode bits, pin 14) */
+#define GPIO_CRH_MODE14_0 (0x1U << GPIO_CRH_MODE14_Pos) /*!< 0x01000000 */
+#define GPIO_CRH_MODE14_1 (0x2U << GPIO_CRH_MODE14_Pos) /*!< 0x02000000 */
+
+#define GPIO_CRH_MODE15_Pos (28U)
+#define GPIO_CRH_MODE15_Msk (0x3U << GPIO_CRH_MODE15_Pos) /*!< 0x30000000 */
+#define GPIO_CRH_MODE15 GPIO_CRH_MODE15_Msk /*!< MODE15[1:0] bits (Port x mode bits, pin 15) */
+#define GPIO_CRH_MODE15_0 (0x1U << GPIO_CRH_MODE15_Pos) /*!< 0x10000000 */
+#define GPIO_CRH_MODE15_1 (0x2U << GPIO_CRH_MODE15_Pos) /*!< 0x20000000 */
+
+#define GPIO_CRH_CNF_Pos (2U)
+#define GPIO_CRH_CNF_Msk (0x33333333U << GPIO_CRH_CNF_Pos) /*!< 0xCCCCCCCC */
+#define GPIO_CRH_CNF GPIO_CRH_CNF_Msk /*!< Port x configuration bits */
+
+#define GPIO_CRH_CNF8_Pos (2U)
+#define GPIO_CRH_CNF8_Msk (0x3U << GPIO_CRH_CNF8_Pos) /*!< 0x0000000C */
+#define GPIO_CRH_CNF8 GPIO_CRH_CNF8_Msk /*!< CNF8[1:0] bits (Port x configuration bits, pin 8) */
+#define GPIO_CRH_CNF8_0 (0x1U << GPIO_CRH_CNF8_Pos) /*!< 0x00000004 */
+#define GPIO_CRH_CNF8_1 (0x2U << GPIO_CRH_CNF8_Pos) /*!< 0x00000008 */
+
+#define GPIO_CRH_CNF9_Pos (6U)
+#define GPIO_CRH_CNF9_Msk (0x3U << GPIO_CRH_CNF9_Pos) /*!< 0x000000C0 */
+#define GPIO_CRH_CNF9 GPIO_CRH_CNF9_Msk /*!< CNF9[1:0] bits (Port x configuration bits, pin 9) */
+#define GPIO_CRH_CNF9_0 (0x1U << GPIO_CRH_CNF9_Pos) /*!< 0x00000040 */
+#define GPIO_CRH_CNF9_1 (0x2U << GPIO_CRH_CNF9_Pos) /*!< 0x00000080 */
+
+#define GPIO_CRH_CNF10_Pos (10U)
+#define GPIO_CRH_CNF10_Msk (0x3U << GPIO_CRH_CNF10_Pos) /*!< 0x00000C00 */
+#define GPIO_CRH_CNF10 GPIO_CRH_CNF10_Msk /*!< CNF10[1:0] bits (Port x configuration bits, pin 10) */
+#define GPIO_CRH_CNF10_0 (0x1U << GPIO_CRH_CNF10_Pos) /*!< 0x00000400 */
+#define GPIO_CRH_CNF10_1 (0x2U << GPIO_CRH_CNF10_Pos) /*!< 0x00000800 */
+
+#define GPIO_CRH_CNF11_Pos (14U)
+#define GPIO_CRH_CNF11_Msk (0x3U << GPIO_CRH_CNF11_Pos) /*!< 0x0000C000 */
+#define GPIO_CRH_CNF11 GPIO_CRH_CNF11_Msk /*!< CNF11[1:0] bits (Port x configuration bits, pin 11) */
+#define GPIO_CRH_CNF11_0 (0x1U << GPIO_CRH_CNF11_Pos) /*!< 0x00004000 */
+#define GPIO_CRH_CNF11_1 (0x2U << GPIO_CRH_CNF11_Pos) /*!< 0x00008000 */
+
+#define GPIO_CRH_CNF12_Pos (18U)
+#define GPIO_CRH_CNF12_Msk (0x3U << GPIO_CRH_CNF12_Pos) /*!< 0x000C0000 */
+#define GPIO_CRH_CNF12 GPIO_CRH_CNF12_Msk /*!< CNF12[1:0] bits (Port x configuration bits, pin 12) */
+#define GPIO_CRH_CNF12_0 (0x1U << GPIO_CRH_CNF12_Pos) /*!< 0x00040000 */
+#define GPIO_CRH_CNF12_1 (0x2U << GPIO_CRH_CNF12_Pos) /*!< 0x00080000 */
+
+#define GPIO_CRH_CNF13_Pos (22U)
+#define GPIO_CRH_CNF13_Msk (0x3U << GPIO_CRH_CNF13_Pos) /*!< 0x00C00000 */
+#define GPIO_CRH_CNF13 GPIO_CRH_CNF13_Msk /*!< CNF13[1:0] bits (Port x configuration bits, pin 13) */
+#define GPIO_CRH_CNF13_0 (0x1U << GPIO_CRH_CNF13_Pos) /*!< 0x00400000 */
+#define GPIO_CRH_CNF13_1 (0x2U << GPIO_CRH_CNF13_Pos) /*!< 0x00800000 */
+
+#define GPIO_CRH_CNF14_Pos (26U)
+#define GPIO_CRH_CNF14_Msk (0x3U << GPIO_CRH_CNF14_Pos) /*!< 0x0C000000 */
+#define GPIO_CRH_CNF14 GPIO_CRH_CNF14_Msk /*!< CNF14[1:0] bits (Port x configuration bits, pin 14) */
+#define GPIO_CRH_CNF14_0 (0x1U << GPIO_CRH_CNF14_Pos) /*!< 0x04000000 */
+#define GPIO_CRH_CNF14_1 (0x2U << GPIO_CRH_CNF14_Pos) /*!< 0x08000000 */
+
+#define GPIO_CRH_CNF15_Pos (30U)
+#define GPIO_CRH_CNF15_Msk (0x3U << GPIO_CRH_CNF15_Pos) /*!< 0xC0000000 */
+#define GPIO_CRH_CNF15 GPIO_CRH_CNF15_Msk /*!< CNF15[1:0] bits (Port x configuration bits, pin 15) */
+#define GPIO_CRH_CNF15_0 (0x1U << GPIO_CRH_CNF15_Pos) /*!< 0x40000000 */
+#define GPIO_CRH_CNF15_1 (0x2U << GPIO_CRH_CNF15_Pos) /*!< 0x80000000 */
+
+/*!<****************** Bit definition for GPIO_IDR register *******************/
+#define GPIO_IDR_IDR0_Pos (0U)
+#define GPIO_IDR_IDR0_Msk (0x1U << GPIO_IDR_IDR0_Pos) /*!< 0x00000001 */
+#define GPIO_IDR_IDR0 GPIO_IDR_IDR0_Msk /*!< Port input data, bit 0 */
+#define GPIO_IDR_IDR1_Pos (1U)
+#define GPIO_IDR_IDR1_Msk (0x1U << GPIO_IDR_IDR1_Pos) /*!< 0x00000002 */
+#define GPIO_IDR_IDR1 GPIO_IDR_IDR1_Msk /*!< Port input data, bit 1 */
+#define GPIO_IDR_IDR2_Pos (2U)
+#define GPIO_IDR_IDR2_Msk (0x1U << GPIO_IDR_IDR2_Pos) /*!< 0x00000004 */
+#define GPIO_IDR_IDR2 GPIO_IDR_IDR2_Msk /*!< Port input data, bit 2 */
+#define GPIO_IDR_IDR3_Pos (3U)
+#define GPIO_IDR_IDR3_Msk (0x1U << GPIO_IDR_IDR3_Pos) /*!< 0x00000008 */
+#define GPIO_IDR_IDR3 GPIO_IDR_IDR3_Msk /*!< Port input data, bit 3 */
+#define GPIO_IDR_IDR4_Pos (4U)
+#define GPIO_IDR_IDR4_Msk (0x1U << GPIO_IDR_IDR4_Pos) /*!< 0x00000010 */
+#define GPIO_IDR_IDR4 GPIO_IDR_IDR4_Msk /*!< Port input data, bit 4 */
+#define GPIO_IDR_IDR5_Pos (5U)
+#define GPIO_IDR_IDR5_Msk (0x1U << GPIO_IDR_IDR5_Pos) /*!< 0x00000020 */
+#define GPIO_IDR_IDR5 GPIO_IDR_IDR5_Msk /*!< Port input data, bit 5 */
+#define GPIO_IDR_IDR6_Pos (6U)
+#define GPIO_IDR_IDR6_Msk (0x1U << GPIO_IDR_IDR6_Pos) /*!< 0x00000040 */
+#define GPIO_IDR_IDR6 GPIO_IDR_IDR6_Msk /*!< Port input data, bit 6 */
+#define GPIO_IDR_IDR7_Pos (7U)
+#define GPIO_IDR_IDR7_Msk (0x1U << GPIO_IDR_IDR7_Pos) /*!< 0x00000080 */
+#define GPIO_IDR_IDR7 GPIO_IDR_IDR7_Msk /*!< Port input data, bit 7 */
+#define GPIO_IDR_IDR8_Pos (8U)
+#define GPIO_IDR_IDR8_Msk (0x1U << GPIO_IDR_IDR8_Pos) /*!< 0x00000100 */
+#define GPIO_IDR_IDR8 GPIO_IDR_IDR8_Msk /*!< Port input data, bit 8 */
+#define GPIO_IDR_IDR9_Pos (9U)
+#define GPIO_IDR_IDR9_Msk (0x1U << GPIO_IDR_IDR9_Pos) /*!< 0x00000200 */
+#define GPIO_IDR_IDR9 GPIO_IDR_IDR9_Msk /*!< Port input data, bit 9 */
+#define GPIO_IDR_IDR10_Pos (10U)
+#define GPIO_IDR_IDR10_Msk (0x1U << GPIO_IDR_IDR10_Pos) /*!< 0x00000400 */
+#define GPIO_IDR_IDR10 GPIO_IDR_IDR10_Msk /*!< Port input data, bit 10 */
+#define GPIO_IDR_IDR11_Pos (11U)
+#define GPIO_IDR_IDR11_Msk (0x1U << GPIO_IDR_IDR11_Pos) /*!< 0x00000800 */
+#define GPIO_IDR_IDR11 GPIO_IDR_IDR11_Msk /*!< Port input data, bit 11 */
+#define GPIO_IDR_IDR12_Pos (12U)
+#define GPIO_IDR_IDR12_Msk (0x1U << GPIO_IDR_IDR12_Pos) /*!< 0x00001000 */
+#define GPIO_IDR_IDR12 GPIO_IDR_IDR12_Msk /*!< Port input data, bit 12 */
+#define GPIO_IDR_IDR13_Pos (13U)
+#define GPIO_IDR_IDR13_Msk (0x1U << GPIO_IDR_IDR13_Pos) /*!< 0x00002000 */
+#define GPIO_IDR_IDR13 GPIO_IDR_IDR13_Msk /*!< Port input data, bit 13 */
+#define GPIO_IDR_IDR14_Pos (14U)
+#define GPIO_IDR_IDR14_Msk (0x1U << GPIO_IDR_IDR14_Pos) /*!< 0x00004000 */
+#define GPIO_IDR_IDR14 GPIO_IDR_IDR14_Msk /*!< Port input data, bit 14 */
+#define GPIO_IDR_IDR15_Pos (15U)
+#define GPIO_IDR_IDR15_Msk (0x1U << GPIO_IDR_IDR15_Pos) /*!< 0x00008000 */
+#define GPIO_IDR_IDR15 GPIO_IDR_IDR15_Msk /*!< Port input data, bit 15 */
+
+/******************* Bit definition for GPIO_ODR register *******************/
+#define GPIO_ODR_ODR0_Pos (0U)
+#define GPIO_ODR_ODR0_Msk (0x1U << GPIO_ODR_ODR0_Pos) /*!< 0x00000001 */
+#define GPIO_ODR_ODR0 GPIO_ODR_ODR0_Msk /*!< Port output data, bit 0 */
+#define GPIO_ODR_ODR1_Pos (1U)
+#define GPIO_ODR_ODR1_Msk (0x1U << GPIO_ODR_ODR1_Pos) /*!< 0x00000002 */
+#define GPIO_ODR_ODR1 GPIO_ODR_ODR1_Msk /*!< Port output data, bit 1 */
+#define GPIO_ODR_ODR2_Pos (2U)
+#define GPIO_ODR_ODR2_Msk (0x1U << GPIO_ODR_ODR2_Pos) /*!< 0x00000004 */
+#define GPIO_ODR_ODR2 GPIO_ODR_ODR2_Msk /*!< Port output data, bit 2 */
+#define GPIO_ODR_ODR3_Pos (3U)
+#define GPIO_ODR_ODR3_Msk (0x1U << GPIO_ODR_ODR3_Pos) /*!< 0x00000008 */
+#define GPIO_ODR_ODR3 GPIO_ODR_ODR3_Msk /*!< Port output data, bit 3 */
+#define GPIO_ODR_ODR4_Pos (4U)
+#define GPIO_ODR_ODR4_Msk (0x1U << GPIO_ODR_ODR4_Pos) /*!< 0x00000010 */
+#define GPIO_ODR_ODR4 GPIO_ODR_ODR4_Msk /*!< Port output data, bit 4 */
+#define GPIO_ODR_ODR5_Pos (5U)
+#define GPIO_ODR_ODR5_Msk (0x1U << GPIO_ODR_ODR5_Pos) /*!< 0x00000020 */
+#define GPIO_ODR_ODR5 GPIO_ODR_ODR5_Msk /*!< Port output data, bit 5 */
+#define GPIO_ODR_ODR6_Pos (6U)
+#define GPIO_ODR_ODR6_Msk (0x1U << GPIO_ODR_ODR6_Pos) /*!< 0x00000040 */
+#define GPIO_ODR_ODR6 GPIO_ODR_ODR6_Msk /*!< Port output data, bit 6 */
+#define GPIO_ODR_ODR7_Pos (7U)
+#define GPIO_ODR_ODR7_Msk (0x1U << GPIO_ODR_ODR7_Pos) /*!< 0x00000080 */
+#define GPIO_ODR_ODR7 GPIO_ODR_ODR7_Msk /*!< Port output data, bit 7 */
+#define GPIO_ODR_ODR8_Pos (8U)
+#define GPIO_ODR_ODR8_Msk (0x1U << GPIO_ODR_ODR8_Pos) /*!< 0x00000100 */
+#define GPIO_ODR_ODR8 GPIO_ODR_ODR8_Msk /*!< Port output data, bit 8 */
+#define GPIO_ODR_ODR9_Pos (9U)
+#define GPIO_ODR_ODR9_Msk (0x1U << GPIO_ODR_ODR9_Pos) /*!< 0x00000200 */
+#define GPIO_ODR_ODR9 GPIO_ODR_ODR9_Msk /*!< Port output data, bit 9 */
+#define GPIO_ODR_ODR10_Pos (10U)
+#define GPIO_ODR_ODR10_Msk (0x1U << GPIO_ODR_ODR10_Pos) /*!< 0x00000400 */
+#define GPIO_ODR_ODR10 GPIO_ODR_ODR10_Msk /*!< Port output data, bit 10 */
+#define GPIO_ODR_ODR11_Pos (11U)
+#define GPIO_ODR_ODR11_Msk (0x1U << GPIO_ODR_ODR11_Pos) /*!< 0x00000800 */
+#define GPIO_ODR_ODR11 GPIO_ODR_ODR11_Msk /*!< Port output data, bit 11 */
+#define GPIO_ODR_ODR12_Pos (12U)
+#define GPIO_ODR_ODR12_Msk (0x1U << GPIO_ODR_ODR12_Pos) /*!< 0x00001000 */
+#define GPIO_ODR_ODR12 GPIO_ODR_ODR12_Msk /*!< Port output data, bit 12 */
+#define GPIO_ODR_ODR13_Pos (13U)
+#define GPIO_ODR_ODR13_Msk (0x1U << GPIO_ODR_ODR13_Pos) /*!< 0x00002000 */
+#define GPIO_ODR_ODR13 GPIO_ODR_ODR13_Msk /*!< Port output data, bit 13 */
+#define GPIO_ODR_ODR14_Pos (14U)
+#define GPIO_ODR_ODR14_Msk (0x1U << GPIO_ODR_ODR14_Pos) /*!< 0x00004000 */
+#define GPIO_ODR_ODR14 GPIO_ODR_ODR14_Msk /*!< Port output data, bit 14 */
+#define GPIO_ODR_ODR15_Pos (15U)
+#define GPIO_ODR_ODR15_Msk (0x1U << GPIO_ODR_ODR15_Pos) /*!< 0x00008000 */
+#define GPIO_ODR_ODR15 GPIO_ODR_ODR15_Msk /*!< Port output data, bit 15 */
+
+/****************** Bit definition for GPIO_BSRR register *******************/
+#define GPIO_BSRR_BS0_Pos (0U)
+#define GPIO_BSRR_BS0_Msk (0x1U << GPIO_BSRR_BS0_Pos) /*!< 0x00000001 */
+#define GPIO_BSRR_BS0 GPIO_BSRR_BS0_Msk /*!< Port x Set bit 0 */
+#define GPIO_BSRR_BS1_Pos (1U)
+#define GPIO_BSRR_BS1_Msk (0x1U << GPIO_BSRR_BS1_Pos) /*!< 0x00000002 */
+#define GPIO_BSRR_BS1 GPIO_BSRR_BS1_Msk /*!< Port x Set bit 1 */
+#define GPIO_BSRR_BS2_Pos (2U)
+#define GPIO_BSRR_BS2_Msk (0x1U << GPIO_BSRR_BS2_Pos) /*!< 0x00000004 */
+#define GPIO_BSRR_BS2 GPIO_BSRR_BS2_Msk /*!< Port x Set bit 2 */
+#define GPIO_BSRR_BS3_Pos (3U)
+#define GPIO_BSRR_BS3_Msk (0x1U << GPIO_BSRR_BS3_Pos) /*!< 0x00000008 */
+#define GPIO_BSRR_BS3 GPIO_BSRR_BS3_Msk /*!< Port x Set bit 3 */
+#define GPIO_BSRR_BS4_Pos (4U)
+#define GPIO_BSRR_BS4_Msk (0x1U << GPIO_BSRR_BS4_Pos) /*!< 0x00000010 */
+#define GPIO_BSRR_BS4 GPIO_BSRR_BS4_Msk /*!< Port x Set bit 4 */
+#define GPIO_BSRR_BS5_Pos (5U)
+#define GPIO_BSRR_BS5_Msk (0x1U << GPIO_BSRR_BS5_Pos) /*!< 0x00000020 */
+#define GPIO_BSRR_BS5 GPIO_BSRR_BS5_Msk /*!< Port x Set bit 5 */
+#define GPIO_BSRR_BS6_Pos (6U)
+#define GPIO_BSRR_BS6_Msk (0x1U << GPIO_BSRR_BS6_Pos) /*!< 0x00000040 */
+#define GPIO_BSRR_BS6 GPIO_BSRR_BS6_Msk /*!< Port x Set bit 6 */
+#define GPIO_BSRR_BS7_Pos (7U)
+#define GPIO_BSRR_BS7_Msk (0x1U << GPIO_BSRR_BS7_Pos) /*!< 0x00000080 */
+#define GPIO_BSRR_BS7 GPIO_BSRR_BS7_Msk /*!< Port x Set bit 7 */
+#define GPIO_BSRR_BS8_Pos (8U)
+#define GPIO_BSRR_BS8_Msk (0x1U << GPIO_BSRR_BS8_Pos) /*!< 0x00000100 */
+#define GPIO_BSRR_BS8 GPIO_BSRR_BS8_Msk /*!< Port x Set bit 8 */
+#define GPIO_BSRR_BS9_Pos (9U)
+#define GPIO_BSRR_BS9_Msk (0x1U << GPIO_BSRR_BS9_Pos) /*!< 0x00000200 */
+#define GPIO_BSRR_BS9 GPIO_BSRR_BS9_Msk /*!< Port x Set bit 9 */
+#define GPIO_BSRR_BS10_Pos (10U)
+#define GPIO_BSRR_BS10_Msk (0x1U << GPIO_BSRR_BS10_Pos) /*!< 0x00000400 */
+#define GPIO_BSRR_BS10 GPIO_BSRR_BS10_Msk /*!< Port x Set bit 10 */
+#define GPIO_BSRR_BS11_Pos (11U)
+#define GPIO_BSRR_BS11_Msk (0x1U << GPIO_BSRR_BS11_Pos) /*!< 0x00000800 */
+#define GPIO_BSRR_BS11 GPIO_BSRR_BS11_Msk /*!< Port x Set bit 11 */
+#define GPIO_BSRR_BS12_Pos (12U)
+#define GPIO_BSRR_BS12_Msk (0x1U << GPIO_BSRR_BS12_Pos) /*!< 0x00001000 */
+#define GPIO_BSRR_BS12 GPIO_BSRR_BS12_Msk /*!< Port x Set bit 12 */
+#define GPIO_BSRR_BS13_Pos (13U)
+#define GPIO_BSRR_BS13_Msk (0x1U << GPIO_BSRR_BS13_Pos) /*!< 0x00002000 */
+#define GPIO_BSRR_BS13 GPIO_BSRR_BS13_Msk /*!< Port x Set bit 13 */
+#define GPIO_BSRR_BS14_Pos (14U)
+#define GPIO_BSRR_BS14_Msk (0x1U << GPIO_BSRR_BS14_Pos) /*!< 0x00004000 */
+#define GPIO_BSRR_BS14 GPIO_BSRR_BS14_Msk /*!< Port x Set bit 14 */
+#define GPIO_BSRR_BS15_Pos (15U)
+#define GPIO_BSRR_BS15_Msk (0x1U << GPIO_BSRR_BS15_Pos) /*!< 0x00008000 */
+#define GPIO_BSRR_BS15 GPIO_BSRR_BS15_Msk /*!< Port x Set bit 15 */
+
+#define GPIO_BSRR_BR0_Pos (16U)
+#define GPIO_BSRR_BR0_Msk (0x1U << GPIO_BSRR_BR0_Pos) /*!< 0x00010000 */
+#define GPIO_BSRR_BR0 GPIO_BSRR_BR0_Msk /*!< Port x Reset bit 0 */
+#define GPIO_BSRR_BR1_Pos (17U)
+#define GPIO_BSRR_BR1_Msk (0x1U << GPIO_BSRR_BR1_Pos) /*!< 0x00020000 */
+#define GPIO_BSRR_BR1 GPIO_BSRR_BR1_Msk /*!< Port x Reset bit 1 */
+#define GPIO_BSRR_BR2_Pos (18U)
+#define GPIO_BSRR_BR2_Msk (0x1U << GPIO_BSRR_BR2_Pos) /*!< 0x00040000 */
+#define GPIO_BSRR_BR2 GPIO_BSRR_BR2_Msk /*!< Port x Reset bit 2 */
+#define GPIO_BSRR_BR3_Pos (19U)
+#define GPIO_BSRR_BR3_Msk (0x1U << GPIO_BSRR_BR3_Pos) /*!< 0x00080000 */
+#define GPIO_BSRR_BR3 GPIO_BSRR_BR3_Msk /*!< Port x Reset bit 3 */
+#define GPIO_BSRR_BR4_Pos (20U)
+#define GPIO_BSRR_BR4_Msk (0x1U << GPIO_BSRR_BR4_Pos) /*!< 0x00100000 */
+#define GPIO_BSRR_BR4 GPIO_BSRR_BR4_Msk /*!< Port x Reset bit 4 */
+#define GPIO_BSRR_BR5_Pos (21U)
+#define GPIO_BSRR_BR5_Msk (0x1U << GPIO_BSRR_BR5_Pos) /*!< 0x00200000 */
+#define GPIO_BSRR_BR5 GPIO_BSRR_BR5_Msk /*!< Port x Reset bit 5 */
+#define GPIO_BSRR_BR6_Pos (22U)
+#define GPIO_BSRR_BR6_Msk (0x1U << GPIO_BSRR_BR6_Pos) /*!< 0x00400000 */
+#define GPIO_BSRR_BR6 GPIO_BSRR_BR6_Msk /*!< Port x Reset bit 6 */
+#define GPIO_BSRR_BR7_Pos (23U)
+#define GPIO_BSRR_BR7_Msk (0x1U << GPIO_BSRR_BR7_Pos) /*!< 0x00800000 */
+#define GPIO_BSRR_BR7 GPIO_BSRR_BR7_Msk /*!< Port x Reset bit 7 */
+#define GPIO_BSRR_BR8_Pos (24U)
+#define GPIO_BSRR_BR8_Msk (0x1U << GPIO_BSRR_BR8_Pos) /*!< 0x01000000 */
+#define GPIO_BSRR_BR8 GPIO_BSRR_BR8_Msk /*!< Port x Reset bit 8 */
+#define GPIO_BSRR_BR9_Pos (25U)
+#define GPIO_BSRR_BR9_Msk (0x1U << GPIO_BSRR_BR9_Pos) /*!< 0x02000000 */
+#define GPIO_BSRR_BR9 GPIO_BSRR_BR9_Msk /*!< Port x Reset bit 9 */
+#define GPIO_BSRR_BR10_Pos (26U)
+#define GPIO_BSRR_BR10_Msk (0x1U << GPIO_BSRR_BR10_Pos) /*!< 0x04000000 */
+#define GPIO_BSRR_BR10 GPIO_BSRR_BR10_Msk /*!< Port x Reset bit 10 */
+#define GPIO_BSRR_BR11_Pos (27U)
+#define GPIO_BSRR_BR11_Msk (0x1U << GPIO_BSRR_BR11_Pos) /*!< 0x08000000 */
+#define GPIO_BSRR_BR11 GPIO_BSRR_BR11_Msk /*!< Port x Reset bit 11 */
+#define GPIO_BSRR_BR12_Pos (28U)
+#define GPIO_BSRR_BR12_Msk (0x1U << GPIO_BSRR_BR12_Pos) /*!< 0x10000000 */
+#define GPIO_BSRR_BR12 GPIO_BSRR_BR12_Msk /*!< Port x Reset bit 12 */
+#define GPIO_BSRR_BR13_Pos (29U)
+#define GPIO_BSRR_BR13_Msk (0x1U << GPIO_BSRR_BR13_Pos) /*!< 0x20000000 */
+#define GPIO_BSRR_BR13 GPIO_BSRR_BR13_Msk /*!< Port x Reset bit 13 */
+#define GPIO_BSRR_BR14_Pos (30U)
+#define GPIO_BSRR_BR14_Msk (0x1U << GPIO_BSRR_BR14_Pos) /*!< 0x40000000 */
+#define GPIO_BSRR_BR14 GPIO_BSRR_BR14_Msk /*!< Port x Reset bit 14 */
+#define GPIO_BSRR_BR15_Pos (31U)
+#define GPIO_BSRR_BR15_Msk (0x1U << GPIO_BSRR_BR15_Pos) /*!< 0x80000000 */
+#define GPIO_BSRR_BR15 GPIO_BSRR_BR15_Msk /*!< Port x Reset bit 15 */
+
+/******************* Bit definition for GPIO_BRR register *******************/
+#define GPIO_BRR_BR0_Pos (0U)
+#define GPIO_BRR_BR0_Msk (0x1U << GPIO_BRR_BR0_Pos) /*!< 0x00000001 */
+#define GPIO_BRR_BR0 GPIO_BRR_BR0_Msk /*!< Port x Reset bit 0 */
+#define GPIO_BRR_BR1_Pos (1U)
+#define GPIO_BRR_BR1_Msk (0x1U << GPIO_BRR_BR1_Pos) /*!< 0x00000002 */
+#define GPIO_BRR_BR1 GPIO_BRR_BR1_Msk /*!< Port x Reset bit 1 */
+#define GPIO_BRR_BR2_Pos (2U)
+#define GPIO_BRR_BR2_Msk (0x1U << GPIO_BRR_BR2_Pos) /*!< 0x00000004 */
+#define GPIO_BRR_BR2 GPIO_BRR_BR2_Msk /*!< Port x Reset bit 2 */
+#define GPIO_BRR_BR3_Pos (3U)
+#define GPIO_BRR_BR3_Msk (0x1U << GPIO_BRR_BR3_Pos) /*!< 0x00000008 */
+#define GPIO_BRR_BR3 GPIO_BRR_BR3_Msk /*!< Port x Reset bit 3 */
+#define GPIO_BRR_BR4_Pos (4U)
+#define GPIO_BRR_BR4_Msk (0x1U << GPIO_BRR_BR4_Pos) /*!< 0x00000010 */
+#define GPIO_BRR_BR4 GPIO_BRR_BR4_Msk /*!< Port x Reset bit 4 */
+#define GPIO_BRR_BR5_Pos (5U)
+#define GPIO_BRR_BR5_Msk (0x1U << GPIO_BRR_BR5_Pos) /*!< 0x00000020 */
+#define GPIO_BRR_BR5 GPIO_BRR_BR5_Msk /*!< Port x Reset bit 5 */
+#define GPIO_BRR_BR6_Pos (6U)
+#define GPIO_BRR_BR6_Msk (0x1U << GPIO_BRR_BR6_Pos) /*!< 0x00000040 */
+#define GPIO_BRR_BR6 GPIO_BRR_BR6_Msk /*!< Port x Reset bit 6 */
+#define GPIO_BRR_BR7_Pos (7U)
+#define GPIO_BRR_BR7_Msk (0x1U << GPIO_BRR_BR7_Pos) /*!< 0x00000080 */
+#define GPIO_BRR_BR7 GPIO_BRR_BR7_Msk /*!< Port x Reset bit 7 */
+#define GPIO_BRR_BR8_Pos (8U)
+#define GPIO_BRR_BR8_Msk (0x1U << GPIO_BRR_BR8_Pos) /*!< 0x00000100 */
+#define GPIO_BRR_BR8 GPIO_BRR_BR8_Msk /*!< Port x Reset bit 8 */
+#define GPIO_BRR_BR9_Pos (9U)
+#define GPIO_BRR_BR9_Msk (0x1U << GPIO_BRR_BR9_Pos) /*!< 0x00000200 */
+#define GPIO_BRR_BR9 GPIO_BRR_BR9_Msk /*!< Port x Reset bit 9 */
+#define GPIO_BRR_BR10_Pos (10U)
+#define GPIO_BRR_BR10_Msk (0x1U << GPIO_BRR_BR10_Pos) /*!< 0x00000400 */
+#define GPIO_BRR_BR10 GPIO_BRR_BR10_Msk /*!< Port x Reset bit 10 */
+#define GPIO_BRR_BR11_Pos (11U)
+#define GPIO_BRR_BR11_Msk (0x1U << GPIO_BRR_BR11_Pos) /*!< 0x00000800 */
+#define GPIO_BRR_BR11 GPIO_BRR_BR11_Msk /*!< Port x Reset bit 11 */
+#define GPIO_BRR_BR12_Pos (12U)
+#define GPIO_BRR_BR12_Msk (0x1U << GPIO_BRR_BR12_Pos) /*!< 0x00001000 */
+#define GPIO_BRR_BR12 GPIO_BRR_BR12_Msk /*!< Port x Reset bit 12 */
+#define GPIO_BRR_BR13_Pos (13U)
+#define GPIO_BRR_BR13_Msk (0x1U << GPIO_BRR_BR13_Pos) /*!< 0x00002000 */
+#define GPIO_BRR_BR13 GPIO_BRR_BR13_Msk /*!< Port x Reset bit 13 */
+#define GPIO_BRR_BR14_Pos (14U)
+#define GPIO_BRR_BR14_Msk (0x1U << GPIO_BRR_BR14_Pos) /*!< 0x00004000 */
+#define GPIO_BRR_BR14 GPIO_BRR_BR14_Msk /*!< Port x Reset bit 14 */
+#define GPIO_BRR_BR15_Pos (15U)
+#define GPIO_BRR_BR15_Msk (0x1U << GPIO_BRR_BR15_Pos) /*!< 0x00008000 */
+#define GPIO_BRR_BR15 GPIO_BRR_BR15_Msk /*!< Port x Reset bit 15 */
+
+/****************** Bit definition for GPIO_LCKR register *******************/
+#define GPIO_LCKR_LCK0_Pos (0U)
+#define GPIO_LCKR_LCK0_Msk (0x1U << GPIO_LCKR_LCK0_Pos) /*!< 0x00000001 */
+#define GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk /*!< Port x Lock bit 0 */
+#define GPIO_LCKR_LCK1_Pos (1U)
+#define GPIO_LCKR_LCK1_Msk (0x1U << GPIO_LCKR_LCK1_Pos) /*!< 0x00000002 */
+#define GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk /*!< Port x Lock bit 1 */
+#define GPIO_LCKR_LCK2_Pos (2U)
+#define GPIO_LCKR_LCK2_Msk (0x1U << GPIO_LCKR_LCK2_Pos) /*!< 0x00000004 */
+#define GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk /*!< Port x Lock bit 2 */
+#define GPIO_LCKR_LCK3_Pos (3U)
+#define GPIO_LCKR_LCK3_Msk (0x1U << GPIO_LCKR_LCK3_Pos) /*!< 0x00000008 */
+#define GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk /*!< Port x Lock bit 3 */
+#define GPIO_LCKR_LCK4_Pos (4U)
+#define GPIO_LCKR_LCK4_Msk (0x1U << GPIO_LCKR_LCK4_Pos) /*!< 0x00000010 */
+#define GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk /*!< Port x Lock bit 4 */
+#define GPIO_LCKR_LCK5_Pos (5U)
+#define GPIO_LCKR_LCK5_Msk (0x1U << GPIO_LCKR_LCK5_Pos) /*!< 0x00000020 */
+#define GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk /*!< Port x Lock bit 5 */
+#define GPIO_LCKR_LCK6_Pos (6U)
+#define GPIO_LCKR_LCK6_Msk (0x1U << GPIO_LCKR_LCK6_Pos) /*!< 0x00000040 */
+#define GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk /*!< Port x Lock bit 6 */
+#define GPIO_LCKR_LCK7_Pos (7U)
+#define GPIO_LCKR_LCK7_Msk (0x1U << GPIO_LCKR_LCK7_Pos) /*!< 0x00000080 */
+#define GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk /*!< Port x Lock bit 7 */
+#define GPIO_LCKR_LCK8_Pos (8U)
+#define GPIO_LCKR_LCK8_Msk (0x1U << GPIO_LCKR_LCK8_Pos) /*!< 0x00000100 */
+#define GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk /*!< Port x Lock bit 8 */
+#define GPIO_LCKR_LCK9_Pos (9U)
+#define GPIO_LCKR_LCK9_Msk (0x1U << GPIO_LCKR_LCK9_Pos) /*!< 0x00000200 */
+#define GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk /*!< Port x Lock bit 9 */
+#define GPIO_LCKR_LCK10_Pos (10U)
+#define GPIO_LCKR_LCK10_Msk (0x1U << GPIO_LCKR_LCK10_Pos) /*!< 0x00000400 */
+#define GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk /*!< Port x Lock bit 10 */
+#define GPIO_LCKR_LCK11_Pos (11U)
+#define GPIO_LCKR_LCK11_Msk (0x1U << GPIO_LCKR_LCK11_Pos) /*!< 0x00000800 */
+#define GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk /*!< Port x Lock bit 11 */
+#define GPIO_LCKR_LCK12_Pos (12U)
+#define GPIO_LCKR_LCK12_Msk (0x1U << GPIO_LCKR_LCK12_Pos) /*!< 0x00001000 */
+#define GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk /*!< Port x Lock bit 12 */
+#define GPIO_LCKR_LCK13_Pos (13U)
+#define GPIO_LCKR_LCK13_Msk (0x1U << GPIO_LCKR_LCK13_Pos) /*!< 0x00002000 */
+#define GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk /*!< Port x Lock bit 13 */
+#define GPIO_LCKR_LCK14_Pos (14U)
+#define GPIO_LCKR_LCK14_Msk (0x1U << GPIO_LCKR_LCK14_Pos) /*!< 0x00004000 */
+#define GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk /*!< Port x Lock bit 14 */
+#define GPIO_LCKR_LCK15_Pos (15U)
+#define GPIO_LCKR_LCK15_Msk (0x1U << GPIO_LCKR_LCK15_Pos) /*!< 0x00008000 */
+#define GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk /*!< Port x Lock bit 15 */
+#define GPIO_LCKR_LCKK_Pos (16U)
+#define GPIO_LCKR_LCKK_Msk (0x1U << GPIO_LCKR_LCKK_Pos) /*!< 0x00010000 */
+#define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk /*!< Lock key */
+
+/*----------------------------------------------------------------------------*/
+
+/****************** Bit definition for AFIO_EVCR register *******************/
+#define AFIO_EVCR_PIN_Pos (0U)
+#define AFIO_EVCR_PIN_Msk (0xFU << AFIO_EVCR_PIN_Pos) /*!< 0x0000000F */
+#define AFIO_EVCR_PIN AFIO_EVCR_PIN_Msk /*!< PIN[3:0] bits (Pin selection) */
+#define AFIO_EVCR_PIN_0 (0x1U << AFIO_EVCR_PIN_Pos) /*!< 0x00000001 */
+#define AFIO_EVCR_PIN_1 (0x2U << AFIO_EVCR_PIN_Pos) /*!< 0x00000002 */
+#define AFIO_EVCR_PIN_2 (0x4U << AFIO_EVCR_PIN_Pos) /*!< 0x00000004 */
+#define AFIO_EVCR_PIN_3 (0x8U << AFIO_EVCR_PIN_Pos) /*!< 0x00000008 */
+
+/*!< PIN configuration */
+#define AFIO_EVCR_PIN_PX0 ((uint32_t)0x00000000) /*!< Pin 0 selected */
+#define AFIO_EVCR_PIN_PX1_Pos (0U)
+#define AFIO_EVCR_PIN_PX1_Msk (0x1U << AFIO_EVCR_PIN_PX1_Pos) /*!< 0x00000001 */
+#define AFIO_EVCR_PIN_PX1 AFIO_EVCR_PIN_PX1_Msk /*!< Pin 1 selected */
+#define AFIO_EVCR_PIN_PX2_Pos (1U)
+#define AFIO_EVCR_PIN_PX2_Msk (0x1U << AFIO_EVCR_PIN_PX2_Pos) /*!< 0x00000002 */
+#define AFIO_EVCR_PIN_PX2 AFIO_EVCR_PIN_PX2_Msk /*!< Pin 2 selected */
+#define AFIO_EVCR_PIN_PX3_Pos (0U)
+#define AFIO_EVCR_PIN_PX3_Msk (0x3U << AFIO_EVCR_PIN_PX3_Pos) /*!< 0x00000003 */
+#define AFIO_EVCR_PIN_PX3 AFIO_EVCR_PIN_PX3_Msk /*!< Pin 3 selected */
+#define AFIO_EVCR_PIN_PX4_Pos (2U)
+#define AFIO_EVCR_PIN_PX4_Msk (0x1U << AFIO_EVCR_PIN_PX4_Pos) /*!< 0x00000004 */
+#define AFIO_EVCR_PIN_PX4 AFIO_EVCR_PIN_PX4_Msk /*!< Pin 4 selected */
+#define AFIO_EVCR_PIN_PX5_Pos (0U)
+#define AFIO_EVCR_PIN_PX5_Msk (0x5U << AFIO_EVCR_PIN_PX5_Pos) /*!< 0x00000005 */
+#define AFIO_EVCR_PIN_PX5 AFIO_EVCR_PIN_PX5_Msk /*!< Pin 5 selected */
+#define AFIO_EVCR_PIN_PX6_Pos (1U)
+#define AFIO_EVCR_PIN_PX6_Msk (0x3U << AFIO_EVCR_PIN_PX6_Pos) /*!< 0x00000006 */
+#define AFIO_EVCR_PIN_PX6 AFIO_EVCR_PIN_PX6_Msk /*!< Pin 6 selected */
+#define AFIO_EVCR_PIN_PX7_Pos (0U)
+#define AFIO_EVCR_PIN_PX7_Msk (0x7U << AFIO_EVCR_PIN_PX7_Pos) /*!< 0x00000007 */
+#define AFIO_EVCR_PIN_PX7 AFIO_EVCR_PIN_PX7_Msk /*!< Pin 7 selected */
+#define AFIO_EVCR_PIN_PX8_Pos (3U)
+#define AFIO_EVCR_PIN_PX8_Msk (0x1U << AFIO_EVCR_PIN_PX8_Pos) /*!< 0x00000008 */
+#define AFIO_EVCR_PIN_PX8 AFIO_EVCR_PIN_PX8_Msk /*!< Pin 8 selected */
+#define AFIO_EVCR_PIN_PX9_Pos (0U)
+#define AFIO_EVCR_PIN_PX9_Msk (0x9U << AFIO_EVCR_PIN_PX9_Pos) /*!< 0x00000009 */
+#define AFIO_EVCR_PIN_PX9 AFIO_EVCR_PIN_PX9_Msk /*!< Pin 9 selected */
+#define AFIO_EVCR_PIN_PX10_Pos (1U)
+#define AFIO_EVCR_PIN_PX10_Msk (0x5U << AFIO_EVCR_PIN_PX10_Pos) /*!< 0x0000000A */
+#define AFIO_EVCR_PIN_PX10 AFIO_EVCR_PIN_PX10_Msk /*!< Pin 10 selected */
+#define AFIO_EVCR_PIN_PX11_Pos (0U)
+#define AFIO_EVCR_PIN_PX11_Msk (0xBU << AFIO_EVCR_PIN_PX11_Pos) /*!< 0x0000000B */
+#define AFIO_EVCR_PIN_PX11 AFIO_EVCR_PIN_PX11_Msk /*!< Pin 11 selected */
+#define AFIO_EVCR_PIN_PX12_Pos (2U)
+#define AFIO_EVCR_PIN_PX12_Msk (0x3U << AFIO_EVCR_PIN_PX12_Pos) /*!< 0x0000000C */
+#define AFIO_EVCR_PIN_PX12 AFIO_EVCR_PIN_PX12_Msk /*!< Pin 12 selected */
+#define AFIO_EVCR_PIN_PX13_Pos (0U)
+#define AFIO_EVCR_PIN_PX13_Msk (0xDU << AFIO_EVCR_PIN_PX13_Pos) /*!< 0x0000000D */
+#define AFIO_EVCR_PIN_PX13 AFIO_EVCR_PIN_PX13_Msk /*!< Pin 13 selected */
+#define AFIO_EVCR_PIN_PX14_Pos (1U)
+#define AFIO_EVCR_PIN_PX14_Msk (0x7U << AFIO_EVCR_PIN_PX14_Pos) /*!< 0x0000000E */
+#define AFIO_EVCR_PIN_PX14 AFIO_EVCR_PIN_PX14_Msk /*!< Pin 14 selected */
+#define AFIO_EVCR_PIN_PX15_Pos (0U)
+#define AFIO_EVCR_PIN_PX15_Msk (0xFU << AFIO_EVCR_PIN_PX15_Pos) /*!< 0x0000000F */
+#define AFIO_EVCR_PIN_PX15 AFIO_EVCR_PIN_PX15_Msk /*!< Pin 15 selected */
+
+#define AFIO_EVCR_PORT_Pos (4U)
+#define AFIO_EVCR_PORT_Msk (0x7U << AFIO_EVCR_PORT_Pos) /*!< 0x00000070 */
+#define AFIO_EVCR_PORT AFIO_EVCR_PORT_Msk /*!< PORT[2:0] bits (Port selection) */
+#define AFIO_EVCR_PORT_0 (0x1U << AFIO_EVCR_PORT_Pos) /*!< 0x00000010 */
+#define AFIO_EVCR_PORT_1 (0x2U << AFIO_EVCR_PORT_Pos) /*!< 0x00000020 */
+#define AFIO_EVCR_PORT_2 (0x4U << AFIO_EVCR_PORT_Pos) /*!< 0x00000040 */
+
+/*!< PORT configuration */
+#define AFIO_EVCR_PORT_PA ((uint32_t)0x00000000) /*!< Port A selected */
+#define AFIO_EVCR_PORT_PB_Pos (4U)
+#define AFIO_EVCR_PORT_PB_Msk (0x1U << AFIO_EVCR_PORT_PB_Pos) /*!< 0x00000010 */
+#define AFIO_EVCR_PORT_PB AFIO_EVCR_PORT_PB_Msk /*!< Port B selected */
+#define AFIO_EVCR_PORT_PC_Pos (5U)
+#define AFIO_EVCR_PORT_PC_Msk (0x1U << AFIO_EVCR_PORT_PC_Pos) /*!< 0x00000020 */
+#define AFIO_EVCR_PORT_PC AFIO_EVCR_PORT_PC_Msk /*!< Port C selected */
+#define AFIO_EVCR_PORT_PD_Pos (4U)
+#define AFIO_EVCR_PORT_PD_Msk (0x3U << AFIO_EVCR_PORT_PD_Pos) /*!< 0x00000030 */
+#define AFIO_EVCR_PORT_PD AFIO_EVCR_PORT_PD_Msk /*!< Port D selected */
+#define AFIO_EVCR_PORT_PE_Pos (6U)
+#define AFIO_EVCR_PORT_PE_Msk (0x1U << AFIO_EVCR_PORT_PE_Pos) /*!< 0x00000040 */
+#define AFIO_EVCR_PORT_PE AFIO_EVCR_PORT_PE_Msk /*!< Port E selected */
+
+#define AFIO_EVCR_EVOE_Pos (7U)
+#define AFIO_EVCR_EVOE_Msk (0x1U << AFIO_EVCR_EVOE_Pos) /*!< 0x00000080 */
+#define AFIO_EVCR_EVOE AFIO_EVCR_EVOE_Msk /*!< Event Output Enable */
+
+/****************** Bit definition for AFIO_MAPR register *******************/
+#define AFIO_MAPR_SPI1_REMAP_Pos (0U)
+#define AFIO_MAPR_SPI1_REMAP_Msk (0x1U << AFIO_MAPR_SPI1_REMAP_Pos) /*!< 0x00000001 */
+#define AFIO_MAPR_SPI1_REMAP AFIO_MAPR_SPI1_REMAP_Msk /*!< SPI1 remapping */
+#define AFIO_MAPR_I2C1_REMAP_Pos (1U)
+#define AFIO_MAPR_I2C1_REMAP_Msk (0x1U << AFIO_MAPR_I2C1_REMAP_Pos) /*!< 0x00000002 */
+#define AFIO_MAPR_I2C1_REMAP AFIO_MAPR_I2C1_REMAP_Msk /*!< I2C1 remapping */
+#define AFIO_MAPR_USART1_REMAP_Pos (2U)
+#define AFIO_MAPR_USART1_REMAP_Msk (0x1U << AFIO_MAPR_USART1_REMAP_Pos) /*!< 0x00000004 */
+#define AFIO_MAPR_USART1_REMAP AFIO_MAPR_USART1_REMAP_Msk /*!< USART1 remapping */
+#define AFIO_MAPR_USART2_REMAP_Pos (3U)
+#define AFIO_MAPR_USART2_REMAP_Msk (0x1U << AFIO_MAPR_USART2_REMAP_Pos) /*!< 0x00000008 */
+#define AFIO_MAPR_USART2_REMAP AFIO_MAPR_USART2_REMAP_Msk /*!< USART2 remapping */
+
+#define AFIO_MAPR_USART3_REMAP_Pos (4U)
+#define AFIO_MAPR_USART3_REMAP_Msk (0x3U << AFIO_MAPR_USART3_REMAP_Pos) /*!< 0x00000030 */
+#define AFIO_MAPR_USART3_REMAP AFIO_MAPR_USART3_REMAP_Msk /*!< USART3_REMAP[1:0] bits (USART3 remapping) */
+#define AFIO_MAPR_USART3_REMAP_0 (0x1U << AFIO_MAPR_USART3_REMAP_Pos) /*!< 0x00000010 */
+#define AFIO_MAPR_USART3_REMAP_1 (0x2U << AFIO_MAPR_USART3_REMAP_Pos) /*!< 0x00000020 */
+
+/* USART3_REMAP configuration */
+#define AFIO_MAPR_USART3_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14) */
+#define AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Pos (4U)
+#define AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Msk (0x1U << AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Pos) /*!< 0x00000010 */
+#define AFIO_MAPR_USART3_REMAP_PARTIALREMAP AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Msk /*!< Partial remap (TX/PC10, RX/PC11, CK/PC12, CTS/PB13, RTS/PB14) */
+#define AFIO_MAPR_USART3_REMAP_FULLREMAP_Pos (4U)
+#define AFIO_MAPR_USART3_REMAP_FULLREMAP_Msk (0x3U << AFIO_MAPR_USART3_REMAP_FULLREMAP_Pos) /*!< 0x00000030 */
+#define AFIO_MAPR_USART3_REMAP_FULLREMAP AFIO_MAPR_USART3_REMAP_FULLREMAP_Msk /*!< Full remap (TX/PD8, RX/PD9, CK/PD10, CTS/PD11, RTS/PD12) */
+
+#define AFIO_MAPR_TIM1_REMAP_Pos (6U)
+#define AFIO_MAPR_TIM1_REMAP_Msk (0x3U << AFIO_MAPR_TIM1_REMAP_Pos) /*!< 0x000000C0 */
+#define AFIO_MAPR_TIM1_REMAP AFIO_MAPR_TIM1_REMAP_Msk /*!< TIM1_REMAP[1:0] bits (TIM1 remapping) */
+#define AFIO_MAPR_TIM1_REMAP_0 (0x1U << AFIO_MAPR_TIM1_REMAP_Pos) /*!< 0x00000040 */
+#define AFIO_MAPR_TIM1_REMAP_1 (0x2U << AFIO_MAPR_TIM1_REMAP_Pos) /*!< 0x00000080 */
+
+/*!< TIM1_REMAP configuration */
+#define AFIO_MAPR_TIM1_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15) */
+#define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Pos (6U)
+#define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Msk (0x1U << AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Pos) /*!< 0x00000040 */
+#define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Msk /*!< Partial remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PA6, CH1N/PA7, CH2N/PB0, CH3N/PB1) */
+#define AFIO_MAPR_TIM1_REMAP_FULLREMAP_Pos (6U)
+#define AFIO_MAPR_TIM1_REMAP_FULLREMAP_Msk (0x3U << AFIO_MAPR_TIM1_REMAP_FULLREMAP_Pos) /*!< 0x000000C0 */
+#define AFIO_MAPR_TIM1_REMAP_FULLREMAP AFIO_MAPR_TIM1_REMAP_FULLREMAP_Msk /*!< Full remap (ETR/PE7, CH1/PE9, CH2/PE11, CH3/PE13, CH4/PE14, BKIN/PE15, CH1N/PE8, CH2N/PE10, CH3N/PE12) */
+
+#define AFIO_MAPR_TIM2_REMAP_Pos (8U)
+#define AFIO_MAPR_TIM2_REMAP_Msk (0x3U << AFIO_MAPR_TIM2_REMAP_Pos) /*!< 0x00000300 */
+#define AFIO_MAPR_TIM2_REMAP AFIO_MAPR_TIM2_REMAP_Msk /*!< TIM2_REMAP[1:0] bits (TIM2 remapping) */
+#define AFIO_MAPR_TIM2_REMAP_0 (0x1U << AFIO_MAPR_TIM2_REMAP_Pos) /*!< 0x00000100 */
+#define AFIO_MAPR_TIM2_REMAP_1 (0x2U << AFIO_MAPR_TIM2_REMAP_Pos) /*!< 0x00000200 */
+
+/*!< TIM2_REMAP configuration */
+#define AFIO_MAPR_TIM2_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3) */
+#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Pos (8U)
+#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Msk (0x1U << AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Pos) /*!< 0x00000100 */
+#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1 AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Msk /*!< Partial remap (CH1/ETR/PA15, CH2/PB3, CH3/PA2, CH4/PA3) */
+#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2_Pos (9U)
+#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2_Msk (0x1U << AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2_Pos) /*!< 0x00000200 */
+#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2 AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2_Msk /*!< Partial remap (CH1/ETR/PA0, CH2/PA1, CH3/PB10, CH4/PB11) */
+#define AFIO_MAPR_TIM2_REMAP_FULLREMAP_Pos (8U)
+#define AFIO_MAPR_TIM2_REMAP_FULLREMAP_Msk (0x3U << AFIO_MAPR_TIM2_REMAP_FULLREMAP_Pos) /*!< 0x00000300 */
+#define AFIO_MAPR_TIM2_REMAP_FULLREMAP AFIO_MAPR_TIM2_REMAP_FULLREMAP_Msk /*!< Full remap (CH1/ETR/PA15, CH2/PB3, CH3/PB10, CH4/PB11) */
+
+#define AFIO_MAPR_TIM3_REMAP_Pos (10U)
+#define AFIO_MAPR_TIM3_REMAP_Msk (0x3U << AFIO_MAPR_TIM3_REMAP_Pos) /*!< 0x00000C00 */
+#define AFIO_MAPR_TIM3_REMAP AFIO_MAPR_TIM3_REMAP_Msk /*!< TIM3_REMAP[1:0] bits (TIM3 remapping) */
+#define AFIO_MAPR_TIM3_REMAP_0 (0x1U << AFIO_MAPR_TIM3_REMAP_Pos) /*!< 0x00000400 */
+#define AFIO_MAPR_TIM3_REMAP_1 (0x2U << AFIO_MAPR_TIM3_REMAP_Pos) /*!< 0x00000800 */
+
+/*!< TIM3_REMAP configuration */
+#define AFIO_MAPR_TIM3_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1) */
+#define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Pos (11U)
+#define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Msk (0x1U << AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Pos) /*!< 0x00000800 */
+#define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Msk /*!< Partial remap (CH1/PB4, CH2/PB5, CH3/PB0, CH4/PB1) */
+#define AFIO_MAPR_TIM3_REMAP_FULLREMAP_Pos (10U)
+#define AFIO_MAPR_TIM3_REMAP_FULLREMAP_Msk (0x3U << AFIO_MAPR_TIM3_REMAP_FULLREMAP_Pos) /*!< 0x00000C00 */
+#define AFIO_MAPR_TIM3_REMAP_FULLREMAP AFIO_MAPR_TIM3_REMAP_FULLREMAP_Msk /*!< Full remap (CH1/PC6, CH2/PC7, CH3/PC8, CH4/PC9) */
+
+#define AFIO_MAPR_TIM4_REMAP_Pos (12U)
+#define AFIO_MAPR_TIM4_REMAP_Msk (0x1U << AFIO_MAPR_TIM4_REMAP_Pos) /*!< 0x00001000 */
+#define AFIO_MAPR_TIM4_REMAP AFIO_MAPR_TIM4_REMAP_Msk /*!< TIM4_REMAP bit (TIM4 remapping) */
+
+
+#define AFIO_MAPR_PD01_REMAP_Pos (15U)
+#define AFIO_MAPR_PD01_REMAP_Msk (0x1U << AFIO_MAPR_PD01_REMAP_Pos) /*!< 0x00008000 */
+#define AFIO_MAPR_PD01_REMAP AFIO_MAPR_PD01_REMAP_Msk /*!< Port D0/Port D1 mapping on OSC_IN/OSC_OUT */
+
+/*!< SWJ_CFG configuration */
+#define AFIO_MAPR_SWJ_CFG_Pos (24U)
+#define AFIO_MAPR_SWJ_CFG_Msk (0x7U << AFIO_MAPR_SWJ_CFG_Pos) /*!< 0x07000000 */
+#define AFIO_MAPR_SWJ_CFG AFIO_MAPR_SWJ_CFG_Msk /*!< SWJ_CFG[2:0] bits (Serial Wire JTAG configuration) */
+#define AFIO_MAPR_SWJ_CFG_0 (0x1U << AFIO_MAPR_SWJ_CFG_Pos) /*!< 0x01000000 */
+#define AFIO_MAPR_SWJ_CFG_1 (0x2U << AFIO_MAPR_SWJ_CFG_Pos) /*!< 0x02000000 */
+#define AFIO_MAPR_SWJ_CFG_2 (0x4U << AFIO_MAPR_SWJ_CFG_Pos) /*!< 0x04000000 */
+
+#define AFIO_MAPR_SWJ_CFG_RESET ((uint32_t)0x00000000) /*!< Full SWJ (JTAG-DP + SW-DP) : Reset State */
+#define AFIO_MAPR_SWJ_CFG_NOJNTRST_Pos (24U)
+#define AFIO_MAPR_SWJ_CFG_NOJNTRST_Msk (0x1U << AFIO_MAPR_SWJ_CFG_NOJNTRST_Pos) /*!< 0x01000000 */
+#define AFIO_MAPR_SWJ_CFG_NOJNTRST AFIO_MAPR_SWJ_CFG_NOJNTRST_Msk /*!< Full SWJ (JTAG-DP + SW-DP) but without JNTRST */
+#define AFIO_MAPR_SWJ_CFG_JTAGDISABLE_Pos (25U)
+#define AFIO_MAPR_SWJ_CFG_JTAGDISABLE_Msk (0x1U << AFIO_MAPR_SWJ_CFG_JTAGDISABLE_Pos) /*!< 0x02000000 */
+#define AFIO_MAPR_SWJ_CFG_JTAGDISABLE AFIO_MAPR_SWJ_CFG_JTAGDISABLE_Msk /*!< JTAG-DP Disabled and SW-DP Enabled */
+#define AFIO_MAPR_SWJ_CFG_DISABLE_Pos (26U)
+#define AFIO_MAPR_SWJ_CFG_DISABLE_Msk (0x1U << AFIO_MAPR_SWJ_CFG_DISABLE_Pos) /*!< 0x04000000 */
+#define AFIO_MAPR_SWJ_CFG_DISABLE AFIO_MAPR_SWJ_CFG_DISABLE_Msk /*!< JTAG-DP Disabled and SW-DP Disabled */
+
+
+/***************** Bit definition for AFIO_EXTICR1 register *****************/
+#define AFIO_EXTICR1_EXTI0_Pos (0U)
+#define AFIO_EXTICR1_EXTI0_Msk (0xFU << AFIO_EXTICR1_EXTI0_Pos) /*!< 0x0000000F */
+#define AFIO_EXTICR1_EXTI0 AFIO_EXTICR1_EXTI0_Msk /*!< EXTI 0 configuration */
+#define AFIO_EXTICR1_EXTI1_Pos (4U)
+#define AFIO_EXTICR1_EXTI1_Msk (0xFU << AFIO_EXTICR1_EXTI1_Pos) /*!< 0x000000F0 */
+#define AFIO_EXTICR1_EXTI1 AFIO_EXTICR1_EXTI1_Msk /*!< EXTI 1 configuration */
+#define AFIO_EXTICR1_EXTI2_Pos (8U)
+#define AFIO_EXTICR1_EXTI2_Msk (0xFU << AFIO_EXTICR1_EXTI2_Pos) /*!< 0x00000F00 */
+#define AFIO_EXTICR1_EXTI2 AFIO_EXTICR1_EXTI2_Msk /*!< EXTI 2 configuration */
+#define AFIO_EXTICR1_EXTI3_Pos (12U)
+#define AFIO_EXTICR1_EXTI3_Msk (0xFU << AFIO_EXTICR1_EXTI3_Pos) /*!< 0x0000F000 */
+#define AFIO_EXTICR1_EXTI3 AFIO_EXTICR1_EXTI3_Msk /*!< EXTI 3 configuration */
+
+/*!< EXTI0 configuration */
+#define AFIO_EXTICR1_EXTI0_PA ((uint32_t)0x00000000) /*!< PA[0] pin */
+#define AFIO_EXTICR1_EXTI0_PB_Pos (0U)
+#define AFIO_EXTICR1_EXTI0_PB_Msk (0x1U << AFIO_EXTICR1_EXTI0_PB_Pos) /*!< 0x00000001 */
+#define AFIO_EXTICR1_EXTI0_PB AFIO_EXTICR1_EXTI0_PB_Msk /*!< PB[0] pin */
+#define AFIO_EXTICR1_EXTI0_PC_Pos (1U)
+#define AFIO_EXTICR1_EXTI0_PC_Msk (0x1U << AFIO_EXTICR1_EXTI0_PC_Pos) /*!< 0x00000002 */
+#define AFIO_EXTICR1_EXTI0_PC AFIO_EXTICR1_EXTI0_PC_Msk /*!< PC[0] pin */
+#define AFIO_EXTICR1_EXTI0_PD_Pos (0U)
+#define AFIO_EXTICR1_EXTI0_PD_Msk (0x3U << AFIO_EXTICR1_EXTI0_PD_Pos) /*!< 0x00000003 */
+#define AFIO_EXTICR1_EXTI0_PD AFIO_EXTICR1_EXTI0_PD_Msk /*!< PD[0] pin */
+#define AFIO_EXTICR1_EXTI0_PE_Pos (2U)
+#define AFIO_EXTICR1_EXTI0_PE_Msk (0x1U << AFIO_EXTICR1_EXTI0_PE_Pos) /*!< 0x00000004 */
+#define AFIO_EXTICR1_EXTI0_PE AFIO_EXTICR1_EXTI0_PE_Msk /*!< PE[0] pin */
+#define AFIO_EXTICR1_EXTI0_PF_Pos (0U)
+#define AFIO_EXTICR1_EXTI0_PF_Msk (0x5U << AFIO_EXTICR1_EXTI0_PF_Pos) /*!< 0x00000005 */
+#define AFIO_EXTICR1_EXTI0_PF AFIO_EXTICR1_EXTI0_PF_Msk /*!< PF[0] pin */
+#define AFIO_EXTICR1_EXTI0_PG_Pos (1U)
+#define AFIO_EXTICR1_EXTI0_PG_Msk (0x3U << AFIO_EXTICR1_EXTI0_PG_Pos) /*!< 0x00000006 */
+#define AFIO_EXTICR1_EXTI0_PG AFIO_EXTICR1_EXTI0_PG_Msk /*!< PG[0] pin */
+
+/*!< EXTI1 configuration */
+#define AFIO_EXTICR1_EXTI1_PA ((uint32_t)0x00000000) /*!< PA[1] pin */
+#define AFIO_EXTICR1_EXTI1_PB_Pos (4U)
+#define AFIO_EXTICR1_EXTI1_PB_Msk (0x1U << AFIO_EXTICR1_EXTI1_PB_Pos) /*!< 0x00000010 */
+#define AFIO_EXTICR1_EXTI1_PB AFIO_EXTICR1_EXTI1_PB_Msk /*!< PB[1] pin */
+#define AFIO_EXTICR1_EXTI1_PC_Pos (5U)
+#define AFIO_EXTICR1_EXTI1_PC_Msk (0x1U << AFIO_EXTICR1_EXTI1_PC_Pos) /*!< 0x00000020 */
+#define AFIO_EXTICR1_EXTI1_PC AFIO_EXTICR1_EXTI1_PC_Msk /*!< PC[1] pin */
+#define AFIO_EXTICR1_EXTI1_PD_Pos (4U)
+#define AFIO_EXTICR1_EXTI1_PD_Msk (0x3U << AFIO_EXTICR1_EXTI1_PD_Pos) /*!< 0x00000030 */
+#define AFIO_EXTICR1_EXTI1_PD AFIO_EXTICR1_EXTI1_PD_Msk /*!< PD[1] pin */
+#define AFIO_EXTICR1_EXTI1_PE_Pos (6U)
+#define AFIO_EXTICR1_EXTI1_PE_Msk (0x1U << AFIO_EXTICR1_EXTI1_PE_Pos) /*!< 0x00000040 */
+#define AFIO_EXTICR1_EXTI1_PE AFIO_EXTICR1_EXTI1_PE_Msk /*!< PE[1] pin */
+#define AFIO_EXTICR1_EXTI1_PF_Pos (4U)
+#define AFIO_EXTICR1_EXTI1_PF_Msk (0x5U << AFIO_EXTICR1_EXTI1_PF_Pos) /*!< 0x00000050 */
+#define AFIO_EXTICR1_EXTI1_PF AFIO_EXTICR1_EXTI1_PF_Msk /*!< PF[1] pin */
+#define AFIO_EXTICR1_EXTI1_PG_Pos (5U)
+#define AFIO_EXTICR1_EXTI1_PG_Msk (0x3U << AFIO_EXTICR1_EXTI1_PG_Pos) /*!< 0x00000060 */
+#define AFIO_EXTICR1_EXTI1_PG AFIO_EXTICR1_EXTI1_PG_Msk /*!< PG[1] pin */
+
+/*!< EXTI2 configuration */
+#define AFIO_EXTICR1_EXTI2_PA ((uint32_t)0x00000000) /*!< PA[2] pin */
+#define AFIO_EXTICR1_EXTI2_PB_Pos (8U)
+#define AFIO_EXTICR1_EXTI2_PB_Msk (0x1U << AFIO_EXTICR1_EXTI2_PB_Pos) /*!< 0x00000100 */
+#define AFIO_EXTICR1_EXTI2_PB AFIO_EXTICR1_EXTI2_PB_Msk /*!< PB[2] pin */
+#define AFIO_EXTICR1_EXTI2_PC_Pos (9U)
+#define AFIO_EXTICR1_EXTI2_PC_Msk (0x1U << AFIO_EXTICR1_EXTI2_PC_Pos) /*!< 0x00000200 */
+#define AFIO_EXTICR1_EXTI2_PC AFIO_EXTICR1_EXTI2_PC_Msk /*!< PC[2] pin */
+#define AFIO_EXTICR1_EXTI2_PD_Pos (8U)
+#define AFIO_EXTICR1_EXTI2_PD_Msk (0x3U << AFIO_EXTICR1_EXTI2_PD_Pos) /*!< 0x00000300 */
+#define AFIO_EXTICR1_EXTI2_PD AFIO_EXTICR1_EXTI2_PD_Msk /*!< PD[2] pin */
+#define AFIO_EXTICR1_EXTI2_PE_Pos (10U)
+#define AFIO_EXTICR1_EXTI2_PE_Msk (0x1U << AFIO_EXTICR1_EXTI2_PE_Pos) /*!< 0x00000400 */
+#define AFIO_EXTICR1_EXTI2_PE AFIO_EXTICR1_EXTI2_PE_Msk /*!< PE[2] pin */
+#define AFIO_EXTICR1_EXTI2_PF_Pos (8U)
+#define AFIO_EXTICR1_EXTI2_PF_Msk (0x5U << AFIO_EXTICR1_EXTI2_PF_Pos) /*!< 0x00000500 */
+#define AFIO_EXTICR1_EXTI2_PF AFIO_EXTICR1_EXTI2_PF_Msk /*!< PF[2] pin */
+#define AFIO_EXTICR1_EXTI2_PG_Pos (9U)
+#define AFIO_EXTICR1_EXTI2_PG_Msk (0x3U << AFIO_EXTICR1_EXTI2_PG_Pos) /*!< 0x00000600 */
+#define AFIO_EXTICR1_EXTI2_PG AFIO_EXTICR1_EXTI2_PG_Msk /*!< PG[2] pin */
+
+/*!< EXTI3 configuration */
+#define AFIO_EXTICR1_EXTI3_PA ((uint32_t)0x00000000) /*!< PA[3] pin */
+#define AFIO_EXTICR1_EXTI3_PB_Pos (12U)
+#define AFIO_EXTICR1_EXTI3_PB_Msk (0x1U << AFIO_EXTICR1_EXTI3_PB_Pos) /*!< 0x00001000 */
+#define AFIO_EXTICR1_EXTI3_PB AFIO_EXTICR1_EXTI3_PB_Msk /*!< PB[3] pin */
+#define AFIO_EXTICR1_EXTI3_PC_Pos (13U)
+#define AFIO_EXTICR1_EXTI3_PC_Msk (0x1U << AFIO_EXTICR1_EXTI3_PC_Pos) /*!< 0x00002000 */
+#define AFIO_EXTICR1_EXTI3_PC AFIO_EXTICR1_EXTI3_PC_Msk /*!< PC[3] pin */
+#define AFIO_EXTICR1_EXTI3_PD_Pos (12U)
+#define AFIO_EXTICR1_EXTI3_PD_Msk (0x3U << AFIO_EXTICR1_EXTI3_PD_Pos) /*!< 0x00003000 */
+#define AFIO_EXTICR1_EXTI3_PD AFIO_EXTICR1_EXTI3_PD_Msk /*!< PD[3] pin */
+#define AFIO_EXTICR1_EXTI3_PE_Pos (14U)
+#define AFIO_EXTICR1_EXTI3_PE_Msk (0x1U << AFIO_EXTICR1_EXTI3_PE_Pos) /*!< 0x00004000 */
+#define AFIO_EXTICR1_EXTI3_PE AFIO_EXTICR1_EXTI3_PE_Msk /*!< PE[3] pin */
+#define AFIO_EXTICR1_EXTI3_PF_Pos (12U)
+#define AFIO_EXTICR1_EXTI3_PF_Msk (0x5U << AFIO_EXTICR1_EXTI3_PF_Pos) /*!< 0x00005000 */
+#define AFIO_EXTICR1_EXTI3_PF AFIO_EXTICR1_EXTI3_PF_Msk /*!< PF[3] pin */
+#define AFIO_EXTICR1_EXTI3_PG_Pos (13U)
+#define AFIO_EXTICR1_EXTI3_PG_Msk (0x3U << AFIO_EXTICR1_EXTI3_PG_Pos) /*!< 0x00006000 */
+#define AFIO_EXTICR1_EXTI3_PG AFIO_EXTICR1_EXTI3_PG_Msk /*!< PG[3] pin */
+
+/***************** Bit definition for AFIO_EXTICR2 register *****************/
+#define AFIO_EXTICR2_EXTI4_Pos (0U)
+#define AFIO_EXTICR2_EXTI4_Msk (0xFU << AFIO_EXTICR2_EXTI4_Pos) /*!< 0x0000000F */
+#define AFIO_EXTICR2_EXTI4 AFIO_EXTICR2_EXTI4_Msk /*!< EXTI 4 configuration */
+#define AFIO_EXTICR2_EXTI5_Pos (4U)
+#define AFIO_EXTICR2_EXTI5_Msk (0xFU << AFIO_EXTICR2_EXTI5_Pos) /*!< 0x000000F0 */
+#define AFIO_EXTICR2_EXTI5 AFIO_EXTICR2_EXTI5_Msk /*!< EXTI 5 configuration */
+#define AFIO_EXTICR2_EXTI6_Pos (8U)
+#define AFIO_EXTICR2_EXTI6_Msk (0xFU << AFIO_EXTICR2_EXTI6_Pos) /*!< 0x00000F00 */
+#define AFIO_EXTICR2_EXTI6 AFIO_EXTICR2_EXTI6_Msk /*!< EXTI 6 configuration */
+#define AFIO_EXTICR2_EXTI7_Pos (12U)
+#define AFIO_EXTICR2_EXTI7_Msk (0xFU << AFIO_EXTICR2_EXTI7_Pos) /*!< 0x0000F000 */
+#define AFIO_EXTICR2_EXTI7 AFIO_EXTICR2_EXTI7_Msk /*!< EXTI 7 configuration */
+
+/*!< EXTI4 configuration */
+#define AFIO_EXTICR2_EXTI4_PA ((uint32_t)0x00000000) /*!< PA[4] pin */
+#define AFIO_EXTICR2_EXTI4_PB_Pos (0U)
+#define AFIO_EXTICR2_EXTI4_PB_Msk (0x1U << AFIO_EXTICR2_EXTI4_PB_Pos) /*!< 0x00000001 */
+#define AFIO_EXTICR2_EXTI4_PB AFIO_EXTICR2_EXTI4_PB_Msk /*!< PB[4] pin */
+#define AFIO_EXTICR2_EXTI4_PC_Pos (1U)
+#define AFIO_EXTICR2_EXTI4_PC_Msk (0x1U << AFIO_EXTICR2_EXTI4_PC_Pos) /*!< 0x00000002 */
+#define AFIO_EXTICR2_EXTI4_PC AFIO_EXTICR2_EXTI4_PC_Msk /*!< PC[4] pin */
+#define AFIO_EXTICR2_EXTI4_PD_Pos (0U)
+#define AFIO_EXTICR2_EXTI4_PD_Msk (0x3U << AFIO_EXTICR2_EXTI4_PD_Pos) /*!< 0x00000003 */
+#define AFIO_EXTICR2_EXTI4_PD AFIO_EXTICR2_EXTI4_PD_Msk /*!< PD[4] pin */
+#define AFIO_EXTICR2_EXTI4_PE_Pos (2U)
+#define AFIO_EXTICR2_EXTI4_PE_Msk (0x1U << AFIO_EXTICR2_EXTI4_PE_Pos) /*!< 0x00000004 */
+#define AFIO_EXTICR2_EXTI4_PE AFIO_EXTICR2_EXTI4_PE_Msk /*!< PE[4] pin */
+#define AFIO_EXTICR2_EXTI4_PF_Pos (0U)
+#define AFIO_EXTICR2_EXTI4_PF_Msk (0x5U << AFIO_EXTICR2_EXTI4_PF_Pos) /*!< 0x00000005 */
+#define AFIO_EXTICR2_EXTI4_PF AFIO_EXTICR2_EXTI4_PF_Msk /*!< PF[4] pin */
+#define AFIO_EXTICR2_EXTI4_PG_Pos (1U)
+#define AFIO_EXTICR2_EXTI4_PG_Msk (0x3U << AFIO_EXTICR2_EXTI4_PG_Pos) /*!< 0x00000006 */
+#define AFIO_EXTICR2_EXTI4_PG AFIO_EXTICR2_EXTI4_PG_Msk /*!< PG[4] pin */
+
+/* EXTI5 configuration */
+#define AFIO_EXTICR2_EXTI5_PA ((uint32_t)0x00000000) /*!< PA[5] pin */
+#define AFIO_EXTICR2_EXTI5_PB_Pos (4U)
+#define AFIO_EXTICR2_EXTI5_PB_Msk (0x1U << AFIO_EXTICR2_EXTI5_PB_Pos) /*!< 0x00000010 */
+#define AFIO_EXTICR2_EXTI5_PB AFIO_EXTICR2_EXTI5_PB_Msk /*!< PB[5] pin */
+#define AFIO_EXTICR2_EXTI5_PC_Pos (5U)
+#define AFIO_EXTICR2_EXTI5_PC_Msk (0x1U << AFIO_EXTICR2_EXTI5_PC_Pos) /*!< 0x00000020 */
+#define AFIO_EXTICR2_EXTI5_PC AFIO_EXTICR2_EXTI5_PC_Msk /*!< PC[5] pin */
+#define AFIO_EXTICR2_EXTI5_PD_Pos (4U)
+#define AFIO_EXTICR2_EXTI5_PD_Msk (0x3U << AFIO_EXTICR2_EXTI5_PD_Pos) /*!< 0x00000030 */
+#define AFIO_EXTICR2_EXTI5_PD AFIO_EXTICR2_EXTI5_PD_Msk /*!< PD[5] pin */
+#define AFIO_EXTICR2_EXTI5_PE_Pos (6U)
+#define AFIO_EXTICR2_EXTI5_PE_Msk (0x1U << AFIO_EXTICR2_EXTI5_PE_Pos) /*!< 0x00000040 */
+#define AFIO_EXTICR2_EXTI5_PE AFIO_EXTICR2_EXTI5_PE_Msk /*!< PE[5] pin */
+#define AFIO_EXTICR2_EXTI5_PF_Pos (4U)
+#define AFIO_EXTICR2_EXTI5_PF_Msk (0x5U << AFIO_EXTICR2_EXTI5_PF_Pos) /*!< 0x00000050 */
+#define AFIO_EXTICR2_EXTI5_PF AFIO_EXTICR2_EXTI5_PF_Msk /*!< PF[5] pin */
+#define AFIO_EXTICR2_EXTI5_PG_Pos (5U)
+#define AFIO_EXTICR2_EXTI5_PG_Msk (0x3U << AFIO_EXTICR2_EXTI5_PG_Pos) /*!< 0x00000060 */
+#define AFIO_EXTICR2_EXTI5_PG AFIO_EXTICR2_EXTI5_PG_Msk /*!< PG[5] pin */
+
+/*!< EXTI6 configuration */
+#define AFIO_EXTICR2_EXTI6_PA ((uint32_t)0x00000000) /*!< PA[6] pin */
+#define AFIO_EXTICR2_EXTI6_PB_Pos (8U)
+#define AFIO_EXTICR2_EXTI6_PB_Msk (0x1U << AFIO_EXTICR2_EXTI6_PB_Pos) /*!< 0x00000100 */
+#define AFIO_EXTICR2_EXTI6_PB AFIO_EXTICR2_EXTI6_PB_Msk /*!< PB[6] pin */
+#define AFIO_EXTICR2_EXTI6_PC_Pos (9U)
+#define AFIO_EXTICR2_EXTI6_PC_Msk (0x1U << AFIO_EXTICR2_EXTI6_PC_Pos) /*!< 0x00000200 */
+#define AFIO_EXTICR2_EXTI6_PC AFIO_EXTICR2_EXTI6_PC_Msk /*!< PC[6] pin */
+#define AFIO_EXTICR2_EXTI6_PD_Pos (8U)
+#define AFIO_EXTICR2_EXTI6_PD_Msk (0x3U << AFIO_EXTICR2_EXTI6_PD_Pos) /*!< 0x00000300 */
+#define AFIO_EXTICR2_EXTI6_PD AFIO_EXTICR2_EXTI6_PD_Msk /*!< PD[6] pin */
+#define AFIO_EXTICR2_EXTI6_PE_Pos (10U)
+#define AFIO_EXTICR2_EXTI6_PE_Msk (0x1U << AFIO_EXTICR2_EXTI6_PE_Pos) /*!< 0x00000400 */
+#define AFIO_EXTICR2_EXTI6_PE AFIO_EXTICR2_EXTI6_PE_Msk /*!< PE[6] pin */
+#define AFIO_EXTICR2_EXTI6_PF_Pos (8U)
+#define AFIO_EXTICR2_EXTI6_PF_Msk (0x5U << AFIO_EXTICR2_EXTI6_PF_Pos) /*!< 0x00000500 */
+#define AFIO_EXTICR2_EXTI6_PF AFIO_EXTICR2_EXTI6_PF_Msk /*!< PF[6] pin */
+#define AFIO_EXTICR2_EXTI6_PG_Pos (9U)
+#define AFIO_EXTICR2_EXTI6_PG_Msk (0x3U << AFIO_EXTICR2_EXTI6_PG_Pos) /*!< 0x00000600 */
+#define AFIO_EXTICR2_EXTI6_PG AFIO_EXTICR2_EXTI6_PG_Msk /*!< PG[6] pin */
+
+/*!< EXTI7 configuration */
+#define AFIO_EXTICR2_EXTI7_PA ((uint32_t)0x00000000) /*!< PA[7] pin */
+#define AFIO_EXTICR2_EXTI7_PB_Pos (12U)
+#define AFIO_EXTICR2_EXTI7_PB_Msk (0x1U << AFIO_EXTICR2_EXTI7_PB_Pos) /*!< 0x00001000 */
+#define AFIO_EXTICR2_EXTI7_PB AFIO_EXTICR2_EXTI7_PB_Msk /*!< PB[7] pin */
+#define AFIO_EXTICR2_EXTI7_PC_Pos (13U)
+#define AFIO_EXTICR2_EXTI7_PC_Msk (0x1U << AFIO_EXTICR2_EXTI7_PC_Pos) /*!< 0x00002000 */
+#define AFIO_EXTICR2_EXTI7_PC AFIO_EXTICR2_EXTI7_PC_Msk /*!< PC[7] pin */
+#define AFIO_EXTICR2_EXTI7_PD_Pos (12U)
+#define AFIO_EXTICR2_EXTI7_PD_Msk (0x3U << AFIO_EXTICR2_EXTI7_PD_Pos) /*!< 0x00003000 */
+#define AFIO_EXTICR2_EXTI7_PD AFIO_EXTICR2_EXTI7_PD_Msk /*!< PD[7] pin */
+#define AFIO_EXTICR2_EXTI7_PE_Pos (14U)
+#define AFIO_EXTICR2_EXTI7_PE_Msk (0x1U << AFIO_EXTICR2_EXTI7_PE_Pos) /*!< 0x00004000 */
+#define AFIO_EXTICR2_EXTI7_PE AFIO_EXTICR2_EXTI7_PE_Msk /*!< PE[7] pin */
+#define AFIO_EXTICR2_EXTI7_PF_Pos (12U)
+#define AFIO_EXTICR2_EXTI7_PF_Msk (0x5U << AFIO_EXTICR2_EXTI7_PF_Pos) /*!< 0x00005000 */
+#define AFIO_EXTICR2_EXTI7_PF AFIO_EXTICR2_EXTI7_PF_Msk /*!< PF[7] pin */
+#define AFIO_EXTICR2_EXTI7_PG_Pos (13U)
+#define AFIO_EXTICR2_EXTI7_PG_Msk (0x3U << AFIO_EXTICR2_EXTI7_PG_Pos) /*!< 0x00006000 */
+#define AFIO_EXTICR2_EXTI7_PG AFIO_EXTICR2_EXTI7_PG_Msk /*!< PG[7] pin */
+
+/***************** Bit definition for AFIO_EXTICR3 register *****************/
+#define AFIO_EXTICR3_EXTI8_Pos (0U)
+#define AFIO_EXTICR3_EXTI8_Msk (0xFU << AFIO_EXTICR3_EXTI8_Pos) /*!< 0x0000000F */
+#define AFIO_EXTICR3_EXTI8 AFIO_EXTICR3_EXTI8_Msk /*!< EXTI 8 configuration */
+#define AFIO_EXTICR3_EXTI9_Pos (4U)
+#define AFIO_EXTICR3_EXTI9_Msk (0xFU << AFIO_EXTICR3_EXTI9_Pos) /*!< 0x000000F0 */
+#define AFIO_EXTICR3_EXTI9 AFIO_EXTICR3_EXTI9_Msk /*!< EXTI 9 configuration */
+#define AFIO_EXTICR3_EXTI10_Pos (8U)
+#define AFIO_EXTICR3_EXTI10_Msk (0xFU << AFIO_EXTICR3_EXTI10_Pos) /*!< 0x00000F00 */
+#define AFIO_EXTICR3_EXTI10 AFIO_EXTICR3_EXTI10_Msk /*!< EXTI 10 configuration */
+#define AFIO_EXTICR3_EXTI11_Pos (12U)
+#define AFIO_EXTICR3_EXTI11_Msk (0xFU << AFIO_EXTICR3_EXTI11_Pos) /*!< 0x0000F000 */
+#define AFIO_EXTICR3_EXTI11 AFIO_EXTICR3_EXTI11_Msk /*!< EXTI 11 configuration */
+
+/*!< EXTI8 configuration */
+#define AFIO_EXTICR3_EXTI8_PA ((uint32_t)0x00000000) /*!< PA[8] pin */
+#define AFIO_EXTICR3_EXTI8_PB_Pos (0U)
+#define AFIO_EXTICR3_EXTI8_PB_Msk (0x1U << AFIO_EXTICR3_EXTI8_PB_Pos) /*!< 0x00000001 */
+#define AFIO_EXTICR3_EXTI8_PB AFIO_EXTICR3_EXTI8_PB_Msk /*!< PB[8] pin */
+#define AFIO_EXTICR3_EXTI8_PC_Pos (1U)
+#define AFIO_EXTICR3_EXTI8_PC_Msk (0x1U << AFIO_EXTICR3_EXTI8_PC_Pos) /*!< 0x00000002 */
+#define AFIO_EXTICR3_EXTI8_PC AFIO_EXTICR3_EXTI8_PC_Msk /*!< PC[8] pin */
+#define AFIO_EXTICR3_EXTI8_PD_Pos (0U)
+#define AFIO_EXTICR3_EXTI8_PD_Msk (0x3U << AFIO_EXTICR3_EXTI8_PD_Pos) /*!< 0x00000003 */
+#define AFIO_EXTICR3_EXTI8_PD AFIO_EXTICR3_EXTI8_PD_Msk /*!< PD[8] pin */
+#define AFIO_EXTICR3_EXTI8_PE_Pos (2U)
+#define AFIO_EXTICR3_EXTI8_PE_Msk (0x1U << AFIO_EXTICR3_EXTI8_PE_Pos) /*!< 0x00000004 */
+#define AFIO_EXTICR3_EXTI8_PE AFIO_EXTICR3_EXTI8_PE_Msk /*!< PE[8] pin */
+#define AFIO_EXTICR3_EXTI8_PF_Pos (0U)
+#define AFIO_EXTICR3_EXTI8_PF_Msk (0x5U << AFIO_EXTICR3_EXTI8_PF_Pos) /*!< 0x00000005 */
+#define AFIO_EXTICR3_EXTI8_PF AFIO_EXTICR3_EXTI8_PF_Msk /*!< PF[8] pin */
+#define AFIO_EXTICR3_EXTI8_PG_Pos (1U)
+#define AFIO_EXTICR3_EXTI8_PG_Msk (0x3U << AFIO_EXTICR3_EXTI8_PG_Pos) /*!< 0x00000006 */
+#define AFIO_EXTICR3_EXTI8_PG AFIO_EXTICR3_EXTI8_PG_Msk /*!< PG[8] pin */
+
+/*!< EXTI9 configuration */
+#define AFIO_EXTICR3_EXTI9_PA ((uint32_t)0x00000000) /*!< PA[9] pin */
+#define AFIO_EXTICR3_EXTI9_PB_Pos (4U)
+#define AFIO_EXTICR3_EXTI9_PB_Msk (0x1U << AFIO_EXTICR3_EXTI9_PB_Pos) /*!< 0x00000010 */
+#define AFIO_EXTICR3_EXTI9_PB AFIO_EXTICR3_EXTI9_PB_Msk /*!< PB[9] pin */
+#define AFIO_EXTICR3_EXTI9_PC_Pos (5U)
+#define AFIO_EXTICR3_EXTI9_PC_Msk (0x1U << AFIO_EXTICR3_EXTI9_PC_Pos) /*!< 0x00000020 */
+#define AFIO_EXTICR3_EXTI9_PC AFIO_EXTICR3_EXTI9_PC_Msk /*!< PC[9] pin */
+#define AFIO_EXTICR3_EXTI9_PD_Pos (4U)
+#define AFIO_EXTICR3_EXTI9_PD_Msk (0x3U << AFIO_EXTICR3_EXTI9_PD_Pos) /*!< 0x00000030 */
+#define AFIO_EXTICR3_EXTI9_PD AFIO_EXTICR3_EXTI9_PD_Msk /*!< PD[9] pin */
+#define AFIO_EXTICR3_EXTI9_PE_Pos (6U)
+#define AFIO_EXTICR3_EXTI9_PE_Msk (0x1U << AFIO_EXTICR3_EXTI9_PE_Pos) /*!< 0x00000040 */
+#define AFIO_EXTICR3_EXTI9_PE AFIO_EXTICR3_EXTI9_PE_Msk /*!< PE[9] pin */
+#define AFIO_EXTICR3_EXTI9_PF_Pos (4U)
+#define AFIO_EXTICR3_EXTI9_PF_Msk (0x5U << AFIO_EXTICR3_EXTI9_PF_Pos) /*!< 0x00000050 */
+#define AFIO_EXTICR3_EXTI9_PF AFIO_EXTICR3_EXTI9_PF_Msk /*!< PF[9] pin */
+#define AFIO_EXTICR3_EXTI9_PG_Pos (5U)
+#define AFIO_EXTICR3_EXTI9_PG_Msk (0x3U << AFIO_EXTICR3_EXTI9_PG_Pos) /*!< 0x00000060 */
+#define AFIO_EXTICR3_EXTI9_PG AFIO_EXTICR3_EXTI9_PG_Msk /*!< PG[9] pin */
+
+/*!< EXTI10 configuration */
+#define AFIO_EXTICR3_EXTI10_PA ((uint32_t)0x00000000) /*!< PA[10] pin */
+#define AFIO_EXTICR3_EXTI10_PB_Pos (8U)
+#define AFIO_EXTICR3_EXTI10_PB_Msk (0x1U << AFIO_EXTICR3_EXTI10_PB_Pos) /*!< 0x00000100 */
+#define AFIO_EXTICR3_EXTI10_PB AFIO_EXTICR3_EXTI10_PB_Msk /*!< PB[10] pin */
+#define AFIO_EXTICR3_EXTI10_PC_Pos (9U)
+#define AFIO_EXTICR3_EXTI10_PC_Msk (0x1U << AFIO_EXTICR3_EXTI10_PC_Pos) /*!< 0x00000200 */
+#define AFIO_EXTICR3_EXTI10_PC AFIO_EXTICR3_EXTI10_PC_Msk /*!< PC[10] pin */
+#define AFIO_EXTICR3_EXTI10_PD_Pos (8U)
+#define AFIO_EXTICR3_EXTI10_PD_Msk (0x3U << AFIO_EXTICR3_EXTI10_PD_Pos) /*!< 0x00000300 */
+#define AFIO_EXTICR3_EXTI10_PD AFIO_EXTICR3_EXTI10_PD_Msk /*!< PD[10] pin */
+#define AFIO_EXTICR3_EXTI10_PE_Pos (10U)
+#define AFIO_EXTICR3_EXTI10_PE_Msk (0x1U << AFIO_EXTICR3_EXTI10_PE_Pos) /*!< 0x00000400 */
+#define AFIO_EXTICR3_EXTI10_PE AFIO_EXTICR3_EXTI10_PE_Msk /*!< PE[10] pin */
+#define AFIO_EXTICR3_EXTI10_PF_Pos (8U)
+#define AFIO_EXTICR3_EXTI10_PF_Msk (0x5U << AFIO_EXTICR3_EXTI10_PF_Pos) /*!< 0x00000500 */
+#define AFIO_EXTICR3_EXTI10_PF AFIO_EXTICR3_EXTI10_PF_Msk /*!< PF[10] pin */
+#define AFIO_EXTICR3_EXTI10_PG_Pos (9U)
+#define AFIO_EXTICR3_EXTI10_PG_Msk (0x3U << AFIO_EXTICR3_EXTI10_PG_Pos) /*!< 0x00000600 */
+#define AFIO_EXTICR3_EXTI10_PG AFIO_EXTICR3_EXTI10_PG_Msk /*!< PG[10] pin */
+
+/*!< EXTI11 configuration */
+#define AFIO_EXTICR3_EXTI11_PA ((uint32_t)0x00000000) /*!< PA[11] pin */
+#define AFIO_EXTICR3_EXTI11_PB_Pos (12U)
+#define AFIO_EXTICR3_EXTI11_PB_Msk (0x1U << AFIO_EXTICR3_EXTI11_PB_Pos) /*!< 0x00001000 */
+#define AFIO_EXTICR3_EXTI11_PB AFIO_EXTICR3_EXTI11_PB_Msk /*!< PB[11] pin */
+#define AFIO_EXTICR3_EXTI11_PC_Pos (13U)
+#define AFIO_EXTICR3_EXTI11_PC_Msk (0x1U << AFIO_EXTICR3_EXTI11_PC_Pos) /*!< 0x00002000 */
+#define AFIO_EXTICR3_EXTI11_PC AFIO_EXTICR3_EXTI11_PC_Msk /*!< PC[11] pin */
+#define AFIO_EXTICR3_EXTI11_PD_Pos (12U)
+#define AFIO_EXTICR3_EXTI11_PD_Msk (0x3U << AFIO_EXTICR3_EXTI11_PD_Pos) /*!< 0x00003000 */
+#define AFIO_EXTICR3_EXTI11_PD AFIO_EXTICR3_EXTI11_PD_Msk /*!< PD[11] pin */
+#define AFIO_EXTICR3_EXTI11_PE_Pos (14U)
+#define AFIO_EXTICR3_EXTI11_PE_Msk (0x1U << AFIO_EXTICR3_EXTI11_PE_Pos) /*!< 0x00004000 */
+#define AFIO_EXTICR3_EXTI11_PE AFIO_EXTICR3_EXTI11_PE_Msk /*!< PE[11] pin */
+#define AFIO_EXTICR3_EXTI11_PF_Pos (12U)
+#define AFIO_EXTICR3_EXTI11_PF_Msk (0x5U << AFIO_EXTICR3_EXTI11_PF_Pos) /*!< 0x00005000 */
+#define AFIO_EXTICR3_EXTI11_PF AFIO_EXTICR3_EXTI11_PF_Msk /*!< PF[11] pin */
+#define AFIO_EXTICR3_EXTI11_PG_Pos (13U)
+#define AFIO_EXTICR3_EXTI11_PG_Msk (0x3U << AFIO_EXTICR3_EXTI11_PG_Pos) /*!< 0x00006000 */
+#define AFIO_EXTICR3_EXTI11_PG AFIO_EXTICR3_EXTI11_PG_Msk /*!< PG[11] pin */
+
+/***************** Bit definition for AFIO_EXTICR4 register *****************/
+#define AFIO_EXTICR4_EXTI12_Pos (0U)
+#define AFIO_EXTICR4_EXTI12_Msk (0xFU << AFIO_EXTICR4_EXTI12_Pos) /*!< 0x0000000F */
+#define AFIO_EXTICR4_EXTI12 AFIO_EXTICR4_EXTI12_Msk /*!< EXTI 12 configuration */
+#define AFIO_EXTICR4_EXTI13_Pos (4U)
+#define AFIO_EXTICR4_EXTI13_Msk (0xFU << AFIO_EXTICR4_EXTI13_Pos) /*!< 0x000000F0 */
+#define AFIO_EXTICR4_EXTI13 AFIO_EXTICR4_EXTI13_Msk /*!< EXTI 13 configuration */
+#define AFIO_EXTICR4_EXTI14_Pos (8U)
+#define AFIO_EXTICR4_EXTI14_Msk (0xFU << AFIO_EXTICR4_EXTI14_Pos) /*!< 0x00000F00 */
+#define AFIO_EXTICR4_EXTI14 AFIO_EXTICR4_EXTI14_Msk /*!< EXTI 14 configuration */
+#define AFIO_EXTICR4_EXTI15_Pos (12U)
+#define AFIO_EXTICR4_EXTI15_Msk (0xFU << AFIO_EXTICR4_EXTI15_Pos) /*!< 0x0000F000 */
+#define AFIO_EXTICR4_EXTI15 AFIO_EXTICR4_EXTI15_Msk /*!< EXTI 15 configuration */
+
+/* EXTI12 configuration */
+#define AFIO_EXTICR4_EXTI12_PA ((uint32_t)0x00000000) /*!< PA[12] pin */
+#define AFIO_EXTICR4_EXTI12_PB_Pos (0U)
+#define AFIO_EXTICR4_EXTI12_PB_Msk (0x1U << AFIO_EXTICR4_EXTI12_PB_Pos) /*!< 0x00000001 */
+#define AFIO_EXTICR4_EXTI12_PB AFIO_EXTICR4_EXTI12_PB_Msk /*!< PB[12] pin */
+#define AFIO_EXTICR4_EXTI12_PC_Pos (1U)
+#define AFIO_EXTICR4_EXTI12_PC_Msk (0x1U << AFIO_EXTICR4_EXTI12_PC_Pos) /*!< 0x00000002 */
+#define AFIO_EXTICR4_EXTI12_PC AFIO_EXTICR4_EXTI12_PC_Msk /*!< PC[12] pin */
+#define AFIO_EXTICR4_EXTI12_PD_Pos (0U)
+#define AFIO_EXTICR4_EXTI12_PD_Msk (0x3U << AFIO_EXTICR4_EXTI12_PD_Pos) /*!< 0x00000003 */
+#define AFIO_EXTICR4_EXTI12_PD AFIO_EXTICR4_EXTI12_PD_Msk /*!< PD[12] pin */
+#define AFIO_EXTICR4_EXTI12_PE_Pos (2U)
+#define AFIO_EXTICR4_EXTI12_PE_Msk (0x1U << AFIO_EXTICR4_EXTI12_PE_Pos) /*!< 0x00000004 */
+#define AFIO_EXTICR4_EXTI12_PE AFIO_EXTICR4_EXTI12_PE_Msk /*!< PE[12] pin */
+#define AFIO_EXTICR4_EXTI12_PF_Pos (0U)
+#define AFIO_EXTICR4_EXTI12_PF_Msk (0x5U << AFIO_EXTICR4_EXTI12_PF_Pos) /*!< 0x00000005 */
+#define AFIO_EXTICR4_EXTI12_PF AFIO_EXTICR4_EXTI12_PF_Msk /*!< PF[12] pin */
+#define AFIO_EXTICR4_EXTI12_PG_Pos (1U)
+#define AFIO_EXTICR4_EXTI12_PG_Msk (0x3U << AFIO_EXTICR4_EXTI12_PG_Pos) /*!< 0x00000006 */
+#define AFIO_EXTICR4_EXTI12_PG AFIO_EXTICR4_EXTI12_PG_Msk /*!< PG[12] pin */
+
+/* EXTI13 configuration */
+#define AFIO_EXTICR4_EXTI13_PA ((uint32_t)0x00000000) /*!< PA[13] pin */
+#define AFIO_EXTICR4_EXTI13_PB_Pos (4U)
+#define AFIO_EXTICR4_EXTI13_PB_Msk (0x1U << AFIO_EXTICR4_EXTI13_PB_Pos) /*!< 0x00000010 */
+#define AFIO_EXTICR4_EXTI13_PB AFIO_EXTICR4_EXTI13_PB_Msk /*!< PB[13] pin */
+#define AFIO_EXTICR4_EXTI13_PC_Pos (5U)
+#define AFIO_EXTICR4_EXTI13_PC_Msk (0x1U << AFIO_EXTICR4_EXTI13_PC_Pos) /*!< 0x00000020 */
+#define AFIO_EXTICR4_EXTI13_PC AFIO_EXTICR4_EXTI13_PC_Msk /*!< PC[13] pin */
+#define AFIO_EXTICR4_EXTI13_PD_Pos (4U)
+#define AFIO_EXTICR4_EXTI13_PD_Msk (0x3U << AFIO_EXTICR4_EXTI13_PD_Pos) /*!< 0x00000030 */
+#define AFIO_EXTICR4_EXTI13_PD AFIO_EXTICR4_EXTI13_PD_Msk /*!< PD[13] pin */
+#define AFIO_EXTICR4_EXTI13_PE_Pos (6U)
+#define AFIO_EXTICR4_EXTI13_PE_Msk (0x1U << AFIO_EXTICR4_EXTI13_PE_Pos) /*!< 0x00000040 */
+#define AFIO_EXTICR4_EXTI13_PE AFIO_EXTICR4_EXTI13_PE_Msk /*!< PE[13] pin */
+#define AFIO_EXTICR4_EXTI13_PF_Pos (4U)
+#define AFIO_EXTICR4_EXTI13_PF_Msk (0x5U << AFIO_EXTICR4_EXTI13_PF_Pos) /*!< 0x00000050 */
+#define AFIO_EXTICR4_EXTI13_PF AFIO_EXTICR4_EXTI13_PF_Msk /*!< PF[13] pin */
+#define AFIO_EXTICR4_EXTI13_PG_Pos (5U)
+#define AFIO_EXTICR4_EXTI13_PG_Msk (0x3U << AFIO_EXTICR4_EXTI13_PG_Pos) /*!< 0x00000060 */
+#define AFIO_EXTICR4_EXTI13_PG AFIO_EXTICR4_EXTI13_PG_Msk /*!< PG[13] pin */
+
+/*!< EXTI14 configuration */
+#define AFIO_EXTICR4_EXTI14_PA ((uint32_t)0x00000000) /*!< PA[14] pin */
+#define AFIO_EXTICR4_EXTI14_PB_Pos (8U)
+#define AFIO_EXTICR4_EXTI14_PB_Msk (0x1U << AFIO_EXTICR4_EXTI14_PB_Pos) /*!< 0x00000100 */
+#define AFIO_EXTICR4_EXTI14_PB AFIO_EXTICR4_EXTI14_PB_Msk /*!< PB[14] pin */
+#define AFIO_EXTICR4_EXTI14_PC_Pos (9U)
+#define AFIO_EXTICR4_EXTI14_PC_Msk (0x1U << AFIO_EXTICR4_EXTI14_PC_Pos) /*!< 0x00000200 */
+#define AFIO_EXTICR4_EXTI14_PC AFIO_EXTICR4_EXTI14_PC_Msk /*!< PC[14] pin */
+#define AFIO_EXTICR4_EXTI14_PD_Pos (8U)
+#define AFIO_EXTICR4_EXTI14_PD_Msk (0x3U << AFIO_EXTICR4_EXTI14_PD_Pos) /*!< 0x00000300 */
+#define AFIO_EXTICR4_EXTI14_PD AFIO_EXTICR4_EXTI14_PD_Msk /*!< PD[14] pin */
+#define AFIO_EXTICR4_EXTI14_PE_Pos (10U)
+#define AFIO_EXTICR4_EXTI14_PE_Msk (0x1U << AFIO_EXTICR4_EXTI14_PE_Pos) /*!< 0x00000400 */
+#define AFIO_EXTICR4_EXTI14_PE AFIO_EXTICR4_EXTI14_PE_Msk /*!< PE[14] pin */
+#define AFIO_EXTICR4_EXTI14_PF_Pos (8U)
+#define AFIO_EXTICR4_EXTI14_PF_Msk (0x5U << AFIO_EXTICR4_EXTI14_PF_Pos) /*!< 0x00000500 */
+#define AFIO_EXTICR4_EXTI14_PF AFIO_EXTICR4_EXTI14_PF_Msk /*!< PF[14] pin */
+#define AFIO_EXTICR4_EXTI14_PG_Pos (9U)
+#define AFIO_EXTICR4_EXTI14_PG_Msk (0x3U << AFIO_EXTICR4_EXTI14_PG_Pos) /*!< 0x00000600 */
+#define AFIO_EXTICR4_EXTI14_PG AFIO_EXTICR4_EXTI14_PG_Msk /*!< PG[14] pin */
+
+/*!< EXTI15 configuration */
+#define AFIO_EXTICR4_EXTI15_PA ((uint32_t)0x00000000) /*!< PA[15] pin */
+#define AFIO_EXTICR4_EXTI15_PB_Pos (12U)
+#define AFIO_EXTICR4_EXTI15_PB_Msk (0x1U << AFIO_EXTICR4_EXTI15_PB_Pos) /*!< 0x00001000 */
+#define AFIO_EXTICR4_EXTI15_PB AFIO_EXTICR4_EXTI15_PB_Msk /*!< PB[15] pin */
+#define AFIO_EXTICR4_EXTI15_PC_Pos (13U)
+#define AFIO_EXTICR4_EXTI15_PC_Msk (0x1U << AFIO_EXTICR4_EXTI15_PC_Pos) /*!< 0x00002000 */
+#define AFIO_EXTICR4_EXTI15_PC AFIO_EXTICR4_EXTI15_PC_Msk /*!< PC[15] pin */
+#define AFIO_EXTICR4_EXTI15_PD_Pos (12U)
+#define AFIO_EXTICR4_EXTI15_PD_Msk (0x3U << AFIO_EXTICR4_EXTI15_PD_Pos) /*!< 0x00003000 */
+#define AFIO_EXTICR4_EXTI15_PD AFIO_EXTICR4_EXTI15_PD_Msk /*!< PD[15] pin */
+#define AFIO_EXTICR4_EXTI15_PE_Pos (14U)
+#define AFIO_EXTICR4_EXTI15_PE_Msk (0x1U << AFIO_EXTICR4_EXTI15_PE_Pos) /*!< 0x00004000 */
+#define AFIO_EXTICR4_EXTI15_PE AFIO_EXTICR4_EXTI15_PE_Msk /*!< PE[15] pin */
+#define AFIO_EXTICR4_EXTI15_PF_Pos (12U)
+#define AFIO_EXTICR4_EXTI15_PF_Msk (0x5U << AFIO_EXTICR4_EXTI15_PF_Pos) /*!< 0x00005000 */
+#define AFIO_EXTICR4_EXTI15_PF AFIO_EXTICR4_EXTI15_PF_Msk /*!< PF[15] pin */
+#define AFIO_EXTICR4_EXTI15_PG_Pos (13U)
+#define AFIO_EXTICR4_EXTI15_PG_Msk (0x3U << AFIO_EXTICR4_EXTI15_PG_Pos) /*!< 0x00006000 */
+#define AFIO_EXTICR4_EXTI15_PG AFIO_EXTICR4_EXTI15_PG_Msk /*!< PG[15] pin */
+
+/****************** Bit definition for AFIO_MAPR2 register ******************/
+
+
+
+/******************************************************************************/
+/* */
+/* SystemTick */
+/* */
+/******************************************************************************/
+
+/***************** Bit definition for SysTick_CTRL register *****************/
+#define SysTick_CTRL_ENABLE ((uint32_t)0x00000001) /*!< Counter enable */
+#define SysTick_CTRL_TICKINT ((uint32_t)0x00000002) /*!< Counting down to 0 pends the SysTick handler */
+#define SysTick_CTRL_CLKSOURCE ((uint32_t)0x00000004) /*!< Clock source */
+#define SysTick_CTRL_COUNTFLAG ((uint32_t)0x00010000) /*!< Count Flag */
+
+/***************** Bit definition for SysTick_LOAD register *****************/
+#define SysTick_LOAD_RELOAD ((uint32_t)0x00FFFFFF) /*!< Value to load into the SysTick Current Value Register when the counter reaches 0 */
+
+/***************** Bit definition for SysTick_VAL register ******************/
+#define SysTick_VAL_CURRENT ((uint32_t)0x00FFFFFF) /*!< Current value at the time the register is accessed */
+
+/***************** Bit definition for SysTick_CALIB register ****************/
+#define SysTick_CALIB_TENMS ((uint32_t)0x00FFFFFF) /*!< Reload value to use for 10ms timing */
+#define SysTick_CALIB_SKEW ((uint32_t)0x40000000) /*!< Calibration value is not exactly 10 ms */
+#define SysTick_CALIB_NOREF ((uint32_t)0x80000000) /*!< The reference clock is not provided */
+
+/******************************************************************************/
+/* */
+/* Nested Vectored Interrupt Controller */
+/* */
+/******************************************************************************/
+
+/****************** Bit definition for NVIC_ISER register *******************/
+#define NVIC_ISER_SETENA_Pos (0U)
+#define NVIC_ISER_SETENA_Msk (0xFFFFFFFFU << NVIC_ISER_SETENA_Pos) /*!< 0xFFFFFFFF */
+#define NVIC_ISER_SETENA NVIC_ISER_SETENA_Msk /*!< Interrupt set enable bits */
+#define NVIC_ISER_SETENA_0 (0x00000001U << NVIC_ISER_SETENA_Pos) /*!< 0x00000001 */
+#define NVIC_ISER_SETENA_1 (0x00000002U << NVIC_ISER_SETENA_Pos) /*!< 0x00000002 */
+#define NVIC_ISER_SETENA_2 (0x00000004U << NVIC_ISER_SETENA_Pos) /*!< 0x00000004 */
+#define NVIC_ISER_SETENA_3 (0x00000008U << NVIC_ISER_SETENA_Pos) /*!< 0x00000008 */
+#define NVIC_ISER_SETENA_4 (0x00000010U << NVIC_ISER_SETENA_Pos) /*!< 0x00000010 */
+#define NVIC_ISER_SETENA_5 (0x00000020U << NVIC_ISER_SETENA_Pos) /*!< 0x00000020 */
+#define NVIC_ISER_SETENA_6 (0x00000040U << NVIC_ISER_SETENA_Pos) /*!< 0x00000040 */
+#define NVIC_ISER_SETENA_7 (0x00000080U << NVIC_ISER_SETENA_Pos) /*!< 0x00000080 */
+#define NVIC_ISER_SETENA_8 (0x00000100U << NVIC_ISER_SETENA_Pos) /*!< 0x00000100 */
+#define NVIC_ISER_SETENA_9 (0x00000200U << NVIC_ISER_SETENA_Pos) /*!< 0x00000200 */
+#define NVIC_ISER_SETENA_10 (0x00000400U << NVIC_ISER_SETENA_Pos) /*!< 0x00000400 */
+#define NVIC_ISER_SETENA_11 (0x00000800U << NVIC_ISER_SETENA_Pos) /*!< 0x00000800 */
+#define NVIC_ISER_SETENA_12 (0x00001000U << NVIC_ISER_SETENA_Pos) /*!< 0x00001000 */
+#define NVIC_ISER_SETENA_13 (0x00002000U << NVIC_ISER_SETENA_Pos) /*!< 0x00002000 */
+#define NVIC_ISER_SETENA_14 (0x00004000U << NVIC_ISER_SETENA_Pos) /*!< 0x00004000 */
+#define NVIC_ISER_SETENA_15 (0x00008000U << NVIC_ISER_SETENA_Pos) /*!< 0x00008000 */
+#define NVIC_ISER_SETENA_16 (0x00010000U << NVIC_ISER_SETENA_Pos) /*!< 0x00010000 */
+#define NVIC_ISER_SETENA_17 (0x00020000U << NVIC_ISER_SETENA_Pos) /*!< 0x00020000 */
+#define NVIC_ISER_SETENA_18 (0x00040000U << NVIC_ISER_SETENA_Pos) /*!< 0x00040000 */
+#define NVIC_ISER_SETENA_19 (0x00080000U << NVIC_ISER_SETENA_Pos) /*!< 0x00080000 */
+#define NVIC_ISER_SETENA_20 (0x00100000U << NVIC_ISER_SETENA_Pos) /*!< 0x00100000 */
+#define NVIC_ISER_SETENA_21 (0x00200000U << NVIC_ISER_SETENA_Pos) /*!< 0x00200000 */
+#define NVIC_ISER_SETENA_22 (0x00400000U << NVIC_ISER_SETENA_Pos) /*!< 0x00400000 */
+#define NVIC_ISER_SETENA_23 (0x00800000U << NVIC_ISER_SETENA_Pos) /*!< 0x00800000 */
+#define NVIC_ISER_SETENA_24 (0x01000000U << NVIC_ISER_SETENA_Pos) /*!< 0x01000000 */
+#define NVIC_ISER_SETENA_25 (0x02000000U << NVIC_ISER_SETENA_Pos) /*!< 0x02000000 */
+#define NVIC_ISER_SETENA_26 (0x04000000U << NVIC_ISER_SETENA_Pos) /*!< 0x04000000 */
+#define NVIC_ISER_SETENA_27 (0x08000000U << NVIC_ISER_SETENA_Pos) /*!< 0x08000000 */
+#define NVIC_ISER_SETENA_28 (0x10000000U << NVIC_ISER_SETENA_Pos) /*!< 0x10000000 */
+#define NVIC_ISER_SETENA_29 (0x20000000U << NVIC_ISER_SETENA_Pos) /*!< 0x20000000 */
+#define NVIC_ISER_SETENA_30 (0x40000000U << NVIC_ISER_SETENA_Pos) /*!< 0x40000000 */
+#define NVIC_ISER_SETENA_31 (0x80000000U << NVIC_ISER_SETENA_Pos) /*!< 0x80000000 */
+
+/****************** Bit definition for NVIC_ICER register *******************/
+#define NVIC_ICER_CLRENA_Pos (0U)
+#define NVIC_ICER_CLRENA_Msk (0xFFFFFFFFU << NVIC_ICER_CLRENA_Pos) /*!< 0xFFFFFFFF */
+#define NVIC_ICER_CLRENA NVIC_ICER_CLRENA_Msk /*!< Interrupt clear-enable bits */
+#define NVIC_ICER_CLRENA_0 (0x00000001U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000001 */
+#define NVIC_ICER_CLRENA_1 (0x00000002U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000002 */
+#define NVIC_ICER_CLRENA_2 (0x00000004U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000004 */
+#define NVIC_ICER_CLRENA_3 (0x00000008U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000008 */
+#define NVIC_ICER_CLRENA_4 (0x00000010U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000010 */
+#define NVIC_ICER_CLRENA_5 (0x00000020U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000020 */
+#define NVIC_ICER_CLRENA_6 (0x00000040U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000040 */
+#define NVIC_ICER_CLRENA_7 (0x00000080U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000080 */
+#define NVIC_ICER_CLRENA_8 (0x00000100U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000100 */
+#define NVIC_ICER_CLRENA_9 (0x00000200U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000200 */
+#define NVIC_ICER_CLRENA_10 (0x00000400U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000400 */
+#define NVIC_ICER_CLRENA_11 (0x00000800U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000800 */
+#define NVIC_ICER_CLRENA_12 (0x00001000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00001000 */
+#define NVIC_ICER_CLRENA_13 (0x00002000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00002000 */
+#define NVIC_ICER_CLRENA_14 (0x00004000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00004000 */
+#define NVIC_ICER_CLRENA_15 (0x00008000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00008000 */
+#define NVIC_ICER_CLRENA_16 (0x00010000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00010000 */
+#define NVIC_ICER_CLRENA_17 (0x00020000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00020000 */
+#define NVIC_ICER_CLRENA_18 (0x00040000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00040000 */
+#define NVIC_ICER_CLRENA_19 (0x00080000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00080000 */
+#define NVIC_ICER_CLRENA_20 (0x00100000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00100000 */
+#define NVIC_ICER_CLRENA_21 (0x00200000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00200000 */
+#define NVIC_ICER_CLRENA_22 (0x00400000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00400000 */
+#define NVIC_ICER_CLRENA_23 (0x00800000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00800000 */
+#define NVIC_ICER_CLRENA_24 (0x01000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x01000000 */
+#define NVIC_ICER_CLRENA_25 (0x02000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x02000000 */
+#define NVIC_ICER_CLRENA_26 (0x04000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x04000000 */
+#define NVIC_ICER_CLRENA_27 (0x08000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x08000000 */
+#define NVIC_ICER_CLRENA_28 (0x10000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x10000000 */
+#define NVIC_ICER_CLRENA_29 (0x20000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x20000000 */
+#define NVIC_ICER_CLRENA_30 (0x40000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x40000000 */
+#define NVIC_ICER_CLRENA_31 (0x80000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x80000000 */
+
+/****************** Bit definition for NVIC_ISPR register *******************/
+#define NVIC_ISPR_SETPEND_Pos (0U)
+#define NVIC_ISPR_SETPEND_Msk (0xFFFFFFFFU << NVIC_ISPR_SETPEND_Pos) /*!< 0xFFFFFFFF */
+#define NVIC_ISPR_SETPEND NVIC_ISPR_SETPEND_Msk /*!< Interrupt set-pending bits */
+#define NVIC_ISPR_SETPEND_0 (0x00000001U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000001 */
+#define NVIC_ISPR_SETPEND_1 (0x00000002U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000002 */
+#define NVIC_ISPR_SETPEND_2 (0x00000004U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000004 */
+#define NVIC_ISPR_SETPEND_3 (0x00000008U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000008 */
+#define NVIC_ISPR_SETPEND_4 (0x00000010U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000010 */
+#define NVIC_ISPR_SETPEND_5 (0x00000020U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000020 */
+#define NVIC_ISPR_SETPEND_6 (0x00000040U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000040 */
+#define NVIC_ISPR_SETPEND_7 (0x00000080U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000080 */
+#define NVIC_ISPR_SETPEND_8 (0x00000100U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000100 */
+#define NVIC_ISPR_SETPEND_9 (0x00000200U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000200 */
+#define NVIC_ISPR_SETPEND_10 (0x00000400U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000400 */
+#define NVIC_ISPR_SETPEND_11 (0x00000800U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000800 */
+#define NVIC_ISPR_SETPEND_12 (0x00001000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00001000 */
+#define NVIC_ISPR_SETPEND_13 (0x00002000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00002000 */
+#define NVIC_ISPR_SETPEND_14 (0x00004000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00004000 */
+#define NVIC_ISPR_SETPEND_15 (0x00008000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00008000 */
+#define NVIC_ISPR_SETPEND_16 (0x00010000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00010000 */
+#define NVIC_ISPR_SETPEND_17 (0x00020000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00020000 */
+#define NVIC_ISPR_SETPEND_18 (0x00040000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00040000 */
+#define NVIC_ISPR_SETPEND_19 (0x00080000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00080000 */
+#define NVIC_ISPR_SETPEND_20 (0x00100000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00100000 */
+#define NVIC_ISPR_SETPEND_21 (0x00200000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00200000 */
+#define NVIC_ISPR_SETPEND_22 (0x00400000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00400000 */
+#define NVIC_ISPR_SETPEND_23 (0x00800000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00800000 */
+#define NVIC_ISPR_SETPEND_24 (0x01000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x01000000 */
+#define NVIC_ISPR_SETPEND_25 (0x02000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x02000000 */
+#define NVIC_ISPR_SETPEND_26 (0x04000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x04000000 */
+#define NVIC_ISPR_SETPEND_27 (0x08000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x08000000 */
+#define NVIC_ISPR_SETPEND_28 (0x10000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x10000000 */
+#define NVIC_ISPR_SETPEND_29 (0x20000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x20000000 */
+#define NVIC_ISPR_SETPEND_30 (0x40000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x40000000 */
+#define NVIC_ISPR_SETPEND_31 (0x80000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x80000000 */
+
+/****************** Bit definition for NVIC_ICPR register *******************/
+#define NVIC_ICPR_CLRPEND_Pos (0U)
+#define NVIC_ICPR_CLRPEND_Msk (0xFFFFFFFFU << NVIC_ICPR_CLRPEND_Pos) /*!< 0xFFFFFFFF */
+#define NVIC_ICPR_CLRPEND NVIC_ICPR_CLRPEND_Msk /*!< Interrupt clear-pending bits */
+#define NVIC_ICPR_CLRPEND_0 (0x00000001U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000001 */
+#define NVIC_ICPR_CLRPEND_1 (0x00000002U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000002 */
+#define NVIC_ICPR_CLRPEND_2 (0x00000004U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000004 */
+#define NVIC_ICPR_CLRPEND_3 (0x00000008U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000008 */
+#define NVIC_ICPR_CLRPEND_4 (0x00000010U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000010 */
+#define NVIC_ICPR_CLRPEND_5 (0x00000020U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000020 */
+#define NVIC_ICPR_CLRPEND_6 (0x00000040U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000040 */
+#define NVIC_ICPR_CLRPEND_7 (0x00000080U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000080 */
+#define NVIC_ICPR_CLRPEND_8 (0x00000100U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000100 */
+#define NVIC_ICPR_CLRPEND_9 (0x00000200U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000200 */
+#define NVIC_ICPR_CLRPEND_10 (0x00000400U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000400 */
+#define NVIC_ICPR_CLRPEND_11 (0x00000800U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000800 */
+#define NVIC_ICPR_CLRPEND_12 (0x00001000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00001000 */
+#define NVIC_ICPR_CLRPEND_13 (0x00002000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00002000 */
+#define NVIC_ICPR_CLRPEND_14 (0x00004000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00004000 */
+#define NVIC_ICPR_CLRPEND_15 (0x00008000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00008000 */
+#define NVIC_ICPR_CLRPEND_16 (0x00010000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00010000 */
+#define NVIC_ICPR_CLRPEND_17 (0x00020000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00020000 */
+#define NVIC_ICPR_CLRPEND_18 (0x00040000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00040000 */
+#define NVIC_ICPR_CLRPEND_19 (0x00080000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00080000 */
+#define NVIC_ICPR_CLRPEND_20 (0x00100000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00100000 */
+#define NVIC_ICPR_CLRPEND_21 (0x00200000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00200000 */
+#define NVIC_ICPR_CLRPEND_22 (0x00400000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00400000 */
+#define NVIC_ICPR_CLRPEND_23 (0x00800000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00800000 */
+#define NVIC_ICPR_CLRPEND_24 (0x01000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x01000000 */
+#define NVIC_ICPR_CLRPEND_25 (0x02000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x02000000 */
+#define NVIC_ICPR_CLRPEND_26 (0x04000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x04000000 */
+#define NVIC_ICPR_CLRPEND_27 (0x08000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x08000000 */
+#define NVIC_ICPR_CLRPEND_28 (0x10000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x10000000 */
+#define NVIC_ICPR_CLRPEND_29 (0x20000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x20000000 */
+#define NVIC_ICPR_CLRPEND_30 (0x40000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x40000000 */
+#define NVIC_ICPR_CLRPEND_31 (0x80000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x80000000 */
+
+/****************** Bit definition for NVIC_IABR register *******************/
+#define NVIC_IABR_ACTIVE_Pos (0U)
+#define NVIC_IABR_ACTIVE_Msk (0xFFFFFFFFU << NVIC_IABR_ACTIVE_Pos) /*!< 0xFFFFFFFF */
+#define NVIC_IABR_ACTIVE NVIC_IABR_ACTIVE_Msk /*!< Interrupt active flags */
+#define NVIC_IABR_ACTIVE_0 (0x00000001U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000001 */
+#define NVIC_IABR_ACTIVE_1 (0x00000002U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000002 */
+#define NVIC_IABR_ACTIVE_2 (0x00000004U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000004 */
+#define NVIC_IABR_ACTIVE_3 (0x00000008U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000008 */
+#define NVIC_IABR_ACTIVE_4 (0x00000010U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000010 */
+#define NVIC_IABR_ACTIVE_5 (0x00000020U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000020 */
+#define NVIC_IABR_ACTIVE_6 (0x00000040U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000040 */
+#define NVIC_IABR_ACTIVE_7 (0x00000080U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000080 */
+#define NVIC_IABR_ACTIVE_8 (0x00000100U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000100 */
+#define NVIC_IABR_ACTIVE_9 (0x00000200U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000200 */
+#define NVIC_IABR_ACTIVE_10 (0x00000400U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000400 */
+#define NVIC_IABR_ACTIVE_11 (0x00000800U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000800 */
+#define NVIC_IABR_ACTIVE_12 (0x00001000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00001000 */
+#define NVIC_IABR_ACTIVE_13 (0x00002000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00002000 */
+#define NVIC_IABR_ACTIVE_14 (0x00004000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00004000 */
+#define NVIC_IABR_ACTIVE_15 (0x00008000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00008000 */
+#define NVIC_IABR_ACTIVE_16 (0x00010000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00010000 */
+#define NVIC_IABR_ACTIVE_17 (0x00020000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00020000 */
+#define NVIC_IABR_ACTIVE_18 (0x00040000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00040000 */
+#define NVIC_IABR_ACTIVE_19 (0x00080000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00080000 */
+#define NVIC_IABR_ACTIVE_20 (0x00100000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00100000 */
+#define NVIC_IABR_ACTIVE_21 (0x00200000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00200000 */
+#define NVIC_IABR_ACTIVE_22 (0x00400000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00400000 */
+#define NVIC_IABR_ACTIVE_23 (0x00800000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00800000 */
+#define NVIC_IABR_ACTIVE_24 (0x01000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x01000000 */
+#define NVIC_IABR_ACTIVE_25 (0x02000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x02000000 */
+#define NVIC_IABR_ACTIVE_26 (0x04000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x04000000 */
+#define NVIC_IABR_ACTIVE_27 (0x08000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x08000000 */
+#define NVIC_IABR_ACTIVE_28 (0x10000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x10000000 */
+#define NVIC_IABR_ACTIVE_29 (0x20000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x20000000 */
+#define NVIC_IABR_ACTIVE_30 (0x40000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x40000000 */
+#define NVIC_IABR_ACTIVE_31 (0x80000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x80000000 */
+
+/****************** Bit definition for NVIC_PRI0 register *******************/
+#define NVIC_IPR0_PRI_0 ((uint32_t)0x000000FF) /*!< Priority of interrupt 0 */
+#define NVIC_IPR0_PRI_1 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 1 */
+#define NVIC_IPR0_PRI_2 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 2 */
+#define NVIC_IPR0_PRI_3 ((uint32_t)0xFF000000) /*!< Priority of interrupt 3 */
+
+/****************** Bit definition for NVIC_PRI1 register *******************/
+#define NVIC_IPR1_PRI_4 ((uint32_t)0x000000FF) /*!< Priority of interrupt 4 */
+#define NVIC_IPR1_PRI_5 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 5 */
+#define NVIC_IPR1_PRI_6 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 6 */
+#define NVIC_IPR1_PRI_7 ((uint32_t)0xFF000000) /*!< Priority of interrupt 7 */
+
+/****************** Bit definition for NVIC_PRI2 register *******************/
+#define NVIC_IPR2_PRI_8 ((uint32_t)0x000000FF) /*!< Priority of interrupt 8 */
+#define NVIC_IPR2_PRI_9 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 9 */
+#define NVIC_IPR2_PRI_10 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 10 */
+#define NVIC_IPR2_PRI_11 ((uint32_t)0xFF000000) /*!< Priority of interrupt 11 */
+
+/****************** Bit definition for NVIC_PRI3 register *******************/
+#define NVIC_IPR3_PRI_12 ((uint32_t)0x000000FF) /*!< Priority of interrupt 12 */
+#define NVIC_IPR3_PRI_13 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 13 */
+#define NVIC_IPR3_PRI_14 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 14 */
+#define NVIC_IPR3_PRI_15 ((uint32_t)0xFF000000) /*!< Priority of interrupt 15 */
+
+/****************** Bit definition for NVIC_PRI4 register *******************/
+#define NVIC_IPR4_PRI_16 ((uint32_t)0x000000FF) /*!< Priority of interrupt 16 */
+#define NVIC_IPR4_PRI_17 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 17 */
+#define NVIC_IPR4_PRI_18 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 18 */
+#define NVIC_IPR4_PRI_19 ((uint32_t)0xFF000000) /*!< Priority of interrupt 19 */
+
+/****************** Bit definition for NVIC_PRI5 register *******************/
+#define NVIC_IPR5_PRI_20 ((uint32_t)0x000000FF) /*!< Priority of interrupt 20 */
+#define NVIC_IPR5_PRI_21 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 21 */
+#define NVIC_IPR5_PRI_22 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 22 */
+#define NVIC_IPR5_PRI_23 ((uint32_t)0xFF000000) /*!< Priority of interrupt 23 */
+
+/****************** Bit definition for NVIC_PRI6 register *******************/
+#define NVIC_IPR6_PRI_24 ((uint32_t)0x000000FF) /*!< Priority of interrupt 24 */
+#define NVIC_IPR6_PRI_25 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 25 */
+#define NVIC_IPR6_PRI_26 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 26 */
+#define NVIC_IPR6_PRI_27 ((uint32_t)0xFF000000) /*!< Priority of interrupt 27 */
+
+/****************** Bit definition for NVIC_PRI7 register *******************/
+#define NVIC_IPR7_PRI_28 ((uint32_t)0x000000FF) /*!< Priority of interrupt 28 */
+#define NVIC_IPR7_PRI_29 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 29 */
+#define NVIC_IPR7_PRI_30 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 30 */
+#define NVIC_IPR7_PRI_31 ((uint32_t)0xFF000000) /*!< Priority of interrupt 31 */
+
+/****************** Bit definition for SCB_CPUID register *******************/
+#define SCB_CPUID_REVISION ((uint32_t)0x0000000F) /*!< Implementation defined revision number */
+#define SCB_CPUID_PARTNO ((uint32_t)0x0000FFF0) /*!< Number of processor within family */
+#define SCB_CPUID_Constant ((uint32_t)0x000F0000) /*!< Reads as 0x0F */
+#define SCB_CPUID_VARIANT ((uint32_t)0x00F00000) /*!< Implementation defined variant number */
+#define SCB_CPUID_IMPLEMENTER ((uint32_t)0xFF000000) /*!< Implementer code. ARM is 0x41 */
+
+/******************* Bit definition for SCB_ICSR register *******************/
+#define SCB_ICSR_VECTACTIVE ((uint32_t)0x000001FF) /*!< Active ISR number field */
+#define SCB_ICSR_RETTOBASE ((uint32_t)0x00000800) /*!< All active exceptions minus the IPSR_current_exception yields the empty set */
+#define SCB_ICSR_VECTPENDING ((uint32_t)0x003FF000) /*!< Pending ISR number field */
+#define SCB_ICSR_ISRPENDING ((uint32_t)0x00400000) /*!< Interrupt pending flag */
+#define SCB_ICSR_ISRPREEMPT ((uint32_t)0x00800000) /*!< It indicates that a pending interrupt becomes active in the next running cycle */
+#define SCB_ICSR_PENDSTCLR ((uint32_t)0x02000000) /*!< Clear pending SysTick bit */
+#define SCB_ICSR_PENDSTSET ((uint32_t)0x04000000) /*!< Set pending SysTick bit */
+#define SCB_ICSR_PENDSVCLR ((uint32_t)0x08000000) /*!< Clear pending pendSV bit */
+#define SCB_ICSR_PENDSVSET ((uint32_t)0x10000000) /*!< Set pending pendSV bit */
+#define SCB_ICSR_NMIPENDSET ((uint32_t)0x80000000) /*!< Set pending NMI bit */
+
+/******************* Bit definition for SCB_VTOR register *******************/
+#define SCB_VTOR_TBLOFF ((uint32_t)0x1FFFFF80) /*!< Vector table base offset field */
+#define SCB_VTOR_TBLBASE ((uint32_t)0x20000000) /*!< Table base in code(0) or RAM(1) */
+
+/*!<***************** Bit definition for SCB_AIRCR register *******************/
+#define SCB_AIRCR_VECTRESET ((uint32_t)0x00000001) /*!< System Reset bit */
+#define SCB_AIRCR_VECTCLRACTIVE ((uint32_t)0x00000002) /*!< Clear active vector bit */
+#define SCB_AIRCR_SYSRESETREQ ((uint32_t)0x00000004) /*!< Requests chip control logic to generate a reset */
+
+#define SCB_AIRCR_PRIGROUP ((uint32_t)0x00000700) /*!< PRIGROUP[2:0] bits (Priority group) */
+#define SCB_AIRCR_PRIGROUP_0 ((uint32_t)0x00000100) /*!< Bit 0 */
+#define SCB_AIRCR_PRIGROUP_1 ((uint32_t)0x00000200) /*!< Bit 1 */
+#define SCB_AIRCR_PRIGROUP_2 ((uint32_t)0x00000400) /*!< Bit 2 */
+
+/* prority group configuration */
+#define SCB_AIRCR_PRIGROUP0 ((uint32_t)0x00000000) /*!< Priority group=0 (7 bits of pre-emption priority, 1 bit of subpriority) */
+#define SCB_AIRCR_PRIGROUP1 ((uint32_t)0x00000100) /*!< Priority group=1 (6 bits of pre-emption priority, 2 bits of subpriority) */
+#define SCB_AIRCR_PRIGROUP2 ((uint32_t)0x00000200) /*!< Priority group=2 (5 bits of pre-emption priority, 3 bits of subpriority) */
+#define SCB_AIRCR_PRIGROUP3 ((uint32_t)0x00000300) /*!< Priority group=3 (4 bits of pre-emption priority, 4 bits of subpriority) */
+#define SCB_AIRCR_PRIGROUP4 ((uint32_t)0x00000400) /*!< Priority group=4 (3 bits of pre-emption priority, 5 bits of subpriority) */
+#define SCB_AIRCR_PRIGROUP5 ((uint32_t)0x00000500) /*!< Priority group=5 (2 bits of pre-emption priority, 6 bits of subpriority) */
+#define SCB_AIRCR_PRIGROUP6 ((uint32_t)0x00000600) /*!< Priority group=6 (1 bit of pre-emption priority, 7 bits of subpriority) */
+#define SCB_AIRCR_PRIGROUP7 ((uint32_t)0x00000700) /*!< Priority group=7 (no pre-emption priority, 8 bits of subpriority) */
+
+#define SCB_AIRCR_ENDIANESS ((uint32_t)0x00008000) /*!< Data endianness bit */
+#define SCB_AIRCR_VECTKEY ((uint32_t)0xFFFF0000) /*!< Register key (VECTKEY) - Reads as 0xFA05 (VECTKEYSTAT) */
+
+/******************* Bit definition for SCB_SCR register ********************/
+#define SCB_SCR_SLEEPONEXIT ((uint32_t)0x00000002) /*!< Sleep on exit bit */
+#define SCB_SCR_SLEEPDEEP ((uint32_t)0x00000004) /*!< Sleep deep bit */
+#define SCB_SCR_SEVONPEND ((uint32_t)0x00000010) /*!< Wake up from WFE */
+
+/******************** Bit definition for SCB_CCR register *******************/
+#define SCB_CCR_NONBASETHRDENA ((uint32_t)0x00000001) /*!< Thread mode can be entered from any level in Handler mode by controlled return value */
+#define SCB_CCR_USERSETMPEND ((uint32_t)0x00000002) /*!< Enables user code to write the Software Trigger Interrupt register to trigger (pend) a Main exception */
+#define SCB_CCR_UNALIGN_TRP ((uint32_t)0x00000008) /*!< Trap for unaligned access */
+#define SCB_CCR_DIV_0_TRP ((uint32_t)0x00000010) /*!< Trap on Divide by 0 */
+#define SCB_CCR_BFHFNMIGN ((uint32_t)0x00000100) /*!< Handlers running at priority -1 and -2 */
+#define SCB_CCR_STKALIGN ((uint32_t)0x00000200) /*!< On exception entry, the SP used prior to the exception is adjusted to be 8-byte aligned */
+
+/******************* Bit definition for SCB_SHPR register ********************/
+#define SCB_SHPR_PRI_N_Pos (0U)
+#define SCB_SHPR_PRI_N_Msk (0xFFU << SCB_SHPR_PRI_N_Pos) /*!< 0x000000FF */
+#define SCB_SHPR_PRI_N SCB_SHPR_PRI_N_Msk /*!< Priority of system handler 4,8, and 12. Mem Manage, reserved and Debug Monitor */
+#define SCB_SHPR_PRI_N1_Pos (8U)
+#define SCB_SHPR_PRI_N1_Msk (0xFFU << SCB_SHPR_PRI_N1_Pos) /*!< 0x0000FF00 */
+#define SCB_SHPR_PRI_N1 SCB_SHPR_PRI_N1_Msk /*!< Priority of system handler 5,9, and 13. Bus Fault, reserved and reserved */
+#define SCB_SHPR_PRI_N2_Pos (16U)
+#define SCB_SHPR_PRI_N2_Msk (0xFFU << SCB_SHPR_PRI_N2_Pos) /*!< 0x00FF0000 */
+#define SCB_SHPR_PRI_N2 SCB_SHPR_PRI_N2_Msk /*!< Priority of system handler 6,10, and 14. Usage Fault, reserved and PendSV */
+#define SCB_SHPR_PRI_N3_Pos (24U)
+#define SCB_SHPR_PRI_N3_Msk (0xFFU << SCB_SHPR_PRI_N3_Pos) /*!< 0xFF000000 */
+#define SCB_SHPR_PRI_N3 SCB_SHPR_PRI_N3_Msk /*!< Priority of system handler 7,11, and 15. Reserved, SVCall and SysTick */
+
+/****************** Bit definition for SCB_SHCSR register *******************/
+#define SCB_SHCSR_MEMFAULTACT ((uint32_t)0x00000001) /*!< MemManage is active */
+#define SCB_SHCSR_BUSFAULTACT ((uint32_t)0x00000002) /*!< BusFault is active */
+#define SCB_SHCSR_USGFAULTACT ((uint32_t)0x00000008) /*!< UsageFault is active */
+#define SCB_SHCSR_SVCALLACT ((uint32_t)0x00000080) /*!< SVCall is active */
+#define SCB_SHCSR_MONITORACT ((uint32_t)0x00000100) /*!< Monitor is active */
+#define SCB_SHCSR_PENDSVACT ((uint32_t)0x00000400) /*!< PendSV is active */
+#define SCB_SHCSR_SYSTICKACT ((uint32_t)0x00000800) /*!< SysTick is active */
+#define SCB_SHCSR_USGFAULTPENDED ((uint32_t)0x00001000) /*!< Usage Fault is pended */
+#define SCB_SHCSR_MEMFAULTPENDED ((uint32_t)0x00002000) /*!< MemManage is pended */
+#define SCB_SHCSR_BUSFAULTPENDED ((uint32_t)0x00004000) /*!< Bus Fault is pended */
+#define SCB_SHCSR_SVCALLPENDED ((uint32_t)0x00008000) /*!< SVCall is pended */
+#define SCB_SHCSR_MEMFAULTENA ((uint32_t)0x00010000) /*!< MemManage enable */
+#define SCB_SHCSR_BUSFAULTENA ((uint32_t)0x00020000) /*!< Bus Fault enable */
+#define SCB_SHCSR_USGFAULTENA ((uint32_t)0x00040000) /*!< UsageFault enable */
+
+/******************* Bit definition for SCB_CFSR register *******************/
+/*!< MFSR */
+#define SCB_CFSR_IACCVIOL_Pos (0U)
+#define SCB_CFSR_IACCVIOL_Msk (0x1U << SCB_CFSR_IACCVIOL_Pos) /*!< 0x00000001 */
+#define SCB_CFSR_IACCVIOL SCB_CFSR_IACCVIOL_Msk /*!< Instruction access violation */
+#define SCB_CFSR_DACCVIOL_Pos (1U)
+#define SCB_CFSR_DACCVIOL_Msk (0x1U << SCB_CFSR_DACCVIOL_Pos) /*!< 0x00000002 */
+#define SCB_CFSR_DACCVIOL SCB_CFSR_DACCVIOL_Msk /*!< Data access violation */
+#define SCB_CFSR_MUNSTKERR_Pos (3U)
+#define SCB_CFSR_MUNSTKERR_Msk (0x1U << SCB_CFSR_MUNSTKERR_Pos) /*!< 0x00000008 */
+#define SCB_CFSR_MUNSTKERR SCB_CFSR_MUNSTKERR_Msk /*!< Unstacking error */
+#define SCB_CFSR_MSTKERR_Pos (4U)
+#define SCB_CFSR_MSTKERR_Msk (0x1U << SCB_CFSR_MSTKERR_Pos) /*!< 0x00000010 */
+#define SCB_CFSR_MSTKERR SCB_CFSR_MSTKERR_Msk /*!< Stacking error */
+#define SCB_CFSR_MMARVALID_Pos (7U)
+#define SCB_CFSR_MMARVALID_Msk (0x1U << SCB_CFSR_MMARVALID_Pos) /*!< 0x00000080 */
+#define SCB_CFSR_MMARVALID SCB_CFSR_MMARVALID_Msk /*!< Memory Manage Address Register address valid flag */
+/*!< BFSR */
+#define SCB_CFSR_IBUSERR_Pos (8U)
+#define SCB_CFSR_IBUSERR_Msk (0x1U << SCB_CFSR_IBUSERR_Pos) /*!< 0x00000100 */
+#define SCB_CFSR_IBUSERR SCB_CFSR_IBUSERR_Msk /*!< Instruction bus error flag */
+#define SCB_CFSR_PRECISERR_Pos (9U)
+#define SCB_CFSR_PRECISERR_Msk (0x1U << SCB_CFSR_PRECISERR_Pos) /*!< 0x00000200 */
+#define SCB_CFSR_PRECISERR SCB_CFSR_PRECISERR_Msk /*!< Precise data bus error */
+#define SCB_CFSR_IMPRECISERR_Pos (10U)
+#define SCB_CFSR_IMPRECISERR_Msk (0x1U << SCB_CFSR_IMPRECISERR_Pos) /*!< 0x00000400 */
+#define SCB_CFSR_IMPRECISERR SCB_CFSR_IMPRECISERR_Msk /*!< Imprecise data bus error */
+#define SCB_CFSR_UNSTKERR_Pos (11U)
+#define SCB_CFSR_UNSTKERR_Msk (0x1U << SCB_CFSR_UNSTKERR_Pos) /*!< 0x00000800 */
+#define SCB_CFSR_UNSTKERR SCB_CFSR_UNSTKERR_Msk /*!< Unstacking error */
+#define SCB_CFSR_STKERR_Pos (12U)
+#define SCB_CFSR_STKERR_Msk (0x1U << SCB_CFSR_STKERR_Pos) /*!< 0x00001000 */
+#define SCB_CFSR_STKERR SCB_CFSR_STKERR_Msk /*!< Stacking error */
+#define SCB_CFSR_BFARVALID_Pos (15U)
+#define SCB_CFSR_BFARVALID_Msk (0x1U << SCB_CFSR_BFARVALID_Pos) /*!< 0x00008000 */
+#define SCB_CFSR_BFARVALID SCB_CFSR_BFARVALID_Msk /*!< Bus Fault Address Register address valid flag */
+/*!< UFSR */
+#define SCB_CFSR_UNDEFINSTR_Pos (16U)
+#define SCB_CFSR_UNDEFINSTR_Msk (0x1U << SCB_CFSR_UNDEFINSTR_Pos) /*!< 0x00010000 */
+#define SCB_CFSR_UNDEFINSTR SCB_CFSR_UNDEFINSTR_Msk /*!< The processor attempt to execute an undefined instruction */
+#define SCB_CFSR_INVSTATE_Pos (17U)
+#define SCB_CFSR_INVSTATE_Msk (0x1U << SCB_CFSR_INVSTATE_Pos) /*!< 0x00020000 */
+#define SCB_CFSR_INVSTATE SCB_CFSR_INVSTATE_Msk /*!< Invalid combination of EPSR and instruction */
+#define SCB_CFSR_INVPC_Pos (18U)
+#define SCB_CFSR_INVPC_Msk (0x1U << SCB_CFSR_INVPC_Pos) /*!< 0x00040000 */
+#define SCB_CFSR_INVPC SCB_CFSR_INVPC_Msk /*!< Attempt to load EXC_RETURN into pc illegally */
+#define SCB_CFSR_NOCP_Pos (19U)
+#define SCB_CFSR_NOCP_Msk (0x1U << SCB_CFSR_NOCP_Pos) /*!< 0x00080000 */
+#define SCB_CFSR_NOCP SCB_CFSR_NOCP_Msk /*!< Attempt to use a coprocessor instruction */
+#define SCB_CFSR_UNALIGNED_Pos (24U)
+#define SCB_CFSR_UNALIGNED_Msk (0x1U << SCB_CFSR_UNALIGNED_Pos) /*!< 0x01000000 */
+#define SCB_CFSR_UNALIGNED SCB_CFSR_UNALIGNED_Msk /*!< Fault occurs when there is an attempt to make an unaligned memory access */
+#define SCB_CFSR_DIVBYZERO_Pos (25U)
+#define SCB_CFSR_DIVBYZERO_Msk (0x1U << SCB_CFSR_DIVBYZERO_Pos) /*!< 0x02000000 */
+#define SCB_CFSR_DIVBYZERO SCB_CFSR_DIVBYZERO_Msk /*!< Fault occurs when SDIV or DIV instruction is used with a divisor of 0 */
+
+/******************* Bit definition for SCB_HFSR register *******************/
+#define SCB_HFSR_VECTTBL ((uint32_t)0x00000002) /*!< Fault occurs because of vector table read on exception processing */
+#define SCB_HFSR_FORCED ((uint32_t)0x40000000) /*!< Hard Fault activated when a configurable Fault was received and cannot activate */
+#define SCB_HFSR_DEBUGEVT ((uint32_t)0x80000000) /*!< Fault related to debug */
+
+/******************* Bit definition for SCB_DFSR register *******************/
+#define SCB_DFSR_HALTED ((uint32_t)0x00000001) /*!< Halt request flag */
+#define SCB_DFSR_BKPT ((uint32_t)0x00000002) /*!< BKPT flag */
+#define SCB_DFSR_DWTTRAP ((uint32_t)0x00000004) /*!< Data Watchpoint and Trace (DWT) flag */
+#define SCB_DFSR_VCATCH ((uint32_t)0x00000008) /*!< Vector catch flag */
+#define SCB_DFSR_EXTERNAL ((uint32_t)0x00000010) /*!< External debug request flag */
+
+/******************* Bit definition for SCB_MMFAR register ******************/
+#define SCB_MMFAR_ADDRESS_Pos (0U)
+#define SCB_MMFAR_ADDRESS_Msk (0xFFFFFFFFU << SCB_MMFAR_ADDRESS_Pos) /*!< 0xFFFFFFFF */
+#define SCB_MMFAR_ADDRESS SCB_MMFAR_ADDRESS_Msk /*!< Mem Manage fault address field */
+
+/******************* Bit definition for SCB_BFAR register *******************/
+#define SCB_BFAR_ADDRESS_Pos (0U)
+#define SCB_BFAR_ADDRESS_Msk (0xFFFFFFFFU << SCB_BFAR_ADDRESS_Pos) /*!< 0xFFFFFFFF */
+#define SCB_BFAR_ADDRESS SCB_BFAR_ADDRESS_Msk /*!< Bus fault address field */
+
+/******************* Bit definition for SCB_afsr register *******************/
+#define SCB_AFSR_IMPDEF_Pos (0U)
+#define SCB_AFSR_IMPDEF_Msk (0xFFFFFFFFU << SCB_AFSR_IMPDEF_Pos) /*!< 0xFFFFFFFF */
+#define SCB_AFSR_IMPDEF SCB_AFSR_IMPDEF_Msk /*!< Implementation defined */
+
+/******************************************************************************/
+/* */
+/* External Interrupt/Event Controller */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for EXTI_IMR register *******************/
+#define EXTI_IMR_MR0_Pos (0U)
+#define EXTI_IMR_MR0_Msk (0x1U << EXTI_IMR_MR0_Pos) /*!< 0x00000001 */
+#define EXTI_IMR_MR0 EXTI_IMR_MR0_Msk /*!< Interrupt Mask on line 0 */
+#define EXTI_IMR_MR1_Pos (1U)
+#define EXTI_IMR_MR1_Msk (0x1U << EXTI_IMR_MR1_Pos) /*!< 0x00000002 */
+#define EXTI_IMR_MR1 EXTI_IMR_MR1_Msk /*!< Interrupt Mask on line 1 */
+#define EXTI_IMR_MR2_Pos (2U)
+#define EXTI_IMR_MR2_Msk (0x1U << EXTI_IMR_MR2_Pos) /*!< 0x00000004 */
+#define EXTI_IMR_MR2 EXTI_IMR_MR2_Msk /*!< Interrupt Mask on line 2 */
+#define EXTI_IMR_MR3_Pos (3U)
+#define EXTI_IMR_MR3_Msk (0x1U << EXTI_IMR_MR3_Pos) /*!< 0x00000008 */
+#define EXTI_IMR_MR3 EXTI_IMR_MR3_Msk /*!< Interrupt Mask on line 3 */
+#define EXTI_IMR_MR4_Pos (4U)
+#define EXTI_IMR_MR4_Msk (0x1U << EXTI_IMR_MR4_Pos) /*!< 0x00000010 */
+#define EXTI_IMR_MR4 EXTI_IMR_MR4_Msk /*!< Interrupt Mask on line 4 */
+#define EXTI_IMR_MR5_Pos (5U)
+#define EXTI_IMR_MR5_Msk (0x1U << EXTI_IMR_MR5_Pos) /*!< 0x00000020 */
+#define EXTI_IMR_MR5 EXTI_IMR_MR5_Msk /*!< Interrupt Mask on line 5 */
+#define EXTI_IMR_MR6_Pos (6U)
+#define EXTI_IMR_MR6_Msk (0x1U << EXTI_IMR_MR6_Pos) /*!< 0x00000040 */
+#define EXTI_IMR_MR6 EXTI_IMR_MR6_Msk /*!< Interrupt Mask on line 6 */
+#define EXTI_IMR_MR7_Pos (7U)
+#define EXTI_IMR_MR7_Msk (0x1U << EXTI_IMR_MR7_Pos) /*!< 0x00000080 */
+#define EXTI_IMR_MR7 EXTI_IMR_MR7_Msk /*!< Interrupt Mask on line 7 */
+#define EXTI_IMR_MR8_Pos (8U)
+#define EXTI_IMR_MR8_Msk (0x1U << EXTI_IMR_MR8_Pos) /*!< 0x00000100 */
+#define EXTI_IMR_MR8 EXTI_IMR_MR8_Msk /*!< Interrupt Mask on line 8 */
+#define EXTI_IMR_MR9_Pos (9U)
+#define EXTI_IMR_MR9_Msk (0x1U << EXTI_IMR_MR9_Pos) /*!< 0x00000200 */
+#define EXTI_IMR_MR9 EXTI_IMR_MR9_Msk /*!< Interrupt Mask on line 9 */
+#define EXTI_IMR_MR10_Pos (10U)
+#define EXTI_IMR_MR10_Msk (0x1U << EXTI_IMR_MR10_Pos) /*!< 0x00000400 */
+#define EXTI_IMR_MR10 EXTI_IMR_MR10_Msk /*!< Interrupt Mask on line 10 */
+#define EXTI_IMR_MR11_Pos (11U)
+#define EXTI_IMR_MR11_Msk (0x1U << EXTI_IMR_MR11_Pos) /*!< 0x00000800 */
+#define EXTI_IMR_MR11 EXTI_IMR_MR11_Msk /*!< Interrupt Mask on line 11 */
+#define EXTI_IMR_MR12_Pos (12U)
+#define EXTI_IMR_MR12_Msk (0x1U << EXTI_IMR_MR12_Pos) /*!< 0x00001000 */
+#define EXTI_IMR_MR12 EXTI_IMR_MR12_Msk /*!< Interrupt Mask on line 12 */
+#define EXTI_IMR_MR13_Pos (13U)
+#define EXTI_IMR_MR13_Msk (0x1U << EXTI_IMR_MR13_Pos) /*!< 0x00002000 */
+#define EXTI_IMR_MR13 EXTI_IMR_MR13_Msk /*!< Interrupt Mask on line 13 */
+#define EXTI_IMR_MR14_Pos (14U)
+#define EXTI_IMR_MR14_Msk (0x1U << EXTI_IMR_MR14_Pos) /*!< 0x00004000 */
+#define EXTI_IMR_MR14 EXTI_IMR_MR14_Msk /*!< Interrupt Mask on line 14 */
+#define EXTI_IMR_MR15_Pos (15U)
+#define EXTI_IMR_MR15_Msk (0x1U << EXTI_IMR_MR15_Pos) /*!< 0x00008000 */
+#define EXTI_IMR_MR15 EXTI_IMR_MR15_Msk /*!< Interrupt Mask on line 15 */
+#define EXTI_IMR_MR16_Pos (16U)
+#define EXTI_IMR_MR16_Msk (0x1U << EXTI_IMR_MR16_Pos) /*!< 0x00010000 */
+#define EXTI_IMR_MR16 EXTI_IMR_MR16_Msk /*!< Interrupt Mask on line 16 */
+#define EXTI_IMR_MR17_Pos (17U)
+#define EXTI_IMR_MR17_Msk (0x1U << EXTI_IMR_MR17_Pos) /*!< 0x00020000 */
+#define EXTI_IMR_MR17 EXTI_IMR_MR17_Msk /*!< Interrupt Mask on line 17 */
+#define EXTI_IMR_MR18_Pos (18U)
+#define EXTI_IMR_MR18_Msk (0x1U << EXTI_IMR_MR18_Pos) /*!< 0x00040000 */
+#define EXTI_IMR_MR18 EXTI_IMR_MR18_Msk /*!< Interrupt Mask on line 18 */
+#define EXTI_IMR_MR19_Pos (19U)
+#define EXTI_IMR_MR19_Msk (0x1U << EXTI_IMR_MR19_Pos) /*!< 0x00080000 */
+#define EXTI_IMR_MR19 EXTI_IMR_MR19_Msk /*!< Interrupt Mask on line 19 */
+
+/* References Defines */
+#define EXTI_IMR_IM0 EXTI_IMR_MR0
+#define EXTI_IMR_IM1 EXTI_IMR_MR1
+#define EXTI_IMR_IM2 EXTI_IMR_MR2
+#define EXTI_IMR_IM3 EXTI_IMR_MR3
+#define EXTI_IMR_IM4 EXTI_IMR_MR4
+#define EXTI_IMR_IM5 EXTI_IMR_MR5
+#define EXTI_IMR_IM6 EXTI_IMR_MR6
+#define EXTI_IMR_IM7 EXTI_IMR_MR7
+#define EXTI_IMR_IM8 EXTI_IMR_MR8
+#define EXTI_IMR_IM9 EXTI_IMR_MR9
+#define EXTI_IMR_IM10 EXTI_IMR_MR10
+#define EXTI_IMR_IM11 EXTI_IMR_MR11
+#define EXTI_IMR_IM12 EXTI_IMR_MR12
+#define EXTI_IMR_IM13 EXTI_IMR_MR13
+#define EXTI_IMR_IM14 EXTI_IMR_MR14
+#define EXTI_IMR_IM15 EXTI_IMR_MR15
+#define EXTI_IMR_IM16 EXTI_IMR_MR16
+#define EXTI_IMR_IM17 EXTI_IMR_MR17
+#define EXTI_IMR_IM18 EXTI_IMR_MR18
+#define EXTI_IMR_IM19 EXTI_IMR_MR19
+
+/******************* Bit definition for EXTI_EMR register *******************/
+#define EXTI_EMR_MR0_Pos (0U)
+#define EXTI_EMR_MR0_Msk (0x1U << EXTI_EMR_MR0_Pos) /*!< 0x00000001 */
+#define EXTI_EMR_MR0 EXTI_EMR_MR0_Msk /*!< Event Mask on line 0 */
+#define EXTI_EMR_MR1_Pos (1U)
+#define EXTI_EMR_MR1_Msk (0x1U << EXTI_EMR_MR1_Pos) /*!< 0x00000002 */
+#define EXTI_EMR_MR1 EXTI_EMR_MR1_Msk /*!< Event Mask on line 1 */
+#define EXTI_EMR_MR2_Pos (2U)
+#define EXTI_EMR_MR2_Msk (0x1U << EXTI_EMR_MR2_Pos) /*!< 0x00000004 */
+#define EXTI_EMR_MR2 EXTI_EMR_MR2_Msk /*!< Event Mask on line 2 */
+#define EXTI_EMR_MR3_Pos (3U)
+#define EXTI_EMR_MR3_Msk (0x1U << EXTI_EMR_MR3_Pos) /*!< 0x00000008 */
+#define EXTI_EMR_MR3 EXTI_EMR_MR3_Msk /*!< Event Mask on line 3 */
+#define EXTI_EMR_MR4_Pos (4U)
+#define EXTI_EMR_MR4_Msk (0x1U << EXTI_EMR_MR4_Pos) /*!< 0x00000010 */
+#define EXTI_EMR_MR4 EXTI_EMR_MR4_Msk /*!< Event Mask on line 4 */
+#define EXTI_EMR_MR5_Pos (5U)
+#define EXTI_EMR_MR5_Msk (0x1U << EXTI_EMR_MR5_Pos) /*!< 0x00000020 */
+#define EXTI_EMR_MR5 EXTI_EMR_MR5_Msk /*!< Event Mask on line 5 */
+#define EXTI_EMR_MR6_Pos (6U)
+#define EXTI_EMR_MR6_Msk (0x1U << EXTI_EMR_MR6_Pos) /*!< 0x00000040 */
+#define EXTI_EMR_MR6 EXTI_EMR_MR6_Msk /*!< Event Mask on line 6 */
+#define EXTI_EMR_MR7_Pos (7U)
+#define EXTI_EMR_MR7_Msk (0x1U << EXTI_EMR_MR7_Pos) /*!< 0x00000080 */
+#define EXTI_EMR_MR7 EXTI_EMR_MR7_Msk /*!< Event Mask on line 7 */
+#define EXTI_EMR_MR8_Pos (8U)
+#define EXTI_EMR_MR8_Msk (0x1U << EXTI_EMR_MR8_Pos) /*!< 0x00000100 */
+#define EXTI_EMR_MR8 EXTI_EMR_MR8_Msk /*!< Event Mask on line 8 */
+#define EXTI_EMR_MR9_Pos (9U)
+#define EXTI_EMR_MR9_Msk (0x1U << EXTI_EMR_MR9_Pos) /*!< 0x00000200 */
+#define EXTI_EMR_MR9 EXTI_EMR_MR9_Msk /*!< Event Mask on line 9 */
+#define EXTI_EMR_MR10_Pos (10U)
+#define EXTI_EMR_MR10_Msk (0x1U << EXTI_EMR_MR10_Pos) /*!< 0x00000400 */
+#define EXTI_EMR_MR10 EXTI_EMR_MR10_Msk /*!< Event Mask on line 10 */
+#define EXTI_EMR_MR11_Pos (11U)
+#define EXTI_EMR_MR11_Msk (0x1U << EXTI_EMR_MR11_Pos) /*!< 0x00000800 */
+#define EXTI_EMR_MR11 EXTI_EMR_MR11_Msk /*!< Event Mask on line 11 */
+#define EXTI_EMR_MR12_Pos (12U)
+#define EXTI_EMR_MR12_Msk (0x1U << EXTI_EMR_MR12_Pos) /*!< 0x00001000 */
+#define EXTI_EMR_MR12 EXTI_EMR_MR12_Msk /*!< Event Mask on line 12 */
+#define EXTI_EMR_MR13_Pos (13U)
+#define EXTI_EMR_MR13_Msk (0x1U << EXTI_EMR_MR13_Pos) /*!< 0x00002000 */
+#define EXTI_EMR_MR13 EXTI_EMR_MR13_Msk /*!< Event Mask on line 13 */
+#define EXTI_EMR_MR14_Pos (14U)
+#define EXTI_EMR_MR14_Msk (0x1U << EXTI_EMR_MR14_Pos) /*!< 0x00004000 */
+#define EXTI_EMR_MR14 EXTI_EMR_MR14_Msk /*!< Event Mask on line 14 */
+#define EXTI_EMR_MR15_Pos (15U)
+#define EXTI_EMR_MR15_Msk (0x1U << EXTI_EMR_MR15_Pos) /*!< 0x00008000 */
+#define EXTI_EMR_MR15 EXTI_EMR_MR15_Msk /*!< Event Mask on line 15 */
+#define EXTI_EMR_MR16_Pos (16U)
+#define EXTI_EMR_MR16_Msk (0x1U << EXTI_EMR_MR16_Pos) /*!< 0x00010000 */
+#define EXTI_EMR_MR16 EXTI_EMR_MR16_Msk /*!< Event Mask on line 16 */
+#define EXTI_EMR_MR17_Pos (17U)
+#define EXTI_EMR_MR17_Msk (0x1U << EXTI_EMR_MR17_Pos) /*!< 0x00020000 */
+#define EXTI_EMR_MR17 EXTI_EMR_MR17_Msk /*!< Event Mask on line 17 */
+#define EXTI_EMR_MR18_Pos (18U)
+#define EXTI_EMR_MR18_Msk (0x1U << EXTI_EMR_MR18_Pos) /*!< 0x00040000 */
+#define EXTI_EMR_MR18 EXTI_EMR_MR18_Msk /*!< Event Mask on line 18 */
+#define EXTI_EMR_MR19_Pos (19U)
+#define EXTI_EMR_MR19_Msk (0x1U << EXTI_EMR_MR19_Pos) /*!< 0x00080000 */
+#define EXTI_EMR_MR19 EXTI_EMR_MR19_Msk /*!< Event Mask on line 19 */
+
+/* References Defines */
+#define EXTI_EMR_EM0 EXTI_EMR_MR0
+#define EXTI_EMR_EM1 EXTI_EMR_MR1
+#define EXTI_EMR_EM2 EXTI_EMR_MR2
+#define EXTI_EMR_EM3 EXTI_EMR_MR3
+#define EXTI_EMR_EM4 EXTI_EMR_MR4
+#define EXTI_EMR_EM5 EXTI_EMR_MR5
+#define EXTI_EMR_EM6 EXTI_EMR_MR6
+#define EXTI_EMR_EM7 EXTI_EMR_MR7
+#define EXTI_EMR_EM8 EXTI_EMR_MR8
+#define EXTI_EMR_EM9 EXTI_EMR_MR9
+#define EXTI_EMR_EM10 EXTI_EMR_MR10
+#define EXTI_EMR_EM11 EXTI_EMR_MR11
+#define EXTI_EMR_EM12 EXTI_EMR_MR12
+#define EXTI_EMR_EM13 EXTI_EMR_MR13
+#define EXTI_EMR_EM14 EXTI_EMR_MR14
+#define EXTI_EMR_EM15 EXTI_EMR_MR15
+#define EXTI_EMR_EM16 EXTI_EMR_MR16
+#define EXTI_EMR_EM17 EXTI_EMR_MR17
+#define EXTI_EMR_EM18 EXTI_EMR_MR18
+#define EXTI_EMR_EM19 EXTI_EMR_MR19
+
+/****************** Bit definition for EXTI_RTSR register *******************/
+#define EXTI_RTSR_TR0_Pos (0U)
+#define EXTI_RTSR_TR0_Msk (0x1U << EXTI_RTSR_TR0_Pos) /*!< 0x00000001 */
+#define EXTI_RTSR_TR0 EXTI_RTSR_TR0_Msk /*!< Rising trigger event configuration bit of line 0 */
+#define EXTI_RTSR_TR1_Pos (1U)
+#define EXTI_RTSR_TR1_Msk (0x1U << EXTI_RTSR_TR1_Pos) /*!< 0x00000002 */
+#define EXTI_RTSR_TR1 EXTI_RTSR_TR1_Msk /*!< Rising trigger event configuration bit of line 1 */
+#define EXTI_RTSR_TR2_Pos (2U)
+#define EXTI_RTSR_TR2_Msk (0x1U << EXTI_RTSR_TR2_Pos) /*!< 0x00000004 */
+#define EXTI_RTSR_TR2 EXTI_RTSR_TR2_Msk /*!< Rising trigger event configuration bit of line 2 */
+#define EXTI_RTSR_TR3_Pos (3U)
+#define EXTI_RTSR_TR3_Msk (0x1U << EXTI_RTSR_TR3_Pos) /*!< 0x00000008 */
+#define EXTI_RTSR_TR3 EXTI_RTSR_TR3_Msk /*!< Rising trigger event configuration bit of line 3 */
+#define EXTI_RTSR_TR4_Pos (4U)
+#define EXTI_RTSR_TR4_Msk (0x1U << EXTI_RTSR_TR4_Pos) /*!< 0x00000010 */
+#define EXTI_RTSR_TR4 EXTI_RTSR_TR4_Msk /*!< Rising trigger event configuration bit of line 4 */
+#define EXTI_RTSR_TR5_Pos (5U)
+#define EXTI_RTSR_TR5_Msk (0x1U << EXTI_RTSR_TR5_Pos) /*!< 0x00000020 */
+#define EXTI_RTSR_TR5 EXTI_RTSR_TR5_Msk /*!< Rising trigger event configuration bit of line 5 */
+#define EXTI_RTSR_TR6_Pos (6U)
+#define EXTI_RTSR_TR6_Msk (0x1U << EXTI_RTSR_TR6_Pos) /*!< 0x00000040 */
+#define EXTI_RTSR_TR6 EXTI_RTSR_TR6_Msk /*!< Rising trigger event configuration bit of line 6 */
+#define EXTI_RTSR_TR7_Pos (7U)
+#define EXTI_RTSR_TR7_Msk (0x1U << EXTI_RTSR_TR7_Pos) /*!< 0x00000080 */
+#define EXTI_RTSR_TR7 EXTI_RTSR_TR7_Msk /*!< Rising trigger event configuration bit of line 7 */
+#define EXTI_RTSR_TR8_Pos (8U)
+#define EXTI_RTSR_TR8_Msk (0x1U << EXTI_RTSR_TR8_Pos) /*!< 0x00000100 */
+#define EXTI_RTSR_TR8 EXTI_RTSR_TR8_Msk /*!< Rising trigger event configuration bit of line 8 */
+#define EXTI_RTSR_TR9_Pos (9U)
+#define EXTI_RTSR_TR9_Msk (0x1U << EXTI_RTSR_TR9_Pos) /*!< 0x00000200 */
+#define EXTI_RTSR_TR9 EXTI_RTSR_TR9_Msk /*!< Rising trigger event configuration bit of line 9 */
+#define EXTI_RTSR_TR10_Pos (10U)
+#define EXTI_RTSR_TR10_Msk (0x1U << EXTI_RTSR_TR10_Pos) /*!< 0x00000400 */
+#define EXTI_RTSR_TR10 EXTI_RTSR_TR10_Msk /*!< Rising trigger event configuration bit of line 10 */
+#define EXTI_RTSR_TR11_Pos (11U)
+#define EXTI_RTSR_TR11_Msk (0x1U << EXTI_RTSR_TR11_Pos) /*!< 0x00000800 */
+#define EXTI_RTSR_TR11 EXTI_RTSR_TR11_Msk /*!< Rising trigger event configuration bit of line 11 */
+#define EXTI_RTSR_TR12_Pos (12U)
+#define EXTI_RTSR_TR12_Msk (0x1U << EXTI_RTSR_TR12_Pos) /*!< 0x00001000 */
+#define EXTI_RTSR_TR12 EXTI_RTSR_TR12_Msk /*!< Rising trigger event configuration bit of line 12 */
+#define EXTI_RTSR_TR13_Pos (13U)
+#define EXTI_RTSR_TR13_Msk (0x1U << EXTI_RTSR_TR13_Pos) /*!< 0x00002000 */
+#define EXTI_RTSR_TR13 EXTI_RTSR_TR13_Msk /*!< Rising trigger event configuration bit of line 13 */
+#define EXTI_RTSR_TR14_Pos (14U)
+#define EXTI_RTSR_TR14_Msk (0x1U << EXTI_RTSR_TR14_Pos) /*!< 0x00004000 */
+#define EXTI_RTSR_TR14 EXTI_RTSR_TR14_Msk /*!< Rising trigger event configuration bit of line 14 */
+#define EXTI_RTSR_TR15_Pos (15U)
+#define EXTI_RTSR_TR15_Msk (0x1U << EXTI_RTSR_TR15_Pos) /*!< 0x00008000 */
+#define EXTI_RTSR_TR15 EXTI_RTSR_TR15_Msk /*!< Rising trigger event configuration bit of line 15 */
+#define EXTI_RTSR_TR16_Pos (16U)
+#define EXTI_RTSR_TR16_Msk (0x1U << EXTI_RTSR_TR16_Pos) /*!< 0x00010000 */
+#define EXTI_RTSR_TR16 EXTI_RTSR_TR16_Msk /*!< Rising trigger event configuration bit of line 16 */
+#define EXTI_RTSR_TR17_Pos (17U)
+#define EXTI_RTSR_TR17_Msk (0x1U << EXTI_RTSR_TR17_Pos) /*!< 0x00020000 */
+#define EXTI_RTSR_TR17 EXTI_RTSR_TR17_Msk /*!< Rising trigger event configuration bit of line 17 */
+#define EXTI_RTSR_TR18_Pos (18U)
+#define EXTI_RTSR_TR18_Msk (0x1U << EXTI_RTSR_TR18_Pos) /*!< 0x00040000 */
+#define EXTI_RTSR_TR18 EXTI_RTSR_TR18_Msk /*!< Rising trigger event configuration bit of line 18 */
+#define EXTI_RTSR_TR19_Pos (19U)
+#define EXTI_RTSR_TR19_Msk (0x1U << EXTI_RTSR_TR19_Pos) /*!< 0x00080000 */
+#define EXTI_RTSR_TR19 EXTI_RTSR_TR19_Msk /*!< Rising trigger event configuration bit of line 19 */
+
+/* References Defines */
+#define EXTI_RTSR_RT0 EXTI_RTSR_TR0
+#define EXTI_RTSR_RT1 EXTI_RTSR_TR1
+#define EXTI_RTSR_RT2 EXTI_RTSR_TR2
+#define EXTI_RTSR_RT3 EXTI_RTSR_TR3
+#define EXTI_RTSR_RT4 EXTI_RTSR_TR4
+#define EXTI_RTSR_RT5 EXTI_RTSR_TR5
+#define EXTI_RTSR_RT6 EXTI_RTSR_TR6
+#define EXTI_RTSR_RT7 EXTI_RTSR_TR7
+#define EXTI_RTSR_RT8 EXTI_RTSR_TR8
+#define EXTI_RTSR_RT9 EXTI_RTSR_TR9
+#define EXTI_RTSR_RT10 EXTI_RTSR_TR10
+#define EXTI_RTSR_RT11 EXTI_RTSR_TR11
+#define EXTI_RTSR_RT12 EXTI_RTSR_TR12
+#define EXTI_RTSR_RT13 EXTI_RTSR_TR13
+#define EXTI_RTSR_RT14 EXTI_RTSR_TR14
+#define EXTI_RTSR_RT15 EXTI_RTSR_TR15
+#define EXTI_RTSR_RT16 EXTI_RTSR_TR16
+#define EXTI_RTSR_RT17 EXTI_RTSR_TR17
+#define EXTI_RTSR_RT18 EXTI_RTSR_TR18
+#define EXTI_RTSR_RT19 EXTI_RTSR_TR19
+
+/****************** Bit definition for EXTI_FTSR register *******************/
+#define EXTI_FTSR_TR0_Pos (0U)
+#define EXTI_FTSR_TR0_Msk (0x1U << EXTI_FTSR_TR0_Pos) /*!< 0x00000001 */
+#define EXTI_FTSR_TR0 EXTI_FTSR_TR0_Msk /*!< Falling trigger event configuration bit of line 0 */
+#define EXTI_FTSR_TR1_Pos (1U)
+#define EXTI_FTSR_TR1_Msk (0x1U << EXTI_FTSR_TR1_Pos) /*!< 0x00000002 */
+#define EXTI_FTSR_TR1 EXTI_FTSR_TR1_Msk /*!< Falling trigger event configuration bit of line 1 */
+#define EXTI_FTSR_TR2_Pos (2U)
+#define EXTI_FTSR_TR2_Msk (0x1U << EXTI_FTSR_TR2_Pos) /*!< 0x00000004 */
+#define EXTI_FTSR_TR2 EXTI_FTSR_TR2_Msk /*!< Falling trigger event configuration bit of line 2 */
+#define EXTI_FTSR_TR3_Pos (3U)
+#define EXTI_FTSR_TR3_Msk (0x1U << EXTI_FTSR_TR3_Pos) /*!< 0x00000008 */
+#define EXTI_FTSR_TR3 EXTI_FTSR_TR3_Msk /*!< Falling trigger event configuration bit of line 3 */
+#define EXTI_FTSR_TR4_Pos (4U)
+#define EXTI_FTSR_TR4_Msk (0x1U << EXTI_FTSR_TR4_Pos) /*!< 0x00000010 */
+#define EXTI_FTSR_TR4 EXTI_FTSR_TR4_Msk /*!< Falling trigger event configuration bit of line 4 */
+#define EXTI_FTSR_TR5_Pos (5U)
+#define EXTI_FTSR_TR5_Msk (0x1U << EXTI_FTSR_TR5_Pos) /*!< 0x00000020 */
+#define EXTI_FTSR_TR5 EXTI_FTSR_TR5_Msk /*!< Falling trigger event configuration bit of line 5 */
+#define EXTI_FTSR_TR6_Pos (6U)
+#define EXTI_FTSR_TR6_Msk (0x1U << EXTI_FTSR_TR6_Pos) /*!< 0x00000040 */
+#define EXTI_FTSR_TR6 EXTI_FTSR_TR6_Msk /*!< Falling trigger event configuration bit of line 6 */
+#define EXTI_FTSR_TR7_Pos (7U)
+#define EXTI_FTSR_TR7_Msk (0x1U << EXTI_FTSR_TR7_Pos) /*!< 0x00000080 */
+#define EXTI_FTSR_TR7 EXTI_FTSR_TR7_Msk /*!< Falling trigger event configuration bit of line 7 */
+#define EXTI_FTSR_TR8_Pos (8U)
+#define EXTI_FTSR_TR8_Msk (0x1U << EXTI_FTSR_TR8_Pos) /*!< 0x00000100 */
+#define EXTI_FTSR_TR8 EXTI_FTSR_TR8_Msk /*!< Falling trigger event configuration bit of line 8 */
+#define EXTI_FTSR_TR9_Pos (9U)
+#define EXTI_FTSR_TR9_Msk (0x1U << EXTI_FTSR_TR9_Pos) /*!< 0x00000200 */
+#define EXTI_FTSR_TR9 EXTI_FTSR_TR9_Msk /*!< Falling trigger event configuration bit of line 9 */
+#define EXTI_FTSR_TR10_Pos (10U)
+#define EXTI_FTSR_TR10_Msk (0x1U << EXTI_FTSR_TR10_Pos) /*!< 0x00000400 */
+#define EXTI_FTSR_TR10 EXTI_FTSR_TR10_Msk /*!< Falling trigger event configuration bit of line 10 */
+#define EXTI_FTSR_TR11_Pos (11U)
+#define EXTI_FTSR_TR11_Msk (0x1U << EXTI_FTSR_TR11_Pos) /*!< 0x00000800 */
+#define EXTI_FTSR_TR11 EXTI_FTSR_TR11_Msk /*!< Falling trigger event configuration bit of line 11 */
+#define EXTI_FTSR_TR12_Pos (12U)
+#define EXTI_FTSR_TR12_Msk (0x1U << EXTI_FTSR_TR12_Pos) /*!< 0x00001000 */
+#define EXTI_FTSR_TR12 EXTI_FTSR_TR12_Msk /*!< Falling trigger event configuration bit of line 12 */
+#define EXTI_FTSR_TR13_Pos (13U)
+#define EXTI_FTSR_TR13_Msk (0x1U << EXTI_FTSR_TR13_Pos) /*!< 0x00002000 */
+#define EXTI_FTSR_TR13 EXTI_FTSR_TR13_Msk /*!< Falling trigger event configuration bit of line 13 */
+#define EXTI_FTSR_TR14_Pos (14U)
+#define EXTI_FTSR_TR14_Msk (0x1U << EXTI_FTSR_TR14_Pos) /*!< 0x00004000 */
+#define EXTI_FTSR_TR14 EXTI_FTSR_TR14_Msk /*!< Falling trigger event configuration bit of line 14 */
+#define EXTI_FTSR_TR15_Pos (15U)
+#define EXTI_FTSR_TR15_Msk (0x1U << EXTI_FTSR_TR15_Pos) /*!< 0x00008000 */
+#define EXTI_FTSR_TR15 EXTI_FTSR_TR15_Msk /*!< Falling trigger event configuration bit of line 15 */
+#define EXTI_FTSR_TR16_Pos (16U)
+#define EXTI_FTSR_TR16_Msk (0x1U << EXTI_FTSR_TR16_Pos) /*!< 0x00010000 */
+#define EXTI_FTSR_TR16 EXTI_FTSR_TR16_Msk /*!< Falling trigger event configuration bit of line 16 */
+#define EXTI_FTSR_TR17_Pos (17U)
+#define EXTI_FTSR_TR17_Msk (0x1U << EXTI_FTSR_TR17_Pos) /*!< 0x00020000 */
+#define EXTI_FTSR_TR17 EXTI_FTSR_TR17_Msk /*!< Falling trigger event configuration bit of line 17 */
+#define EXTI_FTSR_TR18_Pos (18U)
+#define EXTI_FTSR_TR18_Msk (0x1U << EXTI_FTSR_TR18_Pos) /*!< 0x00040000 */
+#define EXTI_FTSR_TR18 EXTI_FTSR_TR18_Msk /*!< Falling trigger event configuration bit of line 18 */
+#define EXTI_FTSR_TR19_Pos (19U)
+#define EXTI_FTSR_TR19_Msk (0x1U << EXTI_FTSR_TR19_Pos) /*!< 0x00080000 */
+#define EXTI_FTSR_TR19 EXTI_FTSR_TR19_Msk /*!< Falling trigger event configuration bit of line 19 */
+
+/* References Defines */
+#define EXTI_FTSR_FT0 EXTI_FTSR_TR0
+#define EXTI_FTSR_FT1 EXTI_FTSR_TR1
+#define EXTI_FTSR_FT2 EXTI_FTSR_TR2
+#define EXTI_FTSR_FT3 EXTI_FTSR_TR3
+#define EXTI_FTSR_FT4 EXTI_FTSR_TR4
+#define EXTI_FTSR_FT5 EXTI_FTSR_TR5
+#define EXTI_FTSR_FT6 EXTI_FTSR_TR6
+#define EXTI_FTSR_FT7 EXTI_FTSR_TR7
+#define EXTI_FTSR_FT8 EXTI_FTSR_TR8
+#define EXTI_FTSR_FT9 EXTI_FTSR_TR9
+#define EXTI_FTSR_FT10 EXTI_FTSR_TR10
+#define EXTI_FTSR_FT11 EXTI_FTSR_TR11
+#define EXTI_FTSR_FT12 EXTI_FTSR_TR12
+#define EXTI_FTSR_FT13 EXTI_FTSR_TR13
+#define EXTI_FTSR_FT14 EXTI_FTSR_TR14
+#define EXTI_FTSR_FT15 EXTI_FTSR_TR15
+#define EXTI_FTSR_FT16 EXTI_FTSR_TR16
+#define EXTI_FTSR_FT17 EXTI_FTSR_TR17
+#define EXTI_FTSR_FT18 EXTI_FTSR_TR18
+#define EXTI_FTSR_FT19 EXTI_FTSR_TR19
+
+/****************** Bit definition for EXTI_SWIER register ******************/
+#define EXTI_SWIER_SWIER0_Pos (0U)
+#define EXTI_SWIER_SWIER0_Msk (0x1U << EXTI_SWIER_SWIER0_Pos) /*!< 0x00000001 */
+#define EXTI_SWIER_SWIER0 EXTI_SWIER_SWIER0_Msk /*!< Software Interrupt on line 0 */
+#define EXTI_SWIER_SWIER1_Pos (1U)
+#define EXTI_SWIER_SWIER1_Msk (0x1U << EXTI_SWIER_SWIER1_Pos) /*!< 0x00000002 */
+#define EXTI_SWIER_SWIER1 EXTI_SWIER_SWIER1_Msk /*!< Software Interrupt on line 1 */
+#define EXTI_SWIER_SWIER2_Pos (2U)
+#define EXTI_SWIER_SWIER2_Msk (0x1U << EXTI_SWIER_SWIER2_Pos) /*!< 0x00000004 */
+#define EXTI_SWIER_SWIER2 EXTI_SWIER_SWIER2_Msk /*!< Software Interrupt on line 2 */
+#define EXTI_SWIER_SWIER3_Pos (3U)
+#define EXTI_SWIER_SWIER3_Msk (0x1U << EXTI_SWIER_SWIER3_Pos) /*!< 0x00000008 */
+#define EXTI_SWIER_SWIER3 EXTI_SWIER_SWIER3_Msk /*!< Software Interrupt on line 3 */
+#define EXTI_SWIER_SWIER4_Pos (4U)
+#define EXTI_SWIER_SWIER4_Msk (0x1U << EXTI_SWIER_SWIER4_Pos) /*!< 0x00000010 */
+#define EXTI_SWIER_SWIER4 EXTI_SWIER_SWIER4_Msk /*!< Software Interrupt on line 4 */
+#define EXTI_SWIER_SWIER5_Pos (5U)
+#define EXTI_SWIER_SWIER5_Msk (0x1U << EXTI_SWIER_SWIER5_Pos) /*!< 0x00000020 */
+#define EXTI_SWIER_SWIER5 EXTI_SWIER_SWIER5_Msk /*!< Software Interrupt on line 5 */
+#define EXTI_SWIER_SWIER6_Pos (6U)
+#define EXTI_SWIER_SWIER6_Msk (0x1U << EXTI_SWIER_SWIER6_Pos) /*!< 0x00000040 */
+#define EXTI_SWIER_SWIER6 EXTI_SWIER_SWIER6_Msk /*!< Software Interrupt on line 6 */
+#define EXTI_SWIER_SWIER7_Pos (7U)
+#define EXTI_SWIER_SWIER7_Msk (0x1U << EXTI_SWIER_SWIER7_Pos) /*!< 0x00000080 */
+#define EXTI_SWIER_SWIER7 EXTI_SWIER_SWIER7_Msk /*!< Software Interrupt on line 7 */
+#define EXTI_SWIER_SWIER8_Pos (8U)
+#define EXTI_SWIER_SWIER8_Msk (0x1U << EXTI_SWIER_SWIER8_Pos) /*!< 0x00000100 */
+#define EXTI_SWIER_SWIER8 EXTI_SWIER_SWIER8_Msk /*!< Software Interrupt on line 8 */
+#define EXTI_SWIER_SWIER9_Pos (9U)
+#define EXTI_SWIER_SWIER9_Msk (0x1U << EXTI_SWIER_SWIER9_Pos) /*!< 0x00000200 */
+#define EXTI_SWIER_SWIER9 EXTI_SWIER_SWIER9_Msk /*!< Software Interrupt on line 9 */
+#define EXTI_SWIER_SWIER10_Pos (10U)
+#define EXTI_SWIER_SWIER10_Msk (0x1U << EXTI_SWIER_SWIER10_Pos) /*!< 0x00000400 */
+#define EXTI_SWIER_SWIER10 EXTI_SWIER_SWIER10_Msk /*!< Software Interrupt on line 10 */
+#define EXTI_SWIER_SWIER11_Pos (11U)
+#define EXTI_SWIER_SWIER11_Msk (0x1U << EXTI_SWIER_SWIER11_Pos) /*!< 0x00000800 */
+#define EXTI_SWIER_SWIER11 EXTI_SWIER_SWIER11_Msk /*!< Software Interrupt on line 11 */
+#define EXTI_SWIER_SWIER12_Pos (12U)
+#define EXTI_SWIER_SWIER12_Msk (0x1U << EXTI_SWIER_SWIER12_Pos) /*!< 0x00001000 */
+#define EXTI_SWIER_SWIER12 EXTI_SWIER_SWIER12_Msk /*!< Software Interrupt on line 12 */
+#define EXTI_SWIER_SWIER13_Pos (13U)
+#define EXTI_SWIER_SWIER13_Msk (0x1U << EXTI_SWIER_SWIER13_Pos) /*!< 0x00002000 */
+#define EXTI_SWIER_SWIER13 EXTI_SWIER_SWIER13_Msk /*!< Software Interrupt on line 13 */
+#define EXTI_SWIER_SWIER14_Pos (14U)
+#define EXTI_SWIER_SWIER14_Msk (0x1U << EXTI_SWIER_SWIER14_Pos) /*!< 0x00004000 */
+#define EXTI_SWIER_SWIER14 EXTI_SWIER_SWIER14_Msk /*!< Software Interrupt on line 14 */
+#define EXTI_SWIER_SWIER15_Pos (15U)
+#define EXTI_SWIER_SWIER15_Msk (0x1U << EXTI_SWIER_SWIER15_Pos) /*!< 0x00008000 */
+#define EXTI_SWIER_SWIER15 EXTI_SWIER_SWIER15_Msk /*!< Software Interrupt on line 15 */
+#define EXTI_SWIER_SWIER16_Pos (16U)
+#define EXTI_SWIER_SWIER16_Msk (0x1U << EXTI_SWIER_SWIER16_Pos) /*!< 0x00010000 */
+#define EXTI_SWIER_SWIER16 EXTI_SWIER_SWIER16_Msk /*!< Software Interrupt on line 16 */
+#define EXTI_SWIER_SWIER17_Pos (17U)
+#define EXTI_SWIER_SWIER17_Msk (0x1U << EXTI_SWIER_SWIER17_Pos) /*!< 0x00020000 */
+#define EXTI_SWIER_SWIER17 EXTI_SWIER_SWIER17_Msk /*!< Software Interrupt on line 17 */
+#define EXTI_SWIER_SWIER18_Pos (18U)
+#define EXTI_SWIER_SWIER18_Msk (0x1U << EXTI_SWIER_SWIER18_Pos) /*!< 0x00040000 */
+#define EXTI_SWIER_SWIER18 EXTI_SWIER_SWIER18_Msk /*!< Software Interrupt on line 18 */
+#define EXTI_SWIER_SWIER19_Pos (19U)
+#define EXTI_SWIER_SWIER19_Msk (0x1U << EXTI_SWIER_SWIER19_Pos) /*!< 0x00080000 */
+#define EXTI_SWIER_SWIER19 EXTI_SWIER_SWIER19_Msk /*!< Software Interrupt on line 19 */
+
+/* References Defines */
+#define EXTI_SWIER_SWI0 EXTI_SWIER_SWIER0
+#define EXTI_SWIER_SWI1 EXTI_SWIER_SWIER1
+#define EXTI_SWIER_SWI2 EXTI_SWIER_SWIER2
+#define EXTI_SWIER_SWI3 EXTI_SWIER_SWIER3
+#define EXTI_SWIER_SWI4 EXTI_SWIER_SWIER4
+#define EXTI_SWIER_SWI5 EXTI_SWIER_SWIER5
+#define EXTI_SWIER_SWI6 EXTI_SWIER_SWIER6
+#define EXTI_SWIER_SWI7 EXTI_SWIER_SWIER7
+#define EXTI_SWIER_SWI8 EXTI_SWIER_SWIER8
+#define EXTI_SWIER_SWI9 EXTI_SWIER_SWIER9
+#define EXTI_SWIER_SWI10 EXTI_SWIER_SWIER10
+#define EXTI_SWIER_SWI11 EXTI_SWIER_SWIER11
+#define EXTI_SWIER_SWI12 EXTI_SWIER_SWIER12
+#define EXTI_SWIER_SWI13 EXTI_SWIER_SWIER13
+#define EXTI_SWIER_SWI14 EXTI_SWIER_SWIER14
+#define EXTI_SWIER_SWI15 EXTI_SWIER_SWIER15
+#define EXTI_SWIER_SWI16 EXTI_SWIER_SWIER16
+#define EXTI_SWIER_SWI17 EXTI_SWIER_SWIER17
+#define EXTI_SWIER_SWI18 EXTI_SWIER_SWIER18
+#define EXTI_SWIER_SWI19 EXTI_SWIER_SWIER19
+
+/******************* Bit definition for EXTI_PR register ********************/
+#define EXTI_PR_PR0_Pos (0U)
+#define EXTI_PR_PR0_Msk (0x1U << EXTI_PR_PR0_Pos) /*!< 0x00000001 */
+#define EXTI_PR_PR0 EXTI_PR_PR0_Msk /*!< Pending bit for line 0 */
+#define EXTI_PR_PR1_Pos (1U)
+#define EXTI_PR_PR1_Msk (0x1U << EXTI_PR_PR1_Pos) /*!< 0x00000002 */
+#define EXTI_PR_PR1 EXTI_PR_PR1_Msk /*!< Pending bit for line 1 */
+#define EXTI_PR_PR2_Pos (2U)
+#define EXTI_PR_PR2_Msk (0x1U << EXTI_PR_PR2_Pos) /*!< 0x00000004 */
+#define EXTI_PR_PR2 EXTI_PR_PR2_Msk /*!< Pending bit for line 2 */
+#define EXTI_PR_PR3_Pos (3U)
+#define EXTI_PR_PR3_Msk (0x1U << EXTI_PR_PR3_Pos) /*!< 0x00000008 */
+#define EXTI_PR_PR3 EXTI_PR_PR3_Msk /*!< Pending bit for line 3 */
+#define EXTI_PR_PR4_Pos (4U)
+#define EXTI_PR_PR4_Msk (0x1U << EXTI_PR_PR4_Pos) /*!< 0x00000010 */
+#define EXTI_PR_PR4 EXTI_PR_PR4_Msk /*!< Pending bit for line 4 */
+#define EXTI_PR_PR5_Pos (5U)
+#define EXTI_PR_PR5_Msk (0x1U << EXTI_PR_PR5_Pos) /*!< 0x00000020 */
+#define EXTI_PR_PR5 EXTI_PR_PR5_Msk /*!< Pending bit for line 5 */
+#define EXTI_PR_PR6_Pos (6U)
+#define EXTI_PR_PR6_Msk (0x1U << EXTI_PR_PR6_Pos) /*!< 0x00000040 */
+#define EXTI_PR_PR6 EXTI_PR_PR6_Msk /*!< Pending bit for line 6 */
+#define EXTI_PR_PR7_Pos (7U)
+#define EXTI_PR_PR7_Msk (0x1U << EXTI_PR_PR7_Pos) /*!< 0x00000080 */
+#define EXTI_PR_PR7 EXTI_PR_PR7_Msk /*!< Pending bit for line 7 */
+#define EXTI_PR_PR8_Pos (8U)
+#define EXTI_PR_PR8_Msk (0x1U << EXTI_PR_PR8_Pos) /*!< 0x00000100 */
+#define EXTI_PR_PR8 EXTI_PR_PR8_Msk /*!< Pending bit for line 8 */
+#define EXTI_PR_PR9_Pos (9U)
+#define EXTI_PR_PR9_Msk (0x1U << EXTI_PR_PR9_Pos) /*!< 0x00000200 */
+#define EXTI_PR_PR9 EXTI_PR_PR9_Msk /*!< Pending bit for line 9 */
+#define EXTI_PR_PR10_Pos (10U)
+#define EXTI_PR_PR10_Msk (0x1U << EXTI_PR_PR10_Pos) /*!< 0x00000400 */
+#define EXTI_PR_PR10 EXTI_PR_PR10_Msk /*!< Pending bit for line 10 */
+#define EXTI_PR_PR11_Pos (11U)
+#define EXTI_PR_PR11_Msk (0x1U << EXTI_PR_PR11_Pos) /*!< 0x00000800 */
+#define EXTI_PR_PR11 EXTI_PR_PR11_Msk /*!< Pending bit for line 11 */
+#define EXTI_PR_PR12_Pos (12U)
+#define EXTI_PR_PR12_Msk (0x1U << EXTI_PR_PR12_Pos) /*!< 0x00001000 */
+#define EXTI_PR_PR12 EXTI_PR_PR12_Msk /*!< Pending bit for line 12 */
+#define EXTI_PR_PR13_Pos (13U)
+#define EXTI_PR_PR13_Msk (0x1U << EXTI_PR_PR13_Pos) /*!< 0x00002000 */
+#define EXTI_PR_PR13 EXTI_PR_PR13_Msk /*!< Pending bit for line 13 */
+#define EXTI_PR_PR14_Pos (14U)
+#define EXTI_PR_PR14_Msk (0x1U << EXTI_PR_PR14_Pos) /*!< 0x00004000 */
+#define EXTI_PR_PR14 EXTI_PR_PR14_Msk /*!< Pending bit for line 14 */
+#define EXTI_PR_PR15_Pos (15U)
+#define EXTI_PR_PR15_Msk (0x1U << EXTI_PR_PR15_Pos) /*!< 0x00008000 */
+#define EXTI_PR_PR15 EXTI_PR_PR15_Msk /*!< Pending bit for line 15 */
+#define EXTI_PR_PR16_Pos (16U)
+#define EXTI_PR_PR16_Msk (0x1U << EXTI_PR_PR16_Pos) /*!< 0x00010000 */
+#define EXTI_PR_PR16 EXTI_PR_PR16_Msk /*!< Pending bit for line 16 */
+#define EXTI_PR_PR17_Pos (17U)
+#define EXTI_PR_PR17_Msk (0x1U << EXTI_PR_PR17_Pos) /*!< 0x00020000 */
+#define EXTI_PR_PR17 EXTI_PR_PR17_Msk /*!< Pending bit for line 17 */
+#define EXTI_PR_PR18_Pos (18U)
+#define EXTI_PR_PR18_Msk (0x1U << EXTI_PR_PR18_Pos) /*!< 0x00040000 */
+#define EXTI_PR_PR18 EXTI_PR_PR18_Msk /*!< Pending bit for line 18 */
+#define EXTI_PR_PR19_Pos (19U)
+#define EXTI_PR_PR19_Msk (0x1U << EXTI_PR_PR19_Pos) /*!< 0x00080000 */
+#define EXTI_PR_PR19 EXTI_PR_PR19_Msk /*!< Pending bit for line 19 */
+
+/* References Defines */
+#define EXTI_PR_PIF0 EXTI_PR_PR0
+#define EXTI_PR_PIF1 EXTI_PR_PR1
+#define EXTI_PR_PIF2 EXTI_PR_PR2
+#define EXTI_PR_PIF3 EXTI_PR_PR3
+#define EXTI_PR_PIF4 EXTI_PR_PR4
+#define EXTI_PR_PIF5 EXTI_PR_PR5
+#define EXTI_PR_PIF6 EXTI_PR_PR6
+#define EXTI_PR_PIF7 EXTI_PR_PR7
+#define EXTI_PR_PIF8 EXTI_PR_PR8
+#define EXTI_PR_PIF9 EXTI_PR_PR9
+#define EXTI_PR_PIF10 EXTI_PR_PR10
+#define EXTI_PR_PIF11 EXTI_PR_PR11
+#define EXTI_PR_PIF12 EXTI_PR_PR12
+#define EXTI_PR_PIF13 EXTI_PR_PR13
+#define EXTI_PR_PIF14 EXTI_PR_PR14
+#define EXTI_PR_PIF15 EXTI_PR_PR15
+#define EXTI_PR_PIF16 EXTI_PR_PR16
+#define EXTI_PR_PIF17 EXTI_PR_PR17
+#define EXTI_PR_PIF18 EXTI_PR_PR18
+#define EXTI_PR_PIF19 EXTI_PR_PR19
+
+/******************************************************************************/
+/* */
+/* DMA Controller */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for DMA_ISR register ********************/
+#define DMA_ISR_GIF1_Pos (0U)
+#define DMA_ISR_GIF1_Msk (0x1U << DMA_ISR_GIF1_Pos) /*!< 0x00000001 */
+#define DMA_ISR_GIF1 DMA_ISR_GIF1_Msk /*!< Channel 1 Global interrupt flag */
+#define DMA_ISR_TCIF1_Pos (1U)
+#define DMA_ISR_TCIF1_Msk (0x1U << DMA_ISR_TCIF1_Pos) /*!< 0x00000002 */
+#define DMA_ISR_TCIF1 DMA_ISR_TCIF1_Msk /*!< Channel 1 Transfer Complete flag */
+#define DMA_ISR_HTIF1_Pos (2U)
+#define DMA_ISR_HTIF1_Msk (0x1U << DMA_ISR_HTIF1_Pos) /*!< 0x00000004 */
+#define DMA_ISR_HTIF1 DMA_ISR_HTIF1_Msk /*!< Channel 1 Half Transfer flag */
+#define DMA_ISR_TEIF1_Pos (3U)
+#define DMA_ISR_TEIF1_Msk (0x1U << DMA_ISR_TEIF1_Pos) /*!< 0x00000008 */
+#define DMA_ISR_TEIF1 DMA_ISR_TEIF1_Msk /*!< Channel 1 Transfer Error flag */
+#define DMA_ISR_GIF2_Pos (4U)
+#define DMA_ISR_GIF2_Msk (0x1U << DMA_ISR_GIF2_Pos) /*!< 0x00000010 */
+#define DMA_ISR_GIF2 DMA_ISR_GIF2_Msk /*!< Channel 2 Global interrupt flag */
+#define DMA_ISR_TCIF2_Pos (5U)
+#define DMA_ISR_TCIF2_Msk (0x1U << DMA_ISR_TCIF2_Pos) /*!< 0x00000020 */
+#define DMA_ISR_TCIF2 DMA_ISR_TCIF2_Msk /*!< Channel 2 Transfer Complete flag */
+#define DMA_ISR_HTIF2_Pos (6U)
+#define DMA_ISR_HTIF2_Msk (0x1U << DMA_ISR_HTIF2_Pos) /*!< 0x00000040 */
+#define DMA_ISR_HTIF2 DMA_ISR_HTIF2_Msk /*!< Channel 2 Half Transfer flag */
+#define DMA_ISR_TEIF2_Pos (7U)
+#define DMA_ISR_TEIF2_Msk (0x1U << DMA_ISR_TEIF2_Pos) /*!< 0x00000080 */
+#define DMA_ISR_TEIF2 DMA_ISR_TEIF2_Msk /*!< Channel 2 Transfer Error flag */
+#define DMA_ISR_GIF3_Pos (8U)
+#define DMA_ISR_GIF3_Msk (0x1U << DMA_ISR_GIF3_Pos) /*!< 0x00000100 */
+#define DMA_ISR_GIF3 DMA_ISR_GIF3_Msk /*!< Channel 3 Global interrupt flag */
+#define DMA_ISR_TCIF3_Pos (9U)
+#define DMA_ISR_TCIF3_Msk (0x1U << DMA_ISR_TCIF3_Pos) /*!< 0x00000200 */
+#define DMA_ISR_TCIF3 DMA_ISR_TCIF3_Msk /*!< Channel 3 Transfer Complete flag */
+#define DMA_ISR_HTIF3_Pos (10U)
+#define DMA_ISR_HTIF3_Msk (0x1U << DMA_ISR_HTIF3_Pos) /*!< 0x00000400 */
+#define DMA_ISR_HTIF3 DMA_ISR_HTIF3_Msk /*!< Channel 3 Half Transfer flag */
+#define DMA_ISR_TEIF3_Pos (11U)
+#define DMA_ISR_TEIF3_Msk (0x1U << DMA_ISR_TEIF3_Pos) /*!< 0x00000800 */
+#define DMA_ISR_TEIF3 DMA_ISR_TEIF3_Msk /*!< Channel 3 Transfer Error flag */
+#define DMA_ISR_GIF4_Pos (12U)
+#define DMA_ISR_GIF4_Msk (0x1U << DMA_ISR_GIF4_Pos) /*!< 0x00001000 */
+#define DMA_ISR_GIF4 DMA_ISR_GIF4_Msk /*!< Channel 4 Global interrupt flag */
+#define DMA_ISR_TCIF4_Pos (13U)
+#define DMA_ISR_TCIF4_Msk (0x1U << DMA_ISR_TCIF4_Pos) /*!< 0x00002000 */
+#define DMA_ISR_TCIF4 DMA_ISR_TCIF4_Msk /*!< Channel 4 Transfer Complete flag */
+#define DMA_ISR_HTIF4_Pos (14U)
+#define DMA_ISR_HTIF4_Msk (0x1U << DMA_ISR_HTIF4_Pos) /*!< 0x00004000 */
+#define DMA_ISR_HTIF4 DMA_ISR_HTIF4_Msk /*!< Channel 4 Half Transfer flag */
+#define DMA_ISR_TEIF4_Pos (15U)
+#define DMA_ISR_TEIF4_Msk (0x1U << DMA_ISR_TEIF4_Pos) /*!< 0x00008000 */
+#define DMA_ISR_TEIF4 DMA_ISR_TEIF4_Msk /*!< Channel 4 Transfer Error flag */
+#define DMA_ISR_GIF5_Pos (16U)
+#define DMA_ISR_GIF5_Msk (0x1U << DMA_ISR_GIF5_Pos) /*!< 0x00010000 */
+#define DMA_ISR_GIF5 DMA_ISR_GIF5_Msk /*!< Channel 5 Global interrupt flag */
+#define DMA_ISR_TCIF5_Pos (17U)
+#define DMA_ISR_TCIF5_Msk (0x1U << DMA_ISR_TCIF5_Pos) /*!< 0x00020000 */
+#define DMA_ISR_TCIF5 DMA_ISR_TCIF5_Msk /*!< Channel 5 Transfer Complete flag */
+#define DMA_ISR_HTIF5_Pos (18U)
+#define DMA_ISR_HTIF5_Msk (0x1U << DMA_ISR_HTIF5_Pos) /*!< 0x00040000 */
+#define DMA_ISR_HTIF5 DMA_ISR_HTIF5_Msk /*!< Channel 5 Half Transfer flag */
+#define DMA_ISR_TEIF5_Pos (19U)
+#define DMA_ISR_TEIF5_Msk (0x1U << DMA_ISR_TEIF5_Pos) /*!< 0x00080000 */
+#define DMA_ISR_TEIF5 DMA_ISR_TEIF5_Msk /*!< Channel 5 Transfer Error flag */
+#define DMA_ISR_GIF6_Pos (20U)
+#define DMA_ISR_GIF6_Msk (0x1U << DMA_ISR_GIF6_Pos) /*!< 0x00100000 */
+#define DMA_ISR_GIF6 DMA_ISR_GIF6_Msk /*!< Channel 6 Global interrupt flag */
+#define DMA_ISR_TCIF6_Pos (21U)
+#define DMA_ISR_TCIF6_Msk (0x1U << DMA_ISR_TCIF6_Pos) /*!< 0x00200000 */
+#define DMA_ISR_TCIF6 DMA_ISR_TCIF6_Msk /*!< Channel 6 Transfer Complete flag */
+#define DMA_ISR_HTIF6_Pos (22U)
+#define DMA_ISR_HTIF6_Msk (0x1U << DMA_ISR_HTIF6_Pos) /*!< 0x00400000 */
+#define DMA_ISR_HTIF6 DMA_ISR_HTIF6_Msk /*!< Channel 6 Half Transfer flag */
+#define DMA_ISR_TEIF6_Pos (23U)
+#define DMA_ISR_TEIF6_Msk (0x1U << DMA_ISR_TEIF6_Pos) /*!< 0x00800000 */
+#define DMA_ISR_TEIF6 DMA_ISR_TEIF6_Msk /*!< Channel 6 Transfer Error flag */
+#define DMA_ISR_GIF7_Pos (24U)
+#define DMA_ISR_GIF7_Msk (0x1U << DMA_ISR_GIF7_Pos) /*!< 0x01000000 */
+#define DMA_ISR_GIF7 DMA_ISR_GIF7_Msk /*!< Channel 7 Global interrupt flag */
+#define DMA_ISR_TCIF7_Pos (25U)
+#define DMA_ISR_TCIF7_Msk (0x1U << DMA_ISR_TCIF7_Pos) /*!< 0x02000000 */
+#define DMA_ISR_TCIF7 DMA_ISR_TCIF7_Msk /*!< Channel 7 Transfer Complete flag */
+#define DMA_ISR_HTIF7_Pos (26U)
+#define DMA_ISR_HTIF7_Msk (0x1U << DMA_ISR_HTIF7_Pos) /*!< 0x04000000 */
+#define DMA_ISR_HTIF7 DMA_ISR_HTIF7_Msk /*!< Channel 7 Half Transfer flag */
+#define DMA_ISR_TEIF7_Pos (27U)
+#define DMA_ISR_TEIF7_Msk (0x1U << DMA_ISR_TEIF7_Pos) /*!< 0x08000000 */
+#define DMA_ISR_TEIF7 DMA_ISR_TEIF7_Msk /*!< Channel 7 Transfer Error flag */
+
+/******************* Bit definition for DMA_IFCR register *******************/
+#define DMA_IFCR_CGIF1_Pos (0U)
+#define DMA_IFCR_CGIF1_Msk (0x1U << DMA_IFCR_CGIF1_Pos) /*!< 0x00000001 */
+#define DMA_IFCR_CGIF1 DMA_IFCR_CGIF1_Msk /*!< Channel 1 Global interrupt clear */
+#define DMA_IFCR_CTCIF1_Pos (1U)
+#define DMA_IFCR_CTCIF1_Msk (0x1U << DMA_IFCR_CTCIF1_Pos) /*!< 0x00000002 */
+#define DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF1_Msk /*!< Channel 1 Transfer Complete clear */
+#define DMA_IFCR_CHTIF1_Pos (2U)
+#define DMA_IFCR_CHTIF1_Msk (0x1U << DMA_IFCR_CHTIF1_Pos) /*!< 0x00000004 */
+#define DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF1_Msk /*!< Channel 1 Half Transfer clear */
+#define DMA_IFCR_CTEIF1_Pos (3U)
+#define DMA_IFCR_CTEIF1_Msk (0x1U << DMA_IFCR_CTEIF1_Pos) /*!< 0x00000008 */
+#define DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF1_Msk /*!< Channel 1 Transfer Error clear */
+#define DMA_IFCR_CGIF2_Pos (4U)
+#define DMA_IFCR_CGIF2_Msk (0x1U << DMA_IFCR_CGIF2_Pos) /*!< 0x00000010 */
+#define DMA_IFCR_CGIF2 DMA_IFCR_CGIF2_Msk /*!< Channel 2 Global interrupt clear */
+#define DMA_IFCR_CTCIF2_Pos (5U)
+#define DMA_IFCR_CTCIF2_Msk (0x1U << DMA_IFCR_CTCIF2_Pos) /*!< 0x00000020 */
+#define DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF2_Msk /*!< Channel 2 Transfer Complete clear */
+#define DMA_IFCR_CHTIF2_Pos (6U)
+#define DMA_IFCR_CHTIF2_Msk (0x1U << DMA_IFCR_CHTIF2_Pos) /*!< 0x00000040 */
+#define DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF2_Msk /*!< Channel 2 Half Transfer clear */
+#define DMA_IFCR_CTEIF2_Pos (7U)
+#define DMA_IFCR_CTEIF2_Msk (0x1U << DMA_IFCR_CTEIF2_Pos) /*!< 0x00000080 */
+#define DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF2_Msk /*!< Channel 2 Transfer Error clear */
+#define DMA_IFCR_CGIF3_Pos (8U)
+#define DMA_IFCR_CGIF3_Msk (0x1U << DMA_IFCR_CGIF3_Pos) /*!< 0x00000100 */
+#define DMA_IFCR_CGIF3 DMA_IFCR_CGIF3_Msk /*!< Channel 3 Global interrupt clear */
+#define DMA_IFCR_CTCIF3_Pos (9U)
+#define DMA_IFCR_CTCIF3_Msk (0x1U << DMA_IFCR_CTCIF3_Pos) /*!< 0x00000200 */
+#define DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF3_Msk /*!< Channel 3 Transfer Complete clear */
+#define DMA_IFCR_CHTIF3_Pos (10U)
+#define DMA_IFCR_CHTIF3_Msk (0x1U << DMA_IFCR_CHTIF3_Pos) /*!< 0x00000400 */
+#define DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF3_Msk /*!< Channel 3 Half Transfer clear */
+#define DMA_IFCR_CTEIF3_Pos (11U)
+#define DMA_IFCR_CTEIF3_Msk (0x1U << DMA_IFCR_CTEIF3_Pos) /*!< 0x00000800 */
+#define DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF3_Msk /*!< Channel 3 Transfer Error clear */
+#define DMA_IFCR_CGIF4_Pos (12U)
+#define DMA_IFCR_CGIF4_Msk (0x1U << DMA_IFCR_CGIF4_Pos) /*!< 0x00001000 */
+#define DMA_IFCR_CGIF4 DMA_IFCR_CGIF4_Msk /*!< Channel 4 Global interrupt clear */
+#define DMA_IFCR_CTCIF4_Pos (13U)
+#define DMA_IFCR_CTCIF4_Msk (0x1U << DMA_IFCR_CTCIF4_Pos) /*!< 0x00002000 */
+#define DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF4_Msk /*!< Channel 4 Transfer Complete clear */
+#define DMA_IFCR_CHTIF4_Pos (14U)
+#define DMA_IFCR_CHTIF4_Msk (0x1U << DMA_IFCR_CHTIF4_Pos) /*!< 0x00004000 */
+#define DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF4_Msk /*!< Channel 4 Half Transfer clear */
+#define DMA_IFCR_CTEIF4_Pos (15U)
+#define DMA_IFCR_CTEIF4_Msk (0x1U << DMA_IFCR_CTEIF4_Pos) /*!< 0x00008000 */
+#define DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF4_Msk /*!< Channel 4 Transfer Error clear */
+#define DMA_IFCR_CGIF5_Pos (16U)
+#define DMA_IFCR_CGIF5_Msk (0x1U << DMA_IFCR_CGIF5_Pos) /*!< 0x00010000 */
+#define DMA_IFCR_CGIF5 DMA_IFCR_CGIF5_Msk /*!< Channel 5 Global interrupt clear */
+#define DMA_IFCR_CTCIF5_Pos (17U)
+#define DMA_IFCR_CTCIF5_Msk (0x1U << DMA_IFCR_CTCIF5_Pos) /*!< 0x00020000 */
+#define DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF5_Msk /*!< Channel 5 Transfer Complete clear */
+#define DMA_IFCR_CHTIF5_Pos (18U)
+#define DMA_IFCR_CHTIF5_Msk (0x1U << DMA_IFCR_CHTIF5_Pos) /*!< 0x00040000 */
+#define DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5_Msk /*!< Channel 5 Half Transfer clear */
+#define DMA_IFCR_CTEIF5_Pos (19U)
+#define DMA_IFCR_CTEIF5_Msk (0x1U << DMA_IFCR_CTEIF5_Pos) /*!< 0x00080000 */
+#define DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF5_Msk /*!< Channel 5 Transfer Error clear */
+#define DMA_IFCR_CGIF6_Pos (20U)
+#define DMA_IFCR_CGIF6_Msk (0x1U << DMA_IFCR_CGIF6_Pos) /*!< 0x00100000 */
+#define DMA_IFCR_CGIF6 DMA_IFCR_CGIF6_Msk /*!< Channel 6 Global interrupt clear */
+#define DMA_IFCR_CTCIF6_Pos (21U)
+#define DMA_IFCR_CTCIF6_Msk (0x1U << DMA_IFCR_CTCIF6_Pos) /*!< 0x00200000 */
+#define DMA_IFCR_CTCIF6 DMA_IFCR_CTCIF6_Msk /*!< Channel 6 Transfer Complete clear */
+#define DMA_IFCR_CHTIF6_Pos (22U)
+#define DMA_IFCR_CHTIF6_Msk (0x1U << DMA_IFCR_CHTIF6_Pos) /*!< 0x00400000 */
+#define DMA_IFCR_CHTIF6 DMA_IFCR_CHTIF6_Msk /*!< Channel 6 Half Transfer clear */
+#define DMA_IFCR_CTEIF6_Pos (23U)
+#define DMA_IFCR_CTEIF6_Msk (0x1U << DMA_IFCR_CTEIF6_Pos) /*!< 0x00800000 */
+#define DMA_IFCR_CTEIF6 DMA_IFCR_CTEIF6_Msk /*!< Channel 6 Transfer Error clear */
+#define DMA_IFCR_CGIF7_Pos (24U)
+#define DMA_IFCR_CGIF7_Msk (0x1U << DMA_IFCR_CGIF7_Pos) /*!< 0x01000000 */
+#define DMA_IFCR_CGIF7 DMA_IFCR_CGIF7_Msk /*!< Channel 7 Global interrupt clear */
+#define DMA_IFCR_CTCIF7_Pos (25U)
+#define DMA_IFCR_CTCIF7_Msk (0x1U << DMA_IFCR_CTCIF7_Pos) /*!< 0x02000000 */
+#define DMA_IFCR_CTCIF7 DMA_IFCR_CTCIF7_Msk /*!< Channel 7 Transfer Complete clear */
+#define DMA_IFCR_CHTIF7_Pos (26U)
+#define DMA_IFCR_CHTIF7_Msk (0x1U << DMA_IFCR_CHTIF7_Pos) /*!< 0x04000000 */
+#define DMA_IFCR_CHTIF7 DMA_IFCR_CHTIF7_Msk /*!< Channel 7 Half Transfer clear */
+#define DMA_IFCR_CTEIF7_Pos (27U)
+#define DMA_IFCR_CTEIF7_Msk (0x1U << DMA_IFCR_CTEIF7_Pos) /*!< 0x08000000 */
+#define DMA_IFCR_CTEIF7 DMA_IFCR_CTEIF7_Msk /*!< Channel 7 Transfer Error clear */
+
+/******************* Bit definition for DMA_CCR register *******************/
+#define DMA_CCR_EN_Pos (0U)
+#define DMA_CCR_EN_Msk (0x1U << DMA_CCR_EN_Pos) /*!< 0x00000001 */
+#define DMA_CCR_EN DMA_CCR_EN_Msk /*!< Channel enable */
+#define DMA_CCR_TCIE_Pos (1U)
+#define DMA_CCR_TCIE_Msk (0x1U << DMA_CCR_TCIE_Pos) /*!< 0x00000002 */
+#define DMA_CCR_TCIE DMA_CCR_TCIE_Msk /*!< Transfer complete interrupt enable */
+#define DMA_CCR_HTIE_Pos (2U)
+#define DMA_CCR_HTIE_Msk (0x1U << DMA_CCR_HTIE_Pos) /*!< 0x00000004 */
+#define DMA_CCR_HTIE DMA_CCR_HTIE_Msk /*!< Half Transfer interrupt enable */
+#define DMA_CCR_TEIE_Pos (3U)
+#define DMA_CCR_TEIE_Msk (0x1U << DMA_CCR_TEIE_Pos) /*!< 0x00000008 */
+#define DMA_CCR_TEIE DMA_CCR_TEIE_Msk /*!< Transfer error interrupt enable */
+#define DMA_CCR_DIR_Pos (4U)
+#define DMA_CCR_DIR_Msk (0x1U << DMA_CCR_DIR_Pos) /*!< 0x00000010 */
+#define DMA_CCR_DIR DMA_CCR_DIR_Msk /*!< Data transfer direction */
+#define DMA_CCR_CIRC_Pos (5U)
+#define DMA_CCR_CIRC_Msk (0x1U << DMA_CCR_CIRC_Pos) /*!< 0x00000020 */
+#define DMA_CCR_CIRC DMA_CCR_CIRC_Msk /*!< Circular mode */
+#define DMA_CCR_PINC_Pos (6U)
+#define DMA_CCR_PINC_Msk (0x1U << DMA_CCR_PINC_Pos) /*!< 0x00000040 */
+#define DMA_CCR_PINC DMA_CCR_PINC_Msk /*!< Peripheral increment mode */
+#define DMA_CCR_MINC_Pos (7U)
+#define DMA_CCR_MINC_Msk (0x1U << DMA_CCR_MINC_Pos) /*!< 0x00000080 */
+#define DMA_CCR_MINC DMA_CCR_MINC_Msk /*!< Memory increment mode */
+
+#define DMA_CCR_PSIZE_Pos (8U)
+#define DMA_CCR_PSIZE_Msk (0x3U << DMA_CCR_PSIZE_Pos) /*!< 0x00000300 */
+#define DMA_CCR_PSIZE DMA_CCR_PSIZE_Msk /*!< PSIZE[1:0] bits (Peripheral size) */
+#define DMA_CCR_PSIZE_0 (0x1U << DMA_CCR_PSIZE_Pos) /*!< 0x00000100 */
+#define DMA_CCR_PSIZE_1 (0x2U << DMA_CCR_PSIZE_Pos) /*!< 0x00000200 */
+
+#define DMA_CCR_MSIZE_Pos (10U)
+#define DMA_CCR_MSIZE_Msk (0x3U << DMA_CCR_MSIZE_Pos) /*!< 0x00000C00 */
+#define DMA_CCR_MSIZE DMA_CCR_MSIZE_Msk /*!< MSIZE[1:0] bits (Memory size) */
+#define DMA_CCR_MSIZE_0 (0x1U << DMA_CCR_MSIZE_Pos) /*!< 0x00000400 */
+#define DMA_CCR_MSIZE_1 (0x2U << DMA_CCR_MSIZE_Pos) /*!< 0x00000800 */
+
+#define DMA_CCR_PL_Pos (12U)
+#define DMA_CCR_PL_Msk (0x3U << DMA_CCR_PL_Pos) /*!< 0x00003000 */
+#define DMA_CCR_PL DMA_CCR_PL_Msk /*!< PL[1:0] bits(Channel Priority level) */
+#define DMA_CCR_PL_0 (0x1U << DMA_CCR_PL_Pos) /*!< 0x00001000 */
+#define DMA_CCR_PL_1 (0x2U << DMA_CCR_PL_Pos) /*!< 0x00002000 */
+
+#define DMA_CCR_MEM2MEM_Pos (14U)
+#define DMA_CCR_MEM2MEM_Msk (0x1U << DMA_CCR_MEM2MEM_Pos) /*!< 0x00004000 */
+#define DMA_CCR_MEM2MEM DMA_CCR_MEM2MEM_Msk /*!< Memory to memory mode */
+
+/****************** Bit definition for DMA_CNDTR register ******************/
+#define DMA_CNDTR_NDT_Pos (0U)
+#define DMA_CNDTR_NDT_Msk (0xFFFFU << DMA_CNDTR_NDT_Pos) /*!< 0x0000FFFF */
+#define DMA_CNDTR_NDT DMA_CNDTR_NDT_Msk /*!< Number of data to Transfer */
+
+/****************** Bit definition for DMA_CPAR register *******************/
+#define DMA_CPAR_PA_Pos (0U)
+#define DMA_CPAR_PA_Msk (0xFFFFFFFFU << DMA_CPAR_PA_Pos) /*!< 0xFFFFFFFF */
+#define DMA_CPAR_PA DMA_CPAR_PA_Msk /*!< Peripheral Address */
+
+/****************** Bit definition for DMA_CMAR register *******************/
+#define DMA_CMAR_MA_Pos (0U)
+#define DMA_CMAR_MA_Msk (0xFFFFFFFFU << DMA_CMAR_MA_Pos) /*!< 0xFFFFFFFF */
+#define DMA_CMAR_MA DMA_CMAR_MA_Msk /*!< Memory Address */
+
+/******************************************************************************/
+/* */
+/* Analog to Digital Converter (ADC) */
+/* */
+/******************************************************************************/
+
+/*
+ * @brief Specific device feature definitions (not present on all devices in the STM32F1 family)
+ */
+/* Note: No specific macro feature on this device */
+
+/******************** Bit definition for ADC_SR register ********************/
+#define ADC_SR_AWD_Pos (0U)
+#define ADC_SR_AWD_Msk (0x1U << ADC_SR_AWD_Pos) /*!< 0x00000001 */
+#define ADC_SR_AWD ADC_SR_AWD_Msk /*!< ADC analog watchdog 1 flag */
+#define ADC_SR_EOS_Pos (1U)
+#define ADC_SR_EOS_Msk (0x1U << ADC_SR_EOS_Pos) /*!< 0x00000002 */
+#define ADC_SR_EOS ADC_SR_EOS_Msk /*!< ADC group regular end of sequence conversions flag */
+#define ADC_SR_JEOS_Pos (2U)
+#define ADC_SR_JEOS_Msk (0x1U << ADC_SR_JEOS_Pos) /*!< 0x00000004 */
+#define ADC_SR_JEOS ADC_SR_JEOS_Msk /*!< ADC group injected end of sequence conversions flag */
+#define ADC_SR_JSTRT_Pos (3U)
+#define ADC_SR_JSTRT_Msk (0x1U << ADC_SR_JSTRT_Pos) /*!< 0x00000008 */
+#define ADC_SR_JSTRT ADC_SR_JSTRT_Msk /*!< ADC group injected conversion start flag */
+#define ADC_SR_STRT_Pos (4U)
+#define ADC_SR_STRT_Msk (0x1U << ADC_SR_STRT_Pos) /*!< 0x00000010 */
+#define ADC_SR_STRT ADC_SR_STRT_Msk /*!< ADC group regular conversion start flag */
+
+/* Legacy defines */
+#define ADC_SR_EOC (ADC_SR_EOS)
+#define ADC_SR_JEOC (ADC_SR_JEOS)
+
+/******************* Bit definition for ADC_CR1 register ********************/
+#define ADC_CR1_AWDCH_Pos (0U)
+#define ADC_CR1_AWDCH_Msk (0x1FU << ADC_CR1_AWDCH_Pos) /*!< 0x0000001F */
+#define ADC_CR1_AWDCH ADC_CR1_AWDCH_Msk /*!< ADC analog watchdog 1 monitored channel selection */
+#define ADC_CR1_AWDCH_0 (0x01U << ADC_CR1_AWDCH_Pos) /*!< 0x00000001 */
+#define ADC_CR1_AWDCH_1 (0x02U << ADC_CR1_AWDCH_Pos) /*!< 0x00000002 */
+#define ADC_CR1_AWDCH_2 (0x04U << ADC_CR1_AWDCH_Pos) /*!< 0x00000004 */
+#define ADC_CR1_AWDCH_3 (0x08U << ADC_CR1_AWDCH_Pos) /*!< 0x00000008 */
+#define ADC_CR1_AWDCH_4 (0x10U << ADC_CR1_AWDCH_Pos) /*!< 0x00000010 */
+
+#define ADC_CR1_EOSIE_Pos (5U)
+#define ADC_CR1_EOSIE_Msk (0x1U << ADC_CR1_EOSIE_Pos) /*!< 0x00000020 */
+#define ADC_CR1_EOSIE ADC_CR1_EOSIE_Msk /*!< ADC group regular end of sequence conversions interrupt */
+#define ADC_CR1_AWDIE_Pos (6U)
+#define ADC_CR1_AWDIE_Msk (0x1U << ADC_CR1_AWDIE_Pos) /*!< 0x00000040 */
+#define ADC_CR1_AWDIE ADC_CR1_AWDIE_Msk /*!< ADC analog watchdog 1 interrupt */
+#define ADC_CR1_JEOSIE_Pos (7U)
+#define ADC_CR1_JEOSIE_Msk (0x1U << ADC_CR1_JEOSIE_Pos) /*!< 0x00000080 */
+#define ADC_CR1_JEOSIE ADC_CR1_JEOSIE_Msk /*!< ADC group injected end of sequence conversions interrupt */
+#define ADC_CR1_SCAN_Pos (8U)
+#define ADC_CR1_SCAN_Msk (0x1U << ADC_CR1_SCAN_Pos) /*!< 0x00000100 */
+#define ADC_CR1_SCAN ADC_CR1_SCAN_Msk /*!< ADC scan mode */
+#define ADC_CR1_AWDSGL_Pos (9U)
+#define ADC_CR1_AWDSGL_Msk (0x1U << ADC_CR1_AWDSGL_Pos) /*!< 0x00000200 */
+#define ADC_CR1_AWDSGL ADC_CR1_AWDSGL_Msk /*!< ADC analog watchdog 1 monitoring a single channel or all channels */
+#define ADC_CR1_JAUTO_Pos (10U)
+#define ADC_CR1_JAUTO_Msk (0x1U << ADC_CR1_JAUTO_Pos) /*!< 0x00000400 */
+#define ADC_CR1_JAUTO ADC_CR1_JAUTO_Msk /*!< ADC group injected automatic trigger mode */
+#define ADC_CR1_DISCEN_Pos (11U)
+#define ADC_CR1_DISCEN_Msk (0x1U << ADC_CR1_DISCEN_Pos) /*!< 0x00000800 */
+#define ADC_CR1_DISCEN ADC_CR1_DISCEN_Msk /*!< ADC group regular sequencer discontinuous mode */
+#define ADC_CR1_JDISCEN_Pos (12U)
+#define ADC_CR1_JDISCEN_Msk (0x1U << ADC_CR1_JDISCEN_Pos) /*!< 0x00001000 */
+#define ADC_CR1_JDISCEN ADC_CR1_JDISCEN_Msk /*!< ADC group injected sequencer discontinuous mode */
+
+#define ADC_CR1_DISCNUM_Pos (13U)
+#define ADC_CR1_DISCNUM_Msk (0x7U << ADC_CR1_DISCNUM_Pos) /*!< 0x0000E000 */
+#define ADC_CR1_DISCNUM ADC_CR1_DISCNUM_Msk /*!< ADC group regular sequencer discontinuous number of ranks */
+#define ADC_CR1_DISCNUM_0 (0x1U << ADC_CR1_DISCNUM_Pos) /*!< 0x00002000 */
+#define ADC_CR1_DISCNUM_1 (0x2U << ADC_CR1_DISCNUM_Pos) /*!< 0x00004000 */
+#define ADC_CR1_DISCNUM_2 (0x4U << ADC_CR1_DISCNUM_Pos) /*!< 0x00008000 */
+
+#define ADC_CR1_JAWDEN_Pos (22U)
+#define ADC_CR1_JAWDEN_Msk (0x1U << ADC_CR1_JAWDEN_Pos) /*!< 0x00400000 */
+#define ADC_CR1_JAWDEN ADC_CR1_JAWDEN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group injected */
+#define ADC_CR1_AWDEN_Pos (23U)
+#define ADC_CR1_AWDEN_Msk (0x1U << ADC_CR1_AWDEN_Pos) /*!< 0x00800000 */
+#define ADC_CR1_AWDEN ADC_CR1_AWDEN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group regular */
+
+/* Legacy defines */
+#define ADC_CR1_EOCIE (ADC_CR1_EOSIE)
+#define ADC_CR1_JEOCIE (ADC_CR1_JEOSIE)
+
+/******************* Bit definition for ADC_CR2 register ********************/
+#define ADC_CR2_ADON_Pos (0U)
+#define ADC_CR2_ADON_Msk (0x1U << ADC_CR2_ADON_Pos) /*!< 0x00000001 */
+#define ADC_CR2_ADON ADC_CR2_ADON_Msk /*!< ADC enable */
+#define ADC_CR2_CONT_Pos (1U)
+#define ADC_CR2_CONT_Msk (0x1U << ADC_CR2_CONT_Pos) /*!< 0x00000002 */
+#define ADC_CR2_CONT ADC_CR2_CONT_Msk /*!< ADC group regular continuous conversion mode */
+#define ADC_CR2_CAL_Pos (2U)
+#define ADC_CR2_CAL_Msk (0x1U << ADC_CR2_CAL_Pos) /*!< 0x00000004 */
+#define ADC_CR2_CAL ADC_CR2_CAL_Msk /*!< ADC calibration start */
+#define ADC_CR2_RSTCAL_Pos (3U)
+#define ADC_CR2_RSTCAL_Msk (0x1U << ADC_CR2_RSTCAL_Pos) /*!< 0x00000008 */
+#define ADC_CR2_RSTCAL ADC_CR2_RSTCAL_Msk /*!< ADC calibration reset */
+#define ADC_CR2_DMA_Pos (8U)
+#define ADC_CR2_DMA_Msk (0x1U << ADC_CR2_DMA_Pos) /*!< 0x00000100 */
+#define ADC_CR2_DMA ADC_CR2_DMA_Msk /*!< ADC DMA transfer enable */
+#define ADC_CR2_ALIGN_Pos (11U)
+#define ADC_CR2_ALIGN_Msk (0x1U << ADC_CR2_ALIGN_Pos) /*!< 0x00000800 */
+#define ADC_CR2_ALIGN ADC_CR2_ALIGN_Msk /*!< ADC data alignement */
+
+#define ADC_CR2_JEXTSEL_Pos (12U)
+#define ADC_CR2_JEXTSEL_Msk (0x7U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00007000 */
+#define ADC_CR2_JEXTSEL ADC_CR2_JEXTSEL_Msk /*!< ADC group injected external trigger source */
+#define ADC_CR2_JEXTSEL_0 (0x1U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00001000 */
+#define ADC_CR2_JEXTSEL_1 (0x2U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00002000 */
+#define ADC_CR2_JEXTSEL_2 (0x4U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00004000 */
+
+#define ADC_CR2_JEXTTRIG_Pos (15U)
+#define ADC_CR2_JEXTTRIG_Msk (0x1U << ADC_CR2_JEXTTRIG_Pos) /*!< 0x00008000 */
+#define ADC_CR2_JEXTTRIG ADC_CR2_JEXTTRIG_Msk /*!< ADC group injected external trigger enable */
+
+#define ADC_CR2_EXTSEL_Pos (17U)
+#define ADC_CR2_EXTSEL_Msk (0x7U << ADC_CR2_EXTSEL_Pos) /*!< 0x000E0000 */
+#define ADC_CR2_EXTSEL ADC_CR2_EXTSEL_Msk /*!< ADC group regular external trigger source */
+#define ADC_CR2_EXTSEL_0 (0x1U << ADC_CR2_EXTSEL_Pos) /*!< 0x00020000 */
+#define ADC_CR2_EXTSEL_1 (0x2U << ADC_CR2_EXTSEL_Pos) /*!< 0x00040000 */
+#define ADC_CR2_EXTSEL_2 (0x4U << ADC_CR2_EXTSEL_Pos) /*!< 0x00080000 */
+
+#define ADC_CR2_EXTTRIG_Pos (20U)
+#define ADC_CR2_EXTTRIG_Msk (0x1U << ADC_CR2_EXTTRIG_Pos) /*!< 0x00100000 */
+#define ADC_CR2_EXTTRIG ADC_CR2_EXTTRIG_Msk /*!< ADC group regular external trigger enable */
+#define ADC_CR2_JSWSTART_Pos (21U)
+#define ADC_CR2_JSWSTART_Msk (0x1U << ADC_CR2_JSWSTART_Pos) /*!< 0x00200000 */
+#define ADC_CR2_JSWSTART ADC_CR2_JSWSTART_Msk /*!< ADC group injected conversion start */
+#define ADC_CR2_SWSTART_Pos (22U)
+#define ADC_CR2_SWSTART_Msk (0x1U << ADC_CR2_SWSTART_Pos) /*!< 0x00400000 */
+#define ADC_CR2_SWSTART ADC_CR2_SWSTART_Msk /*!< ADC group regular conversion start */
+#define ADC_CR2_TSVREFE_Pos (23U)
+#define ADC_CR2_TSVREFE_Msk (0x1U << ADC_CR2_TSVREFE_Pos) /*!< 0x00800000 */
+#define ADC_CR2_TSVREFE ADC_CR2_TSVREFE_Msk /*!< ADC internal path to VrefInt and temperature sensor enable */
+
+/****************** Bit definition for ADC_SMPR1 register *******************/
+#define ADC_SMPR1_SMP10_Pos (0U)
+#define ADC_SMPR1_SMP10_Msk (0x7U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000007 */
+#define ADC_SMPR1_SMP10 ADC_SMPR1_SMP10_Msk /*!< ADC channel 10 sampling time selection */
+#define ADC_SMPR1_SMP10_0 (0x1U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000001 */
+#define ADC_SMPR1_SMP10_1 (0x2U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000002 */
+#define ADC_SMPR1_SMP10_2 (0x4U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000004 */
+
+#define ADC_SMPR1_SMP11_Pos (3U)
+#define ADC_SMPR1_SMP11_Msk (0x7U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000038 */
+#define ADC_SMPR1_SMP11 ADC_SMPR1_SMP11_Msk /*!< ADC channel 11 sampling time selection */
+#define ADC_SMPR1_SMP11_0 (0x1U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000008 */
+#define ADC_SMPR1_SMP11_1 (0x2U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000010 */
+#define ADC_SMPR1_SMP11_2 (0x4U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000020 */
+
+#define ADC_SMPR1_SMP12_Pos (6U)
+#define ADC_SMPR1_SMP12_Msk (0x7U << ADC_SMPR1_SMP12_Pos) /*!< 0x000001C0 */
+#define ADC_SMPR1_SMP12 ADC_SMPR1_SMP12_Msk /*!< ADC channel 12 sampling time selection */
+#define ADC_SMPR1_SMP12_0 (0x1U << ADC_SMPR1_SMP12_Pos) /*!< 0x00000040 */
+#define ADC_SMPR1_SMP12_1 (0x2U << ADC_SMPR1_SMP12_Pos) /*!< 0x00000080 */
+#define ADC_SMPR1_SMP12_2 (0x4U << ADC_SMPR1_SMP12_Pos) /*!< 0x00000100 */
+
+#define ADC_SMPR1_SMP13_Pos (9U)
+#define ADC_SMPR1_SMP13_Msk (0x7U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000E00 */
+#define ADC_SMPR1_SMP13 ADC_SMPR1_SMP13_Msk /*!< ADC channel 13 sampling time selection */
+#define ADC_SMPR1_SMP13_0 (0x1U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000200 */
+#define ADC_SMPR1_SMP13_1 (0x2U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000400 */
+#define ADC_SMPR1_SMP13_2 (0x4U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000800 */
+
+#define ADC_SMPR1_SMP14_Pos (12U)
+#define ADC_SMPR1_SMP14_Msk (0x7U << ADC_SMPR1_SMP14_Pos) /*!< 0x00007000 */
+#define ADC_SMPR1_SMP14 ADC_SMPR1_SMP14_Msk /*!< ADC channel 14 sampling time selection */
+#define ADC_SMPR1_SMP14_0 (0x1U << ADC_SMPR1_SMP14_Pos) /*!< 0x00001000 */
+#define ADC_SMPR1_SMP14_1 (0x2U << ADC_SMPR1_SMP14_Pos) /*!< 0x00002000 */
+#define ADC_SMPR1_SMP14_2 (0x4U << ADC_SMPR1_SMP14_Pos) /*!< 0x00004000 */
+
+#define ADC_SMPR1_SMP15_Pos (15U)
+#define ADC_SMPR1_SMP15_Msk (0x7U << ADC_SMPR1_SMP15_Pos) /*!< 0x00038000 */
+#define ADC_SMPR1_SMP15 ADC_SMPR1_SMP15_Msk /*!< ADC channel 15 sampling time selection */
+#define ADC_SMPR1_SMP15_0 (0x1U << ADC_SMPR1_SMP15_Pos) /*!< 0x00008000 */
+#define ADC_SMPR1_SMP15_1 (0x2U << ADC_SMPR1_SMP15_Pos) /*!< 0x00010000 */
+#define ADC_SMPR1_SMP15_2 (0x4U << ADC_SMPR1_SMP15_Pos) /*!< 0x00020000 */
+
+#define ADC_SMPR1_SMP16_Pos (18U)
+#define ADC_SMPR1_SMP16_Msk (0x7U << ADC_SMPR1_SMP16_Pos) /*!< 0x001C0000 */
+#define ADC_SMPR1_SMP16 ADC_SMPR1_SMP16_Msk /*!< ADC channel 16 sampling time selection */
+#define ADC_SMPR1_SMP16_0 (0x1U << ADC_SMPR1_SMP16_Pos) /*!< 0x00040000 */
+#define ADC_SMPR1_SMP16_1 (0x2U << ADC_SMPR1_SMP16_Pos) /*!< 0x00080000 */
+#define ADC_SMPR1_SMP16_2 (0x4U << ADC_SMPR1_SMP16_Pos) /*!< 0x00100000 */
+
+#define ADC_SMPR1_SMP17_Pos (21U)
+#define ADC_SMPR1_SMP17_Msk (0x7U << ADC_SMPR1_SMP17_Pos) /*!< 0x00E00000 */
+#define ADC_SMPR1_SMP17 ADC_SMPR1_SMP17_Msk /*!< ADC channel 17 sampling time selection */
+#define ADC_SMPR1_SMP17_0 (0x1U << ADC_SMPR1_SMP17_Pos) /*!< 0x00200000 */
+#define ADC_SMPR1_SMP17_1 (0x2U << ADC_SMPR1_SMP17_Pos) /*!< 0x00400000 */
+#define ADC_SMPR1_SMP17_2 (0x4U << ADC_SMPR1_SMP17_Pos) /*!< 0x00800000 */
+
+/****************** Bit definition for ADC_SMPR2 register *******************/
+#define ADC_SMPR2_SMP0_Pos (0U)
+#define ADC_SMPR2_SMP0_Msk (0x7U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000007 */
+#define ADC_SMPR2_SMP0 ADC_SMPR2_SMP0_Msk /*!< ADC channel 0 sampling time selection */
+#define ADC_SMPR2_SMP0_0 (0x1U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000001 */
+#define ADC_SMPR2_SMP0_1 (0x2U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000002 */
+#define ADC_SMPR2_SMP0_2 (0x4U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000004 */
+
+#define ADC_SMPR2_SMP1_Pos (3U)
+#define ADC_SMPR2_SMP1_Msk (0x7U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000038 */
+#define ADC_SMPR2_SMP1 ADC_SMPR2_SMP1_Msk /*!< ADC channel 1 sampling time selection */
+#define ADC_SMPR2_SMP1_0 (0x1U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000008 */
+#define ADC_SMPR2_SMP1_1 (0x2U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000010 */
+#define ADC_SMPR2_SMP1_2 (0x4U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000020 */
+
+#define ADC_SMPR2_SMP2_Pos (6U)
+#define ADC_SMPR2_SMP2_Msk (0x7U << ADC_SMPR2_SMP2_Pos) /*!< 0x000001C0 */
+#define ADC_SMPR2_SMP2 ADC_SMPR2_SMP2_Msk /*!< ADC channel 2 sampling time selection */
+#define ADC_SMPR2_SMP2_0 (0x1U << ADC_SMPR2_SMP2_Pos) /*!< 0x00000040 */
+#define ADC_SMPR2_SMP2_1 (0x2U << ADC_SMPR2_SMP2_Pos) /*!< 0x00000080 */
+#define ADC_SMPR2_SMP2_2 (0x4U << ADC_SMPR2_SMP2_Pos) /*!< 0x00000100 */
+
+#define ADC_SMPR2_SMP3_Pos (9U)
+#define ADC_SMPR2_SMP3_Msk (0x7U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000E00 */
+#define ADC_SMPR2_SMP3 ADC_SMPR2_SMP3_Msk /*!< ADC channel 3 sampling time selection */
+#define ADC_SMPR2_SMP3_0 (0x1U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000200 */
+#define ADC_SMPR2_SMP3_1 (0x2U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000400 */
+#define ADC_SMPR2_SMP3_2 (0x4U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000800 */
+
+#define ADC_SMPR2_SMP4_Pos (12U)
+#define ADC_SMPR2_SMP4_Msk (0x7U << ADC_SMPR2_SMP4_Pos) /*!< 0x00007000 */
+#define ADC_SMPR2_SMP4 ADC_SMPR2_SMP4_Msk /*!< ADC channel 4 sampling time selection */
+#define ADC_SMPR2_SMP4_0 (0x1U << ADC_SMPR2_SMP4_Pos) /*!< 0x00001000 */
+#define ADC_SMPR2_SMP4_1 (0x2U << ADC_SMPR2_SMP4_Pos) /*!< 0x00002000 */
+#define ADC_SMPR2_SMP4_2 (0x4U << ADC_SMPR2_SMP4_Pos) /*!< 0x00004000 */
+
+#define ADC_SMPR2_SMP5_Pos (15U)
+#define ADC_SMPR2_SMP5_Msk (0x7U << ADC_SMPR2_SMP5_Pos) /*!< 0x00038000 */
+#define ADC_SMPR2_SMP5 ADC_SMPR2_SMP5_Msk /*!< ADC channel 5 sampling time selection */
+#define ADC_SMPR2_SMP5_0 (0x1U << ADC_SMPR2_SMP5_Pos) /*!< 0x00008000 */
+#define ADC_SMPR2_SMP5_1 (0x2U << ADC_SMPR2_SMP5_Pos) /*!< 0x00010000 */
+#define ADC_SMPR2_SMP5_2 (0x4U << ADC_SMPR2_SMP5_Pos) /*!< 0x00020000 */
+
+#define ADC_SMPR2_SMP6_Pos (18U)
+#define ADC_SMPR2_SMP6_Msk (0x7U << ADC_SMPR2_SMP6_Pos) /*!< 0x001C0000 */
+#define ADC_SMPR2_SMP6 ADC_SMPR2_SMP6_Msk /*!< ADC channel 6 sampling time selection */
+#define ADC_SMPR2_SMP6_0 (0x1U << ADC_SMPR2_SMP6_Pos) /*!< 0x00040000 */
+#define ADC_SMPR2_SMP6_1 (0x2U << ADC_SMPR2_SMP6_Pos) /*!< 0x00080000 */
+#define ADC_SMPR2_SMP6_2 (0x4U << ADC_SMPR2_SMP6_Pos) /*!< 0x00100000 */
+
+#define ADC_SMPR2_SMP7_Pos (21U)
+#define ADC_SMPR2_SMP7_Msk (0x7U << ADC_SMPR2_SMP7_Pos) /*!< 0x00E00000 */
+#define ADC_SMPR2_SMP7 ADC_SMPR2_SMP7_Msk /*!< ADC channel 7 sampling time selection */
+#define ADC_SMPR2_SMP7_0 (0x1U << ADC_SMPR2_SMP7_Pos) /*!< 0x00200000 */
+#define ADC_SMPR2_SMP7_1 (0x2U << ADC_SMPR2_SMP7_Pos) /*!< 0x00400000 */
+#define ADC_SMPR2_SMP7_2 (0x4U << ADC_SMPR2_SMP7_Pos) /*!< 0x00800000 */
+
+#define ADC_SMPR2_SMP8_Pos (24U)
+#define ADC_SMPR2_SMP8_Msk (0x7U << ADC_SMPR2_SMP8_Pos) /*!< 0x07000000 */
+#define ADC_SMPR2_SMP8 ADC_SMPR2_SMP8_Msk /*!< ADC channel 8 sampling time selection */
+#define ADC_SMPR2_SMP8_0 (0x1U << ADC_SMPR2_SMP8_Pos) /*!< 0x01000000 */
+#define ADC_SMPR2_SMP8_1 (0x2U << ADC_SMPR2_SMP8_Pos) /*!< 0x02000000 */
+#define ADC_SMPR2_SMP8_2 (0x4U << ADC_SMPR2_SMP8_Pos) /*!< 0x04000000 */
+
+#define ADC_SMPR2_SMP9_Pos (27U)
+#define ADC_SMPR2_SMP9_Msk (0x7U << ADC_SMPR2_SMP9_Pos) /*!< 0x38000000 */
+#define ADC_SMPR2_SMP9 ADC_SMPR2_SMP9_Msk /*!< ADC channel 9 sampling time selection */
+#define ADC_SMPR2_SMP9_0 (0x1U << ADC_SMPR2_SMP9_Pos) /*!< 0x08000000 */
+#define ADC_SMPR2_SMP9_1 (0x2U << ADC_SMPR2_SMP9_Pos) /*!< 0x10000000 */
+#define ADC_SMPR2_SMP9_2 (0x4U << ADC_SMPR2_SMP9_Pos) /*!< 0x20000000 */
+
+/****************** Bit definition for ADC_JOFR1 register *******************/
+#define ADC_JOFR1_JOFFSET1_Pos (0U)
+#define ADC_JOFR1_JOFFSET1_Msk (0xFFFU << ADC_JOFR1_JOFFSET1_Pos) /*!< 0x00000FFF */
+#define ADC_JOFR1_JOFFSET1 ADC_JOFR1_JOFFSET1_Msk /*!< ADC group injected sequencer rank 1 offset value */
+
+/****************** Bit definition for ADC_JOFR2 register *******************/
+#define ADC_JOFR2_JOFFSET2_Pos (0U)
+#define ADC_JOFR2_JOFFSET2_Msk (0xFFFU << ADC_JOFR2_JOFFSET2_Pos) /*!< 0x00000FFF */
+#define ADC_JOFR2_JOFFSET2 ADC_JOFR2_JOFFSET2_Msk /*!< ADC group injected sequencer rank 2 offset value */
+
+/****************** Bit definition for ADC_JOFR3 register *******************/
+#define ADC_JOFR3_JOFFSET3_Pos (0U)
+#define ADC_JOFR3_JOFFSET3_Msk (0xFFFU << ADC_JOFR3_JOFFSET3_Pos) /*!< 0x00000FFF */
+#define ADC_JOFR3_JOFFSET3 ADC_JOFR3_JOFFSET3_Msk /*!< ADC group injected sequencer rank 3 offset value */
+
+/****************** Bit definition for ADC_JOFR4 register *******************/
+#define ADC_JOFR4_JOFFSET4_Pos (0U)
+#define ADC_JOFR4_JOFFSET4_Msk (0xFFFU << ADC_JOFR4_JOFFSET4_Pos) /*!< 0x00000FFF */
+#define ADC_JOFR4_JOFFSET4 ADC_JOFR4_JOFFSET4_Msk /*!< ADC group injected sequencer rank 4 offset value */
+
+/******************* Bit definition for ADC_HTR register ********************/
+#define ADC_HTR_HT_Pos (0U)
+#define ADC_HTR_HT_Msk (0xFFFU << ADC_HTR_HT_Pos) /*!< 0x00000FFF */
+#define ADC_HTR_HT ADC_HTR_HT_Msk /*!< ADC analog watchdog 1 threshold high */
+
+/******************* Bit definition for ADC_LTR register ********************/
+#define ADC_LTR_LT_Pos (0U)
+#define ADC_LTR_LT_Msk (0xFFFU << ADC_LTR_LT_Pos) /*!< 0x00000FFF */
+#define ADC_LTR_LT ADC_LTR_LT_Msk /*!< ADC analog watchdog 1 threshold low */
+
+/******************* Bit definition for ADC_SQR1 register *******************/
+#define ADC_SQR1_SQ13_Pos (0U)
+#define ADC_SQR1_SQ13_Msk (0x1FU << ADC_SQR1_SQ13_Pos) /*!< 0x0000001F */
+#define ADC_SQR1_SQ13 ADC_SQR1_SQ13_Msk /*!< ADC group regular sequencer rank 13 */
+#define ADC_SQR1_SQ13_0 (0x01U << ADC_SQR1_SQ13_Pos) /*!< 0x00000001 */
+#define ADC_SQR1_SQ13_1 (0x02U << ADC_SQR1_SQ13_Pos) /*!< 0x00000002 */
+#define ADC_SQR1_SQ13_2 (0x04U << ADC_SQR1_SQ13_Pos) /*!< 0x00000004 */
+#define ADC_SQR1_SQ13_3 (0x08U << ADC_SQR1_SQ13_Pos) /*!< 0x00000008 */
+#define ADC_SQR1_SQ13_4 (0x10U << ADC_SQR1_SQ13_Pos) /*!< 0x00000010 */
+
+#define ADC_SQR1_SQ14_Pos (5U)
+#define ADC_SQR1_SQ14_Msk (0x1FU << ADC_SQR1_SQ14_Pos) /*!< 0x000003E0 */
+#define ADC_SQR1_SQ14 ADC_SQR1_SQ14_Msk /*!< ADC group regular sequencer rank 14 */
+#define ADC_SQR1_SQ14_0 (0x01U << ADC_SQR1_SQ14_Pos) /*!< 0x00000020 */
+#define ADC_SQR1_SQ14_1 (0x02U << ADC_SQR1_SQ14_Pos) /*!< 0x00000040 */
+#define ADC_SQR1_SQ14_2 (0x04U << ADC_SQR1_SQ14_Pos) /*!< 0x00000080 */
+#define ADC_SQR1_SQ14_3 (0x08U << ADC_SQR1_SQ14_Pos) /*!< 0x00000100 */
+#define ADC_SQR1_SQ14_4 (0x10U << ADC_SQR1_SQ14_Pos) /*!< 0x00000200 */
+
+#define ADC_SQR1_SQ15_Pos (10U)
+#define ADC_SQR1_SQ15_Msk (0x1FU << ADC_SQR1_SQ15_Pos) /*!< 0x00007C00 */
+#define ADC_SQR1_SQ15 ADC_SQR1_SQ15_Msk /*!< ADC group regular sequencer rank 15 */
+#define ADC_SQR1_SQ15_0 (0x01U << ADC_SQR1_SQ15_Pos) /*!< 0x00000400 */
+#define ADC_SQR1_SQ15_1 (0x02U << ADC_SQR1_SQ15_Pos) /*!< 0x00000800 */
+#define ADC_SQR1_SQ15_2 (0x04U << ADC_SQR1_SQ15_Pos) /*!< 0x00001000 */
+#define ADC_SQR1_SQ15_3 (0x08U << ADC_SQR1_SQ15_Pos) /*!< 0x00002000 */
+#define ADC_SQR1_SQ15_4 (0x10U << ADC_SQR1_SQ15_Pos) /*!< 0x00004000 */
+
+#define ADC_SQR1_SQ16_Pos (15U)
+#define ADC_SQR1_SQ16_Msk (0x1FU << ADC_SQR1_SQ16_Pos) /*!< 0x000F8000 */
+#define ADC_SQR1_SQ16 ADC_SQR1_SQ16_Msk /*!< ADC group regular sequencer rank 16 */
+#define ADC_SQR1_SQ16_0 (0x01U << ADC_SQR1_SQ16_Pos) /*!< 0x00008000 */
+#define ADC_SQR1_SQ16_1 (0x02U << ADC_SQR1_SQ16_Pos) /*!< 0x00010000 */
+#define ADC_SQR1_SQ16_2 (0x04U << ADC_SQR1_SQ16_Pos) /*!< 0x00020000 */
+#define ADC_SQR1_SQ16_3 (0x08U << ADC_SQR1_SQ16_Pos) /*!< 0x00040000 */
+#define ADC_SQR1_SQ16_4 (0x10U << ADC_SQR1_SQ16_Pos) /*!< 0x00080000 */
+
+#define ADC_SQR1_L_Pos (20U)
+#define ADC_SQR1_L_Msk (0xFU << ADC_SQR1_L_Pos) /*!< 0x00F00000 */
+#define ADC_SQR1_L ADC_SQR1_L_Msk /*!< ADC group regular sequencer scan length */
+#define ADC_SQR1_L_0 (0x1U << ADC_SQR1_L_Pos) /*!< 0x00100000 */
+#define ADC_SQR1_L_1 (0x2U << ADC_SQR1_L_Pos) /*!< 0x00200000 */
+#define ADC_SQR1_L_2 (0x4U << ADC_SQR1_L_Pos) /*!< 0x00400000 */
+#define ADC_SQR1_L_3 (0x8U << ADC_SQR1_L_Pos) /*!< 0x00800000 */
+
+/******************* Bit definition for ADC_SQR2 register *******************/
+#define ADC_SQR2_SQ7_Pos (0U)
+#define ADC_SQR2_SQ7_Msk (0x1FU << ADC_SQR2_SQ7_Pos) /*!< 0x0000001F */
+#define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk /*!< ADC group regular sequencer rank 7 */
+#define ADC_SQR2_SQ7_0 (0x01U << ADC_SQR2_SQ7_Pos) /*!< 0x00000001 */
+#define ADC_SQR2_SQ7_1 (0x02U << ADC_SQR2_SQ7_Pos) /*!< 0x00000002 */
+#define ADC_SQR2_SQ7_2 (0x04U << ADC_SQR2_SQ7_Pos) /*!< 0x00000004 */
+#define ADC_SQR2_SQ7_3 (0x08U << ADC_SQR2_SQ7_Pos) /*!< 0x00000008 */
+#define ADC_SQR2_SQ7_4 (0x10U << ADC_SQR2_SQ7_Pos) /*!< 0x00000010 */
+
+#define ADC_SQR2_SQ8_Pos (5U)
+#define ADC_SQR2_SQ8_Msk (0x1FU << ADC_SQR2_SQ8_Pos) /*!< 0x000003E0 */
+#define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk /*!< ADC group regular sequencer rank 8 */
+#define ADC_SQR2_SQ8_0 (0x01U << ADC_SQR2_SQ8_Pos) /*!< 0x00000020 */
+#define ADC_SQR2_SQ8_1 (0x02U << ADC_SQR2_SQ8_Pos) /*!< 0x00000040 */
+#define ADC_SQR2_SQ8_2 (0x04U << ADC_SQR2_SQ8_Pos) /*!< 0x00000080 */
+#define ADC_SQR2_SQ8_3 (0x08U << ADC_SQR2_SQ8_Pos) /*!< 0x00000100 */
+#define ADC_SQR2_SQ8_4 (0x10U << ADC_SQR2_SQ8_Pos) /*!< 0x00000200 */
+
+#define ADC_SQR2_SQ9_Pos (10U)
+#define ADC_SQR2_SQ9_Msk (0x1FU << ADC_SQR2_SQ9_Pos) /*!< 0x00007C00 */
+#define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk /*!< ADC group regular sequencer rank 9 */
+#define ADC_SQR2_SQ9_0 (0x01U << ADC_SQR2_SQ9_Pos) /*!< 0x00000400 */
+#define ADC_SQR2_SQ9_1 (0x02U << ADC_SQR2_SQ9_Pos) /*!< 0x00000800 */
+#define ADC_SQR2_SQ9_2 (0x04U << ADC_SQR2_SQ9_Pos) /*!< 0x00001000 */
+#define ADC_SQR2_SQ9_3 (0x08U << ADC_SQR2_SQ9_Pos) /*!< 0x00002000 */
+#define ADC_SQR2_SQ9_4 (0x10U << ADC_SQR2_SQ9_Pos) /*!< 0x00004000 */
+
+#define ADC_SQR2_SQ10_Pos (15U)
+#define ADC_SQR2_SQ10_Msk (0x1FU << ADC_SQR2_SQ10_Pos) /*!< 0x000F8000 */
+#define ADC_SQR2_SQ10 ADC_SQR2_SQ10_Msk /*!< ADC group regular sequencer rank 10 */
+#define ADC_SQR2_SQ10_0 (0x01U << ADC_SQR2_SQ10_Pos) /*!< 0x00008000 */
+#define ADC_SQR2_SQ10_1 (0x02U << ADC_SQR2_SQ10_Pos) /*!< 0x00010000 */
+#define ADC_SQR2_SQ10_2 (0x04U << ADC_SQR2_SQ10_Pos) /*!< 0x00020000 */
+#define ADC_SQR2_SQ10_3 (0x08U << ADC_SQR2_SQ10_Pos) /*!< 0x00040000 */
+#define ADC_SQR2_SQ10_4 (0x10U << ADC_SQR2_SQ10_Pos) /*!< 0x00080000 */
+
+#define ADC_SQR2_SQ11_Pos (20U)
+#define ADC_SQR2_SQ11_Msk (0x1FU << ADC_SQR2_SQ11_Pos) /*!< 0x01F00000 */
+#define ADC_SQR2_SQ11 ADC_SQR2_SQ11_Msk /*!< ADC group regular sequencer rank 1 */
+#define ADC_SQR2_SQ11_0 (0x01U << ADC_SQR2_SQ11_Pos) /*!< 0x00100000 */
+#define ADC_SQR2_SQ11_1 (0x02U << ADC_SQR2_SQ11_Pos) /*!< 0x00200000 */
+#define ADC_SQR2_SQ11_2 (0x04U << ADC_SQR2_SQ11_Pos) /*!< 0x00400000 */
+#define ADC_SQR2_SQ11_3 (0x08U << ADC_SQR2_SQ11_Pos) /*!< 0x00800000 */
+#define ADC_SQR2_SQ11_4 (0x10U << ADC_SQR2_SQ11_Pos) /*!< 0x01000000 */
+
+#define ADC_SQR2_SQ12_Pos (25U)
+#define ADC_SQR2_SQ12_Msk (0x1FU << ADC_SQR2_SQ12_Pos) /*!< 0x3E000000 */
+#define ADC_SQR2_SQ12 ADC_SQR2_SQ12_Msk /*!< ADC group regular sequencer rank 12 */
+#define ADC_SQR2_SQ12_0 (0x01U << ADC_SQR2_SQ12_Pos) /*!< 0x02000000 */
+#define ADC_SQR2_SQ12_1 (0x02U << ADC_SQR2_SQ12_Pos) /*!< 0x04000000 */
+#define ADC_SQR2_SQ12_2 (0x04U << ADC_SQR2_SQ12_Pos) /*!< 0x08000000 */
+#define ADC_SQR2_SQ12_3 (0x08U << ADC_SQR2_SQ12_Pos) /*!< 0x10000000 */
+#define ADC_SQR2_SQ12_4 (0x10U << ADC_SQR2_SQ12_Pos) /*!< 0x20000000 */
+
+/******************* Bit definition for ADC_SQR3 register *******************/
+#define ADC_SQR3_SQ1_Pos (0U)
+#define ADC_SQR3_SQ1_Msk (0x1FU << ADC_SQR3_SQ1_Pos) /*!< 0x0000001F */
+#define ADC_SQR3_SQ1 ADC_SQR3_SQ1_Msk /*!< ADC group regular sequencer rank 1 */
+#define ADC_SQR3_SQ1_0 (0x01U << ADC_SQR3_SQ1_Pos) /*!< 0x00000001 */
+#define ADC_SQR3_SQ1_1 (0x02U << ADC_SQR3_SQ1_Pos) /*!< 0x00000002 */
+#define ADC_SQR3_SQ1_2 (0x04U << ADC_SQR3_SQ1_Pos) /*!< 0x00000004 */
+#define ADC_SQR3_SQ1_3 (0x08U << ADC_SQR3_SQ1_Pos) /*!< 0x00000008 */
+#define ADC_SQR3_SQ1_4 (0x10U << ADC_SQR3_SQ1_Pos) /*!< 0x00000010 */
+
+#define ADC_SQR3_SQ2_Pos (5U)
+#define ADC_SQR3_SQ2_Msk (0x1FU << ADC_SQR3_SQ2_Pos) /*!< 0x000003E0 */
+#define ADC_SQR3_SQ2 ADC_SQR3_SQ2_Msk /*!< ADC group regular sequencer rank 2 */
+#define ADC_SQR3_SQ2_0 (0x01U << ADC_SQR3_SQ2_Pos) /*!< 0x00000020 */
+#define ADC_SQR3_SQ2_1 (0x02U << ADC_SQR3_SQ2_Pos) /*!< 0x00000040 */
+#define ADC_SQR3_SQ2_2 (0x04U << ADC_SQR3_SQ2_Pos) /*!< 0x00000080 */
+#define ADC_SQR3_SQ2_3 (0x08U << ADC_SQR3_SQ2_Pos) /*!< 0x00000100 */
+#define ADC_SQR3_SQ2_4 (0x10U << ADC_SQR3_SQ2_Pos) /*!< 0x00000200 */
+
+#define ADC_SQR3_SQ3_Pos (10U)
+#define ADC_SQR3_SQ3_Msk (0x1FU << ADC_SQR3_SQ3_Pos) /*!< 0x00007C00 */
+#define ADC_SQR3_SQ3 ADC_SQR3_SQ3_Msk /*!< ADC group regular sequencer rank 3 */
+#define ADC_SQR3_SQ3_0 (0x01U << ADC_SQR3_SQ3_Pos) /*!< 0x00000400 */
+#define ADC_SQR3_SQ3_1 (0x02U << ADC_SQR3_SQ3_Pos) /*!< 0x00000800 */
+#define ADC_SQR3_SQ3_2 (0x04U << ADC_SQR3_SQ3_Pos) /*!< 0x00001000 */
+#define ADC_SQR3_SQ3_3 (0x08U << ADC_SQR3_SQ3_Pos) /*!< 0x00002000 */
+#define ADC_SQR3_SQ3_4 (0x10U << ADC_SQR3_SQ3_Pos) /*!< 0x00004000 */
+
+#define ADC_SQR3_SQ4_Pos (15U)
+#define ADC_SQR3_SQ4_Msk (0x1FU << ADC_SQR3_SQ4_Pos) /*!< 0x000F8000 */
+#define ADC_SQR3_SQ4 ADC_SQR3_SQ4_Msk /*!< ADC group regular sequencer rank 4 */
+#define ADC_SQR3_SQ4_0 (0x01U << ADC_SQR3_SQ4_Pos) /*!< 0x00008000 */
+#define ADC_SQR3_SQ4_1 (0x02U << ADC_SQR3_SQ4_Pos) /*!< 0x00010000 */
+#define ADC_SQR3_SQ4_2 (0x04U << ADC_SQR3_SQ4_Pos) /*!< 0x00020000 */
+#define ADC_SQR3_SQ4_3 (0x08U << ADC_SQR3_SQ4_Pos) /*!< 0x00040000 */
+#define ADC_SQR3_SQ4_4 (0x10U << ADC_SQR3_SQ4_Pos) /*!< 0x00080000 */
+
+#define ADC_SQR3_SQ5_Pos (20U)
+#define ADC_SQR3_SQ5_Msk (0x1FU << ADC_SQR3_SQ5_Pos) /*!< 0x01F00000 */
+#define ADC_SQR3_SQ5 ADC_SQR3_SQ5_Msk /*!< ADC group regular sequencer rank 5 */
+#define ADC_SQR3_SQ5_0 (0x01U << ADC_SQR3_SQ5_Pos) /*!< 0x00100000 */
+#define ADC_SQR3_SQ5_1 (0x02U << ADC_SQR3_SQ5_Pos) /*!< 0x00200000 */
+#define ADC_SQR3_SQ5_2 (0x04U << ADC_SQR3_SQ5_Pos) /*!< 0x00400000 */
+#define ADC_SQR3_SQ5_3 (0x08U << ADC_SQR3_SQ5_Pos) /*!< 0x00800000 */
+#define ADC_SQR3_SQ5_4 (0x10U << ADC_SQR3_SQ5_Pos) /*!< 0x01000000 */
+
+#define ADC_SQR3_SQ6_Pos (25U)
+#define ADC_SQR3_SQ6_Msk (0x1FU << ADC_SQR3_SQ6_Pos) /*!< 0x3E000000 */
+#define ADC_SQR3_SQ6 ADC_SQR3_SQ6_Msk /*!< ADC group regular sequencer rank 6 */
+#define ADC_SQR3_SQ6_0 (0x01U << ADC_SQR3_SQ6_Pos) /*!< 0x02000000 */
+#define ADC_SQR3_SQ6_1 (0x02U << ADC_SQR3_SQ6_Pos) /*!< 0x04000000 */
+#define ADC_SQR3_SQ6_2 (0x04U << ADC_SQR3_SQ6_Pos) /*!< 0x08000000 */
+#define ADC_SQR3_SQ6_3 (0x08U << ADC_SQR3_SQ6_Pos) /*!< 0x10000000 */
+#define ADC_SQR3_SQ6_4 (0x10U << ADC_SQR3_SQ6_Pos) /*!< 0x20000000 */
+
+/******************* Bit definition for ADC_JSQR register *******************/
+#define ADC_JSQR_JSQ1_Pos (0U)
+#define ADC_JSQR_JSQ1_Msk (0x1FU << ADC_JSQR_JSQ1_Pos) /*!< 0x0000001F */
+#define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!< ADC group injected sequencer rank 1 */
+#define ADC_JSQR_JSQ1_0 (0x01U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000001 */
+#define ADC_JSQR_JSQ1_1 (0x02U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000002 */
+#define ADC_JSQR_JSQ1_2 (0x04U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000004 */
+#define ADC_JSQR_JSQ1_3 (0x08U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000008 */
+#define ADC_JSQR_JSQ1_4 (0x10U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000010 */
+
+#define ADC_JSQR_JSQ2_Pos (5U)
+#define ADC_JSQR_JSQ2_Msk (0x1FU << ADC_JSQR_JSQ2_Pos) /*!< 0x000003E0 */
+#define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!< ADC group injected sequencer rank 2 */
+#define ADC_JSQR_JSQ2_0 (0x01U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000020 */
+#define ADC_JSQR_JSQ2_1 (0x02U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000040 */
+#define ADC_JSQR_JSQ2_2 (0x04U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000080 */
+#define ADC_JSQR_JSQ2_3 (0x08U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000100 */
+#define ADC_JSQR_JSQ2_4 (0x10U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000200 */
+
+#define ADC_JSQR_JSQ3_Pos (10U)
+#define ADC_JSQR_JSQ3_Msk (0x1FU << ADC_JSQR_JSQ3_Pos) /*!< 0x00007C00 */
+#define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!< ADC group injected sequencer rank 3 */
+#define ADC_JSQR_JSQ3_0 (0x01U << ADC_JSQR_JSQ3_Pos) /*!< 0x00000400 */
+#define ADC_JSQR_JSQ3_1 (0x02U << ADC_JSQR_JSQ3_Pos) /*!< 0x00000800 */
+#define ADC_JSQR_JSQ3_2 (0x04U << ADC_JSQR_JSQ3_Pos) /*!< 0x00001000 */
+#define ADC_JSQR_JSQ3_3 (0x08U << ADC_JSQR_JSQ3_Pos) /*!< 0x00002000 */
+#define ADC_JSQR_JSQ3_4 (0x10U << ADC_JSQR_JSQ3_Pos) /*!< 0x00004000 */
+
+#define ADC_JSQR_JSQ4_Pos (15U)
+#define ADC_JSQR_JSQ4_Msk (0x1FU << ADC_JSQR_JSQ4_Pos) /*!< 0x000F8000 */
+#define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!< ADC group injected sequencer rank 4 */
+#define ADC_JSQR_JSQ4_0 (0x01U << ADC_JSQR_JSQ4_Pos) /*!< 0x00008000 */
+#define ADC_JSQR_JSQ4_1 (0x02U << ADC_JSQR_JSQ4_Pos) /*!< 0x00010000 */
+#define ADC_JSQR_JSQ4_2 (0x04U << ADC_JSQR_JSQ4_Pos) /*!< 0x00020000 */
+#define ADC_JSQR_JSQ4_3 (0x08U << ADC_JSQR_JSQ4_Pos) /*!< 0x00040000 */
+#define ADC_JSQR_JSQ4_4 (0x10U << ADC_JSQR_JSQ4_Pos) /*!< 0x00080000 */
+
+#define ADC_JSQR_JL_Pos (20U)
+#define ADC_JSQR_JL_Msk (0x3U << ADC_JSQR_JL_Pos) /*!< 0x00300000 */
+#define ADC_JSQR_JL ADC_JSQR_JL_Msk /*!< ADC group injected sequencer scan length */
+#define ADC_JSQR_JL_0 (0x1U << ADC_JSQR_JL_Pos) /*!< 0x00100000 */
+#define ADC_JSQR_JL_1 (0x2U << ADC_JSQR_JL_Pos) /*!< 0x00200000 */
+
+/******************* Bit definition for ADC_JDR1 register *******************/
+#define ADC_JDR1_JDATA_Pos (0U)
+#define ADC_JDR1_JDATA_Msk (0xFFFFU << ADC_JDR1_JDATA_Pos) /*!< 0x0000FFFF */
+#define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!< ADC group injected sequencer rank 1 conversion data */
+
+/******************* Bit definition for ADC_JDR2 register *******************/
+#define ADC_JDR2_JDATA_Pos (0U)
+#define ADC_JDR2_JDATA_Msk (0xFFFFU << ADC_JDR2_JDATA_Pos) /*!< 0x0000FFFF */
+#define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!< ADC group injected sequencer rank 2 conversion data */
+
+/******************* Bit definition for ADC_JDR3 register *******************/
+#define ADC_JDR3_JDATA_Pos (0U)
+#define ADC_JDR3_JDATA_Msk (0xFFFFU << ADC_JDR3_JDATA_Pos) /*!< 0x0000FFFF */
+#define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!< ADC group injected sequencer rank 3 conversion data */
+
+/******************* Bit definition for ADC_JDR4 register *******************/
+#define ADC_JDR4_JDATA_Pos (0U)
+#define ADC_JDR4_JDATA_Msk (0xFFFFU << ADC_JDR4_JDATA_Pos) /*!< 0x0000FFFF */
+#define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!< ADC group injected sequencer rank 4 conversion data */
+
+/******************** Bit definition for ADC_DR register ********************/
+#define ADC_DR_DATA_Pos (0U)
+#define ADC_DR_DATA_Msk (0xFFFFU << ADC_DR_DATA_Pos) /*!< 0x0000FFFF */
+#define ADC_DR_DATA ADC_DR_DATA_Msk /*!< ADC group regular conversion data */
+
+
+/*****************************************************************************/
+/* */
+/* Timers (TIM) */
+/* */
+/*****************************************************************************/
+/******************* Bit definition for TIM_CR1 register *******************/
+#define TIM_CR1_CEN_Pos (0U)
+#define TIM_CR1_CEN_Msk (0x1U << TIM_CR1_CEN_Pos) /*!< 0x00000001 */
+#define TIM_CR1_CEN TIM_CR1_CEN_Msk /*!<Counter enable */
+#define TIM_CR1_UDIS_Pos (1U)
+#define TIM_CR1_UDIS_Msk (0x1U << TIM_CR1_UDIS_Pos) /*!< 0x00000002 */
+#define TIM_CR1_UDIS TIM_CR1_UDIS_Msk /*!<Update disable */
+#define TIM_CR1_URS_Pos (2U)
+#define TIM_CR1_URS_Msk (0x1U << TIM_CR1_URS_Pos) /*!< 0x00000004 */
+#define TIM_CR1_URS TIM_CR1_URS_Msk /*!<Update request source */
+#define TIM_CR1_OPM_Pos (3U)
+#define TIM_CR1_OPM_Msk (0x1U << TIM_CR1_OPM_Pos) /*!< 0x00000008 */
+#define TIM_CR1_OPM TIM_CR1_OPM_Msk /*!<One pulse mode */
+#define TIM_CR1_DIR_Pos (4U)
+#define TIM_CR1_DIR_Msk (0x1U << TIM_CR1_DIR_Pos) /*!< 0x00000010 */
+#define TIM_CR1_DIR TIM_CR1_DIR_Msk /*!<Direction */
+
+#define TIM_CR1_CMS_Pos (5U)
+#define TIM_CR1_CMS_Msk (0x3U << TIM_CR1_CMS_Pos) /*!< 0x00000060 */
+#define TIM_CR1_CMS TIM_CR1_CMS_Msk /*!<CMS[1:0] bits (Center-aligned mode selection) */
+#define TIM_CR1_CMS_0 (0x1U << TIM_CR1_CMS_Pos) /*!< 0x00000020 */
+#define TIM_CR1_CMS_1 (0x2U << TIM_CR1_CMS_Pos) /*!< 0x00000040 */
+
+#define TIM_CR1_ARPE_Pos (7U)
+#define TIM_CR1_ARPE_Msk (0x1U << TIM_CR1_ARPE_Pos) /*!< 0x00000080 */
+#define TIM_CR1_ARPE TIM_CR1_ARPE_Msk /*!<Auto-reload preload enable */
+
+#define TIM_CR1_CKD_Pos (8U)
+#define TIM_CR1_CKD_Msk (0x3U << TIM_CR1_CKD_Pos) /*!< 0x00000300 */
+#define TIM_CR1_CKD TIM_CR1_CKD_Msk /*!<CKD[1:0] bits (clock division) */
+#define TIM_CR1_CKD_0 (0x1U << TIM_CR1_CKD_Pos) /*!< 0x00000100 */
+#define TIM_CR1_CKD_1 (0x2U << TIM_CR1_CKD_Pos) /*!< 0x00000200 */
+
+/******************* Bit definition for TIM_CR2 register *******************/
+#define TIM_CR2_CCPC_Pos (0U)
+#define TIM_CR2_CCPC_Msk (0x1U << TIM_CR2_CCPC_Pos) /*!< 0x00000001 */
+#define TIM_CR2_CCPC TIM_CR2_CCPC_Msk /*!<Capture/Compare Preloaded Control */
+#define TIM_CR2_CCUS_Pos (2U)
+#define TIM_CR2_CCUS_Msk (0x1U << TIM_CR2_CCUS_Pos) /*!< 0x00000004 */
+#define TIM_CR2_CCUS TIM_CR2_CCUS_Msk /*!<Capture/Compare Control Update Selection */
+#define TIM_CR2_CCDS_Pos (3U)
+#define TIM_CR2_CCDS_Msk (0x1U << TIM_CR2_CCDS_Pos) /*!< 0x00000008 */
+#define TIM_CR2_CCDS TIM_CR2_CCDS_Msk /*!<Capture/Compare DMA Selection */
+
+#define TIM_CR2_MMS_Pos (4U)
+#define TIM_CR2_MMS_Msk (0x7U << TIM_CR2_MMS_Pos) /*!< 0x00000070 */
+#define TIM_CR2_MMS TIM_CR2_MMS_Msk /*!<MMS[2:0] bits (Master Mode Selection) */
+#define TIM_CR2_MMS_0 (0x1U << TIM_CR2_MMS_Pos) /*!< 0x00000010 */
+#define TIM_CR2_MMS_1 (0x2U << TIM_CR2_MMS_Pos) /*!< 0x00000020 */
+#define TIM_CR2_MMS_2 (0x4U << TIM_CR2_MMS_Pos) /*!< 0x00000040 */
+
+#define TIM_CR2_TI1S_Pos (7U)
+#define TIM_CR2_TI1S_Msk (0x1U << TIM_CR2_TI1S_Pos) /*!< 0x00000080 */
+#define TIM_CR2_TI1S TIM_CR2_TI1S_Msk /*!<TI1 Selection */
+#define TIM_CR2_OIS1_Pos (8U)
+#define TIM_CR2_OIS1_Msk (0x1U << TIM_CR2_OIS1_Pos) /*!< 0x00000100 */
+#define TIM_CR2_OIS1 TIM_CR2_OIS1_Msk /*!<Output Idle state 1 (OC1 output) */
+#define TIM_CR2_OIS1N_Pos (9U)
+#define TIM_CR2_OIS1N_Msk (0x1U << TIM_CR2_OIS1N_Pos) /*!< 0x00000200 */
+#define TIM_CR2_OIS1N TIM_CR2_OIS1N_Msk /*!<Output Idle state 1 (OC1N output) */
+#define TIM_CR2_OIS2_Pos (10U)
+#define TIM_CR2_OIS2_Msk (0x1U << TIM_CR2_OIS2_Pos) /*!< 0x00000400 */
+#define TIM_CR2_OIS2 TIM_CR2_OIS2_Msk /*!<Output Idle state 2 (OC2 output) */
+#define TIM_CR2_OIS2N_Pos (11U)
+#define TIM_CR2_OIS2N_Msk (0x1U << TIM_CR2_OIS2N_Pos) /*!< 0x00000800 */
+#define TIM_CR2_OIS2N TIM_CR2_OIS2N_Msk /*!<Output Idle state 2 (OC2N output) */
+#define TIM_CR2_OIS3_Pos (12U)
+#define TIM_CR2_OIS3_Msk (0x1U << TIM_CR2_OIS3_Pos) /*!< 0x00001000 */
+#define TIM_CR2_OIS3 TIM_CR2_OIS3_Msk /*!<Output Idle state 3 (OC3 output) */
+#define TIM_CR2_OIS3N_Pos (13U)
+#define TIM_CR2_OIS3N_Msk (0x1U << TIM_CR2_OIS3N_Pos) /*!< 0x00002000 */
+#define TIM_CR2_OIS3N TIM_CR2_OIS3N_Msk /*!<Output Idle state 3 (OC3N output) */
+#define TIM_CR2_OIS4_Pos (14U)
+#define TIM_CR2_OIS4_Msk (0x1U << TIM_CR2_OIS4_Pos) /*!< 0x00004000 */
+#define TIM_CR2_OIS4 TIM_CR2_OIS4_Msk /*!<Output Idle state 4 (OC4 output) */
+
+/******************* Bit definition for TIM_SMCR register ******************/
+#define TIM_SMCR_SMS_Pos (0U)
+#define TIM_SMCR_SMS_Msk (0x7U << TIM_SMCR_SMS_Pos) /*!< 0x00000007 */
+#define TIM_SMCR_SMS TIM_SMCR_SMS_Msk /*!<SMS[2:0] bits (Slave mode selection) */
+#define TIM_SMCR_SMS_0 (0x1U << TIM_SMCR_SMS_Pos) /*!< 0x00000001 */
+#define TIM_SMCR_SMS_1 (0x2U << TIM_SMCR_SMS_Pos) /*!< 0x00000002 */
+#define TIM_SMCR_SMS_2 (0x4U << TIM_SMCR_SMS_Pos) /*!< 0x00000004 */
+
+#define TIM_SMCR_OCCS_Pos (3U)
+#define TIM_SMCR_OCCS_Msk (0x1U << TIM_SMCR_OCCS_Pos) /*!< 0x00000008 */
+#define TIM_SMCR_OCCS TIM_SMCR_OCCS_Msk /*!< OCREF clear selection */
+
+#define TIM_SMCR_TS_Pos (4U)
+#define TIM_SMCR_TS_Msk (0x7U << TIM_SMCR_TS_Pos) /*!< 0x00000070 */
+#define TIM_SMCR_TS TIM_SMCR_TS_Msk /*!<TS[2:0] bits (Trigger selection) */
+#define TIM_SMCR_TS_0 (0x1U << TIM_SMCR_TS_Pos) /*!< 0x00000010 */
+#define TIM_SMCR_TS_1 (0x2U << TIM_SMCR_TS_Pos) /*!< 0x00000020 */
+#define TIM_SMCR_TS_2 (0x4U << TIM_SMCR_TS_Pos) /*!< 0x00000040 */
+
+#define TIM_SMCR_MSM_Pos (7U)
+#define TIM_SMCR_MSM_Msk (0x1U << TIM_SMCR_MSM_Pos) /*!< 0x00000080 */
+#define TIM_SMCR_MSM TIM_SMCR_MSM_Msk /*!<Master/slave mode */
+
+#define TIM_SMCR_ETF_Pos (8U)
+#define TIM_SMCR_ETF_Msk (0xFU << TIM_SMCR_ETF_Pos) /*!< 0x00000F00 */
+#define TIM_SMCR_ETF TIM_SMCR_ETF_Msk /*!<ETF[3:0] bits (External trigger filter) */
+#define TIM_SMCR_ETF_0 (0x1U << TIM_SMCR_ETF_Pos) /*!< 0x00000100 */
+#define TIM_SMCR_ETF_1 (0x2U << TIM_SMCR_ETF_Pos) /*!< 0x00000200 */
+#define TIM_SMCR_ETF_2 (0x4U << TIM_SMCR_ETF_Pos) /*!< 0x00000400 */
+#define TIM_SMCR_ETF_3 (0x8U << TIM_SMCR_ETF_Pos) /*!< 0x00000800 */
+
+#define TIM_SMCR_ETPS_Pos (12U)
+#define TIM_SMCR_ETPS_Msk (0x3U << TIM_SMCR_ETPS_Pos) /*!< 0x00003000 */
+#define TIM_SMCR_ETPS TIM_SMCR_ETPS_Msk /*!<ETPS[1:0] bits (External trigger prescaler) */
+#define TIM_SMCR_ETPS_0 (0x1U << TIM_SMCR_ETPS_Pos) /*!< 0x00001000 */
+#define TIM_SMCR_ETPS_1 (0x2U << TIM_SMCR_ETPS_Pos) /*!< 0x00002000 */
+
+#define TIM_SMCR_ECE_Pos (14U)
+#define TIM_SMCR_ECE_Msk (0x1U << TIM_SMCR_ECE_Pos) /*!< 0x00004000 */
+#define TIM_SMCR_ECE TIM_SMCR_ECE_Msk /*!<External clock enable */
+#define TIM_SMCR_ETP_Pos (15U)
+#define TIM_SMCR_ETP_Msk (0x1U << TIM_SMCR_ETP_Pos) /*!< 0x00008000 */
+#define TIM_SMCR_ETP TIM_SMCR_ETP_Msk /*!<External trigger polarity */
+
+/******************* Bit definition for TIM_DIER register ******************/
+#define TIM_DIER_UIE_Pos (0U)
+#define TIM_DIER_UIE_Msk (0x1U << TIM_DIER_UIE_Pos) /*!< 0x00000001 */
+#define TIM_DIER_UIE TIM_DIER_UIE_Msk /*!<Update interrupt enable */
+#define TIM_DIER_CC1IE_Pos (1U)
+#define TIM_DIER_CC1IE_Msk (0x1U << TIM_DIER_CC1IE_Pos) /*!< 0x00000002 */
+#define TIM_DIER_CC1IE TIM_DIER_CC1IE_Msk /*!<Capture/Compare 1 interrupt enable */
+#define TIM_DIER_CC2IE_Pos (2U)
+#define TIM_DIER_CC2IE_Msk (0x1U << TIM_DIER_CC2IE_Pos) /*!< 0x00000004 */
+#define TIM_DIER_CC2IE TIM_DIER_CC2IE_Msk /*!<Capture/Compare 2 interrupt enable */
+#define TIM_DIER_CC3IE_Pos (3U)
+#define TIM_DIER_CC3IE_Msk (0x1U << TIM_DIER_CC3IE_Pos) /*!< 0x00000008 */
+#define TIM_DIER_CC3IE TIM_DIER_CC3IE_Msk /*!<Capture/Compare 3 interrupt enable */
+#define TIM_DIER_CC4IE_Pos (4U)
+#define TIM_DIER_CC4IE_Msk (0x1U << TIM_DIER_CC4IE_Pos) /*!< 0x00000010 */
+#define TIM_DIER_CC4IE TIM_DIER_CC4IE_Msk /*!<Capture/Compare 4 interrupt enable */
+#define TIM_DIER_COMIE_Pos (5U)
+#define TIM_DIER_COMIE_Msk (0x1U << TIM_DIER_COMIE_Pos) /*!< 0x00000020 */
+#define TIM_DIER_COMIE TIM_DIER_COMIE_Msk /*!<COM interrupt enable */
+#define TIM_DIER_TIE_Pos (6U)
+#define TIM_DIER_TIE_Msk (0x1U << TIM_DIER_TIE_Pos) /*!< 0x00000040 */
+#define TIM_DIER_TIE TIM_DIER_TIE_Msk /*!<Trigger interrupt enable */
+#define TIM_DIER_BIE_Pos (7U)
+#define TIM_DIER_BIE_Msk (0x1U << TIM_DIER_BIE_Pos) /*!< 0x00000080 */
+#define TIM_DIER_BIE TIM_DIER_BIE_Msk /*!<Break interrupt enable */
+#define TIM_DIER_UDE_Pos (8U)
+#define TIM_DIER_UDE_Msk (0x1U << TIM_DIER_UDE_Pos) /*!< 0x00000100 */
+#define TIM_DIER_UDE TIM_DIER_UDE_Msk /*!<Update DMA request enable */
+#define TIM_DIER_CC1DE_Pos (9U)
+#define TIM_DIER_CC1DE_Msk (0x1U << TIM_DIER_CC1DE_Pos) /*!< 0x00000200 */
+#define TIM_DIER_CC1DE TIM_DIER_CC1DE_Msk /*!<Capture/Compare 1 DMA request enable */
+#define TIM_DIER_CC2DE_Pos (10U)
+#define TIM_DIER_CC2DE_Msk (0x1U << TIM_DIER_CC2DE_Pos) /*!< 0x00000400 */
+#define TIM_DIER_CC2DE TIM_DIER_CC2DE_Msk /*!<Capture/Compare 2 DMA request enable */
+#define TIM_DIER_CC3DE_Pos (11U)
+#define TIM_DIER_CC3DE_Msk (0x1U << TIM_DIER_CC3DE_Pos) /*!< 0x00000800 */
+#define TIM_DIER_CC3DE TIM_DIER_CC3DE_Msk /*!<Capture/Compare 3 DMA request enable */
+#define TIM_DIER_CC4DE_Pos (12U)
+#define TIM_DIER_CC4DE_Msk (0x1U << TIM_DIER_CC4DE_Pos) /*!< 0x00001000 */
+#define TIM_DIER_CC4DE TIM_DIER_CC4DE_Msk /*!<Capture/Compare 4 DMA request enable */
+#define TIM_DIER_COMDE_Pos (13U)
+#define TIM_DIER_COMDE_Msk (0x1U << TIM_DIER_COMDE_Pos) /*!< 0x00002000 */
+#define TIM_DIER_COMDE TIM_DIER_COMDE_Msk /*!<COM DMA request enable */
+#define TIM_DIER_TDE_Pos (14U)
+#define TIM_DIER_TDE_Msk (0x1U << TIM_DIER_TDE_Pos) /*!< 0x00004000 */
+#define TIM_DIER_TDE TIM_DIER_TDE_Msk /*!<Trigger DMA request enable */
+
+/******************** Bit definition for TIM_SR register *******************/
+#define TIM_SR_UIF_Pos (0U)
+#define TIM_SR_UIF_Msk (0x1U << TIM_SR_UIF_Pos) /*!< 0x00000001 */
+#define TIM_SR_UIF TIM_SR_UIF_Msk /*!<Update interrupt Flag */
+#define TIM_SR_CC1IF_Pos (1U)
+#define TIM_SR_CC1IF_Msk (0x1U << TIM_SR_CC1IF_Pos) /*!< 0x00000002 */
+#define TIM_SR_CC1IF TIM_SR_CC1IF_Msk /*!<Capture/Compare 1 interrupt Flag */
+#define TIM_SR_CC2IF_Pos (2U)
+#define TIM_SR_CC2IF_Msk (0x1U << TIM_SR_CC2IF_Pos) /*!< 0x00000004 */
+#define TIM_SR_CC2IF TIM_SR_CC2IF_Msk /*!<Capture/Compare 2 interrupt Flag */
+#define TIM_SR_CC3IF_Pos (3U)
+#define TIM_SR_CC3IF_Msk (0x1U << TIM_SR_CC3IF_Pos) /*!< 0x00000008 */
+#define TIM_SR_CC3IF TIM_SR_CC3IF_Msk /*!<Capture/Compare 3 interrupt Flag */
+#define TIM_SR_CC4IF_Pos (4U)
+#define TIM_SR_CC4IF_Msk (0x1U << TIM_SR_CC4IF_Pos) /*!< 0x00000010 */
+#define TIM_SR_CC4IF TIM_SR_CC4IF_Msk /*!<Capture/Compare 4 interrupt Flag */
+#define TIM_SR_COMIF_Pos (5U)
+#define TIM_SR_COMIF_Msk (0x1U << TIM_SR_COMIF_Pos) /*!< 0x00000020 */
+#define TIM_SR_COMIF TIM_SR_COMIF_Msk /*!<COM interrupt Flag */
+#define TIM_SR_TIF_Pos (6U)
+#define TIM_SR_TIF_Msk (0x1U << TIM_SR_TIF_Pos) /*!< 0x00000040 */
+#define TIM_SR_TIF TIM_SR_TIF_Msk /*!<Trigger interrupt Flag */
+#define TIM_SR_BIF_Pos (7U)
+#define TIM_SR_BIF_Msk (0x1U << TIM_SR_BIF_Pos) /*!< 0x00000080 */
+#define TIM_SR_BIF TIM_SR_BIF_Msk /*!<Break interrupt Flag */
+#define TIM_SR_CC1OF_Pos (9U)
+#define TIM_SR_CC1OF_Msk (0x1U << TIM_SR_CC1OF_Pos) /*!< 0x00000200 */
+#define TIM_SR_CC1OF TIM_SR_CC1OF_Msk /*!<Capture/Compare 1 Overcapture Flag */
+#define TIM_SR_CC2OF_Pos (10U)
+#define TIM_SR_CC2OF_Msk (0x1U << TIM_SR_CC2OF_Pos) /*!< 0x00000400 */
+#define TIM_SR_CC2OF TIM_SR_CC2OF_Msk /*!<Capture/Compare 2 Overcapture Flag */
+#define TIM_SR_CC3OF_Pos (11U)
+#define TIM_SR_CC3OF_Msk (0x1U << TIM_SR_CC3OF_Pos) /*!< 0x00000800 */
+#define TIM_SR_CC3OF TIM_SR_CC3OF_Msk /*!<Capture/Compare 3 Overcapture Flag */
+#define TIM_SR_CC4OF_Pos (12U)
+#define TIM_SR_CC4OF_Msk (0x1U << TIM_SR_CC4OF_Pos) /*!< 0x00001000 */
+#define TIM_SR_CC4OF TIM_SR_CC4OF_Msk /*!<Capture/Compare 4 Overcapture Flag */
+
+/******************* Bit definition for TIM_EGR register *******************/
+#define TIM_EGR_UG_Pos (0U)
+#define TIM_EGR_UG_Msk (0x1U << TIM_EGR_UG_Pos) /*!< 0x00000001 */
+#define TIM_EGR_UG TIM_EGR_UG_Msk /*!<Update Generation */
+#define TIM_EGR_CC1G_Pos (1U)
+#define TIM_EGR_CC1G_Msk (0x1U << TIM_EGR_CC1G_Pos) /*!< 0x00000002 */
+#define TIM_EGR_CC1G TIM_EGR_CC1G_Msk /*!<Capture/Compare 1 Generation */
+#define TIM_EGR_CC2G_Pos (2U)
+#define TIM_EGR_CC2G_Msk (0x1U << TIM_EGR_CC2G_Pos) /*!< 0x00000004 */
+#define TIM_EGR_CC2G TIM_EGR_CC2G_Msk /*!<Capture/Compare 2 Generation */
+#define TIM_EGR_CC3G_Pos (3U)
+#define TIM_EGR_CC3G_Msk (0x1U << TIM_EGR_CC3G_Pos) /*!< 0x00000008 */
+#define TIM_EGR_CC3G TIM_EGR_CC3G_Msk /*!<Capture/Compare 3 Generation */
+#define TIM_EGR_CC4G_Pos (4U)
+#define TIM_EGR_CC4G_Msk (0x1U << TIM_EGR_CC4G_Pos) /*!< 0x00000010 */
+#define TIM_EGR_CC4G TIM_EGR_CC4G_Msk /*!<Capture/Compare 4 Generation */
+#define TIM_EGR_COMG_Pos (5U)
+#define TIM_EGR_COMG_Msk (0x1U << TIM_EGR_COMG_Pos) /*!< 0x00000020 */
+#define TIM_EGR_COMG TIM_EGR_COMG_Msk /*!<Capture/Compare Control Update Generation */
+#define TIM_EGR_TG_Pos (6U)
+#define TIM_EGR_TG_Msk (0x1U << TIM_EGR_TG_Pos) /*!< 0x00000040 */
+#define TIM_EGR_TG TIM_EGR_TG_Msk /*!<Trigger Generation */
+#define TIM_EGR_BG_Pos (7U)
+#define TIM_EGR_BG_Msk (0x1U << TIM_EGR_BG_Pos) /*!< 0x00000080 */
+#define TIM_EGR_BG TIM_EGR_BG_Msk /*!<Break Generation */
+
+/****************** Bit definition for TIM_CCMR1 register ******************/
+#define TIM_CCMR1_CC1S_Pos (0U)
+#define TIM_CCMR1_CC1S_Msk (0x3U << TIM_CCMR1_CC1S_Pos) /*!< 0x00000003 */
+#define TIM_CCMR1_CC1S TIM_CCMR1_CC1S_Msk /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
+#define TIM_CCMR1_CC1S_0 (0x1U << TIM_CCMR1_CC1S_Pos) /*!< 0x00000001 */
+#define TIM_CCMR1_CC1S_1 (0x2U << TIM_CCMR1_CC1S_Pos) /*!< 0x00000002 */
+
+#define TIM_CCMR1_OC1FE_Pos (2U)
+#define TIM_CCMR1_OC1FE_Msk (0x1U << TIM_CCMR1_OC1FE_Pos) /*!< 0x00000004 */
+#define TIM_CCMR1_OC1FE TIM_CCMR1_OC1FE_Msk /*!<Output Compare 1 Fast enable */
+#define TIM_CCMR1_OC1PE_Pos (3U)
+#define TIM_CCMR1_OC1PE_Msk (0x1U << TIM_CCMR1_OC1PE_Pos) /*!< 0x00000008 */
+#define TIM_CCMR1_OC1PE TIM_CCMR1_OC1PE_Msk /*!<Output Compare 1 Preload enable */
+
+#define TIM_CCMR1_OC1M_Pos (4U)
+#define TIM_CCMR1_OC1M_Msk (0x7U << TIM_CCMR1_OC1M_Pos) /*!< 0x00000070 */
+#define TIM_CCMR1_OC1M TIM_CCMR1_OC1M_Msk /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
+#define TIM_CCMR1_OC1M_0 (0x1U << TIM_CCMR1_OC1M_Pos) /*!< 0x00000010 */
+#define TIM_CCMR1_OC1M_1 (0x2U << TIM_CCMR1_OC1M_Pos) /*!< 0x00000020 */
+#define TIM_CCMR1_OC1M_2 (0x4U << TIM_CCMR1_OC1M_Pos) /*!< 0x00000040 */
+
+#define TIM_CCMR1_OC1CE_Pos (7U)
+#define TIM_CCMR1_OC1CE_Msk (0x1U << TIM_CCMR1_OC1CE_Pos) /*!< 0x00000080 */
+#define TIM_CCMR1_OC1CE TIM_CCMR1_OC1CE_Msk /*!<Output Compare 1Clear Enable */
+
+#define TIM_CCMR1_CC2S_Pos (8U)
+#define TIM_CCMR1_CC2S_Msk (0x3U << TIM_CCMR1_CC2S_Pos) /*!< 0x00000300 */
+#define TIM_CCMR1_CC2S TIM_CCMR1_CC2S_Msk /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
+#define TIM_CCMR1_CC2S_0 (0x1U << TIM_CCMR1_CC2S_Pos) /*!< 0x00000100 */
+#define TIM_CCMR1_CC2S_1 (0x2U << TIM_CCMR1_CC2S_Pos) /*!< 0x00000200 */
+
+#define TIM_CCMR1_OC2FE_Pos (10U)
+#define TIM_CCMR1_OC2FE_Msk (0x1U << TIM_CCMR1_OC2FE_Pos) /*!< 0x00000400 */
+#define TIM_CCMR1_OC2FE TIM_CCMR1_OC2FE_Msk /*!<Output Compare 2 Fast enable */
+#define TIM_CCMR1_OC2PE_Pos (11U)
+#define TIM_CCMR1_OC2PE_Msk (0x1U << TIM_CCMR1_OC2PE_Pos) /*!< 0x00000800 */
+#define TIM_CCMR1_OC2PE TIM_CCMR1_OC2PE_Msk /*!<Output Compare 2 Preload enable */
+
+#define TIM_CCMR1_OC2M_Pos (12U)
+#define TIM_CCMR1_OC2M_Msk (0x7U << TIM_CCMR1_OC2M_Pos) /*!< 0x00007000 */
+#define TIM_CCMR1_OC2M TIM_CCMR1_OC2M_Msk /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
+#define TIM_CCMR1_OC2M_0 (0x1U << TIM_CCMR1_OC2M_Pos) /*!< 0x00001000 */
+#define TIM_CCMR1_OC2M_1 (0x2U << TIM_CCMR1_OC2M_Pos) /*!< 0x00002000 */
+#define TIM_CCMR1_OC2M_2 (0x4U << TIM_CCMR1_OC2M_Pos) /*!< 0x00004000 */
+
+#define TIM_CCMR1_OC2CE_Pos (15U)
+#define TIM_CCMR1_OC2CE_Msk (0x1U << TIM_CCMR1_OC2CE_Pos) /*!< 0x00008000 */
+#define TIM_CCMR1_OC2CE TIM_CCMR1_OC2CE_Msk /*!<Output Compare 2 Clear Enable */
+
+/*---------------------------------------------------------------------------*/
+
+#define TIM_CCMR1_IC1PSC_Pos (2U)
+#define TIM_CCMR1_IC1PSC_Msk (0x3U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x0000000C */
+#define TIM_CCMR1_IC1PSC TIM_CCMR1_IC1PSC_Msk /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
+#define TIM_CCMR1_IC1PSC_0 (0x1U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x00000004 */
+#define TIM_CCMR1_IC1PSC_1 (0x2U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x00000008 */
+
+#define TIM_CCMR1_IC1F_Pos (4U)
+#define TIM_CCMR1_IC1F_Msk (0xFU << TIM_CCMR1_IC1F_Pos) /*!< 0x000000F0 */
+#define TIM_CCMR1_IC1F TIM_CCMR1_IC1F_Msk /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
+#define TIM_CCMR1_IC1F_0 (0x1U << TIM_CCMR1_IC1F_Pos) /*!< 0x00000010 */
+#define TIM_CCMR1_IC1F_1 (0x2U << TIM_CCMR1_IC1F_Pos) /*!< 0x00000020 */
+#define TIM_CCMR1_IC1F_2 (0x4U << TIM_CCMR1_IC1F_Pos) /*!< 0x00000040 */
+#define TIM_CCMR1_IC1F_3 (0x8U << TIM_CCMR1_IC1F_Pos) /*!< 0x00000080 */
+
+#define TIM_CCMR1_IC2PSC_Pos (10U)
+#define TIM_CCMR1_IC2PSC_Msk (0x3U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000C00 */
+#define TIM_CCMR1_IC2PSC TIM_CCMR1_IC2PSC_Msk /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
+#define TIM_CCMR1_IC2PSC_0 (0x1U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000400 */
+#define TIM_CCMR1_IC2PSC_1 (0x2U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000800 */
+
+#define TIM_CCMR1_IC2F_Pos (12U)
+#define TIM_CCMR1_IC2F_Msk (0xFU << TIM_CCMR1_IC2F_Pos) /*!< 0x0000F000 */
+#define TIM_CCMR1_IC2F TIM_CCMR1_IC2F_Msk /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
+#define TIM_CCMR1_IC2F_0 (0x1U << TIM_CCMR1_IC2F_Pos) /*!< 0x00001000 */
+#define TIM_CCMR1_IC2F_1 (0x2U << TIM_CCMR1_IC2F_Pos) /*!< 0x00002000 */
+#define TIM_CCMR1_IC2F_2 (0x4U << TIM_CCMR1_IC2F_Pos) /*!< 0x00004000 */
+#define TIM_CCMR1_IC2F_3 (0x8U << TIM_CCMR1_IC2F_Pos) /*!< 0x00008000 */
+
+/****************** Bit definition for TIM_CCMR2 register ******************/
+#define TIM_CCMR2_CC3S_Pos (0U)
+#define TIM_CCMR2_CC3S_Msk (0x3U << TIM_CCMR2_CC3S_Pos) /*!< 0x00000003 */
+#define TIM_CCMR2_CC3S TIM_CCMR2_CC3S_Msk /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
+#define TIM_CCMR2_CC3S_0 (0x1U << TIM_CCMR2_CC3S_Pos) /*!< 0x00000001 */
+#define TIM_CCMR2_CC3S_1 (0x2U << TIM_CCMR2_CC3S_Pos) /*!< 0x00000002 */
+
+#define TIM_CCMR2_OC3FE_Pos (2U)
+#define TIM_CCMR2_OC3FE_Msk (0x1U << TIM_CCMR2_OC3FE_Pos) /*!< 0x00000004 */
+#define TIM_CCMR2_OC3FE TIM_CCMR2_OC3FE_Msk /*!<Output Compare 3 Fast enable */
+#define TIM_CCMR2_OC3PE_Pos (3U)
+#define TIM_CCMR2_OC3PE_Msk (0x1U << TIM_CCMR2_OC3PE_Pos) /*!< 0x00000008 */
+#define TIM_CCMR2_OC3PE TIM_CCMR2_OC3PE_Msk /*!<Output Compare 3 Preload enable */
+
+#define TIM_CCMR2_OC3M_Pos (4U)
+#define TIM_CCMR2_OC3M_Msk (0x7U << TIM_CCMR2_OC3M_Pos) /*!< 0x00000070 */
+#define TIM_CCMR2_OC3M TIM_CCMR2_OC3M_Msk /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
+#define TIM_CCMR2_OC3M_0 (0x1U << TIM_CCMR2_OC3M_Pos) /*!< 0x00000010 */
+#define TIM_CCMR2_OC3M_1 (0x2U << TIM_CCMR2_OC3M_Pos) /*!< 0x00000020 */
+#define TIM_CCMR2_OC3M_2 (0x4U << TIM_CCMR2_OC3M_Pos) /*!< 0x00000040 */
+
+#define TIM_CCMR2_OC3CE_Pos (7U)
+#define TIM_CCMR2_OC3CE_Msk (0x1U << TIM_CCMR2_OC3CE_Pos) /*!< 0x00000080 */
+#define TIM_CCMR2_OC3CE TIM_CCMR2_OC3CE_Msk /*!<Output Compare 3 Clear Enable */
+
+#define TIM_CCMR2_CC4S_Pos (8U)
+#define TIM_CCMR2_CC4S_Msk (0x3U << TIM_CCMR2_CC4S_Pos) /*!< 0x00000300 */
+#define TIM_CCMR2_CC4S TIM_CCMR2_CC4S_Msk /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
+#define TIM_CCMR2_CC4S_0 (0x1U << TIM_CCMR2_CC4S_Pos) /*!< 0x00000100 */
+#define TIM_CCMR2_CC4S_1 (0x2U << TIM_CCMR2_CC4S_Pos) /*!< 0x00000200 */
+
+#define TIM_CCMR2_OC4FE_Pos (10U)
+#define TIM_CCMR2_OC4FE_Msk (0x1U << TIM_CCMR2_OC4FE_Pos) /*!< 0x00000400 */
+#define TIM_CCMR2_OC4FE TIM_CCMR2_OC4FE_Msk /*!<Output Compare 4 Fast enable */
+#define TIM_CCMR2_OC4PE_Pos (11U)
+#define TIM_CCMR2_OC4PE_Msk (0x1U << TIM_CCMR2_OC4PE_Pos) /*!< 0x00000800 */
+#define TIM_CCMR2_OC4PE TIM_CCMR2_OC4PE_Msk /*!<Output Compare 4 Preload enable */
+
+#define TIM_CCMR2_OC4M_Pos (12U)
+#define TIM_CCMR2_OC4M_Msk (0x7U << TIM_CCMR2_OC4M_Pos) /*!< 0x00007000 */
+#define TIM_CCMR2_OC4M TIM_CCMR2_OC4M_Msk /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
+#define TIM_CCMR2_OC4M_0 (0x1U << TIM_CCMR2_OC4M_Pos) /*!< 0x00001000 */
+#define TIM_CCMR2_OC4M_1 (0x2U << TIM_CCMR2_OC4M_Pos) /*!< 0x00002000 */
+#define TIM_CCMR2_OC4M_2 (0x4U << TIM_CCMR2_OC4M_Pos) /*!< 0x00004000 */
+
+#define TIM_CCMR2_OC4CE_Pos (15U)
+#define TIM_CCMR2_OC4CE_Msk (0x1U << TIM_CCMR2_OC4CE_Pos) /*!< 0x00008000 */
+#define TIM_CCMR2_OC4CE TIM_CCMR2_OC4CE_Msk /*!<Output Compare 4 Clear Enable */
+
+/*---------------------------------------------------------------------------*/
+
+#define TIM_CCMR2_IC3PSC_Pos (2U)
+#define TIM_CCMR2_IC3PSC_Msk (0x3U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x0000000C */
+#define TIM_CCMR2_IC3PSC TIM_CCMR2_IC3PSC_Msk /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
+#define TIM_CCMR2_IC3PSC_0 (0x1U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x00000004 */
+#define TIM_CCMR2_IC3PSC_1 (0x2U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x00000008 */
+
+#define TIM_CCMR2_IC3F_Pos (4U)
+#define TIM_CCMR2_IC3F_Msk (0xFU << TIM_CCMR2_IC3F_Pos) /*!< 0x000000F0 */
+#define TIM_CCMR2_IC3F TIM_CCMR2_IC3F_Msk /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
+#define TIM_CCMR2_IC3F_0 (0x1U << TIM_CCMR2_IC3F_Pos) /*!< 0x00000010 */
+#define TIM_CCMR2_IC3F_1 (0x2U << TIM_CCMR2_IC3F_Pos) /*!< 0x00000020 */
+#define TIM_CCMR2_IC3F_2 (0x4U << TIM_CCMR2_IC3F_Pos) /*!< 0x00000040 */
+#define TIM_CCMR2_IC3F_3 (0x8U << TIM_CCMR2_IC3F_Pos) /*!< 0x00000080 */
+
+#define TIM_CCMR2_IC4PSC_Pos (10U)
+#define TIM_CCMR2_IC4PSC_Msk (0x3U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000C00 */
+#define TIM_CCMR2_IC4PSC TIM_CCMR2_IC4PSC_Msk /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
+#define TIM_CCMR2_IC4PSC_0 (0x1U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000400 */
+#define TIM_CCMR2_IC4PSC_1 (0x2U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000800 */
+
+#define TIM_CCMR2_IC4F_Pos (12U)
+#define TIM_CCMR2_IC4F_Msk (0xFU << TIM_CCMR2_IC4F_Pos) /*!< 0x0000F000 */
+#define TIM_CCMR2_IC4F TIM_CCMR2_IC4F_Msk /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
+#define TIM_CCMR2_IC4F_0 (0x1U << TIM_CCMR2_IC4F_Pos) /*!< 0x00001000 */
+#define TIM_CCMR2_IC4F_1 (0x2U << TIM_CCMR2_IC4F_Pos) /*!< 0x00002000 */
+#define TIM_CCMR2_IC4F_2 (0x4U << TIM_CCMR2_IC4F_Pos) /*!< 0x00004000 */
+#define TIM_CCMR2_IC4F_3 (0x8U << TIM_CCMR2_IC4F_Pos) /*!< 0x00008000 */
+
+/******************* Bit definition for TIM_CCER register ******************/
+#define TIM_CCER_CC1E_Pos (0U)
+#define TIM_CCER_CC1E_Msk (0x1U << TIM_CCER_CC1E_Pos) /*!< 0x00000001 */
+#define TIM_CCER_CC1E TIM_CCER_CC1E_Msk /*!<Capture/Compare 1 output enable */
+#define TIM_CCER_CC1P_Pos (1U)
+#define TIM_CCER_CC1P_Msk (0x1U << TIM_CCER_CC1P_Pos) /*!< 0x00000002 */
+#define TIM_CCER_CC1P TIM_CCER_CC1P_Msk /*!<Capture/Compare 1 output Polarity */
+#define TIM_CCER_CC1NE_Pos (2U)
+#define TIM_CCER_CC1NE_Msk (0x1U << TIM_CCER_CC1NE_Pos) /*!< 0x00000004 */
+#define TIM_CCER_CC1NE TIM_CCER_CC1NE_Msk /*!<Capture/Compare 1 Complementary output enable */
+#define TIM_CCER_CC1NP_Pos (3U)
+#define TIM_CCER_CC1NP_Msk (0x1U << TIM_CCER_CC1NP_Pos) /*!< 0x00000008 */
+#define TIM_CCER_CC1NP TIM_CCER_CC1NP_Msk /*!<Capture/Compare 1 Complementary output Polarity */
+#define TIM_CCER_CC2E_Pos (4U)
+#define TIM_CCER_CC2E_Msk (0x1U << TIM_CCER_CC2E_Pos) /*!< 0x00000010 */
+#define TIM_CCER_CC2E TIM_CCER_CC2E_Msk /*!<Capture/Compare 2 output enable */
+#define TIM_CCER_CC2P_Pos (5U)
+#define TIM_CCER_CC2P_Msk (0x1U << TIM_CCER_CC2P_Pos) /*!< 0x00000020 */
+#define TIM_CCER_CC2P TIM_CCER_CC2P_Msk /*!<Capture/Compare 2 output Polarity */
+#define TIM_CCER_CC2NE_Pos (6U)
+#define TIM_CCER_CC2NE_Msk (0x1U << TIM_CCER_CC2NE_Pos) /*!< 0x00000040 */
+#define TIM_CCER_CC2NE TIM_CCER_CC2NE_Msk /*!<Capture/Compare 2 Complementary output enable */
+#define TIM_CCER_CC2NP_Pos (7U)
+#define TIM_CCER_CC2NP_Msk (0x1U << TIM_CCER_CC2NP_Pos) /*!< 0x00000080 */
+#define TIM_CCER_CC2NP TIM_CCER_CC2NP_Msk /*!<Capture/Compare 2 Complementary output Polarity */
+#define TIM_CCER_CC3E_Pos (8U)
+#define TIM_CCER_CC3E_Msk (0x1U << TIM_CCER_CC3E_Pos) /*!< 0x00000100 */
+#define TIM_CCER_CC3E TIM_CCER_CC3E_Msk /*!<Capture/Compare 3 output enable */
+#define TIM_CCER_CC3P_Pos (9U)
+#define TIM_CCER_CC3P_Msk (0x1U << TIM_CCER_CC3P_Pos) /*!< 0x00000200 */
+#define TIM_CCER_CC3P TIM_CCER_CC3P_Msk /*!<Capture/Compare 3 output Polarity */
+#define TIM_CCER_CC3NE_Pos (10U)
+#define TIM_CCER_CC3NE_Msk (0x1U << TIM_CCER_CC3NE_Pos) /*!< 0x00000400 */
+#define TIM_CCER_CC3NE TIM_CCER_CC3NE_Msk /*!<Capture/Compare 3 Complementary output enable */
+#define TIM_CCER_CC3NP_Pos (11U)
+#define TIM_CCER_CC3NP_Msk (0x1U << TIM_CCER_CC3NP_Pos) /*!< 0x00000800 */
+#define TIM_CCER_CC3NP TIM_CCER_CC3NP_Msk /*!<Capture/Compare 3 Complementary output Polarity */
+#define TIM_CCER_CC4E_Pos (12U)
+#define TIM_CCER_CC4E_Msk (0x1U << TIM_CCER_CC4E_Pos) /*!< 0x00001000 */
+#define TIM_CCER_CC4E TIM_CCER_CC4E_Msk /*!<Capture/Compare 4 output enable */
+#define TIM_CCER_CC4P_Pos (13U)
+#define TIM_CCER_CC4P_Msk (0x1U << TIM_CCER_CC4P_Pos) /*!< 0x00002000 */
+#define TIM_CCER_CC4P TIM_CCER_CC4P_Msk /*!<Capture/Compare 4 output Polarity */
+#define TIM_CCER_CC4NP_Pos (15U)
+#define TIM_CCER_CC4NP_Msk (0x1U << TIM_CCER_CC4NP_Pos) /*!< 0x00008000 */
+#define TIM_CCER_CC4NP TIM_CCER_CC4NP_Msk /*!<Capture/Compare 4 Complementary output Polarity */
+
+/******************* Bit definition for TIM_CNT register *******************/
+#define TIM_CNT_CNT_Pos (0U)
+#define TIM_CNT_CNT_Msk (0xFFFFFFFFU << TIM_CNT_CNT_Pos) /*!< 0xFFFFFFFF */
+#define TIM_CNT_CNT TIM_CNT_CNT_Msk /*!<Counter Value */
+
+/******************* Bit definition for TIM_PSC register *******************/
+#define TIM_PSC_PSC_Pos (0U)
+#define TIM_PSC_PSC_Msk (0xFFFFU << TIM_PSC_PSC_Pos) /*!< 0x0000FFFF */
+#define TIM_PSC_PSC TIM_PSC_PSC_Msk /*!<Prescaler Value */
+
+/******************* Bit definition for TIM_ARR register *******************/
+#define TIM_ARR_ARR_Pos (0U)
+#define TIM_ARR_ARR_Msk (0xFFFFFFFFU << TIM_ARR_ARR_Pos) /*!< 0xFFFFFFFF */
+#define TIM_ARR_ARR TIM_ARR_ARR_Msk /*!<actual auto-reload Value */
+
+/******************* Bit definition for TIM_RCR register *******************/
+#define TIM_RCR_REP_Pos (0U)
+#define TIM_RCR_REP_Msk (0xFFU << TIM_RCR_REP_Pos) /*!< 0x000000FF */
+#define TIM_RCR_REP TIM_RCR_REP_Msk /*!<Repetition Counter Value */
+
+/******************* Bit definition for TIM_CCR1 register ******************/
+#define TIM_CCR1_CCR1_Pos (0U)
+#define TIM_CCR1_CCR1_Msk (0xFFFFU << TIM_CCR1_CCR1_Pos) /*!< 0x0000FFFF */
+#define TIM_CCR1_CCR1 TIM_CCR1_CCR1_Msk /*!<Capture/Compare 1 Value */
+
+/******************* Bit definition for TIM_CCR2 register ******************/
+#define TIM_CCR2_CCR2_Pos (0U)
+#define TIM_CCR2_CCR2_Msk (0xFFFFU << TIM_CCR2_CCR2_Pos) /*!< 0x0000FFFF */
+#define TIM_CCR2_CCR2 TIM_CCR2_CCR2_Msk /*!<Capture/Compare 2 Value */
+
+/******************* Bit definition for TIM_CCR3 register ******************/
+#define TIM_CCR3_CCR3_Pos (0U)
+#define TIM_CCR3_CCR3_Msk (0xFFFFU << TIM_CCR3_CCR3_Pos) /*!< 0x0000FFFF */
+#define TIM_CCR3_CCR3 TIM_CCR3_CCR3_Msk /*!<Capture/Compare 3 Value */
+
+/******************* Bit definition for TIM_CCR4 register ******************/
+#define TIM_CCR4_CCR4_Pos (0U)
+#define TIM_CCR4_CCR4_Msk (0xFFFFU << TIM_CCR4_CCR4_Pos) /*!< 0x0000FFFF */
+#define TIM_CCR4_CCR4 TIM_CCR4_CCR4_Msk /*!<Capture/Compare 4 Value */
+
+/******************* Bit definition for TIM_BDTR register ******************/
+#define TIM_BDTR_DTG_Pos (0U)
+#define TIM_BDTR_DTG_Msk (0xFFU << TIM_BDTR_DTG_Pos) /*!< 0x000000FF */
+#define TIM_BDTR_DTG TIM_BDTR_DTG_Msk /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
+#define TIM_BDTR_DTG_0 (0x01U << TIM_BDTR_DTG_Pos) /*!< 0x00000001 */
+#define TIM_BDTR_DTG_1 (0x02U << TIM_BDTR_DTG_Pos) /*!< 0x00000002 */
+#define TIM_BDTR_DTG_2 (0x04U << TIM_BDTR_DTG_Pos) /*!< 0x00000004 */
+#define TIM_BDTR_DTG_3 (0x08U << TIM_BDTR_DTG_Pos) /*!< 0x00000008 */
+#define TIM_BDTR_DTG_4 (0x10U << TIM_BDTR_DTG_Pos) /*!< 0x00000010 */
+#define TIM_BDTR_DTG_5 (0x20U << TIM_BDTR_DTG_Pos) /*!< 0x00000020 */
+#define TIM_BDTR_DTG_6 (0x40U << TIM_BDTR_DTG_Pos) /*!< 0x00000040 */
+#define TIM_BDTR_DTG_7 (0x80U << TIM_BDTR_DTG_Pos) /*!< 0x00000080 */
+
+#define TIM_BDTR_LOCK_Pos (8U)
+#define TIM_BDTR_LOCK_Msk (0x3U << TIM_BDTR_LOCK_Pos) /*!< 0x00000300 */
+#define TIM_BDTR_LOCK TIM_BDTR_LOCK_Msk /*!<LOCK[1:0] bits (Lock Configuration) */
+#define TIM_BDTR_LOCK_0 (0x1U << TIM_BDTR_LOCK_Pos) /*!< 0x00000100 */
+#define TIM_BDTR_LOCK_1 (0x2U << TIM_BDTR_LOCK_Pos) /*!< 0x00000200 */
+
+#define TIM_BDTR_OSSI_Pos (10U)
+#define TIM_BDTR_OSSI_Msk (0x1U << TIM_BDTR_OSSI_Pos) /*!< 0x00000400 */
+#define TIM_BDTR_OSSI TIM_BDTR_OSSI_Msk /*!<Off-State Selection for Idle mode */
+#define TIM_BDTR_OSSR_Pos (11U)
+#define TIM_BDTR_OSSR_Msk (0x1U << TIM_BDTR_OSSR_Pos) /*!< 0x00000800 */
+#define TIM_BDTR_OSSR TIM_BDTR_OSSR_Msk /*!<Off-State Selection for Run mode */
+#define TIM_BDTR_BKE_Pos (12U)
+#define TIM_BDTR_BKE_Msk (0x1U << TIM_BDTR_BKE_Pos) /*!< 0x00001000 */
+#define TIM_BDTR_BKE TIM_BDTR_BKE_Msk /*!<Break enable */
+#define TIM_BDTR_BKP_Pos (13U)
+#define TIM_BDTR_BKP_Msk (0x1U << TIM_BDTR_BKP_Pos) /*!< 0x00002000 */
+#define TIM_BDTR_BKP TIM_BDTR_BKP_Msk /*!<Break Polarity */
+#define TIM_BDTR_AOE_Pos (14U)
+#define TIM_BDTR_AOE_Msk (0x1U << TIM_BDTR_AOE_Pos) /*!< 0x00004000 */
+#define TIM_BDTR_AOE TIM_BDTR_AOE_Msk /*!<Automatic Output enable */
+#define TIM_BDTR_MOE_Pos (15U)
+#define TIM_BDTR_MOE_Msk (0x1U << TIM_BDTR_MOE_Pos) /*!< 0x00008000 */
+#define TIM_BDTR_MOE TIM_BDTR_MOE_Msk /*!<Main Output enable */
+
+/******************* Bit definition for TIM_DCR register *******************/
+#define TIM_DCR_DBA_Pos (0U)
+#define TIM_DCR_DBA_Msk (0x1FU << TIM_DCR_DBA_Pos) /*!< 0x0000001F */
+#define TIM_DCR_DBA TIM_DCR_DBA_Msk /*!<DBA[4:0] bits (DMA Base Address) */
+#define TIM_DCR_DBA_0 (0x01U << TIM_DCR_DBA_Pos) /*!< 0x00000001 */
+#define TIM_DCR_DBA_1 (0x02U << TIM_DCR_DBA_Pos) /*!< 0x00000002 */
+#define TIM_DCR_DBA_2 (0x04U << TIM_DCR_DBA_Pos) /*!< 0x00000004 */
+#define TIM_DCR_DBA_3 (0x08U << TIM_DCR_DBA_Pos) /*!< 0x00000008 */
+#define TIM_DCR_DBA_4 (0x10U << TIM_DCR_DBA_Pos) /*!< 0x00000010 */
+
+#define TIM_DCR_DBL_Pos (8U)
+#define TIM_DCR_DBL_Msk (0x1FU << TIM_DCR_DBL_Pos) /*!< 0x00001F00 */
+#define TIM_DCR_DBL TIM_DCR_DBL_Msk /*!<DBL[4:0] bits (DMA Burst Length) */
+#define TIM_DCR_DBL_0 (0x01U << TIM_DCR_DBL_Pos) /*!< 0x00000100 */
+#define TIM_DCR_DBL_1 (0x02U << TIM_DCR_DBL_Pos) /*!< 0x00000200 */
+#define TIM_DCR_DBL_2 (0x04U << TIM_DCR_DBL_Pos) /*!< 0x00000400 */
+#define TIM_DCR_DBL_3 (0x08U << TIM_DCR_DBL_Pos) /*!< 0x00000800 */
+#define TIM_DCR_DBL_4 (0x10U << TIM_DCR_DBL_Pos) /*!< 0x00001000 */
+
+/******************* Bit definition for TIM_DMAR register ******************/
+#define TIM_DMAR_DMAB_Pos (0U)
+#define TIM_DMAR_DMAB_Msk (0xFFFFU << TIM_DMAR_DMAB_Pos) /*!< 0x0000FFFF */
+#define TIM_DMAR_DMAB TIM_DMAR_DMAB_Msk /*!<DMA register for burst accesses */
+
+/******************* Bit definition for TIM_OR register ********************/
+
+/******************************************************************************/
+/* */
+/* Real-Time Clock */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for RTC_CRH register ********************/
+#define RTC_CRH_SECIE_Pos (0U)
+#define RTC_CRH_SECIE_Msk (0x1U << RTC_CRH_SECIE_Pos) /*!< 0x00000001 */
+#define RTC_CRH_SECIE RTC_CRH_SECIE_Msk /*!< Second Interrupt Enable */
+#define RTC_CRH_ALRIE_Pos (1U)
+#define RTC_CRH_ALRIE_Msk (0x1U << RTC_CRH_ALRIE_Pos) /*!< 0x00000002 */
+#define RTC_CRH_ALRIE RTC_CRH_ALRIE_Msk /*!< Alarm Interrupt Enable */
+#define RTC_CRH_OWIE_Pos (2U)
+#define RTC_CRH_OWIE_Msk (0x1U << RTC_CRH_OWIE_Pos) /*!< 0x00000004 */
+#define RTC_CRH_OWIE RTC_CRH_OWIE_Msk /*!< OverfloW Interrupt Enable */
+
+/******************* Bit definition for RTC_CRL register ********************/
+#define RTC_CRL_SECF_Pos (0U)
+#define RTC_CRL_SECF_Msk (0x1U << RTC_CRL_SECF_Pos) /*!< 0x00000001 */
+#define RTC_CRL_SECF RTC_CRL_SECF_Msk /*!< Second Flag */
+#define RTC_CRL_ALRF_Pos (1U)
+#define RTC_CRL_ALRF_Msk (0x1U << RTC_CRL_ALRF_Pos) /*!< 0x00000002 */
+#define RTC_CRL_ALRF RTC_CRL_ALRF_Msk /*!< Alarm Flag */
+#define RTC_CRL_OWF_Pos (2U)
+#define RTC_CRL_OWF_Msk (0x1U << RTC_CRL_OWF_Pos) /*!< 0x00000004 */
+#define RTC_CRL_OWF RTC_CRL_OWF_Msk /*!< OverfloW Flag */
+#define RTC_CRL_RSF_Pos (3U)
+#define RTC_CRL_RSF_Msk (0x1U << RTC_CRL_RSF_Pos) /*!< 0x00000008 */
+#define RTC_CRL_RSF RTC_CRL_RSF_Msk /*!< Registers Synchronized Flag */
+#define RTC_CRL_CNF_Pos (4U)
+#define RTC_CRL_CNF_Msk (0x1U << RTC_CRL_CNF_Pos) /*!< 0x00000010 */
+#define RTC_CRL_CNF RTC_CRL_CNF_Msk /*!< Configuration Flag */
+#define RTC_CRL_RTOFF_Pos (5U)
+#define RTC_CRL_RTOFF_Msk (0x1U << RTC_CRL_RTOFF_Pos) /*!< 0x00000020 */
+#define RTC_CRL_RTOFF RTC_CRL_RTOFF_Msk /*!< RTC operation OFF */
+
+/******************* Bit definition for RTC_PRLH register *******************/
+#define RTC_PRLH_PRL_Pos (0U)
+#define RTC_PRLH_PRL_Msk (0xFU << RTC_PRLH_PRL_Pos) /*!< 0x0000000F */
+#define RTC_PRLH_PRL RTC_PRLH_PRL_Msk /*!< RTC Prescaler Reload Value High */
+
+/******************* Bit definition for RTC_PRLL register *******************/
+#define RTC_PRLL_PRL_Pos (0U)
+#define RTC_PRLL_PRL_Msk (0xFFFFU << RTC_PRLL_PRL_Pos) /*!< 0x0000FFFF */
+#define RTC_PRLL_PRL RTC_PRLL_PRL_Msk /*!< RTC Prescaler Reload Value Low */
+
+/******************* Bit definition for RTC_DIVH register *******************/
+#define RTC_DIVH_RTC_DIV_Pos (0U)
+#define RTC_DIVH_RTC_DIV_Msk (0xFU << RTC_DIVH_RTC_DIV_Pos) /*!< 0x0000000F */
+#define RTC_DIVH_RTC_DIV RTC_DIVH_RTC_DIV_Msk /*!< RTC Clock Divider High */
+
+/******************* Bit definition for RTC_DIVL register *******************/
+#define RTC_DIVL_RTC_DIV_Pos (0U)
+#define RTC_DIVL_RTC_DIV_Msk (0xFFFFU << RTC_DIVL_RTC_DIV_Pos) /*!< 0x0000FFFF */
+#define RTC_DIVL_RTC_DIV RTC_DIVL_RTC_DIV_Msk /*!< RTC Clock Divider Low */
+
+/******************* Bit definition for RTC_CNTH register *******************/
+#define RTC_CNTH_RTC_CNT_Pos (0U)
+#define RTC_CNTH_RTC_CNT_Msk (0xFFFFU << RTC_CNTH_RTC_CNT_Pos) /*!< 0x0000FFFF */
+#define RTC_CNTH_RTC_CNT RTC_CNTH_RTC_CNT_Msk /*!< RTC Counter High */
+
+/******************* Bit definition for RTC_CNTL register *******************/
+#define RTC_CNTL_RTC_CNT_Pos (0U)
+#define RTC_CNTL_RTC_CNT_Msk (0xFFFFU << RTC_CNTL_RTC_CNT_Pos) /*!< 0x0000FFFF */
+#define RTC_CNTL_RTC_CNT RTC_CNTL_RTC_CNT_Msk /*!< RTC Counter Low */
+
+/******************* Bit definition for RTC_ALRH register *******************/
+#define RTC_ALRH_RTC_ALR_Pos (0U)
+#define RTC_ALRH_RTC_ALR_Msk (0xFFFFU << RTC_ALRH_RTC_ALR_Pos) /*!< 0x0000FFFF */
+#define RTC_ALRH_RTC_ALR RTC_ALRH_RTC_ALR_Msk /*!< RTC Alarm High */
+
+/******************* Bit definition for RTC_ALRL register *******************/
+#define RTC_ALRL_RTC_ALR_Pos (0U)
+#define RTC_ALRL_RTC_ALR_Msk (0xFFFFU << RTC_ALRL_RTC_ALR_Pos) /*!< 0x0000FFFF */
+#define RTC_ALRL_RTC_ALR RTC_ALRL_RTC_ALR_Msk /*!< RTC Alarm Low */
+
+/******************************************************************************/
+/* */
+/* Independent WATCHDOG (IWDG) */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for IWDG_KR register ********************/
+#define IWDG_KR_KEY_Pos (0U)
+#define IWDG_KR_KEY_Msk (0xFFFFU << IWDG_KR_KEY_Pos) /*!< 0x0000FFFF */
+#define IWDG_KR_KEY IWDG_KR_KEY_Msk /*!< Key value (write only, read 0000h) */
+
+/******************* Bit definition for IWDG_PR register ********************/
+#define IWDG_PR_PR_Pos (0U)
+#define IWDG_PR_PR_Msk (0x7U << IWDG_PR_PR_Pos) /*!< 0x00000007 */
+#define IWDG_PR_PR IWDG_PR_PR_Msk /*!< PR[2:0] (Prescaler divider) */
+#define IWDG_PR_PR_0 (0x1U << IWDG_PR_PR_Pos) /*!< 0x00000001 */
+#define IWDG_PR_PR_1 (0x2U << IWDG_PR_PR_Pos) /*!< 0x00000002 */
+#define IWDG_PR_PR_2 (0x4U << IWDG_PR_PR_Pos) /*!< 0x00000004 */
+
+/******************* Bit definition for IWDG_RLR register *******************/
+#define IWDG_RLR_RL_Pos (0U)
+#define IWDG_RLR_RL_Msk (0xFFFU << IWDG_RLR_RL_Pos) /*!< 0x00000FFF */
+#define IWDG_RLR_RL IWDG_RLR_RL_Msk /*!< Watchdog counter reload value */
+
+/******************* Bit definition for IWDG_SR register ********************/
+#define IWDG_SR_PVU_Pos (0U)
+#define IWDG_SR_PVU_Msk (0x1U << IWDG_SR_PVU_Pos) /*!< 0x00000001 */
+#define IWDG_SR_PVU IWDG_SR_PVU_Msk /*!< Watchdog prescaler value update */
+#define IWDG_SR_RVU_Pos (1U)
+#define IWDG_SR_RVU_Msk (0x1U << IWDG_SR_RVU_Pos) /*!< 0x00000002 */
+#define IWDG_SR_RVU IWDG_SR_RVU_Msk /*!< Watchdog counter reload value update */
+
+/******************************************************************************/
+/* */
+/* Window WATCHDOG (WWDG) */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for WWDG_CR register ********************/
+#define WWDG_CR_T_Pos (0U)
+#define WWDG_CR_T_Msk (0x7FU << WWDG_CR_T_Pos) /*!< 0x0000007F */
+#define WWDG_CR_T WWDG_CR_T_Msk /*!< T[6:0] bits (7-Bit counter (MSB to LSB)) */
+#define WWDG_CR_T_0 (0x01U << WWDG_CR_T_Pos) /*!< 0x00000001 */
+#define WWDG_CR_T_1 (0x02U << WWDG_CR_T_Pos) /*!< 0x00000002 */
+#define WWDG_CR_T_2 (0x04U << WWDG_CR_T_Pos) /*!< 0x00000004 */
+#define WWDG_CR_T_3 (0x08U << WWDG_CR_T_Pos) /*!< 0x00000008 */
+#define WWDG_CR_T_4 (0x10U << WWDG_CR_T_Pos) /*!< 0x00000010 */
+#define WWDG_CR_T_5 (0x20U << WWDG_CR_T_Pos) /*!< 0x00000020 */
+#define WWDG_CR_T_6 (0x40U << WWDG_CR_T_Pos) /*!< 0x00000040 */
+
+/* Legacy defines */
+#define WWDG_CR_T0 WWDG_CR_T_0
+#define WWDG_CR_T1 WWDG_CR_T_1
+#define WWDG_CR_T2 WWDG_CR_T_2
+#define WWDG_CR_T3 WWDG_CR_T_3
+#define WWDG_CR_T4 WWDG_CR_T_4
+#define WWDG_CR_T5 WWDG_CR_T_5
+#define WWDG_CR_T6 WWDG_CR_T_6
+
+#define WWDG_CR_WDGA_Pos (7U)
+#define WWDG_CR_WDGA_Msk (0x1U << WWDG_CR_WDGA_Pos) /*!< 0x00000080 */
+#define WWDG_CR_WDGA WWDG_CR_WDGA_Msk /*!< Activation bit */
+
+/******************* Bit definition for WWDG_CFR register *******************/
+#define WWDG_CFR_W_Pos (0U)
+#define WWDG_CFR_W_Msk (0x7FU << WWDG_CFR_W_Pos) /*!< 0x0000007F */
+#define WWDG_CFR_W WWDG_CFR_W_Msk /*!< W[6:0] bits (7-bit window value) */
+#define WWDG_CFR_W_0 (0x01U << WWDG_CFR_W_Pos) /*!< 0x00000001 */
+#define WWDG_CFR_W_1 (0x02U << WWDG_CFR_W_Pos) /*!< 0x00000002 */
+#define WWDG_CFR_W_2 (0x04U << WWDG_CFR_W_Pos) /*!< 0x00000004 */
+#define WWDG_CFR_W_3 (0x08U << WWDG_CFR_W_Pos) /*!< 0x00000008 */
+#define WWDG_CFR_W_4 (0x10U << WWDG_CFR_W_Pos) /*!< 0x00000010 */
+#define WWDG_CFR_W_5 (0x20U << WWDG_CFR_W_Pos) /*!< 0x00000020 */
+#define WWDG_CFR_W_6 (0x40U << WWDG_CFR_W_Pos) /*!< 0x00000040 */
+
+/* Legacy defines */
+#define WWDG_CFR_W0 WWDG_CFR_W_0
+#define WWDG_CFR_W1 WWDG_CFR_W_1
+#define WWDG_CFR_W2 WWDG_CFR_W_2
+#define WWDG_CFR_W3 WWDG_CFR_W_3
+#define WWDG_CFR_W4 WWDG_CFR_W_4
+#define WWDG_CFR_W5 WWDG_CFR_W_5
+#define WWDG_CFR_W6 WWDG_CFR_W_6
+
+#define WWDG_CFR_WDGTB_Pos (7U)
+#define WWDG_CFR_WDGTB_Msk (0x3U << WWDG_CFR_WDGTB_Pos) /*!< 0x00000180 */
+#define WWDG_CFR_WDGTB WWDG_CFR_WDGTB_Msk /*!< WDGTB[1:0] bits (Timer Base) */
+#define WWDG_CFR_WDGTB_0 (0x1U << WWDG_CFR_WDGTB_Pos) /*!< 0x00000080 */
+#define WWDG_CFR_WDGTB_1 (0x2U << WWDG_CFR_WDGTB_Pos) /*!< 0x00000100 */
+
+/* Legacy defines */
+#define WWDG_CFR_WDGTB0 WWDG_CFR_WDGTB_0
+#define WWDG_CFR_WDGTB1 WWDG_CFR_WDGTB_1
+
+#define WWDG_CFR_EWI_Pos (9U)
+#define WWDG_CFR_EWI_Msk (0x1U << WWDG_CFR_EWI_Pos) /*!< 0x00000200 */
+#define WWDG_CFR_EWI WWDG_CFR_EWI_Msk /*!< Early Wakeup Interrupt */
+
+/******************* Bit definition for WWDG_SR register ********************/
+#define WWDG_SR_EWIF_Pos (0U)
+#define WWDG_SR_EWIF_Msk (0x1U << WWDG_SR_EWIF_Pos) /*!< 0x00000001 */
+#define WWDG_SR_EWIF WWDG_SR_EWIF_Msk /*!< Early Wakeup Interrupt Flag */
+
+
+/******************************************************************************/
+/* */
+/* SD host Interface */
+/* */
+/******************************************************************************/
+
+/****************** Bit definition for SDIO_POWER register ******************/
+#define SDIO_POWER_PWRCTRL_Pos (0U)
+#define SDIO_POWER_PWRCTRL_Msk (0x3U << SDIO_POWER_PWRCTRL_Pos) /*!< 0x00000003 */
+#define SDIO_POWER_PWRCTRL SDIO_POWER_PWRCTRL_Msk /*!< PWRCTRL[1:0] bits (Power supply control bits) */
+#define SDIO_POWER_PWRCTRL_0 (0x1U << SDIO_POWER_PWRCTRL_Pos) /*!< 0x01 */
+#define SDIO_POWER_PWRCTRL_1 (0x2U << SDIO_POWER_PWRCTRL_Pos) /*!< 0x02 */
+
+/****************** Bit definition for SDIO_CLKCR register ******************/
+#define SDIO_CLKCR_CLKDIV_Pos (0U)
+#define SDIO_CLKCR_CLKDIV_Msk (0xFFU << SDIO_CLKCR_CLKDIV_Pos) /*!< 0x000000FF */
+#define SDIO_CLKCR_CLKDIV SDIO_CLKCR_CLKDIV_Msk /*!< Clock divide factor */
+#define SDIO_CLKCR_CLKEN_Pos (8U)
+#define SDIO_CLKCR_CLKEN_Msk (0x1U << SDIO_CLKCR_CLKEN_Pos) /*!< 0x00000100 */
+#define SDIO_CLKCR_CLKEN SDIO_CLKCR_CLKEN_Msk /*!< Clock enable bit */
+#define SDIO_CLKCR_PWRSAV_Pos (9U)
+#define SDIO_CLKCR_PWRSAV_Msk (0x1U << SDIO_CLKCR_PWRSAV_Pos) /*!< 0x00000200 */
+#define SDIO_CLKCR_PWRSAV SDIO_CLKCR_PWRSAV_Msk /*!< Power saving configuration bit */
+#define SDIO_CLKCR_BYPASS_Pos (10U)
+#define SDIO_CLKCR_BYPASS_Msk (0x1U << SDIO_CLKCR_BYPASS_Pos) /*!< 0x00000400 */
+#define SDIO_CLKCR_BYPASS SDIO_CLKCR_BYPASS_Msk /*!< Clock divider bypass enable bit */
+
+#define SDIO_CLKCR_WIDBUS_Pos (11U)
+#define SDIO_CLKCR_WIDBUS_Msk (0x3U << SDIO_CLKCR_WIDBUS_Pos) /*!< 0x00001800 */
+#define SDIO_CLKCR_WIDBUS SDIO_CLKCR_WIDBUS_Msk /*!< WIDBUS[1:0] bits (Wide bus mode enable bit) */
+#define SDIO_CLKCR_WIDBUS_0 (0x1U << SDIO_CLKCR_WIDBUS_Pos) /*!< 0x0800 */
+#define SDIO_CLKCR_WIDBUS_1 (0x2U << SDIO_CLKCR_WIDBUS_Pos) /*!< 0x1000 */
+
+#define SDIO_CLKCR_NEGEDGE_Pos (13U)
+#define SDIO_CLKCR_NEGEDGE_Msk (0x1U << SDIO_CLKCR_NEGEDGE_Pos) /*!< 0x00002000 */
+#define SDIO_CLKCR_NEGEDGE SDIO_CLKCR_NEGEDGE_Msk /*!< SDIO_CK dephasing selection bit */
+#define SDIO_CLKCR_HWFC_EN_Pos (14U)
+#define SDIO_CLKCR_HWFC_EN_Msk (0x1U << SDIO_CLKCR_HWFC_EN_Pos) /*!< 0x00004000 */
+#define SDIO_CLKCR_HWFC_EN SDIO_CLKCR_HWFC_EN_Msk /*!< HW Flow Control enable */
+
+/******************* Bit definition for SDIO_ARG register *******************/
+#define SDIO_ARG_CMDARG_Pos (0U)
+#define SDIO_ARG_CMDARG_Msk (0xFFFFFFFFU << SDIO_ARG_CMDARG_Pos) /*!< 0xFFFFFFFF */
+#define SDIO_ARG_CMDARG SDIO_ARG_CMDARG_Msk /*!< Command argument */
+
+/******************* Bit definition for SDIO_CMD register *******************/
+#define SDIO_CMD_CMDINDEX_Pos (0U)
+#define SDIO_CMD_CMDINDEX_Msk (0x3FU << SDIO_CMD_CMDINDEX_Pos) /*!< 0x0000003F */
+#define SDIO_CMD_CMDINDEX SDIO_CMD_CMDINDEX_Msk /*!< Command Index */
+
+#define SDIO_CMD_WAITRESP_Pos (6U)
+#define SDIO_CMD_WAITRESP_Msk (0x3U << SDIO_CMD_WAITRESP_Pos) /*!< 0x000000C0 */
+#define SDIO_CMD_WAITRESP SDIO_CMD_WAITRESP_Msk /*!< WAITRESP[1:0] bits (Wait for response bits) */
+#define SDIO_CMD_WAITRESP_0 (0x1U << SDIO_CMD_WAITRESP_Pos) /*!< 0x0040 */
+#define SDIO_CMD_WAITRESP_1 (0x2U << SDIO_CMD_WAITRESP_Pos) /*!< 0x0080 */
+
+#define SDIO_CMD_WAITINT_Pos (8U)
+#define SDIO_CMD_WAITINT_Msk (0x1U << SDIO_CMD_WAITINT_Pos) /*!< 0x00000100 */
+#define SDIO_CMD_WAITINT SDIO_CMD_WAITINT_Msk /*!< CPSM Waits for Interrupt Request */
+#define SDIO_CMD_WAITPEND_Pos (9U)
+#define SDIO_CMD_WAITPEND_Msk (0x1U << SDIO_CMD_WAITPEND_Pos) /*!< 0x00000200 */
+#define SDIO_CMD_WAITPEND SDIO_CMD_WAITPEND_Msk /*!< CPSM Waits for ends of data transfer (CmdPend internal signal) */
+#define SDIO_CMD_CPSMEN_Pos (10U)
+#define SDIO_CMD_CPSMEN_Msk (0x1U << SDIO_CMD_CPSMEN_Pos) /*!< 0x00000400 */
+#define SDIO_CMD_CPSMEN SDIO_CMD_CPSMEN_Msk /*!< Command path state machine (CPSM) Enable bit */
+#define SDIO_CMD_SDIOSUSPEND_Pos (11U)
+#define SDIO_CMD_SDIOSUSPEND_Msk (0x1U << SDIO_CMD_SDIOSUSPEND_Pos) /*!< 0x00000800 */
+#define SDIO_CMD_SDIOSUSPEND SDIO_CMD_SDIOSUSPEND_Msk /*!< SD I/O suspend command */
+#define SDIO_CMD_ENCMDCOMPL_Pos (12U)
+#define SDIO_CMD_ENCMDCOMPL_Msk (0x1U << SDIO_CMD_ENCMDCOMPL_Pos) /*!< 0x00001000 */
+#define SDIO_CMD_ENCMDCOMPL SDIO_CMD_ENCMDCOMPL_Msk /*!< Enable CMD completion */
+#define SDIO_CMD_NIEN_Pos (13U)
+#define SDIO_CMD_NIEN_Msk (0x1U << SDIO_CMD_NIEN_Pos) /*!< 0x00002000 */
+#define SDIO_CMD_NIEN SDIO_CMD_NIEN_Msk /*!< Not Interrupt Enable */
+#define SDIO_CMD_CEATACMD_Pos (14U)
+#define SDIO_CMD_CEATACMD_Msk (0x1U << SDIO_CMD_CEATACMD_Pos) /*!< 0x00004000 */
+#define SDIO_CMD_CEATACMD SDIO_CMD_CEATACMD_Msk /*!< CE-ATA command */
+
+/***************** Bit definition for SDIO_RESPCMD register *****************/
+#define SDIO_RESPCMD_RESPCMD_Pos (0U)
+#define SDIO_RESPCMD_RESPCMD_Msk (0x3FU << SDIO_RESPCMD_RESPCMD_Pos) /*!< 0x0000003F */
+#define SDIO_RESPCMD_RESPCMD SDIO_RESPCMD_RESPCMD_Msk /*!< Response command index */
+
+/****************** Bit definition for SDIO_RESP0 register ******************/
+#define SDIO_RESP0_CARDSTATUS0_Pos (0U)
+#define SDIO_RESP0_CARDSTATUS0_Msk (0xFFFFFFFFU << SDIO_RESP0_CARDSTATUS0_Pos) /*!< 0xFFFFFFFF */
+#define SDIO_RESP0_CARDSTATUS0 SDIO_RESP0_CARDSTATUS0_Msk /*!< Card Status */
+
+/****************** Bit definition for SDIO_RESP1 register ******************/
+#define SDIO_RESP1_CARDSTATUS1_Pos (0U)
+#define SDIO_RESP1_CARDSTATUS1_Msk (0xFFFFFFFFU << SDIO_RESP1_CARDSTATUS1_Pos) /*!< 0xFFFFFFFF */
+#define SDIO_RESP1_CARDSTATUS1 SDIO_RESP1_CARDSTATUS1_Msk /*!< Card Status */
+
+/****************** Bit definition for SDIO_RESP2 register ******************/
+#define SDIO_RESP2_CARDSTATUS2_Pos (0U)
+#define SDIO_RESP2_CARDSTATUS2_Msk (0xFFFFFFFFU << SDIO_RESP2_CARDSTATUS2_Pos) /*!< 0xFFFFFFFF */
+#define SDIO_RESP2_CARDSTATUS2 SDIO_RESP2_CARDSTATUS2_Msk /*!< Card Status */
+
+/****************** Bit definition for SDIO_RESP3 register ******************/
+#define SDIO_RESP3_CARDSTATUS3_Pos (0U)
+#define SDIO_RESP3_CARDSTATUS3_Msk (0xFFFFFFFFU << SDIO_RESP3_CARDSTATUS3_Pos) /*!< 0xFFFFFFFF */
+#define SDIO_RESP3_CARDSTATUS3 SDIO_RESP3_CARDSTATUS3_Msk /*!< Card Status */
+
+/****************** Bit definition for SDIO_RESP4 register ******************/
+#define SDIO_RESP4_CARDSTATUS4_Pos (0U)
+#define SDIO_RESP4_CARDSTATUS4_Msk (0xFFFFFFFFU << SDIO_RESP4_CARDSTATUS4_Pos) /*!< 0xFFFFFFFF */
+#define SDIO_RESP4_CARDSTATUS4 SDIO_RESP4_CARDSTATUS4_Msk /*!< Card Status */
+
+/****************** Bit definition for SDIO_DTIMER register *****************/
+#define SDIO_DTIMER_DATATIME_Pos (0U)
+#define SDIO_DTIMER_DATATIME_Msk (0xFFFFFFFFU << SDIO_DTIMER_DATATIME_Pos) /*!< 0xFFFFFFFF */
+#define SDIO_DTIMER_DATATIME SDIO_DTIMER_DATATIME_Msk /*!< Data timeout period. */
+
+/****************** Bit definition for SDIO_DLEN register *******************/
+#define SDIO_DLEN_DATALENGTH_Pos (0U)
+#define SDIO_DLEN_DATALENGTH_Msk (0x1FFFFFFU << SDIO_DLEN_DATALENGTH_Pos) /*!< 0x01FFFFFF */
+#define SDIO_DLEN_DATALENGTH SDIO_DLEN_DATALENGTH_Msk /*!< Data length value */
+
+/****************** Bit definition for SDIO_DCTRL register ******************/
+#define SDIO_DCTRL_DTEN_Pos (0U)
+#define SDIO_DCTRL_DTEN_Msk (0x1U << SDIO_DCTRL_DTEN_Pos) /*!< 0x00000001 */
+#define SDIO_DCTRL_DTEN SDIO_DCTRL_DTEN_Msk /*!< Data transfer enabled bit */
+#define SDIO_DCTRL_DTDIR_Pos (1U)
+#define SDIO_DCTRL_DTDIR_Msk (0x1U << SDIO_DCTRL_DTDIR_Pos) /*!< 0x00000002 */
+#define SDIO_DCTRL_DTDIR SDIO_DCTRL_DTDIR_Msk /*!< Data transfer direction selection */
+#define SDIO_DCTRL_DTMODE_Pos (2U)
+#define SDIO_DCTRL_DTMODE_Msk (0x1U << SDIO_DCTRL_DTMODE_Pos) /*!< 0x00000004 */
+#define SDIO_DCTRL_DTMODE SDIO_DCTRL_DTMODE_Msk /*!< Data transfer mode selection */
+#define SDIO_DCTRL_DMAEN_Pos (3U)
+#define SDIO_DCTRL_DMAEN_Msk (0x1U << SDIO_DCTRL_DMAEN_Pos) /*!< 0x00000008 */
+#define SDIO_DCTRL_DMAEN SDIO_DCTRL_DMAEN_Msk /*!< DMA enabled bit */
+
+#define SDIO_DCTRL_DBLOCKSIZE_Pos (4U)
+#define SDIO_DCTRL_DBLOCKSIZE_Msk (0xFU << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x000000F0 */
+#define SDIO_DCTRL_DBLOCKSIZE SDIO_DCTRL_DBLOCKSIZE_Msk /*!< DBLOCKSIZE[3:0] bits (Data block size) */
+#define SDIO_DCTRL_DBLOCKSIZE_0 (0x1U << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0010 */
+#define SDIO_DCTRL_DBLOCKSIZE_1 (0x2U << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0020 */
+#define SDIO_DCTRL_DBLOCKSIZE_2 (0x4U << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0040 */
+#define SDIO_DCTRL_DBLOCKSIZE_3 (0x8U << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0080 */
+
+#define SDIO_DCTRL_RWSTART_Pos (8U)
+#define SDIO_DCTRL_RWSTART_Msk (0x1U << SDIO_DCTRL_RWSTART_Pos) /*!< 0x00000100 */
+#define SDIO_DCTRL_RWSTART SDIO_DCTRL_RWSTART_Msk /*!< Read wait start */
+#define SDIO_DCTRL_RWSTOP_Pos (9U)
+#define SDIO_DCTRL_RWSTOP_Msk (0x1U << SDIO_DCTRL_RWSTOP_Pos) /*!< 0x00000200 */
+#define SDIO_DCTRL_RWSTOP SDIO_DCTRL_RWSTOP_Msk /*!< Read wait stop */
+#define SDIO_DCTRL_RWMOD_Pos (10U)
+#define SDIO_DCTRL_RWMOD_Msk (0x1U << SDIO_DCTRL_RWMOD_Pos) /*!< 0x00000400 */
+#define SDIO_DCTRL_RWMOD SDIO_DCTRL_RWMOD_Msk /*!< Read wait mode */
+#define SDIO_DCTRL_SDIOEN_Pos (11U)
+#define SDIO_DCTRL_SDIOEN_Msk (0x1U << SDIO_DCTRL_SDIOEN_Pos) /*!< 0x00000800 */
+#define SDIO_DCTRL_SDIOEN SDIO_DCTRL_SDIOEN_Msk /*!< SD I/O enable functions */
+
+/****************** Bit definition for SDIO_DCOUNT register *****************/
+#define SDIO_DCOUNT_DATACOUNT_Pos (0U)
+#define SDIO_DCOUNT_DATACOUNT_Msk (0x1FFFFFFU << SDIO_DCOUNT_DATACOUNT_Pos) /*!< 0x01FFFFFF */
+#define SDIO_DCOUNT_DATACOUNT SDIO_DCOUNT_DATACOUNT_Msk /*!< Data count value */
+
+/****************** Bit definition for SDIO_STA register ********************/
+#define SDIO_STA_CCRCFAIL_Pos (0U)
+#define SDIO_STA_CCRCFAIL_Msk (0x1U << SDIO_STA_CCRCFAIL_Pos) /*!< 0x00000001 */
+#define SDIO_STA_CCRCFAIL SDIO_STA_CCRCFAIL_Msk /*!< Command response received (CRC check failed) */
+#define SDIO_STA_DCRCFAIL_Pos (1U)
+#define SDIO_STA_DCRCFAIL_Msk (0x1U << SDIO_STA_DCRCFAIL_Pos) /*!< 0x00000002 */
+#define SDIO_STA_DCRCFAIL SDIO_STA_DCRCFAIL_Msk /*!< Data block sent/received (CRC check failed) */
+#define SDIO_STA_CTIMEOUT_Pos (2U)
+#define SDIO_STA_CTIMEOUT_Msk (0x1U << SDIO_STA_CTIMEOUT_Pos) /*!< 0x00000004 */
+#define SDIO_STA_CTIMEOUT SDIO_STA_CTIMEOUT_Msk /*!< Command response timeout */
+#define SDIO_STA_DTIMEOUT_Pos (3U)
+#define SDIO_STA_DTIMEOUT_Msk (0x1U << SDIO_STA_DTIMEOUT_Pos) /*!< 0x00000008 */
+#define SDIO_STA_DTIMEOUT SDIO_STA_DTIMEOUT_Msk /*!< Data timeout */
+#define SDIO_STA_TXUNDERR_Pos (4U)
+#define SDIO_STA_TXUNDERR_Msk (0x1U << SDIO_STA_TXUNDERR_Pos) /*!< 0x00000010 */
+#define SDIO_STA_TXUNDERR SDIO_STA_TXUNDERR_Msk /*!< Transmit FIFO underrun error */
+#define SDIO_STA_RXOVERR_Pos (5U)
+#define SDIO_STA_RXOVERR_Msk (0x1U << SDIO_STA_RXOVERR_Pos) /*!< 0x00000020 */
+#define SDIO_STA_RXOVERR SDIO_STA_RXOVERR_Msk /*!< Received FIFO overrun error */
+#define SDIO_STA_CMDREND_Pos (6U)
+#define SDIO_STA_CMDREND_Msk (0x1U << SDIO_STA_CMDREND_Pos) /*!< 0x00000040 */
+#define SDIO_STA_CMDREND SDIO_STA_CMDREND_Msk /*!< Command response received (CRC check passed) */
+#define SDIO_STA_CMDSENT_Pos (7U)
+#define SDIO_STA_CMDSENT_Msk (0x1U << SDIO_STA_CMDSENT_Pos) /*!< 0x00000080 */
+#define SDIO_STA_CMDSENT SDIO_STA_CMDSENT_Msk /*!< Command sent (no response required) */
+#define SDIO_STA_DATAEND_Pos (8U)
+#define SDIO_STA_DATAEND_Msk (0x1U << SDIO_STA_DATAEND_Pos) /*!< 0x00000100 */
+#define SDIO_STA_DATAEND SDIO_STA_DATAEND_Msk /*!< Data end (data counter, SDIDCOUNT, is zero) */
+#define SDIO_STA_STBITERR_Pos (9U)
+#define SDIO_STA_STBITERR_Msk (0x1U << SDIO_STA_STBITERR_Pos) /*!< 0x00000200 */
+#define SDIO_STA_STBITERR SDIO_STA_STBITERR_Msk /*!< Start bit not detected on all data signals in wide bus mode */
+#define SDIO_STA_DBCKEND_Pos (10U)
+#define SDIO_STA_DBCKEND_Msk (0x1U << SDIO_STA_DBCKEND_Pos) /*!< 0x00000400 */
+#define SDIO_STA_DBCKEND SDIO_STA_DBCKEND_Msk /*!< Data block sent/received (CRC check passed) */
+#define SDIO_STA_CMDACT_Pos (11U)
+#define SDIO_STA_CMDACT_Msk (0x1U << SDIO_STA_CMDACT_Pos) /*!< 0x00000800 */
+#define SDIO_STA_CMDACT SDIO_STA_CMDACT_Msk /*!< Command transfer in progress */
+#define SDIO_STA_TXACT_Pos (12U)
+#define SDIO_STA_TXACT_Msk (0x1U << SDIO_STA_TXACT_Pos) /*!< 0x00001000 */
+#define SDIO_STA_TXACT SDIO_STA_TXACT_Msk /*!< Data transmit in progress */
+#define SDIO_STA_RXACT_Pos (13U)
+#define SDIO_STA_RXACT_Msk (0x1U << SDIO_STA_RXACT_Pos) /*!< 0x00002000 */
+#define SDIO_STA_RXACT SDIO_STA_RXACT_Msk /*!< Data receive in progress */
+#define SDIO_STA_TXFIFOHE_Pos (14U)
+#define SDIO_STA_TXFIFOHE_Msk (0x1U << SDIO_STA_TXFIFOHE_Pos) /*!< 0x00004000 */
+#define SDIO_STA_TXFIFOHE SDIO_STA_TXFIFOHE_Msk /*!< Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
+#define SDIO_STA_RXFIFOHF_Pos (15U)
+#define SDIO_STA_RXFIFOHF_Msk (0x1U << SDIO_STA_RXFIFOHF_Pos) /*!< 0x00008000 */
+#define SDIO_STA_RXFIFOHF SDIO_STA_RXFIFOHF_Msk /*!< Receive FIFO Half Full: there are at least 8 words in the FIFO */
+#define SDIO_STA_TXFIFOF_Pos (16U)
+#define SDIO_STA_TXFIFOF_Msk (0x1U << SDIO_STA_TXFIFOF_Pos) /*!< 0x00010000 */
+#define SDIO_STA_TXFIFOF SDIO_STA_TXFIFOF_Msk /*!< Transmit FIFO full */
+#define SDIO_STA_RXFIFOF_Pos (17U)
+#define SDIO_STA_RXFIFOF_Msk (0x1U << SDIO_STA_RXFIFOF_Pos) /*!< 0x00020000 */
+#define SDIO_STA_RXFIFOF SDIO_STA_RXFIFOF_Msk /*!< Receive FIFO full */
+#define SDIO_STA_TXFIFOE_Pos (18U)
+#define SDIO_STA_TXFIFOE_Msk (0x1U << SDIO_STA_TXFIFOE_Pos) /*!< 0x00040000 */
+#define SDIO_STA_TXFIFOE SDIO_STA_TXFIFOE_Msk /*!< Transmit FIFO empty */
+#define SDIO_STA_RXFIFOE_Pos (19U)
+#define SDIO_STA_RXFIFOE_Msk (0x1U << SDIO_STA_RXFIFOE_Pos) /*!< 0x00080000 */
+#define SDIO_STA_RXFIFOE SDIO_STA_RXFIFOE_Msk /*!< Receive FIFO empty */
+#define SDIO_STA_TXDAVL_Pos (20U)
+#define SDIO_STA_TXDAVL_Msk (0x1U << SDIO_STA_TXDAVL_Pos) /*!< 0x00100000 */
+#define SDIO_STA_TXDAVL SDIO_STA_TXDAVL_Msk /*!< Data available in transmit FIFO */
+#define SDIO_STA_RXDAVL_Pos (21U)
+#define SDIO_STA_RXDAVL_Msk (0x1U << SDIO_STA_RXDAVL_Pos) /*!< 0x00200000 */
+#define SDIO_STA_RXDAVL SDIO_STA_RXDAVL_Msk /*!< Data available in receive FIFO */
+#define SDIO_STA_SDIOIT_Pos (22U)
+#define SDIO_STA_SDIOIT_Msk (0x1U << SDIO_STA_SDIOIT_Pos) /*!< 0x00400000 */
+#define SDIO_STA_SDIOIT SDIO_STA_SDIOIT_Msk /*!< SDIO interrupt received */
+#define SDIO_STA_CEATAEND_Pos (23U)
+#define SDIO_STA_CEATAEND_Msk (0x1U << SDIO_STA_CEATAEND_Pos) /*!< 0x00800000 */
+#define SDIO_STA_CEATAEND SDIO_STA_CEATAEND_Msk /*!< CE-ATA command completion signal received for CMD61 */
+
+/******************* Bit definition for SDIO_ICR register *******************/
+#define SDIO_ICR_CCRCFAILC_Pos (0U)
+#define SDIO_ICR_CCRCFAILC_Msk (0x1U << SDIO_ICR_CCRCFAILC_Pos) /*!< 0x00000001 */
+#define SDIO_ICR_CCRCFAILC SDIO_ICR_CCRCFAILC_Msk /*!< CCRCFAIL flag clear bit */
+#define SDIO_ICR_DCRCFAILC_Pos (1U)
+#define SDIO_ICR_DCRCFAILC_Msk (0x1U << SDIO_ICR_DCRCFAILC_Pos) /*!< 0x00000002 */
+#define SDIO_ICR_DCRCFAILC SDIO_ICR_DCRCFAILC_Msk /*!< DCRCFAIL flag clear bit */
+#define SDIO_ICR_CTIMEOUTC_Pos (2U)
+#define SDIO_ICR_CTIMEOUTC_Msk (0x1U << SDIO_ICR_CTIMEOUTC_Pos) /*!< 0x00000004 */
+#define SDIO_ICR_CTIMEOUTC SDIO_ICR_CTIMEOUTC_Msk /*!< CTIMEOUT flag clear bit */
+#define SDIO_ICR_DTIMEOUTC_Pos (3U)
+#define SDIO_ICR_DTIMEOUTC_Msk (0x1U << SDIO_ICR_DTIMEOUTC_Pos) /*!< 0x00000008 */
+#define SDIO_ICR_DTIMEOUTC SDIO_ICR_DTIMEOUTC_Msk /*!< DTIMEOUT flag clear bit */
+#define SDIO_ICR_TXUNDERRC_Pos (4U)
+#define SDIO_ICR_TXUNDERRC_Msk (0x1U << SDIO_ICR_TXUNDERRC_Pos) /*!< 0x00000010 */
+#define SDIO_ICR_TXUNDERRC SDIO_ICR_TXUNDERRC_Msk /*!< TXUNDERR flag clear bit */
+#define SDIO_ICR_RXOVERRC_Pos (5U)
+#define SDIO_ICR_RXOVERRC_Msk (0x1U << SDIO_ICR_RXOVERRC_Pos) /*!< 0x00000020 */
+#define SDIO_ICR_RXOVERRC SDIO_ICR_RXOVERRC_Msk /*!< RXOVERR flag clear bit */
+#define SDIO_ICR_CMDRENDC_Pos (6U)
+#define SDIO_ICR_CMDRENDC_Msk (0x1U << SDIO_ICR_CMDRENDC_Pos) /*!< 0x00000040 */
+#define SDIO_ICR_CMDRENDC SDIO_ICR_CMDRENDC_Msk /*!< CMDREND flag clear bit */
+#define SDIO_ICR_CMDSENTC_Pos (7U)
+#define SDIO_ICR_CMDSENTC_Msk (0x1U << SDIO_ICR_CMDSENTC_Pos) /*!< 0x00000080 */
+#define SDIO_ICR_CMDSENTC SDIO_ICR_CMDSENTC_Msk /*!< CMDSENT flag clear bit */
+#define SDIO_ICR_DATAENDC_Pos (8U)
+#define SDIO_ICR_DATAENDC_Msk (0x1U << SDIO_ICR_DATAENDC_Pos) /*!< 0x00000100 */
+#define SDIO_ICR_DATAENDC SDIO_ICR_DATAENDC_Msk /*!< DATAEND flag clear bit */
+#define SDIO_ICR_STBITERRC_Pos (9U)
+#define SDIO_ICR_STBITERRC_Msk (0x1U << SDIO_ICR_STBITERRC_Pos) /*!< 0x00000200 */
+#define SDIO_ICR_STBITERRC SDIO_ICR_STBITERRC_Msk /*!< STBITERR flag clear bit */
+#define SDIO_ICR_DBCKENDC_Pos (10U)
+#define SDIO_ICR_DBCKENDC_Msk (0x1U << SDIO_ICR_DBCKENDC_Pos) /*!< 0x00000400 */
+#define SDIO_ICR_DBCKENDC SDIO_ICR_DBCKENDC_Msk /*!< DBCKEND flag clear bit */
+#define SDIO_ICR_SDIOITC_Pos (22U)
+#define SDIO_ICR_SDIOITC_Msk (0x1U << SDIO_ICR_SDIOITC_Pos) /*!< 0x00400000 */
+#define SDIO_ICR_SDIOITC SDIO_ICR_SDIOITC_Msk /*!< SDIOIT flag clear bit */
+#define SDIO_ICR_CEATAENDC_Pos (23U)
+#define SDIO_ICR_CEATAENDC_Msk (0x1U << SDIO_ICR_CEATAENDC_Pos) /*!< 0x00800000 */
+#define SDIO_ICR_CEATAENDC SDIO_ICR_CEATAENDC_Msk /*!< CEATAEND flag clear bit */
+
+/****************** Bit definition for SDIO_MASK register *******************/
+#define SDIO_MASK_CCRCFAILIE_Pos (0U)
+#define SDIO_MASK_CCRCFAILIE_Msk (0x1U << SDIO_MASK_CCRCFAILIE_Pos) /*!< 0x00000001 */
+#define SDIO_MASK_CCRCFAILIE SDIO_MASK_CCRCFAILIE_Msk /*!< Command CRC Fail Interrupt Enable */
+#define SDIO_MASK_DCRCFAILIE_Pos (1U)
+#define SDIO_MASK_DCRCFAILIE_Msk (0x1U << SDIO_MASK_DCRCFAILIE_Pos) /*!< 0x00000002 */
+#define SDIO_MASK_DCRCFAILIE SDIO_MASK_DCRCFAILIE_Msk /*!< Data CRC Fail Interrupt Enable */
+#define SDIO_MASK_CTIMEOUTIE_Pos (2U)
+#define SDIO_MASK_CTIMEOUTIE_Msk (0x1U << SDIO_MASK_CTIMEOUTIE_Pos) /*!< 0x00000004 */
+#define SDIO_MASK_CTIMEOUTIE SDIO_MASK_CTIMEOUTIE_Msk /*!< Command TimeOut Interrupt Enable */
+#define SDIO_MASK_DTIMEOUTIE_Pos (3U)
+#define SDIO_MASK_DTIMEOUTIE_Msk (0x1U << SDIO_MASK_DTIMEOUTIE_Pos) /*!< 0x00000008 */
+#define SDIO_MASK_DTIMEOUTIE SDIO_MASK_DTIMEOUTIE_Msk /*!< Data TimeOut Interrupt Enable */
+#define SDIO_MASK_TXUNDERRIE_Pos (4U)
+#define SDIO_MASK_TXUNDERRIE_Msk (0x1U << SDIO_MASK_TXUNDERRIE_Pos) /*!< 0x00000010 */
+#define SDIO_MASK_TXUNDERRIE SDIO_MASK_TXUNDERRIE_Msk /*!< Tx FIFO UnderRun Error Interrupt Enable */
+#define SDIO_MASK_RXOVERRIE_Pos (5U)
+#define SDIO_MASK_RXOVERRIE_Msk (0x1U << SDIO_MASK_RXOVERRIE_Pos) /*!< 0x00000020 */
+#define SDIO_MASK_RXOVERRIE SDIO_MASK_RXOVERRIE_Msk /*!< Rx FIFO OverRun Error Interrupt Enable */
+#define SDIO_MASK_CMDRENDIE_Pos (6U)
+#define SDIO_MASK_CMDRENDIE_Msk (0x1U << SDIO_MASK_CMDRENDIE_Pos) /*!< 0x00000040 */
+#define SDIO_MASK_CMDRENDIE SDIO_MASK_CMDRENDIE_Msk /*!< Command Response Received Interrupt Enable */
+#define SDIO_MASK_CMDSENTIE_Pos (7U)
+#define SDIO_MASK_CMDSENTIE_Msk (0x1U << SDIO_MASK_CMDSENTIE_Pos) /*!< 0x00000080 */
+#define SDIO_MASK_CMDSENTIE SDIO_MASK_CMDSENTIE_Msk /*!< Command Sent Interrupt Enable */
+#define SDIO_MASK_DATAENDIE_Pos (8U)
+#define SDIO_MASK_DATAENDIE_Msk (0x1U << SDIO_MASK_DATAENDIE_Pos) /*!< 0x00000100 */
+#define SDIO_MASK_DATAENDIE SDIO_MASK_DATAENDIE_Msk /*!< Data End Interrupt Enable */
+#define SDIO_MASK_STBITERRIE_Pos (9U)
+#define SDIO_MASK_STBITERRIE_Msk (0x1U << SDIO_MASK_STBITERRIE_Pos) /*!< 0x00000200 */
+#define SDIO_MASK_STBITERRIE SDIO_MASK_STBITERRIE_Msk /*!< Start Bit Error Interrupt Enable */
+#define SDIO_MASK_DBCKENDIE_Pos (10U)
+#define SDIO_MASK_DBCKENDIE_Msk (0x1U << SDIO_MASK_DBCKENDIE_Pos) /*!< 0x00000400 */
+#define SDIO_MASK_DBCKENDIE SDIO_MASK_DBCKENDIE_Msk /*!< Data Block End Interrupt Enable */
+#define SDIO_MASK_CMDACTIE_Pos (11U)
+#define SDIO_MASK_CMDACTIE_Msk (0x1U << SDIO_MASK_CMDACTIE_Pos) /*!< 0x00000800 */
+#define SDIO_MASK_CMDACTIE SDIO_MASK_CMDACTIE_Msk /*!< Command Acting Interrupt Enable */
+#define SDIO_MASK_TXACTIE_Pos (12U)
+#define SDIO_MASK_TXACTIE_Msk (0x1U << SDIO_MASK_TXACTIE_Pos) /*!< 0x00001000 */
+#define SDIO_MASK_TXACTIE SDIO_MASK_TXACTIE_Msk /*!< Data Transmit Acting Interrupt Enable */
+#define SDIO_MASK_RXACTIE_Pos (13U)
+#define SDIO_MASK_RXACTIE_Msk (0x1U << SDIO_MASK_RXACTIE_Pos) /*!< 0x00002000 */
+#define SDIO_MASK_RXACTIE SDIO_MASK_RXACTIE_Msk /*!< Data receive acting interrupt enabled */
+#define SDIO_MASK_TXFIFOHEIE_Pos (14U)
+#define SDIO_MASK_TXFIFOHEIE_Msk (0x1U << SDIO_MASK_TXFIFOHEIE_Pos) /*!< 0x00004000 */
+#define SDIO_MASK_TXFIFOHEIE SDIO_MASK_TXFIFOHEIE_Msk /*!< Tx FIFO Half Empty interrupt Enable */
+#define SDIO_MASK_RXFIFOHFIE_Pos (15U)
+#define SDIO_MASK_RXFIFOHFIE_Msk (0x1U << SDIO_MASK_RXFIFOHFIE_Pos) /*!< 0x00008000 */
+#define SDIO_MASK_RXFIFOHFIE SDIO_MASK_RXFIFOHFIE_Msk /*!< Rx FIFO Half Full interrupt Enable */
+#define SDIO_MASK_TXFIFOFIE_Pos (16U)
+#define SDIO_MASK_TXFIFOFIE_Msk (0x1U << SDIO_MASK_TXFIFOFIE_Pos) /*!< 0x00010000 */
+#define SDIO_MASK_TXFIFOFIE SDIO_MASK_TXFIFOFIE_Msk /*!< Tx FIFO Full interrupt Enable */
+#define SDIO_MASK_RXFIFOFIE_Pos (17U)
+#define SDIO_MASK_RXFIFOFIE_Msk (0x1U << SDIO_MASK_RXFIFOFIE_Pos) /*!< 0x00020000 */
+#define SDIO_MASK_RXFIFOFIE SDIO_MASK_RXFIFOFIE_Msk /*!< Rx FIFO Full interrupt Enable */
+#define SDIO_MASK_TXFIFOEIE_Pos (18U)
+#define SDIO_MASK_TXFIFOEIE_Msk (0x1U << SDIO_MASK_TXFIFOEIE_Pos) /*!< 0x00040000 */
+#define SDIO_MASK_TXFIFOEIE SDIO_MASK_TXFIFOEIE_Msk /*!< Tx FIFO Empty interrupt Enable */
+#define SDIO_MASK_RXFIFOEIE_Pos (19U)
+#define SDIO_MASK_RXFIFOEIE_Msk (0x1U << SDIO_MASK_RXFIFOEIE_Pos) /*!< 0x00080000 */
+#define SDIO_MASK_RXFIFOEIE SDIO_MASK_RXFIFOEIE_Msk /*!< Rx FIFO Empty interrupt Enable */
+#define SDIO_MASK_TXDAVLIE_Pos (20U)
+#define SDIO_MASK_TXDAVLIE_Msk (0x1U << SDIO_MASK_TXDAVLIE_Pos) /*!< 0x00100000 */
+#define SDIO_MASK_TXDAVLIE SDIO_MASK_TXDAVLIE_Msk /*!< Data available in Tx FIFO interrupt Enable */
+#define SDIO_MASK_RXDAVLIE_Pos (21U)
+#define SDIO_MASK_RXDAVLIE_Msk (0x1U << SDIO_MASK_RXDAVLIE_Pos) /*!< 0x00200000 */
+#define SDIO_MASK_RXDAVLIE SDIO_MASK_RXDAVLIE_Msk /*!< Data available in Rx FIFO interrupt Enable */
+#define SDIO_MASK_SDIOITIE_Pos (22U)
+#define SDIO_MASK_SDIOITIE_Msk (0x1U << SDIO_MASK_SDIOITIE_Pos) /*!< 0x00400000 */
+#define SDIO_MASK_SDIOITIE SDIO_MASK_SDIOITIE_Msk /*!< SDIO Mode Interrupt Received interrupt Enable */
+#define SDIO_MASK_CEATAENDIE_Pos (23U)
+#define SDIO_MASK_CEATAENDIE_Msk (0x1U << SDIO_MASK_CEATAENDIE_Pos) /*!< 0x00800000 */
+#define SDIO_MASK_CEATAENDIE SDIO_MASK_CEATAENDIE_Msk /*!< CE-ATA command completion signal received Interrupt Enable */
+
+/***************** Bit definition for SDIO_FIFOCNT register *****************/
+#define SDIO_FIFOCNT_FIFOCOUNT_Pos (0U)
+#define SDIO_FIFOCNT_FIFOCOUNT_Msk (0xFFFFFFU << SDIO_FIFOCNT_FIFOCOUNT_Pos) /*!< 0x00FFFFFF */
+#define SDIO_FIFOCNT_FIFOCOUNT SDIO_FIFOCNT_FIFOCOUNT_Msk /*!< Remaining number of words to be written to or read from the FIFO */
+
+/****************** Bit definition for SDIO_FIFO register *******************/
+#define SDIO_FIFO_FIFODATA_Pos (0U)
+#define SDIO_FIFO_FIFODATA_Msk (0xFFFFFFFFU << SDIO_FIFO_FIFODATA_Pos) /*!< 0xFFFFFFFF */
+#define SDIO_FIFO_FIFODATA SDIO_FIFO_FIFODATA_Msk /*!< Receive and transmit FIFO data */
+
+
+
+/******************************************************************************/
+/* */
+/* Serial Peripheral Interface */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for SPI_CR1 register ********************/
+#define SPI_CR1_CPHA_Pos (0U)
+#define SPI_CR1_CPHA_Msk (0x1U << SPI_CR1_CPHA_Pos) /*!< 0x00000001 */
+#define SPI_CR1_CPHA SPI_CR1_CPHA_Msk /*!< Clock Phase */
+#define SPI_CR1_CPOL_Pos (1U)
+#define SPI_CR1_CPOL_Msk (0x1U << SPI_CR1_CPOL_Pos) /*!< 0x00000002 */
+#define SPI_CR1_CPOL SPI_CR1_CPOL_Msk /*!< Clock Polarity */
+#define SPI_CR1_MSTR_Pos (2U)
+#define SPI_CR1_MSTR_Msk (0x1U << SPI_CR1_MSTR_Pos) /*!< 0x00000004 */
+#define SPI_CR1_MSTR SPI_CR1_MSTR_Msk /*!< Master Selection */
+
+#define SPI_CR1_BR_Pos (3U)
+#define SPI_CR1_BR_Msk (0x7U << SPI_CR1_BR_Pos) /*!< 0x00000038 */
+#define SPI_CR1_BR SPI_CR1_BR_Msk /*!< BR[2:0] bits (Baud Rate Control) */
+#define SPI_CR1_BR_0 (0x1U << SPI_CR1_BR_Pos) /*!< 0x00000008 */
+#define SPI_CR1_BR_1 (0x2U << SPI_CR1_BR_Pos) /*!< 0x00000010 */
+#define SPI_CR1_BR_2 (0x4U << SPI_CR1_BR_Pos) /*!< 0x00000020 */
+
+#define SPI_CR1_SPE_Pos (6U)
+#define SPI_CR1_SPE_Msk (0x1U << SPI_CR1_SPE_Pos) /*!< 0x00000040 */
+#define SPI_CR1_SPE SPI_CR1_SPE_Msk /*!< SPI Enable */
+#define SPI_CR1_LSBFIRST_Pos (7U)
+#define SPI_CR1_LSBFIRST_Msk (0x1U << SPI_CR1_LSBFIRST_Pos) /*!< 0x00000080 */
+#define SPI_CR1_LSBFIRST SPI_CR1_LSBFIRST_Msk /*!< Frame Format */
+#define SPI_CR1_SSI_Pos (8U)
+#define SPI_CR1_SSI_Msk (0x1U << SPI_CR1_SSI_Pos) /*!< 0x00000100 */
+#define SPI_CR1_SSI SPI_CR1_SSI_Msk /*!< Internal slave select */
+#define SPI_CR1_SSM_Pos (9U)
+#define SPI_CR1_SSM_Msk (0x1U << SPI_CR1_SSM_Pos) /*!< 0x00000200 */
+#define SPI_CR1_SSM SPI_CR1_SSM_Msk /*!< Software slave management */
+#define SPI_CR1_RXONLY_Pos (10U)
+#define SPI_CR1_RXONLY_Msk (0x1U << SPI_CR1_RXONLY_Pos) /*!< 0x00000400 */
+#define SPI_CR1_RXONLY SPI_CR1_RXONLY_Msk /*!< Receive only */
+#define SPI_CR1_DFF_Pos (11U)
+#define SPI_CR1_DFF_Msk (0x1U << SPI_CR1_DFF_Pos) /*!< 0x00000800 */
+#define SPI_CR1_DFF SPI_CR1_DFF_Msk /*!< Data Frame Format */
+#define SPI_CR1_CRCNEXT_Pos (12U)
+#define SPI_CR1_CRCNEXT_Msk (0x1U << SPI_CR1_CRCNEXT_Pos) /*!< 0x00001000 */
+#define SPI_CR1_CRCNEXT SPI_CR1_CRCNEXT_Msk /*!< Transmit CRC next */
+#define SPI_CR1_CRCEN_Pos (13U)
+#define SPI_CR1_CRCEN_Msk (0x1U << SPI_CR1_CRCEN_Pos) /*!< 0x00002000 */
+#define SPI_CR1_CRCEN SPI_CR1_CRCEN_Msk /*!< Hardware CRC calculation enable */
+#define SPI_CR1_BIDIOE_Pos (14U)
+#define SPI_CR1_BIDIOE_Msk (0x1U << SPI_CR1_BIDIOE_Pos) /*!< 0x00004000 */
+#define SPI_CR1_BIDIOE SPI_CR1_BIDIOE_Msk /*!< Output enable in bidirectional mode */
+#define SPI_CR1_BIDIMODE_Pos (15U)
+#define SPI_CR1_BIDIMODE_Msk (0x1U << SPI_CR1_BIDIMODE_Pos) /*!< 0x00008000 */
+#define SPI_CR1_BIDIMODE SPI_CR1_BIDIMODE_Msk /*!< Bidirectional data mode enable */
+
+/******************* Bit definition for SPI_CR2 register ********************/
+#define SPI_CR2_RXDMAEN_Pos (0U)
+#define SPI_CR2_RXDMAEN_Msk (0x1U << SPI_CR2_RXDMAEN_Pos) /*!< 0x00000001 */
+#define SPI_CR2_RXDMAEN SPI_CR2_RXDMAEN_Msk /*!< Rx Buffer DMA Enable */
+#define SPI_CR2_TXDMAEN_Pos (1U)
+#define SPI_CR2_TXDMAEN_Msk (0x1U << SPI_CR2_TXDMAEN_Pos) /*!< 0x00000002 */
+#define SPI_CR2_TXDMAEN SPI_CR2_TXDMAEN_Msk /*!< Tx Buffer DMA Enable */
+#define SPI_CR2_SSOE_Pos (2U)
+#define SPI_CR2_SSOE_Msk (0x1U << SPI_CR2_SSOE_Pos) /*!< 0x00000004 */
+#define SPI_CR2_SSOE SPI_CR2_SSOE_Msk /*!< SS Output Enable */
+#define SPI_CR2_ERRIE_Pos (5U)
+#define SPI_CR2_ERRIE_Msk (0x1U << SPI_CR2_ERRIE_Pos) /*!< 0x00000020 */
+#define SPI_CR2_ERRIE SPI_CR2_ERRIE_Msk /*!< Error Interrupt Enable */
+#define SPI_CR2_RXNEIE_Pos (6U)
+#define SPI_CR2_RXNEIE_Msk (0x1U << SPI_CR2_RXNEIE_Pos) /*!< 0x00000040 */
+#define SPI_CR2_RXNEIE SPI_CR2_RXNEIE_Msk /*!< RX buffer Not Empty Interrupt Enable */
+#define SPI_CR2_TXEIE_Pos (7U)
+#define SPI_CR2_TXEIE_Msk (0x1U << SPI_CR2_TXEIE_Pos) /*!< 0x00000080 */
+#define SPI_CR2_TXEIE SPI_CR2_TXEIE_Msk /*!< Tx buffer Empty Interrupt Enable */
+
+/******************** Bit definition for SPI_SR register ********************/
+#define SPI_SR_RXNE_Pos (0U)
+#define SPI_SR_RXNE_Msk (0x1U << SPI_SR_RXNE_Pos) /*!< 0x00000001 */
+#define SPI_SR_RXNE SPI_SR_RXNE_Msk /*!< Receive buffer Not Empty */
+#define SPI_SR_TXE_Pos (1U)
+#define SPI_SR_TXE_Msk (0x1U << SPI_SR_TXE_Pos) /*!< 0x00000002 */
+#define SPI_SR_TXE SPI_SR_TXE_Msk /*!< Transmit buffer Empty */
+#define SPI_SR_CHSIDE_Pos (2U)
+#define SPI_SR_CHSIDE_Msk (0x1U << SPI_SR_CHSIDE_Pos) /*!< 0x00000004 */
+#define SPI_SR_CHSIDE SPI_SR_CHSIDE_Msk /*!< Channel side */
+#define SPI_SR_UDR_Pos (3U)
+#define SPI_SR_UDR_Msk (0x1U << SPI_SR_UDR_Pos) /*!< 0x00000008 */
+#define SPI_SR_UDR SPI_SR_UDR_Msk /*!< Underrun flag */
+#define SPI_SR_CRCERR_Pos (4U)
+#define SPI_SR_CRCERR_Msk (0x1U << SPI_SR_CRCERR_Pos) /*!< 0x00000010 */
+#define SPI_SR_CRCERR SPI_SR_CRCERR_Msk /*!< CRC Error flag */
+#define SPI_SR_MODF_Pos (5U)
+#define SPI_SR_MODF_Msk (0x1U << SPI_SR_MODF_Pos) /*!< 0x00000020 */
+#define SPI_SR_MODF SPI_SR_MODF_Msk /*!< Mode fault */
+#define SPI_SR_OVR_Pos (6U)
+#define SPI_SR_OVR_Msk (0x1U << SPI_SR_OVR_Pos) /*!< 0x00000040 */
+#define SPI_SR_OVR SPI_SR_OVR_Msk /*!< Overrun flag */
+#define SPI_SR_BSY_Pos (7U)
+#define SPI_SR_BSY_Msk (0x1U << SPI_SR_BSY_Pos) /*!< 0x00000080 */
+#define SPI_SR_BSY SPI_SR_BSY_Msk /*!< Busy flag */
+
+/******************** Bit definition for SPI_DR register ********************/
+#define SPI_DR_DR_Pos (0U)
+#define SPI_DR_DR_Msk (0xFFFFU << SPI_DR_DR_Pos) /*!< 0x0000FFFF */
+#define SPI_DR_DR SPI_DR_DR_Msk /*!< Data Register */
+
+/******************* Bit definition for SPI_CRCPR register ******************/
+#define SPI_CRCPR_CRCPOLY_Pos (0U)
+#define SPI_CRCPR_CRCPOLY_Msk (0xFFFFU << SPI_CRCPR_CRCPOLY_Pos) /*!< 0x0000FFFF */
+#define SPI_CRCPR_CRCPOLY SPI_CRCPR_CRCPOLY_Msk /*!< CRC polynomial register */
+
+/****************** Bit definition for SPI_RXCRCR register ******************/
+#define SPI_RXCRCR_RXCRC_Pos (0U)
+#define SPI_RXCRCR_RXCRC_Msk (0xFFFFU << SPI_RXCRCR_RXCRC_Pos) /*!< 0x0000FFFF */
+#define SPI_RXCRCR_RXCRC SPI_RXCRCR_RXCRC_Msk /*!< Rx CRC Register */
+
+/****************** Bit definition for SPI_TXCRCR register ******************/
+#define SPI_TXCRCR_TXCRC_Pos (0U)
+#define SPI_TXCRCR_TXCRC_Msk (0xFFFFU << SPI_TXCRCR_TXCRC_Pos) /*!< 0x0000FFFF */
+#define SPI_TXCRCR_TXCRC SPI_TXCRCR_TXCRC_Msk /*!< Tx CRC Register */
+
+/****************** Bit definition for SPI_I2SCFGR register *****************/
+#define SPI_I2SCFGR_I2SMOD_Pos (11U)
+#define SPI_I2SCFGR_I2SMOD_Msk (0x1U << SPI_I2SCFGR_I2SMOD_Pos) /*!< 0x00000800 */
+#define SPI_I2SCFGR_I2SMOD SPI_I2SCFGR_I2SMOD_Msk /*!< I2S mode selection */
+
+
+/******************************************************************************/
+/* */
+/* Inter-integrated Circuit Interface */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for I2C_CR1 register ********************/
+#define I2C_CR1_PE_Pos (0U)
+#define I2C_CR1_PE_Msk (0x1U << I2C_CR1_PE_Pos) /*!< 0x00000001 */
+#define I2C_CR1_PE I2C_CR1_PE_Msk /*!< Peripheral Enable */
+#define I2C_CR1_SMBUS_Pos (1U)
+#define I2C_CR1_SMBUS_Msk (0x1U << I2C_CR1_SMBUS_Pos) /*!< 0x00000002 */
+#define I2C_CR1_SMBUS I2C_CR1_SMBUS_Msk /*!< SMBus Mode */
+#define I2C_CR1_SMBTYPE_Pos (3U)
+#define I2C_CR1_SMBTYPE_Msk (0x1U << I2C_CR1_SMBTYPE_Pos) /*!< 0x00000008 */
+#define I2C_CR1_SMBTYPE I2C_CR1_SMBTYPE_Msk /*!< SMBus Type */
+#define I2C_CR1_ENARP_Pos (4U)
+#define I2C_CR1_ENARP_Msk (0x1U << I2C_CR1_ENARP_Pos) /*!< 0x00000010 */
+#define I2C_CR1_ENARP I2C_CR1_ENARP_Msk /*!< ARP Enable */
+#define I2C_CR1_ENPEC_Pos (5U)
+#define I2C_CR1_ENPEC_Msk (0x1U << I2C_CR1_ENPEC_Pos) /*!< 0x00000020 */
+#define I2C_CR1_ENPEC I2C_CR1_ENPEC_Msk /*!< PEC Enable */
+#define I2C_CR1_ENGC_Pos (6U)
+#define I2C_CR1_ENGC_Msk (0x1U << I2C_CR1_ENGC_Pos) /*!< 0x00000040 */
+#define I2C_CR1_ENGC I2C_CR1_ENGC_Msk /*!< General Call Enable */
+#define I2C_CR1_NOSTRETCH_Pos (7U)
+#define I2C_CR1_NOSTRETCH_Msk (0x1U << I2C_CR1_NOSTRETCH_Pos) /*!< 0x00000080 */
+#define I2C_CR1_NOSTRETCH I2C_CR1_NOSTRETCH_Msk /*!< Clock Stretching Disable (Slave mode) */
+#define I2C_CR1_START_Pos (8U)
+#define I2C_CR1_START_Msk (0x1U << I2C_CR1_START_Pos) /*!< 0x00000100 */
+#define I2C_CR1_START I2C_CR1_START_Msk /*!< Start Generation */
+#define I2C_CR1_STOP_Pos (9U)
+#define I2C_CR1_STOP_Msk (0x1U << I2C_CR1_STOP_Pos) /*!< 0x00000200 */
+#define I2C_CR1_STOP I2C_CR1_STOP_Msk /*!< Stop Generation */
+#define I2C_CR1_ACK_Pos (10U)
+#define I2C_CR1_ACK_Msk (0x1U << I2C_CR1_ACK_Pos) /*!< 0x00000400 */
+#define I2C_CR1_ACK I2C_CR1_ACK_Msk /*!< Acknowledge Enable */
+#define I2C_CR1_POS_Pos (11U)
+#define I2C_CR1_POS_Msk (0x1U << I2C_CR1_POS_Pos) /*!< 0x00000800 */
+#define I2C_CR1_POS I2C_CR1_POS_Msk /*!< Acknowledge/PEC Position (for data reception) */
+#define I2C_CR1_PEC_Pos (12U)
+#define I2C_CR1_PEC_Msk (0x1U << I2C_CR1_PEC_Pos) /*!< 0x00001000 */
+#define I2C_CR1_PEC I2C_CR1_PEC_Msk /*!< Packet Error Checking */
+#define I2C_CR1_ALERT_Pos (13U)
+#define I2C_CR1_ALERT_Msk (0x1U << I2C_CR1_ALERT_Pos) /*!< 0x00002000 */
+#define I2C_CR1_ALERT I2C_CR1_ALERT_Msk /*!< SMBus Alert */
+#define I2C_CR1_SWRST_Pos (15U)
+#define I2C_CR1_SWRST_Msk (0x1U << I2C_CR1_SWRST_Pos) /*!< 0x00008000 */
+#define I2C_CR1_SWRST I2C_CR1_SWRST_Msk /*!< Software Reset */
+
+/******************* Bit definition for I2C_CR2 register ********************/
+#define I2C_CR2_FREQ_Pos (0U)
+#define I2C_CR2_FREQ_Msk (0x3FU << I2C_CR2_FREQ_Pos) /*!< 0x0000003F */
+#define I2C_CR2_FREQ I2C_CR2_FREQ_Msk /*!< FREQ[5:0] bits (Peripheral Clock Frequency) */
+#define I2C_CR2_FREQ_0 (0x01U << I2C_CR2_FREQ_Pos) /*!< 0x00000001 */
+#define I2C_CR2_FREQ_1 (0x02U << I2C_CR2_FREQ_Pos) /*!< 0x00000002 */
+#define I2C_CR2_FREQ_2 (0x04U << I2C_CR2_FREQ_Pos) /*!< 0x00000004 */
+#define I2C_CR2_FREQ_3 (0x08U << I2C_CR2_FREQ_Pos) /*!< 0x00000008 */
+#define I2C_CR2_FREQ_4 (0x10U << I2C_CR2_FREQ_Pos) /*!< 0x00000010 */
+#define I2C_CR2_FREQ_5 (0x20U << I2C_CR2_FREQ_Pos) /*!< 0x00000020 */
+
+#define I2C_CR2_ITERREN_Pos (8U)
+#define I2C_CR2_ITERREN_Msk (0x1U << I2C_CR2_ITERREN_Pos) /*!< 0x00000100 */
+#define I2C_CR2_ITERREN I2C_CR2_ITERREN_Msk /*!< Error Interrupt Enable */
+#define I2C_CR2_ITEVTEN_Pos (9U)
+#define I2C_CR2_ITEVTEN_Msk (0x1U << I2C_CR2_ITEVTEN_Pos) /*!< 0x00000200 */
+#define I2C_CR2_ITEVTEN I2C_CR2_ITEVTEN_Msk /*!< Event Interrupt Enable */
+#define I2C_CR2_ITBUFEN_Pos (10U)
+#define I2C_CR2_ITBUFEN_Msk (0x1U << I2C_CR2_ITBUFEN_Pos) /*!< 0x00000400 */
+#define I2C_CR2_ITBUFEN I2C_CR2_ITBUFEN_Msk /*!< Buffer Interrupt Enable */
+#define I2C_CR2_DMAEN_Pos (11U)
+#define I2C_CR2_DMAEN_Msk (0x1U << I2C_CR2_DMAEN_Pos) /*!< 0x00000800 */
+#define I2C_CR2_DMAEN I2C_CR2_DMAEN_Msk /*!< DMA Requests Enable */
+#define I2C_CR2_LAST_Pos (12U)
+#define I2C_CR2_LAST_Msk (0x1U << I2C_CR2_LAST_Pos) /*!< 0x00001000 */
+#define I2C_CR2_LAST I2C_CR2_LAST_Msk /*!< DMA Last Transfer */
+
+/******************* Bit definition for I2C_OAR1 register *******************/
+#define I2C_OAR1_ADD1_7 ((uint32_t)0x000000FE) /*!< Interface Address */
+#define I2C_OAR1_ADD8_9 ((uint32_t)0x00000300) /*!< Interface Address */
+
+#define I2C_OAR1_ADD0_Pos (0U)
+#define I2C_OAR1_ADD0_Msk (0x1U << I2C_OAR1_ADD0_Pos) /*!< 0x00000001 */
+#define I2C_OAR1_ADD0 I2C_OAR1_ADD0_Msk /*!< Bit 0 */
+#define I2C_OAR1_ADD1_Pos (1U)
+#define I2C_OAR1_ADD1_Msk (0x1U << I2C_OAR1_ADD1_Pos) /*!< 0x00000002 */
+#define I2C_OAR1_ADD1 I2C_OAR1_ADD1_Msk /*!< Bit 1 */
+#define I2C_OAR1_ADD2_Pos (2U)
+#define I2C_OAR1_ADD2_Msk (0x1U << I2C_OAR1_ADD2_Pos) /*!< 0x00000004 */
+#define I2C_OAR1_ADD2 I2C_OAR1_ADD2_Msk /*!< Bit 2 */
+#define I2C_OAR1_ADD3_Pos (3U)
+#define I2C_OAR1_ADD3_Msk (0x1U << I2C_OAR1_ADD3_Pos) /*!< 0x00000008 */
+#define I2C_OAR1_ADD3 I2C_OAR1_ADD3_Msk /*!< Bit 3 */
+#define I2C_OAR1_ADD4_Pos (4U)
+#define I2C_OAR1_ADD4_Msk (0x1U << I2C_OAR1_ADD4_Pos) /*!< 0x00000010 */
+#define I2C_OAR1_ADD4 I2C_OAR1_ADD4_Msk /*!< Bit 4 */
+#define I2C_OAR1_ADD5_Pos (5U)
+#define I2C_OAR1_ADD5_Msk (0x1U << I2C_OAR1_ADD5_Pos) /*!< 0x00000020 */
+#define I2C_OAR1_ADD5 I2C_OAR1_ADD5_Msk /*!< Bit 5 */
+#define I2C_OAR1_ADD6_Pos (6U)
+#define I2C_OAR1_ADD6_Msk (0x1U << I2C_OAR1_ADD6_Pos) /*!< 0x00000040 */
+#define I2C_OAR1_ADD6 I2C_OAR1_ADD6_Msk /*!< Bit 6 */
+#define I2C_OAR1_ADD7_Pos (7U)
+#define I2C_OAR1_ADD7_Msk (0x1U << I2C_OAR1_ADD7_Pos) /*!< 0x00000080 */
+#define I2C_OAR1_ADD7 I2C_OAR1_ADD7_Msk /*!< Bit 7 */
+#define I2C_OAR1_ADD8_Pos (8U)
+#define I2C_OAR1_ADD8_Msk (0x1U << I2C_OAR1_ADD8_Pos) /*!< 0x00000100 */
+#define I2C_OAR1_ADD8 I2C_OAR1_ADD8_Msk /*!< Bit 8 */
+#define I2C_OAR1_ADD9_Pos (9U)
+#define I2C_OAR1_ADD9_Msk (0x1U << I2C_OAR1_ADD9_Pos) /*!< 0x00000200 */
+#define I2C_OAR1_ADD9 I2C_OAR1_ADD9_Msk /*!< Bit 9 */
+
+#define I2C_OAR1_ADDMODE_Pos (15U)
+#define I2C_OAR1_ADDMODE_Msk (0x1U << I2C_OAR1_ADDMODE_Pos) /*!< 0x00008000 */
+#define I2C_OAR1_ADDMODE I2C_OAR1_ADDMODE_Msk /*!< Addressing Mode (Slave mode) */
+
+/******************* Bit definition for I2C_OAR2 register *******************/
+#define I2C_OAR2_ENDUAL_Pos (0U)
+#define I2C_OAR2_ENDUAL_Msk (0x1U << I2C_OAR2_ENDUAL_Pos) /*!< 0x00000001 */
+#define I2C_OAR2_ENDUAL I2C_OAR2_ENDUAL_Msk /*!< Dual addressing mode enable */
+#define I2C_OAR2_ADD2_Pos (1U)
+#define I2C_OAR2_ADD2_Msk (0x7FU << I2C_OAR2_ADD2_Pos) /*!< 0x000000FE */
+#define I2C_OAR2_ADD2 I2C_OAR2_ADD2_Msk /*!< Interface address */
+
+/******************* Bit definition for I2C_SR1 register ********************/
+#define I2C_SR1_SB_Pos (0U)
+#define I2C_SR1_SB_Msk (0x1U << I2C_SR1_SB_Pos) /*!< 0x00000001 */
+#define I2C_SR1_SB I2C_SR1_SB_Msk /*!< Start Bit (Master mode) */
+#define I2C_SR1_ADDR_Pos (1U)
+#define I2C_SR1_ADDR_Msk (0x1U << I2C_SR1_ADDR_Pos) /*!< 0x00000002 */
+#define I2C_SR1_ADDR I2C_SR1_ADDR_Msk /*!< Address sent (master mode)/matched (slave mode) */
+#define I2C_SR1_BTF_Pos (2U)
+#define I2C_SR1_BTF_Msk (0x1U << I2C_SR1_BTF_Pos) /*!< 0x00000004 */
+#define I2C_SR1_BTF I2C_SR1_BTF_Msk /*!< Byte Transfer Finished */
+#define I2C_SR1_ADD10_Pos (3U)
+#define I2C_SR1_ADD10_Msk (0x1U << I2C_SR1_ADD10_Pos) /*!< 0x00000008 */
+#define I2C_SR1_ADD10 I2C_SR1_ADD10_Msk /*!< 10-bit header sent (Master mode) */
+#define I2C_SR1_STOPF_Pos (4U)
+#define I2C_SR1_STOPF_Msk (0x1U << I2C_SR1_STOPF_Pos) /*!< 0x00000010 */
+#define I2C_SR1_STOPF I2C_SR1_STOPF_Msk /*!< Stop detection (Slave mode) */
+#define I2C_SR1_RXNE_Pos (6U)
+#define I2C_SR1_RXNE_Msk (0x1U << I2C_SR1_RXNE_Pos) /*!< 0x00000040 */
+#define I2C_SR1_RXNE I2C_SR1_RXNE_Msk /*!< Data Register not Empty (receivers) */
+#define I2C_SR1_TXE_Pos (7U)
+#define I2C_SR1_TXE_Msk (0x1U << I2C_SR1_TXE_Pos) /*!< 0x00000080 */
+#define I2C_SR1_TXE I2C_SR1_TXE_Msk /*!< Data Register Empty (transmitters) */
+#define I2C_SR1_BERR_Pos (8U)
+#define I2C_SR1_BERR_Msk (0x1U << I2C_SR1_BERR_Pos) /*!< 0x00000100 */
+#define I2C_SR1_BERR I2C_SR1_BERR_Msk /*!< Bus Error */
+#define I2C_SR1_ARLO_Pos (9U)
+#define I2C_SR1_ARLO_Msk (0x1U << I2C_SR1_ARLO_Pos) /*!< 0x00000200 */
+#define I2C_SR1_ARLO I2C_SR1_ARLO_Msk /*!< Arbitration Lost (master mode) */
+#define I2C_SR1_AF_Pos (10U)
+#define I2C_SR1_AF_Msk (0x1U << I2C_SR1_AF_Pos) /*!< 0x00000400 */
+#define I2C_SR1_AF I2C_SR1_AF_Msk /*!< Acknowledge Failure */
+#define I2C_SR1_OVR_Pos (11U)
+#define I2C_SR1_OVR_Msk (0x1U << I2C_SR1_OVR_Pos) /*!< 0x00000800 */
+#define I2C_SR1_OVR I2C_SR1_OVR_Msk /*!< Overrun/Underrun */
+#define I2C_SR1_PECERR_Pos (12U)
+#define I2C_SR1_PECERR_Msk (0x1U << I2C_SR1_PECERR_Pos) /*!< 0x00001000 */
+#define I2C_SR1_PECERR I2C_SR1_PECERR_Msk /*!< PEC Error in reception */
+#define I2C_SR1_TIMEOUT_Pos (14U)
+#define I2C_SR1_TIMEOUT_Msk (0x1U << I2C_SR1_TIMEOUT_Pos) /*!< 0x00004000 */
+#define I2C_SR1_TIMEOUT I2C_SR1_TIMEOUT_Msk /*!< Timeout or Tlow Error */
+#define I2C_SR1_SMBALERT_Pos (15U)
+#define I2C_SR1_SMBALERT_Msk (0x1U << I2C_SR1_SMBALERT_Pos) /*!< 0x00008000 */
+#define I2C_SR1_SMBALERT I2C_SR1_SMBALERT_Msk /*!< SMBus Alert */
+
+/******************* Bit definition for I2C_SR2 register ********************/
+#define I2C_SR2_MSL_Pos (0U)
+#define I2C_SR2_MSL_Msk (0x1U << I2C_SR2_MSL_Pos) /*!< 0x00000001 */
+#define I2C_SR2_MSL I2C_SR2_MSL_Msk /*!< Master/Slave */
+#define I2C_SR2_BUSY_Pos (1U)
+#define I2C_SR2_BUSY_Msk (0x1U << I2C_SR2_BUSY_Pos) /*!< 0x00000002 */
+#define I2C_SR2_BUSY I2C_SR2_BUSY_Msk /*!< Bus Busy */
+#define I2C_SR2_TRA_Pos (2U)
+#define I2C_SR2_TRA_Msk (0x1U << I2C_SR2_TRA_Pos) /*!< 0x00000004 */
+#define I2C_SR2_TRA I2C_SR2_TRA_Msk /*!< Transmitter/Receiver */
+#define I2C_SR2_GENCALL_Pos (4U)
+#define I2C_SR2_GENCALL_Msk (0x1U << I2C_SR2_GENCALL_Pos) /*!< 0x00000010 */
+#define I2C_SR2_GENCALL I2C_SR2_GENCALL_Msk /*!< General Call Address (Slave mode) */
+#define I2C_SR2_SMBDEFAULT_Pos (5U)
+#define I2C_SR2_SMBDEFAULT_Msk (0x1U << I2C_SR2_SMBDEFAULT_Pos) /*!< 0x00000020 */
+#define I2C_SR2_SMBDEFAULT I2C_SR2_SMBDEFAULT_Msk /*!< SMBus Device Default Address (Slave mode) */
+#define I2C_SR2_SMBHOST_Pos (6U)
+#define I2C_SR2_SMBHOST_Msk (0x1U << I2C_SR2_SMBHOST_Pos) /*!< 0x00000040 */
+#define I2C_SR2_SMBHOST I2C_SR2_SMBHOST_Msk /*!< SMBus Host Header (Slave mode) */
+#define I2C_SR2_DUALF_Pos (7U)
+#define I2C_SR2_DUALF_Msk (0x1U << I2C_SR2_DUALF_Pos) /*!< 0x00000080 */
+#define I2C_SR2_DUALF I2C_SR2_DUALF_Msk /*!< Dual Flag (Slave mode) */
+#define I2C_SR2_PEC_Pos (8U)
+#define I2C_SR2_PEC_Msk (0xFFU << I2C_SR2_PEC_Pos) /*!< 0x0000FF00 */
+#define I2C_SR2_PEC I2C_SR2_PEC_Msk /*!< Packet Error Checking Register */
+
+/******************* Bit definition for I2C_CCR register ********************/
+#define I2C_CCR_CCR_Pos (0U)
+#define I2C_CCR_CCR_Msk (0xFFFU << I2C_CCR_CCR_Pos) /*!< 0x00000FFF */
+#define I2C_CCR_CCR I2C_CCR_CCR_Msk /*!< Clock Control Register in Fast/Standard mode (Master mode) */
+#define I2C_CCR_DUTY_Pos (14U)
+#define I2C_CCR_DUTY_Msk (0x1U << I2C_CCR_DUTY_Pos) /*!< 0x00004000 */
+#define I2C_CCR_DUTY I2C_CCR_DUTY_Msk /*!< Fast Mode Duty Cycle */
+#define I2C_CCR_FS_Pos (15U)
+#define I2C_CCR_FS_Msk (0x1U << I2C_CCR_FS_Pos) /*!< 0x00008000 */
+#define I2C_CCR_FS I2C_CCR_FS_Msk /*!< I2C Master Mode Selection */
+
+/****************** Bit definition for I2C_TRISE register *******************/
+#define I2C_TRISE_TRISE_Pos (0U)
+#define I2C_TRISE_TRISE_Msk (0x3FU << I2C_TRISE_TRISE_Pos) /*!< 0x0000003F */
+#define I2C_TRISE_TRISE I2C_TRISE_TRISE_Msk /*!< Maximum Rise Time in Fast/Standard mode (Master mode) */
+
+/******************************************************************************/
+/* */
+/* Universal Synchronous Asynchronous Receiver Transmitter */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for USART_SR register *******************/
+#define USART_SR_PE_Pos (0U)
+#define USART_SR_PE_Msk (0x1U << USART_SR_PE_Pos) /*!< 0x00000001 */
+#define USART_SR_PE USART_SR_PE_Msk /*!< Parity Error */
+#define USART_SR_FE_Pos (1U)
+#define USART_SR_FE_Msk (0x1U << USART_SR_FE_Pos) /*!< 0x00000002 */
+#define USART_SR_FE USART_SR_FE_Msk /*!< Framing Error */
+#define USART_SR_NE_Pos (2U)
+#define USART_SR_NE_Msk (0x1U << USART_SR_NE_Pos) /*!< 0x00000004 */
+#define USART_SR_NE USART_SR_NE_Msk /*!< Noise Error Flag */
+#define USART_SR_ORE_Pos (3U)
+#define USART_SR_ORE_Msk (0x1U << USART_SR_ORE_Pos) /*!< 0x00000008 */
+#define USART_SR_ORE USART_SR_ORE_Msk /*!< OverRun Error */
+#define USART_SR_IDLE_Pos (4U)
+#define USART_SR_IDLE_Msk (0x1U << USART_SR_IDLE_Pos) /*!< 0x00000010 */
+#define USART_SR_IDLE USART_SR_IDLE_Msk /*!< IDLE line detected */
+#define USART_SR_RXNE_Pos (5U)
+#define USART_SR_RXNE_Msk (0x1U << USART_SR_RXNE_Pos) /*!< 0x00000020 */
+#define USART_SR_RXNE USART_SR_RXNE_Msk /*!< Read Data Register Not Empty */
+#define USART_SR_TC_Pos (6U)
+#define USART_SR_TC_Msk (0x1U << USART_SR_TC_Pos) /*!< 0x00000040 */
+#define USART_SR_TC USART_SR_TC_Msk /*!< Transmission Complete */
+#define USART_SR_TXE_Pos (7U)
+#define USART_SR_TXE_Msk (0x1U << USART_SR_TXE_Pos) /*!< 0x00000080 */
+#define USART_SR_TXE USART_SR_TXE_Msk /*!< Transmit Data Register Empty */
+#define USART_SR_LBD_Pos (8U)
+#define USART_SR_LBD_Msk (0x1U << USART_SR_LBD_Pos) /*!< 0x00000100 */
+#define USART_SR_LBD USART_SR_LBD_Msk /*!< LIN Break Detection Flag */
+#define USART_SR_CTS_Pos (9U)
+#define USART_SR_CTS_Msk (0x1U << USART_SR_CTS_Pos) /*!< 0x00000200 */
+#define USART_SR_CTS USART_SR_CTS_Msk /*!< CTS Flag */
+
+/******************* Bit definition for USART_DR register *******************/
+#define USART_DR_DR_Pos (0U)
+#define USART_DR_DR_Msk (0x1FFU << USART_DR_DR_Pos) /*!< 0x000001FF */
+#define USART_DR_DR USART_DR_DR_Msk /*!< Data value */
+
+/****************** Bit definition for USART_BRR register *******************/
+#define USART_BRR_DIV_Fraction_Pos (0U)
+#define USART_BRR_DIV_Fraction_Msk (0xFU << USART_BRR_DIV_Fraction_Pos) /*!< 0x0000000F */
+#define USART_BRR_DIV_Fraction USART_BRR_DIV_Fraction_Msk /*!< Fraction of USARTDIV */
+#define USART_BRR_DIV_Mantissa_Pos (4U)
+#define USART_BRR_DIV_Mantissa_Msk (0xFFFU << USART_BRR_DIV_Mantissa_Pos) /*!< 0x0000FFF0 */
+#define USART_BRR_DIV_Mantissa USART_BRR_DIV_Mantissa_Msk /*!< Mantissa of USARTDIV */
+
+/****************** Bit definition for USART_CR1 register *******************/
+#define USART_CR1_SBK_Pos (0U)
+#define USART_CR1_SBK_Msk (0x1U << USART_CR1_SBK_Pos) /*!< 0x00000001 */
+#define USART_CR1_SBK USART_CR1_SBK_Msk /*!< Send Break */
+#define USART_CR1_RWU_Pos (1U)
+#define USART_CR1_RWU_Msk (0x1U << USART_CR1_RWU_Pos) /*!< 0x00000002 */
+#define USART_CR1_RWU USART_CR1_RWU_Msk /*!< Receiver wakeup */
+#define USART_CR1_RE_Pos (2U)
+#define USART_CR1_RE_Msk (0x1U << USART_CR1_RE_Pos) /*!< 0x00000004 */
+#define USART_CR1_RE USART_CR1_RE_Msk /*!< Receiver Enable */
+#define USART_CR1_TE_Pos (3U)
+#define USART_CR1_TE_Msk (0x1U << USART_CR1_TE_Pos) /*!< 0x00000008 */
+#define USART_CR1_TE USART_CR1_TE_Msk /*!< Transmitter Enable */
+#define USART_CR1_IDLEIE_Pos (4U)
+#define USART_CR1_IDLEIE_Msk (0x1U << USART_CR1_IDLEIE_Pos) /*!< 0x00000010 */
+#define USART_CR1_IDLEIE USART_CR1_IDLEIE_Msk /*!< IDLE Interrupt Enable */
+#define USART_CR1_RXNEIE_Pos (5U)
+#define USART_CR1_RXNEIE_Msk (0x1U << USART_CR1_RXNEIE_Pos) /*!< 0x00000020 */
+#define USART_CR1_RXNEIE USART_CR1_RXNEIE_Msk /*!< RXNE Interrupt Enable */
+#define USART_CR1_TCIE_Pos (6U)
+#define USART_CR1_TCIE_Msk (0x1U << USART_CR1_TCIE_Pos) /*!< 0x00000040 */
+#define USART_CR1_TCIE USART_CR1_TCIE_Msk /*!< Transmission Complete Interrupt Enable */
+#define USART_CR1_TXEIE_Pos (7U)
+#define USART_CR1_TXEIE_Msk (0x1U << USART_CR1_TXEIE_Pos) /*!< 0x00000080 */
+#define USART_CR1_TXEIE USART_CR1_TXEIE_Msk /*!< PE Interrupt Enable */
+#define USART_CR1_PEIE_Pos (8U)
+#define USART_CR1_PEIE_Msk (0x1U << USART_CR1_PEIE_Pos) /*!< 0x00000100 */
+#define USART_CR1_PEIE USART_CR1_PEIE_Msk /*!< PE Interrupt Enable */
+#define USART_CR1_PS_Pos (9U)
+#define USART_CR1_PS_Msk (0x1U << USART_CR1_PS_Pos) /*!< 0x00000200 */
+#define USART_CR1_PS USART_CR1_PS_Msk /*!< Parity Selection */
+#define USART_CR1_PCE_Pos (10U)
+#define USART_CR1_PCE_Msk (0x1U << USART_CR1_PCE_Pos) /*!< 0x00000400 */
+#define USART_CR1_PCE USART_CR1_PCE_Msk /*!< Parity Control Enable */
+#define USART_CR1_WAKE_Pos (11U)
+#define USART_CR1_WAKE_Msk (0x1U << USART_CR1_WAKE_Pos) /*!< 0x00000800 */
+#define USART_CR1_WAKE USART_CR1_WAKE_Msk /*!< Wakeup method */
+#define USART_CR1_M_Pos (12U)
+#define USART_CR1_M_Msk (0x1U << USART_CR1_M_Pos) /*!< 0x00001000 */
+#define USART_CR1_M USART_CR1_M_Msk /*!< Word length */
+#define USART_CR1_UE_Pos (13U)
+#define USART_CR1_UE_Msk (0x1U << USART_CR1_UE_Pos) /*!< 0x00002000 */
+#define USART_CR1_UE USART_CR1_UE_Msk /*!< USART Enable */
+
+/****************** Bit definition for USART_CR2 register *******************/
+#define USART_CR2_ADD_Pos (0U)
+#define USART_CR2_ADD_Msk (0xFU << USART_CR2_ADD_Pos) /*!< 0x0000000F */
+#define USART_CR2_ADD USART_CR2_ADD_Msk /*!< Address of the USART node */
+#define USART_CR2_LBDL_Pos (5U)
+#define USART_CR2_LBDL_Msk (0x1U << USART_CR2_LBDL_Pos) /*!< 0x00000020 */
+#define USART_CR2_LBDL USART_CR2_LBDL_Msk /*!< LIN Break Detection Length */
+#define USART_CR2_LBDIE_Pos (6U)
+#define USART_CR2_LBDIE_Msk (0x1U << USART_CR2_LBDIE_Pos) /*!< 0x00000040 */
+#define USART_CR2_LBDIE USART_CR2_LBDIE_Msk /*!< LIN Break Detection Interrupt Enable */
+#define USART_CR2_LBCL_Pos (8U)
+#define USART_CR2_LBCL_Msk (0x1U << USART_CR2_LBCL_Pos) /*!< 0x00000100 */
+#define USART_CR2_LBCL USART_CR2_LBCL_Msk /*!< Last Bit Clock pulse */
+#define USART_CR2_CPHA_Pos (9U)
+#define USART_CR2_CPHA_Msk (0x1U << USART_CR2_CPHA_Pos) /*!< 0x00000200 */
+#define USART_CR2_CPHA USART_CR2_CPHA_Msk /*!< Clock Phase */
+#define USART_CR2_CPOL_Pos (10U)
+#define USART_CR2_CPOL_Msk (0x1U << USART_CR2_CPOL_Pos) /*!< 0x00000400 */
+#define USART_CR2_CPOL USART_CR2_CPOL_Msk /*!< Clock Polarity */
+#define USART_CR2_CLKEN_Pos (11U)
+#define USART_CR2_CLKEN_Msk (0x1U << USART_CR2_CLKEN_Pos) /*!< 0x00000800 */
+#define USART_CR2_CLKEN USART_CR2_CLKEN_Msk /*!< Clock Enable */
+
+#define USART_CR2_STOP_Pos (12U)
+#define USART_CR2_STOP_Msk (0x3U << USART_CR2_STOP_Pos) /*!< 0x00003000 */
+#define USART_CR2_STOP USART_CR2_STOP_Msk /*!< STOP[1:0] bits (STOP bits) */
+#define USART_CR2_STOP_0 (0x1U << USART_CR2_STOP_Pos) /*!< 0x00001000 */
+#define USART_CR2_STOP_1 (0x2U << USART_CR2_STOP_Pos) /*!< 0x00002000 */
+
+#define USART_CR2_LINEN_Pos (14U)
+#define USART_CR2_LINEN_Msk (0x1U << USART_CR2_LINEN_Pos) /*!< 0x00004000 */
+#define USART_CR2_LINEN USART_CR2_LINEN_Msk /*!< LIN mode enable */
+
+/****************** Bit definition for USART_CR3 register *******************/
+#define USART_CR3_EIE_Pos (0U)
+#define USART_CR3_EIE_Msk (0x1U << USART_CR3_EIE_Pos) /*!< 0x00000001 */
+#define USART_CR3_EIE USART_CR3_EIE_Msk /*!< Error Interrupt Enable */
+#define USART_CR3_IREN_Pos (1U)
+#define USART_CR3_IREN_Msk (0x1U << USART_CR3_IREN_Pos) /*!< 0x00000002 */
+#define USART_CR3_IREN USART_CR3_IREN_Msk /*!< IrDA mode Enable */
+#define USART_CR3_IRLP_Pos (2U)
+#define USART_CR3_IRLP_Msk (0x1U << USART_CR3_IRLP_Pos) /*!< 0x00000004 */
+#define USART_CR3_IRLP USART_CR3_IRLP_Msk /*!< IrDA Low-Power */
+#define USART_CR3_HDSEL_Pos (3U)
+#define USART_CR3_HDSEL_Msk (0x1U << USART_CR3_HDSEL_Pos) /*!< 0x00000008 */
+#define USART_CR3_HDSEL USART_CR3_HDSEL_Msk /*!< Half-Duplex Selection */
+#define USART_CR3_NACK_Pos (4U)
+#define USART_CR3_NACK_Msk (0x1U << USART_CR3_NACK_Pos) /*!< 0x00000010 */
+#define USART_CR3_NACK USART_CR3_NACK_Msk /*!< Smartcard NACK enable */
+#define USART_CR3_SCEN_Pos (5U)
+#define USART_CR3_SCEN_Msk (0x1U << USART_CR3_SCEN_Pos) /*!< 0x00000020 */
+#define USART_CR3_SCEN USART_CR3_SCEN_Msk /*!< Smartcard mode enable */
+#define USART_CR3_DMAR_Pos (6U)
+#define USART_CR3_DMAR_Msk (0x1U << USART_CR3_DMAR_Pos) /*!< 0x00000040 */
+#define USART_CR3_DMAR USART_CR3_DMAR_Msk /*!< DMA Enable Receiver */
+#define USART_CR3_DMAT_Pos (7U)
+#define USART_CR3_DMAT_Msk (0x1U << USART_CR3_DMAT_Pos) /*!< 0x00000080 */
+#define USART_CR3_DMAT USART_CR3_DMAT_Msk /*!< DMA Enable Transmitter */
+#define USART_CR3_RTSE_Pos (8U)
+#define USART_CR3_RTSE_Msk (0x1U << USART_CR3_RTSE_Pos) /*!< 0x00000100 */
+#define USART_CR3_RTSE USART_CR3_RTSE_Msk /*!< RTS Enable */
+#define USART_CR3_CTSE_Pos (9U)
+#define USART_CR3_CTSE_Msk (0x1U << USART_CR3_CTSE_Pos) /*!< 0x00000200 */
+#define USART_CR3_CTSE USART_CR3_CTSE_Msk /*!< CTS Enable */
+#define USART_CR3_CTSIE_Pos (10U)
+#define USART_CR3_CTSIE_Msk (0x1U << USART_CR3_CTSIE_Pos) /*!< 0x00000400 */
+#define USART_CR3_CTSIE USART_CR3_CTSIE_Msk /*!< CTS Interrupt Enable */
+
+/****************** Bit definition for USART_GTPR register ******************/
+#define USART_GTPR_PSC_Pos (0U)
+#define USART_GTPR_PSC_Msk (0xFFU << USART_GTPR_PSC_Pos) /*!< 0x000000FF */
+#define USART_GTPR_PSC USART_GTPR_PSC_Msk /*!< PSC[7:0] bits (Prescaler value) */
+#define USART_GTPR_PSC_0 (0x01U << USART_GTPR_PSC_Pos) /*!< 0x00000001 */
+#define USART_GTPR_PSC_1 (0x02U << USART_GTPR_PSC_Pos) /*!< 0x00000002 */
+#define USART_GTPR_PSC_2 (0x04U << USART_GTPR_PSC_Pos) /*!< 0x00000004 */
+#define USART_GTPR_PSC_3 (0x08U << USART_GTPR_PSC_Pos) /*!< 0x00000008 */
+#define USART_GTPR_PSC_4 (0x10U << USART_GTPR_PSC_Pos) /*!< 0x00000010 */
+#define USART_GTPR_PSC_5 (0x20U << USART_GTPR_PSC_Pos) /*!< 0x00000020 */
+#define USART_GTPR_PSC_6 (0x40U << USART_GTPR_PSC_Pos) /*!< 0x00000040 */
+#define USART_GTPR_PSC_7 (0x80U << USART_GTPR_PSC_Pos) /*!< 0x00000080 */
+
+#define USART_GTPR_GT_Pos (8U)
+#define USART_GTPR_GT_Msk (0xFFU << USART_GTPR_GT_Pos) /*!< 0x0000FF00 */
+#define USART_GTPR_GT USART_GTPR_GT_Msk /*!< Guard time value */
+
+/******************************************************************************/
+/* */
+/* Debug MCU */
+/* */
+/******************************************************************************/
+
+/**************** Bit definition for DBGMCU_IDCODE register *****************/
+#define DBGMCU_IDCODE_DEV_ID_Pos (0U)
+#define DBGMCU_IDCODE_DEV_ID_Msk (0xFFFU << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */
+#define DBGMCU_IDCODE_DEV_ID DBGMCU_IDCODE_DEV_ID_Msk /*!< Device Identifier */
+
+#define DBGMCU_IDCODE_REV_ID_Pos (16U)
+#define DBGMCU_IDCODE_REV_ID_Msk (0xFFFFU << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */
+#define DBGMCU_IDCODE_REV_ID DBGMCU_IDCODE_REV_ID_Msk /*!< REV_ID[15:0] bits (Revision Identifier) */
+#define DBGMCU_IDCODE_REV_ID_0 (0x0001U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00010000 */
+#define DBGMCU_IDCODE_REV_ID_1 (0x0002U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00020000 */
+#define DBGMCU_IDCODE_REV_ID_2 (0x0004U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00040000 */
+#define DBGMCU_IDCODE_REV_ID_3 (0x0008U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00080000 */
+#define DBGMCU_IDCODE_REV_ID_4 (0x0010U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00100000 */
+#define DBGMCU_IDCODE_REV_ID_5 (0x0020U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00200000 */
+#define DBGMCU_IDCODE_REV_ID_6 (0x0040U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00400000 */
+#define DBGMCU_IDCODE_REV_ID_7 (0x0080U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00800000 */
+#define DBGMCU_IDCODE_REV_ID_8 (0x0100U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x01000000 */
+#define DBGMCU_IDCODE_REV_ID_9 (0x0200U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x02000000 */
+#define DBGMCU_IDCODE_REV_ID_10 (0x0400U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x04000000 */
+#define DBGMCU_IDCODE_REV_ID_11 (0x0800U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x08000000 */
+#define DBGMCU_IDCODE_REV_ID_12 (0x1000U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x10000000 */
+#define DBGMCU_IDCODE_REV_ID_13 (0x2000U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x20000000 */
+#define DBGMCU_IDCODE_REV_ID_14 (0x4000U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x40000000 */
+#define DBGMCU_IDCODE_REV_ID_15 (0x8000U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x80000000 */
+
+/****************** Bit definition for DBGMCU_CR register *******************/
+#define DBGMCU_CR_DBG_SLEEP_Pos (0U)
+#define DBGMCU_CR_DBG_SLEEP_Msk (0x1U << DBGMCU_CR_DBG_SLEEP_Pos) /*!< 0x00000001 */
+#define DBGMCU_CR_DBG_SLEEP DBGMCU_CR_DBG_SLEEP_Msk /*!< Debug Sleep Mode */
+#define DBGMCU_CR_DBG_STOP_Pos (1U)
+#define DBGMCU_CR_DBG_STOP_Msk (0x1U << DBGMCU_CR_DBG_STOP_Pos) /*!< 0x00000002 */
+#define DBGMCU_CR_DBG_STOP DBGMCU_CR_DBG_STOP_Msk /*!< Debug Stop Mode */
+#define DBGMCU_CR_DBG_STANDBY_Pos (2U)
+#define DBGMCU_CR_DBG_STANDBY_Msk (0x1U << DBGMCU_CR_DBG_STANDBY_Pos) /*!< 0x00000004 */
+#define DBGMCU_CR_DBG_STANDBY DBGMCU_CR_DBG_STANDBY_Msk /*!< Debug Standby mode */
+#define DBGMCU_CR_TRACE_IOEN_Pos (5U)
+#define DBGMCU_CR_TRACE_IOEN_Msk (0x1U << DBGMCU_CR_TRACE_IOEN_Pos) /*!< 0x00000020 */
+#define DBGMCU_CR_TRACE_IOEN DBGMCU_CR_TRACE_IOEN_Msk /*!< Trace Pin Assignment Control */
+
+#define DBGMCU_CR_TRACE_MODE_Pos (6U)
+#define DBGMCU_CR_TRACE_MODE_Msk (0x3U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x000000C0 */
+#define DBGMCU_CR_TRACE_MODE DBGMCU_CR_TRACE_MODE_Msk /*!< TRACE_MODE[1:0] bits (Trace Pin Assignment Control) */
+#define DBGMCU_CR_TRACE_MODE_0 (0x1U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000040 */
+#define DBGMCU_CR_TRACE_MODE_1 (0x2U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000080 */
+
+#define DBGMCU_CR_DBG_IWDG_STOP_Pos (8U)
+#define DBGMCU_CR_DBG_IWDG_STOP_Msk (0x1U << DBGMCU_CR_DBG_IWDG_STOP_Pos) /*!< 0x00000100 */
+#define DBGMCU_CR_DBG_IWDG_STOP DBGMCU_CR_DBG_IWDG_STOP_Msk /*!< Debug Independent Watchdog stopped when Core is halted */
+#define DBGMCU_CR_DBG_WWDG_STOP_Pos (9U)
+#define DBGMCU_CR_DBG_WWDG_STOP_Msk (0x1U << DBGMCU_CR_DBG_WWDG_STOP_Pos) /*!< 0x00000200 */
+#define DBGMCU_CR_DBG_WWDG_STOP DBGMCU_CR_DBG_WWDG_STOP_Msk /*!< Debug Window Watchdog stopped when Core is halted */
+#define DBGMCU_CR_DBG_TIM2_STOP_Pos (11U)
+#define DBGMCU_CR_DBG_TIM2_STOP_Msk (0x1U << DBGMCU_CR_DBG_TIM2_STOP_Pos) /*!< 0x00000800 */
+#define DBGMCU_CR_DBG_TIM2_STOP DBGMCU_CR_DBG_TIM2_STOP_Msk /*!< TIM2 counter stopped when core is halted */
+#define DBGMCU_CR_DBG_TIM3_STOP_Pos (12U)
+#define DBGMCU_CR_DBG_TIM3_STOP_Msk (0x1U << DBGMCU_CR_DBG_TIM3_STOP_Pos) /*!< 0x00001000 */
+#define DBGMCU_CR_DBG_TIM3_STOP DBGMCU_CR_DBG_TIM3_STOP_Msk /*!< TIM3 counter stopped when core is halted */
+#define DBGMCU_CR_DBG_TIM4_STOP_Pos (13U)
+#define DBGMCU_CR_DBG_TIM4_STOP_Msk (0x1U << DBGMCU_CR_DBG_TIM4_STOP_Pos) /*!< 0x00002000 */
+#define DBGMCU_CR_DBG_TIM4_STOP DBGMCU_CR_DBG_TIM4_STOP_Msk /*!< TIM4 counter stopped when core is halted */
+#define DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT_Pos (15U)
+#define DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT_Msk (0x1U << DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT_Pos) /*!< 0x00008000 */
+#define DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT_Msk /*!< SMBUS timeout mode stopped when Core is halted */
+#define DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT_Pos (16U)
+#define DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT_Msk (0x1U << DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT_Pos) /*!< 0x00010000 */
+#define DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT_Msk /*!< SMBUS timeout mode stopped when Core is halted */
+
+/******************************************************************************/
+/* */
+/* FLASH and Option Bytes Registers */
+/* */
+/******************************************************************************/
+/******************* Bit definition for FLASH_ACR register ******************/
+#define FLASH_ACR_LATENCY_Pos (0U)
+#define FLASH_ACR_LATENCY_Msk (0x7U << FLASH_ACR_LATENCY_Pos) /*!< 0x00000007 */
+#define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk /*!< LATENCY[2:0] bits (Latency) */
+#define FLASH_ACR_LATENCY_0 (0x1U << FLASH_ACR_LATENCY_Pos) /*!< 0x00000001 */
+#define FLASH_ACR_LATENCY_1 (0x2U << FLASH_ACR_LATENCY_Pos) /*!< 0x00000002 */
+#define FLASH_ACR_LATENCY_2 (0x4U << FLASH_ACR_LATENCY_Pos) /*!< 0x00000004 */
+
+#define FLASH_ACR_HLFCYA_Pos (3U)
+#define FLASH_ACR_HLFCYA_Msk (0x1U << FLASH_ACR_HLFCYA_Pos) /*!< 0x00000008 */
+#define FLASH_ACR_HLFCYA FLASH_ACR_HLFCYA_Msk /*!< Flash Half Cycle Access Enable */
+#define FLASH_ACR_PRFTBE_Pos (4U)
+#define FLASH_ACR_PRFTBE_Msk (0x1U << FLASH_ACR_PRFTBE_Pos) /*!< 0x00000010 */
+#define FLASH_ACR_PRFTBE FLASH_ACR_PRFTBE_Msk /*!< Prefetch Buffer Enable */
+#define FLASH_ACR_PRFTBS_Pos (5U)
+#define FLASH_ACR_PRFTBS_Msk (0x1U << FLASH_ACR_PRFTBS_Pos) /*!< 0x00000020 */
+#define FLASH_ACR_PRFTBS FLASH_ACR_PRFTBS_Msk /*!< Prefetch Buffer Status */
+
+/****************** Bit definition for FLASH_KEYR register ******************/
+#define FLASH_KEYR_FKEYR_Pos (0U)
+#define FLASH_KEYR_FKEYR_Msk (0xFFFFFFFFU << FLASH_KEYR_FKEYR_Pos) /*!< 0xFFFFFFFF */
+#define FLASH_KEYR_FKEYR FLASH_KEYR_FKEYR_Msk /*!< FPEC Key */
+
+#define RDP_KEY_Pos (0U)
+#define RDP_KEY_Msk (0xA5U << RDP_KEY_Pos) /*!< 0x000000A5 */
+#define RDP_KEY RDP_KEY_Msk /*!< RDP Key */
+#define FLASH_KEY1_Pos (0U)
+#define FLASH_KEY1_Msk (0x45670123U << FLASH_KEY1_Pos) /*!< 0x45670123 */
+#define FLASH_KEY1 FLASH_KEY1_Msk /*!< FPEC Key1 */
+#define FLASH_KEY2_Pos (0U)
+#define FLASH_KEY2_Msk (0xCDEF89ABU << FLASH_KEY2_Pos) /*!< 0xCDEF89AB */
+#define FLASH_KEY2 FLASH_KEY2_Msk /*!< FPEC Key2 */
+
+/***************** Bit definition for FLASH_OPTKEYR register ****************/
+#define FLASH_OPTKEYR_OPTKEYR_Pos (0U)
+#define FLASH_OPTKEYR_OPTKEYR_Msk (0xFFFFFFFFU << FLASH_OPTKEYR_OPTKEYR_Pos) /*!< 0xFFFFFFFF */
+#define FLASH_OPTKEYR_OPTKEYR FLASH_OPTKEYR_OPTKEYR_Msk /*!< Option Byte Key */
+
+#define FLASH_OPTKEY1 FLASH_KEY1 /*!< Option Byte Key1 */
+#define FLASH_OPTKEY2 FLASH_KEY2 /*!< Option Byte Key2 */
+
+/****************** Bit definition for FLASH_SR register ********************/
+#define FLASH_SR_BSY_Pos (0U)
+#define FLASH_SR_BSY_Msk (0x1U << FLASH_SR_BSY_Pos) /*!< 0x00000001 */
+#define FLASH_SR_BSY FLASH_SR_BSY_Msk /*!< Busy */
+#define FLASH_SR_PGERR_Pos (2U)
+#define FLASH_SR_PGERR_Msk (0x1U << FLASH_SR_PGERR_Pos) /*!< 0x00000004 */
+#define FLASH_SR_PGERR FLASH_SR_PGERR_Msk /*!< Programming Error */
+#define FLASH_SR_WRPRTERR_Pos (4U)
+#define FLASH_SR_WRPRTERR_Msk (0x1U << FLASH_SR_WRPRTERR_Pos) /*!< 0x00000010 */
+#define FLASH_SR_WRPRTERR FLASH_SR_WRPRTERR_Msk /*!< Write Protection Error */
+#define FLASH_SR_EOP_Pos (5U)
+#define FLASH_SR_EOP_Msk (0x1U << FLASH_SR_EOP_Pos) /*!< 0x00000020 */
+#define FLASH_SR_EOP FLASH_SR_EOP_Msk /*!< End of operation */
+
+/******************* Bit definition for FLASH_CR register *******************/
+#define FLASH_CR_PG_Pos (0U)
+#define FLASH_CR_PG_Msk (0x1U << FLASH_CR_PG_Pos) /*!< 0x00000001 */
+#define FLASH_CR_PG FLASH_CR_PG_Msk /*!< Programming */
+#define FLASH_CR_PER_Pos (1U)
+#define FLASH_CR_PER_Msk (0x1U << FLASH_CR_PER_Pos) /*!< 0x00000002 */
+#define FLASH_CR_PER FLASH_CR_PER_Msk /*!< Page Erase */
+#define FLASH_CR_MER_Pos (2U)
+#define FLASH_CR_MER_Msk (0x1U << FLASH_CR_MER_Pos) /*!< 0x00000004 */
+#define FLASH_CR_MER FLASH_CR_MER_Msk /*!< Mass Erase */
+#define FLASH_CR_OPTPG_Pos (4U)
+#define FLASH_CR_OPTPG_Msk (0x1U << FLASH_CR_OPTPG_Pos) /*!< 0x00000010 */
+#define FLASH_CR_OPTPG FLASH_CR_OPTPG_Msk /*!< Option Byte Programming */
+#define FLASH_CR_OPTER_Pos (5U)
+#define FLASH_CR_OPTER_Msk (0x1U << FLASH_CR_OPTER_Pos) /*!< 0x00000020 */
+#define FLASH_CR_OPTER FLASH_CR_OPTER_Msk /*!< Option Byte Erase */
+#define FLASH_CR_STRT_Pos (6U)
+#define FLASH_CR_STRT_Msk (0x1U << FLASH_CR_STRT_Pos) /*!< 0x00000040 */
+#define FLASH_CR_STRT FLASH_CR_STRT_Msk /*!< Start */
+#define FLASH_CR_LOCK_Pos (7U)
+#define FLASH_CR_LOCK_Msk (0x1U << FLASH_CR_LOCK_Pos) /*!< 0x00000080 */
+#define FLASH_CR_LOCK FLASH_CR_LOCK_Msk /*!< Lock */
+#define FLASH_CR_OPTWRE_Pos (9U)
+#define FLASH_CR_OPTWRE_Msk (0x1U << FLASH_CR_OPTWRE_Pos) /*!< 0x00000200 */
+#define FLASH_CR_OPTWRE FLASH_CR_OPTWRE_Msk /*!< Option Bytes Write Enable */
+#define FLASH_CR_ERRIE_Pos (10U)
+#define FLASH_CR_ERRIE_Msk (0x1U << FLASH_CR_ERRIE_Pos) /*!< 0x00000400 */
+#define FLASH_CR_ERRIE FLASH_CR_ERRIE_Msk /*!< Error Interrupt Enable */
+#define FLASH_CR_EOPIE_Pos (12U)
+#define FLASH_CR_EOPIE_Msk (0x1U << FLASH_CR_EOPIE_Pos) /*!< 0x00001000 */
+#define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk /*!< End of operation interrupt enable */
+
+/******************* Bit definition for FLASH_AR register *******************/
+#define FLASH_AR_FAR_Pos (0U)
+#define FLASH_AR_FAR_Msk (0xFFFFFFFFU << FLASH_AR_FAR_Pos) /*!< 0xFFFFFFFF */
+#define FLASH_AR_FAR FLASH_AR_FAR_Msk /*!< Flash Address */
+
+/****************** Bit definition for FLASH_OBR register *******************/
+#define FLASH_OBR_OPTERR_Pos (0U)
+#define FLASH_OBR_OPTERR_Msk (0x1U << FLASH_OBR_OPTERR_Pos) /*!< 0x00000001 */
+#define FLASH_OBR_OPTERR FLASH_OBR_OPTERR_Msk /*!< Option Byte Error */
+#define FLASH_OBR_RDPRT_Pos (1U)
+#define FLASH_OBR_RDPRT_Msk (0x1U << FLASH_OBR_RDPRT_Pos) /*!< 0x00000002 */
+#define FLASH_OBR_RDPRT FLASH_OBR_RDPRT_Msk /*!< Read protection */
+
+#define FLASH_OBR_IWDG_SW_Pos (2U)
+#define FLASH_OBR_IWDG_SW_Msk (0x1U << FLASH_OBR_IWDG_SW_Pos) /*!< 0x00000004 */
+#define FLASH_OBR_IWDG_SW FLASH_OBR_IWDG_SW_Msk /*!< IWDG SW */
+#define FLASH_OBR_nRST_STOP_Pos (3U)
+#define FLASH_OBR_nRST_STOP_Msk (0x1U << FLASH_OBR_nRST_STOP_Pos) /*!< 0x00000008 */
+#define FLASH_OBR_nRST_STOP FLASH_OBR_nRST_STOP_Msk /*!< nRST_STOP */
+#define FLASH_OBR_nRST_STDBY_Pos (4U)
+#define FLASH_OBR_nRST_STDBY_Msk (0x1U << FLASH_OBR_nRST_STDBY_Pos) /*!< 0x00000010 */
+#define FLASH_OBR_nRST_STDBY FLASH_OBR_nRST_STDBY_Msk /*!< nRST_STDBY */
+#define FLASH_OBR_USER_Pos (2U)
+#define FLASH_OBR_USER_Msk (0x7U << FLASH_OBR_USER_Pos) /*!< 0x0000001C */
+#define FLASH_OBR_USER FLASH_OBR_USER_Msk /*!< User Option Bytes */
+#define FLASH_OBR_DATA0_Pos (10U)
+#define FLASH_OBR_DATA0_Msk (0xFFU << FLASH_OBR_DATA0_Pos) /*!< 0x0003FC00 */
+#define FLASH_OBR_DATA0 FLASH_OBR_DATA0_Msk /*!< Data0 */
+#define FLASH_OBR_DATA1_Pos (18U)
+#define FLASH_OBR_DATA1_Msk (0xFFU << FLASH_OBR_DATA1_Pos) /*!< 0x03FC0000 */
+#define FLASH_OBR_DATA1 FLASH_OBR_DATA1_Msk /*!< Data1 */
+
+/****************** Bit definition for FLASH_WRPR register ******************/
+#define FLASH_WRPR_WRP_Pos (0U)
+#define FLASH_WRPR_WRP_Msk (0xFFFFFFFFU << FLASH_WRPR_WRP_Pos) /*!< 0xFFFFFFFF */
+#define FLASH_WRPR_WRP FLASH_WRPR_WRP_Msk /*!< Write Protect */
+
+/*----------------------------------------------------------------------------*/
+
+/****************** Bit definition for FLASH_RDP register *******************/
+#define FLASH_RDP_RDP_Pos (0U)
+#define FLASH_RDP_RDP_Msk (0xFFU << FLASH_RDP_RDP_Pos) /*!< 0x000000FF */
+#define FLASH_RDP_RDP FLASH_RDP_RDP_Msk /*!< Read protection option byte */
+#define FLASH_RDP_nRDP_Pos (8U)
+#define FLASH_RDP_nRDP_Msk (0xFFU << FLASH_RDP_nRDP_Pos) /*!< 0x0000FF00 */
+#define FLASH_RDP_nRDP FLASH_RDP_nRDP_Msk /*!< Read protection complemented option byte */
+
+/****************** Bit definition for FLASH_USER register ******************/
+#define FLASH_USER_USER_Pos (16U)
+#define FLASH_USER_USER_Msk (0xFFU << FLASH_USER_USER_Pos) /*!< 0x00FF0000 */
+#define FLASH_USER_USER FLASH_USER_USER_Msk /*!< User option byte */
+#define FLASH_USER_nUSER_Pos (24U)
+#define FLASH_USER_nUSER_Msk (0xFFU << FLASH_USER_nUSER_Pos) /*!< 0xFF000000 */
+#define FLASH_USER_nUSER FLASH_USER_nUSER_Msk /*!< User complemented option byte */
+
+/****************** Bit definition for FLASH_Data0 register *****************/
+#define FLASH_DATA0_DATA0_Pos (0U)
+#define FLASH_DATA0_DATA0_Msk (0xFFU << FLASH_DATA0_DATA0_Pos) /*!< 0x000000FF */
+#define FLASH_DATA0_DATA0 FLASH_DATA0_DATA0_Msk /*!< User data storage option byte */
+#define FLASH_DATA0_nDATA0_Pos (8U)
+#define FLASH_DATA0_nDATA0_Msk (0xFFU << FLASH_DATA0_nDATA0_Pos) /*!< 0x0000FF00 */
+#define FLASH_DATA0_nDATA0 FLASH_DATA0_nDATA0_Msk /*!< User data storage complemented option byte */
+
+/****************** Bit definition for FLASH_Data1 register *****************/
+#define FLASH_DATA1_DATA1_Pos (16U)
+#define FLASH_DATA1_DATA1_Msk (0xFFU << FLASH_DATA1_DATA1_Pos) /*!< 0x00FF0000 */
+#define FLASH_DATA1_DATA1 FLASH_DATA1_DATA1_Msk /*!< User data storage option byte */
+#define FLASH_DATA1_nDATA1_Pos (24U)
+#define FLASH_DATA1_nDATA1_Msk (0xFFU << FLASH_DATA1_nDATA1_Pos) /*!< 0xFF000000 */
+#define FLASH_DATA1_nDATA1 FLASH_DATA1_nDATA1_Msk /*!< User data storage complemented option byte */
+
+/****************** Bit definition for FLASH_WRP0 register ******************/
+#define FLASH_WRP0_WRP0_Pos (0U)
+#define FLASH_WRP0_WRP0_Msk (0xFFU << FLASH_WRP0_WRP0_Pos) /*!< 0x000000FF */
+#define FLASH_WRP0_WRP0 FLASH_WRP0_WRP0_Msk /*!< Flash memory write protection option bytes */
+#define FLASH_WRP0_nWRP0_Pos (8U)
+#define FLASH_WRP0_nWRP0_Msk (0xFFU << FLASH_WRP0_nWRP0_Pos) /*!< 0x0000FF00 */
+#define FLASH_WRP0_nWRP0 FLASH_WRP0_nWRP0_Msk /*!< Flash memory write protection complemented option bytes */
+
+/****************** Bit definition for FLASH_WRP1 register ******************/
+#define FLASH_WRP1_WRP1_Pos (16U)
+#define FLASH_WRP1_WRP1_Msk (0xFFU << FLASH_WRP1_WRP1_Pos) /*!< 0x00FF0000 */
+#define FLASH_WRP1_WRP1 FLASH_WRP1_WRP1_Msk /*!< Flash memory write protection option bytes */
+#define FLASH_WRP1_nWRP1_Pos (24U)
+#define FLASH_WRP1_nWRP1_Msk (0xFFU << FLASH_WRP1_nWRP1_Pos) /*!< 0xFF000000 */
+#define FLASH_WRP1_nWRP1 FLASH_WRP1_nWRP1_Msk /*!< Flash memory write protection complemented option bytes */
+
+/****************** Bit definition for FLASH_WRP2 register ******************/
+#define FLASH_WRP2_WRP2_Pos (0U)
+#define FLASH_WRP2_WRP2_Msk (0xFFU << FLASH_WRP2_WRP2_Pos) /*!< 0x000000FF */
+#define FLASH_WRP2_WRP2 FLASH_WRP2_WRP2_Msk /*!< Flash memory write protection option bytes */
+#define FLASH_WRP2_nWRP2_Pos (8U)
+#define FLASH_WRP2_nWRP2_Msk (0xFFU << FLASH_WRP2_nWRP2_Pos) /*!< 0x0000FF00 */
+#define FLASH_WRP2_nWRP2 FLASH_WRP2_nWRP2_Msk /*!< Flash memory write protection complemented option bytes */
+
+/****************** Bit definition for FLASH_WRP3 register ******************/
+#define FLASH_WRP3_WRP3_Pos (16U)
+#define FLASH_WRP3_WRP3_Msk (0xFFU << FLASH_WRP3_WRP3_Pos) /*!< 0x00FF0000 */
+#define FLASH_WRP3_WRP3 FLASH_WRP3_WRP3_Msk /*!< Flash memory write protection option bytes */
+#define FLASH_WRP3_nWRP3_Pos (24U)
+#define FLASH_WRP3_nWRP3_Msk (0xFFU << FLASH_WRP3_nWRP3_Pos) /*!< 0xFF000000 */
+#define FLASH_WRP3_nWRP3 FLASH_WRP3_nWRP3_Msk /*!< Flash memory write protection complemented option bytes */
+
+
+
+/**
+ * @}
+*/
+
+/**
+ * @}
+*/
+
+/** @addtogroup Exported_macro
+ * @{
+ */
+
+/****************************** ADC Instances *********************************/
+#define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1))
+
+#define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC1_COMMON)
+
+#define IS_ADC_DMA_CAPABILITY_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
+
+/****************************** CRC Instances *********************************/
+#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
+
+/****************************** DAC Instances *********************************/
+
+/****************************** DMA Instances *********************************/
+#define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \
+ ((INSTANCE) == DMA1_Channel2) || \
+ ((INSTANCE) == DMA1_Channel3) || \
+ ((INSTANCE) == DMA1_Channel4) || \
+ ((INSTANCE) == DMA1_Channel5) || \
+ ((INSTANCE) == DMA1_Channel6) || \
+ ((INSTANCE) == DMA1_Channel7))
+
+/******************************* GPIO Instances *******************************/
+#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
+ ((INSTANCE) == GPIOB) || \
+ ((INSTANCE) == GPIOC) || \
+ ((INSTANCE) == GPIOD) || \
+ ((INSTANCE) == GPIOE))
+
+/**************************** GPIO Alternate Function Instances ***************/
+#define IS_GPIO_AF_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
+
+/**************************** GPIO Lock Instances *****************************/
+#define IS_GPIO_LOCK_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
+
+/******************************** I2C Instances *******************************/
+#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
+ ((INSTANCE) == I2C2))
+
+/****************************** IWDG Instances ********************************/
+#define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
+
+/******************************** SPI Instances *******************************/
+#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
+ ((INSTANCE) == SPI2))
+
+/****************************** START TIM Instances ***************************/
+/****************************** TIM Instances *********************************/
+#define IS_TIM_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4))
+
+#define IS_TIM_CC1_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4))
+
+#define IS_TIM_CC2_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4))
+
+#define IS_TIM_CC3_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4))
+
+#define IS_TIM_CC4_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4))
+
+#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4))
+
+#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4))
+
+#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4))
+
+#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4))
+
+#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4))
+
+#define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4))
+
+#define IS_TIM_XOR_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4))
+
+#define IS_TIM_MASTER_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4))
+
+#define IS_TIM_SLAVE_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4))
+
+#define IS_TIM_DMABURST_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4))
+
+#define IS_TIM_BREAK_INSTANCE(INSTANCE) (0)
+
+#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
+ ((((INSTANCE) == TIM2) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM3) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM4) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))))
+
+#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) (0)
+
+#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4))
+
+#define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE) (0)
+
+#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4))
+
+#define IS_TIM_DMA_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4))
+
+#define IS_TIM_DMA_CC_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4))
+
+#define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) (0)
+
+/****************************** END TIM Instances *****************************/
+
+
+/******************** USART Instances : Synchronous mode **********************/
+#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3))
+
+/******************** UART Instances : Asynchronous mode **********************/
+#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3))
+
+/******************** UART Instances : Half-Duplex mode **********************/
+#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3))
+
+/******************** UART Instances : LIN mode **********************/
+#define IS_UART_LIN_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3))
+
+/****************** UART Instances : Hardware Flow control ********************/
+#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3))
+
+/********************* UART Instances : Smard card mode ***********************/
+#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3))
+
+/*********************** UART Instances : IRDA mode ***************************/
+#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3))
+
+/***************** UART Instances : Multi-Processor mode **********************/
+#define IS_UART_MULTIPROCESSOR_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3))
+
+/***************** UART Instances : DMA mode available **********************/
+#define IS_UART_DMA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3))
+
+/****************************** RTC Instances *********************************/
+#define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
+
+/**************************** WWDG Instances *****************************/
+#define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
+
+
+
+
+
+/**
+ * @}
+*/
+/******************************************************************************/
+/* For a painless codes migration between the STM32F1xx device product */
+/* lines, the aliases defined below are put in place to overcome the */
+/* differences in the interrupt handlers and IRQn definitions. */
+/* No need to update developed interrupt code when moving across */
+/* product lines within the same STM32F1 Family */
+/******************************************************************************/
+
+/* Aliases for __IRQn */
+#define ADC1_2_IRQn ADC1_IRQn
+
+
+/* Aliases for __IRQHandler */
+#define ADC1_2_IRQHandler ADC1_IRQHandler
+
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+
+#ifdef __cplusplus
+ }
+#endif /* __cplusplus */
+
+#endif /* __STM32F101xB_H */
+
+
+
+ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Device/ST/STM32F1xx/Include/stm32f101xe.h b/Device/ST/STM32F1xx/Include/stm32f101xe.h
new file mode 100644
index 0000000..bc0fdee
--- /dev/null
+++ b/Device/ST/STM32F1xx/Include/stm32f101xe.h
@@ -0,0 +1,7281 @@
+/**
+ ******************************************************************************
+ * @file stm32f101xe.h
+ * @author MCD Application Team
+ * @version V4.1.0
+ * @date 29-April-2016
+ * @brief CMSIS Cortex-M3 Device Peripheral Access Layer Header File.
+ * This file contains all the peripheral register's definitions, bits
+ * definitions and memory mapping for STM32F1xx devices.
+ *
+ * This file contains:
+ * - Data structures and the address mapping for all peripherals
+ * - Peripheral's registers declarations and bits definition
+ * - Macros to access peripheral’s registers hardware
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+
+/** @addtogroup CMSIS
+ * @{
+ */
+
+/** @addtogroup stm32f101xe
+ * @{
+ */
+
+#ifndef __STM32F101xE_H
+#define __STM32F101xE_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/** @addtogroup Configuration_section_for_CMSIS
+ * @{
+ */
+/**
+ * @brief Configuration of the Cortex-M3 Processor and Core Peripherals
+ */
+ #define __MPU_PRESENT 0 /*!< Other STM32 devices does not provide an MPU */
+#define __CM3_REV 0x0200 /*!< Core Revision r2p0 */
+#define __NVIC_PRIO_BITS 4 /*!< STM32 uses 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
+
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_interrupt_number_definition
+ * @{
+ */
+
+/**
+ * @brief STM32F10x Interrupt Number Definition, according to the selected device
+ * in @ref Library_configuration_section
+ */
+
+ /*!< Interrupt Number Definition */
+typedef enum
+{
+/****** Cortex-M3 Processor Exceptions Numbers ***************************************************/
+ NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
+ HardFault_IRQn = -13, /*!< 3 Cortex-M3 Hard Fault Interrupt */
+ MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */
+ BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */
+ UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */
+ SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */
+ DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */
+ PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */
+ SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */
+
+/****** STM32 specific Interrupt Numbers *********************************************************/
+ WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
+ PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */
+ TAMPER_IRQn = 2, /*!< Tamper Interrupt */
+ RTC_IRQn = 3, /*!< RTC global Interrupt */
+ FLASH_IRQn = 4, /*!< FLASH global Interrupt */
+ RCC_IRQn = 5, /*!< RCC global Interrupt */
+ EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */
+ EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */
+ EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */
+ EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */
+ EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */
+ DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 global Interrupt */
+ DMA1_Channel2_IRQn = 12, /*!< DMA1 Channel 2 global Interrupt */
+ DMA1_Channel3_IRQn = 13, /*!< DMA1 Channel 3 global Interrupt */
+ DMA1_Channel4_IRQn = 14, /*!< DMA1 Channel 4 global Interrupt */
+ DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 global Interrupt */
+ DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 global Interrupt */
+ DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 global Interrupt */
+ ADC1_IRQn = 18, /*!< ADC1 global Interrupt */
+ EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
+ TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
+ TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
+ TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
+ I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
+ I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
+ I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
+ I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
+ SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
+ SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
+ USART1_IRQn = 37, /*!< USART1 global Interrupt */
+ USART2_IRQn = 38, /*!< USART2 global Interrupt */
+ USART3_IRQn = 39, /*!< USART3 global Interrupt */
+ EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
+ RTC_Alarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */
+ FSMC_IRQn = 48, /*!< FSMC global Interrupt */
+ TIM5_IRQn = 50, /*!< TIM5 global Interrupt */
+ SPI3_IRQn = 51, /*!< SPI3 global Interrupt */
+ UART4_IRQn = 52, /*!< UART4 global Interrupt */
+ UART5_IRQn = 53, /*!< UART5 global Interrupt */
+ TIM6_IRQn = 54, /*!< TIM6 global Interrupt */
+ TIM7_IRQn = 55, /*!< TIM7 global Interrupt */
+ DMA2_Channel1_IRQn = 56, /*!< DMA2 Channel 1 global Interrupt */
+ DMA2_Channel2_IRQn = 57, /*!< DMA2 Channel 2 global Interrupt */
+ DMA2_Channel3_IRQn = 58, /*!< DMA2 Channel 3 global Interrupt */
+ DMA2_Channel4_5_IRQn = 59, /*!< DMA2 Channel 4 and Channel 5 global Interrupt */
+} IRQn_Type;
+
+
+/**
+ * @}
+ */
+
+#include "core_cm3.h"
+#include "system_stm32f1xx.h"
+#include <stdint.h>
+
+/** @addtogroup Peripheral_registers_structures
+ * @{
+ */
+
+/**
+ * @brief Analog to Digital Converter
+ */
+
+typedef struct
+{
+ __IO uint32_t SR;
+ __IO uint32_t CR1;
+ __IO uint32_t CR2;
+ __IO uint32_t SMPR1;
+ __IO uint32_t SMPR2;
+ __IO uint32_t JOFR1;
+ __IO uint32_t JOFR2;
+ __IO uint32_t JOFR3;
+ __IO uint32_t JOFR4;
+ __IO uint32_t HTR;
+ __IO uint32_t LTR;
+ __IO uint32_t SQR1;
+ __IO uint32_t SQR2;
+ __IO uint32_t SQR3;
+ __IO uint32_t JSQR;
+ __IO uint32_t JDR1;
+ __IO uint32_t JDR2;
+ __IO uint32_t JDR3;
+ __IO uint32_t JDR4;
+ __IO uint32_t DR;
+} ADC_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t SR; /*!< ADC status register, used for ADC multimode (bits common to several ADC instances). Address offset: ADC1 base address */
+ __IO uint32_t CR1; /*!< ADC control register 1, used for ADC multimode (bits common to several ADC instances). Address offset: ADC1 base address + 0x04 */
+ __IO uint32_t CR2; /*!< ADC control register 2, used for ADC multimode (bits common to several ADC instances). Address offset: ADC1 base address + 0x08 */
+ uint32_t RESERVED[16];
+ __IO uint32_t DR; /*!< ADC data register, used for ADC multimode (bits common to several ADC instances). Address offset: ADC1 base address + 0x4C */
+} ADC_Common_TypeDef;
+
+/**
+ * @brief Backup Registers
+ */
+
+typedef struct
+{
+ uint32_t RESERVED0;
+ __IO uint32_t DR1;
+ __IO uint32_t DR2;
+ __IO uint32_t DR3;
+ __IO uint32_t DR4;
+ __IO uint32_t DR5;
+ __IO uint32_t DR6;
+ __IO uint32_t DR7;
+ __IO uint32_t DR8;
+ __IO uint32_t DR9;
+ __IO uint32_t DR10;
+ __IO uint32_t RTCCR;
+ __IO uint32_t CR;
+ __IO uint32_t CSR;
+ uint32_t RESERVED13[2];
+ __IO uint32_t DR11;
+ __IO uint32_t DR12;
+ __IO uint32_t DR13;
+ __IO uint32_t DR14;
+ __IO uint32_t DR15;
+ __IO uint32_t DR16;
+ __IO uint32_t DR17;
+ __IO uint32_t DR18;
+ __IO uint32_t DR19;
+ __IO uint32_t DR20;
+ __IO uint32_t DR21;
+ __IO uint32_t DR22;
+ __IO uint32_t DR23;
+ __IO uint32_t DR24;
+ __IO uint32_t DR25;
+ __IO uint32_t DR26;
+ __IO uint32_t DR27;
+ __IO uint32_t DR28;
+ __IO uint32_t DR29;
+ __IO uint32_t DR30;
+ __IO uint32_t DR31;
+ __IO uint32_t DR32;
+ __IO uint32_t DR33;
+ __IO uint32_t DR34;
+ __IO uint32_t DR35;
+ __IO uint32_t DR36;
+ __IO uint32_t DR37;
+ __IO uint32_t DR38;
+ __IO uint32_t DR39;
+ __IO uint32_t DR40;
+ __IO uint32_t DR41;
+ __IO uint32_t DR42;
+} BKP_TypeDef;
+
+
+/**
+ * @brief CRC calculation unit
+ */
+
+typedef struct
+{
+ __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
+ __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
+ uint8_t RESERVED0; /*!< Reserved, Address offset: 0x05 */
+ uint16_t RESERVED1; /*!< Reserved, Address offset: 0x06 */
+ __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
+} CRC_TypeDef;
+
+/**
+ * @brief Digital to Analog Converter
+ */
+
+typedef struct
+{
+ __IO uint32_t CR;
+ __IO uint32_t SWTRIGR;
+ __IO uint32_t DHR12R1;
+ __IO uint32_t DHR12L1;
+ __IO uint32_t DHR8R1;
+ __IO uint32_t DHR12R2;
+ __IO uint32_t DHR12L2;
+ __IO uint32_t DHR8R2;
+ __IO uint32_t DHR12RD;
+ __IO uint32_t DHR12LD;
+ __IO uint32_t DHR8RD;
+ __IO uint32_t DOR1;
+ __IO uint32_t DOR2;
+} DAC_TypeDef;
+
+/**
+ * @brief Debug MCU
+ */
+
+typedef struct
+{
+ __IO uint32_t IDCODE;
+ __IO uint32_t CR;
+}DBGMCU_TypeDef;
+
+/**
+ * @brief DMA Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t CCR;
+ __IO uint32_t CNDTR;
+ __IO uint32_t CPAR;
+ __IO uint32_t CMAR;
+} DMA_Channel_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t ISR;
+ __IO uint32_t IFCR;
+} DMA_TypeDef;
+
+
+
+/**
+ * @brief External Interrupt/Event Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t IMR;
+ __IO uint32_t EMR;
+ __IO uint32_t RTSR;
+ __IO uint32_t FTSR;
+ __IO uint32_t SWIER;
+ __IO uint32_t PR;
+} EXTI_TypeDef;
+
+/**
+ * @brief FLASH Registers
+ */
+
+typedef struct
+{
+ __IO uint32_t ACR;
+ __IO uint32_t KEYR;
+ __IO uint32_t OPTKEYR;
+ __IO uint32_t SR;
+ __IO uint32_t CR;
+ __IO uint32_t AR;
+ __IO uint32_t RESERVED;
+ __IO uint32_t OBR;
+ __IO uint32_t WRPR;
+} FLASH_TypeDef;
+
+/**
+ * @brief Option Bytes Registers
+ */
+
+typedef struct
+{
+ __IO uint16_t RDP;
+ __IO uint16_t USER;
+ __IO uint16_t Data0;
+ __IO uint16_t Data1;
+ __IO uint16_t WRP0;
+ __IO uint16_t WRP1;
+ __IO uint16_t WRP2;
+ __IO uint16_t WRP3;
+} OB_TypeDef;
+
+/**
+ * @brief Flexible Static Memory Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t BTCR[8];
+} FSMC_Bank1_TypeDef;
+
+/**
+ * @brief Flexible Static Memory Controller Bank1E
+ */
+
+typedef struct
+{
+ __IO uint32_t BWTR[7];
+} FSMC_Bank1E_TypeDef;
+
+/**
+ * @brief Flexible Static Memory Controller Bank2
+ */
+
+typedef struct
+{
+ __IO uint32_t PCR2; /*!< NAND Flash control register 2, Address offset: 0x60 */
+ __IO uint32_t SR2; /*!< NAND Flash FIFO status and interrupt register 2, Address offset: 0x64 */
+ __IO uint32_t PMEM2; /*!< NAND Flash Common memory space timing register 2, Address offset: 0x68 */
+ __IO uint32_t PATT2; /*!< NAND Flash Attribute memory space timing register 2, Address offset: 0x6C */
+ uint32_t RESERVED0; /*!< Reserved, 0x70 */
+ __IO uint32_t ECCR2; /*!< NAND Flash ECC result registers 2, Address offset: 0x74 */
+ uint32_t RESERVED1; /*!< Reserved, 0x78 */
+ uint32_t RESERVED2; /*!< Reserved, 0x7C */
+ __IO uint32_t PCR3; /*!< NAND Flash control register 3, Address offset: 0x80 */
+ __IO uint32_t SR3; /*!< NAND Flash FIFO status and interrupt register 3, Address offset: 0x84 */
+ __IO uint32_t PMEM3; /*!< NAND Flash Common memory space timing register 3, Address offset: 0x88 */
+ __IO uint32_t PATT3; /*!< NAND Flash Attribute memory space timing register 3, Address offset: 0x8C */
+ uint32_t RESERVED3; /*!< Reserved, 0x90 */
+ __IO uint32_t ECCR3; /*!< NAND Flash ECC result registers 3, Address offset: 0x94 */
+} FSMC_Bank2_3_TypeDef;
+
+/**
+ * @brief Flexible Static Memory Controller Bank4
+ */
+
+typedef struct
+{
+ __IO uint32_t PCR4;
+ __IO uint32_t SR4;
+ __IO uint32_t PMEM4;
+ __IO uint32_t PATT4;
+ __IO uint32_t PIO4;
+} FSMC_Bank4_TypeDef;
+
+/**
+ * @brief General Purpose I/O
+ */
+
+typedef struct
+{
+ __IO uint32_t CRL;
+ __IO uint32_t CRH;
+ __IO uint32_t IDR;
+ __IO uint32_t ODR;
+ __IO uint32_t BSRR;
+ __IO uint32_t BRR;
+ __IO uint32_t LCKR;
+} GPIO_TypeDef;
+
+/**
+ * @brief Alternate Function I/O
+ */
+
+typedef struct
+{
+ __IO uint32_t EVCR;
+ __IO uint32_t MAPR;
+ __IO uint32_t EXTICR[4];
+ uint32_t RESERVED0;
+ __IO uint32_t MAPR2;
+} AFIO_TypeDef;
+/**
+ * @brief Inter Integrated Circuit Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t CR1;
+ __IO uint32_t CR2;
+ __IO uint32_t OAR1;
+ __IO uint32_t OAR2;
+ __IO uint32_t DR;
+ __IO uint32_t SR1;
+ __IO uint32_t SR2;
+ __IO uint32_t CCR;
+ __IO uint32_t TRISE;
+} I2C_TypeDef;
+
+/**
+ * @brief Independent WATCHDOG
+ */
+
+typedef struct
+{
+ __IO uint32_t KR; /*!< Key register, Address offset: 0x00 */
+ __IO uint32_t PR; /*!< Prescaler register, Address offset: 0x04 */
+ __IO uint32_t RLR; /*!< Reload register, Address offset: 0x08 */
+ __IO uint32_t SR; /*!< Status register, Address offset: 0x0C */
+} IWDG_TypeDef;
+
+/**
+ * @brief Power Control
+ */
+
+typedef struct
+{
+ __IO uint32_t CR;
+ __IO uint32_t CSR;
+} PWR_TypeDef;
+
+/**
+ * @brief Reset and Clock Control
+ */
+
+typedef struct
+{
+ __IO uint32_t CR;
+ __IO uint32_t CFGR;
+ __IO uint32_t CIR;
+ __IO uint32_t APB2RSTR;
+ __IO uint32_t APB1RSTR;
+ __IO uint32_t AHBENR;
+ __IO uint32_t APB2ENR;
+ __IO uint32_t APB1ENR;
+ __IO uint32_t BDCR;
+ __IO uint32_t CSR;
+
+
+} RCC_TypeDef;
+
+/**
+ * @brief Real-Time Clock
+ */
+
+typedef struct
+{
+ __IO uint32_t CRH;
+ __IO uint32_t CRL;
+ __IO uint32_t PRLH;
+ __IO uint32_t PRLL;
+ __IO uint32_t DIVH;
+ __IO uint32_t DIVL;
+ __IO uint32_t CNTH;
+ __IO uint32_t CNTL;
+ __IO uint32_t ALRH;
+ __IO uint32_t ALRL;
+} RTC_TypeDef;
+
+/**
+ * @brief SD host Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t POWER;
+ __IO uint32_t CLKCR;
+ __IO uint32_t ARG;
+ __IO uint32_t CMD;
+ __I uint32_t RESPCMD;
+ __I uint32_t RESP1;
+ __I uint32_t RESP2;
+ __I uint32_t RESP3;
+ __I uint32_t RESP4;
+ __IO uint32_t DTIMER;
+ __IO uint32_t DLEN;
+ __IO uint32_t DCTRL;
+ __I uint32_t DCOUNT;
+ __I uint32_t STA;
+ __IO uint32_t ICR;
+ __IO uint32_t MASK;
+ uint32_t RESERVED0[2];
+ __I uint32_t FIFOCNT;
+ uint32_t RESERVED1[13];
+ __IO uint32_t FIFO;
+} SDIO_TypeDef;
+
+/**
+ * @brief Serial Peripheral Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t CR1;
+ __IO uint32_t CR2;
+ __IO uint32_t SR;
+ __IO uint32_t DR;
+ __IO uint32_t CRCPR;
+ __IO uint32_t RXCRCR;
+ __IO uint32_t TXCRCR;
+ __IO uint32_t I2SCFGR;
+} SPI_TypeDef;
+
+/**
+ * @brief TIM Timers
+ */
+typedef struct
+{
+ __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
+ __IO uint32_t SMCR; /*!< TIM slave Mode Control register, Address offset: 0x08 */
+ __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
+ __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
+ __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
+ __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
+ __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
+ __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
+ __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
+ __IO uint32_t PSC; /*!< TIM prescaler register, Address offset: 0x28 */
+ __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
+ __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */
+ __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
+ __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
+ __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
+ __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
+ __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
+ __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
+ __IO uint32_t DMAR; /*!< TIM DMA address for full transfer register, Address offset: 0x4C */
+ __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */
+}TIM_TypeDef;
+
+
+/**
+ * @brief Universal Synchronous Asynchronous Receiver Transmitter
+ */
+
+typedef struct
+{
+ __IO uint32_t SR; /*!< USART Status register, Address offset: 0x00 */
+ __IO uint32_t DR; /*!< USART Data register, Address offset: 0x04 */
+ __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x08 */
+ __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x0C */
+ __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x10 */
+ __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x14 */
+ __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x18 */
+} USART_TypeDef;
+
+
+
+/**
+ * @brief Window WATCHDOG
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
+ __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
+ __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
+} WWDG_TypeDef;
+
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_memory_map
+ * @{
+ */
+
+
+#define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH base address in the alias region */
+#define FLASH_BANK1_END ((uint32_t)0x0807FFFF) /*!< FLASH END address of bank1 */
+#define SRAM_BASE ((uint32_t)0x20000000) /*!< SRAM base address in the alias region */
+#define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */
+
+#define SRAM_BB_BASE ((uint32_t)0x22000000) /*!< SRAM base address in the bit-band region */
+#define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */
+
+#define FSMC_BASE ((uint32_t)0x60000000) /*!< FSMC base address */
+#define FSMC_R_BASE ((uint32_t)0xA0000000) /*!< FSMC registers base address */
+
+/*!< Peripheral memory map */
+#define APB1PERIPH_BASE PERIPH_BASE
+#define APB2PERIPH_BASE (PERIPH_BASE + 0x10000)
+#define AHBPERIPH_BASE (PERIPH_BASE + 0x20000)
+
+#define TIM2_BASE (APB1PERIPH_BASE + 0x0000)
+#define TIM3_BASE (APB1PERIPH_BASE + 0x0400)
+#define TIM4_BASE (APB1PERIPH_BASE + 0x0800)
+#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00)
+#define TIM6_BASE (APB1PERIPH_BASE + 0x1000)
+#define TIM7_BASE (APB1PERIPH_BASE + 0x1400)
+#define RTC_BASE (APB1PERIPH_BASE + 0x2800)
+#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00)
+#define IWDG_BASE (APB1PERIPH_BASE + 0x3000)
+#define SPI2_BASE (APB1PERIPH_BASE + 0x3800)
+#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00)
+#define USART2_BASE (APB1PERIPH_BASE + 0x4400)
+#define USART3_BASE (APB1PERIPH_BASE + 0x4800)
+#define UART4_BASE (APB1PERIPH_BASE + 0x4C00)
+#define UART5_BASE (APB1PERIPH_BASE + 0x5000)
+#define I2C1_BASE (APB1PERIPH_BASE + 0x5400)
+#define I2C2_BASE (APB1PERIPH_BASE + 0x5800)
+#define BKP_BASE (APB1PERIPH_BASE + 0x6C00)
+#define PWR_BASE (APB1PERIPH_BASE + 0x7000)
+#define DAC_BASE (APB1PERIPH_BASE + 0x7400)
+#define AFIO_BASE (APB2PERIPH_BASE + 0x0000)
+#define EXTI_BASE (APB2PERIPH_BASE + 0x0400)
+#define GPIOA_BASE (APB2PERIPH_BASE + 0x0800)
+#define GPIOB_BASE (APB2PERIPH_BASE + 0x0C00)
+#define GPIOC_BASE (APB2PERIPH_BASE + 0x1000)
+#define GPIOD_BASE (APB2PERIPH_BASE + 0x1400)
+#define GPIOE_BASE (APB2PERIPH_BASE + 0x1800)
+#define GPIOF_BASE (APB2PERIPH_BASE + 0x1C00)
+#define GPIOG_BASE (APB2PERIPH_BASE + 0x2000)
+#define ADC1_BASE (APB2PERIPH_BASE + 0x2400)
+#define SPI1_BASE (APB2PERIPH_BASE + 0x3000)
+#define USART1_BASE (APB2PERIPH_BASE + 0x3800)
+
+#define SDIO_BASE (PERIPH_BASE + 0x18000)
+
+#define DMA1_BASE (AHBPERIPH_BASE + 0x0000)
+#define DMA1_Channel1_BASE (AHBPERIPH_BASE + 0x0008)
+#define DMA1_Channel2_BASE (AHBPERIPH_BASE + 0x001C)
+#define DMA1_Channel3_BASE (AHBPERIPH_BASE + 0x0030)
+#define DMA1_Channel4_BASE (AHBPERIPH_BASE + 0x0044)
+#define DMA1_Channel5_BASE (AHBPERIPH_BASE + 0x0058)
+#define DMA1_Channel6_BASE (AHBPERIPH_BASE + 0x006C)
+#define DMA1_Channel7_BASE (AHBPERIPH_BASE + 0x0080)
+#define DMA2_BASE (AHBPERIPH_BASE + 0x0400)
+#define DMA2_Channel1_BASE (AHBPERIPH_BASE + 0x0408)
+#define DMA2_Channel2_BASE (AHBPERIPH_BASE + 0x041C)
+#define DMA2_Channel3_BASE (AHBPERIPH_BASE + 0x0430)
+#define DMA2_Channel4_BASE (AHBPERIPH_BASE + 0x0444)
+#define DMA2_Channel5_BASE (AHBPERIPH_BASE + 0x0458)
+#define RCC_BASE (AHBPERIPH_BASE + 0x1000)
+#define CRC_BASE (AHBPERIPH_BASE + 0x3000)
+
+#define FLASH_R_BASE (AHBPERIPH_BASE + 0x2000) /*!< Flash registers base address */
+#define FLASHSIZE_BASE ((uint32_t)0x1FFFF7E0) /*!< FLASH Size register base address */
+#define UID_BASE ((uint32_t)0x1FFFF7E8) /*!< Unique device ID register base address */
+#define OB_BASE ((uint32_t)0x1FFFF800) /*!< Flash Option Bytes base address */
+
+
+#define FSMC_BANK1 (FSMC_BASE) /*!< FSMC Bank1 base address */
+#define FSMC_BANK1_1 (FSMC_BANK1) /*!< FSMC Bank1_1 base address */
+#define FSMC_BANK1_2 (FSMC_BANK1 + 0x04000000) /*!< FSMC Bank1_2 base address */
+#define FSMC_BANK1_3 (FSMC_BANK1 + 0x08000000) /*!< FSMC Bank1_3 base address */
+#define FSMC_BANK1_4 (FSMC_BANK1 + 0x0C000000) /*!< FSMC Bank1_4 base address */
+
+#define FSMC_BANK2 (FSMC_BASE + 0x10000000) /*!< FSMC Bank2 base address */
+#define FSMC_BANK3 (FSMC_BASE + 0x20000000) /*!< FSMC Bank3 base address */
+#define FSMC_BANK4 (FSMC_BASE + 0x30000000) /*!< FSMC Bank4 base address */
+
+#define FSMC_BANK1_R_BASE (FSMC_R_BASE + 0x0000) /*!< FSMC Bank1 registers base address */
+#define FSMC_BANK1E_R_BASE (FSMC_R_BASE + 0x0104) /*!< FSMC Bank1E registers base address */
+#define FSMC_BANK2_3_R_BASE (FSMC_R_BASE + 0x0060) /*!< FSMC Bank2/Bank3 registers base address */
+#define FSMC_BANK4_R_BASE (FSMC_R_BASE + 0x00A0) /*!< FSMC Bank4 registers base address */
+
+#define DBGMCU_BASE ((uint32_t)0xE0042000) /*!< Debug MCU registers base address */
+
+
+
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_declaration
+ * @{
+ */
+
+#define TIM2 ((TIM_TypeDef *) TIM2_BASE)
+#define TIM3 ((TIM_TypeDef *) TIM3_BASE)
+#define TIM4 ((TIM_TypeDef *) TIM4_BASE)
+#define TIM5 ((TIM_TypeDef *) TIM5_BASE)
+#define TIM6 ((TIM_TypeDef *) TIM6_BASE)
+#define TIM7 ((TIM_TypeDef *) TIM7_BASE)
+#define RTC ((RTC_TypeDef *) RTC_BASE)
+#define WWDG ((WWDG_TypeDef *) WWDG_BASE)
+#define IWDG ((IWDG_TypeDef *) IWDG_BASE)
+#define SPI2 ((SPI_TypeDef *) SPI2_BASE)
+#define SPI3 ((SPI_TypeDef *) SPI3_BASE)
+#define USART2 ((USART_TypeDef *) USART2_BASE)
+#define USART3 ((USART_TypeDef *) USART3_BASE)
+#define UART4 ((USART_TypeDef *) UART4_BASE)
+#define UART5 ((USART_TypeDef *) UART5_BASE)
+#define I2C1 ((I2C_TypeDef *) I2C1_BASE)
+#define I2C2 ((I2C_TypeDef *) I2C2_BASE)
+#define BKP ((BKP_TypeDef *) BKP_BASE)
+#define PWR ((PWR_TypeDef *) PWR_BASE)
+#define DAC ((DAC_TypeDef *) DAC_BASE)
+#define AFIO ((AFIO_TypeDef *) AFIO_BASE)
+#define EXTI ((EXTI_TypeDef *) EXTI_BASE)
+#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
+#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
+#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
+#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
+#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
+#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
+#define GPIOG ((GPIO_TypeDef *) GPIOG_BASE)
+#define ADC1 ((ADC_TypeDef *) ADC1_BASE)
+#define ADC1_COMMON ((ADC_Common_TypeDef *) ADC1_BASE)
+#define SPI1 ((SPI_TypeDef *) SPI1_BASE)
+#define USART1 ((USART_TypeDef *) USART1_BASE)
+#define SDIO ((SDIO_TypeDef *) SDIO_BASE)
+#define DMA1 ((DMA_TypeDef *) DMA1_BASE)
+#define DMA2 ((DMA_TypeDef *) DMA2_BASE)
+#define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
+#define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
+#define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
+#define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
+#define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
+#define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
+#define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
+#define DMA2_Channel1 ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE)
+#define DMA2_Channel2 ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE)
+#define DMA2_Channel3 ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE)
+#define DMA2_Channel4 ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE)
+#define DMA2_Channel5 ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE)
+#define RCC ((RCC_TypeDef *) RCC_BASE)
+#define CRC ((CRC_TypeDef *) CRC_BASE)
+#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
+#define OB ((OB_TypeDef *) OB_BASE)
+#define FSMC_Bank1 ((FSMC_Bank1_TypeDef *) FSMC_BANK1_R_BASE)
+#define FSMC_Bank1E ((FSMC_Bank1E_TypeDef *) FSMC_BANK1E_R_BASE)
+#define FSMC_Bank2_3 ((FSMC_Bank2_3_TypeDef *) FSMC_BANK2_3_R_BASE)
+#define FSMC_Bank4 ((FSMC_Bank4_TypeDef *) FSMC_BANK4_R_BASE)
+#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
+
+
+/**
+ * @}
+ */
+
+/** @addtogroup Exported_constants
+ * @{
+ */
+
+ /** @addtogroup Peripheral_Registers_Bits_Definition
+ * @{
+ */
+
+/******************************************************************************/
+/* Peripheral Registers_Bits_Definition */
+/******************************************************************************/
+
+/******************************************************************************/
+/* */
+/* CRC calculation unit (CRC) */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for CRC_DR register *********************/
+#define CRC_DR_DR_Pos (0U)
+#define CRC_DR_DR_Msk (0xFFFFFFFFU << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */
+#define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */
+
+/******************* Bit definition for CRC_IDR register ********************/
+#define CRC_IDR_IDR_Pos (0U)
+#define CRC_IDR_IDR_Msk (0xFFU << CRC_IDR_IDR_Pos) /*!< 0x000000FF */
+#define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 8-bit data register bits */
+
+/******************** Bit definition for CRC_CR register ********************/
+#define CRC_CR_RESET_Pos (0U)
+#define CRC_CR_RESET_Msk (0x1U << CRC_CR_RESET_Pos) /*!< 0x00000001 */
+#define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET bit */
+
+/******************************************************************************/
+/* */
+/* Power Control */
+/* */
+/******************************************************************************/
+
+/******************** Bit definition for PWR_CR register ********************/
+#define PWR_CR_LPDS_Pos (0U)
+#define PWR_CR_LPDS_Msk (0x1U << PWR_CR_LPDS_Pos) /*!< 0x00000001 */
+#define PWR_CR_LPDS PWR_CR_LPDS_Msk /*!< Low-Power Deepsleep */
+#define PWR_CR_PDDS_Pos (1U)
+#define PWR_CR_PDDS_Msk (0x1U << PWR_CR_PDDS_Pos) /*!< 0x00000002 */
+#define PWR_CR_PDDS PWR_CR_PDDS_Msk /*!< Power Down Deepsleep */
+#define PWR_CR_CWUF_Pos (2U)
+#define PWR_CR_CWUF_Msk (0x1U << PWR_CR_CWUF_Pos) /*!< 0x00000004 */
+#define PWR_CR_CWUF PWR_CR_CWUF_Msk /*!< Clear Wakeup Flag */
+#define PWR_CR_CSBF_Pos (3U)
+#define PWR_CR_CSBF_Msk (0x1U << PWR_CR_CSBF_Pos) /*!< 0x00000008 */
+#define PWR_CR_CSBF PWR_CR_CSBF_Msk /*!< Clear Standby Flag */
+#define PWR_CR_PVDE_Pos (4U)
+#define PWR_CR_PVDE_Msk (0x1U << PWR_CR_PVDE_Pos) /*!< 0x00000010 */
+#define PWR_CR_PVDE PWR_CR_PVDE_Msk /*!< Power Voltage Detector Enable */
+
+#define PWR_CR_PLS_Pos (5U)
+#define PWR_CR_PLS_Msk (0x7U << PWR_CR_PLS_Pos) /*!< 0x000000E0 */
+#define PWR_CR_PLS PWR_CR_PLS_Msk /*!< PLS[2:0] bits (PVD Level Selection) */
+#define PWR_CR_PLS_0 (0x1U << PWR_CR_PLS_Pos) /*!< 0x00000020 */
+#define PWR_CR_PLS_1 (0x2U << PWR_CR_PLS_Pos) /*!< 0x00000040 */
+#define PWR_CR_PLS_2 (0x4U << PWR_CR_PLS_Pos) /*!< 0x00000080 */
+
+/*!< PVD level configuration */
+#define PWR_CR_PLS_2V2 ((uint32_t)0x00000000) /*!< PVD level 2.2V */
+#define PWR_CR_PLS_2V3 ((uint32_t)0x00000020) /*!< PVD level 2.3V */
+#define PWR_CR_PLS_2V4 ((uint32_t)0x00000040) /*!< PVD level 2.4V */
+#define PWR_CR_PLS_2V5 ((uint32_t)0x00000060) /*!< PVD level 2.5V */
+#define PWR_CR_PLS_2V6 ((uint32_t)0x00000080) /*!< PVD level 2.6V */
+#define PWR_CR_PLS_2V7 ((uint32_t)0x000000A0) /*!< PVD level 2.7V */
+#define PWR_CR_PLS_2V8 ((uint32_t)0x000000C0) /*!< PVD level 2.8V */
+#define PWR_CR_PLS_2V9 ((uint32_t)0x000000E0) /*!< PVD level 2.9V */
+
+#define PWR_CR_DBP_Pos (8U)
+#define PWR_CR_DBP_Msk (0x1U << PWR_CR_DBP_Pos) /*!< 0x00000100 */
+#define PWR_CR_DBP PWR_CR_DBP_Msk /*!< Disable Backup Domain write protection */
+
+
+/******************* Bit definition for PWR_CSR register ********************/
+#define PWR_CSR_WUF_Pos (0U)
+#define PWR_CSR_WUF_Msk (0x1U << PWR_CSR_WUF_Pos) /*!< 0x00000001 */
+#define PWR_CSR_WUF PWR_CSR_WUF_Msk /*!< Wakeup Flag */
+#define PWR_CSR_SBF_Pos (1U)
+#define PWR_CSR_SBF_Msk (0x1U << PWR_CSR_SBF_Pos) /*!< 0x00000002 */
+#define PWR_CSR_SBF PWR_CSR_SBF_Msk /*!< Standby Flag */
+#define PWR_CSR_PVDO_Pos (2U)
+#define PWR_CSR_PVDO_Msk (0x1U << PWR_CSR_PVDO_Pos) /*!< 0x00000004 */
+#define PWR_CSR_PVDO PWR_CSR_PVDO_Msk /*!< PVD Output */
+#define PWR_CSR_EWUP_Pos (8U)
+#define PWR_CSR_EWUP_Msk (0x1U << PWR_CSR_EWUP_Pos) /*!< 0x00000100 */
+#define PWR_CSR_EWUP PWR_CSR_EWUP_Msk /*!< Enable WKUP pin */
+
+/******************************************************************************/
+/* */
+/* Backup registers */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for BKP_DR1 register ********************/
+#define BKP_DR1_D_Pos (0U)
+#define BKP_DR1_D_Msk (0xFFFFU << BKP_DR1_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR1_D BKP_DR1_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR2 register ********************/
+#define BKP_DR2_D_Pos (0U)
+#define BKP_DR2_D_Msk (0xFFFFU << BKP_DR2_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR2_D BKP_DR2_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR3 register ********************/
+#define BKP_DR3_D_Pos (0U)
+#define BKP_DR3_D_Msk (0xFFFFU << BKP_DR3_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR3_D BKP_DR3_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR4 register ********************/
+#define BKP_DR4_D_Pos (0U)
+#define BKP_DR4_D_Msk (0xFFFFU << BKP_DR4_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR4_D BKP_DR4_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR5 register ********************/
+#define BKP_DR5_D_Pos (0U)
+#define BKP_DR5_D_Msk (0xFFFFU << BKP_DR5_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR5_D BKP_DR5_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR6 register ********************/
+#define BKP_DR6_D_Pos (0U)
+#define BKP_DR6_D_Msk (0xFFFFU << BKP_DR6_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR6_D BKP_DR6_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR7 register ********************/
+#define BKP_DR7_D_Pos (0U)
+#define BKP_DR7_D_Msk (0xFFFFU << BKP_DR7_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR7_D BKP_DR7_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR8 register ********************/
+#define BKP_DR8_D_Pos (0U)
+#define BKP_DR8_D_Msk (0xFFFFU << BKP_DR8_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR8_D BKP_DR8_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR9 register ********************/
+#define BKP_DR9_D_Pos (0U)
+#define BKP_DR9_D_Msk (0xFFFFU << BKP_DR9_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR9_D BKP_DR9_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR10 register *******************/
+#define BKP_DR10_D_Pos (0U)
+#define BKP_DR10_D_Msk (0xFFFFU << BKP_DR10_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR10_D BKP_DR10_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR11 register *******************/
+#define BKP_DR11_D_Pos (0U)
+#define BKP_DR11_D_Msk (0xFFFFU << BKP_DR11_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR11_D BKP_DR11_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR12 register *******************/
+#define BKP_DR12_D_Pos (0U)
+#define BKP_DR12_D_Msk (0xFFFFU << BKP_DR12_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR12_D BKP_DR12_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR13 register *******************/
+#define BKP_DR13_D_Pos (0U)
+#define BKP_DR13_D_Msk (0xFFFFU << BKP_DR13_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR13_D BKP_DR13_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR14 register *******************/
+#define BKP_DR14_D_Pos (0U)
+#define BKP_DR14_D_Msk (0xFFFFU << BKP_DR14_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR14_D BKP_DR14_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR15 register *******************/
+#define BKP_DR15_D_Pos (0U)
+#define BKP_DR15_D_Msk (0xFFFFU << BKP_DR15_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR15_D BKP_DR15_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR16 register *******************/
+#define BKP_DR16_D_Pos (0U)
+#define BKP_DR16_D_Msk (0xFFFFU << BKP_DR16_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR16_D BKP_DR16_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR17 register *******************/
+#define BKP_DR17_D_Pos (0U)
+#define BKP_DR17_D_Msk (0xFFFFU << BKP_DR17_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR17_D BKP_DR17_D_Msk /*!< Backup data */
+
+/****************** Bit definition for BKP_DR18 register ********************/
+#define BKP_DR18_D_Pos (0U)
+#define BKP_DR18_D_Msk (0xFFFFU << BKP_DR18_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR18_D BKP_DR18_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR19 register *******************/
+#define BKP_DR19_D_Pos (0U)
+#define BKP_DR19_D_Msk (0xFFFFU << BKP_DR19_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR19_D BKP_DR19_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR20 register *******************/
+#define BKP_DR20_D_Pos (0U)
+#define BKP_DR20_D_Msk (0xFFFFU << BKP_DR20_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR20_D BKP_DR20_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR21 register *******************/
+#define BKP_DR21_D_Pos (0U)
+#define BKP_DR21_D_Msk (0xFFFFU << BKP_DR21_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR21_D BKP_DR21_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR22 register *******************/
+#define BKP_DR22_D_Pos (0U)
+#define BKP_DR22_D_Msk (0xFFFFU << BKP_DR22_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR22_D BKP_DR22_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR23 register *******************/
+#define BKP_DR23_D_Pos (0U)
+#define BKP_DR23_D_Msk (0xFFFFU << BKP_DR23_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR23_D BKP_DR23_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR24 register *******************/
+#define BKP_DR24_D_Pos (0U)
+#define BKP_DR24_D_Msk (0xFFFFU << BKP_DR24_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR24_D BKP_DR24_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR25 register *******************/
+#define BKP_DR25_D_Pos (0U)
+#define BKP_DR25_D_Msk (0xFFFFU << BKP_DR25_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR25_D BKP_DR25_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR26 register *******************/
+#define BKP_DR26_D_Pos (0U)
+#define BKP_DR26_D_Msk (0xFFFFU << BKP_DR26_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR26_D BKP_DR26_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR27 register *******************/
+#define BKP_DR27_D_Pos (0U)
+#define BKP_DR27_D_Msk (0xFFFFU << BKP_DR27_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR27_D BKP_DR27_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR28 register *******************/
+#define BKP_DR28_D_Pos (0U)
+#define BKP_DR28_D_Msk (0xFFFFU << BKP_DR28_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR28_D BKP_DR28_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR29 register *******************/
+#define BKP_DR29_D_Pos (0U)
+#define BKP_DR29_D_Msk (0xFFFFU << BKP_DR29_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR29_D BKP_DR29_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR30 register *******************/
+#define BKP_DR30_D_Pos (0U)
+#define BKP_DR30_D_Msk (0xFFFFU << BKP_DR30_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR30_D BKP_DR30_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR31 register *******************/
+#define BKP_DR31_D_Pos (0U)
+#define BKP_DR31_D_Msk (0xFFFFU << BKP_DR31_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR31_D BKP_DR31_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR32 register *******************/
+#define BKP_DR32_D_Pos (0U)
+#define BKP_DR32_D_Msk (0xFFFFU << BKP_DR32_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR32_D BKP_DR32_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR33 register *******************/
+#define BKP_DR33_D_Pos (0U)
+#define BKP_DR33_D_Msk (0xFFFFU << BKP_DR33_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR33_D BKP_DR33_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR34 register *******************/
+#define BKP_DR34_D_Pos (0U)
+#define BKP_DR34_D_Msk (0xFFFFU << BKP_DR34_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR34_D BKP_DR34_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR35 register *******************/
+#define BKP_DR35_D_Pos (0U)
+#define BKP_DR35_D_Msk (0xFFFFU << BKP_DR35_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR35_D BKP_DR35_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR36 register *******************/
+#define BKP_DR36_D_Pos (0U)
+#define BKP_DR36_D_Msk (0xFFFFU << BKP_DR36_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR36_D BKP_DR36_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR37 register *******************/
+#define BKP_DR37_D_Pos (0U)
+#define BKP_DR37_D_Msk (0xFFFFU << BKP_DR37_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR37_D BKP_DR37_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR38 register *******************/
+#define BKP_DR38_D_Pos (0U)
+#define BKP_DR38_D_Msk (0xFFFFU << BKP_DR38_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR38_D BKP_DR38_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR39 register *******************/
+#define BKP_DR39_D_Pos (0U)
+#define BKP_DR39_D_Msk (0xFFFFU << BKP_DR39_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR39_D BKP_DR39_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR40 register *******************/
+#define BKP_DR40_D_Pos (0U)
+#define BKP_DR40_D_Msk (0xFFFFU << BKP_DR40_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR40_D BKP_DR40_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR41 register *******************/
+#define BKP_DR41_D_Pos (0U)
+#define BKP_DR41_D_Msk (0xFFFFU << BKP_DR41_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR41_D BKP_DR41_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR42 register *******************/
+#define BKP_DR42_D_Pos (0U)
+#define BKP_DR42_D_Msk (0xFFFFU << BKP_DR42_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR42_D BKP_DR42_D_Msk /*!< Backup data */
+
+#define RTC_BKP_NUMBER 42
+
+/****************** Bit definition for BKP_RTCCR register *******************/
+#define BKP_RTCCR_CAL_Pos (0U)
+#define BKP_RTCCR_CAL_Msk (0x7FU << BKP_RTCCR_CAL_Pos) /*!< 0x0000007F */
+#define BKP_RTCCR_CAL BKP_RTCCR_CAL_Msk /*!< Calibration value */
+#define BKP_RTCCR_CCO_Pos (7U)
+#define BKP_RTCCR_CCO_Msk (0x1U << BKP_RTCCR_CCO_Pos) /*!< 0x00000080 */
+#define BKP_RTCCR_CCO BKP_RTCCR_CCO_Msk /*!< Calibration Clock Output */
+#define BKP_RTCCR_ASOE_Pos (8U)
+#define BKP_RTCCR_ASOE_Msk (0x1U << BKP_RTCCR_ASOE_Pos) /*!< 0x00000100 */
+#define BKP_RTCCR_ASOE BKP_RTCCR_ASOE_Msk /*!< Alarm or Second Output Enable */
+#define BKP_RTCCR_ASOS_Pos (9U)
+#define BKP_RTCCR_ASOS_Msk (0x1U << BKP_RTCCR_ASOS_Pos) /*!< 0x00000200 */
+#define BKP_RTCCR_ASOS BKP_RTCCR_ASOS_Msk /*!< Alarm or Second Output Selection */
+
+/******************** Bit definition for BKP_CR register ********************/
+#define BKP_CR_TPE_Pos (0U)
+#define BKP_CR_TPE_Msk (0x1U << BKP_CR_TPE_Pos) /*!< 0x00000001 */
+#define BKP_CR_TPE BKP_CR_TPE_Msk /*!< TAMPER pin enable */
+#define BKP_CR_TPAL_Pos (1U)
+#define BKP_CR_TPAL_Msk (0x1U << BKP_CR_TPAL_Pos) /*!< 0x00000002 */
+#define BKP_CR_TPAL BKP_CR_TPAL_Msk /*!< TAMPER pin active level */
+
+/******************* Bit definition for BKP_CSR register ********************/
+#define BKP_CSR_CTE_Pos (0U)
+#define BKP_CSR_CTE_Msk (0x1U << BKP_CSR_CTE_Pos) /*!< 0x00000001 */
+#define BKP_CSR_CTE BKP_CSR_CTE_Msk /*!< Clear Tamper event */
+#define BKP_CSR_CTI_Pos (1U)
+#define BKP_CSR_CTI_Msk (0x1U << BKP_CSR_CTI_Pos) /*!< 0x00000002 */
+#define BKP_CSR_CTI BKP_CSR_CTI_Msk /*!< Clear Tamper Interrupt */
+#define BKP_CSR_TPIE_Pos (2U)
+#define BKP_CSR_TPIE_Msk (0x1U << BKP_CSR_TPIE_Pos) /*!< 0x00000004 */
+#define BKP_CSR_TPIE BKP_CSR_TPIE_Msk /*!< TAMPER Pin interrupt enable */
+#define BKP_CSR_TEF_Pos (8U)
+#define BKP_CSR_TEF_Msk (0x1U << BKP_CSR_TEF_Pos) /*!< 0x00000100 */
+#define BKP_CSR_TEF BKP_CSR_TEF_Msk /*!< Tamper Event Flag */
+#define BKP_CSR_TIF_Pos (9U)
+#define BKP_CSR_TIF_Msk (0x1U << BKP_CSR_TIF_Pos) /*!< 0x00000200 */
+#define BKP_CSR_TIF BKP_CSR_TIF_Msk /*!< Tamper Interrupt Flag */
+
+/******************************************************************************/
+/* */
+/* Reset and Clock Control */
+/* */
+/******************************************************************************/
+
+/******************** Bit definition for RCC_CR register ********************/
+#define RCC_CR_HSION_Pos (0U)
+#define RCC_CR_HSION_Msk (0x1U << RCC_CR_HSION_Pos) /*!< 0x00000001 */
+#define RCC_CR_HSION RCC_CR_HSION_Msk /*!< Internal High Speed clock enable */
+#define RCC_CR_HSIRDY_Pos (1U)
+#define RCC_CR_HSIRDY_Msk (0x1U << RCC_CR_HSIRDY_Pos) /*!< 0x00000002 */
+#define RCC_CR_HSIRDY RCC_CR_HSIRDY_Msk /*!< Internal High Speed clock ready flag */
+#define RCC_CR_HSITRIM_Pos (3U)
+#define RCC_CR_HSITRIM_Msk (0x1FU << RCC_CR_HSITRIM_Pos) /*!< 0x000000F8 */
+#define RCC_CR_HSITRIM RCC_CR_HSITRIM_Msk /*!< Internal High Speed clock trimming */
+#define RCC_CR_HSICAL_Pos (8U)
+#define RCC_CR_HSICAL_Msk (0xFFU << RCC_CR_HSICAL_Pos) /*!< 0x0000FF00 */
+#define RCC_CR_HSICAL RCC_CR_HSICAL_Msk /*!< Internal High Speed clock Calibration */
+#define RCC_CR_HSEON_Pos (16U)
+#define RCC_CR_HSEON_Msk (0x1U << RCC_CR_HSEON_Pos) /*!< 0x00010000 */
+#define RCC_CR_HSEON RCC_CR_HSEON_Msk /*!< External High Speed clock enable */
+#define RCC_CR_HSERDY_Pos (17U)
+#define RCC_CR_HSERDY_Msk (0x1U << RCC_CR_HSERDY_Pos) /*!< 0x00020000 */
+#define RCC_CR_HSERDY RCC_CR_HSERDY_Msk /*!< External High Speed clock ready flag */
+#define RCC_CR_HSEBYP_Pos (18U)
+#define RCC_CR_HSEBYP_Msk (0x1U << RCC_CR_HSEBYP_Pos) /*!< 0x00040000 */
+#define RCC_CR_HSEBYP RCC_CR_HSEBYP_Msk /*!< External High Speed clock Bypass */
+#define RCC_CR_CSSON_Pos (19U)
+#define RCC_CR_CSSON_Msk (0x1U << RCC_CR_CSSON_Pos) /*!< 0x00080000 */
+#define RCC_CR_CSSON RCC_CR_CSSON_Msk /*!< Clock Security System enable */
+#define RCC_CR_PLLON_Pos (24U)
+#define RCC_CR_PLLON_Msk (0x1U << RCC_CR_PLLON_Pos) /*!< 0x01000000 */
+#define RCC_CR_PLLON RCC_CR_PLLON_Msk /*!< PLL enable */
+#define RCC_CR_PLLRDY_Pos (25U)
+#define RCC_CR_PLLRDY_Msk (0x1U << RCC_CR_PLLRDY_Pos) /*!< 0x02000000 */
+#define RCC_CR_PLLRDY RCC_CR_PLLRDY_Msk /*!< PLL clock ready flag */
+
+
+/******************* Bit definition for RCC_CFGR register *******************/
+/*!< SW configuration */
+#define RCC_CFGR_SW_Pos (0U)
+#define RCC_CFGR_SW_Msk (0x3U << RCC_CFGR_SW_Pos) /*!< 0x00000003 */
+#define RCC_CFGR_SW RCC_CFGR_SW_Msk /*!< SW[1:0] bits (System clock Switch) */
+#define RCC_CFGR_SW_0 (0x1U << RCC_CFGR_SW_Pos) /*!< 0x00000001 */
+#define RCC_CFGR_SW_1 (0x2U << RCC_CFGR_SW_Pos) /*!< 0x00000002 */
+
+#define RCC_CFGR_SW_HSI ((uint32_t)0x00000000) /*!< HSI selected as system clock */
+#define RCC_CFGR_SW_HSE ((uint32_t)0x00000001) /*!< HSE selected as system clock */
+#define RCC_CFGR_SW_PLL ((uint32_t)0x00000002) /*!< PLL selected as system clock */
+
+/*!< SWS configuration */
+#define RCC_CFGR_SWS_Pos (2U)
+#define RCC_CFGR_SWS_Msk (0x3U << RCC_CFGR_SWS_Pos) /*!< 0x0000000C */
+#define RCC_CFGR_SWS RCC_CFGR_SWS_Msk /*!< SWS[1:0] bits (System Clock Switch Status) */
+#define RCC_CFGR_SWS_0 (0x1U << RCC_CFGR_SWS_Pos) /*!< 0x00000004 */
+#define RCC_CFGR_SWS_1 (0x2U << RCC_CFGR_SWS_Pos) /*!< 0x00000008 */
+
+#define RCC_CFGR_SWS_HSI ((uint32_t)0x00000000) /*!< HSI oscillator used as system clock */
+#define RCC_CFGR_SWS_HSE ((uint32_t)0x00000004) /*!< HSE oscillator used as system clock */
+#define RCC_CFGR_SWS_PLL ((uint32_t)0x00000008) /*!< PLL used as system clock */
+
+/*!< HPRE configuration */
+#define RCC_CFGR_HPRE_Pos (4U)
+#define RCC_CFGR_HPRE_Msk (0xFU << RCC_CFGR_HPRE_Pos) /*!< 0x000000F0 */
+#define RCC_CFGR_HPRE RCC_CFGR_HPRE_Msk /*!< HPRE[3:0] bits (AHB prescaler) */
+#define RCC_CFGR_HPRE_0 (0x1U << RCC_CFGR_HPRE_Pos) /*!< 0x00000010 */
+#define RCC_CFGR_HPRE_1 (0x2U << RCC_CFGR_HPRE_Pos) /*!< 0x00000020 */
+#define RCC_CFGR_HPRE_2 (0x4U << RCC_CFGR_HPRE_Pos) /*!< 0x00000040 */
+#define RCC_CFGR_HPRE_3 (0x8U << RCC_CFGR_HPRE_Pos) /*!< 0x00000080 */
+
+#define RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000) /*!< SYSCLK not divided */
+#define RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080) /*!< SYSCLK divided by 2 */
+#define RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090) /*!< SYSCLK divided by 4 */
+#define RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0) /*!< SYSCLK divided by 8 */
+#define RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0) /*!< SYSCLK divided by 16 */
+#define RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0) /*!< SYSCLK divided by 64 */
+#define RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0) /*!< SYSCLK divided by 128 */
+#define RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0) /*!< SYSCLK divided by 256 */
+#define RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0) /*!< SYSCLK divided by 512 */
+
+/*!< PPRE1 configuration */
+#define RCC_CFGR_PPRE1_Pos (8U)
+#define RCC_CFGR_PPRE1_Msk (0x7U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000700 */
+#define RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_Msk /*!< PRE1[2:0] bits (APB1 prescaler) */
+#define RCC_CFGR_PPRE1_0 (0x1U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000100 */
+#define RCC_CFGR_PPRE1_1 (0x2U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000200 */
+#define RCC_CFGR_PPRE1_2 (0x4U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000400 */
+
+#define RCC_CFGR_PPRE1_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */
+#define RCC_CFGR_PPRE1_DIV2 ((uint32_t)0x00000400) /*!< HCLK divided by 2 */
+#define RCC_CFGR_PPRE1_DIV4 ((uint32_t)0x00000500) /*!< HCLK divided by 4 */
+#define RCC_CFGR_PPRE1_DIV8 ((uint32_t)0x00000600) /*!< HCLK divided by 8 */
+#define RCC_CFGR_PPRE1_DIV16 ((uint32_t)0x00000700) /*!< HCLK divided by 16 */
+
+/*!< PPRE2 configuration */
+#define RCC_CFGR_PPRE2_Pos (11U)
+#define RCC_CFGR_PPRE2_Msk (0x7U << RCC_CFGR_PPRE2_Pos) /*!< 0x00003800 */
+#define RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_Msk /*!< PRE2[2:0] bits (APB2 prescaler) */
+#define RCC_CFGR_PPRE2_0 (0x1U << RCC_CFGR_PPRE2_Pos) /*!< 0x00000800 */
+#define RCC_CFGR_PPRE2_1 (0x2U << RCC_CFGR_PPRE2_Pos) /*!< 0x00001000 */
+#define RCC_CFGR_PPRE2_2 (0x4U << RCC_CFGR_PPRE2_Pos) /*!< 0x00002000 */
+
+#define RCC_CFGR_PPRE2_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */
+#define RCC_CFGR_PPRE2_DIV2 ((uint32_t)0x00002000) /*!< HCLK divided by 2 */
+#define RCC_CFGR_PPRE2_DIV4 ((uint32_t)0x00002800) /*!< HCLK divided by 4 */
+#define RCC_CFGR_PPRE2_DIV8 ((uint32_t)0x00003000) /*!< HCLK divided by 8 */
+#define RCC_CFGR_PPRE2_DIV16 ((uint32_t)0x00003800) /*!< HCLK divided by 16 */
+
+/*!< ADCPPRE configuration */
+#define RCC_CFGR_ADCPRE_Pos (14U)
+#define RCC_CFGR_ADCPRE_Msk (0x3U << RCC_CFGR_ADCPRE_Pos) /*!< 0x0000C000 */
+#define RCC_CFGR_ADCPRE RCC_CFGR_ADCPRE_Msk /*!< ADCPRE[1:0] bits (ADC prescaler) */
+#define RCC_CFGR_ADCPRE_0 (0x1U << RCC_CFGR_ADCPRE_Pos) /*!< 0x00004000 */
+#define RCC_CFGR_ADCPRE_1 (0x2U << RCC_CFGR_ADCPRE_Pos) /*!< 0x00008000 */
+
+#define RCC_CFGR_ADCPRE_DIV2 ((uint32_t)0x00000000) /*!< PCLK2 divided by 2 */
+#define RCC_CFGR_ADCPRE_DIV4 ((uint32_t)0x00004000) /*!< PCLK2 divided by 4 */
+#define RCC_CFGR_ADCPRE_DIV6 ((uint32_t)0x00008000) /*!< PCLK2 divided by 6 */
+#define RCC_CFGR_ADCPRE_DIV8 ((uint32_t)0x0000C000) /*!< PCLK2 divided by 8 */
+
+#define RCC_CFGR_PLLSRC_Pos (16U)
+#define RCC_CFGR_PLLSRC_Msk (0x1U << RCC_CFGR_PLLSRC_Pos) /*!< 0x00010000 */
+#define RCC_CFGR_PLLSRC RCC_CFGR_PLLSRC_Msk /*!< PLL entry clock source */
+
+#define RCC_CFGR_PLLXTPRE_Pos (17U)
+#define RCC_CFGR_PLLXTPRE_Msk (0x1U << RCC_CFGR_PLLXTPRE_Pos) /*!< 0x00020000 */
+#define RCC_CFGR_PLLXTPRE RCC_CFGR_PLLXTPRE_Msk /*!< HSE divider for PLL entry */
+
+/*!< PLLMUL configuration */
+#define RCC_CFGR_PLLMULL_Pos (18U)
+#define RCC_CFGR_PLLMULL_Msk (0xFU << RCC_CFGR_PLLMULL_Pos) /*!< 0x003C0000 */
+#define RCC_CFGR_PLLMULL RCC_CFGR_PLLMULL_Msk /*!< PLLMUL[3:0] bits (PLL multiplication factor) */
+#define RCC_CFGR_PLLMULL_0 (0x1U << RCC_CFGR_PLLMULL_Pos) /*!< 0x00040000 */
+#define RCC_CFGR_PLLMULL_1 (0x2U << RCC_CFGR_PLLMULL_Pos) /*!< 0x00080000 */
+#define RCC_CFGR_PLLMULL_2 (0x4U << RCC_CFGR_PLLMULL_Pos) /*!< 0x00100000 */
+#define RCC_CFGR_PLLMULL_3 (0x8U << RCC_CFGR_PLLMULL_Pos) /*!< 0x00200000 */
+
+#define RCC_CFGR_PLLXTPRE_HSE ((uint32_t)0x00000000) /*!< HSE clock not divided for PLL entry */
+#define RCC_CFGR_PLLXTPRE_HSE_DIV2 ((uint32_t)0x00020000) /*!< HSE clock divided by 2 for PLL entry */
+
+#define RCC_CFGR_PLLMULL2 ((uint32_t)0x00000000) /*!< PLL input clock*2 */
+#define RCC_CFGR_PLLMULL3_Pos (18U)
+#define RCC_CFGR_PLLMULL3_Msk (0x1U << RCC_CFGR_PLLMULL3_Pos) /*!< 0x00040000 */
+#define RCC_CFGR_PLLMULL3 RCC_CFGR_PLLMULL3_Msk /*!< PLL input clock*3 */
+#define RCC_CFGR_PLLMULL4_Pos (19U)
+#define RCC_CFGR_PLLMULL4_Msk (0x1U << RCC_CFGR_PLLMULL4_Pos) /*!< 0x00080000 */
+#define RCC_CFGR_PLLMULL4 RCC_CFGR_PLLMULL4_Msk /*!< PLL input clock*4 */
+#define RCC_CFGR_PLLMULL5_Pos (18U)
+#define RCC_CFGR_PLLMULL5_Msk (0x3U << RCC_CFGR_PLLMULL5_Pos) /*!< 0x000C0000 */
+#define RCC_CFGR_PLLMULL5 RCC_CFGR_PLLMULL5_Msk /*!< PLL input clock*5 */
+#define RCC_CFGR_PLLMULL6_Pos (20U)
+#define RCC_CFGR_PLLMULL6_Msk (0x1U << RCC_CFGR_PLLMULL6_Pos) /*!< 0x00100000 */
+#define RCC_CFGR_PLLMULL6 RCC_CFGR_PLLMULL6_Msk /*!< PLL input clock*6 */
+#define RCC_CFGR_PLLMULL7_Pos (18U)
+#define RCC_CFGR_PLLMULL7_Msk (0x5U << RCC_CFGR_PLLMULL7_Pos) /*!< 0x00140000 */
+#define RCC_CFGR_PLLMULL7 RCC_CFGR_PLLMULL7_Msk /*!< PLL input clock*7 */
+#define RCC_CFGR_PLLMULL8_Pos (19U)
+#define RCC_CFGR_PLLMULL8_Msk (0x3U << RCC_CFGR_PLLMULL8_Pos) /*!< 0x00180000 */
+#define RCC_CFGR_PLLMULL8 RCC_CFGR_PLLMULL8_Msk /*!< PLL input clock*8 */
+#define RCC_CFGR_PLLMULL9_Pos (18U)
+#define RCC_CFGR_PLLMULL9_Msk (0x7U << RCC_CFGR_PLLMULL9_Pos) /*!< 0x001C0000 */
+#define RCC_CFGR_PLLMULL9 RCC_CFGR_PLLMULL9_Msk /*!< PLL input clock*9 */
+#define RCC_CFGR_PLLMULL10_Pos (21U)
+#define RCC_CFGR_PLLMULL10_Msk (0x1U << RCC_CFGR_PLLMULL10_Pos) /*!< 0x00200000 */
+#define RCC_CFGR_PLLMULL10 RCC_CFGR_PLLMULL10_Msk /*!< PLL input clock10 */
+#define RCC_CFGR_PLLMULL11_Pos (18U)
+#define RCC_CFGR_PLLMULL11_Msk (0x9U << RCC_CFGR_PLLMULL11_Pos) /*!< 0x00240000 */
+#define RCC_CFGR_PLLMULL11 RCC_CFGR_PLLMULL11_Msk /*!< PLL input clock*11 */
+#define RCC_CFGR_PLLMULL12_Pos (19U)
+#define RCC_CFGR_PLLMULL12_Msk (0x5U << RCC_CFGR_PLLMULL12_Pos) /*!< 0x00280000 */
+#define RCC_CFGR_PLLMULL12 RCC_CFGR_PLLMULL12_Msk /*!< PLL input clock*12 */
+#define RCC_CFGR_PLLMULL13_Pos (18U)
+#define RCC_CFGR_PLLMULL13_Msk (0xBU << RCC_CFGR_PLLMULL13_Pos) /*!< 0x002C0000 */
+#define RCC_CFGR_PLLMULL13 RCC_CFGR_PLLMULL13_Msk /*!< PLL input clock*13 */
+#define RCC_CFGR_PLLMULL14_Pos (20U)
+#define RCC_CFGR_PLLMULL14_Msk (0x3U << RCC_CFGR_PLLMULL14_Pos) /*!< 0x00300000 */
+#define RCC_CFGR_PLLMULL14 RCC_CFGR_PLLMULL14_Msk /*!< PLL input clock*14 */
+#define RCC_CFGR_PLLMULL15_Pos (18U)
+#define RCC_CFGR_PLLMULL15_Msk (0xDU << RCC_CFGR_PLLMULL15_Pos) /*!< 0x00340000 */
+#define RCC_CFGR_PLLMULL15 RCC_CFGR_PLLMULL15_Msk /*!< PLL input clock*15 */
+#define RCC_CFGR_PLLMULL16_Pos (19U)
+#define RCC_CFGR_PLLMULL16_Msk (0x7U << RCC_CFGR_PLLMULL16_Pos) /*!< 0x00380000 */
+#define RCC_CFGR_PLLMULL16 RCC_CFGR_PLLMULL16_Msk /*!< PLL input clock*16 */
+
+/*!< MCO configuration */
+#define RCC_CFGR_MCO_Pos (24U)
+#define RCC_CFGR_MCO_Msk (0x7U << RCC_CFGR_MCO_Pos) /*!< 0x07000000 */
+#define RCC_CFGR_MCO RCC_CFGR_MCO_Msk /*!< MCO[2:0] bits (Microcontroller Clock Output) */
+#define RCC_CFGR_MCO_0 (0x1U << RCC_CFGR_MCO_Pos) /*!< 0x01000000 */
+#define RCC_CFGR_MCO_1 (0x2U << RCC_CFGR_MCO_Pos) /*!< 0x02000000 */
+#define RCC_CFGR_MCO_2 (0x4U << RCC_CFGR_MCO_Pos) /*!< 0x04000000 */
+
+#define RCC_CFGR_MCO_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */
+#define RCC_CFGR_MCO_SYSCLK ((uint32_t)0x04000000) /*!< System clock selected as MCO source */
+#define RCC_CFGR_MCO_HSI ((uint32_t)0x05000000) /*!< HSI clock selected as MCO source */
+#define RCC_CFGR_MCO_HSE ((uint32_t)0x06000000) /*!< HSE clock selected as MCO source */
+#define RCC_CFGR_MCO_PLLCLK_DIV2 ((uint32_t)0x07000000) /*!< PLL clock divided by 2 selected as MCO source */
+
+ /* Reference defines */
+ #define RCC_CFGR_MCOSEL RCC_CFGR_MCO
+ #define RCC_CFGR_MCOSEL_0 RCC_CFGR_MCO_0
+ #define RCC_CFGR_MCOSEL_1 RCC_CFGR_MCO_1
+ #define RCC_CFGR_MCOSEL_2 RCC_CFGR_MCO_2
+ #define RCC_CFGR_MCOSEL_NOCLOCK RCC_CFGR_MCO_NOCLOCK
+ #define RCC_CFGR_MCOSEL_SYSCLK RCC_CFGR_MCO_SYSCLK
+ #define RCC_CFGR_MCOSEL_HSI RCC_CFGR_MCO_HSI
+ #define RCC_CFGR_MCOSEL_HSE RCC_CFGR_MCO_HSE
+ #define RCC_CFGR_MCOSEL_PLL_DIV2 RCC_CFGR_MCO_PLLCLK_DIV2
+
+/*!<****************** Bit definition for RCC_CIR register ********************/
+#define RCC_CIR_LSIRDYF_Pos (0U)
+#define RCC_CIR_LSIRDYF_Msk (0x1U << RCC_CIR_LSIRDYF_Pos) /*!< 0x00000001 */
+#define RCC_CIR_LSIRDYF RCC_CIR_LSIRDYF_Msk /*!< LSI Ready Interrupt flag */
+#define RCC_CIR_LSERDYF_Pos (1U)
+#define RCC_CIR_LSERDYF_Msk (0x1U << RCC_CIR_LSERDYF_Pos) /*!< 0x00000002 */
+#define RCC_CIR_LSERDYF RCC_CIR_LSERDYF_Msk /*!< LSE Ready Interrupt flag */
+#define RCC_CIR_HSIRDYF_Pos (2U)
+#define RCC_CIR_HSIRDYF_Msk (0x1U << RCC_CIR_HSIRDYF_Pos) /*!< 0x00000004 */
+#define RCC_CIR_HSIRDYF RCC_CIR_HSIRDYF_Msk /*!< HSI Ready Interrupt flag */
+#define RCC_CIR_HSERDYF_Pos (3U)
+#define RCC_CIR_HSERDYF_Msk (0x1U << RCC_CIR_HSERDYF_Pos) /*!< 0x00000008 */
+#define RCC_CIR_HSERDYF RCC_CIR_HSERDYF_Msk /*!< HSE Ready Interrupt flag */
+#define RCC_CIR_PLLRDYF_Pos (4U)
+#define RCC_CIR_PLLRDYF_Msk (0x1U << RCC_CIR_PLLRDYF_Pos) /*!< 0x00000010 */
+#define RCC_CIR_PLLRDYF RCC_CIR_PLLRDYF_Msk /*!< PLL Ready Interrupt flag */
+#define RCC_CIR_CSSF_Pos (7U)
+#define RCC_CIR_CSSF_Msk (0x1U << RCC_CIR_CSSF_Pos) /*!< 0x00000080 */
+#define RCC_CIR_CSSF RCC_CIR_CSSF_Msk /*!< Clock Security System Interrupt flag */
+#define RCC_CIR_LSIRDYIE_Pos (8U)
+#define RCC_CIR_LSIRDYIE_Msk (0x1U << RCC_CIR_LSIRDYIE_Pos) /*!< 0x00000100 */
+#define RCC_CIR_LSIRDYIE RCC_CIR_LSIRDYIE_Msk /*!< LSI Ready Interrupt Enable */
+#define RCC_CIR_LSERDYIE_Pos (9U)
+#define RCC_CIR_LSERDYIE_Msk (0x1U << RCC_CIR_LSERDYIE_Pos) /*!< 0x00000200 */
+#define RCC_CIR_LSERDYIE RCC_CIR_LSERDYIE_Msk /*!< LSE Ready Interrupt Enable */
+#define RCC_CIR_HSIRDYIE_Pos (10U)
+#define RCC_CIR_HSIRDYIE_Msk (0x1U << RCC_CIR_HSIRDYIE_Pos) /*!< 0x00000400 */
+#define RCC_CIR_HSIRDYIE RCC_CIR_HSIRDYIE_Msk /*!< HSI Ready Interrupt Enable */
+#define RCC_CIR_HSERDYIE_Pos (11U)
+#define RCC_CIR_HSERDYIE_Msk (0x1U << RCC_CIR_HSERDYIE_Pos) /*!< 0x00000800 */
+#define RCC_CIR_HSERDYIE RCC_CIR_HSERDYIE_Msk /*!< HSE Ready Interrupt Enable */
+#define RCC_CIR_PLLRDYIE_Pos (12U)
+#define RCC_CIR_PLLRDYIE_Msk (0x1U << RCC_CIR_PLLRDYIE_Pos) /*!< 0x00001000 */
+#define RCC_CIR_PLLRDYIE RCC_CIR_PLLRDYIE_Msk /*!< PLL Ready Interrupt Enable */
+#define RCC_CIR_LSIRDYC_Pos (16U)
+#define RCC_CIR_LSIRDYC_Msk (0x1U << RCC_CIR_LSIRDYC_Pos) /*!< 0x00010000 */
+#define RCC_CIR_LSIRDYC RCC_CIR_LSIRDYC_Msk /*!< LSI Ready Interrupt Clear */
+#define RCC_CIR_LSERDYC_Pos (17U)
+#define RCC_CIR_LSERDYC_Msk (0x1U << RCC_CIR_LSERDYC_Pos) /*!< 0x00020000 */
+#define RCC_CIR_LSERDYC RCC_CIR_LSERDYC_Msk /*!< LSE Ready Interrupt Clear */
+#define RCC_CIR_HSIRDYC_Pos (18U)
+#define RCC_CIR_HSIRDYC_Msk (0x1U << RCC_CIR_HSIRDYC_Pos) /*!< 0x00040000 */
+#define RCC_CIR_HSIRDYC RCC_CIR_HSIRDYC_Msk /*!< HSI Ready Interrupt Clear */
+#define RCC_CIR_HSERDYC_Pos (19U)
+#define RCC_CIR_HSERDYC_Msk (0x1U << RCC_CIR_HSERDYC_Pos) /*!< 0x00080000 */
+#define RCC_CIR_HSERDYC RCC_CIR_HSERDYC_Msk /*!< HSE Ready Interrupt Clear */
+#define RCC_CIR_PLLRDYC_Pos (20U)
+#define RCC_CIR_PLLRDYC_Msk (0x1U << RCC_CIR_PLLRDYC_Pos) /*!< 0x00100000 */
+#define RCC_CIR_PLLRDYC RCC_CIR_PLLRDYC_Msk /*!< PLL Ready Interrupt Clear */
+#define RCC_CIR_CSSC_Pos (23U)
+#define RCC_CIR_CSSC_Msk (0x1U << RCC_CIR_CSSC_Pos) /*!< 0x00800000 */
+#define RCC_CIR_CSSC RCC_CIR_CSSC_Msk /*!< Clock Security System Interrupt Clear */
+
+
+/***************** Bit definition for RCC_APB2RSTR register *****************/
+#define RCC_APB2RSTR_AFIORST_Pos (0U)
+#define RCC_APB2RSTR_AFIORST_Msk (0x1U << RCC_APB2RSTR_AFIORST_Pos) /*!< 0x00000001 */
+#define RCC_APB2RSTR_AFIORST RCC_APB2RSTR_AFIORST_Msk /*!< Alternate Function I/O reset */
+#define RCC_APB2RSTR_IOPARST_Pos (2U)
+#define RCC_APB2RSTR_IOPARST_Msk (0x1U << RCC_APB2RSTR_IOPARST_Pos) /*!< 0x00000004 */
+#define RCC_APB2RSTR_IOPARST RCC_APB2RSTR_IOPARST_Msk /*!< I/O port A reset */
+#define RCC_APB2RSTR_IOPBRST_Pos (3U)
+#define RCC_APB2RSTR_IOPBRST_Msk (0x1U << RCC_APB2RSTR_IOPBRST_Pos) /*!< 0x00000008 */
+#define RCC_APB2RSTR_IOPBRST RCC_APB2RSTR_IOPBRST_Msk /*!< I/O port B reset */
+#define RCC_APB2RSTR_IOPCRST_Pos (4U)
+#define RCC_APB2RSTR_IOPCRST_Msk (0x1U << RCC_APB2RSTR_IOPCRST_Pos) /*!< 0x00000010 */
+#define RCC_APB2RSTR_IOPCRST RCC_APB2RSTR_IOPCRST_Msk /*!< I/O port C reset */
+#define RCC_APB2RSTR_IOPDRST_Pos (5U)
+#define RCC_APB2RSTR_IOPDRST_Msk (0x1U << RCC_APB2RSTR_IOPDRST_Pos) /*!< 0x00000020 */
+#define RCC_APB2RSTR_IOPDRST RCC_APB2RSTR_IOPDRST_Msk /*!< I/O port D reset */
+#define RCC_APB2RSTR_ADC1RST_Pos (9U)
+#define RCC_APB2RSTR_ADC1RST_Msk (0x1U << RCC_APB2RSTR_ADC1RST_Pos) /*!< 0x00000200 */
+#define RCC_APB2RSTR_ADC1RST RCC_APB2RSTR_ADC1RST_Msk /*!< ADC 1 interface reset */
+
+
+#define RCC_APB2RSTR_TIM1RST_Pos (11U)
+#define RCC_APB2RSTR_TIM1RST_Msk (0x1U << RCC_APB2RSTR_TIM1RST_Pos) /*!< 0x00000800 */
+#define RCC_APB2RSTR_TIM1RST RCC_APB2RSTR_TIM1RST_Msk /*!< TIM1 Timer reset */
+#define RCC_APB2RSTR_SPI1RST_Pos (12U)
+#define RCC_APB2RSTR_SPI1RST_Msk (0x1U << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */
+#define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk /*!< SPI 1 reset */
+#define RCC_APB2RSTR_USART1RST_Pos (14U)
+#define RCC_APB2RSTR_USART1RST_Msk (0x1U << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00004000 */
+#define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk /*!< USART1 reset */
+
+
+#define RCC_APB2RSTR_IOPERST_Pos (6U)
+#define RCC_APB2RSTR_IOPERST_Msk (0x1U << RCC_APB2RSTR_IOPERST_Pos) /*!< 0x00000040 */
+#define RCC_APB2RSTR_IOPERST RCC_APB2RSTR_IOPERST_Msk /*!< I/O port E reset */
+
+#define RCC_APB2RSTR_IOPFRST_Pos (7U)
+#define RCC_APB2RSTR_IOPFRST_Msk (0x1U << RCC_APB2RSTR_IOPFRST_Pos) /*!< 0x00000080 */
+#define RCC_APB2RSTR_IOPFRST RCC_APB2RSTR_IOPFRST_Msk /*!< I/O port F reset */
+#define RCC_APB2RSTR_IOPGRST_Pos (8U)
+#define RCC_APB2RSTR_IOPGRST_Msk (0x1U << RCC_APB2RSTR_IOPGRST_Pos) /*!< 0x00000100 */
+#define RCC_APB2RSTR_IOPGRST RCC_APB2RSTR_IOPGRST_Msk /*!< I/O port G reset */
+
+
+
+/***************** Bit definition for RCC_APB1RSTR register *****************/
+#define RCC_APB1RSTR_TIM2RST_Pos (0U)
+#define RCC_APB1RSTR_TIM2RST_Msk (0x1U << RCC_APB1RSTR_TIM2RST_Pos) /*!< 0x00000001 */
+#define RCC_APB1RSTR_TIM2RST RCC_APB1RSTR_TIM2RST_Msk /*!< Timer 2 reset */
+#define RCC_APB1RSTR_TIM3RST_Pos (1U)
+#define RCC_APB1RSTR_TIM3RST_Msk (0x1U << RCC_APB1RSTR_TIM3RST_Pos) /*!< 0x00000002 */
+#define RCC_APB1RSTR_TIM3RST RCC_APB1RSTR_TIM3RST_Msk /*!< Timer 3 reset */
+#define RCC_APB1RSTR_WWDGRST_Pos (11U)
+#define RCC_APB1RSTR_WWDGRST_Msk (0x1U << RCC_APB1RSTR_WWDGRST_Pos) /*!< 0x00000800 */
+#define RCC_APB1RSTR_WWDGRST RCC_APB1RSTR_WWDGRST_Msk /*!< Window Watchdog reset */
+#define RCC_APB1RSTR_USART2RST_Pos (17U)
+#define RCC_APB1RSTR_USART2RST_Msk (0x1U << RCC_APB1RSTR_USART2RST_Pos) /*!< 0x00020000 */
+#define RCC_APB1RSTR_USART2RST RCC_APB1RSTR_USART2RST_Msk /*!< USART 2 reset */
+#define RCC_APB1RSTR_I2C1RST_Pos (21U)
+#define RCC_APB1RSTR_I2C1RST_Msk (0x1U << RCC_APB1RSTR_I2C1RST_Pos) /*!< 0x00200000 */
+#define RCC_APB1RSTR_I2C1RST RCC_APB1RSTR_I2C1RST_Msk /*!< I2C 1 reset */
+
+
+#define RCC_APB1RSTR_BKPRST_Pos (27U)
+#define RCC_APB1RSTR_BKPRST_Msk (0x1U << RCC_APB1RSTR_BKPRST_Pos) /*!< 0x08000000 */
+#define RCC_APB1RSTR_BKPRST RCC_APB1RSTR_BKPRST_Msk /*!< Backup interface reset */
+#define RCC_APB1RSTR_PWRRST_Pos (28U)
+#define RCC_APB1RSTR_PWRRST_Msk (0x1U << RCC_APB1RSTR_PWRRST_Pos) /*!< 0x10000000 */
+#define RCC_APB1RSTR_PWRRST RCC_APB1RSTR_PWRRST_Msk /*!< Power interface reset */
+
+#define RCC_APB1RSTR_TIM4RST_Pos (2U)
+#define RCC_APB1RSTR_TIM4RST_Msk (0x1U << RCC_APB1RSTR_TIM4RST_Pos) /*!< 0x00000004 */
+#define RCC_APB1RSTR_TIM4RST RCC_APB1RSTR_TIM4RST_Msk /*!< Timer 4 reset */
+#define RCC_APB1RSTR_SPI2RST_Pos (14U)
+#define RCC_APB1RSTR_SPI2RST_Msk (0x1U << RCC_APB1RSTR_SPI2RST_Pos) /*!< 0x00004000 */
+#define RCC_APB1RSTR_SPI2RST RCC_APB1RSTR_SPI2RST_Msk /*!< SPI 2 reset */
+#define RCC_APB1RSTR_USART3RST_Pos (18U)
+#define RCC_APB1RSTR_USART3RST_Msk (0x1U << RCC_APB1RSTR_USART3RST_Pos) /*!< 0x00040000 */
+#define RCC_APB1RSTR_USART3RST RCC_APB1RSTR_USART3RST_Msk /*!< USART 3 reset */
+#define RCC_APB1RSTR_I2C2RST_Pos (22U)
+#define RCC_APB1RSTR_I2C2RST_Msk (0x1U << RCC_APB1RSTR_I2C2RST_Pos) /*!< 0x00400000 */
+#define RCC_APB1RSTR_I2C2RST RCC_APB1RSTR_I2C2RST_Msk /*!< I2C 2 reset */
+
+
+#define RCC_APB1RSTR_TIM5RST_Pos (3U)
+#define RCC_APB1RSTR_TIM5RST_Msk (0x1U << RCC_APB1RSTR_TIM5RST_Pos) /*!< 0x00000008 */
+#define RCC_APB1RSTR_TIM5RST RCC_APB1RSTR_TIM5RST_Msk /*!< Timer 5 reset */
+#define RCC_APB1RSTR_TIM6RST_Pos (4U)
+#define RCC_APB1RSTR_TIM6RST_Msk (0x1U << RCC_APB1RSTR_TIM6RST_Pos) /*!< 0x00000010 */
+#define RCC_APB1RSTR_TIM6RST RCC_APB1RSTR_TIM6RST_Msk /*!< Timer 6 reset */
+#define RCC_APB1RSTR_TIM7RST_Pos (5U)
+#define RCC_APB1RSTR_TIM7RST_Msk (0x1U << RCC_APB1RSTR_TIM7RST_Pos) /*!< 0x00000020 */
+#define RCC_APB1RSTR_TIM7RST RCC_APB1RSTR_TIM7RST_Msk /*!< Timer 7 reset */
+#define RCC_APB1RSTR_SPI3RST_Pos (15U)
+#define RCC_APB1RSTR_SPI3RST_Msk (0x1U << RCC_APB1RSTR_SPI3RST_Pos) /*!< 0x00008000 */
+#define RCC_APB1RSTR_SPI3RST RCC_APB1RSTR_SPI3RST_Msk /*!< SPI 3 reset */
+#define RCC_APB1RSTR_UART4RST_Pos (19U)
+#define RCC_APB1RSTR_UART4RST_Msk (0x1U << RCC_APB1RSTR_UART4RST_Pos) /*!< 0x00080000 */
+#define RCC_APB1RSTR_UART4RST RCC_APB1RSTR_UART4RST_Msk /*!< UART 4 reset */
+#define RCC_APB1RSTR_UART5RST_Pos (20U)
+#define RCC_APB1RSTR_UART5RST_Msk (0x1U << RCC_APB1RSTR_UART5RST_Pos) /*!< 0x00100000 */
+#define RCC_APB1RSTR_UART5RST RCC_APB1RSTR_UART5RST_Msk /*!< UART 5 reset */
+
+
+
+
+#define RCC_APB1RSTR_DACRST_Pos (29U)
+#define RCC_APB1RSTR_DACRST_Msk (0x1U << RCC_APB1RSTR_DACRST_Pos) /*!< 0x20000000 */
+#define RCC_APB1RSTR_DACRST RCC_APB1RSTR_DACRST_Msk /*!< DAC interface reset */
+
+/****************** Bit definition for RCC_AHBENR register ******************/
+#define RCC_AHBENR_DMA1EN_Pos (0U)
+#define RCC_AHBENR_DMA1EN_Msk (0x1U << RCC_AHBENR_DMA1EN_Pos) /*!< 0x00000001 */
+#define RCC_AHBENR_DMA1EN RCC_AHBENR_DMA1EN_Msk /*!< DMA1 clock enable */
+#define RCC_AHBENR_SRAMEN_Pos (2U)
+#define RCC_AHBENR_SRAMEN_Msk (0x1U << RCC_AHBENR_SRAMEN_Pos) /*!< 0x00000004 */
+#define RCC_AHBENR_SRAMEN RCC_AHBENR_SRAMEN_Msk /*!< SRAM interface clock enable */
+#define RCC_AHBENR_FLITFEN_Pos (4U)
+#define RCC_AHBENR_FLITFEN_Msk (0x1U << RCC_AHBENR_FLITFEN_Pos) /*!< 0x00000010 */
+#define RCC_AHBENR_FLITFEN RCC_AHBENR_FLITFEN_Msk /*!< FLITF clock enable */
+#define RCC_AHBENR_CRCEN_Pos (6U)
+#define RCC_AHBENR_CRCEN_Msk (0x1U << RCC_AHBENR_CRCEN_Pos) /*!< 0x00000040 */
+#define RCC_AHBENR_CRCEN RCC_AHBENR_CRCEN_Msk /*!< CRC clock enable */
+
+#define RCC_AHBENR_DMA2EN_Pos (1U)
+#define RCC_AHBENR_DMA2EN_Msk (0x1U << RCC_AHBENR_DMA2EN_Pos) /*!< 0x00000002 */
+#define RCC_AHBENR_DMA2EN RCC_AHBENR_DMA2EN_Msk /*!< DMA2 clock enable */
+
+#define RCC_AHBENR_FSMCEN_Pos (8U)
+#define RCC_AHBENR_FSMCEN_Msk (0x1U << RCC_AHBENR_FSMCEN_Pos) /*!< 0x00000100 */
+#define RCC_AHBENR_FSMCEN RCC_AHBENR_FSMCEN_Msk /*!< FSMC clock enable */
+
+
+/****************** Bit definition for RCC_APB2ENR register *****************/
+#define RCC_APB2ENR_AFIOEN_Pos (0U)
+#define RCC_APB2ENR_AFIOEN_Msk (0x1U << RCC_APB2ENR_AFIOEN_Pos) /*!< 0x00000001 */
+#define RCC_APB2ENR_AFIOEN RCC_APB2ENR_AFIOEN_Msk /*!< Alternate Function I/O clock enable */
+#define RCC_APB2ENR_IOPAEN_Pos (2U)
+#define RCC_APB2ENR_IOPAEN_Msk (0x1U << RCC_APB2ENR_IOPAEN_Pos) /*!< 0x00000004 */
+#define RCC_APB2ENR_IOPAEN RCC_APB2ENR_IOPAEN_Msk /*!< I/O port A clock enable */
+#define RCC_APB2ENR_IOPBEN_Pos (3U)
+#define RCC_APB2ENR_IOPBEN_Msk (0x1U << RCC_APB2ENR_IOPBEN_Pos) /*!< 0x00000008 */
+#define RCC_APB2ENR_IOPBEN RCC_APB2ENR_IOPBEN_Msk /*!< I/O port B clock enable */
+#define RCC_APB2ENR_IOPCEN_Pos (4U)
+#define RCC_APB2ENR_IOPCEN_Msk (0x1U << RCC_APB2ENR_IOPCEN_Pos) /*!< 0x00000010 */
+#define RCC_APB2ENR_IOPCEN RCC_APB2ENR_IOPCEN_Msk /*!< I/O port C clock enable */
+#define RCC_APB2ENR_IOPDEN_Pos (5U)
+#define RCC_APB2ENR_IOPDEN_Msk (0x1U << RCC_APB2ENR_IOPDEN_Pos) /*!< 0x00000020 */
+#define RCC_APB2ENR_IOPDEN RCC_APB2ENR_IOPDEN_Msk /*!< I/O port D clock enable */
+#define RCC_APB2ENR_ADC1EN_Pos (9U)
+#define RCC_APB2ENR_ADC1EN_Msk (0x1U << RCC_APB2ENR_ADC1EN_Pos) /*!< 0x00000200 */
+#define RCC_APB2ENR_ADC1EN RCC_APB2ENR_ADC1EN_Msk /*!< ADC 1 interface clock enable */
+
+
+#define RCC_APB2ENR_TIM1EN_Pos (11U)
+#define RCC_APB2ENR_TIM1EN_Msk (0x1U << RCC_APB2ENR_TIM1EN_Pos) /*!< 0x00000800 */
+#define RCC_APB2ENR_TIM1EN RCC_APB2ENR_TIM1EN_Msk /*!< TIM1 Timer clock enable */
+#define RCC_APB2ENR_SPI1EN_Pos (12U)
+#define RCC_APB2ENR_SPI1EN_Msk (0x1U << RCC_APB2ENR_SPI1EN_Pos) /*!< 0x00001000 */
+#define RCC_APB2ENR_SPI1EN RCC_APB2ENR_SPI1EN_Msk /*!< SPI 1 clock enable */
+#define RCC_APB2ENR_USART1EN_Pos (14U)
+#define RCC_APB2ENR_USART1EN_Msk (0x1U << RCC_APB2ENR_USART1EN_Pos) /*!< 0x00004000 */
+#define RCC_APB2ENR_USART1EN RCC_APB2ENR_USART1EN_Msk /*!< USART1 clock enable */
+
+
+#define RCC_APB2ENR_IOPEEN_Pos (6U)
+#define RCC_APB2ENR_IOPEEN_Msk (0x1U << RCC_APB2ENR_IOPEEN_Pos) /*!< 0x00000040 */
+#define RCC_APB2ENR_IOPEEN RCC_APB2ENR_IOPEEN_Msk /*!< I/O port E clock enable */
+
+#define RCC_APB2ENR_IOPFEN_Pos (7U)
+#define RCC_APB2ENR_IOPFEN_Msk (0x1U << RCC_APB2ENR_IOPFEN_Pos) /*!< 0x00000080 */
+#define RCC_APB2ENR_IOPFEN RCC_APB2ENR_IOPFEN_Msk /*!< I/O port F clock enable */
+#define RCC_APB2ENR_IOPGEN_Pos (8U)
+#define RCC_APB2ENR_IOPGEN_Msk (0x1U << RCC_APB2ENR_IOPGEN_Pos) /*!< 0x00000100 */
+#define RCC_APB2ENR_IOPGEN RCC_APB2ENR_IOPGEN_Msk /*!< I/O port G clock enable */
+
+
+
+/***************** Bit definition for RCC_APB1ENR register ******************/
+#define RCC_APB1ENR_TIM2EN_Pos (0U)
+#define RCC_APB1ENR_TIM2EN_Msk (0x1U << RCC_APB1ENR_TIM2EN_Pos) /*!< 0x00000001 */
+#define RCC_APB1ENR_TIM2EN RCC_APB1ENR_TIM2EN_Msk /*!< Timer 2 clock enabled*/
+#define RCC_APB1ENR_TIM3EN_Pos (1U)
+#define RCC_APB1ENR_TIM3EN_Msk (0x1U << RCC_APB1ENR_TIM3EN_Pos) /*!< 0x00000002 */
+#define RCC_APB1ENR_TIM3EN RCC_APB1ENR_TIM3EN_Msk /*!< Timer 3 clock enable */
+#define RCC_APB1ENR_WWDGEN_Pos (11U)
+#define RCC_APB1ENR_WWDGEN_Msk (0x1U << RCC_APB1ENR_WWDGEN_Pos) /*!< 0x00000800 */
+#define RCC_APB1ENR_WWDGEN RCC_APB1ENR_WWDGEN_Msk /*!< Window Watchdog clock enable */
+#define RCC_APB1ENR_USART2EN_Pos (17U)
+#define RCC_APB1ENR_USART2EN_Msk (0x1U << RCC_APB1ENR_USART2EN_Pos) /*!< 0x00020000 */
+#define RCC_APB1ENR_USART2EN RCC_APB1ENR_USART2EN_Msk /*!< USART 2 clock enable */
+#define RCC_APB1ENR_I2C1EN_Pos (21U)
+#define RCC_APB1ENR_I2C1EN_Msk (0x1U << RCC_APB1ENR_I2C1EN_Pos) /*!< 0x00200000 */
+#define RCC_APB1ENR_I2C1EN RCC_APB1ENR_I2C1EN_Msk /*!< I2C 1 clock enable */
+
+
+#define RCC_APB1ENR_BKPEN_Pos (27U)
+#define RCC_APB1ENR_BKPEN_Msk (0x1U << RCC_APB1ENR_BKPEN_Pos) /*!< 0x08000000 */
+#define RCC_APB1ENR_BKPEN RCC_APB1ENR_BKPEN_Msk /*!< Backup interface clock enable */
+#define RCC_APB1ENR_PWREN_Pos (28U)
+#define RCC_APB1ENR_PWREN_Msk (0x1U << RCC_APB1ENR_PWREN_Pos) /*!< 0x10000000 */
+#define RCC_APB1ENR_PWREN RCC_APB1ENR_PWREN_Msk /*!< Power interface clock enable */
+
+#define RCC_APB1ENR_TIM4EN_Pos (2U)
+#define RCC_APB1ENR_TIM4EN_Msk (0x1U << RCC_APB1ENR_TIM4EN_Pos) /*!< 0x00000004 */
+#define RCC_APB1ENR_TIM4EN RCC_APB1ENR_TIM4EN_Msk /*!< Timer 4 clock enable */
+#define RCC_APB1ENR_SPI2EN_Pos (14U)
+#define RCC_APB1ENR_SPI2EN_Msk (0x1U << RCC_APB1ENR_SPI2EN_Pos) /*!< 0x00004000 */
+#define RCC_APB1ENR_SPI2EN RCC_APB1ENR_SPI2EN_Msk /*!< SPI 2 clock enable */
+#define RCC_APB1ENR_USART3EN_Pos (18U)
+#define RCC_APB1ENR_USART3EN_Msk (0x1U << RCC_APB1ENR_USART3EN_Pos) /*!< 0x00040000 */
+#define RCC_APB1ENR_USART3EN RCC_APB1ENR_USART3EN_Msk /*!< USART 3 clock enable */
+#define RCC_APB1ENR_I2C2EN_Pos (22U)
+#define RCC_APB1ENR_I2C2EN_Msk (0x1U << RCC_APB1ENR_I2C2EN_Pos) /*!< 0x00400000 */
+#define RCC_APB1ENR_I2C2EN RCC_APB1ENR_I2C2EN_Msk /*!< I2C 2 clock enable */
+
+
+#define RCC_APB1ENR_TIM5EN_Pos (3U)
+#define RCC_APB1ENR_TIM5EN_Msk (0x1U << RCC_APB1ENR_TIM5EN_Pos) /*!< 0x00000008 */
+#define RCC_APB1ENR_TIM5EN RCC_APB1ENR_TIM5EN_Msk /*!< Timer 5 clock enable */
+#define RCC_APB1ENR_TIM6EN_Pos (4U)
+#define RCC_APB1ENR_TIM6EN_Msk (0x1U << RCC_APB1ENR_TIM6EN_Pos) /*!< 0x00000010 */
+#define RCC_APB1ENR_TIM6EN RCC_APB1ENR_TIM6EN_Msk /*!< Timer 6 clock enable */
+#define RCC_APB1ENR_TIM7EN_Pos (5U)
+#define RCC_APB1ENR_TIM7EN_Msk (0x1U << RCC_APB1ENR_TIM7EN_Pos) /*!< 0x00000020 */
+#define RCC_APB1ENR_TIM7EN RCC_APB1ENR_TIM7EN_Msk /*!< Timer 7 clock enable */
+#define RCC_APB1ENR_SPI3EN_Pos (15U)
+#define RCC_APB1ENR_SPI3EN_Msk (0x1U << RCC_APB1ENR_SPI3EN_Pos) /*!< 0x00008000 */
+#define RCC_APB1ENR_SPI3EN RCC_APB1ENR_SPI3EN_Msk /*!< SPI 3 clock enable */
+#define RCC_APB1ENR_UART4EN_Pos (19U)
+#define RCC_APB1ENR_UART4EN_Msk (0x1U << RCC_APB1ENR_UART4EN_Pos) /*!< 0x00080000 */
+#define RCC_APB1ENR_UART4EN RCC_APB1ENR_UART4EN_Msk /*!< UART 4 clock enable */
+#define RCC_APB1ENR_UART5EN_Pos (20U)
+#define RCC_APB1ENR_UART5EN_Msk (0x1U << RCC_APB1ENR_UART5EN_Pos) /*!< 0x00100000 */
+#define RCC_APB1ENR_UART5EN RCC_APB1ENR_UART5EN_Msk /*!< UART 5 clock enable */
+
+
+
+
+#define RCC_APB1ENR_DACEN_Pos (29U)
+#define RCC_APB1ENR_DACEN_Msk (0x1U << RCC_APB1ENR_DACEN_Pos) /*!< 0x20000000 */
+#define RCC_APB1ENR_DACEN RCC_APB1ENR_DACEN_Msk /*!< DAC interface clock enable */
+
+/******************* Bit definition for RCC_BDCR register *******************/
+#define RCC_BDCR_LSEON_Pos (0U)
+#define RCC_BDCR_LSEON_Msk (0x1U << RCC_BDCR_LSEON_Pos) /*!< 0x00000001 */
+#define RCC_BDCR_LSEON RCC_BDCR_LSEON_Msk /*!< External Low Speed oscillator enable */
+#define RCC_BDCR_LSERDY_Pos (1U)
+#define RCC_BDCR_LSERDY_Msk (0x1U << RCC_BDCR_LSERDY_Pos) /*!< 0x00000002 */
+#define RCC_BDCR_LSERDY RCC_BDCR_LSERDY_Msk /*!< External Low Speed oscillator Ready */
+#define RCC_BDCR_LSEBYP_Pos (2U)
+#define RCC_BDCR_LSEBYP_Msk (0x1U << RCC_BDCR_LSEBYP_Pos) /*!< 0x00000004 */
+#define RCC_BDCR_LSEBYP RCC_BDCR_LSEBYP_Msk /*!< External Low Speed oscillator Bypass */
+
+#define RCC_BDCR_RTCSEL_Pos (8U)
+#define RCC_BDCR_RTCSEL_Msk (0x3U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000300 */
+#define RCC_BDCR_RTCSEL RCC_BDCR_RTCSEL_Msk /*!< RTCSEL[1:0] bits (RTC clock source selection) */
+#define RCC_BDCR_RTCSEL_0 (0x1U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000100 */
+#define RCC_BDCR_RTCSEL_1 (0x2U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000200 */
+
+/*!< RTC congiguration */
+#define RCC_BDCR_RTCSEL_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */
+#define RCC_BDCR_RTCSEL_LSE ((uint32_t)0x00000100) /*!< LSE oscillator clock used as RTC clock */
+#define RCC_BDCR_RTCSEL_LSI ((uint32_t)0x00000200) /*!< LSI oscillator clock used as RTC clock */
+#define RCC_BDCR_RTCSEL_HSE ((uint32_t)0x00000300) /*!< HSE oscillator clock divided by 128 used as RTC clock */
+
+#define RCC_BDCR_RTCEN_Pos (15U)
+#define RCC_BDCR_RTCEN_Msk (0x1U << RCC_BDCR_RTCEN_Pos) /*!< 0x00008000 */
+#define RCC_BDCR_RTCEN RCC_BDCR_RTCEN_Msk /*!< RTC clock enable */
+#define RCC_BDCR_BDRST_Pos (16U)
+#define RCC_BDCR_BDRST_Msk (0x1U << RCC_BDCR_BDRST_Pos) /*!< 0x00010000 */
+#define RCC_BDCR_BDRST RCC_BDCR_BDRST_Msk /*!< Backup domain software reset */
+
+/******************* Bit definition for RCC_CSR register ********************/
+#define RCC_CSR_LSION_Pos (0U)
+#define RCC_CSR_LSION_Msk (0x1U << RCC_CSR_LSION_Pos) /*!< 0x00000001 */
+#define RCC_CSR_LSION RCC_CSR_LSION_Msk /*!< Internal Low Speed oscillator enable */
+#define RCC_CSR_LSIRDY_Pos (1U)
+#define RCC_CSR_LSIRDY_Msk (0x1U << RCC_CSR_LSIRDY_Pos) /*!< 0x00000002 */
+#define RCC_CSR_LSIRDY RCC_CSR_LSIRDY_Msk /*!< Internal Low Speed oscillator Ready */
+#define RCC_CSR_RMVF_Pos (24U)
+#define RCC_CSR_RMVF_Msk (0x1U << RCC_CSR_RMVF_Pos) /*!< 0x01000000 */
+#define RCC_CSR_RMVF RCC_CSR_RMVF_Msk /*!< Remove reset flag */
+#define RCC_CSR_PINRSTF_Pos (26U)
+#define RCC_CSR_PINRSTF_Msk (0x1U << RCC_CSR_PINRSTF_Pos) /*!< 0x04000000 */
+#define RCC_CSR_PINRSTF RCC_CSR_PINRSTF_Msk /*!< PIN reset flag */
+#define RCC_CSR_PORRSTF_Pos (27U)
+#define RCC_CSR_PORRSTF_Msk (0x1U << RCC_CSR_PORRSTF_Pos) /*!< 0x08000000 */
+#define RCC_CSR_PORRSTF RCC_CSR_PORRSTF_Msk /*!< POR/PDR reset flag */
+#define RCC_CSR_SFTRSTF_Pos (28U)
+#define RCC_CSR_SFTRSTF_Msk (0x1U << RCC_CSR_SFTRSTF_Pos) /*!< 0x10000000 */
+#define RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF_Msk /*!< Software Reset flag */
+#define RCC_CSR_IWDGRSTF_Pos (29U)
+#define RCC_CSR_IWDGRSTF_Msk (0x1U << RCC_CSR_IWDGRSTF_Pos) /*!< 0x20000000 */
+#define RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF_Msk /*!< Independent Watchdog reset flag */
+#define RCC_CSR_WWDGRSTF_Pos (30U)
+#define RCC_CSR_WWDGRSTF_Msk (0x1U << RCC_CSR_WWDGRSTF_Pos) /*!< 0x40000000 */
+#define RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF_Msk /*!< Window watchdog reset flag */
+#define RCC_CSR_LPWRRSTF_Pos (31U)
+#define RCC_CSR_LPWRRSTF_Msk (0x1U << RCC_CSR_LPWRRSTF_Pos) /*!< 0x80000000 */
+#define RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF_Msk /*!< Low-Power reset flag */
+
+
+
+/******************************************************************************/
+/* */
+/* General Purpose and Alternate Function I/O */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for GPIO_CRL register *******************/
+#define GPIO_CRL_MODE_Pos (0U)
+#define GPIO_CRL_MODE_Msk (0x33333333U << GPIO_CRL_MODE_Pos) /*!< 0x33333333 */
+#define GPIO_CRL_MODE GPIO_CRL_MODE_Msk /*!< Port x mode bits */
+
+#define GPIO_CRL_MODE0_Pos (0U)
+#define GPIO_CRL_MODE0_Msk (0x3U << GPIO_CRL_MODE0_Pos) /*!< 0x00000003 */
+#define GPIO_CRL_MODE0 GPIO_CRL_MODE0_Msk /*!< MODE0[1:0] bits (Port x mode bits, pin 0) */
+#define GPIO_CRL_MODE0_0 (0x1U << GPIO_CRL_MODE0_Pos) /*!< 0x00000001 */
+#define GPIO_CRL_MODE0_1 (0x2U << GPIO_CRL_MODE0_Pos) /*!< 0x00000002 */
+
+#define GPIO_CRL_MODE1_Pos (4U)
+#define GPIO_CRL_MODE1_Msk (0x3U << GPIO_CRL_MODE1_Pos) /*!< 0x00000030 */
+#define GPIO_CRL_MODE1 GPIO_CRL_MODE1_Msk /*!< MODE1[1:0] bits (Port x mode bits, pin 1) */
+#define GPIO_CRL_MODE1_0 (0x1U << GPIO_CRL_MODE1_Pos) /*!< 0x00000010 */
+#define GPIO_CRL_MODE1_1 (0x2U << GPIO_CRL_MODE1_Pos) /*!< 0x00000020 */
+
+#define GPIO_CRL_MODE2_Pos (8U)
+#define GPIO_CRL_MODE2_Msk (0x3U << GPIO_CRL_MODE2_Pos) /*!< 0x00000300 */
+#define GPIO_CRL_MODE2 GPIO_CRL_MODE2_Msk /*!< MODE2[1:0] bits (Port x mode bits, pin 2) */
+#define GPIO_CRL_MODE2_0 (0x1U << GPIO_CRL_MODE2_Pos) /*!< 0x00000100 */
+#define GPIO_CRL_MODE2_1 (0x2U << GPIO_CRL_MODE2_Pos) /*!< 0x00000200 */
+
+#define GPIO_CRL_MODE3_Pos (12U)
+#define GPIO_CRL_MODE3_Msk (0x3U << GPIO_CRL_MODE3_Pos) /*!< 0x00003000 */
+#define GPIO_CRL_MODE3 GPIO_CRL_MODE3_Msk /*!< MODE3[1:0] bits (Port x mode bits, pin 3) */
+#define GPIO_CRL_MODE3_0 (0x1U << GPIO_CRL_MODE3_Pos) /*!< 0x00001000 */
+#define GPIO_CRL_MODE3_1 (0x2U << GPIO_CRL_MODE3_Pos) /*!< 0x00002000 */
+
+#define GPIO_CRL_MODE4_Pos (16U)
+#define GPIO_CRL_MODE4_Msk (0x3U << GPIO_CRL_MODE4_Pos) /*!< 0x00030000 */
+#define GPIO_CRL_MODE4 GPIO_CRL_MODE4_Msk /*!< MODE4[1:0] bits (Port x mode bits, pin 4) */
+#define GPIO_CRL_MODE4_0 (0x1U << GPIO_CRL_MODE4_Pos) /*!< 0x00010000 */
+#define GPIO_CRL_MODE4_1 (0x2U << GPIO_CRL_MODE4_Pos) /*!< 0x00020000 */
+
+#define GPIO_CRL_MODE5_Pos (20U)
+#define GPIO_CRL_MODE5_Msk (0x3U << GPIO_CRL_MODE5_Pos) /*!< 0x00300000 */
+#define GPIO_CRL_MODE5 GPIO_CRL_MODE5_Msk /*!< MODE5[1:0] bits (Port x mode bits, pin 5) */
+#define GPIO_CRL_MODE5_0 (0x1U << GPIO_CRL_MODE5_Pos) /*!< 0x00100000 */
+#define GPIO_CRL_MODE5_1 (0x2U << GPIO_CRL_MODE5_Pos) /*!< 0x00200000 */
+
+#define GPIO_CRL_MODE6_Pos (24U)
+#define GPIO_CRL_MODE6_Msk (0x3U << GPIO_CRL_MODE6_Pos) /*!< 0x03000000 */
+#define GPIO_CRL_MODE6 GPIO_CRL_MODE6_Msk /*!< MODE6[1:0] bits (Port x mode bits, pin 6) */
+#define GPIO_CRL_MODE6_0 (0x1U << GPIO_CRL_MODE6_Pos) /*!< 0x01000000 */
+#define GPIO_CRL_MODE6_1 (0x2U << GPIO_CRL_MODE6_Pos) /*!< 0x02000000 */
+
+#define GPIO_CRL_MODE7_Pos (28U)
+#define GPIO_CRL_MODE7_Msk (0x3U << GPIO_CRL_MODE7_Pos) /*!< 0x30000000 */
+#define GPIO_CRL_MODE7 GPIO_CRL_MODE7_Msk /*!< MODE7[1:0] bits (Port x mode bits, pin 7) */
+#define GPIO_CRL_MODE7_0 (0x1U << GPIO_CRL_MODE7_Pos) /*!< 0x10000000 */
+#define GPIO_CRL_MODE7_1 (0x2U << GPIO_CRL_MODE7_Pos) /*!< 0x20000000 */
+
+#define GPIO_CRL_CNF_Pos (2U)
+#define GPIO_CRL_CNF_Msk (0x33333333U << GPIO_CRL_CNF_Pos) /*!< 0xCCCCCCCC */
+#define GPIO_CRL_CNF GPIO_CRL_CNF_Msk /*!< Port x configuration bits */
+
+#define GPIO_CRL_CNF0_Pos (2U)
+#define GPIO_CRL_CNF0_Msk (0x3U << GPIO_CRL_CNF0_Pos) /*!< 0x0000000C */
+#define GPIO_CRL_CNF0 GPIO_CRL_CNF0_Msk /*!< CNF0[1:0] bits (Port x configuration bits, pin 0) */
+#define GPIO_CRL_CNF0_0 (0x1U << GPIO_CRL_CNF0_Pos) /*!< 0x00000004 */
+#define GPIO_CRL_CNF0_1 (0x2U << GPIO_CRL_CNF0_Pos) /*!< 0x00000008 */
+
+#define GPIO_CRL_CNF1_Pos (6U)
+#define GPIO_CRL_CNF1_Msk (0x3U << GPIO_CRL_CNF1_Pos) /*!< 0x000000C0 */
+#define GPIO_CRL_CNF1 GPIO_CRL_CNF1_Msk /*!< CNF1[1:0] bits (Port x configuration bits, pin 1) */
+#define GPIO_CRL_CNF1_0 (0x1U << GPIO_CRL_CNF1_Pos) /*!< 0x00000040 */
+#define GPIO_CRL_CNF1_1 (0x2U << GPIO_CRL_CNF1_Pos) /*!< 0x00000080 */
+
+#define GPIO_CRL_CNF2_Pos (10U)
+#define GPIO_CRL_CNF2_Msk (0x3U << GPIO_CRL_CNF2_Pos) /*!< 0x00000C00 */
+#define GPIO_CRL_CNF2 GPIO_CRL_CNF2_Msk /*!< CNF2[1:0] bits (Port x configuration bits, pin 2) */
+#define GPIO_CRL_CNF2_0 (0x1U << GPIO_CRL_CNF2_Pos) /*!< 0x00000400 */
+#define GPIO_CRL_CNF2_1 (0x2U << GPIO_CRL_CNF2_Pos) /*!< 0x00000800 */
+
+#define GPIO_CRL_CNF3_Pos (14U)
+#define GPIO_CRL_CNF3_Msk (0x3U << GPIO_CRL_CNF3_Pos) /*!< 0x0000C000 */
+#define GPIO_CRL_CNF3 GPIO_CRL_CNF3_Msk /*!< CNF3[1:0] bits (Port x configuration bits, pin 3) */
+#define GPIO_CRL_CNF3_0 (0x1U << GPIO_CRL_CNF3_Pos) /*!< 0x00004000 */
+#define GPIO_CRL_CNF3_1 (0x2U << GPIO_CRL_CNF3_Pos) /*!< 0x00008000 */
+
+#define GPIO_CRL_CNF4_Pos (18U)
+#define GPIO_CRL_CNF4_Msk (0x3U << GPIO_CRL_CNF4_Pos) /*!< 0x000C0000 */
+#define GPIO_CRL_CNF4 GPIO_CRL_CNF4_Msk /*!< CNF4[1:0] bits (Port x configuration bits, pin 4) */
+#define GPIO_CRL_CNF4_0 (0x1U << GPIO_CRL_CNF4_Pos) /*!< 0x00040000 */
+#define GPIO_CRL_CNF4_1 (0x2U << GPIO_CRL_CNF4_Pos) /*!< 0x00080000 */
+
+#define GPIO_CRL_CNF5_Pos (22U)
+#define GPIO_CRL_CNF5_Msk (0x3U << GPIO_CRL_CNF5_Pos) /*!< 0x00C00000 */
+#define GPIO_CRL_CNF5 GPIO_CRL_CNF5_Msk /*!< CNF5[1:0] bits (Port x configuration bits, pin 5) */
+#define GPIO_CRL_CNF5_0 (0x1U << GPIO_CRL_CNF5_Pos) /*!< 0x00400000 */
+#define GPIO_CRL_CNF5_1 (0x2U << GPIO_CRL_CNF5_Pos) /*!< 0x00800000 */
+
+#define GPIO_CRL_CNF6_Pos (26U)
+#define GPIO_CRL_CNF6_Msk (0x3U << GPIO_CRL_CNF6_Pos) /*!< 0x0C000000 */
+#define GPIO_CRL_CNF6 GPIO_CRL_CNF6_Msk /*!< CNF6[1:0] bits (Port x configuration bits, pin 6) */
+#define GPIO_CRL_CNF6_0 (0x1U << GPIO_CRL_CNF6_Pos) /*!< 0x04000000 */
+#define GPIO_CRL_CNF6_1 (0x2U << GPIO_CRL_CNF6_Pos) /*!< 0x08000000 */
+
+#define GPIO_CRL_CNF7_Pos (30U)
+#define GPIO_CRL_CNF7_Msk (0x3U << GPIO_CRL_CNF7_Pos) /*!< 0xC0000000 */
+#define GPIO_CRL_CNF7 GPIO_CRL_CNF7_Msk /*!< CNF7[1:0] bits (Port x configuration bits, pin 7) */
+#define GPIO_CRL_CNF7_0 (0x1U << GPIO_CRL_CNF7_Pos) /*!< 0x40000000 */
+#define GPIO_CRL_CNF7_1 (0x2U << GPIO_CRL_CNF7_Pos) /*!< 0x80000000 */
+
+/******************* Bit definition for GPIO_CRH register *******************/
+#define GPIO_CRH_MODE_Pos (0U)
+#define GPIO_CRH_MODE_Msk (0x33333333U << GPIO_CRH_MODE_Pos) /*!< 0x33333333 */
+#define GPIO_CRH_MODE GPIO_CRH_MODE_Msk /*!< Port x mode bits */
+
+#define GPIO_CRH_MODE8_Pos (0U)
+#define GPIO_CRH_MODE8_Msk (0x3U << GPIO_CRH_MODE8_Pos) /*!< 0x00000003 */
+#define GPIO_CRH_MODE8 GPIO_CRH_MODE8_Msk /*!< MODE8[1:0] bits (Port x mode bits, pin 8) */
+#define GPIO_CRH_MODE8_0 (0x1U << GPIO_CRH_MODE8_Pos) /*!< 0x00000001 */
+#define GPIO_CRH_MODE8_1 (0x2U << GPIO_CRH_MODE8_Pos) /*!< 0x00000002 */
+
+#define GPIO_CRH_MODE9_Pos (4U)
+#define GPIO_CRH_MODE9_Msk (0x3U << GPIO_CRH_MODE9_Pos) /*!< 0x00000030 */
+#define GPIO_CRH_MODE9 GPIO_CRH_MODE9_Msk /*!< MODE9[1:0] bits (Port x mode bits, pin 9) */
+#define GPIO_CRH_MODE9_0 (0x1U << GPIO_CRH_MODE9_Pos) /*!< 0x00000010 */
+#define GPIO_CRH_MODE9_1 (0x2U << GPIO_CRH_MODE9_Pos) /*!< 0x00000020 */
+
+#define GPIO_CRH_MODE10_Pos (8U)
+#define GPIO_CRH_MODE10_Msk (0x3U << GPIO_CRH_MODE10_Pos) /*!< 0x00000300 */
+#define GPIO_CRH_MODE10 GPIO_CRH_MODE10_Msk /*!< MODE10[1:0] bits (Port x mode bits, pin 10) */
+#define GPIO_CRH_MODE10_0 (0x1U << GPIO_CRH_MODE10_Pos) /*!< 0x00000100 */
+#define GPIO_CRH_MODE10_1 (0x2U << GPIO_CRH_MODE10_Pos) /*!< 0x00000200 */
+
+#define GPIO_CRH_MODE11_Pos (12U)
+#define GPIO_CRH_MODE11_Msk (0x3U << GPIO_CRH_MODE11_Pos) /*!< 0x00003000 */
+#define GPIO_CRH_MODE11 GPIO_CRH_MODE11_Msk /*!< MODE11[1:0] bits (Port x mode bits, pin 11) */
+#define GPIO_CRH_MODE11_0 (0x1U << GPIO_CRH_MODE11_Pos) /*!< 0x00001000 */
+#define GPIO_CRH_MODE11_1 (0x2U << GPIO_CRH_MODE11_Pos) /*!< 0x00002000 */
+
+#define GPIO_CRH_MODE12_Pos (16U)
+#define GPIO_CRH_MODE12_Msk (0x3U << GPIO_CRH_MODE12_Pos) /*!< 0x00030000 */
+#define GPIO_CRH_MODE12 GPIO_CRH_MODE12_Msk /*!< MODE12[1:0] bits (Port x mode bits, pin 12) */
+#define GPIO_CRH_MODE12_0 (0x1U << GPIO_CRH_MODE12_Pos) /*!< 0x00010000 */
+#define GPIO_CRH_MODE12_1 (0x2U << GPIO_CRH_MODE12_Pos) /*!< 0x00020000 */
+
+#define GPIO_CRH_MODE13_Pos (20U)
+#define GPIO_CRH_MODE13_Msk (0x3U << GPIO_CRH_MODE13_Pos) /*!< 0x00300000 */
+#define GPIO_CRH_MODE13 GPIO_CRH_MODE13_Msk /*!< MODE13[1:0] bits (Port x mode bits, pin 13) */
+#define GPIO_CRH_MODE13_0 (0x1U << GPIO_CRH_MODE13_Pos) /*!< 0x00100000 */
+#define GPIO_CRH_MODE13_1 (0x2U << GPIO_CRH_MODE13_Pos) /*!< 0x00200000 */
+
+#define GPIO_CRH_MODE14_Pos (24U)
+#define GPIO_CRH_MODE14_Msk (0x3U << GPIO_CRH_MODE14_Pos) /*!< 0x03000000 */
+#define GPIO_CRH_MODE14 GPIO_CRH_MODE14_Msk /*!< MODE14[1:0] bits (Port x mode bits, pin 14) */
+#define GPIO_CRH_MODE14_0 (0x1U << GPIO_CRH_MODE14_Pos) /*!< 0x01000000 */
+#define GPIO_CRH_MODE14_1 (0x2U << GPIO_CRH_MODE14_Pos) /*!< 0x02000000 */
+
+#define GPIO_CRH_MODE15_Pos (28U)
+#define GPIO_CRH_MODE15_Msk (0x3U << GPIO_CRH_MODE15_Pos) /*!< 0x30000000 */
+#define GPIO_CRH_MODE15 GPIO_CRH_MODE15_Msk /*!< MODE15[1:0] bits (Port x mode bits, pin 15) */
+#define GPIO_CRH_MODE15_0 (0x1U << GPIO_CRH_MODE15_Pos) /*!< 0x10000000 */
+#define GPIO_CRH_MODE15_1 (0x2U << GPIO_CRH_MODE15_Pos) /*!< 0x20000000 */
+
+#define GPIO_CRH_CNF_Pos (2U)
+#define GPIO_CRH_CNF_Msk (0x33333333U << GPIO_CRH_CNF_Pos) /*!< 0xCCCCCCCC */
+#define GPIO_CRH_CNF GPIO_CRH_CNF_Msk /*!< Port x configuration bits */
+
+#define GPIO_CRH_CNF8_Pos (2U)
+#define GPIO_CRH_CNF8_Msk (0x3U << GPIO_CRH_CNF8_Pos) /*!< 0x0000000C */
+#define GPIO_CRH_CNF8 GPIO_CRH_CNF8_Msk /*!< CNF8[1:0] bits (Port x configuration bits, pin 8) */
+#define GPIO_CRH_CNF8_0 (0x1U << GPIO_CRH_CNF8_Pos) /*!< 0x00000004 */
+#define GPIO_CRH_CNF8_1 (0x2U << GPIO_CRH_CNF8_Pos) /*!< 0x00000008 */
+
+#define GPIO_CRH_CNF9_Pos (6U)
+#define GPIO_CRH_CNF9_Msk (0x3U << GPIO_CRH_CNF9_Pos) /*!< 0x000000C0 */
+#define GPIO_CRH_CNF9 GPIO_CRH_CNF9_Msk /*!< CNF9[1:0] bits (Port x configuration bits, pin 9) */
+#define GPIO_CRH_CNF9_0 (0x1U << GPIO_CRH_CNF9_Pos) /*!< 0x00000040 */
+#define GPIO_CRH_CNF9_1 (0x2U << GPIO_CRH_CNF9_Pos) /*!< 0x00000080 */
+
+#define GPIO_CRH_CNF10_Pos (10U)
+#define GPIO_CRH_CNF10_Msk (0x3U << GPIO_CRH_CNF10_Pos) /*!< 0x00000C00 */
+#define GPIO_CRH_CNF10 GPIO_CRH_CNF10_Msk /*!< CNF10[1:0] bits (Port x configuration bits, pin 10) */
+#define GPIO_CRH_CNF10_0 (0x1U << GPIO_CRH_CNF10_Pos) /*!< 0x00000400 */
+#define GPIO_CRH_CNF10_1 (0x2U << GPIO_CRH_CNF10_Pos) /*!< 0x00000800 */
+
+#define GPIO_CRH_CNF11_Pos (14U)
+#define GPIO_CRH_CNF11_Msk (0x3U << GPIO_CRH_CNF11_Pos) /*!< 0x0000C000 */
+#define GPIO_CRH_CNF11 GPIO_CRH_CNF11_Msk /*!< CNF11[1:0] bits (Port x configuration bits, pin 11) */
+#define GPIO_CRH_CNF11_0 (0x1U << GPIO_CRH_CNF11_Pos) /*!< 0x00004000 */
+#define GPIO_CRH_CNF11_1 (0x2U << GPIO_CRH_CNF11_Pos) /*!< 0x00008000 */
+
+#define GPIO_CRH_CNF12_Pos (18U)
+#define GPIO_CRH_CNF12_Msk (0x3U << GPIO_CRH_CNF12_Pos) /*!< 0x000C0000 */
+#define GPIO_CRH_CNF12 GPIO_CRH_CNF12_Msk /*!< CNF12[1:0] bits (Port x configuration bits, pin 12) */
+#define GPIO_CRH_CNF12_0 (0x1U << GPIO_CRH_CNF12_Pos) /*!< 0x00040000 */
+#define GPIO_CRH_CNF12_1 (0x2U << GPIO_CRH_CNF12_Pos) /*!< 0x00080000 */
+
+#define GPIO_CRH_CNF13_Pos (22U)
+#define GPIO_CRH_CNF13_Msk (0x3U << GPIO_CRH_CNF13_Pos) /*!< 0x00C00000 */
+#define GPIO_CRH_CNF13 GPIO_CRH_CNF13_Msk /*!< CNF13[1:0] bits (Port x configuration bits, pin 13) */
+#define GPIO_CRH_CNF13_0 (0x1U << GPIO_CRH_CNF13_Pos) /*!< 0x00400000 */
+#define GPIO_CRH_CNF13_1 (0x2U << GPIO_CRH_CNF13_Pos) /*!< 0x00800000 */
+
+#define GPIO_CRH_CNF14_Pos (26U)
+#define GPIO_CRH_CNF14_Msk (0x3U << GPIO_CRH_CNF14_Pos) /*!< 0x0C000000 */
+#define GPIO_CRH_CNF14 GPIO_CRH_CNF14_Msk /*!< CNF14[1:0] bits (Port x configuration bits, pin 14) */
+#define GPIO_CRH_CNF14_0 (0x1U << GPIO_CRH_CNF14_Pos) /*!< 0x04000000 */
+#define GPIO_CRH_CNF14_1 (0x2U << GPIO_CRH_CNF14_Pos) /*!< 0x08000000 */
+
+#define GPIO_CRH_CNF15_Pos (30U)
+#define GPIO_CRH_CNF15_Msk (0x3U << GPIO_CRH_CNF15_Pos) /*!< 0xC0000000 */
+#define GPIO_CRH_CNF15 GPIO_CRH_CNF15_Msk /*!< CNF15[1:0] bits (Port x configuration bits, pin 15) */
+#define GPIO_CRH_CNF15_0 (0x1U << GPIO_CRH_CNF15_Pos) /*!< 0x40000000 */
+#define GPIO_CRH_CNF15_1 (0x2U << GPIO_CRH_CNF15_Pos) /*!< 0x80000000 */
+
+/*!<****************** Bit definition for GPIO_IDR register *******************/
+#define GPIO_IDR_IDR0_Pos (0U)
+#define GPIO_IDR_IDR0_Msk (0x1U << GPIO_IDR_IDR0_Pos) /*!< 0x00000001 */
+#define GPIO_IDR_IDR0 GPIO_IDR_IDR0_Msk /*!< Port input data, bit 0 */
+#define GPIO_IDR_IDR1_Pos (1U)
+#define GPIO_IDR_IDR1_Msk (0x1U << GPIO_IDR_IDR1_Pos) /*!< 0x00000002 */
+#define GPIO_IDR_IDR1 GPIO_IDR_IDR1_Msk /*!< Port input data, bit 1 */
+#define GPIO_IDR_IDR2_Pos (2U)
+#define GPIO_IDR_IDR2_Msk (0x1U << GPIO_IDR_IDR2_Pos) /*!< 0x00000004 */
+#define GPIO_IDR_IDR2 GPIO_IDR_IDR2_Msk /*!< Port input data, bit 2 */
+#define GPIO_IDR_IDR3_Pos (3U)
+#define GPIO_IDR_IDR3_Msk (0x1U << GPIO_IDR_IDR3_Pos) /*!< 0x00000008 */
+#define GPIO_IDR_IDR3 GPIO_IDR_IDR3_Msk /*!< Port input data, bit 3 */
+#define GPIO_IDR_IDR4_Pos (4U)
+#define GPIO_IDR_IDR4_Msk (0x1U << GPIO_IDR_IDR4_Pos) /*!< 0x00000010 */
+#define GPIO_IDR_IDR4 GPIO_IDR_IDR4_Msk /*!< Port input data, bit 4 */
+#define GPIO_IDR_IDR5_Pos (5U)
+#define GPIO_IDR_IDR5_Msk (0x1U << GPIO_IDR_IDR5_Pos) /*!< 0x00000020 */
+#define GPIO_IDR_IDR5 GPIO_IDR_IDR5_Msk /*!< Port input data, bit 5 */
+#define GPIO_IDR_IDR6_Pos (6U)
+#define GPIO_IDR_IDR6_Msk (0x1U << GPIO_IDR_IDR6_Pos) /*!< 0x00000040 */
+#define GPIO_IDR_IDR6 GPIO_IDR_IDR6_Msk /*!< Port input data, bit 6 */
+#define GPIO_IDR_IDR7_Pos (7U)
+#define GPIO_IDR_IDR7_Msk (0x1U << GPIO_IDR_IDR7_Pos) /*!< 0x00000080 */
+#define GPIO_IDR_IDR7 GPIO_IDR_IDR7_Msk /*!< Port input data, bit 7 */
+#define GPIO_IDR_IDR8_Pos (8U)
+#define GPIO_IDR_IDR8_Msk (0x1U << GPIO_IDR_IDR8_Pos) /*!< 0x00000100 */
+#define GPIO_IDR_IDR8 GPIO_IDR_IDR8_Msk /*!< Port input data, bit 8 */
+#define GPIO_IDR_IDR9_Pos (9U)
+#define GPIO_IDR_IDR9_Msk (0x1U << GPIO_IDR_IDR9_Pos) /*!< 0x00000200 */
+#define GPIO_IDR_IDR9 GPIO_IDR_IDR9_Msk /*!< Port input data, bit 9 */
+#define GPIO_IDR_IDR10_Pos (10U)
+#define GPIO_IDR_IDR10_Msk (0x1U << GPIO_IDR_IDR10_Pos) /*!< 0x00000400 */
+#define GPIO_IDR_IDR10 GPIO_IDR_IDR10_Msk /*!< Port input data, bit 10 */
+#define GPIO_IDR_IDR11_Pos (11U)
+#define GPIO_IDR_IDR11_Msk (0x1U << GPIO_IDR_IDR11_Pos) /*!< 0x00000800 */
+#define GPIO_IDR_IDR11 GPIO_IDR_IDR11_Msk /*!< Port input data, bit 11 */
+#define GPIO_IDR_IDR12_Pos (12U)
+#define GPIO_IDR_IDR12_Msk (0x1U << GPIO_IDR_IDR12_Pos) /*!< 0x00001000 */
+#define GPIO_IDR_IDR12 GPIO_IDR_IDR12_Msk /*!< Port input data, bit 12 */
+#define GPIO_IDR_IDR13_Pos (13U)
+#define GPIO_IDR_IDR13_Msk (0x1U << GPIO_IDR_IDR13_Pos) /*!< 0x00002000 */
+#define GPIO_IDR_IDR13 GPIO_IDR_IDR13_Msk /*!< Port input data, bit 13 */
+#define GPIO_IDR_IDR14_Pos (14U)
+#define GPIO_IDR_IDR14_Msk (0x1U << GPIO_IDR_IDR14_Pos) /*!< 0x00004000 */
+#define GPIO_IDR_IDR14 GPIO_IDR_IDR14_Msk /*!< Port input data, bit 14 */
+#define GPIO_IDR_IDR15_Pos (15U)
+#define GPIO_IDR_IDR15_Msk (0x1U << GPIO_IDR_IDR15_Pos) /*!< 0x00008000 */
+#define GPIO_IDR_IDR15 GPIO_IDR_IDR15_Msk /*!< Port input data, bit 15 */
+
+/******************* Bit definition for GPIO_ODR register *******************/
+#define GPIO_ODR_ODR0_Pos (0U)
+#define GPIO_ODR_ODR0_Msk (0x1U << GPIO_ODR_ODR0_Pos) /*!< 0x00000001 */
+#define GPIO_ODR_ODR0 GPIO_ODR_ODR0_Msk /*!< Port output data, bit 0 */
+#define GPIO_ODR_ODR1_Pos (1U)
+#define GPIO_ODR_ODR1_Msk (0x1U << GPIO_ODR_ODR1_Pos) /*!< 0x00000002 */
+#define GPIO_ODR_ODR1 GPIO_ODR_ODR1_Msk /*!< Port output data, bit 1 */
+#define GPIO_ODR_ODR2_Pos (2U)
+#define GPIO_ODR_ODR2_Msk (0x1U << GPIO_ODR_ODR2_Pos) /*!< 0x00000004 */
+#define GPIO_ODR_ODR2 GPIO_ODR_ODR2_Msk /*!< Port output data, bit 2 */
+#define GPIO_ODR_ODR3_Pos (3U)
+#define GPIO_ODR_ODR3_Msk (0x1U << GPIO_ODR_ODR3_Pos) /*!< 0x00000008 */
+#define GPIO_ODR_ODR3 GPIO_ODR_ODR3_Msk /*!< Port output data, bit 3 */
+#define GPIO_ODR_ODR4_Pos (4U)
+#define GPIO_ODR_ODR4_Msk (0x1U << GPIO_ODR_ODR4_Pos) /*!< 0x00000010 */
+#define GPIO_ODR_ODR4 GPIO_ODR_ODR4_Msk /*!< Port output data, bit 4 */
+#define GPIO_ODR_ODR5_Pos (5U)
+#define GPIO_ODR_ODR5_Msk (0x1U << GPIO_ODR_ODR5_Pos) /*!< 0x00000020 */
+#define GPIO_ODR_ODR5 GPIO_ODR_ODR5_Msk /*!< Port output data, bit 5 */
+#define GPIO_ODR_ODR6_Pos (6U)
+#define GPIO_ODR_ODR6_Msk (0x1U << GPIO_ODR_ODR6_Pos) /*!< 0x00000040 */
+#define GPIO_ODR_ODR6 GPIO_ODR_ODR6_Msk /*!< Port output data, bit 6 */
+#define GPIO_ODR_ODR7_Pos (7U)
+#define GPIO_ODR_ODR7_Msk (0x1U << GPIO_ODR_ODR7_Pos) /*!< 0x00000080 */
+#define GPIO_ODR_ODR7 GPIO_ODR_ODR7_Msk /*!< Port output data, bit 7 */
+#define GPIO_ODR_ODR8_Pos (8U)
+#define GPIO_ODR_ODR8_Msk (0x1U << GPIO_ODR_ODR8_Pos) /*!< 0x00000100 */
+#define GPIO_ODR_ODR8 GPIO_ODR_ODR8_Msk /*!< Port output data, bit 8 */
+#define GPIO_ODR_ODR9_Pos (9U)
+#define GPIO_ODR_ODR9_Msk (0x1U << GPIO_ODR_ODR9_Pos) /*!< 0x00000200 */
+#define GPIO_ODR_ODR9 GPIO_ODR_ODR9_Msk /*!< Port output data, bit 9 */
+#define GPIO_ODR_ODR10_Pos (10U)
+#define GPIO_ODR_ODR10_Msk (0x1U << GPIO_ODR_ODR10_Pos) /*!< 0x00000400 */
+#define GPIO_ODR_ODR10 GPIO_ODR_ODR10_Msk /*!< Port output data, bit 10 */
+#define GPIO_ODR_ODR11_Pos (11U)
+#define GPIO_ODR_ODR11_Msk (0x1U << GPIO_ODR_ODR11_Pos) /*!< 0x00000800 */
+#define GPIO_ODR_ODR11 GPIO_ODR_ODR11_Msk /*!< Port output data, bit 11 */
+#define GPIO_ODR_ODR12_Pos (12U)
+#define GPIO_ODR_ODR12_Msk (0x1U << GPIO_ODR_ODR12_Pos) /*!< 0x00001000 */
+#define GPIO_ODR_ODR12 GPIO_ODR_ODR12_Msk /*!< Port output data, bit 12 */
+#define GPIO_ODR_ODR13_Pos (13U)
+#define GPIO_ODR_ODR13_Msk (0x1U << GPIO_ODR_ODR13_Pos) /*!< 0x00002000 */
+#define GPIO_ODR_ODR13 GPIO_ODR_ODR13_Msk /*!< Port output data, bit 13 */
+#define GPIO_ODR_ODR14_Pos (14U)
+#define GPIO_ODR_ODR14_Msk (0x1U << GPIO_ODR_ODR14_Pos) /*!< 0x00004000 */
+#define GPIO_ODR_ODR14 GPIO_ODR_ODR14_Msk /*!< Port output data, bit 14 */
+#define GPIO_ODR_ODR15_Pos (15U)
+#define GPIO_ODR_ODR15_Msk (0x1U << GPIO_ODR_ODR15_Pos) /*!< 0x00008000 */
+#define GPIO_ODR_ODR15 GPIO_ODR_ODR15_Msk /*!< Port output data, bit 15 */
+
+/****************** Bit definition for GPIO_BSRR register *******************/
+#define GPIO_BSRR_BS0_Pos (0U)
+#define GPIO_BSRR_BS0_Msk (0x1U << GPIO_BSRR_BS0_Pos) /*!< 0x00000001 */
+#define GPIO_BSRR_BS0 GPIO_BSRR_BS0_Msk /*!< Port x Set bit 0 */
+#define GPIO_BSRR_BS1_Pos (1U)
+#define GPIO_BSRR_BS1_Msk (0x1U << GPIO_BSRR_BS1_Pos) /*!< 0x00000002 */
+#define GPIO_BSRR_BS1 GPIO_BSRR_BS1_Msk /*!< Port x Set bit 1 */
+#define GPIO_BSRR_BS2_Pos (2U)
+#define GPIO_BSRR_BS2_Msk (0x1U << GPIO_BSRR_BS2_Pos) /*!< 0x00000004 */
+#define GPIO_BSRR_BS2 GPIO_BSRR_BS2_Msk /*!< Port x Set bit 2 */
+#define GPIO_BSRR_BS3_Pos (3U)
+#define GPIO_BSRR_BS3_Msk (0x1U << GPIO_BSRR_BS3_Pos) /*!< 0x00000008 */
+#define GPIO_BSRR_BS3 GPIO_BSRR_BS3_Msk /*!< Port x Set bit 3 */
+#define GPIO_BSRR_BS4_Pos (4U)
+#define GPIO_BSRR_BS4_Msk (0x1U << GPIO_BSRR_BS4_Pos) /*!< 0x00000010 */
+#define GPIO_BSRR_BS4 GPIO_BSRR_BS4_Msk /*!< Port x Set bit 4 */
+#define GPIO_BSRR_BS5_Pos (5U)
+#define GPIO_BSRR_BS5_Msk (0x1U << GPIO_BSRR_BS5_Pos) /*!< 0x00000020 */
+#define GPIO_BSRR_BS5 GPIO_BSRR_BS5_Msk /*!< Port x Set bit 5 */
+#define GPIO_BSRR_BS6_Pos (6U)
+#define GPIO_BSRR_BS6_Msk (0x1U << GPIO_BSRR_BS6_Pos) /*!< 0x00000040 */
+#define GPIO_BSRR_BS6 GPIO_BSRR_BS6_Msk /*!< Port x Set bit 6 */
+#define GPIO_BSRR_BS7_Pos (7U)
+#define GPIO_BSRR_BS7_Msk (0x1U << GPIO_BSRR_BS7_Pos) /*!< 0x00000080 */
+#define GPIO_BSRR_BS7 GPIO_BSRR_BS7_Msk /*!< Port x Set bit 7 */
+#define GPIO_BSRR_BS8_Pos (8U)
+#define GPIO_BSRR_BS8_Msk (0x1U << GPIO_BSRR_BS8_Pos) /*!< 0x00000100 */
+#define GPIO_BSRR_BS8 GPIO_BSRR_BS8_Msk /*!< Port x Set bit 8 */
+#define GPIO_BSRR_BS9_Pos (9U)
+#define GPIO_BSRR_BS9_Msk (0x1U << GPIO_BSRR_BS9_Pos) /*!< 0x00000200 */
+#define GPIO_BSRR_BS9 GPIO_BSRR_BS9_Msk /*!< Port x Set bit 9 */
+#define GPIO_BSRR_BS10_Pos (10U)
+#define GPIO_BSRR_BS10_Msk (0x1U << GPIO_BSRR_BS10_Pos) /*!< 0x00000400 */
+#define GPIO_BSRR_BS10 GPIO_BSRR_BS10_Msk /*!< Port x Set bit 10 */
+#define GPIO_BSRR_BS11_Pos (11U)
+#define GPIO_BSRR_BS11_Msk (0x1U << GPIO_BSRR_BS11_Pos) /*!< 0x00000800 */
+#define GPIO_BSRR_BS11 GPIO_BSRR_BS11_Msk /*!< Port x Set bit 11 */
+#define GPIO_BSRR_BS12_Pos (12U)
+#define GPIO_BSRR_BS12_Msk (0x1U << GPIO_BSRR_BS12_Pos) /*!< 0x00001000 */
+#define GPIO_BSRR_BS12 GPIO_BSRR_BS12_Msk /*!< Port x Set bit 12 */
+#define GPIO_BSRR_BS13_Pos (13U)
+#define GPIO_BSRR_BS13_Msk (0x1U << GPIO_BSRR_BS13_Pos) /*!< 0x00002000 */
+#define GPIO_BSRR_BS13 GPIO_BSRR_BS13_Msk /*!< Port x Set bit 13 */
+#define GPIO_BSRR_BS14_Pos (14U)
+#define GPIO_BSRR_BS14_Msk (0x1U << GPIO_BSRR_BS14_Pos) /*!< 0x00004000 */
+#define GPIO_BSRR_BS14 GPIO_BSRR_BS14_Msk /*!< Port x Set bit 14 */
+#define GPIO_BSRR_BS15_Pos (15U)
+#define GPIO_BSRR_BS15_Msk (0x1U << GPIO_BSRR_BS15_Pos) /*!< 0x00008000 */
+#define GPIO_BSRR_BS15 GPIO_BSRR_BS15_Msk /*!< Port x Set bit 15 */
+
+#define GPIO_BSRR_BR0_Pos (16U)
+#define GPIO_BSRR_BR0_Msk (0x1U << GPIO_BSRR_BR0_Pos) /*!< 0x00010000 */
+#define GPIO_BSRR_BR0 GPIO_BSRR_BR0_Msk /*!< Port x Reset bit 0 */
+#define GPIO_BSRR_BR1_Pos (17U)
+#define GPIO_BSRR_BR1_Msk (0x1U << GPIO_BSRR_BR1_Pos) /*!< 0x00020000 */
+#define GPIO_BSRR_BR1 GPIO_BSRR_BR1_Msk /*!< Port x Reset bit 1 */
+#define GPIO_BSRR_BR2_Pos (18U)
+#define GPIO_BSRR_BR2_Msk (0x1U << GPIO_BSRR_BR2_Pos) /*!< 0x00040000 */
+#define GPIO_BSRR_BR2 GPIO_BSRR_BR2_Msk /*!< Port x Reset bit 2 */
+#define GPIO_BSRR_BR3_Pos (19U)
+#define GPIO_BSRR_BR3_Msk (0x1U << GPIO_BSRR_BR3_Pos) /*!< 0x00080000 */
+#define GPIO_BSRR_BR3 GPIO_BSRR_BR3_Msk /*!< Port x Reset bit 3 */
+#define GPIO_BSRR_BR4_Pos (20U)
+#define GPIO_BSRR_BR4_Msk (0x1U << GPIO_BSRR_BR4_Pos) /*!< 0x00100000 */
+#define GPIO_BSRR_BR4 GPIO_BSRR_BR4_Msk /*!< Port x Reset bit 4 */
+#define GPIO_BSRR_BR5_Pos (21U)
+#define GPIO_BSRR_BR5_Msk (0x1U << GPIO_BSRR_BR5_Pos) /*!< 0x00200000 */
+#define GPIO_BSRR_BR5 GPIO_BSRR_BR5_Msk /*!< Port x Reset bit 5 */
+#define GPIO_BSRR_BR6_Pos (22U)
+#define GPIO_BSRR_BR6_Msk (0x1U << GPIO_BSRR_BR6_Pos) /*!< 0x00400000 */
+#define GPIO_BSRR_BR6 GPIO_BSRR_BR6_Msk /*!< Port x Reset bit 6 */
+#define GPIO_BSRR_BR7_Pos (23U)
+#define GPIO_BSRR_BR7_Msk (0x1U << GPIO_BSRR_BR7_Pos) /*!< 0x00800000 */
+#define GPIO_BSRR_BR7 GPIO_BSRR_BR7_Msk /*!< Port x Reset bit 7 */
+#define GPIO_BSRR_BR8_Pos (24U)
+#define GPIO_BSRR_BR8_Msk (0x1U << GPIO_BSRR_BR8_Pos) /*!< 0x01000000 */
+#define GPIO_BSRR_BR8 GPIO_BSRR_BR8_Msk /*!< Port x Reset bit 8 */
+#define GPIO_BSRR_BR9_Pos (25U)
+#define GPIO_BSRR_BR9_Msk (0x1U << GPIO_BSRR_BR9_Pos) /*!< 0x02000000 */
+#define GPIO_BSRR_BR9 GPIO_BSRR_BR9_Msk /*!< Port x Reset bit 9 */
+#define GPIO_BSRR_BR10_Pos (26U)
+#define GPIO_BSRR_BR10_Msk (0x1U << GPIO_BSRR_BR10_Pos) /*!< 0x04000000 */
+#define GPIO_BSRR_BR10 GPIO_BSRR_BR10_Msk /*!< Port x Reset bit 10 */
+#define GPIO_BSRR_BR11_Pos (27U)
+#define GPIO_BSRR_BR11_Msk (0x1U << GPIO_BSRR_BR11_Pos) /*!< 0x08000000 */
+#define GPIO_BSRR_BR11 GPIO_BSRR_BR11_Msk /*!< Port x Reset bit 11 */
+#define GPIO_BSRR_BR12_Pos (28U)
+#define GPIO_BSRR_BR12_Msk (0x1U << GPIO_BSRR_BR12_Pos) /*!< 0x10000000 */
+#define GPIO_BSRR_BR12 GPIO_BSRR_BR12_Msk /*!< Port x Reset bit 12 */
+#define GPIO_BSRR_BR13_Pos (29U)
+#define GPIO_BSRR_BR13_Msk (0x1U << GPIO_BSRR_BR13_Pos) /*!< 0x20000000 */
+#define GPIO_BSRR_BR13 GPIO_BSRR_BR13_Msk /*!< Port x Reset bit 13 */
+#define GPIO_BSRR_BR14_Pos (30U)
+#define GPIO_BSRR_BR14_Msk (0x1U << GPIO_BSRR_BR14_Pos) /*!< 0x40000000 */
+#define GPIO_BSRR_BR14 GPIO_BSRR_BR14_Msk /*!< Port x Reset bit 14 */
+#define GPIO_BSRR_BR15_Pos (31U)
+#define GPIO_BSRR_BR15_Msk (0x1U << GPIO_BSRR_BR15_Pos) /*!< 0x80000000 */
+#define GPIO_BSRR_BR15 GPIO_BSRR_BR15_Msk /*!< Port x Reset bit 15 */
+
+/******************* Bit definition for GPIO_BRR register *******************/
+#define GPIO_BRR_BR0_Pos (0U)
+#define GPIO_BRR_BR0_Msk (0x1U << GPIO_BRR_BR0_Pos) /*!< 0x00000001 */
+#define GPIO_BRR_BR0 GPIO_BRR_BR0_Msk /*!< Port x Reset bit 0 */
+#define GPIO_BRR_BR1_Pos (1U)
+#define GPIO_BRR_BR1_Msk (0x1U << GPIO_BRR_BR1_Pos) /*!< 0x00000002 */
+#define GPIO_BRR_BR1 GPIO_BRR_BR1_Msk /*!< Port x Reset bit 1 */
+#define GPIO_BRR_BR2_Pos (2U)
+#define GPIO_BRR_BR2_Msk (0x1U << GPIO_BRR_BR2_Pos) /*!< 0x00000004 */
+#define GPIO_BRR_BR2 GPIO_BRR_BR2_Msk /*!< Port x Reset bit 2 */
+#define GPIO_BRR_BR3_Pos (3U)
+#define GPIO_BRR_BR3_Msk (0x1U << GPIO_BRR_BR3_Pos) /*!< 0x00000008 */
+#define GPIO_BRR_BR3 GPIO_BRR_BR3_Msk /*!< Port x Reset bit 3 */
+#define GPIO_BRR_BR4_Pos (4U)
+#define GPIO_BRR_BR4_Msk (0x1U << GPIO_BRR_BR4_Pos) /*!< 0x00000010 */
+#define GPIO_BRR_BR4 GPIO_BRR_BR4_Msk /*!< Port x Reset bit 4 */
+#define GPIO_BRR_BR5_Pos (5U)
+#define GPIO_BRR_BR5_Msk (0x1U << GPIO_BRR_BR5_Pos) /*!< 0x00000020 */
+#define GPIO_BRR_BR5 GPIO_BRR_BR5_Msk /*!< Port x Reset bit 5 */
+#define GPIO_BRR_BR6_Pos (6U)
+#define GPIO_BRR_BR6_Msk (0x1U << GPIO_BRR_BR6_Pos) /*!< 0x00000040 */
+#define GPIO_BRR_BR6 GPIO_BRR_BR6_Msk /*!< Port x Reset bit 6 */
+#define GPIO_BRR_BR7_Pos (7U)
+#define GPIO_BRR_BR7_Msk (0x1U << GPIO_BRR_BR7_Pos) /*!< 0x00000080 */
+#define GPIO_BRR_BR7 GPIO_BRR_BR7_Msk /*!< Port x Reset bit 7 */
+#define GPIO_BRR_BR8_Pos (8U)
+#define GPIO_BRR_BR8_Msk (0x1U << GPIO_BRR_BR8_Pos) /*!< 0x00000100 */
+#define GPIO_BRR_BR8 GPIO_BRR_BR8_Msk /*!< Port x Reset bit 8 */
+#define GPIO_BRR_BR9_Pos (9U)
+#define GPIO_BRR_BR9_Msk (0x1U << GPIO_BRR_BR9_Pos) /*!< 0x00000200 */
+#define GPIO_BRR_BR9 GPIO_BRR_BR9_Msk /*!< Port x Reset bit 9 */
+#define GPIO_BRR_BR10_Pos (10U)
+#define GPIO_BRR_BR10_Msk (0x1U << GPIO_BRR_BR10_Pos) /*!< 0x00000400 */
+#define GPIO_BRR_BR10 GPIO_BRR_BR10_Msk /*!< Port x Reset bit 10 */
+#define GPIO_BRR_BR11_Pos (11U)
+#define GPIO_BRR_BR11_Msk (0x1U << GPIO_BRR_BR11_Pos) /*!< 0x00000800 */
+#define GPIO_BRR_BR11 GPIO_BRR_BR11_Msk /*!< Port x Reset bit 11 */
+#define GPIO_BRR_BR12_Pos (12U)
+#define GPIO_BRR_BR12_Msk (0x1U << GPIO_BRR_BR12_Pos) /*!< 0x00001000 */
+#define GPIO_BRR_BR12 GPIO_BRR_BR12_Msk /*!< Port x Reset bit 12 */
+#define GPIO_BRR_BR13_Pos (13U)
+#define GPIO_BRR_BR13_Msk (0x1U << GPIO_BRR_BR13_Pos) /*!< 0x00002000 */
+#define GPIO_BRR_BR13 GPIO_BRR_BR13_Msk /*!< Port x Reset bit 13 */
+#define GPIO_BRR_BR14_Pos (14U)
+#define GPIO_BRR_BR14_Msk (0x1U << GPIO_BRR_BR14_Pos) /*!< 0x00004000 */
+#define GPIO_BRR_BR14 GPIO_BRR_BR14_Msk /*!< Port x Reset bit 14 */
+#define GPIO_BRR_BR15_Pos (15U)
+#define GPIO_BRR_BR15_Msk (0x1U << GPIO_BRR_BR15_Pos) /*!< 0x00008000 */
+#define GPIO_BRR_BR15 GPIO_BRR_BR15_Msk /*!< Port x Reset bit 15 */
+
+/****************** Bit definition for GPIO_LCKR register *******************/
+#define GPIO_LCKR_LCK0_Pos (0U)
+#define GPIO_LCKR_LCK0_Msk (0x1U << GPIO_LCKR_LCK0_Pos) /*!< 0x00000001 */
+#define GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk /*!< Port x Lock bit 0 */
+#define GPIO_LCKR_LCK1_Pos (1U)
+#define GPIO_LCKR_LCK1_Msk (0x1U << GPIO_LCKR_LCK1_Pos) /*!< 0x00000002 */
+#define GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk /*!< Port x Lock bit 1 */
+#define GPIO_LCKR_LCK2_Pos (2U)
+#define GPIO_LCKR_LCK2_Msk (0x1U << GPIO_LCKR_LCK2_Pos) /*!< 0x00000004 */
+#define GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk /*!< Port x Lock bit 2 */
+#define GPIO_LCKR_LCK3_Pos (3U)
+#define GPIO_LCKR_LCK3_Msk (0x1U << GPIO_LCKR_LCK3_Pos) /*!< 0x00000008 */
+#define GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk /*!< Port x Lock bit 3 */
+#define GPIO_LCKR_LCK4_Pos (4U)
+#define GPIO_LCKR_LCK4_Msk (0x1U << GPIO_LCKR_LCK4_Pos) /*!< 0x00000010 */
+#define GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk /*!< Port x Lock bit 4 */
+#define GPIO_LCKR_LCK5_Pos (5U)
+#define GPIO_LCKR_LCK5_Msk (0x1U << GPIO_LCKR_LCK5_Pos) /*!< 0x00000020 */
+#define GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk /*!< Port x Lock bit 5 */
+#define GPIO_LCKR_LCK6_Pos (6U)
+#define GPIO_LCKR_LCK6_Msk (0x1U << GPIO_LCKR_LCK6_Pos) /*!< 0x00000040 */
+#define GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk /*!< Port x Lock bit 6 */
+#define GPIO_LCKR_LCK7_Pos (7U)
+#define GPIO_LCKR_LCK7_Msk (0x1U << GPIO_LCKR_LCK7_Pos) /*!< 0x00000080 */
+#define GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk /*!< Port x Lock bit 7 */
+#define GPIO_LCKR_LCK8_Pos (8U)
+#define GPIO_LCKR_LCK8_Msk (0x1U << GPIO_LCKR_LCK8_Pos) /*!< 0x00000100 */
+#define GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk /*!< Port x Lock bit 8 */
+#define GPIO_LCKR_LCK9_Pos (9U)
+#define GPIO_LCKR_LCK9_Msk (0x1U << GPIO_LCKR_LCK9_Pos) /*!< 0x00000200 */
+#define GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk /*!< Port x Lock bit 9 */
+#define GPIO_LCKR_LCK10_Pos (10U)
+#define GPIO_LCKR_LCK10_Msk (0x1U << GPIO_LCKR_LCK10_Pos) /*!< 0x00000400 */
+#define GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk /*!< Port x Lock bit 10 */
+#define GPIO_LCKR_LCK11_Pos (11U)
+#define GPIO_LCKR_LCK11_Msk (0x1U << GPIO_LCKR_LCK11_Pos) /*!< 0x00000800 */
+#define GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk /*!< Port x Lock bit 11 */
+#define GPIO_LCKR_LCK12_Pos (12U)
+#define GPIO_LCKR_LCK12_Msk (0x1U << GPIO_LCKR_LCK12_Pos) /*!< 0x00001000 */
+#define GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk /*!< Port x Lock bit 12 */
+#define GPIO_LCKR_LCK13_Pos (13U)
+#define GPIO_LCKR_LCK13_Msk (0x1U << GPIO_LCKR_LCK13_Pos) /*!< 0x00002000 */
+#define GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk /*!< Port x Lock bit 13 */
+#define GPIO_LCKR_LCK14_Pos (14U)
+#define GPIO_LCKR_LCK14_Msk (0x1U << GPIO_LCKR_LCK14_Pos) /*!< 0x00004000 */
+#define GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk /*!< Port x Lock bit 14 */
+#define GPIO_LCKR_LCK15_Pos (15U)
+#define GPIO_LCKR_LCK15_Msk (0x1U << GPIO_LCKR_LCK15_Pos) /*!< 0x00008000 */
+#define GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk /*!< Port x Lock bit 15 */
+#define GPIO_LCKR_LCKK_Pos (16U)
+#define GPIO_LCKR_LCKK_Msk (0x1U << GPIO_LCKR_LCKK_Pos) /*!< 0x00010000 */
+#define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk /*!< Lock key */
+
+/*----------------------------------------------------------------------------*/
+
+/****************** Bit definition for AFIO_EVCR register *******************/
+#define AFIO_EVCR_PIN_Pos (0U)
+#define AFIO_EVCR_PIN_Msk (0xFU << AFIO_EVCR_PIN_Pos) /*!< 0x0000000F */
+#define AFIO_EVCR_PIN AFIO_EVCR_PIN_Msk /*!< PIN[3:0] bits (Pin selection) */
+#define AFIO_EVCR_PIN_0 (0x1U << AFIO_EVCR_PIN_Pos) /*!< 0x00000001 */
+#define AFIO_EVCR_PIN_1 (0x2U << AFIO_EVCR_PIN_Pos) /*!< 0x00000002 */
+#define AFIO_EVCR_PIN_2 (0x4U << AFIO_EVCR_PIN_Pos) /*!< 0x00000004 */
+#define AFIO_EVCR_PIN_3 (0x8U << AFIO_EVCR_PIN_Pos) /*!< 0x00000008 */
+
+/*!< PIN configuration */
+#define AFIO_EVCR_PIN_PX0 ((uint32_t)0x00000000) /*!< Pin 0 selected */
+#define AFIO_EVCR_PIN_PX1_Pos (0U)
+#define AFIO_EVCR_PIN_PX1_Msk (0x1U << AFIO_EVCR_PIN_PX1_Pos) /*!< 0x00000001 */
+#define AFIO_EVCR_PIN_PX1 AFIO_EVCR_PIN_PX1_Msk /*!< Pin 1 selected */
+#define AFIO_EVCR_PIN_PX2_Pos (1U)
+#define AFIO_EVCR_PIN_PX2_Msk (0x1U << AFIO_EVCR_PIN_PX2_Pos) /*!< 0x00000002 */
+#define AFIO_EVCR_PIN_PX2 AFIO_EVCR_PIN_PX2_Msk /*!< Pin 2 selected */
+#define AFIO_EVCR_PIN_PX3_Pos (0U)
+#define AFIO_EVCR_PIN_PX3_Msk (0x3U << AFIO_EVCR_PIN_PX3_Pos) /*!< 0x00000003 */
+#define AFIO_EVCR_PIN_PX3 AFIO_EVCR_PIN_PX3_Msk /*!< Pin 3 selected */
+#define AFIO_EVCR_PIN_PX4_Pos (2U)
+#define AFIO_EVCR_PIN_PX4_Msk (0x1U << AFIO_EVCR_PIN_PX4_Pos) /*!< 0x00000004 */
+#define AFIO_EVCR_PIN_PX4 AFIO_EVCR_PIN_PX4_Msk /*!< Pin 4 selected */
+#define AFIO_EVCR_PIN_PX5_Pos (0U)
+#define AFIO_EVCR_PIN_PX5_Msk (0x5U << AFIO_EVCR_PIN_PX5_Pos) /*!< 0x00000005 */
+#define AFIO_EVCR_PIN_PX5 AFIO_EVCR_PIN_PX5_Msk /*!< Pin 5 selected */
+#define AFIO_EVCR_PIN_PX6_Pos (1U)
+#define AFIO_EVCR_PIN_PX6_Msk (0x3U << AFIO_EVCR_PIN_PX6_Pos) /*!< 0x00000006 */
+#define AFIO_EVCR_PIN_PX6 AFIO_EVCR_PIN_PX6_Msk /*!< Pin 6 selected */
+#define AFIO_EVCR_PIN_PX7_Pos (0U)
+#define AFIO_EVCR_PIN_PX7_Msk (0x7U << AFIO_EVCR_PIN_PX7_Pos) /*!< 0x00000007 */
+#define AFIO_EVCR_PIN_PX7 AFIO_EVCR_PIN_PX7_Msk /*!< Pin 7 selected */
+#define AFIO_EVCR_PIN_PX8_Pos (3U)
+#define AFIO_EVCR_PIN_PX8_Msk (0x1U << AFIO_EVCR_PIN_PX8_Pos) /*!< 0x00000008 */
+#define AFIO_EVCR_PIN_PX8 AFIO_EVCR_PIN_PX8_Msk /*!< Pin 8 selected */
+#define AFIO_EVCR_PIN_PX9_Pos (0U)
+#define AFIO_EVCR_PIN_PX9_Msk (0x9U << AFIO_EVCR_PIN_PX9_Pos) /*!< 0x00000009 */
+#define AFIO_EVCR_PIN_PX9 AFIO_EVCR_PIN_PX9_Msk /*!< Pin 9 selected */
+#define AFIO_EVCR_PIN_PX10_Pos (1U)
+#define AFIO_EVCR_PIN_PX10_Msk (0x5U << AFIO_EVCR_PIN_PX10_Pos) /*!< 0x0000000A */
+#define AFIO_EVCR_PIN_PX10 AFIO_EVCR_PIN_PX10_Msk /*!< Pin 10 selected */
+#define AFIO_EVCR_PIN_PX11_Pos (0U)
+#define AFIO_EVCR_PIN_PX11_Msk (0xBU << AFIO_EVCR_PIN_PX11_Pos) /*!< 0x0000000B */
+#define AFIO_EVCR_PIN_PX11 AFIO_EVCR_PIN_PX11_Msk /*!< Pin 11 selected */
+#define AFIO_EVCR_PIN_PX12_Pos (2U)
+#define AFIO_EVCR_PIN_PX12_Msk (0x3U << AFIO_EVCR_PIN_PX12_Pos) /*!< 0x0000000C */
+#define AFIO_EVCR_PIN_PX12 AFIO_EVCR_PIN_PX12_Msk /*!< Pin 12 selected */
+#define AFIO_EVCR_PIN_PX13_Pos (0U)
+#define AFIO_EVCR_PIN_PX13_Msk (0xDU << AFIO_EVCR_PIN_PX13_Pos) /*!< 0x0000000D */
+#define AFIO_EVCR_PIN_PX13 AFIO_EVCR_PIN_PX13_Msk /*!< Pin 13 selected */
+#define AFIO_EVCR_PIN_PX14_Pos (1U)
+#define AFIO_EVCR_PIN_PX14_Msk (0x7U << AFIO_EVCR_PIN_PX14_Pos) /*!< 0x0000000E */
+#define AFIO_EVCR_PIN_PX14 AFIO_EVCR_PIN_PX14_Msk /*!< Pin 14 selected */
+#define AFIO_EVCR_PIN_PX15_Pos (0U)
+#define AFIO_EVCR_PIN_PX15_Msk (0xFU << AFIO_EVCR_PIN_PX15_Pos) /*!< 0x0000000F */
+#define AFIO_EVCR_PIN_PX15 AFIO_EVCR_PIN_PX15_Msk /*!< Pin 15 selected */
+
+#define AFIO_EVCR_PORT_Pos (4U)
+#define AFIO_EVCR_PORT_Msk (0x7U << AFIO_EVCR_PORT_Pos) /*!< 0x00000070 */
+#define AFIO_EVCR_PORT AFIO_EVCR_PORT_Msk /*!< PORT[2:0] bits (Port selection) */
+#define AFIO_EVCR_PORT_0 (0x1U << AFIO_EVCR_PORT_Pos) /*!< 0x00000010 */
+#define AFIO_EVCR_PORT_1 (0x2U << AFIO_EVCR_PORT_Pos) /*!< 0x00000020 */
+#define AFIO_EVCR_PORT_2 (0x4U << AFIO_EVCR_PORT_Pos) /*!< 0x00000040 */
+
+/*!< PORT configuration */
+#define AFIO_EVCR_PORT_PA ((uint32_t)0x00000000) /*!< Port A selected */
+#define AFIO_EVCR_PORT_PB_Pos (4U)
+#define AFIO_EVCR_PORT_PB_Msk (0x1U << AFIO_EVCR_PORT_PB_Pos) /*!< 0x00000010 */
+#define AFIO_EVCR_PORT_PB AFIO_EVCR_PORT_PB_Msk /*!< Port B selected */
+#define AFIO_EVCR_PORT_PC_Pos (5U)
+#define AFIO_EVCR_PORT_PC_Msk (0x1U << AFIO_EVCR_PORT_PC_Pos) /*!< 0x00000020 */
+#define AFIO_EVCR_PORT_PC AFIO_EVCR_PORT_PC_Msk /*!< Port C selected */
+#define AFIO_EVCR_PORT_PD_Pos (4U)
+#define AFIO_EVCR_PORT_PD_Msk (0x3U << AFIO_EVCR_PORT_PD_Pos) /*!< 0x00000030 */
+#define AFIO_EVCR_PORT_PD AFIO_EVCR_PORT_PD_Msk /*!< Port D selected */
+#define AFIO_EVCR_PORT_PE_Pos (6U)
+#define AFIO_EVCR_PORT_PE_Msk (0x1U << AFIO_EVCR_PORT_PE_Pos) /*!< 0x00000040 */
+#define AFIO_EVCR_PORT_PE AFIO_EVCR_PORT_PE_Msk /*!< Port E selected */
+
+#define AFIO_EVCR_EVOE_Pos (7U)
+#define AFIO_EVCR_EVOE_Msk (0x1U << AFIO_EVCR_EVOE_Pos) /*!< 0x00000080 */
+#define AFIO_EVCR_EVOE AFIO_EVCR_EVOE_Msk /*!< Event Output Enable */
+
+/****************** Bit definition for AFIO_MAPR register *******************/
+#define AFIO_MAPR_SPI1_REMAP_Pos (0U)
+#define AFIO_MAPR_SPI1_REMAP_Msk (0x1U << AFIO_MAPR_SPI1_REMAP_Pos) /*!< 0x00000001 */
+#define AFIO_MAPR_SPI1_REMAP AFIO_MAPR_SPI1_REMAP_Msk /*!< SPI1 remapping */
+#define AFIO_MAPR_I2C1_REMAP_Pos (1U)
+#define AFIO_MAPR_I2C1_REMAP_Msk (0x1U << AFIO_MAPR_I2C1_REMAP_Pos) /*!< 0x00000002 */
+#define AFIO_MAPR_I2C1_REMAP AFIO_MAPR_I2C1_REMAP_Msk /*!< I2C1 remapping */
+#define AFIO_MAPR_USART1_REMAP_Pos (2U)
+#define AFIO_MAPR_USART1_REMAP_Msk (0x1U << AFIO_MAPR_USART1_REMAP_Pos) /*!< 0x00000004 */
+#define AFIO_MAPR_USART1_REMAP AFIO_MAPR_USART1_REMAP_Msk /*!< USART1 remapping */
+#define AFIO_MAPR_USART2_REMAP_Pos (3U)
+#define AFIO_MAPR_USART2_REMAP_Msk (0x1U << AFIO_MAPR_USART2_REMAP_Pos) /*!< 0x00000008 */
+#define AFIO_MAPR_USART2_REMAP AFIO_MAPR_USART2_REMAP_Msk /*!< USART2 remapping */
+
+#define AFIO_MAPR_USART3_REMAP_Pos (4U)
+#define AFIO_MAPR_USART3_REMAP_Msk (0x3U << AFIO_MAPR_USART3_REMAP_Pos) /*!< 0x00000030 */
+#define AFIO_MAPR_USART3_REMAP AFIO_MAPR_USART3_REMAP_Msk /*!< USART3_REMAP[1:0] bits (USART3 remapping) */
+#define AFIO_MAPR_USART3_REMAP_0 (0x1U << AFIO_MAPR_USART3_REMAP_Pos) /*!< 0x00000010 */
+#define AFIO_MAPR_USART3_REMAP_1 (0x2U << AFIO_MAPR_USART3_REMAP_Pos) /*!< 0x00000020 */
+
+/* USART3_REMAP configuration */
+#define AFIO_MAPR_USART3_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14) */
+#define AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Pos (4U)
+#define AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Msk (0x1U << AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Pos) /*!< 0x00000010 */
+#define AFIO_MAPR_USART3_REMAP_PARTIALREMAP AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Msk /*!< Partial remap (TX/PC10, RX/PC11, CK/PC12, CTS/PB13, RTS/PB14) */
+#define AFIO_MAPR_USART3_REMAP_FULLREMAP_Pos (4U)
+#define AFIO_MAPR_USART3_REMAP_FULLREMAP_Msk (0x3U << AFIO_MAPR_USART3_REMAP_FULLREMAP_Pos) /*!< 0x00000030 */
+#define AFIO_MAPR_USART3_REMAP_FULLREMAP AFIO_MAPR_USART3_REMAP_FULLREMAP_Msk /*!< Full remap (TX/PD8, RX/PD9, CK/PD10, CTS/PD11, RTS/PD12) */
+
+#define AFIO_MAPR_TIM1_REMAP_Pos (6U)
+#define AFIO_MAPR_TIM1_REMAP_Msk (0x3U << AFIO_MAPR_TIM1_REMAP_Pos) /*!< 0x000000C0 */
+#define AFIO_MAPR_TIM1_REMAP AFIO_MAPR_TIM1_REMAP_Msk /*!< TIM1_REMAP[1:0] bits (TIM1 remapping) */
+#define AFIO_MAPR_TIM1_REMAP_0 (0x1U << AFIO_MAPR_TIM1_REMAP_Pos) /*!< 0x00000040 */
+#define AFIO_MAPR_TIM1_REMAP_1 (0x2U << AFIO_MAPR_TIM1_REMAP_Pos) /*!< 0x00000080 */
+
+/*!< TIM1_REMAP configuration */
+#define AFIO_MAPR_TIM1_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15) */
+#define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Pos (6U)
+#define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Msk (0x1U << AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Pos) /*!< 0x00000040 */
+#define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Msk /*!< Partial remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PA6, CH1N/PA7, CH2N/PB0, CH3N/PB1) */
+#define AFIO_MAPR_TIM1_REMAP_FULLREMAP_Pos (6U)
+#define AFIO_MAPR_TIM1_REMAP_FULLREMAP_Msk (0x3U << AFIO_MAPR_TIM1_REMAP_FULLREMAP_Pos) /*!< 0x000000C0 */
+#define AFIO_MAPR_TIM1_REMAP_FULLREMAP AFIO_MAPR_TIM1_REMAP_FULLREMAP_Msk /*!< Full remap (ETR/PE7, CH1/PE9, CH2/PE11, CH3/PE13, CH4/PE14, BKIN/PE15, CH1N/PE8, CH2N/PE10, CH3N/PE12) */
+
+#define AFIO_MAPR_TIM2_REMAP_Pos (8U)
+#define AFIO_MAPR_TIM2_REMAP_Msk (0x3U << AFIO_MAPR_TIM2_REMAP_Pos) /*!< 0x00000300 */
+#define AFIO_MAPR_TIM2_REMAP AFIO_MAPR_TIM2_REMAP_Msk /*!< TIM2_REMAP[1:0] bits (TIM2 remapping) */
+#define AFIO_MAPR_TIM2_REMAP_0 (0x1U << AFIO_MAPR_TIM2_REMAP_Pos) /*!< 0x00000100 */
+#define AFIO_MAPR_TIM2_REMAP_1 (0x2U << AFIO_MAPR_TIM2_REMAP_Pos) /*!< 0x00000200 */
+
+/*!< TIM2_REMAP configuration */
+#define AFIO_MAPR_TIM2_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3) */
+#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Pos (8U)
+#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Msk (0x1U << AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Pos) /*!< 0x00000100 */
+#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1 AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Msk /*!< Partial remap (CH1/ETR/PA15, CH2/PB3, CH3/PA2, CH4/PA3) */
+#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2_Pos (9U)
+#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2_Msk (0x1U << AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2_Pos) /*!< 0x00000200 */
+#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2 AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2_Msk /*!< Partial remap (CH1/ETR/PA0, CH2/PA1, CH3/PB10, CH4/PB11) */
+#define AFIO_MAPR_TIM2_REMAP_FULLREMAP_Pos (8U)
+#define AFIO_MAPR_TIM2_REMAP_FULLREMAP_Msk (0x3U << AFIO_MAPR_TIM2_REMAP_FULLREMAP_Pos) /*!< 0x00000300 */
+#define AFIO_MAPR_TIM2_REMAP_FULLREMAP AFIO_MAPR_TIM2_REMAP_FULLREMAP_Msk /*!< Full remap (CH1/ETR/PA15, CH2/PB3, CH3/PB10, CH4/PB11) */
+
+#define AFIO_MAPR_TIM3_REMAP_Pos (10U)
+#define AFIO_MAPR_TIM3_REMAP_Msk (0x3U << AFIO_MAPR_TIM3_REMAP_Pos) /*!< 0x00000C00 */
+#define AFIO_MAPR_TIM3_REMAP AFIO_MAPR_TIM3_REMAP_Msk /*!< TIM3_REMAP[1:0] bits (TIM3 remapping) */
+#define AFIO_MAPR_TIM3_REMAP_0 (0x1U << AFIO_MAPR_TIM3_REMAP_Pos) /*!< 0x00000400 */
+#define AFIO_MAPR_TIM3_REMAP_1 (0x2U << AFIO_MAPR_TIM3_REMAP_Pos) /*!< 0x00000800 */
+
+/*!< TIM3_REMAP configuration */
+#define AFIO_MAPR_TIM3_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1) */
+#define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Pos (11U)
+#define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Msk (0x1U << AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Pos) /*!< 0x00000800 */
+#define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Msk /*!< Partial remap (CH1/PB4, CH2/PB5, CH3/PB0, CH4/PB1) */
+#define AFIO_MAPR_TIM3_REMAP_FULLREMAP_Pos (10U)
+#define AFIO_MAPR_TIM3_REMAP_FULLREMAP_Msk (0x3U << AFIO_MAPR_TIM3_REMAP_FULLREMAP_Pos) /*!< 0x00000C00 */
+#define AFIO_MAPR_TIM3_REMAP_FULLREMAP AFIO_MAPR_TIM3_REMAP_FULLREMAP_Msk /*!< Full remap (CH1/PC6, CH2/PC7, CH3/PC8, CH4/PC9) */
+
+#define AFIO_MAPR_TIM4_REMAP_Pos (12U)
+#define AFIO_MAPR_TIM4_REMAP_Msk (0x1U << AFIO_MAPR_TIM4_REMAP_Pos) /*!< 0x00001000 */
+#define AFIO_MAPR_TIM4_REMAP AFIO_MAPR_TIM4_REMAP_Msk /*!< TIM4_REMAP bit (TIM4 remapping) */
+
+
+#define AFIO_MAPR_PD01_REMAP_Pos (15U)
+#define AFIO_MAPR_PD01_REMAP_Msk (0x1U << AFIO_MAPR_PD01_REMAP_Pos) /*!< 0x00008000 */
+#define AFIO_MAPR_PD01_REMAP AFIO_MAPR_PD01_REMAP_Msk /*!< Port D0/Port D1 mapping on OSC_IN/OSC_OUT */
+#define AFIO_MAPR_TIM5CH4_IREMAP_Pos (16U)
+#define AFIO_MAPR_TIM5CH4_IREMAP_Msk (0x1U << AFIO_MAPR_TIM5CH4_IREMAP_Pos) /*!< 0x00010000 */
+#define AFIO_MAPR_TIM5CH4_IREMAP AFIO_MAPR_TIM5CH4_IREMAP_Msk /*!< TIM5 Channel4 Internal Remap */
+
+/*!< SWJ_CFG configuration */
+#define AFIO_MAPR_SWJ_CFG_Pos (24U)
+#define AFIO_MAPR_SWJ_CFG_Msk (0x7U << AFIO_MAPR_SWJ_CFG_Pos) /*!< 0x07000000 */
+#define AFIO_MAPR_SWJ_CFG AFIO_MAPR_SWJ_CFG_Msk /*!< SWJ_CFG[2:0] bits (Serial Wire JTAG configuration) */
+#define AFIO_MAPR_SWJ_CFG_0 (0x1U << AFIO_MAPR_SWJ_CFG_Pos) /*!< 0x01000000 */
+#define AFIO_MAPR_SWJ_CFG_1 (0x2U << AFIO_MAPR_SWJ_CFG_Pos) /*!< 0x02000000 */
+#define AFIO_MAPR_SWJ_CFG_2 (0x4U << AFIO_MAPR_SWJ_CFG_Pos) /*!< 0x04000000 */
+
+#define AFIO_MAPR_SWJ_CFG_RESET ((uint32_t)0x00000000) /*!< Full SWJ (JTAG-DP + SW-DP) : Reset State */
+#define AFIO_MAPR_SWJ_CFG_NOJNTRST_Pos (24U)
+#define AFIO_MAPR_SWJ_CFG_NOJNTRST_Msk (0x1U << AFIO_MAPR_SWJ_CFG_NOJNTRST_Pos) /*!< 0x01000000 */
+#define AFIO_MAPR_SWJ_CFG_NOJNTRST AFIO_MAPR_SWJ_CFG_NOJNTRST_Msk /*!< Full SWJ (JTAG-DP + SW-DP) but without JNTRST */
+#define AFIO_MAPR_SWJ_CFG_JTAGDISABLE_Pos (25U)
+#define AFIO_MAPR_SWJ_CFG_JTAGDISABLE_Msk (0x1U << AFIO_MAPR_SWJ_CFG_JTAGDISABLE_Pos) /*!< 0x02000000 */
+#define AFIO_MAPR_SWJ_CFG_JTAGDISABLE AFIO_MAPR_SWJ_CFG_JTAGDISABLE_Msk /*!< JTAG-DP Disabled and SW-DP Enabled */
+#define AFIO_MAPR_SWJ_CFG_DISABLE_Pos (26U)
+#define AFIO_MAPR_SWJ_CFG_DISABLE_Msk (0x1U << AFIO_MAPR_SWJ_CFG_DISABLE_Pos) /*!< 0x04000000 */
+#define AFIO_MAPR_SWJ_CFG_DISABLE AFIO_MAPR_SWJ_CFG_DISABLE_Msk /*!< JTAG-DP Disabled and SW-DP Disabled */
+
+
+/***************** Bit definition for AFIO_EXTICR1 register *****************/
+#define AFIO_EXTICR1_EXTI0_Pos (0U)
+#define AFIO_EXTICR1_EXTI0_Msk (0xFU << AFIO_EXTICR1_EXTI0_Pos) /*!< 0x0000000F */
+#define AFIO_EXTICR1_EXTI0 AFIO_EXTICR1_EXTI0_Msk /*!< EXTI 0 configuration */
+#define AFIO_EXTICR1_EXTI1_Pos (4U)
+#define AFIO_EXTICR1_EXTI1_Msk (0xFU << AFIO_EXTICR1_EXTI1_Pos) /*!< 0x000000F0 */
+#define AFIO_EXTICR1_EXTI1 AFIO_EXTICR1_EXTI1_Msk /*!< EXTI 1 configuration */
+#define AFIO_EXTICR1_EXTI2_Pos (8U)
+#define AFIO_EXTICR1_EXTI2_Msk (0xFU << AFIO_EXTICR1_EXTI2_Pos) /*!< 0x00000F00 */
+#define AFIO_EXTICR1_EXTI2 AFIO_EXTICR1_EXTI2_Msk /*!< EXTI 2 configuration */
+#define AFIO_EXTICR1_EXTI3_Pos (12U)
+#define AFIO_EXTICR1_EXTI3_Msk (0xFU << AFIO_EXTICR1_EXTI3_Pos) /*!< 0x0000F000 */
+#define AFIO_EXTICR1_EXTI3 AFIO_EXTICR1_EXTI3_Msk /*!< EXTI 3 configuration */
+
+/*!< EXTI0 configuration */
+#define AFIO_EXTICR1_EXTI0_PA ((uint32_t)0x00000000) /*!< PA[0] pin */
+#define AFIO_EXTICR1_EXTI0_PB_Pos (0U)
+#define AFIO_EXTICR1_EXTI0_PB_Msk (0x1U << AFIO_EXTICR1_EXTI0_PB_Pos) /*!< 0x00000001 */
+#define AFIO_EXTICR1_EXTI0_PB AFIO_EXTICR1_EXTI0_PB_Msk /*!< PB[0] pin */
+#define AFIO_EXTICR1_EXTI0_PC_Pos (1U)
+#define AFIO_EXTICR1_EXTI0_PC_Msk (0x1U << AFIO_EXTICR1_EXTI0_PC_Pos) /*!< 0x00000002 */
+#define AFIO_EXTICR1_EXTI0_PC AFIO_EXTICR1_EXTI0_PC_Msk /*!< PC[0] pin */
+#define AFIO_EXTICR1_EXTI0_PD_Pos (0U)
+#define AFIO_EXTICR1_EXTI0_PD_Msk (0x3U << AFIO_EXTICR1_EXTI0_PD_Pos) /*!< 0x00000003 */
+#define AFIO_EXTICR1_EXTI0_PD AFIO_EXTICR1_EXTI0_PD_Msk /*!< PD[0] pin */
+#define AFIO_EXTICR1_EXTI0_PE_Pos (2U)
+#define AFIO_EXTICR1_EXTI0_PE_Msk (0x1U << AFIO_EXTICR1_EXTI0_PE_Pos) /*!< 0x00000004 */
+#define AFIO_EXTICR1_EXTI0_PE AFIO_EXTICR1_EXTI0_PE_Msk /*!< PE[0] pin */
+#define AFIO_EXTICR1_EXTI0_PF_Pos (0U)
+#define AFIO_EXTICR1_EXTI0_PF_Msk (0x5U << AFIO_EXTICR1_EXTI0_PF_Pos) /*!< 0x00000005 */
+#define AFIO_EXTICR1_EXTI0_PF AFIO_EXTICR1_EXTI0_PF_Msk /*!< PF[0] pin */
+#define AFIO_EXTICR1_EXTI0_PG_Pos (1U)
+#define AFIO_EXTICR1_EXTI0_PG_Msk (0x3U << AFIO_EXTICR1_EXTI0_PG_Pos) /*!< 0x00000006 */
+#define AFIO_EXTICR1_EXTI0_PG AFIO_EXTICR1_EXTI0_PG_Msk /*!< PG[0] pin */
+
+/*!< EXTI1 configuration */
+#define AFIO_EXTICR1_EXTI1_PA ((uint32_t)0x00000000) /*!< PA[1] pin */
+#define AFIO_EXTICR1_EXTI1_PB_Pos (4U)
+#define AFIO_EXTICR1_EXTI1_PB_Msk (0x1U << AFIO_EXTICR1_EXTI1_PB_Pos) /*!< 0x00000010 */
+#define AFIO_EXTICR1_EXTI1_PB AFIO_EXTICR1_EXTI1_PB_Msk /*!< PB[1] pin */
+#define AFIO_EXTICR1_EXTI1_PC_Pos (5U)
+#define AFIO_EXTICR1_EXTI1_PC_Msk (0x1U << AFIO_EXTICR1_EXTI1_PC_Pos) /*!< 0x00000020 */
+#define AFIO_EXTICR1_EXTI1_PC AFIO_EXTICR1_EXTI1_PC_Msk /*!< PC[1] pin */
+#define AFIO_EXTICR1_EXTI1_PD_Pos (4U)
+#define AFIO_EXTICR1_EXTI1_PD_Msk (0x3U << AFIO_EXTICR1_EXTI1_PD_Pos) /*!< 0x00000030 */
+#define AFIO_EXTICR1_EXTI1_PD AFIO_EXTICR1_EXTI1_PD_Msk /*!< PD[1] pin */
+#define AFIO_EXTICR1_EXTI1_PE_Pos (6U)
+#define AFIO_EXTICR1_EXTI1_PE_Msk (0x1U << AFIO_EXTICR1_EXTI1_PE_Pos) /*!< 0x00000040 */
+#define AFIO_EXTICR1_EXTI1_PE AFIO_EXTICR1_EXTI1_PE_Msk /*!< PE[1] pin */
+#define AFIO_EXTICR1_EXTI1_PF_Pos (4U)
+#define AFIO_EXTICR1_EXTI1_PF_Msk (0x5U << AFIO_EXTICR1_EXTI1_PF_Pos) /*!< 0x00000050 */
+#define AFIO_EXTICR1_EXTI1_PF AFIO_EXTICR1_EXTI1_PF_Msk /*!< PF[1] pin */
+#define AFIO_EXTICR1_EXTI1_PG_Pos (5U)
+#define AFIO_EXTICR1_EXTI1_PG_Msk (0x3U << AFIO_EXTICR1_EXTI1_PG_Pos) /*!< 0x00000060 */
+#define AFIO_EXTICR1_EXTI1_PG AFIO_EXTICR1_EXTI1_PG_Msk /*!< PG[1] pin */
+
+/*!< EXTI2 configuration */
+#define AFIO_EXTICR1_EXTI2_PA ((uint32_t)0x00000000) /*!< PA[2] pin */
+#define AFIO_EXTICR1_EXTI2_PB_Pos (8U)
+#define AFIO_EXTICR1_EXTI2_PB_Msk (0x1U << AFIO_EXTICR1_EXTI2_PB_Pos) /*!< 0x00000100 */
+#define AFIO_EXTICR1_EXTI2_PB AFIO_EXTICR1_EXTI2_PB_Msk /*!< PB[2] pin */
+#define AFIO_EXTICR1_EXTI2_PC_Pos (9U)
+#define AFIO_EXTICR1_EXTI2_PC_Msk (0x1U << AFIO_EXTICR1_EXTI2_PC_Pos) /*!< 0x00000200 */
+#define AFIO_EXTICR1_EXTI2_PC AFIO_EXTICR1_EXTI2_PC_Msk /*!< PC[2] pin */
+#define AFIO_EXTICR1_EXTI2_PD_Pos (8U)
+#define AFIO_EXTICR1_EXTI2_PD_Msk (0x3U << AFIO_EXTICR1_EXTI2_PD_Pos) /*!< 0x00000300 */
+#define AFIO_EXTICR1_EXTI2_PD AFIO_EXTICR1_EXTI2_PD_Msk /*!< PD[2] pin */
+#define AFIO_EXTICR1_EXTI2_PE_Pos (10U)
+#define AFIO_EXTICR1_EXTI2_PE_Msk (0x1U << AFIO_EXTICR1_EXTI2_PE_Pos) /*!< 0x00000400 */
+#define AFIO_EXTICR1_EXTI2_PE AFIO_EXTICR1_EXTI2_PE_Msk /*!< PE[2] pin */
+#define AFIO_EXTICR1_EXTI2_PF_Pos (8U)
+#define AFIO_EXTICR1_EXTI2_PF_Msk (0x5U << AFIO_EXTICR1_EXTI2_PF_Pos) /*!< 0x00000500 */
+#define AFIO_EXTICR1_EXTI2_PF AFIO_EXTICR1_EXTI2_PF_Msk /*!< PF[2] pin */
+#define AFIO_EXTICR1_EXTI2_PG_Pos (9U)
+#define AFIO_EXTICR1_EXTI2_PG_Msk (0x3U << AFIO_EXTICR1_EXTI2_PG_Pos) /*!< 0x00000600 */
+#define AFIO_EXTICR1_EXTI2_PG AFIO_EXTICR1_EXTI2_PG_Msk /*!< PG[2] pin */
+
+/*!< EXTI3 configuration */
+#define AFIO_EXTICR1_EXTI3_PA ((uint32_t)0x00000000) /*!< PA[3] pin */
+#define AFIO_EXTICR1_EXTI3_PB_Pos (12U)
+#define AFIO_EXTICR1_EXTI3_PB_Msk (0x1U << AFIO_EXTICR1_EXTI3_PB_Pos) /*!< 0x00001000 */
+#define AFIO_EXTICR1_EXTI3_PB AFIO_EXTICR1_EXTI3_PB_Msk /*!< PB[3] pin */
+#define AFIO_EXTICR1_EXTI3_PC_Pos (13U)
+#define AFIO_EXTICR1_EXTI3_PC_Msk (0x1U << AFIO_EXTICR1_EXTI3_PC_Pos) /*!< 0x00002000 */
+#define AFIO_EXTICR1_EXTI3_PC AFIO_EXTICR1_EXTI3_PC_Msk /*!< PC[3] pin */
+#define AFIO_EXTICR1_EXTI3_PD_Pos (12U)
+#define AFIO_EXTICR1_EXTI3_PD_Msk (0x3U << AFIO_EXTICR1_EXTI3_PD_Pos) /*!< 0x00003000 */
+#define AFIO_EXTICR1_EXTI3_PD AFIO_EXTICR1_EXTI3_PD_Msk /*!< PD[3] pin */
+#define AFIO_EXTICR1_EXTI3_PE_Pos (14U)
+#define AFIO_EXTICR1_EXTI3_PE_Msk (0x1U << AFIO_EXTICR1_EXTI3_PE_Pos) /*!< 0x00004000 */
+#define AFIO_EXTICR1_EXTI3_PE AFIO_EXTICR1_EXTI3_PE_Msk /*!< PE[3] pin */
+#define AFIO_EXTICR1_EXTI3_PF_Pos (12U)
+#define AFIO_EXTICR1_EXTI3_PF_Msk (0x5U << AFIO_EXTICR1_EXTI3_PF_Pos) /*!< 0x00005000 */
+#define AFIO_EXTICR1_EXTI3_PF AFIO_EXTICR1_EXTI3_PF_Msk /*!< PF[3] pin */
+#define AFIO_EXTICR1_EXTI3_PG_Pos (13U)
+#define AFIO_EXTICR1_EXTI3_PG_Msk (0x3U << AFIO_EXTICR1_EXTI3_PG_Pos) /*!< 0x00006000 */
+#define AFIO_EXTICR1_EXTI3_PG AFIO_EXTICR1_EXTI3_PG_Msk /*!< PG[3] pin */
+
+/***************** Bit definition for AFIO_EXTICR2 register *****************/
+#define AFIO_EXTICR2_EXTI4_Pos (0U)
+#define AFIO_EXTICR2_EXTI4_Msk (0xFU << AFIO_EXTICR2_EXTI4_Pos) /*!< 0x0000000F */
+#define AFIO_EXTICR2_EXTI4 AFIO_EXTICR2_EXTI4_Msk /*!< EXTI 4 configuration */
+#define AFIO_EXTICR2_EXTI5_Pos (4U)
+#define AFIO_EXTICR2_EXTI5_Msk (0xFU << AFIO_EXTICR2_EXTI5_Pos) /*!< 0x000000F0 */
+#define AFIO_EXTICR2_EXTI5 AFIO_EXTICR2_EXTI5_Msk /*!< EXTI 5 configuration */
+#define AFIO_EXTICR2_EXTI6_Pos (8U)
+#define AFIO_EXTICR2_EXTI6_Msk (0xFU << AFIO_EXTICR2_EXTI6_Pos) /*!< 0x00000F00 */
+#define AFIO_EXTICR2_EXTI6 AFIO_EXTICR2_EXTI6_Msk /*!< EXTI 6 configuration */
+#define AFIO_EXTICR2_EXTI7_Pos (12U)
+#define AFIO_EXTICR2_EXTI7_Msk (0xFU << AFIO_EXTICR2_EXTI7_Pos) /*!< 0x0000F000 */
+#define AFIO_EXTICR2_EXTI7 AFIO_EXTICR2_EXTI7_Msk /*!< EXTI 7 configuration */
+
+/*!< EXTI4 configuration */
+#define AFIO_EXTICR2_EXTI4_PA ((uint32_t)0x00000000) /*!< PA[4] pin */
+#define AFIO_EXTICR2_EXTI4_PB_Pos (0U)
+#define AFIO_EXTICR2_EXTI4_PB_Msk (0x1U << AFIO_EXTICR2_EXTI4_PB_Pos) /*!< 0x00000001 */
+#define AFIO_EXTICR2_EXTI4_PB AFIO_EXTICR2_EXTI4_PB_Msk /*!< PB[4] pin */
+#define AFIO_EXTICR2_EXTI4_PC_Pos (1U)
+#define AFIO_EXTICR2_EXTI4_PC_Msk (0x1U << AFIO_EXTICR2_EXTI4_PC_Pos) /*!< 0x00000002 */
+#define AFIO_EXTICR2_EXTI4_PC AFIO_EXTICR2_EXTI4_PC_Msk /*!< PC[4] pin */
+#define AFIO_EXTICR2_EXTI4_PD_Pos (0U)
+#define AFIO_EXTICR2_EXTI4_PD_Msk (0x3U << AFIO_EXTICR2_EXTI4_PD_Pos) /*!< 0x00000003 */
+#define AFIO_EXTICR2_EXTI4_PD AFIO_EXTICR2_EXTI4_PD_Msk /*!< PD[4] pin */
+#define AFIO_EXTICR2_EXTI4_PE_Pos (2U)
+#define AFIO_EXTICR2_EXTI4_PE_Msk (0x1U << AFIO_EXTICR2_EXTI4_PE_Pos) /*!< 0x00000004 */
+#define AFIO_EXTICR2_EXTI4_PE AFIO_EXTICR2_EXTI4_PE_Msk /*!< PE[4] pin */
+#define AFIO_EXTICR2_EXTI4_PF_Pos (0U)
+#define AFIO_EXTICR2_EXTI4_PF_Msk (0x5U << AFIO_EXTICR2_EXTI4_PF_Pos) /*!< 0x00000005 */
+#define AFIO_EXTICR2_EXTI4_PF AFIO_EXTICR2_EXTI4_PF_Msk /*!< PF[4] pin */
+#define AFIO_EXTICR2_EXTI4_PG_Pos (1U)
+#define AFIO_EXTICR2_EXTI4_PG_Msk (0x3U << AFIO_EXTICR2_EXTI4_PG_Pos) /*!< 0x00000006 */
+#define AFIO_EXTICR2_EXTI4_PG AFIO_EXTICR2_EXTI4_PG_Msk /*!< PG[4] pin */
+
+/* EXTI5 configuration */
+#define AFIO_EXTICR2_EXTI5_PA ((uint32_t)0x00000000) /*!< PA[5] pin */
+#define AFIO_EXTICR2_EXTI5_PB_Pos (4U)
+#define AFIO_EXTICR2_EXTI5_PB_Msk (0x1U << AFIO_EXTICR2_EXTI5_PB_Pos) /*!< 0x00000010 */
+#define AFIO_EXTICR2_EXTI5_PB AFIO_EXTICR2_EXTI5_PB_Msk /*!< PB[5] pin */
+#define AFIO_EXTICR2_EXTI5_PC_Pos (5U)
+#define AFIO_EXTICR2_EXTI5_PC_Msk (0x1U << AFIO_EXTICR2_EXTI5_PC_Pos) /*!< 0x00000020 */
+#define AFIO_EXTICR2_EXTI5_PC AFIO_EXTICR2_EXTI5_PC_Msk /*!< PC[5] pin */
+#define AFIO_EXTICR2_EXTI5_PD_Pos (4U)
+#define AFIO_EXTICR2_EXTI5_PD_Msk (0x3U << AFIO_EXTICR2_EXTI5_PD_Pos) /*!< 0x00000030 */
+#define AFIO_EXTICR2_EXTI5_PD AFIO_EXTICR2_EXTI5_PD_Msk /*!< PD[5] pin */
+#define AFIO_EXTICR2_EXTI5_PE_Pos (6U)
+#define AFIO_EXTICR2_EXTI5_PE_Msk (0x1U << AFIO_EXTICR2_EXTI5_PE_Pos) /*!< 0x00000040 */
+#define AFIO_EXTICR2_EXTI5_PE AFIO_EXTICR2_EXTI5_PE_Msk /*!< PE[5] pin */
+#define AFIO_EXTICR2_EXTI5_PF_Pos (4U)
+#define AFIO_EXTICR2_EXTI5_PF_Msk (0x5U << AFIO_EXTICR2_EXTI5_PF_Pos) /*!< 0x00000050 */
+#define AFIO_EXTICR2_EXTI5_PF AFIO_EXTICR2_EXTI5_PF_Msk /*!< PF[5] pin */
+#define AFIO_EXTICR2_EXTI5_PG_Pos (5U)
+#define AFIO_EXTICR2_EXTI5_PG_Msk (0x3U << AFIO_EXTICR2_EXTI5_PG_Pos) /*!< 0x00000060 */
+#define AFIO_EXTICR2_EXTI5_PG AFIO_EXTICR2_EXTI5_PG_Msk /*!< PG[5] pin */
+
+/*!< EXTI6 configuration */
+#define AFIO_EXTICR2_EXTI6_PA ((uint32_t)0x00000000) /*!< PA[6] pin */
+#define AFIO_EXTICR2_EXTI6_PB_Pos (8U)
+#define AFIO_EXTICR2_EXTI6_PB_Msk (0x1U << AFIO_EXTICR2_EXTI6_PB_Pos) /*!< 0x00000100 */
+#define AFIO_EXTICR2_EXTI6_PB AFIO_EXTICR2_EXTI6_PB_Msk /*!< PB[6] pin */
+#define AFIO_EXTICR2_EXTI6_PC_Pos (9U)
+#define AFIO_EXTICR2_EXTI6_PC_Msk (0x1U << AFIO_EXTICR2_EXTI6_PC_Pos) /*!< 0x00000200 */
+#define AFIO_EXTICR2_EXTI6_PC AFIO_EXTICR2_EXTI6_PC_Msk /*!< PC[6] pin */
+#define AFIO_EXTICR2_EXTI6_PD_Pos (8U)
+#define AFIO_EXTICR2_EXTI6_PD_Msk (0x3U << AFIO_EXTICR2_EXTI6_PD_Pos) /*!< 0x00000300 */
+#define AFIO_EXTICR2_EXTI6_PD AFIO_EXTICR2_EXTI6_PD_Msk /*!< PD[6] pin */
+#define AFIO_EXTICR2_EXTI6_PE_Pos (10U)
+#define AFIO_EXTICR2_EXTI6_PE_Msk (0x1U << AFIO_EXTICR2_EXTI6_PE_Pos) /*!< 0x00000400 */
+#define AFIO_EXTICR2_EXTI6_PE AFIO_EXTICR2_EXTI6_PE_Msk /*!< PE[6] pin */
+#define AFIO_EXTICR2_EXTI6_PF_Pos (8U)
+#define AFIO_EXTICR2_EXTI6_PF_Msk (0x5U << AFIO_EXTICR2_EXTI6_PF_Pos) /*!< 0x00000500 */
+#define AFIO_EXTICR2_EXTI6_PF AFIO_EXTICR2_EXTI6_PF_Msk /*!< PF[6] pin */
+#define AFIO_EXTICR2_EXTI6_PG_Pos (9U)
+#define AFIO_EXTICR2_EXTI6_PG_Msk (0x3U << AFIO_EXTICR2_EXTI6_PG_Pos) /*!< 0x00000600 */
+#define AFIO_EXTICR2_EXTI6_PG AFIO_EXTICR2_EXTI6_PG_Msk /*!< PG[6] pin */
+
+/*!< EXTI7 configuration */
+#define AFIO_EXTICR2_EXTI7_PA ((uint32_t)0x00000000) /*!< PA[7] pin */
+#define AFIO_EXTICR2_EXTI7_PB_Pos (12U)
+#define AFIO_EXTICR2_EXTI7_PB_Msk (0x1U << AFIO_EXTICR2_EXTI7_PB_Pos) /*!< 0x00001000 */
+#define AFIO_EXTICR2_EXTI7_PB AFIO_EXTICR2_EXTI7_PB_Msk /*!< PB[7] pin */
+#define AFIO_EXTICR2_EXTI7_PC_Pos (13U)
+#define AFIO_EXTICR2_EXTI7_PC_Msk (0x1U << AFIO_EXTICR2_EXTI7_PC_Pos) /*!< 0x00002000 */
+#define AFIO_EXTICR2_EXTI7_PC AFIO_EXTICR2_EXTI7_PC_Msk /*!< PC[7] pin */
+#define AFIO_EXTICR2_EXTI7_PD_Pos (12U)
+#define AFIO_EXTICR2_EXTI7_PD_Msk (0x3U << AFIO_EXTICR2_EXTI7_PD_Pos) /*!< 0x00003000 */
+#define AFIO_EXTICR2_EXTI7_PD AFIO_EXTICR2_EXTI7_PD_Msk /*!< PD[7] pin */
+#define AFIO_EXTICR2_EXTI7_PE_Pos (14U)
+#define AFIO_EXTICR2_EXTI7_PE_Msk (0x1U << AFIO_EXTICR2_EXTI7_PE_Pos) /*!< 0x00004000 */
+#define AFIO_EXTICR2_EXTI7_PE AFIO_EXTICR2_EXTI7_PE_Msk /*!< PE[7] pin */
+#define AFIO_EXTICR2_EXTI7_PF_Pos (12U)
+#define AFIO_EXTICR2_EXTI7_PF_Msk (0x5U << AFIO_EXTICR2_EXTI7_PF_Pos) /*!< 0x00005000 */
+#define AFIO_EXTICR2_EXTI7_PF AFIO_EXTICR2_EXTI7_PF_Msk /*!< PF[7] pin */
+#define AFIO_EXTICR2_EXTI7_PG_Pos (13U)
+#define AFIO_EXTICR2_EXTI7_PG_Msk (0x3U << AFIO_EXTICR2_EXTI7_PG_Pos) /*!< 0x00006000 */
+#define AFIO_EXTICR2_EXTI7_PG AFIO_EXTICR2_EXTI7_PG_Msk /*!< PG[7] pin */
+
+/***************** Bit definition for AFIO_EXTICR3 register *****************/
+#define AFIO_EXTICR3_EXTI8_Pos (0U)
+#define AFIO_EXTICR3_EXTI8_Msk (0xFU << AFIO_EXTICR3_EXTI8_Pos) /*!< 0x0000000F */
+#define AFIO_EXTICR3_EXTI8 AFIO_EXTICR3_EXTI8_Msk /*!< EXTI 8 configuration */
+#define AFIO_EXTICR3_EXTI9_Pos (4U)
+#define AFIO_EXTICR3_EXTI9_Msk (0xFU << AFIO_EXTICR3_EXTI9_Pos) /*!< 0x000000F0 */
+#define AFIO_EXTICR3_EXTI9 AFIO_EXTICR3_EXTI9_Msk /*!< EXTI 9 configuration */
+#define AFIO_EXTICR3_EXTI10_Pos (8U)
+#define AFIO_EXTICR3_EXTI10_Msk (0xFU << AFIO_EXTICR3_EXTI10_Pos) /*!< 0x00000F00 */
+#define AFIO_EXTICR3_EXTI10 AFIO_EXTICR3_EXTI10_Msk /*!< EXTI 10 configuration */
+#define AFIO_EXTICR3_EXTI11_Pos (12U)
+#define AFIO_EXTICR3_EXTI11_Msk (0xFU << AFIO_EXTICR3_EXTI11_Pos) /*!< 0x0000F000 */
+#define AFIO_EXTICR3_EXTI11 AFIO_EXTICR3_EXTI11_Msk /*!< EXTI 11 configuration */
+
+/*!< EXTI8 configuration */
+#define AFIO_EXTICR3_EXTI8_PA ((uint32_t)0x00000000) /*!< PA[8] pin */
+#define AFIO_EXTICR3_EXTI8_PB_Pos (0U)
+#define AFIO_EXTICR3_EXTI8_PB_Msk (0x1U << AFIO_EXTICR3_EXTI8_PB_Pos) /*!< 0x00000001 */
+#define AFIO_EXTICR3_EXTI8_PB AFIO_EXTICR3_EXTI8_PB_Msk /*!< PB[8] pin */
+#define AFIO_EXTICR3_EXTI8_PC_Pos (1U)
+#define AFIO_EXTICR3_EXTI8_PC_Msk (0x1U << AFIO_EXTICR3_EXTI8_PC_Pos) /*!< 0x00000002 */
+#define AFIO_EXTICR3_EXTI8_PC AFIO_EXTICR3_EXTI8_PC_Msk /*!< PC[8] pin */
+#define AFIO_EXTICR3_EXTI8_PD_Pos (0U)
+#define AFIO_EXTICR3_EXTI8_PD_Msk (0x3U << AFIO_EXTICR3_EXTI8_PD_Pos) /*!< 0x00000003 */
+#define AFIO_EXTICR3_EXTI8_PD AFIO_EXTICR3_EXTI8_PD_Msk /*!< PD[8] pin */
+#define AFIO_EXTICR3_EXTI8_PE_Pos (2U)
+#define AFIO_EXTICR3_EXTI8_PE_Msk (0x1U << AFIO_EXTICR3_EXTI8_PE_Pos) /*!< 0x00000004 */
+#define AFIO_EXTICR3_EXTI8_PE AFIO_EXTICR3_EXTI8_PE_Msk /*!< PE[8] pin */
+#define AFIO_EXTICR3_EXTI8_PF_Pos (0U)
+#define AFIO_EXTICR3_EXTI8_PF_Msk (0x5U << AFIO_EXTICR3_EXTI8_PF_Pos) /*!< 0x00000005 */
+#define AFIO_EXTICR3_EXTI8_PF AFIO_EXTICR3_EXTI8_PF_Msk /*!< PF[8] pin */
+#define AFIO_EXTICR3_EXTI8_PG_Pos (1U)
+#define AFIO_EXTICR3_EXTI8_PG_Msk (0x3U << AFIO_EXTICR3_EXTI8_PG_Pos) /*!< 0x00000006 */
+#define AFIO_EXTICR3_EXTI8_PG AFIO_EXTICR3_EXTI8_PG_Msk /*!< PG[8] pin */
+
+/*!< EXTI9 configuration */
+#define AFIO_EXTICR3_EXTI9_PA ((uint32_t)0x00000000) /*!< PA[9] pin */
+#define AFIO_EXTICR3_EXTI9_PB_Pos (4U)
+#define AFIO_EXTICR3_EXTI9_PB_Msk (0x1U << AFIO_EXTICR3_EXTI9_PB_Pos) /*!< 0x00000010 */
+#define AFIO_EXTICR3_EXTI9_PB AFIO_EXTICR3_EXTI9_PB_Msk /*!< PB[9] pin */
+#define AFIO_EXTICR3_EXTI9_PC_Pos (5U)
+#define AFIO_EXTICR3_EXTI9_PC_Msk (0x1U << AFIO_EXTICR3_EXTI9_PC_Pos) /*!< 0x00000020 */
+#define AFIO_EXTICR3_EXTI9_PC AFIO_EXTICR3_EXTI9_PC_Msk /*!< PC[9] pin */
+#define AFIO_EXTICR3_EXTI9_PD_Pos (4U)
+#define AFIO_EXTICR3_EXTI9_PD_Msk (0x3U << AFIO_EXTICR3_EXTI9_PD_Pos) /*!< 0x00000030 */
+#define AFIO_EXTICR3_EXTI9_PD AFIO_EXTICR3_EXTI9_PD_Msk /*!< PD[9] pin */
+#define AFIO_EXTICR3_EXTI9_PE_Pos (6U)
+#define AFIO_EXTICR3_EXTI9_PE_Msk (0x1U << AFIO_EXTICR3_EXTI9_PE_Pos) /*!< 0x00000040 */
+#define AFIO_EXTICR3_EXTI9_PE AFIO_EXTICR3_EXTI9_PE_Msk /*!< PE[9] pin */
+#define AFIO_EXTICR3_EXTI9_PF_Pos (4U)
+#define AFIO_EXTICR3_EXTI9_PF_Msk (0x5U << AFIO_EXTICR3_EXTI9_PF_Pos) /*!< 0x00000050 */
+#define AFIO_EXTICR3_EXTI9_PF AFIO_EXTICR3_EXTI9_PF_Msk /*!< PF[9] pin */
+#define AFIO_EXTICR3_EXTI9_PG_Pos (5U)
+#define AFIO_EXTICR3_EXTI9_PG_Msk (0x3U << AFIO_EXTICR3_EXTI9_PG_Pos) /*!< 0x00000060 */
+#define AFIO_EXTICR3_EXTI9_PG AFIO_EXTICR3_EXTI9_PG_Msk /*!< PG[9] pin */
+
+/*!< EXTI10 configuration */
+#define AFIO_EXTICR3_EXTI10_PA ((uint32_t)0x00000000) /*!< PA[10] pin */
+#define AFIO_EXTICR3_EXTI10_PB_Pos (8U)
+#define AFIO_EXTICR3_EXTI10_PB_Msk (0x1U << AFIO_EXTICR3_EXTI10_PB_Pos) /*!< 0x00000100 */
+#define AFIO_EXTICR3_EXTI10_PB AFIO_EXTICR3_EXTI10_PB_Msk /*!< PB[10] pin */
+#define AFIO_EXTICR3_EXTI10_PC_Pos (9U)
+#define AFIO_EXTICR3_EXTI10_PC_Msk (0x1U << AFIO_EXTICR3_EXTI10_PC_Pos) /*!< 0x00000200 */
+#define AFIO_EXTICR3_EXTI10_PC AFIO_EXTICR3_EXTI10_PC_Msk /*!< PC[10] pin */
+#define AFIO_EXTICR3_EXTI10_PD_Pos (8U)
+#define AFIO_EXTICR3_EXTI10_PD_Msk (0x3U << AFIO_EXTICR3_EXTI10_PD_Pos) /*!< 0x00000300 */
+#define AFIO_EXTICR3_EXTI10_PD AFIO_EXTICR3_EXTI10_PD_Msk /*!< PD[10] pin */
+#define AFIO_EXTICR3_EXTI10_PE_Pos (10U)
+#define AFIO_EXTICR3_EXTI10_PE_Msk (0x1U << AFIO_EXTICR3_EXTI10_PE_Pos) /*!< 0x00000400 */
+#define AFIO_EXTICR3_EXTI10_PE AFIO_EXTICR3_EXTI10_PE_Msk /*!< PE[10] pin */
+#define AFIO_EXTICR3_EXTI10_PF_Pos (8U)
+#define AFIO_EXTICR3_EXTI10_PF_Msk (0x5U << AFIO_EXTICR3_EXTI10_PF_Pos) /*!< 0x00000500 */
+#define AFIO_EXTICR3_EXTI10_PF AFIO_EXTICR3_EXTI10_PF_Msk /*!< PF[10] pin */
+#define AFIO_EXTICR3_EXTI10_PG_Pos (9U)
+#define AFIO_EXTICR3_EXTI10_PG_Msk (0x3U << AFIO_EXTICR3_EXTI10_PG_Pos) /*!< 0x00000600 */
+#define AFIO_EXTICR3_EXTI10_PG AFIO_EXTICR3_EXTI10_PG_Msk /*!< PG[10] pin */
+
+/*!< EXTI11 configuration */
+#define AFIO_EXTICR3_EXTI11_PA ((uint32_t)0x00000000) /*!< PA[11] pin */
+#define AFIO_EXTICR3_EXTI11_PB_Pos (12U)
+#define AFIO_EXTICR3_EXTI11_PB_Msk (0x1U << AFIO_EXTICR3_EXTI11_PB_Pos) /*!< 0x00001000 */
+#define AFIO_EXTICR3_EXTI11_PB AFIO_EXTICR3_EXTI11_PB_Msk /*!< PB[11] pin */
+#define AFIO_EXTICR3_EXTI11_PC_Pos (13U)
+#define AFIO_EXTICR3_EXTI11_PC_Msk (0x1U << AFIO_EXTICR3_EXTI11_PC_Pos) /*!< 0x00002000 */
+#define AFIO_EXTICR3_EXTI11_PC AFIO_EXTICR3_EXTI11_PC_Msk /*!< PC[11] pin */
+#define AFIO_EXTICR3_EXTI11_PD_Pos (12U)
+#define AFIO_EXTICR3_EXTI11_PD_Msk (0x3U << AFIO_EXTICR3_EXTI11_PD_Pos) /*!< 0x00003000 */
+#define AFIO_EXTICR3_EXTI11_PD AFIO_EXTICR3_EXTI11_PD_Msk /*!< PD[11] pin */
+#define AFIO_EXTICR3_EXTI11_PE_Pos (14U)
+#define AFIO_EXTICR3_EXTI11_PE_Msk (0x1U << AFIO_EXTICR3_EXTI11_PE_Pos) /*!< 0x00004000 */
+#define AFIO_EXTICR3_EXTI11_PE AFIO_EXTICR3_EXTI11_PE_Msk /*!< PE[11] pin */
+#define AFIO_EXTICR3_EXTI11_PF_Pos (12U)
+#define AFIO_EXTICR3_EXTI11_PF_Msk (0x5U << AFIO_EXTICR3_EXTI11_PF_Pos) /*!< 0x00005000 */
+#define AFIO_EXTICR3_EXTI11_PF AFIO_EXTICR3_EXTI11_PF_Msk /*!< PF[11] pin */
+#define AFIO_EXTICR3_EXTI11_PG_Pos (13U)
+#define AFIO_EXTICR3_EXTI11_PG_Msk (0x3U << AFIO_EXTICR3_EXTI11_PG_Pos) /*!< 0x00006000 */
+#define AFIO_EXTICR3_EXTI11_PG AFIO_EXTICR3_EXTI11_PG_Msk /*!< PG[11] pin */
+
+/***************** Bit definition for AFIO_EXTICR4 register *****************/
+#define AFIO_EXTICR4_EXTI12_Pos (0U)
+#define AFIO_EXTICR4_EXTI12_Msk (0xFU << AFIO_EXTICR4_EXTI12_Pos) /*!< 0x0000000F */
+#define AFIO_EXTICR4_EXTI12 AFIO_EXTICR4_EXTI12_Msk /*!< EXTI 12 configuration */
+#define AFIO_EXTICR4_EXTI13_Pos (4U)
+#define AFIO_EXTICR4_EXTI13_Msk (0xFU << AFIO_EXTICR4_EXTI13_Pos) /*!< 0x000000F0 */
+#define AFIO_EXTICR4_EXTI13 AFIO_EXTICR4_EXTI13_Msk /*!< EXTI 13 configuration */
+#define AFIO_EXTICR4_EXTI14_Pos (8U)
+#define AFIO_EXTICR4_EXTI14_Msk (0xFU << AFIO_EXTICR4_EXTI14_Pos) /*!< 0x00000F00 */
+#define AFIO_EXTICR4_EXTI14 AFIO_EXTICR4_EXTI14_Msk /*!< EXTI 14 configuration */
+#define AFIO_EXTICR4_EXTI15_Pos (12U)
+#define AFIO_EXTICR4_EXTI15_Msk (0xFU << AFIO_EXTICR4_EXTI15_Pos) /*!< 0x0000F000 */
+#define AFIO_EXTICR4_EXTI15 AFIO_EXTICR4_EXTI15_Msk /*!< EXTI 15 configuration */
+
+/* EXTI12 configuration */
+#define AFIO_EXTICR4_EXTI12_PA ((uint32_t)0x00000000) /*!< PA[12] pin */
+#define AFIO_EXTICR4_EXTI12_PB_Pos (0U)
+#define AFIO_EXTICR4_EXTI12_PB_Msk (0x1U << AFIO_EXTICR4_EXTI12_PB_Pos) /*!< 0x00000001 */
+#define AFIO_EXTICR4_EXTI12_PB AFIO_EXTICR4_EXTI12_PB_Msk /*!< PB[12] pin */
+#define AFIO_EXTICR4_EXTI12_PC_Pos (1U)
+#define AFIO_EXTICR4_EXTI12_PC_Msk (0x1U << AFIO_EXTICR4_EXTI12_PC_Pos) /*!< 0x00000002 */
+#define AFIO_EXTICR4_EXTI12_PC AFIO_EXTICR4_EXTI12_PC_Msk /*!< PC[12] pin */
+#define AFIO_EXTICR4_EXTI12_PD_Pos (0U)
+#define AFIO_EXTICR4_EXTI12_PD_Msk (0x3U << AFIO_EXTICR4_EXTI12_PD_Pos) /*!< 0x00000003 */
+#define AFIO_EXTICR4_EXTI12_PD AFIO_EXTICR4_EXTI12_PD_Msk /*!< PD[12] pin */
+#define AFIO_EXTICR4_EXTI12_PE_Pos (2U)
+#define AFIO_EXTICR4_EXTI12_PE_Msk (0x1U << AFIO_EXTICR4_EXTI12_PE_Pos) /*!< 0x00000004 */
+#define AFIO_EXTICR4_EXTI12_PE AFIO_EXTICR4_EXTI12_PE_Msk /*!< PE[12] pin */
+#define AFIO_EXTICR4_EXTI12_PF_Pos (0U)
+#define AFIO_EXTICR4_EXTI12_PF_Msk (0x5U << AFIO_EXTICR4_EXTI12_PF_Pos) /*!< 0x00000005 */
+#define AFIO_EXTICR4_EXTI12_PF AFIO_EXTICR4_EXTI12_PF_Msk /*!< PF[12] pin */
+#define AFIO_EXTICR4_EXTI12_PG_Pos (1U)
+#define AFIO_EXTICR4_EXTI12_PG_Msk (0x3U << AFIO_EXTICR4_EXTI12_PG_Pos) /*!< 0x00000006 */
+#define AFIO_EXTICR4_EXTI12_PG AFIO_EXTICR4_EXTI12_PG_Msk /*!< PG[12] pin */
+
+/* EXTI13 configuration */
+#define AFIO_EXTICR4_EXTI13_PA ((uint32_t)0x00000000) /*!< PA[13] pin */
+#define AFIO_EXTICR4_EXTI13_PB_Pos (4U)
+#define AFIO_EXTICR4_EXTI13_PB_Msk (0x1U << AFIO_EXTICR4_EXTI13_PB_Pos) /*!< 0x00000010 */
+#define AFIO_EXTICR4_EXTI13_PB AFIO_EXTICR4_EXTI13_PB_Msk /*!< PB[13] pin */
+#define AFIO_EXTICR4_EXTI13_PC_Pos (5U)
+#define AFIO_EXTICR4_EXTI13_PC_Msk (0x1U << AFIO_EXTICR4_EXTI13_PC_Pos) /*!< 0x00000020 */
+#define AFIO_EXTICR4_EXTI13_PC AFIO_EXTICR4_EXTI13_PC_Msk /*!< PC[13] pin */
+#define AFIO_EXTICR4_EXTI13_PD_Pos (4U)
+#define AFIO_EXTICR4_EXTI13_PD_Msk (0x3U << AFIO_EXTICR4_EXTI13_PD_Pos) /*!< 0x00000030 */
+#define AFIO_EXTICR4_EXTI13_PD AFIO_EXTICR4_EXTI13_PD_Msk /*!< PD[13] pin */
+#define AFIO_EXTICR4_EXTI13_PE_Pos (6U)
+#define AFIO_EXTICR4_EXTI13_PE_Msk (0x1U << AFIO_EXTICR4_EXTI13_PE_Pos) /*!< 0x00000040 */
+#define AFIO_EXTICR4_EXTI13_PE AFIO_EXTICR4_EXTI13_PE_Msk /*!< PE[13] pin */
+#define AFIO_EXTICR4_EXTI13_PF_Pos (4U)
+#define AFIO_EXTICR4_EXTI13_PF_Msk (0x5U << AFIO_EXTICR4_EXTI13_PF_Pos) /*!< 0x00000050 */
+#define AFIO_EXTICR4_EXTI13_PF AFIO_EXTICR4_EXTI13_PF_Msk /*!< PF[13] pin */
+#define AFIO_EXTICR4_EXTI13_PG_Pos (5U)
+#define AFIO_EXTICR4_EXTI13_PG_Msk (0x3U << AFIO_EXTICR4_EXTI13_PG_Pos) /*!< 0x00000060 */
+#define AFIO_EXTICR4_EXTI13_PG AFIO_EXTICR4_EXTI13_PG_Msk /*!< PG[13] pin */
+
+/*!< EXTI14 configuration */
+#define AFIO_EXTICR4_EXTI14_PA ((uint32_t)0x00000000) /*!< PA[14] pin */
+#define AFIO_EXTICR4_EXTI14_PB_Pos (8U)
+#define AFIO_EXTICR4_EXTI14_PB_Msk (0x1U << AFIO_EXTICR4_EXTI14_PB_Pos) /*!< 0x00000100 */
+#define AFIO_EXTICR4_EXTI14_PB AFIO_EXTICR4_EXTI14_PB_Msk /*!< PB[14] pin */
+#define AFIO_EXTICR4_EXTI14_PC_Pos (9U)
+#define AFIO_EXTICR4_EXTI14_PC_Msk (0x1U << AFIO_EXTICR4_EXTI14_PC_Pos) /*!< 0x00000200 */
+#define AFIO_EXTICR4_EXTI14_PC AFIO_EXTICR4_EXTI14_PC_Msk /*!< PC[14] pin */
+#define AFIO_EXTICR4_EXTI14_PD_Pos (8U)
+#define AFIO_EXTICR4_EXTI14_PD_Msk (0x3U << AFIO_EXTICR4_EXTI14_PD_Pos) /*!< 0x00000300 */
+#define AFIO_EXTICR4_EXTI14_PD AFIO_EXTICR4_EXTI14_PD_Msk /*!< PD[14] pin */
+#define AFIO_EXTICR4_EXTI14_PE_Pos (10U)
+#define AFIO_EXTICR4_EXTI14_PE_Msk (0x1U << AFIO_EXTICR4_EXTI14_PE_Pos) /*!< 0x00000400 */
+#define AFIO_EXTICR4_EXTI14_PE AFIO_EXTICR4_EXTI14_PE_Msk /*!< PE[14] pin */
+#define AFIO_EXTICR4_EXTI14_PF_Pos (8U)
+#define AFIO_EXTICR4_EXTI14_PF_Msk (0x5U << AFIO_EXTICR4_EXTI14_PF_Pos) /*!< 0x00000500 */
+#define AFIO_EXTICR4_EXTI14_PF AFIO_EXTICR4_EXTI14_PF_Msk /*!< PF[14] pin */
+#define AFIO_EXTICR4_EXTI14_PG_Pos (9U)
+#define AFIO_EXTICR4_EXTI14_PG_Msk (0x3U << AFIO_EXTICR4_EXTI14_PG_Pos) /*!< 0x00000600 */
+#define AFIO_EXTICR4_EXTI14_PG AFIO_EXTICR4_EXTI14_PG_Msk /*!< PG[14] pin */
+
+/*!< EXTI15 configuration */
+#define AFIO_EXTICR4_EXTI15_PA ((uint32_t)0x00000000) /*!< PA[15] pin */
+#define AFIO_EXTICR4_EXTI15_PB_Pos (12U)
+#define AFIO_EXTICR4_EXTI15_PB_Msk (0x1U << AFIO_EXTICR4_EXTI15_PB_Pos) /*!< 0x00001000 */
+#define AFIO_EXTICR4_EXTI15_PB AFIO_EXTICR4_EXTI15_PB_Msk /*!< PB[15] pin */
+#define AFIO_EXTICR4_EXTI15_PC_Pos (13U)
+#define AFIO_EXTICR4_EXTI15_PC_Msk (0x1U << AFIO_EXTICR4_EXTI15_PC_Pos) /*!< 0x00002000 */
+#define AFIO_EXTICR4_EXTI15_PC AFIO_EXTICR4_EXTI15_PC_Msk /*!< PC[15] pin */
+#define AFIO_EXTICR4_EXTI15_PD_Pos (12U)
+#define AFIO_EXTICR4_EXTI15_PD_Msk (0x3U << AFIO_EXTICR4_EXTI15_PD_Pos) /*!< 0x00003000 */
+#define AFIO_EXTICR4_EXTI15_PD AFIO_EXTICR4_EXTI15_PD_Msk /*!< PD[15] pin */
+#define AFIO_EXTICR4_EXTI15_PE_Pos (14U)
+#define AFIO_EXTICR4_EXTI15_PE_Msk (0x1U << AFIO_EXTICR4_EXTI15_PE_Pos) /*!< 0x00004000 */
+#define AFIO_EXTICR4_EXTI15_PE AFIO_EXTICR4_EXTI15_PE_Msk /*!< PE[15] pin */
+#define AFIO_EXTICR4_EXTI15_PF_Pos (12U)
+#define AFIO_EXTICR4_EXTI15_PF_Msk (0x5U << AFIO_EXTICR4_EXTI15_PF_Pos) /*!< 0x00005000 */
+#define AFIO_EXTICR4_EXTI15_PF AFIO_EXTICR4_EXTI15_PF_Msk /*!< PF[15] pin */
+#define AFIO_EXTICR4_EXTI15_PG_Pos (13U)
+#define AFIO_EXTICR4_EXTI15_PG_Msk (0x3U << AFIO_EXTICR4_EXTI15_PG_Pos) /*!< 0x00006000 */
+#define AFIO_EXTICR4_EXTI15_PG AFIO_EXTICR4_EXTI15_PG_Msk /*!< PG[15] pin */
+
+/****************** Bit definition for AFIO_MAPR2 register ******************/
+
+
+#define AFIO_MAPR2_FSMC_NADV_REMAP_Pos (10U)
+#define AFIO_MAPR2_FSMC_NADV_REMAP_Msk (0x1U << AFIO_MAPR2_FSMC_NADV_REMAP_Pos) /*!< 0x00000400 */
+#define AFIO_MAPR2_FSMC_NADV_REMAP AFIO_MAPR2_FSMC_NADV_REMAP_Msk /*!< FSMC NADV remapping */
+
+/******************************************************************************/
+/* */
+/* SystemTick */
+/* */
+/******************************************************************************/
+
+/***************** Bit definition for SysTick_CTRL register *****************/
+#define SysTick_CTRL_ENABLE ((uint32_t)0x00000001) /*!< Counter enable */
+#define SysTick_CTRL_TICKINT ((uint32_t)0x00000002) /*!< Counting down to 0 pends the SysTick handler */
+#define SysTick_CTRL_CLKSOURCE ((uint32_t)0x00000004) /*!< Clock source */
+#define SysTick_CTRL_COUNTFLAG ((uint32_t)0x00010000) /*!< Count Flag */
+
+/***************** Bit definition for SysTick_LOAD register *****************/
+#define SysTick_LOAD_RELOAD ((uint32_t)0x00FFFFFF) /*!< Value to load into the SysTick Current Value Register when the counter reaches 0 */
+
+/***************** Bit definition for SysTick_VAL register ******************/
+#define SysTick_VAL_CURRENT ((uint32_t)0x00FFFFFF) /*!< Current value at the time the register is accessed */
+
+/***************** Bit definition for SysTick_CALIB register ****************/
+#define SysTick_CALIB_TENMS ((uint32_t)0x00FFFFFF) /*!< Reload value to use for 10ms timing */
+#define SysTick_CALIB_SKEW ((uint32_t)0x40000000) /*!< Calibration value is not exactly 10 ms */
+#define SysTick_CALIB_NOREF ((uint32_t)0x80000000) /*!< The reference clock is not provided */
+
+/******************************************************************************/
+/* */
+/* Nested Vectored Interrupt Controller */
+/* */
+/******************************************************************************/
+
+/****************** Bit definition for NVIC_ISER register *******************/
+#define NVIC_ISER_SETENA_Pos (0U)
+#define NVIC_ISER_SETENA_Msk (0xFFFFFFFFU << NVIC_ISER_SETENA_Pos) /*!< 0xFFFFFFFF */
+#define NVIC_ISER_SETENA NVIC_ISER_SETENA_Msk /*!< Interrupt set enable bits */
+#define NVIC_ISER_SETENA_0 (0x00000001U << NVIC_ISER_SETENA_Pos) /*!< 0x00000001 */
+#define NVIC_ISER_SETENA_1 (0x00000002U << NVIC_ISER_SETENA_Pos) /*!< 0x00000002 */
+#define NVIC_ISER_SETENA_2 (0x00000004U << NVIC_ISER_SETENA_Pos) /*!< 0x00000004 */
+#define NVIC_ISER_SETENA_3 (0x00000008U << NVIC_ISER_SETENA_Pos) /*!< 0x00000008 */
+#define NVIC_ISER_SETENA_4 (0x00000010U << NVIC_ISER_SETENA_Pos) /*!< 0x00000010 */
+#define NVIC_ISER_SETENA_5 (0x00000020U << NVIC_ISER_SETENA_Pos) /*!< 0x00000020 */
+#define NVIC_ISER_SETENA_6 (0x00000040U << NVIC_ISER_SETENA_Pos) /*!< 0x00000040 */
+#define NVIC_ISER_SETENA_7 (0x00000080U << NVIC_ISER_SETENA_Pos) /*!< 0x00000080 */
+#define NVIC_ISER_SETENA_8 (0x00000100U << NVIC_ISER_SETENA_Pos) /*!< 0x00000100 */
+#define NVIC_ISER_SETENA_9 (0x00000200U << NVIC_ISER_SETENA_Pos) /*!< 0x00000200 */
+#define NVIC_ISER_SETENA_10 (0x00000400U << NVIC_ISER_SETENA_Pos) /*!< 0x00000400 */
+#define NVIC_ISER_SETENA_11 (0x00000800U << NVIC_ISER_SETENA_Pos) /*!< 0x00000800 */
+#define NVIC_ISER_SETENA_12 (0x00001000U << NVIC_ISER_SETENA_Pos) /*!< 0x00001000 */
+#define NVIC_ISER_SETENA_13 (0x00002000U << NVIC_ISER_SETENA_Pos) /*!< 0x00002000 */
+#define NVIC_ISER_SETENA_14 (0x00004000U << NVIC_ISER_SETENA_Pos) /*!< 0x00004000 */
+#define NVIC_ISER_SETENA_15 (0x00008000U << NVIC_ISER_SETENA_Pos) /*!< 0x00008000 */
+#define NVIC_ISER_SETENA_16 (0x00010000U << NVIC_ISER_SETENA_Pos) /*!< 0x00010000 */
+#define NVIC_ISER_SETENA_17 (0x00020000U << NVIC_ISER_SETENA_Pos) /*!< 0x00020000 */
+#define NVIC_ISER_SETENA_18 (0x00040000U << NVIC_ISER_SETENA_Pos) /*!< 0x00040000 */
+#define NVIC_ISER_SETENA_19 (0x00080000U << NVIC_ISER_SETENA_Pos) /*!< 0x00080000 */
+#define NVIC_ISER_SETENA_20 (0x00100000U << NVIC_ISER_SETENA_Pos) /*!< 0x00100000 */
+#define NVIC_ISER_SETENA_21 (0x00200000U << NVIC_ISER_SETENA_Pos) /*!< 0x00200000 */
+#define NVIC_ISER_SETENA_22 (0x00400000U << NVIC_ISER_SETENA_Pos) /*!< 0x00400000 */
+#define NVIC_ISER_SETENA_23 (0x00800000U << NVIC_ISER_SETENA_Pos) /*!< 0x00800000 */
+#define NVIC_ISER_SETENA_24 (0x01000000U << NVIC_ISER_SETENA_Pos) /*!< 0x01000000 */
+#define NVIC_ISER_SETENA_25 (0x02000000U << NVIC_ISER_SETENA_Pos) /*!< 0x02000000 */
+#define NVIC_ISER_SETENA_26 (0x04000000U << NVIC_ISER_SETENA_Pos) /*!< 0x04000000 */
+#define NVIC_ISER_SETENA_27 (0x08000000U << NVIC_ISER_SETENA_Pos) /*!< 0x08000000 */
+#define NVIC_ISER_SETENA_28 (0x10000000U << NVIC_ISER_SETENA_Pos) /*!< 0x10000000 */
+#define NVIC_ISER_SETENA_29 (0x20000000U << NVIC_ISER_SETENA_Pos) /*!< 0x20000000 */
+#define NVIC_ISER_SETENA_30 (0x40000000U << NVIC_ISER_SETENA_Pos) /*!< 0x40000000 */
+#define NVIC_ISER_SETENA_31 (0x80000000U << NVIC_ISER_SETENA_Pos) /*!< 0x80000000 */
+
+/****************** Bit definition for NVIC_ICER register *******************/
+#define NVIC_ICER_CLRENA_Pos (0U)
+#define NVIC_ICER_CLRENA_Msk (0xFFFFFFFFU << NVIC_ICER_CLRENA_Pos) /*!< 0xFFFFFFFF */
+#define NVIC_ICER_CLRENA NVIC_ICER_CLRENA_Msk /*!< Interrupt clear-enable bits */
+#define NVIC_ICER_CLRENA_0 (0x00000001U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000001 */
+#define NVIC_ICER_CLRENA_1 (0x00000002U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000002 */
+#define NVIC_ICER_CLRENA_2 (0x00000004U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000004 */
+#define NVIC_ICER_CLRENA_3 (0x00000008U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000008 */
+#define NVIC_ICER_CLRENA_4 (0x00000010U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000010 */
+#define NVIC_ICER_CLRENA_5 (0x00000020U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000020 */
+#define NVIC_ICER_CLRENA_6 (0x00000040U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000040 */
+#define NVIC_ICER_CLRENA_7 (0x00000080U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000080 */
+#define NVIC_ICER_CLRENA_8 (0x00000100U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000100 */
+#define NVIC_ICER_CLRENA_9 (0x00000200U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000200 */
+#define NVIC_ICER_CLRENA_10 (0x00000400U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000400 */
+#define NVIC_ICER_CLRENA_11 (0x00000800U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000800 */
+#define NVIC_ICER_CLRENA_12 (0x00001000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00001000 */
+#define NVIC_ICER_CLRENA_13 (0x00002000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00002000 */
+#define NVIC_ICER_CLRENA_14 (0x00004000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00004000 */
+#define NVIC_ICER_CLRENA_15 (0x00008000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00008000 */
+#define NVIC_ICER_CLRENA_16 (0x00010000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00010000 */
+#define NVIC_ICER_CLRENA_17 (0x00020000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00020000 */
+#define NVIC_ICER_CLRENA_18 (0x00040000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00040000 */
+#define NVIC_ICER_CLRENA_19 (0x00080000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00080000 */
+#define NVIC_ICER_CLRENA_20 (0x00100000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00100000 */
+#define NVIC_ICER_CLRENA_21 (0x00200000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00200000 */
+#define NVIC_ICER_CLRENA_22 (0x00400000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00400000 */
+#define NVIC_ICER_CLRENA_23 (0x00800000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00800000 */
+#define NVIC_ICER_CLRENA_24 (0x01000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x01000000 */
+#define NVIC_ICER_CLRENA_25 (0x02000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x02000000 */
+#define NVIC_ICER_CLRENA_26 (0x04000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x04000000 */
+#define NVIC_ICER_CLRENA_27 (0x08000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x08000000 */
+#define NVIC_ICER_CLRENA_28 (0x10000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x10000000 */
+#define NVIC_ICER_CLRENA_29 (0x20000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x20000000 */
+#define NVIC_ICER_CLRENA_30 (0x40000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x40000000 */
+#define NVIC_ICER_CLRENA_31 (0x80000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x80000000 */
+
+/****************** Bit definition for NVIC_ISPR register *******************/
+#define NVIC_ISPR_SETPEND_Pos (0U)
+#define NVIC_ISPR_SETPEND_Msk (0xFFFFFFFFU << NVIC_ISPR_SETPEND_Pos) /*!< 0xFFFFFFFF */
+#define NVIC_ISPR_SETPEND NVIC_ISPR_SETPEND_Msk /*!< Interrupt set-pending bits */
+#define NVIC_ISPR_SETPEND_0 (0x00000001U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000001 */
+#define NVIC_ISPR_SETPEND_1 (0x00000002U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000002 */
+#define NVIC_ISPR_SETPEND_2 (0x00000004U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000004 */
+#define NVIC_ISPR_SETPEND_3 (0x00000008U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000008 */
+#define NVIC_ISPR_SETPEND_4 (0x00000010U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000010 */
+#define NVIC_ISPR_SETPEND_5 (0x00000020U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000020 */
+#define NVIC_ISPR_SETPEND_6 (0x00000040U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000040 */
+#define NVIC_ISPR_SETPEND_7 (0x00000080U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000080 */
+#define NVIC_ISPR_SETPEND_8 (0x00000100U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000100 */
+#define NVIC_ISPR_SETPEND_9 (0x00000200U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000200 */
+#define NVIC_ISPR_SETPEND_10 (0x00000400U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000400 */
+#define NVIC_ISPR_SETPEND_11 (0x00000800U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000800 */
+#define NVIC_ISPR_SETPEND_12 (0x00001000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00001000 */
+#define NVIC_ISPR_SETPEND_13 (0x00002000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00002000 */
+#define NVIC_ISPR_SETPEND_14 (0x00004000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00004000 */
+#define NVIC_ISPR_SETPEND_15 (0x00008000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00008000 */
+#define NVIC_ISPR_SETPEND_16 (0x00010000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00010000 */
+#define NVIC_ISPR_SETPEND_17 (0x00020000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00020000 */
+#define NVIC_ISPR_SETPEND_18 (0x00040000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00040000 */
+#define NVIC_ISPR_SETPEND_19 (0x00080000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00080000 */
+#define NVIC_ISPR_SETPEND_20 (0x00100000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00100000 */
+#define NVIC_ISPR_SETPEND_21 (0x00200000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00200000 */
+#define NVIC_ISPR_SETPEND_22 (0x00400000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00400000 */
+#define NVIC_ISPR_SETPEND_23 (0x00800000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00800000 */
+#define NVIC_ISPR_SETPEND_24 (0x01000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x01000000 */
+#define NVIC_ISPR_SETPEND_25 (0x02000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x02000000 */
+#define NVIC_ISPR_SETPEND_26 (0x04000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x04000000 */
+#define NVIC_ISPR_SETPEND_27 (0x08000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x08000000 */
+#define NVIC_ISPR_SETPEND_28 (0x10000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x10000000 */
+#define NVIC_ISPR_SETPEND_29 (0x20000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x20000000 */
+#define NVIC_ISPR_SETPEND_30 (0x40000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x40000000 */
+#define NVIC_ISPR_SETPEND_31 (0x80000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x80000000 */
+
+/****************** Bit definition for NVIC_ICPR register *******************/
+#define NVIC_ICPR_CLRPEND_Pos (0U)
+#define NVIC_ICPR_CLRPEND_Msk (0xFFFFFFFFU << NVIC_ICPR_CLRPEND_Pos) /*!< 0xFFFFFFFF */
+#define NVIC_ICPR_CLRPEND NVIC_ICPR_CLRPEND_Msk /*!< Interrupt clear-pending bits */
+#define NVIC_ICPR_CLRPEND_0 (0x00000001U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000001 */
+#define NVIC_ICPR_CLRPEND_1 (0x00000002U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000002 */
+#define NVIC_ICPR_CLRPEND_2 (0x00000004U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000004 */
+#define NVIC_ICPR_CLRPEND_3 (0x00000008U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000008 */
+#define NVIC_ICPR_CLRPEND_4 (0x00000010U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000010 */
+#define NVIC_ICPR_CLRPEND_5 (0x00000020U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000020 */
+#define NVIC_ICPR_CLRPEND_6 (0x00000040U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000040 */
+#define NVIC_ICPR_CLRPEND_7 (0x00000080U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000080 */
+#define NVIC_ICPR_CLRPEND_8 (0x00000100U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000100 */
+#define NVIC_ICPR_CLRPEND_9 (0x00000200U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000200 */
+#define NVIC_ICPR_CLRPEND_10 (0x00000400U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000400 */
+#define NVIC_ICPR_CLRPEND_11 (0x00000800U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000800 */
+#define NVIC_ICPR_CLRPEND_12 (0x00001000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00001000 */
+#define NVIC_ICPR_CLRPEND_13 (0x00002000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00002000 */
+#define NVIC_ICPR_CLRPEND_14 (0x00004000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00004000 */
+#define NVIC_ICPR_CLRPEND_15 (0x00008000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00008000 */
+#define NVIC_ICPR_CLRPEND_16 (0x00010000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00010000 */
+#define NVIC_ICPR_CLRPEND_17 (0x00020000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00020000 */
+#define NVIC_ICPR_CLRPEND_18 (0x00040000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00040000 */
+#define NVIC_ICPR_CLRPEND_19 (0x00080000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00080000 */
+#define NVIC_ICPR_CLRPEND_20 (0x00100000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00100000 */
+#define NVIC_ICPR_CLRPEND_21 (0x00200000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00200000 */
+#define NVIC_ICPR_CLRPEND_22 (0x00400000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00400000 */
+#define NVIC_ICPR_CLRPEND_23 (0x00800000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00800000 */
+#define NVIC_ICPR_CLRPEND_24 (0x01000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x01000000 */
+#define NVIC_ICPR_CLRPEND_25 (0x02000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x02000000 */
+#define NVIC_ICPR_CLRPEND_26 (0x04000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x04000000 */
+#define NVIC_ICPR_CLRPEND_27 (0x08000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x08000000 */
+#define NVIC_ICPR_CLRPEND_28 (0x10000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x10000000 */
+#define NVIC_ICPR_CLRPEND_29 (0x20000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x20000000 */
+#define NVIC_ICPR_CLRPEND_30 (0x40000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x40000000 */
+#define NVIC_ICPR_CLRPEND_31 (0x80000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x80000000 */
+
+/****************** Bit definition for NVIC_IABR register *******************/
+#define NVIC_IABR_ACTIVE_Pos (0U)
+#define NVIC_IABR_ACTIVE_Msk (0xFFFFFFFFU << NVIC_IABR_ACTIVE_Pos) /*!< 0xFFFFFFFF */
+#define NVIC_IABR_ACTIVE NVIC_IABR_ACTIVE_Msk /*!< Interrupt active flags */
+#define NVIC_IABR_ACTIVE_0 (0x00000001U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000001 */
+#define NVIC_IABR_ACTIVE_1 (0x00000002U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000002 */
+#define NVIC_IABR_ACTIVE_2 (0x00000004U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000004 */
+#define NVIC_IABR_ACTIVE_3 (0x00000008U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000008 */
+#define NVIC_IABR_ACTIVE_4 (0x00000010U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000010 */
+#define NVIC_IABR_ACTIVE_5 (0x00000020U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000020 */
+#define NVIC_IABR_ACTIVE_6 (0x00000040U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000040 */
+#define NVIC_IABR_ACTIVE_7 (0x00000080U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000080 */
+#define NVIC_IABR_ACTIVE_8 (0x00000100U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000100 */
+#define NVIC_IABR_ACTIVE_9 (0x00000200U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000200 */
+#define NVIC_IABR_ACTIVE_10 (0x00000400U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000400 */
+#define NVIC_IABR_ACTIVE_11 (0x00000800U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000800 */
+#define NVIC_IABR_ACTIVE_12 (0x00001000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00001000 */
+#define NVIC_IABR_ACTIVE_13 (0x00002000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00002000 */
+#define NVIC_IABR_ACTIVE_14 (0x00004000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00004000 */
+#define NVIC_IABR_ACTIVE_15 (0x00008000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00008000 */
+#define NVIC_IABR_ACTIVE_16 (0x00010000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00010000 */
+#define NVIC_IABR_ACTIVE_17 (0x00020000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00020000 */
+#define NVIC_IABR_ACTIVE_18 (0x00040000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00040000 */
+#define NVIC_IABR_ACTIVE_19 (0x00080000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00080000 */
+#define NVIC_IABR_ACTIVE_20 (0x00100000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00100000 */
+#define NVIC_IABR_ACTIVE_21 (0x00200000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00200000 */
+#define NVIC_IABR_ACTIVE_22 (0x00400000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00400000 */
+#define NVIC_IABR_ACTIVE_23 (0x00800000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00800000 */
+#define NVIC_IABR_ACTIVE_24 (0x01000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x01000000 */
+#define NVIC_IABR_ACTIVE_25 (0x02000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x02000000 */
+#define NVIC_IABR_ACTIVE_26 (0x04000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x04000000 */
+#define NVIC_IABR_ACTIVE_27 (0x08000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x08000000 */
+#define NVIC_IABR_ACTIVE_28 (0x10000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x10000000 */
+#define NVIC_IABR_ACTIVE_29 (0x20000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x20000000 */
+#define NVIC_IABR_ACTIVE_30 (0x40000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x40000000 */
+#define NVIC_IABR_ACTIVE_31 (0x80000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x80000000 */
+
+/****************** Bit definition for NVIC_PRI0 register *******************/
+#define NVIC_IPR0_PRI_0 ((uint32_t)0x000000FF) /*!< Priority of interrupt 0 */
+#define NVIC_IPR0_PRI_1 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 1 */
+#define NVIC_IPR0_PRI_2 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 2 */
+#define NVIC_IPR0_PRI_3 ((uint32_t)0xFF000000) /*!< Priority of interrupt 3 */
+
+/****************** Bit definition for NVIC_PRI1 register *******************/
+#define NVIC_IPR1_PRI_4 ((uint32_t)0x000000FF) /*!< Priority of interrupt 4 */
+#define NVIC_IPR1_PRI_5 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 5 */
+#define NVIC_IPR1_PRI_6 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 6 */
+#define NVIC_IPR1_PRI_7 ((uint32_t)0xFF000000) /*!< Priority of interrupt 7 */
+
+/****************** Bit definition for NVIC_PRI2 register *******************/
+#define NVIC_IPR2_PRI_8 ((uint32_t)0x000000FF) /*!< Priority of interrupt 8 */
+#define NVIC_IPR2_PRI_9 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 9 */
+#define NVIC_IPR2_PRI_10 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 10 */
+#define NVIC_IPR2_PRI_11 ((uint32_t)0xFF000000) /*!< Priority of interrupt 11 */
+
+/****************** Bit definition for NVIC_PRI3 register *******************/
+#define NVIC_IPR3_PRI_12 ((uint32_t)0x000000FF) /*!< Priority of interrupt 12 */
+#define NVIC_IPR3_PRI_13 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 13 */
+#define NVIC_IPR3_PRI_14 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 14 */
+#define NVIC_IPR3_PRI_15 ((uint32_t)0xFF000000) /*!< Priority of interrupt 15 */
+
+/****************** Bit definition for NVIC_PRI4 register *******************/
+#define NVIC_IPR4_PRI_16 ((uint32_t)0x000000FF) /*!< Priority of interrupt 16 */
+#define NVIC_IPR4_PRI_17 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 17 */
+#define NVIC_IPR4_PRI_18 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 18 */
+#define NVIC_IPR4_PRI_19 ((uint32_t)0xFF000000) /*!< Priority of interrupt 19 */
+
+/****************** Bit definition for NVIC_PRI5 register *******************/
+#define NVIC_IPR5_PRI_20 ((uint32_t)0x000000FF) /*!< Priority of interrupt 20 */
+#define NVIC_IPR5_PRI_21 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 21 */
+#define NVIC_IPR5_PRI_22 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 22 */
+#define NVIC_IPR5_PRI_23 ((uint32_t)0xFF000000) /*!< Priority of interrupt 23 */
+
+/****************** Bit definition for NVIC_PRI6 register *******************/
+#define NVIC_IPR6_PRI_24 ((uint32_t)0x000000FF) /*!< Priority of interrupt 24 */
+#define NVIC_IPR6_PRI_25 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 25 */
+#define NVIC_IPR6_PRI_26 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 26 */
+#define NVIC_IPR6_PRI_27 ((uint32_t)0xFF000000) /*!< Priority of interrupt 27 */
+
+/****************** Bit definition for NVIC_PRI7 register *******************/
+#define NVIC_IPR7_PRI_28 ((uint32_t)0x000000FF) /*!< Priority of interrupt 28 */
+#define NVIC_IPR7_PRI_29 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 29 */
+#define NVIC_IPR7_PRI_30 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 30 */
+#define NVIC_IPR7_PRI_31 ((uint32_t)0xFF000000) /*!< Priority of interrupt 31 */
+
+/****************** Bit definition for SCB_CPUID register *******************/
+#define SCB_CPUID_REVISION ((uint32_t)0x0000000F) /*!< Implementation defined revision number */
+#define SCB_CPUID_PARTNO ((uint32_t)0x0000FFF0) /*!< Number of processor within family */
+#define SCB_CPUID_Constant ((uint32_t)0x000F0000) /*!< Reads as 0x0F */
+#define SCB_CPUID_VARIANT ((uint32_t)0x00F00000) /*!< Implementation defined variant number */
+#define SCB_CPUID_IMPLEMENTER ((uint32_t)0xFF000000) /*!< Implementer code. ARM is 0x41 */
+
+/******************* Bit definition for SCB_ICSR register *******************/
+#define SCB_ICSR_VECTACTIVE ((uint32_t)0x000001FF) /*!< Active ISR number field */
+#define SCB_ICSR_RETTOBASE ((uint32_t)0x00000800) /*!< All active exceptions minus the IPSR_current_exception yields the empty set */
+#define SCB_ICSR_VECTPENDING ((uint32_t)0x003FF000) /*!< Pending ISR number field */
+#define SCB_ICSR_ISRPENDING ((uint32_t)0x00400000) /*!< Interrupt pending flag */
+#define SCB_ICSR_ISRPREEMPT ((uint32_t)0x00800000) /*!< It indicates that a pending interrupt becomes active in the next running cycle */
+#define SCB_ICSR_PENDSTCLR ((uint32_t)0x02000000) /*!< Clear pending SysTick bit */
+#define SCB_ICSR_PENDSTSET ((uint32_t)0x04000000) /*!< Set pending SysTick bit */
+#define SCB_ICSR_PENDSVCLR ((uint32_t)0x08000000) /*!< Clear pending pendSV bit */
+#define SCB_ICSR_PENDSVSET ((uint32_t)0x10000000) /*!< Set pending pendSV bit */
+#define SCB_ICSR_NMIPENDSET ((uint32_t)0x80000000) /*!< Set pending NMI bit */
+
+/******************* Bit definition for SCB_VTOR register *******************/
+#define SCB_VTOR_TBLOFF ((uint32_t)0x1FFFFF80) /*!< Vector table base offset field */
+#define SCB_VTOR_TBLBASE ((uint32_t)0x20000000) /*!< Table base in code(0) or RAM(1) */
+
+/*!<***************** Bit definition for SCB_AIRCR register *******************/
+#define SCB_AIRCR_VECTRESET ((uint32_t)0x00000001) /*!< System Reset bit */
+#define SCB_AIRCR_VECTCLRACTIVE ((uint32_t)0x00000002) /*!< Clear active vector bit */
+#define SCB_AIRCR_SYSRESETREQ ((uint32_t)0x00000004) /*!< Requests chip control logic to generate a reset */
+
+#define SCB_AIRCR_PRIGROUP ((uint32_t)0x00000700) /*!< PRIGROUP[2:0] bits (Priority group) */
+#define SCB_AIRCR_PRIGROUP_0 ((uint32_t)0x00000100) /*!< Bit 0 */
+#define SCB_AIRCR_PRIGROUP_1 ((uint32_t)0x00000200) /*!< Bit 1 */
+#define SCB_AIRCR_PRIGROUP_2 ((uint32_t)0x00000400) /*!< Bit 2 */
+
+/* prority group configuration */
+#define SCB_AIRCR_PRIGROUP0 ((uint32_t)0x00000000) /*!< Priority group=0 (7 bits of pre-emption priority, 1 bit of subpriority) */
+#define SCB_AIRCR_PRIGROUP1 ((uint32_t)0x00000100) /*!< Priority group=1 (6 bits of pre-emption priority, 2 bits of subpriority) */
+#define SCB_AIRCR_PRIGROUP2 ((uint32_t)0x00000200) /*!< Priority group=2 (5 bits of pre-emption priority, 3 bits of subpriority) */
+#define SCB_AIRCR_PRIGROUP3 ((uint32_t)0x00000300) /*!< Priority group=3 (4 bits of pre-emption priority, 4 bits of subpriority) */
+#define SCB_AIRCR_PRIGROUP4 ((uint32_t)0x00000400) /*!< Priority group=4 (3 bits of pre-emption priority, 5 bits of subpriority) */
+#define SCB_AIRCR_PRIGROUP5 ((uint32_t)0x00000500) /*!< Priority group=5 (2 bits of pre-emption priority, 6 bits of subpriority) */
+#define SCB_AIRCR_PRIGROUP6 ((uint32_t)0x00000600) /*!< Priority group=6 (1 bit of pre-emption priority, 7 bits of subpriority) */
+#define SCB_AIRCR_PRIGROUP7 ((uint32_t)0x00000700) /*!< Priority group=7 (no pre-emption priority, 8 bits of subpriority) */
+
+#define SCB_AIRCR_ENDIANESS ((uint32_t)0x00008000) /*!< Data endianness bit */
+#define SCB_AIRCR_VECTKEY ((uint32_t)0xFFFF0000) /*!< Register key (VECTKEY) - Reads as 0xFA05 (VECTKEYSTAT) */
+
+/******************* Bit definition for SCB_SCR register ********************/
+#define SCB_SCR_SLEEPONEXIT ((uint32_t)0x00000002) /*!< Sleep on exit bit */
+#define SCB_SCR_SLEEPDEEP ((uint32_t)0x00000004) /*!< Sleep deep bit */
+#define SCB_SCR_SEVONPEND ((uint32_t)0x00000010) /*!< Wake up from WFE */
+
+/******************** Bit definition for SCB_CCR register *******************/
+#define SCB_CCR_NONBASETHRDENA ((uint32_t)0x00000001) /*!< Thread mode can be entered from any level in Handler mode by controlled return value */
+#define SCB_CCR_USERSETMPEND ((uint32_t)0x00000002) /*!< Enables user code to write the Software Trigger Interrupt register to trigger (pend) a Main exception */
+#define SCB_CCR_UNALIGN_TRP ((uint32_t)0x00000008) /*!< Trap for unaligned access */
+#define SCB_CCR_DIV_0_TRP ((uint32_t)0x00000010) /*!< Trap on Divide by 0 */
+#define SCB_CCR_BFHFNMIGN ((uint32_t)0x00000100) /*!< Handlers running at priority -1 and -2 */
+#define SCB_CCR_STKALIGN ((uint32_t)0x00000200) /*!< On exception entry, the SP used prior to the exception is adjusted to be 8-byte aligned */
+
+/******************* Bit definition for SCB_SHPR register ********************/
+#define SCB_SHPR_PRI_N_Pos (0U)
+#define SCB_SHPR_PRI_N_Msk (0xFFU << SCB_SHPR_PRI_N_Pos) /*!< 0x000000FF */
+#define SCB_SHPR_PRI_N SCB_SHPR_PRI_N_Msk /*!< Priority of system handler 4,8, and 12. Mem Manage, reserved and Debug Monitor */
+#define SCB_SHPR_PRI_N1_Pos (8U)
+#define SCB_SHPR_PRI_N1_Msk (0xFFU << SCB_SHPR_PRI_N1_Pos) /*!< 0x0000FF00 */
+#define SCB_SHPR_PRI_N1 SCB_SHPR_PRI_N1_Msk /*!< Priority of system handler 5,9, and 13. Bus Fault, reserved and reserved */
+#define SCB_SHPR_PRI_N2_Pos (16U)
+#define SCB_SHPR_PRI_N2_Msk (0xFFU << SCB_SHPR_PRI_N2_Pos) /*!< 0x00FF0000 */
+#define SCB_SHPR_PRI_N2 SCB_SHPR_PRI_N2_Msk /*!< Priority of system handler 6,10, and 14. Usage Fault, reserved and PendSV */
+#define SCB_SHPR_PRI_N3_Pos (24U)
+#define SCB_SHPR_PRI_N3_Msk (0xFFU << SCB_SHPR_PRI_N3_Pos) /*!< 0xFF000000 */
+#define SCB_SHPR_PRI_N3 SCB_SHPR_PRI_N3_Msk /*!< Priority of system handler 7,11, and 15. Reserved, SVCall and SysTick */
+
+/****************** Bit definition for SCB_SHCSR register *******************/
+#define SCB_SHCSR_MEMFAULTACT ((uint32_t)0x00000001) /*!< MemManage is active */
+#define SCB_SHCSR_BUSFAULTACT ((uint32_t)0x00000002) /*!< BusFault is active */
+#define SCB_SHCSR_USGFAULTACT ((uint32_t)0x00000008) /*!< UsageFault is active */
+#define SCB_SHCSR_SVCALLACT ((uint32_t)0x00000080) /*!< SVCall is active */
+#define SCB_SHCSR_MONITORACT ((uint32_t)0x00000100) /*!< Monitor is active */
+#define SCB_SHCSR_PENDSVACT ((uint32_t)0x00000400) /*!< PendSV is active */
+#define SCB_SHCSR_SYSTICKACT ((uint32_t)0x00000800) /*!< SysTick is active */
+#define SCB_SHCSR_USGFAULTPENDED ((uint32_t)0x00001000) /*!< Usage Fault is pended */
+#define SCB_SHCSR_MEMFAULTPENDED ((uint32_t)0x00002000) /*!< MemManage is pended */
+#define SCB_SHCSR_BUSFAULTPENDED ((uint32_t)0x00004000) /*!< Bus Fault is pended */
+#define SCB_SHCSR_SVCALLPENDED ((uint32_t)0x00008000) /*!< SVCall is pended */
+#define SCB_SHCSR_MEMFAULTENA ((uint32_t)0x00010000) /*!< MemManage enable */
+#define SCB_SHCSR_BUSFAULTENA ((uint32_t)0x00020000) /*!< Bus Fault enable */
+#define SCB_SHCSR_USGFAULTENA ((uint32_t)0x00040000) /*!< UsageFault enable */
+
+/******************* Bit definition for SCB_CFSR register *******************/
+/*!< MFSR */
+#define SCB_CFSR_IACCVIOL_Pos (0U)
+#define SCB_CFSR_IACCVIOL_Msk (0x1U << SCB_CFSR_IACCVIOL_Pos) /*!< 0x00000001 */
+#define SCB_CFSR_IACCVIOL SCB_CFSR_IACCVIOL_Msk /*!< Instruction access violation */
+#define SCB_CFSR_DACCVIOL_Pos (1U)
+#define SCB_CFSR_DACCVIOL_Msk (0x1U << SCB_CFSR_DACCVIOL_Pos) /*!< 0x00000002 */
+#define SCB_CFSR_DACCVIOL SCB_CFSR_DACCVIOL_Msk /*!< Data access violation */
+#define SCB_CFSR_MUNSTKERR_Pos (3U)
+#define SCB_CFSR_MUNSTKERR_Msk (0x1U << SCB_CFSR_MUNSTKERR_Pos) /*!< 0x00000008 */
+#define SCB_CFSR_MUNSTKERR SCB_CFSR_MUNSTKERR_Msk /*!< Unstacking error */
+#define SCB_CFSR_MSTKERR_Pos (4U)
+#define SCB_CFSR_MSTKERR_Msk (0x1U << SCB_CFSR_MSTKERR_Pos) /*!< 0x00000010 */
+#define SCB_CFSR_MSTKERR SCB_CFSR_MSTKERR_Msk /*!< Stacking error */
+#define SCB_CFSR_MMARVALID_Pos (7U)
+#define SCB_CFSR_MMARVALID_Msk (0x1U << SCB_CFSR_MMARVALID_Pos) /*!< 0x00000080 */
+#define SCB_CFSR_MMARVALID SCB_CFSR_MMARVALID_Msk /*!< Memory Manage Address Register address valid flag */
+/*!< BFSR */
+#define SCB_CFSR_IBUSERR_Pos (8U)
+#define SCB_CFSR_IBUSERR_Msk (0x1U << SCB_CFSR_IBUSERR_Pos) /*!< 0x00000100 */
+#define SCB_CFSR_IBUSERR SCB_CFSR_IBUSERR_Msk /*!< Instruction bus error flag */
+#define SCB_CFSR_PRECISERR_Pos (9U)
+#define SCB_CFSR_PRECISERR_Msk (0x1U << SCB_CFSR_PRECISERR_Pos) /*!< 0x00000200 */
+#define SCB_CFSR_PRECISERR SCB_CFSR_PRECISERR_Msk /*!< Precise data bus error */
+#define SCB_CFSR_IMPRECISERR_Pos (10U)
+#define SCB_CFSR_IMPRECISERR_Msk (0x1U << SCB_CFSR_IMPRECISERR_Pos) /*!< 0x00000400 */
+#define SCB_CFSR_IMPRECISERR SCB_CFSR_IMPRECISERR_Msk /*!< Imprecise data bus error */
+#define SCB_CFSR_UNSTKERR_Pos (11U)
+#define SCB_CFSR_UNSTKERR_Msk (0x1U << SCB_CFSR_UNSTKERR_Pos) /*!< 0x00000800 */
+#define SCB_CFSR_UNSTKERR SCB_CFSR_UNSTKERR_Msk /*!< Unstacking error */
+#define SCB_CFSR_STKERR_Pos (12U)
+#define SCB_CFSR_STKERR_Msk (0x1U << SCB_CFSR_STKERR_Pos) /*!< 0x00001000 */
+#define SCB_CFSR_STKERR SCB_CFSR_STKERR_Msk /*!< Stacking error */
+#define SCB_CFSR_BFARVALID_Pos (15U)
+#define SCB_CFSR_BFARVALID_Msk (0x1U << SCB_CFSR_BFARVALID_Pos) /*!< 0x00008000 */
+#define SCB_CFSR_BFARVALID SCB_CFSR_BFARVALID_Msk /*!< Bus Fault Address Register address valid flag */
+/*!< UFSR */
+#define SCB_CFSR_UNDEFINSTR_Pos (16U)
+#define SCB_CFSR_UNDEFINSTR_Msk (0x1U << SCB_CFSR_UNDEFINSTR_Pos) /*!< 0x00010000 */
+#define SCB_CFSR_UNDEFINSTR SCB_CFSR_UNDEFINSTR_Msk /*!< The processor attempt to execute an undefined instruction */
+#define SCB_CFSR_INVSTATE_Pos (17U)
+#define SCB_CFSR_INVSTATE_Msk (0x1U << SCB_CFSR_INVSTATE_Pos) /*!< 0x00020000 */
+#define SCB_CFSR_INVSTATE SCB_CFSR_INVSTATE_Msk /*!< Invalid combination of EPSR and instruction */
+#define SCB_CFSR_INVPC_Pos (18U)
+#define SCB_CFSR_INVPC_Msk (0x1U << SCB_CFSR_INVPC_Pos) /*!< 0x00040000 */
+#define SCB_CFSR_INVPC SCB_CFSR_INVPC_Msk /*!< Attempt to load EXC_RETURN into pc illegally */
+#define SCB_CFSR_NOCP_Pos (19U)
+#define SCB_CFSR_NOCP_Msk (0x1U << SCB_CFSR_NOCP_Pos) /*!< 0x00080000 */
+#define SCB_CFSR_NOCP SCB_CFSR_NOCP_Msk /*!< Attempt to use a coprocessor instruction */
+#define SCB_CFSR_UNALIGNED_Pos (24U)
+#define SCB_CFSR_UNALIGNED_Msk (0x1U << SCB_CFSR_UNALIGNED_Pos) /*!< 0x01000000 */
+#define SCB_CFSR_UNALIGNED SCB_CFSR_UNALIGNED_Msk /*!< Fault occurs when there is an attempt to make an unaligned memory access */
+#define SCB_CFSR_DIVBYZERO_Pos (25U)
+#define SCB_CFSR_DIVBYZERO_Msk (0x1U << SCB_CFSR_DIVBYZERO_Pos) /*!< 0x02000000 */
+#define SCB_CFSR_DIVBYZERO SCB_CFSR_DIVBYZERO_Msk /*!< Fault occurs when SDIV or DIV instruction is used with a divisor of 0 */
+
+/******************* Bit definition for SCB_HFSR register *******************/
+#define SCB_HFSR_VECTTBL ((uint32_t)0x00000002) /*!< Fault occurs because of vector table read on exception processing */
+#define SCB_HFSR_FORCED ((uint32_t)0x40000000) /*!< Hard Fault activated when a configurable Fault was received and cannot activate */
+#define SCB_HFSR_DEBUGEVT ((uint32_t)0x80000000) /*!< Fault related to debug */
+
+/******************* Bit definition for SCB_DFSR register *******************/
+#define SCB_DFSR_HALTED ((uint32_t)0x00000001) /*!< Halt request flag */
+#define SCB_DFSR_BKPT ((uint32_t)0x00000002) /*!< BKPT flag */
+#define SCB_DFSR_DWTTRAP ((uint32_t)0x00000004) /*!< Data Watchpoint and Trace (DWT) flag */
+#define SCB_DFSR_VCATCH ((uint32_t)0x00000008) /*!< Vector catch flag */
+#define SCB_DFSR_EXTERNAL ((uint32_t)0x00000010) /*!< External debug request flag */
+
+/******************* Bit definition for SCB_MMFAR register ******************/
+#define SCB_MMFAR_ADDRESS_Pos (0U)
+#define SCB_MMFAR_ADDRESS_Msk (0xFFFFFFFFU << SCB_MMFAR_ADDRESS_Pos) /*!< 0xFFFFFFFF */
+#define SCB_MMFAR_ADDRESS SCB_MMFAR_ADDRESS_Msk /*!< Mem Manage fault address field */
+
+/******************* Bit definition for SCB_BFAR register *******************/
+#define SCB_BFAR_ADDRESS_Pos (0U)
+#define SCB_BFAR_ADDRESS_Msk (0xFFFFFFFFU << SCB_BFAR_ADDRESS_Pos) /*!< 0xFFFFFFFF */
+#define SCB_BFAR_ADDRESS SCB_BFAR_ADDRESS_Msk /*!< Bus fault address field */
+
+/******************* Bit definition for SCB_afsr register *******************/
+#define SCB_AFSR_IMPDEF_Pos (0U)
+#define SCB_AFSR_IMPDEF_Msk (0xFFFFFFFFU << SCB_AFSR_IMPDEF_Pos) /*!< 0xFFFFFFFF */
+#define SCB_AFSR_IMPDEF SCB_AFSR_IMPDEF_Msk /*!< Implementation defined */
+
+/******************************************************************************/
+/* */
+/* External Interrupt/Event Controller */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for EXTI_IMR register *******************/
+#define EXTI_IMR_MR0_Pos (0U)
+#define EXTI_IMR_MR0_Msk (0x1U << EXTI_IMR_MR0_Pos) /*!< 0x00000001 */
+#define EXTI_IMR_MR0 EXTI_IMR_MR0_Msk /*!< Interrupt Mask on line 0 */
+#define EXTI_IMR_MR1_Pos (1U)
+#define EXTI_IMR_MR1_Msk (0x1U << EXTI_IMR_MR1_Pos) /*!< 0x00000002 */
+#define EXTI_IMR_MR1 EXTI_IMR_MR1_Msk /*!< Interrupt Mask on line 1 */
+#define EXTI_IMR_MR2_Pos (2U)
+#define EXTI_IMR_MR2_Msk (0x1U << EXTI_IMR_MR2_Pos) /*!< 0x00000004 */
+#define EXTI_IMR_MR2 EXTI_IMR_MR2_Msk /*!< Interrupt Mask on line 2 */
+#define EXTI_IMR_MR3_Pos (3U)
+#define EXTI_IMR_MR3_Msk (0x1U << EXTI_IMR_MR3_Pos) /*!< 0x00000008 */
+#define EXTI_IMR_MR3 EXTI_IMR_MR3_Msk /*!< Interrupt Mask on line 3 */
+#define EXTI_IMR_MR4_Pos (4U)
+#define EXTI_IMR_MR4_Msk (0x1U << EXTI_IMR_MR4_Pos) /*!< 0x00000010 */
+#define EXTI_IMR_MR4 EXTI_IMR_MR4_Msk /*!< Interrupt Mask on line 4 */
+#define EXTI_IMR_MR5_Pos (5U)
+#define EXTI_IMR_MR5_Msk (0x1U << EXTI_IMR_MR5_Pos) /*!< 0x00000020 */
+#define EXTI_IMR_MR5 EXTI_IMR_MR5_Msk /*!< Interrupt Mask on line 5 */
+#define EXTI_IMR_MR6_Pos (6U)
+#define EXTI_IMR_MR6_Msk (0x1U << EXTI_IMR_MR6_Pos) /*!< 0x00000040 */
+#define EXTI_IMR_MR6 EXTI_IMR_MR6_Msk /*!< Interrupt Mask on line 6 */
+#define EXTI_IMR_MR7_Pos (7U)
+#define EXTI_IMR_MR7_Msk (0x1U << EXTI_IMR_MR7_Pos) /*!< 0x00000080 */
+#define EXTI_IMR_MR7 EXTI_IMR_MR7_Msk /*!< Interrupt Mask on line 7 */
+#define EXTI_IMR_MR8_Pos (8U)
+#define EXTI_IMR_MR8_Msk (0x1U << EXTI_IMR_MR8_Pos) /*!< 0x00000100 */
+#define EXTI_IMR_MR8 EXTI_IMR_MR8_Msk /*!< Interrupt Mask on line 8 */
+#define EXTI_IMR_MR9_Pos (9U)
+#define EXTI_IMR_MR9_Msk (0x1U << EXTI_IMR_MR9_Pos) /*!< 0x00000200 */
+#define EXTI_IMR_MR9 EXTI_IMR_MR9_Msk /*!< Interrupt Mask on line 9 */
+#define EXTI_IMR_MR10_Pos (10U)
+#define EXTI_IMR_MR10_Msk (0x1U << EXTI_IMR_MR10_Pos) /*!< 0x00000400 */
+#define EXTI_IMR_MR10 EXTI_IMR_MR10_Msk /*!< Interrupt Mask on line 10 */
+#define EXTI_IMR_MR11_Pos (11U)
+#define EXTI_IMR_MR11_Msk (0x1U << EXTI_IMR_MR11_Pos) /*!< 0x00000800 */
+#define EXTI_IMR_MR11 EXTI_IMR_MR11_Msk /*!< Interrupt Mask on line 11 */
+#define EXTI_IMR_MR12_Pos (12U)
+#define EXTI_IMR_MR12_Msk (0x1U << EXTI_IMR_MR12_Pos) /*!< 0x00001000 */
+#define EXTI_IMR_MR12 EXTI_IMR_MR12_Msk /*!< Interrupt Mask on line 12 */
+#define EXTI_IMR_MR13_Pos (13U)
+#define EXTI_IMR_MR13_Msk (0x1U << EXTI_IMR_MR13_Pos) /*!< 0x00002000 */
+#define EXTI_IMR_MR13 EXTI_IMR_MR13_Msk /*!< Interrupt Mask on line 13 */
+#define EXTI_IMR_MR14_Pos (14U)
+#define EXTI_IMR_MR14_Msk (0x1U << EXTI_IMR_MR14_Pos) /*!< 0x00004000 */
+#define EXTI_IMR_MR14 EXTI_IMR_MR14_Msk /*!< Interrupt Mask on line 14 */
+#define EXTI_IMR_MR15_Pos (15U)
+#define EXTI_IMR_MR15_Msk (0x1U << EXTI_IMR_MR15_Pos) /*!< 0x00008000 */
+#define EXTI_IMR_MR15 EXTI_IMR_MR15_Msk /*!< Interrupt Mask on line 15 */
+#define EXTI_IMR_MR16_Pos (16U)
+#define EXTI_IMR_MR16_Msk (0x1U << EXTI_IMR_MR16_Pos) /*!< 0x00010000 */
+#define EXTI_IMR_MR16 EXTI_IMR_MR16_Msk /*!< Interrupt Mask on line 16 */
+#define EXTI_IMR_MR17_Pos (17U)
+#define EXTI_IMR_MR17_Msk (0x1U << EXTI_IMR_MR17_Pos) /*!< 0x00020000 */
+#define EXTI_IMR_MR17 EXTI_IMR_MR17_Msk /*!< Interrupt Mask on line 17 */
+#define EXTI_IMR_MR18_Pos (18U)
+#define EXTI_IMR_MR18_Msk (0x1U << EXTI_IMR_MR18_Pos) /*!< 0x00040000 */
+#define EXTI_IMR_MR18 EXTI_IMR_MR18_Msk /*!< Interrupt Mask on line 18 */
+#define EXTI_IMR_MR19_Pos (19U)
+#define EXTI_IMR_MR19_Msk (0x1U << EXTI_IMR_MR19_Pos) /*!< 0x00080000 */
+#define EXTI_IMR_MR19 EXTI_IMR_MR19_Msk /*!< Interrupt Mask on line 19 */
+
+/* References Defines */
+#define EXTI_IMR_IM0 EXTI_IMR_MR0
+#define EXTI_IMR_IM1 EXTI_IMR_MR1
+#define EXTI_IMR_IM2 EXTI_IMR_MR2
+#define EXTI_IMR_IM3 EXTI_IMR_MR3
+#define EXTI_IMR_IM4 EXTI_IMR_MR4
+#define EXTI_IMR_IM5 EXTI_IMR_MR5
+#define EXTI_IMR_IM6 EXTI_IMR_MR6
+#define EXTI_IMR_IM7 EXTI_IMR_MR7
+#define EXTI_IMR_IM8 EXTI_IMR_MR8
+#define EXTI_IMR_IM9 EXTI_IMR_MR9
+#define EXTI_IMR_IM10 EXTI_IMR_MR10
+#define EXTI_IMR_IM11 EXTI_IMR_MR11
+#define EXTI_IMR_IM12 EXTI_IMR_MR12
+#define EXTI_IMR_IM13 EXTI_IMR_MR13
+#define EXTI_IMR_IM14 EXTI_IMR_MR14
+#define EXTI_IMR_IM15 EXTI_IMR_MR15
+#define EXTI_IMR_IM16 EXTI_IMR_MR16
+#define EXTI_IMR_IM17 EXTI_IMR_MR17
+#define EXTI_IMR_IM18 EXTI_IMR_MR18
+#define EXTI_IMR_IM19 EXTI_IMR_MR19
+
+/******************* Bit definition for EXTI_EMR register *******************/
+#define EXTI_EMR_MR0_Pos (0U)
+#define EXTI_EMR_MR0_Msk (0x1U << EXTI_EMR_MR0_Pos) /*!< 0x00000001 */
+#define EXTI_EMR_MR0 EXTI_EMR_MR0_Msk /*!< Event Mask on line 0 */
+#define EXTI_EMR_MR1_Pos (1U)
+#define EXTI_EMR_MR1_Msk (0x1U << EXTI_EMR_MR1_Pos) /*!< 0x00000002 */
+#define EXTI_EMR_MR1 EXTI_EMR_MR1_Msk /*!< Event Mask on line 1 */
+#define EXTI_EMR_MR2_Pos (2U)
+#define EXTI_EMR_MR2_Msk (0x1U << EXTI_EMR_MR2_Pos) /*!< 0x00000004 */
+#define EXTI_EMR_MR2 EXTI_EMR_MR2_Msk /*!< Event Mask on line 2 */
+#define EXTI_EMR_MR3_Pos (3U)
+#define EXTI_EMR_MR3_Msk (0x1U << EXTI_EMR_MR3_Pos) /*!< 0x00000008 */
+#define EXTI_EMR_MR3 EXTI_EMR_MR3_Msk /*!< Event Mask on line 3 */
+#define EXTI_EMR_MR4_Pos (4U)
+#define EXTI_EMR_MR4_Msk (0x1U << EXTI_EMR_MR4_Pos) /*!< 0x00000010 */
+#define EXTI_EMR_MR4 EXTI_EMR_MR4_Msk /*!< Event Mask on line 4 */
+#define EXTI_EMR_MR5_Pos (5U)
+#define EXTI_EMR_MR5_Msk (0x1U << EXTI_EMR_MR5_Pos) /*!< 0x00000020 */
+#define EXTI_EMR_MR5 EXTI_EMR_MR5_Msk /*!< Event Mask on line 5 */
+#define EXTI_EMR_MR6_Pos (6U)
+#define EXTI_EMR_MR6_Msk (0x1U << EXTI_EMR_MR6_Pos) /*!< 0x00000040 */
+#define EXTI_EMR_MR6 EXTI_EMR_MR6_Msk /*!< Event Mask on line 6 */
+#define EXTI_EMR_MR7_Pos (7U)
+#define EXTI_EMR_MR7_Msk (0x1U << EXTI_EMR_MR7_Pos) /*!< 0x00000080 */
+#define EXTI_EMR_MR7 EXTI_EMR_MR7_Msk /*!< Event Mask on line 7 */
+#define EXTI_EMR_MR8_Pos (8U)
+#define EXTI_EMR_MR8_Msk (0x1U << EXTI_EMR_MR8_Pos) /*!< 0x00000100 */
+#define EXTI_EMR_MR8 EXTI_EMR_MR8_Msk /*!< Event Mask on line 8 */
+#define EXTI_EMR_MR9_Pos (9U)
+#define EXTI_EMR_MR9_Msk (0x1U << EXTI_EMR_MR9_Pos) /*!< 0x00000200 */
+#define EXTI_EMR_MR9 EXTI_EMR_MR9_Msk /*!< Event Mask on line 9 */
+#define EXTI_EMR_MR10_Pos (10U)
+#define EXTI_EMR_MR10_Msk (0x1U << EXTI_EMR_MR10_Pos) /*!< 0x00000400 */
+#define EXTI_EMR_MR10 EXTI_EMR_MR10_Msk /*!< Event Mask on line 10 */
+#define EXTI_EMR_MR11_Pos (11U)
+#define EXTI_EMR_MR11_Msk (0x1U << EXTI_EMR_MR11_Pos) /*!< 0x00000800 */
+#define EXTI_EMR_MR11 EXTI_EMR_MR11_Msk /*!< Event Mask on line 11 */
+#define EXTI_EMR_MR12_Pos (12U)
+#define EXTI_EMR_MR12_Msk (0x1U << EXTI_EMR_MR12_Pos) /*!< 0x00001000 */
+#define EXTI_EMR_MR12 EXTI_EMR_MR12_Msk /*!< Event Mask on line 12 */
+#define EXTI_EMR_MR13_Pos (13U)
+#define EXTI_EMR_MR13_Msk (0x1U << EXTI_EMR_MR13_Pos) /*!< 0x00002000 */
+#define EXTI_EMR_MR13 EXTI_EMR_MR13_Msk /*!< Event Mask on line 13 */
+#define EXTI_EMR_MR14_Pos (14U)
+#define EXTI_EMR_MR14_Msk (0x1U << EXTI_EMR_MR14_Pos) /*!< 0x00004000 */
+#define EXTI_EMR_MR14 EXTI_EMR_MR14_Msk /*!< Event Mask on line 14 */
+#define EXTI_EMR_MR15_Pos (15U)
+#define EXTI_EMR_MR15_Msk (0x1U << EXTI_EMR_MR15_Pos) /*!< 0x00008000 */
+#define EXTI_EMR_MR15 EXTI_EMR_MR15_Msk /*!< Event Mask on line 15 */
+#define EXTI_EMR_MR16_Pos (16U)
+#define EXTI_EMR_MR16_Msk (0x1U << EXTI_EMR_MR16_Pos) /*!< 0x00010000 */
+#define EXTI_EMR_MR16 EXTI_EMR_MR16_Msk /*!< Event Mask on line 16 */
+#define EXTI_EMR_MR17_Pos (17U)
+#define EXTI_EMR_MR17_Msk (0x1U << EXTI_EMR_MR17_Pos) /*!< 0x00020000 */
+#define EXTI_EMR_MR17 EXTI_EMR_MR17_Msk /*!< Event Mask on line 17 */
+#define EXTI_EMR_MR18_Pos (18U)
+#define EXTI_EMR_MR18_Msk (0x1U << EXTI_EMR_MR18_Pos) /*!< 0x00040000 */
+#define EXTI_EMR_MR18 EXTI_EMR_MR18_Msk /*!< Event Mask on line 18 */
+#define EXTI_EMR_MR19_Pos (19U)
+#define EXTI_EMR_MR19_Msk (0x1U << EXTI_EMR_MR19_Pos) /*!< 0x00080000 */
+#define EXTI_EMR_MR19 EXTI_EMR_MR19_Msk /*!< Event Mask on line 19 */
+
+/* References Defines */
+#define EXTI_EMR_EM0 EXTI_EMR_MR0
+#define EXTI_EMR_EM1 EXTI_EMR_MR1
+#define EXTI_EMR_EM2 EXTI_EMR_MR2
+#define EXTI_EMR_EM3 EXTI_EMR_MR3
+#define EXTI_EMR_EM4 EXTI_EMR_MR4
+#define EXTI_EMR_EM5 EXTI_EMR_MR5
+#define EXTI_EMR_EM6 EXTI_EMR_MR6
+#define EXTI_EMR_EM7 EXTI_EMR_MR7
+#define EXTI_EMR_EM8 EXTI_EMR_MR8
+#define EXTI_EMR_EM9 EXTI_EMR_MR9
+#define EXTI_EMR_EM10 EXTI_EMR_MR10
+#define EXTI_EMR_EM11 EXTI_EMR_MR11
+#define EXTI_EMR_EM12 EXTI_EMR_MR12
+#define EXTI_EMR_EM13 EXTI_EMR_MR13
+#define EXTI_EMR_EM14 EXTI_EMR_MR14
+#define EXTI_EMR_EM15 EXTI_EMR_MR15
+#define EXTI_EMR_EM16 EXTI_EMR_MR16
+#define EXTI_EMR_EM17 EXTI_EMR_MR17
+#define EXTI_EMR_EM18 EXTI_EMR_MR18
+#define EXTI_EMR_EM19 EXTI_EMR_MR19
+
+/****************** Bit definition for EXTI_RTSR register *******************/
+#define EXTI_RTSR_TR0_Pos (0U)
+#define EXTI_RTSR_TR0_Msk (0x1U << EXTI_RTSR_TR0_Pos) /*!< 0x00000001 */
+#define EXTI_RTSR_TR0 EXTI_RTSR_TR0_Msk /*!< Rising trigger event configuration bit of line 0 */
+#define EXTI_RTSR_TR1_Pos (1U)
+#define EXTI_RTSR_TR1_Msk (0x1U << EXTI_RTSR_TR1_Pos) /*!< 0x00000002 */
+#define EXTI_RTSR_TR1 EXTI_RTSR_TR1_Msk /*!< Rising trigger event configuration bit of line 1 */
+#define EXTI_RTSR_TR2_Pos (2U)
+#define EXTI_RTSR_TR2_Msk (0x1U << EXTI_RTSR_TR2_Pos) /*!< 0x00000004 */
+#define EXTI_RTSR_TR2 EXTI_RTSR_TR2_Msk /*!< Rising trigger event configuration bit of line 2 */
+#define EXTI_RTSR_TR3_Pos (3U)
+#define EXTI_RTSR_TR3_Msk (0x1U << EXTI_RTSR_TR3_Pos) /*!< 0x00000008 */
+#define EXTI_RTSR_TR3 EXTI_RTSR_TR3_Msk /*!< Rising trigger event configuration bit of line 3 */
+#define EXTI_RTSR_TR4_Pos (4U)
+#define EXTI_RTSR_TR4_Msk (0x1U << EXTI_RTSR_TR4_Pos) /*!< 0x00000010 */
+#define EXTI_RTSR_TR4 EXTI_RTSR_TR4_Msk /*!< Rising trigger event configuration bit of line 4 */
+#define EXTI_RTSR_TR5_Pos (5U)
+#define EXTI_RTSR_TR5_Msk (0x1U << EXTI_RTSR_TR5_Pos) /*!< 0x00000020 */
+#define EXTI_RTSR_TR5 EXTI_RTSR_TR5_Msk /*!< Rising trigger event configuration bit of line 5 */
+#define EXTI_RTSR_TR6_Pos (6U)
+#define EXTI_RTSR_TR6_Msk (0x1U << EXTI_RTSR_TR6_Pos) /*!< 0x00000040 */
+#define EXTI_RTSR_TR6 EXTI_RTSR_TR6_Msk /*!< Rising trigger event configuration bit of line 6 */
+#define EXTI_RTSR_TR7_Pos (7U)
+#define EXTI_RTSR_TR7_Msk (0x1U << EXTI_RTSR_TR7_Pos) /*!< 0x00000080 */
+#define EXTI_RTSR_TR7 EXTI_RTSR_TR7_Msk /*!< Rising trigger event configuration bit of line 7 */
+#define EXTI_RTSR_TR8_Pos (8U)
+#define EXTI_RTSR_TR8_Msk (0x1U << EXTI_RTSR_TR8_Pos) /*!< 0x00000100 */
+#define EXTI_RTSR_TR8 EXTI_RTSR_TR8_Msk /*!< Rising trigger event configuration bit of line 8 */
+#define EXTI_RTSR_TR9_Pos (9U)
+#define EXTI_RTSR_TR9_Msk (0x1U << EXTI_RTSR_TR9_Pos) /*!< 0x00000200 */
+#define EXTI_RTSR_TR9 EXTI_RTSR_TR9_Msk /*!< Rising trigger event configuration bit of line 9 */
+#define EXTI_RTSR_TR10_Pos (10U)
+#define EXTI_RTSR_TR10_Msk (0x1U << EXTI_RTSR_TR10_Pos) /*!< 0x00000400 */
+#define EXTI_RTSR_TR10 EXTI_RTSR_TR10_Msk /*!< Rising trigger event configuration bit of line 10 */
+#define EXTI_RTSR_TR11_Pos (11U)
+#define EXTI_RTSR_TR11_Msk (0x1U << EXTI_RTSR_TR11_Pos) /*!< 0x00000800 */
+#define EXTI_RTSR_TR11 EXTI_RTSR_TR11_Msk /*!< Rising trigger event configuration bit of line 11 */
+#define EXTI_RTSR_TR12_Pos (12U)
+#define EXTI_RTSR_TR12_Msk (0x1U << EXTI_RTSR_TR12_Pos) /*!< 0x00001000 */
+#define EXTI_RTSR_TR12 EXTI_RTSR_TR12_Msk /*!< Rising trigger event configuration bit of line 12 */
+#define EXTI_RTSR_TR13_Pos (13U)
+#define EXTI_RTSR_TR13_Msk (0x1U << EXTI_RTSR_TR13_Pos) /*!< 0x00002000 */
+#define EXTI_RTSR_TR13 EXTI_RTSR_TR13_Msk /*!< Rising trigger event configuration bit of line 13 */
+#define EXTI_RTSR_TR14_Pos (14U)
+#define EXTI_RTSR_TR14_Msk (0x1U << EXTI_RTSR_TR14_Pos) /*!< 0x00004000 */
+#define EXTI_RTSR_TR14 EXTI_RTSR_TR14_Msk /*!< Rising trigger event configuration bit of line 14 */
+#define EXTI_RTSR_TR15_Pos (15U)
+#define EXTI_RTSR_TR15_Msk (0x1U << EXTI_RTSR_TR15_Pos) /*!< 0x00008000 */
+#define EXTI_RTSR_TR15 EXTI_RTSR_TR15_Msk /*!< Rising trigger event configuration bit of line 15 */
+#define EXTI_RTSR_TR16_Pos (16U)
+#define EXTI_RTSR_TR16_Msk (0x1U << EXTI_RTSR_TR16_Pos) /*!< 0x00010000 */
+#define EXTI_RTSR_TR16 EXTI_RTSR_TR16_Msk /*!< Rising trigger event configuration bit of line 16 */
+#define EXTI_RTSR_TR17_Pos (17U)
+#define EXTI_RTSR_TR17_Msk (0x1U << EXTI_RTSR_TR17_Pos) /*!< 0x00020000 */
+#define EXTI_RTSR_TR17 EXTI_RTSR_TR17_Msk /*!< Rising trigger event configuration bit of line 17 */
+#define EXTI_RTSR_TR18_Pos (18U)
+#define EXTI_RTSR_TR18_Msk (0x1U << EXTI_RTSR_TR18_Pos) /*!< 0x00040000 */
+#define EXTI_RTSR_TR18 EXTI_RTSR_TR18_Msk /*!< Rising trigger event configuration bit of line 18 */
+#define EXTI_RTSR_TR19_Pos (19U)
+#define EXTI_RTSR_TR19_Msk (0x1U << EXTI_RTSR_TR19_Pos) /*!< 0x00080000 */
+#define EXTI_RTSR_TR19 EXTI_RTSR_TR19_Msk /*!< Rising trigger event configuration bit of line 19 */
+
+/* References Defines */
+#define EXTI_RTSR_RT0 EXTI_RTSR_TR0
+#define EXTI_RTSR_RT1 EXTI_RTSR_TR1
+#define EXTI_RTSR_RT2 EXTI_RTSR_TR2
+#define EXTI_RTSR_RT3 EXTI_RTSR_TR3
+#define EXTI_RTSR_RT4 EXTI_RTSR_TR4
+#define EXTI_RTSR_RT5 EXTI_RTSR_TR5
+#define EXTI_RTSR_RT6 EXTI_RTSR_TR6
+#define EXTI_RTSR_RT7 EXTI_RTSR_TR7
+#define EXTI_RTSR_RT8 EXTI_RTSR_TR8
+#define EXTI_RTSR_RT9 EXTI_RTSR_TR9
+#define EXTI_RTSR_RT10 EXTI_RTSR_TR10
+#define EXTI_RTSR_RT11 EXTI_RTSR_TR11
+#define EXTI_RTSR_RT12 EXTI_RTSR_TR12
+#define EXTI_RTSR_RT13 EXTI_RTSR_TR13
+#define EXTI_RTSR_RT14 EXTI_RTSR_TR14
+#define EXTI_RTSR_RT15 EXTI_RTSR_TR15
+#define EXTI_RTSR_RT16 EXTI_RTSR_TR16
+#define EXTI_RTSR_RT17 EXTI_RTSR_TR17
+#define EXTI_RTSR_RT18 EXTI_RTSR_TR18
+#define EXTI_RTSR_RT19 EXTI_RTSR_TR19
+
+/****************** Bit definition for EXTI_FTSR register *******************/
+#define EXTI_FTSR_TR0_Pos (0U)
+#define EXTI_FTSR_TR0_Msk (0x1U << EXTI_FTSR_TR0_Pos) /*!< 0x00000001 */
+#define EXTI_FTSR_TR0 EXTI_FTSR_TR0_Msk /*!< Falling trigger event configuration bit of line 0 */
+#define EXTI_FTSR_TR1_Pos (1U)
+#define EXTI_FTSR_TR1_Msk (0x1U << EXTI_FTSR_TR1_Pos) /*!< 0x00000002 */
+#define EXTI_FTSR_TR1 EXTI_FTSR_TR1_Msk /*!< Falling trigger event configuration bit of line 1 */
+#define EXTI_FTSR_TR2_Pos (2U)
+#define EXTI_FTSR_TR2_Msk (0x1U << EXTI_FTSR_TR2_Pos) /*!< 0x00000004 */
+#define EXTI_FTSR_TR2 EXTI_FTSR_TR2_Msk /*!< Falling trigger event configuration bit of line 2 */
+#define EXTI_FTSR_TR3_Pos (3U)
+#define EXTI_FTSR_TR3_Msk (0x1U << EXTI_FTSR_TR3_Pos) /*!< 0x00000008 */
+#define EXTI_FTSR_TR3 EXTI_FTSR_TR3_Msk /*!< Falling trigger event configuration bit of line 3 */
+#define EXTI_FTSR_TR4_Pos (4U)
+#define EXTI_FTSR_TR4_Msk (0x1U << EXTI_FTSR_TR4_Pos) /*!< 0x00000010 */
+#define EXTI_FTSR_TR4 EXTI_FTSR_TR4_Msk /*!< Falling trigger event configuration bit of line 4 */
+#define EXTI_FTSR_TR5_Pos (5U)
+#define EXTI_FTSR_TR5_Msk (0x1U << EXTI_FTSR_TR5_Pos) /*!< 0x00000020 */
+#define EXTI_FTSR_TR5 EXTI_FTSR_TR5_Msk /*!< Falling trigger event configuration bit of line 5 */
+#define EXTI_FTSR_TR6_Pos (6U)
+#define EXTI_FTSR_TR6_Msk (0x1U << EXTI_FTSR_TR6_Pos) /*!< 0x00000040 */
+#define EXTI_FTSR_TR6 EXTI_FTSR_TR6_Msk /*!< Falling trigger event configuration bit of line 6 */
+#define EXTI_FTSR_TR7_Pos (7U)
+#define EXTI_FTSR_TR7_Msk (0x1U << EXTI_FTSR_TR7_Pos) /*!< 0x00000080 */
+#define EXTI_FTSR_TR7 EXTI_FTSR_TR7_Msk /*!< Falling trigger event configuration bit of line 7 */
+#define EXTI_FTSR_TR8_Pos (8U)
+#define EXTI_FTSR_TR8_Msk (0x1U << EXTI_FTSR_TR8_Pos) /*!< 0x00000100 */
+#define EXTI_FTSR_TR8 EXTI_FTSR_TR8_Msk /*!< Falling trigger event configuration bit of line 8 */
+#define EXTI_FTSR_TR9_Pos (9U)
+#define EXTI_FTSR_TR9_Msk (0x1U << EXTI_FTSR_TR9_Pos) /*!< 0x00000200 */
+#define EXTI_FTSR_TR9 EXTI_FTSR_TR9_Msk /*!< Falling trigger event configuration bit of line 9 */
+#define EXTI_FTSR_TR10_Pos (10U)
+#define EXTI_FTSR_TR10_Msk (0x1U << EXTI_FTSR_TR10_Pos) /*!< 0x00000400 */
+#define EXTI_FTSR_TR10 EXTI_FTSR_TR10_Msk /*!< Falling trigger event configuration bit of line 10 */
+#define EXTI_FTSR_TR11_Pos (11U)
+#define EXTI_FTSR_TR11_Msk (0x1U << EXTI_FTSR_TR11_Pos) /*!< 0x00000800 */
+#define EXTI_FTSR_TR11 EXTI_FTSR_TR11_Msk /*!< Falling trigger event configuration bit of line 11 */
+#define EXTI_FTSR_TR12_Pos (12U)
+#define EXTI_FTSR_TR12_Msk (0x1U << EXTI_FTSR_TR12_Pos) /*!< 0x00001000 */
+#define EXTI_FTSR_TR12 EXTI_FTSR_TR12_Msk /*!< Falling trigger event configuration bit of line 12 */
+#define EXTI_FTSR_TR13_Pos (13U)
+#define EXTI_FTSR_TR13_Msk (0x1U << EXTI_FTSR_TR13_Pos) /*!< 0x00002000 */
+#define EXTI_FTSR_TR13 EXTI_FTSR_TR13_Msk /*!< Falling trigger event configuration bit of line 13 */
+#define EXTI_FTSR_TR14_Pos (14U)
+#define EXTI_FTSR_TR14_Msk (0x1U << EXTI_FTSR_TR14_Pos) /*!< 0x00004000 */
+#define EXTI_FTSR_TR14 EXTI_FTSR_TR14_Msk /*!< Falling trigger event configuration bit of line 14 */
+#define EXTI_FTSR_TR15_Pos (15U)
+#define EXTI_FTSR_TR15_Msk (0x1U << EXTI_FTSR_TR15_Pos) /*!< 0x00008000 */
+#define EXTI_FTSR_TR15 EXTI_FTSR_TR15_Msk /*!< Falling trigger event configuration bit of line 15 */
+#define EXTI_FTSR_TR16_Pos (16U)
+#define EXTI_FTSR_TR16_Msk (0x1U << EXTI_FTSR_TR16_Pos) /*!< 0x00010000 */
+#define EXTI_FTSR_TR16 EXTI_FTSR_TR16_Msk /*!< Falling trigger event configuration bit of line 16 */
+#define EXTI_FTSR_TR17_Pos (17U)
+#define EXTI_FTSR_TR17_Msk (0x1U << EXTI_FTSR_TR17_Pos) /*!< 0x00020000 */
+#define EXTI_FTSR_TR17 EXTI_FTSR_TR17_Msk /*!< Falling trigger event configuration bit of line 17 */
+#define EXTI_FTSR_TR18_Pos (18U)
+#define EXTI_FTSR_TR18_Msk (0x1U << EXTI_FTSR_TR18_Pos) /*!< 0x00040000 */
+#define EXTI_FTSR_TR18 EXTI_FTSR_TR18_Msk /*!< Falling trigger event configuration bit of line 18 */
+#define EXTI_FTSR_TR19_Pos (19U)
+#define EXTI_FTSR_TR19_Msk (0x1U << EXTI_FTSR_TR19_Pos) /*!< 0x00080000 */
+#define EXTI_FTSR_TR19 EXTI_FTSR_TR19_Msk /*!< Falling trigger event configuration bit of line 19 */
+
+/* References Defines */
+#define EXTI_FTSR_FT0 EXTI_FTSR_TR0
+#define EXTI_FTSR_FT1 EXTI_FTSR_TR1
+#define EXTI_FTSR_FT2 EXTI_FTSR_TR2
+#define EXTI_FTSR_FT3 EXTI_FTSR_TR3
+#define EXTI_FTSR_FT4 EXTI_FTSR_TR4
+#define EXTI_FTSR_FT5 EXTI_FTSR_TR5
+#define EXTI_FTSR_FT6 EXTI_FTSR_TR6
+#define EXTI_FTSR_FT7 EXTI_FTSR_TR7
+#define EXTI_FTSR_FT8 EXTI_FTSR_TR8
+#define EXTI_FTSR_FT9 EXTI_FTSR_TR9
+#define EXTI_FTSR_FT10 EXTI_FTSR_TR10
+#define EXTI_FTSR_FT11 EXTI_FTSR_TR11
+#define EXTI_FTSR_FT12 EXTI_FTSR_TR12
+#define EXTI_FTSR_FT13 EXTI_FTSR_TR13
+#define EXTI_FTSR_FT14 EXTI_FTSR_TR14
+#define EXTI_FTSR_FT15 EXTI_FTSR_TR15
+#define EXTI_FTSR_FT16 EXTI_FTSR_TR16
+#define EXTI_FTSR_FT17 EXTI_FTSR_TR17
+#define EXTI_FTSR_FT18 EXTI_FTSR_TR18
+#define EXTI_FTSR_FT19 EXTI_FTSR_TR19
+
+/****************** Bit definition for EXTI_SWIER register ******************/
+#define EXTI_SWIER_SWIER0_Pos (0U)
+#define EXTI_SWIER_SWIER0_Msk (0x1U << EXTI_SWIER_SWIER0_Pos) /*!< 0x00000001 */
+#define EXTI_SWIER_SWIER0 EXTI_SWIER_SWIER0_Msk /*!< Software Interrupt on line 0 */
+#define EXTI_SWIER_SWIER1_Pos (1U)
+#define EXTI_SWIER_SWIER1_Msk (0x1U << EXTI_SWIER_SWIER1_Pos) /*!< 0x00000002 */
+#define EXTI_SWIER_SWIER1 EXTI_SWIER_SWIER1_Msk /*!< Software Interrupt on line 1 */
+#define EXTI_SWIER_SWIER2_Pos (2U)
+#define EXTI_SWIER_SWIER2_Msk (0x1U << EXTI_SWIER_SWIER2_Pos) /*!< 0x00000004 */
+#define EXTI_SWIER_SWIER2 EXTI_SWIER_SWIER2_Msk /*!< Software Interrupt on line 2 */
+#define EXTI_SWIER_SWIER3_Pos (3U)
+#define EXTI_SWIER_SWIER3_Msk (0x1U << EXTI_SWIER_SWIER3_Pos) /*!< 0x00000008 */
+#define EXTI_SWIER_SWIER3 EXTI_SWIER_SWIER3_Msk /*!< Software Interrupt on line 3 */
+#define EXTI_SWIER_SWIER4_Pos (4U)
+#define EXTI_SWIER_SWIER4_Msk (0x1U << EXTI_SWIER_SWIER4_Pos) /*!< 0x00000010 */
+#define EXTI_SWIER_SWIER4 EXTI_SWIER_SWIER4_Msk /*!< Software Interrupt on line 4 */
+#define EXTI_SWIER_SWIER5_Pos (5U)
+#define EXTI_SWIER_SWIER5_Msk (0x1U << EXTI_SWIER_SWIER5_Pos) /*!< 0x00000020 */
+#define EXTI_SWIER_SWIER5 EXTI_SWIER_SWIER5_Msk /*!< Software Interrupt on line 5 */
+#define EXTI_SWIER_SWIER6_Pos (6U)
+#define EXTI_SWIER_SWIER6_Msk (0x1U << EXTI_SWIER_SWIER6_Pos) /*!< 0x00000040 */
+#define EXTI_SWIER_SWIER6 EXTI_SWIER_SWIER6_Msk /*!< Software Interrupt on line 6 */
+#define EXTI_SWIER_SWIER7_Pos (7U)
+#define EXTI_SWIER_SWIER7_Msk (0x1U << EXTI_SWIER_SWIER7_Pos) /*!< 0x00000080 */
+#define EXTI_SWIER_SWIER7 EXTI_SWIER_SWIER7_Msk /*!< Software Interrupt on line 7 */
+#define EXTI_SWIER_SWIER8_Pos (8U)
+#define EXTI_SWIER_SWIER8_Msk (0x1U << EXTI_SWIER_SWIER8_Pos) /*!< 0x00000100 */
+#define EXTI_SWIER_SWIER8 EXTI_SWIER_SWIER8_Msk /*!< Software Interrupt on line 8 */
+#define EXTI_SWIER_SWIER9_Pos (9U)
+#define EXTI_SWIER_SWIER9_Msk (0x1U << EXTI_SWIER_SWIER9_Pos) /*!< 0x00000200 */
+#define EXTI_SWIER_SWIER9 EXTI_SWIER_SWIER9_Msk /*!< Software Interrupt on line 9 */
+#define EXTI_SWIER_SWIER10_Pos (10U)
+#define EXTI_SWIER_SWIER10_Msk (0x1U << EXTI_SWIER_SWIER10_Pos) /*!< 0x00000400 */
+#define EXTI_SWIER_SWIER10 EXTI_SWIER_SWIER10_Msk /*!< Software Interrupt on line 10 */
+#define EXTI_SWIER_SWIER11_Pos (11U)
+#define EXTI_SWIER_SWIER11_Msk (0x1U << EXTI_SWIER_SWIER11_Pos) /*!< 0x00000800 */
+#define EXTI_SWIER_SWIER11 EXTI_SWIER_SWIER11_Msk /*!< Software Interrupt on line 11 */
+#define EXTI_SWIER_SWIER12_Pos (12U)
+#define EXTI_SWIER_SWIER12_Msk (0x1U << EXTI_SWIER_SWIER12_Pos) /*!< 0x00001000 */
+#define EXTI_SWIER_SWIER12 EXTI_SWIER_SWIER12_Msk /*!< Software Interrupt on line 12 */
+#define EXTI_SWIER_SWIER13_Pos (13U)
+#define EXTI_SWIER_SWIER13_Msk (0x1U << EXTI_SWIER_SWIER13_Pos) /*!< 0x00002000 */
+#define EXTI_SWIER_SWIER13 EXTI_SWIER_SWIER13_Msk /*!< Software Interrupt on line 13 */
+#define EXTI_SWIER_SWIER14_Pos (14U)
+#define EXTI_SWIER_SWIER14_Msk (0x1U << EXTI_SWIER_SWIER14_Pos) /*!< 0x00004000 */
+#define EXTI_SWIER_SWIER14 EXTI_SWIER_SWIER14_Msk /*!< Software Interrupt on line 14 */
+#define EXTI_SWIER_SWIER15_Pos (15U)
+#define EXTI_SWIER_SWIER15_Msk (0x1U << EXTI_SWIER_SWIER15_Pos) /*!< 0x00008000 */
+#define EXTI_SWIER_SWIER15 EXTI_SWIER_SWIER15_Msk /*!< Software Interrupt on line 15 */
+#define EXTI_SWIER_SWIER16_Pos (16U)
+#define EXTI_SWIER_SWIER16_Msk (0x1U << EXTI_SWIER_SWIER16_Pos) /*!< 0x00010000 */
+#define EXTI_SWIER_SWIER16 EXTI_SWIER_SWIER16_Msk /*!< Software Interrupt on line 16 */
+#define EXTI_SWIER_SWIER17_Pos (17U)
+#define EXTI_SWIER_SWIER17_Msk (0x1U << EXTI_SWIER_SWIER17_Pos) /*!< 0x00020000 */
+#define EXTI_SWIER_SWIER17 EXTI_SWIER_SWIER17_Msk /*!< Software Interrupt on line 17 */
+#define EXTI_SWIER_SWIER18_Pos (18U)
+#define EXTI_SWIER_SWIER18_Msk (0x1U << EXTI_SWIER_SWIER18_Pos) /*!< 0x00040000 */
+#define EXTI_SWIER_SWIER18 EXTI_SWIER_SWIER18_Msk /*!< Software Interrupt on line 18 */
+#define EXTI_SWIER_SWIER19_Pos (19U)
+#define EXTI_SWIER_SWIER19_Msk (0x1U << EXTI_SWIER_SWIER19_Pos) /*!< 0x00080000 */
+#define EXTI_SWIER_SWIER19 EXTI_SWIER_SWIER19_Msk /*!< Software Interrupt on line 19 */
+
+/* References Defines */
+#define EXTI_SWIER_SWI0 EXTI_SWIER_SWIER0
+#define EXTI_SWIER_SWI1 EXTI_SWIER_SWIER1
+#define EXTI_SWIER_SWI2 EXTI_SWIER_SWIER2
+#define EXTI_SWIER_SWI3 EXTI_SWIER_SWIER3
+#define EXTI_SWIER_SWI4 EXTI_SWIER_SWIER4
+#define EXTI_SWIER_SWI5 EXTI_SWIER_SWIER5
+#define EXTI_SWIER_SWI6 EXTI_SWIER_SWIER6
+#define EXTI_SWIER_SWI7 EXTI_SWIER_SWIER7
+#define EXTI_SWIER_SWI8 EXTI_SWIER_SWIER8
+#define EXTI_SWIER_SWI9 EXTI_SWIER_SWIER9
+#define EXTI_SWIER_SWI10 EXTI_SWIER_SWIER10
+#define EXTI_SWIER_SWI11 EXTI_SWIER_SWIER11
+#define EXTI_SWIER_SWI12 EXTI_SWIER_SWIER12
+#define EXTI_SWIER_SWI13 EXTI_SWIER_SWIER13
+#define EXTI_SWIER_SWI14 EXTI_SWIER_SWIER14
+#define EXTI_SWIER_SWI15 EXTI_SWIER_SWIER15
+#define EXTI_SWIER_SWI16 EXTI_SWIER_SWIER16
+#define EXTI_SWIER_SWI17 EXTI_SWIER_SWIER17
+#define EXTI_SWIER_SWI18 EXTI_SWIER_SWIER18
+#define EXTI_SWIER_SWI19 EXTI_SWIER_SWIER19
+
+/******************* Bit definition for EXTI_PR register ********************/
+#define EXTI_PR_PR0_Pos (0U)
+#define EXTI_PR_PR0_Msk (0x1U << EXTI_PR_PR0_Pos) /*!< 0x00000001 */
+#define EXTI_PR_PR0 EXTI_PR_PR0_Msk /*!< Pending bit for line 0 */
+#define EXTI_PR_PR1_Pos (1U)
+#define EXTI_PR_PR1_Msk (0x1U << EXTI_PR_PR1_Pos) /*!< 0x00000002 */
+#define EXTI_PR_PR1 EXTI_PR_PR1_Msk /*!< Pending bit for line 1 */
+#define EXTI_PR_PR2_Pos (2U)
+#define EXTI_PR_PR2_Msk (0x1U << EXTI_PR_PR2_Pos) /*!< 0x00000004 */
+#define EXTI_PR_PR2 EXTI_PR_PR2_Msk /*!< Pending bit for line 2 */
+#define EXTI_PR_PR3_Pos (3U)
+#define EXTI_PR_PR3_Msk (0x1U << EXTI_PR_PR3_Pos) /*!< 0x00000008 */
+#define EXTI_PR_PR3 EXTI_PR_PR3_Msk /*!< Pending bit for line 3 */
+#define EXTI_PR_PR4_Pos (4U)
+#define EXTI_PR_PR4_Msk (0x1U << EXTI_PR_PR4_Pos) /*!< 0x00000010 */
+#define EXTI_PR_PR4 EXTI_PR_PR4_Msk /*!< Pending bit for line 4 */
+#define EXTI_PR_PR5_Pos (5U)
+#define EXTI_PR_PR5_Msk (0x1U << EXTI_PR_PR5_Pos) /*!< 0x00000020 */
+#define EXTI_PR_PR5 EXTI_PR_PR5_Msk /*!< Pending bit for line 5 */
+#define EXTI_PR_PR6_Pos (6U)
+#define EXTI_PR_PR6_Msk (0x1U << EXTI_PR_PR6_Pos) /*!< 0x00000040 */
+#define EXTI_PR_PR6 EXTI_PR_PR6_Msk /*!< Pending bit for line 6 */
+#define EXTI_PR_PR7_Pos (7U)
+#define EXTI_PR_PR7_Msk (0x1U << EXTI_PR_PR7_Pos) /*!< 0x00000080 */
+#define EXTI_PR_PR7 EXTI_PR_PR7_Msk /*!< Pending bit for line 7 */
+#define EXTI_PR_PR8_Pos (8U)
+#define EXTI_PR_PR8_Msk (0x1U << EXTI_PR_PR8_Pos) /*!< 0x00000100 */
+#define EXTI_PR_PR8 EXTI_PR_PR8_Msk /*!< Pending bit for line 8 */
+#define EXTI_PR_PR9_Pos (9U)
+#define EXTI_PR_PR9_Msk (0x1U << EXTI_PR_PR9_Pos) /*!< 0x00000200 */
+#define EXTI_PR_PR9 EXTI_PR_PR9_Msk /*!< Pending bit for line 9 */
+#define EXTI_PR_PR10_Pos (10U)
+#define EXTI_PR_PR10_Msk (0x1U << EXTI_PR_PR10_Pos) /*!< 0x00000400 */
+#define EXTI_PR_PR10 EXTI_PR_PR10_Msk /*!< Pending bit for line 10 */
+#define EXTI_PR_PR11_Pos (11U)
+#define EXTI_PR_PR11_Msk (0x1U << EXTI_PR_PR11_Pos) /*!< 0x00000800 */
+#define EXTI_PR_PR11 EXTI_PR_PR11_Msk /*!< Pending bit for line 11 */
+#define EXTI_PR_PR12_Pos (12U)
+#define EXTI_PR_PR12_Msk (0x1U << EXTI_PR_PR12_Pos) /*!< 0x00001000 */
+#define EXTI_PR_PR12 EXTI_PR_PR12_Msk /*!< Pending bit for line 12 */
+#define EXTI_PR_PR13_Pos (13U)
+#define EXTI_PR_PR13_Msk (0x1U << EXTI_PR_PR13_Pos) /*!< 0x00002000 */
+#define EXTI_PR_PR13 EXTI_PR_PR13_Msk /*!< Pending bit for line 13 */
+#define EXTI_PR_PR14_Pos (14U)
+#define EXTI_PR_PR14_Msk (0x1U << EXTI_PR_PR14_Pos) /*!< 0x00004000 */
+#define EXTI_PR_PR14 EXTI_PR_PR14_Msk /*!< Pending bit for line 14 */
+#define EXTI_PR_PR15_Pos (15U)
+#define EXTI_PR_PR15_Msk (0x1U << EXTI_PR_PR15_Pos) /*!< 0x00008000 */
+#define EXTI_PR_PR15 EXTI_PR_PR15_Msk /*!< Pending bit for line 15 */
+#define EXTI_PR_PR16_Pos (16U)
+#define EXTI_PR_PR16_Msk (0x1U << EXTI_PR_PR16_Pos) /*!< 0x00010000 */
+#define EXTI_PR_PR16 EXTI_PR_PR16_Msk /*!< Pending bit for line 16 */
+#define EXTI_PR_PR17_Pos (17U)
+#define EXTI_PR_PR17_Msk (0x1U << EXTI_PR_PR17_Pos) /*!< 0x00020000 */
+#define EXTI_PR_PR17 EXTI_PR_PR17_Msk /*!< Pending bit for line 17 */
+#define EXTI_PR_PR18_Pos (18U)
+#define EXTI_PR_PR18_Msk (0x1U << EXTI_PR_PR18_Pos) /*!< 0x00040000 */
+#define EXTI_PR_PR18 EXTI_PR_PR18_Msk /*!< Pending bit for line 18 */
+#define EXTI_PR_PR19_Pos (19U)
+#define EXTI_PR_PR19_Msk (0x1U << EXTI_PR_PR19_Pos) /*!< 0x00080000 */
+#define EXTI_PR_PR19 EXTI_PR_PR19_Msk /*!< Pending bit for line 19 */
+
+/* References Defines */
+#define EXTI_PR_PIF0 EXTI_PR_PR0
+#define EXTI_PR_PIF1 EXTI_PR_PR1
+#define EXTI_PR_PIF2 EXTI_PR_PR2
+#define EXTI_PR_PIF3 EXTI_PR_PR3
+#define EXTI_PR_PIF4 EXTI_PR_PR4
+#define EXTI_PR_PIF5 EXTI_PR_PR5
+#define EXTI_PR_PIF6 EXTI_PR_PR6
+#define EXTI_PR_PIF7 EXTI_PR_PR7
+#define EXTI_PR_PIF8 EXTI_PR_PR8
+#define EXTI_PR_PIF9 EXTI_PR_PR9
+#define EXTI_PR_PIF10 EXTI_PR_PR10
+#define EXTI_PR_PIF11 EXTI_PR_PR11
+#define EXTI_PR_PIF12 EXTI_PR_PR12
+#define EXTI_PR_PIF13 EXTI_PR_PR13
+#define EXTI_PR_PIF14 EXTI_PR_PR14
+#define EXTI_PR_PIF15 EXTI_PR_PR15
+#define EXTI_PR_PIF16 EXTI_PR_PR16
+#define EXTI_PR_PIF17 EXTI_PR_PR17
+#define EXTI_PR_PIF18 EXTI_PR_PR18
+#define EXTI_PR_PIF19 EXTI_PR_PR19
+
+/******************************************************************************/
+/* */
+/* DMA Controller */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for DMA_ISR register ********************/
+#define DMA_ISR_GIF1_Pos (0U)
+#define DMA_ISR_GIF1_Msk (0x1U << DMA_ISR_GIF1_Pos) /*!< 0x00000001 */
+#define DMA_ISR_GIF1 DMA_ISR_GIF1_Msk /*!< Channel 1 Global interrupt flag */
+#define DMA_ISR_TCIF1_Pos (1U)
+#define DMA_ISR_TCIF1_Msk (0x1U << DMA_ISR_TCIF1_Pos) /*!< 0x00000002 */
+#define DMA_ISR_TCIF1 DMA_ISR_TCIF1_Msk /*!< Channel 1 Transfer Complete flag */
+#define DMA_ISR_HTIF1_Pos (2U)
+#define DMA_ISR_HTIF1_Msk (0x1U << DMA_ISR_HTIF1_Pos) /*!< 0x00000004 */
+#define DMA_ISR_HTIF1 DMA_ISR_HTIF1_Msk /*!< Channel 1 Half Transfer flag */
+#define DMA_ISR_TEIF1_Pos (3U)
+#define DMA_ISR_TEIF1_Msk (0x1U << DMA_ISR_TEIF1_Pos) /*!< 0x00000008 */
+#define DMA_ISR_TEIF1 DMA_ISR_TEIF1_Msk /*!< Channel 1 Transfer Error flag */
+#define DMA_ISR_GIF2_Pos (4U)
+#define DMA_ISR_GIF2_Msk (0x1U << DMA_ISR_GIF2_Pos) /*!< 0x00000010 */
+#define DMA_ISR_GIF2 DMA_ISR_GIF2_Msk /*!< Channel 2 Global interrupt flag */
+#define DMA_ISR_TCIF2_Pos (5U)
+#define DMA_ISR_TCIF2_Msk (0x1U << DMA_ISR_TCIF2_Pos) /*!< 0x00000020 */
+#define DMA_ISR_TCIF2 DMA_ISR_TCIF2_Msk /*!< Channel 2 Transfer Complete flag */
+#define DMA_ISR_HTIF2_Pos (6U)
+#define DMA_ISR_HTIF2_Msk (0x1U << DMA_ISR_HTIF2_Pos) /*!< 0x00000040 */
+#define DMA_ISR_HTIF2 DMA_ISR_HTIF2_Msk /*!< Channel 2 Half Transfer flag */
+#define DMA_ISR_TEIF2_Pos (7U)
+#define DMA_ISR_TEIF2_Msk (0x1U << DMA_ISR_TEIF2_Pos) /*!< 0x00000080 */
+#define DMA_ISR_TEIF2 DMA_ISR_TEIF2_Msk /*!< Channel 2 Transfer Error flag */
+#define DMA_ISR_GIF3_Pos (8U)
+#define DMA_ISR_GIF3_Msk (0x1U << DMA_ISR_GIF3_Pos) /*!< 0x00000100 */
+#define DMA_ISR_GIF3 DMA_ISR_GIF3_Msk /*!< Channel 3 Global interrupt flag */
+#define DMA_ISR_TCIF3_Pos (9U)
+#define DMA_ISR_TCIF3_Msk (0x1U << DMA_ISR_TCIF3_Pos) /*!< 0x00000200 */
+#define DMA_ISR_TCIF3 DMA_ISR_TCIF3_Msk /*!< Channel 3 Transfer Complete flag */
+#define DMA_ISR_HTIF3_Pos (10U)
+#define DMA_ISR_HTIF3_Msk (0x1U << DMA_ISR_HTIF3_Pos) /*!< 0x00000400 */
+#define DMA_ISR_HTIF3 DMA_ISR_HTIF3_Msk /*!< Channel 3 Half Transfer flag */
+#define DMA_ISR_TEIF3_Pos (11U)
+#define DMA_ISR_TEIF3_Msk (0x1U << DMA_ISR_TEIF3_Pos) /*!< 0x00000800 */
+#define DMA_ISR_TEIF3 DMA_ISR_TEIF3_Msk /*!< Channel 3 Transfer Error flag */
+#define DMA_ISR_GIF4_Pos (12U)
+#define DMA_ISR_GIF4_Msk (0x1U << DMA_ISR_GIF4_Pos) /*!< 0x00001000 */
+#define DMA_ISR_GIF4 DMA_ISR_GIF4_Msk /*!< Channel 4 Global interrupt flag */
+#define DMA_ISR_TCIF4_Pos (13U)
+#define DMA_ISR_TCIF4_Msk (0x1U << DMA_ISR_TCIF4_Pos) /*!< 0x00002000 */
+#define DMA_ISR_TCIF4 DMA_ISR_TCIF4_Msk /*!< Channel 4 Transfer Complete flag */
+#define DMA_ISR_HTIF4_Pos (14U)
+#define DMA_ISR_HTIF4_Msk (0x1U << DMA_ISR_HTIF4_Pos) /*!< 0x00004000 */
+#define DMA_ISR_HTIF4 DMA_ISR_HTIF4_Msk /*!< Channel 4 Half Transfer flag */
+#define DMA_ISR_TEIF4_Pos (15U)
+#define DMA_ISR_TEIF4_Msk (0x1U << DMA_ISR_TEIF4_Pos) /*!< 0x00008000 */
+#define DMA_ISR_TEIF4 DMA_ISR_TEIF4_Msk /*!< Channel 4 Transfer Error flag */
+#define DMA_ISR_GIF5_Pos (16U)
+#define DMA_ISR_GIF5_Msk (0x1U << DMA_ISR_GIF5_Pos) /*!< 0x00010000 */
+#define DMA_ISR_GIF5 DMA_ISR_GIF5_Msk /*!< Channel 5 Global interrupt flag */
+#define DMA_ISR_TCIF5_Pos (17U)
+#define DMA_ISR_TCIF5_Msk (0x1U << DMA_ISR_TCIF5_Pos) /*!< 0x00020000 */
+#define DMA_ISR_TCIF5 DMA_ISR_TCIF5_Msk /*!< Channel 5 Transfer Complete flag */
+#define DMA_ISR_HTIF5_Pos (18U)
+#define DMA_ISR_HTIF5_Msk (0x1U << DMA_ISR_HTIF5_Pos) /*!< 0x00040000 */
+#define DMA_ISR_HTIF5 DMA_ISR_HTIF5_Msk /*!< Channel 5 Half Transfer flag */
+#define DMA_ISR_TEIF5_Pos (19U)
+#define DMA_ISR_TEIF5_Msk (0x1U << DMA_ISR_TEIF5_Pos) /*!< 0x00080000 */
+#define DMA_ISR_TEIF5 DMA_ISR_TEIF5_Msk /*!< Channel 5 Transfer Error flag */
+#define DMA_ISR_GIF6_Pos (20U)
+#define DMA_ISR_GIF6_Msk (0x1U << DMA_ISR_GIF6_Pos) /*!< 0x00100000 */
+#define DMA_ISR_GIF6 DMA_ISR_GIF6_Msk /*!< Channel 6 Global interrupt flag */
+#define DMA_ISR_TCIF6_Pos (21U)
+#define DMA_ISR_TCIF6_Msk (0x1U << DMA_ISR_TCIF6_Pos) /*!< 0x00200000 */
+#define DMA_ISR_TCIF6 DMA_ISR_TCIF6_Msk /*!< Channel 6 Transfer Complete flag */
+#define DMA_ISR_HTIF6_Pos (22U)
+#define DMA_ISR_HTIF6_Msk (0x1U << DMA_ISR_HTIF6_Pos) /*!< 0x00400000 */
+#define DMA_ISR_HTIF6 DMA_ISR_HTIF6_Msk /*!< Channel 6 Half Transfer flag */
+#define DMA_ISR_TEIF6_Pos (23U)
+#define DMA_ISR_TEIF6_Msk (0x1U << DMA_ISR_TEIF6_Pos) /*!< 0x00800000 */
+#define DMA_ISR_TEIF6 DMA_ISR_TEIF6_Msk /*!< Channel 6 Transfer Error flag */
+#define DMA_ISR_GIF7_Pos (24U)
+#define DMA_ISR_GIF7_Msk (0x1U << DMA_ISR_GIF7_Pos) /*!< 0x01000000 */
+#define DMA_ISR_GIF7 DMA_ISR_GIF7_Msk /*!< Channel 7 Global interrupt flag */
+#define DMA_ISR_TCIF7_Pos (25U)
+#define DMA_ISR_TCIF7_Msk (0x1U << DMA_ISR_TCIF7_Pos) /*!< 0x02000000 */
+#define DMA_ISR_TCIF7 DMA_ISR_TCIF7_Msk /*!< Channel 7 Transfer Complete flag */
+#define DMA_ISR_HTIF7_Pos (26U)
+#define DMA_ISR_HTIF7_Msk (0x1U << DMA_ISR_HTIF7_Pos) /*!< 0x04000000 */
+#define DMA_ISR_HTIF7 DMA_ISR_HTIF7_Msk /*!< Channel 7 Half Transfer flag */
+#define DMA_ISR_TEIF7_Pos (27U)
+#define DMA_ISR_TEIF7_Msk (0x1U << DMA_ISR_TEIF7_Pos) /*!< 0x08000000 */
+#define DMA_ISR_TEIF7 DMA_ISR_TEIF7_Msk /*!< Channel 7 Transfer Error flag */
+
+/******************* Bit definition for DMA_IFCR register *******************/
+#define DMA_IFCR_CGIF1_Pos (0U)
+#define DMA_IFCR_CGIF1_Msk (0x1U << DMA_IFCR_CGIF1_Pos) /*!< 0x00000001 */
+#define DMA_IFCR_CGIF1 DMA_IFCR_CGIF1_Msk /*!< Channel 1 Global interrupt clear */
+#define DMA_IFCR_CTCIF1_Pos (1U)
+#define DMA_IFCR_CTCIF1_Msk (0x1U << DMA_IFCR_CTCIF1_Pos) /*!< 0x00000002 */
+#define DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF1_Msk /*!< Channel 1 Transfer Complete clear */
+#define DMA_IFCR_CHTIF1_Pos (2U)
+#define DMA_IFCR_CHTIF1_Msk (0x1U << DMA_IFCR_CHTIF1_Pos) /*!< 0x00000004 */
+#define DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF1_Msk /*!< Channel 1 Half Transfer clear */
+#define DMA_IFCR_CTEIF1_Pos (3U)
+#define DMA_IFCR_CTEIF1_Msk (0x1U << DMA_IFCR_CTEIF1_Pos) /*!< 0x00000008 */
+#define DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF1_Msk /*!< Channel 1 Transfer Error clear */
+#define DMA_IFCR_CGIF2_Pos (4U)
+#define DMA_IFCR_CGIF2_Msk (0x1U << DMA_IFCR_CGIF2_Pos) /*!< 0x00000010 */
+#define DMA_IFCR_CGIF2 DMA_IFCR_CGIF2_Msk /*!< Channel 2 Global interrupt clear */
+#define DMA_IFCR_CTCIF2_Pos (5U)
+#define DMA_IFCR_CTCIF2_Msk (0x1U << DMA_IFCR_CTCIF2_Pos) /*!< 0x00000020 */
+#define DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF2_Msk /*!< Channel 2 Transfer Complete clear */
+#define DMA_IFCR_CHTIF2_Pos (6U)
+#define DMA_IFCR_CHTIF2_Msk (0x1U << DMA_IFCR_CHTIF2_Pos) /*!< 0x00000040 */
+#define DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF2_Msk /*!< Channel 2 Half Transfer clear */
+#define DMA_IFCR_CTEIF2_Pos (7U)
+#define DMA_IFCR_CTEIF2_Msk (0x1U << DMA_IFCR_CTEIF2_Pos) /*!< 0x00000080 */
+#define DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF2_Msk /*!< Channel 2 Transfer Error clear */
+#define DMA_IFCR_CGIF3_Pos (8U)
+#define DMA_IFCR_CGIF3_Msk (0x1U << DMA_IFCR_CGIF3_Pos) /*!< 0x00000100 */
+#define DMA_IFCR_CGIF3 DMA_IFCR_CGIF3_Msk /*!< Channel 3 Global interrupt clear */
+#define DMA_IFCR_CTCIF3_Pos (9U)
+#define DMA_IFCR_CTCIF3_Msk (0x1U << DMA_IFCR_CTCIF3_Pos) /*!< 0x00000200 */
+#define DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF3_Msk /*!< Channel 3 Transfer Complete clear */
+#define DMA_IFCR_CHTIF3_Pos (10U)
+#define DMA_IFCR_CHTIF3_Msk (0x1U << DMA_IFCR_CHTIF3_Pos) /*!< 0x00000400 */
+#define DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF3_Msk /*!< Channel 3 Half Transfer clear */
+#define DMA_IFCR_CTEIF3_Pos (11U)
+#define DMA_IFCR_CTEIF3_Msk (0x1U << DMA_IFCR_CTEIF3_Pos) /*!< 0x00000800 */
+#define DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF3_Msk /*!< Channel 3 Transfer Error clear */
+#define DMA_IFCR_CGIF4_Pos (12U)
+#define DMA_IFCR_CGIF4_Msk (0x1U << DMA_IFCR_CGIF4_Pos) /*!< 0x00001000 */
+#define DMA_IFCR_CGIF4 DMA_IFCR_CGIF4_Msk /*!< Channel 4 Global interrupt clear */
+#define DMA_IFCR_CTCIF4_Pos (13U)
+#define DMA_IFCR_CTCIF4_Msk (0x1U << DMA_IFCR_CTCIF4_Pos) /*!< 0x00002000 */
+#define DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF4_Msk /*!< Channel 4 Transfer Complete clear */
+#define DMA_IFCR_CHTIF4_Pos (14U)
+#define DMA_IFCR_CHTIF4_Msk (0x1U << DMA_IFCR_CHTIF4_Pos) /*!< 0x00004000 */
+#define DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF4_Msk /*!< Channel 4 Half Transfer clear */
+#define DMA_IFCR_CTEIF4_Pos (15U)
+#define DMA_IFCR_CTEIF4_Msk (0x1U << DMA_IFCR_CTEIF4_Pos) /*!< 0x00008000 */
+#define DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF4_Msk /*!< Channel 4 Transfer Error clear */
+#define DMA_IFCR_CGIF5_Pos (16U)
+#define DMA_IFCR_CGIF5_Msk (0x1U << DMA_IFCR_CGIF5_Pos) /*!< 0x00010000 */
+#define DMA_IFCR_CGIF5 DMA_IFCR_CGIF5_Msk /*!< Channel 5 Global interrupt clear */
+#define DMA_IFCR_CTCIF5_Pos (17U)
+#define DMA_IFCR_CTCIF5_Msk (0x1U << DMA_IFCR_CTCIF5_Pos) /*!< 0x00020000 */
+#define DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF5_Msk /*!< Channel 5 Transfer Complete clear */
+#define DMA_IFCR_CHTIF5_Pos (18U)
+#define DMA_IFCR_CHTIF5_Msk (0x1U << DMA_IFCR_CHTIF5_Pos) /*!< 0x00040000 */
+#define DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5_Msk /*!< Channel 5 Half Transfer clear */
+#define DMA_IFCR_CTEIF5_Pos (19U)
+#define DMA_IFCR_CTEIF5_Msk (0x1U << DMA_IFCR_CTEIF5_Pos) /*!< 0x00080000 */
+#define DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF5_Msk /*!< Channel 5 Transfer Error clear */
+#define DMA_IFCR_CGIF6_Pos (20U)
+#define DMA_IFCR_CGIF6_Msk (0x1U << DMA_IFCR_CGIF6_Pos) /*!< 0x00100000 */
+#define DMA_IFCR_CGIF6 DMA_IFCR_CGIF6_Msk /*!< Channel 6 Global interrupt clear */
+#define DMA_IFCR_CTCIF6_Pos (21U)
+#define DMA_IFCR_CTCIF6_Msk (0x1U << DMA_IFCR_CTCIF6_Pos) /*!< 0x00200000 */
+#define DMA_IFCR_CTCIF6 DMA_IFCR_CTCIF6_Msk /*!< Channel 6 Transfer Complete clear */
+#define DMA_IFCR_CHTIF6_Pos (22U)
+#define DMA_IFCR_CHTIF6_Msk (0x1U << DMA_IFCR_CHTIF6_Pos) /*!< 0x00400000 */
+#define DMA_IFCR_CHTIF6 DMA_IFCR_CHTIF6_Msk /*!< Channel 6 Half Transfer clear */
+#define DMA_IFCR_CTEIF6_Pos (23U)
+#define DMA_IFCR_CTEIF6_Msk (0x1U << DMA_IFCR_CTEIF6_Pos) /*!< 0x00800000 */
+#define DMA_IFCR_CTEIF6 DMA_IFCR_CTEIF6_Msk /*!< Channel 6 Transfer Error clear */
+#define DMA_IFCR_CGIF7_Pos (24U)
+#define DMA_IFCR_CGIF7_Msk (0x1U << DMA_IFCR_CGIF7_Pos) /*!< 0x01000000 */
+#define DMA_IFCR_CGIF7 DMA_IFCR_CGIF7_Msk /*!< Channel 7 Global interrupt clear */
+#define DMA_IFCR_CTCIF7_Pos (25U)
+#define DMA_IFCR_CTCIF7_Msk (0x1U << DMA_IFCR_CTCIF7_Pos) /*!< 0x02000000 */
+#define DMA_IFCR_CTCIF7 DMA_IFCR_CTCIF7_Msk /*!< Channel 7 Transfer Complete clear */
+#define DMA_IFCR_CHTIF7_Pos (26U)
+#define DMA_IFCR_CHTIF7_Msk (0x1U << DMA_IFCR_CHTIF7_Pos) /*!< 0x04000000 */
+#define DMA_IFCR_CHTIF7 DMA_IFCR_CHTIF7_Msk /*!< Channel 7 Half Transfer clear */
+#define DMA_IFCR_CTEIF7_Pos (27U)
+#define DMA_IFCR_CTEIF7_Msk (0x1U << DMA_IFCR_CTEIF7_Pos) /*!< 0x08000000 */
+#define DMA_IFCR_CTEIF7 DMA_IFCR_CTEIF7_Msk /*!< Channel 7 Transfer Error clear */
+
+/******************* Bit definition for DMA_CCR register *******************/
+#define DMA_CCR_EN_Pos (0U)
+#define DMA_CCR_EN_Msk (0x1U << DMA_CCR_EN_Pos) /*!< 0x00000001 */
+#define DMA_CCR_EN DMA_CCR_EN_Msk /*!< Channel enable */
+#define DMA_CCR_TCIE_Pos (1U)
+#define DMA_CCR_TCIE_Msk (0x1U << DMA_CCR_TCIE_Pos) /*!< 0x00000002 */
+#define DMA_CCR_TCIE DMA_CCR_TCIE_Msk /*!< Transfer complete interrupt enable */
+#define DMA_CCR_HTIE_Pos (2U)
+#define DMA_CCR_HTIE_Msk (0x1U << DMA_CCR_HTIE_Pos) /*!< 0x00000004 */
+#define DMA_CCR_HTIE DMA_CCR_HTIE_Msk /*!< Half Transfer interrupt enable */
+#define DMA_CCR_TEIE_Pos (3U)
+#define DMA_CCR_TEIE_Msk (0x1U << DMA_CCR_TEIE_Pos) /*!< 0x00000008 */
+#define DMA_CCR_TEIE DMA_CCR_TEIE_Msk /*!< Transfer error interrupt enable */
+#define DMA_CCR_DIR_Pos (4U)
+#define DMA_CCR_DIR_Msk (0x1U << DMA_CCR_DIR_Pos) /*!< 0x00000010 */
+#define DMA_CCR_DIR DMA_CCR_DIR_Msk /*!< Data transfer direction */
+#define DMA_CCR_CIRC_Pos (5U)
+#define DMA_CCR_CIRC_Msk (0x1U << DMA_CCR_CIRC_Pos) /*!< 0x00000020 */
+#define DMA_CCR_CIRC DMA_CCR_CIRC_Msk /*!< Circular mode */
+#define DMA_CCR_PINC_Pos (6U)
+#define DMA_CCR_PINC_Msk (0x1U << DMA_CCR_PINC_Pos) /*!< 0x00000040 */
+#define DMA_CCR_PINC DMA_CCR_PINC_Msk /*!< Peripheral increment mode */
+#define DMA_CCR_MINC_Pos (7U)
+#define DMA_CCR_MINC_Msk (0x1U << DMA_CCR_MINC_Pos) /*!< 0x00000080 */
+#define DMA_CCR_MINC DMA_CCR_MINC_Msk /*!< Memory increment mode */
+
+#define DMA_CCR_PSIZE_Pos (8U)
+#define DMA_CCR_PSIZE_Msk (0x3U << DMA_CCR_PSIZE_Pos) /*!< 0x00000300 */
+#define DMA_CCR_PSIZE DMA_CCR_PSIZE_Msk /*!< PSIZE[1:0] bits (Peripheral size) */
+#define DMA_CCR_PSIZE_0 (0x1U << DMA_CCR_PSIZE_Pos) /*!< 0x00000100 */
+#define DMA_CCR_PSIZE_1 (0x2U << DMA_CCR_PSIZE_Pos) /*!< 0x00000200 */
+
+#define DMA_CCR_MSIZE_Pos (10U)
+#define DMA_CCR_MSIZE_Msk (0x3U << DMA_CCR_MSIZE_Pos) /*!< 0x00000C00 */
+#define DMA_CCR_MSIZE DMA_CCR_MSIZE_Msk /*!< MSIZE[1:0] bits (Memory size) */
+#define DMA_CCR_MSIZE_0 (0x1U << DMA_CCR_MSIZE_Pos) /*!< 0x00000400 */
+#define DMA_CCR_MSIZE_1 (0x2U << DMA_CCR_MSIZE_Pos) /*!< 0x00000800 */
+
+#define DMA_CCR_PL_Pos (12U)
+#define DMA_CCR_PL_Msk (0x3U << DMA_CCR_PL_Pos) /*!< 0x00003000 */
+#define DMA_CCR_PL DMA_CCR_PL_Msk /*!< PL[1:0] bits(Channel Priority level) */
+#define DMA_CCR_PL_0 (0x1U << DMA_CCR_PL_Pos) /*!< 0x00001000 */
+#define DMA_CCR_PL_1 (0x2U << DMA_CCR_PL_Pos) /*!< 0x00002000 */
+
+#define DMA_CCR_MEM2MEM_Pos (14U)
+#define DMA_CCR_MEM2MEM_Msk (0x1U << DMA_CCR_MEM2MEM_Pos) /*!< 0x00004000 */
+#define DMA_CCR_MEM2MEM DMA_CCR_MEM2MEM_Msk /*!< Memory to memory mode */
+
+/****************** Bit definition for DMA_CNDTR register ******************/
+#define DMA_CNDTR_NDT_Pos (0U)
+#define DMA_CNDTR_NDT_Msk (0xFFFFU << DMA_CNDTR_NDT_Pos) /*!< 0x0000FFFF */
+#define DMA_CNDTR_NDT DMA_CNDTR_NDT_Msk /*!< Number of data to Transfer */
+
+/****************** Bit definition for DMA_CPAR register *******************/
+#define DMA_CPAR_PA_Pos (0U)
+#define DMA_CPAR_PA_Msk (0xFFFFFFFFU << DMA_CPAR_PA_Pos) /*!< 0xFFFFFFFF */
+#define DMA_CPAR_PA DMA_CPAR_PA_Msk /*!< Peripheral Address */
+
+/****************** Bit definition for DMA_CMAR register *******************/
+#define DMA_CMAR_MA_Pos (0U)
+#define DMA_CMAR_MA_Msk (0xFFFFFFFFU << DMA_CMAR_MA_Pos) /*!< 0xFFFFFFFF */
+#define DMA_CMAR_MA DMA_CMAR_MA_Msk /*!< Memory Address */
+
+/******************************************************************************/
+/* */
+/* Analog to Digital Converter (ADC) */
+/* */
+/******************************************************************************/
+
+/*
+ * @brief Specific device feature definitions (not present on all devices in the STM32F1 family)
+ */
+/* Note: No specific macro feature on this device */
+
+/******************** Bit definition for ADC_SR register ********************/
+#define ADC_SR_AWD_Pos (0U)
+#define ADC_SR_AWD_Msk (0x1U << ADC_SR_AWD_Pos) /*!< 0x00000001 */
+#define ADC_SR_AWD ADC_SR_AWD_Msk /*!< ADC analog watchdog 1 flag */
+#define ADC_SR_EOS_Pos (1U)
+#define ADC_SR_EOS_Msk (0x1U << ADC_SR_EOS_Pos) /*!< 0x00000002 */
+#define ADC_SR_EOS ADC_SR_EOS_Msk /*!< ADC group regular end of sequence conversions flag */
+#define ADC_SR_JEOS_Pos (2U)
+#define ADC_SR_JEOS_Msk (0x1U << ADC_SR_JEOS_Pos) /*!< 0x00000004 */
+#define ADC_SR_JEOS ADC_SR_JEOS_Msk /*!< ADC group injected end of sequence conversions flag */
+#define ADC_SR_JSTRT_Pos (3U)
+#define ADC_SR_JSTRT_Msk (0x1U << ADC_SR_JSTRT_Pos) /*!< 0x00000008 */
+#define ADC_SR_JSTRT ADC_SR_JSTRT_Msk /*!< ADC group injected conversion start flag */
+#define ADC_SR_STRT_Pos (4U)
+#define ADC_SR_STRT_Msk (0x1U << ADC_SR_STRT_Pos) /*!< 0x00000010 */
+#define ADC_SR_STRT ADC_SR_STRT_Msk /*!< ADC group regular conversion start flag */
+
+/* Legacy defines */
+#define ADC_SR_EOC (ADC_SR_EOS)
+#define ADC_SR_JEOC (ADC_SR_JEOS)
+
+/******************* Bit definition for ADC_CR1 register ********************/
+#define ADC_CR1_AWDCH_Pos (0U)
+#define ADC_CR1_AWDCH_Msk (0x1FU << ADC_CR1_AWDCH_Pos) /*!< 0x0000001F */
+#define ADC_CR1_AWDCH ADC_CR1_AWDCH_Msk /*!< ADC analog watchdog 1 monitored channel selection */
+#define ADC_CR1_AWDCH_0 (0x01U << ADC_CR1_AWDCH_Pos) /*!< 0x00000001 */
+#define ADC_CR1_AWDCH_1 (0x02U << ADC_CR1_AWDCH_Pos) /*!< 0x00000002 */
+#define ADC_CR1_AWDCH_2 (0x04U << ADC_CR1_AWDCH_Pos) /*!< 0x00000004 */
+#define ADC_CR1_AWDCH_3 (0x08U << ADC_CR1_AWDCH_Pos) /*!< 0x00000008 */
+#define ADC_CR1_AWDCH_4 (0x10U << ADC_CR1_AWDCH_Pos) /*!< 0x00000010 */
+
+#define ADC_CR1_EOSIE_Pos (5U)
+#define ADC_CR1_EOSIE_Msk (0x1U << ADC_CR1_EOSIE_Pos) /*!< 0x00000020 */
+#define ADC_CR1_EOSIE ADC_CR1_EOSIE_Msk /*!< ADC group regular end of sequence conversions interrupt */
+#define ADC_CR1_AWDIE_Pos (6U)
+#define ADC_CR1_AWDIE_Msk (0x1U << ADC_CR1_AWDIE_Pos) /*!< 0x00000040 */
+#define ADC_CR1_AWDIE ADC_CR1_AWDIE_Msk /*!< ADC analog watchdog 1 interrupt */
+#define ADC_CR1_JEOSIE_Pos (7U)
+#define ADC_CR1_JEOSIE_Msk (0x1U << ADC_CR1_JEOSIE_Pos) /*!< 0x00000080 */
+#define ADC_CR1_JEOSIE ADC_CR1_JEOSIE_Msk /*!< ADC group injected end of sequence conversions interrupt */
+#define ADC_CR1_SCAN_Pos (8U)
+#define ADC_CR1_SCAN_Msk (0x1U << ADC_CR1_SCAN_Pos) /*!< 0x00000100 */
+#define ADC_CR1_SCAN ADC_CR1_SCAN_Msk /*!< ADC scan mode */
+#define ADC_CR1_AWDSGL_Pos (9U)
+#define ADC_CR1_AWDSGL_Msk (0x1U << ADC_CR1_AWDSGL_Pos) /*!< 0x00000200 */
+#define ADC_CR1_AWDSGL ADC_CR1_AWDSGL_Msk /*!< ADC analog watchdog 1 monitoring a single channel or all channels */
+#define ADC_CR1_JAUTO_Pos (10U)
+#define ADC_CR1_JAUTO_Msk (0x1U << ADC_CR1_JAUTO_Pos) /*!< 0x00000400 */
+#define ADC_CR1_JAUTO ADC_CR1_JAUTO_Msk /*!< ADC group injected automatic trigger mode */
+#define ADC_CR1_DISCEN_Pos (11U)
+#define ADC_CR1_DISCEN_Msk (0x1U << ADC_CR1_DISCEN_Pos) /*!< 0x00000800 */
+#define ADC_CR1_DISCEN ADC_CR1_DISCEN_Msk /*!< ADC group regular sequencer discontinuous mode */
+#define ADC_CR1_JDISCEN_Pos (12U)
+#define ADC_CR1_JDISCEN_Msk (0x1U << ADC_CR1_JDISCEN_Pos) /*!< 0x00001000 */
+#define ADC_CR1_JDISCEN ADC_CR1_JDISCEN_Msk /*!< ADC group injected sequencer discontinuous mode */
+
+#define ADC_CR1_DISCNUM_Pos (13U)
+#define ADC_CR1_DISCNUM_Msk (0x7U << ADC_CR1_DISCNUM_Pos) /*!< 0x0000E000 */
+#define ADC_CR1_DISCNUM ADC_CR1_DISCNUM_Msk /*!< ADC group regular sequencer discontinuous number of ranks */
+#define ADC_CR1_DISCNUM_0 (0x1U << ADC_CR1_DISCNUM_Pos) /*!< 0x00002000 */
+#define ADC_CR1_DISCNUM_1 (0x2U << ADC_CR1_DISCNUM_Pos) /*!< 0x00004000 */
+#define ADC_CR1_DISCNUM_2 (0x4U << ADC_CR1_DISCNUM_Pos) /*!< 0x00008000 */
+
+#define ADC_CR1_JAWDEN_Pos (22U)
+#define ADC_CR1_JAWDEN_Msk (0x1U << ADC_CR1_JAWDEN_Pos) /*!< 0x00400000 */
+#define ADC_CR1_JAWDEN ADC_CR1_JAWDEN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group injected */
+#define ADC_CR1_AWDEN_Pos (23U)
+#define ADC_CR1_AWDEN_Msk (0x1U << ADC_CR1_AWDEN_Pos) /*!< 0x00800000 */
+#define ADC_CR1_AWDEN ADC_CR1_AWDEN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group regular */
+
+/* Legacy defines */
+#define ADC_CR1_EOCIE (ADC_CR1_EOSIE)
+#define ADC_CR1_JEOCIE (ADC_CR1_JEOSIE)
+
+/******************* Bit definition for ADC_CR2 register ********************/
+#define ADC_CR2_ADON_Pos (0U)
+#define ADC_CR2_ADON_Msk (0x1U << ADC_CR2_ADON_Pos) /*!< 0x00000001 */
+#define ADC_CR2_ADON ADC_CR2_ADON_Msk /*!< ADC enable */
+#define ADC_CR2_CONT_Pos (1U)
+#define ADC_CR2_CONT_Msk (0x1U << ADC_CR2_CONT_Pos) /*!< 0x00000002 */
+#define ADC_CR2_CONT ADC_CR2_CONT_Msk /*!< ADC group regular continuous conversion mode */
+#define ADC_CR2_CAL_Pos (2U)
+#define ADC_CR2_CAL_Msk (0x1U << ADC_CR2_CAL_Pos) /*!< 0x00000004 */
+#define ADC_CR2_CAL ADC_CR2_CAL_Msk /*!< ADC calibration start */
+#define ADC_CR2_RSTCAL_Pos (3U)
+#define ADC_CR2_RSTCAL_Msk (0x1U << ADC_CR2_RSTCAL_Pos) /*!< 0x00000008 */
+#define ADC_CR2_RSTCAL ADC_CR2_RSTCAL_Msk /*!< ADC calibration reset */
+#define ADC_CR2_DMA_Pos (8U)
+#define ADC_CR2_DMA_Msk (0x1U << ADC_CR2_DMA_Pos) /*!< 0x00000100 */
+#define ADC_CR2_DMA ADC_CR2_DMA_Msk /*!< ADC DMA transfer enable */
+#define ADC_CR2_ALIGN_Pos (11U)
+#define ADC_CR2_ALIGN_Msk (0x1U << ADC_CR2_ALIGN_Pos) /*!< 0x00000800 */
+#define ADC_CR2_ALIGN ADC_CR2_ALIGN_Msk /*!< ADC data alignement */
+
+#define ADC_CR2_JEXTSEL_Pos (12U)
+#define ADC_CR2_JEXTSEL_Msk (0x7U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00007000 */
+#define ADC_CR2_JEXTSEL ADC_CR2_JEXTSEL_Msk /*!< ADC group injected external trigger source */
+#define ADC_CR2_JEXTSEL_0 (0x1U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00001000 */
+#define ADC_CR2_JEXTSEL_1 (0x2U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00002000 */
+#define ADC_CR2_JEXTSEL_2 (0x4U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00004000 */
+
+#define ADC_CR2_JEXTTRIG_Pos (15U)
+#define ADC_CR2_JEXTTRIG_Msk (0x1U << ADC_CR2_JEXTTRIG_Pos) /*!< 0x00008000 */
+#define ADC_CR2_JEXTTRIG ADC_CR2_JEXTTRIG_Msk /*!< ADC group injected external trigger enable */
+
+#define ADC_CR2_EXTSEL_Pos (17U)
+#define ADC_CR2_EXTSEL_Msk (0x7U << ADC_CR2_EXTSEL_Pos) /*!< 0x000E0000 */
+#define ADC_CR2_EXTSEL ADC_CR2_EXTSEL_Msk /*!< ADC group regular external trigger source */
+#define ADC_CR2_EXTSEL_0 (0x1U << ADC_CR2_EXTSEL_Pos) /*!< 0x00020000 */
+#define ADC_CR2_EXTSEL_1 (0x2U << ADC_CR2_EXTSEL_Pos) /*!< 0x00040000 */
+#define ADC_CR2_EXTSEL_2 (0x4U << ADC_CR2_EXTSEL_Pos) /*!< 0x00080000 */
+
+#define ADC_CR2_EXTTRIG_Pos (20U)
+#define ADC_CR2_EXTTRIG_Msk (0x1U << ADC_CR2_EXTTRIG_Pos) /*!< 0x00100000 */
+#define ADC_CR2_EXTTRIG ADC_CR2_EXTTRIG_Msk /*!< ADC group regular external trigger enable */
+#define ADC_CR2_JSWSTART_Pos (21U)
+#define ADC_CR2_JSWSTART_Msk (0x1U << ADC_CR2_JSWSTART_Pos) /*!< 0x00200000 */
+#define ADC_CR2_JSWSTART ADC_CR2_JSWSTART_Msk /*!< ADC group injected conversion start */
+#define ADC_CR2_SWSTART_Pos (22U)
+#define ADC_CR2_SWSTART_Msk (0x1U << ADC_CR2_SWSTART_Pos) /*!< 0x00400000 */
+#define ADC_CR2_SWSTART ADC_CR2_SWSTART_Msk /*!< ADC group regular conversion start */
+#define ADC_CR2_TSVREFE_Pos (23U)
+#define ADC_CR2_TSVREFE_Msk (0x1U << ADC_CR2_TSVREFE_Pos) /*!< 0x00800000 */
+#define ADC_CR2_TSVREFE ADC_CR2_TSVREFE_Msk /*!< ADC internal path to VrefInt and temperature sensor enable */
+
+/****************** Bit definition for ADC_SMPR1 register *******************/
+#define ADC_SMPR1_SMP10_Pos (0U)
+#define ADC_SMPR1_SMP10_Msk (0x7U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000007 */
+#define ADC_SMPR1_SMP10 ADC_SMPR1_SMP10_Msk /*!< ADC channel 10 sampling time selection */
+#define ADC_SMPR1_SMP10_0 (0x1U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000001 */
+#define ADC_SMPR1_SMP10_1 (0x2U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000002 */
+#define ADC_SMPR1_SMP10_2 (0x4U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000004 */
+
+#define ADC_SMPR1_SMP11_Pos (3U)
+#define ADC_SMPR1_SMP11_Msk (0x7U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000038 */
+#define ADC_SMPR1_SMP11 ADC_SMPR1_SMP11_Msk /*!< ADC channel 11 sampling time selection */
+#define ADC_SMPR1_SMP11_0 (0x1U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000008 */
+#define ADC_SMPR1_SMP11_1 (0x2U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000010 */
+#define ADC_SMPR1_SMP11_2 (0x4U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000020 */
+
+#define ADC_SMPR1_SMP12_Pos (6U)
+#define ADC_SMPR1_SMP12_Msk (0x7U << ADC_SMPR1_SMP12_Pos) /*!< 0x000001C0 */
+#define ADC_SMPR1_SMP12 ADC_SMPR1_SMP12_Msk /*!< ADC channel 12 sampling time selection */
+#define ADC_SMPR1_SMP12_0 (0x1U << ADC_SMPR1_SMP12_Pos) /*!< 0x00000040 */
+#define ADC_SMPR1_SMP12_1 (0x2U << ADC_SMPR1_SMP12_Pos) /*!< 0x00000080 */
+#define ADC_SMPR1_SMP12_2 (0x4U << ADC_SMPR1_SMP12_Pos) /*!< 0x00000100 */
+
+#define ADC_SMPR1_SMP13_Pos (9U)
+#define ADC_SMPR1_SMP13_Msk (0x7U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000E00 */
+#define ADC_SMPR1_SMP13 ADC_SMPR1_SMP13_Msk /*!< ADC channel 13 sampling time selection */
+#define ADC_SMPR1_SMP13_0 (0x1U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000200 */
+#define ADC_SMPR1_SMP13_1 (0x2U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000400 */
+#define ADC_SMPR1_SMP13_2 (0x4U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000800 */
+
+#define ADC_SMPR1_SMP14_Pos (12U)
+#define ADC_SMPR1_SMP14_Msk (0x7U << ADC_SMPR1_SMP14_Pos) /*!< 0x00007000 */
+#define ADC_SMPR1_SMP14 ADC_SMPR1_SMP14_Msk /*!< ADC channel 14 sampling time selection */
+#define ADC_SMPR1_SMP14_0 (0x1U << ADC_SMPR1_SMP14_Pos) /*!< 0x00001000 */
+#define ADC_SMPR1_SMP14_1 (0x2U << ADC_SMPR1_SMP14_Pos) /*!< 0x00002000 */
+#define ADC_SMPR1_SMP14_2 (0x4U << ADC_SMPR1_SMP14_Pos) /*!< 0x00004000 */
+
+#define ADC_SMPR1_SMP15_Pos (15U)
+#define ADC_SMPR1_SMP15_Msk (0x7U << ADC_SMPR1_SMP15_Pos) /*!< 0x00038000 */
+#define ADC_SMPR1_SMP15 ADC_SMPR1_SMP15_Msk /*!< ADC channel 15 sampling time selection */
+#define ADC_SMPR1_SMP15_0 (0x1U << ADC_SMPR1_SMP15_Pos) /*!< 0x00008000 */
+#define ADC_SMPR1_SMP15_1 (0x2U << ADC_SMPR1_SMP15_Pos) /*!< 0x00010000 */
+#define ADC_SMPR1_SMP15_2 (0x4U << ADC_SMPR1_SMP15_Pos) /*!< 0x00020000 */
+
+#define ADC_SMPR1_SMP16_Pos (18U)
+#define ADC_SMPR1_SMP16_Msk (0x7U << ADC_SMPR1_SMP16_Pos) /*!< 0x001C0000 */
+#define ADC_SMPR1_SMP16 ADC_SMPR1_SMP16_Msk /*!< ADC channel 16 sampling time selection */
+#define ADC_SMPR1_SMP16_0 (0x1U << ADC_SMPR1_SMP16_Pos) /*!< 0x00040000 */
+#define ADC_SMPR1_SMP16_1 (0x2U << ADC_SMPR1_SMP16_Pos) /*!< 0x00080000 */
+#define ADC_SMPR1_SMP16_2 (0x4U << ADC_SMPR1_SMP16_Pos) /*!< 0x00100000 */
+
+#define ADC_SMPR1_SMP17_Pos (21U)
+#define ADC_SMPR1_SMP17_Msk (0x7U << ADC_SMPR1_SMP17_Pos) /*!< 0x00E00000 */
+#define ADC_SMPR1_SMP17 ADC_SMPR1_SMP17_Msk /*!< ADC channel 17 sampling time selection */
+#define ADC_SMPR1_SMP17_0 (0x1U << ADC_SMPR1_SMP17_Pos) /*!< 0x00200000 */
+#define ADC_SMPR1_SMP17_1 (0x2U << ADC_SMPR1_SMP17_Pos) /*!< 0x00400000 */
+#define ADC_SMPR1_SMP17_2 (0x4U << ADC_SMPR1_SMP17_Pos) /*!< 0x00800000 */
+
+/****************** Bit definition for ADC_SMPR2 register *******************/
+#define ADC_SMPR2_SMP0_Pos (0U)
+#define ADC_SMPR2_SMP0_Msk (0x7U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000007 */
+#define ADC_SMPR2_SMP0 ADC_SMPR2_SMP0_Msk /*!< ADC channel 0 sampling time selection */
+#define ADC_SMPR2_SMP0_0 (0x1U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000001 */
+#define ADC_SMPR2_SMP0_1 (0x2U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000002 */
+#define ADC_SMPR2_SMP0_2 (0x4U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000004 */
+
+#define ADC_SMPR2_SMP1_Pos (3U)
+#define ADC_SMPR2_SMP1_Msk (0x7U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000038 */
+#define ADC_SMPR2_SMP1 ADC_SMPR2_SMP1_Msk /*!< ADC channel 1 sampling time selection */
+#define ADC_SMPR2_SMP1_0 (0x1U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000008 */
+#define ADC_SMPR2_SMP1_1 (0x2U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000010 */
+#define ADC_SMPR2_SMP1_2 (0x4U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000020 */
+
+#define ADC_SMPR2_SMP2_Pos (6U)
+#define ADC_SMPR2_SMP2_Msk (0x7U << ADC_SMPR2_SMP2_Pos) /*!< 0x000001C0 */
+#define ADC_SMPR2_SMP2 ADC_SMPR2_SMP2_Msk /*!< ADC channel 2 sampling time selection */
+#define ADC_SMPR2_SMP2_0 (0x1U << ADC_SMPR2_SMP2_Pos) /*!< 0x00000040 */
+#define ADC_SMPR2_SMP2_1 (0x2U << ADC_SMPR2_SMP2_Pos) /*!< 0x00000080 */
+#define ADC_SMPR2_SMP2_2 (0x4U << ADC_SMPR2_SMP2_Pos) /*!< 0x00000100 */
+
+#define ADC_SMPR2_SMP3_Pos (9U)
+#define ADC_SMPR2_SMP3_Msk (0x7U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000E00 */
+#define ADC_SMPR2_SMP3 ADC_SMPR2_SMP3_Msk /*!< ADC channel 3 sampling time selection */
+#define ADC_SMPR2_SMP3_0 (0x1U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000200 */
+#define ADC_SMPR2_SMP3_1 (0x2U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000400 */
+#define ADC_SMPR2_SMP3_2 (0x4U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000800 */
+
+#define ADC_SMPR2_SMP4_Pos (12U)
+#define ADC_SMPR2_SMP4_Msk (0x7U << ADC_SMPR2_SMP4_Pos) /*!< 0x00007000 */
+#define ADC_SMPR2_SMP4 ADC_SMPR2_SMP4_Msk /*!< ADC channel 4 sampling time selection */
+#define ADC_SMPR2_SMP4_0 (0x1U << ADC_SMPR2_SMP4_Pos) /*!< 0x00001000 */
+#define ADC_SMPR2_SMP4_1 (0x2U << ADC_SMPR2_SMP4_Pos) /*!< 0x00002000 */
+#define ADC_SMPR2_SMP4_2 (0x4U << ADC_SMPR2_SMP4_Pos) /*!< 0x00004000 */
+
+#define ADC_SMPR2_SMP5_Pos (15U)
+#define ADC_SMPR2_SMP5_Msk (0x7U << ADC_SMPR2_SMP5_Pos) /*!< 0x00038000 */
+#define ADC_SMPR2_SMP5 ADC_SMPR2_SMP5_Msk /*!< ADC channel 5 sampling time selection */
+#define ADC_SMPR2_SMP5_0 (0x1U << ADC_SMPR2_SMP5_Pos) /*!< 0x00008000 */
+#define ADC_SMPR2_SMP5_1 (0x2U << ADC_SMPR2_SMP5_Pos) /*!< 0x00010000 */
+#define ADC_SMPR2_SMP5_2 (0x4U << ADC_SMPR2_SMP5_Pos) /*!< 0x00020000 */
+
+#define ADC_SMPR2_SMP6_Pos (18U)
+#define ADC_SMPR2_SMP6_Msk (0x7U << ADC_SMPR2_SMP6_Pos) /*!< 0x001C0000 */
+#define ADC_SMPR2_SMP6 ADC_SMPR2_SMP6_Msk /*!< ADC channel 6 sampling time selection */
+#define ADC_SMPR2_SMP6_0 (0x1U << ADC_SMPR2_SMP6_Pos) /*!< 0x00040000 */
+#define ADC_SMPR2_SMP6_1 (0x2U << ADC_SMPR2_SMP6_Pos) /*!< 0x00080000 */
+#define ADC_SMPR2_SMP6_2 (0x4U << ADC_SMPR2_SMP6_Pos) /*!< 0x00100000 */
+
+#define ADC_SMPR2_SMP7_Pos (21U)
+#define ADC_SMPR2_SMP7_Msk (0x7U << ADC_SMPR2_SMP7_Pos) /*!< 0x00E00000 */
+#define ADC_SMPR2_SMP7 ADC_SMPR2_SMP7_Msk /*!< ADC channel 7 sampling time selection */
+#define ADC_SMPR2_SMP7_0 (0x1U << ADC_SMPR2_SMP7_Pos) /*!< 0x00200000 */
+#define ADC_SMPR2_SMP7_1 (0x2U << ADC_SMPR2_SMP7_Pos) /*!< 0x00400000 */
+#define ADC_SMPR2_SMP7_2 (0x4U << ADC_SMPR2_SMP7_Pos) /*!< 0x00800000 */
+
+#define ADC_SMPR2_SMP8_Pos (24U)
+#define ADC_SMPR2_SMP8_Msk (0x7U << ADC_SMPR2_SMP8_Pos) /*!< 0x07000000 */
+#define ADC_SMPR2_SMP8 ADC_SMPR2_SMP8_Msk /*!< ADC channel 8 sampling time selection */
+#define ADC_SMPR2_SMP8_0 (0x1U << ADC_SMPR2_SMP8_Pos) /*!< 0x01000000 */
+#define ADC_SMPR2_SMP8_1 (0x2U << ADC_SMPR2_SMP8_Pos) /*!< 0x02000000 */
+#define ADC_SMPR2_SMP8_2 (0x4U << ADC_SMPR2_SMP8_Pos) /*!< 0x04000000 */
+
+#define ADC_SMPR2_SMP9_Pos (27U)
+#define ADC_SMPR2_SMP9_Msk (0x7U << ADC_SMPR2_SMP9_Pos) /*!< 0x38000000 */
+#define ADC_SMPR2_SMP9 ADC_SMPR2_SMP9_Msk /*!< ADC channel 9 sampling time selection */
+#define ADC_SMPR2_SMP9_0 (0x1U << ADC_SMPR2_SMP9_Pos) /*!< 0x08000000 */
+#define ADC_SMPR2_SMP9_1 (0x2U << ADC_SMPR2_SMP9_Pos) /*!< 0x10000000 */
+#define ADC_SMPR2_SMP9_2 (0x4U << ADC_SMPR2_SMP9_Pos) /*!< 0x20000000 */
+
+/****************** Bit definition for ADC_JOFR1 register *******************/
+#define ADC_JOFR1_JOFFSET1_Pos (0U)
+#define ADC_JOFR1_JOFFSET1_Msk (0xFFFU << ADC_JOFR1_JOFFSET1_Pos) /*!< 0x00000FFF */
+#define ADC_JOFR1_JOFFSET1 ADC_JOFR1_JOFFSET1_Msk /*!< ADC group injected sequencer rank 1 offset value */
+
+/****************** Bit definition for ADC_JOFR2 register *******************/
+#define ADC_JOFR2_JOFFSET2_Pos (0U)
+#define ADC_JOFR2_JOFFSET2_Msk (0xFFFU << ADC_JOFR2_JOFFSET2_Pos) /*!< 0x00000FFF */
+#define ADC_JOFR2_JOFFSET2 ADC_JOFR2_JOFFSET2_Msk /*!< ADC group injected sequencer rank 2 offset value */
+
+/****************** Bit definition for ADC_JOFR3 register *******************/
+#define ADC_JOFR3_JOFFSET3_Pos (0U)
+#define ADC_JOFR3_JOFFSET3_Msk (0xFFFU << ADC_JOFR3_JOFFSET3_Pos) /*!< 0x00000FFF */
+#define ADC_JOFR3_JOFFSET3 ADC_JOFR3_JOFFSET3_Msk /*!< ADC group injected sequencer rank 3 offset value */
+
+/****************** Bit definition for ADC_JOFR4 register *******************/
+#define ADC_JOFR4_JOFFSET4_Pos (0U)
+#define ADC_JOFR4_JOFFSET4_Msk (0xFFFU << ADC_JOFR4_JOFFSET4_Pos) /*!< 0x00000FFF */
+#define ADC_JOFR4_JOFFSET4 ADC_JOFR4_JOFFSET4_Msk /*!< ADC group injected sequencer rank 4 offset value */
+
+/******************* Bit definition for ADC_HTR register ********************/
+#define ADC_HTR_HT_Pos (0U)
+#define ADC_HTR_HT_Msk (0xFFFU << ADC_HTR_HT_Pos) /*!< 0x00000FFF */
+#define ADC_HTR_HT ADC_HTR_HT_Msk /*!< ADC analog watchdog 1 threshold high */
+
+/******************* Bit definition for ADC_LTR register ********************/
+#define ADC_LTR_LT_Pos (0U)
+#define ADC_LTR_LT_Msk (0xFFFU << ADC_LTR_LT_Pos) /*!< 0x00000FFF */
+#define ADC_LTR_LT ADC_LTR_LT_Msk /*!< ADC analog watchdog 1 threshold low */
+
+/******************* Bit definition for ADC_SQR1 register *******************/
+#define ADC_SQR1_SQ13_Pos (0U)
+#define ADC_SQR1_SQ13_Msk (0x1FU << ADC_SQR1_SQ13_Pos) /*!< 0x0000001F */
+#define ADC_SQR1_SQ13 ADC_SQR1_SQ13_Msk /*!< ADC group regular sequencer rank 13 */
+#define ADC_SQR1_SQ13_0 (0x01U << ADC_SQR1_SQ13_Pos) /*!< 0x00000001 */
+#define ADC_SQR1_SQ13_1 (0x02U << ADC_SQR1_SQ13_Pos) /*!< 0x00000002 */
+#define ADC_SQR1_SQ13_2 (0x04U << ADC_SQR1_SQ13_Pos) /*!< 0x00000004 */
+#define ADC_SQR1_SQ13_3 (0x08U << ADC_SQR1_SQ13_Pos) /*!< 0x00000008 */
+#define ADC_SQR1_SQ13_4 (0x10U << ADC_SQR1_SQ13_Pos) /*!< 0x00000010 */
+
+#define ADC_SQR1_SQ14_Pos (5U)
+#define ADC_SQR1_SQ14_Msk (0x1FU << ADC_SQR1_SQ14_Pos) /*!< 0x000003E0 */
+#define ADC_SQR1_SQ14 ADC_SQR1_SQ14_Msk /*!< ADC group regular sequencer rank 14 */
+#define ADC_SQR1_SQ14_0 (0x01U << ADC_SQR1_SQ14_Pos) /*!< 0x00000020 */
+#define ADC_SQR1_SQ14_1 (0x02U << ADC_SQR1_SQ14_Pos) /*!< 0x00000040 */
+#define ADC_SQR1_SQ14_2 (0x04U << ADC_SQR1_SQ14_Pos) /*!< 0x00000080 */
+#define ADC_SQR1_SQ14_3 (0x08U << ADC_SQR1_SQ14_Pos) /*!< 0x00000100 */
+#define ADC_SQR1_SQ14_4 (0x10U << ADC_SQR1_SQ14_Pos) /*!< 0x00000200 */
+
+#define ADC_SQR1_SQ15_Pos (10U)
+#define ADC_SQR1_SQ15_Msk (0x1FU << ADC_SQR1_SQ15_Pos) /*!< 0x00007C00 */
+#define ADC_SQR1_SQ15 ADC_SQR1_SQ15_Msk /*!< ADC group regular sequencer rank 15 */
+#define ADC_SQR1_SQ15_0 (0x01U << ADC_SQR1_SQ15_Pos) /*!< 0x00000400 */
+#define ADC_SQR1_SQ15_1 (0x02U << ADC_SQR1_SQ15_Pos) /*!< 0x00000800 */
+#define ADC_SQR1_SQ15_2 (0x04U << ADC_SQR1_SQ15_Pos) /*!< 0x00001000 */
+#define ADC_SQR1_SQ15_3 (0x08U << ADC_SQR1_SQ15_Pos) /*!< 0x00002000 */
+#define ADC_SQR1_SQ15_4 (0x10U << ADC_SQR1_SQ15_Pos) /*!< 0x00004000 */
+
+#define ADC_SQR1_SQ16_Pos (15U)
+#define ADC_SQR1_SQ16_Msk (0x1FU << ADC_SQR1_SQ16_Pos) /*!< 0x000F8000 */
+#define ADC_SQR1_SQ16 ADC_SQR1_SQ16_Msk /*!< ADC group regular sequencer rank 16 */
+#define ADC_SQR1_SQ16_0 (0x01U << ADC_SQR1_SQ16_Pos) /*!< 0x00008000 */
+#define ADC_SQR1_SQ16_1 (0x02U << ADC_SQR1_SQ16_Pos) /*!< 0x00010000 */
+#define ADC_SQR1_SQ16_2 (0x04U << ADC_SQR1_SQ16_Pos) /*!< 0x00020000 */
+#define ADC_SQR1_SQ16_3 (0x08U << ADC_SQR1_SQ16_Pos) /*!< 0x00040000 */
+#define ADC_SQR1_SQ16_4 (0x10U << ADC_SQR1_SQ16_Pos) /*!< 0x00080000 */
+
+#define ADC_SQR1_L_Pos (20U)
+#define ADC_SQR1_L_Msk (0xFU << ADC_SQR1_L_Pos) /*!< 0x00F00000 */
+#define ADC_SQR1_L ADC_SQR1_L_Msk /*!< ADC group regular sequencer scan length */
+#define ADC_SQR1_L_0 (0x1U << ADC_SQR1_L_Pos) /*!< 0x00100000 */
+#define ADC_SQR1_L_1 (0x2U << ADC_SQR1_L_Pos) /*!< 0x00200000 */
+#define ADC_SQR1_L_2 (0x4U << ADC_SQR1_L_Pos) /*!< 0x00400000 */
+#define ADC_SQR1_L_3 (0x8U << ADC_SQR1_L_Pos) /*!< 0x00800000 */
+
+/******************* Bit definition for ADC_SQR2 register *******************/
+#define ADC_SQR2_SQ7_Pos (0U)
+#define ADC_SQR2_SQ7_Msk (0x1FU << ADC_SQR2_SQ7_Pos) /*!< 0x0000001F */
+#define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk /*!< ADC group regular sequencer rank 7 */
+#define ADC_SQR2_SQ7_0 (0x01U << ADC_SQR2_SQ7_Pos) /*!< 0x00000001 */
+#define ADC_SQR2_SQ7_1 (0x02U << ADC_SQR2_SQ7_Pos) /*!< 0x00000002 */
+#define ADC_SQR2_SQ7_2 (0x04U << ADC_SQR2_SQ7_Pos) /*!< 0x00000004 */
+#define ADC_SQR2_SQ7_3 (0x08U << ADC_SQR2_SQ7_Pos) /*!< 0x00000008 */
+#define ADC_SQR2_SQ7_4 (0x10U << ADC_SQR2_SQ7_Pos) /*!< 0x00000010 */
+
+#define ADC_SQR2_SQ8_Pos (5U)
+#define ADC_SQR2_SQ8_Msk (0x1FU << ADC_SQR2_SQ8_Pos) /*!< 0x000003E0 */
+#define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk /*!< ADC group regular sequencer rank 8 */
+#define ADC_SQR2_SQ8_0 (0x01U << ADC_SQR2_SQ8_Pos) /*!< 0x00000020 */
+#define ADC_SQR2_SQ8_1 (0x02U << ADC_SQR2_SQ8_Pos) /*!< 0x00000040 */
+#define ADC_SQR2_SQ8_2 (0x04U << ADC_SQR2_SQ8_Pos) /*!< 0x00000080 */
+#define ADC_SQR2_SQ8_3 (0x08U << ADC_SQR2_SQ8_Pos) /*!< 0x00000100 */
+#define ADC_SQR2_SQ8_4 (0x10U << ADC_SQR2_SQ8_Pos) /*!< 0x00000200 */
+
+#define ADC_SQR2_SQ9_Pos (10U)
+#define ADC_SQR2_SQ9_Msk (0x1FU << ADC_SQR2_SQ9_Pos) /*!< 0x00007C00 */
+#define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk /*!< ADC group regular sequencer rank 9 */
+#define ADC_SQR2_SQ9_0 (0x01U << ADC_SQR2_SQ9_Pos) /*!< 0x00000400 */
+#define ADC_SQR2_SQ9_1 (0x02U << ADC_SQR2_SQ9_Pos) /*!< 0x00000800 */
+#define ADC_SQR2_SQ9_2 (0x04U << ADC_SQR2_SQ9_Pos) /*!< 0x00001000 */
+#define ADC_SQR2_SQ9_3 (0x08U << ADC_SQR2_SQ9_Pos) /*!< 0x00002000 */
+#define ADC_SQR2_SQ9_4 (0x10U << ADC_SQR2_SQ9_Pos) /*!< 0x00004000 */
+
+#define ADC_SQR2_SQ10_Pos (15U)
+#define ADC_SQR2_SQ10_Msk (0x1FU << ADC_SQR2_SQ10_Pos) /*!< 0x000F8000 */
+#define ADC_SQR2_SQ10 ADC_SQR2_SQ10_Msk /*!< ADC group regular sequencer rank 10 */
+#define ADC_SQR2_SQ10_0 (0x01U << ADC_SQR2_SQ10_Pos) /*!< 0x00008000 */
+#define ADC_SQR2_SQ10_1 (0x02U << ADC_SQR2_SQ10_Pos) /*!< 0x00010000 */
+#define ADC_SQR2_SQ10_2 (0x04U << ADC_SQR2_SQ10_Pos) /*!< 0x00020000 */
+#define ADC_SQR2_SQ10_3 (0x08U << ADC_SQR2_SQ10_Pos) /*!< 0x00040000 */
+#define ADC_SQR2_SQ10_4 (0x10U << ADC_SQR2_SQ10_Pos) /*!< 0x00080000 */
+
+#define ADC_SQR2_SQ11_Pos (20U)
+#define ADC_SQR2_SQ11_Msk (0x1FU << ADC_SQR2_SQ11_Pos) /*!< 0x01F00000 */
+#define ADC_SQR2_SQ11 ADC_SQR2_SQ11_Msk /*!< ADC group regular sequencer rank 1 */
+#define ADC_SQR2_SQ11_0 (0x01U << ADC_SQR2_SQ11_Pos) /*!< 0x00100000 */
+#define ADC_SQR2_SQ11_1 (0x02U << ADC_SQR2_SQ11_Pos) /*!< 0x00200000 */
+#define ADC_SQR2_SQ11_2 (0x04U << ADC_SQR2_SQ11_Pos) /*!< 0x00400000 */
+#define ADC_SQR2_SQ11_3 (0x08U << ADC_SQR2_SQ11_Pos) /*!< 0x00800000 */
+#define ADC_SQR2_SQ11_4 (0x10U << ADC_SQR2_SQ11_Pos) /*!< 0x01000000 */
+
+#define ADC_SQR2_SQ12_Pos (25U)
+#define ADC_SQR2_SQ12_Msk (0x1FU << ADC_SQR2_SQ12_Pos) /*!< 0x3E000000 */
+#define ADC_SQR2_SQ12 ADC_SQR2_SQ12_Msk /*!< ADC group regular sequencer rank 12 */
+#define ADC_SQR2_SQ12_0 (0x01U << ADC_SQR2_SQ12_Pos) /*!< 0x02000000 */
+#define ADC_SQR2_SQ12_1 (0x02U << ADC_SQR2_SQ12_Pos) /*!< 0x04000000 */
+#define ADC_SQR2_SQ12_2 (0x04U << ADC_SQR2_SQ12_Pos) /*!< 0x08000000 */
+#define ADC_SQR2_SQ12_3 (0x08U << ADC_SQR2_SQ12_Pos) /*!< 0x10000000 */
+#define ADC_SQR2_SQ12_4 (0x10U << ADC_SQR2_SQ12_Pos) /*!< 0x20000000 */
+
+/******************* Bit definition for ADC_SQR3 register *******************/
+#define ADC_SQR3_SQ1_Pos (0U)
+#define ADC_SQR3_SQ1_Msk (0x1FU << ADC_SQR3_SQ1_Pos) /*!< 0x0000001F */
+#define ADC_SQR3_SQ1 ADC_SQR3_SQ1_Msk /*!< ADC group regular sequencer rank 1 */
+#define ADC_SQR3_SQ1_0 (0x01U << ADC_SQR3_SQ1_Pos) /*!< 0x00000001 */
+#define ADC_SQR3_SQ1_1 (0x02U << ADC_SQR3_SQ1_Pos) /*!< 0x00000002 */
+#define ADC_SQR3_SQ1_2 (0x04U << ADC_SQR3_SQ1_Pos) /*!< 0x00000004 */
+#define ADC_SQR3_SQ1_3 (0x08U << ADC_SQR3_SQ1_Pos) /*!< 0x00000008 */
+#define ADC_SQR3_SQ1_4 (0x10U << ADC_SQR3_SQ1_Pos) /*!< 0x00000010 */
+
+#define ADC_SQR3_SQ2_Pos (5U)
+#define ADC_SQR3_SQ2_Msk (0x1FU << ADC_SQR3_SQ2_Pos) /*!< 0x000003E0 */
+#define ADC_SQR3_SQ2 ADC_SQR3_SQ2_Msk /*!< ADC group regular sequencer rank 2 */
+#define ADC_SQR3_SQ2_0 (0x01U << ADC_SQR3_SQ2_Pos) /*!< 0x00000020 */
+#define ADC_SQR3_SQ2_1 (0x02U << ADC_SQR3_SQ2_Pos) /*!< 0x00000040 */
+#define ADC_SQR3_SQ2_2 (0x04U << ADC_SQR3_SQ2_Pos) /*!< 0x00000080 */
+#define ADC_SQR3_SQ2_3 (0x08U << ADC_SQR3_SQ2_Pos) /*!< 0x00000100 */
+#define ADC_SQR3_SQ2_4 (0x10U << ADC_SQR3_SQ2_Pos) /*!< 0x00000200 */
+
+#define ADC_SQR3_SQ3_Pos (10U)
+#define ADC_SQR3_SQ3_Msk (0x1FU << ADC_SQR3_SQ3_Pos) /*!< 0x00007C00 */
+#define ADC_SQR3_SQ3 ADC_SQR3_SQ3_Msk /*!< ADC group regular sequencer rank 3 */
+#define ADC_SQR3_SQ3_0 (0x01U << ADC_SQR3_SQ3_Pos) /*!< 0x00000400 */
+#define ADC_SQR3_SQ3_1 (0x02U << ADC_SQR3_SQ3_Pos) /*!< 0x00000800 */
+#define ADC_SQR3_SQ3_2 (0x04U << ADC_SQR3_SQ3_Pos) /*!< 0x00001000 */
+#define ADC_SQR3_SQ3_3 (0x08U << ADC_SQR3_SQ3_Pos) /*!< 0x00002000 */
+#define ADC_SQR3_SQ3_4 (0x10U << ADC_SQR3_SQ3_Pos) /*!< 0x00004000 */
+
+#define ADC_SQR3_SQ4_Pos (15U)
+#define ADC_SQR3_SQ4_Msk (0x1FU << ADC_SQR3_SQ4_Pos) /*!< 0x000F8000 */
+#define ADC_SQR3_SQ4 ADC_SQR3_SQ4_Msk /*!< ADC group regular sequencer rank 4 */
+#define ADC_SQR3_SQ4_0 (0x01U << ADC_SQR3_SQ4_Pos) /*!< 0x00008000 */
+#define ADC_SQR3_SQ4_1 (0x02U << ADC_SQR3_SQ4_Pos) /*!< 0x00010000 */
+#define ADC_SQR3_SQ4_2 (0x04U << ADC_SQR3_SQ4_Pos) /*!< 0x00020000 */
+#define ADC_SQR3_SQ4_3 (0x08U << ADC_SQR3_SQ4_Pos) /*!< 0x00040000 */
+#define ADC_SQR3_SQ4_4 (0x10U << ADC_SQR3_SQ4_Pos) /*!< 0x00080000 */
+
+#define ADC_SQR3_SQ5_Pos (20U)
+#define ADC_SQR3_SQ5_Msk (0x1FU << ADC_SQR3_SQ5_Pos) /*!< 0x01F00000 */
+#define ADC_SQR3_SQ5 ADC_SQR3_SQ5_Msk /*!< ADC group regular sequencer rank 5 */
+#define ADC_SQR3_SQ5_0 (0x01U << ADC_SQR3_SQ5_Pos) /*!< 0x00100000 */
+#define ADC_SQR3_SQ5_1 (0x02U << ADC_SQR3_SQ5_Pos) /*!< 0x00200000 */
+#define ADC_SQR3_SQ5_2 (0x04U << ADC_SQR3_SQ5_Pos) /*!< 0x00400000 */
+#define ADC_SQR3_SQ5_3 (0x08U << ADC_SQR3_SQ5_Pos) /*!< 0x00800000 */
+#define ADC_SQR3_SQ5_4 (0x10U << ADC_SQR3_SQ5_Pos) /*!< 0x01000000 */
+
+#define ADC_SQR3_SQ6_Pos (25U)
+#define ADC_SQR3_SQ6_Msk (0x1FU << ADC_SQR3_SQ6_Pos) /*!< 0x3E000000 */
+#define ADC_SQR3_SQ6 ADC_SQR3_SQ6_Msk /*!< ADC group regular sequencer rank 6 */
+#define ADC_SQR3_SQ6_0 (0x01U << ADC_SQR3_SQ6_Pos) /*!< 0x02000000 */
+#define ADC_SQR3_SQ6_1 (0x02U << ADC_SQR3_SQ6_Pos) /*!< 0x04000000 */
+#define ADC_SQR3_SQ6_2 (0x04U << ADC_SQR3_SQ6_Pos) /*!< 0x08000000 */
+#define ADC_SQR3_SQ6_3 (0x08U << ADC_SQR3_SQ6_Pos) /*!< 0x10000000 */
+#define ADC_SQR3_SQ6_4 (0x10U << ADC_SQR3_SQ6_Pos) /*!< 0x20000000 */
+
+/******************* Bit definition for ADC_JSQR register *******************/
+#define ADC_JSQR_JSQ1_Pos (0U)
+#define ADC_JSQR_JSQ1_Msk (0x1FU << ADC_JSQR_JSQ1_Pos) /*!< 0x0000001F */
+#define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!< ADC group injected sequencer rank 1 */
+#define ADC_JSQR_JSQ1_0 (0x01U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000001 */
+#define ADC_JSQR_JSQ1_1 (0x02U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000002 */
+#define ADC_JSQR_JSQ1_2 (0x04U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000004 */
+#define ADC_JSQR_JSQ1_3 (0x08U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000008 */
+#define ADC_JSQR_JSQ1_4 (0x10U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000010 */
+
+#define ADC_JSQR_JSQ2_Pos (5U)
+#define ADC_JSQR_JSQ2_Msk (0x1FU << ADC_JSQR_JSQ2_Pos) /*!< 0x000003E0 */
+#define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!< ADC group injected sequencer rank 2 */
+#define ADC_JSQR_JSQ2_0 (0x01U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000020 */
+#define ADC_JSQR_JSQ2_1 (0x02U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000040 */
+#define ADC_JSQR_JSQ2_2 (0x04U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000080 */
+#define ADC_JSQR_JSQ2_3 (0x08U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000100 */
+#define ADC_JSQR_JSQ2_4 (0x10U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000200 */
+
+#define ADC_JSQR_JSQ3_Pos (10U)
+#define ADC_JSQR_JSQ3_Msk (0x1FU << ADC_JSQR_JSQ3_Pos) /*!< 0x00007C00 */
+#define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!< ADC group injected sequencer rank 3 */
+#define ADC_JSQR_JSQ3_0 (0x01U << ADC_JSQR_JSQ3_Pos) /*!< 0x00000400 */
+#define ADC_JSQR_JSQ3_1 (0x02U << ADC_JSQR_JSQ3_Pos) /*!< 0x00000800 */
+#define ADC_JSQR_JSQ3_2 (0x04U << ADC_JSQR_JSQ3_Pos) /*!< 0x00001000 */
+#define ADC_JSQR_JSQ3_3 (0x08U << ADC_JSQR_JSQ3_Pos) /*!< 0x00002000 */
+#define ADC_JSQR_JSQ3_4 (0x10U << ADC_JSQR_JSQ3_Pos) /*!< 0x00004000 */
+
+#define ADC_JSQR_JSQ4_Pos (15U)
+#define ADC_JSQR_JSQ4_Msk (0x1FU << ADC_JSQR_JSQ4_Pos) /*!< 0x000F8000 */
+#define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!< ADC group injected sequencer rank 4 */
+#define ADC_JSQR_JSQ4_0 (0x01U << ADC_JSQR_JSQ4_Pos) /*!< 0x00008000 */
+#define ADC_JSQR_JSQ4_1 (0x02U << ADC_JSQR_JSQ4_Pos) /*!< 0x00010000 */
+#define ADC_JSQR_JSQ4_2 (0x04U << ADC_JSQR_JSQ4_Pos) /*!< 0x00020000 */
+#define ADC_JSQR_JSQ4_3 (0x08U << ADC_JSQR_JSQ4_Pos) /*!< 0x00040000 */
+#define ADC_JSQR_JSQ4_4 (0x10U << ADC_JSQR_JSQ4_Pos) /*!< 0x00080000 */
+
+#define ADC_JSQR_JL_Pos (20U)
+#define ADC_JSQR_JL_Msk (0x3U << ADC_JSQR_JL_Pos) /*!< 0x00300000 */
+#define ADC_JSQR_JL ADC_JSQR_JL_Msk /*!< ADC group injected sequencer scan length */
+#define ADC_JSQR_JL_0 (0x1U << ADC_JSQR_JL_Pos) /*!< 0x00100000 */
+#define ADC_JSQR_JL_1 (0x2U << ADC_JSQR_JL_Pos) /*!< 0x00200000 */
+
+/******************* Bit definition for ADC_JDR1 register *******************/
+#define ADC_JDR1_JDATA_Pos (0U)
+#define ADC_JDR1_JDATA_Msk (0xFFFFU << ADC_JDR1_JDATA_Pos) /*!< 0x0000FFFF */
+#define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!< ADC group injected sequencer rank 1 conversion data */
+
+/******************* Bit definition for ADC_JDR2 register *******************/
+#define ADC_JDR2_JDATA_Pos (0U)
+#define ADC_JDR2_JDATA_Msk (0xFFFFU << ADC_JDR2_JDATA_Pos) /*!< 0x0000FFFF */
+#define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!< ADC group injected sequencer rank 2 conversion data */
+
+/******************* Bit definition for ADC_JDR3 register *******************/
+#define ADC_JDR3_JDATA_Pos (0U)
+#define ADC_JDR3_JDATA_Msk (0xFFFFU << ADC_JDR3_JDATA_Pos) /*!< 0x0000FFFF */
+#define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!< ADC group injected sequencer rank 3 conversion data */
+
+/******************* Bit definition for ADC_JDR4 register *******************/
+#define ADC_JDR4_JDATA_Pos (0U)
+#define ADC_JDR4_JDATA_Msk (0xFFFFU << ADC_JDR4_JDATA_Pos) /*!< 0x0000FFFF */
+#define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!< ADC group injected sequencer rank 4 conversion data */
+
+/******************** Bit definition for ADC_DR register ********************/
+#define ADC_DR_DATA_Pos (0U)
+#define ADC_DR_DATA_Msk (0xFFFFU << ADC_DR_DATA_Pos) /*!< 0x0000FFFF */
+#define ADC_DR_DATA ADC_DR_DATA_Msk /*!< ADC group regular conversion data */
+/******************************************************************************/
+/* */
+/* Digital to Analog Converter */
+/* */
+/******************************************************************************/
+
+/******************** Bit definition for DAC_CR register ********************/
+#define DAC_CR_EN1_Pos (0U)
+#define DAC_CR_EN1_Msk (0x1U << DAC_CR_EN1_Pos) /*!< 0x00000001 */
+#define DAC_CR_EN1 DAC_CR_EN1_Msk /*!< DAC channel1 enable */
+#define DAC_CR_BOFF1_Pos (1U)
+#define DAC_CR_BOFF1_Msk (0x1U << DAC_CR_BOFF1_Pos) /*!< 0x00000002 */
+#define DAC_CR_BOFF1 DAC_CR_BOFF1_Msk /*!< DAC channel1 output buffer disable */
+#define DAC_CR_TEN1_Pos (2U)
+#define DAC_CR_TEN1_Msk (0x1U << DAC_CR_TEN1_Pos) /*!< 0x00000004 */
+#define DAC_CR_TEN1 DAC_CR_TEN1_Msk /*!< DAC channel1 Trigger enable */
+
+#define DAC_CR_TSEL1_Pos (3U)
+#define DAC_CR_TSEL1_Msk (0x7U << DAC_CR_TSEL1_Pos) /*!< 0x00000038 */
+#define DAC_CR_TSEL1 DAC_CR_TSEL1_Msk /*!< TSEL1[2:0] (DAC channel1 Trigger selection) */
+#define DAC_CR_TSEL1_0 (0x1U << DAC_CR_TSEL1_Pos) /*!< 0x00000008 */
+#define DAC_CR_TSEL1_1 (0x2U << DAC_CR_TSEL1_Pos) /*!< 0x00000010 */
+#define DAC_CR_TSEL1_2 (0x4U << DAC_CR_TSEL1_Pos) /*!< 0x00000020 */
+
+#define DAC_CR_WAVE1_Pos (6U)
+#define DAC_CR_WAVE1_Msk (0x3U << DAC_CR_WAVE1_Pos) /*!< 0x000000C0 */
+#define DAC_CR_WAVE1 DAC_CR_WAVE1_Msk /*!< WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
+#define DAC_CR_WAVE1_0 (0x1U << DAC_CR_WAVE1_Pos) /*!< 0x00000040 */
+#define DAC_CR_WAVE1_1 (0x2U << DAC_CR_WAVE1_Pos) /*!< 0x00000080 */
+
+#define DAC_CR_MAMP1_Pos (8U)
+#define DAC_CR_MAMP1_Msk (0xFU << DAC_CR_MAMP1_Pos) /*!< 0x00000F00 */
+#define DAC_CR_MAMP1 DAC_CR_MAMP1_Msk /*!< MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
+#define DAC_CR_MAMP1_0 (0x1U << DAC_CR_MAMP1_Pos) /*!< 0x00000100 */
+#define DAC_CR_MAMP1_1 (0x2U << DAC_CR_MAMP1_Pos) /*!< 0x00000200 */
+#define DAC_CR_MAMP1_2 (0x4U << DAC_CR_MAMP1_Pos) /*!< 0x00000400 */
+#define DAC_CR_MAMP1_3 (0x8U << DAC_CR_MAMP1_Pos) /*!< 0x00000800 */
+
+#define DAC_CR_DMAEN1_Pos (12U)
+#define DAC_CR_DMAEN1_Msk (0x1U << DAC_CR_DMAEN1_Pos) /*!< 0x00001000 */
+#define DAC_CR_DMAEN1 DAC_CR_DMAEN1_Msk /*!< DAC channel1 DMA enable */
+#define DAC_CR_EN2_Pos (16U)
+#define DAC_CR_EN2_Msk (0x1U << DAC_CR_EN2_Pos) /*!< 0x00010000 */
+#define DAC_CR_EN2 DAC_CR_EN2_Msk /*!< DAC channel2 enable */
+#define DAC_CR_BOFF2_Pos (17U)
+#define DAC_CR_BOFF2_Msk (0x1U << DAC_CR_BOFF2_Pos) /*!< 0x00020000 */
+#define DAC_CR_BOFF2 DAC_CR_BOFF2_Msk /*!< DAC channel2 output buffer disable */
+#define DAC_CR_TEN2_Pos (18U)
+#define DAC_CR_TEN2_Msk (0x1U << DAC_CR_TEN2_Pos) /*!< 0x00040000 */
+#define DAC_CR_TEN2 DAC_CR_TEN2_Msk /*!< DAC channel2 Trigger enable */
+
+#define DAC_CR_TSEL2_Pos (19U)
+#define DAC_CR_TSEL2_Msk (0x7U << DAC_CR_TSEL2_Pos) /*!< 0x00380000 */
+#define DAC_CR_TSEL2 DAC_CR_TSEL2_Msk /*!< TSEL2[2:0] (DAC channel2 Trigger selection) */
+#define DAC_CR_TSEL2_0 (0x1U << DAC_CR_TSEL2_Pos) /*!< 0x00080000 */
+#define DAC_CR_TSEL2_1 (0x2U << DAC_CR_TSEL2_Pos) /*!< 0x00100000 */
+#define DAC_CR_TSEL2_2 (0x4U << DAC_CR_TSEL2_Pos) /*!< 0x00200000 */
+
+#define DAC_CR_WAVE2_Pos (22U)
+#define DAC_CR_WAVE2_Msk (0x3U << DAC_CR_WAVE2_Pos) /*!< 0x00C00000 */
+#define DAC_CR_WAVE2 DAC_CR_WAVE2_Msk /*!< WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
+#define DAC_CR_WAVE2_0 (0x1U << DAC_CR_WAVE2_Pos) /*!< 0x00400000 */
+#define DAC_CR_WAVE2_1 (0x2U << DAC_CR_WAVE2_Pos) /*!< 0x00800000 */
+
+#define DAC_CR_MAMP2_Pos (24U)
+#define DAC_CR_MAMP2_Msk (0xFU << DAC_CR_MAMP2_Pos) /*!< 0x0F000000 */
+#define DAC_CR_MAMP2 DAC_CR_MAMP2_Msk /*!< MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
+#define DAC_CR_MAMP2_0 (0x1U << DAC_CR_MAMP2_Pos) /*!< 0x01000000 */
+#define DAC_CR_MAMP2_1 (0x2U << DAC_CR_MAMP2_Pos) /*!< 0x02000000 */
+#define DAC_CR_MAMP2_2 (0x4U << DAC_CR_MAMP2_Pos) /*!< 0x04000000 */
+#define DAC_CR_MAMP2_3 (0x8U << DAC_CR_MAMP2_Pos) /*!< 0x08000000 */
+
+#define DAC_CR_DMAEN2_Pos (28U)
+#define DAC_CR_DMAEN2_Msk (0x1U << DAC_CR_DMAEN2_Pos) /*!< 0x10000000 */
+#define DAC_CR_DMAEN2 DAC_CR_DMAEN2_Msk /*!< DAC channel2 DMA enabled */
+
+
+/***************** Bit definition for DAC_SWTRIGR register ******************/
+#define DAC_SWTRIGR_SWTRIG1_Pos (0U)
+#define DAC_SWTRIGR_SWTRIG1_Msk (0x1U << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */
+#define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /*!< DAC channel1 software trigger */
+#define DAC_SWTRIGR_SWTRIG2_Pos (1U)
+#define DAC_SWTRIGR_SWTRIG2_Msk (0x1U << DAC_SWTRIGR_SWTRIG2_Pos) /*!< 0x00000002 */
+#define DAC_SWTRIGR_SWTRIG2 DAC_SWTRIGR_SWTRIG2_Msk /*!< DAC channel2 software trigger */
+
+/***************** Bit definition for DAC_DHR12R1 register ******************/
+#define DAC_DHR12R1_DACC1DHR_Pos (0U)
+#define DAC_DHR12R1_DACC1DHR_Msk (0xFFFU << DAC_DHR12R1_DACC1DHR_Pos) /*!< 0x00000FFF */
+#define DAC_DHR12R1_DACC1DHR DAC_DHR12R1_DACC1DHR_Msk /*!< DAC channel1 12-bit Right aligned data */
+
+/***************** Bit definition for DAC_DHR12L1 register ******************/
+#define DAC_DHR12L1_DACC1DHR_Pos (4U)
+#define DAC_DHR12L1_DACC1DHR_Msk (0xFFFU << DAC_DHR12L1_DACC1DHR_Pos) /*!< 0x0000FFF0 */
+#define DAC_DHR12L1_DACC1DHR DAC_DHR12L1_DACC1DHR_Msk /*!< DAC channel1 12-bit Left aligned data */
+
+/****************** Bit definition for DAC_DHR8R1 register ******************/
+#define DAC_DHR8R1_DACC1DHR_Pos (0U)
+#define DAC_DHR8R1_DACC1DHR_Msk (0xFFU << DAC_DHR8R1_DACC1DHR_Pos) /*!< 0x000000FF */
+#define DAC_DHR8R1_DACC1DHR DAC_DHR8R1_DACC1DHR_Msk /*!< DAC channel1 8-bit Right aligned data */
+
+/***************** Bit definition for DAC_DHR12R2 register ******************/
+#define DAC_DHR12R2_DACC2DHR_Pos (0U)
+#define DAC_DHR12R2_DACC2DHR_Msk (0xFFFU << DAC_DHR12R2_DACC2DHR_Pos) /*!< 0x00000FFF */
+#define DAC_DHR12R2_DACC2DHR DAC_DHR12R2_DACC2DHR_Msk /*!< DAC channel2 12-bit Right aligned data */
+
+/***************** Bit definition for DAC_DHR12L2 register ******************/
+#define DAC_DHR12L2_DACC2DHR_Pos (4U)
+#define DAC_DHR12L2_DACC2DHR_Msk (0xFFFU << DAC_DHR12L2_DACC2DHR_Pos) /*!< 0x0000FFF0 */
+#define DAC_DHR12L2_DACC2DHR DAC_DHR12L2_DACC2DHR_Msk /*!< DAC channel2 12-bit Left aligned data */
+
+/****************** Bit definition for DAC_DHR8R2 register ******************/
+#define DAC_DHR8R2_DACC2DHR_Pos (0U)
+#define DAC_DHR8R2_DACC2DHR_Msk (0xFFU << DAC_DHR8R2_DACC2DHR_Pos) /*!< 0x000000FF */
+#define DAC_DHR8R2_DACC2DHR DAC_DHR8R2_DACC2DHR_Msk /*!< DAC channel2 8-bit Right aligned data */
+
+/***************** Bit definition for DAC_DHR12RD register ******************/
+#define DAC_DHR12RD_DACC1DHR_Pos (0U)
+#define DAC_DHR12RD_DACC1DHR_Msk (0xFFFU << DAC_DHR12RD_DACC1DHR_Pos) /*!< 0x00000FFF */
+#define DAC_DHR12RD_DACC1DHR DAC_DHR12RD_DACC1DHR_Msk /*!< DAC channel1 12-bit Right aligned data */
+#define DAC_DHR12RD_DACC2DHR_Pos (16U)
+#define DAC_DHR12RD_DACC2DHR_Msk (0xFFFU << DAC_DHR12RD_DACC2DHR_Pos) /*!< 0x0FFF0000 */
+#define DAC_DHR12RD_DACC2DHR DAC_DHR12RD_DACC2DHR_Msk /*!< DAC channel2 12-bit Right aligned data */
+
+/***************** Bit definition for DAC_DHR12LD register ******************/
+#define DAC_DHR12LD_DACC1DHR_Pos (4U)
+#define DAC_DHR12LD_DACC1DHR_Msk (0xFFFU << DAC_DHR12LD_DACC1DHR_Pos) /*!< 0x0000FFF0 */
+#define DAC_DHR12LD_DACC1DHR DAC_DHR12LD_DACC1DHR_Msk /*!< DAC channel1 12-bit Left aligned data */
+#define DAC_DHR12LD_DACC2DHR_Pos (20U)
+#define DAC_DHR12LD_DACC2DHR_Msk (0xFFFU << DAC_DHR12LD_DACC2DHR_Pos) /*!< 0xFFF00000 */
+#define DAC_DHR12LD_DACC2DHR DAC_DHR12LD_DACC2DHR_Msk /*!< DAC channel2 12-bit Left aligned data */
+
+/****************** Bit definition for DAC_DHR8RD register ******************/
+#define DAC_DHR8RD_DACC1DHR_Pos (0U)
+#define DAC_DHR8RD_DACC1DHR_Msk (0xFFU << DAC_DHR8RD_DACC1DHR_Pos) /*!< 0x000000FF */
+#define DAC_DHR8RD_DACC1DHR DAC_DHR8RD_DACC1DHR_Msk /*!< DAC channel1 8-bit Right aligned data */
+#define DAC_DHR8RD_DACC2DHR_Pos (8U)
+#define DAC_DHR8RD_DACC2DHR_Msk (0xFFU << DAC_DHR8RD_DACC2DHR_Pos) /*!< 0x0000FF00 */
+#define DAC_DHR8RD_DACC2DHR DAC_DHR8RD_DACC2DHR_Msk /*!< DAC channel2 8-bit Right aligned data */
+
+/******************* Bit definition for DAC_DOR1 register *******************/
+#define DAC_DOR1_DACC1DOR_Pos (0U)
+#define DAC_DOR1_DACC1DOR_Msk (0xFFFU << DAC_DOR1_DACC1DOR_Pos) /*!< 0x00000FFF */
+#define DAC_DOR1_DACC1DOR DAC_DOR1_DACC1DOR_Msk /*!< DAC channel1 data output */
+
+/******************* Bit definition for DAC_DOR2 register *******************/
+#define DAC_DOR2_DACC2DOR_Pos (0U)
+#define DAC_DOR2_DACC2DOR_Msk (0xFFFU << DAC_DOR2_DACC2DOR_Pos) /*!< 0x00000FFF */
+#define DAC_DOR2_DACC2DOR DAC_DOR2_DACC2DOR_Msk /*!< DAC channel2 data output */
+
+
+
+/*****************************************************************************/
+/* */
+/* Timers (TIM) */
+/* */
+/*****************************************************************************/
+/******************* Bit definition for TIM_CR1 register *******************/
+#define TIM_CR1_CEN_Pos (0U)
+#define TIM_CR1_CEN_Msk (0x1U << TIM_CR1_CEN_Pos) /*!< 0x00000001 */
+#define TIM_CR1_CEN TIM_CR1_CEN_Msk /*!<Counter enable */
+#define TIM_CR1_UDIS_Pos (1U)
+#define TIM_CR1_UDIS_Msk (0x1U << TIM_CR1_UDIS_Pos) /*!< 0x00000002 */
+#define TIM_CR1_UDIS TIM_CR1_UDIS_Msk /*!<Update disable */
+#define TIM_CR1_URS_Pos (2U)
+#define TIM_CR1_URS_Msk (0x1U << TIM_CR1_URS_Pos) /*!< 0x00000004 */
+#define TIM_CR1_URS TIM_CR1_URS_Msk /*!<Update request source */
+#define TIM_CR1_OPM_Pos (3U)
+#define TIM_CR1_OPM_Msk (0x1U << TIM_CR1_OPM_Pos) /*!< 0x00000008 */
+#define TIM_CR1_OPM TIM_CR1_OPM_Msk /*!<One pulse mode */
+#define TIM_CR1_DIR_Pos (4U)
+#define TIM_CR1_DIR_Msk (0x1U << TIM_CR1_DIR_Pos) /*!< 0x00000010 */
+#define TIM_CR1_DIR TIM_CR1_DIR_Msk /*!<Direction */
+
+#define TIM_CR1_CMS_Pos (5U)
+#define TIM_CR1_CMS_Msk (0x3U << TIM_CR1_CMS_Pos) /*!< 0x00000060 */
+#define TIM_CR1_CMS TIM_CR1_CMS_Msk /*!<CMS[1:0] bits (Center-aligned mode selection) */
+#define TIM_CR1_CMS_0 (0x1U << TIM_CR1_CMS_Pos) /*!< 0x00000020 */
+#define TIM_CR1_CMS_1 (0x2U << TIM_CR1_CMS_Pos) /*!< 0x00000040 */
+
+#define TIM_CR1_ARPE_Pos (7U)
+#define TIM_CR1_ARPE_Msk (0x1U << TIM_CR1_ARPE_Pos) /*!< 0x00000080 */
+#define TIM_CR1_ARPE TIM_CR1_ARPE_Msk /*!<Auto-reload preload enable */
+
+#define TIM_CR1_CKD_Pos (8U)
+#define TIM_CR1_CKD_Msk (0x3U << TIM_CR1_CKD_Pos) /*!< 0x00000300 */
+#define TIM_CR1_CKD TIM_CR1_CKD_Msk /*!<CKD[1:0] bits (clock division) */
+#define TIM_CR1_CKD_0 (0x1U << TIM_CR1_CKD_Pos) /*!< 0x00000100 */
+#define TIM_CR1_CKD_1 (0x2U << TIM_CR1_CKD_Pos) /*!< 0x00000200 */
+
+/******************* Bit definition for TIM_CR2 register *******************/
+#define TIM_CR2_CCPC_Pos (0U)
+#define TIM_CR2_CCPC_Msk (0x1U << TIM_CR2_CCPC_Pos) /*!< 0x00000001 */
+#define TIM_CR2_CCPC TIM_CR2_CCPC_Msk /*!<Capture/Compare Preloaded Control */
+#define TIM_CR2_CCUS_Pos (2U)
+#define TIM_CR2_CCUS_Msk (0x1U << TIM_CR2_CCUS_Pos) /*!< 0x00000004 */
+#define TIM_CR2_CCUS TIM_CR2_CCUS_Msk /*!<Capture/Compare Control Update Selection */
+#define TIM_CR2_CCDS_Pos (3U)
+#define TIM_CR2_CCDS_Msk (0x1U << TIM_CR2_CCDS_Pos) /*!< 0x00000008 */
+#define TIM_CR2_CCDS TIM_CR2_CCDS_Msk /*!<Capture/Compare DMA Selection */
+
+#define TIM_CR2_MMS_Pos (4U)
+#define TIM_CR2_MMS_Msk (0x7U << TIM_CR2_MMS_Pos) /*!< 0x00000070 */
+#define TIM_CR2_MMS TIM_CR2_MMS_Msk /*!<MMS[2:0] bits (Master Mode Selection) */
+#define TIM_CR2_MMS_0 (0x1U << TIM_CR2_MMS_Pos) /*!< 0x00000010 */
+#define TIM_CR2_MMS_1 (0x2U << TIM_CR2_MMS_Pos) /*!< 0x00000020 */
+#define TIM_CR2_MMS_2 (0x4U << TIM_CR2_MMS_Pos) /*!< 0x00000040 */
+
+#define TIM_CR2_TI1S_Pos (7U)
+#define TIM_CR2_TI1S_Msk (0x1U << TIM_CR2_TI1S_Pos) /*!< 0x00000080 */
+#define TIM_CR2_TI1S TIM_CR2_TI1S_Msk /*!<TI1 Selection */
+#define TIM_CR2_OIS1_Pos (8U)
+#define TIM_CR2_OIS1_Msk (0x1U << TIM_CR2_OIS1_Pos) /*!< 0x00000100 */
+#define TIM_CR2_OIS1 TIM_CR2_OIS1_Msk /*!<Output Idle state 1 (OC1 output) */
+#define TIM_CR2_OIS1N_Pos (9U)
+#define TIM_CR2_OIS1N_Msk (0x1U << TIM_CR2_OIS1N_Pos) /*!< 0x00000200 */
+#define TIM_CR2_OIS1N TIM_CR2_OIS1N_Msk /*!<Output Idle state 1 (OC1N output) */
+#define TIM_CR2_OIS2_Pos (10U)
+#define TIM_CR2_OIS2_Msk (0x1U << TIM_CR2_OIS2_Pos) /*!< 0x00000400 */
+#define TIM_CR2_OIS2 TIM_CR2_OIS2_Msk /*!<Output Idle state 2 (OC2 output) */
+#define TIM_CR2_OIS2N_Pos (11U)
+#define TIM_CR2_OIS2N_Msk (0x1U << TIM_CR2_OIS2N_Pos) /*!< 0x00000800 */
+#define TIM_CR2_OIS2N TIM_CR2_OIS2N_Msk /*!<Output Idle state 2 (OC2N output) */
+#define TIM_CR2_OIS3_Pos (12U)
+#define TIM_CR2_OIS3_Msk (0x1U << TIM_CR2_OIS3_Pos) /*!< 0x00001000 */
+#define TIM_CR2_OIS3 TIM_CR2_OIS3_Msk /*!<Output Idle state 3 (OC3 output) */
+#define TIM_CR2_OIS3N_Pos (13U)
+#define TIM_CR2_OIS3N_Msk (0x1U << TIM_CR2_OIS3N_Pos) /*!< 0x00002000 */
+#define TIM_CR2_OIS3N TIM_CR2_OIS3N_Msk /*!<Output Idle state 3 (OC3N output) */
+#define TIM_CR2_OIS4_Pos (14U)
+#define TIM_CR2_OIS4_Msk (0x1U << TIM_CR2_OIS4_Pos) /*!< 0x00004000 */
+#define TIM_CR2_OIS4 TIM_CR2_OIS4_Msk /*!<Output Idle state 4 (OC4 output) */
+
+/******************* Bit definition for TIM_SMCR register ******************/
+#define TIM_SMCR_SMS_Pos (0U)
+#define TIM_SMCR_SMS_Msk (0x7U << TIM_SMCR_SMS_Pos) /*!< 0x00000007 */
+#define TIM_SMCR_SMS TIM_SMCR_SMS_Msk /*!<SMS[2:0] bits (Slave mode selection) */
+#define TIM_SMCR_SMS_0 (0x1U << TIM_SMCR_SMS_Pos) /*!< 0x00000001 */
+#define TIM_SMCR_SMS_1 (0x2U << TIM_SMCR_SMS_Pos) /*!< 0x00000002 */
+#define TIM_SMCR_SMS_2 (0x4U << TIM_SMCR_SMS_Pos) /*!< 0x00000004 */
+
+#define TIM_SMCR_OCCS_Pos (3U)
+#define TIM_SMCR_OCCS_Msk (0x1U << TIM_SMCR_OCCS_Pos) /*!< 0x00000008 */
+#define TIM_SMCR_OCCS TIM_SMCR_OCCS_Msk /*!< OCREF clear selection */
+
+#define TIM_SMCR_TS_Pos (4U)
+#define TIM_SMCR_TS_Msk (0x7U << TIM_SMCR_TS_Pos) /*!< 0x00000070 */
+#define TIM_SMCR_TS TIM_SMCR_TS_Msk /*!<TS[2:0] bits (Trigger selection) */
+#define TIM_SMCR_TS_0 (0x1U << TIM_SMCR_TS_Pos) /*!< 0x00000010 */
+#define TIM_SMCR_TS_1 (0x2U << TIM_SMCR_TS_Pos) /*!< 0x00000020 */
+#define TIM_SMCR_TS_2 (0x4U << TIM_SMCR_TS_Pos) /*!< 0x00000040 */
+
+#define TIM_SMCR_MSM_Pos (7U)
+#define TIM_SMCR_MSM_Msk (0x1U << TIM_SMCR_MSM_Pos) /*!< 0x00000080 */
+#define TIM_SMCR_MSM TIM_SMCR_MSM_Msk /*!<Master/slave mode */
+
+#define TIM_SMCR_ETF_Pos (8U)
+#define TIM_SMCR_ETF_Msk (0xFU << TIM_SMCR_ETF_Pos) /*!< 0x00000F00 */
+#define TIM_SMCR_ETF TIM_SMCR_ETF_Msk /*!<ETF[3:0] bits (External trigger filter) */
+#define TIM_SMCR_ETF_0 (0x1U << TIM_SMCR_ETF_Pos) /*!< 0x00000100 */
+#define TIM_SMCR_ETF_1 (0x2U << TIM_SMCR_ETF_Pos) /*!< 0x00000200 */
+#define TIM_SMCR_ETF_2 (0x4U << TIM_SMCR_ETF_Pos) /*!< 0x00000400 */
+#define TIM_SMCR_ETF_3 (0x8U << TIM_SMCR_ETF_Pos) /*!< 0x00000800 */
+
+#define TIM_SMCR_ETPS_Pos (12U)
+#define TIM_SMCR_ETPS_Msk (0x3U << TIM_SMCR_ETPS_Pos) /*!< 0x00003000 */
+#define TIM_SMCR_ETPS TIM_SMCR_ETPS_Msk /*!<ETPS[1:0] bits (External trigger prescaler) */
+#define TIM_SMCR_ETPS_0 (0x1U << TIM_SMCR_ETPS_Pos) /*!< 0x00001000 */
+#define TIM_SMCR_ETPS_1 (0x2U << TIM_SMCR_ETPS_Pos) /*!< 0x00002000 */
+
+#define TIM_SMCR_ECE_Pos (14U)
+#define TIM_SMCR_ECE_Msk (0x1U << TIM_SMCR_ECE_Pos) /*!< 0x00004000 */
+#define TIM_SMCR_ECE TIM_SMCR_ECE_Msk /*!<External clock enable */
+#define TIM_SMCR_ETP_Pos (15U)
+#define TIM_SMCR_ETP_Msk (0x1U << TIM_SMCR_ETP_Pos) /*!< 0x00008000 */
+#define TIM_SMCR_ETP TIM_SMCR_ETP_Msk /*!<External trigger polarity */
+
+/******************* Bit definition for TIM_DIER register ******************/
+#define TIM_DIER_UIE_Pos (0U)
+#define TIM_DIER_UIE_Msk (0x1U << TIM_DIER_UIE_Pos) /*!< 0x00000001 */
+#define TIM_DIER_UIE TIM_DIER_UIE_Msk /*!<Update interrupt enable */
+#define TIM_DIER_CC1IE_Pos (1U)
+#define TIM_DIER_CC1IE_Msk (0x1U << TIM_DIER_CC1IE_Pos) /*!< 0x00000002 */
+#define TIM_DIER_CC1IE TIM_DIER_CC1IE_Msk /*!<Capture/Compare 1 interrupt enable */
+#define TIM_DIER_CC2IE_Pos (2U)
+#define TIM_DIER_CC2IE_Msk (0x1U << TIM_DIER_CC2IE_Pos) /*!< 0x00000004 */
+#define TIM_DIER_CC2IE TIM_DIER_CC2IE_Msk /*!<Capture/Compare 2 interrupt enable */
+#define TIM_DIER_CC3IE_Pos (3U)
+#define TIM_DIER_CC3IE_Msk (0x1U << TIM_DIER_CC3IE_Pos) /*!< 0x00000008 */
+#define TIM_DIER_CC3IE TIM_DIER_CC3IE_Msk /*!<Capture/Compare 3 interrupt enable */
+#define TIM_DIER_CC4IE_Pos (4U)
+#define TIM_DIER_CC4IE_Msk (0x1U << TIM_DIER_CC4IE_Pos) /*!< 0x00000010 */
+#define TIM_DIER_CC4IE TIM_DIER_CC4IE_Msk /*!<Capture/Compare 4 interrupt enable */
+#define TIM_DIER_COMIE_Pos (5U)
+#define TIM_DIER_COMIE_Msk (0x1U << TIM_DIER_COMIE_Pos) /*!< 0x00000020 */
+#define TIM_DIER_COMIE TIM_DIER_COMIE_Msk /*!<COM interrupt enable */
+#define TIM_DIER_TIE_Pos (6U)
+#define TIM_DIER_TIE_Msk (0x1U << TIM_DIER_TIE_Pos) /*!< 0x00000040 */
+#define TIM_DIER_TIE TIM_DIER_TIE_Msk /*!<Trigger interrupt enable */
+#define TIM_DIER_BIE_Pos (7U)
+#define TIM_DIER_BIE_Msk (0x1U << TIM_DIER_BIE_Pos) /*!< 0x00000080 */
+#define TIM_DIER_BIE TIM_DIER_BIE_Msk /*!<Break interrupt enable */
+#define TIM_DIER_UDE_Pos (8U)
+#define TIM_DIER_UDE_Msk (0x1U << TIM_DIER_UDE_Pos) /*!< 0x00000100 */
+#define TIM_DIER_UDE TIM_DIER_UDE_Msk /*!<Update DMA request enable */
+#define TIM_DIER_CC1DE_Pos (9U)
+#define TIM_DIER_CC1DE_Msk (0x1U << TIM_DIER_CC1DE_Pos) /*!< 0x00000200 */
+#define TIM_DIER_CC1DE TIM_DIER_CC1DE_Msk /*!<Capture/Compare 1 DMA request enable */
+#define TIM_DIER_CC2DE_Pos (10U)
+#define TIM_DIER_CC2DE_Msk (0x1U << TIM_DIER_CC2DE_Pos) /*!< 0x00000400 */
+#define TIM_DIER_CC2DE TIM_DIER_CC2DE_Msk /*!<Capture/Compare 2 DMA request enable */
+#define TIM_DIER_CC3DE_Pos (11U)
+#define TIM_DIER_CC3DE_Msk (0x1U << TIM_DIER_CC3DE_Pos) /*!< 0x00000800 */
+#define TIM_DIER_CC3DE TIM_DIER_CC3DE_Msk /*!<Capture/Compare 3 DMA request enable */
+#define TIM_DIER_CC4DE_Pos (12U)
+#define TIM_DIER_CC4DE_Msk (0x1U << TIM_DIER_CC4DE_Pos) /*!< 0x00001000 */
+#define TIM_DIER_CC4DE TIM_DIER_CC4DE_Msk /*!<Capture/Compare 4 DMA request enable */
+#define TIM_DIER_COMDE_Pos (13U)
+#define TIM_DIER_COMDE_Msk (0x1U << TIM_DIER_COMDE_Pos) /*!< 0x00002000 */
+#define TIM_DIER_COMDE TIM_DIER_COMDE_Msk /*!<COM DMA request enable */
+#define TIM_DIER_TDE_Pos (14U)
+#define TIM_DIER_TDE_Msk (0x1U << TIM_DIER_TDE_Pos) /*!< 0x00004000 */
+#define TIM_DIER_TDE TIM_DIER_TDE_Msk /*!<Trigger DMA request enable */
+
+/******************** Bit definition for TIM_SR register *******************/
+#define TIM_SR_UIF_Pos (0U)
+#define TIM_SR_UIF_Msk (0x1U << TIM_SR_UIF_Pos) /*!< 0x00000001 */
+#define TIM_SR_UIF TIM_SR_UIF_Msk /*!<Update interrupt Flag */
+#define TIM_SR_CC1IF_Pos (1U)
+#define TIM_SR_CC1IF_Msk (0x1U << TIM_SR_CC1IF_Pos) /*!< 0x00000002 */
+#define TIM_SR_CC1IF TIM_SR_CC1IF_Msk /*!<Capture/Compare 1 interrupt Flag */
+#define TIM_SR_CC2IF_Pos (2U)
+#define TIM_SR_CC2IF_Msk (0x1U << TIM_SR_CC2IF_Pos) /*!< 0x00000004 */
+#define TIM_SR_CC2IF TIM_SR_CC2IF_Msk /*!<Capture/Compare 2 interrupt Flag */
+#define TIM_SR_CC3IF_Pos (3U)
+#define TIM_SR_CC3IF_Msk (0x1U << TIM_SR_CC3IF_Pos) /*!< 0x00000008 */
+#define TIM_SR_CC3IF TIM_SR_CC3IF_Msk /*!<Capture/Compare 3 interrupt Flag */
+#define TIM_SR_CC4IF_Pos (4U)
+#define TIM_SR_CC4IF_Msk (0x1U << TIM_SR_CC4IF_Pos) /*!< 0x00000010 */
+#define TIM_SR_CC4IF TIM_SR_CC4IF_Msk /*!<Capture/Compare 4 interrupt Flag */
+#define TIM_SR_COMIF_Pos (5U)
+#define TIM_SR_COMIF_Msk (0x1U << TIM_SR_COMIF_Pos) /*!< 0x00000020 */
+#define TIM_SR_COMIF TIM_SR_COMIF_Msk /*!<COM interrupt Flag */
+#define TIM_SR_TIF_Pos (6U)
+#define TIM_SR_TIF_Msk (0x1U << TIM_SR_TIF_Pos) /*!< 0x00000040 */
+#define TIM_SR_TIF TIM_SR_TIF_Msk /*!<Trigger interrupt Flag */
+#define TIM_SR_BIF_Pos (7U)
+#define TIM_SR_BIF_Msk (0x1U << TIM_SR_BIF_Pos) /*!< 0x00000080 */
+#define TIM_SR_BIF TIM_SR_BIF_Msk /*!<Break interrupt Flag */
+#define TIM_SR_CC1OF_Pos (9U)
+#define TIM_SR_CC1OF_Msk (0x1U << TIM_SR_CC1OF_Pos) /*!< 0x00000200 */
+#define TIM_SR_CC1OF TIM_SR_CC1OF_Msk /*!<Capture/Compare 1 Overcapture Flag */
+#define TIM_SR_CC2OF_Pos (10U)
+#define TIM_SR_CC2OF_Msk (0x1U << TIM_SR_CC2OF_Pos) /*!< 0x00000400 */
+#define TIM_SR_CC2OF TIM_SR_CC2OF_Msk /*!<Capture/Compare 2 Overcapture Flag */
+#define TIM_SR_CC3OF_Pos (11U)
+#define TIM_SR_CC3OF_Msk (0x1U << TIM_SR_CC3OF_Pos) /*!< 0x00000800 */
+#define TIM_SR_CC3OF TIM_SR_CC3OF_Msk /*!<Capture/Compare 3 Overcapture Flag */
+#define TIM_SR_CC4OF_Pos (12U)
+#define TIM_SR_CC4OF_Msk (0x1U << TIM_SR_CC4OF_Pos) /*!< 0x00001000 */
+#define TIM_SR_CC4OF TIM_SR_CC4OF_Msk /*!<Capture/Compare 4 Overcapture Flag */
+
+/******************* Bit definition for TIM_EGR register *******************/
+#define TIM_EGR_UG_Pos (0U)
+#define TIM_EGR_UG_Msk (0x1U << TIM_EGR_UG_Pos) /*!< 0x00000001 */
+#define TIM_EGR_UG TIM_EGR_UG_Msk /*!<Update Generation */
+#define TIM_EGR_CC1G_Pos (1U)
+#define TIM_EGR_CC1G_Msk (0x1U << TIM_EGR_CC1G_Pos) /*!< 0x00000002 */
+#define TIM_EGR_CC1G TIM_EGR_CC1G_Msk /*!<Capture/Compare 1 Generation */
+#define TIM_EGR_CC2G_Pos (2U)
+#define TIM_EGR_CC2G_Msk (0x1U << TIM_EGR_CC2G_Pos) /*!< 0x00000004 */
+#define TIM_EGR_CC2G TIM_EGR_CC2G_Msk /*!<Capture/Compare 2 Generation */
+#define TIM_EGR_CC3G_Pos (3U)
+#define TIM_EGR_CC3G_Msk (0x1U << TIM_EGR_CC3G_Pos) /*!< 0x00000008 */
+#define TIM_EGR_CC3G TIM_EGR_CC3G_Msk /*!<Capture/Compare 3 Generation */
+#define TIM_EGR_CC4G_Pos (4U)
+#define TIM_EGR_CC4G_Msk (0x1U << TIM_EGR_CC4G_Pos) /*!< 0x00000010 */
+#define TIM_EGR_CC4G TIM_EGR_CC4G_Msk /*!<Capture/Compare 4 Generation */
+#define TIM_EGR_COMG_Pos (5U)
+#define TIM_EGR_COMG_Msk (0x1U << TIM_EGR_COMG_Pos) /*!< 0x00000020 */
+#define TIM_EGR_COMG TIM_EGR_COMG_Msk /*!<Capture/Compare Control Update Generation */
+#define TIM_EGR_TG_Pos (6U)
+#define TIM_EGR_TG_Msk (0x1U << TIM_EGR_TG_Pos) /*!< 0x00000040 */
+#define TIM_EGR_TG TIM_EGR_TG_Msk /*!<Trigger Generation */
+#define TIM_EGR_BG_Pos (7U)
+#define TIM_EGR_BG_Msk (0x1U << TIM_EGR_BG_Pos) /*!< 0x00000080 */
+#define TIM_EGR_BG TIM_EGR_BG_Msk /*!<Break Generation */
+
+/****************** Bit definition for TIM_CCMR1 register ******************/
+#define TIM_CCMR1_CC1S_Pos (0U)
+#define TIM_CCMR1_CC1S_Msk (0x3U << TIM_CCMR1_CC1S_Pos) /*!< 0x00000003 */
+#define TIM_CCMR1_CC1S TIM_CCMR1_CC1S_Msk /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
+#define TIM_CCMR1_CC1S_0 (0x1U << TIM_CCMR1_CC1S_Pos) /*!< 0x00000001 */
+#define TIM_CCMR1_CC1S_1 (0x2U << TIM_CCMR1_CC1S_Pos) /*!< 0x00000002 */
+
+#define TIM_CCMR1_OC1FE_Pos (2U)
+#define TIM_CCMR1_OC1FE_Msk (0x1U << TIM_CCMR1_OC1FE_Pos) /*!< 0x00000004 */
+#define TIM_CCMR1_OC1FE TIM_CCMR1_OC1FE_Msk /*!<Output Compare 1 Fast enable */
+#define TIM_CCMR1_OC1PE_Pos (3U)
+#define TIM_CCMR1_OC1PE_Msk (0x1U << TIM_CCMR1_OC1PE_Pos) /*!< 0x00000008 */
+#define TIM_CCMR1_OC1PE TIM_CCMR1_OC1PE_Msk /*!<Output Compare 1 Preload enable */
+
+#define TIM_CCMR1_OC1M_Pos (4U)
+#define TIM_CCMR1_OC1M_Msk (0x7U << TIM_CCMR1_OC1M_Pos) /*!< 0x00000070 */
+#define TIM_CCMR1_OC1M TIM_CCMR1_OC1M_Msk /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
+#define TIM_CCMR1_OC1M_0 (0x1U << TIM_CCMR1_OC1M_Pos) /*!< 0x00000010 */
+#define TIM_CCMR1_OC1M_1 (0x2U << TIM_CCMR1_OC1M_Pos) /*!< 0x00000020 */
+#define TIM_CCMR1_OC1M_2 (0x4U << TIM_CCMR1_OC1M_Pos) /*!< 0x00000040 */
+
+#define TIM_CCMR1_OC1CE_Pos (7U)
+#define TIM_CCMR1_OC1CE_Msk (0x1U << TIM_CCMR1_OC1CE_Pos) /*!< 0x00000080 */
+#define TIM_CCMR1_OC1CE TIM_CCMR1_OC1CE_Msk /*!<Output Compare 1Clear Enable */
+
+#define TIM_CCMR1_CC2S_Pos (8U)
+#define TIM_CCMR1_CC2S_Msk (0x3U << TIM_CCMR1_CC2S_Pos) /*!< 0x00000300 */
+#define TIM_CCMR1_CC2S TIM_CCMR1_CC2S_Msk /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
+#define TIM_CCMR1_CC2S_0 (0x1U << TIM_CCMR1_CC2S_Pos) /*!< 0x00000100 */
+#define TIM_CCMR1_CC2S_1 (0x2U << TIM_CCMR1_CC2S_Pos) /*!< 0x00000200 */
+
+#define TIM_CCMR1_OC2FE_Pos (10U)
+#define TIM_CCMR1_OC2FE_Msk (0x1U << TIM_CCMR1_OC2FE_Pos) /*!< 0x00000400 */
+#define TIM_CCMR1_OC2FE TIM_CCMR1_OC2FE_Msk /*!<Output Compare 2 Fast enable */
+#define TIM_CCMR1_OC2PE_Pos (11U)
+#define TIM_CCMR1_OC2PE_Msk (0x1U << TIM_CCMR1_OC2PE_Pos) /*!< 0x00000800 */
+#define TIM_CCMR1_OC2PE TIM_CCMR1_OC2PE_Msk /*!<Output Compare 2 Preload enable */
+
+#define TIM_CCMR1_OC2M_Pos (12U)
+#define TIM_CCMR1_OC2M_Msk (0x7U << TIM_CCMR1_OC2M_Pos) /*!< 0x00007000 */
+#define TIM_CCMR1_OC2M TIM_CCMR1_OC2M_Msk /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
+#define TIM_CCMR1_OC2M_0 (0x1U << TIM_CCMR1_OC2M_Pos) /*!< 0x00001000 */
+#define TIM_CCMR1_OC2M_1 (0x2U << TIM_CCMR1_OC2M_Pos) /*!< 0x00002000 */
+#define TIM_CCMR1_OC2M_2 (0x4U << TIM_CCMR1_OC2M_Pos) /*!< 0x00004000 */
+
+#define TIM_CCMR1_OC2CE_Pos (15U)
+#define TIM_CCMR1_OC2CE_Msk (0x1U << TIM_CCMR1_OC2CE_Pos) /*!< 0x00008000 */
+#define TIM_CCMR1_OC2CE TIM_CCMR1_OC2CE_Msk /*!<Output Compare 2 Clear Enable */
+
+/*---------------------------------------------------------------------------*/
+
+#define TIM_CCMR1_IC1PSC_Pos (2U)
+#define TIM_CCMR1_IC1PSC_Msk (0x3U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x0000000C */
+#define TIM_CCMR1_IC1PSC TIM_CCMR1_IC1PSC_Msk /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
+#define TIM_CCMR1_IC1PSC_0 (0x1U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x00000004 */
+#define TIM_CCMR1_IC1PSC_1 (0x2U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x00000008 */
+
+#define TIM_CCMR1_IC1F_Pos (4U)
+#define TIM_CCMR1_IC1F_Msk (0xFU << TIM_CCMR1_IC1F_Pos) /*!< 0x000000F0 */
+#define TIM_CCMR1_IC1F TIM_CCMR1_IC1F_Msk /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
+#define TIM_CCMR1_IC1F_0 (0x1U << TIM_CCMR1_IC1F_Pos) /*!< 0x00000010 */
+#define TIM_CCMR1_IC1F_1 (0x2U << TIM_CCMR1_IC1F_Pos) /*!< 0x00000020 */
+#define TIM_CCMR1_IC1F_2 (0x4U << TIM_CCMR1_IC1F_Pos) /*!< 0x00000040 */
+#define TIM_CCMR1_IC1F_3 (0x8U << TIM_CCMR1_IC1F_Pos) /*!< 0x00000080 */
+
+#define TIM_CCMR1_IC2PSC_Pos (10U)
+#define TIM_CCMR1_IC2PSC_Msk (0x3U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000C00 */
+#define TIM_CCMR1_IC2PSC TIM_CCMR1_IC2PSC_Msk /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
+#define TIM_CCMR1_IC2PSC_0 (0x1U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000400 */
+#define TIM_CCMR1_IC2PSC_1 (0x2U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000800 */
+
+#define TIM_CCMR1_IC2F_Pos (12U)
+#define TIM_CCMR1_IC2F_Msk (0xFU << TIM_CCMR1_IC2F_Pos) /*!< 0x0000F000 */
+#define TIM_CCMR1_IC2F TIM_CCMR1_IC2F_Msk /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
+#define TIM_CCMR1_IC2F_0 (0x1U << TIM_CCMR1_IC2F_Pos) /*!< 0x00001000 */
+#define TIM_CCMR1_IC2F_1 (0x2U << TIM_CCMR1_IC2F_Pos) /*!< 0x00002000 */
+#define TIM_CCMR1_IC2F_2 (0x4U << TIM_CCMR1_IC2F_Pos) /*!< 0x00004000 */
+#define TIM_CCMR1_IC2F_3 (0x8U << TIM_CCMR1_IC2F_Pos) /*!< 0x00008000 */
+
+/****************** Bit definition for TIM_CCMR2 register ******************/
+#define TIM_CCMR2_CC3S_Pos (0U)
+#define TIM_CCMR2_CC3S_Msk (0x3U << TIM_CCMR2_CC3S_Pos) /*!< 0x00000003 */
+#define TIM_CCMR2_CC3S TIM_CCMR2_CC3S_Msk /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
+#define TIM_CCMR2_CC3S_0 (0x1U << TIM_CCMR2_CC3S_Pos) /*!< 0x00000001 */
+#define TIM_CCMR2_CC3S_1 (0x2U << TIM_CCMR2_CC3S_Pos) /*!< 0x00000002 */
+
+#define TIM_CCMR2_OC3FE_Pos (2U)
+#define TIM_CCMR2_OC3FE_Msk (0x1U << TIM_CCMR2_OC3FE_Pos) /*!< 0x00000004 */
+#define TIM_CCMR2_OC3FE TIM_CCMR2_OC3FE_Msk /*!<Output Compare 3 Fast enable */
+#define TIM_CCMR2_OC3PE_Pos (3U)
+#define TIM_CCMR2_OC3PE_Msk (0x1U << TIM_CCMR2_OC3PE_Pos) /*!< 0x00000008 */
+#define TIM_CCMR2_OC3PE TIM_CCMR2_OC3PE_Msk /*!<Output Compare 3 Preload enable */
+
+#define TIM_CCMR2_OC3M_Pos (4U)
+#define TIM_CCMR2_OC3M_Msk (0x7U << TIM_CCMR2_OC3M_Pos) /*!< 0x00000070 */
+#define TIM_CCMR2_OC3M TIM_CCMR2_OC3M_Msk /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
+#define TIM_CCMR2_OC3M_0 (0x1U << TIM_CCMR2_OC3M_Pos) /*!< 0x00000010 */
+#define TIM_CCMR2_OC3M_1 (0x2U << TIM_CCMR2_OC3M_Pos) /*!< 0x00000020 */
+#define TIM_CCMR2_OC3M_2 (0x4U << TIM_CCMR2_OC3M_Pos) /*!< 0x00000040 */
+
+#define TIM_CCMR2_OC3CE_Pos (7U)
+#define TIM_CCMR2_OC3CE_Msk (0x1U << TIM_CCMR2_OC3CE_Pos) /*!< 0x00000080 */
+#define TIM_CCMR2_OC3CE TIM_CCMR2_OC3CE_Msk /*!<Output Compare 3 Clear Enable */
+
+#define TIM_CCMR2_CC4S_Pos (8U)
+#define TIM_CCMR2_CC4S_Msk (0x3U << TIM_CCMR2_CC4S_Pos) /*!< 0x00000300 */
+#define TIM_CCMR2_CC4S TIM_CCMR2_CC4S_Msk /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
+#define TIM_CCMR2_CC4S_0 (0x1U << TIM_CCMR2_CC4S_Pos) /*!< 0x00000100 */
+#define TIM_CCMR2_CC4S_1 (0x2U << TIM_CCMR2_CC4S_Pos) /*!< 0x00000200 */
+
+#define TIM_CCMR2_OC4FE_Pos (10U)
+#define TIM_CCMR2_OC4FE_Msk (0x1U << TIM_CCMR2_OC4FE_Pos) /*!< 0x00000400 */
+#define TIM_CCMR2_OC4FE TIM_CCMR2_OC4FE_Msk /*!<Output Compare 4 Fast enable */
+#define TIM_CCMR2_OC4PE_Pos (11U)
+#define TIM_CCMR2_OC4PE_Msk (0x1U << TIM_CCMR2_OC4PE_Pos) /*!< 0x00000800 */
+#define TIM_CCMR2_OC4PE TIM_CCMR2_OC4PE_Msk /*!<Output Compare 4 Preload enable */
+
+#define TIM_CCMR2_OC4M_Pos (12U)
+#define TIM_CCMR2_OC4M_Msk (0x7U << TIM_CCMR2_OC4M_Pos) /*!< 0x00007000 */
+#define TIM_CCMR2_OC4M TIM_CCMR2_OC4M_Msk /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
+#define TIM_CCMR2_OC4M_0 (0x1U << TIM_CCMR2_OC4M_Pos) /*!< 0x00001000 */
+#define TIM_CCMR2_OC4M_1 (0x2U << TIM_CCMR2_OC4M_Pos) /*!< 0x00002000 */
+#define TIM_CCMR2_OC4M_2 (0x4U << TIM_CCMR2_OC4M_Pos) /*!< 0x00004000 */
+
+#define TIM_CCMR2_OC4CE_Pos (15U)
+#define TIM_CCMR2_OC4CE_Msk (0x1U << TIM_CCMR2_OC4CE_Pos) /*!< 0x00008000 */
+#define TIM_CCMR2_OC4CE TIM_CCMR2_OC4CE_Msk /*!<Output Compare 4 Clear Enable */
+
+/*---------------------------------------------------------------------------*/
+
+#define TIM_CCMR2_IC3PSC_Pos (2U)
+#define TIM_CCMR2_IC3PSC_Msk (0x3U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x0000000C */
+#define TIM_CCMR2_IC3PSC TIM_CCMR2_IC3PSC_Msk /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
+#define TIM_CCMR2_IC3PSC_0 (0x1U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x00000004 */
+#define TIM_CCMR2_IC3PSC_1 (0x2U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x00000008 */
+
+#define TIM_CCMR2_IC3F_Pos (4U)
+#define TIM_CCMR2_IC3F_Msk (0xFU << TIM_CCMR2_IC3F_Pos) /*!< 0x000000F0 */
+#define TIM_CCMR2_IC3F TIM_CCMR2_IC3F_Msk /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
+#define TIM_CCMR2_IC3F_0 (0x1U << TIM_CCMR2_IC3F_Pos) /*!< 0x00000010 */
+#define TIM_CCMR2_IC3F_1 (0x2U << TIM_CCMR2_IC3F_Pos) /*!< 0x00000020 */
+#define TIM_CCMR2_IC3F_2 (0x4U << TIM_CCMR2_IC3F_Pos) /*!< 0x00000040 */
+#define TIM_CCMR2_IC3F_3 (0x8U << TIM_CCMR2_IC3F_Pos) /*!< 0x00000080 */
+
+#define TIM_CCMR2_IC4PSC_Pos (10U)
+#define TIM_CCMR2_IC4PSC_Msk (0x3U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000C00 */
+#define TIM_CCMR2_IC4PSC TIM_CCMR2_IC4PSC_Msk /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
+#define TIM_CCMR2_IC4PSC_0 (0x1U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000400 */
+#define TIM_CCMR2_IC4PSC_1 (0x2U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000800 */
+
+#define TIM_CCMR2_IC4F_Pos (12U)
+#define TIM_CCMR2_IC4F_Msk (0xFU << TIM_CCMR2_IC4F_Pos) /*!< 0x0000F000 */
+#define TIM_CCMR2_IC4F TIM_CCMR2_IC4F_Msk /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
+#define TIM_CCMR2_IC4F_0 (0x1U << TIM_CCMR2_IC4F_Pos) /*!< 0x00001000 */
+#define TIM_CCMR2_IC4F_1 (0x2U << TIM_CCMR2_IC4F_Pos) /*!< 0x00002000 */
+#define TIM_CCMR2_IC4F_2 (0x4U << TIM_CCMR2_IC4F_Pos) /*!< 0x00004000 */
+#define TIM_CCMR2_IC4F_3 (0x8U << TIM_CCMR2_IC4F_Pos) /*!< 0x00008000 */
+
+/******************* Bit definition for TIM_CCER register ******************/
+#define TIM_CCER_CC1E_Pos (0U)
+#define TIM_CCER_CC1E_Msk (0x1U << TIM_CCER_CC1E_Pos) /*!< 0x00000001 */
+#define TIM_CCER_CC1E TIM_CCER_CC1E_Msk /*!<Capture/Compare 1 output enable */
+#define TIM_CCER_CC1P_Pos (1U)
+#define TIM_CCER_CC1P_Msk (0x1U << TIM_CCER_CC1P_Pos) /*!< 0x00000002 */
+#define TIM_CCER_CC1P TIM_CCER_CC1P_Msk /*!<Capture/Compare 1 output Polarity */
+#define TIM_CCER_CC1NE_Pos (2U)
+#define TIM_CCER_CC1NE_Msk (0x1U << TIM_CCER_CC1NE_Pos) /*!< 0x00000004 */
+#define TIM_CCER_CC1NE TIM_CCER_CC1NE_Msk /*!<Capture/Compare 1 Complementary output enable */
+#define TIM_CCER_CC1NP_Pos (3U)
+#define TIM_CCER_CC1NP_Msk (0x1U << TIM_CCER_CC1NP_Pos) /*!< 0x00000008 */
+#define TIM_CCER_CC1NP TIM_CCER_CC1NP_Msk /*!<Capture/Compare 1 Complementary output Polarity */
+#define TIM_CCER_CC2E_Pos (4U)
+#define TIM_CCER_CC2E_Msk (0x1U << TIM_CCER_CC2E_Pos) /*!< 0x00000010 */
+#define TIM_CCER_CC2E TIM_CCER_CC2E_Msk /*!<Capture/Compare 2 output enable */
+#define TIM_CCER_CC2P_Pos (5U)
+#define TIM_CCER_CC2P_Msk (0x1U << TIM_CCER_CC2P_Pos) /*!< 0x00000020 */
+#define TIM_CCER_CC2P TIM_CCER_CC2P_Msk /*!<Capture/Compare 2 output Polarity */
+#define TIM_CCER_CC2NE_Pos (6U)
+#define TIM_CCER_CC2NE_Msk (0x1U << TIM_CCER_CC2NE_Pos) /*!< 0x00000040 */
+#define TIM_CCER_CC2NE TIM_CCER_CC2NE_Msk /*!<Capture/Compare 2 Complementary output enable */
+#define TIM_CCER_CC2NP_Pos (7U)
+#define TIM_CCER_CC2NP_Msk (0x1U << TIM_CCER_CC2NP_Pos) /*!< 0x00000080 */
+#define TIM_CCER_CC2NP TIM_CCER_CC2NP_Msk /*!<Capture/Compare 2 Complementary output Polarity */
+#define TIM_CCER_CC3E_Pos (8U)
+#define TIM_CCER_CC3E_Msk (0x1U << TIM_CCER_CC3E_Pos) /*!< 0x00000100 */
+#define TIM_CCER_CC3E TIM_CCER_CC3E_Msk /*!<Capture/Compare 3 output enable */
+#define TIM_CCER_CC3P_Pos (9U)
+#define TIM_CCER_CC3P_Msk (0x1U << TIM_CCER_CC3P_Pos) /*!< 0x00000200 */
+#define TIM_CCER_CC3P TIM_CCER_CC3P_Msk /*!<Capture/Compare 3 output Polarity */
+#define TIM_CCER_CC3NE_Pos (10U)
+#define TIM_CCER_CC3NE_Msk (0x1U << TIM_CCER_CC3NE_Pos) /*!< 0x00000400 */
+#define TIM_CCER_CC3NE TIM_CCER_CC3NE_Msk /*!<Capture/Compare 3 Complementary output enable */
+#define TIM_CCER_CC3NP_Pos (11U)
+#define TIM_CCER_CC3NP_Msk (0x1U << TIM_CCER_CC3NP_Pos) /*!< 0x00000800 */
+#define TIM_CCER_CC3NP TIM_CCER_CC3NP_Msk /*!<Capture/Compare 3 Complementary output Polarity */
+#define TIM_CCER_CC4E_Pos (12U)
+#define TIM_CCER_CC4E_Msk (0x1U << TIM_CCER_CC4E_Pos) /*!< 0x00001000 */
+#define TIM_CCER_CC4E TIM_CCER_CC4E_Msk /*!<Capture/Compare 4 output enable */
+#define TIM_CCER_CC4P_Pos (13U)
+#define TIM_CCER_CC4P_Msk (0x1U << TIM_CCER_CC4P_Pos) /*!< 0x00002000 */
+#define TIM_CCER_CC4P TIM_CCER_CC4P_Msk /*!<Capture/Compare 4 output Polarity */
+#define TIM_CCER_CC4NP_Pos (15U)
+#define TIM_CCER_CC4NP_Msk (0x1U << TIM_CCER_CC4NP_Pos) /*!< 0x00008000 */
+#define TIM_CCER_CC4NP TIM_CCER_CC4NP_Msk /*!<Capture/Compare 4 Complementary output Polarity */
+
+/******************* Bit definition for TIM_CNT register *******************/
+#define TIM_CNT_CNT_Pos (0U)
+#define TIM_CNT_CNT_Msk (0xFFFFFFFFU << TIM_CNT_CNT_Pos) /*!< 0xFFFFFFFF */
+#define TIM_CNT_CNT TIM_CNT_CNT_Msk /*!<Counter Value */
+
+/******************* Bit definition for TIM_PSC register *******************/
+#define TIM_PSC_PSC_Pos (0U)
+#define TIM_PSC_PSC_Msk (0xFFFFU << TIM_PSC_PSC_Pos) /*!< 0x0000FFFF */
+#define TIM_PSC_PSC TIM_PSC_PSC_Msk /*!<Prescaler Value */
+
+/******************* Bit definition for TIM_ARR register *******************/
+#define TIM_ARR_ARR_Pos (0U)
+#define TIM_ARR_ARR_Msk (0xFFFFFFFFU << TIM_ARR_ARR_Pos) /*!< 0xFFFFFFFF */
+#define TIM_ARR_ARR TIM_ARR_ARR_Msk /*!<actual auto-reload Value */
+
+/******************* Bit definition for TIM_RCR register *******************/
+#define TIM_RCR_REP_Pos (0U)
+#define TIM_RCR_REP_Msk (0xFFU << TIM_RCR_REP_Pos) /*!< 0x000000FF */
+#define TIM_RCR_REP TIM_RCR_REP_Msk /*!<Repetition Counter Value */
+
+/******************* Bit definition for TIM_CCR1 register ******************/
+#define TIM_CCR1_CCR1_Pos (0U)
+#define TIM_CCR1_CCR1_Msk (0xFFFFU << TIM_CCR1_CCR1_Pos) /*!< 0x0000FFFF */
+#define TIM_CCR1_CCR1 TIM_CCR1_CCR1_Msk /*!<Capture/Compare 1 Value */
+
+/******************* Bit definition for TIM_CCR2 register ******************/
+#define TIM_CCR2_CCR2_Pos (0U)
+#define TIM_CCR2_CCR2_Msk (0xFFFFU << TIM_CCR2_CCR2_Pos) /*!< 0x0000FFFF */
+#define TIM_CCR2_CCR2 TIM_CCR2_CCR2_Msk /*!<Capture/Compare 2 Value */
+
+/******************* Bit definition for TIM_CCR3 register ******************/
+#define TIM_CCR3_CCR3_Pos (0U)
+#define TIM_CCR3_CCR3_Msk (0xFFFFU << TIM_CCR3_CCR3_Pos) /*!< 0x0000FFFF */
+#define TIM_CCR3_CCR3 TIM_CCR3_CCR3_Msk /*!<Capture/Compare 3 Value */
+
+/******************* Bit definition for TIM_CCR4 register ******************/
+#define TIM_CCR4_CCR4_Pos (0U)
+#define TIM_CCR4_CCR4_Msk (0xFFFFU << TIM_CCR4_CCR4_Pos) /*!< 0x0000FFFF */
+#define TIM_CCR4_CCR4 TIM_CCR4_CCR4_Msk /*!<Capture/Compare 4 Value */
+
+/******************* Bit definition for TIM_BDTR register ******************/
+#define TIM_BDTR_DTG_Pos (0U)
+#define TIM_BDTR_DTG_Msk (0xFFU << TIM_BDTR_DTG_Pos) /*!< 0x000000FF */
+#define TIM_BDTR_DTG TIM_BDTR_DTG_Msk /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
+#define TIM_BDTR_DTG_0 (0x01U << TIM_BDTR_DTG_Pos) /*!< 0x00000001 */
+#define TIM_BDTR_DTG_1 (0x02U << TIM_BDTR_DTG_Pos) /*!< 0x00000002 */
+#define TIM_BDTR_DTG_2 (0x04U << TIM_BDTR_DTG_Pos) /*!< 0x00000004 */
+#define TIM_BDTR_DTG_3 (0x08U << TIM_BDTR_DTG_Pos) /*!< 0x00000008 */
+#define TIM_BDTR_DTG_4 (0x10U << TIM_BDTR_DTG_Pos) /*!< 0x00000010 */
+#define TIM_BDTR_DTG_5 (0x20U << TIM_BDTR_DTG_Pos) /*!< 0x00000020 */
+#define TIM_BDTR_DTG_6 (0x40U << TIM_BDTR_DTG_Pos) /*!< 0x00000040 */
+#define TIM_BDTR_DTG_7 (0x80U << TIM_BDTR_DTG_Pos) /*!< 0x00000080 */
+
+#define TIM_BDTR_LOCK_Pos (8U)
+#define TIM_BDTR_LOCK_Msk (0x3U << TIM_BDTR_LOCK_Pos) /*!< 0x00000300 */
+#define TIM_BDTR_LOCK TIM_BDTR_LOCK_Msk /*!<LOCK[1:0] bits (Lock Configuration) */
+#define TIM_BDTR_LOCK_0 (0x1U << TIM_BDTR_LOCK_Pos) /*!< 0x00000100 */
+#define TIM_BDTR_LOCK_1 (0x2U << TIM_BDTR_LOCK_Pos) /*!< 0x00000200 */
+
+#define TIM_BDTR_OSSI_Pos (10U)
+#define TIM_BDTR_OSSI_Msk (0x1U << TIM_BDTR_OSSI_Pos) /*!< 0x00000400 */
+#define TIM_BDTR_OSSI TIM_BDTR_OSSI_Msk /*!<Off-State Selection for Idle mode */
+#define TIM_BDTR_OSSR_Pos (11U)
+#define TIM_BDTR_OSSR_Msk (0x1U << TIM_BDTR_OSSR_Pos) /*!< 0x00000800 */
+#define TIM_BDTR_OSSR TIM_BDTR_OSSR_Msk /*!<Off-State Selection for Run mode */
+#define TIM_BDTR_BKE_Pos (12U)
+#define TIM_BDTR_BKE_Msk (0x1U << TIM_BDTR_BKE_Pos) /*!< 0x00001000 */
+#define TIM_BDTR_BKE TIM_BDTR_BKE_Msk /*!<Break enable */
+#define TIM_BDTR_BKP_Pos (13U)
+#define TIM_BDTR_BKP_Msk (0x1U << TIM_BDTR_BKP_Pos) /*!< 0x00002000 */
+#define TIM_BDTR_BKP TIM_BDTR_BKP_Msk /*!<Break Polarity */
+#define TIM_BDTR_AOE_Pos (14U)
+#define TIM_BDTR_AOE_Msk (0x1U << TIM_BDTR_AOE_Pos) /*!< 0x00004000 */
+#define TIM_BDTR_AOE TIM_BDTR_AOE_Msk /*!<Automatic Output enable */
+#define TIM_BDTR_MOE_Pos (15U)
+#define TIM_BDTR_MOE_Msk (0x1U << TIM_BDTR_MOE_Pos) /*!< 0x00008000 */
+#define TIM_BDTR_MOE TIM_BDTR_MOE_Msk /*!<Main Output enable */
+
+/******************* Bit definition for TIM_DCR register *******************/
+#define TIM_DCR_DBA_Pos (0U)
+#define TIM_DCR_DBA_Msk (0x1FU << TIM_DCR_DBA_Pos) /*!< 0x0000001F */
+#define TIM_DCR_DBA TIM_DCR_DBA_Msk /*!<DBA[4:0] bits (DMA Base Address) */
+#define TIM_DCR_DBA_0 (0x01U << TIM_DCR_DBA_Pos) /*!< 0x00000001 */
+#define TIM_DCR_DBA_1 (0x02U << TIM_DCR_DBA_Pos) /*!< 0x00000002 */
+#define TIM_DCR_DBA_2 (0x04U << TIM_DCR_DBA_Pos) /*!< 0x00000004 */
+#define TIM_DCR_DBA_3 (0x08U << TIM_DCR_DBA_Pos) /*!< 0x00000008 */
+#define TIM_DCR_DBA_4 (0x10U << TIM_DCR_DBA_Pos) /*!< 0x00000010 */
+
+#define TIM_DCR_DBL_Pos (8U)
+#define TIM_DCR_DBL_Msk (0x1FU << TIM_DCR_DBL_Pos) /*!< 0x00001F00 */
+#define TIM_DCR_DBL TIM_DCR_DBL_Msk /*!<DBL[4:0] bits (DMA Burst Length) */
+#define TIM_DCR_DBL_0 (0x01U << TIM_DCR_DBL_Pos) /*!< 0x00000100 */
+#define TIM_DCR_DBL_1 (0x02U << TIM_DCR_DBL_Pos) /*!< 0x00000200 */
+#define TIM_DCR_DBL_2 (0x04U << TIM_DCR_DBL_Pos) /*!< 0x00000400 */
+#define TIM_DCR_DBL_3 (0x08U << TIM_DCR_DBL_Pos) /*!< 0x00000800 */
+#define TIM_DCR_DBL_4 (0x10U << TIM_DCR_DBL_Pos) /*!< 0x00001000 */
+
+/******************* Bit definition for TIM_DMAR register ******************/
+#define TIM_DMAR_DMAB_Pos (0U)
+#define TIM_DMAR_DMAB_Msk (0xFFFFU << TIM_DMAR_DMAB_Pos) /*!< 0x0000FFFF */
+#define TIM_DMAR_DMAB TIM_DMAR_DMAB_Msk /*!<DMA register for burst accesses */
+
+/******************* Bit definition for TIM_OR register ********************/
+
+/******************************************************************************/
+/* */
+/* Real-Time Clock */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for RTC_CRH register ********************/
+#define RTC_CRH_SECIE_Pos (0U)
+#define RTC_CRH_SECIE_Msk (0x1U << RTC_CRH_SECIE_Pos) /*!< 0x00000001 */
+#define RTC_CRH_SECIE RTC_CRH_SECIE_Msk /*!< Second Interrupt Enable */
+#define RTC_CRH_ALRIE_Pos (1U)
+#define RTC_CRH_ALRIE_Msk (0x1U << RTC_CRH_ALRIE_Pos) /*!< 0x00000002 */
+#define RTC_CRH_ALRIE RTC_CRH_ALRIE_Msk /*!< Alarm Interrupt Enable */
+#define RTC_CRH_OWIE_Pos (2U)
+#define RTC_CRH_OWIE_Msk (0x1U << RTC_CRH_OWIE_Pos) /*!< 0x00000004 */
+#define RTC_CRH_OWIE RTC_CRH_OWIE_Msk /*!< OverfloW Interrupt Enable */
+
+/******************* Bit definition for RTC_CRL register ********************/
+#define RTC_CRL_SECF_Pos (0U)
+#define RTC_CRL_SECF_Msk (0x1U << RTC_CRL_SECF_Pos) /*!< 0x00000001 */
+#define RTC_CRL_SECF RTC_CRL_SECF_Msk /*!< Second Flag */
+#define RTC_CRL_ALRF_Pos (1U)
+#define RTC_CRL_ALRF_Msk (0x1U << RTC_CRL_ALRF_Pos) /*!< 0x00000002 */
+#define RTC_CRL_ALRF RTC_CRL_ALRF_Msk /*!< Alarm Flag */
+#define RTC_CRL_OWF_Pos (2U)
+#define RTC_CRL_OWF_Msk (0x1U << RTC_CRL_OWF_Pos) /*!< 0x00000004 */
+#define RTC_CRL_OWF RTC_CRL_OWF_Msk /*!< OverfloW Flag */
+#define RTC_CRL_RSF_Pos (3U)
+#define RTC_CRL_RSF_Msk (0x1U << RTC_CRL_RSF_Pos) /*!< 0x00000008 */
+#define RTC_CRL_RSF RTC_CRL_RSF_Msk /*!< Registers Synchronized Flag */
+#define RTC_CRL_CNF_Pos (4U)
+#define RTC_CRL_CNF_Msk (0x1U << RTC_CRL_CNF_Pos) /*!< 0x00000010 */
+#define RTC_CRL_CNF RTC_CRL_CNF_Msk /*!< Configuration Flag */
+#define RTC_CRL_RTOFF_Pos (5U)
+#define RTC_CRL_RTOFF_Msk (0x1U << RTC_CRL_RTOFF_Pos) /*!< 0x00000020 */
+#define RTC_CRL_RTOFF RTC_CRL_RTOFF_Msk /*!< RTC operation OFF */
+
+/******************* Bit definition for RTC_PRLH register *******************/
+#define RTC_PRLH_PRL_Pos (0U)
+#define RTC_PRLH_PRL_Msk (0xFU << RTC_PRLH_PRL_Pos) /*!< 0x0000000F */
+#define RTC_PRLH_PRL RTC_PRLH_PRL_Msk /*!< RTC Prescaler Reload Value High */
+
+/******************* Bit definition for RTC_PRLL register *******************/
+#define RTC_PRLL_PRL_Pos (0U)
+#define RTC_PRLL_PRL_Msk (0xFFFFU << RTC_PRLL_PRL_Pos) /*!< 0x0000FFFF */
+#define RTC_PRLL_PRL RTC_PRLL_PRL_Msk /*!< RTC Prescaler Reload Value Low */
+
+/******************* Bit definition for RTC_DIVH register *******************/
+#define RTC_DIVH_RTC_DIV_Pos (0U)
+#define RTC_DIVH_RTC_DIV_Msk (0xFU << RTC_DIVH_RTC_DIV_Pos) /*!< 0x0000000F */
+#define RTC_DIVH_RTC_DIV RTC_DIVH_RTC_DIV_Msk /*!< RTC Clock Divider High */
+
+/******************* Bit definition for RTC_DIVL register *******************/
+#define RTC_DIVL_RTC_DIV_Pos (0U)
+#define RTC_DIVL_RTC_DIV_Msk (0xFFFFU << RTC_DIVL_RTC_DIV_Pos) /*!< 0x0000FFFF */
+#define RTC_DIVL_RTC_DIV RTC_DIVL_RTC_DIV_Msk /*!< RTC Clock Divider Low */
+
+/******************* Bit definition for RTC_CNTH register *******************/
+#define RTC_CNTH_RTC_CNT_Pos (0U)
+#define RTC_CNTH_RTC_CNT_Msk (0xFFFFU << RTC_CNTH_RTC_CNT_Pos) /*!< 0x0000FFFF */
+#define RTC_CNTH_RTC_CNT RTC_CNTH_RTC_CNT_Msk /*!< RTC Counter High */
+
+/******************* Bit definition for RTC_CNTL register *******************/
+#define RTC_CNTL_RTC_CNT_Pos (0U)
+#define RTC_CNTL_RTC_CNT_Msk (0xFFFFU << RTC_CNTL_RTC_CNT_Pos) /*!< 0x0000FFFF */
+#define RTC_CNTL_RTC_CNT RTC_CNTL_RTC_CNT_Msk /*!< RTC Counter Low */
+
+/******************* Bit definition for RTC_ALRH register *******************/
+#define RTC_ALRH_RTC_ALR_Pos (0U)
+#define RTC_ALRH_RTC_ALR_Msk (0xFFFFU << RTC_ALRH_RTC_ALR_Pos) /*!< 0x0000FFFF */
+#define RTC_ALRH_RTC_ALR RTC_ALRH_RTC_ALR_Msk /*!< RTC Alarm High */
+
+/******************* Bit definition for RTC_ALRL register *******************/
+#define RTC_ALRL_RTC_ALR_Pos (0U)
+#define RTC_ALRL_RTC_ALR_Msk (0xFFFFU << RTC_ALRL_RTC_ALR_Pos) /*!< 0x0000FFFF */
+#define RTC_ALRL_RTC_ALR RTC_ALRL_RTC_ALR_Msk /*!< RTC Alarm Low */
+
+/******************************************************************************/
+/* */
+/* Independent WATCHDOG (IWDG) */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for IWDG_KR register ********************/
+#define IWDG_KR_KEY_Pos (0U)
+#define IWDG_KR_KEY_Msk (0xFFFFU << IWDG_KR_KEY_Pos) /*!< 0x0000FFFF */
+#define IWDG_KR_KEY IWDG_KR_KEY_Msk /*!< Key value (write only, read 0000h) */
+
+/******************* Bit definition for IWDG_PR register ********************/
+#define IWDG_PR_PR_Pos (0U)
+#define IWDG_PR_PR_Msk (0x7U << IWDG_PR_PR_Pos) /*!< 0x00000007 */
+#define IWDG_PR_PR IWDG_PR_PR_Msk /*!< PR[2:0] (Prescaler divider) */
+#define IWDG_PR_PR_0 (0x1U << IWDG_PR_PR_Pos) /*!< 0x00000001 */
+#define IWDG_PR_PR_1 (0x2U << IWDG_PR_PR_Pos) /*!< 0x00000002 */
+#define IWDG_PR_PR_2 (0x4U << IWDG_PR_PR_Pos) /*!< 0x00000004 */
+
+/******************* Bit definition for IWDG_RLR register *******************/
+#define IWDG_RLR_RL_Pos (0U)
+#define IWDG_RLR_RL_Msk (0xFFFU << IWDG_RLR_RL_Pos) /*!< 0x00000FFF */
+#define IWDG_RLR_RL IWDG_RLR_RL_Msk /*!< Watchdog counter reload value */
+
+/******************* Bit definition for IWDG_SR register ********************/
+#define IWDG_SR_PVU_Pos (0U)
+#define IWDG_SR_PVU_Msk (0x1U << IWDG_SR_PVU_Pos) /*!< 0x00000001 */
+#define IWDG_SR_PVU IWDG_SR_PVU_Msk /*!< Watchdog prescaler value update */
+#define IWDG_SR_RVU_Pos (1U)
+#define IWDG_SR_RVU_Msk (0x1U << IWDG_SR_RVU_Pos) /*!< 0x00000002 */
+#define IWDG_SR_RVU IWDG_SR_RVU_Msk /*!< Watchdog counter reload value update */
+
+/******************************************************************************/
+/* */
+/* Window WATCHDOG (WWDG) */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for WWDG_CR register ********************/
+#define WWDG_CR_T_Pos (0U)
+#define WWDG_CR_T_Msk (0x7FU << WWDG_CR_T_Pos) /*!< 0x0000007F */
+#define WWDG_CR_T WWDG_CR_T_Msk /*!< T[6:0] bits (7-Bit counter (MSB to LSB)) */
+#define WWDG_CR_T_0 (0x01U << WWDG_CR_T_Pos) /*!< 0x00000001 */
+#define WWDG_CR_T_1 (0x02U << WWDG_CR_T_Pos) /*!< 0x00000002 */
+#define WWDG_CR_T_2 (0x04U << WWDG_CR_T_Pos) /*!< 0x00000004 */
+#define WWDG_CR_T_3 (0x08U << WWDG_CR_T_Pos) /*!< 0x00000008 */
+#define WWDG_CR_T_4 (0x10U << WWDG_CR_T_Pos) /*!< 0x00000010 */
+#define WWDG_CR_T_5 (0x20U << WWDG_CR_T_Pos) /*!< 0x00000020 */
+#define WWDG_CR_T_6 (0x40U << WWDG_CR_T_Pos) /*!< 0x00000040 */
+
+/* Legacy defines */
+#define WWDG_CR_T0 WWDG_CR_T_0
+#define WWDG_CR_T1 WWDG_CR_T_1
+#define WWDG_CR_T2 WWDG_CR_T_2
+#define WWDG_CR_T3 WWDG_CR_T_3
+#define WWDG_CR_T4 WWDG_CR_T_4
+#define WWDG_CR_T5 WWDG_CR_T_5
+#define WWDG_CR_T6 WWDG_CR_T_6
+
+#define WWDG_CR_WDGA_Pos (7U)
+#define WWDG_CR_WDGA_Msk (0x1U << WWDG_CR_WDGA_Pos) /*!< 0x00000080 */
+#define WWDG_CR_WDGA WWDG_CR_WDGA_Msk /*!< Activation bit */
+
+/******************* Bit definition for WWDG_CFR register *******************/
+#define WWDG_CFR_W_Pos (0U)
+#define WWDG_CFR_W_Msk (0x7FU << WWDG_CFR_W_Pos) /*!< 0x0000007F */
+#define WWDG_CFR_W WWDG_CFR_W_Msk /*!< W[6:0] bits (7-bit window value) */
+#define WWDG_CFR_W_0 (0x01U << WWDG_CFR_W_Pos) /*!< 0x00000001 */
+#define WWDG_CFR_W_1 (0x02U << WWDG_CFR_W_Pos) /*!< 0x00000002 */
+#define WWDG_CFR_W_2 (0x04U << WWDG_CFR_W_Pos) /*!< 0x00000004 */
+#define WWDG_CFR_W_3 (0x08U << WWDG_CFR_W_Pos) /*!< 0x00000008 */
+#define WWDG_CFR_W_4 (0x10U << WWDG_CFR_W_Pos) /*!< 0x00000010 */
+#define WWDG_CFR_W_5 (0x20U << WWDG_CFR_W_Pos) /*!< 0x00000020 */
+#define WWDG_CFR_W_6 (0x40U << WWDG_CFR_W_Pos) /*!< 0x00000040 */
+
+/* Legacy defines */
+#define WWDG_CFR_W0 WWDG_CFR_W_0
+#define WWDG_CFR_W1 WWDG_CFR_W_1
+#define WWDG_CFR_W2 WWDG_CFR_W_2
+#define WWDG_CFR_W3 WWDG_CFR_W_3
+#define WWDG_CFR_W4 WWDG_CFR_W_4
+#define WWDG_CFR_W5 WWDG_CFR_W_5
+#define WWDG_CFR_W6 WWDG_CFR_W_6
+
+#define WWDG_CFR_WDGTB_Pos (7U)
+#define WWDG_CFR_WDGTB_Msk (0x3U << WWDG_CFR_WDGTB_Pos) /*!< 0x00000180 */
+#define WWDG_CFR_WDGTB WWDG_CFR_WDGTB_Msk /*!< WDGTB[1:0] bits (Timer Base) */
+#define WWDG_CFR_WDGTB_0 (0x1U << WWDG_CFR_WDGTB_Pos) /*!< 0x00000080 */
+#define WWDG_CFR_WDGTB_1 (0x2U << WWDG_CFR_WDGTB_Pos) /*!< 0x00000100 */
+
+/* Legacy defines */
+#define WWDG_CFR_WDGTB0 WWDG_CFR_WDGTB_0
+#define WWDG_CFR_WDGTB1 WWDG_CFR_WDGTB_1
+
+#define WWDG_CFR_EWI_Pos (9U)
+#define WWDG_CFR_EWI_Msk (0x1U << WWDG_CFR_EWI_Pos) /*!< 0x00000200 */
+#define WWDG_CFR_EWI WWDG_CFR_EWI_Msk /*!< Early Wakeup Interrupt */
+
+/******************* Bit definition for WWDG_SR register ********************/
+#define WWDG_SR_EWIF_Pos (0U)
+#define WWDG_SR_EWIF_Msk (0x1U << WWDG_SR_EWIF_Pos) /*!< 0x00000001 */
+#define WWDG_SR_EWIF WWDG_SR_EWIF_Msk /*!< Early Wakeup Interrupt Flag */
+
+/******************************************************************************/
+/* */
+/* Flexible Static Memory Controller */
+/* */
+/******************************************************************************/
+
+/****************** Bit definition for FSMC_BCRx (x=1..4) register **********/
+#define FSMC_BCRx_MBKEN_Pos (0U)
+#define FSMC_BCRx_MBKEN_Msk (0x1U << FSMC_BCRx_MBKEN_Pos) /*!< 0x00000001 */
+#define FSMC_BCRx_MBKEN FSMC_BCRx_MBKEN_Msk /*!< Memory bank enable bit */
+#define FSMC_BCRx_MUXEN_Pos (1U)
+#define FSMC_BCRx_MUXEN_Msk (0x1U << FSMC_BCRx_MUXEN_Pos) /*!< 0x00000002 */
+#define FSMC_BCRx_MUXEN FSMC_BCRx_MUXEN_Msk /*!< Address/data multiplexing enable bit */
+
+#define FSMC_BCRx_MTYP_Pos (2U)
+#define FSMC_BCRx_MTYP_Msk (0x3U << FSMC_BCRx_MTYP_Pos) /*!< 0x0000000C */
+#define FSMC_BCRx_MTYP FSMC_BCRx_MTYP_Msk /*!< MTYP[1:0] bits (Memory type) */
+#define FSMC_BCRx_MTYP_0 (0x1U << FSMC_BCRx_MTYP_Pos) /*!< 0x00000004 */
+#define FSMC_BCRx_MTYP_1 (0x2U << FSMC_BCRx_MTYP_Pos) /*!< 0x00000008 */
+
+#define FSMC_BCRx_MWID_Pos (4U)
+#define FSMC_BCRx_MWID_Msk (0x3U << FSMC_BCRx_MWID_Pos) /*!< 0x00000030 */
+#define FSMC_BCRx_MWID FSMC_BCRx_MWID_Msk /*!< MWID[1:0] bits (Memory data bus width) */
+#define FSMC_BCRx_MWID_0 (0x1U << FSMC_BCRx_MWID_Pos) /*!< 0x00000010 */
+#define FSMC_BCRx_MWID_1 (0x2U << FSMC_BCRx_MWID_Pos) /*!< 0x00000020 */
+
+#define FSMC_BCRx_FACCEN_Pos (6U)
+#define FSMC_BCRx_FACCEN_Msk (0x1U << FSMC_BCRx_FACCEN_Pos) /*!< 0x00000040 */
+#define FSMC_BCRx_FACCEN FSMC_BCRx_FACCEN_Msk /*!< Flash access enable */
+#define FSMC_BCRx_BURSTEN_Pos (8U)
+#define FSMC_BCRx_BURSTEN_Msk (0x1U << FSMC_BCRx_BURSTEN_Pos) /*!< 0x00000100 */
+#define FSMC_BCRx_BURSTEN FSMC_BCRx_BURSTEN_Msk /*!< Burst enable bit */
+#define FSMC_BCRx_WAITPOL_Pos (9U)
+#define FSMC_BCRx_WAITPOL_Msk (0x1U << FSMC_BCRx_WAITPOL_Pos) /*!< 0x00000200 */
+#define FSMC_BCRx_WAITPOL FSMC_BCRx_WAITPOL_Msk /*!< Wait signal polarity bit */
+#define FSMC_BCRx_WRAPMOD_Pos (10U)
+#define FSMC_BCRx_WRAPMOD_Msk (0x1U << FSMC_BCRx_WRAPMOD_Pos) /*!< 0x00000400 */
+#define FSMC_BCRx_WRAPMOD FSMC_BCRx_WRAPMOD_Msk /*!< Wrapped burst mode support */
+#define FSMC_BCRx_WAITCFG_Pos (11U)
+#define FSMC_BCRx_WAITCFG_Msk (0x1U << FSMC_BCRx_WAITCFG_Pos) /*!< 0x00000800 */
+#define FSMC_BCRx_WAITCFG FSMC_BCRx_WAITCFG_Msk /*!< Wait timing configuration */
+#define FSMC_BCRx_WREN_Pos (12U)
+#define FSMC_BCRx_WREN_Msk (0x1U << FSMC_BCRx_WREN_Pos) /*!< 0x00001000 */
+#define FSMC_BCRx_WREN FSMC_BCRx_WREN_Msk /*!< Write enable bit */
+#define FSMC_BCRx_WAITEN_Pos (13U)
+#define FSMC_BCRx_WAITEN_Msk (0x1U << FSMC_BCRx_WAITEN_Pos) /*!< 0x00002000 */
+#define FSMC_BCRx_WAITEN FSMC_BCRx_WAITEN_Msk /*!< Wait enable bit */
+#define FSMC_BCRx_EXTMOD_Pos (14U)
+#define FSMC_BCRx_EXTMOD_Msk (0x1U << FSMC_BCRx_EXTMOD_Pos) /*!< 0x00004000 */
+#define FSMC_BCRx_EXTMOD FSMC_BCRx_EXTMOD_Msk /*!< Extended mode enable */
+#define FSMC_BCRx_ASYNCWAIT_Pos (15U)
+#define FSMC_BCRx_ASYNCWAIT_Msk (0x1U << FSMC_BCRx_ASYNCWAIT_Pos) /*!< 0x00008000 */
+#define FSMC_BCRx_ASYNCWAIT FSMC_BCRx_ASYNCWAIT_Msk /*!< Asynchronous wait */
+#define FSMC_BCRx_CBURSTRW_Pos (19U)
+#define FSMC_BCRx_CBURSTRW_Msk (0x1U << FSMC_BCRx_CBURSTRW_Pos) /*!< 0x00080000 */
+#define FSMC_BCRx_CBURSTRW FSMC_BCRx_CBURSTRW_Msk /*!< Write burst enable */
+
+/****************** Bit definition for FSMC_BTRx (x=1..4) register ******/
+#define FSMC_BTRx_ADDSET_Pos (0U)
+#define FSMC_BTRx_ADDSET_Msk (0xFU << FSMC_BTRx_ADDSET_Pos) /*!< 0x0000000F */
+#define FSMC_BTRx_ADDSET FSMC_BTRx_ADDSET_Msk /*!< ADDSET[3:0] bits (Address setup phase duration) */
+#define FSMC_BTRx_ADDSET_0 (0x1U << FSMC_BTRx_ADDSET_Pos) /*!< 0x00000001 */
+#define FSMC_BTRx_ADDSET_1 (0x2U << FSMC_BTRx_ADDSET_Pos) /*!< 0x00000002 */
+#define FSMC_BTRx_ADDSET_2 (0x4U << FSMC_BTRx_ADDSET_Pos) /*!< 0x00000004 */
+#define FSMC_BTRx_ADDSET_3 (0x8U << FSMC_BTRx_ADDSET_Pos) /*!< 0x00000008 */
+
+#define FSMC_BTRx_ADDHLD_Pos (4U)
+#define FSMC_BTRx_ADDHLD_Msk (0xFU << FSMC_BTRx_ADDHLD_Pos) /*!< 0x000000F0 */
+#define FSMC_BTRx_ADDHLD FSMC_BTRx_ADDHLD_Msk /*!< ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FSMC_BTRx_ADDHLD_0 (0x1U << FSMC_BTRx_ADDHLD_Pos) /*!< 0x00000010 */
+#define FSMC_BTRx_ADDHLD_1 (0x2U << FSMC_BTRx_ADDHLD_Pos) /*!< 0x00000020 */
+#define FSMC_BTRx_ADDHLD_2 (0x4U << FSMC_BTRx_ADDHLD_Pos) /*!< 0x00000040 */
+#define FSMC_BTRx_ADDHLD_3 (0x8U << FSMC_BTRx_ADDHLD_Pos) /*!< 0x00000080 */
+
+#define FSMC_BTRx_DATAST_Pos (8U)
+#define FSMC_BTRx_DATAST_Msk (0xFFU << FSMC_BTRx_DATAST_Pos) /*!< 0x0000FF00 */
+#define FSMC_BTRx_DATAST FSMC_BTRx_DATAST_Msk /*!< DATAST [3:0] bits (Data-phase duration) */
+#define FSMC_BTRx_DATAST_0 (0x01U << FSMC_BTRx_DATAST_Pos) /*!< 0x00000100 */
+#define FSMC_BTRx_DATAST_1 (0x02U << FSMC_BTRx_DATAST_Pos) /*!< 0x00000200 */
+#define FSMC_BTRx_DATAST_2 (0x04U << FSMC_BTRx_DATAST_Pos) /*!< 0x00000400 */
+#define FSMC_BTRx_DATAST_3 (0x08U << FSMC_BTRx_DATAST_Pos) /*!< 0x00000800 */
+#define FSMC_BTRx_DATAST_4 (0x10U << FSMC_BTRx_DATAST_Pos) /*!< 0x00001000 */
+#define FSMC_BTRx_DATAST_5 (0x20U << FSMC_BTRx_DATAST_Pos) /*!< 0x00002000 */
+#define FSMC_BTRx_DATAST_6 (0x40U << FSMC_BTRx_DATAST_Pos) /*!< 0x00004000 */
+#define FSMC_BTRx_DATAST_7 (0x80U << FSMC_BTRx_DATAST_Pos) /*!< 0x00008000 */
+
+#define FSMC_BTRx_BUSTURN_Pos (16U)
+#define FSMC_BTRx_BUSTURN_Msk (0xFU << FSMC_BTRx_BUSTURN_Pos) /*!< 0x000F0000 */
+#define FSMC_BTRx_BUSTURN FSMC_BTRx_BUSTURN_Msk /*!< BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define FSMC_BTRx_BUSTURN_0 (0x1U << FSMC_BTRx_BUSTURN_Pos) /*!< 0x00010000 */
+#define FSMC_BTRx_BUSTURN_1 (0x2U << FSMC_BTRx_BUSTURN_Pos) /*!< 0x00020000 */
+#define FSMC_BTRx_BUSTURN_2 (0x4U << FSMC_BTRx_BUSTURN_Pos) /*!< 0x00040000 */
+#define FSMC_BTRx_BUSTURN_3 (0x8U << FSMC_BTRx_BUSTURN_Pos) /*!< 0x00080000 */
+
+#define FSMC_BTRx_CLKDIV_Pos (20U)
+#define FSMC_BTRx_CLKDIV_Msk (0xFU << FSMC_BTRx_CLKDIV_Pos) /*!< 0x00F00000 */
+#define FSMC_BTRx_CLKDIV FSMC_BTRx_CLKDIV_Msk /*!< CLKDIV[3:0] bits (Clock divide ratio) */
+#define FSMC_BTRx_CLKDIV_0 (0x1U << FSMC_BTRx_CLKDIV_Pos) /*!< 0x00100000 */
+#define FSMC_BTRx_CLKDIV_1 (0x2U << FSMC_BTRx_CLKDIV_Pos) /*!< 0x00200000 */
+#define FSMC_BTRx_CLKDIV_2 (0x4U << FSMC_BTRx_CLKDIV_Pos) /*!< 0x00400000 */
+#define FSMC_BTRx_CLKDIV_3 (0x8U << FSMC_BTRx_CLKDIV_Pos) /*!< 0x00800000 */
+
+#define FSMC_BTRx_DATLAT_Pos (24U)
+#define FSMC_BTRx_DATLAT_Msk (0xFU << FSMC_BTRx_DATLAT_Pos) /*!< 0x0F000000 */
+#define FSMC_BTRx_DATLAT FSMC_BTRx_DATLAT_Msk /*!< DATLA[3:0] bits (Data latency) */
+#define FSMC_BTRx_DATLAT_0 (0x1U << FSMC_BTRx_DATLAT_Pos) /*!< 0x01000000 */
+#define FSMC_BTRx_DATLAT_1 (0x2U << FSMC_BTRx_DATLAT_Pos) /*!< 0x02000000 */
+#define FSMC_BTRx_DATLAT_2 (0x4U << FSMC_BTRx_DATLAT_Pos) /*!< 0x04000000 */
+#define FSMC_BTRx_DATLAT_3 (0x8U << FSMC_BTRx_DATLAT_Pos) /*!< 0x08000000 */
+
+#define FSMC_BTRx_ACCMOD_Pos (28U)
+#define FSMC_BTRx_ACCMOD_Msk (0x3U << FSMC_BTRx_ACCMOD_Pos) /*!< 0x30000000 */
+#define FSMC_BTRx_ACCMOD FSMC_BTRx_ACCMOD_Msk /*!< ACCMOD[1:0] bits (Access mode) */
+#define FSMC_BTRx_ACCMOD_0 (0x1U << FSMC_BTRx_ACCMOD_Pos) /*!< 0x10000000 */
+#define FSMC_BTRx_ACCMOD_1 (0x2U << FSMC_BTRx_ACCMOD_Pos) /*!< 0x20000000 */
+
+/****************** Bit definition for FSMC_BWTRx (x=1..4) register ******/
+#define FSMC_BWTRx_ADDSET_Pos (0U)
+#define FSMC_BWTRx_ADDSET_Msk (0xFU << FSMC_BWTRx_ADDSET_Pos) /*!< 0x0000000F */
+#define FSMC_BWTRx_ADDSET FSMC_BWTRx_ADDSET_Msk /*!< ADDSET[3:0] bits (Address setup phase duration) */
+#define FSMC_BWTRx_ADDSET_0 (0x1U << FSMC_BWTRx_ADDSET_Pos) /*!< 0x00000001 */
+#define FSMC_BWTRx_ADDSET_1 (0x2U << FSMC_BWTRx_ADDSET_Pos) /*!< 0x00000002 */
+#define FSMC_BWTRx_ADDSET_2 (0x4U << FSMC_BWTRx_ADDSET_Pos) /*!< 0x00000004 */
+#define FSMC_BWTRx_ADDSET_3 (0x8U << FSMC_BWTRx_ADDSET_Pos) /*!< 0x00000008 */
+
+#define FSMC_BWTRx_ADDHLD_Pos (4U)
+#define FSMC_BWTRx_ADDHLD_Msk (0xFU << FSMC_BWTRx_ADDHLD_Pos) /*!< 0x000000F0 */
+#define FSMC_BWTRx_ADDHLD FSMC_BWTRx_ADDHLD_Msk /*!< ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FSMC_BWTRx_ADDHLD_0 (0x1U << FSMC_BWTRx_ADDHLD_Pos) /*!< 0x00000010 */
+#define FSMC_BWTRx_ADDHLD_1 (0x2U << FSMC_BWTRx_ADDHLD_Pos) /*!< 0x00000020 */
+#define FSMC_BWTRx_ADDHLD_2 (0x4U << FSMC_BWTRx_ADDHLD_Pos) /*!< 0x00000040 */
+#define FSMC_BWTRx_ADDHLD_3 (0x8U << FSMC_BWTRx_ADDHLD_Pos) /*!< 0x00000080 */
+
+#define FSMC_BWTRx_DATAST_Pos (8U)
+#define FSMC_BWTRx_DATAST_Msk (0xFFU << FSMC_BWTRx_DATAST_Pos) /*!< 0x0000FF00 */
+#define FSMC_BWTRx_DATAST FSMC_BWTRx_DATAST_Msk /*!< DATAST [3:0] bits (Data-phase duration) */
+#define FSMC_BWTRx_DATAST_0 (0x01U << FSMC_BWTRx_DATAST_Pos) /*!< 0x00000100 */
+#define FSMC_BWTRx_DATAST_1 (0x02U << FSMC_BWTRx_DATAST_Pos) /*!< 0x00000200 */
+#define FSMC_BWTRx_DATAST_2 (0x04U << FSMC_BWTRx_DATAST_Pos) /*!< 0x00000400 */
+#define FSMC_BWTRx_DATAST_3 (0x08U << FSMC_BWTRx_DATAST_Pos) /*!< 0x00000800 */
+#define FSMC_BWTRx_DATAST_4 (0x10U << FSMC_BWTRx_DATAST_Pos) /*!< 0x00001000 */
+#define FSMC_BWTRx_DATAST_5 (0x20U << FSMC_BWTRx_DATAST_Pos) /*!< 0x00002000 */
+#define FSMC_BWTRx_DATAST_6 (0x40U << FSMC_BWTRx_DATAST_Pos) /*!< 0x00004000 */
+#define FSMC_BWTRx_DATAST_7 (0x80U << FSMC_BWTRx_DATAST_Pos) /*!< 0x00008000 */
+
+#define FSMC_BWTRx_BUSTURN_Pos (16U)
+#define FSMC_BWTRx_BUSTURN_Msk (0xFU << FSMC_BWTRx_BUSTURN_Pos) /*!< 0x000F0000 */
+#define FSMC_BWTRx_BUSTURN FSMC_BWTRx_BUSTURN_Msk /*!< BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define FSMC_BWTRx_BUSTURN_0 (0x1U << FSMC_BWTRx_BUSTURN_Pos) /*!< 0x00010000 */
+#define FSMC_BWTRx_BUSTURN_1 (0x2U << FSMC_BWTRx_BUSTURN_Pos) /*!< 0x00020000 */
+#define FSMC_BWTRx_BUSTURN_2 (0x4U << FSMC_BWTRx_BUSTURN_Pos) /*!< 0x00040000 */
+#define FSMC_BWTRx_BUSTURN_3 (0x8U << FSMC_BWTRx_BUSTURN_Pos) /*!< 0x00080000 */
+
+#define FSMC_BWTRx_ACCMOD_Pos (28U)
+#define FSMC_BWTRx_ACCMOD_Msk (0x3U << FSMC_BWTRx_ACCMOD_Pos) /*!< 0x30000000 */
+#define FSMC_BWTRx_ACCMOD FSMC_BWTRx_ACCMOD_Msk /*!< ACCMOD[1:0] bits (Access mode) */
+#define FSMC_BWTRx_ACCMOD_0 (0x1U << FSMC_BWTRx_ACCMOD_Pos) /*!< 0x10000000 */
+#define FSMC_BWTRx_ACCMOD_1 (0x2U << FSMC_BWTRx_ACCMOD_Pos) /*!< 0x20000000 */
+
+/****************** Bit definition for FSMC_PCRx (x = 2 to 4) register *******************/
+#define FSMC_PCRx_PWAITEN_Pos (1U)
+#define FSMC_PCRx_PWAITEN_Msk (0x1U << FSMC_PCRx_PWAITEN_Pos) /*!< 0x00000002 */
+#define FSMC_PCRx_PWAITEN FSMC_PCRx_PWAITEN_Msk /*!< Wait feature enable bit */
+#define FSMC_PCRx_PBKEN_Pos (2U)
+#define FSMC_PCRx_PBKEN_Msk (0x1U << FSMC_PCRx_PBKEN_Pos) /*!< 0x00000004 */
+#define FSMC_PCRx_PBKEN FSMC_PCRx_PBKEN_Msk /*!< PC Card/NAND Flash memory bank enable bit */
+#define FSMC_PCRx_PTYP_Pos (3U)
+#define FSMC_PCRx_PTYP_Msk (0x1U << FSMC_PCRx_PTYP_Pos) /*!< 0x00000008 */
+#define FSMC_PCRx_PTYP FSMC_PCRx_PTYP_Msk /*!< Memory type */
+
+#define FSMC_PCRx_PWID_Pos (4U)
+#define FSMC_PCRx_PWID_Msk (0x3U << FSMC_PCRx_PWID_Pos) /*!< 0x00000030 */
+#define FSMC_PCRx_PWID FSMC_PCRx_PWID_Msk /*!< PWID[1:0] bits (NAND Flash databus width) */
+#define FSMC_PCRx_PWID_0 (0x1U << FSMC_PCRx_PWID_Pos) /*!< 0x00000010 */
+#define FSMC_PCRx_PWID_1 (0x2U << FSMC_PCRx_PWID_Pos) /*!< 0x00000020 */
+
+#define FSMC_PCRx_ECCEN_Pos (6U)
+#define FSMC_PCRx_ECCEN_Msk (0x1U << FSMC_PCRx_ECCEN_Pos) /*!< 0x00000040 */
+#define FSMC_PCRx_ECCEN FSMC_PCRx_ECCEN_Msk /*!< ECC computation logic enable bit */
+
+#define FSMC_PCRx_TCLR_Pos (9U)
+#define FSMC_PCRx_TCLR_Msk (0xFU << FSMC_PCRx_TCLR_Pos) /*!< 0x00001E00 */
+#define FSMC_PCRx_TCLR FSMC_PCRx_TCLR_Msk /*!< TCLR[3:0] bits (CLE to RE delay) */
+#define FSMC_PCRx_TCLR_0 (0x1U << FSMC_PCRx_TCLR_Pos) /*!< 0x00000200 */
+#define FSMC_PCRx_TCLR_1 (0x2U << FSMC_PCRx_TCLR_Pos) /*!< 0x00000400 */
+#define FSMC_PCRx_TCLR_2 (0x4U << FSMC_PCRx_TCLR_Pos) /*!< 0x00000800 */
+#define FSMC_PCRx_TCLR_3 (0x8U << FSMC_PCRx_TCLR_Pos) /*!< 0x00001000 */
+
+#define FSMC_PCRx_TAR_Pos (13U)
+#define FSMC_PCRx_TAR_Msk (0xFU << FSMC_PCRx_TAR_Pos) /*!< 0x0001E000 */
+#define FSMC_PCRx_TAR FSMC_PCRx_TAR_Msk /*!< TAR[3:0] bits (ALE to RE delay) */
+#define FSMC_PCRx_TAR_0 (0x1U << FSMC_PCRx_TAR_Pos) /*!< 0x00002000 */
+#define FSMC_PCRx_TAR_1 (0x2U << FSMC_PCRx_TAR_Pos) /*!< 0x00004000 */
+#define FSMC_PCRx_TAR_2 (0x4U << FSMC_PCRx_TAR_Pos) /*!< 0x00008000 */
+#define FSMC_PCRx_TAR_3 (0x8U << FSMC_PCRx_TAR_Pos) /*!< 0x00010000 */
+
+#define FSMC_PCRx_ECCPS_Pos (17U)
+#define FSMC_PCRx_ECCPS_Msk (0x7U << FSMC_PCRx_ECCPS_Pos) /*!< 0x000E0000 */
+#define FSMC_PCRx_ECCPS FSMC_PCRx_ECCPS_Msk /*!< ECCPS[1:0] bits (ECC page size) */
+#define FSMC_PCRx_ECCPS_0 (0x1U << FSMC_PCRx_ECCPS_Pos) /*!< 0x00020000 */
+#define FSMC_PCRx_ECCPS_1 (0x2U << FSMC_PCRx_ECCPS_Pos) /*!< 0x00040000 */
+#define FSMC_PCRx_ECCPS_2 (0x4U << FSMC_PCRx_ECCPS_Pos) /*!< 0x00080000 */
+
+/******************* Bit definition for FSMC_SRx (x = 2 to 4) register *******************/
+#define FSMC_SRx_IRS_Pos (0U)
+#define FSMC_SRx_IRS_Msk (0x1U << FSMC_SRx_IRS_Pos) /*!< 0x00000001 */
+#define FSMC_SRx_IRS FSMC_SRx_IRS_Msk /*!< Interrupt Rising Edge status */
+#define FSMC_SRx_ILS_Pos (1U)
+#define FSMC_SRx_ILS_Msk (0x1U << FSMC_SRx_ILS_Pos) /*!< 0x00000002 */
+#define FSMC_SRx_ILS FSMC_SRx_ILS_Msk /*!< Interrupt Level status */
+#define FSMC_SRx_IFS_Pos (2U)
+#define FSMC_SRx_IFS_Msk (0x1U << FSMC_SRx_IFS_Pos) /*!< 0x00000004 */
+#define FSMC_SRx_IFS FSMC_SRx_IFS_Msk /*!< Interrupt Falling Edge status */
+#define FSMC_SRx_IREN_Pos (3U)
+#define FSMC_SRx_IREN_Msk (0x1U << FSMC_SRx_IREN_Pos) /*!< 0x00000008 */
+#define FSMC_SRx_IREN FSMC_SRx_IREN_Msk /*!< Interrupt Rising Edge detection Enable bit */
+#define FSMC_SRx_ILEN_Pos (4U)
+#define FSMC_SRx_ILEN_Msk (0x1U << FSMC_SRx_ILEN_Pos) /*!< 0x00000010 */
+#define FSMC_SRx_ILEN FSMC_SRx_ILEN_Msk /*!< Interrupt Level detection Enable bit */
+#define FSMC_SRx_IFEN_Pos (5U)
+#define FSMC_SRx_IFEN_Msk (0x1U << FSMC_SRx_IFEN_Pos) /*!< 0x00000020 */
+#define FSMC_SRx_IFEN FSMC_SRx_IFEN_Msk /*!< Interrupt Falling Edge detection Enable bit */
+#define FSMC_SRx_FEMPT_Pos (6U)
+#define FSMC_SRx_FEMPT_Msk (0x1U << FSMC_SRx_FEMPT_Pos) /*!< 0x00000040 */
+#define FSMC_SRx_FEMPT FSMC_SRx_FEMPT_Msk /*!< FIFO empty */
+
+/****************** Bit definition for FSMC_PMEMx (x = 2 to 4) register ******************/
+#define FSMC_PMEMx_MEMSETx_Pos (0U)
+#define FSMC_PMEMx_MEMSETx_Msk (0xFFU << FSMC_PMEMx_MEMSETx_Pos) /*!< 0x000000FF */
+#define FSMC_PMEMx_MEMSETx FSMC_PMEMx_MEMSETx_Msk /*!< MEMSETx[7:0] bits (Common memory x setup time) */
+#define FSMC_PMEMx_MEMSETx_0 (0x01U << FSMC_PMEMx_MEMSETx_Pos) /*!< 0x00000001 */
+#define FSMC_PMEMx_MEMSETx_1 (0x02U << FSMC_PMEMx_MEMSETx_Pos) /*!< 0x00000002 */
+#define FSMC_PMEMx_MEMSETx_2 (0x04U << FSMC_PMEMx_MEMSETx_Pos) /*!< 0x00000004 */
+#define FSMC_PMEMx_MEMSETx_3 (0x08U << FSMC_PMEMx_MEMSETx_Pos) /*!< 0x00000008 */
+#define FSMC_PMEMx_MEMSETx_4 (0x10U << FSMC_PMEMx_MEMSETx_Pos) /*!< 0x00000010 */
+#define FSMC_PMEMx_MEMSETx_5 (0x20U << FSMC_PMEMx_MEMSETx_Pos) /*!< 0x00000020 */
+#define FSMC_PMEMx_MEMSETx_6 (0x40U << FSMC_PMEMx_MEMSETx_Pos) /*!< 0x00000040 */
+#define FSMC_PMEMx_MEMSETx_7 (0x80U << FSMC_PMEMx_MEMSETx_Pos) /*!< 0x00000080 */
+
+#define FSMC_PMEMx_MEMWAITx_Pos (8U)
+#define FSMC_PMEMx_MEMWAITx_Msk (0xFFU << FSMC_PMEMx_MEMWAITx_Pos) /*!< 0x0000FF00 */
+#define FSMC_PMEMx_MEMWAITx FSMC_PMEMx_MEMWAITx_Msk /*!< MEMWAITx[7:0] bits (Common memory x wait time) */
+#define FSMC_PMEMx_MEMWAIT2_0 ((uint32_t)0x00000100) /*!< Bit 0 */
+#define FSMC_PMEMx_MEMWAITx_1 ((uint32_t)0x00000200) /*!< Bit 1 */
+#define FSMC_PMEMx_MEMWAITx_2 ((uint32_t)0x00000400) /*!< Bit 2 */
+#define FSMC_PMEMx_MEMWAITx_3 ((uint32_t)0x00000800) /*!< Bit 3 */
+#define FSMC_PMEMx_MEMWAITx_4 ((uint32_t)0x00001000) /*!< Bit 4 */
+#define FSMC_PMEMx_MEMWAITx_5 ((uint32_t)0x00002000) /*!< Bit 5 */
+#define FSMC_PMEMx_MEMWAITx_6 ((uint32_t)0x00004000) /*!< Bit 6 */
+#define FSMC_PMEMx_MEMWAITx_7 ((uint32_t)0x00008000) /*!< Bit 7 */
+
+#define FSMC_PMEMx_MEMHOLDx_Pos (16U)
+#define FSMC_PMEMx_MEMHOLDx_Msk (0xFFU << FSMC_PMEMx_MEMHOLDx_Pos) /*!< 0x00FF0000 */
+#define FSMC_PMEMx_MEMHOLDx FSMC_PMEMx_MEMHOLDx_Msk /*!< MEMHOLDx[7:0] bits (Common memory x hold time) */
+#define FSMC_PMEMx_MEMHOLDx_0 (0x01U << FSMC_PMEMx_MEMHOLDx_Pos) /*!< 0x00010000 */
+#define FSMC_PMEMx_MEMHOLDx_1 (0x02U << FSMC_PMEMx_MEMHOLDx_Pos) /*!< 0x00020000 */
+#define FSMC_PMEMx_MEMHOLDx_2 (0x04U << FSMC_PMEMx_MEMHOLDx_Pos) /*!< 0x00040000 */
+#define FSMC_PMEMx_MEMHOLDx_3 (0x08U << FSMC_PMEMx_MEMHOLDx_Pos) /*!< 0x00080000 */
+#define FSMC_PMEMx_MEMHOLDx_4 (0x10U << FSMC_PMEMx_MEMHOLDx_Pos) /*!< 0x00100000 */
+#define FSMC_PMEMx_MEMHOLDx_5 (0x20U << FSMC_PMEMx_MEMHOLDx_Pos) /*!< 0x00200000 */
+#define FSMC_PMEMx_MEMHOLDx_6 (0x40U << FSMC_PMEMx_MEMHOLDx_Pos) /*!< 0x00400000 */
+#define FSMC_PMEMx_MEMHOLDx_7 (0x80U << FSMC_PMEMx_MEMHOLDx_Pos) /*!< 0x00800000 */
+
+#define FSMC_PMEMx_MEMHIZx_Pos (24U)
+#define FSMC_PMEMx_MEMHIZx_Msk (0xFFU << FSMC_PMEMx_MEMHIZx_Pos) /*!< 0xFF000000 */
+#define FSMC_PMEMx_MEMHIZx FSMC_PMEMx_MEMHIZx_Msk /*!< MEMHIZx[7:0] bits (Common memory x databus HiZ time) */
+#define FSMC_PMEMx_MEMHIZx_0 (0x01U << FSMC_PMEMx_MEMHIZx_Pos) /*!< 0x01000000 */
+#define FSMC_PMEMx_MEMHIZx_1 (0x02U << FSMC_PMEMx_MEMHIZx_Pos) /*!< 0x02000000 */
+#define FSMC_PMEMx_MEMHIZx_2 (0x04U << FSMC_PMEMx_MEMHIZx_Pos) /*!< 0x04000000 */
+#define FSMC_PMEMx_MEMHIZx_3 (0x08U << FSMC_PMEMx_MEMHIZx_Pos) /*!< 0x08000000 */
+#define FSMC_PMEMx_MEMHIZx_4 (0x10U << FSMC_PMEMx_MEMHIZx_Pos) /*!< 0x10000000 */
+#define FSMC_PMEMx_MEMHIZx_5 (0x20U << FSMC_PMEMx_MEMHIZx_Pos) /*!< 0x20000000 */
+#define FSMC_PMEMx_MEMHIZx_6 (0x40U << FSMC_PMEMx_MEMHIZx_Pos) /*!< 0x40000000 */
+#define FSMC_PMEMx_MEMHIZx_7 (0x80U << FSMC_PMEMx_MEMHIZx_Pos) /*!< 0x80000000 */
+
+/****************** Bit definition for FSMC_PATTx (x = 2 to 4) register ******************/
+#define FSMC_PATTx_ATTSETx_Pos (0U)
+#define FSMC_PATTx_ATTSETx_Msk (0xFFU << FSMC_PATTx_ATTSETx_Pos) /*!< 0x000000FF */
+#define FSMC_PATTx_ATTSETx FSMC_PATTx_ATTSETx_Msk /*!< ATTSETx[7:0] bits (Attribute memory x setup time) */
+#define FSMC_PATTx_ATTSETx_0 (0x01U << FSMC_PATTx_ATTSETx_Pos) /*!< 0x00000001 */
+#define FSMC_PATTx_ATTSETx_1 (0x02U << FSMC_PATTx_ATTSETx_Pos) /*!< 0x00000002 */
+#define FSMC_PATTx_ATTSETx_2 (0x04U << FSMC_PATTx_ATTSETx_Pos) /*!< 0x00000004 */
+#define FSMC_PATTx_ATTSETx_3 (0x08U << FSMC_PATTx_ATTSETx_Pos) /*!< 0x00000008 */
+#define FSMC_PATTx_ATTSETx_4 (0x10U << FSMC_PATTx_ATTSETx_Pos) /*!< 0x00000010 */
+#define FSMC_PATTx_ATTSETx_5 (0x20U << FSMC_PATTx_ATTSETx_Pos) /*!< 0x00000020 */
+#define FSMC_PATTx_ATTSETx_6 (0x40U << FSMC_PATTx_ATTSETx_Pos) /*!< 0x00000040 */
+#define FSMC_PATTx_ATTSETx_7 (0x80U << FSMC_PATTx_ATTSETx_Pos) /*!< 0x00000080 */
+
+#define FSMC_PATTx_ATTWAITx_Pos (8U)
+#define FSMC_PATTx_ATTWAITx_Msk (0xFFU << FSMC_PATTx_ATTWAITx_Pos) /*!< 0x0000FF00 */
+#define FSMC_PATTx_ATTWAITx FSMC_PATTx_ATTWAITx_Msk /*!< ATTWAITx[7:0] bits (Attribute memory x wait time) */
+#define FSMC_PATTx_ATTWAITx_0 (0x01U << FSMC_PATTx_ATTWAITx_Pos) /*!< 0x00000100 */
+#define FSMC_PATTx_ATTWAITx_1 (0x02U << FSMC_PATTx_ATTWAITx_Pos) /*!< 0x00000200 */
+#define FSMC_PATTx_ATTWAITx_2 (0x04U << FSMC_PATTx_ATTWAITx_Pos) /*!< 0x00000400 */
+#define FSMC_PATTx_ATTWAITx_3 (0x08U << FSMC_PATTx_ATTWAITx_Pos) /*!< 0x00000800 */
+#define FSMC_PATTx_ATTWAITx_4 (0x10U << FSMC_PATTx_ATTWAITx_Pos) /*!< 0x00001000 */
+#define FSMC_PATTx_ATTWAITx_5 (0x20U << FSMC_PATTx_ATTWAITx_Pos) /*!< 0x00002000 */
+#define FSMC_PATTx_ATTWAITx_6 (0x40U << FSMC_PATTx_ATTWAITx_Pos) /*!< 0x00004000 */
+#define FSMC_PATTx_ATTWAITx_7 (0x80U << FSMC_PATTx_ATTWAITx_Pos) /*!< 0x00008000 */
+
+#define FSMC_PATTx_ATTHOLDx_Pos (16U)
+#define FSMC_PATTx_ATTHOLDx_Msk (0xFFU << FSMC_PATTx_ATTHOLDx_Pos) /*!< 0x00FF0000 */
+#define FSMC_PATTx_ATTHOLDx FSMC_PATTx_ATTHOLDx_Msk /*!< ATTHOLDx[7:0] bits (Attribute memory x hold time) */
+#define FSMC_PATTx_ATTHOLDx_0 (0x01U << FSMC_PATTx_ATTHOLDx_Pos) /*!< 0x00010000 */
+#define FSMC_PATTx_ATTHOLDx_1 (0x02U << FSMC_PATTx_ATTHOLDx_Pos) /*!< 0x00020000 */
+#define FSMC_PATTx_ATTHOLDx_2 (0x04U << FSMC_PATTx_ATTHOLDx_Pos) /*!< 0x00040000 */
+#define FSMC_PATTx_ATTHOLDx_3 (0x08U << FSMC_PATTx_ATTHOLDx_Pos) /*!< 0x00080000 */
+#define FSMC_PATTx_ATTHOLDx_4 (0x10U << FSMC_PATTx_ATTHOLDx_Pos) /*!< 0x00100000 */
+#define FSMC_PATTx_ATTHOLDx_5 (0x20U << FSMC_PATTx_ATTHOLDx_Pos) /*!< 0x00200000 */
+#define FSMC_PATTx_ATTHOLDx_6 (0x40U << FSMC_PATTx_ATTHOLDx_Pos) /*!< 0x00400000 */
+#define FSMC_PATTx_ATTHOLDx_7 (0x80U << FSMC_PATTx_ATTHOLDx_Pos) /*!< 0x00800000 */
+
+#define FSMC_PATTx_ATTHIZx_Pos (24U)
+#define FSMC_PATTx_ATTHIZx_Msk (0xFFU << FSMC_PATTx_ATTHIZx_Pos) /*!< 0xFF000000 */
+#define FSMC_PATTx_ATTHIZx FSMC_PATTx_ATTHIZx_Msk /*!< ATTHIZx[7:0] bits (Attribute memory x databus HiZ time) */
+#define FSMC_PATTx_ATTHIZx_0 (0x01U << FSMC_PATTx_ATTHIZx_Pos) /*!< 0x01000000 */
+#define FSMC_PATTx_ATTHIZx_1 (0x02U << FSMC_PATTx_ATTHIZx_Pos) /*!< 0x02000000 */
+#define FSMC_PATTx_ATTHIZx_2 (0x04U << FSMC_PATTx_ATTHIZx_Pos) /*!< 0x04000000 */
+#define FSMC_PATTx_ATTHIZx_3 (0x08U << FSMC_PATTx_ATTHIZx_Pos) /*!< 0x08000000 */
+#define FSMC_PATTx_ATTHIZx_4 (0x10U << FSMC_PATTx_ATTHIZx_Pos) /*!< 0x10000000 */
+#define FSMC_PATTx_ATTHIZx_5 (0x20U << FSMC_PATTx_ATTHIZx_Pos) /*!< 0x20000000 */
+#define FSMC_PATTx_ATTHIZx_6 (0x40U << FSMC_PATTx_ATTHIZx_Pos) /*!< 0x40000000 */
+#define FSMC_PATTx_ATTHIZx_7 (0x80U << FSMC_PATTx_ATTHIZx_Pos) /*!< 0x80000000 */
+
+/****************** Bit definition for FSMC_PIO4 register *******************/
+#define FSMC_PIO4_IOSET4_Pos (0U)
+#define FSMC_PIO4_IOSET4_Msk (0xFFU << FSMC_PIO4_IOSET4_Pos) /*!< 0x000000FF */
+#define FSMC_PIO4_IOSET4 FSMC_PIO4_IOSET4_Msk /*!< IOSET4[7:0] bits (I/O 4 setup time) */
+#define FSMC_PIO4_IOSET4_0 (0x01U << FSMC_PIO4_IOSET4_Pos) /*!< 0x00000001 */
+#define FSMC_PIO4_IOSET4_1 (0x02U << FSMC_PIO4_IOSET4_Pos) /*!< 0x00000002 */
+#define FSMC_PIO4_IOSET4_2 (0x04U << FSMC_PIO4_IOSET4_Pos) /*!< 0x00000004 */
+#define FSMC_PIO4_IOSET4_3 (0x08U << FSMC_PIO4_IOSET4_Pos) /*!< 0x00000008 */
+#define FSMC_PIO4_IOSET4_4 (0x10U << FSMC_PIO4_IOSET4_Pos) /*!< 0x00000010 */
+#define FSMC_PIO4_IOSET4_5 (0x20U << FSMC_PIO4_IOSET4_Pos) /*!< 0x00000020 */
+#define FSMC_PIO4_IOSET4_6 (0x40U << FSMC_PIO4_IOSET4_Pos) /*!< 0x00000040 */
+#define FSMC_PIO4_IOSET4_7 (0x80U << FSMC_PIO4_IOSET4_Pos) /*!< 0x00000080 */
+
+#define FSMC_PIO4_IOWAIT4_Pos (8U)
+#define FSMC_PIO4_IOWAIT4_Msk (0xFFU << FSMC_PIO4_IOWAIT4_Pos) /*!< 0x0000FF00 */
+#define FSMC_PIO4_IOWAIT4 FSMC_PIO4_IOWAIT4_Msk /*!< IOWAIT4[7:0] bits (I/O 4 wait time) */
+#define FSMC_PIO4_IOWAIT4_0 (0x01U << FSMC_PIO4_IOWAIT4_Pos) /*!< 0x00000100 */
+#define FSMC_PIO4_IOWAIT4_1 (0x02U << FSMC_PIO4_IOWAIT4_Pos) /*!< 0x00000200 */
+#define FSMC_PIO4_IOWAIT4_2 (0x04U << FSMC_PIO4_IOWAIT4_Pos) /*!< 0x00000400 */
+#define FSMC_PIO4_IOWAIT4_3 (0x08U << FSMC_PIO4_IOWAIT4_Pos) /*!< 0x00000800 */
+#define FSMC_PIO4_IOWAIT4_4 (0x10U << FSMC_PIO4_IOWAIT4_Pos) /*!< 0x00001000 */
+#define FSMC_PIO4_IOWAIT4_5 (0x20U << FSMC_PIO4_IOWAIT4_Pos) /*!< 0x00002000 */
+#define FSMC_PIO4_IOWAIT4_6 (0x40U << FSMC_PIO4_IOWAIT4_Pos) /*!< 0x00004000 */
+#define FSMC_PIO4_IOWAIT4_7 (0x80U << FSMC_PIO4_IOWAIT4_Pos) /*!< 0x00008000 */
+
+#define FSMC_PIO4_IOHOLD4_Pos (16U)
+#define FSMC_PIO4_IOHOLD4_Msk (0xFFU << FSMC_PIO4_IOHOLD4_Pos) /*!< 0x00FF0000 */
+#define FSMC_PIO4_IOHOLD4 FSMC_PIO4_IOHOLD4_Msk /*!< IOHOLD4[7:0] bits (I/O 4 hold time) */
+#define FSMC_PIO4_IOHOLD4_0 (0x01U << FSMC_PIO4_IOHOLD4_Pos) /*!< 0x00010000 */
+#define FSMC_PIO4_IOHOLD4_1 (0x02U << FSMC_PIO4_IOHOLD4_Pos) /*!< 0x00020000 */
+#define FSMC_PIO4_IOHOLD4_2 (0x04U << FSMC_PIO4_IOHOLD4_Pos) /*!< 0x00040000 */
+#define FSMC_PIO4_IOHOLD4_3 (0x08U << FSMC_PIO4_IOHOLD4_Pos) /*!< 0x00080000 */
+#define FSMC_PIO4_IOHOLD4_4 (0x10U << FSMC_PIO4_IOHOLD4_Pos) /*!< 0x00100000 */
+#define FSMC_PIO4_IOHOLD4_5 (0x20U << FSMC_PIO4_IOHOLD4_Pos) /*!< 0x00200000 */
+#define FSMC_PIO4_IOHOLD4_6 (0x40U << FSMC_PIO4_IOHOLD4_Pos) /*!< 0x00400000 */
+#define FSMC_PIO4_IOHOLD4_7 (0x80U << FSMC_PIO4_IOHOLD4_Pos) /*!< 0x00800000 */
+
+#define FSMC_PIO4_IOHIZ4_Pos (24U)
+#define FSMC_PIO4_IOHIZ4_Msk (0xFFU << FSMC_PIO4_IOHIZ4_Pos) /*!< 0xFF000000 */
+#define FSMC_PIO4_IOHIZ4 FSMC_PIO4_IOHIZ4_Msk /*!< IOHIZ4[7:0] bits (I/O 4 databus HiZ time) */
+#define FSMC_PIO4_IOHIZ4_0 (0x01U << FSMC_PIO4_IOHIZ4_Pos) /*!< 0x01000000 */
+#define FSMC_PIO4_IOHIZ4_1 (0x02U << FSMC_PIO4_IOHIZ4_Pos) /*!< 0x02000000 */
+#define FSMC_PIO4_IOHIZ4_2 (0x04U << FSMC_PIO4_IOHIZ4_Pos) /*!< 0x04000000 */
+#define FSMC_PIO4_IOHIZ4_3 (0x08U << FSMC_PIO4_IOHIZ4_Pos) /*!< 0x08000000 */
+#define FSMC_PIO4_IOHIZ4_4 (0x10U << FSMC_PIO4_IOHIZ4_Pos) /*!< 0x10000000 */
+#define FSMC_PIO4_IOHIZ4_5 (0x20U << FSMC_PIO4_IOHIZ4_Pos) /*!< 0x20000000 */
+#define FSMC_PIO4_IOHIZ4_6 (0x40U << FSMC_PIO4_IOHIZ4_Pos) /*!< 0x40000000 */
+#define FSMC_PIO4_IOHIZ4_7 (0x80U << FSMC_PIO4_IOHIZ4_Pos) /*!< 0x80000000 */
+
+/****************** Bit definition for FSMC_ECCR2 register ******************/
+#define FSMC_ECCR2_ECC2_Pos (0U)
+#define FSMC_ECCR2_ECC2_Msk (0xFFFFFFFFU << FSMC_ECCR2_ECC2_Pos) /*!< 0xFFFFFFFF */
+#define FSMC_ECCR2_ECC2 FSMC_ECCR2_ECC2_Msk /*!< ECC result */
+
+/****************** Bit definition for FSMC_ECCR3 register ******************/
+#define FSMC_ECCR3_ECC3_Pos (0U)
+#define FSMC_ECCR3_ECC3_Msk (0xFFFFFFFFU << FSMC_ECCR3_ECC3_Pos) /*!< 0xFFFFFFFF */
+#define FSMC_ECCR3_ECC3 FSMC_ECCR3_ECC3_Msk /*!< ECC result */
+
+/******************************************************************************/
+/* */
+/* SD host Interface */
+/* */
+/******************************************************************************/
+
+/****************** Bit definition for SDIO_POWER register ******************/
+#define SDIO_POWER_PWRCTRL_Pos (0U)
+#define SDIO_POWER_PWRCTRL_Msk (0x3U << SDIO_POWER_PWRCTRL_Pos) /*!< 0x00000003 */
+#define SDIO_POWER_PWRCTRL SDIO_POWER_PWRCTRL_Msk /*!< PWRCTRL[1:0] bits (Power supply control bits) */
+#define SDIO_POWER_PWRCTRL_0 (0x1U << SDIO_POWER_PWRCTRL_Pos) /*!< 0x01 */
+#define SDIO_POWER_PWRCTRL_1 (0x2U << SDIO_POWER_PWRCTRL_Pos) /*!< 0x02 */
+
+/****************** Bit definition for SDIO_CLKCR register ******************/
+#define SDIO_CLKCR_CLKDIV_Pos (0U)
+#define SDIO_CLKCR_CLKDIV_Msk (0xFFU << SDIO_CLKCR_CLKDIV_Pos) /*!< 0x000000FF */
+#define SDIO_CLKCR_CLKDIV SDIO_CLKCR_CLKDIV_Msk /*!< Clock divide factor */
+#define SDIO_CLKCR_CLKEN_Pos (8U)
+#define SDIO_CLKCR_CLKEN_Msk (0x1U << SDIO_CLKCR_CLKEN_Pos) /*!< 0x00000100 */
+#define SDIO_CLKCR_CLKEN SDIO_CLKCR_CLKEN_Msk /*!< Clock enable bit */
+#define SDIO_CLKCR_PWRSAV_Pos (9U)
+#define SDIO_CLKCR_PWRSAV_Msk (0x1U << SDIO_CLKCR_PWRSAV_Pos) /*!< 0x00000200 */
+#define SDIO_CLKCR_PWRSAV SDIO_CLKCR_PWRSAV_Msk /*!< Power saving configuration bit */
+#define SDIO_CLKCR_BYPASS_Pos (10U)
+#define SDIO_CLKCR_BYPASS_Msk (0x1U << SDIO_CLKCR_BYPASS_Pos) /*!< 0x00000400 */
+#define SDIO_CLKCR_BYPASS SDIO_CLKCR_BYPASS_Msk /*!< Clock divider bypass enable bit */
+
+#define SDIO_CLKCR_WIDBUS_Pos (11U)
+#define SDIO_CLKCR_WIDBUS_Msk (0x3U << SDIO_CLKCR_WIDBUS_Pos) /*!< 0x00001800 */
+#define SDIO_CLKCR_WIDBUS SDIO_CLKCR_WIDBUS_Msk /*!< WIDBUS[1:0] bits (Wide bus mode enable bit) */
+#define SDIO_CLKCR_WIDBUS_0 (0x1U << SDIO_CLKCR_WIDBUS_Pos) /*!< 0x0800 */
+#define SDIO_CLKCR_WIDBUS_1 (0x2U << SDIO_CLKCR_WIDBUS_Pos) /*!< 0x1000 */
+
+#define SDIO_CLKCR_NEGEDGE_Pos (13U)
+#define SDIO_CLKCR_NEGEDGE_Msk (0x1U << SDIO_CLKCR_NEGEDGE_Pos) /*!< 0x00002000 */
+#define SDIO_CLKCR_NEGEDGE SDIO_CLKCR_NEGEDGE_Msk /*!< SDIO_CK dephasing selection bit */
+#define SDIO_CLKCR_HWFC_EN_Pos (14U)
+#define SDIO_CLKCR_HWFC_EN_Msk (0x1U << SDIO_CLKCR_HWFC_EN_Pos) /*!< 0x00004000 */
+#define SDIO_CLKCR_HWFC_EN SDIO_CLKCR_HWFC_EN_Msk /*!< HW Flow Control enable */
+
+/******************* Bit definition for SDIO_ARG register *******************/
+#define SDIO_ARG_CMDARG_Pos (0U)
+#define SDIO_ARG_CMDARG_Msk (0xFFFFFFFFU << SDIO_ARG_CMDARG_Pos) /*!< 0xFFFFFFFF */
+#define SDIO_ARG_CMDARG SDIO_ARG_CMDARG_Msk /*!< Command argument */
+
+/******************* Bit definition for SDIO_CMD register *******************/
+#define SDIO_CMD_CMDINDEX_Pos (0U)
+#define SDIO_CMD_CMDINDEX_Msk (0x3FU << SDIO_CMD_CMDINDEX_Pos) /*!< 0x0000003F */
+#define SDIO_CMD_CMDINDEX SDIO_CMD_CMDINDEX_Msk /*!< Command Index */
+
+#define SDIO_CMD_WAITRESP_Pos (6U)
+#define SDIO_CMD_WAITRESP_Msk (0x3U << SDIO_CMD_WAITRESP_Pos) /*!< 0x000000C0 */
+#define SDIO_CMD_WAITRESP SDIO_CMD_WAITRESP_Msk /*!< WAITRESP[1:0] bits (Wait for response bits) */
+#define SDIO_CMD_WAITRESP_0 (0x1U << SDIO_CMD_WAITRESP_Pos) /*!< 0x0040 */
+#define SDIO_CMD_WAITRESP_1 (0x2U << SDIO_CMD_WAITRESP_Pos) /*!< 0x0080 */
+
+#define SDIO_CMD_WAITINT_Pos (8U)
+#define SDIO_CMD_WAITINT_Msk (0x1U << SDIO_CMD_WAITINT_Pos) /*!< 0x00000100 */
+#define SDIO_CMD_WAITINT SDIO_CMD_WAITINT_Msk /*!< CPSM Waits for Interrupt Request */
+#define SDIO_CMD_WAITPEND_Pos (9U)
+#define SDIO_CMD_WAITPEND_Msk (0x1U << SDIO_CMD_WAITPEND_Pos) /*!< 0x00000200 */
+#define SDIO_CMD_WAITPEND SDIO_CMD_WAITPEND_Msk /*!< CPSM Waits for ends of data transfer (CmdPend internal signal) */
+#define SDIO_CMD_CPSMEN_Pos (10U)
+#define SDIO_CMD_CPSMEN_Msk (0x1U << SDIO_CMD_CPSMEN_Pos) /*!< 0x00000400 */
+#define SDIO_CMD_CPSMEN SDIO_CMD_CPSMEN_Msk /*!< Command path state machine (CPSM) Enable bit */
+#define SDIO_CMD_SDIOSUSPEND_Pos (11U)
+#define SDIO_CMD_SDIOSUSPEND_Msk (0x1U << SDIO_CMD_SDIOSUSPEND_Pos) /*!< 0x00000800 */
+#define SDIO_CMD_SDIOSUSPEND SDIO_CMD_SDIOSUSPEND_Msk /*!< SD I/O suspend command */
+#define SDIO_CMD_ENCMDCOMPL_Pos (12U)
+#define SDIO_CMD_ENCMDCOMPL_Msk (0x1U << SDIO_CMD_ENCMDCOMPL_Pos) /*!< 0x00001000 */
+#define SDIO_CMD_ENCMDCOMPL SDIO_CMD_ENCMDCOMPL_Msk /*!< Enable CMD completion */
+#define SDIO_CMD_NIEN_Pos (13U)
+#define SDIO_CMD_NIEN_Msk (0x1U << SDIO_CMD_NIEN_Pos) /*!< 0x00002000 */
+#define SDIO_CMD_NIEN SDIO_CMD_NIEN_Msk /*!< Not Interrupt Enable */
+#define SDIO_CMD_CEATACMD_Pos (14U)
+#define SDIO_CMD_CEATACMD_Msk (0x1U << SDIO_CMD_CEATACMD_Pos) /*!< 0x00004000 */
+#define SDIO_CMD_CEATACMD SDIO_CMD_CEATACMD_Msk /*!< CE-ATA command */
+
+/***************** Bit definition for SDIO_RESPCMD register *****************/
+#define SDIO_RESPCMD_RESPCMD_Pos (0U)
+#define SDIO_RESPCMD_RESPCMD_Msk (0x3FU << SDIO_RESPCMD_RESPCMD_Pos) /*!< 0x0000003F */
+#define SDIO_RESPCMD_RESPCMD SDIO_RESPCMD_RESPCMD_Msk /*!< Response command index */
+
+/****************** Bit definition for SDIO_RESP0 register ******************/
+#define SDIO_RESP0_CARDSTATUS0_Pos (0U)
+#define SDIO_RESP0_CARDSTATUS0_Msk (0xFFFFFFFFU << SDIO_RESP0_CARDSTATUS0_Pos) /*!< 0xFFFFFFFF */
+#define SDIO_RESP0_CARDSTATUS0 SDIO_RESP0_CARDSTATUS0_Msk /*!< Card Status */
+
+/****************** Bit definition for SDIO_RESP1 register ******************/
+#define SDIO_RESP1_CARDSTATUS1_Pos (0U)
+#define SDIO_RESP1_CARDSTATUS1_Msk (0xFFFFFFFFU << SDIO_RESP1_CARDSTATUS1_Pos) /*!< 0xFFFFFFFF */
+#define SDIO_RESP1_CARDSTATUS1 SDIO_RESP1_CARDSTATUS1_Msk /*!< Card Status */
+
+/****************** Bit definition for SDIO_RESP2 register ******************/
+#define SDIO_RESP2_CARDSTATUS2_Pos (0U)
+#define SDIO_RESP2_CARDSTATUS2_Msk (0xFFFFFFFFU << SDIO_RESP2_CARDSTATUS2_Pos) /*!< 0xFFFFFFFF */
+#define SDIO_RESP2_CARDSTATUS2 SDIO_RESP2_CARDSTATUS2_Msk /*!< Card Status */
+
+/****************** Bit definition for SDIO_RESP3 register ******************/
+#define SDIO_RESP3_CARDSTATUS3_Pos (0U)
+#define SDIO_RESP3_CARDSTATUS3_Msk (0xFFFFFFFFU << SDIO_RESP3_CARDSTATUS3_Pos) /*!< 0xFFFFFFFF */
+#define SDIO_RESP3_CARDSTATUS3 SDIO_RESP3_CARDSTATUS3_Msk /*!< Card Status */
+
+/****************** Bit definition for SDIO_RESP4 register ******************/
+#define SDIO_RESP4_CARDSTATUS4_Pos (0U)
+#define SDIO_RESP4_CARDSTATUS4_Msk (0xFFFFFFFFU << SDIO_RESP4_CARDSTATUS4_Pos) /*!< 0xFFFFFFFF */
+#define SDIO_RESP4_CARDSTATUS4 SDIO_RESP4_CARDSTATUS4_Msk /*!< Card Status */
+
+/****************** Bit definition for SDIO_DTIMER register *****************/
+#define SDIO_DTIMER_DATATIME_Pos (0U)
+#define SDIO_DTIMER_DATATIME_Msk (0xFFFFFFFFU << SDIO_DTIMER_DATATIME_Pos) /*!< 0xFFFFFFFF */
+#define SDIO_DTIMER_DATATIME SDIO_DTIMER_DATATIME_Msk /*!< Data timeout period. */
+
+/****************** Bit definition for SDIO_DLEN register *******************/
+#define SDIO_DLEN_DATALENGTH_Pos (0U)
+#define SDIO_DLEN_DATALENGTH_Msk (0x1FFFFFFU << SDIO_DLEN_DATALENGTH_Pos) /*!< 0x01FFFFFF */
+#define SDIO_DLEN_DATALENGTH SDIO_DLEN_DATALENGTH_Msk /*!< Data length value */
+
+/****************** Bit definition for SDIO_DCTRL register ******************/
+#define SDIO_DCTRL_DTEN_Pos (0U)
+#define SDIO_DCTRL_DTEN_Msk (0x1U << SDIO_DCTRL_DTEN_Pos) /*!< 0x00000001 */
+#define SDIO_DCTRL_DTEN SDIO_DCTRL_DTEN_Msk /*!< Data transfer enabled bit */
+#define SDIO_DCTRL_DTDIR_Pos (1U)
+#define SDIO_DCTRL_DTDIR_Msk (0x1U << SDIO_DCTRL_DTDIR_Pos) /*!< 0x00000002 */
+#define SDIO_DCTRL_DTDIR SDIO_DCTRL_DTDIR_Msk /*!< Data transfer direction selection */
+#define SDIO_DCTRL_DTMODE_Pos (2U)
+#define SDIO_DCTRL_DTMODE_Msk (0x1U << SDIO_DCTRL_DTMODE_Pos) /*!< 0x00000004 */
+#define SDIO_DCTRL_DTMODE SDIO_DCTRL_DTMODE_Msk /*!< Data transfer mode selection */
+#define SDIO_DCTRL_DMAEN_Pos (3U)
+#define SDIO_DCTRL_DMAEN_Msk (0x1U << SDIO_DCTRL_DMAEN_Pos) /*!< 0x00000008 */
+#define SDIO_DCTRL_DMAEN SDIO_DCTRL_DMAEN_Msk /*!< DMA enabled bit */
+
+#define SDIO_DCTRL_DBLOCKSIZE_Pos (4U)
+#define SDIO_DCTRL_DBLOCKSIZE_Msk (0xFU << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x000000F0 */
+#define SDIO_DCTRL_DBLOCKSIZE SDIO_DCTRL_DBLOCKSIZE_Msk /*!< DBLOCKSIZE[3:0] bits (Data block size) */
+#define SDIO_DCTRL_DBLOCKSIZE_0 (0x1U << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0010 */
+#define SDIO_DCTRL_DBLOCKSIZE_1 (0x2U << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0020 */
+#define SDIO_DCTRL_DBLOCKSIZE_2 (0x4U << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0040 */
+#define SDIO_DCTRL_DBLOCKSIZE_3 (0x8U << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0080 */
+
+#define SDIO_DCTRL_RWSTART_Pos (8U)
+#define SDIO_DCTRL_RWSTART_Msk (0x1U << SDIO_DCTRL_RWSTART_Pos) /*!< 0x00000100 */
+#define SDIO_DCTRL_RWSTART SDIO_DCTRL_RWSTART_Msk /*!< Read wait start */
+#define SDIO_DCTRL_RWSTOP_Pos (9U)
+#define SDIO_DCTRL_RWSTOP_Msk (0x1U << SDIO_DCTRL_RWSTOP_Pos) /*!< 0x00000200 */
+#define SDIO_DCTRL_RWSTOP SDIO_DCTRL_RWSTOP_Msk /*!< Read wait stop */
+#define SDIO_DCTRL_RWMOD_Pos (10U)
+#define SDIO_DCTRL_RWMOD_Msk (0x1U << SDIO_DCTRL_RWMOD_Pos) /*!< 0x00000400 */
+#define SDIO_DCTRL_RWMOD SDIO_DCTRL_RWMOD_Msk /*!< Read wait mode */
+#define SDIO_DCTRL_SDIOEN_Pos (11U)
+#define SDIO_DCTRL_SDIOEN_Msk (0x1U << SDIO_DCTRL_SDIOEN_Pos) /*!< 0x00000800 */
+#define SDIO_DCTRL_SDIOEN SDIO_DCTRL_SDIOEN_Msk /*!< SD I/O enable functions */
+
+/****************** Bit definition for SDIO_DCOUNT register *****************/
+#define SDIO_DCOUNT_DATACOUNT_Pos (0U)
+#define SDIO_DCOUNT_DATACOUNT_Msk (0x1FFFFFFU << SDIO_DCOUNT_DATACOUNT_Pos) /*!< 0x01FFFFFF */
+#define SDIO_DCOUNT_DATACOUNT SDIO_DCOUNT_DATACOUNT_Msk /*!< Data count value */
+
+/****************** Bit definition for SDIO_STA register ********************/
+#define SDIO_STA_CCRCFAIL_Pos (0U)
+#define SDIO_STA_CCRCFAIL_Msk (0x1U << SDIO_STA_CCRCFAIL_Pos) /*!< 0x00000001 */
+#define SDIO_STA_CCRCFAIL SDIO_STA_CCRCFAIL_Msk /*!< Command response received (CRC check failed) */
+#define SDIO_STA_DCRCFAIL_Pos (1U)
+#define SDIO_STA_DCRCFAIL_Msk (0x1U << SDIO_STA_DCRCFAIL_Pos) /*!< 0x00000002 */
+#define SDIO_STA_DCRCFAIL SDIO_STA_DCRCFAIL_Msk /*!< Data block sent/received (CRC check failed) */
+#define SDIO_STA_CTIMEOUT_Pos (2U)
+#define SDIO_STA_CTIMEOUT_Msk (0x1U << SDIO_STA_CTIMEOUT_Pos) /*!< 0x00000004 */
+#define SDIO_STA_CTIMEOUT SDIO_STA_CTIMEOUT_Msk /*!< Command response timeout */
+#define SDIO_STA_DTIMEOUT_Pos (3U)
+#define SDIO_STA_DTIMEOUT_Msk (0x1U << SDIO_STA_DTIMEOUT_Pos) /*!< 0x00000008 */
+#define SDIO_STA_DTIMEOUT SDIO_STA_DTIMEOUT_Msk /*!< Data timeout */
+#define SDIO_STA_TXUNDERR_Pos (4U)
+#define SDIO_STA_TXUNDERR_Msk (0x1U << SDIO_STA_TXUNDERR_Pos) /*!< 0x00000010 */
+#define SDIO_STA_TXUNDERR SDIO_STA_TXUNDERR_Msk /*!< Transmit FIFO underrun error */
+#define SDIO_STA_RXOVERR_Pos (5U)
+#define SDIO_STA_RXOVERR_Msk (0x1U << SDIO_STA_RXOVERR_Pos) /*!< 0x00000020 */
+#define SDIO_STA_RXOVERR SDIO_STA_RXOVERR_Msk /*!< Received FIFO overrun error */
+#define SDIO_STA_CMDREND_Pos (6U)
+#define SDIO_STA_CMDREND_Msk (0x1U << SDIO_STA_CMDREND_Pos) /*!< 0x00000040 */
+#define SDIO_STA_CMDREND SDIO_STA_CMDREND_Msk /*!< Command response received (CRC check passed) */
+#define SDIO_STA_CMDSENT_Pos (7U)
+#define SDIO_STA_CMDSENT_Msk (0x1U << SDIO_STA_CMDSENT_Pos) /*!< 0x00000080 */
+#define SDIO_STA_CMDSENT SDIO_STA_CMDSENT_Msk /*!< Command sent (no response required) */
+#define SDIO_STA_DATAEND_Pos (8U)
+#define SDIO_STA_DATAEND_Msk (0x1U << SDIO_STA_DATAEND_Pos) /*!< 0x00000100 */
+#define SDIO_STA_DATAEND SDIO_STA_DATAEND_Msk /*!< Data end (data counter, SDIDCOUNT, is zero) */
+#define SDIO_STA_STBITERR_Pos (9U)
+#define SDIO_STA_STBITERR_Msk (0x1U << SDIO_STA_STBITERR_Pos) /*!< 0x00000200 */
+#define SDIO_STA_STBITERR SDIO_STA_STBITERR_Msk /*!< Start bit not detected on all data signals in wide bus mode */
+#define SDIO_STA_DBCKEND_Pos (10U)
+#define SDIO_STA_DBCKEND_Msk (0x1U << SDIO_STA_DBCKEND_Pos) /*!< 0x00000400 */
+#define SDIO_STA_DBCKEND SDIO_STA_DBCKEND_Msk /*!< Data block sent/received (CRC check passed) */
+#define SDIO_STA_CMDACT_Pos (11U)
+#define SDIO_STA_CMDACT_Msk (0x1U << SDIO_STA_CMDACT_Pos) /*!< 0x00000800 */
+#define SDIO_STA_CMDACT SDIO_STA_CMDACT_Msk /*!< Command transfer in progress */
+#define SDIO_STA_TXACT_Pos (12U)
+#define SDIO_STA_TXACT_Msk (0x1U << SDIO_STA_TXACT_Pos) /*!< 0x00001000 */
+#define SDIO_STA_TXACT SDIO_STA_TXACT_Msk /*!< Data transmit in progress */
+#define SDIO_STA_RXACT_Pos (13U)
+#define SDIO_STA_RXACT_Msk (0x1U << SDIO_STA_RXACT_Pos) /*!< 0x00002000 */
+#define SDIO_STA_RXACT SDIO_STA_RXACT_Msk /*!< Data receive in progress */
+#define SDIO_STA_TXFIFOHE_Pos (14U)
+#define SDIO_STA_TXFIFOHE_Msk (0x1U << SDIO_STA_TXFIFOHE_Pos) /*!< 0x00004000 */
+#define SDIO_STA_TXFIFOHE SDIO_STA_TXFIFOHE_Msk /*!< Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
+#define SDIO_STA_RXFIFOHF_Pos (15U)
+#define SDIO_STA_RXFIFOHF_Msk (0x1U << SDIO_STA_RXFIFOHF_Pos) /*!< 0x00008000 */
+#define SDIO_STA_RXFIFOHF SDIO_STA_RXFIFOHF_Msk /*!< Receive FIFO Half Full: there are at least 8 words in the FIFO */
+#define SDIO_STA_TXFIFOF_Pos (16U)
+#define SDIO_STA_TXFIFOF_Msk (0x1U << SDIO_STA_TXFIFOF_Pos) /*!< 0x00010000 */
+#define SDIO_STA_TXFIFOF SDIO_STA_TXFIFOF_Msk /*!< Transmit FIFO full */
+#define SDIO_STA_RXFIFOF_Pos (17U)
+#define SDIO_STA_RXFIFOF_Msk (0x1U << SDIO_STA_RXFIFOF_Pos) /*!< 0x00020000 */
+#define SDIO_STA_RXFIFOF SDIO_STA_RXFIFOF_Msk /*!< Receive FIFO full */
+#define SDIO_STA_TXFIFOE_Pos (18U)
+#define SDIO_STA_TXFIFOE_Msk (0x1U << SDIO_STA_TXFIFOE_Pos) /*!< 0x00040000 */
+#define SDIO_STA_TXFIFOE SDIO_STA_TXFIFOE_Msk /*!< Transmit FIFO empty */
+#define SDIO_STA_RXFIFOE_Pos (19U)
+#define SDIO_STA_RXFIFOE_Msk (0x1U << SDIO_STA_RXFIFOE_Pos) /*!< 0x00080000 */
+#define SDIO_STA_RXFIFOE SDIO_STA_RXFIFOE_Msk /*!< Receive FIFO empty */
+#define SDIO_STA_TXDAVL_Pos (20U)
+#define SDIO_STA_TXDAVL_Msk (0x1U << SDIO_STA_TXDAVL_Pos) /*!< 0x00100000 */
+#define SDIO_STA_TXDAVL SDIO_STA_TXDAVL_Msk /*!< Data available in transmit FIFO */
+#define SDIO_STA_RXDAVL_Pos (21U)
+#define SDIO_STA_RXDAVL_Msk (0x1U << SDIO_STA_RXDAVL_Pos) /*!< 0x00200000 */
+#define SDIO_STA_RXDAVL SDIO_STA_RXDAVL_Msk /*!< Data available in receive FIFO */
+#define SDIO_STA_SDIOIT_Pos (22U)
+#define SDIO_STA_SDIOIT_Msk (0x1U << SDIO_STA_SDIOIT_Pos) /*!< 0x00400000 */
+#define SDIO_STA_SDIOIT SDIO_STA_SDIOIT_Msk /*!< SDIO interrupt received */
+#define SDIO_STA_CEATAEND_Pos (23U)
+#define SDIO_STA_CEATAEND_Msk (0x1U << SDIO_STA_CEATAEND_Pos) /*!< 0x00800000 */
+#define SDIO_STA_CEATAEND SDIO_STA_CEATAEND_Msk /*!< CE-ATA command completion signal received for CMD61 */
+
+/******************* Bit definition for SDIO_ICR register *******************/
+#define SDIO_ICR_CCRCFAILC_Pos (0U)
+#define SDIO_ICR_CCRCFAILC_Msk (0x1U << SDIO_ICR_CCRCFAILC_Pos) /*!< 0x00000001 */
+#define SDIO_ICR_CCRCFAILC SDIO_ICR_CCRCFAILC_Msk /*!< CCRCFAIL flag clear bit */
+#define SDIO_ICR_DCRCFAILC_Pos (1U)
+#define SDIO_ICR_DCRCFAILC_Msk (0x1U << SDIO_ICR_DCRCFAILC_Pos) /*!< 0x00000002 */
+#define SDIO_ICR_DCRCFAILC SDIO_ICR_DCRCFAILC_Msk /*!< DCRCFAIL flag clear bit */
+#define SDIO_ICR_CTIMEOUTC_Pos (2U)
+#define SDIO_ICR_CTIMEOUTC_Msk (0x1U << SDIO_ICR_CTIMEOUTC_Pos) /*!< 0x00000004 */
+#define SDIO_ICR_CTIMEOUTC SDIO_ICR_CTIMEOUTC_Msk /*!< CTIMEOUT flag clear bit */
+#define SDIO_ICR_DTIMEOUTC_Pos (3U)
+#define SDIO_ICR_DTIMEOUTC_Msk (0x1U << SDIO_ICR_DTIMEOUTC_Pos) /*!< 0x00000008 */
+#define SDIO_ICR_DTIMEOUTC SDIO_ICR_DTIMEOUTC_Msk /*!< DTIMEOUT flag clear bit */
+#define SDIO_ICR_TXUNDERRC_Pos (4U)
+#define SDIO_ICR_TXUNDERRC_Msk (0x1U << SDIO_ICR_TXUNDERRC_Pos) /*!< 0x00000010 */
+#define SDIO_ICR_TXUNDERRC SDIO_ICR_TXUNDERRC_Msk /*!< TXUNDERR flag clear bit */
+#define SDIO_ICR_RXOVERRC_Pos (5U)
+#define SDIO_ICR_RXOVERRC_Msk (0x1U << SDIO_ICR_RXOVERRC_Pos) /*!< 0x00000020 */
+#define SDIO_ICR_RXOVERRC SDIO_ICR_RXOVERRC_Msk /*!< RXOVERR flag clear bit */
+#define SDIO_ICR_CMDRENDC_Pos (6U)
+#define SDIO_ICR_CMDRENDC_Msk (0x1U << SDIO_ICR_CMDRENDC_Pos) /*!< 0x00000040 */
+#define SDIO_ICR_CMDRENDC SDIO_ICR_CMDRENDC_Msk /*!< CMDREND flag clear bit */
+#define SDIO_ICR_CMDSENTC_Pos (7U)
+#define SDIO_ICR_CMDSENTC_Msk (0x1U << SDIO_ICR_CMDSENTC_Pos) /*!< 0x00000080 */
+#define SDIO_ICR_CMDSENTC SDIO_ICR_CMDSENTC_Msk /*!< CMDSENT flag clear bit */
+#define SDIO_ICR_DATAENDC_Pos (8U)
+#define SDIO_ICR_DATAENDC_Msk (0x1U << SDIO_ICR_DATAENDC_Pos) /*!< 0x00000100 */
+#define SDIO_ICR_DATAENDC SDIO_ICR_DATAENDC_Msk /*!< DATAEND flag clear bit */
+#define SDIO_ICR_STBITERRC_Pos (9U)
+#define SDIO_ICR_STBITERRC_Msk (0x1U << SDIO_ICR_STBITERRC_Pos) /*!< 0x00000200 */
+#define SDIO_ICR_STBITERRC SDIO_ICR_STBITERRC_Msk /*!< STBITERR flag clear bit */
+#define SDIO_ICR_DBCKENDC_Pos (10U)
+#define SDIO_ICR_DBCKENDC_Msk (0x1U << SDIO_ICR_DBCKENDC_Pos) /*!< 0x00000400 */
+#define SDIO_ICR_DBCKENDC SDIO_ICR_DBCKENDC_Msk /*!< DBCKEND flag clear bit */
+#define SDIO_ICR_SDIOITC_Pos (22U)
+#define SDIO_ICR_SDIOITC_Msk (0x1U << SDIO_ICR_SDIOITC_Pos) /*!< 0x00400000 */
+#define SDIO_ICR_SDIOITC SDIO_ICR_SDIOITC_Msk /*!< SDIOIT flag clear bit */
+#define SDIO_ICR_CEATAENDC_Pos (23U)
+#define SDIO_ICR_CEATAENDC_Msk (0x1U << SDIO_ICR_CEATAENDC_Pos) /*!< 0x00800000 */
+#define SDIO_ICR_CEATAENDC SDIO_ICR_CEATAENDC_Msk /*!< CEATAEND flag clear bit */
+
+/****************** Bit definition for SDIO_MASK register *******************/
+#define SDIO_MASK_CCRCFAILIE_Pos (0U)
+#define SDIO_MASK_CCRCFAILIE_Msk (0x1U << SDIO_MASK_CCRCFAILIE_Pos) /*!< 0x00000001 */
+#define SDIO_MASK_CCRCFAILIE SDIO_MASK_CCRCFAILIE_Msk /*!< Command CRC Fail Interrupt Enable */
+#define SDIO_MASK_DCRCFAILIE_Pos (1U)
+#define SDIO_MASK_DCRCFAILIE_Msk (0x1U << SDIO_MASK_DCRCFAILIE_Pos) /*!< 0x00000002 */
+#define SDIO_MASK_DCRCFAILIE SDIO_MASK_DCRCFAILIE_Msk /*!< Data CRC Fail Interrupt Enable */
+#define SDIO_MASK_CTIMEOUTIE_Pos (2U)
+#define SDIO_MASK_CTIMEOUTIE_Msk (0x1U << SDIO_MASK_CTIMEOUTIE_Pos) /*!< 0x00000004 */
+#define SDIO_MASK_CTIMEOUTIE SDIO_MASK_CTIMEOUTIE_Msk /*!< Command TimeOut Interrupt Enable */
+#define SDIO_MASK_DTIMEOUTIE_Pos (3U)
+#define SDIO_MASK_DTIMEOUTIE_Msk (0x1U << SDIO_MASK_DTIMEOUTIE_Pos) /*!< 0x00000008 */
+#define SDIO_MASK_DTIMEOUTIE SDIO_MASK_DTIMEOUTIE_Msk /*!< Data TimeOut Interrupt Enable */
+#define SDIO_MASK_TXUNDERRIE_Pos (4U)
+#define SDIO_MASK_TXUNDERRIE_Msk (0x1U << SDIO_MASK_TXUNDERRIE_Pos) /*!< 0x00000010 */
+#define SDIO_MASK_TXUNDERRIE SDIO_MASK_TXUNDERRIE_Msk /*!< Tx FIFO UnderRun Error Interrupt Enable */
+#define SDIO_MASK_RXOVERRIE_Pos (5U)
+#define SDIO_MASK_RXOVERRIE_Msk (0x1U << SDIO_MASK_RXOVERRIE_Pos) /*!< 0x00000020 */
+#define SDIO_MASK_RXOVERRIE SDIO_MASK_RXOVERRIE_Msk /*!< Rx FIFO OverRun Error Interrupt Enable */
+#define SDIO_MASK_CMDRENDIE_Pos (6U)
+#define SDIO_MASK_CMDRENDIE_Msk (0x1U << SDIO_MASK_CMDRENDIE_Pos) /*!< 0x00000040 */
+#define SDIO_MASK_CMDRENDIE SDIO_MASK_CMDRENDIE_Msk /*!< Command Response Received Interrupt Enable */
+#define SDIO_MASK_CMDSENTIE_Pos (7U)
+#define SDIO_MASK_CMDSENTIE_Msk (0x1U << SDIO_MASK_CMDSENTIE_Pos) /*!< 0x00000080 */
+#define SDIO_MASK_CMDSENTIE SDIO_MASK_CMDSENTIE_Msk /*!< Command Sent Interrupt Enable */
+#define SDIO_MASK_DATAENDIE_Pos (8U)
+#define SDIO_MASK_DATAENDIE_Msk (0x1U << SDIO_MASK_DATAENDIE_Pos) /*!< 0x00000100 */
+#define SDIO_MASK_DATAENDIE SDIO_MASK_DATAENDIE_Msk /*!< Data End Interrupt Enable */
+#define SDIO_MASK_STBITERRIE_Pos (9U)
+#define SDIO_MASK_STBITERRIE_Msk (0x1U << SDIO_MASK_STBITERRIE_Pos) /*!< 0x00000200 */
+#define SDIO_MASK_STBITERRIE SDIO_MASK_STBITERRIE_Msk /*!< Start Bit Error Interrupt Enable */
+#define SDIO_MASK_DBCKENDIE_Pos (10U)
+#define SDIO_MASK_DBCKENDIE_Msk (0x1U << SDIO_MASK_DBCKENDIE_Pos) /*!< 0x00000400 */
+#define SDIO_MASK_DBCKENDIE SDIO_MASK_DBCKENDIE_Msk /*!< Data Block End Interrupt Enable */
+#define SDIO_MASK_CMDACTIE_Pos (11U)
+#define SDIO_MASK_CMDACTIE_Msk (0x1U << SDIO_MASK_CMDACTIE_Pos) /*!< 0x00000800 */
+#define SDIO_MASK_CMDACTIE SDIO_MASK_CMDACTIE_Msk /*!< Command Acting Interrupt Enable */
+#define SDIO_MASK_TXACTIE_Pos (12U)
+#define SDIO_MASK_TXACTIE_Msk (0x1U << SDIO_MASK_TXACTIE_Pos) /*!< 0x00001000 */
+#define SDIO_MASK_TXACTIE SDIO_MASK_TXACTIE_Msk /*!< Data Transmit Acting Interrupt Enable */
+#define SDIO_MASK_RXACTIE_Pos (13U)
+#define SDIO_MASK_RXACTIE_Msk (0x1U << SDIO_MASK_RXACTIE_Pos) /*!< 0x00002000 */
+#define SDIO_MASK_RXACTIE SDIO_MASK_RXACTIE_Msk /*!< Data receive acting interrupt enabled */
+#define SDIO_MASK_TXFIFOHEIE_Pos (14U)
+#define SDIO_MASK_TXFIFOHEIE_Msk (0x1U << SDIO_MASK_TXFIFOHEIE_Pos) /*!< 0x00004000 */
+#define SDIO_MASK_TXFIFOHEIE SDIO_MASK_TXFIFOHEIE_Msk /*!< Tx FIFO Half Empty interrupt Enable */
+#define SDIO_MASK_RXFIFOHFIE_Pos (15U)
+#define SDIO_MASK_RXFIFOHFIE_Msk (0x1U << SDIO_MASK_RXFIFOHFIE_Pos) /*!< 0x00008000 */
+#define SDIO_MASK_RXFIFOHFIE SDIO_MASK_RXFIFOHFIE_Msk /*!< Rx FIFO Half Full interrupt Enable */
+#define SDIO_MASK_TXFIFOFIE_Pos (16U)
+#define SDIO_MASK_TXFIFOFIE_Msk (0x1U << SDIO_MASK_TXFIFOFIE_Pos) /*!< 0x00010000 */
+#define SDIO_MASK_TXFIFOFIE SDIO_MASK_TXFIFOFIE_Msk /*!< Tx FIFO Full interrupt Enable */
+#define SDIO_MASK_RXFIFOFIE_Pos (17U)
+#define SDIO_MASK_RXFIFOFIE_Msk (0x1U << SDIO_MASK_RXFIFOFIE_Pos) /*!< 0x00020000 */
+#define SDIO_MASK_RXFIFOFIE SDIO_MASK_RXFIFOFIE_Msk /*!< Rx FIFO Full interrupt Enable */
+#define SDIO_MASK_TXFIFOEIE_Pos (18U)
+#define SDIO_MASK_TXFIFOEIE_Msk (0x1U << SDIO_MASK_TXFIFOEIE_Pos) /*!< 0x00040000 */
+#define SDIO_MASK_TXFIFOEIE SDIO_MASK_TXFIFOEIE_Msk /*!< Tx FIFO Empty interrupt Enable */
+#define SDIO_MASK_RXFIFOEIE_Pos (19U)
+#define SDIO_MASK_RXFIFOEIE_Msk (0x1U << SDIO_MASK_RXFIFOEIE_Pos) /*!< 0x00080000 */
+#define SDIO_MASK_RXFIFOEIE SDIO_MASK_RXFIFOEIE_Msk /*!< Rx FIFO Empty interrupt Enable */
+#define SDIO_MASK_TXDAVLIE_Pos (20U)
+#define SDIO_MASK_TXDAVLIE_Msk (0x1U << SDIO_MASK_TXDAVLIE_Pos) /*!< 0x00100000 */
+#define SDIO_MASK_TXDAVLIE SDIO_MASK_TXDAVLIE_Msk /*!< Data available in Tx FIFO interrupt Enable */
+#define SDIO_MASK_RXDAVLIE_Pos (21U)
+#define SDIO_MASK_RXDAVLIE_Msk (0x1U << SDIO_MASK_RXDAVLIE_Pos) /*!< 0x00200000 */
+#define SDIO_MASK_RXDAVLIE SDIO_MASK_RXDAVLIE_Msk /*!< Data available in Rx FIFO interrupt Enable */
+#define SDIO_MASK_SDIOITIE_Pos (22U)
+#define SDIO_MASK_SDIOITIE_Msk (0x1U << SDIO_MASK_SDIOITIE_Pos) /*!< 0x00400000 */
+#define SDIO_MASK_SDIOITIE SDIO_MASK_SDIOITIE_Msk /*!< SDIO Mode Interrupt Received interrupt Enable */
+#define SDIO_MASK_CEATAENDIE_Pos (23U)
+#define SDIO_MASK_CEATAENDIE_Msk (0x1U << SDIO_MASK_CEATAENDIE_Pos) /*!< 0x00800000 */
+#define SDIO_MASK_CEATAENDIE SDIO_MASK_CEATAENDIE_Msk /*!< CE-ATA command completion signal received Interrupt Enable */
+
+/***************** Bit definition for SDIO_FIFOCNT register *****************/
+#define SDIO_FIFOCNT_FIFOCOUNT_Pos (0U)
+#define SDIO_FIFOCNT_FIFOCOUNT_Msk (0xFFFFFFU << SDIO_FIFOCNT_FIFOCOUNT_Pos) /*!< 0x00FFFFFF */
+#define SDIO_FIFOCNT_FIFOCOUNT SDIO_FIFOCNT_FIFOCOUNT_Msk /*!< Remaining number of words to be written to or read from the FIFO */
+
+/****************** Bit definition for SDIO_FIFO register *******************/
+#define SDIO_FIFO_FIFODATA_Pos (0U)
+#define SDIO_FIFO_FIFODATA_Msk (0xFFFFFFFFU << SDIO_FIFO_FIFODATA_Pos) /*!< 0xFFFFFFFF */
+#define SDIO_FIFO_FIFODATA SDIO_FIFO_FIFODATA_Msk /*!< Receive and transmit FIFO data */
+
+
+
+/******************************************************************************/
+/* */
+/* Serial Peripheral Interface */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for SPI_CR1 register ********************/
+#define SPI_CR1_CPHA_Pos (0U)
+#define SPI_CR1_CPHA_Msk (0x1U << SPI_CR1_CPHA_Pos) /*!< 0x00000001 */
+#define SPI_CR1_CPHA SPI_CR1_CPHA_Msk /*!< Clock Phase */
+#define SPI_CR1_CPOL_Pos (1U)
+#define SPI_CR1_CPOL_Msk (0x1U << SPI_CR1_CPOL_Pos) /*!< 0x00000002 */
+#define SPI_CR1_CPOL SPI_CR1_CPOL_Msk /*!< Clock Polarity */
+#define SPI_CR1_MSTR_Pos (2U)
+#define SPI_CR1_MSTR_Msk (0x1U << SPI_CR1_MSTR_Pos) /*!< 0x00000004 */
+#define SPI_CR1_MSTR SPI_CR1_MSTR_Msk /*!< Master Selection */
+
+#define SPI_CR1_BR_Pos (3U)
+#define SPI_CR1_BR_Msk (0x7U << SPI_CR1_BR_Pos) /*!< 0x00000038 */
+#define SPI_CR1_BR SPI_CR1_BR_Msk /*!< BR[2:0] bits (Baud Rate Control) */
+#define SPI_CR1_BR_0 (0x1U << SPI_CR1_BR_Pos) /*!< 0x00000008 */
+#define SPI_CR1_BR_1 (0x2U << SPI_CR1_BR_Pos) /*!< 0x00000010 */
+#define SPI_CR1_BR_2 (0x4U << SPI_CR1_BR_Pos) /*!< 0x00000020 */
+
+#define SPI_CR1_SPE_Pos (6U)
+#define SPI_CR1_SPE_Msk (0x1U << SPI_CR1_SPE_Pos) /*!< 0x00000040 */
+#define SPI_CR1_SPE SPI_CR1_SPE_Msk /*!< SPI Enable */
+#define SPI_CR1_LSBFIRST_Pos (7U)
+#define SPI_CR1_LSBFIRST_Msk (0x1U << SPI_CR1_LSBFIRST_Pos) /*!< 0x00000080 */
+#define SPI_CR1_LSBFIRST SPI_CR1_LSBFIRST_Msk /*!< Frame Format */
+#define SPI_CR1_SSI_Pos (8U)
+#define SPI_CR1_SSI_Msk (0x1U << SPI_CR1_SSI_Pos) /*!< 0x00000100 */
+#define SPI_CR1_SSI SPI_CR1_SSI_Msk /*!< Internal slave select */
+#define SPI_CR1_SSM_Pos (9U)
+#define SPI_CR1_SSM_Msk (0x1U << SPI_CR1_SSM_Pos) /*!< 0x00000200 */
+#define SPI_CR1_SSM SPI_CR1_SSM_Msk /*!< Software slave management */
+#define SPI_CR1_RXONLY_Pos (10U)
+#define SPI_CR1_RXONLY_Msk (0x1U << SPI_CR1_RXONLY_Pos) /*!< 0x00000400 */
+#define SPI_CR1_RXONLY SPI_CR1_RXONLY_Msk /*!< Receive only */
+#define SPI_CR1_DFF_Pos (11U)
+#define SPI_CR1_DFF_Msk (0x1U << SPI_CR1_DFF_Pos) /*!< 0x00000800 */
+#define SPI_CR1_DFF SPI_CR1_DFF_Msk /*!< Data Frame Format */
+#define SPI_CR1_CRCNEXT_Pos (12U)
+#define SPI_CR1_CRCNEXT_Msk (0x1U << SPI_CR1_CRCNEXT_Pos) /*!< 0x00001000 */
+#define SPI_CR1_CRCNEXT SPI_CR1_CRCNEXT_Msk /*!< Transmit CRC next */
+#define SPI_CR1_CRCEN_Pos (13U)
+#define SPI_CR1_CRCEN_Msk (0x1U << SPI_CR1_CRCEN_Pos) /*!< 0x00002000 */
+#define SPI_CR1_CRCEN SPI_CR1_CRCEN_Msk /*!< Hardware CRC calculation enable */
+#define SPI_CR1_BIDIOE_Pos (14U)
+#define SPI_CR1_BIDIOE_Msk (0x1U << SPI_CR1_BIDIOE_Pos) /*!< 0x00004000 */
+#define SPI_CR1_BIDIOE SPI_CR1_BIDIOE_Msk /*!< Output enable in bidirectional mode */
+#define SPI_CR1_BIDIMODE_Pos (15U)
+#define SPI_CR1_BIDIMODE_Msk (0x1U << SPI_CR1_BIDIMODE_Pos) /*!< 0x00008000 */
+#define SPI_CR1_BIDIMODE SPI_CR1_BIDIMODE_Msk /*!< Bidirectional data mode enable */
+
+/******************* Bit definition for SPI_CR2 register ********************/
+#define SPI_CR2_RXDMAEN_Pos (0U)
+#define SPI_CR2_RXDMAEN_Msk (0x1U << SPI_CR2_RXDMAEN_Pos) /*!< 0x00000001 */
+#define SPI_CR2_RXDMAEN SPI_CR2_RXDMAEN_Msk /*!< Rx Buffer DMA Enable */
+#define SPI_CR2_TXDMAEN_Pos (1U)
+#define SPI_CR2_TXDMAEN_Msk (0x1U << SPI_CR2_TXDMAEN_Pos) /*!< 0x00000002 */
+#define SPI_CR2_TXDMAEN SPI_CR2_TXDMAEN_Msk /*!< Tx Buffer DMA Enable */
+#define SPI_CR2_SSOE_Pos (2U)
+#define SPI_CR2_SSOE_Msk (0x1U << SPI_CR2_SSOE_Pos) /*!< 0x00000004 */
+#define SPI_CR2_SSOE SPI_CR2_SSOE_Msk /*!< SS Output Enable */
+#define SPI_CR2_ERRIE_Pos (5U)
+#define SPI_CR2_ERRIE_Msk (0x1U << SPI_CR2_ERRIE_Pos) /*!< 0x00000020 */
+#define SPI_CR2_ERRIE SPI_CR2_ERRIE_Msk /*!< Error Interrupt Enable */
+#define SPI_CR2_RXNEIE_Pos (6U)
+#define SPI_CR2_RXNEIE_Msk (0x1U << SPI_CR2_RXNEIE_Pos) /*!< 0x00000040 */
+#define SPI_CR2_RXNEIE SPI_CR2_RXNEIE_Msk /*!< RX buffer Not Empty Interrupt Enable */
+#define SPI_CR2_TXEIE_Pos (7U)
+#define SPI_CR2_TXEIE_Msk (0x1U << SPI_CR2_TXEIE_Pos) /*!< 0x00000080 */
+#define SPI_CR2_TXEIE SPI_CR2_TXEIE_Msk /*!< Tx buffer Empty Interrupt Enable */
+
+/******************** Bit definition for SPI_SR register ********************/
+#define SPI_SR_RXNE_Pos (0U)
+#define SPI_SR_RXNE_Msk (0x1U << SPI_SR_RXNE_Pos) /*!< 0x00000001 */
+#define SPI_SR_RXNE SPI_SR_RXNE_Msk /*!< Receive buffer Not Empty */
+#define SPI_SR_TXE_Pos (1U)
+#define SPI_SR_TXE_Msk (0x1U << SPI_SR_TXE_Pos) /*!< 0x00000002 */
+#define SPI_SR_TXE SPI_SR_TXE_Msk /*!< Transmit buffer Empty */
+#define SPI_SR_CHSIDE_Pos (2U)
+#define SPI_SR_CHSIDE_Msk (0x1U << SPI_SR_CHSIDE_Pos) /*!< 0x00000004 */
+#define SPI_SR_CHSIDE SPI_SR_CHSIDE_Msk /*!< Channel side */
+#define SPI_SR_UDR_Pos (3U)
+#define SPI_SR_UDR_Msk (0x1U << SPI_SR_UDR_Pos) /*!< 0x00000008 */
+#define SPI_SR_UDR SPI_SR_UDR_Msk /*!< Underrun flag */
+#define SPI_SR_CRCERR_Pos (4U)
+#define SPI_SR_CRCERR_Msk (0x1U << SPI_SR_CRCERR_Pos) /*!< 0x00000010 */
+#define SPI_SR_CRCERR SPI_SR_CRCERR_Msk /*!< CRC Error flag */
+#define SPI_SR_MODF_Pos (5U)
+#define SPI_SR_MODF_Msk (0x1U << SPI_SR_MODF_Pos) /*!< 0x00000020 */
+#define SPI_SR_MODF SPI_SR_MODF_Msk /*!< Mode fault */
+#define SPI_SR_OVR_Pos (6U)
+#define SPI_SR_OVR_Msk (0x1U << SPI_SR_OVR_Pos) /*!< 0x00000040 */
+#define SPI_SR_OVR SPI_SR_OVR_Msk /*!< Overrun flag */
+#define SPI_SR_BSY_Pos (7U)
+#define SPI_SR_BSY_Msk (0x1U << SPI_SR_BSY_Pos) /*!< 0x00000080 */
+#define SPI_SR_BSY SPI_SR_BSY_Msk /*!< Busy flag */
+
+/******************** Bit definition for SPI_DR register ********************/
+#define SPI_DR_DR_Pos (0U)
+#define SPI_DR_DR_Msk (0xFFFFU << SPI_DR_DR_Pos) /*!< 0x0000FFFF */
+#define SPI_DR_DR SPI_DR_DR_Msk /*!< Data Register */
+
+/******************* Bit definition for SPI_CRCPR register ******************/
+#define SPI_CRCPR_CRCPOLY_Pos (0U)
+#define SPI_CRCPR_CRCPOLY_Msk (0xFFFFU << SPI_CRCPR_CRCPOLY_Pos) /*!< 0x0000FFFF */
+#define SPI_CRCPR_CRCPOLY SPI_CRCPR_CRCPOLY_Msk /*!< CRC polynomial register */
+
+/****************** Bit definition for SPI_RXCRCR register ******************/
+#define SPI_RXCRCR_RXCRC_Pos (0U)
+#define SPI_RXCRCR_RXCRC_Msk (0xFFFFU << SPI_RXCRCR_RXCRC_Pos) /*!< 0x0000FFFF */
+#define SPI_RXCRCR_RXCRC SPI_RXCRCR_RXCRC_Msk /*!< Rx CRC Register */
+
+/****************** Bit definition for SPI_TXCRCR register ******************/
+#define SPI_TXCRCR_TXCRC_Pos (0U)
+#define SPI_TXCRCR_TXCRC_Msk (0xFFFFU << SPI_TXCRCR_TXCRC_Pos) /*!< 0x0000FFFF */
+#define SPI_TXCRCR_TXCRC SPI_TXCRCR_TXCRC_Msk /*!< Tx CRC Register */
+
+/****************** Bit definition for SPI_I2SCFGR register *****************/
+#define SPI_I2SCFGR_I2SMOD_Pos (11U)
+#define SPI_I2SCFGR_I2SMOD_Msk (0x1U << SPI_I2SCFGR_I2SMOD_Pos) /*!< 0x00000800 */
+#define SPI_I2SCFGR_I2SMOD SPI_I2SCFGR_I2SMOD_Msk /*!< I2S mode selection */
+
+
+/******************************************************************************/
+/* */
+/* Inter-integrated Circuit Interface */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for I2C_CR1 register ********************/
+#define I2C_CR1_PE_Pos (0U)
+#define I2C_CR1_PE_Msk (0x1U << I2C_CR1_PE_Pos) /*!< 0x00000001 */
+#define I2C_CR1_PE I2C_CR1_PE_Msk /*!< Peripheral Enable */
+#define I2C_CR1_SMBUS_Pos (1U)
+#define I2C_CR1_SMBUS_Msk (0x1U << I2C_CR1_SMBUS_Pos) /*!< 0x00000002 */
+#define I2C_CR1_SMBUS I2C_CR1_SMBUS_Msk /*!< SMBus Mode */
+#define I2C_CR1_SMBTYPE_Pos (3U)
+#define I2C_CR1_SMBTYPE_Msk (0x1U << I2C_CR1_SMBTYPE_Pos) /*!< 0x00000008 */
+#define I2C_CR1_SMBTYPE I2C_CR1_SMBTYPE_Msk /*!< SMBus Type */
+#define I2C_CR1_ENARP_Pos (4U)
+#define I2C_CR1_ENARP_Msk (0x1U << I2C_CR1_ENARP_Pos) /*!< 0x00000010 */
+#define I2C_CR1_ENARP I2C_CR1_ENARP_Msk /*!< ARP Enable */
+#define I2C_CR1_ENPEC_Pos (5U)
+#define I2C_CR1_ENPEC_Msk (0x1U << I2C_CR1_ENPEC_Pos) /*!< 0x00000020 */
+#define I2C_CR1_ENPEC I2C_CR1_ENPEC_Msk /*!< PEC Enable */
+#define I2C_CR1_ENGC_Pos (6U)
+#define I2C_CR1_ENGC_Msk (0x1U << I2C_CR1_ENGC_Pos) /*!< 0x00000040 */
+#define I2C_CR1_ENGC I2C_CR1_ENGC_Msk /*!< General Call Enable */
+#define I2C_CR1_NOSTRETCH_Pos (7U)
+#define I2C_CR1_NOSTRETCH_Msk (0x1U << I2C_CR1_NOSTRETCH_Pos) /*!< 0x00000080 */
+#define I2C_CR1_NOSTRETCH I2C_CR1_NOSTRETCH_Msk /*!< Clock Stretching Disable (Slave mode) */
+#define I2C_CR1_START_Pos (8U)
+#define I2C_CR1_START_Msk (0x1U << I2C_CR1_START_Pos) /*!< 0x00000100 */
+#define I2C_CR1_START I2C_CR1_START_Msk /*!< Start Generation */
+#define I2C_CR1_STOP_Pos (9U)
+#define I2C_CR1_STOP_Msk (0x1U << I2C_CR1_STOP_Pos) /*!< 0x00000200 */
+#define I2C_CR1_STOP I2C_CR1_STOP_Msk /*!< Stop Generation */
+#define I2C_CR1_ACK_Pos (10U)
+#define I2C_CR1_ACK_Msk (0x1U << I2C_CR1_ACK_Pos) /*!< 0x00000400 */
+#define I2C_CR1_ACK I2C_CR1_ACK_Msk /*!< Acknowledge Enable */
+#define I2C_CR1_POS_Pos (11U)
+#define I2C_CR1_POS_Msk (0x1U << I2C_CR1_POS_Pos) /*!< 0x00000800 */
+#define I2C_CR1_POS I2C_CR1_POS_Msk /*!< Acknowledge/PEC Position (for data reception) */
+#define I2C_CR1_PEC_Pos (12U)
+#define I2C_CR1_PEC_Msk (0x1U << I2C_CR1_PEC_Pos) /*!< 0x00001000 */
+#define I2C_CR1_PEC I2C_CR1_PEC_Msk /*!< Packet Error Checking */
+#define I2C_CR1_ALERT_Pos (13U)
+#define I2C_CR1_ALERT_Msk (0x1U << I2C_CR1_ALERT_Pos) /*!< 0x00002000 */
+#define I2C_CR1_ALERT I2C_CR1_ALERT_Msk /*!< SMBus Alert */
+#define I2C_CR1_SWRST_Pos (15U)
+#define I2C_CR1_SWRST_Msk (0x1U << I2C_CR1_SWRST_Pos) /*!< 0x00008000 */
+#define I2C_CR1_SWRST I2C_CR1_SWRST_Msk /*!< Software Reset */
+
+/******************* Bit definition for I2C_CR2 register ********************/
+#define I2C_CR2_FREQ_Pos (0U)
+#define I2C_CR2_FREQ_Msk (0x3FU << I2C_CR2_FREQ_Pos) /*!< 0x0000003F */
+#define I2C_CR2_FREQ I2C_CR2_FREQ_Msk /*!< FREQ[5:0] bits (Peripheral Clock Frequency) */
+#define I2C_CR2_FREQ_0 (0x01U << I2C_CR2_FREQ_Pos) /*!< 0x00000001 */
+#define I2C_CR2_FREQ_1 (0x02U << I2C_CR2_FREQ_Pos) /*!< 0x00000002 */
+#define I2C_CR2_FREQ_2 (0x04U << I2C_CR2_FREQ_Pos) /*!< 0x00000004 */
+#define I2C_CR2_FREQ_3 (0x08U << I2C_CR2_FREQ_Pos) /*!< 0x00000008 */
+#define I2C_CR2_FREQ_4 (0x10U << I2C_CR2_FREQ_Pos) /*!< 0x00000010 */
+#define I2C_CR2_FREQ_5 (0x20U << I2C_CR2_FREQ_Pos) /*!< 0x00000020 */
+
+#define I2C_CR2_ITERREN_Pos (8U)
+#define I2C_CR2_ITERREN_Msk (0x1U << I2C_CR2_ITERREN_Pos) /*!< 0x00000100 */
+#define I2C_CR2_ITERREN I2C_CR2_ITERREN_Msk /*!< Error Interrupt Enable */
+#define I2C_CR2_ITEVTEN_Pos (9U)
+#define I2C_CR2_ITEVTEN_Msk (0x1U << I2C_CR2_ITEVTEN_Pos) /*!< 0x00000200 */
+#define I2C_CR2_ITEVTEN I2C_CR2_ITEVTEN_Msk /*!< Event Interrupt Enable */
+#define I2C_CR2_ITBUFEN_Pos (10U)
+#define I2C_CR2_ITBUFEN_Msk (0x1U << I2C_CR2_ITBUFEN_Pos) /*!< 0x00000400 */
+#define I2C_CR2_ITBUFEN I2C_CR2_ITBUFEN_Msk /*!< Buffer Interrupt Enable */
+#define I2C_CR2_DMAEN_Pos (11U)
+#define I2C_CR2_DMAEN_Msk (0x1U << I2C_CR2_DMAEN_Pos) /*!< 0x00000800 */
+#define I2C_CR2_DMAEN I2C_CR2_DMAEN_Msk /*!< DMA Requests Enable */
+#define I2C_CR2_LAST_Pos (12U)
+#define I2C_CR2_LAST_Msk (0x1U << I2C_CR2_LAST_Pos) /*!< 0x00001000 */
+#define I2C_CR2_LAST I2C_CR2_LAST_Msk /*!< DMA Last Transfer */
+
+/******************* Bit definition for I2C_OAR1 register *******************/
+#define I2C_OAR1_ADD1_7 ((uint32_t)0x000000FE) /*!< Interface Address */
+#define I2C_OAR1_ADD8_9 ((uint32_t)0x00000300) /*!< Interface Address */
+
+#define I2C_OAR1_ADD0_Pos (0U)
+#define I2C_OAR1_ADD0_Msk (0x1U << I2C_OAR1_ADD0_Pos) /*!< 0x00000001 */
+#define I2C_OAR1_ADD0 I2C_OAR1_ADD0_Msk /*!< Bit 0 */
+#define I2C_OAR1_ADD1_Pos (1U)
+#define I2C_OAR1_ADD1_Msk (0x1U << I2C_OAR1_ADD1_Pos) /*!< 0x00000002 */
+#define I2C_OAR1_ADD1 I2C_OAR1_ADD1_Msk /*!< Bit 1 */
+#define I2C_OAR1_ADD2_Pos (2U)
+#define I2C_OAR1_ADD2_Msk (0x1U << I2C_OAR1_ADD2_Pos) /*!< 0x00000004 */
+#define I2C_OAR1_ADD2 I2C_OAR1_ADD2_Msk /*!< Bit 2 */
+#define I2C_OAR1_ADD3_Pos (3U)
+#define I2C_OAR1_ADD3_Msk (0x1U << I2C_OAR1_ADD3_Pos) /*!< 0x00000008 */
+#define I2C_OAR1_ADD3 I2C_OAR1_ADD3_Msk /*!< Bit 3 */
+#define I2C_OAR1_ADD4_Pos (4U)
+#define I2C_OAR1_ADD4_Msk (0x1U << I2C_OAR1_ADD4_Pos) /*!< 0x00000010 */
+#define I2C_OAR1_ADD4 I2C_OAR1_ADD4_Msk /*!< Bit 4 */
+#define I2C_OAR1_ADD5_Pos (5U)
+#define I2C_OAR1_ADD5_Msk (0x1U << I2C_OAR1_ADD5_Pos) /*!< 0x00000020 */
+#define I2C_OAR1_ADD5 I2C_OAR1_ADD5_Msk /*!< Bit 5 */
+#define I2C_OAR1_ADD6_Pos (6U)
+#define I2C_OAR1_ADD6_Msk (0x1U << I2C_OAR1_ADD6_Pos) /*!< 0x00000040 */
+#define I2C_OAR1_ADD6 I2C_OAR1_ADD6_Msk /*!< Bit 6 */
+#define I2C_OAR1_ADD7_Pos (7U)
+#define I2C_OAR1_ADD7_Msk (0x1U << I2C_OAR1_ADD7_Pos) /*!< 0x00000080 */
+#define I2C_OAR1_ADD7 I2C_OAR1_ADD7_Msk /*!< Bit 7 */
+#define I2C_OAR1_ADD8_Pos (8U)
+#define I2C_OAR1_ADD8_Msk (0x1U << I2C_OAR1_ADD8_Pos) /*!< 0x00000100 */
+#define I2C_OAR1_ADD8 I2C_OAR1_ADD8_Msk /*!< Bit 8 */
+#define I2C_OAR1_ADD9_Pos (9U)
+#define I2C_OAR1_ADD9_Msk (0x1U << I2C_OAR1_ADD9_Pos) /*!< 0x00000200 */
+#define I2C_OAR1_ADD9 I2C_OAR1_ADD9_Msk /*!< Bit 9 */
+
+#define I2C_OAR1_ADDMODE_Pos (15U)
+#define I2C_OAR1_ADDMODE_Msk (0x1U << I2C_OAR1_ADDMODE_Pos) /*!< 0x00008000 */
+#define I2C_OAR1_ADDMODE I2C_OAR1_ADDMODE_Msk /*!< Addressing Mode (Slave mode) */
+
+/******************* Bit definition for I2C_OAR2 register *******************/
+#define I2C_OAR2_ENDUAL_Pos (0U)
+#define I2C_OAR2_ENDUAL_Msk (0x1U << I2C_OAR2_ENDUAL_Pos) /*!< 0x00000001 */
+#define I2C_OAR2_ENDUAL I2C_OAR2_ENDUAL_Msk /*!< Dual addressing mode enable */
+#define I2C_OAR2_ADD2_Pos (1U)
+#define I2C_OAR2_ADD2_Msk (0x7FU << I2C_OAR2_ADD2_Pos) /*!< 0x000000FE */
+#define I2C_OAR2_ADD2 I2C_OAR2_ADD2_Msk /*!< Interface address */
+
+/******************* Bit definition for I2C_SR1 register ********************/
+#define I2C_SR1_SB_Pos (0U)
+#define I2C_SR1_SB_Msk (0x1U << I2C_SR1_SB_Pos) /*!< 0x00000001 */
+#define I2C_SR1_SB I2C_SR1_SB_Msk /*!< Start Bit (Master mode) */
+#define I2C_SR1_ADDR_Pos (1U)
+#define I2C_SR1_ADDR_Msk (0x1U << I2C_SR1_ADDR_Pos) /*!< 0x00000002 */
+#define I2C_SR1_ADDR I2C_SR1_ADDR_Msk /*!< Address sent (master mode)/matched (slave mode) */
+#define I2C_SR1_BTF_Pos (2U)
+#define I2C_SR1_BTF_Msk (0x1U << I2C_SR1_BTF_Pos) /*!< 0x00000004 */
+#define I2C_SR1_BTF I2C_SR1_BTF_Msk /*!< Byte Transfer Finished */
+#define I2C_SR1_ADD10_Pos (3U)
+#define I2C_SR1_ADD10_Msk (0x1U << I2C_SR1_ADD10_Pos) /*!< 0x00000008 */
+#define I2C_SR1_ADD10 I2C_SR1_ADD10_Msk /*!< 10-bit header sent (Master mode) */
+#define I2C_SR1_STOPF_Pos (4U)
+#define I2C_SR1_STOPF_Msk (0x1U << I2C_SR1_STOPF_Pos) /*!< 0x00000010 */
+#define I2C_SR1_STOPF I2C_SR1_STOPF_Msk /*!< Stop detection (Slave mode) */
+#define I2C_SR1_RXNE_Pos (6U)
+#define I2C_SR1_RXNE_Msk (0x1U << I2C_SR1_RXNE_Pos) /*!< 0x00000040 */
+#define I2C_SR1_RXNE I2C_SR1_RXNE_Msk /*!< Data Register not Empty (receivers) */
+#define I2C_SR1_TXE_Pos (7U)
+#define I2C_SR1_TXE_Msk (0x1U << I2C_SR1_TXE_Pos) /*!< 0x00000080 */
+#define I2C_SR1_TXE I2C_SR1_TXE_Msk /*!< Data Register Empty (transmitters) */
+#define I2C_SR1_BERR_Pos (8U)
+#define I2C_SR1_BERR_Msk (0x1U << I2C_SR1_BERR_Pos) /*!< 0x00000100 */
+#define I2C_SR1_BERR I2C_SR1_BERR_Msk /*!< Bus Error */
+#define I2C_SR1_ARLO_Pos (9U)
+#define I2C_SR1_ARLO_Msk (0x1U << I2C_SR1_ARLO_Pos) /*!< 0x00000200 */
+#define I2C_SR1_ARLO I2C_SR1_ARLO_Msk /*!< Arbitration Lost (master mode) */
+#define I2C_SR1_AF_Pos (10U)
+#define I2C_SR1_AF_Msk (0x1U << I2C_SR1_AF_Pos) /*!< 0x00000400 */
+#define I2C_SR1_AF I2C_SR1_AF_Msk /*!< Acknowledge Failure */
+#define I2C_SR1_OVR_Pos (11U)
+#define I2C_SR1_OVR_Msk (0x1U << I2C_SR1_OVR_Pos) /*!< 0x00000800 */
+#define I2C_SR1_OVR I2C_SR1_OVR_Msk /*!< Overrun/Underrun */
+#define I2C_SR1_PECERR_Pos (12U)
+#define I2C_SR1_PECERR_Msk (0x1U << I2C_SR1_PECERR_Pos) /*!< 0x00001000 */
+#define I2C_SR1_PECERR I2C_SR1_PECERR_Msk /*!< PEC Error in reception */
+#define I2C_SR1_TIMEOUT_Pos (14U)
+#define I2C_SR1_TIMEOUT_Msk (0x1U << I2C_SR1_TIMEOUT_Pos) /*!< 0x00004000 */
+#define I2C_SR1_TIMEOUT I2C_SR1_TIMEOUT_Msk /*!< Timeout or Tlow Error */
+#define I2C_SR1_SMBALERT_Pos (15U)
+#define I2C_SR1_SMBALERT_Msk (0x1U << I2C_SR1_SMBALERT_Pos) /*!< 0x00008000 */
+#define I2C_SR1_SMBALERT I2C_SR1_SMBALERT_Msk /*!< SMBus Alert */
+
+/******************* Bit definition for I2C_SR2 register ********************/
+#define I2C_SR2_MSL_Pos (0U)
+#define I2C_SR2_MSL_Msk (0x1U << I2C_SR2_MSL_Pos) /*!< 0x00000001 */
+#define I2C_SR2_MSL I2C_SR2_MSL_Msk /*!< Master/Slave */
+#define I2C_SR2_BUSY_Pos (1U)
+#define I2C_SR2_BUSY_Msk (0x1U << I2C_SR2_BUSY_Pos) /*!< 0x00000002 */
+#define I2C_SR2_BUSY I2C_SR2_BUSY_Msk /*!< Bus Busy */
+#define I2C_SR2_TRA_Pos (2U)
+#define I2C_SR2_TRA_Msk (0x1U << I2C_SR2_TRA_Pos) /*!< 0x00000004 */
+#define I2C_SR2_TRA I2C_SR2_TRA_Msk /*!< Transmitter/Receiver */
+#define I2C_SR2_GENCALL_Pos (4U)
+#define I2C_SR2_GENCALL_Msk (0x1U << I2C_SR2_GENCALL_Pos) /*!< 0x00000010 */
+#define I2C_SR2_GENCALL I2C_SR2_GENCALL_Msk /*!< General Call Address (Slave mode) */
+#define I2C_SR2_SMBDEFAULT_Pos (5U)
+#define I2C_SR2_SMBDEFAULT_Msk (0x1U << I2C_SR2_SMBDEFAULT_Pos) /*!< 0x00000020 */
+#define I2C_SR2_SMBDEFAULT I2C_SR2_SMBDEFAULT_Msk /*!< SMBus Device Default Address (Slave mode) */
+#define I2C_SR2_SMBHOST_Pos (6U)
+#define I2C_SR2_SMBHOST_Msk (0x1U << I2C_SR2_SMBHOST_Pos) /*!< 0x00000040 */
+#define I2C_SR2_SMBHOST I2C_SR2_SMBHOST_Msk /*!< SMBus Host Header (Slave mode) */
+#define I2C_SR2_DUALF_Pos (7U)
+#define I2C_SR2_DUALF_Msk (0x1U << I2C_SR2_DUALF_Pos) /*!< 0x00000080 */
+#define I2C_SR2_DUALF I2C_SR2_DUALF_Msk /*!< Dual Flag (Slave mode) */
+#define I2C_SR2_PEC_Pos (8U)
+#define I2C_SR2_PEC_Msk (0xFFU << I2C_SR2_PEC_Pos) /*!< 0x0000FF00 */
+#define I2C_SR2_PEC I2C_SR2_PEC_Msk /*!< Packet Error Checking Register */
+
+/******************* Bit definition for I2C_CCR register ********************/
+#define I2C_CCR_CCR_Pos (0U)
+#define I2C_CCR_CCR_Msk (0xFFFU << I2C_CCR_CCR_Pos) /*!< 0x00000FFF */
+#define I2C_CCR_CCR I2C_CCR_CCR_Msk /*!< Clock Control Register in Fast/Standard mode (Master mode) */
+#define I2C_CCR_DUTY_Pos (14U)
+#define I2C_CCR_DUTY_Msk (0x1U << I2C_CCR_DUTY_Pos) /*!< 0x00004000 */
+#define I2C_CCR_DUTY I2C_CCR_DUTY_Msk /*!< Fast Mode Duty Cycle */
+#define I2C_CCR_FS_Pos (15U)
+#define I2C_CCR_FS_Msk (0x1U << I2C_CCR_FS_Pos) /*!< 0x00008000 */
+#define I2C_CCR_FS I2C_CCR_FS_Msk /*!< I2C Master Mode Selection */
+
+/****************** Bit definition for I2C_TRISE register *******************/
+#define I2C_TRISE_TRISE_Pos (0U)
+#define I2C_TRISE_TRISE_Msk (0x3FU << I2C_TRISE_TRISE_Pos) /*!< 0x0000003F */
+#define I2C_TRISE_TRISE I2C_TRISE_TRISE_Msk /*!< Maximum Rise Time in Fast/Standard mode (Master mode) */
+
+/******************************************************************************/
+/* */
+/* Universal Synchronous Asynchronous Receiver Transmitter */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for USART_SR register *******************/
+#define USART_SR_PE_Pos (0U)
+#define USART_SR_PE_Msk (0x1U << USART_SR_PE_Pos) /*!< 0x00000001 */
+#define USART_SR_PE USART_SR_PE_Msk /*!< Parity Error */
+#define USART_SR_FE_Pos (1U)
+#define USART_SR_FE_Msk (0x1U << USART_SR_FE_Pos) /*!< 0x00000002 */
+#define USART_SR_FE USART_SR_FE_Msk /*!< Framing Error */
+#define USART_SR_NE_Pos (2U)
+#define USART_SR_NE_Msk (0x1U << USART_SR_NE_Pos) /*!< 0x00000004 */
+#define USART_SR_NE USART_SR_NE_Msk /*!< Noise Error Flag */
+#define USART_SR_ORE_Pos (3U)
+#define USART_SR_ORE_Msk (0x1U << USART_SR_ORE_Pos) /*!< 0x00000008 */
+#define USART_SR_ORE USART_SR_ORE_Msk /*!< OverRun Error */
+#define USART_SR_IDLE_Pos (4U)
+#define USART_SR_IDLE_Msk (0x1U << USART_SR_IDLE_Pos) /*!< 0x00000010 */
+#define USART_SR_IDLE USART_SR_IDLE_Msk /*!< IDLE line detected */
+#define USART_SR_RXNE_Pos (5U)
+#define USART_SR_RXNE_Msk (0x1U << USART_SR_RXNE_Pos) /*!< 0x00000020 */
+#define USART_SR_RXNE USART_SR_RXNE_Msk /*!< Read Data Register Not Empty */
+#define USART_SR_TC_Pos (6U)
+#define USART_SR_TC_Msk (0x1U << USART_SR_TC_Pos) /*!< 0x00000040 */
+#define USART_SR_TC USART_SR_TC_Msk /*!< Transmission Complete */
+#define USART_SR_TXE_Pos (7U)
+#define USART_SR_TXE_Msk (0x1U << USART_SR_TXE_Pos) /*!< 0x00000080 */
+#define USART_SR_TXE USART_SR_TXE_Msk /*!< Transmit Data Register Empty */
+#define USART_SR_LBD_Pos (8U)
+#define USART_SR_LBD_Msk (0x1U << USART_SR_LBD_Pos) /*!< 0x00000100 */
+#define USART_SR_LBD USART_SR_LBD_Msk /*!< LIN Break Detection Flag */
+#define USART_SR_CTS_Pos (9U)
+#define USART_SR_CTS_Msk (0x1U << USART_SR_CTS_Pos) /*!< 0x00000200 */
+#define USART_SR_CTS USART_SR_CTS_Msk /*!< CTS Flag */
+
+/******************* Bit definition for USART_DR register *******************/
+#define USART_DR_DR_Pos (0U)
+#define USART_DR_DR_Msk (0x1FFU << USART_DR_DR_Pos) /*!< 0x000001FF */
+#define USART_DR_DR USART_DR_DR_Msk /*!< Data value */
+
+/****************** Bit definition for USART_BRR register *******************/
+#define USART_BRR_DIV_Fraction_Pos (0U)
+#define USART_BRR_DIV_Fraction_Msk (0xFU << USART_BRR_DIV_Fraction_Pos) /*!< 0x0000000F */
+#define USART_BRR_DIV_Fraction USART_BRR_DIV_Fraction_Msk /*!< Fraction of USARTDIV */
+#define USART_BRR_DIV_Mantissa_Pos (4U)
+#define USART_BRR_DIV_Mantissa_Msk (0xFFFU << USART_BRR_DIV_Mantissa_Pos) /*!< 0x0000FFF0 */
+#define USART_BRR_DIV_Mantissa USART_BRR_DIV_Mantissa_Msk /*!< Mantissa of USARTDIV */
+
+/****************** Bit definition for USART_CR1 register *******************/
+#define USART_CR1_SBK_Pos (0U)
+#define USART_CR1_SBK_Msk (0x1U << USART_CR1_SBK_Pos) /*!< 0x00000001 */
+#define USART_CR1_SBK USART_CR1_SBK_Msk /*!< Send Break */
+#define USART_CR1_RWU_Pos (1U)
+#define USART_CR1_RWU_Msk (0x1U << USART_CR1_RWU_Pos) /*!< 0x00000002 */
+#define USART_CR1_RWU USART_CR1_RWU_Msk /*!< Receiver wakeup */
+#define USART_CR1_RE_Pos (2U)
+#define USART_CR1_RE_Msk (0x1U << USART_CR1_RE_Pos) /*!< 0x00000004 */
+#define USART_CR1_RE USART_CR1_RE_Msk /*!< Receiver Enable */
+#define USART_CR1_TE_Pos (3U)
+#define USART_CR1_TE_Msk (0x1U << USART_CR1_TE_Pos) /*!< 0x00000008 */
+#define USART_CR1_TE USART_CR1_TE_Msk /*!< Transmitter Enable */
+#define USART_CR1_IDLEIE_Pos (4U)
+#define USART_CR1_IDLEIE_Msk (0x1U << USART_CR1_IDLEIE_Pos) /*!< 0x00000010 */
+#define USART_CR1_IDLEIE USART_CR1_IDLEIE_Msk /*!< IDLE Interrupt Enable */
+#define USART_CR1_RXNEIE_Pos (5U)
+#define USART_CR1_RXNEIE_Msk (0x1U << USART_CR1_RXNEIE_Pos) /*!< 0x00000020 */
+#define USART_CR1_RXNEIE USART_CR1_RXNEIE_Msk /*!< RXNE Interrupt Enable */
+#define USART_CR1_TCIE_Pos (6U)
+#define USART_CR1_TCIE_Msk (0x1U << USART_CR1_TCIE_Pos) /*!< 0x00000040 */
+#define USART_CR1_TCIE USART_CR1_TCIE_Msk /*!< Transmission Complete Interrupt Enable */
+#define USART_CR1_TXEIE_Pos (7U)
+#define USART_CR1_TXEIE_Msk (0x1U << USART_CR1_TXEIE_Pos) /*!< 0x00000080 */
+#define USART_CR1_TXEIE USART_CR1_TXEIE_Msk /*!< PE Interrupt Enable */
+#define USART_CR1_PEIE_Pos (8U)
+#define USART_CR1_PEIE_Msk (0x1U << USART_CR1_PEIE_Pos) /*!< 0x00000100 */
+#define USART_CR1_PEIE USART_CR1_PEIE_Msk /*!< PE Interrupt Enable */
+#define USART_CR1_PS_Pos (9U)
+#define USART_CR1_PS_Msk (0x1U << USART_CR1_PS_Pos) /*!< 0x00000200 */
+#define USART_CR1_PS USART_CR1_PS_Msk /*!< Parity Selection */
+#define USART_CR1_PCE_Pos (10U)
+#define USART_CR1_PCE_Msk (0x1U << USART_CR1_PCE_Pos) /*!< 0x00000400 */
+#define USART_CR1_PCE USART_CR1_PCE_Msk /*!< Parity Control Enable */
+#define USART_CR1_WAKE_Pos (11U)
+#define USART_CR1_WAKE_Msk (0x1U << USART_CR1_WAKE_Pos) /*!< 0x00000800 */
+#define USART_CR1_WAKE USART_CR1_WAKE_Msk /*!< Wakeup method */
+#define USART_CR1_M_Pos (12U)
+#define USART_CR1_M_Msk (0x1U << USART_CR1_M_Pos) /*!< 0x00001000 */
+#define USART_CR1_M USART_CR1_M_Msk /*!< Word length */
+#define USART_CR1_UE_Pos (13U)
+#define USART_CR1_UE_Msk (0x1U << USART_CR1_UE_Pos) /*!< 0x00002000 */
+#define USART_CR1_UE USART_CR1_UE_Msk /*!< USART Enable */
+
+/****************** Bit definition for USART_CR2 register *******************/
+#define USART_CR2_ADD_Pos (0U)
+#define USART_CR2_ADD_Msk (0xFU << USART_CR2_ADD_Pos) /*!< 0x0000000F */
+#define USART_CR2_ADD USART_CR2_ADD_Msk /*!< Address of the USART node */
+#define USART_CR2_LBDL_Pos (5U)
+#define USART_CR2_LBDL_Msk (0x1U << USART_CR2_LBDL_Pos) /*!< 0x00000020 */
+#define USART_CR2_LBDL USART_CR2_LBDL_Msk /*!< LIN Break Detection Length */
+#define USART_CR2_LBDIE_Pos (6U)
+#define USART_CR2_LBDIE_Msk (0x1U << USART_CR2_LBDIE_Pos) /*!< 0x00000040 */
+#define USART_CR2_LBDIE USART_CR2_LBDIE_Msk /*!< LIN Break Detection Interrupt Enable */
+#define USART_CR2_LBCL_Pos (8U)
+#define USART_CR2_LBCL_Msk (0x1U << USART_CR2_LBCL_Pos) /*!< 0x00000100 */
+#define USART_CR2_LBCL USART_CR2_LBCL_Msk /*!< Last Bit Clock pulse */
+#define USART_CR2_CPHA_Pos (9U)
+#define USART_CR2_CPHA_Msk (0x1U << USART_CR2_CPHA_Pos) /*!< 0x00000200 */
+#define USART_CR2_CPHA USART_CR2_CPHA_Msk /*!< Clock Phase */
+#define USART_CR2_CPOL_Pos (10U)
+#define USART_CR2_CPOL_Msk (0x1U << USART_CR2_CPOL_Pos) /*!< 0x00000400 */
+#define USART_CR2_CPOL USART_CR2_CPOL_Msk /*!< Clock Polarity */
+#define USART_CR2_CLKEN_Pos (11U)
+#define USART_CR2_CLKEN_Msk (0x1U << USART_CR2_CLKEN_Pos) /*!< 0x00000800 */
+#define USART_CR2_CLKEN USART_CR2_CLKEN_Msk /*!< Clock Enable */
+
+#define USART_CR2_STOP_Pos (12U)
+#define USART_CR2_STOP_Msk (0x3U << USART_CR2_STOP_Pos) /*!< 0x00003000 */
+#define USART_CR2_STOP USART_CR2_STOP_Msk /*!< STOP[1:0] bits (STOP bits) */
+#define USART_CR2_STOP_0 (0x1U << USART_CR2_STOP_Pos) /*!< 0x00001000 */
+#define USART_CR2_STOP_1 (0x2U << USART_CR2_STOP_Pos) /*!< 0x00002000 */
+
+#define USART_CR2_LINEN_Pos (14U)
+#define USART_CR2_LINEN_Msk (0x1U << USART_CR2_LINEN_Pos) /*!< 0x00004000 */
+#define USART_CR2_LINEN USART_CR2_LINEN_Msk /*!< LIN mode enable */
+
+/****************** Bit definition for USART_CR3 register *******************/
+#define USART_CR3_EIE_Pos (0U)
+#define USART_CR3_EIE_Msk (0x1U << USART_CR3_EIE_Pos) /*!< 0x00000001 */
+#define USART_CR3_EIE USART_CR3_EIE_Msk /*!< Error Interrupt Enable */
+#define USART_CR3_IREN_Pos (1U)
+#define USART_CR3_IREN_Msk (0x1U << USART_CR3_IREN_Pos) /*!< 0x00000002 */
+#define USART_CR3_IREN USART_CR3_IREN_Msk /*!< IrDA mode Enable */
+#define USART_CR3_IRLP_Pos (2U)
+#define USART_CR3_IRLP_Msk (0x1U << USART_CR3_IRLP_Pos) /*!< 0x00000004 */
+#define USART_CR3_IRLP USART_CR3_IRLP_Msk /*!< IrDA Low-Power */
+#define USART_CR3_HDSEL_Pos (3U)
+#define USART_CR3_HDSEL_Msk (0x1U << USART_CR3_HDSEL_Pos) /*!< 0x00000008 */
+#define USART_CR3_HDSEL USART_CR3_HDSEL_Msk /*!< Half-Duplex Selection */
+#define USART_CR3_NACK_Pos (4U)
+#define USART_CR3_NACK_Msk (0x1U << USART_CR3_NACK_Pos) /*!< 0x00000010 */
+#define USART_CR3_NACK USART_CR3_NACK_Msk /*!< Smartcard NACK enable */
+#define USART_CR3_SCEN_Pos (5U)
+#define USART_CR3_SCEN_Msk (0x1U << USART_CR3_SCEN_Pos) /*!< 0x00000020 */
+#define USART_CR3_SCEN USART_CR3_SCEN_Msk /*!< Smartcard mode enable */
+#define USART_CR3_DMAR_Pos (6U)
+#define USART_CR3_DMAR_Msk (0x1U << USART_CR3_DMAR_Pos) /*!< 0x00000040 */
+#define USART_CR3_DMAR USART_CR3_DMAR_Msk /*!< DMA Enable Receiver */
+#define USART_CR3_DMAT_Pos (7U)
+#define USART_CR3_DMAT_Msk (0x1U << USART_CR3_DMAT_Pos) /*!< 0x00000080 */
+#define USART_CR3_DMAT USART_CR3_DMAT_Msk /*!< DMA Enable Transmitter */
+#define USART_CR3_RTSE_Pos (8U)
+#define USART_CR3_RTSE_Msk (0x1U << USART_CR3_RTSE_Pos) /*!< 0x00000100 */
+#define USART_CR3_RTSE USART_CR3_RTSE_Msk /*!< RTS Enable */
+#define USART_CR3_CTSE_Pos (9U)
+#define USART_CR3_CTSE_Msk (0x1U << USART_CR3_CTSE_Pos) /*!< 0x00000200 */
+#define USART_CR3_CTSE USART_CR3_CTSE_Msk /*!< CTS Enable */
+#define USART_CR3_CTSIE_Pos (10U)
+#define USART_CR3_CTSIE_Msk (0x1U << USART_CR3_CTSIE_Pos) /*!< 0x00000400 */
+#define USART_CR3_CTSIE USART_CR3_CTSIE_Msk /*!< CTS Interrupt Enable */
+
+/****************** Bit definition for USART_GTPR register ******************/
+#define USART_GTPR_PSC_Pos (0U)
+#define USART_GTPR_PSC_Msk (0xFFU << USART_GTPR_PSC_Pos) /*!< 0x000000FF */
+#define USART_GTPR_PSC USART_GTPR_PSC_Msk /*!< PSC[7:0] bits (Prescaler value) */
+#define USART_GTPR_PSC_0 (0x01U << USART_GTPR_PSC_Pos) /*!< 0x00000001 */
+#define USART_GTPR_PSC_1 (0x02U << USART_GTPR_PSC_Pos) /*!< 0x00000002 */
+#define USART_GTPR_PSC_2 (0x04U << USART_GTPR_PSC_Pos) /*!< 0x00000004 */
+#define USART_GTPR_PSC_3 (0x08U << USART_GTPR_PSC_Pos) /*!< 0x00000008 */
+#define USART_GTPR_PSC_4 (0x10U << USART_GTPR_PSC_Pos) /*!< 0x00000010 */
+#define USART_GTPR_PSC_5 (0x20U << USART_GTPR_PSC_Pos) /*!< 0x00000020 */
+#define USART_GTPR_PSC_6 (0x40U << USART_GTPR_PSC_Pos) /*!< 0x00000040 */
+#define USART_GTPR_PSC_7 (0x80U << USART_GTPR_PSC_Pos) /*!< 0x00000080 */
+
+#define USART_GTPR_GT_Pos (8U)
+#define USART_GTPR_GT_Msk (0xFFU << USART_GTPR_GT_Pos) /*!< 0x0000FF00 */
+#define USART_GTPR_GT USART_GTPR_GT_Msk /*!< Guard time value */
+
+/******************************************************************************/
+/* */
+/* Debug MCU */
+/* */
+/******************************************************************************/
+
+/**************** Bit definition for DBGMCU_IDCODE register *****************/
+#define DBGMCU_IDCODE_DEV_ID_Pos (0U)
+#define DBGMCU_IDCODE_DEV_ID_Msk (0xFFFU << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */
+#define DBGMCU_IDCODE_DEV_ID DBGMCU_IDCODE_DEV_ID_Msk /*!< Device Identifier */
+
+#define DBGMCU_IDCODE_REV_ID_Pos (16U)
+#define DBGMCU_IDCODE_REV_ID_Msk (0xFFFFU << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */
+#define DBGMCU_IDCODE_REV_ID DBGMCU_IDCODE_REV_ID_Msk /*!< REV_ID[15:0] bits (Revision Identifier) */
+#define DBGMCU_IDCODE_REV_ID_0 (0x0001U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00010000 */
+#define DBGMCU_IDCODE_REV_ID_1 (0x0002U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00020000 */
+#define DBGMCU_IDCODE_REV_ID_2 (0x0004U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00040000 */
+#define DBGMCU_IDCODE_REV_ID_3 (0x0008U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00080000 */
+#define DBGMCU_IDCODE_REV_ID_4 (0x0010U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00100000 */
+#define DBGMCU_IDCODE_REV_ID_5 (0x0020U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00200000 */
+#define DBGMCU_IDCODE_REV_ID_6 (0x0040U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00400000 */
+#define DBGMCU_IDCODE_REV_ID_7 (0x0080U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00800000 */
+#define DBGMCU_IDCODE_REV_ID_8 (0x0100U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x01000000 */
+#define DBGMCU_IDCODE_REV_ID_9 (0x0200U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x02000000 */
+#define DBGMCU_IDCODE_REV_ID_10 (0x0400U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x04000000 */
+#define DBGMCU_IDCODE_REV_ID_11 (0x0800U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x08000000 */
+#define DBGMCU_IDCODE_REV_ID_12 (0x1000U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x10000000 */
+#define DBGMCU_IDCODE_REV_ID_13 (0x2000U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x20000000 */
+#define DBGMCU_IDCODE_REV_ID_14 (0x4000U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x40000000 */
+#define DBGMCU_IDCODE_REV_ID_15 (0x8000U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x80000000 */
+
+/****************** Bit definition for DBGMCU_CR register *******************/
+#define DBGMCU_CR_DBG_SLEEP_Pos (0U)
+#define DBGMCU_CR_DBG_SLEEP_Msk (0x1U << DBGMCU_CR_DBG_SLEEP_Pos) /*!< 0x00000001 */
+#define DBGMCU_CR_DBG_SLEEP DBGMCU_CR_DBG_SLEEP_Msk /*!< Debug Sleep Mode */
+#define DBGMCU_CR_DBG_STOP_Pos (1U)
+#define DBGMCU_CR_DBG_STOP_Msk (0x1U << DBGMCU_CR_DBG_STOP_Pos) /*!< 0x00000002 */
+#define DBGMCU_CR_DBG_STOP DBGMCU_CR_DBG_STOP_Msk /*!< Debug Stop Mode */
+#define DBGMCU_CR_DBG_STANDBY_Pos (2U)
+#define DBGMCU_CR_DBG_STANDBY_Msk (0x1U << DBGMCU_CR_DBG_STANDBY_Pos) /*!< 0x00000004 */
+#define DBGMCU_CR_DBG_STANDBY DBGMCU_CR_DBG_STANDBY_Msk /*!< Debug Standby mode */
+#define DBGMCU_CR_TRACE_IOEN_Pos (5U)
+#define DBGMCU_CR_TRACE_IOEN_Msk (0x1U << DBGMCU_CR_TRACE_IOEN_Pos) /*!< 0x00000020 */
+#define DBGMCU_CR_TRACE_IOEN DBGMCU_CR_TRACE_IOEN_Msk /*!< Trace Pin Assignment Control */
+
+#define DBGMCU_CR_TRACE_MODE_Pos (6U)
+#define DBGMCU_CR_TRACE_MODE_Msk (0x3U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x000000C0 */
+#define DBGMCU_CR_TRACE_MODE DBGMCU_CR_TRACE_MODE_Msk /*!< TRACE_MODE[1:0] bits (Trace Pin Assignment Control) */
+#define DBGMCU_CR_TRACE_MODE_0 (0x1U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000040 */
+#define DBGMCU_CR_TRACE_MODE_1 (0x2U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000080 */
+
+#define DBGMCU_CR_DBG_IWDG_STOP_Pos (8U)
+#define DBGMCU_CR_DBG_IWDG_STOP_Msk (0x1U << DBGMCU_CR_DBG_IWDG_STOP_Pos) /*!< 0x00000100 */
+#define DBGMCU_CR_DBG_IWDG_STOP DBGMCU_CR_DBG_IWDG_STOP_Msk /*!< Debug Independent Watchdog stopped when Core is halted */
+#define DBGMCU_CR_DBG_WWDG_STOP_Pos (9U)
+#define DBGMCU_CR_DBG_WWDG_STOP_Msk (0x1U << DBGMCU_CR_DBG_WWDG_STOP_Pos) /*!< 0x00000200 */
+#define DBGMCU_CR_DBG_WWDG_STOP DBGMCU_CR_DBG_WWDG_STOP_Msk /*!< Debug Window Watchdog stopped when Core is halted */
+#define DBGMCU_CR_DBG_TIM1_STOP_Pos (10U)
+#define DBGMCU_CR_DBG_TIM1_STOP_Msk (0x1U << DBGMCU_CR_DBG_TIM1_STOP_Pos) /*!< 0x00000400 */
+#define DBGMCU_CR_DBG_TIM1_STOP DBGMCU_CR_DBG_TIM1_STOP_Msk /*!< TIM1 counter stopped when core is halted */
+#define DBGMCU_CR_DBG_TIM2_STOP_Pos (11U)
+#define DBGMCU_CR_DBG_TIM2_STOP_Msk (0x1U << DBGMCU_CR_DBG_TIM2_STOP_Pos) /*!< 0x00000800 */
+#define DBGMCU_CR_DBG_TIM2_STOP DBGMCU_CR_DBG_TIM2_STOP_Msk /*!< TIM2 counter stopped when core is halted */
+#define DBGMCU_CR_DBG_TIM3_STOP_Pos (12U)
+#define DBGMCU_CR_DBG_TIM3_STOP_Msk (0x1U << DBGMCU_CR_DBG_TIM3_STOP_Pos) /*!< 0x00001000 */
+#define DBGMCU_CR_DBG_TIM3_STOP DBGMCU_CR_DBG_TIM3_STOP_Msk /*!< TIM3 counter stopped when core is halted */
+#define DBGMCU_CR_DBG_TIM4_STOP_Pos (13U)
+#define DBGMCU_CR_DBG_TIM4_STOP_Msk (0x1U << DBGMCU_CR_DBG_TIM4_STOP_Pos) /*!< 0x00002000 */
+#define DBGMCU_CR_DBG_TIM4_STOP DBGMCU_CR_DBG_TIM4_STOP_Msk /*!< TIM4 counter stopped when core is halted */
+#define DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT_Pos (15U)
+#define DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT_Msk (0x1U << DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT_Pos) /*!< 0x00008000 */
+#define DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT_Msk /*!< SMBUS timeout mode stopped when Core is halted */
+#define DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT_Pos (16U)
+#define DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT_Msk (0x1U << DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT_Pos) /*!< 0x00010000 */
+#define DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT_Msk /*!< SMBUS timeout mode stopped when Core is halted */
+#define DBGMCU_CR_DBG_TIM5_STOP_Pos (18U)
+#define DBGMCU_CR_DBG_TIM5_STOP_Msk (0x1U << DBGMCU_CR_DBG_TIM5_STOP_Pos) /*!< 0x00040000 */
+#define DBGMCU_CR_DBG_TIM5_STOP DBGMCU_CR_DBG_TIM5_STOP_Msk /*!< TIM5 counter stopped when core is halted */
+#define DBGMCU_CR_DBG_TIM6_STOP_Pos (19U)
+#define DBGMCU_CR_DBG_TIM6_STOP_Msk (0x1U << DBGMCU_CR_DBG_TIM6_STOP_Pos) /*!< 0x00080000 */
+#define DBGMCU_CR_DBG_TIM6_STOP DBGMCU_CR_DBG_TIM6_STOP_Msk /*!< TIM6 counter stopped when core is halted */
+#define DBGMCU_CR_DBG_TIM7_STOP_Pos (20U)
+#define DBGMCU_CR_DBG_TIM7_STOP_Msk (0x1U << DBGMCU_CR_DBG_TIM7_STOP_Pos) /*!< 0x00100000 */
+#define DBGMCU_CR_DBG_TIM7_STOP DBGMCU_CR_DBG_TIM7_STOP_Msk /*!< TIM7 counter stopped when core is halted */
+#define DBGMCU_CR_DBG_TIM9_STOP_Pos (28U)
+#define DBGMCU_CR_DBG_TIM9_STOP_Msk (0x1U << DBGMCU_CR_DBG_TIM9_STOP_Pos) /*!< 0x10000000 */
+#define DBGMCU_CR_DBG_TIM9_STOP DBGMCU_CR_DBG_TIM9_STOP_Msk /*!< Debug TIM9 stopped when Core is halted */
+#define DBGMCU_CR_DBG_TIM10_STOP_Pos (29U)
+#define DBGMCU_CR_DBG_TIM10_STOP_Msk (0x1U << DBGMCU_CR_DBG_TIM10_STOP_Pos) /*!< 0x20000000 */
+#define DBGMCU_CR_DBG_TIM10_STOP DBGMCU_CR_DBG_TIM10_STOP_Msk /*!< Debug TIM10 stopped when Core is halted */
+#define DBGMCU_CR_DBG_TIM11_STOP_Pos (30U)
+#define DBGMCU_CR_DBG_TIM11_STOP_Msk (0x1U << DBGMCU_CR_DBG_TIM11_STOP_Pos) /*!< 0x40000000 */
+#define DBGMCU_CR_DBG_TIM11_STOP DBGMCU_CR_DBG_TIM11_STOP_Msk /*!< Debug TIM11 stopped when Core is halted */
+
+/******************************************************************************/
+/* */
+/* FLASH and Option Bytes Registers */
+/* */
+/******************************************************************************/
+/******************* Bit definition for FLASH_ACR register ******************/
+#define FLASH_ACR_LATENCY_Pos (0U)
+#define FLASH_ACR_LATENCY_Msk (0x7U << FLASH_ACR_LATENCY_Pos) /*!< 0x00000007 */
+#define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk /*!< LATENCY[2:0] bits (Latency) */
+#define FLASH_ACR_LATENCY_0 (0x1U << FLASH_ACR_LATENCY_Pos) /*!< 0x00000001 */
+#define FLASH_ACR_LATENCY_1 (0x2U << FLASH_ACR_LATENCY_Pos) /*!< 0x00000002 */
+#define FLASH_ACR_LATENCY_2 (0x4U << FLASH_ACR_LATENCY_Pos) /*!< 0x00000004 */
+
+#define FLASH_ACR_HLFCYA_Pos (3U)
+#define FLASH_ACR_HLFCYA_Msk (0x1U << FLASH_ACR_HLFCYA_Pos) /*!< 0x00000008 */
+#define FLASH_ACR_HLFCYA FLASH_ACR_HLFCYA_Msk /*!< Flash Half Cycle Access Enable */
+#define FLASH_ACR_PRFTBE_Pos (4U)
+#define FLASH_ACR_PRFTBE_Msk (0x1U << FLASH_ACR_PRFTBE_Pos) /*!< 0x00000010 */
+#define FLASH_ACR_PRFTBE FLASH_ACR_PRFTBE_Msk /*!< Prefetch Buffer Enable */
+#define FLASH_ACR_PRFTBS_Pos (5U)
+#define FLASH_ACR_PRFTBS_Msk (0x1U << FLASH_ACR_PRFTBS_Pos) /*!< 0x00000020 */
+#define FLASH_ACR_PRFTBS FLASH_ACR_PRFTBS_Msk /*!< Prefetch Buffer Status */
+
+/****************** Bit definition for FLASH_KEYR register ******************/
+#define FLASH_KEYR_FKEYR_Pos (0U)
+#define FLASH_KEYR_FKEYR_Msk (0xFFFFFFFFU << FLASH_KEYR_FKEYR_Pos) /*!< 0xFFFFFFFF */
+#define FLASH_KEYR_FKEYR FLASH_KEYR_FKEYR_Msk /*!< FPEC Key */
+
+#define RDP_KEY_Pos (0U)
+#define RDP_KEY_Msk (0xA5U << RDP_KEY_Pos) /*!< 0x000000A5 */
+#define RDP_KEY RDP_KEY_Msk /*!< RDP Key */
+#define FLASH_KEY1_Pos (0U)
+#define FLASH_KEY1_Msk (0x45670123U << FLASH_KEY1_Pos) /*!< 0x45670123 */
+#define FLASH_KEY1 FLASH_KEY1_Msk /*!< FPEC Key1 */
+#define FLASH_KEY2_Pos (0U)
+#define FLASH_KEY2_Msk (0xCDEF89ABU << FLASH_KEY2_Pos) /*!< 0xCDEF89AB */
+#define FLASH_KEY2 FLASH_KEY2_Msk /*!< FPEC Key2 */
+
+/***************** Bit definition for FLASH_OPTKEYR register ****************/
+#define FLASH_OPTKEYR_OPTKEYR_Pos (0U)
+#define FLASH_OPTKEYR_OPTKEYR_Msk (0xFFFFFFFFU << FLASH_OPTKEYR_OPTKEYR_Pos) /*!< 0xFFFFFFFF */
+#define FLASH_OPTKEYR_OPTKEYR FLASH_OPTKEYR_OPTKEYR_Msk /*!< Option Byte Key */
+
+#define FLASH_OPTKEY1 FLASH_KEY1 /*!< Option Byte Key1 */
+#define FLASH_OPTKEY2 FLASH_KEY2 /*!< Option Byte Key2 */
+
+/****************** Bit definition for FLASH_SR register ********************/
+#define FLASH_SR_BSY_Pos (0U)
+#define FLASH_SR_BSY_Msk (0x1U << FLASH_SR_BSY_Pos) /*!< 0x00000001 */
+#define FLASH_SR_BSY FLASH_SR_BSY_Msk /*!< Busy */
+#define FLASH_SR_PGERR_Pos (2U)
+#define FLASH_SR_PGERR_Msk (0x1U << FLASH_SR_PGERR_Pos) /*!< 0x00000004 */
+#define FLASH_SR_PGERR FLASH_SR_PGERR_Msk /*!< Programming Error */
+#define FLASH_SR_WRPRTERR_Pos (4U)
+#define FLASH_SR_WRPRTERR_Msk (0x1U << FLASH_SR_WRPRTERR_Pos) /*!< 0x00000010 */
+#define FLASH_SR_WRPRTERR FLASH_SR_WRPRTERR_Msk /*!< Write Protection Error */
+#define FLASH_SR_EOP_Pos (5U)
+#define FLASH_SR_EOP_Msk (0x1U << FLASH_SR_EOP_Pos) /*!< 0x00000020 */
+#define FLASH_SR_EOP FLASH_SR_EOP_Msk /*!< End of operation */
+
+/******************* Bit definition for FLASH_CR register *******************/
+#define FLASH_CR_PG_Pos (0U)
+#define FLASH_CR_PG_Msk (0x1U << FLASH_CR_PG_Pos) /*!< 0x00000001 */
+#define FLASH_CR_PG FLASH_CR_PG_Msk /*!< Programming */
+#define FLASH_CR_PER_Pos (1U)
+#define FLASH_CR_PER_Msk (0x1U << FLASH_CR_PER_Pos) /*!< 0x00000002 */
+#define FLASH_CR_PER FLASH_CR_PER_Msk /*!< Page Erase */
+#define FLASH_CR_MER_Pos (2U)
+#define FLASH_CR_MER_Msk (0x1U << FLASH_CR_MER_Pos) /*!< 0x00000004 */
+#define FLASH_CR_MER FLASH_CR_MER_Msk /*!< Mass Erase */
+#define FLASH_CR_OPTPG_Pos (4U)
+#define FLASH_CR_OPTPG_Msk (0x1U << FLASH_CR_OPTPG_Pos) /*!< 0x00000010 */
+#define FLASH_CR_OPTPG FLASH_CR_OPTPG_Msk /*!< Option Byte Programming */
+#define FLASH_CR_OPTER_Pos (5U)
+#define FLASH_CR_OPTER_Msk (0x1U << FLASH_CR_OPTER_Pos) /*!< 0x00000020 */
+#define FLASH_CR_OPTER FLASH_CR_OPTER_Msk /*!< Option Byte Erase */
+#define FLASH_CR_STRT_Pos (6U)
+#define FLASH_CR_STRT_Msk (0x1U << FLASH_CR_STRT_Pos) /*!< 0x00000040 */
+#define FLASH_CR_STRT FLASH_CR_STRT_Msk /*!< Start */
+#define FLASH_CR_LOCK_Pos (7U)
+#define FLASH_CR_LOCK_Msk (0x1U << FLASH_CR_LOCK_Pos) /*!< 0x00000080 */
+#define FLASH_CR_LOCK FLASH_CR_LOCK_Msk /*!< Lock */
+#define FLASH_CR_OPTWRE_Pos (9U)
+#define FLASH_CR_OPTWRE_Msk (0x1U << FLASH_CR_OPTWRE_Pos) /*!< 0x00000200 */
+#define FLASH_CR_OPTWRE FLASH_CR_OPTWRE_Msk /*!< Option Bytes Write Enable */
+#define FLASH_CR_ERRIE_Pos (10U)
+#define FLASH_CR_ERRIE_Msk (0x1U << FLASH_CR_ERRIE_Pos) /*!< 0x00000400 */
+#define FLASH_CR_ERRIE FLASH_CR_ERRIE_Msk /*!< Error Interrupt Enable */
+#define FLASH_CR_EOPIE_Pos (12U)
+#define FLASH_CR_EOPIE_Msk (0x1U << FLASH_CR_EOPIE_Pos) /*!< 0x00001000 */
+#define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk /*!< End of operation interrupt enable */
+
+/******************* Bit definition for FLASH_AR register *******************/
+#define FLASH_AR_FAR_Pos (0U)
+#define FLASH_AR_FAR_Msk (0xFFFFFFFFU << FLASH_AR_FAR_Pos) /*!< 0xFFFFFFFF */
+#define FLASH_AR_FAR FLASH_AR_FAR_Msk /*!< Flash Address */
+
+/****************** Bit definition for FLASH_OBR register *******************/
+#define FLASH_OBR_OPTERR_Pos (0U)
+#define FLASH_OBR_OPTERR_Msk (0x1U << FLASH_OBR_OPTERR_Pos) /*!< 0x00000001 */
+#define FLASH_OBR_OPTERR FLASH_OBR_OPTERR_Msk /*!< Option Byte Error */
+#define FLASH_OBR_RDPRT_Pos (1U)
+#define FLASH_OBR_RDPRT_Msk (0x1U << FLASH_OBR_RDPRT_Pos) /*!< 0x00000002 */
+#define FLASH_OBR_RDPRT FLASH_OBR_RDPRT_Msk /*!< Read protection */
+
+#define FLASH_OBR_IWDG_SW_Pos (2U)
+#define FLASH_OBR_IWDG_SW_Msk (0x1U << FLASH_OBR_IWDG_SW_Pos) /*!< 0x00000004 */
+#define FLASH_OBR_IWDG_SW FLASH_OBR_IWDG_SW_Msk /*!< IWDG SW */
+#define FLASH_OBR_nRST_STOP_Pos (3U)
+#define FLASH_OBR_nRST_STOP_Msk (0x1U << FLASH_OBR_nRST_STOP_Pos) /*!< 0x00000008 */
+#define FLASH_OBR_nRST_STOP FLASH_OBR_nRST_STOP_Msk /*!< nRST_STOP */
+#define FLASH_OBR_nRST_STDBY_Pos (4U)
+#define FLASH_OBR_nRST_STDBY_Msk (0x1U << FLASH_OBR_nRST_STDBY_Pos) /*!< 0x00000010 */
+#define FLASH_OBR_nRST_STDBY FLASH_OBR_nRST_STDBY_Msk /*!< nRST_STDBY */
+#define FLASH_OBR_USER_Pos (2U)
+#define FLASH_OBR_USER_Msk (0x7U << FLASH_OBR_USER_Pos) /*!< 0x0000001C */
+#define FLASH_OBR_USER FLASH_OBR_USER_Msk /*!< User Option Bytes */
+#define FLASH_OBR_DATA0_Pos (10U)
+#define FLASH_OBR_DATA0_Msk (0xFFU << FLASH_OBR_DATA0_Pos) /*!< 0x0003FC00 */
+#define FLASH_OBR_DATA0 FLASH_OBR_DATA0_Msk /*!< Data0 */
+#define FLASH_OBR_DATA1_Pos (18U)
+#define FLASH_OBR_DATA1_Msk (0xFFU << FLASH_OBR_DATA1_Pos) /*!< 0x03FC0000 */
+#define FLASH_OBR_DATA1 FLASH_OBR_DATA1_Msk /*!< Data1 */
+
+/****************** Bit definition for FLASH_WRPR register ******************/
+#define FLASH_WRPR_WRP_Pos (0U)
+#define FLASH_WRPR_WRP_Msk (0xFFFFFFFFU << FLASH_WRPR_WRP_Pos) /*!< 0xFFFFFFFF */
+#define FLASH_WRPR_WRP FLASH_WRPR_WRP_Msk /*!< Write Protect */
+
+/*----------------------------------------------------------------------------*/
+
+/****************** Bit definition for FLASH_RDP register *******************/
+#define FLASH_RDP_RDP_Pos (0U)
+#define FLASH_RDP_RDP_Msk (0xFFU << FLASH_RDP_RDP_Pos) /*!< 0x000000FF */
+#define FLASH_RDP_RDP FLASH_RDP_RDP_Msk /*!< Read protection option byte */
+#define FLASH_RDP_nRDP_Pos (8U)
+#define FLASH_RDP_nRDP_Msk (0xFFU << FLASH_RDP_nRDP_Pos) /*!< 0x0000FF00 */
+#define FLASH_RDP_nRDP FLASH_RDP_nRDP_Msk /*!< Read protection complemented option byte */
+
+/****************** Bit definition for FLASH_USER register ******************/
+#define FLASH_USER_USER_Pos (16U)
+#define FLASH_USER_USER_Msk (0xFFU << FLASH_USER_USER_Pos) /*!< 0x00FF0000 */
+#define FLASH_USER_USER FLASH_USER_USER_Msk /*!< User option byte */
+#define FLASH_USER_nUSER_Pos (24U)
+#define FLASH_USER_nUSER_Msk (0xFFU << FLASH_USER_nUSER_Pos) /*!< 0xFF000000 */
+#define FLASH_USER_nUSER FLASH_USER_nUSER_Msk /*!< User complemented option byte */
+
+/****************** Bit definition for FLASH_Data0 register *****************/
+#define FLASH_DATA0_DATA0_Pos (0U)
+#define FLASH_DATA0_DATA0_Msk (0xFFU << FLASH_DATA0_DATA0_Pos) /*!< 0x000000FF */
+#define FLASH_DATA0_DATA0 FLASH_DATA0_DATA0_Msk /*!< User data storage option byte */
+#define FLASH_DATA0_nDATA0_Pos (8U)
+#define FLASH_DATA0_nDATA0_Msk (0xFFU << FLASH_DATA0_nDATA0_Pos) /*!< 0x0000FF00 */
+#define FLASH_DATA0_nDATA0 FLASH_DATA0_nDATA0_Msk /*!< User data storage complemented option byte */
+
+/****************** Bit definition for FLASH_Data1 register *****************/
+#define FLASH_DATA1_DATA1_Pos (16U)
+#define FLASH_DATA1_DATA1_Msk (0xFFU << FLASH_DATA1_DATA1_Pos) /*!< 0x00FF0000 */
+#define FLASH_DATA1_DATA1 FLASH_DATA1_DATA1_Msk /*!< User data storage option byte */
+#define FLASH_DATA1_nDATA1_Pos (24U)
+#define FLASH_DATA1_nDATA1_Msk (0xFFU << FLASH_DATA1_nDATA1_Pos) /*!< 0xFF000000 */
+#define FLASH_DATA1_nDATA1 FLASH_DATA1_nDATA1_Msk /*!< User data storage complemented option byte */
+
+/****************** Bit definition for FLASH_WRP0 register ******************/
+#define FLASH_WRP0_WRP0_Pos (0U)
+#define FLASH_WRP0_WRP0_Msk (0xFFU << FLASH_WRP0_WRP0_Pos) /*!< 0x000000FF */
+#define FLASH_WRP0_WRP0 FLASH_WRP0_WRP0_Msk /*!< Flash memory write protection option bytes */
+#define FLASH_WRP0_nWRP0_Pos (8U)
+#define FLASH_WRP0_nWRP0_Msk (0xFFU << FLASH_WRP0_nWRP0_Pos) /*!< 0x0000FF00 */
+#define FLASH_WRP0_nWRP0 FLASH_WRP0_nWRP0_Msk /*!< Flash memory write protection complemented option bytes */
+
+/****************** Bit definition for FLASH_WRP1 register ******************/
+#define FLASH_WRP1_WRP1_Pos (16U)
+#define FLASH_WRP1_WRP1_Msk (0xFFU << FLASH_WRP1_WRP1_Pos) /*!< 0x00FF0000 */
+#define FLASH_WRP1_WRP1 FLASH_WRP1_WRP1_Msk /*!< Flash memory write protection option bytes */
+#define FLASH_WRP1_nWRP1_Pos (24U)
+#define FLASH_WRP1_nWRP1_Msk (0xFFU << FLASH_WRP1_nWRP1_Pos) /*!< 0xFF000000 */
+#define FLASH_WRP1_nWRP1 FLASH_WRP1_nWRP1_Msk /*!< Flash memory write protection complemented option bytes */
+
+/****************** Bit definition for FLASH_WRP2 register ******************/
+#define FLASH_WRP2_WRP2_Pos (0U)
+#define FLASH_WRP2_WRP2_Msk (0xFFU << FLASH_WRP2_WRP2_Pos) /*!< 0x000000FF */
+#define FLASH_WRP2_WRP2 FLASH_WRP2_WRP2_Msk /*!< Flash memory write protection option bytes */
+#define FLASH_WRP2_nWRP2_Pos (8U)
+#define FLASH_WRP2_nWRP2_Msk (0xFFU << FLASH_WRP2_nWRP2_Pos) /*!< 0x0000FF00 */
+#define FLASH_WRP2_nWRP2 FLASH_WRP2_nWRP2_Msk /*!< Flash memory write protection complemented option bytes */
+
+/****************** Bit definition for FLASH_WRP3 register ******************/
+#define FLASH_WRP3_WRP3_Pos (16U)
+#define FLASH_WRP3_WRP3_Msk (0xFFU << FLASH_WRP3_WRP3_Pos) /*!< 0x00FF0000 */
+#define FLASH_WRP3_WRP3 FLASH_WRP3_WRP3_Msk /*!< Flash memory write protection option bytes */
+#define FLASH_WRP3_nWRP3_Pos (24U)
+#define FLASH_WRP3_nWRP3_Msk (0xFFU << FLASH_WRP3_nWRP3_Pos) /*!< 0xFF000000 */
+#define FLASH_WRP3_nWRP3 FLASH_WRP3_nWRP3_Msk /*!< Flash memory write protection complemented option bytes */
+
+
+
+/**
+ * @}
+*/
+
+/**
+ * @}
+*/
+
+/** @addtogroup Exported_macro
+ * @{
+ */
+
+/****************************** ADC Instances *********************************/
+#define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1))
+
+#define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC1_COMMON)
+
+#define IS_ADC_DMA_CAPABILITY_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
+
+/****************************** CRC Instances *********************************/
+#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
+
+/****************************** DAC Instances *********************************/
+#define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC)
+
+/****************************** DMA Instances *********************************/
+#define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \
+ ((INSTANCE) == DMA1_Channel2) || \
+ ((INSTANCE) == DMA1_Channel3) || \
+ ((INSTANCE) == DMA1_Channel4) || \
+ ((INSTANCE) == DMA1_Channel5) || \
+ ((INSTANCE) == DMA1_Channel6) || \
+ ((INSTANCE) == DMA1_Channel7) || \
+ ((INSTANCE) == DMA2_Channel1) || \
+ ((INSTANCE) == DMA2_Channel2) || \
+ ((INSTANCE) == DMA2_Channel3) || \
+ ((INSTANCE) == DMA2_Channel4) || \
+ ((INSTANCE) == DMA2_Channel5))
+
+/******************************* GPIO Instances *******************************/
+#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
+ ((INSTANCE) == GPIOB) || \
+ ((INSTANCE) == GPIOC) || \
+ ((INSTANCE) == GPIOD) || \
+ ((INSTANCE) == GPIOE) || \
+ ((INSTANCE) == GPIOF) || \
+ ((INSTANCE) == GPIOG))
+
+/**************************** GPIO Alternate Function Instances ***************/
+#define IS_GPIO_AF_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
+
+/**************************** GPIO Lock Instances *****************************/
+#define IS_GPIO_LOCK_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
+
+/******************************** I2C Instances *******************************/
+#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
+ ((INSTANCE) == I2C2))
+
+/****************************** IWDG Instances ********************************/
+#define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
+
+/******************************** SPI Instances *******************************/
+#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
+ ((INSTANCE) == SPI2) || \
+ ((INSTANCE) == SPI3))
+
+/****************************** START TIM Instances ***************************/
+/****************************** TIM Instances *********************************/
+#define IS_TIM_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM6) || \
+ ((INSTANCE) == TIM7))
+
+#define IS_TIM_CC1_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5))
+
+#define IS_TIM_CC2_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5))
+
+#define IS_TIM_CC3_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5))
+
+#define IS_TIM_CC4_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5))
+
+#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5))
+
+#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5))
+
+#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5))
+
+#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5))
+
+#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5))
+
+#define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5))
+
+#define IS_TIM_XOR_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5))
+
+#define IS_TIM_MASTER_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM6) || \
+ ((INSTANCE) == TIM7))
+
+#define IS_TIM_SLAVE_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5))
+
+#define IS_TIM_DMABURST_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5))
+
+#define IS_TIM_BREAK_INSTANCE(INSTANCE) (0)
+
+#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
+ ((((INSTANCE) == TIM2) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM3) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM4) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM5) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))))
+
+#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) (0)
+
+#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5))
+
+#define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE) (0)
+
+#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5))
+
+#define IS_TIM_DMA_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM6) || \
+ ((INSTANCE) == TIM7))
+
+#define IS_TIM_DMA_CC_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5))
+
+#define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) (0)
+
+/****************************** END TIM Instances *****************************/
+
+
+/******************** USART Instances : Synchronous mode **********************/
+#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3))
+
+/******************** UART Instances : Asynchronous mode **********************/
+#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3) || \
+ ((INSTANCE) == UART4) || \
+ ((INSTANCE) == UART5))
+
+/******************** UART Instances : Half-Duplex mode **********************/
+#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3) || \
+ ((INSTANCE) == UART4) || \
+ ((INSTANCE) == UART5))
+
+/******************** UART Instances : LIN mode **********************/
+#define IS_UART_LIN_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3) || \
+ ((INSTANCE) == UART4) || \
+ ((INSTANCE) == UART5))
+
+/****************** UART Instances : Hardware Flow control ********************/
+#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3))
+
+/********************* UART Instances : Smard card mode ***********************/
+#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3))
+
+/*********************** UART Instances : IRDA mode ***************************/
+#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3) || \
+ ((INSTANCE) == UART4) || \
+ ((INSTANCE) == UART5))
+
+/***************** UART Instances : Multi-Processor mode **********************/
+#define IS_UART_MULTIPROCESSOR_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3) || \
+ ((INSTANCE) == UART4) || \
+ ((INSTANCE) == UART5))
+
+/***************** UART Instances : DMA mode available **********************/
+#define IS_UART_DMA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3) || \
+ ((INSTANCE) == UART4))
+
+/****************************** RTC Instances *********************************/
+#define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
+
+/**************************** WWDG Instances *****************************/
+#define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
+
+
+
+
+
+/**
+ * @}
+*/
+/******************************************************************************/
+/* For a painless codes migration between the STM32F1xx device product */
+/* lines, the aliases defined below are put in place to overcome the */
+/* differences in the interrupt handlers and IRQn definitions. */
+/* No need to update developed interrupt code when moving across */
+/* product lines within the same STM32F1 Family */
+/******************************************************************************/
+
+/* Aliases for __IRQn */
+#define ADC1_2_IRQn ADC1_IRQn
+#define DMA2_Channel4_IRQn DMA2_Channel4_5_IRQn
+#define TIM6_DAC_IRQn TIM6_IRQn
+
+
+/* Aliases for __IRQHandler */
+#define ADC1_2_IRQHandler ADC1_IRQHandler
+#define DMA2_Channel4_IRQHandler DMA2_Channel4_5_IRQHandler
+#define TIM6_DAC_IRQHandler TIM6_IRQHandler
+
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+
+#ifdef __cplusplus
+ }
+#endif /* __cplusplus */
+
+#endif /* __STM32F101xE_H */
+
+
+
+ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Device/ST/STM32F1xx/Include/stm32f101xg.h b/Device/ST/STM32F1xx/Include/stm32f101xg.h
new file mode 100644
index 0000000..768a002
--- /dev/null
+++ b/Device/ST/STM32F1xx/Include/stm32f101xg.h
@@ -0,0 +1,7514 @@
+/**
+ ******************************************************************************
+ * @file stm32f101xg.h
+ * @author MCD Application Team
+ * @version V4.1.0
+ * @date 29-April-2016
+ * @brief CMSIS Cortex-M3 Device Peripheral Access Layer Header File.
+ * This file contains all the peripheral register's definitions, bits
+ * definitions and memory mapping for STM32F1xx devices.
+ *
+ * This file contains:
+ * - Data structures and the address mapping for all peripherals
+ * - Peripheral's registers declarations and bits definition
+ * - Macros to access peripheral’s registers hardware
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+
+/** @addtogroup CMSIS
+ * @{
+ */
+
+/** @addtogroup stm32f101xg
+ * @{
+ */
+
+#ifndef __STM32F101xG_H
+#define __STM32F101xG_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/** @addtogroup Configuration_section_for_CMSIS
+ * @{
+ */
+/**
+ * @brief Configuration of the Cortex-M3 Processor and Core Peripherals
+ */
+ #define __MPU_PRESENT 1 /*!< STM32 XL-density devices provide an MPU */
+#define __CM3_REV 0x0200 /*!< Core Revision r2p0 */
+#define __NVIC_PRIO_BITS 4 /*!< STM32 uses 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
+
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_interrupt_number_definition
+ * @{
+ */
+
+/**
+ * @brief STM32F10x Interrupt Number Definition, according to the selected device
+ * in @ref Library_configuration_section
+ */
+
+ /*!< Interrupt Number Definition */
+typedef enum
+{
+/****** Cortex-M3 Processor Exceptions Numbers ***************************************************/
+ NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
+ HardFault_IRQn = -13, /*!< 3 Cortex-M3 Hard Fault Interrupt */
+ MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */
+ BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */
+ UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */
+ SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */
+ DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */
+ PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */
+ SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */
+
+/****** STM32 specific Interrupt Numbers *********************************************************/
+ WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
+ PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */
+ TAMPER_IRQn = 2, /*!< Tamper Interrupt */
+ RTC_IRQn = 3, /*!< RTC global Interrupt */
+ FLASH_IRQn = 4, /*!< FLASH global Interrupt */
+ RCC_IRQn = 5, /*!< RCC global Interrupt */
+ EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */
+ EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */
+ EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */
+ EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */
+ EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */
+ DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 global Interrupt */
+ DMA1_Channel2_IRQn = 12, /*!< DMA1 Channel 2 global Interrupt */
+ DMA1_Channel3_IRQn = 13, /*!< DMA1 Channel 3 global Interrupt */
+ DMA1_Channel4_IRQn = 14, /*!< DMA1 Channel 4 global Interrupt */
+ DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 global Interrupt */
+ DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 global Interrupt */
+ DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 global Interrupt */
+ ADC1_2_IRQn = 18, /*!< ADC1 and ADC2 global Interrupt */
+ EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
+ TIM9_IRQn = 24, /*!< TIM9 global Interrupt */
+ TIM10_IRQn = 25, /*!< TIM10 global Interrupt */
+ TIM11_IRQn = 26, /*!< TIM11 global interrupt */
+ TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
+ TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
+ TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
+ I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
+ I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
+ I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
+ I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
+ SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
+ SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
+ USART1_IRQn = 37, /*!< USART1 global Interrupt */
+ USART2_IRQn = 38, /*!< USART2 global Interrupt */
+ USART3_IRQn = 39, /*!< USART3 global Interrupt */
+ EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
+ RTC_Alarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */
+ TIM12_IRQn = 43, /*!< TIM12 global Interrupt */
+ TIM13_IRQn = 44, /*!< TIM13 global Interrupt */
+ TIM14_IRQn = 45, /*!< TIM14 global Interrupt */
+ FSMC_IRQn = 48, /*!< FSMC global Interrupt */
+ TIM5_IRQn = 50, /*!< TIM5 global Interrupt */
+ SPI3_IRQn = 51, /*!< SPI3 global Interrupt */
+ UART4_IRQn = 52, /*!< UART4 global Interrupt */
+ UART5_IRQn = 53, /*!< UART5 global Interrupt */
+ TIM6_IRQn = 54, /*!< TIM6 global Interrupt */
+ TIM7_IRQn = 55, /*!< TIM7 global Interrupt */
+ DMA2_Channel1_IRQn = 56, /*!< DMA2 Channel 1 global Interrupt */
+ DMA2_Channel2_IRQn = 57, /*!< DMA2 Channel 2 global Interrupt */
+ DMA2_Channel3_IRQn = 58, /*!< DMA2 Channel 3 global Interrupt */
+ DMA2_Channel4_5_IRQn = 59, /*!< DMA2 Channel 4 and Channel 5 global Interrupt */
+} IRQn_Type;
+
+
+/**
+ * @}
+ */
+
+#include "core_cm3.h"
+#include "system_stm32f1xx.h"
+#include <stdint.h>
+
+/** @addtogroup Peripheral_registers_structures
+ * @{
+ */
+
+/**
+ * @brief Analog to Digital Converter
+ */
+
+typedef struct
+{
+ __IO uint32_t SR;
+ __IO uint32_t CR1;
+ __IO uint32_t CR2;
+ __IO uint32_t SMPR1;
+ __IO uint32_t SMPR2;
+ __IO uint32_t JOFR1;
+ __IO uint32_t JOFR2;
+ __IO uint32_t JOFR3;
+ __IO uint32_t JOFR4;
+ __IO uint32_t HTR;
+ __IO uint32_t LTR;
+ __IO uint32_t SQR1;
+ __IO uint32_t SQR2;
+ __IO uint32_t SQR3;
+ __IO uint32_t JSQR;
+ __IO uint32_t JDR1;
+ __IO uint32_t JDR2;
+ __IO uint32_t JDR3;
+ __IO uint32_t JDR4;
+ __IO uint32_t DR;
+} ADC_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t SR; /*!< ADC status register, used for ADC multimode (bits common to several ADC instances). Address offset: ADC1 base address */
+ __IO uint32_t CR1; /*!< ADC control register 1, used for ADC multimode (bits common to several ADC instances). Address offset: ADC1 base address + 0x04 */
+ __IO uint32_t CR2; /*!< ADC control register 2, used for ADC multimode (bits common to several ADC instances). Address offset: ADC1 base address + 0x08 */
+ uint32_t RESERVED[16];
+ __IO uint32_t DR; /*!< ADC data register, used for ADC multimode (bits common to several ADC instances). Address offset: ADC1 base address + 0x4C */
+} ADC_Common_TypeDef;
+
+/**
+ * @brief Backup Registers
+ */
+
+typedef struct
+{
+ uint32_t RESERVED0;
+ __IO uint32_t DR1;
+ __IO uint32_t DR2;
+ __IO uint32_t DR3;
+ __IO uint32_t DR4;
+ __IO uint32_t DR5;
+ __IO uint32_t DR6;
+ __IO uint32_t DR7;
+ __IO uint32_t DR8;
+ __IO uint32_t DR9;
+ __IO uint32_t DR10;
+ __IO uint32_t RTCCR;
+ __IO uint32_t CR;
+ __IO uint32_t CSR;
+ uint32_t RESERVED13[2];
+ __IO uint32_t DR11;
+ __IO uint32_t DR12;
+ __IO uint32_t DR13;
+ __IO uint32_t DR14;
+ __IO uint32_t DR15;
+ __IO uint32_t DR16;
+ __IO uint32_t DR17;
+ __IO uint32_t DR18;
+ __IO uint32_t DR19;
+ __IO uint32_t DR20;
+ __IO uint32_t DR21;
+ __IO uint32_t DR22;
+ __IO uint32_t DR23;
+ __IO uint32_t DR24;
+ __IO uint32_t DR25;
+ __IO uint32_t DR26;
+ __IO uint32_t DR27;
+ __IO uint32_t DR28;
+ __IO uint32_t DR29;
+ __IO uint32_t DR30;
+ __IO uint32_t DR31;
+ __IO uint32_t DR32;
+ __IO uint32_t DR33;
+ __IO uint32_t DR34;
+ __IO uint32_t DR35;
+ __IO uint32_t DR36;
+ __IO uint32_t DR37;
+ __IO uint32_t DR38;
+ __IO uint32_t DR39;
+ __IO uint32_t DR40;
+ __IO uint32_t DR41;
+ __IO uint32_t DR42;
+} BKP_TypeDef;
+
+
+/**
+ * @brief CRC calculation unit
+ */
+
+typedef struct
+{
+ __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
+ __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
+ uint8_t RESERVED0; /*!< Reserved, Address offset: 0x05 */
+ uint16_t RESERVED1; /*!< Reserved, Address offset: 0x06 */
+ __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
+} CRC_TypeDef;
+
+/**
+ * @brief Digital to Analog Converter
+ */
+
+typedef struct
+{
+ __IO uint32_t CR;
+ __IO uint32_t SWTRIGR;
+ __IO uint32_t DHR12R1;
+ __IO uint32_t DHR12L1;
+ __IO uint32_t DHR8R1;
+ __IO uint32_t DHR12R2;
+ __IO uint32_t DHR12L2;
+ __IO uint32_t DHR8R2;
+ __IO uint32_t DHR12RD;
+ __IO uint32_t DHR12LD;
+ __IO uint32_t DHR8RD;
+ __IO uint32_t DOR1;
+ __IO uint32_t DOR2;
+} DAC_TypeDef;
+
+/**
+ * @brief Debug MCU
+ */
+
+typedef struct
+{
+ __IO uint32_t IDCODE;
+ __IO uint32_t CR;
+}DBGMCU_TypeDef;
+
+/**
+ * @brief DMA Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t CCR;
+ __IO uint32_t CNDTR;
+ __IO uint32_t CPAR;
+ __IO uint32_t CMAR;
+} DMA_Channel_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t ISR;
+ __IO uint32_t IFCR;
+} DMA_TypeDef;
+
+
+
+/**
+ * @brief External Interrupt/Event Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t IMR;
+ __IO uint32_t EMR;
+ __IO uint32_t RTSR;
+ __IO uint32_t FTSR;
+ __IO uint32_t SWIER;
+ __IO uint32_t PR;
+} EXTI_TypeDef;
+
+/**
+ * @brief FLASH Registers
+ */
+
+typedef struct
+{
+ __IO uint32_t ACR;
+ __IO uint32_t KEYR;
+ __IO uint32_t OPTKEYR;
+ __IO uint32_t SR;
+ __IO uint32_t CR;
+ __IO uint32_t AR;
+ __IO uint32_t RESERVED;
+ __IO uint32_t OBR;
+ __IO uint32_t WRPR;
+ uint32_t RESERVED1[8];
+ __IO uint32_t KEYR2;
+ uint32_t RESERVED2;
+ __IO uint32_t SR2;
+ __IO uint32_t CR2;
+ __IO uint32_t AR2;
+} FLASH_TypeDef;
+
+/**
+ * @brief Option Bytes Registers
+ */
+
+typedef struct
+{
+ __IO uint16_t RDP;
+ __IO uint16_t USER;
+ __IO uint16_t Data0;
+ __IO uint16_t Data1;
+ __IO uint16_t WRP0;
+ __IO uint16_t WRP1;
+ __IO uint16_t WRP2;
+ __IO uint16_t WRP3;
+} OB_TypeDef;
+
+/**
+ * @brief Flexible Static Memory Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t BTCR[8];
+} FSMC_Bank1_TypeDef;
+
+/**
+ * @brief Flexible Static Memory Controller Bank1E
+ */
+
+typedef struct
+{
+ __IO uint32_t BWTR[7];
+} FSMC_Bank1E_TypeDef;
+
+/**
+ * @brief Flexible Static Memory Controller Bank2
+ */
+
+typedef struct
+{
+ __IO uint32_t PCR2; /*!< NAND Flash control register 2, Address offset: 0x60 */
+ __IO uint32_t SR2; /*!< NAND Flash FIFO status and interrupt register 2, Address offset: 0x64 */
+ __IO uint32_t PMEM2; /*!< NAND Flash Common memory space timing register 2, Address offset: 0x68 */
+ __IO uint32_t PATT2; /*!< NAND Flash Attribute memory space timing register 2, Address offset: 0x6C */
+ uint32_t RESERVED0; /*!< Reserved, 0x70 */
+ __IO uint32_t ECCR2; /*!< NAND Flash ECC result registers 2, Address offset: 0x74 */
+ uint32_t RESERVED1; /*!< Reserved, 0x78 */
+ uint32_t RESERVED2; /*!< Reserved, 0x7C */
+ __IO uint32_t PCR3; /*!< NAND Flash control register 3, Address offset: 0x80 */
+ __IO uint32_t SR3; /*!< NAND Flash FIFO status and interrupt register 3, Address offset: 0x84 */
+ __IO uint32_t PMEM3; /*!< NAND Flash Common memory space timing register 3, Address offset: 0x88 */
+ __IO uint32_t PATT3; /*!< NAND Flash Attribute memory space timing register 3, Address offset: 0x8C */
+ uint32_t RESERVED3; /*!< Reserved, 0x90 */
+ __IO uint32_t ECCR3; /*!< NAND Flash ECC result registers 3, Address offset: 0x94 */
+} FSMC_Bank2_3_TypeDef;
+
+/**
+ * @brief Flexible Static Memory Controller Bank4
+ */
+
+typedef struct
+{
+ __IO uint32_t PCR4;
+ __IO uint32_t SR4;
+ __IO uint32_t PMEM4;
+ __IO uint32_t PATT4;
+ __IO uint32_t PIO4;
+} FSMC_Bank4_TypeDef;
+
+/**
+ * @brief General Purpose I/O
+ */
+
+typedef struct
+{
+ __IO uint32_t CRL;
+ __IO uint32_t CRH;
+ __IO uint32_t IDR;
+ __IO uint32_t ODR;
+ __IO uint32_t BSRR;
+ __IO uint32_t BRR;
+ __IO uint32_t LCKR;
+} GPIO_TypeDef;
+
+/**
+ * @brief Alternate Function I/O
+ */
+
+typedef struct
+{
+ __IO uint32_t EVCR;
+ __IO uint32_t MAPR;
+ __IO uint32_t EXTICR[4];
+ uint32_t RESERVED0;
+ __IO uint32_t MAPR2;
+} AFIO_TypeDef;
+/**
+ * @brief Inter Integrated Circuit Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t CR1;
+ __IO uint32_t CR2;
+ __IO uint32_t OAR1;
+ __IO uint32_t OAR2;
+ __IO uint32_t DR;
+ __IO uint32_t SR1;
+ __IO uint32_t SR2;
+ __IO uint32_t CCR;
+ __IO uint32_t TRISE;
+} I2C_TypeDef;
+
+/**
+ * @brief Independent WATCHDOG
+ */
+
+typedef struct
+{
+ __IO uint32_t KR; /*!< Key register, Address offset: 0x00 */
+ __IO uint32_t PR; /*!< Prescaler register, Address offset: 0x04 */
+ __IO uint32_t RLR; /*!< Reload register, Address offset: 0x08 */
+ __IO uint32_t SR; /*!< Status register, Address offset: 0x0C */
+} IWDG_TypeDef;
+
+/**
+ * @brief Power Control
+ */
+
+typedef struct
+{
+ __IO uint32_t CR;
+ __IO uint32_t CSR;
+} PWR_TypeDef;
+
+/**
+ * @brief Reset and Clock Control
+ */
+
+typedef struct
+{
+ __IO uint32_t CR;
+ __IO uint32_t CFGR;
+ __IO uint32_t CIR;
+ __IO uint32_t APB2RSTR;
+ __IO uint32_t APB1RSTR;
+ __IO uint32_t AHBENR;
+ __IO uint32_t APB2ENR;
+ __IO uint32_t APB1ENR;
+ __IO uint32_t BDCR;
+ __IO uint32_t CSR;
+
+
+} RCC_TypeDef;
+
+/**
+ * @brief Real-Time Clock
+ */
+
+typedef struct
+{
+ __IO uint32_t CRH;
+ __IO uint32_t CRL;
+ __IO uint32_t PRLH;
+ __IO uint32_t PRLL;
+ __IO uint32_t DIVH;
+ __IO uint32_t DIVL;
+ __IO uint32_t CNTH;
+ __IO uint32_t CNTL;
+ __IO uint32_t ALRH;
+ __IO uint32_t ALRL;
+} RTC_TypeDef;
+
+/**
+ * @brief SD host Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t POWER;
+ __IO uint32_t CLKCR;
+ __IO uint32_t ARG;
+ __IO uint32_t CMD;
+ __I uint32_t RESPCMD;
+ __I uint32_t RESP1;
+ __I uint32_t RESP2;
+ __I uint32_t RESP3;
+ __I uint32_t RESP4;
+ __IO uint32_t DTIMER;
+ __IO uint32_t DLEN;
+ __IO uint32_t DCTRL;
+ __I uint32_t DCOUNT;
+ __I uint32_t STA;
+ __IO uint32_t ICR;
+ __IO uint32_t MASK;
+ uint32_t RESERVED0[2];
+ __I uint32_t FIFOCNT;
+ uint32_t RESERVED1[13];
+ __IO uint32_t FIFO;
+} SDIO_TypeDef;
+
+/**
+ * @brief Serial Peripheral Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t CR1;
+ __IO uint32_t CR2;
+ __IO uint32_t SR;
+ __IO uint32_t DR;
+ __IO uint32_t CRCPR;
+ __IO uint32_t RXCRCR;
+ __IO uint32_t TXCRCR;
+ __IO uint32_t I2SCFGR;
+} SPI_TypeDef;
+
+/**
+ * @brief TIM Timers
+ */
+typedef struct
+{
+ __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
+ __IO uint32_t SMCR; /*!< TIM slave Mode Control register, Address offset: 0x08 */
+ __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
+ __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
+ __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
+ __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
+ __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
+ __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
+ __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
+ __IO uint32_t PSC; /*!< TIM prescaler register, Address offset: 0x28 */
+ __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
+ __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */
+ __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
+ __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
+ __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
+ __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
+ __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
+ __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
+ __IO uint32_t DMAR; /*!< TIM DMA address for full transfer register, Address offset: 0x4C */
+ __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */
+}TIM_TypeDef;
+
+
+/**
+ * @brief Universal Synchronous Asynchronous Receiver Transmitter
+ */
+
+typedef struct
+{
+ __IO uint32_t SR; /*!< USART Status register, Address offset: 0x00 */
+ __IO uint32_t DR; /*!< USART Data register, Address offset: 0x04 */
+ __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x08 */
+ __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x0C */
+ __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x10 */
+ __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x14 */
+ __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x18 */
+} USART_TypeDef;
+
+
+
+/**
+ * @brief Window WATCHDOG
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
+ __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
+ __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
+} WWDG_TypeDef;
+
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_memory_map
+ * @{
+ */
+
+
+#define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH base address in the alias region */
+#define FLASH_BANK1_END ((uint32_t)0x0807FFFF) /*!< FLASH END address of bank1 */
+#define FLASH_BANK2_END ((uint32_t)0x080FFFFF) /*!< FLASH END address of bank2 */
+#define SRAM_BASE ((uint32_t)0x20000000) /*!< SRAM base address in the alias region */
+#define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */
+
+#define SRAM_BB_BASE ((uint32_t)0x22000000) /*!< SRAM base address in the bit-band region */
+#define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */
+
+#define FSMC_BASE ((uint32_t)0x60000000) /*!< FSMC base address */
+#define FSMC_R_BASE ((uint32_t)0xA0000000) /*!< FSMC registers base address */
+
+/*!< Peripheral memory map */
+#define APB1PERIPH_BASE PERIPH_BASE
+#define APB2PERIPH_BASE (PERIPH_BASE + 0x10000)
+#define AHBPERIPH_BASE (PERIPH_BASE + 0x20000)
+
+#define TIM2_BASE (APB1PERIPH_BASE + 0x0000)
+#define TIM3_BASE (APB1PERIPH_BASE + 0x0400)
+#define TIM4_BASE (APB1PERIPH_BASE + 0x0800)
+#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00)
+#define TIM6_BASE (APB1PERIPH_BASE + 0x1000)
+#define TIM7_BASE (APB1PERIPH_BASE + 0x1400)
+#define TIM12_BASE (APB1PERIPH_BASE + 0x1800)
+#define TIM13_BASE (APB1PERIPH_BASE + 0x1C00)
+#define TIM14_BASE (APB1PERIPH_BASE + 0x2000)
+#define RTC_BASE (APB1PERIPH_BASE + 0x2800)
+#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00)
+#define IWDG_BASE (APB1PERIPH_BASE + 0x3000)
+#define SPI2_BASE (APB1PERIPH_BASE + 0x3800)
+#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00)
+#define USART2_BASE (APB1PERIPH_BASE + 0x4400)
+#define USART3_BASE (APB1PERIPH_BASE + 0x4800)
+#define UART4_BASE (APB1PERIPH_BASE + 0x4C00)
+#define UART5_BASE (APB1PERIPH_BASE + 0x5000)
+#define I2C1_BASE (APB1PERIPH_BASE + 0x5400)
+#define I2C2_BASE (APB1PERIPH_BASE + 0x5800)
+#define BKP_BASE (APB1PERIPH_BASE + 0x6C00)
+#define PWR_BASE (APB1PERIPH_BASE + 0x7000)
+#define DAC_BASE (APB1PERIPH_BASE + 0x7400)
+#define AFIO_BASE (APB2PERIPH_BASE + 0x0000)
+#define EXTI_BASE (APB2PERIPH_BASE + 0x0400)
+#define GPIOA_BASE (APB2PERIPH_BASE + 0x0800)
+#define GPIOB_BASE (APB2PERIPH_BASE + 0x0C00)
+#define GPIOC_BASE (APB2PERIPH_BASE + 0x1000)
+#define GPIOD_BASE (APB2PERIPH_BASE + 0x1400)
+#define GPIOE_BASE (APB2PERIPH_BASE + 0x1800)
+#define GPIOF_BASE (APB2PERIPH_BASE + 0x1C00)
+#define GPIOG_BASE (APB2PERIPH_BASE + 0x2000)
+#define ADC1_BASE (APB2PERIPH_BASE + 0x2400)
+#define ADC2_BASE (APB2PERIPH_BASE + 0x2800)
+#define SPI1_BASE (APB2PERIPH_BASE + 0x3000)
+#define USART1_BASE (APB2PERIPH_BASE + 0x3800)
+#define TIM9_BASE (APB2PERIPH_BASE + 0x4C00)
+#define TIM10_BASE (APB2PERIPH_BASE + 0x5000)
+#define TIM11_BASE (APB2PERIPH_BASE + 0x5400)
+
+#define SDIO_BASE (PERIPH_BASE + 0x18000)
+
+#define DMA1_BASE (AHBPERIPH_BASE + 0x0000)
+#define DMA1_Channel1_BASE (AHBPERIPH_BASE + 0x0008)
+#define DMA1_Channel2_BASE (AHBPERIPH_BASE + 0x001C)
+#define DMA1_Channel3_BASE (AHBPERIPH_BASE + 0x0030)
+#define DMA1_Channel4_BASE (AHBPERIPH_BASE + 0x0044)
+#define DMA1_Channel5_BASE (AHBPERIPH_BASE + 0x0058)
+#define DMA1_Channel6_BASE (AHBPERIPH_BASE + 0x006C)
+#define DMA1_Channel7_BASE (AHBPERIPH_BASE + 0x0080)
+#define DMA2_BASE (AHBPERIPH_BASE + 0x0400)
+#define DMA2_Channel1_BASE (AHBPERIPH_BASE + 0x0408)
+#define DMA2_Channel2_BASE (AHBPERIPH_BASE + 0x041C)
+#define DMA2_Channel3_BASE (AHBPERIPH_BASE + 0x0430)
+#define DMA2_Channel4_BASE (AHBPERIPH_BASE + 0x0444)
+#define DMA2_Channel5_BASE (AHBPERIPH_BASE + 0x0458)
+#define RCC_BASE (AHBPERIPH_BASE + 0x1000)
+#define CRC_BASE (AHBPERIPH_BASE + 0x3000)
+
+#define FLASH_R_BASE (AHBPERIPH_BASE + 0x2000) /*!< Flash registers base address */
+#define FLASHSIZE_BASE ((uint32_t)0x1FFFF7E0) /*!< FLASH Size register base address */
+#define UID_BASE ((uint32_t)0x1FFFF7E8) /*!< Unique device ID register base address */
+#define OB_BASE ((uint32_t)0x1FFFF800) /*!< Flash Option Bytes base address */
+
+
+#define FSMC_BANK1 (FSMC_BASE) /*!< FSMC Bank1 base address */
+#define FSMC_BANK1_1 (FSMC_BANK1) /*!< FSMC Bank1_1 base address */
+#define FSMC_BANK1_2 (FSMC_BANK1 + 0x04000000) /*!< FSMC Bank1_2 base address */
+#define FSMC_BANK1_3 (FSMC_BANK1 + 0x08000000) /*!< FSMC Bank1_3 base address */
+#define FSMC_BANK1_4 (FSMC_BANK1 + 0x0C000000) /*!< FSMC Bank1_4 base address */
+
+#define FSMC_BANK2 (FSMC_BASE + 0x10000000) /*!< FSMC Bank2 base address */
+#define FSMC_BANK3 (FSMC_BASE + 0x20000000) /*!< FSMC Bank3 base address */
+#define FSMC_BANK4 (FSMC_BASE + 0x30000000) /*!< FSMC Bank4 base address */
+
+#define FSMC_BANK1_R_BASE (FSMC_R_BASE + 0x0000) /*!< FSMC Bank1 registers base address */
+#define FSMC_BANK1E_R_BASE (FSMC_R_BASE + 0x0104) /*!< FSMC Bank1E registers base address */
+#define FSMC_BANK2_3_R_BASE (FSMC_R_BASE + 0x0060) /*!< FSMC Bank2/Bank3 registers base address */
+#define FSMC_BANK4_R_BASE (FSMC_R_BASE + 0x00A0) /*!< FSMC Bank4 registers base address */
+
+#define DBGMCU_BASE ((uint32_t)0xE0042000) /*!< Debug MCU registers base address */
+
+
+
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_declaration
+ * @{
+ */
+
+#define TIM2 ((TIM_TypeDef *) TIM2_BASE)
+#define TIM3 ((TIM_TypeDef *) TIM3_BASE)
+#define TIM4 ((TIM_TypeDef *) TIM4_BASE)
+#define TIM5 ((TIM_TypeDef *) TIM5_BASE)
+#define TIM6 ((TIM_TypeDef *) TIM6_BASE)
+#define TIM7 ((TIM_TypeDef *) TIM7_BASE)
+#define TIM12 ((TIM_TypeDef *) TIM12_BASE)
+#define TIM13 ((TIM_TypeDef *) TIM13_BASE)
+#define TIM14 ((TIM_TypeDef *) TIM14_BASE)
+#define RTC ((RTC_TypeDef *) RTC_BASE)
+#define WWDG ((WWDG_TypeDef *) WWDG_BASE)
+#define IWDG ((IWDG_TypeDef *) IWDG_BASE)
+#define SPI2 ((SPI_TypeDef *) SPI2_BASE)
+#define SPI3 ((SPI_TypeDef *) SPI3_BASE)
+#define USART2 ((USART_TypeDef *) USART2_BASE)
+#define USART3 ((USART_TypeDef *) USART3_BASE)
+#define UART4 ((USART_TypeDef *) UART4_BASE)
+#define UART5 ((USART_TypeDef *) UART5_BASE)
+#define I2C1 ((I2C_TypeDef *) I2C1_BASE)
+#define I2C2 ((I2C_TypeDef *) I2C2_BASE)
+#define BKP ((BKP_TypeDef *) BKP_BASE)
+#define PWR ((PWR_TypeDef *) PWR_BASE)
+#define DAC ((DAC_TypeDef *) DAC_BASE)
+#define AFIO ((AFIO_TypeDef *) AFIO_BASE)
+#define EXTI ((EXTI_TypeDef *) EXTI_BASE)
+#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
+#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
+#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
+#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
+#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
+#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
+#define GPIOG ((GPIO_TypeDef *) GPIOG_BASE)
+#define ADC1 ((ADC_TypeDef *) ADC1_BASE)
+#define ADC2 ((ADC_TypeDef *) ADC2_BASE)
+#define ADC12_COMMON ((ADC_Common_TypeDef *) ADC1_BASE)
+#define SPI1 ((SPI_TypeDef *) SPI1_BASE)
+#define USART1 ((USART_TypeDef *) USART1_BASE)
+#define TIM9 ((TIM_TypeDef *) TIM9_BASE)
+#define TIM10 ((TIM_TypeDef *) TIM10_BASE)
+#define TIM11 ((TIM_TypeDef *) TIM11_BASE)
+#define SDIO ((SDIO_TypeDef *) SDIO_BASE)
+#define DMA1 ((DMA_TypeDef *) DMA1_BASE)
+#define DMA2 ((DMA_TypeDef *) DMA2_BASE)
+#define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
+#define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
+#define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
+#define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
+#define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
+#define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
+#define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
+#define DMA2_Channel1 ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE)
+#define DMA2_Channel2 ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE)
+#define DMA2_Channel3 ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE)
+#define DMA2_Channel4 ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE)
+#define DMA2_Channel5 ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE)
+#define RCC ((RCC_TypeDef *) RCC_BASE)
+#define CRC ((CRC_TypeDef *) CRC_BASE)
+#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
+#define OB ((OB_TypeDef *) OB_BASE)
+#define FSMC_Bank1 ((FSMC_Bank1_TypeDef *) FSMC_BANK1_R_BASE)
+#define FSMC_Bank1E ((FSMC_Bank1E_TypeDef *) FSMC_BANK1E_R_BASE)
+#define FSMC_Bank2_3 ((FSMC_Bank2_3_TypeDef *) FSMC_BANK2_3_R_BASE)
+#define FSMC_Bank4 ((FSMC_Bank4_TypeDef *) FSMC_BANK4_R_BASE)
+#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
+
+
+/**
+ * @}
+ */
+
+/** @addtogroup Exported_constants
+ * @{
+ */
+
+ /** @addtogroup Peripheral_Registers_Bits_Definition
+ * @{
+ */
+
+/******************************************************************************/
+/* Peripheral Registers_Bits_Definition */
+/******************************************************************************/
+
+/******************************************************************************/
+/* */
+/* CRC calculation unit (CRC) */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for CRC_DR register *********************/
+#define CRC_DR_DR_Pos (0U)
+#define CRC_DR_DR_Msk (0xFFFFFFFFU << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */
+#define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */
+
+/******************* Bit definition for CRC_IDR register ********************/
+#define CRC_IDR_IDR_Pos (0U)
+#define CRC_IDR_IDR_Msk (0xFFU << CRC_IDR_IDR_Pos) /*!< 0x000000FF */
+#define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 8-bit data register bits */
+
+/******************** Bit definition for CRC_CR register ********************/
+#define CRC_CR_RESET_Pos (0U)
+#define CRC_CR_RESET_Msk (0x1U << CRC_CR_RESET_Pos) /*!< 0x00000001 */
+#define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET bit */
+
+/******************************************************************************/
+/* */
+/* Power Control */
+/* */
+/******************************************************************************/
+
+/******************** Bit definition for PWR_CR register ********************/
+#define PWR_CR_LPDS_Pos (0U)
+#define PWR_CR_LPDS_Msk (0x1U << PWR_CR_LPDS_Pos) /*!< 0x00000001 */
+#define PWR_CR_LPDS PWR_CR_LPDS_Msk /*!< Low-Power Deepsleep */
+#define PWR_CR_PDDS_Pos (1U)
+#define PWR_CR_PDDS_Msk (0x1U << PWR_CR_PDDS_Pos) /*!< 0x00000002 */
+#define PWR_CR_PDDS PWR_CR_PDDS_Msk /*!< Power Down Deepsleep */
+#define PWR_CR_CWUF_Pos (2U)
+#define PWR_CR_CWUF_Msk (0x1U << PWR_CR_CWUF_Pos) /*!< 0x00000004 */
+#define PWR_CR_CWUF PWR_CR_CWUF_Msk /*!< Clear Wakeup Flag */
+#define PWR_CR_CSBF_Pos (3U)
+#define PWR_CR_CSBF_Msk (0x1U << PWR_CR_CSBF_Pos) /*!< 0x00000008 */
+#define PWR_CR_CSBF PWR_CR_CSBF_Msk /*!< Clear Standby Flag */
+#define PWR_CR_PVDE_Pos (4U)
+#define PWR_CR_PVDE_Msk (0x1U << PWR_CR_PVDE_Pos) /*!< 0x00000010 */
+#define PWR_CR_PVDE PWR_CR_PVDE_Msk /*!< Power Voltage Detector Enable */
+
+#define PWR_CR_PLS_Pos (5U)
+#define PWR_CR_PLS_Msk (0x7U << PWR_CR_PLS_Pos) /*!< 0x000000E0 */
+#define PWR_CR_PLS PWR_CR_PLS_Msk /*!< PLS[2:0] bits (PVD Level Selection) */
+#define PWR_CR_PLS_0 (0x1U << PWR_CR_PLS_Pos) /*!< 0x00000020 */
+#define PWR_CR_PLS_1 (0x2U << PWR_CR_PLS_Pos) /*!< 0x00000040 */
+#define PWR_CR_PLS_2 (0x4U << PWR_CR_PLS_Pos) /*!< 0x00000080 */
+
+/*!< PVD level configuration */
+#define PWR_CR_PLS_2V2 ((uint32_t)0x00000000) /*!< PVD level 2.2V */
+#define PWR_CR_PLS_2V3 ((uint32_t)0x00000020) /*!< PVD level 2.3V */
+#define PWR_CR_PLS_2V4 ((uint32_t)0x00000040) /*!< PVD level 2.4V */
+#define PWR_CR_PLS_2V5 ((uint32_t)0x00000060) /*!< PVD level 2.5V */
+#define PWR_CR_PLS_2V6 ((uint32_t)0x00000080) /*!< PVD level 2.6V */
+#define PWR_CR_PLS_2V7 ((uint32_t)0x000000A0) /*!< PVD level 2.7V */
+#define PWR_CR_PLS_2V8 ((uint32_t)0x000000C0) /*!< PVD level 2.8V */
+#define PWR_CR_PLS_2V9 ((uint32_t)0x000000E0) /*!< PVD level 2.9V */
+
+#define PWR_CR_DBP_Pos (8U)
+#define PWR_CR_DBP_Msk (0x1U << PWR_CR_DBP_Pos) /*!< 0x00000100 */
+#define PWR_CR_DBP PWR_CR_DBP_Msk /*!< Disable Backup Domain write protection */
+
+
+/******************* Bit definition for PWR_CSR register ********************/
+#define PWR_CSR_WUF_Pos (0U)
+#define PWR_CSR_WUF_Msk (0x1U << PWR_CSR_WUF_Pos) /*!< 0x00000001 */
+#define PWR_CSR_WUF PWR_CSR_WUF_Msk /*!< Wakeup Flag */
+#define PWR_CSR_SBF_Pos (1U)
+#define PWR_CSR_SBF_Msk (0x1U << PWR_CSR_SBF_Pos) /*!< 0x00000002 */
+#define PWR_CSR_SBF PWR_CSR_SBF_Msk /*!< Standby Flag */
+#define PWR_CSR_PVDO_Pos (2U)
+#define PWR_CSR_PVDO_Msk (0x1U << PWR_CSR_PVDO_Pos) /*!< 0x00000004 */
+#define PWR_CSR_PVDO PWR_CSR_PVDO_Msk /*!< PVD Output */
+#define PWR_CSR_EWUP_Pos (8U)
+#define PWR_CSR_EWUP_Msk (0x1U << PWR_CSR_EWUP_Pos) /*!< 0x00000100 */
+#define PWR_CSR_EWUP PWR_CSR_EWUP_Msk /*!< Enable WKUP pin */
+
+/******************************************************************************/
+/* */
+/* Backup registers */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for BKP_DR1 register ********************/
+#define BKP_DR1_D_Pos (0U)
+#define BKP_DR1_D_Msk (0xFFFFU << BKP_DR1_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR1_D BKP_DR1_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR2 register ********************/
+#define BKP_DR2_D_Pos (0U)
+#define BKP_DR2_D_Msk (0xFFFFU << BKP_DR2_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR2_D BKP_DR2_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR3 register ********************/
+#define BKP_DR3_D_Pos (0U)
+#define BKP_DR3_D_Msk (0xFFFFU << BKP_DR3_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR3_D BKP_DR3_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR4 register ********************/
+#define BKP_DR4_D_Pos (0U)
+#define BKP_DR4_D_Msk (0xFFFFU << BKP_DR4_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR4_D BKP_DR4_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR5 register ********************/
+#define BKP_DR5_D_Pos (0U)
+#define BKP_DR5_D_Msk (0xFFFFU << BKP_DR5_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR5_D BKP_DR5_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR6 register ********************/
+#define BKP_DR6_D_Pos (0U)
+#define BKP_DR6_D_Msk (0xFFFFU << BKP_DR6_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR6_D BKP_DR6_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR7 register ********************/
+#define BKP_DR7_D_Pos (0U)
+#define BKP_DR7_D_Msk (0xFFFFU << BKP_DR7_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR7_D BKP_DR7_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR8 register ********************/
+#define BKP_DR8_D_Pos (0U)
+#define BKP_DR8_D_Msk (0xFFFFU << BKP_DR8_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR8_D BKP_DR8_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR9 register ********************/
+#define BKP_DR9_D_Pos (0U)
+#define BKP_DR9_D_Msk (0xFFFFU << BKP_DR9_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR9_D BKP_DR9_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR10 register *******************/
+#define BKP_DR10_D_Pos (0U)
+#define BKP_DR10_D_Msk (0xFFFFU << BKP_DR10_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR10_D BKP_DR10_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR11 register *******************/
+#define BKP_DR11_D_Pos (0U)
+#define BKP_DR11_D_Msk (0xFFFFU << BKP_DR11_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR11_D BKP_DR11_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR12 register *******************/
+#define BKP_DR12_D_Pos (0U)
+#define BKP_DR12_D_Msk (0xFFFFU << BKP_DR12_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR12_D BKP_DR12_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR13 register *******************/
+#define BKP_DR13_D_Pos (0U)
+#define BKP_DR13_D_Msk (0xFFFFU << BKP_DR13_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR13_D BKP_DR13_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR14 register *******************/
+#define BKP_DR14_D_Pos (0U)
+#define BKP_DR14_D_Msk (0xFFFFU << BKP_DR14_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR14_D BKP_DR14_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR15 register *******************/
+#define BKP_DR15_D_Pos (0U)
+#define BKP_DR15_D_Msk (0xFFFFU << BKP_DR15_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR15_D BKP_DR15_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR16 register *******************/
+#define BKP_DR16_D_Pos (0U)
+#define BKP_DR16_D_Msk (0xFFFFU << BKP_DR16_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR16_D BKP_DR16_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR17 register *******************/
+#define BKP_DR17_D_Pos (0U)
+#define BKP_DR17_D_Msk (0xFFFFU << BKP_DR17_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR17_D BKP_DR17_D_Msk /*!< Backup data */
+
+/****************** Bit definition for BKP_DR18 register ********************/
+#define BKP_DR18_D_Pos (0U)
+#define BKP_DR18_D_Msk (0xFFFFU << BKP_DR18_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR18_D BKP_DR18_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR19 register *******************/
+#define BKP_DR19_D_Pos (0U)
+#define BKP_DR19_D_Msk (0xFFFFU << BKP_DR19_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR19_D BKP_DR19_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR20 register *******************/
+#define BKP_DR20_D_Pos (0U)
+#define BKP_DR20_D_Msk (0xFFFFU << BKP_DR20_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR20_D BKP_DR20_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR21 register *******************/
+#define BKP_DR21_D_Pos (0U)
+#define BKP_DR21_D_Msk (0xFFFFU << BKP_DR21_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR21_D BKP_DR21_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR22 register *******************/
+#define BKP_DR22_D_Pos (0U)
+#define BKP_DR22_D_Msk (0xFFFFU << BKP_DR22_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR22_D BKP_DR22_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR23 register *******************/
+#define BKP_DR23_D_Pos (0U)
+#define BKP_DR23_D_Msk (0xFFFFU << BKP_DR23_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR23_D BKP_DR23_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR24 register *******************/
+#define BKP_DR24_D_Pos (0U)
+#define BKP_DR24_D_Msk (0xFFFFU << BKP_DR24_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR24_D BKP_DR24_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR25 register *******************/
+#define BKP_DR25_D_Pos (0U)
+#define BKP_DR25_D_Msk (0xFFFFU << BKP_DR25_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR25_D BKP_DR25_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR26 register *******************/
+#define BKP_DR26_D_Pos (0U)
+#define BKP_DR26_D_Msk (0xFFFFU << BKP_DR26_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR26_D BKP_DR26_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR27 register *******************/
+#define BKP_DR27_D_Pos (0U)
+#define BKP_DR27_D_Msk (0xFFFFU << BKP_DR27_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR27_D BKP_DR27_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR28 register *******************/
+#define BKP_DR28_D_Pos (0U)
+#define BKP_DR28_D_Msk (0xFFFFU << BKP_DR28_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR28_D BKP_DR28_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR29 register *******************/
+#define BKP_DR29_D_Pos (0U)
+#define BKP_DR29_D_Msk (0xFFFFU << BKP_DR29_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR29_D BKP_DR29_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR30 register *******************/
+#define BKP_DR30_D_Pos (0U)
+#define BKP_DR30_D_Msk (0xFFFFU << BKP_DR30_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR30_D BKP_DR30_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR31 register *******************/
+#define BKP_DR31_D_Pos (0U)
+#define BKP_DR31_D_Msk (0xFFFFU << BKP_DR31_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR31_D BKP_DR31_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR32 register *******************/
+#define BKP_DR32_D_Pos (0U)
+#define BKP_DR32_D_Msk (0xFFFFU << BKP_DR32_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR32_D BKP_DR32_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR33 register *******************/
+#define BKP_DR33_D_Pos (0U)
+#define BKP_DR33_D_Msk (0xFFFFU << BKP_DR33_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR33_D BKP_DR33_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR34 register *******************/
+#define BKP_DR34_D_Pos (0U)
+#define BKP_DR34_D_Msk (0xFFFFU << BKP_DR34_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR34_D BKP_DR34_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR35 register *******************/
+#define BKP_DR35_D_Pos (0U)
+#define BKP_DR35_D_Msk (0xFFFFU << BKP_DR35_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR35_D BKP_DR35_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR36 register *******************/
+#define BKP_DR36_D_Pos (0U)
+#define BKP_DR36_D_Msk (0xFFFFU << BKP_DR36_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR36_D BKP_DR36_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR37 register *******************/
+#define BKP_DR37_D_Pos (0U)
+#define BKP_DR37_D_Msk (0xFFFFU << BKP_DR37_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR37_D BKP_DR37_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR38 register *******************/
+#define BKP_DR38_D_Pos (0U)
+#define BKP_DR38_D_Msk (0xFFFFU << BKP_DR38_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR38_D BKP_DR38_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR39 register *******************/
+#define BKP_DR39_D_Pos (0U)
+#define BKP_DR39_D_Msk (0xFFFFU << BKP_DR39_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR39_D BKP_DR39_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR40 register *******************/
+#define BKP_DR40_D_Pos (0U)
+#define BKP_DR40_D_Msk (0xFFFFU << BKP_DR40_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR40_D BKP_DR40_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR41 register *******************/
+#define BKP_DR41_D_Pos (0U)
+#define BKP_DR41_D_Msk (0xFFFFU << BKP_DR41_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR41_D BKP_DR41_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR42 register *******************/
+#define BKP_DR42_D_Pos (0U)
+#define BKP_DR42_D_Msk (0xFFFFU << BKP_DR42_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR42_D BKP_DR42_D_Msk /*!< Backup data */
+
+#define RTC_BKP_NUMBER 42
+
+/****************** Bit definition for BKP_RTCCR register *******************/
+#define BKP_RTCCR_CAL_Pos (0U)
+#define BKP_RTCCR_CAL_Msk (0x7FU << BKP_RTCCR_CAL_Pos) /*!< 0x0000007F */
+#define BKP_RTCCR_CAL BKP_RTCCR_CAL_Msk /*!< Calibration value */
+#define BKP_RTCCR_CCO_Pos (7U)
+#define BKP_RTCCR_CCO_Msk (0x1U << BKP_RTCCR_CCO_Pos) /*!< 0x00000080 */
+#define BKP_RTCCR_CCO BKP_RTCCR_CCO_Msk /*!< Calibration Clock Output */
+#define BKP_RTCCR_ASOE_Pos (8U)
+#define BKP_RTCCR_ASOE_Msk (0x1U << BKP_RTCCR_ASOE_Pos) /*!< 0x00000100 */
+#define BKP_RTCCR_ASOE BKP_RTCCR_ASOE_Msk /*!< Alarm or Second Output Enable */
+#define BKP_RTCCR_ASOS_Pos (9U)
+#define BKP_RTCCR_ASOS_Msk (0x1U << BKP_RTCCR_ASOS_Pos) /*!< 0x00000200 */
+#define BKP_RTCCR_ASOS BKP_RTCCR_ASOS_Msk /*!< Alarm or Second Output Selection */
+
+/******************** Bit definition for BKP_CR register ********************/
+#define BKP_CR_TPE_Pos (0U)
+#define BKP_CR_TPE_Msk (0x1U << BKP_CR_TPE_Pos) /*!< 0x00000001 */
+#define BKP_CR_TPE BKP_CR_TPE_Msk /*!< TAMPER pin enable */
+#define BKP_CR_TPAL_Pos (1U)
+#define BKP_CR_TPAL_Msk (0x1U << BKP_CR_TPAL_Pos) /*!< 0x00000002 */
+#define BKP_CR_TPAL BKP_CR_TPAL_Msk /*!< TAMPER pin active level */
+
+/******************* Bit definition for BKP_CSR register ********************/
+#define BKP_CSR_CTE_Pos (0U)
+#define BKP_CSR_CTE_Msk (0x1U << BKP_CSR_CTE_Pos) /*!< 0x00000001 */
+#define BKP_CSR_CTE BKP_CSR_CTE_Msk /*!< Clear Tamper event */
+#define BKP_CSR_CTI_Pos (1U)
+#define BKP_CSR_CTI_Msk (0x1U << BKP_CSR_CTI_Pos) /*!< 0x00000002 */
+#define BKP_CSR_CTI BKP_CSR_CTI_Msk /*!< Clear Tamper Interrupt */
+#define BKP_CSR_TPIE_Pos (2U)
+#define BKP_CSR_TPIE_Msk (0x1U << BKP_CSR_TPIE_Pos) /*!< 0x00000004 */
+#define BKP_CSR_TPIE BKP_CSR_TPIE_Msk /*!< TAMPER Pin interrupt enable */
+#define BKP_CSR_TEF_Pos (8U)
+#define BKP_CSR_TEF_Msk (0x1U << BKP_CSR_TEF_Pos) /*!< 0x00000100 */
+#define BKP_CSR_TEF BKP_CSR_TEF_Msk /*!< Tamper Event Flag */
+#define BKP_CSR_TIF_Pos (9U)
+#define BKP_CSR_TIF_Msk (0x1U << BKP_CSR_TIF_Pos) /*!< 0x00000200 */
+#define BKP_CSR_TIF BKP_CSR_TIF_Msk /*!< Tamper Interrupt Flag */
+
+/******************************************************************************/
+/* */
+/* Reset and Clock Control */
+/* */
+/******************************************************************************/
+
+/******************** Bit definition for RCC_CR register ********************/
+#define RCC_CR_HSION_Pos (0U)
+#define RCC_CR_HSION_Msk (0x1U << RCC_CR_HSION_Pos) /*!< 0x00000001 */
+#define RCC_CR_HSION RCC_CR_HSION_Msk /*!< Internal High Speed clock enable */
+#define RCC_CR_HSIRDY_Pos (1U)
+#define RCC_CR_HSIRDY_Msk (0x1U << RCC_CR_HSIRDY_Pos) /*!< 0x00000002 */
+#define RCC_CR_HSIRDY RCC_CR_HSIRDY_Msk /*!< Internal High Speed clock ready flag */
+#define RCC_CR_HSITRIM_Pos (3U)
+#define RCC_CR_HSITRIM_Msk (0x1FU << RCC_CR_HSITRIM_Pos) /*!< 0x000000F8 */
+#define RCC_CR_HSITRIM RCC_CR_HSITRIM_Msk /*!< Internal High Speed clock trimming */
+#define RCC_CR_HSICAL_Pos (8U)
+#define RCC_CR_HSICAL_Msk (0xFFU << RCC_CR_HSICAL_Pos) /*!< 0x0000FF00 */
+#define RCC_CR_HSICAL RCC_CR_HSICAL_Msk /*!< Internal High Speed clock Calibration */
+#define RCC_CR_HSEON_Pos (16U)
+#define RCC_CR_HSEON_Msk (0x1U << RCC_CR_HSEON_Pos) /*!< 0x00010000 */
+#define RCC_CR_HSEON RCC_CR_HSEON_Msk /*!< External High Speed clock enable */
+#define RCC_CR_HSERDY_Pos (17U)
+#define RCC_CR_HSERDY_Msk (0x1U << RCC_CR_HSERDY_Pos) /*!< 0x00020000 */
+#define RCC_CR_HSERDY RCC_CR_HSERDY_Msk /*!< External High Speed clock ready flag */
+#define RCC_CR_HSEBYP_Pos (18U)
+#define RCC_CR_HSEBYP_Msk (0x1U << RCC_CR_HSEBYP_Pos) /*!< 0x00040000 */
+#define RCC_CR_HSEBYP RCC_CR_HSEBYP_Msk /*!< External High Speed clock Bypass */
+#define RCC_CR_CSSON_Pos (19U)
+#define RCC_CR_CSSON_Msk (0x1U << RCC_CR_CSSON_Pos) /*!< 0x00080000 */
+#define RCC_CR_CSSON RCC_CR_CSSON_Msk /*!< Clock Security System enable */
+#define RCC_CR_PLLON_Pos (24U)
+#define RCC_CR_PLLON_Msk (0x1U << RCC_CR_PLLON_Pos) /*!< 0x01000000 */
+#define RCC_CR_PLLON RCC_CR_PLLON_Msk /*!< PLL enable */
+#define RCC_CR_PLLRDY_Pos (25U)
+#define RCC_CR_PLLRDY_Msk (0x1U << RCC_CR_PLLRDY_Pos) /*!< 0x02000000 */
+#define RCC_CR_PLLRDY RCC_CR_PLLRDY_Msk /*!< PLL clock ready flag */
+
+
+/******************* Bit definition for RCC_CFGR register *******************/
+/*!< SW configuration */
+#define RCC_CFGR_SW_Pos (0U)
+#define RCC_CFGR_SW_Msk (0x3U << RCC_CFGR_SW_Pos) /*!< 0x00000003 */
+#define RCC_CFGR_SW RCC_CFGR_SW_Msk /*!< SW[1:0] bits (System clock Switch) */
+#define RCC_CFGR_SW_0 (0x1U << RCC_CFGR_SW_Pos) /*!< 0x00000001 */
+#define RCC_CFGR_SW_1 (0x2U << RCC_CFGR_SW_Pos) /*!< 0x00000002 */
+
+#define RCC_CFGR_SW_HSI ((uint32_t)0x00000000) /*!< HSI selected as system clock */
+#define RCC_CFGR_SW_HSE ((uint32_t)0x00000001) /*!< HSE selected as system clock */
+#define RCC_CFGR_SW_PLL ((uint32_t)0x00000002) /*!< PLL selected as system clock */
+
+/*!< SWS configuration */
+#define RCC_CFGR_SWS_Pos (2U)
+#define RCC_CFGR_SWS_Msk (0x3U << RCC_CFGR_SWS_Pos) /*!< 0x0000000C */
+#define RCC_CFGR_SWS RCC_CFGR_SWS_Msk /*!< SWS[1:0] bits (System Clock Switch Status) */
+#define RCC_CFGR_SWS_0 (0x1U << RCC_CFGR_SWS_Pos) /*!< 0x00000004 */
+#define RCC_CFGR_SWS_1 (0x2U << RCC_CFGR_SWS_Pos) /*!< 0x00000008 */
+
+#define RCC_CFGR_SWS_HSI ((uint32_t)0x00000000) /*!< HSI oscillator used as system clock */
+#define RCC_CFGR_SWS_HSE ((uint32_t)0x00000004) /*!< HSE oscillator used as system clock */
+#define RCC_CFGR_SWS_PLL ((uint32_t)0x00000008) /*!< PLL used as system clock */
+
+/*!< HPRE configuration */
+#define RCC_CFGR_HPRE_Pos (4U)
+#define RCC_CFGR_HPRE_Msk (0xFU << RCC_CFGR_HPRE_Pos) /*!< 0x000000F0 */
+#define RCC_CFGR_HPRE RCC_CFGR_HPRE_Msk /*!< HPRE[3:0] bits (AHB prescaler) */
+#define RCC_CFGR_HPRE_0 (0x1U << RCC_CFGR_HPRE_Pos) /*!< 0x00000010 */
+#define RCC_CFGR_HPRE_1 (0x2U << RCC_CFGR_HPRE_Pos) /*!< 0x00000020 */
+#define RCC_CFGR_HPRE_2 (0x4U << RCC_CFGR_HPRE_Pos) /*!< 0x00000040 */
+#define RCC_CFGR_HPRE_3 (0x8U << RCC_CFGR_HPRE_Pos) /*!< 0x00000080 */
+
+#define RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000) /*!< SYSCLK not divided */
+#define RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080) /*!< SYSCLK divided by 2 */
+#define RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090) /*!< SYSCLK divided by 4 */
+#define RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0) /*!< SYSCLK divided by 8 */
+#define RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0) /*!< SYSCLK divided by 16 */
+#define RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0) /*!< SYSCLK divided by 64 */
+#define RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0) /*!< SYSCLK divided by 128 */
+#define RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0) /*!< SYSCLK divided by 256 */
+#define RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0) /*!< SYSCLK divided by 512 */
+
+/*!< PPRE1 configuration */
+#define RCC_CFGR_PPRE1_Pos (8U)
+#define RCC_CFGR_PPRE1_Msk (0x7U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000700 */
+#define RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_Msk /*!< PRE1[2:0] bits (APB1 prescaler) */
+#define RCC_CFGR_PPRE1_0 (0x1U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000100 */
+#define RCC_CFGR_PPRE1_1 (0x2U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000200 */
+#define RCC_CFGR_PPRE1_2 (0x4U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000400 */
+
+#define RCC_CFGR_PPRE1_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */
+#define RCC_CFGR_PPRE1_DIV2 ((uint32_t)0x00000400) /*!< HCLK divided by 2 */
+#define RCC_CFGR_PPRE1_DIV4 ((uint32_t)0x00000500) /*!< HCLK divided by 4 */
+#define RCC_CFGR_PPRE1_DIV8 ((uint32_t)0x00000600) /*!< HCLK divided by 8 */
+#define RCC_CFGR_PPRE1_DIV16 ((uint32_t)0x00000700) /*!< HCLK divided by 16 */
+
+/*!< PPRE2 configuration */
+#define RCC_CFGR_PPRE2_Pos (11U)
+#define RCC_CFGR_PPRE2_Msk (0x7U << RCC_CFGR_PPRE2_Pos) /*!< 0x00003800 */
+#define RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_Msk /*!< PRE2[2:0] bits (APB2 prescaler) */
+#define RCC_CFGR_PPRE2_0 (0x1U << RCC_CFGR_PPRE2_Pos) /*!< 0x00000800 */
+#define RCC_CFGR_PPRE2_1 (0x2U << RCC_CFGR_PPRE2_Pos) /*!< 0x00001000 */
+#define RCC_CFGR_PPRE2_2 (0x4U << RCC_CFGR_PPRE2_Pos) /*!< 0x00002000 */
+
+#define RCC_CFGR_PPRE2_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */
+#define RCC_CFGR_PPRE2_DIV2 ((uint32_t)0x00002000) /*!< HCLK divided by 2 */
+#define RCC_CFGR_PPRE2_DIV4 ((uint32_t)0x00002800) /*!< HCLK divided by 4 */
+#define RCC_CFGR_PPRE2_DIV8 ((uint32_t)0x00003000) /*!< HCLK divided by 8 */
+#define RCC_CFGR_PPRE2_DIV16 ((uint32_t)0x00003800) /*!< HCLK divided by 16 */
+
+/*!< ADCPPRE configuration */
+#define RCC_CFGR_ADCPRE_Pos (14U)
+#define RCC_CFGR_ADCPRE_Msk (0x3U << RCC_CFGR_ADCPRE_Pos) /*!< 0x0000C000 */
+#define RCC_CFGR_ADCPRE RCC_CFGR_ADCPRE_Msk /*!< ADCPRE[1:0] bits (ADC prescaler) */
+#define RCC_CFGR_ADCPRE_0 (0x1U << RCC_CFGR_ADCPRE_Pos) /*!< 0x00004000 */
+#define RCC_CFGR_ADCPRE_1 (0x2U << RCC_CFGR_ADCPRE_Pos) /*!< 0x00008000 */
+
+#define RCC_CFGR_ADCPRE_DIV2 ((uint32_t)0x00000000) /*!< PCLK2 divided by 2 */
+#define RCC_CFGR_ADCPRE_DIV4 ((uint32_t)0x00004000) /*!< PCLK2 divided by 4 */
+#define RCC_CFGR_ADCPRE_DIV6 ((uint32_t)0x00008000) /*!< PCLK2 divided by 6 */
+#define RCC_CFGR_ADCPRE_DIV8 ((uint32_t)0x0000C000) /*!< PCLK2 divided by 8 */
+
+#define RCC_CFGR_PLLSRC_Pos (16U)
+#define RCC_CFGR_PLLSRC_Msk (0x1U << RCC_CFGR_PLLSRC_Pos) /*!< 0x00010000 */
+#define RCC_CFGR_PLLSRC RCC_CFGR_PLLSRC_Msk /*!< PLL entry clock source */
+
+#define RCC_CFGR_PLLXTPRE_Pos (17U)
+#define RCC_CFGR_PLLXTPRE_Msk (0x1U << RCC_CFGR_PLLXTPRE_Pos) /*!< 0x00020000 */
+#define RCC_CFGR_PLLXTPRE RCC_CFGR_PLLXTPRE_Msk /*!< HSE divider for PLL entry */
+
+/*!< PLLMUL configuration */
+#define RCC_CFGR_PLLMULL_Pos (18U)
+#define RCC_CFGR_PLLMULL_Msk (0xFU << RCC_CFGR_PLLMULL_Pos) /*!< 0x003C0000 */
+#define RCC_CFGR_PLLMULL RCC_CFGR_PLLMULL_Msk /*!< PLLMUL[3:0] bits (PLL multiplication factor) */
+#define RCC_CFGR_PLLMULL_0 (0x1U << RCC_CFGR_PLLMULL_Pos) /*!< 0x00040000 */
+#define RCC_CFGR_PLLMULL_1 (0x2U << RCC_CFGR_PLLMULL_Pos) /*!< 0x00080000 */
+#define RCC_CFGR_PLLMULL_2 (0x4U << RCC_CFGR_PLLMULL_Pos) /*!< 0x00100000 */
+#define RCC_CFGR_PLLMULL_3 (0x8U << RCC_CFGR_PLLMULL_Pos) /*!< 0x00200000 */
+
+#define RCC_CFGR_PLLXTPRE_HSE ((uint32_t)0x00000000) /*!< HSE clock not divided for PLL entry */
+#define RCC_CFGR_PLLXTPRE_HSE_DIV2 ((uint32_t)0x00020000) /*!< HSE clock divided by 2 for PLL entry */
+
+#define RCC_CFGR_PLLMULL2 ((uint32_t)0x00000000) /*!< PLL input clock*2 */
+#define RCC_CFGR_PLLMULL3_Pos (18U)
+#define RCC_CFGR_PLLMULL3_Msk (0x1U << RCC_CFGR_PLLMULL3_Pos) /*!< 0x00040000 */
+#define RCC_CFGR_PLLMULL3 RCC_CFGR_PLLMULL3_Msk /*!< PLL input clock*3 */
+#define RCC_CFGR_PLLMULL4_Pos (19U)
+#define RCC_CFGR_PLLMULL4_Msk (0x1U << RCC_CFGR_PLLMULL4_Pos) /*!< 0x00080000 */
+#define RCC_CFGR_PLLMULL4 RCC_CFGR_PLLMULL4_Msk /*!< PLL input clock*4 */
+#define RCC_CFGR_PLLMULL5_Pos (18U)
+#define RCC_CFGR_PLLMULL5_Msk (0x3U << RCC_CFGR_PLLMULL5_Pos) /*!< 0x000C0000 */
+#define RCC_CFGR_PLLMULL5 RCC_CFGR_PLLMULL5_Msk /*!< PLL input clock*5 */
+#define RCC_CFGR_PLLMULL6_Pos (20U)
+#define RCC_CFGR_PLLMULL6_Msk (0x1U << RCC_CFGR_PLLMULL6_Pos) /*!< 0x00100000 */
+#define RCC_CFGR_PLLMULL6 RCC_CFGR_PLLMULL6_Msk /*!< PLL input clock*6 */
+#define RCC_CFGR_PLLMULL7_Pos (18U)
+#define RCC_CFGR_PLLMULL7_Msk (0x5U << RCC_CFGR_PLLMULL7_Pos) /*!< 0x00140000 */
+#define RCC_CFGR_PLLMULL7 RCC_CFGR_PLLMULL7_Msk /*!< PLL input clock*7 */
+#define RCC_CFGR_PLLMULL8_Pos (19U)
+#define RCC_CFGR_PLLMULL8_Msk (0x3U << RCC_CFGR_PLLMULL8_Pos) /*!< 0x00180000 */
+#define RCC_CFGR_PLLMULL8 RCC_CFGR_PLLMULL8_Msk /*!< PLL input clock*8 */
+#define RCC_CFGR_PLLMULL9_Pos (18U)
+#define RCC_CFGR_PLLMULL9_Msk (0x7U << RCC_CFGR_PLLMULL9_Pos) /*!< 0x001C0000 */
+#define RCC_CFGR_PLLMULL9 RCC_CFGR_PLLMULL9_Msk /*!< PLL input clock*9 */
+#define RCC_CFGR_PLLMULL10_Pos (21U)
+#define RCC_CFGR_PLLMULL10_Msk (0x1U << RCC_CFGR_PLLMULL10_Pos) /*!< 0x00200000 */
+#define RCC_CFGR_PLLMULL10 RCC_CFGR_PLLMULL10_Msk /*!< PLL input clock10 */
+#define RCC_CFGR_PLLMULL11_Pos (18U)
+#define RCC_CFGR_PLLMULL11_Msk (0x9U << RCC_CFGR_PLLMULL11_Pos) /*!< 0x00240000 */
+#define RCC_CFGR_PLLMULL11 RCC_CFGR_PLLMULL11_Msk /*!< PLL input clock*11 */
+#define RCC_CFGR_PLLMULL12_Pos (19U)
+#define RCC_CFGR_PLLMULL12_Msk (0x5U << RCC_CFGR_PLLMULL12_Pos) /*!< 0x00280000 */
+#define RCC_CFGR_PLLMULL12 RCC_CFGR_PLLMULL12_Msk /*!< PLL input clock*12 */
+#define RCC_CFGR_PLLMULL13_Pos (18U)
+#define RCC_CFGR_PLLMULL13_Msk (0xBU << RCC_CFGR_PLLMULL13_Pos) /*!< 0x002C0000 */
+#define RCC_CFGR_PLLMULL13 RCC_CFGR_PLLMULL13_Msk /*!< PLL input clock*13 */
+#define RCC_CFGR_PLLMULL14_Pos (20U)
+#define RCC_CFGR_PLLMULL14_Msk (0x3U << RCC_CFGR_PLLMULL14_Pos) /*!< 0x00300000 */
+#define RCC_CFGR_PLLMULL14 RCC_CFGR_PLLMULL14_Msk /*!< PLL input clock*14 */
+#define RCC_CFGR_PLLMULL15_Pos (18U)
+#define RCC_CFGR_PLLMULL15_Msk (0xDU << RCC_CFGR_PLLMULL15_Pos) /*!< 0x00340000 */
+#define RCC_CFGR_PLLMULL15 RCC_CFGR_PLLMULL15_Msk /*!< PLL input clock*15 */
+#define RCC_CFGR_PLLMULL16_Pos (19U)
+#define RCC_CFGR_PLLMULL16_Msk (0x7U << RCC_CFGR_PLLMULL16_Pos) /*!< 0x00380000 */
+#define RCC_CFGR_PLLMULL16 RCC_CFGR_PLLMULL16_Msk /*!< PLL input clock*16 */
+
+/*!< MCO configuration */
+#define RCC_CFGR_MCO_Pos (24U)
+#define RCC_CFGR_MCO_Msk (0x7U << RCC_CFGR_MCO_Pos) /*!< 0x07000000 */
+#define RCC_CFGR_MCO RCC_CFGR_MCO_Msk /*!< MCO[2:0] bits (Microcontroller Clock Output) */
+#define RCC_CFGR_MCO_0 (0x1U << RCC_CFGR_MCO_Pos) /*!< 0x01000000 */
+#define RCC_CFGR_MCO_1 (0x2U << RCC_CFGR_MCO_Pos) /*!< 0x02000000 */
+#define RCC_CFGR_MCO_2 (0x4U << RCC_CFGR_MCO_Pos) /*!< 0x04000000 */
+
+#define RCC_CFGR_MCO_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */
+#define RCC_CFGR_MCO_SYSCLK ((uint32_t)0x04000000) /*!< System clock selected as MCO source */
+#define RCC_CFGR_MCO_HSI ((uint32_t)0x05000000) /*!< HSI clock selected as MCO source */
+#define RCC_CFGR_MCO_HSE ((uint32_t)0x06000000) /*!< HSE clock selected as MCO source */
+#define RCC_CFGR_MCO_PLLCLK_DIV2 ((uint32_t)0x07000000) /*!< PLL clock divided by 2 selected as MCO source */
+
+ /* Reference defines */
+ #define RCC_CFGR_MCOSEL RCC_CFGR_MCO
+ #define RCC_CFGR_MCOSEL_0 RCC_CFGR_MCO_0
+ #define RCC_CFGR_MCOSEL_1 RCC_CFGR_MCO_1
+ #define RCC_CFGR_MCOSEL_2 RCC_CFGR_MCO_2
+ #define RCC_CFGR_MCOSEL_NOCLOCK RCC_CFGR_MCO_NOCLOCK
+ #define RCC_CFGR_MCOSEL_SYSCLK RCC_CFGR_MCO_SYSCLK
+ #define RCC_CFGR_MCOSEL_HSI RCC_CFGR_MCO_HSI
+ #define RCC_CFGR_MCOSEL_HSE RCC_CFGR_MCO_HSE
+ #define RCC_CFGR_MCOSEL_PLL_DIV2 RCC_CFGR_MCO_PLLCLK_DIV2
+
+/*!<****************** Bit definition for RCC_CIR register ********************/
+#define RCC_CIR_LSIRDYF_Pos (0U)
+#define RCC_CIR_LSIRDYF_Msk (0x1U << RCC_CIR_LSIRDYF_Pos) /*!< 0x00000001 */
+#define RCC_CIR_LSIRDYF RCC_CIR_LSIRDYF_Msk /*!< LSI Ready Interrupt flag */
+#define RCC_CIR_LSERDYF_Pos (1U)
+#define RCC_CIR_LSERDYF_Msk (0x1U << RCC_CIR_LSERDYF_Pos) /*!< 0x00000002 */
+#define RCC_CIR_LSERDYF RCC_CIR_LSERDYF_Msk /*!< LSE Ready Interrupt flag */
+#define RCC_CIR_HSIRDYF_Pos (2U)
+#define RCC_CIR_HSIRDYF_Msk (0x1U << RCC_CIR_HSIRDYF_Pos) /*!< 0x00000004 */
+#define RCC_CIR_HSIRDYF RCC_CIR_HSIRDYF_Msk /*!< HSI Ready Interrupt flag */
+#define RCC_CIR_HSERDYF_Pos (3U)
+#define RCC_CIR_HSERDYF_Msk (0x1U << RCC_CIR_HSERDYF_Pos) /*!< 0x00000008 */
+#define RCC_CIR_HSERDYF RCC_CIR_HSERDYF_Msk /*!< HSE Ready Interrupt flag */
+#define RCC_CIR_PLLRDYF_Pos (4U)
+#define RCC_CIR_PLLRDYF_Msk (0x1U << RCC_CIR_PLLRDYF_Pos) /*!< 0x00000010 */
+#define RCC_CIR_PLLRDYF RCC_CIR_PLLRDYF_Msk /*!< PLL Ready Interrupt flag */
+#define RCC_CIR_CSSF_Pos (7U)
+#define RCC_CIR_CSSF_Msk (0x1U << RCC_CIR_CSSF_Pos) /*!< 0x00000080 */
+#define RCC_CIR_CSSF RCC_CIR_CSSF_Msk /*!< Clock Security System Interrupt flag */
+#define RCC_CIR_LSIRDYIE_Pos (8U)
+#define RCC_CIR_LSIRDYIE_Msk (0x1U << RCC_CIR_LSIRDYIE_Pos) /*!< 0x00000100 */
+#define RCC_CIR_LSIRDYIE RCC_CIR_LSIRDYIE_Msk /*!< LSI Ready Interrupt Enable */
+#define RCC_CIR_LSERDYIE_Pos (9U)
+#define RCC_CIR_LSERDYIE_Msk (0x1U << RCC_CIR_LSERDYIE_Pos) /*!< 0x00000200 */
+#define RCC_CIR_LSERDYIE RCC_CIR_LSERDYIE_Msk /*!< LSE Ready Interrupt Enable */
+#define RCC_CIR_HSIRDYIE_Pos (10U)
+#define RCC_CIR_HSIRDYIE_Msk (0x1U << RCC_CIR_HSIRDYIE_Pos) /*!< 0x00000400 */
+#define RCC_CIR_HSIRDYIE RCC_CIR_HSIRDYIE_Msk /*!< HSI Ready Interrupt Enable */
+#define RCC_CIR_HSERDYIE_Pos (11U)
+#define RCC_CIR_HSERDYIE_Msk (0x1U << RCC_CIR_HSERDYIE_Pos) /*!< 0x00000800 */
+#define RCC_CIR_HSERDYIE RCC_CIR_HSERDYIE_Msk /*!< HSE Ready Interrupt Enable */
+#define RCC_CIR_PLLRDYIE_Pos (12U)
+#define RCC_CIR_PLLRDYIE_Msk (0x1U << RCC_CIR_PLLRDYIE_Pos) /*!< 0x00001000 */
+#define RCC_CIR_PLLRDYIE RCC_CIR_PLLRDYIE_Msk /*!< PLL Ready Interrupt Enable */
+#define RCC_CIR_LSIRDYC_Pos (16U)
+#define RCC_CIR_LSIRDYC_Msk (0x1U << RCC_CIR_LSIRDYC_Pos) /*!< 0x00010000 */
+#define RCC_CIR_LSIRDYC RCC_CIR_LSIRDYC_Msk /*!< LSI Ready Interrupt Clear */
+#define RCC_CIR_LSERDYC_Pos (17U)
+#define RCC_CIR_LSERDYC_Msk (0x1U << RCC_CIR_LSERDYC_Pos) /*!< 0x00020000 */
+#define RCC_CIR_LSERDYC RCC_CIR_LSERDYC_Msk /*!< LSE Ready Interrupt Clear */
+#define RCC_CIR_HSIRDYC_Pos (18U)
+#define RCC_CIR_HSIRDYC_Msk (0x1U << RCC_CIR_HSIRDYC_Pos) /*!< 0x00040000 */
+#define RCC_CIR_HSIRDYC RCC_CIR_HSIRDYC_Msk /*!< HSI Ready Interrupt Clear */
+#define RCC_CIR_HSERDYC_Pos (19U)
+#define RCC_CIR_HSERDYC_Msk (0x1U << RCC_CIR_HSERDYC_Pos) /*!< 0x00080000 */
+#define RCC_CIR_HSERDYC RCC_CIR_HSERDYC_Msk /*!< HSE Ready Interrupt Clear */
+#define RCC_CIR_PLLRDYC_Pos (20U)
+#define RCC_CIR_PLLRDYC_Msk (0x1U << RCC_CIR_PLLRDYC_Pos) /*!< 0x00100000 */
+#define RCC_CIR_PLLRDYC RCC_CIR_PLLRDYC_Msk /*!< PLL Ready Interrupt Clear */
+#define RCC_CIR_CSSC_Pos (23U)
+#define RCC_CIR_CSSC_Msk (0x1U << RCC_CIR_CSSC_Pos) /*!< 0x00800000 */
+#define RCC_CIR_CSSC RCC_CIR_CSSC_Msk /*!< Clock Security System Interrupt Clear */
+
+
+/***************** Bit definition for RCC_APB2RSTR register *****************/
+#define RCC_APB2RSTR_AFIORST_Pos (0U)
+#define RCC_APB2RSTR_AFIORST_Msk (0x1U << RCC_APB2RSTR_AFIORST_Pos) /*!< 0x00000001 */
+#define RCC_APB2RSTR_AFIORST RCC_APB2RSTR_AFIORST_Msk /*!< Alternate Function I/O reset */
+#define RCC_APB2RSTR_IOPARST_Pos (2U)
+#define RCC_APB2RSTR_IOPARST_Msk (0x1U << RCC_APB2RSTR_IOPARST_Pos) /*!< 0x00000004 */
+#define RCC_APB2RSTR_IOPARST RCC_APB2RSTR_IOPARST_Msk /*!< I/O port A reset */
+#define RCC_APB2RSTR_IOPBRST_Pos (3U)
+#define RCC_APB2RSTR_IOPBRST_Msk (0x1U << RCC_APB2RSTR_IOPBRST_Pos) /*!< 0x00000008 */
+#define RCC_APB2RSTR_IOPBRST RCC_APB2RSTR_IOPBRST_Msk /*!< I/O port B reset */
+#define RCC_APB2RSTR_IOPCRST_Pos (4U)
+#define RCC_APB2RSTR_IOPCRST_Msk (0x1U << RCC_APB2RSTR_IOPCRST_Pos) /*!< 0x00000010 */
+#define RCC_APB2RSTR_IOPCRST RCC_APB2RSTR_IOPCRST_Msk /*!< I/O port C reset */
+#define RCC_APB2RSTR_IOPDRST_Pos (5U)
+#define RCC_APB2RSTR_IOPDRST_Msk (0x1U << RCC_APB2RSTR_IOPDRST_Pos) /*!< 0x00000020 */
+#define RCC_APB2RSTR_IOPDRST RCC_APB2RSTR_IOPDRST_Msk /*!< I/O port D reset */
+#define RCC_APB2RSTR_ADC1RST_Pos (9U)
+#define RCC_APB2RSTR_ADC1RST_Msk (0x1U << RCC_APB2RSTR_ADC1RST_Pos) /*!< 0x00000200 */
+#define RCC_APB2RSTR_ADC1RST RCC_APB2RSTR_ADC1RST_Msk /*!< ADC 1 interface reset */
+
+#define RCC_APB2RSTR_ADC2RST_Pos (10U)
+#define RCC_APB2RSTR_ADC2RST_Msk (0x1U << RCC_APB2RSTR_ADC2RST_Pos) /*!< 0x00000400 */
+#define RCC_APB2RSTR_ADC2RST RCC_APB2RSTR_ADC2RST_Msk /*!< ADC 2 interface reset */
+
+#define RCC_APB2RSTR_TIM1RST_Pos (11U)
+#define RCC_APB2RSTR_TIM1RST_Msk (0x1U << RCC_APB2RSTR_TIM1RST_Pos) /*!< 0x00000800 */
+#define RCC_APB2RSTR_TIM1RST RCC_APB2RSTR_TIM1RST_Msk /*!< TIM1 Timer reset */
+#define RCC_APB2RSTR_SPI1RST_Pos (12U)
+#define RCC_APB2RSTR_SPI1RST_Msk (0x1U << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */
+#define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk /*!< SPI 1 reset */
+#define RCC_APB2RSTR_USART1RST_Pos (14U)
+#define RCC_APB2RSTR_USART1RST_Msk (0x1U << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00004000 */
+#define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk /*!< USART1 reset */
+
+
+#define RCC_APB2RSTR_IOPERST_Pos (6U)
+#define RCC_APB2RSTR_IOPERST_Msk (0x1U << RCC_APB2RSTR_IOPERST_Pos) /*!< 0x00000040 */
+#define RCC_APB2RSTR_IOPERST RCC_APB2RSTR_IOPERST_Msk /*!< I/O port E reset */
+
+#define RCC_APB2RSTR_IOPFRST_Pos (7U)
+#define RCC_APB2RSTR_IOPFRST_Msk (0x1U << RCC_APB2RSTR_IOPFRST_Pos) /*!< 0x00000080 */
+#define RCC_APB2RSTR_IOPFRST RCC_APB2RSTR_IOPFRST_Msk /*!< I/O port F reset */
+#define RCC_APB2RSTR_IOPGRST_Pos (8U)
+#define RCC_APB2RSTR_IOPGRST_Msk (0x1U << RCC_APB2RSTR_IOPGRST_Pos) /*!< 0x00000100 */
+#define RCC_APB2RSTR_IOPGRST RCC_APB2RSTR_IOPGRST_Msk /*!< I/O port G reset */
+
+
+#define RCC_APB2RSTR_TIM9RST_Pos (19U)
+#define RCC_APB2RSTR_TIM9RST_Msk (0x1U << RCC_APB2RSTR_TIM9RST_Pos) /*!< 0x00080000 */
+#define RCC_APB2RSTR_TIM9RST RCC_APB2RSTR_TIM9RST_Msk /*!< TIM9 Timer reset */
+#define RCC_APB2RSTR_TIM10RST_Pos (20U)
+#define RCC_APB2RSTR_TIM10RST_Msk (0x1U << RCC_APB2RSTR_TIM10RST_Pos) /*!< 0x00100000 */
+#define RCC_APB2RSTR_TIM10RST RCC_APB2RSTR_TIM10RST_Msk /*!< TIM10 Timer reset */
+#define RCC_APB2RSTR_TIM11RST_Pos (21U)
+#define RCC_APB2RSTR_TIM11RST_Msk (0x1U << RCC_APB2RSTR_TIM11RST_Pos) /*!< 0x00200000 */
+#define RCC_APB2RSTR_TIM11RST RCC_APB2RSTR_TIM11RST_Msk /*!< TIM11 Timer reset */
+
+/***************** Bit definition for RCC_APB1RSTR register *****************/
+#define RCC_APB1RSTR_TIM2RST_Pos (0U)
+#define RCC_APB1RSTR_TIM2RST_Msk (0x1U << RCC_APB1RSTR_TIM2RST_Pos) /*!< 0x00000001 */
+#define RCC_APB1RSTR_TIM2RST RCC_APB1RSTR_TIM2RST_Msk /*!< Timer 2 reset */
+#define RCC_APB1RSTR_TIM3RST_Pos (1U)
+#define RCC_APB1RSTR_TIM3RST_Msk (0x1U << RCC_APB1RSTR_TIM3RST_Pos) /*!< 0x00000002 */
+#define RCC_APB1RSTR_TIM3RST RCC_APB1RSTR_TIM3RST_Msk /*!< Timer 3 reset */
+#define RCC_APB1RSTR_WWDGRST_Pos (11U)
+#define RCC_APB1RSTR_WWDGRST_Msk (0x1U << RCC_APB1RSTR_WWDGRST_Pos) /*!< 0x00000800 */
+#define RCC_APB1RSTR_WWDGRST RCC_APB1RSTR_WWDGRST_Msk /*!< Window Watchdog reset */
+#define RCC_APB1RSTR_USART2RST_Pos (17U)
+#define RCC_APB1RSTR_USART2RST_Msk (0x1U << RCC_APB1RSTR_USART2RST_Pos) /*!< 0x00020000 */
+#define RCC_APB1RSTR_USART2RST RCC_APB1RSTR_USART2RST_Msk /*!< USART 2 reset */
+#define RCC_APB1RSTR_I2C1RST_Pos (21U)
+#define RCC_APB1RSTR_I2C1RST_Msk (0x1U << RCC_APB1RSTR_I2C1RST_Pos) /*!< 0x00200000 */
+#define RCC_APB1RSTR_I2C1RST RCC_APB1RSTR_I2C1RST_Msk /*!< I2C 1 reset */
+
+
+#define RCC_APB1RSTR_BKPRST_Pos (27U)
+#define RCC_APB1RSTR_BKPRST_Msk (0x1U << RCC_APB1RSTR_BKPRST_Pos) /*!< 0x08000000 */
+#define RCC_APB1RSTR_BKPRST RCC_APB1RSTR_BKPRST_Msk /*!< Backup interface reset */
+#define RCC_APB1RSTR_PWRRST_Pos (28U)
+#define RCC_APB1RSTR_PWRRST_Msk (0x1U << RCC_APB1RSTR_PWRRST_Pos) /*!< 0x10000000 */
+#define RCC_APB1RSTR_PWRRST RCC_APB1RSTR_PWRRST_Msk /*!< Power interface reset */
+
+#define RCC_APB1RSTR_TIM4RST_Pos (2U)
+#define RCC_APB1RSTR_TIM4RST_Msk (0x1U << RCC_APB1RSTR_TIM4RST_Pos) /*!< 0x00000004 */
+#define RCC_APB1RSTR_TIM4RST RCC_APB1RSTR_TIM4RST_Msk /*!< Timer 4 reset */
+#define RCC_APB1RSTR_SPI2RST_Pos (14U)
+#define RCC_APB1RSTR_SPI2RST_Msk (0x1U << RCC_APB1RSTR_SPI2RST_Pos) /*!< 0x00004000 */
+#define RCC_APB1RSTR_SPI2RST RCC_APB1RSTR_SPI2RST_Msk /*!< SPI 2 reset */
+#define RCC_APB1RSTR_USART3RST_Pos (18U)
+#define RCC_APB1RSTR_USART3RST_Msk (0x1U << RCC_APB1RSTR_USART3RST_Pos) /*!< 0x00040000 */
+#define RCC_APB1RSTR_USART3RST RCC_APB1RSTR_USART3RST_Msk /*!< USART 3 reset */
+#define RCC_APB1RSTR_I2C2RST_Pos (22U)
+#define RCC_APB1RSTR_I2C2RST_Msk (0x1U << RCC_APB1RSTR_I2C2RST_Pos) /*!< 0x00400000 */
+#define RCC_APB1RSTR_I2C2RST RCC_APB1RSTR_I2C2RST_Msk /*!< I2C 2 reset */
+
+
+#define RCC_APB1RSTR_TIM5RST_Pos (3U)
+#define RCC_APB1RSTR_TIM5RST_Msk (0x1U << RCC_APB1RSTR_TIM5RST_Pos) /*!< 0x00000008 */
+#define RCC_APB1RSTR_TIM5RST RCC_APB1RSTR_TIM5RST_Msk /*!< Timer 5 reset */
+#define RCC_APB1RSTR_TIM6RST_Pos (4U)
+#define RCC_APB1RSTR_TIM6RST_Msk (0x1U << RCC_APB1RSTR_TIM6RST_Pos) /*!< 0x00000010 */
+#define RCC_APB1RSTR_TIM6RST RCC_APB1RSTR_TIM6RST_Msk /*!< Timer 6 reset */
+#define RCC_APB1RSTR_TIM7RST_Pos (5U)
+#define RCC_APB1RSTR_TIM7RST_Msk (0x1U << RCC_APB1RSTR_TIM7RST_Pos) /*!< 0x00000020 */
+#define RCC_APB1RSTR_TIM7RST RCC_APB1RSTR_TIM7RST_Msk /*!< Timer 7 reset */
+#define RCC_APB1RSTR_SPI3RST_Pos (15U)
+#define RCC_APB1RSTR_SPI3RST_Msk (0x1U << RCC_APB1RSTR_SPI3RST_Pos) /*!< 0x00008000 */
+#define RCC_APB1RSTR_SPI3RST RCC_APB1RSTR_SPI3RST_Msk /*!< SPI 3 reset */
+#define RCC_APB1RSTR_UART4RST_Pos (19U)
+#define RCC_APB1RSTR_UART4RST_Msk (0x1U << RCC_APB1RSTR_UART4RST_Pos) /*!< 0x00080000 */
+#define RCC_APB1RSTR_UART4RST RCC_APB1RSTR_UART4RST_Msk /*!< UART 4 reset */
+#define RCC_APB1RSTR_UART5RST_Pos (20U)
+#define RCC_APB1RSTR_UART5RST_Msk (0x1U << RCC_APB1RSTR_UART5RST_Pos) /*!< 0x00100000 */
+#define RCC_APB1RSTR_UART5RST RCC_APB1RSTR_UART5RST_Msk /*!< UART 5 reset */
+
+
+
+
+#define RCC_APB1RSTR_TIM12RST_Pos (6U)
+#define RCC_APB1RSTR_TIM12RST_Msk (0x1U << RCC_APB1RSTR_TIM12RST_Pos) /*!< 0x00000040 */
+#define RCC_APB1RSTR_TIM12RST RCC_APB1RSTR_TIM12RST_Msk /*!< TIM12 Timer reset */
+#define RCC_APB1RSTR_TIM13RST_Pos (7U)
+#define RCC_APB1RSTR_TIM13RST_Msk (0x1U << RCC_APB1RSTR_TIM13RST_Pos) /*!< 0x00000080 */
+#define RCC_APB1RSTR_TIM13RST RCC_APB1RSTR_TIM13RST_Msk /*!< TIM13 Timer reset */
+#define RCC_APB1RSTR_TIM14RST_Pos (8U)
+#define RCC_APB1RSTR_TIM14RST_Msk (0x1U << RCC_APB1RSTR_TIM14RST_Pos) /*!< 0x00000100 */
+#define RCC_APB1RSTR_TIM14RST RCC_APB1RSTR_TIM14RST_Msk /*!< TIM14 Timer reset */
+#define RCC_APB1RSTR_DACRST_Pos (29U)
+#define RCC_APB1RSTR_DACRST_Msk (0x1U << RCC_APB1RSTR_DACRST_Pos) /*!< 0x20000000 */
+#define RCC_APB1RSTR_DACRST RCC_APB1RSTR_DACRST_Msk /*!< DAC interface reset */
+
+/****************** Bit definition for RCC_AHBENR register ******************/
+#define RCC_AHBENR_DMA1EN_Pos (0U)
+#define RCC_AHBENR_DMA1EN_Msk (0x1U << RCC_AHBENR_DMA1EN_Pos) /*!< 0x00000001 */
+#define RCC_AHBENR_DMA1EN RCC_AHBENR_DMA1EN_Msk /*!< DMA1 clock enable */
+#define RCC_AHBENR_SRAMEN_Pos (2U)
+#define RCC_AHBENR_SRAMEN_Msk (0x1U << RCC_AHBENR_SRAMEN_Pos) /*!< 0x00000004 */
+#define RCC_AHBENR_SRAMEN RCC_AHBENR_SRAMEN_Msk /*!< SRAM interface clock enable */
+#define RCC_AHBENR_FLITFEN_Pos (4U)
+#define RCC_AHBENR_FLITFEN_Msk (0x1U << RCC_AHBENR_FLITFEN_Pos) /*!< 0x00000010 */
+#define RCC_AHBENR_FLITFEN RCC_AHBENR_FLITFEN_Msk /*!< FLITF clock enable */
+#define RCC_AHBENR_CRCEN_Pos (6U)
+#define RCC_AHBENR_CRCEN_Msk (0x1U << RCC_AHBENR_CRCEN_Pos) /*!< 0x00000040 */
+#define RCC_AHBENR_CRCEN RCC_AHBENR_CRCEN_Msk /*!< CRC clock enable */
+
+#define RCC_AHBENR_DMA2EN_Pos (1U)
+#define RCC_AHBENR_DMA2EN_Msk (0x1U << RCC_AHBENR_DMA2EN_Pos) /*!< 0x00000002 */
+#define RCC_AHBENR_DMA2EN RCC_AHBENR_DMA2EN_Msk /*!< DMA2 clock enable */
+
+#define RCC_AHBENR_FSMCEN_Pos (8U)
+#define RCC_AHBENR_FSMCEN_Msk (0x1U << RCC_AHBENR_FSMCEN_Pos) /*!< 0x00000100 */
+#define RCC_AHBENR_FSMCEN RCC_AHBENR_FSMCEN_Msk /*!< FSMC clock enable */
+
+
+/****************** Bit definition for RCC_APB2ENR register *****************/
+#define RCC_APB2ENR_AFIOEN_Pos (0U)
+#define RCC_APB2ENR_AFIOEN_Msk (0x1U << RCC_APB2ENR_AFIOEN_Pos) /*!< 0x00000001 */
+#define RCC_APB2ENR_AFIOEN RCC_APB2ENR_AFIOEN_Msk /*!< Alternate Function I/O clock enable */
+#define RCC_APB2ENR_IOPAEN_Pos (2U)
+#define RCC_APB2ENR_IOPAEN_Msk (0x1U << RCC_APB2ENR_IOPAEN_Pos) /*!< 0x00000004 */
+#define RCC_APB2ENR_IOPAEN RCC_APB2ENR_IOPAEN_Msk /*!< I/O port A clock enable */
+#define RCC_APB2ENR_IOPBEN_Pos (3U)
+#define RCC_APB2ENR_IOPBEN_Msk (0x1U << RCC_APB2ENR_IOPBEN_Pos) /*!< 0x00000008 */
+#define RCC_APB2ENR_IOPBEN RCC_APB2ENR_IOPBEN_Msk /*!< I/O port B clock enable */
+#define RCC_APB2ENR_IOPCEN_Pos (4U)
+#define RCC_APB2ENR_IOPCEN_Msk (0x1U << RCC_APB2ENR_IOPCEN_Pos) /*!< 0x00000010 */
+#define RCC_APB2ENR_IOPCEN RCC_APB2ENR_IOPCEN_Msk /*!< I/O port C clock enable */
+#define RCC_APB2ENR_IOPDEN_Pos (5U)
+#define RCC_APB2ENR_IOPDEN_Msk (0x1U << RCC_APB2ENR_IOPDEN_Pos) /*!< 0x00000020 */
+#define RCC_APB2ENR_IOPDEN RCC_APB2ENR_IOPDEN_Msk /*!< I/O port D clock enable */
+#define RCC_APB2ENR_ADC1EN_Pos (9U)
+#define RCC_APB2ENR_ADC1EN_Msk (0x1U << RCC_APB2ENR_ADC1EN_Pos) /*!< 0x00000200 */
+#define RCC_APB2ENR_ADC1EN RCC_APB2ENR_ADC1EN_Msk /*!< ADC 1 interface clock enable */
+
+#define RCC_APB2ENR_ADC2EN_Pos (10U)
+#define RCC_APB2ENR_ADC2EN_Msk (0x1U << RCC_APB2ENR_ADC2EN_Pos) /*!< 0x00000400 */
+#define RCC_APB2ENR_ADC2EN RCC_APB2ENR_ADC2EN_Msk /*!< ADC 2 interface clock enable */
+
+#define RCC_APB2ENR_TIM1EN_Pos (11U)
+#define RCC_APB2ENR_TIM1EN_Msk (0x1U << RCC_APB2ENR_TIM1EN_Pos) /*!< 0x00000800 */
+#define RCC_APB2ENR_TIM1EN RCC_APB2ENR_TIM1EN_Msk /*!< TIM1 Timer clock enable */
+#define RCC_APB2ENR_SPI1EN_Pos (12U)
+#define RCC_APB2ENR_SPI1EN_Msk (0x1U << RCC_APB2ENR_SPI1EN_Pos) /*!< 0x00001000 */
+#define RCC_APB2ENR_SPI1EN RCC_APB2ENR_SPI1EN_Msk /*!< SPI 1 clock enable */
+#define RCC_APB2ENR_USART1EN_Pos (14U)
+#define RCC_APB2ENR_USART1EN_Msk (0x1U << RCC_APB2ENR_USART1EN_Pos) /*!< 0x00004000 */
+#define RCC_APB2ENR_USART1EN RCC_APB2ENR_USART1EN_Msk /*!< USART1 clock enable */
+
+
+#define RCC_APB2ENR_IOPEEN_Pos (6U)
+#define RCC_APB2ENR_IOPEEN_Msk (0x1U << RCC_APB2ENR_IOPEEN_Pos) /*!< 0x00000040 */
+#define RCC_APB2ENR_IOPEEN RCC_APB2ENR_IOPEEN_Msk /*!< I/O port E clock enable */
+
+#define RCC_APB2ENR_IOPFEN_Pos (7U)
+#define RCC_APB2ENR_IOPFEN_Msk (0x1U << RCC_APB2ENR_IOPFEN_Pos) /*!< 0x00000080 */
+#define RCC_APB2ENR_IOPFEN RCC_APB2ENR_IOPFEN_Msk /*!< I/O port F clock enable */
+#define RCC_APB2ENR_IOPGEN_Pos (8U)
+#define RCC_APB2ENR_IOPGEN_Msk (0x1U << RCC_APB2ENR_IOPGEN_Pos) /*!< 0x00000100 */
+#define RCC_APB2ENR_IOPGEN RCC_APB2ENR_IOPGEN_Msk /*!< I/O port G clock enable */
+
+
+#define RCC_APB2ENR_TIM9EN_Pos (19U)
+#define RCC_APB2ENR_TIM9EN_Msk (0x1U << RCC_APB2ENR_TIM9EN_Pos) /*!< 0x00080000 */
+#define RCC_APB2ENR_TIM9EN RCC_APB2ENR_TIM9EN_Msk /*!< TIM9 Timer clock enable */
+#define RCC_APB2ENR_TIM10EN_Pos (20U)
+#define RCC_APB2ENR_TIM10EN_Msk (0x1U << RCC_APB2ENR_TIM10EN_Pos) /*!< 0x00100000 */
+#define RCC_APB2ENR_TIM10EN RCC_APB2ENR_TIM10EN_Msk /*!< TIM10 Timer clock enable */
+#define RCC_APB2ENR_TIM11EN_Pos (21U)
+#define RCC_APB2ENR_TIM11EN_Msk (0x1U << RCC_APB2ENR_TIM11EN_Pos) /*!< 0x00200000 */
+#define RCC_APB2ENR_TIM11EN RCC_APB2ENR_TIM11EN_Msk /*!< TIM11 Timer clock enable */
+
+/***************** Bit definition for RCC_APB1ENR register ******************/
+#define RCC_APB1ENR_TIM2EN_Pos (0U)
+#define RCC_APB1ENR_TIM2EN_Msk (0x1U << RCC_APB1ENR_TIM2EN_Pos) /*!< 0x00000001 */
+#define RCC_APB1ENR_TIM2EN RCC_APB1ENR_TIM2EN_Msk /*!< Timer 2 clock enabled*/
+#define RCC_APB1ENR_TIM3EN_Pos (1U)
+#define RCC_APB1ENR_TIM3EN_Msk (0x1U << RCC_APB1ENR_TIM3EN_Pos) /*!< 0x00000002 */
+#define RCC_APB1ENR_TIM3EN RCC_APB1ENR_TIM3EN_Msk /*!< Timer 3 clock enable */
+#define RCC_APB1ENR_WWDGEN_Pos (11U)
+#define RCC_APB1ENR_WWDGEN_Msk (0x1U << RCC_APB1ENR_WWDGEN_Pos) /*!< 0x00000800 */
+#define RCC_APB1ENR_WWDGEN RCC_APB1ENR_WWDGEN_Msk /*!< Window Watchdog clock enable */
+#define RCC_APB1ENR_USART2EN_Pos (17U)
+#define RCC_APB1ENR_USART2EN_Msk (0x1U << RCC_APB1ENR_USART2EN_Pos) /*!< 0x00020000 */
+#define RCC_APB1ENR_USART2EN RCC_APB1ENR_USART2EN_Msk /*!< USART 2 clock enable */
+#define RCC_APB1ENR_I2C1EN_Pos (21U)
+#define RCC_APB1ENR_I2C1EN_Msk (0x1U << RCC_APB1ENR_I2C1EN_Pos) /*!< 0x00200000 */
+#define RCC_APB1ENR_I2C1EN RCC_APB1ENR_I2C1EN_Msk /*!< I2C 1 clock enable */
+
+
+#define RCC_APB1ENR_BKPEN_Pos (27U)
+#define RCC_APB1ENR_BKPEN_Msk (0x1U << RCC_APB1ENR_BKPEN_Pos) /*!< 0x08000000 */
+#define RCC_APB1ENR_BKPEN RCC_APB1ENR_BKPEN_Msk /*!< Backup interface clock enable */
+#define RCC_APB1ENR_PWREN_Pos (28U)
+#define RCC_APB1ENR_PWREN_Msk (0x1U << RCC_APB1ENR_PWREN_Pos) /*!< 0x10000000 */
+#define RCC_APB1ENR_PWREN RCC_APB1ENR_PWREN_Msk /*!< Power interface clock enable */
+
+#define RCC_APB1ENR_TIM4EN_Pos (2U)
+#define RCC_APB1ENR_TIM4EN_Msk (0x1U << RCC_APB1ENR_TIM4EN_Pos) /*!< 0x00000004 */
+#define RCC_APB1ENR_TIM4EN RCC_APB1ENR_TIM4EN_Msk /*!< Timer 4 clock enable */
+#define RCC_APB1ENR_SPI2EN_Pos (14U)
+#define RCC_APB1ENR_SPI2EN_Msk (0x1U << RCC_APB1ENR_SPI2EN_Pos) /*!< 0x00004000 */
+#define RCC_APB1ENR_SPI2EN RCC_APB1ENR_SPI2EN_Msk /*!< SPI 2 clock enable */
+#define RCC_APB1ENR_USART3EN_Pos (18U)
+#define RCC_APB1ENR_USART3EN_Msk (0x1U << RCC_APB1ENR_USART3EN_Pos) /*!< 0x00040000 */
+#define RCC_APB1ENR_USART3EN RCC_APB1ENR_USART3EN_Msk /*!< USART 3 clock enable */
+#define RCC_APB1ENR_I2C2EN_Pos (22U)
+#define RCC_APB1ENR_I2C2EN_Msk (0x1U << RCC_APB1ENR_I2C2EN_Pos) /*!< 0x00400000 */
+#define RCC_APB1ENR_I2C2EN RCC_APB1ENR_I2C2EN_Msk /*!< I2C 2 clock enable */
+
+
+#define RCC_APB1ENR_TIM5EN_Pos (3U)
+#define RCC_APB1ENR_TIM5EN_Msk (0x1U << RCC_APB1ENR_TIM5EN_Pos) /*!< 0x00000008 */
+#define RCC_APB1ENR_TIM5EN RCC_APB1ENR_TIM5EN_Msk /*!< Timer 5 clock enable */
+#define RCC_APB1ENR_TIM6EN_Pos (4U)
+#define RCC_APB1ENR_TIM6EN_Msk (0x1U << RCC_APB1ENR_TIM6EN_Pos) /*!< 0x00000010 */
+#define RCC_APB1ENR_TIM6EN RCC_APB1ENR_TIM6EN_Msk /*!< Timer 6 clock enable */
+#define RCC_APB1ENR_TIM7EN_Pos (5U)
+#define RCC_APB1ENR_TIM7EN_Msk (0x1U << RCC_APB1ENR_TIM7EN_Pos) /*!< 0x00000020 */
+#define RCC_APB1ENR_TIM7EN RCC_APB1ENR_TIM7EN_Msk /*!< Timer 7 clock enable */
+#define RCC_APB1ENR_SPI3EN_Pos (15U)
+#define RCC_APB1ENR_SPI3EN_Msk (0x1U << RCC_APB1ENR_SPI3EN_Pos) /*!< 0x00008000 */
+#define RCC_APB1ENR_SPI3EN RCC_APB1ENR_SPI3EN_Msk /*!< SPI 3 clock enable */
+#define RCC_APB1ENR_UART4EN_Pos (19U)
+#define RCC_APB1ENR_UART4EN_Msk (0x1U << RCC_APB1ENR_UART4EN_Pos) /*!< 0x00080000 */
+#define RCC_APB1ENR_UART4EN RCC_APB1ENR_UART4EN_Msk /*!< UART 4 clock enable */
+#define RCC_APB1ENR_UART5EN_Pos (20U)
+#define RCC_APB1ENR_UART5EN_Msk (0x1U << RCC_APB1ENR_UART5EN_Pos) /*!< 0x00100000 */
+#define RCC_APB1ENR_UART5EN RCC_APB1ENR_UART5EN_Msk /*!< UART 5 clock enable */
+
+
+
+
+#define RCC_APB1ENR_TIM12EN_Pos (6U)
+#define RCC_APB1ENR_TIM12EN_Msk (0x1U << RCC_APB1ENR_TIM12EN_Pos) /*!< 0x00000040 */
+#define RCC_APB1ENR_TIM12EN RCC_APB1ENR_TIM12EN_Msk /*!< TIM12 Timer clock enable */
+#define RCC_APB1ENR_TIM13EN_Pos (7U)
+#define RCC_APB1ENR_TIM13EN_Msk (0x1U << RCC_APB1ENR_TIM13EN_Pos) /*!< 0x00000080 */
+#define RCC_APB1ENR_TIM13EN RCC_APB1ENR_TIM13EN_Msk /*!< TIM13 Timer clock enable */
+#define RCC_APB1ENR_TIM14EN_Pos (8U)
+#define RCC_APB1ENR_TIM14EN_Msk (0x1U << RCC_APB1ENR_TIM14EN_Pos) /*!< 0x00000100 */
+#define RCC_APB1ENR_TIM14EN RCC_APB1ENR_TIM14EN_Msk /*!< TIM14 Timer clock enable */
+#define RCC_APB1ENR_DACEN_Pos (29U)
+#define RCC_APB1ENR_DACEN_Msk (0x1U << RCC_APB1ENR_DACEN_Pos) /*!< 0x20000000 */
+#define RCC_APB1ENR_DACEN RCC_APB1ENR_DACEN_Msk /*!< DAC interface clock enable */
+
+/******************* Bit definition for RCC_BDCR register *******************/
+#define RCC_BDCR_LSEON_Pos (0U)
+#define RCC_BDCR_LSEON_Msk (0x1U << RCC_BDCR_LSEON_Pos) /*!< 0x00000001 */
+#define RCC_BDCR_LSEON RCC_BDCR_LSEON_Msk /*!< External Low Speed oscillator enable */
+#define RCC_BDCR_LSERDY_Pos (1U)
+#define RCC_BDCR_LSERDY_Msk (0x1U << RCC_BDCR_LSERDY_Pos) /*!< 0x00000002 */
+#define RCC_BDCR_LSERDY RCC_BDCR_LSERDY_Msk /*!< External Low Speed oscillator Ready */
+#define RCC_BDCR_LSEBYP_Pos (2U)
+#define RCC_BDCR_LSEBYP_Msk (0x1U << RCC_BDCR_LSEBYP_Pos) /*!< 0x00000004 */
+#define RCC_BDCR_LSEBYP RCC_BDCR_LSEBYP_Msk /*!< External Low Speed oscillator Bypass */
+
+#define RCC_BDCR_RTCSEL_Pos (8U)
+#define RCC_BDCR_RTCSEL_Msk (0x3U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000300 */
+#define RCC_BDCR_RTCSEL RCC_BDCR_RTCSEL_Msk /*!< RTCSEL[1:0] bits (RTC clock source selection) */
+#define RCC_BDCR_RTCSEL_0 (0x1U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000100 */
+#define RCC_BDCR_RTCSEL_1 (0x2U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000200 */
+
+/*!< RTC congiguration */
+#define RCC_BDCR_RTCSEL_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */
+#define RCC_BDCR_RTCSEL_LSE ((uint32_t)0x00000100) /*!< LSE oscillator clock used as RTC clock */
+#define RCC_BDCR_RTCSEL_LSI ((uint32_t)0x00000200) /*!< LSI oscillator clock used as RTC clock */
+#define RCC_BDCR_RTCSEL_HSE ((uint32_t)0x00000300) /*!< HSE oscillator clock divided by 128 used as RTC clock */
+
+#define RCC_BDCR_RTCEN_Pos (15U)
+#define RCC_BDCR_RTCEN_Msk (0x1U << RCC_BDCR_RTCEN_Pos) /*!< 0x00008000 */
+#define RCC_BDCR_RTCEN RCC_BDCR_RTCEN_Msk /*!< RTC clock enable */
+#define RCC_BDCR_BDRST_Pos (16U)
+#define RCC_BDCR_BDRST_Msk (0x1U << RCC_BDCR_BDRST_Pos) /*!< 0x00010000 */
+#define RCC_BDCR_BDRST RCC_BDCR_BDRST_Msk /*!< Backup domain software reset */
+
+/******************* Bit definition for RCC_CSR register ********************/
+#define RCC_CSR_LSION_Pos (0U)
+#define RCC_CSR_LSION_Msk (0x1U << RCC_CSR_LSION_Pos) /*!< 0x00000001 */
+#define RCC_CSR_LSION RCC_CSR_LSION_Msk /*!< Internal Low Speed oscillator enable */
+#define RCC_CSR_LSIRDY_Pos (1U)
+#define RCC_CSR_LSIRDY_Msk (0x1U << RCC_CSR_LSIRDY_Pos) /*!< 0x00000002 */
+#define RCC_CSR_LSIRDY RCC_CSR_LSIRDY_Msk /*!< Internal Low Speed oscillator Ready */
+#define RCC_CSR_RMVF_Pos (24U)
+#define RCC_CSR_RMVF_Msk (0x1U << RCC_CSR_RMVF_Pos) /*!< 0x01000000 */
+#define RCC_CSR_RMVF RCC_CSR_RMVF_Msk /*!< Remove reset flag */
+#define RCC_CSR_PINRSTF_Pos (26U)
+#define RCC_CSR_PINRSTF_Msk (0x1U << RCC_CSR_PINRSTF_Pos) /*!< 0x04000000 */
+#define RCC_CSR_PINRSTF RCC_CSR_PINRSTF_Msk /*!< PIN reset flag */
+#define RCC_CSR_PORRSTF_Pos (27U)
+#define RCC_CSR_PORRSTF_Msk (0x1U << RCC_CSR_PORRSTF_Pos) /*!< 0x08000000 */
+#define RCC_CSR_PORRSTF RCC_CSR_PORRSTF_Msk /*!< POR/PDR reset flag */
+#define RCC_CSR_SFTRSTF_Pos (28U)
+#define RCC_CSR_SFTRSTF_Msk (0x1U << RCC_CSR_SFTRSTF_Pos) /*!< 0x10000000 */
+#define RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF_Msk /*!< Software Reset flag */
+#define RCC_CSR_IWDGRSTF_Pos (29U)
+#define RCC_CSR_IWDGRSTF_Msk (0x1U << RCC_CSR_IWDGRSTF_Pos) /*!< 0x20000000 */
+#define RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF_Msk /*!< Independent Watchdog reset flag */
+#define RCC_CSR_WWDGRSTF_Pos (30U)
+#define RCC_CSR_WWDGRSTF_Msk (0x1U << RCC_CSR_WWDGRSTF_Pos) /*!< 0x40000000 */
+#define RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF_Msk /*!< Window watchdog reset flag */
+#define RCC_CSR_LPWRRSTF_Pos (31U)
+#define RCC_CSR_LPWRRSTF_Msk (0x1U << RCC_CSR_LPWRRSTF_Pos) /*!< 0x80000000 */
+#define RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF_Msk /*!< Low-Power reset flag */
+
+
+
+/******************************************************************************/
+/* */
+/* General Purpose and Alternate Function I/O */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for GPIO_CRL register *******************/
+#define GPIO_CRL_MODE_Pos (0U)
+#define GPIO_CRL_MODE_Msk (0x33333333U << GPIO_CRL_MODE_Pos) /*!< 0x33333333 */
+#define GPIO_CRL_MODE GPIO_CRL_MODE_Msk /*!< Port x mode bits */
+
+#define GPIO_CRL_MODE0_Pos (0U)
+#define GPIO_CRL_MODE0_Msk (0x3U << GPIO_CRL_MODE0_Pos) /*!< 0x00000003 */
+#define GPIO_CRL_MODE0 GPIO_CRL_MODE0_Msk /*!< MODE0[1:0] bits (Port x mode bits, pin 0) */
+#define GPIO_CRL_MODE0_0 (0x1U << GPIO_CRL_MODE0_Pos) /*!< 0x00000001 */
+#define GPIO_CRL_MODE0_1 (0x2U << GPIO_CRL_MODE0_Pos) /*!< 0x00000002 */
+
+#define GPIO_CRL_MODE1_Pos (4U)
+#define GPIO_CRL_MODE1_Msk (0x3U << GPIO_CRL_MODE1_Pos) /*!< 0x00000030 */
+#define GPIO_CRL_MODE1 GPIO_CRL_MODE1_Msk /*!< MODE1[1:0] bits (Port x mode bits, pin 1) */
+#define GPIO_CRL_MODE1_0 (0x1U << GPIO_CRL_MODE1_Pos) /*!< 0x00000010 */
+#define GPIO_CRL_MODE1_1 (0x2U << GPIO_CRL_MODE1_Pos) /*!< 0x00000020 */
+
+#define GPIO_CRL_MODE2_Pos (8U)
+#define GPIO_CRL_MODE2_Msk (0x3U << GPIO_CRL_MODE2_Pos) /*!< 0x00000300 */
+#define GPIO_CRL_MODE2 GPIO_CRL_MODE2_Msk /*!< MODE2[1:0] bits (Port x mode bits, pin 2) */
+#define GPIO_CRL_MODE2_0 (0x1U << GPIO_CRL_MODE2_Pos) /*!< 0x00000100 */
+#define GPIO_CRL_MODE2_1 (0x2U << GPIO_CRL_MODE2_Pos) /*!< 0x00000200 */
+
+#define GPIO_CRL_MODE3_Pos (12U)
+#define GPIO_CRL_MODE3_Msk (0x3U << GPIO_CRL_MODE3_Pos) /*!< 0x00003000 */
+#define GPIO_CRL_MODE3 GPIO_CRL_MODE3_Msk /*!< MODE3[1:0] bits (Port x mode bits, pin 3) */
+#define GPIO_CRL_MODE3_0 (0x1U << GPIO_CRL_MODE3_Pos) /*!< 0x00001000 */
+#define GPIO_CRL_MODE3_1 (0x2U << GPIO_CRL_MODE3_Pos) /*!< 0x00002000 */
+
+#define GPIO_CRL_MODE4_Pos (16U)
+#define GPIO_CRL_MODE4_Msk (0x3U << GPIO_CRL_MODE4_Pos) /*!< 0x00030000 */
+#define GPIO_CRL_MODE4 GPIO_CRL_MODE4_Msk /*!< MODE4[1:0] bits (Port x mode bits, pin 4) */
+#define GPIO_CRL_MODE4_0 (0x1U << GPIO_CRL_MODE4_Pos) /*!< 0x00010000 */
+#define GPIO_CRL_MODE4_1 (0x2U << GPIO_CRL_MODE4_Pos) /*!< 0x00020000 */
+
+#define GPIO_CRL_MODE5_Pos (20U)
+#define GPIO_CRL_MODE5_Msk (0x3U << GPIO_CRL_MODE5_Pos) /*!< 0x00300000 */
+#define GPIO_CRL_MODE5 GPIO_CRL_MODE5_Msk /*!< MODE5[1:0] bits (Port x mode bits, pin 5) */
+#define GPIO_CRL_MODE5_0 (0x1U << GPIO_CRL_MODE5_Pos) /*!< 0x00100000 */
+#define GPIO_CRL_MODE5_1 (0x2U << GPIO_CRL_MODE5_Pos) /*!< 0x00200000 */
+
+#define GPIO_CRL_MODE6_Pos (24U)
+#define GPIO_CRL_MODE6_Msk (0x3U << GPIO_CRL_MODE6_Pos) /*!< 0x03000000 */
+#define GPIO_CRL_MODE6 GPIO_CRL_MODE6_Msk /*!< MODE6[1:0] bits (Port x mode bits, pin 6) */
+#define GPIO_CRL_MODE6_0 (0x1U << GPIO_CRL_MODE6_Pos) /*!< 0x01000000 */
+#define GPIO_CRL_MODE6_1 (0x2U << GPIO_CRL_MODE6_Pos) /*!< 0x02000000 */
+
+#define GPIO_CRL_MODE7_Pos (28U)
+#define GPIO_CRL_MODE7_Msk (0x3U << GPIO_CRL_MODE7_Pos) /*!< 0x30000000 */
+#define GPIO_CRL_MODE7 GPIO_CRL_MODE7_Msk /*!< MODE7[1:0] bits (Port x mode bits, pin 7) */
+#define GPIO_CRL_MODE7_0 (0x1U << GPIO_CRL_MODE7_Pos) /*!< 0x10000000 */
+#define GPIO_CRL_MODE7_1 (0x2U << GPIO_CRL_MODE7_Pos) /*!< 0x20000000 */
+
+#define GPIO_CRL_CNF_Pos (2U)
+#define GPIO_CRL_CNF_Msk (0x33333333U << GPIO_CRL_CNF_Pos) /*!< 0xCCCCCCCC */
+#define GPIO_CRL_CNF GPIO_CRL_CNF_Msk /*!< Port x configuration bits */
+
+#define GPIO_CRL_CNF0_Pos (2U)
+#define GPIO_CRL_CNF0_Msk (0x3U << GPIO_CRL_CNF0_Pos) /*!< 0x0000000C */
+#define GPIO_CRL_CNF0 GPIO_CRL_CNF0_Msk /*!< CNF0[1:0] bits (Port x configuration bits, pin 0) */
+#define GPIO_CRL_CNF0_0 (0x1U << GPIO_CRL_CNF0_Pos) /*!< 0x00000004 */
+#define GPIO_CRL_CNF0_1 (0x2U << GPIO_CRL_CNF0_Pos) /*!< 0x00000008 */
+
+#define GPIO_CRL_CNF1_Pos (6U)
+#define GPIO_CRL_CNF1_Msk (0x3U << GPIO_CRL_CNF1_Pos) /*!< 0x000000C0 */
+#define GPIO_CRL_CNF1 GPIO_CRL_CNF1_Msk /*!< CNF1[1:0] bits (Port x configuration bits, pin 1) */
+#define GPIO_CRL_CNF1_0 (0x1U << GPIO_CRL_CNF1_Pos) /*!< 0x00000040 */
+#define GPIO_CRL_CNF1_1 (0x2U << GPIO_CRL_CNF1_Pos) /*!< 0x00000080 */
+
+#define GPIO_CRL_CNF2_Pos (10U)
+#define GPIO_CRL_CNF2_Msk (0x3U << GPIO_CRL_CNF2_Pos) /*!< 0x00000C00 */
+#define GPIO_CRL_CNF2 GPIO_CRL_CNF2_Msk /*!< CNF2[1:0] bits (Port x configuration bits, pin 2) */
+#define GPIO_CRL_CNF2_0 (0x1U << GPIO_CRL_CNF2_Pos) /*!< 0x00000400 */
+#define GPIO_CRL_CNF2_1 (0x2U << GPIO_CRL_CNF2_Pos) /*!< 0x00000800 */
+
+#define GPIO_CRL_CNF3_Pos (14U)
+#define GPIO_CRL_CNF3_Msk (0x3U << GPIO_CRL_CNF3_Pos) /*!< 0x0000C000 */
+#define GPIO_CRL_CNF3 GPIO_CRL_CNF3_Msk /*!< CNF3[1:0] bits (Port x configuration bits, pin 3) */
+#define GPIO_CRL_CNF3_0 (0x1U << GPIO_CRL_CNF3_Pos) /*!< 0x00004000 */
+#define GPIO_CRL_CNF3_1 (0x2U << GPIO_CRL_CNF3_Pos) /*!< 0x00008000 */
+
+#define GPIO_CRL_CNF4_Pos (18U)
+#define GPIO_CRL_CNF4_Msk (0x3U << GPIO_CRL_CNF4_Pos) /*!< 0x000C0000 */
+#define GPIO_CRL_CNF4 GPIO_CRL_CNF4_Msk /*!< CNF4[1:0] bits (Port x configuration bits, pin 4) */
+#define GPIO_CRL_CNF4_0 (0x1U << GPIO_CRL_CNF4_Pos) /*!< 0x00040000 */
+#define GPIO_CRL_CNF4_1 (0x2U << GPIO_CRL_CNF4_Pos) /*!< 0x00080000 */
+
+#define GPIO_CRL_CNF5_Pos (22U)
+#define GPIO_CRL_CNF5_Msk (0x3U << GPIO_CRL_CNF5_Pos) /*!< 0x00C00000 */
+#define GPIO_CRL_CNF5 GPIO_CRL_CNF5_Msk /*!< CNF5[1:0] bits (Port x configuration bits, pin 5) */
+#define GPIO_CRL_CNF5_0 (0x1U << GPIO_CRL_CNF5_Pos) /*!< 0x00400000 */
+#define GPIO_CRL_CNF5_1 (0x2U << GPIO_CRL_CNF5_Pos) /*!< 0x00800000 */
+
+#define GPIO_CRL_CNF6_Pos (26U)
+#define GPIO_CRL_CNF6_Msk (0x3U << GPIO_CRL_CNF6_Pos) /*!< 0x0C000000 */
+#define GPIO_CRL_CNF6 GPIO_CRL_CNF6_Msk /*!< CNF6[1:0] bits (Port x configuration bits, pin 6) */
+#define GPIO_CRL_CNF6_0 (0x1U << GPIO_CRL_CNF6_Pos) /*!< 0x04000000 */
+#define GPIO_CRL_CNF6_1 (0x2U << GPIO_CRL_CNF6_Pos) /*!< 0x08000000 */
+
+#define GPIO_CRL_CNF7_Pos (30U)
+#define GPIO_CRL_CNF7_Msk (0x3U << GPIO_CRL_CNF7_Pos) /*!< 0xC0000000 */
+#define GPIO_CRL_CNF7 GPIO_CRL_CNF7_Msk /*!< CNF7[1:0] bits (Port x configuration bits, pin 7) */
+#define GPIO_CRL_CNF7_0 (0x1U << GPIO_CRL_CNF7_Pos) /*!< 0x40000000 */
+#define GPIO_CRL_CNF7_1 (0x2U << GPIO_CRL_CNF7_Pos) /*!< 0x80000000 */
+
+/******************* Bit definition for GPIO_CRH register *******************/
+#define GPIO_CRH_MODE_Pos (0U)
+#define GPIO_CRH_MODE_Msk (0x33333333U << GPIO_CRH_MODE_Pos) /*!< 0x33333333 */
+#define GPIO_CRH_MODE GPIO_CRH_MODE_Msk /*!< Port x mode bits */
+
+#define GPIO_CRH_MODE8_Pos (0U)
+#define GPIO_CRH_MODE8_Msk (0x3U << GPIO_CRH_MODE8_Pos) /*!< 0x00000003 */
+#define GPIO_CRH_MODE8 GPIO_CRH_MODE8_Msk /*!< MODE8[1:0] bits (Port x mode bits, pin 8) */
+#define GPIO_CRH_MODE8_0 (0x1U << GPIO_CRH_MODE8_Pos) /*!< 0x00000001 */
+#define GPIO_CRH_MODE8_1 (0x2U << GPIO_CRH_MODE8_Pos) /*!< 0x00000002 */
+
+#define GPIO_CRH_MODE9_Pos (4U)
+#define GPIO_CRH_MODE9_Msk (0x3U << GPIO_CRH_MODE9_Pos) /*!< 0x00000030 */
+#define GPIO_CRH_MODE9 GPIO_CRH_MODE9_Msk /*!< MODE9[1:0] bits (Port x mode bits, pin 9) */
+#define GPIO_CRH_MODE9_0 (0x1U << GPIO_CRH_MODE9_Pos) /*!< 0x00000010 */
+#define GPIO_CRH_MODE9_1 (0x2U << GPIO_CRH_MODE9_Pos) /*!< 0x00000020 */
+
+#define GPIO_CRH_MODE10_Pos (8U)
+#define GPIO_CRH_MODE10_Msk (0x3U << GPIO_CRH_MODE10_Pos) /*!< 0x00000300 */
+#define GPIO_CRH_MODE10 GPIO_CRH_MODE10_Msk /*!< MODE10[1:0] bits (Port x mode bits, pin 10) */
+#define GPIO_CRH_MODE10_0 (0x1U << GPIO_CRH_MODE10_Pos) /*!< 0x00000100 */
+#define GPIO_CRH_MODE10_1 (0x2U << GPIO_CRH_MODE10_Pos) /*!< 0x00000200 */
+
+#define GPIO_CRH_MODE11_Pos (12U)
+#define GPIO_CRH_MODE11_Msk (0x3U << GPIO_CRH_MODE11_Pos) /*!< 0x00003000 */
+#define GPIO_CRH_MODE11 GPIO_CRH_MODE11_Msk /*!< MODE11[1:0] bits (Port x mode bits, pin 11) */
+#define GPIO_CRH_MODE11_0 (0x1U << GPIO_CRH_MODE11_Pos) /*!< 0x00001000 */
+#define GPIO_CRH_MODE11_1 (0x2U << GPIO_CRH_MODE11_Pos) /*!< 0x00002000 */
+
+#define GPIO_CRH_MODE12_Pos (16U)
+#define GPIO_CRH_MODE12_Msk (0x3U << GPIO_CRH_MODE12_Pos) /*!< 0x00030000 */
+#define GPIO_CRH_MODE12 GPIO_CRH_MODE12_Msk /*!< MODE12[1:0] bits (Port x mode bits, pin 12) */
+#define GPIO_CRH_MODE12_0 (0x1U << GPIO_CRH_MODE12_Pos) /*!< 0x00010000 */
+#define GPIO_CRH_MODE12_1 (0x2U << GPIO_CRH_MODE12_Pos) /*!< 0x00020000 */
+
+#define GPIO_CRH_MODE13_Pos (20U)
+#define GPIO_CRH_MODE13_Msk (0x3U << GPIO_CRH_MODE13_Pos) /*!< 0x00300000 */
+#define GPIO_CRH_MODE13 GPIO_CRH_MODE13_Msk /*!< MODE13[1:0] bits (Port x mode bits, pin 13) */
+#define GPIO_CRH_MODE13_0 (0x1U << GPIO_CRH_MODE13_Pos) /*!< 0x00100000 */
+#define GPIO_CRH_MODE13_1 (0x2U << GPIO_CRH_MODE13_Pos) /*!< 0x00200000 */
+
+#define GPIO_CRH_MODE14_Pos (24U)
+#define GPIO_CRH_MODE14_Msk (0x3U << GPIO_CRH_MODE14_Pos) /*!< 0x03000000 */
+#define GPIO_CRH_MODE14 GPIO_CRH_MODE14_Msk /*!< MODE14[1:0] bits (Port x mode bits, pin 14) */
+#define GPIO_CRH_MODE14_0 (0x1U << GPIO_CRH_MODE14_Pos) /*!< 0x01000000 */
+#define GPIO_CRH_MODE14_1 (0x2U << GPIO_CRH_MODE14_Pos) /*!< 0x02000000 */
+
+#define GPIO_CRH_MODE15_Pos (28U)
+#define GPIO_CRH_MODE15_Msk (0x3U << GPIO_CRH_MODE15_Pos) /*!< 0x30000000 */
+#define GPIO_CRH_MODE15 GPIO_CRH_MODE15_Msk /*!< MODE15[1:0] bits (Port x mode bits, pin 15) */
+#define GPIO_CRH_MODE15_0 (0x1U << GPIO_CRH_MODE15_Pos) /*!< 0x10000000 */
+#define GPIO_CRH_MODE15_1 (0x2U << GPIO_CRH_MODE15_Pos) /*!< 0x20000000 */
+
+#define GPIO_CRH_CNF_Pos (2U)
+#define GPIO_CRH_CNF_Msk (0x33333333U << GPIO_CRH_CNF_Pos) /*!< 0xCCCCCCCC */
+#define GPIO_CRH_CNF GPIO_CRH_CNF_Msk /*!< Port x configuration bits */
+
+#define GPIO_CRH_CNF8_Pos (2U)
+#define GPIO_CRH_CNF8_Msk (0x3U << GPIO_CRH_CNF8_Pos) /*!< 0x0000000C */
+#define GPIO_CRH_CNF8 GPIO_CRH_CNF8_Msk /*!< CNF8[1:0] bits (Port x configuration bits, pin 8) */
+#define GPIO_CRH_CNF8_0 (0x1U << GPIO_CRH_CNF8_Pos) /*!< 0x00000004 */
+#define GPIO_CRH_CNF8_1 (0x2U << GPIO_CRH_CNF8_Pos) /*!< 0x00000008 */
+
+#define GPIO_CRH_CNF9_Pos (6U)
+#define GPIO_CRH_CNF9_Msk (0x3U << GPIO_CRH_CNF9_Pos) /*!< 0x000000C0 */
+#define GPIO_CRH_CNF9 GPIO_CRH_CNF9_Msk /*!< CNF9[1:0] bits (Port x configuration bits, pin 9) */
+#define GPIO_CRH_CNF9_0 (0x1U << GPIO_CRH_CNF9_Pos) /*!< 0x00000040 */
+#define GPIO_CRH_CNF9_1 (0x2U << GPIO_CRH_CNF9_Pos) /*!< 0x00000080 */
+
+#define GPIO_CRH_CNF10_Pos (10U)
+#define GPIO_CRH_CNF10_Msk (0x3U << GPIO_CRH_CNF10_Pos) /*!< 0x00000C00 */
+#define GPIO_CRH_CNF10 GPIO_CRH_CNF10_Msk /*!< CNF10[1:0] bits (Port x configuration bits, pin 10) */
+#define GPIO_CRH_CNF10_0 (0x1U << GPIO_CRH_CNF10_Pos) /*!< 0x00000400 */
+#define GPIO_CRH_CNF10_1 (0x2U << GPIO_CRH_CNF10_Pos) /*!< 0x00000800 */
+
+#define GPIO_CRH_CNF11_Pos (14U)
+#define GPIO_CRH_CNF11_Msk (0x3U << GPIO_CRH_CNF11_Pos) /*!< 0x0000C000 */
+#define GPIO_CRH_CNF11 GPIO_CRH_CNF11_Msk /*!< CNF11[1:0] bits (Port x configuration bits, pin 11) */
+#define GPIO_CRH_CNF11_0 (0x1U << GPIO_CRH_CNF11_Pos) /*!< 0x00004000 */
+#define GPIO_CRH_CNF11_1 (0x2U << GPIO_CRH_CNF11_Pos) /*!< 0x00008000 */
+
+#define GPIO_CRH_CNF12_Pos (18U)
+#define GPIO_CRH_CNF12_Msk (0x3U << GPIO_CRH_CNF12_Pos) /*!< 0x000C0000 */
+#define GPIO_CRH_CNF12 GPIO_CRH_CNF12_Msk /*!< CNF12[1:0] bits (Port x configuration bits, pin 12) */
+#define GPIO_CRH_CNF12_0 (0x1U << GPIO_CRH_CNF12_Pos) /*!< 0x00040000 */
+#define GPIO_CRH_CNF12_1 (0x2U << GPIO_CRH_CNF12_Pos) /*!< 0x00080000 */
+
+#define GPIO_CRH_CNF13_Pos (22U)
+#define GPIO_CRH_CNF13_Msk (0x3U << GPIO_CRH_CNF13_Pos) /*!< 0x00C00000 */
+#define GPIO_CRH_CNF13 GPIO_CRH_CNF13_Msk /*!< CNF13[1:0] bits (Port x configuration bits, pin 13) */
+#define GPIO_CRH_CNF13_0 (0x1U << GPIO_CRH_CNF13_Pos) /*!< 0x00400000 */
+#define GPIO_CRH_CNF13_1 (0x2U << GPIO_CRH_CNF13_Pos) /*!< 0x00800000 */
+
+#define GPIO_CRH_CNF14_Pos (26U)
+#define GPIO_CRH_CNF14_Msk (0x3U << GPIO_CRH_CNF14_Pos) /*!< 0x0C000000 */
+#define GPIO_CRH_CNF14 GPIO_CRH_CNF14_Msk /*!< CNF14[1:0] bits (Port x configuration bits, pin 14) */
+#define GPIO_CRH_CNF14_0 (0x1U << GPIO_CRH_CNF14_Pos) /*!< 0x04000000 */
+#define GPIO_CRH_CNF14_1 (0x2U << GPIO_CRH_CNF14_Pos) /*!< 0x08000000 */
+
+#define GPIO_CRH_CNF15_Pos (30U)
+#define GPIO_CRH_CNF15_Msk (0x3U << GPIO_CRH_CNF15_Pos) /*!< 0xC0000000 */
+#define GPIO_CRH_CNF15 GPIO_CRH_CNF15_Msk /*!< CNF15[1:0] bits (Port x configuration bits, pin 15) */
+#define GPIO_CRH_CNF15_0 (0x1U << GPIO_CRH_CNF15_Pos) /*!< 0x40000000 */
+#define GPIO_CRH_CNF15_1 (0x2U << GPIO_CRH_CNF15_Pos) /*!< 0x80000000 */
+
+/*!<****************** Bit definition for GPIO_IDR register *******************/
+#define GPIO_IDR_IDR0_Pos (0U)
+#define GPIO_IDR_IDR0_Msk (0x1U << GPIO_IDR_IDR0_Pos) /*!< 0x00000001 */
+#define GPIO_IDR_IDR0 GPIO_IDR_IDR0_Msk /*!< Port input data, bit 0 */
+#define GPIO_IDR_IDR1_Pos (1U)
+#define GPIO_IDR_IDR1_Msk (0x1U << GPIO_IDR_IDR1_Pos) /*!< 0x00000002 */
+#define GPIO_IDR_IDR1 GPIO_IDR_IDR1_Msk /*!< Port input data, bit 1 */
+#define GPIO_IDR_IDR2_Pos (2U)
+#define GPIO_IDR_IDR2_Msk (0x1U << GPIO_IDR_IDR2_Pos) /*!< 0x00000004 */
+#define GPIO_IDR_IDR2 GPIO_IDR_IDR2_Msk /*!< Port input data, bit 2 */
+#define GPIO_IDR_IDR3_Pos (3U)
+#define GPIO_IDR_IDR3_Msk (0x1U << GPIO_IDR_IDR3_Pos) /*!< 0x00000008 */
+#define GPIO_IDR_IDR3 GPIO_IDR_IDR3_Msk /*!< Port input data, bit 3 */
+#define GPIO_IDR_IDR4_Pos (4U)
+#define GPIO_IDR_IDR4_Msk (0x1U << GPIO_IDR_IDR4_Pos) /*!< 0x00000010 */
+#define GPIO_IDR_IDR4 GPIO_IDR_IDR4_Msk /*!< Port input data, bit 4 */
+#define GPIO_IDR_IDR5_Pos (5U)
+#define GPIO_IDR_IDR5_Msk (0x1U << GPIO_IDR_IDR5_Pos) /*!< 0x00000020 */
+#define GPIO_IDR_IDR5 GPIO_IDR_IDR5_Msk /*!< Port input data, bit 5 */
+#define GPIO_IDR_IDR6_Pos (6U)
+#define GPIO_IDR_IDR6_Msk (0x1U << GPIO_IDR_IDR6_Pos) /*!< 0x00000040 */
+#define GPIO_IDR_IDR6 GPIO_IDR_IDR6_Msk /*!< Port input data, bit 6 */
+#define GPIO_IDR_IDR7_Pos (7U)
+#define GPIO_IDR_IDR7_Msk (0x1U << GPIO_IDR_IDR7_Pos) /*!< 0x00000080 */
+#define GPIO_IDR_IDR7 GPIO_IDR_IDR7_Msk /*!< Port input data, bit 7 */
+#define GPIO_IDR_IDR8_Pos (8U)
+#define GPIO_IDR_IDR8_Msk (0x1U << GPIO_IDR_IDR8_Pos) /*!< 0x00000100 */
+#define GPIO_IDR_IDR8 GPIO_IDR_IDR8_Msk /*!< Port input data, bit 8 */
+#define GPIO_IDR_IDR9_Pos (9U)
+#define GPIO_IDR_IDR9_Msk (0x1U << GPIO_IDR_IDR9_Pos) /*!< 0x00000200 */
+#define GPIO_IDR_IDR9 GPIO_IDR_IDR9_Msk /*!< Port input data, bit 9 */
+#define GPIO_IDR_IDR10_Pos (10U)
+#define GPIO_IDR_IDR10_Msk (0x1U << GPIO_IDR_IDR10_Pos) /*!< 0x00000400 */
+#define GPIO_IDR_IDR10 GPIO_IDR_IDR10_Msk /*!< Port input data, bit 10 */
+#define GPIO_IDR_IDR11_Pos (11U)
+#define GPIO_IDR_IDR11_Msk (0x1U << GPIO_IDR_IDR11_Pos) /*!< 0x00000800 */
+#define GPIO_IDR_IDR11 GPIO_IDR_IDR11_Msk /*!< Port input data, bit 11 */
+#define GPIO_IDR_IDR12_Pos (12U)
+#define GPIO_IDR_IDR12_Msk (0x1U << GPIO_IDR_IDR12_Pos) /*!< 0x00001000 */
+#define GPIO_IDR_IDR12 GPIO_IDR_IDR12_Msk /*!< Port input data, bit 12 */
+#define GPIO_IDR_IDR13_Pos (13U)
+#define GPIO_IDR_IDR13_Msk (0x1U << GPIO_IDR_IDR13_Pos) /*!< 0x00002000 */
+#define GPIO_IDR_IDR13 GPIO_IDR_IDR13_Msk /*!< Port input data, bit 13 */
+#define GPIO_IDR_IDR14_Pos (14U)
+#define GPIO_IDR_IDR14_Msk (0x1U << GPIO_IDR_IDR14_Pos) /*!< 0x00004000 */
+#define GPIO_IDR_IDR14 GPIO_IDR_IDR14_Msk /*!< Port input data, bit 14 */
+#define GPIO_IDR_IDR15_Pos (15U)
+#define GPIO_IDR_IDR15_Msk (0x1U << GPIO_IDR_IDR15_Pos) /*!< 0x00008000 */
+#define GPIO_IDR_IDR15 GPIO_IDR_IDR15_Msk /*!< Port input data, bit 15 */
+
+/******************* Bit definition for GPIO_ODR register *******************/
+#define GPIO_ODR_ODR0_Pos (0U)
+#define GPIO_ODR_ODR0_Msk (0x1U << GPIO_ODR_ODR0_Pos) /*!< 0x00000001 */
+#define GPIO_ODR_ODR0 GPIO_ODR_ODR0_Msk /*!< Port output data, bit 0 */
+#define GPIO_ODR_ODR1_Pos (1U)
+#define GPIO_ODR_ODR1_Msk (0x1U << GPIO_ODR_ODR1_Pos) /*!< 0x00000002 */
+#define GPIO_ODR_ODR1 GPIO_ODR_ODR1_Msk /*!< Port output data, bit 1 */
+#define GPIO_ODR_ODR2_Pos (2U)
+#define GPIO_ODR_ODR2_Msk (0x1U << GPIO_ODR_ODR2_Pos) /*!< 0x00000004 */
+#define GPIO_ODR_ODR2 GPIO_ODR_ODR2_Msk /*!< Port output data, bit 2 */
+#define GPIO_ODR_ODR3_Pos (3U)
+#define GPIO_ODR_ODR3_Msk (0x1U << GPIO_ODR_ODR3_Pos) /*!< 0x00000008 */
+#define GPIO_ODR_ODR3 GPIO_ODR_ODR3_Msk /*!< Port output data, bit 3 */
+#define GPIO_ODR_ODR4_Pos (4U)
+#define GPIO_ODR_ODR4_Msk (0x1U << GPIO_ODR_ODR4_Pos) /*!< 0x00000010 */
+#define GPIO_ODR_ODR4 GPIO_ODR_ODR4_Msk /*!< Port output data, bit 4 */
+#define GPIO_ODR_ODR5_Pos (5U)
+#define GPIO_ODR_ODR5_Msk (0x1U << GPIO_ODR_ODR5_Pos) /*!< 0x00000020 */
+#define GPIO_ODR_ODR5 GPIO_ODR_ODR5_Msk /*!< Port output data, bit 5 */
+#define GPIO_ODR_ODR6_Pos (6U)
+#define GPIO_ODR_ODR6_Msk (0x1U << GPIO_ODR_ODR6_Pos) /*!< 0x00000040 */
+#define GPIO_ODR_ODR6 GPIO_ODR_ODR6_Msk /*!< Port output data, bit 6 */
+#define GPIO_ODR_ODR7_Pos (7U)
+#define GPIO_ODR_ODR7_Msk (0x1U << GPIO_ODR_ODR7_Pos) /*!< 0x00000080 */
+#define GPIO_ODR_ODR7 GPIO_ODR_ODR7_Msk /*!< Port output data, bit 7 */
+#define GPIO_ODR_ODR8_Pos (8U)
+#define GPIO_ODR_ODR8_Msk (0x1U << GPIO_ODR_ODR8_Pos) /*!< 0x00000100 */
+#define GPIO_ODR_ODR8 GPIO_ODR_ODR8_Msk /*!< Port output data, bit 8 */
+#define GPIO_ODR_ODR9_Pos (9U)
+#define GPIO_ODR_ODR9_Msk (0x1U << GPIO_ODR_ODR9_Pos) /*!< 0x00000200 */
+#define GPIO_ODR_ODR9 GPIO_ODR_ODR9_Msk /*!< Port output data, bit 9 */
+#define GPIO_ODR_ODR10_Pos (10U)
+#define GPIO_ODR_ODR10_Msk (0x1U << GPIO_ODR_ODR10_Pos) /*!< 0x00000400 */
+#define GPIO_ODR_ODR10 GPIO_ODR_ODR10_Msk /*!< Port output data, bit 10 */
+#define GPIO_ODR_ODR11_Pos (11U)
+#define GPIO_ODR_ODR11_Msk (0x1U << GPIO_ODR_ODR11_Pos) /*!< 0x00000800 */
+#define GPIO_ODR_ODR11 GPIO_ODR_ODR11_Msk /*!< Port output data, bit 11 */
+#define GPIO_ODR_ODR12_Pos (12U)
+#define GPIO_ODR_ODR12_Msk (0x1U << GPIO_ODR_ODR12_Pos) /*!< 0x00001000 */
+#define GPIO_ODR_ODR12 GPIO_ODR_ODR12_Msk /*!< Port output data, bit 12 */
+#define GPIO_ODR_ODR13_Pos (13U)
+#define GPIO_ODR_ODR13_Msk (0x1U << GPIO_ODR_ODR13_Pos) /*!< 0x00002000 */
+#define GPIO_ODR_ODR13 GPIO_ODR_ODR13_Msk /*!< Port output data, bit 13 */
+#define GPIO_ODR_ODR14_Pos (14U)
+#define GPIO_ODR_ODR14_Msk (0x1U << GPIO_ODR_ODR14_Pos) /*!< 0x00004000 */
+#define GPIO_ODR_ODR14 GPIO_ODR_ODR14_Msk /*!< Port output data, bit 14 */
+#define GPIO_ODR_ODR15_Pos (15U)
+#define GPIO_ODR_ODR15_Msk (0x1U << GPIO_ODR_ODR15_Pos) /*!< 0x00008000 */
+#define GPIO_ODR_ODR15 GPIO_ODR_ODR15_Msk /*!< Port output data, bit 15 */
+
+/****************** Bit definition for GPIO_BSRR register *******************/
+#define GPIO_BSRR_BS0_Pos (0U)
+#define GPIO_BSRR_BS0_Msk (0x1U << GPIO_BSRR_BS0_Pos) /*!< 0x00000001 */
+#define GPIO_BSRR_BS0 GPIO_BSRR_BS0_Msk /*!< Port x Set bit 0 */
+#define GPIO_BSRR_BS1_Pos (1U)
+#define GPIO_BSRR_BS1_Msk (0x1U << GPIO_BSRR_BS1_Pos) /*!< 0x00000002 */
+#define GPIO_BSRR_BS1 GPIO_BSRR_BS1_Msk /*!< Port x Set bit 1 */
+#define GPIO_BSRR_BS2_Pos (2U)
+#define GPIO_BSRR_BS2_Msk (0x1U << GPIO_BSRR_BS2_Pos) /*!< 0x00000004 */
+#define GPIO_BSRR_BS2 GPIO_BSRR_BS2_Msk /*!< Port x Set bit 2 */
+#define GPIO_BSRR_BS3_Pos (3U)
+#define GPIO_BSRR_BS3_Msk (0x1U << GPIO_BSRR_BS3_Pos) /*!< 0x00000008 */
+#define GPIO_BSRR_BS3 GPIO_BSRR_BS3_Msk /*!< Port x Set bit 3 */
+#define GPIO_BSRR_BS4_Pos (4U)
+#define GPIO_BSRR_BS4_Msk (0x1U << GPIO_BSRR_BS4_Pos) /*!< 0x00000010 */
+#define GPIO_BSRR_BS4 GPIO_BSRR_BS4_Msk /*!< Port x Set bit 4 */
+#define GPIO_BSRR_BS5_Pos (5U)
+#define GPIO_BSRR_BS5_Msk (0x1U << GPIO_BSRR_BS5_Pos) /*!< 0x00000020 */
+#define GPIO_BSRR_BS5 GPIO_BSRR_BS5_Msk /*!< Port x Set bit 5 */
+#define GPIO_BSRR_BS6_Pos (6U)
+#define GPIO_BSRR_BS6_Msk (0x1U << GPIO_BSRR_BS6_Pos) /*!< 0x00000040 */
+#define GPIO_BSRR_BS6 GPIO_BSRR_BS6_Msk /*!< Port x Set bit 6 */
+#define GPIO_BSRR_BS7_Pos (7U)
+#define GPIO_BSRR_BS7_Msk (0x1U << GPIO_BSRR_BS7_Pos) /*!< 0x00000080 */
+#define GPIO_BSRR_BS7 GPIO_BSRR_BS7_Msk /*!< Port x Set bit 7 */
+#define GPIO_BSRR_BS8_Pos (8U)
+#define GPIO_BSRR_BS8_Msk (0x1U << GPIO_BSRR_BS8_Pos) /*!< 0x00000100 */
+#define GPIO_BSRR_BS8 GPIO_BSRR_BS8_Msk /*!< Port x Set bit 8 */
+#define GPIO_BSRR_BS9_Pos (9U)
+#define GPIO_BSRR_BS9_Msk (0x1U << GPIO_BSRR_BS9_Pos) /*!< 0x00000200 */
+#define GPIO_BSRR_BS9 GPIO_BSRR_BS9_Msk /*!< Port x Set bit 9 */
+#define GPIO_BSRR_BS10_Pos (10U)
+#define GPIO_BSRR_BS10_Msk (0x1U << GPIO_BSRR_BS10_Pos) /*!< 0x00000400 */
+#define GPIO_BSRR_BS10 GPIO_BSRR_BS10_Msk /*!< Port x Set bit 10 */
+#define GPIO_BSRR_BS11_Pos (11U)
+#define GPIO_BSRR_BS11_Msk (0x1U << GPIO_BSRR_BS11_Pos) /*!< 0x00000800 */
+#define GPIO_BSRR_BS11 GPIO_BSRR_BS11_Msk /*!< Port x Set bit 11 */
+#define GPIO_BSRR_BS12_Pos (12U)
+#define GPIO_BSRR_BS12_Msk (0x1U << GPIO_BSRR_BS12_Pos) /*!< 0x00001000 */
+#define GPIO_BSRR_BS12 GPIO_BSRR_BS12_Msk /*!< Port x Set bit 12 */
+#define GPIO_BSRR_BS13_Pos (13U)
+#define GPIO_BSRR_BS13_Msk (0x1U << GPIO_BSRR_BS13_Pos) /*!< 0x00002000 */
+#define GPIO_BSRR_BS13 GPIO_BSRR_BS13_Msk /*!< Port x Set bit 13 */
+#define GPIO_BSRR_BS14_Pos (14U)
+#define GPIO_BSRR_BS14_Msk (0x1U << GPIO_BSRR_BS14_Pos) /*!< 0x00004000 */
+#define GPIO_BSRR_BS14 GPIO_BSRR_BS14_Msk /*!< Port x Set bit 14 */
+#define GPIO_BSRR_BS15_Pos (15U)
+#define GPIO_BSRR_BS15_Msk (0x1U << GPIO_BSRR_BS15_Pos) /*!< 0x00008000 */
+#define GPIO_BSRR_BS15 GPIO_BSRR_BS15_Msk /*!< Port x Set bit 15 */
+
+#define GPIO_BSRR_BR0_Pos (16U)
+#define GPIO_BSRR_BR0_Msk (0x1U << GPIO_BSRR_BR0_Pos) /*!< 0x00010000 */
+#define GPIO_BSRR_BR0 GPIO_BSRR_BR0_Msk /*!< Port x Reset bit 0 */
+#define GPIO_BSRR_BR1_Pos (17U)
+#define GPIO_BSRR_BR1_Msk (0x1U << GPIO_BSRR_BR1_Pos) /*!< 0x00020000 */
+#define GPIO_BSRR_BR1 GPIO_BSRR_BR1_Msk /*!< Port x Reset bit 1 */
+#define GPIO_BSRR_BR2_Pos (18U)
+#define GPIO_BSRR_BR2_Msk (0x1U << GPIO_BSRR_BR2_Pos) /*!< 0x00040000 */
+#define GPIO_BSRR_BR2 GPIO_BSRR_BR2_Msk /*!< Port x Reset bit 2 */
+#define GPIO_BSRR_BR3_Pos (19U)
+#define GPIO_BSRR_BR3_Msk (0x1U << GPIO_BSRR_BR3_Pos) /*!< 0x00080000 */
+#define GPIO_BSRR_BR3 GPIO_BSRR_BR3_Msk /*!< Port x Reset bit 3 */
+#define GPIO_BSRR_BR4_Pos (20U)
+#define GPIO_BSRR_BR4_Msk (0x1U << GPIO_BSRR_BR4_Pos) /*!< 0x00100000 */
+#define GPIO_BSRR_BR4 GPIO_BSRR_BR4_Msk /*!< Port x Reset bit 4 */
+#define GPIO_BSRR_BR5_Pos (21U)
+#define GPIO_BSRR_BR5_Msk (0x1U << GPIO_BSRR_BR5_Pos) /*!< 0x00200000 */
+#define GPIO_BSRR_BR5 GPIO_BSRR_BR5_Msk /*!< Port x Reset bit 5 */
+#define GPIO_BSRR_BR6_Pos (22U)
+#define GPIO_BSRR_BR6_Msk (0x1U << GPIO_BSRR_BR6_Pos) /*!< 0x00400000 */
+#define GPIO_BSRR_BR6 GPIO_BSRR_BR6_Msk /*!< Port x Reset bit 6 */
+#define GPIO_BSRR_BR7_Pos (23U)
+#define GPIO_BSRR_BR7_Msk (0x1U << GPIO_BSRR_BR7_Pos) /*!< 0x00800000 */
+#define GPIO_BSRR_BR7 GPIO_BSRR_BR7_Msk /*!< Port x Reset bit 7 */
+#define GPIO_BSRR_BR8_Pos (24U)
+#define GPIO_BSRR_BR8_Msk (0x1U << GPIO_BSRR_BR8_Pos) /*!< 0x01000000 */
+#define GPIO_BSRR_BR8 GPIO_BSRR_BR8_Msk /*!< Port x Reset bit 8 */
+#define GPIO_BSRR_BR9_Pos (25U)
+#define GPIO_BSRR_BR9_Msk (0x1U << GPIO_BSRR_BR9_Pos) /*!< 0x02000000 */
+#define GPIO_BSRR_BR9 GPIO_BSRR_BR9_Msk /*!< Port x Reset bit 9 */
+#define GPIO_BSRR_BR10_Pos (26U)
+#define GPIO_BSRR_BR10_Msk (0x1U << GPIO_BSRR_BR10_Pos) /*!< 0x04000000 */
+#define GPIO_BSRR_BR10 GPIO_BSRR_BR10_Msk /*!< Port x Reset bit 10 */
+#define GPIO_BSRR_BR11_Pos (27U)
+#define GPIO_BSRR_BR11_Msk (0x1U << GPIO_BSRR_BR11_Pos) /*!< 0x08000000 */
+#define GPIO_BSRR_BR11 GPIO_BSRR_BR11_Msk /*!< Port x Reset bit 11 */
+#define GPIO_BSRR_BR12_Pos (28U)
+#define GPIO_BSRR_BR12_Msk (0x1U << GPIO_BSRR_BR12_Pos) /*!< 0x10000000 */
+#define GPIO_BSRR_BR12 GPIO_BSRR_BR12_Msk /*!< Port x Reset bit 12 */
+#define GPIO_BSRR_BR13_Pos (29U)
+#define GPIO_BSRR_BR13_Msk (0x1U << GPIO_BSRR_BR13_Pos) /*!< 0x20000000 */
+#define GPIO_BSRR_BR13 GPIO_BSRR_BR13_Msk /*!< Port x Reset bit 13 */
+#define GPIO_BSRR_BR14_Pos (30U)
+#define GPIO_BSRR_BR14_Msk (0x1U << GPIO_BSRR_BR14_Pos) /*!< 0x40000000 */
+#define GPIO_BSRR_BR14 GPIO_BSRR_BR14_Msk /*!< Port x Reset bit 14 */
+#define GPIO_BSRR_BR15_Pos (31U)
+#define GPIO_BSRR_BR15_Msk (0x1U << GPIO_BSRR_BR15_Pos) /*!< 0x80000000 */
+#define GPIO_BSRR_BR15 GPIO_BSRR_BR15_Msk /*!< Port x Reset bit 15 */
+
+/******************* Bit definition for GPIO_BRR register *******************/
+#define GPIO_BRR_BR0_Pos (0U)
+#define GPIO_BRR_BR0_Msk (0x1U << GPIO_BRR_BR0_Pos) /*!< 0x00000001 */
+#define GPIO_BRR_BR0 GPIO_BRR_BR0_Msk /*!< Port x Reset bit 0 */
+#define GPIO_BRR_BR1_Pos (1U)
+#define GPIO_BRR_BR1_Msk (0x1U << GPIO_BRR_BR1_Pos) /*!< 0x00000002 */
+#define GPIO_BRR_BR1 GPIO_BRR_BR1_Msk /*!< Port x Reset bit 1 */
+#define GPIO_BRR_BR2_Pos (2U)
+#define GPIO_BRR_BR2_Msk (0x1U << GPIO_BRR_BR2_Pos) /*!< 0x00000004 */
+#define GPIO_BRR_BR2 GPIO_BRR_BR2_Msk /*!< Port x Reset bit 2 */
+#define GPIO_BRR_BR3_Pos (3U)
+#define GPIO_BRR_BR3_Msk (0x1U << GPIO_BRR_BR3_Pos) /*!< 0x00000008 */
+#define GPIO_BRR_BR3 GPIO_BRR_BR3_Msk /*!< Port x Reset bit 3 */
+#define GPIO_BRR_BR4_Pos (4U)
+#define GPIO_BRR_BR4_Msk (0x1U << GPIO_BRR_BR4_Pos) /*!< 0x00000010 */
+#define GPIO_BRR_BR4 GPIO_BRR_BR4_Msk /*!< Port x Reset bit 4 */
+#define GPIO_BRR_BR5_Pos (5U)
+#define GPIO_BRR_BR5_Msk (0x1U << GPIO_BRR_BR5_Pos) /*!< 0x00000020 */
+#define GPIO_BRR_BR5 GPIO_BRR_BR5_Msk /*!< Port x Reset bit 5 */
+#define GPIO_BRR_BR6_Pos (6U)
+#define GPIO_BRR_BR6_Msk (0x1U << GPIO_BRR_BR6_Pos) /*!< 0x00000040 */
+#define GPIO_BRR_BR6 GPIO_BRR_BR6_Msk /*!< Port x Reset bit 6 */
+#define GPIO_BRR_BR7_Pos (7U)
+#define GPIO_BRR_BR7_Msk (0x1U << GPIO_BRR_BR7_Pos) /*!< 0x00000080 */
+#define GPIO_BRR_BR7 GPIO_BRR_BR7_Msk /*!< Port x Reset bit 7 */
+#define GPIO_BRR_BR8_Pos (8U)
+#define GPIO_BRR_BR8_Msk (0x1U << GPIO_BRR_BR8_Pos) /*!< 0x00000100 */
+#define GPIO_BRR_BR8 GPIO_BRR_BR8_Msk /*!< Port x Reset bit 8 */
+#define GPIO_BRR_BR9_Pos (9U)
+#define GPIO_BRR_BR9_Msk (0x1U << GPIO_BRR_BR9_Pos) /*!< 0x00000200 */
+#define GPIO_BRR_BR9 GPIO_BRR_BR9_Msk /*!< Port x Reset bit 9 */
+#define GPIO_BRR_BR10_Pos (10U)
+#define GPIO_BRR_BR10_Msk (0x1U << GPIO_BRR_BR10_Pos) /*!< 0x00000400 */
+#define GPIO_BRR_BR10 GPIO_BRR_BR10_Msk /*!< Port x Reset bit 10 */
+#define GPIO_BRR_BR11_Pos (11U)
+#define GPIO_BRR_BR11_Msk (0x1U << GPIO_BRR_BR11_Pos) /*!< 0x00000800 */
+#define GPIO_BRR_BR11 GPIO_BRR_BR11_Msk /*!< Port x Reset bit 11 */
+#define GPIO_BRR_BR12_Pos (12U)
+#define GPIO_BRR_BR12_Msk (0x1U << GPIO_BRR_BR12_Pos) /*!< 0x00001000 */
+#define GPIO_BRR_BR12 GPIO_BRR_BR12_Msk /*!< Port x Reset bit 12 */
+#define GPIO_BRR_BR13_Pos (13U)
+#define GPIO_BRR_BR13_Msk (0x1U << GPIO_BRR_BR13_Pos) /*!< 0x00002000 */
+#define GPIO_BRR_BR13 GPIO_BRR_BR13_Msk /*!< Port x Reset bit 13 */
+#define GPIO_BRR_BR14_Pos (14U)
+#define GPIO_BRR_BR14_Msk (0x1U << GPIO_BRR_BR14_Pos) /*!< 0x00004000 */
+#define GPIO_BRR_BR14 GPIO_BRR_BR14_Msk /*!< Port x Reset bit 14 */
+#define GPIO_BRR_BR15_Pos (15U)
+#define GPIO_BRR_BR15_Msk (0x1U << GPIO_BRR_BR15_Pos) /*!< 0x00008000 */
+#define GPIO_BRR_BR15 GPIO_BRR_BR15_Msk /*!< Port x Reset bit 15 */
+
+/****************** Bit definition for GPIO_LCKR register *******************/
+#define GPIO_LCKR_LCK0_Pos (0U)
+#define GPIO_LCKR_LCK0_Msk (0x1U << GPIO_LCKR_LCK0_Pos) /*!< 0x00000001 */
+#define GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk /*!< Port x Lock bit 0 */
+#define GPIO_LCKR_LCK1_Pos (1U)
+#define GPIO_LCKR_LCK1_Msk (0x1U << GPIO_LCKR_LCK1_Pos) /*!< 0x00000002 */
+#define GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk /*!< Port x Lock bit 1 */
+#define GPIO_LCKR_LCK2_Pos (2U)
+#define GPIO_LCKR_LCK2_Msk (0x1U << GPIO_LCKR_LCK2_Pos) /*!< 0x00000004 */
+#define GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk /*!< Port x Lock bit 2 */
+#define GPIO_LCKR_LCK3_Pos (3U)
+#define GPIO_LCKR_LCK3_Msk (0x1U << GPIO_LCKR_LCK3_Pos) /*!< 0x00000008 */
+#define GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk /*!< Port x Lock bit 3 */
+#define GPIO_LCKR_LCK4_Pos (4U)
+#define GPIO_LCKR_LCK4_Msk (0x1U << GPIO_LCKR_LCK4_Pos) /*!< 0x00000010 */
+#define GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk /*!< Port x Lock bit 4 */
+#define GPIO_LCKR_LCK5_Pos (5U)
+#define GPIO_LCKR_LCK5_Msk (0x1U << GPIO_LCKR_LCK5_Pos) /*!< 0x00000020 */
+#define GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk /*!< Port x Lock bit 5 */
+#define GPIO_LCKR_LCK6_Pos (6U)
+#define GPIO_LCKR_LCK6_Msk (0x1U << GPIO_LCKR_LCK6_Pos) /*!< 0x00000040 */
+#define GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk /*!< Port x Lock bit 6 */
+#define GPIO_LCKR_LCK7_Pos (7U)
+#define GPIO_LCKR_LCK7_Msk (0x1U << GPIO_LCKR_LCK7_Pos) /*!< 0x00000080 */
+#define GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk /*!< Port x Lock bit 7 */
+#define GPIO_LCKR_LCK8_Pos (8U)
+#define GPIO_LCKR_LCK8_Msk (0x1U << GPIO_LCKR_LCK8_Pos) /*!< 0x00000100 */
+#define GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk /*!< Port x Lock bit 8 */
+#define GPIO_LCKR_LCK9_Pos (9U)
+#define GPIO_LCKR_LCK9_Msk (0x1U << GPIO_LCKR_LCK9_Pos) /*!< 0x00000200 */
+#define GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk /*!< Port x Lock bit 9 */
+#define GPIO_LCKR_LCK10_Pos (10U)
+#define GPIO_LCKR_LCK10_Msk (0x1U << GPIO_LCKR_LCK10_Pos) /*!< 0x00000400 */
+#define GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk /*!< Port x Lock bit 10 */
+#define GPIO_LCKR_LCK11_Pos (11U)
+#define GPIO_LCKR_LCK11_Msk (0x1U << GPIO_LCKR_LCK11_Pos) /*!< 0x00000800 */
+#define GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk /*!< Port x Lock bit 11 */
+#define GPIO_LCKR_LCK12_Pos (12U)
+#define GPIO_LCKR_LCK12_Msk (0x1U << GPIO_LCKR_LCK12_Pos) /*!< 0x00001000 */
+#define GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk /*!< Port x Lock bit 12 */
+#define GPIO_LCKR_LCK13_Pos (13U)
+#define GPIO_LCKR_LCK13_Msk (0x1U << GPIO_LCKR_LCK13_Pos) /*!< 0x00002000 */
+#define GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk /*!< Port x Lock bit 13 */
+#define GPIO_LCKR_LCK14_Pos (14U)
+#define GPIO_LCKR_LCK14_Msk (0x1U << GPIO_LCKR_LCK14_Pos) /*!< 0x00004000 */
+#define GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk /*!< Port x Lock bit 14 */
+#define GPIO_LCKR_LCK15_Pos (15U)
+#define GPIO_LCKR_LCK15_Msk (0x1U << GPIO_LCKR_LCK15_Pos) /*!< 0x00008000 */
+#define GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk /*!< Port x Lock bit 15 */
+#define GPIO_LCKR_LCKK_Pos (16U)
+#define GPIO_LCKR_LCKK_Msk (0x1U << GPIO_LCKR_LCKK_Pos) /*!< 0x00010000 */
+#define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk /*!< Lock key */
+
+/*----------------------------------------------------------------------------*/
+
+/****************** Bit definition for AFIO_EVCR register *******************/
+#define AFIO_EVCR_PIN_Pos (0U)
+#define AFIO_EVCR_PIN_Msk (0xFU << AFIO_EVCR_PIN_Pos) /*!< 0x0000000F */
+#define AFIO_EVCR_PIN AFIO_EVCR_PIN_Msk /*!< PIN[3:0] bits (Pin selection) */
+#define AFIO_EVCR_PIN_0 (0x1U << AFIO_EVCR_PIN_Pos) /*!< 0x00000001 */
+#define AFIO_EVCR_PIN_1 (0x2U << AFIO_EVCR_PIN_Pos) /*!< 0x00000002 */
+#define AFIO_EVCR_PIN_2 (0x4U << AFIO_EVCR_PIN_Pos) /*!< 0x00000004 */
+#define AFIO_EVCR_PIN_3 (0x8U << AFIO_EVCR_PIN_Pos) /*!< 0x00000008 */
+
+/*!< PIN configuration */
+#define AFIO_EVCR_PIN_PX0 ((uint32_t)0x00000000) /*!< Pin 0 selected */
+#define AFIO_EVCR_PIN_PX1_Pos (0U)
+#define AFIO_EVCR_PIN_PX1_Msk (0x1U << AFIO_EVCR_PIN_PX1_Pos) /*!< 0x00000001 */
+#define AFIO_EVCR_PIN_PX1 AFIO_EVCR_PIN_PX1_Msk /*!< Pin 1 selected */
+#define AFIO_EVCR_PIN_PX2_Pos (1U)
+#define AFIO_EVCR_PIN_PX2_Msk (0x1U << AFIO_EVCR_PIN_PX2_Pos) /*!< 0x00000002 */
+#define AFIO_EVCR_PIN_PX2 AFIO_EVCR_PIN_PX2_Msk /*!< Pin 2 selected */
+#define AFIO_EVCR_PIN_PX3_Pos (0U)
+#define AFIO_EVCR_PIN_PX3_Msk (0x3U << AFIO_EVCR_PIN_PX3_Pos) /*!< 0x00000003 */
+#define AFIO_EVCR_PIN_PX3 AFIO_EVCR_PIN_PX3_Msk /*!< Pin 3 selected */
+#define AFIO_EVCR_PIN_PX4_Pos (2U)
+#define AFIO_EVCR_PIN_PX4_Msk (0x1U << AFIO_EVCR_PIN_PX4_Pos) /*!< 0x00000004 */
+#define AFIO_EVCR_PIN_PX4 AFIO_EVCR_PIN_PX4_Msk /*!< Pin 4 selected */
+#define AFIO_EVCR_PIN_PX5_Pos (0U)
+#define AFIO_EVCR_PIN_PX5_Msk (0x5U << AFIO_EVCR_PIN_PX5_Pos) /*!< 0x00000005 */
+#define AFIO_EVCR_PIN_PX5 AFIO_EVCR_PIN_PX5_Msk /*!< Pin 5 selected */
+#define AFIO_EVCR_PIN_PX6_Pos (1U)
+#define AFIO_EVCR_PIN_PX6_Msk (0x3U << AFIO_EVCR_PIN_PX6_Pos) /*!< 0x00000006 */
+#define AFIO_EVCR_PIN_PX6 AFIO_EVCR_PIN_PX6_Msk /*!< Pin 6 selected */
+#define AFIO_EVCR_PIN_PX7_Pos (0U)
+#define AFIO_EVCR_PIN_PX7_Msk (0x7U << AFIO_EVCR_PIN_PX7_Pos) /*!< 0x00000007 */
+#define AFIO_EVCR_PIN_PX7 AFIO_EVCR_PIN_PX7_Msk /*!< Pin 7 selected */
+#define AFIO_EVCR_PIN_PX8_Pos (3U)
+#define AFIO_EVCR_PIN_PX8_Msk (0x1U << AFIO_EVCR_PIN_PX8_Pos) /*!< 0x00000008 */
+#define AFIO_EVCR_PIN_PX8 AFIO_EVCR_PIN_PX8_Msk /*!< Pin 8 selected */
+#define AFIO_EVCR_PIN_PX9_Pos (0U)
+#define AFIO_EVCR_PIN_PX9_Msk (0x9U << AFIO_EVCR_PIN_PX9_Pos) /*!< 0x00000009 */
+#define AFIO_EVCR_PIN_PX9 AFIO_EVCR_PIN_PX9_Msk /*!< Pin 9 selected */
+#define AFIO_EVCR_PIN_PX10_Pos (1U)
+#define AFIO_EVCR_PIN_PX10_Msk (0x5U << AFIO_EVCR_PIN_PX10_Pos) /*!< 0x0000000A */
+#define AFIO_EVCR_PIN_PX10 AFIO_EVCR_PIN_PX10_Msk /*!< Pin 10 selected */
+#define AFIO_EVCR_PIN_PX11_Pos (0U)
+#define AFIO_EVCR_PIN_PX11_Msk (0xBU << AFIO_EVCR_PIN_PX11_Pos) /*!< 0x0000000B */
+#define AFIO_EVCR_PIN_PX11 AFIO_EVCR_PIN_PX11_Msk /*!< Pin 11 selected */
+#define AFIO_EVCR_PIN_PX12_Pos (2U)
+#define AFIO_EVCR_PIN_PX12_Msk (0x3U << AFIO_EVCR_PIN_PX12_Pos) /*!< 0x0000000C */
+#define AFIO_EVCR_PIN_PX12 AFIO_EVCR_PIN_PX12_Msk /*!< Pin 12 selected */
+#define AFIO_EVCR_PIN_PX13_Pos (0U)
+#define AFIO_EVCR_PIN_PX13_Msk (0xDU << AFIO_EVCR_PIN_PX13_Pos) /*!< 0x0000000D */
+#define AFIO_EVCR_PIN_PX13 AFIO_EVCR_PIN_PX13_Msk /*!< Pin 13 selected */
+#define AFIO_EVCR_PIN_PX14_Pos (1U)
+#define AFIO_EVCR_PIN_PX14_Msk (0x7U << AFIO_EVCR_PIN_PX14_Pos) /*!< 0x0000000E */
+#define AFIO_EVCR_PIN_PX14 AFIO_EVCR_PIN_PX14_Msk /*!< Pin 14 selected */
+#define AFIO_EVCR_PIN_PX15_Pos (0U)
+#define AFIO_EVCR_PIN_PX15_Msk (0xFU << AFIO_EVCR_PIN_PX15_Pos) /*!< 0x0000000F */
+#define AFIO_EVCR_PIN_PX15 AFIO_EVCR_PIN_PX15_Msk /*!< Pin 15 selected */
+
+#define AFIO_EVCR_PORT_Pos (4U)
+#define AFIO_EVCR_PORT_Msk (0x7U << AFIO_EVCR_PORT_Pos) /*!< 0x00000070 */
+#define AFIO_EVCR_PORT AFIO_EVCR_PORT_Msk /*!< PORT[2:0] bits (Port selection) */
+#define AFIO_EVCR_PORT_0 (0x1U << AFIO_EVCR_PORT_Pos) /*!< 0x00000010 */
+#define AFIO_EVCR_PORT_1 (0x2U << AFIO_EVCR_PORT_Pos) /*!< 0x00000020 */
+#define AFIO_EVCR_PORT_2 (0x4U << AFIO_EVCR_PORT_Pos) /*!< 0x00000040 */
+
+/*!< PORT configuration */
+#define AFIO_EVCR_PORT_PA ((uint32_t)0x00000000) /*!< Port A selected */
+#define AFIO_EVCR_PORT_PB_Pos (4U)
+#define AFIO_EVCR_PORT_PB_Msk (0x1U << AFIO_EVCR_PORT_PB_Pos) /*!< 0x00000010 */
+#define AFIO_EVCR_PORT_PB AFIO_EVCR_PORT_PB_Msk /*!< Port B selected */
+#define AFIO_EVCR_PORT_PC_Pos (5U)
+#define AFIO_EVCR_PORT_PC_Msk (0x1U << AFIO_EVCR_PORT_PC_Pos) /*!< 0x00000020 */
+#define AFIO_EVCR_PORT_PC AFIO_EVCR_PORT_PC_Msk /*!< Port C selected */
+#define AFIO_EVCR_PORT_PD_Pos (4U)
+#define AFIO_EVCR_PORT_PD_Msk (0x3U << AFIO_EVCR_PORT_PD_Pos) /*!< 0x00000030 */
+#define AFIO_EVCR_PORT_PD AFIO_EVCR_PORT_PD_Msk /*!< Port D selected */
+#define AFIO_EVCR_PORT_PE_Pos (6U)
+#define AFIO_EVCR_PORT_PE_Msk (0x1U << AFIO_EVCR_PORT_PE_Pos) /*!< 0x00000040 */
+#define AFIO_EVCR_PORT_PE AFIO_EVCR_PORT_PE_Msk /*!< Port E selected */
+
+#define AFIO_EVCR_EVOE_Pos (7U)
+#define AFIO_EVCR_EVOE_Msk (0x1U << AFIO_EVCR_EVOE_Pos) /*!< 0x00000080 */
+#define AFIO_EVCR_EVOE AFIO_EVCR_EVOE_Msk /*!< Event Output Enable */
+
+/****************** Bit definition for AFIO_MAPR register *******************/
+#define AFIO_MAPR_SPI1_REMAP_Pos (0U)
+#define AFIO_MAPR_SPI1_REMAP_Msk (0x1U << AFIO_MAPR_SPI1_REMAP_Pos) /*!< 0x00000001 */
+#define AFIO_MAPR_SPI1_REMAP AFIO_MAPR_SPI1_REMAP_Msk /*!< SPI1 remapping */
+#define AFIO_MAPR_I2C1_REMAP_Pos (1U)
+#define AFIO_MAPR_I2C1_REMAP_Msk (0x1U << AFIO_MAPR_I2C1_REMAP_Pos) /*!< 0x00000002 */
+#define AFIO_MAPR_I2C1_REMAP AFIO_MAPR_I2C1_REMAP_Msk /*!< I2C1 remapping */
+#define AFIO_MAPR_USART1_REMAP_Pos (2U)
+#define AFIO_MAPR_USART1_REMAP_Msk (0x1U << AFIO_MAPR_USART1_REMAP_Pos) /*!< 0x00000004 */
+#define AFIO_MAPR_USART1_REMAP AFIO_MAPR_USART1_REMAP_Msk /*!< USART1 remapping */
+#define AFIO_MAPR_USART2_REMAP_Pos (3U)
+#define AFIO_MAPR_USART2_REMAP_Msk (0x1U << AFIO_MAPR_USART2_REMAP_Pos) /*!< 0x00000008 */
+#define AFIO_MAPR_USART2_REMAP AFIO_MAPR_USART2_REMAP_Msk /*!< USART2 remapping */
+
+#define AFIO_MAPR_USART3_REMAP_Pos (4U)
+#define AFIO_MAPR_USART3_REMAP_Msk (0x3U << AFIO_MAPR_USART3_REMAP_Pos) /*!< 0x00000030 */
+#define AFIO_MAPR_USART3_REMAP AFIO_MAPR_USART3_REMAP_Msk /*!< USART3_REMAP[1:0] bits (USART3 remapping) */
+#define AFIO_MAPR_USART3_REMAP_0 (0x1U << AFIO_MAPR_USART3_REMAP_Pos) /*!< 0x00000010 */
+#define AFIO_MAPR_USART3_REMAP_1 (0x2U << AFIO_MAPR_USART3_REMAP_Pos) /*!< 0x00000020 */
+
+/* USART3_REMAP configuration */
+#define AFIO_MAPR_USART3_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14) */
+#define AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Pos (4U)
+#define AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Msk (0x1U << AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Pos) /*!< 0x00000010 */
+#define AFIO_MAPR_USART3_REMAP_PARTIALREMAP AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Msk /*!< Partial remap (TX/PC10, RX/PC11, CK/PC12, CTS/PB13, RTS/PB14) */
+#define AFIO_MAPR_USART3_REMAP_FULLREMAP_Pos (4U)
+#define AFIO_MAPR_USART3_REMAP_FULLREMAP_Msk (0x3U << AFIO_MAPR_USART3_REMAP_FULLREMAP_Pos) /*!< 0x00000030 */
+#define AFIO_MAPR_USART3_REMAP_FULLREMAP AFIO_MAPR_USART3_REMAP_FULLREMAP_Msk /*!< Full remap (TX/PD8, RX/PD9, CK/PD10, CTS/PD11, RTS/PD12) */
+
+#define AFIO_MAPR_TIM1_REMAP_Pos (6U)
+#define AFIO_MAPR_TIM1_REMAP_Msk (0x3U << AFIO_MAPR_TIM1_REMAP_Pos) /*!< 0x000000C0 */
+#define AFIO_MAPR_TIM1_REMAP AFIO_MAPR_TIM1_REMAP_Msk /*!< TIM1_REMAP[1:0] bits (TIM1 remapping) */
+#define AFIO_MAPR_TIM1_REMAP_0 (0x1U << AFIO_MAPR_TIM1_REMAP_Pos) /*!< 0x00000040 */
+#define AFIO_MAPR_TIM1_REMAP_1 (0x2U << AFIO_MAPR_TIM1_REMAP_Pos) /*!< 0x00000080 */
+
+/*!< TIM1_REMAP configuration */
+#define AFIO_MAPR_TIM1_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15) */
+#define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Pos (6U)
+#define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Msk (0x1U << AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Pos) /*!< 0x00000040 */
+#define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Msk /*!< Partial remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PA6, CH1N/PA7, CH2N/PB0, CH3N/PB1) */
+#define AFIO_MAPR_TIM1_REMAP_FULLREMAP_Pos (6U)
+#define AFIO_MAPR_TIM1_REMAP_FULLREMAP_Msk (0x3U << AFIO_MAPR_TIM1_REMAP_FULLREMAP_Pos) /*!< 0x000000C0 */
+#define AFIO_MAPR_TIM1_REMAP_FULLREMAP AFIO_MAPR_TIM1_REMAP_FULLREMAP_Msk /*!< Full remap (ETR/PE7, CH1/PE9, CH2/PE11, CH3/PE13, CH4/PE14, BKIN/PE15, CH1N/PE8, CH2N/PE10, CH3N/PE12) */
+
+#define AFIO_MAPR_TIM2_REMAP_Pos (8U)
+#define AFIO_MAPR_TIM2_REMAP_Msk (0x3U << AFIO_MAPR_TIM2_REMAP_Pos) /*!< 0x00000300 */
+#define AFIO_MAPR_TIM2_REMAP AFIO_MAPR_TIM2_REMAP_Msk /*!< TIM2_REMAP[1:0] bits (TIM2 remapping) */
+#define AFIO_MAPR_TIM2_REMAP_0 (0x1U << AFIO_MAPR_TIM2_REMAP_Pos) /*!< 0x00000100 */
+#define AFIO_MAPR_TIM2_REMAP_1 (0x2U << AFIO_MAPR_TIM2_REMAP_Pos) /*!< 0x00000200 */
+
+/*!< TIM2_REMAP configuration */
+#define AFIO_MAPR_TIM2_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3) */
+#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Pos (8U)
+#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Msk (0x1U << AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Pos) /*!< 0x00000100 */
+#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1 AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Msk /*!< Partial remap (CH1/ETR/PA15, CH2/PB3, CH3/PA2, CH4/PA3) */
+#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2_Pos (9U)
+#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2_Msk (0x1U << AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2_Pos) /*!< 0x00000200 */
+#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2 AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2_Msk /*!< Partial remap (CH1/ETR/PA0, CH2/PA1, CH3/PB10, CH4/PB11) */
+#define AFIO_MAPR_TIM2_REMAP_FULLREMAP_Pos (8U)
+#define AFIO_MAPR_TIM2_REMAP_FULLREMAP_Msk (0x3U << AFIO_MAPR_TIM2_REMAP_FULLREMAP_Pos) /*!< 0x00000300 */
+#define AFIO_MAPR_TIM2_REMAP_FULLREMAP AFIO_MAPR_TIM2_REMAP_FULLREMAP_Msk /*!< Full remap (CH1/ETR/PA15, CH2/PB3, CH3/PB10, CH4/PB11) */
+
+#define AFIO_MAPR_TIM3_REMAP_Pos (10U)
+#define AFIO_MAPR_TIM3_REMAP_Msk (0x3U << AFIO_MAPR_TIM3_REMAP_Pos) /*!< 0x00000C00 */
+#define AFIO_MAPR_TIM3_REMAP AFIO_MAPR_TIM3_REMAP_Msk /*!< TIM3_REMAP[1:0] bits (TIM3 remapping) */
+#define AFIO_MAPR_TIM3_REMAP_0 (0x1U << AFIO_MAPR_TIM3_REMAP_Pos) /*!< 0x00000400 */
+#define AFIO_MAPR_TIM3_REMAP_1 (0x2U << AFIO_MAPR_TIM3_REMAP_Pos) /*!< 0x00000800 */
+
+/*!< TIM3_REMAP configuration */
+#define AFIO_MAPR_TIM3_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1) */
+#define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Pos (11U)
+#define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Msk (0x1U << AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Pos) /*!< 0x00000800 */
+#define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Msk /*!< Partial remap (CH1/PB4, CH2/PB5, CH3/PB0, CH4/PB1) */
+#define AFIO_MAPR_TIM3_REMAP_FULLREMAP_Pos (10U)
+#define AFIO_MAPR_TIM3_REMAP_FULLREMAP_Msk (0x3U << AFIO_MAPR_TIM3_REMAP_FULLREMAP_Pos) /*!< 0x00000C00 */
+#define AFIO_MAPR_TIM3_REMAP_FULLREMAP AFIO_MAPR_TIM3_REMAP_FULLREMAP_Msk /*!< Full remap (CH1/PC6, CH2/PC7, CH3/PC8, CH4/PC9) */
+
+#define AFIO_MAPR_TIM4_REMAP_Pos (12U)
+#define AFIO_MAPR_TIM4_REMAP_Msk (0x1U << AFIO_MAPR_TIM4_REMAP_Pos) /*!< 0x00001000 */
+#define AFIO_MAPR_TIM4_REMAP AFIO_MAPR_TIM4_REMAP_Msk /*!< TIM4_REMAP bit (TIM4 remapping) */
+
+
+#define AFIO_MAPR_PD01_REMAP_Pos (15U)
+#define AFIO_MAPR_PD01_REMAP_Msk (0x1U << AFIO_MAPR_PD01_REMAP_Pos) /*!< 0x00008000 */
+#define AFIO_MAPR_PD01_REMAP AFIO_MAPR_PD01_REMAP_Msk /*!< Port D0/Port D1 mapping on OSC_IN/OSC_OUT */
+#define AFIO_MAPR_TIM5CH4_IREMAP_Pos (16U)
+#define AFIO_MAPR_TIM5CH4_IREMAP_Msk (0x1U << AFIO_MAPR_TIM5CH4_IREMAP_Pos) /*!< 0x00010000 */
+#define AFIO_MAPR_TIM5CH4_IREMAP AFIO_MAPR_TIM5CH4_IREMAP_Msk /*!< TIM5 Channel4 Internal Remap */
+
+/*!< SWJ_CFG configuration */
+#define AFIO_MAPR_SWJ_CFG_Pos (24U)
+#define AFIO_MAPR_SWJ_CFG_Msk (0x7U << AFIO_MAPR_SWJ_CFG_Pos) /*!< 0x07000000 */
+#define AFIO_MAPR_SWJ_CFG AFIO_MAPR_SWJ_CFG_Msk /*!< SWJ_CFG[2:0] bits (Serial Wire JTAG configuration) */
+#define AFIO_MAPR_SWJ_CFG_0 (0x1U << AFIO_MAPR_SWJ_CFG_Pos) /*!< 0x01000000 */
+#define AFIO_MAPR_SWJ_CFG_1 (0x2U << AFIO_MAPR_SWJ_CFG_Pos) /*!< 0x02000000 */
+#define AFIO_MAPR_SWJ_CFG_2 (0x4U << AFIO_MAPR_SWJ_CFG_Pos) /*!< 0x04000000 */
+
+#define AFIO_MAPR_SWJ_CFG_RESET ((uint32_t)0x00000000) /*!< Full SWJ (JTAG-DP + SW-DP) : Reset State */
+#define AFIO_MAPR_SWJ_CFG_NOJNTRST_Pos (24U)
+#define AFIO_MAPR_SWJ_CFG_NOJNTRST_Msk (0x1U << AFIO_MAPR_SWJ_CFG_NOJNTRST_Pos) /*!< 0x01000000 */
+#define AFIO_MAPR_SWJ_CFG_NOJNTRST AFIO_MAPR_SWJ_CFG_NOJNTRST_Msk /*!< Full SWJ (JTAG-DP + SW-DP) but without JNTRST */
+#define AFIO_MAPR_SWJ_CFG_JTAGDISABLE_Pos (25U)
+#define AFIO_MAPR_SWJ_CFG_JTAGDISABLE_Msk (0x1U << AFIO_MAPR_SWJ_CFG_JTAGDISABLE_Pos) /*!< 0x02000000 */
+#define AFIO_MAPR_SWJ_CFG_JTAGDISABLE AFIO_MAPR_SWJ_CFG_JTAGDISABLE_Msk /*!< JTAG-DP Disabled and SW-DP Enabled */
+#define AFIO_MAPR_SWJ_CFG_DISABLE_Pos (26U)
+#define AFIO_MAPR_SWJ_CFG_DISABLE_Msk (0x1U << AFIO_MAPR_SWJ_CFG_DISABLE_Pos) /*!< 0x04000000 */
+#define AFIO_MAPR_SWJ_CFG_DISABLE AFIO_MAPR_SWJ_CFG_DISABLE_Msk /*!< JTAG-DP Disabled and SW-DP Disabled */
+
+
+/***************** Bit definition for AFIO_EXTICR1 register *****************/
+#define AFIO_EXTICR1_EXTI0_Pos (0U)
+#define AFIO_EXTICR1_EXTI0_Msk (0xFU << AFIO_EXTICR1_EXTI0_Pos) /*!< 0x0000000F */
+#define AFIO_EXTICR1_EXTI0 AFIO_EXTICR1_EXTI0_Msk /*!< EXTI 0 configuration */
+#define AFIO_EXTICR1_EXTI1_Pos (4U)
+#define AFIO_EXTICR1_EXTI1_Msk (0xFU << AFIO_EXTICR1_EXTI1_Pos) /*!< 0x000000F0 */
+#define AFIO_EXTICR1_EXTI1 AFIO_EXTICR1_EXTI1_Msk /*!< EXTI 1 configuration */
+#define AFIO_EXTICR1_EXTI2_Pos (8U)
+#define AFIO_EXTICR1_EXTI2_Msk (0xFU << AFIO_EXTICR1_EXTI2_Pos) /*!< 0x00000F00 */
+#define AFIO_EXTICR1_EXTI2 AFIO_EXTICR1_EXTI2_Msk /*!< EXTI 2 configuration */
+#define AFIO_EXTICR1_EXTI3_Pos (12U)
+#define AFIO_EXTICR1_EXTI3_Msk (0xFU << AFIO_EXTICR1_EXTI3_Pos) /*!< 0x0000F000 */
+#define AFIO_EXTICR1_EXTI3 AFIO_EXTICR1_EXTI3_Msk /*!< EXTI 3 configuration */
+
+/*!< EXTI0 configuration */
+#define AFIO_EXTICR1_EXTI0_PA ((uint32_t)0x00000000) /*!< PA[0] pin */
+#define AFIO_EXTICR1_EXTI0_PB_Pos (0U)
+#define AFIO_EXTICR1_EXTI0_PB_Msk (0x1U << AFIO_EXTICR1_EXTI0_PB_Pos) /*!< 0x00000001 */
+#define AFIO_EXTICR1_EXTI0_PB AFIO_EXTICR1_EXTI0_PB_Msk /*!< PB[0] pin */
+#define AFIO_EXTICR1_EXTI0_PC_Pos (1U)
+#define AFIO_EXTICR1_EXTI0_PC_Msk (0x1U << AFIO_EXTICR1_EXTI0_PC_Pos) /*!< 0x00000002 */
+#define AFIO_EXTICR1_EXTI0_PC AFIO_EXTICR1_EXTI0_PC_Msk /*!< PC[0] pin */
+#define AFIO_EXTICR1_EXTI0_PD_Pos (0U)
+#define AFIO_EXTICR1_EXTI0_PD_Msk (0x3U << AFIO_EXTICR1_EXTI0_PD_Pos) /*!< 0x00000003 */
+#define AFIO_EXTICR1_EXTI0_PD AFIO_EXTICR1_EXTI0_PD_Msk /*!< PD[0] pin */
+#define AFIO_EXTICR1_EXTI0_PE_Pos (2U)
+#define AFIO_EXTICR1_EXTI0_PE_Msk (0x1U << AFIO_EXTICR1_EXTI0_PE_Pos) /*!< 0x00000004 */
+#define AFIO_EXTICR1_EXTI0_PE AFIO_EXTICR1_EXTI0_PE_Msk /*!< PE[0] pin */
+#define AFIO_EXTICR1_EXTI0_PF_Pos (0U)
+#define AFIO_EXTICR1_EXTI0_PF_Msk (0x5U << AFIO_EXTICR1_EXTI0_PF_Pos) /*!< 0x00000005 */
+#define AFIO_EXTICR1_EXTI0_PF AFIO_EXTICR1_EXTI0_PF_Msk /*!< PF[0] pin */
+#define AFIO_EXTICR1_EXTI0_PG_Pos (1U)
+#define AFIO_EXTICR1_EXTI0_PG_Msk (0x3U << AFIO_EXTICR1_EXTI0_PG_Pos) /*!< 0x00000006 */
+#define AFIO_EXTICR1_EXTI0_PG AFIO_EXTICR1_EXTI0_PG_Msk /*!< PG[0] pin */
+
+/*!< EXTI1 configuration */
+#define AFIO_EXTICR1_EXTI1_PA ((uint32_t)0x00000000) /*!< PA[1] pin */
+#define AFIO_EXTICR1_EXTI1_PB_Pos (4U)
+#define AFIO_EXTICR1_EXTI1_PB_Msk (0x1U << AFIO_EXTICR1_EXTI1_PB_Pos) /*!< 0x00000010 */
+#define AFIO_EXTICR1_EXTI1_PB AFIO_EXTICR1_EXTI1_PB_Msk /*!< PB[1] pin */
+#define AFIO_EXTICR1_EXTI1_PC_Pos (5U)
+#define AFIO_EXTICR1_EXTI1_PC_Msk (0x1U << AFIO_EXTICR1_EXTI1_PC_Pos) /*!< 0x00000020 */
+#define AFIO_EXTICR1_EXTI1_PC AFIO_EXTICR1_EXTI1_PC_Msk /*!< PC[1] pin */
+#define AFIO_EXTICR1_EXTI1_PD_Pos (4U)
+#define AFIO_EXTICR1_EXTI1_PD_Msk (0x3U << AFIO_EXTICR1_EXTI1_PD_Pos) /*!< 0x00000030 */
+#define AFIO_EXTICR1_EXTI1_PD AFIO_EXTICR1_EXTI1_PD_Msk /*!< PD[1] pin */
+#define AFIO_EXTICR1_EXTI1_PE_Pos (6U)
+#define AFIO_EXTICR1_EXTI1_PE_Msk (0x1U << AFIO_EXTICR1_EXTI1_PE_Pos) /*!< 0x00000040 */
+#define AFIO_EXTICR1_EXTI1_PE AFIO_EXTICR1_EXTI1_PE_Msk /*!< PE[1] pin */
+#define AFIO_EXTICR1_EXTI1_PF_Pos (4U)
+#define AFIO_EXTICR1_EXTI1_PF_Msk (0x5U << AFIO_EXTICR1_EXTI1_PF_Pos) /*!< 0x00000050 */
+#define AFIO_EXTICR1_EXTI1_PF AFIO_EXTICR1_EXTI1_PF_Msk /*!< PF[1] pin */
+#define AFIO_EXTICR1_EXTI1_PG_Pos (5U)
+#define AFIO_EXTICR1_EXTI1_PG_Msk (0x3U << AFIO_EXTICR1_EXTI1_PG_Pos) /*!< 0x00000060 */
+#define AFIO_EXTICR1_EXTI1_PG AFIO_EXTICR1_EXTI1_PG_Msk /*!< PG[1] pin */
+
+/*!< EXTI2 configuration */
+#define AFIO_EXTICR1_EXTI2_PA ((uint32_t)0x00000000) /*!< PA[2] pin */
+#define AFIO_EXTICR1_EXTI2_PB_Pos (8U)
+#define AFIO_EXTICR1_EXTI2_PB_Msk (0x1U << AFIO_EXTICR1_EXTI2_PB_Pos) /*!< 0x00000100 */
+#define AFIO_EXTICR1_EXTI2_PB AFIO_EXTICR1_EXTI2_PB_Msk /*!< PB[2] pin */
+#define AFIO_EXTICR1_EXTI2_PC_Pos (9U)
+#define AFIO_EXTICR1_EXTI2_PC_Msk (0x1U << AFIO_EXTICR1_EXTI2_PC_Pos) /*!< 0x00000200 */
+#define AFIO_EXTICR1_EXTI2_PC AFIO_EXTICR1_EXTI2_PC_Msk /*!< PC[2] pin */
+#define AFIO_EXTICR1_EXTI2_PD_Pos (8U)
+#define AFIO_EXTICR1_EXTI2_PD_Msk (0x3U << AFIO_EXTICR1_EXTI2_PD_Pos) /*!< 0x00000300 */
+#define AFIO_EXTICR1_EXTI2_PD AFIO_EXTICR1_EXTI2_PD_Msk /*!< PD[2] pin */
+#define AFIO_EXTICR1_EXTI2_PE_Pos (10U)
+#define AFIO_EXTICR1_EXTI2_PE_Msk (0x1U << AFIO_EXTICR1_EXTI2_PE_Pos) /*!< 0x00000400 */
+#define AFIO_EXTICR1_EXTI2_PE AFIO_EXTICR1_EXTI2_PE_Msk /*!< PE[2] pin */
+#define AFIO_EXTICR1_EXTI2_PF_Pos (8U)
+#define AFIO_EXTICR1_EXTI2_PF_Msk (0x5U << AFIO_EXTICR1_EXTI2_PF_Pos) /*!< 0x00000500 */
+#define AFIO_EXTICR1_EXTI2_PF AFIO_EXTICR1_EXTI2_PF_Msk /*!< PF[2] pin */
+#define AFIO_EXTICR1_EXTI2_PG_Pos (9U)
+#define AFIO_EXTICR1_EXTI2_PG_Msk (0x3U << AFIO_EXTICR1_EXTI2_PG_Pos) /*!< 0x00000600 */
+#define AFIO_EXTICR1_EXTI2_PG AFIO_EXTICR1_EXTI2_PG_Msk /*!< PG[2] pin */
+
+/*!< EXTI3 configuration */
+#define AFIO_EXTICR1_EXTI3_PA ((uint32_t)0x00000000) /*!< PA[3] pin */
+#define AFIO_EXTICR1_EXTI3_PB_Pos (12U)
+#define AFIO_EXTICR1_EXTI3_PB_Msk (0x1U << AFIO_EXTICR1_EXTI3_PB_Pos) /*!< 0x00001000 */
+#define AFIO_EXTICR1_EXTI3_PB AFIO_EXTICR1_EXTI3_PB_Msk /*!< PB[3] pin */
+#define AFIO_EXTICR1_EXTI3_PC_Pos (13U)
+#define AFIO_EXTICR1_EXTI3_PC_Msk (0x1U << AFIO_EXTICR1_EXTI3_PC_Pos) /*!< 0x00002000 */
+#define AFIO_EXTICR1_EXTI3_PC AFIO_EXTICR1_EXTI3_PC_Msk /*!< PC[3] pin */
+#define AFIO_EXTICR1_EXTI3_PD_Pos (12U)
+#define AFIO_EXTICR1_EXTI3_PD_Msk (0x3U << AFIO_EXTICR1_EXTI3_PD_Pos) /*!< 0x00003000 */
+#define AFIO_EXTICR1_EXTI3_PD AFIO_EXTICR1_EXTI3_PD_Msk /*!< PD[3] pin */
+#define AFIO_EXTICR1_EXTI3_PE_Pos (14U)
+#define AFIO_EXTICR1_EXTI3_PE_Msk (0x1U << AFIO_EXTICR1_EXTI3_PE_Pos) /*!< 0x00004000 */
+#define AFIO_EXTICR1_EXTI3_PE AFIO_EXTICR1_EXTI3_PE_Msk /*!< PE[3] pin */
+#define AFIO_EXTICR1_EXTI3_PF_Pos (12U)
+#define AFIO_EXTICR1_EXTI3_PF_Msk (0x5U << AFIO_EXTICR1_EXTI3_PF_Pos) /*!< 0x00005000 */
+#define AFIO_EXTICR1_EXTI3_PF AFIO_EXTICR1_EXTI3_PF_Msk /*!< PF[3] pin */
+#define AFIO_EXTICR1_EXTI3_PG_Pos (13U)
+#define AFIO_EXTICR1_EXTI3_PG_Msk (0x3U << AFIO_EXTICR1_EXTI3_PG_Pos) /*!< 0x00006000 */
+#define AFIO_EXTICR1_EXTI3_PG AFIO_EXTICR1_EXTI3_PG_Msk /*!< PG[3] pin */
+
+/***************** Bit definition for AFIO_EXTICR2 register *****************/
+#define AFIO_EXTICR2_EXTI4_Pos (0U)
+#define AFIO_EXTICR2_EXTI4_Msk (0xFU << AFIO_EXTICR2_EXTI4_Pos) /*!< 0x0000000F */
+#define AFIO_EXTICR2_EXTI4 AFIO_EXTICR2_EXTI4_Msk /*!< EXTI 4 configuration */
+#define AFIO_EXTICR2_EXTI5_Pos (4U)
+#define AFIO_EXTICR2_EXTI5_Msk (0xFU << AFIO_EXTICR2_EXTI5_Pos) /*!< 0x000000F0 */
+#define AFIO_EXTICR2_EXTI5 AFIO_EXTICR2_EXTI5_Msk /*!< EXTI 5 configuration */
+#define AFIO_EXTICR2_EXTI6_Pos (8U)
+#define AFIO_EXTICR2_EXTI6_Msk (0xFU << AFIO_EXTICR2_EXTI6_Pos) /*!< 0x00000F00 */
+#define AFIO_EXTICR2_EXTI6 AFIO_EXTICR2_EXTI6_Msk /*!< EXTI 6 configuration */
+#define AFIO_EXTICR2_EXTI7_Pos (12U)
+#define AFIO_EXTICR2_EXTI7_Msk (0xFU << AFIO_EXTICR2_EXTI7_Pos) /*!< 0x0000F000 */
+#define AFIO_EXTICR2_EXTI7 AFIO_EXTICR2_EXTI7_Msk /*!< EXTI 7 configuration */
+
+/*!< EXTI4 configuration */
+#define AFIO_EXTICR2_EXTI4_PA ((uint32_t)0x00000000) /*!< PA[4] pin */
+#define AFIO_EXTICR2_EXTI4_PB_Pos (0U)
+#define AFIO_EXTICR2_EXTI4_PB_Msk (0x1U << AFIO_EXTICR2_EXTI4_PB_Pos) /*!< 0x00000001 */
+#define AFIO_EXTICR2_EXTI4_PB AFIO_EXTICR2_EXTI4_PB_Msk /*!< PB[4] pin */
+#define AFIO_EXTICR2_EXTI4_PC_Pos (1U)
+#define AFIO_EXTICR2_EXTI4_PC_Msk (0x1U << AFIO_EXTICR2_EXTI4_PC_Pos) /*!< 0x00000002 */
+#define AFIO_EXTICR2_EXTI4_PC AFIO_EXTICR2_EXTI4_PC_Msk /*!< PC[4] pin */
+#define AFIO_EXTICR2_EXTI4_PD_Pos (0U)
+#define AFIO_EXTICR2_EXTI4_PD_Msk (0x3U << AFIO_EXTICR2_EXTI4_PD_Pos) /*!< 0x00000003 */
+#define AFIO_EXTICR2_EXTI4_PD AFIO_EXTICR2_EXTI4_PD_Msk /*!< PD[4] pin */
+#define AFIO_EXTICR2_EXTI4_PE_Pos (2U)
+#define AFIO_EXTICR2_EXTI4_PE_Msk (0x1U << AFIO_EXTICR2_EXTI4_PE_Pos) /*!< 0x00000004 */
+#define AFIO_EXTICR2_EXTI4_PE AFIO_EXTICR2_EXTI4_PE_Msk /*!< PE[4] pin */
+#define AFIO_EXTICR2_EXTI4_PF_Pos (0U)
+#define AFIO_EXTICR2_EXTI4_PF_Msk (0x5U << AFIO_EXTICR2_EXTI4_PF_Pos) /*!< 0x00000005 */
+#define AFIO_EXTICR2_EXTI4_PF AFIO_EXTICR2_EXTI4_PF_Msk /*!< PF[4] pin */
+#define AFIO_EXTICR2_EXTI4_PG_Pos (1U)
+#define AFIO_EXTICR2_EXTI4_PG_Msk (0x3U << AFIO_EXTICR2_EXTI4_PG_Pos) /*!< 0x00000006 */
+#define AFIO_EXTICR2_EXTI4_PG AFIO_EXTICR2_EXTI4_PG_Msk /*!< PG[4] pin */
+
+/* EXTI5 configuration */
+#define AFIO_EXTICR2_EXTI5_PA ((uint32_t)0x00000000) /*!< PA[5] pin */
+#define AFIO_EXTICR2_EXTI5_PB_Pos (4U)
+#define AFIO_EXTICR2_EXTI5_PB_Msk (0x1U << AFIO_EXTICR2_EXTI5_PB_Pos) /*!< 0x00000010 */
+#define AFIO_EXTICR2_EXTI5_PB AFIO_EXTICR2_EXTI5_PB_Msk /*!< PB[5] pin */
+#define AFIO_EXTICR2_EXTI5_PC_Pos (5U)
+#define AFIO_EXTICR2_EXTI5_PC_Msk (0x1U << AFIO_EXTICR2_EXTI5_PC_Pos) /*!< 0x00000020 */
+#define AFIO_EXTICR2_EXTI5_PC AFIO_EXTICR2_EXTI5_PC_Msk /*!< PC[5] pin */
+#define AFIO_EXTICR2_EXTI5_PD_Pos (4U)
+#define AFIO_EXTICR2_EXTI5_PD_Msk (0x3U << AFIO_EXTICR2_EXTI5_PD_Pos) /*!< 0x00000030 */
+#define AFIO_EXTICR2_EXTI5_PD AFIO_EXTICR2_EXTI5_PD_Msk /*!< PD[5] pin */
+#define AFIO_EXTICR2_EXTI5_PE_Pos (6U)
+#define AFIO_EXTICR2_EXTI5_PE_Msk (0x1U << AFIO_EXTICR2_EXTI5_PE_Pos) /*!< 0x00000040 */
+#define AFIO_EXTICR2_EXTI5_PE AFIO_EXTICR2_EXTI5_PE_Msk /*!< PE[5] pin */
+#define AFIO_EXTICR2_EXTI5_PF_Pos (4U)
+#define AFIO_EXTICR2_EXTI5_PF_Msk (0x5U << AFIO_EXTICR2_EXTI5_PF_Pos) /*!< 0x00000050 */
+#define AFIO_EXTICR2_EXTI5_PF AFIO_EXTICR2_EXTI5_PF_Msk /*!< PF[5] pin */
+#define AFIO_EXTICR2_EXTI5_PG_Pos (5U)
+#define AFIO_EXTICR2_EXTI5_PG_Msk (0x3U << AFIO_EXTICR2_EXTI5_PG_Pos) /*!< 0x00000060 */
+#define AFIO_EXTICR2_EXTI5_PG AFIO_EXTICR2_EXTI5_PG_Msk /*!< PG[5] pin */
+
+/*!< EXTI6 configuration */
+#define AFIO_EXTICR2_EXTI6_PA ((uint32_t)0x00000000) /*!< PA[6] pin */
+#define AFIO_EXTICR2_EXTI6_PB_Pos (8U)
+#define AFIO_EXTICR2_EXTI6_PB_Msk (0x1U << AFIO_EXTICR2_EXTI6_PB_Pos) /*!< 0x00000100 */
+#define AFIO_EXTICR2_EXTI6_PB AFIO_EXTICR2_EXTI6_PB_Msk /*!< PB[6] pin */
+#define AFIO_EXTICR2_EXTI6_PC_Pos (9U)
+#define AFIO_EXTICR2_EXTI6_PC_Msk (0x1U << AFIO_EXTICR2_EXTI6_PC_Pos) /*!< 0x00000200 */
+#define AFIO_EXTICR2_EXTI6_PC AFIO_EXTICR2_EXTI6_PC_Msk /*!< PC[6] pin */
+#define AFIO_EXTICR2_EXTI6_PD_Pos (8U)
+#define AFIO_EXTICR2_EXTI6_PD_Msk (0x3U << AFIO_EXTICR2_EXTI6_PD_Pos) /*!< 0x00000300 */
+#define AFIO_EXTICR2_EXTI6_PD AFIO_EXTICR2_EXTI6_PD_Msk /*!< PD[6] pin */
+#define AFIO_EXTICR2_EXTI6_PE_Pos (10U)
+#define AFIO_EXTICR2_EXTI6_PE_Msk (0x1U << AFIO_EXTICR2_EXTI6_PE_Pos) /*!< 0x00000400 */
+#define AFIO_EXTICR2_EXTI6_PE AFIO_EXTICR2_EXTI6_PE_Msk /*!< PE[6] pin */
+#define AFIO_EXTICR2_EXTI6_PF_Pos (8U)
+#define AFIO_EXTICR2_EXTI6_PF_Msk (0x5U << AFIO_EXTICR2_EXTI6_PF_Pos) /*!< 0x00000500 */
+#define AFIO_EXTICR2_EXTI6_PF AFIO_EXTICR2_EXTI6_PF_Msk /*!< PF[6] pin */
+#define AFIO_EXTICR2_EXTI6_PG_Pos (9U)
+#define AFIO_EXTICR2_EXTI6_PG_Msk (0x3U << AFIO_EXTICR2_EXTI6_PG_Pos) /*!< 0x00000600 */
+#define AFIO_EXTICR2_EXTI6_PG AFIO_EXTICR2_EXTI6_PG_Msk /*!< PG[6] pin */
+
+/*!< EXTI7 configuration */
+#define AFIO_EXTICR2_EXTI7_PA ((uint32_t)0x00000000) /*!< PA[7] pin */
+#define AFIO_EXTICR2_EXTI7_PB_Pos (12U)
+#define AFIO_EXTICR2_EXTI7_PB_Msk (0x1U << AFIO_EXTICR2_EXTI7_PB_Pos) /*!< 0x00001000 */
+#define AFIO_EXTICR2_EXTI7_PB AFIO_EXTICR2_EXTI7_PB_Msk /*!< PB[7] pin */
+#define AFIO_EXTICR2_EXTI7_PC_Pos (13U)
+#define AFIO_EXTICR2_EXTI7_PC_Msk (0x1U << AFIO_EXTICR2_EXTI7_PC_Pos) /*!< 0x00002000 */
+#define AFIO_EXTICR2_EXTI7_PC AFIO_EXTICR2_EXTI7_PC_Msk /*!< PC[7] pin */
+#define AFIO_EXTICR2_EXTI7_PD_Pos (12U)
+#define AFIO_EXTICR2_EXTI7_PD_Msk (0x3U << AFIO_EXTICR2_EXTI7_PD_Pos) /*!< 0x00003000 */
+#define AFIO_EXTICR2_EXTI7_PD AFIO_EXTICR2_EXTI7_PD_Msk /*!< PD[7] pin */
+#define AFIO_EXTICR2_EXTI7_PE_Pos (14U)
+#define AFIO_EXTICR2_EXTI7_PE_Msk (0x1U << AFIO_EXTICR2_EXTI7_PE_Pos) /*!< 0x00004000 */
+#define AFIO_EXTICR2_EXTI7_PE AFIO_EXTICR2_EXTI7_PE_Msk /*!< PE[7] pin */
+#define AFIO_EXTICR2_EXTI7_PF_Pos (12U)
+#define AFIO_EXTICR2_EXTI7_PF_Msk (0x5U << AFIO_EXTICR2_EXTI7_PF_Pos) /*!< 0x00005000 */
+#define AFIO_EXTICR2_EXTI7_PF AFIO_EXTICR2_EXTI7_PF_Msk /*!< PF[7] pin */
+#define AFIO_EXTICR2_EXTI7_PG_Pos (13U)
+#define AFIO_EXTICR2_EXTI7_PG_Msk (0x3U << AFIO_EXTICR2_EXTI7_PG_Pos) /*!< 0x00006000 */
+#define AFIO_EXTICR2_EXTI7_PG AFIO_EXTICR2_EXTI7_PG_Msk /*!< PG[7] pin */
+
+/***************** Bit definition for AFIO_EXTICR3 register *****************/
+#define AFIO_EXTICR3_EXTI8_Pos (0U)
+#define AFIO_EXTICR3_EXTI8_Msk (0xFU << AFIO_EXTICR3_EXTI8_Pos) /*!< 0x0000000F */
+#define AFIO_EXTICR3_EXTI8 AFIO_EXTICR3_EXTI8_Msk /*!< EXTI 8 configuration */
+#define AFIO_EXTICR3_EXTI9_Pos (4U)
+#define AFIO_EXTICR3_EXTI9_Msk (0xFU << AFIO_EXTICR3_EXTI9_Pos) /*!< 0x000000F0 */
+#define AFIO_EXTICR3_EXTI9 AFIO_EXTICR3_EXTI9_Msk /*!< EXTI 9 configuration */
+#define AFIO_EXTICR3_EXTI10_Pos (8U)
+#define AFIO_EXTICR3_EXTI10_Msk (0xFU << AFIO_EXTICR3_EXTI10_Pos) /*!< 0x00000F00 */
+#define AFIO_EXTICR3_EXTI10 AFIO_EXTICR3_EXTI10_Msk /*!< EXTI 10 configuration */
+#define AFIO_EXTICR3_EXTI11_Pos (12U)
+#define AFIO_EXTICR3_EXTI11_Msk (0xFU << AFIO_EXTICR3_EXTI11_Pos) /*!< 0x0000F000 */
+#define AFIO_EXTICR3_EXTI11 AFIO_EXTICR3_EXTI11_Msk /*!< EXTI 11 configuration */
+
+/*!< EXTI8 configuration */
+#define AFIO_EXTICR3_EXTI8_PA ((uint32_t)0x00000000) /*!< PA[8] pin */
+#define AFIO_EXTICR3_EXTI8_PB_Pos (0U)
+#define AFIO_EXTICR3_EXTI8_PB_Msk (0x1U << AFIO_EXTICR3_EXTI8_PB_Pos) /*!< 0x00000001 */
+#define AFIO_EXTICR3_EXTI8_PB AFIO_EXTICR3_EXTI8_PB_Msk /*!< PB[8] pin */
+#define AFIO_EXTICR3_EXTI8_PC_Pos (1U)
+#define AFIO_EXTICR3_EXTI8_PC_Msk (0x1U << AFIO_EXTICR3_EXTI8_PC_Pos) /*!< 0x00000002 */
+#define AFIO_EXTICR3_EXTI8_PC AFIO_EXTICR3_EXTI8_PC_Msk /*!< PC[8] pin */
+#define AFIO_EXTICR3_EXTI8_PD_Pos (0U)
+#define AFIO_EXTICR3_EXTI8_PD_Msk (0x3U << AFIO_EXTICR3_EXTI8_PD_Pos) /*!< 0x00000003 */
+#define AFIO_EXTICR3_EXTI8_PD AFIO_EXTICR3_EXTI8_PD_Msk /*!< PD[8] pin */
+#define AFIO_EXTICR3_EXTI8_PE_Pos (2U)
+#define AFIO_EXTICR3_EXTI8_PE_Msk (0x1U << AFIO_EXTICR3_EXTI8_PE_Pos) /*!< 0x00000004 */
+#define AFIO_EXTICR3_EXTI8_PE AFIO_EXTICR3_EXTI8_PE_Msk /*!< PE[8] pin */
+#define AFIO_EXTICR3_EXTI8_PF_Pos (0U)
+#define AFIO_EXTICR3_EXTI8_PF_Msk (0x5U << AFIO_EXTICR3_EXTI8_PF_Pos) /*!< 0x00000005 */
+#define AFIO_EXTICR3_EXTI8_PF AFIO_EXTICR3_EXTI8_PF_Msk /*!< PF[8] pin */
+#define AFIO_EXTICR3_EXTI8_PG_Pos (1U)
+#define AFIO_EXTICR3_EXTI8_PG_Msk (0x3U << AFIO_EXTICR3_EXTI8_PG_Pos) /*!< 0x00000006 */
+#define AFIO_EXTICR3_EXTI8_PG AFIO_EXTICR3_EXTI8_PG_Msk /*!< PG[8] pin */
+
+/*!< EXTI9 configuration */
+#define AFIO_EXTICR3_EXTI9_PA ((uint32_t)0x00000000) /*!< PA[9] pin */
+#define AFIO_EXTICR3_EXTI9_PB_Pos (4U)
+#define AFIO_EXTICR3_EXTI9_PB_Msk (0x1U << AFIO_EXTICR3_EXTI9_PB_Pos) /*!< 0x00000010 */
+#define AFIO_EXTICR3_EXTI9_PB AFIO_EXTICR3_EXTI9_PB_Msk /*!< PB[9] pin */
+#define AFIO_EXTICR3_EXTI9_PC_Pos (5U)
+#define AFIO_EXTICR3_EXTI9_PC_Msk (0x1U << AFIO_EXTICR3_EXTI9_PC_Pos) /*!< 0x00000020 */
+#define AFIO_EXTICR3_EXTI9_PC AFIO_EXTICR3_EXTI9_PC_Msk /*!< PC[9] pin */
+#define AFIO_EXTICR3_EXTI9_PD_Pos (4U)
+#define AFIO_EXTICR3_EXTI9_PD_Msk (0x3U << AFIO_EXTICR3_EXTI9_PD_Pos) /*!< 0x00000030 */
+#define AFIO_EXTICR3_EXTI9_PD AFIO_EXTICR3_EXTI9_PD_Msk /*!< PD[9] pin */
+#define AFIO_EXTICR3_EXTI9_PE_Pos (6U)
+#define AFIO_EXTICR3_EXTI9_PE_Msk (0x1U << AFIO_EXTICR3_EXTI9_PE_Pos) /*!< 0x00000040 */
+#define AFIO_EXTICR3_EXTI9_PE AFIO_EXTICR3_EXTI9_PE_Msk /*!< PE[9] pin */
+#define AFIO_EXTICR3_EXTI9_PF_Pos (4U)
+#define AFIO_EXTICR3_EXTI9_PF_Msk (0x5U << AFIO_EXTICR3_EXTI9_PF_Pos) /*!< 0x00000050 */
+#define AFIO_EXTICR3_EXTI9_PF AFIO_EXTICR3_EXTI9_PF_Msk /*!< PF[9] pin */
+#define AFIO_EXTICR3_EXTI9_PG_Pos (5U)
+#define AFIO_EXTICR3_EXTI9_PG_Msk (0x3U << AFIO_EXTICR3_EXTI9_PG_Pos) /*!< 0x00000060 */
+#define AFIO_EXTICR3_EXTI9_PG AFIO_EXTICR3_EXTI9_PG_Msk /*!< PG[9] pin */
+
+/*!< EXTI10 configuration */
+#define AFIO_EXTICR3_EXTI10_PA ((uint32_t)0x00000000) /*!< PA[10] pin */
+#define AFIO_EXTICR3_EXTI10_PB_Pos (8U)
+#define AFIO_EXTICR3_EXTI10_PB_Msk (0x1U << AFIO_EXTICR3_EXTI10_PB_Pos) /*!< 0x00000100 */
+#define AFIO_EXTICR3_EXTI10_PB AFIO_EXTICR3_EXTI10_PB_Msk /*!< PB[10] pin */
+#define AFIO_EXTICR3_EXTI10_PC_Pos (9U)
+#define AFIO_EXTICR3_EXTI10_PC_Msk (0x1U << AFIO_EXTICR3_EXTI10_PC_Pos) /*!< 0x00000200 */
+#define AFIO_EXTICR3_EXTI10_PC AFIO_EXTICR3_EXTI10_PC_Msk /*!< PC[10] pin */
+#define AFIO_EXTICR3_EXTI10_PD_Pos (8U)
+#define AFIO_EXTICR3_EXTI10_PD_Msk (0x3U << AFIO_EXTICR3_EXTI10_PD_Pos) /*!< 0x00000300 */
+#define AFIO_EXTICR3_EXTI10_PD AFIO_EXTICR3_EXTI10_PD_Msk /*!< PD[10] pin */
+#define AFIO_EXTICR3_EXTI10_PE_Pos (10U)
+#define AFIO_EXTICR3_EXTI10_PE_Msk (0x1U << AFIO_EXTICR3_EXTI10_PE_Pos) /*!< 0x00000400 */
+#define AFIO_EXTICR3_EXTI10_PE AFIO_EXTICR3_EXTI10_PE_Msk /*!< PE[10] pin */
+#define AFIO_EXTICR3_EXTI10_PF_Pos (8U)
+#define AFIO_EXTICR3_EXTI10_PF_Msk (0x5U << AFIO_EXTICR3_EXTI10_PF_Pos) /*!< 0x00000500 */
+#define AFIO_EXTICR3_EXTI10_PF AFIO_EXTICR3_EXTI10_PF_Msk /*!< PF[10] pin */
+#define AFIO_EXTICR3_EXTI10_PG_Pos (9U)
+#define AFIO_EXTICR3_EXTI10_PG_Msk (0x3U << AFIO_EXTICR3_EXTI10_PG_Pos) /*!< 0x00000600 */
+#define AFIO_EXTICR3_EXTI10_PG AFIO_EXTICR3_EXTI10_PG_Msk /*!< PG[10] pin */
+
+/*!< EXTI11 configuration */
+#define AFIO_EXTICR3_EXTI11_PA ((uint32_t)0x00000000) /*!< PA[11] pin */
+#define AFIO_EXTICR3_EXTI11_PB_Pos (12U)
+#define AFIO_EXTICR3_EXTI11_PB_Msk (0x1U << AFIO_EXTICR3_EXTI11_PB_Pos) /*!< 0x00001000 */
+#define AFIO_EXTICR3_EXTI11_PB AFIO_EXTICR3_EXTI11_PB_Msk /*!< PB[11] pin */
+#define AFIO_EXTICR3_EXTI11_PC_Pos (13U)
+#define AFIO_EXTICR3_EXTI11_PC_Msk (0x1U << AFIO_EXTICR3_EXTI11_PC_Pos) /*!< 0x00002000 */
+#define AFIO_EXTICR3_EXTI11_PC AFIO_EXTICR3_EXTI11_PC_Msk /*!< PC[11] pin */
+#define AFIO_EXTICR3_EXTI11_PD_Pos (12U)
+#define AFIO_EXTICR3_EXTI11_PD_Msk (0x3U << AFIO_EXTICR3_EXTI11_PD_Pos) /*!< 0x00003000 */
+#define AFIO_EXTICR3_EXTI11_PD AFIO_EXTICR3_EXTI11_PD_Msk /*!< PD[11] pin */
+#define AFIO_EXTICR3_EXTI11_PE_Pos (14U)
+#define AFIO_EXTICR3_EXTI11_PE_Msk (0x1U << AFIO_EXTICR3_EXTI11_PE_Pos) /*!< 0x00004000 */
+#define AFIO_EXTICR3_EXTI11_PE AFIO_EXTICR3_EXTI11_PE_Msk /*!< PE[11] pin */
+#define AFIO_EXTICR3_EXTI11_PF_Pos (12U)
+#define AFIO_EXTICR3_EXTI11_PF_Msk (0x5U << AFIO_EXTICR3_EXTI11_PF_Pos) /*!< 0x00005000 */
+#define AFIO_EXTICR3_EXTI11_PF AFIO_EXTICR3_EXTI11_PF_Msk /*!< PF[11] pin */
+#define AFIO_EXTICR3_EXTI11_PG_Pos (13U)
+#define AFIO_EXTICR3_EXTI11_PG_Msk (0x3U << AFIO_EXTICR3_EXTI11_PG_Pos) /*!< 0x00006000 */
+#define AFIO_EXTICR3_EXTI11_PG AFIO_EXTICR3_EXTI11_PG_Msk /*!< PG[11] pin */
+
+/***************** Bit definition for AFIO_EXTICR4 register *****************/
+#define AFIO_EXTICR4_EXTI12_Pos (0U)
+#define AFIO_EXTICR4_EXTI12_Msk (0xFU << AFIO_EXTICR4_EXTI12_Pos) /*!< 0x0000000F */
+#define AFIO_EXTICR4_EXTI12 AFIO_EXTICR4_EXTI12_Msk /*!< EXTI 12 configuration */
+#define AFIO_EXTICR4_EXTI13_Pos (4U)
+#define AFIO_EXTICR4_EXTI13_Msk (0xFU << AFIO_EXTICR4_EXTI13_Pos) /*!< 0x000000F0 */
+#define AFIO_EXTICR4_EXTI13 AFIO_EXTICR4_EXTI13_Msk /*!< EXTI 13 configuration */
+#define AFIO_EXTICR4_EXTI14_Pos (8U)
+#define AFIO_EXTICR4_EXTI14_Msk (0xFU << AFIO_EXTICR4_EXTI14_Pos) /*!< 0x00000F00 */
+#define AFIO_EXTICR4_EXTI14 AFIO_EXTICR4_EXTI14_Msk /*!< EXTI 14 configuration */
+#define AFIO_EXTICR4_EXTI15_Pos (12U)
+#define AFIO_EXTICR4_EXTI15_Msk (0xFU << AFIO_EXTICR4_EXTI15_Pos) /*!< 0x0000F000 */
+#define AFIO_EXTICR4_EXTI15 AFIO_EXTICR4_EXTI15_Msk /*!< EXTI 15 configuration */
+
+/* EXTI12 configuration */
+#define AFIO_EXTICR4_EXTI12_PA ((uint32_t)0x00000000) /*!< PA[12] pin */
+#define AFIO_EXTICR4_EXTI12_PB_Pos (0U)
+#define AFIO_EXTICR4_EXTI12_PB_Msk (0x1U << AFIO_EXTICR4_EXTI12_PB_Pos) /*!< 0x00000001 */
+#define AFIO_EXTICR4_EXTI12_PB AFIO_EXTICR4_EXTI12_PB_Msk /*!< PB[12] pin */
+#define AFIO_EXTICR4_EXTI12_PC_Pos (1U)
+#define AFIO_EXTICR4_EXTI12_PC_Msk (0x1U << AFIO_EXTICR4_EXTI12_PC_Pos) /*!< 0x00000002 */
+#define AFIO_EXTICR4_EXTI12_PC AFIO_EXTICR4_EXTI12_PC_Msk /*!< PC[12] pin */
+#define AFIO_EXTICR4_EXTI12_PD_Pos (0U)
+#define AFIO_EXTICR4_EXTI12_PD_Msk (0x3U << AFIO_EXTICR4_EXTI12_PD_Pos) /*!< 0x00000003 */
+#define AFIO_EXTICR4_EXTI12_PD AFIO_EXTICR4_EXTI12_PD_Msk /*!< PD[12] pin */
+#define AFIO_EXTICR4_EXTI12_PE_Pos (2U)
+#define AFIO_EXTICR4_EXTI12_PE_Msk (0x1U << AFIO_EXTICR4_EXTI12_PE_Pos) /*!< 0x00000004 */
+#define AFIO_EXTICR4_EXTI12_PE AFIO_EXTICR4_EXTI12_PE_Msk /*!< PE[12] pin */
+#define AFIO_EXTICR4_EXTI12_PF_Pos (0U)
+#define AFIO_EXTICR4_EXTI12_PF_Msk (0x5U << AFIO_EXTICR4_EXTI12_PF_Pos) /*!< 0x00000005 */
+#define AFIO_EXTICR4_EXTI12_PF AFIO_EXTICR4_EXTI12_PF_Msk /*!< PF[12] pin */
+#define AFIO_EXTICR4_EXTI12_PG_Pos (1U)
+#define AFIO_EXTICR4_EXTI12_PG_Msk (0x3U << AFIO_EXTICR4_EXTI12_PG_Pos) /*!< 0x00000006 */
+#define AFIO_EXTICR4_EXTI12_PG AFIO_EXTICR4_EXTI12_PG_Msk /*!< PG[12] pin */
+
+/* EXTI13 configuration */
+#define AFIO_EXTICR4_EXTI13_PA ((uint32_t)0x00000000) /*!< PA[13] pin */
+#define AFIO_EXTICR4_EXTI13_PB_Pos (4U)
+#define AFIO_EXTICR4_EXTI13_PB_Msk (0x1U << AFIO_EXTICR4_EXTI13_PB_Pos) /*!< 0x00000010 */
+#define AFIO_EXTICR4_EXTI13_PB AFIO_EXTICR4_EXTI13_PB_Msk /*!< PB[13] pin */
+#define AFIO_EXTICR4_EXTI13_PC_Pos (5U)
+#define AFIO_EXTICR4_EXTI13_PC_Msk (0x1U << AFIO_EXTICR4_EXTI13_PC_Pos) /*!< 0x00000020 */
+#define AFIO_EXTICR4_EXTI13_PC AFIO_EXTICR4_EXTI13_PC_Msk /*!< PC[13] pin */
+#define AFIO_EXTICR4_EXTI13_PD_Pos (4U)
+#define AFIO_EXTICR4_EXTI13_PD_Msk (0x3U << AFIO_EXTICR4_EXTI13_PD_Pos) /*!< 0x00000030 */
+#define AFIO_EXTICR4_EXTI13_PD AFIO_EXTICR4_EXTI13_PD_Msk /*!< PD[13] pin */
+#define AFIO_EXTICR4_EXTI13_PE_Pos (6U)
+#define AFIO_EXTICR4_EXTI13_PE_Msk (0x1U << AFIO_EXTICR4_EXTI13_PE_Pos) /*!< 0x00000040 */
+#define AFIO_EXTICR4_EXTI13_PE AFIO_EXTICR4_EXTI13_PE_Msk /*!< PE[13] pin */
+#define AFIO_EXTICR4_EXTI13_PF_Pos (4U)
+#define AFIO_EXTICR4_EXTI13_PF_Msk (0x5U << AFIO_EXTICR4_EXTI13_PF_Pos) /*!< 0x00000050 */
+#define AFIO_EXTICR4_EXTI13_PF AFIO_EXTICR4_EXTI13_PF_Msk /*!< PF[13] pin */
+#define AFIO_EXTICR4_EXTI13_PG_Pos (5U)
+#define AFIO_EXTICR4_EXTI13_PG_Msk (0x3U << AFIO_EXTICR4_EXTI13_PG_Pos) /*!< 0x00000060 */
+#define AFIO_EXTICR4_EXTI13_PG AFIO_EXTICR4_EXTI13_PG_Msk /*!< PG[13] pin */
+
+/*!< EXTI14 configuration */
+#define AFIO_EXTICR4_EXTI14_PA ((uint32_t)0x00000000) /*!< PA[14] pin */
+#define AFIO_EXTICR4_EXTI14_PB_Pos (8U)
+#define AFIO_EXTICR4_EXTI14_PB_Msk (0x1U << AFIO_EXTICR4_EXTI14_PB_Pos) /*!< 0x00000100 */
+#define AFIO_EXTICR4_EXTI14_PB AFIO_EXTICR4_EXTI14_PB_Msk /*!< PB[14] pin */
+#define AFIO_EXTICR4_EXTI14_PC_Pos (9U)
+#define AFIO_EXTICR4_EXTI14_PC_Msk (0x1U << AFIO_EXTICR4_EXTI14_PC_Pos) /*!< 0x00000200 */
+#define AFIO_EXTICR4_EXTI14_PC AFIO_EXTICR4_EXTI14_PC_Msk /*!< PC[14] pin */
+#define AFIO_EXTICR4_EXTI14_PD_Pos (8U)
+#define AFIO_EXTICR4_EXTI14_PD_Msk (0x3U << AFIO_EXTICR4_EXTI14_PD_Pos) /*!< 0x00000300 */
+#define AFIO_EXTICR4_EXTI14_PD AFIO_EXTICR4_EXTI14_PD_Msk /*!< PD[14] pin */
+#define AFIO_EXTICR4_EXTI14_PE_Pos (10U)
+#define AFIO_EXTICR4_EXTI14_PE_Msk (0x1U << AFIO_EXTICR4_EXTI14_PE_Pos) /*!< 0x00000400 */
+#define AFIO_EXTICR4_EXTI14_PE AFIO_EXTICR4_EXTI14_PE_Msk /*!< PE[14] pin */
+#define AFIO_EXTICR4_EXTI14_PF_Pos (8U)
+#define AFIO_EXTICR4_EXTI14_PF_Msk (0x5U << AFIO_EXTICR4_EXTI14_PF_Pos) /*!< 0x00000500 */
+#define AFIO_EXTICR4_EXTI14_PF AFIO_EXTICR4_EXTI14_PF_Msk /*!< PF[14] pin */
+#define AFIO_EXTICR4_EXTI14_PG_Pos (9U)
+#define AFIO_EXTICR4_EXTI14_PG_Msk (0x3U << AFIO_EXTICR4_EXTI14_PG_Pos) /*!< 0x00000600 */
+#define AFIO_EXTICR4_EXTI14_PG AFIO_EXTICR4_EXTI14_PG_Msk /*!< PG[14] pin */
+
+/*!< EXTI15 configuration */
+#define AFIO_EXTICR4_EXTI15_PA ((uint32_t)0x00000000) /*!< PA[15] pin */
+#define AFIO_EXTICR4_EXTI15_PB_Pos (12U)
+#define AFIO_EXTICR4_EXTI15_PB_Msk (0x1U << AFIO_EXTICR4_EXTI15_PB_Pos) /*!< 0x00001000 */
+#define AFIO_EXTICR4_EXTI15_PB AFIO_EXTICR4_EXTI15_PB_Msk /*!< PB[15] pin */
+#define AFIO_EXTICR4_EXTI15_PC_Pos (13U)
+#define AFIO_EXTICR4_EXTI15_PC_Msk (0x1U << AFIO_EXTICR4_EXTI15_PC_Pos) /*!< 0x00002000 */
+#define AFIO_EXTICR4_EXTI15_PC AFIO_EXTICR4_EXTI15_PC_Msk /*!< PC[15] pin */
+#define AFIO_EXTICR4_EXTI15_PD_Pos (12U)
+#define AFIO_EXTICR4_EXTI15_PD_Msk (0x3U << AFIO_EXTICR4_EXTI15_PD_Pos) /*!< 0x00003000 */
+#define AFIO_EXTICR4_EXTI15_PD AFIO_EXTICR4_EXTI15_PD_Msk /*!< PD[15] pin */
+#define AFIO_EXTICR4_EXTI15_PE_Pos (14U)
+#define AFIO_EXTICR4_EXTI15_PE_Msk (0x1U << AFIO_EXTICR4_EXTI15_PE_Pos) /*!< 0x00004000 */
+#define AFIO_EXTICR4_EXTI15_PE AFIO_EXTICR4_EXTI15_PE_Msk /*!< PE[15] pin */
+#define AFIO_EXTICR4_EXTI15_PF_Pos (12U)
+#define AFIO_EXTICR4_EXTI15_PF_Msk (0x5U << AFIO_EXTICR4_EXTI15_PF_Pos) /*!< 0x00005000 */
+#define AFIO_EXTICR4_EXTI15_PF AFIO_EXTICR4_EXTI15_PF_Msk /*!< PF[15] pin */
+#define AFIO_EXTICR4_EXTI15_PG_Pos (13U)
+#define AFIO_EXTICR4_EXTI15_PG_Msk (0x3U << AFIO_EXTICR4_EXTI15_PG_Pos) /*!< 0x00006000 */
+#define AFIO_EXTICR4_EXTI15_PG AFIO_EXTICR4_EXTI15_PG_Msk /*!< PG[15] pin */
+
+/****************** Bit definition for AFIO_MAPR2 register ******************/
+
+
+#define AFIO_MAPR2_TIM9_REMAP_Pos (5U)
+#define AFIO_MAPR2_TIM9_REMAP_Msk (0x1U << AFIO_MAPR2_TIM9_REMAP_Pos) /*!< 0x00000020 */
+#define AFIO_MAPR2_TIM9_REMAP AFIO_MAPR2_TIM9_REMAP_Msk /*!< TIM9 remapping */
+#define AFIO_MAPR2_TIM10_REMAP_Pos (6U)
+#define AFIO_MAPR2_TIM10_REMAP_Msk (0x1U << AFIO_MAPR2_TIM10_REMAP_Pos) /*!< 0x00000040 */
+#define AFIO_MAPR2_TIM10_REMAP AFIO_MAPR2_TIM10_REMAP_Msk /*!< TIM10 remapping */
+#define AFIO_MAPR2_TIM11_REMAP_Pos (7U)
+#define AFIO_MAPR2_TIM11_REMAP_Msk (0x1U << AFIO_MAPR2_TIM11_REMAP_Pos) /*!< 0x00000080 */
+#define AFIO_MAPR2_TIM11_REMAP AFIO_MAPR2_TIM11_REMAP_Msk /*!< TIM11 remapping */
+#define AFIO_MAPR2_TIM13_REMAP_Pos (8U)
+#define AFIO_MAPR2_TIM13_REMAP_Msk (0x1U << AFIO_MAPR2_TIM13_REMAP_Pos) /*!< 0x00000100 */
+#define AFIO_MAPR2_TIM13_REMAP AFIO_MAPR2_TIM13_REMAP_Msk /*!< TIM13 remapping */
+#define AFIO_MAPR2_TIM14_REMAP_Pos (9U)
+#define AFIO_MAPR2_TIM14_REMAP_Msk (0x1U << AFIO_MAPR2_TIM14_REMAP_Pos) /*!< 0x00000200 */
+#define AFIO_MAPR2_TIM14_REMAP AFIO_MAPR2_TIM14_REMAP_Msk /*!< TIM14 remapping */
+#define AFIO_MAPR2_FSMC_NADV_REMAP_Pos (10U)
+#define AFIO_MAPR2_FSMC_NADV_REMAP_Msk (0x1U << AFIO_MAPR2_FSMC_NADV_REMAP_Pos) /*!< 0x00000400 */
+#define AFIO_MAPR2_FSMC_NADV_REMAP AFIO_MAPR2_FSMC_NADV_REMAP_Msk /*!< FSMC NADV remapping */
+
+/******************************************************************************/
+/* */
+/* SystemTick */
+/* */
+/******************************************************************************/
+
+/***************** Bit definition for SysTick_CTRL register *****************/
+#define SysTick_CTRL_ENABLE ((uint32_t)0x00000001) /*!< Counter enable */
+#define SysTick_CTRL_TICKINT ((uint32_t)0x00000002) /*!< Counting down to 0 pends the SysTick handler */
+#define SysTick_CTRL_CLKSOURCE ((uint32_t)0x00000004) /*!< Clock source */
+#define SysTick_CTRL_COUNTFLAG ((uint32_t)0x00010000) /*!< Count Flag */
+
+/***************** Bit definition for SysTick_LOAD register *****************/
+#define SysTick_LOAD_RELOAD ((uint32_t)0x00FFFFFF) /*!< Value to load into the SysTick Current Value Register when the counter reaches 0 */
+
+/***************** Bit definition for SysTick_VAL register ******************/
+#define SysTick_VAL_CURRENT ((uint32_t)0x00FFFFFF) /*!< Current value at the time the register is accessed */
+
+/***************** Bit definition for SysTick_CALIB register ****************/
+#define SysTick_CALIB_TENMS ((uint32_t)0x00FFFFFF) /*!< Reload value to use for 10ms timing */
+#define SysTick_CALIB_SKEW ((uint32_t)0x40000000) /*!< Calibration value is not exactly 10 ms */
+#define SysTick_CALIB_NOREF ((uint32_t)0x80000000) /*!< The reference clock is not provided */
+
+/******************************************************************************/
+/* */
+/* Nested Vectored Interrupt Controller */
+/* */
+/******************************************************************************/
+
+/****************** Bit definition for NVIC_ISER register *******************/
+#define NVIC_ISER_SETENA_Pos (0U)
+#define NVIC_ISER_SETENA_Msk (0xFFFFFFFFU << NVIC_ISER_SETENA_Pos) /*!< 0xFFFFFFFF */
+#define NVIC_ISER_SETENA NVIC_ISER_SETENA_Msk /*!< Interrupt set enable bits */
+#define NVIC_ISER_SETENA_0 (0x00000001U << NVIC_ISER_SETENA_Pos) /*!< 0x00000001 */
+#define NVIC_ISER_SETENA_1 (0x00000002U << NVIC_ISER_SETENA_Pos) /*!< 0x00000002 */
+#define NVIC_ISER_SETENA_2 (0x00000004U << NVIC_ISER_SETENA_Pos) /*!< 0x00000004 */
+#define NVIC_ISER_SETENA_3 (0x00000008U << NVIC_ISER_SETENA_Pos) /*!< 0x00000008 */
+#define NVIC_ISER_SETENA_4 (0x00000010U << NVIC_ISER_SETENA_Pos) /*!< 0x00000010 */
+#define NVIC_ISER_SETENA_5 (0x00000020U << NVIC_ISER_SETENA_Pos) /*!< 0x00000020 */
+#define NVIC_ISER_SETENA_6 (0x00000040U << NVIC_ISER_SETENA_Pos) /*!< 0x00000040 */
+#define NVIC_ISER_SETENA_7 (0x00000080U << NVIC_ISER_SETENA_Pos) /*!< 0x00000080 */
+#define NVIC_ISER_SETENA_8 (0x00000100U << NVIC_ISER_SETENA_Pos) /*!< 0x00000100 */
+#define NVIC_ISER_SETENA_9 (0x00000200U << NVIC_ISER_SETENA_Pos) /*!< 0x00000200 */
+#define NVIC_ISER_SETENA_10 (0x00000400U << NVIC_ISER_SETENA_Pos) /*!< 0x00000400 */
+#define NVIC_ISER_SETENA_11 (0x00000800U << NVIC_ISER_SETENA_Pos) /*!< 0x00000800 */
+#define NVIC_ISER_SETENA_12 (0x00001000U << NVIC_ISER_SETENA_Pos) /*!< 0x00001000 */
+#define NVIC_ISER_SETENA_13 (0x00002000U << NVIC_ISER_SETENA_Pos) /*!< 0x00002000 */
+#define NVIC_ISER_SETENA_14 (0x00004000U << NVIC_ISER_SETENA_Pos) /*!< 0x00004000 */
+#define NVIC_ISER_SETENA_15 (0x00008000U << NVIC_ISER_SETENA_Pos) /*!< 0x00008000 */
+#define NVIC_ISER_SETENA_16 (0x00010000U << NVIC_ISER_SETENA_Pos) /*!< 0x00010000 */
+#define NVIC_ISER_SETENA_17 (0x00020000U << NVIC_ISER_SETENA_Pos) /*!< 0x00020000 */
+#define NVIC_ISER_SETENA_18 (0x00040000U << NVIC_ISER_SETENA_Pos) /*!< 0x00040000 */
+#define NVIC_ISER_SETENA_19 (0x00080000U << NVIC_ISER_SETENA_Pos) /*!< 0x00080000 */
+#define NVIC_ISER_SETENA_20 (0x00100000U << NVIC_ISER_SETENA_Pos) /*!< 0x00100000 */
+#define NVIC_ISER_SETENA_21 (0x00200000U << NVIC_ISER_SETENA_Pos) /*!< 0x00200000 */
+#define NVIC_ISER_SETENA_22 (0x00400000U << NVIC_ISER_SETENA_Pos) /*!< 0x00400000 */
+#define NVIC_ISER_SETENA_23 (0x00800000U << NVIC_ISER_SETENA_Pos) /*!< 0x00800000 */
+#define NVIC_ISER_SETENA_24 (0x01000000U << NVIC_ISER_SETENA_Pos) /*!< 0x01000000 */
+#define NVIC_ISER_SETENA_25 (0x02000000U << NVIC_ISER_SETENA_Pos) /*!< 0x02000000 */
+#define NVIC_ISER_SETENA_26 (0x04000000U << NVIC_ISER_SETENA_Pos) /*!< 0x04000000 */
+#define NVIC_ISER_SETENA_27 (0x08000000U << NVIC_ISER_SETENA_Pos) /*!< 0x08000000 */
+#define NVIC_ISER_SETENA_28 (0x10000000U << NVIC_ISER_SETENA_Pos) /*!< 0x10000000 */
+#define NVIC_ISER_SETENA_29 (0x20000000U << NVIC_ISER_SETENA_Pos) /*!< 0x20000000 */
+#define NVIC_ISER_SETENA_30 (0x40000000U << NVIC_ISER_SETENA_Pos) /*!< 0x40000000 */
+#define NVIC_ISER_SETENA_31 (0x80000000U << NVIC_ISER_SETENA_Pos) /*!< 0x80000000 */
+
+/****************** Bit definition for NVIC_ICER register *******************/
+#define NVIC_ICER_CLRENA_Pos (0U)
+#define NVIC_ICER_CLRENA_Msk (0xFFFFFFFFU << NVIC_ICER_CLRENA_Pos) /*!< 0xFFFFFFFF */
+#define NVIC_ICER_CLRENA NVIC_ICER_CLRENA_Msk /*!< Interrupt clear-enable bits */
+#define NVIC_ICER_CLRENA_0 (0x00000001U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000001 */
+#define NVIC_ICER_CLRENA_1 (0x00000002U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000002 */
+#define NVIC_ICER_CLRENA_2 (0x00000004U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000004 */
+#define NVIC_ICER_CLRENA_3 (0x00000008U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000008 */
+#define NVIC_ICER_CLRENA_4 (0x00000010U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000010 */
+#define NVIC_ICER_CLRENA_5 (0x00000020U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000020 */
+#define NVIC_ICER_CLRENA_6 (0x00000040U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000040 */
+#define NVIC_ICER_CLRENA_7 (0x00000080U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000080 */
+#define NVIC_ICER_CLRENA_8 (0x00000100U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000100 */
+#define NVIC_ICER_CLRENA_9 (0x00000200U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000200 */
+#define NVIC_ICER_CLRENA_10 (0x00000400U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000400 */
+#define NVIC_ICER_CLRENA_11 (0x00000800U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000800 */
+#define NVIC_ICER_CLRENA_12 (0x00001000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00001000 */
+#define NVIC_ICER_CLRENA_13 (0x00002000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00002000 */
+#define NVIC_ICER_CLRENA_14 (0x00004000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00004000 */
+#define NVIC_ICER_CLRENA_15 (0x00008000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00008000 */
+#define NVIC_ICER_CLRENA_16 (0x00010000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00010000 */
+#define NVIC_ICER_CLRENA_17 (0x00020000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00020000 */
+#define NVIC_ICER_CLRENA_18 (0x00040000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00040000 */
+#define NVIC_ICER_CLRENA_19 (0x00080000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00080000 */
+#define NVIC_ICER_CLRENA_20 (0x00100000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00100000 */
+#define NVIC_ICER_CLRENA_21 (0x00200000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00200000 */
+#define NVIC_ICER_CLRENA_22 (0x00400000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00400000 */
+#define NVIC_ICER_CLRENA_23 (0x00800000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00800000 */
+#define NVIC_ICER_CLRENA_24 (0x01000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x01000000 */
+#define NVIC_ICER_CLRENA_25 (0x02000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x02000000 */
+#define NVIC_ICER_CLRENA_26 (0x04000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x04000000 */
+#define NVIC_ICER_CLRENA_27 (0x08000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x08000000 */
+#define NVIC_ICER_CLRENA_28 (0x10000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x10000000 */
+#define NVIC_ICER_CLRENA_29 (0x20000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x20000000 */
+#define NVIC_ICER_CLRENA_30 (0x40000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x40000000 */
+#define NVIC_ICER_CLRENA_31 (0x80000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x80000000 */
+
+/****************** Bit definition for NVIC_ISPR register *******************/
+#define NVIC_ISPR_SETPEND_Pos (0U)
+#define NVIC_ISPR_SETPEND_Msk (0xFFFFFFFFU << NVIC_ISPR_SETPEND_Pos) /*!< 0xFFFFFFFF */
+#define NVIC_ISPR_SETPEND NVIC_ISPR_SETPEND_Msk /*!< Interrupt set-pending bits */
+#define NVIC_ISPR_SETPEND_0 (0x00000001U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000001 */
+#define NVIC_ISPR_SETPEND_1 (0x00000002U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000002 */
+#define NVIC_ISPR_SETPEND_2 (0x00000004U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000004 */
+#define NVIC_ISPR_SETPEND_3 (0x00000008U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000008 */
+#define NVIC_ISPR_SETPEND_4 (0x00000010U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000010 */
+#define NVIC_ISPR_SETPEND_5 (0x00000020U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000020 */
+#define NVIC_ISPR_SETPEND_6 (0x00000040U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000040 */
+#define NVIC_ISPR_SETPEND_7 (0x00000080U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000080 */
+#define NVIC_ISPR_SETPEND_8 (0x00000100U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000100 */
+#define NVIC_ISPR_SETPEND_9 (0x00000200U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000200 */
+#define NVIC_ISPR_SETPEND_10 (0x00000400U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000400 */
+#define NVIC_ISPR_SETPEND_11 (0x00000800U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000800 */
+#define NVIC_ISPR_SETPEND_12 (0x00001000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00001000 */
+#define NVIC_ISPR_SETPEND_13 (0x00002000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00002000 */
+#define NVIC_ISPR_SETPEND_14 (0x00004000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00004000 */
+#define NVIC_ISPR_SETPEND_15 (0x00008000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00008000 */
+#define NVIC_ISPR_SETPEND_16 (0x00010000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00010000 */
+#define NVIC_ISPR_SETPEND_17 (0x00020000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00020000 */
+#define NVIC_ISPR_SETPEND_18 (0x00040000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00040000 */
+#define NVIC_ISPR_SETPEND_19 (0x00080000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00080000 */
+#define NVIC_ISPR_SETPEND_20 (0x00100000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00100000 */
+#define NVIC_ISPR_SETPEND_21 (0x00200000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00200000 */
+#define NVIC_ISPR_SETPEND_22 (0x00400000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00400000 */
+#define NVIC_ISPR_SETPEND_23 (0x00800000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00800000 */
+#define NVIC_ISPR_SETPEND_24 (0x01000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x01000000 */
+#define NVIC_ISPR_SETPEND_25 (0x02000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x02000000 */
+#define NVIC_ISPR_SETPEND_26 (0x04000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x04000000 */
+#define NVIC_ISPR_SETPEND_27 (0x08000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x08000000 */
+#define NVIC_ISPR_SETPEND_28 (0x10000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x10000000 */
+#define NVIC_ISPR_SETPEND_29 (0x20000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x20000000 */
+#define NVIC_ISPR_SETPEND_30 (0x40000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x40000000 */
+#define NVIC_ISPR_SETPEND_31 (0x80000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x80000000 */
+
+/****************** Bit definition for NVIC_ICPR register *******************/
+#define NVIC_ICPR_CLRPEND_Pos (0U)
+#define NVIC_ICPR_CLRPEND_Msk (0xFFFFFFFFU << NVIC_ICPR_CLRPEND_Pos) /*!< 0xFFFFFFFF */
+#define NVIC_ICPR_CLRPEND NVIC_ICPR_CLRPEND_Msk /*!< Interrupt clear-pending bits */
+#define NVIC_ICPR_CLRPEND_0 (0x00000001U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000001 */
+#define NVIC_ICPR_CLRPEND_1 (0x00000002U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000002 */
+#define NVIC_ICPR_CLRPEND_2 (0x00000004U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000004 */
+#define NVIC_ICPR_CLRPEND_3 (0x00000008U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000008 */
+#define NVIC_ICPR_CLRPEND_4 (0x00000010U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000010 */
+#define NVIC_ICPR_CLRPEND_5 (0x00000020U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000020 */
+#define NVIC_ICPR_CLRPEND_6 (0x00000040U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000040 */
+#define NVIC_ICPR_CLRPEND_7 (0x00000080U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000080 */
+#define NVIC_ICPR_CLRPEND_8 (0x00000100U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000100 */
+#define NVIC_ICPR_CLRPEND_9 (0x00000200U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000200 */
+#define NVIC_ICPR_CLRPEND_10 (0x00000400U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000400 */
+#define NVIC_ICPR_CLRPEND_11 (0x00000800U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000800 */
+#define NVIC_ICPR_CLRPEND_12 (0x00001000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00001000 */
+#define NVIC_ICPR_CLRPEND_13 (0x00002000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00002000 */
+#define NVIC_ICPR_CLRPEND_14 (0x00004000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00004000 */
+#define NVIC_ICPR_CLRPEND_15 (0x00008000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00008000 */
+#define NVIC_ICPR_CLRPEND_16 (0x00010000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00010000 */
+#define NVIC_ICPR_CLRPEND_17 (0x00020000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00020000 */
+#define NVIC_ICPR_CLRPEND_18 (0x00040000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00040000 */
+#define NVIC_ICPR_CLRPEND_19 (0x00080000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00080000 */
+#define NVIC_ICPR_CLRPEND_20 (0x00100000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00100000 */
+#define NVIC_ICPR_CLRPEND_21 (0x00200000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00200000 */
+#define NVIC_ICPR_CLRPEND_22 (0x00400000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00400000 */
+#define NVIC_ICPR_CLRPEND_23 (0x00800000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00800000 */
+#define NVIC_ICPR_CLRPEND_24 (0x01000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x01000000 */
+#define NVIC_ICPR_CLRPEND_25 (0x02000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x02000000 */
+#define NVIC_ICPR_CLRPEND_26 (0x04000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x04000000 */
+#define NVIC_ICPR_CLRPEND_27 (0x08000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x08000000 */
+#define NVIC_ICPR_CLRPEND_28 (0x10000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x10000000 */
+#define NVIC_ICPR_CLRPEND_29 (0x20000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x20000000 */
+#define NVIC_ICPR_CLRPEND_30 (0x40000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x40000000 */
+#define NVIC_ICPR_CLRPEND_31 (0x80000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x80000000 */
+
+/****************** Bit definition for NVIC_IABR register *******************/
+#define NVIC_IABR_ACTIVE_Pos (0U)
+#define NVIC_IABR_ACTIVE_Msk (0xFFFFFFFFU << NVIC_IABR_ACTIVE_Pos) /*!< 0xFFFFFFFF */
+#define NVIC_IABR_ACTIVE NVIC_IABR_ACTIVE_Msk /*!< Interrupt active flags */
+#define NVIC_IABR_ACTIVE_0 (0x00000001U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000001 */
+#define NVIC_IABR_ACTIVE_1 (0x00000002U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000002 */
+#define NVIC_IABR_ACTIVE_2 (0x00000004U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000004 */
+#define NVIC_IABR_ACTIVE_3 (0x00000008U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000008 */
+#define NVIC_IABR_ACTIVE_4 (0x00000010U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000010 */
+#define NVIC_IABR_ACTIVE_5 (0x00000020U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000020 */
+#define NVIC_IABR_ACTIVE_6 (0x00000040U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000040 */
+#define NVIC_IABR_ACTIVE_7 (0x00000080U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000080 */
+#define NVIC_IABR_ACTIVE_8 (0x00000100U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000100 */
+#define NVIC_IABR_ACTIVE_9 (0x00000200U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000200 */
+#define NVIC_IABR_ACTIVE_10 (0x00000400U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000400 */
+#define NVIC_IABR_ACTIVE_11 (0x00000800U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000800 */
+#define NVIC_IABR_ACTIVE_12 (0x00001000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00001000 */
+#define NVIC_IABR_ACTIVE_13 (0x00002000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00002000 */
+#define NVIC_IABR_ACTIVE_14 (0x00004000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00004000 */
+#define NVIC_IABR_ACTIVE_15 (0x00008000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00008000 */
+#define NVIC_IABR_ACTIVE_16 (0x00010000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00010000 */
+#define NVIC_IABR_ACTIVE_17 (0x00020000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00020000 */
+#define NVIC_IABR_ACTIVE_18 (0x00040000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00040000 */
+#define NVIC_IABR_ACTIVE_19 (0x00080000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00080000 */
+#define NVIC_IABR_ACTIVE_20 (0x00100000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00100000 */
+#define NVIC_IABR_ACTIVE_21 (0x00200000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00200000 */
+#define NVIC_IABR_ACTIVE_22 (0x00400000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00400000 */
+#define NVIC_IABR_ACTIVE_23 (0x00800000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00800000 */
+#define NVIC_IABR_ACTIVE_24 (0x01000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x01000000 */
+#define NVIC_IABR_ACTIVE_25 (0x02000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x02000000 */
+#define NVIC_IABR_ACTIVE_26 (0x04000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x04000000 */
+#define NVIC_IABR_ACTIVE_27 (0x08000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x08000000 */
+#define NVIC_IABR_ACTIVE_28 (0x10000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x10000000 */
+#define NVIC_IABR_ACTIVE_29 (0x20000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x20000000 */
+#define NVIC_IABR_ACTIVE_30 (0x40000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x40000000 */
+#define NVIC_IABR_ACTIVE_31 (0x80000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x80000000 */
+
+/****************** Bit definition for NVIC_PRI0 register *******************/
+#define NVIC_IPR0_PRI_0 ((uint32_t)0x000000FF) /*!< Priority of interrupt 0 */
+#define NVIC_IPR0_PRI_1 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 1 */
+#define NVIC_IPR0_PRI_2 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 2 */
+#define NVIC_IPR0_PRI_3 ((uint32_t)0xFF000000) /*!< Priority of interrupt 3 */
+
+/****************** Bit definition for NVIC_PRI1 register *******************/
+#define NVIC_IPR1_PRI_4 ((uint32_t)0x000000FF) /*!< Priority of interrupt 4 */
+#define NVIC_IPR1_PRI_5 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 5 */
+#define NVIC_IPR1_PRI_6 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 6 */
+#define NVIC_IPR1_PRI_7 ((uint32_t)0xFF000000) /*!< Priority of interrupt 7 */
+
+/****************** Bit definition for NVIC_PRI2 register *******************/
+#define NVIC_IPR2_PRI_8 ((uint32_t)0x000000FF) /*!< Priority of interrupt 8 */
+#define NVIC_IPR2_PRI_9 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 9 */
+#define NVIC_IPR2_PRI_10 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 10 */
+#define NVIC_IPR2_PRI_11 ((uint32_t)0xFF000000) /*!< Priority of interrupt 11 */
+
+/****************** Bit definition for NVIC_PRI3 register *******************/
+#define NVIC_IPR3_PRI_12 ((uint32_t)0x000000FF) /*!< Priority of interrupt 12 */
+#define NVIC_IPR3_PRI_13 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 13 */
+#define NVIC_IPR3_PRI_14 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 14 */
+#define NVIC_IPR3_PRI_15 ((uint32_t)0xFF000000) /*!< Priority of interrupt 15 */
+
+/****************** Bit definition for NVIC_PRI4 register *******************/
+#define NVIC_IPR4_PRI_16 ((uint32_t)0x000000FF) /*!< Priority of interrupt 16 */
+#define NVIC_IPR4_PRI_17 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 17 */
+#define NVIC_IPR4_PRI_18 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 18 */
+#define NVIC_IPR4_PRI_19 ((uint32_t)0xFF000000) /*!< Priority of interrupt 19 */
+
+/****************** Bit definition for NVIC_PRI5 register *******************/
+#define NVIC_IPR5_PRI_20 ((uint32_t)0x000000FF) /*!< Priority of interrupt 20 */
+#define NVIC_IPR5_PRI_21 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 21 */
+#define NVIC_IPR5_PRI_22 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 22 */
+#define NVIC_IPR5_PRI_23 ((uint32_t)0xFF000000) /*!< Priority of interrupt 23 */
+
+/****************** Bit definition for NVIC_PRI6 register *******************/
+#define NVIC_IPR6_PRI_24 ((uint32_t)0x000000FF) /*!< Priority of interrupt 24 */
+#define NVIC_IPR6_PRI_25 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 25 */
+#define NVIC_IPR6_PRI_26 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 26 */
+#define NVIC_IPR6_PRI_27 ((uint32_t)0xFF000000) /*!< Priority of interrupt 27 */
+
+/****************** Bit definition for NVIC_PRI7 register *******************/
+#define NVIC_IPR7_PRI_28 ((uint32_t)0x000000FF) /*!< Priority of interrupt 28 */
+#define NVIC_IPR7_PRI_29 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 29 */
+#define NVIC_IPR7_PRI_30 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 30 */
+#define NVIC_IPR7_PRI_31 ((uint32_t)0xFF000000) /*!< Priority of interrupt 31 */
+
+/****************** Bit definition for SCB_CPUID register *******************/
+#define SCB_CPUID_REVISION ((uint32_t)0x0000000F) /*!< Implementation defined revision number */
+#define SCB_CPUID_PARTNO ((uint32_t)0x0000FFF0) /*!< Number of processor within family */
+#define SCB_CPUID_Constant ((uint32_t)0x000F0000) /*!< Reads as 0x0F */
+#define SCB_CPUID_VARIANT ((uint32_t)0x00F00000) /*!< Implementation defined variant number */
+#define SCB_CPUID_IMPLEMENTER ((uint32_t)0xFF000000) /*!< Implementer code. ARM is 0x41 */
+
+/******************* Bit definition for SCB_ICSR register *******************/
+#define SCB_ICSR_VECTACTIVE ((uint32_t)0x000001FF) /*!< Active ISR number field */
+#define SCB_ICSR_RETTOBASE ((uint32_t)0x00000800) /*!< All active exceptions minus the IPSR_current_exception yields the empty set */
+#define SCB_ICSR_VECTPENDING ((uint32_t)0x003FF000) /*!< Pending ISR number field */
+#define SCB_ICSR_ISRPENDING ((uint32_t)0x00400000) /*!< Interrupt pending flag */
+#define SCB_ICSR_ISRPREEMPT ((uint32_t)0x00800000) /*!< It indicates that a pending interrupt becomes active in the next running cycle */
+#define SCB_ICSR_PENDSTCLR ((uint32_t)0x02000000) /*!< Clear pending SysTick bit */
+#define SCB_ICSR_PENDSTSET ((uint32_t)0x04000000) /*!< Set pending SysTick bit */
+#define SCB_ICSR_PENDSVCLR ((uint32_t)0x08000000) /*!< Clear pending pendSV bit */
+#define SCB_ICSR_PENDSVSET ((uint32_t)0x10000000) /*!< Set pending pendSV bit */
+#define SCB_ICSR_NMIPENDSET ((uint32_t)0x80000000) /*!< Set pending NMI bit */
+
+/******************* Bit definition for SCB_VTOR register *******************/
+#define SCB_VTOR_TBLOFF ((uint32_t)0x1FFFFF80) /*!< Vector table base offset field */
+#define SCB_VTOR_TBLBASE ((uint32_t)0x20000000) /*!< Table base in code(0) or RAM(1) */
+
+/*!<***************** Bit definition for SCB_AIRCR register *******************/
+#define SCB_AIRCR_VECTRESET ((uint32_t)0x00000001) /*!< System Reset bit */
+#define SCB_AIRCR_VECTCLRACTIVE ((uint32_t)0x00000002) /*!< Clear active vector bit */
+#define SCB_AIRCR_SYSRESETREQ ((uint32_t)0x00000004) /*!< Requests chip control logic to generate a reset */
+
+#define SCB_AIRCR_PRIGROUP ((uint32_t)0x00000700) /*!< PRIGROUP[2:0] bits (Priority group) */
+#define SCB_AIRCR_PRIGROUP_0 ((uint32_t)0x00000100) /*!< Bit 0 */
+#define SCB_AIRCR_PRIGROUP_1 ((uint32_t)0x00000200) /*!< Bit 1 */
+#define SCB_AIRCR_PRIGROUP_2 ((uint32_t)0x00000400) /*!< Bit 2 */
+
+/* prority group configuration */
+#define SCB_AIRCR_PRIGROUP0 ((uint32_t)0x00000000) /*!< Priority group=0 (7 bits of pre-emption priority, 1 bit of subpriority) */
+#define SCB_AIRCR_PRIGROUP1 ((uint32_t)0x00000100) /*!< Priority group=1 (6 bits of pre-emption priority, 2 bits of subpriority) */
+#define SCB_AIRCR_PRIGROUP2 ((uint32_t)0x00000200) /*!< Priority group=2 (5 bits of pre-emption priority, 3 bits of subpriority) */
+#define SCB_AIRCR_PRIGROUP3 ((uint32_t)0x00000300) /*!< Priority group=3 (4 bits of pre-emption priority, 4 bits of subpriority) */
+#define SCB_AIRCR_PRIGROUP4 ((uint32_t)0x00000400) /*!< Priority group=4 (3 bits of pre-emption priority, 5 bits of subpriority) */
+#define SCB_AIRCR_PRIGROUP5 ((uint32_t)0x00000500) /*!< Priority group=5 (2 bits of pre-emption priority, 6 bits of subpriority) */
+#define SCB_AIRCR_PRIGROUP6 ((uint32_t)0x00000600) /*!< Priority group=6 (1 bit of pre-emption priority, 7 bits of subpriority) */
+#define SCB_AIRCR_PRIGROUP7 ((uint32_t)0x00000700) /*!< Priority group=7 (no pre-emption priority, 8 bits of subpriority) */
+
+#define SCB_AIRCR_ENDIANESS ((uint32_t)0x00008000) /*!< Data endianness bit */
+#define SCB_AIRCR_VECTKEY ((uint32_t)0xFFFF0000) /*!< Register key (VECTKEY) - Reads as 0xFA05 (VECTKEYSTAT) */
+
+/******************* Bit definition for SCB_SCR register ********************/
+#define SCB_SCR_SLEEPONEXIT ((uint32_t)0x00000002) /*!< Sleep on exit bit */
+#define SCB_SCR_SLEEPDEEP ((uint32_t)0x00000004) /*!< Sleep deep bit */
+#define SCB_SCR_SEVONPEND ((uint32_t)0x00000010) /*!< Wake up from WFE */
+
+/******************** Bit definition for SCB_CCR register *******************/
+#define SCB_CCR_NONBASETHRDENA ((uint32_t)0x00000001) /*!< Thread mode can be entered from any level in Handler mode by controlled return value */
+#define SCB_CCR_USERSETMPEND ((uint32_t)0x00000002) /*!< Enables user code to write the Software Trigger Interrupt register to trigger (pend) a Main exception */
+#define SCB_CCR_UNALIGN_TRP ((uint32_t)0x00000008) /*!< Trap for unaligned access */
+#define SCB_CCR_DIV_0_TRP ((uint32_t)0x00000010) /*!< Trap on Divide by 0 */
+#define SCB_CCR_BFHFNMIGN ((uint32_t)0x00000100) /*!< Handlers running at priority -1 and -2 */
+#define SCB_CCR_STKALIGN ((uint32_t)0x00000200) /*!< On exception entry, the SP used prior to the exception is adjusted to be 8-byte aligned */
+
+/******************* Bit definition for SCB_SHPR register ********************/
+#define SCB_SHPR_PRI_N_Pos (0U)
+#define SCB_SHPR_PRI_N_Msk (0xFFU << SCB_SHPR_PRI_N_Pos) /*!< 0x000000FF */
+#define SCB_SHPR_PRI_N SCB_SHPR_PRI_N_Msk /*!< Priority of system handler 4,8, and 12. Mem Manage, reserved and Debug Monitor */
+#define SCB_SHPR_PRI_N1_Pos (8U)
+#define SCB_SHPR_PRI_N1_Msk (0xFFU << SCB_SHPR_PRI_N1_Pos) /*!< 0x0000FF00 */
+#define SCB_SHPR_PRI_N1 SCB_SHPR_PRI_N1_Msk /*!< Priority of system handler 5,9, and 13. Bus Fault, reserved and reserved */
+#define SCB_SHPR_PRI_N2_Pos (16U)
+#define SCB_SHPR_PRI_N2_Msk (0xFFU << SCB_SHPR_PRI_N2_Pos) /*!< 0x00FF0000 */
+#define SCB_SHPR_PRI_N2 SCB_SHPR_PRI_N2_Msk /*!< Priority of system handler 6,10, and 14. Usage Fault, reserved and PendSV */
+#define SCB_SHPR_PRI_N3_Pos (24U)
+#define SCB_SHPR_PRI_N3_Msk (0xFFU << SCB_SHPR_PRI_N3_Pos) /*!< 0xFF000000 */
+#define SCB_SHPR_PRI_N3 SCB_SHPR_PRI_N3_Msk /*!< Priority of system handler 7,11, and 15. Reserved, SVCall and SysTick */
+
+/****************** Bit definition for SCB_SHCSR register *******************/
+#define SCB_SHCSR_MEMFAULTACT ((uint32_t)0x00000001) /*!< MemManage is active */
+#define SCB_SHCSR_BUSFAULTACT ((uint32_t)0x00000002) /*!< BusFault is active */
+#define SCB_SHCSR_USGFAULTACT ((uint32_t)0x00000008) /*!< UsageFault is active */
+#define SCB_SHCSR_SVCALLACT ((uint32_t)0x00000080) /*!< SVCall is active */
+#define SCB_SHCSR_MONITORACT ((uint32_t)0x00000100) /*!< Monitor is active */
+#define SCB_SHCSR_PENDSVACT ((uint32_t)0x00000400) /*!< PendSV is active */
+#define SCB_SHCSR_SYSTICKACT ((uint32_t)0x00000800) /*!< SysTick is active */
+#define SCB_SHCSR_USGFAULTPENDED ((uint32_t)0x00001000) /*!< Usage Fault is pended */
+#define SCB_SHCSR_MEMFAULTPENDED ((uint32_t)0x00002000) /*!< MemManage is pended */
+#define SCB_SHCSR_BUSFAULTPENDED ((uint32_t)0x00004000) /*!< Bus Fault is pended */
+#define SCB_SHCSR_SVCALLPENDED ((uint32_t)0x00008000) /*!< SVCall is pended */
+#define SCB_SHCSR_MEMFAULTENA ((uint32_t)0x00010000) /*!< MemManage enable */
+#define SCB_SHCSR_BUSFAULTENA ((uint32_t)0x00020000) /*!< Bus Fault enable */
+#define SCB_SHCSR_USGFAULTENA ((uint32_t)0x00040000) /*!< UsageFault enable */
+
+/******************* Bit definition for SCB_CFSR register *******************/
+/*!< MFSR */
+#define SCB_CFSR_IACCVIOL_Pos (0U)
+#define SCB_CFSR_IACCVIOL_Msk (0x1U << SCB_CFSR_IACCVIOL_Pos) /*!< 0x00000001 */
+#define SCB_CFSR_IACCVIOL SCB_CFSR_IACCVIOL_Msk /*!< Instruction access violation */
+#define SCB_CFSR_DACCVIOL_Pos (1U)
+#define SCB_CFSR_DACCVIOL_Msk (0x1U << SCB_CFSR_DACCVIOL_Pos) /*!< 0x00000002 */
+#define SCB_CFSR_DACCVIOL SCB_CFSR_DACCVIOL_Msk /*!< Data access violation */
+#define SCB_CFSR_MUNSTKERR_Pos (3U)
+#define SCB_CFSR_MUNSTKERR_Msk (0x1U << SCB_CFSR_MUNSTKERR_Pos) /*!< 0x00000008 */
+#define SCB_CFSR_MUNSTKERR SCB_CFSR_MUNSTKERR_Msk /*!< Unstacking error */
+#define SCB_CFSR_MSTKERR_Pos (4U)
+#define SCB_CFSR_MSTKERR_Msk (0x1U << SCB_CFSR_MSTKERR_Pos) /*!< 0x00000010 */
+#define SCB_CFSR_MSTKERR SCB_CFSR_MSTKERR_Msk /*!< Stacking error */
+#define SCB_CFSR_MMARVALID_Pos (7U)
+#define SCB_CFSR_MMARVALID_Msk (0x1U << SCB_CFSR_MMARVALID_Pos) /*!< 0x00000080 */
+#define SCB_CFSR_MMARVALID SCB_CFSR_MMARVALID_Msk /*!< Memory Manage Address Register address valid flag */
+/*!< BFSR */
+#define SCB_CFSR_IBUSERR_Pos (8U)
+#define SCB_CFSR_IBUSERR_Msk (0x1U << SCB_CFSR_IBUSERR_Pos) /*!< 0x00000100 */
+#define SCB_CFSR_IBUSERR SCB_CFSR_IBUSERR_Msk /*!< Instruction bus error flag */
+#define SCB_CFSR_PRECISERR_Pos (9U)
+#define SCB_CFSR_PRECISERR_Msk (0x1U << SCB_CFSR_PRECISERR_Pos) /*!< 0x00000200 */
+#define SCB_CFSR_PRECISERR SCB_CFSR_PRECISERR_Msk /*!< Precise data bus error */
+#define SCB_CFSR_IMPRECISERR_Pos (10U)
+#define SCB_CFSR_IMPRECISERR_Msk (0x1U << SCB_CFSR_IMPRECISERR_Pos) /*!< 0x00000400 */
+#define SCB_CFSR_IMPRECISERR SCB_CFSR_IMPRECISERR_Msk /*!< Imprecise data bus error */
+#define SCB_CFSR_UNSTKERR_Pos (11U)
+#define SCB_CFSR_UNSTKERR_Msk (0x1U << SCB_CFSR_UNSTKERR_Pos) /*!< 0x00000800 */
+#define SCB_CFSR_UNSTKERR SCB_CFSR_UNSTKERR_Msk /*!< Unstacking error */
+#define SCB_CFSR_STKERR_Pos (12U)
+#define SCB_CFSR_STKERR_Msk (0x1U << SCB_CFSR_STKERR_Pos) /*!< 0x00001000 */
+#define SCB_CFSR_STKERR SCB_CFSR_STKERR_Msk /*!< Stacking error */
+#define SCB_CFSR_BFARVALID_Pos (15U)
+#define SCB_CFSR_BFARVALID_Msk (0x1U << SCB_CFSR_BFARVALID_Pos) /*!< 0x00008000 */
+#define SCB_CFSR_BFARVALID SCB_CFSR_BFARVALID_Msk /*!< Bus Fault Address Register address valid flag */
+/*!< UFSR */
+#define SCB_CFSR_UNDEFINSTR_Pos (16U)
+#define SCB_CFSR_UNDEFINSTR_Msk (0x1U << SCB_CFSR_UNDEFINSTR_Pos) /*!< 0x00010000 */
+#define SCB_CFSR_UNDEFINSTR SCB_CFSR_UNDEFINSTR_Msk /*!< The processor attempt to execute an undefined instruction */
+#define SCB_CFSR_INVSTATE_Pos (17U)
+#define SCB_CFSR_INVSTATE_Msk (0x1U << SCB_CFSR_INVSTATE_Pos) /*!< 0x00020000 */
+#define SCB_CFSR_INVSTATE SCB_CFSR_INVSTATE_Msk /*!< Invalid combination of EPSR and instruction */
+#define SCB_CFSR_INVPC_Pos (18U)
+#define SCB_CFSR_INVPC_Msk (0x1U << SCB_CFSR_INVPC_Pos) /*!< 0x00040000 */
+#define SCB_CFSR_INVPC SCB_CFSR_INVPC_Msk /*!< Attempt to load EXC_RETURN into pc illegally */
+#define SCB_CFSR_NOCP_Pos (19U)
+#define SCB_CFSR_NOCP_Msk (0x1U << SCB_CFSR_NOCP_Pos) /*!< 0x00080000 */
+#define SCB_CFSR_NOCP SCB_CFSR_NOCP_Msk /*!< Attempt to use a coprocessor instruction */
+#define SCB_CFSR_UNALIGNED_Pos (24U)
+#define SCB_CFSR_UNALIGNED_Msk (0x1U << SCB_CFSR_UNALIGNED_Pos) /*!< 0x01000000 */
+#define SCB_CFSR_UNALIGNED SCB_CFSR_UNALIGNED_Msk /*!< Fault occurs when there is an attempt to make an unaligned memory access */
+#define SCB_CFSR_DIVBYZERO_Pos (25U)
+#define SCB_CFSR_DIVBYZERO_Msk (0x1U << SCB_CFSR_DIVBYZERO_Pos) /*!< 0x02000000 */
+#define SCB_CFSR_DIVBYZERO SCB_CFSR_DIVBYZERO_Msk /*!< Fault occurs when SDIV or DIV instruction is used with a divisor of 0 */
+
+/******************* Bit definition for SCB_HFSR register *******************/
+#define SCB_HFSR_VECTTBL ((uint32_t)0x00000002) /*!< Fault occurs because of vector table read on exception processing */
+#define SCB_HFSR_FORCED ((uint32_t)0x40000000) /*!< Hard Fault activated when a configurable Fault was received and cannot activate */
+#define SCB_HFSR_DEBUGEVT ((uint32_t)0x80000000) /*!< Fault related to debug */
+
+/******************* Bit definition for SCB_DFSR register *******************/
+#define SCB_DFSR_HALTED ((uint32_t)0x00000001) /*!< Halt request flag */
+#define SCB_DFSR_BKPT ((uint32_t)0x00000002) /*!< BKPT flag */
+#define SCB_DFSR_DWTTRAP ((uint32_t)0x00000004) /*!< Data Watchpoint and Trace (DWT) flag */
+#define SCB_DFSR_VCATCH ((uint32_t)0x00000008) /*!< Vector catch flag */
+#define SCB_DFSR_EXTERNAL ((uint32_t)0x00000010) /*!< External debug request flag */
+
+/******************* Bit definition for SCB_MMFAR register ******************/
+#define SCB_MMFAR_ADDRESS_Pos (0U)
+#define SCB_MMFAR_ADDRESS_Msk (0xFFFFFFFFU << SCB_MMFAR_ADDRESS_Pos) /*!< 0xFFFFFFFF */
+#define SCB_MMFAR_ADDRESS SCB_MMFAR_ADDRESS_Msk /*!< Mem Manage fault address field */
+
+/******************* Bit definition for SCB_BFAR register *******************/
+#define SCB_BFAR_ADDRESS_Pos (0U)
+#define SCB_BFAR_ADDRESS_Msk (0xFFFFFFFFU << SCB_BFAR_ADDRESS_Pos) /*!< 0xFFFFFFFF */
+#define SCB_BFAR_ADDRESS SCB_BFAR_ADDRESS_Msk /*!< Bus fault address field */
+
+/******************* Bit definition for SCB_afsr register *******************/
+#define SCB_AFSR_IMPDEF_Pos (0U)
+#define SCB_AFSR_IMPDEF_Msk (0xFFFFFFFFU << SCB_AFSR_IMPDEF_Pos) /*!< 0xFFFFFFFF */
+#define SCB_AFSR_IMPDEF SCB_AFSR_IMPDEF_Msk /*!< Implementation defined */
+
+/******************************************************************************/
+/* */
+/* External Interrupt/Event Controller */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for EXTI_IMR register *******************/
+#define EXTI_IMR_MR0_Pos (0U)
+#define EXTI_IMR_MR0_Msk (0x1U << EXTI_IMR_MR0_Pos) /*!< 0x00000001 */
+#define EXTI_IMR_MR0 EXTI_IMR_MR0_Msk /*!< Interrupt Mask on line 0 */
+#define EXTI_IMR_MR1_Pos (1U)
+#define EXTI_IMR_MR1_Msk (0x1U << EXTI_IMR_MR1_Pos) /*!< 0x00000002 */
+#define EXTI_IMR_MR1 EXTI_IMR_MR1_Msk /*!< Interrupt Mask on line 1 */
+#define EXTI_IMR_MR2_Pos (2U)
+#define EXTI_IMR_MR2_Msk (0x1U << EXTI_IMR_MR2_Pos) /*!< 0x00000004 */
+#define EXTI_IMR_MR2 EXTI_IMR_MR2_Msk /*!< Interrupt Mask on line 2 */
+#define EXTI_IMR_MR3_Pos (3U)
+#define EXTI_IMR_MR3_Msk (0x1U << EXTI_IMR_MR3_Pos) /*!< 0x00000008 */
+#define EXTI_IMR_MR3 EXTI_IMR_MR3_Msk /*!< Interrupt Mask on line 3 */
+#define EXTI_IMR_MR4_Pos (4U)
+#define EXTI_IMR_MR4_Msk (0x1U << EXTI_IMR_MR4_Pos) /*!< 0x00000010 */
+#define EXTI_IMR_MR4 EXTI_IMR_MR4_Msk /*!< Interrupt Mask on line 4 */
+#define EXTI_IMR_MR5_Pos (5U)
+#define EXTI_IMR_MR5_Msk (0x1U << EXTI_IMR_MR5_Pos) /*!< 0x00000020 */
+#define EXTI_IMR_MR5 EXTI_IMR_MR5_Msk /*!< Interrupt Mask on line 5 */
+#define EXTI_IMR_MR6_Pos (6U)
+#define EXTI_IMR_MR6_Msk (0x1U << EXTI_IMR_MR6_Pos) /*!< 0x00000040 */
+#define EXTI_IMR_MR6 EXTI_IMR_MR6_Msk /*!< Interrupt Mask on line 6 */
+#define EXTI_IMR_MR7_Pos (7U)
+#define EXTI_IMR_MR7_Msk (0x1U << EXTI_IMR_MR7_Pos) /*!< 0x00000080 */
+#define EXTI_IMR_MR7 EXTI_IMR_MR7_Msk /*!< Interrupt Mask on line 7 */
+#define EXTI_IMR_MR8_Pos (8U)
+#define EXTI_IMR_MR8_Msk (0x1U << EXTI_IMR_MR8_Pos) /*!< 0x00000100 */
+#define EXTI_IMR_MR8 EXTI_IMR_MR8_Msk /*!< Interrupt Mask on line 8 */
+#define EXTI_IMR_MR9_Pos (9U)
+#define EXTI_IMR_MR9_Msk (0x1U << EXTI_IMR_MR9_Pos) /*!< 0x00000200 */
+#define EXTI_IMR_MR9 EXTI_IMR_MR9_Msk /*!< Interrupt Mask on line 9 */
+#define EXTI_IMR_MR10_Pos (10U)
+#define EXTI_IMR_MR10_Msk (0x1U << EXTI_IMR_MR10_Pos) /*!< 0x00000400 */
+#define EXTI_IMR_MR10 EXTI_IMR_MR10_Msk /*!< Interrupt Mask on line 10 */
+#define EXTI_IMR_MR11_Pos (11U)
+#define EXTI_IMR_MR11_Msk (0x1U << EXTI_IMR_MR11_Pos) /*!< 0x00000800 */
+#define EXTI_IMR_MR11 EXTI_IMR_MR11_Msk /*!< Interrupt Mask on line 11 */
+#define EXTI_IMR_MR12_Pos (12U)
+#define EXTI_IMR_MR12_Msk (0x1U << EXTI_IMR_MR12_Pos) /*!< 0x00001000 */
+#define EXTI_IMR_MR12 EXTI_IMR_MR12_Msk /*!< Interrupt Mask on line 12 */
+#define EXTI_IMR_MR13_Pos (13U)
+#define EXTI_IMR_MR13_Msk (0x1U << EXTI_IMR_MR13_Pos) /*!< 0x00002000 */
+#define EXTI_IMR_MR13 EXTI_IMR_MR13_Msk /*!< Interrupt Mask on line 13 */
+#define EXTI_IMR_MR14_Pos (14U)
+#define EXTI_IMR_MR14_Msk (0x1U << EXTI_IMR_MR14_Pos) /*!< 0x00004000 */
+#define EXTI_IMR_MR14 EXTI_IMR_MR14_Msk /*!< Interrupt Mask on line 14 */
+#define EXTI_IMR_MR15_Pos (15U)
+#define EXTI_IMR_MR15_Msk (0x1U << EXTI_IMR_MR15_Pos) /*!< 0x00008000 */
+#define EXTI_IMR_MR15 EXTI_IMR_MR15_Msk /*!< Interrupt Mask on line 15 */
+#define EXTI_IMR_MR16_Pos (16U)
+#define EXTI_IMR_MR16_Msk (0x1U << EXTI_IMR_MR16_Pos) /*!< 0x00010000 */
+#define EXTI_IMR_MR16 EXTI_IMR_MR16_Msk /*!< Interrupt Mask on line 16 */
+#define EXTI_IMR_MR17_Pos (17U)
+#define EXTI_IMR_MR17_Msk (0x1U << EXTI_IMR_MR17_Pos) /*!< 0x00020000 */
+#define EXTI_IMR_MR17 EXTI_IMR_MR17_Msk /*!< Interrupt Mask on line 17 */
+#define EXTI_IMR_MR18_Pos (18U)
+#define EXTI_IMR_MR18_Msk (0x1U << EXTI_IMR_MR18_Pos) /*!< 0x00040000 */
+#define EXTI_IMR_MR18 EXTI_IMR_MR18_Msk /*!< Interrupt Mask on line 18 */
+#define EXTI_IMR_MR19_Pos (19U)
+#define EXTI_IMR_MR19_Msk (0x1U << EXTI_IMR_MR19_Pos) /*!< 0x00080000 */
+#define EXTI_IMR_MR19 EXTI_IMR_MR19_Msk /*!< Interrupt Mask on line 19 */
+
+/* References Defines */
+#define EXTI_IMR_IM0 EXTI_IMR_MR0
+#define EXTI_IMR_IM1 EXTI_IMR_MR1
+#define EXTI_IMR_IM2 EXTI_IMR_MR2
+#define EXTI_IMR_IM3 EXTI_IMR_MR3
+#define EXTI_IMR_IM4 EXTI_IMR_MR4
+#define EXTI_IMR_IM5 EXTI_IMR_MR5
+#define EXTI_IMR_IM6 EXTI_IMR_MR6
+#define EXTI_IMR_IM7 EXTI_IMR_MR7
+#define EXTI_IMR_IM8 EXTI_IMR_MR8
+#define EXTI_IMR_IM9 EXTI_IMR_MR9
+#define EXTI_IMR_IM10 EXTI_IMR_MR10
+#define EXTI_IMR_IM11 EXTI_IMR_MR11
+#define EXTI_IMR_IM12 EXTI_IMR_MR12
+#define EXTI_IMR_IM13 EXTI_IMR_MR13
+#define EXTI_IMR_IM14 EXTI_IMR_MR14
+#define EXTI_IMR_IM15 EXTI_IMR_MR15
+#define EXTI_IMR_IM16 EXTI_IMR_MR16
+#define EXTI_IMR_IM17 EXTI_IMR_MR17
+#define EXTI_IMR_IM18 EXTI_IMR_MR18
+#define EXTI_IMR_IM19 EXTI_IMR_MR19
+
+/******************* Bit definition for EXTI_EMR register *******************/
+#define EXTI_EMR_MR0_Pos (0U)
+#define EXTI_EMR_MR0_Msk (0x1U << EXTI_EMR_MR0_Pos) /*!< 0x00000001 */
+#define EXTI_EMR_MR0 EXTI_EMR_MR0_Msk /*!< Event Mask on line 0 */
+#define EXTI_EMR_MR1_Pos (1U)
+#define EXTI_EMR_MR1_Msk (0x1U << EXTI_EMR_MR1_Pos) /*!< 0x00000002 */
+#define EXTI_EMR_MR1 EXTI_EMR_MR1_Msk /*!< Event Mask on line 1 */
+#define EXTI_EMR_MR2_Pos (2U)
+#define EXTI_EMR_MR2_Msk (0x1U << EXTI_EMR_MR2_Pos) /*!< 0x00000004 */
+#define EXTI_EMR_MR2 EXTI_EMR_MR2_Msk /*!< Event Mask on line 2 */
+#define EXTI_EMR_MR3_Pos (3U)
+#define EXTI_EMR_MR3_Msk (0x1U << EXTI_EMR_MR3_Pos) /*!< 0x00000008 */
+#define EXTI_EMR_MR3 EXTI_EMR_MR3_Msk /*!< Event Mask on line 3 */
+#define EXTI_EMR_MR4_Pos (4U)
+#define EXTI_EMR_MR4_Msk (0x1U << EXTI_EMR_MR4_Pos) /*!< 0x00000010 */
+#define EXTI_EMR_MR4 EXTI_EMR_MR4_Msk /*!< Event Mask on line 4 */
+#define EXTI_EMR_MR5_Pos (5U)
+#define EXTI_EMR_MR5_Msk (0x1U << EXTI_EMR_MR5_Pos) /*!< 0x00000020 */
+#define EXTI_EMR_MR5 EXTI_EMR_MR5_Msk /*!< Event Mask on line 5 */
+#define EXTI_EMR_MR6_Pos (6U)
+#define EXTI_EMR_MR6_Msk (0x1U << EXTI_EMR_MR6_Pos) /*!< 0x00000040 */
+#define EXTI_EMR_MR6 EXTI_EMR_MR6_Msk /*!< Event Mask on line 6 */
+#define EXTI_EMR_MR7_Pos (7U)
+#define EXTI_EMR_MR7_Msk (0x1U << EXTI_EMR_MR7_Pos) /*!< 0x00000080 */
+#define EXTI_EMR_MR7 EXTI_EMR_MR7_Msk /*!< Event Mask on line 7 */
+#define EXTI_EMR_MR8_Pos (8U)
+#define EXTI_EMR_MR8_Msk (0x1U << EXTI_EMR_MR8_Pos) /*!< 0x00000100 */
+#define EXTI_EMR_MR8 EXTI_EMR_MR8_Msk /*!< Event Mask on line 8 */
+#define EXTI_EMR_MR9_Pos (9U)
+#define EXTI_EMR_MR9_Msk (0x1U << EXTI_EMR_MR9_Pos) /*!< 0x00000200 */
+#define EXTI_EMR_MR9 EXTI_EMR_MR9_Msk /*!< Event Mask on line 9 */
+#define EXTI_EMR_MR10_Pos (10U)
+#define EXTI_EMR_MR10_Msk (0x1U << EXTI_EMR_MR10_Pos) /*!< 0x00000400 */
+#define EXTI_EMR_MR10 EXTI_EMR_MR10_Msk /*!< Event Mask on line 10 */
+#define EXTI_EMR_MR11_Pos (11U)
+#define EXTI_EMR_MR11_Msk (0x1U << EXTI_EMR_MR11_Pos) /*!< 0x00000800 */
+#define EXTI_EMR_MR11 EXTI_EMR_MR11_Msk /*!< Event Mask on line 11 */
+#define EXTI_EMR_MR12_Pos (12U)
+#define EXTI_EMR_MR12_Msk (0x1U << EXTI_EMR_MR12_Pos) /*!< 0x00001000 */
+#define EXTI_EMR_MR12 EXTI_EMR_MR12_Msk /*!< Event Mask on line 12 */
+#define EXTI_EMR_MR13_Pos (13U)
+#define EXTI_EMR_MR13_Msk (0x1U << EXTI_EMR_MR13_Pos) /*!< 0x00002000 */
+#define EXTI_EMR_MR13 EXTI_EMR_MR13_Msk /*!< Event Mask on line 13 */
+#define EXTI_EMR_MR14_Pos (14U)
+#define EXTI_EMR_MR14_Msk (0x1U << EXTI_EMR_MR14_Pos) /*!< 0x00004000 */
+#define EXTI_EMR_MR14 EXTI_EMR_MR14_Msk /*!< Event Mask on line 14 */
+#define EXTI_EMR_MR15_Pos (15U)
+#define EXTI_EMR_MR15_Msk (0x1U << EXTI_EMR_MR15_Pos) /*!< 0x00008000 */
+#define EXTI_EMR_MR15 EXTI_EMR_MR15_Msk /*!< Event Mask on line 15 */
+#define EXTI_EMR_MR16_Pos (16U)
+#define EXTI_EMR_MR16_Msk (0x1U << EXTI_EMR_MR16_Pos) /*!< 0x00010000 */
+#define EXTI_EMR_MR16 EXTI_EMR_MR16_Msk /*!< Event Mask on line 16 */
+#define EXTI_EMR_MR17_Pos (17U)
+#define EXTI_EMR_MR17_Msk (0x1U << EXTI_EMR_MR17_Pos) /*!< 0x00020000 */
+#define EXTI_EMR_MR17 EXTI_EMR_MR17_Msk /*!< Event Mask on line 17 */
+#define EXTI_EMR_MR18_Pos (18U)
+#define EXTI_EMR_MR18_Msk (0x1U << EXTI_EMR_MR18_Pos) /*!< 0x00040000 */
+#define EXTI_EMR_MR18 EXTI_EMR_MR18_Msk /*!< Event Mask on line 18 */
+#define EXTI_EMR_MR19_Pos (19U)
+#define EXTI_EMR_MR19_Msk (0x1U << EXTI_EMR_MR19_Pos) /*!< 0x00080000 */
+#define EXTI_EMR_MR19 EXTI_EMR_MR19_Msk /*!< Event Mask on line 19 */
+
+/* References Defines */
+#define EXTI_EMR_EM0 EXTI_EMR_MR0
+#define EXTI_EMR_EM1 EXTI_EMR_MR1
+#define EXTI_EMR_EM2 EXTI_EMR_MR2
+#define EXTI_EMR_EM3 EXTI_EMR_MR3
+#define EXTI_EMR_EM4 EXTI_EMR_MR4
+#define EXTI_EMR_EM5 EXTI_EMR_MR5
+#define EXTI_EMR_EM6 EXTI_EMR_MR6
+#define EXTI_EMR_EM7 EXTI_EMR_MR7
+#define EXTI_EMR_EM8 EXTI_EMR_MR8
+#define EXTI_EMR_EM9 EXTI_EMR_MR9
+#define EXTI_EMR_EM10 EXTI_EMR_MR10
+#define EXTI_EMR_EM11 EXTI_EMR_MR11
+#define EXTI_EMR_EM12 EXTI_EMR_MR12
+#define EXTI_EMR_EM13 EXTI_EMR_MR13
+#define EXTI_EMR_EM14 EXTI_EMR_MR14
+#define EXTI_EMR_EM15 EXTI_EMR_MR15
+#define EXTI_EMR_EM16 EXTI_EMR_MR16
+#define EXTI_EMR_EM17 EXTI_EMR_MR17
+#define EXTI_EMR_EM18 EXTI_EMR_MR18
+#define EXTI_EMR_EM19 EXTI_EMR_MR19
+
+/****************** Bit definition for EXTI_RTSR register *******************/
+#define EXTI_RTSR_TR0_Pos (0U)
+#define EXTI_RTSR_TR0_Msk (0x1U << EXTI_RTSR_TR0_Pos) /*!< 0x00000001 */
+#define EXTI_RTSR_TR0 EXTI_RTSR_TR0_Msk /*!< Rising trigger event configuration bit of line 0 */
+#define EXTI_RTSR_TR1_Pos (1U)
+#define EXTI_RTSR_TR1_Msk (0x1U << EXTI_RTSR_TR1_Pos) /*!< 0x00000002 */
+#define EXTI_RTSR_TR1 EXTI_RTSR_TR1_Msk /*!< Rising trigger event configuration bit of line 1 */
+#define EXTI_RTSR_TR2_Pos (2U)
+#define EXTI_RTSR_TR2_Msk (0x1U << EXTI_RTSR_TR2_Pos) /*!< 0x00000004 */
+#define EXTI_RTSR_TR2 EXTI_RTSR_TR2_Msk /*!< Rising trigger event configuration bit of line 2 */
+#define EXTI_RTSR_TR3_Pos (3U)
+#define EXTI_RTSR_TR3_Msk (0x1U << EXTI_RTSR_TR3_Pos) /*!< 0x00000008 */
+#define EXTI_RTSR_TR3 EXTI_RTSR_TR3_Msk /*!< Rising trigger event configuration bit of line 3 */
+#define EXTI_RTSR_TR4_Pos (4U)
+#define EXTI_RTSR_TR4_Msk (0x1U << EXTI_RTSR_TR4_Pos) /*!< 0x00000010 */
+#define EXTI_RTSR_TR4 EXTI_RTSR_TR4_Msk /*!< Rising trigger event configuration bit of line 4 */
+#define EXTI_RTSR_TR5_Pos (5U)
+#define EXTI_RTSR_TR5_Msk (0x1U << EXTI_RTSR_TR5_Pos) /*!< 0x00000020 */
+#define EXTI_RTSR_TR5 EXTI_RTSR_TR5_Msk /*!< Rising trigger event configuration bit of line 5 */
+#define EXTI_RTSR_TR6_Pos (6U)
+#define EXTI_RTSR_TR6_Msk (0x1U << EXTI_RTSR_TR6_Pos) /*!< 0x00000040 */
+#define EXTI_RTSR_TR6 EXTI_RTSR_TR6_Msk /*!< Rising trigger event configuration bit of line 6 */
+#define EXTI_RTSR_TR7_Pos (7U)
+#define EXTI_RTSR_TR7_Msk (0x1U << EXTI_RTSR_TR7_Pos) /*!< 0x00000080 */
+#define EXTI_RTSR_TR7 EXTI_RTSR_TR7_Msk /*!< Rising trigger event configuration bit of line 7 */
+#define EXTI_RTSR_TR8_Pos (8U)
+#define EXTI_RTSR_TR8_Msk (0x1U << EXTI_RTSR_TR8_Pos) /*!< 0x00000100 */
+#define EXTI_RTSR_TR8 EXTI_RTSR_TR8_Msk /*!< Rising trigger event configuration bit of line 8 */
+#define EXTI_RTSR_TR9_Pos (9U)
+#define EXTI_RTSR_TR9_Msk (0x1U << EXTI_RTSR_TR9_Pos) /*!< 0x00000200 */
+#define EXTI_RTSR_TR9 EXTI_RTSR_TR9_Msk /*!< Rising trigger event configuration bit of line 9 */
+#define EXTI_RTSR_TR10_Pos (10U)
+#define EXTI_RTSR_TR10_Msk (0x1U << EXTI_RTSR_TR10_Pos) /*!< 0x00000400 */
+#define EXTI_RTSR_TR10 EXTI_RTSR_TR10_Msk /*!< Rising trigger event configuration bit of line 10 */
+#define EXTI_RTSR_TR11_Pos (11U)
+#define EXTI_RTSR_TR11_Msk (0x1U << EXTI_RTSR_TR11_Pos) /*!< 0x00000800 */
+#define EXTI_RTSR_TR11 EXTI_RTSR_TR11_Msk /*!< Rising trigger event configuration bit of line 11 */
+#define EXTI_RTSR_TR12_Pos (12U)
+#define EXTI_RTSR_TR12_Msk (0x1U << EXTI_RTSR_TR12_Pos) /*!< 0x00001000 */
+#define EXTI_RTSR_TR12 EXTI_RTSR_TR12_Msk /*!< Rising trigger event configuration bit of line 12 */
+#define EXTI_RTSR_TR13_Pos (13U)
+#define EXTI_RTSR_TR13_Msk (0x1U << EXTI_RTSR_TR13_Pos) /*!< 0x00002000 */
+#define EXTI_RTSR_TR13 EXTI_RTSR_TR13_Msk /*!< Rising trigger event configuration bit of line 13 */
+#define EXTI_RTSR_TR14_Pos (14U)
+#define EXTI_RTSR_TR14_Msk (0x1U << EXTI_RTSR_TR14_Pos) /*!< 0x00004000 */
+#define EXTI_RTSR_TR14 EXTI_RTSR_TR14_Msk /*!< Rising trigger event configuration bit of line 14 */
+#define EXTI_RTSR_TR15_Pos (15U)
+#define EXTI_RTSR_TR15_Msk (0x1U << EXTI_RTSR_TR15_Pos) /*!< 0x00008000 */
+#define EXTI_RTSR_TR15 EXTI_RTSR_TR15_Msk /*!< Rising trigger event configuration bit of line 15 */
+#define EXTI_RTSR_TR16_Pos (16U)
+#define EXTI_RTSR_TR16_Msk (0x1U << EXTI_RTSR_TR16_Pos) /*!< 0x00010000 */
+#define EXTI_RTSR_TR16 EXTI_RTSR_TR16_Msk /*!< Rising trigger event configuration bit of line 16 */
+#define EXTI_RTSR_TR17_Pos (17U)
+#define EXTI_RTSR_TR17_Msk (0x1U << EXTI_RTSR_TR17_Pos) /*!< 0x00020000 */
+#define EXTI_RTSR_TR17 EXTI_RTSR_TR17_Msk /*!< Rising trigger event configuration bit of line 17 */
+#define EXTI_RTSR_TR18_Pos (18U)
+#define EXTI_RTSR_TR18_Msk (0x1U << EXTI_RTSR_TR18_Pos) /*!< 0x00040000 */
+#define EXTI_RTSR_TR18 EXTI_RTSR_TR18_Msk /*!< Rising trigger event configuration bit of line 18 */
+#define EXTI_RTSR_TR19_Pos (19U)
+#define EXTI_RTSR_TR19_Msk (0x1U << EXTI_RTSR_TR19_Pos) /*!< 0x00080000 */
+#define EXTI_RTSR_TR19 EXTI_RTSR_TR19_Msk /*!< Rising trigger event configuration bit of line 19 */
+
+/* References Defines */
+#define EXTI_RTSR_RT0 EXTI_RTSR_TR0
+#define EXTI_RTSR_RT1 EXTI_RTSR_TR1
+#define EXTI_RTSR_RT2 EXTI_RTSR_TR2
+#define EXTI_RTSR_RT3 EXTI_RTSR_TR3
+#define EXTI_RTSR_RT4 EXTI_RTSR_TR4
+#define EXTI_RTSR_RT5 EXTI_RTSR_TR5
+#define EXTI_RTSR_RT6 EXTI_RTSR_TR6
+#define EXTI_RTSR_RT7 EXTI_RTSR_TR7
+#define EXTI_RTSR_RT8 EXTI_RTSR_TR8
+#define EXTI_RTSR_RT9 EXTI_RTSR_TR9
+#define EXTI_RTSR_RT10 EXTI_RTSR_TR10
+#define EXTI_RTSR_RT11 EXTI_RTSR_TR11
+#define EXTI_RTSR_RT12 EXTI_RTSR_TR12
+#define EXTI_RTSR_RT13 EXTI_RTSR_TR13
+#define EXTI_RTSR_RT14 EXTI_RTSR_TR14
+#define EXTI_RTSR_RT15 EXTI_RTSR_TR15
+#define EXTI_RTSR_RT16 EXTI_RTSR_TR16
+#define EXTI_RTSR_RT17 EXTI_RTSR_TR17
+#define EXTI_RTSR_RT18 EXTI_RTSR_TR18
+#define EXTI_RTSR_RT19 EXTI_RTSR_TR19
+
+/****************** Bit definition for EXTI_FTSR register *******************/
+#define EXTI_FTSR_TR0_Pos (0U)
+#define EXTI_FTSR_TR0_Msk (0x1U << EXTI_FTSR_TR0_Pos) /*!< 0x00000001 */
+#define EXTI_FTSR_TR0 EXTI_FTSR_TR0_Msk /*!< Falling trigger event configuration bit of line 0 */
+#define EXTI_FTSR_TR1_Pos (1U)
+#define EXTI_FTSR_TR1_Msk (0x1U << EXTI_FTSR_TR1_Pos) /*!< 0x00000002 */
+#define EXTI_FTSR_TR1 EXTI_FTSR_TR1_Msk /*!< Falling trigger event configuration bit of line 1 */
+#define EXTI_FTSR_TR2_Pos (2U)
+#define EXTI_FTSR_TR2_Msk (0x1U << EXTI_FTSR_TR2_Pos) /*!< 0x00000004 */
+#define EXTI_FTSR_TR2 EXTI_FTSR_TR2_Msk /*!< Falling trigger event configuration bit of line 2 */
+#define EXTI_FTSR_TR3_Pos (3U)
+#define EXTI_FTSR_TR3_Msk (0x1U << EXTI_FTSR_TR3_Pos) /*!< 0x00000008 */
+#define EXTI_FTSR_TR3 EXTI_FTSR_TR3_Msk /*!< Falling trigger event configuration bit of line 3 */
+#define EXTI_FTSR_TR4_Pos (4U)
+#define EXTI_FTSR_TR4_Msk (0x1U << EXTI_FTSR_TR4_Pos) /*!< 0x00000010 */
+#define EXTI_FTSR_TR4 EXTI_FTSR_TR4_Msk /*!< Falling trigger event configuration bit of line 4 */
+#define EXTI_FTSR_TR5_Pos (5U)
+#define EXTI_FTSR_TR5_Msk (0x1U << EXTI_FTSR_TR5_Pos) /*!< 0x00000020 */
+#define EXTI_FTSR_TR5 EXTI_FTSR_TR5_Msk /*!< Falling trigger event configuration bit of line 5 */
+#define EXTI_FTSR_TR6_Pos (6U)
+#define EXTI_FTSR_TR6_Msk (0x1U << EXTI_FTSR_TR6_Pos) /*!< 0x00000040 */
+#define EXTI_FTSR_TR6 EXTI_FTSR_TR6_Msk /*!< Falling trigger event configuration bit of line 6 */
+#define EXTI_FTSR_TR7_Pos (7U)
+#define EXTI_FTSR_TR7_Msk (0x1U << EXTI_FTSR_TR7_Pos) /*!< 0x00000080 */
+#define EXTI_FTSR_TR7 EXTI_FTSR_TR7_Msk /*!< Falling trigger event configuration bit of line 7 */
+#define EXTI_FTSR_TR8_Pos (8U)
+#define EXTI_FTSR_TR8_Msk (0x1U << EXTI_FTSR_TR8_Pos) /*!< 0x00000100 */
+#define EXTI_FTSR_TR8 EXTI_FTSR_TR8_Msk /*!< Falling trigger event configuration bit of line 8 */
+#define EXTI_FTSR_TR9_Pos (9U)
+#define EXTI_FTSR_TR9_Msk (0x1U << EXTI_FTSR_TR9_Pos) /*!< 0x00000200 */
+#define EXTI_FTSR_TR9 EXTI_FTSR_TR9_Msk /*!< Falling trigger event configuration bit of line 9 */
+#define EXTI_FTSR_TR10_Pos (10U)
+#define EXTI_FTSR_TR10_Msk (0x1U << EXTI_FTSR_TR10_Pos) /*!< 0x00000400 */
+#define EXTI_FTSR_TR10 EXTI_FTSR_TR10_Msk /*!< Falling trigger event configuration bit of line 10 */
+#define EXTI_FTSR_TR11_Pos (11U)
+#define EXTI_FTSR_TR11_Msk (0x1U << EXTI_FTSR_TR11_Pos) /*!< 0x00000800 */
+#define EXTI_FTSR_TR11 EXTI_FTSR_TR11_Msk /*!< Falling trigger event configuration bit of line 11 */
+#define EXTI_FTSR_TR12_Pos (12U)
+#define EXTI_FTSR_TR12_Msk (0x1U << EXTI_FTSR_TR12_Pos) /*!< 0x00001000 */
+#define EXTI_FTSR_TR12 EXTI_FTSR_TR12_Msk /*!< Falling trigger event configuration bit of line 12 */
+#define EXTI_FTSR_TR13_Pos (13U)
+#define EXTI_FTSR_TR13_Msk (0x1U << EXTI_FTSR_TR13_Pos) /*!< 0x00002000 */
+#define EXTI_FTSR_TR13 EXTI_FTSR_TR13_Msk /*!< Falling trigger event configuration bit of line 13 */
+#define EXTI_FTSR_TR14_Pos (14U)
+#define EXTI_FTSR_TR14_Msk (0x1U << EXTI_FTSR_TR14_Pos) /*!< 0x00004000 */
+#define EXTI_FTSR_TR14 EXTI_FTSR_TR14_Msk /*!< Falling trigger event configuration bit of line 14 */
+#define EXTI_FTSR_TR15_Pos (15U)
+#define EXTI_FTSR_TR15_Msk (0x1U << EXTI_FTSR_TR15_Pos) /*!< 0x00008000 */
+#define EXTI_FTSR_TR15 EXTI_FTSR_TR15_Msk /*!< Falling trigger event configuration bit of line 15 */
+#define EXTI_FTSR_TR16_Pos (16U)
+#define EXTI_FTSR_TR16_Msk (0x1U << EXTI_FTSR_TR16_Pos) /*!< 0x00010000 */
+#define EXTI_FTSR_TR16 EXTI_FTSR_TR16_Msk /*!< Falling trigger event configuration bit of line 16 */
+#define EXTI_FTSR_TR17_Pos (17U)
+#define EXTI_FTSR_TR17_Msk (0x1U << EXTI_FTSR_TR17_Pos) /*!< 0x00020000 */
+#define EXTI_FTSR_TR17 EXTI_FTSR_TR17_Msk /*!< Falling trigger event configuration bit of line 17 */
+#define EXTI_FTSR_TR18_Pos (18U)
+#define EXTI_FTSR_TR18_Msk (0x1U << EXTI_FTSR_TR18_Pos) /*!< 0x00040000 */
+#define EXTI_FTSR_TR18 EXTI_FTSR_TR18_Msk /*!< Falling trigger event configuration bit of line 18 */
+#define EXTI_FTSR_TR19_Pos (19U)
+#define EXTI_FTSR_TR19_Msk (0x1U << EXTI_FTSR_TR19_Pos) /*!< 0x00080000 */
+#define EXTI_FTSR_TR19 EXTI_FTSR_TR19_Msk /*!< Falling trigger event configuration bit of line 19 */
+
+/* References Defines */
+#define EXTI_FTSR_FT0 EXTI_FTSR_TR0
+#define EXTI_FTSR_FT1 EXTI_FTSR_TR1
+#define EXTI_FTSR_FT2 EXTI_FTSR_TR2
+#define EXTI_FTSR_FT3 EXTI_FTSR_TR3
+#define EXTI_FTSR_FT4 EXTI_FTSR_TR4
+#define EXTI_FTSR_FT5 EXTI_FTSR_TR5
+#define EXTI_FTSR_FT6 EXTI_FTSR_TR6
+#define EXTI_FTSR_FT7 EXTI_FTSR_TR7
+#define EXTI_FTSR_FT8 EXTI_FTSR_TR8
+#define EXTI_FTSR_FT9 EXTI_FTSR_TR9
+#define EXTI_FTSR_FT10 EXTI_FTSR_TR10
+#define EXTI_FTSR_FT11 EXTI_FTSR_TR11
+#define EXTI_FTSR_FT12 EXTI_FTSR_TR12
+#define EXTI_FTSR_FT13 EXTI_FTSR_TR13
+#define EXTI_FTSR_FT14 EXTI_FTSR_TR14
+#define EXTI_FTSR_FT15 EXTI_FTSR_TR15
+#define EXTI_FTSR_FT16 EXTI_FTSR_TR16
+#define EXTI_FTSR_FT17 EXTI_FTSR_TR17
+#define EXTI_FTSR_FT18 EXTI_FTSR_TR18
+#define EXTI_FTSR_FT19 EXTI_FTSR_TR19
+
+/****************** Bit definition for EXTI_SWIER register ******************/
+#define EXTI_SWIER_SWIER0_Pos (0U)
+#define EXTI_SWIER_SWIER0_Msk (0x1U << EXTI_SWIER_SWIER0_Pos) /*!< 0x00000001 */
+#define EXTI_SWIER_SWIER0 EXTI_SWIER_SWIER0_Msk /*!< Software Interrupt on line 0 */
+#define EXTI_SWIER_SWIER1_Pos (1U)
+#define EXTI_SWIER_SWIER1_Msk (0x1U << EXTI_SWIER_SWIER1_Pos) /*!< 0x00000002 */
+#define EXTI_SWIER_SWIER1 EXTI_SWIER_SWIER1_Msk /*!< Software Interrupt on line 1 */
+#define EXTI_SWIER_SWIER2_Pos (2U)
+#define EXTI_SWIER_SWIER2_Msk (0x1U << EXTI_SWIER_SWIER2_Pos) /*!< 0x00000004 */
+#define EXTI_SWIER_SWIER2 EXTI_SWIER_SWIER2_Msk /*!< Software Interrupt on line 2 */
+#define EXTI_SWIER_SWIER3_Pos (3U)
+#define EXTI_SWIER_SWIER3_Msk (0x1U << EXTI_SWIER_SWIER3_Pos) /*!< 0x00000008 */
+#define EXTI_SWIER_SWIER3 EXTI_SWIER_SWIER3_Msk /*!< Software Interrupt on line 3 */
+#define EXTI_SWIER_SWIER4_Pos (4U)
+#define EXTI_SWIER_SWIER4_Msk (0x1U << EXTI_SWIER_SWIER4_Pos) /*!< 0x00000010 */
+#define EXTI_SWIER_SWIER4 EXTI_SWIER_SWIER4_Msk /*!< Software Interrupt on line 4 */
+#define EXTI_SWIER_SWIER5_Pos (5U)
+#define EXTI_SWIER_SWIER5_Msk (0x1U << EXTI_SWIER_SWIER5_Pos) /*!< 0x00000020 */
+#define EXTI_SWIER_SWIER5 EXTI_SWIER_SWIER5_Msk /*!< Software Interrupt on line 5 */
+#define EXTI_SWIER_SWIER6_Pos (6U)
+#define EXTI_SWIER_SWIER6_Msk (0x1U << EXTI_SWIER_SWIER6_Pos) /*!< 0x00000040 */
+#define EXTI_SWIER_SWIER6 EXTI_SWIER_SWIER6_Msk /*!< Software Interrupt on line 6 */
+#define EXTI_SWIER_SWIER7_Pos (7U)
+#define EXTI_SWIER_SWIER7_Msk (0x1U << EXTI_SWIER_SWIER7_Pos) /*!< 0x00000080 */
+#define EXTI_SWIER_SWIER7 EXTI_SWIER_SWIER7_Msk /*!< Software Interrupt on line 7 */
+#define EXTI_SWIER_SWIER8_Pos (8U)
+#define EXTI_SWIER_SWIER8_Msk (0x1U << EXTI_SWIER_SWIER8_Pos) /*!< 0x00000100 */
+#define EXTI_SWIER_SWIER8 EXTI_SWIER_SWIER8_Msk /*!< Software Interrupt on line 8 */
+#define EXTI_SWIER_SWIER9_Pos (9U)
+#define EXTI_SWIER_SWIER9_Msk (0x1U << EXTI_SWIER_SWIER9_Pos) /*!< 0x00000200 */
+#define EXTI_SWIER_SWIER9 EXTI_SWIER_SWIER9_Msk /*!< Software Interrupt on line 9 */
+#define EXTI_SWIER_SWIER10_Pos (10U)
+#define EXTI_SWIER_SWIER10_Msk (0x1U << EXTI_SWIER_SWIER10_Pos) /*!< 0x00000400 */
+#define EXTI_SWIER_SWIER10 EXTI_SWIER_SWIER10_Msk /*!< Software Interrupt on line 10 */
+#define EXTI_SWIER_SWIER11_Pos (11U)
+#define EXTI_SWIER_SWIER11_Msk (0x1U << EXTI_SWIER_SWIER11_Pos) /*!< 0x00000800 */
+#define EXTI_SWIER_SWIER11 EXTI_SWIER_SWIER11_Msk /*!< Software Interrupt on line 11 */
+#define EXTI_SWIER_SWIER12_Pos (12U)
+#define EXTI_SWIER_SWIER12_Msk (0x1U << EXTI_SWIER_SWIER12_Pos) /*!< 0x00001000 */
+#define EXTI_SWIER_SWIER12 EXTI_SWIER_SWIER12_Msk /*!< Software Interrupt on line 12 */
+#define EXTI_SWIER_SWIER13_Pos (13U)
+#define EXTI_SWIER_SWIER13_Msk (0x1U << EXTI_SWIER_SWIER13_Pos) /*!< 0x00002000 */
+#define EXTI_SWIER_SWIER13 EXTI_SWIER_SWIER13_Msk /*!< Software Interrupt on line 13 */
+#define EXTI_SWIER_SWIER14_Pos (14U)
+#define EXTI_SWIER_SWIER14_Msk (0x1U << EXTI_SWIER_SWIER14_Pos) /*!< 0x00004000 */
+#define EXTI_SWIER_SWIER14 EXTI_SWIER_SWIER14_Msk /*!< Software Interrupt on line 14 */
+#define EXTI_SWIER_SWIER15_Pos (15U)
+#define EXTI_SWIER_SWIER15_Msk (0x1U << EXTI_SWIER_SWIER15_Pos) /*!< 0x00008000 */
+#define EXTI_SWIER_SWIER15 EXTI_SWIER_SWIER15_Msk /*!< Software Interrupt on line 15 */
+#define EXTI_SWIER_SWIER16_Pos (16U)
+#define EXTI_SWIER_SWIER16_Msk (0x1U << EXTI_SWIER_SWIER16_Pos) /*!< 0x00010000 */
+#define EXTI_SWIER_SWIER16 EXTI_SWIER_SWIER16_Msk /*!< Software Interrupt on line 16 */
+#define EXTI_SWIER_SWIER17_Pos (17U)
+#define EXTI_SWIER_SWIER17_Msk (0x1U << EXTI_SWIER_SWIER17_Pos) /*!< 0x00020000 */
+#define EXTI_SWIER_SWIER17 EXTI_SWIER_SWIER17_Msk /*!< Software Interrupt on line 17 */
+#define EXTI_SWIER_SWIER18_Pos (18U)
+#define EXTI_SWIER_SWIER18_Msk (0x1U << EXTI_SWIER_SWIER18_Pos) /*!< 0x00040000 */
+#define EXTI_SWIER_SWIER18 EXTI_SWIER_SWIER18_Msk /*!< Software Interrupt on line 18 */
+#define EXTI_SWIER_SWIER19_Pos (19U)
+#define EXTI_SWIER_SWIER19_Msk (0x1U << EXTI_SWIER_SWIER19_Pos) /*!< 0x00080000 */
+#define EXTI_SWIER_SWIER19 EXTI_SWIER_SWIER19_Msk /*!< Software Interrupt on line 19 */
+
+/* References Defines */
+#define EXTI_SWIER_SWI0 EXTI_SWIER_SWIER0
+#define EXTI_SWIER_SWI1 EXTI_SWIER_SWIER1
+#define EXTI_SWIER_SWI2 EXTI_SWIER_SWIER2
+#define EXTI_SWIER_SWI3 EXTI_SWIER_SWIER3
+#define EXTI_SWIER_SWI4 EXTI_SWIER_SWIER4
+#define EXTI_SWIER_SWI5 EXTI_SWIER_SWIER5
+#define EXTI_SWIER_SWI6 EXTI_SWIER_SWIER6
+#define EXTI_SWIER_SWI7 EXTI_SWIER_SWIER7
+#define EXTI_SWIER_SWI8 EXTI_SWIER_SWIER8
+#define EXTI_SWIER_SWI9 EXTI_SWIER_SWIER9
+#define EXTI_SWIER_SWI10 EXTI_SWIER_SWIER10
+#define EXTI_SWIER_SWI11 EXTI_SWIER_SWIER11
+#define EXTI_SWIER_SWI12 EXTI_SWIER_SWIER12
+#define EXTI_SWIER_SWI13 EXTI_SWIER_SWIER13
+#define EXTI_SWIER_SWI14 EXTI_SWIER_SWIER14
+#define EXTI_SWIER_SWI15 EXTI_SWIER_SWIER15
+#define EXTI_SWIER_SWI16 EXTI_SWIER_SWIER16
+#define EXTI_SWIER_SWI17 EXTI_SWIER_SWIER17
+#define EXTI_SWIER_SWI18 EXTI_SWIER_SWIER18
+#define EXTI_SWIER_SWI19 EXTI_SWIER_SWIER19
+
+/******************* Bit definition for EXTI_PR register ********************/
+#define EXTI_PR_PR0_Pos (0U)
+#define EXTI_PR_PR0_Msk (0x1U << EXTI_PR_PR0_Pos) /*!< 0x00000001 */
+#define EXTI_PR_PR0 EXTI_PR_PR0_Msk /*!< Pending bit for line 0 */
+#define EXTI_PR_PR1_Pos (1U)
+#define EXTI_PR_PR1_Msk (0x1U << EXTI_PR_PR1_Pos) /*!< 0x00000002 */
+#define EXTI_PR_PR1 EXTI_PR_PR1_Msk /*!< Pending bit for line 1 */
+#define EXTI_PR_PR2_Pos (2U)
+#define EXTI_PR_PR2_Msk (0x1U << EXTI_PR_PR2_Pos) /*!< 0x00000004 */
+#define EXTI_PR_PR2 EXTI_PR_PR2_Msk /*!< Pending bit for line 2 */
+#define EXTI_PR_PR3_Pos (3U)
+#define EXTI_PR_PR3_Msk (0x1U << EXTI_PR_PR3_Pos) /*!< 0x00000008 */
+#define EXTI_PR_PR3 EXTI_PR_PR3_Msk /*!< Pending bit for line 3 */
+#define EXTI_PR_PR4_Pos (4U)
+#define EXTI_PR_PR4_Msk (0x1U << EXTI_PR_PR4_Pos) /*!< 0x00000010 */
+#define EXTI_PR_PR4 EXTI_PR_PR4_Msk /*!< Pending bit for line 4 */
+#define EXTI_PR_PR5_Pos (5U)
+#define EXTI_PR_PR5_Msk (0x1U << EXTI_PR_PR5_Pos) /*!< 0x00000020 */
+#define EXTI_PR_PR5 EXTI_PR_PR5_Msk /*!< Pending bit for line 5 */
+#define EXTI_PR_PR6_Pos (6U)
+#define EXTI_PR_PR6_Msk (0x1U << EXTI_PR_PR6_Pos) /*!< 0x00000040 */
+#define EXTI_PR_PR6 EXTI_PR_PR6_Msk /*!< Pending bit for line 6 */
+#define EXTI_PR_PR7_Pos (7U)
+#define EXTI_PR_PR7_Msk (0x1U << EXTI_PR_PR7_Pos) /*!< 0x00000080 */
+#define EXTI_PR_PR7 EXTI_PR_PR7_Msk /*!< Pending bit for line 7 */
+#define EXTI_PR_PR8_Pos (8U)
+#define EXTI_PR_PR8_Msk (0x1U << EXTI_PR_PR8_Pos) /*!< 0x00000100 */
+#define EXTI_PR_PR8 EXTI_PR_PR8_Msk /*!< Pending bit for line 8 */
+#define EXTI_PR_PR9_Pos (9U)
+#define EXTI_PR_PR9_Msk (0x1U << EXTI_PR_PR9_Pos) /*!< 0x00000200 */
+#define EXTI_PR_PR9 EXTI_PR_PR9_Msk /*!< Pending bit for line 9 */
+#define EXTI_PR_PR10_Pos (10U)
+#define EXTI_PR_PR10_Msk (0x1U << EXTI_PR_PR10_Pos) /*!< 0x00000400 */
+#define EXTI_PR_PR10 EXTI_PR_PR10_Msk /*!< Pending bit for line 10 */
+#define EXTI_PR_PR11_Pos (11U)
+#define EXTI_PR_PR11_Msk (0x1U << EXTI_PR_PR11_Pos) /*!< 0x00000800 */
+#define EXTI_PR_PR11 EXTI_PR_PR11_Msk /*!< Pending bit for line 11 */
+#define EXTI_PR_PR12_Pos (12U)
+#define EXTI_PR_PR12_Msk (0x1U << EXTI_PR_PR12_Pos) /*!< 0x00001000 */
+#define EXTI_PR_PR12 EXTI_PR_PR12_Msk /*!< Pending bit for line 12 */
+#define EXTI_PR_PR13_Pos (13U)
+#define EXTI_PR_PR13_Msk (0x1U << EXTI_PR_PR13_Pos) /*!< 0x00002000 */
+#define EXTI_PR_PR13 EXTI_PR_PR13_Msk /*!< Pending bit for line 13 */
+#define EXTI_PR_PR14_Pos (14U)
+#define EXTI_PR_PR14_Msk (0x1U << EXTI_PR_PR14_Pos) /*!< 0x00004000 */
+#define EXTI_PR_PR14 EXTI_PR_PR14_Msk /*!< Pending bit for line 14 */
+#define EXTI_PR_PR15_Pos (15U)
+#define EXTI_PR_PR15_Msk (0x1U << EXTI_PR_PR15_Pos) /*!< 0x00008000 */
+#define EXTI_PR_PR15 EXTI_PR_PR15_Msk /*!< Pending bit for line 15 */
+#define EXTI_PR_PR16_Pos (16U)
+#define EXTI_PR_PR16_Msk (0x1U << EXTI_PR_PR16_Pos) /*!< 0x00010000 */
+#define EXTI_PR_PR16 EXTI_PR_PR16_Msk /*!< Pending bit for line 16 */
+#define EXTI_PR_PR17_Pos (17U)
+#define EXTI_PR_PR17_Msk (0x1U << EXTI_PR_PR17_Pos) /*!< 0x00020000 */
+#define EXTI_PR_PR17 EXTI_PR_PR17_Msk /*!< Pending bit for line 17 */
+#define EXTI_PR_PR18_Pos (18U)
+#define EXTI_PR_PR18_Msk (0x1U << EXTI_PR_PR18_Pos) /*!< 0x00040000 */
+#define EXTI_PR_PR18 EXTI_PR_PR18_Msk /*!< Pending bit for line 18 */
+#define EXTI_PR_PR19_Pos (19U)
+#define EXTI_PR_PR19_Msk (0x1U << EXTI_PR_PR19_Pos) /*!< 0x00080000 */
+#define EXTI_PR_PR19 EXTI_PR_PR19_Msk /*!< Pending bit for line 19 */
+
+/* References Defines */
+#define EXTI_PR_PIF0 EXTI_PR_PR0
+#define EXTI_PR_PIF1 EXTI_PR_PR1
+#define EXTI_PR_PIF2 EXTI_PR_PR2
+#define EXTI_PR_PIF3 EXTI_PR_PR3
+#define EXTI_PR_PIF4 EXTI_PR_PR4
+#define EXTI_PR_PIF5 EXTI_PR_PR5
+#define EXTI_PR_PIF6 EXTI_PR_PR6
+#define EXTI_PR_PIF7 EXTI_PR_PR7
+#define EXTI_PR_PIF8 EXTI_PR_PR8
+#define EXTI_PR_PIF9 EXTI_PR_PR9
+#define EXTI_PR_PIF10 EXTI_PR_PR10
+#define EXTI_PR_PIF11 EXTI_PR_PR11
+#define EXTI_PR_PIF12 EXTI_PR_PR12
+#define EXTI_PR_PIF13 EXTI_PR_PR13
+#define EXTI_PR_PIF14 EXTI_PR_PR14
+#define EXTI_PR_PIF15 EXTI_PR_PR15
+#define EXTI_PR_PIF16 EXTI_PR_PR16
+#define EXTI_PR_PIF17 EXTI_PR_PR17
+#define EXTI_PR_PIF18 EXTI_PR_PR18
+#define EXTI_PR_PIF19 EXTI_PR_PR19
+
+/******************************************************************************/
+/* */
+/* DMA Controller */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for DMA_ISR register ********************/
+#define DMA_ISR_GIF1_Pos (0U)
+#define DMA_ISR_GIF1_Msk (0x1U << DMA_ISR_GIF1_Pos) /*!< 0x00000001 */
+#define DMA_ISR_GIF1 DMA_ISR_GIF1_Msk /*!< Channel 1 Global interrupt flag */
+#define DMA_ISR_TCIF1_Pos (1U)
+#define DMA_ISR_TCIF1_Msk (0x1U << DMA_ISR_TCIF1_Pos) /*!< 0x00000002 */
+#define DMA_ISR_TCIF1 DMA_ISR_TCIF1_Msk /*!< Channel 1 Transfer Complete flag */
+#define DMA_ISR_HTIF1_Pos (2U)
+#define DMA_ISR_HTIF1_Msk (0x1U << DMA_ISR_HTIF1_Pos) /*!< 0x00000004 */
+#define DMA_ISR_HTIF1 DMA_ISR_HTIF1_Msk /*!< Channel 1 Half Transfer flag */
+#define DMA_ISR_TEIF1_Pos (3U)
+#define DMA_ISR_TEIF1_Msk (0x1U << DMA_ISR_TEIF1_Pos) /*!< 0x00000008 */
+#define DMA_ISR_TEIF1 DMA_ISR_TEIF1_Msk /*!< Channel 1 Transfer Error flag */
+#define DMA_ISR_GIF2_Pos (4U)
+#define DMA_ISR_GIF2_Msk (0x1U << DMA_ISR_GIF2_Pos) /*!< 0x00000010 */
+#define DMA_ISR_GIF2 DMA_ISR_GIF2_Msk /*!< Channel 2 Global interrupt flag */
+#define DMA_ISR_TCIF2_Pos (5U)
+#define DMA_ISR_TCIF2_Msk (0x1U << DMA_ISR_TCIF2_Pos) /*!< 0x00000020 */
+#define DMA_ISR_TCIF2 DMA_ISR_TCIF2_Msk /*!< Channel 2 Transfer Complete flag */
+#define DMA_ISR_HTIF2_Pos (6U)
+#define DMA_ISR_HTIF2_Msk (0x1U << DMA_ISR_HTIF2_Pos) /*!< 0x00000040 */
+#define DMA_ISR_HTIF2 DMA_ISR_HTIF2_Msk /*!< Channel 2 Half Transfer flag */
+#define DMA_ISR_TEIF2_Pos (7U)
+#define DMA_ISR_TEIF2_Msk (0x1U << DMA_ISR_TEIF2_Pos) /*!< 0x00000080 */
+#define DMA_ISR_TEIF2 DMA_ISR_TEIF2_Msk /*!< Channel 2 Transfer Error flag */
+#define DMA_ISR_GIF3_Pos (8U)
+#define DMA_ISR_GIF3_Msk (0x1U << DMA_ISR_GIF3_Pos) /*!< 0x00000100 */
+#define DMA_ISR_GIF3 DMA_ISR_GIF3_Msk /*!< Channel 3 Global interrupt flag */
+#define DMA_ISR_TCIF3_Pos (9U)
+#define DMA_ISR_TCIF3_Msk (0x1U << DMA_ISR_TCIF3_Pos) /*!< 0x00000200 */
+#define DMA_ISR_TCIF3 DMA_ISR_TCIF3_Msk /*!< Channel 3 Transfer Complete flag */
+#define DMA_ISR_HTIF3_Pos (10U)
+#define DMA_ISR_HTIF3_Msk (0x1U << DMA_ISR_HTIF3_Pos) /*!< 0x00000400 */
+#define DMA_ISR_HTIF3 DMA_ISR_HTIF3_Msk /*!< Channel 3 Half Transfer flag */
+#define DMA_ISR_TEIF3_Pos (11U)
+#define DMA_ISR_TEIF3_Msk (0x1U << DMA_ISR_TEIF3_Pos) /*!< 0x00000800 */
+#define DMA_ISR_TEIF3 DMA_ISR_TEIF3_Msk /*!< Channel 3 Transfer Error flag */
+#define DMA_ISR_GIF4_Pos (12U)
+#define DMA_ISR_GIF4_Msk (0x1U << DMA_ISR_GIF4_Pos) /*!< 0x00001000 */
+#define DMA_ISR_GIF4 DMA_ISR_GIF4_Msk /*!< Channel 4 Global interrupt flag */
+#define DMA_ISR_TCIF4_Pos (13U)
+#define DMA_ISR_TCIF4_Msk (0x1U << DMA_ISR_TCIF4_Pos) /*!< 0x00002000 */
+#define DMA_ISR_TCIF4 DMA_ISR_TCIF4_Msk /*!< Channel 4 Transfer Complete flag */
+#define DMA_ISR_HTIF4_Pos (14U)
+#define DMA_ISR_HTIF4_Msk (0x1U << DMA_ISR_HTIF4_Pos) /*!< 0x00004000 */
+#define DMA_ISR_HTIF4 DMA_ISR_HTIF4_Msk /*!< Channel 4 Half Transfer flag */
+#define DMA_ISR_TEIF4_Pos (15U)
+#define DMA_ISR_TEIF4_Msk (0x1U << DMA_ISR_TEIF4_Pos) /*!< 0x00008000 */
+#define DMA_ISR_TEIF4 DMA_ISR_TEIF4_Msk /*!< Channel 4 Transfer Error flag */
+#define DMA_ISR_GIF5_Pos (16U)
+#define DMA_ISR_GIF5_Msk (0x1U << DMA_ISR_GIF5_Pos) /*!< 0x00010000 */
+#define DMA_ISR_GIF5 DMA_ISR_GIF5_Msk /*!< Channel 5 Global interrupt flag */
+#define DMA_ISR_TCIF5_Pos (17U)
+#define DMA_ISR_TCIF5_Msk (0x1U << DMA_ISR_TCIF5_Pos) /*!< 0x00020000 */
+#define DMA_ISR_TCIF5 DMA_ISR_TCIF5_Msk /*!< Channel 5 Transfer Complete flag */
+#define DMA_ISR_HTIF5_Pos (18U)
+#define DMA_ISR_HTIF5_Msk (0x1U << DMA_ISR_HTIF5_Pos) /*!< 0x00040000 */
+#define DMA_ISR_HTIF5 DMA_ISR_HTIF5_Msk /*!< Channel 5 Half Transfer flag */
+#define DMA_ISR_TEIF5_Pos (19U)
+#define DMA_ISR_TEIF5_Msk (0x1U << DMA_ISR_TEIF5_Pos) /*!< 0x00080000 */
+#define DMA_ISR_TEIF5 DMA_ISR_TEIF5_Msk /*!< Channel 5 Transfer Error flag */
+#define DMA_ISR_GIF6_Pos (20U)
+#define DMA_ISR_GIF6_Msk (0x1U << DMA_ISR_GIF6_Pos) /*!< 0x00100000 */
+#define DMA_ISR_GIF6 DMA_ISR_GIF6_Msk /*!< Channel 6 Global interrupt flag */
+#define DMA_ISR_TCIF6_Pos (21U)
+#define DMA_ISR_TCIF6_Msk (0x1U << DMA_ISR_TCIF6_Pos) /*!< 0x00200000 */
+#define DMA_ISR_TCIF6 DMA_ISR_TCIF6_Msk /*!< Channel 6 Transfer Complete flag */
+#define DMA_ISR_HTIF6_Pos (22U)
+#define DMA_ISR_HTIF6_Msk (0x1U << DMA_ISR_HTIF6_Pos) /*!< 0x00400000 */
+#define DMA_ISR_HTIF6 DMA_ISR_HTIF6_Msk /*!< Channel 6 Half Transfer flag */
+#define DMA_ISR_TEIF6_Pos (23U)
+#define DMA_ISR_TEIF6_Msk (0x1U << DMA_ISR_TEIF6_Pos) /*!< 0x00800000 */
+#define DMA_ISR_TEIF6 DMA_ISR_TEIF6_Msk /*!< Channel 6 Transfer Error flag */
+#define DMA_ISR_GIF7_Pos (24U)
+#define DMA_ISR_GIF7_Msk (0x1U << DMA_ISR_GIF7_Pos) /*!< 0x01000000 */
+#define DMA_ISR_GIF7 DMA_ISR_GIF7_Msk /*!< Channel 7 Global interrupt flag */
+#define DMA_ISR_TCIF7_Pos (25U)
+#define DMA_ISR_TCIF7_Msk (0x1U << DMA_ISR_TCIF7_Pos) /*!< 0x02000000 */
+#define DMA_ISR_TCIF7 DMA_ISR_TCIF7_Msk /*!< Channel 7 Transfer Complete flag */
+#define DMA_ISR_HTIF7_Pos (26U)
+#define DMA_ISR_HTIF7_Msk (0x1U << DMA_ISR_HTIF7_Pos) /*!< 0x04000000 */
+#define DMA_ISR_HTIF7 DMA_ISR_HTIF7_Msk /*!< Channel 7 Half Transfer flag */
+#define DMA_ISR_TEIF7_Pos (27U)
+#define DMA_ISR_TEIF7_Msk (0x1U << DMA_ISR_TEIF7_Pos) /*!< 0x08000000 */
+#define DMA_ISR_TEIF7 DMA_ISR_TEIF7_Msk /*!< Channel 7 Transfer Error flag */
+
+/******************* Bit definition for DMA_IFCR register *******************/
+#define DMA_IFCR_CGIF1_Pos (0U)
+#define DMA_IFCR_CGIF1_Msk (0x1U << DMA_IFCR_CGIF1_Pos) /*!< 0x00000001 */
+#define DMA_IFCR_CGIF1 DMA_IFCR_CGIF1_Msk /*!< Channel 1 Global interrupt clear */
+#define DMA_IFCR_CTCIF1_Pos (1U)
+#define DMA_IFCR_CTCIF1_Msk (0x1U << DMA_IFCR_CTCIF1_Pos) /*!< 0x00000002 */
+#define DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF1_Msk /*!< Channel 1 Transfer Complete clear */
+#define DMA_IFCR_CHTIF1_Pos (2U)
+#define DMA_IFCR_CHTIF1_Msk (0x1U << DMA_IFCR_CHTIF1_Pos) /*!< 0x00000004 */
+#define DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF1_Msk /*!< Channel 1 Half Transfer clear */
+#define DMA_IFCR_CTEIF1_Pos (3U)
+#define DMA_IFCR_CTEIF1_Msk (0x1U << DMA_IFCR_CTEIF1_Pos) /*!< 0x00000008 */
+#define DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF1_Msk /*!< Channel 1 Transfer Error clear */
+#define DMA_IFCR_CGIF2_Pos (4U)
+#define DMA_IFCR_CGIF2_Msk (0x1U << DMA_IFCR_CGIF2_Pos) /*!< 0x00000010 */
+#define DMA_IFCR_CGIF2 DMA_IFCR_CGIF2_Msk /*!< Channel 2 Global interrupt clear */
+#define DMA_IFCR_CTCIF2_Pos (5U)
+#define DMA_IFCR_CTCIF2_Msk (0x1U << DMA_IFCR_CTCIF2_Pos) /*!< 0x00000020 */
+#define DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF2_Msk /*!< Channel 2 Transfer Complete clear */
+#define DMA_IFCR_CHTIF2_Pos (6U)
+#define DMA_IFCR_CHTIF2_Msk (0x1U << DMA_IFCR_CHTIF2_Pos) /*!< 0x00000040 */
+#define DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF2_Msk /*!< Channel 2 Half Transfer clear */
+#define DMA_IFCR_CTEIF2_Pos (7U)
+#define DMA_IFCR_CTEIF2_Msk (0x1U << DMA_IFCR_CTEIF2_Pos) /*!< 0x00000080 */
+#define DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF2_Msk /*!< Channel 2 Transfer Error clear */
+#define DMA_IFCR_CGIF3_Pos (8U)
+#define DMA_IFCR_CGIF3_Msk (0x1U << DMA_IFCR_CGIF3_Pos) /*!< 0x00000100 */
+#define DMA_IFCR_CGIF3 DMA_IFCR_CGIF3_Msk /*!< Channel 3 Global interrupt clear */
+#define DMA_IFCR_CTCIF3_Pos (9U)
+#define DMA_IFCR_CTCIF3_Msk (0x1U << DMA_IFCR_CTCIF3_Pos) /*!< 0x00000200 */
+#define DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF3_Msk /*!< Channel 3 Transfer Complete clear */
+#define DMA_IFCR_CHTIF3_Pos (10U)
+#define DMA_IFCR_CHTIF3_Msk (0x1U << DMA_IFCR_CHTIF3_Pos) /*!< 0x00000400 */
+#define DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF3_Msk /*!< Channel 3 Half Transfer clear */
+#define DMA_IFCR_CTEIF3_Pos (11U)
+#define DMA_IFCR_CTEIF3_Msk (0x1U << DMA_IFCR_CTEIF3_Pos) /*!< 0x00000800 */
+#define DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF3_Msk /*!< Channel 3 Transfer Error clear */
+#define DMA_IFCR_CGIF4_Pos (12U)
+#define DMA_IFCR_CGIF4_Msk (0x1U << DMA_IFCR_CGIF4_Pos) /*!< 0x00001000 */
+#define DMA_IFCR_CGIF4 DMA_IFCR_CGIF4_Msk /*!< Channel 4 Global interrupt clear */
+#define DMA_IFCR_CTCIF4_Pos (13U)
+#define DMA_IFCR_CTCIF4_Msk (0x1U << DMA_IFCR_CTCIF4_Pos) /*!< 0x00002000 */
+#define DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF4_Msk /*!< Channel 4 Transfer Complete clear */
+#define DMA_IFCR_CHTIF4_Pos (14U)
+#define DMA_IFCR_CHTIF4_Msk (0x1U << DMA_IFCR_CHTIF4_Pos) /*!< 0x00004000 */
+#define DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF4_Msk /*!< Channel 4 Half Transfer clear */
+#define DMA_IFCR_CTEIF4_Pos (15U)
+#define DMA_IFCR_CTEIF4_Msk (0x1U << DMA_IFCR_CTEIF4_Pos) /*!< 0x00008000 */
+#define DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF4_Msk /*!< Channel 4 Transfer Error clear */
+#define DMA_IFCR_CGIF5_Pos (16U)
+#define DMA_IFCR_CGIF5_Msk (0x1U << DMA_IFCR_CGIF5_Pos) /*!< 0x00010000 */
+#define DMA_IFCR_CGIF5 DMA_IFCR_CGIF5_Msk /*!< Channel 5 Global interrupt clear */
+#define DMA_IFCR_CTCIF5_Pos (17U)
+#define DMA_IFCR_CTCIF5_Msk (0x1U << DMA_IFCR_CTCIF5_Pos) /*!< 0x00020000 */
+#define DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF5_Msk /*!< Channel 5 Transfer Complete clear */
+#define DMA_IFCR_CHTIF5_Pos (18U)
+#define DMA_IFCR_CHTIF5_Msk (0x1U << DMA_IFCR_CHTIF5_Pos) /*!< 0x00040000 */
+#define DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5_Msk /*!< Channel 5 Half Transfer clear */
+#define DMA_IFCR_CTEIF5_Pos (19U)
+#define DMA_IFCR_CTEIF5_Msk (0x1U << DMA_IFCR_CTEIF5_Pos) /*!< 0x00080000 */
+#define DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF5_Msk /*!< Channel 5 Transfer Error clear */
+#define DMA_IFCR_CGIF6_Pos (20U)
+#define DMA_IFCR_CGIF6_Msk (0x1U << DMA_IFCR_CGIF6_Pos) /*!< 0x00100000 */
+#define DMA_IFCR_CGIF6 DMA_IFCR_CGIF6_Msk /*!< Channel 6 Global interrupt clear */
+#define DMA_IFCR_CTCIF6_Pos (21U)
+#define DMA_IFCR_CTCIF6_Msk (0x1U << DMA_IFCR_CTCIF6_Pos) /*!< 0x00200000 */
+#define DMA_IFCR_CTCIF6 DMA_IFCR_CTCIF6_Msk /*!< Channel 6 Transfer Complete clear */
+#define DMA_IFCR_CHTIF6_Pos (22U)
+#define DMA_IFCR_CHTIF6_Msk (0x1U << DMA_IFCR_CHTIF6_Pos) /*!< 0x00400000 */
+#define DMA_IFCR_CHTIF6 DMA_IFCR_CHTIF6_Msk /*!< Channel 6 Half Transfer clear */
+#define DMA_IFCR_CTEIF6_Pos (23U)
+#define DMA_IFCR_CTEIF6_Msk (0x1U << DMA_IFCR_CTEIF6_Pos) /*!< 0x00800000 */
+#define DMA_IFCR_CTEIF6 DMA_IFCR_CTEIF6_Msk /*!< Channel 6 Transfer Error clear */
+#define DMA_IFCR_CGIF7_Pos (24U)
+#define DMA_IFCR_CGIF7_Msk (0x1U << DMA_IFCR_CGIF7_Pos) /*!< 0x01000000 */
+#define DMA_IFCR_CGIF7 DMA_IFCR_CGIF7_Msk /*!< Channel 7 Global interrupt clear */
+#define DMA_IFCR_CTCIF7_Pos (25U)
+#define DMA_IFCR_CTCIF7_Msk (0x1U << DMA_IFCR_CTCIF7_Pos) /*!< 0x02000000 */
+#define DMA_IFCR_CTCIF7 DMA_IFCR_CTCIF7_Msk /*!< Channel 7 Transfer Complete clear */
+#define DMA_IFCR_CHTIF7_Pos (26U)
+#define DMA_IFCR_CHTIF7_Msk (0x1U << DMA_IFCR_CHTIF7_Pos) /*!< 0x04000000 */
+#define DMA_IFCR_CHTIF7 DMA_IFCR_CHTIF7_Msk /*!< Channel 7 Half Transfer clear */
+#define DMA_IFCR_CTEIF7_Pos (27U)
+#define DMA_IFCR_CTEIF7_Msk (0x1U << DMA_IFCR_CTEIF7_Pos) /*!< 0x08000000 */
+#define DMA_IFCR_CTEIF7 DMA_IFCR_CTEIF7_Msk /*!< Channel 7 Transfer Error clear */
+
+/******************* Bit definition for DMA_CCR register *******************/
+#define DMA_CCR_EN_Pos (0U)
+#define DMA_CCR_EN_Msk (0x1U << DMA_CCR_EN_Pos) /*!< 0x00000001 */
+#define DMA_CCR_EN DMA_CCR_EN_Msk /*!< Channel enable */
+#define DMA_CCR_TCIE_Pos (1U)
+#define DMA_CCR_TCIE_Msk (0x1U << DMA_CCR_TCIE_Pos) /*!< 0x00000002 */
+#define DMA_CCR_TCIE DMA_CCR_TCIE_Msk /*!< Transfer complete interrupt enable */
+#define DMA_CCR_HTIE_Pos (2U)
+#define DMA_CCR_HTIE_Msk (0x1U << DMA_CCR_HTIE_Pos) /*!< 0x00000004 */
+#define DMA_CCR_HTIE DMA_CCR_HTIE_Msk /*!< Half Transfer interrupt enable */
+#define DMA_CCR_TEIE_Pos (3U)
+#define DMA_CCR_TEIE_Msk (0x1U << DMA_CCR_TEIE_Pos) /*!< 0x00000008 */
+#define DMA_CCR_TEIE DMA_CCR_TEIE_Msk /*!< Transfer error interrupt enable */
+#define DMA_CCR_DIR_Pos (4U)
+#define DMA_CCR_DIR_Msk (0x1U << DMA_CCR_DIR_Pos) /*!< 0x00000010 */
+#define DMA_CCR_DIR DMA_CCR_DIR_Msk /*!< Data transfer direction */
+#define DMA_CCR_CIRC_Pos (5U)
+#define DMA_CCR_CIRC_Msk (0x1U << DMA_CCR_CIRC_Pos) /*!< 0x00000020 */
+#define DMA_CCR_CIRC DMA_CCR_CIRC_Msk /*!< Circular mode */
+#define DMA_CCR_PINC_Pos (6U)
+#define DMA_CCR_PINC_Msk (0x1U << DMA_CCR_PINC_Pos) /*!< 0x00000040 */
+#define DMA_CCR_PINC DMA_CCR_PINC_Msk /*!< Peripheral increment mode */
+#define DMA_CCR_MINC_Pos (7U)
+#define DMA_CCR_MINC_Msk (0x1U << DMA_CCR_MINC_Pos) /*!< 0x00000080 */
+#define DMA_CCR_MINC DMA_CCR_MINC_Msk /*!< Memory increment mode */
+
+#define DMA_CCR_PSIZE_Pos (8U)
+#define DMA_CCR_PSIZE_Msk (0x3U << DMA_CCR_PSIZE_Pos) /*!< 0x00000300 */
+#define DMA_CCR_PSIZE DMA_CCR_PSIZE_Msk /*!< PSIZE[1:0] bits (Peripheral size) */
+#define DMA_CCR_PSIZE_0 (0x1U << DMA_CCR_PSIZE_Pos) /*!< 0x00000100 */
+#define DMA_CCR_PSIZE_1 (0x2U << DMA_CCR_PSIZE_Pos) /*!< 0x00000200 */
+
+#define DMA_CCR_MSIZE_Pos (10U)
+#define DMA_CCR_MSIZE_Msk (0x3U << DMA_CCR_MSIZE_Pos) /*!< 0x00000C00 */
+#define DMA_CCR_MSIZE DMA_CCR_MSIZE_Msk /*!< MSIZE[1:0] bits (Memory size) */
+#define DMA_CCR_MSIZE_0 (0x1U << DMA_CCR_MSIZE_Pos) /*!< 0x00000400 */
+#define DMA_CCR_MSIZE_1 (0x2U << DMA_CCR_MSIZE_Pos) /*!< 0x00000800 */
+
+#define DMA_CCR_PL_Pos (12U)
+#define DMA_CCR_PL_Msk (0x3U << DMA_CCR_PL_Pos) /*!< 0x00003000 */
+#define DMA_CCR_PL DMA_CCR_PL_Msk /*!< PL[1:0] bits(Channel Priority level) */
+#define DMA_CCR_PL_0 (0x1U << DMA_CCR_PL_Pos) /*!< 0x00001000 */
+#define DMA_CCR_PL_1 (0x2U << DMA_CCR_PL_Pos) /*!< 0x00002000 */
+
+#define DMA_CCR_MEM2MEM_Pos (14U)
+#define DMA_CCR_MEM2MEM_Msk (0x1U << DMA_CCR_MEM2MEM_Pos) /*!< 0x00004000 */
+#define DMA_CCR_MEM2MEM DMA_CCR_MEM2MEM_Msk /*!< Memory to memory mode */
+
+/****************** Bit definition for DMA_CNDTR register ******************/
+#define DMA_CNDTR_NDT_Pos (0U)
+#define DMA_CNDTR_NDT_Msk (0xFFFFU << DMA_CNDTR_NDT_Pos) /*!< 0x0000FFFF */
+#define DMA_CNDTR_NDT DMA_CNDTR_NDT_Msk /*!< Number of data to Transfer */
+
+/****************** Bit definition for DMA_CPAR register *******************/
+#define DMA_CPAR_PA_Pos (0U)
+#define DMA_CPAR_PA_Msk (0xFFFFFFFFU << DMA_CPAR_PA_Pos) /*!< 0xFFFFFFFF */
+#define DMA_CPAR_PA DMA_CPAR_PA_Msk /*!< Peripheral Address */
+
+/****************** Bit definition for DMA_CMAR register *******************/
+#define DMA_CMAR_MA_Pos (0U)
+#define DMA_CMAR_MA_Msk (0xFFFFFFFFU << DMA_CMAR_MA_Pos) /*!< 0xFFFFFFFF */
+#define DMA_CMAR_MA DMA_CMAR_MA_Msk /*!< Memory Address */
+
+/******************************************************************************/
+/* */
+/* Analog to Digital Converter (ADC) */
+/* */
+/******************************************************************************/
+
+/*
+ * @brief Specific device feature definitions (not present on all devices in the STM32F1 family)
+ */
+#define ADC_MULTIMODE_SUPPORT /*!< ADC feature available only on specific devices: multimode available on devices with several ADC instances */
+
+/******************** Bit definition for ADC_SR register ********************/
+#define ADC_SR_AWD_Pos (0U)
+#define ADC_SR_AWD_Msk (0x1U << ADC_SR_AWD_Pos) /*!< 0x00000001 */
+#define ADC_SR_AWD ADC_SR_AWD_Msk /*!< ADC analog watchdog 1 flag */
+#define ADC_SR_EOS_Pos (1U)
+#define ADC_SR_EOS_Msk (0x1U << ADC_SR_EOS_Pos) /*!< 0x00000002 */
+#define ADC_SR_EOS ADC_SR_EOS_Msk /*!< ADC group regular end of sequence conversions flag */
+#define ADC_SR_JEOS_Pos (2U)
+#define ADC_SR_JEOS_Msk (0x1U << ADC_SR_JEOS_Pos) /*!< 0x00000004 */
+#define ADC_SR_JEOS ADC_SR_JEOS_Msk /*!< ADC group injected end of sequence conversions flag */
+#define ADC_SR_JSTRT_Pos (3U)
+#define ADC_SR_JSTRT_Msk (0x1U << ADC_SR_JSTRT_Pos) /*!< 0x00000008 */
+#define ADC_SR_JSTRT ADC_SR_JSTRT_Msk /*!< ADC group injected conversion start flag */
+#define ADC_SR_STRT_Pos (4U)
+#define ADC_SR_STRT_Msk (0x1U << ADC_SR_STRT_Pos) /*!< 0x00000010 */
+#define ADC_SR_STRT ADC_SR_STRT_Msk /*!< ADC group regular conversion start flag */
+
+/* Legacy defines */
+#define ADC_SR_EOC (ADC_SR_EOS)
+#define ADC_SR_JEOC (ADC_SR_JEOS)
+
+/******************* Bit definition for ADC_CR1 register ********************/
+#define ADC_CR1_AWDCH_Pos (0U)
+#define ADC_CR1_AWDCH_Msk (0x1FU << ADC_CR1_AWDCH_Pos) /*!< 0x0000001F */
+#define ADC_CR1_AWDCH ADC_CR1_AWDCH_Msk /*!< ADC analog watchdog 1 monitored channel selection */
+#define ADC_CR1_AWDCH_0 (0x01U << ADC_CR1_AWDCH_Pos) /*!< 0x00000001 */
+#define ADC_CR1_AWDCH_1 (0x02U << ADC_CR1_AWDCH_Pos) /*!< 0x00000002 */
+#define ADC_CR1_AWDCH_2 (0x04U << ADC_CR1_AWDCH_Pos) /*!< 0x00000004 */
+#define ADC_CR1_AWDCH_3 (0x08U << ADC_CR1_AWDCH_Pos) /*!< 0x00000008 */
+#define ADC_CR1_AWDCH_4 (0x10U << ADC_CR1_AWDCH_Pos) /*!< 0x00000010 */
+
+#define ADC_CR1_EOSIE_Pos (5U)
+#define ADC_CR1_EOSIE_Msk (0x1U << ADC_CR1_EOSIE_Pos) /*!< 0x00000020 */
+#define ADC_CR1_EOSIE ADC_CR1_EOSIE_Msk /*!< ADC group regular end of sequence conversions interrupt */
+#define ADC_CR1_AWDIE_Pos (6U)
+#define ADC_CR1_AWDIE_Msk (0x1U << ADC_CR1_AWDIE_Pos) /*!< 0x00000040 */
+#define ADC_CR1_AWDIE ADC_CR1_AWDIE_Msk /*!< ADC analog watchdog 1 interrupt */
+#define ADC_CR1_JEOSIE_Pos (7U)
+#define ADC_CR1_JEOSIE_Msk (0x1U << ADC_CR1_JEOSIE_Pos) /*!< 0x00000080 */
+#define ADC_CR1_JEOSIE ADC_CR1_JEOSIE_Msk /*!< ADC group injected end of sequence conversions interrupt */
+#define ADC_CR1_SCAN_Pos (8U)
+#define ADC_CR1_SCAN_Msk (0x1U << ADC_CR1_SCAN_Pos) /*!< 0x00000100 */
+#define ADC_CR1_SCAN ADC_CR1_SCAN_Msk /*!< ADC scan mode */
+#define ADC_CR1_AWDSGL_Pos (9U)
+#define ADC_CR1_AWDSGL_Msk (0x1U << ADC_CR1_AWDSGL_Pos) /*!< 0x00000200 */
+#define ADC_CR1_AWDSGL ADC_CR1_AWDSGL_Msk /*!< ADC analog watchdog 1 monitoring a single channel or all channels */
+#define ADC_CR1_JAUTO_Pos (10U)
+#define ADC_CR1_JAUTO_Msk (0x1U << ADC_CR1_JAUTO_Pos) /*!< 0x00000400 */
+#define ADC_CR1_JAUTO ADC_CR1_JAUTO_Msk /*!< ADC group injected automatic trigger mode */
+#define ADC_CR1_DISCEN_Pos (11U)
+#define ADC_CR1_DISCEN_Msk (0x1U << ADC_CR1_DISCEN_Pos) /*!< 0x00000800 */
+#define ADC_CR1_DISCEN ADC_CR1_DISCEN_Msk /*!< ADC group regular sequencer discontinuous mode */
+#define ADC_CR1_JDISCEN_Pos (12U)
+#define ADC_CR1_JDISCEN_Msk (0x1U << ADC_CR1_JDISCEN_Pos) /*!< 0x00001000 */
+#define ADC_CR1_JDISCEN ADC_CR1_JDISCEN_Msk /*!< ADC group injected sequencer discontinuous mode */
+
+#define ADC_CR1_DISCNUM_Pos (13U)
+#define ADC_CR1_DISCNUM_Msk (0x7U << ADC_CR1_DISCNUM_Pos) /*!< 0x0000E000 */
+#define ADC_CR1_DISCNUM ADC_CR1_DISCNUM_Msk /*!< ADC group regular sequencer discontinuous number of ranks */
+#define ADC_CR1_DISCNUM_0 (0x1U << ADC_CR1_DISCNUM_Pos) /*!< 0x00002000 */
+#define ADC_CR1_DISCNUM_1 (0x2U << ADC_CR1_DISCNUM_Pos) /*!< 0x00004000 */
+#define ADC_CR1_DISCNUM_2 (0x4U << ADC_CR1_DISCNUM_Pos) /*!< 0x00008000 */
+
+#define ADC_CR1_DUALMOD_Pos (16U)
+#define ADC_CR1_DUALMOD_Msk (0xFU << ADC_CR1_DUALMOD_Pos) /*!< 0x000F0000 */
+#define ADC_CR1_DUALMOD ADC_CR1_DUALMOD_Msk /*!< ADC multimode mode selection */
+#define ADC_CR1_DUALMOD_0 (0x1U << ADC_CR1_DUALMOD_Pos) /*!< 0x00010000 */
+#define ADC_CR1_DUALMOD_1 (0x2U << ADC_CR1_DUALMOD_Pos) /*!< 0x00020000 */
+#define ADC_CR1_DUALMOD_2 (0x4U << ADC_CR1_DUALMOD_Pos) /*!< 0x00040000 */
+#define ADC_CR1_DUALMOD_3 (0x8U << ADC_CR1_DUALMOD_Pos) /*!< 0x00080000 */
+
+#define ADC_CR1_JAWDEN_Pos (22U)
+#define ADC_CR1_JAWDEN_Msk (0x1U << ADC_CR1_JAWDEN_Pos) /*!< 0x00400000 */
+#define ADC_CR1_JAWDEN ADC_CR1_JAWDEN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group injected */
+#define ADC_CR1_AWDEN_Pos (23U)
+#define ADC_CR1_AWDEN_Msk (0x1U << ADC_CR1_AWDEN_Pos) /*!< 0x00800000 */
+#define ADC_CR1_AWDEN ADC_CR1_AWDEN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group regular */
+
+/* Legacy defines */
+#define ADC_CR1_EOCIE (ADC_CR1_EOSIE)
+#define ADC_CR1_JEOCIE (ADC_CR1_JEOSIE)
+
+/******************* Bit definition for ADC_CR2 register ********************/
+#define ADC_CR2_ADON_Pos (0U)
+#define ADC_CR2_ADON_Msk (0x1U << ADC_CR2_ADON_Pos) /*!< 0x00000001 */
+#define ADC_CR2_ADON ADC_CR2_ADON_Msk /*!< ADC enable */
+#define ADC_CR2_CONT_Pos (1U)
+#define ADC_CR2_CONT_Msk (0x1U << ADC_CR2_CONT_Pos) /*!< 0x00000002 */
+#define ADC_CR2_CONT ADC_CR2_CONT_Msk /*!< ADC group regular continuous conversion mode */
+#define ADC_CR2_CAL_Pos (2U)
+#define ADC_CR2_CAL_Msk (0x1U << ADC_CR2_CAL_Pos) /*!< 0x00000004 */
+#define ADC_CR2_CAL ADC_CR2_CAL_Msk /*!< ADC calibration start */
+#define ADC_CR2_RSTCAL_Pos (3U)
+#define ADC_CR2_RSTCAL_Msk (0x1U << ADC_CR2_RSTCAL_Pos) /*!< 0x00000008 */
+#define ADC_CR2_RSTCAL ADC_CR2_RSTCAL_Msk /*!< ADC calibration reset */
+#define ADC_CR2_DMA_Pos (8U)
+#define ADC_CR2_DMA_Msk (0x1U << ADC_CR2_DMA_Pos) /*!< 0x00000100 */
+#define ADC_CR2_DMA ADC_CR2_DMA_Msk /*!< ADC DMA transfer enable */
+#define ADC_CR2_ALIGN_Pos (11U)
+#define ADC_CR2_ALIGN_Msk (0x1U << ADC_CR2_ALIGN_Pos) /*!< 0x00000800 */
+#define ADC_CR2_ALIGN ADC_CR2_ALIGN_Msk /*!< ADC data alignement */
+
+#define ADC_CR2_JEXTSEL_Pos (12U)
+#define ADC_CR2_JEXTSEL_Msk (0x7U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00007000 */
+#define ADC_CR2_JEXTSEL ADC_CR2_JEXTSEL_Msk /*!< ADC group injected external trigger source */
+#define ADC_CR2_JEXTSEL_0 (0x1U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00001000 */
+#define ADC_CR2_JEXTSEL_1 (0x2U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00002000 */
+#define ADC_CR2_JEXTSEL_2 (0x4U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00004000 */
+
+#define ADC_CR2_JEXTTRIG_Pos (15U)
+#define ADC_CR2_JEXTTRIG_Msk (0x1U << ADC_CR2_JEXTTRIG_Pos) /*!< 0x00008000 */
+#define ADC_CR2_JEXTTRIG ADC_CR2_JEXTTRIG_Msk /*!< ADC group injected external trigger enable */
+
+#define ADC_CR2_EXTSEL_Pos (17U)
+#define ADC_CR2_EXTSEL_Msk (0x7U << ADC_CR2_EXTSEL_Pos) /*!< 0x000E0000 */
+#define ADC_CR2_EXTSEL ADC_CR2_EXTSEL_Msk /*!< ADC group regular external trigger source */
+#define ADC_CR2_EXTSEL_0 (0x1U << ADC_CR2_EXTSEL_Pos) /*!< 0x00020000 */
+#define ADC_CR2_EXTSEL_1 (0x2U << ADC_CR2_EXTSEL_Pos) /*!< 0x00040000 */
+#define ADC_CR2_EXTSEL_2 (0x4U << ADC_CR2_EXTSEL_Pos) /*!< 0x00080000 */
+
+#define ADC_CR2_EXTTRIG_Pos (20U)
+#define ADC_CR2_EXTTRIG_Msk (0x1U << ADC_CR2_EXTTRIG_Pos) /*!< 0x00100000 */
+#define ADC_CR2_EXTTRIG ADC_CR2_EXTTRIG_Msk /*!< ADC group regular external trigger enable */
+#define ADC_CR2_JSWSTART_Pos (21U)
+#define ADC_CR2_JSWSTART_Msk (0x1U << ADC_CR2_JSWSTART_Pos) /*!< 0x00200000 */
+#define ADC_CR2_JSWSTART ADC_CR2_JSWSTART_Msk /*!< ADC group injected conversion start */
+#define ADC_CR2_SWSTART_Pos (22U)
+#define ADC_CR2_SWSTART_Msk (0x1U << ADC_CR2_SWSTART_Pos) /*!< 0x00400000 */
+#define ADC_CR2_SWSTART ADC_CR2_SWSTART_Msk /*!< ADC group regular conversion start */
+#define ADC_CR2_TSVREFE_Pos (23U)
+#define ADC_CR2_TSVREFE_Msk (0x1U << ADC_CR2_TSVREFE_Pos) /*!< 0x00800000 */
+#define ADC_CR2_TSVREFE ADC_CR2_TSVREFE_Msk /*!< ADC internal path to VrefInt and temperature sensor enable */
+
+/****************** Bit definition for ADC_SMPR1 register *******************/
+#define ADC_SMPR1_SMP10_Pos (0U)
+#define ADC_SMPR1_SMP10_Msk (0x7U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000007 */
+#define ADC_SMPR1_SMP10 ADC_SMPR1_SMP10_Msk /*!< ADC channel 10 sampling time selection */
+#define ADC_SMPR1_SMP10_0 (0x1U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000001 */
+#define ADC_SMPR1_SMP10_1 (0x2U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000002 */
+#define ADC_SMPR1_SMP10_2 (0x4U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000004 */
+
+#define ADC_SMPR1_SMP11_Pos (3U)
+#define ADC_SMPR1_SMP11_Msk (0x7U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000038 */
+#define ADC_SMPR1_SMP11 ADC_SMPR1_SMP11_Msk /*!< ADC channel 11 sampling time selection */
+#define ADC_SMPR1_SMP11_0 (0x1U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000008 */
+#define ADC_SMPR1_SMP11_1 (0x2U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000010 */
+#define ADC_SMPR1_SMP11_2 (0x4U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000020 */
+
+#define ADC_SMPR1_SMP12_Pos (6U)
+#define ADC_SMPR1_SMP12_Msk (0x7U << ADC_SMPR1_SMP12_Pos) /*!< 0x000001C0 */
+#define ADC_SMPR1_SMP12 ADC_SMPR1_SMP12_Msk /*!< ADC channel 12 sampling time selection */
+#define ADC_SMPR1_SMP12_0 (0x1U << ADC_SMPR1_SMP12_Pos) /*!< 0x00000040 */
+#define ADC_SMPR1_SMP12_1 (0x2U << ADC_SMPR1_SMP12_Pos) /*!< 0x00000080 */
+#define ADC_SMPR1_SMP12_2 (0x4U << ADC_SMPR1_SMP12_Pos) /*!< 0x00000100 */
+
+#define ADC_SMPR1_SMP13_Pos (9U)
+#define ADC_SMPR1_SMP13_Msk (0x7U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000E00 */
+#define ADC_SMPR1_SMP13 ADC_SMPR1_SMP13_Msk /*!< ADC channel 13 sampling time selection */
+#define ADC_SMPR1_SMP13_0 (0x1U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000200 */
+#define ADC_SMPR1_SMP13_1 (0x2U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000400 */
+#define ADC_SMPR1_SMP13_2 (0x4U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000800 */
+
+#define ADC_SMPR1_SMP14_Pos (12U)
+#define ADC_SMPR1_SMP14_Msk (0x7U << ADC_SMPR1_SMP14_Pos) /*!< 0x00007000 */
+#define ADC_SMPR1_SMP14 ADC_SMPR1_SMP14_Msk /*!< ADC channel 14 sampling time selection */
+#define ADC_SMPR1_SMP14_0 (0x1U << ADC_SMPR1_SMP14_Pos) /*!< 0x00001000 */
+#define ADC_SMPR1_SMP14_1 (0x2U << ADC_SMPR1_SMP14_Pos) /*!< 0x00002000 */
+#define ADC_SMPR1_SMP14_2 (0x4U << ADC_SMPR1_SMP14_Pos) /*!< 0x00004000 */
+
+#define ADC_SMPR1_SMP15_Pos (15U)
+#define ADC_SMPR1_SMP15_Msk (0x7U << ADC_SMPR1_SMP15_Pos) /*!< 0x00038000 */
+#define ADC_SMPR1_SMP15 ADC_SMPR1_SMP15_Msk /*!< ADC channel 15 sampling time selection */
+#define ADC_SMPR1_SMP15_0 (0x1U << ADC_SMPR1_SMP15_Pos) /*!< 0x00008000 */
+#define ADC_SMPR1_SMP15_1 (0x2U << ADC_SMPR1_SMP15_Pos) /*!< 0x00010000 */
+#define ADC_SMPR1_SMP15_2 (0x4U << ADC_SMPR1_SMP15_Pos) /*!< 0x00020000 */
+
+#define ADC_SMPR1_SMP16_Pos (18U)
+#define ADC_SMPR1_SMP16_Msk (0x7U << ADC_SMPR1_SMP16_Pos) /*!< 0x001C0000 */
+#define ADC_SMPR1_SMP16 ADC_SMPR1_SMP16_Msk /*!< ADC channel 16 sampling time selection */
+#define ADC_SMPR1_SMP16_0 (0x1U << ADC_SMPR1_SMP16_Pos) /*!< 0x00040000 */
+#define ADC_SMPR1_SMP16_1 (0x2U << ADC_SMPR1_SMP16_Pos) /*!< 0x00080000 */
+#define ADC_SMPR1_SMP16_2 (0x4U << ADC_SMPR1_SMP16_Pos) /*!< 0x00100000 */
+
+#define ADC_SMPR1_SMP17_Pos (21U)
+#define ADC_SMPR1_SMP17_Msk (0x7U << ADC_SMPR1_SMP17_Pos) /*!< 0x00E00000 */
+#define ADC_SMPR1_SMP17 ADC_SMPR1_SMP17_Msk /*!< ADC channel 17 sampling time selection */
+#define ADC_SMPR1_SMP17_0 (0x1U << ADC_SMPR1_SMP17_Pos) /*!< 0x00200000 */
+#define ADC_SMPR1_SMP17_1 (0x2U << ADC_SMPR1_SMP17_Pos) /*!< 0x00400000 */
+#define ADC_SMPR1_SMP17_2 (0x4U << ADC_SMPR1_SMP17_Pos) /*!< 0x00800000 */
+
+/****************** Bit definition for ADC_SMPR2 register *******************/
+#define ADC_SMPR2_SMP0_Pos (0U)
+#define ADC_SMPR2_SMP0_Msk (0x7U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000007 */
+#define ADC_SMPR2_SMP0 ADC_SMPR2_SMP0_Msk /*!< ADC channel 0 sampling time selection */
+#define ADC_SMPR2_SMP0_0 (0x1U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000001 */
+#define ADC_SMPR2_SMP0_1 (0x2U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000002 */
+#define ADC_SMPR2_SMP0_2 (0x4U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000004 */
+
+#define ADC_SMPR2_SMP1_Pos (3U)
+#define ADC_SMPR2_SMP1_Msk (0x7U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000038 */
+#define ADC_SMPR2_SMP1 ADC_SMPR2_SMP1_Msk /*!< ADC channel 1 sampling time selection */
+#define ADC_SMPR2_SMP1_0 (0x1U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000008 */
+#define ADC_SMPR2_SMP1_1 (0x2U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000010 */
+#define ADC_SMPR2_SMP1_2 (0x4U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000020 */
+
+#define ADC_SMPR2_SMP2_Pos (6U)
+#define ADC_SMPR2_SMP2_Msk (0x7U << ADC_SMPR2_SMP2_Pos) /*!< 0x000001C0 */
+#define ADC_SMPR2_SMP2 ADC_SMPR2_SMP2_Msk /*!< ADC channel 2 sampling time selection */
+#define ADC_SMPR2_SMP2_0 (0x1U << ADC_SMPR2_SMP2_Pos) /*!< 0x00000040 */
+#define ADC_SMPR2_SMP2_1 (0x2U << ADC_SMPR2_SMP2_Pos) /*!< 0x00000080 */
+#define ADC_SMPR2_SMP2_2 (0x4U << ADC_SMPR2_SMP2_Pos) /*!< 0x00000100 */
+
+#define ADC_SMPR2_SMP3_Pos (9U)
+#define ADC_SMPR2_SMP3_Msk (0x7U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000E00 */
+#define ADC_SMPR2_SMP3 ADC_SMPR2_SMP3_Msk /*!< ADC channel 3 sampling time selection */
+#define ADC_SMPR2_SMP3_0 (0x1U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000200 */
+#define ADC_SMPR2_SMP3_1 (0x2U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000400 */
+#define ADC_SMPR2_SMP3_2 (0x4U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000800 */
+
+#define ADC_SMPR2_SMP4_Pos (12U)
+#define ADC_SMPR2_SMP4_Msk (0x7U << ADC_SMPR2_SMP4_Pos) /*!< 0x00007000 */
+#define ADC_SMPR2_SMP4 ADC_SMPR2_SMP4_Msk /*!< ADC channel 4 sampling time selection */
+#define ADC_SMPR2_SMP4_0 (0x1U << ADC_SMPR2_SMP4_Pos) /*!< 0x00001000 */
+#define ADC_SMPR2_SMP4_1 (0x2U << ADC_SMPR2_SMP4_Pos) /*!< 0x00002000 */
+#define ADC_SMPR2_SMP4_2 (0x4U << ADC_SMPR2_SMP4_Pos) /*!< 0x00004000 */
+
+#define ADC_SMPR2_SMP5_Pos (15U)
+#define ADC_SMPR2_SMP5_Msk (0x7U << ADC_SMPR2_SMP5_Pos) /*!< 0x00038000 */
+#define ADC_SMPR2_SMP5 ADC_SMPR2_SMP5_Msk /*!< ADC channel 5 sampling time selection */
+#define ADC_SMPR2_SMP5_0 (0x1U << ADC_SMPR2_SMP5_Pos) /*!< 0x00008000 */
+#define ADC_SMPR2_SMP5_1 (0x2U << ADC_SMPR2_SMP5_Pos) /*!< 0x00010000 */
+#define ADC_SMPR2_SMP5_2 (0x4U << ADC_SMPR2_SMP5_Pos) /*!< 0x00020000 */
+
+#define ADC_SMPR2_SMP6_Pos (18U)
+#define ADC_SMPR2_SMP6_Msk (0x7U << ADC_SMPR2_SMP6_Pos) /*!< 0x001C0000 */
+#define ADC_SMPR2_SMP6 ADC_SMPR2_SMP6_Msk /*!< ADC channel 6 sampling time selection */
+#define ADC_SMPR2_SMP6_0 (0x1U << ADC_SMPR2_SMP6_Pos) /*!< 0x00040000 */
+#define ADC_SMPR2_SMP6_1 (0x2U << ADC_SMPR2_SMP6_Pos) /*!< 0x00080000 */
+#define ADC_SMPR2_SMP6_2 (0x4U << ADC_SMPR2_SMP6_Pos) /*!< 0x00100000 */
+
+#define ADC_SMPR2_SMP7_Pos (21U)
+#define ADC_SMPR2_SMP7_Msk (0x7U << ADC_SMPR2_SMP7_Pos) /*!< 0x00E00000 */
+#define ADC_SMPR2_SMP7 ADC_SMPR2_SMP7_Msk /*!< ADC channel 7 sampling time selection */
+#define ADC_SMPR2_SMP7_0 (0x1U << ADC_SMPR2_SMP7_Pos) /*!< 0x00200000 */
+#define ADC_SMPR2_SMP7_1 (0x2U << ADC_SMPR2_SMP7_Pos) /*!< 0x00400000 */
+#define ADC_SMPR2_SMP7_2 (0x4U << ADC_SMPR2_SMP7_Pos) /*!< 0x00800000 */
+
+#define ADC_SMPR2_SMP8_Pos (24U)
+#define ADC_SMPR2_SMP8_Msk (0x7U << ADC_SMPR2_SMP8_Pos) /*!< 0x07000000 */
+#define ADC_SMPR2_SMP8 ADC_SMPR2_SMP8_Msk /*!< ADC channel 8 sampling time selection */
+#define ADC_SMPR2_SMP8_0 (0x1U << ADC_SMPR2_SMP8_Pos) /*!< 0x01000000 */
+#define ADC_SMPR2_SMP8_1 (0x2U << ADC_SMPR2_SMP8_Pos) /*!< 0x02000000 */
+#define ADC_SMPR2_SMP8_2 (0x4U << ADC_SMPR2_SMP8_Pos) /*!< 0x04000000 */
+
+#define ADC_SMPR2_SMP9_Pos (27U)
+#define ADC_SMPR2_SMP9_Msk (0x7U << ADC_SMPR2_SMP9_Pos) /*!< 0x38000000 */
+#define ADC_SMPR2_SMP9 ADC_SMPR2_SMP9_Msk /*!< ADC channel 9 sampling time selection */
+#define ADC_SMPR2_SMP9_0 (0x1U << ADC_SMPR2_SMP9_Pos) /*!< 0x08000000 */
+#define ADC_SMPR2_SMP9_1 (0x2U << ADC_SMPR2_SMP9_Pos) /*!< 0x10000000 */
+#define ADC_SMPR2_SMP9_2 (0x4U << ADC_SMPR2_SMP9_Pos) /*!< 0x20000000 */
+
+/****************** Bit definition for ADC_JOFR1 register *******************/
+#define ADC_JOFR1_JOFFSET1_Pos (0U)
+#define ADC_JOFR1_JOFFSET1_Msk (0xFFFU << ADC_JOFR1_JOFFSET1_Pos) /*!< 0x00000FFF */
+#define ADC_JOFR1_JOFFSET1 ADC_JOFR1_JOFFSET1_Msk /*!< ADC group injected sequencer rank 1 offset value */
+
+/****************** Bit definition for ADC_JOFR2 register *******************/
+#define ADC_JOFR2_JOFFSET2_Pos (0U)
+#define ADC_JOFR2_JOFFSET2_Msk (0xFFFU << ADC_JOFR2_JOFFSET2_Pos) /*!< 0x00000FFF */
+#define ADC_JOFR2_JOFFSET2 ADC_JOFR2_JOFFSET2_Msk /*!< ADC group injected sequencer rank 2 offset value */
+
+/****************** Bit definition for ADC_JOFR3 register *******************/
+#define ADC_JOFR3_JOFFSET3_Pos (0U)
+#define ADC_JOFR3_JOFFSET3_Msk (0xFFFU << ADC_JOFR3_JOFFSET3_Pos) /*!< 0x00000FFF */
+#define ADC_JOFR3_JOFFSET3 ADC_JOFR3_JOFFSET3_Msk /*!< ADC group injected sequencer rank 3 offset value */
+
+/****************** Bit definition for ADC_JOFR4 register *******************/
+#define ADC_JOFR4_JOFFSET4_Pos (0U)
+#define ADC_JOFR4_JOFFSET4_Msk (0xFFFU << ADC_JOFR4_JOFFSET4_Pos) /*!< 0x00000FFF */
+#define ADC_JOFR4_JOFFSET4 ADC_JOFR4_JOFFSET4_Msk /*!< ADC group injected sequencer rank 4 offset value */
+
+/******************* Bit definition for ADC_HTR register ********************/
+#define ADC_HTR_HT_Pos (0U)
+#define ADC_HTR_HT_Msk (0xFFFU << ADC_HTR_HT_Pos) /*!< 0x00000FFF */
+#define ADC_HTR_HT ADC_HTR_HT_Msk /*!< ADC analog watchdog 1 threshold high */
+
+/******************* Bit definition for ADC_LTR register ********************/
+#define ADC_LTR_LT_Pos (0U)
+#define ADC_LTR_LT_Msk (0xFFFU << ADC_LTR_LT_Pos) /*!< 0x00000FFF */
+#define ADC_LTR_LT ADC_LTR_LT_Msk /*!< ADC analog watchdog 1 threshold low */
+
+/******************* Bit definition for ADC_SQR1 register *******************/
+#define ADC_SQR1_SQ13_Pos (0U)
+#define ADC_SQR1_SQ13_Msk (0x1FU << ADC_SQR1_SQ13_Pos) /*!< 0x0000001F */
+#define ADC_SQR1_SQ13 ADC_SQR1_SQ13_Msk /*!< ADC group regular sequencer rank 13 */
+#define ADC_SQR1_SQ13_0 (0x01U << ADC_SQR1_SQ13_Pos) /*!< 0x00000001 */
+#define ADC_SQR1_SQ13_1 (0x02U << ADC_SQR1_SQ13_Pos) /*!< 0x00000002 */
+#define ADC_SQR1_SQ13_2 (0x04U << ADC_SQR1_SQ13_Pos) /*!< 0x00000004 */
+#define ADC_SQR1_SQ13_3 (0x08U << ADC_SQR1_SQ13_Pos) /*!< 0x00000008 */
+#define ADC_SQR1_SQ13_4 (0x10U << ADC_SQR1_SQ13_Pos) /*!< 0x00000010 */
+
+#define ADC_SQR1_SQ14_Pos (5U)
+#define ADC_SQR1_SQ14_Msk (0x1FU << ADC_SQR1_SQ14_Pos) /*!< 0x000003E0 */
+#define ADC_SQR1_SQ14 ADC_SQR1_SQ14_Msk /*!< ADC group regular sequencer rank 14 */
+#define ADC_SQR1_SQ14_0 (0x01U << ADC_SQR1_SQ14_Pos) /*!< 0x00000020 */
+#define ADC_SQR1_SQ14_1 (0x02U << ADC_SQR1_SQ14_Pos) /*!< 0x00000040 */
+#define ADC_SQR1_SQ14_2 (0x04U << ADC_SQR1_SQ14_Pos) /*!< 0x00000080 */
+#define ADC_SQR1_SQ14_3 (0x08U << ADC_SQR1_SQ14_Pos) /*!< 0x00000100 */
+#define ADC_SQR1_SQ14_4 (0x10U << ADC_SQR1_SQ14_Pos) /*!< 0x00000200 */
+
+#define ADC_SQR1_SQ15_Pos (10U)
+#define ADC_SQR1_SQ15_Msk (0x1FU << ADC_SQR1_SQ15_Pos) /*!< 0x00007C00 */
+#define ADC_SQR1_SQ15 ADC_SQR1_SQ15_Msk /*!< ADC group regular sequencer rank 15 */
+#define ADC_SQR1_SQ15_0 (0x01U << ADC_SQR1_SQ15_Pos) /*!< 0x00000400 */
+#define ADC_SQR1_SQ15_1 (0x02U << ADC_SQR1_SQ15_Pos) /*!< 0x00000800 */
+#define ADC_SQR1_SQ15_2 (0x04U << ADC_SQR1_SQ15_Pos) /*!< 0x00001000 */
+#define ADC_SQR1_SQ15_3 (0x08U << ADC_SQR1_SQ15_Pos) /*!< 0x00002000 */
+#define ADC_SQR1_SQ15_4 (0x10U << ADC_SQR1_SQ15_Pos) /*!< 0x00004000 */
+
+#define ADC_SQR1_SQ16_Pos (15U)
+#define ADC_SQR1_SQ16_Msk (0x1FU << ADC_SQR1_SQ16_Pos) /*!< 0x000F8000 */
+#define ADC_SQR1_SQ16 ADC_SQR1_SQ16_Msk /*!< ADC group regular sequencer rank 16 */
+#define ADC_SQR1_SQ16_0 (0x01U << ADC_SQR1_SQ16_Pos) /*!< 0x00008000 */
+#define ADC_SQR1_SQ16_1 (0x02U << ADC_SQR1_SQ16_Pos) /*!< 0x00010000 */
+#define ADC_SQR1_SQ16_2 (0x04U << ADC_SQR1_SQ16_Pos) /*!< 0x00020000 */
+#define ADC_SQR1_SQ16_3 (0x08U << ADC_SQR1_SQ16_Pos) /*!< 0x00040000 */
+#define ADC_SQR1_SQ16_4 (0x10U << ADC_SQR1_SQ16_Pos) /*!< 0x00080000 */
+
+#define ADC_SQR1_L_Pos (20U)
+#define ADC_SQR1_L_Msk (0xFU << ADC_SQR1_L_Pos) /*!< 0x00F00000 */
+#define ADC_SQR1_L ADC_SQR1_L_Msk /*!< ADC group regular sequencer scan length */
+#define ADC_SQR1_L_0 (0x1U << ADC_SQR1_L_Pos) /*!< 0x00100000 */
+#define ADC_SQR1_L_1 (0x2U << ADC_SQR1_L_Pos) /*!< 0x00200000 */
+#define ADC_SQR1_L_2 (0x4U << ADC_SQR1_L_Pos) /*!< 0x00400000 */
+#define ADC_SQR1_L_3 (0x8U << ADC_SQR1_L_Pos) /*!< 0x00800000 */
+
+/******************* Bit definition for ADC_SQR2 register *******************/
+#define ADC_SQR2_SQ7_Pos (0U)
+#define ADC_SQR2_SQ7_Msk (0x1FU << ADC_SQR2_SQ7_Pos) /*!< 0x0000001F */
+#define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk /*!< ADC group regular sequencer rank 7 */
+#define ADC_SQR2_SQ7_0 (0x01U << ADC_SQR2_SQ7_Pos) /*!< 0x00000001 */
+#define ADC_SQR2_SQ7_1 (0x02U << ADC_SQR2_SQ7_Pos) /*!< 0x00000002 */
+#define ADC_SQR2_SQ7_2 (0x04U << ADC_SQR2_SQ7_Pos) /*!< 0x00000004 */
+#define ADC_SQR2_SQ7_3 (0x08U << ADC_SQR2_SQ7_Pos) /*!< 0x00000008 */
+#define ADC_SQR2_SQ7_4 (0x10U << ADC_SQR2_SQ7_Pos) /*!< 0x00000010 */
+
+#define ADC_SQR2_SQ8_Pos (5U)
+#define ADC_SQR2_SQ8_Msk (0x1FU << ADC_SQR2_SQ8_Pos) /*!< 0x000003E0 */
+#define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk /*!< ADC group regular sequencer rank 8 */
+#define ADC_SQR2_SQ8_0 (0x01U << ADC_SQR2_SQ8_Pos) /*!< 0x00000020 */
+#define ADC_SQR2_SQ8_1 (0x02U << ADC_SQR2_SQ8_Pos) /*!< 0x00000040 */
+#define ADC_SQR2_SQ8_2 (0x04U << ADC_SQR2_SQ8_Pos) /*!< 0x00000080 */
+#define ADC_SQR2_SQ8_3 (0x08U << ADC_SQR2_SQ8_Pos) /*!< 0x00000100 */
+#define ADC_SQR2_SQ8_4 (0x10U << ADC_SQR2_SQ8_Pos) /*!< 0x00000200 */
+
+#define ADC_SQR2_SQ9_Pos (10U)
+#define ADC_SQR2_SQ9_Msk (0x1FU << ADC_SQR2_SQ9_Pos) /*!< 0x00007C00 */
+#define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk /*!< ADC group regular sequencer rank 9 */
+#define ADC_SQR2_SQ9_0 (0x01U << ADC_SQR2_SQ9_Pos) /*!< 0x00000400 */
+#define ADC_SQR2_SQ9_1 (0x02U << ADC_SQR2_SQ9_Pos) /*!< 0x00000800 */
+#define ADC_SQR2_SQ9_2 (0x04U << ADC_SQR2_SQ9_Pos) /*!< 0x00001000 */
+#define ADC_SQR2_SQ9_3 (0x08U << ADC_SQR2_SQ9_Pos) /*!< 0x00002000 */
+#define ADC_SQR2_SQ9_4 (0x10U << ADC_SQR2_SQ9_Pos) /*!< 0x00004000 */
+
+#define ADC_SQR2_SQ10_Pos (15U)
+#define ADC_SQR2_SQ10_Msk (0x1FU << ADC_SQR2_SQ10_Pos) /*!< 0x000F8000 */
+#define ADC_SQR2_SQ10 ADC_SQR2_SQ10_Msk /*!< ADC group regular sequencer rank 10 */
+#define ADC_SQR2_SQ10_0 (0x01U << ADC_SQR2_SQ10_Pos) /*!< 0x00008000 */
+#define ADC_SQR2_SQ10_1 (0x02U << ADC_SQR2_SQ10_Pos) /*!< 0x00010000 */
+#define ADC_SQR2_SQ10_2 (0x04U << ADC_SQR2_SQ10_Pos) /*!< 0x00020000 */
+#define ADC_SQR2_SQ10_3 (0x08U << ADC_SQR2_SQ10_Pos) /*!< 0x00040000 */
+#define ADC_SQR2_SQ10_4 (0x10U << ADC_SQR2_SQ10_Pos) /*!< 0x00080000 */
+
+#define ADC_SQR2_SQ11_Pos (20U)
+#define ADC_SQR2_SQ11_Msk (0x1FU << ADC_SQR2_SQ11_Pos) /*!< 0x01F00000 */
+#define ADC_SQR2_SQ11 ADC_SQR2_SQ11_Msk /*!< ADC group regular sequencer rank 1 */
+#define ADC_SQR2_SQ11_0 (0x01U << ADC_SQR2_SQ11_Pos) /*!< 0x00100000 */
+#define ADC_SQR2_SQ11_1 (0x02U << ADC_SQR2_SQ11_Pos) /*!< 0x00200000 */
+#define ADC_SQR2_SQ11_2 (0x04U << ADC_SQR2_SQ11_Pos) /*!< 0x00400000 */
+#define ADC_SQR2_SQ11_3 (0x08U << ADC_SQR2_SQ11_Pos) /*!< 0x00800000 */
+#define ADC_SQR2_SQ11_4 (0x10U << ADC_SQR2_SQ11_Pos) /*!< 0x01000000 */
+
+#define ADC_SQR2_SQ12_Pos (25U)
+#define ADC_SQR2_SQ12_Msk (0x1FU << ADC_SQR2_SQ12_Pos) /*!< 0x3E000000 */
+#define ADC_SQR2_SQ12 ADC_SQR2_SQ12_Msk /*!< ADC group regular sequencer rank 12 */
+#define ADC_SQR2_SQ12_0 (0x01U << ADC_SQR2_SQ12_Pos) /*!< 0x02000000 */
+#define ADC_SQR2_SQ12_1 (0x02U << ADC_SQR2_SQ12_Pos) /*!< 0x04000000 */
+#define ADC_SQR2_SQ12_2 (0x04U << ADC_SQR2_SQ12_Pos) /*!< 0x08000000 */
+#define ADC_SQR2_SQ12_3 (0x08U << ADC_SQR2_SQ12_Pos) /*!< 0x10000000 */
+#define ADC_SQR2_SQ12_4 (0x10U << ADC_SQR2_SQ12_Pos) /*!< 0x20000000 */
+
+/******************* Bit definition for ADC_SQR3 register *******************/
+#define ADC_SQR3_SQ1_Pos (0U)
+#define ADC_SQR3_SQ1_Msk (0x1FU << ADC_SQR3_SQ1_Pos) /*!< 0x0000001F */
+#define ADC_SQR3_SQ1 ADC_SQR3_SQ1_Msk /*!< ADC group regular sequencer rank 1 */
+#define ADC_SQR3_SQ1_0 (0x01U << ADC_SQR3_SQ1_Pos) /*!< 0x00000001 */
+#define ADC_SQR3_SQ1_1 (0x02U << ADC_SQR3_SQ1_Pos) /*!< 0x00000002 */
+#define ADC_SQR3_SQ1_2 (0x04U << ADC_SQR3_SQ1_Pos) /*!< 0x00000004 */
+#define ADC_SQR3_SQ1_3 (0x08U << ADC_SQR3_SQ1_Pos) /*!< 0x00000008 */
+#define ADC_SQR3_SQ1_4 (0x10U << ADC_SQR3_SQ1_Pos) /*!< 0x00000010 */
+
+#define ADC_SQR3_SQ2_Pos (5U)
+#define ADC_SQR3_SQ2_Msk (0x1FU << ADC_SQR3_SQ2_Pos) /*!< 0x000003E0 */
+#define ADC_SQR3_SQ2 ADC_SQR3_SQ2_Msk /*!< ADC group regular sequencer rank 2 */
+#define ADC_SQR3_SQ2_0 (0x01U << ADC_SQR3_SQ2_Pos) /*!< 0x00000020 */
+#define ADC_SQR3_SQ2_1 (0x02U << ADC_SQR3_SQ2_Pos) /*!< 0x00000040 */
+#define ADC_SQR3_SQ2_2 (0x04U << ADC_SQR3_SQ2_Pos) /*!< 0x00000080 */
+#define ADC_SQR3_SQ2_3 (0x08U << ADC_SQR3_SQ2_Pos) /*!< 0x00000100 */
+#define ADC_SQR3_SQ2_4 (0x10U << ADC_SQR3_SQ2_Pos) /*!< 0x00000200 */
+
+#define ADC_SQR3_SQ3_Pos (10U)
+#define ADC_SQR3_SQ3_Msk (0x1FU << ADC_SQR3_SQ3_Pos) /*!< 0x00007C00 */
+#define ADC_SQR3_SQ3 ADC_SQR3_SQ3_Msk /*!< ADC group regular sequencer rank 3 */
+#define ADC_SQR3_SQ3_0 (0x01U << ADC_SQR3_SQ3_Pos) /*!< 0x00000400 */
+#define ADC_SQR3_SQ3_1 (0x02U << ADC_SQR3_SQ3_Pos) /*!< 0x00000800 */
+#define ADC_SQR3_SQ3_2 (0x04U << ADC_SQR3_SQ3_Pos) /*!< 0x00001000 */
+#define ADC_SQR3_SQ3_3 (0x08U << ADC_SQR3_SQ3_Pos) /*!< 0x00002000 */
+#define ADC_SQR3_SQ3_4 (0x10U << ADC_SQR3_SQ3_Pos) /*!< 0x00004000 */
+
+#define ADC_SQR3_SQ4_Pos (15U)
+#define ADC_SQR3_SQ4_Msk (0x1FU << ADC_SQR3_SQ4_Pos) /*!< 0x000F8000 */
+#define ADC_SQR3_SQ4 ADC_SQR3_SQ4_Msk /*!< ADC group regular sequencer rank 4 */
+#define ADC_SQR3_SQ4_0 (0x01U << ADC_SQR3_SQ4_Pos) /*!< 0x00008000 */
+#define ADC_SQR3_SQ4_1 (0x02U << ADC_SQR3_SQ4_Pos) /*!< 0x00010000 */
+#define ADC_SQR3_SQ4_2 (0x04U << ADC_SQR3_SQ4_Pos) /*!< 0x00020000 */
+#define ADC_SQR3_SQ4_3 (0x08U << ADC_SQR3_SQ4_Pos) /*!< 0x00040000 */
+#define ADC_SQR3_SQ4_4 (0x10U << ADC_SQR3_SQ4_Pos) /*!< 0x00080000 */
+
+#define ADC_SQR3_SQ5_Pos (20U)
+#define ADC_SQR3_SQ5_Msk (0x1FU << ADC_SQR3_SQ5_Pos) /*!< 0x01F00000 */
+#define ADC_SQR3_SQ5 ADC_SQR3_SQ5_Msk /*!< ADC group regular sequencer rank 5 */
+#define ADC_SQR3_SQ5_0 (0x01U << ADC_SQR3_SQ5_Pos) /*!< 0x00100000 */
+#define ADC_SQR3_SQ5_1 (0x02U << ADC_SQR3_SQ5_Pos) /*!< 0x00200000 */
+#define ADC_SQR3_SQ5_2 (0x04U << ADC_SQR3_SQ5_Pos) /*!< 0x00400000 */
+#define ADC_SQR3_SQ5_3 (0x08U << ADC_SQR3_SQ5_Pos) /*!< 0x00800000 */
+#define ADC_SQR3_SQ5_4 (0x10U << ADC_SQR3_SQ5_Pos) /*!< 0x01000000 */
+
+#define ADC_SQR3_SQ6_Pos (25U)
+#define ADC_SQR3_SQ6_Msk (0x1FU << ADC_SQR3_SQ6_Pos) /*!< 0x3E000000 */
+#define ADC_SQR3_SQ6 ADC_SQR3_SQ6_Msk /*!< ADC group regular sequencer rank 6 */
+#define ADC_SQR3_SQ6_0 (0x01U << ADC_SQR3_SQ6_Pos) /*!< 0x02000000 */
+#define ADC_SQR3_SQ6_1 (0x02U << ADC_SQR3_SQ6_Pos) /*!< 0x04000000 */
+#define ADC_SQR3_SQ6_2 (0x04U << ADC_SQR3_SQ6_Pos) /*!< 0x08000000 */
+#define ADC_SQR3_SQ6_3 (0x08U << ADC_SQR3_SQ6_Pos) /*!< 0x10000000 */
+#define ADC_SQR3_SQ6_4 (0x10U << ADC_SQR3_SQ6_Pos) /*!< 0x20000000 */
+
+/******************* Bit definition for ADC_JSQR register *******************/
+#define ADC_JSQR_JSQ1_Pos (0U)
+#define ADC_JSQR_JSQ1_Msk (0x1FU << ADC_JSQR_JSQ1_Pos) /*!< 0x0000001F */
+#define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!< ADC group injected sequencer rank 1 */
+#define ADC_JSQR_JSQ1_0 (0x01U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000001 */
+#define ADC_JSQR_JSQ1_1 (0x02U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000002 */
+#define ADC_JSQR_JSQ1_2 (0x04U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000004 */
+#define ADC_JSQR_JSQ1_3 (0x08U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000008 */
+#define ADC_JSQR_JSQ1_4 (0x10U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000010 */
+
+#define ADC_JSQR_JSQ2_Pos (5U)
+#define ADC_JSQR_JSQ2_Msk (0x1FU << ADC_JSQR_JSQ2_Pos) /*!< 0x000003E0 */
+#define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!< ADC group injected sequencer rank 2 */
+#define ADC_JSQR_JSQ2_0 (0x01U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000020 */
+#define ADC_JSQR_JSQ2_1 (0x02U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000040 */
+#define ADC_JSQR_JSQ2_2 (0x04U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000080 */
+#define ADC_JSQR_JSQ2_3 (0x08U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000100 */
+#define ADC_JSQR_JSQ2_4 (0x10U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000200 */
+
+#define ADC_JSQR_JSQ3_Pos (10U)
+#define ADC_JSQR_JSQ3_Msk (0x1FU << ADC_JSQR_JSQ3_Pos) /*!< 0x00007C00 */
+#define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!< ADC group injected sequencer rank 3 */
+#define ADC_JSQR_JSQ3_0 (0x01U << ADC_JSQR_JSQ3_Pos) /*!< 0x00000400 */
+#define ADC_JSQR_JSQ3_1 (0x02U << ADC_JSQR_JSQ3_Pos) /*!< 0x00000800 */
+#define ADC_JSQR_JSQ3_2 (0x04U << ADC_JSQR_JSQ3_Pos) /*!< 0x00001000 */
+#define ADC_JSQR_JSQ3_3 (0x08U << ADC_JSQR_JSQ3_Pos) /*!< 0x00002000 */
+#define ADC_JSQR_JSQ3_4 (0x10U << ADC_JSQR_JSQ3_Pos) /*!< 0x00004000 */
+
+#define ADC_JSQR_JSQ4_Pos (15U)
+#define ADC_JSQR_JSQ4_Msk (0x1FU << ADC_JSQR_JSQ4_Pos) /*!< 0x000F8000 */
+#define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!< ADC group injected sequencer rank 4 */
+#define ADC_JSQR_JSQ4_0 (0x01U << ADC_JSQR_JSQ4_Pos) /*!< 0x00008000 */
+#define ADC_JSQR_JSQ4_1 (0x02U << ADC_JSQR_JSQ4_Pos) /*!< 0x00010000 */
+#define ADC_JSQR_JSQ4_2 (0x04U << ADC_JSQR_JSQ4_Pos) /*!< 0x00020000 */
+#define ADC_JSQR_JSQ4_3 (0x08U << ADC_JSQR_JSQ4_Pos) /*!< 0x00040000 */
+#define ADC_JSQR_JSQ4_4 (0x10U << ADC_JSQR_JSQ4_Pos) /*!< 0x00080000 */
+
+#define ADC_JSQR_JL_Pos (20U)
+#define ADC_JSQR_JL_Msk (0x3U << ADC_JSQR_JL_Pos) /*!< 0x00300000 */
+#define ADC_JSQR_JL ADC_JSQR_JL_Msk /*!< ADC group injected sequencer scan length */
+#define ADC_JSQR_JL_0 (0x1U << ADC_JSQR_JL_Pos) /*!< 0x00100000 */
+#define ADC_JSQR_JL_1 (0x2U << ADC_JSQR_JL_Pos) /*!< 0x00200000 */
+
+/******************* Bit definition for ADC_JDR1 register *******************/
+#define ADC_JDR1_JDATA_Pos (0U)
+#define ADC_JDR1_JDATA_Msk (0xFFFFU << ADC_JDR1_JDATA_Pos) /*!< 0x0000FFFF */
+#define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!< ADC group injected sequencer rank 1 conversion data */
+
+/******************* Bit definition for ADC_JDR2 register *******************/
+#define ADC_JDR2_JDATA_Pos (0U)
+#define ADC_JDR2_JDATA_Msk (0xFFFFU << ADC_JDR2_JDATA_Pos) /*!< 0x0000FFFF */
+#define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!< ADC group injected sequencer rank 2 conversion data */
+
+/******************* Bit definition for ADC_JDR3 register *******************/
+#define ADC_JDR3_JDATA_Pos (0U)
+#define ADC_JDR3_JDATA_Msk (0xFFFFU << ADC_JDR3_JDATA_Pos) /*!< 0x0000FFFF */
+#define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!< ADC group injected sequencer rank 3 conversion data */
+
+/******************* Bit definition for ADC_JDR4 register *******************/
+#define ADC_JDR4_JDATA_Pos (0U)
+#define ADC_JDR4_JDATA_Msk (0xFFFFU << ADC_JDR4_JDATA_Pos) /*!< 0x0000FFFF */
+#define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!< ADC group injected sequencer rank 4 conversion data */
+
+/******************** Bit definition for ADC_DR register ********************/
+#define ADC_DR_DATA_Pos (0U)
+#define ADC_DR_DATA_Msk (0xFFFFU << ADC_DR_DATA_Pos) /*!< 0x0000FFFF */
+#define ADC_DR_DATA ADC_DR_DATA_Msk /*!< ADC group regular conversion data */
+#define ADC_DR_ADC2DATA_Pos (16U)
+#define ADC_DR_ADC2DATA_Msk (0xFFFFU << ADC_DR_ADC2DATA_Pos) /*!< 0xFFFF0000 */
+#define ADC_DR_ADC2DATA ADC_DR_ADC2DATA_Msk /*!< ADC group regular conversion data for ADC slave, in multimode */
+/******************************************************************************/
+/* */
+/* Digital to Analog Converter */
+/* */
+/******************************************************************************/
+
+/******************** Bit definition for DAC_CR register ********************/
+#define DAC_CR_EN1_Pos (0U)
+#define DAC_CR_EN1_Msk (0x1U << DAC_CR_EN1_Pos) /*!< 0x00000001 */
+#define DAC_CR_EN1 DAC_CR_EN1_Msk /*!< DAC channel1 enable */
+#define DAC_CR_BOFF1_Pos (1U)
+#define DAC_CR_BOFF1_Msk (0x1U << DAC_CR_BOFF1_Pos) /*!< 0x00000002 */
+#define DAC_CR_BOFF1 DAC_CR_BOFF1_Msk /*!< DAC channel1 output buffer disable */
+#define DAC_CR_TEN1_Pos (2U)
+#define DAC_CR_TEN1_Msk (0x1U << DAC_CR_TEN1_Pos) /*!< 0x00000004 */
+#define DAC_CR_TEN1 DAC_CR_TEN1_Msk /*!< DAC channel1 Trigger enable */
+
+#define DAC_CR_TSEL1_Pos (3U)
+#define DAC_CR_TSEL1_Msk (0x7U << DAC_CR_TSEL1_Pos) /*!< 0x00000038 */
+#define DAC_CR_TSEL1 DAC_CR_TSEL1_Msk /*!< TSEL1[2:0] (DAC channel1 Trigger selection) */
+#define DAC_CR_TSEL1_0 (0x1U << DAC_CR_TSEL1_Pos) /*!< 0x00000008 */
+#define DAC_CR_TSEL1_1 (0x2U << DAC_CR_TSEL1_Pos) /*!< 0x00000010 */
+#define DAC_CR_TSEL1_2 (0x4U << DAC_CR_TSEL1_Pos) /*!< 0x00000020 */
+
+#define DAC_CR_WAVE1_Pos (6U)
+#define DAC_CR_WAVE1_Msk (0x3U << DAC_CR_WAVE1_Pos) /*!< 0x000000C0 */
+#define DAC_CR_WAVE1 DAC_CR_WAVE1_Msk /*!< WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
+#define DAC_CR_WAVE1_0 (0x1U << DAC_CR_WAVE1_Pos) /*!< 0x00000040 */
+#define DAC_CR_WAVE1_1 (0x2U << DAC_CR_WAVE1_Pos) /*!< 0x00000080 */
+
+#define DAC_CR_MAMP1_Pos (8U)
+#define DAC_CR_MAMP1_Msk (0xFU << DAC_CR_MAMP1_Pos) /*!< 0x00000F00 */
+#define DAC_CR_MAMP1 DAC_CR_MAMP1_Msk /*!< MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
+#define DAC_CR_MAMP1_0 (0x1U << DAC_CR_MAMP1_Pos) /*!< 0x00000100 */
+#define DAC_CR_MAMP1_1 (0x2U << DAC_CR_MAMP1_Pos) /*!< 0x00000200 */
+#define DAC_CR_MAMP1_2 (0x4U << DAC_CR_MAMP1_Pos) /*!< 0x00000400 */
+#define DAC_CR_MAMP1_3 (0x8U << DAC_CR_MAMP1_Pos) /*!< 0x00000800 */
+
+#define DAC_CR_DMAEN1_Pos (12U)
+#define DAC_CR_DMAEN1_Msk (0x1U << DAC_CR_DMAEN1_Pos) /*!< 0x00001000 */
+#define DAC_CR_DMAEN1 DAC_CR_DMAEN1_Msk /*!< DAC channel1 DMA enable */
+#define DAC_CR_EN2_Pos (16U)
+#define DAC_CR_EN2_Msk (0x1U << DAC_CR_EN2_Pos) /*!< 0x00010000 */
+#define DAC_CR_EN2 DAC_CR_EN2_Msk /*!< DAC channel2 enable */
+#define DAC_CR_BOFF2_Pos (17U)
+#define DAC_CR_BOFF2_Msk (0x1U << DAC_CR_BOFF2_Pos) /*!< 0x00020000 */
+#define DAC_CR_BOFF2 DAC_CR_BOFF2_Msk /*!< DAC channel2 output buffer disable */
+#define DAC_CR_TEN2_Pos (18U)
+#define DAC_CR_TEN2_Msk (0x1U << DAC_CR_TEN2_Pos) /*!< 0x00040000 */
+#define DAC_CR_TEN2 DAC_CR_TEN2_Msk /*!< DAC channel2 Trigger enable */
+
+#define DAC_CR_TSEL2_Pos (19U)
+#define DAC_CR_TSEL2_Msk (0x7U << DAC_CR_TSEL2_Pos) /*!< 0x00380000 */
+#define DAC_CR_TSEL2 DAC_CR_TSEL2_Msk /*!< TSEL2[2:0] (DAC channel2 Trigger selection) */
+#define DAC_CR_TSEL2_0 (0x1U << DAC_CR_TSEL2_Pos) /*!< 0x00080000 */
+#define DAC_CR_TSEL2_1 (0x2U << DAC_CR_TSEL2_Pos) /*!< 0x00100000 */
+#define DAC_CR_TSEL2_2 (0x4U << DAC_CR_TSEL2_Pos) /*!< 0x00200000 */
+
+#define DAC_CR_WAVE2_Pos (22U)
+#define DAC_CR_WAVE2_Msk (0x3U << DAC_CR_WAVE2_Pos) /*!< 0x00C00000 */
+#define DAC_CR_WAVE2 DAC_CR_WAVE2_Msk /*!< WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
+#define DAC_CR_WAVE2_0 (0x1U << DAC_CR_WAVE2_Pos) /*!< 0x00400000 */
+#define DAC_CR_WAVE2_1 (0x2U << DAC_CR_WAVE2_Pos) /*!< 0x00800000 */
+
+#define DAC_CR_MAMP2_Pos (24U)
+#define DAC_CR_MAMP2_Msk (0xFU << DAC_CR_MAMP2_Pos) /*!< 0x0F000000 */
+#define DAC_CR_MAMP2 DAC_CR_MAMP2_Msk /*!< MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
+#define DAC_CR_MAMP2_0 (0x1U << DAC_CR_MAMP2_Pos) /*!< 0x01000000 */
+#define DAC_CR_MAMP2_1 (0x2U << DAC_CR_MAMP2_Pos) /*!< 0x02000000 */
+#define DAC_CR_MAMP2_2 (0x4U << DAC_CR_MAMP2_Pos) /*!< 0x04000000 */
+#define DAC_CR_MAMP2_3 (0x8U << DAC_CR_MAMP2_Pos) /*!< 0x08000000 */
+
+#define DAC_CR_DMAEN2_Pos (28U)
+#define DAC_CR_DMAEN2_Msk (0x1U << DAC_CR_DMAEN2_Pos) /*!< 0x10000000 */
+#define DAC_CR_DMAEN2 DAC_CR_DMAEN2_Msk /*!< DAC channel2 DMA enabled */
+
+
+/***************** Bit definition for DAC_SWTRIGR register ******************/
+#define DAC_SWTRIGR_SWTRIG1_Pos (0U)
+#define DAC_SWTRIGR_SWTRIG1_Msk (0x1U << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */
+#define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /*!< DAC channel1 software trigger */
+#define DAC_SWTRIGR_SWTRIG2_Pos (1U)
+#define DAC_SWTRIGR_SWTRIG2_Msk (0x1U << DAC_SWTRIGR_SWTRIG2_Pos) /*!< 0x00000002 */
+#define DAC_SWTRIGR_SWTRIG2 DAC_SWTRIGR_SWTRIG2_Msk /*!< DAC channel2 software trigger */
+
+/***************** Bit definition for DAC_DHR12R1 register ******************/
+#define DAC_DHR12R1_DACC1DHR_Pos (0U)
+#define DAC_DHR12R1_DACC1DHR_Msk (0xFFFU << DAC_DHR12R1_DACC1DHR_Pos) /*!< 0x00000FFF */
+#define DAC_DHR12R1_DACC1DHR DAC_DHR12R1_DACC1DHR_Msk /*!< DAC channel1 12-bit Right aligned data */
+
+/***************** Bit definition for DAC_DHR12L1 register ******************/
+#define DAC_DHR12L1_DACC1DHR_Pos (4U)
+#define DAC_DHR12L1_DACC1DHR_Msk (0xFFFU << DAC_DHR12L1_DACC1DHR_Pos) /*!< 0x0000FFF0 */
+#define DAC_DHR12L1_DACC1DHR DAC_DHR12L1_DACC1DHR_Msk /*!< DAC channel1 12-bit Left aligned data */
+
+/****************** Bit definition for DAC_DHR8R1 register ******************/
+#define DAC_DHR8R1_DACC1DHR_Pos (0U)
+#define DAC_DHR8R1_DACC1DHR_Msk (0xFFU << DAC_DHR8R1_DACC1DHR_Pos) /*!< 0x000000FF */
+#define DAC_DHR8R1_DACC1DHR DAC_DHR8R1_DACC1DHR_Msk /*!< DAC channel1 8-bit Right aligned data */
+
+/***************** Bit definition for DAC_DHR12R2 register ******************/
+#define DAC_DHR12R2_DACC2DHR_Pos (0U)
+#define DAC_DHR12R2_DACC2DHR_Msk (0xFFFU << DAC_DHR12R2_DACC2DHR_Pos) /*!< 0x00000FFF */
+#define DAC_DHR12R2_DACC2DHR DAC_DHR12R2_DACC2DHR_Msk /*!< DAC channel2 12-bit Right aligned data */
+
+/***************** Bit definition for DAC_DHR12L2 register ******************/
+#define DAC_DHR12L2_DACC2DHR_Pos (4U)
+#define DAC_DHR12L2_DACC2DHR_Msk (0xFFFU << DAC_DHR12L2_DACC2DHR_Pos) /*!< 0x0000FFF0 */
+#define DAC_DHR12L2_DACC2DHR DAC_DHR12L2_DACC2DHR_Msk /*!< DAC channel2 12-bit Left aligned data */
+
+/****************** Bit definition for DAC_DHR8R2 register ******************/
+#define DAC_DHR8R2_DACC2DHR_Pos (0U)
+#define DAC_DHR8R2_DACC2DHR_Msk (0xFFU << DAC_DHR8R2_DACC2DHR_Pos) /*!< 0x000000FF */
+#define DAC_DHR8R2_DACC2DHR DAC_DHR8R2_DACC2DHR_Msk /*!< DAC channel2 8-bit Right aligned data */
+
+/***************** Bit definition for DAC_DHR12RD register ******************/
+#define DAC_DHR12RD_DACC1DHR_Pos (0U)
+#define DAC_DHR12RD_DACC1DHR_Msk (0xFFFU << DAC_DHR12RD_DACC1DHR_Pos) /*!< 0x00000FFF */
+#define DAC_DHR12RD_DACC1DHR DAC_DHR12RD_DACC1DHR_Msk /*!< DAC channel1 12-bit Right aligned data */
+#define DAC_DHR12RD_DACC2DHR_Pos (16U)
+#define DAC_DHR12RD_DACC2DHR_Msk (0xFFFU << DAC_DHR12RD_DACC2DHR_Pos) /*!< 0x0FFF0000 */
+#define DAC_DHR12RD_DACC2DHR DAC_DHR12RD_DACC2DHR_Msk /*!< DAC channel2 12-bit Right aligned data */
+
+/***************** Bit definition for DAC_DHR12LD register ******************/
+#define DAC_DHR12LD_DACC1DHR_Pos (4U)
+#define DAC_DHR12LD_DACC1DHR_Msk (0xFFFU << DAC_DHR12LD_DACC1DHR_Pos) /*!< 0x0000FFF0 */
+#define DAC_DHR12LD_DACC1DHR DAC_DHR12LD_DACC1DHR_Msk /*!< DAC channel1 12-bit Left aligned data */
+#define DAC_DHR12LD_DACC2DHR_Pos (20U)
+#define DAC_DHR12LD_DACC2DHR_Msk (0xFFFU << DAC_DHR12LD_DACC2DHR_Pos) /*!< 0xFFF00000 */
+#define DAC_DHR12LD_DACC2DHR DAC_DHR12LD_DACC2DHR_Msk /*!< DAC channel2 12-bit Left aligned data */
+
+/****************** Bit definition for DAC_DHR8RD register ******************/
+#define DAC_DHR8RD_DACC1DHR_Pos (0U)
+#define DAC_DHR8RD_DACC1DHR_Msk (0xFFU << DAC_DHR8RD_DACC1DHR_Pos) /*!< 0x000000FF */
+#define DAC_DHR8RD_DACC1DHR DAC_DHR8RD_DACC1DHR_Msk /*!< DAC channel1 8-bit Right aligned data */
+#define DAC_DHR8RD_DACC2DHR_Pos (8U)
+#define DAC_DHR8RD_DACC2DHR_Msk (0xFFU << DAC_DHR8RD_DACC2DHR_Pos) /*!< 0x0000FF00 */
+#define DAC_DHR8RD_DACC2DHR DAC_DHR8RD_DACC2DHR_Msk /*!< DAC channel2 8-bit Right aligned data */
+
+/******************* Bit definition for DAC_DOR1 register *******************/
+#define DAC_DOR1_DACC1DOR_Pos (0U)
+#define DAC_DOR1_DACC1DOR_Msk (0xFFFU << DAC_DOR1_DACC1DOR_Pos) /*!< 0x00000FFF */
+#define DAC_DOR1_DACC1DOR DAC_DOR1_DACC1DOR_Msk /*!< DAC channel1 data output */
+
+/******************* Bit definition for DAC_DOR2 register *******************/
+#define DAC_DOR2_DACC2DOR_Pos (0U)
+#define DAC_DOR2_DACC2DOR_Msk (0xFFFU << DAC_DOR2_DACC2DOR_Pos) /*!< 0x00000FFF */
+#define DAC_DOR2_DACC2DOR DAC_DOR2_DACC2DOR_Msk /*!< DAC channel2 data output */
+
+
+
+/*****************************************************************************/
+/* */
+/* Timers (TIM) */
+/* */
+/*****************************************************************************/
+/******************* Bit definition for TIM_CR1 register *******************/
+#define TIM_CR1_CEN_Pos (0U)
+#define TIM_CR1_CEN_Msk (0x1U << TIM_CR1_CEN_Pos) /*!< 0x00000001 */
+#define TIM_CR1_CEN TIM_CR1_CEN_Msk /*!<Counter enable */
+#define TIM_CR1_UDIS_Pos (1U)
+#define TIM_CR1_UDIS_Msk (0x1U << TIM_CR1_UDIS_Pos) /*!< 0x00000002 */
+#define TIM_CR1_UDIS TIM_CR1_UDIS_Msk /*!<Update disable */
+#define TIM_CR1_URS_Pos (2U)
+#define TIM_CR1_URS_Msk (0x1U << TIM_CR1_URS_Pos) /*!< 0x00000004 */
+#define TIM_CR1_URS TIM_CR1_URS_Msk /*!<Update request source */
+#define TIM_CR1_OPM_Pos (3U)
+#define TIM_CR1_OPM_Msk (0x1U << TIM_CR1_OPM_Pos) /*!< 0x00000008 */
+#define TIM_CR1_OPM TIM_CR1_OPM_Msk /*!<One pulse mode */
+#define TIM_CR1_DIR_Pos (4U)
+#define TIM_CR1_DIR_Msk (0x1U << TIM_CR1_DIR_Pos) /*!< 0x00000010 */
+#define TIM_CR1_DIR TIM_CR1_DIR_Msk /*!<Direction */
+
+#define TIM_CR1_CMS_Pos (5U)
+#define TIM_CR1_CMS_Msk (0x3U << TIM_CR1_CMS_Pos) /*!< 0x00000060 */
+#define TIM_CR1_CMS TIM_CR1_CMS_Msk /*!<CMS[1:0] bits (Center-aligned mode selection) */
+#define TIM_CR1_CMS_0 (0x1U << TIM_CR1_CMS_Pos) /*!< 0x00000020 */
+#define TIM_CR1_CMS_1 (0x2U << TIM_CR1_CMS_Pos) /*!< 0x00000040 */
+
+#define TIM_CR1_ARPE_Pos (7U)
+#define TIM_CR1_ARPE_Msk (0x1U << TIM_CR1_ARPE_Pos) /*!< 0x00000080 */
+#define TIM_CR1_ARPE TIM_CR1_ARPE_Msk /*!<Auto-reload preload enable */
+
+#define TIM_CR1_CKD_Pos (8U)
+#define TIM_CR1_CKD_Msk (0x3U << TIM_CR1_CKD_Pos) /*!< 0x00000300 */
+#define TIM_CR1_CKD TIM_CR1_CKD_Msk /*!<CKD[1:0] bits (clock division) */
+#define TIM_CR1_CKD_0 (0x1U << TIM_CR1_CKD_Pos) /*!< 0x00000100 */
+#define TIM_CR1_CKD_1 (0x2U << TIM_CR1_CKD_Pos) /*!< 0x00000200 */
+
+/******************* Bit definition for TIM_CR2 register *******************/
+#define TIM_CR2_CCPC_Pos (0U)
+#define TIM_CR2_CCPC_Msk (0x1U << TIM_CR2_CCPC_Pos) /*!< 0x00000001 */
+#define TIM_CR2_CCPC TIM_CR2_CCPC_Msk /*!<Capture/Compare Preloaded Control */
+#define TIM_CR2_CCUS_Pos (2U)
+#define TIM_CR2_CCUS_Msk (0x1U << TIM_CR2_CCUS_Pos) /*!< 0x00000004 */
+#define TIM_CR2_CCUS TIM_CR2_CCUS_Msk /*!<Capture/Compare Control Update Selection */
+#define TIM_CR2_CCDS_Pos (3U)
+#define TIM_CR2_CCDS_Msk (0x1U << TIM_CR2_CCDS_Pos) /*!< 0x00000008 */
+#define TIM_CR2_CCDS TIM_CR2_CCDS_Msk /*!<Capture/Compare DMA Selection */
+
+#define TIM_CR2_MMS_Pos (4U)
+#define TIM_CR2_MMS_Msk (0x7U << TIM_CR2_MMS_Pos) /*!< 0x00000070 */
+#define TIM_CR2_MMS TIM_CR2_MMS_Msk /*!<MMS[2:0] bits (Master Mode Selection) */
+#define TIM_CR2_MMS_0 (0x1U << TIM_CR2_MMS_Pos) /*!< 0x00000010 */
+#define TIM_CR2_MMS_1 (0x2U << TIM_CR2_MMS_Pos) /*!< 0x00000020 */
+#define TIM_CR2_MMS_2 (0x4U << TIM_CR2_MMS_Pos) /*!< 0x00000040 */
+
+#define TIM_CR2_TI1S_Pos (7U)
+#define TIM_CR2_TI1S_Msk (0x1U << TIM_CR2_TI1S_Pos) /*!< 0x00000080 */
+#define TIM_CR2_TI1S TIM_CR2_TI1S_Msk /*!<TI1 Selection */
+#define TIM_CR2_OIS1_Pos (8U)
+#define TIM_CR2_OIS1_Msk (0x1U << TIM_CR2_OIS1_Pos) /*!< 0x00000100 */
+#define TIM_CR2_OIS1 TIM_CR2_OIS1_Msk /*!<Output Idle state 1 (OC1 output) */
+#define TIM_CR2_OIS1N_Pos (9U)
+#define TIM_CR2_OIS1N_Msk (0x1U << TIM_CR2_OIS1N_Pos) /*!< 0x00000200 */
+#define TIM_CR2_OIS1N TIM_CR2_OIS1N_Msk /*!<Output Idle state 1 (OC1N output) */
+#define TIM_CR2_OIS2_Pos (10U)
+#define TIM_CR2_OIS2_Msk (0x1U << TIM_CR2_OIS2_Pos) /*!< 0x00000400 */
+#define TIM_CR2_OIS2 TIM_CR2_OIS2_Msk /*!<Output Idle state 2 (OC2 output) */
+#define TIM_CR2_OIS2N_Pos (11U)
+#define TIM_CR2_OIS2N_Msk (0x1U << TIM_CR2_OIS2N_Pos) /*!< 0x00000800 */
+#define TIM_CR2_OIS2N TIM_CR2_OIS2N_Msk /*!<Output Idle state 2 (OC2N output) */
+#define TIM_CR2_OIS3_Pos (12U)
+#define TIM_CR2_OIS3_Msk (0x1U << TIM_CR2_OIS3_Pos) /*!< 0x00001000 */
+#define TIM_CR2_OIS3 TIM_CR2_OIS3_Msk /*!<Output Idle state 3 (OC3 output) */
+#define TIM_CR2_OIS3N_Pos (13U)
+#define TIM_CR2_OIS3N_Msk (0x1U << TIM_CR2_OIS3N_Pos) /*!< 0x00002000 */
+#define TIM_CR2_OIS3N TIM_CR2_OIS3N_Msk /*!<Output Idle state 3 (OC3N output) */
+#define TIM_CR2_OIS4_Pos (14U)
+#define TIM_CR2_OIS4_Msk (0x1U << TIM_CR2_OIS4_Pos) /*!< 0x00004000 */
+#define TIM_CR2_OIS4 TIM_CR2_OIS4_Msk /*!<Output Idle state 4 (OC4 output) */
+
+/******************* Bit definition for TIM_SMCR register ******************/
+#define TIM_SMCR_SMS_Pos (0U)
+#define TIM_SMCR_SMS_Msk (0x7U << TIM_SMCR_SMS_Pos) /*!< 0x00000007 */
+#define TIM_SMCR_SMS TIM_SMCR_SMS_Msk /*!<SMS[2:0] bits (Slave mode selection) */
+#define TIM_SMCR_SMS_0 (0x1U << TIM_SMCR_SMS_Pos) /*!< 0x00000001 */
+#define TIM_SMCR_SMS_1 (0x2U << TIM_SMCR_SMS_Pos) /*!< 0x00000002 */
+#define TIM_SMCR_SMS_2 (0x4U << TIM_SMCR_SMS_Pos) /*!< 0x00000004 */
+
+#define TIM_SMCR_OCCS_Pos (3U)
+#define TIM_SMCR_OCCS_Msk (0x1U << TIM_SMCR_OCCS_Pos) /*!< 0x00000008 */
+#define TIM_SMCR_OCCS TIM_SMCR_OCCS_Msk /*!< OCREF clear selection */
+
+#define TIM_SMCR_TS_Pos (4U)
+#define TIM_SMCR_TS_Msk (0x7U << TIM_SMCR_TS_Pos) /*!< 0x00000070 */
+#define TIM_SMCR_TS TIM_SMCR_TS_Msk /*!<TS[2:0] bits (Trigger selection) */
+#define TIM_SMCR_TS_0 (0x1U << TIM_SMCR_TS_Pos) /*!< 0x00000010 */
+#define TIM_SMCR_TS_1 (0x2U << TIM_SMCR_TS_Pos) /*!< 0x00000020 */
+#define TIM_SMCR_TS_2 (0x4U << TIM_SMCR_TS_Pos) /*!< 0x00000040 */
+
+#define TIM_SMCR_MSM_Pos (7U)
+#define TIM_SMCR_MSM_Msk (0x1U << TIM_SMCR_MSM_Pos) /*!< 0x00000080 */
+#define TIM_SMCR_MSM TIM_SMCR_MSM_Msk /*!<Master/slave mode */
+
+#define TIM_SMCR_ETF_Pos (8U)
+#define TIM_SMCR_ETF_Msk (0xFU << TIM_SMCR_ETF_Pos) /*!< 0x00000F00 */
+#define TIM_SMCR_ETF TIM_SMCR_ETF_Msk /*!<ETF[3:0] bits (External trigger filter) */
+#define TIM_SMCR_ETF_0 (0x1U << TIM_SMCR_ETF_Pos) /*!< 0x00000100 */
+#define TIM_SMCR_ETF_1 (0x2U << TIM_SMCR_ETF_Pos) /*!< 0x00000200 */
+#define TIM_SMCR_ETF_2 (0x4U << TIM_SMCR_ETF_Pos) /*!< 0x00000400 */
+#define TIM_SMCR_ETF_3 (0x8U << TIM_SMCR_ETF_Pos) /*!< 0x00000800 */
+
+#define TIM_SMCR_ETPS_Pos (12U)
+#define TIM_SMCR_ETPS_Msk (0x3U << TIM_SMCR_ETPS_Pos) /*!< 0x00003000 */
+#define TIM_SMCR_ETPS TIM_SMCR_ETPS_Msk /*!<ETPS[1:0] bits (External trigger prescaler) */
+#define TIM_SMCR_ETPS_0 (0x1U << TIM_SMCR_ETPS_Pos) /*!< 0x00001000 */
+#define TIM_SMCR_ETPS_1 (0x2U << TIM_SMCR_ETPS_Pos) /*!< 0x00002000 */
+
+#define TIM_SMCR_ECE_Pos (14U)
+#define TIM_SMCR_ECE_Msk (0x1U << TIM_SMCR_ECE_Pos) /*!< 0x00004000 */
+#define TIM_SMCR_ECE TIM_SMCR_ECE_Msk /*!<External clock enable */
+#define TIM_SMCR_ETP_Pos (15U)
+#define TIM_SMCR_ETP_Msk (0x1U << TIM_SMCR_ETP_Pos) /*!< 0x00008000 */
+#define TIM_SMCR_ETP TIM_SMCR_ETP_Msk /*!<External trigger polarity */
+
+/******************* Bit definition for TIM_DIER register ******************/
+#define TIM_DIER_UIE_Pos (0U)
+#define TIM_DIER_UIE_Msk (0x1U << TIM_DIER_UIE_Pos) /*!< 0x00000001 */
+#define TIM_DIER_UIE TIM_DIER_UIE_Msk /*!<Update interrupt enable */
+#define TIM_DIER_CC1IE_Pos (1U)
+#define TIM_DIER_CC1IE_Msk (0x1U << TIM_DIER_CC1IE_Pos) /*!< 0x00000002 */
+#define TIM_DIER_CC1IE TIM_DIER_CC1IE_Msk /*!<Capture/Compare 1 interrupt enable */
+#define TIM_DIER_CC2IE_Pos (2U)
+#define TIM_DIER_CC2IE_Msk (0x1U << TIM_DIER_CC2IE_Pos) /*!< 0x00000004 */
+#define TIM_DIER_CC2IE TIM_DIER_CC2IE_Msk /*!<Capture/Compare 2 interrupt enable */
+#define TIM_DIER_CC3IE_Pos (3U)
+#define TIM_DIER_CC3IE_Msk (0x1U << TIM_DIER_CC3IE_Pos) /*!< 0x00000008 */
+#define TIM_DIER_CC3IE TIM_DIER_CC3IE_Msk /*!<Capture/Compare 3 interrupt enable */
+#define TIM_DIER_CC4IE_Pos (4U)
+#define TIM_DIER_CC4IE_Msk (0x1U << TIM_DIER_CC4IE_Pos) /*!< 0x00000010 */
+#define TIM_DIER_CC4IE TIM_DIER_CC4IE_Msk /*!<Capture/Compare 4 interrupt enable */
+#define TIM_DIER_COMIE_Pos (5U)
+#define TIM_DIER_COMIE_Msk (0x1U << TIM_DIER_COMIE_Pos) /*!< 0x00000020 */
+#define TIM_DIER_COMIE TIM_DIER_COMIE_Msk /*!<COM interrupt enable */
+#define TIM_DIER_TIE_Pos (6U)
+#define TIM_DIER_TIE_Msk (0x1U << TIM_DIER_TIE_Pos) /*!< 0x00000040 */
+#define TIM_DIER_TIE TIM_DIER_TIE_Msk /*!<Trigger interrupt enable */
+#define TIM_DIER_BIE_Pos (7U)
+#define TIM_DIER_BIE_Msk (0x1U << TIM_DIER_BIE_Pos) /*!< 0x00000080 */
+#define TIM_DIER_BIE TIM_DIER_BIE_Msk /*!<Break interrupt enable */
+#define TIM_DIER_UDE_Pos (8U)
+#define TIM_DIER_UDE_Msk (0x1U << TIM_DIER_UDE_Pos) /*!< 0x00000100 */
+#define TIM_DIER_UDE TIM_DIER_UDE_Msk /*!<Update DMA request enable */
+#define TIM_DIER_CC1DE_Pos (9U)
+#define TIM_DIER_CC1DE_Msk (0x1U << TIM_DIER_CC1DE_Pos) /*!< 0x00000200 */
+#define TIM_DIER_CC1DE TIM_DIER_CC1DE_Msk /*!<Capture/Compare 1 DMA request enable */
+#define TIM_DIER_CC2DE_Pos (10U)
+#define TIM_DIER_CC2DE_Msk (0x1U << TIM_DIER_CC2DE_Pos) /*!< 0x00000400 */
+#define TIM_DIER_CC2DE TIM_DIER_CC2DE_Msk /*!<Capture/Compare 2 DMA request enable */
+#define TIM_DIER_CC3DE_Pos (11U)
+#define TIM_DIER_CC3DE_Msk (0x1U << TIM_DIER_CC3DE_Pos) /*!< 0x00000800 */
+#define TIM_DIER_CC3DE TIM_DIER_CC3DE_Msk /*!<Capture/Compare 3 DMA request enable */
+#define TIM_DIER_CC4DE_Pos (12U)
+#define TIM_DIER_CC4DE_Msk (0x1U << TIM_DIER_CC4DE_Pos) /*!< 0x00001000 */
+#define TIM_DIER_CC4DE TIM_DIER_CC4DE_Msk /*!<Capture/Compare 4 DMA request enable */
+#define TIM_DIER_COMDE_Pos (13U)
+#define TIM_DIER_COMDE_Msk (0x1U << TIM_DIER_COMDE_Pos) /*!< 0x00002000 */
+#define TIM_DIER_COMDE TIM_DIER_COMDE_Msk /*!<COM DMA request enable */
+#define TIM_DIER_TDE_Pos (14U)
+#define TIM_DIER_TDE_Msk (0x1U << TIM_DIER_TDE_Pos) /*!< 0x00004000 */
+#define TIM_DIER_TDE TIM_DIER_TDE_Msk /*!<Trigger DMA request enable */
+
+/******************** Bit definition for TIM_SR register *******************/
+#define TIM_SR_UIF_Pos (0U)
+#define TIM_SR_UIF_Msk (0x1U << TIM_SR_UIF_Pos) /*!< 0x00000001 */
+#define TIM_SR_UIF TIM_SR_UIF_Msk /*!<Update interrupt Flag */
+#define TIM_SR_CC1IF_Pos (1U)
+#define TIM_SR_CC1IF_Msk (0x1U << TIM_SR_CC1IF_Pos) /*!< 0x00000002 */
+#define TIM_SR_CC1IF TIM_SR_CC1IF_Msk /*!<Capture/Compare 1 interrupt Flag */
+#define TIM_SR_CC2IF_Pos (2U)
+#define TIM_SR_CC2IF_Msk (0x1U << TIM_SR_CC2IF_Pos) /*!< 0x00000004 */
+#define TIM_SR_CC2IF TIM_SR_CC2IF_Msk /*!<Capture/Compare 2 interrupt Flag */
+#define TIM_SR_CC3IF_Pos (3U)
+#define TIM_SR_CC3IF_Msk (0x1U << TIM_SR_CC3IF_Pos) /*!< 0x00000008 */
+#define TIM_SR_CC3IF TIM_SR_CC3IF_Msk /*!<Capture/Compare 3 interrupt Flag */
+#define TIM_SR_CC4IF_Pos (4U)
+#define TIM_SR_CC4IF_Msk (0x1U << TIM_SR_CC4IF_Pos) /*!< 0x00000010 */
+#define TIM_SR_CC4IF TIM_SR_CC4IF_Msk /*!<Capture/Compare 4 interrupt Flag */
+#define TIM_SR_COMIF_Pos (5U)
+#define TIM_SR_COMIF_Msk (0x1U << TIM_SR_COMIF_Pos) /*!< 0x00000020 */
+#define TIM_SR_COMIF TIM_SR_COMIF_Msk /*!<COM interrupt Flag */
+#define TIM_SR_TIF_Pos (6U)
+#define TIM_SR_TIF_Msk (0x1U << TIM_SR_TIF_Pos) /*!< 0x00000040 */
+#define TIM_SR_TIF TIM_SR_TIF_Msk /*!<Trigger interrupt Flag */
+#define TIM_SR_BIF_Pos (7U)
+#define TIM_SR_BIF_Msk (0x1U << TIM_SR_BIF_Pos) /*!< 0x00000080 */
+#define TIM_SR_BIF TIM_SR_BIF_Msk /*!<Break interrupt Flag */
+#define TIM_SR_CC1OF_Pos (9U)
+#define TIM_SR_CC1OF_Msk (0x1U << TIM_SR_CC1OF_Pos) /*!< 0x00000200 */
+#define TIM_SR_CC1OF TIM_SR_CC1OF_Msk /*!<Capture/Compare 1 Overcapture Flag */
+#define TIM_SR_CC2OF_Pos (10U)
+#define TIM_SR_CC2OF_Msk (0x1U << TIM_SR_CC2OF_Pos) /*!< 0x00000400 */
+#define TIM_SR_CC2OF TIM_SR_CC2OF_Msk /*!<Capture/Compare 2 Overcapture Flag */
+#define TIM_SR_CC3OF_Pos (11U)
+#define TIM_SR_CC3OF_Msk (0x1U << TIM_SR_CC3OF_Pos) /*!< 0x00000800 */
+#define TIM_SR_CC3OF TIM_SR_CC3OF_Msk /*!<Capture/Compare 3 Overcapture Flag */
+#define TIM_SR_CC4OF_Pos (12U)
+#define TIM_SR_CC4OF_Msk (0x1U << TIM_SR_CC4OF_Pos) /*!< 0x00001000 */
+#define TIM_SR_CC4OF TIM_SR_CC4OF_Msk /*!<Capture/Compare 4 Overcapture Flag */
+
+/******************* Bit definition for TIM_EGR register *******************/
+#define TIM_EGR_UG_Pos (0U)
+#define TIM_EGR_UG_Msk (0x1U << TIM_EGR_UG_Pos) /*!< 0x00000001 */
+#define TIM_EGR_UG TIM_EGR_UG_Msk /*!<Update Generation */
+#define TIM_EGR_CC1G_Pos (1U)
+#define TIM_EGR_CC1G_Msk (0x1U << TIM_EGR_CC1G_Pos) /*!< 0x00000002 */
+#define TIM_EGR_CC1G TIM_EGR_CC1G_Msk /*!<Capture/Compare 1 Generation */
+#define TIM_EGR_CC2G_Pos (2U)
+#define TIM_EGR_CC2G_Msk (0x1U << TIM_EGR_CC2G_Pos) /*!< 0x00000004 */
+#define TIM_EGR_CC2G TIM_EGR_CC2G_Msk /*!<Capture/Compare 2 Generation */
+#define TIM_EGR_CC3G_Pos (3U)
+#define TIM_EGR_CC3G_Msk (0x1U << TIM_EGR_CC3G_Pos) /*!< 0x00000008 */
+#define TIM_EGR_CC3G TIM_EGR_CC3G_Msk /*!<Capture/Compare 3 Generation */
+#define TIM_EGR_CC4G_Pos (4U)
+#define TIM_EGR_CC4G_Msk (0x1U << TIM_EGR_CC4G_Pos) /*!< 0x00000010 */
+#define TIM_EGR_CC4G TIM_EGR_CC4G_Msk /*!<Capture/Compare 4 Generation */
+#define TIM_EGR_COMG_Pos (5U)
+#define TIM_EGR_COMG_Msk (0x1U << TIM_EGR_COMG_Pos) /*!< 0x00000020 */
+#define TIM_EGR_COMG TIM_EGR_COMG_Msk /*!<Capture/Compare Control Update Generation */
+#define TIM_EGR_TG_Pos (6U)
+#define TIM_EGR_TG_Msk (0x1U << TIM_EGR_TG_Pos) /*!< 0x00000040 */
+#define TIM_EGR_TG TIM_EGR_TG_Msk /*!<Trigger Generation */
+#define TIM_EGR_BG_Pos (7U)
+#define TIM_EGR_BG_Msk (0x1U << TIM_EGR_BG_Pos) /*!< 0x00000080 */
+#define TIM_EGR_BG TIM_EGR_BG_Msk /*!<Break Generation */
+
+/****************** Bit definition for TIM_CCMR1 register ******************/
+#define TIM_CCMR1_CC1S_Pos (0U)
+#define TIM_CCMR1_CC1S_Msk (0x3U << TIM_CCMR1_CC1S_Pos) /*!< 0x00000003 */
+#define TIM_CCMR1_CC1S TIM_CCMR1_CC1S_Msk /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
+#define TIM_CCMR1_CC1S_0 (0x1U << TIM_CCMR1_CC1S_Pos) /*!< 0x00000001 */
+#define TIM_CCMR1_CC1S_1 (0x2U << TIM_CCMR1_CC1S_Pos) /*!< 0x00000002 */
+
+#define TIM_CCMR1_OC1FE_Pos (2U)
+#define TIM_CCMR1_OC1FE_Msk (0x1U << TIM_CCMR1_OC1FE_Pos) /*!< 0x00000004 */
+#define TIM_CCMR1_OC1FE TIM_CCMR1_OC1FE_Msk /*!<Output Compare 1 Fast enable */
+#define TIM_CCMR1_OC1PE_Pos (3U)
+#define TIM_CCMR1_OC1PE_Msk (0x1U << TIM_CCMR1_OC1PE_Pos) /*!< 0x00000008 */
+#define TIM_CCMR1_OC1PE TIM_CCMR1_OC1PE_Msk /*!<Output Compare 1 Preload enable */
+
+#define TIM_CCMR1_OC1M_Pos (4U)
+#define TIM_CCMR1_OC1M_Msk (0x7U << TIM_CCMR1_OC1M_Pos) /*!< 0x00000070 */
+#define TIM_CCMR1_OC1M TIM_CCMR1_OC1M_Msk /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
+#define TIM_CCMR1_OC1M_0 (0x1U << TIM_CCMR1_OC1M_Pos) /*!< 0x00000010 */
+#define TIM_CCMR1_OC1M_1 (0x2U << TIM_CCMR1_OC1M_Pos) /*!< 0x00000020 */
+#define TIM_CCMR1_OC1M_2 (0x4U << TIM_CCMR1_OC1M_Pos) /*!< 0x00000040 */
+
+#define TIM_CCMR1_OC1CE_Pos (7U)
+#define TIM_CCMR1_OC1CE_Msk (0x1U << TIM_CCMR1_OC1CE_Pos) /*!< 0x00000080 */
+#define TIM_CCMR1_OC1CE TIM_CCMR1_OC1CE_Msk /*!<Output Compare 1Clear Enable */
+
+#define TIM_CCMR1_CC2S_Pos (8U)
+#define TIM_CCMR1_CC2S_Msk (0x3U << TIM_CCMR1_CC2S_Pos) /*!< 0x00000300 */
+#define TIM_CCMR1_CC2S TIM_CCMR1_CC2S_Msk /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
+#define TIM_CCMR1_CC2S_0 (0x1U << TIM_CCMR1_CC2S_Pos) /*!< 0x00000100 */
+#define TIM_CCMR1_CC2S_1 (0x2U << TIM_CCMR1_CC2S_Pos) /*!< 0x00000200 */
+
+#define TIM_CCMR1_OC2FE_Pos (10U)
+#define TIM_CCMR1_OC2FE_Msk (0x1U << TIM_CCMR1_OC2FE_Pos) /*!< 0x00000400 */
+#define TIM_CCMR1_OC2FE TIM_CCMR1_OC2FE_Msk /*!<Output Compare 2 Fast enable */
+#define TIM_CCMR1_OC2PE_Pos (11U)
+#define TIM_CCMR1_OC2PE_Msk (0x1U << TIM_CCMR1_OC2PE_Pos) /*!< 0x00000800 */
+#define TIM_CCMR1_OC2PE TIM_CCMR1_OC2PE_Msk /*!<Output Compare 2 Preload enable */
+
+#define TIM_CCMR1_OC2M_Pos (12U)
+#define TIM_CCMR1_OC2M_Msk (0x7U << TIM_CCMR1_OC2M_Pos) /*!< 0x00007000 */
+#define TIM_CCMR1_OC2M TIM_CCMR1_OC2M_Msk /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
+#define TIM_CCMR1_OC2M_0 (0x1U << TIM_CCMR1_OC2M_Pos) /*!< 0x00001000 */
+#define TIM_CCMR1_OC2M_1 (0x2U << TIM_CCMR1_OC2M_Pos) /*!< 0x00002000 */
+#define TIM_CCMR1_OC2M_2 (0x4U << TIM_CCMR1_OC2M_Pos) /*!< 0x00004000 */
+
+#define TIM_CCMR1_OC2CE_Pos (15U)
+#define TIM_CCMR1_OC2CE_Msk (0x1U << TIM_CCMR1_OC2CE_Pos) /*!< 0x00008000 */
+#define TIM_CCMR1_OC2CE TIM_CCMR1_OC2CE_Msk /*!<Output Compare 2 Clear Enable */
+
+/*---------------------------------------------------------------------------*/
+
+#define TIM_CCMR1_IC1PSC_Pos (2U)
+#define TIM_CCMR1_IC1PSC_Msk (0x3U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x0000000C */
+#define TIM_CCMR1_IC1PSC TIM_CCMR1_IC1PSC_Msk /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
+#define TIM_CCMR1_IC1PSC_0 (0x1U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x00000004 */
+#define TIM_CCMR1_IC1PSC_1 (0x2U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x00000008 */
+
+#define TIM_CCMR1_IC1F_Pos (4U)
+#define TIM_CCMR1_IC1F_Msk (0xFU << TIM_CCMR1_IC1F_Pos) /*!< 0x000000F0 */
+#define TIM_CCMR1_IC1F TIM_CCMR1_IC1F_Msk /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
+#define TIM_CCMR1_IC1F_0 (0x1U << TIM_CCMR1_IC1F_Pos) /*!< 0x00000010 */
+#define TIM_CCMR1_IC1F_1 (0x2U << TIM_CCMR1_IC1F_Pos) /*!< 0x00000020 */
+#define TIM_CCMR1_IC1F_2 (0x4U << TIM_CCMR1_IC1F_Pos) /*!< 0x00000040 */
+#define TIM_CCMR1_IC1F_3 (0x8U << TIM_CCMR1_IC1F_Pos) /*!< 0x00000080 */
+
+#define TIM_CCMR1_IC2PSC_Pos (10U)
+#define TIM_CCMR1_IC2PSC_Msk (0x3U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000C00 */
+#define TIM_CCMR1_IC2PSC TIM_CCMR1_IC2PSC_Msk /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
+#define TIM_CCMR1_IC2PSC_0 (0x1U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000400 */
+#define TIM_CCMR1_IC2PSC_1 (0x2U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000800 */
+
+#define TIM_CCMR1_IC2F_Pos (12U)
+#define TIM_CCMR1_IC2F_Msk (0xFU << TIM_CCMR1_IC2F_Pos) /*!< 0x0000F000 */
+#define TIM_CCMR1_IC2F TIM_CCMR1_IC2F_Msk /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
+#define TIM_CCMR1_IC2F_0 (0x1U << TIM_CCMR1_IC2F_Pos) /*!< 0x00001000 */
+#define TIM_CCMR1_IC2F_1 (0x2U << TIM_CCMR1_IC2F_Pos) /*!< 0x00002000 */
+#define TIM_CCMR1_IC2F_2 (0x4U << TIM_CCMR1_IC2F_Pos) /*!< 0x00004000 */
+#define TIM_CCMR1_IC2F_3 (0x8U << TIM_CCMR1_IC2F_Pos) /*!< 0x00008000 */
+
+/****************** Bit definition for TIM_CCMR2 register ******************/
+#define TIM_CCMR2_CC3S_Pos (0U)
+#define TIM_CCMR2_CC3S_Msk (0x3U << TIM_CCMR2_CC3S_Pos) /*!< 0x00000003 */
+#define TIM_CCMR2_CC3S TIM_CCMR2_CC3S_Msk /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
+#define TIM_CCMR2_CC3S_0 (0x1U << TIM_CCMR2_CC3S_Pos) /*!< 0x00000001 */
+#define TIM_CCMR2_CC3S_1 (0x2U << TIM_CCMR2_CC3S_Pos) /*!< 0x00000002 */
+
+#define TIM_CCMR2_OC3FE_Pos (2U)
+#define TIM_CCMR2_OC3FE_Msk (0x1U << TIM_CCMR2_OC3FE_Pos) /*!< 0x00000004 */
+#define TIM_CCMR2_OC3FE TIM_CCMR2_OC3FE_Msk /*!<Output Compare 3 Fast enable */
+#define TIM_CCMR2_OC3PE_Pos (3U)
+#define TIM_CCMR2_OC3PE_Msk (0x1U << TIM_CCMR2_OC3PE_Pos) /*!< 0x00000008 */
+#define TIM_CCMR2_OC3PE TIM_CCMR2_OC3PE_Msk /*!<Output Compare 3 Preload enable */
+
+#define TIM_CCMR2_OC3M_Pos (4U)
+#define TIM_CCMR2_OC3M_Msk (0x7U << TIM_CCMR2_OC3M_Pos) /*!< 0x00000070 */
+#define TIM_CCMR2_OC3M TIM_CCMR2_OC3M_Msk /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
+#define TIM_CCMR2_OC3M_0 (0x1U << TIM_CCMR2_OC3M_Pos) /*!< 0x00000010 */
+#define TIM_CCMR2_OC3M_1 (0x2U << TIM_CCMR2_OC3M_Pos) /*!< 0x00000020 */
+#define TIM_CCMR2_OC3M_2 (0x4U << TIM_CCMR2_OC3M_Pos) /*!< 0x00000040 */
+
+#define TIM_CCMR2_OC3CE_Pos (7U)
+#define TIM_CCMR2_OC3CE_Msk (0x1U << TIM_CCMR2_OC3CE_Pos) /*!< 0x00000080 */
+#define TIM_CCMR2_OC3CE TIM_CCMR2_OC3CE_Msk /*!<Output Compare 3 Clear Enable */
+
+#define TIM_CCMR2_CC4S_Pos (8U)
+#define TIM_CCMR2_CC4S_Msk (0x3U << TIM_CCMR2_CC4S_Pos) /*!< 0x00000300 */
+#define TIM_CCMR2_CC4S TIM_CCMR2_CC4S_Msk /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
+#define TIM_CCMR2_CC4S_0 (0x1U << TIM_CCMR2_CC4S_Pos) /*!< 0x00000100 */
+#define TIM_CCMR2_CC4S_1 (0x2U << TIM_CCMR2_CC4S_Pos) /*!< 0x00000200 */
+
+#define TIM_CCMR2_OC4FE_Pos (10U)
+#define TIM_CCMR2_OC4FE_Msk (0x1U << TIM_CCMR2_OC4FE_Pos) /*!< 0x00000400 */
+#define TIM_CCMR2_OC4FE TIM_CCMR2_OC4FE_Msk /*!<Output Compare 4 Fast enable */
+#define TIM_CCMR2_OC4PE_Pos (11U)
+#define TIM_CCMR2_OC4PE_Msk (0x1U << TIM_CCMR2_OC4PE_Pos) /*!< 0x00000800 */
+#define TIM_CCMR2_OC4PE TIM_CCMR2_OC4PE_Msk /*!<Output Compare 4 Preload enable */
+
+#define TIM_CCMR2_OC4M_Pos (12U)
+#define TIM_CCMR2_OC4M_Msk (0x7U << TIM_CCMR2_OC4M_Pos) /*!< 0x00007000 */
+#define TIM_CCMR2_OC4M TIM_CCMR2_OC4M_Msk /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
+#define TIM_CCMR2_OC4M_0 (0x1U << TIM_CCMR2_OC4M_Pos) /*!< 0x00001000 */
+#define TIM_CCMR2_OC4M_1 (0x2U << TIM_CCMR2_OC4M_Pos) /*!< 0x00002000 */
+#define TIM_CCMR2_OC4M_2 (0x4U << TIM_CCMR2_OC4M_Pos) /*!< 0x00004000 */
+
+#define TIM_CCMR2_OC4CE_Pos (15U)
+#define TIM_CCMR2_OC4CE_Msk (0x1U << TIM_CCMR2_OC4CE_Pos) /*!< 0x00008000 */
+#define TIM_CCMR2_OC4CE TIM_CCMR2_OC4CE_Msk /*!<Output Compare 4 Clear Enable */
+
+/*---------------------------------------------------------------------------*/
+
+#define TIM_CCMR2_IC3PSC_Pos (2U)
+#define TIM_CCMR2_IC3PSC_Msk (0x3U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x0000000C */
+#define TIM_CCMR2_IC3PSC TIM_CCMR2_IC3PSC_Msk /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
+#define TIM_CCMR2_IC3PSC_0 (0x1U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x00000004 */
+#define TIM_CCMR2_IC3PSC_1 (0x2U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x00000008 */
+
+#define TIM_CCMR2_IC3F_Pos (4U)
+#define TIM_CCMR2_IC3F_Msk (0xFU << TIM_CCMR2_IC3F_Pos) /*!< 0x000000F0 */
+#define TIM_CCMR2_IC3F TIM_CCMR2_IC3F_Msk /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
+#define TIM_CCMR2_IC3F_0 (0x1U << TIM_CCMR2_IC3F_Pos) /*!< 0x00000010 */
+#define TIM_CCMR2_IC3F_1 (0x2U << TIM_CCMR2_IC3F_Pos) /*!< 0x00000020 */
+#define TIM_CCMR2_IC3F_2 (0x4U << TIM_CCMR2_IC3F_Pos) /*!< 0x00000040 */
+#define TIM_CCMR2_IC3F_3 (0x8U << TIM_CCMR2_IC3F_Pos) /*!< 0x00000080 */
+
+#define TIM_CCMR2_IC4PSC_Pos (10U)
+#define TIM_CCMR2_IC4PSC_Msk (0x3U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000C00 */
+#define TIM_CCMR2_IC4PSC TIM_CCMR2_IC4PSC_Msk /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
+#define TIM_CCMR2_IC4PSC_0 (0x1U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000400 */
+#define TIM_CCMR2_IC4PSC_1 (0x2U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000800 */
+
+#define TIM_CCMR2_IC4F_Pos (12U)
+#define TIM_CCMR2_IC4F_Msk (0xFU << TIM_CCMR2_IC4F_Pos) /*!< 0x0000F000 */
+#define TIM_CCMR2_IC4F TIM_CCMR2_IC4F_Msk /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
+#define TIM_CCMR2_IC4F_0 (0x1U << TIM_CCMR2_IC4F_Pos) /*!< 0x00001000 */
+#define TIM_CCMR2_IC4F_1 (0x2U << TIM_CCMR2_IC4F_Pos) /*!< 0x00002000 */
+#define TIM_CCMR2_IC4F_2 (0x4U << TIM_CCMR2_IC4F_Pos) /*!< 0x00004000 */
+#define TIM_CCMR2_IC4F_3 (0x8U << TIM_CCMR2_IC4F_Pos) /*!< 0x00008000 */
+
+/******************* Bit definition for TIM_CCER register ******************/
+#define TIM_CCER_CC1E_Pos (0U)
+#define TIM_CCER_CC1E_Msk (0x1U << TIM_CCER_CC1E_Pos) /*!< 0x00000001 */
+#define TIM_CCER_CC1E TIM_CCER_CC1E_Msk /*!<Capture/Compare 1 output enable */
+#define TIM_CCER_CC1P_Pos (1U)
+#define TIM_CCER_CC1P_Msk (0x1U << TIM_CCER_CC1P_Pos) /*!< 0x00000002 */
+#define TIM_CCER_CC1P TIM_CCER_CC1P_Msk /*!<Capture/Compare 1 output Polarity */
+#define TIM_CCER_CC1NE_Pos (2U)
+#define TIM_CCER_CC1NE_Msk (0x1U << TIM_CCER_CC1NE_Pos) /*!< 0x00000004 */
+#define TIM_CCER_CC1NE TIM_CCER_CC1NE_Msk /*!<Capture/Compare 1 Complementary output enable */
+#define TIM_CCER_CC1NP_Pos (3U)
+#define TIM_CCER_CC1NP_Msk (0x1U << TIM_CCER_CC1NP_Pos) /*!< 0x00000008 */
+#define TIM_CCER_CC1NP TIM_CCER_CC1NP_Msk /*!<Capture/Compare 1 Complementary output Polarity */
+#define TIM_CCER_CC2E_Pos (4U)
+#define TIM_CCER_CC2E_Msk (0x1U << TIM_CCER_CC2E_Pos) /*!< 0x00000010 */
+#define TIM_CCER_CC2E TIM_CCER_CC2E_Msk /*!<Capture/Compare 2 output enable */
+#define TIM_CCER_CC2P_Pos (5U)
+#define TIM_CCER_CC2P_Msk (0x1U << TIM_CCER_CC2P_Pos) /*!< 0x00000020 */
+#define TIM_CCER_CC2P TIM_CCER_CC2P_Msk /*!<Capture/Compare 2 output Polarity */
+#define TIM_CCER_CC2NE_Pos (6U)
+#define TIM_CCER_CC2NE_Msk (0x1U << TIM_CCER_CC2NE_Pos) /*!< 0x00000040 */
+#define TIM_CCER_CC2NE TIM_CCER_CC2NE_Msk /*!<Capture/Compare 2 Complementary output enable */
+#define TIM_CCER_CC2NP_Pos (7U)
+#define TIM_CCER_CC2NP_Msk (0x1U << TIM_CCER_CC2NP_Pos) /*!< 0x00000080 */
+#define TIM_CCER_CC2NP TIM_CCER_CC2NP_Msk /*!<Capture/Compare 2 Complementary output Polarity */
+#define TIM_CCER_CC3E_Pos (8U)
+#define TIM_CCER_CC3E_Msk (0x1U << TIM_CCER_CC3E_Pos) /*!< 0x00000100 */
+#define TIM_CCER_CC3E TIM_CCER_CC3E_Msk /*!<Capture/Compare 3 output enable */
+#define TIM_CCER_CC3P_Pos (9U)
+#define TIM_CCER_CC3P_Msk (0x1U << TIM_CCER_CC3P_Pos) /*!< 0x00000200 */
+#define TIM_CCER_CC3P TIM_CCER_CC3P_Msk /*!<Capture/Compare 3 output Polarity */
+#define TIM_CCER_CC3NE_Pos (10U)
+#define TIM_CCER_CC3NE_Msk (0x1U << TIM_CCER_CC3NE_Pos) /*!< 0x00000400 */
+#define TIM_CCER_CC3NE TIM_CCER_CC3NE_Msk /*!<Capture/Compare 3 Complementary output enable */
+#define TIM_CCER_CC3NP_Pos (11U)
+#define TIM_CCER_CC3NP_Msk (0x1U << TIM_CCER_CC3NP_Pos) /*!< 0x00000800 */
+#define TIM_CCER_CC3NP TIM_CCER_CC3NP_Msk /*!<Capture/Compare 3 Complementary output Polarity */
+#define TIM_CCER_CC4E_Pos (12U)
+#define TIM_CCER_CC4E_Msk (0x1U << TIM_CCER_CC4E_Pos) /*!< 0x00001000 */
+#define TIM_CCER_CC4E TIM_CCER_CC4E_Msk /*!<Capture/Compare 4 output enable */
+#define TIM_CCER_CC4P_Pos (13U)
+#define TIM_CCER_CC4P_Msk (0x1U << TIM_CCER_CC4P_Pos) /*!< 0x00002000 */
+#define TIM_CCER_CC4P TIM_CCER_CC4P_Msk /*!<Capture/Compare 4 output Polarity */
+#define TIM_CCER_CC4NP_Pos (15U)
+#define TIM_CCER_CC4NP_Msk (0x1U << TIM_CCER_CC4NP_Pos) /*!< 0x00008000 */
+#define TIM_CCER_CC4NP TIM_CCER_CC4NP_Msk /*!<Capture/Compare 4 Complementary output Polarity */
+
+/******************* Bit definition for TIM_CNT register *******************/
+#define TIM_CNT_CNT_Pos (0U)
+#define TIM_CNT_CNT_Msk (0xFFFFFFFFU << TIM_CNT_CNT_Pos) /*!< 0xFFFFFFFF */
+#define TIM_CNT_CNT TIM_CNT_CNT_Msk /*!<Counter Value */
+
+/******************* Bit definition for TIM_PSC register *******************/
+#define TIM_PSC_PSC_Pos (0U)
+#define TIM_PSC_PSC_Msk (0xFFFFU << TIM_PSC_PSC_Pos) /*!< 0x0000FFFF */
+#define TIM_PSC_PSC TIM_PSC_PSC_Msk /*!<Prescaler Value */
+
+/******************* Bit definition for TIM_ARR register *******************/
+#define TIM_ARR_ARR_Pos (0U)
+#define TIM_ARR_ARR_Msk (0xFFFFFFFFU << TIM_ARR_ARR_Pos) /*!< 0xFFFFFFFF */
+#define TIM_ARR_ARR TIM_ARR_ARR_Msk /*!<actual auto-reload Value */
+
+/******************* Bit definition for TIM_RCR register *******************/
+#define TIM_RCR_REP_Pos (0U)
+#define TIM_RCR_REP_Msk (0xFFU << TIM_RCR_REP_Pos) /*!< 0x000000FF */
+#define TIM_RCR_REP TIM_RCR_REP_Msk /*!<Repetition Counter Value */
+
+/******************* Bit definition for TIM_CCR1 register ******************/
+#define TIM_CCR1_CCR1_Pos (0U)
+#define TIM_CCR1_CCR1_Msk (0xFFFFU << TIM_CCR1_CCR1_Pos) /*!< 0x0000FFFF */
+#define TIM_CCR1_CCR1 TIM_CCR1_CCR1_Msk /*!<Capture/Compare 1 Value */
+
+/******************* Bit definition for TIM_CCR2 register ******************/
+#define TIM_CCR2_CCR2_Pos (0U)
+#define TIM_CCR2_CCR2_Msk (0xFFFFU << TIM_CCR2_CCR2_Pos) /*!< 0x0000FFFF */
+#define TIM_CCR2_CCR2 TIM_CCR2_CCR2_Msk /*!<Capture/Compare 2 Value */
+
+/******************* Bit definition for TIM_CCR3 register ******************/
+#define TIM_CCR3_CCR3_Pos (0U)
+#define TIM_CCR3_CCR3_Msk (0xFFFFU << TIM_CCR3_CCR3_Pos) /*!< 0x0000FFFF */
+#define TIM_CCR3_CCR3 TIM_CCR3_CCR3_Msk /*!<Capture/Compare 3 Value */
+
+/******************* Bit definition for TIM_CCR4 register ******************/
+#define TIM_CCR4_CCR4_Pos (0U)
+#define TIM_CCR4_CCR4_Msk (0xFFFFU << TIM_CCR4_CCR4_Pos) /*!< 0x0000FFFF */
+#define TIM_CCR4_CCR4 TIM_CCR4_CCR4_Msk /*!<Capture/Compare 4 Value */
+
+/******************* Bit definition for TIM_BDTR register ******************/
+#define TIM_BDTR_DTG_Pos (0U)
+#define TIM_BDTR_DTG_Msk (0xFFU << TIM_BDTR_DTG_Pos) /*!< 0x000000FF */
+#define TIM_BDTR_DTG TIM_BDTR_DTG_Msk /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
+#define TIM_BDTR_DTG_0 (0x01U << TIM_BDTR_DTG_Pos) /*!< 0x00000001 */
+#define TIM_BDTR_DTG_1 (0x02U << TIM_BDTR_DTG_Pos) /*!< 0x00000002 */
+#define TIM_BDTR_DTG_2 (0x04U << TIM_BDTR_DTG_Pos) /*!< 0x00000004 */
+#define TIM_BDTR_DTG_3 (0x08U << TIM_BDTR_DTG_Pos) /*!< 0x00000008 */
+#define TIM_BDTR_DTG_4 (0x10U << TIM_BDTR_DTG_Pos) /*!< 0x00000010 */
+#define TIM_BDTR_DTG_5 (0x20U << TIM_BDTR_DTG_Pos) /*!< 0x00000020 */
+#define TIM_BDTR_DTG_6 (0x40U << TIM_BDTR_DTG_Pos) /*!< 0x00000040 */
+#define TIM_BDTR_DTG_7 (0x80U << TIM_BDTR_DTG_Pos) /*!< 0x00000080 */
+
+#define TIM_BDTR_LOCK_Pos (8U)
+#define TIM_BDTR_LOCK_Msk (0x3U << TIM_BDTR_LOCK_Pos) /*!< 0x00000300 */
+#define TIM_BDTR_LOCK TIM_BDTR_LOCK_Msk /*!<LOCK[1:0] bits (Lock Configuration) */
+#define TIM_BDTR_LOCK_0 (0x1U << TIM_BDTR_LOCK_Pos) /*!< 0x00000100 */
+#define TIM_BDTR_LOCK_1 (0x2U << TIM_BDTR_LOCK_Pos) /*!< 0x00000200 */
+
+#define TIM_BDTR_OSSI_Pos (10U)
+#define TIM_BDTR_OSSI_Msk (0x1U << TIM_BDTR_OSSI_Pos) /*!< 0x00000400 */
+#define TIM_BDTR_OSSI TIM_BDTR_OSSI_Msk /*!<Off-State Selection for Idle mode */
+#define TIM_BDTR_OSSR_Pos (11U)
+#define TIM_BDTR_OSSR_Msk (0x1U << TIM_BDTR_OSSR_Pos) /*!< 0x00000800 */
+#define TIM_BDTR_OSSR TIM_BDTR_OSSR_Msk /*!<Off-State Selection for Run mode */
+#define TIM_BDTR_BKE_Pos (12U)
+#define TIM_BDTR_BKE_Msk (0x1U << TIM_BDTR_BKE_Pos) /*!< 0x00001000 */
+#define TIM_BDTR_BKE TIM_BDTR_BKE_Msk /*!<Break enable */
+#define TIM_BDTR_BKP_Pos (13U)
+#define TIM_BDTR_BKP_Msk (0x1U << TIM_BDTR_BKP_Pos) /*!< 0x00002000 */
+#define TIM_BDTR_BKP TIM_BDTR_BKP_Msk /*!<Break Polarity */
+#define TIM_BDTR_AOE_Pos (14U)
+#define TIM_BDTR_AOE_Msk (0x1U << TIM_BDTR_AOE_Pos) /*!< 0x00004000 */
+#define TIM_BDTR_AOE TIM_BDTR_AOE_Msk /*!<Automatic Output enable */
+#define TIM_BDTR_MOE_Pos (15U)
+#define TIM_BDTR_MOE_Msk (0x1U << TIM_BDTR_MOE_Pos) /*!< 0x00008000 */
+#define TIM_BDTR_MOE TIM_BDTR_MOE_Msk /*!<Main Output enable */
+
+/******************* Bit definition for TIM_DCR register *******************/
+#define TIM_DCR_DBA_Pos (0U)
+#define TIM_DCR_DBA_Msk (0x1FU << TIM_DCR_DBA_Pos) /*!< 0x0000001F */
+#define TIM_DCR_DBA TIM_DCR_DBA_Msk /*!<DBA[4:0] bits (DMA Base Address) */
+#define TIM_DCR_DBA_0 (0x01U << TIM_DCR_DBA_Pos) /*!< 0x00000001 */
+#define TIM_DCR_DBA_1 (0x02U << TIM_DCR_DBA_Pos) /*!< 0x00000002 */
+#define TIM_DCR_DBA_2 (0x04U << TIM_DCR_DBA_Pos) /*!< 0x00000004 */
+#define TIM_DCR_DBA_3 (0x08U << TIM_DCR_DBA_Pos) /*!< 0x00000008 */
+#define TIM_DCR_DBA_4 (0x10U << TIM_DCR_DBA_Pos) /*!< 0x00000010 */
+
+#define TIM_DCR_DBL_Pos (8U)
+#define TIM_DCR_DBL_Msk (0x1FU << TIM_DCR_DBL_Pos) /*!< 0x00001F00 */
+#define TIM_DCR_DBL TIM_DCR_DBL_Msk /*!<DBL[4:0] bits (DMA Burst Length) */
+#define TIM_DCR_DBL_0 (0x01U << TIM_DCR_DBL_Pos) /*!< 0x00000100 */
+#define TIM_DCR_DBL_1 (0x02U << TIM_DCR_DBL_Pos) /*!< 0x00000200 */
+#define TIM_DCR_DBL_2 (0x04U << TIM_DCR_DBL_Pos) /*!< 0x00000400 */
+#define TIM_DCR_DBL_3 (0x08U << TIM_DCR_DBL_Pos) /*!< 0x00000800 */
+#define TIM_DCR_DBL_4 (0x10U << TIM_DCR_DBL_Pos) /*!< 0x00001000 */
+
+/******************* Bit definition for TIM_DMAR register ******************/
+#define TIM_DMAR_DMAB_Pos (0U)
+#define TIM_DMAR_DMAB_Msk (0xFFFFU << TIM_DMAR_DMAB_Pos) /*!< 0x0000FFFF */
+#define TIM_DMAR_DMAB TIM_DMAR_DMAB_Msk /*!<DMA register for burst accesses */
+
+/******************* Bit definition for TIM_OR register ********************/
+
+/******************************************************************************/
+/* */
+/* Real-Time Clock */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for RTC_CRH register ********************/
+#define RTC_CRH_SECIE_Pos (0U)
+#define RTC_CRH_SECIE_Msk (0x1U << RTC_CRH_SECIE_Pos) /*!< 0x00000001 */
+#define RTC_CRH_SECIE RTC_CRH_SECIE_Msk /*!< Second Interrupt Enable */
+#define RTC_CRH_ALRIE_Pos (1U)
+#define RTC_CRH_ALRIE_Msk (0x1U << RTC_CRH_ALRIE_Pos) /*!< 0x00000002 */
+#define RTC_CRH_ALRIE RTC_CRH_ALRIE_Msk /*!< Alarm Interrupt Enable */
+#define RTC_CRH_OWIE_Pos (2U)
+#define RTC_CRH_OWIE_Msk (0x1U << RTC_CRH_OWIE_Pos) /*!< 0x00000004 */
+#define RTC_CRH_OWIE RTC_CRH_OWIE_Msk /*!< OverfloW Interrupt Enable */
+
+/******************* Bit definition for RTC_CRL register ********************/
+#define RTC_CRL_SECF_Pos (0U)
+#define RTC_CRL_SECF_Msk (0x1U << RTC_CRL_SECF_Pos) /*!< 0x00000001 */
+#define RTC_CRL_SECF RTC_CRL_SECF_Msk /*!< Second Flag */
+#define RTC_CRL_ALRF_Pos (1U)
+#define RTC_CRL_ALRF_Msk (0x1U << RTC_CRL_ALRF_Pos) /*!< 0x00000002 */
+#define RTC_CRL_ALRF RTC_CRL_ALRF_Msk /*!< Alarm Flag */
+#define RTC_CRL_OWF_Pos (2U)
+#define RTC_CRL_OWF_Msk (0x1U << RTC_CRL_OWF_Pos) /*!< 0x00000004 */
+#define RTC_CRL_OWF RTC_CRL_OWF_Msk /*!< OverfloW Flag */
+#define RTC_CRL_RSF_Pos (3U)
+#define RTC_CRL_RSF_Msk (0x1U << RTC_CRL_RSF_Pos) /*!< 0x00000008 */
+#define RTC_CRL_RSF RTC_CRL_RSF_Msk /*!< Registers Synchronized Flag */
+#define RTC_CRL_CNF_Pos (4U)
+#define RTC_CRL_CNF_Msk (0x1U << RTC_CRL_CNF_Pos) /*!< 0x00000010 */
+#define RTC_CRL_CNF RTC_CRL_CNF_Msk /*!< Configuration Flag */
+#define RTC_CRL_RTOFF_Pos (5U)
+#define RTC_CRL_RTOFF_Msk (0x1U << RTC_CRL_RTOFF_Pos) /*!< 0x00000020 */
+#define RTC_CRL_RTOFF RTC_CRL_RTOFF_Msk /*!< RTC operation OFF */
+
+/******************* Bit definition for RTC_PRLH register *******************/
+#define RTC_PRLH_PRL_Pos (0U)
+#define RTC_PRLH_PRL_Msk (0xFU << RTC_PRLH_PRL_Pos) /*!< 0x0000000F */
+#define RTC_PRLH_PRL RTC_PRLH_PRL_Msk /*!< RTC Prescaler Reload Value High */
+
+/******************* Bit definition for RTC_PRLL register *******************/
+#define RTC_PRLL_PRL_Pos (0U)
+#define RTC_PRLL_PRL_Msk (0xFFFFU << RTC_PRLL_PRL_Pos) /*!< 0x0000FFFF */
+#define RTC_PRLL_PRL RTC_PRLL_PRL_Msk /*!< RTC Prescaler Reload Value Low */
+
+/******************* Bit definition for RTC_DIVH register *******************/
+#define RTC_DIVH_RTC_DIV_Pos (0U)
+#define RTC_DIVH_RTC_DIV_Msk (0xFU << RTC_DIVH_RTC_DIV_Pos) /*!< 0x0000000F */
+#define RTC_DIVH_RTC_DIV RTC_DIVH_RTC_DIV_Msk /*!< RTC Clock Divider High */
+
+/******************* Bit definition for RTC_DIVL register *******************/
+#define RTC_DIVL_RTC_DIV_Pos (0U)
+#define RTC_DIVL_RTC_DIV_Msk (0xFFFFU << RTC_DIVL_RTC_DIV_Pos) /*!< 0x0000FFFF */
+#define RTC_DIVL_RTC_DIV RTC_DIVL_RTC_DIV_Msk /*!< RTC Clock Divider Low */
+
+/******************* Bit definition for RTC_CNTH register *******************/
+#define RTC_CNTH_RTC_CNT_Pos (0U)
+#define RTC_CNTH_RTC_CNT_Msk (0xFFFFU << RTC_CNTH_RTC_CNT_Pos) /*!< 0x0000FFFF */
+#define RTC_CNTH_RTC_CNT RTC_CNTH_RTC_CNT_Msk /*!< RTC Counter High */
+
+/******************* Bit definition for RTC_CNTL register *******************/
+#define RTC_CNTL_RTC_CNT_Pos (0U)
+#define RTC_CNTL_RTC_CNT_Msk (0xFFFFU << RTC_CNTL_RTC_CNT_Pos) /*!< 0x0000FFFF */
+#define RTC_CNTL_RTC_CNT RTC_CNTL_RTC_CNT_Msk /*!< RTC Counter Low */
+
+/******************* Bit definition for RTC_ALRH register *******************/
+#define RTC_ALRH_RTC_ALR_Pos (0U)
+#define RTC_ALRH_RTC_ALR_Msk (0xFFFFU << RTC_ALRH_RTC_ALR_Pos) /*!< 0x0000FFFF */
+#define RTC_ALRH_RTC_ALR RTC_ALRH_RTC_ALR_Msk /*!< RTC Alarm High */
+
+/******************* Bit definition for RTC_ALRL register *******************/
+#define RTC_ALRL_RTC_ALR_Pos (0U)
+#define RTC_ALRL_RTC_ALR_Msk (0xFFFFU << RTC_ALRL_RTC_ALR_Pos) /*!< 0x0000FFFF */
+#define RTC_ALRL_RTC_ALR RTC_ALRL_RTC_ALR_Msk /*!< RTC Alarm Low */
+
+/******************************************************************************/
+/* */
+/* Independent WATCHDOG (IWDG) */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for IWDG_KR register ********************/
+#define IWDG_KR_KEY_Pos (0U)
+#define IWDG_KR_KEY_Msk (0xFFFFU << IWDG_KR_KEY_Pos) /*!< 0x0000FFFF */
+#define IWDG_KR_KEY IWDG_KR_KEY_Msk /*!< Key value (write only, read 0000h) */
+
+/******************* Bit definition for IWDG_PR register ********************/
+#define IWDG_PR_PR_Pos (0U)
+#define IWDG_PR_PR_Msk (0x7U << IWDG_PR_PR_Pos) /*!< 0x00000007 */
+#define IWDG_PR_PR IWDG_PR_PR_Msk /*!< PR[2:0] (Prescaler divider) */
+#define IWDG_PR_PR_0 (0x1U << IWDG_PR_PR_Pos) /*!< 0x00000001 */
+#define IWDG_PR_PR_1 (0x2U << IWDG_PR_PR_Pos) /*!< 0x00000002 */
+#define IWDG_PR_PR_2 (0x4U << IWDG_PR_PR_Pos) /*!< 0x00000004 */
+
+/******************* Bit definition for IWDG_RLR register *******************/
+#define IWDG_RLR_RL_Pos (0U)
+#define IWDG_RLR_RL_Msk (0xFFFU << IWDG_RLR_RL_Pos) /*!< 0x00000FFF */
+#define IWDG_RLR_RL IWDG_RLR_RL_Msk /*!< Watchdog counter reload value */
+
+/******************* Bit definition for IWDG_SR register ********************/
+#define IWDG_SR_PVU_Pos (0U)
+#define IWDG_SR_PVU_Msk (0x1U << IWDG_SR_PVU_Pos) /*!< 0x00000001 */
+#define IWDG_SR_PVU IWDG_SR_PVU_Msk /*!< Watchdog prescaler value update */
+#define IWDG_SR_RVU_Pos (1U)
+#define IWDG_SR_RVU_Msk (0x1U << IWDG_SR_RVU_Pos) /*!< 0x00000002 */
+#define IWDG_SR_RVU IWDG_SR_RVU_Msk /*!< Watchdog counter reload value update */
+
+/******************************************************************************/
+/* */
+/* Window WATCHDOG (WWDG) */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for WWDG_CR register ********************/
+#define WWDG_CR_T_Pos (0U)
+#define WWDG_CR_T_Msk (0x7FU << WWDG_CR_T_Pos) /*!< 0x0000007F */
+#define WWDG_CR_T WWDG_CR_T_Msk /*!< T[6:0] bits (7-Bit counter (MSB to LSB)) */
+#define WWDG_CR_T_0 (0x01U << WWDG_CR_T_Pos) /*!< 0x00000001 */
+#define WWDG_CR_T_1 (0x02U << WWDG_CR_T_Pos) /*!< 0x00000002 */
+#define WWDG_CR_T_2 (0x04U << WWDG_CR_T_Pos) /*!< 0x00000004 */
+#define WWDG_CR_T_3 (0x08U << WWDG_CR_T_Pos) /*!< 0x00000008 */
+#define WWDG_CR_T_4 (0x10U << WWDG_CR_T_Pos) /*!< 0x00000010 */
+#define WWDG_CR_T_5 (0x20U << WWDG_CR_T_Pos) /*!< 0x00000020 */
+#define WWDG_CR_T_6 (0x40U << WWDG_CR_T_Pos) /*!< 0x00000040 */
+
+/* Legacy defines */
+#define WWDG_CR_T0 WWDG_CR_T_0
+#define WWDG_CR_T1 WWDG_CR_T_1
+#define WWDG_CR_T2 WWDG_CR_T_2
+#define WWDG_CR_T3 WWDG_CR_T_3
+#define WWDG_CR_T4 WWDG_CR_T_4
+#define WWDG_CR_T5 WWDG_CR_T_5
+#define WWDG_CR_T6 WWDG_CR_T_6
+
+#define WWDG_CR_WDGA_Pos (7U)
+#define WWDG_CR_WDGA_Msk (0x1U << WWDG_CR_WDGA_Pos) /*!< 0x00000080 */
+#define WWDG_CR_WDGA WWDG_CR_WDGA_Msk /*!< Activation bit */
+
+/******************* Bit definition for WWDG_CFR register *******************/
+#define WWDG_CFR_W_Pos (0U)
+#define WWDG_CFR_W_Msk (0x7FU << WWDG_CFR_W_Pos) /*!< 0x0000007F */
+#define WWDG_CFR_W WWDG_CFR_W_Msk /*!< W[6:0] bits (7-bit window value) */
+#define WWDG_CFR_W_0 (0x01U << WWDG_CFR_W_Pos) /*!< 0x00000001 */
+#define WWDG_CFR_W_1 (0x02U << WWDG_CFR_W_Pos) /*!< 0x00000002 */
+#define WWDG_CFR_W_2 (0x04U << WWDG_CFR_W_Pos) /*!< 0x00000004 */
+#define WWDG_CFR_W_3 (0x08U << WWDG_CFR_W_Pos) /*!< 0x00000008 */
+#define WWDG_CFR_W_4 (0x10U << WWDG_CFR_W_Pos) /*!< 0x00000010 */
+#define WWDG_CFR_W_5 (0x20U << WWDG_CFR_W_Pos) /*!< 0x00000020 */
+#define WWDG_CFR_W_6 (0x40U << WWDG_CFR_W_Pos) /*!< 0x00000040 */
+
+/* Legacy defines */
+#define WWDG_CFR_W0 WWDG_CFR_W_0
+#define WWDG_CFR_W1 WWDG_CFR_W_1
+#define WWDG_CFR_W2 WWDG_CFR_W_2
+#define WWDG_CFR_W3 WWDG_CFR_W_3
+#define WWDG_CFR_W4 WWDG_CFR_W_4
+#define WWDG_CFR_W5 WWDG_CFR_W_5
+#define WWDG_CFR_W6 WWDG_CFR_W_6
+
+#define WWDG_CFR_WDGTB_Pos (7U)
+#define WWDG_CFR_WDGTB_Msk (0x3U << WWDG_CFR_WDGTB_Pos) /*!< 0x00000180 */
+#define WWDG_CFR_WDGTB WWDG_CFR_WDGTB_Msk /*!< WDGTB[1:0] bits (Timer Base) */
+#define WWDG_CFR_WDGTB_0 (0x1U << WWDG_CFR_WDGTB_Pos) /*!< 0x00000080 */
+#define WWDG_CFR_WDGTB_1 (0x2U << WWDG_CFR_WDGTB_Pos) /*!< 0x00000100 */
+
+/* Legacy defines */
+#define WWDG_CFR_WDGTB0 WWDG_CFR_WDGTB_0
+#define WWDG_CFR_WDGTB1 WWDG_CFR_WDGTB_1
+
+#define WWDG_CFR_EWI_Pos (9U)
+#define WWDG_CFR_EWI_Msk (0x1U << WWDG_CFR_EWI_Pos) /*!< 0x00000200 */
+#define WWDG_CFR_EWI WWDG_CFR_EWI_Msk /*!< Early Wakeup Interrupt */
+
+/******************* Bit definition for WWDG_SR register ********************/
+#define WWDG_SR_EWIF_Pos (0U)
+#define WWDG_SR_EWIF_Msk (0x1U << WWDG_SR_EWIF_Pos) /*!< 0x00000001 */
+#define WWDG_SR_EWIF WWDG_SR_EWIF_Msk /*!< Early Wakeup Interrupt Flag */
+
+/******************************************************************************/
+/* */
+/* Flexible Static Memory Controller */
+/* */
+/******************************************************************************/
+
+/****************** Bit definition for FSMC_BCRx (x=1..4) register **********/
+#define FSMC_BCRx_MBKEN_Pos (0U)
+#define FSMC_BCRx_MBKEN_Msk (0x1U << FSMC_BCRx_MBKEN_Pos) /*!< 0x00000001 */
+#define FSMC_BCRx_MBKEN FSMC_BCRx_MBKEN_Msk /*!< Memory bank enable bit */
+#define FSMC_BCRx_MUXEN_Pos (1U)
+#define FSMC_BCRx_MUXEN_Msk (0x1U << FSMC_BCRx_MUXEN_Pos) /*!< 0x00000002 */
+#define FSMC_BCRx_MUXEN FSMC_BCRx_MUXEN_Msk /*!< Address/data multiplexing enable bit */
+
+#define FSMC_BCRx_MTYP_Pos (2U)
+#define FSMC_BCRx_MTYP_Msk (0x3U << FSMC_BCRx_MTYP_Pos) /*!< 0x0000000C */
+#define FSMC_BCRx_MTYP FSMC_BCRx_MTYP_Msk /*!< MTYP[1:0] bits (Memory type) */
+#define FSMC_BCRx_MTYP_0 (0x1U << FSMC_BCRx_MTYP_Pos) /*!< 0x00000004 */
+#define FSMC_BCRx_MTYP_1 (0x2U << FSMC_BCRx_MTYP_Pos) /*!< 0x00000008 */
+
+#define FSMC_BCRx_MWID_Pos (4U)
+#define FSMC_BCRx_MWID_Msk (0x3U << FSMC_BCRx_MWID_Pos) /*!< 0x00000030 */
+#define FSMC_BCRx_MWID FSMC_BCRx_MWID_Msk /*!< MWID[1:0] bits (Memory data bus width) */
+#define FSMC_BCRx_MWID_0 (0x1U << FSMC_BCRx_MWID_Pos) /*!< 0x00000010 */
+#define FSMC_BCRx_MWID_1 (0x2U << FSMC_BCRx_MWID_Pos) /*!< 0x00000020 */
+
+#define FSMC_BCRx_FACCEN_Pos (6U)
+#define FSMC_BCRx_FACCEN_Msk (0x1U << FSMC_BCRx_FACCEN_Pos) /*!< 0x00000040 */
+#define FSMC_BCRx_FACCEN FSMC_BCRx_FACCEN_Msk /*!< Flash access enable */
+#define FSMC_BCRx_BURSTEN_Pos (8U)
+#define FSMC_BCRx_BURSTEN_Msk (0x1U << FSMC_BCRx_BURSTEN_Pos) /*!< 0x00000100 */
+#define FSMC_BCRx_BURSTEN FSMC_BCRx_BURSTEN_Msk /*!< Burst enable bit */
+#define FSMC_BCRx_WAITPOL_Pos (9U)
+#define FSMC_BCRx_WAITPOL_Msk (0x1U << FSMC_BCRx_WAITPOL_Pos) /*!< 0x00000200 */
+#define FSMC_BCRx_WAITPOL FSMC_BCRx_WAITPOL_Msk /*!< Wait signal polarity bit */
+#define FSMC_BCRx_WRAPMOD_Pos (10U)
+#define FSMC_BCRx_WRAPMOD_Msk (0x1U << FSMC_BCRx_WRAPMOD_Pos) /*!< 0x00000400 */
+#define FSMC_BCRx_WRAPMOD FSMC_BCRx_WRAPMOD_Msk /*!< Wrapped burst mode support */
+#define FSMC_BCRx_WAITCFG_Pos (11U)
+#define FSMC_BCRx_WAITCFG_Msk (0x1U << FSMC_BCRx_WAITCFG_Pos) /*!< 0x00000800 */
+#define FSMC_BCRx_WAITCFG FSMC_BCRx_WAITCFG_Msk /*!< Wait timing configuration */
+#define FSMC_BCRx_WREN_Pos (12U)
+#define FSMC_BCRx_WREN_Msk (0x1U << FSMC_BCRx_WREN_Pos) /*!< 0x00001000 */
+#define FSMC_BCRx_WREN FSMC_BCRx_WREN_Msk /*!< Write enable bit */
+#define FSMC_BCRx_WAITEN_Pos (13U)
+#define FSMC_BCRx_WAITEN_Msk (0x1U << FSMC_BCRx_WAITEN_Pos) /*!< 0x00002000 */
+#define FSMC_BCRx_WAITEN FSMC_BCRx_WAITEN_Msk /*!< Wait enable bit */
+#define FSMC_BCRx_EXTMOD_Pos (14U)
+#define FSMC_BCRx_EXTMOD_Msk (0x1U << FSMC_BCRx_EXTMOD_Pos) /*!< 0x00004000 */
+#define FSMC_BCRx_EXTMOD FSMC_BCRx_EXTMOD_Msk /*!< Extended mode enable */
+#define FSMC_BCRx_ASYNCWAIT_Pos (15U)
+#define FSMC_BCRx_ASYNCWAIT_Msk (0x1U << FSMC_BCRx_ASYNCWAIT_Pos) /*!< 0x00008000 */
+#define FSMC_BCRx_ASYNCWAIT FSMC_BCRx_ASYNCWAIT_Msk /*!< Asynchronous wait */
+#define FSMC_BCRx_CBURSTRW_Pos (19U)
+#define FSMC_BCRx_CBURSTRW_Msk (0x1U << FSMC_BCRx_CBURSTRW_Pos) /*!< 0x00080000 */
+#define FSMC_BCRx_CBURSTRW FSMC_BCRx_CBURSTRW_Msk /*!< Write burst enable */
+
+/****************** Bit definition for FSMC_BTRx (x=1..4) register ******/
+#define FSMC_BTRx_ADDSET_Pos (0U)
+#define FSMC_BTRx_ADDSET_Msk (0xFU << FSMC_BTRx_ADDSET_Pos) /*!< 0x0000000F */
+#define FSMC_BTRx_ADDSET FSMC_BTRx_ADDSET_Msk /*!< ADDSET[3:0] bits (Address setup phase duration) */
+#define FSMC_BTRx_ADDSET_0 (0x1U << FSMC_BTRx_ADDSET_Pos) /*!< 0x00000001 */
+#define FSMC_BTRx_ADDSET_1 (0x2U << FSMC_BTRx_ADDSET_Pos) /*!< 0x00000002 */
+#define FSMC_BTRx_ADDSET_2 (0x4U << FSMC_BTRx_ADDSET_Pos) /*!< 0x00000004 */
+#define FSMC_BTRx_ADDSET_3 (0x8U << FSMC_BTRx_ADDSET_Pos) /*!< 0x00000008 */
+
+#define FSMC_BTRx_ADDHLD_Pos (4U)
+#define FSMC_BTRx_ADDHLD_Msk (0xFU << FSMC_BTRx_ADDHLD_Pos) /*!< 0x000000F0 */
+#define FSMC_BTRx_ADDHLD FSMC_BTRx_ADDHLD_Msk /*!< ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FSMC_BTRx_ADDHLD_0 (0x1U << FSMC_BTRx_ADDHLD_Pos) /*!< 0x00000010 */
+#define FSMC_BTRx_ADDHLD_1 (0x2U << FSMC_BTRx_ADDHLD_Pos) /*!< 0x00000020 */
+#define FSMC_BTRx_ADDHLD_2 (0x4U << FSMC_BTRx_ADDHLD_Pos) /*!< 0x00000040 */
+#define FSMC_BTRx_ADDHLD_3 (0x8U << FSMC_BTRx_ADDHLD_Pos) /*!< 0x00000080 */
+
+#define FSMC_BTRx_DATAST_Pos (8U)
+#define FSMC_BTRx_DATAST_Msk (0xFFU << FSMC_BTRx_DATAST_Pos) /*!< 0x0000FF00 */
+#define FSMC_BTRx_DATAST FSMC_BTRx_DATAST_Msk /*!< DATAST [3:0] bits (Data-phase duration) */
+#define FSMC_BTRx_DATAST_0 (0x01U << FSMC_BTRx_DATAST_Pos) /*!< 0x00000100 */
+#define FSMC_BTRx_DATAST_1 (0x02U << FSMC_BTRx_DATAST_Pos) /*!< 0x00000200 */
+#define FSMC_BTRx_DATAST_2 (0x04U << FSMC_BTRx_DATAST_Pos) /*!< 0x00000400 */
+#define FSMC_BTRx_DATAST_3 (0x08U << FSMC_BTRx_DATAST_Pos) /*!< 0x00000800 */
+#define FSMC_BTRx_DATAST_4 (0x10U << FSMC_BTRx_DATAST_Pos) /*!< 0x00001000 */
+#define FSMC_BTRx_DATAST_5 (0x20U << FSMC_BTRx_DATAST_Pos) /*!< 0x00002000 */
+#define FSMC_BTRx_DATAST_6 (0x40U << FSMC_BTRx_DATAST_Pos) /*!< 0x00004000 */
+#define FSMC_BTRx_DATAST_7 (0x80U << FSMC_BTRx_DATAST_Pos) /*!< 0x00008000 */
+
+#define FSMC_BTRx_BUSTURN_Pos (16U)
+#define FSMC_BTRx_BUSTURN_Msk (0xFU << FSMC_BTRx_BUSTURN_Pos) /*!< 0x000F0000 */
+#define FSMC_BTRx_BUSTURN FSMC_BTRx_BUSTURN_Msk /*!< BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define FSMC_BTRx_BUSTURN_0 (0x1U << FSMC_BTRx_BUSTURN_Pos) /*!< 0x00010000 */
+#define FSMC_BTRx_BUSTURN_1 (0x2U << FSMC_BTRx_BUSTURN_Pos) /*!< 0x00020000 */
+#define FSMC_BTRx_BUSTURN_2 (0x4U << FSMC_BTRx_BUSTURN_Pos) /*!< 0x00040000 */
+#define FSMC_BTRx_BUSTURN_3 (0x8U << FSMC_BTRx_BUSTURN_Pos) /*!< 0x00080000 */
+
+#define FSMC_BTRx_CLKDIV_Pos (20U)
+#define FSMC_BTRx_CLKDIV_Msk (0xFU << FSMC_BTRx_CLKDIV_Pos) /*!< 0x00F00000 */
+#define FSMC_BTRx_CLKDIV FSMC_BTRx_CLKDIV_Msk /*!< CLKDIV[3:0] bits (Clock divide ratio) */
+#define FSMC_BTRx_CLKDIV_0 (0x1U << FSMC_BTRx_CLKDIV_Pos) /*!< 0x00100000 */
+#define FSMC_BTRx_CLKDIV_1 (0x2U << FSMC_BTRx_CLKDIV_Pos) /*!< 0x00200000 */
+#define FSMC_BTRx_CLKDIV_2 (0x4U << FSMC_BTRx_CLKDIV_Pos) /*!< 0x00400000 */
+#define FSMC_BTRx_CLKDIV_3 (0x8U << FSMC_BTRx_CLKDIV_Pos) /*!< 0x00800000 */
+
+#define FSMC_BTRx_DATLAT_Pos (24U)
+#define FSMC_BTRx_DATLAT_Msk (0xFU << FSMC_BTRx_DATLAT_Pos) /*!< 0x0F000000 */
+#define FSMC_BTRx_DATLAT FSMC_BTRx_DATLAT_Msk /*!< DATLA[3:0] bits (Data latency) */
+#define FSMC_BTRx_DATLAT_0 (0x1U << FSMC_BTRx_DATLAT_Pos) /*!< 0x01000000 */
+#define FSMC_BTRx_DATLAT_1 (0x2U << FSMC_BTRx_DATLAT_Pos) /*!< 0x02000000 */
+#define FSMC_BTRx_DATLAT_2 (0x4U << FSMC_BTRx_DATLAT_Pos) /*!< 0x04000000 */
+#define FSMC_BTRx_DATLAT_3 (0x8U << FSMC_BTRx_DATLAT_Pos) /*!< 0x08000000 */
+
+#define FSMC_BTRx_ACCMOD_Pos (28U)
+#define FSMC_BTRx_ACCMOD_Msk (0x3U << FSMC_BTRx_ACCMOD_Pos) /*!< 0x30000000 */
+#define FSMC_BTRx_ACCMOD FSMC_BTRx_ACCMOD_Msk /*!< ACCMOD[1:0] bits (Access mode) */
+#define FSMC_BTRx_ACCMOD_0 (0x1U << FSMC_BTRx_ACCMOD_Pos) /*!< 0x10000000 */
+#define FSMC_BTRx_ACCMOD_1 (0x2U << FSMC_BTRx_ACCMOD_Pos) /*!< 0x20000000 */
+
+/****************** Bit definition for FSMC_BWTRx (x=1..4) register ******/
+#define FSMC_BWTRx_ADDSET_Pos (0U)
+#define FSMC_BWTRx_ADDSET_Msk (0xFU << FSMC_BWTRx_ADDSET_Pos) /*!< 0x0000000F */
+#define FSMC_BWTRx_ADDSET FSMC_BWTRx_ADDSET_Msk /*!< ADDSET[3:0] bits (Address setup phase duration) */
+#define FSMC_BWTRx_ADDSET_0 (0x1U << FSMC_BWTRx_ADDSET_Pos) /*!< 0x00000001 */
+#define FSMC_BWTRx_ADDSET_1 (0x2U << FSMC_BWTRx_ADDSET_Pos) /*!< 0x00000002 */
+#define FSMC_BWTRx_ADDSET_2 (0x4U << FSMC_BWTRx_ADDSET_Pos) /*!< 0x00000004 */
+#define FSMC_BWTRx_ADDSET_3 (0x8U << FSMC_BWTRx_ADDSET_Pos) /*!< 0x00000008 */
+
+#define FSMC_BWTRx_ADDHLD_Pos (4U)
+#define FSMC_BWTRx_ADDHLD_Msk (0xFU << FSMC_BWTRx_ADDHLD_Pos) /*!< 0x000000F0 */
+#define FSMC_BWTRx_ADDHLD FSMC_BWTRx_ADDHLD_Msk /*!< ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FSMC_BWTRx_ADDHLD_0 (0x1U << FSMC_BWTRx_ADDHLD_Pos) /*!< 0x00000010 */
+#define FSMC_BWTRx_ADDHLD_1 (0x2U << FSMC_BWTRx_ADDHLD_Pos) /*!< 0x00000020 */
+#define FSMC_BWTRx_ADDHLD_2 (0x4U << FSMC_BWTRx_ADDHLD_Pos) /*!< 0x00000040 */
+#define FSMC_BWTRx_ADDHLD_3 (0x8U << FSMC_BWTRx_ADDHLD_Pos) /*!< 0x00000080 */
+
+#define FSMC_BWTRx_DATAST_Pos (8U)
+#define FSMC_BWTRx_DATAST_Msk (0xFFU << FSMC_BWTRx_DATAST_Pos) /*!< 0x0000FF00 */
+#define FSMC_BWTRx_DATAST FSMC_BWTRx_DATAST_Msk /*!< DATAST [3:0] bits (Data-phase duration) */
+#define FSMC_BWTRx_DATAST_0 (0x01U << FSMC_BWTRx_DATAST_Pos) /*!< 0x00000100 */
+#define FSMC_BWTRx_DATAST_1 (0x02U << FSMC_BWTRx_DATAST_Pos) /*!< 0x00000200 */
+#define FSMC_BWTRx_DATAST_2 (0x04U << FSMC_BWTRx_DATAST_Pos) /*!< 0x00000400 */
+#define FSMC_BWTRx_DATAST_3 (0x08U << FSMC_BWTRx_DATAST_Pos) /*!< 0x00000800 */
+#define FSMC_BWTRx_DATAST_4 (0x10U << FSMC_BWTRx_DATAST_Pos) /*!< 0x00001000 */
+#define FSMC_BWTRx_DATAST_5 (0x20U << FSMC_BWTRx_DATAST_Pos) /*!< 0x00002000 */
+#define FSMC_BWTRx_DATAST_6 (0x40U << FSMC_BWTRx_DATAST_Pos) /*!< 0x00004000 */
+#define FSMC_BWTRx_DATAST_7 (0x80U << FSMC_BWTRx_DATAST_Pos) /*!< 0x00008000 */
+
+#define FSMC_BWTRx_BUSTURN_Pos (16U)
+#define FSMC_BWTRx_BUSTURN_Msk (0xFU << FSMC_BWTRx_BUSTURN_Pos) /*!< 0x000F0000 */
+#define FSMC_BWTRx_BUSTURN FSMC_BWTRx_BUSTURN_Msk /*!< BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define FSMC_BWTRx_BUSTURN_0 (0x1U << FSMC_BWTRx_BUSTURN_Pos) /*!< 0x00010000 */
+#define FSMC_BWTRx_BUSTURN_1 (0x2U << FSMC_BWTRx_BUSTURN_Pos) /*!< 0x00020000 */
+#define FSMC_BWTRx_BUSTURN_2 (0x4U << FSMC_BWTRx_BUSTURN_Pos) /*!< 0x00040000 */
+#define FSMC_BWTRx_BUSTURN_3 (0x8U << FSMC_BWTRx_BUSTURN_Pos) /*!< 0x00080000 */
+
+#define FSMC_BWTRx_ACCMOD_Pos (28U)
+#define FSMC_BWTRx_ACCMOD_Msk (0x3U << FSMC_BWTRx_ACCMOD_Pos) /*!< 0x30000000 */
+#define FSMC_BWTRx_ACCMOD FSMC_BWTRx_ACCMOD_Msk /*!< ACCMOD[1:0] bits (Access mode) */
+#define FSMC_BWTRx_ACCMOD_0 (0x1U << FSMC_BWTRx_ACCMOD_Pos) /*!< 0x10000000 */
+#define FSMC_BWTRx_ACCMOD_1 (0x2U << FSMC_BWTRx_ACCMOD_Pos) /*!< 0x20000000 */
+
+/****************** Bit definition for FSMC_PCRx (x = 2 to 4) register *******************/
+#define FSMC_PCRx_PWAITEN_Pos (1U)
+#define FSMC_PCRx_PWAITEN_Msk (0x1U << FSMC_PCRx_PWAITEN_Pos) /*!< 0x00000002 */
+#define FSMC_PCRx_PWAITEN FSMC_PCRx_PWAITEN_Msk /*!< Wait feature enable bit */
+#define FSMC_PCRx_PBKEN_Pos (2U)
+#define FSMC_PCRx_PBKEN_Msk (0x1U << FSMC_PCRx_PBKEN_Pos) /*!< 0x00000004 */
+#define FSMC_PCRx_PBKEN FSMC_PCRx_PBKEN_Msk /*!< PC Card/NAND Flash memory bank enable bit */
+#define FSMC_PCRx_PTYP_Pos (3U)
+#define FSMC_PCRx_PTYP_Msk (0x1U << FSMC_PCRx_PTYP_Pos) /*!< 0x00000008 */
+#define FSMC_PCRx_PTYP FSMC_PCRx_PTYP_Msk /*!< Memory type */
+
+#define FSMC_PCRx_PWID_Pos (4U)
+#define FSMC_PCRx_PWID_Msk (0x3U << FSMC_PCRx_PWID_Pos) /*!< 0x00000030 */
+#define FSMC_PCRx_PWID FSMC_PCRx_PWID_Msk /*!< PWID[1:0] bits (NAND Flash databus width) */
+#define FSMC_PCRx_PWID_0 (0x1U << FSMC_PCRx_PWID_Pos) /*!< 0x00000010 */
+#define FSMC_PCRx_PWID_1 (0x2U << FSMC_PCRx_PWID_Pos) /*!< 0x00000020 */
+
+#define FSMC_PCRx_ECCEN_Pos (6U)
+#define FSMC_PCRx_ECCEN_Msk (0x1U << FSMC_PCRx_ECCEN_Pos) /*!< 0x00000040 */
+#define FSMC_PCRx_ECCEN FSMC_PCRx_ECCEN_Msk /*!< ECC computation logic enable bit */
+
+#define FSMC_PCRx_TCLR_Pos (9U)
+#define FSMC_PCRx_TCLR_Msk (0xFU << FSMC_PCRx_TCLR_Pos) /*!< 0x00001E00 */
+#define FSMC_PCRx_TCLR FSMC_PCRx_TCLR_Msk /*!< TCLR[3:0] bits (CLE to RE delay) */
+#define FSMC_PCRx_TCLR_0 (0x1U << FSMC_PCRx_TCLR_Pos) /*!< 0x00000200 */
+#define FSMC_PCRx_TCLR_1 (0x2U << FSMC_PCRx_TCLR_Pos) /*!< 0x00000400 */
+#define FSMC_PCRx_TCLR_2 (0x4U << FSMC_PCRx_TCLR_Pos) /*!< 0x00000800 */
+#define FSMC_PCRx_TCLR_3 (0x8U << FSMC_PCRx_TCLR_Pos) /*!< 0x00001000 */
+
+#define FSMC_PCRx_TAR_Pos (13U)
+#define FSMC_PCRx_TAR_Msk (0xFU << FSMC_PCRx_TAR_Pos) /*!< 0x0001E000 */
+#define FSMC_PCRx_TAR FSMC_PCRx_TAR_Msk /*!< TAR[3:0] bits (ALE to RE delay) */
+#define FSMC_PCRx_TAR_0 (0x1U << FSMC_PCRx_TAR_Pos) /*!< 0x00002000 */
+#define FSMC_PCRx_TAR_1 (0x2U << FSMC_PCRx_TAR_Pos) /*!< 0x00004000 */
+#define FSMC_PCRx_TAR_2 (0x4U << FSMC_PCRx_TAR_Pos) /*!< 0x00008000 */
+#define FSMC_PCRx_TAR_3 (0x8U << FSMC_PCRx_TAR_Pos) /*!< 0x00010000 */
+
+#define FSMC_PCRx_ECCPS_Pos (17U)
+#define FSMC_PCRx_ECCPS_Msk (0x7U << FSMC_PCRx_ECCPS_Pos) /*!< 0x000E0000 */
+#define FSMC_PCRx_ECCPS FSMC_PCRx_ECCPS_Msk /*!< ECCPS[1:0] bits (ECC page size) */
+#define FSMC_PCRx_ECCPS_0 (0x1U << FSMC_PCRx_ECCPS_Pos) /*!< 0x00020000 */
+#define FSMC_PCRx_ECCPS_1 (0x2U << FSMC_PCRx_ECCPS_Pos) /*!< 0x00040000 */
+#define FSMC_PCRx_ECCPS_2 (0x4U << FSMC_PCRx_ECCPS_Pos) /*!< 0x00080000 */
+
+/******************* Bit definition for FSMC_SRx (x = 2 to 4) register *******************/
+#define FSMC_SRx_IRS_Pos (0U)
+#define FSMC_SRx_IRS_Msk (0x1U << FSMC_SRx_IRS_Pos) /*!< 0x00000001 */
+#define FSMC_SRx_IRS FSMC_SRx_IRS_Msk /*!< Interrupt Rising Edge status */
+#define FSMC_SRx_ILS_Pos (1U)
+#define FSMC_SRx_ILS_Msk (0x1U << FSMC_SRx_ILS_Pos) /*!< 0x00000002 */
+#define FSMC_SRx_ILS FSMC_SRx_ILS_Msk /*!< Interrupt Level status */
+#define FSMC_SRx_IFS_Pos (2U)
+#define FSMC_SRx_IFS_Msk (0x1U << FSMC_SRx_IFS_Pos) /*!< 0x00000004 */
+#define FSMC_SRx_IFS FSMC_SRx_IFS_Msk /*!< Interrupt Falling Edge status */
+#define FSMC_SRx_IREN_Pos (3U)
+#define FSMC_SRx_IREN_Msk (0x1U << FSMC_SRx_IREN_Pos) /*!< 0x00000008 */
+#define FSMC_SRx_IREN FSMC_SRx_IREN_Msk /*!< Interrupt Rising Edge detection Enable bit */
+#define FSMC_SRx_ILEN_Pos (4U)
+#define FSMC_SRx_ILEN_Msk (0x1U << FSMC_SRx_ILEN_Pos) /*!< 0x00000010 */
+#define FSMC_SRx_ILEN FSMC_SRx_ILEN_Msk /*!< Interrupt Level detection Enable bit */
+#define FSMC_SRx_IFEN_Pos (5U)
+#define FSMC_SRx_IFEN_Msk (0x1U << FSMC_SRx_IFEN_Pos) /*!< 0x00000020 */
+#define FSMC_SRx_IFEN FSMC_SRx_IFEN_Msk /*!< Interrupt Falling Edge detection Enable bit */
+#define FSMC_SRx_FEMPT_Pos (6U)
+#define FSMC_SRx_FEMPT_Msk (0x1U << FSMC_SRx_FEMPT_Pos) /*!< 0x00000040 */
+#define FSMC_SRx_FEMPT FSMC_SRx_FEMPT_Msk /*!< FIFO empty */
+
+/****************** Bit definition for FSMC_PMEMx (x = 2 to 4) register ******************/
+#define FSMC_PMEMx_MEMSETx_Pos (0U)
+#define FSMC_PMEMx_MEMSETx_Msk (0xFFU << FSMC_PMEMx_MEMSETx_Pos) /*!< 0x000000FF */
+#define FSMC_PMEMx_MEMSETx FSMC_PMEMx_MEMSETx_Msk /*!< MEMSETx[7:0] bits (Common memory x setup time) */
+#define FSMC_PMEMx_MEMSETx_0 (0x01U << FSMC_PMEMx_MEMSETx_Pos) /*!< 0x00000001 */
+#define FSMC_PMEMx_MEMSETx_1 (0x02U << FSMC_PMEMx_MEMSETx_Pos) /*!< 0x00000002 */
+#define FSMC_PMEMx_MEMSETx_2 (0x04U << FSMC_PMEMx_MEMSETx_Pos) /*!< 0x00000004 */
+#define FSMC_PMEMx_MEMSETx_3 (0x08U << FSMC_PMEMx_MEMSETx_Pos) /*!< 0x00000008 */
+#define FSMC_PMEMx_MEMSETx_4 (0x10U << FSMC_PMEMx_MEMSETx_Pos) /*!< 0x00000010 */
+#define FSMC_PMEMx_MEMSETx_5 (0x20U << FSMC_PMEMx_MEMSETx_Pos) /*!< 0x00000020 */
+#define FSMC_PMEMx_MEMSETx_6 (0x40U << FSMC_PMEMx_MEMSETx_Pos) /*!< 0x00000040 */
+#define FSMC_PMEMx_MEMSETx_7 (0x80U << FSMC_PMEMx_MEMSETx_Pos) /*!< 0x00000080 */
+
+#define FSMC_PMEMx_MEMWAITx_Pos (8U)
+#define FSMC_PMEMx_MEMWAITx_Msk (0xFFU << FSMC_PMEMx_MEMWAITx_Pos) /*!< 0x0000FF00 */
+#define FSMC_PMEMx_MEMWAITx FSMC_PMEMx_MEMWAITx_Msk /*!< MEMWAITx[7:0] bits (Common memory x wait time) */
+#define FSMC_PMEMx_MEMWAIT2_0 ((uint32_t)0x00000100) /*!< Bit 0 */
+#define FSMC_PMEMx_MEMWAITx_1 ((uint32_t)0x00000200) /*!< Bit 1 */
+#define FSMC_PMEMx_MEMWAITx_2 ((uint32_t)0x00000400) /*!< Bit 2 */
+#define FSMC_PMEMx_MEMWAITx_3 ((uint32_t)0x00000800) /*!< Bit 3 */
+#define FSMC_PMEMx_MEMWAITx_4 ((uint32_t)0x00001000) /*!< Bit 4 */
+#define FSMC_PMEMx_MEMWAITx_5 ((uint32_t)0x00002000) /*!< Bit 5 */
+#define FSMC_PMEMx_MEMWAITx_6 ((uint32_t)0x00004000) /*!< Bit 6 */
+#define FSMC_PMEMx_MEMWAITx_7 ((uint32_t)0x00008000) /*!< Bit 7 */
+
+#define FSMC_PMEMx_MEMHOLDx_Pos (16U)
+#define FSMC_PMEMx_MEMHOLDx_Msk (0xFFU << FSMC_PMEMx_MEMHOLDx_Pos) /*!< 0x00FF0000 */
+#define FSMC_PMEMx_MEMHOLDx FSMC_PMEMx_MEMHOLDx_Msk /*!< MEMHOLDx[7:0] bits (Common memory x hold time) */
+#define FSMC_PMEMx_MEMHOLDx_0 (0x01U << FSMC_PMEMx_MEMHOLDx_Pos) /*!< 0x00010000 */
+#define FSMC_PMEMx_MEMHOLDx_1 (0x02U << FSMC_PMEMx_MEMHOLDx_Pos) /*!< 0x00020000 */
+#define FSMC_PMEMx_MEMHOLDx_2 (0x04U << FSMC_PMEMx_MEMHOLDx_Pos) /*!< 0x00040000 */
+#define FSMC_PMEMx_MEMHOLDx_3 (0x08U << FSMC_PMEMx_MEMHOLDx_Pos) /*!< 0x00080000 */
+#define FSMC_PMEMx_MEMHOLDx_4 (0x10U << FSMC_PMEMx_MEMHOLDx_Pos) /*!< 0x00100000 */
+#define FSMC_PMEMx_MEMHOLDx_5 (0x20U << FSMC_PMEMx_MEMHOLDx_Pos) /*!< 0x00200000 */
+#define FSMC_PMEMx_MEMHOLDx_6 (0x40U << FSMC_PMEMx_MEMHOLDx_Pos) /*!< 0x00400000 */
+#define FSMC_PMEMx_MEMHOLDx_7 (0x80U << FSMC_PMEMx_MEMHOLDx_Pos) /*!< 0x00800000 */
+
+#define FSMC_PMEMx_MEMHIZx_Pos (24U)
+#define FSMC_PMEMx_MEMHIZx_Msk (0xFFU << FSMC_PMEMx_MEMHIZx_Pos) /*!< 0xFF000000 */
+#define FSMC_PMEMx_MEMHIZx FSMC_PMEMx_MEMHIZx_Msk /*!< MEMHIZx[7:0] bits (Common memory x databus HiZ time) */
+#define FSMC_PMEMx_MEMHIZx_0 (0x01U << FSMC_PMEMx_MEMHIZx_Pos) /*!< 0x01000000 */
+#define FSMC_PMEMx_MEMHIZx_1 (0x02U << FSMC_PMEMx_MEMHIZx_Pos) /*!< 0x02000000 */
+#define FSMC_PMEMx_MEMHIZx_2 (0x04U << FSMC_PMEMx_MEMHIZx_Pos) /*!< 0x04000000 */
+#define FSMC_PMEMx_MEMHIZx_3 (0x08U << FSMC_PMEMx_MEMHIZx_Pos) /*!< 0x08000000 */
+#define FSMC_PMEMx_MEMHIZx_4 (0x10U << FSMC_PMEMx_MEMHIZx_Pos) /*!< 0x10000000 */
+#define FSMC_PMEMx_MEMHIZx_5 (0x20U << FSMC_PMEMx_MEMHIZx_Pos) /*!< 0x20000000 */
+#define FSMC_PMEMx_MEMHIZx_6 (0x40U << FSMC_PMEMx_MEMHIZx_Pos) /*!< 0x40000000 */
+#define FSMC_PMEMx_MEMHIZx_7 (0x80U << FSMC_PMEMx_MEMHIZx_Pos) /*!< 0x80000000 */
+
+/****************** Bit definition for FSMC_PATTx (x = 2 to 4) register ******************/
+#define FSMC_PATTx_ATTSETx_Pos (0U)
+#define FSMC_PATTx_ATTSETx_Msk (0xFFU << FSMC_PATTx_ATTSETx_Pos) /*!< 0x000000FF */
+#define FSMC_PATTx_ATTSETx FSMC_PATTx_ATTSETx_Msk /*!< ATTSETx[7:0] bits (Attribute memory x setup time) */
+#define FSMC_PATTx_ATTSETx_0 (0x01U << FSMC_PATTx_ATTSETx_Pos) /*!< 0x00000001 */
+#define FSMC_PATTx_ATTSETx_1 (0x02U << FSMC_PATTx_ATTSETx_Pos) /*!< 0x00000002 */
+#define FSMC_PATTx_ATTSETx_2 (0x04U << FSMC_PATTx_ATTSETx_Pos) /*!< 0x00000004 */
+#define FSMC_PATTx_ATTSETx_3 (0x08U << FSMC_PATTx_ATTSETx_Pos) /*!< 0x00000008 */
+#define FSMC_PATTx_ATTSETx_4 (0x10U << FSMC_PATTx_ATTSETx_Pos) /*!< 0x00000010 */
+#define FSMC_PATTx_ATTSETx_5 (0x20U << FSMC_PATTx_ATTSETx_Pos) /*!< 0x00000020 */
+#define FSMC_PATTx_ATTSETx_6 (0x40U << FSMC_PATTx_ATTSETx_Pos) /*!< 0x00000040 */
+#define FSMC_PATTx_ATTSETx_7 (0x80U << FSMC_PATTx_ATTSETx_Pos) /*!< 0x00000080 */
+
+#define FSMC_PATTx_ATTWAITx_Pos (8U)
+#define FSMC_PATTx_ATTWAITx_Msk (0xFFU << FSMC_PATTx_ATTWAITx_Pos) /*!< 0x0000FF00 */
+#define FSMC_PATTx_ATTWAITx FSMC_PATTx_ATTWAITx_Msk /*!< ATTWAITx[7:0] bits (Attribute memory x wait time) */
+#define FSMC_PATTx_ATTWAITx_0 (0x01U << FSMC_PATTx_ATTWAITx_Pos) /*!< 0x00000100 */
+#define FSMC_PATTx_ATTWAITx_1 (0x02U << FSMC_PATTx_ATTWAITx_Pos) /*!< 0x00000200 */
+#define FSMC_PATTx_ATTWAITx_2 (0x04U << FSMC_PATTx_ATTWAITx_Pos) /*!< 0x00000400 */
+#define FSMC_PATTx_ATTWAITx_3 (0x08U << FSMC_PATTx_ATTWAITx_Pos) /*!< 0x00000800 */
+#define FSMC_PATTx_ATTWAITx_4 (0x10U << FSMC_PATTx_ATTWAITx_Pos) /*!< 0x00001000 */
+#define FSMC_PATTx_ATTWAITx_5 (0x20U << FSMC_PATTx_ATTWAITx_Pos) /*!< 0x00002000 */
+#define FSMC_PATTx_ATTWAITx_6 (0x40U << FSMC_PATTx_ATTWAITx_Pos) /*!< 0x00004000 */
+#define FSMC_PATTx_ATTWAITx_7 (0x80U << FSMC_PATTx_ATTWAITx_Pos) /*!< 0x00008000 */
+
+#define FSMC_PATTx_ATTHOLDx_Pos (16U)
+#define FSMC_PATTx_ATTHOLDx_Msk (0xFFU << FSMC_PATTx_ATTHOLDx_Pos) /*!< 0x00FF0000 */
+#define FSMC_PATTx_ATTHOLDx FSMC_PATTx_ATTHOLDx_Msk /*!< ATTHOLDx[7:0] bits (Attribute memory x hold time) */
+#define FSMC_PATTx_ATTHOLDx_0 (0x01U << FSMC_PATTx_ATTHOLDx_Pos) /*!< 0x00010000 */
+#define FSMC_PATTx_ATTHOLDx_1 (0x02U << FSMC_PATTx_ATTHOLDx_Pos) /*!< 0x00020000 */
+#define FSMC_PATTx_ATTHOLDx_2 (0x04U << FSMC_PATTx_ATTHOLDx_Pos) /*!< 0x00040000 */
+#define FSMC_PATTx_ATTHOLDx_3 (0x08U << FSMC_PATTx_ATTHOLDx_Pos) /*!< 0x00080000 */
+#define FSMC_PATTx_ATTHOLDx_4 (0x10U << FSMC_PATTx_ATTHOLDx_Pos) /*!< 0x00100000 */
+#define FSMC_PATTx_ATTHOLDx_5 (0x20U << FSMC_PATTx_ATTHOLDx_Pos) /*!< 0x00200000 */
+#define FSMC_PATTx_ATTHOLDx_6 (0x40U << FSMC_PATTx_ATTHOLDx_Pos) /*!< 0x00400000 */
+#define FSMC_PATTx_ATTHOLDx_7 (0x80U << FSMC_PATTx_ATTHOLDx_Pos) /*!< 0x00800000 */
+
+#define FSMC_PATTx_ATTHIZx_Pos (24U)
+#define FSMC_PATTx_ATTHIZx_Msk (0xFFU << FSMC_PATTx_ATTHIZx_Pos) /*!< 0xFF000000 */
+#define FSMC_PATTx_ATTHIZx FSMC_PATTx_ATTHIZx_Msk /*!< ATTHIZx[7:0] bits (Attribute memory x databus HiZ time) */
+#define FSMC_PATTx_ATTHIZx_0 (0x01U << FSMC_PATTx_ATTHIZx_Pos) /*!< 0x01000000 */
+#define FSMC_PATTx_ATTHIZx_1 (0x02U << FSMC_PATTx_ATTHIZx_Pos) /*!< 0x02000000 */
+#define FSMC_PATTx_ATTHIZx_2 (0x04U << FSMC_PATTx_ATTHIZx_Pos) /*!< 0x04000000 */
+#define FSMC_PATTx_ATTHIZx_3 (0x08U << FSMC_PATTx_ATTHIZx_Pos) /*!< 0x08000000 */
+#define FSMC_PATTx_ATTHIZx_4 (0x10U << FSMC_PATTx_ATTHIZx_Pos) /*!< 0x10000000 */
+#define FSMC_PATTx_ATTHIZx_5 (0x20U << FSMC_PATTx_ATTHIZx_Pos) /*!< 0x20000000 */
+#define FSMC_PATTx_ATTHIZx_6 (0x40U << FSMC_PATTx_ATTHIZx_Pos) /*!< 0x40000000 */
+#define FSMC_PATTx_ATTHIZx_7 (0x80U << FSMC_PATTx_ATTHIZx_Pos) /*!< 0x80000000 */
+
+/****************** Bit definition for FSMC_PIO4 register *******************/
+#define FSMC_PIO4_IOSET4_Pos (0U)
+#define FSMC_PIO4_IOSET4_Msk (0xFFU << FSMC_PIO4_IOSET4_Pos) /*!< 0x000000FF */
+#define FSMC_PIO4_IOSET4 FSMC_PIO4_IOSET4_Msk /*!< IOSET4[7:0] bits (I/O 4 setup time) */
+#define FSMC_PIO4_IOSET4_0 (0x01U << FSMC_PIO4_IOSET4_Pos) /*!< 0x00000001 */
+#define FSMC_PIO4_IOSET4_1 (0x02U << FSMC_PIO4_IOSET4_Pos) /*!< 0x00000002 */
+#define FSMC_PIO4_IOSET4_2 (0x04U << FSMC_PIO4_IOSET4_Pos) /*!< 0x00000004 */
+#define FSMC_PIO4_IOSET4_3 (0x08U << FSMC_PIO4_IOSET4_Pos) /*!< 0x00000008 */
+#define FSMC_PIO4_IOSET4_4 (0x10U << FSMC_PIO4_IOSET4_Pos) /*!< 0x00000010 */
+#define FSMC_PIO4_IOSET4_5 (0x20U << FSMC_PIO4_IOSET4_Pos) /*!< 0x00000020 */
+#define FSMC_PIO4_IOSET4_6 (0x40U << FSMC_PIO4_IOSET4_Pos) /*!< 0x00000040 */
+#define FSMC_PIO4_IOSET4_7 (0x80U << FSMC_PIO4_IOSET4_Pos) /*!< 0x00000080 */
+
+#define FSMC_PIO4_IOWAIT4_Pos (8U)
+#define FSMC_PIO4_IOWAIT4_Msk (0xFFU << FSMC_PIO4_IOWAIT4_Pos) /*!< 0x0000FF00 */
+#define FSMC_PIO4_IOWAIT4 FSMC_PIO4_IOWAIT4_Msk /*!< IOWAIT4[7:0] bits (I/O 4 wait time) */
+#define FSMC_PIO4_IOWAIT4_0 (0x01U << FSMC_PIO4_IOWAIT4_Pos) /*!< 0x00000100 */
+#define FSMC_PIO4_IOWAIT4_1 (0x02U << FSMC_PIO4_IOWAIT4_Pos) /*!< 0x00000200 */
+#define FSMC_PIO4_IOWAIT4_2 (0x04U << FSMC_PIO4_IOWAIT4_Pos) /*!< 0x00000400 */
+#define FSMC_PIO4_IOWAIT4_3 (0x08U << FSMC_PIO4_IOWAIT4_Pos) /*!< 0x00000800 */
+#define FSMC_PIO4_IOWAIT4_4 (0x10U << FSMC_PIO4_IOWAIT4_Pos) /*!< 0x00001000 */
+#define FSMC_PIO4_IOWAIT4_5 (0x20U << FSMC_PIO4_IOWAIT4_Pos) /*!< 0x00002000 */
+#define FSMC_PIO4_IOWAIT4_6 (0x40U << FSMC_PIO4_IOWAIT4_Pos) /*!< 0x00004000 */
+#define FSMC_PIO4_IOWAIT4_7 (0x80U << FSMC_PIO4_IOWAIT4_Pos) /*!< 0x00008000 */
+
+#define FSMC_PIO4_IOHOLD4_Pos (16U)
+#define FSMC_PIO4_IOHOLD4_Msk (0xFFU << FSMC_PIO4_IOHOLD4_Pos) /*!< 0x00FF0000 */
+#define FSMC_PIO4_IOHOLD4 FSMC_PIO4_IOHOLD4_Msk /*!< IOHOLD4[7:0] bits (I/O 4 hold time) */
+#define FSMC_PIO4_IOHOLD4_0 (0x01U << FSMC_PIO4_IOHOLD4_Pos) /*!< 0x00010000 */
+#define FSMC_PIO4_IOHOLD4_1 (0x02U << FSMC_PIO4_IOHOLD4_Pos) /*!< 0x00020000 */
+#define FSMC_PIO4_IOHOLD4_2 (0x04U << FSMC_PIO4_IOHOLD4_Pos) /*!< 0x00040000 */
+#define FSMC_PIO4_IOHOLD4_3 (0x08U << FSMC_PIO4_IOHOLD4_Pos) /*!< 0x00080000 */
+#define FSMC_PIO4_IOHOLD4_4 (0x10U << FSMC_PIO4_IOHOLD4_Pos) /*!< 0x00100000 */
+#define FSMC_PIO4_IOHOLD4_5 (0x20U << FSMC_PIO4_IOHOLD4_Pos) /*!< 0x00200000 */
+#define FSMC_PIO4_IOHOLD4_6 (0x40U << FSMC_PIO4_IOHOLD4_Pos) /*!< 0x00400000 */
+#define FSMC_PIO4_IOHOLD4_7 (0x80U << FSMC_PIO4_IOHOLD4_Pos) /*!< 0x00800000 */
+
+#define FSMC_PIO4_IOHIZ4_Pos (24U)
+#define FSMC_PIO4_IOHIZ4_Msk (0xFFU << FSMC_PIO4_IOHIZ4_Pos) /*!< 0xFF000000 */
+#define FSMC_PIO4_IOHIZ4 FSMC_PIO4_IOHIZ4_Msk /*!< IOHIZ4[7:0] bits (I/O 4 databus HiZ time) */
+#define FSMC_PIO4_IOHIZ4_0 (0x01U << FSMC_PIO4_IOHIZ4_Pos) /*!< 0x01000000 */
+#define FSMC_PIO4_IOHIZ4_1 (0x02U << FSMC_PIO4_IOHIZ4_Pos) /*!< 0x02000000 */
+#define FSMC_PIO4_IOHIZ4_2 (0x04U << FSMC_PIO4_IOHIZ4_Pos) /*!< 0x04000000 */
+#define FSMC_PIO4_IOHIZ4_3 (0x08U << FSMC_PIO4_IOHIZ4_Pos) /*!< 0x08000000 */
+#define FSMC_PIO4_IOHIZ4_4 (0x10U << FSMC_PIO4_IOHIZ4_Pos) /*!< 0x10000000 */
+#define FSMC_PIO4_IOHIZ4_5 (0x20U << FSMC_PIO4_IOHIZ4_Pos) /*!< 0x20000000 */
+#define FSMC_PIO4_IOHIZ4_6 (0x40U << FSMC_PIO4_IOHIZ4_Pos) /*!< 0x40000000 */
+#define FSMC_PIO4_IOHIZ4_7 (0x80U << FSMC_PIO4_IOHIZ4_Pos) /*!< 0x80000000 */
+
+/****************** Bit definition for FSMC_ECCR2 register ******************/
+#define FSMC_ECCR2_ECC2_Pos (0U)
+#define FSMC_ECCR2_ECC2_Msk (0xFFFFFFFFU << FSMC_ECCR2_ECC2_Pos) /*!< 0xFFFFFFFF */
+#define FSMC_ECCR2_ECC2 FSMC_ECCR2_ECC2_Msk /*!< ECC result */
+
+/****************** Bit definition for FSMC_ECCR3 register ******************/
+#define FSMC_ECCR3_ECC3_Pos (0U)
+#define FSMC_ECCR3_ECC3_Msk (0xFFFFFFFFU << FSMC_ECCR3_ECC3_Pos) /*!< 0xFFFFFFFF */
+#define FSMC_ECCR3_ECC3 FSMC_ECCR3_ECC3_Msk /*!< ECC result */
+
+/******************************************************************************/
+/* */
+/* SD host Interface */
+/* */
+/******************************************************************************/
+
+/****************** Bit definition for SDIO_POWER register ******************/
+#define SDIO_POWER_PWRCTRL_Pos (0U)
+#define SDIO_POWER_PWRCTRL_Msk (0x3U << SDIO_POWER_PWRCTRL_Pos) /*!< 0x00000003 */
+#define SDIO_POWER_PWRCTRL SDIO_POWER_PWRCTRL_Msk /*!< PWRCTRL[1:0] bits (Power supply control bits) */
+#define SDIO_POWER_PWRCTRL_0 (0x1U << SDIO_POWER_PWRCTRL_Pos) /*!< 0x01 */
+#define SDIO_POWER_PWRCTRL_1 (0x2U << SDIO_POWER_PWRCTRL_Pos) /*!< 0x02 */
+
+/****************** Bit definition for SDIO_CLKCR register ******************/
+#define SDIO_CLKCR_CLKDIV_Pos (0U)
+#define SDIO_CLKCR_CLKDIV_Msk (0xFFU << SDIO_CLKCR_CLKDIV_Pos) /*!< 0x000000FF */
+#define SDIO_CLKCR_CLKDIV SDIO_CLKCR_CLKDIV_Msk /*!< Clock divide factor */
+#define SDIO_CLKCR_CLKEN_Pos (8U)
+#define SDIO_CLKCR_CLKEN_Msk (0x1U << SDIO_CLKCR_CLKEN_Pos) /*!< 0x00000100 */
+#define SDIO_CLKCR_CLKEN SDIO_CLKCR_CLKEN_Msk /*!< Clock enable bit */
+#define SDIO_CLKCR_PWRSAV_Pos (9U)
+#define SDIO_CLKCR_PWRSAV_Msk (0x1U << SDIO_CLKCR_PWRSAV_Pos) /*!< 0x00000200 */
+#define SDIO_CLKCR_PWRSAV SDIO_CLKCR_PWRSAV_Msk /*!< Power saving configuration bit */
+#define SDIO_CLKCR_BYPASS_Pos (10U)
+#define SDIO_CLKCR_BYPASS_Msk (0x1U << SDIO_CLKCR_BYPASS_Pos) /*!< 0x00000400 */
+#define SDIO_CLKCR_BYPASS SDIO_CLKCR_BYPASS_Msk /*!< Clock divider bypass enable bit */
+
+#define SDIO_CLKCR_WIDBUS_Pos (11U)
+#define SDIO_CLKCR_WIDBUS_Msk (0x3U << SDIO_CLKCR_WIDBUS_Pos) /*!< 0x00001800 */
+#define SDIO_CLKCR_WIDBUS SDIO_CLKCR_WIDBUS_Msk /*!< WIDBUS[1:0] bits (Wide bus mode enable bit) */
+#define SDIO_CLKCR_WIDBUS_0 (0x1U << SDIO_CLKCR_WIDBUS_Pos) /*!< 0x0800 */
+#define SDIO_CLKCR_WIDBUS_1 (0x2U << SDIO_CLKCR_WIDBUS_Pos) /*!< 0x1000 */
+
+#define SDIO_CLKCR_NEGEDGE_Pos (13U)
+#define SDIO_CLKCR_NEGEDGE_Msk (0x1U << SDIO_CLKCR_NEGEDGE_Pos) /*!< 0x00002000 */
+#define SDIO_CLKCR_NEGEDGE SDIO_CLKCR_NEGEDGE_Msk /*!< SDIO_CK dephasing selection bit */
+#define SDIO_CLKCR_HWFC_EN_Pos (14U)
+#define SDIO_CLKCR_HWFC_EN_Msk (0x1U << SDIO_CLKCR_HWFC_EN_Pos) /*!< 0x00004000 */
+#define SDIO_CLKCR_HWFC_EN SDIO_CLKCR_HWFC_EN_Msk /*!< HW Flow Control enable */
+
+/******************* Bit definition for SDIO_ARG register *******************/
+#define SDIO_ARG_CMDARG_Pos (0U)
+#define SDIO_ARG_CMDARG_Msk (0xFFFFFFFFU << SDIO_ARG_CMDARG_Pos) /*!< 0xFFFFFFFF */
+#define SDIO_ARG_CMDARG SDIO_ARG_CMDARG_Msk /*!< Command argument */
+
+/******************* Bit definition for SDIO_CMD register *******************/
+#define SDIO_CMD_CMDINDEX_Pos (0U)
+#define SDIO_CMD_CMDINDEX_Msk (0x3FU << SDIO_CMD_CMDINDEX_Pos) /*!< 0x0000003F */
+#define SDIO_CMD_CMDINDEX SDIO_CMD_CMDINDEX_Msk /*!< Command Index */
+
+#define SDIO_CMD_WAITRESP_Pos (6U)
+#define SDIO_CMD_WAITRESP_Msk (0x3U << SDIO_CMD_WAITRESP_Pos) /*!< 0x000000C0 */
+#define SDIO_CMD_WAITRESP SDIO_CMD_WAITRESP_Msk /*!< WAITRESP[1:0] bits (Wait for response bits) */
+#define SDIO_CMD_WAITRESP_0 (0x1U << SDIO_CMD_WAITRESP_Pos) /*!< 0x0040 */
+#define SDIO_CMD_WAITRESP_1 (0x2U << SDIO_CMD_WAITRESP_Pos) /*!< 0x0080 */
+
+#define SDIO_CMD_WAITINT_Pos (8U)
+#define SDIO_CMD_WAITINT_Msk (0x1U << SDIO_CMD_WAITINT_Pos) /*!< 0x00000100 */
+#define SDIO_CMD_WAITINT SDIO_CMD_WAITINT_Msk /*!< CPSM Waits for Interrupt Request */
+#define SDIO_CMD_WAITPEND_Pos (9U)
+#define SDIO_CMD_WAITPEND_Msk (0x1U << SDIO_CMD_WAITPEND_Pos) /*!< 0x00000200 */
+#define SDIO_CMD_WAITPEND SDIO_CMD_WAITPEND_Msk /*!< CPSM Waits for ends of data transfer (CmdPend internal signal) */
+#define SDIO_CMD_CPSMEN_Pos (10U)
+#define SDIO_CMD_CPSMEN_Msk (0x1U << SDIO_CMD_CPSMEN_Pos) /*!< 0x00000400 */
+#define SDIO_CMD_CPSMEN SDIO_CMD_CPSMEN_Msk /*!< Command path state machine (CPSM) Enable bit */
+#define SDIO_CMD_SDIOSUSPEND_Pos (11U)
+#define SDIO_CMD_SDIOSUSPEND_Msk (0x1U << SDIO_CMD_SDIOSUSPEND_Pos) /*!< 0x00000800 */
+#define SDIO_CMD_SDIOSUSPEND SDIO_CMD_SDIOSUSPEND_Msk /*!< SD I/O suspend command */
+#define SDIO_CMD_ENCMDCOMPL_Pos (12U)
+#define SDIO_CMD_ENCMDCOMPL_Msk (0x1U << SDIO_CMD_ENCMDCOMPL_Pos) /*!< 0x00001000 */
+#define SDIO_CMD_ENCMDCOMPL SDIO_CMD_ENCMDCOMPL_Msk /*!< Enable CMD completion */
+#define SDIO_CMD_NIEN_Pos (13U)
+#define SDIO_CMD_NIEN_Msk (0x1U << SDIO_CMD_NIEN_Pos) /*!< 0x00002000 */
+#define SDIO_CMD_NIEN SDIO_CMD_NIEN_Msk /*!< Not Interrupt Enable */
+#define SDIO_CMD_CEATACMD_Pos (14U)
+#define SDIO_CMD_CEATACMD_Msk (0x1U << SDIO_CMD_CEATACMD_Pos) /*!< 0x00004000 */
+#define SDIO_CMD_CEATACMD SDIO_CMD_CEATACMD_Msk /*!< CE-ATA command */
+
+/***************** Bit definition for SDIO_RESPCMD register *****************/
+#define SDIO_RESPCMD_RESPCMD_Pos (0U)
+#define SDIO_RESPCMD_RESPCMD_Msk (0x3FU << SDIO_RESPCMD_RESPCMD_Pos) /*!< 0x0000003F */
+#define SDIO_RESPCMD_RESPCMD SDIO_RESPCMD_RESPCMD_Msk /*!< Response command index */
+
+/****************** Bit definition for SDIO_RESP0 register ******************/
+#define SDIO_RESP0_CARDSTATUS0_Pos (0U)
+#define SDIO_RESP0_CARDSTATUS0_Msk (0xFFFFFFFFU << SDIO_RESP0_CARDSTATUS0_Pos) /*!< 0xFFFFFFFF */
+#define SDIO_RESP0_CARDSTATUS0 SDIO_RESP0_CARDSTATUS0_Msk /*!< Card Status */
+
+/****************** Bit definition for SDIO_RESP1 register ******************/
+#define SDIO_RESP1_CARDSTATUS1_Pos (0U)
+#define SDIO_RESP1_CARDSTATUS1_Msk (0xFFFFFFFFU << SDIO_RESP1_CARDSTATUS1_Pos) /*!< 0xFFFFFFFF */
+#define SDIO_RESP1_CARDSTATUS1 SDIO_RESP1_CARDSTATUS1_Msk /*!< Card Status */
+
+/****************** Bit definition for SDIO_RESP2 register ******************/
+#define SDIO_RESP2_CARDSTATUS2_Pos (0U)
+#define SDIO_RESP2_CARDSTATUS2_Msk (0xFFFFFFFFU << SDIO_RESP2_CARDSTATUS2_Pos) /*!< 0xFFFFFFFF */
+#define SDIO_RESP2_CARDSTATUS2 SDIO_RESP2_CARDSTATUS2_Msk /*!< Card Status */
+
+/****************** Bit definition for SDIO_RESP3 register ******************/
+#define SDIO_RESP3_CARDSTATUS3_Pos (0U)
+#define SDIO_RESP3_CARDSTATUS3_Msk (0xFFFFFFFFU << SDIO_RESP3_CARDSTATUS3_Pos) /*!< 0xFFFFFFFF */
+#define SDIO_RESP3_CARDSTATUS3 SDIO_RESP3_CARDSTATUS3_Msk /*!< Card Status */
+
+/****************** Bit definition for SDIO_RESP4 register ******************/
+#define SDIO_RESP4_CARDSTATUS4_Pos (0U)
+#define SDIO_RESP4_CARDSTATUS4_Msk (0xFFFFFFFFU << SDIO_RESP4_CARDSTATUS4_Pos) /*!< 0xFFFFFFFF */
+#define SDIO_RESP4_CARDSTATUS4 SDIO_RESP4_CARDSTATUS4_Msk /*!< Card Status */
+
+/****************** Bit definition for SDIO_DTIMER register *****************/
+#define SDIO_DTIMER_DATATIME_Pos (0U)
+#define SDIO_DTIMER_DATATIME_Msk (0xFFFFFFFFU << SDIO_DTIMER_DATATIME_Pos) /*!< 0xFFFFFFFF */
+#define SDIO_DTIMER_DATATIME SDIO_DTIMER_DATATIME_Msk /*!< Data timeout period. */
+
+/****************** Bit definition for SDIO_DLEN register *******************/
+#define SDIO_DLEN_DATALENGTH_Pos (0U)
+#define SDIO_DLEN_DATALENGTH_Msk (0x1FFFFFFU << SDIO_DLEN_DATALENGTH_Pos) /*!< 0x01FFFFFF */
+#define SDIO_DLEN_DATALENGTH SDIO_DLEN_DATALENGTH_Msk /*!< Data length value */
+
+/****************** Bit definition for SDIO_DCTRL register ******************/
+#define SDIO_DCTRL_DTEN_Pos (0U)
+#define SDIO_DCTRL_DTEN_Msk (0x1U << SDIO_DCTRL_DTEN_Pos) /*!< 0x00000001 */
+#define SDIO_DCTRL_DTEN SDIO_DCTRL_DTEN_Msk /*!< Data transfer enabled bit */
+#define SDIO_DCTRL_DTDIR_Pos (1U)
+#define SDIO_DCTRL_DTDIR_Msk (0x1U << SDIO_DCTRL_DTDIR_Pos) /*!< 0x00000002 */
+#define SDIO_DCTRL_DTDIR SDIO_DCTRL_DTDIR_Msk /*!< Data transfer direction selection */
+#define SDIO_DCTRL_DTMODE_Pos (2U)
+#define SDIO_DCTRL_DTMODE_Msk (0x1U << SDIO_DCTRL_DTMODE_Pos) /*!< 0x00000004 */
+#define SDIO_DCTRL_DTMODE SDIO_DCTRL_DTMODE_Msk /*!< Data transfer mode selection */
+#define SDIO_DCTRL_DMAEN_Pos (3U)
+#define SDIO_DCTRL_DMAEN_Msk (0x1U << SDIO_DCTRL_DMAEN_Pos) /*!< 0x00000008 */
+#define SDIO_DCTRL_DMAEN SDIO_DCTRL_DMAEN_Msk /*!< DMA enabled bit */
+
+#define SDIO_DCTRL_DBLOCKSIZE_Pos (4U)
+#define SDIO_DCTRL_DBLOCKSIZE_Msk (0xFU << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x000000F0 */
+#define SDIO_DCTRL_DBLOCKSIZE SDIO_DCTRL_DBLOCKSIZE_Msk /*!< DBLOCKSIZE[3:0] bits (Data block size) */
+#define SDIO_DCTRL_DBLOCKSIZE_0 (0x1U << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0010 */
+#define SDIO_DCTRL_DBLOCKSIZE_1 (0x2U << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0020 */
+#define SDIO_DCTRL_DBLOCKSIZE_2 (0x4U << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0040 */
+#define SDIO_DCTRL_DBLOCKSIZE_3 (0x8U << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0080 */
+
+#define SDIO_DCTRL_RWSTART_Pos (8U)
+#define SDIO_DCTRL_RWSTART_Msk (0x1U << SDIO_DCTRL_RWSTART_Pos) /*!< 0x00000100 */
+#define SDIO_DCTRL_RWSTART SDIO_DCTRL_RWSTART_Msk /*!< Read wait start */
+#define SDIO_DCTRL_RWSTOP_Pos (9U)
+#define SDIO_DCTRL_RWSTOP_Msk (0x1U << SDIO_DCTRL_RWSTOP_Pos) /*!< 0x00000200 */
+#define SDIO_DCTRL_RWSTOP SDIO_DCTRL_RWSTOP_Msk /*!< Read wait stop */
+#define SDIO_DCTRL_RWMOD_Pos (10U)
+#define SDIO_DCTRL_RWMOD_Msk (0x1U << SDIO_DCTRL_RWMOD_Pos) /*!< 0x00000400 */
+#define SDIO_DCTRL_RWMOD SDIO_DCTRL_RWMOD_Msk /*!< Read wait mode */
+#define SDIO_DCTRL_SDIOEN_Pos (11U)
+#define SDIO_DCTRL_SDIOEN_Msk (0x1U << SDIO_DCTRL_SDIOEN_Pos) /*!< 0x00000800 */
+#define SDIO_DCTRL_SDIOEN SDIO_DCTRL_SDIOEN_Msk /*!< SD I/O enable functions */
+
+/****************** Bit definition for SDIO_DCOUNT register *****************/
+#define SDIO_DCOUNT_DATACOUNT_Pos (0U)
+#define SDIO_DCOUNT_DATACOUNT_Msk (0x1FFFFFFU << SDIO_DCOUNT_DATACOUNT_Pos) /*!< 0x01FFFFFF */
+#define SDIO_DCOUNT_DATACOUNT SDIO_DCOUNT_DATACOUNT_Msk /*!< Data count value */
+
+/****************** Bit definition for SDIO_STA register ********************/
+#define SDIO_STA_CCRCFAIL_Pos (0U)
+#define SDIO_STA_CCRCFAIL_Msk (0x1U << SDIO_STA_CCRCFAIL_Pos) /*!< 0x00000001 */
+#define SDIO_STA_CCRCFAIL SDIO_STA_CCRCFAIL_Msk /*!< Command response received (CRC check failed) */
+#define SDIO_STA_DCRCFAIL_Pos (1U)
+#define SDIO_STA_DCRCFAIL_Msk (0x1U << SDIO_STA_DCRCFAIL_Pos) /*!< 0x00000002 */
+#define SDIO_STA_DCRCFAIL SDIO_STA_DCRCFAIL_Msk /*!< Data block sent/received (CRC check failed) */
+#define SDIO_STA_CTIMEOUT_Pos (2U)
+#define SDIO_STA_CTIMEOUT_Msk (0x1U << SDIO_STA_CTIMEOUT_Pos) /*!< 0x00000004 */
+#define SDIO_STA_CTIMEOUT SDIO_STA_CTIMEOUT_Msk /*!< Command response timeout */
+#define SDIO_STA_DTIMEOUT_Pos (3U)
+#define SDIO_STA_DTIMEOUT_Msk (0x1U << SDIO_STA_DTIMEOUT_Pos) /*!< 0x00000008 */
+#define SDIO_STA_DTIMEOUT SDIO_STA_DTIMEOUT_Msk /*!< Data timeout */
+#define SDIO_STA_TXUNDERR_Pos (4U)
+#define SDIO_STA_TXUNDERR_Msk (0x1U << SDIO_STA_TXUNDERR_Pos) /*!< 0x00000010 */
+#define SDIO_STA_TXUNDERR SDIO_STA_TXUNDERR_Msk /*!< Transmit FIFO underrun error */
+#define SDIO_STA_RXOVERR_Pos (5U)
+#define SDIO_STA_RXOVERR_Msk (0x1U << SDIO_STA_RXOVERR_Pos) /*!< 0x00000020 */
+#define SDIO_STA_RXOVERR SDIO_STA_RXOVERR_Msk /*!< Received FIFO overrun error */
+#define SDIO_STA_CMDREND_Pos (6U)
+#define SDIO_STA_CMDREND_Msk (0x1U << SDIO_STA_CMDREND_Pos) /*!< 0x00000040 */
+#define SDIO_STA_CMDREND SDIO_STA_CMDREND_Msk /*!< Command response received (CRC check passed) */
+#define SDIO_STA_CMDSENT_Pos (7U)
+#define SDIO_STA_CMDSENT_Msk (0x1U << SDIO_STA_CMDSENT_Pos) /*!< 0x00000080 */
+#define SDIO_STA_CMDSENT SDIO_STA_CMDSENT_Msk /*!< Command sent (no response required) */
+#define SDIO_STA_DATAEND_Pos (8U)
+#define SDIO_STA_DATAEND_Msk (0x1U << SDIO_STA_DATAEND_Pos) /*!< 0x00000100 */
+#define SDIO_STA_DATAEND SDIO_STA_DATAEND_Msk /*!< Data end (data counter, SDIDCOUNT, is zero) */
+#define SDIO_STA_STBITERR_Pos (9U)
+#define SDIO_STA_STBITERR_Msk (0x1U << SDIO_STA_STBITERR_Pos) /*!< 0x00000200 */
+#define SDIO_STA_STBITERR SDIO_STA_STBITERR_Msk /*!< Start bit not detected on all data signals in wide bus mode */
+#define SDIO_STA_DBCKEND_Pos (10U)
+#define SDIO_STA_DBCKEND_Msk (0x1U << SDIO_STA_DBCKEND_Pos) /*!< 0x00000400 */
+#define SDIO_STA_DBCKEND SDIO_STA_DBCKEND_Msk /*!< Data block sent/received (CRC check passed) */
+#define SDIO_STA_CMDACT_Pos (11U)
+#define SDIO_STA_CMDACT_Msk (0x1U << SDIO_STA_CMDACT_Pos) /*!< 0x00000800 */
+#define SDIO_STA_CMDACT SDIO_STA_CMDACT_Msk /*!< Command transfer in progress */
+#define SDIO_STA_TXACT_Pos (12U)
+#define SDIO_STA_TXACT_Msk (0x1U << SDIO_STA_TXACT_Pos) /*!< 0x00001000 */
+#define SDIO_STA_TXACT SDIO_STA_TXACT_Msk /*!< Data transmit in progress */
+#define SDIO_STA_RXACT_Pos (13U)
+#define SDIO_STA_RXACT_Msk (0x1U << SDIO_STA_RXACT_Pos) /*!< 0x00002000 */
+#define SDIO_STA_RXACT SDIO_STA_RXACT_Msk /*!< Data receive in progress */
+#define SDIO_STA_TXFIFOHE_Pos (14U)
+#define SDIO_STA_TXFIFOHE_Msk (0x1U << SDIO_STA_TXFIFOHE_Pos) /*!< 0x00004000 */
+#define SDIO_STA_TXFIFOHE SDIO_STA_TXFIFOHE_Msk /*!< Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
+#define SDIO_STA_RXFIFOHF_Pos (15U)
+#define SDIO_STA_RXFIFOHF_Msk (0x1U << SDIO_STA_RXFIFOHF_Pos) /*!< 0x00008000 */
+#define SDIO_STA_RXFIFOHF SDIO_STA_RXFIFOHF_Msk /*!< Receive FIFO Half Full: there are at least 8 words in the FIFO */
+#define SDIO_STA_TXFIFOF_Pos (16U)
+#define SDIO_STA_TXFIFOF_Msk (0x1U << SDIO_STA_TXFIFOF_Pos) /*!< 0x00010000 */
+#define SDIO_STA_TXFIFOF SDIO_STA_TXFIFOF_Msk /*!< Transmit FIFO full */
+#define SDIO_STA_RXFIFOF_Pos (17U)
+#define SDIO_STA_RXFIFOF_Msk (0x1U << SDIO_STA_RXFIFOF_Pos) /*!< 0x00020000 */
+#define SDIO_STA_RXFIFOF SDIO_STA_RXFIFOF_Msk /*!< Receive FIFO full */
+#define SDIO_STA_TXFIFOE_Pos (18U)
+#define SDIO_STA_TXFIFOE_Msk (0x1U << SDIO_STA_TXFIFOE_Pos) /*!< 0x00040000 */
+#define SDIO_STA_TXFIFOE SDIO_STA_TXFIFOE_Msk /*!< Transmit FIFO empty */
+#define SDIO_STA_RXFIFOE_Pos (19U)
+#define SDIO_STA_RXFIFOE_Msk (0x1U << SDIO_STA_RXFIFOE_Pos) /*!< 0x00080000 */
+#define SDIO_STA_RXFIFOE SDIO_STA_RXFIFOE_Msk /*!< Receive FIFO empty */
+#define SDIO_STA_TXDAVL_Pos (20U)
+#define SDIO_STA_TXDAVL_Msk (0x1U << SDIO_STA_TXDAVL_Pos) /*!< 0x00100000 */
+#define SDIO_STA_TXDAVL SDIO_STA_TXDAVL_Msk /*!< Data available in transmit FIFO */
+#define SDIO_STA_RXDAVL_Pos (21U)
+#define SDIO_STA_RXDAVL_Msk (0x1U << SDIO_STA_RXDAVL_Pos) /*!< 0x00200000 */
+#define SDIO_STA_RXDAVL SDIO_STA_RXDAVL_Msk /*!< Data available in receive FIFO */
+#define SDIO_STA_SDIOIT_Pos (22U)
+#define SDIO_STA_SDIOIT_Msk (0x1U << SDIO_STA_SDIOIT_Pos) /*!< 0x00400000 */
+#define SDIO_STA_SDIOIT SDIO_STA_SDIOIT_Msk /*!< SDIO interrupt received */
+#define SDIO_STA_CEATAEND_Pos (23U)
+#define SDIO_STA_CEATAEND_Msk (0x1U << SDIO_STA_CEATAEND_Pos) /*!< 0x00800000 */
+#define SDIO_STA_CEATAEND SDIO_STA_CEATAEND_Msk /*!< CE-ATA command completion signal received for CMD61 */
+
+/******************* Bit definition for SDIO_ICR register *******************/
+#define SDIO_ICR_CCRCFAILC_Pos (0U)
+#define SDIO_ICR_CCRCFAILC_Msk (0x1U << SDIO_ICR_CCRCFAILC_Pos) /*!< 0x00000001 */
+#define SDIO_ICR_CCRCFAILC SDIO_ICR_CCRCFAILC_Msk /*!< CCRCFAIL flag clear bit */
+#define SDIO_ICR_DCRCFAILC_Pos (1U)
+#define SDIO_ICR_DCRCFAILC_Msk (0x1U << SDIO_ICR_DCRCFAILC_Pos) /*!< 0x00000002 */
+#define SDIO_ICR_DCRCFAILC SDIO_ICR_DCRCFAILC_Msk /*!< DCRCFAIL flag clear bit */
+#define SDIO_ICR_CTIMEOUTC_Pos (2U)
+#define SDIO_ICR_CTIMEOUTC_Msk (0x1U << SDIO_ICR_CTIMEOUTC_Pos) /*!< 0x00000004 */
+#define SDIO_ICR_CTIMEOUTC SDIO_ICR_CTIMEOUTC_Msk /*!< CTIMEOUT flag clear bit */
+#define SDIO_ICR_DTIMEOUTC_Pos (3U)
+#define SDIO_ICR_DTIMEOUTC_Msk (0x1U << SDIO_ICR_DTIMEOUTC_Pos) /*!< 0x00000008 */
+#define SDIO_ICR_DTIMEOUTC SDIO_ICR_DTIMEOUTC_Msk /*!< DTIMEOUT flag clear bit */
+#define SDIO_ICR_TXUNDERRC_Pos (4U)
+#define SDIO_ICR_TXUNDERRC_Msk (0x1U << SDIO_ICR_TXUNDERRC_Pos) /*!< 0x00000010 */
+#define SDIO_ICR_TXUNDERRC SDIO_ICR_TXUNDERRC_Msk /*!< TXUNDERR flag clear bit */
+#define SDIO_ICR_RXOVERRC_Pos (5U)
+#define SDIO_ICR_RXOVERRC_Msk (0x1U << SDIO_ICR_RXOVERRC_Pos) /*!< 0x00000020 */
+#define SDIO_ICR_RXOVERRC SDIO_ICR_RXOVERRC_Msk /*!< RXOVERR flag clear bit */
+#define SDIO_ICR_CMDRENDC_Pos (6U)
+#define SDIO_ICR_CMDRENDC_Msk (0x1U << SDIO_ICR_CMDRENDC_Pos) /*!< 0x00000040 */
+#define SDIO_ICR_CMDRENDC SDIO_ICR_CMDRENDC_Msk /*!< CMDREND flag clear bit */
+#define SDIO_ICR_CMDSENTC_Pos (7U)
+#define SDIO_ICR_CMDSENTC_Msk (0x1U << SDIO_ICR_CMDSENTC_Pos) /*!< 0x00000080 */
+#define SDIO_ICR_CMDSENTC SDIO_ICR_CMDSENTC_Msk /*!< CMDSENT flag clear bit */
+#define SDIO_ICR_DATAENDC_Pos (8U)
+#define SDIO_ICR_DATAENDC_Msk (0x1U << SDIO_ICR_DATAENDC_Pos) /*!< 0x00000100 */
+#define SDIO_ICR_DATAENDC SDIO_ICR_DATAENDC_Msk /*!< DATAEND flag clear bit */
+#define SDIO_ICR_STBITERRC_Pos (9U)
+#define SDIO_ICR_STBITERRC_Msk (0x1U << SDIO_ICR_STBITERRC_Pos) /*!< 0x00000200 */
+#define SDIO_ICR_STBITERRC SDIO_ICR_STBITERRC_Msk /*!< STBITERR flag clear bit */
+#define SDIO_ICR_DBCKENDC_Pos (10U)
+#define SDIO_ICR_DBCKENDC_Msk (0x1U << SDIO_ICR_DBCKENDC_Pos) /*!< 0x00000400 */
+#define SDIO_ICR_DBCKENDC SDIO_ICR_DBCKENDC_Msk /*!< DBCKEND flag clear bit */
+#define SDIO_ICR_SDIOITC_Pos (22U)
+#define SDIO_ICR_SDIOITC_Msk (0x1U << SDIO_ICR_SDIOITC_Pos) /*!< 0x00400000 */
+#define SDIO_ICR_SDIOITC SDIO_ICR_SDIOITC_Msk /*!< SDIOIT flag clear bit */
+#define SDIO_ICR_CEATAENDC_Pos (23U)
+#define SDIO_ICR_CEATAENDC_Msk (0x1U << SDIO_ICR_CEATAENDC_Pos) /*!< 0x00800000 */
+#define SDIO_ICR_CEATAENDC SDIO_ICR_CEATAENDC_Msk /*!< CEATAEND flag clear bit */
+
+/****************** Bit definition for SDIO_MASK register *******************/
+#define SDIO_MASK_CCRCFAILIE_Pos (0U)
+#define SDIO_MASK_CCRCFAILIE_Msk (0x1U << SDIO_MASK_CCRCFAILIE_Pos) /*!< 0x00000001 */
+#define SDIO_MASK_CCRCFAILIE SDIO_MASK_CCRCFAILIE_Msk /*!< Command CRC Fail Interrupt Enable */
+#define SDIO_MASK_DCRCFAILIE_Pos (1U)
+#define SDIO_MASK_DCRCFAILIE_Msk (0x1U << SDIO_MASK_DCRCFAILIE_Pos) /*!< 0x00000002 */
+#define SDIO_MASK_DCRCFAILIE SDIO_MASK_DCRCFAILIE_Msk /*!< Data CRC Fail Interrupt Enable */
+#define SDIO_MASK_CTIMEOUTIE_Pos (2U)
+#define SDIO_MASK_CTIMEOUTIE_Msk (0x1U << SDIO_MASK_CTIMEOUTIE_Pos) /*!< 0x00000004 */
+#define SDIO_MASK_CTIMEOUTIE SDIO_MASK_CTIMEOUTIE_Msk /*!< Command TimeOut Interrupt Enable */
+#define SDIO_MASK_DTIMEOUTIE_Pos (3U)
+#define SDIO_MASK_DTIMEOUTIE_Msk (0x1U << SDIO_MASK_DTIMEOUTIE_Pos) /*!< 0x00000008 */
+#define SDIO_MASK_DTIMEOUTIE SDIO_MASK_DTIMEOUTIE_Msk /*!< Data TimeOut Interrupt Enable */
+#define SDIO_MASK_TXUNDERRIE_Pos (4U)
+#define SDIO_MASK_TXUNDERRIE_Msk (0x1U << SDIO_MASK_TXUNDERRIE_Pos) /*!< 0x00000010 */
+#define SDIO_MASK_TXUNDERRIE SDIO_MASK_TXUNDERRIE_Msk /*!< Tx FIFO UnderRun Error Interrupt Enable */
+#define SDIO_MASK_RXOVERRIE_Pos (5U)
+#define SDIO_MASK_RXOVERRIE_Msk (0x1U << SDIO_MASK_RXOVERRIE_Pos) /*!< 0x00000020 */
+#define SDIO_MASK_RXOVERRIE SDIO_MASK_RXOVERRIE_Msk /*!< Rx FIFO OverRun Error Interrupt Enable */
+#define SDIO_MASK_CMDRENDIE_Pos (6U)
+#define SDIO_MASK_CMDRENDIE_Msk (0x1U << SDIO_MASK_CMDRENDIE_Pos) /*!< 0x00000040 */
+#define SDIO_MASK_CMDRENDIE SDIO_MASK_CMDRENDIE_Msk /*!< Command Response Received Interrupt Enable */
+#define SDIO_MASK_CMDSENTIE_Pos (7U)
+#define SDIO_MASK_CMDSENTIE_Msk (0x1U << SDIO_MASK_CMDSENTIE_Pos) /*!< 0x00000080 */
+#define SDIO_MASK_CMDSENTIE SDIO_MASK_CMDSENTIE_Msk /*!< Command Sent Interrupt Enable */
+#define SDIO_MASK_DATAENDIE_Pos (8U)
+#define SDIO_MASK_DATAENDIE_Msk (0x1U << SDIO_MASK_DATAENDIE_Pos) /*!< 0x00000100 */
+#define SDIO_MASK_DATAENDIE SDIO_MASK_DATAENDIE_Msk /*!< Data End Interrupt Enable */
+#define SDIO_MASK_STBITERRIE_Pos (9U)
+#define SDIO_MASK_STBITERRIE_Msk (0x1U << SDIO_MASK_STBITERRIE_Pos) /*!< 0x00000200 */
+#define SDIO_MASK_STBITERRIE SDIO_MASK_STBITERRIE_Msk /*!< Start Bit Error Interrupt Enable */
+#define SDIO_MASK_DBCKENDIE_Pos (10U)
+#define SDIO_MASK_DBCKENDIE_Msk (0x1U << SDIO_MASK_DBCKENDIE_Pos) /*!< 0x00000400 */
+#define SDIO_MASK_DBCKENDIE SDIO_MASK_DBCKENDIE_Msk /*!< Data Block End Interrupt Enable */
+#define SDIO_MASK_CMDACTIE_Pos (11U)
+#define SDIO_MASK_CMDACTIE_Msk (0x1U << SDIO_MASK_CMDACTIE_Pos) /*!< 0x00000800 */
+#define SDIO_MASK_CMDACTIE SDIO_MASK_CMDACTIE_Msk /*!< Command Acting Interrupt Enable */
+#define SDIO_MASK_TXACTIE_Pos (12U)
+#define SDIO_MASK_TXACTIE_Msk (0x1U << SDIO_MASK_TXACTIE_Pos) /*!< 0x00001000 */
+#define SDIO_MASK_TXACTIE SDIO_MASK_TXACTIE_Msk /*!< Data Transmit Acting Interrupt Enable */
+#define SDIO_MASK_RXACTIE_Pos (13U)
+#define SDIO_MASK_RXACTIE_Msk (0x1U << SDIO_MASK_RXACTIE_Pos) /*!< 0x00002000 */
+#define SDIO_MASK_RXACTIE SDIO_MASK_RXACTIE_Msk /*!< Data receive acting interrupt enabled */
+#define SDIO_MASK_TXFIFOHEIE_Pos (14U)
+#define SDIO_MASK_TXFIFOHEIE_Msk (0x1U << SDIO_MASK_TXFIFOHEIE_Pos) /*!< 0x00004000 */
+#define SDIO_MASK_TXFIFOHEIE SDIO_MASK_TXFIFOHEIE_Msk /*!< Tx FIFO Half Empty interrupt Enable */
+#define SDIO_MASK_RXFIFOHFIE_Pos (15U)
+#define SDIO_MASK_RXFIFOHFIE_Msk (0x1U << SDIO_MASK_RXFIFOHFIE_Pos) /*!< 0x00008000 */
+#define SDIO_MASK_RXFIFOHFIE SDIO_MASK_RXFIFOHFIE_Msk /*!< Rx FIFO Half Full interrupt Enable */
+#define SDIO_MASK_TXFIFOFIE_Pos (16U)
+#define SDIO_MASK_TXFIFOFIE_Msk (0x1U << SDIO_MASK_TXFIFOFIE_Pos) /*!< 0x00010000 */
+#define SDIO_MASK_TXFIFOFIE SDIO_MASK_TXFIFOFIE_Msk /*!< Tx FIFO Full interrupt Enable */
+#define SDIO_MASK_RXFIFOFIE_Pos (17U)
+#define SDIO_MASK_RXFIFOFIE_Msk (0x1U << SDIO_MASK_RXFIFOFIE_Pos) /*!< 0x00020000 */
+#define SDIO_MASK_RXFIFOFIE SDIO_MASK_RXFIFOFIE_Msk /*!< Rx FIFO Full interrupt Enable */
+#define SDIO_MASK_TXFIFOEIE_Pos (18U)
+#define SDIO_MASK_TXFIFOEIE_Msk (0x1U << SDIO_MASK_TXFIFOEIE_Pos) /*!< 0x00040000 */
+#define SDIO_MASK_TXFIFOEIE SDIO_MASK_TXFIFOEIE_Msk /*!< Tx FIFO Empty interrupt Enable */
+#define SDIO_MASK_RXFIFOEIE_Pos (19U)
+#define SDIO_MASK_RXFIFOEIE_Msk (0x1U << SDIO_MASK_RXFIFOEIE_Pos) /*!< 0x00080000 */
+#define SDIO_MASK_RXFIFOEIE SDIO_MASK_RXFIFOEIE_Msk /*!< Rx FIFO Empty interrupt Enable */
+#define SDIO_MASK_TXDAVLIE_Pos (20U)
+#define SDIO_MASK_TXDAVLIE_Msk (0x1U << SDIO_MASK_TXDAVLIE_Pos) /*!< 0x00100000 */
+#define SDIO_MASK_TXDAVLIE SDIO_MASK_TXDAVLIE_Msk /*!< Data available in Tx FIFO interrupt Enable */
+#define SDIO_MASK_RXDAVLIE_Pos (21U)
+#define SDIO_MASK_RXDAVLIE_Msk (0x1U << SDIO_MASK_RXDAVLIE_Pos) /*!< 0x00200000 */
+#define SDIO_MASK_RXDAVLIE SDIO_MASK_RXDAVLIE_Msk /*!< Data available in Rx FIFO interrupt Enable */
+#define SDIO_MASK_SDIOITIE_Pos (22U)
+#define SDIO_MASK_SDIOITIE_Msk (0x1U << SDIO_MASK_SDIOITIE_Pos) /*!< 0x00400000 */
+#define SDIO_MASK_SDIOITIE SDIO_MASK_SDIOITIE_Msk /*!< SDIO Mode Interrupt Received interrupt Enable */
+#define SDIO_MASK_CEATAENDIE_Pos (23U)
+#define SDIO_MASK_CEATAENDIE_Msk (0x1U << SDIO_MASK_CEATAENDIE_Pos) /*!< 0x00800000 */
+#define SDIO_MASK_CEATAENDIE SDIO_MASK_CEATAENDIE_Msk /*!< CE-ATA command completion signal received Interrupt Enable */
+
+/***************** Bit definition for SDIO_FIFOCNT register *****************/
+#define SDIO_FIFOCNT_FIFOCOUNT_Pos (0U)
+#define SDIO_FIFOCNT_FIFOCOUNT_Msk (0xFFFFFFU << SDIO_FIFOCNT_FIFOCOUNT_Pos) /*!< 0x00FFFFFF */
+#define SDIO_FIFOCNT_FIFOCOUNT SDIO_FIFOCNT_FIFOCOUNT_Msk /*!< Remaining number of words to be written to or read from the FIFO */
+
+/****************** Bit definition for SDIO_FIFO register *******************/
+#define SDIO_FIFO_FIFODATA_Pos (0U)
+#define SDIO_FIFO_FIFODATA_Msk (0xFFFFFFFFU << SDIO_FIFO_FIFODATA_Pos) /*!< 0xFFFFFFFF */
+#define SDIO_FIFO_FIFODATA SDIO_FIFO_FIFODATA_Msk /*!< Receive and transmit FIFO data */
+
+
+
+/******************************************************************************/
+/* */
+/* Serial Peripheral Interface */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for SPI_CR1 register ********************/
+#define SPI_CR1_CPHA_Pos (0U)
+#define SPI_CR1_CPHA_Msk (0x1U << SPI_CR1_CPHA_Pos) /*!< 0x00000001 */
+#define SPI_CR1_CPHA SPI_CR1_CPHA_Msk /*!< Clock Phase */
+#define SPI_CR1_CPOL_Pos (1U)
+#define SPI_CR1_CPOL_Msk (0x1U << SPI_CR1_CPOL_Pos) /*!< 0x00000002 */
+#define SPI_CR1_CPOL SPI_CR1_CPOL_Msk /*!< Clock Polarity */
+#define SPI_CR1_MSTR_Pos (2U)
+#define SPI_CR1_MSTR_Msk (0x1U << SPI_CR1_MSTR_Pos) /*!< 0x00000004 */
+#define SPI_CR1_MSTR SPI_CR1_MSTR_Msk /*!< Master Selection */
+
+#define SPI_CR1_BR_Pos (3U)
+#define SPI_CR1_BR_Msk (0x7U << SPI_CR1_BR_Pos) /*!< 0x00000038 */
+#define SPI_CR1_BR SPI_CR1_BR_Msk /*!< BR[2:0] bits (Baud Rate Control) */
+#define SPI_CR1_BR_0 (0x1U << SPI_CR1_BR_Pos) /*!< 0x00000008 */
+#define SPI_CR1_BR_1 (0x2U << SPI_CR1_BR_Pos) /*!< 0x00000010 */
+#define SPI_CR1_BR_2 (0x4U << SPI_CR1_BR_Pos) /*!< 0x00000020 */
+
+#define SPI_CR1_SPE_Pos (6U)
+#define SPI_CR1_SPE_Msk (0x1U << SPI_CR1_SPE_Pos) /*!< 0x00000040 */
+#define SPI_CR1_SPE SPI_CR1_SPE_Msk /*!< SPI Enable */
+#define SPI_CR1_LSBFIRST_Pos (7U)
+#define SPI_CR1_LSBFIRST_Msk (0x1U << SPI_CR1_LSBFIRST_Pos) /*!< 0x00000080 */
+#define SPI_CR1_LSBFIRST SPI_CR1_LSBFIRST_Msk /*!< Frame Format */
+#define SPI_CR1_SSI_Pos (8U)
+#define SPI_CR1_SSI_Msk (0x1U << SPI_CR1_SSI_Pos) /*!< 0x00000100 */
+#define SPI_CR1_SSI SPI_CR1_SSI_Msk /*!< Internal slave select */
+#define SPI_CR1_SSM_Pos (9U)
+#define SPI_CR1_SSM_Msk (0x1U << SPI_CR1_SSM_Pos) /*!< 0x00000200 */
+#define SPI_CR1_SSM SPI_CR1_SSM_Msk /*!< Software slave management */
+#define SPI_CR1_RXONLY_Pos (10U)
+#define SPI_CR1_RXONLY_Msk (0x1U << SPI_CR1_RXONLY_Pos) /*!< 0x00000400 */
+#define SPI_CR1_RXONLY SPI_CR1_RXONLY_Msk /*!< Receive only */
+#define SPI_CR1_DFF_Pos (11U)
+#define SPI_CR1_DFF_Msk (0x1U << SPI_CR1_DFF_Pos) /*!< 0x00000800 */
+#define SPI_CR1_DFF SPI_CR1_DFF_Msk /*!< Data Frame Format */
+#define SPI_CR1_CRCNEXT_Pos (12U)
+#define SPI_CR1_CRCNEXT_Msk (0x1U << SPI_CR1_CRCNEXT_Pos) /*!< 0x00001000 */
+#define SPI_CR1_CRCNEXT SPI_CR1_CRCNEXT_Msk /*!< Transmit CRC next */
+#define SPI_CR1_CRCEN_Pos (13U)
+#define SPI_CR1_CRCEN_Msk (0x1U << SPI_CR1_CRCEN_Pos) /*!< 0x00002000 */
+#define SPI_CR1_CRCEN SPI_CR1_CRCEN_Msk /*!< Hardware CRC calculation enable */
+#define SPI_CR1_BIDIOE_Pos (14U)
+#define SPI_CR1_BIDIOE_Msk (0x1U << SPI_CR1_BIDIOE_Pos) /*!< 0x00004000 */
+#define SPI_CR1_BIDIOE SPI_CR1_BIDIOE_Msk /*!< Output enable in bidirectional mode */
+#define SPI_CR1_BIDIMODE_Pos (15U)
+#define SPI_CR1_BIDIMODE_Msk (0x1U << SPI_CR1_BIDIMODE_Pos) /*!< 0x00008000 */
+#define SPI_CR1_BIDIMODE SPI_CR1_BIDIMODE_Msk /*!< Bidirectional data mode enable */
+
+/******************* Bit definition for SPI_CR2 register ********************/
+#define SPI_CR2_RXDMAEN_Pos (0U)
+#define SPI_CR2_RXDMAEN_Msk (0x1U << SPI_CR2_RXDMAEN_Pos) /*!< 0x00000001 */
+#define SPI_CR2_RXDMAEN SPI_CR2_RXDMAEN_Msk /*!< Rx Buffer DMA Enable */
+#define SPI_CR2_TXDMAEN_Pos (1U)
+#define SPI_CR2_TXDMAEN_Msk (0x1U << SPI_CR2_TXDMAEN_Pos) /*!< 0x00000002 */
+#define SPI_CR2_TXDMAEN SPI_CR2_TXDMAEN_Msk /*!< Tx Buffer DMA Enable */
+#define SPI_CR2_SSOE_Pos (2U)
+#define SPI_CR2_SSOE_Msk (0x1U << SPI_CR2_SSOE_Pos) /*!< 0x00000004 */
+#define SPI_CR2_SSOE SPI_CR2_SSOE_Msk /*!< SS Output Enable */
+#define SPI_CR2_ERRIE_Pos (5U)
+#define SPI_CR2_ERRIE_Msk (0x1U << SPI_CR2_ERRIE_Pos) /*!< 0x00000020 */
+#define SPI_CR2_ERRIE SPI_CR2_ERRIE_Msk /*!< Error Interrupt Enable */
+#define SPI_CR2_RXNEIE_Pos (6U)
+#define SPI_CR2_RXNEIE_Msk (0x1U << SPI_CR2_RXNEIE_Pos) /*!< 0x00000040 */
+#define SPI_CR2_RXNEIE SPI_CR2_RXNEIE_Msk /*!< RX buffer Not Empty Interrupt Enable */
+#define SPI_CR2_TXEIE_Pos (7U)
+#define SPI_CR2_TXEIE_Msk (0x1U << SPI_CR2_TXEIE_Pos) /*!< 0x00000080 */
+#define SPI_CR2_TXEIE SPI_CR2_TXEIE_Msk /*!< Tx buffer Empty Interrupt Enable */
+
+/******************** Bit definition for SPI_SR register ********************/
+#define SPI_SR_RXNE_Pos (0U)
+#define SPI_SR_RXNE_Msk (0x1U << SPI_SR_RXNE_Pos) /*!< 0x00000001 */
+#define SPI_SR_RXNE SPI_SR_RXNE_Msk /*!< Receive buffer Not Empty */
+#define SPI_SR_TXE_Pos (1U)
+#define SPI_SR_TXE_Msk (0x1U << SPI_SR_TXE_Pos) /*!< 0x00000002 */
+#define SPI_SR_TXE SPI_SR_TXE_Msk /*!< Transmit buffer Empty */
+#define SPI_SR_CHSIDE_Pos (2U)
+#define SPI_SR_CHSIDE_Msk (0x1U << SPI_SR_CHSIDE_Pos) /*!< 0x00000004 */
+#define SPI_SR_CHSIDE SPI_SR_CHSIDE_Msk /*!< Channel side */
+#define SPI_SR_UDR_Pos (3U)
+#define SPI_SR_UDR_Msk (0x1U << SPI_SR_UDR_Pos) /*!< 0x00000008 */
+#define SPI_SR_UDR SPI_SR_UDR_Msk /*!< Underrun flag */
+#define SPI_SR_CRCERR_Pos (4U)
+#define SPI_SR_CRCERR_Msk (0x1U << SPI_SR_CRCERR_Pos) /*!< 0x00000010 */
+#define SPI_SR_CRCERR SPI_SR_CRCERR_Msk /*!< CRC Error flag */
+#define SPI_SR_MODF_Pos (5U)
+#define SPI_SR_MODF_Msk (0x1U << SPI_SR_MODF_Pos) /*!< 0x00000020 */
+#define SPI_SR_MODF SPI_SR_MODF_Msk /*!< Mode fault */
+#define SPI_SR_OVR_Pos (6U)
+#define SPI_SR_OVR_Msk (0x1U << SPI_SR_OVR_Pos) /*!< 0x00000040 */
+#define SPI_SR_OVR SPI_SR_OVR_Msk /*!< Overrun flag */
+#define SPI_SR_BSY_Pos (7U)
+#define SPI_SR_BSY_Msk (0x1U << SPI_SR_BSY_Pos) /*!< 0x00000080 */
+#define SPI_SR_BSY SPI_SR_BSY_Msk /*!< Busy flag */
+
+/******************** Bit definition for SPI_DR register ********************/
+#define SPI_DR_DR_Pos (0U)
+#define SPI_DR_DR_Msk (0xFFFFU << SPI_DR_DR_Pos) /*!< 0x0000FFFF */
+#define SPI_DR_DR SPI_DR_DR_Msk /*!< Data Register */
+
+/******************* Bit definition for SPI_CRCPR register ******************/
+#define SPI_CRCPR_CRCPOLY_Pos (0U)
+#define SPI_CRCPR_CRCPOLY_Msk (0xFFFFU << SPI_CRCPR_CRCPOLY_Pos) /*!< 0x0000FFFF */
+#define SPI_CRCPR_CRCPOLY SPI_CRCPR_CRCPOLY_Msk /*!< CRC polynomial register */
+
+/****************** Bit definition for SPI_RXCRCR register ******************/
+#define SPI_RXCRCR_RXCRC_Pos (0U)
+#define SPI_RXCRCR_RXCRC_Msk (0xFFFFU << SPI_RXCRCR_RXCRC_Pos) /*!< 0x0000FFFF */
+#define SPI_RXCRCR_RXCRC SPI_RXCRCR_RXCRC_Msk /*!< Rx CRC Register */
+
+/****************** Bit definition for SPI_TXCRCR register ******************/
+#define SPI_TXCRCR_TXCRC_Pos (0U)
+#define SPI_TXCRCR_TXCRC_Msk (0xFFFFU << SPI_TXCRCR_TXCRC_Pos) /*!< 0x0000FFFF */
+#define SPI_TXCRCR_TXCRC SPI_TXCRCR_TXCRC_Msk /*!< Tx CRC Register */
+
+/****************** Bit definition for SPI_I2SCFGR register *****************/
+#define SPI_I2SCFGR_I2SMOD_Pos (11U)
+#define SPI_I2SCFGR_I2SMOD_Msk (0x1U << SPI_I2SCFGR_I2SMOD_Pos) /*!< 0x00000800 */
+#define SPI_I2SCFGR_I2SMOD SPI_I2SCFGR_I2SMOD_Msk /*!< I2S mode selection */
+
+
+/******************************************************************************/
+/* */
+/* Inter-integrated Circuit Interface */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for I2C_CR1 register ********************/
+#define I2C_CR1_PE_Pos (0U)
+#define I2C_CR1_PE_Msk (0x1U << I2C_CR1_PE_Pos) /*!< 0x00000001 */
+#define I2C_CR1_PE I2C_CR1_PE_Msk /*!< Peripheral Enable */
+#define I2C_CR1_SMBUS_Pos (1U)
+#define I2C_CR1_SMBUS_Msk (0x1U << I2C_CR1_SMBUS_Pos) /*!< 0x00000002 */
+#define I2C_CR1_SMBUS I2C_CR1_SMBUS_Msk /*!< SMBus Mode */
+#define I2C_CR1_SMBTYPE_Pos (3U)
+#define I2C_CR1_SMBTYPE_Msk (0x1U << I2C_CR1_SMBTYPE_Pos) /*!< 0x00000008 */
+#define I2C_CR1_SMBTYPE I2C_CR1_SMBTYPE_Msk /*!< SMBus Type */
+#define I2C_CR1_ENARP_Pos (4U)
+#define I2C_CR1_ENARP_Msk (0x1U << I2C_CR1_ENARP_Pos) /*!< 0x00000010 */
+#define I2C_CR1_ENARP I2C_CR1_ENARP_Msk /*!< ARP Enable */
+#define I2C_CR1_ENPEC_Pos (5U)
+#define I2C_CR1_ENPEC_Msk (0x1U << I2C_CR1_ENPEC_Pos) /*!< 0x00000020 */
+#define I2C_CR1_ENPEC I2C_CR1_ENPEC_Msk /*!< PEC Enable */
+#define I2C_CR1_ENGC_Pos (6U)
+#define I2C_CR1_ENGC_Msk (0x1U << I2C_CR1_ENGC_Pos) /*!< 0x00000040 */
+#define I2C_CR1_ENGC I2C_CR1_ENGC_Msk /*!< General Call Enable */
+#define I2C_CR1_NOSTRETCH_Pos (7U)
+#define I2C_CR1_NOSTRETCH_Msk (0x1U << I2C_CR1_NOSTRETCH_Pos) /*!< 0x00000080 */
+#define I2C_CR1_NOSTRETCH I2C_CR1_NOSTRETCH_Msk /*!< Clock Stretching Disable (Slave mode) */
+#define I2C_CR1_START_Pos (8U)
+#define I2C_CR1_START_Msk (0x1U << I2C_CR1_START_Pos) /*!< 0x00000100 */
+#define I2C_CR1_START I2C_CR1_START_Msk /*!< Start Generation */
+#define I2C_CR1_STOP_Pos (9U)
+#define I2C_CR1_STOP_Msk (0x1U << I2C_CR1_STOP_Pos) /*!< 0x00000200 */
+#define I2C_CR1_STOP I2C_CR1_STOP_Msk /*!< Stop Generation */
+#define I2C_CR1_ACK_Pos (10U)
+#define I2C_CR1_ACK_Msk (0x1U << I2C_CR1_ACK_Pos) /*!< 0x00000400 */
+#define I2C_CR1_ACK I2C_CR1_ACK_Msk /*!< Acknowledge Enable */
+#define I2C_CR1_POS_Pos (11U)
+#define I2C_CR1_POS_Msk (0x1U << I2C_CR1_POS_Pos) /*!< 0x00000800 */
+#define I2C_CR1_POS I2C_CR1_POS_Msk /*!< Acknowledge/PEC Position (for data reception) */
+#define I2C_CR1_PEC_Pos (12U)
+#define I2C_CR1_PEC_Msk (0x1U << I2C_CR1_PEC_Pos) /*!< 0x00001000 */
+#define I2C_CR1_PEC I2C_CR1_PEC_Msk /*!< Packet Error Checking */
+#define I2C_CR1_ALERT_Pos (13U)
+#define I2C_CR1_ALERT_Msk (0x1U << I2C_CR1_ALERT_Pos) /*!< 0x00002000 */
+#define I2C_CR1_ALERT I2C_CR1_ALERT_Msk /*!< SMBus Alert */
+#define I2C_CR1_SWRST_Pos (15U)
+#define I2C_CR1_SWRST_Msk (0x1U << I2C_CR1_SWRST_Pos) /*!< 0x00008000 */
+#define I2C_CR1_SWRST I2C_CR1_SWRST_Msk /*!< Software Reset */
+
+/******************* Bit definition for I2C_CR2 register ********************/
+#define I2C_CR2_FREQ_Pos (0U)
+#define I2C_CR2_FREQ_Msk (0x3FU << I2C_CR2_FREQ_Pos) /*!< 0x0000003F */
+#define I2C_CR2_FREQ I2C_CR2_FREQ_Msk /*!< FREQ[5:0] bits (Peripheral Clock Frequency) */
+#define I2C_CR2_FREQ_0 (0x01U << I2C_CR2_FREQ_Pos) /*!< 0x00000001 */
+#define I2C_CR2_FREQ_1 (0x02U << I2C_CR2_FREQ_Pos) /*!< 0x00000002 */
+#define I2C_CR2_FREQ_2 (0x04U << I2C_CR2_FREQ_Pos) /*!< 0x00000004 */
+#define I2C_CR2_FREQ_3 (0x08U << I2C_CR2_FREQ_Pos) /*!< 0x00000008 */
+#define I2C_CR2_FREQ_4 (0x10U << I2C_CR2_FREQ_Pos) /*!< 0x00000010 */
+#define I2C_CR2_FREQ_5 (0x20U << I2C_CR2_FREQ_Pos) /*!< 0x00000020 */
+
+#define I2C_CR2_ITERREN_Pos (8U)
+#define I2C_CR2_ITERREN_Msk (0x1U << I2C_CR2_ITERREN_Pos) /*!< 0x00000100 */
+#define I2C_CR2_ITERREN I2C_CR2_ITERREN_Msk /*!< Error Interrupt Enable */
+#define I2C_CR2_ITEVTEN_Pos (9U)
+#define I2C_CR2_ITEVTEN_Msk (0x1U << I2C_CR2_ITEVTEN_Pos) /*!< 0x00000200 */
+#define I2C_CR2_ITEVTEN I2C_CR2_ITEVTEN_Msk /*!< Event Interrupt Enable */
+#define I2C_CR2_ITBUFEN_Pos (10U)
+#define I2C_CR2_ITBUFEN_Msk (0x1U << I2C_CR2_ITBUFEN_Pos) /*!< 0x00000400 */
+#define I2C_CR2_ITBUFEN I2C_CR2_ITBUFEN_Msk /*!< Buffer Interrupt Enable */
+#define I2C_CR2_DMAEN_Pos (11U)
+#define I2C_CR2_DMAEN_Msk (0x1U << I2C_CR2_DMAEN_Pos) /*!< 0x00000800 */
+#define I2C_CR2_DMAEN I2C_CR2_DMAEN_Msk /*!< DMA Requests Enable */
+#define I2C_CR2_LAST_Pos (12U)
+#define I2C_CR2_LAST_Msk (0x1U << I2C_CR2_LAST_Pos) /*!< 0x00001000 */
+#define I2C_CR2_LAST I2C_CR2_LAST_Msk /*!< DMA Last Transfer */
+
+/******************* Bit definition for I2C_OAR1 register *******************/
+#define I2C_OAR1_ADD1_7 ((uint32_t)0x000000FE) /*!< Interface Address */
+#define I2C_OAR1_ADD8_9 ((uint32_t)0x00000300) /*!< Interface Address */
+
+#define I2C_OAR1_ADD0_Pos (0U)
+#define I2C_OAR1_ADD0_Msk (0x1U << I2C_OAR1_ADD0_Pos) /*!< 0x00000001 */
+#define I2C_OAR1_ADD0 I2C_OAR1_ADD0_Msk /*!< Bit 0 */
+#define I2C_OAR1_ADD1_Pos (1U)
+#define I2C_OAR1_ADD1_Msk (0x1U << I2C_OAR1_ADD1_Pos) /*!< 0x00000002 */
+#define I2C_OAR1_ADD1 I2C_OAR1_ADD1_Msk /*!< Bit 1 */
+#define I2C_OAR1_ADD2_Pos (2U)
+#define I2C_OAR1_ADD2_Msk (0x1U << I2C_OAR1_ADD2_Pos) /*!< 0x00000004 */
+#define I2C_OAR1_ADD2 I2C_OAR1_ADD2_Msk /*!< Bit 2 */
+#define I2C_OAR1_ADD3_Pos (3U)
+#define I2C_OAR1_ADD3_Msk (0x1U << I2C_OAR1_ADD3_Pos) /*!< 0x00000008 */
+#define I2C_OAR1_ADD3 I2C_OAR1_ADD3_Msk /*!< Bit 3 */
+#define I2C_OAR1_ADD4_Pos (4U)
+#define I2C_OAR1_ADD4_Msk (0x1U << I2C_OAR1_ADD4_Pos) /*!< 0x00000010 */
+#define I2C_OAR1_ADD4 I2C_OAR1_ADD4_Msk /*!< Bit 4 */
+#define I2C_OAR1_ADD5_Pos (5U)
+#define I2C_OAR1_ADD5_Msk (0x1U << I2C_OAR1_ADD5_Pos) /*!< 0x00000020 */
+#define I2C_OAR1_ADD5 I2C_OAR1_ADD5_Msk /*!< Bit 5 */
+#define I2C_OAR1_ADD6_Pos (6U)
+#define I2C_OAR1_ADD6_Msk (0x1U << I2C_OAR1_ADD6_Pos) /*!< 0x00000040 */
+#define I2C_OAR1_ADD6 I2C_OAR1_ADD6_Msk /*!< Bit 6 */
+#define I2C_OAR1_ADD7_Pos (7U)
+#define I2C_OAR1_ADD7_Msk (0x1U << I2C_OAR1_ADD7_Pos) /*!< 0x00000080 */
+#define I2C_OAR1_ADD7 I2C_OAR1_ADD7_Msk /*!< Bit 7 */
+#define I2C_OAR1_ADD8_Pos (8U)
+#define I2C_OAR1_ADD8_Msk (0x1U << I2C_OAR1_ADD8_Pos) /*!< 0x00000100 */
+#define I2C_OAR1_ADD8 I2C_OAR1_ADD8_Msk /*!< Bit 8 */
+#define I2C_OAR1_ADD9_Pos (9U)
+#define I2C_OAR1_ADD9_Msk (0x1U << I2C_OAR1_ADD9_Pos) /*!< 0x00000200 */
+#define I2C_OAR1_ADD9 I2C_OAR1_ADD9_Msk /*!< Bit 9 */
+
+#define I2C_OAR1_ADDMODE_Pos (15U)
+#define I2C_OAR1_ADDMODE_Msk (0x1U << I2C_OAR1_ADDMODE_Pos) /*!< 0x00008000 */
+#define I2C_OAR1_ADDMODE I2C_OAR1_ADDMODE_Msk /*!< Addressing Mode (Slave mode) */
+
+/******************* Bit definition for I2C_OAR2 register *******************/
+#define I2C_OAR2_ENDUAL_Pos (0U)
+#define I2C_OAR2_ENDUAL_Msk (0x1U << I2C_OAR2_ENDUAL_Pos) /*!< 0x00000001 */
+#define I2C_OAR2_ENDUAL I2C_OAR2_ENDUAL_Msk /*!< Dual addressing mode enable */
+#define I2C_OAR2_ADD2_Pos (1U)
+#define I2C_OAR2_ADD2_Msk (0x7FU << I2C_OAR2_ADD2_Pos) /*!< 0x000000FE */
+#define I2C_OAR2_ADD2 I2C_OAR2_ADD2_Msk /*!< Interface address */
+
+/******************* Bit definition for I2C_SR1 register ********************/
+#define I2C_SR1_SB_Pos (0U)
+#define I2C_SR1_SB_Msk (0x1U << I2C_SR1_SB_Pos) /*!< 0x00000001 */
+#define I2C_SR1_SB I2C_SR1_SB_Msk /*!< Start Bit (Master mode) */
+#define I2C_SR1_ADDR_Pos (1U)
+#define I2C_SR1_ADDR_Msk (0x1U << I2C_SR1_ADDR_Pos) /*!< 0x00000002 */
+#define I2C_SR1_ADDR I2C_SR1_ADDR_Msk /*!< Address sent (master mode)/matched (slave mode) */
+#define I2C_SR1_BTF_Pos (2U)
+#define I2C_SR1_BTF_Msk (0x1U << I2C_SR1_BTF_Pos) /*!< 0x00000004 */
+#define I2C_SR1_BTF I2C_SR1_BTF_Msk /*!< Byte Transfer Finished */
+#define I2C_SR1_ADD10_Pos (3U)
+#define I2C_SR1_ADD10_Msk (0x1U << I2C_SR1_ADD10_Pos) /*!< 0x00000008 */
+#define I2C_SR1_ADD10 I2C_SR1_ADD10_Msk /*!< 10-bit header sent (Master mode) */
+#define I2C_SR1_STOPF_Pos (4U)
+#define I2C_SR1_STOPF_Msk (0x1U << I2C_SR1_STOPF_Pos) /*!< 0x00000010 */
+#define I2C_SR1_STOPF I2C_SR1_STOPF_Msk /*!< Stop detection (Slave mode) */
+#define I2C_SR1_RXNE_Pos (6U)
+#define I2C_SR1_RXNE_Msk (0x1U << I2C_SR1_RXNE_Pos) /*!< 0x00000040 */
+#define I2C_SR1_RXNE I2C_SR1_RXNE_Msk /*!< Data Register not Empty (receivers) */
+#define I2C_SR1_TXE_Pos (7U)
+#define I2C_SR1_TXE_Msk (0x1U << I2C_SR1_TXE_Pos) /*!< 0x00000080 */
+#define I2C_SR1_TXE I2C_SR1_TXE_Msk /*!< Data Register Empty (transmitters) */
+#define I2C_SR1_BERR_Pos (8U)
+#define I2C_SR1_BERR_Msk (0x1U << I2C_SR1_BERR_Pos) /*!< 0x00000100 */
+#define I2C_SR1_BERR I2C_SR1_BERR_Msk /*!< Bus Error */
+#define I2C_SR1_ARLO_Pos (9U)
+#define I2C_SR1_ARLO_Msk (0x1U << I2C_SR1_ARLO_Pos) /*!< 0x00000200 */
+#define I2C_SR1_ARLO I2C_SR1_ARLO_Msk /*!< Arbitration Lost (master mode) */
+#define I2C_SR1_AF_Pos (10U)
+#define I2C_SR1_AF_Msk (0x1U << I2C_SR1_AF_Pos) /*!< 0x00000400 */
+#define I2C_SR1_AF I2C_SR1_AF_Msk /*!< Acknowledge Failure */
+#define I2C_SR1_OVR_Pos (11U)
+#define I2C_SR1_OVR_Msk (0x1U << I2C_SR1_OVR_Pos) /*!< 0x00000800 */
+#define I2C_SR1_OVR I2C_SR1_OVR_Msk /*!< Overrun/Underrun */
+#define I2C_SR1_PECERR_Pos (12U)
+#define I2C_SR1_PECERR_Msk (0x1U << I2C_SR1_PECERR_Pos) /*!< 0x00001000 */
+#define I2C_SR1_PECERR I2C_SR1_PECERR_Msk /*!< PEC Error in reception */
+#define I2C_SR1_TIMEOUT_Pos (14U)
+#define I2C_SR1_TIMEOUT_Msk (0x1U << I2C_SR1_TIMEOUT_Pos) /*!< 0x00004000 */
+#define I2C_SR1_TIMEOUT I2C_SR1_TIMEOUT_Msk /*!< Timeout or Tlow Error */
+#define I2C_SR1_SMBALERT_Pos (15U)
+#define I2C_SR1_SMBALERT_Msk (0x1U << I2C_SR1_SMBALERT_Pos) /*!< 0x00008000 */
+#define I2C_SR1_SMBALERT I2C_SR1_SMBALERT_Msk /*!< SMBus Alert */
+
+/******************* Bit definition for I2C_SR2 register ********************/
+#define I2C_SR2_MSL_Pos (0U)
+#define I2C_SR2_MSL_Msk (0x1U << I2C_SR2_MSL_Pos) /*!< 0x00000001 */
+#define I2C_SR2_MSL I2C_SR2_MSL_Msk /*!< Master/Slave */
+#define I2C_SR2_BUSY_Pos (1U)
+#define I2C_SR2_BUSY_Msk (0x1U << I2C_SR2_BUSY_Pos) /*!< 0x00000002 */
+#define I2C_SR2_BUSY I2C_SR2_BUSY_Msk /*!< Bus Busy */
+#define I2C_SR2_TRA_Pos (2U)
+#define I2C_SR2_TRA_Msk (0x1U << I2C_SR2_TRA_Pos) /*!< 0x00000004 */
+#define I2C_SR2_TRA I2C_SR2_TRA_Msk /*!< Transmitter/Receiver */
+#define I2C_SR2_GENCALL_Pos (4U)
+#define I2C_SR2_GENCALL_Msk (0x1U << I2C_SR2_GENCALL_Pos) /*!< 0x00000010 */
+#define I2C_SR2_GENCALL I2C_SR2_GENCALL_Msk /*!< General Call Address (Slave mode) */
+#define I2C_SR2_SMBDEFAULT_Pos (5U)
+#define I2C_SR2_SMBDEFAULT_Msk (0x1U << I2C_SR2_SMBDEFAULT_Pos) /*!< 0x00000020 */
+#define I2C_SR2_SMBDEFAULT I2C_SR2_SMBDEFAULT_Msk /*!< SMBus Device Default Address (Slave mode) */
+#define I2C_SR2_SMBHOST_Pos (6U)
+#define I2C_SR2_SMBHOST_Msk (0x1U << I2C_SR2_SMBHOST_Pos) /*!< 0x00000040 */
+#define I2C_SR2_SMBHOST I2C_SR2_SMBHOST_Msk /*!< SMBus Host Header (Slave mode) */
+#define I2C_SR2_DUALF_Pos (7U)
+#define I2C_SR2_DUALF_Msk (0x1U << I2C_SR2_DUALF_Pos) /*!< 0x00000080 */
+#define I2C_SR2_DUALF I2C_SR2_DUALF_Msk /*!< Dual Flag (Slave mode) */
+#define I2C_SR2_PEC_Pos (8U)
+#define I2C_SR2_PEC_Msk (0xFFU << I2C_SR2_PEC_Pos) /*!< 0x0000FF00 */
+#define I2C_SR2_PEC I2C_SR2_PEC_Msk /*!< Packet Error Checking Register */
+
+/******************* Bit definition for I2C_CCR register ********************/
+#define I2C_CCR_CCR_Pos (0U)
+#define I2C_CCR_CCR_Msk (0xFFFU << I2C_CCR_CCR_Pos) /*!< 0x00000FFF */
+#define I2C_CCR_CCR I2C_CCR_CCR_Msk /*!< Clock Control Register in Fast/Standard mode (Master mode) */
+#define I2C_CCR_DUTY_Pos (14U)
+#define I2C_CCR_DUTY_Msk (0x1U << I2C_CCR_DUTY_Pos) /*!< 0x00004000 */
+#define I2C_CCR_DUTY I2C_CCR_DUTY_Msk /*!< Fast Mode Duty Cycle */
+#define I2C_CCR_FS_Pos (15U)
+#define I2C_CCR_FS_Msk (0x1U << I2C_CCR_FS_Pos) /*!< 0x00008000 */
+#define I2C_CCR_FS I2C_CCR_FS_Msk /*!< I2C Master Mode Selection */
+
+/****************** Bit definition for I2C_TRISE register *******************/
+#define I2C_TRISE_TRISE_Pos (0U)
+#define I2C_TRISE_TRISE_Msk (0x3FU << I2C_TRISE_TRISE_Pos) /*!< 0x0000003F */
+#define I2C_TRISE_TRISE I2C_TRISE_TRISE_Msk /*!< Maximum Rise Time in Fast/Standard mode (Master mode) */
+
+/******************************************************************************/
+/* */
+/* Universal Synchronous Asynchronous Receiver Transmitter */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for USART_SR register *******************/
+#define USART_SR_PE_Pos (0U)
+#define USART_SR_PE_Msk (0x1U << USART_SR_PE_Pos) /*!< 0x00000001 */
+#define USART_SR_PE USART_SR_PE_Msk /*!< Parity Error */
+#define USART_SR_FE_Pos (1U)
+#define USART_SR_FE_Msk (0x1U << USART_SR_FE_Pos) /*!< 0x00000002 */
+#define USART_SR_FE USART_SR_FE_Msk /*!< Framing Error */
+#define USART_SR_NE_Pos (2U)
+#define USART_SR_NE_Msk (0x1U << USART_SR_NE_Pos) /*!< 0x00000004 */
+#define USART_SR_NE USART_SR_NE_Msk /*!< Noise Error Flag */
+#define USART_SR_ORE_Pos (3U)
+#define USART_SR_ORE_Msk (0x1U << USART_SR_ORE_Pos) /*!< 0x00000008 */
+#define USART_SR_ORE USART_SR_ORE_Msk /*!< OverRun Error */
+#define USART_SR_IDLE_Pos (4U)
+#define USART_SR_IDLE_Msk (0x1U << USART_SR_IDLE_Pos) /*!< 0x00000010 */
+#define USART_SR_IDLE USART_SR_IDLE_Msk /*!< IDLE line detected */
+#define USART_SR_RXNE_Pos (5U)
+#define USART_SR_RXNE_Msk (0x1U << USART_SR_RXNE_Pos) /*!< 0x00000020 */
+#define USART_SR_RXNE USART_SR_RXNE_Msk /*!< Read Data Register Not Empty */
+#define USART_SR_TC_Pos (6U)
+#define USART_SR_TC_Msk (0x1U << USART_SR_TC_Pos) /*!< 0x00000040 */
+#define USART_SR_TC USART_SR_TC_Msk /*!< Transmission Complete */
+#define USART_SR_TXE_Pos (7U)
+#define USART_SR_TXE_Msk (0x1U << USART_SR_TXE_Pos) /*!< 0x00000080 */
+#define USART_SR_TXE USART_SR_TXE_Msk /*!< Transmit Data Register Empty */
+#define USART_SR_LBD_Pos (8U)
+#define USART_SR_LBD_Msk (0x1U << USART_SR_LBD_Pos) /*!< 0x00000100 */
+#define USART_SR_LBD USART_SR_LBD_Msk /*!< LIN Break Detection Flag */
+#define USART_SR_CTS_Pos (9U)
+#define USART_SR_CTS_Msk (0x1U << USART_SR_CTS_Pos) /*!< 0x00000200 */
+#define USART_SR_CTS USART_SR_CTS_Msk /*!< CTS Flag */
+
+/******************* Bit definition for USART_DR register *******************/
+#define USART_DR_DR_Pos (0U)
+#define USART_DR_DR_Msk (0x1FFU << USART_DR_DR_Pos) /*!< 0x000001FF */
+#define USART_DR_DR USART_DR_DR_Msk /*!< Data value */
+
+/****************** Bit definition for USART_BRR register *******************/
+#define USART_BRR_DIV_Fraction_Pos (0U)
+#define USART_BRR_DIV_Fraction_Msk (0xFU << USART_BRR_DIV_Fraction_Pos) /*!< 0x0000000F */
+#define USART_BRR_DIV_Fraction USART_BRR_DIV_Fraction_Msk /*!< Fraction of USARTDIV */
+#define USART_BRR_DIV_Mantissa_Pos (4U)
+#define USART_BRR_DIV_Mantissa_Msk (0xFFFU << USART_BRR_DIV_Mantissa_Pos) /*!< 0x0000FFF0 */
+#define USART_BRR_DIV_Mantissa USART_BRR_DIV_Mantissa_Msk /*!< Mantissa of USARTDIV */
+
+/****************** Bit definition for USART_CR1 register *******************/
+#define USART_CR1_SBK_Pos (0U)
+#define USART_CR1_SBK_Msk (0x1U << USART_CR1_SBK_Pos) /*!< 0x00000001 */
+#define USART_CR1_SBK USART_CR1_SBK_Msk /*!< Send Break */
+#define USART_CR1_RWU_Pos (1U)
+#define USART_CR1_RWU_Msk (0x1U << USART_CR1_RWU_Pos) /*!< 0x00000002 */
+#define USART_CR1_RWU USART_CR1_RWU_Msk /*!< Receiver wakeup */
+#define USART_CR1_RE_Pos (2U)
+#define USART_CR1_RE_Msk (0x1U << USART_CR1_RE_Pos) /*!< 0x00000004 */
+#define USART_CR1_RE USART_CR1_RE_Msk /*!< Receiver Enable */
+#define USART_CR1_TE_Pos (3U)
+#define USART_CR1_TE_Msk (0x1U << USART_CR1_TE_Pos) /*!< 0x00000008 */
+#define USART_CR1_TE USART_CR1_TE_Msk /*!< Transmitter Enable */
+#define USART_CR1_IDLEIE_Pos (4U)
+#define USART_CR1_IDLEIE_Msk (0x1U << USART_CR1_IDLEIE_Pos) /*!< 0x00000010 */
+#define USART_CR1_IDLEIE USART_CR1_IDLEIE_Msk /*!< IDLE Interrupt Enable */
+#define USART_CR1_RXNEIE_Pos (5U)
+#define USART_CR1_RXNEIE_Msk (0x1U << USART_CR1_RXNEIE_Pos) /*!< 0x00000020 */
+#define USART_CR1_RXNEIE USART_CR1_RXNEIE_Msk /*!< RXNE Interrupt Enable */
+#define USART_CR1_TCIE_Pos (6U)
+#define USART_CR1_TCIE_Msk (0x1U << USART_CR1_TCIE_Pos) /*!< 0x00000040 */
+#define USART_CR1_TCIE USART_CR1_TCIE_Msk /*!< Transmission Complete Interrupt Enable */
+#define USART_CR1_TXEIE_Pos (7U)
+#define USART_CR1_TXEIE_Msk (0x1U << USART_CR1_TXEIE_Pos) /*!< 0x00000080 */
+#define USART_CR1_TXEIE USART_CR1_TXEIE_Msk /*!< PE Interrupt Enable */
+#define USART_CR1_PEIE_Pos (8U)
+#define USART_CR1_PEIE_Msk (0x1U << USART_CR1_PEIE_Pos) /*!< 0x00000100 */
+#define USART_CR1_PEIE USART_CR1_PEIE_Msk /*!< PE Interrupt Enable */
+#define USART_CR1_PS_Pos (9U)
+#define USART_CR1_PS_Msk (0x1U << USART_CR1_PS_Pos) /*!< 0x00000200 */
+#define USART_CR1_PS USART_CR1_PS_Msk /*!< Parity Selection */
+#define USART_CR1_PCE_Pos (10U)
+#define USART_CR1_PCE_Msk (0x1U << USART_CR1_PCE_Pos) /*!< 0x00000400 */
+#define USART_CR1_PCE USART_CR1_PCE_Msk /*!< Parity Control Enable */
+#define USART_CR1_WAKE_Pos (11U)
+#define USART_CR1_WAKE_Msk (0x1U << USART_CR1_WAKE_Pos) /*!< 0x00000800 */
+#define USART_CR1_WAKE USART_CR1_WAKE_Msk /*!< Wakeup method */
+#define USART_CR1_M_Pos (12U)
+#define USART_CR1_M_Msk (0x1U << USART_CR1_M_Pos) /*!< 0x00001000 */
+#define USART_CR1_M USART_CR1_M_Msk /*!< Word length */
+#define USART_CR1_UE_Pos (13U)
+#define USART_CR1_UE_Msk (0x1U << USART_CR1_UE_Pos) /*!< 0x00002000 */
+#define USART_CR1_UE USART_CR1_UE_Msk /*!< USART Enable */
+
+/****************** Bit definition for USART_CR2 register *******************/
+#define USART_CR2_ADD_Pos (0U)
+#define USART_CR2_ADD_Msk (0xFU << USART_CR2_ADD_Pos) /*!< 0x0000000F */
+#define USART_CR2_ADD USART_CR2_ADD_Msk /*!< Address of the USART node */
+#define USART_CR2_LBDL_Pos (5U)
+#define USART_CR2_LBDL_Msk (0x1U << USART_CR2_LBDL_Pos) /*!< 0x00000020 */
+#define USART_CR2_LBDL USART_CR2_LBDL_Msk /*!< LIN Break Detection Length */
+#define USART_CR2_LBDIE_Pos (6U)
+#define USART_CR2_LBDIE_Msk (0x1U << USART_CR2_LBDIE_Pos) /*!< 0x00000040 */
+#define USART_CR2_LBDIE USART_CR2_LBDIE_Msk /*!< LIN Break Detection Interrupt Enable */
+#define USART_CR2_LBCL_Pos (8U)
+#define USART_CR2_LBCL_Msk (0x1U << USART_CR2_LBCL_Pos) /*!< 0x00000100 */
+#define USART_CR2_LBCL USART_CR2_LBCL_Msk /*!< Last Bit Clock pulse */
+#define USART_CR2_CPHA_Pos (9U)
+#define USART_CR2_CPHA_Msk (0x1U << USART_CR2_CPHA_Pos) /*!< 0x00000200 */
+#define USART_CR2_CPHA USART_CR2_CPHA_Msk /*!< Clock Phase */
+#define USART_CR2_CPOL_Pos (10U)
+#define USART_CR2_CPOL_Msk (0x1U << USART_CR2_CPOL_Pos) /*!< 0x00000400 */
+#define USART_CR2_CPOL USART_CR2_CPOL_Msk /*!< Clock Polarity */
+#define USART_CR2_CLKEN_Pos (11U)
+#define USART_CR2_CLKEN_Msk (0x1U << USART_CR2_CLKEN_Pos) /*!< 0x00000800 */
+#define USART_CR2_CLKEN USART_CR2_CLKEN_Msk /*!< Clock Enable */
+
+#define USART_CR2_STOP_Pos (12U)
+#define USART_CR2_STOP_Msk (0x3U << USART_CR2_STOP_Pos) /*!< 0x00003000 */
+#define USART_CR2_STOP USART_CR2_STOP_Msk /*!< STOP[1:0] bits (STOP bits) */
+#define USART_CR2_STOP_0 (0x1U << USART_CR2_STOP_Pos) /*!< 0x00001000 */
+#define USART_CR2_STOP_1 (0x2U << USART_CR2_STOP_Pos) /*!< 0x00002000 */
+
+#define USART_CR2_LINEN_Pos (14U)
+#define USART_CR2_LINEN_Msk (0x1U << USART_CR2_LINEN_Pos) /*!< 0x00004000 */
+#define USART_CR2_LINEN USART_CR2_LINEN_Msk /*!< LIN mode enable */
+
+/****************** Bit definition for USART_CR3 register *******************/
+#define USART_CR3_EIE_Pos (0U)
+#define USART_CR3_EIE_Msk (0x1U << USART_CR3_EIE_Pos) /*!< 0x00000001 */
+#define USART_CR3_EIE USART_CR3_EIE_Msk /*!< Error Interrupt Enable */
+#define USART_CR3_IREN_Pos (1U)
+#define USART_CR3_IREN_Msk (0x1U << USART_CR3_IREN_Pos) /*!< 0x00000002 */
+#define USART_CR3_IREN USART_CR3_IREN_Msk /*!< IrDA mode Enable */
+#define USART_CR3_IRLP_Pos (2U)
+#define USART_CR3_IRLP_Msk (0x1U << USART_CR3_IRLP_Pos) /*!< 0x00000004 */
+#define USART_CR3_IRLP USART_CR3_IRLP_Msk /*!< IrDA Low-Power */
+#define USART_CR3_HDSEL_Pos (3U)
+#define USART_CR3_HDSEL_Msk (0x1U << USART_CR3_HDSEL_Pos) /*!< 0x00000008 */
+#define USART_CR3_HDSEL USART_CR3_HDSEL_Msk /*!< Half-Duplex Selection */
+#define USART_CR3_NACK_Pos (4U)
+#define USART_CR3_NACK_Msk (0x1U << USART_CR3_NACK_Pos) /*!< 0x00000010 */
+#define USART_CR3_NACK USART_CR3_NACK_Msk /*!< Smartcard NACK enable */
+#define USART_CR3_SCEN_Pos (5U)
+#define USART_CR3_SCEN_Msk (0x1U << USART_CR3_SCEN_Pos) /*!< 0x00000020 */
+#define USART_CR3_SCEN USART_CR3_SCEN_Msk /*!< Smartcard mode enable */
+#define USART_CR3_DMAR_Pos (6U)
+#define USART_CR3_DMAR_Msk (0x1U << USART_CR3_DMAR_Pos) /*!< 0x00000040 */
+#define USART_CR3_DMAR USART_CR3_DMAR_Msk /*!< DMA Enable Receiver */
+#define USART_CR3_DMAT_Pos (7U)
+#define USART_CR3_DMAT_Msk (0x1U << USART_CR3_DMAT_Pos) /*!< 0x00000080 */
+#define USART_CR3_DMAT USART_CR3_DMAT_Msk /*!< DMA Enable Transmitter */
+#define USART_CR3_RTSE_Pos (8U)
+#define USART_CR3_RTSE_Msk (0x1U << USART_CR3_RTSE_Pos) /*!< 0x00000100 */
+#define USART_CR3_RTSE USART_CR3_RTSE_Msk /*!< RTS Enable */
+#define USART_CR3_CTSE_Pos (9U)
+#define USART_CR3_CTSE_Msk (0x1U << USART_CR3_CTSE_Pos) /*!< 0x00000200 */
+#define USART_CR3_CTSE USART_CR3_CTSE_Msk /*!< CTS Enable */
+#define USART_CR3_CTSIE_Pos (10U)
+#define USART_CR3_CTSIE_Msk (0x1U << USART_CR3_CTSIE_Pos) /*!< 0x00000400 */
+#define USART_CR3_CTSIE USART_CR3_CTSIE_Msk /*!< CTS Interrupt Enable */
+
+/****************** Bit definition for USART_GTPR register ******************/
+#define USART_GTPR_PSC_Pos (0U)
+#define USART_GTPR_PSC_Msk (0xFFU << USART_GTPR_PSC_Pos) /*!< 0x000000FF */
+#define USART_GTPR_PSC USART_GTPR_PSC_Msk /*!< PSC[7:0] bits (Prescaler value) */
+#define USART_GTPR_PSC_0 (0x01U << USART_GTPR_PSC_Pos) /*!< 0x00000001 */
+#define USART_GTPR_PSC_1 (0x02U << USART_GTPR_PSC_Pos) /*!< 0x00000002 */
+#define USART_GTPR_PSC_2 (0x04U << USART_GTPR_PSC_Pos) /*!< 0x00000004 */
+#define USART_GTPR_PSC_3 (0x08U << USART_GTPR_PSC_Pos) /*!< 0x00000008 */
+#define USART_GTPR_PSC_4 (0x10U << USART_GTPR_PSC_Pos) /*!< 0x00000010 */
+#define USART_GTPR_PSC_5 (0x20U << USART_GTPR_PSC_Pos) /*!< 0x00000020 */
+#define USART_GTPR_PSC_6 (0x40U << USART_GTPR_PSC_Pos) /*!< 0x00000040 */
+#define USART_GTPR_PSC_7 (0x80U << USART_GTPR_PSC_Pos) /*!< 0x00000080 */
+
+#define USART_GTPR_GT_Pos (8U)
+#define USART_GTPR_GT_Msk (0xFFU << USART_GTPR_GT_Pos) /*!< 0x0000FF00 */
+#define USART_GTPR_GT USART_GTPR_GT_Msk /*!< Guard time value */
+
+/******************************************************************************/
+/* */
+/* Debug MCU */
+/* */
+/******************************************************************************/
+
+/**************** Bit definition for DBGMCU_IDCODE register *****************/
+#define DBGMCU_IDCODE_DEV_ID_Pos (0U)
+#define DBGMCU_IDCODE_DEV_ID_Msk (0xFFFU << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */
+#define DBGMCU_IDCODE_DEV_ID DBGMCU_IDCODE_DEV_ID_Msk /*!< Device Identifier */
+
+#define DBGMCU_IDCODE_REV_ID_Pos (16U)
+#define DBGMCU_IDCODE_REV_ID_Msk (0xFFFFU << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */
+#define DBGMCU_IDCODE_REV_ID DBGMCU_IDCODE_REV_ID_Msk /*!< REV_ID[15:0] bits (Revision Identifier) */
+#define DBGMCU_IDCODE_REV_ID_0 (0x0001U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00010000 */
+#define DBGMCU_IDCODE_REV_ID_1 (0x0002U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00020000 */
+#define DBGMCU_IDCODE_REV_ID_2 (0x0004U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00040000 */
+#define DBGMCU_IDCODE_REV_ID_3 (0x0008U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00080000 */
+#define DBGMCU_IDCODE_REV_ID_4 (0x0010U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00100000 */
+#define DBGMCU_IDCODE_REV_ID_5 (0x0020U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00200000 */
+#define DBGMCU_IDCODE_REV_ID_6 (0x0040U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00400000 */
+#define DBGMCU_IDCODE_REV_ID_7 (0x0080U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00800000 */
+#define DBGMCU_IDCODE_REV_ID_8 (0x0100U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x01000000 */
+#define DBGMCU_IDCODE_REV_ID_9 (0x0200U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x02000000 */
+#define DBGMCU_IDCODE_REV_ID_10 (0x0400U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x04000000 */
+#define DBGMCU_IDCODE_REV_ID_11 (0x0800U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x08000000 */
+#define DBGMCU_IDCODE_REV_ID_12 (0x1000U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x10000000 */
+#define DBGMCU_IDCODE_REV_ID_13 (0x2000U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x20000000 */
+#define DBGMCU_IDCODE_REV_ID_14 (0x4000U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x40000000 */
+#define DBGMCU_IDCODE_REV_ID_15 (0x8000U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x80000000 */
+
+/****************** Bit definition for DBGMCU_CR register *******************/
+#define DBGMCU_CR_DBG_SLEEP_Pos (0U)
+#define DBGMCU_CR_DBG_SLEEP_Msk (0x1U << DBGMCU_CR_DBG_SLEEP_Pos) /*!< 0x00000001 */
+#define DBGMCU_CR_DBG_SLEEP DBGMCU_CR_DBG_SLEEP_Msk /*!< Debug Sleep Mode */
+#define DBGMCU_CR_DBG_STOP_Pos (1U)
+#define DBGMCU_CR_DBG_STOP_Msk (0x1U << DBGMCU_CR_DBG_STOP_Pos) /*!< 0x00000002 */
+#define DBGMCU_CR_DBG_STOP DBGMCU_CR_DBG_STOP_Msk /*!< Debug Stop Mode */
+#define DBGMCU_CR_DBG_STANDBY_Pos (2U)
+#define DBGMCU_CR_DBG_STANDBY_Msk (0x1U << DBGMCU_CR_DBG_STANDBY_Pos) /*!< 0x00000004 */
+#define DBGMCU_CR_DBG_STANDBY DBGMCU_CR_DBG_STANDBY_Msk /*!< Debug Standby mode */
+#define DBGMCU_CR_TRACE_IOEN_Pos (5U)
+#define DBGMCU_CR_TRACE_IOEN_Msk (0x1U << DBGMCU_CR_TRACE_IOEN_Pos) /*!< 0x00000020 */
+#define DBGMCU_CR_TRACE_IOEN DBGMCU_CR_TRACE_IOEN_Msk /*!< Trace Pin Assignment Control */
+
+#define DBGMCU_CR_TRACE_MODE_Pos (6U)
+#define DBGMCU_CR_TRACE_MODE_Msk (0x3U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x000000C0 */
+#define DBGMCU_CR_TRACE_MODE DBGMCU_CR_TRACE_MODE_Msk /*!< TRACE_MODE[1:0] bits (Trace Pin Assignment Control) */
+#define DBGMCU_CR_TRACE_MODE_0 (0x1U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000040 */
+#define DBGMCU_CR_TRACE_MODE_1 (0x2U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000080 */
+
+#define DBGMCU_CR_DBG_IWDG_STOP_Pos (8U)
+#define DBGMCU_CR_DBG_IWDG_STOP_Msk (0x1U << DBGMCU_CR_DBG_IWDG_STOP_Pos) /*!< 0x00000100 */
+#define DBGMCU_CR_DBG_IWDG_STOP DBGMCU_CR_DBG_IWDG_STOP_Msk /*!< Debug Independent Watchdog stopped when Core is halted */
+#define DBGMCU_CR_DBG_WWDG_STOP_Pos (9U)
+#define DBGMCU_CR_DBG_WWDG_STOP_Msk (0x1U << DBGMCU_CR_DBG_WWDG_STOP_Pos) /*!< 0x00000200 */
+#define DBGMCU_CR_DBG_WWDG_STOP DBGMCU_CR_DBG_WWDG_STOP_Msk /*!< Debug Window Watchdog stopped when Core is halted */
+#define DBGMCU_CR_DBG_TIM1_STOP_Pos (10U)
+#define DBGMCU_CR_DBG_TIM1_STOP_Msk (0x1U << DBGMCU_CR_DBG_TIM1_STOP_Pos) /*!< 0x00000400 */
+#define DBGMCU_CR_DBG_TIM1_STOP DBGMCU_CR_DBG_TIM1_STOP_Msk /*!< TIM1 counter stopped when core is halted */
+#define DBGMCU_CR_DBG_TIM2_STOP_Pos (11U)
+#define DBGMCU_CR_DBG_TIM2_STOP_Msk (0x1U << DBGMCU_CR_DBG_TIM2_STOP_Pos) /*!< 0x00000800 */
+#define DBGMCU_CR_DBG_TIM2_STOP DBGMCU_CR_DBG_TIM2_STOP_Msk /*!< TIM2 counter stopped when core is halted */
+#define DBGMCU_CR_DBG_TIM3_STOP_Pos (12U)
+#define DBGMCU_CR_DBG_TIM3_STOP_Msk (0x1U << DBGMCU_CR_DBG_TIM3_STOP_Pos) /*!< 0x00001000 */
+#define DBGMCU_CR_DBG_TIM3_STOP DBGMCU_CR_DBG_TIM3_STOP_Msk /*!< TIM3 counter stopped when core is halted */
+#define DBGMCU_CR_DBG_TIM4_STOP_Pos (13U)
+#define DBGMCU_CR_DBG_TIM4_STOP_Msk (0x1U << DBGMCU_CR_DBG_TIM4_STOP_Pos) /*!< 0x00002000 */
+#define DBGMCU_CR_DBG_TIM4_STOP DBGMCU_CR_DBG_TIM4_STOP_Msk /*!< TIM4 counter stopped when core is halted */
+#define DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT_Pos (15U)
+#define DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT_Msk (0x1U << DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT_Pos) /*!< 0x00008000 */
+#define DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT_Msk /*!< SMBUS timeout mode stopped when Core is halted */
+#define DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT_Pos (16U)
+#define DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT_Msk (0x1U << DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT_Pos) /*!< 0x00010000 */
+#define DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT_Msk /*!< SMBUS timeout mode stopped when Core is halted */
+#define DBGMCU_CR_DBG_TIM5_STOP_Pos (18U)
+#define DBGMCU_CR_DBG_TIM5_STOP_Msk (0x1U << DBGMCU_CR_DBG_TIM5_STOP_Pos) /*!< 0x00040000 */
+#define DBGMCU_CR_DBG_TIM5_STOP DBGMCU_CR_DBG_TIM5_STOP_Msk /*!< TIM5 counter stopped when core is halted */
+#define DBGMCU_CR_DBG_TIM6_STOP_Pos (19U)
+#define DBGMCU_CR_DBG_TIM6_STOP_Msk (0x1U << DBGMCU_CR_DBG_TIM6_STOP_Pos) /*!< 0x00080000 */
+#define DBGMCU_CR_DBG_TIM6_STOP DBGMCU_CR_DBG_TIM6_STOP_Msk /*!< TIM6 counter stopped when core is halted */
+#define DBGMCU_CR_DBG_TIM7_STOP_Pos (20U)
+#define DBGMCU_CR_DBG_TIM7_STOP_Msk (0x1U << DBGMCU_CR_DBG_TIM7_STOP_Pos) /*!< 0x00100000 */
+#define DBGMCU_CR_DBG_TIM7_STOP DBGMCU_CR_DBG_TIM7_STOP_Msk /*!< TIM7 counter stopped when core is halted */
+#define DBGMCU_CR_DBG_TIM12_STOP_Pos (25U)
+#define DBGMCU_CR_DBG_TIM12_STOP_Msk (0x1U << DBGMCU_CR_DBG_TIM12_STOP_Pos) /*!< 0x02000000 */
+#define DBGMCU_CR_DBG_TIM12_STOP DBGMCU_CR_DBG_TIM12_STOP_Msk /*!< Debug TIM12 stopped when Core is halted */
+#define DBGMCU_CR_DBG_TIM13_STOP_Pos (26U)
+#define DBGMCU_CR_DBG_TIM13_STOP_Msk (0x1U << DBGMCU_CR_DBG_TIM13_STOP_Pos) /*!< 0x04000000 */
+#define DBGMCU_CR_DBG_TIM13_STOP DBGMCU_CR_DBG_TIM13_STOP_Msk /*!< Debug TIM13 stopped when Core is halted */
+#define DBGMCU_CR_DBG_TIM14_STOP_Pos (27U)
+#define DBGMCU_CR_DBG_TIM14_STOP_Msk (0x1U << DBGMCU_CR_DBG_TIM14_STOP_Pos) /*!< 0x08000000 */
+#define DBGMCU_CR_DBG_TIM14_STOP DBGMCU_CR_DBG_TIM14_STOP_Msk /*!< Debug TIM14 stopped when Core is halted */
+#define DBGMCU_CR_DBG_TIM9_STOP_Pos (28U)
+#define DBGMCU_CR_DBG_TIM9_STOP_Msk (0x1U << DBGMCU_CR_DBG_TIM9_STOP_Pos) /*!< 0x10000000 */
+#define DBGMCU_CR_DBG_TIM9_STOP DBGMCU_CR_DBG_TIM9_STOP_Msk /*!< Debug TIM9 stopped when Core is halted */
+#define DBGMCU_CR_DBG_TIM10_STOP_Pos (29U)
+#define DBGMCU_CR_DBG_TIM10_STOP_Msk (0x1U << DBGMCU_CR_DBG_TIM10_STOP_Pos) /*!< 0x20000000 */
+#define DBGMCU_CR_DBG_TIM10_STOP DBGMCU_CR_DBG_TIM10_STOP_Msk /*!< Debug TIM10 stopped when Core is halted */
+#define DBGMCU_CR_DBG_TIM11_STOP_Pos (30U)
+#define DBGMCU_CR_DBG_TIM11_STOP_Msk (0x1U << DBGMCU_CR_DBG_TIM11_STOP_Pos) /*!< 0x40000000 */
+#define DBGMCU_CR_DBG_TIM11_STOP DBGMCU_CR_DBG_TIM11_STOP_Msk /*!< Debug TIM11 stopped when Core is halted */
+
+/******************************************************************************/
+/* */
+/* FLASH and Option Bytes Registers */
+/* */
+/******************************************************************************/
+/******************* Bit definition for FLASH_ACR register ******************/
+#define FLASH_ACR_LATENCY_Pos (0U)
+#define FLASH_ACR_LATENCY_Msk (0x7U << FLASH_ACR_LATENCY_Pos) /*!< 0x00000007 */
+#define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk /*!< LATENCY[2:0] bits (Latency) */
+#define FLASH_ACR_LATENCY_0 (0x1U << FLASH_ACR_LATENCY_Pos) /*!< 0x00000001 */
+#define FLASH_ACR_LATENCY_1 (0x2U << FLASH_ACR_LATENCY_Pos) /*!< 0x00000002 */
+#define FLASH_ACR_LATENCY_2 (0x4U << FLASH_ACR_LATENCY_Pos) /*!< 0x00000004 */
+
+#define FLASH_ACR_HLFCYA_Pos (3U)
+#define FLASH_ACR_HLFCYA_Msk (0x1U << FLASH_ACR_HLFCYA_Pos) /*!< 0x00000008 */
+#define FLASH_ACR_HLFCYA FLASH_ACR_HLFCYA_Msk /*!< Flash Half Cycle Access Enable */
+#define FLASH_ACR_PRFTBE_Pos (4U)
+#define FLASH_ACR_PRFTBE_Msk (0x1U << FLASH_ACR_PRFTBE_Pos) /*!< 0x00000010 */
+#define FLASH_ACR_PRFTBE FLASH_ACR_PRFTBE_Msk /*!< Prefetch Buffer Enable */
+#define FLASH_ACR_PRFTBS_Pos (5U)
+#define FLASH_ACR_PRFTBS_Msk (0x1U << FLASH_ACR_PRFTBS_Pos) /*!< 0x00000020 */
+#define FLASH_ACR_PRFTBS FLASH_ACR_PRFTBS_Msk /*!< Prefetch Buffer Status */
+
+/****************** Bit definition for FLASH_KEYR register ******************/
+#define FLASH_KEYR_FKEYR_Pos (0U)
+#define FLASH_KEYR_FKEYR_Msk (0xFFFFFFFFU << FLASH_KEYR_FKEYR_Pos) /*!< 0xFFFFFFFF */
+#define FLASH_KEYR_FKEYR FLASH_KEYR_FKEYR_Msk /*!< FPEC Key */
+
+#define RDP_KEY_Pos (0U)
+#define RDP_KEY_Msk (0xA5U << RDP_KEY_Pos) /*!< 0x000000A5 */
+#define RDP_KEY RDP_KEY_Msk /*!< RDP Key */
+#define FLASH_KEY1_Pos (0U)
+#define FLASH_KEY1_Msk (0x45670123U << FLASH_KEY1_Pos) /*!< 0x45670123 */
+#define FLASH_KEY1 FLASH_KEY1_Msk /*!< FPEC Key1 */
+#define FLASH_KEY2_Pos (0U)
+#define FLASH_KEY2_Msk (0xCDEF89ABU << FLASH_KEY2_Pos) /*!< 0xCDEF89AB */
+#define FLASH_KEY2 FLASH_KEY2_Msk /*!< FPEC Key2 */
+
+/***************** Bit definition for FLASH_OPTKEYR register ****************/
+#define FLASH_OPTKEYR_OPTKEYR_Pos (0U)
+#define FLASH_OPTKEYR_OPTKEYR_Msk (0xFFFFFFFFU << FLASH_OPTKEYR_OPTKEYR_Pos) /*!< 0xFFFFFFFF */
+#define FLASH_OPTKEYR_OPTKEYR FLASH_OPTKEYR_OPTKEYR_Msk /*!< Option Byte Key */
+
+#define FLASH_OPTKEY1 FLASH_KEY1 /*!< Option Byte Key1 */
+#define FLASH_OPTKEY2 FLASH_KEY2 /*!< Option Byte Key2 */
+
+/****************** Bit definition for FLASH_SR register ********************/
+#define FLASH_SR_BSY_Pos (0U)
+#define FLASH_SR_BSY_Msk (0x1U << FLASH_SR_BSY_Pos) /*!< 0x00000001 */
+#define FLASH_SR_BSY FLASH_SR_BSY_Msk /*!< Busy */
+#define FLASH_SR_PGERR_Pos (2U)
+#define FLASH_SR_PGERR_Msk (0x1U << FLASH_SR_PGERR_Pos) /*!< 0x00000004 */
+#define FLASH_SR_PGERR FLASH_SR_PGERR_Msk /*!< Programming Error */
+#define FLASH_SR_WRPRTERR_Pos (4U)
+#define FLASH_SR_WRPRTERR_Msk (0x1U << FLASH_SR_WRPRTERR_Pos) /*!< 0x00000010 */
+#define FLASH_SR_WRPRTERR FLASH_SR_WRPRTERR_Msk /*!< Write Protection Error */
+#define FLASH_SR_EOP_Pos (5U)
+#define FLASH_SR_EOP_Msk (0x1U << FLASH_SR_EOP_Pos) /*!< 0x00000020 */
+#define FLASH_SR_EOP FLASH_SR_EOP_Msk /*!< End of operation */
+
+/******************* Bit definition for FLASH_CR register *******************/
+#define FLASH_CR_PG_Pos (0U)
+#define FLASH_CR_PG_Msk (0x1U << FLASH_CR_PG_Pos) /*!< 0x00000001 */
+#define FLASH_CR_PG FLASH_CR_PG_Msk /*!< Programming */
+#define FLASH_CR_PER_Pos (1U)
+#define FLASH_CR_PER_Msk (0x1U << FLASH_CR_PER_Pos) /*!< 0x00000002 */
+#define FLASH_CR_PER FLASH_CR_PER_Msk /*!< Page Erase */
+#define FLASH_CR_MER_Pos (2U)
+#define FLASH_CR_MER_Msk (0x1U << FLASH_CR_MER_Pos) /*!< 0x00000004 */
+#define FLASH_CR_MER FLASH_CR_MER_Msk /*!< Mass Erase */
+#define FLASH_CR_OPTPG_Pos (4U)
+#define FLASH_CR_OPTPG_Msk (0x1U << FLASH_CR_OPTPG_Pos) /*!< 0x00000010 */
+#define FLASH_CR_OPTPG FLASH_CR_OPTPG_Msk /*!< Option Byte Programming */
+#define FLASH_CR_OPTER_Pos (5U)
+#define FLASH_CR_OPTER_Msk (0x1U << FLASH_CR_OPTER_Pos) /*!< 0x00000020 */
+#define FLASH_CR_OPTER FLASH_CR_OPTER_Msk /*!< Option Byte Erase */
+#define FLASH_CR_STRT_Pos (6U)
+#define FLASH_CR_STRT_Msk (0x1U << FLASH_CR_STRT_Pos) /*!< 0x00000040 */
+#define FLASH_CR_STRT FLASH_CR_STRT_Msk /*!< Start */
+#define FLASH_CR_LOCK_Pos (7U)
+#define FLASH_CR_LOCK_Msk (0x1U << FLASH_CR_LOCK_Pos) /*!< 0x00000080 */
+#define FLASH_CR_LOCK FLASH_CR_LOCK_Msk /*!< Lock */
+#define FLASH_CR_OPTWRE_Pos (9U)
+#define FLASH_CR_OPTWRE_Msk (0x1U << FLASH_CR_OPTWRE_Pos) /*!< 0x00000200 */
+#define FLASH_CR_OPTWRE FLASH_CR_OPTWRE_Msk /*!< Option Bytes Write Enable */
+#define FLASH_CR_ERRIE_Pos (10U)
+#define FLASH_CR_ERRIE_Msk (0x1U << FLASH_CR_ERRIE_Pos) /*!< 0x00000400 */
+#define FLASH_CR_ERRIE FLASH_CR_ERRIE_Msk /*!< Error Interrupt Enable */
+#define FLASH_CR_EOPIE_Pos (12U)
+#define FLASH_CR_EOPIE_Msk (0x1U << FLASH_CR_EOPIE_Pos) /*!< 0x00001000 */
+#define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk /*!< End of operation interrupt enable */
+
+/******************* Bit definition for FLASH_AR register *******************/
+#define FLASH_AR_FAR_Pos (0U)
+#define FLASH_AR_FAR_Msk (0xFFFFFFFFU << FLASH_AR_FAR_Pos) /*!< 0xFFFFFFFF */
+#define FLASH_AR_FAR FLASH_AR_FAR_Msk /*!< Flash Address */
+
+/****************** Bit definition for FLASH_OBR register *******************/
+#define FLASH_OBR_OPTERR_Pos (0U)
+#define FLASH_OBR_OPTERR_Msk (0x1U << FLASH_OBR_OPTERR_Pos) /*!< 0x00000001 */
+#define FLASH_OBR_OPTERR FLASH_OBR_OPTERR_Msk /*!< Option Byte Error */
+#define FLASH_OBR_RDPRT_Pos (1U)
+#define FLASH_OBR_RDPRT_Msk (0x1U << FLASH_OBR_RDPRT_Pos) /*!< 0x00000002 */
+#define FLASH_OBR_RDPRT FLASH_OBR_RDPRT_Msk /*!< Read protection */
+
+#define FLASH_OBR_IWDG_SW_Pos (2U)
+#define FLASH_OBR_IWDG_SW_Msk (0x1U << FLASH_OBR_IWDG_SW_Pos) /*!< 0x00000004 */
+#define FLASH_OBR_IWDG_SW FLASH_OBR_IWDG_SW_Msk /*!< IWDG SW */
+#define FLASH_OBR_nRST_STOP_Pos (3U)
+#define FLASH_OBR_nRST_STOP_Msk (0x1U << FLASH_OBR_nRST_STOP_Pos) /*!< 0x00000008 */
+#define FLASH_OBR_nRST_STOP FLASH_OBR_nRST_STOP_Msk /*!< nRST_STOP */
+#define FLASH_OBR_nRST_STDBY_Pos (4U)
+#define FLASH_OBR_nRST_STDBY_Msk (0x1U << FLASH_OBR_nRST_STDBY_Pos) /*!< 0x00000010 */
+#define FLASH_OBR_nRST_STDBY FLASH_OBR_nRST_STDBY_Msk /*!< nRST_STDBY */
+#define FLASH_OBR_BFB2_Pos (5U)
+#define FLASH_OBR_BFB2_Msk (0x1U << FLASH_OBR_BFB2_Pos) /*!< 0x00000020 */
+#define FLASH_OBR_BFB2 FLASH_OBR_BFB2_Msk /*!< BFB2 */
+#define FLASH_OBR_USER_Pos (2U)
+#define FLASH_OBR_USER_Msk (0xFU << FLASH_OBR_USER_Pos) /*!< 0x0000003C */
+#define FLASH_OBR_USER FLASH_OBR_USER_Msk /*!< User Option Bytes */
+#define FLASH_OBR_DATA0_Pos (10U)
+#define FLASH_OBR_DATA0_Msk (0xFFU << FLASH_OBR_DATA0_Pos) /*!< 0x0003FC00 */
+#define FLASH_OBR_DATA0 FLASH_OBR_DATA0_Msk /*!< Data0 */
+#define FLASH_OBR_DATA1_Pos (18U)
+#define FLASH_OBR_DATA1_Msk (0xFFU << FLASH_OBR_DATA1_Pos) /*!< 0x03FC0000 */
+#define FLASH_OBR_DATA1 FLASH_OBR_DATA1_Msk /*!< Data1 */
+
+/****************** Bit definition for FLASH_WRPR register ******************/
+#define FLASH_WRPR_WRP_Pos (0U)
+#define FLASH_WRPR_WRP_Msk (0xFFFFFFFFU << FLASH_WRPR_WRP_Pos) /*!< 0xFFFFFFFF */
+#define FLASH_WRPR_WRP FLASH_WRPR_WRP_Msk /*!< Write Protect */
+
+/***************** Bit definition for FLASH_OPTKEYR2 register ****************/
+#define FLASH_OPTKEYR_OPTKEYR2_Pos (0U)
+#define FLASH_OPTKEYR_OPTKEYR2_Msk (0xFFFFFFFFU << FLASH_OPTKEYR_OPTKEYR2_Pos) /*!< 0xFFFFFFFF */
+#define FLASH_OPTKEYR_OPTKEYR2 FLASH_OPTKEYR_OPTKEYR2_Msk /*!< Option Byte Key */
+
+/****************** Bit definition for FLASH_SR2 register ********************/
+#define FLASH_SR2_BSY_Pos (0U)
+#define FLASH_SR2_BSY_Msk (0x1U << FLASH_SR2_BSY_Pos) /*!< 0x00000001 */
+#define FLASH_SR2_BSY FLASH_SR2_BSY_Msk /*!< Busy */
+#define FLASH_SR2_PGERR_Pos (2U)
+#define FLASH_SR2_PGERR_Msk (0x1U << FLASH_SR2_PGERR_Pos) /*!< 0x00000004 */
+#define FLASH_SR2_PGERR FLASH_SR2_PGERR_Msk /*!< Programming Error */
+#define FLASH_SR2_WRPRTERR_Pos (4U)
+#define FLASH_SR2_WRPRTERR_Msk (0x1U << FLASH_SR2_WRPRTERR_Pos) /*!< 0x00000010 */
+#define FLASH_SR2_WRPRTERR FLASH_SR2_WRPRTERR_Msk /*!< Write Protection Error */
+#define FLASH_SR2_EOP_Pos (5U)
+#define FLASH_SR2_EOP_Msk (0x1U << FLASH_SR2_EOP_Pos) /*!< 0x00000020 */
+#define FLASH_SR2_EOP FLASH_SR2_EOP_Msk /*!< End of operation */
+
+/******************* Bit definition for FLASH_CR2 register *******************/
+#define FLASH_CR2_PG_Pos (0U)
+#define FLASH_CR2_PG_Msk (0x1U << FLASH_CR2_PG_Pos) /*!< 0x00000001 */
+#define FLASH_CR2_PG FLASH_CR2_PG_Msk /*!< Programming */
+#define FLASH_CR2_PER_Pos (1U)
+#define FLASH_CR2_PER_Msk (0x1U << FLASH_CR2_PER_Pos) /*!< 0x00000002 */
+#define FLASH_CR2_PER FLASH_CR2_PER_Msk /*!< Page Erase */
+#define FLASH_CR2_MER_Pos (2U)
+#define FLASH_CR2_MER_Msk (0x1U << FLASH_CR2_MER_Pos) /*!< 0x00000004 */
+#define FLASH_CR2_MER FLASH_CR2_MER_Msk /*!< Mass Erase */
+#define FLASH_CR2_STRT_Pos (6U)
+#define FLASH_CR2_STRT_Msk (0x1U << FLASH_CR2_STRT_Pos) /*!< 0x00000040 */
+#define FLASH_CR2_STRT FLASH_CR2_STRT_Msk /*!< Start */
+#define FLASH_CR2_LOCK_Pos (7U)
+#define FLASH_CR2_LOCK_Msk (0x1U << FLASH_CR2_LOCK_Pos) /*!< 0x00000080 */
+#define FLASH_CR2_LOCK FLASH_CR2_LOCK_Msk /*!< Lock */
+#define FLASH_CR2_ERRIE_Pos (10U)
+#define FLASH_CR2_ERRIE_Msk (0x1U << FLASH_CR2_ERRIE_Pos) /*!< 0x00000400 */
+#define FLASH_CR2_ERRIE FLASH_CR2_ERRIE_Msk /*!< Error Interrupt Enable */
+#define FLASH_CR2_EOPIE_Pos (12U)
+#define FLASH_CR2_EOPIE_Msk (0x1U << FLASH_CR2_EOPIE_Pos) /*!< 0x00001000 */
+#define FLASH_CR2_EOPIE FLASH_CR2_EOPIE_Msk /*!< End of operation interrupt enable */
+
+/******************* Bit definition for FLASH_AR2 register *******************/
+#define FLASH_AR_FAR2_Pos (0U)
+#define FLASH_AR_FAR2_Msk (0xFFFFFFFFU << FLASH_AR_FAR2_Pos) /*!< 0xFFFFFFFF */
+#define FLASH_AR_FAR2 FLASH_AR_FAR2_Msk /*!< Flash Address */
+
+/*----------------------------------------------------------------------------*/
+
+/****************** Bit definition for FLASH_RDP register *******************/
+#define FLASH_RDP_RDP_Pos (0U)
+#define FLASH_RDP_RDP_Msk (0xFFU << FLASH_RDP_RDP_Pos) /*!< 0x000000FF */
+#define FLASH_RDP_RDP FLASH_RDP_RDP_Msk /*!< Read protection option byte */
+#define FLASH_RDP_nRDP_Pos (8U)
+#define FLASH_RDP_nRDP_Msk (0xFFU << FLASH_RDP_nRDP_Pos) /*!< 0x0000FF00 */
+#define FLASH_RDP_nRDP FLASH_RDP_nRDP_Msk /*!< Read protection complemented option byte */
+
+/****************** Bit definition for FLASH_USER register ******************/
+#define FLASH_USER_USER_Pos (16U)
+#define FLASH_USER_USER_Msk (0xFFU << FLASH_USER_USER_Pos) /*!< 0x00FF0000 */
+#define FLASH_USER_USER FLASH_USER_USER_Msk /*!< User option byte */
+#define FLASH_USER_nUSER_Pos (24U)
+#define FLASH_USER_nUSER_Msk (0xFFU << FLASH_USER_nUSER_Pos) /*!< 0xFF000000 */
+#define FLASH_USER_nUSER FLASH_USER_nUSER_Msk /*!< User complemented option byte */
+
+/****************** Bit definition for FLASH_Data0 register *****************/
+#define FLASH_DATA0_DATA0_Pos (0U)
+#define FLASH_DATA0_DATA0_Msk (0xFFU << FLASH_DATA0_DATA0_Pos) /*!< 0x000000FF */
+#define FLASH_DATA0_DATA0 FLASH_DATA0_DATA0_Msk /*!< User data storage option byte */
+#define FLASH_DATA0_nDATA0_Pos (8U)
+#define FLASH_DATA0_nDATA0_Msk (0xFFU << FLASH_DATA0_nDATA0_Pos) /*!< 0x0000FF00 */
+#define FLASH_DATA0_nDATA0 FLASH_DATA0_nDATA0_Msk /*!< User data storage complemented option byte */
+
+/****************** Bit definition for FLASH_Data1 register *****************/
+#define FLASH_DATA1_DATA1_Pos (16U)
+#define FLASH_DATA1_DATA1_Msk (0xFFU << FLASH_DATA1_DATA1_Pos) /*!< 0x00FF0000 */
+#define FLASH_DATA1_DATA1 FLASH_DATA1_DATA1_Msk /*!< User data storage option byte */
+#define FLASH_DATA1_nDATA1_Pos (24U)
+#define FLASH_DATA1_nDATA1_Msk (0xFFU << FLASH_DATA1_nDATA1_Pos) /*!< 0xFF000000 */
+#define FLASH_DATA1_nDATA1 FLASH_DATA1_nDATA1_Msk /*!< User data storage complemented option byte */
+
+/****************** Bit definition for FLASH_WRP0 register ******************/
+#define FLASH_WRP0_WRP0_Pos (0U)
+#define FLASH_WRP0_WRP0_Msk (0xFFU << FLASH_WRP0_WRP0_Pos) /*!< 0x000000FF */
+#define FLASH_WRP0_WRP0 FLASH_WRP0_WRP0_Msk /*!< Flash memory write protection option bytes */
+#define FLASH_WRP0_nWRP0_Pos (8U)
+#define FLASH_WRP0_nWRP0_Msk (0xFFU << FLASH_WRP0_nWRP0_Pos) /*!< 0x0000FF00 */
+#define FLASH_WRP0_nWRP0 FLASH_WRP0_nWRP0_Msk /*!< Flash memory write protection complemented option bytes */
+
+/****************** Bit definition for FLASH_WRP1 register ******************/
+#define FLASH_WRP1_WRP1_Pos (16U)
+#define FLASH_WRP1_WRP1_Msk (0xFFU << FLASH_WRP1_WRP1_Pos) /*!< 0x00FF0000 */
+#define FLASH_WRP1_WRP1 FLASH_WRP1_WRP1_Msk /*!< Flash memory write protection option bytes */
+#define FLASH_WRP1_nWRP1_Pos (24U)
+#define FLASH_WRP1_nWRP1_Msk (0xFFU << FLASH_WRP1_nWRP1_Pos) /*!< 0xFF000000 */
+#define FLASH_WRP1_nWRP1 FLASH_WRP1_nWRP1_Msk /*!< Flash memory write protection complemented option bytes */
+
+/****************** Bit definition for FLASH_WRP2 register ******************/
+#define FLASH_WRP2_WRP2_Pos (0U)
+#define FLASH_WRP2_WRP2_Msk (0xFFU << FLASH_WRP2_WRP2_Pos) /*!< 0x000000FF */
+#define FLASH_WRP2_WRP2 FLASH_WRP2_WRP2_Msk /*!< Flash memory write protection option bytes */
+#define FLASH_WRP2_nWRP2_Pos (8U)
+#define FLASH_WRP2_nWRP2_Msk (0xFFU << FLASH_WRP2_nWRP2_Pos) /*!< 0x0000FF00 */
+#define FLASH_WRP2_nWRP2 FLASH_WRP2_nWRP2_Msk /*!< Flash memory write protection complemented option bytes */
+
+/****************** Bit definition for FLASH_WRP3 register ******************/
+#define FLASH_WRP3_WRP3_Pos (16U)
+#define FLASH_WRP3_WRP3_Msk (0xFFU << FLASH_WRP3_WRP3_Pos) /*!< 0x00FF0000 */
+#define FLASH_WRP3_WRP3 FLASH_WRP3_WRP3_Msk /*!< Flash memory write protection option bytes */
+#define FLASH_WRP3_nWRP3_Pos (24U)
+#define FLASH_WRP3_nWRP3_Msk (0xFFU << FLASH_WRP3_nWRP3_Pos) /*!< 0xFF000000 */
+#define FLASH_WRP3_nWRP3 FLASH_WRP3_nWRP3_Msk /*!< Flash memory write protection complemented option bytes */
+
+
+
+/**
+ * @}
+*/
+
+/**
+ * @}
+*/
+
+/** @addtogroup Exported_macro
+ * @{
+ */
+
+/****************************** ADC Instances *********************************/
+#define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) || \
+ ((INSTANCE) == ADC2))
+
+#define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC12_COMMON)
+
+#define IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
+
+#define IS_ADC_DMA_CAPABILITY_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
+
+/****************************** CRC Instances *********************************/
+#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
+
+/****************************** DAC Instances *********************************/
+#define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC)
+
+/****************************** DMA Instances *********************************/
+#define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \
+ ((INSTANCE) == DMA1_Channel2) || \
+ ((INSTANCE) == DMA1_Channel3) || \
+ ((INSTANCE) == DMA1_Channel4) || \
+ ((INSTANCE) == DMA1_Channel5) || \
+ ((INSTANCE) == DMA1_Channel6) || \
+ ((INSTANCE) == DMA1_Channel7) || \
+ ((INSTANCE) == DMA2_Channel1) || \
+ ((INSTANCE) == DMA2_Channel2) || \
+ ((INSTANCE) == DMA2_Channel3) || \
+ ((INSTANCE) == DMA2_Channel4) || \
+ ((INSTANCE) == DMA2_Channel5))
+
+/******************************* GPIO Instances *******************************/
+#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
+ ((INSTANCE) == GPIOB) || \
+ ((INSTANCE) == GPIOC) || \
+ ((INSTANCE) == GPIOD) || \
+ ((INSTANCE) == GPIOE) || \
+ ((INSTANCE) == GPIOF) || \
+ ((INSTANCE) == GPIOG))
+
+/**************************** GPIO Alternate Function Instances ***************/
+#define IS_GPIO_AF_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
+
+/**************************** GPIO Lock Instances *****************************/
+#define IS_GPIO_LOCK_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
+
+/******************************** I2C Instances *******************************/
+#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
+ ((INSTANCE) == I2C2))
+
+/****************************** IWDG Instances ********************************/
+#define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
+
+/******************************** SPI Instances *******************************/
+#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
+ ((INSTANCE) == SPI2) || \
+ ((INSTANCE) == SPI3))
+
+/****************************** START TIM Instances ***************************/
+/****************************** TIM Instances *********************************/
+#define IS_TIM_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM6) || \
+ ((INSTANCE) == TIM7) || \
+ ((INSTANCE) == TIM9) || \
+ ((INSTANCE) == TIM10) || \
+ ((INSTANCE) == TIM11) || \
+ ((INSTANCE) == TIM12) || \
+ ((INSTANCE) == TIM13) || \
+ ((INSTANCE) == TIM14))
+
+#define IS_TIM_CC1_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM9) || \
+ ((INSTANCE) == TIM10) || \
+ ((INSTANCE) == TIM11) || \
+ ((INSTANCE) == TIM12) || \
+ ((INSTANCE) == TIM13) || \
+ ((INSTANCE) == TIM14))
+
+#define IS_TIM_CC2_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM9) || \
+ ((INSTANCE) == TIM12))
+
+#define IS_TIM_CC3_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5))
+
+#define IS_TIM_CC4_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5))
+
+#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5))
+
+#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5))
+
+#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM9) || \
+ ((INSTANCE) == TIM12))
+
+#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM9) || \
+ ((INSTANCE) == TIM12))
+
+#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5))
+
+#define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5))
+
+#define IS_TIM_XOR_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5))
+
+#define IS_TIM_MASTER_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM6) || \
+ ((INSTANCE) == TIM7) || \
+ ((INSTANCE) == TIM12))
+
+#define IS_TIM_SLAVE_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM12))
+
+#define IS_TIM_DMABURST_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5))
+
+#define IS_TIM_BREAK_INSTANCE(INSTANCE) (0)
+
+#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
+ ((((INSTANCE) == TIM2) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM3) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM4) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM5) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM9) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2))) \
+ || \
+ (((INSTANCE) == TIM10) && \
+ (((CHANNEL) == TIM_CHANNEL_1))) \
+ || \
+ (((INSTANCE) == TIM11) && \
+ (((CHANNEL) == TIM_CHANNEL_1))) \
+ || \
+ (((INSTANCE) == TIM12) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2))) \
+ || \
+ (((INSTANCE) == TIM13) && \
+ (((CHANNEL) == TIM_CHANNEL_1))) \
+ || \
+ (((INSTANCE) == TIM14) && \
+ (((CHANNEL) == TIM_CHANNEL_1))))
+
+#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) (0)
+
+#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5))
+
+#define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE) (0)
+
+#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM9) || \
+ ((INSTANCE) == TIM10) || \
+ ((INSTANCE) == TIM11) || \
+ ((INSTANCE) == TIM12) || \
+ ((INSTANCE) == TIM13) || \
+ ((INSTANCE) == TIM14))
+
+#define IS_TIM_DMA_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM6) || \
+ ((INSTANCE) == TIM7))
+
+#define IS_TIM_DMA_CC_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5))
+
+#define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) (0)
+
+/****************************** END TIM Instances *****************************/
+
+
+/******************** USART Instances : Synchronous mode **********************/
+#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3))
+
+/******************** UART Instances : Asynchronous mode **********************/
+#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3) || \
+ ((INSTANCE) == UART4) || \
+ ((INSTANCE) == UART5))
+
+/******************** UART Instances : Half-Duplex mode **********************/
+#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3) || \
+ ((INSTANCE) == UART4) || \
+ ((INSTANCE) == UART5))
+
+/******************** UART Instances : LIN mode **********************/
+#define IS_UART_LIN_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3) || \
+ ((INSTANCE) == UART4) || \
+ ((INSTANCE) == UART5))
+
+/****************** UART Instances : Hardware Flow control ********************/
+#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3))
+
+/********************* UART Instances : Smard card mode ***********************/
+#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3))
+
+/*********************** UART Instances : IRDA mode ***************************/
+#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3) || \
+ ((INSTANCE) == UART4) || \
+ ((INSTANCE) == UART5))
+
+/***************** UART Instances : Multi-Processor mode **********************/
+#define IS_UART_MULTIPROCESSOR_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3) || \
+ ((INSTANCE) == UART4) || \
+ ((INSTANCE) == UART5))
+
+/***************** UART Instances : DMA mode available **********************/
+#define IS_UART_DMA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3) || \
+ ((INSTANCE) == UART4))
+
+/****************************** RTC Instances *********************************/
+#define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
+
+/**************************** WWDG Instances *****************************/
+#define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
+
+
+
+
+
+/**
+ * @}
+*/
+/******************************************************************************/
+/* For a painless codes migration between the STM32F1xx device product */
+/* lines, the aliases defined below are put in place to overcome the */
+/* differences in the interrupt handlers and IRQn definitions. */
+/* No need to update developed interrupt code when moving across */
+/* product lines within the same STM32F1 Family */
+/******************************************************************************/
+
+/* Aliases for __IRQn */
+#define ADC1_IRQn ADC1_2_IRQn
+#define DMA2_Channel4_IRQn DMA2_Channel4_5_IRQn
+#define TIM1_UP_TIM16_IRQn TIM10_IRQn
+#define TIM1_UP_IRQn TIM10_IRQn
+#define TIM1_UP_TIM10_IRQn TIM10_IRQn
+#define TIM1_TRG_COM_TIM11_IRQn TIM11_IRQn
+#define TIM1_TRG_COM_TIM17_IRQn TIM11_IRQn
+#define TIM1_TRG_COM_IRQn TIM11_IRQn
+#define TIM8_BRK_TIM12_IRQn TIM12_IRQn
+#define TIM8_BRK_IRQn TIM12_IRQn
+#define TIM8_UP_IRQn TIM13_IRQn
+#define TIM8_UP_TIM13_IRQn TIM13_IRQn
+#define TIM8_TRG_COM_IRQn TIM14_IRQn
+#define TIM8_TRG_COM_TIM14_IRQn TIM14_IRQn
+#define TIM6_DAC_IRQn TIM6_IRQn
+#define TIM1_BRK_TIM15_IRQn TIM9_IRQn
+#define TIM1_BRK_IRQn TIM9_IRQn
+#define TIM1_BRK_TIM9_IRQn TIM9_IRQn
+
+
+/* Aliases for __IRQHandler */
+#define ADC1_IRQHandler ADC1_2_IRQHandler
+#define DMA2_Channel4_IRQHandler DMA2_Channel4_5_IRQHandler
+#define TIM1_UP_TIM16_IRQHandler TIM10_IRQHandler
+#define TIM1_UP_IRQHandler TIM10_IRQHandler
+#define TIM1_UP_TIM10_IRQHandler TIM10_IRQHandler
+#define TIM1_TRG_COM_TIM11_IRQHandler TIM11_IRQHandler
+#define TIM1_TRG_COM_TIM17_IRQHandler TIM11_IRQHandler
+#define TIM1_TRG_COM_IRQHandler TIM11_IRQHandler
+#define TIM8_BRK_TIM12_IRQHandler TIM12_IRQHandler
+#define TIM8_BRK_IRQHandler TIM12_IRQHandler
+#define TIM8_UP_IRQHandler TIM13_IRQHandler
+#define TIM8_UP_TIM13_IRQHandler TIM13_IRQHandler
+#define TIM8_TRG_COM_IRQHandler TIM14_IRQHandler
+#define TIM8_TRG_COM_TIM14_IRQHandler TIM14_IRQHandler
+#define TIM6_DAC_IRQHandler TIM6_IRQHandler
+#define TIM1_BRK_TIM15_IRQHandler TIM9_IRQHandler
+#define TIM1_BRK_IRQHandler TIM9_IRQHandler
+#define TIM1_BRK_TIM9_IRQHandler TIM9_IRQHandler
+
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+
+#ifdef __cplusplus
+ }
+#endif /* __cplusplus */
+
+#endif /* __STM32F101xG_H */
+
+
+
+ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Device/ST/STM32F1xx/Include/stm32f102x6.h b/Device/ST/STM32F1xx/Include/stm32f102x6.h
new file mode 100644
index 0000000..4fb02af
--- /dev/null
+++ b/Device/ST/STM32F1xx/Include/stm32f102x6.h
@@ -0,0 +1,7285 @@
+/**
+ ******************************************************************************
+ * @file stm32f102x6.h
+ * @author MCD Application Team
+ * @version V4.1.0
+ * @date 29-April-2016
+ * @brief CMSIS Cortex-M3 Device Peripheral Access Layer Header File.
+ * This file contains all the peripheral register's definitions, bits
+ * definitions and memory mapping for STM32F1xx devices.
+ *
+ * This file contains:
+ * - Data structures and the address mapping for all peripherals
+ * - Peripheral's registers declarations and bits definition
+ * - Macros to access peripheral’s registers hardware
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+
+/** @addtogroup CMSIS
+ * @{
+ */
+
+/** @addtogroup stm32f102x6
+ * @{
+ */
+
+#ifndef __STM32F102x6_H
+#define __STM32F102x6_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/** @addtogroup Configuration_section_for_CMSIS
+ * @{
+ */
+/**
+ * @brief Configuration of the Cortex-M3 Processor and Core Peripherals
+ */
+ #define __MPU_PRESENT 0 /*!< Other STM32 devices does not provide an MPU */
+#define __CM3_REV 0x0200 /*!< Core Revision r2p0 */
+#define __NVIC_PRIO_BITS 4 /*!< STM32 uses 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
+
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_interrupt_number_definition
+ * @{
+ */
+
+/**
+ * @brief STM32F10x Interrupt Number Definition, according to the selected device
+ * in @ref Library_configuration_section
+ */
+
+ /*!< Interrupt Number Definition */
+typedef enum
+{
+/****** Cortex-M3 Processor Exceptions Numbers ***************************************************/
+ NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
+ HardFault_IRQn = -13, /*!< 3 Cortex-M3 Hard Fault Interrupt */
+ MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */
+ BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */
+ UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */
+ SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */
+ DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */
+ PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */
+ SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */
+
+/****** STM32 specific Interrupt Numbers *********************************************************/
+ WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
+ PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */
+ TAMPER_IRQn = 2, /*!< Tamper Interrupt */
+ RTC_IRQn = 3, /*!< RTC global Interrupt */
+ FLASH_IRQn = 4, /*!< FLASH global Interrupt */
+ RCC_IRQn = 5, /*!< RCC global Interrupt */
+ EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */
+ EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */
+ EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */
+ EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */
+ EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */
+ DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 global Interrupt */
+ DMA1_Channel2_IRQn = 12, /*!< DMA1 Channel 2 global Interrupt */
+ DMA1_Channel3_IRQn = 13, /*!< DMA1 Channel 3 global Interrupt */
+ DMA1_Channel4_IRQn = 14, /*!< DMA1 Channel 4 global Interrupt */
+ DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 global Interrupt */
+ DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 global Interrupt */
+ DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 global Interrupt */
+ ADC1_IRQn = 18, /*!< ADC1 global Interrupt */
+ USB_HP_IRQn = 19, /*!< USB Device High Priority */
+ USB_LP_IRQn = 20, /*!< USB Device Low Priority */
+ EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
+ TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
+ TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
+ I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
+ I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
+ SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
+ USART1_IRQn = 37, /*!< USART1 global Interrupt */
+ USART2_IRQn = 38, /*!< USART2 global Interrupt */
+ EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
+ RTC_Alarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */
+ USBWakeUp_IRQn = 42, /*!< USB Device WakeUp from suspend through EXTI Line Interrupt */
+} IRQn_Type;
+
+
+/**
+ * @}
+ */
+
+#include "core_cm3.h"
+#include "system_stm32f1xx.h"
+#include <stdint.h>
+
+/** @addtogroup Peripheral_registers_structures
+ * @{
+ */
+
+/**
+ * @brief Analog to Digital Converter
+ */
+
+typedef struct
+{
+ __IO uint32_t SR;
+ __IO uint32_t CR1;
+ __IO uint32_t CR2;
+ __IO uint32_t SMPR1;
+ __IO uint32_t SMPR2;
+ __IO uint32_t JOFR1;
+ __IO uint32_t JOFR2;
+ __IO uint32_t JOFR3;
+ __IO uint32_t JOFR4;
+ __IO uint32_t HTR;
+ __IO uint32_t LTR;
+ __IO uint32_t SQR1;
+ __IO uint32_t SQR2;
+ __IO uint32_t SQR3;
+ __IO uint32_t JSQR;
+ __IO uint32_t JDR1;
+ __IO uint32_t JDR2;
+ __IO uint32_t JDR3;
+ __IO uint32_t JDR4;
+ __IO uint32_t DR;
+} ADC_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t SR; /*!< ADC status register, used for ADC multimode (bits common to several ADC instances). Address offset: ADC1 base address */
+ __IO uint32_t CR1; /*!< ADC control register 1, used for ADC multimode (bits common to several ADC instances). Address offset: ADC1 base address + 0x04 */
+ __IO uint32_t CR2; /*!< ADC control register 2, used for ADC multimode (bits common to several ADC instances). Address offset: ADC1 base address + 0x08 */
+ uint32_t RESERVED[16];
+ __IO uint32_t DR; /*!< ADC data register, used for ADC multimode (bits common to several ADC instances). Address offset: ADC1 base address + 0x4C */
+} ADC_Common_TypeDef;
+
+/**
+ * @brief Backup Registers
+ */
+
+typedef struct
+{
+ uint32_t RESERVED0;
+ __IO uint32_t DR1;
+ __IO uint32_t DR2;
+ __IO uint32_t DR3;
+ __IO uint32_t DR4;
+ __IO uint32_t DR5;
+ __IO uint32_t DR6;
+ __IO uint32_t DR7;
+ __IO uint32_t DR8;
+ __IO uint32_t DR9;
+ __IO uint32_t DR10;
+ __IO uint32_t RTCCR;
+ __IO uint32_t CR;
+ __IO uint32_t CSR;
+} BKP_TypeDef;
+
+
+/**
+ * @brief CRC calculation unit
+ */
+
+typedef struct
+{
+ __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
+ __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
+ uint8_t RESERVED0; /*!< Reserved, Address offset: 0x05 */
+ uint16_t RESERVED1; /*!< Reserved, Address offset: 0x06 */
+ __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
+} CRC_TypeDef;
+
+
+/**
+ * @brief Debug MCU
+ */
+
+typedef struct
+{
+ __IO uint32_t IDCODE;
+ __IO uint32_t CR;
+}DBGMCU_TypeDef;
+
+/**
+ * @brief DMA Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t CCR;
+ __IO uint32_t CNDTR;
+ __IO uint32_t CPAR;
+ __IO uint32_t CMAR;
+} DMA_Channel_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t ISR;
+ __IO uint32_t IFCR;
+} DMA_TypeDef;
+
+
+
+/**
+ * @brief External Interrupt/Event Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t IMR;
+ __IO uint32_t EMR;
+ __IO uint32_t RTSR;
+ __IO uint32_t FTSR;
+ __IO uint32_t SWIER;
+ __IO uint32_t PR;
+} EXTI_TypeDef;
+
+/**
+ * @brief FLASH Registers
+ */
+
+typedef struct
+{
+ __IO uint32_t ACR;
+ __IO uint32_t KEYR;
+ __IO uint32_t OPTKEYR;
+ __IO uint32_t SR;
+ __IO uint32_t CR;
+ __IO uint32_t AR;
+ __IO uint32_t RESERVED;
+ __IO uint32_t OBR;
+ __IO uint32_t WRPR;
+} FLASH_TypeDef;
+
+/**
+ * @brief Option Bytes Registers
+ */
+
+typedef struct
+{
+ __IO uint16_t RDP;
+ __IO uint16_t USER;
+ __IO uint16_t Data0;
+ __IO uint16_t Data1;
+ __IO uint16_t WRP0;
+ __IO uint16_t WRP1;
+ __IO uint16_t WRP2;
+ __IO uint16_t WRP3;
+} OB_TypeDef;
+
+/**
+ * @brief General Purpose I/O
+ */
+
+typedef struct
+{
+ __IO uint32_t CRL;
+ __IO uint32_t CRH;
+ __IO uint32_t IDR;
+ __IO uint32_t ODR;
+ __IO uint32_t BSRR;
+ __IO uint32_t BRR;
+ __IO uint32_t LCKR;
+} GPIO_TypeDef;
+
+/**
+ * @brief Alternate Function I/O
+ */
+
+typedef struct
+{
+ __IO uint32_t EVCR;
+ __IO uint32_t MAPR;
+ __IO uint32_t EXTICR[4];
+ uint32_t RESERVED0;
+ __IO uint32_t MAPR2;
+} AFIO_TypeDef;
+/**
+ * @brief Inter Integrated Circuit Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t CR1;
+ __IO uint32_t CR2;
+ __IO uint32_t OAR1;
+ __IO uint32_t OAR2;
+ __IO uint32_t DR;
+ __IO uint32_t SR1;
+ __IO uint32_t SR2;
+ __IO uint32_t CCR;
+ __IO uint32_t TRISE;
+} I2C_TypeDef;
+
+/**
+ * @brief Independent WATCHDOG
+ */
+
+typedef struct
+{
+ __IO uint32_t KR; /*!< Key register, Address offset: 0x00 */
+ __IO uint32_t PR; /*!< Prescaler register, Address offset: 0x04 */
+ __IO uint32_t RLR; /*!< Reload register, Address offset: 0x08 */
+ __IO uint32_t SR; /*!< Status register, Address offset: 0x0C */
+} IWDG_TypeDef;
+
+/**
+ * @brief Power Control
+ */
+
+typedef struct
+{
+ __IO uint32_t CR;
+ __IO uint32_t CSR;
+} PWR_TypeDef;
+
+/**
+ * @brief Reset and Clock Control
+ */
+
+typedef struct
+{
+ __IO uint32_t CR;
+ __IO uint32_t CFGR;
+ __IO uint32_t CIR;
+ __IO uint32_t APB2RSTR;
+ __IO uint32_t APB1RSTR;
+ __IO uint32_t AHBENR;
+ __IO uint32_t APB2ENR;
+ __IO uint32_t APB1ENR;
+ __IO uint32_t BDCR;
+ __IO uint32_t CSR;
+
+
+} RCC_TypeDef;
+
+/**
+ * @brief Real-Time Clock
+ */
+
+typedef struct
+{
+ __IO uint32_t CRH;
+ __IO uint32_t CRL;
+ __IO uint32_t PRLH;
+ __IO uint32_t PRLL;
+ __IO uint32_t DIVH;
+ __IO uint32_t DIVL;
+ __IO uint32_t CNTH;
+ __IO uint32_t CNTL;
+ __IO uint32_t ALRH;
+ __IO uint32_t ALRL;
+} RTC_TypeDef;
+
+/**
+ * @brief SD host Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t POWER;
+ __IO uint32_t CLKCR;
+ __IO uint32_t ARG;
+ __IO uint32_t CMD;
+ __I uint32_t RESPCMD;
+ __I uint32_t RESP1;
+ __I uint32_t RESP2;
+ __I uint32_t RESP3;
+ __I uint32_t RESP4;
+ __IO uint32_t DTIMER;
+ __IO uint32_t DLEN;
+ __IO uint32_t DCTRL;
+ __I uint32_t DCOUNT;
+ __I uint32_t STA;
+ __IO uint32_t ICR;
+ __IO uint32_t MASK;
+ uint32_t RESERVED0[2];
+ __I uint32_t FIFOCNT;
+ uint32_t RESERVED1[13];
+ __IO uint32_t FIFO;
+} SDIO_TypeDef;
+
+/**
+ * @brief Serial Peripheral Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t CR1;
+ __IO uint32_t CR2;
+ __IO uint32_t SR;
+ __IO uint32_t DR;
+ __IO uint32_t CRCPR;
+ __IO uint32_t RXCRCR;
+ __IO uint32_t TXCRCR;
+ __IO uint32_t I2SCFGR;
+} SPI_TypeDef;
+
+/**
+ * @brief TIM Timers
+ */
+typedef struct
+{
+ __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
+ __IO uint32_t SMCR; /*!< TIM slave Mode Control register, Address offset: 0x08 */
+ __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
+ __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
+ __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
+ __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
+ __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
+ __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
+ __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
+ __IO uint32_t PSC; /*!< TIM prescaler register, Address offset: 0x28 */
+ __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
+ __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */
+ __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
+ __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
+ __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
+ __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
+ __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
+ __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
+ __IO uint32_t DMAR; /*!< TIM DMA address for full transfer register, Address offset: 0x4C */
+ __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */
+}TIM_TypeDef;
+
+
+/**
+ * @brief Universal Synchronous Asynchronous Receiver Transmitter
+ */
+
+typedef struct
+{
+ __IO uint32_t SR; /*!< USART Status register, Address offset: 0x00 */
+ __IO uint32_t DR; /*!< USART Data register, Address offset: 0x04 */
+ __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x08 */
+ __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x0C */
+ __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x10 */
+ __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x14 */
+ __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x18 */
+} USART_TypeDef;
+
+/**
+ * @brief Universal Serial Bus Full Speed Device
+ */
+
+typedef struct
+{
+ __IO uint16_t EP0R; /*!< USB Endpoint 0 register, Address offset: 0x00 */
+ __IO uint16_t RESERVED0; /*!< Reserved */
+ __IO uint16_t EP1R; /*!< USB Endpoint 1 register, Address offset: 0x04 */
+ __IO uint16_t RESERVED1; /*!< Reserved */
+ __IO uint16_t EP2R; /*!< USB Endpoint 2 register, Address offset: 0x08 */
+ __IO uint16_t RESERVED2; /*!< Reserved */
+ __IO uint16_t EP3R; /*!< USB Endpoint 3 register, Address offset: 0x0C */
+ __IO uint16_t RESERVED3; /*!< Reserved */
+ __IO uint16_t EP4R; /*!< USB Endpoint 4 register, Address offset: 0x10 */
+ __IO uint16_t RESERVED4; /*!< Reserved */
+ __IO uint16_t EP5R; /*!< USB Endpoint 5 register, Address offset: 0x14 */
+ __IO uint16_t RESERVED5; /*!< Reserved */
+ __IO uint16_t EP6R; /*!< USB Endpoint 6 register, Address offset: 0x18 */
+ __IO uint16_t RESERVED6; /*!< Reserved */
+ __IO uint16_t EP7R; /*!< USB Endpoint 7 register, Address offset: 0x1C */
+ __IO uint16_t RESERVED7[17]; /*!< Reserved */
+ __IO uint16_t CNTR; /*!< Control register, Address offset: 0x40 */
+ __IO uint16_t RESERVED8; /*!< Reserved */
+ __IO uint16_t ISTR; /*!< Interrupt status register, Address offset: 0x44 */
+ __IO uint16_t RESERVED9; /*!< Reserved */
+ __IO uint16_t FNR; /*!< Frame number register, Address offset: 0x48 */
+ __IO uint16_t RESERVEDA; /*!< Reserved */
+ __IO uint16_t DADDR; /*!< Device address register, Address offset: 0x4C */
+ __IO uint16_t RESERVEDB; /*!< Reserved */
+ __IO uint16_t BTABLE; /*!< Buffer Table address register, Address offset: 0x50 */
+ __IO uint16_t RESERVEDC; /*!< Reserved */
+} USB_TypeDef;
+
+
+/**
+ * @brief Window WATCHDOG
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
+ __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
+ __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
+} WWDG_TypeDef;
+
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_memory_map
+ * @{
+ */
+
+
+#define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH base address in the alias region */
+#define FLASH_BANK1_END ((uint32_t)0x08007FFF) /*!< FLASH END address of bank1 */
+#define SRAM_BASE ((uint32_t)0x20000000) /*!< SRAM base address in the alias region */
+#define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */
+
+#define SRAM_BB_BASE ((uint32_t)0x22000000) /*!< SRAM base address in the bit-band region */
+#define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */
+
+
+/*!< Peripheral memory map */
+#define APB1PERIPH_BASE PERIPH_BASE
+#define APB2PERIPH_BASE (PERIPH_BASE + 0x10000)
+#define AHBPERIPH_BASE (PERIPH_BASE + 0x20000)
+
+#define TIM2_BASE (APB1PERIPH_BASE + 0x0000)
+#define TIM3_BASE (APB1PERIPH_BASE + 0x0400)
+#define RTC_BASE (APB1PERIPH_BASE + 0x2800)
+#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00)
+#define IWDG_BASE (APB1PERIPH_BASE + 0x3000)
+#define USART2_BASE (APB1PERIPH_BASE + 0x4400)
+#define I2C1_BASE (APB1PERIPH_BASE + 0x5400)
+#define BKP_BASE (APB1PERIPH_BASE + 0x6C00)
+#define PWR_BASE (APB1PERIPH_BASE + 0x7000)
+#define AFIO_BASE (APB2PERIPH_BASE + 0x0000)
+#define EXTI_BASE (APB2PERIPH_BASE + 0x0400)
+#define GPIOA_BASE (APB2PERIPH_BASE + 0x0800)
+#define GPIOB_BASE (APB2PERIPH_BASE + 0x0C00)
+#define GPIOC_BASE (APB2PERIPH_BASE + 0x1000)
+#define GPIOD_BASE (APB2PERIPH_BASE + 0x1400)
+#define ADC1_BASE (APB2PERIPH_BASE + 0x2400)
+#define SPI1_BASE (APB2PERIPH_BASE + 0x3000)
+#define USART1_BASE (APB2PERIPH_BASE + 0x3800)
+
+#define SDIO_BASE (PERIPH_BASE + 0x18000)
+
+#define DMA1_BASE (AHBPERIPH_BASE + 0x0000)
+#define DMA1_Channel1_BASE (AHBPERIPH_BASE + 0x0008)
+#define DMA1_Channel2_BASE (AHBPERIPH_BASE + 0x001C)
+#define DMA1_Channel3_BASE (AHBPERIPH_BASE + 0x0030)
+#define DMA1_Channel4_BASE (AHBPERIPH_BASE + 0x0044)
+#define DMA1_Channel5_BASE (AHBPERIPH_BASE + 0x0058)
+#define DMA1_Channel6_BASE (AHBPERIPH_BASE + 0x006C)
+#define DMA1_Channel7_BASE (AHBPERIPH_BASE + 0x0080)
+#define RCC_BASE (AHBPERIPH_BASE + 0x1000)
+#define CRC_BASE (AHBPERIPH_BASE + 0x3000)
+
+#define FLASH_R_BASE (AHBPERIPH_BASE + 0x2000) /*!< Flash registers base address */
+#define FLASHSIZE_BASE ((uint32_t)0x1FFFF7E0) /*!< FLASH Size register base address */
+#define UID_BASE ((uint32_t)0x1FFFF7E8) /*!< Unique device ID register base address */
+#define OB_BASE ((uint32_t)0x1FFFF800) /*!< Flash Option Bytes base address */
+
+
+
+#define DBGMCU_BASE ((uint32_t)0xE0042000) /*!< Debug MCU registers base address */
+
+/* USB device FS */
+#define USB_BASE (APB1PERIPH_BASE + 0x00005C00) /*!< USB_IP Peripheral Registers base address */
+#define USB_PMAADDR (APB1PERIPH_BASE + 0x00006000) /*!< USB_IP Packet Memory Area base address */
+
+
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_declaration
+ * @{
+ */
+
+#define TIM2 ((TIM_TypeDef *) TIM2_BASE)
+#define TIM3 ((TIM_TypeDef *) TIM3_BASE)
+#define RTC ((RTC_TypeDef *) RTC_BASE)
+#define WWDG ((WWDG_TypeDef *) WWDG_BASE)
+#define IWDG ((IWDG_TypeDef *) IWDG_BASE)
+#define USART2 ((USART_TypeDef *) USART2_BASE)
+#define I2C1 ((I2C_TypeDef *) I2C1_BASE)
+#define USB ((USB_TypeDef *) USB_BASE)
+#define BKP ((BKP_TypeDef *) BKP_BASE)
+#define PWR ((PWR_TypeDef *) PWR_BASE)
+#define AFIO ((AFIO_TypeDef *) AFIO_BASE)
+#define EXTI ((EXTI_TypeDef *) EXTI_BASE)
+#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
+#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
+#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
+#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
+#define ADC1 ((ADC_TypeDef *) ADC1_BASE)
+#define ADC1_COMMON ((ADC_Common_TypeDef *) ADC1_BASE)
+#define SPI1 ((SPI_TypeDef *) SPI1_BASE)
+#define USART1 ((USART_TypeDef *) USART1_BASE)
+#define SDIO ((SDIO_TypeDef *) SDIO_BASE)
+#define DMA1 ((DMA_TypeDef *) DMA1_BASE)
+#define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
+#define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
+#define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
+#define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
+#define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
+#define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
+#define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
+#define RCC ((RCC_TypeDef *) RCC_BASE)
+#define CRC ((CRC_TypeDef *) CRC_BASE)
+#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
+#define OB ((OB_TypeDef *) OB_BASE)
+#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
+
+
+/**
+ * @}
+ */
+
+/** @addtogroup Exported_constants
+ * @{
+ */
+
+ /** @addtogroup Peripheral_Registers_Bits_Definition
+ * @{
+ */
+
+/******************************************************************************/
+/* Peripheral Registers_Bits_Definition */
+/******************************************************************************/
+
+/******************************************************************************/
+/* */
+/* CRC calculation unit (CRC) */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for CRC_DR register *********************/
+#define CRC_DR_DR_Pos (0U)
+#define CRC_DR_DR_Msk (0xFFFFFFFFU << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */
+#define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */
+
+/******************* Bit definition for CRC_IDR register ********************/
+#define CRC_IDR_IDR_Pos (0U)
+#define CRC_IDR_IDR_Msk (0xFFU << CRC_IDR_IDR_Pos) /*!< 0x000000FF */
+#define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 8-bit data register bits */
+
+/******************** Bit definition for CRC_CR register ********************/
+#define CRC_CR_RESET_Pos (0U)
+#define CRC_CR_RESET_Msk (0x1U << CRC_CR_RESET_Pos) /*!< 0x00000001 */
+#define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET bit */
+
+/******************************************************************************/
+/* */
+/* Power Control */
+/* */
+/******************************************************************************/
+
+/******************** Bit definition for PWR_CR register ********************/
+#define PWR_CR_LPDS_Pos (0U)
+#define PWR_CR_LPDS_Msk (0x1U << PWR_CR_LPDS_Pos) /*!< 0x00000001 */
+#define PWR_CR_LPDS PWR_CR_LPDS_Msk /*!< Low-Power Deepsleep */
+#define PWR_CR_PDDS_Pos (1U)
+#define PWR_CR_PDDS_Msk (0x1U << PWR_CR_PDDS_Pos) /*!< 0x00000002 */
+#define PWR_CR_PDDS PWR_CR_PDDS_Msk /*!< Power Down Deepsleep */
+#define PWR_CR_CWUF_Pos (2U)
+#define PWR_CR_CWUF_Msk (0x1U << PWR_CR_CWUF_Pos) /*!< 0x00000004 */
+#define PWR_CR_CWUF PWR_CR_CWUF_Msk /*!< Clear Wakeup Flag */
+#define PWR_CR_CSBF_Pos (3U)
+#define PWR_CR_CSBF_Msk (0x1U << PWR_CR_CSBF_Pos) /*!< 0x00000008 */
+#define PWR_CR_CSBF PWR_CR_CSBF_Msk /*!< Clear Standby Flag */
+#define PWR_CR_PVDE_Pos (4U)
+#define PWR_CR_PVDE_Msk (0x1U << PWR_CR_PVDE_Pos) /*!< 0x00000010 */
+#define PWR_CR_PVDE PWR_CR_PVDE_Msk /*!< Power Voltage Detector Enable */
+
+#define PWR_CR_PLS_Pos (5U)
+#define PWR_CR_PLS_Msk (0x7U << PWR_CR_PLS_Pos) /*!< 0x000000E0 */
+#define PWR_CR_PLS PWR_CR_PLS_Msk /*!< PLS[2:0] bits (PVD Level Selection) */
+#define PWR_CR_PLS_0 (0x1U << PWR_CR_PLS_Pos) /*!< 0x00000020 */
+#define PWR_CR_PLS_1 (0x2U << PWR_CR_PLS_Pos) /*!< 0x00000040 */
+#define PWR_CR_PLS_2 (0x4U << PWR_CR_PLS_Pos) /*!< 0x00000080 */
+
+/*!< PVD level configuration */
+#define PWR_CR_PLS_2V2 ((uint32_t)0x00000000) /*!< PVD level 2.2V */
+#define PWR_CR_PLS_2V3 ((uint32_t)0x00000020) /*!< PVD level 2.3V */
+#define PWR_CR_PLS_2V4 ((uint32_t)0x00000040) /*!< PVD level 2.4V */
+#define PWR_CR_PLS_2V5 ((uint32_t)0x00000060) /*!< PVD level 2.5V */
+#define PWR_CR_PLS_2V6 ((uint32_t)0x00000080) /*!< PVD level 2.6V */
+#define PWR_CR_PLS_2V7 ((uint32_t)0x000000A0) /*!< PVD level 2.7V */
+#define PWR_CR_PLS_2V8 ((uint32_t)0x000000C0) /*!< PVD level 2.8V */
+#define PWR_CR_PLS_2V9 ((uint32_t)0x000000E0) /*!< PVD level 2.9V */
+
+#define PWR_CR_DBP_Pos (8U)
+#define PWR_CR_DBP_Msk (0x1U << PWR_CR_DBP_Pos) /*!< 0x00000100 */
+#define PWR_CR_DBP PWR_CR_DBP_Msk /*!< Disable Backup Domain write protection */
+
+
+/******************* Bit definition for PWR_CSR register ********************/
+#define PWR_CSR_WUF_Pos (0U)
+#define PWR_CSR_WUF_Msk (0x1U << PWR_CSR_WUF_Pos) /*!< 0x00000001 */
+#define PWR_CSR_WUF PWR_CSR_WUF_Msk /*!< Wakeup Flag */
+#define PWR_CSR_SBF_Pos (1U)
+#define PWR_CSR_SBF_Msk (0x1U << PWR_CSR_SBF_Pos) /*!< 0x00000002 */
+#define PWR_CSR_SBF PWR_CSR_SBF_Msk /*!< Standby Flag */
+#define PWR_CSR_PVDO_Pos (2U)
+#define PWR_CSR_PVDO_Msk (0x1U << PWR_CSR_PVDO_Pos) /*!< 0x00000004 */
+#define PWR_CSR_PVDO PWR_CSR_PVDO_Msk /*!< PVD Output */
+#define PWR_CSR_EWUP_Pos (8U)
+#define PWR_CSR_EWUP_Msk (0x1U << PWR_CSR_EWUP_Pos) /*!< 0x00000100 */
+#define PWR_CSR_EWUP PWR_CSR_EWUP_Msk /*!< Enable WKUP pin */
+
+/******************************************************************************/
+/* */
+/* Backup registers */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for BKP_DR1 register ********************/
+#define BKP_DR1_D_Pos (0U)
+#define BKP_DR1_D_Msk (0xFFFFU << BKP_DR1_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR1_D BKP_DR1_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR2 register ********************/
+#define BKP_DR2_D_Pos (0U)
+#define BKP_DR2_D_Msk (0xFFFFU << BKP_DR2_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR2_D BKP_DR2_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR3 register ********************/
+#define BKP_DR3_D_Pos (0U)
+#define BKP_DR3_D_Msk (0xFFFFU << BKP_DR3_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR3_D BKP_DR3_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR4 register ********************/
+#define BKP_DR4_D_Pos (0U)
+#define BKP_DR4_D_Msk (0xFFFFU << BKP_DR4_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR4_D BKP_DR4_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR5 register ********************/
+#define BKP_DR5_D_Pos (0U)
+#define BKP_DR5_D_Msk (0xFFFFU << BKP_DR5_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR5_D BKP_DR5_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR6 register ********************/
+#define BKP_DR6_D_Pos (0U)
+#define BKP_DR6_D_Msk (0xFFFFU << BKP_DR6_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR6_D BKP_DR6_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR7 register ********************/
+#define BKP_DR7_D_Pos (0U)
+#define BKP_DR7_D_Msk (0xFFFFU << BKP_DR7_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR7_D BKP_DR7_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR8 register ********************/
+#define BKP_DR8_D_Pos (0U)
+#define BKP_DR8_D_Msk (0xFFFFU << BKP_DR8_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR8_D BKP_DR8_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR9 register ********************/
+#define BKP_DR9_D_Pos (0U)
+#define BKP_DR9_D_Msk (0xFFFFU << BKP_DR9_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR9_D BKP_DR9_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR10 register *******************/
+#define BKP_DR10_D_Pos (0U)
+#define BKP_DR10_D_Msk (0xFFFFU << BKP_DR10_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR10_D BKP_DR10_D_Msk /*!< Backup data */
+
+#define RTC_BKP_NUMBER 10
+
+/****************** Bit definition for BKP_RTCCR register *******************/
+#define BKP_RTCCR_CAL_Pos (0U)
+#define BKP_RTCCR_CAL_Msk (0x7FU << BKP_RTCCR_CAL_Pos) /*!< 0x0000007F */
+#define BKP_RTCCR_CAL BKP_RTCCR_CAL_Msk /*!< Calibration value */
+#define BKP_RTCCR_CCO_Pos (7U)
+#define BKP_RTCCR_CCO_Msk (0x1U << BKP_RTCCR_CCO_Pos) /*!< 0x00000080 */
+#define BKP_RTCCR_CCO BKP_RTCCR_CCO_Msk /*!< Calibration Clock Output */
+#define BKP_RTCCR_ASOE_Pos (8U)
+#define BKP_RTCCR_ASOE_Msk (0x1U << BKP_RTCCR_ASOE_Pos) /*!< 0x00000100 */
+#define BKP_RTCCR_ASOE BKP_RTCCR_ASOE_Msk /*!< Alarm or Second Output Enable */
+#define BKP_RTCCR_ASOS_Pos (9U)
+#define BKP_RTCCR_ASOS_Msk (0x1U << BKP_RTCCR_ASOS_Pos) /*!< 0x00000200 */
+#define BKP_RTCCR_ASOS BKP_RTCCR_ASOS_Msk /*!< Alarm or Second Output Selection */
+
+/******************** Bit definition for BKP_CR register ********************/
+#define BKP_CR_TPE_Pos (0U)
+#define BKP_CR_TPE_Msk (0x1U << BKP_CR_TPE_Pos) /*!< 0x00000001 */
+#define BKP_CR_TPE BKP_CR_TPE_Msk /*!< TAMPER pin enable */
+#define BKP_CR_TPAL_Pos (1U)
+#define BKP_CR_TPAL_Msk (0x1U << BKP_CR_TPAL_Pos) /*!< 0x00000002 */
+#define BKP_CR_TPAL BKP_CR_TPAL_Msk /*!< TAMPER pin active level */
+
+/******************* Bit definition for BKP_CSR register ********************/
+#define BKP_CSR_CTE_Pos (0U)
+#define BKP_CSR_CTE_Msk (0x1U << BKP_CSR_CTE_Pos) /*!< 0x00000001 */
+#define BKP_CSR_CTE BKP_CSR_CTE_Msk /*!< Clear Tamper event */
+#define BKP_CSR_CTI_Pos (1U)
+#define BKP_CSR_CTI_Msk (0x1U << BKP_CSR_CTI_Pos) /*!< 0x00000002 */
+#define BKP_CSR_CTI BKP_CSR_CTI_Msk /*!< Clear Tamper Interrupt */
+#define BKP_CSR_TPIE_Pos (2U)
+#define BKP_CSR_TPIE_Msk (0x1U << BKP_CSR_TPIE_Pos) /*!< 0x00000004 */
+#define BKP_CSR_TPIE BKP_CSR_TPIE_Msk /*!< TAMPER Pin interrupt enable */
+#define BKP_CSR_TEF_Pos (8U)
+#define BKP_CSR_TEF_Msk (0x1U << BKP_CSR_TEF_Pos) /*!< 0x00000100 */
+#define BKP_CSR_TEF BKP_CSR_TEF_Msk /*!< Tamper Event Flag */
+#define BKP_CSR_TIF_Pos (9U)
+#define BKP_CSR_TIF_Msk (0x1U << BKP_CSR_TIF_Pos) /*!< 0x00000200 */
+#define BKP_CSR_TIF BKP_CSR_TIF_Msk /*!< Tamper Interrupt Flag */
+
+/******************************************************************************/
+/* */
+/* Reset and Clock Control */
+/* */
+/******************************************************************************/
+
+/******************** Bit definition for RCC_CR register ********************/
+#define RCC_CR_HSION_Pos (0U)
+#define RCC_CR_HSION_Msk (0x1U << RCC_CR_HSION_Pos) /*!< 0x00000001 */
+#define RCC_CR_HSION RCC_CR_HSION_Msk /*!< Internal High Speed clock enable */
+#define RCC_CR_HSIRDY_Pos (1U)
+#define RCC_CR_HSIRDY_Msk (0x1U << RCC_CR_HSIRDY_Pos) /*!< 0x00000002 */
+#define RCC_CR_HSIRDY RCC_CR_HSIRDY_Msk /*!< Internal High Speed clock ready flag */
+#define RCC_CR_HSITRIM_Pos (3U)
+#define RCC_CR_HSITRIM_Msk (0x1FU << RCC_CR_HSITRIM_Pos) /*!< 0x000000F8 */
+#define RCC_CR_HSITRIM RCC_CR_HSITRIM_Msk /*!< Internal High Speed clock trimming */
+#define RCC_CR_HSICAL_Pos (8U)
+#define RCC_CR_HSICAL_Msk (0xFFU << RCC_CR_HSICAL_Pos) /*!< 0x0000FF00 */
+#define RCC_CR_HSICAL RCC_CR_HSICAL_Msk /*!< Internal High Speed clock Calibration */
+#define RCC_CR_HSEON_Pos (16U)
+#define RCC_CR_HSEON_Msk (0x1U << RCC_CR_HSEON_Pos) /*!< 0x00010000 */
+#define RCC_CR_HSEON RCC_CR_HSEON_Msk /*!< External High Speed clock enable */
+#define RCC_CR_HSERDY_Pos (17U)
+#define RCC_CR_HSERDY_Msk (0x1U << RCC_CR_HSERDY_Pos) /*!< 0x00020000 */
+#define RCC_CR_HSERDY RCC_CR_HSERDY_Msk /*!< External High Speed clock ready flag */
+#define RCC_CR_HSEBYP_Pos (18U)
+#define RCC_CR_HSEBYP_Msk (0x1U << RCC_CR_HSEBYP_Pos) /*!< 0x00040000 */
+#define RCC_CR_HSEBYP RCC_CR_HSEBYP_Msk /*!< External High Speed clock Bypass */
+#define RCC_CR_CSSON_Pos (19U)
+#define RCC_CR_CSSON_Msk (0x1U << RCC_CR_CSSON_Pos) /*!< 0x00080000 */
+#define RCC_CR_CSSON RCC_CR_CSSON_Msk /*!< Clock Security System enable */
+#define RCC_CR_PLLON_Pos (24U)
+#define RCC_CR_PLLON_Msk (0x1U << RCC_CR_PLLON_Pos) /*!< 0x01000000 */
+#define RCC_CR_PLLON RCC_CR_PLLON_Msk /*!< PLL enable */
+#define RCC_CR_PLLRDY_Pos (25U)
+#define RCC_CR_PLLRDY_Msk (0x1U << RCC_CR_PLLRDY_Pos) /*!< 0x02000000 */
+#define RCC_CR_PLLRDY RCC_CR_PLLRDY_Msk /*!< PLL clock ready flag */
+
+
+/******************* Bit definition for RCC_CFGR register *******************/
+/*!< SW configuration */
+#define RCC_CFGR_SW_Pos (0U)
+#define RCC_CFGR_SW_Msk (0x3U << RCC_CFGR_SW_Pos) /*!< 0x00000003 */
+#define RCC_CFGR_SW RCC_CFGR_SW_Msk /*!< SW[1:0] bits (System clock Switch) */
+#define RCC_CFGR_SW_0 (0x1U << RCC_CFGR_SW_Pos) /*!< 0x00000001 */
+#define RCC_CFGR_SW_1 (0x2U << RCC_CFGR_SW_Pos) /*!< 0x00000002 */
+
+#define RCC_CFGR_SW_HSI ((uint32_t)0x00000000) /*!< HSI selected as system clock */
+#define RCC_CFGR_SW_HSE ((uint32_t)0x00000001) /*!< HSE selected as system clock */
+#define RCC_CFGR_SW_PLL ((uint32_t)0x00000002) /*!< PLL selected as system clock */
+
+/*!< SWS configuration */
+#define RCC_CFGR_SWS_Pos (2U)
+#define RCC_CFGR_SWS_Msk (0x3U << RCC_CFGR_SWS_Pos) /*!< 0x0000000C */
+#define RCC_CFGR_SWS RCC_CFGR_SWS_Msk /*!< SWS[1:0] bits (System Clock Switch Status) */
+#define RCC_CFGR_SWS_0 (0x1U << RCC_CFGR_SWS_Pos) /*!< 0x00000004 */
+#define RCC_CFGR_SWS_1 (0x2U << RCC_CFGR_SWS_Pos) /*!< 0x00000008 */
+
+#define RCC_CFGR_SWS_HSI ((uint32_t)0x00000000) /*!< HSI oscillator used as system clock */
+#define RCC_CFGR_SWS_HSE ((uint32_t)0x00000004) /*!< HSE oscillator used as system clock */
+#define RCC_CFGR_SWS_PLL ((uint32_t)0x00000008) /*!< PLL used as system clock */
+
+/*!< HPRE configuration */
+#define RCC_CFGR_HPRE_Pos (4U)
+#define RCC_CFGR_HPRE_Msk (0xFU << RCC_CFGR_HPRE_Pos) /*!< 0x000000F0 */
+#define RCC_CFGR_HPRE RCC_CFGR_HPRE_Msk /*!< HPRE[3:0] bits (AHB prescaler) */
+#define RCC_CFGR_HPRE_0 (0x1U << RCC_CFGR_HPRE_Pos) /*!< 0x00000010 */
+#define RCC_CFGR_HPRE_1 (0x2U << RCC_CFGR_HPRE_Pos) /*!< 0x00000020 */
+#define RCC_CFGR_HPRE_2 (0x4U << RCC_CFGR_HPRE_Pos) /*!< 0x00000040 */
+#define RCC_CFGR_HPRE_3 (0x8U << RCC_CFGR_HPRE_Pos) /*!< 0x00000080 */
+
+#define RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000) /*!< SYSCLK not divided */
+#define RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080) /*!< SYSCLK divided by 2 */
+#define RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090) /*!< SYSCLK divided by 4 */
+#define RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0) /*!< SYSCLK divided by 8 */
+#define RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0) /*!< SYSCLK divided by 16 */
+#define RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0) /*!< SYSCLK divided by 64 */
+#define RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0) /*!< SYSCLK divided by 128 */
+#define RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0) /*!< SYSCLK divided by 256 */
+#define RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0) /*!< SYSCLK divided by 512 */
+
+/*!< PPRE1 configuration */
+#define RCC_CFGR_PPRE1_Pos (8U)
+#define RCC_CFGR_PPRE1_Msk (0x7U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000700 */
+#define RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_Msk /*!< PRE1[2:0] bits (APB1 prescaler) */
+#define RCC_CFGR_PPRE1_0 (0x1U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000100 */
+#define RCC_CFGR_PPRE1_1 (0x2U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000200 */
+#define RCC_CFGR_PPRE1_2 (0x4U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000400 */
+
+#define RCC_CFGR_PPRE1_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */
+#define RCC_CFGR_PPRE1_DIV2 ((uint32_t)0x00000400) /*!< HCLK divided by 2 */
+#define RCC_CFGR_PPRE1_DIV4 ((uint32_t)0x00000500) /*!< HCLK divided by 4 */
+#define RCC_CFGR_PPRE1_DIV8 ((uint32_t)0x00000600) /*!< HCLK divided by 8 */
+#define RCC_CFGR_PPRE1_DIV16 ((uint32_t)0x00000700) /*!< HCLK divided by 16 */
+
+/*!< PPRE2 configuration */
+#define RCC_CFGR_PPRE2_Pos (11U)
+#define RCC_CFGR_PPRE2_Msk (0x7U << RCC_CFGR_PPRE2_Pos) /*!< 0x00003800 */
+#define RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_Msk /*!< PRE2[2:0] bits (APB2 prescaler) */
+#define RCC_CFGR_PPRE2_0 (0x1U << RCC_CFGR_PPRE2_Pos) /*!< 0x00000800 */
+#define RCC_CFGR_PPRE2_1 (0x2U << RCC_CFGR_PPRE2_Pos) /*!< 0x00001000 */
+#define RCC_CFGR_PPRE2_2 (0x4U << RCC_CFGR_PPRE2_Pos) /*!< 0x00002000 */
+
+#define RCC_CFGR_PPRE2_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */
+#define RCC_CFGR_PPRE2_DIV2 ((uint32_t)0x00002000) /*!< HCLK divided by 2 */
+#define RCC_CFGR_PPRE2_DIV4 ((uint32_t)0x00002800) /*!< HCLK divided by 4 */
+#define RCC_CFGR_PPRE2_DIV8 ((uint32_t)0x00003000) /*!< HCLK divided by 8 */
+#define RCC_CFGR_PPRE2_DIV16 ((uint32_t)0x00003800) /*!< HCLK divided by 16 */
+
+/*!< ADCPPRE configuration */
+#define RCC_CFGR_ADCPRE_Pos (14U)
+#define RCC_CFGR_ADCPRE_Msk (0x3U << RCC_CFGR_ADCPRE_Pos) /*!< 0x0000C000 */
+#define RCC_CFGR_ADCPRE RCC_CFGR_ADCPRE_Msk /*!< ADCPRE[1:0] bits (ADC prescaler) */
+#define RCC_CFGR_ADCPRE_0 (0x1U << RCC_CFGR_ADCPRE_Pos) /*!< 0x00004000 */
+#define RCC_CFGR_ADCPRE_1 (0x2U << RCC_CFGR_ADCPRE_Pos) /*!< 0x00008000 */
+
+#define RCC_CFGR_ADCPRE_DIV2 ((uint32_t)0x00000000) /*!< PCLK2 divided by 2 */
+#define RCC_CFGR_ADCPRE_DIV4 ((uint32_t)0x00004000) /*!< PCLK2 divided by 4 */
+#define RCC_CFGR_ADCPRE_DIV6 ((uint32_t)0x00008000) /*!< PCLK2 divided by 6 */
+#define RCC_CFGR_ADCPRE_DIV8 ((uint32_t)0x0000C000) /*!< PCLK2 divided by 8 */
+
+#define RCC_CFGR_PLLSRC_Pos (16U)
+#define RCC_CFGR_PLLSRC_Msk (0x1U << RCC_CFGR_PLLSRC_Pos) /*!< 0x00010000 */
+#define RCC_CFGR_PLLSRC RCC_CFGR_PLLSRC_Msk /*!< PLL entry clock source */
+
+#define RCC_CFGR_PLLXTPRE_Pos (17U)
+#define RCC_CFGR_PLLXTPRE_Msk (0x1U << RCC_CFGR_PLLXTPRE_Pos) /*!< 0x00020000 */
+#define RCC_CFGR_PLLXTPRE RCC_CFGR_PLLXTPRE_Msk /*!< HSE divider for PLL entry */
+
+/*!< PLLMUL configuration */
+#define RCC_CFGR_PLLMULL_Pos (18U)
+#define RCC_CFGR_PLLMULL_Msk (0xFU << RCC_CFGR_PLLMULL_Pos) /*!< 0x003C0000 */
+#define RCC_CFGR_PLLMULL RCC_CFGR_PLLMULL_Msk /*!< PLLMUL[3:0] bits (PLL multiplication factor) */
+#define RCC_CFGR_PLLMULL_0 (0x1U << RCC_CFGR_PLLMULL_Pos) /*!< 0x00040000 */
+#define RCC_CFGR_PLLMULL_1 (0x2U << RCC_CFGR_PLLMULL_Pos) /*!< 0x00080000 */
+#define RCC_CFGR_PLLMULL_2 (0x4U << RCC_CFGR_PLLMULL_Pos) /*!< 0x00100000 */
+#define RCC_CFGR_PLLMULL_3 (0x8U << RCC_CFGR_PLLMULL_Pos) /*!< 0x00200000 */
+
+#define RCC_CFGR_PLLXTPRE_HSE ((uint32_t)0x00000000) /*!< HSE clock not divided for PLL entry */
+#define RCC_CFGR_PLLXTPRE_HSE_DIV2 ((uint32_t)0x00020000) /*!< HSE clock divided by 2 for PLL entry */
+
+#define RCC_CFGR_PLLMULL2 ((uint32_t)0x00000000) /*!< PLL input clock*2 */
+#define RCC_CFGR_PLLMULL3_Pos (18U)
+#define RCC_CFGR_PLLMULL3_Msk (0x1U << RCC_CFGR_PLLMULL3_Pos) /*!< 0x00040000 */
+#define RCC_CFGR_PLLMULL3 RCC_CFGR_PLLMULL3_Msk /*!< PLL input clock*3 */
+#define RCC_CFGR_PLLMULL4_Pos (19U)
+#define RCC_CFGR_PLLMULL4_Msk (0x1U << RCC_CFGR_PLLMULL4_Pos) /*!< 0x00080000 */
+#define RCC_CFGR_PLLMULL4 RCC_CFGR_PLLMULL4_Msk /*!< PLL input clock*4 */
+#define RCC_CFGR_PLLMULL5_Pos (18U)
+#define RCC_CFGR_PLLMULL5_Msk (0x3U << RCC_CFGR_PLLMULL5_Pos) /*!< 0x000C0000 */
+#define RCC_CFGR_PLLMULL5 RCC_CFGR_PLLMULL5_Msk /*!< PLL input clock*5 */
+#define RCC_CFGR_PLLMULL6_Pos (20U)
+#define RCC_CFGR_PLLMULL6_Msk (0x1U << RCC_CFGR_PLLMULL6_Pos) /*!< 0x00100000 */
+#define RCC_CFGR_PLLMULL6 RCC_CFGR_PLLMULL6_Msk /*!< PLL input clock*6 */
+#define RCC_CFGR_PLLMULL7_Pos (18U)
+#define RCC_CFGR_PLLMULL7_Msk (0x5U << RCC_CFGR_PLLMULL7_Pos) /*!< 0x00140000 */
+#define RCC_CFGR_PLLMULL7 RCC_CFGR_PLLMULL7_Msk /*!< PLL input clock*7 */
+#define RCC_CFGR_PLLMULL8_Pos (19U)
+#define RCC_CFGR_PLLMULL8_Msk (0x3U << RCC_CFGR_PLLMULL8_Pos) /*!< 0x00180000 */
+#define RCC_CFGR_PLLMULL8 RCC_CFGR_PLLMULL8_Msk /*!< PLL input clock*8 */
+#define RCC_CFGR_PLLMULL9_Pos (18U)
+#define RCC_CFGR_PLLMULL9_Msk (0x7U << RCC_CFGR_PLLMULL9_Pos) /*!< 0x001C0000 */
+#define RCC_CFGR_PLLMULL9 RCC_CFGR_PLLMULL9_Msk /*!< PLL input clock*9 */
+#define RCC_CFGR_PLLMULL10_Pos (21U)
+#define RCC_CFGR_PLLMULL10_Msk (0x1U << RCC_CFGR_PLLMULL10_Pos) /*!< 0x00200000 */
+#define RCC_CFGR_PLLMULL10 RCC_CFGR_PLLMULL10_Msk /*!< PLL input clock10 */
+#define RCC_CFGR_PLLMULL11_Pos (18U)
+#define RCC_CFGR_PLLMULL11_Msk (0x9U << RCC_CFGR_PLLMULL11_Pos) /*!< 0x00240000 */
+#define RCC_CFGR_PLLMULL11 RCC_CFGR_PLLMULL11_Msk /*!< PLL input clock*11 */
+#define RCC_CFGR_PLLMULL12_Pos (19U)
+#define RCC_CFGR_PLLMULL12_Msk (0x5U << RCC_CFGR_PLLMULL12_Pos) /*!< 0x00280000 */
+#define RCC_CFGR_PLLMULL12 RCC_CFGR_PLLMULL12_Msk /*!< PLL input clock*12 */
+#define RCC_CFGR_PLLMULL13_Pos (18U)
+#define RCC_CFGR_PLLMULL13_Msk (0xBU << RCC_CFGR_PLLMULL13_Pos) /*!< 0x002C0000 */
+#define RCC_CFGR_PLLMULL13 RCC_CFGR_PLLMULL13_Msk /*!< PLL input clock*13 */
+#define RCC_CFGR_PLLMULL14_Pos (20U)
+#define RCC_CFGR_PLLMULL14_Msk (0x3U << RCC_CFGR_PLLMULL14_Pos) /*!< 0x00300000 */
+#define RCC_CFGR_PLLMULL14 RCC_CFGR_PLLMULL14_Msk /*!< PLL input clock*14 */
+#define RCC_CFGR_PLLMULL15_Pos (18U)
+#define RCC_CFGR_PLLMULL15_Msk (0xDU << RCC_CFGR_PLLMULL15_Pos) /*!< 0x00340000 */
+#define RCC_CFGR_PLLMULL15 RCC_CFGR_PLLMULL15_Msk /*!< PLL input clock*15 */
+#define RCC_CFGR_PLLMULL16_Pos (19U)
+#define RCC_CFGR_PLLMULL16_Msk (0x7U << RCC_CFGR_PLLMULL16_Pos) /*!< 0x00380000 */
+#define RCC_CFGR_PLLMULL16 RCC_CFGR_PLLMULL16_Msk /*!< PLL input clock*16 */
+#define RCC_CFGR_USBPRE_Pos (22U)
+#define RCC_CFGR_USBPRE_Msk (0x1U << RCC_CFGR_USBPRE_Pos) /*!< 0x00400000 */
+#define RCC_CFGR_USBPRE RCC_CFGR_USBPRE_Msk /*!< USB Device prescaler */
+
+/*!< MCO configuration */
+#define RCC_CFGR_MCO_Pos (24U)
+#define RCC_CFGR_MCO_Msk (0x7U << RCC_CFGR_MCO_Pos) /*!< 0x07000000 */
+#define RCC_CFGR_MCO RCC_CFGR_MCO_Msk /*!< MCO[2:0] bits (Microcontroller Clock Output) */
+#define RCC_CFGR_MCO_0 (0x1U << RCC_CFGR_MCO_Pos) /*!< 0x01000000 */
+#define RCC_CFGR_MCO_1 (0x2U << RCC_CFGR_MCO_Pos) /*!< 0x02000000 */
+#define RCC_CFGR_MCO_2 (0x4U << RCC_CFGR_MCO_Pos) /*!< 0x04000000 */
+
+#define RCC_CFGR_MCO_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */
+#define RCC_CFGR_MCO_SYSCLK ((uint32_t)0x04000000) /*!< System clock selected as MCO source */
+#define RCC_CFGR_MCO_HSI ((uint32_t)0x05000000) /*!< HSI clock selected as MCO source */
+#define RCC_CFGR_MCO_HSE ((uint32_t)0x06000000) /*!< HSE clock selected as MCO source */
+#define RCC_CFGR_MCO_PLLCLK_DIV2 ((uint32_t)0x07000000) /*!< PLL clock divided by 2 selected as MCO source */
+
+ /* Reference defines */
+ #define RCC_CFGR_MCOSEL RCC_CFGR_MCO
+ #define RCC_CFGR_MCOSEL_0 RCC_CFGR_MCO_0
+ #define RCC_CFGR_MCOSEL_1 RCC_CFGR_MCO_1
+ #define RCC_CFGR_MCOSEL_2 RCC_CFGR_MCO_2
+ #define RCC_CFGR_MCOSEL_NOCLOCK RCC_CFGR_MCO_NOCLOCK
+ #define RCC_CFGR_MCOSEL_SYSCLK RCC_CFGR_MCO_SYSCLK
+ #define RCC_CFGR_MCOSEL_HSI RCC_CFGR_MCO_HSI
+ #define RCC_CFGR_MCOSEL_HSE RCC_CFGR_MCO_HSE
+ #define RCC_CFGR_MCOSEL_PLL_DIV2 RCC_CFGR_MCO_PLLCLK_DIV2
+
+/*!<****************** Bit definition for RCC_CIR register ********************/
+#define RCC_CIR_LSIRDYF_Pos (0U)
+#define RCC_CIR_LSIRDYF_Msk (0x1U << RCC_CIR_LSIRDYF_Pos) /*!< 0x00000001 */
+#define RCC_CIR_LSIRDYF RCC_CIR_LSIRDYF_Msk /*!< LSI Ready Interrupt flag */
+#define RCC_CIR_LSERDYF_Pos (1U)
+#define RCC_CIR_LSERDYF_Msk (0x1U << RCC_CIR_LSERDYF_Pos) /*!< 0x00000002 */
+#define RCC_CIR_LSERDYF RCC_CIR_LSERDYF_Msk /*!< LSE Ready Interrupt flag */
+#define RCC_CIR_HSIRDYF_Pos (2U)
+#define RCC_CIR_HSIRDYF_Msk (0x1U << RCC_CIR_HSIRDYF_Pos) /*!< 0x00000004 */
+#define RCC_CIR_HSIRDYF RCC_CIR_HSIRDYF_Msk /*!< HSI Ready Interrupt flag */
+#define RCC_CIR_HSERDYF_Pos (3U)
+#define RCC_CIR_HSERDYF_Msk (0x1U << RCC_CIR_HSERDYF_Pos) /*!< 0x00000008 */
+#define RCC_CIR_HSERDYF RCC_CIR_HSERDYF_Msk /*!< HSE Ready Interrupt flag */
+#define RCC_CIR_PLLRDYF_Pos (4U)
+#define RCC_CIR_PLLRDYF_Msk (0x1U << RCC_CIR_PLLRDYF_Pos) /*!< 0x00000010 */
+#define RCC_CIR_PLLRDYF RCC_CIR_PLLRDYF_Msk /*!< PLL Ready Interrupt flag */
+#define RCC_CIR_CSSF_Pos (7U)
+#define RCC_CIR_CSSF_Msk (0x1U << RCC_CIR_CSSF_Pos) /*!< 0x00000080 */
+#define RCC_CIR_CSSF RCC_CIR_CSSF_Msk /*!< Clock Security System Interrupt flag */
+#define RCC_CIR_LSIRDYIE_Pos (8U)
+#define RCC_CIR_LSIRDYIE_Msk (0x1U << RCC_CIR_LSIRDYIE_Pos) /*!< 0x00000100 */
+#define RCC_CIR_LSIRDYIE RCC_CIR_LSIRDYIE_Msk /*!< LSI Ready Interrupt Enable */
+#define RCC_CIR_LSERDYIE_Pos (9U)
+#define RCC_CIR_LSERDYIE_Msk (0x1U << RCC_CIR_LSERDYIE_Pos) /*!< 0x00000200 */
+#define RCC_CIR_LSERDYIE RCC_CIR_LSERDYIE_Msk /*!< LSE Ready Interrupt Enable */
+#define RCC_CIR_HSIRDYIE_Pos (10U)
+#define RCC_CIR_HSIRDYIE_Msk (0x1U << RCC_CIR_HSIRDYIE_Pos) /*!< 0x00000400 */
+#define RCC_CIR_HSIRDYIE RCC_CIR_HSIRDYIE_Msk /*!< HSI Ready Interrupt Enable */
+#define RCC_CIR_HSERDYIE_Pos (11U)
+#define RCC_CIR_HSERDYIE_Msk (0x1U << RCC_CIR_HSERDYIE_Pos) /*!< 0x00000800 */
+#define RCC_CIR_HSERDYIE RCC_CIR_HSERDYIE_Msk /*!< HSE Ready Interrupt Enable */
+#define RCC_CIR_PLLRDYIE_Pos (12U)
+#define RCC_CIR_PLLRDYIE_Msk (0x1U << RCC_CIR_PLLRDYIE_Pos) /*!< 0x00001000 */
+#define RCC_CIR_PLLRDYIE RCC_CIR_PLLRDYIE_Msk /*!< PLL Ready Interrupt Enable */
+#define RCC_CIR_LSIRDYC_Pos (16U)
+#define RCC_CIR_LSIRDYC_Msk (0x1U << RCC_CIR_LSIRDYC_Pos) /*!< 0x00010000 */
+#define RCC_CIR_LSIRDYC RCC_CIR_LSIRDYC_Msk /*!< LSI Ready Interrupt Clear */
+#define RCC_CIR_LSERDYC_Pos (17U)
+#define RCC_CIR_LSERDYC_Msk (0x1U << RCC_CIR_LSERDYC_Pos) /*!< 0x00020000 */
+#define RCC_CIR_LSERDYC RCC_CIR_LSERDYC_Msk /*!< LSE Ready Interrupt Clear */
+#define RCC_CIR_HSIRDYC_Pos (18U)
+#define RCC_CIR_HSIRDYC_Msk (0x1U << RCC_CIR_HSIRDYC_Pos) /*!< 0x00040000 */
+#define RCC_CIR_HSIRDYC RCC_CIR_HSIRDYC_Msk /*!< HSI Ready Interrupt Clear */
+#define RCC_CIR_HSERDYC_Pos (19U)
+#define RCC_CIR_HSERDYC_Msk (0x1U << RCC_CIR_HSERDYC_Pos) /*!< 0x00080000 */
+#define RCC_CIR_HSERDYC RCC_CIR_HSERDYC_Msk /*!< HSE Ready Interrupt Clear */
+#define RCC_CIR_PLLRDYC_Pos (20U)
+#define RCC_CIR_PLLRDYC_Msk (0x1U << RCC_CIR_PLLRDYC_Pos) /*!< 0x00100000 */
+#define RCC_CIR_PLLRDYC RCC_CIR_PLLRDYC_Msk /*!< PLL Ready Interrupt Clear */
+#define RCC_CIR_CSSC_Pos (23U)
+#define RCC_CIR_CSSC_Msk (0x1U << RCC_CIR_CSSC_Pos) /*!< 0x00800000 */
+#define RCC_CIR_CSSC RCC_CIR_CSSC_Msk /*!< Clock Security System Interrupt Clear */
+
+
+/***************** Bit definition for RCC_APB2RSTR register *****************/
+#define RCC_APB2RSTR_AFIORST_Pos (0U)
+#define RCC_APB2RSTR_AFIORST_Msk (0x1U << RCC_APB2RSTR_AFIORST_Pos) /*!< 0x00000001 */
+#define RCC_APB2RSTR_AFIORST RCC_APB2RSTR_AFIORST_Msk /*!< Alternate Function I/O reset */
+#define RCC_APB2RSTR_IOPARST_Pos (2U)
+#define RCC_APB2RSTR_IOPARST_Msk (0x1U << RCC_APB2RSTR_IOPARST_Pos) /*!< 0x00000004 */
+#define RCC_APB2RSTR_IOPARST RCC_APB2RSTR_IOPARST_Msk /*!< I/O port A reset */
+#define RCC_APB2RSTR_IOPBRST_Pos (3U)
+#define RCC_APB2RSTR_IOPBRST_Msk (0x1U << RCC_APB2RSTR_IOPBRST_Pos) /*!< 0x00000008 */
+#define RCC_APB2RSTR_IOPBRST RCC_APB2RSTR_IOPBRST_Msk /*!< I/O port B reset */
+#define RCC_APB2RSTR_IOPCRST_Pos (4U)
+#define RCC_APB2RSTR_IOPCRST_Msk (0x1U << RCC_APB2RSTR_IOPCRST_Pos) /*!< 0x00000010 */
+#define RCC_APB2RSTR_IOPCRST RCC_APB2RSTR_IOPCRST_Msk /*!< I/O port C reset */
+#define RCC_APB2RSTR_IOPDRST_Pos (5U)
+#define RCC_APB2RSTR_IOPDRST_Msk (0x1U << RCC_APB2RSTR_IOPDRST_Pos) /*!< 0x00000020 */
+#define RCC_APB2RSTR_IOPDRST RCC_APB2RSTR_IOPDRST_Msk /*!< I/O port D reset */
+#define RCC_APB2RSTR_ADC1RST_Pos (9U)
+#define RCC_APB2RSTR_ADC1RST_Msk (0x1U << RCC_APB2RSTR_ADC1RST_Pos) /*!< 0x00000200 */
+#define RCC_APB2RSTR_ADC1RST RCC_APB2RSTR_ADC1RST_Msk /*!< ADC 1 interface reset */
+
+
+#define RCC_APB2RSTR_TIM1RST_Pos (11U)
+#define RCC_APB2RSTR_TIM1RST_Msk (0x1U << RCC_APB2RSTR_TIM1RST_Pos) /*!< 0x00000800 */
+#define RCC_APB2RSTR_TIM1RST RCC_APB2RSTR_TIM1RST_Msk /*!< TIM1 Timer reset */
+#define RCC_APB2RSTR_SPI1RST_Pos (12U)
+#define RCC_APB2RSTR_SPI1RST_Msk (0x1U << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */
+#define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk /*!< SPI 1 reset */
+#define RCC_APB2RSTR_USART1RST_Pos (14U)
+#define RCC_APB2RSTR_USART1RST_Msk (0x1U << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00004000 */
+#define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk /*!< USART1 reset */
+
+
+
+
+
+
+/***************** Bit definition for RCC_APB1RSTR register *****************/
+#define RCC_APB1RSTR_TIM2RST_Pos (0U)
+#define RCC_APB1RSTR_TIM2RST_Msk (0x1U << RCC_APB1RSTR_TIM2RST_Pos) /*!< 0x00000001 */
+#define RCC_APB1RSTR_TIM2RST RCC_APB1RSTR_TIM2RST_Msk /*!< Timer 2 reset */
+#define RCC_APB1RSTR_TIM3RST_Pos (1U)
+#define RCC_APB1RSTR_TIM3RST_Msk (0x1U << RCC_APB1RSTR_TIM3RST_Pos) /*!< 0x00000002 */
+#define RCC_APB1RSTR_TIM3RST RCC_APB1RSTR_TIM3RST_Msk /*!< Timer 3 reset */
+#define RCC_APB1RSTR_WWDGRST_Pos (11U)
+#define RCC_APB1RSTR_WWDGRST_Msk (0x1U << RCC_APB1RSTR_WWDGRST_Pos) /*!< 0x00000800 */
+#define RCC_APB1RSTR_WWDGRST RCC_APB1RSTR_WWDGRST_Msk /*!< Window Watchdog reset */
+#define RCC_APB1RSTR_USART2RST_Pos (17U)
+#define RCC_APB1RSTR_USART2RST_Msk (0x1U << RCC_APB1RSTR_USART2RST_Pos) /*!< 0x00020000 */
+#define RCC_APB1RSTR_USART2RST RCC_APB1RSTR_USART2RST_Msk /*!< USART 2 reset */
+#define RCC_APB1RSTR_I2C1RST_Pos (21U)
+#define RCC_APB1RSTR_I2C1RST_Msk (0x1U << RCC_APB1RSTR_I2C1RST_Pos) /*!< 0x00200000 */
+#define RCC_APB1RSTR_I2C1RST RCC_APB1RSTR_I2C1RST_Msk /*!< I2C 1 reset */
+
+
+#define RCC_APB1RSTR_BKPRST_Pos (27U)
+#define RCC_APB1RSTR_BKPRST_Msk (0x1U << RCC_APB1RSTR_BKPRST_Pos) /*!< 0x08000000 */
+#define RCC_APB1RSTR_BKPRST RCC_APB1RSTR_BKPRST_Msk /*!< Backup interface reset */
+#define RCC_APB1RSTR_PWRRST_Pos (28U)
+#define RCC_APB1RSTR_PWRRST_Msk (0x1U << RCC_APB1RSTR_PWRRST_Pos) /*!< 0x10000000 */
+#define RCC_APB1RSTR_PWRRST RCC_APB1RSTR_PWRRST_Msk /*!< Power interface reset */
+
+
+#define RCC_APB1RSTR_USBRST_Pos (23U)
+#define RCC_APB1RSTR_USBRST_Msk (0x1U << RCC_APB1RSTR_USBRST_Pos) /*!< 0x00800000 */
+#define RCC_APB1RSTR_USBRST RCC_APB1RSTR_USBRST_Msk /*!< USB Device reset */
+
+
+
+
+
+
+/****************** Bit definition for RCC_AHBENR register ******************/
+#define RCC_AHBENR_DMA1EN_Pos (0U)
+#define RCC_AHBENR_DMA1EN_Msk (0x1U << RCC_AHBENR_DMA1EN_Pos) /*!< 0x00000001 */
+#define RCC_AHBENR_DMA1EN RCC_AHBENR_DMA1EN_Msk /*!< DMA1 clock enable */
+#define RCC_AHBENR_SRAMEN_Pos (2U)
+#define RCC_AHBENR_SRAMEN_Msk (0x1U << RCC_AHBENR_SRAMEN_Pos) /*!< 0x00000004 */
+#define RCC_AHBENR_SRAMEN RCC_AHBENR_SRAMEN_Msk /*!< SRAM interface clock enable */
+#define RCC_AHBENR_FLITFEN_Pos (4U)
+#define RCC_AHBENR_FLITFEN_Msk (0x1U << RCC_AHBENR_FLITFEN_Pos) /*!< 0x00000010 */
+#define RCC_AHBENR_FLITFEN RCC_AHBENR_FLITFEN_Msk /*!< FLITF clock enable */
+#define RCC_AHBENR_CRCEN_Pos (6U)
+#define RCC_AHBENR_CRCEN_Msk (0x1U << RCC_AHBENR_CRCEN_Pos) /*!< 0x00000040 */
+#define RCC_AHBENR_CRCEN RCC_AHBENR_CRCEN_Msk /*!< CRC clock enable */
+
+
+
+
+/****************** Bit definition for RCC_APB2ENR register *****************/
+#define RCC_APB2ENR_AFIOEN_Pos (0U)
+#define RCC_APB2ENR_AFIOEN_Msk (0x1U << RCC_APB2ENR_AFIOEN_Pos) /*!< 0x00000001 */
+#define RCC_APB2ENR_AFIOEN RCC_APB2ENR_AFIOEN_Msk /*!< Alternate Function I/O clock enable */
+#define RCC_APB2ENR_IOPAEN_Pos (2U)
+#define RCC_APB2ENR_IOPAEN_Msk (0x1U << RCC_APB2ENR_IOPAEN_Pos) /*!< 0x00000004 */
+#define RCC_APB2ENR_IOPAEN RCC_APB2ENR_IOPAEN_Msk /*!< I/O port A clock enable */
+#define RCC_APB2ENR_IOPBEN_Pos (3U)
+#define RCC_APB2ENR_IOPBEN_Msk (0x1U << RCC_APB2ENR_IOPBEN_Pos) /*!< 0x00000008 */
+#define RCC_APB2ENR_IOPBEN RCC_APB2ENR_IOPBEN_Msk /*!< I/O port B clock enable */
+#define RCC_APB2ENR_IOPCEN_Pos (4U)
+#define RCC_APB2ENR_IOPCEN_Msk (0x1U << RCC_APB2ENR_IOPCEN_Pos) /*!< 0x00000010 */
+#define RCC_APB2ENR_IOPCEN RCC_APB2ENR_IOPCEN_Msk /*!< I/O port C clock enable */
+#define RCC_APB2ENR_IOPDEN_Pos (5U)
+#define RCC_APB2ENR_IOPDEN_Msk (0x1U << RCC_APB2ENR_IOPDEN_Pos) /*!< 0x00000020 */
+#define RCC_APB2ENR_IOPDEN RCC_APB2ENR_IOPDEN_Msk /*!< I/O port D clock enable */
+#define RCC_APB2ENR_ADC1EN_Pos (9U)
+#define RCC_APB2ENR_ADC1EN_Msk (0x1U << RCC_APB2ENR_ADC1EN_Pos) /*!< 0x00000200 */
+#define RCC_APB2ENR_ADC1EN RCC_APB2ENR_ADC1EN_Msk /*!< ADC 1 interface clock enable */
+
+
+#define RCC_APB2ENR_TIM1EN_Pos (11U)
+#define RCC_APB2ENR_TIM1EN_Msk (0x1U << RCC_APB2ENR_TIM1EN_Pos) /*!< 0x00000800 */
+#define RCC_APB2ENR_TIM1EN RCC_APB2ENR_TIM1EN_Msk /*!< TIM1 Timer clock enable */
+#define RCC_APB2ENR_SPI1EN_Pos (12U)
+#define RCC_APB2ENR_SPI1EN_Msk (0x1U << RCC_APB2ENR_SPI1EN_Pos) /*!< 0x00001000 */
+#define RCC_APB2ENR_SPI1EN RCC_APB2ENR_SPI1EN_Msk /*!< SPI 1 clock enable */
+#define RCC_APB2ENR_USART1EN_Pos (14U)
+#define RCC_APB2ENR_USART1EN_Msk (0x1U << RCC_APB2ENR_USART1EN_Pos) /*!< 0x00004000 */
+#define RCC_APB2ENR_USART1EN RCC_APB2ENR_USART1EN_Msk /*!< USART1 clock enable */
+
+
+
+
+
+
+/***************** Bit definition for RCC_APB1ENR register ******************/
+#define RCC_APB1ENR_TIM2EN_Pos (0U)
+#define RCC_APB1ENR_TIM2EN_Msk (0x1U << RCC_APB1ENR_TIM2EN_Pos) /*!< 0x00000001 */
+#define RCC_APB1ENR_TIM2EN RCC_APB1ENR_TIM2EN_Msk /*!< Timer 2 clock enabled*/
+#define RCC_APB1ENR_TIM3EN_Pos (1U)
+#define RCC_APB1ENR_TIM3EN_Msk (0x1U << RCC_APB1ENR_TIM3EN_Pos) /*!< 0x00000002 */
+#define RCC_APB1ENR_TIM3EN RCC_APB1ENR_TIM3EN_Msk /*!< Timer 3 clock enable */
+#define RCC_APB1ENR_WWDGEN_Pos (11U)
+#define RCC_APB1ENR_WWDGEN_Msk (0x1U << RCC_APB1ENR_WWDGEN_Pos) /*!< 0x00000800 */
+#define RCC_APB1ENR_WWDGEN RCC_APB1ENR_WWDGEN_Msk /*!< Window Watchdog clock enable */
+#define RCC_APB1ENR_USART2EN_Pos (17U)
+#define RCC_APB1ENR_USART2EN_Msk (0x1U << RCC_APB1ENR_USART2EN_Pos) /*!< 0x00020000 */
+#define RCC_APB1ENR_USART2EN RCC_APB1ENR_USART2EN_Msk /*!< USART 2 clock enable */
+#define RCC_APB1ENR_I2C1EN_Pos (21U)
+#define RCC_APB1ENR_I2C1EN_Msk (0x1U << RCC_APB1ENR_I2C1EN_Pos) /*!< 0x00200000 */
+#define RCC_APB1ENR_I2C1EN RCC_APB1ENR_I2C1EN_Msk /*!< I2C 1 clock enable */
+
+
+#define RCC_APB1ENR_BKPEN_Pos (27U)
+#define RCC_APB1ENR_BKPEN_Msk (0x1U << RCC_APB1ENR_BKPEN_Pos) /*!< 0x08000000 */
+#define RCC_APB1ENR_BKPEN RCC_APB1ENR_BKPEN_Msk /*!< Backup interface clock enable */
+#define RCC_APB1ENR_PWREN_Pos (28U)
+#define RCC_APB1ENR_PWREN_Msk (0x1U << RCC_APB1ENR_PWREN_Pos) /*!< 0x10000000 */
+#define RCC_APB1ENR_PWREN RCC_APB1ENR_PWREN_Msk /*!< Power interface clock enable */
+
+
+#define RCC_APB1ENR_USBEN_Pos (23U)
+#define RCC_APB1ENR_USBEN_Msk (0x1U << RCC_APB1ENR_USBEN_Pos) /*!< 0x00800000 */
+#define RCC_APB1ENR_USBEN RCC_APB1ENR_USBEN_Msk /*!< USB Device clock enable */
+
+
+
+
+
+
+/******************* Bit definition for RCC_BDCR register *******************/
+#define RCC_BDCR_LSEON_Pos (0U)
+#define RCC_BDCR_LSEON_Msk (0x1U << RCC_BDCR_LSEON_Pos) /*!< 0x00000001 */
+#define RCC_BDCR_LSEON RCC_BDCR_LSEON_Msk /*!< External Low Speed oscillator enable */
+#define RCC_BDCR_LSERDY_Pos (1U)
+#define RCC_BDCR_LSERDY_Msk (0x1U << RCC_BDCR_LSERDY_Pos) /*!< 0x00000002 */
+#define RCC_BDCR_LSERDY RCC_BDCR_LSERDY_Msk /*!< External Low Speed oscillator Ready */
+#define RCC_BDCR_LSEBYP_Pos (2U)
+#define RCC_BDCR_LSEBYP_Msk (0x1U << RCC_BDCR_LSEBYP_Pos) /*!< 0x00000004 */
+#define RCC_BDCR_LSEBYP RCC_BDCR_LSEBYP_Msk /*!< External Low Speed oscillator Bypass */
+
+#define RCC_BDCR_RTCSEL_Pos (8U)
+#define RCC_BDCR_RTCSEL_Msk (0x3U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000300 */
+#define RCC_BDCR_RTCSEL RCC_BDCR_RTCSEL_Msk /*!< RTCSEL[1:0] bits (RTC clock source selection) */
+#define RCC_BDCR_RTCSEL_0 (0x1U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000100 */
+#define RCC_BDCR_RTCSEL_1 (0x2U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000200 */
+
+/*!< RTC congiguration */
+#define RCC_BDCR_RTCSEL_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */
+#define RCC_BDCR_RTCSEL_LSE ((uint32_t)0x00000100) /*!< LSE oscillator clock used as RTC clock */
+#define RCC_BDCR_RTCSEL_LSI ((uint32_t)0x00000200) /*!< LSI oscillator clock used as RTC clock */
+#define RCC_BDCR_RTCSEL_HSE ((uint32_t)0x00000300) /*!< HSE oscillator clock divided by 128 used as RTC clock */
+
+#define RCC_BDCR_RTCEN_Pos (15U)
+#define RCC_BDCR_RTCEN_Msk (0x1U << RCC_BDCR_RTCEN_Pos) /*!< 0x00008000 */
+#define RCC_BDCR_RTCEN RCC_BDCR_RTCEN_Msk /*!< RTC clock enable */
+#define RCC_BDCR_BDRST_Pos (16U)
+#define RCC_BDCR_BDRST_Msk (0x1U << RCC_BDCR_BDRST_Pos) /*!< 0x00010000 */
+#define RCC_BDCR_BDRST RCC_BDCR_BDRST_Msk /*!< Backup domain software reset */
+
+/******************* Bit definition for RCC_CSR register ********************/
+#define RCC_CSR_LSION_Pos (0U)
+#define RCC_CSR_LSION_Msk (0x1U << RCC_CSR_LSION_Pos) /*!< 0x00000001 */
+#define RCC_CSR_LSION RCC_CSR_LSION_Msk /*!< Internal Low Speed oscillator enable */
+#define RCC_CSR_LSIRDY_Pos (1U)
+#define RCC_CSR_LSIRDY_Msk (0x1U << RCC_CSR_LSIRDY_Pos) /*!< 0x00000002 */
+#define RCC_CSR_LSIRDY RCC_CSR_LSIRDY_Msk /*!< Internal Low Speed oscillator Ready */
+#define RCC_CSR_RMVF_Pos (24U)
+#define RCC_CSR_RMVF_Msk (0x1U << RCC_CSR_RMVF_Pos) /*!< 0x01000000 */
+#define RCC_CSR_RMVF RCC_CSR_RMVF_Msk /*!< Remove reset flag */
+#define RCC_CSR_PINRSTF_Pos (26U)
+#define RCC_CSR_PINRSTF_Msk (0x1U << RCC_CSR_PINRSTF_Pos) /*!< 0x04000000 */
+#define RCC_CSR_PINRSTF RCC_CSR_PINRSTF_Msk /*!< PIN reset flag */
+#define RCC_CSR_PORRSTF_Pos (27U)
+#define RCC_CSR_PORRSTF_Msk (0x1U << RCC_CSR_PORRSTF_Pos) /*!< 0x08000000 */
+#define RCC_CSR_PORRSTF RCC_CSR_PORRSTF_Msk /*!< POR/PDR reset flag */
+#define RCC_CSR_SFTRSTF_Pos (28U)
+#define RCC_CSR_SFTRSTF_Msk (0x1U << RCC_CSR_SFTRSTF_Pos) /*!< 0x10000000 */
+#define RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF_Msk /*!< Software Reset flag */
+#define RCC_CSR_IWDGRSTF_Pos (29U)
+#define RCC_CSR_IWDGRSTF_Msk (0x1U << RCC_CSR_IWDGRSTF_Pos) /*!< 0x20000000 */
+#define RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF_Msk /*!< Independent Watchdog reset flag */
+#define RCC_CSR_WWDGRSTF_Pos (30U)
+#define RCC_CSR_WWDGRSTF_Msk (0x1U << RCC_CSR_WWDGRSTF_Pos) /*!< 0x40000000 */
+#define RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF_Msk /*!< Window watchdog reset flag */
+#define RCC_CSR_LPWRRSTF_Pos (31U)
+#define RCC_CSR_LPWRRSTF_Msk (0x1U << RCC_CSR_LPWRRSTF_Pos) /*!< 0x80000000 */
+#define RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF_Msk /*!< Low-Power reset flag */
+
+
+
+/******************************************************************************/
+/* */
+/* General Purpose and Alternate Function I/O */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for GPIO_CRL register *******************/
+#define GPIO_CRL_MODE_Pos (0U)
+#define GPIO_CRL_MODE_Msk (0x33333333U << GPIO_CRL_MODE_Pos) /*!< 0x33333333 */
+#define GPIO_CRL_MODE GPIO_CRL_MODE_Msk /*!< Port x mode bits */
+
+#define GPIO_CRL_MODE0_Pos (0U)
+#define GPIO_CRL_MODE0_Msk (0x3U << GPIO_CRL_MODE0_Pos) /*!< 0x00000003 */
+#define GPIO_CRL_MODE0 GPIO_CRL_MODE0_Msk /*!< MODE0[1:0] bits (Port x mode bits, pin 0) */
+#define GPIO_CRL_MODE0_0 (0x1U << GPIO_CRL_MODE0_Pos) /*!< 0x00000001 */
+#define GPIO_CRL_MODE0_1 (0x2U << GPIO_CRL_MODE0_Pos) /*!< 0x00000002 */
+
+#define GPIO_CRL_MODE1_Pos (4U)
+#define GPIO_CRL_MODE1_Msk (0x3U << GPIO_CRL_MODE1_Pos) /*!< 0x00000030 */
+#define GPIO_CRL_MODE1 GPIO_CRL_MODE1_Msk /*!< MODE1[1:0] bits (Port x mode bits, pin 1) */
+#define GPIO_CRL_MODE1_0 (0x1U << GPIO_CRL_MODE1_Pos) /*!< 0x00000010 */
+#define GPIO_CRL_MODE1_1 (0x2U << GPIO_CRL_MODE1_Pos) /*!< 0x00000020 */
+
+#define GPIO_CRL_MODE2_Pos (8U)
+#define GPIO_CRL_MODE2_Msk (0x3U << GPIO_CRL_MODE2_Pos) /*!< 0x00000300 */
+#define GPIO_CRL_MODE2 GPIO_CRL_MODE2_Msk /*!< MODE2[1:0] bits (Port x mode bits, pin 2) */
+#define GPIO_CRL_MODE2_0 (0x1U << GPIO_CRL_MODE2_Pos) /*!< 0x00000100 */
+#define GPIO_CRL_MODE2_1 (0x2U << GPIO_CRL_MODE2_Pos) /*!< 0x00000200 */
+
+#define GPIO_CRL_MODE3_Pos (12U)
+#define GPIO_CRL_MODE3_Msk (0x3U << GPIO_CRL_MODE3_Pos) /*!< 0x00003000 */
+#define GPIO_CRL_MODE3 GPIO_CRL_MODE3_Msk /*!< MODE3[1:0] bits (Port x mode bits, pin 3) */
+#define GPIO_CRL_MODE3_0 (0x1U << GPIO_CRL_MODE3_Pos) /*!< 0x00001000 */
+#define GPIO_CRL_MODE3_1 (0x2U << GPIO_CRL_MODE3_Pos) /*!< 0x00002000 */
+
+#define GPIO_CRL_MODE4_Pos (16U)
+#define GPIO_CRL_MODE4_Msk (0x3U << GPIO_CRL_MODE4_Pos) /*!< 0x00030000 */
+#define GPIO_CRL_MODE4 GPIO_CRL_MODE4_Msk /*!< MODE4[1:0] bits (Port x mode bits, pin 4) */
+#define GPIO_CRL_MODE4_0 (0x1U << GPIO_CRL_MODE4_Pos) /*!< 0x00010000 */
+#define GPIO_CRL_MODE4_1 (0x2U << GPIO_CRL_MODE4_Pos) /*!< 0x00020000 */
+
+#define GPIO_CRL_MODE5_Pos (20U)
+#define GPIO_CRL_MODE5_Msk (0x3U << GPIO_CRL_MODE5_Pos) /*!< 0x00300000 */
+#define GPIO_CRL_MODE5 GPIO_CRL_MODE5_Msk /*!< MODE5[1:0] bits (Port x mode bits, pin 5) */
+#define GPIO_CRL_MODE5_0 (0x1U << GPIO_CRL_MODE5_Pos) /*!< 0x00100000 */
+#define GPIO_CRL_MODE5_1 (0x2U << GPIO_CRL_MODE5_Pos) /*!< 0x00200000 */
+
+#define GPIO_CRL_MODE6_Pos (24U)
+#define GPIO_CRL_MODE6_Msk (0x3U << GPIO_CRL_MODE6_Pos) /*!< 0x03000000 */
+#define GPIO_CRL_MODE6 GPIO_CRL_MODE6_Msk /*!< MODE6[1:0] bits (Port x mode bits, pin 6) */
+#define GPIO_CRL_MODE6_0 (0x1U << GPIO_CRL_MODE6_Pos) /*!< 0x01000000 */
+#define GPIO_CRL_MODE6_1 (0x2U << GPIO_CRL_MODE6_Pos) /*!< 0x02000000 */
+
+#define GPIO_CRL_MODE7_Pos (28U)
+#define GPIO_CRL_MODE7_Msk (0x3U << GPIO_CRL_MODE7_Pos) /*!< 0x30000000 */
+#define GPIO_CRL_MODE7 GPIO_CRL_MODE7_Msk /*!< MODE7[1:0] bits (Port x mode bits, pin 7) */
+#define GPIO_CRL_MODE7_0 (0x1U << GPIO_CRL_MODE7_Pos) /*!< 0x10000000 */
+#define GPIO_CRL_MODE7_1 (0x2U << GPIO_CRL_MODE7_Pos) /*!< 0x20000000 */
+
+#define GPIO_CRL_CNF_Pos (2U)
+#define GPIO_CRL_CNF_Msk (0x33333333U << GPIO_CRL_CNF_Pos) /*!< 0xCCCCCCCC */
+#define GPIO_CRL_CNF GPIO_CRL_CNF_Msk /*!< Port x configuration bits */
+
+#define GPIO_CRL_CNF0_Pos (2U)
+#define GPIO_CRL_CNF0_Msk (0x3U << GPIO_CRL_CNF0_Pos) /*!< 0x0000000C */
+#define GPIO_CRL_CNF0 GPIO_CRL_CNF0_Msk /*!< CNF0[1:0] bits (Port x configuration bits, pin 0) */
+#define GPIO_CRL_CNF0_0 (0x1U << GPIO_CRL_CNF0_Pos) /*!< 0x00000004 */
+#define GPIO_CRL_CNF0_1 (0x2U << GPIO_CRL_CNF0_Pos) /*!< 0x00000008 */
+
+#define GPIO_CRL_CNF1_Pos (6U)
+#define GPIO_CRL_CNF1_Msk (0x3U << GPIO_CRL_CNF1_Pos) /*!< 0x000000C0 */
+#define GPIO_CRL_CNF1 GPIO_CRL_CNF1_Msk /*!< CNF1[1:0] bits (Port x configuration bits, pin 1) */
+#define GPIO_CRL_CNF1_0 (0x1U << GPIO_CRL_CNF1_Pos) /*!< 0x00000040 */
+#define GPIO_CRL_CNF1_1 (0x2U << GPIO_CRL_CNF1_Pos) /*!< 0x00000080 */
+
+#define GPIO_CRL_CNF2_Pos (10U)
+#define GPIO_CRL_CNF2_Msk (0x3U << GPIO_CRL_CNF2_Pos) /*!< 0x00000C00 */
+#define GPIO_CRL_CNF2 GPIO_CRL_CNF2_Msk /*!< CNF2[1:0] bits (Port x configuration bits, pin 2) */
+#define GPIO_CRL_CNF2_0 (0x1U << GPIO_CRL_CNF2_Pos) /*!< 0x00000400 */
+#define GPIO_CRL_CNF2_1 (0x2U << GPIO_CRL_CNF2_Pos) /*!< 0x00000800 */
+
+#define GPIO_CRL_CNF3_Pos (14U)
+#define GPIO_CRL_CNF3_Msk (0x3U << GPIO_CRL_CNF3_Pos) /*!< 0x0000C000 */
+#define GPIO_CRL_CNF3 GPIO_CRL_CNF3_Msk /*!< CNF3[1:0] bits (Port x configuration bits, pin 3) */
+#define GPIO_CRL_CNF3_0 (0x1U << GPIO_CRL_CNF3_Pos) /*!< 0x00004000 */
+#define GPIO_CRL_CNF3_1 (0x2U << GPIO_CRL_CNF3_Pos) /*!< 0x00008000 */
+
+#define GPIO_CRL_CNF4_Pos (18U)
+#define GPIO_CRL_CNF4_Msk (0x3U << GPIO_CRL_CNF4_Pos) /*!< 0x000C0000 */
+#define GPIO_CRL_CNF4 GPIO_CRL_CNF4_Msk /*!< CNF4[1:0] bits (Port x configuration bits, pin 4) */
+#define GPIO_CRL_CNF4_0 (0x1U << GPIO_CRL_CNF4_Pos) /*!< 0x00040000 */
+#define GPIO_CRL_CNF4_1 (0x2U << GPIO_CRL_CNF4_Pos) /*!< 0x00080000 */
+
+#define GPIO_CRL_CNF5_Pos (22U)
+#define GPIO_CRL_CNF5_Msk (0x3U << GPIO_CRL_CNF5_Pos) /*!< 0x00C00000 */
+#define GPIO_CRL_CNF5 GPIO_CRL_CNF5_Msk /*!< CNF5[1:0] bits (Port x configuration bits, pin 5) */
+#define GPIO_CRL_CNF5_0 (0x1U << GPIO_CRL_CNF5_Pos) /*!< 0x00400000 */
+#define GPIO_CRL_CNF5_1 (0x2U << GPIO_CRL_CNF5_Pos) /*!< 0x00800000 */
+
+#define GPIO_CRL_CNF6_Pos (26U)
+#define GPIO_CRL_CNF6_Msk (0x3U << GPIO_CRL_CNF6_Pos) /*!< 0x0C000000 */
+#define GPIO_CRL_CNF6 GPIO_CRL_CNF6_Msk /*!< CNF6[1:0] bits (Port x configuration bits, pin 6) */
+#define GPIO_CRL_CNF6_0 (0x1U << GPIO_CRL_CNF6_Pos) /*!< 0x04000000 */
+#define GPIO_CRL_CNF6_1 (0x2U << GPIO_CRL_CNF6_Pos) /*!< 0x08000000 */
+
+#define GPIO_CRL_CNF7_Pos (30U)
+#define GPIO_CRL_CNF7_Msk (0x3U << GPIO_CRL_CNF7_Pos) /*!< 0xC0000000 */
+#define GPIO_CRL_CNF7 GPIO_CRL_CNF7_Msk /*!< CNF7[1:0] bits (Port x configuration bits, pin 7) */
+#define GPIO_CRL_CNF7_0 (0x1U << GPIO_CRL_CNF7_Pos) /*!< 0x40000000 */
+#define GPIO_CRL_CNF7_1 (0x2U << GPIO_CRL_CNF7_Pos) /*!< 0x80000000 */
+
+/******************* Bit definition for GPIO_CRH register *******************/
+#define GPIO_CRH_MODE_Pos (0U)
+#define GPIO_CRH_MODE_Msk (0x33333333U << GPIO_CRH_MODE_Pos) /*!< 0x33333333 */
+#define GPIO_CRH_MODE GPIO_CRH_MODE_Msk /*!< Port x mode bits */
+
+#define GPIO_CRH_MODE8_Pos (0U)
+#define GPIO_CRH_MODE8_Msk (0x3U << GPIO_CRH_MODE8_Pos) /*!< 0x00000003 */
+#define GPIO_CRH_MODE8 GPIO_CRH_MODE8_Msk /*!< MODE8[1:0] bits (Port x mode bits, pin 8) */
+#define GPIO_CRH_MODE8_0 (0x1U << GPIO_CRH_MODE8_Pos) /*!< 0x00000001 */
+#define GPIO_CRH_MODE8_1 (0x2U << GPIO_CRH_MODE8_Pos) /*!< 0x00000002 */
+
+#define GPIO_CRH_MODE9_Pos (4U)
+#define GPIO_CRH_MODE9_Msk (0x3U << GPIO_CRH_MODE9_Pos) /*!< 0x00000030 */
+#define GPIO_CRH_MODE9 GPIO_CRH_MODE9_Msk /*!< MODE9[1:0] bits (Port x mode bits, pin 9) */
+#define GPIO_CRH_MODE9_0 (0x1U << GPIO_CRH_MODE9_Pos) /*!< 0x00000010 */
+#define GPIO_CRH_MODE9_1 (0x2U << GPIO_CRH_MODE9_Pos) /*!< 0x00000020 */
+
+#define GPIO_CRH_MODE10_Pos (8U)
+#define GPIO_CRH_MODE10_Msk (0x3U << GPIO_CRH_MODE10_Pos) /*!< 0x00000300 */
+#define GPIO_CRH_MODE10 GPIO_CRH_MODE10_Msk /*!< MODE10[1:0] bits (Port x mode bits, pin 10) */
+#define GPIO_CRH_MODE10_0 (0x1U << GPIO_CRH_MODE10_Pos) /*!< 0x00000100 */
+#define GPIO_CRH_MODE10_1 (0x2U << GPIO_CRH_MODE10_Pos) /*!< 0x00000200 */
+
+#define GPIO_CRH_MODE11_Pos (12U)
+#define GPIO_CRH_MODE11_Msk (0x3U << GPIO_CRH_MODE11_Pos) /*!< 0x00003000 */
+#define GPIO_CRH_MODE11 GPIO_CRH_MODE11_Msk /*!< MODE11[1:0] bits (Port x mode bits, pin 11) */
+#define GPIO_CRH_MODE11_0 (0x1U << GPIO_CRH_MODE11_Pos) /*!< 0x00001000 */
+#define GPIO_CRH_MODE11_1 (0x2U << GPIO_CRH_MODE11_Pos) /*!< 0x00002000 */
+
+#define GPIO_CRH_MODE12_Pos (16U)
+#define GPIO_CRH_MODE12_Msk (0x3U << GPIO_CRH_MODE12_Pos) /*!< 0x00030000 */
+#define GPIO_CRH_MODE12 GPIO_CRH_MODE12_Msk /*!< MODE12[1:0] bits (Port x mode bits, pin 12) */
+#define GPIO_CRH_MODE12_0 (0x1U << GPIO_CRH_MODE12_Pos) /*!< 0x00010000 */
+#define GPIO_CRH_MODE12_1 (0x2U << GPIO_CRH_MODE12_Pos) /*!< 0x00020000 */
+
+#define GPIO_CRH_MODE13_Pos (20U)
+#define GPIO_CRH_MODE13_Msk (0x3U << GPIO_CRH_MODE13_Pos) /*!< 0x00300000 */
+#define GPIO_CRH_MODE13 GPIO_CRH_MODE13_Msk /*!< MODE13[1:0] bits (Port x mode bits, pin 13) */
+#define GPIO_CRH_MODE13_0 (0x1U << GPIO_CRH_MODE13_Pos) /*!< 0x00100000 */
+#define GPIO_CRH_MODE13_1 (0x2U << GPIO_CRH_MODE13_Pos) /*!< 0x00200000 */
+
+#define GPIO_CRH_MODE14_Pos (24U)
+#define GPIO_CRH_MODE14_Msk (0x3U << GPIO_CRH_MODE14_Pos) /*!< 0x03000000 */
+#define GPIO_CRH_MODE14 GPIO_CRH_MODE14_Msk /*!< MODE14[1:0] bits (Port x mode bits, pin 14) */
+#define GPIO_CRH_MODE14_0 (0x1U << GPIO_CRH_MODE14_Pos) /*!< 0x01000000 */
+#define GPIO_CRH_MODE14_1 (0x2U << GPIO_CRH_MODE14_Pos) /*!< 0x02000000 */
+
+#define GPIO_CRH_MODE15_Pos (28U)
+#define GPIO_CRH_MODE15_Msk (0x3U << GPIO_CRH_MODE15_Pos) /*!< 0x30000000 */
+#define GPIO_CRH_MODE15 GPIO_CRH_MODE15_Msk /*!< MODE15[1:0] bits (Port x mode bits, pin 15) */
+#define GPIO_CRH_MODE15_0 (0x1U << GPIO_CRH_MODE15_Pos) /*!< 0x10000000 */
+#define GPIO_CRH_MODE15_1 (0x2U << GPIO_CRH_MODE15_Pos) /*!< 0x20000000 */
+
+#define GPIO_CRH_CNF_Pos (2U)
+#define GPIO_CRH_CNF_Msk (0x33333333U << GPIO_CRH_CNF_Pos) /*!< 0xCCCCCCCC */
+#define GPIO_CRH_CNF GPIO_CRH_CNF_Msk /*!< Port x configuration bits */
+
+#define GPIO_CRH_CNF8_Pos (2U)
+#define GPIO_CRH_CNF8_Msk (0x3U << GPIO_CRH_CNF8_Pos) /*!< 0x0000000C */
+#define GPIO_CRH_CNF8 GPIO_CRH_CNF8_Msk /*!< CNF8[1:0] bits (Port x configuration bits, pin 8) */
+#define GPIO_CRH_CNF8_0 (0x1U << GPIO_CRH_CNF8_Pos) /*!< 0x00000004 */
+#define GPIO_CRH_CNF8_1 (0x2U << GPIO_CRH_CNF8_Pos) /*!< 0x00000008 */
+
+#define GPIO_CRH_CNF9_Pos (6U)
+#define GPIO_CRH_CNF9_Msk (0x3U << GPIO_CRH_CNF9_Pos) /*!< 0x000000C0 */
+#define GPIO_CRH_CNF9 GPIO_CRH_CNF9_Msk /*!< CNF9[1:0] bits (Port x configuration bits, pin 9) */
+#define GPIO_CRH_CNF9_0 (0x1U << GPIO_CRH_CNF9_Pos) /*!< 0x00000040 */
+#define GPIO_CRH_CNF9_1 (0x2U << GPIO_CRH_CNF9_Pos) /*!< 0x00000080 */
+
+#define GPIO_CRH_CNF10_Pos (10U)
+#define GPIO_CRH_CNF10_Msk (0x3U << GPIO_CRH_CNF10_Pos) /*!< 0x00000C00 */
+#define GPIO_CRH_CNF10 GPIO_CRH_CNF10_Msk /*!< CNF10[1:0] bits (Port x configuration bits, pin 10) */
+#define GPIO_CRH_CNF10_0 (0x1U << GPIO_CRH_CNF10_Pos) /*!< 0x00000400 */
+#define GPIO_CRH_CNF10_1 (0x2U << GPIO_CRH_CNF10_Pos) /*!< 0x00000800 */
+
+#define GPIO_CRH_CNF11_Pos (14U)
+#define GPIO_CRH_CNF11_Msk (0x3U << GPIO_CRH_CNF11_Pos) /*!< 0x0000C000 */
+#define GPIO_CRH_CNF11 GPIO_CRH_CNF11_Msk /*!< CNF11[1:0] bits (Port x configuration bits, pin 11) */
+#define GPIO_CRH_CNF11_0 (0x1U << GPIO_CRH_CNF11_Pos) /*!< 0x00004000 */
+#define GPIO_CRH_CNF11_1 (0x2U << GPIO_CRH_CNF11_Pos) /*!< 0x00008000 */
+
+#define GPIO_CRH_CNF12_Pos (18U)
+#define GPIO_CRH_CNF12_Msk (0x3U << GPIO_CRH_CNF12_Pos) /*!< 0x000C0000 */
+#define GPIO_CRH_CNF12 GPIO_CRH_CNF12_Msk /*!< CNF12[1:0] bits (Port x configuration bits, pin 12) */
+#define GPIO_CRH_CNF12_0 (0x1U << GPIO_CRH_CNF12_Pos) /*!< 0x00040000 */
+#define GPIO_CRH_CNF12_1 (0x2U << GPIO_CRH_CNF12_Pos) /*!< 0x00080000 */
+
+#define GPIO_CRH_CNF13_Pos (22U)
+#define GPIO_CRH_CNF13_Msk (0x3U << GPIO_CRH_CNF13_Pos) /*!< 0x00C00000 */
+#define GPIO_CRH_CNF13 GPIO_CRH_CNF13_Msk /*!< CNF13[1:0] bits (Port x configuration bits, pin 13) */
+#define GPIO_CRH_CNF13_0 (0x1U << GPIO_CRH_CNF13_Pos) /*!< 0x00400000 */
+#define GPIO_CRH_CNF13_1 (0x2U << GPIO_CRH_CNF13_Pos) /*!< 0x00800000 */
+
+#define GPIO_CRH_CNF14_Pos (26U)
+#define GPIO_CRH_CNF14_Msk (0x3U << GPIO_CRH_CNF14_Pos) /*!< 0x0C000000 */
+#define GPIO_CRH_CNF14 GPIO_CRH_CNF14_Msk /*!< CNF14[1:0] bits (Port x configuration bits, pin 14) */
+#define GPIO_CRH_CNF14_0 (0x1U << GPIO_CRH_CNF14_Pos) /*!< 0x04000000 */
+#define GPIO_CRH_CNF14_1 (0x2U << GPIO_CRH_CNF14_Pos) /*!< 0x08000000 */
+
+#define GPIO_CRH_CNF15_Pos (30U)
+#define GPIO_CRH_CNF15_Msk (0x3U << GPIO_CRH_CNF15_Pos) /*!< 0xC0000000 */
+#define GPIO_CRH_CNF15 GPIO_CRH_CNF15_Msk /*!< CNF15[1:0] bits (Port x configuration bits, pin 15) */
+#define GPIO_CRH_CNF15_0 (0x1U << GPIO_CRH_CNF15_Pos) /*!< 0x40000000 */
+#define GPIO_CRH_CNF15_1 (0x2U << GPIO_CRH_CNF15_Pos) /*!< 0x80000000 */
+
+/*!<****************** Bit definition for GPIO_IDR register *******************/
+#define GPIO_IDR_IDR0_Pos (0U)
+#define GPIO_IDR_IDR0_Msk (0x1U << GPIO_IDR_IDR0_Pos) /*!< 0x00000001 */
+#define GPIO_IDR_IDR0 GPIO_IDR_IDR0_Msk /*!< Port input data, bit 0 */
+#define GPIO_IDR_IDR1_Pos (1U)
+#define GPIO_IDR_IDR1_Msk (0x1U << GPIO_IDR_IDR1_Pos) /*!< 0x00000002 */
+#define GPIO_IDR_IDR1 GPIO_IDR_IDR1_Msk /*!< Port input data, bit 1 */
+#define GPIO_IDR_IDR2_Pos (2U)
+#define GPIO_IDR_IDR2_Msk (0x1U << GPIO_IDR_IDR2_Pos) /*!< 0x00000004 */
+#define GPIO_IDR_IDR2 GPIO_IDR_IDR2_Msk /*!< Port input data, bit 2 */
+#define GPIO_IDR_IDR3_Pos (3U)
+#define GPIO_IDR_IDR3_Msk (0x1U << GPIO_IDR_IDR3_Pos) /*!< 0x00000008 */
+#define GPIO_IDR_IDR3 GPIO_IDR_IDR3_Msk /*!< Port input data, bit 3 */
+#define GPIO_IDR_IDR4_Pos (4U)
+#define GPIO_IDR_IDR4_Msk (0x1U << GPIO_IDR_IDR4_Pos) /*!< 0x00000010 */
+#define GPIO_IDR_IDR4 GPIO_IDR_IDR4_Msk /*!< Port input data, bit 4 */
+#define GPIO_IDR_IDR5_Pos (5U)
+#define GPIO_IDR_IDR5_Msk (0x1U << GPIO_IDR_IDR5_Pos) /*!< 0x00000020 */
+#define GPIO_IDR_IDR5 GPIO_IDR_IDR5_Msk /*!< Port input data, bit 5 */
+#define GPIO_IDR_IDR6_Pos (6U)
+#define GPIO_IDR_IDR6_Msk (0x1U << GPIO_IDR_IDR6_Pos) /*!< 0x00000040 */
+#define GPIO_IDR_IDR6 GPIO_IDR_IDR6_Msk /*!< Port input data, bit 6 */
+#define GPIO_IDR_IDR7_Pos (7U)
+#define GPIO_IDR_IDR7_Msk (0x1U << GPIO_IDR_IDR7_Pos) /*!< 0x00000080 */
+#define GPIO_IDR_IDR7 GPIO_IDR_IDR7_Msk /*!< Port input data, bit 7 */
+#define GPIO_IDR_IDR8_Pos (8U)
+#define GPIO_IDR_IDR8_Msk (0x1U << GPIO_IDR_IDR8_Pos) /*!< 0x00000100 */
+#define GPIO_IDR_IDR8 GPIO_IDR_IDR8_Msk /*!< Port input data, bit 8 */
+#define GPIO_IDR_IDR9_Pos (9U)
+#define GPIO_IDR_IDR9_Msk (0x1U << GPIO_IDR_IDR9_Pos) /*!< 0x00000200 */
+#define GPIO_IDR_IDR9 GPIO_IDR_IDR9_Msk /*!< Port input data, bit 9 */
+#define GPIO_IDR_IDR10_Pos (10U)
+#define GPIO_IDR_IDR10_Msk (0x1U << GPIO_IDR_IDR10_Pos) /*!< 0x00000400 */
+#define GPIO_IDR_IDR10 GPIO_IDR_IDR10_Msk /*!< Port input data, bit 10 */
+#define GPIO_IDR_IDR11_Pos (11U)
+#define GPIO_IDR_IDR11_Msk (0x1U << GPIO_IDR_IDR11_Pos) /*!< 0x00000800 */
+#define GPIO_IDR_IDR11 GPIO_IDR_IDR11_Msk /*!< Port input data, bit 11 */
+#define GPIO_IDR_IDR12_Pos (12U)
+#define GPIO_IDR_IDR12_Msk (0x1U << GPIO_IDR_IDR12_Pos) /*!< 0x00001000 */
+#define GPIO_IDR_IDR12 GPIO_IDR_IDR12_Msk /*!< Port input data, bit 12 */
+#define GPIO_IDR_IDR13_Pos (13U)
+#define GPIO_IDR_IDR13_Msk (0x1U << GPIO_IDR_IDR13_Pos) /*!< 0x00002000 */
+#define GPIO_IDR_IDR13 GPIO_IDR_IDR13_Msk /*!< Port input data, bit 13 */
+#define GPIO_IDR_IDR14_Pos (14U)
+#define GPIO_IDR_IDR14_Msk (0x1U << GPIO_IDR_IDR14_Pos) /*!< 0x00004000 */
+#define GPIO_IDR_IDR14 GPIO_IDR_IDR14_Msk /*!< Port input data, bit 14 */
+#define GPIO_IDR_IDR15_Pos (15U)
+#define GPIO_IDR_IDR15_Msk (0x1U << GPIO_IDR_IDR15_Pos) /*!< 0x00008000 */
+#define GPIO_IDR_IDR15 GPIO_IDR_IDR15_Msk /*!< Port input data, bit 15 */
+
+/******************* Bit definition for GPIO_ODR register *******************/
+#define GPIO_ODR_ODR0_Pos (0U)
+#define GPIO_ODR_ODR0_Msk (0x1U << GPIO_ODR_ODR0_Pos) /*!< 0x00000001 */
+#define GPIO_ODR_ODR0 GPIO_ODR_ODR0_Msk /*!< Port output data, bit 0 */
+#define GPIO_ODR_ODR1_Pos (1U)
+#define GPIO_ODR_ODR1_Msk (0x1U << GPIO_ODR_ODR1_Pos) /*!< 0x00000002 */
+#define GPIO_ODR_ODR1 GPIO_ODR_ODR1_Msk /*!< Port output data, bit 1 */
+#define GPIO_ODR_ODR2_Pos (2U)
+#define GPIO_ODR_ODR2_Msk (0x1U << GPIO_ODR_ODR2_Pos) /*!< 0x00000004 */
+#define GPIO_ODR_ODR2 GPIO_ODR_ODR2_Msk /*!< Port output data, bit 2 */
+#define GPIO_ODR_ODR3_Pos (3U)
+#define GPIO_ODR_ODR3_Msk (0x1U << GPIO_ODR_ODR3_Pos) /*!< 0x00000008 */
+#define GPIO_ODR_ODR3 GPIO_ODR_ODR3_Msk /*!< Port output data, bit 3 */
+#define GPIO_ODR_ODR4_Pos (4U)
+#define GPIO_ODR_ODR4_Msk (0x1U << GPIO_ODR_ODR4_Pos) /*!< 0x00000010 */
+#define GPIO_ODR_ODR4 GPIO_ODR_ODR4_Msk /*!< Port output data, bit 4 */
+#define GPIO_ODR_ODR5_Pos (5U)
+#define GPIO_ODR_ODR5_Msk (0x1U << GPIO_ODR_ODR5_Pos) /*!< 0x00000020 */
+#define GPIO_ODR_ODR5 GPIO_ODR_ODR5_Msk /*!< Port output data, bit 5 */
+#define GPIO_ODR_ODR6_Pos (6U)
+#define GPIO_ODR_ODR6_Msk (0x1U << GPIO_ODR_ODR6_Pos) /*!< 0x00000040 */
+#define GPIO_ODR_ODR6 GPIO_ODR_ODR6_Msk /*!< Port output data, bit 6 */
+#define GPIO_ODR_ODR7_Pos (7U)
+#define GPIO_ODR_ODR7_Msk (0x1U << GPIO_ODR_ODR7_Pos) /*!< 0x00000080 */
+#define GPIO_ODR_ODR7 GPIO_ODR_ODR7_Msk /*!< Port output data, bit 7 */
+#define GPIO_ODR_ODR8_Pos (8U)
+#define GPIO_ODR_ODR8_Msk (0x1U << GPIO_ODR_ODR8_Pos) /*!< 0x00000100 */
+#define GPIO_ODR_ODR8 GPIO_ODR_ODR8_Msk /*!< Port output data, bit 8 */
+#define GPIO_ODR_ODR9_Pos (9U)
+#define GPIO_ODR_ODR9_Msk (0x1U << GPIO_ODR_ODR9_Pos) /*!< 0x00000200 */
+#define GPIO_ODR_ODR9 GPIO_ODR_ODR9_Msk /*!< Port output data, bit 9 */
+#define GPIO_ODR_ODR10_Pos (10U)
+#define GPIO_ODR_ODR10_Msk (0x1U << GPIO_ODR_ODR10_Pos) /*!< 0x00000400 */
+#define GPIO_ODR_ODR10 GPIO_ODR_ODR10_Msk /*!< Port output data, bit 10 */
+#define GPIO_ODR_ODR11_Pos (11U)
+#define GPIO_ODR_ODR11_Msk (0x1U << GPIO_ODR_ODR11_Pos) /*!< 0x00000800 */
+#define GPIO_ODR_ODR11 GPIO_ODR_ODR11_Msk /*!< Port output data, bit 11 */
+#define GPIO_ODR_ODR12_Pos (12U)
+#define GPIO_ODR_ODR12_Msk (0x1U << GPIO_ODR_ODR12_Pos) /*!< 0x00001000 */
+#define GPIO_ODR_ODR12 GPIO_ODR_ODR12_Msk /*!< Port output data, bit 12 */
+#define GPIO_ODR_ODR13_Pos (13U)
+#define GPIO_ODR_ODR13_Msk (0x1U << GPIO_ODR_ODR13_Pos) /*!< 0x00002000 */
+#define GPIO_ODR_ODR13 GPIO_ODR_ODR13_Msk /*!< Port output data, bit 13 */
+#define GPIO_ODR_ODR14_Pos (14U)
+#define GPIO_ODR_ODR14_Msk (0x1U << GPIO_ODR_ODR14_Pos) /*!< 0x00004000 */
+#define GPIO_ODR_ODR14 GPIO_ODR_ODR14_Msk /*!< Port output data, bit 14 */
+#define GPIO_ODR_ODR15_Pos (15U)
+#define GPIO_ODR_ODR15_Msk (0x1U << GPIO_ODR_ODR15_Pos) /*!< 0x00008000 */
+#define GPIO_ODR_ODR15 GPIO_ODR_ODR15_Msk /*!< Port output data, bit 15 */
+
+/****************** Bit definition for GPIO_BSRR register *******************/
+#define GPIO_BSRR_BS0_Pos (0U)
+#define GPIO_BSRR_BS0_Msk (0x1U << GPIO_BSRR_BS0_Pos) /*!< 0x00000001 */
+#define GPIO_BSRR_BS0 GPIO_BSRR_BS0_Msk /*!< Port x Set bit 0 */
+#define GPIO_BSRR_BS1_Pos (1U)
+#define GPIO_BSRR_BS1_Msk (0x1U << GPIO_BSRR_BS1_Pos) /*!< 0x00000002 */
+#define GPIO_BSRR_BS1 GPIO_BSRR_BS1_Msk /*!< Port x Set bit 1 */
+#define GPIO_BSRR_BS2_Pos (2U)
+#define GPIO_BSRR_BS2_Msk (0x1U << GPIO_BSRR_BS2_Pos) /*!< 0x00000004 */
+#define GPIO_BSRR_BS2 GPIO_BSRR_BS2_Msk /*!< Port x Set bit 2 */
+#define GPIO_BSRR_BS3_Pos (3U)
+#define GPIO_BSRR_BS3_Msk (0x1U << GPIO_BSRR_BS3_Pos) /*!< 0x00000008 */
+#define GPIO_BSRR_BS3 GPIO_BSRR_BS3_Msk /*!< Port x Set bit 3 */
+#define GPIO_BSRR_BS4_Pos (4U)
+#define GPIO_BSRR_BS4_Msk (0x1U << GPIO_BSRR_BS4_Pos) /*!< 0x00000010 */
+#define GPIO_BSRR_BS4 GPIO_BSRR_BS4_Msk /*!< Port x Set bit 4 */
+#define GPIO_BSRR_BS5_Pos (5U)
+#define GPIO_BSRR_BS5_Msk (0x1U << GPIO_BSRR_BS5_Pos) /*!< 0x00000020 */
+#define GPIO_BSRR_BS5 GPIO_BSRR_BS5_Msk /*!< Port x Set bit 5 */
+#define GPIO_BSRR_BS6_Pos (6U)
+#define GPIO_BSRR_BS6_Msk (0x1U << GPIO_BSRR_BS6_Pos) /*!< 0x00000040 */
+#define GPIO_BSRR_BS6 GPIO_BSRR_BS6_Msk /*!< Port x Set bit 6 */
+#define GPIO_BSRR_BS7_Pos (7U)
+#define GPIO_BSRR_BS7_Msk (0x1U << GPIO_BSRR_BS7_Pos) /*!< 0x00000080 */
+#define GPIO_BSRR_BS7 GPIO_BSRR_BS7_Msk /*!< Port x Set bit 7 */
+#define GPIO_BSRR_BS8_Pos (8U)
+#define GPIO_BSRR_BS8_Msk (0x1U << GPIO_BSRR_BS8_Pos) /*!< 0x00000100 */
+#define GPIO_BSRR_BS8 GPIO_BSRR_BS8_Msk /*!< Port x Set bit 8 */
+#define GPIO_BSRR_BS9_Pos (9U)
+#define GPIO_BSRR_BS9_Msk (0x1U << GPIO_BSRR_BS9_Pos) /*!< 0x00000200 */
+#define GPIO_BSRR_BS9 GPIO_BSRR_BS9_Msk /*!< Port x Set bit 9 */
+#define GPIO_BSRR_BS10_Pos (10U)
+#define GPIO_BSRR_BS10_Msk (0x1U << GPIO_BSRR_BS10_Pos) /*!< 0x00000400 */
+#define GPIO_BSRR_BS10 GPIO_BSRR_BS10_Msk /*!< Port x Set bit 10 */
+#define GPIO_BSRR_BS11_Pos (11U)
+#define GPIO_BSRR_BS11_Msk (0x1U << GPIO_BSRR_BS11_Pos) /*!< 0x00000800 */
+#define GPIO_BSRR_BS11 GPIO_BSRR_BS11_Msk /*!< Port x Set bit 11 */
+#define GPIO_BSRR_BS12_Pos (12U)
+#define GPIO_BSRR_BS12_Msk (0x1U << GPIO_BSRR_BS12_Pos) /*!< 0x00001000 */
+#define GPIO_BSRR_BS12 GPIO_BSRR_BS12_Msk /*!< Port x Set bit 12 */
+#define GPIO_BSRR_BS13_Pos (13U)
+#define GPIO_BSRR_BS13_Msk (0x1U << GPIO_BSRR_BS13_Pos) /*!< 0x00002000 */
+#define GPIO_BSRR_BS13 GPIO_BSRR_BS13_Msk /*!< Port x Set bit 13 */
+#define GPIO_BSRR_BS14_Pos (14U)
+#define GPIO_BSRR_BS14_Msk (0x1U << GPIO_BSRR_BS14_Pos) /*!< 0x00004000 */
+#define GPIO_BSRR_BS14 GPIO_BSRR_BS14_Msk /*!< Port x Set bit 14 */
+#define GPIO_BSRR_BS15_Pos (15U)
+#define GPIO_BSRR_BS15_Msk (0x1U << GPIO_BSRR_BS15_Pos) /*!< 0x00008000 */
+#define GPIO_BSRR_BS15 GPIO_BSRR_BS15_Msk /*!< Port x Set bit 15 */
+
+#define GPIO_BSRR_BR0_Pos (16U)
+#define GPIO_BSRR_BR0_Msk (0x1U << GPIO_BSRR_BR0_Pos) /*!< 0x00010000 */
+#define GPIO_BSRR_BR0 GPIO_BSRR_BR0_Msk /*!< Port x Reset bit 0 */
+#define GPIO_BSRR_BR1_Pos (17U)
+#define GPIO_BSRR_BR1_Msk (0x1U << GPIO_BSRR_BR1_Pos) /*!< 0x00020000 */
+#define GPIO_BSRR_BR1 GPIO_BSRR_BR1_Msk /*!< Port x Reset bit 1 */
+#define GPIO_BSRR_BR2_Pos (18U)
+#define GPIO_BSRR_BR2_Msk (0x1U << GPIO_BSRR_BR2_Pos) /*!< 0x00040000 */
+#define GPIO_BSRR_BR2 GPIO_BSRR_BR2_Msk /*!< Port x Reset bit 2 */
+#define GPIO_BSRR_BR3_Pos (19U)
+#define GPIO_BSRR_BR3_Msk (0x1U << GPIO_BSRR_BR3_Pos) /*!< 0x00080000 */
+#define GPIO_BSRR_BR3 GPIO_BSRR_BR3_Msk /*!< Port x Reset bit 3 */
+#define GPIO_BSRR_BR4_Pos (20U)
+#define GPIO_BSRR_BR4_Msk (0x1U << GPIO_BSRR_BR4_Pos) /*!< 0x00100000 */
+#define GPIO_BSRR_BR4 GPIO_BSRR_BR4_Msk /*!< Port x Reset bit 4 */
+#define GPIO_BSRR_BR5_Pos (21U)
+#define GPIO_BSRR_BR5_Msk (0x1U << GPIO_BSRR_BR5_Pos) /*!< 0x00200000 */
+#define GPIO_BSRR_BR5 GPIO_BSRR_BR5_Msk /*!< Port x Reset bit 5 */
+#define GPIO_BSRR_BR6_Pos (22U)
+#define GPIO_BSRR_BR6_Msk (0x1U << GPIO_BSRR_BR6_Pos) /*!< 0x00400000 */
+#define GPIO_BSRR_BR6 GPIO_BSRR_BR6_Msk /*!< Port x Reset bit 6 */
+#define GPIO_BSRR_BR7_Pos (23U)
+#define GPIO_BSRR_BR7_Msk (0x1U << GPIO_BSRR_BR7_Pos) /*!< 0x00800000 */
+#define GPIO_BSRR_BR7 GPIO_BSRR_BR7_Msk /*!< Port x Reset bit 7 */
+#define GPIO_BSRR_BR8_Pos (24U)
+#define GPIO_BSRR_BR8_Msk (0x1U << GPIO_BSRR_BR8_Pos) /*!< 0x01000000 */
+#define GPIO_BSRR_BR8 GPIO_BSRR_BR8_Msk /*!< Port x Reset bit 8 */
+#define GPIO_BSRR_BR9_Pos (25U)
+#define GPIO_BSRR_BR9_Msk (0x1U << GPIO_BSRR_BR9_Pos) /*!< 0x02000000 */
+#define GPIO_BSRR_BR9 GPIO_BSRR_BR9_Msk /*!< Port x Reset bit 9 */
+#define GPIO_BSRR_BR10_Pos (26U)
+#define GPIO_BSRR_BR10_Msk (0x1U << GPIO_BSRR_BR10_Pos) /*!< 0x04000000 */
+#define GPIO_BSRR_BR10 GPIO_BSRR_BR10_Msk /*!< Port x Reset bit 10 */
+#define GPIO_BSRR_BR11_Pos (27U)
+#define GPIO_BSRR_BR11_Msk (0x1U << GPIO_BSRR_BR11_Pos) /*!< 0x08000000 */
+#define GPIO_BSRR_BR11 GPIO_BSRR_BR11_Msk /*!< Port x Reset bit 11 */
+#define GPIO_BSRR_BR12_Pos (28U)
+#define GPIO_BSRR_BR12_Msk (0x1U << GPIO_BSRR_BR12_Pos) /*!< 0x10000000 */
+#define GPIO_BSRR_BR12 GPIO_BSRR_BR12_Msk /*!< Port x Reset bit 12 */
+#define GPIO_BSRR_BR13_Pos (29U)
+#define GPIO_BSRR_BR13_Msk (0x1U << GPIO_BSRR_BR13_Pos) /*!< 0x20000000 */
+#define GPIO_BSRR_BR13 GPIO_BSRR_BR13_Msk /*!< Port x Reset bit 13 */
+#define GPIO_BSRR_BR14_Pos (30U)
+#define GPIO_BSRR_BR14_Msk (0x1U << GPIO_BSRR_BR14_Pos) /*!< 0x40000000 */
+#define GPIO_BSRR_BR14 GPIO_BSRR_BR14_Msk /*!< Port x Reset bit 14 */
+#define GPIO_BSRR_BR15_Pos (31U)
+#define GPIO_BSRR_BR15_Msk (0x1U << GPIO_BSRR_BR15_Pos) /*!< 0x80000000 */
+#define GPIO_BSRR_BR15 GPIO_BSRR_BR15_Msk /*!< Port x Reset bit 15 */
+
+/******************* Bit definition for GPIO_BRR register *******************/
+#define GPIO_BRR_BR0_Pos (0U)
+#define GPIO_BRR_BR0_Msk (0x1U << GPIO_BRR_BR0_Pos) /*!< 0x00000001 */
+#define GPIO_BRR_BR0 GPIO_BRR_BR0_Msk /*!< Port x Reset bit 0 */
+#define GPIO_BRR_BR1_Pos (1U)
+#define GPIO_BRR_BR1_Msk (0x1U << GPIO_BRR_BR1_Pos) /*!< 0x00000002 */
+#define GPIO_BRR_BR1 GPIO_BRR_BR1_Msk /*!< Port x Reset bit 1 */
+#define GPIO_BRR_BR2_Pos (2U)
+#define GPIO_BRR_BR2_Msk (0x1U << GPIO_BRR_BR2_Pos) /*!< 0x00000004 */
+#define GPIO_BRR_BR2 GPIO_BRR_BR2_Msk /*!< Port x Reset bit 2 */
+#define GPIO_BRR_BR3_Pos (3U)
+#define GPIO_BRR_BR3_Msk (0x1U << GPIO_BRR_BR3_Pos) /*!< 0x00000008 */
+#define GPIO_BRR_BR3 GPIO_BRR_BR3_Msk /*!< Port x Reset bit 3 */
+#define GPIO_BRR_BR4_Pos (4U)
+#define GPIO_BRR_BR4_Msk (0x1U << GPIO_BRR_BR4_Pos) /*!< 0x00000010 */
+#define GPIO_BRR_BR4 GPIO_BRR_BR4_Msk /*!< Port x Reset bit 4 */
+#define GPIO_BRR_BR5_Pos (5U)
+#define GPIO_BRR_BR5_Msk (0x1U << GPIO_BRR_BR5_Pos) /*!< 0x00000020 */
+#define GPIO_BRR_BR5 GPIO_BRR_BR5_Msk /*!< Port x Reset bit 5 */
+#define GPIO_BRR_BR6_Pos (6U)
+#define GPIO_BRR_BR6_Msk (0x1U << GPIO_BRR_BR6_Pos) /*!< 0x00000040 */
+#define GPIO_BRR_BR6 GPIO_BRR_BR6_Msk /*!< Port x Reset bit 6 */
+#define GPIO_BRR_BR7_Pos (7U)
+#define GPIO_BRR_BR7_Msk (0x1U << GPIO_BRR_BR7_Pos) /*!< 0x00000080 */
+#define GPIO_BRR_BR7 GPIO_BRR_BR7_Msk /*!< Port x Reset bit 7 */
+#define GPIO_BRR_BR8_Pos (8U)
+#define GPIO_BRR_BR8_Msk (0x1U << GPIO_BRR_BR8_Pos) /*!< 0x00000100 */
+#define GPIO_BRR_BR8 GPIO_BRR_BR8_Msk /*!< Port x Reset bit 8 */
+#define GPIO_BRR_BR9_Pos (9U)
+#define GPIO_BRR_BR9_Msk (0x1U << GPIO_BRR_BR9_Pos) /*!< 0x00000200 */
+#define GPIO_BRR_BR9 GPIO_BRR_BR9_Msk /*!< Port x Reset bit 9 */
+#define GPIO_BRR_BR10_Pos (10U)
+#define GPIO_BRR_BR10_Msk (0x1U << GPIO_BRR_BR10_Pos) /*!< 0x00000400 */
+#define GPIO_BRR_BR10 GPIO_BRR_BR10_Msk /*!< Port x Reset bit 10 */
+#define GPIO_BRR_BR11_Pos (11U)
+#define GPIO_BRR_BR11_Msk (0x1U << GPIO_BRR_BR11_Pos) /*!< 0x00000800 */
+#define GPIO_BRR_BR11 GPIO_BRR_BR11_Msk /*!< Port x Reset bit 11 */
+#define GPIO_BRR_BR12_Pos (12U)
+#define GPIO_BRR_BR12_Msk (0x1U << GPIO_BRR_BR12_Pos) /*!< 0x00001000 */
+#define GPIO_BRR_BR12 GPIO_BRR_BR12_Msk /*!< Port x Reset bit 12 */
+#define GPIO_BRR_BR13_Pos (13U)
+#define GPIO_BRR_BR13_Msk (0x1U << GPIO_BRR_BR13_Pos) /*!< 0x00002000 */
+#define GPIO_BRR_BR13 GPIO_BRR_BR13_Msk /*!< Port x Reset bit 13 */
+#define GPIO_BRR_BR14_Pos (14U)
+#define GPIO_BRR_BR14_Msk (0x1U << GPIO_BRR_BR14_Pos) /*!< 0x00004000 */
+#define GPIO_BRR_BR14 GPIO_BRR_BR14_Msk /*!< Port x Reset bit 14 */
+#define GPIO_BRR_BR15_Pos (15U)
+#define GPIO_BRR_BR15_Msk (0x1U << GPIO_BRR_BR15_Pos) /*!< 0x00008000 */
+#define GPIO_BRR_BR15 GPIO_BRR_BR15_Msk /*!< Port x Reset bit 15 */
+
+/****************** Bit definition for GPIO_LCKR register *******************/
+#define GPIO_LCKR_LCK0_Pos (0U)
+#define GPIO_LCKR_LCK0_Msk (0x1U << GPIO_LCKR_LCK0_Pos) /*!< 0x00000001 */
+#define GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk /*!< Port x Lock bit 0 */
+#define GPIO_LCKR_LCK1_Pos (1U)
+#define GPIO_LCKR_LCK1_Msk (0x1U << GPIO_LCKR_LCK1_Pos) /*!< 0x00000002 */
+#define GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk /*!< Port x Lock bit 1 */
+#define GPIO_LCKR_LCK2_Pos (2U)
+#define GPIO_LCKR_LCK2_Msk (0x1U << GPIO_LCKR_LCK2_Pos) /*!< 0x00000004 */
+#define GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk /*!< Port x Lock bit 2 */
+#define GPIO_LCKR_LCK3_Pos (3U)
+#define GPIO_LCKR_LCK3_Msk (0x1U << GPIO_LCKR_LCK3_Pos) /*!< 0x00000008 */
+#define GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk /*!< Port x Lock bit 3 */
+#define GPIO_LCKR_LCK4_Pos (4U)
+#define GPIO_LCKR_LCK4_Msk (0x1U << GPIO_LCKR_LCK4_Pos) /*!< 0x00000010 */
+#define GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk /*!< Port x Lock bit 4 */
+#define GPIO_LCKR_LCK5_Pos (5U)
+#define GPIO_LCKR_LCK5_Msk (0x1U << GPIO_LCKR_LCK5_Pos) /*!< 0x00000020 */
+#define GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk /*!< Port x Lock bit 5 */
+#define GPIO_LCKR_LCK6_Pos (6U)
+#define GPIO_LCKR_LCK6_Msk (0x1U << GPIO_LCKR_LCK6_Pos) /*!< 0x00000040 */
+#define GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk /*!< Port x Lock bit 6 */
+#define GPIO_LCKR_LCK7_Pos (7U)
+#define GPIO_LCKR_LCK7_Msk (0x1U << GPIO_LCKR_LCK7_Pos) /*!< 0x00000080 */
+#define GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk /*!< Port x Lock bit 7 */
+#define GPIO_LCKR_LCK8_Pos (8U)
+#define GPIO_LCKR_LCK8_Msk (0x1U << GPIO_LCKR_LCK8_Pos) /*!< 0x00000100 */
+#define GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk /*!< Port x Lock bit 8 */
+#define GPIO_LCKR_LCK9_Pos (9U)
+#define GPIO_LCKR_LCK9_Msk (0x1U << GPIO_LCKR_LCK9_Pos) /*!< 0x00000200 */
+#define GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk /*!< Port x Lock bit 9 */
+#define GPIO_LCKR_LCK10_Pos (10U)
+#define GPIO_LCKR_LCK10_Msk (0x1U << GPIO_LCKR_LCK10_Pos) /*!< 0x00000400 */
+#define GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk /*!< Port x Lock bit 10 */
+#define GPIO_LCKR_LCK11_Pos (11U)
+#define GPIO_LCKR_LCK11_Msk (0x1U << GPIO_LCKR_LCK11_Pos) /*!< 0x00000800 */
+#define GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk /*!< Port x Lock bit 11 */
+#define GPIO_LCKR_LCK12_Pos (12U)
+#define GPIO_LCKR_LCK12_Msk (0x1U << GPIO_LCKR_LCK12_Pos) /*!< 0x00001000 */
+#define GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk /*!< Port x Lock bit 12 */
+#define GPIO_LCKR_LCK13_Pos (13U)
+#define GPIO_LCKR_LCK13_Msk (0x1U << GPIO_LCKR_LCK13_Pos) /*!< 0x00002000 */
+#define GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk /*!< Port x Lock bit 13 */
+#define GPIO_LCKR_LCK14_Pos (14U)
+#define GPIO_LCKR_LCK14_Msk (0x1U << GPIO_LCKR_LCK14_Pos) /*!< 0x00004000 */
+#define GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk /*!< Port x Lock bit 14 */
+#define GPIO_LCKR_LCK15_Pos (15U)
+#define GPIO_LCKR_LCK15_Msk (0x1U << GPIO_LCKR_LCK15_Pos) /*!< 0x00008000 */
+#define GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk /*!< Port x Lock bit 15 */
+#define GPIO_LCKR_LCKK_Pos (16U)
+#define GPIO_LCKR_LCKK_Msk (0x1U << GPIO_LCKR_LCKK_Pos) /*!< 0x00010000 */
+#define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk /*!< Lock key */
+
+/*----------------------------------------------------------------------------*/
+
+/****************** Bit definition for AFIO_EVCR register *******************/
+#define AFIO_EVCR_PIN_Pos (0U)
+#define AFIO_EVCR_PIN_Msk (0xFU << AFIO_EVCR_PIN_Pos) /*!< 0x0000000F */
+#define AFIO_EVCR_PIN AFIO_EVCR_PIN_Msk /*!< PIN[3:0] bits (Pin selection) */
+#define AFIO_EVCR_PIN_0 (0x1U << AFIO_EVCR_PIN_Pos) /*!< 0x00000001 */
+#define AFIO_EVCR_PIN_1 (0x2U << AFIO_EVCR_PIN_Pos) /*!< 0x00000002 */
+#define AFIO_EVCR_PIN_2 (0x4U << AFIO_EVCR_PIN_Pos) /*!< 0x00000004 */
+#define AFIO_EVCR_PIN_3 (0x8U << AFIO_EVCR_PIN_Pos) /*!< 0x00000008 */
+
+/*!< PIN configuration */
+#define AFIO_EVCR_PIN_PX0 ((uint32_t)0x00000000) /*!< Pin 0 selected */
+#define AFIO_EVCR_PIN_PX1_Pos (0U)
+#define AFIO_EVCR_PIN_PX1_Msk (0x1U << AFIO_EVCR_PIN_PX1_Pos) /*!< 0x00000001 */
+#define AFIO_EVCR_PIN_PX1 AFIO_EVCR_PIN_PX1_Msk /*!< Pin 1 selected */
+#define AFIO_EVCR_PIN_PX2_Pos (1U)
+#define AFIO_EVCR_PIN_PX2_Msk (0x1U << AFIO_EVCR_PIN_PX2_Pos) /*!< 0x00000002 */
+#define AFIO_EVCR_PIN_PX2 AFIO_EVCR_PIN_PX2_Msk /*!< Pin 2 selected */
+#define AFIO_EVCR_PIN_PX3_Pos (0U)
+#define AFIO_EVCR_PIN_PX3_Msk (0x3U << AFIO_EVCR_PIN_PX3_Pos) /*!< 0x00000003 */
+#define AFIO_EVCR_PIN_PX3 AFIO_EVCR_PIN_PX3_Msk /*!< Pin 3 selected */
+#define AFIO_EVCR_PIN_PX4_Pos (2U)
+#define AFIO_EVCR_PIN_PX4_Msk (0x1U << AFIO_EVCR_PIN_PX4_Pos) /*!< 0x00000004 */
+#define AFIO_EVCR_PIN_PX4 AFIO_EVCR_PIN_PX4_Msk /*!< Pin 4 selected */
+#define AFIO_EVCR_PIN_PX5_Pos (0U)
+#define AFIO_EVCR_PIN_PX5_Msk (0x5U << AFIO_EVCR_PIN_PX5_Pos) /*!< 0x00000005 */
+#define AFIO_EVCR_PIN_PX5 AFIO_EVCR_PIN_PX5_Msk /*!< Pin 5 selected */
+#define AFIO_EVCR_PIN_PX6_Pos (1U)
+#define AFIO_EVCR_PIN_PX6_Msk (0x3U << AFIO_EVCR_PIN_PX6_Pos) /*!< 0x00000006 */
+#define AFIO_EVCR_PIN_PX6 AFIO_EVCR_PIN_PX6_Msk /*!< Pin 6 selected */
+#define AFIO_EVCR_PIN_PX7_Pos (0U)
+#define AFIO_EVCR_PIN_PX7_Msk (0x7U << AFIO_EVCR_PIN_PX7_Pos) /*!< 0x00000007 */
+#define AFIO_EVCR_PIN_PX7 AFIO_EVCR_PIN_PX7_Msk /*!< Pin 7 selected */
+#define AFIO_EVCR_PIN_PX8_Pos (3U)
+#define AFIO_EVCR_PIN_PX8_Msk (0x1U << AFIO_EVCR_PIN_PX8_Pos) /*!< 0x00000008 */
+#define AFIO_EVCR_PIN_PX8 AFIO_EVCR_PIN_PX8_Msk /*!< Pin 8 selected */
+#define AFIO_EVCR_PIN_PX9_Pos (0U)
+#define AFIO_EVCR_PIN_PX9_Msk (0x9U << AFIO_EVCR_PIN_PX9_Pos) /*!< 0x00000009 */
+#define AFIO_EVCR_PIN_PX9 AFIO_EVCR_PIN_PX9_Msk /*!< Pin 9 selected */
+#define AFIO_EVCR_PIN_PX10_Pos (1U)
+#define AFIO_EVCR_PIN_PX10_Msk (0x5U << AFIO_EVCR_PIN_PX10_Pos) /*!< 0x0000000A */
+#define AFIO_EVCR_PIN_PX10 AFIO_EVCR_PIN_PX10_Msk /*!< Pin 10 selected */
+#define AFIO_EVCR_PIN_PX11_Pos (0U)
+#define AFIO_EVCR_PIN_PX11_Msk (0xBU << AFIO_EVCR_PIN_PX11_Pos) /*!< 0x0000000B */
+#define AFIO_EVCR_PIN_PX11 AFIO_EVCR_PIN_PX11_Msk /*!< Pin 11 selected */
+#define AFIO_EVCR_PIN_PX12_Pos (2U)
+#define AFIO_EVCR_PIN_PX12_Msk (0x3U << AFIO_EVCR_PIN_PX12_Pos) /*!< 0x0000000C */
+#define AFIO_EVCR_PIN_PX12 AFIO_EVCR_PIN_PX12_Msk /*!< Pin 12 selected */
+#define AFIO_EVCR_PIN_PX13_Pos (0U)
+#define AFIO_EVCR_PIN_PX13_Msk (0xDU << AFIO_EVCR_PIN_PX13_Pos) /*!< 0x0000000D */
+#define AFIO_EVCR_PIN_PX13 AFIO_EVCR_PIN_PX13_Msk /*!< Pin 13 selected */
+#define AFIO_EVCR_PIN_PX14_Pos (1U)
+#define AFIO_EVCR_PIN_PX14_Msk (0x7U << AFIO_EVCR_PIN_PX14_Pos) /*!< 0x0000000E */
+#define AFIO_EVCR_PIN_PX14 AFIO_EVCR_PIN_PX14_Msk /*!< Pin 14 selected */
+#define AFIO_EVCR_PIN_PX15_Pos (0U)
+#define AFIO_EVCR_PIN_PX15_Msk (0xFU << AFIO_EVCR_PIN_PX15_Pos) /*!< 0x0000000F */
+#define AFIO_EVCR_PIN_PX15 AFIO_EVCR_PIN_PX15_Msk /*!< Pin 15 selected */
+
+#define AFIO_EVCR_PORT_Pos (4U)
+#define AFIO_EVCR_PORT_Msk (0x7U << AFIO_EVCR_PORT_Pos) /*!< 0x00000070 */
+#define AFIO_EVCR_PORT AFIO_EVCR_PORT_Msk /*!< PORT[2:0] bits (Port selection) */
+#define AFIO_EVCR_PORT_0 (0x1U << AFIO_EVCR_PORT_Pos) /*!< 0x00000010 */
+#define AFIO_EVCR_PORT_1 (0x2U << AFIO_EVCR_PORT_Pos) /*!< 0x00000020 */
+#define AFIO_EVCR_PORT_2 (0x4U << AFIO_EVCR_PORT_Pos) /*!< 0x00000040 */
+
+/*!< PORT configuration */
+#define AFIO_EVCR_PORT_PA ((uint32_t)0x00000000) /*!< Port A selected */
+#define AFIO_EVCR_PORT_PB_Pos (4U)
+#define AFIO_EVCR_PORT_PB_Msk (0x1U << AFIO_EVCR_PORT_PB_Pos) /*!< 0x00000010 */
+#define AFIO_EVCR_PORT_PB AFIO_EVCR_PORT_PB_Msk /*!< Port B selected */
+#define AFIO_EVCR_PORT_PC_Pos (5U)
+#define AFIO_EVCR_PORT_PC_Msk (0x1U << AFIO_EVCR_PORT_PC_Pos) /*!< 0x00000020 */
+#define AFIO_EVCR_PORT_PC AFIO_EVCR_PORT_PC_Msk /*!< Port C selected */
+#define AFIO_EVCR_PORT_PD_Pos (4U)
+#define AFIO_EVCR_PORT_PD_Msk (0x3U << AFIO_EVCR_PORT_PD_Pos) /*!< 0x00000030 */
+#define AFIO_EVCR_PORT_PD AFIO_EVCR_PORT_PD_Msk /*!< Port D selected */
+#define AFIO_EVCR_PORT_PE_Pos (6U)
+#define AFIO_EVCR_PORT_PE_Msk (0x1U << AFIO_EVCR_PORT_PE_Pos) /*!< 0x00000040 */
+#define AFIO_EVCR_PORT_PE AFIO_EVCR_PORT_PE_Msk /*!< Port E selected */
+
+#define AFIO_EVCR_EVOE_Pos (7U)
+#define AFIO_EVCR_EVOE_Msk (0x1U << AFIO_EVCR_EVOE_Pos) /*!< 0x00000080 */
+#define AFIO_EVCR_EVOE AFIO_EVCR_EVOE_Msk /*!< Event Output Enable */
+
+/****************** Bit definition for AFIO_MAPR register *******************/
+#define AFIO_MAPR_SPI1_REMAP_Pos (0U)
+#define AFIO_MAPR_SPI1_REMAP_Msk (0x1U << AFIO_MAPR_SPI1_REMAP_Pos) /*!< 0x00000001 */
+#define AFIO_MAPR_SPI1_REMAP AFIO_MAPR_SPI1_REMAP_Msk /*!< SPI1 remapping */
+#define AFIO_MAPR_I2C1_REMAP_Pos (1U)
+#define AFIO_MAPR_I2C1_REMAP_Msk (0x1U << AFIO_MAPR_I2C1_REMAP_Pos) /*!< 0x00000002 */
+#define AFIO_MAPR_I2C1_REMAP AFIO_MAPR_I2C1_REMAP_Msk /*!< I2C1 remapping */
+#define AFIO_MAPR_USART1_REMAP_Pos (2U)
+#define AFIO_MAPR_USART1_REMAP_Msk (0x1U << AFIO_MAPR_USART1_REMAP_Pos) /*!< 0x00000004 */
+#define AFIO_MAPR_USART1_REMAP AFIO_MAPR_USART1_REMAP_Msk /*!< USART1 remapping */
+#define AFIO_MAPR_USART2_REMAP_Pos (3U)
+#define AFIO_MAPR_USART2_REMAP_Msk (0x1U << AFIO_MAPR_USART2_REMAP_Pos) /*!< 0x00000008 */
+#define AFIO_MAPR_USART2_REMAP AFIO_MAPR_USART2_REMAP_Msk /*!< USART2 remapping */
+
+
+#define AFIO_MAPR_TIM1_REMAP_Pos (6U)
+#define AFIO_MAPR_TIM1_REMAP_Msk (0x3U << AFIO_MAPR_TIM1_REMAP_Pos) /*!< 0x000000C0 */
+#define AFIO_MAPR_TIM1_REMAP AFIO_MAPR_TIM1_REMAP_Msk /*!< TIM1_REMAP[1:0] bits (TIM1 remapping) */
+#define AFIO_MAPR_TIM1_REMAP_0 (0x1U << AFIO_MAPR_TIM1_REMAP_Pos) /*!< 0x00000040 */
+#define AFIO_MAPR_TIM1_REMAP_1 (0x2U << AFIO_MAPR_TIM1_REMAP_Pos) /*!< 0x00000080 */
+
+/*!< TIM1_REMAP configuration */
+#define AFIO_MAPR_TIM1_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15) */
+#define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Pos (6U)
+#define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Msk (0x1U << AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Pos) /*!< 0x00000040 */
+#define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Msk /*!< Partial remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PA6, CH1N/PA7, CH2N/PB0, CH3N/PB1) */
+#define AFIO_MAPR_TIM1_REMAP_FULLREMAP_Pos (6U)
+#define AFIO_MAPR_TIM1_REMAP_FULLREMAP_Msk (0x3U << AFIO_MAPR_TIM1_REMAP_FULLREMAP_Pos) /*!< 0x000000C0 */
+#define AFIO_MAPR_TIM1_REMAP_FULLREMAP AFIO_MAPR_TIM1_REMAP_FULLREMAP_Msk /*!< Full remap (ETR/PE7, CH1/PE9, CH2/PE11, CH3/PE13, CH4/PE14, BKIN/PE15, CH1N/PE8, CH2N/PE10, CH3N/PE12) */
+
+#define AFIO_MAPR_TIM2_REMAP_Pos (8U)
+#define AFIO_MAPR_TIM2_REMAP_Msk (0x3U << AFIO_MAPR_TIM2_REMAP_Pos) /*!< 0x00000300 */
+#define AFIO_MAPR_TIM2_REMAP AFIO_MAPR_TIM2_REMAP_Msk /*!< TIM2_REMAP[1:0] bits (TIM2 remapping) */
+#define AFIO_MAPR_TIM2_REMAP_0 (0x1U << AFIO_MAPR_TIM2_REMAP_Pos) /*!< 0x00000100 */
+#define AFIO_MAPR_TIM2_REMAP_1 (0x2U << AFIO_MAPR_TIM2_REMAP_Pos) /*!< 0x00000200 */
+
+/*!< TIM2_REMAP configuration */
+#define AFIO_MAPR_TIM2_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3) */
+#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Pos (8U)
+#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Msk (0x1U << AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Pos) /*!< 0x00000100 */
+#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1 AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Msk /*!< Partial remap (CH1/ETR/PA15, CH2/PB3, CH3/PA2, CH4/PA3) */
+#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2_Pos (9U)
+#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2_Msk (0x1U << AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2_Pos) /*!< 0x00000200 */
+#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2 AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2_Msk /*!< Partial remap (CH1/ETR/PA0, CH2/PA1, CH3/PB10, CH4/PB11) */
+#define AFIO_MAPR_TIM2_REMAP_FULLREMAP_Pos (8U)
+#define AFIO_MAPR_TIM2_REMAP_FULLREMAP_Msk (0x3U << AFIO_MAPR_TIM2_REMAP_FULLREMAP_Pos) /*!< 0x00000300 */
+#define AFIO_MAPR_TIM2_REMAP_FULLREMAP AFIO_MAPR_TIM2_REMAP_FULLREMAP_Msk /*!< Full remap (CH1/ETR/PA15, CH2/PB3, CH3/PB10, CH4/PB11) */
+
+#define AFIO_MAPR_TIM3_REMAP_Pos (10U)
+#define AFIO_MAPR_TIM3_REMAP_Msk (0x3U << AFIO_MAPR_TIM3_REMAP_Pos) /*!< 0x00000C00 */
+#define AFIO_MAPR_TIM3_REMAP AFIO_MAPR_TIM3_REMAP_Msk /*!< TIM3_REMAP[1:0] bits (TIM3 remapping) */
+#define AFIO_MAPR_TIM3_REMAP_0 (0x1U << AFIO_MAPR_TIM3_REMAP_Pos) /*!< 0x00000400 */
+#define AFIO_MAPR_TIM3_REMAP_1 (0x2U << AFIO_MAPR_TIM3_REMAP_Pos) /*!< 0x00000800 */
+
+/*!< TIM3_REMAP configuration */
+#define AFIO_MAPR_TIM3_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1) */
+#define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Pos (11U)
+#define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Msk (0x1U << AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Pos) /*!< 0x00000800 */
+#define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Msk /*!< Partial remap (CH1/PB4, CH2/PB5, CH3/PB0, CH4/PB1) */
+#define AFIO_MAPR_TIM3_REMAP_FULLREMAP_Pos (10U)
+#define AFIO_MAPR_TIM3_REMAP_FULLREMAP_Msk (0x3U << AFIO_MAPR_TIM3_REMAP_FULLREMAP_Pos) /*!< 0x00000C00 */
+#define AFIO_MAPR_TIM3_REMAP_FULLREMAP AFIO_MAPR_TIM3_REMAP_FULLREMAP_Msk /*!< Full remap (CH1/PC6, CH2/PC7, CH3/PC8, CH4/PC9) */
+
+
+
+#define AFIO_MAPR_PD01_REMAP_Pos (15U)
+#define AFIO_MAPR_PD01_REMAP_Msk (0x1U << AFIO_MAPR_PD01_REMAP_Pos) /*!< 0x00008000 */
+#define AFIO_MAPR_PD01_REMAP AFIO_MAPR_PD01_REMAP_Msk /*!< Port D0/Port D1 mapping on OSC_IN/OSC_OUT */
+
+/*!< SWJ_CFG configuration */
+#define AFIO_MAPR_SWJ_CFG_Pos (24U)
+#define AFIO_MAPR_SWJ_CFG_Msk (0x7U << AFIO_MAPR_SWJ_CFG_Pos) /*!< 0x07000000 */
+#define AFIO_MAPR_SWJ_CFG AFIO_MAPR_SWJ_CFG_Msk /*!< SWJ_CFG[2:0] bits (Serial Wire JTAG configuration) */
+#define AFIO_MAPR_SWJ_CFG_0 (0x1U << AFIO_MAPR_SWJ_CFG_Pos) /*!< 0x01000000 */
+#define AFIO_MAPR_SWJ_CFG_1 (0x2U << AFIO_MAPR_SWJ_CFG_Pos) /*!< 0x02000000 */
+#define AFIO_MAPR_SWJ_CFG_2 (0x4U << AFIO_MAPR_SWJ_CFG_Pos) /*!< 0x04000000 */
+
+#define AFIO_MAPR_SWJ_CFG_RESET ((uint32_t)0x00000000) /*!< Full SWJ (JTAG-DP + SW-DP) : Reset State */
+#define AFIO_MAPR_SWJ_CFG_NOJNTRST_Pos (24U)
+#define AFIO_MAPR_SWJ_CFG_NOJNTRST_Msk (0x1U << AFIO_MAPR_SWJ_CFG_NOJNTRST_Pos) /*!< 0x01000000 */
+#define AFIO_MAPR_SWJ_CFG_NOJNTRST AFIO_MAPR_SWJ_CFG_NOJNTRST_Msk /*!< Full SWJ (JTAG-DP + SW-DP) but without JNTRST */
+#define AFIO_MAPR_SWJ_CFG_JTAGDISABLE_Pos (25U)
+#define AFIO_MAPR_SWJ_CFG_JTAGDISABLE_Msk (0x1U << AFIO_MAPR_SWJ_CFG_JTAGDISABLE_Pos) /*!< 0x02000000 */
+#define AFIO_MAPR_SWJ_CFG_JTAGDISABLE AFIO_MAPR_SWJ_CFG_JTAGDISABLE_Msk /*!< JTAG-DP Disabled and SW-DP Enabled */
+#define AFIO_MAPR_SWJ_CFG_DISABLE_Pos (26U)
+#define AFIO_MAPR_SWJ_CFG_DISABLE_Msk (0x1U << AFIO_MAPR_SWJ_CFG_DISABLE_Pos) /*!< 0x04000000 */
+#define AFIO_MAPR_SWJ_CFG_DISABLE AFIO_MAPR_SWJ_CFG_DISABLE_Msk /*!< JTAG-DP Disabled and SW-DP Disabled */
+
+
+/***************** Bit definition for AFIO_EXTICR1 register *****************/
+#define AFIO_EXTICR1_EXTI0_Pos (0U)
+#define AFIO_EXTICR1_EXTI0_Msk (0xFU << AFIO_EXTICR1_EXTI0_Pos) /*!< 0x0000000F */
+#define AFIO_EXTICR1_EXTI0 AFIO_EXTICR1_EXTI0_Msk /*!< EXTI 0 configuration */
+#define AFIO_EXTICR1_EXTI1_Pos (4U)
+#define AFIO_EXTICR1_EXTI1_Msk (0xFU << AFIO_EXTICR1_EXTI1_Pos) /*!< 0x000000F0 */
+#define AFIO_EXTICR1_EXTI1 AFIO_EXTICR1_EXTI1_Msk /*!< EXTI 1 configuration */
+#define AFIO_EXTICR1_EXTI2_Pos (8U)
+#define AFIO_EXTICR1_EXTI2_Msk (0xFU << AFIO_EXTICR1_EXTI2_Pos) /*!< 0x00000F00 */
+#define AFIO_EXTICR1_EXTI2 AFIO_EXTICR1_EXTI2_Msk /*!< EXTI 2 configuration */
+#define AFIO_EXTICR1_EXTI3_Pos (12U)
+#define AFIO_EXTICR1_EXTI3_Msk (0xFU << AFIO_EXTICR1_EXTI3_Pos) /*!< 0x0000F000 */
+#define AFIO_EXTICR1_EXTI3 AFIO_EXTICR1_EXTI3_Msk /*!< EXTI 3 configuration */
+
+/*!< EXTI0 configuration */
+#define AFIO_EXTICR1_EXTI0_PA ((uint32_t)0x00000000) /*!< PA[0] pin */
+#define AFIO_EXTICR1_EXTI0_PB_Pos (0U)
+#define AFIO_EXTICR1_EXTI0_PB_Msk (0x1U << AFIO_EXTICR1_EXTI0_PB_Pos) /*!< 0x00000001 */
+#define AFIO_EXTICR1_EXTI0_PB AFIO_EXTICR1_EXTI0_PB_Msk /*!< PB[0] pin */
+#define AFIO_EXTICR1_EXTI0_PC_Pos (1U)
+#define AFIO_EXTICR1_EXTI0_PC_Msk (0x1U << AFIO_EXTICR1_EXTI0_PC_Pos) /*!< 0x00000002 */
+#define AFIO_EXTICR1_EXTI0_PC AFIO_EXTICR1_EXTI0_PC_Msk /*!< PC[0] pin */
+#define AFIO_EXTICR1_EXTI0_PD_Pos (0U)
+#define AFIO_EXTICR1_EXTI0_PD_Msk (0x3U << AFIO_EXTICR1_EXTI0_PD_Pos) /*!< 0x00000003 */
+#define AFIO_EXTICR1_EXTI0_PD AFIO_EXTICR1_EXTI0_PD_Msk /*!< PD[0] pin */
+#define AFIO_EXTICR1_EXTI0_PE_Pos (2U)
+#define AFIO_EXTICR1_EXTI0_PE_Msk (0x1U << AFIO_EXTICR1_EXTI0_PE_Pos) /*!< 0x00000004 */
+#define AFIO_EXTICR1_EXTI0_PE AFIO_EXTICR1_EXTI0_PE_Msk /*!< PE[0] pin */
+#define AFIO_EXTICR1_EXTI0_PF_Pos (0U)
+#define AFIO_EXTICR1_EXTI0_PF_Msk (0x5U << AFIO_EXTICR1_EXTI0_PF_Pos) /*!< 0x00000005 */
+#define AFIO_EXTICR1_EXTI0_PF AFIO_EXTICR1_EXTI0_PF_Msk /*!< PF[0] pin */
+#define AFIO_EXTICR1_EXTI0_PG_Pos (1U)
+#define AFIO_EXTICR1_EXTI0_PG_Msk (0x3U << AFIO_EXTICR1_EXTI0_PG_Pos) /*!< 0x00000006 */
+#define AFIO_EXTICR1_EXTI0_PG AFIO_EXTICR1_EXTI0_PG_Msk /*!< PG[0] pin */
+
+/*!< EXTI1 configuration */
+#define AFIO_EXTICR1_EXTI1_PA ((uint32_t)0x00000000) /*!< PA[1] pin */
+#define AFIO_EXTICR1_EXTI1_PB_Pos (4U)
+#define AFIO_EXTICR1_EXTI1_PB_Msk (0x1U << AFIO_EXTICR1_EXTI1_PB_Pos) /*!< 0x00000010 */
+#define AFIO_EXTICR1_EXTI1_PB AFIO_EXTICR1_EXTI1_PB_Msk /*!< PB[1] pin */
+#define AFIO_EXTICR1_EXTI1_PC_Pos (5U)
+#define AFIO_EXTICR1_EXTI1_PC_Msk (0x1U << AFIO_EXTICR1_EXTI1_PC_Pos) /*!< 0x00000020 */
+#define AFIO_EXTICR1_EXTI1_PC AFIO_EXTICR1_EXTI1_PC_Msk /*!< PC[1] pin */
+#define AFIO_EXTICR1_EXTI1_PD_Pos (4U)
+#define AFIO_EXTICR1_EXTI1_PD_Msk (0x3U << AFIO_EXTICR1_EXTI1_PD_Pos) /*!< 0x00000030 */
+#define AFIO_EXTICR1_EXTI1_PD AFIO_EXTICR1_EXTI1_PD_Msk /*!< PD[1] pin */
+#define AFIO_EXTICR1_EXTI1_PE_Pos (6U)
+#define AFIO_EXTICR1_EXTI1_PE_Msk (0x1U << AFIO_EXTICR1_EXTI1_PE_Pos) /*!< 0x00000040 */
+#define AFIO_EXTICR1_EXTI1_PE AFIO_EXTICR1_EXTI1_PE_Msk /*!< PE[1] pin */
+#define AFIO_EXTICR1_EXTI1_PF_Pos (4U)
+#define AFIO_EXTICR1_EXTI1_PF_Msk (0x5U << AFIO_EXTICR1_EXTI1_PF_Pos) /*!< 0x00000050 */
+#define AFIO_EXTICR1_EXTI1_PF AFIO_EXTICR1_EXTI1_PF_Msk /*!< PF[1] pin */
+#define AFIO_EXTICR1_EXTI1_PG_Pos (5U)
+#define AFIO_EXTICR1_EXTI1_PG_Msk (0x3U << AFIO_EXTICR1_EXTI1_PG_Pos) /*!< 0x00000060 */
+#define AFIO_EXTICR1_EXTI1_PG AFIO_EXTICR1_EXTI1_PG_Msk /*!< PG[1] pin */
+
+/*!< EXTI2 configuration */
+#define AFIO_EXTICR1_EXTI2_PA ((uint32_t)0x00000000) /*!< PA[2] pin */
+#define AFIO_EXTICR1_EXTI2_PB_Pos (8U)
+#define AFIO_EXTICR1_EXTI2_PB_Msk (0x1U << AFIO_EXTICR1_EXTI2_PB_Pos) /*!< 0x00000100 */
+#define AFIO_EXTICR1_EXTI2_PB AFIO_EXTICR1_EXTI2_PB_Msk /*!< PB[2] pin */
+#define AFIO_EXTICR1_EXTI2_PC_Pos (9U)
+#define AFIO_EXTICR1_EXTI2_PC_Msk (0x1U << AFIO_EXTICR1_EXTI2_PC_Pos) /*!< 0x00000200 */
+#define AFIO_EXTICR1_EXTI2_PC AFIO_EXTICR1_EXTI2_PC_Msk /*!< PC[2] pin */
+#define AFIO_EXTICR1_EXTI2_PD_Pos (8U)
+#define AFIO_EXTICR1_EXTI2_PD_Msk (0x3U << AFIO_EXTICR1_EXTI2_PD_Pos) /*!< 0x00000300 */
+#define AFIO_EXTICR1_EXTI2_PD AFIO_EXTICR1_EXTI2_PD_Msk /*!< PD[2] pin */
+#define AFIO_EXTICR1_EXTI2_PE_Pos (10U)
+#define AFIO_EXTICR1_EXTI2_PE_Msk (0x1U << AFIO_EXTICR1_EXTI2_PE_Pos) /*!< 0x00000400 */
+#define AFIO_EXTICR1_EXTI2_PE AFIO_EXTICR1_EXTI2_PE_Msk /*!< PE[2] pin */
+#define AFIO_EXTICR1_EXTI2_PF_Pos (8U)
+#define AFIO_EXTICR1_EXTI2_PF_Msk (0x5U << AFIO_EXTICR1_EXTI2_PF_Pos) /*!< 0x00000500 */
+#define AFIO_EXTICR1_EXTI2_PF AFIO_EXTICR1_EXTI2_PF_Msk /*!< PF[2] pin */
+#define AFIO_EXTICR1_EXTI2_PG_Pos (9U)
+#define AFIO_EXTICR1_EXTI2_PG_Msk (0x3U << AFIO_EXTICR1_EXTI2_PG_Pos) /*!< 0x00000600 */
+#define AFIO_EXTICR1_EXTI2_PG AFIO_EXTICR1_EXTI2_PG_Msk /*!< PG[2] pin */
+
+/*!< EXTI3 configuration */
+#define AFIO_EXTICR1_EXTI3_PA ((uint32_t)0x00000000) /*!< PA[3] pin */
+#define AFIO_EXTICR1_EXTI3_PB_Pos (12U)
+#define AFIO_EXTICR1_EXTI3_PB_Msk (0x1U << AFIO_EXTICR1_EXTI3_PB_Pos) /*!< 0x00001000 */
+#define AFIO_EXTICR1_EXTI3_PB AFIO_EXTICR1_EXTI3_PB_Msk /*!< PB[3] pin */
+#define AFIO_EXTICR1_EXTI3_PC_Pos (13U)
+#define AFIO_EXTICR1_EXTI3_PC_Msk (0x1U << AFIO_EXTICR1_EXTI3_PC_Pos) /*!< 0x00002000 */
+#define AFIO_EXTICR1_EXTI3_PC AFIO_EXTICR1_EXTI3_PC_Msk /*!< PC[3] pin */
+#define AFIO_EXTICR1_EXTI3_PD_Pos (12U)
+#define AFIO_EXTICR1_EXTI3_PD_Msk (0x3U << AFIO_EXTICR1_EXTI3_PD_Pos) /*!< 0x00003000 */
+#define AFIO_EXTICR1_EXTI3_PD AFIO_EXTICR1_EXTI3_PD_Msk /*!< PD[3] pin */
+#define AFIO_EXTICR1_EXTI3_PE_Pos (14U)
+#define AFIO_EXTICR1_EXTI3_PE_Msk (0x1U << AFIO_EXTICR1_EXTI3_PE_Pos) /*!< 0x00004000 */
+#define AFIO_EXTICR1_EXTI3_PE AFIO_EXTICR1_EXTI3_PE_Msk /*!< PE[3] pin */
+#define AFIO_EXTICR1_EXTI3_PF_Pos (12U)
+#define AFIO_EXTICR1_EXTI3_PF_Msk (0x5U << AFIO_EXTICR1_EXTI3_PF_Pos) /*!< 0x00005000 */
+#define AFIO_EXTICR1_EXTI3_PF AFIO_EXTICR1_EXTI3_PF_Msk /*!< PF[3] pin */
+#define AFIO_EXTICR1_EXTI3_PG_Pos (13U)
+#define AFIO_EXTICR1_EXTI3_PG_Msk (0x3U << AFIO_EXTICR1_EXTI3_PG_Pos) /*!< 0x00006000 */
+#define AFIO_EXTICR1_EXTI3_PG AFIO_EXTICR1_EXTI3_PG_Msk /*!< PG[3] pin */
+
+/***************** Bit definition for AFIO_EXTICR2 register *****************/
+#define AFIO_EXTICR2_EXTI4_Pos (0U)
+#define AFIO_EXTICR2_EXTI4_Msk (0xFU << AFIO_EXTICR2_EXTI4_Pos) /*!< 0x0000000F */
+#define AFIO_EXTICR2_EXTI4 AFIO_EXTICR2_EXTI4_Msk /*!< EXTI 4 configuration */
+#define AFIO_EXTICR2_EXTI5_Pos (4U)
+#define AFIO_EXTICR2_EXTI5_Msk (0xFU << AFIO_EXTICR2_EXTI5_Pos) /*!< 0x000000F0 */
+#define AFIO_EXTICR2_EXTI5 AFIO_EXTICR2_EXTI5_Msk /*!< EXTI 5 configuration */
+#define AFIO_EXTICR2_EXTI6_Pos (8U)
+#define AFIO_EXTICR2_EXTI6_Msk (0xFU << AFIO_EXTICR2_EXTI6_Pos) /*!< 0x00000F00 */
+#define AFIO_EXTICR2_EXTI6 AFIO_EXTICR2_EXTI6_Msk /*!< EXTI 6 configuration */
+#define AFIO_EXTICR2_EXTI7_Pos (12U)
+#define AFIO_EXTICR2_EXTI7_Msk (0xFU << AFIO_EXTICR2_EXTI7_Pos) /*!< 0x0000F000 */
+#define AFIO_EXTICR2_EXTI7 AFIO_EXTICR2_EXTI7_Msk /*!< EXTI 7 configuration */
+
+/*!< EXTI4 configuration */
+#define AFIO_EXTICR2_EXTI4_PA ((uint32_t)0x00000000) /*!< PA[4] pin */
+#define AFIO_EXTICR2_EXTI4_PB_Pos (0U)
+#define AFIO_EXTICR2_EXTI4_PB_Msk (0x1U << AFIO_EXTICR2_EXTI4_PB_Pos) /*!< 0x00000001 */
+#define AFIO_EXTICR2_EXTI4_PB AFIO_EXTICR2_EXTI4_PB_Msk /*!< PB[4] pin */
+#define AFIO_EXTICR2_EXTI4_PC_Pos (1U)
+#define AFIO_EXTICR2_EXTI4_PC_Msk (0x1U << AFIO_EXTICR2_EXTI4_PC_Pos) /*!< 0x00000002 */
+#define AFIO_EXTICR2_EXTI4_PC AFIO_EXTICR2_EXTI4_PC_Msk /*!< PC[4] pin */
+#define AFIO_EXTICR2_EXTI4_PD_Pos (0U)
+#define AFIO_EXTICR2_EXTI4_PD_Msk (0x3U << AFIO_EXTICR2_EXTI4_PD_Pos) /*!< 0x00000003 */
+#define AFIO_EXTICR2_EXTI4_PD AFIO_EXTICR2_EXTI4_PD_Msk /*!< PD[4] pin */
+#define AFIO_EXTICR2_EXTI4_PE_Pos (2U)
+#define AFIO_EXTICR2_EXTI4_PE_Msk (0x1U << AFIO_EXTICR2_EXTI4_PE_Pos) /*!< 0x00000004 */
+#define AFIO_EXTICR2_EXTI4_PE AFIO_EXTICR2_EXTI4_PE_Msk /*!< PE[4] pin */
+#define AFIO_EXTICR2_EXTI4_PF_Pos (0U)
+#define AFIO_EXTICR2_EXTI4_PF_Msk (0x5U << AFIO_EXTICR2_EXTI4_PF_Pos) /*!< 0x00000005 */
+#define AFIO_EXTICR2_EXTI4_PF AFIO_EXTICR2_EXTI4_PF_Msk /*!< PF[4] pin */
+#define AFIO_EXTICR2_EXTI4_PG_Pos (1U)
+#define AFIO_EXTICR2_EXTI4_PG_Msk (0x3U << AFIO_EXTICR2_EXTI4_PG_Pos) /*!< 0x00000006 */
+#define AFIO_EXTICR2_EXTI4_PG AFIO_EXTICR2_EXTI4_PG_Msk /*!< PG[4] pin */
+
+/* EXTI5 configuration */
+#define AFIO_EXTICR2_EXTI5_PA ((uint32_t)0x00000000) /*!< PA[5] pin */
+#define AFIO_EXTICR2_EXTI5_PB_Pos (4U)
+#define AFIO_EXTICR2_EXTI5_PB_Msk (0x1U << AFIO_EXTICR2_EXTI5_PB_Pos) /*!< 0x00000010 */
+#define AFIO_EXTICR2_EXTI5_PB AFIO_EXTICR2_EXTI5_PB_Msk /*!< PB[5] pin */
+#define AFIO_EXTICR2_EXTI5_PC_Pos (5U)
+#define AFIO_EXTICR2_EXTI5_PC_Msk (0x1U << AFIO_EXTICR2_EXTI5_PC_Pos) /*!< 0x00000020 */
+#define AFIO_EXTICR2_EXTI5_PC AFIO_EXTICR2_EXTI5_PC_Msk /*!< PC[5] pin */
+#define AFIO_EXTICR2_EXTI5_PD_Pos (4U)
+#define AFIO_EXTICR2_EXTI5_PD_Msk (0x3U << AFIO_EXTICR2_EXTI5_PD_Pos) /*!< 0x00000030 */
+#define AFIO_EXTICR2_EXTI5_PD AFIO_EXTICR2_EXTI5_PD_Msk /*!< PD[5] pin */
+#define AFIO_EXTICR2_EXTI5_PE_Pos (6U)
+#define AFIO_EXTICR2_EXTI5_PE_Msk (0x1U << AFIO_EXTICR2_EXTI5_PE_Pos) /*!< 0x00000040 */
+#define AFIO_EXTICR2_EXTI5_PE AFIO_EXTICR2_EXTI5_PE_Msk /*!< PE[5] pin */
+#define AFIO_EXTICR2_EXTI5_PF_Pos (4U)
+#define AFIO_EXTICR2_EXTI5_PF_Msk (0x5U << AFIO_EXTICR2_EXTI5_PF_Pos) /*!< 0x00000050 */
+#define AFIO_EXTICR2_EXTI5_PF AFIO_EXTICR2_EXTI5_PF_Msk /*!< PF[5] pin */
+#define AFIO_EXTICR2_EXTI5_PG_Pos (5U)
+#define AFIO_EXTICR2_EXTI5_PG_Msk (0x3U << AFIO_EXTICR2_EXTI5_PG_Pos) /*!< 0x00000060 */
+#define AFIO_EXTICR2_EXTI5_PG AFIO_EXTICR2_EXTI5_PG_Msk /*!< PG[5] pin */
+
+/*!< EXTI6 configuration */
+#define AFIO_EXTICR2_EXTI6_PA ((uint32_t)0x00000000) /*!< PA[6] pin */
+#define AFIO_EXTICR2_EXTI6_PB_Pos (8U)
+#define AFIO_EXTICR2_EXTI6_PB_Msk (0x1U << AFIO_EXTICR2_EXTI6_PB_Pos) /*!< 0x00000100 */
+#define AFIO_EXTICR2_EXTI6_PB AFIO_EXTICR2_EXTI6_PB_Msk /*!< PB[6] pin */
+#define AFIO_EXTICR2_EXTI6_PC_Pos (9U)
+#define AFIO_EXTICR2_EXTI6_PC_Msk (0x1U << AFIO_EXTICR2_EXTI6_PC_Pos) /*!< 0x00000200 */
+#define AFIO_EXTICR2_EXTI6_PC AFIO_EXTICR2_EXTI6_PC_Msk /*!< PC[6] pin */
+#define AFIO_EXTICR2_EXTI6_PD_Pos (8U)
+#define AFIO_EXTICR2_EXTI6_PD_Msk (0x3U << AFIO_EXTICR2_EXTI6_PD_Pos) /*!< 0x00000300 */
+#define AFIO_EXTICR2_EXTI6_PD AFIO_EXTICR2_EXTI6_PD_Msk /*!< PD[6] pin */
+#define AFIO_EXTICR2_EXTI6_PE_Pos (10U)
+#define AFIO_EXTICR2_EXTI6_PE_Msk (0x1U << AFIO_EXTICR2_EXTI6_PE_Pos) /*!< 0x00000400 */
+#define AFIO_EXTICR2_EXTI6_PE AFIO_EXTICR2_EXTI6_PE_Msk /*!< PE[6] pin */
+#define AFIO_EXTICR2_EXTI6_PF_Pos (8U)
+#define AFIO_EXTICR2_EXTI6_PF_Msk (0x5U << AFIO_EXTICR2_EXTI6_PF_Pos) /*!< 0x00000500 */
+#define AFIO_EXTICR2_EXTI6_PF AFIO_EXTICR2_EXTI6_PF_Msk /*!< PF[6] pin */
+#define AFIO_EXTICR2_EXTI6_PG_Pos (9U)
+#define AFIO_EXTICR2_EXTI6_PG_Msk (0x3U << AFIO_EXTICR2_EXTI6_PG_Pos) /*!< 0x00000600 */
+#define AFIO_EXTICR2_EXTI6_PG AFIO_EXTICR2_EXTI6_PG_Msk /*!< PG[6] pin */
+
+/*!< EXTI7 configuration */
+#define AFIO_EXTICR2_EXTI7_PA ((uint32_t)0x00000000) /*!< PA[7] pin */
+#define AFIO_EXTICR2_EXTI7_PB_Pos (12U)
+#define AFIO_EXTICR2_EXTI7_PB_Msk (0x1U << AFIO_EXTICR2_EXTI7_PB_Pos) /*!< 0x00001000 */
+#define AFIO_EXTICR2_EXTI7_PB AFIO_EXTICR2_EXTI7_PB_Msk /*!< PB[7] pin */
+#define AFIO_EXTICR2_EXTI7_PC_Pos (13U)
+#define AFIO_EXTICR2_EXTI7_PC_Msk (0x1U << AFIO_EXTICR2_EXTI7_PC_Pos) /*!< 0x00002000 */
+#define AFIO_EXTICR2_EXTI7_PC AFIO_EXTICR2_EXTI7_PC_Msk /*!< PC[7] pin */
+#define AFIO_EXTICR2_EXTI7_PD_Pos (12U)
+#define AFIO_EXTICR2_EXTI7_PD_Msk (0x3U << AFIO_EXTICR2_EXTI7_PD_Pos) /*!< 0x00003000 */
+#define AFIO_EXTICR2_EXTI7_PD AFIO_EXTICR2_EXTI7_PD_Msk /*!< PD[7] pin */
+#define AFIO_EXTICR2_EXTI7_PE_Pos (14U)
+#define AFIO_EXTICR2_EXTI7_PE_Msk (0x1U << AFIO_EXTICR2_EXTI7_PE_Pos) /*!< 0x00004000 */
+#define AFIO_EXTICR2_EXTI7_PE AFIO_EXTICR2_EXTI7_PE_Msk /*!< PE[7] pin */
+#define AFIO_EXTICR2_EXTI7_PF_Pos (12U)
+#define AFIO_EXTICR2_EXTI7_PF_Msk (0x5U << AFIO_EXTICR2_EXTI7_PF_Pos) /*!< 0x00005000 */
+#define AFIO_EXTICR2_EXTI7_PF AFIO_EXTICR2_EXTI7_PF_Msk /*!< PF[7] pin */
+#define AFIO_EXTICR2_EXTI7_PG_Pos (13U)
+#define AFIO_EXTICR2_EXTI7_PG_Msk (0x3U << AFIO_EXTICR2_EXTI7_PG_Pos) /*!< 0x00006000 */
+#define AFIO_EXTICR2_EXTI7_PG AFIO_EXTICR2_EXTI7_PG_Msk /*!< PG[7] pin */
+
+/***************** Bit definition for AFIO_EXTICR3 register *****************/
+#define AFIO_EXTICR3_EXTI8_Pos (0U)
+#define AFIO_EXTICR3_EXTI8_Msk (0xFU << AFIO_EXTICR3_EXTI8_Pos) /*!< 0x0000000F */
+#define AFIO_EXTICR3_EXTI8 AFIO_EXTICR3_EXTI8_Msk /*!< EXTI 8 configuration */
+#define AFIO_EXTICR3_EXTI9_Pos (4U)
+#define AFIO_EXTICR3_EXTI9_Msk (0xFU << AFIO_EXTICR3_EXTI9_Pos) /*!< 0x000000F0 */
+#define AFIO_EXTICR3_EXTI9 AFIO_EXTICR3_EXTI9_Msk /*!< EXTI 9 configuration */
+#define AFIO_EXTICR3_EXTI10_Pos (8U)
+#define AFIO_EXTICR3_EXTI10_Msk (0xFU << AFIO_EXTICR3_EXTI10_Pos) /*!< 0x00000F00 */
+#define AFIO_EXTICR3_EXTI10 AFIO_EXTICR3_EXTI10_Msk /*!< EXTI 10 configuration */
+#define AFIO_EXTICR3_EXTI11_Pos (12U)
+#define AFIO_EXTICR3_EXTI11_Msk (0xFU << AFIO_EXTICR3_EXTI11_Pos) /*!< 0x0000F000 */
+#define AFIO_EXTICR3_EXTI11 AFIO_EXTICR3_EXTI11_Msk /*!< EXTI 11 configuration */
+
+/*!< EXTI8 configuration */
+#define AFIO_EXTICR3_EXTI8_PA ((uint32_t)0x00000000) /*!< PA[8] pin */
+#define AFIO_EXTICR3_EXTI8_PB_Pos (0U)
+#define AFIO_EXTICR3_EXTI8_PB_Msk (0x1U << AFIO_EXTICR3_EXTI8_PB_Pos) /*!< 0x00000001 */
+#define AFIO_EXTICR3_EXTI8_PB AFIO_EXTICR3_EXTI8_PB_Msk /*!< PB[8] pin */
+#define AFIO_EXTICR3_EXTI8_PC_Pos (1U)
+#define AFIO_EXTICR3_EXTI8_PC_Msk (0x1U << AFIO_EXTICR3_EXTI8_PC_Pos) /*!< 0x00000002 */
+#define AFIO_EXTICR3_EXTI8_PC AFIO_EXTICR3_EXTI8_PC_Msk /*!< PC[8] pin */
+#define AFIO_EXTICR3_EXTI8_PD_Pos (0U)
+#define AFIO_EXTICR3_EXTI8_PD_Msk (0x3U << AFIO_EXTICR3_EXTI8_PD_Pos) /*!< 0x00000003 */
+#define AFIO_EXTICR3_EXTI8_PD AFIO_EXTICR3_EXTI8_PD_Msk /*!< PD[8] pin */
+#define AFIO_EXTICR3_EXTI8_PE_Pos (2U)
+#define AFIO_EXTICR3_EXTI8_PE_Msk (0x1U << AFIO_EXTICR3_EXTI8_PE_Pos) /*!< 0x00000004 */
+#define AFIO_EXTICR3_EXTI8_PE AFIO_EXTICR3_EXTI8_PE_Msk /*!< PE[8] pin */
+#define AFIO_EXTICR3_EXTI8_PF_Pos (0U)
+#define AFIO_EXTICR3_EXTI8_PF_Msk (0x5U << AFIO_EXTICR3_EXTI8_PF_Pos) /*!< 0x00000005 */
+#define AFIO_EXTICR3_EXTI8_PF AFIO_EXTICR3_EXTI8_PF_Msk /*!< PF[8] pin */
+#define AFIO_EXTICR3_EXTI8_PG_Pos (1U)
+#define AFIO_EXTICR3_EXTI8_PG_Msk (0x3U << AFIO_EXTICR3_EXTI8_PG_Pos) /*!< 0x00000006 */
+#define AFIO_EXTICR3_EXTI8_PG AFIO_EXTICR3_EXTI8_PG_Msk /*!< PG[8] pin */
+
+/*!< EXTI9 configuration */
+#define AFIO_EXTICR3_EXTI9_PA ((uint32_t)0x00000000) /*!< PA[9] pin */
+#define AFIO_EXTICR3_EXTI9_PB_Pos (4U)
+#define AFIO_EXTICR3_EXTI9_PB_Msk (0x1U << AFIO_EXTICR3_EXTI9_PB_Pos) /*!< 0x00000010 */
+#define AFIO_EXTICR3_EXTI9_PB AFIO_EXTICR3_EXTI9_PB_Msk /*!< PB[9] pin */
+#define AFIO_EXTICR3_EXTI9_PC_Pos (5U)
+#define AFIO_EXTICR3_EXTI9_PC_Msk (0x1U << AFIO_EXTICR3_EXTI9_PC_Pos) /*!< 0x00000020 */
+#define AFIO_EXTICR3_EXTI9_PC AFIO_EXTICR3_EXTI9_PC_Msk /*!< PC[9] pin */
+#define AFIO_EXTICR3_EXTI9_PD_Pos (4U)
+#define AFIO_EXTICR3_EXTI9_PD_Msk (0x3U << AFIO_EXTICR3_EXTI9_PD_Pos) /*!< 0x00000030 */
+#define AFIO_EXTICR3_EXTI9_PD AFIO_EXTICR3_EXTI9_PD_Msk /*!< PD[9] pin */
+#define AFIO_EXTICR3_EXTI9_PE_Pos (6U)
+#define AFIO_EXTICR3_EXTI9_PE_Msk (0x1U << AFIO_EXTICR3_EXTI9_PE_Pos) /*!< 0x00000040 */
+#define AFIO_EXTICR3_EXTI9_PE AFIO_EXTICR3_EXTI9_PE_Msk /*!< PE[9] pin */
+#define AFIO_EXTICR3_EXTI9_PF_Pos (4U)
+#define AFIO_EXTICR3_EXTI9_PF_Msk (0x5U << AFIO_EXTICR3_EXTI9_PF_Pos) /*!< 0x00000050 */
+#define AFIO_EXTICR3_EXTI9_PF AFIO_EXTICR3_EXTI9_PF_Msk /*!< PF[9] pin */
+#define AFIO_EXTICR3_EXTI9_PG_Pos (5U)
+#define AFIO_EXTICR3_EXTI9_PG_Msk (0x3U << AFIO_EXTICR3_EXTI9_PG_Pos) /*!< 0x00000060 */
+#define AFIO_EXTICR3_EXTI9_PG AFIO_EXTICR3_EXTI9_PG_Msk /*!< PG[9] pin */
+
+/*!< EXTI10 configuration */
+#define AFIO_EXTICR3_EXTI10_PA ((uint32_t)0x00000000) /*!< PA[10] pin */
+#define AFIO_EXTICR3_EXTI10_PB_Pos (8U)
+#define AFIO_EXTICR3_EXTI10_PB_Msk (0x1U << AFIO_EXTICR3_EXTI10_PB_Pos) /*!< 0x00000100 */
+#define AFIO_EXTICR3_EXTI10_PB AFIO_EXTICR3_EXTI10_PB_Msk /*!< PB[10] pin */
+#define AFIO_EXTICR3_EXTI10_PC_Pos (9U)
+#define AFIO_EXTICR3_EXTI10_PC_Msk (0x1U << AFIO_EXTICR3_EXTI10_PC_Pos) /*!< 0x00000200 */
+#define AFIO_EXTICR3_EXTI10_PC AFIO_EXTICR3_EXTI10_PC_Msk /*!< PC[10] pin */
+#define AFIO_EXTICR3_EXTI10_PD_Pos (8U)
+#define AFIO_EXTICR3_EXTI10_PD_Msk (0x3U << AFIO_EXTICR3_EXTI10_PD_Pos) /*!< 0x00000300 */
+#define AFIO_EXTICR3_EXTI10_PD AFIO_EXTICR3_EXTI10_PD_Msk /*!< PD[10] pin */
+#define AFIO_EXTICR3_EXTI10_PE_Pos (10U)
+#define AFIO_EXTICR3_EXTI10_PE_Msk (0x1U << AFIO_EXTICR3_EXTI10_PE_Pos) /*!< 0x00000400 */
+#define AFIO_EXTICR3_EXTI10_PE AFIO_EXTICR3_EXTI10_PE_Msk /*!< PE[10] pin */
+#define AFIO_EXTICR3_EXTI10_PF_Pos (8U)
+#define AFIO_EXTICR3_EXTI10_PF_Msk (0x5U << AFIO_EXTICR3_EXTI10_PF_Pos) /*!< 0x00000500 */
+#define AFIO_EXTICR3_EXTI10_PF AFIO_EXTICR3_EXTI10_PF_Msk /*!< PF[10] pin */
+#define AFIO_EXTICR3_EXTI10_PG_Pos (9U)
+#define AFIO_EXTICR3_EXTI10_PG_Msk (0x3U << AFIO_EXTICR3_EXTI10_PG_Pos) /*!< 0x00000600 */
+#define AFIO_EXTICR3_EXTI10_PG AFIO_EXTICR3_EXTI10_PG_Msk /*!< PG[10] pin */
+
+/*!< EXTI11 configuration */
+#define AFIO_EXTICR3_EXTI11_PA ((uint32_t)0x00000000) /*!< PA[11] pin */
+#define AFIO_EXTICR3_EXTI11_PB_Pos (12U)
+#define AFIO_EXTICR3_EXTI11_PB_Msk (0x1U << AFIO_EXTICR3_EXTI11_PB_Pos) /*!< 0x00001000 */
+#define AFIO_EXTICR3_EXTI11_PB AFIO_EXTICR3_EXTI11_PB_Msk /*!< PB[11] pin */
+#define AFIO_EXTICR3_EXTI11_PC_Pos (13U)
+#define AFIO_EXTICR3_EXTI11_PC_Msk (0x1U << AFIO_EXTICR3_EXTI11_PC_Pos) /*!< 0x00002000 */
+#define AFIO_EXTICR3_EXTI11_PC AFIO_EXTICR3_EXTI11_PC_Msk /*!< PC[11] pin */
+#define AFIO_EXTICR3_EXTI11_PD_Pos (12U)
+#define AFIO_EXTICR3_EXTI11_PD_Msk (0x3U << AFIO_EXTICR3_EXTI11_PD_Pos) /*!< 0x00003000 */
+#define AFIO_EXTICR3_EXTI11_PD AFIO_EXTICR3_EXTI11_PD_Msk /*!< PD[11] pin */
+#define AFIO_EXTICR3_EXTI11_PE_Pos (14U)
+#define AFIO_EXTICR3_EXTI11_PE_Msk (0x1U << AFIO_EXTICR3_EXTI11_PE_Pos) /*!< 0x00004000 */
+#define AFIO_EXTICR3_EXTI11_PE AFIO_EXTICR3_EXTI11_PE_Msk /*!< PE[11] pin */
+#define AFIO_EXTICR3_EXTI11_PF_Pos (12U)
+#define AFIO_EXTICR3_EXTI11_PF_Msk (0x5U << AFIO_EXTICR3_EXTI11_PF_Pos) /*!< 0x00005000 */
+#define AFIO_EXTICR3_EXTI11_PF AFIO_EXTICR3_EXTI11_PF_Msk /*!< PF[11] pin */
+#define AFIO_EXTICR3_EXTI11_PG_Pos (13U)
+#define AFIO_EXTICR3_EXTI11_PG_Msk (0x3U << AFIO_EXTICR3_EXTI11_PG_Pos) /*!< 0x00006000 */
+#define AFIO_EXTICR3_EXTI11_PG AFIO_EXTICR3_EXTI11_PG_Msk /*!< PG[11] pin */
+
+/***************** Bit definition for AFIO_EXTICR4 register *****************/
+#define AFIO_EXTICR4_EXTI12_Pos (0U)
+#define AFIO_EXTICR4_EXTI12_Msk (0xFU << AFIO_EXTICR4_EXTI12_Pos) /*!< 0x0000000F */
+#define AFIO_EXTICR4_EXTI12 AFIO_EXTICR4_EXTI12_Msk /*!< EXTI 12 configuration */
+#define AFIO_EXTICR4_EXTI13_Pos (4U)
+#define AFIO_EXTICR4_EXTI13_Msk (0xFU << AFIO_EXTICR4_EXTI13_Pos) /*!< 0x000000F0 */
+#define AFIO_EXTICR4_EXTI13 AFIO_EXTICR4_EXTI13_Msk /*!< EXTI 13 configuration */
+#define AFIO_EXTICR4_EXTI14_Pos (8U)
+#define AFIO_EXTICR4_EXTI14_Msk (0xFU << AFIO_EXTICR4_EXTI14_Pos) /*!< 0x00000F00 */
+#define AFIO_EXTICR4_EXTI14 AFIO_EXTICR4_EXTI14_Msk /*!< EXTI 14 configuration */
+#define AFIO_EXTICR4_EXTI15_Pos (12U)
+#define AFIO_EXTICR4_EXTI15_Msk (0xFU << AFIO_EXTICR4_EXTI15_Pos) /*!< 0x0000F000 */
+#define AFIO_EXTICR4_EXTI15 AFIO_EXTICR4_EXTI15_Msk /*!< EXTI 15 configuration */
+
+/* EXTI12 configuration */
+#define AFIO_EXTICR4_EXTI12_PA ((uint32_t)0x00000000) /*!< PA[12] pin */
+#define AFIO_EXTICR4_EXTI12_PB_Pos (0U)
+#define AFIO_EXTICR4_EXTI12_PB_Msk (0x1U << AFIO_EXTICR4_EXTI12_PB_Pos) /*!< 0x00000001 */
+#define AFIO_EXTICR4_EXTI12_PB AFIO_EXTICR4_EXTI12_PB_Msk /*!< PB[12] pin */
+#define AFIO_EXTICR4_EXTI12_PC_Pos (1U)
+#define AFIO_EXTICR4_EXTI12_PC_Msk (0x1U << AFIO_EXTICR4_EXTI12_PC_Pos) /*!< 0x00000002 */
+#define AFIO_EXTICR4_EXTI12_PC AFIO_EXTICR4_EXTI12_PC_Msk /*!< PC[12] pin */
+#define AFIO_EXTICR4_EXTI12_PD_Pos (0U)
+#define AFIO_EXTICR4_EXTI12_PD_Msk (0x3U << AFIO_EXTICR4_EXTI12_PD_Pos) /*!< 0x00000003 */
+#define AFIO_EXTICR4_EXTI12_PD AFIO_EXTICR4_EXTI12_PD_Msk /*!< PD[12] pin */
+#define AFIO_EXTICR4_EXTI12_PE_Pos (2U)
+#define AFIO_EXTICR4_EXTI12_PE_Msk (0x1U << AFIO_EXTICR4_EXTI12_PE_Pos) /*!< 0x00000004 */
+#define AFIO_EXTICR4_EXTI12_PE AFIO_EXTICR4_EXTI12_PE_Msk /*!< PE[12] pin */
+#define AFIO_EXTICR4_EXTI12_PF_Pos (0U)
+#define AFIO_EXTICR4_EXTI12_PF_Msk (0x5U << AFIO_EXTICR4_EXTI12_PF_Pos) /*!< 0x00000005 */
+#define AFIO_EXTICR4_EXTI12_PF AFIO_EXTICR4_EXTI12_PF_Msk /*!< PF[12] pin */
+#define AFIO_EXTICR4_EXTI12_PG_Pos (1U)
+#define AFIO_EXTICR4_EXTI12_PG_Msk (0x3U << AFIO_EXTICR4_EXTI12_PG_Pos) /*!< 0x00000006 */
+#define AFIO_EXTICR4_EXTI12_PG AFIO_EXTICR4_EXTI12_PG_Msk /*!< PG[12] pin */
+
+/* EXTI13 configuration */
+#define AFIO_EXTICR4_EXTI13_PA ((uint32_t)0x00000000) /*!< PA[13] pin */
+#define AFIO_EXTICR4_EXTI13_PB_Pos (4U)
+#define AFIO_EXTICR4_EXTI13_PB_Msk (0x1U << AFIO_EXTICR4_EXTI13_PB_Pos) /*!< 0x00000010 */
+#define AFIO_EXTICR4_EXTI13_PB AFIO_EXTICR4_EXTI13_PB_Msk /*!< PB[13] pin */
+#define AFIO_EXTICR4_EXTI13_PC_Pos (5U)
+#define AFIO_EXTICR4_EXTI13_PC_Msk (0x1U << AFIO_EXTICR4_EXTI13_PC_Pos) /*!< 0x00000020 */
+#define AFIO_EXTICR4_EXTI13_PC AFIO_EXTICR4_EXTI13_PC_Msk /*!< PC[13] pin */
+#define AFIO_EXTICR4_EXTI13_PD_Pos (4U)
+#define AFIO_EXTICR4_EXTI13_PD_Msk (0x3U << AFIO_EXTICR4_EXTI13_PD_Pos) /*!< 0x00000030 */
+#define AFIO_EXTICR4_EXTI13_PD AFIO_EXTICR4_EXTI13_PD_Msk /*!< PD[13] pin */
+#define AFIO_EXTICR4_EXTI13_PE_Pos (6U)
+#define AFIO_EXTICR4_EXTI13_PE_Msk (0x1U << AFIO_EXTICR4_EXTI13_PE_Pos) /*!< 0x00000040 */
+#define AFIO_EXTICR4_EXTI13_PE AFIO_EXTICR4_EXTI13_PE_Msk /*!< PE[13] pin */
+#define AFIO_EXTICR4_EXTI13_PF_Pos (4U)
+#define AFIO_EXTICR4_EXTI13_PF_Msk (0x5U << AFIO_EXTICR4_EXTI13_PF_Pos) /*!< 0x00000050 */
+#define AFIO_EXTICR4_EXTI13_PF AFIO_EXTICR4_EXTI13_PF_Msk /*!< PF[13] pin */
+#define AFIO_EXTICR4_EXTI13_PG_Pos (5U)
+#define AFIO_EXTICR4_EXTI13_PG_Msk (0x3U << AFIO_EXTICR4_EXTI13_PG_Pos) /*!< 0x00000060 */
+#define AFIO_EXTICR4_EXTI13_PG AFIO_EXTICR4_EXTI13_PG_Msk /*!< PG[13] pin */
+
+/*!< EXTI14 configuration */
+#define AFIO_EXTICR4_EXTI14_PA ((uint32_t)0x00000000) /*!< PA[14] pin */
+#define AFIO_EXTICR4_EXTI14_PB_Pos (8U)
+#define AFIO_EXTICR4_EXTI14_PB_Msk (0x1U << AFIO_EXTICR4_EXTI14_PB_Pos) /*!< 0x00000100 */
+#define AFIO_EXTICR4_EXTI14_PB AFIO_EXTICR4_EXTI14_PB_Msk /*!< PB[14] pin */
+#define AFIO_EXTICR4_EXTI14_PC_Pos (9U)
+#define AFIO_EXTICR4_EXTI14_PC_Msk (0x1U << AFIO_EXTICR4_EXTI14_PC_Pos) /*!< 0x00000200 */
+#define AFIO_EXTICR4_EXTI14_PC AFIO_EXTICR4_EXTI14_PC_Msk /*!< PC[14] pin */
+#define AFIO_EXTICR4_EXTI14_PD_Pos (8U)
+#define AFIO_EXTICR4_EXTI14_PD_Msk (0x3U << AFIO_EXTICR4_EXTI14_PD_Pos) /*!< 0x00000300 */
+#define AFIO_EXTICR4_EXTI14_PD AFIO_EXTICR4_EXTI14_PD_Msk /*!< PD[14] pin */
+#define AFIO_EXTICR4_EXTI14_PE_Pos (10U)
+#define AFIO_EXTICR4_EXTI14_PE_Msk (0x1U << AFIO_EXTICR4_EXTI14_PE_Pos) /*!< 0x00000400 */
+#define AFIO_EXTICR4_EXTI14_PE AFIO_EXTICR4_EXTI14_PE_Msk /*!< PE[14] pin */
+#define AFIO_EXTICR4_EXTI14_PF_Pos (8U)
+#define AFIO_EXTICR4_EXTI14_PF_Msk (0x5U << AFIO_EXTICR4_EXTI14_PF_Pos) /*!< 0x00000500 */
+#define AFIO_EXTICR4_EXTI14_PF AFIO_EXTICR4_EXTI14_PF_Msk /*!< PF[14] pin */
+#define AFIO_EXTICR4_EXTI14_PG_Pos (9U)
+#define AFIO_EXTICR4_EXTI14_PG_Msk (0x3U << AFIO_EXTICR4_EXTI14_PG_Pos) /*!< 0x00000600 */
+#define AFIO_EXTICR4_EXTI14_PG AFIO_EXTICR4_EXTI14_PG_Msk /*!< PG[14] pin */
+
+/*!< EXTI15 configuration */
+#define AFIO_EXTICR4_EXTI15_PA ((uint32_t)0x00000000) /*!< PA[15] pin */
+#define AFIO_EXTICR4_EXTI15_PB_Pos (12U)
+#define AFIO_EXTICR4_EXTI15_PB_Msk (0x1U << AFIO_EXTICR4_EXTI15_PB_Pos) /*!< 0x00001000 */
+#define AFIO_EXTICR4_EXTI15_PB AFIO_EXTICR4_EXTI15_PB_Msk /*!< PB[15] pin */
+#define AFIO_EXTICR4_EXTI15_PC_Pos (13U)
+#define AFIO_EXTICR4_EXTI15_PC_Msk (0x1U << AFIO_EXTICR4_EXTI15_PC_Pos) /*!< 0x00002000 */
+#define AFIO_EXTICR4_EXTI15_PC AFIO_EXTICR4_EXTI15_PC_Msk /*!< PC[15] pin */
+#define AFIO_EXTICR4_EXTI15_PD_Pos (12U)
+#define AFIO_EXTICR4_EXTI15_PD_Msk (0x3U << AFIO_EXTICR4_EXTI15_PD_Pos) /*!< 0x00003000 */
+#define AFIO_EXTICR4_EXTI15_PD AFIO_EXTICR4_EXTI15_PD_Msk /*!< PD[15] pin */
+#define AFIO_EXTICR4_EXTI15_PE_Pos (14U)
+#define AFIO_EXTICR4_EXTI15_PE_Msk (0x1U << AFIO_EXTICR4_EXTI15_PE_Pos) /*!< 0x00004000 */
+#define AFIO_EXTICR4_EXTI15_PE AFIO_EXTICR4_EXTI15_PE_Msk /*!< PE[15] pin */
+#define AFIO_EXTICR4_EXTI15_PF_Pos (12U)
+#define AFIO_EXTICR4_EXTI15_PF_Msk (0x5U << AFIO_EXTICR4_EXTI15_PF_Pos) /*!< 0x00005000 */
+#define AFIO_EXTICR4_EXTI15_PF AFIO_EXTICR4_EXTI15_PF_Msk /*!< PF[15] pin */
+#define AFIO_EXTICR4_EXTI15_PG_Pos (13U)
+#define AFIO_EXTICR4_EXTI15_PG_Msk (0x3U << AFIO_EXTICR4_EXTI15_PG_Pos) /*!< 0x00006000 */
+#define AFIO_EXTICR4_EXTI15_PG AFIO_EXTICR4_EXTI15_PG_Msk /*!< PG[15] pin */
+
+/****************** Bit definition for AFIO_MAPR2 register ******************/
+
+
+
+/******************************************************************************/
+/* */
+/* SystemTick */
+/* */
+/******************************************************************************/
+
+/***************** Bit definition for SysTick_CTRL register *****************/
+#define SysTick_CTRL_ENABLE ((uint32_t)0x00000001) /*!< Counter enable */
+#define SysTick_CTRL_TICKINT ((uint32_t)0x00000002) /*!< Counting down to 0 pends the SysTick handler */
+#define SysTick_CTRL_CLKSOURCE ((uint32_t)0x00000004) /*!< Clock source */
+#define SysTick_CTRL_COUNTFLAG ((uint32_t)0x00010000) /*!< Count Flag */
+
+/***************** Bit definition for SysTick_LOAD register *****************/
+#define SysTick_LOAD_RELOAD ((uint32_t)0x00FFFFFF) /*!< Value to load into the SysTick Current Value Register when the counter reaches 0 */
+
+/***************** Bit definition for SysTick_VAL register ******************/
+#define SysTick_VAL_CURRENT ((uint32_t)0x00FFFFFF) /*!< Current value at the time the register is accessed */
+
+/***************** Bit definition for SysTick_CALIB register ****************/
+#define SysTick_CALIB_TENMS ((uint32_t)0x00FFFFFF) /*!< Reload value to use for 10ms timing */
+#define SysTick_CALIB_SKEW ((uint32_t)0x40000000) /*!< Calibration value is not exactly 10 ms */
+#define SysTick_CALIB_NOREF ((uint32_t)0x80000000) /*!< The reference clock is not provided */
+
+/******************************************************************************/
+/* */
+/* Nested Vectored Interrupt Controller */
+/* */
+/******************************************************************************/
+
+/****************** Bit definition for NVIC_ISER register *******************/
+#define NVIC_ISER_SETENA_Pos (0U)
+#define NVIC_ISER_SETENA_Msk (0xFFFFFFFFU << NVIC_ISER_SETENA_Pos) /*!< 0xFFFFFFFF */
+#define NVIC_ISER_SETENA NVIC_ISER_SETENA_Msk /*!< Interrupt set enable bits */
+#define NVIC_ISER_SETENA_0 (0x00000001U << NVIC_ISER_SETENA_Pos) /*!< 0x00000001 */
+#define NVIC_ISER_SETENA_1 (0x00000002U << NVIC_ISER_SETENA_Pos) /*!< 0x00000002 */
+#define NVIC_ISER_SETENA_2 (0x00000004U << NVIC_ISER_SETENA_Pos) /*!< 0x00000004 */
+#define NVIC_ISER_SETENA_3 (0x00000008U << NVIC_ISER_SETENA_Pos) /*!< 0x00000008 */
+#define NVIC_ISER_SETENA_4 (0x00000010U << NVIC_ISER_SETENA_Pos) /*!< 0x00000010 */
+#define NVIC_ISER_SETENA_5 (0x00000020U << NVIC_ISER_SETENA_Pos) /*!< 0x00000020 */
+#define NVIC_ISER_SETENA_6 (0x00000040U << NVIC_ISER_SETENA_Pos) /*!< 0x00000040 */
+#define NVIC_ISER_SETENA_7 (0x00000080U << NVIC_ISER_SETENA_Pos) /*!< 0x00000080 */
+#define NVIC_ISER_SETENA_8 (0x00000100U << NVIC_ISER_SETENA_Pos) /*!< 0x00000100 */
+#define NVIC_ISER_SETENA_9 (0x00000200U << NVIC_ISER_SETENA_Pos) /*!< 0x00000200 */
+#define NVIC_ISER_SETENA_10 (0x00000400U << NVIC_ISER_SETENA_Pos) /*!< 0x00000400 */
+#define NVIC_ISER_SETENA_11 (0x00000800U << NVIC_ISER_SETENA_Pos) /*!< 0x00000800 */
+#define NVIC_ISER_SETENA_12 (0x00001000U << NVIC_ISER_SETENA_Pos) /*!< 0x00001000 */
+#define NVIC_ISER_SETENA_13 (0x00002000U << NVIC_ISER_SETENA_Pos) /*!< 0x00002000 */
+#define NVIC_ISER_SETENA_14 (0x00004000U << NVIC_ISER_SETENA_Pos) /*!< 0x00004000 */
+#define NVIC_ISER_SETENA_15 (0x00008000U << NVIC_ISER_SETENA_Pos) /*!< 0x00008000 */
+#define NVIC_ISER_SETENA_16 (0x00010000U << NVIC_ISER_SETENA_Pos) /*!< 0x00010000 */
+#define NVIC_ISER_SETENA_17 (0x00020000U << NVIC_ISER_SETENA_Pos) /*!< 0x00020000 */
+#define NVIC_ISER_SETENA_18 (0x00040000U << NVIC_ISER_SETENA_Pos) /*!< 0x00040000 */
+#define NVIC_ISER_SETENA_19 (0x00080000U << NVIC_ISER_SETENA_Pos) /*!< 0x00080000 */
+#define NVIC_ISER_SETENA_20 (0x00100000U << NVIC_ISER_SETENA_Pos) /*!< 0x00100000 */
+#define NVIC_ISER_SETENA_21 (0x00200000U << NVIC_ISER_SETENA_Pos) /*!< 0x00200000 */
+#define NVIC_ISER_SETENA_22 (0x00400000U << NVIC_ISER_SETENA_Pos) /*!< 0x00400000 */
+#define NVIC_ISER_SETENA_23 (0x00800000U << NVIC_ISER_SETENA_Pos) /*!< 0x00800000 */
+#define NVIC_ISER_SETENA_24 (0x01000000U << NVIC_ISER_SETENA_Pos) /*!< 0x01000000 */
+#define NVIC_ISER_SETENA_25 (0x02000000U << NVIC_ISER_SETENA_Pos) /*!< 0x02000000 */
+#define NVIC_ISER_SETENA_26 (0x04000000U << NVIC_ISER_SETENA_Pos) /*!< 0x04000000 */
+#define NVIC_ISER_SETENA_27 (0x08000000U << NVIC_ISER_SETENA_Pos) /*!< 0x08000000 */
+#define NVIC_ISER_SETENA_28 (0x10000000U << NVIC_ISER_SETENA_Pos) /*!< 0x10000000 */
+#define NVIC_ISER_SETENA_29 (0x20000000U << NVIC_ISER_SETENA_Pos) /*!< 0x20000000 */
+#define NVIC_ISER_SETENA_30 (0x40000000U << NVIC_ISER_SETENA_Pos) /*!< 0x40000000 */
+#define NVIC_ISER_SETENA_31 (0x80000000U << NVIC_ISER_SETENA_Pos) /*!< 0x80000000 */
+
+/****************** Bit definition for NVIC_ICER register *******************/
+#define NVIC_ICER_CLRENA_Pos (0U)
+#define NVIC_ICER_CLRENA_Msk (0xFFFFFFFFU << NVIC_ICER_CLRENA_Pos) /*!< 0xFFFFFFFF */
+#define NVIC_ICER_CLRENA NVIC_ICER_CLRENA_Msk /*!< Interrupt clear-enable bits */
+#define NVIC_ICER_CLRENA_0 (0x00000001U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000001 */
+#define NVIC_ICER_CLRENA_1 (0x00000002U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000002 */
+#define NVIC_ICER_CLRENA_2 (0x00000004U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000004 */
+#define NVIC_ICER_CLRENA_3 (0x00000008U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000008 */
+#define NVIC_ICER_CLRENA_4 (0x00000010U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000010 */
+#define NVIC_ICER_CLRENA_5 (0x00000020U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000020 */
+#define NVIC_ICER_CLRENA_6 (0x00000040U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000040 */
+#define NVIC_ICER_CLRENA_7 (0x00000080U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000080 */
+#define NVIC_ICER_CLRENA_8 (0x00000100U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000100 */
+#define NVIC_ICER_CLRENA_9 (0x00000200U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000200 */
+#define NVIC_ICER_CLRENA_10 (0x00000400U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000400 */
+#define NVIC_ICER_CLRENA_11 (0x00000800U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000800 */
+#define NVIC_ICER_CLRENA_12 (0x00001000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00001000 */
+#define NVIC_ICER_CLRENA_13 (0x00002000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00002000 */
+#define NVIC_ICER_CLRENA_14 (0x00004000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00004000 */
+#define NVIC_ICER_CLRENA_15 (0x00008000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00008000 */
+#define NVIC_ICER_CLRENA_16 (0x00010000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00010000 */
+#define NVIC_ICER_CLRENA_17 (0x00020000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00020000 */
+#define NVIC_ICER_CLRENA_18 (0x00040000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00040000 */
+#define NVIC_ICER_CLRENA_19 (0x00080000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00080000 */
+#define NVIC_ICER_CLRENA_20 (0x00100000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00100000 */
+#define NVIC_ICER_CLRENA_21 (0x00200000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00200000 */
+#define NVIC_ICER_CLRENA_22 (0x00400000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00400000 */
+#define NVIC_ICER_CLRENA_23 (0x00800000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00800000 */
+#define NVIC_ICER_CLRENA_24 (0x01000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x01000000 */
+#define NVIC_ICER_CLRENA_25 (0x02000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x02000000 */
+#define NVIC_ICER_CLRENA_26 (0x04000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x04000000 */
+#define NVIC_ICER_CLRENA_27 (0x08000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x08000000 */
+#define NVIC_ICER_CLRENA_28 (0x10000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x10000000 */
+#define NVIC_ICER_CLRENA_29 (0x20000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x20000000 */
+#define NVIC_ICER_CLRENA_30 (0x40000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x40000000 */
+#define NVIC_ICER_CLRENA_31 (0x80000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x80000000 */
+
+/****************** Bit definition for NVIC_ISPR register *******************/
+#define NVIC_ISPR_SETPEND_Pos (0U)
+#define NVIC_ISPR_SETPEND_Msk (0xFFFFFFFFU << NVIC_ISPR_SETPEND_Pos) /*!< 0xFFFFFFFF */
+#define NVIC_ISPR_SETPEND NVIC_ISPR_SETPEND_Msk /*!< Interrupt set-pending bits */
+#define NVIC_ISPR_SETPEND_0 (0x00000001U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000001 */
+#define NVIC_ISPR_SETPEND_1 (0x00000002U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000002 */
+#define NVIC_ISPR_SETPEND_2 (0x00000004U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000004 */
+#define NVIC_ISPR_SETPEND_3 (0x00000008U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000008 */
+#define NVIC_ISPR_SETPEND_4 (0x00000010U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000010 */
+#define NVIC_ISPR_SETPEND_5 (0x00000020U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000020 */
+#define NVIC_ISPR_SETPEND_6 (0x00000040U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000040 */
+#define NVIC_ISPR_SETPEND_7 (0x00000080U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000080 */
+#define NVIC_ISPR_SETPEND_8 (0x00000100U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000100 */
+#define NVIC_ISPR_SETPEND_9 (0x00000200U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000200 */
+#define NVIC_ISPR_SETPEND_10 (0x00000400U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000400 */
+#define NVIC_ISPR_SETPEND_11 (0x00000800U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000800 */
+#define NVIC_ISPR_SETPEND_12 (0x00001000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00001000 */
+#define NVIC_ISPR_SETPEND_13 (0x00002000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00002000 */
+#define NVIC_ISPR_SETPEND_14 (0x00004000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00004000 */
+#define NVIC_ISPR_SETPEND_15 (0x00008000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00008000 */
+#define NVIC_ISPR_SETPEND_16 (0x00010000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00010000 */
+#define NVIC_ISPR_SETPEND_17 (0x00020000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00020000 */
+#define NVIC_ISPR_SETPEND_18 (0x00040000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00040000 */
+#define NVIC_ISPR_SETPEND_19 (0x00080000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00080000 */
+#define NVIC_ISPR_SETPEND_20 (0x00100000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00100000 */
+#define NVIC_ISPR_SETPEND_21 (0x00200000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00200000 */
+#define NVIC_ISPR_SETPEND_22 (0x00400000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00400000 */
+#define NVIC_ISPR_SETPEND_23 (0x00800000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00800000 */
+#define NVIC_ISPR_SETPEND_24 (0x01000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x01000000 */
+#define NVIC_ISPR_SETPEND_25 (0x02000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x02000000 */
+#define NVIC_ISPR_SETPEND_26 (0x04000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x04000000 */
+#define NVIC_ISPR_SETPEND_27 (0x08000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x08000000 */
+#define NVIC_ISPR_SETPEND_28 (0x10000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x10000000 */
+#define NVIC_ISPR_SETPEND_29 (0x20000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x20000000 */
+#define NVIC_ISPR_SETPEND_30 (0x40000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x40000000 */
+#define NVIC_ISPR_SETPEND_31 (0x80000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x80000000 */
+
+/****************** Bit definition for NVIC_ICPR register *******************/
+#define NVIC_ICPR_CLRPEND_Pos (0U)
+#define NVIC_ICPR_CLRPEND_Msk (0xFFFFFFFFU << NVIC_ICPR_CLRPEND_Pos) /*!< 0xFFFFFFFF */
+#define NVIC_ICPR_CLRPEND NVIC_ICPR_CLRPEND_Msk /*!< Interrupt clear-pending bits */
+#define NVIC_ICPR_CLRPEND_0 (0x00000001U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000001 */
+#define NVIC_ICPR_CLRPEND_1 (0x00000002U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000002 */
+#define NVIC_ICPR_CLRPEND_2 (0x00000004U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000004 */
+#define NVIC_ICPR_CLRPEND_3 (0x00000008U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000008 */
+#define NVIC_ICPR_CLRPEND_4 (0x00000010U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000010 */
+#define NVIC_ICPR_CLRPEND_5 (0x00000020U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000020 */
+#define NVIC_ICPR_CLRPEND_6 (0x00000040U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000040 */
+#define NVIC_ICPR_CLRPEND_7 (0x00000080U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000080 */
+#define NVIC_ICPR_CLRPEND_8 (0x00000100U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000100 */
+#define NVIC_ICPR_CLRPEND_9 (0x00000200U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000200 */
+#define NVIC_ICPR_CLRPEND_10 (0x00000400U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000400 */
+#define NVIC_ICPR_CLRPEND_11 (0x00000800U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000800 */
+#define NVIC_ICPR_CLRPEND_12 (0x00001000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00001000 */
+#define NVIC_ICPR_CLRPEND_13 (0x00002000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00002000 */
+#define NVIC_ICPR_CLRPEND_14 (0x00004000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00004000 */
+#define NVIC_ICPR_CLRPEND_15 (0x00008000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00008000 */
+#define NVIC_ICPR_CLRPEND_16 (0x00010000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00010000 */
+#define NVIC_ICPR_CLRPEND_17 (0x00020000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00020000 */
+#define NVIC_ICPR_CLRPEND_18 (0x00040000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00040000 */
+#define NVIC_ICPR_CLRPEND_19 (0x00080000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00080000 */
+#define NVIC_ICPR_CLRPEND_20 (0x00100000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00100000 */
+#define NVIC_ICPR_CLRPEND_21 (0x00200000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00200000 */
+#define NVIC_ICPR_CLRPEND_22 (0x00400000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00400000 */
+#define NVIC_ICPR_CLRPEND_23 (0x00800000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00800000 */
+#define NVIC_ICPR_CLRPEND_24 (0x01000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x01000000 */
+#define NVIC_ICPR_CLRPEND_25 (0x02000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x02000000 */
+#define NVIC_ICPR_CLRPEND_26 (0x04000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x04000000 */
+#define NVIC_ICPR_CLRPEND_27 (0x08000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x08000000 */
+#define NVIC_ICPR_CLRPEND_28 (0x10000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x10000000 */
+#define NVIC_ICPR_CLRPEND_29 (0x20000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x20000000 */
+#define NVIC_ICPR_CLRPEND_30 (0x40000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x40000000 */
+#define NVIC_ICPR_CLRPEND_31 (0x80000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x80000000 */
+
+/****************** Bit definition for NVIC_IABR register *******************/
+#define NVIC_IABR_ACTIVE_Pos (0U)
+#define NVIC_IABR_ACTIVE_Msk (0xFFFFFFFFU << NVIC_IABR_ACTIVE_Pos) /*!< 0xFFFFFFFF */
+#define NVIC_IABR_ACTIVE NVIC_IABR_ACTIVE_Msk /*!< Interrupt active flags */
+#define NVIC_IABR_ACTIVE_0 (0x00000001U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000001 */
+#define NVIC_IABR_ACTIVE_1 (0x00000002U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000002 */
+#define NVIC_IABR_ACTIVE_2 (0x00000004U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000004 */
+#define NVIC_IABR_ACTIVE_3 (0x00000008U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000008 */
+#define NVIC_IABR_ACTIVE_4 (0x00000010U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000010 */
+#define NVIC_IABR_ACTIVE_5 (0x00000020U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000020 */
+#define NVIC_IABR_ACTIVE_6 (0x00000040U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000040 */
+#define NVIC_IABR_ACTIVE_7 (0x00000080U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000080 */
+#define NVIC_IABR_ACTIVE_8 (0x00000100U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000100 */
+#define NVIC_IABR_ACTIVE_9 (0x00000200U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000200 */
+#define NVIC_IABR_ACTIVE_10 (0x00000400U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000400 */
+#define NVIC_IABR_ACTIVE_11 (0x00000800U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000800 */
+#define NVIC_IABR_ACTIVE_12 (0x00001000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00001000 */
+#define NVIC_IABR_ACTIVE_13 (0x00002000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00002000 */
+#define NVIC_IABR_ACTIVE_14 (0x00004000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00004000 */
+#define NVIC_IABR_ACTIVE_15 (0x00008000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00008000 */
+#define NVIC_IABR_ACTIVE_16 (0x00010000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00010000 */
+#define NVIC_IABR_ACTIVE_17 (0x00020000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00020000 */
+#define NVIC_IABR_ACTIVE_18 (0x00040000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00040000 */
+#define NVIC_IABR_ACTIVE_19 (0x00080000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00080000 */
+#define NVIC_IABR_ACTIVE_20 (0x00100000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00100000 */
+#define NVIC_IABR_ACTIVE_21 (0x00200000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00200000 */
+#define NVIC_IABR_ACTIVE_22 (0x00400000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00400000 */
+#define NVIC_IABR_ACTIVE_23 (0x00800000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00800000 */
+#define NVIC_IABR_ACTIVE_24 (0x01000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x01000000 */
+#define NVIC_IABR_ACTIVE_25 (0x02000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x02000000 */
+#define NVIC_IABR_ACTIVE_26 (0x04000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x04000000 */
+#define NVIC_IABR_ACTIVE_27 (0x08000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x08000000 */
+#define NVIC_IABR_ACTIVE_28 (0x10000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x10000000 */
+#define NVIC_IABR_ACTIVE_29 (0x20000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x20000000 */
+#define NVIC_IABR_ACTIVE_30 (0x40000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x40000000 */
+#define NVIC_IABR_ACTIVE_31 (0x80000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x80000000 */
+
+/****************** Bit definition for NVIC_PRI0 register *******************/
+#define NVIC_IPR0_PRI_0 ((uint32_t)0x000000FF) /*!< Priority of interrupt 0 */
+#define NVIC_IPR0_PRI_1 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 1 */
+#define NVIC_IPR0_PRI_2 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 2 */
+#define NVIC_IPR0_PRI_3 ((uint32_t)0xFF000000) /*!< Priority of interrupt 3 */
+
+/****************** Bit definition for NVIC_PRI1 register *******************/
+#define NVIC_IPR1_PRI_4 ((uint32_t)0x000000FF) /*!< Priority of interrupt 4 */
+#define NVIC_IPR1_PRI_5 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 5 */
+#define NVIC_IPR1_PRI_6 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 6 */
+#define NVIC_IPR1_PRI_7 ((uint32_t)0xFF000000) /*!< Priority of interrupt 7 */
+
+/****************** Bit definition for NVIC_PRI2 register *******************/
+#define NVIC_IPR2_PRI_8 ((uint32_t)0x000000FF) /*!< Priority of interrupt 8 */
+#define NVIC_IPR2_PRI_9 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 9 */
+#define NVIC_IPR2_PRI_10 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 10 */
+#define NVIC_IPR2_PRI_11 ((uint32_t)0xFF000000) /*!< Priority of interrupt 11 */
+
+/****************** Bit definition for NVIC_PRI3 register *******************/
+#define NVIC_IPR3_PRI_12 ((uint32_t)0x000000FF) /*!< Priority of interrupt 12 */
+#define NVIC_IPR3_PRI_13 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 13 */
+#define NVIC_IPR3_PRI_14 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 14 */
+#define NVIC_IPR3_PRI_15 ((uint32_t)0xFF000000) /*!< Priority of interrupt 15 */
+
+/****************** Bit definition for NVIC_PRI4 register *******************/
+#define NVIC_IPR4_PRI_16 ((uint32_t)0x000000FF) /*!< Priority of interrupt 16 */
+#define NVIC_IPR4_PRI_17 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 17 */
+#define NVIC_IPR4_PRI_18 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 18 */
+#define NVIC_IPR4_PRI_19 ((uint32_t)0xFF000000) /*!< Priority of interrupt 19 */
+
+/****************** Bit definition for NVIC_PRI5 register *******************/
+#define NVIC_IPR5_PRI_20 ((uint32_t)0x000000FF) /*!< Priority of interrupt 20 */
+#define NVIC_IPR5_PRI_21 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 21 */
+#define NVIC_IPR5_PRI_22 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 22 */
+#define NVIC_IPR5_PRI_23 ((uint32_t)0xFF000000) /*!< Priority of interrupt 23 */
+
+/****************** Bit definition for NVIC_PRI6 register *******************/
+#define NVIC_IPR6_PRI_24 ((uint32_t)0x000000FF) /*!< Priority of interrupt 24 */
+#define NVIC_IPR6_PRI_25 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 25 */
+#define NVIC_IPR6_PRI_26 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 26 */
+#define NVIC_IPR6_PRI_27 ((uint32_t)0xFF000000) /*!< Priority of interrupt 27 */
+
+/****************** Bit definition for NVIC_PRI7 register *******************/
+#define NVIC_IPR7_PRI_28 ((uint32_t)0x000000FF) /*!< Priority of interrupt 28 */
+#define NVIC_IPR7_PRI_29 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 29 */
+#define NVIC_IPR7_PRI_30 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 30 */
+#define NVIC_IPR7_PRI_31 ((uint32_t)0xFF000000) /*!< Priority of interrupt 31 */
+
+/****************** Bit definition for SCB_CPUID register *******************/
+#define SCB_CPUID_REVISION ((uint32_t)0x0000000F) /*!< Implementation defined revision number */
+#define SCB_CPUID_PARTNO ((uint32_t)0x0000FFF0) /*!< Number of processor within family */
+#define SCB_CPUID_Constant ((uint32_t)0x000F0000) /*!< Reads as 0x0F */
+#define SCB_CPUID_VARIANT ((uint32_t)0x00F00000) /*!< Implementation defined variant number */
+#define SCB_CPUID_IMPLEMENTER ((uint32_t)0xFF000000) /*!< Implementer code. ARM is 0x41 */
+
+/******************* Bit definition for SCB_ICSR register *******************/
+#define SCB_ICSR_VECTACTIVE ((uint32_t)0x000001FF) /*!< Active ISR number field */
+#define SCB_ICSR_RETTOBASE ((uint32_t)0x00000800) /*!< All active exceptions minus the IPSR_current_exception yields the empty set */
+#define SCB_ICSR_VECTPENDING ((uint32_t)0x003FF000) /*!< Pending ISR number field */
+#define SCB_ICSR_ISRPENDING ((uint32_t)0x00400000) /*!< Interrupt pending flag */
+#define SCB_ICSR_ISRPREEMPT ((uint32_t)0x00800000) /*!< It indicates that a pending interrupt becomes active in the next running cycle */
+#define SCB_ICSR_PENDSTCLR ((uint32_t)0x02000000) /*!< Clear pending SysTick bit */
+#define SCB_ICSR_PENDSTSET ((uint32_t)0x04000000) /*!< Set pending SysTick bit */
+#define SCB_ICSR_PENDSVCLR ((uint32_t)0x08000000) /*!< Clear pending pendSV bit */
+#define SCB_ICSR_PENDSVSET ((uint32_t)0x10000000) /*!< Set pending pendSV bit */
+#define SCB_ICSR_NMIPENDSET ((uint32_t)0x80000000) /*!< Set pending NMI bit */
+
+/******************* Bit definition for SCB_VTOR register *******************/
+#define SCB_VTOR_TBLOFF ((uint32_t)0x1FFFFF80) /*!< Vector table base offset field */
+#define SCB_VTOR_TBLBASE ((uint32_t)0x20000000) /*!< Table base in code(0) or RAM(1) */
+
+/*!<***************** Bit definition for SCB_AIRCR register *******************/
+#define SCB_AIRCR_VECTRESET ((uint32_t)0x00000001) /*!< System Reset bit */
+#define SCB_AIRCR_VECTCLRACTIVE ((uint32_t)0x00000002) /*!< Clear active vector bit */
+#define SCB_AIRCR_SYSRESETREQ ((uint32_t)0x00000004) /*!< Requests chip control logic to generate a reset */
+
+#define SCB_AIRCR_PRIGROUP ((uint32_t)0x00000700) /*!< PRIGROUP[2:0] bits (Priority group) */
+#define SCB_AIRCR_PRIGROUP_0 ((uint32_t)0x00000100) /*!< Bit 0 */
+#define SCB_AIRCR_PRIGROUP_1 ((uint32_t)0x00000200) /*!< Bit 1 */
+#define SCB_AIRCR_PRIGROUP_2 ((uint32_t)0x00000400) /*!< Bit 2 */
+
+/* prority group configuration */
+#define SCB_AIRCR_PRIGROUP0 ((uint32_t)0x00000000) /*!< Priority group=0 (7 bits of pre-emption priority, 1 bit of subpriority) */
+#define SCB_AIRCR_PRIGROUP1 ((uint32_t)0x00000100) /*!< Priority group=1 (6 bits of pre-emption priority, 2 bits of subpriority) */
+#define SCB_AIRCR_PRIGROUP2 ((uint32_t)0x00000200) /*!< Priority group=2 (5 bits of pre-emption priority, 3 bits of subpriority) */
+#define SCB_AIRCR_PRIGROUP3 ((uint32_t)0x00000300) /*!< Priority group=3 (4 bits of pre-emption priority, 4 bits of subpriority) */
+#define SCB_AIRCR_PRIGROUP4 ((uint32_t)0x00000400) /*!< Priority group=4 (3 bits of pre-emption priority, 5 bits of subpriority) */
+#define SCB_AIRCR_PRIGROUP5 ((uint32_t)0x00000500) /*!< Priority group=5 (2 bits of pre-emption priority, 6 bits of subpriority) */
+#define SCB_AIRCR_PRIGROUP6 ((uint32_t)0x00000600) /*!< Priority group=6 (1 bit of pre-emption priority, 7 bits of subpriority) */
+#define SCB_AIRCR_PRIGROUP7 ((uint32_t)0x00000700) /*!< Priority group=7 (no pre-emption priority, 8 bits of subpriority) */
+
+#define SCB_AIRCR_ENDIANESS ((uint32_t)0x00008000) /*!< Data endianness bit */
+#define SCB_AIRCR_VECTKEY ((uint32_t)0xFFFF0000) /*!< Register key (VECTKEY) - Reads as 0xFA05 (VECTKEYSTAT) */
+
+/******************* Bit definition for SCB_SCR register ********************/
+#define SCB_SCR_SLEEPONEXIT ((uint32_t)0x00000002) /*!< Sleep on exit bit */
+#define SCB_SCR_SLEEPDEEP ((uint32_t)0x00000004) /*!< Sleep deep bit */
+#define SCB_SCR_SEVONPEND ((uint32_t)0x00000010) /*!< Wake up from WFE */
+
+/******************** Bit definition for SCB_CCR register *******************/
+#define SCB_CCR_NONBASETHRDENA ((uint32_t)0x00000001) /*!< Thread mode can be entered from any level in Handler mode by controlled return value */
+#define SCB_CCR_USERSETMPEND ((uint32_t)0x00000002) /*!< Enables user code to write the Software Trigger Interrupt register to trigger (pend) a Main exception */
+#define SCB_CCR_UNALIGN_TRP ((uint32_t)0x00000008) /*!< Trap for unaligned access */
+#define SCB_CCR_DIV_0_TRP ((uint32_t)0x00000010) /*!< Trap on Divide by 0 */
+#define SCB_CCR_BFHFNMIGN ((uint32_t)0x00000100) /*!< Handlers running at priority -1 and -2 */
+#define SCB_CCR_STKALIGN ((uint32_t)0x00000200) /*!< On exception entry, the SP used prior to the exception is adjusted to be 8-byte aligned */
+
+/******************* Bit definition for SCB_SHPR register ********************/
+#define SCB_SHPR_PRI_N_Pos (0U)
+#define SCB_SHPR_PRI_N_Msk (0xFFU << SCB_SHPR_PRI_N_Pos) /*!< 0x000000FF */
+#define SCB_SHPR_PRI_N SCB_SHPR_PRI_N_Msk /*!< Priority of system handler 4,8, and 12. Mem Manage, reserved and Debug Monitor */
+#define SCB_SHPR_PRI_N1_Pos (8U)
+#define SCB_SHPR_PRI_N1_Msk (0xFFU << SCB_SHPR_PRI_N1_Pos) /*!< 0x0000FF00 */
+#define SCB_SHPR_PRI_N1 SCB_SHPR_PRI_N1_Msk /*!< Priority of system handler 5,9, and 13. Bus Fault, reserved and reserved */
+#define SCB_SHPR_PRI_N2_Pos (16U)
+#define SCB_SHPR_PRI_N2_Msk (0xFFU << SCB_SHPR_PRI_N2_Pos) /*!< 0x00FF0000 */
+#define SCB_SHPR_PRI_N2 SCB_SHPR_PRI_N2_Msk /*!< Priority of system handler 6,10, and 14. Usage Fault, reserved and PendSV */
+#define SCB_SHPR_PRI_N3_Pos (24U)
+#define SCB_SHPR_PRI_N3_Msk (0xFFU << SCB_SHPR_PRI_N3_Pos) /*!< 0xFF000000 */
+#define SCB_SHPR_PRI_N3 SCB_SHPR_PRI_N3_Msk /*!< Priority of system handler 7,11, and 15. Reserved, SVCall and SysTick */
+
+/****************** Bit definition for SCB_SHCSR register *******************/
+#define SCB_SHCSR_MEMFAULTACT ((uint32_t)0x00000001) /*!< MemManage is active */
+#define SCB_SHCSR_BUSFAULTACT ((uint32_t)0x00000002) /*!< BusFault is active */
+#define SCB_SHCSR_USGFAULTACT ((uint32_t)0x00000008) /*!< UsageFault is active */
+#define SCB_SHCSR_SVCALLACT ((uint32_t)0x00000080) /*!< SVCall is active */
+#define SCB_SHCSR_MONITORACT ((uint32_t)0x00000100) /*!< Monitor is active */
+#define SCB_SHCSR_PENDSVACT ((uint32_t)0x00000400) /*!< PendSV is active */
+#define SCB_SHCSR_SYSTICKACT ((uint32_t)0x00000800) /*!< SysTick is active */
+#define SCB_SHCSR_USGFAULTPENDED ((uint32_t)0x00001000) /*!< Usage Fault is pended */
+#define SCB_SHCSR_MEMFAULTPENDED ((uint32_t)0x00002000) /*!< MemManage is pended */
+#define SCB_SHCSR_BUSFAULTPENDED ((uint32_t)0x00004000) /*!< Bus Fault is pended */
+#define SCB_SHCSR_SVCALLPENDED ((uint32_t)0x00008000) /*!< SVCall is pended */
+#define SCB_SHCSR_MEMFAULTENA ((uint32_t)0x00010000) /*!< MemManage enable */
+#define SCB_SHCSR_BUSFAULTENA ((uint32_t)0x00020000) /*!< Bus Fault enable */
+#define SCB_SHCSR_USGFAULTENA ((uint32_t)0x00040000) /*!< UsageFault enable */
+
+/******************* Bit definition for SCB_CFSR register *******************/
+/*!< MFSR */
+#define SCB_CFSR_IACCVIOL_Pos (0U)
+#define SCB_CFSR_IACCVIOL_Msk (0x1U << SCB_CFSR_IACCVIOL_Pos) /*!< 0x00000001 */
+#define SCB_CFSR_IACCVIOL SCB_CFSR_IACCVIOL_Msk /*!< Instruction access violation */
+#define SCB_CFSR_DACCVIOL_Pos (1U)
+#define SCB_CFSR_DACCVIOL_Msk (0x1U << SCB_CFSR_DACCVIOL_Pos) /*!< 0x00000002 */
+#define SCB_CFSR_DACCVIOL SCB_CFSR_DACCVIOL_Msk /*!< Data access violation */
+#define SCB_CFSR_MUNSTKERR_Pos (3U)
+#define SCB_CFSR_MUNSTKERR_Msk (0x1U << SCB_CFSR_MUNSTKERR_Pos) /*!< 0x00000008 */
+#define SCB_CFSR_MUNSTKERR SCB_CFSR_MUNSTKERR_Msk /*!< Unstacking error */
+#define SCB_CFSR_MSTKERR_Pos (4U)
+#define SCB_CFSR_MSTKERR_Msk (0x1U << SCB_CFSR_MSTKERR_Pos) /*!< 0x00000010 */
+#define SCB_CFSR_MSTKERR SCB_CFSR_MSTKERR_Msk /*!< Stacking error */
+#define SCB_CFSR_MMARVALID_Pos (7U)
+#define SCB_CFSR_MMARVALID_Msk (0x1U << SCB_CFSR_MMARVALID_Pos) /*!< 0x00000080 */
+#define SCB_CFSR_MMARVALID SCB_CFSR_MMARVALID_Msk /*!< Memory Manage Address Register address valid flag */
+/*!< BFSR */
+#define SCB_CFSR_IBUSERR_Pos (8U)
+#define SCB_CFSR_IBUSERR_Msk (0x1U << SCB_CFSR_IBUSERR_Pos) /*!< 0x00000100 */
+#define SCB_CFSR_IBUSERR SCB_CFSR_IBUSERR_Msk /*!< Instruction bus error flag */
+#define SCB_CFSR_PRECISERR_Pos (9U)
+#define SCB_CFSR_PRECISERR_Msk (0x1U << SCB_CFSR_PRECISERR_Pos) /*!< 0x00000200 */
+#define SCB_CFSR_PRECISERR SCB_CFSR_PRECISERR_Msk /*!< Precise data bus error */
+#define SCB_CFSR_IMPRECISERR_Pos (10U)
+#define SCB_CFSR_IMPRECISERR_Msk (0x1U << SCB_CFSR_IMPRECISERR_Pos) /*!< 0x00000400 */
+#define SCB_CFSR_IMPRECISERR SCB_CFSR_IMPRECISERR_Msk /*!< Imprecise data bus error */
+#define SCB_CFSR_UNSTKERR_Pos (11U)
+#define SCB_CFSR_UNSTKERR_Msk (0x1U << SCB_CFSR_UNSTKERR_Pos) /*!< 0x00000800 */
+#define SCB_CFSR_UNSTKERR SCB_CFSR_UNSTKERR_Msk /*!< Unstacking error */
+#define SCB_CFSR_STKERR_Pos (12U)
+#define SCB_CFSR_STKERR_Msk (0x1U << SCB_CFSR_STKERR_Pos) /*!< 0x00001000 */
+#define SCB_CFSR_STKERR SCB_CFSR_STKERR_Msk /*!< Stacking error */
+#define SCB_CFSR_BFARVALID_Pos (15U)
+#define SCB_CFSR_BFARVALID_Msk (0x1U << SCB_CFSR_BFARVALID_Pos) /*!< 0x00008000 */
+#define SCB_CFSR_BFARVALID SCB_CFSR_BFARVALID_Msk /*!< Bus Fault Address Register address valid flag */
+/*!< UFSR */
+#define SCB_CFSR_UNDEFINSTR_Pos (16U)
+#define SCB_CFSR_UNDEFINSTR_Msk (0x1U << SCB_CFSR_UNDEFINSTR_Pos) /*!< 0x00010000 */
+#define SCB_CFSR_UNDEFINSTR SCB_CFSR_UNDEFINSTR_Msk /*!< The processor attempt to execute an undefined instruction */
+#define SCB_CFSR_INVSTATE_Pos (17U)
+#define SCB_CFSR_INVSTATE_Msk (0x1U << SCB_CFSR_INVSTATE_Pos) /*!< 0x00020000 */
+#define SCB_CFSR_INVSTATE SCB_CFSR_INVSTATE_Msk /*!< Invalid combination of EPSR and instruction */
+#define SCB_CFSR_INVPC_Pos (18U)
+#define SCB_CFSR_INVPC_Msk (0x1U << SCB_CFSR_INVPC_Pos) /*!< 0x00040000 */
+#define SCB_CFSR_INVPC SCB_CFSR_INVPC_Msk /*!< Attempt to load EXC_RETURN into pc illegally */
+#define SCB_CFSR_NOCP_Pos (19U)
+#define SCB_CFSR_NOCP_Msk (0x1U << SCB_CFSR_NOCP_Pos) /*!< 0x00080000 */
+#define SCB_CFSR_NOCP SCB_CFSR_NOCP_Msk /*!< Attempt to use a coprocessor instruction */
+#define SCB_CFSR_UNALIGNED_Pos (24U)
+#define SCB_CFSR_UNALIGNED_Msk (0x1U << SCB_CFSR_UNALIGNED_Pos) /*!< 0x01000000 */
+#define SCB_CFSR_UNALIGNED SCB_CFSR_UNALIGNED_Msk /*!< Fault occurs when there is an attempt to make an unaligned memory access */
+#define SCB_CFSR_DIVBYZERO_Pos (25U)
+#define SCB_CFSR_DIVBYZERO_Msk (0x1U << SCB_CFSR_DIVBYZERO_Pos) /*!< 0x02000000 */
+#define SCB_CFSR_DIVBYZERO SCB_CFSR_DIVBYZERO_Msk /*!< Fault occurs when SDIV or DIV instruction is used with a divisor of 0 */
+
+/******************* Bit definition for SCB_HFSR register *******************/
+#define SCB_HFSR_VECTTBL ((uint32_t)0x00000002) /*!< Fault occurs because of vector table read on exception processing */
+#define SCB_HFSR_FORCED ((uint32_t)0x40000000) /*!< Hard Fault activated when a configurable Fault was received and cannot activate */
+#define SCB_HFSR_DEBUGEVT ((uint32_t)0x80000000) /*!< Fault related to debug */
+
+/******************* Bit definition for SCB_DFSR register *******************/
+#define SCB_DFSR_HALTED ((uint32_t)0x00000001) /*!< Halt request flag */
+#define SCB_DFSR_BKPT ((uint32_t)0x00000002) /*!< BKPT flag */
+#define SCB_DFSR_DWTTRAP ((uint32_t)0x00000004) /*!< Data Watchpoint and Trace (DWT) flag */
+#define SCB_DFSR_VCATCH ((uint32_t)0x00000008) /*!< Vector catch flag */
+#define SCB_DFSR_EXTERNAL ((uint32_t)0x00000010) /*!< External debug request flag */
+
+/******************* Bit definition for SCB_MMFAR register ******************/
+#define SCB_MMFAR_ADDRESS_Pos (0U)
+#define SCB_MMFAR_ADDRESS_Msk (0xFFFFFFFFU << SCB_MMFAR_ADDRESS_Pos) /*!< 0xFFFFFFFF */
+#define SCB_MMFAR_ADDRESS SCB_MMFAR_ADDRESS_Msk /*!< Mem Manage fault address field */
+
+/******************* Bit definition for SCB_BFAR register *******************/
+#define SCB_BFAR_ADDRESS_Pos (0U)
+#define SCB_BFAR_ADDRESS_Msk (0xFFFFFFFFU << SCB_BFAR_ADDRESS_Pos) /*!< 0xFFFFFFFF */
+#define SCB_BFAR_ADDRESS SCB_BFAR_ADDRESS_Msk /*!< Bus fault address field */
+
+/******************* Bit definition for SCB_afsr register *******************/
+#define SCB_AFSR_IMPDEF_Pos (0U)
+#define SCB_AFSR_IMPDEF_Msk (0xFFFFFFFFU << SCB_AFSR_IMPDEF_Pos) /*!< 0xFFFFFFFF */
+#define SCB_AFSR_IMPDEF SCB_AFSR_IMPDEF_Msk /*!< Implementation defined */
+
+/******************************************************************************/
+/* */
+/* External Interrupt/Event Controller */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for EXTI_IMR register *******************/
+#define EXTI_IMR_MR0_Pos (0U)
+#define EXTI_IMR_MR0_Msk (0x1U << EXTI_IMR_MR0_Pos) /*!< 0x00000001 */
+#define EXTI_IMR_MR0 EXTI_IMR_MR0_Msk /*!< Interrupt Mask on line 0 */
+#define EXTI_IMR_MR1_Pos (1U)
+#define EXTI_IMR_MR1_Msk (0x1U << EXTI_IMR_MR1_Pos) /*!< 0x00000002 */
+#define EXTI_IMR_MR1 EXTI_IMR_MR1_Msk /*!< Interrupt Mask on line 1 */
+#define EXTI_IMR_MR2_Pos (2U)
+#define EXTI_IMR_MR2_Msk (0x1U << EXTI_IMR_MR2_Pos) /*!< 0x00000004 */
+#define EXTI_IMR_MR2 EXTI_IMR_MR2_Msk /*!< Interrupt Mask on line 2 */
+#define EXTI_IMR_MR3_Pos (3U)
+#define EXTI_IMR_MR3_Msk (0x1U << EXTI_IMR_MR3_Pos) /*!< 0x00000008 */
+#define EXTI_IMR_MR3 EXTI_IMR_MR3_Msk /*!< Interrupt Mask on line 3 */
+#define EXTI_IMR_MR4_Pos (4U)
+#define EXTI_IMR_MR4_Msk (0x1U << EXTI_IMR_MR4_Pos) /*!< 0x00000010 */
+#define EXTI_IMR_MR4 EXTI_IMR_MR4_Msk /*!< Interrupt Mask on line 4 */
+#define EXTI_IMR_MR5_Pos (5U)
+#define EXTI_IMR_MR5_Msk (0x1U << EXTI_IMR_MR5_Pos) /*!< 0x00000020 */
+#define EXTI_IMR_MR5 EXTI_IMR_MR5_Msk /*!< Interrupt Mask on line 5 */
+#define EXTI_IMR_MR6_Pos (6U)
+#define EXTI_IMR_MR6_Msk (0x1U << EXTI_IMR_MR6_Pos) /*!< 0x00000040 */
+#define EXTI_IMR_MR6 EXTI_IMR_MR6_Msk /*!< Interrupt Mask on line 6 */
+#define EXTI_IMR_MR7_Pos (7U)
+#define EXTI_IMR_MR7_Msk (0x1U << EXTI_IMR_MR7_Pos) /*!< 0x00000080 */
+#define EXTI_IMR_MR7 EXTI_IMR_MR7_Msk /*!< Interrupt Mask on line 7 */
+#define EXTI_IMR_MR8_Pos (8U)
+#define EXTI_IMR_MR8_Msk (0x1U << EXTI_IMR_MR8_Pos) /*!< 0x00000100 */
+#define EXTI_IMR_MR8 EXTI_IMR_MR8_Msk /*!< Interrupt Mask on line 8 */
+#define EXTI_IMR_MR9_Pos (9U)
+#define EXTI_IMR_MR9_Msk (0x1U << EXTI_IMR_MR9_Pos) /*!< 0x00000200 */
+#define EXTI_IMR_MR9 EXTI_IMR_MR9_Msk /*!< Interrupt Mask on line 9 */
+#define EXTI_IMR_MR10_Pos (10U)
+#define EXTI_IMR_MR10_Msk (0x1U << EXTI_IMR_MR10_Pos) /*!< 0x00000400 */
+#define EXTI_IMR_MR10 EXTI_IMR_MR10_Msk /*!< Interrupt Mask on line 10 */
+#define EXTI_IMR_MR11_Pos (11U)
+#define EXTI_IMR_MR11_Msk (0x1U << EXTI_IMR_MR11_Pos) /*!< 0x00000800 */
+#define EXTI_IMR_MR11 EXTI_IMR_MR11_Msk /*!< Interrupt Mask on line 11 */
+#define EXTI_IMR_MR12_Pos (12U)
+#define EXTI_IMR_MR12_Msk (0x1U << EXTI_IMR_MR12_Pos) /*!< 0x00001000 */
+#define EXTI_IMR_MR12 EXTI_IMR_MR12_Msk /*!< Interrupt Mask on line 12 */
+#define EXTI_IMR_MR13_Pos (13U)
+#define EXTI_IMR_MR13_Msk (0x1U << EXTI_IMR_MR13_Pos) /*!< 0x00002000 */
+#define EXTI_IMR_MR13 EXTI_IMR_MR13_Msk /*!< Interrupt Mask on line 13 */
+#define EXTI_IMR_MR14_Pos (14U)
+#define EXTI_IMR_MR14_Msk (0x1U << EXTI_IMR_MR14_Pos) /*!< 0x00004000 */
+#define EXTI_IMR_MR14 EXTI_IMR_MR14_Msk /*!< Interrupt Mask on line 14 */
+#define EXTI_IMR_MR15_Pos (15U)
+#define EXTI_IMR_MR15_Msk (0x1U << EXTI_IMR_MR15_Pos) /*!< 0x00008000 */
+#define EXTI_IMR_MR15 EXTI_IMR_MR15_Msk /*!< Interrupt Mask on line 15 */
+#define EXTI_IMR_MR16_Pos (16U)
+#define EXTI_IMR_MR16_Msk (0x1U << EXTI_IMR_MR16_Pos) /*!< 0x00010000 */
+#define EXTI_IMR_MR16 EXTI_IMR_MR16_Msk /*!< Interrupt Mask on line 16 */
+#define EXTI_IMR_MR17_Pos (17U)
+#define EXTI_IMR_MR17_Msk (0x1U << EXTI_IMR_MR17_Pos) /*!< 0x00020000 */
+#define EXTI_IMR_MR17 EXTI_IMR_MR17_Msk /*!< Interrupt Mask on line 17 */
+#define EXTI_IMR_MR18_Pos (18U)
+#define EXTI_IMR_MR18_Msk (0x1U << EXTI_IMR_MR18_Pos) /*!< 0x00040000 */
+#define EXTI_IMR_MR18 EXTI_IMR_MR18_Msk /*!< Interrupt Mask on line 18 */
+#define EXTI_IMR_MR19_Pos (19U)
+#define EXTI_IMR_MR19_Msk (0x1U << EXTI_IMR_MR19_Pos) /*!< 0x00080000 */
+#define EXTI_IMR_MR19 EXTI_IMR_MR19_Msk /*!< Interrupt Mask on line 19 */
+
+/* References Defines */
+#define EXTI_IMR_IM0 EXTI_IMR_MR0
+#define EXTI_IMR_IM1 EXTI_IMR_MR1
+#define EXTI_IMR_IM2 EXTI_IMR_MR2
+#define EXTI_IMR_IM3 EXTI_IMR_MR3
+#define EXTI_IMR_IM4 EXTI_IMR_MR4
+#define EXTI_IMR_IM5 EXTI_IMR_MR5
+#define EXTI_IMR_IM6 EXTI_IMR_MR6
+#define EXTI_IMR_IM7 EXTI_IMR_MR7
+#define EXTI_IMR_IM8 EXTI_IMR_MR8
+#define EXTI_IMR_IM9 EXTI_IMR_MR9
+#define EXTI_IMR_IM10 EXTI_IMR_MR10
+#define EXTI_IMR_IM11 EXTI_IMR_MR11
+#define EXTI_IMR_IM12 EXTI_IMR_MR12
+#define EXTI_IMR_IM13 EXTI_IMR_MR13
+#define EXTI_IMR_IM14 EXTI_IMR_MR14
+#define EXTI_IMR_IM15 EXTI_IMR_MR15
+#define EXTI_IMR_IM16 EXTI_IMR_MR16
+#define EXTI_IMR_IM17 EXTI_IMR_MR17
+#define EXTI_IMR_IM18 EXTI_IMR_MR18
+#define EXTI_IMR_IM19 EXTI_IMR_MR19
+
+/******************* Bit definition for EXTI_EMR register *******************/
+#define EXTI_EMR_MR0_Pos (0U)
+#define EXTI_EMR_MR0_Msk (0x1U << EXTI_EMR_MR0_Pos) /*!< 0x00000001 */
+#define EXTI_EMR_MR0 EXTI_EMR_MR0_Msk /*!< Event Mask on line 0 */
+#define EXTI_EMR_MR1_Pos (1U)
+#define EXTI_EMR_MR1_Msk (0x1U << EXTI_EMR_MR1_Pos) /*!< 0x00000002 */
+#define EXTI_EMR_MR1 EXTI_EMR_MR1_Msk /*!< Event Mask on line 1 */
+#define EXTI_EMR_MR2_Pos (2U)
+#define EXTI_EMR_MR2_Msk (0x1U << EXTI_EMR_MR2_Pos) /*!< 0x00000004 */
+#define EXTI_EMR_MR2 EXTI_EMR_MR2_Msk /*!< Event Mask on line 2 */
+#define EXTI_EMR_MR3_Pos (3U)
+#define EXTI_EMR_MR3_Msk (0x1U << EXTI_EMR_MR3_Pos) /*!< 0x00000008 */
+#define EXTI_EMR_MR3 EXTI_EMR_MR3_Msk /*!< Event Mask on line 3 */
+#define EXTI_EMR_MR4_Pos (4U)
+#define EXTI_EMR_MR4_Msk (0x1U << EXTI_EMR_MR4_Pos) /*!< 0x00000010 */
+#define EXTI_EMR_MR4 EXTI_EMR_MR4_Msk /*!< Event Mask on line 4 */
+#define EXTI_EMR_MR5_Pos (5U)
+#define EXTI_EMR_MR5_Msk (0x1U << EXTI_EMR_MR5_Pos) /*!< 0x00000020 */
+#define EXTI_EMR_MR5 EXTI_EMR_MR5_Msk /*!< Event Mask on line 5 */
+#define EXTI_EMR_MR6_Pos (6U)
+#define EXTI_EMR_MR6_Msk (0x1U << EXTI_EMR_MR6_Pos) /*!< 0x00000040 */
+#define EXTI_EMR_MR6 EXTI_EMR_MR6_Msk /*!< Event Mask on line 6 */
+#define EXTI_EMR_MR7_Pos (7U)
+#define EXTI_EMR_MR7_Msk (0x1U << EXTI_EMR_MR7_Pos) /*!< 0x00000080 */
+#define EXTI_EMR_MR7 EXTI_EMR_MR7_Msk /*!< Event Mask on line 7 */
+#define EXTI_EMR_MR8_Pos (8U)
+#define EXTI_EMR_MR8_Msk (0x1U << EXTI_EMR_MR8_Pos) /*!< 0x00000100 */
+#define EXTI_EMR_MR8 EXTI_EMR_MR8_Msk /*!< Event Mask on line 8 */
+#define EXTI_EMR_MR9_Pos (9U)
+#define EXTI_EMR_MR9_Msk (0x1U << EXTI_EMR_MR9_Pos) /*!< 0x00000200 */
+#define EXTI_EMR_MR9 EXTI_EMR_MR9_Msk /*!< Event Mask on line 9 */
+#define EXTI_EMR_MR10_Pos (10U)
+#define EXTI_EMR_MR10_Msk (0x1U << EXTI_EMR_MR10_Pos) /*!< 0x00000400 */
+#define EXTI_EMR_MR10 EXTI_EMR_MR10_Msk /*!< Event Mask on line 10 */
+#define EXTI_EMR_MR11_Pos (11U)
+#define EXTI_EMR_MR11_Msk (0x1U << EXTI_EMR_MR11_Pos) /*!< 0x00000800 */
+#define EXTI_EMR_MR11 EXTI_EMR_MR11_Msk /*!< Event Mask on line 11 */
+#define EXTI_EMR_MR12_Pos (12U)
+#define EXTI_EMR_MR12_Msk (0x1U << EXTI_EMR_MR12_Pos) /*!< 0x00001000 */
+#define EXTI_EMR_MR12 EXTI_EMR_MR12_Msk /*!< Event Mask on line 12 */
+#define EXTI_EMR_MR13_Pos (13U)
+#define EXTI_EMR_MR13_Msk (0x1U << EXTI_EMR_MR13_Pos) /*!< 0x00002000 */
+#define EXTI_EMR_MR13 EXTI_EMR_MR13_Msk /*!< Event Mask on line 13 */
+#define EXTI_EMR_MR14_Pos (14U)
+#define EXTI_EMR_MR14_Msk (0x1U << EXTI_EMR_MR14_Pos) /*!< 0x00004000 */
+#define EXTI_EMR_MR14 EXTI_EMR_MR14_Msk /*!< Event Mask on line 14 */
+#define EXTI_EMR_MR15_Pos (15U)
+#define EXTI_EMR_MR15_Msk (0x1U << EXTI_EMR_MR15_Pos) /*!< 0x00008000 */
+#define EXTI_EMR_MR15 EXTI_EMR_MR15_Msk /*!< Event Mask on line 15 */
+#define EXTI_EMR_MR16_Pos (16U)
+#define EXTI_EMR_MR16_Msk (0x1U << EXTI_EMR_MR16_Pos) /*!< 0x00010000 */
+#define EXTI_EMR_MR16 EXTI_EMR_MR16_Msk /*!< Event Mask on line 16 */
+#define EXTI_EMR_MR17_Pos (17U)
+#define EXTI_EMR_MR17_Msk (0x1U << EXTI_EMR_MR17_Pos) /*!< 0x00020000 */
+#define EXTI_EMR_MR17 EXTI_EMR_MR17_Msk /*!< Event Mask on line 17 */
+#define EXTI_EMR_MR18_Pos (18U)
+#define EXTI_EMR_MR18_Msk (0x1U << EXTI_EMR_MR18_Pos) /*!< 0x00040000 */
+#define EXTI_EMR_MR18 EXTI_EMR_MR18_Msk /*!< Event Mask on line 18 */
+#define EXTI_EMR_MR19_Pos (19U)
+#define EXTI_EMR_MR19_Msk (0x1U << EXTI_EMR_MR19_Pos) /*!< 0x00080000 */
+#define EXTI_EMR_MR19 EXTI_EMR_MR19_Msk /*!< Event Mask on line 19 */
+
+/* References Defines */
+#define EXTI_EMR_EM0 EXTI_EMR_MR0
+#define EXTI_EMR_EM1 EXTI_EMR_MR1
+#define EXTI_EMR_EM2 EXTI_EMR_MR2
+#define EXTI_EMR_EM3 EXTI_EMR_MR3
+#define EXTI_EMR_EM4 EXTI_EMR_MR4
+#define EXTI_EMR_EM5 EXTI_EMR_MR5
+#define EXTI_EMR_EM6 EXTI_EMR_MR6
+#define EXTI_EMR_EM7 EXTI_EMR_MR7
+#define EXTI_EMR_EM8 EXTI_EMR_MR8
+#define EXTI_EMR_EM9 EXTI_EMR_MR9
+#define EXTI_EMR_EM10 EXTI_EMR_MR10
+#define EXTI_EMR_EM11 EXTI_EMR_MR11
+#define EXTI_EMR_EM12 EXTI_EMR_MR12
+#define EXTI_EMR_EM13 EXTI_EMR_MR13
+#define EXTI_EMR_EM14 EXTI_EMR_MR14
+#define EXTI_EMR_EM15 EXTI_EMR_MR15
+#define EXTI_EMR_EM16 EXTI_EMR_MR16
+#define EXTI_EMR_EM17 EXTI_EMR_MR17
+#define EXTI_EMR_EM18 EXTI_EMR_MR18
+#define EXTI_EMR_EM19 EXTI_EMR_MR19
+
+/****************** Bit definition for EXTI_RTSR register *******************/
+#define EXTI_RTSR_TR0_Pos (0U)
+#define EXTI_RTSR_TR0_Msk (0x1U << EXTI_RTSR_TR0_Pos) /*!< 0x00000001 */
+#define EXTI_RTSR_TR0 EXTI_RTSR_TR0_Msk /*!< Rising trigger event configuration bit of line 0 */
+#define EXTI_RTSR_TR1_Pos (1U)
+#define EXTI_RTSR_TR1_Msk (0x1U << EXTI_RTSR_TR1_Pos) /*!< 0x00000002 */
+#define EXTI_RTSR_TR1 EXTI_RTSR_TR1_Msk /*!< Rising trigger event configuration bit of line 1 */
+#define EXTI_RTSR_TR2_Pos (2U)
+#define EXTI_RTSR_TR2_Msk (0x1U << EXTI_RTSR_TR2_Pos) /*!< 0x00000004 */
+#define EXTI_RTSR_TR2 EXTI_RTSR_TR2_Msk /*!< Rising trigger event configuration bit of line 2 */
+#define EXTI_RTSR_TR3_Pos (3U)
+#define EXTI_RTSR_TR3_Msk (0x1U << EXTI_RTSR_TR3_Pos) /*!< 0x00000008 */
+#define EXTI_RTSR_TR3 EXTI_RTSR_TR3_Msk /*!< Rising trigger event configuration bit of line 3 */
+#define EXTI_RTSR_TR4_Pos (4U)
+#define EXTI_RTSR_TR4_Msk (0x1U << EXTI_RTSR_TR4_Pos) /*!< 0x00000010 */
+#define EXTI_RTSR_TR4 EXTI_RTSR_TR4_Msk /*!< Rising trigger event configuration bit of line 4 */
+#define EXTI_RTSR_TR5_Pos (5U)
+#define EXTI_RTSR_TR5_Msk (0x1U << EXTI_RTSR_TR5_Pos) /*!< 0x00000020 */
+#define EXTI_RTSR_TR5 EXTI_RTSR_TR5_Msk /*!< Rising trigger event configuration bit of line 5 */
+#define EXTI_RTSR_TR6_Pos (6U)
+#define EXTI_RTSR_TR6_Msk (0x1U << EXTI_RTSR_TR6_Pos) /*!< 0x00000040 */
+#define EXTI_RTSR_TR6 EXTI_RTSR_TR6_Msk /*!< Rising trigger event configuration bit of line 6 */
+#define EXTI_RTSR_TR7_Pos (7U)
+#define EXTI_RTSR_TR7_Msk (0x1U << EXTI_RTSR_TR7_Pos) /*!< 0x00000080 */
+#define EXTI_RTSR_TR7 EXTI_RTSR_TR7_Msk /*!< Rising trigger event configuration bit of line 7 */
+#define EXTI_RTSR_TR8_Pos (8U)
+#define EXTI_RTSR_TR8_Msk (0x1U << EXTI_RTSR_TR8_Pos) /*!< 0x00000100 */
+#define EXTI_RTSR_TR8 EXTI_RTSR_TR8_Msk /*!< Rising trigger event configuration bit of line 8 */
+#define EXTI_RTSR_TR9_Pos (9U)
+#define EXTI_RTSR_TR9_Msk (0x1U << EXTI_RTSR_TR9_Pos) /*!< 0x00000200 */
+#define EXTI_RTSR_TR9 EXTI_RTSR_TR9_Msk /*!< Rising trigger event configuration bit of line 9 */
+#define EXTI_RTSR_TR10_Pos (10U)
+#define EXTI_RTSR_TR10_Msk (0x1U << EXTI_RTSR_TR10_Pos) /*!< 0x00000400 */
+#define EXTI_RTSR_TR10 EXTI_RTSR_TR10_Msk /*!< Rising trigger event configuration bit of line 10 */
+#define EXTI_RTSR_TR11_Pos (11U)
+#define EXTI_RTSR_TR11_Msk (0x1U << EXTI_RTSR_TR11_Pos) /*!< 0x00000800 */
+#define EXTI_RTSR_TR11 EXTI_RTSR_TR11_Msk /*!< Rising trigger event configuration bit of line 11 */
+#define EXTI_RTSR_TR12_Pos (12U)
+#define EXTI_RTSR_TR12_Msk (0x1U << EXTI_RTSR_TR12_Pos) /*!< 0x00001000 */
+#define EXTI_RTSR_TR12 EXTI_RTSR_TR12_Msk /*!< Rising trigger event configuration bit of line 12 */
+#define EXTI_RTSR_TR13_Pos (13U)
+#define EXTI_RTSR_TR13_Msk (0x1U << EXTI_RTSR_TR13_Pos) /*!< 0x00002000 */
+#define EXTI_RTSR_TR13 EXTI_RTSR_TR13_Msk /*!< Rising trigger event configuration bit of line 13 */
+#define EXTI_RTSR_TR14_Pos (14U)
+#define EXTI_RTSR_TR14_Msk (0x1U << EXTI_RTSR_TR14_Pos) /*!< 0x00004000 */
+#define EXTI_RTSR_TR14 EXTI_RTSR_TR14_Msk /*!< Rising trigger event configuration bit of line 14 */
+#define EXTI_RTSR_TR15_Pos (15U)
+#define EXTI_RTSR_TR15_Msk (0x1U << EXTI_RTSR_TR15_Pos) /*!< 0x00008000 */
+#define EXTI_RTSR_TR15 EXTI_RTSR_TR15_Msk /*!< Rising trigger event configuration bit of line 15 */
+#define EXTI_RTSR_TR16_Pos (16U)
+#define EXTI_RTSR_TR16_Msk (0x1U << EXTI_RTSR_TR16_Pos) /*!< 0x00010000 */
+#define EXTI_RTSR_TR16 EXTI_RTSR_TR16_Msk /*!< Rising trigger event configuration bit of line 16 */
+#define EXTI_RTSR_TR17_Pos (17U)
+#define EXTI_RTSR_TR17_Msk (0x1U << EXTI_RTSR_TR17_Pos) /*!< 0x00020000 */
+#define EXTI_RTSR_TR17 EXTI_RTSR_TR17_Msk /*!< Rising trigger event configuration bit of line 17 */
+#define EXTI_RTSR_TR18_Pos (18U)
+#define EXTI_RTSR_TR18_Msk (0x1U << EXTI_RTSR_TR18_Pos) /*!< 0x00040000 */
+#define EXTI_RTSR_TR18 EXTI_RTSR_TR18_Msk /*!< Rising trigger event configuration bit of line 18 */
+#define EXTI_RTSR_TR19_Pos (19U)
+#define EXTI_RTSR_TR19_Msk (0x1U << EXTI_RTSR_TR19_Pos) /*!< 0x00080000 */
+#define EXTI_RTSR_TR19 EXTI_RTSR_TR19_Msk /*!< Rising trigger event configuration bit of line 19 */
+
+/* References Defines */
+#define EXTI_RTSR_RT0 EXTI_RTSR_TR0
+#define EXTI_RTSR_RT1 EXTI_RTSR_TR1
+#define EXTI_RTSR_RT2 EXTI_RTSR_TR2
+#define EXTI_RTSR_RT3 EXTI_RTSR_TR3
+#define EXTI_RTSR_RT4 EXTI_RTSR_TR4
+#define EXTI_RTSR_RT5 EXTI_RTSR_TR5
+#define EXTI_RTSR_RT6 EXTI_RTSR_TR6
+#define EXTI_RTSR_RT7 EXTI_RTSR_TR7
+#define EXTI_RTSR_RT8 EXTI_RTSR_TR8
+#define EXTI_RTSR_RT9 EXTI_RTSR_TR9
+#define EXTI_RTSR_RT10 EXTI_RTSR_TR10
+#define EXTI_RTSR_RT11 EXTI_RTSR_TR11
+#define EXTI_RTSR_RT12 EXTI_RTSR_TR12
+#define EXTI_RTSR_RT13 EXTI_RTSR_TR13
+#define EXTI_RTSR_RT14 EXTI_RTSR_TR14
+#define EXTI_RTSR_RT15 EXTI_RTSR_TR15
+#define EXTI_RTSR_RT16 EXTI_RTSR_TR16
+#define EXTI_RTSR_RT17 EXTI_RTSR_TR17
+#define EXTI_RTSR_RT18 EXTI_RTSR_TR18
+#define EXTI_RTSR_RT19 EXTI_RTSR_TR19
+
+/****************** Bit definition for EXTI_FTSR register *******************/
+#define EXTI_FTSR_TR0_Pos (0U)
+#define EXTI_FTSR_TR0_Msk (0x1U << EXTI_FTSR_TR0_Pos) /*!< 0x00000001 */
+#define EXTI_FTSR_TR0 EXTI_FTSR_TR0_Msk /*!< Falling trigger event configuration bit of line 0 */
+#define EXTI_FTSR_TR1_Pos (1U)
+#define EXTI_FTSR_TR1_Msk (0x1U << EXTI_FTSR_TR1_Pos) /*!< 0x00000002 */
+#define EXTI_FTSR_TR1 EXTI_FTSR_TR1_Msk /*!< Falling trigger event configuration bit of line 1 */
+#define EXTI_FTSR_TR2_Pos (2U)
+#define EXTI_FTSR_TR2_Msk (0x1U << EXTI_FTSR_TR2_Pos) /*!< 0x00000004 */
+#define EXTI_FTSR_TR2 EXTI_FTSR_TR2_Msk /*!< Falling trigger event configuration bit of line 2 */
+#define EXTI_FTSR_TR3_Pos (3U)
+#define EXTI_FTSR_TR3_Msk (0x1U << EXTI_FTSR_TR3_Pos) /*!< 0x00000008 */
+#define EXTI_FTSR_TR3 EXTI_FTSR_TR3_Msk /*!< Falling trigger event configuration bit of line 3 */
+#define EXTI_FTSR_TR4_Pos (4U)
+#define EXTI_FTSR_TR4_Msk (0x1U << EXTI_FTSR_TR4_Pos) /*!< 0x00000010 */
+#define EXTI_FTSR_TR4 EXTI_FTSR_TR4_Msk /*!< Falling trigger event configuration bit of line 4 */
+#define EXTI_FTSR_TR5_Pos (5U)
+#define EXTI_FTSR_TR5_Msk (0x1U << EXTI_FTSR_TR5_Pos) /*!< 0x00000020 */
+#define EXTI_FTSR_TR5 EXTI_FTSR_TR5_Msk /*!< Falling trigger event configuration bit of line 5 */
+#define EXTI_FTSR_TR6_Pos (6U)
+#define EXTI_FTSR_TR6_Msk (0x1U << EXTI_FTSR_TR6_Pos) /*!< 0x00000040 */
+#define EXTI_FTSR_TR6 EXTI_FTSR_TR6_Msk /*!< Falling trigger event configuration bit of line 6 */
+#define EXTI_FTSR_TR7_Pos (7U)
+#define EXTI_FTSR_TR7_Msk (0x1U << EXTI_FTSR_TR7_Pos) /*!< 0x00000080 */
+#define EXTI_FTSR_TR7 EXTI_FTSR_TR7_Msk /*!< Falling trigger event configuration bit of line 7 */
+#define EXTI_FTSR_TR8_Pos (8U)
+#define EXTI_FTSR_TR8_Msk (0x1U << EXTI_FTSR_TR8_Pos) /*!< 0x00000100 */
+#define EXTI_FTSR_TR8 EXTI_FTSR_TR8_Msk /*!< Falling trigger event configuration bit of line 8 */
+#define EXTI_FTSR_TR9_Pos (9U)
+#define EXTI_FTSR_TR9_Msk (0x1U << EXTI_FTSR_TR9_Pos) /*!< 0x00000200 */
+#define EXTI_FTSR_TR9 EXTI_FTSR_TR9_Msk /*!< Falling trigger event configuration bit of line 9 */
+#define EXTI_FTSR_TR10_Pos (10U)
+#define EXTI_FTSR_TR10_Msk (0x1U << EXTI_FTSR_TR10_Pos) /*!< 0x00000400 */
+#define EXTI_FTSR_TR10 EXTI_FTSR_TR10_Msk /*!< Falling trigger event configuration bit of line 10 */
+#define EXTI_FTSR_TR11_Pos (11U)
+#define EXTI_FTSR_TR11_Msk (0x1U << EXTI_FTSR_TR11_Pos) /*!< 0x00000800 */
+#define EXTI_FTSR_TR11 EXTI_FTSR_TR11_Msk /*!< Falling trigger event configuration bit of line 11 */
+#define EXTI_FTSR_TR12_Pos (12U)
+#define EXTI_FTSR_TR12_Msk (0x1U << EXTI_FTSR_TR12_Pos) /*!< 0x00001000 */
+#define EXTI_FTSR_TR12 EXTI_FTSR_TR12_Msk /*!< Falling trigger event configuration bit of line 12 */
+#define EXTI_FTSR_TR13_Pos (13U)
+#define EXTI_FTSR_TR13_Msk (0x1U << EXTI_FTSR_TR13_Pos) /*!< 0x00002000 */
+#define EXTI_FTSR_TR13 EXTI_FTSR_TR13_Msk /*!< Falling trigger event configuration bit of line 13 */
+#define EXTI_FTSR_TR14_Pos (14U)
+#define EXTI_FTSR_TR14_Msk (0x1U << EXTI_FTSR_TR14_Pos) /*!< 0x00004000 */
+#define EXTI_FTSR_TR14 EXTI_FTSR_TR14_Msk /*!< Falling trigger event configuration bit of line 14 */
+#define EXTI_FTSR_TR15_Pos (15U)
+#define EXTI_FTSR_TR15_Msk (0x1U << EXTI_FTSR_TR15_Pos) /*!< 0x00008000 */
+#define EXTI_FTSR_TR15 EXTI_FTSR_TR15_Msk /*!< Falling trigger event configuration bit of line 15 */
+#define EXTI_FTSR_TR16_Pos (16U)
+#define EXTI_FTSR_TR16_Msk (0x1U << EXTI_FTSR_TR16_Pos) /*!< 0x00010000 */
+#define EXTI_FTSR_TR16 EXTI_FTSR_TR16_Msk /*!< Falling trigger event configuration bit of line 16 */
+#define EXTI_FTSR_TR17_Pos (17U)
+#define EXTI_FTSR_TR17_Msk (0x1U << EXTI_FTSR_TR17_Pos) /*!< 0x00020000 */
+#define EXTI_FTSR_TR17 EXTI_FTSR_TR17_Msk /*!< Falling trigger event configuration bit of line 17 */
+#define EXTI_FTSR_TR18_Pos (18U)
+#define EXTI_FTSR_TR18_Msk (0x1U << EXTI_FTSR_TR18_Pos) /*!< 0x00040000 */
+#define EXTI_FTSR_TR18 EXTI_FTSR_TR18_Msk /*!< Falling trigger event configuration bit of line 18 */
+#define EXTI_FTSR_TR19_Pos (19U)
+#define EXTI_FTSR_TR19_Msk (0x1U << EXTI_FTSR_TR19_Pos) /*!< 0x00080000 */
+#define EXTI_FTSR_TR19 EXTI_FTSR_TR19_Msk /*!< Falling trigger event configuration bit of line 19 */
+
+/* References Defines */
+#define EXTI_FTSR_FT0 EXTI_FTSR_TR0
+#define EXTI_FTSR_FT1 EXTI_FTSR_TR1
+#define EXTI_FTSR_FT2 EXTI_FTSR_TR2
+#define EXTI_FTSR_FT3 EXTI_FTSR_TR3
+#define EXTI_FTSR_FT4 EXTI_FTSR_TR4
+#define EXTI_FTSR_FT5 EXTI_FTSR_TR5
+#define EXTI_FTSR_FT6 EXTI_FTSR_TR6
+#define EXTI_FTSR_FT7 EXTI_FTSR_TR7
+#define EXTI_FTSR_FT8 EXTI_FTSR_TR8
+#define EXTI_FTSR_FT9 EXTI_FTSR_TR9
+#define EXTI_FTSR_FT10 EXTI_FTSR_TR10
+#define EXTI_FTSR_FT11 EXTI_FTSR_TR11
+#define EXTI_FTSR_FT12 EXTI_FTSR_TR12
+#define EXTI_FTSR_FT13 EXTI_FTSR_TR13
+#define EXTI_FTSR_FT14 EXTI_FTSR_TR14
+#define EXTI_FTSR_FT15 EXTI_FTSR_TR15
+#define EXTI_FTSR_FT16 EXTI_FTSR_TR16
+#define EXTI_FTSR_FT17 EXTI_FTSR_TR17
+#define EXTI_FTSR_FT18 EXTI_FTSR_TR18
+#define EXTI_FTSR_FT19 EXTI_FTSR_TR19
+
+/****************** Bit definition for EXTI_SWIER register ******************/
+#define EXTI_SWIER_SWIER0_Pos (0U)
+#define EXTI_SWIER_SWIER0_Msk (0x1U << EXTI_SWIER_SWIER0_Pos) /*!< 0x00000001 */
+#define EXTI_SWIER_SWIER0 EXTI_SWIER_SWIER0_Msk /*!< Software Interrupt on line 0 */
+#define EXTI_SWIER_SWIER1_Pos (1U)
+#define EXTI_SWIER_SWIER1_Msk (0x1U << EXTI_SWIER_SWIER1_Pos) /*!< 0x00000002 */
+#define EXTI_SWIER_SWIER1 EXTI_SWIER_SWIER1_Msk /*!< Software Interrupt on line 1 */
+#define EXTI_SWIER_SWIER2_Pos (2U)
+#define EXTI_SWIER_SWIER2_Msk (0x1U << EXTI_SWIER_SWIER2_Pos) /*!< 0x00000004 */
+#define EXTI_SWIER_SWIER2 EXTI_SWIER_SWIER2_Msk /*!< Software Interrupt on line 2 */
+#define EXTI_SWIER_SWIER3_Pos (3U)
+#define EXTI_SWIER_SWIER3_Msk (0x1U << EXTI_SWIER_SWIER3_Pos) /*!< 0x00000008 */
+#define EXTI_SWIER_SWIER3 EXTI_SWIER_SWIER3_Msk /*!< Software Interrupt on line 3 */
+#define EXTI_SWIER_SWIER4_Pos (4U)
+#define EXTI_SWIER_SWIER4_Msk (0x1U << EXTI_SWIER_SWIER4_Pos) /*!< 0x00000010 */
+#define EXTI_SWIER_SWIER4 EXTI_SWIER_SWIER4_Msk /*!< Software Interrupt on line 4 */
+#define EXTI_SWIER_SWIER5_Pos (5U)
+#define EXTI_SWIER_SWIER5_Msk (0x1U << EXTI_SWIER_SWIER5_Pos) /*!< 0x00000020 */
+#define EXTI_SWIER_SWIER5 EXTI_SWIER_SWIER5_Msk /*!< Software Interrupt on line 5 */
+#define EXTI_SWIER_SWIER6_Pos (6U)
+#define EXTI_SWIER_SWIER6_Msk (0x1U << EXTI_SWIER_SWIER6_Pos) /*!< 0x00000040 */
+#define EXTI_SWIER_SWIER6 EXTI_SWIER_SWIER6_Msk /*!< Software Interrupt on line 6 */
+#define EXTI_SWIER_SWIER7_Pos (7U)
+#define EXTI_SWIER_SWIER7_Msk (0x1U << EXTI_SWIER_SWIER7_Pos) /*!< 0x00000080 */
+#define EXTI_SWIER_SWIER7 EXTI_SWIER_SWIER7_Msk /*!< Software Interrupt on line 7 */
+#define EXTI_SWIER_SWIER8_Pos (8U)
+#define EXTI_SWIER_SWIER8_Msk (0x1U << EXTI_SWIER_SWIER8_Pos) /*!< 0x00000100 */
+#define EXTI_SWIER_SWIER8 EXTI_SWIER_SWIER8_Msk /*!< Software Interrupt on line 8 */
+#define EXTI_SWIER_SWIER9_Pos (9U)
+#define EXTI_SWIER_SWIER9_Msk (0x1U << EXTI_SWIER_SWIER9_Pos) /*!< 0x00000200 */
+#define EXTI_SWIER_SWIER9 EXTI_SWIER_SWIER9_Msk /*!< Software Interrupt on line 9 */
+#define EXTI_SWIER_SWIER10_Pos (10U)
+#define EXTI_SWIER_SWIER10_Msk (0x1U << EXTI_SWIER_SWIER10_Pos) /*!< 0x00000400 */
+#define EXTI_SWIER_SWIER10 EXTI_SWIER_SWIER10_Msk /*!< Software Interrupt on line 10 */
+#define EXTI_SWIER_SWIER11_Pos (11U)
+#define EXTI_SWIER_SWIER11_Msk (0x1U << EXTI_SWIER_SWIER11_Pos) /*!< 0x00000800 */
+#define EXTI_SWIER_SWIER11 EXTI_SWIER_SWIER11_Msk /*!< Software Interrupt on line 11 */
+#define EXTI_SWIER_SWIER12_Pos (12U)
+#define EXTI_SWIER_SWIER12_Msk (0x1U << EXTI_SWIER_SWIER12_Pos) /*!< 0x00001000 */
+#define EXTI_SWIER_SWIER12 EXTI_SWIER_SWIER12_Msk /*!< Software Interrupt on line 12 */
+#define EXTI_SWIER_SWIER13_Pos (13U)
+#define EXTI_SWIER_SWIER13_Msk (0x1U << EXTI_SWIER_SWIER13_Pos) /*!< 0x00002000 */
+#define EXTI_SWIER_SWIER13 EXTI_SWIER_SWIER13_Msk /*!< Software Interrupt on line 13 */
+#define EXTI_SWIER_SWIER14_Pos (14U)
+#define EXTI_SWIER_SWIER14_Msk (0x1U << EXTI_SWIER_SWIER14_Pos) /*!< 0x00004000 */
+#define EXTI_SWIER_SWIER14 EXTI_SWIER_SWIER14_Msk /*!< Software Interrupt on line 14 */
+#define EXTI_SWIER_SWIER15_Pos (15U)
+#define EXTI_SWIER_SWIER15_Msk (0x1U << EXTI_SWIER_SWIER15_Pos) /*!< 0x00008000 */
+#define EXTI_SWIER_SWIER15 EXTI_SWIER_SWIER15_Msk /*!< Software Interrupt on line 15 */
+#define EXTI_SWIER_SWIER16_Pos (16U)
+#define EXTI_SWIER_SWIER16_Msk (0x1U << EXTI_SWIER_SWIER16_Pos) /*!< 0x00010000 */
+#define EXTI_SWIER_SWIER16 EXTI_SWIER_SWIER16_Msk /*!< Software Interrupt on line 16 */
+#define EXTI_SWIER_SWIER17_Pos (17U)
+#define EXTI_SWIER_SWIER17_Msk (0x1U << EXTI_SWIER_SWIER17_Pos) /*!< 0x00020000 */
+#define EXTI_SWIER_SWIER17 EXTI_SWIER_SWIER17_Msk /*!< Software Interrupt on line 17 */
+#define EXTI_SWIER_SWIER18_Pos (18U)
+#define EXTI_SWIER_SWIER18_Msk (0x1U << EXTI_SWIER_SWIER18_Pos) /*!< 0x00040000 */
+#define EXTI_SWIER_SWIER18 EXTI_SWIER_SWIER18_Msk /*!< Software Interrupt on line 18 */
+#define EXTI_SWIER_SWIER19_Pos (19U)
+#define EXTI_SWIER_SWIER19_Msk (0x1U << EXTI_SWIER_SWIER19_Pos) /*!< 0x00080000 */
+#define EXTI_SWIER_SWIER19 EXTI_SWIER_SWIER19_Msk /*!< Software Interrupt on line 19 */
+
+/* References Defines */
+#define EXTI_SWIER_SWI0 EXTI_SWIER_SWIER0
+#define EXTI_SWIER_SWI1 EXTI_SWIER_SWIER1
+#define EXTI_SWIER_SWI2 EXTI_SWIER_SWIER2
+#define EXTI_SWIER_SWI3 EXTI_SWIER_SWIER3
+#define EXTI_SWIER_SWI4 EXTI_SWIER_SWIER4
+#define EXTI_SWIER_SWI5 EXTI_SWIER_SWIER5
+#define EXTI_SWIER_SWI6 EXTI_SWIER_SWIER6
+#define EXTI_SWIER_SWI7 EXTI_SWIER_SWIER7
+#define EXTI_SWIER_SWI8 EXTI_SWIER_SWIER8
+#define EXTI_SWIER_SWI9 EXTI_SWIER_SWIER9
+#define EXTI_SWIER_SWI10 EXTI_SWIER_SWIER10
+#define EXTI_SWIER_SWI11 EXTI_SWIER_SWIER11
+#define EXTI_SWIER_SWI12 EXTI_SWIER_SWIER12
+#define EXTI_SWIER_SWI13 EXTI_SWIER_SWIER13
+#define EXTI_SWIER_SWI14 EXTI_SWIER_SWIER14
+#define EXTI_SWIER_SWI15 EXTI_SWIER_SWIER15
+#define EXTI_SWIER_SWI16 EXTI_SWIER_SWIER16
+#define EXTI_SWIER_SWI17 EXTI_SWIER_SWIER17
+#define EXTI_SWIER_SWI18 EXTI_SWIER_SWIER18
+#define EXTI_SWIER_SWI19 EXTI_SWIER_SWIER19
+
+/******************* Bit definition for EXTI_PR register ********************/
+#define EXTI_PR_PR0_Pos (0U)
+#define EXTI_PR_PR0_Msk (0x1U << EXTI_PR_PR0_Pos) /*!< 0x00000001 */
+#define EXTI_PR_PR0 EXTI_PR_PR0_Msk /*!< Pending bit for line 0 */
+#define EXTI_PR_PR1_Pos (1U)
+#define EXTI_PR_PR1_Msk (0x1U << EXTI_PR_PR1_Pos) /*!< 0x00000002 */
+#define EXTI_PR_PR1 EXTI_PR_PR1_Msk /*!< Pending bit for line 1 */
+#define EXTI_PR_PR2_Pos (2U)
+#define EXTI_PR_PR2_Msk (0x1U << EXTI_PR_PR2_Pos) /*!< 0x00000004 */
+#define EXTI_PR_PR2 EXTI_PR_PR2_Msk /*!< Pending bit for line 2 */
+#define EXTI_PR_PR3_Pos (3U)
+#define EXTI_PR_PR3_Msk (0x1U << EXTI_PR_PR3_Pos) /*!< 0x00000008 */
+#define EXTI_PR_PR3 EXTI_PR_PR3_Msk /*!< Pending bit for line 3 */
+#define EXTI_PR_PR4_Pos (4U)
+#define EXTI_PR_PR4_Msk (0x1U << EXTI_PR_PR4_Pos) /*!< 0x00000010 */
+#define EXTI_PR_PR4 EXTI_PR_PR4_Msk /*!< Pending bit for line 4 */
+#define EXTI_PR_PR5_Pos (5U)
+#define EXTI_PR_PR5_Msk (0x1U << EXTI_PR_PR5_Pos) /*!< 0x00000020 */
+#define EXTI_PR_PR5 EXTI_PR_PR5_Msk /*!< Pending bit for line 5 */
+#define EXTI_PR_PR6_Pos (6U)
+#define EXTI_PR_PR6_Msk (0x1U << EXTI_PR_PR6_Pos) /*!< 0x00000040 */
+#define EXTI_PR_PR6 EXTI_PR_PR6_Msk /*!< Pending bit for line 6 */
+#define EXTI_PR_PR7_Pos (7U)
+#define EXTI_PR_PR7_Msk (0x1U << EXTI_PR_PR7_Pos) /*!< 0x00000080 */
+#define EXTI_PR_PR7 EXTI_PR_PR7_Msk /*!< Pending bit for line 7 */
+#define EXTI_PR_PR8_Pos (8U)
+#define EXTI_PR_PR8_Msk (0x1U << EXTI_PR_PR8_Pos) /*!< 0x00000100 */
+#define EXTI_PR_PR8 EXTI_PR_PR8_Msk /*!< Pending bit for line 8 */
+#define EXTI_PR_PR9_Pos (9U)
+#define EXTI_PR_PR9_Msk (0x1U << EXTI_PR_PR9_Pos) /*!< 0x00000200 */
+#define EXTI_PR_PR9 EXTI_PR_PR9_Msk /*!< Pending bit for line 9 */
+#define EXTI_PR_PR10_Pos (10U)
+#define EXTI_PR_PR10_Msk (0x1U << EXTI_PR_PR10_Pos) /*!< 0x00000400 */
+#define EXTI_PR_PR10 EXTI_PR_PR10_Msk /*!< Pending bit for line 10 */
+#define EXTI_PR_PR11_Pos (11U)
+#define EXTI_PR_PR11_Msk (0x1U << EXTI_PR_PR11_Pos) /*!< 0x00000800 */
+#define EXTI_PR_PR11 EXTI_PR_PR11_Msk /*!< Pending bit for line 11 */
+#define EXTI_PR_PR12_Pos (12U)
+#define EXTI_PR_PR12_Msk (0x1U << EXTI_PR_PR12_Pos) /*!< 0x00001000 */
+#define EXTI_PR_PR12 EXTI_PR_PR12_Msk /*!< Pending bit for line 12 */
+#define EXTI_PR_PR13_Pos (13U)
+#define EXTI_PR_PR13_Msk (0x1U << EXTI_PR_PR13_Pos) /*!< 0x00002000 */
+#define EXTI_PR_PR13 EXTI_PR_PR13_Msk /*!< Pending bit for line 13 */
+#define EXTI_PR_PR14_Pos (14U)
+#define EXTI_PR_PR14_Msk (0x1U << EXTI_PR_PR14_Pos) /*!< 0x00004000 */
+#define EXTI_PR_PR14 EXTI_PR_PR14_Msk /*!< Pending bit for line 14 */
+#define EXTI_PR_PR15_Pos (15U)
+#define EXTI_PR_PR15_Msk (0x1U << EXTI_PR_PR15_Pos) /*!< 0x00008000 */
+#define EXTI_PR_PR15 EXTI_PR_PR15_Msk /*!< Pending bit for line 15 */
+#define EXTI_PR_PR16_Pos (16U)
+#define EXTI_PR_PR16_Msk (0x1U << EXTI_PR_PR16_Pos) /*!< 0x00010000 */
+#define EXTI_PR_PR16 EXTI_PR_PR16_Msk /*!< Pending bit for line 16 */
+#define EXTI_PR_PR17_Pos (17U)
+#define EXTI_PR_PR17_Msk (0x1U << EXTI_PR_PR17_Pos) /*!< 0x00020000 */
+#define EXTI_PR_PR17 EXTI_PR_PR17_Msk /*!< Pending bit for line 17 */
+#define EXTI_PR_PR18_Pos (18U)
+#define EXTI_PR_PR18_Msk (0x1U << EXTI_PR_PR18_Pos) /*!< 0x00040000 */
+#define EXTI_PR_PR18 EXTI_PR_PR18_Msk /*!< Pending bit for line 18 */
+#define EXTI_PR_PR19_Pos (19U)
+#define EXTI_PR_PR19_Msk (0x1U << EXTI_PR_PR19_Pos) /*!< 0x00080000 */
+#define EXTI_PR_PR19 EXTI_PR_PR19_Msk /*!< Pending bit for line 19 */
+
+/* References Defines */
+#define EXTI_PR_PIF0 EXTI_PR_PR0
+#define EXTI_PR_PIF1 EXTI_PR_PR1
+#define EXTI_PR_PIF2 EXTI_PR_PR2
+#define EXTI_PR_PIF3 EXTI_PR_PR3
+#define EXTI_PR_PIF4 EXTI_PR_PR4
+#define EXTI_PR_PIF5 EXTI_PR_PR5
+#define EXTI_PR_PIF6 EXTI_PR_PR6
+#define EXTI_PR_PIF7 EXTI_PR_PR7
+#define EXTI_PR_PIF8 EXTI_PR_PR8
+#define EXTI_PR_PIF9 EXTI_PR_PR9
+#define EXTI_PR_PIF10 EXTI_PR_PR10
+#define EXTI_PR_PIF11 EXTI_PR_PR11
+#define EXTI_PR_PIF12 EXTI_PR_PR12
+#define EXTI_PR_PIF13 EXTI_PR_PR13
+#define EXTI_PR_PIF14 EXTI_PR_PR14
+#define EXTI_PR_PIF15 EXTI_PR_PR15
+#define EXTI_PR_PIF16 EXTI_PR_PR16
+#define EXTI_PR_PIF17 EXTI_PR_PR17
+#define EXTI_PR_PIF18 EXTI_PR_PR18
+#define EXTI_PR_PIF19 EXTI_PR_PR19
+
+/******************************************************************************/
+/* */
+/* DMA Controller */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for DMA_ISR register ********************/
+#define DMA_ISR_GIF1_Pos (0U)
+#define DMA_ISR_GIF1_Msk (0x1U << DMA_ISR_GIF1_Pos) /*!< 0x00000001 */
+#define DMA_ISR_GIF1 DMA_ISR_GIF1_Msk /*!< Channel 1 Global interrupt flag */
+#define DMA_ISR_TCIF1_Pos (1U)
+#define DMA_ISR_TCIF1_Msk (0x1U << DMA_ISR_TCIF1_Pos) /*!< 0x00000002 */
+#define DMA_ISR_TCIF1 DMA_ISR_TCIF1_Msk /*!< Channel 1 Transfer Complete flag */
+#define DMA_ISR_HTIF1_Pos (2U)
+#define DMA_ISR_HTIF1_Msk (0x1U << DMA_ISR_HTIF1_Pos) /*!< 0x00000004 */
+#define DMA_ISR_HTIF1 DMA_ISR_HTIF1_Msk /*!< Channel 1 Half Transfer flag */
+#define DMA_ISR_TEIF1_Pos (3U)
+#define DMA_ISR_TEIF1_Msk (0x1U << DMA_ISR_TEIF1_Pos) /*!< 0x00000008 */
+#define DMA_ISR_TEIF1 DMA_ISR_TEIF1_Msk /*!< Channel 1 Transfer Error flag */
+#define DMA_ISR_GIF2_Pos (4U)
+#define DMA_ISR_GIF2_Msk (0x1U << DMA_ISR_GIF2_Pos) /*!< 0x00000010 */
+#define DMA_ISR_GIF2 DMA_ISR_GIF2_Msk /*!< Channel 2 Global interrupt flag */
+#define DMA_ISR_TCIF2_Pos (5U)
+#define DMA_ISR_TCIF2_Msk (0x1U << DMA_ISR_TCIF2_Pos) /*!< 0x00000020 */
+#define DMA_ISR_TCIF2 DMA_ISR_TCIF2_Msk /*!< Channel 2 Transfer Complete flag */
+#define DMA_ISR_HTIF2_Pos (6U)
+#define DMA_ISR_HTIF2_Msk (0x1U << DMA_ISR_HTIF2_Pos) /*!< 0x00000040 */
+#define DMA_ISR_HTIF2 DMA_ISR_HTIF2_Msk /*!< Channel 2 Half Transfer flag */
+#define DMA_ISR_TEIF2_Pos (7U)
+#define DMA_ISR_TEIF2_Msk (0x1U << DMA_ISR_TEIF2_Pos) /*!< 0x00000080 */
+#define DMA_ISR_TEIF2 DMA_ISR_TEIF2_Msk /*!< Channel 2 Transfer Error flag */
+#define DMA_ISR_GIF3_Pos (8U)
+#define DMA_ISR_GIF3_Msk (0x1U << DMA_ISR_GIF3_Pos) /*!< 0x00000100 */
+#define DMA_ISR_GIF3 DMA_ISR_GIF3_Msk /*!< Channel 3 Global interrupt flag */
+#define DMA_ISR_TCIF3_Pos (9U)
+#define DMA_ISR_TCIF3_Msk (0x1U << DMA_ISR_TCIF3_Pos) /*!< 0x00000200 */
+#define DMA_ISR_TCIF3 DMA_ISR_TCIF3_Msk /*!< Channel 3 Transfer Complete flag */
+#define DMA_ISR_HTIF3_Pos (10U)
+#define DMA_ISR_HTIF3_Msk (0x1U << DMA_ISR_HTIF3_Pos) /*!< 0x00000400 */
+#define DMA_ISR_HTIF3 DMA_ISR_HTIF3_Msk /*!< Channel 3 Half Transfer flag */
+#define DMA_ISR_TEIF3_Pos (11U)
+#define DMA_ISR_TEIF3_Msk (0x1U << DMA_ISR_TEIF3_Pos) /*!< 0x00000800 */
+#define DMA_ISR_TEIF3 DMA_ISR_TEIF3_Msk /*!< Channel 3 Transfer Error flag */
+#define DMA_ISR_GIF4_Pos (12U)
+#define DMA_ISR_GIF4_Msk (0x1U << DMA_ISR_GIF4_Pos) /*!< 0x00001000 */
+#define DMA_ISR_GIF4 DMA_ISR_GIF4_Msk /*!< Channel 4 Global interrupt flag */
+#define DMA_ISR_TCIF4_Pos (13U)
+#define DMA_ISR_TCIF4_Msk (0x1U << DMA_ISR_TCIF4_Pos) /*!< 0x00002000 */
+#define DMA_ISR_TCIF4 DMA_ISR_TCIF4_Msk /*!< Channel 4 Transfer Complete flag */
+#define DMA_ISR_HTIF4_Pos (14U)
+#define DMA_ISR_HTIF4_Msk (0x1U << DMA_ISR_HTIF4_Pos) /*!< 0x00004000 */
+#define DMA_ISR_HTIF4 DMA_ISR_HTIF4_Msk /*!< Channel 4 Half Transfer flag */
+#define DMA_ISR_TEIF4_Pos (15U)
+#define DMA_ISR_TEIF4_Msk (0x1U << DMA_ISR_TEIF4_Pos) /*!< 0x00008000 */
+#define DMA_ISR_TEIF4 DMA_ISR_TEIF4_Msk /*!< Channel 4 Transfer Error flag */
+#define DMA_ISR_GIF5_Pos (16U)
+#define DMA_ISR_GIF5_Msk (0x1U << DMA_ISR_GIF5_Pos) /*!< 0x00010000 */
+#define DMA_ISR_GIF5 DMA_ISR_GIF5_Msk /*!< Channel 5 Global interrupt flag */
+#define DMA_ISR_TCIF5_Pos (17U)
+#define DMA_ISR_TCIF5_Msk (0x1U << DMA_ISR_TCIF5_Pos) /*!< 0x00020000 */
+#define DMA_ISR_TCIF5 DMA_ISR_TCIF5_Msk /*!< Channel 5 Transfer Complete flag */
+#define DMA_ISR_HTIF5_Pos (18U)
+#define DMA_ISR_HTIF5_Msk (0x1U << DMA_ISR_HTIF5_Pos) /*!< 0x00040000 */
+#define DMA_ISR_HTIF5 DMA_ISR_HTIF5_Msk /*!< Channel 5 Half Transfer flag */
+#define DMA_ISR_TEIF5_Pos (19U)
+#define DMA_ISR_TEIF5_Msk (0x1U << DMA_ISR_TEIF5_Pos) /*!< 0x00080000 */
+#define DMA_ISR_TEIF5 DMA_ISR_TEIF5_Msk /*!< Channel 5 Transfer Error flag */
+#define DMA_ISR_GIF6_Pos (20U)
+#define DMA_ISR_GIF6_Msk (0x1U << DMA_ISR_GIF6_Pos) /*!< 0x00100000 */
+#define DMA_ISR_GIF6 DMA_ISR_GIF6_Msk /*!< Channel 6 Global interrupt flag */
+#define DMA_ISR_TCIF6_Pos (21U)
+#define DMA_ISR_TCIF6_Msk (0x1U << DMA_ISR_TCIF6_Pos) /*!< 0x00200000 */
+#define DMA_ISR_TCIF6 DMA_ISR_TCIF6_Msk /*!< Channel 6 Transfer Complete flag */
+#define DMA_ISR_HTIF6_Pos (22U)
+#define DMA_ISR_HTIF6_Msk (0x1U << DMA_ISR_HTIF6_Pos) /*!< 0x00400000 */
+#define DMA_ISR_HTIF6 DMA_ISR_HTIF6_Msk /*!< Channel 6 Half Transfer flag */
+#define DMA_ISR_TEIF6_Pos (23U)
+#define DMA_ISR_TEIF6_Msk (0x1U << DMA_ISR_TEIF6_Pos) /*!< 0x00800000 */
+#define DMA_ISR_TEIF6 DMA_ISR_TEIF6_Msk /*!< Channel 6 Transfer Error flag */
+#define DMA_ISR_GIF7_Pos (24U)
+#define DMA_ISR_GIF7_Msk (0x1U << DMA_ISR_GIF7_Pos) /*!< 0x01000000 */
+#define DMA_ISR_GIF7 DMA_ISR_GIF7_Msk /*!< Channel 7 Global interrupt flag */
+#define DMA_ISR_TCIF7_Pos (25U)
+#define DMA_ISR_TCIF7_Msk (0x1U << DMA_ISR_TCIF7_Pos) /*!< 0x02000000 */
+#define DMA_ISR_TCIF7 DMA_ISR_TCIF7_Msk /*!< Channel 7 Transfer Complete flag */
+#define DMA_ISR_HTIF7_Pos (26U)
+#define DMA_ISR_HTIF7_Msk (0x1U << DMA_ISR_HTIF7_Pos) /*!< 0x04000000 */
+#define DMA_ISR_HTIF7 DMA_ISR_HTIF7_Msk /*!< Channel 7 Half Transfer flag */
+#define DMA_ISR_TEIF7_Pos (27U)
+#define DMA_ISR_TEIF7_Msk (0x1U << DMA_ISR_TEIF7_Pos) /*!< 0x08000000 */
+#define DMA_ISR_TEIF7 DMA_ISR_TEIF7_Msk /*!< Channel 7 Transfer Error flag */
+
+/******************* Bit definition for DMA_IFCR register *******************/
+#define DMA_IFCR_CGIF1_Pos (0U)
+#define DMA_IFCR_CGIF1_Msk (0x1U << DMA_IFCR_CGIF1_Pos) /*!< 0x00000001 */
+#define DMA_IFCR_CGIF1 DMA_IFCR_CGIF1_Msk /*!< Channel 1 Global interrupt clear */
+#define DMA_IFCR_CTCIF1_Pos (1U)
+#define DMA_IFCR_CTCIF1_Msk (0x1U << DMA_IFCR_CTCIF1_Pos) /*!< 0x00000002 */
+#define DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF1_Msk /*!< Channel 1 Transfer Complete clear */
+#define DMA_IFCR_CHTIF1_Pos (2U)
+#define DMA_IFCR_CHTIF1_Msk (0x1U << DMA_IFCR_CHTIF1_Pos) /*!< 0x00000004 */
+#define DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF1_Msk /*!< Channel 1 Half Transfer clear */
+#define DMA_IFCR_CTEIF1_Pos (3U)
+#define DMA_IFCR_CTEIF1_Msk (0x1U << DMA_IFCR_CTEIF1_Pos) /*!< 0x00000008 */
+#define DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF1_Msk /*!< Channel 1 Transfer Error clear */
+#define DMA_IFCR_CGIF2_Pos (4U)
+#define DMA_IFCR_CGIF2_Msk (0x1U << DMA_IFCR_CGIF2_Pos) /*!< 0x00000010 */
+#define DMA_IFCR_CGIF2 DMA_IFCR_CGIF2_Msk /*!< Channel 2 Global interrupt clear */
+#define DMA_IFCR_CTCIF2_Pos (5U)
+#define DMA_IFCR_CTCIF2_Msk (0x1U << DMA_IFCR_CTCIF2_Pos) /*!< 0x00000020 */
+#define DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF2_Msk /*!< Channel 2 Transfer Complete clear */
+#define DMA_IFCR_CHTIF2_Pos (6U)
+#define DMA_IFCR_CHTIF2_Msk (0x1U << DMA_IFCR_CHTIF2_Pos) /*!< 0x00000040 */
+#define DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF2_Msk /*!< Channel 2 Half Transfer clear */
+#define DMA_IFCR_CTEIF2_Pos (7U)
+#define DMA_IFCR_CTEIF2_Msk (0x1U << DMA_IFCR_CTEIF2_Pos) /*!< 0x00000080 */
+#define DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF2_Msk /*!< Channel 2 Transfer Error clear */
+#define DMA_IFCR_CGIF3_Pos (8U)
+#define DMA_IFCR_CGIF3_Msk (0x1U << DMA_IFCR_CGIF3_Pos) /*!< 0x00000100 */
+#define DMA_IFCR_CGIF3 DMA_IFCR_CGIF3_Msk /*!< Channel 3 Global interrupt clear */
+#define DMA_IFCR_CTCIF3_Pos (9U)
+#define DMA_IFCR_CTCIF3_Msk (0x1U << DMA_IFCR_CTCIF3_Pos) /*!< 0x00000200 */
+#define DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF3_Msk /*!< Channel 3 Transfer Complete clear */
+#define DMA_IFCR_CHTIF3_Pos (10U)
+#define DMA_IFCR_CHTIF3_Msk (0x1U << DMA_IFCR_CHTIF3_Pos) /*!< 0x00000400 */
+#define DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF3_Msk /*!< Channel 3 Half Transfer clear */
+#define DMA_IFCR_CTEIF3_Pos (11U)
+#define DMA_IFCR_CTEIF3_Msk (0x1U << DMA_IFCR_CTEIF3_Pos) /*!< 0x00000800 */
+#define DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF3_Msk /*!< Channel 3 Transfer Error clear */
+#define DMA_IFCR_CGIF4_Pos (12U)
+#define DMA_IFCR_CGIF4_Msk (0x1U << DMA_IFCR_CGIF4_Pos) /*!< 0x00001000 */
+#define DMA_IFCR_CGIF4 DMA_IFCR_CGIF4_Msk /*!< Channel 4 Global interrupt clear */
+#define DMA_IFCR_CTCIF4_Pos (13U)
+#define DMA_IFCR_CTCIF4_Msk (0x1U << DMA_IFCR_CTCIF4_Pos) /*!< 0x00002000 */
+#define DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF4_Msk /*!< Channel 4 Transfer Complete clear */
+#define DMA_IFCR_CHTIF4_Pos (14U)
+#define DMA_IFCR_CHTIF4_Msk (0x1U << DMA_IFCR_CHTIF4_Pos) /*!< 0x00004000 */
+#define DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF4_Msk /*!< Channel 4 Half Transfer clear */
+#define DMA_IFCR_CTEIF4_Pos (15U)
+#define DMA_IFCR_CTEIF4_Msk (0x1U << DMA_IFCR_CTEIF4_Pos) /*!< 0x00008000 */
+#define DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF4_Msk /*!< Channel 4 Transfer Error clear */
+#define DMA_IFCR_CGIF5_Pos (16U)
+#define DMA_IFCR_CGIF5_Msk (0x1U << DMA_IFCR_CGIF5_Pos) /*!< 0x00010000 */
+#define DMA_IFCR_CGIF5 DMA_IFCR_CGIF5_Msk /*!< Channel 5 Global interrupt clear */
+#define DMA_IFCR_CTCIF5_Pos (17U)
+#define DMA_IFCR_CTCIF5_Msk (0x1U << DMA_IFCR_CTCIF5_Pos) /*!< 0x00020000 */
+#define DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF5_Msk /*!< Channel 5 Transfer Complete clear */
+#define DMA_IFCR_CHTIF5_Pos (18U)
+#define DMA_IFCR_CHTIF5_Msk (0x1U << DMA_IFCR_CHTIF5_Pos) /*!< 0x00040000 */
+#define DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5_Msk /*!< Channel 5 Half Transfer clear */
+#define DMA_IFCR_CTEIF5_Pos (19U)
+#define DMA_IFCR_CTEIF5_Msk (0x1U << DMA_IFCR_CTEIF5_Pos) /*!< 0x00080000 */
+#define DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF5_Msk /*!< Channel 5 Transfer Error clear */
+#define DMA_IFCR_CGIF6_Pos (20U)
+#define DMA_IFCR_CGIF6_Msk (0x1U << DMA_IFCR_CGIF6_Pos) /*!< 0x00100000 */
+#define DMA_IFCR_CGIF6 DMA_IFCR_CGIF6_Msk /*!< Channel 6 Global interrupt clear */
+#define DMA_IFCR_CTCIF6_Pos (21U)
+#define DMA_IFCR_CTCIF6_Msk (0x1U << DMA_IFCR_CTCIF6_Pos) /*!< 0x00200000 */
+#define DMA_IFCR_CTCIF6 DMA_IFCR_CTCIF6_Msk /*!< Channel 6 Transfer Complete clear */
+#define DMA_IFCR_CHTIF6_Pos (22U)
+#define DMA_IFCR_CHTIF6_Msk (0x1U << DMA_IFCR_CHTIF6_Pos) /*!< 0x00400000 */
+#define DMA_IFCR_CHTIF6 DMA_IFCR_CHTIF6_Msk /*!< Channel 6 Half Transfer clear */
+#define DMA_IFCR_CTEIF6_Pos (23U)
+#define DMA_IFCR_CTEIF6_Msk (0x1U << DMA_IFCR_CTEIF6_Pos) /*!< 0x00800000 */
+#define DMA_IFCR_CTEIF6 DMA_IFCR_CTEIF6_Msk /*!< Channel 6 Transfer Error clear */
+#define DMA_IFCR_CGIF7_Pos (24U)
+#define DMA_IFCR_CGIF7_Msk (0x1U << DMA_IFCR_CGIF7_Pos) /*!< 0x01000000 */
+#define DMA_IFCR_CGIF7 DMA_IFCR_CGIF7_Msk /*!< Channel 7 Global interrupt clear */
+#define DMA_IFCR_CTCIF7_Pos (25U)
+#define DMA_IFCR_CTCIF7_Msk (0x1U << DMA_IFCR_CTCIF7_Pos) /*!< 0x02000000 */
+#define DMA_IFCR_CTCIF7 DMA_IFCR_CTCIF7_Msk /*!< Channel 7 Transfer Complete clear */
+#define DMA_IFCR_CHTIF7_Pos (26U)
+#define DMA_IFCR_CHTIF7_Msk (0x1U << DMA_IFCR_CHTIF7_Pos) /*!< 0x04000000 */
+#define DMA_IFCR_CHTIF7 DMA_IFCR_CHTIF7_Msk /*!< Channel 7 Half Transfer clear */
+#define DMA_IFCR_CTEIF7_Pos (27U)
+#define DMA_IFCR_CTEIF7_Msk (0x1U << DMA_IFCR_CTEIF7_Pos) /*!< 0x08000000 */
+#define DMA_IFCR_CTEIF7 DMA_IFCR_CTEIF7_Msk /*!< Channel 7 Transfer Error clear */
+
+/******************* Bit definition for DMA_CCR register *******************/
+#define DMA_CCR_EN_Pos (0U)
+#define DMA_CCR_EN_Msk (0x1U << DMA_CCR_EN_Pos) /*!< 0x00000001 */
+#define DMA_CCR_EN DMA_CCR_EN_Msk /*!< Channel enable */
+#define DMA_CCR_TCIE_Pos (1U)
+#define DMA_CCR_TCIE_Msk (0x1U << DMA_CCR_TCIE_Pos) /*!< 0x00000002 */
+#define DMA_CCR_TCIE DMA_CCR_TCIE_Msk /*!< Transfer complete interrupt enable */
+#define DMA_CCR_HTIE_Pos (2U)
+#define DMA_CCR_HTIE_Msk (0x1U << DMA_CCR_HTIE_Pos) /*!< 0x00000004 */
+#define DMA_CCR_HTIE DMA_CCR_HTIE_Msk /*!< Half Transfer interrupt enable */
+#define DMA_CCR_TEIE_Pos (3U)
+#define DMA_CCR_TEIE_Msk (0x1U << DMA_CCR_TEIE_Pos) /*!< 0x00000008 */
+#define DMA_CCR_TEIE DMA_CCR_TEIE_Msk /*!< Transfer error interrupt enable */
+#define DMA_CCR_DIR_Pos (4U)
+#define DMA_CCR_DIR_Msk (0x1U << DMA_CCR_DIR_Pos) /*!< 0x00000010 */
+#define DMA_CCR_DIR DMA_CCR_DIR_Msk /*!< Data transfer direction */
+#define DMA_CCR_CIRC_Pos (5U)
+#define DMA_CCR_CIRC_Msk (0x1U << DMA_CCR_CIRC_Pos) /*!< 0x00000020 */
+#define DMA_CCR_CIRC DMA_CCR_CIRC_Msk /*!< Circular mode */
+#define DMA_CCR_PINC_Pos (6U)
+#define DMA_CCR_PINC_Msk (0x1U << DMA_CCR_PINC_Pos) /*!< 0x00000040 */
+#define DMA_CCR_PINC DMA_CCR_PINC_Msk /*!< Peripheral increment mode */
+#define DMA_CCR_MINC_Pos (7U)
+#define DMA_CCR_MINC_Msk (0x1U << DMA_CCR_MINC_Pos) /*!< 0x00000080 */
+#define DMA_CCR_MINC DMA_CCR_MINC_Msk /*!< Memory increment mode */
+
+#define DMA_CCR_PSIZE_Pos (8U)
+#define DMA_CCR_PSIZE_Msk (0x3U << DMA_CCR_PSIZE_Pos) /*!< 0x00000300 */
+#define DMA_CCR_PSIZE DMA_CCR_PSIZE_Msk /*!< PSIZE[1:0] bits (Peripheral size) */
+#define DMA_CCR_PSIZE_0 (0x1U << DMA_CCR_PSIZE_Pos) /*!< 0x00000100 */
+#define DMA_CCR_PSIZE_1 (0x2U << DMA_CCR_PSIZE_Pos) /*!< 0x00000200 */
+
+#define DMA_CCR_MSIZE_Pos (10U)
+#define DMA_CCR_MSIZE_Msk (0x3U << DMA_CCR_MSIZE_Pos) /*!< 0x00000C00 */
+#define DMA_CCR_MSIZE DMA_CCR_MSIZE_Msk /*!< MSIZE[1:0] bits (Memory size) */
+#define DMA_CCR_MSIZE_0 (0x1U << DMA_CCR_MSIZE_Pos) /*!< 0x00000400 */
+#define DMA_CCR_MSIZE_1 (0x2U << DMA_CCR_MSIZE_Pos) /*!< 0x00000800 */
+
+#define DMA_CCR_PL_Pos (12U)
+#define DMA_CCR_PL_Msk (0x3U << DMA_CCR_PL_Pos) /*!< 0x00003000 */
+#define DMA_CCR_PL DMA_CCR_PL_Msk /*!< PL[1:0] bits(Channel Priority level) */
+#define DMA_CCR_PL_0 (0x1U << DMA_CCR_PL_Pos) /*!< 0x00001000 */
+#define DMA_CCR_PL_1 (0x2U << DMA_CCR_PL_Pos) /*!< 0x00002000 */
+
+#define DMA_CCR_MEM2MEM_Pos (14U)
+#define DMA_CCR_MEM2MEM_Msk (0x1U << DMA_CCR_MEM2MEM_Pos) /*!< 0x00004000 */
+#define DMA_CCR_MEM2MEM DMA_CCR_MEM2MEM_Msk /*!< Memory to memory mode */
+
+/****************** Bit definition for DMA_CNDTR register ******************/
+#define DMA_CNDTR_NDT_Pos (0U)
+#define DMA_CNDTR_NDT_Msk (0xFFFFU << DMA_CNDTR_NDT_Pos) /*!< 0x0000FFFF */
+#define DMA_CNDTR_NDT DMA_CNDTR_NDT_Msk /*!< Number of data to Transfer */
+
+/****************** Bit definition for DMA_CPAR register *******************/
+#define DMA_CPAR_PA_Pos (0U)
+#define DMA_CPAR_PA_Msk (0xFFFFFFFFU << DMA_CPAR_PA_Pos) /*!< 0xFFFFFFFF */
+#define DMA_CPAR_PA DMA_CPAR_PA_Msk /*!< Peripheral Address */
+
+/****************** Bit definition for DMA_CMAR register *******************/
+#define DMA_CMAR_MA_Pos (0U)
+#define DMA_CMAR_MA_Msk (0xFFFFFFFFU << DMA_CMAR_MA_Pos) /*!< 0xFFFFFFFF */
+#define DMA_CMAR_MA DMA_CMAR_MA_Msk /*!< Memory Address */
+
+/******************************************************************************/
+/* */
+/* Analog to Digital Converter (ADC) */
+/* */
+/******************************************************************************/
+
+/*
+ * @brief Specific device feature definitions (not present on all devices in the STM32F1 family)
+ */
+/* Note: No specific macro feature on this device */
+
+/******************** Bit definition for ADC_SR register ********************/
+#define ADC_SR_AWD_Pos (0U)
+#define ADC_SR_AWD_Msk (0x1U << ADC_SR_AWD_Pos) /*!< 0x00000001 */
+#define ADC_SR_AWD ADC_SR_AWD_Msk /*!< ADC analog watchdog 1 flag */
+#define ADC_SR_EOS_Pos (1U)
+#define ADC_SR_EOS_Msk (0x1U << ADC_SR_EOS_Pos) /*!< 0x00000002 */
+#define ADC_SR_EOS ADC_SR_EOS_Msk /*!< ADC group regular end of sequence conversions flag */
+#define ADC_SR_JEOS_Pos (2U)
+#define ADC_SR_JEOS_Msk (0x1U << ADC_SR_JEOS_Pos) /*!< 0x00000004 */
+#define ADC_SR_JEOS ADC_SR_JEOS_Msk /*!< ADC group injected end of sequence conversions flag */
+#define ADC_SR_JSTRT_Pos (3U)
+#define ADC_SR_JSTRT_Msk (0x1U << ADC_SR_JSTRT_Pos) /*!< 0x00000008 */
+#define ADC_SR_JSTRT ADC_SR_JSTRT_Msk /*!< ADC group injected conversion start flag */
+#define ADC_SR_STRT_Pos (4U)
+#define ADC_SR_STRT_Msk (0x1U << ADC_SR_STRT_Pos) /*!< 0x00000010 */
+#define ADC_SR_STRT ADC_SR_STRT_Msk /*!< ADC group regular conversion start flag */
+
+/* Legacy defines */
+#define ADC_SR_EOC (ADC_SR_EOS)
+#define ADC_SR_JEOC (ADC_SR_JEOS)
+
+/******************* Bit definition for ADC_CR1 register ********************/
+#define ADC_CR1_AWDCH_Pos (0U)
+#define ADC_CR1_AWDCH_Msk (0x1FU << ADC_CR1_AWDCH_Pos) /*!< 0x0000001F */
+#define ADC_CR1_AWDCH ADC_CR1_AWDCH_Msk /*!< ADC analog watchdog 1 monitored channel selection */
+#define ADC_CR1_AWDCH_0 (0x01U << ADC_CR1_AWDCH_Pos) /*!< 0x00000001 */
+#define ADC_CR1_AWDCH_1 (0x02U << ADC_CR1_AWDCH_Pos) /*!< 0x00000002 */
+#define ADC_CR1_AWDCH_2 (0x04U << ADC_CR1_AWDCH_Pos) /*!< 0x00000004 */
+#define ADC_CR1_AWDCH_3 (0x08U << ADC_CR1_AWDCH_Pos) /*!< 0x00000008 */
+#define ADC_CR1_AWDCH_4 (0x10U << ADC_CR1_AWDCH_Pos) /*!< 0x00000010 */
+
+#define ADC_CR1_EOSIE_Pos (5U)
+#define ADC_CR1_EOSIE_Msk (0x1U << ADC_CR1_EOSIE_Pos) /*!< 0x00000020 */
+#define ADC_CR1_EOSIE ADC_CR1_EOSIE_Msk /*!< ADC group regular end of sequence conversions interrupt */
+#define ADC_CR1_AWDIE_Pos (6U)
+#define ADC_CR1_AWDIE_Msk (0x1U << ADC_CR1_AWDIE_Pos) /*!< 0x00000040 */
+#define ADC_CR1_AWDIE ADC_CR1_AWDIE_Msk /*!< ADC analog watchdog 1 interrupt */
+#define ADC_CR1_JEOSIE_Pos (7U)
+#define ADC_CR1_JEOSIE_Msk (0x1U << ADC_CR1_JEOSIE_Pos) /*!< 0x00000080 */
+#define ADC_CR1_JEOSIE ADC_CR1_JEOSIE_Msk /*!< ADC group injected end of sequence conversions interrupt */
+#define ADC_CR1_SCAN_Pos (8U)
+#define ADC_CR1_SCAN_Msk (0x1U << ADC_CR1_SCAN_Pos) /*!< 0x00000100 */
+#define ADC_CR1_SCAN ADC_CR1_SCAN_Msk /*!< ADC scan mode */
+#define ADC_CR1_AWDSGL_Pos (9U)
+#define ADC_CR1_AWDSGL_Msk (0x1U << ADC_CR1_AWDSGL_Pos) /*!< 0x00000200 */
+#define ADC_CR1_AWDSGL ADC_CR1_AWDSGL_Msk /*!< ADC analog watchdog 1 monitoring a single channel or all channels */
+#define ADC_CR1_JAUTO_Pos (10U)
+#define ADC_CR1_JAUTO_Msk (0x1U << ADC_CR1_JAUTO_Pos) /*!< 0x00000400 */
+#define ADC_CR1_JAUTO ADC_CR1_JAUTO_Msk /*!< ADC group injected automatic trigger mode */
+#define ADC_CR1_DISCEN_Pos (11U)
+#define ADC_CR1_DISCEN_Msk (0x1U << ADC_CR1_DISCEN_Pos) /*!< 0x00000800 */
+#define ADC_CR1_DISCEN ADC_CR1_DISCEN_Msk /*!< ADC group regular sequencer discontinuous mode */
+#define ADC_CR1_JDISCEN_Pos (12U)
+#define ADC_CR1_JDISCEN_Msk (0x1U << ADC_CR1_JDISCEN_Pos) /*!< 0x00001000 */
+#define ADC_CR1_JDISCEN ADC_CR1_JDISCEN_Msk /*!< ADC group injected sequencer discontinuous mode */
+
+#define ADC_CR1_DISCNUM_Pos (13U)
+#define ADC_CR1_DISCNUM_Msk (0x7U << ADC_CR1_DISCNUM_Pos) /*!< 0x0000E000 */
+#define ADC_CR1_DISCNUM ADC_CR1_DISCNUM_Msk /*!< ADC group regular sequencer discontinuous number of ranks */
+#define ADC_CR1_DISCNUM_0 (0x1U << ADC_CR1_DISCNUM_Pos) /*!< 0x00002000 */
+#define ADC_CR1_DISCNUM_1 (0x2U << ADC_CR1_DISCNUM_Pos) /*!< 0x00004000 */
+#define ADC_CR1_DISCNUM_2 (0x4U << ADC_CR1_DISCNUM_Pos) /*!< 0x00008000 */
+
+#define ADC_CR1_JAWDEN_Pos (22U)
+#define ADC_CR1_JAWDEN_Msk (0x1U << ADC_CR1_JAWDEN_Pos) /*!< 0x00400000 */
+#define ADC_CR1_JAWDEN ADC_CR1_JAWDEN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group injected */
+#define ADC_CR1_AWDEN_Pos (23U)
+#define ADC_CR1_AWDEN_Msk (0x1U << ADC_CR1_AWDEN_Pos) /*!< 0x00800000 */
+#define ADC_CR1_AWDEN ADC_CR1_AWDEN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group regular */
+
+/* Legacy defines */
+#define ADC_CR1_EOCIE (ADC_CR1_EOSIE)
+#define ADC_CR1_JEOCIE (ADC_CR1_JEOSIE)
+
+/******************* Bit definition for ADC_CR2 register ********************/
+#define ADC_CR2_ADON_Pos (0U)
+#define ADC_CR2_ADON_Msk (0x1U << ADC_CR2_ADON_Pos) /*!< 0x00000001 */
+#define ADC_CR2_ADON ADC_CR2_ADON_Msk /*!< ADC enable */
+#define ADC_CR2_CONT_Pos (1U)
+#define ADC_CR2_CONT_Msk (0x1U << ADC_CR2_CONT_Pos) /*!< 0x00000002 */
+#define ADC_CR2_CONT ADC_CR2_CONT_Msk /*!< ADC group regular continuous conversion mode */
+#define ADC_CR2_CAL_Pos (2U)
+#define ADC_CR2_CAL_Msk (0x1U << ADC_CR2_CAL_Pos) /*!< 0x00000004 */
+#define ADC_CR2_CAL ADC_CR2_CAL_Msk /*!< ADC calibration start */
+#define ADC_CR2_RSTCAL_Pos (3U)
+#define ADC_CR2_RSTCAL_Msk (0x1U << ADC_CR2_RSTCAL_Pos) /*!< 0x00000008 */
+#define ADC_CR2_RSTCAL ADC_CR2_RSTCAL_Msk /*!< ADC calibration reset */
+#define ADC_CR2_DMA_Pos (8U)
+#define ADC_CR2_DMA_Msk (0x1U << ADC_CR2_DMA_Pos) /*!< 0x00000100 */
+#define ADC_CR2_DMA ADC_CR2_DMA_Msk /*!< ADC DMA transfer enable */
+#define ADC_CR2_ALIGN_Pos (11U)
+#define ADC_CR2_ALIGN_Msk (0x1U << ADC_CR2_ALIGN_Pos) /*!< 0x00000800 */
+#define ADC_CR2_ALIGN ADC_CR2_ALIGN_Msk /*!< ADC data alignement */
+
+#define ADC_CR2_JEXTSEL_Pos (12U)
+#define ADC_CR2_JEXTSEL_Msk (0x7U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00007000 */
+#define ADC_CR2_JEXTSEL ADC_CR2_JEXTSEL_Msk /*!< ADC group injected external trigger source */
+#define ADC_CR2_JEXTSEL_0 (0x1U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00001000 */
+#define ADC_CR2_JEXTSEL_1 (0x2U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00002000 */
+#define ADC_CR2_JEXTSEL_2 (0x4U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00004000 */
+
+#define ADC_CR2_JEXTTRIG_Pos (15U)
+#define ADC_CR2_JEXTTRIG_Msk (0x1U << ADC_CR2_JEXTTRIG_Pos) /*!< 0x00008000 */
+#define ADC_CR2_JEXTTRIG ADC_CR2_JEXTTRIG_Msk /*!< ADC group injected external trigger enable */
+
+#define ADC_CR2_EXTSEL_Pos (17U)
+#define ADC_CR2_EXTSEL_Msk (0x7U << ADC_CR2_EXTSEL_Pos) /*!< 0x000E0000 */
+#define ADC_CR2_EXTSEL ADC_CR2_EXTSEL_Msk /*!< ADC group regular external trigger source */
+#define ADC_CR2_EXTSEL_0 (0x1U << ADC_CR2_EXTSEL_Pos) /*!< 0x00020000 */
+#define ADC_CR2_EXTSEL_1 (0x2U << ADC_CR2_EXTSEL_Pos) /*!< 0x00040000 */
+#define ADC_CR2_EXTSEL_2 (0x4U << ADC_CR2_EXTSEL_Pos) /*!< 0x00080000 */
+
+#define ADC_CR2_EXTTRIG_Pos (20U)
+#define ADC_CR2_EXTTRIG_Msk (0x1U << ADC_CR2_EXTTRIG_Pos) /*!< 0x00100000 */
+#define ADC_CR2_EXTTRIG ADC_CR2_EXTTRIG_Msk /*!< ADC group regular external trigger enable */
+#define ADC_CR2_JSWSTART_Pos (21U)
+#define ADC_CR2_JSWSTART_Msk (0x1U << ADC_CR2_JSWSTART_Pos) /*!< 0x00200000 */
+#define ADC_CR2_JSWSTART ADC_CR2_JSWSTART_Msk /*!< ADC group injected conversion start */
+#define ADC_CR2_SWSTART_Pos (22U)
+#define ADC_CR2_SWSTART_Msk (0x1U << ADC_CR2_SWSTART_Pos) /*!< 0x00400000 */
+#define ADC_CR2_SWSTART ADC_CR2_SWSTART_Msk /*!< ADC group regular conversion start */
+#define ADC_CR2_TSVREFE_Pos (23U)
+#define ADC_CR2_TSVREFE_Msk (0x1U << ADC_CR2_TSVREFE_Pos) /*!< 0x00800000 */
+#define ADC_CR2_TSVREFE ADC_CR2_TSVREFE_Msk /*!< ADC internal path to VrefInt and temperature sensor enable */
+
+/****************** Bit definition for ADC_SMPR1 register *******************/
+#define ADC_SMPR1_SMP10_Pos (0U)
+#define ADC_SMPR1_SMP10_Msk (0x7U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000007 */
+#define ADC_SMPR1_SMP10 ADC_SMPR1_SMP10_Msk /*!< ADC channel 10 sampling time selection */
+#define ADC_SMPR1_SMP10_0 (0x1U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000001 */
+#define ADC_SMPR1_SMP10_1 (0x2U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000002 */
+#define ADC_SMPR1_SMP10_2 (0x4U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000004 */
+
+#define ADC_SMPR1_SMP11_Pos (3U)
+#define ADC_SMPR1_SMP11_Msk (0x7U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000038 */
+#define ADC_SMPR1_SMP11 ADC_SMPR1_SMP11_Msk /*!< ADC channel 11 sampling time selection */
+#define ADC_SMPR1_SMP11_0 (0x1U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000008 */
+#define ADC_SMPR1_SMP11_1 (0x2U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000010 */
+#define ADC_SMPR1_SMP11_2 (0x4U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000020 */
+
+#define ADC_SMPR1_SMP12_Pos (6U)
+#define ADC_SMPR1_SMP12_Msk (0x7U << ADC_SMPR1_SMP12_Pos) /*!< 0x000001C0 */
+#define ADC_SMPR1_SMP12 ADC_SMPR1_SMP12_Msk /*!< ADC channel 12 sampling time selection */
+#define ADC_SMPR1_SMP12_0 (0x1U << ADC_SMPR1_SMP12_Pos) /*!< 0x00000040 */
+#define ADC_SMPR1_SMP12_1 (0x2U << ADC_SMPR1_SMP12_Pos) /*!< 0x00000080 */
+#define ADC_SMPR1_SMP12_2 (0x4U << ADC_SMPR1_SMP12_Pos) /*!< 0x00000100 */
+
+#define ADC_SMPR1_SMP13_Pos (9U)
+#define ADC_SMPR1_SMP13_Msk (0x7U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000E00 */
+#define ADC_SMPR1_SMP13 ADC_SMPR1_SMP13_Msk /*!< ADC channel 13 sampling time selection */
+#define ADC_SMPR1_SMP13_0 (0x1U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000200 */
+#define ADC_SMPR1_SMP13_1 (0x2U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000400 */
+#define ADC_SMPR1_SMP13_2 (0x4U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000800 */
+
+#define ADC_SMPR1_SMP14_Pos (12U)
+#define ADC_SMPR1_SMP14_Msk (0x7U << ADC_SMPR1_SMP14_Pos) /*!< 0x00007000 */
+#define ADC_SMPR1_SMP14 ADC_SMPR1_SMP14_Msk /*!< ADC channel 14 sampling time selection */
+#define ADC_SMPR1_SMP14_0 (0x1U << ADC_SMPR1_SMP14_Pos) /*!< 0x00001000 */
+#define ADC_SMPR1_SMP14_1 (0x2U << ADC_SMPR1_SMP14_Pos) /*!< 0x00002000 */
+#define ADC_SMPR1_SMP14_2 (0x4U << ADC_SMPR1_SMP14_Pos) /*!< 0x00004000 */
+
+#define ADC_SMPR1_SMP15_Pos (15U)
+#define ADC_SMPR1_SMP15_Msk (0x7U << ADC_SMPR1_SMP15_Pos) /*!< 0x00038000 */
+#define ADC_SMPR1_SMP15 ADC_SMPR1_SMP15_Msk /*!< ADC channel 15 sampling time selection */
+#define ADC_SMPR1_SMP15_0 (0x1U << ADC_SMPR1_SMP15_Pos) /*!< 0x00008000 */
+#define ADC_SMPR1_SMP15_1 (0x2U << ADC_SMPR1_SMP15_Pos) /*!< 0x00010000 */
+#define ADC_SMPR1_SMP15_2 (0x4U << ADC_SMPR1_SMP15_Pos) /*!< 0x00020000 */
+
+#define ADC_SMPR1_SMP16_Pos (18U)
+#define ADC_SMPR1_SMP16_Msk (0x7U << ADC_SMPR1_SMP16_Pos) /*!< 0x001C0000 */
+#define ADC_SMPR1_SMP16 ADC_SMPR1_SMP16_Msk /*!< ADC channel 16 sampling time selection */
+#define ADC_SMPR1_SMP16_0 (0x1U << ADC_SMPR1_SMP16_Pos) /*!< 0x00040000 */
+#define ADC_SMPR1_SMP16_1 (0x2U << ADC_SMPR1_SMP16_Pos) /*!< 0x00080000 */
+#define ADC_SMPR1_SMP16_2 (0x4U << ADC_SMPR1_SMP16_Pos) /*!< 0x00100000 */
+
+#define ADC_SMPR1_SMP17_Pos (21U)
+#define ADC_SMPR1_SMP17_Msk (0x7U << ADC_SMPR1_SMP17_Pos) /*!< 0x00E00000 */
+#define ADC_SMPR1_SMP17 ADC_SMPR1_SMP17_Msk /*!< ADC channel 17 sampling time selection */
+#define ADC_SMPR1_SMP17_0 (0x1U << ADC_SMPR1_SMP17_Pos) /*!< 0x00200000 */
+#define ADC_SMPR1_SMP17_1 (0x2U << ADC_SMPR1_SMP17_Pos) /*!< 0x00400000 */
+#define ADC_SMPR1_SMP17_2 (0x4U << ADC_SMPR1_SMP17_Pos) /*!< 0x00800000 */
+
+/****************** Bit definition for ADC_SMPR2 register *******************/
+#define ADC_SMPR2_SMP0_Pos (0U)
+#define ADC_SMPR2_SMP0_Msk (0x7U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000007 */
+#define ADC_SMPR2_SMP0 ADC_SMPR2_SMP0_Msk /*!< ADC channel 0 sampling time selection */
+#define ADC_SMPR2_SMP0_0 (0x1U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000001 */
+#define ADC_SMPR2_SMP0_1 (0x2U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000002 */
+#define ADC_SMPR2_SMP0_2 (0x4U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000004 */
+
+#define ADC_SMPR2_SMP1_Pos (3U)
+#define ADC_SMPR2_SMP1_Msk (0x7U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000038 */
+#define ADC_SMPR2_SMP1 ADC_SMPR2_SMP1_Msk /*!< ADC channel 1 sampling time selection */
+#define ADC_SMPR2_SMP1_0 (0x1U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000008 */
+#define ADC_SMPR2_SMP1_1 (0x2U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000010 */
+#define ADC_SMPR2_SMP1_2 (0x4U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000020 */
+
+#define ADC_SMPR2_SMP2_Pos (6U)
+#define ADC_SMPR2_SMP2_Msk (0x7U << ADC_SMPR2_SMP2_Pos) /*!< 0x000001C0 */
+#define ADC_SMPR2_SMP2 ADC_SMPR2_SMP2_Msk /*!< ADC channel 2 sampling time selection */
+#define ADC_SMPR2_SMP2_0 (0x1U << ADC_SMPR2_SMP2_Pos) /*!< 0x00000040 */
+#define ADC_SMPR2_SMP2_1 (0x2U << ADC_SMPR2_SMP2_Pos) /*!< 0x00000080 */
+#define ADC_SMPR2_SMP2_2 (0x4U << ADC_SMPR2_SMP2_Pos) /*!< 0x00000100 */
+
+#define ADC_SMPR2_SMP3_Pos (9U)
+#define ADC_SMPR2_SMP3_Msk (0x7U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000E00 */
+#define ADC_SMPR2_SMP3 ADC_SMPR2_SMP3_Msk /*!< ADC channel 3 sampling time selection */
+#define ADC_SMPR2_SMP3_0 (0x1U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000200 */
+#define ADC_SMPR2_SMP3_1 (0x2U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000400 */
+#define ADC_SMPR2_SMP3_2 (0x4U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000800 */
+
+#define ADC_SMPR2_SMP4_Pos (12U)
+#define ADC_SMPR2_SMP4_Msk (0x7U << ADC_SMPR2_SMP4_Pos) /*!< 0x00007000 */
+#define ADC_SMPR2_SMP4 ADC_SMPR2_SMP4_Msk /*!< ADC channel 4 sampling time selection */
+#define ADC_SMPR2_SMP4_0 (0x1U << ADC_SMPR2_SMP4_Pos) /*!< 0x00001000 */
+#define ADC_SMPR2_SMP4_1 (0x2U << ADC_SMPR2_SMP4_Pos) /*!< 0x00002000 */
+#define ADC_SMPR2_SMP4_2 (0x4U << ADC_SMPR2_SMP4_Pos) /*!< 0x00004000 */
+
+#define ADC_SMPR2_SMP5_Pos (15U)
+#define ADC_SMPR2_SMP5_Msk (0x7U << ADC_SMPR2_SMP5_Pos) /*!< 0x00038000 */
+#define ADC_SMPR2_SMP5 ADC_SMPR2_SMP5_Msk /*!< ADC channel 5 sampling time selection */
+#define ADC_SMPR2_SMP5_0 (0x1U << ADC_SMPR2_SMP5_Pos) /*!< 0x00008000 */
+#define ADC_SMPR2_SMP5_1 (0x2U << ADC_SMPR2_SMP5_Pos) /*!< 0x00010000 */
+#define ADC_SMPR2_SMP5_2 (0x4U << ADC_SMPR2_SMP5_Pos) /*!< 0x00020000 */
+
+#define ADC_SMPR2_SMP6_Pos (18U)
+#define ADC_SMPR2_SMP6_Msk (0x7U << ADC_SMPR2_SMP6_Pos) /*!< 0x001C0000 */
+#define ADC_SMPR2_SMP6 ADC_SMPR2_SMP6_Msk /*!< ADC channel 6 sampling time selection */
+#define ADC_SMPR2_SMP6_0 (0x1U << ADC_SMPR2_SMP6_Pos) /*!< 0x00040000 */
+#define ADC_SMPR2_SMP6_1 (0x2U << ADC_SMPR2_SMP6_Pos) /*!< 0x00080000 */
+#define ADC_SMPR2_SMP6_2 (0x4U << ADC_SMPR2_SMP6_Pos) /*!< 0x00100000 */
+
+#define ADC_SMPR2_SMP7_Pos (21U)
+#define ADC_SMPR2_SMP7_Msk (0x7U << ADC_SMPR2_SMP7_Pos) /*!< 0x00E00000 */
+#define ADC_SMPR2_SMP7 ADC_SMPR2_SMP7_Msk /*!< ADC channel 7 sampling time selection */
+#define ADC_SMPR2_SMP7_0 (0x1U << ADC_SMPR2_SMP7_Pos) /*!< 0x00200000 */
+#define ADC_SMPR2_SMP7_1 (0x2U << ADC_SMPR2_SMP7_Pos) /*!< 0x00400000 */
+#define ADC_SMPR2_SMP7_2 (0x4U << ADC_SMPR2_SMP7_Pos) /*!< 0x00800000 */
+
+#define ADC_SMPR2_SMP8_Pos (24U)
+#define ADC_SMPR2_SMP8_Msk (0x7U << ADC_SMPR2_SMP8_Pos) /*!< 0x07000000 */
+#define ADC_SMPR2_SMP8 ADC_SMPR2_SMP8_Msk /*!< ADC channel 8 sampling time selection */
+#define ADC_SMPR2_SMP8_0 (0x1U << ADC_SMPR2_SMP8_Pos) /*!< 0x01000000 */
+#define ADC_SMPR2_SMP8_1 (0x2U << ADC_SMPR2_SMP8_Pos) /*!< 0x02000000 */
+#define ADC_SMPR2_SMP8_2 (0x4U << ADC_SMPR2_SMP8_Pos) /*!< 0x04000000 */
+
+#define ADC_SMPR2_SMP9_Pos (27U)
+#define ADC_SMPR2_SMP9_Msk (0x7U << ADC_SMPR2_SMP9_Pos) /*!< 0x38000000 */
+#define ADC_SMPR2_SMP9 ADC_SMPR2_SMP9_Msk /*!< ADC channel 9 sampling time selection */
+#define ADC_SMPR2_SMP9_0 (0x1U << ADC_SMPR2_SMP9_Pos) /*!< 0x08000000 */
+#define ADC_SMPR2_SMP9_1 (0x2U << ADC_SMPR2_SMP9_Pos) /*!< 0x10000000 */
+#define ADC_SMPR2_SMP9_2 (0x4U << ADC_SMPR2_SMP9_Pos) /*!< 0x20000000 */
+
+/****************** Bit definition for ADC_JOFR1 register *******************/
+#define ADC_JOFR1_JOFFSET1_Pos (0U)
+#define ADC_JOFR1_JOFFSET1_Msk (0xFFFU << ADC_JOFR1_JOFFSET1_Pos) /*!< 0x00000FFF */
+#define ADC_JOFR1_JOFFSET1 ADC_JOFR1_JOFFSET1_Msk /*!< ADC group injected sequencer rank 1 offset value */
+
+/****************** Bit definition for ADC_JOFR2 register *******************/
+#define ADC_JOFR2_JOFFSET2_Pos (0U)
+#define ADC_JOFR2_JOFFSET2_Msk (0xFFFU << ADC_JOFR2_JOFFSET2_Pos) /*!< 0x00000FFF */
+#define ADC_JOFR2_JOFFSET2 ADC_JOFR2_JOFFSET2_Msk /*!< ADC group injected sequencer rank 2 offset value */
+
+/****************** Bit definition for ADC_JOFR3 register *******************/
+#define ADC_JOFR3_JOFFSET3_Pos (0U)
+#define ADC_JOFR3_JOFFSET3_Msk (0xFFFU << ADC_JOFR3_JOFFSET3_Pos) /*!< 0x00000FFF */
+#define ADC_JOFR3_JOFFSET3 ADC_JOFR3_JOFFSET3_Msk /*!< ADC group injected sequencer rank 3 offset value */
+
+/****************** Bit definition for ADC_JOFR4 register *******************/
+#define ADC_JOFR4_JOFFSET4_Pos (0U)
+#define ADC_JOFR4_JOFFSET4_Msk (0xFFFU << ADC_JOFR4_JOFFSET4_Pos) /*!< 0x00000FFF */
+#define ADC_JOFR4_JOFFSET4 ADC_JOFR4_JOFFSET4_Msk /*!< ADC group injected sequencer rank 4 offset value */
+
+/******************* Bit definition for ADC_HTR register ********************/
+#define ADC_HTR_HT_Pos (0U)
+#define ADC_HTR_HT_Msk (0xFFFU << ADC_HTR_HT_Pos) /*!< 0x00000FFF */
+#define ADC_HTR_HT ADC_HTR_HT_Msk /*!< ADC analog watchdog 1 threshold high */
+
+/******************* Bit definition for ADC_LTR register ********************/
+#define ADC_LTR_LT_Pos (0U)
+#define ADC_LTR_LT_Msk (0xFFFU << ADC_LTR_LT_Pos) /*!< 0x00000FFF */
+#define ADC_LTR_LT ADC_LTR_LT_Msk /*!< ADC analog watchdog 1 threshold low */
+
+/******************* Bit definition for ADC_SQR1 register *******************/
+#define ADC_SQR1_SQ13_Pos (0U)
+#define ADC_SQR1_SQ13_Msk (0x1FU << ADC_SQR1_SQ13_Pos) /*!< 0x0000001F */
+#define ADC_SQR1_SQ13 ADC_SQR1_SQ13_Msk /*!< ADC group regular sequencer rank 13 */
+#define ADC_SQR1_SQ13_0 (0x01U << ADC_SQR1_SQ13_Pos) /*!< 0x00000001 */
+#define ADC_SQR1_SQ13_1 (0x02U << ADC_SQR1_SQ13_Pos) /*!< 0x00000002 */
+#define ADC_SQR1_SQ13_2 (0x04U << ADC_SQR1_SQ13_Pos) /*!< 0x00000004 */
+#define ADC_SQR1_SQ13_3 (0x08U << ADC_SQR1_SQ13_Pos) /*!< 0x00000008 */
+#define ADC_SQR1_SQ13_4 (0x10U << ADC_SQR1_SQ13_Pos) /*!< 0x00000010 */
+
+#define ADC_SQR1_SQ14_Pos (5U)
+#define ADC_SQR1_SQ14_Msk (0x1FU << ADC_SQR1_SQ14_Pos) /*!< 0x000003E0 */
+#define ADC_SQR1_SQ14 ADC_SQR1_SQ14_Msk /*!< ADC group regular sequencer rank 14 */
+#define ADC_SQR1_SQ14_0 (0x01U << ADC_SQR1_SQ14_Pos) /*!< 0x00000020 */
+#define ADC_SQR1_SQ14_1 (0x02U << ADC_SQR1_SQ14_Pos) /*!< 0x00000040 */
+#define ADC_SQR1_SQ14_2 (0x04U << ADC_SQR1_SQ14_Pos) /*!< 0x00000080 */
+#define ADC_SQR1_SQ14_3 (0x08U << ADC_SQR1_SQ14_Pos) /*!< 0x00000100 */
+#define ADC_SQR1_SQ14_4 (0x10U << ADC_SQR1_SQ14_Pos) /*!< 0x00000200 */
+
+#define ADC_SQR1_SQ15_Pos (10U)
+#define ADC_SQR1_SQ15_Msk (0x1FU << ADC_SQR1_SQ15_Pos) /*!< 0x00007C00 */
+#define ADC_SQR1_SQ15 ADC_SQR1_SQ15_Msk /*!< ADC group regular sequencer rank 15 */
+#define ADC_SQR1_SQ15_0 (0x01U << ADC_SQR1_SQ15_Pos) /*!< 0x00000400 */
+#define ADC_SQR1_SQ15_1 (0x02U << ADC_SQR1_SQ15_Pos) /*!< 0x00000800 */
+#define ADC_SQR1_SQ15_2 (0x04U << ADC_SQR1_SQ15_Pos) /*!< 0x00001000 */
+#define ADC_SQR1_SQ15_3 (0x08U << ADC_SQR1_SQ15_Pos) /*!< 0x00002000 */
+#define ADC_SQR1_SQ15_4 (0x10U << ADC_SQR1_SQ15_Pos) /*!< 0x00004000 */
+
+#define ADC_SQR1_SQ16_Pos (15U)
+#define ADC_SQR1_SQ16_Msk (0x1FU << ADC_SQR1_SQ16_Pos) /*!< 0x000F8000 */
+#define ADC_SQR1_SQ16 ADC_SQR1_SQ16_Msk /*!< ADC group regular sequencer rank 16 */
+#define ADC_SQR1_SQ16_0 (0x01U << ADC_SQR1_SQ16_Pos) /*!< 0x00008000 */
+#define ADC_SQR1_SQ16_1 (0x02U << ADC_SQR1_SQ16_Pos) /*!< 0x00010000 */
+#define ADC_SQR1_SQ16_2 (0x04U << ADC_SQR1_SQ16_Pos) /*!< 0x00020000 */
+#define ADC_SQR1_SQ16_3 (0x08U << ADC_SQR1_SQ16_Pos) /*!< 0x00040000 */
+#define ADC_SQR1_SQ16_4 (0x10U << ADC_SQR1_SQ16_Pos) /*!< 0x00080000 */
+
+#define ADC_SQR1_L_Pos (20U)
+#define ADC_SQR1_L_Msk (0xFU << ADC_SQR1_L_Pos) /*!< 0x00F00000 */
+#define ADC_SQR1_L ADC_SQR1_L_Msk /*!< ADC group regular sequencer scan length */
+#define ADC_SQR1_L_0 (0x1U << ADC_SQR1_L_Pos) /*!< 0x00100000 */
+#define ADC_SQR1_L_1 (0x2U << ADC_SQR1_L_Pos) /*!< 0x00200000 */
+#define ADC_SQR1_L_2 (0x4U << ADC_SQR1_L_Pos) /*!< 0x00400000 */
+#define ADC_SQR1_L_3 (0x8U << ADC_SQR1_L_Pos) /*!< 0x00800000 */
+
+/******************* Bit definition for ADC_SQR2 register *******************/
+#define ADC_SQR2_SQ7_Pos (0U)
+#define ADC_SQR2_SQ7_Msk (0x1FU << ADC_SQR2_SQ7_Pos) /*!< 0x0000001F */
+#define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk /*!< ADC group regular sequencer rank 7 */
+#define ADC_SQR2_SQ7_0 (0x01U << ADC_SQR2_SQ7_Pos) /*!< 0x00000001 */
+#define ADC_SQR2_SQ7_1 (0x02U << ADC_SQR2_SQ7_Pos) /*!< 0x00000002 */
+#define ADC_SQR2_SQ7_2 (0x04U << ADC_SQR2_SQ7_Pos) /*!< 0x00000004 */
+#define ADC_SQR2_SQ7_3 (0x08U << ADC_SQR2_SQ7_Pos) /*!< 0x00000008 */
+#define ADC_SQR2_SQ7_4 (0x10U << ADC_SQR2_SQ7_Pos) /*!< 0x00000010 */
+
+#define ADC_SQR2_SQ8_Pos (5U)
+#define ADC_SQR2_SQ8_Msk (0x1FU << ADC_SQR2_SQ8_Pos) /*!< 0x000003E0 */
+#define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk /*!< ADC group regular sequencer rank 8 */
+#define ADC_SQR2_SQ8_0 (0x01U << ADC_SQR2_SQ8_Pos) /*!< 0x00000020 */
+#define ADC_SQR2_SQ8_1 (0x02U << ADC_SQR2_SQ8_Pos) /*!< 0x00000040 */
+#define ADC_SQR2_SQ8_2 (0x04U << ADC_SQR2_SQ8_Pos) /*!< 0x00000080 */
+#define ADC_SQR2_SQ8_3 (0x08U << ADC_SQR2_SQ8_Pos) /*!< 0x00000100 */
+#define ADC_SQR2_SQ8_4 (0x10U << ADC_SQR2_SQ8_Pos) /*!< 0x00000200 */
+
+#define ADC_SQR2_SQ9_Pos (10U)
+#define ADC_SQR2_SQ9_Msk (0x1FU << ADC_SQR2_SQ9_Pos) /*!< 0x00007C00 */
+#define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk /*!< ADC group regular sequencer rank 9 */
+#define ADC_SQR2_SQ9_0 (0x01U << ADC_SQR2_SQ9_Pos) /*!< 0x00000400 */
+#define ADC_SQR2_SQ9_1 (0x02U << ADC_SQR2_SQ9_Pos) /*!< 0x00000800 */
+#define ADC_SQR2_SQ9_2 (0x04U << ADC_SQR2_SQ9_Pos) /*!< 0x00001000 */
+#define ADC_SQR2_SQ9_3 (0x08U << ADC_SQR2_SQ9_Pos) /*!< 0x00002000 */
+#define ADC_SQR2_SQ9_4 (0x10U << ADC_SQR2_SQ9_Pos) /*!< 0x00004000 */
+
+#define ADC_SQR2_SQ10_Pos (15U)
+#define ADC_SQR2_SQ10_Msk (0x1FU << ADC_SQR2_SQ10_Pos) /*!< 0x000F8000 */
+#define ADC_SQR2_SQ10 ADC_SQR2_SQ10_Msk /*!< ADC group regular sequencer rank 10 */
+#define ADC_SQR2_SQ10_0 (0x01U << ADC_SQR2_SQ10_Pos) /*!< 0x00008000 */
+#define ADC_SQR2_SQ10_1 (0x02U << ADC_SQR2_SQ10_Pos) /*!< 0x00010000 */
+#define ADC_SQR2_SQ10_2 (0x04U << ADC_SQR2_SQ10_Pos) /*!< 0x00020000 */
+#define ADC_SQR2_SQ10_3 (0x08U << ADC_SQR2_SQ10_Pos) /*!< 0x00040000 */
+#define ADC_SQR2_SQ10_4 (0x10U << ADC_SQR2_SQ10_Pos) /*!< 0x00080000 */
+
+#define ADC_SQR2_SQ11_Pos (20U)
+#define ADC_SQR2_SQ11_Msk (0x1FU << ADC_SQR2_SQ11_Pos) /*!< 0x01F00000 */
+#define ADC_SQR2_SQ11 ADC_SQR2_SQ11_Msk /*!< ADC group regular sequencer rank 1 */
+#define ADC_SQR2_SQ11_0 (0x01U << ADC_SQR2_SQ11_Pos) /*!< 0x00100000 */
+#define ADC_SQR2_SQ11_1 (0x02U << ADC_SQR2_SQ11_Pos) /*!< 0x00200000 */
+#define ADC_SQR2_SQ11_2 (0x04U << ADC_SQR2_SQ11_Pos) /*!< 0x00400000 */
+#define ADC_SQR2_SQ11_3 (0x08U << ADC_SQR2_SQ11_Pos) /*!< 0x00800000 */
+#define ADC_SQR2_SQ11_4 (0x10U << ADC_SQR2_SQ11_Pos) /*!< 0x01000000 */
+
+#define ADC_SQR2_SQ12_Pos (25U)
+#define ADC_SQR2_SQ12_Msk (0x1FU << ADC_SQR2_SQ12_Pos) /*!< 0x3E000000 */
+#define ADC_SQR2_SQ12 ADC_SQR2_SQ12_Msk /*!< ADC group regular sequencer rank 12 */
+#define ADC_SQR2_SQ12_0 (0x01U << ADC_SQR2_SQ12_Pos) /*!< 0x02000000 */
+#define ADC_SQR2_SQ12_1 (0x02U << ADC_SQR2_SQ12_Pos) /*!< 0x04000000 */
+#define ADC_SQR2_SQ12_2 (0x04U << ADC_SQR2_SQ12_Pos) /*!< 0x08000000 */
+#define ADC_SQR2_SQ12_3 (0x08U << ADC_SQR2_SQ12_Pos) /*!< 0x10000000 */
+#define ADC_SQR2_SQ12_4 (0x10U << ADC_SQR2_SQ12_Pos) /*!< 0x20000000 */
+
+/******************* Bit definition for ADC_SQR3 register *******************/
+#define ADC_SQR3_SQ1_Pos (0U)
+#define ADC_SQR3_SQ1_Msk (0x1FU << ADC_SQR3_SQ1_Pos) /*!< 0x0000001F */
+#define ADC_SQR3_SQ1 ADC_SQR3_SQ1_Msk /*!< ADC group regular sequencer rank 1 */
+#define ADC_SQR3_SQ1_0 (0x01U << ADC_SQR3_SQ1_Pos) /*!< 0x00000001 */
+#define ADC_SQR3_SQ1_1 (0x02U << ADC_SQR3_SQ1_Pos) /*!< 0x00000002 */
+#define ADC_SQR3_SQ1_2 (0x04U << ADC_SQR3_SQ1_Pos) /*!< 0x00000004 */
+#define ADC_SQR3_SQ1_3 (0x08U << ADC_SQR3_SQ1_Pos) /*!< 0x00000008 */
+#define ADC_SQR3_SQ1_4 (0x10U << ADC_SQR3_SQ1_Pos) /*!< 0x00000010 */
+
+#define ADC_SQR3_SQ2_Pos (5U)
+#define ADC_SQR3_SQ2_Msk (0x1FU << ADC_SQR3_SQ2_Pos) /*!< 0x000003E0 */
+#define ADC_SQR3_SQ2 ADC_SQR3_SQ2_Msk /*!< ADC group regular sequencer rank 2 */
+#define ADC_SQR3_SQ2_0 (0x01U << ADC_SQR3_SQ2_Pos) /*!< 0x00000020 */
+#define ADC_SQR3_SQ2_1 (0x02U << ADC_SQR3_SQ2_Pos) /*!< 0x00000040 */
+#define ADC_SQR3_SQ2_2 (0x04U << ADC_SQR3_SQ2_Pos) /*!< 0x00000080 */
+#define ADC_SQR3_SQ2_3 (0x08U << ADC_SQR3_SQ2_Pos) /*!< 0x00000100 */
+#define ADC_SQR3_SQ2_4 (0x10U << ADC_SQR3_SQ2_Pos) /*!< 0x00000200 */
+
+#define ADC_SQR3_SQ3_Pos (10U)
+#define ADC_SQR3_SQ3_Msk (0x1FU << ADC_SQR3_SQ3_Pos) /*!< 0x00007C00 */
+#define ADC_SQR3_SQ3 ADC_SQR3_SQ3_Msk /*!< ADC group regular sequencer rank 3 */
+#define ADC_SQR3_SQ3_0 (0x01U << ADC_SQR3_SQ3_Pos) /*!< 0x00000400 */
+#define ADC_SQR3_SQ3_1 (0x02U << ADC_SQR3_SQ3_Pos) /*!< 0x00000800 */
+#define ADC_SQR3_SQ3_2 (0x04U << ADC_SQR3_SQ3_Pos) /*!< 0x00001000 */
+#define ADC_SQR3_SQ3_3 (0x08U << ADC_SQR3_SQ3_Pos) /*!< 0x00002000 */
+#define ADC_SQR3_SQ3_4 (0x10U << ADC_SQR3_SQ3_Pos) /*!< 0x00004000 */
+
+#define ADC_SQR3_SQ4_Pos (15U)
+#define ADC_SQR3_SQ4_Msk (0x1FU << ADC_SQR3_SQ4_Pos) /*!< 0x000F8000 */
+#define ADC_SQR3_SQ4 ADC_SQR3_SQ4_Msk /*!< ADC group regular sequencer rank 4 */
+#define ADC_SQR3_SQ4_0 (0x01U << ADC_SQR3_SQ4_Pos) /*!< 0x00008000 */
+#define ADC_SQR3_SQ4_1 (0x02U << ADC_SQR3_SQ4_Pos) /*!< 0x00010000 */
+#define ADC_SQR3_SQ4_2 (0x04U << ADC_SQR3_SQ4_Pos) /*!< 0x00020000 */
+#define ADC_SQR3_SQ4_3 (0x08U << ADC_SQR3_SQ4_Pos) /*!< 0x00040000 */
+#define ADC_SQR3_SQ4_4 (0x10U << ADC_SQR3_SQ4_Pos) /*!< 0x00080000 */
+
+#define ADC_SQR3_SQ5_Pos (20U)
+#define ADC_SQR3_SQ5_Msk (0x1FU << ADC_SQR3_SQ5_Pos) /*!< 0x01F00000 */
+#define ADC_SQR3_SQ5 ADC_SQR3_SQ5_Msk /*!< ADC group regular sequencer rank 5 */
+#define ADC_SQR3_SQ5_0 (0x01U << ADC_SQR3_SQ5_Pos) /*!< 0x00100000 */
+#define ADC_SQR3_SQ5_1 (0x02U << ADC_SQR3_SQ5_Pos) /*!< 0x00200000 */
+#define ADC_SQR3_SQ5_2 (0x04U << ADC_SQR3_SQ5_Pos) /*!< 0x00400000 */
+#define ADC_SQR3_SQ5_3 (0x08U << ADC_SQR3_SQ5_Pos) /*!< 0x00800000 */
+#define ADC_SQR3_SQ5_4 (0x10U << ADC_SQR3_SQ5_Pos) /*!< 0x01000000 */
+
+#define ADC_SQR3_SQ6_Pos (25U)
+#define ADC_SQR3_SQ6_Msk (0x1FU << ADC_SQR3_SQ6_Pos) /*!< 0x3E000000 */
+#define ADC_SQR3_SQ6 ADC_SQR3_SQ6_Msk /*!< ADC group regular sequencer rank 6 */
+#define ADC_SQR3_SQ6_0 (0x01U << ADC_SQR3_SQ6_Pos) /*!< 0x02000000 */
+#define ADC_SQR3_SQ6_1 (0x02U << ADC_SQR3_SQ6_Pos) /*!< 0x04000000 */
+#define ADC_SQR3_SQ6_2 (0x04U << ADC_SQR3_SQ6_Pos) /*!< 0x08000000 */
+#define ADC_SQR3_SQ6_3 (0x08U << ADC_SQR3_SQ6_Pos) /*!< 0x10000000 */
+#define ADC_SQR3_SQ6_4 (0x10U << ADC_SQR3_SQ6_Pos) /*!< 0x20000000 */
+
+/******************* Bit definition for ADC_JSQR register *******************/
+#define ADC_JSQR_JSQ1_Pos (0U)
+#define ADC_JSQR_JSQ1_Msk (0x1FU << ADC_JSQR_JSQ1_Pos) /*!< 0x0000001F */
+#define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!< ADC group injected sequencer rank 1 */
+#define ADC_JSQR_JSQ1_0 (0x01U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000001 */
+#define ADC_JSQR_JSQ1_1 (0x02U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000002 */
+#define ADC_JSQR_JSQ1_2 (0x04U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000004 */
+#define ADC_JSQR_JSQ1_3 (0x08U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000008 */
+#define ADC_JSQR_JSQ1_4 (0x10U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000010 */
+
+#define ADC_JSQR_JSQ2_Pos (5U)
+#define ADC_JSQR_JSQ2_Msk (0x1FU << ADC_JSQR_JSQ2_Pos) /*!< 0x000003E0 */
+#define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!< ADC group injected sequencer rank 2 */
+#define ADC_JSQR_JSQ2_0 (0x01U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000020 */
+#define ADC_JSQR_JSQ2_1 (0x02U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000040 */
+#define ADC_JSQR_JSQ2_2 (0x04U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000080 */
+#define ADC_JSQR_JSQ2_3 (0x08U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000100 */
+#define ADC_JSQR_JSQ2_4 (0x10U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000200 */
+
+#define ADC_JSQR_JSQ3_Pos (10U)
+#define ADC_JSQR_JSQ3_Msk (0x1FU << ADC_JSQR_JSQ3_Pos) /*!< 0x00007C00 */
+#define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!< ADC group injected sequencer rank 3 */
+#define ADC_JSQR_JSQ3_0 (0x01U << ADC_JSQR_JSQ3_Pos) /*!< 0x00000400 */
+#define ADC_JSQR_JSQ3_1 (0x02U << ADC_JSQR_JSQ3_Pos) /*!< 0x00000800 */
+#define ADC_JSQR_JSQ3_2 (0x04U << ADC_JSQR_JSQ3_Pos) /*!< 0x00001000 */
+#define ADC_JSQR_JSQ3_3 (0x08U << ADC_JSQR_JSQ3_Pos) /*!< 0x00002000 */
+#define ADC_JSQR_JSQ3_4 (0x10U << ADC_JSQR_JSQ3_Pos) /*!< 0x00004000 */
+
+#define ADC_JSQR_JSQ4_Pos (15U)
+#define ADC_JSQR_JSQ4_Msk (0x1FU << ADC_JSQR_JSQ4_Pos) /*!< 0x000F8000 */
+#define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!< ADC group injected sequencer rank 4 */
+#define ADC_JSQR_JSQ4_0 (0x01U << ADC_JSQR_JSQ4_Pos) /*!< 0x00008000 */
+#define ADC_JSQR_JSQ4_1 (0x02U << ADC_JSQR_JSQ4_Pos) /*!< 0x00010000 */
+#define ADC_JSQR_JSQ4_2 (0x04U << ADC_JSQR_JSQ4_Pos) /*!< 0x00020000 */
+#define ADC_JSQR_JSQ4_3 (0x08U << ADC_JSQR_JSQ4_Pos) /*!< 0x00040000 */
+#define ADC_JSQR_JSQ4_4 (0x10U << ADC_JSQR_JSQ4_Pos) /*!< 0x00080000 */
+
+#define ADC_JSQR_JL_Pos (20U)
+#define ADC_JSQR_JL_Msk (0x3U << ADC_JSQR_JL_Pos) /*!< 0x00300000 */
+#define ADC_JSQR_JL ADC_JSQR_JL_Msk /*!< ADC group injected sequencer scan length */
+#define ADC_JSQR_JL_0 (0x1U << ADC_JSQR_JL_Pos) /*!< 0x00100000 */
+#define ADC_JSQR_JL_1 (0x2U << ADC_JSQR_JL_Pos) /*!< 0x00200000 */
+
+/******************* Bit definition for ADC_JDR1 register *******************/
+#define ADC_JDR1_JDATA_Pos (0U)
+#define ADC_JDR1_JDATA_Msk (0xFFFFU << ADC_JDR1_JDATA_Pos) /*!< 0x0000FFFF */
+#define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!< ADC group injected sequencer rank 1 conversion data */
+
+/******************* Bit definition for ADC_JDR2 register *******************/
+#define ADC_JDR2_JDATA_Pos (0U)
+#define ADC_JDR2_JDATA_Msk (0xFFFFU << ADC_JDR2_JDATA_Pos) /*!< 0x0000FFFF */
+#define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!< ADC group injected sequencer rank 2 conversion data */
+
+/******************* Bit definition for ADC_JDR3 register *******************/
+#define ADC_JDR3_JDATA_Pos (0U)
+#define ADC_JDR3_JDATA_Msk (0xFFFFU << ADC_JDR3_JDATA_Pos) /*!< 0x0000FFFF */
+#define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!< ADC group injected sequencer rank 3 conversion data */
+
+/******************* Bit definition for ADC_JDR4 register *******************/
+#define ADC_JDR4_JDATA_Pos (0U)
+#define ADC_JDR4_JDATA_Msk (0xFFFFU << ADC_JDR4_JDATA_Pos) /*!< 0x0000FFFF */
+#define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!< ADC group injected sequencer rank 4 conversion data */
+
+/******************** Bit definition for ADC_DR register ********************/
+#define ADC_DR_DATA_Pos (0U)
+#define ADC_DR_DATA_Msk (0xFFFFU << ADC_DR_DATA_Pos) /*!< 0x0000FFFF */
+#define ADC_DR_DATA ADC_DR_DATA_Msk /*!< ADC group regular conversion data */
+
+
+/*****************************************************************************/
+/* */
+/* Timers (TIM) */
+/* */
+/*****************************************************************************/
+/******************* Bit definition for TIM_CR1 register *******************/
+#define TIM_CR1_CEN_Pos (0U)
+#define TIM_CR1_CEN_Msk (0x1U << TIM_CR1_CEN_Pos) /*!< 0x00000001 */
+#define TIM_CR1_CEN TIM_CR1_CEN_Msk /*!<Counter enable */
+#define TIM_CR1_UDIS_Pos (1U)
+#define TIM_CR1_UDIS_Msk (0x1U << TIM_CR1_UDIS_Pos) /*!< 0x00000002 */
+#define TIM_CR1_UDIS TIM_CR1_UDIS_Msk /*!<Update disable */
+#define TIM_CR1_URS_Pos (2U)
+#define TIM_CR1_URS_Msk (0x1U << TIM_CR1_URS_Pos) /*!< 0x00000004 */
+#define TIM_CR1_URS TIM_CR1_URS_Msk /*!<Update request source */
+#define TIM_CR1_OPM_Pos (3U)
+#define TIM_CR1_OPM_Msk (0x1U << TIM_CR1_OPM_Pos) /*!< 0x00000008 */
+#define TIM_CR1_OPM TIM_CR1_OPM_Msk /*!<One pulse mode */
+#define TIM_CR1_DIR_Pos (4U)
+#define TIM_CR1_DIR_Msk (0x1U << TIM_CR1_DIR_Pos) /*!< 0x00000010 */
+#define TIM_CR1_DIR TIM_CR1_DIR_Msk /*!<Direction */
+
+#define TIM_CR1_CMS_Pos (5U)
+#define TIM_CR1_CMS_Msk (0x3U << TIM_CR1_CMS_Pos) /*!< 0x00000060 */
+#define TIM_CR1_CMS TIM_CR1_CMS_Msk /*!<CMS[1:0] bits (Center-aligned mode selection) */
+#define TIM_CR1_CMS_0 (0x1U << TIM_CR1_CMS_Pos) /*!< 0x00000020 */
+#define TIM_CR1_CMS_1 (0x2U << TIM_CR1_CMS_Pos) /*!< 0x00000040 */
+
+#define TIM_CR1_ARPE_Pos (7U)
+#define TIM_CR1_ARPE_Msk (0x1U << TIM_CR1_ARPE_Pos) /*!< 0x00000080 */
+#define TIM_CR1_ARPE TIM_CR1_ARPE_Msk /*!<Auto-reload preload enable */
+
+#define TIM_CR1_CKD_Pos (8U)
+#define TIM_CR1_CKD_Msk (0x3U << TIM_CR1_CKD_Pos) /*!< 0x00000300 */
+#define TIM_CR1_CKD TIM_CR1_CKD_Msk /*!<CKD[1:0] bits (clock division) */
+#define TIM_CR1_CKD_0 (0x1U << TIM_CR1_CKD_Pos) /*!< 0x00000100 */
+#define TIM_CR1_CKD_1 (0x2U << TIM_CR1_CKD_Pos) /*!< 0x00000200 */
+
+/******************* Bit definition for TIM_CR2 register *******************/
+#define TIM_CR2_CCPC_Pos (0U)
+#define TIM_CR2_CCPC_Msk (0x1U << TIM_CR2_CCPC_Pos) /*!< 0x00000001 */
+#define TIM_CR2_CCPC TIM_CR2_CCPC_Msk /*!<Capture/Compare Preloaded Control */
+#define TIM_CR2_CCUS_Pos (2U)
+#define TIM_CR2_CCUS_Msk (0x1U << TIM_CR2_CCUS_Pos) /*!< 0x00000004 */
+#define TIM_CR2_CCUS TIM_CR2_CCUS_Msk /*!<Capture/Compare Control Update Selection */
+#define TIM_CR2_CCDS_Pos (3U)
+#define TIM_CR2_CCDS_Msk (0x1U << TIM_CR2_CCDS_Pos) /*!< 0x00000008 */
+#define TIM_CR2_CCDS TIM_CR2_CCDS_Msk /*!<Capture/Compare DMA Selection */
+
+#define TIM_CR2_MMS_Pos (4U)
+#define TIM_CR2_MMS_Msk (0x7U << TIM_CR2_MMS_Pos) /*!< 0x00000070 */
+#define TIM_CR2_MMS TIM_CR2_MMS_Msk /*!<MMS[2:0] bits (Master Mode Selection) */
+#define TIM_CR2_MMS_0 (0x1U << TIM_CR2_MMS_Pos) /*!< 0x00000010 */
+#define TIM_CR2_MMS_1 (0x2U << TIM_CR2_MMS_Pos) /*!< 0x00000020 */
+#define TIM_CR2_MMS_2 (0x4U << TIM_CR2_MMS_Pos) /*!< 0x00000040 */
+
+#define TIM_CR2_TI1S_Pos (7U)
+#define TIM_CR2_TI1S_Msk (0x1U << TIM_CR2_TI1S_Pos) /*!< 0x00000080 */
+#define TIM_CR2_TI1S TIM_CR2_TI1S_Msk /*!<TI1 Selection */
+#define TIM_CR2_OIS1_Pos (8U)
+#define TIM_CR2_OIS1_Msk (0x1U << TIM_CR2_OIS1_Pos) /*!< 0x00000100 */
+#define TIM_CR2_OIS1 TIM_CR2_OIS1_Msk /*!<Output Idle state 1 (OC1 output) */
+#define TIM_CR2_OIS1N_Pos (9U)
+#define TIM_CR2_OIS1N_Msk (0x1U << TIM_CR2_OIS1N_Pos) /*!< 0x00000200 */
+#define TIM_CR2_OIS1N TIM_CR2_OIS1N_Msk /*!<Output Idle state 1 (OC1N output) */
+#define TIM_CR2_OIS2_Pos (10U)
+#define TIM_CR2_OIS2_Msk (0x1U << TIM_CR2_OIS2_Pos) /*!< 0x00000400 */
+#define TIM_CR2_OIS2 TIM_CR2_OIS2_Msk /*!<Output Idle state 2 (OC2 output) */
+#define TIM_CR2_OIS2N_Pos (11U)
+#define TIM_CR2_OIS2N_Msk (0x1U << TIM_CR2_OIS2N_Pos) /*!< 0x00000800 */
+#define TIM_CR2_OIS2N TIM_CR2_OIS2N_Msk /*!<Output Idle state 2 (OC2N output) */
+#define TIM_CR2_OIS3_Pos (12U)
+#define TIM_CR2_OIS3_Msk (0x1U << TIM_CR2_OIS3_Pos) /*!< 0x00001000 */
+#define TIM_CR2_OIS3 TIM_CR2_OIS3_Msk /*!<Output Idle state 3 (OC3 output) */
+#define TIM_CR2_OIS3N_Pos (13U)
+#define TIM_CR2_OIS3N_Msk (0x1U << TIM_CR2_OIS3N_Pos) /*!< 0x00002000 */
+#define TIM_CR2_OIS3N TIM_CR2_OIS3N_Msk /*!<Output Idle state 3 (OC3N output) */
+#define TIM_CR2_OIS4_Pos (14U)
+#define TIM_CR2_OIS4_Msk (0x1U << TIM_CR2_OIS4_Pos) /*!< 0x00004000 */
+#define TIM_CR2_OIS4 TIM_CR2_OIS4_Msk /*!<Output Idle state 4 (OC4 output) */
+
+/******************* Bit definition for TIM_SMCR register ******************/
+#define TIM_SMCR_SMS_Pos (0U)
+#define TIM_SMCR_SMS_Msk (0x7U << TIM_SMCR_SMS_Pos) /*!< 0x00000007 */
+#define TIM_SMCR_SMS TIM_SMCR_SMS_Msk /*!<SMS[2:0] bits (Slave mode selection) */
+#define TIM_SMCR_SMS_0 (0x1U << TIM_SMCR_SMS_Pos) /*!< 0x00000001 */
+#define TIM_SMCR_SMS_1 (0x2U << TIM_SMCR_SMS_Pos) /*!< 0x00000002 */
+#define TIM_SMCR_SMS_2 (0x4U << TIM_SMCR_SMS_Pos) /*!< 0x00000004 */
+
+#define TIM_SMCR_OCCS_Pos (3U)
+#define TIM_SMCR_OCCS_Msk (0x1U << TIM_SMCR_OCCS_Pos) /*!< 0x00000008 */
+#define TIM_SMCR_OCCS TIM_SMCR_OCCS_Msk /*!< OCREF clear selection */
+
+#define TIM_SMCR_TS_Pos (4U)
+#define TIM_SMCR_TS_Msk (0x7U << TIM_SMCR_TS_Pos) /*!< 0x00000070 */
+#define TIM_SMCR_TS TIM_SMCR_TS_Msk /*!<TS[2:0] bits (Trigger selection) */
+#define TIM_SMCR_TS_0 (0x1U << TIM_SMCR_TS_Pos) /*!< 0x00000010 */
+#define TIM_SMCR_TS_1 (0x2U << TIM_SMCR_TS_Pos) /*!< 0x00000020 */
+#define TIM_SMCR_TS_2 (0x4U << TIM_SMCR_TS_Pos) /*!< 0x00000040 */
+
+#define TIM_SMCR_MSM_Pos (7U)
+#define TIM_SMCR_MSM_Msk (0x1U << TIM_SMCR_MSM_Pos) /*!< 0x00000080 */
+#define TIM_SMCR_MSM TIM_SMCR_MSM_Msk /*!<Master/slave mode */
+
+#define TIM_SMCR_ETF_Pos (8U)
+#define TIM_SMCR_ETF_Msk (0xFU << TIM_SMCR_ETF_Pos) /*!< 0x00000F00 */
+#define TIM_SMCR_ETF TIM_SMCR_ETF_Msk /*!<ETF[3:0] bits (External trigger filter) */
+#define TIM_SMCR_ETF_0 (0x1U << TIM_SMCR_ETF_Pos) /*!< 0x00000100 */
+#define TIM_SMCR_ETF_1 (0x2U << TIM_SMCR_ETF_Pos) /*!< 0x00000200 */
+#define TIM_SMCR_ETF_2 (0x4U << TIM_SMCR_ETF_Pos) /*!< 0x00000400 */
+#define TIM_SMCR_ETF_3 (0x8U << TIM_SMCR_ETF_Pos) /*!< 0x00000800 */
+
+#define TIM_SMCR_ETPS_Pos (12U)
+#define TIM_SMCR_ETPS_Msk (0x3U << TIM_SMCR_ETPS_Pos) /*!< 0x00003000 */
+#define TIM_SMCR_ETPS TIM_SMCR_ETPS_Msk /*!<ETPS[1:0] bits (External trigger prescaler) */
+#define TIM_SMCR_ETPS_0 (0x1U << TIM_SMCR_ETPS_Pos) /*!< 0x00001000 */
+#define TIM_SMCR_ETPS_1 (0x2U << TIM_SMCR_ETPS_Pos) /*!< 0x00002000 */
+
+#define TIM_SMCR_ECE_Pos (14U)
+#define TIM_SMCR_ECE_Msk (0x1U << TIM_SMCR_ECE_Pos) /*!< 0x00004000 */
+#define TIM_SMCR_ECE TIM_SMCR_ECE_Msk /*!<External clock enable */
+#define TIM_SMCR_ETP_Pos (15U)
+#define TIM_SMCR_ETP_Msk (0x1U << TIM_SMCR_ETP_Pos) /*!< 0x00008000 */
+#define TIM_SMCR_ETP TIM_SMCR_ETP_Msk /*!<External trigger polarity */
+
+/******************* Bit definition for TIM_DIER register ******************/
+#define TIM_DIER_UIE_Pos (0U)
+#define TIM_DIER_UIE_Msk (0x1U << TIM_DIER_UIE_Pos) /*!< 0x00000001 */
+#define TIM_DIER_UIE TIM_DIER_UIE_Msk /*!<Update interrupt enable */
+#define TIM_DIER_CC1IE_Pos (1U)
+#define TIM_DIER_CC1IE_Msk (0x1U << TIM_DIER_CC1IE_Pos) /*!< 0x00000002 */
+#define TIM_DIER_CC1IE TIM_DIER_CC1IE_Msk /*!<Capture/Compare 1 interrupt enable */
+#define TIM_DIER_CC2IE_Pos (2U)
+#define TIM_DIER_CC2IE_Msk (0x1U << TIM_DIER_CC2IE_Pos) /*!< 0x00000004 */
+#define TIM_DIER_CC2IE TIM_DIER_CC2IE_Msk /*!<Capture/Compare 2 interrupt enable */
+#define TIM_DIER_CC3IE_Pos (3U)
+#define TIM_DIER_CC3IE_Msk (0x1U << TIM_DIER_CC3IE_Pos) /*!< 0x00000008 */
+#define TIM_DIER_CC3IE TIM_DIER_CC3IE_Msk /*!<Capture/Compare 3 interrupt enable */
+#define TIM_DIER_CC4IE_Pos (4U)
+#define TIM_DIER_CC4IE_Msk (0x1U << TIM_DIER_CC4IE_Pos) /*!< 0x00000010 */
+#define TIM_DIER_CC4IE TIM_DIER_CC4IE_Msk /*!<Capture/Compare 4 interrupt enable */
+#define TIM_DIER_COMIE_Pos (5U)
+#define TIM_DIER_COMIE_Msk (0x1U << TIM_DIER_COMIE_Pos) /*!< 0x00000020 */
+#define TIM_DIER_COMIE TIM_DIER_COMIE_Msk /*!<COM interrupt enable */
+#define TIM_DIER_TIE_Pos (6U)
+#define TIM_DIER_TIE_Msk (0x1U << TIM_DIER_TIE_Pos) /*!< 0x00000040 */
+#define TIM_DIER_TIE TIM_DIER_TIE_Msk /*!<Trigger interrupt enable */
+#define TIM_DIER_BIE_Pos (7U)
+#define TIM_DIER_BIE_Msk (0x1U << TIM_DIER_BIE_Pos) /*!< 0x00000080 */
+#define TIM_DIER_BIE TIM_DIER_BIE_Msk /*!<Break interrupt enable */
+#define TIM_DIER_UDE_Pos (8U)
+#define TIM_DIER_UDE_Msk (0x1U << TIM_DIER_UDE_Pos) /*!< 0x00000100 */
+#define TIM_DIER_UDE TIM_DIER_UDE_Msk /*!<Update DMA request enable */
+#define TIM_DIER_CC1DE_Pos (9U)
+#define TIM_DIER_CC1DE_Msk (0x1U << TIM_DIER_CC1DE_Pos) /*!< 0x00000200 */
+#define TIM_DIER_CC1DE TIM_DIER_CC1DE_Msk /*!<Capture/Compare 1 DMA request enable */
+#define TIM_DIER_CC2DE_Pos (10U)
+#define TIM_DIER_CC2DE_Msk (0x1U << TIM_DIER_CC2DE_Pos) /*!< 0x00000400 */
+#define TIM_DIER_CC2DE TIM_DIER_CC2DE_Msk /*!<Capture/Compare 2 DMA request enable */
+#define TIM_DIER_CC3DE_Pos (11U)
+#define TIM_DIER_CC3DE_Msk (0x1U << TIM_DIER_CC3DE_Pos) /*!< 0x00000800 */
+#define TIM_DIER_CC3DE TIM_DIER_CC3DE_Msk /*!<Capture/Compare 3 DMA request enable */
+#define TIM_DIER_CC4DE_Pos (12U)
+#define TIM_DIER_CC4DE_Msk (0x1U << TIM_DIER_CC4DE_Pos) /*!< 0x00001000 */
+#define TIM_DIER_CC4DE TIM_DIER_CC4DE_Msk /*!<Capture/Compare 4 DMA request enable */
+#define TIM_DIER_COMDE_Pos (13U)
+#define TIM_DIER_COMDE_Msk (0x1U << TIM_DIER_COMDE_Pos) /*!< 0x00002000 */
+#define TIM_DIER_COMDE TIM_DIER_COMDE_Msk /*!<COM DMA request enable */
+#define TIM_DIER_TDE_Pos (14U)
+#define TIM_DIER_TDE_Msk (0x1U << TIM_DIER_TDE_Pos) /*!< 0x00004000 */
+#define TIM_DIER_TDE TIM_DIER_TDE_Msk /*!<Trigger DMA request enable */
+
+/******************** Bit definition for TIM_SR register *******************/
+#define TIM_SR_UIF_Pos (0U)
+#define TIM_SR_UIF_Msk (0x1U << TIM_SR_UIF_Pos) /*!< 0x00000001 */
+#define TIM_SR_UIF TIM_SR_UIF_Msk /*!<Update interrupt Flag */
+#define TIM_SR_CC1IF_Pos (1U)
+#define TIM_SR_CC1IF_Msk (0x1U << TIM_SR_CC1IF_Pos) /*!< 0x00000002 */
+#define TIM_SR_CC1IF TIM_SR_CC1IF_Msk /*!<Capture/Compare 1 interrupt Flag */
+#define TIM_SR_CC2IF_Pos (2U)
+#define TIM_SR_CC2IF_Msk (0x1U << TIM_SR_CC2IF_Pos) /*!< 0x00000004 */
+#define TIM_SR_CC2IF TIM_SR_CC2IF_Msk /*!<Capture/Compare 2 interrupt Flag */
+#define TIM_SR_CC3IF_Pos (3U)
+#define TIM_SR_CC3IF_Msk (0x1U << TIM_SR_CC3IF_Pos) /*!< 0x00000008 */
+#define TIM_SR_CC3IF TIM_SR_CC3IF_Msk /*!<Capture/Compare 3 interrupt Flag */
+#define TIM_SR_CC4IF_Pos (4U)
+#define TIM_SR_CC4IF_Msk (0x1U << TIM_SR_CC4IF_Pos) /*!< 0x00000010 */
+#define TIM_SR_CC4IF TIM_SR_CC4IF_Msk /*!<Capture/Compare 4 interrupt Flag */
+#define TIM_SR_COMIF_Pos (5U)
+#define TIM_SR_COMIF_Msk (0x1U << TIM_SR_COMIF_Pos) /*!< 0x00000020 */
+#define TIM_SR_COMIF TIM_SR_COMIF_Msk /*!<COM interrupt Flag */
+#define TIM_SR_TIF_Pos (6U)
+#define TIM_SR_TIF_Msk (0x1U << TIM_SR_TIF_Pos) /*!< 0x00000040 */
+#define TIM_SR_TIF TIM_SR_TIF_Msk /*!<Trigger interrupt Flag */
+#define TIM_SR_BIF_Pos (7U)
+#define TIM_SR_BIF_Msk (0x1U << TIM_SR_BIF_Pos) /*!< 0x00000080 */
+#define TIM_SR_BIF TIM_SR_BIF_Msk /*!<Break interrupt Flag */
+#define TIM_SR_CC1OF_Pos (9U)
+#define TIM_SR_CC1OF_Msk (0x1U << TIM_SR_CC1OF_Pos) /*!< 0x00000200 */
+#define TIM_SR_CC1OF TIM_SR_CC1OF_Msk /*!<Capture/Compare 1 Overcapture Flag */
+#define TIM_SR_CC2OF_Pos (10U)
+#define TIM_SR_CC2OF_Msk (0x1U << TIM_SR_CC2OF_Pos) /*!< 0x00000400 */
+#define TIM_SR_CC2OF TIM_SR_CC2OF_Msk /*!<Capture/Compare 2 Overcapture Flag */
+#define TIM_SR_CC3OF_Pos (11U)
+#define TIM_SR_CC3OF_Msk (0x1U << TIM_SR_CC3OF_Pos) /*!< 0x00000800 */
+#define TIM_SR_CC3OF TIM_SR_CC3OF_Msk /*!<Capture/Compare 3 Overcapture Flag */
+#define TIM_SR_CC4OF_Pos (12U)
+#define TIM_SR_CC4OF_Msk (0x1U << TIM_SR_CC4OF_Pos) /*!< 0x00001000 */
+#define TIM_SR_CC4OF TIM_SR_CC4OF_Msk /*!<Capture/Compare 4 Overcapture Flag */
+
+/******************* Bit definition for TIM_EGR register *******************/
+#define TIM_EGR_UG_Pos (0U)
+#define TIM_EGR_UG_Msk (0x1U << TIM_EGR_UG_Pos) /*!< 0x00000001 */
+#define TIM_EGR_UG TIM_EGR_UG_Msk /*!<Update Generation */
+#define TIM_EGR_CC1G_Pos (1U)
+#define TIM_EGR_CC1G_Msk (0x1U << TIM_EGR_CC1G_Pos) /*!< 0x00000002 */
+#define TIM_EGR_CC1G TIM_EGR_CC1G_Msk /*!<Capture/Compare 1 Generation */
+#define TIM_EGR_CC2G_Pos (2U)
+#define TIM_EGR_CC2G_Msk (0x1U << TIM_EGR_CC2G_Pos) /*!< 0x00000004 */
+#define TIM_EGR_CC2G TIM_EGR_CC2G_Msk /*!<Capture/Compare 2 Generation */
+#define TIM_EGR_CC3G_Pos (3U)
+#define TIM_EGR_CC3G_Msk (0x1U << TIM_EGR_CC3G_Pos) /*!< 0x00000008 */
+#define TIM_EGR_CC3G TIM_EGR_CC3G_Msk /*!<Capture/Compare 3 Generation */
+#define TIM_EGR_CC4G_Pos (4U)
+#define TIM_EGR_CC4G_Msk (0x1U << TIM_EGR_CC4G_Pos) /*!< 0x00000010 */
+#define TIM_EGR_CC4G TIM_EGR_CC4G_Msk /*!<Capture/Compare 4 Generation */
+#define TIM_EGR_COMG_Pos (5U)
+#define TIM_EGR_COMG_Msk (0x1U << TIM_EGR_COMG_Pos) /*!< 0x00000020 */
+#define TIM_EGR_COMG TIM_EGR_COMG_Msk /*!<Capture/Compare Control Update Generation */
+#define TIM_EGR_TG_Pos (6U)
+#define TIM_EGR_TG_Msk (0x1U << TIM_EGR_TG_Pos) /*!< 0x00000040 */
+#define TIM_EGR_TG TIM_EGR_TG_Msk /*!<Trigger Generation */
+#define TIM_EGR_BG_Pos (7U)
+#define TIM_EGR_BG_Msk (0x1U << TIM_EGR_BG_Pos) /*!< 0x00000080 */
+#define TIM_EGR_BG TIM_EGR_BG_Msk /*!<Break Generation */
+
+/****************** Bit definition for TIM_CCMR1 register ******************/
+#define TIM_CCMR1_CC1S_Pos (0U)
+#define TIM_CCMR1_CC1S_Msk (0x3U << TIM_CCMR1_CC1S_Pos) /*!< 0x00000003 */
+#define TIM_CCMR1_CC1S TIM_CCMR1_CC1S_Msk /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
+#define TIM_CCMR1_CC1S_0 (0x1U << TIM_CCMR1_CC1S_Pos) /*!< 0x00000001 */
+#define TIM_CCMR1_CC1S_1 (0x2U << TIM_CCMR1_CC1S_Pos) /*!< 0x00000002 */
+
+#define TIM_CCMR1_OC1FE_Pos (2U)
+#define TIM_CCMR1_OC1FE_Msk (0x1U << TIM_CCMR1_OC1FE_Pos) /*!< 0x00000004 */
+#define TIM_CCMR1_OC1FE TIM_CCMR1_OC1FE_Msk /*!<Output Compare 1 Fast enable */
+#define TIM_CCMR1_OC1PE_Pos (3U)
+#define TIM_CCMR1_OC1PE_Msk (0x1U << TIM_CCMR1_OC1PE_Pos) /*!< 0x00000008 */
+#define TIM_CCMR1_OC1PE TIM_CCMR1_OC1PE_Msk /*!<Output Compare 1 Preload enable */
+
+#define TIM_CCMR1_OC1M_Pos (4U)
+#define TIM_CCMR1_OC1M_Msk (0x7U << TIM_CCMR1_OC1M_Pos) /*!< 0x00000070 */
+#define TIM_CCMR1_OC1M TIM_CCMR1_OC1M_Msk /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
+#define TIM_CCMR1_OC1M_0 (0x1U << TIM_CCMR1_OC1M_Pos) /*!< 0x00000010 */
+#define TIM_CCMR1_OC1M_1 (0x2U << TIM_CCMR1_OC1M_Pos) /*!< 0x00000020 */
+#define TIM_CCMR1_OC1M_2 (0x4U << TIM_CCMR1_OC1M_Pos) /*!< 0x00000040 */
+
+#define TIM_CCMR1_OC1CE_Pos (7U)
+#define TIM_CCMR1_OC1CE_Msk (0x1U << TIM_CCMR1_OC1CE_Pos) /*!< 0x00000080 */
+#define TIM_CCMR1_OC1CE TIM_CCMR1_OC1CE_Msk /*!<Output Compare 1Clear Enable */
+
+#define TIM_CCMR1_CC2S_Pos (8U)
+#define TIM_CCMR1_CC2S_Msk (0x3U << TIM_CCMR1_CC2S_Pos) /*!< 0x00000300 */
+#define TIM_CCMR1_CC2S TIM_CCMR1_CC2S_Msk /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
+#define TIM_CCMR1_CC2S_0 (0x1U << TIM_CCMR1_CC2S_Pos) /*!< 0x00000100 */
+#define TIM_CCMR1_CC2S_1 (0x2U << TIM_CCMR1_CC2S_Pos) /*!< 0x00000200 */
+
+#define TIM_CCMR1_OC2FE_Pos (10U)
+#define TIM_CCMR1_OC2FE_Msk (0x1U << TIM_CCMR1_OC2FE_Pos) /*!< 0x00000400 */
+#define TIM_CCMR1_OC2FE TIM_CCMR1_OC2FE_Msk /*!<Output Compare 2 Fast enable */
+#define TIM_CCMR1_OC2PE_Pos (11U)
+#define TIM_CCMR1_OC2PE_Msk (0x1U << TIM_CCMR1_OC2PE_Pos) /*!< 0x00000800 */
+#define TIM_CCMR1_OC2PE TIM_CCMR1_OC2PE_Msk /*!<Output Compare 2 Preload enable */
+
+#define TIM_CCMR1_OC2M_Pos (12U)
+#define TIM_CCMR1_OC2M_Msk (0x7U << TIM_CCMR1_OC2M_Pos) /*!< 0x00007000 */
+#define TIM_CCMR1_OC2M TIM_CCMR1_OC2M_Msk /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
+#define TIM_CCMR1_OC2M_0 (0x1U << TIM_CCMR1_OC2M_Pos) /*!< 0x00001000 */
+#define TIM_CCMR1_OC2M_1 (0x2U << TIM_CCMR1_OC2M_Pos) /*!< 0x00002000 */
+#define TIM_CCMR1_OC2M_2 (0x4U << TIM_CCMR1_OC2M_Pos) /*!< 0x00004000 */
+
+#define TIM_CCMR1_OC2CE_Pos (15U)
+#define TIM_CCMR1_OC2CE_Msk (0x1U << TIM_CCMR1_OC2CE_Pos) /*!< 0x00008000 */
+#define TIM_CCMR1_OC2CE TIM_CCMR1_OC2CE_Msk /*!<Output Compare 2 Clear Enable */
+
+/*---------------------------------------------------------------------------*/
+
+#define TIM_CCMR1_IC1PSC_Pos (2U)
+#define TIM_CCMR1_IC1PSC_Msk (0x3U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x0000000C */
+#define TIM_CCMR1_IC1PSC TIM_CCMR1_IC1PSC_Msk /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
+#define TIM_CCMR1_IC1PSC_0 (0x1U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x00000004 */
+#define TIM_CCMR1_IC1PSC_1 (0x2U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x00000008 */
+
+#define TIM_CCMR1_IC1F_Pos (4U)
+#define TIM_CCMR1_IC1F_Msk (0xFU << TIM_CCMR1_IC1F_Pos) /*!< 0x000000F0 */
+#define TIM_CCMR1_IC1F TIM_CCMR1_IC1F_Msk /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
+#define TIM_CCMR1_IC1F_0 (0x1U << TIM_CCMR1_IC1F_Pos) /*!< 0x00000010 */
+#define TIM_CCMR1_IC1F_1 (0x2U << TIM_CCMR1_IC1F_Pos) /*!< 0x00000020 */
+#define TIM_CCMR1_IC1F_2 (0x4U << TIM_CCMR1_IC1F_Pos) /*!< 0x00000040 */
+#define TIM_CCMR1_IC1F_3 (0x8U << TIM_CCMR1_IC1F_Pos) /*!< 0x00000080 */
+
+#define TIM_CCMR1_IC2PSC_Pos (10U)
+#define TIM_CCMR1_IC2PSC_Msk (0x3U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000C00 */
+#define TIM_CCMR1_IC2PSC TIM_CCMR1_IC2PSC_Msk /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
+#define TIM_CCMR1_IC2PSC_0 (0x1U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000400 */
+#define TIM_CCMR1_IC2PSC_1 (0x2U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000800 */
+
+#define TIM_CCMR1_IC2F_Pos (12U)
+#define TIM_CCMR1_IC2F_Msk (0xFU << TIM_CCMR1_IC2F_Pos) /*!< 0x0000F000 */
+#define TIM_CCMR1_IC2F TIM_CCMR1_IC2F_Msk /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
+#define TIM_CCMR1_IC2F_0 (0x1U << TIM_CCMR1_IC2F_Pos) /*!< 0x00001000 */
+#define TIM_CCMR1_IC2F_1 (0x2U << TIM_CCMR1_IC2F_Pos) /*!< 0x00002000 */
+#define TIM_CCMR1_IC2F_2 (0x4U << TIM_CCMR1_IC2F_Pos) /*!< 0x00004000 */
+#define TIM_CCMR1_IC2F_3 (0x8U << TIM_CCMR1_IC2F_Pos) /*!< 0x00008000 */
+
+/****************** Bit definition for TIM_CCMR2 register ******************/
+#define TIM_CCMR2_CC3S_Pos (0U)
+#define TIM_CCMR2_CC3S_Msk (0x3U << TIM_CCMR2_CC3S_Pos) /*!< 0x00000003 */
+#define TIM_CCMR2_CC3S TIM_CCMR2_CC3S_Msk /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
+#define TIM_CCMR2_CC3S_0 (0x1U << TIM_CCMR2_CC3S_Pos) /*!< 0x00000001 */
+#define TIM_CCMR2_CC3S_1 (0x2U << TIM_CCMR2_CC3S_Pos) /*!< 0x00000002 */
+
+#define TIM_CCMR2_OC3FE_Pos (2U)
+#define TIM_CCMR2_OC3FE_Msk (0x1U << TIM_CCMR2_OC3FE_Pos) /*!< 0x00000004 */
+#define TIM_CCMR2_OC3FE TIM_CCMR2_OC3FE_Msk /*!<Output Compare 3 Fast enable */
+#define TIM_CCMR2_OC3PE_Pos (3U)
+#define TIM_CCMR2_OC3PE_Msk (0x1U << TIM_CCMR2_OC3PE_Pos) /*!< 0x00000008 */
+#define TIM_CCMR2_OC3PE TIM_CCMR2_OC3PE_Msk /*!<Output Compare 3 Preload enable */
+
+#define TIM_CCMR2_OC3M_Pos (4U)
+#define TIM_CCMR2_OC3M_Msk (0x7U << TIM_CCMR2_OC3M_Pos) /*!< 0x00000070 */
+#define TIM_CCMR2_OC3M TIM_CCMR2_OC3M_Msk /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
+#define TIM_CCMR2_OC3M_0 (0x1U << TIM_CCMR2_OC3M_Pos) /*!< 0x00000010 */
+#define TIM_CCMR2_OC3M_1 (0x2U << TIM_CCMR2_OC3M_Pos) /*!< 0x00000020 */
+#define TIM_CCMR2_OC3M_2 (0x4U << TIM_CCMR2_OC3M_Pos) /*!< 0x00000040 */
+
+#define TIM_CCMR2_OC3CE_Pos (7U)
+#define TIM_CCMR2_OC3CE_Msk (0x1U << TIM_CCMR2_OC3CE_Pos) /*!< 0x00000080 */
+#define TIM_CCMR2_OC3CE TIM_CCMR2_OC3CE_Msk /*!<Output Compare 3 Clear Enable */
+
+#define TIM_CCMR2_CC4S_Pos (8U)
+#define TIM_CCMR2_CC4S_Msk (0x3U << TIM_CCMR2_CC4S_Pos) /*!< 0x00000300 */
+#define TIM_CCMR2_CC4S TIM_CCMR2_CC4S_Msk /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
+#define TIM_CCMR2_CC4S_0 (0x1U << TIM_CCMR2_CC4S_Pos) /*!< 0x00000100 */
+#define TIM_CCMR2_CC4S_1 (0x2U << TIM_CCMR2_CC4S_Pos) /*!< 0x00000200 */
+
+#define TIM_CCMR2_OC4FE_Pos (10U)
+#define TIM_CCMR2_OC4FE_Msk (0x1U << TIM_CCMR2_OC4FE_Pos) /*!< 0x00000400 */
+#define TIM_CCMR2_OC4FE TIM_CCMR2_OC4FE_Msk /*!<Output Compare 4 Fast enable */
+#define TIM_CCMR2_OC4PE_Pos (11U)
+#define TIM_CCMR2_OC4PE_Msk (0x1U << TIM_CCMR2_OC4PE_Pos) /*!< 0x00000800 */
+#define TIM_CCMR2_OC4PE TIM_CCMR2_OC4PE_Msk /*!<Output Compare 4 Preload enable */
+
+#define TIM_CCMR2_OC4M_Pos (12U)
+#define TIM_CCMR2_OC4M_Msk (0x7U << TIM_CCMR2_OC4M_Pos) /*!< 0x00007000 */
+#define TIM_CCMR2_OC4M TIM_CCMR2_OC4M_Msk /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
+#define TIM_CCMR2_OC4M_0 (0x1U << TIM_CCMR2_OC4M_Pos) /*!< 0x00001000 */
+#define TIM_CCMR2_OC4M_1 (0x2U << TIM_CCMR2_OC4M_Pos) /*!< 0x00002000 */
+#define TIM_CCMR2_OC4M_2 (0x4U << TIM_CCMR2_OC4M_Pos) /*!< 0x00004000 */
+
+#define TIM_CCMR2_OC4CE_Pos (15U)
+#define TIM_CCMR2_OC4CE_Msk (0x1U << TIM_CCMR2_OC4CE_Pos) /*!< 0x00008000 */
+#define TIM_CCMR2_OC4CE TIM_CCMR2_OC4CE_Msk /*!<Output Compare 4 Clear Enable */
+
+/*---------------------------------------------------------------------------*/
+
+#define TIM_CCMR2_IC3PSC_Pos (2U)
+#define TIM_CCMR2_IC3PSC_Msk (0x3U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x0000000C */
+#define TIM_CCMR2_IC3PSC TIM_CCMR2_IC3PSC_Msk /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
+#define TIM_CCMR2_IC3PSC_0 (0x1U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x00000004 */
+#define TIM_CCMR2_IC3PSC_1 (0x2U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x00000008 */
+
+#define TIM_CCMR2_IC3F_Pos (4U)
+#define TIM_CCMR2_IC3F_Msk (0xFU << TIM_CCMR2_IC3F_Pos) /*!< 0x000000F0 */
+#define TIM_CCMR2_IC3F TIM_CCMR2_IC3F_Msk /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
+#define TIM_CCMR2_IC3F_0 (0x1U << TIM_CCMR2_IC3F_Pos) /*!< 0x00000010 */
+#define TIM_CCMR2_IC3F_1 (0x2U << TIM_CCMR2_IC3F_Pos) /*!< 0x00000020 */
+#define TIM_CCMR2_IC3F_2 (0x4U << TIM_CCMR2_IC3F_Pos) /*!< 0x00000040 */
+#define TIM_CCMR2_IC3F_3 (0x8U << TIM_CCMR2_IC3F_Pos) /*!< 0x00000080 */
+
+#define TIM_CCMR2_IC4PSC_Pos (10U)
+#define TIM_CCMR2_IC4PSC_Msk (0x3U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000C00 */
+#define TIM_CCMR2_IC4PSC TIM_CCMR2_IC4PSC_Msk /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
+#define TIM_CCMR2_IC4PSC_0 (0x1U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000400 */
+#define TIM_CCMR2_IC4PSC_1 (0x2U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000800 */
+
+#define TIM_CCMR2_IC4F_Pos (12U)
+#define TIM_CCMR2_IC4F_Msk (0xFU << TIM_CCMR2_IC4F_Pos) /*!< 0x0000F000 */
+#define TIM_CCMR2_IC4F TIM_CCMR2_IC4F_Msk /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
+#define TIM_CCMR2_IC4F_0 (0x1U << TIM_CCMR2_IC4F_Pos) /*!< 0x00001000 */
+#define TIM_CCMR2_IC4F_1 (0x2U << TIM_CCMR2_IC4F_Pos) /*!< 0x00002000 */
+#define TIM_CCMR2_IC4F_2 (0x4U << TIM_CCMR2_IC4F_Pos) /*!< 0x00004000 */
+#define TIM_CCMR2_IC4F_3 (0x8U << TIM_CCMR2_IC4F_Pos) /*!< 0x00008000 */
+
+/******************* Bit definition for TIM_CCER register ******************/
+#define TIM_CCER_CC1E_Pos (0U)
+#define TIM_CCER_CC1E_Msk (0x1U << TIM_CCER_CC1E_Pos) /*!< 0x00000001 */
+#define TIM_CCER_CC1E TIM_CCER_CC1E_Msk /*!<Capture/Compare 1 output enable */
+#define TIM_CCER_CC1P_Pos (1U)
+#define TIM_CCER_CC1P_Msk (0x1U << TIM_CCER_CC1P_Pos) /*!< 0x00000002 */
+#define TIM_CCER_CC1P TIM_CCER_CC1P_Msk /*!<Capture/Compare 1 output Polarity */
+#define TIM_CCER_CC1NE_Pos (2U)
+#define TIM_CCER_CC1NE_Msk (0x1U << TIM_CCER_CC1NE_Pos) /*!< 0x00000004 */
+#define TIM_CCER_CC1NE TIM_CCER_CC1NE_Msk /*!<Capture/Compare 1 Complementary output enable */
+#define TIM_CCER_CC1NP_Pos (3U)
+#define TIM_CCER_CC1NP_Msk (0x1U << TIM_CCER_CC1NP_Pos) /*!< 0x00000008 */
+#define TIM_CCER_CC1NP TIM_CCER_CC1NP_Msk /*!<Capture/Compare 1 Complementary output Polarity */
+#define TIM_CCER_CC2E_Pos (4U)
+#define TIM_CCER_CC2E_Msk (0x1U << TIM_CCER_CC2E_Pos) /*!< 0x00000010 */
+#define TIM_CCER_CC2E TIM_CCER_CC2E_Msk /*!<Capture/Compare 2 output enable */
+#define TIM_CCER_CC2P_Pos (5U)
+#define TIM_CCER_CC2P_Msk (0x1U << TIM_CCER_CC2P_Pos) /*!< 0x00000020 */
+#define TIM_CCER_CC2P TIM_CCER_CC2P_Msk /*!<Capture/Compare 2 output Polarity */
+#define TIM_CCER_CC2NE_Pos (6U)
+#define TIM_CCER_CC2NE_Msk (0x1U << TIM_CCER_CC2NE_Pos) /*!< 0x00000040 */
+#define TIM_CCER_CC2NE TIM_CCER_CC2NE_Msk /*!<Capture/Compare 2 Complementary output enable */
+#define TIM_CCER_CC2NP_Pos (7U)
+#define TIM_CCER_CC2NP_Msk (0x1U << TIM_CCER_CC2NP_Pos) /*!< 0x00000080 */
+#define TIM_CCER_CC2NP TIM_CCER_CC2NP_Msk /*!<Capture/Compare 2 Complementary output Polarity */
+#define TIM_CCER_CC3E_Pos (8U)
+#define TIM_CCER_CC3E_Msk (0x1U << TIM_CCER_CC3E_Pos) /*!< 0x00000100 */
+#define TIM_CCER_CC3E TIM_CCER_CC3E_Msk /*!<Capture/Compare 3 output enable */
+#define TIM_CCER_CC3P_Pos (9U)
+#define TIM_CCER_CC3P_Msk (0x1U << TIM_CCER_CC3P_Pos) /*!< 0x00000200 */
+#define TIM_CCER_CC3P TIM_CCER_CC3P_Msk /*!<Capture/Compare 3 output Polarity */
+#define TIM_CCER_CC3NE_Pos (10U)
+#define TIM_CCER_CC3NE_Msk (0x1U << TIM_CCER_CC3NE_Pos) /*!< 0x00000400 */
+#define TIM_CCER_CC3NE TIM_CCER_CC3NE_Msk /*!<Capture/Compare 3 Complementary output enable */
+#define TIM_CCER_CC3NP_Pos (11U)
+#define TIM_CCER_CC3NP_Msk (0x1U << TIM_CCER_CC3NP_Pos) /*!< 0x00000800 */
+#define TIM_CCER_CC3NP TIM_CCER_CC3NP_Msk /*!<Capture/Compare 3 Complementary output Polarity */
+#define TIM_CCER_CC4E_Pos (12U)
+#define TIM_CCER_CC4E_Msk (0x1U << TIM_CCER_CC4E_Pos) /*!< 0x00001000 */
+#define TIM_CCER_CC4E TIM_CCER_CC4E_Msk /*!<Capture/Compare 4 output enable */
+#define TIM_CCER_CC4P_Pos (13U)
+#define TIM_CCER_CC4P_Msk (0x1U << TIM_CCER_CC4P_Pos) /*!< 0x00002000 */
+#define TIM_CCER_CC4P TIM_CCER_CC4P_Msk /*!<Capture/Compare 4 output Polarity */
+#define TIM_CCER_CC4NP_Pos (15U)
+#define TIM_CCER_CC4NP_Msk (0x1U << TIM_CCER_CC4NP_Pos) /*!< 0x00008000 */
+#define TIM_CCER_CC4NP TIM_CCER_CC4NP_Msk /*!<Capture/Compare 4 Complementary output Polarity */
+
+/******************* Bit definition for TIM_CNT register *******************/
+#define TIM_CNT_CNT_Pos (0U)
+#define TIM_CNT_CNT_Msk (0xFFFFFFFFU << TIM_CNT_CNT_Pos) /*!< 0xFFFFFFFF */
+#define TIM_CNT_CNT TIM_CNT_CNT_Msk /*!<Counter Value */
+
+/******************* Bit definition for TIM_PSC register *******************/
+#define TIM_PSC_PSC_Pos (0U)
+#define TIM_PSC_PSC_Msk (0xFFFFU << TIM_PSC_PSC_Pos) /*!< 0x0000FFFF */
+#define TIM_PSC_PSC TIM_PSC_PSC_Msk /*!<Prescaler Value */
+
+/******************* Bit definition for TIM_ARR register *******************/
+#define TIM_ARR_ARR_Pos (0U)
+#define TIM_ARR_ARR_Msk (0xFFFFFFFFU << TIM_ARR_ARR_Pos) /*!< 0xFFFFFFFF */
+#define TIM_ARR_ARR TIM_ARR_ARR_Msk /*!<actual auto-reload Value */
+
+/******************* Bit definition for TIM_RCR register *******************/
+#define TIM_RCR_REP_Pos (0U)
+#define TIM_RCR_REP_Msk (0xFFU << TIM_RCR_REP_Pos) /*!< 0x000000FF */
+#define TIM_RCR_REP TIM_RCR_REP_Msk /*!<Repetition Counter Value */
+
+/******************* Bit definition for TIM_CCR1 register ******************/
+#define TIM_CCR1_CCR1_Pos (0U)
+#define TIM_CCR1_CCR1_Msk (0xFFFFU << TIM_CCR1_CCR1_Pos) /*!< 0x0000FFFF */
+#define TIM_CCR1_CCR1 TIM_CCR1_CCR1_Msk /*!<Capture/Compare 1 Value */
+
+/******************* Bit definition for TIM_CCR2 register ******************/
+#define TIM_CCR2_CCR2_Pos (0U)
+#define TIM_CCR2_CCR2_Msk (0xFFFFU << TIM_CCR2_CCR2_Pos) /*!< 0x0000FFFF */
+#define TIM_CCR2_CCR2 TIM_CCR2_CCR2_Msk /*!<Capture/Compare 2 Value */
+
+/******************* Bit definition for TIM_CCR3 register ******************/
+#define TIM_CCR3_CCR3_Pos (0U)
+#define TIM_CCR3_CCR3_Msk (0xFFFFU << TIM_CCR3_CCR3_Pos) /*!< 0x0000FFFF */
+#define TIM_CCR3_CCR3 TIM_CCR3_CCR3_Msk /*!<Capture/Compare 3 Value */
+
+/******************* Bit definition for TIM_CCR4 register ******************/
+#define TIM_CCR4_CCR4_Pos (0U)
+#define TIM_CCR4_CCR4_Msk (0xFFFFU << TIM_CCR4_CCR4_Pos) /*!< 0x0000FFFF */
+#define TIM_CCR4_CCR4 TIM_CCR4_CCR4_Msk /*!<Capture/Compare 4 Value */
+
+/******************* Bit definition for TIM_BDTR register ******************/
+#define TIM_BDTR_DTG_Pos (0U)
+#define TIM_BDTR_DTG_Msk (0xFFU << TIM_BDTR_DTG_Pos) /*!< 0x000000FF */
+#define TIM_BDTR_DTG TIM_BDTR_DTG_Msk /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
+#define TIM_BDTR_DTG_0 (0x01U << TIM_BDTR_DTG_Pos) /*!< 0x00000001 */
+#define TIM_BDTR_DTG_1 (0x02U << TIM_BDTR_DTG_Pos) /*!< 0x00000002 */
+#define TIM_BDTR_DTG_2 (0x04U << TIM_BDTR_DTG_Pos) /*!< 0x00000004 */
+#define TIM_BDTR_DTG_3 (0x08U << TIM_BDTR_DTG_Pos) /*!< 0x00000008 */
+#define TIM_BDTR_DTG_4 (0x10U << TIM_BDTR_DTG_Pos) /*!< 0x00000010 */
+#define TIM_BDTR_DTG_5 (0x20U << TIM_BDTR_DTG_Pos) /*!< 0x00000020 */
+#define TIM_BDTR_DTG_6 (0x40U << TIM_BDTR_DTG_Pos) /*!< 0x00000040 */
+#define TIM_BDTR_DTG_7 (0x80U << TIM_BDTR_DTG_Pos) /*!< 0x00000080 */
+
+#define TIM_BDTR_LOCK_Pos (8U)
+#define TIM_BDTR_LOCK_Msk (0x3U << TIM_BDTR_LOCK_Pos) /*!< 0x00000300 */
+#define TIM_BDTR_LOCK TIM_BDTR_LOCK_Msk /*!<LOCK[1:0] bits (Lock Configuration) */
+#define TIM_BDTR_LOCK_0 (0x1U << TIM_BDTR_LOCK_Pos) /*!< 0x00000100 */
+#define TIM_BDTR_LOCK_1 (0x2U << TIM_BDTR_LOCK_Pos) /*!< 0x00000200 */
+
+#define TIM_BDTR_OSSI_Pos (10U)
+#define TIM_BDTR_OSSI_Msk (0x1U << TIM_BDTR_OSSI_Pos) /*!< 0x00000400 */
+#define TIM_BDTR_OSSI TIM_BDTR_OSSI_Msk /*!<Off-State Selection for Idle mode */
+#define TIM_BDTR_OSSR_Pos (11U)
+#define TIM_BDTR_OSSR_Msk (0x1U << TIM_BDTR_OSSR_Pos) /*!< 0x00000800 */
+#define TIM_BDTR_OSSR TIM_BDTR_OSSR_Msk /*!<Off-State Selection for Run mode */
+#define TIM_BDTR_BKE_Pos (12U)
+#define TIM_BDTR_BKE_Msk (0x1U << TIM_BDTR_BKE_Pos) /*!< 0x00001000 */
+#define TIM_BDTR_BKE TIM_BDTR_BKE_Msk /*!<Break enable */
+#define TIM_BDTR_BKP_Pos (13U)
+#define TIM_BDTR_BKP_Msk (0x1U << TIM_BDTR_BKP_Pos) /*!< 0x00002000 */
+#define TIM_BDTR_BKP TIM_BDTR_BKP_Msk /*!<Break Polarity */
+#define TIM_BDTR_AOE_Pos (14U)
+#define TIM_BDTR_AOE_Msk (0x1U << TIM_BDTR_AOE_Pos) /*!< 0x00004000 */
+#define TIM_BDTR_AOE TIM_BDTR_AOE_Msk /*!<Automatic Output enable */
+#define TIM_BDTR_MOE_Pos (15U)
+#define TIM_BDTR_MOE_Msk (0x1U << TIM_BDTR_MOE_Pos) /*!< 0x00008000 */
+#define TIM_BDTR_MOE TIM_BDTR_MOE_Msk /*!<Main Output enable */
+
+/******************* Bit definition for TIM_DCR register *******************/
+#define TIM_DCR_DBA_Pos (0U)
+#define TIM_DCR_DBA_Msk (0x1FU << TIM_DCR_DBA_Pos) /*!< 0x0000001F */
+#define TIM_DCR_DBA TIM_DCR_DBA_Msk /*!<DBA[4:0] bits (DMA Base Address) */
+#define TIM_DCR_DBA_0 (0x01U << TIM_DCR_DBA_Pos) /*!< 0x00000001 */
+#define TIM_DCR_DBA_1 (0x02U << TIM_DCR_DBA_Pos) /*!< 0x00000002 */
+#define TIM_DCR_DBA_2 (0x04U << TIM_DCR_DBA_Pos) /*!< 0x00000004 */
+#define TIM_DCR_DBA_3 (0x08U << TIM_DCR_DBA_Pos) /*!< 0x00000008 */
+#define TIM_DCR_DBA_4 (0x10U << TIM_DCR_DBA_Pos) /*!< 0x00000010 */
+
+#define TIM_DCR_DBL_Pos (8U)
+#define TIM_DCR_DBL_Msk (0x1FU << TIM_DCR_DBL_Pos) /*!< 0x00001F00 */
+#define TIM_DCR_DBL TIM_DCR_DBL_Msk /*!<DBL[4:0] bits (DMA Burst Length) */
+#define TIM_DCR_DBL_0 (0x01U << TIM_DCR_DBL_Pos) /*!< 0x00000100 */
+#define TIM_DCR_DBL_1 (0x02U << TIM_DCR_DBL_Pos) /*!< 0x00000200 */
+#define TIM_DCR_DBL_2 (0x04U << TIM_DCR_DBL_Pos) /*!< 0x00000400 */
+#define TIM_DCR_DBL_3 (0x08U << TIM_DCR_DBL_Pos) /*!< 0x00000800 */
+#define TIM_DCR_DBL_4 (0x10U << TIM_DCR_DBL_Pos) /*!< 0x00001000 */
+
+/******************* Bit definition for TIM_DMAR register ******************/
+#define TIM_DMAR_DMAB_Pos (0U)
+#define TIM_DMAR_DMAB_Msk (0xFFFFU << TIM_DMAR_DMAB_Pos) /*!< 0x0000FFFF */
+#define TIM_DMAR_DMAB TIM_DMAR_DMAB_Msk /*!<DMA register for burst accesses */
+
+/******************* Bit definition for TIM_OR register ********************/
+
+/******************************************************************************/
+/* */
+/* Real-Time Clock */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for RTC_CRH register ********************/
+#define RTC_CRH_SECIE_Pos (0U)
+#define RTC_CRH_SECIE_Msk (0x1U << RTC_CRH_SECIE_Pos) /*!< 0x00000001 */
+#define RTC_CRH_SECIE RTC_CRH_SECIE_Msk /*!< Second Interrupt Enable */
+#define RTC_CRH_ALRIE_Pos (1U)
+#define RTC_CRH_ALRIE_Msk (0x1U << RTC_CRH_ALRIE_Pos) /*!< 0x00000002 */
+#define RTC_CRH_ALRIE RTC_CRH_ALRIE_Msk /*!< Alarm Interrupt Enable */
+#define RTC_CRH_OWIE_Pos (2U)
+#define RTC_CRH_OWIE_Msk (0x1U << RTC_CRH_OWIE_Pos) /*!< 0x00000004 */
+#define RTC_CRH_OWIE RTC_CRH_OWIE_Msk /*!< OverfloW Interrupt Enable */
+
+/******************* Bit definition for RTC_CRL register ********************/
+#define RTC_CRL_SECF_Pos (0U)
+#define RTC_CRL_SECF_Msk (0x1U << RTC_CRL_SECF_Pos) /*!< 0x00000001 */
+#define RTC_CRL_SECF RTC_CRL_SECF_Msk /*!< Second Flag */
+#define RTC_CRL_ALRF_Pos (1U)
+#define RTC_CRL_ALRF_Msk (0x1U << RTC_CRL_ALRF_Pos) /*!< 0x00000002 */
+#define RTC_CRL_ALRF RTC_CRL_ALRF_Msk /*!< Alarm Flag */
+#define RTC_CRL_OWF_Pos (2U)
+#define RTC_CRL_OWF_Msk (0x1U << RTC_CRL_OWF_Pos) /*!< 0x00000004 */
+#define RTC_CRL_OWF RTC_CRL_OWF_Msk /*!< OverfloW Flag */
+#define RTC_CRL_RSF_Pos (3U)
+#define RTC_CRL_RSF_Msk (0x1U << RTC_CRL_RSF_Pos) /*!< 0x00000008 */
+#define RTC_CRL_RSF RTC_CRL_RSF_Msk /*!< Registers Synchronized Flag */
+#define RTC_CRL_CNF_Pos (4U)
+#define RTC_CRL_CNF_Msk (0x1U << RTC_CRL_CNF_Pos) /*!< 0x00000010 */
+#define RTC_CRL_CNF RTC_CRL_CNF_Msk /*!< Configuration Flag */
+#define RTC_CRL_RTOFF_Pos (5U)
+#define RTC_CRL_RTOFF_Msk (0x1U << RTC_CRL_RTOFF_Pos) /*!< 0x00000020 */
+#define RTC_CRL_RTOFF RTC_CRL_RTOFF_Msk /*!< RTC operation OFF */
+
+/******************* Bit definition for RTC_PRLH register *******************/
+#define RTC_PRLH_PRL_Pos (0U)
+#define RTC_PRLH_PRL_Msk (0xFU << RTC_PRLH_PRL_Pos) /*!< 0x0000000F */
+#define RTC_PRLH_PRL RTC_PRLH_PRL_Msk /*!< RTC Prescaler Reload Value High */
+
+/******************* Bit definition for RTC_PRLL register *******************/
+#define RTC_PRLL_PRL_Pos (0U)
+#define RTC_PRLL_PRL_Msk (0xFFFFU << RTC_PRLL_PRL_Pos) /*!< 0x0000FFFF */
+#define RTC_PRLL_PRL RTC_PRLL_PRL_Msk /*!< RTC Prescaler Reload Value Low */
+
+/******************* Bit definition for RTC_DIVH register *******************/
+#define RTC_DIVH_RTC_DIV_Pos (0U)
+#define RTC_DIVH_RTC_DIV_Msk (0xFU << RTC_DIVH_RTC_DIV_Pos) /*!< 0x0000000F */
+#define RTC_DIVH_RTC_DIV RTC_DIVH_RTC_DIV_Msk /*!< RTC Clock Divider High */
+
+/******************* Bit definition for RTC_DIVL register *******************/
+#define RTC_DIVL_RTC_DIV_Pos (0U)
+#define RTC_DIVL_RTC_DIV_Msk (0xFFFFU << RTC_DIVL_RTC_DIV_Pos) /*!< 0x0000FFFF */
+#define RTC_DIVL_RTC_DIV RTC_DIVL_RTC_DIV_Msk /*!< RTC Clock Divider Low */
+
+/******************* Bit definition for RTC_CNTH register *******************/
+#define RTC_CNTH_RTC_CNT_Pos (0U)
+#define RTC_CNTH_RTC_CNT_Msk (0xFFFFU << RTC_CNTH_RTC_CNT_Pos) /*!< 0x0000FFFF */
+#define RTC_CNTH_RTC_CNT RTC_CNTH_RTC_CNT_Msk /*!< RTC Counter High */
+
+/******************* Bit definition for RTC_CNTL register *******************/
+#define RTC_CNTL_RTC_CNT_Pos (0U)
+#define RTC_CNTL_RTC_CNT_Msk (0xFFFFU << RTC_CNTL_RTC_CNT_Pos) /*!< 0x0000FFFF */
+#define RTC_CNTL_RTC_CNT RTC_CNTL_RTC_CNT_Msk /*!< RTC Counter Low */
+
+/******************* Bit definition for RTC_ALRH register *******************/
+#define RTC_ALRH_RTC_ALR_Pos (0U)
+#define RTC_ALRH_RTC_ALR_Msk (0xFFFFU << RTC_ALRH_RTC_ALR_Pos) /*!< 0x0000FFFF */
+#define RTC_ALRH_RTC_ALR RTC_ALRH_RTC_ALR_Msk /*!< RTC Alarm High */
+
+/******************* Bit definition for RTC_ALRL register *******************/
+#define RTC_ALRL_RTC_ALR_Pos (0U)
+#define RTC_ALRL_RTC_ALR_Msk (0xFFFFU << RTC_ALRL_RTC_ALR_Pos) /*!< 0x0000FFFF */
+#define RTC_ALRL_RTC_ALR RTC_ALRL_RTC_ALR_Msk /*!< RTC Alarm Low */
+
+/******************************************************************************/
+/* */
+/* Independent WATCHDOG (IWDG) */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for IWDG_KR register ********************/
+#define IWDG_KR_KEY_Pos (0U)
+#define IWDG_KR_KEY_Msk (0xFFFFU << IWDG_KR_KEY_Pos) /*!< 0x0000FFFF */
+#define IWDG_KR_KEY IWDG_KR_KEY_Msk /*!< Key value (write only, read 0000h) */
+
+/******************* Bit definition for IWDG_PR register ********************/
+#define IWDG_PR_PR_Pos (0U)
+#define IWDG_PR_PR_Msk (0x7U << IWDG_PR_PR_Pos) /*!< 0x00000007 */
+#define IWDG_PR_PR IWDG_PR_PR_Msk /*!< PR[2:0] (Prescaler divider) */
+#define IWDG_PR_PR_0 (0x1U << IWDG_PR_PR_Pos) /*!< 0x00000001 */
+#define IWDG_PR_PR_1 (0x2U << IWDG_PR_PR_Pos) /*!< 0x00000002 */
+#define IWDG_PR_PR_2 (0x4U << IWDG_PR_PR_Pos) /*!< 0x00000004 */
+
+/******************* Bit definition for IWDG_RLR register *******************/
+#define IWDG_RLR_RL_Pos (0U)
+#define IWDG_RLR_RL_Msk (0xFFFU << IWDG_RLR_RL_Pos) /*!< 0x00000FFF */
+#define IWDG_RLR_RL IWDG_RLR_RL_Msk /*!< Watchdog counter reload value */
+
+/******************* Bit definition for IWDG_SR register ********************/
+#define IWDG_SR_PVU_Pos (0U)
+#define IWDG_SR_PVU_Msk (0x1U << IWDG_SR_PVU_Pos) /*!< 0x00000001 */
+#define IWDG_SR_PVU IWDG_SR_PVU_Msk /*!< Watchdog prescaler value update */
+#define IWDG_SR_RVU_Pos (1U)
+#define IWDG_SR_RVU_Msk (0x1U << IWDG_SR_RVU_Pos) /*!< 0x00000002 */
+#define IWDG_SR_RVU IWDG_SR_RVU_Msk /*!< Watchdog counter reload value update */
+
+/******************************************************************************/
+/* */
+/* Window WATCHDOG (WWDG) */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for WWDG_CR register ********************/
+#define WWDG_CR_T_Pos (0U)
+#define WWDG_CR_T_Msk (0x7FU << WWDG_CR_T_Pos) /*!< 0x0000007F */
+#define WWDG_CR_T WWDG_CR_T_Msk /*!< T[6:0] bits (7-Bit counter (MSB to LSB)) */
+#define WWDG_CR_T_0 (0x01U << WWDG_CR_T_Pos) /*!< 0x00000001 */
+#define WWDG_CR_T_1 (0x02U << WWDG_CR_T_Pos) /*!< 0x00000002 */
+#define WWDG_CR_T_2 (0x04U << WWDG_CR_T_Pos) /*!< 0x00000004 */
+#define WWDG_CR_T_3 (0x08U << WWDG_CR_T_Pos) /*!< 0x00000008 */
+#define WWDG_CR_T_4 (0x10U << WWDG_CR_T_Pos) /*!< 0x00000010 */
+#define WWDG_CR_T_5 (0x20U << WWDG_CR_T_Pos) /*!< 0x00000020 */
+#define WWDG_CR_T_6 (0x40U << WWDG_CR_T_Pos) /*!< 0x00000040 */
+
+/* Legacy defines */
+#define WWDG_CR_T0 WWDG_CR_T_0
+#define WWDG_CR_T1 WWDG_CR_T_1
+#define WWDG_CR_T2 WWDG_CR_T_2
+#define WWDG_CR_T3 WWDG_CR_T_3
+#define WWDG_CR_T4 WWDG_CR_T_4
+#define WWDG_CR_T5 WWDG_CR_T_5
+#define WWDG_CR_T6 WWDG_CR_T_6
+
+#define WWDG_CR_WDGA_Pos (7U)
+#define WWDG_CR_WDGA_Msk (0x1U << WWDG_CR_WDGA_Pos) /*!< 0x00000080 */
+#define WWDG_CR_WDGA WWDG_CR_WDGA_Msk /*!< Activation bit */
+
+/******************* Bit definition for WWDG_CFR register *******************/
+#define WWDG_CFR_W_Pos (0U)
+#define WWDG_CFR_W_Msk (0x7FU << WWDG_CFR_W_Pos) /*!< 0x0000007F */
+#define WWDG_CFR_W WWDG_CFR_W_Msk /*!< W[6:0] bits (7-bit window value) */
+#define WWDG_CFR_W_0 (0x01U << WWDG_CFR_W_Pos) /*!< 0x00000001 */
+#define WWDG_CFR_W_1 (0x02U << WWDG_CFR_W_Pos) /*!< 0x00000002 */
+#define WWDG_CFR_W_2 (0x04U << WWDG_CFR_W_Pos) /*!< 0x00000004 */
+#define WWDG_CFR_W_3 (0x08U << WWDG_CFR_W_Pos) /*!< 0x00000008 */
+#define WWDG_CFR_W_4 (0x10U << WWDG_CFR_W_Pos) /*!< 0x00000010 */
+#define WWDG_CFR_W_5 (0x20U << WWDG_CFR_W_Pos) /*!< 0x00000020 */
+#define WWDG_CFR_W_6 (0x40U << WWDG_CFR_W_Pos) /*!< 0x00000040 */
+
+/* Legacy defines */
+#define WWDG_CFR_W0 WWDG_CFR_W_0
+#define WWDG_CFR_W1 WWDG_CFR_W_1
+#define WWDG_CFR_W2 WWDG_CFR_W_2
+#define WWDG_CFR_W3 WWDG_CFR_W_3
+#define WWDG_CFR_W4 WWDG_CFR_W_4
+#define WWDG_CFR_W5 WWDG_CFR_W_5
+#define WWDG_CFR_W6 WWDG_CFR_W_6
+
+#define WWDG_CFR_WDGTB_Pos (7U)
+#define WWDG_CFR_WDGTB_Msk (0x3U << WWDG_CFR_WDGTB_Pos) /*!< 0x00000180 */
+#define WWDG_CFR_WDGTB WWDG_CFR_WDGTB_Msk /*!< WDGTB[1:0] bits (Timer Base) */
+#define WWDG_CFR_WDGTB_0 (0x1U << WWDG_CFR_WDGTB_Pos) /*!< 0x00000080 */
+#define WWDG_CFR_WDGTB_1 (0x2U << WWDG_CFR_WDGTB_Pos) /*!< 0x00000100 */
+
+/* Legacy defines */
+#define WWDG_CFR_WDGTB0 WWDG_CFR_WDGTB_0
+#define WWDG_CFR_WDGTB1 WWDG_CFR_WDGTB_1
+
+#define WWDG_CFR_EWI_Pos (9U)
+#define WWDG_CFR_EWI_Msk (0x1U << WWDG_CFR_EWI_Pos) /*!< 0x00000200 */
+#define WWDG_CFR_EWI WWDG_CFR_EWI_Msk /*!< Early Wakeup Interrupt */
+
+/******************* Bit definition for WWDG_SR register ********************/
+#define WWDG_SR_EWIF_Pos (0U)
+#define WWDG_SR_EWIF_Msk (0x1U << WWDG_SR_EWIF_Pos) /*!< 0x00000001 */
+#define WWDG_SR_EWIF WWDG_SR_EWIF_Msk /*!< Early Wakeup Interrupt Flag */
+
+
+/******************************************************************************/
+/* */
+/* SD host Interface */
+/* */
+/******************************************************************************/
+
+/****************** Bit definition for SDIO_POWER register ******************/
+#define SDIO_POWER_PWRCTRL_Pos (0U)
+#define SDIO_POWER_PWRCTRL_Msk (0x3U << SDIO_POWER_PWRCTRL_Pos) /*!< 0x00000003 */
+#define SDIO_POWER_PWRCTRL SDIO_POWER_PWRCTRL_Msk /*!< PWRCTRL[1:0] bits (Power supply control bits) */
+#define SDIO_POWER_PWRCTRL_0 (0x1U << SDIO_POWER_PWRCTRL_Pos) /*!< 0x01 */
+#define SDIO_POWER_PWRCTRL_1 (0x2U << SDIO_POWER_PWRCTRL_Pos) /*!< 0x02 */
+
+/****************** Bit definition for SDIO_CLKCR register ******************/
+#define SDIO_CLKCR_CLKDIV_Pos (0U)
+#define SDIO_CLKCR_CLKDIV_Msk (0xFFU << SDIO_CLKCR_CLKDIV_Pos) /*!< 0x000000FF */
+#define SDIO_CLKCR_CLKDIV SDIO_CLKCR_CLKDIV_Msk /*!< Clock divide factor */
+#define SDIO_CLKCR_CLKEN_Pos (8U)
+#define SDIO_CLKCR_CLKEN_Msk (0x1U << SDIO_CLKCR_CLKEN_Pos) /*!< 0x00000100 */
+#define SDIO_CLKCR_CLKEN SDIO_CLKCR_CLKEN_Msk /*!< Clock enable bit */
+#define SDIO_CLKCR_PWRSAV_Pos (9U)
+#define SDIO_CLKCR_PWRSAV_Msk (0x1U << SDIO_CLKCR_PWRSAV_Pos) /*!< 0x00000200 */
+#define SDIO_CLKCR_PWRSAV SDIO_CLKCR_PWRSAV_Msk /*!< Power saving configuration bit */
+#define SDIO_CLKCR_BYPASS_Pos (10U)
+#define SDIO_CLKCR_BYPASS_Msk (0x1U << SDIO_CLKCR_BYPASS_Pos) /*!< 0x00000400 */
+#define SDIO_CLKCR_BYPASS SDIO_CLKCR_BYPASS_Msk /*!< Clock divider bypass enable bit */
+
+#define SDIO_CLKCR_WIDBUS_Pos (11U)
+#define SDIO_CLKCR_WIDBUS_Msk (0x3U << SDIO_CLKCR_WIDBUS_Pos) /*!< 0x00001800 */
+#define SDIO_CLKCR_WIDBUS SDIO_CLKCR_WIDBUS_Msk /*!< WIDBUS[1:0] bits (Wide bus mode enable bit) */
+#define SDIO_CLKCR_WIDBUS_0 (0x1U << SDIO_CLKCR_WIDBUS_Pos) /*!< 0x0800 */
+#define SDIO_CLKCR_WIDBUS_1 (0x2U << SDIO_CLKCR_WIDBUS_Pos) /*!< 0x1000 */
+
+#define SDIO_CLKCR_NEGEDGE_Pos (13U)
+#define SDIO_CLKCR_NEGEDGE_Msk (0x1U << SDIO_CLKCR_NEGEDGE_Pos) /*!< 0x00002000 */
+#define SDIO_CLKCR_NEGEDGE SDIO_CLKCR_NEGEDGE_Msk /*!< SDIO_CK dephasing selection bit */
+#define SDIO_CLKCR_HWFC_EN_Pos (14U)
+#define SDIO_CLKCR_HWFC_EN_Msk (0x1U << SDIO_CLKCR_HWFC_EN_Pos) /*!< 0x00004000 */
+#define SDIO_CLKCR_HWFC_EN SDIO_CLKCR_HWFC_EN_Msk /*!< HW Flow Control enable */
+
+/******************* Bit definition for SDIO_ARG register *******************/
+#define SDIO_ARG_CMDARG_Pos (0U)
+#define SDIO_ARG_CMDARG_Msk (0xFFFFFFFFU << SDIO_ARG_CMDARG_Pos) /*!< 0xFFFFFFFF */
+#define SDIO_ARG_CMDARG SDIO_ARG_CMDARG_Msk /*!< Command argument */
+
+/******************* Bit definition for SDIO_CMD register *******************/
+#define SDIO_CMD_CMDINDEX_Pos (0U)
+#define SDIO_CMD_CMDINDEX_Msk (0x3FU << SDIO_CMD_CMDINDEX_Pos) /*!< 0x0000003F */
+#define SDIO_CMD_CMDINDEX SDIO_CMD_CMDINDEX_Msk /*!< Command Index */
+
+#define SDIO_CMD_WAITRESP_Pos (6U)
+#define SDIO_CMD_WAITRESP_Msk (0x3U << SDIO_CMD_WAITRESP_Pos) /*!< 0x000000C0 */
+#define SDIO_CMD_WAITRESP SDIO_CMD_WAITRESP_Msk /*!< WAITRESP[1:0] bits (Wait for response bits) */
+#define SDIO_CMD_WAITRESP_0 (0x1U << SDIO_CMD_WAITRESP_Pos) /*!< 0x0040 */
+#define SDIO_CMD_WAITRESP_1 (0x2U << SDIO_CMD_WAITRESP_Pos) /*!< 0x0080 */
+
+#define SDIO_CMD_WAITINT_Pos (8U)
+#define SDIO_CMD_WAITINT_Msk (0x1U << SDIO_CMD_WAITINT_Pos) /*!< 0x00000100 */
+#define SDIO_CMD_WAITINT SDIO_CMD_WAITINT_Msk /*!< CPSM Waits for Interrupt Request */
+#define SDIO_CMD_WAITPEND_Pos (9U)
+#define SDIO_CMD_WAITPEND_Msk (0x1U << SDIO_CMD_WAITPEND_Pos) /*!< 0x00000200 */
+#define SDIO_CMD_WAITPEND SDIO_CMD_WAITPEND_Msk /*!< CPSM Waits for ends of data transfer (CmdPend internal signal) */
+#define SDIO_CMD_CPSMEN_Pos (10U)
+#define SDIO_CMD_CPSMEN_Msk (0x1U << SDIO_CMD_CPSMEN_Pos) /*!< 0x00000400 */
+#define SDIO_CMD_CPSMEN SDIO_CMD_CPSMEN_Msk /*!< Command path state machine (CPSM) Enable bit */
+#define SDIO_CMD_SDIOSUSPEND_Pos (11U)
+#define SDIO_CMD_SDIOSUSPEND_Msk (0x1U << SDIO_CMD_SDIOSUSPEND_Pos) /*!< 0x00000800 */
+#define SDIO_CMD_SDIOSUSPEND SDIO_CMD_SDIOSUSPEND_Msk /*!< SD I/O suspend command */
+#define SDIO_CMD_ENCMDCOMPL_Pos (12U)
+#define SDIO_CMD_ENCMDCOMPL_Msk (0x1U << SDIO_CMD_ENCMDCOMPL_Pos) /*!< 0x00001000 */
+#define SDIO_CMD_ENCMDCOMPL SDIO_CMD_ENCMDCOMPL_Msk /*!< Enable CMD completion */
+#define SDIO_CMD_NIEN_Pos (13U)
+#define SDIO_CMD_NIEN_Msk (0x1U << SDIO_CMD_NIEN_Pos) /*!< 0x00002000 */
+#define SDIO_CMD_NIEN SDIO_CMD_NIEN_Msk /*!< Not Interrupt Enable */
+#define SDIO_CMD_CEATACMD_Pos (14U)
+#define SDIO_CMD_CEATACMD_Msk (0x1U << SDIO_CMD_CEATACMD_Pos) /*!< 0x00004000 */
+#define SDIO_CMD_CEATACMD SDIO_CMD_CEATACMD_Msk /*!< CE-ATA command */
+
+/***************** Bit definition for SDIO_RESPCMD register *****************/
+#define SDIO_RESPCMD_RESPCMD_Pos (0U)
+#define SDIO_RESPCMD_RESPCMD_Msk (0x3FU << SDIO_RESPCMD_RESPCMD_Pos) /*!< 0x0000003F */
+#define SDIO_RESPCMD_RESPCMD SDIO_RESPCMD_RESPCMD_Msk /*!< Response command index */
+
+/****************** Bit definition for SDIO_RESP0 register ******************/
+#define SDIO_RESP0_CARDSTATUS0_Pos (0U)
+#define SDIO_RESP0_CARDSTATUS0_Msk (0xFFFFFFFFU << SDIO_RESP0_CARDSTATUS0_Pos) /*!< 0xFFFFFFFF */
+#define SDIO_RESP0_CARDSTATUS0 SDIO_RESP0_CARDSTATUS0_Msk /*!< Card Status */
+
+/****************** Bit definition for SDIO_RESP1 register ******************/
+#define SDIO_RESP1_CARDSTATUS1_Pos (0U)
+#define SDIO_RESP1_CARDSTATUS1_Msk (0xFFFFFFFFU << SDIO_RESP1_CARDSTATUS1_Pos) /*!< 0xFFFFFFFF */
+#define SDIO_RESP1_CARDSTATUS1 SDIO_RESP1_CARDSTATUS1_Msk /*!< Card Status */
+
+/****************** Bit definition for SDIO_RESP2 register ******************/
+#define SDIO_RESP2_CARDSTATUS2_Pos (0U)
+#define SDIO_RESP2_CARDSTATUS2_Msk (0xFFFFFFFFU << SDIO_RESP2_CARDSTATUS2_Pos) /*!< 0xFFFFFFFF */
+#define SDIO_RESP2_CARDSTATUS2 SDIO_RESP2_CARDSTATUS2_Msk /*!< Card Status */
+
+/****************** Bit definition for SDIO_RESP3 register ******************/
+#define SDIO_RESP3_CARDSTATUS3_Pos (0U)
+#define SDIO_RESP3_CARDSTATUS3_Msk (0xFFFFFFFFU << SDIO_RESP3_CARDSTATUS3_Pos) /*!< 0xFFFFFFFF */
+#define SDIO_RESP3_CARDSTATUS3 SDIO_RESP3_CARDSTATUS3_Msk /*!< Card Status */
+
+/****************** Bit definition for SDIO_RESP4 register ******************/
+#define SDIO_RESP4_CARDSTATUS4_Pos (0U)
+#define SDIO_RESP4_CARDSTATUS4_Msk (0xFFFFFFFFU << SDIO_RESP4_CARDSTATUS4_Pos) /*!< 0xFFFFFFFF */
+#define SDIO_RESP4_CARDSTATUS4 SDIO_RESP4_CARDSTATUS4_Msk /*!< Card Status */
+
+/****************** Bit definition for SDIO_DTIMER register *****************/
+#define SDIO_DTIMER_DATATIME_Pos (0U)
+#define SDIO_DTIMER_DATATIME_Msk (0xFFFFFFFFU << SDIO_DTIMER_DATATIME_Pos) /*!< 0xFFFFFFFF */
+#define SDIO_DTIMER_DATATIME SDIO_DTIMER_DATATIME_Msk /*!< Data timeout period. */
+
+/****************** Bit definition for SDIO_DLEN register *******************/
+#define SDIO_DLEN_DATALENGTH_Pos (0U)
+#define SDIO_DLEN_DATALENGTH_Msk (0x1FFFFFFU << SDIO_DLEN_DATALENGTH_Pos) /*!< 0x01FFFFFF */
+#define SDIO_DLEN_DATALENGTH SDIO_DLEN_DATALENGTH_Msk /*!< Data length value */
+
+/****************** Bit definition for SDIO_DCTRL register ******************/
+#define SDIO_DCTRL_DTEN_Pos (0U)
+#define SDIO_DCTRL_DTEN_Msk (0x1U << SDIO_DCTRL_DTEN_Pos) /*!< 0x00000001 */
+#define SDIO_DCTRL_DTEN SDIO_DCTRL_DTEN_Msk /*!< Data transfer enabled bit */
+#define SDIO_DCTRL_DTDIR_Pos (1U)
+#define SDIO_DCTRL_DTDIR_Msk (0x1U << SDIO_DCTRL_DTDIR_Pos) /*!< 0x00000002 */
+#define SDIO_DCTRL_DTDIR SDIO_DCTRL_DTDIR_Msk /*!< Data transfer direction selection */
+#define SDIO_DCTRL_DTMODE_Pos (2U)
+#define SDIO_DCTRL_DTMODE_Msk (0x1U << SDIO_DCTRL_DTMODE_Pos) /*!< 0x00000004 */
+#define SDIO_DCTRL_DTMODE SDIO_DCTRL_DTMODE_Msk /*!< Data transfer mode selection */
+#define SDIO_DCTRL_DMAEN_Pos (3U)
+#define SDIO_DCTRL_DMAEN_Msk (0x1U << SDIO_DCTRL_DMAEN_Pos) /*!< 0x00000008 */
+#define SDIO_DCTRL_DMAEN SDIO_DCTRL_DMAEN_Msk /*!< DMA enabled bit */
+
+#define SDIO_DCTRL_DBLOCKSIZE_Pos (4U)
+#define SDIO_DCTRL_DBLOCKSIZE_Msk (0xFU << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x000000F0 */
+#define SDIO_DCTRL_DBLOCKSIZE SDIO_DCTRL_DBLOCKSIZE_Msk /*!< DBLOCKSIZE[3:0] bits (Data block size) */
+#define SDIO_DCTRL_DBLOCKSIZE_0 (0x1U << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0010 */
+#define SDIO_DCTRL_DBLOCKSIZE_1 (0x2U << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0020 */
+#define SDIO_DCTRL_DBLOCKSIZE_2 (0x4U << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0040 */
+#define SDIO_DCTRL_DBLOCKSIZE_3 (0x8U << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0080 */
+
+#define SDIO_DCTRL_RWSTART_Pos (8U)
+#define SDIO_DCTRL_RWSTART_Msk (0x1U << SDIO_DCTRL_RWSTART_Pos) /*!< 0x00000100 */
+#define SDIO_DCTRL_RWSTART SDIO_DCTRL_RWSTART_Msk /*!< Read wait start */
+#define SDIO_DCTRL_RWSTOP_Pos (9U)
+#define SDIO_DCTRL_RWSTOP_Msk (0x1U << SDIO_DCTRL_RWSTOP_Pos) /*!< 0x00000200 */
+#define SDIO_DCTRL_RWSTOP SDIO_DCTRL_RWSTOP_Msk /*!< Read wait stop */
+#define SDIO_DCTRL_RWMOD_Pos (10U)
+#define SDIO_DCTRL_RWMOD_Msk (0x1U << SDIO_DCTRL_RWMOD_Pos) /*!< 0x00000400 */
+#define SDIO_DCTRL_RWMOD SDIO_DCTRL_RWMOD_Msk /*!< Read wait mode */
+#define SDIO_DCTRL_SDIOEN_Pos (11U)
+#define SDIO_DCTRL_SDIOEN_Msk (0x1U << SDIO_DCTRL_SDIOEN_Pos) /*!< 0x00000800 */
+#define SDIO_DCTRL_SDIOEN SDIO_DCTRL_SDIOEN_Msk /*!< SD I/O enable functions */
+
+/****************** Bit definition for SDIO_DCOUNT register *****************/
+#define SDIO_DCOUNT_DATACOUNT_Pos (0U)
+#define SDIO_DCOUNT_DATACOUNT_Msk (0x1FFFFFFU << SDIO_DCOUNT_DATACOUNT_Pos) /*!< 0x01FFFFFF */
+#define SDIO_DCOUNT_DATACOUNT SDIO_DCOUNT_DATACOUNT_Msk /*!< Data count value */
+
+/****************** Bit definition for SDIO_STA register ********************/
+#define SDIO_STA_CCRCFAIL_Pos (0U)
+#define SDIO_STA_CCRCFAIL_Msk (0x1U << SDIO_STA_CCRCFAIL_Pos) /*!< 0x00000001 */
+#define SDIO_STA_CCRCFAIL SDIO_STA_CCRCFAIL_Msk /*!< Command response received (CRC check failed) */
+#define SDIO_STA_DCRCFAIL_Pos (1U)
+#define SDIO_STA_DCRCFAIL_Msk (0x1U << SDIO_STA_DCRCFAIL_Pos) /*!< 0x00000002 */
+#define SDIO_STA_DCRCFAIL SDIO_STA_DCRCFAIL_Msk /*!< Data block sent/received (CRC check failed) */
+#define SDIO_STA_CTIMEOUT_Pos (2U)
+#define SDIO_STA_CTIMEOUT_Msk (0x1U << SDIO_STA_CTIMEOUT_Pos) /*!< 0x00000004 */
+#define SDIO_STA_CTIMEOUT SDIO_STA_CTIMEOUT_Msk /*!< Command response timeout */
+#define SDIO_STA_DTIMEOUT_Pos (3U)
+#define SDIO_STA_DTIMEOUT_Msk (0x1U << SDIO_STA_DTIMEOUT_Pos) /*!< 0x00000008 */
+#define SDIO_STA_DTIMEOUT SDIO_STA_DTIMEOUT_Msk /*!< Data timeout */
+#define SDIO_STA_TXUNDERR_Pos (4U)
+#define SDIO_STA_TXUNDERR_Msk (0x1U << SDIO_STA_TXUNDERR_Pos) /*!< 0x00000010 */
+#define SDIO_STA_TXUNDERR SDIO_STA_TXUNDERR_Msk /*!< Transmit FIFO underrun error */
+#define SDIO_STA_RXOVERR_Pos (5U)
+#define SDIO_STA_RXOVERR_Msk (0x1U << SDIO_STA_RXOVERR_Pos) /*!< 0x00000020 */
+#define SDIO_STA_RXOVERR SDIO_STA_RXOVERR_Msk /*!< Received FIFO overrun error */
+#define SDIO_STA_CMDREND_Pos (6U)
+#define SDIO_STA_CMDREND_Msk (0x1U << SDIO_STA_CMDREND_Pos) /*!< 0x00000040 */
+#define SDIO_STA_CMDREND SDIO_STA_CMDREND_Msk /*!< Command response received (CRC check passed) */
+#define SDIO_STA_CMDSENT_Pos (7U)
+#define SDIO_STA_CMDSENT_Msk (0x1U << SDIO_STA_CMDSENT_Pos) /*!< 0x00000080 */
+#define SDIO_STA_CMDSENT SDIO_STA_CMDSENT_Msk /*!< Command sent (no response required) */
+#define SDIO_STA_DATAEND_Pos (8U)
+#define SDIO_STA_DATAEND_Msk (0x1U << SDIO_STA_DATAEND_Pos) /*!< 0x00000100 */
+#define SDIO_STA_DATAEND SDIO_STA_DATAEND_Msk /*!< Data end (data counter, SDIDCOUNT, is zero) */
+#define SDIO_STA_STBITERR_Pos (9U)
+#define SDIO_STA_STBITERR_Msk (0x1U << SDIO_STA_STBITERR_Pos) /*!< 0x00000200 */
+#define SDIO_STA_STBITERR SDIO_STA_STBITERR_Msk /*!< Start bit not detected on all data signals in wide bus mode */
+#define SDIO_STA_DBCKEND_Pos (10U)
+#define SDIO_STA_DBCKEND_Msk (0x1U << SDIO_STA_DBCKEND_Pos) /*!< 0x00000400 */
+#define SDIO_STA_DBCKEND SDIO_STA_DBCKEND_Msk /*!< Data block sent/received (CRC check passed) */
+#define SDIO_STA_CMDACT_Pos (11U)
+#define SDIO_STA_CMDACT_Msk (0x1U << SDIO_STA_CMDACT_Pos) /*!< 0x00000800 */
+#define SDIO_STA_CMDACT SDIO_STA_CMDACT_Msk /*!< Command transfer in progress */
+#define SDIO_STA_TXACT_Pos (12U)
+#define SDIO_STA_TXACT_Msk (0x1U << SDIO_STA_TXACT_Pos) /*!< 0x00001000 */
+#define SDIO_STA_TXACT SDIO_STA_TXACT_Msk /*!< Data transmit in progress */
+#define SDIO_STA_RXACT_Pos (13U)
+#define SDIO_STA_RXACT_Msk (0x1U << SDIO_STA_RXACT_Pos) /*!< 0x00002000 */
+#define SDIO_STA_RXACT SDIO_STA_RXACT_Msk /*!< Data receive in progress */
+#define SDIO_STA_TXFIFOHE_Pos (14U)
+#define SDIO_STA_TXFIFOHE_Msk (0x1U << SDIO_STA_TXFIFOHE_Pos) /*!< 0x00004000 */
+#define SDIO_STA_TXFIFOHE SDIO_STA_TXFIFOHE_Msk /*!< Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
+#define SDIO_STA_RXFIFOHF_Pos (15U)
+#define SDIO_STA_RXFIFOHF_Msk (0x1U << SDIO_STA_RXFIFOHF_Pos) /*!< 0x00008000 */
+#define SDIO_STA_RXFIFOHF SDIO_STA_RXFIFOHF_Msk /*!< Receive FIFO Half Full: there are at least 8 words in the FIFO */
+#define SDIO_STA_TXFIFOF_Pos (16U)
+#define SDIO_STA_TXFIFOF_Msk (0x1U << SDIO_STA_TXFIFOF_Pos) /*!< 0x00010000 */
+#define SDIO_STA_TXFIFOF SDIO_STA_TXFIFOF_Msk /*!< Transmit FIFO full */
+#define SDIO_STA_RXFIFOF_Pos (17U)
+#define SDIO_STA_RXFIFOF_Msk (0x1U << SDIO_STA_RXFIFOF_Pos) /*!< 0x00020000 */
+#define SDIO_STA_RXFIFOF SDIO_STA_RXFIFOF_Msk /*!< Receive FIFO full */
+#define SDIO_STA_TXFIFOE_Pos (18U)
+#define SDIO_STA_TXFIFOE_Msk (0x1U << SDIO_STA_TXFIFOE_Pos) /*!< 0x00040000 */
+#define SDIO_STA_TXFIFOE SDIO_STA_TXFIFOE_Msk /*!< Transmit FIFO empty */
+#define SDIO_STA_RXFIFOE_Pos (19U)
+#define SDIO_STA_RXFIFOE_Msk (0x1U << SDIO_STA_RXFIFOE_Pos) /*!< 0x00080000 */
+#define SDIO_STA_RXFIFOE SDIO_STA_RXFIFOE_Msk /*!< Receive FIFO empty */
+#define SDIO_STA_TXDAVL_Pos (20U)
+#define SDIO_STA_TXDAVL_Msk (0x1U << SDIO_STA_TXDAVL_Pos) /*!< 0x00100000 */
+#define SDIO_STA_TXDAVL SDIO_STA_TXDAVL_Msk /*!< Data available in transmit FIFO */
+#define SDIO_STA_RXDAVL_Pos (21U)
+#define SDIO_STA_RXDAVL_Msk (0x1U << SDIO_STA_RXDAVL_Pos) /*!< 0x00200000 */
+#define SDIO_STA_RXDAVL SDIO_STA_RXDAVL_Msk /*!< Data available in receive FIFO */
+#define SDIO_STA_SDIOIT_Pos (22U)
+#define SDIO_STA_SDIOIT_Msk (0x1U << SDIO_STA_SDIOIT_Pos) /*!< 0x00400000 */
+#define SDIO_STA_SDIOIT SDIO_STA_SDIOIT_Msk /*!< SDIO interrupt received */
+#define SDIO_STA_CEATAEND_Pos (23U)
+#define SDIO_STA_CEATAEND_Msk (0x1U << SDIO_STA_CEATAEND_Pos) /*!< 0x00800000 */
+#define SDIO_STA_CEATAEND SDIO_STA_CEATAEND_Msk /*!< CE-ATA command completion signal received for CMD61 */
+
+/******************* Bit definition for SDIO_ICR register *******************/
+#define SDIO_ICR_CCRCFAILC_Pos (0U)
+#define SDIO_ICR_CCRCFAILC_Msk (0x1U << SDIO_ICR_CCRCFAILC_Pos) /*!< 0x00000001 */
+#define SDIO_ICR_CCRCFAILC SDIO_ICR_CCRCFAILC_Msk /*!< CCRCFAIL flag clear bit */
+#define SDIO_ICR_DCRCFAILC_Pos (1U)
+#define SDIO_ICR_DCRCFAILC_Msk (0x1U << SDIO_ICR_DCRCFAILC_Pos) /*!< 0x00000002 */
+#define SDIO_ICR_DCRCFAILC SDIO_ICR_DCRCFAILC_Msk /*!< DCRCFAIL flag clear bit */
+#define SDIO_ICR_CTIMEOUTC_Pos (2U)
+#define SDIO_ICR_CTIMEOUTC_Msk (0x1U << SDIO_ICR_CTIMEOUTC_Pos) /*!< 0x00000004 */
+#define SDIO_ICR_CTIMEOUTC SDIO_ICR_CTIMEOUTC_Msk /*!< CTIMEOUT flag clear bit */
+#define SDIO_ICR_DTIMEOUTC_Pos (3U)
+#define SDIO_ICR_DTIMEOUTC_Msk (0x1U << SDIO_ICR_DTIMEOUTC_Pos) /*!< 0x00000008 */
+#define SDIO_ICR_DTIMEOUTC SDIO_ICR_DTIMEOUTC_Msk /*!< DTIMEOUT flag clear bit */
+#define SDIO_ICR_TXUNDERRC_Pos (4U)
+#define SDIO_ICR_TXUNDERRC_Msk (0x1U << SDIO_ICR_TXUNDERRC_Pos) /*!< 0x00000010 */
+#define SDIO_ICR_TXUNDERRC SDIO_ICR_TXUNDERRC_Msk /*!< TXUNDERR flag clear bit */
+#define SDIO_ICR_RXOVERRC_Pos (5U)
+#define SDIO_ICR_RXOVERRC_Msk (0x1U << SDIO_ICR_RXOVERRC_Pos) /*!< 0x00000020 */
+#define SDIO_ICR_RXOVERRC SDIO_ICR_RXOVERRC_Msk /*!< RXOVERR flag clear bit */
+#define SDIO_ICR_CMDRENDC_Pos (6U)
+#define SDIO_ICR_CMDRENDC_Msk (0x1U << SDIO_ICR_CMDRENDC_Pos) /*!< 0x00000040 */
+#define SDIO_ICR_CMDRENDC SDIO_ICR_CMDRENDC_Msk /*!< CMDREND flag clear bit */
+#define SDIO_ICR_CMDSENTC_Pos (7U)
+#define SDIO_ICR_CMDSENTC_Msk (0x1U << SDIO_ICR_CMDSENTC_Pos) /*!< 0x00000080 */
+#define SDIO_ICR_CMDSENTC SDIO_ICR_CMDSENTC_Msk /*!< CMDSENT flag clear bit */
+#define SDIO_ICR_DATAENDC_Pos (8U)
+#define SDIO_ICR_DATAENDC_Msk (0x1U << SDIO_ICR_DATAENDC_Pos) /*!< 0x00000100 */
+#define SDIO_ICR_DATAENDC SDIO_ICR_DATAENDC_Msk /*!< DATAEND flag clear bit */
+#define SDIO_ICR_STBITERRC_Pos (9U)
+#define SDIO_ICR_STBITERRC_Msk (0x1U << SDIO_ICR_STBITERRC_Pos) /*!< 0x00000200 */
+#define SDIO_ICR_STBITERRC SDIO_ICR_STBITERRC_Msk /*!< STBITERR flag clear bit */
+#define SDIO_ICR_DBCKENDC_Pos (10U)
+#define SDIO_ICR_DBCKENDC_Msk (0x1U << SDIO_ICR_DBCKENDC_Pos) /*!< 0x00000400 */
+#define SDIO_ICR_DBCKENDC SDIO_ICR_DBCKENDC_Msk /*!< DBCKEND flag clear bit */
+#define SDIO_ICR_SDIOITC_Pos (22U)
+#define SDIO_ICR_SDIOITC_Msk (0x1U << SDIO_ICR_SDIOITC_Pos) /*!< 0x00400000 */
+#define SDIO_ICR_SDIOITC SDIO_ICR_SDIOITC_Msk /*!< SDIOIT flag clear bit */
+#define SDIO_ICR_CEATAENDC_Pos (23U)
+#define SDIO_ICR_CEATAENDC_Msk (0x1U << SDIO_ICR_CEATAENDC_Pos) /*!< 0x00800000 */
+#define SDIO_ICR_CEATAENDC SDIO_ICR_CEATAENDC_Msk /*!< CEATAEND flag clear bit */
+
+/****************** Bit definition for SDIO_MASK register *******************/
+#define SDIO_MASK_CCRCFAILIE_Pos (0U)
+#define SDIO_MASK_CCRCFAILIE_Msk (0x1U << SDIO_MASK_CCRCFAILIE_Pos) /*!< 0x00000001 */
+#define SDIO_MASK_CCRCFAILIE SDIO_MASK_CCRCFAILIE_Msk /*!< Command CRC Fail Interrupt Enable */
+#define SDIO_MASK_DCRCFAILIE_Pos (1U)
+#define SDIO_MASK_DCRCFAILIE_Msk (0x1U << SDIO_MASK_DCRCFAILIE_Pos) /*!< 0x00000002 */
+#define SDIO_MASK_DCRCFAILIE SDIO_MASK_DCRCFAILIE_Msk /*!< Data CRC Fail Interrupt Enable */
+#define SDIO_MASK_CTIMEOUTIE_Pos (2U)
+#define SDIO_MASK_CTIMEOUTIE_Msk (0x1U << SDIO_MASK_CTIMEOUTIE_Pos) /*!< 0x00000004 */
+#define SDIO_MASK_CTIMEOUTIE SDIO_MASK_CTIMEOUTIE_Msk /*!< Command TimeOut Interrupt Enable */
+#define SDIO_MASK_DTIMEOUTIE_Pos (3U)
+#define SDIO_MASK_DTIMEOUTIE_Msk (0x1U << SDIO_MASK_DTIMEOUTIE_Pos) /*!< 0x00000008 */
+#define SDIO_MASK_DTIMEOUTIE SDIO_MASK_DTIMEOUTIE_Msk /*!< Data TimeOut Interrupt Enable */
+#define SDIO_MASK_TXUNDERRIE_Pos (4U)
+#define SDIO_MASK_TXUNDERRIE_Msk (0x1U << SDIO_MASK_TXUNDERRIE_Pos) /*!< 0x00000010 */
+#define SDIO_MASK_TXUNDERRIE SDIO_MASK_TXUNDERRIE_Msk /*!< Tx FIFO UnderRun Error Interrupt Enable */
+#define SDIO_MASK_RXOVERRIE_Pos (5U)
+#define SDIO_MASK_RXOVERRIE_Msk (0x1U << SDIO_MASK_RXOVERRIE_Pos) /*!< 0x00000020 */
+#define SDIO_MASK_RXOVERRIE SDIO_MASK_RXOVERRIE_Msk /*!< Rx FIFO OverRun Error Interrupt Enable */
+#define SDIO_MASK_CMDRENDIE_Pos (6U)
+#define SDIO_MASK_CMDRENDIE_Msk (0x1U << SDIO_MASK_CMDRENDIE_Pos) /*!< 0x00000040 */
+#define SDIO_MASK_CMDRENDIE SDIO_MASK_CMDRENDIE_Msk /*!< Command Response Received Interrupt Enable */
+#define SDIO_MASK_CMDSENTIE_Pos (7U)
+#define SDIO_MASK_CMDSENTIE_Msk (0x1U << SDIO_MASK_CMDSENTIE_Pos) /*!< 0x00000080 */
+#define SDIO_MASK_CMDSENTIE SDIO_MASK_CMDSENTIE_Msk /*!< Command Sent Interrupt Enable */
+#define SDIO_MASK_DATAENDIE_Pos (8U)
+#define SDIO_MASK_DATAENDIE_Msk (0x1U << SDIO_MASK_DATAENDIE_Pos) /*!< 0x00000100 */
+#define SDIO_MASK_DATAENDIE SDIO_MASK_DATAENDIE_Msk /*!< Data End Interrupt Enable */
+#define SDIO_MASK_STBITERRIE_Pos (9U)
+#define SDIO_MASK_STBITERRIE_Msk (0x1U << SDIO_MASK_STBITERRIE_Pos) /*!< 0x00000200 */
+#define SDIO_MASK_STBITERRIE SDIO_MASK_STBITERRIE_Msk /*!< Start Bit Error Interrupt Enable */
+#define SDIO_MASK_DBCKENDIE_Pos (10U)
+#define SDIO_MASK_DBCKENDIE_Msk (0x1U << SDIO_MASK_DBCKENDIE_Pos) /*!< 0x00000400 */
+#define SDIO_MASK_DBCKENDIE SDIO_MASK_DBCKENDIE_Msk /*!< Data Block End Interrupt Enable */
+#define SDIO_MASK_CMDACTIE_Pos (11U)
+#define SDIO_MASK_CMDACTIE_Msk (0x1U << SDIO_MASK_CMDACTIE_Pos) /*!< 0x00000800 */
+#define SDIO_MASK_CMDACTIE SDIO_MASK_CMDACTIE_Msk /*!< Command Acting Interrupt Enable */
+#define SDIO_MASK_TXACTIE_Pos (12U)
+#define SDIO_MASK_TXACTIE_Msk (0x1U << SDIO_MASK_TXACTIE_Pos) /*!< 0x00001000 */
+#define SDIO_MASK_TXACTIE SDIO_MASK_TXACTIE_Msk /*!< Data Transmit Acting Interrupt Enable */
+#define SDIO_MASK_RXACTIE_Pos (13U)
+#define SDIO_MASK_RXACTIE_Msk (0x1U << SDIO_MASK_RXACTIE_Pos) /*!< 0x00002000 */
+#define SDIO_MASK_RXACTIE SDIO_MASK_RXACTIE_Msk /*!< Data receive acting interrupt enabled */
+#define SDIO_MASK_TXFIFOHEIE_Pos (14U)
+#define SDIO_MASK_TXFIFOHEIE_Msk (0x1U << SDIO_MASK_TXFIFOHEIE_Pos) /*!< 0x00004000 */
+#define SDIO_MASK_TXFIFOHEIE SDIO_MASK_TXFIFOHEIE_Msk /*!< Tx FIFO Half Empty interrupt Enable */
+#define SDIO_MASK_RXFIFOHFIE_Pos (15U)
+#define SDIO_MASK_RXFIFOHFIE_Msk (0x1U << SDIO_MASK_RXFIFOHFIE_Pos) /*!< 0x00008000 */
+#define SDIO_MASK_RXFIFOHFIE SDIO_MASK_RXFIFOHFIE_Msk /*!< Rx FIFO Half Full interrupt Enable */
+#define SDIO_MASK_TXFIFOFIE_Pos (16U)
+#define SDIO_MASK_TXFIFOFIE_Msk (0x1U << SDIO_MASK_TXFIFOFIE_Pos) /*!< 0x00010000 */
+#define SDIO_MASK_TXFIFOFIE SDIO_MASK_TXFIFOFIE_Msk /*!< Tx FIFO Full interrupt Enable */
+#define SDIO_MASK_RXFIFOFIE_Pos (17U)
+#define SDIO_MASK_RXFIFOFIE_Msk (0x1U << SDIO_MASK_RXFIFOFIE_Pos) /*!< 0x00020000 */
+#define SDIO_MASK_RXFIFOFIE SDIO_MASK_RXFIFOFIE_Msk /*!< Rx FIFO Full interrupt Enable */
+#define SDIO_MASK_TXFIFOEIE_Pos (18U)
+#define SDIO_MASK_TXFIFOEIE_Msk (0x1U << SDIO_MASK_TXFIFOEIE_Pos) /*!< 0x00040000 */
+#define SDIO_MASK_TXFIFOEIE SDIO_MASK_TXFIFOEIE_Msk /*!< Tx FIFO Empty interrupt Enable */
+#define SDIO_MASK_RXFIFOEIE_Pos (19U)
+#define SDIO_MASK_RXFIFOEIE_Msk (0x1U << SDIO_MASK_RXFIFOEIE_Pos) /*!< 0x00080000 */
+#define SDIO_MASK_RXFIFOEIE SDIO_MASK_RXFIFOEIE_Msk /*!< Rx FIFO Empty interrupt Enable */
+#define SDIO_MASK_TXDAVLIE_Pos (20U)
+#define SDIO_MASK_TXDAVLIE_Msk (0x1U << SDIO_MASK_TXDAVLIE_Pos) /*!< 0x00100000 */
+#define SDIO_MASK_TXDAVLIE SDIO_MASK_TXDAVLIE_Msk /*!< Data available in Tx FIFO interrupt Enable */
+#define SDIO_MASK_RXDAVLIE_Pos (21U)
+#define SDIO_MASK_RXDAVLIE_Msk (0x1U << SDIO_MASK_RXDAVLIE_Pos) /*!< 0x00200000 */
+#define SDIO_MASK_RXDAVLIE SDIO_MASK_RXDAVLIE_Msk /*!< Data available in Rx FIFO interrupt Enable */
+#define SDIO_MASK_SDIOITIE_Pos (22U)
+#define SDIO_MASK_SDIOITIE_Msk (0x1U << SDIO_MASK_SDIOITIE_Pos) /*!< 0x00400000 */
+#define SDIO_MASK_SDIOITIE SDIO_MASK_SDIOITIE_Msk /*!< SDIO Mode Interrupt Received interrupt Enable */
+#define SDIO_MASK_CEATAENDIE_Pos (23U)
+#define SDIO_MASK_CEATAENDIE_Msk (0x1U << SDIO_MASK_CEATAENDIE_Pos) /*!< 0x00800000 */
+#define SDIO_MASK_CEATAENDIE SDIO_MASK_CEATAENDIE_Msk /*!< CE-ATA command completion signal received Interrupt Enable */
+
+/***************** Bit definition for SDIO_FIFOCNT register *****************/
+#define SDIO_FIFOCNT_FIFOCOUNT_Pos (0U)
+#define SDIO_FIFOCNT_FIFOCOUNT_Msk (0xFFFFFFU << SDIO_FIFOCNT_FIFOCOUNT_Pos) /*!< 0x00FFFFFF */
+#define SDIO_FIFOCNT_FIFOCOUNT SDIO_FIFOCNT_FIFOCOUNT_Msk /*!< Remaining number of words to be written to or read from the FIFO */
+
+/****************** Bit definition for SDIO_FIFO register *******************/
+#define SDIO_FIFO_FIFODATA_Pos (0U)
+#define SDIO_FIFO_FIFODATA_Msk (0xFFFFFFFFU << SDIO_FIFO_FIFODATA_Pos) /*!< 0xFFFFFFFF */
+#define SDIO_FIFO_FIFODATA SDIO_FIFO_FIFODATA_Msk /*!< Receive and transmit FIFO data */
+
+/******************************************************************************/
+/* */
+/* USB Device FS */
+/* */
+/******************************************************************************/
+
+/*!< Endpoint-specific registers */
+#define USB_EP0R USB_BASE /*!< Endpoint 0 register address */
+#define USB_EP1R (USB_BASE + 0x00000004) /*!< Endpoint 1 register address */
+#define USB_EP2R (USB_BASE + 0x00000008) /*!< Endpoint 2 register address */
+#define USB_EP3R (USB_BASE + 0x0000000C) /*!< Endpoint 3 register address */
+#define USB_EP4R (USB_BASE + 0x00000010) /*!< Endpoint 4 register address */
+#define USB_EP5R (USB_BASE + 0x00000014) /*!< Endpoint 5 register address */
+#define USB_EP6R (USB_BASE + 0x00000018) /*!< Endpoint 6 register address */
+#define USB_EP7R (USB_BASE + 0x0000001C) /*!< Endpoint 7 register address */
+
+/* bit positions */
+#define USB_EP_CTR_RX_Pos (15U)
+#define USB_EP_CTR_RX_Msk (0x1U << USB_EP_CTR_RX_Pos) /*!< 0x00008000 */
+#define USB_EP_CTR_RX USB_EP_CTR_RX_Msk /*!< EndPoint Correct TRansfer RX */
+#define USB_EP_DTOG_RX_Pos (14U)
+#define USB_EP_DTOG_RX_Msk (0x1U << USB_EP_DTOG_RX_Pos) /*!< 0x00004000 */
+#define USB_EP_DTOG_RX USB_EP_DTOG_RX_Msk /*!< EndPoint Data TOGGLE RX */
+#define USB_EPRX_STAT_Pos (12U)
+#define USB_EPRX_STAT_Msk (0x3U << USB_EPRX_STAT_Pos) /*!< 0x00003000 */
+#define USB_EPRX_STAT USB_EPRX_STAT_Msk /*!< EndPoint RX STATus bit field */
+#define USB_EP_SETUP_Pos (11U)
+#define USB_EP_SETUP_Msk (0x1U << USB_EP_SETUP_Pos) /*!< 0x00000800 */
+#define USB_EP_SETUP USB_EP_SETUP_Msk /*!< EndPoint SETUP */
+#define USB_EP_T_FIELD_Pos (9U)
+#define USB_EP_T_FIELD_Msk (0x3U << USB_EP_T_FIELD_Pos) /*!< 0x00000600 */
+#define USB_EP_T_FIELD USB_EP_T_FIELD_Msk /*!< EndPoint TYPE */
+#define USB_EP_KIND_Pos (8U)
+#define USB_EP_KIND_Msk (0x1U << USB_EP_KIND_Pos) /*!< 0x00000100 */
+#define USB_EP_KIND USB_EP_KIND_Msk /*!< EndPoint KIND */
+#define USB_EP_CTR_TX_Pos (7U)
+#define USB_EP_CTR_TX_Msk (0x1U << USB_EP_CTR_TX_Pos) /*!< 0x00000080 */
+#define USB_EP_CTR_TX USB_EP_CTR_TX_Msk /*!< EndPoint Correct TRansfer TX */
+#define USB_EP_DTOG_TX_Pos (6U)
+#define USB_EP_DTOG_TX_Msk (0x1U << USB_EP_DTOG_TX_Pos) /*!< 0x00000040 */
+#define USB_EP_DTOG_TX USB_EP_DTOG_TX_Msk /*!< EndPoint Data TOGGLE TX */
+#define USB_EPTX_STAT_Pos (4U)
+#define USB_EPTX_STAT_Msk (0x3U << USB_EPTX_STAT_Pos) /*!< 0x00000030 */
+#define USB_EPTX_STAT USB_EPTX_STAT_Msk /*!< EndPoint TX STATus bit field */
+#define USB_EPADDR_FIELD_Pos (0U)
+#define USB_EPADDR_FIELD_Msk (0xFU << USB_EPADDR_FIELD_Pos) /*!< 0x0000000F */
+#define USB_EPADDR_FIELD USB_EPADDR_FIELD_Msk /*!< EndPoint ADDRess FIELD */
+
+/* EndPoint REGister MASK (no toggle fields) */
+#define USB_EPREG_MASK (USB_EP_CTR_RX|USB_EP_SETUP|USB_EP_T_FIELD|USB_EP_KIND|USB_EP_CTR_TX|USB_EPADDR_FIELD)
+ /*!< EP_TYPE[1:0] EndPoint TYPE */
+#define USB_EP_TYPE_MASK_Pos (9U)
+#define USB_EP_TYPE_MASK_Msk (0x3U << USB_EP_TYPE_MASK_Pos) /*!< 0x00000600 */
+#define USB_EP_TYPE_MASK USB_EP_TYPE_MASK_Msk /*!< EndPoint TYPE Mask */
+#define USB_EP_BULK ((uint32_t)0x00000000) /*!< EndPoint BULK */
+#define USB_EP_CONTROL ((uint32_t)0x00000200) /*!< EndPoint CONTROL */
+#define USB_EP_ISOCHRONOUS ((uint32_t)0x00000400) /*!< EndPoint ISOCHRONOUS */
+#define USB_EP_INTERRUPT ((uint32_t)0x00000600) /*!< EndPoint INTERRUPT */
+#define USB_EP_T_MASK (~USB_EP_T_FIELD & USB_EPREG_MASK)
+
+#define USB_EPKIND_MASK (~USB_EP_KIND & USB_EPREG_MASK) /*!< EP_KIND EndPoint KIND */
+ /*!< STAT_TX[1:0] STATus for TX transfer */
+#define USB_EP_TX_DIS ((uint32_t)0x00000000) /*!< EndPoint TX DISabled */
+#define USB_EP_TX_STALL ((uint32_t)0x00000010) /*!< EndPoint TX STALLed */
+#define USB_EP_TX_NAK ((uint32_t)0x00000020) /*!< EndPoint TX NAKed */
+#define USB_EP_TX_VALID ((uint32_t)0x00000030) /*!< EndPoint TX VALID */
+#define USB_EPTX_DTOG1 ((uint32_t)0x00000010) /*!< EndPoint TX Data TOGgle bit1 */
+#define USB_EPTX_DTOG2 ((uint32_t)0x00000020) /*!< EndPoint TX Data TOGgle bit2 */
+#define USB_EPTX_DTOGMASK (USB_EPTX_STAT|USB_EPREG_MASK)
+ /*!< STAT_RX[1:0] STATus for RX transfer */
+#define USB_EP_RX_DIS ((uint32_t)0x00000000) /*!< EndPoint RX DISabled */
+#define USB_EP_RX_STALL ((uint32_t)0x00001000) /*!< EndPoint RX STALLed */
+#define USB_EP_RX_NAK ((uint32_t)0x00002000) /*!< EndPoint RX NAKed */
+#define USB_EP_RX_VALID ((uint32_t)0x00003000) /*!< EndPoint RX VALID */
+#define USB_EPRX_DTOG1 ((uint32_t)0x00001000) /*!< EndPoint RX Data TOGgle bit1 */
+#define USB_EPRX_DTOG2 ((uint32_t)0x00002000) /*!< EndPoint RX Data TOGgle bit1 */
+#define USB_EPRX_DTOGMASK (USB_EPRX_STAT|USB_EPREG_MASK)
+
+/******************* Bit definition for USB_EP0R register *******************/
+#define USB_EP0R_EA_Pos (0U)
+#define USB_EP0R_EA_Msk (0xFU << USB_EP0R_EA_Pos) /*!< 0x0000000F */
+#define USB_EP0R_EA USB_EP0R_EA_Msk /*!< Endpoint Address */
+
+#define USB_EP0R_STAT_TX_Pos (4U)
+#define USB_EP0R_STAT_TX_Msk (0x3U << USB_EP0R_STAT_TX_Pos) /*!< 0x00000030 */
+#define USB_EP0R_STAT_TX USB_EP0R_STAT_TX_Msk /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */
+#define USB_EP0R_STAT_TX_0 (0x1U << USB_EP0R_STAT_TX_Pos) /*!< 0x00000010 */
+#define USB_EP0R_STAT_TX_1 (0x2U << USB_EP0R_STAT_TX_Pos) /*!< 0x00000020 */
+
+#define USB_EP0R_DTOG_TX_Pos (6U)
+#define USB_EP0R_DTOG_TX_Msk (0x1U << USB_EP0R_DTOG_TX_Pos) /*!< 0x00000040 */
+#define USB_EP0R_DTOG_TX USB_EP0R_DTOG_TX_Msk /*!< Data Toggle, for transmission transfers */
+#define USB_EP0R_CTR_TX_Pos (7U)
+#define USB_EP0R_CTR_TX_Msk (0x1U << USB_EP0R_CTR_TX_Pos) /*!< 0x00000080 */
+#define USB_EP0R_CTR_TX USB_EP0R_CTR_TX_Msk /*!< Correct Transfer for transmission */
+#define USB_EP0R_EP_KIND_Pos (8U)
+#define USB_EP0R_EP_KIND_Msk (0x1U << USB_EP0R_EP_KIND_Pos) /*!< 0x00000100 */
+#define USB_EP0R_EP_KIND USB_EP0R_EP_KIND_Msk /*!< Endpoint Kind */
+
+#define USB_EP0R_EP_TYPE_Pos (9U)
+#define USB_EP0R_EP_TYPE_Msk (0x3U << USB_EP0R_EP_TYPE_Pos) /*!< 0x00000600 */
+#define USB_EP0R_EP_TYPE USB_EP0R_EP_TYPE_Msk /*!< EP_TYPE[1:0] bits (Endpoint type) */
+#define USB_EP0R_EP_TYPE_0 (0x1U << USB_EP0R_EP_TYPE_Pos) /*!< 0x00000200 */
+#define USB_EP0R_EP_TYPE_1 (0x2U << USB_EP0R_EP_TYPE_Pos) /*!< 0x00000400 */
+
+#define USB_EP0R_SETUP_Pos (11U)
+#define USB_EP0R_SETUP_Msk (0x1U << USB_EP0R_SETUP_Pos) /*!< 0x00000800 */
+#define USB_EP0R_SETUP USB_EP0R_SETUP_Msk /*!< Setup transaction completed */
+
+#define USB_EP0R_STAT_RX_Pos (12U)
+#define USB_EP0R_STAT_RX_Msk (0x3U << USB_EP0R_STAT_RX_Pos) /*!< 0x00003000 */
+#define USB_EP0R_STAT_RX USB_EP0R_STAT_RX_Msk /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */
+#define USB_EP0R_STAT_RX_0 (0x1U << USB_EP0R_STAT_RX_Pos) /*!< 0x00001000 */
+#define USB_EP0R_STAT_RX_1 (0x2U << USB_EP0R_STAT_RX_Pos) /*!< 0x00002000 */
+
+#define USB_EP0R_DTOG_RX_Pos (14U)
+#define USB_EP0R_DTOG_RX_Msk (0x1U << USB_EP0R_DTOG_RX_Pos) /*!< 0x00004000 */
+#define USB_EP0R_DTOG_RX USB_EP0R_DTOG_RX_Msk /*!< Data Toggle, for reception transfers */
+#define USB_EP0R_CTR_RX_Pos (15U)
+#define USB_EP0R_CTR_RX_Msk (0x1U << USB_EP0R_CTR_RX_Pos) /*!< 0x00008000 */
+#define USB_EP0R_CTR_RX USB_EP0R_CTR_RX_Msk /*!< Correct Transfer for reception */
+
+/******************* Bit definition for USB_EP1R register *******************/
+#define USB_EP1R_EA_Pos (0U)
+#define USB_EP1R_EA_Msk (0xFU << USB_EP1R_EA_Pos) /*!< 0x0000000F */
+#define USB_EP1R_EA USB_EP1R_EA_Msk /*!< Endpoint Address */
+
+#define USB_EP1R_STAT_TX_Pos (4U)
+#define USB_EP1R_STAT_TX_Msk (0x3U << USB_EP1R_STAT_TX_Pos) /*!< 0x00000030 */
+#define USB_EP1R_STAT_TX USB_EP1R_STAT_TX_Msk /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */
+#define USB_EP1R_STAT_TX_0 (0x1U << USB_EP1R_STAT_TX_Pos) /*!< 0x00000010 */
+#define USB_EP1R_STAT_TX_1 (0x2U << USB_EP1R_STAT_TX_Pos) /*!< 0x00000020 */
+
+#define USB_EP1R_DTOG_TX_Pos (6U)
+#define USB_EP1R_DTOG_TX_Msk (0x1U << USB_EP1R_DTOG_TX_Pos) /*!< 0x00000040 */
+#define USB_EP1R_DTOG_TX USB_EP1R_DTOG_TX_Msk /*!< Data Toggle, for transmission transfers */
+#define USB_EP1R_CTR_TX_Pos (7U)
+#define USB_EP1R_CTR_TX_Msk (0x1U << USB_EP1R_CTR_TX_Pos) /*!< 0x00000080 */
+#define USB_EP1R_CTR_TX USB_EP1R_CTR_TX_Msk /*!< Correct Transfer for transmission */
+#define USB_EP1R_EP_KIND_Pos (8U)
+#define USB_EP1R_EP_KIND_Msk (0x1U << USB_EP1R_EP_KIND_Pos) /*!< 0x00000100 */
+#define USB_EP1R_EP_KIND USB_EP1R_EP_KIND_Msk /*!< Endpoint Kind */
+
+#define USB_EP1R_EP_TYPE_Pos (9U)
+#define USB_EP1R_EP_TYPE_Msk (0x3U << USB_EP1R_EP_TYPE_Pos) /*!< 0x00000600 */
+#define USB_EP1R_EP_TYPE USB_EP1R_EP_TYPE_Msk /*!< EP_TYPE[1:0] bits (Endpoint type) */
+#define USB_EP1R_EP_TYPE_0 (0x1U << USB_EP1R_EP_TYPE_Pos) /*!< 0x00000200 */
+#define USB_EP1R_EP_TYPE_1 (0x2U << USB_EP1R_EP_TYPE_Pos) /*!< 0x00000400 */
+
+#define USB_EP1R_SETUP_Pos (11U)
+#define USB_EP1R_SETUP_Msk (0x1U << USB_EP1R_SETUP_Pos) /*!< 0x00000800 */
+#define USB_EP1R_SETUP USB_EP1R_SETUP_Msk /*!< Setup transaction completed */
+
+#define USB_EP1R_STAT_RX_Pos (12U)
+#define USB_EP1R_STAT_RX_Msk (0x3U << USB_EP1R_STAT_RX_Pos) /*!< 0x00003000 */
+#define USB_EP1R_STAT_RX USB_EP1R_STAT_RX_Msk /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */
+#define USB_EP1R_STAT_RX_0 (0x1U << USB_EP1R_STAT_RX_Pos) /*!< 0x00001000 */
+#define USB_EP1R_STAT_RX_1 (0x2U << USB_EP1R_STAT_RX_Pos) /*!< 0x00002000 */
+
+#define USB_EP1R_DTOG_RX_Pos (14U)
+#define USB_EP1R_DTOG_RX_Msk (0x1U << USB_EP1R_DTOG_RX_Pos) /*!< 0x00004000 */
+#define USB_EP1R_DTOG_RX USB_EP1R_DTOG_RX_Msk /*!< Data Toggle, for reception transfers */
+#define USB_EP1R_CTR_RX_Pos (15U)
+#define USB_EP1R_CTR_RX_Msk (0x1U << USB_EP1R_CTR_RX_Pos) /*!< 0x00008000 */
+#define USB_EP1R_CTR_RX USB_EP1R_CTR_RX_Msk /*!< Correct Transfer for reception */
+
+/******************* Bit definition for USB_EP2R register *******************/
+#define USB_EP2R_EA_Pos (0U)
+#define USB_EP2R_EA_Msk (0xFU << USB_EP2R_EA_Pos) /*!< 0x0000000F */
+#define USB_EP2R_EA USB_EP2R_EA_Msk /*!< Endpoint Address */
+
+#define USB_EP2R_STAT_TX_Pos (4U)
+#define USB_EP2R_STAT_TX_Msk (0x3U << USB_EP2R_STAT_TX_Pos) /*!< 0x00000030 */
+#define USB_EP2R_STAT_TX USB_EP2R_STAT_TX_Msk /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */
+#define USB_EP2R_STAT_TX_0 (0x1U << USB_EP2R_STAT_TX_Pos) /*!< 0x00000010 */
+#define USB_EP2R_STAT_TX_1 (0x2U << USB_EP2R_STAT_TX_Pos) /*!< 0x00000020 */
+
+#define USB_EP2R_DTOG_TX_Pos (6U)
+#define USB_EP2R_DTOG_TX_Msk (0x1U << USB_EP2R_DTOG_TX_Pos) /*!< 0x00000040 */
+#define USB_EP2R_DTOG_TX USB_EP2R_DTOG_TX_Msk /*!< Data Toggle, for transmission transfers */
+#define USB_EP2R_CTR_TX_Pos (7U)
+#define USB_EP2R_CTR_TX_Msk (0x1U << USB_EP2R_CTR_TX_Pos) /*!< 0x00000080 */
+#define USB_EP2R_CTR_TX USB_EP2R_CTR_TX_Msk /*!< Correct Transfer for transmission */
+#define USB_EP2R_EP_KIND_Pos (8U)
+#define USB_EP2R_EP_KIND_Msk (0x1U << USB_EP2R_EP_KIND_Pos) /*!< 0x00000100 */
+#define USB_EP2R_EP_KIND USB_EP2R_EP_KIND_Msk /*!< Endpoint Kind */
+
+#define USB_EP2R_EP_TYPE_Pos (9U)
+#define USB_EP2R_EP_TYPE_Msk (0x3U << USB_EP2R_EP_TYPE_Pos) /*!< 0x00000600 */
+#define USB_EP2R_EP_TYPE USB_EP2R_EP_TYPE_Msk /*!< EP_TYPE[1:0] bits (Endpoint type) */
+#define USB_EP2R_EP_TYPE_0 (0x1U << USB_EP2R_EP_TYPE_Pos) /*!< 0x00000200 */
+#define USB_EP2R_EP_TYPE_1 (0x2U << USB_EP2R_EP_TYPE_Pos) /*!< 0x00000400 */
+
+#define USB_EP2R_SETUP_Pos (11U)
+#define USB_EP2R_SETUP_Msk (0x1U << USB_EP2R_SETUP_Pos) /*!< 0x00000800 */
+#define USB_EP2R_SETUP USB_EP2R_SETUP_Msk /*!< Setup transaction completed */
+
+#define USB_EP2R_STAT_RX_Pos (12U)
+#define USB_EP2R_STAT_RX_Msk (0x3U << USB_EP2R_STAT_RX_Pos) /*!< 0x00003000 */
+#define USB_EP2R_STAT_RX USB_EP2R_STAT_RX_Msk /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */
+#define USB_EP2R_STAT_RX_0 (0x1U << USB_EP2R_STAT_RX_Pos) /*!< 0x00001000 */
+#define USB_EP2R_STAT_RX_1 (0x2U << USB_EP2R_STAT_RX_Pos) /*!< 0x00002000 */
+
+#define USB_EP2R_DTOG_RX_Pos (14U)
+#define USB_EP2R_DTOG_RX_Msk (0x1U << USB_EP2R_DTOG_RX_Pos) /*!< 0x00004000 */
+#define USB_EP2R_DTOG_RX USB_EP2R_DTOG_RX_Msk /*!< Data Toggle, for reception transfers */
+#define USB_EP2R_CTR_RX_Pos (15U)
+#define USB_EP2R_CTR_RX_Msk (0x1U << USB_EP2R_CTR_RX_Pos) /*!< 0x00008000 */
+#define USB_EP2R_CTR_RX USB_EP2R_CTR_RX_Msk /*!< Correct Transfer for reception */
+
+/******************* Bit definition for USB_EP3R register *******************/
+#define USB_EP3R_EA_Pos (0U)
+#define USB_EP3R_EA_Msk (0xFU << USB_EP3R_EA_Pos) /*!< 0x0000000F */
+#define USB_EP3R_EA USB_EP3R_EA_Msk /*!< Endpoint Address */
+
+#define USB_EP3R_STAT_TX_Pos (4U)
+#define USB_EP3R_STAT_TX_Msk (0x3U << USB_EP3R_STAT_TX_Pos) /*!< 0x00000030 */
+#define USB_EP3R_STAT_TX USB_EP3R_STAT_TX_Msk /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */
+#define USB_EP3R_STAT_TX_0 (0x1U << USB_EP3R_STAT_TX_Pos) /*!< 0x00000010 */
+#define USB_EP3R_STAT_TX_1 (0x2U << USB_EP3R_STAT_TX_Pos) /*!< 0x00000020 */
+
+#define USB_EP3R_DTOG_TX_Pos (6U)
+#define USB_EP3R_DTOG_TX_Msk (0x1U << USB_EP3R_DTOG_TX_Pos) /*!< 0x00000040 */
+#define USB_EP3R_DTOG_TX USB_EP3R_DTOG_TX_Msk /*!< Data Toggle, for transmission transfers */
+#define USB_EP3R_CTR_TX_Pos (7U)
+#define USB_EP3R_CTR_TX_Msk (0x1U << USB_EP3R_CTR_TX_Pos) /*!< 0x00000080 */
+#define USB_EP3R_CTR_TX USB_EP3R_CTR_TX_Msk /*!< Correct Transfer for transmission */
+#define USB_EP3R_EP_KIND_Pos (8U)
+#define USB_EP3R_EP_KIND_Msk (0x1U << USB_EP3R_EP_KIND_Pos) /*!< 0x00000100 */
+#define USB_EP3R_EP_KIND USB_EP3R_EP_KIND_Msk /*!< Endpoint Kind */
+
+#define USB_EP3R_EP_TYPE_Pos (9U)
+#define USB_EP3R_EP_TYPE_Msk (0x3U << USB_EP3R_EP_TYPE_Pos) /*!< 0x00000600 */
+#define USB_EP3R_EP_TYPE USB_EP3R_EP_TYPE_Msk /*!< EP_TYPE[1:0] bits (Endpoint type) */
+#define USB_EP3R_EP_TYPE_0 (0x1U << USB_EP3R_EP_TYPE_Pos) /*!< 0x00000200 */
+#define USB_EP3R_EP_TYPE_1 (0x2U << USB_EP3R_EP_TYPE_Pos) /*!< 0x00000400 */
+
+#define USB_EP3R_SETUP_Pos (11U)
+#define USB_EP3R_SETUP_Msk (0x1U << USB_EP3R_SETUP_Pos) /*!< 0x00000800 */
+#define USB_EP3R_SETUP USB_EP3R_SETUP_Msk /*!< Setup transaction completed */
+
+#define USB_EP3R_STAT_RX_Pos (12U)
+#define USB_EP3R_STAT_RX_Msk (0x3U << USB_EP3R_STAT_RX_Pos) /*!< 0x00003000 */
+#define USB_EP3R_STAT_RX USB_EP3R_STAT_RX_Msk /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */
+#define USB_EP3R_STAT_RX_0 (0x1U << USB_EP3R_STAT_RX_Pos) /*!< 0x00001000 */
+#define USB_EP3R_STAT_RX_1 (0x2U << USB_EP3R_STAT_RX_Pos) /*!< 0x00002000 */
+
+#define USB_EP3R_DTOG_RX_Pos (14U)
+#define USB_EP3R_DTOG_RX_Msk (0x1U << USB_EP3R_DTOG_RX_Pos) /*!< 0x00004000 */
+#define USB_EP3R_DTOG_RX USB_EP3R_DTOG_RX_Msk /*!< Data Toggle, for reception transfers */
+#define USB_EP3R_CTR_RX_Pos (15U)
+#define USB_EP3R_CTR_RX_Msk (0x1U << USB_EP3R_CTR_RX_Pos) /*!< 0x00008000 */
+#define USB_EP3R_CTR_RX USB_EP3R_CTR_RX_Msk /*!< Correct Transfer for reception */
+
+/******************* Bit definition for USB_EP4R register *******************/
+#define USB_EP4R_EA_Pos (0U)
+#define USB_EP4R_EA_Msk (0xFU << USB_EP4R_EA_Pos) /*!< 0x0000000F */
+#define USB_EP4R_EA USB_EP4R_EA_Msk /*!< Endpoint Address */
+
+#define USB_EP4R_STAT_TX_Pos (4U)
+#define USB_EP4R_STAT_TX_Msk (0x3U << USB_EP4R_STAT_TX_Pos) /*!< 0x00000030 */
+#define USB_EP4R_STAT_TX USB_EP4R_STAT_TX_Msk /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */
+#define USB_EP4R_STAT_TX_0 (0x1U << USB_EP4R_STAT_TX_Pos) /*!< 0x00000010 */
+#define USB_EP4R_STAT_TX_1 (0x2U << USB_EP4R_STAT_TX_Pos) /*!< 0x00000020 */
+
+#define USB_EP4R_DTOG_TX_Pos (6U)
+#define USB_EP4R_DTOG_TX_Msk (0x1U << USB_EP4R_DTOG_TX_Pos) /*!< 0x00000040 */
+#define USB_EP4R_DTOG_TX USB_EP4R_DTOG_TX_Msk /*!< Data Toggle, for transmission transfers */
+#define USB_EP4R_CTR_TX_Pos (7U)
+#define USB_EP4R_CTR_TX_Msk (0x1U << USB_EP4R_CTR_TX_Pos) /*!< 0x00000080 */
+#define USB_EP4R_CTR_TX USB_EP4R_CTR_TX_Msk /*!< Correct Transfer for transmission */
+#define USB_EP4R_EP_KIND_Pos (8U)
+#define USB_EP4R_EP_KIND_Msk (0x1U << USB_EP4R_EP_KIND_Pos) /*!< 0x00000100 */
+#define USB_EP4R_EP_KIND USB_EP4R_EP_KIND_Msk /*!< Endpoint Kind */
+
+#define USB_EP4R_EP_TYPE_Pos (9U)
+#define USB_EP4R_EP_TYPE_Msk (0x3U << USB_EP4R_EP_TYPE_Pos) /*!< 0x00000600 */
+#define USB_EP4R_EP_TYPE USB_EP4R_EP_TYPE_Msk /*!< EP_TYPE[1:0] bits (Endpoint type) */
+#define USB_EP4R_EP_TYPE_0 (0x1U << USB_EP4R_EP_TYPE_Pos) /*!< 0x00000200 */
+#define USB_EP4R_EP_TYPE_1 (0x2U << USB_EP4R_EP_TYPE_Pos) /*!< 0x00000400 */
+
+#define USB_EP4R_SETUP_Pos (11U)
+#define USB_EP4R_SETUP_Msk (0x1U << USB_EP4R_SETUP_Pos) /*!< 0x00000800 */
+#define USB_EP4R_SETUP USB_EP4R_SETUP_Msk /*!< Setup transaction completed */
+
+#define USB_EP4R_STAT_RX_Pos (12U)
+#define USB_EP4R_STAT_RX_Msk (0x3U << USB_EP4R_STAT_RX_Pos) /*!< 0x00003000 */
+#define USB_EP4R_STAT_RX USB_EP4R_STAT_RX_Msk /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */
+#define USB_EP4R_STAT_RX_0 (0x1U << USB_EP4R_STAT_RX_Pos) /*!< 0x00001000 */
+#define USB_EP4R_STAT_RX_1 (0x2U << USB_EP4R_STAT_RX_Pos) /*!< 0x00002000 */
+
+#define USB_EP4R_DTOG_RX_Pos (14U)
+#define USB_EP4R_DTOG_RX_Msk (0x1U << USB_EP4R_DTOG_RX_Pos) /*!< 0x00004000 */
+#define USB_EP4R_DTOG_RX USB_EP4R_DTOG_RX_Msk /*!< Data Toggle, for reception transfers */
+#define USB_EP4R_CTR_RX_Pos (15U)
+#define USB_EP4R_CTR_RX_Msk (0x1U << USB_EP4R_CTR_RX_Pos) /*!< 0x00008000 */
+#define USB_EP4R_CTR_RX USB_EP4R_CTR_RX_Msk /*!< Correct Transfer for reception */
+
+/******************* Bit definition for USB_EP5R register *******************/
+#define USB_EP5R_EA_Pos (0U)
+#define USB_EP5R_EA_Msk (0xFU << USB_EP5R_EA_Pos) /*!< 0x0000000F */
+#define USB_EP5R_EA USB_EP5R_EA_Msk /*!< Endpoint Address */
+
+#define USB_EP5R_STAT_TX_Pos (4U)
+#define USB_EP5R_STAT_TX_Msk (0x3U << USB_EP5R_STAT_TX_Pos) /*!< 0x00000030 */
+#define USB_EP5R_STAT_TX USB_EP5R_STAT_TX_Msk /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */
+#define USB_EP5R_STAT_TX_0 (0x1U << USB_EP5R_STAT_TX_Pos) /*!< 0x00000010 */
+#define USB_EP5R_STAT_TX_1 (0x2U << USB_EP5R_STAT_TX_Pos) /*!< 0x00000020 */
+
+#define USB_EP5R_DTOG_TX_Pos (6U)
+#define USB_EP5R_DTOG_TX_Msk (0x1U << USB_EP5R_DTOG_TX_Pos) /*!< 0x00000040 */
+#define USB_EP5R_DTOG_TX USB_EP5R_DTOG_TX_Msk /*!< Data Toggle, for transmission transfers */
+#define USB_EP5R_CTR_TX_Pos (7U)
+#define USB_EP5R_CTR_TX_Msk (0x1U << USB_EP5R_CTR_TX_Pos) /*!< 0x00000080 */
+#define USB_EP5R_CTR_TX USB_EP5R_CTR_TX_Msk /*!< Correct Transfer for transmission */
+#define USB_EP5R_EP_KIND_Pos (8U)
+#define USB_EP5R_EP_KIND_Msk (0x1U << USB_EP5R_EP_KIND_Pos) /*!< 0x00000100 */
+#define USB_EP5R_EP_KIND USB_EP5R_EP_KIND_Msk /*!< Endpoint Kind */
+
+#define USB_EP5R_EP_TYPE_Pos (9U)
+#define USB_EP5R_EP_TYPE_Msk (0x3U << USB_EP5R_EP_TYPE_Pos) /*!< 0x00000600 */
+#define USB_EP5R_EP_TYPE USB_EP5R_EP_TYPE_Msk /*!< EP_TYPE[1:0] bits (Endpoint type) */
+#define USB_EP5R_EP_TYPE_0 (0x1U << USB_EP5R_EP_TYPE_Pos) /*!< 0x00000200 */
+#define USB_EP5R_EP_TYPE_1 (0x2U << USB_EP5R_EP_TYPE_Pos) /*!< 0x00000400 */
+
+#define USB_EP5R_SETUP_Pos (11U)
+#define USB_EP5R_SETUP_Msk (0x1U << USB_EP5R_SETUP_Pos) /*!< 0x00000800 */
+#define USB_EP5R_SETUP USB_EP5R_SETUP_Msk /*!< Setup transaction completed */
+
+#define USB_EP5R_STAT_RX_Pos (12U)
+#define USB_EP5R_STAT_RX_Msk (0x3U << USB_EP5R_STAT_RX_Pos) /*!< 0x00003000 */
+#define USB_EP5R_STAT_RX USB_EP5R_STAT_RX_Msk /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */
+#define USB_EP5R_STAT_RX_0 (0x1U << USB_EP5R_STAT_RX_Pos) /*!< 0x00001000 */
+#define USB_EP5R_STAT_RX_1 (0x2U << USB_EP5R_STAT_RX_Pos) /*!< 0x00002000 */
+
+#define USB_EP5R_DTOG_RX_Pos (14U)
+#define USB_EP5R_DTOG_RX_Msk (0x1U << USB_EP5R_DTOG_RX_Pos) /*!< 0x00004000 */
+#define USB_EP5R_DTOG_RX USB_EP5R_DTOG_RX_Msk /*!< Data Toggle, for reception transfers */
+#define USB_EP5R_CTR_RX_Pos (15U)
+#define USB_EP5R_CTR_RX_Msk (0x1U << USB_EP5R_CTR_RX_Pos) /*!< 0x00008000 */
+#define USB_EP5R_CTR_RX USB_EP5R_CTR_RX_Msk /*!< Correct Transfer for reception */
+
+/******************* Bit definition for USB_EP6R register *******************/
+#define USB_EP6R_EA_Pos (0U)
+#define USB_EP6R_EA_Msk (0xFU << USB_EP6R_EA_Pos) /*!< 0x0000000F */
+#define USB_EP6R_EA USB_EP6R_EA_Msk /*!< Endpoint Address */
+
+#define USB_EP6R_STAT_TX_Pos (4U)
+#define USB_EP6R_STAT_TX_Msk (0x3U << USB_EP6R_STAT_TX_Pos) /*!< 0x00000030 */
+#define USB_EP6R_STAT_TX USB_EP6R_STAT_TX_Msk /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */
+#define USB_EP6R_STAT_TX_0 (0x1U << USB_EP6R_STAT_TX_Pos) /*!< 0x00000010 */
+#define USB_EP6R_STAT_TX_1 (0x2U << USB_EP6R_STAT_TX_Pos) /*!< 0x00000020 */
+
+#define USB_EP6R_DTOG_TX_Pos (6U)
+#define USB_EP6R_DTOG_TX_Msk (0x1U << USB_EP6R_DTOG_TX_Pos) /*!< 0x00000040 */
+#define USB_EP6R_DTOG_TX USB_EP6R_DTOG_TX_Msk /*!< Data Toggle, for transmission transfers */
+#define USB_EP6R_CTR_TX_Pos (7U)
+#define USB_EP6R_CTR_TX_Msk (0x1U << USB_EP6R_CTR_TX_Pos) /*!< 0x00000080 */
+#define USB_EP6R_CTR_TX USB_EP6R_CTR_TX_Msk /*!< Correct Transfer for transmission */
+#define USB_EP6R_EP_KIND_Pos (8U)
+#define USB_EP6R_EP_KIND_Msk (0x1U << USB_EP6R_EP_KIND_Pos) /*!< 0x00000100 */
+#define USB_EP6R_EP_KIND USB_EP6R_EP_KIND_Msk /*!< Endpoint Kind */
+
+#define USB_EP6R_EP_TYPE_Pos (9U)
+#define USB_EP6R_EP_TYPE_Msk (0x3U << USB_EP6R_EP_TYPE_Pos) /*!< 0x00000600 */
+#define USB_EP6R_EP_TYPE USB_EP6R_EP_TYPE_Msk /*!< EP_TYPE[1:0] bits (Endpoint type) */
+#define USB_EP6R_EP_TYPE_0 (0x1U << USB_EP6R_EP_TYPE_Pos) /*!< 0x00000200 */
+#define USB_EP6R_EP_TYPE_1 (0x2U << USB_EP6R_EP_TYPE_Pos) /*!< 0x00000400 */
+
+#define USB_EP6R_SETUP_Pos (11U)
+#define USB_EP6R_SETUP_Msk (0x1U << USB_EP6R_SETUP_Pos) /*!< 0x00000800 */
+#define USB_EP6R_SETUP USB_EP6R_SETUP_Msk /*!< Setup transaction completed */
+
+#define USB_EP6R_STAT_RX_Pos (12U)
+#define USB_EP6R_STAT_RX_Msk (0x3U << USB_EP6R_STAT_RX_Pos) /*!< 0x00003000 */
+#define USB_EP6R_STAT_RX USB_EP6R_STAT_RX_Msk /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */
+#define USB_EP6R_STAT_RX_0 (0x1U << USB_EP6R_STAT_RX_Pos) /*!< 0x00001000 */
+#define USB_EP6R_STAT_RX_1 (0x2U << USB_EP6R_STAT_RX_Pos) /*!< 0x00002000 */
+
+#define USB_EP6R_DTOG_RX_Pos (14U)
+#define USB_EP6R_DTOG_RX_Msk (0x1U << USB_EP6R_DTOG_RX_Pos) /*!< 0x00004000 */
+#define USB_EP6R_DTOG_RX USB_EP6R_DTOG_RX_Msk /*!< Data Toggle, for reception transfers */
+#define USB_EP6R_CTR_RX_Pos (15U)
+#define USB_EP6R_CTR_RX_Msk (0x1U << USB_EP6R_CTR_RX_Pos) /*!< 0x00008000 */
+#define USB_EP6R_CTR_RX USB_EP6R_CTR_RX_Msk /*!< Correct Transfer for reception */
+
+/******************* Bit definition for USB_EP7R register *******************/
+#define USB_EP7R_EA_Pos (0U)
+#define USB_EP7R_EA_Msk (0xFU << USB_EP7R_EA_Pos) /*!< 0x0000000F */
+#define USB_EP7R_EA USB_EP7R_EA_Msk /*!< Endpoint Address */
+
+#define USB_EP7R_STAT_TX_Pos (4U)
+#define USB_EP7R_STAT_TX_Msk (0x3U << USB_EP7R_STAT_TX_Pos) /*!< 0x00000030 */
+#define USB_EP7R_STAT_TX USB_EP7R_STAT_TX_Msk /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */
+#define USB_EP7R_STAT_TX_0 (0x1U << USB_EP7R_STAT_TX_Pos) /*!< 0x00000010 */
+#define USB_EP7R_STAT_TX_1 (0x2U << USB_EP7R_STAT_TX_Pos) /*!< 0x00000020 */
+
+#define USB_EP7R_DTOG_TX_Pos (6U)
+#define USB_EP7R_DTOG_TX_Msk (0x1U << USB_EP7R_DTOG_TX_Pos) /*!< 0x00000040 */
+#define USB_EP7R_DTOG_TX USB_EP7R_DTOG_TX_Msk /*!< Data Toggle, for transmission transfers */
+#define USB_EP7R_CTR_TX_Pos (7U)
+#define USB_EP7R_CTR_TX_Msk (0x1U << USB_EP7R_CTR_TX_Pos) /*!< 0x00000080 */
+#define USB_EP7R_CTR_TX USB_EP7R_CTR_TX_Msk /*!< Correct Transfer for transmission */
+#define USB_EP7R_EP_KIND_Pos (8U)
+#define USB_EP7R_EP_KIND_Msk (0x1U << USB_EP7R_EP_KIND_Pos) /*!< 0x00000100 */
+#define USB_EP7R_EP_KIND USB_EP7R_EP_KIND_Msk /*!< Endpoint Kind */
+
+#define USB_EP7R_EP_TYPE_Pos (9U)
+#define USB_EP7R_EP_TYPE_Msk (0x3U << USB_EP7R_EP_TYPE_Pos) /*!< 0x00000600 */
+#define USB_EP7R_EP_TYPE USB_EP7R_EP_TYPE_Msk /*!< EP_TYPE[1:0] bits (Endpoint type) */
+#define USB_EP7R_EP_TYPE_0 (0x1U << USB_EP7R_EP_TYPE_Pos) /*!< 0x00000200 */
+#define USB_EP7R_EP_TYPE_1 (0x2U << USB_EP7R_EP_TYPE_Pos) /*!< 0x00000400 */
+
+#define USB_EP7R_SETUP_Pos (11U)
+#define USB_EP7R_SETUP_Msk (0x1U << USB_EP7R_SETUP_Pos) /*!< 0x00000800 */
+#define USB_EP7R_SETUP USB_EP7R_SETUP_Msk /*!< Setup transaction completed */
+
+#define USB_EP7R_STAT_RX_Pos (12U)
+#define USB_EP7R_STAT_RX_Msk (0x3U << USB_EP7R_STAT_RX_Pos) /*!< 0x00003000 */
+#define USB_EP7R_STAT_RX USB_EP7R_STAT_RX_Msk /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */
+#define USB_EP7R_STAT_RX_0 (0x1U << USB_EP7R_STAT_RX_Pos) /*!< 0x00001000 */
+#define USB_EP7R_STAT_RX_1 (0x2U << USB_EP7R_STAT_RX_Pos) /*!< 0x00002000 */
+
+#define USB_EP7R_DTOG_RX_Pos (14U)
+#define USB_EP7R_DTOG_RX_Msk (0x1U << USB_EP7R_DTOG_RX_Pos) /*!< 0x00004000 */
+#define USB_EP7R_DTOG_RX USB_EP7R_DTOG_RX_Msk /*!< Data Toggle, for reception transfers */
+#define USB_EP7R_CTR_RX_Pos (15U)
+#define USB_EP7R_CTR_RX_Msk (0x1U << USB_EP7R_CTR_RX_Pos) /*!< 0x00008000 */
+#define USB_EP7R_CTR_RX USB_EP7R_CTR_RX_Msk /*!< Correct Transfer for reception */
+
+/*!< Common registers */
+/******************* Bit definition for USB_CNTR register *******************/
+#define USB_CNTR_FRES_Pos (0U)
+#define USB_CNTR_FRES_Msk (0x1U << USB_CNTR_FRES_Pos) /*!< 0x00000001 */
+#define USB_CNTR_FRES USB_CNTR_FRES_Msk /*!< Force USB Reset */
+#define USB_CNTR_PDWN_Pos (1U)
+#define USB_CNTR_PDWN_Msk (0x1U << USB_CNTR_PDWN_Pos) /*!< 0x00000002 */
+#define USB_CNTR_PDWN USB_CNTR_PDWN_Msk /*!< Power down */
+#define USB_CNTR_LP_MODE_Pos (2U)
+#define USB_CNTR_LP_MODE_Msk (0x1U << USB_CNTR_LP_MODE_Pos) /*!< 0x00000004 */
+#define USB_CNTR_LP_MODE USB_CNTR_LP_MODE_Msk /*!< Low-power mode */
+#define USB_CNTR_FSUSP_Pos (3U)
+#define USB_CNTR_FSUSP_Msk (0x1U << USB_CNTR_FSUSP_Pos) /*!< 0x00000008 */
+#define USB_CNTR_FSUSP USB_CNTR_FSUSP_Msk /*!< Force suspend */
+#define USB_CNTR_RESUME_Pos (4U)
+#define USB_CNTR_RESUME_Msk (0x1U << USB_CNTR_RESUME_Pos) /*!< 0x00000010 */
+#define USB_CNTR_RESUME USB_CNTR_RESUME_Msk /*!< Resume request */
+#define USB_CNTR_ESOFM_Pos (8U)
+#define USB_CNTR_ESOFM_Msk (0x1U << USB_CNTR_ESOFM_Pos) /*!< 0x00000100 */
+#define USB_CNTR_ESOFM USB_CNTR_ESOFM_Msk /*!< Expected Start Of Frame Interrupt Mask */
+#define USB_CNTR_SOFM_Pos (9U)
+#define USB_CNTR_SOFM_Msk (0x1U << USB_CNTR_SOFM_Pos) /*!< 0x00000200 */
+#define USB_CNTR_SOFM USB_CNTR_SOFM_Msk /*!< Start Of Frame Interrupt Mask */
+#define USB_CNTR_RESETM_Pos (10U)
+#define USB_CNTR_RESETM_Msk (0x1U << USB_CNTR_RESETM_Pos) /*!< 0x00000400 */
+#define USB_CNTR_RESETM USB_CNTR_RESETM_Msk /*!< RESET Interrupt Mask */
+#define USB_CNTR_SUSPM_Pos (11U)
+#define USB_CNTR_SUSPM_Msk (0x1U << USB_CNTR_SUSPM_Pos) /*!< 0x00000800 */
+#define USB_CNTR_SUSPM USB_CNTR_SUSPM_Msk /*!< Suspend mode Interrupt Mask */
+#define USB_CNTR_WKUPM_Pos (12U)
+#define USB_CNTR_WKUPM_Msk (0x1U << USB_CNTR_WKUPM_Pos) /*!< 0x00001000 */
+#define USB_CNTR_WKUPM USB_CNTR_WKUPM_Msk /*!< Wakeup Interrupt Mask */
+#define USB_CNTR_ERRM_Pos (13U)
+#define USB_CNTR_ERRM_Msk (0x1U << USB_CNTR_ERRM_Pos) /*!< 0x00002000 */
+#define USB_CNTR_ERRM USB_CNTR_ERRM_Msk /*!< Error Interrupt Mask */
+#define USB_CNTR_PMAOVRM_Pos (14U)
+#define USB_CNTR_PMAOVRM_Msk (0x1U << USB_CNTR_PMAOVRM_Pos) /*!< 0x00004000 */
+#define USB_CNTR_PMAOVRM USB_CNTR_PMAOVRM_Msk /*!< Packet Memory Area Over / Underrun Interrupt Mask */
+#define USB_CNTR_CTRM_Pos (15U)
+#define USB_CNTR_CTRM_Msk (0x1U << USB_CNTR_CTRM_Pos) /*!< 0x00008000 */
+#define USB_CNTR_CTRM USB_CNTR_CTRM_Msk /*!< Correct Transfer Interrupt Mask */
+
+/******************* Bit definition for USB_ISTR register *******************/
+#define USB_ISTR_EP_ID_Pos (0U)
+#define USB_ISTR_EP_ID_Msk (0xFU << USB_ISTR_EP_ID_Pos) /*!< 0x0000000F */
+#define USB_ISTR_EP_ID USB_ISTR_EP_ID_Msk /*!< Endpoint Identifier */
+#define USB_ISTR_DIR_Pos (4U)
+#define USB_ISTR_DIR_Msk (0x1U << USB_ISTR_DIR_Pos) /*!< 0x00000010 */
+#define USB_ISTR_DIR USB_ISTR_DIR_Msk /*!< Direction of transaction */
+#define USB_ISTR_ESOF_Pos (8U)
+#define USB_ISTR_ESOF_Msk (0x1U << USB_ISTR_ESOF_Pos) /*!< 0x00000100 */
+#define USB_ISTR_ESOF USB_ISTR_ESOF_Msk /*!< Expected Start Of Frame */
+#define USB_ISTR_SOF_Pos (9U)
+#define USB_ISTR_SOF_Msk (0x1U << USB_ISTR_SOF_Pos) /*!< 0x00000200 */
+#define USB_ISTR_SOF USB_ISTR_SOF_Msk /*!< Start Of Frame */
+#define USB_ISTR_RESET_Pos (10U)
+#define USB_ISTR_RESET_Msk (0x1U << USB_ISTR_RESET_Pos) /*!< 0x00000400 */
+#define USB_ISTR_RESET USB_ISTR_RESET_Msk /*!< USB RESET request */
+#define USB_ISTR_SUSP_Pos (11U)
+#define USB_ISTR_SUSP_Msk (0x1U << USB_ISTR_SUSP_Pos) /*!< 0x00000800 */
+#define USB_ISTR_SUSP USB_ISTR_SUSP_Msk /*!< Suspend mode request */
+#define USB_ISTR_WKUP_Pos (12U)
+#define USB_ISTR_WKUP_Msk (0x1U << USB_ISTR_WKUP_Pos) /*!< 0x00001000 */
+#define USB_ISTR_WKUP USB_ISTR_WKUP_Msk /*!< Wake up */
+#define USB_ISTR_ERR_Pos (13U)
+#define USB_ISTR_ERR_Msk (0x1U << USB_ISTR_ERR_Pos) /*!< 0x00002000 */
+#define USB_ISTR_ERR USB_ISTR_ERR_Msk /*!< Error */
+#define USB_ISTR_PMAOVR_Pos (14U)
+#define USB_ISTR_PMAOVR_Msk (0x1U << USB_ISTR_PMAOVR_Pos) /*!< 0x00004000 */
+#define USB_ISTR_PMAOVR USB_ISTR_PMAOVR_Msk /*!< Packet Memory Area Over / Underrun */
+#define USB_ISTR_CTR_Pos (15U)
+#define USB_ISTR_CTR_Msk (0x1U << USB_ISTR_CTR_Pos) /*!< 0x00008000 */
+#define USB_ISTR_CTR USB_ISTR_CTR_Msk /*!< Correct Transfer */
+
+/******************* Bit definition for USB_FNR register ********************/
+#define USB_FNR_FN_Pos (0U)
+#define USB_FNR_FN_Msk (0x7FFU << USB_FNR_FN_Pos) /*!< 0x000007FF */
+#define USB_FNR_FN USB_FNR_FN_Msk /*!< Frame Number */
+#define USB_FNR_LSOF_Pos (11U)
+#define USB_FNR_LSOF_Msk (0x3U << USB_FNR_LSOF_Pos) /*!< 0x00001800 */
+#define USB_FNR_LSOF USB_FNR_LSOF_Msk /*!< Lost SOF */
+#define USB_FNR_LCK_Pos (13U)
+#define USB_FNR_LCK_Msk (0x1U << USB_FNR_LCK_Pos) /*!< 0x00002000 */
+#define USB_FNR_LCK USB_FNR_LCK_Msk /*!< Locked */
+#define USB_FNR_RXDM_Pos (14U)
+#define USB_FNR_RXDM_Msk (0x1U << USB_FNR_RXDM_Pos) /*!< 0x00004000 */
+#define USB_FNR_RXDM USB_FNR_RXDM_Msk /*!< Receive Data - Line Status */
+#define USB_FNR_RXDP_Pos (15U)
+#define USB_FNR_RXDP_Msk (0x1U << USB_FNR_RXDP_Pos) /*!< 0x00008000 */
+#define USB_FNR_RXDP USB_FNR_RXDP_Msk /*!< Receive Data + Line Status */
+
+/****************** Bit definition for USB_DADDR register *******************/
+#define USB_DADDR_ADD_Pos (0U)
+#define USB_DADDR_ADD_Msk (0x7FU << USB_DADDR_ADD_Pos) /*!< 0x0000007F */
+#define USB_DADDR_ADD USB_DADDR_ADD_Msk /*!< ADD[6:0] bits (Device Address) */
+#define USB_DADDR_ADD0_Pos (0U)
+#define USB_DADDR_ADD0_Msk (0x1U << USB_DADDR_ADD0_Pos) /*!< 0x00000001 */
+#define USB_DADDR_ADD0 USB_DADDR_ADD0_Msk /*!< Bit 0 */
+#define USB_DADDR_ADD1_Pos (1U)
+#define USB_DADDR_ADD1_Msk (0x1U << USB_DADDR_ADD1_Pos) /*!< 0x00000002 */
+#define USB_DADDR_ADD1 USB_DADDR_ADD1_Msk /*!< Bit 1 */
+#define USB_DADDR_ADD2_Pos (2U)
+#define USB_DADDR_ADD2_Msk (0x1U << USB_DADDR_ADD2_Pos) /*!< 0x00000004 */
+#define USB_DADDR_ADD2 USB_DADDR_ADD2_Msk /*!< Bit 2 */
+#define USB_DADDR_ADD3_Pos (3U)
+#define USB_DADDR_ADD3_Msk (0x1U << USB_DADDR_ADD3_Pos) /*!< 0x00000008 */
+#define USB_DADDR_ADD3 USB_DADDR_ADD3_Msk /*!< Bit 3 */
+#define USB_DADDR_ADD4_Pos (4U)
+#define USB_DADDR_ADD4_Msk (0x1U << USB_DADDR_ADD4_Pos) /*!< 0x00000010 */
+#define USB_DADDR_ADD4 USB_DADDR_ADD4_Msk /*!< Bit 4 */
+#define USB_DADDR_ADD5_Pos (5U)
+#define USB_DADDR_ADD5_Msk (0x1U << USB_DADDR_ADD5_Pos) /*!< 0x00000020 */
+#define USB_DADDR_ADD5 USB_DADDR_ADD5_Msk /*!< Bit 5 */
+#define USB_DADDR_ADD6_Pos (6U)
+#define USB_DADDR_ADD6_Msk (0x1U << USB_DADDR_ADD6_Pos) /*!< 0x00000040 */
+#define USB_DADDR_ADD6 USB_DADDR_ADD6_Msk /*!< Bit 6 */
+
+#define USB_DADDR_EF_Pos (7U)
+#define USB_DADDR_EF_Msk (0x1U << USB_DADDR_EF_Pos) /*!< 0x00000080 */
+#define USB_DADDR_EF USB_DADDR_EF_Msk /*!< Enable Function */
+
+/****************** Bit definition for USB_BTABLE register ******************/
+#define USB_BTABLE_BTABLE_Pos (3U)
+#define USB_BTABLE_BTABLE_Msk (0x1FFFU << USB_BTABLE_BTABLE_Pos) /*!< 0x0000FFF8 */
+#define USB_BTABLE_BTABLE USB_BTABLE_BTABLE_Msk /*!< Buffer Table */
+
+/*!< Buffer descriptor table */
+/***************** Bit definition for USB_ADDR0_TX register *****************/
+#define USB_ADDR0_TX_ADDR0_TX_Pos (1U)
+#define USB_ADDR0_TX_ADDR0_TX_Msk (0x7FFFU << USB_ADDR0_TX_ADDR0_TX_Pos) /*!< 0x0000FFFE */
+#define USB_ADDR0_TX_ADDR0_TX USB_ADDR0_TX_ADDR0_TX_Msk /*!< Transmission Buffer Address 0 */
+
+/***************** Bit definition for USB_ADDR1_TX register *****************/
+#define USB_ADDR1_TX_ADDR1_TX_Pos (1U)
+#define USB_ADDR1_TX_ADDR1_TX_Msk (0x7FFFU << USB_ADDR1_TX_ADDR1_TX_Pos) /*!< 0x0000FFFE */
+#define USB_ADDR1_TX_ADDR1_TX USB_ADDR1_TX_ADDR1_TX_Msk /*!< Transmission Buffer Address 1 */
+
+/***************** Bit definition for USB_ADDR2_TX register *****************/
+#define USB_ADDR2_TX_ADDR2_TX_Pos (1U)
+#define USB_ADDR2_TX_ADDR2_TX_Msk (0x7FFFU << USB_ADDR2_TX_ADDR2_TX_Pos) /*!< 0x0000FFFE */
+#define USB_ADDR2_TX_ADDR2_TX USB_ADDR2_TX_ADDR2_TX_Msk /*!< Transmission Buffer Address 2 */
+
+/***************** Bit definition for USB_ADDR3_TX register *****************/
+#define USB_ADDR3_TX_ADDR3_TX_Pos (1U)
+#define USB_ADDR3_TX_ADDR3_TX_Msk (0x7FFFU << USB_ADDR3_TX_ADDR3_TX_Pos) /*!< 0x0000FFFE */
+#define USB_ADDR3_TX_ADDR3_TX USB_ADDR3_TX_ADDR3_TX_Msk /*!< Transmission Buffer Address 3 */
+
+/***************** Bit definition for USB_ADDR4_TX register *****************/
+#define USB_ADDR4_TX_ADDR4_TX_Pos (1U)
+#define USB_ADDR4_TX_ADDR4_TX_Msk (0x7FFFU << USB_ADDR4_TX_ADDR4_TX_Pos) /*!< 0x0000FFFE */
+#define USB_ADDR4_TX_ADDR4_TX USB_ADDR4_TX_ADDR4_TX_Msk /*!< Transmission Buffer Address 4 */
+
+/***************** Bit definition for USB_ADDR5_TX register *****************/
+#define USB_ADDR5_TX_ADDR5_TX_Pos (1U)
+#define USB_ADDR5_TX_ADDR5_TX_Msk (0x7FFFU << USB_ADDR5_TX_ADDR5_TX_Pos) /*!< 0x0000FFFE */
+#define USB_ADDR5_TX_ADDR5_TX USB_ADDR5_TX_ADDR5_TX_Msk /*!< Transmission Buffer Address 5 */
+
+/***************** Bit definition for USB_ADDR6_TX register *****************/
+#define USB_ADDR6_TX_ADDR6_TX_Pos (1U)
+#define USB_ADDR6_TX_ADDR6_TX_Msk (0x7FFFU << USB_ADDR6_TX_ADDR6_TX_Pos) /*!< 0x0000FFFE */
+#define USB_ADDR6_TX_ADDR6_TX USB_ADDR6_TX_ADDR6_TX_Msk /*!< Transmission Buffer Address 6 */
+
+/***************** Bit definition for USB_ADDR7_TX register *****************/
+#define USB_ADDR7_TX_ADDR7_TX_Pos (1U)
+#define USB_ADDR7_TX_ADDR7_TX_Msk (0x7FFFU << USB_ADDR7_TX_ADDR7_TX_Pos) /*!< 0x0000FFFE */
+#define USB_ADDR7_TX_ADDR7_TX USB_ADDR7_TX_ADDR7_TX_Msk /*!< Transmission Buffer Address 7 */
+
+/*----------------------------------------------------------------------------*/
+
+/***************** Bit definition for USB_COUNT0_TX register ****************/
+#define USB_COUNT0_TX_COUNT0_TX_Pos (0U)
+#define USB_COUNT0_TX_COUNT0_TX_Msk (0x3FFU << USB_COUNT0_TX_COUNT0_TX_Pos) /*!< 0x000003FF */
+#define USB_COUNT0_TX_COUNT0_TX USB_COUNT0_TX_COUNT0_TX_Msk /*!< Transmission Byte Count 0 */
+
+/***************** Bit definition for USB_COUNT1_TX register ****************/
+#define USB_COUNT1_TX_COUNT1_TX_Pos (0U)
+#define USB_COUNT1_TX_COUNT1_TX_Msk (0x3FFU << USB_COUNT1_TX_COUNT1_TX_Pos) /*!< 0x000003FF */
+#define USB_COUNT1_TX_COUNT1_TX USB_COUNT1_TX_COUNT1_TX_Msk /*!< Transmission Byte Count 1 */
+
+/***************** Bit definition for USB_COUNT2_TX register ****************/
+#define USB_COUNT2_TX_COUNT2_TX_Pos (0U)
+#define USB_COUNT2_TX_COUNT2_TX_Msk (0x3FFU << USB_COUNT2_TX_COUNT2_TX_Pos) /*!< 0x000003FF */
+#define USB_COUNT2_TX_COUNT2_TX USB_COUNT2_TX_COUNT2_TX_Msk /*!< Transmission Byte Count 2 */
+
+/***************** Bit definition for USB_COUNT3_TX register ****************/
+#define USB_COUNT3_TX_COUNT3_TX_Pos (0U)
+#define USB_COUNT3_TX_COUNT3_TX_Msk (0x3FFU << USB_COUNT3_TX_COUNT3_TX_Pos) /*!< 0x000003FF */
+#define USB_COUNT3_TX_COUNT3_TX USB_COUNT3_TX_COUNT3_TX_Msk /*!< Transmission Byte Count 3 */
+
+/***************** Bit definition for USB_COUNT4_TX register ****************/
+#define USB_COUNT4_TX_COUNT4_TX_Pos (0U)
+#define USB_COUNT4_TX_COUNT4_TX_Msk (0x3FFU << USB_COUNT4_TX_COUNT4_TX_Pos) /*!< 0x000003FF */
+#define USB_COUNT4_TX_COUNT4_TX USB_COUNT4_TX_COUNT4_TX_Msk /*!< Transmission Byte Count 4 */
+
+/***************** Bit definition for USB_COUNT5_TX register ****************/
+#define USB_COUNT5_TX_COUNT5_TX_Pos (0U)
+#define USB_COUNT5_TX_COUNT5_TX_Msk (0x3FFU << USB_COUNT5_TX_COUNT5_TX_Pos) /*!< 0x000003FF */
+#define USB_COUNT5_TX_COUNT5_TX USB_COUNT5_TX_COUNT5_TX_Msk /*!< Transmission Byte Count 5 */
+
+/***************** Bit definition for USB_COUNT6_TX register ****************/
+#define USB_COUNT6_TX_COUNT6_TX_Pos (0U)
+#define USB_COUNT6_TX_COUNT6_TX_Msk (0x3FFU << USB_COUNT6_TX_COUNT6_TX_Pos) /*!< 0x000003FF */
+#define USB_COUNT6_TX_COUNT6_TX USB_COUNT6_TX_COUNT6_TX_Msk /*!< Transmission Byte Count 6 */
+
+/***************** Bit definition for USB_COUNT7_TX register ****************/
+#define USB_COUNT7_TX_COUNT7_TX_Pos (0U)
+#define USB_COUNT7_TX_COUNT7_TX_Msk (0x3FFU << USB_COUNT7_TX_COUNT7_TX_Pos) /*!< 0x000003FF */
+#define USB_COUNT7_TX_COUNT7_TX USB_COUNT7_TX_COUNT7_TX_Msk /*!< Transmission Byte Count 7 */
+
+/*----------------------------------------------------------------------------*/
+
+/**************** Bit definition for USB_COUNT0_TX_0 register ***************/
+#define USB_COUNT0_TX_0_COUNT0_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 0 (low) */
+
+/**************** Bit definition for USB_COUNT0_TX_1 register ***************/
+#define USB_COUNT0_TX_1_COUNT0_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 0 (high) */
+
+/**************** Bit definition for USB_COUNT1_TX_0 register ***************/
+#define USB_COUNT1_TX_0_COUNT1_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 1 (low) */
+
+/**************** Bit definition for USB_COUNT1_TX_1 register ***************/
+#define USB_COUNT1_TX_1_COUNT1_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 1 (high) */
+
+/**************** Bit definition for USB_COUNT2_TX_0 register ***************/
+#define USB_COUNT2_TX_0_COUNT2_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 2 (low) */
+
+/**************** Bit definition for USB_COUNT2_TX_1 register ***************/
+#define USB_COUNT2_TX_1_COUNT2_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 2 (high) */
+
+/**************** Bit definition for USB_COUNT3_TX_0 register ***************/
+#define USB_COUNT3_TX_0_COUNT3_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 3 (low) */
+
+/**************** Bit definition for USB_COUNT3_TX_1 register ***************/
+#define USB_COUNT3_TX_1_COUNT3_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 3 (high) */
+
+/**************** Bit definition for USB_COUNT4_TX_0 register ***************/
+#define USB_COUNT4_TX_0_COUNT4_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 4 (low) */
+
+/**************** Bit definition for USB_COUNT4_TX_1 register ***************/
+#define USB_COUNT4_TX_1_COUNT4_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 4 (high) */
+
+/**************** Bit definition for USB_COUNT5_TX_0 register ***************/
+#define USB_COUNT5_TX_0_COUNT5_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 5 (low) */
+
+/**************** Bit definition for USB_COUNT5_TX_1 register ***************/
+#define USB_COUNT5_TX_1_COUNT5_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 5 (high) */
+
+/**************** Bit definition for USB_COUNT6_TX_0 register ***************/
+#define USB_COUNT6_TX_0_COUNT6_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 6 (low) */
+
+/**************** Bit definition for USB_COUNT6_TX_1 register ***************/
+#define USB_COUNT6_TX_1_COUNT6_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 6 (high) */
+
+/**************** Bit definition for USB_COUNT7_TX_0 register ***************/
+#define USB_COUNT7_TX_0_COUNT7_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 7 (low) */
+
+/**************** Bit definition for USB_COUNT7_TX_1 register ***************/
+#define USB_COUNT7_TX_1_COUNT7_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 7 (high) */
+
+/*----------------------------------------------------------------------------*/
+
+/***************** Bit definition for USB_ADDR0_RX register *****************/
+#define USB_ADDR0_RX_ADDR0_RX_Pos (1U)
+#define USB_ADDR0_RX_ADDR0_RX_Msk (0x7FFFU << USB_ADDR0_RX_ADDR0_RX_Pos) /*!< 0x0000FFFE */
+#define USB_ADDR0_RX_ADDR0_RX USB_ADDR0_RX_ADDR0_RX_Msk /*!< Reception Buffer Address 0 */
+
+/***************** Bit definition for USB_ADDR1_RX register *****************/
+#define USB_ADDR1_RX_ADDR1_RX_Pos (1U)
+#define USB_ADDR1_RX_ADDR1_RX_Msk (0x7FFFU << USB_ADDR1_RX_ADDR1_RX_Pos) /*!< 0x0000FFFE */
+#define USB_ADDR1_RX_ADDR1_RX USB_ADDR1_RX_ADDR1_RX_Msk /*!< Reception Buffer Address 1 */
+
+/***************** Bit definition for USB_ADDR2_RX register *****************/
+#define USB_ADDR2_RX_ADDR2_RX_Pos (1U)
+#define USB_ADDR2_RX_ADDR2_RX_Msk (0x7FFFU << USB_ADDR2_RX_ADDR2_RX_Pos) /*!< 0x0000FFFE */
+#define USB_ADDR2_RX_ADDR2_RX USB_ADDR2_RX_ADDR2_RX_Msk /*!< Reception Buffer Address 2 */
+
+/***************** Bit definition for USB_ADDR3_RX register *****************/
+#define USB_ADDR3_RX_ADDR3_RX_Pos (1U)
+#define USB_ADDR3_RX_ADDR3_RX_Msk (0x7FFFU << USB_ADDR3_RX_ADDR3_RX_Pos) /*!< 0x0000FFFE */
+#define USB_ADDR3_RX_ADDR3_RX USB_ADDR3_RX_ADDR3_RX_Msk /*!< Reception Buffer Address 3 */
+
+/***************** Bit definition for USB_ADDR4_RX register *****************/
+#define USB_ADDR4_RX_ADDR4_RX_Pos (1U)
+#define USB_ADDR4_RX_ADDR4_RX_Msk (0x7FFFU << USB_ADDR4_RX_ADDR4_RX_Pos) /*!< 0x0000FFFE */
+#define USB_ADDR4_RX_ADDR4_RX USB_ADDR4_RX_ADDR4_RX_Msk /*!< Reception Buffer Address 4 */
+
+/***************** Bit definition for USB_ADDR5_RX register *****************/
+#define USB_ADDR5_RX_ADDR5_RX_Pos (1U)
+#define USB_ADDR5_RX_ADDR5_RX_Msk (0x7FFFU << USB_ADDR5_RX_ADDR5_RX_Pos) /*!< 0x0000FFFE */
+#define USB_ADDR5_RX_ADDR5_RX USB_ADDR5_RX_ADDR5_RX_Msk /*!< Reception Buffer Address 5 */
+
+/***************** Bit definition for USB_ADDR6_RX register *****************/
+#define USB_ADDR6_RX_ADDR6_RX_Pos (1U)
+#define USB_ADDR6_RX_ADDR6_RX_Msk (0x7FFFU << USB_ADDR6_RX_ADDR6_RX_Pos) /*!< 0x0000FFFE */
+#define USB_ADDR6_RX_ADDR6_RX USB_ADDR6_RX_ADDR6_RX_Msk /*!< Reception Buffer Address 6 */
+
+/***************** Bit definition for USB_ADDR7_RX register *****************/
+#define USB_ADDR7_RX_ADDR7_RX_Pos (1U)
+#define USB_ADDR7_RX_ADDR7_RX_Msk (0x7FFFU << USB_ADDR7_RX_ADDR7_RX_Pos) /*!< 0x0000FFFE */
+#define USB_ADDR7_RX_ADDR7_RX USB_ADDR7_RX_ADDR7_RX_Msk /*!< Reception Buffer Address 7 */
+
+/*----------------------------------------------------------------------------*/
+
+/***************** Bit definition for USB_COUNT0_RX register ****************/
+#define USB_COUNT0_RX_COUNT0_RX_Pos (0U)
+#define USB_COUNT0_RX_COUNT0_RX_Msk (0x3FFU << USB_COUNT0_RX_COUNT0_RX_Pos) /*!< 0x000003FF */
+#define USB_COUNT0_RX_COUNT0_RX USB_COUNT0_RX_COUNT0_RX_Msk /*!< Reception Byte Count */
+
+#define USB_COUNT0_RX_NUM_BLOCK_Pos (10U)
+#define USB_COUNT0_RX_NUM_BLOCK_Msk (0x1FU << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
+#define USB_COUNT0_RX_NUM_BLOCK USB_COUNT0_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
+#define USB_COUNT0_RX_NUM_BLOCK_0 (0x01U << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
+#define USB_COUNT0_RX_NUM_BLOCK_1 (0x02U << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
+#define USB_COUNT0_RX_NUM_BLOCK_2 (0x04U << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
+#define USB_COUNT0_RX_NUM_BLOCK_3 (0x08U << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
+#define USB_COUNT0_RX_NUM_BLOCK_4 (0x10U << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
+
+#define USB_COUNT0_RX_BLSIZE_Pos (15U)
+#define USB_COUNT0_RX_BLSIZE_Msk (0x1U << USB_COUNT0_RX_BLSIZE_Pos) /*!< 0x00008000 */
+#define USB_COUNT0_RX_BLSIZE USB_COUNT0_RX_BLSIZE_Msk /*!< BLock SIZE */
+
+/***************** Bit definition for USB_COUNT1_RX register ****************/
+#define USB_COUNT1_RX_COUNT1_RX_Pos (0U)
+#define USB_COUNT1_RX_COUNT1_RX_Msk (0x3FFU << USB_COUNT1_RX_COUNT1_RX_Pos) /*!< 0x000003FF */
+#define USB_COUNT1_RX_COUNT1_RX USB_COUNT1_RX_COUNT1_RX_Msk /*!< Reception Byte Count */
+
+#define USB_COUNT1_RX_NUM_BLOCK_Pos (10U)
+#define USB_COUNT1_RX_NUM_BLOCK_Msk (0x1FU << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
+#define USB_COUNT1_RX_NUM_BLOCK USB_COUNT1_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
+#define USB_COUNT1_RX_NUM_BLOCK_0 (0x01U << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
+#define USB_COUNT1_RX_NUM_BLOCK_1 (0x02U << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
+#define USB_COUNT1_RX_NUM_BLOCK_2 (0x04U << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
+#define USB_COUNT1_RX_NUM_BLOCK_3 (0x08U << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
+#define USB_COUNT1_RX_NUM_BLOCK_4 (0x10U << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
+
+#define USB_COUNT1_RX_BLSIZE_Pos (15U)
+#define USB_COUNT1_RX_BLSIZE_Msk (0x1U << USB_COUNT1_RX_BLSIZE_Pos) /*!< 0x00008000 */
+#define USB_COUNT1_RX_BLSIZE USB_COUNT1_RX_BLSIZE_Msk /*!< BLock SIZE */
+
+/***************** Bit definition for USB_COUNT2_RX register ****************/
+#define USB_COUNT2_RX_COUNT2_RX_Pos (0U)
+#define USB_COUNT2_RX_COUNT2_RX_Msk (0x3FFU << USB_COUNT2_RX_COUNT2_RX_Pos) /*!< 0x000003FF */
+#define USB_COUNT2_RX_COUNT2_RX USB_COUNT2_RX_COUNT2_RX_Msk /*!< Reception Byte Count */
+
+#define USB_COUNT2_RX_NUM_BLOCK_Pos (10U)
+#define USB_COUNT2_RX_NUM_BLOCK_Msk (0x1FU << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
+#define USB_COUNT2_RX_NUM_BLOCK USB_COUNT2_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
+#define USB_COUNT2_RX_NUM_BLOCK_0 (0x01U << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
+#define USB_COUNT2_RX_NUM_BLOCK_1 (0x02U << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
+#define USB_COUNT2_RX_NUM_BLOCK_2 (0x04U << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
+#define USB_COUNT2_RX_NUM_BLOCK_3 (0x08U << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
+#define USB_COUNT2_RX_NUM_BLOCK_4 (0x10U << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
+
+#define USB_COUNT2_RX_BLSIZE_Pos (15U)
+#define USB_COUNT2_RX_BLSIZE_Msk (0x1U << USB_COUNT2_RX_BLSIZE_Pos) /*!< 0x00008000 */
+#define USB_COUNT2_RX_BLSIZE USB_COUNT2_RX_BLSIZE_Msk /*!< BLock SIZE */
+
+/***************** Bit definition for USB_COUNT3_RX register ****************/
+#define USB_COUNT3_RX_COUNT3_RX_Pos (0U)
+#define USB_COUNT3_RX_COUNT3_RX_Msk (0x3FFU << USB_COUNT3_RX_COUNT3_RX_Pos) /*!< 0x000003FF */
+#define USB_COUNT3_RX_COUNT3_RX USB_COUNT3_RX_COUNT3_RX_Msk /*!< Reception Byte Count */
+
+#define USB_COUNT3_RX_NUM_BLOCK_Pos (10U)
+#define USB_COUNT3_RX_NUM_BLOCK_Msk (0x1FU << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
+#define USB_COUNT3_RX_NUM_BLOCK USB_COUNT3_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
+#define USB_COUNT3_RX_NUM_BLOCK_0 (0x01U << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
+#define USB_COUNT3_RX_NUM_BLOCK_1 (0x02U << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
+#define USB_COUNT3_RX_NUM_BLOCK_2 (0x04U << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
+#define USB_COUNT3_RX_NUM_BLOCK_3 (0x08U << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
+#define USB_COUNT3_RX_NUM_BLOCK_4 (0x10U << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
+
+#define USB_COUNT3_RX_BLSIZE_Pos (15U)
+#define USB_COUNT3_RX_BLSIZE_Msk (0x1U << USB_COUNT3_RX_BLSIZE_Pos) /*!< 0x00008000 */
+#define USB_COUNT3_RX_BLSIZE USB_COUNT3_RX_BLSIZE_Msk /*!< BLock SIZE */
+
+/***************** Bit definition for USB_COUNT4_RX register ****************/
+#define USB_COUNT4_RX_COUNT4_RX_Pos (0U)
+#define USB_COUNT4_RX_COUNT4_RX_Msk (0x3FFU << USB_COUNT4_RX_COUNT4_RX_Pos) /*!< 0x000003FF */
+#define USB_COUNT4_RX_COUNT4_RX USB_COUNT4_RX_COUNT4_RX_Msk /*!< Reception Byte Count */
+
+#define USB_COUNT4_RX_NUM_BLOCK_Pos (10U)
+#define USB_COUNT4_RX_NUM_BLOCK_Msk (0x1FU << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
+#define USB_COUNT4_RX_NUM_BLOCK USB_COUNT4_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
+#define USB_COUNT4_RX_NUM_BLOCK_0 (0x01U << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
+#define USB_COUNT4_RX_NUM_BLOCK_1 (0x02U << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
+#define USB_COUNT4_RX_NUM_BLOCK_2 (0x04U << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
+#define USB_COUNT4_RX_NUM_BLOCK_3 (0x08U << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
+#define USB_COUNT4_RX_NUM_BLOCK_4 (0x10U << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
+
+#define USB_COUNT4_RX_BLSIZE_Pos (15U)
+#define USB_COUNT4_RX_BLSIZE_Msk (0x1U << USB_COUNT4_RX_BLSIZE_Pos) /*!< 0x00008000 */
+#define USB_COUNT4_RX_BLSIZE USB_COUNT4_RX_BLSIZE_Msk /*!< BLock SIZE */
+
+/***************** Bit definition for USB_COUNT5_RX register ****************/
+#define USB_COUNT5_RX_COUNT5_RX_Pos (0U)
+#define USB_COUNT5_RX_COUNT5_RX_Msk (0x3FFU << USB_COUNT5_RX_COUNT5_RX_Pos) /*!< 0x000003FF */
+#define USB_COUNT5_RX_COUNT5_RX USB_COUNT5_RX_COUNT5_RX_Msk /*!< Reception Byte Count */
+
+#define USB_COUNT5_RX_NUM_BLOCK_Pos (10U)
+#define USB_COUNT5_RX_NUM_BLOCK_Msk (0x1FU << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
+#define USB_COUNT5_RX_NUM_BLOCK USB_COUNT5_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
+#define USB_COUNT5_RX_NUM_BLOCK_0 (0x01U << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
+#define USB_COUNT5_RX_NUM_BLOCK_1 (0x02U << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
+#define USB_COUNT5_RX_NUM_BLOCK_2 (0x04U << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
+#define USB_COUNT5_RX_NUM_BLOCK_3 (0x08U << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
+#define USB_COUNT5_RX_NUM_BLOCK_4 (0x10U << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
+
+#define USB_COUNT5_RX_BLSIZE_Pos (15U)
+#define USB_COUNT5_RX_BLSIZE_Msk (0x1U << USB_COUNT5_RX_BLSIZE_Pos) /*!< 0x00008000 */
+#define USB_COUNT5_RX_BLSIZE USB_COUNT5_RX_BLSIZE_Msk /*!< BLock SIZE */
+
+/***************** Bit definition for USB_COUNT6_RX register ****************/
+#define USB_COUNT6_RX_COUNT6_RX_Pos (0U)
+#define USB_COUNT6_RX_COUNT6_RX_Msk (0x3FFU << USB_COUNT6_RX_COUNT6_RX_Pos) /*!< 0x000003FF */
+#define USB_COUNT6_RX_COUNT6_RX USB_COUNT6_RX_COUNT6_RX_Msk /*!< Reception Byte Count */
+
+#define USB_COUNT6_RX_NUM_BLOCK_Pos (10U)
+#define USB_COUNT6_RX_NUM_BLOCK_Msk (0x1FU << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
+#define USB_COUNT6_RX_NUM_BLOCK USB_COUNT6_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
+#define USB_COUNT6_RX_NUM_BLOCK_0 (0x01U << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
+#define USB_COUNT6_RX_NUM_BLOCK_1 (0x02U << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
+#define USB_COUNT6_RX_NUM_BLOCK_2 (0x04U << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
+#define USB_COUNT6_RX_NUM_BLOCK_3 (0x08U << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
+#define USB_COUNT6_RX_NUM_BLOCK_4 (0x10U << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
+
+#define USB_COUNT6_RX_BLSIZE_Pos (15U)
+#define USB_COUNT6_RX_BLSIZE_Msk (0x1U << USB_COUNT6_RX_BLSIZE_Pos) /*!< 0x00008000 */
+#define USB_COUNT6_RX_BLSIZE USB_COUNT6_RX_BLSIZE_Msk /*!< BLock SIZE */
+
+/***************** Bit definition for USB_COUNT7_RX register ****************/
+#define USB_COUNT7_RX_COUNT7_RX_Pos (0U)
+#define USB_COUNT7_RX_COUNT7_RX_Msk (0x3FFU << USB_COUNT7_RX_COUNT7_RX_Pos) /*!< 0x000003FF */
+#define USB_COUNT7_RX_COUNT7_RX USB_COUNT7_RX_COUNT7_RX_Msk /*!< Reception Byte Count */
+
+#define USB_COUNT7_RX_NUM_BLOCK_Pos (10U)
+#define USB_COUNT7_RX_NUM_BLOCK_Msk (0x1FU << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
+#define USB_COUNT7_RX_NUM_BLOCK USB_COUNT7_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
+#define USB_COUNT7_RX_NUM_BLOCK_0 (0x01U << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
+#define USB_COUNT7_RX_NUM_BLOCK_1 (0x02U << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
+#define USB_COUNT7_RX_NUM_BLOCK_2 (0x04U << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
+#define USB_COUNT7_RX_NUM_BLOCK_3 (0x08U << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
+#define USB_COUNT7_RX_NUM_BLOCK_4 (0x10U << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
+
+#define USB_COUNT7_RX_BLSIZE_Pos (15U)
+#define USB_COUNT7_RX_BLSIZE_Msk (0x1U << USB_COUNT7_RX_BLSIZE_Pos) /*!< 0x00008000 */
+#define USB_COUNT7_RX_BLSIZE USB_COUNT7_RX_BLSIZE_Msk /*!< BLock SIZE */
+
+/*----------------------------------------------------------------------------*/
+
+/**************** Bit definition for USB_COUNT0_RX_0 register ***************/
+#define USB_COUNT0_RX_0_COUNT0_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */
+
+#define USB_COUNT0_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
+#define USB_COUNT0_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */
+#define USB_COUNT0_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */
+#define USB_COUNT0_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */
+#define USB_COUNT0_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */
+#define USB_COUNT0_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */
+
+#define USB_COUNT0_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */
+
+/**************** Bit definition for USB_COUNT0_RX_1 register ***************/
+#define USB_COUNT0_RX_1_COUNT0_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */
+
+#define USB_COUNT0_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
+#define USB_COUNT0_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 1 */
+#define USB_COUNT0_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */
+#define USB_COUNT0_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */
+#define USB_COUNT0_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */
+#define USB_COUNT0_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */
+
+#define USB_COUNT0_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */
+
+/**************** Bit definition for USB_COUNT1_RX_0 register ***************/
+#define USB_COUNT1_RX_0_COUNT1_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */
+
+#define USB_COUNT1_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
+#define USB_COUNT1_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */
+#define USB_COUNT1_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */
+#define USB_COUNT1_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */
+#define USB_COUNT1_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */
+#define USB_COUNT1_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */
+
+#define USB_COUNT1_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */
+
+/**************** Bit definition for USB_COUNT1_RX_1 register ***************/
+#define USB_COUNT1_RX_1_COUNT1_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */
+
+#define USB_COUNT1_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
+#define USB_COUNT1_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */
+#define USB_COUNT1_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */
+#define USB_COUNT1_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */
+#define USB_COUNT1_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */
+#define USB_COUNT1_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */
+
+#define USB_COUNT1_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */
+
+/**************** Bit definition for USB_COUNT2_RX_0 register ***************/
+#define USB_COUNT2_RX_0_COUNT2_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */
+
+#define USB_COUNT2_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
+#define USB_COUNT2_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */
+#define USB_COUNT2_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */
+#define USB_COUNT2_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */
+#define USB_COUNT2_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */
+#define USB_COUNT2_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */
+
+#define USB_COUNT2_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */
+
+/**************** Bit definition for USB_COUNT2_RX_1 register ***************/
+#define USB_COUNT2_RX_1_COUNT2_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */
+
+#define USB_COUNT2_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
+#define USB_COUNT2_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */
+#define USB_COUNT2_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */
+#define USB_COUNT2_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */
+#define USB_COUNT2_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */
+#define USB_COUNT2_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */
+
+#define USB_COUNT2_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */
+
+/**************** Bit definition for USB_COUNT3_RX_0 register ***************/
+#define USB_COUNT3_RX_0_COUNT3_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */
+
+#define USB_COUNT3_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
+#define USB_COUNT3_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */
+#define USB_COUNT3_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */
+#define USB_COUNT3_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */
+#define USB_COUNT3_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */
+#define USB_COUNT3_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */
+
+#define USB_COUNT3_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */
+
+/**************** Bit definition for USB_COUNT3_RX_1 register ***************/
+#define USB_COUNT3_RX_1_COUNT3_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */
+
+#define USB_COUNT3_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
+#define USB_COUNT3_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */
+#define USB_COUNT3_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */
+#define USB_COUNT3_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */
+#define USB_COUNT3_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */
+#define USB_COUNT3_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */
+
+#define USB_COUNT3_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */
+
+/**************** Bit definition for USB_COUNT4_RX_0 register ***************/
+#define USB_COUNT4_RX_0_COUNT4_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */
+
+#define USB_COUNT4_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
+#define USB_COUNT4_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */
+#define USB_COUNT4_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */
+#define USB_COUNT4_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */
+#define USB_COUNT4_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */
+#define USB_COUNT4_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */
+
+#define USB_COUNT4_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */
+
+/**************** Bit definition for USB_COUNT4_RX_1 register ***************/
+#define USB_COUNT4_RX_1_COUNT4_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */
+
+#define USB_COUNT4_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
+#define USB_COUNT4_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */
+#define USB_COUNT4_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */
+#define USB_COUNT4_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */
+#define USB_COUNT4_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */
+#define USB_COUNT4_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */
+
+#define USB_COUNT4_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */
+
+/**************** Bit definition for USB_COUNT5_RX_0 register ***************/
+#define USB_COUNT5_RX_0_COUNT5_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */
+
+#define USB_COUNT5_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
+#define USB_COUNT5_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */
+#define USB_COUNT5_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */
+#define USB_COUNT5_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */
+#define USB_COUNT5_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */
+#define USB_COUNT5_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */
+
+#define USB_COUNT5_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */
+
+/**************** Bit definition for USB_COUNT5_RX_1 register ***************/
+#define USB_COUNT5_RX_1_COUNT5_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */
+
+#define USB_COUNT5_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
+#define USB_COUNT5_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */
+#define USB_COUNT5_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */
+#define USB_COUNT5_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */
+#define USB_COUNT5_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */
+#define USB_COUNT5_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */
+
+#define USB_COUNT5_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */
+
+/*************** Bit definition for USB_COUNT6_RX_0 register ***************/
+#define USB_COUNT6_RX_0_COUNT6_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */
+
+#define USB_COUNT6_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
+#define USB_COUNT6_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */
+#define USB_COUNT6_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */
+#define USB_COUNT6_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */
+#define USB_COUNT6_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */
+#define USB_COUNT6_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */
+
+#define USB_COUNT6_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */
+
+/**************** Bit definition for USB_COUNT6_RX_1 register ***************/
+#define USB_COUNT6_RX_1_COUNT6_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */
+
+#define USB_COUNT6_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
+#define USB_COUNT6_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */
+#define USB_COUNT6_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */
+#define USB_COUNT6_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */
+#define USB_COUNT6_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */
+#define USB_COUNT6_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */
+
+#define USB_COUNT6_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */
+
+/*************** Bit definition for USB_COUNT7_RX_0 register ****************/
+#define USB_COUNT7_RX_0_COUNT7_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */
+
+#define USB_COUNT7_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
+#define USB_COUNT7_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */
+#define USB_COUNT7_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */
+#define USB_COUNT7_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */
+#define USB_COUNT7_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */
+#define USB_COUNT7_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */
+
+#define USB_COUNT7_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */
+
+/*************** Bit definition for USB_COUNT7_RX_1 register ****************/
+#define USB_COUNT7_RX_1_COUNT7_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */
+
+#define USB_COUNT7_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
+#define USB_COUNT7_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */
+#define USB_COUNT7_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */
+#define USB_COUNT7_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */
+#define USB_COUNT7_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */
+#define USB_COUNT7_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */
+
+#define USB_COUNT7_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */
+
+
+/******************************************************************************/
+/* */
+/* Serial Peripheral Interface */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for SPI_CR1 register ********************/
+#define SPI_CR1_CPHA_Pos (0U)
+#define SPI_CR1_CPHA_Msk (0x1U << SPI_CR1_CPHA_Pos) /*!< 0x00000001 */
+#define SPI_CR1_CPHA SPI_CR1_CPHA_Msk /*!< Clock Phase */
+#define SPI_CR1_CPOL_Pos (1U)
+#define SPI_CR1_CPOL_Msk (0x1U << SPI_CR1_CPOL_Pos) /*!< 0x00000002 */
+#define SPI_CR1_CPOL SPI_CR1_CPOL_Msk /*!< Clock Polarity */
+#define SPI_CR1_MSTR_Pos (2U)
+#define SPI_CR1_MSTR_Msk (0x1U << SPI_CR1_MSTR_Pos) /*!< 0x00000004 */
+#define SPI_CR1_MSTR SPI_CR1_MSTR_Msk /*!< Master Selection */
+
+#define SPI_CR1_BR_Pos (3U)
+#define SPI_CR1_BR_Msk (0x7U << SPI_CR1_BR_Pos) /*!< 0x00000038 */
+#define SPI_CR1_BR SPI_CR1_BR_Msk /*!< BR[2:0] bits (Baud Rate Control) */
+#define SPI_CR1_BR_0 (0x1U << SPI_CR1_BR_Pos) /*!< 0x00000008 */
+#define SPI_CR1_BR_1 (0x2U << SPI_CR1_BR_Pos) /*!< 0x00000010 */
+#define SPI_CR1_BR_2 (0x4U << SPI_CR1_BR_Pos) /*!< 0x00000020 */
+
+#define SPI_CR1_SPE_Pos (6U)
+#define SPI_CR1_SPE_Msk (0x1U << SPI_CR1_SPE_Pos) /*!< 0x00000040 */
+#define SPI_CR1_SPE SPI_CR1_SPE_Msk /*!< SPI Enable */
+#define SPI_CR1_LSBFIRST_Pos (7U)
+#define SPI_CR1_LSBFIRST_Msk (0x1U << SPI_CR1_LSBFIRST_Pos) /*!< 0x00000080 */
+#define SPI_CR1_LSBFIRST SPI_CR1_LSBFIRST_Msk /*!< Frame Format */
+#define SPI_CR1_SSI_Pos (8U)
+#define SPI_CR1_SSI_Msk (0x1U << SPI_CR1_SSI_Pos) /*!< 0x00000100 */
+#define SPI_CR1_SSI SPI_CR1_SSI_Msk /*!< Internal slave select */
+#define SPI_CR1_SSM_Pos (9U)
+#define SPI_CR1_SSM_Msk (0x1U << SPI_CR1_SSM_Pos) /*!< 0x00000200 */
+#define SPI_CR1_SSM SPI_CR1_SSM_Msk /*!< Software slave management */
+#define SPI_CR1_RXONLY_Pos (10U)
+#define SPI_CR1_RXONLY_Msk (0x1U << SPI_CR1_RXONLY_Pos) /*!< 0x00000400 */
+#define SPI_CR1_RXONLY SPI_CR1_RXONLY_Msk /*!< Receive only */
+#define SPI_CR1_DFF_Pos (11U)
+#define SPI_CR1_DFF_Msk (0x1U << SPI_CR1_DFF_Pos) /*!< 0x00000800 */
+#define SPI_CR1_DFF SPI_CR1_DFF_Msk /*!< Data Frame Format */
+#define SPI_CR1_CRCNEXT_Pos (12U)
+#define SPI_CR1_CRCNEXT_Msk (0x1U << SPI_CR1_CRCNEXT_Pos) /*!< 0x00001000 */
+#define SPI_CR1_CRCNEXT SPI_CR1_CRCNEXT_Msk /*!< Transmit CRC next */
+#define SPI_CR1_CRCEN_Pos (13U)
+#define SPI_CR1_CRCEN_Msk (0x1U << SPI_CR1_CRCEN_Pos) /*!< 0x00002000 */
+#define SPI_CR1_CRCEN SPI_CR1_CRCEN_Msk /*!< Hardware CRC calculation enable */
+#define SPI_CR1_BIDIOE_Pos (14U)
+#define SPI_CR1_BIDIOE_Msk (0x1U << SPI_CR1_BIDIOE_Pos) /*!< 0x00004000 */
+#define SPI_CR1_BIDIOE SPI_CR1_BIDIOE_Msk /*!< Output enable in bidirectional mode */
+#define SPI_CR1_BIDIMODE_Pos (15U)
+#define SPI_CR1_BIDIMODE_Msk (0x1U << SPI_CR1_BIDIMODE_Pos) /*!< 0x00008000 */
+#define SPI_CR1_BIDIMODE SPI_CR1_BIDIMODE_Msk /*!< Bidirectional data mode enable */
+
+/******************* Bit definition for SPI_CR2 register ********************/
+#define SPI_CR2_RXDMAEN_Pos (0U)
+#define SPI_CR2_RXDMAEN_Msk (0x1U << SPI_CR2_RXDMAEN_Pos) /*!< 0x00000001 */
+#define SPI_CR2_RXDMAEN SPI_CR2_RXDMAEN_Msk /*!< Rx Buffer DMA Enable */
+#define SPI_CR2_TXDMAEN_Pos (1U)
+#define SPI_CR2_TXDMAEN_Msk (0x1U << SPI_CR2_TXDMAEN_Pos) /*!< 0x00000002 */
+#define SPI_CR2_TXDMAEN SPI_CR2_TXDMAEN_Msk /*!< Tx Buffer DMA Enable */
+#define SPI_CR2_SSOE_Pos (2U)
+#define SPI_CR2_SSOE_Msk (0x1U << SPI_CR2_SSOE_Pos) /*!< 0x00000004 */
+#define SPI_CR2_SSOE SPI_CR2_SSOE_Msk /*!< SS Output Enable */
+#define SPI_CR2_ERRIE_Pos (5U)
+#define SPI_CR2_ERRIE_Msk (0x1U << SPI_CR2_ERRIE_Pos) /*!< 0x00000020 */
+#define SPI_CR2_ERRIE SPI_CR2_ERRIE_Msk /*!< Error Interrupt Enable */
+#define SPI_CR2_RXNEIE_Pos (6U)
+#define SPI_CR2_RXNEIE_Msk (0x1U << SPI_CR2_RXNEIE_Pos) /*!< 0x00000040 */
+#define SPI_CR2_RXNEIE SPI_CR2_RXNEIE_Msk /*!< RX buffer Not Empty Interrupt Enable */
+#define SPI_CR2_TXEIE_Pos (7U)
+#define SPI_CR2_TXEIE_Msk (0x1U << SPI_CR2_TXEIE_Pos) /*!< 0x00000080 */
+#define SPI_CR2_TXEIE SPI_CR2_TXEIE_Msk /*!< Tx buffer Empty Interrupt Enable */
+
+/******************** Bit definition for SPI_SR register ********************/
+#define SPI_SR_RXNE_Pos (0U)
+#define SPI_SR_RXNE_Msk (0x1U << SPI_SR_RXNE_Pos) /*!< 0x00000001 */
+#define SPI_SR_RXNE SPI_SR_RXNE_Msk /*!< Receive buffer Not Empty */
+#define SPI_SR_TXE_Pos (1U)
+#define SPI_SR_TXE_Msk (0x1U << SPI_SR_TXE_Pos) /*!< 0x00000002 */
+#define SPI_SR_TXE SPI_SR_TXE_Msk /*!< Transmit buffer Empty */
+#define SPI_SR_CHSIDE_Pos (2U)
+#define SPI_SR_CHSIDE_Msk (0x1U << SPI_SR_CHSIDE_Pos) /*!< 0x00000004 */
+#define SPI_SR_CHSIDE SPI_SR_CHSIDE_Msk /*!< Channel side */
+#define SPI_SR_UDR_Pos (3U)
+#define SPI_SR_UDR_Msk (0x1U << SPI_SR_UDR_Pos) /*!< 0x00000008 */
+#define SPI_SR_UDR SPI_SR_UDR_Msk /*!< Underrun flag */
+#define SPI_SR_CRCERR_Pos (4U)
+#define SPI_SR_CRCERR_Msk (0x1U << SPI_SR_CRCERR_Pos) /*!< 0x00000010 */
+#define SPI_SR_CRCERR SPI_SR_CRCERR_Msk /*!< CRC Error flag */
+#define SPI_SR_MODF_Pos (5U)
+#define SPI_SR_MODF_Msk (0x1U << SPI_SR_MODF_Pos) /*!< 0x00000020 */
+#define SPI_SR_MODF SPI_SR_MODF_Msk /*!< Mode fault */
+#define SPI_SR_OVR_Pos (6U)
+#define SPI_SR_OVR_Msk (0x1U << SPI_SR_OVR_Pos) /*!< 0x00000040 */
+#define SPI_SR_OVR SPI_SR_OVR_Msk /*!< Overrun flag */
+#define SPI_SR_BSY_Pos (7U)
+#define SPI_SR_BSY_Msk (0x1U << SPI_SR_BSY_Pos) /*!< 0x00000080 */
+#define SPI_SR_BSY SPI_SR_BSY_Msk /*!< Busy flag */
+
+/******************** Bit definition for SPI_DR register ********************/
+#define SPI_DR_DR_Pos (0U)
+#define SPI_DR_DR_Msk (0xFFFFU << SPI_DR_DR_Pos) /*!< 0x0000FFFF */
+#define SPI_DR_DR SPI_DR_DR_Msk /*!< Data Register */
+
+/******************* Bit definition for SPI_CRCPR register ******************/
+#define SPI_CRCPR_CRCPOLY_Pos (0U)
+#define SPI_CRCPR_CRCPOLY_Msk (0xFFFFU << SPI_CRCPR_CRCPOLY_Pos) /*!< 0x0000FFFF */
+#define SPI_CRCPR_CRCPOLY SPI_CRCPR_CRCPOLY_Msk /*!< CRC polynomial register */
+
+/****************** Bit definition for SPI_RXCRCR register ******************/
+#define SPI_RXCRCR_RXCRC_Pos (0U)
+#define SPI_RXCRCR_RXCRC_Msk (0xFFFFU << SPI_RXCRCR_RXCRC_Pos) /*!< 0x0000FFFF */
+#define SPI_RXCRCR_RXCRC SPI_RXCRCR_RXCRC_Msk /*!< Rx CRC Register */
+
+/****************** Bit definition for SPI_TXCRCR register ******************/
+#define SPI_TXCRCR_TXCRC_Pos (0U)
+#define SPI_TXCRCR_TXCRC_Msk (0xFFFFU << SPI_TXCRCR_TXCRC_Pos) /*!< 0x0000FFFF */
+#define SPI_TXCRCR_TXCRC SPI_TXCRCR_TXCRC_Msk /*!< Tx CRC Register */
+
+/****************** Bit definition for SPI_I2SCFGR register *****************/
+#define SPI_I2SCFGR_I2SMOD_Pos (11U)
+#define SPI_I2SCFGR_I2SMOD_Msk (0x1U << SPI_I2SCFGR_I2SMOD_Pos) /*!< 0x00000800 */
+#define SPI_I2SCFGR_I2SMOD SPI_I2SCFGR_I2SMOD_Msk /*!< I2S mode selection */
+
+
+/******************************************************************************/
+/* */
+/* Inter-integrated Circuit Interface */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for I2C_CR1 register ********************/
+#define I2C_CR1_PE_Pos (0U)
+#define I2C_CR1_PE_Msk (0x1U << I2C_CR1_PE_Pos) /*!< 0x00000001 */
+#define I2C_CR1_PE I2C_CR1_PE_Msk /*!< Peripheral Enable */
+#define I2C_CR1_SMBUS_Pos (1U)
+#define I2C_CR1_SMBUS_Msk (0x1U << I2C_CR1_SMBUS_Pos) /*!< 0x00000002 */
+#define I2C_CR1_SMBUS I2C_CR1_SMBUS_Msk /*!< SMBus Mode */
+#define I2C_CR1_SMBTYPE_Pos (3U)
+#define I2C_CR1_SMBTYPE_Msk (0x1U << I2C_CR1_SMBTYPE_Pos) /*!< 0x00000008 */
+#define I2C_CR1_SMBTYPE I2C_CR1_SMBTYPE_Msk /*!< SMBus Type */
+#define I2C_CR1_ENARP_Pos (4U)
+#define I2C_CR1_ENARP_Msk (0x1U << I2C_CR1_ENARP_Pos) /*!< 0x00000010 */
+#define I2C_CR1_ENARP I2C_CR1_ENARP_Msk /*!< ARP Enable */
+#define I2C_CR1_ENPEC_Pos (5U)
+#define I2C_CR1_ENPEC_Msk (0x1U << I2C_CR1_ENPEC_Pos) /*!< 0x00000020 */
+#define I2C_CR1_ENPEC I2C_CR1_ENPEC_Msk /*!< PEC Enable */
+#define I2C_CR1_ENGC_Pos (6U)
+#define I2C_CR1_ENGC_Msk (0x1U << I2C_CR1_ENGC_Pos) /*!< 0x00000040 */
+#define I2C_CR1_ENGC I2C_CR1_ENGC_Msk /*!< General Call Enable */
+#define I2C_CR1_NOSTRETCH_Pos (7U)
+#define I2C_CR1_NOSTRETCH_Msk (0x1U << I2C_CR1_NOSTRETCH_Pos) /*!< 0x00000080 */
+#define I2C_CR1_NOSTRETCH I2C_CR1_NOSTRETCH_Msk /*!< Clock Stretching Disable (Slave mode) */
+#define I2C_CR1_START_Pos (8U)
+#define I2C_CR1_START_Msk (0x1U << I2C_CR1_START_Pos) /*!< 0x00000100 */
+#define I2C_CR1_START I2C_CR1_START_Msk /*!< Start Generation */
+#define I2C_CR1_STOP_Pos (9U)
+#define I2C_CR1_STOP_Msk (0x1U << I2C_CR1_STOP_Pos) /*!< 0x00000200 */
+#define I2C_CR1_STOP I2C_CR1_STOP_Msk /*!< Stop Generation */
+#define I2C_CR1_ACK_Pos (10U)
+#define I2C_CR1_ACK_Msk (0x1U << I2C_CR1_ACK_Pos) /*!< 0x00000400 */
+#define I2C_CR1_ACK I2C_CR1_ACK_Msk /*!< Acknowledge Enable */
+#define I2C_CR1_POS_Pos (11U)
+#define I2C_CR1_POS_Msk (0x1U << I2C_CR1_POS_Pos) /*!< 0x00000800 */
+#define I2C_CR1_POS I2C_CR1_POS_Msk /*!< Acknowledge/PEC Position (for data reception) */
+#define I2C_CR1_PEC_Pos (12U)
+#define I2C_CR1_PEC_Msk (0x1U << I2C_CR1_PEC_Pos) /*!< 0x00001000 */
+#define I2C_CR1_PEC I2C_CR1_PEC_Msk /*!< Packet Error Checking */
+#define I2C_CR1_ALERT_Pos (13U)
+#define I2C_CR1_ALERT_Msk (0x1U << I2C_CR1_ALERT_Pos) /*!< 0x00002000 */
+#define I2C_CR1_ALERT I2C_CR1_ALERT_Msk /*!< SMBus Alert */
+#define I2C_CR1_SWRST_Pos (15U)
+#define I2C_CR1_SWRST_Msk (0x1U << I2C_CR1_SWRST_Pos) /*!< 0x00008000 */
+#define I2C_CR1_SWRST I2C_CR1_SWRST_Msk /*!< Software Reset */
+
+/******************* Bit definition for I2C_CR2 register ********************/
+#define I2C_CR2_FREQ_Pos (0U)
+#define I2C_CR2_FREQ_Msk (0x3FU << I2C_CR2_FREQ_Pos) /*!< 0x0000003F */
+#define I2C_CR2_FREQ I2C_CR2_FREQ_Msk /*!< FREQ[5:0] bits (Peripheral Clock Frequency) */
+#define I2C_CR2_FREQ_0 (0x01U << I2C_CR2_FREQ_Pos) /*!< 0x00000001 */
+#define I2C_CR2_FREQ_1 (0x02U << I2C_CR2_FREQ_Pos) /*!< 0x00000002 */
+#define I2C_CR2_FREQ_2 (0x04U << I2C_CR2_FREQ_Pos) /*!< 0x00000004 */
+#define I2C_CR2_FREQ_3 (0x08U << I2C_CR2_FREQ_Pos) /*!< 0x00000008 */
+#define I2C_CR2_FREQ_4 (0x10U << I2C_CR2_FREQ_Pos) /*!< 0x00000010 */
+#define I2C_CR2_FREQ_5 (0x20U << I2C_CR2_FREQ_Pos) /*!< 0x00000020 */
+
+#define I2C_CR2_ITERREN_Pos (8U)
+#define I2C_CR2_ITERREN_Msk (0x1U << I2C_CR2_ITERREN_Pos) /*!< 0x00000100 */
+#define I2C_CR2_ITERREN I2C_CR2_ITERREN_Msk /*!< Error Interrupt Enable */
+#define I2C_CR2_ITEVTEN_Pos (9U)
+#define I2C_CR2_ITEVTEN_Msk (0x1U << I2C_CR2_ITEVTEN_Pos) /*!< 0x00000200 */
+#define I2C_CR2_ITEVTEN I2C_CR2_ITEVTEN_Msk /*!< Event Interrupt Enable */
+#define I2C_CR2_ITBUFEN_Pos (10U)
+#define I2C_CR2_ITBUFEN_Msk (0x1U << I2C_CR2_ITBUFEN_Pos) /*!< 0x00000400 */
+#define I2C_CR2_ITBUFEN I2C_CR2_ITBUFEN_Msk /*!< Buffer Interrupt Enable */
+#define I2C_CR2_DMAEN_Pos (11U)
+#define I2C_CR2_DMAEN_Msk (0x1U << I2C_CR2_DMAEN_Pos) /*!< 0x00000800 */
+#define I2C_CR2_DMAEN I2C_CR2_DMAEN_Msk /*!< DMA Requests Enable */
+#define I2C_CR2_LAST_Pos (12U)
+#define I2C_CR2_LAST_Msk (0x1U << I2C_CR2_LAST_Pos) /*!< 0x00001000 */
+#define I2C_CR2_LAST I2C_CR2_LAST_Msk /*!< DMA Last Transfer */
+
+/******************* Bit definition for I2C_OAR1 register *******************/
+#define I2C_OAR1_ADD1_7 ((uint32_t)0x000000FE) /*!< Interface Address */
+#define I2C_OAR1_ADD8_9 ((uint32_t)0x00000300) /*!< Interface Address */
+
+#define I2C_OAR1_ADD0_Pos (0U)
+#define I2C_OAR1_ADD0_Msk (0x1U << I2C_OAR1_ADD0_Pos) /*!< 0x00000001 */
+#define I2C_OAR1_ADD0 I2C_OAR1_ADD0_Msk /*!< Bit 0 */
+#define I2C_OAR1_ADD1_Pos (1U)
+#define I2C_OAR1_ADD1_Msk (0x1U << I2C_OAR1_ADD1_Pos) /*!< 0x00000002 */
+#define I2C_OAR1_ADD1 I2C_OAR1_ADD1_Msk /*!< Bit 1 */
+#define I2C_OAR1_ADD2_Pos (2U)
+#define I2C_OAR1_ADD2_Msk (0x1U << I2C_OAR1_ADD2_Pos) /*!< 0x00000004 */
+#define I2C_OAR1_ADD2 I2C_OAR1_ADD2_Msk /*!< Bit 2 */
+#define I2C_OAR1_ADD3_Pos (3U)
+#define I2C_OAR1_ADD3_Msk (0x1U << I2C_OAR1_ADD3_Pos) /*!< 0x00000008 */
+#define I2C_OAR1_ADD3 I2C_OAR1_ADD3_Msk /*!< Bit 3 */
+#define I2C_OAR1_ADD4_Pos (4U)
+#define I2C_OAR1_ADD4_Msk (0x1U << I2C_OAR1_ADD4_Pos) /*!< 0x00000010 */
+#define I2C_OAR1_ADD4 I2C_OAR1_ADD4_Msk /*!< Bit 4 */
+#define I2C_OAR1_ADD5_Pos (5U)
+#define I2C_OAR1_ADD5_Msk (0x1U << I2C_OAR1_ADD5_Pos) /*!< 0x00000020 */
+#define I2C_OAR1_ADD5 I2C_OAR1_ADD5_Msk /*!< Bit 5 */
+#define I2C_OAR1_ADD6_Pos (6U)
+#define I2C_OAR1_ADD6_Msk (0x1U << I2C_OAR1_ADD6_Pos) /*!< 0x00000040 */
+#define I2C_OAR1_ADD6 I2C_OAR1_ADD6_Msk /*!< Bit 6 */
+#define I2C_OAR1_ADD7_Pos (7U)
+#define I2C_OAR1_ADD7_Msk (0x1U << I2C_OAR1_ADD7_Pos) /*!< 0x00000080 */
+#define I2C_OAR1_ADD7 I2C_OAR1_ADD7_Msk /*!< Bit 7 */
+#define I2C_OAR1_ADD8_Pos (8U)
+#define I2C_OAR1_ADD8_Msk (0x1U << I2C_OAR1_ADD8_Pos) /*!< 0x00000100 */
+#define I2C_OAR1_ADD8 I2C_OAR1_ADD8_Msk /*!< Bit 8 */
+#define I2C_OAR1_ADD9_Pos (9U)
+#define I2C_OAR1_ADD9_Msk (0x1U << I2C_OAR1_ADD9_Pos) /*!< 0x00000200 */
+#define I2C_OAR1_ADD9 I2C_OAR1_ADD9_Msk /*!< Bit 9 */
+
+#define I2C_OAR1_ADDMODE_Pos (15U)
+#define I2C_OAR1_ADDMODE_Msk (0x1U << I2C_OAR1_ADDMODE_Pos) /*!< 0x00008000 */
+#define I2C_OAR1_ADDMODE I2C_OAR1_ADDMODE_Msk /*!< Addressing Mode (Slave mode) */
+
+/******************* Bit definition for I2C_OAR2 register *******************/
+#define I2C_OAR2_ENDUAL_Pos (0U)
+#define I2C_OAR2_ENDUAL_Msk (0x1U << I2C_OAR2_ENDUAL_Pos) /*!< 0x00000001 */
+#define I2C_OAR2_ENDUAL I2C_OAR2_ENDUAL_Msk /*!< Dual addressing mode enable */
+#define I2C_OAR2_ADD2_Pos (1U)
+#define I2C_OAR2_ADD2_Msk (0x7FU << I2C_OAR2_ADD2_Pos) /*!< 0x000000FE */
+#define I2C_OAR2_ADD2 I2C_OAR2_ADD2_Msk /*!< Interface address */
+
+/******************* Bit definition for I2C_SR1 register ********************/
+#define I2C_SR1_SB_Pos (0U)
+#define I2C_SR1_SB_Msk (0x1U << I2C_SR1_SB_Pos) /*!< 0x00000001 */
+#define I2C_SR1_SB I2C_SR1_SB_Msk /*!< Start Bit (Master mode) */
+#define I2C_SR1_ADDR_Pos (1U)
+#define I2C_SR1_ADDR_Msk (0x1U << I2C_SR1_ADDR_Pos) /*!< 0x00000002 */
+#define I2C_SR1_ADDR I2C_SR1_ADDR_Msk /*!< Address sent (master mode)/matched (slave mode) */
+#define I2C_SR1_BTF_Pos (2U)
+#define I2C_SR1_BTF_Msk (0x1U << I2C_SR1_BTF_Pos) /*!< 0x00000004 */
+#define I2C_SR1_BTF I2C_SR1_BTF_Msk /*!< Byte Transfer Finished */
+#define I2C_SR1_ADD10_Pos (3U)
+#define I2C_SR1_ADD10_Msk (0x1U << I2C_SR1_ADD10_Pos) /*!< 0x00000008 */
+#define I2C_SR1_ADD10 I2C_SR1_ADD10_Msk /*!< 10-bit header sent (Master mode) */
+#define I2C_SR1_STOPF_Pos (4U)
+#define I2C_SR1_STOPF_Msk (0x1U << I2C_SR1_STOPF_Pos) /*!< 0x00000010 */
+#define I2C_SR1_STOPF I2C_SR1_STOPF_Msk /*!< Stop detection (Slave mode) */
+#define I2C_SR1_RXNE_Pos (6U)
+#define I2C_SR1_RXNE_Msk (0x1U << I2C_SR1_RXNE_Pos) /*!< 0x00000040 */
+#define I2C_SR1_RXNE I2C_SR1_RXNE_Msk /*!< Data Register not Empty (receivers) */
+#define I2C_SR1_TXE_Pos (7U)
+#define I2C_SR1_TXE_Msk (0x1U << I2C_SR1_TXE_Pos) /*!< 0x00000080 */
+#define I2C_SR1_TXE I2C_SR1_TXE_Msk /*!< Data Register Empty (transmitters) */
+#define I2C_SR1_BERR_Pos (8U)
+#define I2C_SR1_BERR_Msk (0x1U << I2C_SR1_BERR_Pos) /*!< 0x00000100 */
+#define I2C_SR1_BERR I2C_SR1_BERR_Msk /*!< Bus Error */
+#define I2C_SR1_ARLO_Pos (9U)
+#define I2C_SR1_ARLO_Msk (0x1U << I2C_SR1_ARLO_Pos) /*!< 0x00000200 */
+#define I2C_SR1_ARLO I2C_SR1_ARLO_Msk /*!< Arbitration Lost (master mode) */
+#define I2C_SR1_AF_Pos (10U)
+#define I2C_SR1_AF_Msk (0x1U << I2C_SR1_AF_Pos) /*!< 0x00000400 */
+#define I2C_SR1_AF I2C_SR1_AF_Msk /*!< Acknowledge Failure */
+#define I2C_SR1_OVR_Pos (11U)
+#define I2C_SR1_OVR_Msk (0x1U << I2C_SR1_OVR_Pos) /*!< 0x00000800 */
+#define I2C_SR1_OVR I2C_SR1_OVR_Msk /*!< Overrun/Underrun */
+#define I2C_SR1_PECERR_Pos (12U)
+#define I2C_SR1_PECERR_Msk (0x1U << I2C_SR1_PECERR_Pos) /*!< 0x00001000 */
+#define I2C_SR1_PECERR I2C_SR1_PECERR_Msk /*!< PEC Error in reception */
+#define I2C_SR1_TIMEOUT_Pos (14U)
+#define I2C_SR1_TIMEOUT_Msk (0x1U << I2C_SR1_TIMEOUT_Pos) /*!< 0x00004000 */
+#define I2C_SR1_TIMEOUT I2C_SR1_TIMEOUT_Msk /*!< Timeout or Tlow Error */
+#define I2C_SR1_SMBALERT_Pos (15U)
+#define I2C_SR1_SMBALERT_Msk (0x1U << I2C_SR1_SMBALERT_Pos) /*!< 0x00008000 */
+#define I2C_SR1_SMBALERT I2C_SR1_SMBALERT_Msk /*!< SMBus Alert */
+
+/******************* Bit definition for I2C_SR2 register ********************/
+#define I2C_SR2_MSL_Pos (0U)
+#define I2C_SR2_MSL_Msk (0x1U << I2C_SR2_MSL_Pos) /*!< 0x00000001 */
+#define I2C_SR2_MSL I2C_SR2_MSL_Msk /*!< Master/Slave */
+#define I2C_SR2_BUSY_Pos (1U)
+#define I2C_SR2_BUSY_Msk (0x1U << I2C_SR2_BUSY_Pos) /*!< 0x00000002 */
+#define I2C_SR2_BUSY I2C_SR2_BUSY_Msk /*!< Bus Busy */
+#define I2C_SR2_TRA_Pos (2U)
+#define I2C_SR2_TRA_Msk (0x1U << I2C_SR2_TRA_Pos) /*!< 0x00000004 */
+#define I2C_SR2_TRA I2C_SR2_TRA_Msk /*!< Transmitter/Receiver */
+#define I2C_SR2_GENCALL_Pos (4U)
+#define I2C_SR2_GENCALL_Msk (0x1U << I2C_SR2_GENCALL_Pos) /*!< 0x00000010 */
+#define I2C_SR2_GENCALL I2C_SR2_GENCALL_Msk /*!< General Call Address (Slave mode) */
+#define I2C_SR2_SMBDEFAULT_Pos (5U)
+#define I2C_SR2_SMBDEFAULT_Msk (0x1U << I2C_SR2_SMBDEFAULT_Pos) /*!< 0x00000020 */
+#define I2C_SR2_SMBDEFAULT I2C_SR2_SMBDEFAULT_Msk /*!< SMBus Device Default Address (Slave mode) */
+#define I2C_SR2_SMBHOST_Pos (6U)
+#define I2C_SR2_SMBHOST_Msk (0x1U << I2C_SR2_SMBHOST_Pos) /*!< 0x00000040 */
+#define I2C_SR2_SMBHOST I2C_SR2_SMBHOST_Msk /*!< SMBus Host Header (Slave mode) */
+#define I2C_SR2_DUALF_Pos (7U)
+#define I2C_SR2_DUALF_Msk (0x1U << I2C_SR2_DUALF_Pos) /*!< 0x00000080 */
+#define I2C_SR2_DUALF I2C_SR2_DUALF_Msk /*!< Dual Flag (Slave mode) */
+#define I2C_SR2_PEC_Pos (8U)
+#define I2C_SR2_PEC_Msk (0xFFU << I2C_SR2_PEC_Pos) /*!< 0x0000FF00 */
+#define I2C_SR2_PEC I2C_SR2_PEC_Msk /*!< Packet Error Checking Register */
+
+/******************* Bit definition for I2C_CCR register ********************/
+#define I2C_CCR_CCR_Pos (0U)
+#define I2C_CCR_CCR_Msk (0xFFFU << I2C_CCR_CCR_Pos) /*!< 0x00000FFF */
+#define I2C_CCR_CCR I2C_CCR_CCR_Msk /*!< Clock Control Register in Fast/Standard mode (Master mode) */
+#define I2C_CCR_DUTY_Pos (14U)
+#define I2C_CCR_DUTY_Msk (0x1U << I2C_CCR_DUTY_Pos) /*!< 0x00004000 */
+#define I2C_CCR_DUTY I2C_CCR_DUTY_Msk /*!< Fast Mode Duty Cycle */
+#define I2C_CCR_FS_Pos (15U)
+#define I2C_CCR_FS_Msk (0x1U << I2C_CCR_FS_Pos) /*!< 0x00008000 */
+#define I2C_CCR_FS I2C_CCR_FS_Msk /*!< I2C Master Mode Selection */
+
+/****************** Bit definition for I2C_TRISE register *******************/
+#define I2C_TRISE_TRISE_Pos (0U)
+#define I2C_TRISE_TRISE_Msk (0x3FU << I2C_TRISE_TRISE_Pos) /*!< 0x0000003F */
+#define I2C_TRISE_TRISE I2C_TRISE_TRISE_Msk /*!< Maximum Rise Time in Fast/Standard mode (Master mode) */
+
+/******************************************************************************/
+/* */
+/* Universal Synchronous Asynchronous Receiver Transmitter */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for USART_SR register *******************/
+#define USART_SR_PE_Pos (0U)
+#define USART_SR_PE_Msk (0x1U << USART_SR_PE_Pos) /*!< 0x00000001 */
+#define USART_SR_PE USART_SR_PE_Msk /*!< Parity Error */
+#define USART_SR_FE_Pos (1U)
+#define USART_SR_FE_Msk (0x1U << USART_SR_FE_Pos) /*!< 0x00000002 */
+#define USART_SR_FE USART_SR_FE_Msk /*!< Framing Error */
+#define USART_SR_NE_Pos (2U)
+#define USART_SR_NE_Msk (0x1U << USART_SR_NE_Pos) /*!< 0x00000004 */
+#define USART_SR_NE USART_SR_NE_Msk /*!< Noise Error Flag */
+#define USART_SR_ORE_Pos (3U)
+#define USART_SR_ORE_Msk (0x1U << USART_SR_ORE_Pos) /*!< 0x00000008 */
+#define USART_SR_ORE USART_SR_ORE_Msk /*!< OverRun Error */
+#define USART_SR_IDLE_Pos (4U)
+#define USART_SR_IDLE_Msk (0x1U << USART_SR_IDLE_Pos) /*!< 0x00000010 */
+#define USART_SR_IDLE USART_SR_IDLE_Msk /*!< IDLE line detected */
+#define USART_SR_RXNE_Pos (5U)
+#define USART_SR_RXNE_Msk (0x1U << USART_SR_RXNE_Pos) /*!< 0x00000020 */
+#define USART_SR_RXNE USART_SR_RXNE_Msk /*!< Read Data Register Not Empty */
+#define USART_SR_TC_Pos (6U)
+#define USART_SR_TC_Msk (0x1U << USART_SR_TC_Pos) /*!< 0x00000040 */
+#define USART_SR_TC USART_SR_TC_Msk /*!< Transmission Complete */
+#define USART_SR_TXE_Pos (7U)
+#define USART_SR_TXE_Msk (0x1U << USART_SR_TXE_Pos) /*!< 0x00000080 */
+#define USART_SR_TXE USART_SR_TXE_Msk /*!< Transmit Data Register Empty */
+#define USART_SR_LBD_Pos (8U)
+#define USART_SR_LBD_Msk (0x1U << USART_SR_LBD_Pos) /*!< 0x00000100 */
+#define USART_SR_LBD USART_SR_LBD_Msk /*!< LIN Break Detection Flag */
+#define USART_SR_CTS_Pos (9U)
+#define USART_SR_CTS_Msk (0x1U << USART_SR_CTS_Pos) /*!< 0x00000200 */
+#define USART_SR_CTS USART_SR_CTS_Msk /*!< CTS Flag */
+
+/******************* Bit definition for USART_DR register *******************/
+#define USART_DR_DR_Pos (0U)
+#define USART_DR_DR_Msk (0x1FFU << USART_DR_DR_Pos) /*!< 0x000001FF */
+#define USART_DR_DR USART_DR_DR_Msk /*!< Data value */
+
+/****************** Bit definition for USART_BRR register *******************/
+#define USART_BRR_DIV_Fraction_Pos (0U)
+#define USART_BRR_DIV_Fraction_Msk (0xFU << USART_BRR_DIV_Fraction_Pos) /*!< 0x0000000F */
+#define USART_BRR_DIV_Fraction USART_BRR_DIV_Fraction_Msk /*!< Fraction of USARTDIV */
+#define USART_BRR_DIV_Mantissa_Pos (4U)
+#define USART_BRR_DIV_Mantissa_Msk (0xFFFU << USART_BRR_DIV_Mantissa_Pos) /*!< 0x0000FFF0 */
+#define USART_BRR_DIV_Mantissa USART_BRR_DIV_Mantissa_Msk /*!< Mantissa of USARTDIV */
+
+/****************** Bit definition for USART_CR1 register *******************/
+#define USART_CR1_SBK_Pos (0U)
+#define USART_CR1_SBK_Msk (0x1U << USART_CR1_SBK_Pos) /*!< 0x00000001 */
+#define USART_CR1_SBK USART_CR1_SBK_Msk /*!< Send Break */
+#define USART_CR1_RWU_Pos (1U)
+#define USART_CR1_RWU_Msk (0x1U << USART_CR1_RWU_Pos) /*!< 0x00000002 */
+#define USART_CR1_RWU USART_CR1_RWU_Msk /*!< Receiver wakeup */
+#define USART_CR1_RE_Pos (2U)
+#define USART_CR1_RE_Msk (0x1U << USART_CR1_RE_Pos) /*!< 0x00000004 */
+#define USART_CR1_RE USART_CR1_RE_Msk /*!< Receiver Enable */
+#define USART_CR1_TE_Pos (3U)
+#define USART_CR1_TE_Msk (0x1U << USART_CR1_TE_Pos) /*!< 0x00000008 */
+#define USART_CR1_TE USART_CR1_TE_Msk /*!< Transmitter Enable */
+#define USART_CR1_IDLEIE_Pos (4U)
+#define USART_CR1_IDLEIE_Msk (0x1U << USART_CR1_IDLEIE_Pos) /*!< 0x00000010 */
+#define USART_CR1_IDLEIE USART_CR1_IDLEIE_Msk /*!< IDLE Interrupt Enable */
+#define USART_CR1_RXNEIE_Pos (5U)
+#define USART_CR1_RXNEIE_Msk (0x1U << USART_CR1_RXNEIE_Pos) /*!< 0x00000020 */
+#define USART_CR1_RXNEIE USART_CR1_RXNEIE_Msk /*!< RXNE Interrupt Enable */
+#define USART_CR1_TCIE_Pos (6U)
+#define USART_CR1_TCIE_Msk (0x1U << USART_CR1_TCIE_Pos) /*!< 0x00000040 */
+#define USART_CR1_TCIE USART_CR1_TCIE_Msk /*!< Transmission Complete Interrupt Enable */
+#define USART_CR1_TXEIE_Pos (7U)
+#define USART_CR1_TXEIE_Msk (0x1U << USART_CR1_TXEIE_Pos) /*!< 0x00000080 */
+#define USART_CR1_TXEIE USART_CR1_TXEIE_Msk /*!< PE Interrupt Enable */
+#define USART_CR1_PEIE_Pos (8U)
+#define USART_CR1_PEIE_Msk (0x1U << USART_CR1_PEIE_Pos) /*!< 0x00000100 */
+#define USART_CR1_PEIE USART_CR1_PEIE_Msk /*!< PE Interrupt Enable */
+#define USART_CR1_PS_Pos (9U)
+#define USART_CR1_PS_Msk (0x1U << USART_CR1_PS_Pos) /*!< 0x00000200 */
+#define USART_CR1_PS USART_CR1_PS_Msk /*!< Parity Selection */
+#define USART_CR1_PCE_Pos (10U)
+#define USART_CR1_PCE_Msk (0x1U << USART_CR1_PCE_Pos) /*!< 0x00000400 */
+#define USART_CR1_PCE USART_CR1_PCE_Msk /*!< Parity Control Enable */
+#define USART_CR1_WAKE_Pos (11U)
+#define USART_CR1_WAKE_Msk (0x1U << USART_CR1_WAKE_Pos) /*!< 0x00000800 */
+#define USART_CR1_WAKE USART_CR1_WAKE_Msk /*!< Wakeup method */
+#define USART_CR1_M_Pos (12U)
+#define USART_CR1_M_Msk (0x1U << USART_CR1_M_Pos) /*!< 0x00001000 */
+#define USART_CR1_M USART_CR1_M_Msk /*!< Word length */
+#define USART_CR1_UE_Pos (13U)
+#define USART_CR1_UE_Msk (0x1U << USART_CR1_UE_Pos) /*!< 0x00002000 */
+#define USART_CR1_UE USART_CR1_UE_Msk /*!< USART Enable */
+
+/****************** Bit definition for USART_CR2 register *******************/
+#define USART_CR2_ADD_Pos (0U)
+#define USART_CR2_ADD_Msk (0xFU << USART_CR2_ADD_Pos) /*!< 0x0000000F */
+#define USART_CR2_ADD USART_CR2_ADD_Msk /*!< Address of the USART node */
+#define USART_CR2_LBDL_Pos (5U)
+#define USART_CR2_LBDL_Msk (0x1U << USART_CR2_LBDL_Pos) /*!< 0x00000020 */
+#define USART_CR2_LBDL USART_CR2_LBDL_Msk /*!< LIN Break Detection Length */
+#define USART_CR2_LBDIE_Pos (6U)
+#define USART_CR2_LBDIE_Msk (0x1U << USART_CR2_LBDIE_Pos) /*!< 0x00000040 */
+#define USART_CR2_LBDIE USART_CR2_LBDIE_Msk /*!< LIN Break Detection Interrupt Enable */
+#define USART_CR2_LBCL_Pos (8U)
+#define USART_CR2_LBCL_Msk (0x1U << USART_CR2_LBCL_Pos) /*!< 0x00000100 */
+#define USART_CR2_LBCL USART_CR2_LBCL_Msk /*!< Last Bit Clock pulse */
+#define USART_CR2_CPHA_Pos (9U)
+#define USART_CR2_CPHA_Msk (0x1U << USART_CR2_CPHA_Pos) /*!< 0x00000200 */
+#define USART_CR2_CPHA USART_CR2_CPHA_Msk /*!< Clock Phase */
+#define USART_CR2_CPOL_Pos (10U)
+#define USART_CR2_CPOL_Msk (0x1U << USART_CR2_CPOL_Pos) /*!< 0x00000400 */
+#define USART_CR2_CPOL USART_CR2_CPOL_Msk /*!< Clock Polarity */
+#define USART_CR2_CLKEN_Pos (11U)
+#define USART_CR2_CLKEN_Msk (0x1U << USART_CR2_CLKEN_Pos) /*!< 0x00000800 */
+#define USART_CR2_CLKEN USART_CR2_CLKEN_Msk /*!< Clock Enable */
+
+#define USART_CR2_STOP_Pos (12U)
+#define USART_CR2_STOP_Msk (0x3U << USART_CR2_STOP_Pos) /*!< 0x00003000 */
+#define USART_CR2_STOP USART_CR2_STOP_Msk /*!< STOP[1:0] bits (STOP bits) */
+#define USART_CR2_STOP_0 (0x1U << USART_CR2_STOP_Pos) /*!< 0x00001000 */
+#define USART_CR2_STOP_1 (0x2U << USART_CR2_STOP_Pos) /*!< 0x00002000 */
+
+#define USART_CR2_LINEN_Pos (14U)
+#define USART_CR2_LINEN_Msk (0x1U << USART_CR2_LINEN_Pos) /*!< 0x00004000 */
+#define USART_CR2_LINEN USART_CR2_LINEN_Msk /*!< LIN mode enable */
+
+/****************** Bit definition for USART_CR3 register *******************/
+#define USART_CR3_EIE_Pos (0U)
+#define USART_CR3_EIE_Msk (0x1U << USART_CR3_EIE_Pos) /*!< 0x00000001 */
+#define USART_CR3_EIE USART_CR3_EIE_Msk /*!< Error Interrupt Enable */
+#define USART_CR3_IREN_Pos (1U)
+#define USART_CR3_IREN_Msk (0x1U << USART_CR3_IREN_Pos) /*!< 0x00000002 */
+#define USART_CR3_IREN USART_CR3_IREN_Msk /*!< IrDA mode Enable */
+#define USART_CR3_IRLP_Pos (2U)
+#define USART_CR3_IRLP_Msk (0x1U << USART_CR3_IRLP_Pos) /*!< 0x00000004 */
+#define USART_CR3_IRLP USART_CR3_IRLP_Msk /*!< IrDA Low-Power */
+#define USART_CR3_HDSEL_Pos (3U)
+#define USART_CR3_HDSEL_Msk (0x1U << USART_CR3_HDSEL_Pos) /*!< 0x00000008 */
+#define USART_CR3_HDSEL USART_CR3_HDSEL_Msk /*!< Half-Duplex Selection */
+#define USART_CR3_NACK_Pos (4U)
+#define USART_CR3_NACK_Msk (0x1U << USART_CR3_NACK_Pos) /*!< 0x00000010 */
+#define USART_CR3_NACK USART_CR3_NACK_Msk /*!< Smartcard NACK enable */
+#define USART_CR3_SCEN_Pos (5U)
+#define USART_CR3_SCEN_Msk (0x1U << USART_CR3_SCEN_Pos) /*!< 0x00000020 */
+#define USART_CR3_SCEN USART_CR3_SCEN_Msk /*!< Smartcard mode enable */
+#define USART_CR3_DMAR_Pos (6U)
+#define USART_CR3_DMAR_Msk (0x1U << USART_CR3_DMAR_Pos) /*!< 0x00000040 */
+#define USART_CR3_DMAR USART_CR3_DMAR_Msk /*!< DMA Enable Receiver */
+#define USART_CR3_DMAT_Pos (7U)
+#define USART_CR3_DMAT_Msk (0x1U << USART_CR3_DMAT_Pos) /*!< 0x00000080 */
+#define USART_CR3_DMAT USART_CR3_DMAT_Msk /*!< DMA Enable Transmitter */
+#define USART_CR3_RTSE_Pos (8U)
+#define USART_CR3_RTSE_Msk (0x1U << USART_CR3_RTSE_Pos) /*!< 0x00000100 */
+#define USART_CR3_RTSE USART_CR3_RTSE_Msk /*!< RTS Enable */
+#define USART_CR3_CTSE_Pos (9U)
+#define USART_CR3_CTSE_Msk (0x1U << USART_CR3_CTSE_Pos) /*!< 0x00000200 */
+#define USART_CR3_CTSE USART_CR3_CTSE_Msk /*!< CTS Enable */
+#define USART_CR3_CTSIE_Pos (10U)
+#define USART_CR3_CTSIE_Msk (0x1U << USART_CR3_CTSIE_Pos) /*!< 0x00000400 */
+#define USART_CR3_CTSIE USART_CR3_CTSIE_Msk /*!< CTS Interrupt Enable */
+
+/****************** Bit definition for USART_GTPR register ******************/
+#define USART_GTPR_PSC_Pos (0U)
+#define USART_GTPR_PSC_Msk (0xFFU << USART_GTPR_PSC_Pos) /*!< 0x000000FF */
+#define USART_GTPR_PSC USART_GTPR_PSC_Msk /*!< PSC[7:0] bits (Prescaler value) */
+#define USART_GTPR_PSC_0 (0x01U << USART_GTPR_PSC_Pos) /*!< 0x00000001 */
+#define USART_GTPR_PSC_1 (0x02U << USART_GTPR_PSC_Pos) /*!< 0x00000002 */
+#define USART_GTPR_PSC_2 (0x04U << USART_GTPR_PSC_Pos) /*!< 0x00000004 */
+#define USART_GTPR_PSC_3 (0x08U << USART_GTPR_PSC_Pos) /*!< 0x00000008 */
+#define USART_GTPR_PSC_4 (0x10U << USART_GTPR_PSC_Pos) /*!< 0x00000010 */
+#define USART_GTPR_PSC_5 (0x20U << USART_GTPR_PSC_Pos) /*!< 0x00000020 */
+#define USART_GTPR_PSC_6 (0x40U << USART_GTPR_PSC_Pos) /*!< 0x00000040 */
+#define USART_GTPR_PSC_7 (0x80U << USART_GTPR_PSC_Pos) /*!< 0x00000080 */
+
+#define USART_GTPR_GT_Pos (8U)
+#define USART_GTPR_GT_Msk (0xFFU << USART_GTPR_GT_Pos) /*!< 0x0000FF00 */
+#define USART_GTPR_GT USART_GTPR_GT_Msk /*!< Guard time value */
+
+/******************************************************************************/
+/* */
+/* Debug MCU */
+/* */
+/******************************************************************************/
+
+/**************** Bit definition for DBGMCU_IDCODE register *****************/
+#define DBGMCU_IDCODE_DEV_ID_Pos (0U)
+#define DBGMCU_IDCODE_DEV_ID_Msk (0xFFFU << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */
+#define DBGMCU_IDCODE_DEV_ID DBGMCU_IDCODE_DEV_ID_Msk /*!< Device Identifier */
+
+#define DBGMCU_IDCODE_REV_ID_Pos (16U)
+#define DBGMCU_IDCODE_REV_ID_Msk (0xFFFFU << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */
+#define DBGMCU_IDCODE_REV_ID DBGMCU_IDCODE_REV_ID_Msk /*!< REV_ID[15:0] bits (Revision Identifier) */
+#define DBGMCU_IDCODE_REV_ID_0 (0x0001U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00010000 */
+#define DBGMCU_IDCODE_REV_ID_1 (0x0002U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00020000 */
+#define DBGMCU_IDCODE_REV_ID_2 (0x0004U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00040000 */
+#define DBGMCU_IDCODE_REV_ID_3 (0x0008U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00080000 */
+#define DBGMCU_IDCODE_REV_ID_4 (0x0010U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00100000 */
+#define DBGMCU_IDCODE_REV_ID_5 (0x0020U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00200000 */
+#define DBGMCU_IDCODE_REV_ID_6 (0x0040U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00400000 */
+#define DBGMCU_IDCODE_REV_ID_7 (0x0080U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00800000 */
+#define DBGMCU_IDCODE_REV_ID_8 (0x0100U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x01000000 */
+#define DBGMCU_IDCODE_REV_ID_9 (0x0200U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x02000000 */
+#define DBGMCU_IDCODE_REV_ID_10 (0x0400U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x04000000 */
+#define DBGMCU_IDCODE_REV_ID_11 (0x0800U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x08000000 */
+#define DBGMCU_IDCODE_REV_ID_12 (0x1000U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x10000000 */
+#define DBGMCU_IDCODE_REV_ID_13 (0x2000U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x20000000 */
+#define DBGMCU_IDCODE_REV_ID_14 (0x4000U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x40000000 */
+#define DBGMCU_IDCODE_REV_ID_15 (0x8000U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x80000000 */
+
+/****************** Bit definition for DBGMCU_CR register *******************/
+#define DBGMCU_CR_DBG_SLEEP_Pos (0U)
+#define DBGMCU_CR_DBG_SLEEP_Msk (0x1U << DBGMCU_CR_DBG_SLEEP_Pos) /*!< 0x00000001 */
+#define DBGMCU_CR_DBG_SLEEP DBGMCU_CR_DBG_SLEEP_Msk /*!< Debug Sleep Mode */
+#define DBGMCU_CR_DBG_STOP_Pos (1U)
+#define DBGMCU_CR_DBG_STOP_Msk (0x1U << DBGMCU_CR_DBG_STOP_Pos) /*!< 0x00000002 */
+#define DBGMCU_CR_DBG_STOP DBGMCU_CR_DBG_STOP_Msk /*!< Debug Stop Mode */
+#define DBGMCU_CR_DBG_STANDBY_Pos (2U)
+#define DBGMCU_CR_DBG_STANDBY_Msk (0x1U << DBGMCU_CR_DBG_STANDBY_Pos) /*!< 0x00000004 */
+#define DBGMCU_CR_DBG_STANDBY DBGMCU_CR_DBG_STANDBY_Msk /*!< Debug Standby mode */
+#define DBGMCU_CR_TRACE_IOEN_Pos (5U)
+#define DBGMCU_CR_TRACE_IOEN_Msk (0x1U << DBGMCU_CR_TRACE_IOEN_Pos) /*!< 0x00000020 */
+#define DBGMCU_CR_TRACE_IOEN DBGMCU_CR_TRACE_IOEN_Msk /*!< Trace Pin Assignment Control */
+
+#define DBGMCU_CR_TRACE_MODE_Pos (6U)
+#define DBGMCU_CR_TRACE_MODE_Msk (0x3U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x000000C0 */
+#define DBGMCU_CR_TRACE_MODE DBGMCU_CR_TRACE_MODE_Msk /*!< TRACE_MODE[1:0] bits (Trace Pin Assignment Control) */
+#define DBGMCU_CR_TRACE_MODE_0 (0x1U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000040 */
+#define DBGMCU_CR_TRACE_MODE_1 (0x2U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000080 */
+
+#define DBGMCU_CR_DBG_IWDG_STOP_Pos (8U)
+#define DBGMCU_CR_DBG_IWDG_STOP_Msk (0x1U << DBGMCU_CR_DBG_IWDG_STOP_Pos) /*!< 0x00000100 */
+#define DBGMCU_CR_DBG_IWDG_STOP DBGMCU_CR_DBG_IWDG_STOP_Msk /*!< Debug Independent Watchdog stopped when Core is halted */
+#define DBGMCU_CR_DBG_WWDG_STOP_Pos (9U)
+#define DBGMCU_CR_DBG_WWDG_STOP_Msk (0x1U << DBGMCU_CR_DBG_WWDG_STOP_Pos) /*!< 0x00000200 */
+#define DBGMCU_CR_DBG_WWDG_STOP DBGMCU_CR_DBG_WWDG_STOP_Msk /*!< Debug Window Watchdog stopped when Core is halted */
+#define DBGMCU_CR_DBG_TIM2_STOP_Pos (11U)
+#define DBGMCU_CR_DBG_TIM2_STOP_Msk (0x1U << DBGMCU_CR_DBG_TIM2_STOP_Pos) /*!< 0x00000800 */
+#define DBGMCU_CR_DBG_TIM2_STOP DBGMCU_CR_DBG_TIM2_STOP_Msk /*!< TIM2 counter stopped when core is halted */
+#define DBGMCU_CR_DBG_TIM3_STOP_Pos (12U)
+#define DBGMCU_CR_DBG_TIM3_STOP_Msk (0x1U << DBGMCU_CR_DBG_TIM3_STOP_Pos) /*!< 0x00001000 */
+#define DBGMCU_CR_DBG_TIM3_STOP DBGMCU_CR_DBG_TIM3_STOP_Msk /*!< TIM3 counter stopped when core is halted */
+#define DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT_Pos (15U)
+#define DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT_Msk (0x1U << DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT_Pos) /*!< 0x00008000 */
+#define DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT_Msk /*!< SMBUS timeout mode stopped when Core is halted */
+
+/******************************************************************************/
+/* */
+/* FLASH and Option Bytes Registers */
+/* */
+/******************************************************************************/
+/******************* Bit definition for FLASH_ACR register ******************/
+#define FLASH_ACR_LATENCY_Pos (0U)
+#define FLASH_ACR_LATENCY_Msk (0x7U << FLASH_ACR_LATENCY_Pos) /*!< 0x00000007 */
+#define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk /*!< LATENCY[2:0] bits (Latency) */
+#define FLASH_ACR_LATENCY_0 (0x1U << FLASH_ACR_LATENCY_Pos) /*!< 0x00000001 */
+#define FLASH_ACR_LATENCY_1 (0x2U << FLASH_ACR_LATENCY_Pos) /*!< 0x00000002 */
+#define FLASH_ACR_LATENCY_2 (0x4U << FLASH_ACR_LATENCY_Pos) /*!< 0x00000004 */
+
+#define FLASH_ACR_HLFCYA_Pos (3U)
+#define FLASH_ACR_HLFCYA_Msk (0x1U << FLASH_ACR_HLFCYA_Pos) /*!< 0x00000008 */
+#define FLASH_ACR_HLFCYA FLASH_ACR_HLFCYA_Msk /*!< Flash Half Cycle Access Enable */
+#define FLASH_ACR_PRFTBE_Pos (4U)
+#define FLASH_ACR_PRFTBE_Msk (0x1U << FLASH_ACR_PRFTBE_Pos) /*!< 0x00000010 */
+#define FLASH_ACR_PRFTBE FLASH_ACR_PRFTBE_Msk /*!< Prefetch Buffer Enable */
+#define FLASH_ACR_PRFTBS_Pos (5U)
+#define FLASH_ACR_PRFTBS_Msk (0x1U << FLASH_ACR_PRFTBS_Pos) /*!< 0x00000020 */
+#define FLASH_ACR_PRFTBS FLASH_ACR_PRFTBS_Msk /*!< Prefetch Buffer Status */
+
+/****************** Bit definition for FLASH_KEYR register ******************/
+#define FLASH_KEYR_FKEYR_Pos (0U)
+#define FLASH_KEYR_FKEYR_Msk (0xFFFFFFFFU << FLASH_KEYR_FKEYR_Pos) /*!< 0xFFFFFFFF */
+#define FLASH_KEYR_FKEYR FLASH_KEYR_FKEYR_Msk /*!< FPEC Key */
+
+#define RDP_KEY_Pos (0U)
+#define RDP_KEY_Msk (0xA5U << RDP_KEY_Pos) /*!< 0x000000A5 */
+#define RDP_KEY RDP_KEY_Msk /*!< RDP Key */
+#define FLASH_KEY1_Pos (0U)
+#define FLASH_KEY1_Msk (0x45670123U << FLASH_KEY1_Pos) /*!< 0x45670123 */
+#define FLASH_KEY1 FLASH_KEY1_Msk /*!< FPEC Key1 */
+#define FLASH_KEY2_Pos (0U)
+#define FLASH_KEY2_Msk (0xCDEF89ABU << FLASH_KEY2_Pos) /*!< 0xCDEF89AB */
+#define FLASH_KEY2 FLASH_KEY2_Msk /*!< FPEC Key2 */
+
+/***************** Bit definition for FLASH_OPTKEYR register ****************/
+#define FLASH_OPTKEYR_OPTKEYR_Pos (0U)
+#define FLASH_OPTKEYR_OPTKEYR_Msk (0xFFFFFFFFU << FLASH_OPTKEYR_OPTKEYR_Pos) /*!< 0xFFFFFFFF */
+#define FLASH_OPTKEYR_OPTKEYR FLASH_OPTKEYR_OPTKEYR_Msk /*!< Option Byte Key */
+
+#define FLASH_OPTKEY1 FLASH_KEY1 /*!< Option Byte Key1 */
+#define FLASH_OPTKEY2 FLASH_KEY2 /*!< Option Byte Key2 */
+
+/****************** Bit definition for FLASH_SR register ********************/
+#define FLASH_SR_BSY_Pos (0U)
+#define FLASH_SR_BSY_Msk (0x1U << FLASH_SR_BSY_Pos) /*!< 0x00000001 */
+#define FLASH_SR_BSY FLASH_SR_BSY_Msk /*!< Busy */
+#define FLASH_SR_PGERR_Pos (2U)
+#define FLASH_SR_PGERR_Msk (0x1U << FLASH_SR_PGERR_Pos) /*!< 0x00000004 */
+#define FLASH_SR_PGERR FLASH_SR_PGERR_Msk /*!< Programming Error */
+#define FLASH_SR_WRPRTERR_Pos (4U)
+#define FLASH_SR_WRPRTERR_Msk (0x1U << FLASH_SR_WRPRTERR_Pos) /*!< 0x00000010 */
+#define FLASH_SR_WRPRTERR FLASH_SR_WRPRTERR_Msk /*!< Write Protection Error */
+#define FLASH_SR_EOP_Pos (5U)
+#define FLASH_SR_EOP_Msk (0x1U << FLASH_SR_EOP_Pos) /*!< 0x00000020 */
+#define FLASH_SR_EOP FLASH_SR_EOP_Msk /*!< End of operation */
+
+/******************* Bit definition for FLASH_CR register *******************/
+#define FLASH_CR_PG_Pos (0U)
+#define FLASH_CR_PG_Msk (0x1U << FLASH_CR_PG_Pos) /*!< 0x00000001 */
+#define FLASH_CR_PG FLASH_CR_PG_Msk /*!< Programming */
+#define FLASH_CR_PER_Pos (1U)
+#define FLASH_CR_PER_Msk (0x1U << FLASH_CR_PER_Pos) /*!< 0x00000002 */
+#define FLASH_CR_PER FLASH_CR_PER_Msk /*!< Page Erase */
+#define FLASH_CR_MER_Pos (2U)
+#define FLASH_CR_MER_Msk (0x1U << FLASH_CR_MER_Pos) /*!< 0x00000004 */
+#define FLASH_CR_MER FLASH_CR_MER_Msk /*!< Mass Erase */
+#define FLASH_CR_OPTPG_Pos (4U)
+#define FLASH_CR_OPTPG_Msk (0x1U << FLASH_CR_OPTPG_Pos) /*!< 0x00000010 */
+#define FLASH_CR_OPTPG FLASH_CR_OPTPG_Msk /*!< Option Byte Programming */
+#define FLASH_CR_OPTER_Pos (5U)
+#define FLASH_CR_OPTER_Msk (0x1U << FLASH_CR_OPTER_Pos) /*!< 0x00000020 */
+#define FLASH_CR_OPTER FLASH_CR_OPTER_Msk /*!< Option Byte Erase */
+#define FLASH_CR_STRT_Pos (6U)
+#define FLASH_CR_STRT_Msk (0x1U << FLASH_CR_STRT_Pos) /*!< 0x00000040 */
+#define FLASH_CR_STRT FLASH_CR_STRT_Msk /*!< Start */
+#define FLASH_CR_LOCK_Pos (7U)
+#define FLASH_CR_LOCK_Msk (0x1U << FLASH_CR_LOCK_Pos) /*!< 0x00000080 */
+#define FLASH_CR_LOCK FLASH_CR_LOCK_Msk /*!< Lock */
+#define FLASH_CR_OPTWRE_Pos (9U)
+#define FLASH_CR_OPTWRE_Msk (0x1U << FLASH_CR_OPTWRE_Pos) /*!< 0x00000200 */
+#define FLASH_CR_OPTWRE FLASH_CR_OPTWRE_Msk /*!< Option Bytes Write Enable */
+#define FLASH_CR_ERRIE_Pos (10U)
+#define FLASH_CR_ERRIE_Msk (0x1U << FLASH_CR_ERRIE_Pos) /*!< 0x00000400 */
+#define FLASH_CR_ERRIE FLASH_CR_ERRIE_Msk /*!< Error Interrupt Enable */
+#define FLASH_CR_EOPIE_Pos (12U)
+#define FLASH_CR_EOPIE_Msk (0x1U << FLASH_CR_EOPIE_Pos) /*!< 0x00001000 */
+#define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk /*!< End of operation interrupt enable */
+
+/******************* Bit definition for FLASH_AR register *******************/
+#define FLASH_AR_FAR_Pos (0U)
+#define FLASH_AR_FAR_Msk (0xFFFFFFFFU << FLASH_AR_FAR_Pos) /*!< 0xFFFFFFFF */
+#define FLASH_AR_FAR FLASH_AR_FAR_Msk /*!< Flash Address */
+
+/****************** Bit definition for FLASH_OBR register *******************/
+#define FLASH_OBR_OPTERR_Pos (0U)
+#define FLASH_OBR_OPTERR_Msk (0x1U << FLASH_OBR_OPTERR_Pos) /*!< 0x00000001 */
+#define FLASH_OBR_OPTERR FLASH_OBR_OPTERR_Msk /*!< Option Byte Error */
+#define FLASH_OBR_RDPRT_Pos (1U)
+#define FLASH_OBR_RDPRT_Msk (0x1U << FLASH_OBR_RDPRT_Pos) /*!< 0x00000002 */
+#define FLASH_OBR_RDPRT FLASH_OBR_RDPRT_Msk /*!< Read protection */
+
+#define FLASH_OBR_IWDG_SW_Pos (2U)
+#define FLASH_OBR_IWDG_SW_Msk (0x1U << FLASH_OBR_IWDG_SW_Pos) /*!< 0x00000004 */
+#define FLASH_OBR_IWDG_SW FLASH_OBR_IWDG_SW_Msk /*!< IWDG SW */
+#define FLASH_OBR_nRST_STOP_Pos (3U)
+#define FLASH_OBR_nRST_STOP_Msk (0x1U << FLASH_OBR_nRST_STOP_Pos) /*!< 0x00000008 */
+#define FLASH_OBR_nRST_STOP FLASH_OBR_nRST_STOP_Msk /*!< nRST_STOP */
+#define FLASH_OBR_nRST_STDBY_Pos (4U)
+#define FLASH_OBR_nRST_STDBY_Msk (0x1U << FLASH_OBR_nRST_STDBY_Pos) /*!< 0x00000010 */
+#define FLASH_OBR_nRST_STDBY FLASH_OBR_nRST_STDBY_Msk /*!< nRST_STDBY */
+#define FLASH_OBR_USER_Pos (2U)
+#define FLASH_OBR_USER_Msk (0x7U << FLASH_OBR_USER_Pos) /*!< 0x0000001C */
+#define FLASH_OBR_USER FLASH_OBR_USER_Msk /*!< User Option Bytes */
+#define FLASH_OBR_DATA0_Pos (10U)
+#define FLASH_OBR_DATA0_Msk (0xFFU << FLASH_OBR_DATA0_Pos) /*!< 0x0003FC00 */
+#define FLASH_OBR_DATA0 FLASH_OBR_DATA0_Msk /*!< Data0 */
+#define FLASH_OBR_DATA1_Pos (18U)
+#define FLASH_OBR_DATA1_Msk (0xFFU << FLASH_OBR_DATA1_Pos) /*!< 0x03FC0000 */
+#define FLASH_OBR_DATA1 FLASH_OBR_DATA1_Msk /*!< Data1 */
+
+/****************** Bit definition for FLASH_WRPR register ******************/
+#define FLASH_WRPR_WRP_Pos (0U)
+#define FLASH_WRPR_WRP_Msk (0xFFFFFFFFU << FLASH_WRPR_WRP_Pos) /*!< 0xFFFFFFFF */
+#define FLASH_WRPR_WRP FLASH_WRPR_WRP_Msk /*!< Write Protect */
+
+/*----------------------------------------------------------------------------*/
+
+/****************** Bit definition for FLASH_RDP register *******************/
+#define FLASH_RDP_RDP_Pos (0U)
+#define FLASH_RDP_RDP_Msk (0xFFU << FLASH_RDP_RDP_Pos) /*!< 0x000000FF */
+#define FLASH_RDP_RDP FLASH_RDP_RDP_Msk /*!< Read protection option byte */
+#define FLASH_RDP_nRDP_Pos (8U)
+#define FLASH_RDP_nRDP_Msk (0xFFU << FLASH_RDP_nRDP_Pos) /*!< 0x0000FF00 */
+#define FLASH_RDP_nRDP FLASH_RDP_nRDP_Msk /*!< Read protection complemented option byte */
+
+/****************** Bit definition for FLASH_USER register ******************/
+#define FLASH_USER_USER_Pos (16U)
+#define FLASH_USER_USER_Msk (0xFFU << FLASH_USER_USER_Pos) /*!< 0x00FF0000 */
+#define FLASH_USER_USER FLASH_USER_USER_Msk /*!< User option byte */
+#define FLASH_USER_nUSER_Pos (24U)
+#define FLASH_USER_nUSER_Msk (0xFFU << FLASH_USER_nUSER_Pos) /*!< 0xFF000000 */
+#define FLASH_USER_nUSER FLASH_USER_nUSER_Msk /*!< User complemented option byte */
+
+/****************** Bit definition for FLASH_Data0 register *****************/
+#define FLASH_DATA0_DATA0_Pos (0U)
+#define FLASH_DATA0_DATA0_Msk (0xFFU << FLASH_DATA0_DATA0_Pos) /*!< 0x000000FF */
+#define FLASH_DATA0_DATA0 FLASH_DATA0_DATA0_Msk /*!< User data storage option byte */
+#define FLASH_DATA0_nDATA0_Pos (8U)
+#define FLASH_DATA0_nDATA0_Msk (0xFFU << FLASH_DATA0_nDATA0_Pos) /*!< 0x0000FF00 */
+#define FLASH_DATA0_nDATA0 FLASH_DATA0_nDATA0_Msk /*!< User data storage complemented option byte */
+
+/****************** Bit definition for FLASH_Data1 register *****************/
+#define FLASH_DATA1_DATA1_Pos (16U)
+#define FLASH_DATA1_DATA1_Msk (0xFFU << FLASH_DATA1_DATA1_Pos) /*!< 0x00FF0000 */
+#define FLASH_DATA1_DATA1 FLASH_DATA1_DATA1_Msk /*!< User data storage option byte */
+#define FLASH_DATA1_nDATA1_Pos (24U)
+#define FLASH_DATA1_nDATA1_Msk (0xFFU << FLASH_DATA1_nDATA1_Pos) /*!< 0xFF000000 */
+#define FLASH_DATA1_nDATA1 FLASH_DATA1_nDATA1_Msk /*!< User data storage complemented option byte */
+
+/****************** Bit definition for FLASH_WRP0 register ******************/
+#define FLASH_WRP0_WRP0_Pos (0U)
+#define FLASH_WRP0_WRP0_Msk (0xFFU << FLASH_WRP0_WRP0_Pos) /*!< 0x000000FF */
+#define FLASH_WRP0_WRP0 FLASH_WRP0_WRP0_Msk /*!< Flash memory write protection option bytes */
+#define FLASH_WRP0_nWRP0_Pos (8U)
+#define FLASH_WRP0_nWRP0_Msk (0xFFU << FLASH_WRP0_nWRP0_Pos) /*!< 0x0000FF00 */
+#define FLASH_WRP0_nWRP0 FLASH_WRP0_nWRP0_Msk /*!< Flash memory write protection complemented option bytes */
+
+
+
+/**
+ * @}
+*/
+
+/**
+ * @}
+*/
+
+/** @addtogroup Exported_macro
+ * @{
+ */
+
+/****************************** ADC Instances *********************************/
+#define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1))
+
+#define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC1_COMMON)
+
+#define IS_ADC_DMA_CAPABILITY_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
+
+/****************************** CRC Instances *********************************/
+#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
+
+/****************************** DAC Instances *********************************/
+
+/****************************** DMA Instances *********************************/
+#define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \
+ ((INSTANCE) == DMA1_Channel2) || \
+ ((INSTANCE) == DMA1_Channel3) || \
+ ((INSTANCE) == DMA1_Channel4) || \
+ ((INSTANCE) == DMA1_Channel5) || \
+ ((INSTANCE) == DMA1_Channel6) || \
+ ((INSTANCE) == DMA1_Channel7))
+
+/******************************* GPIO Instances *******************************/
+#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
+ ((INSTANCE) == GPIOB) || \
+ ((INSTANCE) == GPIOC) || \
+ ((INSTANCE) == GPIOD))
+
+/**************************** GPIO Alternate Function Instances ***************/
+#define IS_GPIO_AF_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
+
+/**************************** GPIO Lock Instances *****************************/
+#define IS_GPIO_LOCK_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
+
+/******************************** I2C Instances *******************************/
+#define IS_I2C_ALL_INSTANCE(INSTANCE) ((INSTANCE) == I2C1)
+
+/****************************** IWDG Instances ********************************/
+#define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
+
+/******************************** SPI Instances *******************************/
+#define IS_SPI_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SPI1)
+
+/****************************** START TIM Instances ***************************/
+/****************************** TIM Instances *********************************/
+#define IS_TIM_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3))
+
+#define IS_TIM_CC1_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3))
+
+#define IS_TIM_CC2_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3))
+
+#define IS_TIM_CC3_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3))
+
+#define IS_TIM_CC4_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3))
+
+#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3))
+
+#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3))
+
+#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3))
+
+#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3))
+
+#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3))
+
+#define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3))
+
+#define IS_TIM_XOR_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3))
+
+#define IS_TIM_MASTER_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3))
+
+#define IS_TIM_SLAVE_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3))
+
+#define IS_TIM_DMABURST_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3))
+
+#define IS_TIM_BREAK_INSTANCE(INSTANCE) (0)
+
+#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
+ ((((INSTANCE) == TIM2) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM3) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))))
+
+#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) (0)
+
+#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3))
+
+#define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE) (0)
+
+#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3))
+
+#define IS_TIM_DMA_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3))
+
+#define IS_TIM_DMA_CC_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3))
+
+#define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) (0)
+
+/****************************** END TIM Instances *****************************/
+
+
+/******************** USART Instances : Synchronous mode **********************/
+#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2))
+
+/******************** UART Instances : Asynchronous mode **********************/
+#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) )
+
+/******************** UART Instances : Half-Duplex mode **********************/
+#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) )
+
+/******************** UART Instances : LIN mode **********************/
+#define IS_UART_LIN_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) )
+
+/****************** UART Instances : Hardware Flow control ********************/
+#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) )
+
+/********************* UART Instances : Smard card mode ***********************/
+#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) )
+
+/*********************** UART Instances : IRDA mode ***************************/
+#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) )
+
+/***************** UART Instances : Multi-Processor mode **********************/
+#define IS_UART_MULTIPROCESSOR_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) )
+
+/***************** UART Instances : DMA mode available **********************/
+#define IS_UART_DMA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) )
+
+/****************************** RTC Instances *********************************/
+#define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
+
+/**************************** WWDG Instances *****************************/
+#define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
+
+/****************************** USB Instances ********************************/
+#define IS_USB_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB)
+
+
+
+
+/**
+ * @}
+*/
+/******************************************************************************/
+/* For a painless codes migration between the STM32F1xx device product */
+/* lines, the aliases defined below are put in place to overcome the */
+/* differences in the interrupt handlers and IRQn definitions. */
+/* No need to update developed interrupt code when moving across */
+/* product lines within the same STM32F1 Family */
+/******************************************************************************/
+
+/* Aliases for __IRQn */
+#define ADC1_2_IRQn ADC1_IRQn
+#define CEC_IRQn USBWakeUp_IRQn
+#define OTG_FS_WKUP_IRQn USBWakeUp_IRQn
+#define USB_HP_CAN1_TX_IRQn USB_HP_IRQn
+#define CAN1_TX_IRQn USB_HP_IRQn
+#define USB_LP_CAN1_RX0_IRQn USB_LP_IRQn
+#define CAN1_RX0_IRQn USB_LP_IRQn
+
+
+/* Aliases for __IRQHandler */
+#define ADC1_2_IRQHandler ADC1_IRQHandler
+#define CEC_IRQHandler USBWakeUp_IRQHandler
+#define OTG_FS_WKUP_IRQHandler USBWakeUp_IRQHandler
+#define USB_HP_CAN1_TX_IRQHandler USB_HP_IRQHandler
+#define CAN1_TX_IRQHandler USB_HP_IRQHandler
+#define USB_LP_CAN1_RX0_IRQHandler USB_LP_IRQHandler
+#define CAN1_RX0_IRQHandler USB_LP_IRQHandler
+
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+
+#ifdef __cplusplus
+ }
+#endif /* __cplusplus */
+
+#endif /* __STM32F102x6_H */
+
+
+
+ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Device/ST/STM32F1xx/Include/stm32f102xb.h b/Device/ST/STM32F1xx/Include/stm32f102xb.h
new file mode 100644
index 0000000..63a3945
--- /dev/null
+++ b/Device/ST/STM32F1xx/Include/stm32f102xb.h
@@ -0,0 +1,7405 @@
+/**
+ ******************************************************************************
+ * @file stm32f102xb.h
+ * @author MCD Application Team
+ * @version V4.1.0
+ * @date 29-April-2016
+ * @brief CMSIS Cortex-M3 Device Peripheral Access Layer Header File.
+ * This file contains all the peripheral register's definitions, bits
+ * definitions and memory mapping for STM32F1xx devices.
+ *
+ * This file contains:
+ * - Data structures and the address mapping for all peripherals
+ * - Peripheral's registers declarations and bits definition
+ * - Macros to access peripheral’s registers hardware
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+
+/** @addtogroup CMSIS
+ * @{
+ */
+
+/** @addtogroup stm32f102xb
+ * @{
+ */
+
+#ifndef __STM32F102xB_H
+#define __STM32F102xB_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/** @addtogroup Configuration_section_for_CMSIS
+ * @{
+ */
+/**
+ * @brief Configuration of the Cortex-M3 Processor and Core Peripherals
+ */
+ #define __MPU_PRESENT 0 /*!< Other STM32 devices does not provide an MPU */
+#define __CM3_REV 0x0200 /*!< Core Revision r2p0 */
+#define __NVIC_PRIO_BITS 4 /*!< STM32 uses 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
+
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_interrupt_number_definition
+ * @{
+ */
+
+/**
+ * @brief STM32F10x Interrupt Number Definition, according to the selected device
+ * in @ref Library_configuration_section
+ */
+
+ /*!< Interrupt Number Definition */
+typedef enum
+{
+/****** Cortex-M3 Processor Exceptions Numbers ***************************************************/
+ NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
+ HardFault_IRQn = -13, /*!< 3 Cortex-M3 Hard Fault Interrupt */
+ MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */
+ BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */
+ UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */
+ SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */
+ DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */
+ PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */
+ SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */
+
+/****** STM32 specific Interrupt Numbers *********************************************************/
+ WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
+ PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */
+ TAMPER_IRQn = 2, /*!< Tamper Interrupt */
+ RTC_IRQn = 3, /*!< RTC global Interrupt */
+ FLASH_IRQn = 4, /*!< FLASH global Interrupt */
+ RCC_IRQn = 5, /*!< RCC global Interrupt */
+ EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */
+ EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */
+ EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */
+ EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */
+ EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */
+ DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 global Interrupt */
+ DMA1_Channel2_IRQn = 12, /*!< DMA1 Channel 2 global Interrupt */
+ DMA1_Channel3_IRQn = 13, /*!< DMA1 Channel 3 global Interrupt */
+ DMA1_Channel4_IRQn = 14, /*!< DMA1 Channel 4 global Interrupt */
+ DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 global Interrupt */
+ DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 global Interrupt */
+ DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 global Interrupt */
+ ADC1_IRQn = 18, /*!< ADC1 global Interrupt */
+ USB_HP_IRQn = 19, /*!< USB Device High Priority */
+ USB_LP_IRQn = 20, /*!< USB Device Low Priority */
+ EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
+ TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
+ TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
+ TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
+ I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
+ I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
+ I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
+ I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
+ SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
+ SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
+ USART1_IRQn = 37, /*!< USART1 global Interrupt */
+ USART2_IRQn = 38, /*!< USART2 global Interrupt */
+ USART3_IRQn = 39, /*!< USART3 global Interrupt */
+ EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
+ RTC_Alarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */
+ USBWakeUp_IRQn = 42, /*!< USB Device WakeUp from suspend through EXTI Line Interrupt */
+} IRQn_Type;
+
+
+/**
+ * @}
+ */
+
+#include "core_cm3.h"
+#include "system_stm32f1xx.h"
+#include <stdint.h>
+
+/** @addtogroup Peripheral_registers_structures
+ * @{
+ */
+
+/**
+ * @brief Analog to Digital Converter
+ */
+
+typedef struct
+{
+ __IO uint32_t SR;
+ __IO uint32_t CR1;
+ __IO uint32_t CR2;
+ __IO uint32_t SMPR1;
+ __IO uint32_t SMPR2;
+ __IO uint32_t JOFR1;
+ __IO uint32_t JOFR2;
+ __IO uint32_t JOFR3;
+ __IO uint32_t JOFR4;
+ __IO uint32_t HTR;
+ __IO uint32_t LTR;
+ __IO uint32_t SQR1;
+ __IO uint32_t SQR2;
+ __IO uint32_t SQR3;
+ __IO uint32_t JSQR;
+ __IO uint32_t JDR1;
+ __IO uint32_t JDR2;
+ __IO uint32_t JDR3;
+ __IO uint32_t JDR4;
+ __IO uint32_t DR;
+} ADC_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t SR; /*!< ADC status register, used for ADC multimode (bits common to several ADC instances). Address offset: ADC1 base address */
+ __IO uint32_t CR1; /*!< ADC control register 1, used for ADC multimode (bits common to several ADC instances). Address offset: ADC1 base address + 0x04 */
+ __IO uint32_t CR2; /*!< ADC control register 2, used for ADC multimode (bits common to several ADC instances). Address offset: ADC1 base address + 0x08 */
+ uint32_t RESERVED[16];
+ __IO uint32_t DR; /*!< ADC data register, used for ADC multimode (bits common to several ADC instances). Address offset: ADC1 base address + 0x4C */
+} ADC_Common_TypeDef;
+
+/**
+ * @brief Backup Registers
+ */
+
+typedef struct
+{
+ uint32_t RESERVED0;
+ __IO uint32_t DR1;
+ __IO uint32_t DR2;
+ __IO uint32_t DR3;
+ __IO uint32_t DR4;
+ __IO uint32_t DR5;
+ __IO uint32_t DR6;
+ __IO uint32_t DR7;
+ __IO uint32_t DR8;
+ __IO uint32_t DR9;
+ __IO uint32_t DR10;
+ __IO uint32_t RTCCR;
+ __IO uint32_t CR;
+ __IO uint32_t CSR;
+} BKP_TypeDef;
+
+
+/**
+ * @brief CRC calculation unit
+ */
+
+typedef struct
+{
+ __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
+ __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
+ uint8_t RESERVED0; /*!< Reserved, Address offset: 0x05 */
+ uint16_t RESERVED1; /*!< Reserved, Address offset: 0x06 */
+ __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
+} CRC_TypeDef;
+
+
+/**
+ * @brief Debug MCU
+ */
+
+typedef struct
+{
+ __IO uint32_t IDCODE;
+ __IO uint32_t CR;
+}DBGMCU_TypeDef;
+
+/**
+ * @brief DMA Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t CCR;
+ __IO uint32_t CNDTR;
+ __IO uint32_t CPAR;
+ __IO uint32_t CMAR;
+} DMA_Channel_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t ISR;
+ __IO uint32_t IFCR;
+} DMA_TypeDef;
+
+
+
+/**
+ * @brief External Interrupt/Event Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t IMR;
+ __IO uint32_t EMR;
+ __IO uint32_t RTSR;
+ __IO uint32_t FTSR;
+ __IO uint32_t SWIER;
+ __IO uint32_t PR;
+} EXTI_TypeDef;
+
+/**
+ * @brief FLASH Registers
+ */
+
+typedef struct
+{
+ __IO uint32_t ACR;
+ __IO uint32_t KEYR;
+ __IO uint32_t OPTKEYR;
+ __IO uint32_t SR;
+ __IO uint32_t CR;
+ __IO uint32_t AR;
+ __IO uint32_t RESERVED;
+ __IO uint32_t OBR;
+ __IO uint32_t WRPR;
+} FLASH_TypeDef;
+
+/**
+ * @brief Option Bytes Registers
+ */
+
+typedef struct
+{
+ __IO uint16_t RDP;
+ __IO uint16_t USER;
+ __IO uint16_t Data0;
+ __IO uint16_t Data1;
+ __IO uint16_t WRP0;
+ __IO uint16_t WRP1;
+ __IO uint16_t WRP2;
+ __IO uint16_t WRP3;
+} OB_TypeDef;
+
+/**
+ * @brief General Purpose I/O
+ */
+
+typedef struct
+{
+ __IO uint32_t CRL;
+ __IO uint32_t CRH;
+ __IO uint32_t IDR;
+ __IO uint32_t ODR;
+ __IO uint32_t BSRR;
+ __IO uint32_t BRR;
+ __IO uint32_t LCKR;
+} GPIO_TypeDef;
+
+/**
+ * @brief Alternate Function I/O
+ */
+
+typedef struct
+{
+ __IO uint32_t EVCR;
+ __IO uint32_t MAPR;
+ __IO uint32_t EXTICR[4];
+ uint32_t RESERVED0;
+ __IO uint32_t MAPR2;
+} AFIO_TypeDef;
+/**
+ * @brief Inter Integrated Circuit Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t CR1;
+ __IO uint32_t CR2;
+ __IO uint32_t OAR1;
+ __IO uint32_t OAR2;
+ __IO uint32_t DR;
+ __IO uint32_t SR1;
+ __IO uint32_t SR2;
+ __IO uint32_t CCR;
+ __IO uint32_t TRISE;
+} I2C_TypeDef;
+
+/**
+ * @brief Independent WATCHDOG
+ */
+
+typedef struct
+{
+ __IO uint32_t KR; /*!< Key register, Address offset: 0x00 */
+ __IO uint32_t PR; /*!< Prescaler register, Address offset: 0x04 */
+ __IO uint32_t RLR; /*!< Reload register, Address offset: 0x08 */
+ __IO uint32_t SR; /*!< Status register, Address offset: 0x0C */
+} IWDG_TypeDef;
+
+/**
+ * @brief Power Control
+ */
+
+typedef struct
+{
+ __IO uint32_t CR;
+ __IO uint32_t CSR;
+} PWR_TypeDef;
+
+/**
+ * @brief Reset and Clock Control
+ */
+
+typedef struct
+{
+ __IO uint32_t CR;
+ __IO uint32_t CFGR;
+ __IO uint32_t CIR;
+ __IO uint32_t APB2RSTR;
+ __IO uint32_t APB1RSTR;
+ __IO uint32_t AHBENR;
+ __IO uint32_t APB2ENR;
+ __IO uint32_t APB1ENR;
+ __IO uint32_t BDCR;
+ __IO uint32_t CSR;
+
+
+} RCC_TypeDef;
+
+/**
+ * @brief Real-Time Clock
+ */
+
+typedef struct
+{
+ __IO uint32_t CRH;
+ __IO uint32_t CRL;
+ __IO uint32_t PRLH;
+ __IO uint32_t PRLL;
+ __IO uint32_t DIVH;
+ __IO uint32_t DIVL;
+ __IO uint32_t CNTH;
+ __IO uint32_t CNTL;
+ __IO uint32_t ALRH;
+ __IO uint32_t ALRL;
+} RTC_TypeDef;
+
+/**
+ * @brief SD host Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t POWER;
+ __IO uint32_t CLKCR;
+ __IO uint32_t ARG;
+ __IO uint32_t CMD;
+ __I uint32_t RESPCMD;
+ __I uint32_t RESP1;
+ __I uint32_t RESP2;
+ __I uint32_t RESP3;
+ __I uint32_t RESP4;
+ __IO uint32_t DTIMER;
+ __IO uint32_t DLEN;
+ __IO uint32_t DCTRL;
+ __I uint32_t DCOUNT;
+ __I uint32_t STA;
+ __IO uint32_t ICR;
+ __IO uint32_t MASK;
+ uint32_t RESERVED0[2];
+ __I uint32_t FIFOCNT;
+ uint32_t RESERVED1[13];
+ __IO uint32_t FIFO;
+} SDIO_TypeDef;
+
+/**
+ * @brief Serial Peripheral Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t CR1;
+ __IO uint32_t CR2;
+ __IO uint32_t SR;
+ __IO uint32_t DR;
+ __IO uint32_t CRCPR;
+ __IO uint32_t RXCRCR;
+ __IO uint32_t TXCRCR;
+ __IO uint32_t I2SCFGR;
+} SPI_TypeDef;
+
+/**
+ * @brief TIM Timers
+ */
+typedef struct
+{
+ __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
+ __IO uint32_t SMCR; /*!< TIM slave Mode Control register, Address offset: 0x08 */
+ __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
+ __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
+ __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
+ __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
+ __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
+ __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
+ __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
+ __IO uint32_t PSC; /*!< TIM prescaler register, Address offset: 0x28 */
+ __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
+ __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */
+ __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
+ __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
+ __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
+ __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
+ __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
+ __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
+ __IO uint32_t DMAR; /*!< TIM DMA address for full transfer register, Address offset: 0x4C */
+ __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */
+}TIM_TypeDef;
+
+
+/**
+ * @brief Universal Synchronous Asynchronous Receiver Transmitter
+ */
+
+typedef struct
+{
+ __IO uint32_t SR; /*!< USART Status register, Address offset: 0x00 */
+ __IO uint32_t DR; /*!< USART Data register, Address offset: 0x04 */
+ __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x08 */
+ __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x0C */
+ __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x10 */
+ __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x14 */
+ __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x18 */
+} USART_TypeDef;
+
+/**
+ * @brief Universal Serial Bus Full Speed Device
+ */
+
+typedef struct
+{
+ __IO uint16_t EP0R; /*!< USB Endpoint 0 register, Address offset: 0x00 */
+ __IO uint16_t RESERVED0; /*!< Reserved */
+ __IO uint16_t EP1R; /*!< USB Endpoint 1 register, Address offset: 0x04 */
+ __IO uint16_t RESERVED1; /*!< Reserved */
+ __IO uint16_t EP2R; /*!< USB Endpoint 2 register, Address offset: 0x08 */
+ __IO uint16_t RESERVED2; /*!< Reserved */
+ __IO uint16_t EP3R; /*!< USB Endpoint 3 register, Address offset: 0x0C */
+ __IO uint16_t RESERVED3; /*!< Reserved */
+ __IO uint16_t EP4R; /*!< USB Endpoint 4 register, Address offset: 0x10 */
+ __IO uint16_t RESERVED4; /*!< Reserved */
+ __IO uint16_t EP5R; /*!< USB Endpoint 5 register, Address offset: 0x14 */
+ __IO uint16_t RESERVED5; /*!< Reserved */
+ __IO uint16_t EP6R; /*!< USB Endpoint 6 register, Address offset: 0x18 */
+ __IO uint16_t RESERVED6; /*!< Reserved */
+ __IO uint16_t EP7R; /*!< USB Endpoint 7 register, Address offset: 0x1C */
+ __IO uint16_t RESERVED7[17]; /*!< Reserved */
+ __IO uint16_t CNTR; /*!< Control register, Address offset: 0x40 */
+ __IO uint16_t RESERVED8; /*!< Reserved */
+ __IO uint16_t ISTR; /*!< Interrupt status register, Address offset: 0x44 */
+ __IO uint16_t RESERVED9; /*!< Reserved */
+ __IO uint16_t FNR; /*!< Frame number register, Address offset: 0x48 */
+ __IO uint16_t RESERVEDA; /*!< Reserved */
+ __IO uint16_t DADDR; /*!< Device address register, Address offset: 0x4C */
+ __IO uint16_t RESERVEDB; /*!< Reserved */
+ __IO uint16_t BTABLE; /*!< Buffer Table address register, Address offset: 0x50 */
+ __IO uint16_t RESERVEDC; /*!< Reserved */
+} USB_TypeDef;
+
+
+/**
+ * @brief Window WATCHDOG
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
+ __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
+ __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
+} WWDG_TypeDef;
+
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_memory_map
+ * @{
+ */
+
+
+#define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH base address in the alias region */
+#define FLASH_BANK1_END ((uint32_t)0x0801FFFF) /*!< FLASH END address of bank1 */
+#define SRAM_BASE ((uint32_t)0x20000000) /*!< SRAM base address in the alias region */
+#define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */
+
+#define SRAM_BB_BASE ((uint32_t)0x22000000) /*!< SRAM base address in the bit-band region */
+#define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */
+
+
+/*!< Peripheral memory map */
+#define APB1PERIPH_BASE PERIPH_BASE
+#define APB2PERIPH_BASE (PERIPH_BASE + 0x10000)
+#define AHBPERIPH_BASE (PERIPH_BASE + 0x20000)
+
+#define TIM2_BASE (APB1PERIPH_BASE + 0x0000)
+#define TIM3_BASE (APB1PERIPH_BASE + 0x0400)
+#define TIM4_BASE (APB1PERIPH_BASE + 0x0800)
+#define RTC_BASE (APB1PERIPH_BASE + 0x2800)
+#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00)
+#define IWDG_BASE (APB1PERIPH_BASE + 0x3000)
+#define SPI2_BASE (APB1PERIPH_BASE + 0x3800)
+#define USART2_BASE (APB1PERIPH_BASE + 0x4400)
+#define USART3_BASE (APB1PERIPH_BASE + 0x4800)
+#define I2C1_BASE (APB1PERIPH_BASE + 0x5400)
+#define I2C2_BASE (APB1PERIPH_BASE + 0x5800)
+#define BKP_BASE (APB1PERIPH_BASE + 0x6C00)
+#define PWR_BASE (APB1PERIPH_BASE + 0x7000)
+#define AFIO_BASE (APB2PERIPH_BASE + 0x0000)
+#define EXTI_BASE (APB2PERIPH_BASE + 0x0400)
+#define GPIOA_BASE (APB2PERIPH_BASE + 0x0800)
+#define GPIOB_BASE (APB2PERIPH_BASE + 0x0C00)
+#define GPIOC_BASE (APB2PERIPH_BASE + 0x1000)
+#define GPIOD_BASE (APB2PERIPH_BASE + 0x1400)
+#define ADC1_BASE (APB2PERIPH_BASE + 0x2400)
+#define SPI1_BASE (APB2PERIPH_BASE + 0x3000)
+#define USART1_BASE (APB2PERIPH_BASE + 0x3800)
+
+#define SDIO_BASE (PERIPH_BASE + 0x18000)
+
+#define DMA1_BASE (AHBPERIPH_BASE + 0x0000)
+#define DMA1_Channel1_BASE (AHBPERIPH_BASE + 0x0008)
+#define DMA1_Channel2_BASE (AHBPERIPH_BASE + 0x001C)
+#define DMA1_Channel3_BASE (AHBPERIPH_BASE + 0x0030)
+#define DMA1_Channel4_BASE (AHBPERIPH_BASE + 0x0044)
+#define DMA1_Channel5_BASE (AHBPERIPH_BASE + 0x0058)
+#define DMA1_Channel6_BASE (AHBPERIPH_BASE + 0x006C)
+#define DMA1_Channel7_BASE (AHBPERIPH_BASE + 0x0080)
+#define RCC_BASE (AHBPERIPH_BASE + 0x1000)
+#define CRC_BASE (AHBPERIPH_BASE + 0x3000)
+
+#define FLASH_R_BASE (AHBPERIPH_BASE + 0x2000) /*!< Flash registers base address */
+#define FLASHSIZE_BASE ((uint32_t)0x1FFFF7E0) /*!< FLASH Size register base address */
+#define UID_BASE ((uint32_t)0x1FFFF7E8) /*!< Unique device ID register base address */
+#define OB_BASE ((uint32_t)0x1FFFF800) /*!< Flash Option Bytes base address */
+
+
+
+#define DBGMCU_BASE ((uint32_t)0xE0042000) /*!< Debug MCU registers base address */
+
+/* USB device FS */
+#define USB_BASE (APB1PERIPH_BASE + 0x00005C00) /*!< USB_IP Peripheral Registers base address */
+#define USB_PMAADDR (APB1PERIPH_BASE + 0x00006000) /*!< USB_IP Packet Memory Area base address */
+
+
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_declaration
+ * @{
+ */
+
+#define TIM2 ((TIM_TypeDef *) TIM2_BASE)
+#define TIM3 ((TIM_TypeDef *) TIM3_BASE)
+#define TIM4 ((TIM_TypeDef *) TIM4_BASE)
+#define RTC ((RTC_TypeDef *) RTC_BASE)
+#define WWDG ((WWDG_TypeDef *) WWDG_BASE)
+#define IWDG ((IWDG_TypeDef *) IWDG_BASE)
+#define SPI2 ((SPI_TypeDef *) SPI2_BASE)
+#define USART2 ((USART_TypeDef *) USART2_BASE)
+#define USART3 ((USART_TypeDef *) USART3_BASE)
+#define I2C1 ((I2C_TypeDef *) I2C1_BASE)
+#define I2C2 ((I2C_TypeDef *) I2C2_BASE)
+#define USB ((USB_TypeDef *) USB_BASE)
+#define BKP ((BKP_TypeDef *) BKP_BASE)
+#define PWR ((PWR_TypeDef *) PWR_BASE)
+#define AFIO ((AFIO_TypeDef *) AFIO_BASE)
+#define EXTI ((EXTI_TypeDef *) EXTI_BASE)
+#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
+#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
+#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
+#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
+#define ADC1 ((ADC_TypeDef *) ADC1_BASE)
+#define ADC1_COMMON ((ADC_Common_TypeDef *) ADC1_BASE)
+#define SPI1 ((SPI_TypeDef *) SPI1_BASE)
+#define USART1 ((USART_TypeDef *) USART1_BASE)
+#define SDIO ((SDIO_TypeDef *) SDIO_BASE)
+#define DMA1 ((DMA_TypeDef *) DMA1_BASE)
+#define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
+#define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
+#define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
+#define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
+#define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
+#define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
+#define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
+#define RCC ((RCC_TypeDef *) RCC_BASE)
+#define CRC ((CRC_TypeDef *) CRC_BASE)
+#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
+#define OB ((OB_TypeDef *) OB_BASE)
+#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
+
+
+/**
+ * @}
+ */
+
+/** @addtogroup Exported_constants
+ * @{
+ */
+
+ /** @addtogroup Peripheral_Registers_Bits_Definition
+ * @{
+ */
+
+/******************************************************************************/
+/* Peripheral Registers_Bits_Definition */
+/******************************************************************************/
+
+/******************************************************************************/
+/* */
+/* CRC calculation unit (CRC) */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for CRC_DR register *********************/
+#define CRC_DR_DR_Pos (0U)
+#define CRC_DR_DR_Msk (0xFFFFFFFFU << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */
+#define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */
+
+/******************* Bit definition for CRC_IDR register ********************/
+#define CRC_IDR_IDR_Pos (0U)
+#define CRC_IDR_IDR_Msk (0xFFU << CRC_IDR_IDR_Pos) /*!< 0x000000FF */
+#define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 8-bit data register bits */
+
+/******************** Bit definition for CRC_CR register ********************/
+#define CRC_CR_RESET_Pos (0U)
+#define CRC_CR_RESET_Msk (0x1U << CRC_CR_RESET_Pos) /*!< 0x00000001 */
+#define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET bit */
+
+/******************************************************************************/
+/* */
+/* Power Control */
+/* */
+/******************************************************************************/
+
+/******************** Bit definition for PWR_CR register ********************/
+#define PWR_CR_LPDS_Pos (0U)
+#define PWR_CR_LPDS_Msk (0x1U << PWR_CR_LPDS_Pos) /*!< 0x00000001 */
+#define PWR_CR_LPDS PWR_CR_LPDS_Msk /*!< Low-Power Deepsleep */
+#define PWR_CR_PDDS_Pos (1U)
+#define PWR_CR_PDDS_Msk (0x1U << PWR_CR_PDDS_Pos) /*!< 0x00000002 */
+#define PWR_CR_PDDS PWR_CR_PDDS_Msk /*!< Power Down Deepsleep */
+#define PWR_CR_CWUF_Pos (2U)
+#define PWR_CR_CWUF_Msk (0x1U << PWR_CR_CWUF_Pos) /*!< 0x00000004 */
+#define PWR_CR_CWUF PWR_CR_CWUF_Msk /*!< Clear Wakeup Flag */
+#define PWR_CR_CSBF_Pos (3U)
+#define PWR_CR_CSBF_Msk (0x1U << PWR_CR_CSBF_Pos) /*!< 0x00000008 */
+#define PWR_CR_CSBF PWR_CR_CSBF_Msk /*!< Clear Standby Flag */
+#define PWR_CR_PVDE_Pos (4U)
+#define PWR_CR_PVDE_Msk (0x1U << PWR_CR_PVDE_Pos) /*!< 0x00000010 */
+#define PWR_CR_PVDE PWR_CR_PVDE_Msk /*!< Power Voltage Detector Enable */
+
+#define PWR_CR_PLS_Pos (5U)
+#define PWR_CR_PLS_Msk (0x7U << PWR_CR_PLS_Pos) /*!< 0x000000E0 */
+#define PWR_CR_PLS PWR_CR_PLS_Msk /*!< PLS[2:0] bits (PVD Level Selection) */
+#define PWR_CR_PLS_0 (0x1U << PWR_CR_PLS_Pos) /*!< 0x00000020 */
+#define PWR_CR_PLS_1 (0x2U << PWR_CR_PLS_Pos) /*!< 0x00000040 */
+#define PWR_CR_PLS_2 (0x4U << PWR_CR_PLS_Pos) /*!< 0x00000080 */
+
+/*!< PVD level configuration */
+#define PWR_CR_PLS_2V2 ((uint32_t)0x00000000) /*!< PVD level 2.2V */
+#define PWR_CR_PLS_2V3 ((uint32_t)0x00000020) /*!< PVD level 2.3V */
+#define PWR_CR_PLS_2V4 ((uint32_t)0x00000040) /*!< PVD level 2.4V */
+#define PWR_CR_PLS_2V5 ((uint32_t)0x00000060) /*!< PVD level 2.5V */
+#define PWR_CR_PLS_2V6 ((uint32_t)0x00000080) /*!< PVD level 2.6V */
+#define PWR_CR_PLS_2V7 ((uint32_t)0x000000A0) /*!< PVD level 2.7V */
+#define PWR_CR_PLS_2V8 ((uint32_t)0x000000C0) /*!< PVD level 2.8V */
+#define PWR_CR_PLS_2V9 ((uint32_t)0x000000E0) /*!< PVD level 2.9V */
+
+#define PWR_CR_DBP_Pos (8U)
+#define PWR_CR_DBP_Msk (0x1U << PWR_CR_DBP_Pos) /*!< 0x00000100 */
+#define PWR_CR_DBP PWR_CR_DBP_Msk /*!< Disable Backup Domain write protection */
+
+
+/******************* Bit definition for PWR_CSR register ********************/
+#define PWR_CSR_WUF_Pos (0U)
+#define PWR_CSR_WUF_Msk (0x1U << PWR_CSR_WUF_Pos) /*!< 0x00000001 */
+#define PWR_CSR_WUF PWR_CSR_WUF_Msk /*!< Wakeup Flag */
+#define PWR_CSR_SBF_Pos (1U)
+#define PWR_CSR_SBF_Msk (0x1U << PWR_CSR_SBF_Pos) /*!< 0x00000002 */
+#define PWR_CSR_SBF PWR_CSR_SBF_Msk /*!< Standby Flag */
+#define PWR_CSR_PVDO_Pos (2U)
+#define PWR_CSR_PVDO_Msk (0x1U << PWR_CSR_PVDO_Pos) /*!< 0x00000004 */
+#define PWR_CSR_PVDO PWR_CSR_PVDO_Msk /*!< PVD Output */
+#define PWR_CSR_EWUP_Pos (8U)
+#define PWR_CSR_EWUP_Msk (0x1U << PWR_CSR_EWUP_Pos) /*!< 0x00000100 */
+#define PWR_CSR_EWUP PWR_CSR_EWUP_Msk /*!< Enable WKUP pin */
+
+/******************************************************************************/
+/* */
+/* Backup registers */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for BKP_DR1 register ********************/
+#define BKP_DR1_D_Pos (0U)
+#define BKP_DR1_D_Msk (0xFFFFU << BKP_DR1_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR1_D BKP_DR1_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR2 register ********************/
+#define BKP_DR2_D_Pos (0U)
+#define BKP_DR2_D_Msk (0xFFFFU << BKP_DR2_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR2_D BKP_DR2_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR3 register ********************/
+#define BKP_DR3_D_Pos (0U)
+#define BKP_DR3_D_Msk (0xFFFFU << BKP_DR3_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR3_D BKP_DR3_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR4 register ********************/
+#define BKP_DR4_D_Pos (0U)
+#define BKP_DR4_D_Msk (0xFFFFU << BKP_DR4_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR4_D BKP_DR4_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR5 register ********************/
+#define BKP_DR5_D_Pos (0U)
+#define BKP_DR5_D_Msk (0xFFFFU << BKP_DR5_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR5_D BKP_DR5_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR6 register ********************/
+#define BKP_DR6_D_Pos (0U)
+#define BKP_DR6_D_Msk (0xFFFFU << BKP_DR6_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR6_D BKP_DR6_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR7 register ********************/
+#define BKP_DR7_D_Pos (0U)
+#define BKP_DR7_D_Msk (0xFFFFU << BKP_DR7_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR7_D BKP_DR7_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR8 register ********************/
+#define BKP_DR8_D_Pos (0U)
+#define BKP_DR8_D_Msk (0xFFFFU << BKP_DR8_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR8_D BKP_DR8_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR9 register ********************/
+#define BKP_DR9_D_Pos (0U)
+#define BKP_DR9_D_Msk (0xFFFFU << BKP_DR9_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR9_D BKP_DR9_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR10 register *******************/
+#define BKP_DR10_D_Pos (0U)
+#define BKP_DR10_D_Msk (0xFFFFU << BKP_DR10_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR10_D BKP_DR10_D_Msk /*!< Backup data */
+
+#define RTC_BKP_NUMBER 10
+
+/****************** Bit definition for BKP_RTCCR register *******************/
+#define BKP_RTCCR_CAL_Pos (0U)
+#define BKP_RTCCR_CAL_Msk (0x7FU << BKP_RTCCR_CAL_Pos) /*!< 0x0000007F */
+#define BKP_RTCCR_CAL BKP_RTCCR_CAL_Msk /*!< Calibration value */
+#define BKP_RTCCR_CCO_Pos (7U)
+#define BKP_RTCCR_CCO_Msk (0x1U << BKP_RTCCR_CCO_Pos) /*!< 0x00000080 */
+#define BKP_RTCCR_CCO BKP_RTCCR_CCO_Msk /*!< Calibration Clock Output */
+#define BKP_RTCCR_ASOE_Pos (8U)
+#define BKP_RTCCR_ASOE_Msk (0x1U << BKP_RTCCR_ASOE_Pos) /*!< 0x00000100 */
+#define BKP_RTCCR_ASOE BKP_RTCCR_ASOE_Msk /*!< Alarm or Second Output Enable */
+#define BKP_RTCCR_ASOS_Pos (9U)
+#define BKP_RTCCR_ASOS_Msk (0x1U << BKP_RTCCR_ASOS_Pos) /*!< 0x00000200 */
+#define BKP_RTCCR_ASOS BKP_RTCCR_ASOS_Msk /*!< Alarm or Second Output Selection */
+
+/******************** Bit definition for BKP_CR register ********************/
+#define BKP_CR_TPE_Pos (0U)
+#define BKP_CR_TPE_Msk (0x1U << BKP_CR_TPE_Pos) /*!< 0x00000001 */
+#define BKP_CR_TPE BKP_CR_TPE_Msk /*!< TAMPER pin enable */
+#define BKP_CR_TPAL_Pos (1U)
+#define BKP_CR_TPAL_Msk (0x1U << BKP_CR_TPAL_Pos) /*!< 0x00000002 */
+#define BKP_CR_TPAL BKP_CR_TPAL_Msk /*!< TAMPER pin active level */
+
+/******************* Bit definition for BKP_CSR register ********************/
+#define BKP_CSR_CTE_Pos (0U)
+#define BKP_CSR_CTE_Msk (0x1U << BKP_CSR_CTE_Pos) /*!< 0x00000001 */
+#define BKP_CSR_CTE BKP_CSR_CTE_Msk /*!< Clear Tamper event */
+#define BKP_CSR_CTI_Pos (1U)
+#define BKP_CSR_CTI_Msk (0x1U << BKP_CSR_CTI_Pos) /*!< 0x00000002 */
+#define BKP_CSR_CTI BKP_CSR_CTI_Msk /*!< Clear Tamper Interrupt */
+#define BKP_CSR_TPIE_Pos (2U)
+#define BKP_CSR_TPIE_Msk (0x1U << BKP_CSR_TPIE_Pos) /*!< 0x00000004 */
+#define BKP_CSR_TPIE BKP_CSR_TPIE_Msk /*!< TAMPER Pin interrupt enable */
+#define BKP_CSR_TEF_Pos (8U)
+#define BKP_CSR_TEF_Msk (0x1U << BKP_CSR_TEF_Pos) /*!< 0x00000100 */
+#define BKP_CSR_TEF BKP_CSR_TEF_Msk /*!< Tamper Event Flag */
+#define BKP_CSR_TIF_Pos (9U)
+#define BKP_CSR_TIF_Msk (0x1U << BKP_CSR_TIF_Pos) /*!< 0x00000200 */
+#define BKP_CSR_TIF BKP_CSR_TIF_Msk /*!< Tamper Interrupt Flag */
+
+/******************************************************************************/
+/* */
+/* Reset and Clock Control */
+/* */
+/******************************************************************************/
+
+/******************** Bit definition for RCC_CR register ********************/
+#define RCC_CR_HSION_Pos (0U)
+#define RCC_CR_HSION_Msk (0x1U << RCC_CR_HSION_Pos) /*!< 0x00000001 */
+#define RCC_CR_HSION RCC_CR_HSION_Msk /*!< Internal High Speed clock enable */
+#define RCC_CR_HSIRDY_Pos (1U)
+#define RCC_CR_HSIRDY_Msk (0x1U << RCC_CR_HSIRDY_Pos) /*!< 0x00000002 */
+#define RCC_CR_HSIRDY RCC_CR_HSIRDY_Msk /*!< Internal High Speed clock ready flag */
+#define RCC_CR_HSITRIM_Pos (3U)
+#define RCC_CR_HSITRIM_Msk (0x1FU << RCC_CR_HSITRIM_Pos) /*!< 0x000000F8 */
+#define RCC_CR_HSITRIM RCC_CR_HSITRIM_Msk /*!< Internal High Speed clock trimming */
+#define RCC_CR_HSICAL_Pos (8U)
+#define RCC_CR_HSICAL_Msk (0xFFU << RCC_CR_HSICAL_Pos) /*!< 0x0000FF00 */
+#define RCC_CR_HSICAL RCC_CR_HSICAL_Msk /*!< Internal High Speed clock Calibration */
+#define RCC_CR_HSEON_Pos (16U)
+#define RCC_CR_HSEON_Msk (0x1U << RCC_CR_HSEON_Pos) /*!< 0x00010000 */
+#define RCC_CR_HSEON RCC_CR_HSEON_Msk /*!< External High Speed clock enable */
+#define RCC_CR_HSERDY_Pos (17U)
+#define RCC_CR_HSERDY_Msk (0x1U << RCC_CR_HSERDY_Pos) /*!< 0x00020000 */
+#define RCC_CR_HSERDY RCC_CR_HSERDY_Msk /*!< External High Speed clock ready flag */
+#define RCC_CR_HSEBYP_Pos (18U)
+#define RCC_CR_HSEBYP_Msk (0x1U << RCC_CR_HSEBYP_Pos) /*!< 0x00040000 */
+#define RCC_CR_HSEBYP RCC_CR_HSEBYP_Msk /*!< External High Speed clock Bypass */
+#define RCC_CR_CSSON_Pos (19U)
+#define RCC_CR_CSSON_Msk (0x1U << RCC_CR_CSSON_Pos) /*!< 0x00080000 */
+#define RCC_CR_CSSON RCC_CR_CSSON_Msk /*!< Clock Security System enable */
+#define RCC_CR_PLLON_Pos (24U)
+#define RCC_CR_PLLON_Msk (0x1U << RCC_CR_PLLON_Pos) /*!< 0x01000000 */
+#define RCC_CR_PLLON RCC_CR_PLLON_Msk /*!< PLL enable */
+#define RCC_CR_PLLRDY_Pos (25U)
+#define RCC_CR_PLLRDY_Msk (0x1U << RCC_CR_PLLRDY_Pos) /*!< 0x02000000 */
+#define RCC_CR_PLLRDY RCC_CR_PLLRDY_Msk /*!< PLL clock ready flag */
+
+
+/******************* Bit definition for RCC_CFGR register *******************/
+/*!< SW configuration */
+#define RCC_CFGR_SW_Pos (0U)
+#define RCC_CFGR_SW_Msk (0x3U << RCC_CFGR_SW_Pos) /*!< 0x00000003 */
+#define RCC_CFGR_SW RCC_CFGR_SW_Msk /*!< SW[1:0] bits (System clock Switch) */
+#define RCC_CFGR_SW_0 (0x1U << RCC_CFGR_SW_Pos) /*!< 0x00000001 */
+#define RCC_CFGR_SW_1 (0x2U << RCC_CFGR_SW_Pos) /*!< 0x00000002 */
+
+#define RCC_CFGR_SW_HSI ((uint32_t)0x00000000) /*!< HSI selected as system clock */
+#define RCC_CFGR_SW_HSE ((uint32_t)0x00000001) /*!< HSE selected as system clock */
+#define RCC_CFGR_SW_PLL ((uint32_t)0x00000002) /*!< PLL selected as system clock */
+
+/*!< SWS configuration */
+#define RCC_CFGR_SWS_Pos (2U)
+#define RCC_CFGR_SWS_Msk (0x3U << RCC_CFGR_SWS_Pos) /*!< 0x0000000C */
+#define RCC_CFGR_SWS RCC_CFGR_SWS_Msk /*!< SWS[1:0] bits (System Clock Switch Status) */
+#define RCC_CFGR_SWS_0 (0x1U << RCC_CFGR_SWS_Pos) /*!< 0x00000004 */
+#define RCC_CFGR_SWS_1 (0x2U << RCC_CFGR_SWS_Pos) /*!< 0x00000008 */
+
+#define RCC_CFGR_SWS_HSI ((uint32_t)0x00000000) /*!< HSI oscillator used as system clock */
+#define RCC_CFGR_SWS_HSE ((uint32_t)0x00000004) /*!< HSE oscillator used as system clock */
+#define RCC_CFGR_SWS_PLL ((uint32_t)0x00000008) /*!< PLL used as system clock */
+
+/*!< HPRE configuration */
+#define RCC_CFGR_HPRE_Pos (4U)
+#define RCC_CFGR_HPRE_Msk (0xFU << RCC_CFGR_HPRE_Pos) /*!< 0x000000F0 */
+#define RCC_CFGR_HPRE RCC_CFGR_HPRE_Msk /*!< HPRE[3:0] bits (AHB prescaler) */
+#define RCC_CFGR_HPRE_0 (0x1U << RCC_CFGR_HPRE_Pos) /*!< 0x00000010 */
+#define RCC_CFGR_HPRE_1 (0x2U << RCC_CFGR_HPRE_Pos) /*!< 0x00000020 */
+#define RCC_CFGR_HPRE_2 (0x4U << RCC_CFGR_HPRE_Pos) /*!< 0x00000040 */
+#define RCC_CFGR_HPRE_3 (0x8U << RCC_CFGR_HPRE_Pos) /*!< 0x00000080 */
+
+#define RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000) /*!< SYSCLK not divided */
+#define RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080) /*!< SYSCLK divided by 2 */
+#define RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090) /*!< SYSCLK divided by 4 */
+#define RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0) /*!< SYSCLK divided by 8 */
+#define RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0) /*!< SYSCLK divided by 16 */
+#define RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0) /*!< SYSCLK divided by 64 */
+#define RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0) /*!< SYSCLK divided by 128 */
+#define RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0) /*!< SYSCLK divided by 256 */
+#define RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0) /*!< SYSCLK divided by 512 */
+
+/*!< PPRE1 configuration */
+#define RCC_CFGR_PPRE1_Pos (8U)
+#define RCC_CFGR_PPRE1_Msk (0x7U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000700 */
+#define RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_Msk /*!< PRE1[2:0] bits (APB1 prescaler) */
+#define RCC_CFGR_PPRE1_0 (0x1U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000100 */
+#define RCC_CFGR_PPRE1_1 (0x2U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000200 */
+#define RCC_CFGR_PPRE1_2 (0x4U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000400 */
+
+#define RCC_CFGR_PPRE1_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */
+#define RCC_CFGR_PPRE1_DIV2 ((uint32_t)0x00000400) /*!< HCLK divided by 2 */
+#define RCC_CFGR_PPRE1_DIV4 ((uint32_t)0x00000500) /*!< HCLK divided by 4 */
+#define RCC_CFGR_PPRE1_DIV8 ((uint32_t)0x00000600) /*!< HCLK divided by 8 */
+#define RCC_CFGR_PPRE1_DIV16 ((uint32_t)0x00000700) /*!< HCLK divided by 16 */
+
+/*!< PPRE2 configuration */
+#define RCC_CFGR_PPRE2_Pos (11U)
+#define RCC_CFGR_PPRE2_Msk (0x7U << RCC_CFGR_PPRE2_Pos) /*!< 0x00003800 */
+#define RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_Msk /*!< PRE2[2:0] bits (APB2 prescaler) */
+#define RCC_CFGR_PPRE2_0 (0x1U << RCC_CFGR_PPRE2_Pos) /*!< 0x00000800 */
+#define RCC_CFGR_PPRE2_1 (0x2U << RCC_CFGR_PPRE2_Pos) /*!< 0x00001000 */
+#define RCC_CFGR_PPRE2_2 (0x4U << RCC_CFGR_PPRE2_Pos) /*!< 0x00002000 */
+
+#define RCC_CFGR_PPRE2_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */
+#define RCC_CFGR_PPRE2_DIV2 ((uint32_t)0x00002000) /*!< HCLK divided by 2 */
+#define RCC_CFGR_PPRE2_DIV4 ((uint32_t)0x00002800) /*!< HCLK divided by 4 */
+#define RCC_CFGR_PPRE2_DIV8 ((uint32_t)0x00003000) /*!< HCLK divided by 8 */
+#define RCC_CFGR_PPRE2_DIV16 ((uint32_t)0x00003800) /*!< HCLK divided by 16 */
+
+/*!< ADCPPRE configuration */
+#define RCC_CFGR_ADCPRE_Pos (14U)
+#define RCC_CFGR_ADCPRE_Msk (0x3U << RCC_CFGR_ADCPRE_Pos) /*!< 0x0000C000 */
+#define RCC_CFGR_ADCPRE RCC_CFGR_ADCPRE_Msk /*!< ADCPRE[1:0] bits (ADC prescaler) */
+#define RCC_CFGR_ADCPRE_0 (0x1U << RCC_CFGR_ADCPRE_Pos) /*!< 0x00004000 */
+#define RCC_CFGR_ADCPRE_1 (0x2U << RCC_CFGR_ADCPRE_Pos) /*!< 0x00008000 */
+
+#define RCC_CFGR_ADCPRE_DIV2 ((uint32_t)0x00000000) /*!< PCLK2 divided by 2 */
+#define RCC_CFGR_ADCPRE_DIV4 ((uint32_t)0x00004000) /*!< PCLK2 divided by 4 */
+#define RCC_CFGR_ADCPRE_DIV6 ((uint32_t)0x00008000) /*!< PCLK2 divided by 6 */
+#define RCC_CFGR_ADCPRE_DIV8 ((uint32_t)0x0000C000) /*!< PCLK2 divided by 8 */
+
+#define RCC_CFGR_PLLSRC_Pos (16U)
+#define RCC_CFGR_PLLSRC_Msk (0x1U << RCC_CFGR_PLLSRC_Pos) /*!< 0x00010000 */
+#define RCC_CFGR_PLLSRC RCC_CFGR_PLLSRC_Msk /*!< PLL entry clock source */
+
+#define RCC_CFGR_PLLXTPRE_Pos (17U)
+#define RCC_CFGR_PLLXTPRE_Msk (0x1U << RCC_CFGR_PLLXTPRE_Pos) /*!< 0x00020000 */
+#define RCC_CFGR_PLLXTPRE RCC_CFGR_PLLXTPRE_Msk /*!< HSE divider for PLL entry */
+
+/*!< PLLMUL configuration */
+#define RCC_CFGR_PLLMULL_Pos (18U)
+#define RCC_CFGR_PLLMULL_Msk (0xFU << RCC_CFGR_PLLMULL_Pos) /*!< 0x003C0000 */
+#define RCC_CFGR_PLLMULL RCC_CFGR_PLLMULL_Msk /*!< PLLMUL[3:0] bits (PLL multiplication factor) */
+#define RCC_CFGR_PLLMULL_0 (0x1U << RCC_CFGR_PLLMULL_Pos) /*!< 0x00040000 */
+#define RCC_CFGR_PLLMULL_1 (0x2U << RCC_CFGR_PLLMULL_Pos) /*!< 0x00080000 */
+#define RCC_CFGR_PLLMULL_2 (0x4U << RCC_CFGR_PLLMULL_Pos) /*!< 0x00100000 */
+#define RCC_CFGR_PLLMULL_3 (0x8U << RCC_CFGR_PLLMULL_Pos) /*!< 0x00200000 */
+
+#define RCC_CFGR_PLLXTPRE_HSE ((uint32_t)0x00000000) /*!< HSE clock not divided for PLL entry */
+#define RCC_CFGR_PLLXTPRE_HSE_DIV2 ((uint32_t)0x00020000) /*!< HSE clock divided by 2 for PLL entry */
+
+#define RCC_CFGR_PLLMULL2 ((uint32_t)0x00000000) /*!< PLL input clock*2 */
+#define RCC_CFGR_PLLMULL3_Pos (18U)
+#define RCC_CFGR_PLLMULL3_Msk (0x1U << RCC_CFGR_PLLMULL3_Pos) /*!< 0x00040000 */
+#define RCC_CFGR_PLLMULL3 RCC_CFGR_PLLMULL3_Msk /*!< PLL input clock*3 */
+#define RCC_CFGR_PLLMULL4_Pos (19U)
+#define RCC_CFGR_PLLMULL4_Msk (0x1U << RCC_CFGR_PLLMULL4_Pos) /*!< 0x00080000 */
+#define RCC_CFGR_PLLMULL4 RCC_CFGR_PLLMULL4_Msk /*!< PLL input clock*4 */
+#define RCC_CFGR_PLLMULL5_Pos (18U)
+#define RCC_CFGR_PLLMULL5_Msk (0x3U << RCC_CFGR_PLLMULL5_Pos) /*!< 0x000C0000 */
+#define RCC_CFGR_PLLMULL5 RCC_CFGR_PLLMULL5_Msk /*!< PLL input clock*5 */
+#define RCC_CFGR_PLLMULL6_Pos (20U)
+#define RCC_CFGR_PLLMULL6_Msk (0x1U << RCC_CFGR_PLLMULL6_Pos) /*!< 0x00100000 */
+#define RCC_CFGR_PLLMULL6 RCC_CFGR_PLLMULL6_Msk /*!< PLL input clock*6 */
+#define RCC_CFGR_PLLMULL7_Pos (18U)
+#define RCC_CFGR_PLLMULL7_Msk (0x5U << RCC_CFGR_PLLMULL7_Pos) /*!< 0x00140000 */
+#define RCC_CFGR_PLLMULL7 RCC_CFGR_PLLMULL7_Msk /*!< PLL input clock*7 */
+#define RCC_CFGR_PLLMULL8_Pos (19U)
+#define RCC_CFGR_PLLMULL8_Msk (0x3U << RCC_CFGR_PLLMULL8_Pos) /*!< 0x00180000 */
+#define RCC_CFGR_PLLMULL8 RCC_CFGR_PLLMULL8_Msk /*!< PLL input clock*8 */
+#define RCC_CFGR_PLLMULL9_Pos (18U)
+#define RCC_CFGR_PLLMULL9_Msk (0x7U << RCC_CFGR_PLLMULL9_Pos) /*!< 0x001C0000 */
+#define RCC_CFGR_PLLMULL9 RCC_CFGR_PLLMULL9_Msk /*!< PLL input clock*9 */
+#define RCC_CFGR_PLLMULL10_Pos (21U)
+#define RCC_CFGR_PLLMULL10_Msk (0x1U << RCC_CFGR_PLLMULL10_Pos) /*!< 0x00200000 */
+#define RCC_CFGR_PLLMULL10 RCC_CFGR_PLLMULL10_Msk /*!< PLL input clock10 */
+#define RCC_CFGR_PLLMULL11_Pos (18U)
+#define RCC_CFGR_PLLMULL11_Msk (0x9U << RCC_CFGR_PLLMULL11_Pos) /*!< 0x00240000 */
+#define RCC_CFGR_PLLMULL11 RCC_CFGR_PLLMULL11_Msk /*!< PLL input clock*11 */
+#define RCC_CFGR_PLLMULL12_Pos (19U)
+#define RCC_CFGR_PLLMULL12_Msk (0x5U << RCC_CFGR_PLLMULL12_Pos) /*!< 0x00280000 */
+#define RCC_CFGR_PLLMULL12 RCC_CFGR_PLLMULL12_Msk /*!< PLL input clock*12 */
+#define RCC_CFGR_PLLMULL13_Pos (18U)
+#define RCC_CFGR_PLLMULL13_Msk (0xBU << RCC_CFGR_PLLMULL13_Pos) /*!< 0x002C0000 */
+#define RCC_CFGR_PLLMULL13 RCC_CFGR_PLLMULL13_Msk /*!< PLL input clock*13 */
+#define RCC_CFGR_PLLMULL14_Pos (20U)
+#define RCC_CFGR_PLLMULL14_Msk (0x3U << RCC_CFGR_PLLMULL14_Pos) /*!< 0x00300000 */
+#define RCC_CFGR_PLLMULL14 RCC_CFGR_PLLMULL14_Msk /*!< PLL input clock*14 */
+#define RCC_CFGR_PLLMULL15_Pos (18U)
+#define RCC_CFGR_PLLMULL15_Msk (0xDU << RCC_CFGR_PLLMULL15_Pos) /*!< 0x00340000 */
+#define RCC_CFGR_PLLMULL15 RCC_CFGR_PLLMULL15_Msk /*!< PLL input clock*15 */
+#define RCC_CFGR_PLLMULL16_Pos (19U)
+#define RCC_CFGR_PLLMULL16_Msk (0x7U << RCC_CFGR_PLLMULL16_Pos) /*!< 0x00380000 */
+#define RCC_CFGR_PLLMULL16 RCC_CFGR_PLLMULL16_Msk /*!< PLL input clock*16 */
+#define RCC_CFGR_USBPRE_Pos (22U)
+#define RCC_CFGR_USBPRE_Msk (0x1U << RCC_CFGR_USBPRE_Pos) /*!< 0x00400000 */
+#define RCC_CFGR_USBPRE RCC_CFGR_USBPRE_Msk /*!< USB Device prescaler */
+
+/*!< MCO configuration */
+#define RCC_CFGR_MCO_Pos (24U)
+#define RCC_CFGR_MCO_Msk (0x7U << RCC_CFGR_MCO_Pos) /*!< 0x07000000 */
+#define RCC_CFGR_MCO RCC_CFGR_MCO_Msk /*!< MCO[2:0] bits (Microcontroller Clock Output) */
+#define RCC_CFGR_MCO_0 (0x1U << RCC_CFGR_MCO_Pos) /*!< 0x01000000 */
+#define RCC_CFGR_MCO_1 (0x2U << RCC_CFGR_MCO_Pos) /*!< 0x02000000 */
+#define RCC_CFGR_MCO_2 (0x4U << RCC_CFGR_MCO_Pos) /*!< 0x04000000 */
+
+#define RCC_CFGR_MCO_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */
+#define RCC_CFGR_MCO_SYSCLK ((uint32_t)0x04000000) /*!< System clock selected as MCO source */
+#define RCC_CFGR_MCO_HSI ((uint32_t)0x05000000) /*!< HSI clock selected as MCO source */
+#define RCC_CFGR_MCO_HSE ((uint32_t)0x06000000) /*!< HSE clock selected as MCO source */
+#define RCC_CFGR_MCO_PLLCLK_DIV2 ((uint32_t)0x07000000) /*!< PLL clock divided by 2 selected as MCO source */
+
+ /* Reference defines */
+ #define RCC_CFGR_MCOSEL RCC_CFGR_MCO
+ #define RCC_CFGR_MCOSEL_0 RCC_CFGR_MCO_0
+ #define RCC_CFGR_MCOSEL_1 RCC_CFGR_MCO_1
+ #define RCC_CFGR_MCOSEL_2 RCC_CFGR_MCO_2
+ #define RCC_CFGR_MCOSEL_NOCLOCK RCC_CFGR_MCO_NOCLOCK
+ #define RCC_CFGR_MCOSEL_SYSCLK RCC_CFGR_MCO_SYSCLK
+ #define RCC_CFGR_MCOSEL_HSI RCC_CFGR_MCO_HSI
+ #define RCC_CFGR_MCOSEL_HSE RCC_CFGR_MCO_HSE
+ #define RCC_CFGR_MCOSEL_PLL_DIV2 RCC_CFGR_MCO_PLLCLK_DIV2
+
+/*!<****************** Bit definition for RCC_CIR register ********************/
+#define RCC_CIR_LSIRDYF_Pos (0U)
+#define RCC_CIR_LSIRDYF_Msk (0x1U << RCC_CIR_LSIRDYF_Pos) /*!< 0x00000001 */
+#define RCC_CIR_LSIRDYF RCC_CIR_LSIRDYF_Msk /*!< LSI Ready Interrupt flag */
+#define RCC_CIR_LSERDYF_Pos (1U)
+#define RCC_CIR_LSERDYF_Msk (0x1U << RCC_CIR_LSERDYF_Pos) /*!< 0x00000002 */
+#define RCC_CIR_LSERDYF RCC_CIR_LSERDYF_Msk /*!< LSE Ready Interrupt flag */
+#define RCC_CIR_HSIRDYF_Pos (2U)
+#define RCC_CIR_HSIRDYF_Msk (0x1U << RCC_CIR_HSIRDYF_Pos) /*!< 0x00000004 */
+#define RCC_CIR_HSIRDYF RCC_CIR_HSIRDYF_Msk /*!< HSI Ready Interrupt flag */
+#define RCC_CIR_HSERDYF_Pos (3U)
+#define RCC_CIR_HSERDYF_Msk (0x1U << RCC_CIR_HSERDYF_Pos) /*!< 0x00000008 */
+#define RCC_CIR_HSERDYF RCC_CIR_HSERDYF_Msk /*!< HSE Ready Interrupt flag */
+#define RCC_CIR_PLLRDYF_Pos (4U)
+#define RCC_CIR_PLLRDYF_Msk (0x1U << RCC_CIR_PLLRDYF_Pos) /*!< 0x00000010 */
+#define RCC_CIR_PLLRDYF RCC_CIR_PLLRDYF_Msk /*!< PLL Ready Interrupt flag */
+#define RCC_CIR_CSSF_Pos (7U)
+#define RCC_CIR_CSSF_Msk (0x1U << RCC_CIR_CSSF_Pos) /*!< 0x00000080 */
+#define RCC_CIR_CSSF RCC_CIR_CSSF_Msk /*!< Clock Security System Interrupt flag */
+#define RCC_CIR_LSIRDYIE_Pos (8U)
+#define RCC_CIR_LSIRDYIE_Msk (0x1U << RCC_CIR_LSIRDYIE_Pos) /*!< 0x00000100 */
+#define RCC_CIR_LSIRDYIE RCC_CIR_LSIRDYIE_Msk /*!< LSI Ready Interrupt Enable */
+#define RCC_CIR_LSERDYIE_Pos (9U)
+#define RCC_CIR_LSERDYIE_Msk (0x1U << RCC_CIR_LSERDYIE_Pos) /*!< 0x00000200 */
+#define RCC_CIR_LSERDYIE RCC_CIR_LSERDYIE_Msk /*!< LSE Ready Interrupt Enable */
+#define RCC_CIR_HSIRDYIE_Pos (10U)
+#define RCC_CIR_HSIRDYIE_Msk (0x1U << RCC_CIR_HSIRDYIE_Pos) /*!< 0x00000400 */
+#define RCC_CIR_HSIRDYIE RCC_CIR_HSIRDYIE_Msk /*!< HSI Ready Interrupt Enable */
+#define RCC_CIR_HSERDYIE_Pos (11U)
+#define RCC_CIR_HSERDYIE_Msk (0x1U << RCC_CIR_HSERDYIE_Pos) /*!< 0x00000800 */
+#define RCC_CIR_HSERDYIE RCC_CIR_HSERDYIE_Msk /*!< HSE Ready Interrupt Enable */
+#define RCC_CIR_PLLRDYIE_Pos (12U)
+#define RCC_CIR_PLLRDYIE_Msk (0x1U << RCC_CIR_PLLRDYIE_Pos) /*!< 0x00001000 */
+#define RCC_CIR_PLLRDYIE RCC_CIR_PLLRDYIE_Msk /*!< PLL Ready Interrupt Enable */
+#define RCC_CIR_LSIRDYC_Pos (16U)
+#define RCC_CIR_LSIRDYC_Msk (0x1U << RCC_CIR_LSIRDYC_Pos) /*!< 0x00010000 */
+#define RCC_CIR_LSIRDYC RCC_CIR_LSIRDYC_Msk /*!< LSI Ready Interrupt Clear */
+#define RCC_CIR_LSERDYC_Pos (17U)
+#define RCC_CIR_LSERDYC_Msk (0x1U << RCC_CIR_LSERDYC_Pos) /*!< 0x00020000 */
+#define RCC_CIR_LSERDYC RCC_CIR_LSERDYC_Msk /*!< LSE Ready Interrupt Clear */
+#define RCC_CIR_HSIRDYC_Pos (18U)
+#define RCC_CIR_HSIRDYC_Msk (0x1U << RCC_CIR_HSIRDYC_Pos) /*!< 0x00040000 */
+#define RCC_CIR_HSIRDYC RCC_CIR_HSIRDYC_Msk /*!< HSI Ready Interrupt Clear */
+#define RCC_CIR_HSERDYC_Pos (19U)
+#define RCC_CIR_HSERDYC_Msk (0x1U << RCC_CIR_HSERDYC_Pos) /*!< 0x00080000 */
+#define RCC_CIR_HSERDYC RCC_CIR_HSERDYC_Msk /*!< HSE Ready Interrupt Clear */
+#define RCC_CIR_PLLRDYC_Pos (20U)
+#define RCC_CIR_PLLRDYC_Msk (0x1U << RCC_CIR_PLLRDYC_Pos) /*!< 0x00100000 */
+#define RCC_CIR_PLLRDYC RCC_CIR_PLLRDYC_Msk /*!< PLL Ready Interrupt Clear */
+#define RCC_CIR_CSSC_Pos (23U)
+#define RCC_CIR_CSSC_Msk (0x1U << RCC_CIR_CSSC_Pos) /*!< 0x00800000 */
+#define RCC_CIR_CSSC RCC_CIR_CSSC_Msk /*!< Clock Security System Interrupt Clear */
+
+
+/***************** Bit definition for RCC_APB2RSTR register *****************/
+#define RCC_APB2RSTR_AFIORST_Pos (0U)
+#define RCC_APB2RSTR_AFIORST_Msk (0x1U << RCC_APB2RSTR_AFIORST_Pos) /*!< 0x00000001 */
+#define RCC_APB2RSTR_AFIORST RCC_APB2RSTR_AFIORST_Msk /*!< Alternate Function I/O reset */
+#define RCC_APB2RSTR_IOPARST_Pos (2U)
+#define RCC_APB2RSTR_IOPARST_Msk (0x1U << RCC_APB2RSTR_IOPARST_Pos) /*!< 0x00000004 */
+#define RCC_APB2RSTR_IOPARST RCC_APB2RSTR_IOPARST_Msk /*!< I/O port A reset */
+#define RCC_APB2RSTR_IOPBRST_Pos (3U)
+#define RCC_APB2RSTR_IOPBRST_Msk (0x1U << RCC_APB2RSTR_IOPBRST_Pos) /*!< 0x00000008 */
+#define RCC_APB2RSTR_IOPBRST RCC_APB2RSTR_IOPBRST_Msk /*!< I/O port B reset */
+#define RCC_APB2RSTR_IOPCRST_Pos (4U)
+#define RCC_APB2RSTR_IOPCRST_Msk (0x1U << RCC_APB2RSTR_IOPCRST_Pos) /*!< 0x00000010 */
+#define RCC_APB2RSTR_IOPCRST RCC_APB2RSTR_IOPCRST_Msk /*!< I/O port C reset */
+#define RCC_APB2RSTR_IOPDRST_Pos (5U)
+#define RCC_APB2RSTR_IOPDRST_Msk (0x1U << RCC_APB2RSTR_IOPDRST_Pos) /*!< 0x00000020 */
+#define RCC_APB2RSTR_IOPDRST RCC_APB2RSTR_IOPDRST_Msk /*!< I/O port D reset */
+#define RCC_APB2RSTR_ADC1RST_Pos (9U)
+#define RCC_APB2RSTR_ADC1RST_Msk (0x1U << RCC_APB2RSTR_ADC1RST_Pos) /*!< 0x00000200 */
+#define RCC_APB2RSTR_ADC1RST RCC_APB2RSTR_ADC1RST_Msk /*!< ADC 1 interface reset */
+
+
+#define RCC_APB2RSTR_TIM1RST_Pos (11U)
+#define RCC_APB2RSTR_TIM1RST_Msk (0x1U << RCC_APB2RSTR_TIM1RST_Pos) /*!< 0x00000800 */
+#define RCC_APB2RSTR_TIM1RST RCC_APB2RSTR_TIM1RST_Msk /*!< TIM1 Timer reset */
+#define RCC_APB2RSTR_SPI1RST_Pos (12U)
+#define RCC_APB2RSTR_SPI1RST_Msk (0x1U << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */
+#define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk /*!< SPI 1 reset */
+#define RCC_APB2RSTR_USART1RST_Pos (14U)
+#define RCC_APB2RSTR_USART1RST_Msk (0x1U << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00004000 */
+#define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk /*!< USART1 reset */
+
+
+
+
+
+
+/***************** Bit definition for RCC_APB1RSTR register *****************/
+#define RCC_APB1RSTR_TIM2RST_Pos (0U)
+#define RCC_APB1RSTR_TIM2RST_Msk (0x1U << RCC_APB1RSTR_TIM2RST_Pos) /*!< 0x00000001 */
+#define RCC_APB1RSTR_TIM2RST RCC_APB1RSTR_TIM2RST_Msk /*!< Timer 2 reset */
+#define RCC_APB1RSTR_TIM3RST_Pos (1U)
+#define RCC_APB1RSTR_TIM3RST_Msk (0x1U << RCC_APB1RSTR_TIM3RST_Pos) /*!< 0x00000002 */
+#define RCC_APB1RSTR_TIM3RST RCC_APB1RSTR_TIM3RST_Msk /*!< Timer 3 reset */
+#define RCC_APB1RSTR_WWDGRST_Pos (11U)
+#define RCC_APB1RSTR_WWDGRST_Msk (0x1U << RCC_APB1RSTR_WWDGRST_Pos) /*!< 0x00000800 */
+#define RCC_APB1RSTR_WWDGRST RCC_APB1RSTR_WWDGRST_Msk /*!< Window Watchdog reset */
+#define RCC_APB1RSTR_USART2RST_Pos (17U)
+#define RCC_APB1RSTR_USART2RST_Msk (0x1U << RCC_APB1RSTR_USART2RST_Pos) /*!< 0x00020000 */
+#define RCC_APB1RSTR_USART2RST RCC_APB1RSTR_USART2RST_Msk /*!< USART 2 reset */
+#define RCC_APB1RSTR_I2C1RST_Pos (21U)
+#define RCC_APB1RSTR_I2C1RST_Msk (0x1U << RCC_APB1RSTR_I2C1RST_Pos) /*!< 0x00200000 */
+#define RCC_APB1RSTR_I2C1RST RCC_APB1RSTR_I2C1RST_Msk /*!< I2C 1 reset */
+
+
+#define RCC_APB1RSTR_BKPRST_Pos (27U)
+#define RCC_APB1RSTR_BKPRST_Msk (0x1U << RCC_APB1RSTR_BKPRST_Pos) /*!< 0x08000000 */
+#define RCC_APB1RSTR_BKPRST RCC_APB1RSTR_BKPRST_Msk /*!< Backup interface reset */
+#define RCC_APB1RSTR_PWRRST_Pos (28U)
+#define RCC_APB1RSTR_PWRRST_Msk (0x1U << RCC_APB1RSTR_PWRRST_Pos) /*!< 0x10000000 */
+#define RCC_APB1RSTR_PWRRST RCC_APB1RSTR_PWRRST_Msk /*!< Power interface reset */
+
+#define RCC_APB1RSTR_TIM4RST_Pos (2U)
+#define RCC_APB1RSTR_TIM4RST_Msk (0x1U << RCC_APB1RSTR_TIM4RST_Pos) /*!< 0x00000004 */
+#define RCC_APB1RSTR_TIM4RST RCC_APB1RSTR_TIM4RST_Msk /*!< Timer 4 reset */
+#define RCC_APB1RSTR_SPI2RST_Pos (14U)
+#define RCC_APB1RSTR_SPI2RST_Msk (0x1U << RCC_APB1RSTR_SPI2RST_Pos) /*!< 0x00004000 */
+#define RCC_APB1RSTR_SPI2RST RCC_APB1RSTR_SPI2RST_Msk /*!< SPI 2 reset */
+#define RCC_APB1RSTR_USART3RST_Pos (18U)
+#define RCC_APB1RSTR_USART3RST_Msk (0x1U << RCC_APB1RSTR_USART3RST_Pos) /*!< 0x00040000 */
+#define RCC_APB1RSTR_USART3RST RCC_APB1RSTR_USART3RST_Msk /*!< USART 3 reset */
+#define RCC_APB1RSTR_I2C2RST_Pos (22U)
+#define RCC_APB1RSTR_I2C2RST_Msk (0x1U << RCC_APB1RSTR_I2C2RST_Pos) /*!< 0x00400000 */
+#define RCC_APB1RSTR_I2C2RST RCC_APB1RSTR_I2C2RST_Msk /*!< I2C 2 reset */
+
+#define RCC_APB1RSTR_USBRST_Pos (23U)
+#define RCC_APB1RSTR_USBRST_Msk (0x1U << RCC_APB1RSTR_USBRST_Pos) /*!< 0x00800000 */
+#define RCC_APB1RSTR_USBRST RCC_APB1RSTR_USBRST_Msk /*!< USB Device reset */
+
+
+
+
+
+
+/****************** Bit definition for RCC_AHBENR register ******************/
+#define RCC_AHBENR_DMA1EN_Pos (0U)
+#define RCC_AHBENR_DMA1EN_Msk (0x1U << RCC_AHBENR_DMA1EN_Pos) /*!< 0x00000001 */
+#define RCC_AHBENR_DMA1EN RCC_AHBENR_DMA1EN_Msk /*!< DMA1 clock enable */
+#define RCC_AHBENR_SRAMEN_Pos (2U)
+#define RCC_AHBENR_SRAMEN_Msk (0x1U << RCC_AHBENR_SRAMEN_Pos) /*!< 0x00000004 */
+#define RCC_AHBENR_SRAMEN RCC_AHBENR_SRAMEN_Msk /*!< SRAM interface clock enable */
+#define RCC_AHBENR_FLITFEN_Pos (4U)
+#define RCC_AHBENR_FLITFEN_Msk (0x1U << RCC_AHBENR_FLITFEN_Pos) /*!< 0x00000010 */
+#define RCC_AHBENR_FLITFEN RCC_AHBENR_FLITFEN_Msk /*!< FLITF clock enable */
+#define RCC_AHBENR_CRCEN_Pos (6U)
+#define RCC_AHBENR_CRCEN_Msk (0x1U << RCC_AHBENR_CRCEN_Pos) /*!< 0x00000040 */
+#define RCC_AHBENR_CRCEN RCC_AHBENR_CRCEN_Msk /*!< CRC clock enable */
+
+
+
+
+/****************** Bit definition for RCC_APB2ENR register *****************/
+#define RCC_APB2ENR_AFIOEN_Pos (0U)
+#define RCC_APB2ENR_AFIOEN_Msk (0x1U << RCC_APB2ENR_AFIOEN_Pos) /*!< 0x00000001 */
+#define RCC_APB2ENR_AFIOEN RCC_APB2ENR_AFIOEN_Msk /*!< Alternate Function I/O clock enable */
+#define RCC_APB2ENR_IOPAEN_Pos (2U)
+#define RCC_APB2ENR_IOPAEN_Msk (0x1U << RCC_APB2ENR_IOPAEN_Pos) /*!< 0x00000004 */
+#define RCC_APB2ENR_IOPAEN RCC_APB2ENR_IOPAEN_Msk /*!< I/O port A clock enable */
+#define RCC_APB2ENR_IOPBEN_Pos (3U)
+#define RCC_APB2ENR_IOPBEN_Msk (0x1U << RCC_APB2ENR_IOPBEN_Pos) /*!< 0x00000008 */
+#define RCC_APB2ENR_IOPBEN RCC_APB2ENR_IOPBEN_Msk /*!< I/O port B clock enable */
+#define RCC_APB2ENR_IOPCEN_Pos (4U)
+#define RCC_APB2ENR_IOPCEN_Msk (0x1U << RCC_APB2ENR_IOPCEN_Pos) /*!< 0x00000010 */
+#define RCC_APB2ENR_IOPCEN RCC_APB2ENR_IOPCEN_Msk /*!< I/O port C clock enable */
+#define RCC_APB2ENR_IOPDEN_Pos (5U)
+#define RCC_APB2ENR_IOPDEN_Msk (0x1U << RCC_APB2ENR_IOPDEN_Pos) /*!< 0x00000020 */
+#define RCC_APB2ENR_IOPDEN RCC_APB2ENR_IOPDEN_Msk /*!< I/O port D clock enable */
+#define RCC_APB2ENR_ADC1EN_Pos (9U)
+#define RCC_APB2ENR_ADC1EN_Msk (0x1U << RCC_APB2ENR_ADC1EN_Pos) /*!< 0x00000200 */
+#define RCC_APB2ENR_ADC1EN RCC_APB2ENR_ADC1EN_Msk /*!< ADC 1 interface clock enable */
+
+
+#define RCC_APB2ENR_TIM1EN_Pos (11U)
+#define RCC_APB2ENR_TIM1EN_Msk (0x1U << RCC_APB2ENR_TIM1EN_Pos) /*!< 0x00000800 */
+#define RCC_APB2ENR_TIM1EN RCC_APB2ENR_TIM1EN_Msk /*!< TIM1 Timer clock enable */
+#define RCC_APB2ENR_SPI1EN_Pos (12U)
+#define RCC_APB2ENR_SPI1EN_Msk (0x1U << RCC_APB2ENR_SPI1EN_Pos) /*!< 0x00001000 */
+#define RCC_APB2ENR_SPI1EN RCC_APB2ENR_SPI1EN_Msk /*!< SPI 1 clock enable */
+#define RCC_APB2ENR_USART1EN_Pos (14U)
+#define RCC_APB2ENR_USART1EN_Msk (0x1U << RCC_APB2ENR_USART1EN_Pos) /*!< 0x00004000 */
+#define RCC_APB2ENR_USART1EN RCC_APB2ENR_USART1EN_Msk /*!< USART1 clock enable */
+
+
+
+
+
+
+/***************** Bit definition for RCC_APB1ENR register ******************/
+#define RCC_APB1ENR_TIM2EN_Pos (0U)
+#define RCC_APB1ENR_TIM2EN_Msk (0x1U << RCC_APB1ENR_TIM2EN_Pos) /*!< 0x00000001 */
+#define RCC_APB1ENR_TIM2EN RCC_APB1ENR_TIM2EN_Msk /*!< Timer 2 clock enabled*/
+#define RCC_APB1ENR_TIM3EN_Pos (1U)
+#define RCC_APB1ENR_TIM3EN_Msk (0x1U << RCC_APB1ENR_TIM3EN_Pos) /*!< 0x00000002 */
+#define RCC_APB1ENR_TIM3EN RCC_APB1ENR_TIM3EN_Msk /*!< Timer 3 clock enable */
+#define RCC_APB1ENR_WWDGEN_Pos (11U)
+#define RCC_APB1ENR_WWDGEN_Msk (0x1U << RCC_APB1ENR_WWDGEN_Pos) /*!< 0x00000800 */
+#define RCC_APB1ENR_WWDGEN RCC_APB1ENR_WWDGEN_Msk /*!< Window Watchdog clock enable */
+#define RCC_APB1ENR_USART2EN_Pos (17U)
+#define RCC_APB1ENR_USART2EN_Msk (0x1U << RCC_APB1ENR_USART2EN_Pos) /*!< 0x00020000 */
+#define RCC_APB1ENR_USART2EN RCC_APB1ENR_USART2EN_Msk /*!< USART 2 clock enable */
+#define RCC_APB1ENR_I2C1EN_Pos (21U)
+#define RCC_APB1ENR_I2C1EN_Msk (0x1U << RCC_APB1ENR_I2C1EN_Pos) /*!< 0x00200000 */
+#define RCC_APB1ENR_I2C1EN RCC_APB1ENR_I2C1EN_Msk /*!< I2C 1 clock enable */
+
+
+#define RCC_APB1ENR_BKPEN_Pos (27U)
+#define RCC_APB1ENR_BKPEN_Msk (0x1U << RCC_APB1ENR_BKPEN_Pos) /*!< 0x08000000 */
+#define RCC_APB1ENR_BKPEN RCC_APB1ENR_BKPEN_Msk /*!< Backup interface clock enable */
+#define RCC_APB1ENR_PWREN_Pos (28U)
+#define RCC_APB1ENR_PWREN_Msk (0x1U << RCC_APB1ENR_PWREN_Pos) /*!< 0x10000000 */
+#define RCC_APB1ENR_PWREN RCC_APB1ENR_PWREN_Msk /*!< Power interface clock enable */
+
+#define RCC_APB1ENR_TIM4EN_Pos (2U)
+#define RCC_APB1ENR_TIM4EN_Msk (0x1U << RCC_APB1ENR_TIM4EN_Pos) /*!< 0x00000004 */
+#define RCC_APB1ENR_TIM4EN RCC_APB1ENR_TIM4EN_Msk /*!< Timer 4 clock enable */
+#define RCC_APB1ENR_SPI2EN_Pos (14U)
+#define RCC_APB1ENR_SPI2EN_Msk (0x1U << RCC_APB1ENR_SPI2EN_Pos) /*!< 0x00004000 */
+#define RCC_APB1ENR_SPI2EN RCC_APB1ENR_SPI2EN_Msk /*!< SPI 2 clock enable */
+#define RCC_APB1ENR_USART3EN_Pos (18U)
+#define RCC_APB1ENR_USART3EN_Msk (0x1U << RCC_APB1ENR_USART3EN_Pos) /*!< 0x00040000 */
+#define RCC_APB1ENR_USART3EN RCC_APB1ENR_USART3EN_Msk /*!< USART 3 clock enable */
+#define RCC_APB1ENR_I2C2EN_Pos (22U)
+#define RCC_APB1ENR_I2C2EN_Msk (0x1U << RCC_APB1ENR_I2C2EN_Pos) /*!< 0x00400000 */
+#define RCC_APB1ENR_I2C2EN RCC_APB1ENR_I2C2EN_Msk /*!< I2C 2 clock enable */
+
+#define RCC_APB1ENR_USBEN_Pos (23U)
+#define RCC_APB1ENR_USBEN_Msk (0x1U << RCC_APB1ENR_USBEN_Pos) /*!< 0x00800000 */
+#define RCC_APB1ENR_USBEN RCC_APB1ENR_USBEN_Msk /*!< USB Device clock enable */
+
+
+
+
+
+
+/******************* Bit definition for RCC_BDCR register *******************/
+#define RCC_BDCR_LSEON_Pos (0U)
+#define RCC_BDCR_LSEON_Msk (0x1U << RCC_BDCR_LSEON_Pos) /*!< 0x00000001 */
+#define RCC_BDCR_LSEON RCC_BDCR_LSEON_Msk /*!< External Low Speed oscillator enable */
+#define RCC_BDCR_LSERDY_Pos (1U)
+#define RCC_BDCR_LSERDY_Msk (0x1U << RCC_BDCR_LSERDY_Pos) /*!< 0x00000002 */
+#define RCC_BDCR_LSERDY RCC_BDCR_LSERDY_Msk /*!< External Low Speed oscillator Ready */
+#define RCC_BDCR_LSEBYP_Pos (2U)
+#define RCC_BDCR_LSEBYP_Msk (0x1U << RCC_BDCR_LSEBYP_Pos) /*!< 0x00000004 */
+#define RCC_BDCR_LSEBYP RCC_BDCR_LSEBYP_Msk /*!< External Low Speed oscillator Bypass */
+
+#define RCC_BDCR_RTCSEL_Pos (8U)
+#define RCC_BDCR_RTCSEL_Msk (0x3U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000300 */
+#define RCC_BDCR_RTCSEL RCC_BDCR_RTCSEL_Msk /*!< RTCSEL[1:0] bits (RTC clock source selection) */
+#define RCC_BDCR_RTCSEL_0 (0x1U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000100 */
+#define RCC_BDCR_RTCSEL_1 (0x2U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000200 */
+
+/*!< RTC congiguration */
+#define RCC_BDCR_RTCSEL_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */
+#define RCC_BDCR_RTCSEL_LSE ((uint32_t)0x00000100) /*!< LSE oscillator clock used as RTC clock */
+#define RCC_BDCR_RTCSEL_LSI ((uint32_t)0x00000200) /*!< LSI oscillator clock used as RTC clock */
+#define RCC_BDCR_RTCSEL_HSE ((uint32_t)0x00000300) /*!< HSE oscillator clock divided by 128 used as RTC clock */
+
+#define RCC_BDCR_RTCEN_Pos (15U)
+#define RCC_BDCR_RTCEN_Msk (0x1U << RCC_BDCR_RTCEN_Pos) /*!< 0x00008000 */
+#define RCC_BDCR_RTCEN RCC_BDCR_RTCEN_Msk /*!< RTC clock enable */
+#define RCC_BDCR_BDRST_Pos (16U)
+#define RCC_BDCR_BDRST_Msk (0x1U << RCC_BDCR_BDRST_Pos) /*!< 0x00010000 */
+#define RCC_BDCR_BDRST RCC_BDCR_BDRST_Msk /*!< Backup domain software reset */
+
+/******************* Bit definition for RCC_CSR register ********************/
+#define RCC_CSR_LSION_Pos (0U)
+#define RCC_CSR_LSION_Msk (0x1U << RCC_CSR_LSION_Pos) /*!< 0x00000001 */
+#define RCC_CSR_LSION RCC_CSR_LSION_Msk /*!< Internal Low Speed oscillator enable */
+#define RCC_CSR_LSIRDY_Pos (1U)
+#define RCC_CSR_LSIRDY_Msk (0x1U << RCC_CSR_LSIRDY_Pos) /*!< 0x00000002 */
+#define RCC_CSR_LSIRDY RCC_CSR_LSIRDY_Msk /*!< Internal Low Speed oscillator Ready */
+#define RCC_CSR_RMVF_Pos (24U)
+#define RCC_CSR_RMVF_Msk (0x1U << RCC_CSR_RMVF_Pos) /*!< 0x01000000 */
+#define RCC_CSR_RMVF RCC_CSR_RMVF_Msk /*!< Remove reset flag */
+#define RCC_CSR_PINRSTF_Pos (26U)
+#define RCC_CSR_PINRSTF_Msk (0x1U << RCC_CSR_PINRSTF_Pos) /*!< 0x04000000 */
+#define RCC_CSR_PINRSTF RCC_CSR_PINRSTF_Msk /*!< PIN reset flag */
+#define RCC_CSR_PORRSTF_Pos (27U)
+#define RCC_CSR_PORRSTF_Msk (0x1U << RCC_CSR_PORRSTF_Pos) /*!< 0x08000000 */
+#define RCC_CSR_PORRSTF RCC_CSR_PORRSTF_Msk /*!< POR/PDR reset flag */
+#define RCC_CSR_SFTRSTF_Pos (28U)
+#define RCC_CSR_SFTRSTF_Msk (0x1U << RCC_CSR_SFTRSTF_Pos) /*!< 0x10000000 */
+#define RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF_Msk /*!< Software Reset flag */
+#define RCC_CSR_IWDGRSTF_Pos (29U)
+#define RCC_CSR_IWDGRSTF_Msk (0x1U << RCC_CSR_IWDGRSTF_Pos) /*!< 0x20000000 */
+#define RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF_Msk /*!< Independent Watchdog reset flag */
+#define RCC_CSR_WWDGRSTF_Pos (30U)
+#define RCC_CSR_WWDGRSTF_Msk (0x1U << RCC_CSR_WWDGRSTF_Pos) /*!< 0x40000000 */
+#define RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF_Msk /*!< Window watchdog reset flag */
+#define RCC_CSR_LPWRRSTF_Pos (31U)
+#define RCC_CSR_LPWRRSTF_Msk (0x1U << RCC_CSR_LPWRRSTF_Pos) /*!< 0x80000000 */
+#define RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF_Msk /*!< Low-Power reset flag */
+
+
+
+/******************************************************************************/
+/* */
+/* General Purpose and Alternate Function I/O */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for GPIO_CRL register *******************/
+#define GPIO_CRL_MODE_Pos (0U)
+#define GPIO_CRL_MODE_Msk (0x33333333U << GPIO_CRL_MODE_Pos) /*!< 0x33333333 */
+#define GPIO_CRL_MODE GPIO_CRL_MODE_Msk /*!< Port x mode bits */
+
+#define GPIO_CRL_MODE0_Pos (0U)
+#define GPIO_CRL_MODE0_Msk (0x3U << GPIO_CRL_MODE0_Pos) /*!< 0x00000003 */
+#define GPIO_CRL_MODE0 GPIO_CRL_MODE0_Msk /*!< MODE0[1:0] bits (Port x mode bits, pin 0) */
+#define GPIO_CRL_MODE0_0 (0x1U << GPIO_CRL_MODE0_Pos) /*!< 0x00000001 */
+#define GPIO_CRL_MODE0_1 (0x2U << GPIO_CRL_MODE0_Pos) /*!< 0x00000002 */
+
+#define GPIO_CRL_MODE1_Pos (4U)
+#define GPIO_CRL_MODE1_Msk (0x3U << GPIO_CRL_MODE1_Pos) /*!< 0x00000030 */
+#define GPIO_CRL_MODE1 GPIO_CRL_MODE1_Msk /*!< MODE1[1:0] bits (Port x mode bits, pin 1) */
+#define GPIO_CRL_MODE1_0 (0x1U << GPIO_CRL_MODE1_Pos) /*!< 0x00000010 */
+#define GPIO_CRL_MODE1_1 (0x2U << GPIO_CRL_MODE1_Pos) /*!< 0x00000020 */
+
+#define GPIO_CRL_MODE2_Pos (8U)
+#define GPIO_CRL_MODE2_Msk (0x3U << GPIO_CRL_MODE2_Pos) /*!< 0x00000300 */
+#define GPIO_CRL_MODE2 GPIO_CRL_MODE2_Msk /*!< MODE2[1:0] bits (Port x mode bits, pin 2) */
+#define GPIO_CRL_MODE2_0 (0x1U << GPIO_CRL_MODE2_Pos) /*!< 0x00000100 */
+#define GPIO_CRL_MODE2_1 (0x2U << GPIO_CRL_MODE2_Pos) /*!< 0x00000200 */
+
+#define GPIO_CRL_MODE3_Pos (12U)
+#define GPIO_CRL_MODE3_Msk (0x3U << GPIO_CRL_MODE3_Pos) /*!< 0x00003000 */
+#define GPIO_CRL_MODE3 GPIO_CRL_MODE3_Msk /*!< MODE3[1:0] bits (Port x mode bits, pin 3) */
+#define GPIO_CRL_MODE3_0 (0x1U << GPIO_CRL_MODE3_Pos) /*!< 0x00001000 */
+#define GPIO_CRL_MODE3_1 (0x2U << GPIO_CRL_MODE3_Pos) /*!< 0x00002000 */
+
+#define GPIO_CRL_MODE4_Pos (16U)
+#define GPIO_CRL_MODE4_Msk (0x3U << GPIO_CRL_MODE4_Pos) /*!< 0x00030000 */
+#define GPIO_CRL_MODE4 GPIO_CRL_MODE4_Msk /*!< MODE4[1:0] bits (Port x mode bits, pin 4) */
+#define GPIO_CRL_MODE4_0 (0x1U << GPIO_CRL_MODE4_Pos) /*!< 0x00010000 */
+#define GPIO_CRL_MODE4_1 (0x2U << GPIO_CRL_MODE4_Pos) /*!< 0x00020000 */
+
+#define GPIO_CRL_MODE5_Pos (20U)
+#define GPIO_CRL_MODE5_Msk (0x3U << GPIO_CRL_MODE5_Pos) /*!< 0x00300000 */
+#define GPIO_CRL_MODE5 GPIO_CRL_MODE5_Msk /*!< MODE5[1:0] bits (Port x mode bits, pin 5) */
+#define GPIO_CRL_MODE5_0 (0x1U << GPIO_CRL_MODE5_Pos) /*!< 0x00100000 */
+#define GPIO_CRL_MODE5_1 (0x2U << GPIO_CRL_MODE5_Pos) /*!< 0x00200000 */
+
+#define GPIO_CRL_MODE6_Pos (24U)
+#define GPIO_CRL_MODE6_Msk (0x3U << GPIO_CRL_MODE6_Pos) /*!< 0x03000000 */
+#define GPIO_CRL_MODE6 GPIO_CRL_MODE6_Msk /*!< MODE6[1:0] bits (Port x mode bits, pin 6) */
+#define GPIO_CRL_MODE6_0 (0x1U << GPIO_CRL_MODE6_Pos) /*!< 0x01000000 */
+#define GPIO_CRL_MODE6_1 (0x2U << GPIO_CRL_MODE6_Pos) /*!< 0x02000000 */
+
+#define GPIO_CRL_MODE7_Pos (28U)
+#define GPIO_CRL_MODE7_Msk (0x3U << GPIO_CRL_MODE7_Pos) /*!< 0x30000000 */
+#define GPIO_CRL_MODE7 GPIO_CRL_MODE7_Msk /*!< MODE7[1:0] bits (Port x mode bits, pin 7) */
+#define GPIO_CRL_MODE7_0 (0x1U << GPIO_CRL_MODE7_Pos) /*!< 0x10000000 */
+#define GPIO_CRL_MODE7_1 (0x2U << GPIO_CRL_MODE7_Pos) /*!< 0x20000000 */
+
+#define GPIO_CRL_CNF_Pos (2U)
+#define GPIO_CRL_CNF_Msk (0x33333333U << GPIO_CRL_CNF_Pos) /*!< 0xCCCCCCCC */
+#define GPIO_CRL_CNF GPIO_CRL_CNF_Msk /*!< Port x configuration bits */
+
+#define GPIO_CRL_CNF0_Pos (2U)
+#define GPIO_CRL_CNF0_Msk (0x3U << GPIO_CRL_CNF0_Pos) /*!< 0x0000000C */
+#define GPIO_CRL_CNF0 GPIO_CRL_CNF0_Msk /*!< CNF0[1:0] bits (Port x configuration bits, pin 0) */
+#define GPIO_CRL_CNF0_0 (0x1U << GPIO_CRL_CNF0_Pos) /*!< 0x00000004 */
+#define GPIO_CRL_CNF0_1 (0x2U << GPIO_CRL_CNF0_Pos) /*!< 0x00000008 */
+
+#define GPIO_CRL_CNF1_Pos (6U)
+#define GPIO_CRL_CNF1_Msk (0x3U << GPIO_CRL_CNF1_Pos) /*!< 0x000000C0 */
+#define GPIO_CRL_CNF1 GPIO_CRL_CNF1_Msk /*!< CNF1[1:0] bits (Port x configuration bits, pin 1) */
+#define GPIO_CRL_CNF1_0 (0x1U << GPIO_CRL_CNF1_Pos) /*!< 0x00000040 */
+#define GPIO_CRL_CNF1_1 (0x2U << GPIO_CRL_CNF1_Pos) /*!< 0x00000080 */
+
+#define GPIO_CRL_CNF2_Pos (10U)
+#define GPIO_CRL_CNF2_Msk (0x3U << GPIO_CRL_CNF2_Pos) /*!< 0x00000C00 */
+#define GPIO_CRL_CNF2 GPIO_CRL_CNF2_Msk /*!< CNF2[1:0] bits (Port x configuration bits, pin 2) */
+#define GPIO_CRL_CNF2_0 (0x1U << GPIO_CRL_CNF2_Pos) /*!< 0x00000400 */
+#define GPIO_CRL_CNF2_1 (0x2U << GPIO_CRL_CNF2_Pos) /*!< 0x00000800 */
+
+#define GPIO_CRL_CNF3_Pos (14U)
+#define GPIO_CRL_CNF3_Msk (0x3U << GPIO_CRL_CNF3_Pos) /*!< 0x0000C000 */
+#define GPIO_CRL_CNF3 GPIO_CRL_CNF3_Msk /*!< CNF3[1:0] bits (Port x configuration bits, pin 3) */
+#define GPIO_CRL_CNF3_0 (0x1U << GPIO_CRL_CNF3_Pos) /*!< 0x00004000 */
+#define GPIO_CRL_CNF3_1 (0x2U << GPIO_CRL_CNF3_Pos) /*!< 0x00008000 */
+
+#define GPIO_CRL_CNF4_Pos (18U)
+#define GPIO_CRL_CNF4_Msk (0x3U << GPIO_CRL_CNF4_Pos) /*!< 0x000C0000 */
+#define GPIO_CRL_CNF4 GPIO_CRL_CNF4_Msk /*!< CNF4[1:0] bits (Port x configuration bits, pin 4) */
+#define GPIO_CRL_CNF4_0 (0x1U << GPIO_CRL_CNF4_Pos) /*!< 0x00040000 */
+#define GPIO_CRL_CNF4_1 (0x2U << GPIO_CRL_CNF4_Pos) /*!< 0x00080000 */
+
+#define GPIO_CRL_CNF5_Pos (22U)
+#define GPIO_CRL_CNF5_Msk (0x3U << GPIO_CRL_CNF5_Pos) /*!< 0x00C00000 */
+#define GPIO_CRL_CNF5 GPIO_CRL_CNF5_Msk /*!< CNF5[1:0] bits (Port x configuration bits, pin 5) */
+#define GPIO_CRL_CNF5_0 (0x1U << GPIO_CRL_CNF5_Pos) /*!< 0x00400000 */
+#define GPIO_CRL_CNF5_1 (0x2U << GPIO_CRL_CNF5_Pos) /*!< 0x00800000 */
+
+#define GPIO_CRL_CNF6_Pos (26U)
+#define GPIO_CRL_CNF6_Msk (0x3U << GPIO_CRL_CNF6_Pos) /*!< 0x0C000000 */
+#define GPIO_CRL_CNF6 GPIO_CRL_CNF6_Msk /*!< CNF6[1:0] bits (Port x configuration bits, pin 6) */
+#define GPIO_CRL_CNF6_0 (0x1U << GPIO_CRL_CNF6_Pos) /*!< 0x04000000 */
+#define GPIO_CRL_CNF6_1 (0x2U << GPIO_CRL_CNF6_Pos) /*!< 0x08000000 */
+
+#define GPIO_CRL_CNF7_Pos (30U)
+#define GPIO_CRL_CNF7_Msk (0x3U << GPIO_CRL_CNF7_Pos) /*!< 0xC0000000 */
+#define GPIO_CRL_CNF7 GPIO_CRL_CNF7_Msk /*!< CNF7[1:0] bits (Port x configuration bits, pin 7) */
+#define GPIO_CRL_CNF7_0 (0x1U << GPIO_CRL_CNF7_Pos) /*!< 0x40000000 */
+#define GPIO_CRL_CNF7_1 (0x2U << GPIO_CRL_CNF7_Pos) /*!< 0x80000000 */
+
+/******************* Bit definition for GPIO_CRH register *******************/
+#define GPIO_CRH_MODE_Pos (0U)
+#define GPIO_CRH_MODE_Msk (0x33333333U << GPIO_CRH_MODE_Pos) /*!< 0x33333333 */
+#define GPIO_CRH_MODE GPIO_CRH_MODE_Msk /*!< Port x mode bits */
+
+#define GPIO_CRH_MODE8_Pos (0U)
+#define GPIO_CRH_MODE8_Msk (0x3U << GPIO_CRH_MODE8_Pos) /*!< 0x00000003 */
+#define GPIO_CRH_MODE8 GPIO_CRH_MODE8_Msk /*!< MODE8[1:0] bits (Port x mode bits, pin 8) */
+#define GPIO_CRH_MODE8_0 (0x1U << GPIO_CRH_MODE8_Pos) /*!< 0x00000001 */
+#define GPIO_CRH_MODE8_1 (0x2U << GPIO_CRH_MODE8_Pos) /*!< 0x00000002 */
+
+#define GPIO_CRH_MODE9_Pos (4U)
+#define GPIO_CRH_MODE9_Msk (0x3U << GPIO_CRH_MODE9_Pos) /*!< 0x00000030 */
+#define GPIO_CRH_MODE9 GPIO_CRH_MODE9_Msk /*!< MODE9[1:0] bits (Port x mode bits, pin 9) */
+#define GPIO_CRH_MODE9_0 (0x1U << GPIO_CRH_MODE9_Pos) /*!< 0x00000010 */
+#define GPIO_CRH_MODE9_1 (0x2U << GPIO_CRH_MODE9_Pos) /*!< 0x00000020 */
+
+#define GPIO_CRH_MODE10_Pos (8U)
+#define GPIO_CRH_MODE10_Msk (0x3U << GPIO_CRH_MODE10_Pos) /*!< 0x00000300 */
+#define GPIO_CRH_MODE10 GPIO_CRH_MODE10_Msk /*!< MODE10[1:0] bits (Port x mode bits, pin 10) */
+#define GPIO_CRH_MODE10_0 (0x1U << GPIO_CRH_MODE10_Pos) /*!< 0x00000100 */
+#define GPIO_CRH_MODE10_1 (0x2U << GPIO_CRH_MODE10_Pos) /*!< 0x00000200 */
+
+#define GPIO_CRH_MODE11_Pos (12U)
+#define GPIO_CRH_MODE11_Msk (0x3U << GPIO_CRH_MODE11_Pos) /*!< 0x00003000 */
+#define GPIO_CRH_MODE11 GPIO_CRH_MODE11_Msk /*!< MODE11[1:0] bits (Port x mode bits, pin 11) */
+#define GPIO_CRH_MODE11_0 (0x1U << GPIO_CRH_MODE11_Pos) /*!< 0x00001000 */
+#define GPIO_CRH_MODE11_1 (0x2U << GPIO_CRH_MODE11_Pos) /*!< 0x00002000 */
+
+#define GPIO_CRH_MODE12_Pos (16U)
+#define GPIO_CRH_MODE12_Msk (0x3U << GPIO_CRH_MODE12_Pos) /*!< 0x00030000 */
+#define GPIO_CRH_MODE12 GPIO_CRH_MODE12_Msk /*!< MODE12[1:0] bits (Port x mode bits, pin 12) */
+#define GPIO_CRH_MODE12_0 (0x1U << GPIO_CRH_MODE12_Pos) /*!< 0x00010000 */
+#define GPIO_CRH_MODE12_1 (0x2U << GPIO_CRH_MODE12_Pos) /*!< 0x00020000 */
+
+#define GPIO_CRH_MODE13_Pos (20U)
+#define GPIO_CRH_MODE13_Msk (0x3U << GPIO_CRH_MODE13_Pos) /*!< 0x00300000 */
+#define GPIO_CRH_MODE13 GPIO_CRH_MODE13_Msk /*!< MODE13[1:0] bits (Port x mode bits, pin 13) */
+#define GPIO_CRH_MODE13_0 (0x1U << GPIO_CRH_MODE13_Pos) /*!< 0x00100000 */
+#define GPIO_CRH_MODE13_1 (0x2U << GPIO_CRH_MODE13_Pos) /*!< 0x00200000 */
+
+#define GPIO_CRH_MODE14_Pos (24U)
+#define GPIO_CRH_MODE14_Msk (0x3U << GPIO_CRH_MODE14_Pos) /*!< 0x03000000 */
+#define GPIO_CRH_MODE14 GPIO_CRH_MODE14_Msk /*!< MODE14[1:0] bits (Port x mode bits, pin 14) */
+#define GPIO_CRH_MODE14_0 (0x1U << GPIO_CRH_MODE14_Pos) /*!< 0x01000000 */
+#define GPIO_CRH_MODE14_1 (0x2U << GPIO_CRH_MODE14_Pos) /*!< 0x02000000 */
+
+#define GPIO_CRH_MODE15_Pos (28U)
+#define GPIO_CRH_MODE15_Msk (0x3U << GPIO_CRH_MODE15_Pos) /*!< 0x30000000 */
+#define GPIO_CRH_MODE15 GPIO_CRH_MODE15_Msk /*!< MODE15[1:0] bits (Port x mode bits, pin 15) */
+#define GPIO_CRH_MODE15_0 (0x1U << GPIO_CRH_MODE15_Pos) /*!< 0x10000000 */
+#define GPIO_CRH_MODE15_1 (0x2U << GPIO_CRH_MODE15_Pos) /*!< 0x20000000 */
+
+#define GPIO_CRH_CNF_Pos (2U)
+#define GPIO_CRH_CNF_Msk (0x33333333U << GPIO_CRH_CNF_Pos) /*!< 0xCCCCCCCC */
+#define GPIO_CRH_CNF GPIO_CRH_CNF_Msk /*!< Port x configuration bits */
+
+#define GPIO_CRH_CNF8_Pos (2U)
+#define GPIO_CRH_CNF8_Msk (0x3U << GPIO_CRH_CNF8_Pos) /*!< 0x0000000C */
+#define GPIO_CRH_CNF8 GPIO_CRH_CNF8_Msk /*!< CNF8[1:0] bits (Port x configuration bits, pin 8) */
+#define GPIO_CRH_CNF8_0 (0x1U << GPIO_CRH_CNF8_Pos) /*!< 0x00000004 */
+#define GPIO_CRH_CNF8_1 (0x2U << GPIO_CRH_CNF8_Pos) /*!< 0x00000008 */
+
+#define GPIO_CRH_CNF9_Pos (6U)
+#define GPIO_CRH_CNF9_Msk (0x3U << GPIO_CRH_CNF9_Pos) /*!< 0x000000C0 */
+#define GPIO_CRH_CNF9 GPIO_CRH_CNF9_Msk /*!< CNF9[1:0] bits (Port x configuration bits, pin 9) */
+#define GPIO_CRH_CNF9_0 (0x1U << GPIO_CRH_CNF9_Pos) /*!< 0x00000040 */
+#define GPIO_CRH_CNF9_1 (0x2U << GPIO_CRH_CNF9_Pos) /*!< 0x00000080 */
+
+#define GPIO_CRH_CNF10_Pos (10U)
+#define GPIO_CRH_CNF10_Msk (0x3U << GPIO_CRH_CNF10_Pos) /*!< 0x00000C00 */
+#define GPIO_CRH_CNF10 GPIO_CRH_CNF10_Msk /*!< CNF10[1:0] bits (Port x configuration bits, pin 10) */
+#define GPIO_CRH_CNF10_0 (0x1U << GPIO_CRH_CNF10_Pos) /*!< 0x00000400 */
+#define GPIO_CRH_CNF10_1 (0x2U << GPIO_CRH_CNF10_Pos) /*!< 0x00000800 */
+
+#define GPIO_CRH_CNF11_Pos (14U)
+#define GPIO_CRH_CNF11_Msk (0x3U << GPIO_CRH_CNF11_Pos) /*!< 0x0000C000 */
+#define GPIO_CRH_CNF11 GPIO_CRH_CNF11_Msk /*!< CNF11[1:0] bits (Port x configuration bits, pin 11) */
+#define GPIO_CRH_CNF11_0 (0x1U << GPIO_CRH_CNF11_Pos) /*!< 0x00004000 */
+#define GPIO_CRH_CNF11_1 (0x2U << GPIO_CRH_CNF11_Pos) /*!< 0x00008000 */
+
+#define GPIO_CRH_CNF12_Pos (18U)
+#define GPIO_CRH_CNF12_Msk (0x3U << GPIO_CRH_CNF12_Pos) /*!< 0x000C0000 */
+#define GPIO_CRH_CNF12 GPIO_CRH_CNF12_Msk /*!< CNF12[1:0] bits (Port x configuration bits, pin 12) */
+#define GPIO_CRH_CNF12_0 (0x1U << GPIO_CRH_CNF12_Pos) /*!< 0x00040000 */
+#define GPIO_CRH_CNF12_1 (0x2U << GPIO_CRH_CNF12_Pos) /*!< 0x00080000 */
+
+#define GPIO_CRH_CNF13_Pos (22U)
+#define GPIO_CRH_CNF13_Msk (0x3U << GPIO_CRH_CNF13_Pos) /*!< 0x00C00000 */
+#define GPIO_CRH_CNF13 GPIO_CRH_CNF13_Msk /*!< CNF13[1:0] bits (Port x configuration bits, pin 13) */
+#define GPIO_CRH_CNF13_0 (0x1U << GPIO_CRH_CNF13_Pos) /*!< 0x00400000 */
+#define GPIO_CRH_CNF13_1 (0x2U << GPIO_CRH_CNF13_Pos) /*!< 0x00800000 */
+
+#define GPIO_CRH_CNF14_Pos (26U)
+#define GPIO_CRH_CNF14_Msk (0x3U << GPIO_CRH_CNF14_Pos) /*!< 0x0C000000 */
+#define GPIO_CRH_CNF14 GPIO_CRH_CNF14_Msk /*!< CNF14[1:0] bits (Port x configuration bits, pin 14) */
+#define GPIO_CRH_CNF14_0 (0x1U << GPIO_CRH_CNF14_Pos) /*!< 0x04000000 */
+#define GPIO_CRH_CNF14_1 (0x2U << GPIO_CRH_CNF14_Pos) /*!< 0x08000000 */
+
+#define GPIO_CRH_CNF15_Pos (30U)
+#define GPIO_CRH_CNF15_Msk (0x3U << GPIO_CRH_CNF15_Pos) /*!< 0xC0000000 */
+#define GPIO_CRH_CNF15 GPIO_CRH_CNF15_Msk /*!< CNF15[1:0] bits (Port x configuration bits, pin 15) */
+#define GPIO_CRH_CNF15_0 (0x1U << GPIO_CRH_CNF15_Pos) /*!< 0x40000000 */
+#define GPIO_CRH_CNF15_1 (0x2U << GPIO_CRH_CNF15_Pos) /*!< 0x80000000 */
+
+/*!<****************** Bit definition for GPIO_IDR register *******************/
+#define GPIO_IDR_IDR0_Pos (0U)
+#define GPIO_IDR_IDR0_Msk (0x1U << GPIO_IDR_IDR0_Pos) /*!< 0x00000001 */
+#define GPIO_IDR_IDR0 GPIO_IDR_IDR0_Msk /*!< Port input data, bit 0 */
+#define GPIO_IDR_IDR1_Pos (1U)
+#define GPIO_IDR_IDR1_Msk (0x1U << GPIO_IDR_IDR1_Pos) /*!< 0x00000002 */
+#define GPIO_IDR_IDR1 GPIO_IDR_IDR1_Msk /*!< Port input data, bit 1 */
+#define GPIO_IDR_IDR2_Pos (2U)
+#define GPIO_IDR_IDR2_Msk (0x1U << GPIO_IDR_IDR2_Pos) /*!< 0x00000004 */
+#define GPIO_IDR_IDR2 GPIO_IDR_IDR2_Msk /*!< Port input data, bit 2 */
+#define GPIO_IDR_IDR3_Pos (3U)
+#define GPIO_IDR_IDR3_Msk (0x1U << GPIO_IDR_IDR3_Pos) /*!< 0x00000008 */
+#define GPIO_IDR_IDR3 GPIO_IDR_IDR3_Msk /*!< Port input data, bit 3 */
+#define GPIO_IDR_IDR4_Pos (4U)
+#define GPIO_IDR_IDR4_Msk (0x1U << GPIO_IDR_IDR4_Pos) /*!< 0x00000010 */
+#define GPIO_IDR_IDR4 GPIO_IDR_IDR4_Msk /*!< Port input data, bit 4 */
+#define GPIO_IDR_IDR5_Pos (5U)
+#define GPIO_IDR_IDR5_Msk (0x1U << GPIO_IDR_IDR5_Pos) /*!< 0x00000020 */
+#define GPIO_IDR_IDR5 GPIO_IDR_IDR5_Msk /*!< Port input data, bit 5 */
+#define GPIO_IDR_IDR6_Pos (6U)
+#define GPIO_IDR_IDR6_Msk (0x1U << GPIO_IDR_IDR6_Pos) /*!< 0x00000040 */
+#define GPIO_IDR_IDR6 GPIO_IDR_IDR6_Msk /*!< Port input data, bit 6 */
+#define GPIO_IDR_IDR7_Pos (7U)
+#define GPIO_IDR_IDR7_Msk (0x1U << GPIO_IDR_IDR7_Pos) /*!< 0x00000080 */
+#define GPIO_IDR_IDR7 GPIO_IDR_IDR7_Msk /*!< Port input data, bit 7 */
+#define GPIO_IDR_IDR8_Pos (8U)
+#define GPIO_IDR_IDR8_Msk (0x1U << GPIO_IDR_IDR8_Pos) /*!< 0x00000100 */
+#define GPIO_IDR_IDR8 GPIO_IDR_IDR8_Msk /*!< Port input data, bit 8 */
+#define GPIO_IDR_IDR9_Pos (9U)
+#define GPIO_IDR_IDR9_Msk (0x1U << GPIO_IDR_IDR9_Pos) /*!< 0x00000200 */
+#define GPIO_IDR_IDR9 GPIO_IDR_IDR9_Msk /*!< Port input data, bit 9 */
+#define GPIO_IDR_IDR10_Pos (10U)
+#define GPIO_IDR_IDR10_Msk (0x1U << GPIO_IDR_IDR10_Pos) /*!< 0x00000400 */
+#define GPIO_IDR_IDR10 GPIO_IDR_IDR10_Msk /*!< Port input data, bit 10 */
+#define GPIO_IDR_IDR11_Pos (11U)
+#define GPIO_IDR_IDR11_Msk (0x1U << GPIO_IDR_IDR11_Pos) /*!< 0x00000800 */
+#define GPIO_IDR_IDR11 GPIO_IDR_IDR11_Msk /*!< Port input data, bit 11 */
+#define GPIO_IDR_IDR12_Pos (12U)
+#define GPIO_IDR_IDR12_Msk (0x1U << GPIO_IDR_IDR12_Pos) /*!< 0x00001000 */
+#define GPIO_IDR_IDR12 GPIO_IDR_IDR12_Msk /*!< Port input data, bit 12 */
+#define GPIO_IDR_IDR13_Pos (13U)
+#define GPIO_IDR_IDR13_Msk (0x1U << GPIO_IDR_IDR13_Pos) /*!< 0x00002000 */
+#define GPIO_IDR_IDR13 GPIO_IDR_IDR13_Msk /*!< Port input data, bit 13 */
+#define GPIO_IDR_IDR14_Pos (14U)
+#define GPIO_IDR_IDR14_Msk (0x1U << GPIO_IDR_IDR14_Pos) /*!< 0x00004000 */
+#define GPIO_IDR_IDR14 GPIO_IDR_IDR14_Msk /*!< Port input data, bit 14 */
+#define GPIO_IDR_IDR15_Pos (15U)
+#define GPIO_IDR_IDR15_Msk (0x1U << GPIO_IDR_IDR15_Pos) /*!< 0x00008000 */
+#define GPIO_IDR_IDR15 GPIO_IDR_IDR15_Msk /*!< Port input data, bit 15 */
+
+/******************* Bit definition for GPIO_ODR register *******************/
+#define GPIO_ODR_ODR0_Pos (0U)
+#define GPIO_ODR_ODR0_Msk (0x1U << GPIO_ODR_ODR0_Pos) /*!< 0x00000001 */
+#define GPIO_ODR_ODR0 GPIO_ODR_ODR0_Msk /*!< Port output data, bit 0 */
+#define GPIO_ODR_ODR1_Pos (1U)
+#define GPIO_ODR_ODR1_Msk (0x1U << GPIO_ODR_ODR1_Pos) /*!< 0x00000002 */
+#define GPIO_ODR_ODR1 GPIO_ODR_ODR1_Msk /*!< Port output data, bit 1 */
+#define GPIO_ODR_ODR2_Pos (2U)
+#define GPIO_ODR_ODR2_Msk (0x1U << GPIO_ODR_ODR2_Pos) /*!< 0x00000004 */
+#define GPIO_ODR_ODR2 GPIO_ODR_ODR2_Msk /*!< Port output data, bit 2 */
+#define GPIO_ODR_ODR3_Pos (3U)
+#define GPIO_ODR_ODR3_Msk (0x1U << GPIO_ODR_ODR3_Pos) /*!< 0x00000008 */
+#define GPIO_ODR_ODR3 GPIO_ODR_ODR3_Msk /*!< Port output data, bit 3 */
+#define GPIO_ODR_ODR4_Pos (4U)
+#define GPIO_ODR_ODR4_Msk (0x1U << GPIO_ODR_ODR4_Pos) /*!< 0x00000010 */
+#define GPIO_ODR_ODR4 GPIO_ODR_ODR4_Msk /*!< Port output data, bit 4 */
+#define GPIO_ODR_ODR5_Pos (5U)
+#define GPIO_ODR_ODR5_Msk (0x1U << GPIO_ODR_ODR5_Pos) /*!< 0x00000020 */
+#define GPIO_ODR_ODR5 GPIO_ODR_ODR5_Msk /*!< Port output data, bit 5 */
+#define GPIO_ODR_ODR6_Pos (6U)
+#define GPIO_ODR_ODR6_Msk (0x1U << GPIO_ODR_ODR6_Pos) /*!< 0x00000040 */
+#define GPIO_ODR_ODR6 GPIO_ODR_ODR6_Msk /*!< Port output data, bit 6 */
+#define GPIO_ODR_ODR7_Pos (7U)
+#define GPIO_ODR_ODR7_Msk (0x1U << GPIO_ODR_ODR7_Pos) /*!< 0x00000080 */
+#define GPIO_ODR_ODR7 GPIO_ODR_ODR7_Msk /*!< Port output data, bit 7 */
+#define GPIO_ODR_ODR8_Pos (8U)
+#define GPIO_ODR_ODR8_Msk (0x1U << GPIO_ODR_ODR8_Pos) /*!< 0x00000100 */
+#define GPIO_ODR_ODR8 GPIO_ODR_ODR8_Msk /*!< Port output data, bit 8 */
+#define GPIO_ODR_ODR9_Pos (9U)
+#define GPIO_ODR_ODR9_Msk (0x1U << GPIO_ODR_ODR9_Pos) /*!< 0x00000200 */
+#define GPIO_ODR_ODR9 GPIO_ODR_ODR9_Msk /*!< Port output data, bit 9 */
+#define GPIO_ODR_ODR10_Pos (10U)
+#define GPIO_ODR_ODR10_Msk (0x1U << GPIO_ODR_ODR10_Pos) /*!< 0x00000400 */
+#define GPIO_ODR_ODR10 GPIO_ODR_ODR10_Msk /*!< Port output data, bit 10 */
+#define GPIO_ODR_ODR11_Pos (11U)
+#define GPIO_ODR_ODR11_Msk (0x1U << GPIO_ODR_ODR11_Pos) /*!< 0x00000800 */
+#define GPIO_ODR_ODR11 GPIO_ODR_ODR11_Msk /*!< Port output data, bit 11 */
+#define GPIO_ODR_ODR12_Pos (12U)
+#define GPIO_ODR_ODR12_Msk (0x1U << GPIO_ODR_ODR12_Pos) /*!< 0x00001000 */
+#define GPIO_ODR_ODR12 GPIO_ODR_ODR12_Msk /*!< Port output data, bit 12 */
+#define GPIO_ODR_ODR13_Pos (13U)
+#define GPIO_ODR_ODR13_Msk (0x1U << GPIO_ODR_ODR13_Pos) /*!< 0x00002000 */
+#define GPIO_ODR_ODR13 GPIO_ODR_ODR13_Msk /*!< Port output data, bit 13 */
+#define GPIO_ODR_ODR14_Pos (14U)
+#define GPIO_ODR_ODR14_Msk (0x1U << GPIO_ODR_ODR14_Pos) /*!< 0x00004000 */
+#define GPIO_ODR_ODR14 GPIO_ODR_ODR14_Msk /*!< Port output data, bit 14 */
+#define GPIO_ODR_ODR15_Pos (15U)
+#define GPIO_ODR_ODR15_Msk (0x1U << GPIO_ODR_ODR15_Pos) /*!< 0x00008000 */
+#define GPIO_ODR_ODR15 GPIO_ODR_ODR15_Msk /*!< Port output data, bit 15 */
+
+/****************** Bit definition for GPIO_BSRR register *******************/
+#define GPIO_BSRR_BS0_Pos (0U)
+#define GPIO_BSRR_BS0_Msk (0x1U << GPIO_BSRR_BS0_Pos) /*!< 0x00000001 */
+#define GPIO_BSRR_BS0 GPIO_BSRR_BS0_Msk /*!< Port x Set bit 0 */
+#define GPIO_BSRR_BS1_Pos (1U)
+#define GPIO_BSRR_BS1_Msk (0x1U << GPIO_BSRR_BS1_Pos) /*!< 0x00000002 */
+#define GPIO_BSRR_BS1 GPIO_BSRR_BS1_Msk /*!< Port x Set bit 1 */
+#define GPIO_BSRR_BS2_Pos (2U)
+#define GPIO_BSRR_BS2_Msk (0x1U << GPIO_BSRR_BS2_Pos) /*!< 0x00000004 */
+#define GPIO_BSRR_BS2 GPIO_BSRR_BS2_Msk /*!< Port x Set bit 2 */
+#define GPIO_BSRR_BS3_Pos (3U)
+#define GPIO_BSRR_BS3_Msk (0x1U << GPIO_BSRR_BS3_Pos) /*!< 0x00000008 */
+#define GPIO_BSRR_BS3 GPIO_BSRR_BS3_Msk /*!< Port x Set bit 3 */
+#define GPIO_BSRR_BS4_Pos (4U)
+#define GPIO_BSRR_BS4_Msk (0x1U << GPIO_BSRR_BS4_Pos) /*!< 0x00000010 */
+#define GPIO_BSRR_BS4 GPIO_BSRR_BS4_Msk /*!< Port x Set bit 4 */
+#define GPIO_BSRR_BS5_Pos (5U)
+#define GPIO_BSRR_BS5_Msk (0x1U << GPIO_BSRR_BS5_Pos) /*!< 0x00000020 */
+#define GPIO_BSRR_BS5 GPIO_BSRR_BS5_Msk /*!< Port x Set bit 5 */
+#define GPIO_BSRR_BS6_Pos (6U)
+#define GPIO_BSRR_BS6_Msk (0x1U << GPIO_BSRR_BS6_Pos) /*!< 0x00000040 */
+#define GPIO_BSRR_BS6 GPIO_BSRR_BS6_Msk /*!< Port x Set bit 6 */
+#define GPIO_BSRR_BS7_Pos (7U)
+#define GPIO_BSRR_BS7_Msk (0x1U << GPIO_BSRR_BS7_Pos) /*!< 0x00000080 */
+#define GPIO_BSRR_BS7 GPIO_BSRR_BS7_Msk /*!< Port x Set bit 7 */
+#define GPIO_BSRR_BS8_Pos (8U)
+#define GPIO_BSRR_BS8_Msk (0x1U << GPIO_BSRR_BS8_Pos) /*!< 0x00000100 */
+#define GPIO_BSRR_BS8 GPIO_BSRR_BS8_Msk /*!< Port x Set bit 8 */
+#define GPIO_BSRR_BS9_Pos (9U)
+#define GPIO_BSRR_BS9_Msk (0x1U << GPIO_BSRR_BS9_Pos) /*!< 0x00000200 */
+#define GPIO_BSRR_BS9 GPIO_BSRR_BS9_Msk /*!< Port x Set bit 9 */
+#define GPIO_BSRR_BS10_Pos (10U)
+#define GPIO_BSRR_BS10_Msk (0x1U << GPIO_BSRR_BS10_Pos) /*!< 0x00000400 */
+#define GPIO_BSRR_BS10 GPIO_BSRR_BS10_Msk /*!< Port x Set bit 10 */
+#define GPIO_BSRR_BS11_Pos (11U)
+#define GPIO_BSRR_BS11_Msk (0x1U << GPIO_BSRR_BS11_Pos) /*!< 0x00000800 */
+#define GPIO_BSRR_BS11 GPIO_BSRR_BS11_Msk /*!< Port x Set bit 11 */
+#define GPIO_BSRR_BS12_Pos (12U)
+#define GPIO_BSRR_BS12_Msk (0x1U << GPIO_BSRR_BS12_Pos) /*!< 0x00001000 */
+#define GPIO_BSRR_BS12 GPIO_BSRR_BS12_Msk /*!< Port x Set bit 12 */
+#define GPIO_BSRR_BS13_Pos (13U)
+#define GPIO_BSRR_BS13_Msk (0x1U << GPIO_BSRR_BS13_Pos) /*!< 0x00002000 */
+#define GPIO_BSRR_BS13 GPIO_BSRR_BS13_Msk /*!< Port x Set bit 13 */
+#define GPIO_BSRR_BS14_Pos (14U)
+#define GPIO_BSRR_BS14_Msk (0x1U << GPIO_BSRR_BS14_Pos) /*!< 0x00004000 */
+#define GPIO_BSRR_BS14 GPIO_BSRR_BS14_Msk /*!< Port x Set bit 14 */
+#define GPIO_BSRR_BS15_Pos (15U)
+#define GPIO_BSRR_BS15_Msk (0x1U << GPIO_BSRR_BS15_Pos) /*!< 0x00008000 */
+#define GPIO_BSRR_BS15 GPIO_BSRR_BS15_Msk /*!< Port x Set bit 15 */
+
+#define GPIO_BSRR_BR0_Pos (16U)
+#define GPIO_BSRR_BR0_Msk (0x1U << GPIO_BSRR_BR0_Pos) /*!< 0x00010000 */
+#define GPIO_BSRR_BR0 GPIO_BSRR_BR0_Msk /*!< Port x Reset bit 0 */
+#define GPIO_BSRR_BR1_Pos (17U)
+#define GPIO_BSRR_BR1_Msk (0x1U << GPIO_BSRR_BR1_Pos) /*!< 0x00020000 */
+#define GPIO_BSRR_BR1 GPIO_BSRR_BR1_Msk /*!< Port x Reset bit 1 */
+#define GPIO_BSRR_BR2_Pos (18U)
+#define GPIO_BSRR_BR2_Msk (0x1U << GPIO_BSRR_BR2_Pos) /*!< 0x00040000 */
+#define GPIO_BSRR_BR2 GPIO_BSRR_BR2_Msk /*!< Port x Reset bit 2 */
+#define GPIO_BSRR_BR3_Pos (19U)
+#define GPIO_BSRR_BR3_Msk (0x1U << GPIO_BSRR_BR3_Pos) /*!< 0x00080000 */
+#define GPIO_BSRR_BR3 GPIO_BSRR_BR3_Msk /*!< Port x Reset bit 3 */
+#define GPIO_BSRR_BR4_Pos (20U)
+#define GPIO_BSRR_BR4_Msk (0x1U << GPIO_BSRR_BR4_Pos) /*!< 0x00100000 */
+#define GPIO_BSRR_BR4 GPIO_BSRR_BR4_Msk /*!< Port x Reset bit 4 */
+#define GPIO_BSRR_BR5_Pos (21U)
+#define GPIO_BSRR_BR5_Msk (0x1U << GPIO_BSRR_BR5_Pos) /*!< 0x00200000 */
+#define GPIO_BSRR_BR5 GPIO_BSRR_BR5_Msk /*!< Port x Reset bit 5 */
+#define GPIO_BSRR_BR6_Pos (22U)
+#define GPIO_BSRR_BR6_Msk (0x1U << GPIO_BSRR_BR6_Pos) /*!< 0x00400000 */
+#define GPIO_BSRR_BR6 GPIO_BSRR_BR6_Msk /*!< Port x Reset bit 6 */
+#define GPIO_BSRR_BR7_Pos (23U)
+#define GPIO_BSRR_BR7_Msk (0x1U << GPIO_BSRR_BR7_Pos) /*!< 0x00800000 */
+#define GPIO_BSRR_BR7 GPIO_BSRR_BR7_Msk /*!< Port x Reset bit 7 */
+#define GPIO_BSRR_BR8_Pos (24U)
+#define GPIO_BSRR_BR8_Msk (0x1U << GPIO_BSRR_BR8_Pos) /*!< 0x01000000 */
+#define GPIO_BSRR_BR8 GPIO_BSRR_BR8_Msk /*!< Port x Reset bit 8 */
+#define GPIO_BSRR_BR9_Pos (25U)
+#define GPIO_BSRR_BR9_Msk (0x1U << GPIO_BSRR_BR9_Pos) /*!< 0x02000000 */
+#define GPIO_BSRR_BR9 GPIO_BSRR_BR9_Msk /*!< Port x Reset bit 9 */
+#define GPIO_BSRR_BR10_Pos (26U)
+#define GPIO_BSRR_BR10_Msk (0x1U << GPIO_BSRR_BR10_Pos) /*!< 0x04000000 */
+#define GPIO_BSRR_BR10 GPIO_BSRR_BR10_Msk /*!< Port x Reset bit 10 */
+#define GPIO_BSRR_BR11_Pos (27U)
+#define GPIO_BSRR_BR11_Msk (0x1U << GPIO_BSRR_BR11_Pos) /*!< 0x08000000 */
+#define GPIO_BSRR_BR11 GPIO_BSRR_BR11_Msk /*!< Port x Reset bit 11 */
+#define GPIO_BSRR_BR12_Pos (28U)
+#define GPIO_BSRR_BR12_Msk (0x1U << GPIO_BSRR_BR12_Pos) /*!< 0x10000000 */
+#define GPIO_BSRR_BR12 GPIO_BSRR_BR12_Msk /*!< Port x Reset bit 12 */
+#define GPIO_BSRR_BR13_Pos (29U)
+#define GPIO_BSRR_BR13_Msk (0x1U << GPIO_BSRR_BR13_Pos) /*!< 0x20000000 */
+#define GPIO_BSRR_BR13 GPIO_BSRR_BR13_Msk /*!< Port x Reset bit 13 */
+#define GPIO_BSRR_BR14_Pos (30U)
+#define GPIO_BSRR_BR14_Msk (0x1U << GPIO_BSRR_BR14_Pos) /*!< 0x40000000 */
+#define GPIO_BSRR_BR14 GPIO_BSRR_BR14_Msk /*!< Port x Reset bit 14 */
+#define GPIO_BSRR_BR15_Pos (31U)
+#define GPIO_BSRR_BR15_Msk (0x1U << GPIO_BSRR_BR15_Pos) /*!< 0x80000000 */
+#define GPIO_BSRR_BR15 GPIO_BSRR_BR15_Msk /*!< Port x Reset bit 15 */
+
+/******************* Bit definition for GPIO_BRR register *******************/
+#define GPIO_BRR_BR0_Pos (0U)
+#define GPIO_BRR_BR0_Msk (0x1U << GPIO_BRR_BR0_Pos) /*!< 0x00000001 */
+#define GPIO_BRR_BR0 GPIO_BRR_BR0_Msk /*!< Port x Reset bit 0 */
+#define GPIO_BRR_BR1_Pos (1U)
+#define GPIO_BRR_BR1_Msk (0x1U << GPIO_BRR_BR1_Pos) /*!< 0x00000002 */
+#define GPIO_BRR_BR1 GPIO_BRR_BR1_Msk /*!< Port x Reset bit 1 */
+#define GPIO_BRR_BR2_Pos (2U)
+#define GPIO_BRR_BR2_Msk (0x1U << GPIO_BRR_BR2_Pos) /*!< 0x00000004 */
+#define GPIO_BRR_BR2 GPIO_BRR_BR2_Msk /*!< Port x Reset bit 2 */
+#define GPIO_BRR_BR3_Pos (3U)
+#define GPIO_BRR_BR3_Msk (0x1U << GPIO_BRR_BR3_Pos) /*!< 0x00000008 */
+#define GPIO_BRR_BR3 GPIO_BRR_BR3_Msk /*!< Port x Reset bit 3 */
+#define GPIO_BRR_BR4_Pos (4U)
+#define GPIO_BRR_BR4_Msk (0x1U << GPIO_BRR_BR4_Pos) /*!< 0x00000010 */
+#define GPIO_BRR_BR4 GPIO_BRR_BR4_Msk /*!< Port x Reset bit 4 */
+#define GPIO_BRR_BR5_Pos (5U)
+#define GPIO_BRR_BR5_Msk (0x1U << GPIO_BRR_BR5_Pos) /*!< 0x00000020 */
+#define GPIO_BRR_BR5 GPIO_BRR_BR5_Msk /*!< Port x Reset bit 5 */
+#define GPIO_BRR_BR6_Pos (6U)
+#define GPIO_BRR_BR6_Msk (0x1U << GPIO_BRR_BR6_Pos) /*!< 0x00000040 */
+#define GPIO_BRR_BR6 GPIO_BRR_BR6_Msk /*!< Port x Reset bit 6 */
+#define GPIO_BRR_BR7_Pos (7U)
+#define GPIO_BRR_BR7_Msk (0x1U << GPIO_BRR_BR7_Pos) /*!< 0x00000080 */
+#define GPIO_BRR_BR7 GPIO_BRR_BR7_Msk /*!< Port x Reset bit 7 */
+#define GPIO_BRR_BR8_Pos (8U)
+#define GPIO_BRR_BR8_Msk (0x1U << GPIO_BRR_BR8_Pos) /*!< 0x00000100 */
+#define GPIO_BRR_BR8 GPIO_BRR_BR8_Msk /*!< Port x Reset bit 8 */
+#define GPIO_BRR_BR9_Pos (9U)
+#define GPIO_BRR_BR9_Msk (0x1U << GPIO_BRR_BR9_Pos) /*!< 0x00000200 */
+#define GPIO_BRR_BR9 GPIO_BRR_BR9_Msk /*!< Port x Reset bit 9 */
+#define GPIO_BRR_BR10_Pos (10U)
+#define GPIO_BRR_BR10_Msk (0x1U << GPIO_BRR_BR10_Pos) /*!< 0x00000400 */
+#define GPIO_BRR_BR10 GPIO_BRR_BR10_Msk /*!< Port x Reset bit 10 */
+#define GPIO_BRR_BR11_Pos (11U)
+#define GPIO_BRR_BR11_Msk (0x1U << GPIO_BRR_BR11_Pos) /*!< 0x00000800 */
+#define GPIO_BRR_BR11 GPIO_BRR_BR11_Msk /*!< Port x Reset bit 11 */
+#define GPIO_BRR_BR12_Pos (12U)
+#define GPIO_BRR_BR12_Msk (0x1U << GPIO_BRR_BR12_Pos) /*!< 0x00001000 */
+#define GPIO_BRR_BR12 GPIO_BRR_BR12_Msk /*!< Port x Reset bit 12 */
+#define GPIO_BRR_BR13_Pos (13U)
+#define GPIO_BRR_BR13_Msk (0x1U << GPIO_BRR_BR13_Pos) /*!< 0x00002000 */
+#define GPIO_BRR_BR13 GPIO_BRR_BR13_Msk /*!< Port x Reset bit 13 */
+#define GPIO_BRR_BR14_Pos (14U)
+#define GPIO_BRR_BR14_Msk (0x1U << GPIO_BRR_BR14_Pos) /*!< 0x00004000 */
+#define GPIO_BRR_BR14 GPIO_BRR_BR14_Msk /*!< Port x Reset bit 14 */
+#define GPIO_BRR_BR15_Pos (15U)
+#define GPIO_BRR_BR15_Msk (0x1U << GPIO_BRR_BR15_Pos) /*!< 0x00008000 */
+#define GPIO_BRR_BR15 GPIO_BRR_BR15_Msk /*!< Port x Reset bit 15 */
+
+/****************** Bit definition for GPIO_LCKR register *******************/
+#define GPIO_LCKR_LCK0_Pos (0U)
+#define GPIO_LCKR_LCK0_Msk (0x1U << GPIO_LCKR_LCK0_Pos) /*!< 0x00000001 */
+#define GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk /*!< Port x Lock bit 0 */
+#define GPIO_LCKR_LCK1_Pos (1U)
+#define GPIO_LCKR_LCK1_Msk (0x1U << GPIO_LCKR_LCK1_Pos) /*!< 0x00000002 */
+#define GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk /*!< Port x Lock bit 1 */
+#define GPIO_LCKR_LCK2_Pos (2U)
+#define GPIO_LCKR_LCK2_Msk (0x1U << GPIO_LCKR_LCK2_Pos) /*!< 0x00000004 */
+#define GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk /*!< Port x Lock bit 2 */
+#define GPIO_LCKR_LCK3_Pos (3U)
+#define GPIO_LCKR_LCK3_Msk (0x1U << GPIO_LCKR_LCK3_Pos) /*!< 0x00000008 */
+#define GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk /*!< Port x Lock bit 3 */
+#define GPIO_LCKR_LCK4_Pos (4U)
+#define GPIO_LCKR_LCK4_Msk (0x1U << GPIO_LCKR_LCK4_Pos) /*!< 0x00000010 */
+#define GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk /*!< Port x Lock bit 4 */
+#define GPIO_LCKR_LCK5_Pos (5U)
+#define GPIO_LCKR_LCK5_Msk (0x1U << GPIO_LCKR_LCK5_Pos) /*!< 0x00000020 */
+#define GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk /*!< Port x Lock bit 5 */
+#define GPIO_LCKR_LCK6_Pos (6U)
+#define GPIO_LCKR_LCK6_Msk (0x1U << GPIO_LCKR_LCK6_Pos) /*!< 0x00000040 */
+#define GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk /*!< Port x Lock bit 6 */
+#define GPIO_LCKR_LCK7_Pos (7U)
+#define GPIO_LCKR_LCK7_Msk (0x1U << GPIO_LCKR_LCK7_Pos) /*!< 0x00000080 */
+#define GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk /*!< Port x Lock bit 7 */
+#define GPIO_LCKR_LCK8_Pos (8U)
+#define GPIO_LCKR_LCK8_Msk (0x1U << GPIO_LCKR_LCK8_Pos) /*!< 0x00000100 */
+#define GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk /*!< Port x Lock bit 8 */
+#define GPIO_LCKR_LCK9_Pos (9U)
+#define GPIO_LCKR_LCK9_Msk (0x1U << GPIO_LCKR_LCK9_Pos) /*!< 0x00000200 */
+#define GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk /*!< Port x Lock bit 9 */
+#define GPIO_LCKR_LCK10_Pos (10U)
+#define GPIO_LCKR_LCK10_Msk (0x1U << GPIO_LCKR_LCK10_Pos) /*!< 0x00000400 */
+#define GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk /*!< Port x Lock bit 10 */
+#define GPIO_LCKR_LCK11_Pos (11U)
+#define GPIO_LCKR_LCK11_Msk (0x1U << GPIO_LCKR_LCK11_Pos) /*!< 0x00000800 */
+#define GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk /*!< Port x Lock bit 11 */
+#define GPIO_LCKR_LCK12_Pos (12U)
+#define GPIO_LCKR_LCK12_Msk (0x1U << GPIO_LCKR_LCK12_Pos) /*!< 0x00001000 */
+#define GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk /*!< Port x Lock bit 12 */
+#define GPIO_LCKR_LCK13_Pos (13U)
+#define GPIO_LCKR_LCK13_Msk (0x1U << GPIO_LCKR_LCK13_Pos) /*!< 0x00002000 */
+#define GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk /*!< Port x Lock bit 13 */
+#define GPIO_LCKR_LCK14_Pos (14U)
+#define GPIO_LCKR_LCK14_Msk (0x1U << GPIO_LCKR_LCK14_Pos) /*!< 0x00004000 */
+#define GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk /*!< Port x Lock bit 14 */
+#define GPIO_LCKR_LCK15_Pos (15U)
+#define GPIO_LCKR_LCK15_Msk (0x1U << GPIO_LCKR_LCK15_Pos) /*!< 0x00008000 */
+#define GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk /*!< Port x Lock bit 15 */
+#define GPIO_LCKR_LCKK_Pos (16U)
+#define GPIO_LCKR_LCKK_Msk (0x1U << GPIO_LCKR_LCKK_Pos) /*!< 0x00010000 */
+#define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk /*!< Lock key */
+
+/*----------------------------------------------------------------------------*/
+
+/****************** Bit definition for AFIO_EVCR register *******************/
+#define AFIO_EVCR_PIN_Pos (0U)
+#define AFIO_EVCR_PIN_Msk (0xFU << AFIO_EVCR_PIN_Pos) /*!< 0x0000000F */
+#define AFIO_EVCR_PIN AFIO_EVCR_PIN_Msk /*!< PIN[3:0] bits (Pin selection) */
+#define AFIO_EVCR_PIN_0 (0x1U << AFIO_EVCR_PIN_Pos) /*!< 0x00000001 */
+#define AFIO_EVCR_PIN_1 (0x2U << AFIO_EVCR_PIN_Pos) /*!< 0x00000002 */
+#define AFIO_EVCR_PIN_2 (0x4U << AFIO_EVCR_PIN_Pos) /*!< 0x00000004 */
+#define AFIO_EVCR_PIN_3 (0x8U << AFIO_EVCR_PIN_Pos) /*!< 0x00000008 */
+
+/*!< PIN configuration */
+#define AFIO_EVCR_PIN_PX0 ((uint32_t)0x00000000) /*!< Pin 0 selected */
+#define AFIO_EVCR_PIN_PX1_Pos (0U)
+#define AFIO_EVCR_PIN_PX1_Msk (0x1U << AFIO_EVCR_PIN_PX1_Pos) /*!< 0x00000001 */
+#define AFIO_EVCR_PIN_PX1 AFIO_EVCR_PIN_PX1_Msk /*!< Pin 1 selected */
+#define AFIO_EVCR_PIN_PX2_Pos (1U)
+#define AFIO_EVCR_PIN_PX2_Msk (0x1U << AFIO_EVCR_PIN_PX2_Pos) /*!< 0x00000002 */
+#define AFIO_EVCR_PIN_PX2 AFIO_EVCR_PIN_PX2_Msk /*!< Pin 2 selected */
+#define AFIO_EVCR_PIN_PX3_Pos (0U)
+#define AFIO_EVCR_PIN_PX3_Msk (0x3U << AFIO_EVCR_PIN_PX3_Pos) /*!< 0x00000003 */
+#define AFIO_EVCR_PIN_PX3 AFIO_EVCR_PIN_PX3_Msk /*!< Pin 3 selected */
+#define AFIO_EVCR_PIN_PX4_Pos (2U)
+#define AFIO_EVCR_PIN_PX4_Msk (0x1U << AFIO_EVCR_PIN_PX4_Pos) /*!< 0x00000004 */
+#define AFIO_EVCR_PIN_PX4 AFIO_EVCR_PIN_PX4_Msk /*!< Pin 4 selected */
+#define AFIO_EVCR_PIN_PX5_Pos (0U)
+#define AFIO_EVCR_PIN_PX5_Msk (0x5U << AFIO_EVCR_PIN_PX5_Pos) /*!< 0x00000005 */
+#define AFIO_EVCR_PIN_PX5 AFIO_EVCR_PIN_PX5_Msk /*!< Pin 5 selected */
+#define AFIO_EVCR_PIN_PX6_Pos (1U)
+#define AFIO_EVCR_PIN_PX6_Msk (0x3U << AFIO_EVCR_PIN_PX6_Pos) /*!< 0x00000006 */
+#define AFIO_EVCR_PIN_PX6 AFIO_EVCR_PIN_PX6_Msk /*!< Pin 6 selected */
+#define AFIO_EVCR_PIN_PX7_Pos (0U)
+#define AFIO_EVCR_PIN_PX7_Msk (0x7U << AFIO_EVCR_PIN_PX7_Pos) /*!< 0x00000007 */
+#define AFIO_EVCR_PIN_PX7 AFIO_EVCR_PIN_PX7_Msk /*!< Pin 7 selected */
+#define AFIO_EVCR_PIN_PX8_Pos (3U)
+#define AFIO_EVCR_PIN_PX8_Msk (0x1U << AFIO_EVCR_PIN_PX8_Pos) /*!< 0x00000008 */
+#define AFIO_EVCR_PIN_PX8 AFIO_EVCR_PIN_PX8_Msk /*!< Pin 8 selected */
+#define AFIO_EVCR_PIN_PX9_Pos (0U)
+#define AFIO_EVCR_PIN_PX9_Msk (0x9U << AFIO_EVCR_PIN_PX9_Pos) /*!< 0x00000009 */
+#define AFIO_EVCR_PIN_PX9 AFIO_EVCR_PIN_PX9_Msk /*!< Pin 9 selected */
+#define AFIO_EVCR_PIN_PX10_Pos (1U)
+#define AFIO_EVCR_PIN_PX10_Msk (0x5U << AFIO_EVCR_PIN_PX10_Pos) /*!< 0x0000000A */
+#define AFIO_EVCR_PIN_PX10 AFIO_EVCR_PIN_PX10_Msk /*!< Pin 10 selected */
+#define AFIO_EVCR_PIN_PX11_Pos (0U)
+#define AFIO_EVCR_PIN_PX11_Msk (0xBU << AFIO_EVCR_PIN_PX11_Pos) /*!< 0x0000000B */
+#define AFIO_EVCR_PIN_PX11 AFIO_EVCR_PIN_PX11_Msk /*!< Pin 11 selected */
+#define AFIO_EVCR_PIN_PX12_Pos (2U)
+#define AFIO_EVCR_PIN_PX12_Msk (0x3U << AFIO_EVCR_PIN_PX12_Pos) /*!< 0x0000000C */
+#define AFIO_EVCR_PIN_PX12 AFIO_EVCR_PIN_PX12_Msk /*!< Pin 12 selected */
+#define AFIO_EVCR_PIN_PX13_Pos (0U)
+#define AFIO_EVCR_PIN_PX13_Msk (0xDU << AFIO_EVCR_PIN_PX13_Pos) /*!< 0x0000000D */
+#define AFIO_EVCR_PIN_PX13 AFIO_EVCR_PIN_PX13_Msk /*!< Pin 13 selected */
+#define AFIO_EVCR_PIN_PX14_Pos (1U)
+#define AFIO_EVCR_PIN_PX14_Msk (0x7U << AFIO_EVCR_PIN_PX14_Pos) /*!< 0x0000000E */
+#define AFIO_EVCR_PIN_PX14 AFIO_EVCR_PIN_PX14_Msk /*!< Pin 14 selected */
+#define AFIO_EVCR_PIN_PX15_Pos (0U)
+#define AFIO_EVCR_PIN_PX15_Msk (0xFU << AFIO_EVCR_PIN_PX15_Pos) /*!< 0x0000000F */
+#define AFIO_EVCR_PIN_PX15 AFIO_EVCR_PIN_PX15_Msk /*!< Pin 15 selected */
+
+#define AFIO_EVCR_PORT_Pos (4U)
+#define AFIO_EVCR_PORT_Msk (0x7U << AFIO_EVCR_PORT_Pos) /*!< 0x00000070 */
+#define AFIO_EVCR_PORT AFIO_EVCR_PORT_Msk /*!< PORT[2:0] bits (Port selection) */
+#define AFIO_EVCR_PORT_0 (0x1U << AFIO_EVCR_PORT_Pos) /*!< 0x00000010 */
+#define AFIO_EVCR_PORT_1 (0x2U << AFIO_EVCR_PORT_Pos) /*!< 0x00000020 */
+#define AFIO_EVCR_PORT_2 (0x4U << AFIO_EVCR_PORT_Pos) /*!< 0x00000040 */
+
+/*!< PORT configuration */
+#define AFIO_EVCR_PORT_PA ((uint32_t)0x00000000) /*!< Port A selected */
+#define AFIO_EVCR_PORT_PB_Pos (4U)
+#define AFIO_EVCR_PORT_PB_Msk (0x1U << AFIO_EVCR_PORT_PB_Pos) /*!< 0x00000010 */
+#define AFIO_EVCR_PORT_PB AFIO_EVCR_PORT_PB_Msk /*!< Port B selected */
+#define AFIO_EVCR_PORT_PC_Pos (5U)
+#define AFIO_EVCR_PORT_PC_Msk (0x1U << AFIO_EVCR_PORT_PC_Pos) /*!< 0x00000020 */
+#define AFIO_EVCR_PORT_PC AFIO_EVCR_PORT_PC_Msk /*!< Port C selected */
+#define AFIO_EVCR_PORT_PD_Pos (4U)
+#define AFIO_EVCR_PORT_PD_Msk (0x3U << AFIO_EVCR_PORT_PD_Pos) /*!< 0x00000030 */
+#define AFIO_EVCR_PORT_PD AFIO_EVCR_PORT_PD_Msk /*!< Port D selected */
+#define AFIO_EVCR_PORT_PE_Pos (6U)
+#define AFIO_EVCR_PORT_PE_Msk (0x1U << AFIO_EVCR_PORT_PE_Pos) /*!< 0x00000040 */
+#define AFIO_EVCR_PORT_PE AFIO_EVCR_PORT_PE_Msk /*!< Port E selected */
+
+#define AFIO_EVCR_EVOE_Pos (7U)
+#define AFIO_EVCR_EVOE_Msk (0x1U << AFIO_EVCR_EVOE_Pos) /*!< 0x00000080 */
+#define AFIO_EVCR_EVOE AFIO_EVCR_EVOE_Msk /*!< Event Output Enable */
+
+/****************** Bit definition for AFIO_MAPR register *******************/
+#define AFIO_MAPR_SPI1_REMAP_Pos (0U)
+#define AFIO_MAPR_SPI1_REMAP_Msk (0x1U << AFIO_MAPR_SPI1_REMAP_Pos) /*!< 0x00000001 */
+#define AFIO_MAPR_SPI1_REMAP AFIO_MAPR_SPI1_REMAP_Msk /*!< SPI1 remapping */
+#define AFIO_MAPR_I2C1_REMAP_Pos (1U)
+#define AFIO_MAPR_I2C1_REMAP_Msk (0x1U << AFIO_MAPR_I2C1_REMAP_Pos) /*!< 0x00000002 */
+#define AFIO_MAPR_I2C1_REMAP AFIO_MAPR_I2C1_REMAP_Msk /*!< I2C1 remapping */
+#define AFIO_MAPR_USART1_REMAP_Pos (2U)
+#define AFIO_MAPR_USART1_REMAP_Msk (0x1U << AFIO_MAPR_USART1_REMAP_Pos) /*!< 0x00000004 */
+#define AFIO_MAPR_USART1_REMAP AFIO_MAPR_USART1_REMAP_Msk /*!< USART1 remapping */
+#define AFIO_MAPR_USART2_REMAP_Pos (3U)
+#define AFIO_MAPR_USART2_REMAP_Msk (0x1U << AFIO_MAPR_USART2_REMAP_Pos) /*!< 0x00000008 */
+#define AFIO_MAPR_USART2_REMAP AFIO_MAPR_USART2_REMAP_Msk /*!< USART2 remapping */
+
+#define AFIO_MAPR_USART3_REMAP_Pos (4U)
+#define AFIO_MAPR_USART3_REMAP_Msk (0x3U << AFIO_MAPR_USART3_REMAP_Pos) /*!< 0x00000030 */
+#define AFIO_MAPR_USART3_REMAP AFIO_MAPR_USART3_REMAP_Msk /*!< USART3_REMAP[1:0] bits (USART3 remapping) */
+#define AFIO_MAPR_USART3_REMAP_0 (0x1U << AFIO_MAPR_USART3_REMAP_Pos) /*!< 0x00000010 */
+#define AFIO_MAPR_USART3_REMAP_1 (0x2U << AFIO_MAPR_USART3_REMAP_Pos) /*!< 0x00000020 */
+
+/* USART3_REMAP configuration */
+#define AFIO_MAPR_USART3_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14) */
+#define AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Pos (4U)
+#define AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Msk (0x1U << AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Pos) /*!< 0x00000010 */
+#define AFIO_MAPR_USART3_REMAP_PARTIALREMAP AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Msk /*!< Partial remap (TX/PC10, RX/PC11, CK/PC12, CTS/PB13, RTS/PB14) */
+#define AFIO_MAPR_USART3_REMAP_FULLREMAP_Pos (4U)
+#define AFIO_MAPR_USART3_REMAP_FULLREMAP_Msk (0x3U << AFIO_MAPR_USART3_REMAP_FULLREMAP_Pos) /*!< 0x00000030 */
+#define AFIO_MAPR_USART3_REMAP_FULLREMAP AFIO_MAPR_USART3_REMAP_FULLREMAP_Msk /*!< Full remap (TX/PD8, RX/PD9, CK/PD10, CTS/PD11, RTS/PD12) */
+
+#define AFIO_MAPR_TIM1_REMAP_Pos (6U)
+#define AFIO_MAPR_TIM1_REMAP_Msk (0x3U << AFIO_MAPR_TIM1_REMAP_Pos) /*!< 0x000000C0 */
+#define AFIO_MAPR_TIM1_REMAP AFIO_MAPR_TIM1_REMAP_Msk /*!< TIM1_REMAP[1:0] bits (TIM1 remapping) */
+#define AFIO_MAPR_TIM1_REMAP_0 (0x1U << AFIO_MAPR_TIM1_REMAP_Pos) /*!< 0x00000040 */
+#define AFIO_MAPR_TIM1_REMAP_1 (0x2U << AFIO_MAPR_TIM1_REMAP_Pos) /*!< 0x00000080 */
+
+/*!< TIM1_REMAP configuration */
+#define AFIO_MAPR_TIM1_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15) */
+#define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Pos (6U)
+#define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Msk (0x1U << AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Pos) /*!< 0x00000040 */
+#define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Msk /*!< Partial remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PA6, CH1N/PA7, CH2N/PB0, CH3N/PB1) */
+#define AFIO_MAPR_TIM1_REMAP_FULLREMAP_Pos (6U)
+#define AFIO_MAPR_TIM1_REMAP_FULLREMAP_Msk (0x3U << AFIO_MAPR_TIM1_REMAP_FULLREMAP_Pos) /*!< 0x000000C0 */
+#define AFIO_MAPR_TIM1_REMAP_FULLREMAP AFIO_MAPR_TIM1_REMAP_FULLREMAP_Msk /*!< Full remap (ETR/PE7, CH1/PE9, CH2/PE11, CH3/PE13, CH4/PE14, BKIN/PE15, CH1N/PE8, CH2N/PE10, CH3N/PE12) */
+
+#define AFIO_MAPR_TIM2_REMAP_Pos (8U)
+#define AFIO_MAPR_TIM2_REMAP_Msk (0x3U << AFIO_MAPR_TIM2_REMAP_Pos) /*!< 0x00000300 */
+#define AFIO_MAPR_TIM2_REMAP AFIO_MAPR_TIM2_REMAP_Msk /*!< TIM2_REMAP[1:0] bits (TIM2 remapping) */
+#define AFIO_MAPR_TIM2_REMAP_0 (0x1U << AFIO_MAPR_TIM2_REMAP_Pos) /*!< 0x00000100 */
+#define AFIO_MAPR_TIM2_REMAP_1 (0x2U << AFIO_MAPR_TIM2_REMAP_Pos) /*!< 0x00000200 */
+
+/*!< TIM2_REMAP configuration */
+#define AFIO_MAPR_TIM2_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3) */
+#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Pos (8U)
+#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Msk (0x1U << AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Pos) /*!< 0x00000100 */
+#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1 AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Msk /*!< Partial remap (CH1/ETR/PA15, CH2/PB3, CH3/PA2, CH4/PA3) */
+#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2_Pos (9U)
+#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2_Msk (0x1U << AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2_Pos) /*!< 0x00000200 */
+#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2 AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2_Msk /*!< Partial remap (CH1/ETR/PA0, CH2/PA1, CH3/PB10, CH4/PB11) */
+#define AFIO_MAPR_TIM2_REMAP_FULLREMAP_Pos (8U)
+#define AFIO_MAPR_TIM2_REMAP_FULLREMAP_Msk (0x3U << AFIO_MAPR_TIM2_REMAP_FULLREMAP_Pos) /*!< 0x00000300 */
+#define AFIO_MAPR_TIM2_REMAP_FULLREMAP AFIO_MAPR_TIM2_REMAP_FULLREMAP_Msk /*!< Full remap (CH1/ETR/PA15, CH2/PB3, CH3/PB10, CH4/PB11) */
+
+#define AFIO_MAPR_TIM3_REMAP_Pos (10U)
+#define AFIO_MAPR_TIM3_REMAP_Msk (0x3U << AFIO_MAPR_TIM3_REMAP_Pos) /*!< 0x00000C00 */
+#define AFIO_MAPR_TIM3_REMAP AFIO_MAPR_TIM3_REMAP_Msk /*!< TIM3_REMAP[1:0] bits (TIM3 remapping) */
+#define AFIO_MAPR_TIM3_REMAP_0 (0x1U << AFIO_MAPR_TIM3_REMAP_Pos) /*!< 0x00000400 */
+#define AFIO_MAPR_TIM3_REMAP_1 (0x2U << AFIO_MAPR_TIM3_REMAP_Pos) /*!< 0x00000800 */
+
+/*!< TIM3_REMAP configuration */
+#define AFIO_MAPR_TIM3_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1) */
+#define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Pos (11U)
+#define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Msk (0x1U << AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Pos) /*!< 0x00000800 */
+#define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Msk /*!< Partial remap (CH1/PB4, CH2/PB5, CH3/PB0, CH4/PB1) */
+#define AFIO_MAPR_TIM3_REMAP_FULLREMAP_Pos (10U)
+#define AFIO_MAPR_TIM3_REMAP_FULLREMAP_Msk (0x3U << AFIO_MAPR_TIM3_REMAP_FULLREMAP_Pos) /*!< 0x00000C00 */
+#define AFIO_MAPR_TIM3_REMAP_FULLREMAP AFIO_MAPR_TIM3_REMAP_FULLREMAP_Msk /*!< Full remap (CH1/PC6, CH2/PC7, CH3/PC8, CH4/PC9) */
+
+#define AFIO_MAPR_TIM4_REMAP_Pos (12U)
+#define AFIO_MAPR_TIM4_REMAP_Msk (0x1U << AFIO_MAPR_TIM4_REMAP_Pos) /*!< 0x00001000 */
+#define AFIO_MAPR_TIM4_REMAP AFIO_MAPR_TIM4_REMAP_Msk /*!< TIM4_REMAP bit (TIM4 remapping) */
+
+
+#define AFIO_MAPR_PD01_REMAP_Pos (15U)
+#define AFIO_MAPR_PD01_REMAP_Msk (0x1U << AFIO_MAPR_PD01_REMAP_Pos) /*!< 0x00008000 */
+#define AFIO_MAPR_PD01_REMAP AFIO_MAPR_PD01_REMAP_Msk /*!< Port D0/Port D1 mapping on OSC_IN/OSC_OUT */
+
+/*!< SWJ_CFG configuration */
+#define AFIO_MAPR_SWJ_CFG_Pos (24U)
+#define AFIO_MAPR_SWJ_CFG_Msk (0x7U << AFIO_MAPR_SWJ_CFG_Pos) /*!< 0x07000000 */
+#define AFIO_MAPR_SWJ_CFG AFIO_MAPR_SWJ_CFG_Msk /*!< SWJ_CFG[2:0] bits (Serial Wire JTAG configuration) */
+#define AFIO_MAPR_SWJ_CFG_0 (0x1U << AFIO_MAPR_SWJ_CFG_Pos) /*!< 0x01000000 */
+#define AFIO_MAPR_SWJ_CFG_1 (0x2U << AFIO_MAPR_SWJ_CFG_Pos) /*!< 0x02000000 */
+#define AFIO_MAPR_SWJ_CFG_2 (0x4U << AFIO_MAPR_SWJ_CFG_Pos) /*!< 0x04000000 */
+
+#define AFIO_MAPR_SWJ_CFG_RESET ((uint32_t)0x00000000) /*!< Full SWJ (JTAG-DP + SW-DP) : Reset State */
+#define AFIO_MAPR_SWJ_CFG_NOJNTRST_Pos (24U)
+#define AFIO_MAPR_SWJ_CFG_NOJNTRST_Msk (0x1U << AFIO_MAPR_SWJ_CFG_NOJNTRST_Pos) /*!< 0x01000000 */
+#define AFIO_MAPR_SWJ_CFG_NOJNTRST AFIO_MAPR_SWJ_CFG_NOJNTRST_Msk /*!< Full SWJ (JTAG-DP + SW-DP) but without JNTRST */
+#define AFIO_MAPR_SWJ_CFG_JTAGDISABLE_Pos (25U)
+#define AFIO_MAPR_SWJ_CFG_JTAGDISABLE_Msk (0x1U << AFIO_MAPR_SWJ_CFG_JTAGDISABLE_Pos) /*!< 0x02000000 */
+#define AFIO_MAPR_SWJ_CFG_JTAGDISABLE AFIO_MAPR_SWJ_CFG_JTAGDISABLE_Msk /*!< JTAG-DP Disabled and SW-DP Enabled */
+#define AFIO_MAPR_SWJ_CFG_DISABLE_Pos (26U)
+#define AFIO_MAPR_SWJ_CFG_DISABLE_Msk (0x1U << AFIO_MAPR_SWJ_CFG_DISABLE_Pos) /*!< 0x04000000 */
+#define AFIO_MAPR_SWJ_CFG_DISABLE AFIO_MAPR_SWJ_CFG_DISABLE_Msk /*!< JTAG-DP Disabled and SW-DP Disabled */
+
+
+/***************** Bit definition for AFIO_EXTICR1 register *****************/
+#define AFIO_EXTICR1_EXTI0_Pos (0U)
+#define AFIO_EXTICR1_EXTI0_Msk (0xFU << AFIO_EXTICR1_EXTI0_Pos) /*!< 0x0000000F */
+#define AFIO_EXTICR1_EXTI0 AFIO_EXTICR1_EXTI0_Msk /*!< EXTI 0 configuration */
+#define AFIO_EXTICR1_EXTI1_Pos (4U)
+#define AFIO_EXTICR1_EXTI1_Msk (0xFU << AFIO_EXTICR1_EXTI1_Pos) /*!< 0x000000F0 */
+#define AFIO_EXTICR1_EXTI1 AFIO_EXTICR1_EXTI1_Msk /*!< EXTI 1 configuration */
+#define AFIO_EXTICR1_EXTI2_Pos (8U)
+#define AFIO_EXTICR1_EXTI2_Msk (0xFU << AFIO_EXTICR1_EXTI2_Pos) /*!< 0x00000F00 */
+#define AFIO_EXTICR1_EXTI2 AFIO_EXTICR1_EXTI2_Msk /*!< EXTI 2 configuration */
+#define AFIO_EXTICR1_EXTI3_Pos (12U)
+#define AFIO_EXTICR1_EXTI3_Msk (0xFU << AFIO_EXTICR1_EXTI3_Pos) /*!< 0x0000F000 */
+#define AFIO_EXTICR1_EXTI3 AFIO_EXTICR1_EXTI3_Msk /*!< EXTI 3 configuration */
+
+/*!< EXTI0 configuration */
+#define AFIO_EXTICR1_EXTI0_PA ((uint32_t)0x00000000) /*!< PA[0] pin */
+#define AFIO_EXTICR1_EXTI0_PB_Pos (0U)
+#define AFIO_EXTICR1_EXTI0_PB_Msk (0x1U << AFIO_EXTICR1_EXTI0_PB_Pos) /*!< 0x00000001 */
+#define AFIO_EXTICR1_EXTI0_PB AFIO_EXTICR1_EXTI0_PB_Msk /*!< PB[0] pin */
+#define AFIO_EXTICR1_EXTI0_PC_Pos (1U)
+#define AFIO_EXTICR1_EXTI0_PC_Msk (0x1U << AFIO_EXTICR1_EXTI0_PC_Pos) /*!< 0x00000002 */
+#define AFIO_EXTICR1_EXTI0_PC AFIO_EXTICR1_EXTI0_PC_Msk /*!< PC[0] pin */
+#define AFIO_EXTICR1_EXTI0_PD_Pos (0U)
+#define AFIO_EXTICR1_EXTI0_PD_Msk (0x3U << AFIO_EXTICR1_EXTI0_PD_Pos) /*!< 0x00000003 */
+#define AFIO_EXTICR1_EXTI0_PD AFIO_EXTICR1_EXTI0_PD_Msk /*!< PD[0] pin */
+#define AFIO_EXTICR1_EXTI0_PE_Pos (2U)
+#define AFIO_EXTICR1_EXTI0_PE_Msk (0x1U << AFIO_EXTICR1_EXTI0_PE_Pos) /*!< 0x00000004 */
+#define AFIO_EXTICR1_EXTI0_PE AFIO_EXTICR1_EXTI0_PE_Msk /*!< PE[0] pin */
+#define AFIO_EXTICR1_EXTI0_PF_Pos (0U)
+#define AFIO_EXTICR1_EXTI0_PF_Msk (0x5U << AFIO_EXTICR1_EXTI0_PF_Pos) /*!< 0x00000005 */
+#define AFIO_EXTICR1_EXTI0_PF AFIO_EXTICR1_EXTI0_PF_Msk /*!< PF[0] pin */
+#define AFIO_EXTICR1_EXTI0_PG_Pos (1U)
+#define AFIO_EXTICR1_EXTI0_PG_Msk (0x3U << AFIO_EXTICR1_EXTI0_PG_Pos) /*!< 0x00000006 */
+#define AFIO_EXTICR1_EXTI0_PG AFIO_EXTICR1_EXTI0_PG_Msk /*!< PG[0] pin */
+
+/*!< EXTI1 configuration */
+#define AFIO_EXTICR1_EXTI1_PA ((uint32_t)0x00000000) /*!< PA[1] pin */
+#define AFIO_EXTICR1_EXTI1_PB_Pos (4U)
+#define AFIO_EXTICR1_EXTI1_PB_Msk (0x1U << AFIO_EXTICR1_EXTI1_PB_Pos) /*!< 0x00000010 */
+#define AFIO_EXTICR1_EXTI1_PB AFIO_EXTICR1_EXTI1_PB_Msk /*!< PB[1] pin */
+#define AFIO_EXTICR1_EXTI1_PC_Pos (5U)
+#define AFIO_EXTICR1_EXTI1_PC_Msk (0x1U << AFIO_EXTICR1_EXTI1_PC_Pos) /*!< 0x00000020 */
+#define AFIO_EXTICR1_EXTI1_PC AFIO_EXTICR1_EXTI1_PC_Msk /*!< PC[1] pin */
+#define AFIO_EXTICR1_EXTI1_PD_Pos (4U)
+#define AFIO_EXTICR1_EXTI1_PD_Msk (0x3U << AFIO_EXTICR1_EXTI1_PD_Pos) /*!< 0x00000030 */
+#define AFIO_EXTICR1_EXTI1_PD AFIO_EXTICR1_EXTI1_PD_Msk /*!< PD[1] pin */
+#define AFIO_EXTICR1_EXTI1_PE_Pos (6U)
+#define AFIO_EXTICR1_EXTI1_PE_Msk (0x1U << AFIO_EXTICR1_EXTI1_PE_Pos) /*!< 0x00000040 */
+#define AFIO_EXTICR1_EXTI1_PE AFIO_EXTICR1_EXTI1_PE_Msk /*!< PE[1] pin */
+#define AFIO_EXTICR1_EXTI1_PF_Pos (4U)
+#define AFIO_EXTICR1_EXTI1_PF_Msk (0x5U << AFIO_EXTICR1_EXTI1_PF_Pos) /*!< 0x00000050 */
+#define AFIO_EXTICR1_EXTI1_PF AFIO_EXTICR1_EXTI1_PF_Msk /*!< PF[1] pin */
+#define AFIO_EXTICR1_EXTI1_PG_Pos (5U)
+#define AFIO_EXTICR1_EXTI1_PG_Msk (0x3U << AFIO_EXTICR1_EXTI1_PG_Pos) /*!< 0x00000060 */
+#define AFIO_EXTICR1_EXTI1_PG AFIO_EXTICR1_EXTI1_PG_Msk /*!< PG[1] pin */
+
+/*!< EXTI2 configuration */
+#define AFIO_EXTICR1_EXTI2_PA ((uint32_t)0x00000000) /*!< PA[2] pin */
+#define AFIO_EXTICR1_EXTI2_PB_Pos (8U)
+#define AFIO_EXTICR1_EXTI2_PB_Msk (0x1U << AFIO_EXTICR1_EXTI2_PB_Pos) /*!< 0x00000100 */
+#define AFIO_EXTICR1_EXTI2_PB AFIO_EXTICR1_EXTI2_PB_Msk /*!< PB[2] pin */
+#define AFIO_EXTICR1_EXTI2_PC_Pos (9U)
+#define AFIO_EXTICR1_EXTI2_PC_Msk (0x1U << AFIO_EXTICR1_EXTI2_PC_Pos) /*!< 0x00000200 */
+#define AFIO_EXTICR1_EXTI2_PC AFIO_EXTICR1_EXTI2_PC_Msk /*!< PC[2] pin */
+#define AFIO_EXTICR1_EXTI2_PD_Pos (8U)
+#define AFIO_EXTICR1_EXTI2_PD_Msk (0x3U << AFIO_EXTICR1_EXTI2_PD_Pos) /*!< 0x00000300 */
+#define AFIO_EXTICR1_EXTI2_PD AFIO_EXTICR1_EXTI2_PD_Msk /*!< PD[2] pin */
+#define AFIO_EXTICR1_EXTI2_PE_Pos (10U)
+#define AFIO_EXTICR1_EXTI2_PE_Msk (0x1U << AFIO_EXTICR1_EXTI2_PE_Pos) /*!< 0x00000400 */
+#define AFIO_EXTICR1_EXTI2_PE AFIO_EXTICR1_EXTI2_PE_Msk /*!< PE[2] pin */
+#define AFIO_EXTICR1_EXTI2_PF_Pos (8U)
+#define AFIO_EXTICR1_EXTI2_PF_Msk (0x5U << AFIO_EXTICR1_EXTI2_PF_Pos) /*!< 0x00000500 */
+#define AFIO_EXTICR1_EXTI2_PF AFIO_EXTICR1_EXTI2_PF_Msk /*!< PF[2] pin */
+#define AFIO_EXTICR1_EXTI2_PG_Pos (9U)
+#define AFIO_EXTICR1_EXTI2_PG_Msk (0x3U << AFIO_EXTICR1_EXTI2_PG_Pos) /*!< 0x00000600 */
+#define AFIO_EXTICR1_EXTI2_PG AFIO_EXTICR1_EXTI2_PG_Msk /*!< PG[2] pin */
+
+/*!< EXTI3 configuration */
+#define AFIO_EXTICR1_EXTI3_PA ((uint32_t)0x00000000) /*!< PA[3] pin */
+#define AFIO_EXTICR1_EXTI3_PB_Pos (12U)
+#define AFIO_EXTICR1_EXTI3_PB_Msk (0x1U << AFIO_EXTICR1_EXTI3_PB_Pos) /*!< 0x00001000 */
+#define AFIO_EXTICR1_EXTI3_PB AFIO_EXTICR1_EXTI3_PB_Msk /*!< PB[3] pin */
+#define AFIO_EXTICR1_EXTI3_PC_Pos (13U)
+#define AFIO_EXTICR1_EXTI3_PC_Msk (0x1U << AFIO_EXTICR1_EXTI3_PC_Pos) /*!< 0x00002000 */
+#define AFIO_EXTICR1_EXTI3_PC AFIO_EXTICR1_EXTI3_PC_Msk /*!< PC[3] pin */
+#define AFIO_EXTICR1_EXTI3_PD_Pos (12U)
+#define AFIO_EXTICR1_EXTI3_PD_Msk (0x3U << AFIO_EXTICR1_EXTI3_PD_Pos) /*!< 0x00003000 */
+#define AFIO_EXTICR1_EXTI3_PD AFIO_EXTICR1_EXTI3_PD_Msk /*!< PD[3] pin */
+#define AFIO_EXTICR1_EXTI3_PE_Pos (14U)
+#define AFIO_EXTICR1_EXTI3_PE_Msk (0x1U << AFIO_EXTICR1_EXTI3_PE_Pos) /*!< 0x00004000 */
+#define AFIO_EXTICR1_EXTI3_PE AFIO_EXTICR1_EXTI3_PE_Msk /*!< PE[3] pin */
+#define AFIO_EXTICR1_EXTI3_PF_Pos (12U)
+#define AFIO_EXTICR1_EXTI3_PF_Msk (0x5U << AFIO_EXTICR1_EXTI3_PF_Pos) /*!< 0x00005000 */
+#define AFIO_EXTICR1_EXTI3_PF AFIO_EXTICR1_EXTI3_PF_Msk /*!< PF[3] pin */
+#define AFIO_EXTICR1_EXTI3_PG_Pos (13U)
+#define AFIO_EXTICR1_EXTI3_PG_Msk (0x3U << AFIO_EXTICR1_EXTI3_PG_Pos) /*!< 0x00006000 */
+#define AFIO_EXTICR1_EXTI3_PG AFIO_EXTICR1_EXTI3_PG_Msk /*!< PG[3] pin */
+
+/***************** Bit definition for AFIO_EXTICR2 register *****************/
+#define AFIO_EXTICR2_EXTI4_Pos (0U)
+#define AFIO_EXTICR2_EXTI4_Msk (0xFU << AFIO_EXTICR2_EXTI4_Pos) /*!< 0x0000000F */
+#define AFIO_EXTICR2_EXTI4 AFIO_EXTICR2_EXTI4_Msk /*!< EXTI 4 configuration */
+#define AFIO_EXTICR2_EXTI5_Pos (4U)
+#define AFIO_EXTICR2_EXTI5_Msk (0xFU << AFIO_EXTICR2_EXTI5_Pos) /*!< 0x000000F0 */
+#define AFIO_EXTICR2_EXTI5 AFIO_EXTICR2_EXTI5_Msk /*!< EXTI 5 configuration */
+#define AFIO_EXTICR2_EXTI6_Pos (8U)
+#define AFIO_EXTICR2_EXTI6_Msk (0xFU << AFIO_EXTICR2_EXTI6_Pos) /*!< 0x00000F00 */
+#define AFIO_EXTICR2_EXTI6 AFIO_EXTICR2_EXTI6_Msk /*!< EXTI 6 configuration */
+#define AFIO_EXTICR2_EXTI7_Pos (12U)
+#define AFIO_EXTICR2_EXTI7_Msk (0xFU << AFIO_EXTICR2_EXTI7_Pos) /*!< 0x0000F000 */
+#define AFIO_EXTICR2_EXTI7 AFIO_EXTICR2_EXTI7_Msk /*!< EXTI 7 configuration */
+
+/*!< EXTI4 configuration */
+#define AFIO_EXTICR2_EXTI4_PA ((uint32_t)0x00000000) /*!< PA[4] pin */
+#define AFIO_EXTICR2_EXTI4_PB_Pos (0U)
+#define AFIO_EXTICR2_EXTI4_PB_Msk (0x1U << AFIO_EXTICR2_EXTI4_PB_Pos) /*!< 0x00000001 */
+#define AFIO_EXTICR2_EXTI4_PB AFIO_EXTICR2_EXTI4_PB_Msk /*!< PB[4] pin */
+#define AFIO_EXTICR2_EXTI4_PC_Pos (1U)
+#define AFIO_EXTICR2_EXTI4_PC_Msk (0x1U << AFIO_EXTICR2_EXTI4_PC_Pos) /*!< 0x00000002 */
+#define AFIO_EXTICR2_EXTI4_PC AFIO_EXTICR2_EXTI4_PC_Msk /*!< PC[4] pin */
+#define AFIO_EXTICR2_EXTI4_PD_Pos (0U)
+#define AFIO_EXTICR2_EXTI4_PD_Msk (0x3U << AFIO_EXTICR2_EXTI4_PD_Pos) /*!< 0x00000003 */
+#define AFIO_EXTICR2_EXTI4_PD AFIO_EXTICR2_EXTI4_PD_Msk /*!< PD[4] pin */
+#define AFIO_EXTICR2_EXTI4_PE_Pos (2U)
+#define AFIO_EXTICR2_EXTI4_PE_Msk (0x1U << AFIO_EXTICR2_EXTI4_PE_Pos) /*!< 0x00000004 */
+#define AFIO_EXTICR2_EXTI4_PE AFIO_EXTICR2_EXTI4_PE_Msk /*!< PE[4] pin */
+#define AFIO_EXTICR2_EXTI4_PF_Pos (0U)
+#define AFIO_EXTICR2_EXTI4_PF_Msk (0x5U << AFIO_EXTICR2_EXTI4_PF_Pos) /*!< 0x00000005 */
+#define AFIO_EXTICR2_EXTI4_PF AFIO_EXTICR2_EXTI4_PF_Msk /*!< PF[4] pin */
+#define AFIO_EXTICR2_EXTI4_PG_Pos (1U)
+#define AFIO_EXTICR2_EXTI4_PG_Msk (0x3U << AFIO_EXTICR2_EXTI4_PG_Pos) /*!< 0x00000006 */
+#define AFIO_EXTICR2_EXTI4_PG AFIO_EXTICR2_EXTI4_PG_Msk /*!< PG[4] pin */
+
+/* EXTI5 configuration */
+#define AFIO_EXTICR2_EXTI5_PA ((uint32_t)0x00000000) /*!< PA[5] pin */
+#define AFIO_EXTICR2_EXTI5_PB_Pos (4U)
+#define AFIO_EXTICR2_EXTI5_PB_Msk (0x1U << AFIO_EXTICR2_EXTI5_PB_Pos) /*!< 0x00000010 */
+#define AFIO_EXTICR2_EXTI5_PB AFIO_EXTICR2_EXTI5_PB_Msk /*!< PB[5] pin */
+#define AFIO_EXTICR2_EXTI5_PC_Pos (5U)
+#define AFIO_EXTICR2_EXTI5_PC_Msk (0x1U << AFIO_EXTICR2_EXTI5_PC_Pos) /*!< 0x00000020 */
+#define AFIO_EXTICR2_EXTI5_PC AFIO_EXTICR2_EXTI5_PC_Msk /*!< PC[5] pin */
+#define AFIO_EXTICR2_EXTI5_PD_Pos (4U)
+#define AFIO_EXTICR2_EXTI5_PD_Msk (0x3U << AFIO_EXTICR2_EXTI5_PD_Pos) /*!< 0x00000030 */
+#define AFIO_EXTICR2_EXTI5_PD AFIO_EXTICR2_EXTI5_PD_Msk /*!< PD[5] pin */
+#define AFIO_EXTICR2_EXTI5_PE_Pos (6U)
+#define AFIO_EXTICR2_EXTI5_PE_Msk (0x1U << AFIO_EXTICR2_EXTI5_PE_Pos) /*!< 0x00000040 */
+#define AFIO_EXTICR2_EXTI5_PE AFIO_EXTICR2_EXTI5_PE_Msk /*!< PE[5] pin */
+#define AFIO_EXTICR2_EXTI5_PF_Pos (4U)
+#define AFIO_EXTICR2_EXTI5_PF_Msk (0x5U << AFIO_EXTICR2_EXTI5_PF_Pos) /*!< 0x00000050 */
+#define AFIO_EXTICR2_EXTI5_PF AFIO_EXTICR2_EXTI5_PF_Msk /*!< PF[5] pin */
+#define AFIO_EXTICR2_EXTI5_PG_Pos (5U)
+#define AFIO_EXTICR2_EXTI5_PG_Msk (0x3U << AFIO_EXTICR2_EXTI5_PG_Pos) /*!< 0x00000060 */
+#define AFIO_EXTICR2_EXTI5_PG AFIO_EXTICR2_EXTI5_PG_Msk /*!< PG[5] pin */
+
+/*!< EXTI6 configuration */
+#define AFIO_EXTICR2_EXTI6_PA ((uint32_t)0x00000000) /*!< PA[6] pin */
+#define AFIO_EXTICR2_EXTI6_PB_Pos (8U)
+#define AFIO_EXTICR2_EXTI6_PB_Msk (0x1U << AFIO_EXTICR2_EXTI6_PB_Pos) /*!< 0x00000100 */
+#define AFIO_EXTICR2_EXTI6_PB AFIO_EXTICR2_EXTI6_PB_Msk /*!< PB[6] pin */
+#define AFIO_EXTICR2_EXTI6_PC_Pos (9U)
+#define AFIO_EXTICR2_EXTI6_PC_Msk (0x1U << AFIO_EXTICR2_EXTI6_PC_Pos) /*!< 0x00000200 */
+#define AFIO_EXTICR2_EXTI6_PC AFIO_EXTICR2_EXTI6_PC_Msk /*!< PC[6] pin */
+#define AFIO_EXTICR2_EXTI6_PD_Pos (8U)
+#define AFIO_EXTICR2_EXTI6_PD_Msk (0x3U << AFIO_EXTICR2_EXTI6_PD_Pos) /*!< 0x00000300 */
+#define AFIO_EXTICR2_EXTI6_PD AFIO_EXTICR2_EXTI6_PD_Msk /*!< PD[6] pin */
+#define AFIO_EXTICR2_EXTI6_PE_Pos (10U)
+#define AFIO_EXTICR2_EXTI6_PE_Msk (0x1U << AFIO_EXTICR2_EXTI6_PE_Pos) /*!< 0x00000400 */
+#define AFIO_EXTICR2_EXTI6_PE AFIO_EXTICR2_EXTI6_PE_Msk /*!< PE[6] pin */
+#define AFIO_EXTICR2_EXTI6_PF_Pos (8U)
+#define AFIO_EXTICR2_EXTI6_PF_Msk (0x5U << AFIO_EXTICR2_EXTI6_PF_Pos) /*!< 0x00000500 */
+#define AFIO_EXTICR2_EXTI6_PF AFIO_EXTICR2_EXTI6_PF_Msk /*!< PF[6] pin */
+#define AFIO_EXTICR2_EXTI6_PG_Pos (9U)
+#define AFIO_EXTICR2_EXTI6_PG_Msk (0x3U << AFIO_EXTICR2_EXTI6_PG_Pos) /*!< 0x00000600 */
+#define AFIO_EXTICR2_EXTI6_PG AFIO_EXTICR2_EXTI6_PG_Msk /*!< PG[6] pin */
+
+/*!< EXTI7 configuration */
+#define AFIO_EXTICR2_EXTI7_PA ((uint32_t)0x00000000) /*!< PA[7] pin */
+#define AFIO_EXTICR2_EXTI7_PB_Pos (12U)
+#define AFIO_EXTICR2_EXTI7_PB_Msk (0x1U << AFIO_EXTICR2_EXTI7_PB_Pos) /*!< 0x00001000 */
+#define AFIO_EXTICR2_EXTI7_PB AFIO_EXTICR2_EXTI7_PB_Msk /*!< PB[7] pin */
+#define AFIO_EXTICR2_EXTI7_PC_Pos (13U)
+#define AFIO_EXTICR2_EXTI7_PC_Msk (0x1U << AFIO_EXTICR2_EXTI7_PC_Pos) /*!< 0x00002000 */
+#define AFIO_EXTICR2_EXTI7_PC AFIO_EXTICR2_EXTI7_PC_Msk /*!< PC[7] pin */
+#define AFIO_EXTICR2_EXTI7_PD_Pos (12U)
+#define AFIO_EXTICR2_EXTI7_PD_Msk (0x3U << AFIO_EXTICR2_EXTI7_PD_Pos) /*!< 0x00003000 */
+#define AFIO_EXTICR2_EXTI7_PD AFIO_EXTICR2_EXTI7_PD_Msk /*!< PD[7] pin */
+#define AFIO_EXTICR2_EXTI7_PE_Pos (14U)
+#define AFIO_EXTICR2_EXTI7_PE_Msk (0x1U << AFIO_EXTICR2_EXTI7_PE_Pos) /*!< 0x00004000 */
+#define AFIO_EXTICR2_EXTI7_PE AFIO_EXTICR2_EXTI7_PE_Msk /*!< PE[7] pin */
+#define AFIO_EXTICR2_EXTI7_PF_Pos (12U)
+#define AFIO_EXTICR2_EXTI7_PF_Msk (0x5U << AFIO_EXTICR2_EXTI7_PF_Pos) /*!< 0x00005000 */
+#define AFIO_EXTICR2_EXTI7_PF AFIO_EXTICR2_EXTI7_PF_Msk /*!< PF[7] pin */
+#define AFIO_EXTICR2_EXTI7_PG_Pos (13U)
+#define AFIO_EXTICR2_EXTI7_PG_Msk (0x3U << AFIO_EXTICR2_EXTI7_PG_Pos) /*!< 0x00006000 */
+#define AFIO_EXTICR2_EXTI7_PG AFIO_EXTICR2_EXTI7_PG_Msk /*!< PG[7] pin */
+
+/***************** Bit definition for AFIO_EXTICR3 register *****************/
+#define AFIO_EXTICR3_EXTI8_Pos (0U)
+#define AFIO_EXTICR3_EXTI8_Msk (0xFU << AFIO_EXTICR3_EXTI8_Pos) /*!< 0x0000000F */
+#define AFIO_EXTICR3_EXTI8 AFIO_EXTICR3_EXTI8_Msk /*!< EXTI 8 configuration */
+#define AFIO_EXTICR3_EXTI9_Pos (4U)
+#define AFIO_EXTICR3_EXTI9_Msk (0xFU << AFIO_EXTICR3_EXTI9_Pos) /*!< 0x000000F0 */
+#define AFIO_EXTICR3_EXTI9 AFIO_EXTICR3_EXTI9_Msk /*!< EXTI 9 configuration */
+#define AFIO_EXTICR3_EXTI10_Pos (8U)
+#define AFIO_EXTICR3_EXTI10_Msk (0xFU << AFIO_EXTICR3_EXTI10_Pos) /*!< 0x00000F00 */
+#define AFIO_EXTICR3_EXTI10 AFIO_EXTICR3_EXTI10_Msk /*!< EXTI 10 configuration */
+#define AFIO_EXTICR3_EXTI11_Pos (12U)
+#define AFIO_EXTICR3_EXTI11_Msk (0xFU << AFIO_EXTICR3_EXTI11_Pos) /*!< 0x0000F000 */
+#define AFIO_EXTICR3_EXTI11 AFIO_EXTICR3_EXTI11_Msk /*!< EXTI 11 configuration */
+
+/*!< EXTI8 configuration */
+#define AFIO_EXTICR3_EXTI8_PA ((uint32_t)0x00000000) /*!< PA[8] pin */
+#define AFIO_EXTICR3_EXTI8_PB_Pos (0U)
+#define AFIO_EXTICR3_EXTI8_PB_Msk (0x1U << AFIO_EXTICR3_EXTI8_PB_Pos) /*!< 0x00000001 */
+#define AFIO_EXTICR3_EXTI8_PB AFIO_EXTICR3_EXTI8_PB_Msk /*!< PB[8] pin */
+#define AFIO_EXTICR3_EXTI8_PC_Pos (1U)
+#define AFIO_EXTICR3_EXTI8_PC_Msk (0x1U << AFIO_EXTICR3_EXTI8_PC_Pos) /*!< 0x00000002 */
+#define AFIO_EXTICR3_EXTI8_PC AFIO_EXTICR3_EXTI8_PC_Msk /*!< PC[8] pin */
+#define AFIO_EXTICR3_EXTI8_PD_Pos (0U)
+#define AFIO_EXTICR3_EXTI8_PD_Msk (0x3U << AFIO_EXTICR3_EXTI8_PD_Pos) /*!< 0x00000003 */
+#define AFIO_EXTICR3_EXTI8_PD AFIO_EXTICR3_EXTI8_PD_Msk /*!< PD[8] pin */
+#define AFIO_EXTICR3_EXTI8_PE_Pos (2U)
+#define AFIO_EXTICR3_EXTI8_PE_Msk (0x1U << AFIO_EXTICR3_EXTI8_PE_Pos) /*!< 0x00000004 */
+#define AFIO_EXTICR3_EXTI8_PE AFIO_EXTICR3_EXTI8_PE_Msk /*!< PE[8] pin */
+#define AFIO_EXTICR3_EXTI8_PF_Pos (0U)
+#define AFIO_EXTICR3_EXTI8_PF_Msk (0x5U << AFIO_EXTICR3_EXTI8_PF_Pos) /*!< 0x00000005 */
+#define AFIO_EXTICR3_EXTI8_PF AFIO_EXTICR3_EXTI8_PF_Msk /*!< PF[8] pin */
+#define AFIO_EXTICR3_EXTI8_PG_Pos (1U)
+#define AFIO_EXTICR3_EXTI8_PG_Msk (0x3U << AFIO_EXTICR3_EXTI8_PG_Pos) /*!< 0x00000006 */
+#define AFIO_EXTICR3_EXTI8_PG AFIO_EXTICR3_EXTI8_PG_Msk /*!< PG[8] pin */
+
+/*!< EXTI9 configuration */
+#define AFIO_EXTICR3_EXTI9_PA ((uint32_t)0x00000000) /*!< PA[9] pin */
+#define AFIO_EXTICR3_EXTI9_PB_Pos (4U)
+#define AFIO_EXTICR3_EXTI9_PB_Msk (0x1U << AFIO_EXTICR3_EXTI9_PB_Pos) /*!< 0x00000010 */
+#define AFIO_EXTICR3_EXTI9_PB AFIO_EXTICR3_EXTI9_PB_Msk /*!< PB[9] pin */
+#define AFIO_EXTICR3_EXTI9_PC_Pos (5U)
+#define AFIO_EXTICR3_EXTI9_PC_Msk (0x1U << AFIO_EXTICR3_EXTI9_PC_Pos) /*!< 0x00000020 */
+#define AFIO_EXTICR3_EXTI9_PC AFIO_EXTICR3_EXTI9_PC_Msk /*!< PC[9] pin */
+#define AFIO_EXTICR3_EXTI9_PD_Pos (4U)
+#define AFIO_EXTICR3_EXTI9_PD_Msk (0x3U << AFIO_EXTICR3_EXTI9_PD_Pos) /*!< 0x00000030 */
+#define AFIO_EXTICR3_EXTI9_PD AFIO_EXTICR3_EXTI9_PD_Msk /*!< PD[9] pin */
+#define AFIO_EXTICR3_EXTI9_PE_Pos (6U)
+#define AFIO_EXTICR3_EXTI9_PE_Msk (0x1U << AFIO_EXTICR3_EXTI9_PE_Pos) /*!< 0x00000040 */
+#define AFIO_EXTICR3_EXTI9_PE AFIO_EXTICR3_EXTI9_PE_Msk /*!< PE[9] pin */
+#define AFIO_EXTICR3_EXTI9_PF_Pos (4U)
+#define AFIO_EXTICR3_EXTI9_PF_Msk (0x5U << AFIO_EXTICR3_EXTI9_PF_Pos) /*!< 0x00000050 */
+#define AFIO_EXTICR3_EXTI9_PF AFIO_EXTICR3_EXTI9_PF_Msk /*!< PF[9] pin */
+#define AFIO_EXTICR3_EXTI9_PG_Pos (5U)
+#define AFIO_EXTICR3_EXTI9_PG_Msk (0x3U << AFIO_EXTICR3_EXTI9_PG_Pos) /*!< 0x00000060 */
+#define AFIO_EXTICR3_EXTI9_PG AFIO_EXTICR3_EXTI9_PG_Msk /*!< PG[9] pin */
+
+/*!< EXTI10 configuration */
+#define AFIO_EXTICR3_EXTI10_PA ((uint32_t)0x00000000) /*!< PA[10] pin */
+#define AFIO_EXTICR3_EXTI10_PB_Pos (8U)
+#define AFIO_EXTICR3_EXTI10_PB_Msk (0x1U << AFIO_EXTICR3_EXTI10_PB_Pos) /*!< 0x00000100 */
+#define AFIO_EXTICR3_EXTI10_PB AFIO_EXTICR3_EXTI10_PB_Msk /*!< PB[10] pin */
+#define AFIO_EXTICR3_EXTI10_PC_Pos (9U)
+#define AFIO_EXTICR3_EXTI10_PC_Msk (0x1U << AFIO_EXTICR3_EXTI10_PC_Pos) /*!< 0x00000200 */
+#define AFIO_EXTICR3_EXTI10_PC AFIO_EXTICR3_EXTI10_PC_Msk /*!< PC[10] pin */
+#define AFIO_EXTICR3_EXTI10_PD_Pos (8U)
+#define AFIO_EXTICR3_EXTI10_PD_Msk (0x3U << AFIO_EXTICR3_EXTI10_PD_Pos) /*!< 0x00000300 */
+#define AFIO_EXTICR3_EXTI10_PD AFIO_EXTICR3_EXTI10_PD_Msk /*!< PD[10] pin */
+#define AFIO_EXTICR3_EXTI10_PE_Pos (10U)
+#define AFIO_EXTICR3_EXTI10_PE_Msk (0x1U << AFIO_EXTICR3_EXTI10_PE_Pos) /*!< 0x00000400 */
+#define AFIO_EXTICR3_EXTI10_PE AFIO_EXTICR3_EXTI10_PE_Msk /*!< PE[10] pin */
+#define AFIO_EXTICR3_EXTI10_PF_Pos (8U)
+#define AFIO_EXTICR3_EXTI10_PF_Msk (0x5U << AFIO_EXTICR3_EXTI10_PF_Pos) /*!< 0x00000500 */
+#define AFIO_EXTICR3_EXTI10_PF AFIO_EXTICR3_EXTI10_PF_Msk /*!< PF[10] pin */
+#define AFIO_EXTICR3_EXTI10_PG_Pos (9U)
+#define AFIO_EXTICR3_EXTI10_PG_Msk (0x3U << AFIO_EXTICR3_EXTI10_PG_Pos) /*!< 0x00000600 */
+#define AFIO_EXTICR3_EXTI10_PG AFIO_EXTICR3_EXTI10_PG_Msk /*!< PG[10] pin */
+
+/*!< EXTI11 configuration */
+#define AFIO_EXTICR3_EXTI11_PA ((uint32_t)0x00000000) /*!< PA[11] pin */
+#define AFIO_EXTICR3_EXTI11_PB_Pos (12U)
+#define AFIO_EXTICR3_EXTI11_PB_Msk (0x1U << AFIO_EXTICR3_EXTI11_PB_Pos) /*!< 0x00001000 */
+#define AFIO_EXTICR3_EXTI11_PB AFIO_EXTICR3_EXTI11_PB_Msk /*!< PB[11] pin */
+#define AFIO_EXTICR3_EXTI11_PC_Pos (13U)
+#define AFIO_EXTICR3_EXTI11_PC_Msk (0x1U << AFIO_EXTICR3_EXTI11_PC_Pos) /*!< 0x00002000 */
+#define AFIO_EXTICR3_EXTI11_PC AFIO_EXTICR3_EXTI11_PC_Msk /*!< PC[11] pin */
+#define AFIO_EXTICR3_EXTI11_PD_Pos (12U)
+#define AFIO_EXTICR3_EXTI11_PD_Msk (0x3U << AFIO_EXTICR3_EXTI11_PD_Pos) /*!< 0x00003000 */
+#define AFIO_EXTICR3_EXTI11_PD AFIO_EXTICR3_EXTI11_PD_Msk /*!< PD[11] pin */
+#define AFIO_EXTICR3_EXTI11_PE_Pos (14U)
+#define AFIO_EXTICR3_EXTI11_PE_Msk (0x1U << AFIO_EXTICR3_EXTI11_PE_Pos) /*!< 0x00004000 */
+#define AFIO_EXTICR3_EXTI11_PE AFIO_EXTICR3_EXTI11_PE_Msk /*!< PE[11] pin */
+#define AFIO_EXTICR3_EXTI11_PF_Pos (12U)
+#define AFIO_EXTICR3_EXTI11_PF_Msk (0x5U << AFIO_EXTICR3_EXTI11_PF_Pos) /*!< 0x00005000 */
+#define AFIO_EXTICR3_EXTI11_PF AFIO_EXTICR3_EXTI11_PF_Msk /*!< PF[11] pin */
+#define AFIO_EXTICR3_EXTI11_PG_Pos (13U)
+#define AFIO_EXTICR3_EXTI11_PG_Msk (0x3U << AFIO_EXTICR3_EXTI11_PG_Pos) /*!< 0x00006000 */
+#define AFIO_EXTICR3_EXTI11_PG AFIO_EXTICR3_EXTI11_PG_Msk /*!< PG[11] pin */
+
+/***************** Bit definition for AFIO_EXTICR4 register *****************/
+#define AFIO_EXTICR4_EXTI12_Pos (0U)
+#define AFIO_EXTICR4_EXTI12_Msk (0xFU << AFIO_EXTICR4_EXTI12_Pos) /*!< 0x0000000F */
+#define AFIO_EXTICR4_EXTI12 AFIO_EXTICR4_EXTI12_Msk /*!< EXTI 12 configuration */
+#define AFIO_EXTICR4_EXTI13_Pos (4U)
+#define AFIO_EXTICR4_EXTI13_Msk (0xFU << AFIO_EXTICR4_EXTI13_Pos) /*!< 0x000000F0 */
+#define AFIO_EXTICR4_EXTI13 AFIO_EXTICR4_EXTI13_Msk /*!< EXTI 13 configuration */
+#define AFIO_EXTICR4_EXTI14_Pos (8U)
+#define AFIO_EXTICR4_EXTI14_Msk (0xFU << AFIO_EXTICR4_EXTI14_Pos) /*!< 0x00000F00 */
+#define AFIO_EXTICR4_EXTI14 AFIO_EXTICR4_EXTI14_Msk /*!< EXTI 14 configuration */
+#define AFIO_EXTICR4_EXTI15_Pos (12U)
+#define AFIO_EXTICR4_EXTI15_Msk (0xFU << AFIO_EXTICR4_EXTI15_Pos) /*!< 0x0000F000 */
+#define AFIO_EXTICR4_EXTI15 AFIO_EXTICR4_EXTI15_Msk /*!< EXTI 15 configuration */
+
+/* EXTI12 configuration */
+#define AFIO_EXTICR4_EXTI12_PA ((uint32_t)0x00000000) /*!< PA[12] pin */
+#define AFIO_EXTICR4_EXTI12_PB_Pos (0U)
+#define AFIO_EXTICR4_EXTI12_PB_Msk (0x1U << AFIO_EXTICR4_EXTI12_PB_Pos) /*!< 0x00000001 */
+#define AFIO_EXTICR4_EXTI12_PB AFIO_EXTICR4_EXTI12_PB_Msk /*!< PB[12] pin */
+#define AFIO_EXTICR4_EXTI12_PC_Pos (1U)
+#define AFIO_EXTICR4_EXTI12_PC_Msk (0x1U << AFIO_EXTICR4_EXTI12_PC_Pos) /*!< 0x00000002 */
+#define AFIO_EXTICR4_EXTI12_PC AFIO_EXTICR4_EXTI12_PC_Msk /*!< PC[12] pin */
+#define AFIO_EXTICR4_EXTI12_PD_Pos (0U)
+#define AFIO_EXTICR4_EXTI12_PD_Msk (0x3U << AFIO_EXTICR4_EXTI12_PD_Pos) /*!< 0x00000003 */
+#define AFIO_EXTICR4_EXTI12_PD AFIO_EXTICR4_EXTI12_PD_Msk /*!< PD[12] pin */
+#define AFIO_EXTICR4_EXTI12_PE_Pos (2U)
+#define AFIO_EXTICR4_EXTI12_PE_Msk (0x1U << AFIO_EXTICR4_EXTI12_PE_Pos) /*!< 0x00000004 */
+#define AFIO_EXTICR4_EXTI12_PE AFIO_EXTICR4_EXTI12_PE_Msk /*!< PE[12] pin */
+#define AFIO_EXTICR4_EXTI12_PF_Pos (0U)
+#define AFIO_EXTICR4_EXTI12_PF_Msk (0x5U << AFIO_EXTICR4_EXTI12_PF_Pos) /*!< 0x00000005 */
+#define AFIO_EXTICR4_EXTI12_PF AFIO_EXTICR4_EXTI12_PF_Msk /*!< PF[12] pin */
+#define AFIO_EXTICR4_EXTI12_PG_Pos (1U)
+#define AFIO_EXTICR4_EXTI12_PG_Msk (0x3U << AFIO_EXTICR4_EXTI12_PG_Pos) /*!< 0x00000006 */
+#define AFIO_EXTICR4_EXTI12_PG AFIO_EXTICR4_EXTI12_PG_Msk /*!< PG[12] pin */
+
+/* EXTI13 configuration */
+#define AFIO_EXTICR4_EXTI13_PA ((uint32_t)0x00000000) /*!< PA[13] pin */
+#define AFIO_EXTICR4_EXTI13_PB_Pos (4U)
+#define AFIO_EXTICR4_EXTI13_PB_Msk (0x1U << AFIO_EXTICR4_EXTI13_PB_Pos) /*!< 0x00000010 */
+#define AFIO_EXTICR4_EXTI13_PB AFIO_EXTICR4_EXTI13_PB_Msk /*!< PB[13] pin */
+#define AFIO_EXTICR4_EXTI13_PC_Pos (5U)
+#define AFIO_EXTICR4_EXTI13_PC_Msk (0x1U << AFIO_EXTICR4_EXTI13_PC_Pos) /*!< 0x00000020 */
+#define AFIO_EXTICR4_EXTI13_PC AFIO_EXTICR4_EXTI13_PC_Msk /*!< PC[13] pin */
+#define AFIO_EXTICR4_EXTI13_PD_Pos (4U)
+#define AFIO_EXTICR4_EXTI13_PD_Msk (0x3U << AFIO_EXTICR4_EXTI13_PD_Pos) /*!< 0x00000030 */
+#define AFIO_EXTICR4_EXTI13_PD AFIO_EXTICR4_EXTI13_PD_Msk /*!< PD[13] pin */
+#define AFIO_EXTICR4_EXTI13_PE_Pos (6U)
+#define AFIO_EXTICR4_EXTI13_PE_Msk (0x1U << AFIO_EXTICR4_EXTI13_PE_Pos) /*!< 0x00000040 */
+#define AFIO_EXTICR4_EXTI13_PE AFIO_EXTICR4_EXTI13_PE_Msk /*!< PE[13] pin */
+#define AFIO_EXTICR4_EXTI13_PF_Pos (4U)
+#define AFIO_EXTICR4_EXTI13_PF_Msk (0x5U << AFIO_EXTICR4_EXTI13_PF_Pos) /*!< 0x00000050 */
+#define AFIO_EXTICR4_EXTI13_PF AFIO_EXTICR4_EXTI13_PF_Msk /*!< PF[13] pin */
+#define AFIO_EXTICR4_EXTI13_PG_Pos (5U)
+#define AFIO_EXTICR4_EXTI13_PG_Msk (0x3U << AFIO_EXTICR4_EXTI13_PG_Pos) /*!< 0x00000060 */
+#define AFIO_EXTICR4_EXTI13_PG AFIO_EXTICR4_EXTI13_PG_Msk /*!< PG[13] pin */
+
+/*!< EXTI14 configuration */
+#define AFIO_EXTICR4_EXTI14_PA ((uint32_t)0x00000000) /*!< PA[14] pin */
+#define AFIO_EXTICR4_EXTI14_PB_Pos (8U)
+#define AFIO_EXTICR4_EXTI14_PB_Msk (0x1U << AFIO_EXTICR4_EXTI14_PB_Pos) /*!< 0x00000100 */
+#define AFIO_EXTICR4_EXTI14_PB AFIO_EXTICR4_EXTI14_PB_Msk /*!< PB[14] pin */
+#define AFIO_EXTICR4_EXTI14_PC_Pos (9U)
+#define AFIO_EXTICR4_EXTI14_PC_Msk (0x1U << AFIO_EXTICR4_EXTI14_PC_Pos) /*!< 0x00000200 */
+#define AFIO_EXTICR4_EXTI14_PC AFIO_EXTICR4_EXTI14_PC_Msk /*!< PC[14] pin */
+#define AFIO_EXTICR4_EXTI14_PD_Pos (8U)
+#define AFIO_EXTICR4_EXTI14_PD_Msk (0x3U << AFIO_EXTICR4_EXTI14_PD_Pos) /*!< 0x00000300 */
+#define AFIO_EXTICR4_EXTI14_PD AFIO_EXTICR4_EXTI14_PD_Msk /*!< PD[14] pin */
+#define AFIO_EXTICR4_EXTI14_PE_Pos (10U)
+#define AFIO_EXTICR4_EXTI14_PE_Msk (0x1U << AFIO_EXTICR4_EXTI14_PE_Pos) /*!< 0x00000400 */
+#define AFIO_EXTICR4_EXTI14_PE AFIO_EXTICR4_EXTI14_PE_Msk /*!< PE[14] pin */
+#define AFIO_EXTICR4_EXTI14_PF_Pos (8U)
+#define AFIO_EXTICR4_EXTI14_PF_Msk (0x5U << AFIO_EXTICR4_EXTI14_PF_Pos) /*!< 0x00000500 */
+#define AFIO_EXTICR4_EXTI14_PF AFIO_EXTICR4_EXTI14_PF_Msk /*!< PF[14] pin */
+#define AFIO_EXTICR4_EXTI14_PG_Pos (9U)
+#define AFIO_EXTICR4_EXTI14_PG_Msk (0x3U << AFIO_EXTICR4_EXTI14_PG_Pos) /*!< 0x00000600 */
+#define AFIO_EXTICR4_EXTI14_PG AFIO_EXTICR4_EXTI14_PG_Msk /*!< PG[14] pin */
+
+/*!< EXTI15 configuration */
+#define AFIO_EXTICR4_EXTI15_PA ((uint32_t)0x00000000) /*!< PA[15] pin */
+#define AFIO_EXTICR4_EXTI15_PB_Pos (12U)
+#define AFIO_EXTICR4_EXTI15_PB_Msk (0x1U << AFIO_EXTICR4_EXTI15_PB_Pos) /*!< 0x00001000 */
+#define AFIO_EXTICR4_EXTI15_PB AFIO_EXTICR4_EXTI15_PB_Msk /*!< PB[15] pin */
+#define AFIO_EXTICR4_EXTI15_PC_Pos (13U)
+#define AFIO_EXTICR4_EXTI15_PC_Msk (0x1U << AFIO_EXTICR4_EXTI15_PC_Pos) /*!< 0x00002000 */
+#define AFIO_EXTICR4_EXTI15_PC AFIO_EXTICR4_EXTI15_PC_Msk /*!< PC[15] pin */
+#define AFIO_EXTICR4_EXTI15_PD_Pos (12U)
+#define AFIO_EXTICR4_EXTI15_PD_Msk (0x3U << AFIO_EXTICR4_EXTI15_PD_Pos) /*!< 0x00003000 */
+#define AFIO_EXTICR4_EXTI15_PD AFIO_EXTICR4_EXTI15_PD_Msk /*!< PD[15] pin */
+#define AFIO_EXTICR4_EXTI15_PE_Pos (14U)
+#define AFIO_EXTICR4_EXTI15_PE_Msk (0x1U << AFIO_EXTICR4_EXTI15_PE_Pos) /*!< 0x00004000 */
+#define AFIO_EXTICR4_EXTI15_PE AFIO_EXTICR4_EXTI15_PE_Msk /*!< PE[15] pin */
+#define AFIO_EXTICR4_EXTI15_PF_Pos (12U)
+#define AFIO_EXTICR4_EXTI15_PF_Msk (0x5U << AFIO_EXTICR4_EXTI15_PF_Pos) /*!< 0x00005000 */
+#define AFIO_EXTICR4_EXTI15_PF AFIO_EXTICR4_EXTI15_PF_Msk /*!< PF[15] pin */
+#define AFIO_EXTICR4_EXTI15_PG_Pos (13U)
+#define AFIO_EXTICR4_EXTI15_PG_Msk (0x3U << AFIO_EXTICR4_EXTI15_PG_Pos) /*!< 0x00006000 */
+#define AFIO_EXTICR4_EXTI15_PG AFIO_EXTICR4_EXTI15_PG_Msk /*!< PG[15] pin */
+
+/****************** Bit definition for AFIO_MAPR2 register ******************/
+
+
+
+/******************************************************************************/
+/* */
+/* SystemTick */
+/* */
+/******************************************************************************/
+
+/***************** Bit definition for SysTick_CTRL register *****************/
+#define SysTick_CTRL_ENABLE ((uint32_t)0x00000001) /*!< Counter enable */
+#define SysTick_CTRL_TICKINT ((uint32_t)0x00000002) /*!< Counting down to 0 pends the SysTick handler */
+#define SysTick_CTRL_CLKSOURCE ((uint32_t)0x00000004) /*!< Clock source */
+#define SysTick_CTRL_COUNTFLAG ((uint32_t)0x00010000) /*!< Count Flag */
+
+/***************** Bit definition for SysTick_LOAD register *****************/
+#define SysTick_LOAD_RELOAD ((uint32_t)0x00FFFFFF) /*!< Value to load into the SysTick Current Value Register when the counter reaches 0 */
+
+/***************** Bit definition for SysTick_VAL register ******************/
+#define SysTick_VAL_CURRENT ((uint32_t)0x00FFFFFF) /*!< Current value at the time the register is accessed */
+
+/***************** Bit definition for SysTick_CALIB register ****************/
+#define SysTick_CALIB_TENMS ((uint32_t)0x00FFFFFF) /*!< Reload value to use for 10ms timing */
+#define SysTick_CALIB_SKEW ((uint32_t)0x40000000) /*!< Calibration value is not exactly 10 ms */
+#define SysTick_CALIB_NOREF ((uint32_t)0x80000000) /*!< The reference clock is not provided */
+
+/******************************************************************************/
+/* */
+/* Nested Vectored Interrupt Controller */
+/* */
+/******************************************************************************/
+
+/****************** Bit definition for NVIC_ISER register *******************/
+#define NVIC_ISER_SETENA_Pos (0U)
+#define NVIC_ISER_SETENA_Msk (0xFFFFFFFFU << NVIC_ISER_SETENA_Pos) /*!< 0xFFFFFFFF */
+#define NVIC_ISER_SETENA NVIC_ISER_SETENA_Msk /*!< Interrupt set enable bits */
+#define NVIC_ISER_SETENA_0 (0x00000001U << NVIC_ISER_SETENA_Pos) /*!< 0x00000001 */
+#define NVIC_ISER_SETENA_1 (0x00000002U << NVIC_ISER_SETENA_Pos) /*!< 0x00000002 */
+#define NVIC_ISER_SETENA_2 (0x00000004U << NVIC_ISER_SETENA_Pos) /*!< 0x00000004 */
+#define NVIC_ISER_SETENA_3 (0x00000008U << NVIC_ISER_SETENA_Pos) /*!< 0x00000008 */
+#define NVIC_ISER_SETENA_4 (0x00000010U << NVIC_ISER_SETENA_Pos) /*!< 0x00000010 */
+#define NVIC_ISER_SETENA_5 (0x00000020U << NVIC_ISER_SETENA_Pos) /*!< 0x00000020 */
+#define NVIC_ISER_SETENA_6 (0x00000040U << NVIC_ISER_SETENA_Pos) /*!< 0x00000040 */
+#define NVIC_ISER_SETENA_7 (0x00000080U << NVIC_ISER_SETENA_Pos) /*!< 0x00000080 */
+#define NVIC_ISER_SETENA_8 (0x00000100U << NVIC_ISER_SETENA_Pos) /*!< 0x00000100 */
+#define NVIC_ISER_SETENA_9 (0x00000200U << NVIC_ISER_SETENA_Pos) /*!< 0x00000200 */
+#define NVIC_ISER_SETENA_10 (0x00000400U << NVIC_ISER_SETENA_Pos) /*!< 0x00000400 */
+#define NVIC_ISER_SETENA_11 (0x00000800U << NVIC_ISER_SETENA_Pos) /*!< 0x00000800 */
+#define NVIC_ISER_SETENA_12 (0x00001000U << NVIC_ISER_SETENA_Pos) /*!< 0x00001000 */
+#define NVIC_ISER_SETENA_13 (0x00002000U << NVIC_ISER_SETENA_Pos) /*!< 0x00002000 */
+#define NVIC_ISER_SETENA_14 (0x00004000U << NVIC_ISER_SETENA_Pos) /*!< 0x00004000 */
+#define NVIC_ISER_SETENA_15 (0x00008000U << NVIC_ISER_SETENA_Pos) /*!< 0x00008000 */
+#define NVIC_ISER_SETENA_16 (0x00010000U << NVIC_ISER_SETENA_Pos) /*!< 0x00010000 */
+#define NVIC_ISER_SETENA_17 (0x00020000U << NVIC_ISER_SETENA_Pos) /*!< 0x00020000 */
+#define NVIC_ISER_SETENA_18 (0x00040000U << NVIC_ISER_SETENA_Pos) /*!< 0x00040000 */
+#define NVIC_ISER_SETENA_19 (0x00080000U << NVIC_ISER_SETENA_Pos) /*!< 0x00080000 */
+#define NVIC_ISER_SETENA_20 (0x00100000U << NVIC_ISER_SETENA_Pos) /*!< 0x00100000 */
+#define NVIC_ISER_SETENA_21 (0x00200000U << NVIC_ISER_SETENA_Pos) /*!< 0x00200000 */
+#define NVIC_ISER_SETENA_22 (0x00400000U << NVIC_ISER_SETENA_Pos) /*!< 0x00400000 */
+#define NVIC_ISER_SETENA_23 (0x00800000U << NVIC_ISER_SETENA_Pos) /*!< 0x00800000 */
+#define NVIC_ISER_SETENA_24 (0x01000000U << NVIC_ISER_SETENA_Pos) /*!< 0x01000000 */
+#define NVIC_ISER_SETENA_25 (0x02000000U << NVIC_ISER_SETENA_Pos) /*!< 0x02000000 */
+#define NVIC_ISER_SETENA_26 (0x04000000U << NVIC_ISER_SETENA_Pos) /*!< 0x04000000 */
+#define NVIC_ISER_SETENA_27 (0x08000000U << NVIC_ISER_SETENA_Pos) /*!< 0x08000000 */
+#define NVIC_ISER_SETENA_28 (0x10000000U << NVIC_ISER_SETENA_Pos) /*!< 0x10000000 */
+#define NVIC_ISER_SETENA_29 (0x20000000U << NVIC_ISER_SETENA_Pos) /*!< 0x20000000 */
+#define NVIC_ISER_SETENA_30 (0x40000000U << NVIC_ISER_SETENA_Pos) /*!< 0x40000000 */
+#define NVIC_ISER_SETENA_31 (0x80000000U << NVIC_ISER_SETENA_Pos) /*!< 0x80000000 */
+
+/****************** Bit definition for NVIC_ICER register *******************/
+#define NVIC_ICER_CLRENA_Pos (0U)
+#define NVIC_ICER_CLRENA_Msk (0xFFFFFFFFU << NVIC_ICER_CLRENA_Pos) /*!< 0xFFFFFFFF */
+#define NVIC_ICER_CLRENA NVIC_ICER_CLRENA_Msk /*!< Interrupt clear-enable bits */
+#define NVIC_ICER_CLRENA_0 (0x00000001U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000001 */
+#define NVIC_ICER_CLRENA_1 (0x00000002U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000002 */
+#define NVIC_ICER_CLRENA_2 (0x00000004U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000004 */
+#define NVIC_ICER_CLRENA_3 (0x00000008U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000008 */
+#define NVIC_ICER_CLRENA_4 (0x00000010U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000010 */
+#define NVIC_ICER_CLRENA_5 (0x00000020U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000020 */
+#define NVIC_ICER_CLRENA_6 (0x00000040U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000040 */
+#define NVIC_ICER_CLRENA_7 (0x00000080U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000080 */
+#define NVIC_ICER_CLRENA_8 (0x00000100U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000100 */
+#define NVIC_ICER_CLRENA_9 (0x00000200U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000200 */
+#define NVIC_ICER_CLRENA_10 (0x00000400U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000400 */
+#define NVIC_ICER_CLRENA_11 (0x00000800U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000800 */
+#define NVIC_ICER_CLRENA_12 (0x00001000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00001000 */
+#define NVIC_ICER_CLRENA_13 (0x00002000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00002000 */
+#define NVIC_ICER_CLRENA_14 (0x00004000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00004000 */
+#define NVIC_ICER_CLRENA_15 (0x00008000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00008000 */
+#define NVIC_ICER_CLRENA_16 (0x00010000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00010000 */
+#define NVIC_ICER_CLRENA_17 (0x00020000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00020000 */
+#define NVIC_ICER_CLRENA_18 (0x00040000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00040000 */
+#define NVIC_ICER_CLRENA_19 (0x00080000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00080000 */
+#define NVIC_ICER_CLRENA_20 (0x00100000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00100000 */
+#define NVIC_ICER_CLRENA_21 (0x00200000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00200000 */
+#define NVIC_ICER_CLRENA_22 (0x00400000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00400000 */
+#define NVIC_ICER_CLRENA_23 (0x00800000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00800000 */
+#define NVIC_ICER_CLRENA_24 (0x01000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x01000000 */
+#define NVIC_ICER_CLRENA_25 (0x02000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x02000000 */
+#define NVIC_ICER_CLRENA_26 (0x04000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x04000000 */
+#define NVIC_ICER_CLRENA_27 (0x08000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x08000000 */
+#define NVIC_ICER_CLRENA_28 (0x10000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x10000000 */
+#define NVIC_ICER_CLRENA_29 (0x20000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x20000000 */
+#define NVIC_ICER_CLRENA_30 (0x40000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x40000000 */
+#define NVIC_ICER_CLRENA_31 (0x80000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x80000000 */
+
+/****************** Bit definition for NVIC_ISPR register *******************/
+#define NVIC_ISPR_SETPEND_Pos (0U)
+#define NVIC_ISPR_SETPEND_Msk (0xFFFFFFFFU << NVIC_ISPR_SETPEND_Pos) /*!< 0xFFFFFFFF */
+#define NVIC_ISPR_SETPEND NVIC_ISPR_SETPEND_Msk /*!< Interrupt set-pending bits */
+#define NVIC_ISPR_SETPEND_0 (0x00000001U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000001 */
+#define NVIC_ISPR_SETPEND_1 (0x00000002U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000002 */
+#define NVIC_ISPR_SETPEND_2 (0x00000004U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000004 */
+#define NVIC_ISPR_SETPEND_3 (0x00000008U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000008 */
+#define NVIC_ISPR_SETPEND_4 (0x00000010U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000010 */
+#define NVIC_ISPR_SETPEND_5 (0x00000020U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000020 */
+#define NVIC_ISPR_SETPEND_6 (0x00000040U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000040 */
+#define NVIC_ISPR_SETPEND_7 (0x00000080U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000080 */
+#define NVIC_ISPR_SETPEND_8 (0x00000100U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000100 */
+#define NVIC_ISPR_SETPEND_9 (0x00000200U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000200 */
+#define NVIC_ISPR_SETPEND_10 (0x00000400U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000400 */
+#define NVIC_ISPR_SETPEND_11 (0x00000800U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000800 */
+#define NVIC_ISPR_SETPEND_12 (0x00001000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00001000 */
+#define NVIC_ISPR_SETPEND_13 (0x00002000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00002000 */
+#define NVIC_ISPR_SETPEND_14 (0x00004000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00004000 */
+#define NVIC_ISPR_SETPEND_15 (0x00008000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00008000 */
+#define NVIC_ISPR_SETPEND_16 (0x00010000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00010000 */
+#define NVIC_ISPR_SETPEND_17 (0x00020000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00020000 */
+#define NVIC_ISPR_SETPEND_18 (0x00040000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00040000 */
+#define NVIC_ISPR_SETPEND_19 (0x00080000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00080000 */
+#define NVIC_ISPR_SETPEND_20 (0x00100000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00100000 */
+#define NVIC_ISPR_SETPEND_21 (0x00200000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00200000 */
+#define NVIC_ISPR_SETPEND_22 (0x00400000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00400000 */
+#define NVIC_ISPR_SETPEND_23 (0x00800000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00800000 */
+#define NVIC_ISPR_SETPEND_24 (0x01000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x01000000 */
+#define NVIC_ISPR_SETPEND_25 (0x02000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x02000000 */
+#define NVIC_ISPR_SETPEND_26 (0x04000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x04000000 */
+#define NVIC_ISPR_SETPEND_27 (0x08000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x08000000 */
+#define NVIC_ISPR_SETPEND_28 (0x10000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x10000000 */
+#define NVIC_ISPR_SETPEND_29 (0x20000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x20000000 */
+#define NVIC_ISPR_SETPEND_30 (0x40000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x40000000 */
+#define NVIC_ISPR_SETPEND_31 (0x80000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x80000000 */
+
+/****************** Bit definition for NVIC_ICPR register *******************/
+#define NVIC_ICPR_CLRPEND_Pos (0U)
+#define NVIC_ICPR_CLRPEND_Msk (0xFFFFFFFFU << NVIC_ICPR_CLRPEND_Pos) /*!< 0xFFFFFFFF */
+#define NVIC_ICPR_CLRPEND NVIC_ICPR_CLRPEND_Msk /*!< Interrupt clear-pending bits */
+#define NVIC_ICPR_CLRPEND_0 (0x00000001U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000001 */
+#define NVIC_ICPR_CLRPEND_1 (0x00000002U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000002 */
+#define NVIC_ICPR_CLRPEND_2 (0x00000004U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000004 */
+#define NVIC_ICPR_CLRPEND_3 (0x00000008U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000008 */
+#define NVIC_ICPR_CLRPEND_4 (0x00000010U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000010 */
+#define NVIC_ICPR_CLRPEND_5 (0x00000020U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000020 */
+#define NVIC_ICPR_CLRPEND_6 (0x00000040U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000040 */
+#define NVIC_ICPR_CLRPEND_7 (0x00000080U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000080 */
+#define NVIC_ICPR_CLRPEND_8 (0x00000100U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000100 */
+#define NVIC_ICPR_CLRPEND_9 (0x00000200U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000200 */
+#define NVIC_ICPR_CLRPEND_10 (0x00000400U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000400 */
+#define NVIC_ICPR_CLRPEND_11 (0x00000800U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000800 */
+#define NVIC_ICPR_CLRPEND_12 (0x00001000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00001000 */
+#define NVIC_ICPR_CLRPEND_13 (0x00002000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00002000 */
+#define NVIC_ICPR_CLRPEND_14 (0x00004000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00004000 */
+#define NVIC_ICPR_CLRPEND_15 (0x00008000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00008000 */
+#define NVIC_ICPR_CLRPEND_16 (0x00010000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00010000 */
+#define NVIC_ICPR_CLRPEND_17 (0x00020000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00020000 */
+#define NVIC_ICPR_CLRPEND_18 (0x00040000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00040000 */
+#define NVIC_ICPR_CLRPEND_19 (0x00080000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00080000 */
+#define NVIC_ICPR_CLRPEND_20 (0x00100000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00100000 */
+#define NVIC_ICPR_CLRPEND_21 (0x00200000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00200000 */
+#define NVIC_ICPR_CLRPEND_22 (0x00400000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00400000 */
+#define NVIC_ICPR_CLRPEND_23 (0x00800000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00800000 */
+#define NVIC_ICPR_CLRPEND_24 (0x01000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x01000000 */
+#define NVIC_ICPR_CLRPEND_25 (0x02000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x02000000 */
+#define NVIC_ICPR_CLRPEND_26 (0x04000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x04000000 */
+#define NVIC_ICPR_CLRPEND_27 (0x08000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x08000000 */
+#define NVIC_ICPR_CLRPEND_28 (0x10000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x10000000 */
+#define NVIC_ICPR_CLRPEND_29 (0x20000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x20000000 */
+#define NVIC_ICPR_CLRPEND_30 (0x40000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x40000000 */
+#define NVIC_ICPR_CLRPEND_31 (0x80000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x80000000 */
+
+/****************** Bit definition for NVIC_IABR register *******************/
+#define NVIC_IABR_ACTIVE_Pos (0U)
+#define NVIC_IABR_ACTIVE_Msk (0xFFFFFFFFU << NVIC_IABR_ACTIVE_Pos) /*!< 0xFFFFFFFF */
+#define NVIC_IABR_ACTIVE NVIC_IABR_ACTIVE_Msk /*!< Interrupt active flags */
+#define NVIC_IABR_ACTIVE_0 (0x00000001U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000001 */
+#define NVIC_IABR_ACTIVE_1 (0x00000002U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000002 */
+#define NVIC_IABR_ACTIVE_2 (0x00000004U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000004 */
+#define NVIC_IABR_ACTIVE_3 (0x00000008U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000008 */
+#define NVIC_IABR_ACTIVE_4 (0x00000010U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000010 */
+#define NVIC_IABR_ACTIVE_5 (0x00000020U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000020 */
+#define NVIC_IABR_ACTIVE_6 (0x00000040U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000040 */
+#define NVIC_IABR_ACTIVE_7 (0x00000080U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000080 */
+#define NVIC_IABR_ACTIVE_8 (0x00000100U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000100 */
+#define NVIC_IABR_ACTIVE_9 (0x00000200U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000200 */
+#define NVIC_IABR_ACTIVE_10 (0x00000400U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000400 */
+#define NVIC_IABR_ACTIVE_11 (0x00000800U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000800 */
+#define NVIC_IABR_ACTIVE_12 (0x00001000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00001000 */
+#define NVIC_IABR_ACTIVE_13 (0x00002000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00002000 */
+#define NVIC_IABR_ACTIVE_14 (0x00004000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00004000 */
+#define NVIC_IABR_ACTIVE_15 (0x00008000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00008000 */
+#define NVIC_IABR_ACTIVE_16 (0x00010000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00010000 */
+#define NVIC_IABR_ACTIVE_17 (0x00020000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00020000 */
+#define NVIC_IABR_ACTIVE_18 (0x00040000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00040000 */
+#define NVIC_IABR_ACTIVE_19 (0x00080000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00080000 */
+#define NVIC_IABR_ACTIVE_20 (0x00100000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00100000 */
+#define NVIC_IABR_ACTIVE_21 (0x00200000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00200000 */
+#define NVIC_IABR_ACTIVE_22 (0x00400000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00400000 */
+#define NVIC_IABR_ACTIVE_23 (0x00800000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00800000 */
+#define NVIC_IABR_ACTIVE_24 (0x01000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x01000000 */
+#define NVIC_IABR_ACTIVE_25 (0x02000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x02000000 */
+#define NVIC_IABR_ACTIVE_26 (0x04000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x04000000 */
+#define NVIC_IABR_ACTIVE_27 (0x08000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x08000000 */
+#define NVIC_IABR_ACTIVE_28 (0x10000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x10000000 */
+#define NVIC_IABR_ACTIVE_29 (0x20000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x20000000 */
+#define NVIC_IABR_ACTIVE_30 (0x40000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x40000000 */
+#define NVIC_IABR_ACTIVE_31 (0x80000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x80000000 */
+
+/****************** Bit definition for NVIC_PRI0 register *******************/
+#define NVIC_IPR0_PRI_0 ((uint32_t)0x000000FF) /*!< Priority of interrupt 0 */
+#define NVIC_IPR0_PRI_1 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 1 */
+#define NVIC_IPR0_PRI_2 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 2 */
+#define NVIC_IPR0_PRI_3 ((uint32_t)0xFF000000) /*!< Priority of interrupt 3 */
+
+/****************** Bit definition for NVIC_PRI1 register *******************/
+#define NVIC_IPR1_PRI_4 ((uint32_t)0x000000FF) /*!< Priority of interrupt 4 */
+#define NVIC_IPR1_PRI_5 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 5 */
+#define NVIC_IPR1_PRI_6 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 6 */
+#define NVIC_IPR1_PRI_7 ((uint32_t)0xFF000000) /*!< Priority of interrupt 7 */
+
+/****************** Bit definition for NVIC_PRI2 register *******************/
+#define NVIC_IPR2_PRI_8 ((uint32_t)0x000000FF) /*!< Priority of interrupt 8 */
+#define NVIC_IPR2_PRI_9 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 9 */
+#define NVIC_IPR2_PRI_10 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 10 */
+#define NVIC_IPR2_PRI_11 ((uint32_t)0xFF000000) /*!< Priority of interrupt 11 */
+
+/****************** Bit definition for NVIC_PRI3 register *******************/
+#define NVIC_IPR3_PRI_12 ((uint32_t)0x000000FF) /*!< Priority of interrupt 12 */
+#define NVIC_IPR3_PRI_13 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 13 */
+#define NVIC_IPR3_PRI_14 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 14 */
+#define NVIC_IPR3_PRI_15 ((uint32_t)0xFF000000) /*!< Priority of interrupt 15 */
+
+/****************** Bit definition for NVIC_PRI4 register *******************/
+#define NVIC_IPR4_PRI_16 ((uint32_t)0x000000FF) /*!< Priority of interrupt 16 */
+#define NVIC_IPR4_PRI_17 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 17 */
+#define NVIC_IPR4_PRI_18 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 18 */
+#define NVIC_IPR4_PRI_19 ((uint32_t)0xFF000000) /*!< Priority of interrupt 19 */
+
+/****************** Bit definition for NVIC_PRI5 register *******************/
+#define NVIC_IPR5_PRI_20 ((uint32_t)0x000000FF) /*!< Priority of interrupt 20 */
+#define NVIC_IPR5_PRI_21 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 21 */
+#define NVIC_IPR5_PRI_22 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 22 */
+#define NVIC_IPR5_PRI_23 ((uint32_t)0xFF000000) /*!< Priority of interrupt 23 */
+
+/****************** Bit definition for NVIC_PRI6 register *******************/
+#define NVIC_IPR6_PRI_24 ((uint32_t)0x000000FF) /*!< Priority of interrupt 24 */
+#define NVIC_IPR6_PRI_25 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 25 */
+#define NVIC_IPR6_PRI_26 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 26 */
+#define NVIC_IPR6_PRI_27 ((uint32_t)0xFF000000) /*!< Priority of interrupt 27 */
+
+/****************** Bit definition for NVIC_PRI7 register *******************/
+#define NVIC_IPR7_PRI_28 ((uint32_t)0x000000FF) /*!< Priority of interrupt 28 */
+#define NVIC_IPR7_PRI_29 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 29 */
+#define NVIC_IPR7_PRI_30 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 30 */
+#define NVIC_IPR7_PRI_31 ((uint32_t)0xFF000000) /*!< Priority of interrupt 31 */
+
+/****************** Bit definition for SCB_CPUID register *******************/
+#define SCB_CPUID_REVISION ((uint32_t)0x0000000F) /*!< Implementation defined revision number */
+#define SCB_CPUID_PARTNO ((uint32_t)0x0000FFF0) /*!< Number of processor within family */
+#define SCB_CPUID_Constant ((uint32_t)0x000F0000) /*!< Reads as 0x0F */
+#define SCB_CPUID_VARIANT ((uint32_t)0x00F00000) /*!< Implementation defined variant number */
+#define SCB_CPUID_IMPLEMENTER ((uint32_t)0xFF000000) /*!< Implementer code. ARM is 0x41 */
+
+/******************* Bit definition for SCB_ICSR register *******************/
+#define SCB_ICSR_VECTACTIVE ((uint32_t)0x000001FF) /*!< Active ISR number field */
+#define SCB_ICSR_RETTOBASE ((uint32_t)0x00000800) /*!< All active exceptions minus the IPSR_current_exception yields the empty set */
+#define SCB_ICSR_VECTPENDING ((uint32_t)0x003FF000) /*!< Pending ISR number field */
+#define SCB_ICSR_ISRPENDING ((uint32_t)0x00400000) /*!< Interrupt pending flag */
+#define SCB_ICSR_ISRPREEMPT ((uint32_t)0x00800000) /*!< It indicates that a pending interrupt becomes active in the next running cycle */
+#define SCB_ICSR_PENDSTCLR ((uint32_t)0x02000000) /*!< Clear pending SysTick bit */
+#define SCB_ICSR_PENDSTSET ((uint32_t)0x04000000) /*!< Set pending SysTick bit */
+#define SCB_ICSR_PENDSVCLR ((uint32_t)0x08000000) /*!< Clear pending pendSV bit */
+#define SCB_ICSR_PENDSVSET ((uint32_t)0x10000000) /*!< Set pending pendSV bit */
+#define SCB_ICSR_NMIPENDSET ((uint32_t)0x80000000) /*!< Set pending NMI bit */
+
+/******************* Bit definition for SCB_VTOR register *******************/
+#define SCB_VTOR_TBLOFF ((uint32_t)0x1FFFFF80) /*!< Vector table base offset field */
+#define SCB_VTOR_TBLBASE ((uint32_t)0x20000000) /*!< Table base in code(0) or RAM(1) */
+
+/*!<***************** Bit definition for SCB_AIRCR register *******************/
+#define SCB_AIRCR_VECTRESET ((uint32_t)0x00000001) /*!< System Reset bit */
+#define SCB_AIRCR_VECTCLRACTIVE ((uint32_t)0x00000002) /*!< Clear active vector bit */
+#define SCB_AIRCR_SYSRESETREQ ((uint32_t)0x00000004) /*!< Requests chip control logic to generate a reset */
+
+#define SCB_AIRCR_PRIGROUP ((uint32_t)0x00000700) /*!< PRIGROUP[2:0] bits (Priority group) */
+#define SCB_AIRCR_PRIGROUP_0 ((uint32_t)0x00000100) /*!< Bit 0 */
+#define SCB_AIRCR_PRIGROUP_1 ((uint32_t)0x00000200) /*!< Bit 1 */
+#define SCB_AIRCR_PRIGROUP_2 ((uint32_t)0x00000400) /*!< Bit 2 */
+
+/* prority group configuration */
+#define SCB_AIRCR_PRIGROUP0 ((uint32_t)0x00000000) /*!< Priority group=0 (7 bits of pre-emption priority, 1 bit of subpriority) */
+#define SCB_AIRCR_PRIGROUP1 ((uint32_t)0x00000100) /*!< Priority group=1 (6 bits of pre-emption priority, 2 bits of subpriority) */
+#define SCB_AIRCR_PRIGROUP2 ((uint32_t)0x00000200) /*!< Priority group=2 (5 bits of pre-emption priority, 3 bits of subpriority) */
+#define SCB_AIRCR_PRIGROUP3 ((uint32_t)0x00000300) /*!< Priority group=3 (4 bits of pre-emption priority, 4 bits of subpriority) */
+#define SCB_AIRCR_PRIGROUP4 ((uint32_t)0x00000400) /*!< Priority group=4 (3 bits of pre-emption priority, 5 bits of subpriority) */
+#define SCB_AIRCR_PRIGROUP5 ((uint32_t)0x00000500) /*!< Priority group=5 (2 bits of pre-emption priority, 6 bits of subpriority) */
+#define SCB_AIRCR_PRIGROUP6 ((uint32_t)0x00000600) /*!< Priority group=6 (1 bit of pre-emption priority, 7 bits of subpriority) */
+#define SCB_AIRCR_PRIGROUP7 ((uint32_t)0x00000700) /*!< Priority group=7 (no pre-emption priority, 8 bits of subpriority) */
+
+#define SCB_AIRCR_ENDIANESS ((uint32_t)0x00008000) /*!< Data endianness bit */
+#define SCB_AIRCR_VECTKEY ((uint32_t)0xFFFF0000) /*!< Register key (VECTKEY) - Reads as 0xFA05 (VECTKEYSTAT) */
+
+/******************* Bit definition for SCB_SCR register ********************/
+#define SCB_SCR_SLEEPONEXIT ((uint32_t)0x00000002) /*!< Sleep on exit bit */
+#define SCB_SCR_SLEEPDEEP ((uint32_t)0x00000004) /*!< Sleep deep bit */
+#define SCB_SCR_SEVONPEND ((uint32_t)0x00000010) /*!< Wake up from WFE */
+
+/******************** Bit definition for SCB_CCR register *******************/
+#define SCB_CCR_NONBASETHRDENA ((uint32_t)0x00000001) /*!< Thread mode can be entered from any level in Handler mode by controlled return value */
+#define SCB_CCR_USERSETMPEND ((uint32_t)0x00000002) /*!< Enables user code to write the Software Trigger Interrupt register to trigger (pend) a Main exception */
+#define SCB_CCR_UNALIGN_TRP ((uint32_t)0x00000008) /*!< Trap for unaligned access */
+#define SCB_CCR_DIV_0_TRP ((uint32_t)0x00000010) /*!< Trap on Divide by 0 */
+#define SCB_CCR_BFHFNMIGN ((uint32_t)0x00000100) /*!< Handlers running at priority -1 and -2 */
+#define SCB_CCR_STKALIGN ((uint32_t)0x00000200) /*!< On exception entry, the SP used prior to the exception is adjusted to be 8-byte aligned */
+
+/******************* Bit definition for SCB_SHPR register ********************/
+#define SCB_SHPR_PRI_N_Pos (0U)
+#define SCB_SHPR_PRI_N_Msk (0xFFU << SCB_SHPR_PRI_N_Pos) /*!< 0x000000FF */
+#define SCB_SHPR_PRI_N SCB_SHPR_PRI_N_Msk /*!< Priority of system handler 4,8, and 12. Mem Manage, reserved and Debug Monitor */
+#define SCB_SHPR_PRI_N1_Pos (8U)
+#define SCB_SHPR_PRI_N1_Msk (0xFFU << SCB_SHPR_PRI_N1_Pos) /*!< 0x0000FF00 */
+#define SCB_SHPR_PRI_N1 SCB_SHPR_PRI_N1_Msk /*!< Priority of system handler 5,9, and 13. Bus Fault, reserved and reserved */
+#define SCB_SHPR_PRI_N2_Pos (16U)
+#define SCB_SHPR_PRI_N2_Msk (0xFFU << SCB_SHPR_PRI_N2_Pos) /*!< 0x00FF0000 */
+#define SCB_SHPR_PRI_N2 SCB_SHPR_PRI_N2_Msk /*!< Priority of system handler 6,10, and 14. Usage Fault, reserved and PendSV */
+#define SCB_SHPR_PRI_N3_Pos (24U)
+#define SCB_SHPR_PRI_N3_Msk (0xFFU << SCB_SHPR_PRI_N3_Pos) /*!< 0xFF000000 */
+#define SCB_SHPR_PRI_N3 SCB_SHPR_PRI_N3_Msk /*!< Priority of system handler 7,11, and 15. Reserved, SVCall and SysTick */
+
+/****************** Bit definition for SCB_SHCSR register *******************/
+#define SCB_SHCSR_MEMFAULTACT ((uint32_t)0x00000001) /*!< MemManage is active */
+#define SCB_SHCSR_BUSFAULTACT ((uint32_t)0x00000002) /*!< BusFault is active */
+#define SCB_SHCSR_USGFAULTACT ((uint32_t)0x00000008) /*!< UsageFault is active */
+#define SCB_SHCSR_SVCALLACT ((uint32_t)0x00000080) /*!< SVCall is active */
+#define SCB_SHCSR_MONITORACT ((uint32_t)0x00000100) /*!< Monitor is active */
+#define SCB_SHCSR_PENDSVACT ((uint32_t)0x00000400) /*!< PendSV is active */
+#define SCB_SHCSR_SYSTICKACT ((uint32_t)0x00000800) /*!< SysTick is active */
+#define SCB_SHCSR_USGFAULTPENDED ((uint32_t)0x00001000) /*!< Usage Fault is pended */
+#define SCB_SHCSR_MEMFAULTPENDED ((uint32_t)0x00002000) /*!< MemManage is pended */
+#define SCB_SHCSR_BUSFAULTPENDED ((uint32_t)0x00004000) /*!< Bus Fault is pended */
+#define SCB_SHCSR_SVCALLPENDED ((uint32_t)0x00008000) /*!< SVCall is pended */
+#define SCB_SHCSR_MEMFAULTENA ((uint32_t)0x00010000) /*!< MemManage enable */
+#define SCB_SHCSR_BUSFAULTENA ((uint32_t)0x00020000) /*!< Bus Fault enable */
+#define SCB_SHCSR_USGFAULTENA ((uint32_t)0x00040000) /*!< UsageFault enable */
+
+/******************* Bit definition for SCB_CFSR register *******************/
+/*!< MFSR */
+#define SCB_CFSR_IACCVIOL_Pos (0U)
+#define SCB_CFSR_IACCVIOL_Msk (0x1U << SCB_CFSR_IACCVIOL_Pos) /*!< 0x00000001 */
+#define SCB_CFSR_IACCVIOL SCB_CFSR_IACCVIOL_Msk /*!< Instruction access violation */
+#define SCB_CFSR_DACCVIOL_Pos (1U)
+#define SCB_CFSR_DACCVIOL_Msk (0x1U << SCB_CFSR_DACCVIOL_Pos) /*!< 0x00000002 */
+#define SCB_CFSR_DACCVIOL SCB_CFSR_DACCVIOL_Msk /*!< Data access violation */
+#define SCB_CFSR_MUNSTKERR_Pos (3U)
+#define SCB_CFSR_MUNSTKERR_Msk (0x1U << SCB_CFSR_MUNSTKERR_Pos) /*!< 0x00000008 */
+#define SCB_CFSR_MUNSTKERR SCB_CFSR_MUNSTKERR_Msk /*!< Unstacking error */
+#define SCB_CFSR_MSTKERR_Pos (4U)
+#define SCB_CFSR_MSTKERR_Msk (0x1U << SCB_CFSR_MSTKERR_Pos) /*!< 0x00000010 */
+#define SCB_CFSR_MSTKERR SCB_CFSR_MSTKERR_Msk /*!< Stacking error */
+#define SCB_CFSR_MMARVALID_Pos (7U)
+#define SCB_CFSR_MMARVALID_Msk (0x1U << SCB_CFSR_MMARVALID_Pos) /*!< 0x00000080 */
+#define SCB_CFSR_MMARVALID SCB_CFSR_MMARVALID_Msk /*!< Memory Manage Address Register address valid flag */
+/*!< BFSR */
+#define SCB_CFSR_IBUSERR_Pos (8U)
+#define SCB_CFSR_IBUSERR_Msk (0x1U << SCB_CFSR_IBUSERR_Pos) /*!< 0x00000100 */
+#define SCB_CFSR_IBUSERR SCB_CFSR_IBUSERR_Msk /*!< Instruction bus error flag */
+#define SCB_CFSR_PRECISERR_Pos (9U)
+#define SCB_CFSR_PRECISERR_Msk (0x1U << SCB_CFSR_PRECISERR_Pos) /*!< 0x00000200 */
+#define SCB_CFSR_PRECISERR SCB_CFSR_PRECISERR_Msk /*!< Precise data bus error */
+#define SCB_CFSR_IMPRECISERR_Pos (10U)
+#define SCB_CFSR_IMPRECISERR_Msk (0x1U << SCB_CFSR_IMPRECISERR_Pos) /*!< 0x00000400 */
+#define SCB_CFSR_IMPRECISERR SCB_CFSR_IMPRECISERR_Msk /*!< Imprecise data bus error */
+#define SCB_CFSR_UNSTKERR_Pos (11U)
+#define SCB_CFSR_UNSTKERR_Msk (0x1U << SCB_CFSR_UNSTKERR_Pos) /*!< 0x00000800 */
+#define SCB_CFSR_UNSTKERR SCB_CFSR_UNSTKERR_Msk /*!< Unstacking error */
+#define SCB_CFSR_STKERR_Pos (12U)
+#define SCB_CFSR_STKERR_Msk (0x1U << SCB_CFSR_STKERR_Pos) /*!< 0x00001000 */
+#define SCB_CFSR_STKERR SCB_CFSR_STKERR_Msk /*!< Stacking error */
+#define SCB_CFSR_BFARVALID_Pos (15U)
+#define SCB_CFSR_BFARVALID_Msk (0x1U << SCB_CFSR_BFARVALID_Pos) /*!< 0x00008000 */
+#define SCB_CFSR_BFARVALID SCB_CFSR_BFARVALID_Msk /*!< Bus Fault Address Register address valid flag */
+/*!< UFSR */
+#define SCB_CFSR_UNDEFINSTR_Pos (16U)
+#define SCB_CFSR_UNDEFINSTR_Msk (0x1U << SCB_CFSR_UNDEFINSTR_Pos) /*!< 0x00010000 */
+#define SCB_CFSR_UNDEFINSTR SCB_CFSR_UNDEFINSTR_Msk /*!< The processor attempt to execute an undefined instruction */
+#define SCB_CFSR_INVSTATE_Pos (17U)
+#define SCB_CFSR_INVSTATE_Msk (0x1U << SCB_CFSR_INVSTATE_Pos) /*!< 0x00020000 */
+#define SCB_CFSR_INVSTATE SCB_CFSR_INVSTATE_Msk /*!< Invalid combination of EPSR and instruction */
+#define SCB_CFSR_INVPC_Pos (18U)
+#define SCB_CFSR_INVPC_Msk (0x1U << SCB_CFSR_INVPC_Pos) /*!< 0x00040000 */
+#define SCB_CFSR_INVPC SCB_CFSR_INVPC_Msk /*!< Attempt to load EXC_RETURN into pc illegally */
+#define SCB_CFSR_NOCP_Pos (19U)
+#define SCB_CFSR_NOCP_Msk (0x1U << SCB_CFSR_NOCP_Pos) /*!< 0x00080000 */
+#define SCB_CFSR_NOCP SCB_CFSR_NOCP_Msk /*!< Attempt to use a coprocessor instruction */
+#define SCB_CFSR_UNALIGNED_Pos (24U)
+#define SCB_CFSR_UNALIGNED_Msk (0x1U << SCB_CFSR_UNALIGNED_Pos) /*!< 0x01000000 */
+#define SCB_CFSR_UNALIGNED SCB_CFSR_UNALIGNED_Msk /*!< Fault occurs when there is an attempt to make an unaligned memory access */
+#define SCB_CFSR_DIVBYZERO_Pos (25U)
+#define SCB_CFSR_DIVBYZERO_Msk (0x1U << SCB_CFSR_DIVBYZERO_Pos) /*!< 0x02000000 */
+#define SCB_CFSR_DIVBYZERO SCB_CFSR_DIVBYZERO_Msk /*!< Fault occurs when SDIV or DIV instruction is used with a divisor of 0 */
+
+/******************* Bit definition for SCB_HFSR register *******************/
+#define SCB_HFSR_VECTTBL ((uint32_t)0x00000002) /*!< Fault occurs because of vector table read on exception processing */
+#define SCB_HFSR_FORCED ((uint32_t)0x40000000) /*!< Hard Fault activated when a configurable Fault was received and cannot activate */
+#define SCB_HFSR_DEBUGEVT ((uint32_t)0x80000000) /*!< Fault related to debug */
+
+/******************* Bit definition for SCB_DFSR register *******************/
+#define SCB_DFSR_HALTED ((uint32_t)0x00000001) /*!< Halt request flag */
+#define SCB_DFSR_BKPT ((uint32_t)0x00000002) /*!< BKPT flag */
+#define SCB_DFSR_DWTTRAP ((uint32_t)0x00000004) /*!< Data Watchpoint and Trace (DWT) flag */
+#define SCB_DFSR_VCATCH ((uint32_t)0x00000008) /*!< Vector catch flag */
+#define SCB_DFSR_EXTERNAL ((uint32_t)0x00000010) /*!< External debug request flag */
+
+/******************* Bit definition for SCB_MMFAR register ******************/
+#define SCB_MMFAR_ADDRESS_Pos (0U)
+#define SCB_MMFAR_ADDRESS_Msk (0xFFFFFFFFU << SCB_MMFAR_ADDRESS_Pos) /*!< 0xFFFFFFFF */
+#define SCB_MMFAR_ADDRESS SCB_MMFAR_ADDRESS_Msk /*!< Mem Manage fault address field */
+
+/******************* Bit definition for SCB_BFAR register *******************/
+#define SCB_BFAR_ADDRESS_Pos (0U)
+#define SCB_BFAR_ADDRESS_Msk (0xFFFFFFFFU << SCB_BFAR_ADDRESS_Pos) /*!< 0xFFFFFFFF */
+#define SCB_BFAR_ADDRESS SCB_BFAR_ADDRESS_Msk /*!< Bus fault address field */
+
+/******************* Bit definition for SCB_afsr register *******************/
+#define SCB_AFSR_IMPDEF_Pos (0U)
+#define SCB_AFSR_IMPDEF_Msk (0xFFFFFFFFU << SCB_AFSR_IMPDEF_Pos) /*!< 0xFFFFFFFF */
+#define SCB_AFSR_IMPDEF SCB_AFSR_IMPDEF_Msk /*!< Implementation defined */
+
+/******************************************************************************/
+/* */
+/* External Interrupt/Event Controller */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for EXTI_IMR register *******************/
+#define EXTI_IMR_MR0_Pos (0U)
+#define EXTI_IMR_MR0_Msk (0x1U << EXTI_IMR_MR0_Pos) /*!< 0x00000001 */
+#define EXTI_IMR_MR0 EXTI_IMR_MR0_Msk /*!< Interrupt Mask on line 0 */
+#define EXTI_IMR_MR1_Pos (1U)
+#define EXTI_IMR_MR1_Msk (0x1U << EXTI_IMR_MR1_Pos) /*!< 0x00000002 */
+#define EXTI_IMR_MR1 EXTI_IMR_MR1_Msk /*!< Interrupt Mask on line 1 */
+#define EXTI_IMR_MR2_Pos (2U)
+#define EXTI_IMR_MR2_Msk (0x1U << EXTI_IMR_MR2_Pos) /*!< 0x00000004 */
+#define EXTI_IMR_MR2 EXTI_IMR_MR2_Msk /*!< Interrupt Mask on line 2 */
+#define EXTI_IMR_MR3_Pos (3U)
+#define EXTI_IMR_MR3_Msk (0x1U << EXTI_IMR_MR3_Pos) /*!< 0x00000008 */
+#define EXTI_IMR_MR3 EXTI_IMR_MR3_Msk /*!< Interrupt Mask on line 3 */
+#define EXTI_IMR_MR4_Pos (4U)
+#define EXTI_IMR_MR4_Msk (0x1U << EXTI_IMR_MR4_Pos) /*!< 0x00000010 */
+#define EXTI_IMR_MR4 EXTI_IMR_MR4_Msk /*!< Interrupt Mask on line 4 */
+#define EXTI_IMR_MR5_Pos (5U)
+#define EXTI_IMR_MR5_Msk (0x1U << EXTI_IMR_MR5_Pos) /*!< 0x00000020 */
+#define EXTI_IMR_MR5 EXTI_IMR_MR5_Msk /*!< Interrupt Mask on line 5 */
+#define EXTI_IMR_MR6_Pos (6U)
+#define EXTI_IMR_MR6_Msk (0x1U << EXTI_IMR_MR6_Pos) /*!< 0x00000040 */
+#define EXTI_IMR_MR6 EXTI_IMR_MR6_Msk /*!< Interrupt Mask on line 6 */
+#define EXTI_IMR_MR7_Pos (7U)
+#define EXTI_IMR_MR7_Msk (0x1U << EXTI_IMR_MR7_Pos) /*!< 0x00000080 */
+#define EXTI_IMR_MR7 EXTI_IMR_MR7_Msk /*!< Interrupt Mask on line 7 */
+#define EXTI_IMR_MR8_Pos (8U)
+#define EXTI_IMR_MR8_Msk (0x1U << EXTI_IMR_MR8_Pos) /*!< 0x00000100 */
+#define EXTI_IMR_MR8 EXTI_IMR_MR8_Msk /*!< Interrupt Mask on line 8 */
+#define EXTI_IMR_MR9_Pos (9U)
+#define EXTI_IMR_MR9_Msk (0x1U << EXTI_IMR_MR9_Pos) /*!< 0x00000200 */
+#define EXTI_IMR_MR9 EXTI_IMR_MR9_Msk /*!< Interrupt Mask on line 9 */
+#define EXTI_IMR_MR10_Pos (10U)
+#define EXTI_IMR_MR10_Msk (0x1U << EXTI_IMR_MR10_Pos) /*!< 0x00000400 */
+#define EXTI_IMR_MR10 EXTI_IMR_MR10_Msk /*!< Interrupt Mask on line 10 */
+#define EXTI_IMR_MR11_Pos (11U)
+#define EXTI_IMR_MR11_Msk (0x1U << EXTI_IMR_MR11_Pos) /*!< 0x00000800 */
+#define EXTI_IMR_MR11 EXTI_IMR_MR11_Msk /*!< Interrupt Mask on line 11 */
+#define EXTI_IMR_MR12_Pos (12U)
+#define EXTI_IMR_MR12_Msk (0x1U << EXTI_IMR_MR12_Pos) /*!< 0x00001000 */
+#define EXTI_IMR_MR12 EXTI_IMR_MR12_Msk /*!< Interrupt Mask on line 12 */
+#define EXTI_IMR_MR13_Pos (13U)
+#define EXTI_IMR_MR13_Msk (0x1U << EXTI_IMR_MR13_Pos) /*!< 0x00002000 */
+#define EXTI_IMR_MR13 EXTI_IMR_MR13_Msk /*!< Interrupt Mask on line 13 */
+#define EXTI_IMR_MR14_Pos (14U)
+#define EXTI_IMR_MR14_Msk (0x1U << EXTI_IMR_MR14_Pos) /*!< 0x00004000 */
+#define EXTI_IMR_MR14 EXTI_IMR_MR14_Msk /*!< Interrupt Mask on line 14 */
+#define EXTI_IMR_MR15_Pos (15U)
+#define EXTI_IMR_MR15_Msk (0x1U << EXTI_IMR_MR15_Pos) /*!< 0x00008000 */
+#define EXTI_IMR_MR15 EXTI_IMR_MR15_Msk /*!< Interrupt Mask on line 15 */
+#define EXTI_IMR_MR16_Pos (16U)
+#define EXTI_IMR_MR16_Msk (0x1U << EXTI_IMR_MR16_Pos) /*!< 0x00010000 */
+#define EXTI_IMR_MR16 EXTI_IMR_MR16_Msk /*!< Interrupt Mask on line 16 */
+#define EXTI_IMR_MR17_Pos (17U)
+#define EXTI_IMR_MR17_Msk (0x1U << EXTI_IMR_MR17_Pos) /*!< 0x00020000 */
+#define EXTI_IMR_MR17 EXTI_IMR_MR17_Msk /*!< Interrupt Mask on line 17 */
+#define EXTI_IMR_MR18_Pos (18U)
+#define EXTI_IMR_MR18_Msk (0x1U << EXTI_IMR_MR18_Pos) /*!< 0x00040000 */
+#define EXTI_IMR_MR18 EXTI_IMR_MR18_Msk /*!< Interrupt Mask on line 18 */
+#define EXTI_IMR_MR19_Pos (19U)
+#define EXTI_IMR_MR19_Msk (0x1U << EXTI_IMR_MR19_Pos) /*!< 0x00080000 */
+#define EXTI_IMR_MR19 EXTI_IMR_MR19_Msk /*!< Interrupt Mask on line 19 */
+
+/* References Defines */
+#define EXTI_IMR_IM0 EXTI_IMR_MR0
+#define EXTI_IMR_IM1 EXTI_IMR_MR1
+#define EXTI_IMR_IM2 EXTI_IMR_MR2
+#define EXTI_IMR_IM3 EXTI_IMR_MR3
+#define EXTI_IMR_IM4 EXTI_IMR_MR4
+#define EXTI_IMR_IM5 EXTI_IMR_MR5
+#define EXTI_IMR_IM6 EXTI_IMR_MR6
+#define EXTI_IMR_IM7 EXTI_IMR_MR7
+#define EXTI_IMR_IM8 EXTI_IMR_MR8
+#define EXTI_IMR_IM9 EXTI_IMR_MR9
+#define EXTI_IMR_IM10 EXTI_IMR_MR10
+#define EXTI_IMR_IM11 EXTI_IMR_MR11
+#define EXTI_IMR_IM12 EXTI_IMR_MR12
+#define EXTI_IMR_IM13 EXTI_IMR_MR13
+#define EXTI_IMR_IM14 EXTI_IMR_MR14
+#define EXTI_IMR_IM15 EXTI_IMR_MR15
+#define EXTI_IMR_IM16 EXTI_IMR_MR16
+#define EXTI_IMR_IM17 EXTI_IMR_MR17
+#define EXTI_IMR_IM18 EXTI_IMR_MR18
+#define EXTI_IMR_IM19 EXTI_IMR_MR19
+
+/******************* Bit definition for EXTI_EMR register *******************/
+#define EXTI_EMR_MR0_Pos (0U)
+#define EXTI_EMR_MR0_Msk (0x1U << EXTI_EMR_MR0_Pos) /*!< 0x00000001 */
+#define EXTI_EMR_MR0 EXTI_EMR_MR0_Msk /*!< Event Mask on line 0 */
+#define EXTI_EMR_MR1_Pos (1U)
+#define EXTI_EMR_MR1_Msk (0x1U << EXTI_EMR_MR1_Pos) /*!< 0x00000002 */
+#define EXTI_EMR_MR1 EXTI_EMR_MR1_Msk /*!< Event Mask on line 1 */
+#define EXTI_EMR_MR2_Pos (2U)
+#define EXTI_EMR_MR2_Msk (0x1U << EXTI_EMR_MR2_Pos) /*!< 0x00000004 */
+#define EXTI_EMR_MR2 EXTI_EMR_MR2_Msk /*!< Event Mask on line 2 */
+#define EXTI_EMR_MR3_Pos (3U)
+#define EXTI_EMR_MR3_Msk (0x1U << EXTI_EMR_MR3_Pos) /*!< 0x00000008 */
+#define EXTI_EMR_MR3 EXTI_EMR_MR3_Msk /*!< Event Mask on line 3 */
+#define EXTI_EMR_MR4_Pos (4U)
+#define EXTI_EMR_MR4_Msk (0x1U << EXTI_EMR_MR4_Pos) /*!< 0x00000010 */
+#define EXTI_EMR_MR4 EXTI_EMR_MR4_Msk /*!< Event Mask on line 4 */
+#define EXTI_EMR_MR5_Pos (5U)
+#define EXTI_EMR_MR5_Msk (0x1U << EXTI_EMR_MR5_Pos) /*!< 0x00000020 */
+#define EXTI_EMR_MR5 EXTI_EMR_MR5_Msk /*!< Event Mask on line 5 */
+#define EXTI_EMR_MR6_Pos (6U)
+#define EXTI_EMR_MR6_Msk (0x1U << EXTI_EMR_MR6_Pos) /*!< 0x00000040 */
+#define EXTI_EMR_MR6 EXTI_EMR_MR6_Msk /*!< Event Mask on line 6 */
+#define EXTI_EMR_MR7_Pos (7U)
+#define EXTI_EMR_MR7_Msk (0x1U << EXTI_EMR_MR7_Pos) /*!< 0x00000080 */
+#define EXTI_EMR_MR7 EXTI_EMR_MR7_Msk /*!< Event Mask on line 7 */
+#define EXTI_EMR_MR8_Pos (8U)
+#define EXTI_EMR_MR8_Msk (0x1U << EXTI_EMR_MR8_Pos) /*!< 0x00000100 */
+#define EXTI_EMR_MR8 EXTI_EMR_MR8_Msk /*!< Event Mask on line 8 */
+#define EXTI_EMR_MR9_Pos (9U)
+#define EXTI_EMR_MR9_Msk (0x1U << EXTI_EMR_MR9_Pos) /*!< 0x00000200 */
+#define EXTI_EMR_MR9 EXTI_EMR_MR9_Msk /*!< Event Mask on line 9 */
+#define EXTI_EMR_MR10_Pos (10U)
+#define EXTI_EMR_MR10_Msk (0x1U << EXTI_EMR_MR10_Pos) /*!< 0x00000400 */
+#define EXTI_EMR_MR10 EXTI_EMR_MR10_Msk /*!< Event Mask on line 10 */
+#define EXTI_EMR_MR11_Pos (11U)
+#define EXTI_EMR_MR11_Msk (0x1U << EXTI_EMR_MR11_Pos) /*!< 0x00000800 */
+#define EXTI_EMR_MR11 EXTI_EMR_MR11_Msk /*!< Event Mask on line 11 */
+#define EXTI_EMR_MR12_Pos (12U)
+#define EXTI_EMR_MR12_Msk (0x1U << EXTI_EMR_MR12_Pos) /*!< 0x00001000 */
+#define EXTI_EMR_MR12 EXTI_EMR_MR12_Msk /*!< Event Mask on line 12 */
+#define EXTI_EMR_MR13_Pos (13U)
+#define EXTI_EMR_MR13_Msk (0x1U << EXTI_EMR_MR13_Pos) /*!< 0x00002000 */
+#define EXTI_EMR_MR13 EXTI_EMR_MR13_Msk /*!< Event Mask on line 13 */
+#define EXTI_EMR_MR14_Pos (14U)
+#define EXTI_EMR_MR14_Msk (0x1U << EXTI_EMR_MR14_Pos) /*!< 0x00004000 */
+#define EXTI_EMR_MR14 EXTI_EMR_MR14_Msk /*!< Event Mask on line 14 */
+#define EXTI_EMR_MR15_Pos (15U)
+#define EXTI_EMR_MR15_Msk (0x1U << EXTI_EMR_MR15_Pos) /*!< 0x00008000 */
+#define EXTI_EMR_MR15 EXTI_EMR_MR15_Msk /*!< Event Mask on line 15 */
+#define EXTI_EMR_MR16_Pos (16U)
+#define EXTI_EMR_MR16_Msk (0x1U << EXTI_EMR_MR16_Pos) /*!< 0x00010000 */
+#define EXTI_EMR_MR16 EXTI_EMR_MR16_Msk /*!< Event Mask on line 16 */
+#define EXTI_EMR_MR17_Pos (17U)
+#define EXTI_EMR_MR17_Msk (0x1U << EXTI_EMR_MR17_Pos) /*!< 0x00020000 */
+#define EXTI_EMR_MR17 EXTI_EMR_MR17_Msk /*!< Event Mask on line 17 */
+#define EXTI_EMR_MR18_Pos (18U)
+#define EXTI_EMR_MR18_Msk (0x1U << EXTI_EMR_MR18_Pos) /*!< 0x00040000 */
+#define EXTI_EMR_MR18 EXTI_EMR_MR18_Msk /*!< Event Mask on line 18 */
+#define EXTI_EMR_MR19_Pos (19U)
+#define EXTI_EMR_MR19_Msk (0x1U << EXTI_EMR_MR19_Pos) /*!< 0x00080000 */
+#define EXTI_EMR_MR19 EXTI_EMR_MR19_Msk /*!< Event Mask on line 19 */
+
+/* References Defines */
+#define EXTI_EMR_EM0 EXTI_EMR_MR0
+#define EXTI_EMR_EM1 EXTI_EMR_MR1
+#define EXTI_EMR_EM2 EXTI_EMR_MR2
+#define EXTI_EMR_EM3 EXTI_EMR_MR3
+#define EXTI_EMR_EM4 EXTI_EMR_MR4
+#define EXTI_EMR_EM5 EXTI_EMR_MR5
+#define EXTI_EMR_EM6 EXTI_EMR_MR6
+#define EXTI_EMR_EM7 EXTI_EMR_MR7
+#define EXTI_EMR_EM8 EXTI_EMR_MR8
+#define EXTI_EMR_EM9 EXTI_EMR_MR9
+#define EXTI_EMR_EM10 EXTI_EMR_MR10
+#define EXTI_EMR_EM11 EXTI_EMR_MR11
+#define EXTI_EMR_EM12 EXTI_EMR_MR12
+#define EXTI_EMR_EM13 EXTI_EMR_MR13
+#define EXTI_EMR_EM14 EXTI_EMR_MR14
+#define EXTI_EMR_EM15 EXTI_EMR_MR15
+#define EXTI_EMR_EM16 EXTI_EMR_MR16
+#define EXTI_EMR_EM17 EXTI_EMR_MR17
+#define EXTI_EMR_EM18 EXTI_EMR_MR18
+#define EXTI_EMR_EM19 EXTI_EMR_MR19
+
+/****************** Bit definition for EXTI_RTSR register *******************/
+#define EXTI_RTSR_TR0_Pos (0U)
+#define EXTI_RTSR_TR0_Msk (0x1U << EXTI_RTSR_TR0_Pos) /*!< 0x00000001 */
+#define EXTI_RTSR_TR0 EXTI_RTSR_TR0_Msk /*!< Rising trigger event configuration bit of line 0 */
+#define EXTI_RTSR_TR1_Pos (1U)
+#define EXTI_RTSR_TR1_Msk (0x1U << EXTI_RTSR_TR1_Pos) /*!< 0x00000002 */
+#define EXTI_RTSR_TR1 EXTI_RTSR_TR1_Msk /*!< Rising trigger event configuration bit of line 1 */
+#define EXTI_RTSR_TR2_Pos (2U)
+#define EXTI_RTSR_TR2_Msk (0x1U << EXTI_RTSR_TR2_Pos) /*!< 0x00000004 */
+#define EXTI_RTSR_TR2 EXTI_RTSR_TR2_Msk /*!< Rising trigger event configuration bit of line 2 */
+#define EXTI_RTSR_TR3_Pos (3U)
+#define EXTI_RTSR_TR3_Msk (0x1U << EXTI_RTSR_TR3_Pos) /*!< 0x00000008 */
+#define EXTI_RTSR_TR3 EXTI_RTSR_TR3_Msk /*!< Rising trigger event configuration bit of line 3 */
+#define EXTI_RTSR_TR4_Pos (4U)
+#define EXTI_RTSR_TR4_Msk (0x1U << EXTI_RTSR_TR4_Pos) /*!< 0x00000010 */
+#define EXTI_RTSR_TR4 EXTI_RTSR_TR4_Msk /*!< Rising trigger event configuration bit of line 4 */
+#define EXTI_RTSR_TR5_Pos (5U)
+#define EXTI_RTSR_TR5_Msk (0x1U << EXTI_RTSR_TR5_Pos) /*!< 0x00000020 */
+#define EXTI_RTSR_TR5 EXTI_RTSR_TR5_Msk /*!< Rising trigger event configuration bit of line 5 */
+#define EXTI_RTSR_TR6_Pos (6U)
+#define EXTI_RTSR_TR6_Msk (0x1U << EXTI_RTSR_TR6_Pos) /*!< 0x00000040 */
+#define EXTI_RTSR_TR6 EXTI_RTSR_TR6_Msk /*!< Rising trigger event configuration bit of line 6 */
+#define EXTI_RTSR_TR7_Pos (7U)
+#define EXTI_RTSR_TR7_Msk (0x1U << EXTI_RTSR_TR7_Pos) /*!< 0x00000080 */
+#define EXTI_RTSR_TR7 EXTI_RTSR_TR7_Msk /*!< Rising trigger event configuration bit of line 7 */
+#define EXTI_RTSR_TR8_Pos (8U)
+#define EXTI_RTSR_TR8_Msk (0x1U << EXTI_RTSR_TR8_Pos) /*!< 0x00000100 */
+#define EXTI_RTSR_TR8 EXTI_RTSR_TR8_Msk /*!< Rising trigger event configuration bit of line 8 */
+#define EXTI_RTSR_TR9_Pos (9U)
+#define EXTI_RTSR_TR9_Msk (0x1U << EXTI_RTSR_TR9_Pos) /*!< 0x00000200 */
+#define EXTI_RTSR_TR9 EXTI_RTSR_TR9_Msk /*!< Rising trigger event configuration bit of line 9 */
+#define EXTI_RTSR_TR10_Pos (10U)
+#define EXTI_RTSR_TR10_Msk (0x1U << EXTI_RTSR_TR10_Pos) /*!< 0x00000400 */
+#define EXTI_RTSR_TR10 EXTI_RTSR_TR10_Msk /*!< Rising trigger event configuration bit of line 10 */
+#define EXTI_RTSR_TR11_Pos (11U)
+#define EXTI_RTSR_TR11_Msk (0x1U << EXTI_RTSR_TR11_Pos) /*!< 0x00000800 */
+#define EXTI_RTSR_TR11 EXTI_RTSR_TR11_Msk /*!< Rising trigger event configuration bit of line 11 */
+#define EXTI_RTSR_TR12_Pos (12U)
+#define EXTI_RTSR_TR12_Msk (0x1U << EXTI_RTSR_TR12_Pos) /*!< 0x00001000 */
+#define EXTI_RTSR_TR12 EXTI_RTSR_TR12_Msk /*!< Rising trigger event configuration bit of line 12 */
+#define EXTI_RTSR_TR13_Pos (13U)
+#define EXTI_RTSR_TR13_Msk (0x1U << EXTI_RTSR_TR13_Pos) /*!< 0x00002000 */
+#define EXTI_RTSR_TR13 EXTI_RTSR_TR13_Msk /*!< Rising trigger event configuration bit of line 13 */
+#define EXTI_RTSR_TR14_Pos (14U)
+#define EXTI_RTSR_TR14_Msk (0x1U << EXTI_RTSR_TR14_Pos) /*!< 0x00004000 */
+#define EXTI_RTSR_TR14 EXTI_RTSR_TR14_Msk /*!< Rising trigger event configuration bit of line 14 */
+#define EXTI_RTSR_TR15_Pos (15U)
+#define EXTI_RTSR_TR15_Msk (0x1U << EXTI_RTSR_TR15_Pos) /*!< 0x00008000 */
+#define EXTI_RTSR_TR15 EXTI_RTSR_TR15_Msk /*!< Rising trigger event configuration bit of line 15 */
+#define EXTI_RTSR_TR16_Pos (16U)
+#define EXTI_RTSR_TR16_Msk (0x1U << EXTI_RTSR_TR16_Pos) /*!< 0x00010000 */
+#define EXTI_RTSR_TR16 EXTI_RTSR_TR16_Msk /*!< Rising trigger event configuration bit of line 16 */
+#define EXTI_RTSR_TR17_Pos (17U)
+#define EXTI_RTSR_TR17_Msk (0x1U << EXTI_RTSR_TR17_Pos) /*!< 0x00020000 */
+#define EXTI_RTSR_TR17 EXTI_RTSR_TR17_Msk /*!< Rising trigger event configuration bit of line 17 */
+#define EXTI_RTSR_TR18_Pos (18U)
+#define EXTI_RTSR_TR18_Msk (0x1U << EXTI_RTSR_TR18_Pos) /*!< 0x00040000 */
+#define EXTI_RTSR_TR18 EXTI_RTSR_TR18_Msk /*!< Rising trigger event configuration bit of line 18 */
+#define EXTI_RTSR_TR19_Pos (19U)
+#define EXTI_RTSR_TR19_Msk (0x1U << EXTI_RTSR_TR19_Pos) /*!< 0x00080000 */
+#define EXTI_RTSR_TR19 EXTI_RTSR_TR19_Msk /*!< Rising trigger event configuration bit of line 19 */
+
+/* References Defines */
+#define EXTI_RTSR_RT0 EXTI_RTSR_TR0
+#define EXTI_RTSR_RT1 EXTI_RTSR_TR1
+#define EXTI_RTSR_RT2 EXTI_RTSR_TR2
+#define EXTI_RTSR_RT3 EXTI_RTSR_TR3
+#define EXTI_RTSR_RT4 EXTI_RTSR_TR4
+#define EXTI_RTSR_RT5 EXTI_RTSR_TR5
+#define EXTI_RTSR_RT6 EXTI_RTSR_TR6
+#define EXTI_RTSR_RT7 EXTI_RTSR_TR7
+#define EXTI_RTSR_RT8 EXTI_RTSR_TR8
+#define EXTI_RTSR_RT9 EXTI_RTSR_TR9
+#define EXTI_RTSR_RT10 EXTI_RTSR_TR10
+#define EXTI_RTSR_RT11 EXTI_RTSR_TR11
+#define EXTI_RTSR_RT12 EXTI_RTSR_TR12
+#define EXTI_RTSR_RT13 EXTI_RTSR_TR13
+#define EXTI_RTSR_RT14 EXTI_RTSR_TR14
+#define EXTI_RTSR_RT15 EXTI_RTSR_TR15
+#define EXTI_RTSR_RT16 EXTI_RTSR_TR16
+#define EXTI_RTSR_RT17 EXTI_RTSR_TR17
+#define EXTI_RTSR_RT18 EXTI_RTSR_TR18
+#define EXTI_RTSR_RT19 EXTI_RTSR_TR19
+
+/****************** Bit definition for EXTI_FTSR register *******************/
+#define EXTI_FTSR_TR0_Pos (0U)
+#define EXTI_FTSR_TR0_Msk (0x1U << EXTI_FTSR_TR0_Pos) /*!< 0x00000001 */
+#define EXTI_FTSR_TR0 EXTI_FTSR_TR0_Msk /*!< Falling trigger event configuration bit of line 0 */
+#define EXTI_FTSR_TR1_Pos (1U)
+#define EXTI_FTSR_TR1_Msk (0x1U << EXTI_FTSR_TR1_Pos) /*!< 0x00000002 */
+#define EXTI_FTSR_TR1 EXTI_FTSR_TR1_Msk /*!< Falling trigger event configuration bit of line 1 */
+#define EXTI_FTSR_TR2_Pos (2U)
+#define EXTI_FTSR_TR2_Msk (0x1U << EXTI_FTSR_TR2_Pos) /*!< 0x00000004 */
+#define EXTI_FTSR_TR2 EXTI_FTSR_TR2_Msk /*!< Falling trigger event configuration bit of line 2 */
+#define EXTI_FTSR_TR3_Pos (3U)
+#define EXTI_FTSR_TR3_Msk (0x1U << EXTI_FTSR_TR3_Pos) /*!< 0x00000008 */
+#define EXTI_FTSR_TR3 EXTI_FTSR_TR3_Msk /*!< Falling trigger event configuration bit of line 3 */
+#define EXTI_FTSR_TR4_Pos (4U)
+#define EXTI_FTSR_TR4_Msk (0x1U << EXTI_FTSR_TR4_Pos) /*!< 0x00000010 */
+#define EXTI_FTSR_TR4 EXTI_FTSR_TR4_Msk /*!< Falling trigger event configuration bit of line 4 */
+#define EXTI_FTSR_TR5_Pos (5U)
+#define EXTI_FTSR_TR5_Msk (0x1U << EXTI_FTSR_TR5_Pos) /*!< 0x00000020 */
+#define EXTI_FTSR_TR5 EXTI_FTSR_TR5_Msk /*!< Falling trigger event configuration bit of line 5 */
+#define EXTI_FTSR_TR6_Pos (6U)
+#define EXTI_FTSR_TR6_Msk (0x1U << EXTI_FTSR_TR6_Pos) /*!< 0x00000040 */
+#define EXTI_FTSR_TR6 EXTI_FTSR_TR6_Msk /*!< Falling trigger event configuration bit of line 6 */
+#define EXTI_FTSR_TR7_Pos (7U)
+#define EXTI_FTSR_TR7_Msk (0x1U << EXTI_FTSR_TR7_Pos) /*!< 0x00000080 */
+#define EXTI_FTSR_TR7 EXTI_FTSR_TR7_Msk /*!< Falling trigger event configuration bit of line 7 */
+#define EXTI_FTSR_TR8_Pos (8U)
+#define EXTI_FTSR_TR8_Msk (0x1U << EXTI_FTSR_TR8_Pos) /*!< 0x00000100 */
+#define EXTI_FTSR_TR8 EXTI_FTSR_TR8_Msk /*!< Falling trigger event configuration bit of line 8 */
+#define EXTI_FTSR_TR9_Pos (9U)
+#define EXTI_FTSR_TR9_Msk (0x1U << EXTI_FTSR_TR9_Pos) /*!< 0x00000200 */
+#define EXTI_FTSR_TR9 EXTI_FTSR_TR9_Msk /*!< Falling trigger event configuration bit of line 9 */
+#define EXTI_FTSR_TR10_Pos (10U)
+#define EXTI_FTSR_TR10_Msk (0x1U << EXTI_FTSR_TR10_Pos) /*!< 0x00000400 */
+#define EXTI_FTSR_TR10 EXTI_FTSR_TR10_Msk /*!< Falling trigger event configuration bit of line 10 */
+#define EXTI_FTSR_TR11_Pos (11U)
+#define EXTI_FTSR_TR11_Msk (0x1U << EXTI_FTSR_TR11_Pos) /*!< 0x00000800 */
+#define EXTI_FTSR_TR11 EXTI_FTSR_TR11_Msk /*!< Falling trigger event configuration bit of line 11 */
+#define EXTI_FTSR_TR12_Pos (12U)
+#define EXTI_FTSR_TR12_Msk (0x1U << EXTI_FTSR_TR12_Pos) /*!< 0x00001000 */
+#define EXTI_FTSR_TR12 EXTI_FTSR_TR12_Msk /*!< Falling trigger event configuration bit of line 12 */
+#define EXTI_FTSR_TR13_Pos (13U)
+#define EXTI_FTSR_TR13_Msk (0x1U << EXTI_FTSR_TR13_Pos) /*!< 0x00002000 */
+#define EXTI_FTSR_TR13 EXTI_FTSR_TR13_Msk /*!< Falling trigger event configuration bit of line 13 */
+#define EXTI_FTSR_TR14_Pos (14U)
+#define EXTI_FTSR_TR14_Msk (0x1U << EXTI_FTSR_TR14_Pos) /*!< 0x00004000 */
+#define EXTI_FTSR_TR14 EXTI_FTSR_TR14_Msk /*!< Falling trigger event configuration bit of line 14 */
+#define EXTI_FTSR_TR15_Pos (15U)
+#define EXTI_FTSR_TR15_Msk (0x1U << EXTI_FTSR_TR15_Pos) /*!< 0x00008000 */
+#define EXTI_FTSR_TR15 EXTI_FTSR_TR15_Msk /*!< Falling trigger event configuration bit of line 15 */
+#define EXTI_FTSR_TR16_Pos (16U)
+#define EXTI_FTSR_TR16_Msk (0x1U << EXTI_FTSR_TR16_Pos) /*!< 0x00010000 */
+#define EXTI_FTSR_TR16 EXTI_FTSR_TR16_Msk /*!< Falling trigger event configuration bit of line 16 */
+#define EXTI_FTSR_TR17_Pos (17U)
+#define EXTI_FTSR_TR17_Msk (0x1U << EXTI_FTSR_TR17_Pos) /*!< 0x00020000 */
+#define EXTI_FTSR_TR17 EXTI_FTSR_TR17_Msk /*!< Falling trigger event configuration bit of line 17 */
+#define EXTI_FTSR_TR18_Pos (18U)
+#define EXTI_FTSR_TR18_Msk (0x1U << EXTI_FTSR_TR18_Pos) /*!< 0x00040000 */
+#define EXTI_FTSR_TR18 EXTI_FTSR_TR18_Msk /*!< Falling trigger event configuration bit of line 18 */
+#define EXTI_FTSR_TR19_Pos (19U)
+#define EXTI_FTSR_TR19_Msk (0x1U << EXTI_FTSR_TR19_Pos) /*!< 0x00080000 */
+#define EXTI_FTSR_TR19 EXTI_FTSR_TR19_Msk /*!< Falling trigger event configuration bit of line 19 */
+
+/* References Defines */
+#define EXTI_FTSR_FT0 EXTI_FTSR_TR0
+#define EXTI_FTSR_FT1 EXTI_FTSR_TR1
+#define EXTI_FTSR_FT2 EXTI_FTSR_TR2
+#define EXTI_FTSR_FT3 EXTI_FTSR_TR3
+#define EXTI_FTSR_FT4 EXTI_FTSR_TR4
+#define EXTI_FTSR_FT5 EXTI_FTSR_TR5
+#define EXTI_FTSR_FT6 EXTI_FTSR_TR6
+#define EXTI_FTSR_FT7 EXTI_FTSR_TR7
+#define EXTI_FTSR_FT8 EXTI_FTSR_TR8
+#define EXTI_FTSR_FT9 EXTI_FTSR_TR9
+#define EXTI_FTSR_FT10 EXTI_FTSR_TR10
+#define EXTI_FTSR_FT11 EXTI_FTSR_TR11
+#define EXTI_FTSR_FT12 EXTI_FTSR_TR12
+#define EXTI_FTSR_FT13 EXTI_FTSR_TR13
+#define EXTI_FTSR_FT14 EXTI_FTSR_TR14
+#define EXTI_FTSR_FT15 EXTI_FTSR_TR15
+#define EXTI_FTSR_FT16 EXTI_FTSR_TR16
+#define EXTI_FTSR_FT17 EXTI_FTSR_TR17
+#define EXTI_FTSR_FT18 EXTI_FTSR_TR18
+#define EXTI_FTSR_FT19 EXTI_FTSR_TR19
+
+/****************** Bit definition for EXTI_SWIER register ******************/
+#define EXTI_SWIER_SWIER0_Pos (0U)
+#define EXTI_SWIER_SWIER0_Msk (0x1U << EXTI_SWIER_SWIER0_Pos) /*!< 0x00000001 */
+#define EXTI_SWIER_SWIER0 EXTI_SWIER_SWIER0_Msk /*!< Software Interrupt on line 0 */
+#define EXTI_SWIER_SWIER1_Pos (1U)
+#define EXTI_SWIER_SWIER1_Msk (0x1U << EXTI_SWIER_SWIER1_Pos) /*!< 0x00000002 */
+#define EXTI_SWIER_SWIER1 EXTI_SWIER_SWIER1_Msk /*!< Software Interrupt on line 1 */
+#define EXTI_SWIER_SWIER2_Pos (2U)
+#define EXTI_SWIER_SWIER2_Msk (0x1U << EXTI_SWIER_SWIER2_Pos) /*!< 0x00000004 */
+#define EXTI_SWIER_SWIER2 EXTI_SWIER_SWIER2_Msk /*!< Software Interrupt on line 2 */
+#define EXTI_SWIER_SWIER3_Pos (3U)
+#define EXTI_SWIER_SWIER3_Msk (0x1U << EXTI_SWIER_SWIER3_Pos) /*!< 0x00000008 */
+#define EXTI_SWIER_SWIER3 EXTI_SWIER_SWIER3_Msk /*!< Software Interrupt on line 3 */
+#define EXTI_SWIER_SWIER4_Pos (4U)
+#define EXTI_SWIER_SWIER4_Msk (0x1U << EXTI_SWIER_SWIER4_Pos) /*!< 0x00000010 */
+#define EXTI_SWIER_SWIER4 EXTI_SWIER_SWIER4_Msk /*!< Software Interrupt on line 4 */
+#define EXTI_SWIER_SWIER5_Pos (5U)
+#define EXTI_SWIER_SWIER5_Msk (0x1U << EXTI_SWIER_SWIER5_Pos) /*!< 0x00000020 */
+#define EXTI_SWIER_SWIER5 EXTI_SWIER_SWIER5_Msk /*!< Software Interrupt on line 5 */
+#define EXTI_SWIER_SWIER6_Pos (6U)
+#define EXTI_SWIER_SWIER6_Msk (0x1U << EXTI_SWIER_SWIER6_Pos) /*!< 0x00000040 */
+#define EXTI_SWIER_SWIER6 EXTI_SWIER_SWIER6_Msk /*!< Software Interrupt on line 6 */
+#define EXTI_SWIER_SWIER7_Pos (7U)
+#define EXTI_SWIER_SWIER7_Msk (0x1U << EXTI_SWIER_SWIER7_Pos) /*!< 0x00000080 */
+#define EXTI_SWIER_SWIER7 EXTI_SWIER_SWIER7_Msk /*!< Software Interrupt on line 7 */
+#define EXTI_SWIER_SWIER8_Pos (8U)
+#define EXTI_SWIER_SWIER8_Msk (0x1U << EXTI_SWIER_SWIER8_Pos) /*!< 0x00000100 */
+#define EXTI_SWIER_SWIER8 EXTI_SWIER_SWIER8_Msk /*!< Software Interrupt on line 8 */
+#define EXTI_SWIER_SWIER9_Pos (9U)
+#define EXTI_SWIER_SWIER9_Msk (0x1U << EXTI_SWIER_SWIER9_Pos) /*!< 0x00000200 */
+#define EXTI_SWIER_SWIER9 EXTI_SWIER_SWIER9_Msk /*!< Software Interrupt on line 9 */
+#define EXTI_SWIER_SWIER10_Pos (10U)
+#define EXTI_SWIER_SWIER10_Msk (0x1U << EXTI_SWIER_SWIER10_Pos) /*!< 0x00000400 */
+#define EXTI_SWIER_SWIER10 EXTI_SWIER_SWIER10_Msk /*!< Software Interrupt on line 10 */
+#define EXTI_SWIER_SWIER11_Pos (11U)
+#define EXTI_SWIER_SWIER11_Msk (0x1U << EXTI_SWIER_SWIER11_Pos) /*!< 0x00000800 */
+#define EXTI_SWIER_SWIER11 EXTI_SWIER_SWIER11_Msk /*!< Software Interrupt on line 11 */
+#define EXTI_SWIER_SWIER12_Pos (12U)
+#define EXTI_SWIER_SWIER12_Msk (0x1U << EXTI_SWIER_SWIER12_Pos) /*!< 0x00001000 */
+#define EXTI_SWIER_SWIER12 EXTI_SWIER_SWIER12_Msk /*!< Software Interrupt on line 12 */
+#define EXTI_SWIER_SWIER13_Pos (13U)
+#define EXTI_SWIER_SWIER13_Msk (0x1U << EXTI_SWIER_SWIER13_Pos) /*!< 0x00002000 */
+#define EXTI_SWIER_SWIER13 EXTI_SWIER_SWIER13_Msk /*!< Software Interrupt on line 13 */
+#define EXTI_SWIER_SWIER14_Pos (14U)
+#define EXTI_SWIER_SWIER14_Msk (0x1U << EXTI_SWIER_SWIER14_Pos) /*!< 0x00004000 */
+#define EXTI_SWIER_SWIER14 EXTI_SWIER_SWIER14_Msk /*!< Software Interrupt on line 14 */
+#define EXTI_SWIER_SWIER15_Pos (15U)
+#define EXTI_SWIER_SWIER15_Msk (0x1U << EXTI_SWIER_SWIER15_Pos) /*!< 0x00008000 */
+#define EXTI_SWIER_SWIER15 EXTI_SWIER_SWIER15_Msk /*!< Software Interrupt on line 15 */
+#define EXTI_SWIER_SWIER16_Pos (16U)
+#define EXTI_SWIER_SWIER16_Msk (0x1U << EXTI_SWIER_SWIER16_Pos) /*!< 0x00010000 */
+#define EXTI_SWIER_SWIER16 EXTI_SWIER_SWIER16_Msk /*!< Software Interrupt on line 16 */
+#define EXTI_SWIER_SWIER17_Pos (17U)
+#define EXTI_SWIER_SWIER17_Msk (0x1U << EXTI_SWIER_SWIER17_Pos) /*!< 0x00020000 */
+#define EXTI_SWIER_SWIER17 EXTI_SWIER_SWIER17_Msk /*!< Software Interrupt on line 17 */
+#define EXTI_SWIER_SWIER18_Pos (18U)
+#define EXTI_SWIER_SWIER18_Msk (0x1U << EXTI_SWIER_SWIER18_Pos) /*!< 0x00040000 */
+#define EXTI_SWIER_SWIER18 EXTI_SWIER_SWIER18_Msk /*!< Software Interrupt on line 18 */
+#define EXTI_SWIER_SWIER19_Pos (19U)
+#define EXTI_SWIER_SWIER19_Msk (0x1U << EXTI_SWIER_SWIER19_Pos) /*!< 0x00080000 */
+#define EXTI_SWIER_SWIER19 EXTI_SWIER_SWIER19_Msk /*!< Software Interrupt on line 19 */
+
+/* References Defines */
+#define EXTI_SWIER_SWI0 EXTI_SWIER_SWIER0
+#define EXTI_SWIER_SWI1 EXTI_SWIER_SWIER1
+#define EXTI_SWIER_SWI2 EXTI_SWIER_SWIER2
+#define EXTI_SWIER_SWI3 EXTI_SWIER_SWIER3
+#define EXTI_SWIER_SWI4 EXTI_SWIER_SWIER4
+#define EXTI_SWIER_SWI5 EXTI_SWIER_SWIER5
+#define EXTI_SWIER_SWI6 EXTI_SWIER_SWIER6
+#define EXTI_SWIER_SWI7 EXTI_SWIER_SWIER7
+#define EXTI_SWIER_SWI8 EXTI_SWIER_SWIER8
+#define EXTI_SWIER_SWI9 EXTI_SWIER_SWIER9
+#define EXTI_SWIER_SWI10 EXTI_SWIER_SWIER10
+#define EXTI_SWIER_SWI11 EXTI_SWIER_SWIER11
+#define EXTI_SWIER_SWI12 EXTI_SWIER_SWIER12
+#define EXTI_SWIER_SWI13 EXTI_SWIER_SWIER13
+#define EXTI_SWIER_SWI14 EXTI_SWIER_SWIER14
+#define EXTI_SWIER_SWI15 EXTI_SWIER_SWIER15
+#define EXTI_SWIER_SWI16 EXTI_SWIER_SWIER16
+#define EXTI_SWIER_SWI17 EXTI_SWIER_SWIER17
+#define EXTI_SWIER_SWI18 EXTI_SWIER_SWIER18
+#define EXTI_SWIER_SWI19 EXTI_SWIER_SWIER19
+
+/******************* Bit definition for EXTI_PR register ********************/
+#define EXTI_PR_PR0_Pos (0U)
+#define EXTI_PR_PR0_Msk (0x1U << EXTI_PR_PR0_Pos) /*!< 0x00000001 */
+#define EXTI_PR_PR0 EXTI_PR_PR0_Msk /*!< Pending bit for line 0 */
+#define EXTI_PR_PR1_Pos (1U)
+#define EXTI_PR_PR1_Msk (0x1U << EXTI_PR_PR1_Pos) /*!< 0x00000002 */
+#define EXTI_PR_PR1 EXTI_PR_PR1_Msk /*!< Pending bit for line 1 */
+#define EXTI_PR_PR2_Pos (2U)
+#define EXTI_PR_PR2_Msk (0x1U << EXTI_PR_PR2_Pos) /*!< 0x00000004 */
+#define EXTI_PR_PR2 EXTI_PR_PR2_Msk /*!< Pending bit for line 2 */
+#define EXTI_PR_PR3_Pos (3U)
+#define EXTI_PR_PR3_Msk (0x1U << EXTI_PR_PR3_Pos) /*!< 0x00000008 */
+#define EXTI_PR_PR3 EXTI_PR_PR3_Msk /*!< Pending bit for line 3 */
+#define EXTI_PR_PR4_Pos (4U)
+#define EXTI_PR_PR4_Msk (0x1U << EXTI_PR_PR4_Pos) /*!< 0x00000010 */
+#define EXTI_PR_PR4 EXTI_PR_PR4_Msk /*!< Pending bit for line 4 */
+#define EXTI_PR_PR5_Pos (5U)
+#define EXTI_PR_PR5_Msk (0x1U << EXTI_PR_PR5_Pos) /*!< 0x00000020 */
+#define EXTI_PR_PR5 EXTI_PR_PR5_Msk /*!< Pending bit for line 5 */
+#define EXTI_PR_PR6_Pos (6U)
+#define EXTI_PR_PR6_Msk (0x1U << EXTI_PR_PR6_Pos) /*!< 0x00000040 */
+#define EXTI_PR_PR6 EXTI_PR_PR6_Msk /*!< Pending bit for line 6 */
+#define EXTI_PR_PR7_Pos (7U)
+#define EXTI_PR_PR7_Msk (0x1U << EXTI_PR_PR7_Pos) /*!< 0x00000080 */
+#define EXTI_PR_PR7 EXTI_PR_PR7_Msk /*!< Pending bit for line 7 */
+#define EXTI_PR_PR8_Pos (8U)
+#define EXTI_PR_PR8_Msk (0x1U << EXTI_PR_PR8_Pos) /*!< 0x00000100 */
+#define EXTI_PR_PR8 EXTI_PR_PR8_Msk /*!< Pending bit for line 8 */
+#define EXTI_PR_PR9_Pos (9U)
+#define EXTI_PR_PR9_Msk (0x1U << EXTI_PR_PR9_Pos) /*!< 0x00000200 */
+#define EXTI_PR_PR9 EXTI_PR_PR9_Msk /*!< Pending bit for line 9 */
+#define EXTI_PR_PR10_Pos (10U)
+#define EXTI_PR_PR10_Msk (0x1U << EXTI_PR_PR10_Pos) /*!< 0x00000400 */
+#define EXTI_PR_PR10 EXTI_PR_PR10_Msk /*!< Pending bit for line 10 */
+#define EXTI_PR_PR11_Pos (11U)
+#define EXTI_PR_PR11_Msk (0x1U << EXTI_PR_PR11_Pos) /*!< 0x00000800 */
+#define EXTI_PR_PR11 EXTI_PR_PR11_Msk /*!< Pending bit for line 11 */
+#define EXTI_PR_PR12_Pos (12U)
+#define EXTI_PR_PR12_Msk (0x1U << EXTI_PR_PR12_Pos) /*!< 0x00001000 */
+#define EXTI_PR_PR12 EXTI_PR_PR12_Msk /*!< Pending bit for line 12 */
+#define EXTI_PR_PR13_Pos (13U)
+#define EXTI_PR_PR13_Msk (0x1U << EXTI_PR_PR13_Pos) /*!< 0x00002000 */
+#define EXTI_PR_PR13 EXTI_PR_PR13_Msk /*!< Pending bit for line 13 */
+#define EXTI_PR_PR14_Pos (14U)
+#define EXTI_PR_PR14_Msk (0x1U << EXTI_PR_PR14_Pos) /*!< 0x00004000 */
+#define EXTI_PR_PR14 EXTI_PR_PR14_Msk /*!< Pending bit for line 14 */
+#define EXTI_PR_PR15_Pos (15U)
+#define EXTI_PR_PR15_Msk (0x1U << EXTI_PR_PR15_Pos) /*!< 0x00008000 */
+#define EXTI_PR_PR15 EXTI_PR_PR15_Msk /*!< Pending bit for line 15 */
+#define EXTI_PR_PR16_Pos (16U)
+#define EXTI_PR_PR16_Msk (0x1U << EXTI_PR_PR16_Pos) /*!< 0x00010000 */
+#define EXTI_PR_PR16 EXTI_PR_PR16_Msk /*!< Pending bit for line 16 */
+#define EXTI_PR_PR17_Pos (17U)
+#define EXTI_PR_PR17_Msk (0x1U << EXTI_PR_PR17_Pos) /*!< 0x00020000 */
+#define EXTI_PR_PR17 EXTI_PR_PR17_Msk /*!< Pending bit for line 17 */
+#define EXTI_PR_PR18_Pos (18U)
+#define EXTI_PR_PR18_Msk (0x1U << EXTI_PR_PR18_Pos) /*!< 0x00040000 */
+#define EXTI_PR_PR18 EXTI_PR_PR18_Msk /*!< Pending bit for line 18 */
+#define EXTI_PR_PR19_Pos (19U)
+#define EXTI_PR_PR19_Msk (0x1U << EXTI_PR_PR19_Pos) /*!< 0x00080000 */
+#define EXTI_PR_PR19 EXTI_PR_PR19_Msk /*!< Pending bit for line 19 */
+
+/* References Defines */
+#define EXTI_PR_PIF0 EXTI_PR_PR0
+#define EXTI_PR_PIF1 EXTI_PR_PR1
+#define EXTI_PR_PIF2 EXTI_PR_PR2
+#define EXTI_PR_PIF3 EXTI_PR_PR3
+#define EXTI_PR_PIF4 EXTI_PR_PR4
+#define EXTI_PR_PIF5 EXTI_PR_PR5
+#define EXTI_PR_PIF6 EXTI_PR_PR6
+#define EXTI_PR_PIF7 EXTI_PR_PR7
+#define EXTI_PR_PIF8 EXTI_PR_PR8
+#define EXTI_PR_PIF9 EXTI_PR_PR9
+#define EXTI_PR_PIF10 EXTI_PR_PR10
+#define EXTI_PR_PIF11 EXTI_PR_PR11
+#define EXTI_PR_PIF12 EXTI_PR_PR12
+#define EXTI_PR_PIF13 EXTI_PR_PR13
+#define EXTI_PR_PIF14 EXTI_PR_PR14
+#define EXTI_PR_PIF15 EXTI_PR_PR15
+#define EXTI_PR_PIF16 EXTI_PR_PR16
+#define EXTI_PR_PIF17 EXTI_PR_PR17
+#define EXTI_PR_PIF18 EXTI_PR_PR18
+#define EXTI_PR_PIF19 EXTI_PR_PR19
+
+/******************************************************************************/
+/* */
+/* DMA Controller */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for DMA_ISR register ********************/
+#define DMA_ISR_GIF1_Pos (0U)
+#define DMA_ISR_GIF1_Msk (0x1U << DMA_ISR_GIF1_Pos) /*!< 0x00000001 */
+#define DMA_ISR_GIF1 DMA_ISR_GIF1_Msk /*!< Channel 1 Global interrupt flag */
+#define DMA_ISR_TCIF1_Pos (1U)
+#define DMA_ISR_TCIF1_Msk (0x1U << DMA_ISR_TCIF1_Pos) /*!< 0x00000002 */
+#define DMA_ISR_TCIF1 DMA_ISR_TCIF1_Msk /*!< Channel 1 Transfer Complete flag */
+#define DMA_ISR_HTIF1_Pos (2U)
+#define DMA_ISR_HTIF1_Msk (0x1U << DMA_ISR_HTIF1_Pos) /*!< 0x00000004 */
+#define DMA_ISR_HTIF1 DMA_ISR_HTIF1_Msk /*!< Channel 1 Half Transfer flag */
+#define DMA_ISR_TEIF1_Pos (3U)
+#define DMA_ISR_TEIF1_Msk (0x1U << DMA_ISR_TEIF1_Pos) /*!< 0x00000008 */
+#define DMA_ISR_TEIF1 DMA_ISR_TEIF1_Msk /*!< Channel 1 Transfer Error flag */
+#define DMA_ISR_GIF2_Pos (4U)
+#define DMA_ISR_GIF2_Msk (0x1U << DMA_ISR_GIF2_Pos) /*!< 0x00000010 */
+#define DMA_ISR_GIF2 DMA_ISR_GIF2_Msk /*!< Channel 2 Global interrupt flag */
+#define DMA_ISR_TCIF2_Pos (5U)
+#define DMA_ISR_TCIF2_Msk (0x1U << DMA_ISR_TCIF2_Pos) /*!< 0x00000020 */
+#define DMA_ISR_TCIF2 DMA_ISR_TCIF2_Msk /*!< Channel 2 Transfer Complete flag */
+#define DMA_ISR_HTIF2_Pos (6U)
+#define DMA_ISR_HTIF2_Msk (0x1U << DMA_ISR_HTIF2_Pos) /*!< 0x00000040 */
+#define DMA_ISR_HTIF2 DMA_ISR_HTIF2_Msk /*!< Channel 2 Half Transfer flag */
+#define DMA_ISR_TEIF2_Pos (7U)
+#define DMA_ISR_TEIF2_Msk (0x1U << DMA_ISR_TEIF2_Pos) /*!< 0x00000080 */
+#define DMA_ISR_TEIF2 DMA_ISR_TEIF2_Msk /*!< Channel 2 Transfer Error flag */
+#define DMA_ISR_GIF3_Pos (8U)
+#define DMA_ISR_GIF3_Msk (0x1U << DMA_ISR_GIF3_Pos) /*!< 0x00000100 */
+#define DMA_ISR_GIF3 DMA_ISR_GIF3_Msk /*!< Channel 3 Global interrupt flag */
+#define DMA_ISR_TCIF3_Pos (9U)
+#define DMA_ISR_TCIF3_Msk (0x1U << DMA_ISR_TCIF3_Pos) /*!< 0x00000200 */
+#define DMA_ISR_TCIF3 DMA_ISR_TCIF3_Msk /*!< Channel 3 Transfer Complete flag */
+#define DMA_ISR_HTIF3_Pos (10U)
+#define DMA_ISR_HTIF3_Msk (0x1U << DMA_ISR_HTIF3_Pos) /*!< 0x00000400 */
+#define DMA_ISR_HTIF3 DMA_ISR_HTIF3_Msk /*!< Channel 3 Half Transfer flag */
+#define DMA_ISR_TEIF3_Pos (11U)
+#define DMA_ISR_TEIF3_Msk (0x1U << DMA_ISR_TEIF3_Pos) /*!< 0x00000800 */
+#define DMA_ISR_TEIF3 DMA_ISR_TEIF3_Msk /*!< Channel 3 Transfer Error flag */
+#define DMA_ISR_GIF4_Pos (12U)
+#define DMA_ISR_GIF4_Msk (0x1U << DMA_ISR_GIF4_Pos) /*!< 0x00001000 */
+#define DMA_ISR_GIF4 DMA_ISR_GIF4_Msk /*!< Channel 4 Global interrupt flag */
+#define DMA_ISR_TCIF4_Pos (13U)
+#define DMA_ISR_TCIF4_Msk (0x1U << DMA_ISR_TCIF4_Pos) /*!< 0x00002000 */
+#define DMA_ISR_TCIF4 DMA_ISR_TCIF4_Msk /*!< Channel 4 Transfer Complete flag */
+#define DMA_ISR_HTIF4_Pos (14U)
+#define DMA_ISR_HTIF4_Msk (0x1U << DMA_ISR_HTIF4_Pos) /*!< 0x00004000 */
+#define DMA_ISR_HTIF4 DMA_ISR_HTIF4_Msk /*!< Channel 4 Half Transfer flag */
+#define DMA_ISR_TEIF4_Pos (15U)
+#define DMA_ISR_TEIF4_Msk (0x1U << DMA_ISR_TEIF4_Pos) /*!< 0x00008000 */
+#define DMA_ISR_TEIF4 DMA_ISR_TEIF4_Msk /*!< Channel 4 Transfer Error flag */
+#define DMA_ISR_GIF5_Pos (16U)
+#define DMA_ISR_GIF5_Msk (0x1U << DMA_ISR_GIF5_Pos) /*!< 0x00010000 */
+#define DMA_ISR_GIF5 DMA_ISR_GIF5_Msk /*!< Channel 5 Global interrupt flag */
+#define DMA_ISR_TCIF5_Pos (17U)
+#define DMA_ISR_TCIF5_Msk (0x1U << DMA_ISR_TCIF5_Pos) /*!< 0x00020000 */
+#define DMA_ISR_TCIF5 DMA_ISR_TCIF5_Msk /*!< Channel 5 Transfer Complete flag */
+#define DMA_ISR_HTIF5_Pos (18U)
+#define DMA_ISR_HTIF5_Msk (0x1U << DMA_ISR_HTIF5_Pos) /*!< 0x00040000 */
+#define DMA_ISR_HTIF5 DMA_ISR_HTIF5_Msk /*!< Channel 5 Half Transfer flag */
+#define DMA_ISR_TEIF5_Pos (19U)
+#define DMA_ISR_TEIF5_Msk (0x1U << DMA_ISR_TEIF5_Pos) /*!< 0x00080000 */
+#define DMA_ISR_TEIF5 DMA_ISR_TEIF5_Msk /*!< Channel 5 Transfer Error flag */
+#define DMA_ISR_GIF6_Pos (20U)
+#define DMA_ISR_GIF6_Msk (0x1U << DMA_ISR_GIF6_Pos) /*!< 0x00100000 */
+#define DMA_ISR_GIF6 DMA_ISR_GIF6_Msk /*!< Channel 6 Global interrupt flag */
+#define DMA_ISR_TCIF6_Pos (21U)
+#define DMA_ISR_TCIF6_Msk (0x1U << DMA_ISR_TCIF6_Pos) /*!< 0x00200000 */
+#define DMA_ISR_TCIF6 DMA_ISR_TCIF6_Msk /*!< Channel 6 Transfer Complete flag */
+#define DMA_ISR_HTIF6_Pos (22U)
+#define DMA_ISR_HTIF6_Msk (0x1U << DMA_ISR_HTIF6_Pos) /*!< 0x00400000 */
+#define DMA_ISR_HTIF6 DMA_ISR_HTIF6_Msk /*!< Channel 6 Half Transfer flag */
+#define DMA_ISR_TEIF6_Pos (23U)
+#define DMA_ISR_TEIF6_Msk (0x1U << DMA_ISR_TEIF6_Pos) /*!< 0x00800000 */
+#define DMA_ISR_TEIF6 DMA_ISR_TEIF6_Msk /*!< Channel 6 Transfer Error flag */
+#define DMA_ISR_GIF7_Pos (24U)
+#define DMA_ISR_GIF7_Msk (0x1U << DMA_ISR_GIF7_Pos) /*!< 0x01000000 */
+#define DMA_ISR_GIF7 DMA_ISR_GIF7_Msk /*!< Channel 7 Global interrupt flag */
+#define DMA_ISR_TCIF7_Pos (25U)
+#define DMA_ISR_TCIF7_Msk (0x1U << DMA_ISR_TCIF7_Pos) /*!< 0x02000000 */
+#define DMA_ISR_TCIF7 DMA_ISR_TCIF7_Msk /*!< Channel 7 Transfer Complete flag */
+#define DMA_ISR_HTIF7_Pos (26U)
+#define DMA_ISR_HTIF7_Msk (0x1U << DMA_ISR_HTIF7_Pos) /*!< 0x04000000 */
+#define DMA_ISR_HTIF7 DMA_ISR_HTIF7_Msk /*!< Channel 7 Half Transfer flag */
+#define DMA_ISR_TEIF7_Pos (27U)
+#define DMA_ISR_TEIF7_Msk (0x1U << DMA_ISR_TEIF7_Pos) /*!< 0x08000000 */
+#define DMA_ISR_TEIF7 DMA_ISR_TEIF7_Msk /*!< Channel 7 Transfer Error flag */
+
+/******************* Bit definition for DMA_IFCR register *******************/
+#define DMA_IFCR_CGIF1_Pos (0U)
+#define DMA_IFCR_CGIF1_Msk (0x1U << DMA_IFCR_CGIF1_Pos) /*!< 0x00000001 */
+#define DMA_IFCR_CGIF1 DMA_IFCR_CGIF1_Msk /*!< Channel 1 Global interrupt clear */
+#define DMA_IFCR_CTCIF1_Pos (1U)
+#define DMA_IFCR_CTCIF1_Msk (0x1U << DMA_IFCR_CTCIF1_Pos) /*!< 0x00000002 */
+#define DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF1_Msk /*!< Channel 1 Transfer Complete clear */
+#define DMA_IFCR_CHTIF1_Pos (2U)
+#define DMA_IFCR_CHTIF1_Msk (0x1U << DMA_IFCR_CHTIF1_Pos) /*!< 0x00000004 */
+#define DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF1_Msk /*!< Channel 1 Half Transfer clear */
+#define DMA_IFCR_CTEIF1_Pos (3U)
+#define DMA_IFCR_CTEIF1_Msk (0x1U << DMA_IFCR_CTEIF1_Pos) /*!< 0x00000008 */
+#define DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF1_Msk /*!< Channel 1 Transfer Error clear */
+#define DMA_IFCR_CGIF2_Pos (4U)
+#define DMA_IFCR_CGIF2_Msk (0x1U << DMA_IFCR_CGIF2_Pos) /*!< 0x00000010 */
+#define DMA_IFCR_CGIF2 DMA_IFCR_CGIF2_Msk /*!< Channel 2 Global interrupt clear */
+#define DMA_IFCR_CTCIF2_Pos (5U)
+#define DMA_IFCR_CTCIF2_Msk (0x1U << DMA_IFCR_CTCIF2_Pos) /*!< 0x00000020 */
+#define DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF2_Msk /*!< Channel 2 Transfer Complete clear */
+#define DMA_IFCR_CHTIF2_Pos (6U)
+#define DMA_IFCR_CHTIF2_Msk (0x1U << DMA_IFCR_CHTIF2_Pos) /*!< 0x00000040 */
+#define DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF2_Msk /*!< Channel 2 Half Transfer clear */
+#define DMA_IFCR_CTEIF2_Pos (7U)
+#define DMA_IFCR_CTEIF2_Msk (0x1U << DMA_IFCR_CTEIF2_Pos) /*!< 0x00000080 */
+#define DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF2_Msk /*!< Channel 2 Transfer Error clear */
+#define DMA_IFCR_CGIF3_Pos (8U)
+#define DMA_IFCR_CGIF3_Msk (0x1U << DMA_IFCR_CGIF3_Pos) /*!< 0x00000100 */
+#define DMA_IFCR_CGIF3 DMA_IFCR_CGIF3_Msk /*!< Channel 3 Global interrupt clear */
+#define DMA_IFCR_CTCIF3_Pos (9U)
+#define DMA_IFCR_CTCIF3_Msk (0x1U << DMA_IFCR_CTCIF3_Pos) /*!< 0x00000200 */
+#define DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF3_Msk /*!< Channel 3 Transfer Complete clear */
+#define DMA_IFCR_CHTIF3_Pos (10U)
+#define DMA_IFCR_CHTIF3_Msk (0x1U << DMA_IFCR_CHTIF3_Pos) /*!< 0x00000400 */
+#define DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF3_Msk /*!< Channel 3 Half Transfer clear */
+#define DMA_IFCR_CTEIF3_Pos (11U)
+#define DMA_IFCR_CTEIF3_Msk (0x1U << DMA_IFCR_CTEIF3_Pos) /*!< 0x00000800 */
+#define DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF3_Msk /*!< Channel 3 Transfer Error clear */
+#define DMA_IFCR_CGIF4_Pos (12U)
+#define DMA_IFCR_CGIF4_Msk (0x1U << DMA_IFCR_CGIF4_Pos) /*!< 0x00001000 */
+#define DMA_IFCR_CGIF4 DMA_IFCR_CGIF4_Msk /*!< Channel 4 Global interrupt clear */
+#define DMA_IFCR_CTCIF4_Pos (13U)
+#define DMA_IFCR_CTCIF4_Msk (0x1U << DMA_IFCR_CTCIF4_Pos) /*!< 0x00002000 */
+#define DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF4_Msk /*!< Channel 4 Transfer Complete clear */
+#define DMA_IFCR_CHTIF4_Pos (14U)
+#define DMA_IFCR_CHTIF4_Msk (0x1U << DMA_IFCR_CHTIF4_Pos) /*!< 0x00004000 */
+#define DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF4_Msk /*!< Channel 4 Half Transfer clear */
+#define DMA_IFCR_CTEIF4_Pos (15U)
+#define DMA_IFCR_CTEIF4_Msk (0x1U << DMA_IFCR_CTEIF4_Pos) /*!< 0x00008000 */
+#define DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF4_Msk /*!< Channel 4 Transfer Error clear */
+#define DMA_IFCR_CGIF5_Pos (16U)
+#define DMA_IFCR_CGIF5_Msk (0x1U << DMA_IFCR_CGIF5_Pos) /*!< 0x00010000 */
+#define DMA_IFCR_CGIF5 DMA_IFCR_CGIF5_Msk /*!< Channel 5 Global interrupt clear */
+#define DMA_IFCR_CTCIF5_Pos (17U)
+#define DMA_IFCR_CTCIF5_Msk (0x1U << DMA_IFCR_CTCIF5_Pos) /*!< 0x00020000 */
+#define DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF5_Msk /*!< Channel 5 Transfer Complete clear */
+#define DMA_IFCR_CHTIF5_Pos (18U)
+#define DMA_IFCR_CHTIF5_Msk (0x1U << DMA_IFCR_CHTIF5_Pos) /*!< 0x00040000 */
+#define DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5_Msk /*!< Channel 5 Half Transfer clear */
+#define DMA_IFCR_CTEIF5_Pos (19U)
+#define DMA_IFCR_CTEIF5_Msk (0x1U << DMA_IFCR_CTEIF5_Pos) /*!< 0x00080000 */
+#define DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF5_Msk /*!< Channel 5 Transfer Error clear */
+#define DMA_IFCR_CGIF6_Pos (20U)
+#define DMA_IFCR_CGIF6_Msk (0x1U << DMA_IFCR_CGIF6_Pos) /*!< 0x00100000 */
+#define DMA_IFCR_CGIF6 DMA_IFCR_CGIF6_Msk /*!< Channel 6 Global interrupt clear */
+#define DMA_IFCR_CTCIF6_Pos (21U)
+#define DMA_IFCR_CTCIF6_Msk (0x1U << DMA_IFCR_CTCIF6_Pos) /*!< 0x00200000 */
+#define DMA_IFCR_CTCIF6 DMA_IFCR_CTCIF6_Msk /*!< Channel 6 Transfer Complete clear */
+#define DMA_IFCR_CHTIF6_Pos (22U)
+#define DMA_IFCR_CHTIF6_Msk (0x1U << DMA_IFCR_CHTIF6_Pos) /*!< 0x00400000 */
+#define DMA_IFCR_CHTIF6 DMA_IFCR_CHTIF6_Msk /*!< Channel 6 Half Transfer clear */
+#define DMA_IFCR_CTEIF6_Pos (23U)
+#define DMA_IFCR_CTEIF6_Msk (0x1U << DMA_IFCR_CTEIF6_Pos) /*!< 0x00800000 */
+#define DMA_IFCR_CTEIF6 DMA_IFCR_CTEIF6_Msk /*!< Channel 6 Transfer Error clear */
+#define DMA_IFCR_CGIF7_Pos (24U)
+#define DMA_IFCR_CGIF7_Msk (0x1U << DMA_IFCR_CGIF7_Pos) /*!< 0x01000000 */
+#define DMA_IFCR_CGIF7 DMA_IFCR_CGIF7_Msk /*!< Channel 7 Global interrupt clear */
+#define DMA_IFCR_CTCIF7_Pos (25U)
+#define DMA_IFCR_CTCIF7_Msk (0x1U << DMA_IFCR_CTCIF7_Pos) /*!< 0x02000000 */
+#define DMA_IFCR_CTCIF7 DMA_IFCR_CTCIF7_Msk /*!< Channel 7 Transfer Complete clear */
+#define DMA_IFCR_CHTIF7_Pos (26U)
+#define DMA_IFCR_CHTIF7_Msk (0x1U << DMA_IFCR_CHTIF7_Pos) /*!< 0x04000000 */
+#define DMA_IFCR_CHTIF7 DMA_IFCR_CHTIF7_Msk /*!< Channel 7 Half Transfer clear */
+#define DMA_IFCR_CTEIF7_Pos (27U)
+#define DMA_IFCR_CTEIF7_Msk (0x1U << DMA_IFCR_CTEIF7_Pos) /*!< 0x08000000 */
+#define DMA_IFCR_CTEIF7 DMA_IFCR_CTEIF7_Msk /*!< Channel 7 Transfer Error clear */
+
+/******************* Bit definition for DMA_CCR register *******************/
+#define DMA_CCR_EN_Pos (0U)
+#define DMA_CCR_EN_Msk (0x1U << DMA_CCR_EN_Pos) /*!< 0x00000001 */
+#define DMA_CCR_EN DMA_CCR_EN_Msk /*!< Channel enable */
+#define DMA_CCR_TCIE_Pos (1U)
+#define DMA_CCR_TCIE_Msk (0x1U << DMA_CCR_TCIE_Pos) /*!< 0x00000002 */
+#define DMA_CCR_TCIE DMA_CCR_TCIE_Msk /*!< Transfer complete interrupt enable */
+#define DMA_CCR_HTIE_Pos (2U)
+#define DMA_CCR_HTIE_Msk (0x1U << DMA_CCR_HTIE_Pos) /*!< 0x00000004 */
+#define DMA_CCR_HTIE DMA_CCR_HTIE_Msk /*!< Half Transfer interrupt enable */
+#define DMA_CCR_TEIE_Pos (3U)
+#define DMA_CCR_TEIE_Msk (0x1U << DMA_CCR_TEIE_Pos) /*!< 0x00000008 */
+#define DMA_CCR_TEIE DMA_CCR_TEIE_Msk /*!< Transfer error interrupt enable */
+#define DMA_CCR_DIR_Pos (4U)
+#define DMA_CCR_DIR_Msk (0x1U << DMA_CCR_DIR_Pos) /*!< 0x00000010 */
+#define DMA_CCR_DIR DMA_CCR_DIR_Msk /*!< Data transfer direction */
+#define DMA_CCR_CIRC_Pos (5U)
+#define DMA_CCR_CIRC_Msk (0x1U << DMA_CCR_CIRC_Pos) /*!< 0x00000020 */
+#define DMA_CCR_CIRC DMA_CCR_CIRC_Msk /*!< Circular mode */
+#define DMA_CCR_PINC_Pos (6U)
+#define DMA_CCR_PINC_Msk (0x1U << DMA_CCR_PINC_Pos) /*!< 0x00000040 */
+#define DMA_CCR_PINC DMA_CCR_PINC_Msk /*!< Peripheral increment mode */
+#define DMA_CCR_MINC_Pos (7U)
+#define DMA_CCR_MINC_Msk (0x1U << DMA_CCR_MINC_Pos) /*!< 0x00000080 */
+#define DMA_CCR_MINC DMA_CCR_MINC_Msk /*!< Memory increment mode */
+
+#define DMA_CCR_PSIZE_Pos (8U)
+#define DMA_CCR_PSIZE_Msk (0x3U << DMA_CCR_PSIZE_Pos) /*!< 0x00000300 */
+#define DMA_CCR_PSIZE DMA_CCR_PSIZE_Msk /*!< PSIZE[1:0] bits (Peripheral size) */
+#define DMA_CCR_PSIZE_0 (0x1U << DMA_CCR_PSIZE_Pos) /*!< 0x00000100 */
+#define DMA_CCR_PSIZE_1 (0x2U << DMA_CCR_PSIZE_Pos) /*!< 0x00000200 */
+
+#define DMA_CCR_MSIZE_Pos (10U)
+#define DMA_CCR_MSIZE_Msk (0x3U << DMA_CCR_MSIZE_Pos) /*!< 0x00000C00 */
+#define DMA_CCR_MSIZE DMA_CCR_MSIZE_Msk /*!< MSIZE[1:0] bits (Memory size) */
+#define DMA_CCR_MSIZE_0 (0x1U << DMA_CCR_MSIZE_Pos) /*!< 0x00000400 */
+#define DMA_CCR_MSIZE_1 (0x2U << DMA_CCR_MSIZE_Pos) /*!< 0x00000800 */
+
+#define DMA_CCR_PL_Pos (12U)
+#define DMA_CCR_PL_Msk (0x3U << DMA_CCR_PL_Pos) /*!< 0x00003000 */
+#define DMA_CCR_PL DMA_CCR_PL_Msk /*!< PL[1:0] bits(Channel Priority level) */
+#define DMA_CCR_PL_0 (0x1U << DMA_CCR_PL_Pos) /*!< 0x00001000 */
+#define DMA_CCR_PL_1 (0x2U << DMA_CCR_PL_Pos) /*!< 0x00002000 */
+
+#define DMA_CCR_MEM2MEM_Pos (14U)
+#define DMA_CCR_MEM2MEM_Msk (0x1U << DMA_CCR_MEM2MEM_Pos) /*!< 0x00004000 */
+#define DMA_CCR_MEM2MEM DMA_CCR_MEM2MEM_Msk /*!< Memory to memory mode */
+
+/****************** Bit definition for DMA_CNDTR register ******************/
+#define DMA_CNDTR_NDT_Pos (0U)
+#define DMA_CNDTR_NDT_Msk (0xFFFFU << DMA_CNDTR_NDT_Pos) /*!< 0x0000FFFF */
+#define DMA_CNDTR_NDT DMA_CNDTR_NDT_Msk /*!< Number of data to Transfer */
+
+/****************** Bit definition for DMA_CPAR register *******************/
+#define DMA_CPAR_PA_Pos (0U)
+#define DMA_CPAR_PA_Msk (0xFFFFFFFFU << DMA_CPAR_PA_Pos) /*!< 0xFFFFFFFF */
+#define DMA_CPAR_PA DMA_CPAR_PA_Msk /*!< Peripheral Address */
+
+/****************** Bit definition for DMA_CMAR register *******************/
+#define DMA_CMAR_MA_Pos (0U)
+#define DMA_CMAR_MA_Msk (0xFFFFFFFFU << DMA_CMAR_MA_Pos) /*!< 0xFFFFFFFF */
+#define DMA_CMAR_MA DMA_CMAR_MA_Msk /*!< Memory Address */
+
+/******************************************************************************/
+/* */
+/* Analog to Digital Converter (ADC) */
+/* */
+/******************************************************************************/
+
+/*
+ * @brief Specific device feature definitions (not present on all devices in the STM32F1 family)
+ */
+/* Note: No specific macro feature on this device */
+
+/******************** Bit definition for ADC_SR register ********************/
+#define ADC_SR_AWD_Pos (0U)
+#define ADC_SR_AWD_Msk (0x1U << ADC_SR_AWD_Pos) /*!< 0x00000001 */
+#define ADC_SR_AWD ADC_SR_AWD_Msk /*!< ADC analog watchdog 1 flag */
+#define ADC_SR_EOS_Pos (1U)
+#define ADC_SR_EOS_Msk (0x1U << ADC_SR_EOS_Pos) /*!< 0x00000002 */
+#define ADC_SR_EOS ADC_SR_EOS_Msk /*!< ADC group regular end of sequence conversions flag */
+#define ADC_SR_JEOS_Pos (2U)
+#define ADC_SR_JEOS_Msk (0x1U << ADC_SR_JEOS_Pos) /*!< 0x00000004 */
+#define ADC_SR_JEOS ADC_SR_JEOS_Msk /*!< ADC group injected end of sequence conversions flag */
+#define ADC_SR_JSTRT_Pos (3U)
+#define ADC_SR_JSTRT_Msk (0x1U << ADC_SR_JSTRT_Pos) /*!< 0x00000008 */
+#define ADC_SR_JSTRT ADC_SR_JSTRT_Msk /*!< ADC group injected conversion start flag */
+#define ADC_SR_STRT_Pos (4U)
+#define ADC_SR_STRT_Msk (0x1U << ADC_SR_STRT_Pos) /*!< 0x00000010 */
+#define ADC_SR_STRT ADC_SR_STRT_Msk /*!< ADC group regular conversion start flag */
+
+/* Legacy defines */
+#define ADC_SR_EOC (ADC_SR_EOS)
+#define ADC_SR_JEOC (ADC_SR_JEOS)
+
+/******************* Bit definition for ADC_CR1 register ********************/
+#define ADC_CR1_AWDCH_Pos (0U)
+#define ADC_CR1_AWDCH_Msk (0x1FU << ADC_CR1_AWDCH_Pos) /*!< 0x0000001F */
+#define ADC_CR1_AWDCH ADC_CR1_AWDCH_Msk /*!< ADC analog watchdog 1 monitored channel selection */
+#define ADC_CR1_AWDCH_0 (0x01U << ADC_CR1_AWDCH_Pos) /*!< 0x00000001 */
+#define ADC_CR1_AWDCH_1 (0x02U << ADC_CR1_AWDCH_Pos) /*!< 0x00000002 */
+#define ADC_CR1_AWDCH_2 (0x04U << ADC_CR1_AWDCH_Pos) /*!< 0x00000004 */
+#define ADC_CR1_AWDCH_3 (0x08U << ADC_CR1_AWDCH_Pos) /*!< 0x00000008 */
+#define ADC_CR1_AWDCH_4 (0x10U << ADC_CR1_AWDCH_Pos) /*!< 0x00000010 */
+
+#define ADC_CR1_EOSIE_Pos (5U)
+#define ADC_CR1_EOSIE_Msk (0x1U << ADC_CR1_EOSIE_Pos) /*!< 0x00000020 */
+#define ADC_CR1_EOSIE ADC_CR1_EOSIE_Msk /*!< ADC group regular end of sequence conversions interrupt */
+#define ADC_CR1_AWDIE_Pos (6U)
+#define ADC_CR1_AWDIE_Msk (0x1U << ADC_CR1_AWDIE_Pos) /*!< 0x00000040 */
+#define ADC_CR1_AWDIE ADC_CR1_AWDIE_Msk /*!< ADC analog watchdog 1 interrupt */
+#define ADC_CR1_JEOSIE_Pos (7U)
+#define ADC_CR1_JEOSIE_Msk (0x1U << ADC_CR1_JEOSIE_Pos) /*!< 0x00000080 */
+#define ADC_CR1_JEOSIE ADC_CR1_JEOSIE_Msk /*!< ADC group injected end of sequence conversions interrupt */
+#define ADC_CR1_SCAN_Pos (8U)
+#define ADC_CR1_SCAN_Msk (0x1U << ADC_CR1_SCAN_Pos) /*!< 0x00000100 */
+#define ADC_CR1_SCAN ADC_CR1_SCAN_Msk /*!< ADC scan mode */
+#define ADC_CR1_AWDSGL_Pos (9U)
+#define ADC_CR1_AWDSGL_Msk (0x1U << ADC_CR1_AWDSGL_Pos) /*!< 0x00000200 */
+#define ADC_CR1_AWDSGL ADC_CR1_AWDSGL_Msk /*!< ADC analog watchdog 1 monitoring a single channel or all channels */
+#define ADC_CR1_JAUTO_Pos (10U)
+#define ADC_CR1_JAUTO_Msk (0x1U << ADC_CR1_JAUTO_Pos) /*!< 0x00000400 */
+#define ADC_CR1_JAUTO ADC_CR1_JAUTO_Msk /*!< ADC group injected automatic trigger mode */
+#define ADC_CR1_DISCEN_Pos (11U)
+#define ADC_CR1_DISCEN_Msk (0x1U << ADC_CR1_DISCEN_Pos) /*!< 0x00000800 */
+#define ADC_CR1_DISCEN ADC_CR1_DISCEN_Msk /*!< ADC group regular sequencer discontinuous mode */
+#define ADC_CR1_JDISCEN_Pos (12U)
+#define ADC_CR1_JDISCEN_Msk (0x1U << ADC_CR1_JDISCEN_Pos) /*!< 0x00001000 */
+#define ADC_CR1_JDISCEN ADC_CR1_JDISCEN_Msk /*!< ADC group injected sequencer discontinuous mode */
+
+#define ADC_CR1_DISCNUM_Pos (13U)
+#define ADC_CR1_DISCNUM_Msk (0x7U << ADC_CR1_DISCNUM_Pos) /*!< 0x0000E000 */
+#define ADC_CR1_DISCNUM ADC_CR1_DISCNUM_Msk /*!< ADC group regular sequencer discontinuous number of ranks */
+#define ADC_CR1_DISCNUM_0 (0x1U << ADC_CR1_DISCNUM_Pos) /*!< 0x00002000 */
+#define ADC_CR1_DISCNUM_1 (0x2U << ADC_CR1_DISCNUM_Pos) /*!< 0x00004000 */
+#define ADC_CR1_DISCNUM_2 (0x4U << ADC_CR1_DISCNUM_Pos) /*!< 0x00008000 */
+
+#define ADC_CR1_JAWDEN_Pos (22U)
+#define ADC_CR1_JAWDEN_Msk (0x1U << ADC_CR1_JAWDEN_Pos) /*!< 0x00400000 */
+#define ADC_CR1_JAWDEN ADC_CR1_JAWDEN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group injected */
+#define ADC_CR1_AWDEN_Pos (23U)
+#define ADC_CR1_AWDEN_Msk (0x1U << ADC_CR1_AWDEN_Pos) /*!< 0x00800000 */
+#define ADC_CR1_AWDEN ADC_CR1_AWDEN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group regular */
+
+/* Legacy defines */
+#define ADC_CR1_EOCIE (ADC_CR1_EOSIE)
+#define ADC_CR1_JEOCIE (ADC_CR1_JEOSIE)
+
+/******************* Bit definition for ADC_CR2 register ********************/
+#define ADC_CR2_ADON_Pos (0U)
+#define ADC_CR2_ADON_Msk (0x1U << ADC_CR2_ADON_Pos) /*!< 0x00000001 */
+#define ADC_CR2_ADON ADC_CR2_ADON_Msk /*!< ADC enable */
+#define ADC_CR2_CONT_Pos (1U)
+#define ADC_CR2_CONT_Msk (0x1U << ADC_CR2_CONT_Pos) /*!< 0x00000002 */
+#define ADC_CR2_CONT ADC_CR2_CONT_Msk /*!< ADC group regular continuous conversion mode */
+#define ADC_CR2_CAL_Pos (2U)
+#define ADC_CR2_CAL_Msk (0x1U << ADC_CR2_CAL_Pos) /*!< 0x00000004 */
+#define ADC_CR2_CAL ADC_CR2_CAL_Msk /*!< ADC calibration start */
+#define ADC_CR2_RSTCAL_Pos (3U)
+#define ADC_CR2_RSTCAL_Msk (0x1U << ADC_CR2_RSTCAL_Pos) /*!< 0x00000008 */
+#define ADC_CR2_RSTCAL ADC_CR2_RSTCAL_Msk /*!< ADC calibration reset */
+#define ADC_CR2_DMA_Pos (8U)
+#define ADC_CR2_DMA_Msk (0x1U << ADC_CR2_DMA_Pos) /*!< 0x00000100 */
+#define ADC_CR2_DMA ADC_CR2_DMA_Msk /*!< ADC DMA transfer enable */
+#define ADC_CR2_ALIGN_Pos (11U)
+#define ADC_CR2_ALIGN_Msk (0x1U << ADC_CR2_ALIGN_Pos) /*!< 0x00000800 */
+#define ADC_CR2_ALIGN ADC_CR2_ALIGN_Msk /*!< ADC data alignement */
+
+#define ADC_CR2_JEXTSEL_Pos (12U)
+#define ADC_CR2_JEXTSEL_Msk (0x7U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00007000 */
+#define ADC_CR2_JEXTSEL ADC_CR2_JEXTSEL_Msk /*!< ADC group injected external trigger source */
+#define ADC_CR2_JEXTSEL_0 (0x1U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00001000 */
+#define ADC_CR2_JEXTSEL_1 (0x2U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00002000 */
+#define ADC_CR2_JEXTSEL_2 (0x4U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00004000 */
+
+#define ADC_CR2_JEXTTRIG_Pos (15U)
+#define ADC_CR2_JEXTTRIG_Msk (0x1U << ADC_CR2_JEXTTRIG_Pos) /*!< 0x00008000 */
+#define ADC_CR2_JEXTTRIG ADC_CR2_JEXTTRIG_Msk /*!< ADC group injected external trigger enable */
+
+#define ADC_CR2_EXTSEL_Pos (17U)
+#define ADC_CR2_EXTSEL_Msk (0x7U << ADC_CR2_EXTSEL_Pos) /*!< 0x000E0000 */
+#define ADC_CR2_EXTSEL ADC_CR2_EXTSEL_Msk /*!< ADC group regular external trigger source */
+#define ADC_CR2_EXTSEL_0 (0x1U << ADC_CR2_EXTSEL_Pos) /*!< 0x00020000 */
+#define ADC_CR2_EXTSEL_1 (0x2U << ADC_CR2_EXTSEL_Pos) /*!< 0x00040000 */
+#define ADC_CR2_EXTSEL_2 (0x4U << ADC_CR2_EXTSEL_Pos) /*!< 0x00080000 */
+
+#define ADC_CR2_EXTTRIG_Pos (20U)
+#define ADC_CR2_EXTTRIG_Msk (0x1U << ADC_CR2_EXTTRIG_Pos) /*!< 0x00100000 */
+#define ADC_CR2_EXTTRIG ADC_CR2_EXTTRIG_Msk /*!< ADC group regular external trigger enable */
+#define ADC_CR2_JSWSTART_Pos (21U)
+#define ADC_CR2_JSWSTART_Msk (0x1U << ADC_CR2_JSWSTART_Pos) /*!< 0x00200000 */
+#define ADC_CR2_JSWSTART ADC_CR2_JSWSTART_Msk /*!< ADC group injected conversion start */
+#define ADC_CR2_SWSTART_Pos (22U)
+#define ADC_CR2_SWSTART_Msk (0x1U << ADC_CR2_SWSTART_Pos) /*!< 0x00400000 */
+#define ADC_CR2_SWSTART ADC_CR2_SWSTART_Msk /*!< ADC group regular conversion start */
+#define ADC_CR2_TSVREFE_Pos (23U)
+#define ADC_CR2_TSVREFE_Msk (0x1U << ADC_CR2_TSVREFE_Pos) /*!< 0x00800000 */
+#define ADC_CR2_TSVREFE ADC_CR2_TSVREFE_Msk /*!< ADC internal path to VrefInt and temperature sensor enable */
+
+/****************** Bit definition for ADC_SMPR1 register *******************/
+#define ADC_SMPR1_SMP10_Pos (0U)
+#define ADC_SMPR1_SMP10_Msk (0x7U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000007 */
+#define ADC_SMPR1_SMP10 ADC_SMPR1_SMP10_Msk /*!< ADC channel 10 sampling time selection */
+#define ADC_SMPR1_SMP10_0 (0x1U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000001 */
+#define ADC_SMPR1_SMP10_1 (0x2U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000002 */
+#define ADC_SMPR1_SMP10_2 (0x4U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000004 */
+
+#define ADC_SMPR1_SMP11_Pos (3U)
+#define ADC_SMPR1_SMP11_Msk (0x7U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000038 */
+#define ADC_SMPR1_SMP11 ADC_SMPR1_SMP11_Msk /*!< ADC channel 11 sampling time selection */
+#define ADC_SMPR1_SMP11_0 (0x1U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000008 */
+#define ADC_SMPR1_SMP11_1 (0x2U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000010 */
+#define ADC_SMPR1_SMP11_2 (0x4U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000020 */
+
+#define ADC_SMPR1_SMP12_Pos (6U)
+#define ADC_SMPR1_SMP12_Msk (0x7U << ADC_SMPR1_SMP12_Pos) /*!< 0x000001C0 */
+#define ADC_SMPR1_SMP12 ADC_SMPR1_SMP12_Msk /*!< ADC channel 12 sampling time selection */
+#define ADC_SMPR1_SMP12_0 (0x1U << ADC_SMPR1_SMP12_Pos) /*!< 0x00000040 */
+#define ADC_SMPR1_SMP12_1 (0x2U << ADC_SMPR1_SMP12_Pos) /*!< 0x00000080 */
+#define ADC_SMPR1_SMP12_2 (0x4U << ADC_SMPR1_SMP12_Pos) /*!< 0x00000100 */
+
+#define ADC_SMPR1_SMP13_Pos (9U)
+#define ADC_SMPR1_SMP13_Msk (0x7U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000E00 */
+#define ADC_SMPR1_SMP13 ADC_SMPR1_SMP13_Msk /*!< ADC channel 13 sampling time selection */
+#define ADC_SMPR1_SMP13_0 (0x1U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000200 */
+#define ADC_SMPR1_SMP13_1 (0x2U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000400 */
+#define ADC_SMPR1_SMP13_2 (0x4U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000800 */
+
+#define ADC_SMPR1_SMP14_Pos (12U)
+#define ADC_SMPR1_SMP14_Msk (0x7U << ADC_SMPR1_SMP14_Pos) /*!< 0x00007000 */
+#define ADC_SMPR1_SMP14 ADC_SMPR1_SMP14_Msk /*!< ADC channel 14 sampling time selection */
+#define ADC_SMPR1_SMP14_0 (0x1U << ADC_SMPR1_SMP14_Pos) /*!< 0x00001000 */
+#define ADC_SMPR1_SMP14_1 (0x2U << ADC_SMPR1_SMP14_Pos) /*!< 0x00002000 */
+#define ADC_SMPR1_SMP14_2 (0x4U << ADC_SMPR1_SMP14_Pos) /*!< 0x00004000 */
+
+#define ADC_SMPR1_SMP15_Pos (15U)
+#define ADC_SMPR1_SMP15_Msk (0x7U << ADC_SMPR1_SMP15_Pos) /*!< 0x00038000 */
+#define ADC_SMPR1_SMP15 ADC_SMPR1_SMP15_Msk /*!< ADC channel 15 sampling time selection */
+#define ADC_SMPR1_SMP15_0 (0x1U << ADC_SMPR1_SMP15_Pos) /*!< 0x00008000 */
+#define ADC_SMPR1_SMP15_1 (0x2U << ADC_SMPR1_SMP15_Pos) /*!< 0x00010000 */
+#define ADC_SMPR1_SMP15_2 (0x4U << ADC_SMPR1_SMP15_Pos) /*!< 0x00020000 */
+
+#define ADC_SMPR1_SMP16_Pos (18U)
+#define ADC_SMPR1_SMP16_Msk (0x7U << ADC_SMPR1_SMP16_Pos) /*!< 0x001C0000 */
+#define ADC_SMPR1_SMP16 ADC_SMPR1_SMP16_Msk /*!< ADC channel 16 sampling time selection */
+#define ADC_SMPR1_SMP16_0 (0x1U << ADC_SMPR1_SMP16_Pos) /*!< 0x00040000 */
+#define ADC_SMPR1_SMP16_1 (0x2U << ADC_SMPR1_SMP16_Pos) /*!< 0x00080000 */
+#define ADC_SMPR1_SMP16_2 (0x4U << ADC_SMPR1_SMP16_Pos) /*!< 0x00100000 */
+
+#define ADC_SMPR1_SMP17_Pos (21U)
+#define ADC_SMPR1_SMP17_Msk (0x7U << ADC_SMPR1_SMP17_Pos) /*!< 0x00E00000 */
+#define ADC_SMPR1_SMP17 ADC_SMPR1_SMP17_Msk /*!< ADC channel 17 sampling time selection */
+#define ADC_SMPR1_SMP17_0 (0x1U << ADC_SMPR1_SMP17_Pos) /*!< 0x00200000 */
+#define ADC_SMPR1_SMP17_1 (0x2U << ADC_SMPR1_SMP17_Pos) /*!< 0x00400000 */
+#define ADC_SMPR1_SMP17_2 (0x4U << ADC_SMPR1_SMP17_Pos) /*!< 0x00800000 */
+
+/****************** Bit definition for ADC_SMPR2 register *******************/
+#define ADC_SMPR2_SMP0_Pos (0U)
+#define ADC_SMPR2_SMP0_Msk (0x7U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000007 */
+#define ADC_SMPR2_SMP0 ADC_SMPR2_SMP0_Msk /*!< ADC channel 0 sampling time selection */
+#define ADC_SMPR2_SMP0_0 (0x1U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000001 */
+#define ADC_SMPR2_SMP0_1 (0x2U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000002 */
+#define ADC_SMPR2_SMP0_2 (0x4U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000004 */
+
+#define ADC_SMPR2_SMP1_Pos (3U)
+#define ADC_SMPR2_SMP1_Msk (0x7U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000038 */
+#define ADC_SMPR2_SMP1 ADC_SMPR2_SMP1_Msk /*!< ADC channel 1 sampling time selection */
+#define ADC_SMPR2_SMP1_0 (0x1U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000008 */
+#define ADC_SMPR2_SMP1_1 (0x2U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000010 */
+#define ADC_SMPR2_SMP1_2 (0x4U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000020 */
+
+#define ADC_SMPR2_SMP2_Pos (6U)
+#define ADC_SMPR2_SMP2_Msk (0x7U << ADC_SMPR2_SMP2_Pos) /*!< 0x000001C0 */
+#define ADC_SMPR2_SMP2 ADC_SMPR2_SMP2_Msk /*!< ADC channel 2 sampling time selection */
+#define ADC_SMPR2_SMP2_0 (0x1U << ADC_SMPR2_SMP2_Pos) /*!< 0x00000040 */
+#define ADC_SMPR2_SMP2_1 (0x2U << ADC_SMPR2_SMP2_Pos) /*!< 0x00000080 */
+#define ADC_SMPR2_SMP2_2 (0x4U << ADC_SMPR2_SMP2_Pos) /*!< 0x00000100 */
+
+#define ADC_SMPR2_SMP3_Pos (9U)
+#define ADC_SMPR2_SMP3_Msk (0x7U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000E00 */
+#define ADC_SMPR2_SMP3 ADC_SMPR2_SMP3_Msk /*!< ADC channel 3 sampling time selection */
+#define ADC_SMPR2_SMP3_0 (0x1U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000200 */
+#define ADC_SMPR2_SMP3_1 (0x2U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000400 */
+#define ADC_SMPR2_SMP3_2 (0x4U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000800 */
+
+#define ADC_SMPR2_SMP4_Pos (12U)
+#define ADC_SMPR2_SMP4_Msk (0x7U << ADC_SMPR2_SMP4_Pos) /*!< 0x00007000 */
+#define ADC_SMPR2_SMP4 ADC_SMPR2_SMP4_Msk /*!< ADC channel 4 sampling time selection */
+#define ADC_SMPR2_SMP4_0 (0x1U << ADC_SMPR2_SMP4_Pos) /*!< 0x00001000 */
+#define ADC_SMPR2_SMP4_1 (0x2U << ADC_SMPR2_SMP4_Pos) /*!< 0x00002000 */
+#define ADC_SMPR2_SMP4_2 (0x4U << ADC_SMPR2_SMP4_Pos) /*!< 0x00004000 */
+
+#define ADC_SMPR2_SMP5_Pos (15U)
+#define ADC_SMPR2_SMP5_Msk (0x7U << ADC_SMPR2_SMP5_Pos) /*!< 0x00038000 */
+#define ADC_SMPR2_SMP5 ADC_SMPR2_SMP5_Msk /*!< ADC channel 5 sampling time selection */
+#define ADC_SMPR2_SMP5_0 (0x1U << ADC_SMPR2_SMP5_Pos) /*!< 0x00008000 */
+#define ADC_SMPR2_SMP5_1 (0x2U << ADC_SMPR2_SMP5_Pos) /*!< 0x00010000 */
+#define ADC_SMPR2_SMP5_2 (0x4U << ADC_SMPR2_SMP5_Pos) /*!< 0x00020000 */
+
+#define ADC_SMPR2_SMP6_Pos (18U)
+#define ADC_SMPR2_SMP6_Msk (0x7U << ADC_SMPR2_SMP6_Pos) /*!< 0x001C0000 */
+#define ADC_SMPR2_SMP6 ADC_SMPR2_SMP6_Msk /*!< ADC channel 6 sampling time selection */
+#define ADC_SMPR2_SMP6_0 (0x1U << ADC_SMPR2_SMP6_Pos) /*!< 0x00040000 */
+#define ADC_SMPR2_SMP6_1 (0x2U << ADC_SMPR2_SMP6_Pos) /*!< 0x00080000 */
+#define ADC_SMPR2_SMP6_2 (0x4U << ADC_SMPR2_SMP6_Pos) /*!< 0x00100000 */
+
+#define ADC_SMPR2_SMP7_Pos (21U)
+#define ADC_SMPR2_SMP7_Msk (0x7U << ADC_SMPR2_SMP7_Pos) /*!< 0x00E00000 */
+#define ADC_SMPR2_SMP7 ADC_SMPR2_SMP7_Msk /*!< ADC channel 7 sampling time selection */
+#define ADC_SMPR2_SMP7_0 (0x1U << ADC_SMPR2_SMP7_Pos) /*!< 0x00200000 */
+#define ADC_SMPR2_SMP7_1 (0x2U << ADC_SMPR2_SMP7_Pos) /*!< 0x00400000 */
+#define ADC_SMPR2_SMP7_2 (0x4U << ADC_SMPR2_SMP7_Pos) /*!< 0x00800000 */
+
+#define ADC_SMPR2_SMP8_Pos (24U)
+#define ADC_SMPR2_SMP8_Msk (0x7U << ADC_SMPR2_SMP8_Pos) /*!< 0x07000000 */
+#define ADC_SMPR2_SMP8 ADC_SMPR2_SMP8_Msk /*!< ADC channel 8 sampling time selection */
+#define ADC_SMPR2_SMP8_0 (0x1U << ADC_SMPR2_SMP8_Pos) /*!< 0x01000000 */
+#define ADC_SMPR2_SMP8_1 (0x2U << ADC_SMPR2_SMP8_Pos) /*!< 0x02000000 */
+#define ADC_SMPR2_SMP8_2 (0x4U << ADC_SMPR2_SMP8_Pos) /*!< 0x04000000 */
+
+#define ADC_SMPR2_SMP9_Pos (27U)
+#define ADC_SMPR2_SMP9_Msk (0x7U << ADC_SMPR2_SMP9_Pos) /*!< 0x38000000 */
+#define ADC_SMPR2_SMP9 ADC_SMPR2_SMP9_Msk /*!< ADC channel 9 sampling time selection */
+#define ADC_SMPR2_SMP9_0 (0x1U << ADC_SMPR2_SMP9_Pos) /*!< 0x08000000 */
+#define ADC_SMPR2_SMP9_1 (0x2U << ADC_SMPR2_SMP9_Pos) /*!< 0x10000000 */
+#define ADC_SMPR2_SMP9_2 (0x4U << ADC_SMPR2_SMP9_Pos) /*!< 0x20000000 */
+
+/****************** Bit definition for ADC_JOFR1 register *******************/
+#define ADC_JOFR1_JOFFSET1_Pos (0U)
+#define ADC_JOFR1_JOFFSET1_Msk (0xFFFU << ADC_JOFR1_JOFFSET1_Pos) /*!< 0x00000FFF */
+#define ADC_JOFR1_JOFFSET1 ADC_JOFR1_JOFFSET1_Msk /*!< ADC group injected sequencer rank 1 offset value */
+
+/****************** Bit definition for ADC_JOFR2 register *******************/
+#define ADC_JOFR2_JOFFSET2_Pos (0U)
+#define ADC_JOFR2_JOFFSET2_Msk (0xFFFU << ADC_JOFR2_JOFFSET2_Pos) /*!< 0x00000FFF */
+#define ADC_JOFR2_JOFFSET2 ADC_JOFR2_JOFFSET2_Msk /*!< ADC group injected sequencer rank 2 offset value */
+
+/****************** Bit definition for ADC_JOFR3 register *******************/
+#define ADC_JOFR3_JOFFSET3_Pos (0U)
+#define ADC_JOFR3_JOFFSET3_Msk (0xFFFU << ADC_JOFR3_JOFFSET3_Pos) /*!< 0x00000FFF */
+#define ADC_JOFR3_JOFFSET3 ADC_JOFR3_JOFFSET3_Msk /*!< ADC group injected sequencer rank 3 offset value */
+
+/****************** Bit definition for ADC_JOFR4 register *******************/
+#define ADC_JOFR4_JOFFSET4_Pos (0U)
+#define ADC_JOFR4_JOFFSET4_Msk (0xFFFU << ADC_JOFR4_JOFFSET4_Pos) /*!< 0x00000FFF */
+#define ADC_JOFR4_JOFFSET4 ADC_JOFR4_JOFFSET4_Msk /*!< ADC group injected sequencer rank 4 offset value */
+
+/******************* Bit definition for ADC_HTR register ********************/
+#define ADC_HTR_HT_Pos (0U)
+#define ADC_HTR_HT_Msk (0xFFFU << ADC_HTR_HT_Pos) /*!< 0x00000FFF */
+#define ADC_HTR_HT ADC_HTR_HT_Msk /*!< ADC analog watchdog 1 threshold high */
+
+/******************* Bit definition for ADC_LTR register ********************/
+#define ADC_LTR_LT_Pos (0U)
+#define ADC_LTR_LT_Msk (0xFFFU << ADC_LTR_LT_Pos) /*!< 0x00000FFF */
+#define ADC_LTR_LT ADC_LTR_LT_Msk /*!< ADC analog watchdog 1 threshold low */
+
+/******************* Bit definition for ADC_SQR1 register *******************/
+#define ADC_SQR1_SQ13_Pos (0U)
+#define ADC_SQR1_SQ13_Msk (0x1FU << ADC_SQR1_SQ13_Pos) /*!< 0x0000001F */
+#define ADC_SQR1_SQ13 ADC_SQR1_SQ13_Msk /*!< ADC group regular sequencer rank 13 */
+#define ADC_SQR1_SQ13_0 (0x01U << ADC_SQR1_SQ13_Pos) /*!< 0x00000001 */
+#define ADC_SQR1_SQ13_1 (0x02U << ADC_SQR1_SQ13_Pos) /*!< 0x00000002 */
+#define ADC_SQR1_SQ13_2 (0x04U << ADC_SQR1_SQ13_Pos) /*!< 0x00000004 */
+#define ADC_SQR1_SQ13_3 (0x08U << ADC_SQR1_SQ13_Pos) /*!< 0x00000008 */
+#define ADC_SQR1_SQ13_4 (0x10U << ADC_SQR1_SQ13_Pos) /*!< 0x00000010 */
+
+#define ADC_SQR1_SQ14_Pos (5U)
+#define ADC_SQR1_SQ14_Msk (0x1FU << ADC_SQR1_SQ14_Pos) /*!< 0x000003E0 */
+#define ADC_SQR1_SQ14 ADC_SQR1_SQ14_Msk /*!< ADC group regular sequencer rank 14 */
+#define ADC_SQR1_SQ14_0 (0x01U << ADC_SQR1_SQ14_Pos) /*!< 0x00000020 */
+#define ADC_SQR1_SQ14_1 (0x02U << ADC_SQR1_SQ14_Pos) /*!< 0x00000040 */
+#define ADC_SQR1_SQ14_2 (0x04U << ADC_SQR1_SQ14_Pos) /*!< 0x00000080 */
+#define ADC_SQR1_SQ14_3 (0x08U << ADC_SQR1_SQ14_Pos) /*!< 0x00000100 */
+#define ADC_SQR1_SQ14_4 (0x10U << ADC_SQR1_SQ14_Pos) /*!< 0x00000200 */
+
+#define ADC_SQR1_SQ15_Pos (10U)
+#define ADC_SQR1_SQ15_Msk (0x1FU << ADC_SQR1_SQ15_Pos) /*!< 0x00007C00 */
+#define ADC_SQR1_SQ15 ADC_SQR1_SQ15_Msk /*!< ADC group regular sequencer rank 15 */
+#define ADC_SQR1_SQ15_0 (0x01U << ADC_SQR1_SQ15_Pos) /*!< 0x00000400 */
+#define ADC_SQR1_SQ15_1 (0x02U << ADC_SQR1_SQ15_Pos) /*!< 0x00000800 */
+#define ADC_SQR1_SQ15_2 (0x04U << ADC_SQR1_SQ15_Pos) /*!< 0x00001000 */
+#define ADC_SQR1_SQ15_3 (0x08U << ADC_SQR1_SQ15_Pos) /*!< 0x00002000 */
+#define ADC_SQR1_SQ15_4 (0x10U << ADC_SQR1_SQ15_Pos) /*!< 0x00004000 */
+
+#define ADC_SQR1_SQ16_Pos (15U)
+#define ADC_SQR1_SQ16_Msk (0x1FU << ADC_SQR1_SQ16_Pos) /*!< 0x000F8000 */
+#define ADC_SQR1_SQ16 ADC_SQR1_SQ16_Msk /*!< ADC group regular sequencer rank 16 */
+#define ADC_SQR1_SQ16_0 (0x01U << ADC_SQR1_SQ16_Pos) /*!< 0x00008000 */
+#define ADC_SQR1_SQ16_1 (0x02U << ADC_SQR1_SQ16_Pos) /*!< 0x00010000 */
+#define ADC_SQR1_SQ16_2 (0x04U << ADC_SQR1_SQ16_Pos) /*!< 0x00020000 */
+#define ADC_SQR1_SQ16_3 (0x08U << ADC_SQR1_SQ16_Pos) /*!< 0x00040000 */
+#define ADC_SQR1_SQ16_4 (0x10U << ADC_SQR1_SQ16_Pos) /*!< 0x00080000 */
+
+#define ADC_SQR1_L_Pos (20U)
+#define ADC_SQR1_L_Msk (0xFU << ADC_SQR1_L_Pos) /*!< 0x00F00000 */
+#define ADC_SQR1_L ADC_SQR1_L_Msk /*!< ADC group regular sequencer scan length */
+#define ADC_SQR1_L_0 (0x1U << ADC_SQR1_L_Pos) /*!< 0x00100000 */
+#define ADC_SQR1_L_1 (0x2U << ADC_SQR1_L_Pos) /*!< 0x00200000 */
+#define ADC_SQR1_L_2 (0x4U << ADC_SQR1_L_Pos) /*!< 0x00400000 */
+#define ADC_SQR1_L_3 (0x8U << ADC_SQR1_L_Pos) /*!< 0x00800000 */
+
+/******************* Bit definition for ADC_SQR2 register *******************/
+#define ADC_SQR2_SQ7_Pos (0U)
+#define ADC_SQR2_SQ7_Msk (0x1FU << ADC_SQR2_SQ7_Pos) /*!< 0x0000001F */
+#define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk /*!< ADC group regular sequencer rank 7 */
+#define ADC_SQR2_SQ7_0 (0x01U << ADC_SQR2_SQ7_Pos) /*!< 0x00000001 */
+#define ADC_SQR2_SQ7_1 (0x02U << ADC_SQR2_SQ7_Pos) /*!< 0x00000002 */
+#define ADC_SQR2_SQ7_2 (0x04U << ADC_SQR2_SQ7_Pos) /*!< 0x00000004 */
+#define ADC_SQR2_SQ7_3 (0x08U << ADC_SQR2_SQ7_Pos) /*!< 0x00000008 */
+#define ADC_SQR2_SQ7_4 (0x10U << ADC_SQR2_SQ7_Pos) /*!< 0x00000010 */
+
+#define ADC_SQR2_SQ8_Pos (5U)
+#define ADC_SQR2_SQ8_Msk (0x1FU << ADC_SQR2_SQ8_Pos) /*!< 0x000003E0 */
+#define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk /*!< ADC group regular sequencer rank 8 */
+#define ADC_SQR2_SQ8_0 (0x01U << ADC_SQR2_SQ8_Pos) /*!< 0x00000020 */
+#define ADC_SQR2_SQ8_1 (0x02U << ADC_SQR2_SQ8_Pos) /*!< 0x00000040 */
+#define ADC_SQR2_SQ8_2 (0x04U << ADC_SQR2_SQ8_Pos) /*!< 0x00000080 */
+#define ADC_SQR2_SQ8_3 (0x08U << ADC_SQR2_SQ8_Pos) /*!< 0x00000100 */
+#define ADC_SQR2_SQ8_4 (0x10U << ADC_SQR2_SQ8_Pos) /*!< 0x00000200 */
+
+#define ADC_SQR2_SQ9_Pos (10U)
+#define ADC_SQR2_SQ9_Msk (0x1FU << ADC_SQR2_SQ9_Pos) /*!< 0x00007C00 */
+#define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk /*!< ADC group regular sequencer rank 9 */
+#define ADC_SQR2_SQ9_0 (0x01U << ADC_SQR2_SQ9_Pos) /*!< 0x00000400 */
+#define ADC_SQR2_SQ9_1 (0x02U << ADC_SQR2_SQ9_Pos) /*!< 0x00000800 */
+#define ADC_SQR2_SQ9_2 (0x04U << ADC_SQR2_SQ9_Pos) /*!< 0x00001000 */
+#define ADC_SQR2_SQ9_3 (0x08U << ADC_SQR2_SQ9_Pos) /*!< 0x00002000 */
+#define ADC_SQR2_SQ9_4 (0x10U << ADC_SQR2_SQ9_Pos) /*!< 0x00004000 */
+
+#define ADC_SQR2_SQ10_Pos (15U)
+#define ADC_SQR2_SQ10_Msk (0x1FU << ADC_SQR2_SQ10_Pos) /*!< 0x000F8000 */
+#define ADC_SQR2_SQ10 ADC_SQR2_SQ10_Msk /*!< ADC group regular sequencer rank 10 */
+#define ADC_SQR2_SQ10_0 (0x01U << ADC_SQR2_SQ10_Pos) /*!< 0x00008000 */
+#define ADC_SQR2_SQ10_1 (0x02U << ADC_SQR2_SQ10_Pos) /*!< 0x00010000 */
+#define ADC_SQR2_SQ10_2 (0x04U << ADC_SQR2_SQ10_Pos) /*!< 0x00020000 */
+#define ADC_SQR2_SQ10_3 (0x08U << ADC_SQR2_SQ10_Pos) /*!< 0x00040000 */
+#define ADC_SQR2_SQ10_4 (0x10U << ADC_SQR2_SQ10_Pos) /*!< 0x00080000 */
+
+#define ADC_SQR2_SQ11_Pos (20U)
+#define ADC_SQR2_SQ11_Msk (0x1FU << ADC_SQR2_SQ11_Pos) /*!< 0x01F00000 */
+#define ADC_SQR2_SQ11 ADC_SQR2_SQ11_Msk /*!< ADC group regular sequencer rank 1 */
+#define ADC_SQR2_SQ11_0 (0x01U << ADC_SQR2_SQ11_Pos) /*!< 0x00100000 */
+#define ADC_SQR2_SQ11_1 (0x02U << ADC_SQR2_SQ11_Pos) /*!< 0x00200000 */
+#define ADC_SQR2_SQ11_2 (0x04U << ADC_SQR2_SQ11_Pos) /*!< 0x00400000 */
+#define ADC_SQR2_SQ11_3 (0x08U << ADC_SQR2_SQ11_Pos) /*!< 0x00800000 */
+#define ADC_SQR2_SQ11_4 (0x10U << ADC_SQR2_SQ11_Pos) /*!< 0x01000000 */
+
+#define ADC_SQR2_SQ12_Pos (25U)
+#define ADC_SQR2_SQ12_Msk (0x1FU << ADC_SQR2_SQ12_Pos) /*!< 0x3E000000 */
+#define ADC_SQR2_SQ12 ADC_SQR2_SQ12_Msk /*!< ADC group regular sequencer rank 12 */
+#define ADC_SQR2_SQ12_0 (0x01U << ADC_SQR2_SQ12_Pos) /*!< 0x02000000 */
+#define ADC_SQR2_SQ12_1 (0x02U << ADC_SQR2_SQ12_Pos) /*!< 0x04000000 */
+#define ADC_SQR2_SQ12_2 (0x04U << ADC_SQR2_SQ12_Pos) /*!< 0x08000000 */
+#define ADC_SQR2_SQ12_3 (0x08U << ADC_SQR2_SQ12_Pos) /*!< 0x10000000 */
+#define ADC_SQR2_SQ12_4 (0x10U << ADC_SQR2_SQ12_Pos) /*!< 0x20000000 */
+
+/******************* Bit definition for ADC_SQR3 register *******************/
+#define ADC_SQR3_SQ1_Pos (0U)
+#define ADC_SQR3_SQ1_Msk (0x1FU << ADC_SQR3_SQ1_Pos) /*!< 0x0000001F */
+#define ADC_SQR3_SQ1 ADC_SQR3_SQ1_Msk /*!< ADC group regular sequencer rank 1 */
+#define ADC_SQR3_SQ1_0 (0x01U << ADC_SQR3_SQ1_Pos) /*!< 0x00000001 */
+#define ADC_SQR3_SQ1_1 (0x02U << ADC_SQR3_SQ1_Pos) /*!< 0x00000002 */
+#define ADC_SQR3_SQ1_2 (0x04U << ADC_SQR3_SQ1_Pos) /*!< 0x00000004 */
+#define ADC_SQR3_SQ1_3 (0x08U << ADC_SQR3_SQ1_Pos) /*!< 0x00000008 */
+#define ADC_SQR3_SQ1_4 (0x10U << ADC_SQR3_SQ1_Pos) /*!< 0x00000010 */
+
+#define ADC_SQR3_SQ2_Pos (5U)
+#define ADC_SQR3_SQ2_Msk (0x1FU << ADC_SQR3_SQ2_Pos) /*!< 0x000003E0 */
+#define ADC_SQR3_SQ2 ADC_SQR3_SQ2_Msk /*!< ADC group regular sequencer rank 2 */
+#define ADC_SQR3_SQ2_0 (0x01U << ADC_SQR3_SQ2_Pos) /*!< 0x00000020 */
+#define ADC_SQR3_SQ2_1 (0x02U << ADC_SQR3_SQ2_Pos) /*!< 0x00000040 */
+#define ADC_SQR3_SQ2_2 (0x04U << ADC_SQR3_SQ2_Pos) /*!< 0x00000080 */
+#define ADC_SQR3_SQ2_3 (0x08U << ADC_SQR3_SQ2_Pos) /*!< 0x00000100 */
+#define ADC_SQR3_SQ2_4 (0x10U << ADC_SQR3_SQ2_Pos) /*!< 0x00000200 */
+
+#define ADC_SQR3_SQ3_Pos (10U)
+#define ADC_SQR3_SQ3_Msk (0x1FU << ADC_SQR3_SQ3_Pos) /*!< 0x00007C00 */
+#define ADC_SQR3_SQ3 ADC_SQR3_SQ3_Msk /*!< ADC group regular sequencer rank 3 */
+#define ADC_SQR3_SQ3_0 (0x01U << ADC_SQR3_SQ3_Pos) /*!< 0x00000400 */
+#define ADC_SQR3_SQ3_1 (0x02U << ADC_SQR3_SQ3_Pos) /*!< 0x00000800 */
+#define ADC_SQR3_SQ3_2 (0x04U << ADC_SQR3_SQ3_Pos) /*!< 0x00001000 */
+#define ADC_SQR3_SQ3_3 (0x08U << ADC_SQR3_SQ3_Pos) /*!< 0x00002000 */
+#define ADC_SQR3_SQ3_4 (0x10U << ADC_SQR3_SQ3_Pos) /*!< 0x00004000 */
+
+#define ADC_SQR3_SQ4_Pos (15U)
+#define ADC_SQR3_SQ4_Msk (0x1FU << ADC_SQR3_SQ4_Pos) /*!< 0x000F8000 */
+#define ADC_SQR3_SQ4 ADC_SQR3_SQ4_Msk /*!< ADC group regular sequencer rank 4 */
+#define ADC_SQR3_SQ4_0 (0x01U << ADC_SQR3_SQ4_Pos) /*!< 0x00008000 */
+#define ADC_SQR3_SQ4_1 (0x02U << ADC_SQR3_SQ4_Pos) /*!< 0x00010000 */
+#define ADC_SQR3_SQ4_2 (0x04U << ADC_SQR3_SQ4_Pos) /*!< 0x00020000 */
+#define ADC_SQR3_SQ4_3 (0x08U << ADC_SQR3_SQ4_Pos) /*!< 0x00040000 */
+#define ADC_SQR3_SQ4_4 (0x10U << ADC_SQR3_SQ4_Pos) /*!< 0x00080000 */
+
+#define ADC_SQR3_SQ5_Pos (20U)
+#define ADC_SQR3_SQ5_Msk (0x1FU << ADC_SQR3_SQ5_Pos) /*!< 0x01F00000 */
+#define ADC_SQR3_SQ5 ADC_SQR3_SQ5_Msk /*!< ADC group regular sequencer rank 5 */
+#define ADC_SQR3_SQ5_0 (0x01U << ADC_SQR3_SQ5_Pos) /*!< 0x00100000 */
+#define ADC_SQR3_SQ5_1 (0x02U << ADC_SQR3_SQ5_Pos) /*!< 0x00200000 */
+#define ADC_SQR3_SQ5_2 (0x04U << ADC_SQR3_SQ5_Pos) /*!< 0x00400000 */
+#define ADC_SQR3_SQ5_3 (0x08U << ADC_SQR3_SQ5_Pos) /*!< 0x00800000 */
+#define ADC_SQR3_SQ5_4 (0x10U << ADC_SQR3_SQ5_Pos) /*!< 0x01000000 */
+
+#define ADC_SQR3_SQ6_Pos (25U)
+#define ADC_SQR3_SQ6_Msk (0x1FU << ADC_SQR3_SQ6_Pos) /*!< 0x3E000000 */
+#define ADC_SQR3_SQ6 ADC_SQR3_SQ6_Msk /*!< ADC group regular sequencer rank 6 */
+#define ADC_SQR3_SQ6_0 (0x01U << ADC_SQR3_SQ6_Pos) /*!< 0x02000000 */
+#define ADC_SQR3_SQ6_1 (0x02U << ADC_SQR3_SQ6_Pos) /*!< 0x04000000 */
+#define ADC_SQR3_SQ6_2 (0x04U << ADC_SQR3_SQ6_Pos) /*!< 0x08000000 */
+#define ADC_SQR3_SQ6_3 (0x08U << ADC_SQR3_SQ6_Pos) /*!< 0x10000000 */
+#define ADC_SQR3_SQ6_4 (0x10U << ADC_SQR3_SQ6_Pos) /*!< 0x20000000 */
+
+/******************* Bit definition for ADC_JSQR register *******************/
+#define ADC_JSQR_JSQ1_Pos (0U)
+#define ADC_JSQR_JSQ1_Msk (0x1FU << ADC_JSQR_JSQ1_Pos) /*!< 0x0000001F */
+#define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!< ADC group injected sequencer rank 1 */
+#define ADC_JSQR_JSQ1_0 (0x01U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000001 */
+#define ADC_JSQR_JSQ1_1 (0x02U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000002 */
+#define ADC_JSQR_JSQ1_2 (0x04U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000004 */
+#define ADC_JSQR_JSQ1_3 (0x08U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000008 */
+#define ADC_JSQR_JSQ1_4 (0x10U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000010 */
+
+#define ADC_JSQR_JSQ2_Pos (5U)
+#define ADC_JSQR_JSQ2_Msk (0x1FU << ADC_JSQR_JSQ2_Pos) /*!< 0x000003E0 */
+#define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!< ADC group injected sequencer rank 2 */
+#define ADC_JSQR_JSQ2_0 (0x01U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000020 */
+#define ADC_JSQR_JSQ2_1 (0x02U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000040 */
+#define ADC_JSQR_JSQ2_2 (0x04U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000080 */
+#define ADC_JSQR_JSQ2_3 (0x08U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000100 */
+#define ADC_JSQR_JSQ2_4 (0x10U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000200 */
+
+#define ADC_JSQR_JSQ3_Pos (10U)
+#define ADC_JSQR_JSQ3_Msk (0x1FU << ADC_JSQR_JSQ3_Pos) /*!< 0x00007C00 */
+#define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!< ADC group injected sequencer rank 3 */
+#define ADC_JSQR_JSQ3_0 (0x01U << ADC_JSQR_JSQ3_Pos) /*!< 0x00000400 */
+#define ADC_JSQR_JSQ3_1 (0x02U << ADC_JSQR_JSQ3_Pos) /*!< 0x00000800 */
+#define ADC_JSQR_JSQ3_2 (0x04U << ADC_JSQR_JSQ3_Pos) /*!< 0x00001000 */
+#define ADC_JSQR_JSQ3_3 (0x08U << ADC_JSQR_JSQ3_Pos) /*!< 0x00002000 */
+#define ADC_JSQR_JSQ3_4 (0x10U << ADC_JSQR_JSQ3_Pos) /*!< 0x00004000 */
+
+#define ADC_JSQR_JSQ4_Pos (15U)
+#define ADC_JSQR_JSQ4_Msk (0x1FU << ADC_JSQR_JSQ4_Pos) /*!< 0x000F8000 */
+#define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!< ADC group injected sequencer rank 4 */
+#define ADC_JSQR_JSQ4_0 (0x01U << ADC_JSQR_JSQ4_Pos) /*!< 0x00008000 */
+#define ADC_JSQR_JSQ4_1 (0x02U << ADC_JSQR_JSQ4_Pos) /*!< 0x00010000 */
+#define ADC_JSQR_JSQ4_2 (0x04U << ADC_JSQR_JSQ4_Pos) /*!< 0x00020000 */
+#define ADC_JSQR_JSQ4_3 (0x08U << ADC_JSQR_JSQ4_Pos) /*!< 0x00040000 */
+#define ADC_JSQR_JSQ4_4 (0x10U << ADC_JSQR_JSQ4_Pos) /*!< 0x00080000 */
+
+#define ADC_JSQR_JL_Pos (20U)
+#define ADC_JSQR_JL_Msk (0x3U << ADC_JSQR_JL_Pos) /*!< 0x00300000 */
+#define ADC_JSQR_JL ADC_JSQR_JL_Msk /*!< ADC group injected sequencer scan length */
+#define ADC_JSQR_JL_0 (0x1U << ADC_JSQR_JL_Pos) /*!< 0x00100000 */
+#define ADC_JSQR_JL_1 (0x2U << ADC_JSQR_JL_Pos) /*!< 0x00200000 */
+
+/******************* Bit definition for ADC_JDR1 register *******************/
+#define ADC_JDR1_JDATA_Pos (0U)
+#define ADC_JDR1_JDATA_Msk (0xFFFFU << ADC_JDR1_JDATA_Pos) /*!< 0x0000FFFF */
+#define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!< ADC group injected sequencer rank 1 conversion data */
+
+/******************* Bit definition for ADC_JDR2 register *******************/
+#define ADC_JDR2_JDATA_Pos (0U)
+#define ADC_JDR2_JDATA_Msk (0xFFFFU << ADC_JDR2_JDATA_Pos) /*!< 0x0000FFFF */
+#define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!< ADC group injected sequencer rank 2 conversion data */
+
+/******************* Bit definition for ADC_JDR3 register *******************/
+#define ADC_JDR3_JDATA_Pos (0U)
+#define ADC_JDR3_JDATA_Msk (0xFFFFU << ADC_JDR3_JDATA_Pos) /*!< 0x0000FFFF */
+#define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!< ADC group injected sequencer rank 3 conversion data */
+
+/******************* Bit definition for ADC_JDR4 register *******************/
+#define ADC_JDR4_JDATA_Pos (0U)
+#define ADC_JDR4_JDATA_Msk (0xFFFFU << ADC_JDR4_JDATA_Pos) /*!< 0x0000FFFF */
+#define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!< ADC group injected sequencer rank 4 conversion data */
+
+/******************** Bit definition for ADC_DR register ********************/
+#define ADC_DR_DATA_Pos (0U)
+#define ADC_DR_DATA_Msk (0xFFFFU << ADC_DR_DATA_Pos) /*!< 0x0000FFFF */
+#define ADC_DR_DATA ADC_DR_DATA_Msk /*!< ADC group regular conversion data */
+
+
+/*****************************************************************************/
+/* */
+/* Timers (TIM) */
+/* */
+/*****************************************************************************/
+/******************* Bit definition for TIM_CR1 register *******************/
+#define TIM_CR1_CEN_Pos (0U)
+#define TIM_CR1_CEN_Msk (0x1U << TIM_CR1_CEN_Pos) /*!< 0x00000001 */
+#define TIM_CR1_CEN TIM_CR1_CEN_Msk /*!<Counter enable */
+#define TIM_CR1_UDIS_Pos (1U)
+#define TIM_CR1_UDIS_Msk (0x1U << TIM_CR1_UDIS_Pos) /*!< 0x00000002 */
+#define TIM_CR1_UDIS TIM_CR1_UDIS_Msk /*!<Update disable */
+#define TIM_CR1_URS_Pos (2U)
+#define TIM_CR1_URS_Msk (0x1U << TIM_CR1_URS_Pos) /*!< 0x00000004 */
+#define TIM_CR1_URS TIM_CR1_URS_Msk /*!<Update request source */
+#define TIM_CR1_OPM_Pos (3U)
+#define TIM_CR1_OPM_Msk (0x1U << TIM_CR1_OPM_Pos) /*!< 0x00000008 */
+#define TIM_CR1_OPM TIM_CR1_OPM_Msk /*!<One pulse mode */
+#define TIM_CR1_DIR_Pos (4U)
+#define TIM_CR1_DIR_Msk (0x1U << TIM_CR1_DIR_Pos) /*!< 0x00000010 */
+#define TIM_CR1_DIR TIM_CR1_DIR_Msk /*!<Direction */
+
+#define TIM_CR1_CMS_Pos (5U)
+#define TIM_CR1_CMS_Msk (0x3U << TIM_CR1_CMS_Pos) /*!< 0x00000060 */
+#define TIM_CR1_CMS TIM_CR1_CMS_Msk /*!<CMS[1:0] bits (Center-aligned mode selection) */
+#define TIM_CR1_CMS_0 (0x1U << TIM_CR1_CMS_Pos) /*!< 0x00000020 */
+#define TIM_CR1_CMS_1 (0x2U << TIM_CR1_CMS_Pos) /*!< 0x00000040 */
+
+#define TIM_CR1_ARPE_Pos (7U)
+#define TIM_CR1_ARPE_Msk (0x1U << TIM_CR1_ARPE_Pos) /*!< 0x00000080 */
+#define TIM_CR1_ARPE TIM_CR1_ARPE_Msk /*!<Auto-reload preload enable */
+
+#define TIM_CR1_CKD_Pos (8U)
+#define TIM_CR1_CKD_Msk (0x3U << TIM_CR1_CKD_Pos) /*!< 0x00000300 */
+#define TIM_CR1_CKD TIM_CR1_CKD_Msk /*!<CKD[1:0] bits (clock division) */
+#define TIM_CR1_CKD_0 (0x1U << TIM_CR1_CKD_Pos) /*!< 0x00000100 */
+#define TIM_CR1_CKD_1 (0x2U << TIM_CR1_CKD_Pos) /*!< 0x00000200 */
+
+/******************* Bit definition for TIM_CR2 register *******************/
+#define TIM_CR2_CCPC_Pos (0U)
+#define TIM_CR2_CCPC_Msk (0x1U << TIM_CR2_CCPC_Pos) /*!< 0x00000001 */
+#define TIM_CR2_CCPC TIM_CR2_CCPC_Msk /*!<Capture/Compare Preloaded Control */
+#define TIM_CR2_CCUS_Pos (2U)
+#define TIM_CR2_CCUS_Msk (0x1U << TIM_CR2_CCUS_Pos) /*!< 0x00000004 */
+#define TIM_CR2_CCUS TIM_CR2_CCUS_Msk /*!<Capture/Compare Control Update Selection */
+#define TIM_CR2_CCDS_Pos (3U)
+#define TIM_CR2_CCDS_Msk (0x1U << TIM_CR2_CCDS_Pos) /*!< 0x00000008 */
+#define TIM_CR2_CCDS TIM_CR2_CCDS_Msk /*!<Capture/Compare DMA Selection */
+
+#define TIM_CR2_MMS_Pos (4U)
+#define TIM_CR2_MMS_Msk (0x7U << TIM_CR2_MMS_Pos) /*!< 0x00000070 */
+#define TIM_CR2_MMS TIM_CR2_MMS_Msk /*!<MMS[2:0] bits (Master Mode Selection) */
+#define TIM_CR2_MMS_0 (0x1U << TIM_CR2_MMS_Pos) /*!< 0x00000010 */
+#define TIM_CR2_MMS_1 (0x2U << TIM_CR2_MMS_Pos) /*!< 0x00000020 */
+#define TIM_CR2_MMS_2 (0x4U << TIM_CR2_MMS_Pos) /*!< 0x00000040 */
+
+#define TIM_CR2_TI1S_Pos (7U)
+#define TIM_CR2_TI1S_Msk (0x1U << TIM_CR2_TI1S_Pos) /*!< 0x00000080 */
+#define TIM_CR2_TI1S TIM_CR2_TI1S_Msk /*!<TI1 Selection */
+#define TIM_CR2_OIS1_Pos (8U)
+#define TIM_CR2_OIS1_Msk (0x1U << TIM_CR2_OIS1_Pos) /*!< 0x00000100 */
+#define TIM_CR2_OIS1 TIM_CR2_OIS1_Msk /*!<Output Idle state 1 (OC1 output) */
+#define TIM_CR2_OIS1N_Pos (9U)
+#define TIM_CR2_OIS1N_Msk (0x1U << TIM_CR2_OIS1N_Pos) /*!< 0x00000200 */
+#define TIM_CR2_OIS1N TIM_CR2_OIS1N_Msk /*!<Output Idle state 1 (OC1N output) */
+#define TIM_CR2_OIS2_Pos (10U)
+#define TIM_CR2_OIS2_Msk (0x1U << TIM_CR2_OIS2_Pos) /*!< 0x00000400 */
+#define TIM_CR2_OIS2 TIM_CR2_OIS2_Msk /*!<Output Idle state 2 (OC2 output) */
+#define TIM_CR2_OIS2N_Pos (11U)
+#define TIM_CR2_OIS2N_Msk (0x1U << TIM_CR2_OIS2N_Pos) /*!< 0x00000800 */
+#define TIM_CR2_OIS2N TIM_CR2_OIS2N_Msk /*!<Output Idle state 2 (OC2N output) */
+#define TIM_CR2_OIS3_Pos (12U)
+#define TIM_CR2_OIS3_Msk (0x1U << TIM_CR2_OIS3_Pos) /*!< 0x00001000 */
+#define TIM_CR2_OIS3 TIM_CR2_OIS3_Msk /*!<Output Idle state 3 (OC3 output) */
+#define TIM_CR2_OIS3N_Pos (13U)
+#define TIM_CR2_OIS3N_Msk (0x1U << TIM_CR2_OIS3N_Pos) /*!< 0x00002000 */
+#define TIM_CR2_OIS3N TIM_CR2_OIS3N_Msk /*!<Output Idle state 3 (OC3N output) */
+#define TIM_CR2_OIS4_Pos (14U)
+#define TIM_CR2_OIS4_Msk (0x1U << TIM_CR2_OIS4_Pos) /*!< 0x00004000 */
+#define TIM_CR2_OIS4 TIM_CR2_OIS4_Msk /*!<Output Idle state 4 (OC4 output) */
+
+/******************* Bit definition for TIM_SMCR register ******************/
+#define TIM_SMCR_SMS_Pos (0U)
+#define TIM_SMCR_SMS_Msk (0x7U << TIM_SMCR_SMS_Pos) /*!< 0x00000007 */
+#define TIM_SMCR_SMS TIM_SMCR_SMS_Msk /*!<SMS[2:0] bits (Slave mode selection) */
+#define TIM_SMCR_SMS_0 (0x1U << TIM_SMCR_SMS_Pos) /*!< 0x00000001 */
+#define TIM_SMCR_SMS_1 (0x2U << TIM_SMCR_SMS_Pos) /*!< 0x00000002 */
+#define TIM_SMCR_SMS_2 (0x4U << TIM_SMCR_SMS_Pos) /*!< 0x00000004 */
+
+#define TIM_SMCR_OCCS_Pos (3U)
+#define TIM_SMCR_OCCS_Msk (0x1U << TIM_SMCR_OCCS_Pos) /*!< 0x00000008 */
+#define TIM_SMCR_OCCS TIM_SMCR_OCCS_Msk /*!< OCREF clear selection */
+
+#define TIM_SMCR_TS_Pos (4U)
+#define TIM_SMCR_TS_Msk (0x7U << TIM_SMCR_TS_Pos) /*!< 0x00000070 */
+#define TIM_SMCR_TS TIM_SMCR_TS_Msk /*!<TS[2:0] bits (Trigger selection) */
+#define TIM_SMCR_TS_0 (0x1U << TIM_SMCR_TS_Pos) /*!< 0x00000010 */
+#define TIM_SMCR_TS_1 (0x2U << TIM_SMCR_TS_Pos) /*!< 0x00000020 */
+#define TIM_SMCR_TS_2 (0x4U << TIM_SMCR_TS_Pos) /*!< 0x00000040 */
+
+#define TIM_SMCR_MSM_Pos (7U)
+#define TIM_SMCR_MSM_Msk (0x1U << TIM_SMCR_MSM_Pos) /*!< 0x00000080 */
+#define TIM_SMCR_MSM TIM_SMCR_MSM_Msk /*!<Master/slave mode */
+
+#define TIM_SMCR_ETF_Pos (8U)
+#define TIM_SMCR_ETF_Msk (0xFU << TIM_SMCR_ETF_Pos) /*!< 0x00000F00 */
+#define TIM_SMCR_ETF TIM_SMCR_ETF_Msk /*!<ETF[3:0] bits (External trigger filter) */
+#define TIM_SMCR_ETF_0 (0x1U << TIM_SMCR_ETF_Pos) /*!< 0x00000100 */
+#define TIM_SMCR_ETF_1 (0x2U << TIM_SMCR_ETF_Pos) /*!< 0x00000200 */
+#define TIM_SMCR_ETF_2 (0x4U << TIM_SMCR_ETF_Pos) /*!< 0x00000400 */
+#define TIM_SMCR_ETF_3 (0x8U << TIM_SMCR_ETF_Pos) /*!< 0x00000800 */
+
+#define TIM_SMCR_ETPS_Pos (12U)
+#define TIM_SMCR_ETPS_Msk (0x3U << TIM_SMCR_ETPS_Pos) /*!< 0x00003000 */
+#define TIM_SMCR_ETPS TIM_SMCR_ETPS_Msk /*!<ETPS[1:0] bits (External trigger prescaler) */
+#define TIM_SMCR_ETPS_0 (0x1U << TIM_SMCR_ETPS_Pos) /*!< 0x00001000 */
+#define TIM_SMCR_ETPS_1 (0x2U << TIM_SMCR_ETPS_Pos) /*!< 0x00002000 */
+
+#define TIM_SMCR_ECE_Pos (14U)
+#define TIM_SMCR_ECE_Msk (0x1U << TIM_SMCR_ECE_Pos) /*!< 0x00004000 */
+#define TIM_SMCR_ECE TIM_SMCR_ECE_Msk /*!<External clock enable */
+#define TIM_SMCR_ETP_Pos (15U)
+#define TIM_SMCR_ETP_Msk (0x1U << TIM_SMCR_ETP_Pos) /*!< 0x00008000 */
+#define TIM_SMCR_ETP TIM_SMCR_ETP_Msk /*!<External trigger polarity */
+
+/******************* Bit definition for TIM_DIER register ******************/
+#define TIM_DIER_UIE_Pos (0U)
+#define TIM_DIER_UIE_Msk (0x1U << TIM_DIER_UIE_Pos) /*!< 0x00000001 */
+#define TIM_DIER_UIE TIM_DIER_UIE_Msk /*!<Update interrupt enable */
+#define TIM_DIER_CC1IE_Pos (1U)
+#define TIM_DIER_CC1IE_Msk (0x1U << TIM_DIER_CC1IE_Pos) /*!< 0x00000002 */
+#define TIM_DIER_CC1IE TIM_DIER_CC1IE_Msk /*!<Capture/Compare 1 interrupt enable */
+#define TIM_DIER_CC2IE_Pos (2U)
+#define TIM_DIER_CC2IE_Msk (0x1U << TIM_DIER_CC2IE_Pos) /*!< 0x00000004 */
+#define TIM_DIER_CC2IE TIM_DIER_CC2IE_Msk /*!<Capture/Compare 2 interrupt enable */
+#define TIM_DIER_CC3IE_Pos (3U)
+#define TIM_DIER_CC3IE_Msk (0x1U << TIM_DIER_CC3IE_Pos) /*!< 0x00000008 */
+#define TIM_DIER_CC3IE TIM_DIER_CC3IE_Msk /*!<Capture/Compare 3 interrupt enable */
+#define TIM_DIER_CC4IE_Pos (4U)
+#define TIM_DIER_CC4IE_Msk (0x1U << TIM_DIER_CC4IE_Pos) /*!< 0x00000010 */
+#define TIM_DIER_CC4IE TIM_DIER_CC4IE_Msk /*!<Capture/Compare 4 interrupt enable */
+#define TIM_DIER_COMIE_Pos (5U)
+#define TIM_DIER_COMIE_Msk (0x1U << TIM_DIER_COMIE_Pos) /*!< 0x00000020 */
+#define TIM_DIER_COMIE TIM_DIER_COMIE_Msk /*!<COM interrupt enable */
+#define TIM_DIER_TIE_Pos (6U)
+#define TIM_DIER_TIE_Msk (0x1U << TIM_DIER_TIE_Pos) /*!< 0x00000040 */
+#define TIM_DIER_TIE TIM_DIER_TIE_Msk /*!<Trigger interrupt enable */
+#define TIM_DIER_BIE_Pos (7U)
+#define TIM_DIER_BIE_Msk (0x1U << TIM_DIER_BIE_Pos) /*!< 0x00000080 */
+#define TIM_DIER_BIE TIM_DIER_BIE_Msk /*!<Break interrupt enable */
+#define TIM_DIER_UDE_Pos (8U)
+#define TIM_DIER_UDE_Msk (0x1U << TIM_DIER_UDE_Pos) /*!< 0x00000100 */
+#define TIM_DIER_UDE TIM_DIER_UDE_Msk /*!<Update DMA request enable */
+#define TIM_DIER_CC1DE_Pos (9U)
+#define TIM_DIER_CC1DE_Msk (0x1U << TIM_DIER_CC1DE_Pos) /*!< 0x00000200 */
+#define TIM_DIER_CC1DE TIM_DIER_CC1DE_Msk /*!<Capture/Compare 1 DMA request enable */
+#define TIM_DIER_CC2DE_Pos (10U)
+#define TIM_DIER_CC2DE_Msk (0x1U << TIM_DIER_CC2DE_Pos) /*!< 0x00000400 */
+#define TIM_DIER_CC2DE TIM_DIER_CC2DE_Msk /*!<Capture/Compare 2 DMA request enable */
+#define TIM_DIER_CC3DE_Pos (11U)
+#define TIM_DIER_CC3DE_Msk (0x1U << TIM_DIER_CC3DE_Pos) /*!< 0x00000800 */
+#define TIM_DIER_CC3DE TIM_DIER_CC3DE_Msk /*!<Capture/Compare 3 DMA request enable */
+#define TIM_DIER_CC4DE_Pos (12U)
+#define TIM_DIER_CC4DE_Msk (0x1U << TIM_DIER_CC4DE_Pos) /*!< 0x00001000 */
+#define TIM_DIER_CC4DE TIM_DIER_CC4DE_Msk /*!<Capture/Compare 4 DMA request enable */
+#define TIM_DIER_COMDE_Pos (13U)
+#define TIM_DIER_COMDE_Msk (0x1U << TIM_DIER_COMDE_Pos) /*!< 0x00002000 */
+#define TIM_DIER_COMDE TIM_DIER_COMDE_Msk /*!<COM DMA request enable */
+#define TIM_DIER_TDE_Pos (14U)
+#define TIM_DIER_TDE_Msk (0x1U << TIM_DIER_TDE_Pos) /*!< 0x00004000 */
+#define TIM_DIER_TDE TIM_DIER_TDE_Msk /*!<Trigger DMA request enable */
+
+/******************** Bit definition for TIM_SR register *******************/
+#define TIM_SR_UIF_Pos (0U)
+#define TIM_SR_UIF_Msk (0x1U << TIM_SR_UIF_Pos) /*!< 0x00000001 */
+#define TIM_SR_UIF TIM_SR_UIF_Msk /*!<Update interrupt Flag */
+#define TIM_SR_CC1IF_Pos (1U)
+#define TIM_SR_CC1IF_Msk (0x1U << TIM_SR_CC1IF_Pos) /*!< 0x00000002 */
+#define TIM_SR_CC1IF TIM_SR_CC1IF_Msk /*!<Capture/Compare 1 interrupt Flag */
+#define TIM_SR_CC2IF_Pos (2U)
+#define TIM_SR_CC2IF_Msk (0x1U << TIM_SR_CC2IF_Pos) /*!< 0x00000004 */
+#define TIM_SR_CC2IF TIM_SR_CC2IF_Msk /*!<Capture/Compare 2 interrupt Flag */
+#define TIM_SR_CC3IF_Pos (3U)
+#define TIM_SR_CC3IF_Msk (0x1U << TIM_SR_CC3IF_Pos) /*!< 0x00000008 */
+#define TIM_SR_CC3IF TIM_SR_CC3IF_Msk /*!<Capture/Compare 3 interrupt Flag */
+#define TIM_SR_CC4IF_Pos (4U)
+#define TIM_SR_CC4IF_Msk (0x1U << TIM_SR_CC4IF_Pos) /*!< 0x00000010 */
+#define TIM_SR_CC4IF TIM_SR_CC4IF_Msk /*!<Capture/Compare 4 interrupt Flag */
+#define TIM_SR_COMIF_Pos (5U)
+#define TIM_SR_COMIF_Msk (0x1U << TIM_SR_COMIF_Pos) /*!< 0x00000020 */
+#define TIM_SR_COMIF TIM_SR_COMIF_Msk /*!<COM interrupt Flag */
+#define TIM_SR_TIF_Pos (6U)
+#define TIM_SR_TIF_Msk (0x1U << TIM_SR_TIF_Pos) /*!< 0x00000040 */
+#define TIM_SR_TIF TIM_SR_TIF_Msk /*!<Trigger interrupt Flag */
+#define TIM_SR_BIF_Pos (7U)
+#define TIM_SR_BIF_Msk (0x1U << TIM_SR_BIF_Pos) /*!< 0x00000080 */
+#define TIM_SR_BIF TIM_SR_BIF_Msk /*!<Break interrupt Flag */
+#define TIM_SR_CC1OF_Pos (9U)
+#define TIM_SR_CC1OF_Msk (0x1U << TIM_SR_CC1OF_Pos) /*!< 0x00000200 */
+#define TIM_SR_CC1OF TIM_SR_CC1OF_Msk /*!<Capture/Compare 1 Overcapture Flag */
+#define TIM_SR_CC2OF_Pos (10U)
+#define TIM_SR_CC2OF_Msk (0x1U << TIM_SR_CC2OF_Pos) /*!< 0x00000400 */
+#define TIM_SR_CC2OF TIM_SR_CC2OF_Msk /*!<Capture/Compare 2 Overcapture Flag */
+#define TIM_SR_CC3OF_Pos (11U)
+#define TIM_SR_CC3OF_Msk (0x1U << TIM_SR_CC3OF_Pos) /*!< 0x00000800 */
+#define TIM_SR_CC3OF TIM_SR_CC3OF_Msk /*!<Capture/Compare 3 Overcapture Flag */
+#define TIM_SR_CC4OF_Pos (12U)
+#define TIM_SR_CC4OF_Msk (0x1U << TIM_SR_CC4OF_Pos) /*!< 0x00001000 */
+#define TIM_SR_CC4OF TIM_SR_CC4OF_Msk /*!<Capture/Compare 4 Overcapture Flag */
+
+/******************* Bit definition for TIM_EGR register *******************/
+#define TIM_EGR_UG_Pos (0U)
+#define TIM_EGR_UG_Msk (0x1U << TIM_EGR_UG_Pos) /*!< 0x00000001 */
+#define TIM_EGR_UG TIM_EGR_UG_Msk /*!<Update Generation */
+#define TIM_EGR_CC1G_Pos (1U)
+#define TIM_EGR_CC1G_Msk (0x1U << TIM_EGR_CC1G_Pos) /*!< 0x00000002 */
+#define TIM_EGR_CC1G TIM_EGR_CC1G_Msk /*!<Capture/Compare 1 Generation */
+#define TIM_EGR_CC2G_Pos (2U)
+#define TIM_EGR_CC2G_Msk (0x1U << TIM_EGR_CC2G_Pos) /*!< 0x00000004 */
+#define TIM_EGR_CC2G TIM_EGR_CC2G_Msk /*!<Capture/Compare 2 Generation */
+#define TIM_EGR_CC3G_Pos (3U)
+#define TIM_EGR_CC3G_Msk (0x1U << TIM_EGR_CC3G_Pos) /*!< 0x00000008 */
+#define TIM_EGR_CC3G TIM_EGR_CC3G_Msk /*!<Capture/Compare 3 Generation */
+#define TIM_EGR_CC4G_Pos (4U)
+#define TIM_EGR_CC4G_Msk (0x1U << TIM_EGR_CC4G_Pos) /*!< 0x00000010 */
+#define TIM_EGR_CC4G TIM_EGR_CC4G_Msk /*!<Capture/Compare 4 Generation */
+#define TIM_EGR_COMG_Pos (5U)
+#define TIM_EGR_COMG_Msk (0x1U << TIM_EGR_COMG_Pos) /*!< 0x00000020 */
+#define TIM_EGR_COMG TIM_EGR_COMG_Msk /*!<Capture/Compare Control Update Generation */
+#define TIM_EGR_TG_Pos (6U)
+#define TIM_EGR_TG_Msk (0x1U << TIM_EGR_TG_Pos) /*!< 0x00000040 */
+#define TIM_EGR_TG TIM_EGR_TG_Msk /*!<Trigger Generation */
+#define TIM_EGR_BG_Pos (7U)
+#define TIM_EGR_BG_Msk (0x1U << TIM_EGR_BG_Pos) /*!< 0x00000080 */
+#define TIM_EGR_BG TIM_EGR_BG_Msk /*!<Break Generation */
+
+/****************** Bit definition for TIM_CCMR1 register ******************/
+#define TIM_CCMR1_CC1S_Pos (0U)
+#define TIM_CCMR1_CC1S_Msk (0x3U << TIM_CCMR1_CC1S_Pos) /*!< 0x00000003 */
+#define TIM_CCMR1_CC1S TIM_CCMR1_CC1S_Msk /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
+#define TIM_CCMR1_CC1S_0 (0x1U << TIM_CCMR1_CC1S_Pos) /*!< 0x00000001 */
+#define TIM_CCMR1_CC1S_1 (0x2U << TIM_CCMR1_CC1S_Pos) /*!< 0x00000002 */
+
+#define TIM_CCMR1_OC1FE_Pos (2U)
+#define TIM_CCMR1_OC1FE_Msk (0x1U << TIM_CCMR1_OC1FE_Pos) /*!< 0x00000004 */
+#define TIM_CCMR1_OC1FE TIM_CCMR1_OC1FE_Msk /*!<Output Compare 1 Fast enable */
+#define TIM_CCMR1_OC1PE_Pos (3U)
+#define TIM_CCMR1_OC1PE_Msk (0x1U << TIM_CCMR1_OC1PE_Pos) /*!< 0x00000008 */
+#define TIM_CCMR1_OC1PE TIM_CCMR1_OC1PE_Msk /*!<Output Compare 1 Preload enable */
+
+#define TIM_CCMR1_OC1M_Pos (4U)
+#define TIM_CCMR1_OC1M_Msk (0x7U << TIM_CCMR1_OC1M_Pos) /*!< 0x00000070 */
+#define TIM_CCMR1_OC1M TIM_CCMR1_OC1M_Msk /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
+#define TIM_CCMR1_OC1M_0 (0x1U << TIM_CCMR1_OC1M_Pos) /*!< 0x00000010 */
+#define TIM_CCMR1_OC1M_1 (0x2U << TIM_CCMR1_OC1M_Pos) /*!< 0x00000020 */
+#define TIM_CCMR1_OC1M_2 (0x4U << TIM_CCMR1_OC1M_Pos) /*!< 0x00000040 */
+
+#define TIM_CCMR1_OC1CE_Pos (7U)
+#define TIM_CCMR1_OC1CE_Msk (0x1U << TIM_CCMR1_OC1CE_Pos) /*!< 0x00000080 */
+#define TIM_CCMR1_OC1CE TIM_CCMR1_OC1CE_Msk /*!<Output Compare 1Clear Enable */
+
+#define TIM_CCMR1_CC2S_Pos (8U)
+#define TIM_CCMR1_CC2S_Msk (0x3U << TIM_CCMR1_CC2S_Pos) /*!< 0x00000300 */
+#define TIM_CCMR1_CC2S TIM_CCMR1_CC2S_Msk /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
+#define TIM_CCMR1_CC2S_0 (0x1U << TIM_CCMR1_CC2S_Pos) /*!< 0x00000100 */
+#define TIM_CCMR1_CC2S_1 (0x2U << TIM_CCMR1_CC2S_Pos) /*!< 0x00000200 */
+
+#define TIM_CCMR1_OC2FE_Pos (10U)
+#define TIM_CCMR1_OC2FE_Msk (0x1U << TIM_CCMR1_OC2FE_Pos) /*!< 0x00000400 */
+#define TIM_CCMR1_OC2FE TIM_CCMR1_OC2FE_Msk /*!<Output Compare 2 Fast enable */
+#define TIM_CCMR1_OC2PE_Pos (11U)
+#define TIM_CCMR1_OC2PE_Msk (0x1U << TIM_CCMR1_OC2PE_Pos) /*!< 0x00000800 */
+#define TIM_CCMR1_OC2PE TIM_CCMR1_OC2PE_Msk /*!<Output Compare 2 Preload enable */
+
+#define TIM_CCMR1_OC2M_Pos (12U)
+#define TIM_CCMR1_OC2M_Msk (0x7U << TIM_CCMR1_OC2M_Pos) /*!< 0x00007000 */
+#define TIM_CCMR1_OC2M TIM_CCMR1_OC2M_Msk /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
+#define TIM_CCMR1_OC2M_0 (0x1U << TIM_CCMR1_OC2M_Pos) /*!< 0x00001000 */
+#define TIM_CCMR1_OC2M_1 (0x2U << TIM_CCMR1_OC2M_Pos) /*!< 0x00002000 */
+#define TIM_CCMR1_OC2M_2 (0x4U << TIM_CCMR1_OC2M_Pos) /*!< 0x00004000 */
+
+#define TIM_CCMR1_OC2CE_Pos (15U)
+#define TIM_CCMR1_OC2CE_Msk (0x1U << TIM_CCMR1_OC2CE_Pos) /*!< 0x00008000 */
+#define TIM_CCMR1_OC2CE TIM_CCMR1_OC2CE_Msk /*!<Output Compare 2 Clear Enable */
+
+/*---------------------------------------------------------------------------*/
+
+#define TIM_CCMR1_IC1PSC_Pos (2U)
+#define TIM_CCMR1_IC1PSC_Msk (0x3U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x0000000C */
+#define TIM_CCMR1_IC1PSC TIM_CCMR1_IC1PSC_Msk /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
+#define TIM_CCMR1_IC1PSC_0 (0x1U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x00000004 */
+#define TIM_CCMR1_IC1PSC_1 (0x2U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x00000008 */
+
+#define TIM_CCMR1_IC1F_Pos (4U)
+#define TIM_CCMR1_IC1F_Msk (0xFU << TIM_CCMR1_IC1F_Pos) /*!< 0x000000F0 */
+#define TIM_CCMR1_IC1F TIM_CCMR1_IC1F_Msk /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
+#define TIM_CCMR1_IC1F_0 (0x1U << TIM_CCMR1_IC1F_Pos) /*!< 0x00000010 */
+#define TIM_CCMR1_IC1F_1 (0x2U << TIM_CCMR1_IC1F_Pos) /*!< 0x00000020 */
+#define TIM_CCMR1_IC1F_2 (0x4U << TIM_CCMR1_IC1F_Pos) /*!< 0x00000040 */
+#define TIM_CCMR1_IC1F_3 (0x8U << TIM_CCMR1_IC1F_Pos) /*!< 0x00000080 */
+
+#define TIM_CCMR1_IC2PSC_Pos (10U)
+#define TIM_CCMR1_IC2PSC_Msk (0x3U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000C00 */
+#define TIM_CCMR1_IC2PSC TIM_CCMR1_IC2PSC_Msk /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
+#define TIM_CCMR1_IC2PSC_0 (0x1U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000400 */
+#define TIM_CCMR1_IC2PSC_1 (0x2U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000800 */
+
+#define TIM_CCMR1_IC2F_Pos (12U)
+#define TIM_CCMR1_IC2F_Msk (0xFU << TIM_CCMR1_IC2F_Pos) /*!< 0x0000F000 */
+#define TIM_CCMR1_IC2F TIM_CCMR1_IC2F_Msk /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
+#define TIM_CCMR1_IC2F_0 (0x1U << TIM_CCMR1_IC2F_Pos) /*!< 0x00001000 */
+#define TIM_CCMR1_IC2F_1 (0x2U << TIM_CCMR1_IC2F_Pos) /*!< 0x00002000 */
+#define TIM_CCMR1_IC2F_2 (0x4U << TIM_CCMR1_IC2F_Pos) /*!< 0x00004000 */
+#define TIM_CCMR1_IC2F_3 (0x8U << TIM_CCMR1_IC2F_Pos) /*!< 0x00008000 */
+
+/****************** Bit definition for TIM_CCMR2 register ******************/
+#define TIM_CCMR2_CC3S_Pos (0U)
+#define TIM_CCMR2_CC3S_Msk (0x3U << TIM_CCMR2_CC3S_Pos) /*!< 0x00000003 */
+#define TIM_CCMR2_CC3S TIM_CCMR2_CC3S_Msk /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
+#define TIM_CCMR2_CC3S_0 (0x1U << TIM_CCMR2_CC3S_Pos) /*!< 0x00000001 */
+#define TIM_CCMR2_CC3S_1 (0x2U << TIM_CCMR2_CC3S_Pos) /*!< 0x00000002 */
+
+#define TIM_CCMR2_OC3FE_Pos (2U)
+#define TIM_CCMR2_OC3FE_Msk (0x1U << TIM_CCMR2_OC3FE_Pos) /*!< 0x00000004 */
+#define TIM_CCMR2_OC3FE TIM_CCMR2_OC3FE_Msk /*!<Output Compare 3 Fast enable */
+#define TIM_CCMR2_OC3PE_Pos (3U)
+#define TIM_CCMR2_OC3PE_Msk (0x1U << TIM_CCMR2_OC3PE_Pos) /*!< 0x00000008 */
+#define TIM_CCMR2_OC3PE TIM_CCMR2_OC3PE_Msk /*!<Output Compare 3 Preload enable */
+
+#define TIM_CCMR2_OC3M_Pos (4U)
+#define TIM_CCMR2_OC3M_Msk (0x7U << TIM_CCMR2_OC3M_Pos) /*!< 0x00000070 */
+#define TIM_CCMR2_OC3M TIM_CCMR2_OC3M_Msk /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
+#define TIM_CCMR2_OC3M_0 (0x1U << TIM_CCMR2_OC3M_Pos) /*!< 0x00000010 */
+#define TIM_CCMR2_OC3M_1 (0x2U << TIM_CCMR2_OC3M_Pos) /*!< 0x00000020 */
+#define TIM_CCMR2_OC3M_2 (0x4U << TIM_CCMR2_OC3M_Pos) /*!< 0x00000040 */
+
+#define TIM_CCMR2_OC3CE_Pos (7U)
+#define TIM_CCMR2_OC3CE_Msk (0x1U << TIM_CCMR2_OC3CE_Pos) /*!< 0x00000080 */
+#define TIM_CCMR2_OC3CE TIM_CCMR2_OC3CE_Msk /*!<Output Compare 3 Clear Enable */
+
+#define TIM_CCMR2_CC4S_Pos (8U)
+#define TIM_CCMR2_CC4S_Msk (0x3U << TIM_CCMR2_CC4S_Pos) /*!< 0x00000300 */
+#define TIM_CCMR2_CC4S TIM_CCMR2_CC4S_Msk /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
+#define TIM_CCMR2_CC4S_0 (0x1U << TIM_CCMR2_CC4S_Pos) /*!< 0x00000100 */
+#define TIM_CCMR2_CC4S_1 (0x2U << TIM_CCMR2_CC4S_Pos) /*!< 0x00000200 */
+
+#define TIM_CCMR2_OC4FE_Pos (10U)
+#define TIM_CCMR2_OC4FE_Msk (0x1U << TIM_CCMR2_OC4FE_Pos) /*!< 0x00000400 */
+#define TIM_CCMR2_OC4FE TIM_CCMR2_OC4FE_Msk /*!<Output Compare 4 Fast enable */
+#define TIM_CCMR2_OC4PE_Pos (11U)
+#define TIM_CCMR2_OC4PE_Msk (0x1U << TIM_CCMR2_OC4PE_Pos) /*!< 0x00000800 */
+#define TIM_CCMR2_OC4PE TIM_CCMR2_OC4PE_Msk /*!<Output Compare 4 Preload enable */
+
+#define TIM_CCMR2_OC4M_Pos (12U)
+#define TIM_CCMR2_OC4M_Msk (0x7U << TIM_CCMR2_OC4M_Pos) /*!< 0x00007000 */
+#define TIM_CCMR2_OC4M TIM_CCMR2_OC4M_Msk /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
+#define TIM_CCMR2_OC4M_0 (0x1U << TIM_CCMR2_OC4M_Pos) /*!< 0x00001000 */
+#define TIM_CCMR2_OC4M_1 (0x2U << TIM_CCMR2_OC4M_Pos) /*!< 0x00002000 */
+#define TIM_CCMR2_OC4M_2 (0x4U << TIM_CCMR2_OC4M_Pos) /*!< 0x00004000 */
+
+#define TIM_CCMR2_OC4CE_Pos (15U)
+#define TIM_CCMR2_OC4CE_Msk (0x1U << TIM_CCMR2_OC4CE_Pos) /*!< 0x00008000 */
+#define TIM_CCMR2_OC4CE TIM_CCMR2_OC4CE_Msk /*!<Output Compare 4 Clear Enable */
+
+/*---------------------------------------------------------------------------*/
+
+#define TIM_CCMR2_IC3PSC_Pos (2U)
+#define TIM_CCMR2_IC3PSC_Msk (0x3U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x0000000C */
+#define TIM_CCMR2_IC3PSC TIM_CCMR2_IC3PSC_Msk /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
+#define TIM_CCMR2_IC3PSC_0 (0x1U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x00000004 */
+#define TIM_CCMR2_IC3PSC_1 (0x2U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x00000008 */
+
+#define TIM_CCMR2_IC3F_Pos (4U)
+#define TIM_CCMR2_IC3F_Msk (0xFU << TIM_CCMR2_IC3F_Pos) /*!< 0x000000F0 */
+#define TIM_CCMR2_IC3F TIM_CCMR2_IC3F_Msk /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
+#define TIM_CCMR2_IC3F_0 (0x1U << TIM_CCMR2_IC3F_Pos) /*!< 0x00000010 */
+#define TIM_CCMR2_IC3F_1 (0x2U << TIM_CCMR2_IC3F_Pos) /*!< 0x00000020 */
+#define TIM_CCMR2_IC3F_2 (0x4U << TIM_CCMR2_IC3F_Pos) /*!< 0x00000040 */
+#define TIM_CCMR2_IC3F_3 (0x8U << TIM_CCMR2_IC3F_Pos) /*!< 0x00000080 */
+
+#define TIM_CCMR2_IC4PSC_Pos (10U)
+#define TIM_CCMR2_IC4PSC_Msk (0x3U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000C00 */
+#define TIM_CCMR2_IC4PSC TIM_CCMR2_IC4PSC_Msk /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
+#define TIM_CCMR2_IC4PSC_0 (0x1U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000400 */
+#define TIM_CCMR2_IC4PSC_1 (0x2U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000800 */
+
+#define TIM_CCMR2_IC4F_Pos (12U)
+#define TIM_CCMR2_IC4F_Msk (0xFU << TIM_CCMR2_IC4F_Pos) /*!< 0x0000F000 */
+#define TIM_CCMR2_IC4F TIM_CCMR2_IC4F_Msk /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
+#define TIM_CCMR2_IC4F_0 (0x1U << TIM_CCMR2_IC4F_Pos) /*!< 0x00001000 */
+#define TIM_CCMR2_IC4F_1 (0x2U << TIM_CCMR2_IC4F_Pos) /*!< 0x00002000 */
+#define TIM_CCMR2_IC4F_2 (0x4U << TIM_CCMR2_IC4F_Pos) /*!< 0x00004000 */
+#define TIM_CCMR2_IC4F_3 (0x8U << TIM_CCMR2_IC4F_Pos) /*!< 0x00008000 */
+
+/******************* Bit definition for TIM_CCER register ******************/
+#define TIM_CCER_CC1E_Pos (0U)
+#define TIM_CCER_CC1E_Msk (0x1U << TIM_CCER_CC1E_Pos) /*!< 0x00000001 */
+#define TIM_CCER_CC1E TIM_CCER_CC1E_Msk /*!<Capture/Compare 1 output enable */
+#define TIM_CCER_CC1P_Pos (1U)
+#define TIM_CCER_CC1P_Msk (0x1U << TIM_CCER_CC1P_Pos) /*!< 0x00000002 */
+#define TIM_CCER_CC1P TIM_CCER_CC1P_Msk /*!<Capture/Compare 1 output Polarity */
+#define TIM_CCER_CC1NE_Pos (2U)
+#define TIM_CCER_CC1NE_Msk (0x1U << TIM_CCER_CC1NE_Pos) /*!< 0x00000004 */
+#define TIM_CCER_CC1NE TIM_CCER_CC1NE_Msk /*!<Capture/Compare 1 Complementary output enable */
+#define TIM_CCER_CC1NP_Pos (3U)
+#define TIM_CCER_CC1NP_Msk (0x1U << TIM_CCER_CC1NP_Pos) /*!< 0x00000008 */
+#define TIM_CCER_CC1NP TIM_CCER_CC1NP_Msk /*!<Capture/Compare 1 Complementary output Polarity */
+#define TIM_CCER_CC2E_Pos (4U)
+#define TIM_CCER_CC2E_Msk (0x1U << TIM_CCER_CC2E_Pos) /*!< 0x00000010 */
+#define TIM_CCER_CC2E TIM_CCER_CC2E_Msk /*!<Capture/Compare 2 output enable */
+#define TIM_CCER_CC2P_Pos (5U)
+#define TIM_CCER_CC2P_Msk (0x1U << TIM_CCER_CC2P_Pos) /*!< 0x00000020 */
+#define TIM_CCER_CC2P TIM_CCER_CC2P_Msk /*!<Capture/Compare 2 output Polarity */
+#define TIM_CCER_CC2NE_Pos (6U)
+#define TIM_CCER_CC2NE_Msk (0x1U << TIM_CCER_CC2NE_Pos) /*!< 0x00000040 */
+#define TIM_CCER_CC2NE TIM_CCER_CC2NE_Msk /*!<Capture/Compare 2 Complementary output enable */
+#define TIM_CCER_CC2NP_Pos (7U)
+#define TIM_CCER_CC2NP_Msk (0x1U << TIM_CCER_CC2NP_Pos) /*!< 0x00000080 */
+#define TIM_CCER_CC2NP TIM_CCER_CC2NP_Msk /*!<Capture/Compare 2 Complementary output Polarity */
+#define TIM_CCER_CC3E_Pos (8U)
+#define TIM_CCER_CC3E_Msk (0x1U << TIM_CCER_CC3E_Pos) /*!< 0x00000100 */
+#define TIM_CCER_CC3E TIM_CCER_CC3E_Msk /*!<Capture/Compare 3 output enable */
+#define TIM_CCER_CC3P_Pos (9U)
+#define TIM_CCER_CC3P_Msk (0x1U << TIM_CCER_CC3P_Pos) /*!< 0x00000200 */
+#define TIM_CCER_CC3P TIM_CCER_CC3P_Msk /*!<Capture/Compare 3 output Polarity */
+#define TIM_CCER_CC3NE_Pos (10U)
+#define TIM_CCER_CC3NE_Msk (0x1U << TIM_CCER_CC3NE_Pos) /*!< 0x00000400 */
+#define TIM_CCER_CC3NE TIM_CCER_CC3NE_Msk /*!<Capture/Compare 3 Complementary output enable */
+#define TIM_CCER_CC3NP_Pos (11U)
+#define TIM_CCER_CC3NP_Msk (0x1U << TIM_CCER_CC3NP_Pos) /*!< 0x00000800 */
+#define TIM_CCER_CC3NP TIM_CCER_CC3NP_Msk /*!<Capture/Compare 3 Complementary output Polarity */
+#define TIM_CCER_CC4E_Pos (12U)
+#define TIM_CCER_CC4E_Msk (0x1U << TIM_CCER_CC4E_Pos) /*!< 0x00001000 */
+#define TIM_CCER_CC4E TIM_CCER_CC4E_Msk /*!<Capture/Compare 4 output enable */
+#define TIM_CCER_CC4P_Pos (13U)
+#define TIM_CCER_CC4P_Msk (0x1U << TIM_CCER_CC4P_Pos) /*!< 0x00002000 */
+#define TIM_CCER_CC4P TIM_CCER_CC4P_Msk /*!<Capture/Compare 4 output Polarity */
+#define TIM_CCER_CC4NP_Pos (15U)
+#define TIM_CCER_CC4NP_Msk (0x1U << TIM_CCER_CC4NP_Pos) /*!< 0x00008000 */
+#define TIM_CCER_CC4NP TIM_CCER_CC4NP_Msk /*!<Capture/Compare 4 Complementary output Polarity */
+
+/******************* Bit definition for TIM_CNT register *******************/
+#define TIM_CNT_CNT_Pos (0U)
+#define TIM_CNT_CNT_Msk (0xFFFFFFFFU << TIM_CNT_CNT_Pos) /*!< 0xFFFFFFFF */
+#define TIM_CNT_CNT TIM_CNT_CNT_Msk /*!<Counter Value */
+
+/******************* Bit definition for TIM_PSC register *******************/
+#define TIM_PSC_PSC_Pos (0U)
+#define TIM_PSC_PSC_Msk (0xFFFFU << TIM_PSC_PSC_Pos) /*!< 0x0000FFFF */
+#define TIM_PSC_PSC TIM_PSC_PSC_Msk /*!<Prescaler Value */
+
+/******************* Bit definition for TIM_ARR register *******************/
+#define TIM_ARR_ARR_Pos (0U)
+#define TIM_ARR_ARR_Msk (0xFFFFFFFFU << TIM_ARR_ARR_Pos) /*!< 0xFFFFFFFF */
+#define TIM_ARR_ARR TIM_ARR_ARR_Msk /*!<actual auto-reload Value */
+
+/******************* Bit definition for TIM_RCR register *******************/
+#define TIM_RCR_REP_Pos (0U)
+#define TIM_RCR_REP_Msk (0xFFU << TIM_RCR_REP_Pos) /*!< 0x000000FF */
+#define TIM_RCR_REP TIM_RCR_REP_Msk /*!<Repetition Counter Value */
+
+/******************* Bit definition for TIM_CCR1 register ******************/
+#define TIM_CCR1_CCR1_Pos (0U)
+#define TIM_CCR1_CCR1_Msk (0xFFFFU << TIM_CCR1_CCR1_Pos) /*!< 0x0000FFFF */
+#define TIM_CCR1_CCR1 TIM_CCR1_CCR1_Msk /*!<Capture/Compare 1 Value */
+
+/******************* Bit definition for TIM_CCR2 register ******************/
+#define TIM_CCR2_CCR2_Pos (0U)
+#define TIM_CCR2_CCR2_Msk (0xFFFFU << TIM_CCR2_CCR2_Pos) /*!< 0x0000FFFF */
+#define TIM_CCR2_CCR2 TIM_CCR2_CCR2_Msk /*!<Capture/Compare 2 Value */
+
+/******************* Bit definition for TIM_CCR3 register ******************/
+#define TIM_CCR3_CCR3_Pos (0U)
+#define TIM_CCR3_CCR3_Msk (0xFFFFU << TIM_CCR3_CCR3_Pos) /*!< 0x0000FFFF */
+#define TIM_CCR3_CCR3 TIM_CCR3_CCR3_Msk /*!<Capture/Compare 3 Value */
+
+/******************* Bit definition for TIM_CCR4 register ******************/
+#define TIM_CCR4_CCR4_Pos (0U)
+#define TIM_CCR4_CCR4_Msk (0xFFFFU << TIM_CCR4_CCR4_Pos) /*!< 0x0000FFFF */
+#define TIM_CCR4_CCR4 TIM_CCR4_CCR4_Msk /*!<Capture/Compare 4 Value */
+
+/******************* Bit definition for TIM_BDTR register ******************/
+#define TIM_BDTR_DTG_Pos (0U)
+#define TIM_BDTR_DTG_Msk (0xFFU << TIM_BDTR_DTG_Pos) /*!< 0x000000FF */
+#define TIM_BDTR_DTG TIM_BDTR_DTG_Msk /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
+#define TIM_BDTR_DTG_0 (0x01U << TIM_BDTR_DTG_Pos) /*!< 0x00000001 */
+#define TIM_BDTR_DTG_1 (0x02U << TIM_BDTR_DTG_Pos) /*!< 0x00000002 */
+#define TIM_BDTR_DTG_2 (0x04U << TIM_BDTR_DTG_Pos) /*!< 0x00000004 */
+#define TIM_BDTR_DTG_3 (0x08U << TIM_BDTR_DTG_Pos) /*!< 0x00000008 */
+#define TIM_BDTR_DTG_4 (0x10U << TIM_BDTR_DTG_Pos) /*!< 0x00000010 */
+#define TIM_BDTR_DTG_5 (0x20U << TIM_BDTR_DTG_Pos) /*!< 0x00000020 */
+#define TIM_BDTR_DTG_6 (0x40U << TIM_BDTR_DTG_Pos) /*!< 0x00000040 */
+#define TIM_BDTR_DTG_7 (0x80U << TIM_BDTR_DTG_Pos) /*!< 0x00000080 */
+
+#define TIM_BDTR_LOCK_Pos (8U)
+#define TIM_BDTR_LOCK_Msk (0x3U << TIM_BDTR_LOCK_Pos) /*!< 0x00000300 */
+#define TIM_BDTR_LOCK TIM_BDTR_LOCK_Msk /*!<LOCK[1:0] bits (Lock Configuration) */
+#define TIM_BDTR_LOCK_0 (0x1U << TIM_BDTR_LOCK_Pos) /*!< 0x00000100 */
+#define TIM_BDTR_LOCK_1 (0x2U << TIM_BDTR_LOCK_Pos) /*!< 0x00000200 */
+
+#define TIM_BDTR_OSSI_Pos (10U)
+#define TIM_BDTR_OSSI_Msk (0x1U << TIM_BDTR_OSSI_Pos) /*!< 0x00000400 */
+#define TIM_BDTR_OSSI TIM_BDTR_OSSI_Msk /*!<Off-State Selection for Idle mode */
+#define TIM_BDTR_OSSR_Pos (11U)
+#define TIM_BDTR_OSSR_Msk (0x1U << TIM_BDTR_OSSR_Pos) /*!< 0x00000800 */
+#define TIM_BDTR_OSSR TIM_BDTR_OSSR_Msk /*!<Off-State Selection for Run mode */
+#define TIM_BDTR_BKE_Pos (12U)
+#define TIM_BDTR_BKE_Msk (0x1U << TIM_BDTR_BKE_Pos) /*!< 0x00001000 */
+#define TIM_BDTR_BKE TIM_BDTR_BKE_Msk /*!<Break enable */
+#define TIM_BDTR_BKP_Pos (13U)
+#define TIM_BDTR_BKP_Msk (0x1U << TIM_BDTR_BKP_Pos) /*!< 0x00002000 */
+#define TIM_BDTR_BKP TIM_BDTR_BKP_Msk /*!<Break Polarity */
+#define TIM_BDTR_AOE_Pos (14U)
+#define TIM_BDTR_AOE_Msk (0x1U << TIM_BDTR_AOE_Pos) /*!< 0x00004000 */
+#define TIM_BDTR_AOE TIM_BDTR_AOE_Msk /*!<Automatic Output enable */
+#define TIM_BDTR_MOE_Pos (15U)
+#define TIM_BDTR_MOE_Msk (0x1U << TIM_BDTR_MOE_Pos) /*!< 0x00008000 */
+#define TIM_BDTR_MOE TIM_BDTR_MOE_Msk /*!<Main Output enable */
+
+/******************* Bit definition for TIM_DCR register *******************/
+#define TIM_DCR_DBA_Pos (0U)
+#define TIM_DCR_DBA_Msk (0x1FU << TIM_DCR_DBA_Pos) /*!< 0x0000001F */
+#define TIM_DCR_DBA TIM_DCR_DBA_Msk /*!<DBA[4:0] bits (DMA Base Address) */
+#define TIM_DCR_DBA_0 (0x01U << TIM_DCR_DBA_Pos) /*!< 0x00000001 */
+#define TIM_DCR_DBA_1 (0x02U << TIM_DCR_DBA_Pos) /*!< 0x00000002 */
+#define TIM_DCR_DBA_2 (0x04U << TIM_DCR_DBA_Pos) /*!< 0x00000004 */
+#define TIM_DCR_DBA_3 (0x08U << TIM_DCR_DBA_Pos) /*!< 0x00000008 */
+#define TIM_DCR_DBA_4 (0x10U << TIM_DCR_DBA_Pos) /*!< 0x00000010 */
+
+#define TIM_DCR_DBL_Pos (8U)
+#define TIM_DCR_DBL_Msk (0x1FU << TIM_DCR_DBL_Pos) /*!< 0x00001F00 */
+#define TIM_DCR_DBL TIM_DCR_DBL_Msk /*!<DBL[4:0] bits (DMA Burst Length) */
+#define TIM_DCR_DBL_0 (0x01U << TIM_DCR_DBL_Pos) /*!< 0x00000100 */
+#define TIM_DCR_DBL_1 (0x02U << TIM_DCR_DBL_Pos) /*!< 0x00000200 */
+#define TIM_DCR_DBL_2 (0x04U << TIM_DCR_DBL_Pos) /*!< 0x00000400 */
+#define TIM_DCR_DBL_3 (0x08U << TIM_DCR_DBL_Pos) /*!< 0x00000800 */
+#define TIM_DCR_DBL_4 (0x10U << TIM_DCR_DBL_Pos) /*!< 0x00001000 */
+
+/******************* Bit definition for TIM_DMAR register ******************/
+#define TIM_DMAR_DMAB_Pos (0U)
+#define TIM_DMAR_DMAB_Msk (0xFFFFU << TIM_DMAR_DMAB_Pos) /*!< 0x0000FFFF */
+#define TIM_DMAR_DMAB TIM_DMAR_DMAB_Msk /*!<DMA register for burst accesses */
+
+/******************* Bit definition for TIM_OR register ********************/
+
+/******************************************************************************/
+/* */
+/* Real-Time Clock */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for RTC_CRH register ********************/
+#define RTC_CRH_SECIE_Pos (0U)
+#define RTC_CRH_SECIE_Msk (0x1U << RTC_CRH_SECIE_Pos) /*!< 0x00000001 */
+#define RTC_CRH_SECIE RTC_CRH_SECIE_Msk /*!< Second Interrupt Enable */
+#define RTC_CRH_ALRIE_Pos (1U)
+#define RTC_CRH_ALRIE_Msk (0x1U << RTC_CRH_ALRIE_Pos) /*!< 0x00000002 */
+#define RTC_CRH_ALRIE RTC_CRH_ALRIE_Msk /*!< Alarm Interrupt Enable */
+#define RTC_CRH_OWIE_Pos (2U)
+#define RTC_CRH_OWIE_Msk (0x1U << RTC_CRH_OWIE_Pos) /*!< 0x00000004 */
+#define RTC_CRH_OWIE RTC_CRH_OWIE_Msk /*!< OverfloW Interrupt Enable */
+
+/******************* Bit definition for RTC_CRL register ********************/
+#define RTC_CRL_SECF_Pos (0U)
+#define RTC_CRL_SECF_Msk (0x1U << RTC_CRL_SECF_Pos) /*!< 0x00000001 */
+#define RTC_CRL_SECF RTC_CRL_SECF_Msk /*!< Second Flag */
+#define RTC_CRL_ALRF_Pos (1U)
+#define RTC_CRL_ALRF_Msk (0x1U << RTC_CRL_ALRF_Pos) /*!< 0x00000002 */
+#define RTC_CRL_ALRF RTC_CRL_ALRF_Msk /*!< Alarm Flag */
+#define RTC_CRL_OWF_Pos (2U)
+#define RTC_CRL_OWF_Msk (0x1U << RTC_CRL_OWF_Pos) /*!< 0x00000004 */
+#define RTC_CRL_OWF RTC_CRL_OWF_Msk /*!< OverfloW Flag */
+#define RTC_CRL_RSF_Pos (3U)
+#define RTC_CRL_RSF_Msk (0x1U << RTC_CRL_RSF_Pos) /*!< 0x00000008 */
+#define RTC_CRL_RSF RTC_CRL_RSF_Msk /*!< Registers Synchronized Flag */
+#define RTC_CRL_CNF_Pos (4U)
+#define RTC_CRL_CNF_Msk (0x1U << RTC_CRL_CNF_Pos) /*!< 0x00000010 */
+#define RTC_CRL_CNF RTC_CRL_CNF_Msk /*!< Configuration Flag */
+#define RTC_CRL_RTOFF_Pos (5U)
+#define RTC_CRL_RTOFF_Msk (0x1U << RTC_CRL_RTOFF_Pos) /*!< 0x00000020 */
+#define RTC_CRL_RTOFF RTC_CRL_RTOFF_Msk /*!< RTC operation OFF */
+
+/******************* Bit definition for RTC_PRLH register *******************/
+#define RTC_PRLH_PRL_Pos (0U)
+#define RTC_PRLH_PRL_Msk (0xFU << RTC_PRLH_PRL_Pos) /*!< 0x0000000F */
+#define RTC_PRLH_PRL RTC_PRLH_PRL_Msk /*!< RTC Prescaler Reload Value High */
+
+/******************* Bit definition for RTC_PRLL register *******************/
+#define RTC_PRLL_PRL_Pos (0U)
+#define RTC_PRLL_PRL_Msk (0xFFFFU << RTC_PRLL_PRL_Pos) /*!< 0x0000FFFF */
+#define RTC_PRLL_PRL RTC_PRLL_PRL_Msk /*!< RTC Prescaler Reload Value Low */
+
+/******************* Bit definition for RTC_DIVH register *******************/
+#define RTC_DIVH_RTC_DIV_Pos (0U)
+#define RTC_DIVH_RTC_DIV_Msk (0xFU << RTC_DIVH_RTC_DIV_Pos) /*!< 0x0000000F */
+#define RTC_DIVH_RTC_DIV RTC_DIVH_RTC_DIV_Msk /*!< RTC Clock Divider High */
+
+/******************* Bit definition for RTC_DIVL register *******************/
+#define RTC_DIVL_RTC_DIV_Pos (0U)
+#define RTC_DIVL_RTC_DIV_Msk (0xFFFFU << RTC_DIVL_RTC_DIV_Pos) /*!< 0x0000FFFF */
+#define RTC_DIVL_RTC_DIV RTC_DIVL_RTC_DIV_Msk /*!< RTC Clock Divider Low */
+
+/******************* Bit definition for RTC_CNTH register *******************/
+#define RTC_CNTH_RTC_CNT_Pos (0U)
+#define RTC_CNTH_RTC_CNT_Msk (0xFFFFU << RTC_CNTH_RTC_CNT_Pos) /*!< 0x0000FFFF */
+#define RTC_CNTH_RTC_CNT RTC_CNTH_RTC_CNT_Msk /*!< RTC Counter High */
+
+/******************* Bit definition for RTC_CNTL register *******************/
+#define RTC_CNTL_RTC_CNT_Pos (0U)
+#define RTC_CNTL_RTC_CNT_Msk (0xFFFFU << RTC_CNTL_RTC_CNT_Pos) /*!< 0x0000FFFF */
+#define RTC_CNTL_RTC_CNT RTC_CNTL_RTC_CNT_Msk /*!< RTC Counter Low */
+
+/******************* Bit definition for RTC_ALRH register *******************/
+#define RTC_ALRH_RTC_ALR_Pos (0U)
+#define RTC_ALRH_RTC_ALR_Msk (0xFFFFU << RTC_ALRH_RTC_ALR_Pos) /*!< 0x0000FFFF */
+#define RTC_ALRH_RTC_ALR RTC_ALRH_RTC_ALR_Msk /*!< RTC Alarm High */
+
+/******************* Bit definition for RTC_ALRL register *******************/
+#define RTC_ALRL_RTC_ALR_Pos (0U)
+#define RTC_ALRL_RTC_ALR_Msk (0xFFFFU << RTC_ALRL_RTC_ALR_Pos) /*!< 0x0000FFFF */
+#define RTC_ALRL_RTC_ALR RTC_ALRL_RTC_ALR_Msk /*!< RTC Alarm Low */
+
+/******************************************************************************/
+/* */
+/* Independent WATCHDOG (IWDG) */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for IWDG_KR register ********************/
+#define IWDG_KR_KEY_Pos (0U)
+#define IWDG_KR_KEY_Msk (0xFFFFU << IWDG_KR_KEY_Pos) /*!< 0x0000FFFF */
+#define IWDG_KR_KEY IWDG_KR_KEY_Msk /*!< Key value (write only, read 0000h) */
+
+/******************* Bit definition for IWDG_PR register ********************/
+#define IWDG_PR_PR_Pos (0U)
+#define IWDG_PR_PR_Msk (0x7U << IWDG_PR_PR_Pos) /*!< 0x00000007 */
+#define IWDG_PR_PR IWDG_PR_PR_Msk /*!< PR[2:0] (Prescaler divider) */
+#define IWDG_PR_PR_0 (0x1U << IWDG_PR_PR_Pos) /*!< 0x00000001 */
+#define IWDG_PR_PR_1 (0x2U << IWDG_PR_PR_Pos) /*!< 0x00000002 */
+#define IWDG_PR_PR_2 (0x4U << IWDG_PR_PR_Pos) /*!< 0x00000004 */
+
+/******************* Bit definition for IWDG_RLR register *******************/
+#define IWDG_RLR_RL_Pos (0U)
+#define IWDG_RLR_RL_Msk (0xFFFU << IWDG_RLR_RL_Pos) /*!< 0x00000FFF */
+#define IWDG_RLR_RL IWDG_RLR_RL_Msk /*!< Watchdog counter reload value */
+
+/******************* Bit definition for IWDG_SR register ********************/
+#define IWDG_SR_PVU_Pos (0U)
+#define IWDG_SR_PVU_Msk (0x1U << IWDG_SR_PVU_Pos) /*!< 0x00000001 */
+#define IWDG_SR_PVU IWDG_SR_PVU_Msk /*!< Watchdog prescaler value update */
+#define IWDG_SR_RVU_Pos (1U)
+#define IWDG_SR_RVU_Msk (0x1U << IWDG_SR_RVU_Pos) /*!< 0x00000002 */
+#define IWDG_SR_RVU IWDG_SR_RVU_Msk /*!< Watchdog counter reload value update */
+
+/******************************************************************************/
+/* */
+/* Window WATCHDOG (WWDG) */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for WWDG_CR register ********************/
+#define WWDG_CR_T_Pos (0U)
+#define WWDG_CR_T_Msk (0x7FU << WWDG_CR_T_Pos) /*!< 0x0000007F */
+#define WWDG_CR_T WWDG_CR_T_Msk /*!< T[6:0] bits (7-Bit counter (MSB to LSB)) */
+#define WWDG_CR_T_0 (0x01U << WWDG_CR_T_Pos) /*!< 0x00000001 */
+#define WWDG_CR_T_1 (0x02U << WWDG_CR_T_Pos) /*!< 0x00000002 */
+#define WWDG_CR_T_2 (0x04U << WWDG_CR_T_Pos) /*!< 0x00000004 */
+#define WWDG_CR_T_3 (0x08U << WWDG_CR_T_Pos) /*!< 0x00000008 */
+#define WWDG_CR_T_4 (0x10U << WWDG_CR_T_Pos) /*!< 0x00000010 */
+#define WWDG_CR_T_5 (0x20U << WWDG_CR_T_Pos) /*!< 0x00000020 */
+#define WWDG_CR_T_6 (0x40U << WWDG_CR_T_Pos) /*!< 0x00000040 */
+
+/* Legacy defines */
+#define WWDG_CR_T0 WWDG_CR_T_0
+#define WWDG_CR_T1 WWDG_CR_T_1
+#define WWDG_CR_T2 WWDG_CR_T_2
+#define WWDG_CR_T3 WWDG_CR_T_3
+#define WWDG_CR_T4 WWDG_CR_T_4
+#define WWDG_CR_T5 WWDG_CR_T_5
+#define WWDG_CR_T6 WWDG_CR_T_6
+
+#define WWDG_CR_WDGA_Pos (7U)
+#define WWDG_CR_WDGA_Msk (0x1U << WWDG_CR_WDGA_Pos) /*!< 0x00000080 */
+#define WWDG_CR_WDGA WWDG_CR_WDGA_Msk /*!< Activation bit */
+
+/******************* Bit definition for WWDG_CFR register *******************/
+#define WWDG_CFR_W_Pos (0U)
+#define WWDG_CFR_W_Msk (0x7FU << WWDG_CFR_W_Pos) /*!< 0x0000007F */
+#define WWDG_CFR_W WWDG_CFR_W_Msk /*!< W[6:0] bits (7-bit window value) */
+#define WWDG_CFR_W_0 (0x01U << WWDG_CFR_W_Pos) /*!< 0x00000001 */
+#define WWDG_CFR_W_1 (0x02U << WWDG_CFR_W_Pos) /*!< 0x00000002 */
+#define WWDG_CFR_W_2 (0x04U << WWDG_CFR_W_Pos) /*!< 0x00000004 */
+#define WWDG_CFR_W_3 (0x08U << WWDG_CFR_W_Pos) /*!< 0x00000008 */
+#define WWDG_CFR_W_4 (0x10U << WWDG_CFR_W_Pos) /*!< 0x00000010 */
+#define WWDG_CFR_W_5 (0x20U << WWDG_CFR_W_Pos) /*!< 0x00000020 */
+#define WWDG_CFR_W_6 (0x40U << WWDG_CFR_W_Pos) /*!< 0x00000040 */
+
+/* Legacy defines */
+#define WWDG_CFR_W0 WWDG_CFR_W_0
+#define WWDG_CFR_W1 WWDG_CFR_W_1
+#define WWDG_CFR_W2 WWDG_CFR_W_2
+#define WWDG_CFR_W3 WWDG_CFR_W_3
+#define WWDG_CFR_W4 WWDG_CFR_W_4
+#define WWDG_CFR_W5 WWDG_CFR_W_5
+#define WWDG_CFR_W6 WWDG_CFR_W_6
+
+#define WWDG_CFR_WDGTB_Pos (7U)
+#define WWDG_CFR_WDGTB_Msk (0x3U << WWDG_CFR_WDGTB_Pos) /*!< 0x00000180 */
+#define WWDG_CFR_WDGTB WWDG_CFR_WDGTB_Msk /*!< WDGTB[1:0] bits (Timer Base) */
+#define WWDG_CFR_WDGTB_0 (0x1U << WWDG_CFR_WDGTB_Pos) /*!< 0x00000080 */
+#define WWDG_CFR_WDGTB_1 (0x2U << WWDG_CFR_WDGTB_Pos) /*!< 0x00000100 */
+
+/* Legacy defines */
+#define WWDG_CFR_WDGTB0 WWDG_CFR_WDGTB_0
+#define WWDG_CFR_WDGTB1 WWDG_CFR_WDGTB_1
+
+#define WWDG_CFR_EWI_Pos (9U)
+#define WWDG_CFR_EWI_Msk (0x1U << WWDG_CFR_EWI_Pos) /*!< 0x00000200 */
+#define WWDG_CFR_EWI WWDG_CFR_EWI_Msk /*!< Early Wakeup Interrupt */
+
+/******************* Bit definition for WWDG_SR register ********************/
+#define WWDG_SR_EWIF_Pos (0U)
+#define WWDG_SR_EWIF_Msk (0x1U << WWDG_SR_EWIF_Pos) /*!< 0x00000001 */
+#define WWDG_SR_EWIF WWDG_SR_EWIF_Msk /*!< Early Wakeup Interrupt Flag */
+
+
+/******************************************************************************/
+/* */
+/* SD host Interface */
+/* */
+/******************************************************************************/
+
+/****************** Bit definition for SDIO_POWER register ******************/
+#define SDIO_POWER_PWRCTRL_Pos (0U)
+#define SDIO_POWER_PWRCTRL_Msk (0x3U << SDIO_POWER_PWRCTRL_Pos) /*!< 0x00000003 */
+#define SDIO_POWER_PWRCTRL SDIO_POWER_PWRCTRL_Msk /*!< PWRCTRL[1:0] bits (Power supply control bits) */
+#define SDIO_POWER_PWRCTRL_0 (0x1U << SDIO_POWER_PWRCTRL_Pos) /*!< 0x01 */
+#define SDIO_POWER_PWRCTRL_1 (0x2U << SDIO_POWER_PWRCTRL_Pos) /*!< 0x02 */
+
+/****************** Bit definition for SDIO_CLKCR register ******************/
+#define SDIO_CLKCR_CLKDIV_Pos (0U)
+#define SDIO_CLKCR_CLKDIV_Msk (0xFFU << SDIO_CLKCR_CLKDIV_Pos) /*!< 0x000000FF */
+#define SDIO_CLKCR_CLKDIV SDIO_CLKCR_CLKDIV_Msk /*!< Clock divide factor */
+#define SDIO_CLKCR_CLKEN_Pos (8U)
+#define SDIO_CLKCR_CLKEN_Msk (0x1U << SDIO_CLKCR_CLKEN_Pos) /*!< 0x00000100 */
+#define SDIO_CLKCR_CLKEN SDIO_CLKCR_CLKEN_Msk /*!< Clock enable bit */
+#define SDIO_CLKCR_PWRSAV_Pos (9U)
+#define SDIO_CLKCR_PWRSAV_Msk (0x1U << SDIO_CLKCR_PWRSAV_Pos) /*!< 0x00000200 */
+#define SDIO_CLKCR_PWRSAV SDIO_CLKCR_PWRSAV_Msk /*!< Power saving configuration bit */
+#define SDIO_CLKCR_BYPASS_Pos (10U)
+#define SDIO_CLKCR_BYPASS_Msk (0x1U << SDIO_CLKCR_BYPASS_Pos) /*!< 0x00000400 */
+#define SDIO_CLKCR_BYPASS SDIO_CLKCR_BYPASS_Msk /*!< Clock divider bypass enable bit */
+
+#define SDIO_CLKCR_WIDBUS_Pos (11U)
+#define SDIO_CLKCR_WIDBUS_Msk (0x3U << SDIO_CLKCR_WIDBUS_Pos) /*!< 0x00001800 */
+#define SDIO_CLKCR_WIDBUS SDIO_CLKCR_WIDBUS_Msk /*!< WIDBUS[1:0] bits (Wide bus mode enable bit) */
+#define SDIO_CLKCR_WIDBUS_0 (0x1U << SDIO_CLKCR_WIDBUS_Pos) /*!< 0x0800 */
+#define SDIO_CLKCR_WIDBUS_1 (0x2U << SDIO_CLKCR_WIDBUS_Pos) /*!< 0x1000 */
+
+#define SDIO_CLKCR_NEGEDGE_Pos (13U)
+#define SDIO_CLKCR_NEGEDGE_Msk (0x1U << SDIO_CLKCR_NEGEDGE_Pos) /*!< 0x00002000 */
+#define SDIO_CLKCR_NEGEDGE SDIO_CLKCR_NEGEDGE_Msk /*!< SDIO_CK dephasing selection bit */
+#define SDIO_CLKCR_HWFC_EN_Pos (14U)
+#define SDIO_CLKCR_HWFC_EN_Msk (0x1U << SDIO_CLKCR_HWFC_EN_Pos) /*!< 0x00004000 */
+#define SDIO_CLKCR_HWFC_EN SDIO_CLKCR_HWFC_EN_Msk /*!< HW Flow Control enable */
+
+/******************* Bit definition for SDIO_ARG register *******************/
+#define SDIO_ARG_CMDARG_Pos (0U)
+#define SDIO_ARG_CMDARG_Msk (0xFFFFFFFFU << SDIO_ARG_CMDARG_Pos) /*!< 0xFFFFFFFF */
+#define SDIO_ARG_CMDARG SDIO_ARG_CMDARG_Msk /*!< Command argument */
+
+/******************* Bit definition for SDIO_CMD register *******************/
+#define SDIO_CMD_CMDINDEX_Pos (0U)
+#define SDIO_CMD_CMDINDEX_Msk (0x3FU << SDIO_CMD_CMDINDEX_Pos) /*!< 0x0000003F */
+#define SDIO_CMD_CMDINDEX SDIO_CMD_CMDINDEX_Msk /*!< Command Index */
+
+#define SDIO_CMD_WAITRESP_Pos (6U)
+#define SDIO_CMD_WAITRESP_Msk (0x3U << SDIO_CMD_WAITRESP_Pos) /*!< 0x000000C0 */
+#define SDIO_CMD_WAITRESP SDIO_CMD_WAITRESP_Msk /*!< WAITRESP[1:0] bits (Wait for response bits) */
+#define SDIO_CMD_WAITRESP_0 (0x1U << SDIO_CMD_WAITRESP_Pos) /*!< 0x0040 */
+#define SDIO_CMD_WAITRESP_1 (0x2U << SDIO_CMD_WAITRESP_Pos) /*!< 0x0080 */
+
+#define SDIO_CMD_WAITINT_Pos (8U)
+#define SDIO_CMD_WAITINT_Msk (0x1U << SDIO_CMD_WAITINT_Pos) /*!< 0x00000100 */
+#define SDIO_CMD_WAITINT SDIO_CMD_WAITINT_Msk /*!< CPSM Waits for Interrupt Request */
+#define SDIO_CMD_WAITPEND_Pos (9U)
+#define SDIO_CMD_WAITPEND_Msk (0x1U << SDIO_CMD_WAITPEND_Pos) /*!< 0x00000200 */
+#define SDIO_CMD_WAITPEND SDIO_CMD_WAITPEND_Msk /*!< CPSM Waits for ends of data transfer (CmdPend internal signal) */
+#define SDIO_CMD_CPSMEN_Pos (10U)
+#define SDIO_CMD_CPSMEN_Msk (0x1U << SDIO_CMD_CPSMEN_Pos) /*!< 0x00000400 */
+#define SDIO_CMD_CPSMEN SDIO_CMD_CPSMEN_Msk /*!< Command path state machine (CPSM) Enable bit */
+#define SDIO_CMD_SDIOSUSPEND_Pos (11U)
+#define SDIO_CMD_SDIOSUSPEND_Msk (0x1U << SDIO_CMD_SDIOSUSPEND_Pos) /*!< 0x00000800 */
+#define SDIO_CMD_SDIOSUSPEND SDIO_CMD_SDIOSUSPEND_Msk /*!< SD I/O suspend command */
+#define SDIO_CMD_ENCMDCOMPL_Pos (12U)
+#define SDIO_CMD_ENCMDCOMPL_Msk (0x1U << SDIO_CMD_ENCMDCOMPL_Pos) /*!< 0x00001000 */
+#define SDIO_CMD_ENCMDCOMPL SDIO_CMD_ENCMDCOMPL_Msk /*!< Enable CMD completion */
+#define SDIO_CMD_NIEN_Pos (13U)
+#define SDIO_CMD_NIEN_Msk (0x1U << SDIO_CMD_NIEN_Pos) /*!< 0x00002000 */
+#define SDIO_CMD_NIEN SDIO_CMD_NIEN_Msk /*!< Not Interrupt Enable */
+#define SDIO_CMD_CEATACMD_Pos (14U)
+#define SDIO_CMD_CEATACMD_Msk (0x1U << SDIO_CMD_CEATACMD_Pos) /*!< 0x00004000 */
+#define SDIO_CMD_CEATACMD SDIO_CMD_CEATACMD_Msk /*!< CE-ATA command */
+
+/***************** Bit definition for SDIO_RESPCMD register *****************/
+#define SDIO_RESPCMD_RESPCMD_Pos (0U)
+#define SDIO_RESPCMD_RESPCMD_Msk (0x3FU << SDIO_RESPCMD_RESPCMD_Pos) /*!< 0x0000003F */
+#define SDIO_RESPCMD_RESPCMD SDIO_RESPCMD_RESPCMD_Msk /*!< Response command index */
+
+/****************** Bit definition for SDIO_RESP0 register ******************/
+#define SDIO_RESP0_CARDSTATUS0_Pos (0U)
+#define SDIO_RESP0_CARDSTATUS0_Msk (0xFFFFFFFFU << SDIO_RESP0_CARDSTATUS0_Pos) /*!< 0xFFFFFFFF */
+#define SDIO_RESP0_CARDSTATUS0 SDIO_RESP0_CARDSTATUS0_Msk /*!< Card Status */
+
+/****************** Bit definition for SDIO_RESP1 register ******************/
+#define SDIO_RESP1_CARDSTATUS1_Pos (0U)
+#define SDIO_RESP1_CARDSTATUS1_Msk (0xFFFFFFFFU << SDIO_RESP1_CARDSTATUS1_Pos) /*!< 0xFFFFFFFF */
+#define SDIO_RESP1_CARDSTATUS1 SDIO_RESP1_CARDSTATUS1_Msk /*!< Card Status */
+
+/****************** Bit definition for SDIO_RESP2 register ******************/
+#define SDIO_RESP2_CARDSTATUS2_Pos (0U)
+#define SDIO_RESP2_CARDSTATUS2_Msk (0xFFFFFFFFU << SDIO_RESP2_CARDSTATUS2_Pos) /*!< 0xFFFFFFFF */
+#define SDIO_RESP2_CARDSTATUS2 SDIO_RESP2_CARDSTATUS2_Msk /*!< Card Status */
+
+/****************** Bit definition for SDIO_RESP3 register ******************/
+#define SDIO_RESP3_CARDSTATUS3_Pos (0U)
+#define SDIO_RESP3_CARDSTATUS3_Msk (0xFFFFFFFFU << SDIO_RESP3_CARDSTATUS3_Pos) /*!< 0xFFFFFFFF */
+#define SDIO_RESP3_CARDSTATUS3 SDIO_RESP3_CARDSTATUS3_Msk /*!< Card Status */
+
+/****************** Bit definition for SDIO_RESP4 register ******************/
+#define SDIO_RESP4_CARDSTATUS4_Pos (0U)
+#define SDIO_RESP4_CARDSTATUS4_Msk (0xFFFFFFFFU << SDIO_RESP4_CARDSTATUS4_Pos) /*!< 0xFFFFFFFF */
+#define SDIO_RESP4_CARDSTATUS4 SDIO_RESP4_CARDSTATUS4_Msk /*!< Card Status */
+
+/****************** Bit definition for SDIO_DTIMER register *****************/
+#define SDIO_DTIMER_DATATIME_Pos (0U)
+#define SDIO_DTIMER_DATATIME_Msk (0xFFFFFFFFU << SDIO_DTIMER_DATATIME_Pos) /*!< 0xFFFFFFFF */
+#define SDIO_DTIMER_DATATIME SDIO_DTIMER_DATATIME_Msk /*!< Data timeout period. */
+
+/****************** Bit definition for SDIO_DLEN register *******************/
+#define SDIO_DLEN_DATALENGTH_Pos (0U)
+#define SDIO_DLEN_DATALENGTH_Msk (0x1FFFFFFU << SDIO_DLEN_DATALENGTH_Pos) /*!< 0x01FFFFFF */
+#define SDIO_DLEN_DATALENGTH SDIO_DLEN_DATALENGTH_Msk /*!< Data length value */
+
+/****************** Bit definition for SDIO_DCTRL register ******************/
+#define SDIO_DCTRL_DTEN_Pos (0U)
+#define SDIO_DCTRL_DTEN_Msk (0x1U << SDIO_DCTRL_DTEN_Pos) /*!< 0x00000001 */
+#define SDIO_DCTRL_DTEN SDIO_DCTRL_DTEN_Msk /*!< Data transfer enabled bit */
+#define SDIO_DCTRL_DTDIR_Pos (1U)
+#define SDIO_DCTRL_DTDIR_Msk (0x1U << SDIO_DCTRL_DTDIR_Pos) /*!< 0x00000002 */
+#define SDIO_DCTRL_DTDIR SDIO_DCTRL_DTDIR_Msk /*!< Data transfer direction selection */
+#define SDIO_DCTRL_DTMODE_Pos (2U)
+#define SDIO_DCTRL_DTMODE_Msk (0x1U << SDIO_DCTRL_DTMODE_Pos) /*!< 0x00000004 */
+#define SDIO_DCTRL_DTMODE SDIO_DCTRL_DTMODE_Msk /*!< Data transfer mode selection */
+#define SDIO_DCTRL_DMAEN_Pos (3U)
+#define SDIO_DCTRL_DMAEN_Msk (0x1U << SDIO_DCTRL_DMAEN_Pos) /*!< 0x00000008 */
+#define SDIO_DCTRL_DMAEN SDIO_DCTRL_DMAEN_Msk /*!< DMA enabled bit */
+
+#define SDIO_DCTRL_DBLOCKSIZE_Pos (4U)
+#define SDIO_DCTRL_DBLOCKSIZE_Msk (0xFU << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x000000F0 */
+#define SDIO_DCTRL_DBLOCKSIZE SDIO_DCTRL_DBLOCKSIZE_Msk /*!< DBLOCKSIZE[3:0] bits (Data block size) */
+#define SDIO_DCTRL_DBLOCKSIZE_0 (0x1U << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0010 */
+#define SDIO_DCTRL_DBLOCKSIZE_1 (0x2U << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0020 */
+#define SDIO_DCTRL_DBLOCKSIZE_2 (0x4U << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0040 */
+#define SDIO_DCTRL_DBLOCKSIZE_3 (0x8U << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0080 */
+
+#define SDIO_DCTRL_RWSTART_Pos (8U)
+#define SDIO_DCTRL_RWSTART_Msk (0x1U << SDIO_DCTRL_RWSTART_Pos) /*!< 0x00000100 */
+#define SDIO_DCTRL_RWSTART SDIO_DCTRL_RWSTART_Msk /*!< Read wait start */
+#define SDIO_DCTRL_RWSTOP_Pos (9U)
+#define SDIO_DCTRL_RWSTOP_Msk (0x1U << SDIO_DCTRL_RWSTOP_Pos) /*!< 0x00000200 */
+#define SDIO_DCTRL_RWSTOP SDIO_DCTRL_RWSTOP_Msk /*!< Read wait stop */
+#define SDIO_DCTRL_RWMOD_Pos (10U)
+#define SDIO_DCTRL_RWMOD_Msk (0x1U << SDIO_DCTRL_RWMOD_Pos) /*!< 0x00000400 */
+#define SDIO_DCTRL_RWMOD SDIO_DCTRL_RWMOD_Msk /*!< Read wait mode */
+#define SDIO_DCTRL_SDIOEN_Pos (11U)
+#define SDIO_DCTRL_SDIOEN_Msk (0x1U << SDIO_DCTRL_SDIOEN_Pos) /*!< 0x00000800 */
+#define SDIO_DCTRL_SDIOEN SDIO_DCTRL_SDIOEN_Msk /*!< SD I/O enable functions */
+
+/****************** Bit definition for SDIO_DCOUNT register *****************/
+#define SDIO_DCOUNT_DATACOUNT_Pos (0U)
+#define SDIO_DCOUNT_DATACOUNT_Msk (0x1FFFFFFU << SDIO_DCOUNT_DATACOUNT_Pos) /*!< 0x01FFFFFF */
+#define SDIO_DCOUNT_DATACOUNT SDIO_DCOUNT_DATACOUNT_Msk /*!< Data count value */
+
+/****************** Bit definition for SDIO_STA register ********************/
+#define SDIO_STA_CCRCFAIL_Pos (0U)
+#define SDIO_STA_CCRCFAIL_Msk (0x1U << SDIO_STA_CCRCFAIL_Pos) /*!< 0x00000001 */
+#define SDIO_STA_CCRCFAIL SDIO_STA_CCRCFAIL_Msk /*!< Command response received (CRC check failed) */
+#define SDIO_STA_DCRCFAIL_Pos (1U)
+#define SDIO_STA_DCRCFAIL_Msk (0x1U << SDIO_STA_DCRCFAIL_Pos) /*!< 0x00000002 */
+#define SDIO_STA_DCRCFAIL SDIO_STA_DCRCFAIL_Msk /*!< Data block sent/received (CRC check failed) */
+#define SDIO_STA_CTIMEOUT_Pos (2U)
+#define SDIO_STA_CTIMEOUT_Msk (0x1U << SDIO_STA_CTIMEOUT_Pos) /*!< 0x00000004 */
+#define SDIO_STA_CTIMEOUT SDIO_STA_CTIMEOUT_Msk /*!< Command response timeout */
+#define SDIO_STA_DTIMEOUT_Pos (3U)
+#define SDIO_STA_DTIMEOUT_Msk (0x1U << SDIO_STA_DTIMEOUT_Pos) /*!< 0x00000008 */
+#define SDIO_STA_DTIMEOUT SDIO_STA_DTIMEOUT_Msk /*!< Data timeout */
+#define SDIO_STA_TXUNDERR_Pos (4U)
+#define SDIO_STA_TXUNDERR_Msk (0x1U << SDIO_STA_TXUNDERR_Pos) /*!< 0x00000010 */
+#define SDIO_STA_TXUNDERR SDIO_STA_TXUNDERR_Msk /*!< Transmit FIFO underrun error */
+#define SDIO_STA_RXOVERR_Pos (5U)
+#define SDIO_STA_RXOVERR_Msk (0x1U << SDIO_STA_RXOVERR_Pos) /*!< 0x00000020 */
+#define SDIO_STA_RXOVERR SDIO_STA_RXOVERR_Msk /*!< Received FIFO overrun error */
+#define SDIO_STA_CMDREND_Pos (6U)
+#define SDIO_STA_CMDREND_Msk (0x1U << SDIO_STA_CMDREND_Pos) /*!< 0x00000040 */
+#define SDIO_STA_CMDREND SDIO_STA_CMDREND_Msk /*!< Command response received (CRC check passed) */
+#define SDIO_STA_CMDSENT_Pos (7U)
+#define SDIO_STA_CMDSENT_Msk (0x1U << SDIO_STA_CMDSENT_Pos) /*!< 0x00000080 */
+#define SDIO_STA_CMDSENT SDIO_STA_CMDSENT_Msk /*!< Command sent (no response required) */
+#define SDIO_STA_DATAEND_Pos (8U)
+#define SDIO_STA_DATAEND_Msk (0x1U << SDIO_STA_DATAEND_Pos) /*!< 0x00000100 */
+#define SDIO_STA_DATAEND SDIO_STA_DATAEND_Msk /*!< Data end (data counter, SDIDCOUNT, is zero) */
+#define SDIO_STA_STBITERR_Pos (9U)
+#define SDIO_STA_STBITERR_Msk (0x1U << SDIO_STA_STBITERR_Pos) /*!< 0x00000200 */
+#define SDIO_STA_STBITERR SDIO_STA_STBITERR_Msk /*!< Start bit not detected on all data signals in wide bus mode */
+#define SDIO_STA_DBCKEND_Pos (10U)
+#define SDIO_STA_DBCKEND_Msk (0x1U << SDIO_STA_DBCKEND_Pos) /*!< 0x00000400 */
+#define SDIO_STA_DBCKEND SDIO_STA_DBCKEND_Msk /*!< Data block sent/received (CRC check passed) */
+#define SDIO_STA_CMDACT_Pos (11U)
+#define SDIO_STA_CMDACT_Msk (0x1U << SDIO_STA_CMDACT_Pos) /*!< 0x00000800 */
+#define SDIO_STA_CMDACT SDIO_STA_CMDACT_Msk /*!< Command transfer in progress */
+#define SDIO_STA_TXACT_Pos (12U)
+#define SDIO_STA_TXACT_Msk (0x1U << SDIO_STA_TXACT_Pos) /*!< 0x00001000 */
+#define SDIO_STA_TXACT SDIO_STA_TXACT_Msk /*!< Data transmit in progress */
+#define SDIO_STA_RXACT_Pos (13U)
+#define SDIO_STA_RXACT_Msk (0x1U << SDIO_STA_RXACT_Pos) /*!< 0x00002000 */
+#define SDIO_STA_RXACT SDIO_STA_RXACT_Msk /*!< Data receive in progress */
+#define SDIO_STA_TXFIFOHE_Pos (14U)
+#define SDIO_STA_TXFIFOHE_Msk (0x1U << SDIO_STA_TXFIFOHE_Pos) /*!< 0x00004000 */
+#define SDIO_STA_TXFIFOHE SDIO_STA_TXFIFOHE_Msk /*!< Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
+#define SDIO_STA_RXFIFOHF_Pos (15U)
+#define SDIO_STA_RXFIFOHF_Msk (0x1U << SDIO_STA_RXFIFOHF_Pos) /*!< 0x00008000 */
+#define SDIO_STA_RXFIFOHF SDIO_STA_RXFIFOHF_Msk /*!< Receive FIFO Half Full: there are at least 8 words in the FIFO */
+#define SDIO_STA_TXFIFOF_Pos (16U)
+#define SDIO_STA_TXFIFOF_Msk (0x1U << SDIO_STA_TXFIFOF_Pos) /*!< 0x00010000 */
+#define SDIO_STA_TXFIFOF SDIO_STA_TXFIFOF_Msk /*!< Transmit FIFO full */
+#define SDIO_STA_RXFIFOF_Pos (17U)
+#define SDIO_STA_RXFIFOF_Msk (0x1U << SDIO_STA_RXFIFOF_Pos) /*!< 0x00020000 */
+#define SDIO_STA_RXFIFOF SDIO_STA_RXFIFOF_Msk /*!< Receive FIFO full */
+#define SDIO_STA_TXFIFOE_Pos (18U)
+#define SDIO_STA_TXFIFOE_Msk (0x1U << SDIO_STA_TXFIFOE_Pos) /*!< 0x00040000 */
+#define SDIO_STA_TXFIFOE SDIO_STA_TXFIFOE_Msk /*!< Transmit FIFO empty */
+#define SDIO_STA_RXFIFOE_Pos (19U)
+#define SDIO_STA_RXFIFOE_Msk (0x1U << SDIO_STA_RXFIFOE_Pos) /*!< 0x00080000 */
+#define SDIO_STA_RXFIFOE SDIO_STA_RXFIFOE_Msk /*!< Receive FIFO empty */
+#define SDIO_STA_TXDAVL_Pos (20U)
+#define SDIO_STA_TXDAVL_Msk (0x1U << SDIO_STA_TXDAVL_Pos) /*!< 0x00100000 */
+#define SDIO_STA_TXDAVL SDIO_STA_TXDAVL_Msk /*!< Data available in transmit FIFO */
+#define SDIO_STA_RXDAVL_Pos (21U)
+#define SDIO_STA_RXDAVL_Msk (0x1U << SDIO_STA_RXDAVL_Pos) /*!< 0x00200000 */
+#define SDIO_STA_RXDAVL SDIO_STA_RXDAVL_Msk /*!< Data available in receive FIFO */
+#define SDIO_STA_SDIOIT_Pos (22U)
+#define SDIO_STA_SDIOIT_Msk (0x1U << SDIO_STA_SDIOIT_Pos) /*!< 0x00400000 */
+#define SDIO_STA_SDIOIT SDIO_STA_SDIOIT_Msk /*!< SDIO interrupt received */
+#define SDIO_STA_CEATAEND_Pos (23U)
+#define SDIO_STA_CEATAEND_Msk (0x1U << SDIO_STA_CEATAEND_Pos) /*!< 0x00800000 */
+#define SDIO_STA_CEATAEND SDIO_STA_CEATAEND_Msk /*!< CE-ATA command completion signal received for CMD61 */
+
+/******************* Bit definition for SDIO_ICR register *******************/
+#define SDIO_ICR_CCRCFAILC_Pos (0U)
+#define SDIO_ICR_CCRCFAILC_Msk (0x1U << SDIO_ICR_CCRCFAILC_Pos) /*!< 0x00000001 */
+#define SDIO_ICR_CCRCFAILC SDIO_ICR_CCRCFAILC_Msk /*!< CCRCFAIL flag clear bit */
+#define SDIO_ICR_DCRCFAILC_Pos (1U)
+#define SDIO_ICR_DCRCFAILC_Msk (0x1U << SDIO_ICR_DCRCFAILC_Pos) /*!< 0x00000002 */
+#define SDIO_ICR_DCRCFAILC SDIO_ICR_DCRCFAILC_Msk /*!< DCRCFAIL flag clear bit */
+#define SDIO_ICR_CTIMEOUTC_Pos (2U)
+#define SDIO_ICR_CTIMEOUTC_Msk (0x1U << SDIO_ICR_CTIMEOUTC_Pos) /*!< 0x00000004 */
+#define SDIO_ICR_CTIMEOUTC SDIO_ICR_CTIMEOUTC_Msk /*!< CTIMEOUT flag clear bit */
+#define SDIO_ICR_DTIMEOUTC_Pos (3U)
+#define SDIO_ICR_DTIMEOUTC_Msk (0x1U << SDIO_ICR_DTIMEOUTC_Pos) /*!< 0x00000008 */
+#define SDIO_ICR_DTIMEOUTC SDIO_ICR_DTIMEOUTC_Msk /*!< DTIMEOUT flag clear bit */
+#define SDIO_ICR_TXUNDERRC_Pos (4U)
+#define SDIO_ICR_TXUNDERRC_Msk (0x1U << SDIO_ICR_TXUNDERRC_Pos) /*!< 0x00000010 */
+#define SDIO_ICR_TXUNDERRC SDIO_ICR_TXUNDERRC_Msk /*!< TXUNDERR flag clear bit */
+#define SDIO_ICR_RXOVERRC_Pos (5U)
+#define SDIO_ICR_RXOVERRC_Msk (0x1U << SDIO_ICR_RXOVERRC_Pos) /*!< 0x00000020 */
+#define SDIO_ICR_RXOVERRC SDIO_ICR_RXOVERRC_Msk /*!< RXOVERR flag clear bit */
+#define SDIO_ICR_CMDRENDC_Pos (6U)
+#define SDIO_ICR_CMDRENDC_Msk (0x1U << SDIO_ICR_CMDRENDC_Pos) /*!< 0x00000040 */
+#define SDIO_ICR_CMDRENDC SDIO_ICR_CMDRENDC_Msk /*!< CMDREND flag clear bit */
+#define SDIO_ICR_CMDSENTC_Pos (7U)
+#define SDIO_ICR_CMDSENTC_Msk (0x1U << SDIO_ICR_CMDSENTC_Pos) /*!< 0x00000080 */
+#define SDIO_ICR_CMDSENTC SDIO_ICR_CMDSENTC_Msk /*!< CMDSENT flag clear bit */
+#define SDIO_ICR_DATAENDC_Pos (8U)
+#define SDIO_ICR_DATAENDC_Msk (0x1U << SDIO_ICR_DATAENDC_Pos) /*!< 0x00000100 */
+#define SDIO_ICR_DATAENDC SDIO_ICR_DATAENDC_Msk /*!< DATAEND flag clear bit */
+#define SDIO_ICR_STBITERRC_Pos (9U)
+#define SDIO_ICR_STBITERRC_Msk (0x1U << SDIO_ICR_STBITERRC_Pos) /*!< 0x00000200 */
+#define SDIO_ICR_STBITERRC SDIO_ICR_STBITERRC_Msk /*!< STBITERR flag clear bit */
+#define SDIO_ICR_DBCKENDC_Pos (10U)
+#define SDIO_ICR_DBCKENDC_Msk (0x1U << SDIO_ICR_DBCKENDC_Pos) /*!< 0x00000400 */
+#define SDIO_ICR_DBCKENDC SDIO_ICR_DBCKENDC_Msk /*!< DBCKEND flag clear bit */
+#define SDIO_ICR_SDIOITC_Pos (22U)
+#define SDIO_ICR_SDIOITC_Msk (0x1U << SDIO_ICR_SDIOITC_Pos) /*!< 0x00400000 */
+#define SDIO_ICR_SDIOITC SDIO_ICR_SDIOITC_Msk /*!< SDIOIT flag clear bit */
+#define SDIO_ICR_CEATAENDC_Pos (23U)
+#define SDIO_ICR_CEATAENDC_Msk (0x1U << SDIO_ICR_CEATAENDC_Pos) /*!< 0x00800000 */
+#define SDIO_ICR_CEATAENDC SDIO_ICR_CEATAENDC_Msk /*!< CEATAEND flag clear bit */
+
+/****************** Bit definition for SDIO_MASK register *******************/
+#define SDIO_MASK_CCRCFAILIE_Pos (0U)
+#define SDIO_MASK_CCRCFAILIE_Msk (0x1U << SDIO_MASK_CCRCFAILIE_Pos) /*!< 0x00000001 */
+#define SDIO_MASK_CCRCFAILIE SDIO_MASK_CCRCFAILIE_Msk /*!< Command CRC Fail Interrupt Enable */
+#define SDIO_MASK_DCRCFAILIE_Pos (1U)
+#define SDIO_MASK_DCRCFAILIE_Msk (0x1U << SDIO_MASK_DCRCFAILIE_Pos) /*!< 0x00000002 */
+#define SDIO_MASK_DCRCFAILIE SDIO_MASK_DCRCFAILIE_Msk /*!< Data CRC Fail Interrupt Enable */
+#define SDIO_MASK_CTIMEOUTIE_Pos (2U)
+#define SDIO_MASK_CTIMEOUTIE_Msk (0x1U << SDIO_MASK_CTIMEOUTIE_Pos) /*!< 0x00000004 */
+#define SDIO_MASK_CTIMEOUTIE SDIO_MASK_CTIMEOUTIE_Msk /*!< Command TimeOut Interrupt Enable */
+#define SDIO_MASK_DTIMEOUTIE_Pos (3U)
+#define SDIO_MASK_DTIMEOUTIE_Msk (0x1U << SDIO_MASK_DTIMEOUTIE_Pos) /*!< 0x00000008 */
+#define SDIO_MASK_DTIMEOUTIE SDIO_MASK_DTIMEOUTIE_Msk /*!< Data TimeOut Interrupt Enable */
+#define SDIO_MASK_TXUNDERRIE_Pos (4U)
+#define SDIO_MASK_TXUNDERRIE_Msk (0x1U << SDIO_MASK_TXUNDERRIE_Pos) /*!< 0x00000010 */
+#define SDIO_MASK_TXUNDERRIE SDIO_MASK_TXUNDERRIE_Msk /*!< Tx FIFO UnderRun Error Interrupt Enable */
+#define SDIO_MASK_RXOVERRIE_Pos (5U)
+#define SDIO_MASK_RXOVERRIE_Msk (0x1U << SDIO_MASK_RXOVERRIE_Pos) /*!< 0x00000020 */
+#define SDIO_MASK_RXOVERRIE SDIO_MASK_RXOVERRIE_Msk /*!< Rx FIFO OverRun Error Interrupt Enable */
+#define SDIO_MASK_CMDRENDIE_Pos (6U)
+#define SDIO_MASK_CMDRENDIE_Msk (0x1U << SDIO_MASK_CMDRENDIE_Pos) /*!< 0x00000040 */
+#define SDIO_MASK_CMDRENDIE SDIO_MASK_CMDRENDIE_Msk /*!< Command Response Received Interrupt Enable */
+#define SDIO_MASK_CMDSENTIE_Pos (7U)
+#define SDIO_MASK_CMDSENTIE_Msk (0x1U << SDIO_MASK_CMDSENTIE_Pos) /*!< 0x00000080 */
+#define SDIO_MASK_CMDSENTIE SDIO_MASK_CMDSENTIE_Msk /*!< Command Sent Interrupt Enable */
+#define SDIO_MASK_DATAENDIE_Pos (8U)
+#define SDIO_MASK_DATAENDIE_Msk (0x1U << SDIO_MASK_DATAENDIE_Pos) /*!< 0x00000100 */
+#define SDIO_MASK_DATAENDIE SDIO_MASK_DATAENDIE_Msk /*!< Data End Interrupt Enable */
+#define SDIO_MASK_STBITERRIE_Pos (9U)
+#define SDIO_MASK_STBITERRIE_Msk (0x1U << SDIO_MASK_STBITERRIE_Pos) /*!< 0x00000200 */
+#define SDIO_MASK_STBITERRIE SDIO_MASK_STBITERRIE_Msk /*!< Start Bit Error Interrupt Enable */
+#define SDIO_MASK_DBCKENDIE_Pos (10U)
+#define SDIO_MASK_DBCKENDIE_Msk (0x1U << SDIO_MASK_DBCKENDIE_Pos) /*!< 0x00000400 */
+#define SDIO_MASK_DBCKENDIE SDIO_MASK_DBCKENDIE_Msk /*!< Data Block End Interrupt Enable */
+#define SDIO_MASK_CMDACTIE_Pos (11U)
+#define SDIO_MASK_CMDACTIE_Msk (0x1U << SDIO_MASK_CMDACTIE_Pos) /*!< 0x00000800 */
+#define SDIO_MASK_CMDACTIE SDIO_MASK_CMDACTIE_Msk /*!< Command Acting Interrupt Enable */
+#define SDIO_MASK_TXACTIE_Pos (12U)
+#define SDIO_MASK_TXACTIE_Msk (0x1U << SDIO_MASK_TXACTIE_Pos) /*!< 0x00001000 */
+#define SDIO_MASK_TXACTIE SDIO_MASK_TXACTIE_Msk /*!< Data Transmit Acting Interrupt Enable */
+#define SDIO_MASK_RXACTIE_Pos (13U)
+#define SDIO_MASK_RXACTIE_Msk (0x1U << SDIO_MASK_RXACTIE_Pos) /*!< 0x00002000 */
+#define SDIO_MASK_RXACTIE SDIO_MASK_RXACTIE_Msk /*!< Data receive acting interrupt enabled */
+#define SDIO_MASK_TXFIFOHEIE_Pos (14U)
+#define SDIO_MASK_TXFIFOHEIE_Msk (0x1U << SDIO_MASK_TXFIFOHEIE_Pos) /*!< 0x00004000 */
+#define SDIO_MASK_TXFIFOHEIE SDIO_MASK_TXFIFOHEIE_Msk /*!< Tx FIFO Half Empty interrupt Enable */
+#define SDIO_MASK_RXFIFOHFIE_Pos (15U)
+#define SDIO_MASK_RXFIFOHFIE_Msk (0x1U << SDIO_MASK_RXFIFOHFIE_Pos) /*!< 0x00008000 */
+#define SDIO_MASK_RXFIFOHFIE SDIO_MASK_RXFIFOHFIE_Msk /*!< Rx FIFO Half Full interrupt Enable */
+#define SDIO_MASK_TXFIFOFIE_Pos (16U)
+#define SDIO_MASK_TXFIFOFIE_Msk (0x1U << SDIO_MASK_TXFIFOFIE_Pos) /*!< 0x00010000 */
+#define SDIO_MASK_TXFIFOFIE SDIO_MASK_TXFIFOFIE_Msk /*!< Tx FIFO Full interrupt Enable */
+#define SDIO_MASK_RXFIFOFIE_Pos (17U)
+#define SDIO_MASK_RXFIFOFIE_Msk (0x1U << SDIO_MASK_RXFIFOFIE_Pos) /*!< 0x00020000 */
+#define SDIO_MASK_RXFIFOFIE SDIO_MASK_RXFIFOFIE_Msk /*!< Rx FIFO Full interrupt Enable */
+#define SDIO_MASK_TXFIFOEIE_Pos (18U)
+#define SDIO_MASK_TXFIFOEIE_Msk (0x1U << SDIO_MASK_TXFIFOEIE_Pos) /*!< 0x00040000 */
+#define SDIO_MASK_TXFIFOEIE SDIO_MASK_TXFIFOEIE_Msk /*!< Tx FIFO Empty interrupt Enable */
+#define SDIO_MASK_RXFIFOEIE_Pos (19U)
+#define SDIO_MASK_RXFIFOEIE_Msk (0x1U << SDIO_MASK_RXFIFOEIE_Pos) /*!< 0x00080000 */
+#define SDIO_MASK_RXFIFOEIE SDIO_MASK_RXFIFOEIE_Msk /*!< Rx FIFO Empty interrupt Enable */
+#define SDIO_MASK_TXDAVLIE_Pos (20U)
+#define SDIO_MASK_TXDAVLIE_Msk (0x1U << SDIO_MASK_TXDAVLIE_Pos) /*!< 0x00100000 */
+#define SDIO_MASK_TXDAVLIE SDIO_MASK_TXDAVLIE_Msk /*!< Data available in Tx FIFO interrupt Enable */
+#define SDIO_MASK_RXDAVLIE_Pos (21U)
+#define SDIO_MASK_RXDAVLIE_Msk (0x1U << SDIO_MASK_RXDAVLIE_Pos) /*!< 0x00200000 */
+#define SDIO_MASK_RXDAVLIE SDIO_MASK_RXDAVLIE_Msk /*!< Data available in Rx FIFO interrupt Enable */
+#define SDIO_MASK_SDIOITIE_Pos (22U)
+#define SDIO_MASK_SDIOITIE_Msk (0x1U << SDIO_MASK_SDIOITIE_Pos) /*!< 0x00400000 */
+#define SDIO_MASK_SDIOITIE SDIO_MASK_SDIOITIE_Msk /*!< SDIO Mode Interrupt Received interrupt Enable */
+#define SDIO_MASK_CEATAENDIE_Pos (23U)
+#define SDIO_MASK_CEATAENDIE_Msk (0x1U << SDIO_MASK_CEATAENDIE_Pos) /*!< 0x00800000 */
+#define SDIO_MASK_CEATAENDIE SDIO_MASK_CEATAENDIE_Msk /*!< CE-ATA command completion signal received Interrupt Enable */
+
+/***************** Bit definition for SDIO_FIFOCNT register *****************/
+#define SDIO_FIFOCNT_FIFOCOUNT_Pos (0U)
+#define SDIO_FIFOCNT_FIFOCOUNT_Msk (0xFFFFFFU << SDIO_FIFOCNT_FIFOCOUNT_Pos) /*!< 0x00FFFFFF */
+#define SDIO_FIFOCNT_FIFOCOUNT SDIO_FIFOCNT_FIFOCOUNT_Msk /*!< Remaining number of words to be written to or read from the FIFO */
+
+/****************** Bit definition for SDIO_FIFO register *******************/
+#define SDIO_FIFO_FIFODATA_Pos (0U)
+#define SDIO_FIFO_FIFODATA_Msk (0xFFFFFFFFU << SDIO_FIFO_FIFODATA_Pos) /*!< 0xFFFFFFFF */
+#define SDIO_FIFO_FIFODATA SDIO_FIFO_FIFODATA_Msk /*!< Receive and transmit FIFO data */
+
+/******************************************************************************/
+/* */
+/* USB Device FS */
+/* */
+/******************************************************************************/
+
+/*!< Endpoint-specific registers */
+#define USB_EP0R USB_BASE /*!< Endpoint 0 register address */
+#define USB_EP1R (USB_BASE + 0x00000004) /*!< Endpoint 1 register address */
+#define USB_EP2R (USB_BASE + 0x00000008) /*!< Endpoint 2 register address */
+#define USB_EP3R (USB_BASE + 0x0000000C) /*!< Endpoint 3 register address */
+#define USB_EP4R (USB_BASE + 0x00000010) /*!< Endpoint 4 register address */
+#define USB_EP5R (USB_BASE + 0x00000014) /*!< Endpoint 5 register address */
+#define USB_EP6R (USB_BASE + 0x00000018) /*!< Endpoint 6 register address */
+#define USB_EP7R (USB_BASE + 0x0000001C) /*!< Endpoint 7 register address */
+
+/* bit positions */
+#define USB_EP_CTR_RX_Pos (15U)
+#define USB_EP_CTR_RX_Msk (0x1U << USB_EP_CTR_RX_Pos) /*!< 0x00008000 */
+#define USB_EP_CTR_RX USB_EP_CTR_RX_Msk /*!< EndPoint Correct TRansfer RX */
+#define USB_EP_DTOG_RX_Pos (14U)
+#define USB_EP_DTOG_RX_Msk (0x1U << USB_EP_DTOG_RX_Pos) /*!< 0x00004000 */
+#define USB_EP_DTOG_RX USB_EP_DTOG_RX_Msk /*!< EndPoint Data TOGGLE RX */
+#define USB_EPRX_STAT_Pos (12U)
+#define USB_EPRX_STAT_Msk (0x3U << USB_EPRX_STAT_Pos) /*!< 0x00003000 */
+#define USB_EPRX_STAT USB_EPRX_STAT_Msk /*!< EndPoint RX STATus bit field */
+#define USB_EP_SETUP_Pos (11U)
+#define USB_EP_SETUP_Msk (0x1U << USB_EP_SETUP_Pos) /*!< 0x00000800 */
+#define USB_EP_SETUP USB_EP_SETUP_Msk /*!< EndPoint SETUP */
+#define USB_EP_T_FIELD_Pos (9U)
+#define USB_EP_T_FIELD_Msk (0x3U << USB_EP_T_FIELD_Pos) /*!< 0x00000600 */
+#define USB_EP_T_FIELD USB_EP_T_FIELD_Msk /*!< EndPoint TYPE */
+#define USB_EP_KIND_Pos (8U)
+#define USB_EP_KIND_Msk (0x1U << USB_EP_KIND_Pos) /*!< 0x00000100 */
+#define USB_EP_KIND USB_EP_KIND_Msk /*!< EndPoint KIND */
+#define USB_EP_CTR_TX_Pos (7U)
+#define USB_EP_CTR_TX_Msk (0x1U << USB_EP_CTR_TX_Pos) /*!< 0x00000080 */
+#define USB_EP_CTR_TX USB_EP_CTR_TX_Msk /*!< EndPoint Correct TRansfer TX */
+#define USB_EP_DTOG_TX_Pos (6U)
+#define USB_EP_DTOG_TX_Msk (0x1U << USB_EP_DTOG_TX_Pos) /*!< 0x00000040 */
+#define USB_EP_DTOG_TX USB_EP_DTOG_TX_Msk /*!< EndPoint Data TOGGLE TX */
+#define USB_EPTX_STAT_Pos (4U)
+#define USB_EPTX_STAT_Msk (0x3U << USB_EPTX_STAT_Pos) /*!< 0x00000030 */
+#define USB_EPTX_STAT USB_EPTX_STAT_Msk /*!< EndPoint TX STATus bit field */
+#define USB_EPADDR_FIELD_Pos (0U)
+#define USB_EPADDR_FIELD_Msk (0xFU << USB_EPADDR_FIELD_Pos) /*!< 0x0000000F */
+#define USB_EPADDR_FIELD USB_EPADDR_FIELD_Msk /*!< EndPoint ADDRess FIELD */
+
+/* EndPoint REGister MASK (no toggle fields) */
+#define USB_EPREG_MASK (USB_EP_CTR_RX|USB_EP_SETUP|USB_EP_T_FIELD|USB_EP_KIND|USB_EP_CTR_TX|USB_EPADDR_FIELD)
+ /*!< EP_TYPE[1:0] EndPoint TYPE */
+#define USB_EP_TYPE_MASK_Pos (9U)
+#define USB_EP_TYPE_MASK_Msk (0x3U << USB_EP_TYPE_MASK_Pos) /*!< 0x00000600 */
+#define USB_EP_TYPE_MASK USB_EP_TYPE_MASK_Msk /*!< EndPoint TYPE Mask */
+#define USB_EP_BULK ((uint32_t)0x00000000) /*!< EndPoint BULK */
+#define USB_EP_CONTROL ((uint32_t)0x00000200) /*!< EndPoint CONTROL */
+#define USB_EP_ISOCHRONOUS ((uint32_t)0x00000400) /*!< EndPoint ISOCHRONOUS */
+#define USB_EP_INTERRUPT ((uint32_t)0x00000600) /*!< EndPoint INTERRUPT */
+#define USB_EP_T_MASK (~USB_EP_T_FIELD & USB_EPREG_MASK)
+
+#define USB_EPKIND_MASK (~USB_EP_KIND & USB_EPREG_MASK) /*!< EP_KIND EndPoint KIND */
+ /*!< STAT_TX[1:0] STATus for TX transfer */
+#define USB_EP_TX_DIS ((uint32_t)0x00000000) /*!< EndPoint TX DISabled */
+#define USB_EP_TX_STALL ((uint32_t)0x00000010) /*!< EndPoint TX STALLed */
+#define USB_EP_TX_NAK ((uint32_t)0x00000020) /*!< EndPoint TX NAKed */
+#define USB_EP_TX_VALID ((uint32_t)0x00000030) /*!< EndPoint TX VALID */
+#define USB_EPTX_DTOG1 ((uint32_t)0x00000010) /*!< EndPoint TX Data TOGgle bit1 */
+#define USB_EPTX_DTOG2 ((uint32_t)0x00000020) /*!< EndPoint TX Data TOGgle bit2 */
+#define USB_EPTX_DTOGMASK (USB_EPTX_STAT|USB_EPREG_MASK)
+ /*!< STAT_RX[1:0] STATus for RX transfer */
+#define USB_EP_RX_DIS ((uint32_t)0x00000000) /*!< EndPoint RX DISabled */
+#define USB_EP_RX_STALL ((uint32_t)0x00001000) /*!< EndPoint RX STALLed */
+#define USB_EP_RX_NAK ((uint32_t)0x00002000) /*!< EndPoint RX NAKed */
+#define USB_EP_RX_VALID ((uint32_t)0x00003000) /*!< EndPoint RX VALID */
+#define USB_EPRX_DTOG1 ((uint32_t)0x00001000) /*!< EndPoint RX Data TOGgle bit1 */
+#define USB_EPRX_DTOG2 ((uint32_t)0x00002000) /*!< EndPoint RX Data TOGgle bit1 */
+#define USB_EPRX_DTOGMASK (USB_EPRX_STAT|USB_EPREG_MASK)
+
+/******************* Bit definition for USB_EP0R register *******************/
+#define USB_EP0R_EA_Pos (0U)
+#define USB_EP0R_EA_Msk (0xFU << USB_EP0R_EA_Pos) /*!< 0x0000000F */
+#define USB_EP0R_EA USB_EP0R_EA_Msk /*!< Endpoint Address */
+
+#define USB_EP0R_STAT_TX_Pos (4U)
+#define USB_EP0R_STAT_TX_Msk (0x3U << USB_EP0R_STAT_TX_Pos) /*!< 0x00000030 */
+#define USB_EP0R_STAT_TX USB_EP0R_STAT_TX_Msk /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */
+#define USB_EP0R_STAT_TX_0 (0x1U << USB_EP0R_STAT_TX_Pos) /*!< 0x00000010 */
+#define USB_EP0R_STAT_TX_1 (0x2U << USB_EP0R_STAT_TX_Pos) /*!< 0x00000020 */
+
+#define USB_EP0R_DTOG_TX_Pos (6U)
+#define USB_EP0R_DTOG_TX_Msk (0x1U << USB_EP0R_DTOG_TX_Pos) /*!< 0x00000040 */
+#define USB_EP0R_DTOG_TX USB_EP0R_DTOG_TX_Msk /*!< Data Toggle, for transmission transfers */
+#define USB_EP0R_CTR_TX_Pos (7U)
+#define USB_EP0R_CTR_TX_Msk (0x1U << USB_EP0R_CTR_TX_Pos) /*!< 0x00000080 */
+#define USB_EP0R_CTR_TX USB_EP0R_CTR_TX_Msk /*!< Correct Transfer for transmission */
+#define USB_EP0R_EP_KIND_Pos (8U)
+#define USB_EP0R_EP_KIND_Msk (0x1U << USB_EP0R_EP_KIND_Pos) /*!< 0x00000100 */
+#define USB_EP0R_EP_KIND USB_EP0R_EP_KIND_Msk /*!< Endpoint Kind */
+
+#define USB_EP0R_EP_TYPE_Pos (9U)
+#define USB_EP0R_EP_TYPE_Msk (0x3U << USB_EP0R_EP_TYPE_Pos) /*!< 0x00000600 */
+#define USB_EP0R_EP_TYPE USB_EP0R_EP_TYPE_Msk /*!< EP_TYPE[1:0] bits (Endpoint type) */
+#define USB_EP0R_EP_TYPE_0 (0x1U << USB_EP0R_EP_TYPE_Pos) /*!< 0x00000200 */
+#define USB_EP0R_EP_TYPE_1 (0x2U << USB_EP0R_EP_TYPE_Pos) /*!< 0x00000400 */
+
+#define USB_EP0R_SETUP_Pos (11U)
+#define USB_EP0R_SETUP_Msk (0x1U << USB_EP0R_SETUP_Pos) /*!< 0x00000800 */
+#define USB_EP0R_SETUP USB_EP0R_SETUP_Msk /*!< Setup transaction completed */
+
+#define USB_EP0R_STAT_RX_Pos (12U)
+#define USB_EP0R_STAT_RX_Msk (0x3U << USB_EP0R_STAT_RX_Pos) /*!< 0x00003000 */
+#define USB_EP0R_STAT_RX USB_EP0R_STAT_RX_Msk /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */
+#define USB_EP0R_STAT_RX_0 (0x1U << USB_EP0R_STAT_RX_Pos) /*!< 0x00001000 */
+#define USB_EP0R_STAT_RX_1 (0x2U << USB_EP0R_STAT_RX_Pos) /*!< 0x00002000 */
+
+#define USB_EP0R_DTOG_RX_Pos (14U)
+#define USB_EP0R_DTOG_RX_Msk (0x1U << USB_EP0R_DTOG_RX_Pos) /*!< 0x00004000 */
+#define USB_EP0R_DTOG_RX USB_EP0R_DTOG_RX_Msk /*!< Data Toggle, for reception transfers */
+#define USB_EP0R_CTR_RX_Pos (15U)
+#define USB_EP0R_CTR_RX_Msk (0x1U << USB_EP0R_CTR_RX_Pos) /*!< 0x00008000 */
+#define USB_EP0R_CTR_RX USB_EP0R_CTR_RX_Msk /*!< Correct Transfer for reception */
+
+/******************* Bit definition for USB_EP1R register *******************/
+#define USB_EP1R_EA_Pos (0U)
+#define USB_EP1R_EA_Msk (0xFU << USB_EP1R_EA_Pos) /*!< 0x0000000F */
+#define USB_EP1R_EA USB_EP1R_EA_Msk /*!< Endpoint Address */
+
+#define USB_EP1R_STAT_TX_Pos (4U)
+#define USB_EP1R_STAT_TX_Msk (0x3U << USB_EP1R_STAT_TX_Pos) /*!< 0x00000030 */
+#define USB_EP1R_STAT_TX USB_EP1R_STAT_TX_Msk /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */
+#define USB_EP1R_STAT_TX_0 (0x1U << USB_EP1R_STAT_TX_Pos) /*!< 0x00000010 */
+#define USB_EP1R_STAT_TX_1 (0x2U << USB_EP1R_STAT_TX_Pos) /*!< 0x00000020 */
+
+#define USB_EP1R_DTOG_TX_Pos (6U)
+#define USB_EP1R_DTOG_TX_Msk (0x1U << USB_EP1R_DTOG_TX_Pos) /*!< 0x00000040 */
+#define USB_EP1R_DTOG_TX USB_EP1R_DTOG_TX_Msk /*!< Data Toggle, for transmission transfers */
+#define USB_EP1R_CTR_TX_Pos (7U)
+#define USB_EP1R_CTR_TX_Msk (0x1U << USB_EP1R_CTR_TX_Pos) /*!< 0x00000080 */
+#define USB_EP1R_CTR_TX USB_EP1R_CTR_TX_Msk /*!< Correct Transfer for transmission */
+#define USB_EP1R_EP_KIND_Pos (8U)
+#define USB_EP1R_EP_KIND_Msk (0x1U << USB_EP1R_EP_KIND_Pos) /*!< 0x00000100 */
+#define USB_EP1R_EP_KIND USB_EP1R_EP_KIND_Msk /*!< Endpoint Kind */
+
+#define USB_EP1R_EP_TYPE_Pos (9U)
+#define USB_EP1R_EP_TYPE_Msk (0x3U << USB_EP1R_EP_TYPE_Pos) /*!< 0x00000600 */
+#define USB_EP1R_EP_TYPE USB_EP1R_EP_TYPE_Msk /*!< EP_TYPE[1:0] bits (Endpoint type) */
+#define USB_EP1R_EP_TYPE_0 (0x1U << USB_EP1R_EP_TYPE_Pos) /*!< 0x00000200 */
+#define USB_EP1R_EP_TYPE_1 (0x2U << USB_EP1R_EP_TYPE_Pos) /*!< 0x00000400 */
+
+#define USB_EP1R_SETUP_Pos (11U)
+#define USB_EP1R_SETUP_Msk (0x1U << USB_EP1R_SETUP_Pos) /*!< 0x00000800 */
+#define USB_EP1R_SETUP USB_EP1R_SETUP_Msk /*!< Setup transaction completed */
+
+#define USB_EP1R_STAT_RX_Pos (12U)
+#define USB_EP1R_STAT_RX_Msk (0x3U << USB_EP1R_STAT_RX_Pos) /*!< 0x00003000 */
+#define USB_EP1R_STAT_RX USB_EP1R_STAT_RX_Msk /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */
+#define USB_EP1R_STAT_RX_0 (0x1U << USB_EP1R_STAT_RX_Pos) /*!< 0x00001000 */
+#define USB_EP1R_STAT_RX_1 (0x2U << USB_EP1R_STAT_RX_Pos) /*!< 0x00002000 */
+
+#define USB_EP1R_DTOG_RX_Pos (14U)
+#define USB_EP1R_DTOG_RX_Msk (0x1U << USB_EP1R_DTOG_RX_Pos) /*!< 0x00004000 */
+#define USB_EP1R_DTOG_RX USB_EP1R_DTOG_RX_Msk /*!< Data Toggle, for reception transfers */
+#define USB_EP1R_CTR_RX_Pos (15U)
+#define USB_EP1R_CTR_RX_Msk (0x1U << USB_EP1R_CTR_RX_Pos) /*!< 0x00008000 */
+#define USB_EP1R_CTR_RX USB_EP1R_CTR_RX_Msk /*!< Correct Transfer for reception */
+
+/******************* Bit definition for USB_EP2R register *******************/
+#define USB_EP2R_EA_Pos (0U)
+#define USB_EP2R_EA_Msk (0xFU << USB_EP2R_EA_Pos) /*!< 0x0000000F */
+#define USB_EP2R_EA USB_EP2R_EA_Msk /*!< Endpoint Address */
+
+#define USB_EP2R_STAT_TX_Pos (4U)
+#define USB_EP2R_STAT_TX_Msk (0x3U << USB_EP2R_STAT_TX_Pos) /*!< 0x00000030 */
+#define USB_EP2R_STAT_TX USB_EP2R_STAT_TX_Msk /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */
+#define USB_EP2R_STAT_TX_0 (0x1U << USB_EP2R_STAT_TX_Pos) /*!< 0x00000010 */
+#define USB_EP2R_STAT_TX_1 (0x2U << USB_EP2R_STAT_TX_Pos) /*!< 0x00000020 */
+
+#define USB_EP2R_DTOG_TX_Pos (6U)
+#define USB_EP2R_DTOG_TX_Msk (0x1U << USB_EP2R_DTOG_TX_Pos) /*!< 0x00000040 */
+#define USB_EP2R_DTOG_TX USB_EP2R_DTOG_TX_Msk /*!< Data Toggle, for transmission transfers */
+#define USB_EP2R_CTR_TX_Pos (7U)
+#define USB_EP2R_CTR_TX_Msk (0x1U << USB_EP2R_CTR_TX_Pos) /*!< 0x00000080 */
+#define USB_EP2R_CTR_TX USB_EP2R_CTR_TX_Msk /*!< Correct Transfer for transmission */
+#define USB_EP2R_EP_KIND_Pos (8U)
+#define USB_EP2R_EP_KIND_Msk (0x1U << USB_EP2R_EP_KIND_Pos) /*!< 0x00000100 */
+#define USB_EP2R_EP_KIND USB_EP2R_EP_KIND_Msk /*!< Endpoint Kind */
+
+#define USB_EP2R_EP_TYPE_Pos (9U)
+#define USB_EP2R_EP_TYPE_Msk (0x3U << USB_EP2R_EP_TYPE_Pos) /*!< 0x00000600 */
+#define USB_EP2R_EP_TYPE USB_EP2R_EP_TYPE_Msk /*!< EP_TYPE[1:0] bits (Endpoint type) */
+#define USB_EP2R_EP_TYPE_0 (0x1U << USB_EP2R_EP_TYPE_Pos) /*!< 0x00000200 */
+#define USB_EP2R_EP_TYPE_1 (0x2U << USB_EP2R_EP_TYPE_Pos) /*!< 0x00000400 */
+
+#define USB_EP2R_SETUP_Pos (11U)
+#define USB_EP2R_SETUP_Msk (0x1U << USB_EP2R_SETUP_Pos) /*!< 0x00000800 */
+#define USB_EP2R_SETUP USB_EP2R_SETUP_Msk /*!< Setup transaction completed */
+
+#define USB_EP2R_STAT_RX_Pos (12U)
+#define USB_EP2R_STAT_RX_Msk (0x3U << USB_EP2R_STAT_RX_Pos) /*!< 0x00003000 */
+#define USB_EP2R_STAT_RX USB_EP2R_STAT_RX_Msk /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */
+#define USB_EP2R_STAT_RX_0 (0x1U << USB_EP2R_STAT_RX_Pos) /*!< 0x00001000 */
+#define USB_EP2R_STAT_RX_1 (0x2U << USB_EP2R_STAT_RX_Pos) /*!< 0x00002000 */
+
+#define USB_EP2R_DTOG_RX_Pos (14U)
+#define USB_EP2R_DTOG_RX_Msk (0x1U << USB_EP2R_DTOG_RX_Pos) /*!< 0x00004000 */
+#define USB_EP2R_DTOG_RX USB_EP2R_DTOG_RX_Msk /*!< Data Toggle, for reception transfers */
+#define USB_EP2R_CTR_RX_Pos (15U)
+#define USB_EP2R_CTR_RX_Msk (0x1U << USB_EP2R_CTR_RX_Pos) /*!< 0x00008000 */
+#define USB_EP2R_CTR_RX USB_EP2R_CTR_RX_Msk /*!< Correct Transfer for reception */
+
+/******************* Bit definition for USB_EP3R register *******************/
+#define USB_EP3R_EA_Pos (0U)
+#define USB_EP3R_EA_Msk (0xFU << USB_EP3R_EA_Pos) /*!< 0x0000000F */
+#define USB_EP3R_EA USB_EP3R_EA_Msk /*!< Endpoint Address */
+
+#define USB_EP3R_STAT_TX_Pos (4U)
+#define USB_EP3R_STAT_TX_Msk (0x3U << USB_EP3R_STAT_TX_Pos) /*!< 0x00000030 */
+#define USB_EP3R_STAT_TX USB_EP3R_STAT_TX_Msk /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */
+#define USB_EP3R_STAT_TX_0 (0x1U << USB_EP3R_STAT_TX_Pos) /*!< 0x00000010 */
+#define USB_EP3R_STAT_TX_1 (0x2U << USB_EP3R_STAT_TX_Pos) /*!< 0x00000020 */
+
+#define USB_EP3R_DTOG_TX_Pos (6U)
+#define USB_EP3R_DTOG_TX_Msk (0x1U << USB_EP3R_DTOG_TX_Pos) /*!< 0x00000040 */
+#define USB_EP3R_DTOG_TX USB_EP3R_DTOG_TX_Msk /*!< Data Toggle, for transmission transfers */
+#define USB_EP3R_CTR_TX_Pos (7U)
+#define USB_EP3R_CTR_TX_Msk (0x1U << USB_EP3R_CTR_TX_Pos) /*!< 0x00000080 */
+#define USB_EP3R_CTR_TX USB_EP3R_CTR_TX_Msk /*!< Correct Transfer for transmission */
+#define USB_EP3R_EP_KIND_Pos (8U)
+#define USB_EP3R_EP_KIND_Msk (0x1U << USB_EP3R_EP_KIND_Pos) /*!< 0x00000100 */
+#define USB_EP3R_EP_KIND USB_EP3R_EP_KIND_Msk /*!< Endpoint Kind */
+
+#define USB_EP3R_EP_TYPE_Pos (9U)
+#define USB_EP3R_EP_TYPE_Msk (0x3U << USB_EP3R_EP_TYPE_Pos) /*!< 0x00000600 */
+#define USB_EP3R_EP_TYPE USB_EP3R_EP_TYPE_Msk /*!< EP_TYPE[1:0] bits (Endpoint type) */
+#define USB_EP3R_EP_TYPE_0 (0x1U << USB_EP3R_EP_TYPE_Pos) /*!< 0x00000200 */
+#define USB_EP3R_EP_TYPE_1 (0x2U << USB_EP3R_EP_TYPE_Pos) /*!< 0x00000400 */
+
+#define USB_EP3R_SETUP_Pos (11U)
+#define USB_EP3R_SETUP_Msk (0x1U << USB_EP3R_SETUP_Pos) /*!< 0x00000800 */
+#define USB_EP3R_SETUP USB_EP3R_SETUP_Msk /*!< Setup transaction completed */
+
+#define USB_EP3R_STAT_RX_Pos (12U)
+#define USB_EP3R_STAT_RX_Msk (0x3U << USB_EP3R_STAT_RX_Pos) /*!< 0x00003000 */
+#define USB_EP3R_STAT_RX USB_EP3R_STAT_RX_Msk /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */
+#define USB_EP3R_STAT_RX_0 (0x1U << USB_EP3R_STAT_RX_Pos) /*!< 0x00001000 */
+#define USB_EP3R_STAT_RX_1 (0x2U << USB_EP3R_STAT_RX_Pos) /*!< 0x00002000 */
+
+#define USB_EP3R_DTOG_RX_Pos (14U)
+#define USB_EP3R_DTOG_RX_Msk (0x1U << USB_EP3R_DTOG_RX_Pos) /*!< 0x00004000 */
+#define USB_EP3R_DTOG_RX USB_EP3R_DTOG_RX_Msk /*!< Data Toggle, for reception transfers */
+#define USB_EP3R_CTR_RX_Pos (15U)
+#define USB_EP3R_CTR_RX_Msk (0x1U << USB_EP3R_CTR_RX_Pos) /*!< 0x00008000 */
+#define USB_EP3R_CTR_RX USB_EP3R_CTR_RX_Msk /*!< Correct Transfer for reception */
+
+/******************* Bit definition for USB_EP4R register *******************/
+#define USB_EP4R_EA_Pos (0U)
+#define USB_EP4R_EA_Msk (0xFU << USB_EP4R_EA_Pos) /*!< 0x0000000F */
+#define USB_EP4R_EA USB_EP4R_EA_Msk /*!< Endpoint Address */
+
+#define USB_EP4R_STAT_TX_Pos (4U)
+#define USB_EP4R_STAT_TX_Msk (0x3U << USB_EP4R_STAT_TX_Pos) /*!< 0x00000030 */
+#define USB_EP4R_STAT_TX USB_EP4R_STAT_TX_Msk /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */
+#define USB_EP4R_STAT_TX_0 (0x1U << USB_EP4R_STAT_TX_Pos) /*!< 0x00000010 */
+#define USB_EP4R_STAT_TX_1 (0x2U << USB_EP4R_STAT_TX_Pos) /*!< 0x00000020 */
+
+#define USB_EP4R_DTOG_TX_Pos (6U)
+#define USB_EP4R_DTOG_TX_Msk (0x1U << USB_EP4R_DTOG_TX_Pos) /*!< 0x00000040 */
+#define USB_EP4R_DTOG_TX USB_EP4R_DTOG_TX_Msk /*!< Data Toggle, for transmission transfers */
+#define USB_EP4R_CTR_TX_Pos (7U)
+#define USB_EP4R_CTR_TX_Msk (0x1U << USB_EP4R_CTR_TX_Pos) /*!< 0x00000080 */
+#define USB_EP4R_CTR_TX USB_EP4R_CTR_TX_Msk /*!< Correct Transfer for transmission */
+#define USB_EP4R_EP_KIND_Pos (8U)
+#define USB_EP4R_EP_KIND_Msk (0x1U << USB_EP4R_EP_KIND_Pos) /*!< 0x00000100 */
+#define USB_EP4R_EP_KIND USB_EP4R_EP_KIND_Msk /*!< Endpoint Kind */
+
+#define USB_EP4R_EP_TYPE_Pos (9U)
+#define USB_EP4R_EP_TYPE_Msk (0x3U << USB_EP4R_EP_TYPE_Pos) /*!< 0x00000600 */
+#define USB_EP4R_EP_TYPE USB_EP4R_EP_TYPE_Msk /*!< EP_TYPE[1:0] bits (Endpoint type) */
+#define USB_EP4R_EP_TYPE_0 (0x1U << USB_EP4R_EP_TYPE_Pos) /*!< 0x00000200 */
+#define USB_EP4R_EP_TYPE_1 (0x2U << USB_EP4R_EP_TYPE_Pos) /*!< 0x00000400 */
+
+#define USB_EP4R_SETUP_Pos (11U)
+#define USB_EP4R_SETUP_Msk (0x1U << USB_EP4R_SETUP_Pos) /*!< 0x00000800 */
+#define USB_EP4R_SETUP USB_EP4R_SETUP_Msk /*!< Setup transaction completed */
+
+#define USB_EP4R_STAT_RX_Pos (12U)
+#define USB_EP4R_STAT_RX_Msk (0x3U << USB_EP4R_STAT_RX_Pos) /*!< 0x00003000 */
+#define USB_EP4R_STAT_RX USB_EP4R_STAT_RX_Msk /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */
+#define USB_EP4R_STAT_RX_0 (0x1U << USB_EP4R_STAT_RX_Pos) /*!< 0x00001000 */
+#define USB_EP4R_STAT_RX_1 (0x2U << USB_EP4R_STAT_RX_Pos) /*!< 0x00002000 */
+
+#define USB_EP4R_DTOG_RX_Pos (14U)
+#define USB_EP4R_DTOG_RX_Msk (0x1U << USB_EP4R_DTOG_RX_Pos) /*!< 0x00004000 */
+#define USB_EP4R_DTOG_RX USB_EP4R_DTOG_RX_Msk /*!< Data Toggle, for reception transfers */
+#define USB_EP4R_CTR_RX_Pos (15U)
+#define USB_EP4R_CTR_RX_Msk (0x1U << USB_EP4R_CTR_RX_Pos) /*!< 0x00008000 */
+#define USB_EP4R_CTR_RX USB_EP4R_CTR_RX_Msk /*!< Correct Transfer for reception */
+
+/******************* Bit definition for USB_EP5R register *******************/
+#define USB_EP5R_EA_Pos (0U)
+#define USB_EP5R_EA_Msk (0xFU << USB_EP5R_EA_Pos) /*!< 0x0000000F */
+#define USB_EP5R_EA USB_EP5R_EA_Msk /*!< Endpoint Address */
+
+#define USB_EP5R_STAT_TX_Pos (4U)
+#define USB_EP5R_STAT_TX_Msk (0x3U << USB_EP5R_STAT_TX_Pos) /*!< 0x00000030 */
+#define USB_EP5R_STAT_TX USB_EP5R_STAT_TX_Msk /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */
+#define USB_EP5R_STAT_TX_0 (0x1U << USB_EP5R_STAT_TX_Pos) /*!< 0x00000010 */
+#define USB_EP5R_STAT_TX_1 (0x2U << USB_EP5R_STAT_TX_Pos) /*!< 0x00000020 */
+
+#define USB_EP5R_DTOG_TX_Pos (6U)
+#define USB_EP5R_DTOG_TX_Msk (0x1U << USB_EP5R_DTOG_TX_Pos) /*!< 0x00000040 */
+#define USB_EP5R_DTOG_TX USB_EP5R_DTOG_TX_Msk /*!< Data Toggle, for transmission transfers */
+#define USB_EP5R_CTR_TX_Pos (7U)
+#define USB_EP5R_CTR_TX_Msk (0x1U << USB_EP5R_CTR_TX_Pos) /*!< 0x00000080 */
+#define USB_EP5R_CTR_TX USB_EP5R_CTR_TX_Msk /*!< Correct Transfer for transmission */
+#define USB_EP5R_EP_KIND_Pos (8U)
+#define USB_EP5R_EP_KIND_Msk (0x1U << USB_EP5R_EP_KIND_Pos) /*!< 0x00000100 */
+#define USB_EP5R_EP_KIND USB_EP5R_EP_KIND_Msk /*!< Endpoint Kind */
+
+#define USB_EP5R_EP_TYPE_Pos (9U)
+#define USB_EP5R_EP_TYPE_Msk (0x3U << USB_EP5R_EP_TYPE_Pos) /*!< 0x00000600 */
+#define USB_EP5R_EP_TYPE USB_EP5R_EP_TYPE_Msk /*!< EP_TYPE[1:0] bits (Endpoint type) */
+#define USB_EP5R_EP_TYPE_0 (0x1U << USB_EP5R_EP_TYPE_Pos) /*!< 0x00000200 */
+#define USB_EP5R_EP_TYPE_1 (0x2U << USB_EP5R_EP_TYPE_Pos) /*!< 0x00000400 */
+
+#define USB_EP5R_SETUP_Pos (11U)
+#define USB_EP5R_SETUP_Msk (0x1U << USB_EP5R_SETUP_Pos) /*!< 0x00000800 */
+#define USB_EP5R_SETUP USB_EP5R_SETUP_Msk /*!< Setup transaction completed */
+
+#define USB_EP5R_STAT_RX_Pos (12U)
+#define USB_EP5R_STAT_RX_Msk (0x3U << USB_EP5R_STAT_RX_Pos) /*!< 0x00003000 */
+#define USB_EP5R_STAT_RX USB_EP5R_STAT_RX_Msk /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */
+#define USB_EP5R_STAT_RX_0 (0x1U << USB_EP5R_STAT_RX_Pos) /*!< 0x00001000 */
+#define USB_EP5R_STAT_RX_1 (0x2U << USB_EP5R_STAT_RX_Pos) /*!< 0x00002000 */
+
+#define USB_EP5R_DTOG_RX_Pos (14U)
+#define USB_EP5R_DTOG_RX_Msk (0x1U << USB_EP5R_DTOG_RX_Pos) /*!< 0x00004000 */
+#define USB_EP5R_DTOG_RX USB_EP5R_DTOG_RX_Msk /*!< Data Toggle, for reception transfers */
+#define USB_EP5R_CTR_RX_Pos (15U)
+#define USB_EP5R_CTR_RX_Msk (0x1U << USB_EP5R_CTR_RX_Pos) /*!< 0x00008000 */
+#define USB_EP5R_CTR_RX USB_EP5R_CTR_RX_Msk /*!< Correct Transfer for reception */
+
+/******************* Bit definition for USB_EP6R register *******************/
+#define USB_EP6R_EA_Pos (0U)
+#define USB_EP6R_EA_Msk (0xFU << USB_EP6R_EA_Pos) /*!< 0x0000000F */
+#define USB_EP6R_EA USB_EP6R_EA_Msk /*!< Endpoint Address */
+
+#define USB_EP6R_STAT_TX_Pos (4U)
+#define USB_EP6R_STAT_TX_Msk (0x3U << USB_EP6R_STAT_TX_Pos) /*!< 0x00000030 */
+#define USB_EP6R_STAT_TX USB_EP6R_STAT_TX_Msk /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */
+#define USB_EP6R_STAT_TX_0 (0x1U << USB_EP6R_STAT_TX_Pos) /*!< 0x00000010 */
+#define USB_EP6R_STAT_TX_1 (0x2U << USB_EP6R_STAT_TX_Pos) /*!< 0x00000020 */
+
+#define USB_EP6R_DTOG_TX_Pos (6U)
+#define USB_EP6R_DTOG_TX_Msk (0x1U << USB_EP6R_DTOG_TX_Pos) /*!< 0x00000040 */
+#define USB_EP6R_DTOG_TX USB_EP6R_DTOG_TX_Msk /*!< Data Toggle, for transmission transfers */
+#define USB_EP6R_CTR_TX_Pos (7U)
+#define USB_EP6R_CTR_TX_Msk (0x1U << USB_EP6R_CTR_TX_Pos) /*!< 0x00000080 */
+#define USB_EP6R_CTR_TX USB_EP6R_CTR_TX_Msk /*!< Correct Transfer for transmission */
+#define USB_EP6R_EP_KIND_Pos (8U)
+#define USB_EP6R_EP_KIND_Msk (0x1U << USB_EP6R_EP_KIND_Pos) /*!< 0x00000100 */
+#define USB_EP6R_EP_KIND USB_EP6R_EP_KIND_Msk /*!< Endpoint Kind */
+
+#define USB_EP6R_EP_TYPE_Pos (9U)
+#define USB_EP6R_EP_TYPE_Msk (0x3U << USB_EP6R_EP_TYPE_Pos) /*!< 0x00000600 */
+#define USB_EP6R_EP_TYPE USB_EP6R_EP_TYPE_Msk /*!< EP_TYPE[1:0] bits (Endpoint type) */
+#define USB_EP6R_EP_TYPE_0 (0x1U << USB_EP6R_EP_TYPE_Pos) /*!< 0x00000200 */
+#define USB_EP6R_EP_TYPE_1 (0x2U << USB_EP6R_EP_TYPE_Pos) /*!< 0x00000400 */
+
+#define USB_EP6R_SETUP_Pos (11U)
+#define USB_EP6R_SETUP_Msk (0x1U << USB_EP6R_SETUP_Pos) /*!< 0x00000800 */
+#define USB_EP6R_SETUP USB_EP6R_SETUP_Msk /*!< Setup transaction completed */
+
+#define USB_EP6R_STAT_RX_Pos (12U)
+#define USB_EP6R_STAT_RX_Msk (0x3U << USB_EP6R_STAT_RX_Pos) /*!< 0x00003000 */
+#define USB_EP6R_STAT_RX USB_EP6R_STAT_RX_Msk /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */
+#define USB_EP6R_STAT_RX_0 (0x1U << USB_EP6R_STAT_RX_Pos) /*!< 0x00001000 */
+#define USB_EP6R_STAT_RX_1 (0x2U << USB_EP6R_STAT_RX_Pos) /*!< 0x00002000 */
+
+#define USB_EP6R_DTOG_RX_Pos (14U)
+#define USB_EP6R_DTOG_RX_Msk (0x1U << USB_EP6R_DTOG_RX_Pos) /*!< 0x00004000 */
+#define USB_EP6R_DTOG_RX USB_EP6R_DTOG_RX_Msk /*!< Data Toggle, for reception transfers */
+#define USB_EP6R_CTR_RX_Pos (15U)
+#define USB_EP6R_CTR_RX_Msk (0x1U << USB_EP6R_CTR_RX_Pos) /*!< 0x00008000 */
+#define USB_EP6R_CTR_RX USB_EP6R_CTR_RX_Msk /*!< Correct Transfer for reception */
+
+/******************* Bit definition for USB_EP7R register *******************/
+#define USB_EP7R_EA_Pos (0U)
+#define USB_EP7R_EA_Msk (0xFU << USB_EP7R_EA_Pos) /*!< 0x0000000F */
+#define USB_EP7R_EA USB_EP7R_EA_Msk /*!< Endpoint Address */
+
+#define USB_EP7R_STAT_TX_Pos (4U)
+#define USB_EP7R_STAT_TX_Msk (0x3U << USB_EP7R_STAT_TX_Pos) /*!< 0x00000030 */
+#define USB_EP7R_STAT_TX USB_EP7R_STAT_TX_Msk /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */
+#define USB_EP7R_STAT_TX_0 (0x1U << USB_EP7R_STAT_TX_Pos) /*!< 0x00000010 */
+#define USB_EP7R_STAT_TX_1 (0x2U << USB_EP7R_STAT_TX_Pos) /*!< 0x00000020 */
+
+#define USB_EP7R_DTOG_TX_Pos (6U)
+#define USB_EP7R_DTOG_TX_Msk (0x1U << USB_EP7R_DTOG_TX_Pos) /*!< 0x00000040 */
+#define USB_EP7R_DTOG_TX USB_EP7R_DTOG_TX_Msk /*!< Data Toggle, for transmission transfers */
+#define USB_EP7R_CTR_TX_Pos (7U)
+#define USB_EP7R_CTR_TX_Msk (0x1U << USB_EP7R_CTR_TX_Pos) /*!< 0x00000080 */
+#define USB_EP7R_CTR_TX USB_EP7R_CTR_TX_Msk /*!< Correct Transfer for transmission */
+#define USB_EP7R_EP_KIND_Pos (8U)
+#define USB_EP7R_EP_KIND_Msk (0x1U << USB_EP7R_EP_KIND_Pos) /*!< 0x00000100 */
+#define USB_EP7R_EP_KIND USB_EP7R_EP_KIND_Msk /*!< Endpoint Kind */
+
+#define USB_EP7R_EP_TYPE_Pos (9U)
+#define USB_EP7R_EP_TYPE_Msk (0x3U << USB_EP7R_EP_TYPE_Pos) /*!< 0x00000600 */
+#define USB_EP7R_EP_TYPE USB_EP7R_EP_TYPE_Msk /*!< EP_TYPE[1:0] bits (Endpoint type) */
+#define USB_EP7R_EP_TYPE_0 (0x1U << USB_EP7R_EP_TYPE_Pos) /*!< 0x00000200 */
+#define USB_EP7R_EP_TYPE_1 (0x2U << USB_EP7R_EP_TYPE_Pos) /*!< 0x00000400 */
+
+#define USB_EP7R_SETUP_Pos (11U)
+#define USB_EP7R_SETUP_Msk (0x1U << USB_EP7R_SETUP_Pos) /*!< 0x00000800 */
+#define USB_EP7R_SETUP USB_EP7R_SETUP_Msk /*!< Setup transaction completed */
+
+#define USB_EP7R_STAT_RX_Pos (12U)
+#define USB_EP7R_STAT_RX_Msk (0x3U << USB_EP7R_STAT_RX_Pos) /*!< 0x00003000 */
+#define USB_EP7R_STAT_RX USB_EP7R_STAT_RX_Msk /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */
+#define USB_EP7R_STAT_RX_0 (0x1U << USB_EP7R_STAT_RX_Pos) /*!< 0x00001000 */
+#define USB_EP7R_STAT_RX_1 (0x2U << USB_EP7R_STAT_RX_Pos) /*!< 0x00002000 */
+
+#define USB_EP7R_DTOG_RX_Pos (14U)
+#define USB_EP7R_DTOG_RX_Msk (0x1U << USB_EP7R_DTOG_RX_Pos) /*!< 0x00004000 */
+#define USB_EP7R_DTOG_RX USB_EP7R_DTOG_RX_Msk /*!< Data Toggle, for reception transfers */
+#define USB_EP7R_CTR_RX_Pos (15U)
+#define USB_EP7R_CTR_RX_Msk (0x1U << USB_EP7R_CTR_RX_Pos) /*!< 0x00008000 */
+#define USB_EP7R_CTR_RX USB_EP7R_CTR_RX_Msk /*!< Correct Transfer for reception */
+
+/*!< Common registers */
+/******************* Bit definition for USB_CNTR register *******************/
+#define USB_CNTR_FRES_Pos (0U)
+#define USB_CNTR_FRES_Msk (0x1U << USB_CNTR_FRES_Pos) /*!< 0x00000001 */
+#define USB_CNTR_FRES USB_CNTR_FRES_Msk /*!< Force USB Reset */
+#define USB_CNTR_PDWN_Pos (1U)
+#define USB_CNTR_PDWN_Msk (0x1U << USB_CNTR_PDWN_Pos) /*!< 0x00000002 */
+#define USB_CNTR_PDWN USB_CNTR_PDWN_Msk /*!< Power down */
+#define USB_CNTR_LP_MODE_Pos (2U)
+#define USB_CNTR_LP_MODE_Msk (0x1U << USB_CNTR_LP_MODE_Pos) /*!< 0x00000004 */
+#define USB_CNTR_LP_MODE USB_CNTR_LP_MODE_Msk /*!< Low-power mode */
+#define USB_CNTR_FSUSP_Pos (3U)
+#define USB_CNTR_FSUSP_Msk (0x1U << USB_CNTR_FSUSP_Pos) /*!< 0x00000008 */
+#define USB_CNTR_FSUSP USB_CNTR_FSUSP_Msk /*!< Force suspend */
+#define USB_CNTR_RESUME_Pos (4U)
+#define USB_CNTR_RESUME_Msk (0x1U << USB_CNTR_RESUME_Pos) /*!< 0x00000010 */
+#define USB_CNTR_RESUME USB_CNTR_RESUME_Msk /*!< Resume request */
+#define USB_CNTR_ESOFM_Pos (8U)
+#define USB_CNTR_ESOFM_Msk (0x1U << USB_CNTR_ESOFM_Pos) /*!< 0x00000100 */
+#define USB_CNTR_ESOFM USB_CNTR_ESOFM_Msk /*!< Expected Start Of Frame Interrupt Mask */
+#define USB_CNTR_SOFM_Pos (9U)
+#define USB_CNTR_SOFM_Msk (0x1U << USB_CNTR_SOFM_Pos) /*!< 0x00000200 */
+#define USB_CNTR_SOFM USB_CNTR_SOFM_Msk /*!< Start Of Frame Interrupt Mask */
+#define USB_CNTR_RESETM_Pos (10U)
+#define USB_CNTR_RESETM_Msk (0x1U << USB_CNTR_RESETM_Pos) /*!< 0x00000400 */
+#define USB_CNTR_RESETM USB_CNTR_RESETM_Msk /*!< RESET Interrupt Mask */
+#define USB_CNTR_SUSPM_Pos (11U)
+#define USB_CNTR_SUSPM_Msk (0x1U << USB_CNTR_SUSPM_Pos) /*!< 0x00000800 */
+#define USB_CNTR_SUSPM USB_CNTR_SUSPM_Msk /*!< Suspend mode Interrupt Mask */
+#define USB_CNTR_WKUPM_Pos (12U)
+#define USB_CNTR_WKUPM_Msk (0x1U << USB_CNTR_WKUPM_Pos) /*!< 0x00001000 */
+#define USB_CNTR_WKUPM USB_CNTR_WKUPM_Msk /*!< Wakeup Interrupt Mask */
+#define USB_CNTR_ERRM_Pos (13U)
+#define USB_CNTR_ERRM_Msk (0x1U << USB_CNTR_ERRM_Pos) /*!< 0x00002000 */
+#define USB_CNTR_ERRM USB_CNTR_ERRM_Msk /*!< Error Interrupt Mask */
+#define USB_CNTR_PMAOVRM_Pos (14U)
+#define USB_CNTR_PMAOVRM_Msk (0x1U << USB_CNTR_PMAOVRM_Pos) /*!< 0x00004000 */
+#define USB_CNTR_PMAOVRM USB_CNTR_PMAOVRM_Msk /*!< Packet Memory Area Over / Underrun Interrupt Mask */
+#define USB_CNTR_CTRM_Pos (15U)
+#define USB_CNTR_CTRM_Msk (0x1U << USB_CNTR_CTRM_Pos) /*!< 0x00008000 */
+#define USB_CNTR_CTRM USB_CNTR_CTRM_Msk /*!< Correct Transfer Interrupt Mask */
+
+/******************* Bit definition for USB_ISTR register *******************/
+#define USB_ISTR_EP_ID_Pos (0U)
+#define USB_ISTR_EP_ID_Msk (0xFU << USB_ISTR_EP_ID_Pos) /*!< 0x0000000F */
+#define USB_ISTR_EP_ID USB_ISTR_EP_ID_Msk /*!< Endpoint Identifier */
+#define USB_ISTR_DIR_Pos (4U)
+#define USB_ISTR_DIR_Msk (0x1U << USB_ISTR_DIR_Pos) /*!< 0x00000010 */
+#define USB_ISTR_DIR USB_ISTR_DIR_Msk /*!< Direction of transaction */
+#define USB_ISTR_ESOF_Pos (8U)
+#define USB_ISTR_ESOF_Msk (0x1U << USB_ISTR_ESOF_Pos) /*!< 0x00000100 */
+#define USB_ISTR_ESOF USB_ISTR_ESOF_Msk /*!< Expected Start Of Frame */
+#define USB_ISTR_SOF_Pos (9U)
+#define USB_ISTR_SOF_Msk (0x1U << USB_ISTR_SOF_Pos) /*!< 0x00000200 */
+#define USB_ISTR_SOF USB_ISTR_SOF_Msk /*!< Start Of Frame */
+#define USB_ISTR_RESET_Pos (10U)
+#define USB_ISTR_RESET_Msk (0x1U << USB_ISTR_RESET_Pos) /*!< 0x00000400 */
+#define USB_ISTR_RESET USB_ISTR_RESET_Msk /*!< USB RESET request */
+#define USB_ISTR_SUSP_Pos (11U)
+#define USB_ISTR_SUSP_Msk (0x1U << USB_ISTR_SUSP_Pos) /*!< 0x00000800 */
+#define USB_ISTR_SUSP USB_ISTR_SUSP_Msk /*!< Suspend mode request */
+#define USB_ISTR_WKUP_Pos (12U)
+#define USB_ISTR_WKUP_Msk (0x1U << USB_ISTR_WKUP_Pos) /*!< 0x00001000 */
+#define USB_ISTR_WKUP USB_ISTR_WKUP_Msk /*!< Wake up */
+#define USB_ISTR_ERR_Pos (13U)
+#define USB_ISTR_ERR_Msk (0x1U << USB_ISTR_ERR_Pos) /*!< 0x00002000 */
+#define USB_ISTR_ERR USB_ISTR_ERR_Msk /*!< Error */
+#define USB_ISTR_PMAOVR_Pos (14U)
+#define USB_ISTR_PMAOVR_Msk (0x1U << USB_ISTR_PMAOVR_Pos) /*!< 0x00004000 */
+#define USB_ISTR_PMAOVR USB_ISTR_PMAOVR_Msk /*!< Packet Memory Area Over / Underrun */
+#define USB_ISTR_CTR_Pos (15U)
+#define USB_ISTR_CTR_Msk (0x1U << USB_ISTR_CTR_Pos) /*!< 0x00008000 */
+#define USB_ISTR_CTR USB_ISTR_CTR_Msk /*!< Correct Transfer */
+
+/******************* Bit definition for USB_FNR register ********************/
+#define USB_FNR_FN_Pos (0U)
+#define USB_FNR_FN_Msk (0x7FFU << USB_FNR_FN_Pos) /*!< 0x000007FF */
+#define USB_FNR_FN USB_FNR_FN_Msk /*!< Frame Number */
+#define USB_FNR_LSOF_Pos (11U)
+#define USB_FNR_LSOF_Msk (0x3U << USB_FNR_LSOF_Pos) /*!< 0x00001800 */
+#define USB_FNR_LSOF USB_FNR_LSOF_Msk /*!< Lost SOF */
+#define USB_FNR_LCK_Pos (13U)
+#define USB_FNR_LCK_Msk (0x1U << USB_FNR_LCK_Pos) /*!< 0x00002000 */
+#define USB_FNR_LCK USB_FNR_LCK_Msk /*!< Locked */
+#define USB_FNR_RXDM_Pos (14U)
+#define USB_FNR_RXDM_Msk (0x1U << USB_FNR_RXDM_Pos) /*!< 0x00004000 */
+#define USB_FNR_RXDM USB_FNR_RXDM_Msk /*!< Receive Data - Line Status */
+#define USB_FNR_RXDP_Pos (15U)
+#define USB_FNR_RXDP_Msk (0x1U << USB_FNR_RXDP_Pos) /*!< 0x00008000 */
+#define USB_FNR_RXDP USB_FNR_RXDP_Msk /*!< Receive Data + Line Status */
+
+/****************** Bit definition for USB_DADDR register *******************/
+#define USB_DADDR_ADD_Pos (0U)
+#define USB_DADDR_ADD_Msk (0x7FU << USB_DADDR_ADD_Pos) /*!< 0x0000007F */
+#define USB_DADDR_ADD USB_DADDR_ADD_Msk /*!< ADD[6:0] bits (Device Address) */
+#define USB_DADDR_ADD0_Pos (0U)
+#define USB_DADDR_ADD0_Msk (0x1U << USB_DADDR_ADD0_Pos) /*!< 0x00000001 */
+#define USB_DADDR_ADD0 USB_DADDR_ADD0_Msk /*!< Bit 0 */
+#define USB_DADDR_ADD1_Pos (1U)
+#define USB_DADDR_ADD1_Msk (0x1U << USB_DADDR_ADD1_Pos) /*!< 0x00000002 */
+#define USB_DADDR_ADD1 USB_DADDR_ADD1_Msk /*!< Bit 1 */
+#define USB_DADDR_ADD2_Pos (2U)
+#define USB_DADDR_ADD2_Msk (0x1U << USB_DADDR_ADD2_Pos) /*!< 0x00000004 */
+#define USB_DADDR_ADD2 USB_DADDR_ADD2_Msk /*!< Bit 2 */
+#define USB_DADDR_ADD3_Pos (3U)
+#define USB_DADDR_ADD3_Msk (0x1U << USB_DADDR_ADD3_Pos) /*!< 0x00000008 */
+#define USB_DADDR_ADD3 USB_DADDR_ADD3_Msk /*!< Bit 3 */
+#define USB_DADDR_ADD4_Pos (4U)
+#define USB_DADDR_ADD4_Msk (0x1U << USB_DADDR_ADD4_Pos) /*!< 0x00000010 */
+#define USB_DADDR_ADD4 USB_DADDR_ADD4_Msk /*!< Bit 4 */
+#define USB_DADDR_ADD5_Pos (5U)
+#define USB_DADDR_ADD5_Msk (0x1U << USB_DADDR_ADD5_Pos) /*!< 0x00000020 */
+#define USB_DADDR_ADD5 USB_DADDR_ADD5_Msk /*!< Bit 5 */
+#define USB_DADDR_ADD6_Pos (6U)
+#define USB_DADDR_ADD6_Msk (0x1U << USB_DADDR_ADD6_Pos) /*!< 0x00000040 */
+#define USB_DADDR_ADD6 USB_DADDR_ADD6_Msk /*!< Bit 6 */
+
+#define USB_DADDR_EF_Pos (7U)
+#define USB_DADDR_EF_Msk (0x1U << USB_DADDR_EF_Pos) /*!< 0x00000080 */
+#define USB_DADDR_EF USB_DADDR_EF_Msk /*!< Enable Function */
+
+/****************** Bit definition for USB_BTABLE register ******************/
+#define USB_BTABLE_BTABLE_Pos (3U)
+#define USB_BTABLE_BTABLE_Msk (0x1FFFU << USB_BTABLE_BTABLE_Pos) /*!< 0x0000FFF8 */
+#define USB_BTABLE_BTABLE USB_BTABLE_BTABLE_Msk /*!< Buffer Table */
+
+/*!< Buffer descriptor table */
+/***************** Bit definition for USB_ADDR0_TX register *****************/
+#define USB_ADDR0_TX_ADDR0_TX_Pos (1U)
+#define USB_ADDR0_TX_ADDR0_TX_Msk (0x7FFFU << USB_ADDR0_TX_ADDR0_TX_Pos) /*!< 0x0000FFFE */
+#define USB_ADDR0_TX_ADDR0_TX USB_ADDR0_TX_ADDR0_TX_Msk /*!< Transmission Buffer Address 0 */
+
+/***************** Bit definition for USB_ADDR1_TX register *****************/
+#define USB_ADDR1_TX_ADDR1_TX_Pos (1U)
+#define USB_ADDR1_TX_ADDR1_TX_Msk (0x7FFFU << USB_ADDR1_TX_ADDR1_TX_Pos) /*!< 0x0000FFFE */
+#define USB_ADDR1_TX_ADDR1_TX USB_ADDR1_TX_ADDR1_TX_Msk /*!< Transmission Buffer Address 1 */
+
+/***************** Bit definition for USB_ADDR2_TX register *****************/
+#define USB_ADDR2_TX_ADDR2_TX_Pos (1U)
+#define USB_ADDR2_TX_ADDR2_TX_Msk (0x7FFFU << USB_ADDR2_TX_ADDR2_TX_Pos) /*!< 0x0000FFFE */
+#define USB_ADDR2_TX_ADDR2_TX USB_ADDR2_TX_ADDR2_TX_Msk /*!< Transmission Buffer Address 2 */
+
+/***************** Bit definition for USB_ADDR3_TX register *****************/
+#define USB_ADDR3_TX_ADDR3_TX_Pos (1U)
+#define USB_ADDR3_TX_ADDR3_TX_Msk (0x7FFFU << USB_ADDR3_TX_ADDR3_TX_Pos) /*!< 0x0000FFFE */
+#define USB_ADDR3_TX_ADDR3_TX USB_ADDR3_TX_ADDR3_TX_Msk /*!< Transmission Buffer Address 3 */
+
+/***************** Bit definition for USB_ADDR4_TX register *****************/
+#define USB_ADDR4_TX_ADDR4_TX_Pos (1U)
+#define USB_ADDR4_TX_ADDR4_TX_Msk (0x7FFFU << USB_ADDR4_TX_ADDR4_TX_Pos) /*!< 0x0000FFFE */
+#define USB_ADDR4_TX_ADDR4_TX USB_ADDR4_TX_ADDR4_TX_Msk /*!< Transmission Buffer Address 4 */
+
+/***************** Bit definition for USB_ADDR5_TX register *****************/
+#define USB_ADDR5_TX_ADDR5_TX_Pos (1U)
+#define USB_ADDR5_TX_ADDR5_TX_Msk (0x7FFFU << USB_ADDR5_TX_ADDR5_TX_Pos) /*!< 0x0000FFFE */
+#define USB_ADDR5_TX_ADDR5_TX USB_ADDR5_TX_ADDR5_TX_Msk /*!< Transmission Buffer Address 5 */
+
+/***************** Bit definition for USB_ADDR6_TX register *****************/
+#define USB_ADDR6_TX_ADDR6_TX_Pos (1U)
+#define USB_ADDR6_TX_ADDR6_TX_Msk (0x7FFFU << USB_ADDR6_TX_ADDR6_TX_Pos) /*!< 0x0000FFFE */
+#define USB_ADDR6_TX_ADDR6_TX USB_ADDR6_TX_ADDR6_TX_Msk /*!< Transmission Buffer Address 6 */
+
+/***************** Bit definition for USB_ADDR7_TX register *****************/
+#define USB_ADDR7_TX_ADDR7_TX_Pos (1U)
+#define USB_ADDR7_TX_ADDR7_TX_Msk (0x7FFFU << USB_ADDR7_TX_ADDR7_TX_Pos) /*!< 0x0000FFFE */
+#define USB_ADDR7_TX_ADDR7_TX USB_ADDR7_TX_ADDR7_TX_Msk /*!< Transmission Buffer Address 7 */
+
+/*----------------------------------------------------------------------------*/
+
+/***************** Bit definition for USB_COUNT0_TX register ****************/
+#define USB_COUNT0_TX_COUNT0_TX_Pos (0U)
+#define USB_COUNT0_TX_COUNT0_TX_Msk (0x3FFU << USB_COUNT0_TX_COUNT0_TX_Pos) /*!< 0x000003FF */
+#define USB_COUNT0_TX_COUNT0_TX USB_COUNT0_TX_COUNT0_TX_Msk /*!< Transmission Byte Count 0 */
+
+/***************** Bit definition for USB_COUNT1_TX register ****************/
+#define USB_COUNT1_TX_COUNT1_TX_Pos (0U)
+#define USB_COUNT1_TX_COUNT1_TX_Msk (0x3FFU << USB_COUNT1_TX_COUNT1_TX_Pos) /*!< 0x000003FF */
+#define USB_COUNT1_TX_COUNT1_TX USB_COUNT1_TX_COUNT1_TX_Msk /*!< Transmission Byte Count 1 */
+
+/***************** Bit definition for USB_COUNT2_TX register ****************/
+#define USB_COUNT2_TX_COUNT2_TX_Pos (0U)
+#define USB_COUNT2_TX_COUNT2_TX_Msk (0x3FFU << USB_COUNT2_TX_COUNT2_TX_Pos) /*!< 0x000003FF */
+#define USB_COUNT2_TX_COUNT2_TX USB_COUNT2_TX_COUNT2_TX_Msk /*!< Transmission Byte Count 2 */
+
+/***************** Bit definition for USB_COUNT3_TX register ****************/
+#define USB_COUNT3_TX_COUNT3_TX_Pos (0U)
+#define USB_COUNT3_TX_COUNT3_TX_Msk (0x3FFU << USB_COUNT3_TX_COUNT3_TX_Pos) /*!< 0x000003FF */
+#define USB_COUNT3_TX_COUNT3_TX USB_COUNT3_TX_COUNT3_TX_Msk /*!< Transmission Byte Count 3 */
+
+/***************** Bit definition for USB_COUNT4_TX register ****************/
+#define USB_COUNT4_TX_COUNT4_TX_Pos (0U)
+#define USB_COUNT4_TX_COUNT4_TX_Msk (0x3FFU << USB_COUNT4_TX_COUNT4_TX_Pos) /*!< 0x000003FF */
+#define USB_COUNT4_TX_COUNT4_TX USB_COUNT4_TX_COUNT4_TX_Msk /*!< Transmission Byte Count 4 */
+
+/***************** Bit definition for USB_COUNT5_TX register ****************/
+#define USB_COUNT5_TX_COUNT5_TX_Pos (0U)
+#define USB_COUNT5_TX_COUNT5_TX_Msk (0x3FFU << USB_COUNT5_TX_COUNT5_TX_Pos) /*!< 0x000003FF */
+#define USB_COUNT5_TX_COUNT5_TX USB_COUNT5_TX_COUNT5_TX_Msk /*!< Transmission Byte Count 5 */
+
+/***************** Bit definition for USB_COUNT6_TX register ****************/
+#define USB_COUNT6_TX_COUNT6_TX_Pos (0U)
+#define USB_COUNT6_TX_COUNT6_TX_Msk (0x3FFU << USB_COUNT6_TX_COUNT6_TX_Pos) /*!< 0x000003FF */
+#define USB_COUNT6_TX_COUNT6_TX USB_COUNT6_TX_COUNT6_TX_Msk /*!< Transmission Byte Count 6 */
+
+/***************** Bit definition for USB_COUNT7_TX register ****************/
+#define USB_COUNT7_TX_COUNT7_TX_Pos (0U)
+#define USB_COUNT7_TX_COUNT7_TX_Msk (0x3FFU << USB_COUNT7_TX_COUNT7_TX_Pos) /*!< 0x000003FF */
+#define USB_COUNT7_TX_COUNT7_TX USB_COUNT7_TX_COUNT7_TX_Msk /*!< Transmission Byte Count 7 */
+
+/*----------------------------------------------------------------------------*/
+
+/**************** Bit definition for USB_COUNT0_TX_0 register ***************/
+#define USB_COUNT0_TX_0_COUNT0_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 0 (low) */
+
+/**************** Bit definition for USB_COUNT0_TX_1 register ***************/
+#define USB_COUNT0_TX_1_COUNT0_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 0 (high) */
+
+/**************** Bit definition for USB_COUNT1_TX_0 register ***************/
+#define USB_COUNT1_TX_0_COUNT1_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 1 (low) */
+
+/**************** Bit definition for USB_COUNT1_TX_1 register ***************/
+#define USB_COUNT1_TX_1_COUNT1_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 1 (high) */
+
+/**************** Bit definition for USB_COUNT2_TX_0 register ***************/
+#define USB_COUNT2_TX_0_COUNT2_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 2 (low) */
+
+/**************** Bit definition for USB_COUNT2_TX_1 register ***************/
+#define USB_COUNT2_TX_1_COUNT2_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 2 (high) */
+
+/**************** Bit definition for USB_COUNT3_TX_0 register ***************/
+#define USB_COUNT3_TX_0_COUNT3_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 3 (low) */
+
+/**************** Bit definition for USB_COUNT3_TX_1 register ***************/
+#define USB_COUNT3_TX_1_COUNT3_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 3 (high) */
+
+/**************** Bit definition for USB_COUNT4_TX_0 register ***************/
+#define USB_COUNT4_TX_0_COUNT4_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 4 (low) */
+
+/**************** Bit definition for USB_COUNT4_TX_1 register ***************/
+#define USB_COUNT4_TX_1_COUNT4_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 4 (high) */
+
+/**************** Bit definition for USB_COUNT5_TX_0 register ***************/
+#define USB_COUNT5_TX_0_COUNT5_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 5 (low) */
+
+/**************** Bit definition for USB_COUNT5_TX_1 register ***************/
+#define USB_COUNT5_TX_1_COUNT5_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 5 (high) */
+
+/**************** Bit definition for USB_COUNT6_TX_0 register ***************/
+#define USB_COUNT6_TX_0_COUNT6_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 6 (low) */
+
+/**************** Bit definition for USB_COUNT6_TX_1 register ***************/
+#define USB_COUNT6_TX_1_COUNT6_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 6 (high) */
+
+/**************** Bit definition for USB_COUNT7_TX_0 register ***************/
+#define USB_COUNT7_TX_0_COUNT7_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 7 (low) */
+
+/**************** Bit definition for USB_COUNT7_TX_1 register ***************/
+#define USB_COUNT7_TX_1_COUNT7_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 7 (high) */
+
+/*----------------------------------------------------------------------------*/
+
+/***************** Bit definition for USB_ADDR0_RX register *****************/
+#define USB_ADDR0_RX_ADDR0_RX_Pos (1U)
+#define USB_ADDR0_RX_ADDR0_RX_Msk (0x7FFFU << USB_ADDR0_RX_ADDR0_RX_Pos) /*!< 0x0000FFFE */
+#define USB_ADDR0_RX_ADDR0_RX USB_ADDR0_RX_ADDR0_RX_Msk /*!< Reception Buffer Address 0 */
+
+/***************** Bit definition for USB_ADDR1_RX register *****************/
+#define USB_ADDR1_RX_ADDR1_RX_Pos (1U)
+#define USB_ADDR1_RX_ADDR1_RX_Msk (0x7FFFU << USB_ADDR1_RX_ADDR1_RX_Pos) /*!< 0x0000FFFE */
+#define USB_ADDR1_RX_ADDR1_RX USB_ADDR1_RX_ADDR1_RX_Msk /*!< Reception Buffer Address 1 */
+
+/***************** Bit definition for USB_ADDR2_RX register *****************/
+#define USB_ADDR2_RX_ADDR2_RX_Pos (1U)
+#define USB_ADDR2_RX_ADDR2_RX_Msk (0x7FFFU << USB_ADDR2_RX_ADDR2_RX_Pos) /*!< 0x0000FFFE */
+#define USB_ADDR2_RX_ADDR2_RX USB_ADDR2_RX_ADDR2_RX_Msk /*!< Reception Buffer Address 2 */
+
+/***************** Bit definition for USB_ADDR3_RX register *****************/
+#define USB_ADDR3_RX_ADDR3_RX_Pos (1U)
+#define USB_ADDR3_RX_ADDR3_RX_Msk (0x7FFFU << USB_ADDR3_RX_ADDR3_RX_Pos) /*!< 0x0000FFFE */
+#define USB_ADDR3_RX_ADDR3_RX USB_ADDR3_RX_ADDR3_RX_Msk /*!< Reception Buffer Address 3 */
+
+/***************** Bit definition for USB_ADDR4_RX register *****************/
+#define USB_ADDR4_RX_ADDR4_RX_Pos (1U)
+#define USB_ADDR4_RX_ADDR4_RX_Msk (0x7FFFU << USB_ADDR4_RX_ADDR4_RX_Pos) /*!< 0x0000FFFE */
+#define USB_ADDR4_RX_ADDR4_RX USB_ADDR4_RX_ADDR4_RX_Msk /*!< Reception Buffer Address 4 */
+
+/***************** Bit definition for USB_ADDR5_RX register *****************/
+#define USB_ADDR5_RX_ADDR5_RX_Pos (1U)
+#define USB_ADDR5_RX_ADDR5_RX_Msk (0x7FFFU << USB_ADDR5_RX_ADDR5_RX_Pos) /*!< 0x0000FFFE */
+#define USB_ADDR5_RX_ADDR5_RX USB_ADDR5_RX_ADDR5_RX_Msk /*!< Reception Buffer Address 5 */
+
+/***************** Bit definition for USB_ADDR6_RX register *****************/
+#define USB_ADDR6_RX_ADDR6_RX_Pos (1U)
+#define USB_ADDR6_RX_ADDR6_RX_Msk (0x7FFFU << USB_ADDR6_RX_ADDR6_RX_Pos) /*!< 0x0000FFFE */
+#define USB_ADDR6_RX_ADDR6_RX USB_ADDR6_RX_ADDR6_RX_Msk /*!< Reception Buffer Address 6 */
+
+/***************** Bit definition for USB_ADDR7_RX register *****************/
+#define USB_ADDR7_RX_ADDR7_RX_Pos (1U)
+#define USB_ADDR7_RX_ADDR7_RX_Msk (0x7FFFU << USB_ADDR7_RX_ADDR7_RX_Pos) /*!< 0x0000FFFE */
+#define USB_ADDR7_RX_ADDR7_RX USB_ADDR7_RX_ADDR7_RX_Msk /*!< Reception Buffer Address 7 */
+
+/*----------------------------------------------------------------------------*/
+
+/***************** Bit definition for USB_COUNT0_RX register ****************/
+#define USB_COUNT0_RX_COUNT0_RX_Pos (0U)
+#define USB_COUNT0_RX_COUNT0_RX_Msk (0x3FFU << USB_COUNT0_RX_COUNT0_RX_Pos) /*!< 0x000003FF */
+#define USB_COUNT0_RX_COUNT0_RX USB_COUNT0_RX_COUNT0_RX_Msk /*!< Reception Byte Count */
+
+#define USB_COUNT0_RX_NUM_BLOCK_Pos (10U)
+#define USB_COUNT0_RX_NUM_BLOCK_Msk (0x1FU << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
+#define USB_COUNT0_RX_NUM_BLOCK USB_COUNT0_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
+#define USB_COUNT0_RX_NUM_BLOCK_0 (0x01U << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
+#define USB_COUNT0_RX_NUM_BLOCK_1 (0x02U << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
+#define USB_COUNT0_RX_NUM_BLOCK_2 (0x04U << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
+#define USB_COUNT0_RX_NUM_BLOCK_3 (0x08U << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
+#define USB_COUNT0_RX_NUM_BLOCK_4 (0x10U << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
+
+#define USB_COUNT0_RX_BLSIZE_Pos (15U)
+#define USB_COUNT0_RX_BLSIZE_Msk (0x1U << USB_COUNT0_RX_BLSIZE_Pos) /*!< 0x00008000 */
+#define USB_COUNT0_RX_BLSIZE USB_COUNT0_RX_BLSIZE_Msk /*!< BLock SIZE */
+
+/***************** Bit definition for USB_COUNT1_RX register ****************/
+#define USB_COUNT1_RX_COUNT1_RX_Pos (0U)
+#define USB_COUNT1_RX_COUNT1_RX_Msk (0x3FFU << USB_COUNT1_RX_COUNT1_RX_Pos) /*!< 0x000003FF */
+#define USB_COUNT1_RX_COUNT1_RX USB_COUNT1_RX_COUNT1_RX_Msk /*!< Reception Byte Count */
+
+#define USB_COUNT1_RX_NUM_BLOCK_Pos (10U)
+#define USB_COUNT1_RX_NUM_BLOCK_Msk (0x1FU << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
+#define USB_COUNT1_RX_NUM_BLOCK USB_COUNT1_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
+#define USB_COUNT1_RX_NUM_BLOCK_0 (0x01U << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
+#define USB_COUNT1_RX_NUM_BLOCK_1 (0x02U << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
+#define USB_COUNT1_RX_NUM_BLOCK_2 (0x04U << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
+#define USB_COUNT1_RX_NUM_BLOCK_3 (0x08U << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
+#define USB_COUNT1_RX_NUM_BLOCK_4 (0x10U << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
+
+#define USB_COUNT1_RX_BLSIZE_Pos (15U)
+#define USB_COUNT1_RX_BLSIZE_Msk (0x1U << USB_COUNT1_RX_BLSIZE_Pos) /*!< 0x00008000 */
+#define USB_COUNT1_RX_BLSIZE USB_COUNT1_RX_BLSIZE_Msk /*!< BLock SIZE */
+
+/***************** Bit definition for USB_COUNT2_RX register ****************/
+#define USB_COUNT2_RX_COUNT2_RX_Pos (0U)
+#define USB_COUNT2_RX_COUNT2_RX_Msk (0x3FFU << USB_COUNT2_RX_COUNT2_RX_Pos) /*!< 0x000003FF */
+#define USB_COUNT2_RX_COUNT2_RX USB_COUNT2_RX_COUNT2_RX_Msk /*!< Reception Byte Count */
+
+#define USB_COUNT2_RX_NUM_BLOCK_Pos (10U)
+#define USB_COUNT2_RX_NUM_BLOCK_Msk (0x1FU << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
+#define USB_COUNT2_RX_NUM_BLOCK USB_COUNT2_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
+#define USB_COUNT2_RX_NUM_BLOCK_0 (0x01U << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
+#define USB_COUNT2_RX_NUM_BLOCK_1 (0x02U << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
+#define USB_COUNT2_RX_NUM_BLOCK_2 (0x04U << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
+#define USB_COUNT2_RX_NUM_BLOCK_3 (0x08U << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
+#define USB_COUNT2_RX_NUM_BLOCK_4 (0x10U << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
+
+#define USB_COUNT2_RX_BLSIZE_Pos (15U)
+#define USB_COUNT2_RX_BLSIZE_Msk (0x1U << USB_COUNT2_RX_BLSIZE_Pos) /*!< 0x00008000 */
+#define USB_COUNT2_RX_BLSIZE USB_COUNT2_RX_BLSIZE_Msk /*!< BLock SIZE */
+
+/***************** Bit definition for USB_COUNT3_RX register ****************/
+#define USB_COUNT3_RX_COUNT3_RX_Pos (0U)
+#define USB_COUNT3_RX_COUNT3_RX_Msk (0x3FFU << USB_COUNT3_RX_COUNT3_RX_Pos) /*!< 0x000003FF */
+#define USB_COUNT3_RX_COUNT3_RX USB_COUNT3_RX_COUNT3_RX_Msk /*!< Reception Byte Count */
+
+#define USB_COUNT3_RX_NUM_BLOCK_Pos (10U)
+#define USB_COUNT3_RX_NUM_BLOCK_Msk (0x1FU << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
+#define USB_COUNT3_RX_NUM_BLOCK USB_COUNT3_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
+#define USB_COUNT3_RX_NUM_BLOCK_0 (0x01U << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
+#define USB_COUNT3_RX_NUM_BLOCK_1 (0x02U << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
+#define USB_COUNT3_RX_NUM_BLOCK_2 (0x04U << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
+#define USB_COUNT3_RX_NUM_BLOCK_3 (0x08U << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
+#define USB_COUNT3_RX_NUM_BLOCK_4 (0x10U << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
+
+#define USB_COUNT3_RX_BLSIZE_Pos (15U)
+#define USB_COUNT3_RX_BLSIZE_Msk (0x1U << USB_COUNT3_RX_BLSIZE_Pos) /*!< 0x00008000 */
+#define USB_COUNT3_RX_BLSIZE USB_COUNT3_RX_BLSIZE_Msk /*!< BLock SIZE */
+
+/***************** Bit definition for USB_COUNT4_RX register ****************/
+#define USB_COUNT4_RX_COUNT4_RX_Pos (0U)
+#define USB_COUNT4_RX_COUNT4_RX_Msk (0x3FFU << USB_COUNT4_RX_COUNT4_RX_Pos) /*!< 0x000003FF */
+#define USB_COUNT4_RX_COUNT4_RX USB_COUNT4_RX_COUNT4_RX_Msk /*!< Reception Byte Count */
+
+#define USB_COUNT4_RX_NUM_BLOCK_Pos (10U)
+#define USB_COUNT4_RX_NUM_BLOCK_Msk (0x1FU << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
+#define USB_COUNT4_RX_NUM_BLOCK USB_COUNT4_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
+#define USB_COUNT4_RX_NUM_BLOCK_0 (0x01U << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
+#define USB_COUNT4_RX_NUM_BLOCK_1 (0x02U << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
+#define USB_COUNT4_RX_NUM_BLOCK_2 (0x04U << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
+#define USB_COUNT4_RX_NUM_BLOCK_3 (0x08U << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
+#define USB_COUNT4_RX_NUM_BLOCK_4 (0x10U << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
+
+#define USB_COUNT4_RX_BLSIZE_Pos (15U)
+#define USB_COUNT4_RX_BLSIZE_Msk (0x1U << USB_COUNT4_RX_BLSIZE_Pos) /*!< 0x00008000 */
+#define USB_COUNT4_RX_BLSIZE USB_COUNT4_RX_BLSIZE_Msk /*!< BLock SIZE */
+
+/***************** Bit definition for USB_COUNT5_RX register ****************/
+#define USB_COUNT5_RX_COUNT5_RX_Pos (0U)
+#define USB_COUNT5_RX_COUNT5_RX_Msk (0x3FFU << USB_COUNT5_RX_COUNT5_RX_Pos) /*!< 0x000003FF */
+#define USB_COUNT5_RX_COUNT5_RX USB_COUNT5_RX_COUNT5_RX_Msk /*!< Reception Byte Count */
+
+#define USB_COUNT5_RX_NUM_BLOCK_Pos (10U)
+#define USB_COUNT5_RX_NUM_BLOCK_Msk (0x1FU << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
+#define USB_COUNT5_RX_NUM_BLOCK USB_COUNT5_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
+#define USB_COUNT5_RX_NUM_BLOCK_0 (0x01U << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
+#define USB_COUNT5_RX_NUM_BLOCK_1 (0x02U << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
+#define USB_COUNT5_RX_NUM_BLOCK_2 (0x04U << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
+#define USB_COUNT5_RX_NUM_BLOCK_3 (0x08U << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
+#define USB_COUNT5_RX_NUM_BLOCK_4 (0x10U << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
+
+#define USB_COUNT5_RX_BLSIZE_Pos (15U)
+#define USB_COUNT5_RX_BLSIZE_Msk (0x1U << USB_COUNT5_RX_BLSIZE_Pos) /*!< 0x00008000 */
+#define USB_COUNT5_RX_BLSIZE USB_COUNT5_RX_BLSIZE_Msk /*!< BLock SIZE */
+
+/***************** Bit definition for USB_COUNT6_RX register ****************/
+#define USB_COUNT6_RX_COUNT6_RX_Pos (0U)
+#define USB_COUNT6_RX_COUNT6_RX_Msk (0x3FFU << USB_COUNT6_RX_COUNT6_RX_Pos) /*!< 0x000003FF */
+#define USB_COUNT6_RX_COUNT6_RX USB_COUNT6_RX_COUNT6_RX_Msk /*!< Reception Byte Count */
+
+#define USB_COUNT6_RX_NUM_BLOCK_Pos (10U)
+#define USB_COUNT6_RX_NUM_BLOCK_Msk (0x1FU << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
+#define USB_COUNT6_RX_NUM_BLOCK USB_COUNT6_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
+#define USB_COUNT6_RX_NUM_BLOCK_0 (0x01U << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
+#define USB_COUNT6_RX_NUM_BLOCK_1 (0x02U << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
+#define USB_COUNT6_RX_NUM_BLOCK_2 (0x04U << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
+#define USB_COUNT6_RX_NUM_BLOCK_3 (0x08U << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
+#define USB_COUNT6_RX_NUM_BLOCK_4 (0x10U << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
+
+#define USB_COUNT6_RX_BLSIZE_Pos (15U)
+#define USB_COUNT6_RX_BLSIZE_Msk (0x1U << USB_COUNT6_RX_BLSIZE_Pos) /*!< 0x00008000 */
+#define USB_COUNT6_RX_BLSIZE USB_COUNT6_RX_BLSIZE_Msk /*!< BLock SIZE */
+
+/***************** Bit definition for USB_COUNT7_RX register ****************/
+#define USB_COUNT7_RX_COUNT7_RX_Pos (0U)
+#define USB_COUNT7_RX_COUNT7_RX_Msk (0x3FFU << USB_COUNT7_RX_COUNT7_RX_Pos) /*!< 0x000003FF */
+#define USB_COUNT7_RX_COUNT7_RX USB_COUNT7_RX_COUNT7_RX_Msk /*!< Reception Byte Count */
+
+#define USB_COUNT7_RX_NUM_BLOCK_Pos (10U)
+#define USB_COUNT7_RX_NUM_BLOCK_Msk (0x1FU << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
+#define USB_COUNT7_RX_NUM_BLOCK USB_COUNT7_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
+#define USB_COUNT7_RX_NUM_BLOCK_0 (0x01U << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
+#define USB_COUNT7_RX_NUM_BLOCK_1 (0x02U << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
+#define USB_COUNT7_RX_NUM_BLOCK_2 (0x04U << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
+#define USB_COUNT7_RX_NUM_BLOCK_3 (0x08U << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
+#define USB_COUNT7_RX_NUM_BLOCK_4 (0x10U << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
+
+#define USB_COUNT7_RX_BLSIZE_Pos (15U)
+#define USB_COUNT7_RX_BLSIZE_Msk (0x1U << USB_COUNT7_RX_BLSIZE_Pos) /*!< 0x00008000 */
+#define USB_COUNT7_RX_BLSIZE USB_COUNT7_RX_BLSIZE_Msk /*!< BLock SIZE */
+
+/*----------------------------------------------------------------------------*/
+
+/**************** Bit definition for USB_COUNT0_RX_0 register ***************/
+#define USB_COUNT0_RX_0_COUNT0_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */
+
+#define USB_COUNT0_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
+#define USB_COUNT0_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */
+#define USB_COUNT0_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */
+#define USB_COUNT0_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */
+#define USB_COUNT0_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */
+#define USB_COUNT0_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */
+
+#define USB_COUNT0_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */
+
+/**************** Bit definition for USB_COUNT0_RX_1 register ***************/
+#define USB_COUNT0_RX_1_COUNT0_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */
+
+#define USB_COUNT0_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
+#define USB_COUNT0_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 1 */
+#define USB_COUNT0_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */
+#define USB_COUNT0_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */
+#define USB_COUNT0_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */
+#define USB_COUNT0_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */
+
+#define USB_COUNT0_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */
+
+/**************** Bit definition for USB_COUNT1_RX_0 register ***************/
+#define USB_COUNT1_RX_0_COUNT1_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */
+
+#define USB_COUNT1_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
+#define USB_COUNT1_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */
+#define USB_COUNT1_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */
+#define USB_COUNT1_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */
+#define USB_COUNT1_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */
+#define USB_COUNT1_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */
+
+#define USB_COUNT1_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */
+
+/**************** Bit definition for USB_COUNT1_RX_1 register ***************/
+#define USB_COUNT1_RX_1_COUNT1_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */
+
+#define USB_COUNT1_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
+#define USB_COUNT1_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */
+#define USB_COUNT1_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */
+#define USB_COUNT1_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */
+#define USB_COUNT1_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */
+#define USB_COUNT1_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */
+
+#define USB_COUNT1_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */
+
+/**************** Bit definition for USB_COUNT2_RX_0 register ***************/
+#define USB_COUNT2_RX_0_COUNT2_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */
+
+#define USB_COUNT2_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
+#define USB_COUNT2_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */
+#define USB_COUNT2_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */
+#define USB_COUNT2_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */
+#define USB_COUNT2_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */
+#define USB_COUNT2_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */
+
+#define USB_COUNT2_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */
+
+/**************** Bit definition for USB_COUNT2_RX_1 register ***************/
+#define USB_COUNT2_RX_1_COUNT2_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */
+
+#define USB_COUNT2_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
+#define USB_COUNT2_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */
+#define USB_COUNT2_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */
+#define USB_COUNT2_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */
+#define USB_COUNT2_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */
+#define USB_COUNT2_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */
+
+#define USB_COUNT2_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */
+
+/**************** Bit definition for USB_COUNT3_RX_0 register ***************/
+#define USB_COUNT3_RX_0_COUNT3_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */
+
+#define USB_COUNT3_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
+#define USB_COUNT3_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */
+#define USB_COUNT3_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */
+#define USB_COUNT3_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */
+#define USB_COUNT3_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */
+#define USB_COUNT3_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */
+
+#define USB_COUNT3_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */
+
+/**************** Bit definition for USB_COUNT3_RX_1 register ***************/
+#define USB_COUNT3_RX_1_COUNT3_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */
+
+#define USB_COUNT3_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
+#define USB_COUNT3_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */
+#define USB_COUNT3_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */
+#define USB_COUNT3_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */
+#define USB_COUNT3_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */
+#define USB_COUNT3_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */
+
+#define USB_COUNT3_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */
+
+/**************** Bit definition for USB_COUNT4_RX_0 register ***************/
+#define USB_COUNT4_RX_0_COUNT4_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */
+
+#define USB_COUNT4_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
+#define USB_COUNT4_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */
+#define USB_COUNT4_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */
+#define USB_COUNT4_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */
+#define USB_COUNT4_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */
+#define USB_COUNT4_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */
+
+#define USB_COUNT4_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */
+
+/**************** Bit definition for USB_COUNT4_RX_1 register ***************/
+#define USB_COUNT4_RX_1_COUNT4_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */
+
+#define USB_COUNT4_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
+#define USB_COUNT4_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */
+#define USB_COUNT4_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */
+#define USB_COUNT4_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */
+#define USB_COUNT4_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */
+#define USB_COUNT4_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */
+
+#define USB_COUNT4_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */
+
+/**************** Bit definition for USB_COUNT5_RX_0 register ***************/
+#define USB_COUNT5_RX_0_COUNT5_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */
+
+#define USB_COUNT5_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
+#define USB_COUNT5_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */
+#define USB_COUNT5_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */
+#define USB_COUNT5_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */
+#define USB_COUNT5_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */
+#define USB_COUNT5_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */
+
+#define USB_COUNT5_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */
+
+/**************** Bit definition for USB_COUNT5_RX_1 register ***************/
+#define USB_COUNT5_RX_1_COUNT5_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */
+
+#define USB_COUNT5_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
+#define USB_COUNT5_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */
+#define USB_COUNT5_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */
+#define USB_COUNT5_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */
+#define USB_COUNT5_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */
+#define USB_COUNT5_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */
+
+#define USB_COUNT5_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */
+
+/*************** Bit definition for USB_COUNT6_RX_0 register ***************/
+#define USB_COUNT6_RX_0_COUNT6_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */
+
+#define USB_COUNT6_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
+#define USB_COUNT6_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */
+#define USB_COUNT6_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */
+#define USB_COUNT6_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */
+#define USB_COUNT6_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */
+#define USB_COUNT6_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */
+
+#define USB_COUNT6_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */
+
+/**************** Bit definition for USB_COUNT6_RX_1 register ***************/
+#define USB_COUNT6_RX_1_COUNT6_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */
+
+#define USB_COUNT6_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
+#define USB_COUNT6_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */
+#define USB_COUNT6_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */
+#define USB_COUNT6_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */
+#define USB_COUNT6_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */
+#define USB_COUNT6_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */
+
+#define USB_COUNT6_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */
+
+/*************** Bit definition for USB_COUNT7_RX_0 register ****************/
+#define USB_COUNT7_RX_0_COUNT7_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */
+
+#define USB_COUNT7_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
+#define USB_COUNT7_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */
+#define USB_COUNT7_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */
+#define USB_COUNT7_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */
+#define USB_COUNT7_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */
+#define USB_COUNT7_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */
+
+#define USB_COUNT7_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */
+
+/*************** Bit definition for USB_COUNT7_RX_1 register ****************/
+#define USB_COUNT7_RX_1_COUNT7_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */
+
+#define USB_COUNT7_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
+#define USB_COUNT7_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */
+#define USB_COUNT7_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */
+#define USB_COUNT7_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */
+#define USB_COUNT7_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */
+#define USB_COUNT7_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */
+
+#define USB_COUNT7_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */
+
+
+/******************************************************************************/
+/* */
+/* Serial Peripheral Interface */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for SPI_CR1 register ********************/
+#define SPI_CR1_CPHA_Pos (0U)
+#define SPI_CR1_CPHA_Msk (0x1U << SPI_CR1_CPHA_Pos) /*!< 0x00000001 */
+#define SPI_CR1_CPHA SPI_CR1_CPHA_Msk /*!< Clock Phase */
+#define SPI_CR1_CPOL_Pos (1U)
+#define SPI_CR1_CPOL_Msk (0x1U << SPI_CR1_CPOL_Pos) /*!< 0x00000002 */
+#define SPI_CR1_CPOL SPI_CR1_CPOL_Msk /*!< Clock Polarity */
+#define SPI_CR1_MSTR_Pos (2U)
+#define SPI_CR1_MSTR_Msk (0x1U << SPI_CR1_MSTR_Pos) /*!< 0x00000004 */
+#define SPI_CR1_MSTR SPI_CR1_MSTR_Msk /*!< Master Selection */
+
+#define SPI_CR1_BR_Pos (3U)
+#define SPI_CR1_BR_Msk (0x7U << SPI_CR1_BR_Pos) /*!< 0x00000038 */
+#define SPI_CR1_BR SPI_CR1_BR_Msk /*!< BR[2:0] bits (Baud Rate Control) */
+#define SPI_CR1_BR_0 (0x1U << SPI_CR1_BR_Pos) /*!< 0x00000008 */
+#define SPI_CR1_BR_1 (0x2U << SPI_CR1_BR_Pos) /*!< 0x00000010 */
+#define SPI_CR1_BR_2 (0x4U << SPI_CR1_BR_Pos) /*!< 0x00000020 */
+
+#define SPI_CR1_SPE_Pos (6U)
+#define SPI_CR1_SPE_Msk (0x1U << SPI_CR1_SPE_Pos) /*!< 0x00000040 */
+#define SPI_CR1_SPE SPI_CR1_SPE_Msk /*!< SPI Enable */
+#define SPI_CR1_LSBFIRST_Pos (7U)
+#define SPI_CR1_LSBFIRST_Msk (0x1U << SPI_CR1_LSBFIRST_Pos) /*!< 0x00000080 */
+#define SPI_CR1_LSBFIRST SPI_CR1_LSBFIRST_Msk /*!< Frame Format */
+#define SPI_CR1_SSI_Pos (8U)
+#define SPI_CR1_SSI_Msk (0x1U << SPI_CR1_SSI_Pos) /*!< 0x00000100 */
+#define SPI_CR1_SSI SPI_CR1_SSI_Msk /*!< Internal slave select */
+#define SPI_CR1_SSM_Pos (9U)
+#define SPI_CR1_SSM_Msk (0x1U << SPI_CR1_SSM_Pos) /*!< 0x00000200 */
+#define SPI_CR1_SSM SPI_CR1_SSM_Msk /*!< Software slave management */
+#define SPI_CR1_RXONLY_Pos (10U)
+#define SPI_CR1_RXONLY_Msk (0x1U << SPI_CR1_RXONLY_Pos) /*!< 0x00000400 */
+#define SPI_CR1_RXONLY SPI_CR1_RXONLY_Msk /*!< Receive only */
+#define SPI_CR1_DFF_Pos (11U)
+#define SPI_CR1_DFF_Msk (0x1U << SPI_CR1_DFF_Pos) /*!< 0x00000800 */
+#define SPI_CR1_DFF SPI_CR1_DFF_Msk /*!< Data Frame Format */
+#define SPI_CR1_CRCNEXT_Pos (12U)
+#define SPI_CR1_CRCNEXT_Msk (0x1U << SPI_CR1_CRCNEXT_Pos) /*!< 0x00001000 */
+#define SPI_CR1_CRCNEXT SPI_CR1_CRCNEXT_Msk /*!< Transmit CRC next */
+#define SPI_CR1_CRCEN_Pos (13U)
+#define SPI_CR1_CRCEN_Msk (0x1U << SPI_CR1_CRCEN_Pos) /*!< 0x00002000 */
+#define SPI_CR1_CRCEN SPI_CR1_CRCEN_Msk /*!< Hardware CRC calculation enable */
+#define SPI_CR1_BIDIOE_Pos (14U)
+#define SPI_CR1_BIDIOE_Msk (0x1U << SPI_CR1_BIDIOE_Pos) /*!< 0x00004000 */
+#define SPI_CR1_BIDIOE SPI_CR1_BIDIOE_Msk /*!< Output enable in bidirectional mode */
+#define SPI_CR1_BIDIMODE_Pos (15U)
+#define SPI_CR1_BIDIMODE_Msk (0x1U << SPI_CR1_BIDIMODE_Pos) /*!< 0x00008000 */
+#define SPI_CR1_BIDIMODE SPI_CR1_BIDIMODE_Msk /*!< Bidirectional data mode enable */
+
+/******************* Bit definition for SPI_CR2 register ********************/
+#define SPI_CR2_RXDMAEN_Pos (0U)
+#define SPI_CR2_RXDMAEN_Msk (0x1U << SPI_CR2_RXDMAEN_Pos) /*!< 0x00000001 */
+#define SPI_CR2_RXDMAEN SPI_CR2_RXDMAEN_Msk /*!< Rx Buffer DMA Enable */
+#define SPI_CR2_TXDMAEN_Pos (1U)
+#define SPI_CR2_TXDMAEN_Msk (0x1U << SPI_CR2_TXDMAEN_Pos) /*!< 0x00000002 */
+#define SPI_CR2_TXDMAEN SPI_CR2_TXDMAEN_Msk /*!< Tx Buffer DMA Enable */
+#define SPI_CR2_SSOE_Pos (2U)
+#define SPI_CR2_SSOE_Msk (0x1U << SPI_CR2_SSOE_Pos) /*!< 0x00000004 */
+#define SPI_CR2_SSOE SPI_CR2_SSOE_Msk /*!< SS Output Enable */
+#define SPI_CR2_ERRIE_Pos (5U)
+#define SPI_CR2_ERRIE_Msk (0x1U << SPI_CR2_ERRIE_Pos) /*!< 0x00000020 */
+#define SPI_CR2_ERRIE SPI_CR2_ERRIE_Msk /*!< Error Interrupt Enable */
+#define SPI_CR2_RXNEIE_Pos (6U)
+#define SPI_CR2_RXNEIE_Msk (0x1U << SPI_CR2_RXNEIE_Pos) /*!< 0x00000040 */
+#define SPI_CR2_RXNEIE SPI_CR2_RXNEIE_Msk /*!< RX buffer Not Empty Interrupt Enable */
+#define SPI_CR2_TXEIE_Pos (7U)
+#define SPI_CR2_TXEIE_Msk (0x1U << SPI_CR2_TXEIE_Pos) /*!< 0x00000080 */
+#define SPI_CR2_TXEIE SPI_CR2_TXEIE_Msk /*!< Tx buffer Empty Interrupt Enable */
+
+/******************** Bit definition for SPI_SR register ********************/
+#define SPI_SR_RXNE_Pos (0U)
+#define SPI_SR_RXNE_Msk (0x1U << SPI_SR_RXNE_Pos) /*!< 0x00000001 */
+#define SPI_SR_RXNE SPI_SR_RXNE_Msk /*!< Receive buffer Not Empty */
+#define SPI_SR_TXE_Pos (1U)
+#define SPI_SR_TXE_Msk (0x1U << SPI_SR_TXE_Pos) /*!< 0x00000002 */
+#define SPI_SR_TXE SPI_SR_TXE_Msk /*!< Transmit buffer Empty */
+#define SPI_SR_CHSIDE_Pos (2U)
+#define SPI_SR_CHSIDE_Msk (0x1U << SPI_SR_CHSIDE_Pos) /*!< 0x00000004 */
+#define SPI_SR_CHSIDE SPI_SR_CHSIDE_Msk /*!< Channel side */
+#define SPI_SR_UDR_Pos (3U)
+#define SPI_SR_UDR_Msk (0x1U << SPI_SR_UDR_Pos) /*!< 0x00000008 */
+#define SPI_SR_UDR SPI_SR_UDR_Msk /*!< Underrun flag */
+#define SPI_SR_CRCERR_Pos (4U)
+#define SPI_SR_CRCERR_Msk (0x1U << SPI_SR_CRCERR_Pos) /*!< 0x00000010 */
+#define SPI_SR_CRCERR SPI_SR_CRCERR_Msk /*!< CRC Error flag */
+#define SPI_SR_MODF_Pos (5U)
+#define SPI_SR_MODF_Msk (0x1U << SPI_SR_MODF_Pos) /*!< 0x00000020 */
+#define SPI_SR_MODF SPI_SR_MODF_Msk /*!< Mode fault */
+#define SPI_SR_OVR_Pos (6U)
+#define SPI_SR_OVR_Msk (0x1U << SPI_SR_OVR_Pos) /*!< 0x00000040 */
+#define SPI_SR_OVR SPI_SR_OVR_Msk /*!< Overrun flag */
+#define SPI_SR_BSY_Pos (7U)
+#define SPI_SR_BSY_Msk (0x1U << SPI_SR_BSY_Pos) /*!< 0x00000080 */
+#define SPI_SR_BSY SPI_SR_BSY_Msk /*!< Busy flag */
+
+/******************** Bit definition for SPI_DR register ********************/
+#define SPI_DR_DR_Pos (0U)
+#define SPI_DR_DR_Msk (0xFFFFU << SPI_DR_DR_Pos) /*!< 0x0000FFFF */
+#define SPI_DR_DR SPI_DR_DR_Msk /*!< Data Register */
+
+/******************* Bit definition for SPI_CRCPR register ******************/
+#define SPI_CRCPR_CRCPOLY_Pos (0U)
+#define SPI_CRCPR_CRCPOLY_Msk (0xFFFFU << SPI_CRCPR_CRCPOLY_Pos) /*!< 0x0000FFFF */
+#define SPI_CRCPR_CRCPOLY SPI_CRCPR_CRCPOLY_Msk /*!< CRC polynomial register */
+
+/****************** Bit definition for SPI_RXCRCR register ******************/
+#define SPI_RXCRCR_RXCRC_Pos (0U)
+#define SPI_RXCRCR_RXCRC_Msk (0xFFFFU << SPI_RXCRCR_RXCRC_Pos) /*!< 0x0000FFFF */
+#define SPI_RXCRCR_RXCRC SPI_RXCRCR_RXCRC_Msk /*!< Rx CRC Register */
+
+/****************** Bit definition for SPI_TXCRCR register ******************/
+#define SPI_TXCRCR_TXCRC_Pos (0U)
+#define SPI_TXCRCR_TXCRC_Msk (0xFFFFU << SPI_TXCRCR_TXCRC_Pos) /*!< 0x0000FFFF */
+#define SPI_TXCRCR_TXCRC SPI_TXCRCR_TXCRC_Msk /*!< Tx CRC Register */
+
+/****************** Bit definition for SPI_I2SCFGR register *****************/
+#define SPI_I2SCFGR_I2SMOD_Pos (11U)
+#define SPI_I2SCFGR_I2SMOD_Msk (0x1U << SPI_I2SCFGR_I2SMOD_Pos) /*!< 0x00000800 */
+#define SPI_I2SCFGR_I2SMOD SPI_I2SCFGR_I2SMOD_Msk /*!< I2S mode selection */
+
+
+/******************************************************************************/
+/* */
+/* Inter-integrated Circuit Interface */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for I2C_CR1 register ********************/
+#define I2C_CR1_PE_Pos (0U)
+#define I2C_CR1_PE_Msk (0x1U << I2C_CR1_PE_Pos) /*!< 0x00000001 */
+#define I2C_CR1_PE I2C_CR1_PE_Msk /*!< Peripheral Enable */
+#define I2C_CR1_SMBUS_Pos (1U)
+#define I2C_CR1_SMBUS_Msk (0x1U << I2C_CR1_SMBUS_Pos) /*!< 0x00000002 */
+#define I2C_CR1_SMBUS I2C_CR1_SMBUS_Msk /*!< SMBus Mode */
+#define I2C_CR1_SMBTYPE_Pos (3U)
+#define I2C_CR1_SMBTYPE_Msk (0x1U << I2C_CR1_SMBTYPE_Pos) /*!< 0x00000008 */
+#define I2C_CR1_SMBTYPE I2C_CR1_SMBTYPE_Msk /*!< SMBus Type */
+#define I2C_CR1_ENARP_Pos (4U)
+#define I2C_CR1_ENARP_Msk (0x1U << I2C_CR1_ENARP_Pos) /*!< 0x00000010 */
+#define I2C_CR1_ENARP I2C_CR1_ENARP_Msk /*!< ARP Enable */
+#define I2C_CR1_ENPEC_Pos (5U)
+#define I2C_CR1_ENPEC_Msk (0x1U << I2C_CR1_ENPEC_Pos) /*!< 0x00000020 */
+#define I2C_CR1_ENPEC I2C_CR1_ENPEC_Msk /*!< PEC Enable */
+#define I2C_CR1_ENGC_Pos (6U)
+#define I2C_CR1_ENGC_Msk (0x1U << I2C_CR1_ENGC_Pos) /*!< 0x00000040 */
+#define I2C_CR1_ENGC I2C_CR1_ENGC_Msk /*!< General Call Enable */
+#define I2C_CR1_NOSTRETCH_Pos (7U)
+#define I2C_CR1_NOSTRETCH_Msk (0x1U << I2C_CR1_NOSTRETCH_Pos) /*!< 0x00000080 */
+#define I2C_CR1_NOSTRETCH I2C_CR1_NOSTRETCH_Msk /*!< Clock Stretching Disable (Slave mode) */
+#define I2C_CR1_START_Pos (8U)
+#define I2C_CR1_START_Msk (0x1U << I2C_CR1_START_Pos) /*!< 0x00000100 */
+#define I2C_CR1_START I2C_CR1_START_Msk /*!< Start Generation */
+#define I2C_CR1_STOP_Pos (9U)
+#define I2C_CR1_STOP_Msk (0x1U << I2C_CR1_STOP_Pos) /*!< 0x00000200 */
+#define I2C_CR1_STOP I2C_CR1_STOP_Msk /*!< Stop Generation */
+#define I2C_CR1_ACK_Pos (10U)
+#define I2C_CR1_ACK_Msk (0x1U << I2C_CR1_ACK_Pos) /*!< 0x00000400 */
+#define I2C_CR1_ACK I2C_CR1_ACK_Msk /*!< Acknowledge Enable */
+#define I2C_CR1_POS_Pos (11U)
+#define I2C_CR1_POS_Msk (0x1U << I2C_CR1_POS_Pos) /*!< 0x00000800 */
+#define I2C_CR1_POS I2C_CR1_POS_Msk /*!< Acknowledge/PEC Position (for data reception) */
+#define I2C_CR1_PEC_Pos (12U)
+#define I2C_CR1_PEC_Msk (0x1U << I2C_CR1_PEC_Pos) /*!< 0x00001000 */
+#define I2C_CR1_PEC I2C_CR1_PEC_Msk /*!< Packet Error Checking */
+#define I2C_CR1_ALERT_Pos (13U)
+#define I2C_CR1_ALERT_Msk (0x1U << I2C_CR1_ALERT_Pos) /*!< 0x00002000 */
+#define I2C_CR1_ALERT I2C_CR1_ALERT_Msk /*!< SMBus Alert */
+#define I2C_CR1_SWRST_Pos (15U)
+#define I2C_CR1_SWRST_Msk (0x1U << I2C_CR1_SWRST_Pos) /*!< 0x00008000 */
+#define I2C_CR1_SWRST I2C_CR1_SWRST_Msk /*!< Software Reset */
+
+/******************* Bit definition for I2C_CR2 register ********************/
+#define I2C_CR2_FREQ_Pos (0U)
+#define I2C_CR2_FREQ_Msk (0x3FU << I2C_CR2_FREQ_Pos) /*!< 0x0000003F */
+#define I2C_CR2_FREQ I2C_CR2_FREQ_Msk /*!< FREQ[5:0] bits (Peripheral Clock Frequency) */
+#define I2C_CR2_FREQ_0 (0x01U << I2C_CR2_FREQ_Pos) /*!< 0x00000001 */
+#define I2C_CR2_FREQ_1 (0x02U << I2C_CR2_FREQ_Pos) /*!< 0x00000002 */
+#define I2C_CR2_FREQ_2 (0x04U << I2C_CR2_FREQ_Pos) /*!< 0x00000004 */
+#define I2C_CR2_FREQ_3 (0x08U << I2C_CR2_FREQ_Pos) /*!< 0x00000008 */
+#define I2C_CR2_FREQ_4 (0x10U << I2C_CR2_FREQ_Pos) /*!< 0x00000010 */
+#define I2C_CR2_FREQ_5 (0x20U << I2C_CR2_FREQ_Pos) /*!< 0x00000020 */
+
+#define I2C_CR2_ITERREN_Pos (8U)
+#define I2C_CR2_ITERREN_Msk (0x1U << I2C_CR2_ITERREN_Pos) /*!< 0x00000100 */
+#define I2C_CR2_ITERREN I2C_CR2_ITERREN_Msk /*!< Error Interrupt Enable */
+#define I2C_CR2_ITEVTEN_Pos (9U)
+#define I2C_CR2_ITEVTEN_Msk (0x1U << I2C_CR2_ITEVTEN_Pos) /*!< 0x00000200 */
+#define I2C_CR2_ITEVTEN I2C_CR2_ITEVTEN_Msk /*!< Event Interrupt Enable */
+#define I2C_CR2_ITBUFEN_Pos (10U)
+#define I2C_CR2_ITBUFEN_Msk (0x1U << I2C_CR2_ITBUFEN_Pos) /*!< 0x00000400 */
+#define I2C_CR2_ITBUFEN I2C_CR2_ITBUFEN_Msk /*!< Buffer Interrupt Enable */
+#define I2C_CR2_DMAEN_Pos (11U)
+#define I2C_CR2_DMAEN_Msk (0x1U << I2C_CR2_DMAEN_Pos) /*!< 0x00000800 */
+#define I2C_CR2_DMAEN I2C_CR2_DMAEN_Msk /*!< DMA Requests Enable */
+#define I2C_CR2_LAST_Pos (12U)
+#define I2C_CR2_LAST_Msk (0x1U << I2C_CR2_LAST_Pos) /*!< 0x00001000 */
+#define I2C_CR2_LAST I2C_CR2_LAST_Msk /*!< DMA Last Transfer */
+
+/******************* Bit definition for I2C_OAR1 register *******************/
+#define I2C_OAR1_ADD1_7 ((uint32_t)0x000000FE) /*!< Interface Address */
+#define I2C_OAR1_ADD8_9 ((uint32_t)0x00000300) /*!< Interface Address */
+
+#define I2C_OAR1_ADD0_Pos (0U)
+#define I2C_OAR1_ADD0_Msk (0x1U << I2C_OAR1_ADD0_Pos) /*!< 0x00000001 */
+#define I2C_OAR1_ADD0 I2C_OAR1_ADD0_Msk /*!< Bit 0 */
+#define I2C_OAR1_ADD1_Pos (1U)
+#define I2C_OAR1_ADD1_Msk (0x1U << I2C_OAR1_ADD1_Pos) /*!< 0x00000002 */
+#define I2C_OAR1_ADD1 I2C_OAR1_ADD1_Msk /*!< Bit 1 */
+#define I2C_OAR1_ADD2_Pos (2U)
+#define I2C_OAR1_ADD2_Msk (0x1U << I2C_OAR1_ADD2_Pos) /*!< 0x00000004 */
+#define I2C_OAR1_ADD2 I2C_OAR1_ADD2_Msk /*!< Bit 2 */
+#define I2C_OAR1_ADD3_Pos (3U)
+#define I2C_OAR1_ADD3_Msk (0x1U << I2C_OAR1_ADD3_Pos) /*!< 0x00000008 */
+#define I2C_OAR1_ADD3 I2C_OAR1_ADD3_Msk /*!< Bit 3 */
+#define I2C_OAR1_ADD4_Pos (4U)
+#define I2C_OAR1_ADD4_Msk (0x1U << I2C_OAR1_ADD4_Pos) /*!< 0x00000010 */
+#define I2C_OAR1_ADD4 I2C_OAR1_ADD4_Msk /*!< Bit 4 */
+#define I2C_OAR1_ADD5_Pos (5U)
+#define I2C_OAR1_ADD5_Msk (0x1U << I2C_OAR1_ADD5_Pos) /*!< 0x00000020 */
+#define I2C_OAR1_ADD5 I2C_OAR1_ADD5_Msk /*!< Bit 5 */
+#define I2C_OAR1_ADD6_Pos (6U)
+#define I2C_OAR1_ADD6_Msk (0x1U << I2C_OAR1_ADD6_Pos) /*!< 0x00000040 */
+#define I2C_OAR1_ADD6 I2C_OAR1_ADD6_Msk /*!< Bit 6 */
+#define I2C_OAR1_ADD7_Pos (7U)
+#define I2C_OAR1_ADD7_Msk (0x1U << I2C_OAR1_ADD7_Pos) /*!< 0x00000080 */
+#define I2C_OAR1_ADD7 I2C_OAR1_ADD7_Msk /*!< Bit 7 */
+#define I2C_OAR1_ADD8_Pos (8U)
+#define I2C_OAR1_ADD8_Msk (0x1U << I2C_OAR1_ADD8_Pos) /*!< 0x00000100 */
+#define I2C_OAR1_ADD8 I2C_OAR1_ADD8_Msk /*!< Bit 8 */
+#define I2C_OAR1_ADD9_Pos (9U)
+#define I2C_OAR1_ADD9_Msk (0x1U << I2C_OAR1_ADD9_Pos) /*!< 0x00000200 */
+#define I2C_OAR1_ADD9 I2C_OAR1_ADD9_Msk /*!< Bit 9 */
+
+#define I2C_OAR1_ADDMODE_Pos (15U)
+#define I2C_OAR1_ADDMODE_Msk (0x1U << I2C_OAR1_ADDMODE_Pos) /*!< 0x00008000 */
+#define I2C_OAR1_ADDMODE I2C_OAR1_ADDMODE_Msk /*!< Addressing Mode (Slave mode) */
+
+/******************* Bit definition for I2C_OAR2 register *******************/
+#define I2C_OAR2_ENDUAL_Pos (0U)
+#define I2C_OAR2_ENDUAL_Msk (0x1U << I2C_OAR2_ENDUAL_Pos) /*!< 0x00000001 */
+#define I2C_OAR2_ENDUAL I2C_OAR2_ENDUAL_Msk /*!< Dual addressing mode enable */
+#define I2C_OAR2_ADD2_Pos (1U)
+#define I2C_OAR2_ADD2_Msk (0x7FU << I2C_OAR2_ADD2_Pos) /*!< 0x000000FE */
+#define I2C_OAR2_ADD2 I2C_OAR2_ADD2_Msk /*!< Interface address */
+
+/******************* Bit definition for I2C_SR1 register ********************/
+#define I2C_SR1_SB_Pos (0U)
+#define I2C_SR1_SB_Msk (0x1U << I2C_SR1_SB_Pos) /*!< 0x00000001 */
+#define I2C_SR1_SB I2C_SR1_SB_Msk /*!< Start Bit (Master mode) */
+#define I2C_SR1_ADDR_Pos (1U)
+#define I2C_SR1_ADDR_Msk (0x1U << I2C_SR1_ADDR_Pos) /*!< 0x00000002 */
+#define I2C_SR1_ADDR I2C_SR1_ADDR_Msk /*!< Address sent (master mode)/matched (slave mode) */
+#define I2C_SR1_BTF_Pos (2U)
+#define I2C_SR1_BTF_Msk (0x1U << I2C_SR1_BTF_Pos) /*!< 0x00000004 */
+#define I2C_SR1_BTF I2C_SR1_BTF_Msk /*!< Byte Transfer Finished */
+#define I2C_SR1_ADD10_Pos (3U)
+#define I2C_SR1_ADD10_Msk (0x1U << I2C_SR1_ADD10_Pos) /*!< 0x00000008 */
+#define I2C_SR1_ADD10 I2C_SR1_ADD10_Msk /*!< 10-bit header sent (Master mode) */
+#define I2C_SR1_STOPF_Pos (4U)
+#define I2C_SR1_STOPF_Msk (0x1U << I2C_SR1_STOPF_Pos) /*!< 0x00000010 */
+#define I2C_SR1_STOPF I2C_SR1_STOPF_Msk /*!< Stop detection (Slave mode) */
+#define I2C_SR1_RXNE_Pos (6U)
+#define I2C_SR1_RXNE_Msk (0x1U << I2C_SR1_RXNE_Pos) /*!< 0x00000040 */
+#define I2C_SR1_RXNE I2C_SR1_RXNE_Msk /*!< Data Register not Empty (receivers) */
+#define I2C_SR1_TXE_Pos (7U)
+#define I2C_SR1_TXE_Msk (0x1U << I2C_SR1_TXE_Pos) /*!< 0x00000080 */
+#define I2C_SR1_TXE I2C_SR1_TXE_Msk /*!< Data Register Empty (transmitters) */
+#define I2C_SR1_BERR_Pos (8U)
+#define I2C_SR1_BERR_Msk (0x1U << I2C_SR1_BERR_Pos) /*!< 0x00000100 */
+#define I2C_SR1_BERR I2C_SR1_BERR_Msk /*!< Bus Error */
+#define I2C_SR1_ARLO_Pos (9U)
+#define I2C_SR1_ARLO_Msk (0x1U << I2C_SR1_ARLO_Pos) /*!< 0x00000200 */
+#define I2C_SR1_ARLO I2C_SR1_ARLO_Msk /*!< Arbitration Lost (master mode) */
+#define I2C_SR1_AF_Pos (10U)
+#define I2C_SR1_AF_Msk (0x1U << I2C_SR1_AF_Pos) /*!< 0x00000400 */
+#define I2C_SR1_AF I2C_SR1_AF_Msk /*!< Acknowledge Failure */
+#define I2C_SR1_OVR_Pos (11U)
+#define I2C_SR1_OVR_Msk (0x1U << I2C_SR1_OVR_Pos) /*!< 0x00000800 */
+#define I2C_SR1_OVR I2C_SR1_OVR_Msk /*!< Overrun/Underrun */
+#define I2C_SR1_PECERR_Pos (12U)
+#define I2C_SR1_PECERR_Msk (0x1U << I2C_SR1_PECERR_Pos) /*!< 0x00001000 */
+#define I2C_SR1_PECERR I2C_SR1_PECERR_Msk /*!< PEC Error in reception */
+#define I2C_SR1_TIMEOUT_Pos (14U)
+#define I2C_SR1_TIMEOUT_Msk (0x1U << I2C_SR1_TIMEOUT_Pos) /*!< 0x00004000 */
+#define I2C_SR1_TIMEOUT I2C_SR1_TIMEOUT_Msk /*!< Timeout or Tlow Error */
+#define I2C_SR1_SMBALERT_Pos (15U)
+#define I2C_SR1_SMBALERT_Msk (0x1U << I2C_SR1_SMBALERT_Pos) /*!< 0x00008000 */
+#define I2C_SR1_SMBALERT I2C_SR1_SMBALERT_Msk /*!< SMBus Alert */
+
+/******************* Bit definition for I2C_SR2 register ********************/
+#define I2C_SR2_MSL_Pos (0U)
+#define I2C_SR2_MSL_Msk (0x1U << I2C_SR2_MSL_Pos) /*!< 0x00000001 */
+#define I2C_SR2_MSL I2C_SR2_MSL_Msk /*!< Master/Slave */
+#define I2C_SR2_BUSY_Pos (1U)
+#define I2C_SR2_BUSY_Msk (0x1U << I2C_SR2_BUSY_Pos) /*!< 0x00000002 */
+#define I2C_SR2_BUSY I2C_SR2_BUSY_Msk /*!< Bus Busy */
+#define I2C_SR2_TRA_Pos (2U)
+#define I2C_SR2_TRA_Msk (0x1U << I2C_SR2_TRA_Pos) /*!< 0x00000004 */
+#define I2C_SR2_TRA I2C_SR2_TRA_Msk /*!< Transmitter/Receiver */
+#define I2C_SR2_GENCALL_Pos (4U)
+#define I2C_SR2_GENCALL_Msk (0x1U << I2C_SR2_GENCALL_Pos) /*!< 0x00000010 */
+#define I2C_SR2_GENCALL I2C_SR2_GENCALL_Msk /*!< General Call Address (Slave mode) */
+#define I2C_SR2_SMBDEFAULT_Pos (5U)
+#define I2C_SR2_SMBDEFAULT_Msk (0x1U << I2C_SR2_SMBDEFAULT_Pos) /*!< 0x00000020 */
+#define I2C_SR2_SMBDEFAULT I2C_SR2_SMBDEFAULT_Msk /*!< SMBus Device Default Address (Slave mode) */
+#define I2C_SR2_SMBHOST_Pos (6U)
+#define I2C_SR2_SMBHOST_Msk (0x1U << I2C_SR2_SMBHOST_Pos) /*!< 0x00000040 */
+#define I2C_SR2_SMBHOST I2C_SR2_SMBHOST_Msk /*!< SMBus Host Header (Slave mode) */
+#define I2C_SR2_DUALF_Pos (7U)
+#define I2C_SR2_DUALF_Msk (0x1U << I2C_SR2_DUALF_Pos) /*!< 0x00000080 */
+#define I2C_SR2_DUALF I2C_SR2_DUALF_Msk /*!< Dual Flag (Slave mode) */
+#define I2C_SR2_PEC_Pos (8U)
+#define I2C_SR2_PEC_Msk (0xFFU << I2C_SR2_PEC_Pos) /*!< 0x0000FF00 */
+#define I2C_SR2_PEC I2C_SR2_PEC_Msk /*!< Packet Error Checking Register */
+
+/******************* Bit definition for I2C_CCR register ********************/
+#define I2C_CCR_CCR_Pos (0U)
+#define I2C_CCR_CCR_Msk (0xFFFU << I2C_CCR_CCR_Pos) /*!< 0x00000FFF */
+#define I2C_CCR_CCR I2C_CCR_CCR_Msk /*!< Clock Control Register in Fast/Standard mode (Master mode) */
+#define I2C_CCR_DUTY_Pos (14U)
+#define I2C_CCR_DUTY_Msk (0x1U << I2C_CCR_DUTY_Pos) /*!< 0x00004000 */
+#define I2C_CCR_DUTY I2C_CCR_DUTY_Msk /*!< Fast Mode Duty Cycle */
+#define I2C_CCR_FS_Pos (15U)
+#define I2C_CCR_FS_Msk (0x1U << I2C_CCR_FS_Pos) /*!< 0x00008000 */
+#define I2C_CCR_FS I2C_CCR_FS_Msk /*!< I2C Master Mode Selection */
+
+/****************** Bit definition for I2C_TRISE register *******************/
+#define I2C_TRISE_TRISE_Pos (0U)
+#define I2C_TRISE_TRISE_Msk (0x3FU << I2C_TRISE_TRISE_Pos) /*!< 0x0000003F */
+#define I2C_TRISE_TRISE I2C_TRISE_TRISE_Msk /*!< Maximum Rise Time in Fast/Standard mode (Master mode) */
+
+/******************************************************************************/
+/* */
+/* Universal Synchronous Asynchronous Receiver Transmitter */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for USART_SR register *******************/
+#define USART_SR_PE_Pos (0U)
+#define USART_SR_PE_Msk (0x1U << USART_SR_PE_Pos) /*!< 0x00000001 */
+#define USART_SR_PE USART_SR_PE_Msk /*!< Parity Error */
+#define USART_SR_FE_Pos (1U)
+#define USART_SR_FE_Msk (0x1U << USART_SR_FE_Pos) /*!< 0x00000002 */
+#define USART_SR_FE USART_SR_FE_Msk /*!< Framing Error */
+#define USART_SR_NE_Pos (2U)
+#define USART_SR_NE_Msk (0x1U << USART_SR_NE_Pos) /*!< 0x00000004 */
+#define USART_SR_NE USART_SR_NE_Msk /*!< Noise Error Flag */
+#define USART_SR_ORE_Pos (3U)
+#define USART_SR_ORE_Msk (0x1U << USART_SR_ORE_Pos) /*!< 0x00000008 */
+#define USART_SR_ORE USART_SR_ORE_Msk /*!< OverRun Error */
+#define USART_SR_IDLE_Pos (4U)
+#define USART_SR_IDLE_Msk (0x1U << USART_SR_IDLE_Pos) /*!< 0x00000010 */
+#define USART_SR_IDLE USART_SR_IDLE_Msk /*!< IDLE line detected */
+#define USART_SR_RXNE_Pos (5U)
+#define USART_SR_RXNE_Msk (0x1U << USART_SR_RXNE_Pos) /*!< 0x00000020 */
+#define USART_SR_RXNE USART_SR_RXNE_Msk /*!< Read Data Register Not Empty */
+#define USART_SR_TC_Pos (6U)
+#define USART_SR_TC_Msk (0x1U << USART_SR_TC_Pos) /*!< 0x00000040 */
+#define USART_SR_TC USART_SR_TC_Msk /*!< Transmission Complete */
+#define USART_SR_TXE_Pos (7U)
+#define USART_SR_TXE_Msk (0x1U << USART_SR_TXE_Pos) /*!< 0x00000080 */
+#define USART_SR_TXE USART_SR_TXE_Msk /*!< Transmit Data Register Empty */
+#define USART_SR_LBD_Pos (8U)
+#define USART_SR_LBD_Msk (0x1U << USART_SR_LBD_Pos) /*!< 0x00000100 */
+#define USART_SR_LBD USART_SR_LBD_Msk /*!< LIN Break Detection Flag */
+#define USART_SR_CTS_Pos (9U)
+#define USART_SR_CTS_Msk (0x1U << USART_SR_CTS_Pos) /*!< 0x00000200 */
+#define USART_SR_CTS USART_SR_CTS_Msk /*!< CTS Flag */
+
+/******************* Bit definition for USART_DR register *******************/
+#define USART_DR_DR_Pos (0U)
+#define USART_DR_DR_Msk (0x1FFU << USART_DR_DR_Pos) /*!< 0x000001FF */
+#define USART_DR_DR USART_DR_DR_Msk /*!< Data value */
+
+/****************** Bit definition for USART_BRR register *******************/
+#define USART_BRR_DIV_Fraction_Pos (0U)
+#define USART_BRR_DIV_Fraction_Msk (0xFU << USART_BRR_DIV_Fraction_Pos) /*!< 0x0000000F */
+#define USART_BRR_DIV_Fraction USART_BRR_DIV_Fraction_Msk /*!< Fraction of USARTDIV */
+#define USART_BRR_DIV_Mantissa_Pos (4U)
+#define USART_BRR_DIV_Mantissa_Msk (0xFFFU << USART_BRR_DIV_Mantissa_Pos) /*!< 0x0000FFF0 */
+#define USART_BRR_DIV_Mantissa USART_BRR_DIV_Mantissa_Msk /*!< Mantissa of USARTDIV */
+
+/****************** Bit definition for USART_CR1 register *******************/
+#define USART_CR1_SBK_Pos (0U)
+#define USART_CR1_SBK_Msk (0x1U << USART_CR1_SBK_Pos) /*!< 0x00000001 */
+#define USART_CR1_SBK USART_CR1_SBK_Msk /*!< Send Break */
+#define USART_CR1_RWU_Pos (1U)
+#define USART_CR1_RWU_Msk (0x1U << USART_CR1_RWU_Pos) /*!< 0x00000002 */
+#define USART_CR1_RWU USART_CR1_RWU_Msk /*!< Receiver wakeup */
+#define USART_CR1_RE_Pos (2U)
+#define USART_CR1_RE_Msk (0x1U << USART_CR1_RE_Pos) /*!< 0x00000004 */
+#define USART_CR1_RE USART_CR1_RE_Msk /*!< Receiver Enable */
+#define USART_CR1_TE_Pos (3U)
+#define USART_CR1_TE_Msk (0x1U << USART_CR1_TE_Pos) /*!< 0x00000008 */
+#define USART_CR1_TE USART_CR1_TE_Msk /*!< Transmitter Enable */
+#define USART_CR1_IDLEIE_Pos (4U)
+#define USART_CR1_IDLEIE_Msk (0x1U << USART_CR1_IDLEIE_Pos) /*!< 0x00000010 */
+#define USART_CR1_IDLEIE USART_CR1_IDLEIE_Msk /*!< IDLE Interrupt Enable */
+#define USART_CR1_RXNEIE_Pos (5U)
+#define USART_CR1_RXNEIE_Msk (0x1U << USART_CR1_RXNEIE_Pos) /*!< 0x00000020 */
+#define USART_CR1_RXNEIE USART_CR1_RXNEIE_Msk /*!< RXNE Interrupt Enable */
+#define USART_CR1_TCIE_Pos (6U)
+#define USART_CR1_TCIE_Msk (0x1U << USART_CR1_TCIE_Pos) /*!< 0x00000040 */
+#define USART_CR1_TCIE USART_CR1_TCIE_Msk /*!< Transmission Complete Interrupt Enable */
+#define USART_CR1_TXEIE_Pos (7U)
+#define USART_CR1_TXEIE_Msk (0x1U << USART_CR1_TXEIE_Pos) /*!< 0x00000080 */
+#define USART_CR1_TXEIE USART_CR1_TXEIE_Msk /*!< PE Interrupt Enable */
+#define USART_CR1_PEIE_Pos (8U)
+#define USART_CR1_PEIE_Msk (0x1U << USART_CR1_PEIE_Pos) /*!< 0x00000100 */
+#define USART_CR1_PEIE USART_CR1_PEIE_Msk /*!< PE Interrupt Enable */
+#define USART_CR1_PS_Pos (9U)
+#define USART_CR1_PS_Msk (0x1U << USART_CR1_PS_Pos) /*!< 0x00000200 */
+#define USART_CR1_PS USART_CR1_PS_Msk /*!< Parity Selection */
+#define USART_CR1_PCE_Pos (10U)
+#define USART_CR1_PCE_Msk (0x1U << USART_CR1_PCE_Pos) /*!< 0x00000400 */
+#define USART_CR1_PCE USART_CR1_PCE_Msk /*!< Parity Control Enable */
+#define USART_CR1_WAKE_Pos (11U)
+#define USART_CR1_WAKE_Msk (0x1U << USART_CR1_WAKE_Pos) /*!< 0x00000800 */
+#define USART_CR1_WAKE USART_CR1_WAKE_Msk /*!< Wakeup method */
+#define USART_CR1_M_Pos (12U)
+#define USART_CR1_M_Msk (0x1U << USART_CR1_M_Pos) /*!< 0x00001000 */
+#define USART_CR1_M USART_CR1_M_Msk /*!< Word length */
+#define USART_CR1_UE_Pos (13U)
+#define USART_CR1_UE_Msk (0x1U << USART_CR1_UE_Pos) /*!< 0x00002000 */
+#define USART_CR1_UE USART_CR1_UE_Msk /*!< USART Enable */
+
+/****************** Bit definition for USART_CR2 register *******************/
+#define USART_CR2_ADD_Pos (0U)
+#define USART_CR2_ADD_Msk (0xFU << USART_CR2_ADD_Pos) /*!< 0x0000000F */
+#define USART_CR2_ADD USART_CR2_ADD_Msk /*!< Address of the USART node */
+#define USART_CR2_LBDL_Pos (5U)
+#define USART_CR2_LBDL_Msk (0x1U << USART_CR2_LBDL_Pos) /*!< 0x00000020 */
+#define USART_CR2_LBDL USART_CR2_LBDL_Msk /*!< LIN Break Detection Length */
+#define USART_CR2_LBDIE_Pos (6U)
+#define USART_CR2_LBDIE_Msk (0x1U << USART_CR2_LBDIE_Pos) /*!< 0x00000040 */
+#define USART_CR2_LBDIE USART_CR2_LBDIE_Msk /*!< LIN Break Detection Interrupt Enable */
+#define USART_CR2_LBCL_Pos (8U)
+#define USART_CR2_LBCL_Msk (0x1U << USART_CR2_LBCL_Pos) /*!< 0x00000100 */
+#define USART_CR2_LBCL USART_CR2_LBCL_Msk /*!< Last Bit Clock pulse */
+#define USART_CR2_CPHA_Pos (9U)
+#define USART_CR2_CPHA_Msk (0x1U << USART_CR2_CPHA_Pos) /*!< 0x00000200 */
+#define USART_CR2_CPHA USART_CR2_CPHA_Msk /*!< Clock Phase */
+#define USART_CR2_CPOL_Pos (10U)
+#define USART_CR2_CPOL_Msk (0x1U << USART_CR2_CPOL_Pos) /*!< 0x00000400 */
+#define USART_CR2_CPOL USART_CR2_CPOL_Msk /*!< Clock Polarity */
+#define USART_CR2_CLKEN_Pos (11U)
+#define USART_CR2_CLKEN_Msk (0x1U << USART_CR2_CLKEN_Pos) /*!< 0x00000800 */
+#define USART_CR2_CLKEN USART_CR2_CLKEN_Msk /*!< Clock Enable */
+
+#define USART_CR2_STOP_Pos (12U)
+#define USART_CR2_STOP_Msk (0x3U << USART_CR2_STOP_Pos) /*!< 0x00003000 */
+#define USART_CR2_STOP USART_CR2_STOP_Msk /*!< STOP[1:0] bits (STOP bits) */
+#define USART_CR2_STOP_0 (0x1U << USART_CR2_STOP_Pos) /*!< 0x00001000 */
+#define USART_CR2_STOP_1 (0x2U << USART_CR2_STOP_Pos) /*!< 0x00002000 */
+
+#define USART_CR2_LINEN_Pos (14U)
+#define USART_CR2_LINEN_Msk (0x1U << USART_CR2_LINEN_Pos) /*!< 0x00004000 */
+#define USART_CR2_LINEN USART_CR2_LINEN_Msk /*!< LIN mode enable */
+
+/****************** Bit definition for USART_CR3 register *******************/
+#define USART_CR3_EIE_Pos (0U)
+#define USART_CR3_EIE_Msk (0x1U << USART_CR3_EIE_Pos) /*!< 0x00000001 */
+#define USART_CR3_EIE USART_CR3_EIE_Msk /*!< Error Interrupt Enable */
+#define USART_CR3_IREN_Pos (1U)
+#define USART_CR3_IREN_Msk (0x1U << USART_CR3_IREN_Pos) /*!< 0x00000002 */
+#define USART_CR3_IREN USART_CR3_IREN_Msk /*!< IrDA mode Enable */
+#define USART_CR3_IRLP_Pos (2U)
+#define USART_CR3_IRLP_Msk (0x1U << USART_CR3_IRLP_Pos) /*!< 0x00000004 */
+#define USART_CR3_IRLP USART_CR3_IRLP_Msk /*!< IrDA Low-Power */
+#define USART_CR3_HDSEL_Pos (3U)
+#define USART_CR3_HDSEL_Msk (0x1U << USART_CR3_HDSEL_Pos) /*!< 0x00000008 */
+#define USART_CR3_HDSEL USART_CR3_HDSEL_Msk /*!< Half-Duplex Selection */
+#define USART_CR3_NACK_Pos (4U)
+#define USART_CR3_NACK_Msk (0x1U << USART_CR3_NACK_Pos) /*!< 0x00000010 */
+#define USART_CR3_NACK USART_CR3_NACK_Msk /*!< Smartcard NACK enable */
+#define USART_CR3_SCEN_Pos (5U)
+#define USART_CR3_SCEN_Msk (0x1U << USART_CR3_SCEN_Pos) /*!< 0x00000020 */
+#define USART_CR3_SCEN USART_CR3_SCEN_Msk /*!< Smartcard mode enable */
+#define USART_CR3_DMAR_Pos (6U)
+#define USART_CR3_DMAR_Msk (0x1U << USART_CR3_DMAR_Pos) /*!< 0x00000040 */
+#define USART_CR3_DMAR USART_CR3_DMAR_Msk /*!< DMA Enable Receiver */
+#define USART_CR3_DMAT_Pos (7U)
+#define USART_CR3_DMAT_Msk (0x1U << USART_CR3_DMAT_Pos) /*!< 0x00000080 */
+#define USART_CR3_DMAT USART_CR3_DMAT_Msk /*!< DMA Enable Transmitter */
+#define USART_CR3_RTSE_Pos (8U)
+#define USART_CR3_RTSE_Msk (0x1U << USART_CR3_RTSE_Pos) /*!< 0x00000100 */
+#define USART_CR3_RTSE USART_CR3_RTSE_Msk /*!< RTS Enable */
+#define USART_CR3_CTSE_Pos (9U)
+#define USART_CR3_CTSE_Msk (0x1U << USART_CR3_CTSE_Pos) /*!< 0x00000200 */
+#define USART_CR3_CTSE USART_CR3_CTSE_Msk /*!< CTS Enable */
+#define USART_CR3_CTSIE_Pos (10U)
+#define USART_CR3_CTSIE_Msk (0x1U << USART_CR3_CTSIE_Pos) /*!< 0x00000400 */
+#define USART_CR3_CTSIE USART_CR3_CTSIE_Msk /*!< CTS Interrupt Enable */
+
+/****************** Bit definition for USART_GTPR register ******************/
+#define USART_GTPR_PSC_Pos (0U)
+#define USART_GTPR_PSC_Msk (0xFFU << USART_GTPR_PSC_Pos) /*!< 0x000000FF */
+#define USART_GTPR_PSC USART_GTPR_PSC_Msk /*!< PSC[7:0] bits (Prescaler value) */
+#define USART_GTPR_PSC_0 (0x01U << USART_GTPR_PSC_Pos) /*!< 0x00000001 */
+#define USART_GTPR_PSC_1 (0x02U << USART_GTPR_PSC_Pos) /*!< 0x00000002 */
+#define USART_GTPR_PSC_2 (0x04U << USART_GTPR_PSC_Pos) /*!< 0x00000004 */
+#define USART_GTPR_PSC_3 (0x08U << USART_GTPR_PSC_Pos) /*!< 0x00000008 */
+#define USART_GTPR_PSC_4 (0x10U << USART_GTPR_PSC_Pos) /*!< 0x00000010 */
+#define USART_GTPR_PSC_5 (0x20U << USART_GTPR_PSC_Pos) /*!< 0x00000020 */
+#define USART_GTPR_PSC_6 (0x40U << USART_GTPR_PSC_Pos) /*!< 0x00000040 */
+#define USART_GTPR_PSC_7 (0x80U << USART_GTPR_PSC_Pos) /*!< 0x00000080 */
+
+#define USART_GTPR_GT_Pos (8U)
+#define USART_GTPR_GT_Msk (0xFFU << USART_GTPR_GT_Pos) /*!< 0x0000FF00 */
+#define USART_GTPR_GT USART_GTPR_GT_Msk /*!< Guard time value */
+
+/******************************************************************************/
+/* */
+/* Debug MCU */
+/* */
+/******************************************************************************/
+
+/**************** Bit definition for DBGMCU_IDCODE register *****************/
+#define DBGMCU_IDCODE_DEV_ID_Pos (0U)
+#define DBGMCU_IDCODE_DEV_ID_Msk (0xFFFU << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */
+#define DBGMCU_IDCODE_DEV_ID DBGMCU_IDCODE_DEV_ID_Msk /*!< Device Identifier */
+
+#define DBGMCU_IDCODE_REV_ID_Pos (16U)
+#define DBGMCU_IDCODE_REV_ID_Msk (0xFFFFU << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */
+#define DBGMCU_IDCODE_REV_ID DBGMCU_IDCODE_REV_ID_Msk /*!< REV_ID[15:0] bits (Revision Identifier) */
+#define DBGMCU_IDCODE_REV_ID_0 (0x0001U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00010000 */
+#define DBGMCU_IDCODE_REV_ID_1 (0x0002U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00020000 */
+#define DBGMCU_IDCODE_REV_ID_2 (0x0004U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00040000 */
+#define DBGMCU_IDCODE_REV_ID_3 (0x0008U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00080000 */
+#define DBGMCU_IDCODE_REV_ID_4 (0x0010U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00100000 */
+#define DBGMCU_IDCODE_REV_ID_5 (0x0020U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00200000 */
+#define DBGMCU_IDCODE_REV_ID_6 (0x0040U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00400000 */
+#define DBGMCU_IDCODE_REV_ID_7 (0x0080U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00800000 */
+#define DBGMCU_IDCODE_REV_ID_8 (0x0100U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x01000000 */
+#define DBGMCU_IDCODE_REV_ID_9 (0x0200U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x02000000 */
+#define DBGMCU_IDCODE_REV_ID_10 (0x0400U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x04000000 */
+#define DBGMCU_IDCODE_REV_ID_11 (0x0800U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x08000000 */
+#define DBGMCU_IDCODE_REV_ID_12 (0x1000U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x10000000 */
+#define DBGMCU_IDCODE_REV_ID_13 (0x2000U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x20000000 */
+#define DBGMCU_IDCODE_REV_ID_14 (0x4000U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x40000000 */
+#define DBGMCU_IDCODE_REV_ID_15 (0x8000U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x80000000 */
+
+/****************** Bit definition for DBGMCU_CR register *******************/
+#define DBGMCU_CR_DBG_SLEEP_Pos (0U)
+#define DBGMCU_CR_DBG_SLEEP_Msk (0x1U << DBGMCU_CR_DBG_SLEEP_Pos) /*!< 0x00000001 */
+#define DBGMCU_CR_DBG_SLEEP DBGMCU_CR_DBG_SLEEP_Msk /*!< Debug Sleep Mode */
+#define DBGMCU_CR_DBG_STOP_Pos (1U)
+#define DBGMCU_CR_DBG_STOP_Msk (0x1U << DBGMCU_CR_DBG_STOP_Pos) /*!< 0x00000002 */
+#define DBGMCU_CR_DBG_STOP DBGMCU_CR_DBG_STOP_Msk /*!< Debug Stop Mode */
+#define DBGMCU_CR_DBG_STANDBY_Pos (2U)
+#define DBGMCU_CR_DBG_STANDBY_Msk (0x1U << DBGMCU_CR_DBG_STANDBY_Pos) /*!< 0x00000004 */
+#define DBGMCU_CR_DBG_STANDBY DBGMCU_CR_DBG_STANDBY_Msk /*!< Debug Standby mode */
+#define DBGMCU_CR_TRACE_IOEN_Pos (5U)
+#define DBGMCU_CR_TRACE_IOEN_Msk (0x1U << DBGMCU_CR_TRACE_IOEN_Pos) /*!< 0x00000020 */
+#define DBGMCU_CR_TRACE_IOEN DBGMCU_CR_TRACE_IOEN_Msk /*!< Trace Pin Assignment Control */
+
+#define DBGMCU_CR_TRACE_MODE_Pos (6U)
+#define DBGMCU_CR_TRACE_MODE_Msk (0x3U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x000000C0 */
+#define DBGMCU_CR_TRACE_MODE DBGMCU_CR_TRACE_MODE_Msk /*!< TRACE_MODE[1:0] bits (Trace Pin Assignment Control) */
+#define DBGMCU_CR_TRACE_MODE_0 (0x1U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000040 */
+#define DBGMCU_CR_TRACE_MODE_1 (0x2U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000080 */
+
+#define DBGMCU_CR_DBG_IWDG_STOP_Pos (8U)
+#define DBGMCU_CR_DBG_IWDG_STOP_Msk (0x1U << DBGMCU_CR_DBG_IWDG_STOP_Pos) /*!< 0x00000100 */
+#define DBGMCU_CR_DBG_IWDG_STOP DBGMCU_CR_DBG_IWDG_STOP_Msk /*!< Debug Independent Watchdog stopped when Core is halted */
+#define DBGMCU_CR_DBG_WWDG_STOP_Pos (9U)
+#define DBGMCU_CR_DBG_WWDG_STOP_Msk (0x1U << DBGMCU_CR_DBG_WWDG_STOP_Pos) /*!< 0x00000200 */
+#define DBGMCU_CR_DBG_WWDG_STOP DBGMCU_CR_DBG_WWDG_STOP_Msk /*!< Debug Window Watchdog stopped when Core is halted */
+#define DBGMCU_CR_DBG_TIM2_STOP_Pos (11U)
+#define DBGMCU_CR_DBG_TIM2_STOP_Msk (0x1U << DBGMCU_CR_DBG_TIM2_STOP_Pos) /*!< 0x00000800 */
+#define DBGMCU_CR_DBG_TIM2_STOP DBGMCU_CR_DBG_TIM2_STOP_Msk /*!< TIM2 counter stopped when core is halted */
+#define DBGMCU_CR_DBG_TIM3_STOP_Pos (12U)
+#define DBGMCU_CR_DBG_TIM3_STOP_Msk (0x1U << DBGMCU_CR_DBG_TIM3_STOP_Pos) /*!< 0x00001000 */
+#define DBGMCU_CR_DBG_TIM3_STOP DBGMCU_CR_DBG_TIM3_STOP_Msk /*!< TIM3 counter stopped when core is halted */
+#define DBGMCU_CR_DBG_TIM4_STOP_Pos (13U)
+#define DBGMCU_CR_DBG_TIM4_STOP_Msk (0x1U << DBGMCU_CR_DBG_TIM4_STOP_Pos) /*!< 0x00002000 */
+#define DBGMCU_CR_DBG_TIM4_STOP DBGMCU_CR_DBG_TIM4_STOP_Msk /*!< TIM4 counter stopped when core is halted */
+#define DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT_Pos (15U)
+#define DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT_Msk (0x1U << DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT_Pos) /*!< 0x00008000 */
+#define DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT_Msk /*!< SMBUS timeout mode stopped when Core is halted */
+#define DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT_Pos (16U)
+#define DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT_Msk (0x1U << DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT_Pos) /*!< 0x00010000 */
+#define DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT_Msk /*!< SMBUS timeout mode stopped when Core is halted */
+
+/******************************************************************************/
+/* */
+/* FLASH and Option Bytes Registers */
+/* */
+/******************************************************************************/
+/******************* Bit definition for FLASH_ACR register ******************/
+#define FLASH_ACR_LATENCY_Pos (0U)
+#define FLASH_ACR_LATENCY_Msk (0x7U << FLASH_ACR_LATENCY_Pos) /*!< 0x00000007 */
+#define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk /*!< LATENCY[2:0] bits (Latency) */
+#define FLASH_ACR_LATENCY_0 (0x1U << FLASH_ACR_LATENCY_Pos) /*!< 0x00000001 */
+#define FLASH_ACR_LATENCY_1 (0x2U << FLASH_ACR_LATENCY_Pos) /*!< 0x00000002 */
+#define FLASH_ACR_LATENCY_2 (0x4U << FLASH_ACR_LATENCY_Pos) /*!< 0x00000004 */
+
+#define FLASH_ACR_HLFCYA_Pos (3U)
+#define FLASH_ACR_HLFCYA_Msk (0x1U << FLASH_ACR_HLFCYA_Pos) /*!< 0x00000008 */
+#define FLASH_ACR_HLFCYA FLASH_ACR_HLFCYA_Msk /*!< Flash Half Cycle Access Enable */
+#define FLASH_ACR_PRFTBE_Pos (4U)
+#define FLASH_ACR_PRFTBE_Msk (0x1U << FLASH_ACR_PRFTBE_Pos) /*!< 0x00000010 */
+#define FLASH_ACR_PRFTBE FLASH_ACR_PRFTBE_Msk /*!< Prefetch Buffer Enable */
+#define FLASH_ACR_PRFTBS_Pos (5U)
+#define FLASH_ACR_PRFTBS_Msk (0x1U << FLASH_ACR_PRFTBS_Pos) /*!< 0x00000020 */
+#define FLASH_ACR_PRFTBS FLASH_ACR_PRFTBS_Msk /*!< Prefetch Buffer Status */
+
+/****************** Bit definition for FLASH_KEYR register ******************/
+#define FLASH_KEYR_FKEYR_Pos (0U)
+#define FLASH_KEYR_FKEYR_Msk (0xFFFFFFFFU << FLASH_KEYR_FKEYR_Pos) /*!< 0xFFFFFFFF */
+#define FLASH_KEYR_FKEYR FLASH_KEYR_FKEYR_Msk /*!< FPEC Key */
+
+#define RDP_KEY_Pos (0U)
+#define RDP_KEY_Msk (0xA5U << RDP_KEY_Pos) /*!< 0x000000A5 */
+#define RDP_KEY RDP_KEY_Msk /*!< RDP Key */
+#define FLASH_KEY1_Pos (0U)
+#define FLASH_KEY1_Msk (0x45670123U << FLASH_KEY1_Pos) /*!< 0x45670123 */
+#define FLASH_KEY1 FLASH_KEY1_Msk /*!< FPEC Key1 */
+#define FLASH_KEY2_Pos (0U)
+#define FLASH_KEY2_Msk (0xCDEF89ABU << FLASH_KEY2_Pos) /*!< 0xCDEF89AB */
+#define FLASH_KEY2 FLASH_KEY2_Msk /*!< FPEC Key2 */
+
+/***************** Bit definition for FLASH_OPTKEYR register ****************/
+#define FLASH_OPTKEYR_OPTKEYR_Pos (0U)
+#define FLASH_OPTKEYR_OPTKEYR_Msk (0xFFFFFFFFU << FLASH_OPTKEYR_OPTKEYR_Pos) /*!< 0xFFFFFFFF */
+#define FLASH_OPTKEYR_OPTKEYR FLASH_OPTKEYR_OPTKEYR_Msk /*!< Option Byte Key */
+
+#define FLASH_OPTKEY1 FLASH_KEY1 /*!< Option Byte Key1 */
+#define FLASH_OPTKEY2 FLASH_KEY2 /*!< Option Byte Key2 */
+
+/****************** Bit definition for FLASH_SR register ********************/
+#define FLASH_SR_BSY_Pos (0U)
+#define FLASH_SR_BSY_Msk (0x1U << FLASH_SR_BSY_Pos) /*!< 0x00000001 */
+#define FLASH_SR_BSY FLASH_SR_BSY_Msk /*!< Busy */
+#define FLASH_SR_PGERR_Pos (2U)
+#define FLASH_SR_PGERR_Msk (0x1U << FLASH_SR_PGERR_Pos) /*!< 0x00000004 */
+#define FLASH_SR_PGERR FLASH_SR_PGERR_Msk /*!< Programming Error */
+#define FLASH_SR_WRPRTERR_Pos (4U)
+#define FLASH_SR_WRPRTERR_Msk (0x1U << FLASH_SR_WRPRTERR_Pos) /*!< 0x00000010 */
+#define FLASH_SR_WRPRTERR FLASH_SR_WRPRTERR_Msk /*!< Write Protection Error */
+#define FLASH_SR_EOP_Pos (5U)
+#define FLASH_SR_EOP_Msk (0x1U << FLASH_SR_EOP_Pos) /*!< 0x00000020 */
+#define FLASH_SR_EOP FLASH_SR_EOP_Msk /*!< End of operation */
+
+/******************* Bit definition for FLASH_CR register *******************/
+#define FLASH_CR_PG_Pos (0U)
+#define FLASH_CR_PG_Msk (0x1U << FLASH_CR_PG_Pos) /*!< 0x00000001 */
+#define FLASH_CR_PG FLASH_CR_PG_Msk /*!< Programming */
+#define FLASH_CR_PER_Pos (1U)
+#define FLASH_CR_PER_Msk (0x1U << FLASH_CR_PER_Pos) /*!< 0x00000002 */
+#define FLASH_CR_PER FLASH_CR_PER_Msk /*!< Page Erase */
+#define FLASH_CR_MER_Pos (2U)
+#define FLASH_CR_MER_Msk (0x1U << FLASH_CR_MER_Pos) /*!< 0x00000004 */
+#define FLASH_CR_MER FLASH_CR_MER_Msk /*!< Mass Erase */
+#define FLASH_CR_OPTPG_Pos (4U)
+#define FLASH_CR_OPTPG_Msk (0x1U << FLASH_CR_OPTPG_Pos) /*!< 0x00000010 */
+#define FLASH_CR_OPTPG FLASH_CR_OPTPG_Msk /*!< Option Byte Programming */
+#define FLASH_CR_OPTER_Pos (5U)
+#define FLASH_CR_OPTER_Msk (0x1U << FLASH_CR_OPTER_Pos) /*!< 0x00000020 */
+#define FLASH_CR_OPTER FLASH_CR_OPTER_Msk /*!< Option Byte Erase */
+#define FLASH_CR_STRT_Pos (6U)
+#define FLASH_CR_STRT_Msk (0x1U << FLASH_CR_STRT_Pos) /*!< 0x00000040 */
+#define FLASH_CR_STRT FLASH_CR_STRT_Msk /*!< Start */
+#define FLASH_CR_LOCK_Pos (7U)
+#define FLASH_CR_LOCK_Msk (0x1U << FLASH_CR_LOCK_Pos) /*!< 0x00000080 */
+#define FLASH_CR_LOCK FLASH_CR_LOCK_Msk /*!< Lock */
+#define FLASH_CR_OPTWRE_Pos (9U)
+#define FLASH_CR_OPTWRE_Msk (0x1U << FLASH_CR_OPTWRE_Pos) /*!< 0x00000200 */
+#define FLASH_CR_OPTWRE FLASH_CR_OPTWRE_Msk /*!< Option Bytes Write Enable */
+#define FLASH_CR_ERRIE_Pos (10U)
+#define FLASH_CR_ERRIE_Msk (0x1U << FLASH_CR_ERRIE_Pos) /*!< 0x00000400 */
+#define FLASH_CR_ERRIE FLASH_CR_ERRIE_Msk /*!< Error Interrupt Enable */
+#define FLASH_CR_EOPIE_Pos (12U)
+#define FLASH_CR_EOPIE_Msk (0x1U << FLASH_CR_EOPIE_Pos) /*!< 0x00001000 */
+#define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk /*!< End of operation interrupt enable */
+
+/******************* Bit definition for FLASH_AR register *******************/
+#define FLASH_AR_FAR_Pos (0U)
+#define FLASH_AR_FAR_Msk (0xFFFFFFFFU << FLASH_AR_FAR_Pos) /*!< 0xFFFFFFFF */
+#define FLASH_AR_FAR FLASH_AR_FAR_Msk /*!< Flash Address */
+
+/****************** Bit definition for FLASH_OBR register *******************/
+#define FLASH_OBR_OPTERR_Pos (0U)
+#define FLASH_OBR_OPTERR_Msk (0x1U << FLASH_OBR_OPTERR_Pos) /*!< 0x00000001 */
+#define FLASH_OBR_OPTERR FLASH_OBR_OPTERR_Msk /*!< Option Byte Error */
+#define FLASH_OBR_RDPRT_Pos (1U)
+#define FLASH_OBR_RDPRT_Msk (0x1U << FLASH_OBR_RDPRT_Pos) /*!< 0x00000002 */
+#define FLASH_OBR_RDPRT FLASH_OBR_RDPRT_Msk /*!< Read protection */
+
+#define FLASH_OBR_IWDG_SW_Pos (2U)
+#define FLASH_OBR_IWDG_SW_Msk (0x1U << FLASH_OBR_IWDG_SW_Pos) /*!< 0x00000004 */
+#define FLASH_OBR_IWDG_SW FLASH_OBR_IWDG_SW_Msk /*!< IWDG SW */
+#define FLASH_OBR_nRST_STOP_Pos (3U)
+#define FLASH_OBR_nRST_STOP_Msk (0x1U << FLASH_OBR_nRST_STOP_Pos) /*!< 0x00000008 */
+#define FLASH_OBR_nRST_STOP FLASH_OBR_nRST_STOP_Msk /*!< nRST_STOP */
+#define FLASH_OBR_nRST_STDBY_Pos (4U)
+#define FLASH_OBR_nRST_STDBY_Msk (0x1U << FLASH_OBR_nRST_STDBY_Pos) /*!< 0x00000010 */
+#define FLASH_OBR_nRST_STDBY FLASH_OBR_nRST_STDBY_Msk /*!< nRST_STDBY */
+#define FLASH_OBR_USER_Pos (2U)
+#define FLASH_OBR_USER_Msk (0x7U << FLASH_OBR_USER_Pos) /*!< 0x0000001C */
+#define FLASH_OBR_USER FLASH_OBR_USER_Msk /*!< User Option Bytes */
+#define FLASH_OBR_DATA0_Pos (10U)
+#define FLASH_OBR_DATA0_Msk (0xFFU << FLASH_OBR_DATA0_Pos) /*!< 0x0003FC00 */
+#define FLASH_OBR_DATA0 FLASH_OBR_DATA0_Msk /*!< Data0 */
+#define FLASH_OBR_DATA1_Pos (18U)
+#define FLASH_OBR_DATA1_Msk (0xFFU << FLASH_OBR_DATA1_Pos) /*!< 0x03FC0000 */
+#define FLASH_OBR_DATA1 FLASH_OBR_DATA1_Msk /*!< Data1 */
+
+/****************** Bit definition for FLASH_WRPR register ******************/
+#define FLASH_WRPR_WRP_Pos (0U)
+#define FLASH_WRPR_WRP_Msk (0xFFFFFFFFU << FLASH_WRPR_WRP_Pos) /*!< 0xFFFFFFFF */
+#define FLASH_WRPR_WRP FLASH_WRPR_WRP_Msk /*!< Write Protect */
+
+/*----------------------------------------------------------------------------*/
+
+/****************** Bit definition for FLASH_RDP register *******************/
+#define FLASH_RDP_RDP_Pos (0U)
+#define FLASH_RDP_RDP_Msk (0xFFU << FLASH_RDP_RDP_Pos) /*!< 0x000000FF */
+#define FLASH_RDP_RDP FLASH_RDP_RDP_Msk /*!< Read protection option byte */
+#define FLASH_RDP_nRDP_Pos (8U)
+#define FLASH_RDP_nRDP_Msk (0xFFU << FLASH_RDP_nRDP_Pos) /*!< 0x0000FF00 */
+#define FLASH_RDP_nRDP FLASH_RDP_nRDP_Msk /*!< Read protection complemented option byte */
+
+/****************** Bit definition for FLASH_USER register ******************/
+#define FLASH_USER_USER_Pos (16U)
+#define FLASH_USER_USER_Msk (0xFFU << FLASH_USER_USER_Pos) /*!< 0x00FF0000 */
+#define FLASH_USER_USER FLASH_USER_USER_Msk /*!< User option byte */
+#define FLASH_USER_nUSER_Pos (24U)
+#define FLASH_USER_nUSER_Msk (0xFFU << FLASH_USER_nUSER_Pos) /*!< 0xFF000000 */
+#define FLASH_USER_nUSER FLASH_USER_nUSER_Msk /*!< User complemented option byte */
+
+/****************** Bit definition for FLASH_Data0 register *****************/
+#define FLASH_DATA0_DATA0_Pos (0U)
+#define FLASH_DATA0_DATA0_Msk (0xFFU << FLASH_DATA0_DATA0_Pos) /*!< 0x000000FF */
+#define FLASH_DATA0_DATA0 FLASH_DATA0_DATA0_Msk /*!< User data storage option byte */
+#define FLASH_DATA0_nDATA0_Pos (8U)
+#define FLASH_DATA0_nDATA0_Msk (0xFFU << FLASH_DATA0_nDATA0_Pos) /*!< 0x0000FF00 */
+#define FLASH_DATA0_nDATA0 FLASH_DATA0_nDATA0_Msk /*!< User data storage complemented option byte */
+
+/****************** Bit definition for FLASH_Data1 register *****************/
+#define FLASH_DATA1_DATA1_Pos (16U)
+#define FLASH_DATA1_DATA1_Msk (0xFFU << FLASH_DATA1_DATA1_Pos) /*!< 0x00FF0000 */
+#define FLASH_DATA1_DATA1 FLASH_DATA1_DATA1_Msk /*!< User data storage option byte */
+#define FLASH_DATA1_nDATA1_Pos (24U)
+#define FLASH_DATA1_nDATA1_Msk (0xFFU << FLASH_DATA1_nDATA1_Pos) /*!< 0xFF000000 */
+#define FLASH_DATA1_nDATA1 FLASH_DATA1_nDATA1_Msk /*!< User data storage complemented option byte */
+
+/****************** Bit definition for FLASH_WRP0 register ******************/
+#define FLASH_WRP0_WRP0_Pos (0U)
+#define FLASH_WRP0_WRP0_Msk (0xFFU << FLASH_WRP0_WRP0_Pos) /*!< 0x000000FF */
+#define FLASH_WRP0_WRP0 FLASH_WRP0_WRP0_Msk /*!< Flash memory write protection option bytes */
+#define FLASH_WRP0_nWRP0_Pos (8U)
+#define FLASH_WRP0_nWRP0_Msk (0xFFU << FLASH_WRP0_nWRP0_Pos) /*!< 0x0000FF00 */
+#define FLASH_WRP0_nWRP0 FLASH_WRP0_nWRP0_Msk /*!< Flash memory write protection complemented option bytes */
+
+/****************** Bit definition for FLASH_WRP1 register ******************/
+#define FLASH_WRP1_WRP1_Pos (16U)
+#define FLASH_WRP1_WRP1_Msk (0xFFU << FLASH_WRP1_WRP1_Pos) /*!< 0x00FF0000 */
+#define FLASH_WRP1_WRP1 FLASH_WRP1_WRP1_Msk /*!< Flash memory write protection option bytes */
+#define FLASH_WRP1_nWRP1_Pos (24U)
+#define FLASH_WRP1_nWRP1_Msk (0xFFU << FLASH_WRP1_nWRP1_Pos) /*!< 0xFF000000 */
+#define FLASH_WRP1_nWRP1 FLASH_WRP1_nWRP1_Msk /*!< Flash memory write protection complemented option bytes */
+
+/****************** Bit definition for FLASH_WRP2 register ******************/
+#define FLASH_WRP2_WRP2_Pos (0U)
+#define FLASH_WRP2_WRP2_Msk (0xFFU << FLASH_WRP2_WRP2_Pos) /*!< 0x000000FF */
+#define FLASH_WRP2_WRP2 FLASH_WRP2_WRP2_Msk /*!< Flash memory write protection option bytes */
+#define FLASH_WRP2_nWRP2_Pos (8U)
+#define FLASH_WRP2_nWRP2_Msk (0xFFU << FLASH_WRP2_nWRP2_Pos) /*!< 0x0000FF00 */
+#define FLASH_WRP2_nWRP2 FLASH_WRP2_nWRP2_Msk /*!< Flash memory write protection complemented option bytes */
+
+/****************** Bit definition for FLASH_WRP3 register ******************/
+#define FLASH_WRP3_WRP3_Pos (16U)
+#define FLASH_WRP3_WRP3_Msk (0xFFU << FLASH_WRP3_WRP3_Pos) /*!< 0x00FF0000 */
+#define FLASH_WRP3_WRP3 FLASH_WRP3_WRP3_Msk /*!< Flash memory write protection option bytes */
+#define FLASH_WRP3_nWRP3_Pos (24U)
+#define FLASH_WRP3_nWRP3_Msk (0xFFU << FLASH_WRP3_nWRP3_Pos) /*!< 0xFF000000 */
+#define FLASH_WRP3_nWRP3 FLASH_WRP3_nWRP3_Msk /*!< Flash memory write protection complemented option bytes */
+
+
+
+/**
+ * @}
+*/
+
+/**
+ * @}
+*/
+
+/** @addtogroup Exported_macro
+ * @{
+ */
+
+/****************************** ADC Instances *********************************/
+#define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1))
+
+#define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC1_COMMON)
+
+#define IS_ADC_DMA_CAPABILITY_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
+
+/****************************** CRC Instances *********************************/
+#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
+
+/****************************** DAC Instances *********************************/
+
+/****************************** DMA Instances *********************************/
+#define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \
+ ((INSTANCE) == DMA1_Channel2) || \
+ ((INSTANCE) == DMA1_Channel3) || \
+ ((INSTANCE) == DMA1_Channel4) || \
+ ((INSTANCE) == DMA1_Channel5) || \
+ ((INSTANCE) == DMA1_Channel6) || \
+ ((INSTANCE) == DMA1_Channel7))
+
+/******************************* GPIO Instances *******************************/
+#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
+ ((INSTANCE) == GPIOB) || \
+ ((INSTANCE) == GPIOC) || \
+ ((INSTANCE) == GPIOD))
+
+/**************************** GPIO Alternate Function Instances ***************/
+#define IS_GPIO_AF_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
+
+/**************************** GPIO Lock Instances *****************************/
+#define IS_GPIO_LOCK_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
+
+/******************************** I2C Instances *******************************/
+#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
+ ((INSTANCE) == I2C2))
+
+/****************************** IWDG Instances ********************************/
+#define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
+
+/******************************** SPI Instances *******************************/
+#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
+ ((INSTANCE) == SPI2))
+
+/****************************** START TIM Instances ***************************/
+/****************************** TIM Instances *********************************/
+#define IS_TIM_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4))
+
+#define IS_TIM_CC1_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4))
+
+#define IS_TIM_CC2_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4))
+
+#define IS_TIM_CC3_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4))
+
+#define IS_TIM_CC4_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4))
+
+#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4))
+
+#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4))
+
+#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4))
+
+#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4))
+
+#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4))
+
+#define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4))
+
+#define IS_TIM_XOR_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4))
+
+#define IS_TIM_MASTER_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4))
+
+#define IS_TIM_SLAVE_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4))
+
+#define IS_TIM_DMABURST_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4))
+
+#define IS_TIM_BREAK_INSTANCE(INSTANCE) (0)
+
+#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
+ ((((INSTANCE) == TIM2) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM3) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM4) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))))
+
+#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) (0)
+
+#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4))
+
+#define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE) (0)
+
+#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4))
+
+#define IS_TIM_DMA_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4))
+
+#define IS_TIM_DMA_CC_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4))
+
+#define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) (0)
+
+/****************************** END TIM Instances *****************************/
+
+
+/******************** USART Instances : Synchronous mode **********************/
+#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3))
+
+/******************** UART Instances : Asynchronous mode **********************/
+#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3))
+
+/******************** UART Instances : Half-Duplex mode **********************/
+#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3))
+
+/******************** UART Instances : LIN mode **********************/
+#define IS_UART_LIN_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3))
+
+/****************** UART Instances : Hardware Flow control ********************/
+#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3))
+
+/********************* UART Instances : Smard card mode ***********************/
+#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3))
+
+/*********************** UART Instances : IRDA mode ***************************/
+#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3))
+
+/***************** UART Instances : Multi-Processor mode **********************/
+#define IS_UART_MULTIPROCESSOR_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3))
+
+/***************** UART Instances : DMA mode available **********************/
+#define IS_UART_DMA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3))
+
+/****************************** RTC Instances *********************************/
+#define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
+
+/**************************** WWDG Instances *****************************/
+#define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
+
+/****************************** USB Instances ********************************/
+#define IS_USB_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB)
+
+
+
+
+/**
+ * @}
+*/
+/******************************************************************************/
+/* For a painless codes migration between the STM32F1xx device product */
+/* lines, the aliases defined below are put in place to overcome the */
+/* differences in the interrupt handlers and IRQn definitions. */
+/* No need to update developed interrupt code when moving across */
+/* product lines within the same STM32F1 Family */
+/******************************************************************************/
+
+/* Aliases for __IRQn */
+#define ADC1_2_IRQn ADC1_IRQn
+#define CEC_IRQn USBWakeUp_IRQn
+#define OTG_FS_WKUP_IRQn USBWakeUp_IRQn
+#define USB_HP_CAN1_TX_IRQn USB_HP_IRQn
+#define CAN1_TX_IRQn USB_HP_IRQn
+#define USB_LP_CAN1_RX0_IRQn USB_LP_IRQn
+#define CAN1_RX0_IRQn USB_LP_IRQn
+
+
+/* Aliases for __IRQHandler */
+#define ADC1_2_IRQHandler ADC1_IRQHandler
+#define CEC_IRQHandler USBWakeUp_IRQHandler
+#define OTG_FS_WKUP_IRQHandler USBWakeUp_IRQHandler
+#define USB_HP_CAN1_TX_IRQHandler USB_HP_IRQHandler
+#define CAN1_TX_IRQHandler USB_HP_IRQHandler
+#define USB_LP_CAN1_RX0_IRQHandler USB_LP_IRQHandler
+#define CAN1_RX0_IRQHandler USB_LP_IRQHandler
+
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+
+#ifdef __cplusplus
+ }
+#endif /* __cplusplus */
+
+#endif /* __STM32F102xB_H */
+
+
+
+ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Device/ST/STM32F1xx/Include/stm32f103x6.h b/Device/ST/STM32F1xx/Include/stm32f103x6.h
new file mode 100644
index 0000000..78c09d1
--- /dev/null
+++ b/Device/ST/STM32F1xx/Include/stm32f103x6.h
@@ -0,0 +1,10944 @@
+/**
+ ******************************************************************************
+ * @file stm32f103x6.h
+ * @author MCD Application Team
+ * @version V4.1.0
+ * @date 29-April-2016
+ * @brief CMSIS Cortex-M3 Device Peripheral Access Layer Header File.
+ * This file contains all the peripheral register's definitions, bits
+ * definitions and memory mapping for STM32F1xx devices.
+ *
+ * This file contains:
+ * - Data structures and the address mapping for all peripherals
+ * - Peripheral's registers declarations and bits definition
+ * - Macros to access peripheral’s registers hardware
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+
+/** @addtogroup CMSIS
+ * @{
+ */
+
+/** @addtogroup stm32f103x6
+ * @{
+ */
+
+#ifndef __STM32F103x6_H
+#define __STM32F103x6_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/** @addtogroup Configuration_section_for_CMSIS
+ * @{
+ */
+/**
+ * @brief Configuration of the Cortex-M3 Processor and Core Peripherals
+ */
+ #define __MPU_PRESENT 0 /*!< Other STM32 devices does not provide an MPU */
+#define __CM3_REV 0x0200 /*!< Core Revision r2p0 */
+#define __NVIC_PRIO_BITS 4 /*!< STM32 uses 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
+
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_interrupt_number_definition
+ * @{
+ */
+
+/**
+ * @brief STM32F10x Interrupt Number Definition, according to the selected device
+ * in @ref Library_configuration_section
+ */
+
+ /*!< Interrupt Number Definition */
+typedef enum
+{
+/****** Cortex-M3 Processor Exceptions Numbers ***************************************************/
+ NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
+ HardFault_IRQn = -13, /*!< 3 Cortex-M3 Hard Fault Interrupt */
+ MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */
+ BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */
+ UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */
+ SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */
+ DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */
+ PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */
+ SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */
+
+/****** STM32 specific Interrupt Numbers *********************************************************/
+ WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
+ PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */
+ TAMPER_IRQn = 2, /*!< Tamper Interrupt */
+ RTC_IRQn = 3, /*!< RTC global Interrupt */
+ FLASH_IRQn = 4, /*!< FLASH global Interrupt */
+ RCC_IRQn = 5, /*!< RCC global Interrupt */
+ EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */
+ EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */
+ EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */
+ EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */
+ EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */
+ DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 global Interrupt */
+ DMA1_Channel2_IRQn = 12, /*!< DMA1 Channel 2 global Interrupt */
+ DMA1_Channel3_IRQn = 13, /*!< DMA1 Channel 3 global Interrupt */
+ DMA1_Channel4_IRQn = 14, /*!< DMA1 Channel 4 global Interrupt */
+ DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 global Interrupt */
+ DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 global Interrupt */
+ DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 global Interrupt */
+ ADC1_2_IRQn = 18, /*!< ADC1 and ADC2 global Interrupt */
+ USB_HP_CAN1_TX_IRQn = 19, /*!< USB Device High Priority or CAN1 TX Interrupts */
+ USB_LP_CAN1_RX0_IRQn = 20, /*!< USB Device Low Priority or CAN1 RX0 Interrupts */
+ CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */
+ CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */
+ EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
+ TIM1_BRK_IRQn = 24, /*!< TIM1 Break Interrupt */
+ TIM1_UP_IRQn = 25, /*!< TIM1 Update Interrupt */
+ TIM1_TRG_COM_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt */
+ TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
+ TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
+ TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
+ I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
+ I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
+ SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
+ USART1_IRQn = 37, /*!< USART1 global Interrupt */
+ USART2_IRQn = 38, /*!< USART2 global Interrupt */
+ EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
+ RTC_Alarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */
+ USBWakeUp_IRQn = 42, /*!< USB Device WakeUp from suspend through EXTI Line Interrupt */
+} IRQn_Type;
+
+
+/**
+ * @}
+ */
+
+#include "core_cm3.h"
+#include "system_stm32f1xx.h"
+#include <stdint.h>
+
+/** @addtogroup Peripheral_registers_structures
+ * @{
+ */
+
+/**
+ * @brief Analog to Digital Converter
+ */
+
+typedef struct
+{
+ __IO uint32_t SR;
+ __IO uint32_t CR1;
+ __IO uint32_t CR2;
+ __IO uint32_t SMPR1;
+ __IO uint32_t SMPR2;
+ __IO uint32_t JOFR1;
+ __IO uint32_t JOFR2;
+ __IO uint32_t JOFR3;
+ __IO uint32_t JOFR4;
+ __IO uint32_t HTR;
+ __IO uint32_t LTR;
+ __IO uint32_t SQR1;
+ __IO uint32_t SQR2;
+ __IO uint32_t SQR3;
+ __IO uint32_t JSQR;
+ __IO uint32_t JDR1;
+ __IO uint32_t JDR2;
+ __IO uint32_t JDR3;
+ __IO uint32_t JDR4;
+ __IO uint32_t DR;
+} ADC_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t SR; /*!< ADC status register, used for ADC multimode (bits common to several ADC instances). Address offset: ADC1 base address */
+ __IO uint32_t CR1; /*!< ADC control register 1, used for ADC multimode (bits common to several ADC instances). Address offset: ADC1 base address + 0x04 */
+ __IO uint32_t CR2; /*!< ADC control register 2, used for ADC multimode (bits common to several ADC instances). Address offset: ADC1 base address + 0x08 */
+ uint32_t RESERVED[16];
+ __IO uint32_t DR; /*!< ADC data register, used for ADC multimode (bits common to several ADC instances). Address offset: ADC1 base address + 0x4C */
+} ADC_Common_TypeDef;
+
+/**
+ * @brief Backup Registers
+ */
+
+typedef struct
+{
+ uint32_t RESERVED0;
+ __IO uint32_t DR1;
+ __IO uint32_t DR2;
+ __IO uint32_t DR3;
+ __IO uint32_t DR4;
+ __IO uint32_t DR5;
+ __IO uint32_t DR6;
+ __IO uint32_t DR7;
+ __IO uint32_t DR8;
+ __IO uint32_t DR9;
+ __IO uint32_t DR10;
+ __IO uint32_t RTCCR;
+ __IO uint32_t CR;
+ __IO uint32_t CSR;
+} BKP_TypeDef;
+
+/**
+ * @brief Controller Area Network TxMailBox
+ */
+
+typedef struct
+{
+ __IO uint32_t TIR;
+ __IO uint32_t TDTR;
+ __IO uint32_t TDLR;
+ __IO uint32_t TDHR;
+} CAN_TxMailBox_TypeDef;
+
+/**
+ * @brief Controller Area Network FIFOMailBox
+ */
+
+typedef struct
+{
+ __IO uint32_t RIR;
+ __IO uint32_t RDTR;
+ __IO uint32_t RDLR;
+ __IO uint32_t RDHR;
+} CAN_FIFOMailBox_TypeDef;
+
+/**
+ * @brief Controller Area Network FilterRegister
+ */
+
+typedef struct
+{
+ __IO uint32_t FR1;
+ __IO uint32_t FR2;
+} CAN_FilterRegister_TypeDef;
+
+/**
+ * @brief Controller Area Network
+ */
+
+typedef struct
+{
+ __IO uint32_t MCR;
+ __IO uint32_t MSR;
+ __IO uint32_t TSR;
+ __IO uint32_t RF0R;
+ __IO uint32_t RF1R;
+ __IO uint32_t IER;
+ __IO uint32_t ESR;
+ __IO uint32_t BTR;
+ uint32_t RESERVED0[88];
+ CAN_TxMailBox_TypeDef sTxMailBox[3];
+ CAN_FIFOMailBox_TypeDef sFIFOMailBox[2];
+ uint32_t RESERVED1[12];
+ __IO uint32_t FMR;
+ __IO uint32_t FM1R;
+ uint32_t RESERVED2;
+ __IO uint32_t FS1R;
+ uint32_t RESERVED3;
+ __IO uint32_t FFA1R;
+ uint32_t RESERVED4;
+ __IO uint32_t FA1R;
+ uint32_t RESERVED5[8];
+ CAN_FilterRegister_TypeDef sFilterRegister[14];
+} CAN_TypeDef;
+
+/**
+ * @brief CRC calculation unit
+ */
+
+typedef struct
+{
+ __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
+ __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
+ uint8_t RESERVED0; /*!< Reserved, Address offset: 0x05 */
+ uint16_t RESERVED1; /*!< Reserved, Address offset: 0x06 */
+ __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
+} CRC_TypeDef;
+
+
+/**
+ * @brief Debug MCU
+ */
+
+typedef struct
+{
+ __IO uint32_t IDCODE;
+ __IO uint32_t CR;
+}DBGMCU_TypeDef;
+
+/**
+ * @brief DMA Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t CCR;
+ __IO uint32_t CNDTR;
+ __IO uint32_t CPAR;
+ __IO uint32_t CMAR;
+} DMA_Channel_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t ISR;
+ __IO uint32_t IFCR;
+} DMA_TypeDef;
+
+
+
+/**
+ * @brief External Interrupt/Event Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t IMR;
+ __IO uint32_t EMR;
+ __IO uint32_t RTSR;
+ __IO uint32_t FTSR;
+ __IO uint32_t SWIER;
+ __IO uint32_t PR;
+} EXTI_TypeDef;
+
+/**
+ * @brief FLASH Registers
+ */
+
+typedef struct
+{
+ __IO uint32_t ACR;
+ __IO uint32_t KEYR;
+ __IO uint32_t OPTKEYR;
+ __IO uint32_t SR;
+ __IO uint32_t CR;
+ __IO uint32_t AR;
+ __IO uint32_t RESERVED;
+ __IO uint32_t OBR;
+ __IO uint32_t WRPR;
+} FLASH_TypeDef;
+
+/**
+ * @brief Option Bytes Registers
+ */
+
+typedef struct
+{
+ __IO uint16_t RDP;
+ __IO uint16_t USER;
+ __IO uint16_t Data0;
+ __IO uint16_t Data1;
+ __IO uint16_t WRP0;
+ __IO uint16_t WRP1;
+ __IO uint16_t WRP2;
+ __IO uint16_t WRP3;
+} OB_TypeDef;
+
+/**
+ * @brief General Purpose I/O
+ */
+
+typedef struct
+{
+ __IO uint32_t CRL;
+ __IO uint32_t CRH;
+ __IO uint32_t IDR;
+ __IO uint32_t ODR;
+ __IO uint32_t BSRR;
+ __IO uint32_t BRR;
+ __IO uint32_t LCKR;
+} GPIO_TypeDef;
+
+/**
+ * @brief Alternate Function I/O
+ */
+
+typedef struct
+{
+ __IO uint32_t EVCR;
+ __IO uint32_t MAPR;
+ __IO uint32_t EXTICR[4];
+ uint32_t RESERVED0;
+ __IO uint32_t MAPR2;
+} AFIO_TypeDef;
+/**
+ * @brief Inter Integrated Circuit Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t CR1;
+ __IO uint32_t CR2;
+ __IO uint32_t OAR1;
+ __IO uint32_t OAR2;
+ __IO uint32_t DR;
+ __IO uint32_t SR1;
+ __IO uint32_t SR2;
+ __IO uint32_t CCR;
+ __IO uint32_t TRISE;
+} I2C_TypeDef;
+
+/**
+ * @brief Independent WATCHDOG
+ */
+
+typedef struct
+{
+ __IO uint32_t KR; /*!< Key register, Address offset: 0x00 */
+ __IO uint32_t PR; /*!< Prescaler register, Address offset: 0x04 */
+ __IO uint32_t RLR; /*!< Reload register, Address offset: 0x08 */
+ __IO uint32_t SR; /*!< Status register, Address offset: 0x0C */
+} IWDG_TypeDef;
+
+/**
+ * @brief Power Control
+ */
+
+typedef struct
+{
+ __IO uint32_t CR;
+ __IO uint32_t CSR;
+} PWR_TypeDef;
+
+/**
+ * @brief Reset and Clock Control
+ */
+
+typedef struct
+{
+ __IO uint32_t CR;
+ __IO uint32_t CFGR;
+ __IO uint32_t CIR;
+ __IO uint32_t APB2RSTR;
+ __IO uint32_t APB1RSTR;
+ __IO uint32_t AHBENR;
+ __IO uint32_t APB2ENR;
+ __IO uint32_t APB1ENR;
+ __IO uint32_t BDCR;
+ __IO uint32_t CSR;
+
+
+} RCC_TypeDef;
+
+/**
+ * @brief Real-Time Clock
+ */
+
+typedef struct
+{
+ __IO uint32_t CRH;
+ __IO uint32_t CRL;
+ __IO uint32_t PRLH;
+ __IO uint32_t PRLL;
+ __IO uint32_t DIVH;
+ __IO uint32_t DIVL;
+ __IO uint32_t CNTH;
+ __IO uint32_t CNTL;
+ __IO uint32_t ALRH;
+ __IO uint32_t ALRL;
+} RTC_TypeDef;
+
+/**
+ * @brief SD host Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t POWER;
+ __IO uint32_t CLKCR;
+ __IO uint32_t ARG;
+ __IO uint32_t CMD;
+ __I uint32_t RESPCMD;
+ __I uint32_t RESP1;
+ __I uint32_t RESP2;
+ __I uint32_t RESP3;
+ __I uint32_t RESP4;
+ __IO uint32_t DTIMER;
+ __IO uint32_t DLEN;
+ __IO uint32_t DCTRL;
+ __I uint32_t DCOUNT;
+ __I uint32_t STA;
+ __IO uint32_t ICR;
+ __IO uint32_t MASK;
+ uint32_t RESERVED0[2];
+ __I uint32_t FIFOCNT;
+ uint32_t RESERVED1[13];
+ __IO uint32_t FIFO;
+} SDIO_TypeDef;
+
+/**
+ * @brief Serial Peripheral Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t CR1;
+ __IO uint32_t CR2;
+ __IO uint32_t SR;
+ __IO uint32_t DR;
+ __IO uint32_t CRCPR;
+ __IO uint32_t RXCRCR;
+ __IO uint32_t TXCRCR;
+ __IO uint32_t I2SCFGR;
+} SPI_TypeDef;
+
+/**
+ * @brief TIM Timers
+ */
+typedef struct
+{
+ __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
+ __IO uint32_t SMCR; /*!< TIM slave Mode Control register, Address offset: 0x08 */
+ __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
+ __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
+ __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
+ __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
+ __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
+ __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
+ __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
+ __IO uint32_t PSC; /*!< TIM prescaler register, Address offset: 0x28 */
+ __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
+ __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */
+ __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
+ __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
+ __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
+ __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
+ __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
+ __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
+ __IO uint32_t DMAR; /*!< TIM DMA address for full transfer register, Address offset: 0x4C */
+ __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */
+}TIM_TypeDef;
+
+
+/**
+ * @brief Universal Synchronous Asynchronous Receiver Transmitter
+ */
+
+typedef struct
+{
+ __IO uint32_t SR; /*!< USART Status register, Address offset: 0x00 */
+ __IO uint32_t DR; /*!< USART Data register, Address offset: 0x04 */
+ __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x08 */
+ __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x0C */
+ __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x10 */
+ __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x14 */
+ __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x18 */
+} USART_TypeDef;
+
+/**
+ * @brief Universal Serial Bus Full Speed Device
+ */
+
+typedef struct
+{
+ __IO uint16_t EP0R; /*!< USB Endpoint 0 register, Address offset: 0x00 */
+ __IO uint16_t RESERVED0; /*!< Reserved */
+ __IO uint16_t EP1R; /*!< USB Endpoint 1 register, Address offset: 0x04 */
+ __IO uint16_t RESERVED1; /*!< Reserved */
+ __IO uint16_t EP2R; /*!< USB Endpoint 2 register, Address offset: 0x08 */
+ __IO uint16_t RESERVED2; /*!< Reserved */
+ __IO uint16_t EP3R; /*!< USB Endpoint 3 register, Address offset: 0x0C */
+ __IO uint16_t RESERVED3; /*!< Reserved */
+ __IO uint16_t EP4R; /*!< USB Endpoint 4 register, Address offset: 0x10 */
+ __IO uint16_t RESERVED4; /*!< Reserved */
+ __IO uint16_t EP5R; /*!< USB Endpoint 5 register, Address offset: 0x14 */
+ __IO uint16_t RESERVED5; /*!< Reserved */
+ __IO uint16_t EP6R; /*!< USB Endpoint 6 register, Address offset: 0x18 */
+ __IO uint16_t RESERVED6; /*!< Reserved */
+ __IO uint16_t EP7R; /*!< USB Endpoint 7 register, Address offset: 0x1C */
+ __IO uint16_t RESERVED7[17]; /*!< Reserved */
+ __IO uint16_t CNTR; /*!< Control register, Address offset: 0x40 */
+ __IO uint16_t RESERVED8; /*!< Reserved */
+ __IO uint16_t ISTR; /*!< Interrupt status register, Address offset: 0x44 */
+ __IO uint16_t RESERVED9; /*!< Reserved */
+ __IO uint16_t FNR; /*!< Frame number register, Address offset: 0x48 */
+ __IO uint16_t RESERVEDA; /*!< Reserved */
+ __IO uint16_t DADDR; /*!< Device address register, Address offset: 0x4C */
+ __IO uint16_t RESERVEDB; /*!< Reserved */
+ __IO uint16_t BTABLE; /*!< Buffer Table address register, Address offset: 0x50 */
+ __IO uint16_t RESERVEDC; /*!< Reserved */
+} USB_TypeDef;
+
+
+/**
+ * @brief Window WATCHDOG
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
+ __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
+ __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
+} WWDG_TypeDef;
+
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_memory_map
+ * @{
+ */
+
+
+#define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH base address in the alias region */
+#define FLASH_BANK1_END ((uint32_t)0x08007FFF) /*!< FLASH END address of bank1 */
+#define SRAM_BASE ((uint32_t)0x20000000) /*!< SRAM base address in the alias region */
+#define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */
+
+#define SRAM_BB_BASE ((uint32_t)0x22000000) /*!< SRAM base address in the bit-band region */
+#define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */
+
+
+/*!< Peripheral memory map */
+#define APB1PERIPH_BASE PERIPH_BASE
+#define APB2PERIPH_BASE (PERIPH_BASE + 0x10000)
+#define AHBPERIPH_BASE (PERIPH_BASE + 0x20000)
+
+#define TIM2_BASE (APB1PERIPH_BASE + 0x0000)
+#define TIM3_BASE (APB1PERIPH_BASE + 0x0400)
+#define RTC_BASE (APB1PERIPH_BASE + 0x2800)
+#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00)
+#define IWDG_BASE (APB1PERIPH_BASE + 0x3000)
+#define USART2_BASE (APB1PERIPH_BASE + 0x4400)
+#define I2C1_BASE (APB1PERIPH_BASE + 0x5400)
+#define CAN1_BASE (APB1PERIPH_BASE + 0x6400)
+#define BKP_BASE (APB1PERIPH_BASE + 0x6C00)
+#define PWR_BASE (APB1PERIPH_BASE + 0x7000)
+#define AFIO_BASE (APB2PERIPH_BASE + 0x0000)
+#define EXTI_BASE (APB2PERIPH_BASE + 0x0400)
+#define GPIOA_BASE (APB2PERIPH_BASE + 0x0800)
+#define GPIOB_BASE (APB2PERIPH_BASE + 0x0C00)
+#define GPIOC_BASE (APB2PERIPH_BASE + 0x1000)
+#define GPIOD_BASE (APB2PERIPH_BASE + 0x1400)
+#define ADC1_BASE (APB2PERIPH_BASE + 0x2400)
+#define ADC2_BASE (APB2PERIPH_BASE + 0x2800)
+#define TIM1_BASE (APB2PERIPH_BASE + 0x2C00)
+#define SPI1_BASE (APB2PERIPH_BASE + 0x3000)
+#define USART1_BASE (APB2PERIPH_BASE + 0x3800)
+
+#define SDIO_BASE (PERIPH_BASE + 0x18000)
+
+#define DMA1_BASE (AHBPERIPH_BASE + 0x0000)
+#define DMA1_Channel1_BASE (AHBPERIPH_BASE + 0x0008)
+#define DMA1_Channel2_BASE (AHBPERIPH_BASE + 0x001C)
+#define DMA1_Channel3_BASE (AHBPERIPH_BASE + 0x0030)
+#define DMA1_Channel4_BASE (AHBPERIPH_BASE + 0x0044)
+#define DMA1_Channel5_BASE (AHBPERIPH_BASE + 0x0058)
+#define DMA1_Channel6_BASE (AHBPERIPH_BASE + 0x006C)
+#define DMA1_Channel7_BASE (AHBPERIPH_BASE + 0x0080)
+#define RCC_BASE (AHBPERIPH_BASE + 0x1000)
+#define CRC_BASE (AHBPERIPH_BASE + 0x3000)
+
+#define FLASH_R_BASE (AHBPERIPH_BASE + 0x2000) /*!< Flash registers base address */
+#define FLASHSIZE_BASE ((uint32_t)0x1FFFF7E0) /*!< FLASH Size register base address */
+#define UID_BASE ((uint32_t)0x1FFFF7E8) /*!< Unique device ID register base address */
+#define OB_BASE ((uint32_t)0x1FFFF800) /*!< Flash Option Bytes base address */
+
+
+
+#define DBGMCU_BASE ((uint32_t)0xE0042000) /*!< Debug MCU registers base address */
+
+/* USB device FS */
+#define USB_BASE (APB1PERIPH_BASE + 0x00005C00) /*!< USB_IP Peripheral Registers base address */
+#define USB_PMAADDR (APB1PERIPH_BASE + 0x00006000) /*!< USB_IP Packet Memory Area base address */
+
+
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_declaration
+ * @{
+ */
+
+#define TIM2 ((TIM_TypeDef *) TIM2_BASE)
+#define TIM3 ((TIM_TypeDef *) TIM3_BASE)
+#define RTC ((RTC_TypeDef *) RTC_BASE)
+#define WWDG ((WWDG_TypeDef *) WWDG_BASE)
+#define IWDG ((IWDG_TypeDef *) IWDG_BASE)
+#define USART2 ((USART_TypeDef *) USART2_BASE)
+#define I2C1 ((I2C_TypeDef *) I2C1_BASE)
+#define USB ((USB_TypeDef *) USB_BASE)
+#define CAN1 ((CAN_TypeDef *) CAN1_BASE)
+#define BKP ((BKP_TypeDef *) BKP_BASE)
+#define PWR ((PWR_TypeDef *) PWR_BASE)
+#define AFIO ((AFIO_TypeDef *) AFIO_BASE)
+#define EXTI ((EXTI_TypeDef *) EXTI_BASE)
+#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
+#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
+#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
+#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
+#define ADC1 ((ADC_TypeDef *) ADC1_BASE)
+#define ADC2 ((ADC_TypeDef *) ADC2_BASE)
+#define ADC12_COMMON ((ADC_Common_TypeDef *) ADC1_BASE)
+#define TIM1 ((TIM_TypeDef *) TIM1_BASE)
+#define SPI1 ((SPI_TypeDef *) SPI1_BASE)
+#define USART1 ((USART_TypeDef *) USART1_BASE)
+#define SDIO ((SDIO_TypeDef *) SDIO_BASE)
+#define DMA1 ((DMA_TypeDef *) DMA1_BASE)
+#define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
+#define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
+#define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
+#define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
+#define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
+#define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
+#define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
+#define RCC ((RCC_TypeDef *) RCC_BASE)
+#define CRC ((CRC_TypeDef *) CRC_BASE)
+#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
+#define OB ((OB_TypeDef *) OB_BASE)
+#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
+
+
+/**
+ * @}
+ */
+
+/** @addtogroup Exported_constants
+ * @{
+ */
+
+ /** @addtogroup Peripheral_Registers_Bits_Definition
+ * @{
+ */
+
+/******************************************************************************/
+/* Peripheral Registers_Bits_Definition */
+/******************************************************************************/
+
+/******************************************************************************/
+/* */
+/* CRC calculation unit (CRC) */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for CRC_DR register *********************/
+#define CRC_DR_DR_Pos (0U)
+#define CRC_DR_DR_Msk (0xFFFFFFFFU << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */
+#define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */
+
+/******************* Bit definition for CRC_IDR register ********************/
+#define CRC_IDR_IDR_Pos (0U)
+#define CRC_IDR_IDR_Msk (0xFFU << CRC_IDR_IDR_Pos) /*!< 0x000000FF */
+#define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 8-bit data register bits */
+
+/******************** Bit definition for CRC_CR register ********************/
+#define CRC_CR_RESET_Pos (0U)
+#define CRC_CR_RESET_Msk (0x1U << CRC_CR_RESET_Pos) /*!< 0x00000001 */
+#define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET bit */
+
+/******************************************************************************/
+/* */
+/* Power Control */
+/* */
+/******************************************************************************/
+
+/******************** Bit definition for PWR_CR register ********************/
+#define PWR_CR_LPDS_Pos (0U)
+#define PWR_CR_LPDS_Msk (0x1U << PWR_CR_LPDS_Pos) /*!< 0x00000001 */
+#define PWR_CR_LPDS PWR_CR_LPDS_Msk /*!< Low-Power Deepsleep */
+#define PWR_CR_PDDS_Pos (1U)
+#define PWR_CR_PDDS_Msk (0x1U << PWR_CR_PDDS_Pos) /*!< 0x00000002 */
+#define PWR_CR_PDDS PWR_CR_PDDS_Msk /*!< Power Down Deepsleep */
+#define PWR_CR_CWUF_Pos (2U)
+#define PWR_CR_CWUF_Msk (0x1U << PWR_CR_CWUF_Pos) /*!< 0x00000004 */
+#define PWR_CR_CWUF PWR_CR_CWUF_Msk /*!< Clear Wakeup Flag */
+#define PWR_CR_CSBF_Pos (3U)
+#define PWR_CR_CSBF_Msk (0x1U << PWR_CR_CSBF_Pos) /*!< 0x00000008 */
+#define PWR_CR_CSBF PWR_CR_CSBF_Msk /*!< Clear Standby Flag */
+#define PWR_CR_PVDE_Pos (4U)
+#define PWR_CR_PVDE_Msk (0x1U << PWR_CR_PVDE_Pos) /*!< 0x00000010 */
+#define PWR_CR_PVDE PWR_CR_PVDE_Msk /*!< Power Voltage Detector Enable */
+
+#define PWR_CR_PLS_Pos (5U)
+#define PWR_CR_PLS_Msk (0x7U << PWR_CR_PLS_Pos) /*!< 0x000000E0 */
+#define PWR_CR_PLS PWR_CR_PLS_Msk /*!< PLS[2:0] bits (PVD Level Selection) */
+#define PWR_CR_PLS_0 (0x1U << PWR_CR_PLS_Pos) /*!< 0x00000020 */
+#define PWR_CR_PLS_1 (0x2U << PWR_CR_PLS_Pos) /*!< 0x00000040 */
+#define PWR_CR_PLS_2 (0x4U << PWR_CR_PLS_Pos) /*!< 0x00000080 */
+
+/*!< PVD level configuration */
+#define PWR_CR_PLS_2V2 ((uint32_t)0x00000000) /*!< PVD level 2.2V */
+#define PWR_CR_PLS_2V3 ((uint32_t)0x00000020) /*!< PVD level 2.3V */
+#define PWR_CR_PLS_2V4 ((uint32_t)0x00000040) /*!< PVD level 2.4V */
+#define PWR_CR_PLS_2V5 ((uint32_t)0x00000060) /*!< PVD level 2.5V */
+#define PWR_CR_PLS_2V6 ((uint32_t)0x00000080) /*!< PVD level 2.6V */
+#define PWR_CR_PLS_2V7 ((uint32_t)0x000000A0) /*!< PVD level 2.7V */
+#define PWR_CR_PLS_2V8 ((uint32_t)0x000000C0) /*!< PVD level 2.8V */
+#define PWR_CR_PLS_2V9 ((uint32_t)0x000000E0) /*!< PVD level 2.9V */
+
+#define PWR_CR_DBP_Pos (8U)
+#define PWR_CR_DBP_Msk (0x1U << PWR_CR_DBP_Pos) /*!< 0x00000100 */
+#define PWR_CR_DBP PWR_CR_DBP_Msk /*!< Disable Backup Domain write protection */
+
+
+/******************* Bit definition for PWR_CSR register ********************/
+#define PWR_CSR_WUF_Pos (0U)
+#define PWR_CSR_WUF_Msk (0x1U << PWR_CSR_WUF_Pos) /*!< 0x00000001 */
+#define PWR_CSR_WUF PWR_CSR_WUF_Msk /*!< Wakeup Flag */
+#define PWR_CSR_SBF_Pos (1U)
+#define PWR_CSR_SBF_Msk (0x1U << PWR_CSR_SBF_Pos) /*!< 0x00000002 */
+#define PWR_CSR_SBF PWR_CSR_SBF_Msk /*!< Standby Flag */
+#define PWR_CSR_PVDO_Pos (2U)
+#define PWR_CSR_PVDO_Msk (0x1U << PWR_CSR_PVDO_Pos) /*!< 0x00000004 */
+#define PWR_CSR_PVDO PWR_CSR_PVDO_Msk /*!< PVD Output */
+#define PWR_CSR_EWUP_Pos (8U)
+#define PWR_CSR_EWUP_Msk (0x1U << PWR_CSR_EWUP_Pos) /*!< 0x00000100 */
+#define PWR_CSR_EWUP PWR_CSR_EWUP_Msk /*!< Enable WKUP pin */
+
+/******************************************************************************/
+/* */
+/* Backup registers */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for BKP_DR1 register ********************/
+#define BKP_DR1_D_Pos (0U)
+#define BKP_DR1_D_Msk (0xFFFFU << BKP_DR1_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR1_D BKP_DR1_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR2 register ********************/
+#define BKP_DR2_D_Pos (0U)
+#define BKP_DR2_D_Msk (0xFFFFU << BKP_DR2_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR2_D BKP_DR2_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR3 register ********************/
+#define BKP_DR3_D_Pos (0U)
+#define BKP_DR3_D_Msk (0xFFFFU << BKP_DR3_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR3_D BKP_DR3_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR4 register ********************/
+#define BKP_DR4_D_Pos (0U)
+#define BKP_DR4_D_Msk (0xFFFFU << BKP_DR4_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR4_D BKP_DR4_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR5 register ********************/
+#define BKP_DR5_D_Pos (0U)
+#define BKP_DR5_D_Msk (0xFFFFU << BKP_DR5_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR5_D BKP_DR5_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR6 register ********************/
+#define BKP_DR6_D_Pos (0U)
+#define BKP_DR6_D_Msk (0xFFFFU << BKP_DR6_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR6_D BKP_DR6_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR7 register ********************/
+#define BKP_DR7_D_Pos (0U)
+#define BKP_DR7_D_Msk (0xFFFFU << BKP_DR7_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR7_D BKP_DR7_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR8 register ********************/
+#define BKP_DR8_D_Pos (0U)
+#define BKP_DR8_D_Msk (0xFFFFU << BKP_DR8_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR8_D BKP_DR8_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR9 register ********************/
+#define BKP_DR9_D_Pos (0U)
+#define BKP_DR9_D_Msk (0xFFFFU << BKP_DR9_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR9_D BKP_DR9_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR10 register *******************/
+#define BKP_DR10_D_Pos (0U)
+#define BKP_DR10_D_Msk (0xFFFFU << BKP_DR10_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR10_D BKP_DR10_D_Msk /*!< Backup data */
+
+#define RTC_BKP_NUMBER 10
+
+/****************** Bit definition for BKP_RTCCR register *******************/
+#define BKP_RTCCR_CAL_Pos (0U)
+#define BKP_RTCCR_CAL_Msk (0x7FU << BKP_RTCCR_CAL_Pos) /*!< 0x0000007F */
+#define BKP_RTCCR_CAL BKP_RTCCR_CAL_Msk /*!< Calibration value */
+#define BKP_RTCCR_CCO_Pos (7U)
+#define BKP_RTCCR_CCO_Msk (0x1U << BKP_RTCCR_CCO_Pos) /*!< 0x00000080 */
+#define BKP_RTCCR_CCO BKP_RTCCR_CCO_Msk /*!< Calibration Clock Output */
+#define BKP_RTCCR_ASOE_Pos (8U)
+#define BKP_RTCCR_ASOE_Msk (0x1U << BKP_RTCCR_ASOE_Pos) /*!< 0x00000100 */
+#define BKP_RTCCR_ASOE BKP_RTCCR_ASOE_Msk /*!< Alarm or Second Output Enable */
+#define BKP_RTCCR_ASOS_Pos (9U)
+#define BKP_RTCCR_ASOS_Msk (0x1U << BKP_RTCCR_ASOS_Pos) /*!< 0x00000200 */
+#define BKP_RTCCR_ASOS BKP_RTCCR_ASOS_Msk /*!< Alarm or Second Output Selection */
+
+/******************** Bit definition for BKP_CR register ********************/
+#define BKP_CR_TPE_Pos (0U)
+#define BKP_CR_TPE_Msk (0x1U << BKP_CR_TPE_Pos) /*!< 0x00000001 */
+#define BKP_CR_TPE BKP_CR_TPE_Msk /*!< TAMPER pin enable */
+#define BKP_CR_TPAL_Pos (1U)
+#define BKP_CR_TPAL_Msk (0x1U << BKP_CR_TPAL_Pos) /*!< 0x00000002 */
+#define BKP_CR_TPAL BKP_CR_TPAL_Msk /*!< TAMPER pin active level */
+
+/******************* Bit definition for BKP_CSR register ********************/
+#define BKP_CSR_CTE_Pos (0U)
+#define BKP_CSR_CTE_Msk (0x1U << BKP_CSR_CTE_Pos) /*!< 0x00000001 */
+#define BKP_CSR_CTE BKP_CSR_CTE_Msk /*!< Clear Tamper event */
+#define BKP_CSR_CTI_Pos (1U)
+#define BKP_CSR_CTI_Msk (0x1U << BKP_CSR_CTI_Pos) /*!< 0x00000002 */
+#define BKP_CSR_CTI BKP_CSR_CTI_Msk /*!< Clear Tamper Interrupt */
+#define BKP_CSR_TPIE_Pos (2U)
+#define BKP_CSR_TPIE_Msk (0x1U << BKP_CSR_TPIE_Pos) /*!< 0x00000004 */
+#define BKP_CSR_TPIE BKP_CSR_TPIE_Msk /*!< TAMPER Pin interrupt enable */
+#define BKP_CSR_TEF_Pos (8U)
+#define BKP_CSR_TEF_Msk (0x1U << BKP_CSR_TEF_Pos) /*!< 0x00000100 */
+#define BKP_CSR_TEF BKP_CSR_TEF_Msk /*!< Tamper Event Flag */
+#define BKP_CSR_TIF_Pos (9U)
+#define BKP_CSR_TIF_Msk (0x1U << BKP_CSR_TIF_Pos) /*!< 0x00000200 */
+#define BKP_CSR_TIF BKP_CSR_TIF_Msk /*!< Tamper Interrupt Flag */
+
+/******************************************************************************/
+/* */
+/* Reset and Clock Control */
+/* */
+/******************************************************************************/
+
+/******************** Bit definition for RCC_CR register ********************/
+#define RCC_CR_HSION_Pos (0U)
+#define RCC_CR_HSION_Msk (0x1U << RCC_CR_HSION_Pos) /*!< 0x00000001 */
+#define RCC_CR_HSION RCC_CR_HSION_Msk /*!< Internal High Speed clock enable */
+#define RCC_CR_HSIRDY_Pos (1U)
+#define RCC_CR_HSIRDY_Msk (0x1U << RCC_CR_HSIRDY_Pos) /*!< 0x00000002 */
+#define RCC_CR_HSIRDY RCC_CR_HSIRDY_Msk /*!< Internal High Speed clock ready flag */
+#define RCC_CR_HSITRIM_Pos (3U)
+#define RCC_CR_HSITRIM_Msk (0x1FU << RCC_CR_HSITRIM_Pos) /*!< 0x000000F8 */
+#define RCC_CR_HSITRIM RCC_CR_HSITRIM_Msk /*!< Internal High Speed clock trimming */
+#define RCC_CR_HSICAL_Pos (8U)
+#define RCC_CR_HSICAL_Msk (0xFFU << RCC_CR_HSICAL_Pos) /*!< 0x0000FF00 */
+#define RCC_CR_HSICAL RCC_CR_HSICAL_Msk /*!< Internal High Speed clock Calibration */
+#define RCC_CR_HSEON_Pos (16U)
+#define RCC_CR_HSEON_Msk (0x1U << RCC_CR_HSEON_Pos) /*!< 0x00010000 */
+#define RCC_CR_HSEON RCC_CR_HSEON_Msk /*!< External High Speed clock enable */
+#define RCC_CR_HSERDY_Pos (17U)
+#define RCC_CR_HSERDY_Msk (0x1U << RCC_CR_HSERDY_Pos) /*!< 0x00020000 */
+#define RCC_CR_HSERDY RCC_CR_HSERDY_Msk /*!< External High Speed clock ready flag */
+#define RCC_CR_HSEBYP_Pos (18U)
+#define RCC_CR_HSEBYP_Msk (0x1U << RCC_CR_HSEBYP_Pos) /*!< 0x00040000 */
+#define RCC_CR_HSEBYP RCC_CR_HSEBYP_Msk /*!< External High Speed clock Bypass */
+#define RCC_CR_CSSON_Pos (19U)
+#define RCC_CR_CSSON_Msk (0x1U << RCC_CR_CSSON_Pos) /*!< 0x00080000 */
+#define RCC_CR_CSSON RCC_CR_CSSON_Msk /*!< Clock Security System enable */
+#define RCC_CR_PLLON_Pos (24U)
+#define RCC_CR_PLLON_Msk (0x1U << RCC_CR_PLLON_Pos) /*!< 0x01000000 */
+#define RCC_CR_PLLON RCC_CR_PLLON_Msk /*!< PLL enable */
+#define RCC_CR_PLLRDY_Pos (25U)
+#define RCC_CR_PLLRDY_Msk (0x1U << RCC_CR_PLLRDY_Pos) /*!< 0x02000000 */
+#define RCC_CR_PLLRDY RCC_CR_PLLRDY_Msk /*!< PLL clock ready flag */
+
+
+/******************* Bit definition for RCC_CFGR register *******************/
+/*!< SW configuration */
+#define RCC_CFGR_SW_Pos (0U)
+#define RCC_CFGR_SW_Msk (0x3U << RCC_CFGR_SW_Pos) /*!< 0x00000003 */
+#define RCC_CFGR_SW RCC_CFGR_SW_Msk /*!< SW[1:0] bits (System clock Switch) */
+#define RCC_CFGR_SW_0 (0x1U << RCC_CFGR_SW_Pos) /*!< 0x00000001 */
+#define RCC_CFGR_SW_1 (0x2U << RCC_CFGR_SW_Pos) /*!< 0x00000002 */
+
+#define RCC_CFGR_SW_HSI ((uint32_t)0x00000000) /*!< HSI selected as system clock */
+#define RCC_CFGR_SW_HSE ((uint32_t)0x00000001) /*!< HSE selected as system clock */
+#define RCC_CFGR_SW_PLL ((uint32_t)0x00000002) /*!< PLL selected as system clock */
+
+/*!< SWS configuration */
+#define RCC_CFGR_SWS_Pos (2U)
+#define RCC_CFGR_SWS_Msk (0x3U << RCC_CFGR_SWS_Pos) /*!< 0x0000000C */
+#define RCC_CFGR_SWS RCC_CFGR_SWS_Msk /*!< SWS[1:0] bits (System Clock Switch Status) */
+#define RCC_CFGR_SWS_0 (0x1U << RCC_CFGR_SWS_Pos) /*!< 0x00000004 */
+#define RCC_CFGR_SWS_1 (0x2U << RCC_CFGR_SWS_Pos) /*!< 0x00000008 */
+
+#define RCC_CFGR_SWS_HSI ((uint32_t)0x00000000) /*!< HSI oscillator used as system clock */
+#define RCC_CFGR_SWS_HSE ((uint32_t)0x00000004) /*!< HSE oscillator used as system clock */
+#define RCC_CFGR_SWS_PLL ((uint32_t)0x00000008) /*!< PLL used as system clock */
+
+/*!< HPRE configuration */
+#define RCC_CFGR_HPRE_Pos (4U)
+#define RCC_CFGR_HPRE_Msk (0xFU << RCC_CFGR_HPRE_Pos) /*!< 0x000000F0 */
+#define RCC_CFGR_HPRE RCC_CFGR_HPRE_Msk /*!< HPRE[3:0] bits (AHB prescaler) */
+#define RCC_CFGR_HPRE_0 (0x1U << RCC_CFGR_HPRE_Pos) /*!< 0x00000010 */
+#define RCC_CFGR_HPRE_1 (0x2U << RCC_CFGR_HPRE_Pos) /*!< 0x00000020 */
+#define RCC_CFGR_HPRE_2 (0x4U << RCC_CFGR_HPRE_Pos) /*!< 0x00000040 */
+#define RCC_CFGR_HPRE_3 (0x8U << RCC_CFGR_HPRE_Pos) /*!< 0x00000080 */
+
+#define RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000) /*!< SYSCLK not divided */
+#define RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080) /*!< SYSCLK divided by 2 */
+#define RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090) /*!< SYSCLK divided by 4 */
+#define RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0) /*!< SYSCLK divided by 8 */
+#define RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0) /*!< SYSCLK divided by 16 */
+#define RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0) /*!< SYSCLK divided by 64 */
+#define RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0) /*!< SYSCLK divided by 128 */
+#define RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0) /*!< SYSCLK divided by 256 */
+#define RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0) /*!< SYSCLK divided by 512 */
+
+/*!< PPRE1 configuration */
+#define RCC_CFGR_PPRE1_Pos (8U)
+#define RCC_CFGR_PPRE1_Msk (0x7U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000700 */
+#define RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_Msk /*!< PRE1[2:0] bits (APB1 prescaler) */
+#define RCC_CFGR_PPRE1_0 (0x1U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000100 */
+#define RCC_CFGR_PPRE1_1 (0x2U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000200 */
+#define RCC_CFGR_PPRE1_2 (0x4U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000400 */
+
+#define RCC_CFGR_PPRE1_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */
+#define RCC_CFGR_PPRE1_DIV2 ((uint32_t)0x00000400) /*!< HCLK divided by 2 */
+#define RCC_CFGR_PPRE1_DIV4 ((uint32_t)0x00000500) /*!< HCLK divided by 4 */
+#define RCC_CFGR_PPRE1_DIV8 ((uint32_t)0x00000600) /*!< HCLK divided by 8 */
+#define RCC_CFGR_PPRE1_DIV16 ((uint32_t)0x00000700) /*!< HCLK divided by 16 */
+
+/*!< PPRE2 configuration */
+#define RCC_CFGR_PPRE2_Pos (11U)
+#define RCC_CFGR_PPRE2_Msk (0x7U << RCC_CFGR_PPRE2_Pos) /*!< 0x00003800 */
+#define RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_Msk /*!< PRE2[2:0] bits (APB2 prescaler) */
+#define RCC_CFGR_PPRE2_0 (0x1U << RCC_CFGR_PPRE2_Pos) /*!< 0x00000800 */
+#define RCC_CFGR_PPRE2_1 (0x2U << RCC_CFGR_PPRE2_Pos) /*!< 0x00001000 */
+#define RCC_CFGR_PPRE2_2 (0x4U << RCC_CFGR_PPRE2_Pos) /*!< 0x00002000 */
+
+#define RCC_CFGR_PPRE2_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */
+#define RCC_CFGR_PPRE2_DIV2 ((uint32_t)0x00002000) /*!< HCLK divided by 2 */
+#define RCC_CFGR_PPRE2_DIV4 ((uint32_t)0x00002800) /*!< HCLK divided by 4 */
+#define RCC_CFGR_PPRE2_DIV8 ((uint32_t)0x00003000) /*!< HCLK divided by 8 */
+#define RCC_CFGR_PPRE2_DIV16 ((uint32_t)0x00003800) /*!< HCLK divided by 16 */
+
+/*!< ADCPPRE configuration */
+#define RCC_CFGR_ADCPRE_Pos (14U)
+#define RCC_CFGR_ADCPRE_Msk (0x3U << RCC_CFGR_ADCPRE_Pos) /*!< 0x0000C000 */
+#define RCC_CFGR_ADCPRE RCC_CFGR_ADCPRE_Msk /*!< ADCPRE[1:0] bits (ADC prescaler) */
+#define RCC_CFGR_ADCPRE_0 (0x1U << RCC_CFGR_ADCPRE_Pos) /*!< 0x00004000 */
+#define RCC_CFGR_ADCPRE_1 (0x2U << RCC_CFGR_ADCPRE_Pos) /*!< 0x00008000 */
+
+#define RCC_CFGR_ADCPRE_DIV2 ((uint32_t)0x00000000) /*!< PCLK2 divided by 2 */
+#define RCC_CFGR_ADCPRE_DIV4 ((uint32_t)0x00004000) /*!< PCLK2 divided by 4 */
+#define RCC_CFGR_ADCPRE_DIV6 ((uint32_t)0x00008000) /*!< PCLK2 divided by 6 */
+#define RCC_CFGR_ADCPRE_DIV8 ((uint32_t)0x0000C000) /*!< PCLK2 divided by 8 */
+
+#define RCC_CFGR_PLLSRC_Pos (16U)
+#define RCC_CFGR_PLLSRC_Msk (0x1U << RCC_CFGR_PLLSRC_Pos) /*!< 0x00010000 */
+#define RCC_CFGR_PLLSRC RCC_CFGR_PLLSRC_Msk /*!< PLL entry clock source */
+
+#define RCC_CFGR_PLLXTPRE_Pos (17U)
+#define RCC_CFGR_PLLXTPRE_Msk (0x1U << RCC_CFGR_PLLXTPRE_Pos) /*!< 0x00020000 */
+#define RCC_CFGR_PLLXTPRE RCC_CFGR_PLLXTPRE_Msk /*!< HSE divider for PLL entry */
+
+/*!< PLLMUL configuration */
+#define RCC_CFGR_PLLMULL_Pos (18U)
+#define RCC_CFGR_PLLMULL_Msk (0xFU << RCC_CFGR_PLLMULL_Pos) /*!< 0x003C0000 */
+#define RCC_CFGR_PLLMULL RCC_CFGR_PLLMULL_Msk /*!< PLLMUL[3:0] bits (PLL multiplication factor) */
+#define RCC_CFGR_PLLMULL_0 (0x1U << RCC_CFGR_PLLMULL_Pos) /*!< 0x00040000 */
+#define RCC_CFGR_PLLMULL_1 (0x2U << RCC_CFGR_PLLMULL_Pos) /*!< 0x00080000 */
+#define RCC_CFGR_PLLMULL_2 (0x4U << RCC_CFGR_PLLMULL_Pos) /*!< 0x00100000 */
+#define RCC_CFGR_PLLMULL_3 (0x8U << RCC_CFGR_PLLMULL_Pos) /*!< 0x00200000 */
+
+#define RCC_CFGR_PLLXTPRE_HSE ((uint32_t)0x00000000) /*!< HSE clock not divided for PLL entry */
+#define RCC_CFGR_PLLXTPRE_HSE_DIV2 ((uint32_t)0x00020000) /*!< HSE clock divided by 2 for PLL entry */
+
+#define RCC_CFGR_PLLMULL2 ((uint32_t)0x00000000) /*!< PLL input clock*2 */
+#define RCC_CFGR_PLLMULL3_Pos (18U)
+#define RCC_CFGR_PLLMULL3_Msk (0x1U << RCC_CFGR_PLLMULL3_Pos) /*!< 0x00040000 */
+#define RCC_CFGR_PLLMULL3 RCC_CFGR_PLLMULL3_Msk /*!< PLL input clock*3 */
+#define RCC_CFGR_PLLMULL4_Pos (19U)
+#define RCC_CFGR_PLLMULL4_Msk (0x1U << RCC_CFGR_PLLMULL4_Pos) /*!< 0x00080000 */
+#define RCC_CFGR_PLLMULL4 RCC_CFGR_PLLMULL4_Msk /*!< PLL input clock*4 */
+#define RCC_CFGR_PLLMULL5_Pos (18U)
+#define RCC_CFGR_PLLMULL5_Msk (0x3U << RCC_CFGR_PLLMULL5_Pos) /*!< 0x000C0000 */
+#define RCC_CFGR_PLLMULL5 RCC_CFGR_PLLMULL5_Msk /*!< PLL input clock*5 */
+#define RCC_CFGR_PLLMULL6_Pos (20U)
+#define RCC_CFGR_PLLMULL6_Msk (0x1U << RCC_CFGR_PLLMULL6_Pos) /*!< 0x00100000 */
+#define RCC_CFGR_PLLMULL6 RCC_CFGR_PLLMULL6_Msk /*!< PLL input clock*6 */
+#define RCC_CFGR_PLLMULL7_Pos (18U)
+#define RCC_CFGR_PLLMULL7_Msk (0x5U << RCC_CFGR_PLLMULL7_Pos) /*!< 0x00140000 */
+#define RCC_CFGR_PLLMULL7 RCC_CFGR_PLLMULL7_Msk /*!< PLL input clock*7 */
+#define RCC_CFGR_PLLMULL8_Pos (19U)
+#define RCC_CFGR_PLLMULL8_Msk (0x3U << RCC_CFGR_PLLMULL8_Pos) /*!< 0x00180000 */
+#define RCC_CFGR_PLLMULL8 RCC_CFGR_PLLMULL8_Msk /*!< PLL input clock*8 */
+#define RCC_CFGR_PLLMULL9_Pos (18U)
+#define RCC_CFGR_PLLMULL9_Msk (0x7U << RCC_CFGR_PLLMULL9_Pos) /*!< 0x001C0000 */
+#define RCC_CFGR_PLLMULL9 RCC_CFGR_PLLMULL9_Msk /*!< PLL input clock*9 */
+#define RCC_CFGR_PLLMULL10_Pos (21U)
+#define RCC_CFGR_PLLMULL10_Msk (0x1U << RCC_CFGR_PLLMULL10_Pos) /*!< 0x00200000 */
+#define RCC_CFGR_PLLMULL10 RCC_CFGR_PLLMULL10_Msk /*!< PLL input clock10 */
+#define RCC_CFGR_PLLMULL11_Pos (18U)
+#define RCC_CFGR_PLLMULL11_Msk (0x9U << RCC_CFGR_PLLMULL11_Pos) /*!< 0x00240000 */
+#define RCC_CFGR_PLLMULL11 RCC_CFGR_PLLMULL11_Msk /*!< PLL input clock*11 */
+#define RCC_CFGR_PLLMULL12_Pos (19U)
+#define RCC_CFGR_PLLMULL12_Msk (0x5U << RCC_CFGR_PLLMULL12_Pos) /*!< 0x00280000 */
+#define RCC_CFGR_PLLMULL12 RCC_CFGR_PLLMULL12_Msk /*!< PLL input clock*12 */
+#define RCC_CFGR_PLLMULL13_Pos (18U)
+#define RCC_CFGR_PLLMULL13_Msk (0xBU << RCC_CFGR_PLLMULL13_Pos) /*!< 0x002C0000 */
+#define RCC_CFGR_PLLMULL13 RCC_CFGR_PLLMULL13_Msk /*!< PLL input clock*13 */
+#define RCC_CFGR_PLLMULL14_Pos (20U)
+#define RCC_CFGR_PLLMULL14_Msk (0x3U << RCC_CFGR_PLLMULL14_Pos) /*!< 0x00300000 */
+#define RCC_CFGR_PLLMULL14 RCC_CFGR_PLLMULL14_Msk /*!< PLL input clock*14 */
+#define RCC_CFGR_PLLMULL15_Pos (18U)
+#define RCC_CFGR_PLLMULL15_Msk (0xDU << RCC_CFGR_PLLMULL15_Pos) /*!< 0x00340000 */
+#define RCC_CFGR_PLLMULL15 RCC_CFGR_PLLMULL15_Msk /*!< PLL input clock*15 */
+#define RCC_CFGR_PLLMULL16_Pos (19U)
+#define RCC_CFGR_PLLMULL16_Msk (0x7U << RCC_CFGR_PLLMULL16_Pos) /*!< 0x00380000 */
+#define RCC_CFGR_PLLMULL16 RCC_CFGR_PLLMULL16_Msk /*!< PLL input clock*16 */
+#define RCC_CFGR_USBPRE_Pos (22U)
+#define RCC_CFGR_USBPRE_Msk (0x1U << RCC_CFGR_USBPRE_Pos) /*!< 0x00400000 */
+#define RCC_CFGR_USBPRE RCC_CFGR_USBPRE_Msk /*!< USB Device prescaler */
+
+/*!< MCO configuration */
+#define RCC_CFGR_MCO_Pos (24U)
+#define RCC_CFGR_MCO_Msk (0x7U << RCC_CFGR_MCO_Pos) /*!< 0x07000000 */
+#define RCC_CFGR_MCO RCC_CFGR_MCO_Msk /*!< MCO[2:0] bits (Microcontroller Clock Output) */
+#define RCC_CFGR_MCO_0 (0x1U << RCC_CFGR_MCO_Pos) /*!< 0x01000000 */
+#define RCC_CFGR_MCO_1 (0x2U << RCC_CFGR_MCO_Pos) /*!< 0x02000000 */
+#define RCC_CFGR_MCO_2 (0x4U << RCC_CFGR_MCO_Pos) /*!< 0x04000000 */
+
+#define RCC_CFGR_MCO_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */
+#define RCC_CFGR_MCO_SYSCLK ((uint32_t)0x04000000) /*!< System clock selected as MCO source */
+#define RCC_CFGR_MCO_HSI ((uint32_t)0x05000000) /*!< HSI clock selected as MCO source */
+#define RCC_CFGR_MCO_HSE ((uint32_t)0x06000000) /*!< HSE clock selected as MCO source */
+#define RCC_CFGR_MCO_PLLCLK_DIV2 ((uint32_t)0x07000000) /*!< PLL clock divided by 2 selected as MCO source */
+
+ /* Reference defines */
+ #define RCC_CFGR_MCOSEL RCC_CFGR_MCO
+ #define RCC_CFGR_MCOSEL_0 RCC_CFGR_MCO_0
+ #define RCC_CFGR_MCOSEL_1 RCC_CFGR_MCO_1
+ #define RCC_CFGR_MCOSEL_2 RCC_CFGR_MCO_2
+ #define RCC_CFGR_MCOSEL_NOCLOCK RCC_CFGR_MCO_NOCLOCK
+ #define RCC_CFGR_MCOSEL_SYSCLK RCC_CFGR_MCO_SYSCLK
+ #define RCC_CFGR_MCOSEL_HSI RCC_CFGR_MCO_HSI
+ #define RCC_CFGR_MCOSEL_HSE RCC_CFGR_MCO_HSE
+ #define RCC_CFGR_MCOSEL_PLL_DIV2 RCC_CFGR_MCO_PLLCLK_DIV2
+
+/*!<****************** Bit definition for RCC_CIR register ********************/
+#define RCC_CIR_LSIRDYF_Pos (0U)
+#define RCC_CIR_LSIRDYF_Msk (0x1U << RCC_CIR_LSIRDYF_Pos) /*!< 0x00000001 */
+#define RCC_CIR_LSIRDYF RCC_CIR_LSIRDYF_Msk /*!< LSI Ready Interrupt flag */
+#define RCC_CIR_LSERDYF_Pos (1U)
+#define RCC_CIR_LSERDYF_Msk (0x1U << RCC_CIR_LSERDYF_Pos) /*!< 0x00000002 */
+#define RCC_CIR_LSERDYF RCC_CIR_LSERDYF_Msk /*!< LSE Ready Interrupt flag */
+#define RCC_CIR_HSIRDYF_Pos (2U)
+#define RCC_CIR_HSIRDYF_Msk (0x1U << RCC_CIR_HSIRDYF_Pos) /*!< 0x00000004 */
+#define RCC_CIR_HSIRDYF RCC_CIR_HSIRDYF_Msk /*!< HSI Ready Interrupt flag */
+#define RCC_CIR_HSERDYF_Pos (3U)
+#define RCC_CIR_HSERDYF_Msk (0x1U << RCC_CIR_HSERDYF_Pos) /*!< 0x00000008 */
+#define RCC_CIR_HSERDYF RCC_CIR_HSERDYF_Msk /*!< HSE Ready Interrupt flag */
+#define RCC_CIR_PLLRDYF_Pos (4U)
+#define RCC_CIR_PLLRDYF_Msk (0x1U << RCC_CIR_PLLRDYF_Pos) /*!< 0x00000010 */
+#define RCC_CIR_PLLRDYF RCC_CIR_PLLRDYF_Msk /*!< PLL Ready Interrupt flag */
+#define RCC_CIR_CSSF_Pos (7U)
+#define RCC_CIR_CSSF_Msk (0x1U << RCC_CIR_CSSF_Pos) /*!< 0x00000080 */
+#define RCC_CIR_CSSF RCC_CIR_CSSF_Msk /*!< Clock Security System Interrupt flag */
+#define RCC_CIR_LSIRDYIE_Pos (8U)
+#define RCC_CIR_LSIRDYIE_Msk (0x1U << RCC_CIR_LSIRDYIE_Pos) /*!< 0x00000100 */
+#define RCC_CIR_LSIRDYIE RCC_CIR_LSIRDYIE_Msk /*!< LSI Ready Interrupt Enable */
+#define RCC_CIR_LSERDYIE_Pos (9U)
+#define RCC_CIR_LSERDYIE_Msk (0x1U << RCC_CIR_LSERDYIE_Pos) /*!< 0x00000200 */
+#define RCC_CIR_LSERDYIE RCC_CIR_LSERDYIE_Msk /*!< LSE Ready Interrupt Enable */
+#define RCC_CIR_HSIRDYIE_Pos (10U)
+#define RCC_CIR_HSIRDYIE_Msk (0x1U << RCC_CIR_HSIRDYIE_Pos) /*!< 0x00000400 */
+#define RCC_CIR_HSIRDYIE RCC_CIR_HSIRDYIE_Msk /*!< HSI Ready Interrupt Enable */
+#define RCC_CIR_HSERDYIE_Pos (11U)
+#define RCC_CIR_HSERDYIE_Msk (0x1U << RCC_CIR_HSERDYIE_Pos) /*!< 0x00000800 */
+#define RCC_CIR_HSERDYIE RCC_CIR_HSERDYIE_Msk /*!< HSE Ready Interrupt Enable */
+#define RCC_CIR_PLLRDYIE_Pos (12U)
+#define RCC_CIR_PLLRDYIE_Msk (0x1U << RCC_CIR_PLLRDYIE_Pos) /*!< 0x00001000 */
+#define RCC_CIR_PLLRDYIE RCC_CIR_PLLRDYIE_Msk /*!< PLL Ready Interrupt Enable */
+#define RCC_CIR_LSIRDYC_Pos (16U)
+#define RCC_CIR_LSIRDYC_Msk (0x1U << RCC_CIR_LSIRDYC_Pos) /*!< 0x00010000 */
+#define RCC_CIR_LSIRDYC RCC_CIR_LSIRDYC_Msk /*!< LSI Ready Interrupt Clear */
+#define RCC_CIR_LSERDYC_Pos (17U)
+#define RCC_CIR_LSERDYC_Msk (0x1U << RCC_CIR_LSERDYC_Pos) /*!< 0x00020000 */
+#define RCC_CIR_LSERDYC RCC_CIR_LSERDYC_Msk /*!< LSE Ready Interrupt Clear */
+#define RCC_CIR_HSIRDYC_Pos (18U)
+#define RCC_CIR_HSIRDYC_Msk (0x1U << RCC_CIR_HSIRDYC_Pos) /*!< 0x00040000 */
+#define RCC_CIR_HSIRDYC RCC_CIR_HSIRDYC_Msk /*!< HSI Ready Interrupt Clear */
+#define RCC_CIR_HSERDYC_Pos (19U)
+#define RCC_CIR_HSERDYC_Msk (0x1U << RCC_CIR_HSERDYC_Pos) /*!< 0x00080000 */
+#define RCC_CIR_HSERDYC RCC_CIR_HSERDYC_Msk /*!< HSE Ready Interrupt Clear */
+#define RCC_CIR_PLLRDYC_Pos (20U)
+#define RCC_CIR_PLLRDYC_Msk (0x1U << RCC_CIR_PLLRDYC_Pos) /*!< 0x00100000 */
+#define RCC_CIR_PLLRDYC RCC_CIR_PLLRDYC_Msk /*!< PLL Ready Interrupt Clear */
+#define RCC_CIR_CSSC_Pos (23U)
+#define RCC_CIR_CSSC_Msk (0x1U << RCC_CIR_CSSC_Pos) /*!< 0x00800000 */
+#define RCC_CIR_CSSC RCC_CIR_CSSC_Msk /*!< Clock Security System Interrupt Clear */
+
+
+/***************** Bit definition for RCC_APB2RSTR register *****************/
+#define RCC_APB2RSTR_AFIORST_Pos (0U)
+#define RCC_APB2RSTR_AFIORST_Msk (0x1U << RCC_APB2RSTR_AFIORST_Pos) /*!< 0x00000001 */
+#define RCC_APB2RSTR_AFIORST RCC_APB2RSTR_AFIORST_Msk /*!< Alternate Function I/O reset */
+#define RCC_APB2RSTR_IOPARST_Pos (2U)
+#define RCC_APB2RSTR_IOPARST_Msk (0x1U << RCC_APB2RSTR_IOPARST_Pos) /*!< 0x00000004 */
+#define RCC_APB2RSTR_IOPARST RCC_APB2RSTR_IOPARST_Msk /*!< I/O port A reset */
+#define RCC_APB2RSTR_IOPBRST_Pos (3U)
+#define RCC_APB2RSTR_IOPBRST_Msk (0x1U << RCC_APB2RSTR_IOPBRST_Pos) /*!< 0x00000008 */
+#define RCC_APB2RSTR_IOPBRST RCC_APB2RSTR_IOPBRST_Msk /*!< I/O port B reset */
+#define RCC_APB2RSTR_IOPCRST_Pos (4U)
+#define RCC_APB2RSTR_IOPCRST_Msk (0x1U << RCC_APB2RSTR_IOPCRST_Pos) /*!< 0x00000010 */
+#define RCC_APB2RSTR_IOPCRST RCC_APB2RSTR_IOPCRST_Msk /*!< I/O port C reset */
+#define RCC_APB2RSTR_IOPDRST_Pos (5U)
+#define RCC_APB2RSTR_IOPDRST_Msk (0x1U << RCC_APB2RSTR_IOPDRST_Pos) /*!< 0x00000020 */
+#define RCC_APB2RSTR_IOPDRST RCC_APB2RSTR_IOPDRST_Msk /*!< I/O port D reset */
+#define RCC_APB2RSTR_ADC1RST_Pos (9U)
+#define RCC_APB2RSTR_ADC1RST_Msk (0x1U << RCC_APB2RSTR_ADC1RST_Pos) /*!< 0x00000200 */
+#define RCC_APB2RSTR_ADC1RST RCC_APB2RSTR_ADC1RST_Msk /*!< ADC 1 interface reset */
+
+#define RCC_APB2RSTR_ADC2RST_Pos (10U)
+#define RCC_APB2RSTR_ADC2RST_Msk (0x1U << RCC_APB2RSTR_ADC2RST_Pos) /*!< 0x00000400 */
+#define RCC_APB2RSTR_ADC2RST RCC_APB2RSTR_ADC2RST_Msk /*!< ADC 2 interface reset */
+
+#define RCC_APB2RSTR_TIM1RST_Pos (11U)
+#define RCC_APB2RSTR_TIM1RST_Msk (0x1U << RCC_APB2RSTR_TIM1RST_Pos) /*!< 0x00000800 */
+#define RCC_APB2RSTR_TIM1RST RCC_APB2RSTR_TIM1RST_Msk /*!< TIM1 Timer reset */
+#define RCC_APB2RSTR_SPI1RST_Pos (12U)
+#define RCC_APB2RSTR_SPI1RST_Msk (0x1U << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */
+#define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk /*!< SPI 1 reset */
+#define RCC_APB2RSTR_USART1RST_Pos (14U)
+#define RCC_APB2RSTR_USART1RST_Msk (0x1U << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00004000 */
+#define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk /*!< USART1 reset */
+
+
+
+
+
+
+/***************** Bit definition for RCC_APB1RSTR register *****************/
+#define RCC_APB1RSTR_TIM2RST_Pos (0U)
+#define RCC_APB1RSTR_TIM2RST_Msk (0x1U << RCC_APB1RSTR_TIM2RST_Pos) /*!< 0x00000001 */
+#define RCC_APB1RSTR_TIM2RST RCC_APB1RSTR_TIM2RST_Msk /*!< Timer 2 reset */
+#define RCC_APB1RSTR_TIM3RST_Pos (1U)
+#define RCC_APB1RSTR_TIM3RST_Msk (0x1U << RCC_APB1RSTR_TIM3RST_Pos) /*!< 0x00000002 */
+#define RCC_APB1RSTR_TIM3RST RCC_APB1RSTR_TIM3RST_Msk /*!< Timer 3 reset */
+#define RCC_APB1RSTR_WWDGRST_Pos (11U)
+#define RCC_APB1RSTR_WWDGRST_Msk (0x1U << RCC_APB1RSTR_WWDGRST_Pos) /*!< 0x00000800 */
+#define RCC_APB1RSTR_WWDGRST RCC_APB1RSTR_WWDGRST_Msk /*!< Window Watchdog reset */
+#define RCC_APB1RSTR_USART2RST_Pos (17U)
+#define RCC_APB1RSTR_USART2RST_Msk (0x1U << RCC_APB1RSTR_USART2RST_Pos) /*!< 0x00020000 */
+#define RCC_APB1RSTR_USART2RST RCC_APB1RSTR_USART2RST_Msk /*!< USART 2 reset */
+#define RCC_APB1RSTR_I2C1RST_Pos (21U)
+#define RCC_APB1RSTR_I2C1RST_Msk (0x1U << RCC_APB1RSTR_I2C1RST_Pos) /*!< 0x00200000 */
+#define RCC_APB1RSTR_I2C1RST RCC_APB1RSTR_I2C1RST_Msk /*!< I2C 1 reset */
+
+#define RCC_APB1RSTR_CAN1RST_Pos (25U)
+#define RCC_APB1RSTR_CAN1RST_Msk (0x1U << RCC_APB1RSTR_CAN1RST_Pos) /*!< 0x02000000 */
+#define RCC_APB1RSTR_CAN1RST RCC_APB1RSTR_CAN1RST_Msk /*!< CAN1 reset */
+
+#define RCC_APB1RSTR_BKPRST_Pos (27U)
+#define RCC_APB1RSTR_BKPRST_Msk (0x1U << RCC_APB1RSTR_BKPRST_Pos) /*!< 0x08000000 */
+#define RCC_APB1RSTR_BKPRST RCC_APB1RSTR_BKPRST_Msk /*!< Backup interface reset */
+#define RCC_APB1RSTR_PWRRST_Pos (28U)
+#define RCC_APB1RSTR_PWRRST_Msk (0x1U << RCC_APB1RSTR_PWRRST_Pos) /*!< 0x10000000 */
+#define RCC_APB1RSTR_PWRRST RCC_APB1RSTR_PWRRST_Msk /*!< Power interface reset */
+
+
+#define RCC_APB1RSTR_USBRST_Pos (23U)
+#define RCC_APB1RSTR_USBRST_Msk (0x1U << RCC_APB1RSTR_USBRST_Pos) /*!< 0x00800000 */
+#define RCC_APB1RSTR_USBRST RCC_APB1RSTR_USBRST_Msk /*!< USB Device reset */
+
+
+
+
+
+
+/****************** Bit definition for RCC_AHBENR register ******************/
+#define RCC_AHBENR_DMA1EN_Pos (0U)
+#define RCC_AHBENR_DMA1EN_Msk (0x1U << RCC_AHBENR_DMA1EN_Pos) /*!< 0x00000001 */
+#define RCC_AHBENR_DMA1EN RCC_AHBENR_DMA1EN_Msk /*!< DMA1 clock enable */
+#define RCC_AHBENR_SRAMEN_Pos (2U)
+#define RCC_AHBENR_SRAMEN_Msk (0x1U << RCC_AHBENR_SRAMEN_Pos) /*!< 0x00000004 */
+#define RCC_AHBENR_SRAMEN RCC_AHBENR_SRAMEN_Msk /*!< SRAM interface clock enable */
+#define RCC_AHBENR_FLITFEN_Pos (4U)
+#define RCC_AHBENR_FLITFEN_Msk (0x1U << RCC_AHBENR_FLITFEN_Pos) /*!< 0x00000010 */
+#define RCC_AHBENR_FLITFEN RCC_AHBENR_FLITFEN_Msk /*!< FLITF clock enable */
+#define RCC_AHBENR_CRCEN_Pos (6U)
+#define RCC_AHBENR_CRCEN_Msk (0x1U << RCC_AHBENR_CRCEN_Pos) /*!< 0x00000040 */
+#define RCC_AHBENR_CRCEN RCC_AHBENR_CRCEN_Msk /*!< CRC clock enable */
+
+
+
+
+/****************** Bit definition for RCC_APB2ENR register *****************/
+#define RCC_APB2ENR_AFIOEN_Pos (0U)
+#define RCC_APB2ENR_AFIOEN_Msk (0x1U << RCC_APB2ENR_AFIOEN_Pos) /*!< 0x00000001 */
+#define RCC_APB2ENR_AFIOEN RCC_APB2ENR_AFIOEN_Msk /*!< Alternate Function I/O clock enable */
+#define RCC_APB2ENR_IOPAEN_Pos (2U)
+#define RCC_APB2ENR_IOPAEN_Msk (0x1U << RCC_APB2ENR_IOPAEN_Pos) /*!< 0x00000004 */
+#define RCC_APB2ENR_IOPAEN RCC_APB2ENR_IOPAEN_Msk /*!< I/O port A clock enable */
+#define RCC_APB2ENR_IOPBEN_Pos (3U)
+#define RCC_APB2ENR_IOPBEN_Msk (0x1U << RCC_APB2ENR_IOPBEN_Pos) /*!< 0x00000008 */
+#define RCC_APB2ENR_IOPBEN RCC_APB2ENR_IOPBEN_Msk /*!< I/O port B clock enable */
+#define RCC_APB2ENR_IOPCEN_Pos (4U)
+#define RCC_APB2ENR_IOPCEN_Msk (0x1U << RCC_APB2ENR_IOPCEN_Pos) /*!< 0x00000010 */
+#define RCC_APB2ENR_IOPCEN RCC_APB2ENR_IOPCEN_Msk /*!< I/O port C clock enable */
+#define RCC_APB2ENR_IOPDEN_Pos (5U)
+#define RCC_APB2ENR_IOPDEN_Msk (0x1U << RCC_APB2ENR_IOPDEN_Pos) /*!< 0x00000020 */
+#define RCC_APB2ENR_IOPDEN RCC_APB2ENR_IOPDEN_Msk /*!< I/O port D clock enable */
+#define RCC_APB2ENR_ADC1EN_Pos (9U)
+#define RCC_APB2ENR_ADC1EN_Msk (0x1U << RCC_APB2ENR_ADC1EN_Pos) /*!< 0x00000200 */
+#define RCC_APB2ENR_ADC1EN RCC_APB2ENR_ADC1EN_Msk /*!< ADC 1 interface clock enable */
+
+#define RCC_APB2ENR_ADC2EN_Pos (10U)
+#define RCC_APB2ENR_ADC2EN_Msk (0x1U << RCC_APB2ENR_ADC2EN_Pos) /*!< 0x00000400 */
+#define RCC_APB2ENR_ADC2EN RCC_APB2ENR_ADC2EN_Msk /*!< ADC 2 interface clock enable */
+
+#define RCC_APB2ENR_TIM1EN_Pos (11U)
+#define RCC_APB2ENR_TIM1EN_Msk (0x1U << RCC_APB2ENR_TIM1EN_Pos) /*!< 0x00000800 */
+#define RCC_APB2ENR_TIM1EN RCC_APB2ENR_TIM1EN_Msk /*!< TIM1 Timer clock enable */
+#define RCC_APB2ENR_SPI1EN_Pos (12U)
+#define RCC_APB2ENR_SPI1EN_Msk (0x1U << RCC_APB2ENR_SPI1EN_Pos) /*!< 0x00001000 */
+#define RCC_APB2ENR_SPI1EN RCC_APB2ENR_SPI1EN_Msk /*!< SPI 1 clock enable */
+#define RCC_APB2ENR_USART1EN_Pos (14U)
+#define RCC_APB2ENR_USART1EN_Msk (0x1U << RCC_APB2ENR_USART1EN_Pos) /*!< 0x00004000 */
+#define RCC_APB2ENR_USART1EN RCC_APB2ENR_USART1EN_Msk /*!< USART1 clock enable */
+
+
+
+
+
+
+/***************** Bit definition for RCC_APB1ENR register ******************/
+#define RCC_APB1ENR_TIM2EN_Pos (0U)
+#define RCC_APB1ENR_TIM2EN_Msk (0x1U << RCC_APB1ENR_TIM2EN_Pos) /*!< 0x00000001 */
+#define RCC_APB1ENR_TIM2EN RCC_APB1ENR_TIM2EN_Msk /*!< Timer 2 clock enabled*/
+#define RCC_APB1ENR_TIM3EN_Pos (1U)
+#define RCC_APB1ENR_TIM3EN_Msk (0x1U << RCC_APB1ENR_TIM3EN_Pos) /*!< 0x00000002 */
+#define RCC_APB1ENR_TIM3EN RCC_APB1ENR_TIM3EN_Msk /*!< Timer 3 clock enable */
+#define RCC_APB1ENR_WWDGEN_Pos (11U)
+#define RCC_APB1ENR_WWDGEN_Msk (0x1U << RCC_APB1ENR_WWDGEN_Pos) /*!< 0x00000800 */
+#define RCC_APB1ENR_WWDGEN RCC_APB1ENR_WWDGEN_Msk /*!< Window Watchdog clock enable */
+#define RCC_APB1ENR_USART2EN_Pos (17U)
+#define RCC_APB1ENR_USART2EN_Msk (0x1U << RCC_APB1ENR_USART2EN_Pos) /*!< 0x00020000 */
+#define RCC_APB1ENR_USART2EN RCC_APB1ENR_USART2EN_Msk /*!< USART 2 clock enable */
+#define RCC_APB1ENR_I2C1EN_Pos (21U)
+#define RCC_APB1ENR_I2C1EN_Msk (0x1U << RCC_APB1ENR_I2C1EN_Pos) /*!< 0x00200000 */
+#define RCC_APB1ENR_I2C1EN RCC_APB1ENR_I2C1EN_Msk /*!< I2C 1 clock enable */
+
+#define RCC_APB1ENR_CAN1EN_Pos (25U)
+#define RCC_APB1ENR_CAN1EN_Msk (0x1U << RCC_APB1ENR_CAN1EN_Pos) /*!< 0x02000000 */
+#define RCC_APB1ENR_CAN1EN RCC_APB1ENR_CAN1EN_Msk /*!< CAN1 clock enable */
+
+#define RCC_APB1ENR_BKPEN_Pos (27U)
+#define RCC_APB1ENR_BKPEN_Msk (0x1U << RCC_APB1ENR_BKPEN_Pos) /*!< 0x08000000 */
+#define RCC_APB1ENR_BKPEN RCC_APB1ENR_BKPEN_Msk /*!< Backup interface clock enable */
+#define RCC_APB1ENR_PWREN_Pos (28U)
+#define RCC_APB1ENR_PWREN_Msk (0x1U << RCC_APB1ENR_PWREN_Pos) /*!< 0x10000000 */
+#define RCC_APB1ENR_PWREN RCC_APB1ENR_PWREN_Msk /*!< Power interface clock enable */
+
+
+#define RCC_APB1ENR_USBEN_Pos (23U)
+#define RCC_APB1ENR_USBEN_Msk (0x1U << RCC_APB1ENR_USBEN_Pos) /*!< 0x00800000 */
+#define RCC_APB1ENR_USBEN RCC_APB1ENR_USBEN_Msk /*!< USB Device clock enable */
+
+
+
+
+
+
+/******************* Bit definition for RCC_BDCR register *******************/
+#define RCC_BDCR_LSEON_Pos (0U)
+#define RCC_BDCR_LSEON_Msk (0x1U << RCC_BDCR_LSEON_Pos) /*!< 0x00000001 */
+#define RCC_BDCR_LSEON RCC_BDCR_LSEON_Msk /*!< External Low Speed oscillator enable */
+#define RCC_BDCR_LSERDY_Pos (1U)
+#define RCC_BDCR_LSERDY_Msk (0x1U << RCC_BDCR_LSERDY_Pos) /*!< 0x00000002 */
+#define RCC_BDCR_LSERDY RCC_BDCR_LSERDY_Msk /*!< External Low Speed oscillator Ready */
+#define RCC_BDCR_LSEBYP_Pos (2U)
+#define RCC_BDCR_LSEBYP_Msk (0x1U << RCC_BDCR_LSEBYP_Pos) /*!< 0x00000004 */
+#define RCC_BDCR_LSEBYP RCC_BDCR_LSEBYP_Msk /*!< External Low Speed oscillator Bypass */
+
+#define RCC_BDCR_RTCSEL_Pos (8U)
+#define RCC_BDCR_RTCSEL_Msk (0x3U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000300 */
+#define RCC_BDCR_RTCSEL RCC_BDCR_RTCSEL_Msk /*!< RTCSEL[1:0] bits (RTC clock source selection) */
+#define RCC_BDCR_RTCSEL_0 (0x1U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000100 */
+#define RCC_BDCR_RTCSEL_1 (0x2U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000200 */
+
+/*!< RTC congiguration */
+#define RCC_BDCR_RTCSEL_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */
+#define RCC_BDCR_RTCSEL_LSE ((uint32_t)0x00000100) /*!< LSE oscillator clock used as RTC clock */
+#define RCC_BDCR_RTCSEL_LSI ((uint32_t)0x00000200) /*!< LSI oscillator clock used as RTC clock */
+#define RCC_BDCR_RTCSEL_HSE ((uint32_t)0x00000300) /*!< HSE oscillator clock divided by 128 used as RTC clock */
+
+#define RCC_BDCR_RTCEN_Pos (15U)
+#define RCC_BDCR_RTCEN_Msk (0x1U << RCC_BDCR_RTCEN_Pos) /*!< 0x00008000 */
+#define RCC_BDCR_RTCEN RCC_BDCR_RTCEN_Msk /*!< RTC clock enable */
+#define RCC_BDCR_BDRST_Pos (16U)
+#define RCC_BDCR_BDRST_Msk (0x1U << RCC_BDCR_BDRST_Pos) /*!< 0x00010000 */
+#define RCC_BDCR_BDRST RCC_BDCR_BDRST_Msk /*!< Backup domain software reset */
+
+/******************* Bit definition for RCC_CSR register ********************/
+#define RCC_CSR_LSION_Pos (0U)
+#define RCC_CSR_LSION_Msk (0x1U << RCC_CSR_LSION_Pos) /*!< 0x00000001 */
+#define RCC_CSR_LSION RCC_CSR_LSION_Msk /*!< Internal Low Speed oscillator enable */
+#define RCC_CSR_LSIRDY_Pos (1U)
+#define RCC_CSR_LSIRDY_Msk (0x1U << RCC_CSR_LSIRDY_Pos) /*!< 0x00000002 */
+#define RCC_CSR_LSIRDY RCC_CSR_LSIRDY_Msk /*!< Internal Low Speed oscillator Ready */
+#define RCC_CSR_RMVF_Pos (24U)
+#define RCC_CSR_RMVF_Msk (0x1U << RCC_CSR_RMVF_Pos) /*!< 0x01000000 */
+#define RCC_CSR_RMVF RCC_CSR_RMVF_Msk /*!< Remove reset flag */
+#define RCC_CSR_PINRSTF_Pos (26U)
+#define RCC_CSR_PINRSTF_Msk (0x1U << RCC_CSR_PINRSTF_Pos) /*!< 0x04000000 */
+#define RCC_CSR_PINRSTF RCC_CSR_PINRSTF_Msk /*!< PIN reset flag */
+#define RCC_CSR_PORRSTF_Pos (27U)
+#define RCC_CSR_PORRSTF_Msk (0x1U << RCC_CSR_PORRSTF_Pos) /*!< 0x08000000 */
+#define RCC_CSR_PORRSTF RCC_CSR_PORRSTF_Msk /*!< POR/PDR reset flag */
+#define RCC_CSR_SFTRSTF_Pos (28U)
+#define RCC_CSR_SFTRSTF_Msk (0x1U << RCC_CSR_SFTRSTF_Pos) /*!< 0x10000000 */
+#define RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF_Msk /*!< Software Reset flag */
+#define RCC_CSR_IWDGRSTF_Pos (29U)
+#define RCC_CSR_IWDGRSTF_Msk (0x1U << RCC_CSR_IWDGRSTF_Pos) /*!< 0x20000000 */
+#define RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF_Msk /*!< Independent Watchdog reset flag */
+#define RCC_CSR_WWDGRSTF_Pos (30U)
+#define RCC_CSR_WWDGRSTF_Msk (0x1U << RCC_CSR_WWDGRSTF_Pos) /*!< 0x40000000 */
+#define RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF_Msk /*!< Window watchdog reset flag */
+#define RCC_CSR_LPWRRSTF_Pos (31U)
+#define RCC_CSR_LPWRRSTF_Msk (0x1U << RCC_CSR_LPWRRSTF_Pos) /*!< 0x80000000 */
+#define RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF_Msk /*!< Low-Power reset flag */
+
+
+
+/******************************************************************************/
+/* */
+/* General Purpose and Alternate Function I/O */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for GPIO_CRL register *******************/
+#define GPIO_CRL_MODE_Pos (0U)
+#define GPIO_CRL_MODE_Msk (0x33333333U << GPIO_CRL_MODE_Pos) /*!< 0x33333333 */
+#define GPIO_CRL_MODE GPIO_CRL_MODE_Msk /*!< Port x mode bits */
+
+#define GPIO_CRL_MODE0_Pos (0U)
+#define GPIO_CRL_MODE0_Msk (0x3U << GPIO_CRL_MODE0_Pos) /*!< 0x00000003 */
+#define GPIO_CRL_MODE0 GPIO_CRL_MODE0_Msk /*!< MODE0[1:0] bits (Port x mode bits, pin 0) */
+#define GPIO_CRL_MODE0_0 (0x1U << GPIO_CRL_MODE0_Pos) /*!< 0x00000001 */
+#define GPIO_CRL_MODE0_1 (0x2U << GPIO_CRL_MODE0_Pos) /*!< 0x00000002 */
+
+#define GPIO_CRL_MODE1_Pos (4U)
+#define GPIO_CRL_MODE1_Msk (0x3U << GPIO_CRL_MODE1_Pos) /*!< 0x00000030 */
+#define GPIO_CRL_MODE1 GPIO_CRL_MODE1_Msk /*!< MODE1[1:0] bits (Port x mode bits, pin 1) */
+#define GPIO_CRL_MODE1_0 (0x1U << GPIO_CRL_MODE1_Pos) /*!< 0x00000010 */
+#define GPIO_CRL_MODE1_1 (0x2U << GPIO_CRL_MODE1_Pos) /*!< 0x00000020 */
+
+#define GPIO_CRL_MODE2_Pos (8U)
+#define GPIO_CRL_MODE2_Msk (0x3U << GPIO_CRL_MODE2_Pos) /*!< 0x00000300 */
+#define GPIO_CRL_MODE2 GPIO_CRL_MODE2_Msk /*!< MODE2[1:0] bits (Port x mode bits, pin 2) */
+#define GPIO_CRL_MODE2_0 (0x1U << GPIO_CRL_MODE2_Pos) /*!< 0x00000100 */
+#define GPIO_CRL_MODE2_1 (0x2U << GPIO_CRL_MODE2_Pos) /*!< 0x00000200 */
+
+#define GPIO_CRL_MODE3_Pos (12U)
+#define GPIO_CRL_MODE3_Msk (0x3U << GPIO_CRL_MODE3_Pos) /*!< 0x00003000 */
+#define GPIO_CRL_MODE3 GPIO_CRL_MODE3_Msk /*!< MODE3[1:0] bits (Port x mode bits, pin 3) */
+#define GPIO_CRL_MODE3_0 (0x1U << GPIO_CRL_MODE3_Pos) /*!< 0x00001000 */
+#define GPIO_CRL_MODE3_1 (0x2U << GPIO_CRL_MODE3_Pos) /*!< 0x00002000 */
+
+#define GPIO_CRL_MODE4_Pos (16U)
+#define GPIO_CRL_MODE4_Msk (0x3U << GPIO_CRL_MODE4_Pos) /*!< 0x00030000 */
+#define GPIO_CRL_MODE4 GPIO_CRL_MODE4_Msk /*!< MODE4[1:0] bits (Port x mode bits, pin 4) */
+#define GPIO_CRL_MODE4_0 (0x1U << GPIO_CRL_MODE4_Pos) /*!< 0x00010000 */
+#define GPIO_CRL_MODE4_1 (0x2U << GPIO_CRL_MODE4_Pos) /*!< 0x00020000 */
+
+#define GPIO_CRL_MODE5_Pos (20U)
+#define GPIO_CRL_MODE5_Msk (0x3U << GPIO_CRL_MODE5_Pos) /*!< 0x00300000 */
+#define GPIO_CRL_MODE5 GPIO_CRL_MODE5_Msk /*!< MODE5[1:0] bits (Port x mode bits, pin 5) */
+#define GPIO_CRL_MODE5_0 (0x1U << GPIO_CRL_MODE5_Pos) /*!< 0x00100000 */
+#define GPIO_CRL_MODE5_1 (0x2U << GPIO_CRL_MODE5_Pos) /*!< 0x00200000 */
+
+#define GPIO_CRL_MODE6_Pos (24U)
+#define GPIO_CRL_MODE6_Msk (0x3U << GPIO_CRL_MODE6_Pos) /*!< 0x03000000 */
+#define GPIO_CRL_MODE6 GPIO_CRL_MODE6_Msk /*!< MODE6[1:0] bits (Port x mode bits, pin 6) */
+#define GPIO_CRL_MODE6_0 (0x1U << GPIO_CRL_MODE6_Pos) /*!< 0x01000000 */
+#define GPIO_CRL_MODE6_1 (0x2U << GPIO_CRL_MODE6_Pos) /*!< 0x02000000 */
+
+#define GPIO_CRL_MODE7_Pos (28U)
+#define GPIO_CRL_MODE7_Msk (0x3U << GPIO_CRL_MODE7_Pos) /*!< 0x30000000 */
+#define GPIO_CRL_MODE7 GPIO_CRL_MODE7_Msk /*!< MODE7[1:0] bits (Port x mode bits, pin 7) */
+#define GPIO_CRL_MODE7_0 (0x1U << GPIO_CRL_MODE7_Pos) /*!< 0x10000000 */
+#define GPIO_CRL_MODE7_1 (0x2U << GPIO_CRL_MODE7_Pos) /*!< 0x20000000 */
+
+#define GPIO_CRL_CNF_Pos (2U)
+#define GPIO_CRL_CNF_Msk (0x33333333U << GPIO_CRL_CNF_Pos) /*!< 0xCCCCCCCC */
+#define GPIO_CRL_CNF GPIO_CRL_CNF_Msk /*!< Port x configuration bits */
+
+#define GPIO_CRL_CNF0_Pos (2U)
+#define GPIO_CRL_CNF0_Msk (0x3U << GPIO_CRL_CNF0_Pos) /*!< 0x0000000C */
+#define GPIO_CRL_CNF0 GPIO_CRL_CNF0_Msk /*!< CNF0[1:0] bits (Port x configuration bits, pin 0) */
+#define GPIO_CRL_CNF0_0 (0x1U << GPIO_CRL_CNF0_Pos) /*!< 0x00000004 */
+#define GPIO_CRL_CNF0_1 (0x2U << GPIO_CRL_CNF0_Pos) /*!< 0x00000008 */
+
+#define GPIO_CRL_CNF1_Pos (6U)
+#define GPIO_CRL_CNF1_Msk (0x3U << GPIO_CRL_CNF1_Pos) /*!< 0x000000C0 */
+#define GPIO_CRL_CNF1 GPIO_CRL_CNF1_Msk /*!< CNF1[1:0] bits (Port x configuration bits, pin 1) */
+#define GPIO_CRL_CNF1_0 (0x1U << GPIO_CRL_CNF1_Pos) /*!< 0x00000040 */
+#define GPIO_CRL_CNF1_1 (0x2U << GPIO_CRL_CNF1_Pos) /*!< 0x00000080 */
+
+#define GPIO_CRL_CNF2_Pos (10U)
+#define GPIO_CRL_CNF2_Msk (0x3U << GPIO_CRL_CNF2_Pos) /*!< 0x00000C00 */
+#define GPIO_CRL_CNF2 GPIO_CRL_CNF2_Msk /*!< CNF2[1:0] bits (Port x configuration bits, pin 2) */
+#define GPIO_CRL_CNF2_0 (0x1U << GPIO_CRL_CNF2_Pos) /*!< 0x00000400 */
+#define GPIO_CRL_CNF2_1 (0x2U << GPIO_CRL_CNF2_Pos) /*!< 0x00000800 */
+
+#define GPIO_CRL_CNF3_Pos (14U)
+#define GPIO_CRL_CNF3_Msk (0x3U << GPIO_CRL_CNF3_Pos) /*!< 0x0000C000 */
+#define GPIO_CRL_CNF3 GPIO_CRL_CNF3_Msk /*!< CNF3[1:0] bits (Port x configuration bits, pin 3) */
+#define GPIO_CRL_CNF3_0 (0x1U << GPIO_CRL_CNF3_Pos) /*!< 0x00004000 */
+#define GPIO_CRL_CNF3_1 (0x2U << GPIO_CRL_CNF3_Pos) /*!< 0x00008000 */
+
+#define GPIO_CRL_CNF4_Pos (18U)
+#define GPIO_CRL_CNF4_Msk (0x3U << GPIO_CRL_CNF4_Pos) /*!< 0x000C0000 */
+#define GPIO_CRL_CNF4 GPIO_CRL_CNF4_Msk /*!< CNF4[1:0] bits (Port x configuration bits, pin 4) */
+#define GPIO_CRL_CNF4_0 (0x1U << GPIO_CRL_CNF4_Pos) /*!< 0x00040000 */
+#define GPIO_CRL_CNF4_1 (0x2U << GPIO_CRL_CNF4_Pos) /*!< 0x00080000 */
+
+#define GPIO_CRL_CNF5_Pos (22U)
+#define GPIO_CRL_CNF5_Msk (0x3U << GPIO_CRL_CNF5_Pos) /*!< 0x00C00000 */
+#define GPIO_CRL_CNF5 GPIO_CRL_CNF5_Msk /*!< CNF5[1:0] bits (Port x configuration bits, pin 5) */
+#define GPIO_CRL_CNF5_0 (0x1U << GPIO_CRL_CNF5_Pos) /*!< 0x00400000 */
+#define GPIO_CRL_CNF5_1 (0x2U << GPIO_CRL_CNF5_Pos) /*!< 0x00800000 */
+
+#define GPIO_CRL_CNF6_Pos (26U)
+#define GPIO_CRL_CNF6_Msk (0x3U << GPIO_CRL_CNF6_Pos) /*!< 0x0C000000 */
+#define GPIO_CRL_CNF6 GPIO_CRL_CNF6_Msk /*!< CNF6[1:0] bits (Port x configuration bits, pin 6) */
+#define GPIO_CRL_CNF6_0 (0x1U << GPIO_CRL_CNF6_Pos) /*!< 0x04000000 */
+#define GPIO_CRL_CNF6_1 (0x2U << GPIO_CRL_CNF6_Pos) /*!< 0x08000000 */
+
+#define GPIO_CRL_CNF7_Pos (30U)
+#define GPIO_CRL_CNF7_Msk (0x3U << GPIO_CRL_CNF7_Pos) /*!< 0xC0000000 */
+#define GPIO_CRL_CNF7 GPIO_CRL_CNF7_Msk /*!< CNF7[1:0] bits (Port x configuration bits, pin 7) */
+#define GPIO_CRL_CNF7_0 (0x1U << GPIO_CRL_CNF7_Pos) /*!< 0x40000000 */
+#define GPIO_CRL_CNF7_1 (0x2U << GPIO_CRL_CNF7_Pos) /*!< 0x80000000 */
+
+/******************* Bit definition for GPIO_CRH register *******************/
+#define GPIO_CRH_MODE_Pos (0U)
+#define GPIO_CRH_MODE_Msk (0x33333333U << GPIO_CRH_MODE_Pos) /*!< 0x33333333 */
+#define GPIO_CRH_MODE GPIO_CRH_MODE_Msk /*!< Port x mode bits */
+
+#define GPIO_CRH_MODE8_Pos (0U)
+#define GPIO_CRH_MODE8_Msk (0x3U << GPIO_CRH_MODE8_Pos) /*!< 0x00000003 */
+#define GPIO_CRH_MODE8 GPIO_CRH_MODE8_Msk /*!< MODE8[1:0] bits (Port x mode bits, pin 8) */
+#define GPIO_CRH_MODE8_0 (0x1U << GPIO_CRH_MODE8_Pos) /*!< 0x00000001 */
+#define GPIO_CRH_MODE8_1 (0x2U << GPIO_CRH_MODE8_Pos) /*!< 0x00000002 */
+
+#define GPIO_CRH_MODE9_Pos (4U)
+#define GPIO_CRH_MODE9_Msk (0x3U << GPIO_CRH_MODE9_Pos) /*!< 0x00000030 */
+#define GPIO_CRH_MODE9 GPIO_CRH_MODE9_Msk /*!< MODE9[1:0] bits (Port x mode bits, pin 9) */
+#define GPIO_CRH_MODE9_0 (0x1U << GPIO_CRH_MODE9_Pos) /*!< 0x00000010 */
+#define GPIO_CRH_MODE9_1 (0x2U << GPIO_CRH_MODE9_Pos) /*!< 0x00000020 */
+
+#define GPIO_CRH_MODE10_Pos (8U)
+#define GPIO_CRH_MODE10_Msk (0x3U << GPIO_CRH_MODE10_Pos) /*!< 0x00000300 */
+#define GPIO_CRH_MODE10 GPIO_CRH_MODE10_Msk /*!< MODE10[1:0] bits (Port x mode bits, pin 10) */
+#define GPIO_CRH_MODE10_0 (0x1U << GPIO_CRH_MODE10_Pos) /*!< 0x00000100 */
+#define GPIO_CRH_MODE10_1 (0x2U << GPIO_CRH_MODE10_Pos) /*!< 0x00000200 */
+
+#define GPIO_CRH_MODE11_Pos (12U)
+#define GPIO_CRH_MODE11_Msk (0x3U << GPIO_CRH_MODE11_Pos) /*!< 0x00003000 */
+#define GPIO_CRH_MODE11 GPIO_CRH_MODE11_Msk /*!< MODE11[1:0] bits (Port x mode bits, pin 11) */
+#define GPIO_CRH_MODE11_0 (0x1U << GPIO_CRH_MODE11_Pos) /*!< 0x00001000 */
+#define GPIO_CRH_MODE11_1 (0x2U << GPIO_CRH_MODE11_Pos) /*!< 0x00002000 */
+
+#define GPIO_CRH_MODE12_Pos (16U)
+#define GPIO_CRH_MODE12_Msk (0x3U << GPIO_CRH_MODE12_Pos) /*!< 0x00030000 */
+#define GPIO_CRH_MODE12 GPIO_CRH_MODE12_Msk /*!< MODE12[1:0] bits (Port x mode bits, pin 12) */
+#define GPIO_CRH_MODE12_0 (0x1U << GPIO_CRH_MODE12_Pos) /*!< 0x00010000 */
+#define GPIO_CRH_MODE12_1 (0x2U << GPIO_CRH_MODE12_Pos) /*!< 0x00020000 */
+
+#define GPIO_CRH_MODE13_Pos (20U)
+#define GPIO_CRH_MODE13_Msk (0x3U << GPIO_CRH_MODE13_Pos) /*!< 0x00300000 */
+#define GPIO_CRH_MODE13 GPIO_CRH_MODE13_Msk /*!< MODE13[1:0] bits (Port x mode bits, pin 13) */
+#define GPIO_CRH_MODE13_0 (0x1U << GPIO_CRH_MODE13_Pos) /*!< 0x00100000 */
+#define GPIO_CRH_MODE13_1 (0x2U << GPIO_CRH_MODE13_Pos) /*!< 0x00200000 */
+
+#define GPIO_CRH_MODE14_Pos (24U)
+#define GPIO_CRH_MODE14_Msk (0x3U << GPIO_CRH_MODE14_Pos) /*!< 0x03000000 */
+#define GPIO_CRH_MODE14 GPIO_CRH_MODE14_Msk /*!< MODE14[1:0] bits (Port x mode bits, pin 14) */
+#define GPIO_CRH_MODE14_0 (0x1U << GPIO_CRH_MODE14_Pos) /*!< 0x01000000 */
+#define GPIO_CRH_MODE14_1 (0x2U << GPIO_CRH_MODE14_Pos) /*!< 0x02000000 */
+
+#define GPIO_CRH_MODE15_Pos (28U)
+#define GPIO_CRH_MODE15_Msk (0x3U << GPIO_CRH_MODE15_Pos) /*!< 0x30000000 */
+#define GPIO_CRH_MODE15 GPIO_CRH_MODE15_Msk /*!< MODE15[1:0] bits (Port x mode bits, pin 15) */
+#define GPIO_CRH_MODE15_0 (0x1U << GPIO_CRH_MODE15_Pos) /*!< 0x10000000 */
+#define GPIO_CRH_MODE15_1 (0x2U << GPIO_CRH_MODE15_Pos) /*!< 0x20000000 */
+
+#define GPIO_CRH_CNF_Pos (2U)
+#define GPIO_CRH_CNF_Msk (0x33333333U << GPIO_CRH_CNF_Pos) /*!< 0xCCCCCCCC */
+#define GPIO_CRH_CNF GPIO_CRH_CNF_Msk /*!< Port x configuration bits */
+
+#define GPIO_CRH_CNF8_Pos (2U)
+#define GPIO_CRH_CNF8_Msk (0x3U << GPIO_CRH_CNF8_Pos) /*!< 0x0000000C */
+#define GPIO_CRH_CNF8 GPIO_CRH_CNF8_Msk /*!< CNF8[1:0] bits (Port x configuration bits, pin 8) */
+#define GPIO_CRH_CNF8_0 (0x1U << GPIO_CRH_CNF8_Pos) /*!< 0x00000004 */
+#define GPIO_CRH_CNF8_1 (0x2U << GPIO_CRH_CNF8_Pos) /*!< 0x00000008 */
+
+#define GPIO_CRH_CNF9_Pos (6U)
+#define GPIO_CRH_CNF9_Msk (0x3U << GPIO_CRH_CNF9_Pos) /*!< 0x000000C0 */
+#define GPIO_CRH_CNF9 GPIO_CRH_CNF9_Msk /*!< CNF9[1:0] bits (Port x configuration bits, pin 9) */
+#define GPIO_CRH_CNF9_0 (0x1U << GPIO_CRH_CNF9_Pos) /*!< 0x00000040 */
+#define GPIO_CRH_CNF9_1 (0x2U << GPIO_CRH_CNF9_Pos) /*!< 0x00000080 */
+
+#define GPIO_CRH_CNF10_Pos (10U)
+#define GPIO_CRH_CNF10_Msk (0x3U << GPIO_CRH_CNF10_Pos) /*!< 0x00000C00 */
+#define GPIO_CRH_CNF10 GPIO_CRH_CNF10_Msk /*!< CNF10[1:0] bits (Port x configuration bits, pin 10) */
+#define GPIO_CRH_CNF10_0 (0x1U << GPIO_CRH_CNF10_Pos) /*!< 0x00000400 */
+#define GPIO_CRH_CNF10_1 (0x2U << GPIO_CRH_CNF10_Pos) /*!< 0x00000800 */
+
+#define GPIO_CRH_CNF11_Pos (14U)
+#define GPIO_CRH_CNF11_Msk (0x3U << GPIO_CRH_CNF11_Pos) /*!< 0x0000C000 */
+#define GPIO_CRH_CNF11 GPIO_CRH_CNF11_Msk /*!< CNF11[1:0] bits (Port x configuration bits, pin 11) */
+#define GPIO_CRH_CNF11_0 (0x1U << GPIO_CRH_CNF11_Pos) /*!< 0x00004000 */
+#define GPIO_CRH_CNF11_1 (0x2U << GPIO_CRH_CNF11_Pos) /*!< 0x00008000 */
+
+#define GPIO_CRH_CNF12_Pos (18U)
+#define GPIO_CRH_CNF12_Msk (0x3U << GPIO_CRH_CNF12_Pos) /*!< 0x000C0000 */
+#define GPIO_CRH_CNF12 GPIO_CRH_CNF12_Msk /*!< CNF12[1:0] bits (Port x configuration bits, pin 12) */
+#define GPIO_CRH_CNF12_0 (0x1U << GPIO_CRH_CNF12_Pos) /*!< 0x00040000 */
+#define GPIO_CRH_CNF12_1 (0x2U << GPIO_CRH_CNF12_Pos) /*!< 0x00080000 */
+
+#define GPIO_CRH_CNF13_Pos (22U)
+#define GPIO_CRH_CNF13_Msk (0x3U << GPIO_CRH_CNF13_Pos) /*!< 0x00C00000 */
+#define GPIO_CRH_CNF13 GPIO_CRH_CNF13_Msk /*!< CNF13[1:0] bits (Port x configuration bits, pin 13) */
+#define GPIO_CRH_CNF13_0 (0x1U << GPIO_CRH_CNF13_Pos) /*!< 0x00400000 */
+#define GPIO_CRH_CNF13_1 (0x2U << GPIO_CRH_CNF13_Pos) /*!< 0x00800000 */
+
+#define GPIO_CRH_CNF14_Pos (26U)
+#define GPIO_CRH_CNF14_Msk (0x3U << GPIO_CRH_CNF14_Pos) /*!< 0x0C000000 */
+#define GPIO_CRH_CNF14 GPIO_CRH_CNF14_Msk /*!< CNF14[1:0] bits (Port x configuration bits, pin 14) */
+#define GPIO_CRH_CNF14_0 (0x1U << GPIO_CRH_CNF14_Pos) /*!< 0x04000000 */
+#define GPIO_CRH_CNF14_1 (0x2U << GPIO_CRH_CNF14_Pos) /*!< 0x08000000 */
+
+#define GPIO_CRH_CNF15_Pos (30U)
+#define GPIO_CRH_CNF15_Msk (0x3U << GPIO_CRH_CNF15_Pos) /*!< 0xC0000000 */
+#define GPIO_CRH_CNF15 GPIO_CRH_CNF15_Msk /*!< CNF15[1:0] bits (Port x configuration bits, pin 15) */
+#define GPIO_CRH_CNF15_0 (0x1U << GPIO_CRH_CNF15_Pos) /*!< 0x40000000 */
+#define GPIO_CRH_CNF15_1 (0x2U << GPIO_CRH_CNF15_Pos) /*!< 0x80000000 */
+
+/*!<****************** Bit definition for GPIO_IDR register *******************/
+#define GPIO_IDR_IDR0_Pos (0U)
+#define GPIO_IDR_IDR0_Msk (0x1U << GPIO_IDR_IDR0_Pos) /*!< 0x00000001 */
+#define GPIO_IDR_IDR0 GPIO_IDR_IDR0_Msk /*!< Port input data, bit 0 */
+#define GPIO_IDR_IDR1_Pos (1U)
+#define GPIO_IDR_IDR1_Msk (0x1U << GPIO_IDR_IDR1_Pos) /*!< 0x00000002 */
+#define GPIO_IDR_IDR1 GPIO_IDR_IDR1_Msk /*!< Port input data, bit 1 */
+#define GPIO_IDR_IDR2_Pos (2U)
+#define GPIO_IDR_IDR2_Msk (0x1U << GPIO_IDR_IDR2_Pos) /*!< 0x00000004 */
+#define GPIO_IDR_IDR2 GPIO_IDR_IDR2_Msk /*!< Port input data, bit 2 */
+#define GPIO_IDR_IDR3_Pos (3U)
+#define GPIO_IDR_IDR3_Msk (0x1U << GPIO_IDR_IDR3_Pos) /*!< 0x00000008 */
+#define GPIO_IDR_IDR3 GPIO_IDR_IDR3_Msk /*!< Port input data, bit 3 */
+#define GPIO_IDR_IDR4_Pos (4U)
+#define GPIO_IDR_IDR4_Msk (0x1U << GPIO_IDR_IDR4_Pos) /*!< 0x00000010 */
+#define GPIO_IDR_IDR4 GPIO_IDR_IDR4_Msk /*!< Port input data, bit 4 */
+#define GPIO_IDR_IDR5_Pos (5U)
+#define GPIO_IDR_IDR5_Msk (0x1U << GPIO_IDR_IDR5_Pos) /*!< 0x00000020 */
+#define GPIO_IDR_IDR5 GPIO_IDR_IDR5_Msk /*!< Port input data, bit 5 */
+#define GPIO_IDR_IDR6_Pos (6U)
+#define GPIO_IDR_IDR6_Msk (0x1U << GPIO_IDR_IDR6_Pos) /*!< 0x00000040 */
+#define GPIO_IDR_IDR6 GPIO_IDR_IDR6_Msk /*!< Port input data, bit 6 */
+#define GPIO_IDR_IDR7_Pos (7U)
+#define GPIO_IDR_IDR7_Msk (0x1U << GPIO_IDR_IDR7_Pos) /*!< 0x00000080 */
+#define GPIO_IDR_IDR7 GPIO_IDR_IDR7_Msk /*!< Port input data, bit 7 */
+#define GPIO_IDR_IDR8_Pos (8U)
+#define GPIO_IDR_IDR8_Msk (0x1U << GPIO_IDR_IDR8_Pos) /*!< 0x00000100 */
+#define GPIO_IDR_IDR8 GPIO_IDR_IDR8_Msk /*!< Port input data, bit 8 */
+#define GPIO_IDR_IDR9_Pos (9U)
+#define GPIO_IDR_IDR9_Msk (0x1U << GPIO_IDR_IDR9_Pos) /*!< 0x00000200 */
+#define GPIO_IDR_IDR9 GPIO_IDR_IDR9_Msk /*!< Port input data, bit 9 */
+#define GPIO_IDR_IDR10_Pos (10U)
+#define GPIO_IDR_IDR10_Msk (0x1U << GPIO_IDR_IDR10_Pos) /*!< 0x00000400 */
+#define GPIO_IDR_IDR10 GPIO_IDR_IDR10_Msk /*!< Port input data, bit 10 */
+#define GPIO_IDR_IDR11_Pos (11U)
+#define GPIO_IDR_IDR11_Msk (0x1U << GPIO_IDR_IDR11_Pos) /*!< 0x00000800 */
+#define GPIO_IDR_IDR11 GPIO_IDR_IDR11_Msk /*!< Port input data, bit 11 */
+#define GPIO_IDR_IDR12_Pos (12U)
+#define GPIO_IDR_IDR12_Msk (0x1U << GPIO_IDR_IDR12_Pos) /*!< 0x00001000 */
+#define GPIO_IDR_IDR12 GPIO_IDR_IDR12_Msk /*!< Port input data, bit 12 */
+#define GPIO_IDR_IDR13_Pos (13U)
+#define GPIO_IDR_IDR13_Msk (0x1U << GPIO_IDR_IDR13_Pos) /*!< 0x00002000 */
+#define GPIO_IDR_IDR13 GPIO_IDR_IDR13_Msk /*!< Port input data, bit 13 */
+#define GPIO_IDR_IDR14_Pos (14U)
+#define GPIO_IDR_IDR14_Msk (0x1U << GPIO_IDR_IDR14_Pos) /*!< 0x00004000 */
+#define GPIO_IDR_IDR14 GPIO_IDR_IDR14_Msk /*!< Port input data, bit 14 */
+#define GPIO_IDR_IDR15_Pos (15U)
+#define GPIO_IDR_IDR15_Msk (0x1U << GPIO_IDR_IDR15_Pos) /*!< 0x00008000 */
+#define GPIO_IDR_IDR15 GPIO_IDR_IDR15_Msk /*!< Port input data, bit 15 */
+
+/******************* Bit definition for GPIO_ODR register *******************/
+#define GPIO_ODR_ODR0_Pos (0U)
+#define GPIO_ODR_ODR0_Msk (0x1U << GPIO_ODR_ODR0_Pos) /*!< 0x00000001 */
+#define GPIO_ODR_ODR0 GPIO_ODR_ODR0_Msk /*!< Port output data, bit 0 */
+#define GPIO_ODR_ODR1_Pos (1U)
+#define GPIO_ODR_ODR1_Msk (0x1U << GPIO_ODR_ODR1_Pos) /*!< 0x00000002 */
+#define GPIO_ODR_ODR1 GPIO_ODR_ODR1_Msk /*!< Port output data, bit 1 */
+#define GPIO_ODR_ODR2_Pos (2U)
+#define GPIO_ODR_ODR2_Msk (0x1U << GPIO_ODR_ODR2_Pos) /*!< 0x00000004 */
+#define GPIO_ODR_ODR2 GPIO_ODR_ODR2_Msk /*!< Port output data, bit 2 */
+#define GPIO_ODR_ODR3_Pos (3U)
+#define GPIO_ODR_ODR3_Msk (0x1U << GPIO_ODR_ODR3_Pos) /*!< 0x00000008 */
+#define GPIO_ODR_ODR3 GPIO_ODR_ODR3_Msk /*!< Port output data, bit 3 */
+#define GPIO_ODR_ODR4_Pos (4U)
+#define GPIO_ODR_ODR4_Msk (0x1U << GPIO_ODR_ODR4_Pos) /*!< 0x00000010 */
+#define GPIO_ODR_ODR4 GPIO_ODR_ODR4_Msk /*!< Port output data, bit 4 */
+#define GPIO_ODR_ODR5_Pos (5U)
+#define GPIO_ODR_ODR5_Msk (0x1U << GPIO_ODR_ODR5_Pos) /*!< 0x00000020 */
+#define GPIO_ODR_ODR5 GPIO_ODR_ODR5_Msk /*!< Port output data, bit 5 */
+#define GPIO_ODR_ODR6_Pos (6U)
+#define GPIO_ODR_ODR6_Msk (0x1U << GPIO_ODR_ODR6_Pos) /*!< 0x00000040 */
+#define GPIO_ODR_ODR6 GPIO_ODR_ODR6_Msk /*!< Port output data, bit 6 */
+#define GPIO_ODR_ODR7_Pos (7U)
+#define GPIO_ODR_ODR7_Msk (0x1U << GPIO_ODR_ODR7_Pos) /*!< 0x00000080 */
+#define GPIO_ODR_ODR7 GPIO_ODR_ODR7_Msk /*!< Port output data, bit 7 */
+#define GPIO_ODR_ODR8_Pos (8U)
+#define GPIO_ODR_ODR8_Msk (0x1U << GPIO_ODR_ODR8_Pos) /*!< 0x00000100 */
+#define GPIO_ODR_ODR8 GPIO_ODR_ODR8_Msk /*!< Port output data, bit 8 */
+#define GPIO_ODR_ODR9_Pos (9U)
+#define GPIO_ODR_ODR9_Msk (0x1U << GPIO_ODR_ODR9_Pos) /*!< 0x00000200 */
+#define GPIO_ODR_ODR9 GPIO_ODR_ODR9_Msk /*!< Port output data, bit 9 */
+#define GPIO_ODR_ODR10_Pos (10U)
+#define GPIO_ODR_ODR10_Msk (0x1U << GPIO_ODR_ODR10_Pos) /*!< 0x00000400 */
+#define GPIO_ODR_ODR10 GPIO_ODR_ODR10_Msk /*!< Port output data, bit 10 */
+#define GPIO_ODR_ODR11_Pos (11U)
+#define GPIO_ODR_ODR11_Msk (0x1U << GPIO_ODR_ODR11_Pos) /*!< 0x00000800 */
+#define GPIO_ODR_ODR11 GPIO_ODR_ODR11_Msk /*!< Port output data, bit 11 */
+#define GPIO_ODR_ODR12_Pos (12U)
+#define GPIO_ODR_ODR12_Msk (0x1U << GPIO_ODR_ODR12_Pos) /*!< 0x00001000 */
+#define GPIO_ODR_ODR12 GPIO_ODR_ODR12_Msk /*!< Port output data, bit 12 */
+#define GPIO_ODR_ODR13_Pos (13U)
+#define GPIO_ODR_ODR13_Msk (0x1U << GPIO_ODR_ODR13_Pos) /*!< 0x00002000 */
+#define GPIO_ODR_ODR13 GPIO_ODR_ODR13_Msk /*!< Port output data, bit 13 */
+#define GPIO_ODR_ODR14_Pos (14U)
+#define GPIO_ODR_ODR14_Msk (0x1U << GPIO_ODR_ODR14_Pos) /*!< 0x00004000 */
+#define GPIO_ODR_ODR14 GPIO_ODR_ODR14_Msk /*!< Port output data, bit 14 */
+#define GPIO_ODR_ODR15_Pos (15U)
+#define GPIO_ODR_ODR15_Msk (0x1U << GPIO_ODR_ODR15_Pos) /*!< 0x00008000 */
+#define GPIO_ODR_ODR15 GPIO_ODR_ODR15_Msk /*!< Port output data, bit 15 */
+
+/****************** Bit definition for GPIO_BSRR register *******************/
+#define GPIO_BSRR_BS0_Pos (0U)
+#define GPIO_BSRR_BS0_Msk (0x1U << GPIO_BSRR_BS0_Pos) /*!< 0x00000001 */
+#define GPIO_BSRR_BS0 GPIO_BSRR_BS0_Msk /*!< Port x Set bit 0 */
+#define GPIO_BSRR_BS1_Pos (1U)
+#define GPIO_BSRR_BS1_Msk (0x1U << GPIO_BSRR_BS1_Pos) /*!< 0x00000002 */
+#define GPIO_BSRR_BS1 GPIO_BSRR_BS1_Msk /*!< Port x Set bit 1 */
+#define GPIO_BSRR_BS2_Pos (2U)
+#define GPIO_BSRR_BS2_Msk (0x1U << GPIO_BSRR_BS2_Pos) /*!< 0x00000004 */
+#define GPIO_BSRR_BS2 GPIO_BSRR_BS2_Msk /*!< Port x Set bit 2 */
+#define GPIO_BSRR_BS3_Pos (3U)
+#define GPIO_BSRR_BS3_Msk (0x1U << GPIO_BSRR_BS3_Pos) /*!< 0x00000008 */
+#define GPIO_BSRR_BS3 GPIO_BSRR_BS3_Msk /*!< Port x Set bit 3 */
+#define GPIO_BSRR_BS4_Pos (4U)
+#define GPIO_BSRR_BS4_Msk (0x1U << GPIO_BSRR_BS4_Pos) /*!< 0x00000010 */
+#define GPIO_BSRR_BS4 GPIO_BSRR_BS4_Msk /*!< Port x Set bit 4 */
+#define GPIO_BSRR_BS5_Pos (5U)
+#define GPIO_BSRR_BS5_Msk (0x1U << GPIO_BSRR_BS5_Pos) /*!< 0x00000020 */
+#define GPIO_BSRR_BS5 GPIO_BSRR_BS5_Msk /*!< Port x Set bit 5 */
+#define GPIO_BSRR_BS6_Pos (6U)
+#define GPIO_BSRR_BS6_Msk (0x1U << GPIO_BSRR_BS6_Pos) /*!< 0x00000040 */
+#define GPIO_BSRR_BS6 GPIO_BSRR_BS6_Msk /*!< Port x Set bit 6 */
+#define GPIO_BSRR_BS7_Pos (7U)
+#define GPIO_BSRR_BS7_Msk (0x1U << GPIO_BSRR_BS7_Pos) /*!< 0x00000080 */
+#define GPIO_BSRR_BS7 GPIO_BSRR_BS7_Msk /*!< Port x Set bit 7 */
+#define GPIO_BSRR_BS8_Pos (8U)
+#define GPIO_BSRR_BS8_Msk (0x1U << GPIO_BSRR_BS8_Pos) /*!< 0x00000100 */
+#define GPIO_BSRR_BS8 GPIO_BSRR_BS8_Msk /*!< Port x Set bit 8 */
+#define GPIO_BSRR_BS9_Pos (9U)
+#define GPIO_BSRR_BS9_Msk (0x1U << GPIO_BSRR_BS9_Pos) /*!< 0x00000200 */
+#define GPIO_BSRR_BS9 GPIO_BSRR_BS9_Msk /*!< Port x Set bit 9 */
+#define GPIO_BSRR_BS10_Pos (10U)
+#define GPIO_BSRR_BS10_Msk (0x1U << GPIO_BSRR_BS10_Pos) /*!< 0x00000400 */
+#define GPIO_BSRR_BS10 GPIO_BSRR_BS10_Msk /*!< Port x Set bit 10 */
+#define GPIO_BSRR_BS11_Pos (11U)
+#define GPIO_BSRR_BS11_Msk (0x1U << GPIO_BSRR_BS11_Pos) /*!< 0x00000800 */
+#define GPIO_BSRR_BS11 GPIO_BSRR_BS11_Msk /*!< Port x Set bit 11 */
+#define GPIO_BSRR_BS12_Pos (12U)
+#define GPIO_BSRR_BS12_Msk (0x1U << GPIO_BSRR_BS12_Pos) /*!< 0x00001000 */
+#define GPIO_BSRR_BS12 GPIO_BSRR_BS12_Msk /*!< Port x Set bit 12 */
+#define GPIO_BSRR_BS13_Pos (13U)
+#define GPIO_BSRR_BS13_Msk (0x1U << GPIO_BSRR_BS13_Pos) /*!< 0x00002000 */
+#define GPIO_BSRR_BS13 GPIO_BSRR_BS13_Msk /*!< Port x Set bit 13 */
+#define GPIO_BSRR_BS14_Pos (14U)
+#define GPIO_BSRR_BS14_Msk (0x1U << GPIO_BSRR_BS14_Pos) /*!< 0x00004000 */
+#define GPIO_BSRR_BS14 GPIO_BSRR_BS14_Msk /*!< Port x Set bit 14 */
+#define GPIO_BSRR_BS15_Pos (15U)
+#define GPIO_BSRR_BS15_Msk (0x1U << GPIO_BSRR_BS15_Pos) /*!< 0x00008000 */
+#define GPIO_BSRR_BS15 GPIO_BSRR_BS15_Msk /*!< Port x Set bit 15 */
+
+#define GPIO_BSRR_BR0_Pos (16U)
+#define GPIO_BSRR_BR0_Msk (0x1U << GPIO_BSRR_BR0_Pos) /*!< 0x00010000 */
+#define GPIO_BSRR_BR0 GPIO_BSRR_BR0_Msk /*!< Port x Reset bit 0 */
+#define GPIO_BSRR_BR1_Pos (17U)
+#define GPIO_BSRR_BR1_Msk (0x1U << GPIO_BSRR_BR1_Pos) /*!< 0x00020000 */
+#define GPIO_BSRR_BR1 GPIO_BSRR_BR1_Msk /*!< Port x Reset bit 1 */
+#define GPIO_BSRR_BR2_Pos (18U)
+#define GPIO_BSRR_BR2_Msk (0x1U << GPIO_BSRR_BR2_Pos) /*!< 0x00040000 */
+#define GPIO_BSRR_BR2 GPIO_BSRR_BR2_Msk /*!< Port x Reset bit 2 */
+#define GPIO_BSRR_BR3_Pos (19U)
+#define GPIO_BSRR_BR3_Msk (0x1U << GPIO_BSRR_BR3_Pos) /*!< 0x00080000 */
+#define GPIO_BSRR_BR3 GPIO_BSRR_BR3_Msk /*!< Port x Reset bit 3 */
+#define GPIO_BSRR_BR4_Pos (20U)
+#define GPIO_BSRR_BR4_Msk (0x1U << GPIO_BSRR_BR4_Pos) /*!< 0x00100000 */
+#define GPIO_BSRR_BR4 GPIO_BSRR_BR4_Msk /*!< Port x Reset bit 4 */
+#define GPIO_BSRR_BR5_Pos (21U)
+#define GPIO_BSRR_BR5_Msk (0x1U << GPIO_BSRR_BR5_Pos) /*!< 0x00200000 */
+#define GPIO_BSRR_BR5 GPIO_BSRR_BR5_Msk /*!< Port x Reset bit 5 */
+#define GPIO_BSRR_BR6_Pos (22U)
+#define GPIO_BSRR_BR6_Msk (0x1U << GPIO_BSRR_BR6_Pos) /*!< 0x00400000 */
+#define GPIO_BSRR_BR6 GPIO_BSRR_BR6_Msk /*!< Port x Reset bit 6 */
+#define GPIO_BSRR_BR7_Pos (23U)
+#define GPIO_BSRR_BR7_Msk (0x1U << GPIO_BSRR_BR7_Pos) /*!< 0x00800000 */
+#define GPIO_BSRR_BR7 GPIO_BSRR_BR7_Msk /*!< Port x Reset bit 7 */
+#define GPIO_BSRR_BR8_Pos (24U)
+#define GPIO_BSRR_BR8_Msk (0x1U << GPIO_BSRR_BR8_Pos) /*!< 0x01000000 */
+#define GPIO_BSRR_BR8 GPIO_BSRR_BR8_Msk /*!< Port x Reset bit 8 */
+#define GPIO_BSRR_BR9_Pos (25U)
+#define GPIO_BSRR_BR9_Msk (0x1U << GPIO_BSRR_BR9_Pos) /*!< 0x02000000 */
+#define GPIO_BSRR_BR9 GPIO_BSRR_BR9_Msk /*!< Port x Reset bit 9 */
+#define GPIO_BSRR_BR10_Pos (26U)
+#define GPIO_BSRR_BR10_Msk (0x1U << GPIO_BSRR_BR10_Pos) /*!< 0x04000000 */
+#define GPIO_BSRR_BR10 GPIO_BSRR_BR10_Msk /*!< Port x Reset bit 10 */
+#define GPIO_BSRR_BR11_Pos (27U)
+#define GPIO_BSRR_BR11_Msk (0x1U << GPIO_BSRR_BR11_Pos) /*!< 0x08000000 */
+#define GPIO_BSRR_BR11 GPIO_BSRR_BR11_Msk /*!< Port x Reset bit 11 */
+#define GPIO_BSRR_BR12_Pos (28U)
+#define GPIO_BSRR_BR12_Msk (0x1U << GPIO_BSRR_BR12_Pos) /*!< 0x10000000 */
+#define GPIO_BSRR_BR12 GPIO_BSRR_BR12_Msk /*!< Port x Reset bit 12 */
+#define GPIO_BSRR_BR13_Pos (29U)
+#define GPIO_BSRR_BR13_Msk (0x1U << GPIO_BSRR_BR13_Pos) /*!< 0x20000000 */
+#define GPIO_BSRR_BR13 GPIO_BSRR_BR13_Msk /*!< Port x Reset bit 13 */
+#define GPIO_BSRR_BR14_Pos (30U)
+#define GPIO_BSRR_BR14_Msk (0x1U << GPIO_BSRR_BR14_Pos) /*!< 0x40000000 */
+#define GPIO_BSRR_BR14 GPIO_BSRR_BR14_Msk /*!< Port x Reset bit 14 */
+#define GPIO_BSRR_BR15_Pos (31U)
+#define GPIO_BSRR_BR15_Msk (0x1U << GPIO_BSRR_BR15_Pos) /*!< 0x80000000 */
+#define GPIO_BSRR_BR15 GPIO_BSRR_BR15_Msk /*!< Port x Reset bit 15 */
+
+/******************* Bit definition for GPIO_BRR register *******************/
+#define GPIO_BRR_BR0_Pos (0U)
+#define GPIO_BRR_BR0_Msk (0x1U << GPIO_BRR_BR0_Pos) /*!< 0x00000001 */
+#define GPIO_BRR_BR0 GPIO_BRR_BR0_Msk /*!< Port x Reset bit 0 */
+#define GPIO_BRR_BR1_Pos (1U)
+#define GPIO_BRR_BR1_Msk (0x1U << GPIO_BRR_BR1_Pos) /*!< 0x00000002 */
+#define GPIO_BRR_BR1 GPIO_BRR_BR1_Msk /*!< Port x Reset bit 1 */
+#define GPIO_BRR_BR2_Pos (2U)
+#define GPIO_BRR_BR2_Msk (0x1U << GPIO_BRR_BR2_Pos) /*!< 0x00000004 */
+#define GPIO_BRR_BR2 GPIO_BRR_BR2_Msk /*!< Port x Reset bit 2 */
+#define GPIO_BRR_BR3_Pos (3U)
+#define GPIO_BRR_BR3_Msk (0x1U << GPIO_BRR_BR3_Pos) /*!< 0x00000008 */
+#define GPIO_BRR_BR3 GPIO_BRR_BR3_Msk /*!< Port x Reset bit 3 */
+#define GPIO_BRR_BR4_Pos (4U)
+#define GPIO_BRR_BR4_Msk (0x1U << GPIO_BRR_BR4_Pos) /*!< 0x00000010 */
+#define GPIO_BRR_BR4 GPIO_BRR_BR4_Msk /*!< Port x Reset bit 4 */
+#define GPIO_BRR_BR5_Pos (5U)
+#define GPIO_BRR_BR5_Msk (0x1U << GPIO_BRR_BR5_Pos) /*!< 0x00000020 */
+#define GPIO_BRR_BR5 GPIO_BRR_BR5_Msk /*!< Port x Reset bit 5 */
+#define GPIO_BRR_BR6_Pos (6U)
+#define GPIO_BRR_BR6_Msk (0x1U << GPIO_BRR_BR6_Pos) /*!< 0x00000040 */
+#define GPIO_BRR_BR6 GPIO_BRR_BR6_Msk /*!< Port x Reset bit 6 */
+#define GPIO_BRR_BR7_Pos (7U)
+#define GPIO_BRR_BR7_Msk (0x1U << GPIO_BRR_BR7_Pos) /*!< 0x00000080 */
+#define GPIO_BRR_BR7 GPIO_BRR_BR7_Msk /*!< Port x Reset bit 7 */
+#define GPIO_BRR_BR8_Pos (8U)
+#define GPIO_BRR_BR8_Msk (0x1U << GPIO_BRR_BR8_Pos) /*!< 0x00000100 */
+#define GPIO_BRR_BR8 GPIO_BRR_BR8_Msk /*!< Port x Reset bit 8 */
+#define GPIO_BRR_BR9_Pos (9U)
+#define GPIO_BRR_BR9_Msk (0x1U << GPIO_BRR_BR9_Pos) /*!< 0x00000200 */
+#define GPIO_BRR_BR9 GPIO_BRR_BR9_Msk /*!< Port x Reset bit 9 */
+#define GPIO_BRR_BR10_Pos (10U)
+#define GPIO_BRR_BR10_Msk (0x1U << GPIO_BRR_BR10_Pos) /*!< 0x00000400 */
+#define GPIO_BRR_BR10 GPIO_BRR_BR10_Msk /*!< Port x Reset bit 10 */
+#define GPIO_BRR_BR11_Pos (11U)
+#define GPIO_BRR_BR11_Msk (0x1U << GPIO_BRR_BR11_Pos) /*!< 0x00000800 */
+#define GPIO_BRR_BR11 GPIO_BRR_BR11_Msk /*!< Port x Reset bit 11 */
+#define GPIO_BRR_BR12_Pos (12U)
+#define GPIO_BRR_BR12_Msk (0x1U << GPIO_BRR_BR12_Pos) /*!< 0x00001000 */
+#define GPIO_BRR_BR12 GPIO_BRR_BR12_Msk /*!< Port x Reset bit 12 */
+#define GPIO_BRR_BR13_Pos (13U)
+#define GPIO_BRR_BR13_Msk (0x1U << GPIO_BRR_BR13_Pos) /*!< 0x00002000 */
+#define GPIO_BRR_BR13 GPIO_BRR_BR13_Msk /*!< Port x Reset bit 13 */
+#define GPIO_BRR_BR14_Pos (14U)
+#define GPIO_BRR_BR14_Msk (0x1U << GPIO_BRR_BR14_Pos) /*!< 0x00004000 */
+#define GPIO_BRR_BR14 GPIO_BRR_BR14_Msk /*!< Port x Reset bit 14 */
+#define GPIO_BRR_BR15_Pos (15U)
+#define GPIO_BRR_BR15_Msk (0x1U << GPIO_BRR_BR15_Pos) /*!< 0x00008000 */
+#define GPIO_BRR_BR15 GPIO_BRR_BR15_Msk /*!< Port x Reset bit 15 */
+
+/****************** Bit definition for GPIO_LCKR register *******************/
+#define GPIO_LCKR_LCK0_Pos (0U)
+#define GPIO_LCKR_LCK0_Msk (0x1U << GPIO_LCKR_LCK0_Pos) /*!< 0x00000001 */
+#define GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk /*!< Port x Lock bit 0 */
+#define GPIO_LCKR_LCK1_Pos (1U)
+#define GPIO_LCKR_LCK1_Msk (0x1U << GPIO_LCKR_LCK1_Pos) /*!< 0x00000002 */
+#define GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk /*!< Port x Lock bit 1 */
+#define GPIO_LCKR_LCK2_Pos (2U)
+#define GPIO_LCKR_LCK2_Msk (0x1U << GPIO_LCKR_LCK2_Pos) /*!< 0x00000004 */
+#define GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk /*!< Port x Lock bit 2 */
+#define GPIO_LCKR_LCK3_Pos (3U)
+#define GPIO_LCKR_LCK3_Msk (0x1U << GPIO_LCKR_LCK3_Pos) /*!< 0x00000008 */
+#define GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk /*!< Port x Lock bit 3 */
+#define GPIO_LCKR_LCK4_Pos (4U)
+#define GPIO_LCKR_LCK4_Msk (0x1U << GPIO_LCKR_LCK4_Pos) /*!< 0x00000010 */
+#define GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk /*!< Port x Lock bit 4 */
+#define GPIO_LCKR_LCK5_Pos (5U)
+#define GPIO_LCKR_LCK5_Msk (0x1U << GPIO_LCKR_LCK5_Pos) /*!< 0x00000020 */
+#define GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk /*!< Port x Lock bit 5 */
+#define GPIO_LCKR_LCK6_Pos (6U)
+#define GPIO_LCKR_LCK6_Msk (0x1U << GPIO_LCKR_LCK6_Pos) /*!< 0x00000040 */
+#define GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk /*!< Port x Lock bit 6 */
+#define GPIO_LCKR_LCK7_Pos (7U)
+#define GPIO_LCKR_LCK7_Msk (0x1U << GPIO_LCKR_LCK7_Pos) /*!< 0x00000080 */
+#define GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk /*!< Port x Lock bit 7 */
+#define GPIO_LCKR_LCK8_Pos (8U)
+#define GPIO_LCKR_LCK8_Msk (0x1U << GPIO_LCKR_LCK8_Pos) /*!< 0x00000100 */
+#define GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk /*!< Port x Lock bit 8 */
+#define GPIO_LCKR_LCK9_Pos (9U)
+#define GPIO_LCKR_LCK9_Msk (0x1U << GPIO_LCKR_LCK9_Pos) /*!< 0x00000200 */
+#define GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk /*!< Port x Lock bit 9 */
+#define GPIO_LCKR_LCK10_Pos (10U)
+#define GPIO_LCKR_LCK10_Msk (0x1U << GPIO_LCKR_LCK10_Pos) /*!< 0x00000400 */
+#define GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk /*!< Port x Lock bit 10 */
+#define GPIO_LCKR_LCK11_Pos (11U)
+#define GPIO_LCKR_LCK11_Msk (0x1U << GPIO_LCKR_LCK11_Pos) /*!< 0x00000800 */
+#define GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk /*!< Port x Lock bit 11 */
+#define GPIO_LCKR_LCK12_Pos (12U)
+#define GPIO_LCKR_LCK12_Msk (0x1U << GPIO_LCKR_LCK12_Pos) /*!< 0x00001000 */
+#define GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk /*!< Port x Lock bit 12 */
+#define GPIO_LCKR_LCK13_Pos (13U)
+#define GPIO_LCKR_LCK13_Msk (0x1U << GPIO_LCKR_LCK13_Pos) /*!< 0x00002000 */
+#define GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk /*!< Port x Lock bit 13 */
+#define GPIO_LCKR_LCK14_Pos (14U)
+#define GPIO_LCKR_LCK14_Msk (0x1U << GPIO_LCKR_LCK14_Pos) /*!< 0x00004000 */
+#define GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk /*!< Port x Lock bit 14 */
+#define GPIO_LCKR_LCK15_Pos (15U)
+#define GPIO_LCKR_LCK15_Msk (0x1U << GPIO_LCKR_LCK15_Pos) /*!< 0x00008000 */
+#define GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk /*!< Port x Lock bit 15 */
+#define GPIO_LCKR_LCKK_Pos (16U)
+#define GPIO_LCKR_LCKK_Msk (0x1U << GPIO_LCKR_LCKK_Pos) /*!< 0x00010000 */
+#define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk /*!< Lock key */
+
+/*----------------------------------------------------------------------------*/
+
+/****************** Bit definition for AFIO_EVCR register *******************/
+#define AFIO_EVCR_PIN_Pos (0U)
+#define AFIO_EVCR_PIN_Msk (0xFU << AFIO_EVCR_PIN_Pos) /*!< 0x0000000F */
+#define AFIO_EVCR_PIN AFIO_EVCR_PIN_Msk /*!< PIN[3:0] bits (Pin selection) */
+#define AFIO_EVCR_PIN_0 (0x1U << AFIO_EVCR_PIN_Pos) /*!< 0x00000001 */
+#define AFIO_EVCR_PIN_1 (0x2U << AFIO_EVCR_PIN_Pos) /*!< 0x00000002 */
+#define AFIO_EVCR_PIN_2 (0x4U << AFIO_EVCR_PIN_Pos) /*!< 0x00000004 */
+#define AFIO_EVCR_PIN_3 (0x8U << AFIO_EVCR_PIN_Pos) /*!< 0x00000008 */
+
+/*!< PIN configuration */
+#define AFIO_EVCR_PIN_PX0 ((uint32_t)0x00000000) /*!< Pin 0 selected */
+#define AFIO_EVCR_PIN_PX1_Pos (0U)
+#define AFIO_EVCR_PIN_PX1_Msk (0x1U << AFIO_EVCR_PIN_PX1_Pos) /*!< 0x00000001 */
+#define AFIO_EVCR_PIN_PX1 AFIO_EVCR_PIN_PX1_Msk /*!< Pin 1 selected */
+#define AFIO_EVCR_PIN_PX2_Pos (1U)
+#define AFIO_EVCR_PIN_PX2_Msk (0x1U << AFIO_EVCR_PIN_PX2_Pos) /*!< 0x00000002 */
+#define AFIO_EVCR_PIN_PX2 AFIO_EVCR_PIN_PX2_Msk /*!< Pin 2 selected */
+#define AFIO_EVCR_PIN_PX3_Pos (0U)
+#define AFIO_EVCR_PIN_PX3_Msk (0x3U << AFIO_EVCR_PIN_PX3_Pos) /*!< 0x00000003 */
+#define AFIO_EVCR_PIN_PX3 AFIO_EVCR_PIN_PX3_Msk /*!< Pin 3 selected */
+#define AFIO_EVCR_PIN_PX4_Pos (2U)
+#define AFIO_EVCR_PIN_PX4_Msk (0x1U << AFIO_EVCR_PIN_PX4_Pos) /*!< 0x00000004 */
+#define AFIO_EVCR_PIN_PX4 AFIO_EVCR_PIN_PX4_Msk /*!< Pin 4 selected */
+#define AFIO_EVCR_PIN_PX5_Pos (0U)
+#define AFIO_EVCR_PIN_PX5_Msk (0x5U << AFIO_EVCR_PIN_PX5_Pos) /*!< 0x00000005 */
+#define AFIO_EVCR_PIN_PX5 AFIO_EVCR_PIN_PX5_Msk /*!< Pin 5 selected */
+#define AFIO_EVCR_PIN_PX6_Pos (1U)
+#define AFIO_EVCR_PIN_PX6_Msk (0x3U << AFIO_EVCR_PIN_PX6_Pos) /*!< 0x00000006 */
+#define AFIO_EVCR_PIN_PX6 AFIO_EVCR_PIN_PX6_Msk /*!< Pin 6 selected */
+#define AFIO_EVCR_PIN_PX7_Pos (0U)
+#define AFIO_EVCR_PIN_PX7_Msk (0x7U << AFIO_EVCR_PIN_PX7_Pos) /*!< 0x00000007 */
+#define AFIO_EVCR_PIN_PX7 AFIO_EVCR_PIN_PX7_Msk /*!< Pin 7 selected */
+#define AFIO_EVCR_PIN_PX8_Pos (3U)
+#define AFIO_EVCR_PIN_PX8_Msk (0x1U << AFIO_EVCR_PIN_PX8_Pos) /*!< 0x00000008 */
+#define AFIO_EVCR_PIN_PX8 AFIO_EVCR_PIN_PX8_Msk /*!< Pin 8 selected */
+#define AFIO_EVCR_PIN_PX9_Pos (0U)
+#define AFIO_EVCR_PIN_PX9_Msk (0x9U << AFIO_EVCR_PIN_PX9_Pos) /*!< 0x00000009 */
+#define AFIO_EVCR_PIN_PX9 AFIO_EVCR_PIN_PX9_Msk /*!< Pin 9 selected */
+#define AFIO_EVCR_PIN_PX10_Pos (1U)
+#define AFIO_EVCR_PIN_PX10_Msk (0x5U << AFIO_EVCR_PIN_PX10_Pos) /*!< 0x0000000A */
+#define AFIO_EVCR_PIN_PX10 AFIO_EVCR_PIN_PX10_Msk /*!< Pin 10 selected */
+#define AFIO_EVCR_PIN_PX11_Pos (0U)
+#define AFIO_EVCR_PIN_PX11_Msk (0xBU << AFIO_EVCR_PIN_PX11_Pos) /*!< 0x0000000B */
+#define AFIO_EVCR_PIN_PX11 AFIO_EVCR_PIN_PX11_Msk /*!< Pin 11 selected */
+#define AFIO_EVCR_PIN_PX12_Pos (2U)
+#define AFIO_EVCR_PIN_PX12_Msk (0x3U << AFIO_EVCR_PIN_PX12_Pos) /*!< 0x0000000C */
+#define AFIO_EVCR_PIN_PX12 AFIO_EVCR_PIN_PX12_Msk /*!< Pin 12 selected */
+#define AFIO_EVCR_PIN_PX13_Pos (0U)
+#define AFIO_EVCR_PIN_PX13_Msk (0xDU << AFIO_EVCR_PIN_PX13_Pos) /*!< 0x0000000D */
+#define AFIO_EVCR_PIN_PX13 AFIO_EVCR_PIN_PX13_Msk /*!< Pin 13 selected */
+#define AFIO_EVCR_PIN_PX14_Pos (1U)
+#define AFIO_EVCR_PIN_PX14_Msk (0x7U << AFIO_EVCR_PIN_PX14_Pos) /*!< 0x0000000E */
+#define AFIO_EVCR_PIN_PX14 AFIO_EVCR_PIN_PX14_Msk /*!< Pin 14 selected */
+#define AFIO_EVCR_PIN_PX15_Pos (0U)
+#define AFIO_EVCR_PIN_PX15_Msk (0xFU << AFIO_EVCR_PIN_PX15_Pos) /*!< 0x0000000F */
+#define AFIO_EVCR_PIN_PX15 AFIO_EVCR_PIN_PX15_Msk /*!< Pin 15 selected */
+
+#define AFIO_EVCR_PORT_Pos (4U)
+#define AFIO_EVCR_PORT_Msk (0x7U << AFIO_EVCR_PORT_Pos) /*!< 0x00000070 */
+#define AFIO_EVCR_PORT AFIO_EVCR_PORT_Msk /*!< PORT[2:0] bits (Port selection) */
+#define AFIO_EVCR_PORT_0 (0x1U << AFIO_EVCR_PORT_Pos) /*!< 0x00000010 */
+#define AFIO_EVCR_PORT_1 (0x2U << AFIO_EVCR_PORT_Pos) /*!< 0x00000020 */
+#define AFIO_EVCR_PORT_2 (0x4U << AFIO_EVCR_PORT_Pos) /*!< 0x00000040 */
+
+/*!< PORT configuration */
+#define AFIO_EVCR_PORT_PA ((uint32_t)0x00000000) /*!< Port A selected */
+#define AFIO_EVCR_PORT_PB_Pos (4U)
+#define AFIO_EVCR_PORT_PB_Msk (0x1U << AFIO_EVCR_PORT_PB_Pos) /*!< 0x00000010 */
+#define AFIO_EVCR_PORT_PB AFIO_EVCR_PORT_PB_Msk /*!< Port B selected */
+#define AFIO_EVCR_PORT_PC_Pos (5U)
+#define AFIO_EVCR_PORT_PC_Msk (0x1U << AFIO_EVCR_PORT_PC_Pos) /*!< 0x00000020 */
+#define AFIO_EVCR_PORT_PC AFIO_EVCR_PORT_PC_Msk /*!< Port C selected */
+#define AFIO_EVCR_PORT_PD_Pos (4U)
+#define AFIO_EVCR_PORT_PD_Msk (0x3U << AFIO_EVCR_PORT_PD_Pos) /*!< 0x00000030 */
+#define AFIO_EVCR_PORT_PD AFIO_EVCR_PORT_PD_Msk /*!< Port D selected */
+#define AFIO_EVCR_PORT_PE_Pos (6U)
+#define AFIO_EVCR_PORT_PE_Msk (0x1U << AFIO_EVCR_PORT_PE_Pos) /*!< 0x00000040 */
+#define AFIO_EVCR_PORT_PE AFIO_EVCR_PORT_PE_Msk /*!< Port E selected */
+
+#define AFIO_EVCR_EVOE_Pos (7U)
+#define AFIO_EVCR_EVOE_Msk (0x1U << AFIO_EVCR_EVOE_Pos) /*!< 0x00000080 */
+#define AFIO_EVCR_EVOE AFIO_EVCR_EVOE_Msk /*!< Event Output Enable */
+
+/****************** Bit definition for AFIO_MAPR register *******************/
+#define AFIO_MAPR_SPI1_REMAP_Pos (0U)
+#define AFIO_MAPR_SPI1_REMAP_Msk (0x1U << AFIO_MAPR_SPI1_REMAP_Pos) /*!< 0x00000001 */
+#define AFIO_MAPR_SPI1_REMAP AFIO_MAPR_SPI1_REMAP_Msk /*!< SPI1 remapping */
+#define AFIO_MAPR_I2C1_REMAP_Pos (1U)
+#define AFIO_MAPR_I2C1_REMAP_Msk (0x1U << AFIO_MAPR_I2C1_REMAP_Pos) /*!< 0x00000002 */
+#define AFIO_MAPR_I2C1_REMAP AFIO_MAPR_I2C1_REMAP_Msk /*!< I2C1 remapping */
+#define AFIO_MAPR_USART1_REMAP_Pos (2U)
+#define AFIO_MAPR_USART1_REMAP_Msk (0x1U << AFIO_MAPR_USART1_REMAP_Pos) /*!< 0x00000004 */
+#define AFIO_MAPR_USART1_REMAP AFIO_MAPR_USART1_REMAP_Msk /*!< USART1 remapping */
+#define AFIO_MAPR_USART2_REMAP_Pos (3U)
+#define AFIO_MAPR_USART2_REMAP_Msk (0x1U << AFIO_MAPR_USART2_REMAP_Pos) /*!< 0x00000008 */
+#define AFIO_MAPR_USART2_REMAP AFIO_MAPR_USART2_REMAP_Msk /*!< USART2 remapping */
+
+
+#define AFIO_MAPR_TIM1_REMAP_Pos (6U)
+#define AFIO_MAPR_TIM1_REMAP_Msk (0x3U << AFIO_MAPR_TIM1_REMAP_Pos) /*!< 0x000000C0 */
+#define AFIO_MAPR_TIM1_REMAP AFIO_MAPR_TIM1_REMAP_Msk /*!< TIM1_REMAP[1:0] bits (TIM1 remapping) */
+#define AFIO_MAPR_TIM1_REMAP_0 (0x1U << AFIO_MAPR_TIM1_REMAP_Pos) /*!< 0x00000040 */
+#define AFIO_MAPR_TIM1_REMAP_1 (0x2U << AFIO_MAPR_TIM1_REMAP_Pos) /*!< 0x00000080 */
+
+/*!< TIM1_REMAP configuration */
+#define AFIO_MAPR_TIM1_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15) */
+#define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Pos (6U)
+#define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Msk (0x1U << AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Pos) /*!< 0x00000040 */
+#define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Msk /*!< Partial remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PA6, CH1N/PA7, CH2N/PB0, CH3N/PB1) */
+#define AFIO_MAPR_TIM1_REMAP_FULLREMAP_Pos (6U)
+#define AFIO_MAPR_TIM1_REMAP_FULLREMAP_Msk (0x3U << AFIO_MAPR_TIM1_REMAP_FULLREMAP_Pos) /*!< 0x000000C0 */
+#define AFIO_MAPR_TIM1_REMAP_FULLREMAP AFIO_MAPR_TIM1_REMAP_FULLREMAP_Msk /*!< Full remap (ETR/PE7, CH1/PE9, CH2/PE11, CH3/PE13, CH4/PE14, BKIN/PE15, CH1N/PE8, CH2N/PE10, CH3N/PE12) */
+
+#define AFIO_MAPR_TIM2_REMAP_Pos (8U)
+#define AFIO_MAPR_TIM2_REMAP_Msk (0x3U << AFIO_MAPR_TIM2_REMAP_Pos) /*!< 0x00000300 */
+#define AFIO_MAPR_TIM2_REMAP AFIO_MAPR_TIM2_REMAP_Msk /*!< TIM2_REMAP[1:0] bits (TIM2 remapping) */
+#define AFIO_MAPR_TIM2_REMAP_0 (0x1U << AFIO_MAPR_TIM2_REMAP_Pos) /*!< 0x00000100 */
+#define AFIO_MAPR_TIM2_REMAP_1 (0x2U << AFIO_MAPR_TIM2_REMAP_Pos) /*!< 0x00000200 */
+
+/*!< TIM2_REMAP configuration */
+#define AFIO_MAPR_TIM2_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3) */
+#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Pos (8U)
+#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Msk (0x1U << AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Pos) /*!< 0x00000100 */
+#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1 AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Msk /*!< Partial remap (CH1/ETR/PA15, CH2/PB3, CH3/PA2, CH4/PA3) */
+#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2_Pos (9U)
+#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2_Msk (0x1U << AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2_Pos) /*!< 0x00000200 */
+#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2 AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2_Msk /*!< Partial remap (CH1/ETR/PA0, CH2/PA1, CH3/PB10, CH4/PB11) */
+#define AFIO_MAPR_TIM2_REMAP_FULLREMAP_Pos (8U)
+#define AFIO_MAPR_TIM2_REMAP_FULLREMAP_Msk (0x3U << AFIO_MAPR_TIM2_REMAP_FULLREMAP_Pos) /*!< 0x00000300 */
+#define AFIO_MAPR_TIM2_REMAP_FULLREMAP AFIO_MAPR_TIM2_REMAP_FULLREMAP_Msk /*!< Full remap (CH1/ETR/PA15, CH2/PB3, CH3/PB10, CH4/PB11) */
+
+#define AFIO_MAPR_TIM3_REMAP_Pos (10U)
+#define AFIO_MAPR_TIM3_REMAP_Msk (0x3U << AFIO_MAPR_TIM3_REMAP_Pos) /*!< 0x00000C00 */
+#define AFIO_MAPR_TIM3_REMAP AFIO_MAPR_TIM3_REMAP_Msk /*!< TIM3_REMAP[1:0] bits (TIM3 remapping) */
+#define AFIO_MAPR_TIM3_REMAP_0 (0x1U << AFIO_MAPR_TIM3_REMAP_Pos) /*!< 0x00000400 */
+#define AFIO_MAPR_TIM3_REMAP_1 (0x2U << AFIO_MAPR_TIM3_REMAP_Pos) /*!< 0x00000800 */
+
+/*!< TIM3_REMAP configuration */
+#define AFIO_MAPR_TIM3_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1) */
+#define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Pos (11U)
+#define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Msk (0x1U << AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Pos) /*!< 0x00000800 */
+#define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Msk /*!< Partial remap (CH1/PB4, CH2/PB5, CH3/PB0, CH4/PB1) */
+#define AFIO_MAPR_TIM3_REMAP_FULLREMAP_Pos (10U)
+#define AFIO_MAPR_TIM3_REMAP_FULLREMAP_Msk (0x3U << AFIO_MAPR_TIM3_REMAP_FULLREMAP_Pos) /*!< 0x00000C00 */
+#define AFIO_MAPR_TIM3_REMAP_FULLREMAP AFIO_MAPR_TIM3_REMAP_FULLREMAP_Msk /*!< Full remap (CH1/PC6, CH2/PC7, CH3/PC8, CH4/PC9) */
+
+
+#define AFIO_MAPR_CAN_REMAP_Pos (13U)
+#define AFIO_MAPR_CAN_REMAP_Msk (0x3U << AFIO_MAPR_CAN_REMAP_Pos) /*!< 0x00006000 */
+#define AFIO_MAPR_CAN_REMAP AFIO_MAPR_CAN_REMAP_Msk /*!< CAN_REMAP[1:0] bits (CAN Alternate function remapping) */
+#define AFIO_MAPR_CAN_REMAP_0 (0x1U << AFIO_MAPR_CAN_REMAP_Pos) /*!< 0x00002000 */
+#define AFIO_MAPR_CAN_REMAP_1 (0x2U << AFIO_MAPR_CAN_REMAP_Pos) /*!< 0x00004000 */
+
+/*!< CAN_REMAP configuration */
+#define AFIO_MAPR_CAN_REMAP_REMAP1 ((uint32_t)0x00000000) /*!< CANRX mapped to PA11, CANTX mapped to PA12 */
+#define AFIO_MAPR_CAN_REMAP_REMAP2_Pos (14U)
+#define AFIO_MAPR_CAN_REMAP_REMAP2_Msk (0x1U << AFIO_MAPR_CAN_REMAP_REMAP2_Pos) /*!< 0x00004000 */
+#define AFIO_MAPR_CAN_REMAP_REMAP2 AFIO_MAPR_CAN_REMAP_REMAP2_Msk /*!< CANRX mapped to PB8, CANTX mapped to PB9 */
+#define AFIO_MAPR_CAN_REMAP_REMAP3_Pos (13U)
+#define AFIO_MAPR_CAN_REMAP_REMAP3_Msk (0x3U << AFIO_MAPR_CAN_REMAP_REMAP3_Pos) /*!< 0x00006000 */
+#define AFIO_MAPR_CAN_REMAP_REMAP3 AFIO_MAPR_CAN_REMAP_REMAP3_Msk /*!< CANRX mapped to PD0, CANTX mapped to PD1 */
+
+#define AFIO_MAPR_PD01_REMAP_Pos (15U)
+#define AFIO_MAPR_PD01_REMAP_Msk (0x1U << AFIO_MAPR_PD01_REMAP_Pos) /*!< 0x00008000 */
+#define AFIO_MAPR_PD01_REMAP AFIO_MAPR_PD01_REMAP_Msk /*!< Port D0/Port D1 mapping on OSC_IN/OSC_OUT */
+
+/*!< SWJ_CFG configuration */
+#define AFIO_MAPR_SWJ_CFG_Pos (24U)
+#define AFIO_MAPR_SWJ_CFG_Msk (0x7U << AFIO_MAPR_SWJ_CFG_Pos) /*!< 0x07000000 */
+#define AFIO_MAPR_SWJ_CFG AFIO_MAPR_SWJ_CFG_Msk /*!< SWJ_CFG[2:0] bits (Serial Wire JTAG configuration) */
+#define AFIO_MAPR_SWJ_CFG_0 (0x1U << AFIO_MAPR_SWJ_CFG_Pos) /*!< 0x01000000 */
+#define AFIO_MAPR_SWJ_CFG_1 (0x2U << AFIO_MAPR_SWJ_CFG_Pos) /*!< 0x02000000 */
+#define AFIO_MAPR_SWJ_CFG_2 (0x4U << AFIO_MAPR_SWJ_CFG_Pos) /*!< 0x04000000 */
+
+#define AFIO_MAPR_SWJ_CFG_RESET ((uint32_t)0x00000000) /*!< Full SWJ (JTAG-DP + SW-DP) : Reset State */
+#define AFIO_MAPR_SWJ_CFG_NOJNTRST_Pos (24U)
+#define AFIO_MAPR_SWJ_CFG_NOJNTRST_Msk (0x1U << AFIO_MAPR_SWJ_CFG_NOJNTRST_Pos) /*!< 0x01000000 */
+#define AFIO_MAPR_SWJ_CFG_NOJNTRST AFIO_MAPR_SWJ_CFG_NOJNTRST_Msk /*!< Full SWJ (JTAG-DP + SW-DP) but without JNTRST */
+#define AFIO_MAPR_SWJ_CFG_JTAGDISABLE_Pos (25U)
+#define AFIO_MAPR_SWJ_CFG_JTAGDISABLE_Msk (0x1U << AFIO_MAPR_SWJ_CFG_JTAGDISABLE_Pos) /*!< 0x02000000 */
+#define AFIO_MAPR_SWJ_CFG_JTAGDISABLE AFIO_MAPR_SWJ_CFG_JTAGDISABLE_Msk /*!< JTAG-DP Disabled and SW-DP Enabled */
+#define AFIO_MAPR_SWJ_CFG_DISABLE_Pos (26U)
+#define AFIO_MAPR_SWJ_CFG_DISABLE_Msk (0x1U << AFIO_MAPR_SWJ_CFG_DISABLE_Pos) /*!< 0x04000000 */
+#define AFIO_MAPR_SWJ_CFG_DISABLE AFIO_MAPR_SWJ_CFG_DISABLE_Msk /*!< JTAG-DP Disabled and SW-DP Disabled */
+
+
+/***************** Bit definition for AFIO_EXTICR1 register *****************/
+#define AFIO_EXTICR1_EXTI0_Pos (0U)
+#define AFIO_EXTICR1_EXTI0_Msk (0xFU << AFIO_EXTICR1_EXTI0_Pos) /*!< 0x0000000F */
+#define AFIO_EXTICR1_EXTI0 AFIO_EXTICR1_EXTI0_Msk /*!< EXTI 0 configuration */
+#define AFIO_EXTICR1_EXTI1_Pos (4U)
+#define AFIO_EXTICR1_EXTI1_Msk (0xFU << AFIO_EXTICR1_EXTI1_Pos) /*!< 0x000000F0 */
+#define AFIO_EXTICR1_EXTI1 AFIO_EXTICR1_EXTI1_Msk /*!< EXTI 1 configuration */
+#define AFIO_EXTICR1_EXTI2_Pos (8U)
+#define AFIO_EXTICR1_EXTI2_Msk (0xFU << AFIO_EXTICR1_EXTI2_Pos) /*!< 0x00000F00 */
+#define AFIO_EXTICR1_EXTI2 AFIO_EXTICR1_EXTI2_Msk /*!< EXTI 2 configuration */
+#define AFIO_EXTICR1_EXTI3_Pos (12U)
+#define AFIO_EXTICR1_EXTI3_Msk (0xFU << AFIO_EXTICR1_EXTI3_Pos) /*!< 0x0000F000 */
+#define AFIO_EXTICR1_EXTI3 AFIO_EXTICR1_EXTI3_Msk /*!< EXTI 3 configuration */
+
+/*!< EXTI0 configuration */
+#define AFIO_EXTICR1_EXTI0_PA ((uint32_t)0x00000000) /*!< PA[0] pin */
+#define AFIO_EXTICR1_EXTI0_PB_Pos (0U)
+#define AFIO_EXTICR1_EXTI0_PB_Msk (0x1U << AFIO_EXTICR1_EXTI0_PB_Pos) /*!< 0x00000001 */
+#define AFIO_EXTICR1_EXTI0_PB AFIO_EXTICR1_EXTI0_PB_Msk /*!< PB[0] pin */
+#define AFIO_EXTICR1_EXTI0_PC_Pos (1U)
+#define AFIO_EXTICR1_EXTI0_PC_Msk (0x1U << AFIO_EXTICR1_EXTI0_PC_Pos) /*!< 0x00000002 */
+#define AFIO_EXTICR1_EXTI0_PC AFIO_EXTICR1_EXTI0_PC_Msk /*!< PC[0] pin */
+#define AFIO_EXTICR1_EXTI0_PD_Pos (0U)
+#define AFIO_EXTICR1_EXTI0_PD_Msk (0x3U << AFIO_EXTICR1_EXTI0_PD_Pos) /*!< 0x00000003 */
+#define AFIO_EXTICR1_EXTI0_PD AFIO_EXTICR1_EXTI0_PD_Msk /*!< PD[0] pin */
+#define AFIO_EXTICR1_EXTI0_PE_Pos (2U)
+#define AFIO_EXTICR1_EXTI0_PE_Msk (0x1U << AFIO_EXTICR1_EXTI0_PE_Pos) /*!< 0x00000004 */
+#define AFIO_EXTICR1_EXTI0_PE AFIO_EXTICR1_EXTI0_PE_Msk /*!< PE[0] pin */
+#define AFIO_EXTICR1_EXTI0_PF_Pos (0U)
+#define AFIO_EXTICR1_EXTI0_PF_Msk (0x5U << AFIO_EXTICR1_EXTI0_PF_Pos) /*!< 0x00000005 */
+#define AFIO_EXTICR1_EXTI0_PF AFIO_EXTICR1_EXTI0_PF_Msk /*!< PF[0] pin */
+#define AFIO_EXTICR1_EXTI0_PG_Pos (1U)
+#define AFIO_EXTICR1_EXTI0_PG_Msk (0x3U << AFIO_EXTICR1_EXTI0_PG_Pos) /*!< 0x00000006 */
+#define AFIO_EXTICR1_EXTI0_PG AFIO_EXTICR1_EXTI0_PG_Msk /*!< PG[0] pin */
+
+/*!< EXTI1 configuration */
+#define AFIO_EXTICR1_EXTI1_PA ((uint32_t)0x00000000) /*!< PA[1] pin */
+#define AFIO_EXTICR1_EXTI1_PB_Pos (4U)
+#define AFIO_EXTICR1_EXTI1_PB_Msk (0x1U << AFIO_EXTICR1_EXTI1_PB_Pos) /*!< 0x00000010 */
+#define AFIO_EXTICR1_EXTI1_PB AFIO_EXTICR1_EXTI1_PB_Msk /*!< PB[1] pin */
+#define AFIO_EXTICR1_EXTI1_PC_Pos (5U)
+#define AFIO_EXTICR1_EXTI1_PC_Msk (0x1U << AFIO_EXTICR1_EXTI1_PC_Pos) /*!< 0x00000020 */
+#define AFIO_EXTICR1_EXTI1_PC AFIO_EXTICR1_EXTI1_PC_Msk /*!< PC[1] pin */
+#define AFIO_EXTICR1_EXTI1_PD_Pos (4U)
+#define AFIO_EXTICR1_EXTI1_PD_Msk (0x3U << AFIO_EXTICR1_EXTI1_PD_Pos) /*!< 0x00000030 */
+#define AFIO_EXTICR1_EXTI1_PD AFIO_EXTICR1_EXTI1_PD_Msk /*!< PD[1] pin */
+#define AFIO_EXTICR1_EXTI1_PE_Pos (6U)
+#define AFIO_EXTICR1_EXTI1_PE_Msk (0x1U << AFIO_EXTICR1_EXTI1_PE_Pos) /*!< 0x00000040 */
+#define AFIO_EXTICR1_EXTI1_PE AFIO_EXTICR1_EXTI1_PE_Msk /*!< PE[1] pin */
+#define AFIO_EXTICR1_EXTI1_PF_Pos (4U)
+#define AFIO_EXTICR1_EXTI1_PF_Msk (0x5U << AFIO_EXTICR1_EXTI1_PF_Pos) /*!< 0x00000050 */
+#define AFIO_EXTICR1_EXTI1_PF AFIO_EXTICR1_EXTI1_PF_Msk /*!< PF[1] pin */
+#define AFIO_EXTICR1_EXTI1_PG_Pos (5U)
+#define AFIO_EXTICR1_EXTI1_PG_Msk (0x3U << AFIO_EXTICR1_EXTI1_PG_Pos) /*!< 0x00000060 */
+#define AFIO_EXTICR1_EXTI1_PG AFIO_EXTICR1_EXTI1_PG_Msk /*!< PG[1] pin */
+
+/*!< EXTI2 configuration */
+#define AFIO_EXTICR1_EXTI2_PA ((uint32_t)0x00000000) /*!< PA[2] pin */
+#define AFIO_EXTICR1_EXTI2_PB_Pos (8U)
+#define AFIO_EXTICR1_EXTI2_PB_Msk (0x1U << AFIO_EXTICR1_EXTI2_PB_Pos) /*!< 0x00000100 */
+#define AFIO_EXTICR1_EXTI2_PB AFIO_EXTICR1_EXTI2_PB_Msk /*!< PB[2] pin */
+#define AFIO_EXTICR1_EXTI2_PC_Pos (9U)
+#define AFIO_EXTICR1_EXTI2_PC_Msk (0x1U << AFIO_EXTICR1_EXTI2_PC_Pos) /*!< 0x00000200 */
+#define AFIO_EXTICR1_EXTI2_PC AFIO_EXTICR1_EXTI2_PC_Msk /*!< PC[2] pin */
+#define AFIO_EXTICR1_EXTI2_PD_Pos (8U)
+#define AFIO_EXTICR1_EXTI2_PD_Msk (0x3U << AFIO_EXTICR1_EXTI2_PD_Pos) /*!< 0x00000300 */
+#define AFIO_EXTICR1_EXTI2_PD AFIO_EXTICR1_EXTI2_PD_Msk /*!< PD[2] pin */
+#define AFIO_EXTICR1_EXTI2_PE_Pos (10U)
+#define AFIO_EXTICR1_EXTI2_PE_Msk (0x1U << AFIO_EXTICR1_EXTI2_PE_Pos) /*!< 0x00000400 */
+#define AFIO_EXTICR1_EXTI2_PE AFIO_EXTICR1_EXTI2_PE_Msk /*!< PE[2] pin */
+#define AFIO_EXTICR1_EXTI2_PF_Pos (8U)
+#define AFIO_EXTICR1_EXTI2_PF_Msk (0x5U << AFIO_EXTICR1_EXTI2_PF_Pos) /*!< 0x00000500 */
+#define AFIO_EXTICR1_EXTI2_PF AFIO_EXTICR1_EXTI2_PF_Msk /*!< PF[2] pin */
+#define AFIO_EXTICR1_EXTI2_PG_Pos (9U)
+#define AFIO_EXTICR1_EXTI2_PG_Msk (0x3U << AFIO_EXTICR1_EXTI2_PG_Pos) /*!< 0x00000600 */
+#define AFIO_EXTICR1_EXTI2_PG AFIO_EXTICR1_EXTI2_PG_Msk /*!< PG[2] pin */
+
+/*!< EXTI3 configuration */
+#define AFIO_EXTICR1_EXTI3_PA ((uint32_t)0x00000000) /*!< PA[3] pin */
+#define AFIO_EXTICR1_EXTI3_PB_Pos (12U)
+#define AFIO_EXTICR1_EXTI3_PB_Msk (0x1U << AFIO_EXTICR1_EXTI3_PB_Pos) /*!< 0x00001000 */
+#define AFIO_EXTICR1_EXTI3_PB AFIO_EXTICR1_EXTI3_PB_Msk /*!< PB[3] pin */
+#define AFIO_EXTICR1_EXTI3_PC_Pos (13U)
+#define AFIO_EXTICR1_EXTI3_PC_Msk (0x1U << AFIO_EXTICR1_EXTI3_PC_Pos) /*!< 0x00002000 */
+#define AFIO_EXTICR1_EXTI3_PC AFIO_EXTICR1_EXTI3_PC_Msk /*!< PC[3] pin */
+#define AFIO_EXTICR1_EXTI3_PD_Pos (12U)
+#define AFIO_EXTICR1_EXTI3_PD_Msk (0x3U << AFIO_EXTICR1_EXTI3_PD_Pos) /*!< 0x00003000 */
+#define AFIO_EXTICR1_EXTI3_PD AFIO_EXTICR1_EXTI3_PD_Msk /*!< PD[3] pin */
+#define AFIO_EXTICR1_EXTI3_PE_Pos (14U)
+#define AFIO_EXTICR1_EXTI3_PE_Msk (0x1U << AFIO_EXTICR1_EXTI3_PE_Pos) /*!< 0x00004000 */
+#define AFIO_EXTICR1_EXTI3_PE AFIO_EXTICR1_EXTI3_PE_Msk /*!< PE[3] pin */
+#define AFIO_EXTICR1_EXTI3_PF_Pos (12U)
+#define AFIO_EXTICR1_EXTI3_PF_Msk (0x5U << AFIO_EXTICR1_EXTI3_PF_Pos) /*!< 0x00005000 */
+#define AFIO_EXTICR1_EXTI3_PF AFIO_EXTICR1_EXTI3_PF_Msk /*!< PF[3] pin */
+#define AFIO_EXTICR1_EXTI3_PG_Pos (13U)
+#define AFIO_EXTICR1_EXTI3_PG_Msk (0x3U << AFIO_EXTICR1_EXTI3_PG_Pos) /*!< 0x00006000 */
+#define AFIO_EXTICR1_EXTI3_PG AFIO_EXTICR1_EXTI3_PG_Msk /*!< PG[3] pin */
+
+/***************** Bit definition for AFIO_EXTICR2 register *****************/
+#define AFIO_EXTICR2_EXTI4_Pos (0U)
+#define AFIO_EXTICR2_EXTI4_Msk (0xFU << AFIO_EXTICR2_EXTI4_Pos) /*!< 0x0000000F */
+#define AFIO_EXTICR2_EXTI4 AFIO_EXTICR2_EXTI4_Msk /*!< EXTI 4 configuration */
+#define AFIO_EXTICR2_EXTI5_Pos (4U)
+#define AFIO_EXTICR2_EXTI5_Msk (0xFU << AFIO_EXTICR2_EXTI5_Pos) /*!< 0x000000F0 */
+#define AFIO_EXTICR2_EXTI5 AFIO_EXTICR2_EXTI5_Msk /*!< EXTI 5 configuration */
+#define AFIO_EXTICR2_EXTI6_Pos (8U)
+#define AFIO_EXTICR2_EXTI6_Msk (0xFU << AFIO_EXTICR2_EXTI6_Pos) /*!< 0x00000F00 */
+#define AFIO_EXTICR2_EXTI6 AFIO_EXTICR2_EXTI6_Msk /*!< EXTI 6 configuration */
+#define AFIO_EXTICR2_EXTI7_Pos (12U)
+#define AFIO_EXTICR2_EXTI7_Msk (0xFU << AFIO_EXTICR2_EXTI7_Pos) /*!< 0x0000F000 */
+#define AFIO_EXTICR2_EXTI7 AFIO_EXTICR2_EXTI7_Msk /*!< EXTI 7 configuration */
+
+/*!< EXTI4 configuration */
+#define AFIO_EXTICR2_EXTI4_PA ((uint32_t)0x00000000) /*!< PA[4] pin */
+#define AFIO_EXTICR2_EXTI4_PB_Pos (0U)
+#define AFIO_EXTICR2_EXTI4_PB_Msk (0x1U << AFIO_EXTICR2_EXTI4_PB_Pos) /*!< 0x00000001 */
+#define AFIO_EXTICR2_EXTI4_PB AFIO_EXTICR2_EXTI4_PB_Msk /*!< PB[4] pin */
+#define AFIO_EXTICR2_EXTI4_PC_Pos (1U)
+#define AFIO_EXTICR2_EXTI4_PC_Msk (0x1U << AFIO_EXTICR2_EXTI4_PC_Pos) /*!< 0x00000002 */
+#define AFIO_EXTICR2_EXTI4_PC AFIO_EXTICR2_EXTI4_PC_Msk /*!< PC[4] pin */
+#define AFIO_EXTICR2_EXTI4_PD_Pos (0U)
+#define AFIO_EXTICR2_EXTI4_PD_Msk (0x3U << AFIO_EXTICR2_EXTI4_PD_Pos) /*!< 0x00000003 */
+#define AFIO_EXTICR2_EXTI4_PD AFIO_EXTICR2_EXTI4_PD_Msk /*!< PD[4] pin */
+#define AFIO_EXTICR2_EXTI4_PE_Pos (2U)
+#define AFIO_EXTICR2_EXTI4_PE_Msk (0x1U << AFIO_EXTICR2_EXTI4_PE_Pos) /*!< 0x00000004 */
+#define AFIO_EXTICR2_EXTI4_PE AFIO_EXTICR2_EXTI4_PE_Msk /*!< PE[4] pin */
+#define AFIO_EXTICR2_EXTI4_PF_Pos (0U)
+#define AFIO_EXTICR2_EXTI4_PF_Msk (0x5U << AFIO_EXTICR2_EXTI4_PF_Pos) /*!< 0x00000005 */
+#define AFIO_EXTICR2_EXTI4_PF AFIO_EXTICR2_EXTI4_PF_Msk /*!< PF[4] pin */
+#define AFIO_EXTICR2_EXTI4_PG_Pos (1U)
+#define AFIO_EXTICR2_EXTI4_PG_Msk (0x3U << AFIO_EXTICR2_EXTI4_PG_Pos) /*!< 0x00000006 */
+#define AFIO_EXTICR2_EXTI4_PG AFIO_EXTICR2_EXTI4_PG_Msk /*!< PG[4] pin */
+
+/* EXTI5 configuration */
+#define AFIO_EXTICR2_EXTI5_PA ((uint32_t)0x00000000) /*!< PA[5] pin */
+#define AFIO_EXTICR2_EXTI5_PB_Pos (4U)
+#define AFIO_EXTICR2_EXTI5_PB_Msk (0x1U << AFIO_EXTICR2_EXTI5_PB_Pos) /*!< 0x00000010 */
+#define AFIO_EXTICR2_EXTI5_PB AFIO_EXTICR2_EXTI5_PB_Msk /*!< PB[5] pin */
+#define AFIO_EXTICR2_EXTI5_PC_Pos (5U)
+#define AFIO_EXTICR2_EXTI5_PC_Msk (0x1U << AFIO_EXTICR2_EXTI5_PC_Pos) /*!< 0x00000020 */
+#define AFIO_EXTICR2_EXTI5_PC AFIO_EXTICR2_EXTI5_PC_Msk /*!< PC[5] pin */
+#define AFIO_EXTICR2_EXTI5_PD_Pos (4U)
+#define AFIO_EXTICR2_EXTI5_PD_Msk (0x3U << AFIO_EXTICR2_EXTI5_PD_Pos) /*!< 0x00000030 */
+#define AFIO_EXTICR2_EXTI5_PD AFIO_EXTICR2_EXTI5_PD_Msk /*!< PD[5] pin */
+#define AFIO_EXTICR2_EXTI5_PE_Pos (6U)
+#define AFIO_EXTICR2_EXTI5_PE_Msk (0x1U << AFIO_EXTICR2_EXTI5_PE_Pos) /*!< 0x00000040 */
+#define AFIO_EXTICR2_EXTI5_PE AFIO_EXTICR2_EXTI5_PE_Msk /*!< PE[5] pin */
+#define AFIO_EXTICR2_EXTI5_PF_Pos (4U)
+#define AFIO_EXTICR2_EXTI5_PF_Msk (0x5U << AFIO_EXTICR2_EXTI5_PF_Pos) /*!< 0x00000050 */
+#define AFIO_EXTICR2_EXTI5_PF AFIO_EXTICR2_EXTI5_PF_Msk /*!< PF[5] pin */
+#define AFIO_EXTICR2_EXTI5_PG_Pos (5U)
+#define AFIO_EXTICR2_EXTI5_PG_Msk (0x3U << AFIO_EXTICR2_EXTI5_PG_Pos) /*!< 0x00000060 */
+#define AFIO_EXTICR2_EXTI5_PG AFIO_EXTICR2_EXTI5_PG_Msk /*!< PG[5] pin */
+
+/*!< EXTI6 configuration */
+#define AFIO_EXTICR2_EXTI6_PA ((uint32_t)0x00000000) /*!< PA[6] pin */
+#define AFIO_EXTICR2_EXTI6_PB_Pos (8U)
+#define AFIO_EXTICR2_EXTI6_PB_Msk (0x1U << AFIO_EXTICR2_EXTI6_PB_Pos) /*!< 0x00000100 */
+#define AFIO_EXTICR2_EXTI6_PB AFIO_EXTICR2_EXTI6_PB_Msk /*!< PB[6] pin */
+#define AFIO_EXTICR2_EXTI6_PC_Pos (9U)
+#define AFIO_EXTICR2_EXTI6_PC_Msk (0x1U << AFIO_EXTICR2_EXTI6_PC_Pos) /*!< 0x00000200 */
+#define AFIO_EXTICR2_EXTI6_PC AFIO_EXTICR2_EXTI6_PC_Msk /*!< PC[6] pin */
+#define AFIO_EXTICR2_EXTI6_PD_Pos (8U)
+#define AFIO_EXTICR2_EXTI6_PD_Msk (0x3U << AFIO_EXTICR2_EXTI6_PD_Pos) /*!< 0x00000300 */
+#define AFIO_EXTICR2_EXTI6_PD AFIO_EXTICR2_EXTI6_PD_Msk /*!< PD[6] pin */
+#define AFIO_EXTICR2_EXTI6_PE_Pos (10U)
+#define AFIO_EXTICR2_EXTI6_PE_Msk (0x1U << AFIO_EXTICR2_EXTI6_PE_Pos) /*!< 0x00000400 */
+#define AFIO_EXTICR2_EXTI6_PE AFIO_EXTICR2_EXTI6_PE_Msk /*!< PE[6] pin */
+#define AFIO_EXTICR2_EXTI6_PF_Pos (8U)
+#define AFIO_EXTICR2_EXTI6_PF_Msk (0x5U << AFIO_EXTICR2_EXTI6_PF_Pos) /*!< 0x00000500 */
+#define AFIO_EXTICR2_EXTI6_PF AFIO_EXTICR2_EXTI6_PF_Msk /*!< PF[6] pin */
+#define AFIO_EXTICR2_EXTI6_PG_Pos (9U)
+#define AFIO_EXTICR2_EXTI6_PG_Msk (0x3U << AFIO_EXTICR2_EXTI6_PG_Pos) /*!< 0x00000600 */
+#define AFIO_EXTICR2_EXTI6_PG AFIO_EXTICR2_EXTI6_PG_Msk /*!< PG[6] pin */
+
+/*!< EXTI7 configuration */
+#define AFIO_EXTICR2_EXTI7_PA ((uint32_t)0x00000000) /*!< PA[7] pin */
+#define AFIO_EXTICR2_EXTI7_PB_Pos (12U)
+#define AFIO_EXTICR2_EXTI7_PB_Msk (0x1U << AFIO_EXTICR2_EXTI7_PB_Pos) /*!< 0x00001000 */
+#define AFIO_EXTICR2_EXTI7_PB AFIO_EXTICR2_EXTI7_PB_Msk /*!< PB[7] pin */
+#define AFIO_EXTICR2_EXTI7_PC_Pos (13U)
+#define AFIO_EXTICR2_EXTI7_PC_Msk (0x1U << AFIO_EXTICR2_EXTI7_PC_Pos) /*!< 0x00002000 */
+#define AFIO_EXTICR2_EXTI7_PC AFIO_EXTICR2_EXTI7_PC_Msk /*!< PC[7] pin */
+#define AFIO_EXTICR2_EXTI7_PD_Pos (12U)
+#define AFIO_EXTICR2_EXTI7_PD_Msk (0x3U << AFIO_EXTICR2_EXTI7_PD_Pos) /*!< 0x00003000 */
+#define AFIO_EXTICR2_EXTI7_PD AFIO_EXTICR2_EXTI7_PD_Msk /*!< PD[7] pin */
+#define AFIO_EXTICR2_EXTI7_PE_Pos (14U)
+#define AFIO_EXTICR2_EXTI7_PE_Msk (0x1U << AFIO_EXTICR2_EXTI7_PE_Pos) /*!< 0x00004000 */
+#define AFIO_EXTICR2_EXTI7_PE AFIO_EXTICR2_EXTI7_PE_Msk /*!< PE[7] pin */
+#define AFIO_EXTICR2_EXTI7_PF_Pos (12U)
+#define AFIO_EXTICR2_EXTI7_PF_Msk (0x5U << AFIO_EXTICR2_EXTI7_PF_Pos) /*!< 0x00005000 */
+#define AFIO_EXTICR2_EXTI7_PF AFIO_EXTICR2_EXTI7_PF_Msk /*!< PF[7] pin */
+#define AFIO_EXTICR2_EXTI7_PG_Pos (13U)
+#define AFIO_EXTICR2_EXTI7_PG_Msk (0x3U << AFIO_EXTICR2_EXTI7_PG_Pos) /*!< 0x00006000 */
+#define AFIO_EXTICR2_EXTI7_PG AFIO_EXTICR2_EXTI7_PG_Msk /*!< PG[7] pin */
+
+/***************** Bit definition for AFIO_EXTICR3 register *****************/
+#define AFIO_EXTICR3_EXTI8_Pos (0U)
+#define AFIO_EXTICR3_EXTI8_Msk (0xFU << AFIO_EXTICR3_EXTI8_Pos) /*!< 0x0000000F */
+#define AFIO_EXTICR3_EXTI8 AFIO_EXTICR3_EXTI8_Msk /*!< EXTI 8 configuration */
+#define AFIO_EXTICR3_EXTI9_Pos (4U)
+#define AFIO_EXTICR3_EXTI9_Msk (0xFU << AFIO_EXTICR3_EXTI9_Pos) /*!< 0x000000F0 */
+#define AFIO_EXTICR3_EXTI9 AFIO_EXTICR3_EXTI9_Msk /*!< EXTI 9 configuration */
+#define AFIO_EXTICR3_EXTI10_Pos (8U)
+#define AFIO_EXTICR3_EXTI10_Msk (0xFU << AFIO_EXTICR3_EXTI10_Pos) /*!< 0x00000F00 */
+#define AFIO_EXTICR3_EXTI10 AFIO_EXTICR3_EXTI10_Msk /*!< EXTI 10 configuration */
+#define AFIO_EXTICR3_EXTI11_Pos (12U)
+#define AFIO_EXTICR3_EXTI11_Msk (0xFU << AFIO_EXTICR3_EXTI11_Pos) /*!< 0x0000F000 */
+#define AFIO_EXTICR3_EXTI11 AFIO_EXTICR3_EXTI11_Msk /*!< EXTI 11 configuration */
+
+/*!< EXTI8 configuration */
+#define AFIO_EXTICR3_EXTI8_PA ((uint32_t)0x00000000) /*!< PA[8] pin */
+#define AFIO_EXTICR3_EXTI8_PB_Pos (0U)
+#define AFIO_EXTICR3_EXTI8_PB_Msk (0x1U << AFIO_EXTICR3_EXTI8_PB_Pos) /*!< 0x00000001 */
+#define AFIO_EXTICR3_EXTI8_PB AFIO_EXTICR3_EXTI8_PB_Msk /*!< PB[8] pin */
+#define AFIO_EXTICR3_EXTI8_PC_Pos (1U)
+#define AFIO_EXTICR3_EXTI8_PC_Msk (0x1U << AFIO_EXTICR3_EXTI8_PC_Pos) /*!< 0x00000002 */
+#define AFIO_EXTICR3_EXTI8_PC AFIO_EXTICR3_EXTI8_PC_Msk /*!< PC[8] pin */
+#define AFIO_EXTICR3_EXTI8_PD_Pos (0U)
+#define AFIO_EXTICR3_EXTI8_PD_Msk (0x3U << AFIO_EXTICR3_EXTI8_PD_Pos) /*!< 0x00000003 */
+#define AFIO_EXTICR3_EXTI8_PD AFIO_EXTICR3_EXTI8_PD_Msk /*!< PD[8] pin */
+#define AFIO_EXTICR3_EXTI8_PE_Pos (2U)
+#define AFIO_EXTICR3_EXTI8_PE_Msk (0x1U << AFIO_EXTICR3_EXTI8_PE_Pos) /*!< 0x00000004 */
+#define AFIO_EXTICR3_EXTI8_PE AFIO_EXTICR3_EXTI8_PE_Msk /*!< PE[8] pin */
+#define AFIO_EXTICR3_EXTI8_PF_Pos (0U)
+#define AFIO_EXTICR3_EXTI8_PF_Msk (0x5U << AFIO_EXTICR3_EXTI8_PF_Pos) /*!< 0x00000005 */
+#define AFIO_EXTICR3_EXTI8_PF AFIO_EXTICR3_EXTI8_PF_Msk /*!< PF[8] pin */
+#define AFIO_EXTICR3_EXTI8_PG_Pos (1U)
+#define AFIO_EXTICR3_EXTI8_PG_Msk (0x3U << AFIO_EXTICR3_EXTI8_PG_Pos) /*!< 0x00000006 */
+#define AFIO_EXTICR3_EXTI8_PG AFIO_EXTICR3_EXTI8_PG_Msk /*!< PG[8] pin */
+
+/*!< EXTI9 configuration */
+#define AFIO_EXTICR3_EXTI9_PA ((uint32_t)0x00000000) /*!< PA[9] pin */
+#define AFIO_EXTICR3_EXTI9_PB_Pos (4U)
+#define AFIO_EXTICR3_EXTI9_PB_Msk (0x1U << AFIO_EXTICR3_EXTI9_PB_Pos) /*!< 0x00000010 */
+#define AFIO_EXTICR3_EXTI9_PB AFIO_EXTICR3_EXTI9_PB_Msk /*!< PB[9] pin */
+#define AFIO_EXTICR3_EXTI9_PC_Pos (5U)
+#define AFIO_EXTICR3_EXTI9_PC_Msk (0x1U << AFIO_EXTICR3_EXTI9_PC_Pos) /*!< 0x00000020 */
+#define AFIO_EXTICR3_EXTI9_PC AFIO_EXTICR3_EXTI9_PC_Msk /*!< PC[9] pin */
+#define AFIO_EXTICR3_EXTI9_PD_Pos (4U)
+#define AFIO_EXTICR3_EXTI9_PD_Msk (0x3U << AFIO_EXTICR3_EXTI9_PD_Pos) /*!< 0x00000030 */
+#define AFIO_EXTICR3_EXTI9_PD AFIO_EXTICR3_EXTI9_PD_Msk /*!< PD[9] pin */
+#define AFIO_EXTICR3_EXTI9_PE_Pos (6U)
+#define AFIO_EXTICR3_EXTI9_PE_Msk (0x1U << AFIO_EXTICR3_EXTI9_PE_Pos) /*!< 0x00000040 */
+#define AFIO_EXTICR3_EXTI9_PE AFIO_EXTICR3_EXTI9_PE_Msk /*!< PE[9] pin */
+#define AFIO_EXTICR3_EXTI9_PF_Pos (4U)
+#define AFIO_EXTICR3_EXTI9_PF_Msk (0x5U << AFIO_EXTICR3_EXTI9_PF_Pos) /*!< 0x00000050 */
+#define AFIO_EXTICR3_EXTI9_PF AFIO_EXTICR3_EXTI9_PF_Msk /*!< PF[9] pin */
+#define AFIO_EXTICR3_EXTI9_PG_Pos (5U)
+#define AFIO_EXTICR3_EXTI9_PG_Msk (0x3U << AFIO_EXTICR3_EXTI9_PG_Pos) /*!< 0x00000060 */
+#define AFIO_EXTICR3_EXTI9_PG AFIO_EXTICR3_EXTI9_PG_Msk /*!< PG[9] pin */
+
+/*!< EXTI10 configuration */
+#define AFIO_EXTICR3_EXTI10_PA ((uint32_t)0x00000000) /*!< PA[10] pin */
+#define AFIO_EXTICR3_EXTI10_PB_Pos (8U)
+#define AFIO_EXTICR3_EXTI10_PB_Msk (0x1U << AFIO_EXTICR3_EXTI10_PB_Pos) /*!< 0x00000100 */
+#define AFIO_EXTICR3_EXTI10_PB AFIO_EXTICR3_EXTI10_PB_Msk /*!< PB[10] pin */
+#define AFIO_EXTICR3_EXTI10_PC_Pos (9U)
+#define AFIO_EXTICR3_EXTI10_PC_Msk (0x1U << AFIO_EXTICR3_EXTI10_PC_Pos) /*!< 0x00000200 */
+#define AFIO_EXTICR3_EXTI10_PC AFIO_EXTICR3_EXTI10_PC_Msk /*!< PC[10] pin */
+#define AFIO_EXTICR3_EXTI10_PD_Pos (8U)
+#define AFIO_EXTICR3_EXTI10_PD_Msk (0x3U << AFIO_EXTICR3_EXTI10_PD_Pos) /*!< 0x00000300 */
+#define AFIO_EXTICR3_EXTI10_PD AFIO_EXTICR3_EXTI10_PD_Msk /*!< PD[10] pin */
+#define AFIO_EXTICR3_EXTI10_PE_Pos (10U)
+#define AFIO_EXTICR3_EXTI10_PE_Msk (0x1U << AFIO_EXTICR3_EXTI10_PE_Pos) /*!< 0x00000400 */
+#define AFIO_EXTICR3_EXTI10_PE AFIO_EXTICR3_EXTI10_PE_Msk /*!< PE[10] pin */
+#define AFIO_EXTICR3_EXTI10_PF_Pos (8U)
+#define AFIO_EXTICR3_EXTI10_PF_Msk (0x5U << AFIO_EXTICR3_EXTI10_PF_Pos) /*!< 0x00000500 */
+#define AFIO_EXTICR3_EXTI10_PF AFIO_EXTICR3_EXTI10_PF_Msk /*!< PF[10] pin */
+#define AFIO_EXTICR3_EXTI10_PG_Pos (9U)
+#define AFIO_EXTICR3_EXTI10_PG_Msk (0x3U << AFIO_EXTICR3_EXTI10_PG_Pos) /*!< 0x00000600 */
+#define AFIO_EXTICR3_EXTI10_PG AFIO_EXTICR3_EXTI10_PG_Msk /*!< PG[10] pin */
+
+/*!< EXTI11 configuration */
+#define AFIO_EXTICR3_EXTI11_PA ((uint32_t)0x00000000) /*!< PA[11] pin */
+#define AFIO_EXTICR3_EXTI11_PB_Pos (12U)
+#define AFIO_EXTICR3_EXTI11_PB_Msk (0x1U << AFIO_EXTICR3_EXTI11_PB_Pos) /*!< 0x00001000 */
+#define AFIO_EXTICR3_EXTI11_PB AFIO_EXTICR3_EXTI11_PB_Msk /*!< PB[11] pin */
+#define AFIO_EXTICR3_EXTI11_PC_Pos (13U)
+#define AFIO_EXTICR3_EXTI11_PC_Msk (0x1U << AFIO_EXTICR3_EXTI11_PC_Pos) /*!< 0x00002000 */
+#define AFIO_EXTICR3_EXTI11_PC AFIO_EXTICR3_EXTI11_PC_Msk /*!< PC[11] pin */
+#define AFIO_EXTICR3_EXTI11_PD_Pos (12U)
+#define AFIO_EXTICR3_EXTI11_PD_Msk (0x3U << AFIO_EXTICR3_EXTI11_PD_Pos) /*!< 0x00003000 */
+#define AFIO_EXTICR3_EXTI11_PD AFIO_EXTICR3_EXTI11_PD_Msk /*!< PD[11] pin */
+#define AFIO_EXTICR3_EXTI11_PE_Pos (14U)
+#define AFIO_EXTICR3_EXTI11_PE_Msk (0x1U << AFIO_EXTICR3_EXTI11_PE_Pos) /*!< 0x00004000 */
+#define AFIO_EXTICR3_EXTI11_PE AFIO_EXTICR3_EXTI11_PE_Msk /*!< PE[11] pin */
+#define AFIO_EXTICR3_EXTI11_PF_Pos (12U)
+#define AFIO_EXTICR3_EXTI11_PF_Msk (0x5U << AFIO_EXTICR3_EXTI11_PF_Pos) /*!< 0x00005000 */
+#define AFIO_EXTICR3_EXTI11_PF AFIO_EXTICR3_EXTI11_PF_Msk /*!< PF[11] pin */
+#define AFIO_EXTICR3_EXTI11_PG_Pos (13U)
+#define AFIO_EXTICR3_EXTI11_PG_Msk (0x3U << AFIO_EXTICR3_EXTI11_PG_Pos) /*!< 0x00006000 */
+#define AFIO_EXTICR3_EXTI11_PG AFIO_EXTICR3_EXTI11_PG_Msk /*!< PG[11] pin */
+
+/***************** Bit definition for AFIO_EXTICR4 register *****************/
+#define AFIO_EXTICR4_EXTI12_Pos (0U)
+#define AFIO_EXTICR4_EXTI12_Msk (0xFU << AFIO_EXTICR4_EXTI12_Pos) /*!< 0x0000000F */
+#define AFIO_EXTICR4_EXTI12 AFIO_EXTICR4_EXTI12_Msk /*!< EXTI 12 configuration */
+#define AFIO_EXTICR4_EXTI13_Pos (4U)
+#define AFIO_EXTICR4_EXTI13_Msk (0xFU << AFIO_EXTICR4_EXTI13_Pos) /*!< 0x000000F0 */
+#define AFIO_EXTICR4_EXTI13 AFIO_EXTICR4_EXTI13_Msk /*!< EXTI 13 configuration */
+#define AFIO_EXTICR4_EXTI14_Pos (8U)
+#define AFIO_EXTICR4_EXTI14_Msk (0xFU << AFIO_EXTICR4_EXTI14_Pos) /*!< 0x00000F00 */
+#define AFIO_EXTICR4_EXTI14 AFIO_EXTICR4_EXTI14_Msk /*!< EXTI 14 configuration */
+#define AFIO_EXTICR4_EXTI15_Pos (12U)
+#define AFIO_EXTICR4_EXTI15_Msk (0xFU << AFIO_EXTICR4_EXTI15_Pos) /*!< 0x0000F000 */
+#define AFIO_EXTICR4_EXTI15 AFIO_EXTICR4_EXTI15_Msk /*!< EXTI 15 configuration */
+
+/* EXTI12 configuration */
+#define AFIO_EXTICR4_EXTI12_PA ((uint32_t)0x00000000) /*!< PA[12] pin */
+#define AFIO_EXTICR4_EXTI12_PB_Pos (0U)
+#define AFIO_EXTICR4_EXTI12_PB_Msk (0x1U << AFIO_EXTICR4_EXTI12_PB_Pos) /*!< 0x00000001 */
+#define AFIO_EXTICR4_EXTI12_PB AFIO_EXTICR4_EXTI12_PB_Msk /*!< PB[12] pin */
+#define AFIO_EXTICR4_EXTI12_PC_Pos (1U)
+#define AFIO_EXTICR4_EXTI12_PC_Msk (0x1U << AFIO_EXTICR4_EXTI12_PC_Pos) /*!< 0x00000002 */
+#define AFIO_EXTICR4_EXTI12_PC AFIO_EXTICR4_EXTI12_PC_Msk /*!< PC[12] pin */
+#define AFIO_EXTICR4_EXTI12_PD_Pos (0U)
+#define AFIO_EXTICR4_EXTI12_PD_Msk (0x3U << AFIO_EXTICR4_EXTI12_PD_Pos) /*!< 0x00000003 */
+#define AFIO_EXTICR4_EXTI12_PD AFIO_EXTICR4_EXTI12_PD_Msk /*!< PD[12] pin */
+#define AFIO_EXTICR4_EXTI12_PE_Pos (2U)
+#define AFIO_EXTICR4_EXTI12_PE_Msk (0x1U << AFIO_EXTICR4_EXTI12_PE_Pos) /*!< 0x00000004 */
+#define AFIO_EXTICR4_EXTI12_PE AFIO_EXTICR4_EXTI12_PE_Msk /*!< PE[12] pin */
+#define AFIO_EXTICR4_EXTI12_PF_Pos (0U)
+#define AFIO_EXTICR4_EXTI12_PF_Msk (0x5U << AFIO_EXTICR4_EXTI12_PF_Pos) /*!< 0x00000005 */
+#define AFIO_EXTICR4_EXTI12_PF AFIO_EXTICR4_EXTI12_PF_Msk /*!< PF[12] pin */
+#define AFIO_EXTICR4_EXTI12_PG_Pos (1U)
+#define AFIO_EXTICR4_EXTI12_PG_Msk (0x3U << AFIO_EXTICR4_EXTI12_PG_Pos) /*!< 0x00000006 */
+#define AFIO_EXTICR4_EXTI12_PG AFIO_EXTICR4_EXTI12_PG_Msk /*!< PG[12] pin */
+
+/* EXTI13 configuration */
+#define AFIO_EXTICR4_EXTI13_PA ((uint32_t)0x00000000) /*!< PA[13] pin */
+#define AFIO_EXTICR4_EXTI13_PB_Pos (4U)
+#define AFIO_EXTICR4_EXTI13_PB_Msk (0x1U << AFIO_EXTICR4_EXTI13_PB_Pos) /*!< 0x00000010 */
+#define AFIO_EXTICR4_EXTI13_PB AFIO_EXTICR4_EXTI13_PB_Msk /*!< PB[13] pin */
+#define AFIO_EXTICR4_EXTI13_PC_Pos (5U)
+#define AFIO_EXTICR4_EXTI13_PC_Msk (0x1U << AFIO_EXTICR4_EXTI13_PC_Pos) /*!< 0x00000020 */
+#define AFIO_EXTICR4_EXTI13_PC AFIO_EXTICR4_EXTI13_PC_Msk /*!< PC[13] pin */
+#define AFIO_EXTICR4_EXTI13_PD_Pos (4U)
+#define AFIO_EXTICR4_EXTI13_PD_Msk (0x3U << AFIO_EXTICR4_EXTI13_PD_Pos) /*!< 0x00000030 */
+#define AFIO_EXTICR4_EXTI13_PD AFIO_EXTICR4_EXTI13_PD_Msk /*!< PD[13] pin */
+#define AFIO_EXTICR4_EXTI13_PE_Pos (6U)
+#define AFIO_EXTICR4_EXTI13_PE_Msk (0x1U << AFIO_EXTICR4_EXTI13_PE_Pos) /*!< 0x00000040 */
+#define AFIO_EXTICR4_EXTI13_PE AFIO_EXTICR4_EXTI13_PE_Msk /*!< PE[13] pin */
+#define AFIO_EXTICR4_EXTI13_PF_Pos (4U)
+#define AFIO_EXTICR4_EXTI13_PF_Msk (0x5U << AFIO_EXTICR4_EXTI13_PF_Pos) /*!< 0x00000050 */
+#define AFIO_EXTICR4_EXTI13_PF AFIO_EXTICR4_EXTI13_PF_Msk /*!< PF[13] pin */
+#define AFIO_EXTICR4_EXTI13_PG_Pos (5U)
+#define AFIO_EXTICR4_EXTI13_PG_Msk (0x3U << AFIO_EXTICR4_EXTI13_PG_Pos) /*!< 0x00000060 */
+#define AFIO_EXTICR4_EXTI13_PG AFIO_EXTICR4_EXTI13_PG_Msk /*!< PG[13] pin */
+
+/*!< EXTI14 configuration */
+#define AFIO_EXTICR4_EXTI14_PA ((uint32_t)0x00000000) /*!< PA[14] pin */
+#define AFIO_EXTICR4_EXTI14_PB_Pos (8U)
+#define AFIO_EXTICR4_EXTI14_PB_Msk (0x1U << AFIO_EXTICR4_EXTI14_PB_Pos) /*!< 0x00000100 */
+#define AFIO_EXTICR4_EXTI14_PB AFIO_EXTICR4_EXTI14_PB_Msk /*!< PB[14] pin */
+#define AFIO_EXTICR4_EXTI14_PC_Pos (9U)
+#define AFIO_EXTICR4_EXTI14_PC_Msk (0x1U << AFIO_EXTICR4_EXTI14_PC_Pos) /*!< 0x00000200 */
+#define AFIO_EXTICR4_EXTI14_PC AFIO_EXTICR4_EXTI14_PC_Msk /*!< PC[14] pin */
+#define AFIO_EXTICR4_EXTI14_PD_Pos (8U)
+#define AFIO_EXTICR4_EXTI14_PD_Msk (0x3U << AFIO_EXTICR4_EXTI14_PD_Pos) /*!< 0x00000300 */
+#define AFIO_EXTICR4_EXTI14_PD AFIO_EXTICR4_EXTI14_PD_Msk /*!< PD[14] pin */
+#define AFIO_EXTICR4_EXTI14_PE_Pos (10U)
+#define AFIO_EXTICR4_EXTI14_PE_Msk (0x1U << AFIO_EXTICR4_EXTI14_PE_Pos) /*!< 0x00000400 */
+#define AFIO_EXTICR4_EXTI14_PE AFIO_EXTICR4_EXTI14_PE_Msk /*!< PE[14] pin */
+#define AFIO_EXTICR4_EXTI14_PF_Pos (8U)
+#define AFIO_EXTICR4_EXTI14_PF_Msk (0x5U << AFIO_EXTICR4_EXTI14_PF_Pos) /*!< 0x00000500 */
+#define AFIO_EXTICR4_EXTI14_PF AFIO_EXTICR4_EXTI14_PF_Msk /*!< PF[14] pin */
+#define AFIO_EXTICR4_EXTI14_PG_Pos (9U)
+#define AFIO_EXTICR4_EXTI14_PG_Msk (0x3U << AFIO_EXTICR4_EXTI14_PG_Pos) /*!< 0x00000600 */
+#define AFIO_EXTICR4_EXTI14_PG AFIO_EXTICR4_EXTI14_PG_Msk /*!< PG[14] pin */
+
+/*!< EXTI15 configuration */
+#define AFIO_EXTICR4_EXTI15_PA ((uint32_t)0x00000000) /*!< PA[15] pin */
+#define AFIO_EXTICR4_EXTI15_PB_Pos (12U)
+#define AFIO_EXTICR4_EXTI15_PB_Msk (0x1U << AFIO_EXTICR4_EXTI15_PB_Pos) /*!< 0x00001000 */
+#define AFIO_EXTICR4_EXTI15_PB AFIO_EXTICR4_EXTI15_PB_Msk /*!< PB[15] pin */
+#define AFIO_EXTICR4_EXTI15_PC_Pos (13U)
+#define AFIO_EXTICR4_EXTI15_PC_Msk (0x1U << AFIO_EXTICR4_EXTI15_PC_Pos) /*!< 0x00002000 */
+#define AFIO_EXTICR4_EXTI15_PC AFIO_EXTICR4_EXTI15_PC_Msk /*!< PC[15] pin */
+#define AFIO_EXTICR4_EXTI15_PD_Pos (12U)
+#define AFIO_EXTICR4_EXTI15_PD_Msk (0x3U << AFIO_EXTICR4_EXTI15_PD_Pos) /*!< 0x00003000 */
+#define AFIO_EXTICR4_EXTI15_PD AFIO_EXTICR4_EXTI15_PD_Msk /*!< PD[15] pin */
+#define AFIO_EXTICR4_EXTI15_PE_Pos (14U)
+#define AFIO_EXTICR4_EXTI15_PE_Msk (0x1U << AFIO_EXTICR4_EXTI15_PE_Pos) /*!< 0x00004000 */
+#define AFIO_EXTICR4_EXTI15_PE AFIO_EXTICR4_EXTI15_PE_Msk /*!< PE[15] pin */
+#define AFIO_EXTICR4_EXTI15_PF_Pos (12U)
+#define AFIO_EXTICR4_EXTI15_PF_Msk (0x5U << AFIO_EXTICR4_EXTI15_PF_Pos) /*!< 0x00005000 */
+#define AFIO_EXTICR4_EXTI15_PF AFIO_EXTICR4_EXTI15_PF_Msk /*!< PF[15] pin */
+#define AFIO_EXTICR4_EXTI15_PG_Pos (13U)
+#define AFIO_EXTICR4_EXTI15_PG_Msk (0x3U << AFIO_EXTICR4_EXTI15_PG_Pos) /*!< 0x00006000 */
+#define AFIO_EXTICR4_EXTI15_PG AFIO_EXTICR4_EXTI15_PG_Msk /*!< PG[15] pin */
+
+/****************** Bit definition for AFIO_MAPR2 register ******************/
+
+
+
+/******************************************************************************/
+/* */
+/* SystemTick */
+/* */
+/******************************************************************************/
+
+/***************** Bit definition for SysTick_CTRL register *****************/
+#define SysTick_CTRL_ENABLE ((uint32_t)0x00000001) /*!< Counter enable */
+#define SysTick_CTRL_TICKINT ((uint32_t)0x00000002) /*!< Counting down to 0 pends the SysTick handler */
+#define SysTick_CTRL_CLKSOURCE ((uint32_t)0x00000004) /*!< Clock source */
+#define SysTick_CTRL_COUNTFLAG ((uint32_t)0x00010000) /*!< Count Flag */
+
+/***************** Bit definition for SysTick_LOAD register *****************/
+#define SysTick_LOAD_RELOAD ((uint32_t)0x00FFFFFF) /*!< Value to load into the SysTick Current Value Register when the counter reaches 0 */
+
+/***************** Bit definition for SysTick_VAL register ******************/
+#define SysTick_VAL_CURRENT ((uint32_t)0x00FFFFFF) /*!< Current value at the time the register is accessed */
+
+/***************** Bit definition for SysTick_CALIB register ****************/
+#define SysTick_CALIB_TENMS ((uint32_t)0x00FFFFFF) /*!< Reload value to use for 10ms timing */
+#define SysTick_CALIB_SKEW ((uint32_t)0x40000000) /*!< Calibration value is not exactly 10 ms */
+#define SysTick_CALIB_NOREF ((uint32_t)0x80000000) /*!< The reference clock is not provided */
+
+/******************************************************************************/
+/* */
+/* Nested Vectored Interrupt Controller */
+/* */
+/******************************************************************************/
+
+/****************** Bit definition for NVIC_ISER register *******************/
+#define NVIC_ISER_SETENA_Pos (0U)
+#define NVIC_ISER_SETENA_Msk (0xFFFFFFFFU << NVIC_ISER_SETENA_Pos) /*!< 0xFFFFFFFF */
+#define NVIC_ISER_SETENA NVIC_ISER_SETENA_Msk /*!< Interrupt set enable bits */
+#define NVIC_ISER_SETENA_0 (0x00000001U << NVIC_ISER_SETENA_Pos) /*!< 0x00000001 */
+#define NVIC_ISER_SETENA_1 (0x00000002U << NVIC_ISER_SETENA_Pos) /*!< 0x00000002 */
+#define NVIC_ISER_SETENA_2 (0x00000004U << NVIC_ISER_SETENA_Pos) /*!< 0x00000004 */
+#define NVIC_ISER_SETENA_3 (0x00000008U << NVIC_ISER_SETENA_Pos) /*!< 0x00000008 */
+#define NVIC_ISER_SETENA_4 (0x00000010U << NVIC_ISER_SETENA_Pos) /*!< 0x00000010 */
+#define NVIC_ISER_SETENA_5 (0x00000020U << NVIC_ISER_SETENA_Pos) /*!< 0x00000020 */
+#define NVIC_ISER_SETENA_6 (0x00000040U << NVIC_ISER_SETENA_Pos) /*!< 0x00000040 */
+#define NVIC_ISER_SETENA_7 (0x00000080U << NVIC_ISER_SETENA_Pos) /*!< 0x00000080 */
+#define NVIC_ISER_SETENA_8 (0x00000100U << NVIC_ISER_SETENA_Pos) /*!< 0x00000100 */
+#define NVIC_ISER_SETENA_9 (0x00000200U << NVIC_ISER_SETENA_Pos) /*!< 0x00000200 */
+#define NVIC_ISER_SETENA_10 (0x00000400U << NVIC_ISER_SETENA_Pos) /*!< 0x00000400 */
+#define NVIC_ISER_SETENA_11 (0x00000800U << NVIC_ISER_SETENA_Pos) /*!< 0x00000800 */
+#define NVIC_ISER_SETENA_12 (0x00001000U << NVIC_ISER_SETENA_Pos) /*!< 0x00001000 */
+#define NVIC_ISER_SETENA_13 (0x00002000U << NVIC_ISER_SETENA_Pos) /*!< 0x00002000 */
+#define NVIC_ISER_SETENA_14 (0x00004000U << NVIC_ISER_SETENA_Pos) /*!< 0x00004000 */
+#define NVIC_ISER_SETENA_15 (0x00008000U << NVIC_ISER_SETENA_Pos) /*!< 0x00008000 */
+#define NVIC_ISER_SETENA_16 (0x00010000U << NVIC_ISER_SETENA_Pos) /*!< 0x00010000 */
+#define NVIC_ISER_SETENA_17 (0x00020000U << NVIC_ISER_SETENA_Pos) /*!< 0x00020000 */
+#define NVIC_ISER_SETENA_18 (0x00040000U << NVIC_ISER_SETENA_Pos) /*!< 0x00040000 */
+#define NVIC_ISER_SETENA_19 (0x00080000U << NVIC_ISER_SETENA_Pos) /*!< 0x00080000 */
+#define NVIC_ISER_SETENA_20 (0x00100000U << NVIC_ISER_SETENA_Pos) /*!< 0x00100000 */
+#define NVIC_ISER_SETENA_21 (0x00200000U << NVIC_ISER_SETENA_Pos) /*!< 0x00200000 */
+#define NVIC_ISER_SETENA_22 (0x00400000U << NVIC_ISER_SETENA_Pos) /*!< 0x00400000 */
+#define NVIC_ISER_SETENA_23 (0x00800000U << NVIC_ISER_SETENA_Pos) /*!< 0x00800000 */
+#define NVIC_ISER_SETENA_24 (0x01000000U << NVIC_ISER_SETENA_Pos) /*!< 0x01000000 */
+#define NVIC_ISER_SETENA_25 (0x02000000U << NVIC_ISER_SETENA_Pos) /*!< 0x02000000 */
+#define NVIC_ISER_SETENA_26 (0x04000000U << NVIC_ISER_SETENA_Pos) /*!< 0x04000000 */
+#define NVIC_ISER_SETENA_27 (0x08000000U << NVIC_ISER_SETENA_Pos) /*!< 0x08000000 */
+#define NVIC_ISER_SETENA_28 (0x10000000U << NVIC_ISER_SETENA_Pos) /*!< 0x10000000 */
+#define NVIC_ISER_SETENA_29 (0x20000000U << NVIC_ISER_SETENA_Pos) /*!< 0x20000000 */
+#define NVIC_ISER_SETENA_30 (0x40000000U << NVIC_ISER_SETENA_Pos) /*!< 0x40000000 */
+#define NVIC_ISER_SETENA_31 (0x80000000U << NVIC_ISER_SETENA_Pos) /*!< 0x80000000 */
+
+/****************** Bit definition for NVIC_ICER register *******************/
+#define NVIC_ICER_CLRENA_Pos (0U)
+#define NVIC_ICER_CLRENA_Msk (0xFFFFFFFFU << NVIC_ICER_CLRENA_Pos) /*!< 0xFFFFFFFF */
+#define NVIC_ICER_CLRENA NVIC_ICER_CLRENA_Msk /*!< Interrupt clear-enable bits */
+#define NVIC_ICER_CLRENA_0 (0x00000001U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000001 */
+#define NVIC_ICER_CLRENA_1 (0x00000002U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000002 */
+#define NVIC_ICER_CLRENA_2 (0x00000004U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000004 */
+#define NVIC_ICER_CLRENA_3 (0x00000008U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000008 */
+#define NVIC_ICER_CLRENA_4 (0x00000010U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000010 */
+#define NVIC_ICER_CLRENA_5 (0x00000020U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000020 */
+#define NVIC_ICER_CLRENA_6 (0x00000040U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000040 */
+#define NVIC_ICER_CLRENA_7 (0x00000080U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000080 */
+#define NVIC_ICER_CLRENA_8 (0x00000100U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000100 */
+#define NVIC_ICER_CLRENA_9 (0x00000200U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000200 */
+#define NVIC_ICER_CLRENA_10 (0x00000400U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000400 */
+#define NVIC_ICER_CLRENA_11 (0x00000800U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000800 */
+#define NVIC_ICER_CLRENA_12 (0x00001000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00001000 */
+#define NVIC_ICER_CLRENA_13 (0x00002000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00002000 */
+#define NVIC_ICER_CLRENA_14 (0x00004000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00004000 */
+#define NVIC_ICER_CLRENA_15 (0x00008000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00008000 */
+#define NVIC_ICER_CLRENA_16 (0x00010000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00010000 */
+#define NVIC_ICER_CLRENA_17 (0x00020000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00020000 */
+#define NVIC_ICER_CLRENA_18 (0x00040000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00040000 */
+#define NVIC_ICER_CLRENA_19 (0x00080000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00080000 */
+#define NVIC_ICER_CLRENA_20 (0x00100000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00100000 */
+#define NVIC_ICER_CLRENA_21 (0x00200000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00200000 */
+#define NVIC_ICER_CLRENA_22 (0x00400000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00400000 */
+#define NVIC_ICER_CLRENA_23 (0x00800000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00800000 */
+#define NVIC_ICER_CLRENA_24 (0x01000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x01000000 */
+#define NVIC_ICER_CLRENA_25 (0x02000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x02000000 */
+#define NVIC_ICER_CLRENA_26 (0x04000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x04000000 */
+#define NVIC_ICER_CLRENA_27 (0x08000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x08000000 */
+#define NVIC_ICER_CLRENA_28 (0x10000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x10000000 */
+#define NVIC_ICER_CLRENA_29 (0x20000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x20000000 */
+#define NVIC_ICER_CLRENA_30 (0x40000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x40000000 */
+#define NVIC_ICER_CLRENA_31 (0x80000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x80000000 */
+
+/****************** Bit definition for NVIC_ISPR register *******************/
+#define NVIC_ISPR_SETPEND_Pos (0U)
+#define NVIC_ISPR_SETPEND_Msk (0xFFFFFFFFU << NVIC_ISPR_SETPEND_Pos) /*!< 0xFFFFFFFF */
+#define NVIC_ISPR_SETPEND NVIC_ISPR_SETPEND_Msk /*!< Interrupt set-pending bits */
+#define NVIC_ISPR_SETPEND_0 (0x00000001U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000001 */
+#define NVIC_ISPR_SETPEND_1 (0x00000002U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000002 */
+#define NVIC_ISPR_SETPEND_2 (0x00000004U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000004 */
+#define NVIC_ISPR_SETPEND_3 (0x00000008U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000008 */
+#define NVIC_ISPR_SETPEND_4 (0x00000010U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000010 */
+#define NVIC_ISPR_SETPEND_5 (0x00000020U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000020 */
+#define NVIC_ISPR_SETPEND_6 (0x00000040U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000040 */
+#define NVIC_ISPR_SETPEND_7 (0x00000080U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000080 */
+#define NVIC_ISPR_SETPEND_8 (0x00000100U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000100 */
+#define NVIC_ISPR_SETPEND_9 (0x00000200U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000200 */
+#define NVIC_ISPR_SETPEND_10 (0x00000400U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000400 */
+#define NVIC_ISPR_SETPEND_11 (0x00000800U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000800 */
+#define NVIC_ISPR_SETPEND_12 (0x00001000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00001000 */
+#define NVIC_ISPR_SETPEND_13 (0x00002000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00002000 */
+#define NVIC_ISPR_SETPEND_14 (0x00004000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00004000 */
+#define NVIC_ISPR_SETPEND_15 (0x00008000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00008000 */
+#define NVIC_ISPR_SETPEND_16 (0x00010000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00010000 */
+#define NVIC_ISPR_SETPEND_17 (0x00020000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00020000 */
+#define NVIC_ISPR_SETPEND_18 (0x00040000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00040000 */
+#define NVIC_ISPR_SETPEND_19 (0x00080000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00080000 */
+#define NVIC_ISPR_SETPEND_20 (0x00100000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00100000 */
+#define NVIC_ISPR_SETPEND_21 (0x00200000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00200000 */
+#define NVIC_ISPR_SETPEND_22 (0x00400000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00400000 */
+#define NVIC_ISPR_SETPEND_23 (0x00800000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00800000 */
+#define NVIC_ISPR_SETPEND_24 (0x01000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x01000000 */
+#define NVIC_ISPR_SETPEND_25 (0x02000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x02000000 */
+#define NVIC_ISPR_SETPEND_26 (0x04000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x04000000 */
+#define NVIC_ISPR_SETPEND_27 (0x08000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x08000000 */
+#define NVIC_ISPR_SETPEND_28 (0x10000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x10000000 */
+#define NVIC_ISPR_SETPEND_29 (0x20000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x20000000 */
+#define NVIC_ISPR_SETPEND_30 (0x40000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x40000000 */
+#define NVIC_ISPR_SETPEND_31 (0x80000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x80000000 */
+
+/****************** Bit definition for NVIC_ICPR register *******************/
+#define NVIC_ICPR_CLRPEND_Pos (0U)
+#define NVIC_ICPR_CLRPEND_Msk (0xFFFFFFFFU << NVIC_ICPR_CLRPEND_Pos) /*!< 0xFFFFFFFF */
+#define NVIC_ICPR_CLRPEND NVIC_ICPR_CLRPEND_Msk /*!< Interrupt clear-pending bits */
+#define NVIC_ICPR_CLRPEND_0 (0x00000001U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000001 */
+#define NVIC_ICPR_CLRPEND_1 (0x00000002U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000002 */
+#define NVIC_ICPR_CLRPEND_2 (0x00000004U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000004 */
+#define NVIC_ICPR_CLRPEND_3 (0x00000008U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000008 */
+#define NVIC_ICPR_CLRPEND_4 (0x00000010U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000010 */
+#define NVIC_ICPR_CLRPEND_5 (0x00000020U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000020 */
+#define NVIC_ICPR_CLRPEND_6 (0x00000040U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000040 */
+#define NVIC_ICPR_CLRPEND_7 (0x00000080U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000080 */
+#define NVIC_ICPR_CLRPEND_8 (0x00000100U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000100 */
+#define NVIC_ICPR_CLRPEND_9 (0x00000200U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000200 */
+#define NVIC_ICPR_CLRPEND_10 (0x00000400U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000400 */
+#define NVIC_ICPR_CLRPEND_11 (0x00000800U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000800 */
+#define NVIC_ICPR_CLRPEND_12 (0x00001000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00001000 */
+#define NVIC_ICPR_CLRPEND_13 (0x00002000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00002000 */
+#define NVIC_ICPR_CLRPEND_14 (0x00004000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00004000 */
+#define NVIC_ICPR_CLRPEND_15 (0x00008000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00008000 */
+#define NVIC_ICPR_CLRPEND_16 (0x00010000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00010000 */
+#define NVIC_ICPR_CLRPEND_17 (0x00020000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00020000 */
+#define NVIC_ICPR_CLRPEND_18 (0x00040000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00040000 */
+#define NVIC_ICPR_CLRPEND_19 (0x00080000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00080000 */
+#define NVIC_ICPR_CLRPEND_20 (0x00100000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00100000 */
+#define NVIC_ICPR_CLRPEND_21 (0x00200000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00200000 */
+#define NVIC_ICPR_CLRPEND_22 (0x00400000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00400000 */
+#define NVIC_ICPR_CLRPEND_23 (0x00800000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00800000 */
+#define NVIC_ICPR_CLRPEND_24 (0x01000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x01000000 */
+#define NVIC_ICPR_CLRPEND_25 (0x02000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x02000000 */
+#define NVIC_ICPR_CLRPEND_26 (0x04000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x04000000 */
+#define NVIC_ICPR_CLRPEND_27 (0x08000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x08000000 */
+#define NVIC_ICPR_CLRPEND_28 (0x10000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x10000000 */
+#define NVIC_ICPR_CLRPEND_29 (0x20000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x20000000 */
+#define NVIC_ICPR_CLRPEND_30 (0x40000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x40000000 */
+#define NVIC_ICPR_CLRPEND_31 (0x80000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x80000000 */
+
+/****************** Bit definition for NVIC_IABR register *******************/
+#define NVIC_IABR_ACTIVE_Pos (0U)
+#define NVIC_IABR_ACTIVE_Msk (0xFFFFFFFFU << NVIC_IABR_ACTIVE_Pos) /*!< 0xFFFFFFFF */
+#define NVIC_IABR_ACTIVE NVIC_IABR_ACTIVE_Msk /*!< Interrupt active flags */
+#define NVIC_IABR_ACTIVE_0 (0x00000001U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000001 */
+#define NVIC_IABR_ACTIVE_1 (0x00000002U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000002 */
+#define NVIC_IABR_ACTIVE_2 (0x00000004U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000004 */
+#define NVIC_IABR_ACTIVE_3 (0x00000008U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000008 */
+#define NVIC_IABR_ACTIVE_4 (0x00000010U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000010 */
+#define NVIC_IABR_ACTIVE_5 (0x00000020U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000020 */
+#define NVIC_IABR_ACTIVE_6 (0x00000040U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000040 */
+#define NVIC_IABR_ACTIVE_7 (0x00000080U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000080 */
+#define NVIC_IABR_ACTIVE_8 (0x00000100U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000100 */
+#define NVIC_IABR_ACTIVE_9 (0x00000200U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000200 */
+#define NVIC_IABR_ACTIVE_10 (0x00000400U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000400 */
+#define NVIC_IABR_ACTIVE_11 (0x00000800U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000800 */
+#define NVIC_IABR_ACTIVE_12 (0x00001000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00001000 */
+#define NVIC_IABR_ACTIVE_13 (0x00002000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00002000 */
+#define NVIC_IABR_ACTIVE_14 (0x00004000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00004000 */
+#define NVIC_IABR_ACTIVE_15 (0x00008000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00008000 */
+#define NVIC_IABR_ACTIVE_16 (0x00010000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00010000 */
+#define NVIC_IABR_ACTIVE_17 (0x00020000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00020000 */
+#define NVIC_IABR_ACTIVE_18 (0x00040000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00040000 */
+#define NVIC_IABR_ACTIVE_19 (0x00080000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00080000 */
+#define NVIC_IABR_ACTIVE_20 (0x00100000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00100000 */
+#define NVIC_IABR_ACTIVE_21 (0x00200000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00200000 */
+#define NVIC_IABR_ACTIVE_22 (0x00400000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00400000 */
+#define NVIC_IABR_ACTIVE_23 (0x00800000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00800000 */
+#define NVIC_IABR_ACTIVE_24 (0x01000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x01000000 */
+#define NVIC_IABR_ACTIVE_25 (0x02000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x02000000 */
+#define NVIC_IABR_ACTIVE_26 (0x04000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x04000000 */
+#define NVIC_IABR_ACTIVE_27 (0x08000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x08000000 */
+#define NVIC_IABR_ACTIVE_28 (0x10000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x10000000 */
+#define NVIC_IABR_ACTIVE_29 (0x20000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x20000000 */
+#define NVIC_IABR_ACTIVE_30 (0x40000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x40000000 */
+#define NVIC_IABR_ACTIVE_31 (0x80000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x80000000 */
+
+/****************** Bit definition for NVIC_PRI0 register *******************/
+#define NVIC_IPR0_PRI_0 ((uint32_t)0x000000FF) /*!< Priority of interrupt 0 */
+#define NVIC_IPR0_PRI_1 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 1 */
+#define NVIC_IPR0_PRI_2 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 2 */
+#define NVIC_IPR0_PRI_3 ((uint32_t)0xFF000000) /*!< Priority of interrupt 3 */
+
+/****************** Bit definition for NVIC_PRI1 register *******************/
+#define NVIC_IPR1_PRI_4 ((uint32_t)0x000000FF) /*!< Priority of interrupt 4 */
+#define NVIC_IPR1_PRI_5 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 5 */
+#define NVIC_IPR1_PRI_6 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 6 */
+#define NVIC_IPR1_PRI_7 ((uint32_t)0xFF000000) /*!< Priority of interrupt 7 */
+
+/****************** Bit definition for NVIC_PRI2 register *******************/
+#define NVIC_IPR2_PRI_8 ((uint32_t)0x000000FF) /*!< Priority of interrupt 8 */
+#define NVIC_IPR2_PRI_9 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 9 */
+#define NVIC_IPR2_PRI_10 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 10 */
+#define NVIC_IPR2_PRI_11 ((uint32_t)0xFF000000) /*!< Priority of interrupt 11 */
+
+/****************** Bit definition for NVIC_PRI3 register *******************/
+#define NVIC_IPR3_PRI_12 ((uint32_t)0x000000FF) /*!< Priority of interrupt 12 */
+#define NVIC_IPR3_PRI_13 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 13 */
+#define NVIC_IPR3_PRI_14 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 14 */
+#define NVIC_IPR3_PRI_15 ((uint32_t)0xFF000000) /*!< Priority of interrupt 15 */
+
+/****************** Bit definition for NVIC_PRI4 register *******************/
+#define NVIC_IPR4_PRI_16 ((uint32_t)0x000000FF) /*!< Priority of interrupt 16 */
+#define NVIC_IPR4_PRI_17 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 17 */
+#define NVIC_IPR4_PRI_18 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 18 */
+#define NVIC_IPR4_PRI_19 ((uint32_t)0xFF000000) /*!< Priority of interrupt 19 */
+
+/****************** Bit definition for NVIC_PRI5 register *******************/
+#define NVIC_IPR5_PRI_20 ((uint32_t)0x000000FF) /*!< Priority of interrupt 20 */
+#define NVIC_IPR5_PRI_21 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 21 */
+#define NVIC_IPR5_PRI_22 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 22 */
+#define NVIC_IPR5_PRI_23 ((uint32_t)0xFF000000) /*!< Priority of interrupt 23 */
+
+/****************** Bit definition for NVIC_PRI6 register *******************/
+#define NVIC_IPR6_PRI_24 ((uint32_t)0x000000FF) /*!< Priority of interrupt 24 */
+#define NVIC_IPR6_PRI_25 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 25 */
+#define NVIC_IPR6_PRI_26 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 26 */
+#define NVIC_IPR6_PRI_27 ((uint32_t)0xFF000000) /*!< Priority of interrupt 27 */
+
+/****************** Bit definition for NVIC_PRI7 register *******************/
+#define NVIC_IPR7_PRI_28 ((uint32_t)0x000000FF) /*!< Priority of interrupt 28 */
+#define NVIC_IPR7_PRI_29 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 29 */
+#define NVIC_IPR7_PRI_30 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 30 */
+#define NVIC_IPR7_PRI_31 ((uint32_t)0xFF000000) /*!< Priority of interrupt 31 */
+
+/****************** Bit definition for SCB_CPUID register *******************/
+#define SCB_CPUID_REVISION ((uint32_t)0x0000000F) /*!< Implementation defined revision number */
+#define SCB_CPUID_PARTNO ((uint32_t)0x0000FFF0) /*!< Number of processor within family */
+#define SCB_CPUID_Constant ((uint32_t)0x000F0000) /*!< Reads as 0x0F */
+#define SCB_CPUID_VARIANT ((uint32_t)0x00F00000) /*!< Implementation defined variant number */
+#define SCB_CPUID_IMPLEMENTER ((uint32_t)0xFF000000) /*!< Implementer code. ARM is 0x41 */
+
+/******************* Bit definition for SCB_ICSR register *******************/
+#define SCB_ICSR_VECTACTIVE ((uint32_t)0x000001FF) /*!< Active ISR number field */
+#define SCB_ICSR_RETTOBASE ((uint32_t)0x00000800) /*!< All active exceptions minus the IPSR_current_exception yields the empty set */
+#define SCB_ICSR_VECTPENDING ((uint32_t)0x003FF000) /*!< Pending ISR number field */
+#define SCB_ICSR_ISRPENDING ((uint32_t)0x00400000) /*!< Interrupt pending flag */
+#define SCB_ICSR_ISRPREEMPT ((uint32_t)0x00800000) /*!< It indicates that a pending interrupt becomes active in the next running cycle */
+#define SCB_ICSR_PENDSTCLR ((uint32_t)0x02000000) /*!< Clear pending SysTick bit */
+#define SCB_ICSR_PENDSTSET ((uint32_t)0x04000000) /*!< Set pending SysTick bit */
+#define SCB_ICSR_PENDSVCLR ((uint32_t)0x08000000) /*!< Clear pending pendSV bit */
+#define SCB_ICSR_PENDSVSET ((uint32_t)0x10000000) /*!< Set pending pendSV bit */
+#define SCB_ICSR_NMIPENDSET ((uint32_t)0x80000000) /*!< Set pending NMI bit */
+
+/******************* Bit definition for SCB_VTOR register *******************/
+#define SCB_VTOR_TBLOFF ((uint32_t)0x1FFFFF80) /*!< Vector table base offset field */
+#define SCB_VTOR_TBLBASE ((uint32_t)0x20000000) /*!< Table base in code(0) or RAM(1) */
+
+/*!<***************** Bit definition for SCB_AIRCR register *******************/
+#define SCB_AIRCR_VECTRESET ((uint32_t)0x00000001) /*!< System Reset bit */
+#define SCB_AIRCR_VECTCLRACTIVE ((uint32_t)0x00000002) /*!< Clear active vector bit */
+#define SCB_AIRCR_SYSRESETREQ ((uint32_t)0x00000004) /*!< Requests chip control logic to generate a reset */
+
+#define SCB_AIRCR_PRIGROUP ((uint32_t)0x00000700) /*!< PRIGROUP[2:0] bits (Priority group) */
+#define SCB_AIRCR_PRIGROUP_0 ((uint32_t)0x00000100) /*!< Bit 0 */
+#define SCB_AIRCR_PRIGROUP_1 ((uint32_t)0x00000200) /*!< Bit 1 */
+#define SCB_AIRCR_PRIGROUP_2 ((uint32_t)0x00000400) /*!< Bit 2 */
+
+/* prority group configuration */
+#define SCB_AIRCR_PRIGROUP0 ((uint32_t)0x00000000) /*!< Priority group=0 (7 bits of pre-emption priority, 1 bit of subpriority) */
+#define SCB_AIRCR_PRIGROUP1 ((uint32_t)0x00000100) /*!< Priority group=1 (6 bits of pre-emption priority, 2 bits of subpriority) */
+#define SCB_AIRCR_PRIGROUP2 ((uint32_t)0x00000200) /*!< Priority group=2 (5 bits of pre-emption priority, 3 bits of subpriority) */
+#define SCB_AIRCR_PRIGROUP3 ((uint32_t)0x00000300) /*!< Priority group=3 (4 bits of pre-emption priority, 4 bits of subpriority) */
+#define SCB_AIRCR_PRIGROUP4 ((uint32_t)0x00000400) /*!< Priority group=4 (3 bits of pre-emption priority, 5 bits of subpriority) */
+#define SCB_AIRCR_PRIGROUP5 ((uint32_t)0x00000500) /*!< Priority group=5 (2 bits of pre-emption priority, 6 bits of subpriority) */
+#define SCB_AIRCR_PRIGROUP6 ((uint32_t)0x00000600) /*!< Priority group=6 (1 bit of pre-emption priority, 7 bits of subpriority) */
+#define SCB_AIRCR_PRIGROUP7 ((uint32_t)0x00000700) /*!< Priority group=7 (no pre-emption priority, 8 bits of subpriority) */
+
+#define SCB_AIRCR_ENDIANESS ((uint32_t)0x00008000) /*!< Data endianness bit */
+#define SCB_AIRCR_VECTKEY ((uint32_t)0xFFFF0000) /*!< Register key (VECTKEY) - Reads as 0xFA05 (VECTKEYSTAT) */
+
+/******************* Bit definition for SCB_SCR register ********************/
+#define SCB_SCR_SLEEPONEXIT ((uint32_t)0x00000002) /*!< Sleep on exit bit */
+#define SCB_SCR_SLEEPDEEP ((uint32_t)0x00000004) /*!< Sleep deep bit */
+#define SCB_SCR_SEVONPEND ((uint32_t)0x00000010) /*!< Wake up from WFE */
+
+/******************** Bit definition for SCB_CCR register *******************/
+#define SCB_CCR_NONBASETHRDENA ((uint32_t)0x00000001) /*!< Thread mode can be entered from any level in Handler mode by controlled return value */
+#define SCB_CCR_USERSETMPEND ((uint32_t)0x00000002) /*!< Enables user code to write the Software Trigger Interrupt register to trigger (pend) a Main exception */
+#define SCB_CCR_UNALIGN_TRP ((uint32_t)0x00000008) /*!< Trap for unaligned access */
+#define SCB_CCR_DIV_0_TRP ((uint32_t)0x00000010) /*!< Trap on Divide by 0 */
+#define SCB_CCR_BFHFNMIGN ((uint32_t)0x00000100) /*!< Handlers running at priority -1 and -2 */
+#define SCB_CCR_STKALIGN ((uint32_t)0x00000200) /*!< On exception entry, the SP used prior to the exception is adjusted to be 8-byte aligned */
+
+/******************* Bit definition for SCB_SHPR register ********************/
+#define SCB_SHPR_PRI_N_Pos (0U)
+#define SCB_SHPR_PRI_N_Msk (0xFFU << SCB_SHPR_PRI_N_Pos) /*!< 0x000000FF */
+#define SCB_SHPR_PRI_N SCB_SHPR_PRI_N_Msk /*!< Priority of system handler 4,8, and 12. Mem Manage, reserved and Debug Monitor */
+#define SCB_SHPR_PRI_N1_Pos (8U)
+#define SCB_SHPR_PRI_N1_Msk (0xFFU << SCB_SHPR_PRI_N1_Pos) /*!< 0x0000FF00 */
+#define SCB_SHPR_PRI_N1 SCB_SHPR_PRI_N1_Msk /*!< Priority of system handler 5,9, and 13. Bus Fault, reserved and reserved */
+#define SCB_SHPR_PRI_N2_Pos (16U)
+#define SCB_SHPR_PRI_N2_Msk (0xFFU << SCB_SHPR_PRI_N2_Pos) /*!< 0x00FF0000 */
+#define SCB_SHPR_PRI_N2 SCB_SHPR_PRI_N2_Msk /*!< Priority of system handler 6,10, and 14. Usage Fault, reserved and PendSV */
+#define SCB_SHPR_PRI_N3_Pos (24U)
+#define SCB_SHPR_PRI_N3_Msk (0xFFU << SCB_SHPR_PRI_N3_Pos) /*!< 0xFF000000 */
+#define SCB_SHPR_PRI_N3 SCB_SHPR_PRI_N3_Msk /*!< Priority of system handler 7,11, and 15. Reserved, SVCall and SysTick */
+
+/****************** Bit definition for SCB_SHCSR register *******************/
+#define SCB_SHCSR_MEMFAULTACT ((uint32_t)0x00000001) /*!< MemManage is active */
+#define SCB_SHCSR_BUSFAULTACT ((uint32_t)0x00000002) /*!< BusFault is active */
+#define SCB_SHCSR_USGFAULTACT ((uint32_t)0x00000008) /*!< UsageFault is active */
+#define SCB_SHCSR_SVCALLACT ((uint32_t)0x00000080) /*!< SVCall is active */
+#define SCB_SHCSR_MONITORACT ((uint32_t)0x00000100) /*!< Monitor is active */
+#define SCB_SHCSR_PENDSVACT ((uint32_t)0x00000400) /*!< PendSV is active */
+#define SCB_SHCSR_SYSTICKACT ((uint32_t)0x00000800) /*!< SysTick is active */
+#define SCB_SHCSR_USGFAULTPENDED ((uint32_t)0x00001000) /*!< Usage Fault is pended */
+#define SCB_SHCSR_MEMFAULTPENDED ((uint32_t)0x00002000) /*!< MemManage is pended */
+#define SCB_SHCSR_BUSFAULTPENDED ((uint32_t)0x00004000) /*!< Bus Fault is pended */
+#define SCB_SHCSR_SVCALLPENDED ((uint32_t)0x00008000) /*!< SVCall is pended */
+#define SCB_SHCSR_MEMFAULTENA ((uint32_t)0x00010000) /*!< MemManage enable */
+#define SCB_SHCSR_BUSFAULTENA ((uint32_t)0x00020000) /*!< Bus Fault enable */
+#define SCB_SHCSR_USGFAULTENA ((uint32_t)0x00040000) /*!< UsageFault enable */
+
+/******************* Bit definition for SCB_CFSR register *******************/
+/*!< MFSR */
+#define SCB_CFSR_IACCVIOL_Pos (0U)
+#define SCB_CFSR_IACCVIOL_Msk (0x1U << SCB_CFSR_IACCVIOL_Pos) /*!< 0x00000001 */
+#define SCB_CFSR_IACCVIOL SCB_CFSR_IACCVIOL_Msk /*!< Instruction access violation */
+#define SCB_CFSR_DACCVIOL_Pos (1U)
+#define SCB_CFSR_DACCVIOL_Msk (0x1U << SCB_CFSR_DACCVIOL_Pos) /*!< 0x00000002 */
+#define SCB_CFSR_DACCVIOL SCB_CFSR_DACCVIOL_Msk /*!< Data access violation */
+#define SCB_CFSR_MUNSTKERR_Pos (3U)
+#define SCB_CFSR_MUNSTKERR_Msk (0x1U << SCB_CFSR_MUNSTKERR_Pos) /*!< 0x00000008 */
+#define SCB_CFSR_MUNSTKERR SCB_CFSR_MUNSTKERR_Msk /*!< Unstacking error */
+#define SCB_CFSR_MSTKERR_Pos (4U)
+#define SCB_CFSR_MSTKERR_Msk (0x1U << SCB_CFSR_MSTKERR_Pos) /*!< 0x00000010 */
+#define SCB_CFSR_MSTKERR SCB_CFSR_MSTKERR_Msk /*!< Stacking error */
+#define SCB_CFSR_MMARVALID_Pos (7U)
+#define SCB_CFSR_MMARVALID_Msk (0x1U << SCB_CFSR_MMARVALID_Pos) /*!< 0x00000080 */
+#define SCB_CFSR_MMARVALID SCB_CFSR_MMARVALID_Msk /*!< Memory Manage Address Register address valid flag */
+/*!< BFSR */
+#define SCB_CFSR_IBUSERR_Pos (8U)
+#define SCB_CFSR_IBUSERR_Msk (0x1U << SCB_CFSR_IBUSERR_Pos) /*!< 0x00000100 */
+#define SCB_CFSR_IBUSERR SCB_CFSR_IBUSERR_Msk /*!< Instruction bus error flag */
+#define SCB_CFSR_PRECISERR_Pos (9U)
+#define SCB_CFSR_PRECISERR_Msk (0x1U << SCB_CFSR_PRECISERR_Pos) /*!< 0x00000200 */
+#define SCB_CFSR_PRECISERR SCB_CFSR_PRECISERR_Msk /*!< Precise data bus error */
+#define SCB_CFSR_IMPRECISERR_Pos (10U)
+#define SCB_CFSR_IMPRECISERR_Msk (0x1U << SCB_CFSR_IMPRECISERR_Pos) /*!< 0x00000400 */
+#define SCB_CFSR_IMPRECISERR SCB_CFSR_IMPRECISERR_Msk /*!< Imprecise data bus error */
+#define SCB_CFSR_UNSTKERR_Pos (11U)
+#define SCB_CFSR_UNSTKERR_Msk (0x1U << SCB_CFSR_UNSTKERR_Pos) /*!< 0x00000800 */
+#define SCB_CFSR_UNSTKERR SCB_CFSR_UNSTKERR_Msk /*!< Unstacking error */
+#define SCB_CFSR_STKERR_Pos (12U)
+#define SCB_CFSR_STKERR_Msk (0x1U << SCB_CFSR_STKERR_Pos) /*!< 0x00001000 */
+#define SCB_CFSR_STKERR SCB_CFSR_STKERR_Msk /*!< Stacking error */
+#define SCB_CFSR_BFARVALID_Pos (15U)
+#define SCB_CFSR_BFARVALID_Msk (0x1U << SCB_CFSR_BFARVALID_Pos) /*!< 0x00008000 */
+#define SCB_CFSR_BFARVALID SCB_CFSR_BFARVALID_Msk /*!< Bus Fault Address Register address valid flag */
+/*!< UFSR */
+#define SCB_CFSR_UNDEFINSTR_Pos (16U)
+#define SCB_CFSR_UNDEFINSTR_Msk (0x1U << SCB_CFSR_UNDEFINSTR_Pos) /*!< 0x00010000 */
+#define SCB_CFSR_UNDEFINSTR SCB_CFSR_UNDEFINSTR_Msk /*!< The processor attempt to execute an undefined instruction */
+#define SCB_CFSR_INVSTATE_Pos (17U)
+#define SCB_CFSR_INVSTATE_Msk (0x1U << SCB_CFSR_INVSTATE_Pos) /*!< 0x00020000 */
+#define SCB_CFSR_INVSTATE SCB_CFSR_INVSTATE_Msk /*!< Invalid combination of EPSR and instruction */
+#define SCB_CFSR_INVPC_Pos (18U)
+#define SCB_CFSR_INVPC_Msk (0x1U << SCB_CFSR_INVPC_Pos) /*!< 0x00040000 */
+#define SCB_CFSR_INVPC SCB_CFSR_INVPC_Msk /*!< Attempt to load EXC_RETURN into pc illegally */
+#define SCB_CFSR_NOCP_Pos (19U)
+#define SCB_CFSR_NOCP_Msk (0x1U << SCB_CFSR_NOCP_Pos) /*!< 0x00080000 */
+#define SCB_CFSR_NOCP SCB_CFSR_NOCP_Msk /*!< Attempt to use a coprocessor instruction */
+#define SCB_CFSR_UNALIGNED_Pos (24U)
+#define SCB_CFSR_UNALIGNED_Msk (0x1U << SCB_CFSR_UNALIGNED_Pos) /*!< 0x01000000 */
+#define SCB_CFSR_UNALIGNED SCB_CFSR_UNALIGNED_Msk /*!< Fault occurs when there is an attempt to make an unaligned memory access */
+#define SCB_CFSR_DIVBYZERO_Pos (25U)
+#define SCB_CFSR_DIVBYZERO_Msk (0x1U << SCB_CFSR_DIVBYZERO_Pos) /*!< 0x02000000 */
+#define SCB_CFSR_DIVBYZERO SCB_CFSR_DIVBYZERO_Msk /*!< Fault occurs when SDIV or DIV instruction is used with a divisor of 0 */
+
+/******************* Bit definition for SCB_HFSR register *******************/
+#define SCB_HFSR_VECTTBL ((uint32_t)0x00000002) /*!< Fault occurs because of vector table read on exception processing */
+#define SCB_HFSR_FORCED ((uint32_t)0x40000000) /*!< Hard Fault activated when a configurable Fault was received and cannot activate */
+#define SCB_HFSR_DEBUGEVT ((uint32_t)0x80000000) /*!< Fault related to debug */
+
+/******************* Bit definition for SCB_DFSR register *******************/
+#define SCB_DFSR_HALTED ((uint32_t)0x00000001) /*!< Halt request flag */
+#define SCB_DFSR_BKPT ((uint32_t)0x00000002) /*!< BKPT flag */
+#define SCB_DFSR_DWTTRAP ((uint32_t)0x00000004) /*!< Data Watchpoint and Trace (DWT) flag */
+#define SCB_DFSR_VCATCH ((uint32_t)0x00000008) /*!< Vector catch flag */
+#define SCB_DFSR_EXTERNAL ((uint32_t)0x00000010) /*!< External debug request flag */
+
+/******************* Bit definition for SCB_MMFAR register ******************/
+#define SCB_MMFAR_ADDRESS_Pos (0U)
+#define SCB_MMFAR_ADDRESS_Msk (0xFFFFFFFFU << SCB_MMFAR_ADDRESS_Pos) /*!< 0xFFFFFFFF */
+#define SCB_MMFAR_ADDRESS SCB_MMFAR_ADDRESS_Msk /*!< Mem Manage fault address field */
+
+/******************* Bit definition for SCB_BFAR register *******************/
+#define SCB_BFAR_ADDRESS_Pos (0U)
+#define SCB_BFAR_ADDRESS_Msk (0xFFFFFFFFU << SCB_BFAR_ADDRESS_Pos) /*!< 0xFFFFFFFF */
+#define SCB_BFAR_ADDRESS SCB_BFAR_ADDRESS_Msk /*!< Bus fault address field */
+
+/******************* Bit definition for SCB_afsr register *******************/
+#define SCB_AFSR_IMPDEF_Pos (0U)
+#define SCB_AFSR_IMPDEF_Msk (0xFFFFFFFFU << SCB_AFSR_IMPDEF_Pos) /*!< 0xFFFFFFFF */
+#define SCB_AFSR_IMPDEF SCB_AFSR_IMPDEF_Msk /*!< Implementation defined */
+
+/******************************************************************************/
+/* */
+/* External Interrupt/Event Controller */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for EXTI_IMR register *******************/
+#define EXTI_IMR_MR0_Pos (0U)
+#define EXTI_IMR_MR0_Msk (0x1U << EXTI_IMR_MR0_Pos) /*!< 0x00000001 */
+#define EXTI_IMR_MR0 EXTI_IMR_MR0_Msk /*!< Interrupt Mask on line 0 */
+#define EXTI_IMR_MR1_Pos (1U)
+#define EXTI_IMR_MR1_Msk (0x1U << EXTI_IMR_MR1_Pos) /*!< 0x00000002 */
+#define EXTI_IMR_MR1 EXTI_IMR_MR1_Msk /*!< Interrupt Mask on line 1 */
+#define EXTI_IMR_MR2_Pos (2U)
+#define EXTI_IMR_MR2_Msk (0x1U << EXTI_IMR_MR2_Pos) /*!< 0x00000004 */
+#define EXTI_IMR_MR2 EXTI_IMR_MR2_Msk /*!< Interrupt Mask on line 2 */
+#define EXTI_IMR_MR3_Pos (3U)
+#define EXTI_IMR_MR3_Msk (0x1U << EXTI_IMR_MR3_Pos) /*!< 0x00000008 */
+#define EXTI_IMR_MR3 EXTI_IMR_MR3_Msk /*!< Interrupt Mask on line 3 */
+#define EXTI_IMR_MR4_Pos (4U)
+#define EXTI_IMR_MR4_Msk (0x1U << EXTI_IMR_MR4_Pos) /*!< 0x00000010 */
+#define EXTI_IMR_MR4 EXTI_IMR_MR4_Msk /*!< Interrupt Mask on line 4 */
+#define EXTI_IMR_MR5_Pos (5U)
+#define EXTI_IMR_MR5_Msk (0x1U << EXTI_IMR_MR5_Pos) /*!< 0x00000020 */
+#define EXTI_IMR_MR5 EXTI_IMR_MR5_Msk /*!< Interrupt Mask on line 5 */
+#define EXTI_IMR_MR6_Pos (6U)
+#define EXTI_IMR_MR6_Msk (0x1U << EXTI_IMR_MR6_Pos) /*!< 0x00000040 */
+#define EXTI_IMR_MR6 EXTI_IMR_MR6_Msk /*!< Interrupt Mask on line 6 */
+#define EXTI_IMR_MR7_Pos (7U)
+#define EXTI_IMR_MR7_Msk (0x1U << EXTI_IMR_MR7_Pos) /*!< 0x00000080 */
+#define EXTI_IMR_MR7 EXTI_IMR_MR7_Msk /*!< Interrupt Mask on line 7 */
+#define EXTI_IMR_MR8_Pos (8U)
+#define EXTI_IMR_MR8_Msk (0x1U << EXTI_IMR_MR8_Pos) /*!< 0x00000100 */
+#define EXTI_IMR_MR8 EXTI_IMR_MR8_Msk /*!< Interrupt Mask on line 8 */
+#define EXTI_IMR_MR9_Pos (9U)
+#define EXTI_IMR_MR9_Msk (0x1U << EXTI_IMR_MR9_Pos) /*!< 0x00000200 */
+#define EXTI_IMR_MR9 EXTI_IMR_MR9_Msk /*!< Interrupt Mask on line 9 */
+#define EXTI_IMR_MR10_Pos (10U)
+#define EXTI_IMR_MR10_Msk (0x1U << EXTI_IMR_MR10_Pos) /*!< 0x00000400 */
+#define EXTI_IMR_MR10 EXTI_IMR_MR10_Msk /*!< Interrupt Mask on line 10 */
+#define EXTI_IMR_MR11_Pos (11U)
+#define EXTI_IMR_MR11_Msk (0x1U << EXTI_IMR_MR11_Pos) /*!< 0x00000800 */
+#define EXTI_IMR_MR11 EXTI_IMR_MR11_Msk /*!< Interrupt Mask on line 11 */
+#define EXTI_IMR_MR12_Pos (12U)
+#define EXTI_IMR_MR12_Msk (0x1U << EXTI_IMR_MR12_Pos) /*!< 0x00001000 */
+#define EXTI_IMR_MR12 EXTI_IMR_MR12_Msk /*!< Interrupt Mask on line 12 */
+#define EXTI_IMR_MR13_Pos (13U)
+#define EXTI_IMR_MR13_Msk (0x1U << EXTI_IMR_MR13_Pos) /*!< 0x00002000 */
+#define EXTI_IMR_MR13 EXTI_IMR_MR13_Msk /*!< Interrupt Mask on line 13 */
+#define EXTI_IMR_MR14_Pos (14U)
+#define EXTI_IMR_MR14_Msk (0x1U << EXTI_IMR_MR14_Pos) /*!< 0x00004000 */
+#define EXTI_IMR_MR14 EXTI_IMR_MR14_Msk /*!< Interrupt Mask on line 14 */
+#define EXTI_IMR_MR15_Pos (15U)
+#define EXTI_IMR_MR15_Msk (0x1U << EXTI_IMR_MR15_Pos) /*!< 0x00008000 */
+#define EXTI_IMR_MR15 EXTI_IMR_MR15_Msk /*!< Interrupt Mask on line 15 */
+#define EXTI_IMR_MR16_Pos (16U)
+#define EXTI_IMR_MR16_Msk (0x1U << EXTI_IMR_MR16_Pos) /*!< 0x00010000 */
+#define EXTI_IMR_MR16 EXTI_IMR_MR16_Msk /*!< Interrupt Mask on line 16 */
+#define EXTI_IMR_MR17_Pos (17U)
+#define EXTI_IMR_MR17_Msk (0x1U << EXTI_IMR_MR17_Pos) /*!< 0x00020000 */
+#define EXTI_IMR_MR17 EXTI_IMR_MR17_Msk /*!< Interrupt Mask on line 17 */
+#define EXTI_IMR_MR18_Pos (18U)
+#define EXTI_IMR_MR18_Msk (0x1U << EXTI_IMR_MR18_Pos) /*!< 0x00040000 */
+#define EXTI_IMR_MR18 EXTI_IMR_MR18_Msk /*!< Interrupt Mask on line 18 */
+#define EXTI_IMR_MR19_Pos (19U)
+#define EXTI_IMR_MR19_Msk (0x1U << EXTI_IMR_MR19_Pos) /*!< 0x00080000 */
+#define EXTI_IMR_MR19 EXTI_IMR_MR19_Msk /*!< Interrupt Mask on line 19 */
+
+/* References Defines */
+#define EXTI_IMR_IM0 EXTI_IMR_MR0
+#define EXTI_IMR_IM1 EXTI_IMR_MR1
+#define EXTI_IMR_IM2 EXTI_IMR_MR2
+#define EXTI_IMR_IM3 EXTI_IMR_MR3
+#define EXTI_IMR_IM4 EXTI_IMR_MR4
+#define EXTI_IMR_IM5 EXTI_IMR_MR5
+#define EXTI_IMR_IM6 EXTI_IMR_MR6
+#define EXTI_IMR_IM7 EXTI_IMR_MR7
+#define EXTI_IMR_IM8 EXTI_IMR_MR8
+#define EXTI_IMR_IM9 EXTI_IMR_MR9
+#define EXTI_IMR_IM10 EXTI_IMR_MR10
+#define EXTI_IMR_IM11 EXTI_IMR_MR11
+#define EXTI_IMR_IM12 EXTI_IMR_MR12
+#define EXTI_IMR_IM13 EXTI_IMR_MR13
+#define EXTI_IMR_IM14 EXTI_IMR_MR14
+#define EXTI_IMR_IM15 EXTI_IMR_MR15
+#define EXTI_IMR_IM16 EXTI_IMR_MR16
+#define EXTI_IMR_IM17 EXTI_IMR_MR17
+#define EXTI_IMR_IM18 EXTI_IMR_MR18
+#define EXTI_IMR_IM19 EXTI_IMR_MR19
+
+/******************* Bit definition for EXTI_EMR register *******************/
+#define EXTI_EMR_MR0_Pos (0U)
+#define EXTI_EMR_MR0_Msk (0x1U << EXTI_EMR_MR0_Pos) /*!< 0x00000001 */
+#define EXTI_EMR_MR0 EXTI_EMR_MR0_Msk /*!< Event Mask on line 0 */
+#define EXTI_EMR_MR1_Pos (1U)
+#define EXTI_EMR_MR1_Msk (0x1U << EXTI_EMR_MR1_Pos) /*!< 0x00000002 */
+#define EXTI_EMR_MR1 EXTI_EMR_MR1_Msk /*!< Event Mask on line 1 */
+#define EXTI_EMR_MR2_Pos (2U)
+#define EXTI_EMR_MR2_Msk (0x1U << EXTI_EMR_MR2_Pos) /*!< 0x00000004 */
+#define EXTI_EMR_MR2 EXTI_EMR_MR2_Msk /*!< Event Mask on line 2 */
+#define EXTI_EMR_MR3_Pos (3U)
+#define EXTI_EMR_MR3_Msk (0x1U << EXTI_EMR_MR3_Pos) /*!< 0x00000008 */
+#define EXTI_EMR_MR3 EXTI_EMR_MR3_Msk /*!< Event Mask on line 3 */
+#define EXTI_EMR_MR4_Pos (4U)
+#define EXTI_EMR_MR4_Msk (0x1U << EXTI_EMR_MR4_Pos) /*!< 0x00000010 */
+#define EXTI_EMR_MR4 EXTI_EMR_MR4_Msk /*!< Event Mask on line 4 */
+#define EXTI_EMR_MR5_Pos (5U)
+#define EXTI_EMR_MR5_Msk (0x1U << EXTI_EMR_MR5_Pos) /*!< 0x00000020 */
+#define EXTI_EMR_MR5 EXTI_EMR_MR5_Msk /*!< Event Mask on line 5 */
+#define EXTI_EMR_MR6_Pos (6U)
+#define EXTI_EMR_MR6_Msk (0x1U << EXTI_EMR_MR6_Pos) /*!< 0x00000040 */
+#define EXTI_EMR_MR6 EXTI_EMR_MR6_Msk /*!< Event Mask on line 6 */
+#define EXTI_EMR_MR7_Pos (7U)
+#define EXTI_EMR_MR7_Msk (0x1U << EXTI_EMR_MR7_Pos) /*!< 0x00000080 */
+#define EXTI_EMR_MR7 EXTI_EMR_MR7_Msk /*!< Event Mask on line 7 */
+#define EXTI_EMR_MR8_Pos (8U)
+#define EXTI_EMR_MR8_Msk (0x1U << EXTI_EMR_MR8_Pos) /*!< 0x00000100 */
+#define EXTI_EMR_MR8 EXTI_EMR_MR8_Msk /*!< Event Mask on line 8 */
+#define EXTI_EMR_MR9_Pos (9U)
+#define EXTI_EMR_MR9_Msk (0x1U << EXTI_EMR_MR9_Pos) /*!< 0x00000200 */
+#define EXTI_EMR_MR9 EXTI_EMR_MR9_Msk /*!< Event Mask on line 9 */
+#define EXTI_EMR_MR10_Pos (10U)
+#define EXTI_EMR_MR10_Msk (0x1U << EXTI_EMR_MR10_Pos) /*!< 0x00000400 */
+#define EXTI_EMR_MR10 EXTI_EMR_MR10_Msk /*!< Event Mask on line 10 */
+#define EXTI_EMR_MR11_Pos (11U)
+#define EXTI_EMR_MR11_Msk (0x1U << EXTI_EMR_MR11_Pos) /*!< 0x00000800 */
+#define EXTI_EMR_MR11 EXTI_EMR_MR11_Msk /*!< Event Mask on line 11 */
+#define EXTI_EMR_MR12_Pos (12U)
+#define EXTI_EMR_MR12_Msk (0x1U << EXTI_EMR_MR12_Pos) /*!< 0x00001000 */
+#define EXTI_EMR_MR12 EXTI_EMR_MR12_Msk /*!< Event Mask on line 12 */
+#define EXTI_EMR_MR13_Pos (13U)
+#define EXTI_EMR_MR13_Msk (0x1U << EXTI_EMR_MR13_Pos) /*!< 0x00002000 */
+#define EXTI_EMR_MR13 EXTI_EMR_MR13_Msk /*!< Event Mask on line 13 */
+#define EXTI_EMR_MR14_Pos (14U)
+#define EXTI_EMR_MR14_Msk (0x1U << EXTI_EMR_MR14_Pos) /*!< 0x00004000 */
+#define EXTI_EMR_MR14 EXTI_EMR_MR14_Msk /*!< Event Mask on line 14 */
+#define EXTI_EMR_MR15_Pos (15U)
+#define EXTI_EMR_MR15_Msk (0x1U << EXTI_EMR_MR15_Pos) /*!< 0x00008000 */
+#define EXTI_EMR_MR15 EXTI_EMR_MR15_Msk /*!< Event Mask on line 15 */
+#define EXTI_EMR_MR16_Pos (16U)
+#define EXTI_EMR_MR16_Msk (0x1U << EXTI_EMR_MR16_Pos) /*!< 0x00010000 */
+#define EXTI_EMR_MR16 EXTI_EMR_MR16_Msk /*!< Event Mask on line 16 */
+#define EXTI_EMR_MR17_Pos (17U)
+#define EXTI_EMR_MR17_Msk (0x1U << EXTI_EMR_MR17_Pos) /*!< 0x00020000 */
+#define EXTI_EMR_MR17 EXTI_EMR_MR17_Msk /*!< Event Mask on line 17 */
+#define EXTI_EMR_MR18_Pos (18U)
+#define EXTI_EMR_MR18_Msk (0x1U << EXTI_EMR_MR18_Pos) /*!< 0x00040000 */
+#define EXTI_EMR_MR18 EXTI_EMR_MR18_Msk /*!< Event Mask on line 18 */
+#define EXTI_EMR_MR19_Pos (19U)
+#define EXTI_EMR_MR19_Msk (0x1U << EXTI_EMR_MR19_Pos) /*!< 0x00080000 */
+#define EXTI_EMR_MR19 EXTI_EMR_MR19_Msk /*!< Event Mask on line 19 */
+
+/* References Defines */
+#define EXTI_EMR_EM0 EXTI_EMR_MR0
+#define EXTI_EMR_EM1 EXTI_EMR_MR1
+#define EXTI_EMR_EM2 EXTI_EMR_MR2
+#define EXTI_EMR_EM3 EXTI_EMR_MR3
+#define EXTI_EMR_EM4 EXTI_EMR_MR4
+#define EXTI_EMR_EM5 EXTI_EMR_MR5
+#define EXTI_EMR_EM6 EXTI_EMR_MR6
+#define EXTI_EMR_EM7 EXTI_EMR_MR7
+#define EXTI_EMR_EM8 EXTI_EMR_MR8
+#define EXTI_EMR_EM9 EXTI_EMR_MR9
+#define EXTI_EMR_EM10 EXTI_EMR_MR10
+#define EXTI_EMR_EM11 EXTI_EMR_MR11
+#define EXTI_EMR_EM12 EXTI_EMR_MR12
+#define EXTI_EMR_EM13 EXTI_EMR_MR13
+#define EXTI_EMR_EM14 EXTI_EMR_MR14
+#define EXTI_EMR_EM15 EXTI_EMR_MR15
+#define EXTI_EMR_EM16 EXTI_EMR_MR16
+#define EXTI_EMR_EM17 EXTI_EMR_MR17
+#define EXTI_EMR_EM18 EXTI_EMR_MR18
+#define EXTI_EMR_EM19 EXTI_EMR_MR19
+
+/****************** Bit definition for EXTI_RTSR register *******************/
+#define EXTI_RTSR_TR0_Pos (0U)
+#define EXTI_RTSR_TR0_Msk (0x1U << EXTI_RTSR_TR0_Pos) /*!< 0x00000001 */
+#define EXTI_RTSR_TR0 EXTI_RTSR_TR0_Msk /*!< Rising trigger event configuration bit of line 0 */
+#define EXTI_RTSR_TR1_Pos (1U)
+#define EXTI_RTSR_TR1_Msk (0x1U << EXTI_RTSR_TR1_Pos) /*!< 0x00000002 */
+#define EXTI_RTSR_TR1 EXTI_RTSR_TR1_Msk /*!< Rising trigger event configuration bit of line 1 */
+#define EXTI_RTSR_TR2_Pos (2U)
+#define EXTI_RTSR_TR2_Msk (0x1U << EXTI_RTSR_TR2_Pos) /*!< 0x00000004 */
+#define EXTI_RTSR_TR2 EXTI_RTSR_TR2_Msk /*!< Rising trigger event configuration bit of line 2 */
+#define EXTI_RTSR_TR3_Pos (3U)
+#define EXTI_RTSR_TR3_Msk (0x1U << EXTI_RTSR_TR3_Pos) /*!< 0x00000008 */
+#define EXTI_RTSR_TR3 EXTI_RTSR_TR3_Msk /*!< Rising trigger event configuration bit of line 3 */
+#define EXTI_RTSR_TR4_Pos (4U)
+#define EXTI_RTSR_TR4_Msk (0x1U << EXTI_RTSR_TR4_Pos) /*!< 0x00000010 */
+#define EXTI_RTSR_TR4 EXTI_RTSR_TR4_Msk /*!< Rising trigger event configuration bit of line 4 */
+#define EXTI_RTSR_TR5_Pos (5U)
+#define EXTI_RTSR_TR5_Msk (0x1U << EXTI_RTSR_TR5_Pos) /*!< 0x00000020 */
+#define EXTI_RTSR_TR5 EXTI_RTSR_TR5_Msk /*!< Rising trigger event configuration bit of line 5 */
+#define EXTI_RTSR_TR6_Pos (6U)
+#define EXTI_RTSR_TR6_Msk (0x1U << EXTI_RTSR_TR6_Pos) /*!< 0x00000040 */
+#define EXTI_RTSR_TR6 EXTI_RTSR_TR6_Msk /*!< Rising trigger event configuration bit of line 6 */
+#define EXTI_RTSR_TR7_Pos (7U)
+#define EXTI_RTSR_TR7_Msk (0x1U << EXTI_RTSR_TR7_Pos) /*!< 0x00000080 */
+#define EXTI_RTSR_TR7 EXTI_RTSR_TR7_Msk /*!< Rising trigger event configuration bit of line 7 */
+#define EXTI_RTSR_TR8_Pos (8U)
+#define EXTI_RTSR_TR8_Msk (0x1U << EXTI_RTSR_TR8_Pos) /*!< 0x00000100 */
+#define EXTI_RTSR_TR8 EXTI_RTSR_TR8_Msk /*!< Rising trigger event configuration bit of line 8 */
+#define EXTI_RTSR_TR9_Pos (9U)
+#define EXTI_RTSR_TR9_Msk (0x1U << EXTI_RTSR_TR9_Pos) /*!< 0x00000200 */
+#define EXTI_RTSR_TR9 EXTI_RTSR_TR9_Msk /*!< Rising trigger event configuration bit of line 9 */
+#define EXTI_RTSR_TR10_Pos (10U)
+#define EXTI_RTSR_TR10_Msk (0x1U << EXTI_RTSR_TR10_Pos) /*!< 0x00000400 */
+#define EXTI_RTSR_TR10 EXTI_RTSR_TR10_Msk /*!< Rising trigger event configuration bit of line 10 */
+#define EXTI_RTSR_TR11_Pos (11U)
+#define EXTI_RTSR_TR11_Msk (0x1U << EXTI_RTSR_TR11_Pos) /*!< 0x00000800 */
+#define EXTI_RTSR_TR11 EXTI_RTSR_TR11_Msk /*!< Rising trigger event configuration bit of line 11 */
+#define EXTI_RTSR_TR12_Pos (12U)
+#define EXTI_RTSR_TR12_Msk (0x1U << EXTI_RTSR_TR12_Pos) /*!< 0x00001000 */
+#define EXTI_RTSR_TR12 EXTI_RTSR_TR12_Msk /*!< Rising trigger event configuration bit of line 12 */
+#define EXTI_RTSR_TR13_Pos (13U)
+#define EXTI_RTSR_TR13_Msk (0x1U << EXTI_RTSR_TR13_Pos) /*!< 0x00002000 */
+#define EXTI_RTSR_TR13 EXTI_RTSR_TR13_Msk /*!< Rising trigger event configuration bit of line 13 */
+#define EXTI_RTSR_TR14_Pos (14U)
+#define EXTI_RTSR_TR14_Msk (0x1U << EXTI_RTSR_TR14_Pos) /*!< 0x00004000 */
+#define EXTI_RTSR_TR14 EXTI_RTSR_TR14_Msk /*!< Rising trigger event configuration bit of line 14 */
+#define EXTI_RTSR_TR15_Pos (15U)
+#define EXTI_RTSR_TR15_Msk (0x1U << EXTI_RTSR_TR15_Pos) /*!< 0x00008000 */
+#define EXTI_RTSR_TR15 EXTI_RTSR_TR15_Msk /*!< Rising trigger event configuration bit of line 15 */
+#define EXTI_RTSR_TR16_Pos (16U)
+#define EXTI_RTSR_TR16_Msk (0x1U << EXTI_RTSR_TR16_Pos) /*!< 0x00010000 */
+#define EXTI_RTSR_TR16 EXTI_RTSR_TR16_Msk /*!< Rising trigger event configuration bit of line 16 */
+#define EXTI_RTSR_TR17_Pos (17U)
+#define EXTI_RTSR_TR17_Msk (0x1U << EXTI_RTSR_TR17_Pos) /*!< 0x00020000 */
+#define EXTI_RTSR_TR17 EXTI_RTSR_TR17_Msk /*!< Rising trigger event configuration bit of line 17 */
+#define EXTI_RTSR_TR18_Pos (18U)
+#define EXTI_RTSR_TR18_Msk (0x1U << EXTI_RTSR_TR18_Pos) /*!< 0x00040000 */
+#define EXTI_RTSR_TR18 EXTI_RTSR_TR18_Msk /*!< Rising trigger event configuration bit of line 18 */
+#define EXTI_RTSR_TR19_Pos (19U)
+#define EXTI_RTSR_TR19_Msk (0x1U << EXTI_RTSR_TR19_Pos) /*!< 0x00080000 */
+#define EXTI_RTSR_TR19 EXTI_RTSR_TR19_Msk /*!< Rising trigger event configuration bit of line 19 */
+
+/* References Defines */
+#define EXTI_RTSR_RT0 EXTI_RTSR_TR0
+#define EXTI_RTSR_RT1 EXTI_RTSR_TR1
+#define EXTI_RTSR_RT2 EXTI_RTSR_TR2
+#define EXTI_RTSR_RT3 EXTI_RTSR_TR3
+#define EXTI_RTSR_RT4 EXTI_RTSR_TR4
+#define EXTI_RTSR_RT5 EXTI_RTSR_TR5
+#define EXTI_RTSR_RT6 EXTI_RTSR_TR6
+#define EXTI_RTSR_RT7 EXTI_RTSR_TR7
+#define EXTI_RTSR_RT8 EXTI_RTSR_TR8
+#define EXTI_RTSR_RT9 EXTI_RTSR_TR9
+#define EXTI_RTSR_RT10 EXTI_RTSR_TR10
+#define EXTI_RTSR_RT11 EXTI_RTSR_TR11
+#define EXTI_RTSR_RT12 EXTI_RTSR_TR12
+#define EXTI_RTSR_RT13 EXTI_RTSR_TR13
+#define EXTI_RTSR_RT14 EXTI_RTSR_TR14
+#define EXTI_RTSR_RT15 EXTI_RTSR_TR15
+#define EXTI_RTSR_RT16 EXTI_RTSR_TR16
+#define EXTI_RTSR_RT17 EXTI_RTSR_TR17
+#define EXTI_RTSR_RT18 EXTI_RTSR_TR18
+#define EXTI_RTSR_RT19 EXTI_RTSR_TR19
+
+/****************** Bit definition for EXTI_FTSR register *******************/
+#define EXTI_FTSR_TR0_Pos (0U)
+#define EXTI_FTSR_TR0_Msk (0x1U << EXTI_FTSR_TR0_Pos) /*!< 0x00000001 */
+#define EXTI_FTSR_TR0 EXTI_FTSR_TR0_Msk /*!< Falling trigger event configuration bit of line 0 */
+#define EXTI_FTSR_TR1_Pos (1U)
+#define EXTI_FTSR_TR1_Msk (0x1U << EXTI_FTSR_TR1_Pos) /*!< 0x00000002 */
+#define EXTI_FTSR_TR1 EXTI_FTSR_TR1_Msk /*!< Falling trigger event configuration bit of line 1 */
+#define EXTI_FTSR_TR2_Pos (2U)
+#define EXTI_FTSR_TR2_Msk (0x1U << EXTI_FTSR_TR2_Pos) /*!< 0x00000004 */
+#define EXTI_FTSR_TR2 EXTI_FTSR_TR2_Msk /*!< Falling trigger event configuration bit of line 2 */
+#define EXTI_FTSR_TR3_Pos (3U)
+#define EXTI_FTSR_TR3_Msk (0x1U << EXTI_FTSR_TR3_Pos) /*!< 0x00000008 */
+#define EXTI_FTSR_TR3 EXTI_FTSR_TR3_Msk /*!< Falling trigger event configuration bit of line 3 */
+#define EXTI_FTSR_TR4_Pos (4U)
+#define EXTI_FTSR_TR4_Msk (0x1U << EXTI_FTSR_TR4_Pos) /*!< 0x00000010 */
+#define EXTI_FTSR_TR4 EXTI_FTSR_TR4_Msk /*!< Falling trigger event configuration bit of line 4 */
+#define EXTI_FTSR_TR5_Pos (5U)
+#define EXTI_FTSR_TR5_Msk (0x1U << EXTI_FTSR_TR5_Pos) /*!< 0x00000020 */
+#define EXTI_FTSR_TR5 EXTI_FTSR_TR5_Msk /*!< Falling trigger event configuration bit of line 5 */
+#define EXTI_FTSR_TR6_Pos (6U)
+#define EXTI_FTSR_TR6_Msk (0x1U << EXTI_FTSR_TR6_Pos) /*!< 0x00000040 */
+#define EXTI_FTSR_TR6 EXTI_FTSR_TR6_Msk /*!< Falling trigger event configuration bit of line 6 */
+#define EXTI_FTSR_TR7_Pos (7U)
+#define EXTI_FTSR_TR7_Msk (0x1U << EXTI_FTSR_TR7_Pos) /*!< 0x00000080 */
+#define EXTI_FTSR_TR7 EXTI_FTSR_TR7_Msk /*!< Falling trigger event configuration bit of line 7 */
+#define EXTI_FTSR_TR8_Pos (8U)
+#define EXTI_FTSR_TR8_Msk (0x1U << EXTI_FTSR_TR8_Pos) /*!< 0x00000100 */
+#define EXTI_FTSR_TR8 EXTI_FTSR_TR8_Msk /*!< Falling trigger event configuration bit of line 8 */
+#define EXTI_FTSR_TR9_Pos (9U)
+#define EXTI_FTSR_TR9_Msk (0x1U << EXTI_FTSR_TR9_Pos) /*!< 0x00000200 */
+#define EXTI_FTSR_TR9 EXTI_FTSR_TR9_Msk /*!< Falling trigger event configuration bit of line 9 */
+#define EXTI_FTSR_TR10_Pos (10U)
+#define EXTI_FTSR_TR10_Msk (0x1U << EXTI_FTSR_TR10_Pos) /*!< 0x00000400 */
+#define EXTI_FTSR_TR10 EXTI_FTSR_TR10_Msk /*!< Falling trigger event configuration bit of line 10 */
+#define EXTI_FTSR_TR11_Pos (11U)
+#define EXTI_FTSR_TR11_Msk (0x1U << EXTI_FTSR_TR11_Pos) /*!< 0x00000800 */
+#define EXTI_FTSR_TR11 EXTI_FTSR_TR11_Msk /*!< Falling trigger event configuration bit of line 11 */
+#define EXTI_FTSR_TR12_Pos (12U)
+#define EXTI_FTSR_TR12_Msk (0x1U << EXTI_FTSR_TR12_Pos) /*!< 0x00001000 */
+#define EXTI_FTSR_TR12 EXTI_FTSR_TR12_Msk /*!< Falling trigger event configuration bit of line 12 */
+#define EXTI_FTSR_TR13_Pos (13U)
+#define EXTI_FTSR_TR13_Msk (0x1U << EXTI_FTSR_TR13_Pos) /*!< 0x00002000 */
+#define EXTI_FTSR_TR13 EXTI_FTSR_TR13_Msk /*!< Falling trigger event configuration bit of line 13 */
+#define EXTI_FTSR_TR14_Pos (14U)
+#define EXTI_FTSR_TR14_Msk (0x1U << EXTI_FTSR_TR14_Pos) /*!< 0x00004000 */
+#define EXTI_FTSR_TR14 EXTI_FTSR_TR14_Msk /*!< Falling trigger event configuration bit of line 14 */
+#define EXTI_FTSR_TR15_Pos (15U)
+#define EXTI_FTSR_TR15_Msk (0x1U << EXTI_FTSR_TR15_Pos) /*!< 0x00008000 */
+#define EXTI_FTSR_TR15 EXTI_FTSR_TR15_Msk /*!< Falling trigger event configuration bit of line 15 */
+#define EXTI_FTSR_TR16_Pos (16U)
+#define EXTI_FTSR_TR16_Msk (0x1U << EXTI_FTSR_TR16_Pos) /*!< 0x00010000 */
+#define EXTI_FTSR_TR16 EXTI_FTSR_TR16_Msk /*!< Falling trigger event configuration bit of line 16 */
+#define EXTI_FTSR_TR17_Pos (17U)
+#define EXTI_FTSR_TR17_Msk (0x1U << EXTI_FTSR_TR17_Pos) /*!< 0x00020000 */
+#define EXTI_FTSR_TR17 EXTI_FTSR_TR17_Msk /*!< Falling trigger event configuration bit of line 17 */
+#define EXTI_FTSR_TR18_Pos (18U)
+#define EXTI_FTSR_TR18_Msk (0x1U << EXTI_FTSR_TR18_Pos) /*!< 0x00040000 */
+#define EXTI_FTSR_TR18 EXTI_FTSR_TR18_Msk /*!< Falling trigger event configuration bit of line 18 */
+#define EXTI_FTSR_TR19_Pos (19U)
+#define EXTI_FTSR_TR19_Msk (0x1U << EXTI_FTSR_TR19_Pos) /*!< 0x00080000 */
+#define EXTI_FTSR_TR19 EXTI_FTSR_TR19_Msk /*!< Falling trigger event configuration bit of line 19 */
+
+/* References Defines */
+#define EXTI_FTSR_FT0 EXTI_FTSR_TR0
+#define EXTI_FTSR_FT1 EXTI_FTSR_TR1
+#define EXTI_FTSR_FT2 EXTI_FTSR_TR2
+#define EXTI_FTSR_FT3 EXTI_FTSR_TR3
+#define EXTI_FTSR_FT4 EXTI_FTSR_TR4
+#define EXTI_FTSR_FT5 EXTI_FTSR_TR5
+#define EXTI_FTSR_FT6 EXTI_FTSR_TR6
+#define EXTI_FTSR_FT7 EXTI_FTSR_TR7
+#define EXTI_FTSR_FT8 EXTI_FTSR_TR8
+#define EXTI_FTSR_FT9 EXTI_FTSR_TR9
+#define EXTI_FTSR_FT10 EXTI_FTSR_TR10
+#define EXTI_FTSR_FT11 EXTI_FTSR_TR11
+#define EXTI_FTSR_FT12 EXTI_FTSR_TR12
+#define EXTI_FTSR_FT13 EXTI_FTSR_TR13
+#define EXTI_FTSR_FT14 EXTI_FTSR_TR14
+#define EXTI_FTSR_FT15 EXTI_FTSR_TR15
+#define EXTI_FTSR_FT16 EXTI_FTSR_TR16
+#define EXTI_FTSR_FT17 EXTI_FTSR_TR17
+#define EXTI_FTSR_FT18 EXTI_FTSR_TR18
+#define EXTI_FTSR_FT19 EXTI_FTSR_TR19
+
+/****************** Bit definition for EXTI_SWIER register ******************/
+#define EXTI_SWIER_SWIER0_Pos (0U)
+#define EXTI_SWIER_SWIER0_Msk (0x1U << EXTI_SWIER_SWIER0_Pos) /*!< 0x00000001 */
+#define EXTI_SWIER_SWIER0 EXTI_SWIER_SWIER0_Msk /*!< Software Interrupt on line 0 */
+#define EXTI_SWIER_SWIER1_Pos (1U)
+#define EXTI_SWIER_SWIER1_Msk (0x1U << EXTI_SWIER_SWIER1_Pos) /*!< 0x00000002 */
+#define EXTI_SWIER_SWIER1 EXTI_SWIER_SWIER1_Msk /*!< Software Interrupt on line 1 */
+#define EXTI_SWIER_SWIER2_Pos (2U)
+#define EXTI_SWIER_SWIER2_Msk (0x1U << EXTI_SWIER_SWIER2_Pos) /*!< 0x00000004 */
+#define EXTI_SWIER_SWIER2 EXTI_SWIER_SWIER2_Msk /*!< Software Interrupt on line 2 */
+#define EXTI_SWIER_SWIER3_Pos (3U)
+#define EXTI_SWIER_SWIER3_Msk (0x1U << EXTI_SWIER_SWIER3_Pos) /*!< 0x00000008 */
+#define EXTI_SWIER_SWIER3 EXTI_SWIER_SWIER3_Msk /*!< Software Interrupt on line 3 */
+#define EXTI_SWIER_SWIER4_Pos (4U)
+#define EXTI_SWIER_SWIER4_Msk (0x1U << EXTI_SWIER_SWIER4_Pos) /*!< 0x00000010 */
+#define EXTI_SWIER_SWIER4 EXTI_SWIER_SWIER4_Msk /*!< Software Interrupt on line 4 */
+#define EXTI_SWIER_SWIER5_Pos (5U)
+#define EXTI_SWIER_SWIER5_Msk (0x1U << EXTI_SWIER_SWIER5_Pos) /*!< 0x00000020 */
+#define EXTI_SWIER_SWIER5 EXTI_SWIER_SWIER5_Msk /*!< Software Interrupt on line 5 */
+#define EXTI_SWIER_SWIER6_Pos (6U)
+#define EXTI_SWIER_SWIER6_Msk (0x1U << EXTI_SWIER_SWIER6_Pos) /*!< 0x00000040 */
+#define EXTI_SWIER_SWIER6 EXTI_SWIER_SWIER6_Msk /*!< Software Interrupt on line 6 */
+#define EXTI_SWIER_SWIER7_Pos (7U)
+#define EXTI_SWIER_SWIER7_Msk (0x1U << EXTI_SWIER_SWIER7_Pos) /*!< 0x00000080 */
+#define EXTI_SWIER_SWIER7 EXTI_SWIER_SWIER7_Msk /*!< Software Interrupt on line 7 */
+#define EXTI_SWIER_SWIER8_Pos (8U)
+#define EXTI_SWIER_SWIER8_Msk (0x1U << EXTI_SWIER_SWIER8_Pos) /*!< 0x00000100 */
+#define EXTI_SWIER_SWIER8 EXTI_SWIER_SWIER8_Msk /*!< Software Interrupt on line 8 */
+#define EXTI_SWIER_SWIER9_Pos (9U)
+#define EXTI_SWIER_SWIER9_Msk (0x1U << EXTI_SWIER_SWIER9_Pos) /*!< 0x00000200 */
+#define EXTI_SWIER_SWIER9 EXTI_SWIER_SWIER9_Msk /*!< Software Interrupt on line 9 */
+#define EXTI_SWIER_SWIER10_Pos (10U)
+#define EXTI_SWIER_SWIER10_Msk (0x1U << EXTI_SWIER_SWIER10_Pos) /*!< 0x00000400 */
+#define EXTI_SWIER_SWIER10 EXTI_SWIER_SWIER10_Msk /*!< Software Interrupt on line 10 */
+#define EXTI_SWIER_SWIER11_Pos (11U)
+#define EXTI_SWIER_SWIER11_Msk (0x1U << EXTI_SWIER_SWIER11_Pos) /*!< 0x00000800 */
+#define EXTI_SWIER_SWIER11 EXTI_SWIER_SWIER11_Msk /*!< Software Interrupt on line 11 */
+#define EXTI_SWIER_SWIER12_Pos (12U)
+#define EXTI_SWIER_SWIER12_Msk (0x1U << EXTI_SWIER_SWIER12_Pos) /*!< 0x00001000 */
+#define EXTI_SWIER_SWIER12 EXTI_SWIER_SWIER12_Msk /*!< Software Interrupt on line 12 */
+#define EXTI_SWIER_SWIER13_Pos (13U)
+#define EXTI_SWIER_SWIER13_Msk (0x1U << EXTI_SWIER_SWIER13_Pos) /*!< 0x00002000 */
+#define EXTI_SWIER_SWIER13 EXTI_SWIER_SWIER13_Msk /*!< Software Interrupt on line 13 */
+#define EXTI_SWIER_SWIER14_Pos (14U)
+#define EXTI_SWIER_SWIER14_Msk (0x1U << EXTI_SWIER_SWIER14_Pos) /*!< 0x00004000 */
+#define EXTI_SWIER_SWIER14 EXTI_SWIER_SWIER14_Msk /*!< Software Interrupt on line 14 */
+#define EXTI_SWIER_SWIER15_Pos (15U)
+#define EXTI_SWIER_SWIER15_Msk (0x1U << EXTI_SWIER_SWIER15_Pos) /*!< 0x00008000 */
+#define EXTI_SWIER_SWIER15 EXTI_SWIER_SWIER15_Msk /*!< Software Interrupt on line 15 */
+#define EXTI_SWIER_SWIER16_Pos (16U)
+#define EXTI_SWIER_SWIER16_Msk (0x1U << EXTI_SWIER_SWIER16_Pos) /*!< 0x00010000 */
+#define EXTI_SWIER_SWIER16 EXTI_SWIER_SWIER16_Msk /*!< Software Interrupt on line 16 */
+#define EXTI_SWIER_SWIER17_Pos (17U)
+#define EXTI_SWIER_SWIER17_Msk (0x1U << EXTI_SWIER_SWIER17_Pos) /*!< 0x00020000 */
+#define EXTI_SWIER_SWIER17 EXTI_SWIER_SWIER17_Msk /*!< Software Interrupt on line 17 */
+#define EXTI_SWIER_SWIER18_Pos (18U)
+#define EXTI_SWIER_SWIER18_Msk (0x1U << EXTI_SWIER_SWIER18_Pos) /*!< 0x00040000 */
+#define EXTI_SWIER_SWIER18 EXTI_SWIER_SWIER18_Msk /*!< Software Interrupt on line 18 */
+#define EXTI_SWIER_SWIER19_Pos (19U)
+#define EXTI_SWIER_SWIER19_Msk (0x1U << EXTI_SWIER_SWIER19_Pos) /*!< 0x00080000 */
+#define EXTI_SWIER_SWIER19 EXTI_SWIER_SWIER19_Msk /*!< Software Interrupt on line 19 */
+
+/* References Defines */
+#define EXTI_SWIER_SWI0 EXTI_SWIER_SWIER0
+#define EXTI_SWIER_SWI1 EXTI_SWIER_SWIER1
+#define EXTI_SWIER_SWI2 EXTI_SWIER_SWIER2
+#define EXTI_SWIER_SWI3 EXTI_SWIER_SWIER3
+#define EXTI_SWIER_SWI4 EXTI_SWIER_SWIER4
+#define EXTI_SWIER_SWI5 EXTI_SWIER_SWIER5
+#define EXTI_SWIER_SWI6 EXTI_SWIER_SWIER6
+#define EXTI_SWIER_SWI7 EXTI_SWIER_SWIER7
+#define EXTI_SWIER_SWI8 EXTI_SWIER_SWIER8
+#define EXTI_SWIER_SWI9 EXTI_SWIER_SWIER9
+#define EXTI_SWIER_SWI10 EXTI_SWIER_SWIER10
+#define EXTI_SWIER_SWI11 EXTI_SWIER_SWIER11
+#define EXTI_SWIER_SWI12 EXTI_SWIER_SWIER12
+#define EXTI_SWIER_SWI13 EXTI_SWIER_SWIER13
+#define EXTI_SWIER_SWI14 EXTI_SWIER_SWIER14
+#define EXTI_SWIER_SWI15 EXTI_SWIER_SWIER15
+#define EXTI_SWIER_SWI16 EXTI_SWIER_SWIER16
+#define EXTI_SWIER_SWI17 EXTI_SWIER_SWIER17
+#define EXTI_SWIER_SWI18 EXTI_SWIER_SWIER18
+#define EXTI_SWIER_SWI19 EXTI_SWIER_SWIER19
+
+/******************* Bit definition for EXTI_PR register ********************/
+#define EXTI_PR_PR0_Pos (0U)
+#define EXTI_PR_PR0_Msk (0x1U << EXTI_PR_PR0_Pos) /*!< 0x00000001 */
+#define EXTI_PR_PR0 EXTI_PR_PR0_Msk /*!< Pending bit for line 0 */
+#define EXTI_PR_PR1_Pos (1U)
+#define EXTI_PR_PR1_Msk (0x1U << EXTI_PR_PR1_Pos) /*!< 0x00000002 */
+#define EXTI_PR_PR1 EXTI_PR_PR1_Msk /*!< Pending bit for line 1 */
+#define EXTI_PR_PR2_Pos (2U)
+#define EXTI_PR_PR2_Msk (0x1U << EXTI_PR_PR2_Pos) /*!< 0x00000004 */
+#define EXTI_PR_PR2 EXTI_PR_PR2_Msk /*!< Pending bit for line 2 */
+#define EXTI_PR_PR3_Pos (3U)
+#define EXTI_PR_PR3_Msk (0x1U << EXTI_PR_PR3_Pos) /*!< 0x00000008 */
+#define EXTI_PR_PR3 EXTI_PR_PR3_Msk /*!< Pending bit for line 3 */
+#define EXTI_PR_PR4_Pos (4U)
+#define EXTI_PR_PR4_Msk (0x1U << EXTI_PR_PR4_Pos) /*!< 0x00000010 */
+#define EXTI_PR_PR4 EXTI_PR_PR4_Msk /*!< Pending bit for line 4 */
+#define EXTI_PR_PR5_Pos (5U)
+#define EXTI_PR_PR5_Msk (0x1U << EXTI_PR_PR5_Pos) /*!< 0x00000020 */
+#define EXTI_PR_PR5 EXTI_PR_PR5_Msk /*!< Pending bit for line 5 */
+#define EXTI_PR_PR6_Pos (6U)
+#define EXTI_PR_PR6_Msk (0x1U << EXTI_PR_PR6_Pos) /*!< 0x00000040 */
+#define EXTI_PR_PR6 EXTI_PR_PR6_Msk /*!< Pending bit for line 6 */
+#define EXTI_PR_PR7_Pos (7U)
+#define EXTI_PR_PR7_Msk (0x1U << EXTI_PR_PR7_Pos) /*!< 0x00000080 */
+#define EXTI_PR_PR7 EXTI_PR_PR7_Msk /*!< Pending bit for line 7 */
+#define EXTI_PR_PR8_Pos (8U)
+#define EXTI_PR_PR8_Msk (0x1U << EXTI_PR_PR8_Pos) /*!< 0x00000100 */
+#define EXTI_PR_PR8 EXTI_PR_PR8_Msk /*!< Pending bit for line 8 */
+#define EXTI_PR_PR9_Pos (9U)
+#define EXTI_PR_PR9_Msk (0x1U << EXTI_PR_PR9_Pos) /*!< 0x00000200 */
+#define EXTI_PR_PR9 EXTI_PR_PR9_Msk /*!< Pending bit for line 9 */
+#define EXTI_PR_PR10_Pos (10U)
+#define EXTI_PR_PR10_Msk (0x1U << EXTI_PR_PR10_Pos) /*!< 0x00000400 */
+#define EXTI_PR_PR10 EXTI_PR_PR10_Msk /*!< Pending bit for line 10 */
+#define EXTI_PR_PR11_Pos (11U)
+#define EXTI_PR_PR11_Msk (0x1U << EXTI_PR_PR11_Pos) /*!< 0x00000800 */
+#define EXTI_PR_PR11 EXTI_PR_PR11_Msk /*!< Pending bit for line 11 */
+#define EXTI_PR_PR12_Pos (12U)
+#define EXTI_PR_PR12_Msk (0x1U << EXTI_PR_PR12_Pos) /*!< 0x00001000 */
+#define EXTI_PR_PR12 EXTI_PR_PR12_Msk /*!< Pending bit for line 12 */
+#define EXTI_PR_PR13_Pos (13U)
+#define EXTI_PR_PR13_Msk (0x1U << EXTI_PR_PR13_Pos) /*!< 0x00002000 */
+#define EXTI_PR_PR13 EXTI_PR_PR13_Msk /*!< Pending bit for line 13 */
+#define EXTI_PR_PR14_Pos (14U)
+#define EXTI_PR_PR14_Msk (0x1U << EXTI_PR_PR14_Pos) /*!< 0x00004000 */
+#define EXTI_PR_PR14 EXTI_PR_PR14_Msk /*!< Pending bit for line 14 */
+#define EXTI_PR_PR15_Pos (15U)
+#define EXTI_PR_PR15_Msk (0x1U << EXTI_PR_PR15_Pos) /*!< 0x00008000 */
+#define EXTI_PR_PR15 EXTI_PR_PR15_Msk /*!< Pending bit for line 15 */
+#define EXTI_PR_PR16_Pos (16U)
+#define EXTI_PR_PR16_Msk (0x1U << EXTI_PR_PR16_Pos) /*!< 0x00010000 */
+#define EXTI_PR_PR16 EXTI_PR_PR16_Msk /*!< Pending bit for line 16 */
+#define EXTI_PR_PR17_Pos (17U)
+#define EXTI_PR_PR17_Msk (0x1U << EXTI_PR_PR17_Pos) /*!< 0x00020000 */
+#define EXTI_PR_PR17 EXTI_PR_PR17_Msk /*!< Pending bit for line 17 */
+#define EXTI_PR_PR18_Pos (18U)
+#define EXTI_PR_PR18_Msk (0x1U << EXTI_PR_PR18_Pos) /*!< 0x00040000 */
+#define EXTI_PR_PR18 EXTI_PR_PR18_Msk /*!< Pending bit for line 18 */
+#define EXTI_PR_PR19_Pos (19U)
+#define EXTI_PR_PR19_Msk (0x1U << EXTI_PR_PR19_Pos) /*!< 0x00080000 */
+#define EXTI_PR_PR19 EXTI_PR_PR19_Msk /*!< Pending bit for line 19 */
+
+/* References Defines */
+#define EXTI_PR_PIF0 EXTI_PR_PR0
+#define EXTI_PR_PIF1 EXTI_PR_PR1
+#define EXTI_PR_PIF2 EXTI_PR_PR2
+#define EXTI_PR_PIF3 EXTI_PR_PR3
+#define EXTI_PR_PIF4 EXTI_PR_PR4
+#define EXTI_PR_PIF5 EXTI_PR_PR5
+#define EXTI_PR_PIF6 EXTI_PR_PR6
+#define EXTI_PR_PIF7 EXTI_PR_PR7
+#define EXTI_PR_PIF8 EXTI_PR_PR8
+#define EXTI_PR_PIF9 EXTI_PR_PR9
+#define EXTI_PR_PIF10 EXTI_PR_PR10
+#define EXTI_PR_PIF11 EXTI_PR_PR11
+#define EXTI_PR_PIF12 EXTI_PR_PR12
+#define EXTI_PR_PIF13 EXTI_PR_PR13
+#define EXTI_PR_PIF14 EXTI_PR_PR14
+#define EXTI_PR_PIF15 EXTI_PR_PR15
+#define EXTI_PR_PIF16 EXTI_PR_PR16
+#define EXTI_PR_PIF17 EXTI_PR_PR17
+#define EXTI_PR_PIF18 EXTI_PR_PR18
+#define EXTI_PR_PIF19 EXTI_PR_PR19
+
+/******************************************************************************/
+/* */
+/* DMA Controller */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for DMA_ISR register ********************/
+#define DMA_ISR_GIF1_Pos (0U)
+#define DMA_ISR_GIF1_Msk (0x1U << DMA_ISR_GIF1_Pos) /*!< 0x00000001 */
+#define DMA_ISR_GIF1 DMA_ISR_GIF1_Msk /*!< Channel 1 Global interrupt flag */
+#define DMA_ISR_TCIF1_Pos (1U)
+#define DMA_ISR_TCIF1_Msk (0x1U << DMA_ISR_TCIF1_Pos) /*!< 0x00000002 */
+#define DMA_ISR_TCIF1 DMA_ISR_TCIF1_Msk /*!< Channel 1 Transfer Complete flag */
+#define DMA_ISR_HTIF1_Pos (2U)
+#define DMA_ISR_HTIF1_Msk (0x1U << DMA_ISR_HTIF1_Pos) /*!< 0x00000004 */
+#define DMA_ISR_HTIF1 DMA_ISR_HTIF1_Msk /*!< Channel 1 Half Transfer flag */
+#define DMA_ISR_TEIF1_Pos (3U)
+#define DMA_ISR_TEIF1_Msk (0x1U << DMA_ISR_TEIF1_Pos) /*!< 0x00000008 */
+#define DMA_ISR_TEIF1 DMA_ISR_TEIF1_Msk /*!< Channel 1 Transfer Error flag */
+#define DMA_ISR_GIF2_Pos (4U)
+#define DMA_ISR_GIF2_Msk (0x1U << DMA_ISR_GIF2_Pos) /*!< 0x00000010 */
+#define DMA_ISR_GIF2 DMA_ISR_GIF2_Msk /*!< Channel 2 Global interrupt flag */
+#define DMA_ISR_TCIF2_Pos (5U)
+#define DMA_ISR_TCIF2_Msk (0x1U << DMA_ISR_TCIF2_Pos) /*!< 0x00000020 */
+#define DMA_ISR_TCIF2 DMA_ISR_TCIF2_Msk /*!< Channel 2 Transfer Complete flag */
+#define DMA_ISR_HTIF2_Pos (6U)
+#define DMA_ISR_HTIF2_Msk (0x1U << DMA_ISR_HTIF2_Pos) /*!< 0x00000040 */
+#define DMA_ISR_HTIF2 DMA_ISR_HTIF2_Msk /*!< Channel 2 Half Transfer flag */
+#define DMA_ISR_TEIF2_Pos (7U)
+#define DMA_ISR_TEIF2_Msk (0x1U << DMA_ISR_TEIF2_Pos) /*!< 0x00000080 */
+#define DMA_ISR_TEIF2 DMA_ISR_TEIF2_Msk /*!< Channel 2 Transfer Error flag */
+#define DMA_ISR_GIF3_Pos (8U)
+#define DMA_ISR_GIF3_Msk (0x1U << DMA_ISR_GIF3_Pos) /*!< 0x00000100 */
+#define DMA_ISR_GIF3 DMA_ISR_GIF3_Msk /*!< Channel 3 Global interrupt flag */
+#define DMA_ISR_TCIF3_Pos (9U)
+#define DMA_ISR_TCIF3_Msk (0x1U << DMA_ISR_TCIF3_Pos) /*!< 0x00000200 */
+#define DMA_ISR_TCIF3 DMA_ISR_TCIF3_Msk /*!< Channel 3 Transfer Complete flag */
+#define DMA_ISR_HTIF3_Pos (10U)
+#define DMA_ISR_HTIF3_Msk (0x1U << DMA_ISR_HTIF3_Pos) /*!< 0x00000400 */
+#define DMA_ISR_HTIF3 DMA_ISR_HTIF3_Msk /*!< Channel 3 Half Transfer flag */
+#define DMA_ISR_TEIF3_Pos (11U)
+#define DMA_ISR_TEIF3_Msk (0x1U << DMA_ISR_TEIF3_Pos) /*!< 0x00000800 */
+#define DMA_ISR_TEIF3 DMA_ISR_TEIF3_Msk /*!< Channel 3 Transfer Error flag */
+#define DMA_ISR_GIF4_Pos (12U)
+#define DMA_ISR_GIF4_Msk (0x1U << DMA_ISR_GIF4_Pos) /*!< 0x00001000 */
+#define DMA_ISR_GIF4 DMA_ISR_GIF4_Msk /*!< Channel 4 Global interrupt flag */
+#define DMA_ISR_TCIF4_Pos (13U)
+#define DMA_ISR_TCIF4_Msk (0x1U << DMA_ISR_TCIF4_Pos) /*!< 0x00002000 */
+#define DMA_ISR_TCIF4 DMA_ISR_TCIF4_Msk /*!< Channel 4 Transfer Complete flag */
+#define DMA_ISR_HTIF4_Pos (14U)
+#define DMA_ISR_HTIF4_Msk (0x1U << DMA_ISR_HTIF4_Pos) /*!< 0x00004000 */
+#define DMA_ISR_HTIF4 DMA_ISR_HTIF4_Msk /*!< Channel 4 Half Transfer flag */
+#define DMA_ISR_TEIF4_Pos (15U)
+#define DMA_ISR_TEIF4_Msk (0x1U << DMA_ISR_TEIF4_Pos) /*!< 0x00008000 */
+#define DMA_ISR_TEIF4 DMA_ISR_TEIF4_Msk /*!< Channel 4 Transfer Error flag */
+#define DMA_ISR_GIF5_Pos (16U)
+#define DMA_ISR_GIF5_Msk (0x1U << DMA_ISR_GIF5_Pos) /*!< 0x00010000 */
+#define DMA_ISR_GIF5 DMA_ISR_GIF5_Msk /*!< Channel 5 Global interrupt flag */
+#define DMA_ISR_TCIF5_Pos (17U)
+#define DMA_ISR_TCIF5_Msk (0x1U << DMA_ISR_TCIF5_Pos) /*!< 0x00020000 */
+#define DMA_ISR_TCIF5 DMA_ISR_TCIF5_Msk /*!< Channel 5 Transfer Complete flag */
+#define DMA_ISR_HTIF5_Pos (18U)
+#define DMA_ISR_HTIF5_Msk (0x1U << DMA_ISR_HTIF5_Pos) /*!< 0x00040000 */
+#define DMA_ISR_HTIF5 DMA_ISR_HTIF5_Msk /*!< Channel 5 Half Transfer flag */
+#define DMA_ISR_TEIF5_Pos (19U)
+#define DMA_ISR_TEIF5_Msk (0x1U << DMA_ISR_TEIF5_Pos) /*!< 0x00080000 */
+#define DMA_ISR_TEIF5 DMA_ISR_TEIF5_Msk /*!< Channel 5 Transfer Error flag */
+#define DMA_ISR_GIF6_Pos (20U)
+#define DMA_ISR_GIF6_Msk (0x1U << DMA_ISR_GIF6_Pos) /*!< 0x00100000 */
+#define DMA_ISR_GIF6 DMA_ISR_GIF6_Msk /*!< Channel 6 Global interrupt flag */
+#define DMA_ISR_TCIF6_Pos (21U)
+#define DMA_ISR_TCIF6_Msk (0x1U << DMA_ISR_TCIF6_Pos) /*!< 0x00200000 */
+#define DMA_ISR_TCIF6 DMA_ISR_TCIF6_Msk /*!< Channel 6 Transfer Complete flag */
+#define DMA_ISR_HTIF6_Pos (22U)
+#define DMA_ISR_HTIF6_Msk (0x1U << DMA_ISR_HTIF6_Pos) /*!< 0x00400000 */
+#define DMA_ISR_HTIF6 DMA_ISR_HTIF6_Msk /*!< Channel 6 Half Transfer flag */
+#define DMA_ISR_TEIF6_Pos (23U)
+#define DMA_ISR_TEIF6_Msk (0x1U << DMA_ISR_TEIF6_Pos) /*!< 0x00800000 */
+#define DMA_ISR_TEIF6 DMA_ISR_TEIF6_Msk /*!< Channel 6 Transfer Error flag */
+#define DMA_ISR_GIF7_Pos (24U)
+#define DMA_ISR_GIF7_Msk (0x1U << DMA_ISR_GIF7_Pos) /*!< 0x01000000 */
+#define DMA_ISR_GIF7 DMA_ISR_GIF7_Msk /*!< Channel 7 Global interrupt flag */
+#define DMA_ISR_TCIF7_Pos (25U)
+#define DMA_ISR_TCIF7_Msk (0x1U << DMA_ISR_TCIF7_Pos) /*!< 0x02000000 */
+#define DMA_ISR_TCIF7 DMA_ISR_TCIF7_Msk /*!< Channel 7 Transfer Complete flag */
+#define DMA_ISR_HTIF7_Pos (26U)
+#define DMA_ISR_HTIF7_Msk (0x1U << DMA_ISR_HTIF7_Pos) /*!< 0x04000000 */
+#define DMA_ISR_HTIF7 DMA_ISR_HTIF7_Msk /*!< Channel 7 Half Transfer flag */
+#define DMA_ISR_TEIF7_Pos (27U)
+#define DMA_ISR_TEIF7_Msk (0x1U << DMA_ISR_TEIF7_Pos) /*!< 0x08000000 */
+#define DMA_ISR_TEIF7 DMA_ISR_TEIF7_Msk /*!< Channel 7 Transfer Error flag */
+
+/******************* Bit definition for DMA_IFCR register *******************/
+#define DMA_IFCR_CGIF1_Pos (0U)
+#define DMA_IFCR_CGIF1_Msk (0x1U << DMA_IFCR_CGIF1_Pos) /*!< 0x00000001 */
+#define DMA_IFCR_CGIF1 DMA_IFCR_CGIF1_Msk /*!< Channel 1 Global interrupt clear */
+#define DMA_IFCR_CTCIF1_Pos (1U)
+#define DMA_IFCR_CTCIF1_Msk (0x1U << DMA_IFCR_CTCIF1_Pos) /*!< 0x00000002 */
+#define DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF1_Msk /*!< Channel 1 Transfer Complete clear */
+#define DMA_IFCR_CHTIF1_Pos (2U)
+#define DMA_IFCR_CHTIF1_Msk (0x1U << DMA_IFCR_CHTIF1_Pos) /*!< 0x00000004 */
+#define DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF1_Msk /*!< Channel 1 Half Transfer clear */
+#define DMA_IFCR_CTEIF1_Pos (3U)
+#define DMA_IFCR_CTEIF1_Msk (0x1U << DMA_IFCR_CTEIF1_Pos) /*!< 0x00000008 */
+#define DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF1_Msk /*!< Channel 1 Transfer Error clear */
+#define DMA_IFCR_CGIF2_Pos (4U)
+#define DMA_IFCR_CGIF2_Msk (0x1U << DMA_IFCR_CGIF2_Pos) /*!< 0x00000010 */
+#define DMA_IFCR_CGIF2 DMA_IFCR_CGIF2_Msk /*!< Channel 2 Global interrupt clear */
+#define DMA_IFCR_CTCIF2_Pos (5U)
+#define DMA_IFCR_CTCIF2_Msk (0x1U << DMA_IFCR_CTCIF2_Pos) /*!< 0x00000020 */
+#define DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF2_Msk /*!< Channel 2 Transfer Complete clear */
+#define DMA_IFCR_CHTIF2_Pos (6U)
+#define DMA_IFCR_CHTIF2_Msk (0x1U << DMA_IFCR_CHTIF2_Pos) /*!< 0x00000040 */
+#define DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF2_Msk /*!< Channel 2 Half Transfer clear */
+#define DMA_IFCR_CTEIF2_Pos (7U)
+#define DMA_IFCR_CTEIF2_Msk (0x1U << DMA_IFCR_CTEIF2_Pos) /*!< 0x00000080 */
+#define DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF2_Msk /*!< Channel 2 Transfer Error clear */
+#define DMA_IFCR_CGIF3_Pos (8U)
+#define DMA_IFCR_CGIF3_Msk (0x1U << DMA_IFCR_CGIF3_Pos) /*!< 0x00000100 */
+#define DMA_IFCR_CGIF3 DMA_IFCR_CGIF3_Msk /*!< Channel 3 Global interrupt clear */
+#define DMA_IFCR_CTCIF3_Pos (9U)
+#define DMA_IFCR_CTCIF3_Msk (0x1U << DMA_IFCR_CTCIF3_Pos) /*!< 0x00000200 */
+#define DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF3_Msk /*!< Channel 3 Transfer Complete clear */
+#define DMA_IFCR_CHTIF3_Pos (10U)
+#define DMA_IFCR_CHTIF3_Msk (0x1U << DMA_IFCR_CHTIF3_Pos) /*!< 0x00000400 */
+#define DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF3_Msk /*!< Channel 3 Half Transfer clear */
+#define DMA_IFCR_CTEIF3_Pos (11U)
+#define DMA_IFCR_CTEIF3_Msk (0x1U << DMA_IFCR_CTEIF3_Pos) /*!< 0x00000800 */
+#define DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF3_Msk /*!< Channel 3 Transfer Error clear */
+#define DMA_IFCR_CGIF4_Pos (12U)
+#define DMA_IFCR_CGIF4_Msk (0x1U << DMA_IFCR_CGIF4_Pos) /*!< 0x00001000 */
+#define DMA_IFCR_CGIF4 DMA_IFCR_CGIF4_Msk /*!< Channel 4 Global interrupt clear */
+#define DMA_IFCR_CTCIF4_Pos (13U)
+#define DMA_IFCR_CTCIF4_Msk (0x1U << DMA_IFCR_CTCIF4_Pos) /*!< 0x00002000 */
+#define DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF4_Msk /*!< Channel 4 Transfer Complete clear */
+#define DMA_IFCR_CHTIF4_Pos (14U)
+#define DMA_IFCR_CHTIF4_Msk (0x1U << DMA_IFCR_CHTIF4_Pos) /*!< 0x00004000 */
+#define DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF4_Msk /*!< Channel 4 Half Transfer clear */
+#define DMA_IFCR_CTEIF4_Pos (15U)
+#define DMA_IFCR_CTEIF4_Msk (0x1U << DMA_IFCR_CTEIF4_Pos) /*!< 0x00008000 */
+#define DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF4_Msk /*!< Channel 4 Transfer Error clear */
+#define DMA_IFCR_CGIF5_Pos (16U)
+#define DMA_IFCR_CGIF5_Msk (0x1U << DMA_IFCR_CGIF5_Pos) /*!< 0x00010000 */
+#define DMA_IFCR_CGIF5 DMA_IFCR_CGIF5_Msk /*!< Channel 5 Global interrupt clear */
+#define DMA_IFCR_CTCIF5_Pos (17U)
+#define DMA_IFCR_CTCIF5_Msk (0x1U << DMA_IFCR_CTCIF5_Pos) /*!< 0x00020000 */
+#define DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF5_Msk /*!< Channel 5 Transfer Complete clear */
+#define DMA_IFCR_CHTIF5_Pos (18U)
+#define DMA_IFCR_CHTIF5_Msk (0x1U << DMA_IFCR_CHTIF5_Pos) /*!< 0x00040000 */
+#define DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5_Msk /*!< Channel 5 Half Transfer clear */
+#define DMA_IFCR_CTEIF5_Pos (19U)
+#define DMA_IFCR_CTEIF5_Msk (0x1U << DMA_IFCR_CTEIF5_Pos) /*!< 0x00080000 */
+#define DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF5_Msk /*!< Channel 5 Transfer Error clear */
+#define DMA_IFCR_CGIF6_Pos (20U)
+#define DMA_IFCR_CGIF6_Msk (0x1U << DMA_IFCR_CGIF6_Pos) /*!< 0x00100000 */
+#define DMA_IFCR_CGIF6 DMA_IFCR_CGIF6_Msk /*!< Channel 6 Global interrupt clear */
+#define DMA_IFCR_CTCIF6_Pos (21U)
+#define DMA_IFCR_CTCIF6_Msk (0x1U << DMA_IFCR_CTCIF6_Pos) /*!< 0x00200000 */
+#define DMA_IFCR_CTCIF6 DMA_IFCR_CTCIF6_Msk /*!< Channel 6 Transfer Complete clear */
+#define DMA_IFCR_CHTIF6_Pos (22U)
+#define DMA_IFCR_CHTIF6_Msk (0x1U << DMA_IFCR_CHTIF6_Pos) /*!< 0x00400000 */
+#define DMA_IFCR_CHTIF6 DMA_IFCR_CHTIF6_Msk /*!< Channel 6 Half Transfer clear */
+#define DMA_IFCR_CTEIF6_Pos (23U)
+#define DMA_IFCR_CTEIF6_Msk (0x1U << DMA_IFCR_CTEIF6_Pos) /*!< 0x00800000 */
+#define DMA_IFCR_CTEIF6 DMA_IFCR_CTEIF6_Msk /*!< Channel 6 Transfer Error clear */
+#define DMA_IFCR_CGIF7_Pos (24U)
+#define DMA_IFCR_CGIF7_Msk (0x1U << DMA_IFCR_CGIF7_Pos) /*!< 0x01000000 */
+#define DMA_IFCR_CGIF7 DMA_IFCR_CGIF7_Msk /*!< Channel 7 Global interrupt clear */
+#define DMA_IFCR_CTCIF7_Pos (25U)
+#define DMA_IFCR_CTCIF7_Msk (0x1U << DMA_IFCR_CTCIF7_Pos) /*!< 0x02000000 */
+#define DMA_IFCR_CTCIF7 DMA_IFCR_CTCIF7_Msk /*!< Channel 7 Transfer Complete clear */
+#define DMA_IFCR_CHTIF7_Pos (26U)
+#define DMA_IFCR_CHTIF7_Msk (0x1U << DMA_IFCR_CHTIF7_Pos) /*!< 0x04000000 */
+#define DMA_IFCR_CHTIF7 DMA_IFCR_CHTIF7_Msk /*!< Channel 7 Half Transfer clear */
+#define DMA_IFCR_CTEIF7_Pos (27U)
+#define DMA_IFCR_CTEIF7_Msk (0x1U << DMA_IFCR_CTEIF7_Pos) /*!< 0x08000000 */
+#define DMA_IFCR_CTEIF7 DMA_IFCR_CTEIF7_Msk /*!< Channel 7 Transfer Error clear */
+
+/******************* Bit definition for DMA_CCR register *******************/
+#define DMA_CCR_EN_Pos (0U)
+#define DMA_CCR_EN_Msk (0x1U << DMA_CCR_EN_Pos) /*!< 0x00000001 */
+#define DMA_CCR_EN DMA_CCR_EN_Msk /*!< Channel enable */
+#define DMA_CCR_TCIE_Pos (1U)
+#define DMA_CCR_TCIE_Msk (0x1U << DMA_CCR_TCIE_Pos) /*!< 0x00000002 */
+#define DMA_CCR_TCIE DMA_CCR_TCIE_Msk /*!< Transfer complete interrupt enable */
+#define DMA_CCR_HTIE_Pos (2U)
+#define DMA_CCR_HTIE_Msk (0x1U << DMA_CCR_HTIE_Pos) /*!< 0x00000004 */
+#define DMA_CCR_HTIE DMA_CCR_HTIE_Msk /*!< Half Transfer interrupt enable */
+#define DMA_CCR_TEIE_Pos (3U)
+#define DMA_CCR_TEIE_Msk (0x1U << DMA_CCR_TEIE_Pos) /*!< 0x00000008 */
+#define DMA_CCR_TEIE DMA_CCR_TEIE_Msk /*!< Transfer error interrupt enable */
+#define DMA_CCR_DIR_Pos (4U)
+#define DMA_CCR_DIR_Msk (0x1U << DMA_CCR_DIR_Pos) /*!< 0x00000010 */
+#define DMA_CCR_DIR DMA_CCR_DIR_Msk /*!< Data transfer direction */
+#define DMA_CCR_CIRC_Pos (5U)
+#define DMA_CCR_CIRC_Msk (0x1U << DMA_CCR_CIRC_Pos) /*!< 0x00000020 */
+#define DMA_CCR_CIRC DMA_CCR_CIRC_Msk /*!< Circular mode */
+#define DMA_CCR_PINC_Pos (6U)
+#define DMA_CCR_PINC_Msk (0x1U << DMA_CCR_PINC_Pos) /*!< 0x00000040 */
+#define DMA_CCR_PINC DMA_CCR_PINC_Msk /*!< Peripheral increment mode */
+#define DMA_CCR_MINC_Pos (7U)
+#define DMA_CCR_MINC_Msk (0x1U << DMA_CCR_MINC_Pos) /*!< 0x00000080 */
+#define DMA_CCR_MINC DMA_CCR_MINC_Msk /*!< Memory increment mode */
+
+#define DMA_CCR_PSIZE_Pos (8U)
+#define DMA_CCR_PSIZE_Msk (0x3U << DMA_CCR_PSIZE_Pos) /*!< 0x00000300 */
+#define DMA_CCR_PSIZE DMA_CCR_PSIZE_Msk /*!< PSIZE[1:0] bits (Peripheral size) */
+#define DMA_CCR_PSIZE_0 (0x1U << DMA_CCR_PSIZE_Pos) /*!< 0x00000100 */
+#define DMA_CCR_PSIZE_1 (0x2U << DMA_CCR_PSIZE_Pos) /*!< 0x00000200 */
+
+#define DMA_CCR_MSIZE_Pos (10U)
+#define DMA_CCR_MSIZE_Msk (0x3U << DMA_CCR_MSIZE_Pos) /*!< 0x00000C00 */
+#define DMA_CCR_MSIZE DMA_CCR_MSIZE_Msk /*!< MSIZE[1:0] bits (Memory size) */
+#define DMA_CCR_MSIZE_0 (0x1U << DMA_CCR_MSIZE_Pos) /*!< 0x00000400 */
+#define DMA_CCR_MSIZE_1 (0x2U << DMA_CCR_MSIZE_Pos) /*!< 0x00000800 */
+
+#define DMA_CCR_PL_Pos (12U)
+#define DMA_CCR_PL_Msk (0x3U << DMA_CCR_PL_Pos) /*!< 0x00003000 */
+#define DMA_CCR_PL DMA_CCR_PL_Msk /*!< PL[1:0] bits(Channel Priority level) */
+#define DMA_CCR_PL_0 (0x1U << DMA_CCR_PL_Pos) /*!< 0x00001000 */
+#define DMA_CCR_PL_1 (0x2U << DMA_CCR_PL_Pos) /*!< 0x00002000 */
+
+#define DMA_CCR_MEM2MEM_Pos (14U)
+#define DMA_CCR_MEM2MEM_Msk (0x1U << DMA_CCR_MEM2MEM_Pos) /*!< 0x00004000 */
+#define DMA_CCR_MEM2MEM DMA_CCR_MEM2MEM_Msk /*!< Memory to memory mode */
+
+/****************** Bit definition for DMA_CNDTR register ******************/
+#define DMA_CNDTR_NDT_Pos (0U)
+#define DMA_CNDTR_NDT_Msk (0xFFFFU << DMA_CNDTR_NDT_Pos) /*!< 0x0000FFFF */
+#define DMA_CNDTR_NDT DMA_CNDTR_NDT_Msk /*!< Number of data to Transfer */
+
+/****************** Bit definition for DMA_CPAR register *******************/
+#define DMA_CPAR_PA_Pos (0U)
+#define DMA_CPAR_PA_Msk (0xFFFFFFFFU << DMA_CPAR_PA_Pos) /*!< 0xFFFFFFFF */
+#define DMA_CPAR_PA DMA_CPAR_PA_Msk /*!< Peripheral Address */
+
+/****************** Bit definition for DMA_CMAR register *******************/
+#define DMA_CMAR_MA_Pos (0U)
+#define DMA_CMAR_MA_Msk (0xFFFFFFFFU << DMA_CMAR_MA_Pos) /*!< 0xFFFFFFFF */
+#define DMA_CMAR_MA DMA_CMAR_MA_Msk /*!< Memory Address */
+
+/******************************************************************************/
+/* */
+/* Analog to Digital Converter (ADC) */
+/* */
+/******************************************************************************/
+
+/*
+ * @brief Specific device feature definitions (not present on all devices in the STM32F1 family)
+ */
+#define ADC_MULTIMODE_SUPPORT /*!< ADC feature available only on specific devices: multimode available on devices with several ADC instances */
+
+/******************** Bit definition for ADC_SR register ********************/
+#define ADC_SR_AWD_Pos (0U)
+#define ADC_SR_AWD_Msk (0x1U << ADC_SR_AWD_Pos) /*!< 0x00000001 */
+#define ADC_SR_AWD ADC_SR_AWD_Msk /*!< ADC analog watchdog 1 flag */
+#define ADC_SR_EOS_Pos (1U)
+#define ADC_SR_EOS_Msk (0x1U << ADC_SR_EOS_Pos) /*!< 0x00000002 */
+#define ADC_SR_EOS ADC_SR_EOS_Msk /*!< ADC group regular end of sequence conversions flag */
+#define ADC_SR_JEOS_Pos (2U)
+#define ADC_SR_JEOS_Msk (0x1U << ADC_SR_JEOS_Pos) /*!< 0x00000004 */
+#define ADC_SR_JEOS ADC_SR_JEOS_Msk /*!< ADC group injected end of sequence conversions flag */
+#define ADC_SR_JSTRT_Pos (3U)
+#define ADC_SR_JSTRT_Msk (0x1U << ADC_SR_JSTRT_Pos) /*!< 0x00000008 */
+#define ADC_SR_JSTRT ADC_SR_JSTRT_Msk /*!< ADC group injected conversion start flag */
+#define ADC_SR_STRT_Pos (4U)
+#define ADC_SR_STRT_Msk (0x1U << ADC_SR_STRT_Pos) /*!< 0x00000010 */
+#define ADC_SR_STRT ADC_SR_STRT_Msk /*!< ADC group regular conversion start flag */
+
+/* Legacy defines */
+#define ADC_SR_EOC (ADC_SR_EOS)
+#define ADC_SR_JEOC (ADC_SR_JEOS)
+
+/******************* Bit definition for ADC_CR1 register ********************/
+#define ADC_CR1_AWDCH_Pos (0U)
+#define ADC_CR1_AWDCH_Msk (0x1FU << ADC_CR1_AWDCH_Pos) /*!< 0x0000001F */
+#define ADC_CR1_AWDCH ADC_CR1_AWDCH_Msk /*!< ADC analog watchdog 1 monitored channel selection */
+#define ADC_CR1_AWDCH_0 (0x01U << ADC_CR1_AWDCH_Pos) /*!< 0x00000001 */
+#define ADC_CR1_AWDCH_1 (0x02U << ADC_CR1_AWDCH_Pos) /*!< 0x00000002 */
+#define ADC_CR1_AWDCH_2 (0x04U << ADC_CR1_AWDCH_Pos) /*!< 0x00000004 */
+#define ADC_CR1_AWDCH_3 (0x08U << ADC_CR1_AWDCH_Pos) /*!< 0x00000008 */
+#define ADC_CR1_AWDCH_4 (0x10U << ADC_CR1_AWDCH_Pos) /*!< 0x00000010 */
+
+#define ADC_CR1_EOSIE_Pos (5U)
+#define ADC_CR1_EOSIE_Msk (0x1U << ADC_CR1_EOSIE_Pos) /*!< 0x00000020 */
+#define ADC_CR1_EOSIE ADC_CR1_EOSIE_Msk /*!< ADC group regular end of sequence conversions interrupt */
+#define ADC_CR1_AWDIE_Pos (6U)
+#define ADC_CR1_AWDIE_Msk (0x1U << ADC_CR1_AWDIE_Pos) /*!< 0x00000040 */
+#define ADC_CR1_AWDIE ADC_CR1_AWDIE_Msk /*!< ADC analog watchdog 1 interrupt */
+#define ADC_CR1_JEOSIE_Pos (7U)
+#define ADC_CR1_JEOSIE_Msk (0x1U << ADC_CR1_JEOSIE_Pos) /*!< 0x00000080 */
+#define ADC_CR1_JEOSIE ADC_CR1_JEOSIE_Msk /*!< ADC group injected end of sequence conversions interrupt */
+#define ADC_CR1_SCAN_Pos (8U)
+#define ADC_CR1_SCAN_Msk (0x1U << ADC_CR1_SCAN_Pos) /*!< 0x00000100 */
+#define ADC_CR1_SCAN ADC_CR1_SCAN_Msk /*!< ADC scan mode */
+#define ADC_CR1_AWDSGL_Pos (9U)
+#define ADC_CR1_AWDSGL_Msk (0x1U << ADC_CR1_AWDSGL_Pos) /*!< 0x00000200 */
+#define ADC_CR1_AWDSGL ADC_CR1_AWDSGL_Msk /*!< ADC analog watchdog 1 monitoring a single channel or all channels */
+#define ADC_CR1_JAUTO_Pos (10U)
+#define ADC_CR1_JAUTO_Msk (0x1U << ADC_CR1_JAUTO_Pos) /*!< 0x00000400 */
+#define ADC_CR1_JAUTO ADC_CR1_JAUTO_Msk /*!< ADC group injected automatic trigger mode */
+#define ADC_CR1_DISCEN_Pos (11U)
+#define ADC_CR1_DISCEN_Msk (0x1U << ADC_CR1_DISCEN_Pos) /*!< 0x00000800 */
+#define ADC_CR1_DISCEN ADC_CR1_DISCEN_Msk /*!< ADC group regular sequencer discontinuous mode */
+#define ADC_CR1_JDISCEN_Pos (12U)
+#define ADC_CR1_JDISCEN_Msk (0x1U << ADC_CR1_JDISCEN_Pos) /*!< 0x00001000 */
+#define ADC_CR1_JDISCEN ADC_CR1_JDISCEN_Msk /*!< ADC group injected sequencer discontinuous mode */
+
+#define ADC_CR1_DISCNUM_Pos (13U)
+#define ADC_CR1_DISCNUM_Msk (0x7U << ADC_CR1_DISCNUM_Pos) /*!< 0x0000E000 */
+#define ADC_CR1_DISCNUM ADC_CR1_DISCNUM_Msk /*!< ADC group regular sequencer discontinuous number of ranks */
+#define ADC_CR1_DISCNUM_0 (0x1U << ADC_CR1_DISCNUM_Pos) /*!< 0x00002000 */
+#define ADC_CR1_DISCNUM_1 (0x2U << ADC_CR1_DISCNUM_Pos) /*!< 0x00004000 */
+#define ADC_CR1_DISCNUM_2 (0x4U << ADC_CR1_DISCNUM_Pos) /*!< 0x00008000 */
+
+#define ADC_CR1_DUALMOD_Pos (16U)
+#define ADC_CR1_DUALMOD_Msk (0xFU << ADC_CR1_DUALMOD_Pos) /*!< 0x000F0000 */
+#define ADC_CR1_DUALMOD ADC_CR1_DUALMOD_Msk /*!< ADC multimode mode selection */
+#define ADC_CR1_DUALMOD_0 (0x1U << ADC_CR1_DUALMOD_Pos) /*!< 0x00010000 */
+#define ADC_CR1_DUALMOD_1 (0x2U << ADC_CR1_DUALMOD_Pos) /*!< 0x00020000 */
+#define ADC_CR1_DUALMOD_2 (0x4U << ADC_CR1_DUALMOD_Pos) /*!< 0x00040000 */
+#define ADC_CR1_DUALMOD_3 (0x8U << ADC_CR1_DUALMOD_Pos) /*!< 0x00080000 */
+
+#define ADC_CR1_JAWDEN_Pos (22U)
+#define ADC_CR1_JAWDEN_Msk (0x1U << ADC_CR1_JAWDEN_Pos) /*!< 0x00400000 */
+#define ADC_CR1_JAWDEN ADC_CR1_JAWDEN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group injected */
+#define ADC_CR1_AWDEN_Pos (23U)
+#define ADC_CR1_AWDEN_Msk (0x1U << ADC_CR1_AWDEN_Pos) /*!< 0x00800000 */
+#define ADC_CR1_AWDEN ADC_CR1_AWDEN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group regular */
+
+/* Legacy defines */
+#define ADC_CR1_EOCIE (ADC_CR1_EOSIE)
+#define ADC_CR1_JEOCIE (ADC_CR1_JEOSIE)
+
+/******************* Bit definition for ADC_CR2 register ********************/
+#define ADC_CR2_ADON_Pos (0U)
+#define ADC_CR2_ADON_Msk (0x1U << ADC_CR2_ADON_Pos) /*!< 0x00000001 */
+#define ADC_CR2_ADON ADC_CR2_ADON_Msk /*!< ADC enable */
+#define ADC_CR2_CONT_Pos (1U)
+#define ADC_CR2_CONT_Msk (0x1U << ADC_CR2_CONT_Pos) /*!< 0x00000002 */
+#define ADC_CR2_CONT ADC_CR2_CONT_Msk /*!< ADC group regular continuous conversion mode */
+#define ADC_CR2_CAL_Pos (2U)
+#define ADC_CR2_CAL_Msk (0x1U << ADC_CR2_CAL_Pos) /*!< 0x00000004 */
+#define ADC_CR2_CAL ADC_CR2_CAL_Msk /*!< ADC calibration start */
+#define ADC_CR2_RSTCAL_Pos (3U)
+#define ADC_CR2_RSTCAL_Msk (0x1U << ADC_CR2_RSTCAL_Pos) /*!< 0x00000008 */
+#define ADC_CR2_RSTCAL ADC_CR2_RSTCAL_Msk /*!< ADC calibration reset */
+#define ADC_CR2_DMA_Pos (8U)
+#define ADC_CR2_DMA_Msk (0x1U << ADC_CR2_DMA_Pos) /*!< 0x00000100 */
+#define ADC_CR2_DMA ADC_CR2_DMA_Msk /*!< ADC DMA transfer enable */
+#define ADC_CR2_ALIGN_Pos (11U)
+#define ADC_CR2_ALIGN_Msk (0x1U << ADC_CR2_ALIGN_Pos) /*!< 0x00000800 */
+#define ADC_CR2_ALIGN ADC_CR2_ALIGN_Msk /*!< ADC data alignement */
+
+#define ADC_CR2_JEXTSEL_Pos (12U)
+#define ADC_CR2_JEXTSEL_Msk (0x7U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00007000 */
+#define ADC_CR2_JEXTSEL ADC_CR2_JEXTSEL_Msk /*!< ADC group injected external trigger source */
+#define ADC_CR2_JEXTSEL_0 (0x1U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00001000 */
+#define ADC_CR2_JEXTSEL_1 (0x2U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00002000 */
+#define ADC_CR2_JEXTSEL_2 (0x4U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00004000 */
+
+#define ADC_CR2_JEXTTRIG_Pos (15U)
+#define ADC_CR2_JEXTTRIG_Msk (0x1U << ADC_CR2_JEXTTRIG_Pos) /*!< 0x00008000 */
+#define ADC_CR2_JEXTTRIG ADC_CR2_JEXTTRIG_Msk /*!< ADC group injected external trigger enable */
+
+#define ADC_CR2_EXTSEL_Pos (17U)
+#define ADC_CR2_EXTSEL_Msk (0x7U << ADC_CR2_EXTSEL_Pos) /*!< 0x000E0000 */
+#define ADC_CR2_EXTSEL ADC_CR2_EXTSEL_Msk /*!< ADC group regular external trigger source */
+#define ADC_CR2_EXTSEL_0 (0x1U << ADC_CR2_EXTSEL_Pos) /*!< 0x00020000 */
+#define ADC_CR2_EXTSEL_1 (0x2U << ADC_CR2_EXTSEL_Pos) /*!< 0x00040000 */
+#define ADC_CR2_EXTSEL_2 (0x4U << ADC_CR2_EXTSEL_Pos) /*!< 0x00080000 */
+
+#define ADC_CR2_EXTTRIG_Pos (20U)
+#define ADC_CR2_EXTTRIG_Msk (0x1U << ADC_CR2_EXTTRIG_Pos) /*!< 0x00100000 */
+#define ADC_CR2_EXTTRIG ADC_CR2_EXTTRIG_Msk /*!< ADC group regular external trigger enable */
+#define ADC_CR2_JSWSTART_Pos (21U)
+#define ADC_CR2_JSWSTART_Msk (0x1U << ADC_CR2_JSWSTART_Pos) /*!< 0x00200000 */
+#define ADC_CR2_JSWSTART ADC_CR2_JSWSTART_Msk /*!< ADC group injected conversion start */
+#define ADC_CR2_SWSTART_Pos (22U)
+#define ADC_CR2_SWSTART_Msk (0x1U << ADC_CR2_SWSTART_Pos) /*!< 0x00400000 */
+#define ADC_CR2_SWSTART ADC_CR2_SWSTART_Msk /*!< ADC group regular conversion start */
+#define ADC_CR2_TSVREFE_Pos (23U)
+#define ADC_CR2_TSVREFE_Msk (0x1U << ADC_CR2_TSVREFE_Pos) /*!< 0x00800000 */
+#define ADC_CR2_TSVREFE ADC_CR2_TSVREFE_Msk /*!< ADC internal path to VrefInt and temperature sensor enable */
+
+/****************** Bit definition for ADC_SMPR1 register *******************/
+#define ADC_SMPR1_SMP10_Pos (0U)
+#define ADC_SMPR1_SMP10_Msk (0x7U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000007 */
+#define ADC_SMPR1_SMP10 ADC_SMPR1_SMP10_Msk /*!< ADC channel 10 sampling time selection */
+#define ADC_SMPR1_SMP10_0 (0x1U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000001 */
+#define ADC_SMPR1_SMP10_1 (0x2U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000002 */
+#define ADC_SMPR1_SMP10_2 (0x4U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000004 */
+
+#define ADC_SMPR1_SMP11_Pos (3U)
+#define ADC_SMPR1_SMP11_Msk (0x7U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000038 */
+#define ADC_SMPR1_SMP11 ADC_SMPR1_SMP11_Msk /*!< ADC channel 11 sampling time selection */
+#define ADC_SMPR1_SMP11_0 (0x1U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000008 */
+#define ADC_SMPR1_SMP11_1 (0x2U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000010 */
+#define ADC_SMPR1_SMP11_2 (0x4U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000020 */
+
+#define ADC_SMPR1_SMP12_Pos (6U)
+#define ADC_SMPR1_SMP12_Msk (0x7U << ADC_SMPR1_SMP12_Pos) /*!< 0x000001C0 */
+#define ADC_SMPR1_SMP12 ADC_SMPR1_SMP12_Msk /*!< ADC channel 12 sampling time selection */
+#define ADC_SMPR1_SMP12_0 (0x1U << ADC_SMPR1_SMP12_Pos) /*!< 0x00000040 */
+#define ADC_SMPR1_SMP12_1 (0x2U << ADC_SMPR1_SMP12_Pos) /*!< 0x00000080 */
+#define ADC_SMPR1_SMP12_2 (0x4U << ADC_SMPR1_SMP12_Pos) /*!< 0x00000100 */
+
+#define ADC_SMPR1_SMP13_Pos (9U)
+#define ADC_SMPR1_SMP13_Msk (0x7U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000E00 */
+#define ADC_SMPR1_SMP13 ADC_SMPR1_SMP13_Msk /*!< ADC channel 13 sampling time selection */
+#define ADC_SMPR1_SMP13_0 (0x1U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000200 */
+#define ADC_SMPR1_SMP13_1 (0x2U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000400 */
+#define ADC_SMPR1_SMP13_2 (0x4U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000800 */
+
+#define ADC_SMPR1_SMP14_Pos (12U)
+#define ADC_SMPR1_SMP14_Msk (0x7U << ADC_SMPR1_SMP14_Pos) /*!< 0x00007000 */
+#define ADC_SMPR1_SMP14 ADC_SMPR1_SMP14_Msk /*!< ADC channel 14 sampling time selection */
+#define ADC_SMPR1_SMP14_0 (0x1U << ADC_SMPR1_SMP14_Pos) /*!< 0x00001000 */
+#define ADC_SMPR1_SMP14_1 (0x2U << ADC_SMPR1_SMP14_Pos) /*!< 0x00002000 */
+#define ADC_SMPR1_SMP14_2 (0x4U << ADC_SMPR1_SMP14_Pos) /*!< 0x00004000 */
+
+#define ADC_SMPR1_SMP15_Pos (15U)
+#define ADC_SMPR1_SMP15_Msk (0x7U << ADC_SMPR1_SMP15_Pos) /*!< 0x00038000 */
+#define ADC_SMPR1_SMP15 ADC_SMPR1_SMP15_Msk /*!< ADC channel 15 sampling time selection */
+#define ADC_SMPR1_SMP15_0 (0x1U << ADC_SMPR1_SMP15_Pos) /*!< 0x00008000 */
+#define ADC_SMPR1_SMP15_1 (0x2U << ADC_SMPR1_SMP15_Pos) /*!< 0x00010000 */
+#define ADC_SMPR1_SMP15_2 (0x4U << ADC_SMPR1_SMP15_Pos) /*!< 0x00020000 */
+
+#define ADC_SMPR1_SMP16_Pos (18U)
+#define ADC_SMPR1_SMP16_Msk (0x7U << ADC_SMPR1_SMP16_Pos) /*!< 0x001C0000 */
+#define ADC_SMPR1_SMP16 ADC_SMPR1_SMP16_Msk /*!< ADC channel 16 sampling time selection */
+#define ADC_SMPR1_SMP16_0 (0x1U << ADC_SMPR1_SMP16_Pos) /*!< 0x00040000 */
+#define ADC_SMPR1_SMP16_1 (0x2U << ADC_SMPR1_SMP16_Pos) /*!< 0x00080000 */
+#define ADC_SMPR1_SMP16_2 (0x4U << ADC_SMPR1_SMP16_Pos) /*!< 0x00100000 */
+
+#define ADC_SMPR1_SMP17_Pos (21U)
+#define ADC_SMPR1_SMP17_Msk (0x7U << ADC_SMPR1_SMP17_Pos) /*!< 0x00E00000 */
+#define ADC_SMPR1_SMP17 ADC_SMPR1_SMP17_Msk /*!< ADC channel 17 sampling time selection */
+#define ADC_SMPR1_SMP17_0 (0x1U << ADC_SMPR1_SMP17_Pos) /*!< 0x00200000 */
+#define ADC_SMPR1_SMP17_1 (0x2U << ADC_SMPR1_SMP17_Pos) /*!< 0x00400000 */
+#define ADC_SMPR1_SMP17_2 (0x4U << ADC_SMPR1_SMP17_Pos) /*!< 0x00800000 */
+
+/****************** Bit definition for ADC_SMPR2 register *******************/
+#define ADC_SMPR2_SMP0_Pos (0U)
+#define ADC_SMPR2_SMP0_Msk (0x7U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000007 */
+#define ADC_SMPR2_SMP0 ADC_SMPR2_SMP0_Msk /*!< ADC channel 0 sampling time selection */
+#define ADC_SMPR2_SMP0_0 (0x1U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000001 */
+#define ADC_SMPR2_SMP0_1 (0x2U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000002 */
+#define ADC_SMPR2_SMP0_2 (0x4U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000004 */
+
+#define ADC_SMPR2_SMP1_Pos (3U)
+#define ADC_SMPR2_SMP1_Msk (0x7U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000038 */
+#define ADC_SMPR2_SMP1 ADC_SMPR2_SMP1_Msk /*!< ADC channel 1 sampling time selection */
+#define ADC_SMPR2_SMP1_0 (0x1U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000008 */
+#define ADC_SMPR2_SMP1_1 (0x2U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000010 */
+#define ADC_SMPR2_SMP1_2 (0x4U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000020 */
+
+#define ADC_SMPR2_SMP2_Pos (6U)
+#define ADC_SMPR2_SMP2_Msk (0x7U << ADC_SMPR2_SMP2_Pos) /*!< 0x000001C0 */
+#define ADC_SMPR2_SMP2 ADC_SMPR2_SMP2_Msk /*!< ADC channel 2 sampling time selection */
+#define ADC_SMPR2_SMP2_0 (0x1U << ADC_SMPR2_SMP2_Pos) /*!< 0x00000040 */
+#define ADC_SMPR2_SMP2_1 (0x2U << ADC_SMPR2_SMP2_Pos) /*!< 0x00000080 */
+#define ADC_SMPR2_SMP2_2 (0x4U << ADC_SMPR2_SMP2_Pos) /*!< 0x00000100 */
+
+#define ADC_SMPR2_SMP3_Pos (9U)
+#define ADC_SMPR2_SMP3_Msk (0x7U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000E00 */
+#define ADC_SMPR2_SMP3 ADC_SMPR2_SMP3_Msk /*!< ADC channel 3 sampling time selection */
+#define ADC_SMPR2_SMP3_0 (0x1U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000200 */
+#define ADC_SMPR2_SMP3_1 (0x2U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000400 */
+#define ADC_SMPR2_SMP3_2 (0x4U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000800 */
+
+#define ADC_SMPR2_SMP4_Pos (12U)
+#define ADC_SMPR2_SMP4_Msk (0x7U << ADC_SMPR2_SMP4_Pos) /*!< 0x00007000 */
+#define ADC_SMPR2_SMP4 ADC_SMPR2_SMP4_Msk /*!< ADC channel 4 sampling time selection */
+#define ADC_SMPR2_SMP4_0 (0x1U << ADC_SMPR2_SMP4_Pos) /*!< 0x00001000 */
+#define ADC_SMPR2_SMP4_1 (0x2U << ADC_SMPR2_SMP4_Pos) /*!< 0x00002000 */
+#define ADC_SMPR2_SMP4_2 (0x4U << ADC_SMPR2_SMP4_Pos) /*!< 0x00004000 */
+
+#define ADC_SMPR2_SMP5_Pos (15U)
+#define ADC_SMPR2_SMP5_Msk (0x7U << ADC_SMPR2_SMP5_Pos) /*!< 0x00038000 */
+#define ADC_SMPR2_SMP5 ADC_SMPR2_SMP5_Msk /*!< ADC channel 5 sampling time selection */
+#define ADC_SMPR2_SMP5_0 (0x1U << ADC_SMPR2_SMP5_Pos) /*!< 0x00008000 */
+#define ADC_SMPR2_SMP5_1 (0x2U << ADC_SMPR2_SMP5_Pos) /*!< 0x00010000 */
+#define ADC_SMPR2_SMP5_2 (0x4U << ADC_SMPR2_SMP5_Pos) /*!< 0x00020000 */
+
+#define ADC_SMPR2_SMP6_Pos (18U)
+#define ADC_SMPR2_SMP6_Msk (0x7U << ADC_SMPR2_SMP6_Pos) /*!< 0x001C0000 */
+#define ADC_SMPR2_SMP6 ADC_SMPR2_SMP6_Msk /*!< ADC channel 6 sampling time selection */
+#define ADC_SMPR2_SMP6_0 (0x1U << ADC_SMPR2_SMP6_Pos) /*!< 0x00040000 */
+#define ADC_SMPR2_SMP6_1 (0x2U << ADC_SMPR2_SMP6_Pos) /*!< 0x00080000 */
+#define ADC_SMPR2_SMP6_2 (0x4U << ADC_SMPR2_SMP6_Pos) /*!< 0x00100000 */
+
+#define ADC_SMPR2_SMP7_Pos (21U)
+#define ADC_SMPR2_SMP7_Msk (0x7U << ADC_SMPR2_SMP7_Pos) /*!< 0x00E00000 */
+#define ADC_SMPR2_SMP7 ADC_SMPR2_SMP7_Msk /*!< ADC channel 7 sampling time selection */
+#define ADC_SMPR2_SMP7_0 (0x1U << ADC_SMPR2_SMP7_Pos) /*!< 0x00200000 */
+#define ADC_SMPR2_SMP7_1 (0x2U << ADC_SMPR2_SMP7_Pos) /*!< 0x00400000 */
+#define ADC_SMPR2_SMP7_2 (0x4U << ADC_SMPR2_SMP7_Pos) /*!< 0x00800000 */
+
+#define ADC_SMPR2_SMP8_Pos (24U)
+#define ADC_SMPR2_SMP8_Msk (0x7U << ADC_SMPR2_SMP8_Pos) /*!< 0x07000000 */
+#define ADC_SMPR2_SMP8 ADC_SMPR2_SMP8_Msk /*!< ADC channel 8 sampling time selection */
+#define ADC_SMPR2_SMP8_0 (0x1U << ADC_SMPR2_SMP8_Pos) /*!< 0x01000000 */
+#define ADC_SMPR2_SMP8_1 (0x2U << ADC_SMPR2_SMP8_Pos) /*!< 0x02000000 */
+#define ADC_SMPR2_SMP8_2 (0x4U << ADC_SMPR2_SMP8_Pos) /*!< 0x04000000 */
+
+#define ADC_SMPR2_SMP9_Pos (27U)
+#define ADC_SMPR2_SMP9_Msk (0x7U << ADC_SMPR2_SMP9_Pos) /*!< 0x38000000 */
+#define ADC_SMPR2_SMP9 ADC_SMPR2_SMP9_Msk /*!< ADC channel 9 sampling time selection */
+#define ADC_SMPR2_SMP9_0 (0x1U << ADC_SMPR2_SMP9_Pos) /*!< 0x08000000 */
+#define ADC_SMPR2_SMP9_1 (0x2U << ADC_SMPR2_SMP9_Pos) /*!< 0x10000000 */
+#define ADC_SMPR2_SMP9_2 (0x4U << ADC_SMPR2_SMP9_Pos) /*!< 0x20000000 */
+
+/****************** Bit definition for ADC_JOFR1 register *******************/
+#define ADC_JOFR1_JOFFSET1_Pos (0U)
+#define ADC_JOFR1_JOFFSET1_Msk (0xFFFU << ADC_JOFR1_JOFFSET1_Pos) /*!< 0x00000FFF */
+#define ADC_JOFR1_JOFFSET1 ADC_JOFR1_JOFFSET1_Msk /*!< ADC group injected sequencer rank 1 offset value */
+
+/****************** Bit definition for ADC_JOFR2 register *******************/
+#define ADC_JOFR2_JOFFSET2_Pos (0U)
+#define ADC_JOFR2_JOFFSET2_Msk (0xFFFU << ADC_JOFR2_JOFFSET2_Pos) /*!< 0x00000FFF */
+#define ADC_JOFR2_JOFFSET2 ADC_JOFR2_JOFFSET2_Msk /*!< ADC group injected sequencer rank 2 offset value */
+
+/****************** Bit definition for ADC_JOFR3 register *******************/
+#define ADC_JOFR3_JOFFSET3_Pos (0U)
+#define ADC_JOFR3_JOFFSET3_Msk (0xFFFU << ADC_JOFR3_JOFFSET3_Pos) /*!< 0x00000FFF */
+#define ADC_JOFR3_JOFFSET3 ADC_JOFR3_JOFFSET3_Msk /*!< ADC group injected sequencer rank 3 offset value */
+
+/****************** Bit definition for ADC_JOFR4 register *******************/
+#define ADC_JOFR4_JOFFSET4_Pos (0U)
+#define ADC_JOFR4_JOFFSET4_Msk (0xFFFU << ADC_JOFR4_JOFFSET4_Pos) /*!< 0x00000FFF */
+#define ADC_JOFR4_JOFFSET4 ADC_JOFR4_JOFFSET4_Msk /*!< ADC group injected sequencer rank 4 offset value */
+
+/******************* Bit definition for ADC_HTR register ********************/
+#define ADC_HTR_HT_Pos (0U)
+#define ADC_HTR_HT_Msk (0xFFFU << ADC_HTR_HT_Pos) /*!< 0x00000FFF */
+#define ADC_HTR_HT ADC_HTR_HT_Msk /*!< ADC analog watchdog 1 threshold high */
+
+/******************* Bit definition for ADC_LTR register ********************/
+#define ADC_LTR_LT_Pos (0U)
+#define ADC_LTR_LT_Msk (0xFFFU << ADC_LTR_LT_Pos) /*!< 0x00000FFF */
+#define ADC_LTR_LT ADC_LTR_LT_Msk /*!< ADC analog watchdog 1 threshold low */
+
+/******************* Bit definition for ADC_SQR1 register *******************/
+#define ADC_SQR1_SQ13_Pos (0U)
+#define ADC_SQR1_SQ13_Msk (0x1FU << ADC_SQR1_SQ13_Pos) /*!< 0x0000001F */
+#define ADC_SQR1_SQ13 ADC_SQR1_SQ13_Msk /*!< ADC group regular sequencer rank 13 */
+#define ADC_SQR1_SQ13_0 (0x01U << ADC_SQR1_SQ13_Pos) /*!< 0x00000001 */
+#define ADC_SQR1_SQ13_1 (0x02U << ADC_SQR1_SQ13_Pos) /*!< 0x00000002 */
+#define ADC_SQR1_SQ13_2 (0x04U << ADC_SQR1_SQ13_Pos) /*!< 0x00000004 */
+#define ADC_SQR1_SQ13_3 (0x08U << ADC_SQR1_SQ13_Pos) /*!< 0x00000008 */
+#define ADC_SQR1_SQ13_4 (0x10U << ADC_SQR1_SQ13_Pos) /*!< 0x00000010 */
+
+#define ADC_SQR1_SQ14_Pos (5U)
+#define ADC_SQR1_SQ14_Msk (0x1FU << ADC_SQR1_SQ14_Pos) /*!< 0x000003E0 */
+#define ADC_SQR1_SQ14 ADC_SQR1_SQ14_Msk /*!< ADC group regular sequencer rank 14 */
+#define ADC_SQR1_SQ14_0 (0x01U << ADC_SQR1_SQ14_Pos) /*!< 0x00000020 */
+#define ADC_SQR1_SQ14_1 (0x02U << ADC_SQR1_SQ14_Pos) /*!< 0x00000040 */
+#define ADC_SQR1_SQ14_2 (0x04U << ADC_SQR1_SQ14_Pos) /*!< 0x00000080 */
+#define ADC_SQR1_SQ14_3 (0x08U << ADC_SQR1_SQ14_Pos) /*!< 0x00000100 */
+#define ADC_SQR1_SQ14_4 (0x10U << ADC_SQR1_SQ14_Pos) /*!< 0x00000200 */
+
+#define ADC_SQR1_SQ15_Pos (10U)
+#define ADC_SQR1_SQ15_Msk (0x1FU << ADC_SQR1_SQ15_Pos) /*!< 0x00007C00 */
+#define ADC_SQR1_SQ15 ADC_SQR1_SQ15_Msk /*!< ADC group regular sequencer rank 15 */
+#define ADC_SQR1_SQ15_0 (0x01U << ADC_SQR1_SQ15_Pos) /*!< 0x00000400 */
+#define ADC_SQR1_SQ15_1 (0x02U << ADC_SQR1_SQ15_Pos) /*!< 0x00000800 */
+#define ADC_SQR1_SQ15_2 (0x04U << ADC_SQR1_SQ15_Pos) /*!< 0x00001000 */
+#define ADC_SQR1_SQ15_3 (0x08U << ADC_SQR1_SQ15_Pos) /*!< 0x00002000 */
+#define ADC_SQR1_SQ15_4 (0x10U << ADC_SQR1_SQ15_Pos) /*!< 0x00004000 */
+
+#define ADC_SQR1_SQ16_Pos (15U)
+#define ADC_SQR1_SQ16_Msk (0x1FU << ADC_SQR1_SQ16_Pos) /*!< 0x000F8000 */
+#define ADC_SQR1_SQ16 ADC_SQR1_SQ16_Msk /*!< ADC group regular sequencer rank 16 */
+#define ADC_SQR1_SQ16_0 (0x01U << ADC_SQR1_SQ16_Pos) /*!< 0x00008000 */
+#define ADC_SQR1_SQ16_1 (0x02U << ADC_SQR1_SQ16_Pos) /*!< 0x00010000 */
+#define ADC_SQR1_SQ16_2 (0x04U << ADC_SQR1_SQ16_Pos) /*!< 0x00020000 */
+#define ADC_SQR1_SQ16_3 (0x08U << ADC_SQR1_SQ16_Pos) /*!< 0x00040000 */
+#define ADC_SQR1_SQ16_4 (0x10U << ADC_SQR1_SQ16_Pos) /*!< 0x00080000 */
+
+#define ADC_SQR1_L_Pos (20U)
+#define ADC_SQR1_L_Msk (0xFU << ADC_SQR1_L_Pos) /*!< 0x00F00000 */
+#define ADC_SQR1_L ADC_SQR1_L_Msk /*!< ADC group regular sequencer scan length */
+#define ADC_SQR1_L_0 (0x1U << ADC_SQR1_L_Pos) /*!< 0x00100000 */
+#define ADC_SQR1_L_1 (0x2U << ADC_SQR1_L_Pos) /*!< 0x00200000 */
+#define ADC_SQR1_L_2 (0x4U << ADC_SQR1_L_Pos) /*!< 0x00400000 */
+#define ADC_SQR1_L_3 (0x8U << ADC_SQR1_L_Pos) /*!< 0x00800000 */
+
+/******************* Bit definition for ADC_SQR2 register *******************/
+#define ADC_SQR2_SQ7_Pos (0U)
+#define ADC_SQR2_SQ7_Msk (0x1FU << ADC_SQR2_SQ7_Pos) /*!< 0x0000001F */
+#define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk /*!< ADC group regular sequencer rank 7 */
+#define ADC_SQR2_SQ7_0 (0x01U << ADC_SQR2_SQ7_Pos) /*!< 0x00000001 */
+#define ADC_SQR2_SQ7_1 (0x02U << ADC_SQR2_SQ7_Pos) /*!< 0x00000002 */
+#define ADC_SQR2_SQ7_2 (0x04U << ADC_SQR2_SQ7_Pos) /*!< 0x00000004 */
+#define ADC_SQR2_SQ7_3 (0x08U << ADC_SQR2_SQ7_Pos) /*!< 0x00000008 */
+#define ADC_SQR2_SQ7_4 (0x10U << ADC_SQR2_SQ7_Pos) /*!< 0x00000010 */
+
+#define ADC_SQR2_SQ8_Pos (5U)
+#define ADC_SQR2_SQ8_Msk (0x1FU << ADC_SQR2_SQ8_Pos) /*!< 0x000003E0 */
+#define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk /*!< ADC group regular sequencer rank 8 */
+#define ADC_SQR2_SQ8_0 (0x01U << ADC_SQR2_SQ8_Pos) /*!< 0x00000020 */
+#define ADC_SQR2_SQ8_1 (0x02U << ADC_SQR2_SQ8_Pos) /*!< 0x00000040 */
+#define ADC_SQR2_SQ8_2 (0x04U << ADC_SQR2_SQ8_Pos) /*!< 0x00000080 */
+#define ADC_SQR2_SQ8_3 (0x08U << ADC_SQR2_SQ8_Pos) /*!< 0x00000100 */
+#define ADC_SQR2_SQ8_4 (0x10U << ADC_SQR2_SQ8_Pos) /*!< 0x00000200 */
+
+#define ADC_SQR2_SQ9_Pos (10U)
+#define ADC_SQR2_SQ9_Msk (0x1FU << ADC_SQR2_SQ9_Pos) /*!< 0x00007C00 */
+#define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk /*!< ADC group regular sequencer rank 9 */
+#define ADC_SQR2_SQ9_0 (0x01U << ADC_SQR2_SQ9_Pos) /*!< 0x00000400 */
+#define ADC_SQR2_SQ9_1 (0x02U << ADC_SQR2_SQ9_Pos) /*!< 0x00000800 */
+#define ADC_SQR2_SQ9_2 (0x04U << ADC_SQR2_SQ9_Pos) /*!< 0x00001000 */
+#define ADC_SQR2_SQ9_3 (0x08U << ADC_SQR2_SQ9_Pos) /*!< 0x00002000 */
+#define ADC_SQR2_SQ9_4 (0x10U << ADC_SQR2_SQ9_Pos) /*!< 0x00004000 */
+
+#define ADC_SQR2_SQ10_Pos (15U)
+#define ADC_SQR2_SQ10_Msk (0x1FU << ADC_SQR2_SQ10_Pos) /*!< 0x000F8000 */
+#define ADC_SQR2_SQ10 ADC_SQR2_SQ10_Msk /*!< ADC group regular sequencer rank 10 */
+#define ADC_SQR2_SQ10_0 (0x01U << ADC_SQR2_SQ10_Pos) /*!< 0x00008000 */
+#define ADC_SQR2_SQ10_1 (0x02U << ADC_SQR2_SQ10_Pos) /*!< 0x00010000 */
+#define ADC_SQR2_SQ10_2 (0x04U << ADC_SQR2_SQ10_Pos) /*!< 0x00020000 */
+#define ADC_SQR2_SQ10_3 (0x08U << ADC_SQR2_SQ10_Pos) /*!< 0x00040000 */
+#define ADC_SQR2_SQ10_4 (0x10U << ADC_SQR2_SQ10_Pos) /*!< 0x00080000 */
+
+#define ADC_SQR2_SQ11_Pos (20U)
+#define ADC_SQR2_SQ11_Msk (0x1FU << ADC_SQR2_SQ11_Pos) /*!< 0x01F00000 */
+#define ADC_SQR2_SQ11 ADC_SQR2_SQ11_Msk /*!< ADC group regular sequencer rank 1 */
+#define ADC_SQR2_SQ11_0 (0x01U << ADC_SQR2_SQ11_Pos) /*!< 0x00100000 */
+#define ADC_SQR2_SQ11_1 (0x02U << ADC_SQR2_SQ11_Pos) /*!< 0x00200000 */
+#define ADC_SQR2_SQ11_2 (0x04U << ADC_SQR2_SQ11_Pos) /*!< 0x00400000 */
+#define ADC_SQR2_SQ11_3 (0x08U << ADC_SQR2_SQ11_Pos) /*!< 0x00800000 */
+#define ADC_SQR2_SQ11_4 (0x10U << ADC_SQR2_SQ11_Pos) /*!< 0x01000000 */
+
+#define ADC_SQR2_SQ12_Pos (25U)
+#define ADC_SQR2_SQ12_Msk (0x1FU << ADC_SQR2_SQ12_Pos) /*!< 0x3E000000 */
+#define ADC_SQR2_SQ12 ADC_SQR2_SQ12_Msk /*!< ADC group regular sequencer rank 12 */
+#define ADC_SQR2_SQ12_0 (0x01U << ADC_SQR2_SQ12_Pos) /*!< 0x02000000 */
+#define ADC_SQR2_SQ12_1 (0x02U << ADC_SQR2_SQ12_Pos) /*!< 0x04000000 */
+#define ADC_SQR2_SQ12_2 (0x04U << ADC_SQR2_SQ12_Pos) /*!< 0x08000000 */
+#define ADC_SQR2_SQ12_3 (0x08U << ADC_SQR2_SQ12_Pos) /*!< 0x10000000 */
+#define ADC_SQR2_SQ12_4 (0x10U << ADC_SQR2_SQ12_Pos) /*!< 0x20000000 */
+
+/******************* Bit definition for ADC_SQR3 register *******************/
+#define ADC_SQR3_SQ1_Pos (0U)
+#define ADC_SQR3_SQ1_Msk (0x1FU << ADC_SQR3_SQ1_Pos) /*!< 0x0000001F */
+#define ADC_SQR3_SQ1 ADC_SQR3_SQ1_Msk /*!< ADC group regular sequencer rank 1 */
+#define ADC_SQR3_SQ1_0 (0x01U << ADC_SQR3_SQ1_Pos) /*!< 0x00000001 */
+#define ADC_SQR3_SQ1_1 (0x02U << ADC_SQR3_SQ1_Pos) /*!< 0x00000002 */
+#define ADC_SQR3_SQ1_2 (0x04U << ADC_SQR3_SQ1_Pos) /*!< 0x00000004 */
+#define ADC_SQR3_SQ1_3 (0x08U << ADC_SQR3_SQ1_Pos) /*!< 0x00000008 */
+#define ADC_SQR3_SQ1_4 (0x10U << ADC_SQR3_SQ1_Pos) /*!< 0x00000010 */
+
+#define ADC_SQR3_SQ2_Pos (5U)
+#define ADC_SQR3_SQ2_Msk (0x1FU << ADC_SQR3_SQ2_Pos) /*!< 0x000003E0 */
+#define ADC_SQR3_SQ2 ADC_SQR3_SQ2_Msk /*!< ADC group regular sequencer rank 2 */
+#define ADC_SQR3_SQ2_0 (0x01U << ADC_SQR3_SQ2_Pos) /*!< 0x00000020 */
+#define ADC_SQR3_SQ2_1 (0x02U << ADC_SQR3_SQ2_Pos) /*!< 0x00000040 */
+#define ADC_SQR3_SQ2_2 (0x04U << ADC_SQR3_SQ2_Pos) /*!< 0x00000080 */
+#define ADC_SQR3_SQ2_3 (0x08U << ADC_SQR3_SQ2_Pos) /*!< 0x00000100 */
+#define ADC_SQR3_SQ2_4 (0x10U << ADC_SQR3_SQ2_Pos) /*!< 0x00000200 */
+
+#define ADC_SQR3_SQ3_Pos (10U)
+#define ADC_SQR3_SQ3_Msk (0x1FU << ADC_SQR3_SQ3_Pos) /*!< 0x00007C00 */
+#define ADC_SQR3_SQ3 ADC_SQR3_SQ3_Msk /*!< ADC group regular sequencer rank 3 */
+#define ADC_SQR3_SQ3_0 (0x01U << ADC_SQR3_SQ3_Pos) /*!< 0x00000400 */
+#define ADC_SQR3_SQ3_1 (0x02U << ADC_SQR3_SQ3_Pos) /*!< 0x00000800 */
+#define ADC_SQR3_SQ3_2 (0x04U << ADC_SQR3_SQ3_Pos) /*!< 0x00001000 */
+#define ADC_SQR3_SQ3_3 (0x08U << ADC_SQR3_SQ3_Pos) /*!< 0x00002000 */
+#define ADC_SQR3_SQ3_4 (0x10U << ADC_SQR3_SQ3_Pos) /*!< 0x00004000 */
+
+#define ADC_SQR3_SQ4_Pos (15U)
+#define ADC_SQR3_SQ4_Msk (0x1FU << ADC_SQR3_SQ4_Pos) /*!< 0x000F8000 */
+#define ADC_SQR3_SQ4 ADC_SQR3_SQ4_Msk /*!< ADC group regular sequencer rank 4 */
+#define ADC_SQR3_SQ4_0 (0x01U << ADC_SQR3_SQ4_Pos) /*!< 0x00008000 */
+#define ADC_SQR3_SQ4_1 (0x02U << ADC_SQR3_SQ4_Pos) /*!< 0x00010000 */
+#define ADC_SQR3_SQ4_2 (0x04U << ADC_SQR3_SQ4_Pos) /*!< 0x00020000 */
+#define ADC_SQR3_SQ4_3 (0x08U << ADC_SQR3_SQ4_Pos) /*!< 0x00040000 */
+#define ADC_SQR3_SQ4_4 (0x10U << ADC_SQR3_SQ4_Pos) /*!< 0x00080000 */
+
+#define ADC_SQR3_SQ5_Pos (20U)
+#define ADC_SQR3_SQ5_Msk (0x1FU << ADC_SQR3_SQ5_Pos) /*!< 0x01F00000 */
+#define ADC_SQR3_SQ5 ADC_SQR3_SQ5_Msk /*!< ADC group regular sequencer rank 5 */
+#define ADC_SQR3_SQ5_0 (0x01U << ADC_SQR3_SQ5_Pos) /*!< 0x00100000 */
+#define ADC_SQR3_SQ5_1 (0x02U << ADC_SQR3_SQ5_Pos) /*!< 0x00200000 */
+#define ADC_SQR3_SQ5_2 (0x04U << ADC_SQR3_SQ5_Pos) /*!< 0x00400000 */
+#define ADC_SQR3_SQ5_3 (0x08U << ADC_SQR3_SQ5_Pos) /*!< 0x00800000 */
+#define ADC_SQR3_SQ5_4 (0x10U << ADC_SQR3_SQ5_Pos) /*!< 0x01000000 */
+
+#define ADC_SQR3_SQ6_Pos (25U)
+#define ADC_SQR3_SQ6_Msk (0x1FU << ADC_SQR3_SQ6_Pos) /*!< 0x3E000000 */
+#define ADC_SQR3_SQ6 ADC_SQR3_SQ6_Msk /*!< ADC group regular sequencer rank 6 */
+#define ADC_SQR3_SQ6_0 (0x01U << ADC_SQR3_SQ6_Pos) /*!< 0x02000000 */
+#define ADC_SQR3_SQ6_1 (0x02U << ADC_SQR3_SQ6_Pos) /*!< 0x04000000 */
+#define ADC_SQR3_SQ6_2 (0x04U << ADC_SQR3_SQ6_Pos) /*!< 0x08000000 */
+#define ADC_SQR3_SQ6_3 (0x08U << ADC_SQR3_SQ6_Pos) /*!< 0x10000000 */
+#define ADC_SQR3_SQ6_4 (0x10U << ADC_SQR3_SQ6_Pos) /*!< 0x20000000 */
+
+/******************* Bit definition for ADC_JSQR register *******************/
+#define ADC_JSQR_JSQ1_Pos (0U)
+#define ADC_JSQR_JSQ1_Msk (0x1FU << ADC_JSQR_JSQ1_Pos) /*!< 0x0000001F */
+#define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!< ADC group injected sequencer rank 1 */
+#define ADC_JSQR_JSQ1_0 (0x01U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000001 */
+#define ADC_JSQR_JSQ1_1 (0x02U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000002 */
+#define ADC_JSQR_JSQ1_2 (0x04U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000004 */
+#define ADC_JSQR_JSQ1_3 (0x08U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000008 */
+#define ADC_JSQR_JSQ1_4 (0x10U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000010 */
+
+#define ADC_JSQR_JSQ2_Pos (5U)
+#define ADC_JSQR_JSQ2_Msk (0x1FU << ADC_JSQR_JSQ2_Pos) /*!< 0x000003E0 */
+#define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!< ADC group injected sequencer rank 2 */
+#define ADC_JSQR_JSQ2_0 (0x01U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000020 */
+#define ADC_JSQR_JSQ2_1 (0x02U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000040 */
+#define ADC_JSQR_JSQ2_2 (0x04U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000080 */
+#define ADC_JSQR_JSQ2_3 (0x08U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000100 */
+#define ADC_JSQR_JSQ2_4 (0x10U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000200 */
+
+#define ADC_JSQR_JSQ3_Pos (10U)
+#define ADC_JSQR_JSQ3_Msk (0x1FU << ADC_JSQR_JSQ3_Pos) /*!< 0x00007C00 */
+#define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!< ADC group injected sequencer rank 3 */
+#define ADC_JSQR_JSQ3_0 (0x01U << ADC_JSQR_JSQ3_Pos) /*!< 0x00000400 */
+#define ADC_JSQR_JSQ3_1 (0x02U << ADC_JSQR_JSQ3_Pos) /*!< 0x00000800 */
+#define ADC_JSQR_JSQ3_2 (0x04U << ADC_JSQR_JSQ3_Pos) /*!< 0x00001000 */
+#define ADC_JSQR_JSQ3_3 (0x08U << ADC_JSQR_JSQ3_Pos) /*!< 0x00002000 */
+#define ADC_JSQR_JSQ3_4 (0x10U << ADC_JSQR_JSQ3_Pos) /*!< 0x00004000 */
+
+#define ADC_JSQR_JSQ4_Pos (15U)
+#define ADC_JSQR_JSQ4_Msk (0x1FU << ADC_JSQR_JSQ4_Pos) /*!< 0x000F8000 */
+#define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!< ADC group injected sequencer rank 4 */
+#define ADC_JSQR_JSQ4_0 (0x01U << ADC_JSQR_JSQ4_Pos) /*!< 0x00008000 */
+#define ADC_JSQR_JSQ4_1 (0x02U << ADC_JSQR_JSQ4_Pos) /*!< 0x00010000 */
+#define ADC_JSQR_JSQ4_2 (0x04U << ADC_JSQR_JSQ4_Pos) /*!< 0x00020000 */
+#define ADC_JSQR_JSQ4_3 (0x08U << ADC_JSQR_JSQ4_Pos) /*!< 0x00040000 */
+#define ADC_JSQR_JSQ4_4 (0x10U << ADC_JSQR_JSQ4_Pos) /*!< 0x00080000 */
+
+#define ADC_JSQR_JL_Pos (20U)
+#define ADC_JSQR_JL_Msk (0x3U << ADC_JSQR_JL_Pos) /*!< 0x00300000 */
+#define ADC_JSQR_JL ADC_JSQR_JL_Msk /*!< ADC group injected sequencer scan length */
+#define ADC_JSQR_JL_0 (0x1U << ADC_JSQR_JL_Pos) /*!< 0x00100000 */
+#define ADC_JSQR_JL_1 (0x2U << ADC_JSQR_JL_Pos) /*!< 0x00200000 */
+
+/******************* Bit definition for ADC_JDR1 register *******************/
+#define ADC_JDR1_JDATA_Pos (0U)
+#define ADC_JDR1_JDATA_Msk (0xFFFFU << ADC_JDR1_JDATA_Pos) /*!< 0x0000FFFF */
+#define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!< ADC group injected sequencer rank 1 conversion data */
+
+/******************* Bit definition for ADC_JDR2 register *******************/
+#define ADC_JDR2_JDATA_Pos (0U)
+#define ADC_JDR2_JDATA_Msk (0xFFFFU << ADC_JDR2_JDATA_Pos) /*!< 0x0000FFFF */
+#define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!< ADC group injected sequencer rank 2 conversion data */
+
+/******************* Bit definition for ADC_JDR3 register *******************/
+#define ADC_JDR3_JDATA_Pos (0U)
+#define ADC_JDR3_JDATA_Msk (0xFFFFU << ADC_JDR3_JDATA_Pos) /*!< 0x0000FFFF */
+#define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!< ADC group injected sequencer rank 3 conversion data */
+
+/******************* Bit definition for ADC_JDR4 register *******************/
+#define ADC_JDR4_JDATA_Pos (0U)
+#define ADC_JDR4_JDATA_Msk (0xFFFFU << ADC_JDR4_JDATA_Pos) /*!< 0x0000FFFF */
+#define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!< ADC group injected sequencer rank 4 conversion data */
+
+/******************** Bit definition for ADC_DR register ********************/
+#define ADC_DR_DATA_Pos (0U)
+#define ADC_DR_DATA_Msk (0xFFFFU << ADC_DR_DATA_Pos) /*!< 0x0000FFFF */
+#define ADC_DR_DATA ADC_DR_DATA_Msk /*!< ADC group regular conversion data */
+#define ADC_DR_ADC2DATA_Pos (16U)
+#define ADC_DR_ADC2DATA_Msk (0xFFFFU << ADC_DR_ADC2DATA_Pos) /*!< 0xFFFF0000 */
+#define ADC_DR_ADC2DATA ADC_DR_ADC2DATA_Msk /*!< ADC group regular conversion data for ADC slave, in multimode */
+
+
+/*****************************************************************************/
+/* */
+/* Timers (TIM) */
+/* */
+/*****************************************************************************/
+/******************* Bit definition for TIM_CR1 register *******************/
+#define TIM_CR1_CEN_Pos (0U)
+#define TIM_CR1_CEN_Msk (0x1U << TIM_CR1_CEN_Pos) /*!< 0x00000001 */
+#define TIM_CR1_CEN TIM_CR1_CEN_Msk /*!<Counter enable */
+#define TIM_CR1_UDIS_Pos (1U)
+#define TIM_CR1_UDIS_Msk (0x1U << TIM_CR1_UDIS_Pos) /*!< 0x00000002 */
+#define TIM_CR1_UDIS TIM_CR1_UDIS_Msk /*!<Update disable */
+#define TIM_CR1_URS_Pos (2U)
+#define TIM_CR1_URS_Msk (0x1U << TIM_CR1_URS_Pos) /*!< 0x00000004 */
+#define TIM_CR1_URS TIM_CR1_URS_Msk /*!<Update request source */
+#define TIM_CR1_OPM_Pos (3U)
+#define TIM_CR1_OPM_Msk (0x1U << TIM_CR1_OPM_Pos) /*!< 0x00000008 */
+#define TIM_CR1_OPM TIM_CR1_OPM_Msk /*!<One pulse mode */
+#define TIM_CR1_DIR_Pos (4U)
+#define TIM_CR1_DIR_Msk (0x1U << TIM_CR1_DIR_Pos) /*!< 0x00000010 */
+#define TIM_CR1_DIR TIM_CR1_DIR_Msk /*!<Direction */
+
+#define TIM_CR1_CMS_Pos (5U)
+#define TIM_CR1_CMS_Msk (0x3U << TIM_CR1_CMS_Pos) /*!< 0x00000060 */
+#define TIM_CR1_CMS TIM_CR1_CMS_Msk /*!<CMS[1:0] bits (Center-aligned mode selection) */
+#define TIM_CR1_CMS_0 (0x1U << TIM_CR1_CMS_Pos) /*!< 0x00000020 */
+#define TIM_CR1_CMS_1 (0x2U << TIM_CR1_CMS_Pos) /*!< 0x00000040 */
+
+#define TIM_CR1_ARPE_Pos (7U)
+#define TIM_CR1_ARPE_Msk (0x1U << TIM_CR1_ARPE_Pos) /*!< 0x00000080 */
+#define TIM_CR1_ARPE TIM_CR1_ARPE_Msk /*!<Auto-reload preload enable */
+
+#define TIM_CR1_CKD_Pos (8U)
+#define TIM_CR1_CKD_Msk (0x3U << TIM_CR1_CKD_Pos) /*!< 0x00000300 */
+#define TIM_CR1_CKD TIM_CR1_CKD_Msk /*!<CKD[1:0] bits (clock division) */
+#define TIM_CR1_CKD_0 (0x1U << TIM_CR1_CKD_Pos) /*!< 0x00000100 */
+#define TIM_CR1_CKD_1 (0x2U << TIM_CR1_CKD_Pos) /*!< 0x00000200 */
+
+/******************* Bit definition for TIM_CR2 register *******************/
+#define TIM_CR2_CCPC_Pos (0U)
+#define TIM_CR2_CCPC_Msk (0x1U << TIM_CR2_CCPC_Pos) /*!< 0x00000001 */
+#define TIM_CR2_CCPC TIM_CR2_CCPC_Msk /*!<Capture/Compare Preloaded Control */
+#define TIM_CR2_CCUS_Pos (2U)
+#define TIM_CR2_CCUS_Msk (0x1U << TIM_CR2_CCUS_Pos) /*!< 0x00000004 */
+#define TIM_CR2_CCUS TIM_CR2_CCUS_Msk /*!<Capture/Compare Control Update Selection */
+#define TIM_CR2_CCDS_Pos (3U)
+#define TIM_CR2_CCDS_Msk (0x1U << TIM_CR2_CCDS_Pos) /*!< 0x00000008 */
+#define TIM_CR2_CCDS TIM_CR2_CCDS_Msk /*!<Capture/Compare DMA Selection */
+
+#define TIM_CR2_MMS_Pos (4U)
+#define TIM_CR2_MMS_Msk (0x7U << TIM_CR2_MMS_Pos) /*!< 0x00000070 */
+#define TIM_CR2_MMS TIM_CR2_MMS_Msk /*!<MMS[2:0] bits (Master Mode Selection) */
+#define TIM_CR2_MMS_0 (0x1U << TIM_CR2_MMS_Pos) /*!< 0x00000010 */
+#define TIM_CR2_MMS_1 (0x2U << TIM_CR2_MMS_Pos) /*!< 0x00000020 */
+#define TIM_CR2_MMS_2 (0x4U << TIM_CR2_MMS_Pos) /*!< 0x00000040 */
+
+#define TIM_CR2_TI1S_Pos (7U)
+#define TIM_CR2_TI1S_Msk (0x1U << TIM_CR2_TI1S_Pos) /*!< 0x00000080 */
+#define TIM_CR2_TI1S TIM_CR2_TI1S_Msk /*!<TI1 Selection */
+#define TIM_CR2_OIS1_Pos (8U)
+#define TIM_CR2_OIS1_Msk (0x1U << TIM_CR2_OIS1_Pos) /*!< 0x00000100 */
+#define TIM_CR2_OIS1 TIM_CR2_OIS1_Msk /*!<Output Idle state 1 (OC1 output) */
+#define TIM_CR2_OIS1N_Pos (9U)
+#define TIM_CR2_OIS1N_Msk (0x1U << TIM_CR2_OIS1N_Pos) /*!< 0x00000200 */
+#define TIM_CR2_OIS1N TIM_CR2_OIS1N_Msk /*!<Output Idle state 1 (OC1N output) */
+#define TIM_CR2_OIS2_Pos (10U)
+#define TIM_CR2_OIS2_Msk (0x1U << TIM_CR2_OIS2_Pos) /*!< 0x00000400 */
+#define TIM_CR2_OIS2 TIM_CR2_OIS2_Msk /*!<Output Idle state 2 (OC2 output) */
+#define TIM_CR2_OIS2N_Pos (11U)
+#define TIM_CR2_OIS2N_Msk (0x1U << TIM_CR2_OIS2N_Pos) /*!< 0x00000800 */
+#define TIM_CR2_OIS2N TIM_CR2_OIS2N_Msk /*!<Output Idle state 2 (OC2N output) */
+#define TIM_CR2_OIS3_Pos (12U)
+#define TIM_CR2_OIS3_Msk (0x1U << TIM_CR2_OIS3_Pos) /*!< 0x00001000 */
+#define TIM_CR2_OIS3 TIM_CR2_OIS3_Msk /*!<Output Idle state 3 (OC3 output) */
+#define TIM_CR2_OIS3N_Pos (13U)
+#define TIM_CR2_OIS3N_Msk (0x1U << TIM_CR2_OIS3N_Pos) /*!< 0x00002000 */
+#define TIM_CR2_OIS3N TIM_CR2_OIS3N_Msk /*!<Output Idle state 3 (OC3N output) */
+#define TIM_CR2_OIS4_Pos (14U)
+#define TIM_CR2_OIS4_Msk (0x1U << TIM_CR2_OIS4_Pos) /*!< 0x00004000 */
+#define TIM_CR2_OIS4 TIM_CR2_OIS4_Msk /*!<Output Idle state 4 (OC4 output) */
+
+/******************* Bit definition for TIM_SMCR register ******************/
+#define TIM_SMCR_SMS_Pos (0U)
+#define TIM_SMCR_SMS_Msk (0x7U << TIM_SMCR_SMS_Pos) /*!< 0x00000007 */
+#define TIM_SMCR_SMS TIM_SMCR_SMS_Msk /*!<SMS[2:0] bits (Slave mode selection) */
+#define TIM_SMCR_SMS_0 (0x1U << TIM_SMCR_SMS_Pos) /*!< 0x00000001 */
+#define TIM_SMCR_SMS_1 (0x2U << TIM_SMCR_SMS_Pos) /*!< 0x00000002 */
+#define TIM_SMCR_SMS_2 (0x4U << TIM_SMCR_SMS_Pos) /*!< 0x00000004 */
+
+#define TIM_SMCR_OCCS_Pos (3U)
+#define TIM_SMCR_OCCS_Msk (0x1U << TIM_SMCR_OCCS_Pos) /*!< 0x00000008 */
+#define TIM_SMCR_OCCS TIM_SMCR_OCCS_Msk /*!< OCREF clear selection */
+
+#define TIM_SMCR_TS_Pos (4U)
+#define TIM_SMCR_TS_Msk (0x7U << TIM_SMCR_TS_Pos) /*!< 0x00000070 */
+#define TIM_SMCR_TS TIM_SMCR_TS_Msk /*!<TS[2:0] bits (Trigger selection) */
+#define TIM_SMCR_TS_0 (0x1U << TIM_SMCR_TS_Pos) /*!< 0x00000010 */
+#define TIM_SMCR_TS_1 (0x2U << TIM_SMCR_TS_Pos) /*!< 0x00000020 */
+#define TIM_SMCR_TS_2 (0x4U << TIM_SMCR_TS_Pos) /*!< 0x00000040 */
+
+#define TIM_SMCR_MSM_Pos (7U)
+#define TIM_SMCR_MSM_Msk (0x1U << TIM_SMCR_MSM_Pos) /*!< 0x00000080 */
+#define TIM_SMCR_MSM TIM_SMCR_MSM_Msk /*!<Master/slave mode */
+
+#define TIM_SMCR_ETF_Pos (8U)
+#define TIM_SMCR_ETF_Msk (0xFU << TIM_SMCR_ETF_Pos) /*!< 0x00000F00 */
+#define TIM_SMCR_ETF TIM_SMCR_ETF_Msk /*!<ETF[3:0] bits (External trigger filter) */
+#define TIM_SMCR_ETF_0 (0x1U << TIM_SMCR_ETF_Pos) /*!< 0x00000100 */
+#define TIM_SMCR_ETF_1 (0x2U << TIM_SMCR_ETF_Pos) /*!< 0x00000200 */
+#define TIM_SMCR_ETF_2 (0x4U << TIM_SMCR_ETF_Pos) /*!< 0x00000400 */
+#define TIM_SMCR_ETF_3 (0x8U << TIM_SMCR_ETF_Pos) /*!< 0x00000800 */
+
+#define TIM_SMCR_ETPS_Pos (12U)
+#define TIM_SMCR_ETPS_Msk (0x3U << TIM_SMCR_ETPS_Pos) /*!< 0x00003000 */
+#define TIM_SMCR_ETPS TIM_SMCR_ETPS_Msk /*!<ETPS[1:0] bits (External trigger prescaler) */
+#define TIM_SMCR_ETPS_0 (0x1U << TIM_SMCR_ETPS_Pos) /*!< 0x00001000 */
+#define TIM_SMCR_ETPS_1 (0x2U << TIM_SMCR_ETPS_Pos) /*!< 0x00002000 */
+
+#define TIM_SMCR_ECE_Pos (14U)
+#define TIM_SMCR_ECE_Msk (0x1U << TIM_SMCR_ECE_Pos) /*!< 0x00004000 */
+#define TIM_SMCR_ECE TIM_SMCR_ECE_Msk /*!<External clock enable */
+#define TIM_SMCR_ETP_Pos (15U)
+#define TIM_SMCR_ETP_Msk (0x1U << TIM_SMCR_ETP_Pos) /*!< 0x00008000 */
+#define TIM_SMCR_ETP TIM_SMCR_ETP_Msk /*!<External trigger polarity */
+
+/******************* Bit definition for TIM_DIER register ******************/
+#define TIM_DIER_UIE_Pos (0U)
+#define TIM_DIER_UIE_Msk (0x1U << TIM_DIER_UIE_Pos) /*!< 0x00000001 */
+#define TIM_DIER_UIE TIM_DIER_UIE_Msk /*!<Update interrupt enable */
+#define TIM_DIER_CC1IE_Pos (1U)
+#define TIM_DIER_CC1IE_Msk (0x1U << TIM_DIER_CC1IE_Pos) /*!< 0x00000002 */
+#define TIM_DIER_CC1IE TIM_DIER_CC1IE_Msk /*!<Capture/Compare 1 interrupt enable */
+#define TIM_DIER_CC2IE_Pos (2U)
+#define TIM_DIER_CC2IE_Msk (0x1U << TIM_DIER_CC2IE_Pos) /*!< 0x00000004 */
+#define TIM_DIER_CC2IE TIM_DIER_CC2IE_Msk /*!<Capture/Compare 2 interrupt enable */
+#define TIM_DIER_CC3IE_Pos (3U)
+#define TIM_DIER_CC3IE_Msk (0x1U << TIM_DIER_CC3IE_Pos) /*!< 0x00000008 */
+#define TIM_DIER_CC3IE TIM_DIER_CC3IE_Msk /*!<Capture/Compare 3 interrupt enable */
+#define TIM_DIER_CC4IE_Pos (4U)
+#define TIM_DIER_CC4IE_Msk (0x1U << TIM_DIER_CC4IE_Pos) /*!< 0x00000010 */
+#define TIM_DIER_CC4IE TIM_DIER_CC4IE_Msk /*!<Capture/Compare 4 interrupt enable */
+#define TIM_DIER_COMIE_Pos (5U)
+#define TIM_DIER_COMIE_Msk (0x1U << TIM_DIER_COMIE_Pos) /*!< 0x00000020 */
+#define TIM_DIER_COMIE TIM_DIER_COMIE_Msk /*!<COM interrupt enable */
+#define TIM_DIER_TIE_Pos (6U)
+#define TIM_DIER_TIE_Msk (0x1U << TIM_DIER_TIE_Pos) /*!< 0x00000040 */
+#define TIM_DIER_TIE TIM_DIER_TIE_Msk /*!<Trigger interrupt enable */
+#define TIM_DIER_BIE_Pos (7U)
+#define TIM_DIER_BIE_Msk (0x1U << TIM_DIER_BIE_Pos) /*!< 0x00000080 */
+#define TIM_DIER_BIE TIM_DIER_BIE_Msk /*!<Break interrupt enable */
+#define TIM_DIER_UDE_Pos (8U)
+#define TIM_DIER_UDE_Msk (0x1U << TIM_DIER_UDE_Pos) /*!< 0x00000100 */
+#define TIM_DIER_UDE TIM_DIER_UDE_Msk /*!<Update DMA request enable */
+#define TIM_DIER_CC1DE_Pos (9U)
+#define TIM_DIER_CC1DE_Msk (0x1U << TIM_DIER_CC1DE_Pos) /*!< 0x00000200 */
+#define TIM_DIER_CC1DE TIM_DIER_CC1DE_Msk /*!<Capture/Compare 1 DMA request enable */
+#define TIM_DIER_CC2DE_Pos (10U)
+#define TIM_DIER_CC2DE_Msk (0x1U << TIM_DIER_CC2DE_Pos) /*!< 0x00000400 */
+#define TIM_DIER_CC2DE TIM_DIER_CC2DE_Msk /*!<Capture/Compare 2 DMA request enable */
+#define TIM_DIER_CC3DE_Pos (11U)
+#define TIM_DIER_CC3DE_Msk (0x1U << TIM_DIER_CC3DE_Pos) /*!< 0x00000800 */
+#define TIM_DIER_CC3DE TIM_DIER_CC3DE_Msk /*!<Capture/Compare 3 DMA request enable */
+#define TIM_DIER_CC4DE_Pos (12U)
+#define TIM_DIER_CC4DE_Msk (0x1U << TIM_DIER_CC4DE_Pos) /*!< 0x00001000 */
+#define TIM_DIER_CC4DE TIM_DIER_CC4DE_Msk /*!<Capture/Compare 4 DMA request enable */
+#define TIM_DIER_COMDE_Pos (13U)
+#define TIM_DIER_COMDE_Msk (0x1U << TIM_DIER_COMDE_Pos) /*!< 0x00002000 */
+#define TIM_DIER_COMDE TIM_DIER_COMDE_Msk /*!<COM DMA request enable */
+#define TIM_DIER_TDE_Pos (14U)
+#define TIM_DIER_TDE_Msk (0x1U << TIM_DIER_TDE_Pos) /*!< 0x00004000 */
+#define TIM_DIER_TDE TIM_DIER_TDE_Msk /*!<Trigger DMA request enable */
+
+/******************** Bit definition for TIM_SR register *******************/
+#define TIM_SR_UIF_Pos (0U)
+#define TIM_SR_UIF_Msk (0x1U << TIM_SR_UIF_Pos) /*!< 0x00000001 */
+#define TIM_SR_UIF TIM_SR_UIF_Msk /*!<Update interrupt Flag */
+#define TIM_SR_CC1IF_Pos (1U)
+#define TIM_SR_CC1IF_Msk (0x1U << TIM_SR_CC1IF_Pos) /*!< 0x00000002 */
+#define TIM_SR_CC1IF TIM_SR_CC1IF_Msk /*!<Capture/Compare 1 interrupt Flag */
+#define TIM_SR_CC2IF_Pos (2U)
+#define TIM_SR_CC2IF_Msk (0x1U << TIM_SR_CC2IF_Pos) /*!< 0x00000004 */
+#define TIM_SR_CC2IF TIM_SR_CC2IF_Msk /*!<Capture/Compare 2 interrupt Flag */
+#define TIM_SR_CC3IF_Pos (3U)
+#define TIM_SR_CC3IF_Msk (0x1U << TIM_SR_CC3IF_Pos) /*!< 0x00000008 */
+#define TIM_SR_CC3IF TIM_SR_CC3IF_Msk /*!<Capture/Compare 3 interrupt Flag */
+#define TIM_SR_CC4IF_Pos (4U)
+#define TIM_SR_CC4IF_Msk (0x1U << TIM_SR_CC4IF_Pos) /*!< 0x00000010 */
+#define TIM_SR_CC4IF TIM_SR_CC4IF_Msk /*!<Capture/Compare 4 interrupt Flag */
+#define TIM_SR_COMIF_Pos (5U)
+#define TIM_SR_COMIF_Msk (0x1U << TIM_SR_COMIF_Pos) /*!< 0x00000020 */
+#define TIM_SR_COMIF TIM_SR_COMIF_Msk /*!<COM interrupt Flag */
+#define TIM_SR_TIF_Pos (6U)
+#define TIM_SR_TIF_Msk (0x1U << TIM_SR_TIF_Pos) /*!< 0x00000040 */
+#define TIM_SR_TIF TIM_SR_TIF_Msk /*!<Trigger interrupt Flag */
+#define TIM_SR_BIF_Pos (7U)
+#define TIM_SR_BIF_Msk (0x1U << TIM_SR_BIF_Pos) /*!< 0x00000080 */
+#define TIM_SR_BIF TIM_SR_BIF_Msk /*!<Break interrupt Flag */
+#define TIM_SR_CC1OF_Pos (9U)
+#define TIM_SR_CC1OF_Msk (0x1U << TIM_SR_CC1OF_Pos) /*!< 0x00000200 */
+#define TIM_SR_CC1OF TIM_SR_CC1OF_Msk /*!<Capture/Compare 1 Overcapture Flag */
+#define TIM_SR_CC2OF_Pos (10U)
+#define TIM_SR_CC2OF_Msk (0x1U << TIM_SR_CC2OF_Pos) /*!< 0x00000400 */
+#define TIM_SR_CC2OF TIM_SR_CC2OF_Msk /*!<Capture/Compare 2 Overcapture Flag */
+#define TIM_SR_CC3OF_Pos (11U)
+#define TIM_SR_CC3OF_Msk (0x1U << TIM_SR_CC3OF_Pos) /*!< 0x00000800 */
+#define TIM_SR_CC3OF TIM_SR_CC3OF_Msk /*!<Capture/Compare 3 Overcapture Flag */
+#define TIM_SR_CC4OF_Pos (12U)
+#define TIM_SR_CC4OF_Msk (0x1U << TIM_SR_CC4OF_Pos) /*!< 0x00001000 */
+#define TIM_SR_CC4OF TIM_SR_CC4OF_Msk /*!<Capture/Compare 4 Overcapture Flag */
+
+/******************* Bit definition for TIM_EGR register *******************/
+#define TIM_EGR_UG_Pos (0U)
+#define TIM_EGR_UG_Msk (0x1U << TIM_EGR_UG_Pos) /*!< 0x00000001 */
+#define TIM_EGR_UG TIM_EGR_UG_Msk /*!<Update Generation */
+#define TIM_EGR_CC1G_Pos (1U)
+#define TIM_EGR_CC1G_Msk (0x1U << TIM_EGR_CC1G_Pos) /*!< 0x00000002 */
+#define TIM_EGR_CC1G TIM_EGR_CC1G_Msk /*!<Capture/Compare 1 Generation */
+#define TIM_EGR_CC2G_Pos (2U)
+#define TIM_EGR_CC2G_Msk (0x1U << TIM_EGR_CC2G_Pos) /*!< 0x00000004 */
+#define TIM_EGR_CC2G TIM_EGR_CC2G_Msk /*!<Capture/Compare 2 Generation */
+#define TIM_EGR_CC3G_Pos (3U)
+#define TIM_EGR_CC3G_Msk (0x1U << TIM_EGR_CC3G_Pos) /*!< 0x00000008 */
+#define TIM_EGR_CC3G TIM_EGR_CC3G_Msk /*!<Capture/Compare 3 Generation */
+#define TIM_EGR_CC4G_Pos (4U)
+#define TIM_EGR_CC4G_Msk (0x1U << TIM_EGR_CC4G_Pos) /*!< 0x00000010 */
+#define TIM_EGR_CC4G TIM_EGR_CC4G_Msk /*!<Capture/Compare 4 Generation */
+#define TIM_EGR_COMG_Pos (5U)
+#define TIM_EGR_COMG_Msk (0x1U << TIM_EGR_COMG_Pos) /*!< 0x00000020 */
+#define TIM_EGR_COMG TIM_EGR_COMG_Msk /*!<Capture/Compare Control Update Generation */
+#define TIM_EGR_TG_Pos (6U)
+#define TIM_EGR_TG_Msk (0x1U << TIM_EGR_TG_Pos) /*!< 0x00000040 */
+#define TIM_EGR_TG TIM_EGR_TG_Msk /*!<Trigger Generation */
+#define TIM_EGR_BG_Pos (7U)
+#define TIM_EGR_BG_Msk (0x1U << TIM_EGR_BG_Pos) /*!< 0x00000080 */
+#define TIM_EGR_BG TIM_EGR_BG_Msk /*!<Break Generation */
+
+/****************** Bit definition for TIM_CCMR1 register ******************/
+#define TIM_CCMR1_CC1S_Pos (0U)
+#define TIM_CCMR1_CC1S_Msk (0x3U << TIM_CCMR1_CC1S_Pos) /*!< 0x00000003 */
+#define TIM_CCMR1_CC1S TIM_CCMR1_CC1S_Msk /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
+#define TIM_CCMR1_CC1S_0 (0x1U << TIM_CCMR1_CC1S_Pos) /*!< 0x00000001 */
+#define TIM_CCMR1_CC1S_1 (0x2U << TIM_CCMR1_CC1S_Pos) /*!< 0x00000002 */
+
+#define TIM_CCMR1_OC1FE_Pos (2U)
+#define TIM_CCMR1_OC1FE_Msk (0x1U << TIM_CCMR1_OC1FE_Pos) /*!< 0x00000004 */
+#define TIM_CCMR1_OC1FE TIM_CCMR1_OC1FE_Msk /*!<Output Compare 1 Fast enable */
+#define TIM_CCMR1_OC1PE_Pos (3U)
+#define TIM_CCMR1_OC1PE_Msk (0x1U << TIM_CCMR1_OC1PE_Pos) /*!< 0x00000008 */
+#define TIM_CCMR1_OC1PE TIM_CCMR1_OC1PE_Msk /*!<Output Compare 1 Preload enable */
+
+#define TIM_CCMR1_OC1M_Pos (4U)
+#define TIM_CCMR1_OC1M_Msk (0x7U << TIM_CCMR1_OC1M_Pos) /*!< 0x00000070 */
+#define TIM_CCMR1_OC1M TIM_CCMR1_OC1M_Msk /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
+#define TIM_CCMR1_OC1M_0 (0x1U << TIM_CCMR1_OC1M_Pos) /*!< 0x00000010 */
+#define TIM_CCMR1_OC1M_1 (0x2U << TIM_CCMR1_OC1M_Pos) /*!< 0x00000020 */
+#define TIM_CCMR1_OC1M_2 (0x4U << TIM_CCMR1_OC1M_Pos) /*!< 0x00000040 */
+
+#define TIM_CCMR1_OC1CE_Pos (7U)
+#define TIM_CCMR1_OC1CE_Msk (0x1U << TIM_CCMR1_OC1CE_Pos) /*!< 0x00000080 */
+#define TIM_CCMR1_OC1CE TIM_CCMR1_OC1CE_Msk /*!<Output Compare 1Clear Enable */
+
+#define TIM_CCMR1_CC2S_Pos (8U)
+#define TIM_CCMR1_CC2S_Msk (0x3U << TIM_CCMR1_CC2S_Pos) /*!< 0x00000300 */
+#define TIM_CCMR1_CC2S TIM_CCMR1_CC2S_Msk /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
+#define TIM_CCMR1_CC2S_0 (0x1U << TIM_CCMR1_CC2S_Pos) /*!< 0x00000100 */
+#define TIM_CCMR1_CC2S_1 (0x2U << TIM_CCMR1_CC2S_Pos) /*!< 0x00000200 */
+
+#define TIM_CCMR1_OC2FE_Pos (10U)
+#define TIM_CCMR1_OC2FE_Msk (0x1U << TIM_CCMR1_OC2FE_Pos) /*!< 0x00000400 */
+#define TIM_CCMR1_OC2FE TIM_CCMR1_OC2FE_Msk /*!<Output Compare 2 Fast enable */
+#define TIM_CCMR1_OC2PE_Pos (11U)
+#define TIM_CCMR1_OC2PE_Msk (0x1U << TIM_CCMR1_OC2PE_Pos) /*!< 0x00000800 */
+#define TIM_CCMR1_OC2PE TIM_CCMR1_OC2PE_Msk /*!<Output Compare 2 Preload enable */
+
+#define TIM_CCMR1_OC2M_Pos (12U)
+#define TIM_CCMR1_OC2M_Msk (0x7U << TIM_CCMR1_OC2M_Pos) /*!< 0x00007000 */
+#define TIM_CCMR1_OC2M TIM_CCMR1_OC2M_Msk /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
+#define TIM_CCMR1_OC2M_0 (0x1U << TIM_CCMR1_OC2M_Pos) /*!< 0x00001000 */
+#define TIM_CCMR1_OC2M_1 (0x2U << TIM_CCMR1_OC2M_Pos) /*!< 0x00002000 */
+#define TIM_CCMR1_OC2M_2 (0x4U << TIM_CCMR1_OC2M_Pos) /*!< 0x00004000 */
+
+#define TIM_CCMR1_OC2CE_Pos (15U)
+#define TIM_CCMR1_OC2CE_Msk (0x1U << TIM_CCMR1_OC2CE_Pos) /*!< 0x00008000 */
+#define TIM_CCMR1_OC2CE TIM_CCMR1_OC2CE_Msk /*!<Output Compare 2 Clear Enable */
+
+/*---------------------------------------------------------------------------*/
+
+#define TIM_CCMR1_IC1PSC_Pos (2U)
+#define TIM_CCMR1_IC1PSC_Msk (0x3U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x0000000C */
+#define TIM_CCMR1_IC1PSC TIM_CCMR1_IC1PSC_Msk /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
+#define TIM_CCMR1_IC1PSC_0 (0x1U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x00000004 */
+#define TIM_CCMR1_IC1PSC_1 (0x2U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x00000008 */
+
+#define TIM_CCMR1_IC1F_Pos (4U)
+#define TIM_CCMR1_IC1F_Msk (0xFU << TIM_CCMR1_IC1F_Pos) /*!< 0x000000F0 */
+#define TIM_CCMR1_IC1F TIM_CCMR1_IC1F_Msk /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
+#define TIM_CCMR1_IC1F_0 (0x1U << TIM_CCMR1_IC1F_Pos) /*!< 0x00000010 */
+#define TIM_CCMR1_IC1F_1 (0x2U << TIM_CCMR1_IC1F_Pos) /*!< 0x00000020 */
+#define TIM_CCMR1_IC1F_2 (0x4U << TIM_CCMR1_IC1F_Pos) /*!< 0x00000040 */
+#define TIM_CCMR1_IC1F_3 (0x8U << TIM_CCMR1_IC1F_Pos) /*!< 0x00000080 */
+
+#define TIM_CCMR1_IC2PSC_Pos (10U)
+#define TIM_CCMR1_IC2PSC_Msk (0x3U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000C00 */
+#define TIM_CCMR1_IC2PSC TIM_CCMR1_IC2PSC_Msk /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
+#define TIM_CCMR1_IC2PSC_0 (0x1U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000400 */
+#define TIM_CCMR1_IC2PSC_1 (0x2U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000800 */
+
+#define TIM_CCMR1_IC2F_Pos (12U)
+#define TIM_CCMR1_IC2F_Msk (0xFU << TIM_CCMR1_IC2F_Pos) /*!< 0x0000F000 */
+#define TIM_CCMR1_IC2F TIM_CCMR1_IC2F_Msk /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
+#define TIM_CCMR1_IC2F_0 (0x1U << TIM_CCMR1_IC2F_Pos) /*!< 0x00001000 */
+#define TIM_CCMR1_IC2F_1 (0x2U << TIM_CCMR1_IC2F_Pos) /*!< 0x00002000 */
+#define TIM_CCMR1_IC2F_2 (0x4U << TIM_CCMR1_IC2F_Pos) /*!< 0x00004000 */
+#define TIM_CCMR1_IC2F_3 (0x8U << TIM_CCMR1_IC2F_Pos) /*!< 0x00008000 */
+
+/****************** Bit definition for TIM_CCMR2 register ******************/
+#define TIM_CCMR2_CC3S_Pos (0U)
+#define TIM_CCMR2_CC3S_Msk (0x3U << TIM_CCMR2_CC3S_Pos) /*!< 0x00000003 */
+#define TIM_CCMR2_CC3S TIM_CCMR2_CC3S_Msk /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
+#define TIM_CCMR2_CC3S_0 (0x1U << TIM_CCMR2_CC3S_Pos) /*!< 0x00000001 */
+#define TIM_CCMR2_CC3S_1 (0x2U << TIM_CCMR2_CC3S_Pos) /*!< 0x00000002 */
+
+#define TIM_CCMR2_OC3FE_Pos (2U)
+#define TIM_CCMR2_OC3FE_Msk (0x1U << TIM_CCMR2_OC3FE_Pos) /*!< 0x00000004 */
+#define TIM_CCMR2_OC3FE TIM_CCMR2_OC3FE_Msk /*!<Output Compare 3 Fast enable */
+#define TIM_CCMR2_OC3PE_Pos (3U)
+#define TIM_CCMR2_OC3PE_Msk (0x1U << TIM_CCMR2_OC3PE_Pos) /*!< 0x00000008 */
+#define TIM_CCMR2_OC3PE TIM_CCMR2_OC3PE_Msk /*!<Output Compare 3 Preload enable */
+
+#define TIM_CCMR2_OC3M_Pos (4U)
+#define TIM_CCMR2_OC3M_Msk (0x7U << TIM_CCMR2_OC3M_Pos) /*!< 0x00000070 */
+#define TIM_CCMR2_OC3M TIM_CCMR2_OC3M_Msk /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
+#define TIM_CCMR2_OC3M_0 (0x1U << TIM_CCMR2_OC3M_Pos) /*!< 0x00000010 */
+#define TIM_CCMR2_OC3M_1 (0x2U << TIM_CCMR2_OC3M_Pos) /*!< 0x00000020 */
+#define TIM_CCMR2_OC3M_2 (0x4U << TIM_CCMR2_OC3M_Pos) /*!< 0x00000040 */
+
+#define TIM_CCMR2_OC3CE_Pos (7U)
+#define TIM_CCMR2_OC3CE_Msk (0x1U << TIM_CCMR2_OC3CE_Pos) /*!< 0x00000080 */
+#define TIM_CCMR2_OC3CE TIM_CCMR2_OC3CE_Msk /*!<Output Compare 3 Clear Enable */
+
+#define TIM_CCMR2_CC4S_Pos (8U)
+#define TIM_CCMR2_CC4S_Msk (0x3U << TIM_CCMR2_CC4S_Pos) /*!< 0x00000300 */
+#define TIM_CCMR2_CC4S TIM_CCMR2_CC4S_Msk /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
+#define TIM_CCMR2_CC4S_0 (0x1U << TIM_CCMR2_CC4S_Pos) /*!< 0x00000100 */
+#define TIM_CCMR2_CC4S_1 (0x2U << TIM_CCMR2_CC4S_Pos) /*!< 0x00000200 */
+
+#define TIM_CCMR2_OC4FE_Pos (10U)
+#define TIM_CCMR2_OC4FE_Msk (0x1U << TIM_CCMR2_OC4FE_Pos) /*!< 0x00000400 */
+#define TIM_CCMR2_OC4FE TIM_CCMR2_OC4FE_Msk /*!<Output Compare 4 Fast enable */
+#define TIM_CCMR2_OC4PE_Pos (11U)
+#define TIM_CCMR2_OC4PE_Msk (0x1U << TIM_CCMR2_OC4PE_Pos) /*!< 0x00000800 */
+#define TIM_CCMR2_OC4PE TIM_CCMR2_OC4PE_Msk /*!<Output Compare 4 Preload enable */
+
+#define TIM_CCMR2_OC4M_Pos (12U)
+#define TIM_CCMR2_OC4M_Msk (0x7U << TIM_CCMR2_OC4M_Pos) /*!< 0x00007000 */
+#define TIM_CCMR2_OC4M TIM_CCMR2_OC4M_Msk /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
+#define TIM_CCMR2_OC4M_0 (0x1U << TIM_CCMR2_OC4M_Pos) /*!< 0x00001000 */
+#define TIM_CCMR2_OC4M_1 (0x2U << TIM_CCMR2_OC4M_Pos) /*!< 0x00002000 */
+#define TIM_CCMR2_OC4M_2 (0x4U << TIM_CCMR2_OC4M_Pos) /*!< 0x00004000 */
+
+#define TIM_CCMR2_OC4CE_Pos (15U)
+#define TIM_CCMR2_OC4CE_Msk (0x1U << TIM_CCMR2_OC4CE_Pos) /*!< 0x00008000 */
+#define TIM_CCMR2_OC4CE TIM_CCMR2_OC4CE_Msk /*!<Output Compare 4 Clear Enable */
+
+/*---------------------------------------------------------------------------*/
+
+#define TIM_CCMR2_IC3PSC_Pos (2U)
+#define TIM_CCMR2_IC3PSC_Msk (0x3U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x0000000C */
+#define TIM_CCMR2_IC3PSC TIM_CCMR2_IC3PSC_Msk /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
+#define TIM_CCMR2_IC3PSC_0 (0x1U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x00000004 */
+#define TIM_CCMR2_IC3PSC_1 (0x2U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x00000008 */
+
+#define TIM_CCMR2_IC3F_Pos (4U)
+#define TIM_CCMR2_IC3F_Msk (0xFU << TIM_CCMR2_IC3F_Pos) /*!< 0x000000F0 */
+#define TIM_CCMR2_IC3F TIM_CCMR2_IC3F_Msk /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
+#define TIM_CCMR2_IC3F_0 (0x1U << TIM_CCMR2_IC3F_Pos) /*!< 0x00000010 */
+#define TIM_CCMR2_IC3F_1 (0x2U << TIM_CCMR2_IC3F_Pos) /*!< 0x00000020 */
+#define TIM_CCMR2_IC3F_2 (0x4U << TIM_CCMR2_IC3F_Pos) /*!< 0x00000040 */
+#define TIM_CCMR2_IC3F_3 (0x8U << TIM_CCMR2_IC3F_Pos) /*!< 0x00000080 */
+
+#define TIM_CCMR2_IC4PSC_Pos (10U)
+#define TIM_CCMR2_IC4PSC_Msk (0x3U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000C00 */
+#define TIM_CCMR2_IC4PSC TIM_CCMR2_IC4PSC_Msk /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
+#define TIM_CCMR2_IC4PSC_0 (0x1U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000400 */
+#define TIM_CCMR2_IC4PSC_1 (0x2U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000800 */
+
+#define TIM_CCMR2_IC4F_Pos (12U)
+#define TIM_CCMR2_IC4F_Msk (0xFU << TIM_CCMR2_IC4F_Pos) /*!< 0x0000F000 */
+#define TIM_CCMR2_IC4F TIM_CCMR2_IC4F_Msk /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
+#define TIM_CCMR2_IC4F_0 (0x1U << TIM_CCMR2_IC4F_Pos) /*!< 0x00001000 */
+#define TIM_CCMR2_IC4F_1 (0x2U << TIM_CCMR2_IC4F_Pos) /*!< 0x00002000 */
+#define TIM_CCMR2_IC4F_2 (0x4U << TIM_CCMR2_IC4F_Pos) /*!< 0x00004000 */
+#define TIM_CCMR2_IC4F_3 (0x8U << TIM_CCMR2_IC4F_Pos) /*!< 0x00008000 */
+
+/******************* Bit definition for TIM_CCER register ******************/
+#define TIM_CCER_CC1E_Pos (0U)
+#define TIM_CCER_CC1E_Msk (0x1U << TIM_CCER_CC1E_Pos) /*!< 0x00000001 */
+#define TIM_CCER_CC1E TIM_CCER_CC1E_Msk /*!<Capture/Compare 1 output enable */
+#define TIM_CCER_CC1P_Pos (1U)
+#define TIM_CCER_CC1P_Msk (0x1U << TIM_CCER_CC1P_Pos) /*!< 0x00000002 */
+#define TIM_CCER_CC1P TIM_CCER_CC1P_Msk /*!<Capture/Compare 1 output Polarity */
+#define TIM_CCER_CC1NE_Pos (2U)
+#define TIM_CCER_CC1NE_Msk (0x1U << TIM_CCER_CC1NE_Pos) /*!< 0x00000004 */
+#define TIM_CCER_CC1NE TIM_CCER_CC1NE_Msk /*!<Capture/Compare 1 Complementary output enable */
+#define TIM_CCER_CC1NP_Pos (3U)
+#define TIM_CCER_CC1NP_Msk (0x1U << TIM_CCER_CC1NP_Pos) /*!< 0x00000008 */
+#define TIM_CCER_CC1NP TIM_CCER_CC1NP_Msk /*!<Capture/Compare 1 Complementary output Polarity */
+#define TIM_CCER_CC2E_Pos (4U)
+#define TIM_CCER_CC2E_Msk (0x1U << TIM_CCER_CC2E_Pos) /*!< 0x00000010 */
+#define TIM_CCER_CC2E TIM_CCER_CC2E_Msk /*!<Capture/Compare 2 output enable */
+#define TIM_CCER_CC2P_Pos (5U)
+#define TIM_CCER_CC2P_Msk (0x1U << TIM_CCER_CC2P_Pos) /*!< 0x00000020 */
+#define TIM_CCER_CC2P TIM_CCER_CC2P_Msk /*!<Capture/Compare 2 output Polarity */
+#define TIM_CCER_CC2NE_Pos (6U)
+#define TIM_CCER_CC2NE_Msk (0x1U << TIM_CCER_CC2NE_Pos) /*!< 0x00000040 */
+#define TIM_CCER_CC2NE TIM_CCER_CC2NE_Msk /*!<Capture/Compare 2 Complementary output enable */
+#define TIM_CCER_CC2NP_Pos (7U)
+#define TIM_CCER_CC2NP_Msk (0x1U << TIM_CCER_CC2NP_Pos) /*!< 0x00000080 */
+#define TIM_CCER_CC2NP TIM_CCER_CC2NP_Msk /*!<Capture/Compare 2 Complementary output Polarity */
+#define TIM_CCER_CC3E_Pos (8U)
+#define TIM_CCER_CC3E_Msk (0x1U << TIM_CCER_CC3E_Pos) /*!< 0x00000100 */
+#define TIM_CCER_CC3E TIM_CCER_CC3E_Msk /*!<Capture/Compare 3 output enable */
+#define TIM_CCER_CC3P_Pos (9U)
+#define TIM_CCER_CC3P_Msk (0x1U << TIM_CCER_CC3P_Pos) /*!< 0x00000200 */
+#define TIM_CCER_CC3P TIM_CCER_CC3P_Msk /*!<Capture/Compare 3 output Polarity */
+#define TIM_CCER_CC3NE_Pos (10U)
+#define TIM_CCER_CC3NE_Msk (0x1U << TIM_CCER_CC3NE_Pos) /*!< 0x00000400 */
+#define TIM_CCER_CC3NE TIM_CCER_CC3NE_Msk /*!<Capture/Compare 3 Complementary output enable */
+#define TIM_CCER_CC3NP_Pos (11U)
+#define TIM_CCER_CC3NP_Msk (0x1U << TIM_CCER_CC3NP_Pos) /*!< 0x00000800 */
+#define TIM_CCER_CC3NP TIM_CCER_CC3NP_Msk /*!<Capture/Compare 3 Complementary output Polarity */
+#define TIM_CCER_CC4E_Pos (12U)
+#define TIM_CCER_CC4E_Msk (0x1U << TIM_CCER_CC4E_Pos) /*!< 0x00001000 */
+#define TIM_CCER_CC4E TIM_CCER_CC4E_Msk /*!<Capture/Compare 4 output enable */
+#define TIM_CCER_CC4P_Pos (13U)
+#define TIM_CCER_CC4P_Msk (0x1U << TIM_CCER_CC4P_Pos) /*!< 0x00002000 */
+#define TIM_CCER_CC4P TIM_CCER_CC4P_Msk /*!<Capture/Compare 4 output Polarity */
+#define TIM_CCER_CC4NP_Pos (15U)
+#define TIM_CCER_CC4NP_Msk (0x1U << TIM_CCER_CC4NP_Pos) /*!< 0x00008000 */
+#define TIM_CCER_CC4NP TIM_CCER_CC4NP_Msk /*!<Capture/Compare 4 Complementary output Polarity */
+
+/******************* Bit definition for TIM_CNT register *******************/
+#define TIM_CNT_CNT_Pos (0U)
+#define TIM_CNT_CNT_Msk (0xFFFFFFFFU << TIM_CNT_CNT_Pos) /*!< 0xFFFFFFFF */
+#define TIM_CNT_CNT TIM_CNT_CNT_Msk /*!<Counter Value */
+
+/******************* Bit definition for TIM_PSC register *******************/
+#define TIM_PSC_PSC_Pos (0U)
+#define TIM_PSC_PSC_Msk (0xFFFFU << TIM_PSC_PSC_Pos) /*!< 0x0000FFFF */
+#define TIM_PSC_PSC TIM_PSC_PSC_Msk /*!<Prescaler Value */
+
+/******************* Bit definition for TIM_ARR register *******************/
+#define TIM_ARR_ARR_Pos (0U)
+#define TIM_ARR_ARR_Msk (0xFFFFFFFFU << TIM_ARR_ARR_Pos) /*!< 0xFFFFFFFF */
+#define TIM_ARR_ARR TIM_ARR_ARR_Msk /*!<actual auto-reload Value */
+
+/******************* Bit definition for TIM_RCR register *******************/
+#define TIM_RCR_REP_Pos (0U)
+#define TIM_RCR_REP_Msk (0xFFU << TIM_RCR_REP_Pos) /*!< 0x000000FF */
+#define TIM_RCR_REP TIM_RCR_REP_Msk /*!<Repetition Counter Value */
+
+/******************* Bit definition for TIM_CCR1 register ******************/
+#define TIM_CCR1_CCR1_Pos (0U)
+#define TIM_CCR1_CCR1_Msk (0xFFFFU << TIM_CCR1_CCR1_Pos) /*!< 0x0000FFFF */
+#define TIM_CCR1_CCR1 TIM_CCR1_CCR1_Msk /*!<Capture/Compare 1 Value */
+
+/******************* Bit definition for TIM_CCR2 register ******************/
+#define TIM_CCR2_CCR2_Pos (0U)
+#define TIM_CCR2_CCR2_Msk (0xFFFFU << TIM_CCR2_CCR2_Pos) /*!< 0x0000FFFF */
+#define TIM_CCR2_CCR2 TIM_CCR2_CCR2_Msk /*!<Capture/Compare 2 Value */
+
+/******************* Bit definition for TIM_CCR3 register ******************/
+#define TIM_CCR3_CCR3_Pos (0U)
+#define TIM_CCR3_CCR3_Msk (0xFFFFU << TIM_CCR3_CCR3_Pos) /*!< 0x0000FFFF */
+#define TIM_CCR3_CCR3 TIM_CCR3_CCR3_Msk /*!<Capture/Compare 3 Value */
+
+/******************* Bit definition for TIM_CCR4 register ******************/
+#define TIM_CCR4_CCR4_Pos (0U)
+#define TIM_CCR4_CCR4_Msk (0xFFFFU << TIM_CCR4_CCR4_Pos) /*!< 0x0000FFFF */
+#define TIM_CCR4_CCR4 TIM_CCR4_CCR4_Msk /*!<Capture/Compare 4 Value */
+
+/******************* Bit definition for TIM_BDTR register ******************/
+#define TIM_BDTR_DTG_Pos (0U)
+#define TIM_BDTR_DTG_Msk (0xFFU << TIM_BDTR_DTG_Pos) /*!< 0x000000FF */
+#define TIM_BDTR_DTG TIM_BDTR_DTG_Msk /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
+#define TIM_BDTR_DTG_0 (0x01U << TIM_BDTR_DTG_Pos) /*!< 0x00000001 */
+#define TIM_BDTR_DTG_1 (0x02U << TIM_BDTR_DTG_Pos) /*!< 0x00000002 */
+#define TIM_BDTR_DTG_2 (0x04U << TIM_BDTR_DTG_Pos) /*!< 0x00000004 */
+#define TIM_BDTR_DTG_3 (0x08U << TIM_BDTR_DTG_Pos) /*!< 0x00000008 */
+#define TIM_BDTR_DTG_4 (0x10U << TIM_BDTR_DTG_Pos) /*!< 0x00000010 */
+#define TIM_BDTR_DTG_5 (0x20U << TIM_BDTR_DTG_Pos) /*!< 0x00000020 */
+#define TIM_BDTR_DTG_6 (0x40U << TIM_BDTR_DTG_Pos) /*!< 0x00000040 */
+#define TIM_BDTR_DTG_7 (0x80U << TIM_BDTR_DTG_Pos) /*!< 0x00000080 */
+
+#define TIM_BDTR_LOCK_Pos (8U)
+#define TIM_BDTR_LOCK_Msk (0x3U << TIM_BDTR_LOCK_Pos) /*!< 0x00000300 */
+#define TIM_BDTR_LOCK TIM_BDTR_LOCK_Msk /*!<LOCK[1:0] bits (Lock Configuration) */
+#define TIM_BDTR_LOCK_0 (0x1U << TIM_BDTR_LOCK_Pos) /*!< 0x00000100 */
+#define TIM_BDTR_LOCK_1 (0x2U << TIM_BDTR_LOCK_Pos) /*!< 0x00000200 */
+
+#define TIM_BDTR_OSSI_Pos (10U)
+#define TIM_BDTR_OSSI_Msk (0x1U << TIM_BDTR_OSSI_Pos) /*!< 0x00000400 */
+#define TIM_BDTR_OSSI TIM_BDTR_OSSI_Msk /*!<Off-State Selection for Idle mode */
+#define TIM_BDTR_OSSR_Pos (11U)
+#define TIM_BDTR_OSSR_Msk (0x1U << TIM_BDTR_OSSR_Pos) /*!< 0x00000800 */
+#define TIM_BDTR_OSSR TIM_BDTR_OSSR_Msk /*!<Off-State Selection for Run mode */
+#define TIM_BDTR_BKE_Pos (12U)
+#define TIM_BDTR_BKE_Msk (0x1U << TIM_BDTR_BKE_Pos) /*!< 0x00001000 */
+#define TIM_BDTR_BKE TIM_BDTR_BKE_Msk /*!<Break enable */
+#define TIM_BDTR_BKP_Pos (13U)
+#define TIM_BDTR_BKP_Msk (0x1U << TIM_BDTR_BKP_Pos) /*!< 0x00002000 */
+#define TIM_BDTR_BKP TIM_BDTR_BKP_Msk /*!<Break Polarity */
+#define TIM_BDTR_AOE_Pos (14U)
+#define TIM_BDTR_AOE_Msk (0x1U << TIM_BDTR_AOE_Pos) /*!< 0x00004000 */
+#define TIM_BDTR_AOE TIM_BDTR_AOE_Msk /*!<Automatic Output enable */
+#define TIM_BDTR_MOE_Pos (15U)
+#define TIM_BDTR_MOE_Msk (0x1U << TIM_BDTR_MOE_Pos) /*!< 0x00008000 */
+#define TIM_BDTR_MOE TIM_BDTR_MOE_Msk /*!<Main Output enable */
+
+/******************* Bit definition for TIM_DCR register *******************/
+#define TIM_DCR_DBA_Pos (0U)
+#define TIM_DCR_DBA_Msk (0x1FU << TIM_DCR_DBA_Pos) /*!< 0x0000001F */
+#define TIM_DCR_DBA TIM_DCR_DBA_Msk /*!<DBA[4:0] bits (DMA Base Address) */
+#define TIM_DCR_DBA_0 (0x01U << TIM_DCR_DBA_Pos) /*!< 0x00000001 */
+#define TIM_DCR_DBA_1 (0x02U << TIM_DCR_DBA_Pos) /*!< 0x00000002 */
+#define TIM_DCR_DBA_2 (0x04U << TIM_DCR_DBA_Pos) /*!< 0x00000004 */
+#define TIM_DCR_DBA_3 (0x08U << TIM_DCR_DBA_Pos) /*!< 0x00000008 */
+#define TIM_DCR_DBA_4 (0x10U << TIM_DCR_DBA_Pos) /*!< 0x00000010 */
+
+#define TIM_DCR_DBL_Pos (8U)
+#define TIM_DCR_DBL_Msk (0x1FU << TIM_DCR_DBL_Pos) /*!< 0x00001F00 */
+#define TIM_DCR_DBL TIM_DCR_DBL_Msk /*!<DBL[4:0] bits (DMA Burst Length) */
+#define TIM_DCR_DBL_0 (0x01U << TIM_DCR_DBL_Pos) /*!< 0x00000100 */
+#define TIM_DCR_DBL_1 (0x02U << TIM_DCR_DBL_Pos) /*!< 0x00000200 */
+#define TIM_DCR_DBL_2 (0x04U << TIM_DCR_DBL_Pos) /*!< 0x00000400 */
+#define TIM_DCR_DBL_3 (0x08U << TIM_DCR_DBL_Pos) /*!< 0x00000800 */
+#define TIM_DCR_DBL_4 (0x10U << TIM_DCR_DBL_Pos) /*!< 0x00001000 */
+
+/******************* Bit definition for TIM_DMAR register ******************/
+#define TIM_DMAR_DMAB_Pos (0U)
+#define TIM_DMAR_DMAB_Msk (0xFFFFU << TIM_DMAR_DMAB_Pos) /*!< 0x0000FFFF */
+#define TIM_DMAR_DMAB TIM_DMAR_DMAB_Msk /*!<DMA register for burst accesses */
+
+/******************* Bit definition for TIM_OR register ********************/
+
+/******************************************************************************/
+/* */
+/* Real-Time Clock */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for RTC_CRH register ********************/
+#define RTC_CRH_SECIE_Pos (0U)
+#define RTC_CRH_SECIE_Msk (0x1U << RTC_CRH_SECIE_Pos) /*!< 0x00000001 */
+#define RTC_CRH_SECIE RTC_CRH_SECIE_Msk /*!< Second Interrupt Enable */
+#define RTC_CRH_ALRIE_Pos (1U)
+#define RTC_CRH_ALRIE_Msk (0x1U << RTC_CRH_ALRIE_Pos) /*!< 0x00000002 */
+#define RTC_CRH_ALRIE RTC_CRH_ALRIE_Msk /*!< Alarm Interrupt Enable */
+#define RTC_CRH_OWIE_Pos (2U)
+#define RTC_CRH_OWIE_Msk (0x1U << RTC_CRH_OWIE_Pos) /*!< 0x00000004 */
+#define RTC_CRH_OWIE RTC_CRH_OWIE_Msk /*!< OverfloW Interrupt Enable */
+
+/******************* Bit definition for RTC_CRL register ********************/
+#define RTC_CRL_SECF_Pos (0U)
+#define RTC_CRL_SECF_Msk (0x1U << RTC_CRL_SECF_Pos) /*!< 0x00000001 */
+#define RTC_CRL_SECF RTC_CRL_SECF_Msk /*!< Second Flag */
+#define RTC_CRL_ALRF_Pos (1U)
+#define RTC_CRL_ALRF_Msk (0x1U << RTC_CRL_ALRF_Pos) /*!< 0x00000002 */
+#define RTC_CRL_ALRF RTC_CRL_ALRF_Msk /*!< Alarm Flag */
+#define RTC_CRL_OWF_Pos (2U)
+#define RTC_CRL_OWF_Msk (0x1U << RTC_CRL_OWF_Pos) /*!< 0x00000004 */
+#define RTC_CRL_OWF RTC_CRL_OWF_Msk /*!< OverfloW Flag */
+#define RTC_CRL_RSF_Pos (3U)
+#define RTC_CRL_RSF_Msk (0x1U << RTC_CRL_RSF_Pos) /*!< 0x00000008 */
+#define RTC_CRL_RSF RTC_CRL_RSF_Msk /*!< Registers Synchronized Flag */
+#define RTC_CRL_CNF_Pos (4U)
+#define RTC_CRL_CNF_Msk (0x1U << RTC_CRL_CNF_Pos) /*!< 0x00000010 */
+#define RTC_CRL_CNF RTC_CRL_CNF_Msk /*!< Configuration Flag */
+#define RTC_CRL_RTOFF_Pos (5U)
+#define RTC_CRL_RTOFF_Msk (0x1U << RTC_CRL_RTOFF_Pos) /*!< 0x00000020 */
+#define RTC_CRL_RTOFF RTC_CRL_RTOFF_Msk /*!< RTC operation OFF */
+
+/******************* Bit definition for RTC_PRLH register *******************/
+#define RTC_PRLH_PRL_Pos (0U)
+#define RTC_PRLH_PRL_Msk (0xFU << RTC_PRLH_PRL_Pos) /*!< 0x0000000F */
+#define RTC_PRLH_PRL RTC_PRLH_PRL_Msk /*!< RTC Prescaler Reload Value High */
+
+/******************* Bit definition for RTC_PRLL register *******************/
+#define RTC_PRLL_PRL_Pos (0U)
+#define RTC_PRLL_PRL_Msk (0xFFFFU << RTC_PRLL_PRL_Pos) /*!< 0x0000FFFF */
+#define RTC_PRLL_PRL RTC_PRLL_PRL_Msk /*!< RTC Prescaler Reload Value Low */
+
+/******************* Bit definition for RTC_DIVH register *******************/
+#define RTC_DIVH_RTC_DIV_Pos (0U)
+#define RTC_DIVH_RTC_DIV_Msk (0xFU << RTC_DIVH_RTC_DIV_Pos) /*!< 0x0000000F */
+#define RTC_DIVH_RTC_DIV RTC_DIVH_RTC_DIV_Msk /*!< RTC Clock Divider High */
+
+/******************* Bit definition for RTC_DIVL register *******************/
+#define RTC_DIVL_RTC_DIV_Pos (0U)
+#define RTC_DIVL_RTC_DIV_Msk (0xFFFFU << RTC_DIVL_RTC_DIV_Pos) /*!< 0x0000FFFF */
+#define RTC_DIVL_RTC_DIV RTC_DIVL_RTC_DIV_Msk /*!< RTC Clock Divider Low */
+
+/******************* Bit definition for RTC_CNTH register *******************/
+#define RTC_CNTH_RTC_CNT_Pos (0U)
+#define RTC_CNTH_RTC_CNT_Msk (0xFFFFU << RTC_CNTH_RTC_CNT_Pos) /*!< 0x0000FFFF */
+#define RTC_CNTH_RTC_CNT RTC_CNTH_RTC_CNT_Msk /*!< RTC Counter High */
+
+/******************* Bit definition for RTC_CNTL register *******************/
+#define RTC_CNTL_RTC_CNT_Pos (0U)
+#define RTC_CNTL_RTC_CNT_Msk (0xFFFFU << RTC_CNTL_RTC_CNT_Pos) /*!< 0x0000FFFF */
+#define RTC_CNTL_RTC_CNT RTC_CNTL_RTC_CNT_Msk /*!< RTC Counter Low */
+
+/******************* Bit definition for RTC_ALRH register *******************/
+#define RTC_ALRH_RTC_ALR_Pos (0U)
+#define RTC_ALRH_RTC_ALR_Msk (0xFFFFU << RTC_ALRH_RTC_ALR_Pos) /*!< 0x0000FFFF */
+#define RTC_ALRH_RTC_ALR RTC_ALRH_RTC_ALR_Msk /*!< RTC Alarm High */
+
+/******************* Bit definition for RTC_ALRL register *******************/
+#define RTC_ALRL_RTC_ALR_Pos (0U)
+#define RTC_ALRL_RTC_ALR_Msk (0xFFFFU << RTC_ALRL_RTC_ALR_Pos) /*!< 0x0000FFFF */
+#define RTC_ALRL_RTC_ALR RTC_ALRL_RTC_ALR_Msk /*!< RTC Alarm Low */
+
+/******************************************************************************/
+/* */
+/* Independent WATCHDOG (IWDG) */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for IWDG_KR register ********************/
+#define IWDG_KR_KEY_Pos (0U)
+#define IWDG_KR_KEY_Msk (0xFFFFU << IWDG_KR_KEY_Pos) /*!< 0x0000FFFF */
+#define IWDG_KR_KEY IWDG_KR_KEY_Msk /*!< Key value (write only, read 0000h) */
+
+/******************* Bit definition for IWDG_PR register ********************/
+#define IWDG_PR_PR_Pos (0U)
+#define IWDG_PR_PR_Msk (0x7U << IWDG_PR_PR_Pos) /*!< 0x00000007 */
+#define IWDG_PR_PR IWDG_PR_PR_Msk /*!< PR[2:0] (Prescaler divider) */
+#define IWDG_PR_PR_0 (0x1U << IWDG_PR_PR_Pos) /*!< 0x00000001 */
+#define IWDG_PR_PR_1 (0x2U << IWDG_PR_PR_Pos) /*!< 0x00000002 */
+#define IWDG_PR_PR_2 (0x4U << IWDG_PR_PR_Pos) /*!< 0x00000004 */
+
+/******************* Bit definition for IWDG_RLR register *******************/
+#define IWDG_RLR_RL_Pos (0U)
+#define IWDG_RLR_RL_Msk (0xFFFU << IWDG_RLR_RL_Pos) /*!< 0x00000FFF */
+#define IWDG_RLR_RL IWDG_RLR_RL_Msk /*!< Watchdog counter reload value */
+
+/******************* Bit definition for IWDG_SR register ********************/
+#define IWDG_SR_PVU_Pos (0U)
+#define IWDG_SR_PVU_Msk (0x1U << IWDG_SR_PVU_Pos) /*!< 0x00000001 */
+#define IWDG_SR_PVU IWDG_SR_PVU_Msk /*!< Watchdog prescaler value update */
+#define IWDG_SR_RVU_Pos (1U)
+#define IWDG_SR_RVU_Msk (0x1U << IWDG_SR_RVU_Pos) /*!< 0x00000002 */
+#define IWDG_SR_RVU IWDG_SR_RVU_Msk /*!< Watchdog counter reload value update */
+
+/******************************************************************************/
+/* */
+/* Window WATCHDOG (WWDG) */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for WWDG_CR register ********************/
+#define WWDG_CR_T_Pos (0U)
+#define WWDG_CR_T_Msk (0x7FU << WWDG_CR_T_Pos) /*!< 0x0000007F */
+#define WWDG_CR_T WWDG_CR_T_Msk /*!< T[6:0] bits (7-Bit counter (MSB to LSB)) */
+#define WWDG_CR_T_0 (0x01U << WWDG_CR_T_Pos) /*!< 0x00000001 */
+#define WWDG_CR_T_1 (0x02U << WWDG_CR_T_Pos) /*!< 0x00000002 */
+#define WWDG_CR_T_2 (0x04U << WWDG_CR_T_Pos) /*!< 0x00000004 */
+#define WWDG_CR_T_3 (0x08U << WWDG_CR_T_Pos) /*!< 0x00000008 */
+#define WWDG_CR_T_4 (0x10U << WWDG_CR_T_Pos) /*!< 0x00000010 */
+#define WWDG_CR_T_5 (0x20U << WWDG_CR_T_Pos) /*!< 0x00000020 */
+#define WWDG_CR_T_6 (0x40U << WWDG_CR_T_Pos) /*!< 0x00000040 */
+
+/* Legacy defines */
+#define WWDG_CR_T0 WWDG_CR_T_0
+#define WWDG_CR_T1 WWDG_CR_T_1
+#define WWDG_CR_T2 WWDG_CR_T_2
+#define WWDG_CR_T3 WWDG_CR_T_3
+#define WWDG_CR_T4 WWDG_CR_T_4
+#define WWDG_CR_T5 WWDG_CR_T_5
+#define WWDG_CR_T6 WWDG_CR_T_6
+
+#define WWDG_CR_WDGA_Pos (7U)
+#define WWDG_CR_WDGA_Msk (0x1U << WWDG_CR_WDGA_Pos) /*!< 0x00000080 */
+#define WWDG_CR_WDGA WWDG_CR_WDGA_Msk /*!< Activation bit */
+
+/******************* Bit definition for WWDG_CFR register *******************/
+#define WWDG_CFR_W_Pos (0U)
+#define WWDG_CFR_W_Msk (0x7FU << WWDG_CFR_W_Pos) /*!< 0x0000007F */
+#define WWDG_CFR_W WWDG_CFR_W_Msk /*!< W[6:0] bits (7-bit window value) */
+#define WWDG_CFR_W_0 (0x01U << WWDG_CFR_W_Pos) /*!< 0x00000001 */
+#define WWDG_CFR_W_1 (0x02U << WWDG_CFR_W_Pos) /*!< 0x00000002 */
+#define WWDG_CFR_W_2 (0x04U << WWDG_CFR_W_Pos) /*!< 0x00000004 */
+#define WWDG_CFR_W_3 (0x08U << WWDG_CFR_W_Pos) /*!< 0x00000008 */
+#define WWDG_CFR_W_4 (0x10U << WWDG_CFR_W_Pos) /*!< 0x00000010 */
+#define WWDG_CFR_W_5 (0x20U << WWDG_CFR_W_Pos) /*!< 0x00000020 */
+#define WWDG_CFR_W_6 (0x40U << WWDG_CFR_W_Pos) /*!< 0x00000040 */
+
+/* Legacy defines */
+#define WWDG_CFR_W0 WWDG_CFR_W_0
+#define WWDG_CFR_W1 WWDG_CFR_W_1
+#define WWDG_CFR_W2 WWDG_CFR_W_2
+#define WWDG_CFR_W3 WWDG_CFR_W_3
+#define WWDG_CFR_W4 WWDG_CFR_W_4
+#define WWDG_CFR_W5 WWDG_CFR_W_5
+#define WWDG_CFR_W6 WWDG_CFR_W_6
+
+#define WWDG_CFR_WDGTB_Pos (7U)
+#define WWDG_CFR_WDGTB_Msk (0x3U << WWDG_CFR_WDGTB_Pos) /*!< 0x00000180 */
+#define WWDG_CFR_WDGTB WWDG_CFR_WDGTB_Msk /*!< WDGTB[1:0] bits (Timer Base) */
+#define WWDG_CFR_WDGTB_0 (0x1U << WWDG_CFR_WDGTB_Pos) /*!< 0x00000080 */
+#define WWDG_CFR_WDGTB_1 (0x2U << WWDG_CFR_WDGTB_Pos) /*!< 0x00000100 */
+
+/* Legacy defines */
+#define WWDG_CFR_WDGTB0 WWDG_CFR_WDGTB_0
+#define WWDG_CFR_WDGTB1 WWDG_CFR_WDGTB_1
+
+#define WWDG_CFR_EWI_Pos (9U)
+#define WWDG_CFR_EWI_Msk (0x1U << WWDG_CFR_EWI_Pos) /*!< 0x00000200 */
+#define WWDG_CFR_EWI WWDG_CFR_EWI_Msk /*!< Early Wakeup Interrupt */
+
+/******************* Bit definition for WWDG_SR register ********************/
+#define WWDG_SR_EWIF_Pos (0U)
+#define WWDG_SR_EWIF_Msk (0x1U << WWDG_SR_EWIF_Pos) /*!< 0x00000001 */
+#define WWDG_SR_EWIF WWDG_SR_EWIF_Msk /*!< Early Wakeup Interrupt Flag */
+
+
+/******************************************************************************/
+/* */
+/* SD host Interface */
+/* */
+/******************************************************************************/
+
+/****************** Bit definition for SDIO_POWER register ******************/
+#define SDIO_POWER_PWRCTRL_Pos (0U)
+#define SDIO_POWER_PWRCTRL_Msk (0x3U << SDIO_POWER_PWRCTRL_Pos) /*!< 0x00000003 */
+#define SDIO_POWER_PWRCTRL SDIO_POWER_PWRCTRL_Msk /*!< PWRCTRL[1:0] bits (Power supply control bits) */
+#define SDIO_POWER_PWRCTRL_0 (0x1U << SDIO_POWER_PWRCTRL_Pos) /*!< 0x01 */
+#define SDIO_POWER_PWRCTRL_1 (0x2U << SDIO_POWER_PWRCTRL_Pos) /*!< 0x02 */
+
+/****************** Bit definition for SDIO_CLKCR register ******************/
+#define SDIO_CLKCR_CLKDIV_Pos (0U)
+#define SDIO_CLKCR_CLKDIV_Msk (0xFFU << SDIO_CLKCR_CLKDIV_Pos) /*!< 0x000000FF */
+#define SDIO_CLKCR_CLKDIV SDIO_CLKCR_CLKDIV_Msk /*!< Clock divide factor */
+#define SDIO_CLKCR_CLKEN_Pos (8U)
+#define SDIO_CLKCR_CLKEN_Msk (0x1U << SDIO_CLKCR_CLKEN_Pos) /*!< 0x00000100 */
+#define SDIO_CLKCR_CLKEN SDIO_CLKCR_CLKEN_Msk /*!< Clock enable bit */
+#define SDIO_CLKCR_PWRSAV_Pos (9U)
+#define SDIO_CLKCR_PWRSAV_Msk (0x1U << SDIO_CLKCR_PWRSAV_Pos) /*!< 0x00000200 */
+#define SDIO_CLKCR_PWRSAV SDIO_CLKCR_PWRSAV_Msk /*!< Power saving configuration bit */
+#define SDIO_CLKCR_BYPASS_Pos (10U)
+#define SDIO_CLKCR_BYPASS_Msk (0x1U << SDIO_CLKCR_BYPASS_Pos) /*!< 0x00000400 */
+#define SDIO_CLKCR_BYPASS SDIO_CLKCR_BYPASS_Msk /*!< Clock divider bypass enable bit */
+
+#define SDIO_CLKCR_WIDBUS_Pos (11U)
+#define SDIO_CLKCR_WIDBUS_Msk (0x3U << SDIO_CLKCR_WIDBUS_Pos) /*!< 0x00001800 */
+#define SDIO_CLKCR_WIDBUS SDIO_CLKCR_WIDBUS_Msk /*!< WIDBUS[1:0] bits (Wide bus mode enable bit) */
+#define SDIO_CLKCR_WIDBUS_0 (0x1U << SDIO_CLKCR_WIDBUS_Pos) /*!< 0x0800 */
+#define SDIO_CLKCR_WIDBUS_1 (0x2U << SDIO_CLKCR_WIDBUS_Pos) /*!< 0x1000 */
+
+#define SDIO_CLKCR_NEGEDGE_Pos (13U)
+#define SDIO_CLKCR_NEGEDGE_Msk (0x1U << SDIO_CLKCR_NEGEDGE_Pos) /*!< 0x00002000 */
+#define SDIO_CLKCR_NEGEDGE SDIO_CLKCR_NEGEDGE_Msk /*!< SDIO_CK dephasing selection bit */
+#define SDIO_CLKCR_HWFC_EN_Pos (14U)
+#define SDIO_CLKCR_HWFC_EN_Msk (0x1U << SDIO_CLKCR_HWFC_EN_Pos) /*!< 0x00004000 */
+#define SDIO_CLKCR_HWFC_EN SDIO_CLKCR_HWFC_EN_Msk /*!< HW Flow Control enable */
+
+/******************* Bit definition for SDIO_ARG register *******************/
+#define SDIO_ARG_CMDARG_Pos (0U)
+#define SDIO_ARG_CMDARG_Msk (0xFFFFFFFFU << SDIO_ARG_CMDARG_Pos) /*!< 0xFFFFFFFF */
+#define SDIO_ARG_CMDARG SDIO_ARG_CMDARG_Msk /*!< Command argument */
+
+/******************* Bit definition for SDIO_CMD register *******************/
+#define SDIO_CMD_CMDINDEX_Pos (0U)
+#define SDIO_CMD_CMDINDEX_Msk (0x3FU << SDIO_CMD_CMDINDEX_Pos) /*!< 0x0000003F */
+#define SDIO_CMD_CMDINDEX SDIO_CMD_CMDINDEX_Msk /*!< Command Index */
+
+#define SDIO_CMD_WAITRESP_Pos (6U)
+#define SDIO_CMD_WAITRESP_Msk (0x3U << SDIO_CMD_WAITRESP_Pos) /*!< 0x000000C0 */
+#define SDIO_CMD_WAITRESP SDIO_CMD_WAITRESP_Msk /*!< WAITRESP[1:0] bits (Wait for response bits) */
+#define SDIO_CMD_WAITRESP_0 (0x1U << SDIO_CMD_WAITRESP_Pos) /*!< 0x0040 */
+#define SDIO_CMD_WAITRESP_1 (0x2U << SDIO_CMD_WAITRESP_Pos) /*!< 0x0080 */
+
+#define SDIO_CMD_WAITINT_Pos (8U)
+#define SDIO_CMD_WAITINT_Msk (0x1U << SDIO_CMD_WAITINT_Pos) /*!< 0x00000100 */
+#define SDIO_CMD_WAITINT SDIO_CMD_WAITINT_Msk /*!< CPSM Waits for Interrupt Request */
+#define SDIO_CMD_WAITPEND_Pos (9U)
+#define SDIO_CMD_WAITPEND_Msk (0x1U << SDIO_CMD_WAITPEND_Pos) /*!< 0x00000200 */
+#define SDIO_CMD_WAITPEND SDIO_CMD_WAITPEND_Msk /*!< CPSM Waits for ends of data transfer (CmdPend internal signal) */
+#define SDIO_CMD_CPSMEN_Pos (10U)
+#define SDIO_CMD_CPSMEN_Msk (0x1U << SDIO_CMD_CPSMEN_Pos) /*!< 0x00000400 */
+#define SDIO_CMD_CPSMEN SDIO_CMD_CPSMEN_Msk /*!< Command path state machine (CPSM) Enable bit */
+#define SDIO_CMD_SDIOSUSPEND_Pos (11U)
+#define SDIO_CMD_SDIOSUSPEND_Msk (0x1U << SDIO_CMD_SDIOSUSPEND_Pos) /*!< 0x00000800 */
+#define SDIO_CMD_SDIOSUSPEND SDIO_CMD_SDIOSUSPEND_Msk /*!< SD I/O suspend command */
+#define SDIO_CMD_ENCMDCOMPL_Pos (12U)
+#define SDIO_CMD_ENCMDCOMPL_Msk (0x1U << SDIO_CMD_ENCMDCOMPL_Pos) /*!< 0x00001000 */
+#define SDIO_CMD_ENCMDCOMPL SDIO_CMD_ENCMDCOMPL_Msk /*!< Enable CMD completion */
+#define SDIO_CMD_NIEN_Pos (13U)
+#define SDIO_CMD_NIEN_Msk (0x1U << SDIO_CMD_NIEN_Pos) /*!< 0x00002000 */
+#define SDIO_CMD_NIEN SDIO_CMD_NIEN_Msk /*!< Not Interrupt Enable */
+#define SDIO_CMD_CEATACMD_Pos (14U)
+#define SDIO_CMD_CEATACMD_Msk (0x1U << SDIO_CMD_CEATACMD_Pos) /*!< 0x00004000 */
+#define SDIO_CMD_CEATACMD SDIO_CMD_CEATACMD_Msk /*!< CE-ATA command */
+
+/***************** Bit definition for SDIO_RESPCMD register *****************/
+#define SDIO_RESPCMD_RESPCMD_Pos (0U)
+#define SDIO_RESPCMD_RESPCMD_Msk (0x3FU << SDIO_RESPCMD_RESPCMD_Pos) /*!< 0x0000003F */
+#define SDIO_RESPCMD_RESPCMD SDIO_RESPCMD_RESPCMD_Msk /*!< Response command index */
+
+/****************** Bit definition for SDIO_RESP0 register ******************/
+#define SDIO_RESP0_CARDSTATUS0_Pos (0U)
+#define SDIO_RESP0_CARDSTATUS0_Msk (0xFFFFFFFFU << SDIO_RESP0_CARDSTATUS0_Pos) /*!< 0xFFFFFFFF */
+#define SDIO_RESP0_CARDSTATUS0 SDIO_RESP0_CARDSTATUS0_Msk /*!< Card Status */
+
+/****************** Bit definition for SDIO_RESP1 register ******************/
+#define SDIO_RESP1_CARDSTATUS1_Pos (0U)
+#define SDIO_RESP1_CARDSTATUS1_Msk (0xFFFFFFFFU << SDIO_RESP1_CARDSTATUS1_Pos) /*!< 0xFFFFFFFF */
+#define SDIO_RESP1_CARDSTATUS1 SDIO_RESP1_CARDSTATUS1_Msk /*!< Card Status */
+
+/****************** Bit definition for SDIO_RESP2 register ******************/
+#define SDIO_RESP2_CARDSTATUS2_Pos (0U)
+#define SDIO_RESP2_CARDSTATUS2_Msk (0xFFFFFFFFU << SDIO_RESP2_CARDSTATUS2_Pos) /*!< 0xFFFFFFFF */
+#define SDIO_RESP2_CARDSTATUS2 SDIO_RESP2_CARDSTATUS2_Msk /*!< Card Status */
+
+/****************** Bit definition for SDIO_RESP3 register ******************/
+#define SDIO_RESP3_CARDSTATUS3_Pos (0U)
+#define SDIO_RESP3_CARDSTATUS3_Msk (0xFFFFFFFFU << SDIO_RESP3_CARDSTATUS3_Pos) /*!< 0xFFFFFFFF */
+#define SDIO_RESP3_CARDSTATUS3 SDIO_RESP3_CARDSTATUS3_Msk /*!< Card Status */
+
+/****************** Bit definition for SDIO_RESP4 register ******************/
+#define SDIO_RESP4_CARDSTATUS4_Pos (0U)
+#define SDIO_RESP4_CARDSTATUS4_Msk (0xFFFFFFFFU << SDIO_RESP4_CARDSTATUS4_Pos) /*!< 0xFFFFFFFF */
+#define SDIO_RESP4_CARDSTATUS4 SDIO_RESP4_CARDSTATUS4_Msk /*!< Card Status */
+
+/****************** Bit definition for SDIO_DTIMER register *****************/
+#define SDIO_DTIMER_DATATIME_Pos (0U)
+#define SDIO_DTIMER_DATATIME_Msk (0xFFFFFFFFU << SDIO_DTIMER_DATATIME_Pos) /*!< 0xFFFFFFFF */
+#define SDIO_DTIMER_DATATIME SDIO_DTIMER_DATATIME_Msk /*!< Data timeout period. */
+
+/****************** Bit definition for SDIO_DLEN register *******************/
+#define SDIO_DLEN_DATALENGTH_Pos (0U)
+#define SDIO_DLEN_DATALENGTH_Msk (0x1FFFFFFU << SDIO_DLEN_DATALENGTH_Pos) /*!< 0x01FFFFFF */
+#define SDIO_DLEN_DATALENGTH SDIO_DLEN_DATALENGTH_Msk /*!< Data length value */
+
+/****************** Bit definition for SDIO_DCTRL register ******************/
+#define SDIO_DCTRL_DTEN_Pos (0U)
+#define SDIO_DCTRL_DTEN_Msk (0x1U << SDIO_DCTRL_DTEN_Pos) /*!< 0x00000001 */
+#define SDIO_DCTRL_DTEN SDIO_DCTRL_DTEN_Msk /*!< Data transfer enabled bit */
+#define SDIO_DCTRL_DTDIR_Pos (1U)
+#define SDIO_DCTRL_DTDIR_Msk (0x1U << SDIO_DCTRL_DTDIR_Pos) /*!< 0x00000002 */
+#define SDIO_DCTRL_DTDIR SDIO_DCTRL_DTDIR_Msk /*!< Data transfer direction selection */
+#define SDIO_DCTRL_DTMODE_Pos (2U)
+#define SDIO_DCTRL_DTMODE_Msk (0x1U << SDIO_DCTRL_DTMODE_Pos) /*!< 0x00000004 */
+#define SDIO_DCTRL_DTMODE SDIO_DCTRL_DTMODE_Msk /*!< Data transfer mode selection */
+#define SDIO_DCTRL_DMAEN_Pos (3U)
+#define SDIO_DCTRL_DMAEN_Msk (0x1U << SDIO_DCTRL_DMAEN_Pos) /*!< 0x00000008 */
+#define SDIO_DCTRL_DMAEN SDIO_DCTRL_DMAEN_Msk /*!< DMA enabled bit */
+
+#define SDIO_DCTRL_DBLOCKSIZE_Pos (4U)
+#define SDIO_DCTRL_DBLOCKSIZE_Msk (0xFU << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x000000F0 */
+#define SDIO_DCTRL_DBLOCKSIZE SDIO_DCTRL_DBLOCKSIZE_Msk /*!< DBLOCKSIZE[3:0] bits (Data block size) */
+#define SDIO_DCTRL_DBLOCKSIZE_0 (0x1U << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0010 */
+#define SDIO_DCTRL_DBLOCKSIZE_1 (0x2U << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0020 */
+#define SDIO_DCTRL_DBLOCKSIZE_2 (0x4U << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0040 */
+#define SDIO_DCTRL_DBLOCKSIZE_3 (0x8U << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0080 */
+
+#define SDIO_DCTRL_RWSTART_Pos (8U)
+#define SDIO_DCTRL_RWSTART_Msk (0x1U << SDIO_DCTRL_RWSTART_Pos) /*!< 0x00000100 */
+#define SDIO_DCTRL_RWSTART SDIO_DCTRL_RWSTART_Msk /*!< Read wait start */
+#define SDIO_DCTRL_RWSTOP_Pos (9U)
+#define SDIO_DCTRL_RWSTOP_Msk (0x1U << SDIO_DCTRL_RWSTOP_Pos) /*!< 0x00000200 */
+#define SDIO_DCTRL_RWSTOP SDIO_DCTRL_RWSTOP_Msk /*!< Read wait stop */
+#define SDIO_DCTRL_RWMOD_Pos (10U)
+#define SDIO_DCTRL_RWMOD_Msk (0x1U << SDIO_DCTRL_RWMOD_Pos) /*!< 0x00000400 */
+#define SDIO_DCTRL_RWMOD SDIO_DCTRL_RWMOD_Msk /*!< Read wait mode */
+#define SDIO_DCTRL_SDIOEN_Pos (11U)
+#define SDIO_DCTRL_SDIOEN_Msk (0x1U << SDIO_DCTRL_SDIOEN_Pos) /*!< 0x00000800 */
+#define SDIO_DCTRL_SDIOEN SDIO_DCTRL_SDIOEN_Msk /*!< SD I/O enable functions */
+
+/****************** Bit definition for SDIO_DCOUNT register *****************/
+#define SDIO_DCOUNT_DATACOUNT_Pos (0U)
+#define SDIO_DCOUNT_DATACOUNT_Msk (0x1FFFFFFU << SDIO_DCOUNT_DATACOUNT_Pos) /*!< 0x01FFFFFF */
+#define SDIO_DCOUNT_DATACOUNT SDIO_DCOUNT_DATACOUNT_Msk /*!< Data count value */
+
+/****************** Bit definition for SDIO_STA register ********************/
+#define SDIO_STA_CCRCFAIL_Pos (0U)
+#define SDIO_STA_CCRCFAIL_Msk (0x1U << SDIO_STA_CCRCFAIL_Pos) /*!< 0x00000001 */
+#define SDIO_STA_CCRCFAIL SDIO_STA_CCRCFAIL_Msk /*!< Command response received (CRC check failed) */
+#define SDIO_STA_DCRCFAIL_Pos (1U)
+#define SDIO_STA_DCRCFAIL_Msk (0x1U << SDIO_STA_DCRCFAIL_Pos) /*!< 0x00000002 */
+#define SDIO_STA_DCRCFAIL SDIO_STA_DCRCFAIL_Msk /*!< Data block sent/received (CRC check failed) */
+#define SDIO_STA_CTIMEOUT_Pos (2U)
+#define SDIO_STA_CTIMEOUT_Msk (0x1U << SDIO_STA_CTIMEOUT_Pos) /*!< 0x00000004 */
+#define SDIO_STA_CTIMEOUT SDIO_STA_CTIMEOUT_Msk /*!< Command response timeout */
+#define SDIO_STA_DTIMEOUT_Pos (3U)
+#define SDIO_STA_DTIMEOUT_Msk (0x1U << SDIO_STA_DTIMEOUT_Pos) /*!< 0x00000008 */
+#define SDIO_STA_DTIMEOUT SDIO_STA_DTIMEOUT_Msk /*!< Data timeout */
+#define SDIO_STA_TXUNDERR_Pos (4U)
+#define SDIO_STA_TXUNDERR_Msk (0x1U << SDIO_STA_TXUNDERR_Pos) /*!< 0x00000010 */
+#define SDIO_STA_TXUNDERR SDIO_STA_TXUNDERR_Msk /*!< Transmit FIFO underrun error */
+#define SDIO_STA_RXOVERR_Pos (5U)
+#define SDIO_STA_RXOVERR_Msk (0x1U << SDIO_STA_RXOVERR_Pos) /*!< 0x00000020 */
+#define SDIO_STA_RXOVERR SDIO_STA_RXOVERR_Msk /*!< Received FIFO overrun error */
+#define SDIO_STA_CMDREND_Pos (6U)
+#define SDIO_STA_CMDREND_Msk (0x1U << SDIO_STA_CMDREND_Pos) /*!< 0x00000040 */
+#define SDIO_STA_CMDREND SDIO_STA_CMDREND_Msk /*!< Command response received (CRC check passed) */
+#define SDIO_STA_CMDSENT_Pos (7U)
+#define SDIO_STA_CMDSENT_Msk (0x1U << SDIO_STA_CMDSENT_Pos) /*!< 0x00000080 */
+#define SDIO_STA_CMDSENT SDIO_STA_CMDSENT_Msk /*!< Command sent (no response required) */
+#define SDIO_STA_DATAEND_Pos (8U)
+#define SDIO_STA_DATAEND_Msk (0x1U << SDIO_STA_DATAEND_Pos) /*!< 0x00000100 */
+#define SDIO_STA_DATAEND SDIO_STA_DATAEND_Msk /*!< Data end (data counter, SDIDCOUNT, is zero) */
+#define SDIO_STA_STBITERR_Pos (9U)
+#define SDIO_STA_STBITERR_Msk (0x1U << SDIO_STA_STBITERR_Pos) /*!< 0x00000200 */
+#define SDIO_STA_STBITERR SDIO_STA_STBITERR_Msk /*!< Start bit not detected on all data signals in wide bus mode */
+#define SDIO_STA_DBCKEND_Pos (10U)
+#define SDIO_STA_DBCKEND_Msk (0x1U << SDIO_STA_DBCKEND_Pos) /*!< 0x00000400 */
+#define SDIO_STA_DBCKEND SDIO_STA_DBCKEND_Msk /*!< Data block sent/received (CRC check passed) */
+#define SDIO_STA_CMDACT_Pos (11U)
+#define SDIO_STA_CMDACT_Msk (0x1U << SDIO_STA_CMDACT_Pos) /*!< 0x00000800 */
+#define SDIO_STA_CMDACT SDIO_STA_CMDACT_Msk /*!< Command transfer in progress */
+#define SDIO_STA_TXACT_Pos (12U)
+#define SDIO_STA_TXACT_Msk (0x1U << SDIO_STA_TXACT_Pos) /*!< 0x00001000 */
+#define SDIO_STA_TXACT SDIO_STA_TXACT_Msk /*!< Data transmit in progress */
+#define SDIO_STA_RXACT_Pos (13U)
+#define SDIO_STA_RXACT_Msk (0x1U << SDIO_STA_RXACT_Pos) /*!< 0x00002000 */
+#define SDIO_STA_RXACT SDIO_STA_RXACT_Msk /*!< Data receive in progress */
+#define SDIO_STA_TXFIFOHE_Pos (14U)
+#define SDIO_STA_TXFIFOHE_Msk (0x1U << SDIO_STA_TXFIFOHE_Pos) /*!< 0x00004000 */
+#define SDIO_STA_TXFIFOHE SDIO_STA_TXFIFOHE_Msk /*!< Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
+#define SDIO_STA_RXFIFOHF_Pos (15U)
+#define SDIO_STA_RXFIFOHF_Msk (0x1U << SDIO_STA_RXFIFOHF_Pos) /*!< 0x00008000 */
+#define SDIO_STA_RXFIFOHF SDIO_STA_RXFIFOHF_Msk /*!< Receive FIFO Half Full: there are at least 8 words in the FIFO */
+#define SDIO_STA_TXFIFOF_Pos (16U)
+#define SDIO_STA_TXFIFOF_Msk (0x1U << SDIO_STA_TXFIFOF_Pos) /*!< 0x00010000 */
+#define SDIO_STA_TXFIFOF SDIO_STA_TXFIFOF_Msk /*!< Transmit FIFO full */
+#define SDIO_STA_RXFIFOF_Pos (17U)
+#define SDIO_STA_RXFIFOF_Msk (0x1U << SDIO_STA_RXFIFOF_Pos) /*!< 0x00020000 */
+#define SDIO_STA_RXFIFOF SDIO_STA_RXFIFOF_Msk /*!< Receive FIFO full */
+#define SDIO_STA_TXFIFOE_Pos (18U)
+#define SDIO_STA_TXFIFOE_Msk (0x1U << SDIO_STA_TXFIFOE_Pos) /*!< 0x00040000 */
+#define SDIO_STA_TXFIFOE SDIO_STA_TXFIFOE_Msk /*!< Transmit FIFO empty */
+#define SDIO_STA_RXFIFOE_Pos (19U)
+#define SDIO_STA_RXFIFOE_Msk (0x1U << SDIO_STA_RXFIFOE_Pos) /*!< 0x00080000 */
+#define SDIO_STA_RXFIFOE SDIO_STA_RXFIFOE_Msk /*!< Receive FIFO empty */
+#define SDIO_STA_TXDAVL_Pos (20U)
+#define SDIO_STA_TXDAVL_Msk (0x1U << SDIO_STA_TXDAVL_Pos) /*!< 0x00100000 */
+#define SDIO_STA_TXDAVL SDIO_STA_TXDAVL_Msk /*!< Data available in transmit FIFO */
+#define SDIO_STA_RXDAVL_Pos (21U)
+#define SDIO_STA_RXDAVL_Msk (0x1U << SDIO_STA_RXDAVL_Pos) /*!< 0x00200000 */
+#define SDIO_STA_RXDAVL SDIO_STA_RXDAVL_Msk /*!< Data available in receive FIFO */
+#define SDIO_STA_SDIOIT_Pos (22U)
+#define SDIO_STA_SDIOIT_Msk (0x1U << SDIO_STA_SDIOIT_Pos) /*!< 0x00400000 */
+#define SDIO_STA_SDIOIT SDIO_STA_SDIOIT_Msk /*!< SDIO interrupt received */
+#define SDIO_STA_CEATAEND_Pos (23U)
+#define SDIO_STA_CEATAEND_Msk (0x1U << SDIO_STA_CEATAEND_Pos) /*!< 0x00800000 */
+#define SDIO_STA_CEATAEND SDIO_STA_CEATAEND_Msk /*!< CE-ATA command completion signal received for CMD61 */
+
+/******************* Bit definition for SDIO_ICR register *******************/
+#define SDIO_ICR_CCRCFAILC_Pos (0U)
+#define SDIO_ICR_CCRCFAILC_Msk (0x1U << SDIO_ICR_CCRCFAILC_Pos) /*!< 0x00000001 */
+#define SDIO_ICR_CCRCFAILC SDIO_ICR_CCRCFAILC_Msk /*!< CCRCFAIL flag clear bit */
+#define SDIO_ICR_DCRCFAILC_Pos (1U)
+#define SDIO_ICR_DCRCFAILC_Msk (0x1U << SDIO_ICR_DCRCFAILC_Pos) /*!< 0x00000002 */
+#define SDIO_ICR_DCRCFAILC SDIO_ICR_DCRCFAILC_Msk /*!< DCRCFAIL flag clear bit */
+#define SDIO_ICR_CTIMEOUTC_Pos (2U)
+#define SDIO_ICR_CTIMEOUTC_Msk (0x1U << SDIO_ICR_CTIMEOUTC_Pos) /*!< 0x00000004 */
+#define SDIO_ICR_CTIMEOUTC SDIO_ICR_CTIMEOUTC_Msk /*!< CTIMEOUT flag clear bit */
+#define SDIO_ICR_DTIMEOUTC_Pos (3U)
+#define SDIO_ICR_DTIMEOUTC_Msk (0x1U << SDIO_ICR_DTIMEOUTC_Pos) /*!< 0x00000008 */
+#define SDIO_ICR_DTIMEOUTC SDIO_ICR_DTIMEOUTC_Msk /*!< DTIMEOUT flag clear bit */
+#define SDIO_ICR_TXUNDERRC_Pos (4U)
+#define SDIO_ICR_TXUNDERRC_Msk (0x1U << SDIO_ICR_TXUNDERRC_Pos) /*!< 0x00000010 */
+#define SDIO_ICR_TXUNDERRC SDIO_ICR_TXUNDERRC_Msk /*!< TXUNDERR flag clear bit */
+#define SDIO_ICR_RXOVERRC_Pos (5U)
+#define SDIO_ICR_RXOVERRC_Msk (0x1U << SDIO_ICR_RXOVERRC_Pos) /*!< 0x00000020 */
+#define SDIO_ICR_RXOVERRC SDIO_ICR_RXOVERRC_Msk /*!< RXOVERR flag clear bit */
+#define SDIO_ICR_CMDRENDC_Pos (6U)
+#define SDIO_ICR_CMDRENDC_Msk (0x1U << SDIO_ICR_CMDRENDC_Pos) /*!< 0x00000040 */
+#define SDIO_ICR_CMDRENDC SDIO_ICR_CMDRENDC_Msk /*!< CMDREND flag clear bit */
+#define SDIO_ICR_CMDSENTC_Pos (7U)
+#define SDIO_ICR_CMDSENTC_Msk (0x1U << SDIO_ICR_CMDSENTC_Pos) /*!< 0x00000080 */
+#define SDIO_ICR_CMDSENTC SDIO_ICR_CMDSENTC_Msk /*!< CMDSENT flag clear bit */
+#define SDIO_ICR_DATAENDC_Pos (8U)
+#define SDIO_ICR_DATAENDC_Msk (0x1U << SDIO_ICR_DATAENDC_Pos) /*!< 0x00000100 */
+#define SDIO_ICR_DATAENDC SDIO_ICR_DATAENDC_Msk /*!< DATAEND flag clear bit */
+#define SDIO_ICR_STBITERRC_Pos (9U)
+#define SDIO_ICR_STBITERRC_Msk (0x1U << SDIO_ICR_STBITERRC_Pos) /*!< 0x00000200 */
+#define SDIO_ICR_STBITERRC SDIO_ICR_STBITERRC_Msk /*!< STBITERR flag clear bit */
+#define SDIO_ICR_DBCKENDC_Pos (10U)
+#define SDIO_ICR_DBCKENDC_Msk (0x1U << SDIO_ICR_DBCKENDC_Pos) /*!< 0x00000400 */
+#define SDIO_ICR_DBCKENDC SDIO_ICR_DBCKENDC_Msk /*!< DBCKEND flag clear bit */
+#define SDIO_ICR_SDIOITC_Pos (22U)
+#define SDIO_ICR_SDIOITC_Msk (0x1U << SDIO_ICR_SDIOITC_Pos) /*!< 0x00400000 */
+#define SDIO_ICR_SDIOITC SDIO_ICR_SDIOITC_Msk /*!< SDIOIT flag clear bit */
+#define SDIO_ICR_CEATAENDC_Pos (23U)
+#define SDIO_ICR_CEATAENDC_Msk (0x1U << SDIO_ICR_CEATAENDC_Pos) /*!< 0x00800000 */
+#define SDIO_ICR_CEATAENDC SDIO_ICR_CEATAENDC_Msk /*!< CEATAEND flag clear bit */
+
+/****************** Bit definition for SDIO_MASK register *******************/
+#define SDIO_MASK_CCRCFAILIE_Pos (0U)
+#define SDIO_MASK_CCRCFAILIE_Msk (0x1U << SDIO_MASK_CCRCFAILIE_Pos) /*!< 0x00000001 */
+#define SDIO_MASK_CCRCFAILIE SDIO_MASK_CCRCFAILIE_Msk /*!< Command CRC Fail Interrupt Enable */
+#define SDIO_MASK_DCRCFAILIE_Pos (1U)
+#define SDIO_MASK_DCRCFAILIE_Msk (0x1U << SDIO_MASK_DCRCFAILIE_Pos) /*!< 0x00000002 */
+#define SDIO_MASK_DCRCFAILIE SDIO_MASK_DCRCFAILIE_Msk /*!< Data CRC Fail Interrupt Enable */
+#define SDIO_MASK_CTIMEOUTIE_Pos (2U)
+#define SDIO_MASK_CTIMEOUTIE_Msk (0x1U << SDIO_MASK_CTIMEOUTIE_Pos) /*!< 0x00000004 */
+#define SDIO_MASK_CTIMEOUTIE SDIO_MASK_CTIMEOUTIE_Msk /*!< Command TimeOut Interrupt Enable */
+#define SDIO_MASK_DTIMEOUTIE_Pos (3U)
+#define SDIO_MASK_DTIMEOUTIE_Msk (0x1U << SDIO_MASK_DTIMEOUTIE_Pos) /*!< 0x00000008 */
+#define SDIO_MASK_DTIMEOUTIE SDIO_MASK_DTIMEOUTIE_Msk /*!< Data TimeOut Interrupt Enable */
+#define SDIO_MASK_TXUNDERRIE_Pos (4U)
+#define SDIO_MASK_TXUNDERRIE_Msk (0x1U << SDIO_MASK_TXUNDERRIE_Pos) /*!< 0x00000010 */
+#define SDIO_MASK_TXUNDERRIE SDIO_MASK_TXUNDERRIE_Msk /*!< Tx FIFO UnderRun Error Interrupt Enable */
+#define SDIO_MASK_RXOVERRIE_Pos (5U)
+#define SDIO_MASK_RXOVERRIE_Msk (0x1U << SDIO_MASK_RXOVERRIE_Pos) /*!< 0x00000020 */
+#define SDIO_MASK_RXOVERRIE SDIO_MASK_RXOVERRIE_Msk /*!< Rx FIFO OverRun Error Interrupt Enable */
+#define SDIO_MASK_CMDRENDIE_Pos (6U)
+#define SDIO_MASK_CMDRENDIE_Msk (0x1U << SDIO_MASK_CMDRENDIE_Pos) /*!< 0x00000040 */
+#define SDIO_MASK_CMDRENDIE SDIO_MASK_CMDRENDIE_Msk /*!< Command Response Received Interrupt Enable */
+#define SDIO_MASK_CMDSENTIE_Pos (7U)
+#define SDIO_MASK_CMDSENTIE_Msk (0x1U << SDIO_MASK_CMDSENTIE_Pos) /*!< 0x00000080 */
+#define SDIO_MASK_CMDSENTIE SDIO_MASK_CMDSENTIE_Msk /*!< Command Sent Interrupt Enable */
+#define SDIO_MASK_DATAENDIE_Pos (8U)
+#define SDIO_MASK_DATAENDIE_Msk (0x1U << SDIO_MASK_DATAENDIE_Pos) /*!< 0x00000100 */
+#define SDIO_MASK_DATAENDIE SDIO_MASK_DATAENDIE_Msk /*!< Data End Interrupt Enable */
+#define SDIO_MASK_STBITERRIE_Pos (9U)
+#define SDIO_MASK_STBITERRIE_Msk (0x1U << SDIO_MASK_STBITERRIE_Pos) /*!< 0x00000200 */
+#define SDIO_MASK_STBITERRIE SDIO_MASK_STBITERRIE_Msk /*!< Start Bit Error Interrupt Enable */
+#define SDIO_MASK_DBCKENDIE_Pos (10U)
+#define SDIO_MASK_DBCKENDIE_Msk (0x1U << SDIO_MASK_DBCKENDIE_Pos) /*!< 0x00000400 */
+#define SDIO_MASK_DBCKENDIE SDIO_MASK_DBCKENDIE_Msk /*!< Data Block End Interrupt Enable */
+#define SDIO_MASK_CMDACTIE_Pos (11U)
+#define SDIO_MASK_CMDACTIE_Msk (0x1U << SDIO_MASK_CMDACTIE_Pos) /*!< 0x00000800 */
+#define SDIO_MASK_CMDACTIE SDIO_MASK_CMDACTIE_Msk /*!< Command Acting Interrupt Enable */
+#define SDIO_MASK_TXACTIE_Pos (12U)
+#define SDIO_MASK_TXACTIE_Msk (0x1U << SDIO_MASK_TXACTIE_Pos) /*!< 0x00001000 */
+#define SDIO_MASK_TXACTIE SDIO_MASK_TXACTIE_Msk /*!< Data Transmit Acting Interrupt Enable */
+#define SDIO_MASK_RXACTIE_Pos (13U)
+#define SDIO_MASK_RXACTIE_Msk (0x1U << SDIO_MASK_RXACTIE_Pos) /*!< 0x00002000 */
+#define SDIO_MASK_RXACTIE SDIO_MASK_RXACTIE_Msk /*!< Data receive acting interrupt enabled */
+#define SDIO_MASK_TXFIFOHEIE_Pos (14U)
+#define SDIO_MASK_TXFIFOHEIE_Msk (0x1U << SDIO_MASK_TXFIFOHEIE_Pos) /*!< 0x00004000 */
+#define SDIO_MASK_TXFIFOHEIE SDIO_MASK_TXFIFOHEIE_Msk /*!< Tx FIFO Half Empty interrupt Enable */
+#define SDIO_MASK_RXFIFOHFIE_Pos (15U)
+#define SDIO_MASK_RXFIFOHFIE_Msk (0x1U << SDIO_MASK_RXFIFOHFIE_Pos) /*!< 0x00008000 */
+#define SDIO_MASK_RXFIFOHFIE SDIO_MASK_RXFIFOHFIE_Msk /*!< Rx FIFO Half Full interrupt Enable */
+#define SDIO_MASK_TXFIFOFIE_Pos (16U)
+#define SDIO_MASK_TXFIFOFIE_Msk (0x1U << SDIO_MASK_TXFIFOFIE_Pos) /*!< 0x00010000 */
+#define SDIO_MASK_TXFIFOFIE SDIO_MASK_TXFIFOFIE_Msk /*!< Tx FIFO Full interrupt Enable */
+#define SDIO_MASK_RXFIFOFIE_Pos (17U)
+#define SDIO_MASK_RXFIFOFIE_Msk (0x1U << SDIO_MASK_RXFIFOFIE_Pos) /*!< 0x00020000 */
+#define SDIO_MASK_RXFIFOFIE SDIO_MASK_RXFIFOFIE_Msk /*!< Rx FIFO Full interrupt Enable */
+#define SDIO_MASK_TXFIFOEIE_Pos (18U)
+#define SDIO_MASK_TXFIFOEIE_Msk (0x1U << SDIO_MASK_TXFIFOEIE_Pos) /*!< 0x00040000 */
+#define SDIO_MASK_TXFIFOEIE SDIO_MASK_TXFIFOEIE_Msk /*!< Tx FIFO Empty interrupt Enable */
+#define SDIO_MASK_RXFIFOEIE_Pos (19U)
+#define SDIO_MASK_RXFIFOEIE_Msk (0x1U << SDIO_MASK_RXFIFOEIE_Pos) /*!< 0x00080000 */
+#define SDIO_MASK_RXFIFOEIE SDIO_MASK_RXFIFOEIE_Msk /*!< Rx FIFO Empty interrupt Enable */
+#define SDIO_MASK_TXDAVLIE_Pos (20U)
+#define SDIO_MASK_TXDAVLIE_Msk (0x1U << SDIO_MASK_TXDAVLIE_Pos) /*!< 0x00100000 */
+#define SDIO_MASK_TXDAVLIE SDIO_MASK_TXDAVLIE_Msk /*!< Data available in Tx FIFO interrupt Enable */
+#define SDIO_MASK_RXDAVLIE_Pos (21U)
+#define SDIO_MASK_RXDAVLIE_Msk (0x1U << SDIO_MASK_RXDAVLIE_Pos) /*!< 0x00200000 */
+#define SDIO_MASK_RXDAVLIE SDIO_MASK_RXDAVLIE_Msk /*!< Data available in Rx FIFO interrupt Enable */
+#define SDIO_MASK_SDIOITIE_Pos (22U)
+#define SDIO_MASK_SDIOITIE_Msk (0x1U << SDIO_MASK_SDIOITIE_Pos) /*!< 0x00400000 */
+#define SDIO_MASK_SDIOITIE SDIO_MASK_SDIOITIE_Msk /*!< SDIO Mode Interrupt Received interrupt Enable */
+#define SDIO_MASK_CEATAENDIE_Pos (23U)
+#define SDIO_MASK_CEATAENDIE_Msk (0x1U << SDIO_MASK_CEATAENDIE_Pos) /*!< 0x00800000 */
+#define SDIO_MASK_CEATAENDIE SDIO_MASK_CEATAENDIE_Msk /*!< CE-ATA command completion signal received Interrupt Enable */
+
+/***************** Bit definition for SDIO_FIFOCNT register *****************/
+#define SDIO_FIFOCNT_FIFOCOUNT_Pos (0U)
+#define SDIO_FIFOCNT_FIFOCOUNT_Msk (0xFFFFFFU << SDIO_FIFOCNT_FIFOCOUNT_Pos) /*!< 0x00FFFFFF */
+#define SDIO_FIFOCNT_FIFOCOUNT SDIO_FIFOCNT_FIFOCOUNT_Msk /*!< Remaining number of words to be written to or read from the FIFO */
+
+/****************** Bit definition for SDIO_FIFO register *******************/
+#define SDIO_FIFO_FIFODATA_Pos (0U)
+#define SDIO_FIFO_FIFODATA_Msk (0xFFFFFFFFU << SDIO_FIFO_FIFODATA_Pos) /*!< 0xFFFFFFFF */
+#define SDIO_FIFO_FIFODATA SDIO_FIFO_FIFODATA_Msk /*!< Receive and transmit FIFO data */
+
+/******************************************************************************/
+/* */
+/* USB Device FS */
+/* */
+/******************************************************************************/
+
+/*!< Endpoint-specific registers */
+#define USB_EP0R USB_BASE /*!< Endpoint 0 register address */
+#define USB_EP1R (USB_BASE + 0x00000004) /*!< Endpoint 1 register address */
+#define USB_EP2R (USB_BASE + 0x00000008) /*!< Endpoint 2 register address */
+#define USB_EP3R (USB_BASE + 0x0000000C) /*!< Endpoint 3 register address */
+#define USB_EP4R (USB_BASE + 0x00000010) /*!< Endpoint 4 register address */
+#define USB_EP5R (USB_BASE + 0x00000014) /*!< Endpoint 5 register address */
+#define USB_EP6R (USB_BASE + 0x00000018) /*!< Endpoint 6 register address */
+#define USB_EP7R (USB_BASE + 0x0000001C) /*!< Endpoint 7 register address */
+
+/* bit positions */
+#define USB_EP_CTR_RX_Pos (15U)
+#define USB_EP_CTR_RX_Msk (0x1U << USB_EP_CTR_RX_Pos) /*!< 0x00008000 */
+#define USB_EP_CTR_RX USB_EP_CTR_RX_Msk /*!< EndPoint Correct TRansfer RX */
+#define USB_EP_DTOG_RX_Pos (14U)
+#define USB_EP_DTOG_RX_Msk (0x1U << USB_EP_DTOG_RX_Pos) /*!< 0x00004000 */
+#define USB_EP_DTOG_RX USB_EP_DTOG_RX_Msk /*!< EndPoint Data TOGGLE RX */
+#define USB_EPRX_STAT_Pos (12U)
+#define USB_EPRX_STAT_Msk (0x3U << USB_EPRX_STAT_Pos) /*!< 0x00003000 */
+#define USB_EPRX_STAT USB_EPRX_STAT_Msk /*!< EndPoint RX STATus bit field */
+#define USB_EP_SETUP_Pos (11U)
+#define USB_EP_SETUP_Msk (0x1U << USB_EP_SETUP_Pos) /*!< 0x00000800 */
+#define USB_EP_SETUP USB_EP_SETUP_Msk /*!< EndPoint SETUP */
+#define USB_EP_T_FIELD_Pos (9U)
+#define USB_EP_T_FIELD_Msk (0x3U << USB_EP_T_FIELD_Pos) /*!< 0x00000600 */
+#define USB_EP_T_FIELD USB_EP_T_FIELD_Msk /*!< EndPoint TYPE */
+#define USB_EP_KIND_Pos (8U)
+#define USB_EP_KIND_Msk (0x1U << USB_EP_KIND_Pos) /*!< 0x00000100 */
+#define USB_EP_KIND USB_EP_KIND_Msk /*!< EndPoint KIND */
+#define USB_EP_CTR_TX_Pos (7U)
+#define USB_EP_CTR_TX_Msk (0x1U << USB_EP_CTR_TX_Pos) /*!< 0x00000080 */
+#define USB_EP_CTR_TX USB_EP_CTR_TX_Msk /*!< EndPoint Correct TRansfer TX */
+#define USB_EP_DTOG_TX_Pos (6U)
+#define USB_EP_DTOG_TX_Msk (0x1U << USB_EP_DTOG_TX_Pos) /*!< 0x00000040 */
+#define USB_EP_DTOG_TX USB_EP_DTOG_TX_Msk /*!< EndPoint Data TOGGLE TX */
+#define USB_EPTX_STAT_Pos (4U)
+#define USB_EPTX_STAT_Msk (0x3U << USB_EPTX_STAT_Pos) /*!< 0x00000030 */
+#define USB_EPTX_STAT USB_EPTX_STAT_Msk /*!< EndPoint TX STATus bit field */
+#define USB_EPADDR_FIELD_Pos (0U)
+#define USB_EPADDR_FIELD_Msk (0xFU << USB_EPADDR_FIELD_Pos) /*!< 0x0000000F */
+#define USB_EPADDR_FIELD USB_EPADDR_FIELD_Msk /*!< EndPoint ADDRess FIELD */
+
+/* EndPoint REGister MASK (no toggle fields) */
+#define USB_EPREG_MASK (USB_EP_CTR_RX|USB_EP_SETUP|USB_EP_T_FIELD|USB_EP_KIND|USB_EP_CTR_TX|USB_EPADDR_FIELD)
+ /*!< EP_TYPE[1:0] EndPoint TYPE */
+#define USB_EP_TYPE_MASK_Pos (9U)
+#define USB_EP_TYPE_MASK_Msk (0x3U << USB_EP_TYPE_MASK_Pos) /*!< 0x00000600 */
+#define USB_EP_TYPE_MASK USB_EP_TYPE_MASK_Msk /*!< EndPoint TYPE Mask */
+#define USB_EP_BULK ((uint32_t)0x00000000) /*!< EndPoint BULK */
+#define USB_EP_CONTROL ((uint32_t)0x00000200) /*!< EndPoint CONTROL */
+#define USB_EP_ISOCHRONOUS ((uint32_t)0x00000400) /*!< EndPoint ISOCHRONOUS */
+#define USB_EP_INTERRUPT ((uint32_t)0x00000600) /*!< EndPoint INTERRUPT */
+#define USB_EP_T_MASK (~USB_EP_T_FIELD & USB_EPREG_MASK)
+
+#define USB_EPKIND_MASK (~USB_EP_KIND & USB_EPREG_MASK) /*!< EP_KIND EndPoint KIND */
+ /*!< STAT_TX[1:0] STATus for TX transfer */
+#define USB_EP_TX_DIS ((uint32_t)0x00000000) /*!< EndPoint TX DISabled */
+#define USB_EP_TX_STALL ((uint32_t)0x00000010) /*!< EndPoint TX STALLed */
+#define USB_EP_TX_NAK ((uint32_t)0x00000020) /*!< EndPoint TX NAKed */
+#define USB_EP_TX_VALID ((uint32_t)0x00000030) /*!< EndPoint TX VALID */
+#define USB_EPTX_DTOG1 ((uint32_t)0x00000010) /*!< EndPoint TX Data TOGgle bit1 */
+#define USB_EPTX_DTOG2 ((uint32_t)0x00000020) /*!< EndPoint TX Data TOGgle bit2 */
+#define USB_EPTX_DTOGMASK (USB_EPTX_STAT|USB_EPREG_MASK)
+ /*!< STAT_RX[1:0] STATus for RX transfer */
+#define USB_EP_RX_DIS ((uint32_t)0x00000000) /*!< EndPoint RX DISabled */
+#define USB_EP_RX_STALL ((uint32_t)0x00001000) /*!< EndPoint RX STALLed */
+#define USB_EP_RX_NAK ((uint32_t)0x00002000) /*!< EndPoint RX NAKed */
+#define USB_EP_RX_VALID ((uint32_t)0x00003000) /*!< EndPoint RX VALID */
+#define USB_EPRX_DTOG1 ((uint32_t)0x00001000) /*!< EndPoint RX Data TOGgle bit1 */
+#define USB_EPRX_DTOG2 ((uint32_t)0x00002000) /*!< EndPoint RX Data TOGgle bit1 */
+#define USB_EPRX_DTOGMASK (USB_EPRX_STAT|USB_EPREG_MASK)
+
+/******************* Bit definition for USB_EP0R register *******************/
+#define USB_EP0R_EA_Pos (0U)
+#define USB_EP0R_EA_Msk (0xFU << USB_EP0R_EA_Pos) /*!< 0x0000000F */
+#define USB_EP0R_EA USB_EP0R_EA_Msk /*!< Endpoint Address */
+
+#define USB_EP0R_STAT_TX_Pos (4U)
+#define USB_EP0R_STAT_TX_Msk (0x3U << USB_EP0R_STAT_TX_Pos) /*!< 0x00000030 */
+#define USB_EP0R_STAT_TX USB_EP0R_STAT_TX_Msk /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */
+#define USB_EP0R_STAT_TX_0 (0x1U << USB_EP0R_STAT_TX_Pos) /*!< 0x00000010 */
+#define USB_EP0R_STAT_TX_1 (0x2U << USB_EP0R_STAT_TX_Pos) /*!< 0x00000020 */
+
+#define USB_EP0R_DTOG_TX_Pos (6U)
+#define USB_EP0R_DTOG_TX_Msk (0x1U << USB_EP0R_DTOG_TX_Pos) /*!< 0x00000040 */
+#define USB_EP0R_DTOG_TX USB_EP0R_DTOG_TX_Msk /*!< Data Toggle, for transmission transfers */
+#define USB_EP0R_CTR_TX_Pos (7U)
+#define USB_EP0R_CTR_TX_Msk (0x1U << USB_EP0R_CTR_TX_Pos) /*!< 0x00000080 */
+#define USB_EP0R_CTR_TX USB_EP0R_CTR_TX_Msk /*!< Correct Transfer for transmission */
+#define USB_EP0R_EP_KIND_Pos (8U)
+#define USB_EP0R_EP_KIND_Msk (0x1U << USB_EP0R_EP_KIND_Pos) /*!< 0x00000100 */
+#define USB_EP0R_EP_KIND USB_EP0R_EP_KIND_Msk /*!< Endpoint Kind */
+
+#define USB_EP0R_EP_TYPE_Pos (9U)
+#define USB_EP0R_EP_TYPE_Msk (0x3U << USB_EP0R_EP_TYPE_Pos) /*!< 0x00000600 */
+#define USB_EP0R_EP_TYPE USB_EP0R_EP_TYPE_Msk /*!< EP_TYPE[1:0] bits (Endpoint type) */
+#define USB_EP0R_EP_TYPE_0 (0x1U << USB_EP0R_EP_TYPE_Pos) /*!< 0x00000200 */
+#define USB_EP0R_EP_TYPE_1 (0x2U << USB_EP0R_EP_TYPE_Pos) /*!< 0x00000400 */
+
+#define USB_EP0R_SETUP_Pos (11U)
+#define USB_EP0R_SETUP_Msk (0x1U << USB_EP0R_SETUP_Pos) /*!< 0x00000800 */
+#define USB_EP0R_SETUP USB_EP0R_SETUP_Msk /*!< Setup transaction completed */
+
+#define USB_EP0R_STAT_RX_Pos (12U)
+#define USB_EP0R_STAT_RX_Msk (0x3U << USB_EP0R_STAT_RX_Pos) /*!< 0x00003000 */
+#define USB_EP0R_STAT_RX USB_EP0R_STAT_RX_Msk /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */
+#define USB_EP0R_STAT_RX_0 (0x1U << USB_EP0R_STAT_RX_Pos) /*!< 0x00001000 */
+#define USB_EP0R_STAT_RX_1 (0x2U << USB_EP0R_STAT_RX_Pos) /*!< 0x00002000 */
+
+#define USB_EP0R_DTOG_RX_Pos (14U)
+#define USB_EP0R_DTOG_RX_Msk (0x1U << USB_EP0R_DTOG_RX_Pos) /*!< 0x00004000 */
+#define USB_EP0R_DTOG_RX USB_EP0R_DTOG_RX_Msk /*!< Data Toggle, for reception transfers */
+#define USB_EP0R_CTR_RX_Pos (15U)
+#define USB_EP0R_CTR_RX_Msk (0x1U << USB_EP0R_CTR_RX_Pos) /*!< 0x00008000 */
+#define USB_EP0R_CTR_RX USB_EP0R_CTR_RX_Msk /*!< Correct Transfer for reception */
+
+/******************* Bit definition for USB_EP1R register *******************/
+#define USB_EP1R_EA_Pos (0U)
+#define USB_EP1R_EA_Msk (0xFU << USB_EP1R_EA_Pos) /*!< 0x0000000F */
+#define USB_EP1R_EA USB_EP1R_EA_Msk /*!< Endpoint Address */
+
+#define USB_EP1R_STAT_TX_Pos (4U)
+#define USB_EP1R_STAT_TX_Msk (0x3U << USB_EP1R_STAT_TX_Pos) /*!< 0x00000030 */
+#define USB_EP1R_STAT_TX USB_EP1R_STAT_TX_Msk /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */
+#define USB_EP1R_STAT_TX_0 (0x1U << USB_EP1R_STAT_TX_Pos) /*!< 0x00000010 */
+#define USB_EP1R_STAT_TX_1 (0x2U << USB_EP1R_STAT_TX_Pos) /*!< 0x00000020 */
+
+#define USB_EP1R_DTOG_TX_Pos (6U)
+#define USB_EP1R_DTOG_TX_Msk (0x1U << USB_EP1R_DTOG_TX_Pos) /*!< 0x00000040 */
+#define USB_EP1R_DTOG_TX USB_EP1R_DTOG_TX_Msk /*!< Data Toggle, for transmission transfers */
+#define USB_EP1R_CTR_TX_Pos (7U)
+#define USB_EP1R_CTR_TX_Msk (0x1U << USB_EP1R_CTR_TX_Pos) /*!< 0x00000080 */
+#define USB_EP1R_CTR_TX USB_EP1R_CTR_TX_Msk /*!< Correct Transfer for transmission */
+#define USB_EP1R_EP_KIND_Pos (8U)
+#define USB_EP1R_EP_KIND_Msk (0x1U << USB_EP1R_EP_KIND_Pos) /*!< 0x00000100 */
+#define USB_EP1R_EP_KIND USB_EP1R_EP_KIND_Msk /*!< Endpoint Kind */
+
+#define USB_EP1R_EP_TYPE_Pos (9U)
+#define USB_EP1R_EP_TYPE_Msk (0x3U << USB_EP1R_EP_TYPE_Pos) /*!< 0x00000600 */
+#define USB_EP1R_EP_TYPE USB_EP1R_EP_TYPE_Msk /*!< EP_TYPE[1:0] bits (Endpoint type) */
+#define USB_EP1R_EP_TYPE_0 (0x1U << USB_EP1R_EP_TYPE_Pos) /*!< 0x00000200 */
+#define USB_EP1R_EP_TYPE_1 (0x2U << USB_EP1R_EP_TYPE_Pos) /*!< 0x00000400 */
+
+#define USB_EP1R_SETUP_Pos (11U)
+#define USB_EP1R_SETUP_Msk (0x1U << USB_EP1R_SETUP_Pos) /*!< 0x00000800 */
+#define USB_EP1R_SETUP USB_EP1R_SETUP_Msk /*!< Setup transaction completed */
+
+#define USB_EP1R_STAT_RX_Pos (12U)
+#define USB_EP1R_STAT_RX_Msk (0x3U << USB_EP1R_STAT_RX_Pos) /*!< 0x00003000 */
+#define USB_EP1R_STAT_RX USB_EP1R_STAT_RX_Msk /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */
+#define USB_EP1R_STAT_RX_0 (0x1U << USB_EP1R_STAT_RX_Pos) /*!< 0x00001000 */
+#define USB_EP1R_STAT_RX_1 (0x2U << USB_EP1R_STAT_RX_Pos) /*!< 0x00002000 */
+
+#define USB_EP1R_DTOG_RX_Pos (14U)
+#define USB_EP1R_DTOG_RX_Msk (0x1U << USB_EP1R_DTOG_RX_Pos) /*!< 0x00004000 */
+#define USB_EP1R_DTOG_RX USB_EP1R_DTOG_RX_Msk /*!< Data Toggle, for reception transfers */
+#define USB_EP1R_CTR_RX_Pos (15U)
+#define USB_EP1R_CTR_RX_Msk (0x1U << USB_EP1R_CTR_RX_Pos) /*!< 0x00008000 */
+#define USB_EP1R_CTR_RX USB_EP1R_CTR_RX_Msk /*!< Correct Transfer for reception */
+
+/******************* Bit definition for USB_EP2R register *******************/
+#define USB_EP2R_EA_Pos (0U)
+#define USB_EP2R_EA_Msk (0xFU << USB_EP2R_EA_Pos) /*!< 0x0000000F */
+#define USB_EP2R_EA USB_EP2R_EA_Msk /*!< Endpoint Address */
+
+#define USB_EP2R_STAT_TX_Pos (4U)
+#define USB_EP2R_STAT_TX_Msk (0x3U << USB_EP2R_STAT_TX_Pos) /*!< 0x00000030 */
+#define USB_EP2R_STAT_TX USB_EP2R_STAT_TX_Msk /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */
+#define USB_EP2R_STAT_TX_0 (0x1U << USB_EP2R_STAT_TX_Pos) /*!< 0x00000010 */
+#define USB_EP2R_STAT_TX_1 (0x2U << USB_EP2R_STAT_TX_Pos) /*!< 0x00000020 */
+
+#define USB_EP2R_DTOG_TX_Pos (6U)
+#define USB_EP2R_DTOG_TX_Msk (0x1U << USB_EP2R_DTOG_TX_Pos) /*!< 0x00000040 */
+#define USB_EP2R_DTOG_TX USB_EP2R_DTOG_TX_Msk /*!< Data Toggle, for transmission transfers */
+#define USB_EP2R_CTR_TX_Pos (7U)
+#define USB_EP2R_CTR_TX_Msk (0x1U << USB_EP2R_CTR_TX_Pos) /*!< 0x00000080 */
+#define USB_EP2R_CTR_TX USB_EP2R_CTR_TX_Msk /*!< Correct Transfer for transmission */
+#define USB_EP2R_EP_KIND_Pos (8U)
+#define USB_EP2R_EP_KIND_Msk (0x1U << USB_EP2R_EP_KIND_Pos) /*!< 0x00000100 */
+#define USB_EP2R_EP_KIND USB_EP2R_EP_KIND_Msk /*!< Endpoint Kind */
+
+#define USB_EP2R_EP_TYPE_Pos (9U)
+#define USB_EP2R_EP_TYPE_Msk (0x3U << USB_EP2R_EP_TYPE_Pos) /*!< 0x00000600 */
+#define USB_EP2R_EP_TYPE USB_EP2R_EP_TYPE_Msk /*!< EP_TYPE[1:0] bits (Endpoint type) */
+#define USB_EP2R_EP_TYPE_0 (0x1U << USB_EP2R_EP_TYPE_Pos) /*!< 0x00000200 */
+#define USB_EP2R_EP_TYPE_1 (0x2U << USB_EP2R_EP_TYPE_Pos) /*!< 0x00000400 */
+
+#define USB_EP2R_SETUP_Pos (11U)
+#define USB_EP2R_SETUP_Msk (0x1U << USB_EP2R_SETUP_Pos) /*!< 0x00000800 */
+#define USB_EP2R_SETUP USB_EP2R_SETUP_Msk /*!< Setup transaction completed */
+
+#define USB_EP2R_STAT_RX_Pos (12U)
+#define USB_EP2R_STAT_RX_Msk (0x3U << USB_EP2R_STAT_RX_Pos) /*!< 0x00003000 */
+#define USB_EP2R_STAT_RX USB_EP2R_STAT_RX_Msk /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */
+#define USB_EP2R_STAT_RX_0 (0x1U << USB_EP2R_STAT_RX_Pos) /*!< 0x00001000 */
+#define USB_EP2R_STAT_RX_1 (0x2U << USB_EP2R_STAT_RX_Pos) /*!< 0x00002000 */
+
+#define USB_EP2R_DTOG_RX_Pos (14U)
+#define USB_EP2R_DTOG_RX_Msk (0x1U << USB_EP2R_DTOG_RX_Pos) /*!< 0x00004000 */
+#define USB_EP2R_DTOG_RX USB_EP2R_DTOG_RX_Msk /*!< Data Toggle, for reception transfers */
+#define USB_EP2R_CTR_RX_Pos (15U)
+#define USB_EP2R_CTR_RX_Msk (0x1U << USB_EP2R_CTR_RX_Pos) /*!< 0x00008000 */
+#define USB_EP2R_CTR_RX USB_EP2R_CTR_RX_Msk /*!< Correct Transfer for reception */
+
+/******************* Bit definition for USB_EP3R register *******************/
+#define USB_EP3R_EA_Pos (0U)
+#define USB_EP3R_EA_Msk (0xFU << USB_EP3R_EA_Pos) /*!< 0x0000000F */
+#define USB_EP3R_EA USB_EP3R_EA_Msk /*!< Endpoint Address */
+
+#define USB_EP3R_STAT_TX_Pos (4U)
+#define USB_EP3R_STAT_TX_Msk (0x3U << USB_EP3R_STAT_TX_Pos) /*!< 0x00000030 */
+#define USB_EP3R_STAT_TX USB_EP3R_STAT_TX_Msk /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */
+#define USB_EP3R_STAT_TX_0 (0x1U << USB_EP3R_STAT_TX_Pos) /*!< 0x00000010 */
+#define USB_EP3R_STAT_TX_1 (0x2U << USB_EP3R_STAT_TX_Pos) /*!< 0x00000020 */
+
+#define USB_EP3R_DTOG_TX_Pos (6U)
+#define USB_EP3R_DTOG_TX_Msk (0x1U << USB_EP3R_DTOG_TX_Pos) /*!< 0x00000040 */
+#define USB_EP3R_DTOG_TX USB_EP3R_DTOG_TX_Msk /*!< Data Toggle, for transmission transfers */
+#define USB_EP3R_CTR_TX_Pos (7U)
+#define USB_EP3R_CTR_TX_Msk (0x1U << USB_EP3R_CTR_TX_Pos) /*!< 0x00000080 */
+#define USB_EP3R_CTR_TX USB_EP3R_CTR_TX_Msk /*!< Correct Transfer for transmission */
+#define USB_EP3R_EP_KIND_Pos (8U)
+#define USB_EP3R_EP_KIND_Msk (0x1U << USB_EP3R_EP_KIND_Pos) /*!< 0x00000100 */
+#define USB_EP3R_EP_KIND USB_EP3R_EP_KIND_Msk /*!< Endpoint Kind */
+
+#define USB_EP3R_EP_TYPE_Pos (9U)
+#define USB_EP3R_EP_TYPE_Msk (0x3U << USB_EP3R_EP_TYPE_Pos) /*!< 0x00000600 */
+#define USB_EP3R_EP_TYPE USB_EP3R_EP_TYPE_Msk /*!< EP_TYPE[1:0] bits (Endpoint type) */
+#define USB_EP3R_EP_TYPE_0 (0x1U << USB_EP3R_EP_TYPE_Pos) /*!< 0x00000200 */
+#define USB_EP3R_EP_TYPE_1 (0x2U << USB_EP3R_EP_TYPE_Pos) /*!< 0x00000400 */
+
+#define USB_EP3R_SETUP_Pos (11U)
+#define USB_EP3R_SETUP_Msk (0x1U << USB_EP3R_SETUP_Pos) /*!< 0x00000800 */
+#define USB_EP3R_SETUP USB_EP3R_SETUP_Msk /*!< Setup transaction completed */
+
+#define USB_EP3R_STAT_RX_Pos (12U)
+#define USB_EP3R_STAT_RX_Msk (0x3U << USB_EP3R_STAT_RX_Pos) /*!< 0x00003000 */
+#define USB_EP3R_STAT_RX USB_EP3R_STAT_RX_Msk /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */
+#define USB_EP3R_STAT_RX_0 (0x1U << USB_EP3R_STAT_RX_Pos) /*!< 0x00001000 */
+#define USB_EP3R_STAT_RX_1 (0x2U << USB_EP3R_STAT_RX_Pos) /*!< 0x00002000 */
+
+#define USB_EP3R_DTOG_RX_Pos (14U)
+#define USB_EP3R_DTOG_RX_Msk (0x1U << USB_EP3R_DTOG_RX_Pos) /*!< 0x00004000 */
+#define USB_EP3R_DTOG_RX USB_EP3R_DTOG_RX_Msk /*!< Data Toggle, for reception transfers */
+#define USB_EP3R_CTR_RX_Pos (15U)
+#define USB_EP3R_CTR_RX_Msk (0x1U << USB_EP3R_CTR_RX_Pos) /*!< 0x00008000 */
+#define USB_EP3R_CTR_RX USB_EP3R_CTR_RX_Msk /*!< Correct Transfer for reception */
+
+/******************* Bit definition for USB_EP4R register *******************/
+#define USB_EP4R_EA_Pos (0U)
+#define USB_EP4R_EA_Msk (0xFU << USB_EP4R_EA_Pos) /*!< 0x0000000F */
+#define USB_EP4R_EA USB_EP4R_EA_Msk /*!< Endpoint Address */
+
+#define USB_EP4R_STAT_TX_Pos (4U)
+#define USB_EP4R_STAT_TX_Msk (0x3U << USB_EP4R_STAT_TX_Pos) /*!< 0x00000030 */
+#define USB_EP4R_STAT_TX USB_EP4R_STAT_TX_Msk /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */
+#define USB_EP4R_STAT_TX_0 (0x1U << USB_EP4R_STAT_TX_Pos) /*!< 0x00000010 */
+#define USB_EP4R_STAT_TX_1 (0x2U << USB_EP4R_STAT_TX_Pos) /*!< 0x00000020 */
+
+#define USB_EP4R_DTOG_TX_Pos (6U)
+#define USB_EP4R_DTOG_TX_Msk (0x1U << USB_EP4R_DTOG_TX_Pos) /*!< 0x00000040 */
+#define USB_EP4R_DTOG_TX USB_EP4R_DTOG_TX_Msk /*!< Data Toggle, for transmission transfers */
+#define USB_EP4R_CTR_TX_Pos (7U)
+#define USB_EP4R_CTR_TX_Msk (0x1U << USB_EP4R_CTR_TX_Pos) /*!< 0x00000080 */
+#define USB_EP4R_CTR_TX USB_EP4R_CTR_TX_Msk /*!< Correct Transfer for transmission */
+#define USB_EP4R_EP_KIND_Pos (8U)
+#define USB_EP4R_EP_KIND_Msk (0x1U << USB_EP4R_EP_KIND_Pos) /*!< 0x00000100 */
+#define USB_EP4R_EP_KIND USB_EP4R_EP_KIND_Msk /*!< Endpoint Kind */
+
+#define USB_EP4R_EP_TYPE_Pos (9U)
+#define USB_EP4R_EP_TYPE_Msk (0x3U << USB_EP4R_EP_TYPE_Pos) /*!< 0x00000600 */
+#define USB_EP4R_EP_TYPE USB_EP4R_EP_TYPE_Msk /*!< EP_TYPE[1:0] bits (Endpoint type) */
+#define USB_EP4R_EP_TYPE_0 (0x1U << USB_EP4R_EP_TYPE_Pos) /*!< 0x00000200 */
+#define USB_EP4R_EP_TYPE_1 (0x2U << USB_EP4R_EP_TYPE_Pos) /*!< 0x00000400 */
+
+#define USB_EP4R_SETUP_Pos (11U)
+#define USB_EP4R_SETUP_Msk (0x1U << USB_EP4R_SETUP_Pos) /*!< 0x00000800 */
+#define USB_EP4R_SETUP USB_EP4R_SETUP_Msk /*!< Setup transaction completed */
+
+#define USB_EP4R_STAT_RX_Pos (12U)
+#define USB_EP4R_STAT_RX_Msk (0x3U << USB_EP4R_STAT_RX_Pos) /*!< 0x00003000 */
+#define USB_EP4R_STAT_RX USB_EP4R_STAT_RX_Msk /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */
+#define USB_EP4R_STAT_RX_0 (0x1U << USB_EP4R_STAT_RX_Pos) /*!< 0x00001000 */
+#define USB_EP4R_STAT_RX_1 (0x2U << USB_EP4R_STAT_RX_Pos) /*!< 0x00002000 */
+
+#define USB_EP4R_DTOG_RX_Pos (14U)
+#define USB_EP4R_DTOG_RX_Msk (0x1U << USB_EP4R_DTOG_RX_Pos) /*!< 0x00004000 */
+#define USB_EP4R_DTOG_RX USB_EP4R_DTOG_RX_Msk /*!< Data Toggle, for reception transfers */
+#define USB_EP4R_CTR_RX_Pos (15U)
+#define USB_EP4R_CTR_RX_Msk (0x1U << USB_EP4R_CTR_RX_Pos) /*!< 0x00008000 */
+#define USB_EP4R_CTR_RX USB_EP4R_CTR_RX_Msk /*!< Correct Transfer for reception */
+
+/******************* Bit definition for USB_EP5R register *******************/
+#define USB_EP5R_EA_Pos (0U)
+#define USB_EP5R_EA_Msk (0xFU << USB_EP5R_EA_Pos) /*!< 0x0000000F */
+#define USB_EP5R_EA USB_EP5R_EA_Msk /*!< Endpoint Address */
+
+#define USB_EP5R_STAT_TX_Pos (4U)
+#define USB_EP5R_STAT_TX_Msk (0x3U << USB_EP5R_STAT_TX_Pos) /*!< 0x00000030 */
+#define USB_EP5R_STAT_TX USB_EP5R_STAT_TX_Msk /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */
+#define USB_EP5R_STAT_TX_0 (0x1U << USB_EP5R_STAT_TX_Pos) /*!< 0x00000010 */
+#define USB_EP5R_STAT_TX_1 (0x2U << USB_EP5R_STAT_TX_Pos) /*!< 0x00000020 */
+
+#define USB_EP5R_DTOG_TX_Pos (6U)
+#define USB_EP5R_DTOG_TX_Msk (0x1U << USB_EP5R_DTOG_TX_Pos) /*!< 0x00000040 */
+#define USB_EP5R_DTOG_TX USB_EP5R_DTOG_TX_Msk /*!< Data Toggle, for transmission transfers */
+#define USB_EP5R_CTR_TX_Pos (7U)
+#define USB_EP5R_CTR_TX_Msk (0x1U << USB_EP5R_CTR_TX_Pos) /*!< 0x00000080 */
+#define USB_EP5R_CTR_TX USB_EP5R_CTR_TX_Msk /*!< Correct Transfer for transmission */
+#define USB_EP5R_EP_KIND_Pos (8U)
+#define USB_EP5R_EP_KIND_Msk (0x1U << USB_EP5R_EP_KIND_Pos) /*!< 0x00000100 */
+#define USB_EP5R_EP_KIND USB_EP5R_EP_KIND_Msk /*!< Endpoint Kind */
+
+#define USB_EP5R_EP_TYPE_Pos (9U)
+#define USB_EP5R_EP_TYPE_Msk (0x3U << USB_EP5R_EP_TYPE_Pos) /*!< 0x00000600 */
+#define USB_EP5R_EP_TYPE USB_EP5R_EP_TYPE_Msk /*!< EP_TYPE[1:0] bits (Endpoint type) */
+#define USB_EP5R_EP_TYPE_0 (0x1U << USB_EP5R_EP_TYPE_Pos) /*!< 0x00000200 */
+#define USB_EP5R_EP_TYPE_1 (0x2U << USB_EP5R_EP_TYPE_Pos) /*!< 0x00000400 */
+
+#define USB_EP5R_SETUP_Pos (11U)
+#define USB_EP5R_SETUP_Msk (0x1U << USB_EP5R_SETUP_Pos) /*!< 0x00000800 */
+#define USB_EP5R_SETUP USB_EP5R_SETUP_Msk /*!< Setup transaction completed */
+
+#define USB_EP5R_STAT_RX_Pos (12U)
+#define USB_EP5R_STAT_RX_Msk (0x3U << USB_EP5R_STAT_RX_Pos) /*!< 0x00003000 */
+#define USB_EP5R_STAT_RX USB_EP5R_STAT_RX_Msk /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */
+#define USB_EP5R_STAT_RX_0 (0x1U << USB_EP5R_STAT_RX_Pos) /*!< 0x00001000 */
+#define USB_EP5R_STAT_RX_1 (0x2U << USB_EP5R_STAT_RX_Pos) /*!< 0x00002000 */
+
+#define USB_EP5R_DTOG_RX_Pos (14U)
+#define USB_EP5R_DTOG_RX_Msk (0x1U << USB_EP5R_DTOG_RX_Pos) /*!< 0x00004000 */
+#define USB_EP5R_DTOG_RX USB_EP5R_DTOG_RX_Msk /*!< Data Toggle, for reception transfers */
+#define USB_EP5R_CTR_RX_Pos (15U)
+#define USB_EP5R_CTR_RX_Msk (0x1U << USB_EP5R_CTR_RX_Pos) /*!< 0x00008000 */
+#define USB_EP5R_CTR_RX USB_EP5R_CTR_RX_Msk /*!< Correct Transfer for reception */
+
+/******************* Bit definition for USB_EP6R register *******************/
+#define USB_EP6R_EA_Pos (0U)
+#define USB_EP6R_EA_Msk (0xFU << USB_EP6R_EA_Pos) /*!< 0x0000000F */
+#define USB_EP6R_EA USB_EP6R_EA_Msk /*!< Endpoint Address */
+
+#define USB_EP6R_STAT_TX_Pos (4U)
+#define USB_EP6R_STAT_TX_Msk (0x3U << USB_EP6R_STAT_TX_Pos) /*!< 0x00000030 */
+#define USB_EP6R_STAT_TX USB_EP6R_STAT_TX_Msk /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */
+#define USB_EP6R_STAT_TX_0 (0x1U << USB_EP6R_STAT_TX_Pos) /*!< 0x00000010 */
+#define USB_EP6R_STAT_TX_1 (0x2U << USB_EP6R_STAT_TX_Pos) /*!< 0x00000020 */
+
+#define USB_EP6R_DTOG_TX_Pos (6U)
+#define USB_EP6R_DTOG_TX_Msk (0x1U << USB_EP6R_DTOG_TX_Pos) /*!< 0x00000040 */
+#define USB_EP6R_DTOG_TX USB_EP6R_DTOG_TX_Msk /*!< Data Toggle, for transmission transfers */
+#define USB_EP6R_CTR_TX_Pos (7U)
+#define USB_EP6R_CTR_TX_Msk (0x1U << USB_EP6R_CTR_TX_Pos) /*!< 0x00000080 */
+#define USB_EP6R_CTR_TX USB_EP6R_CTR_TX_Msk /*!< Correct Transfer for transmission */
+#define USB_EP6R_EP_KIND_Pos (8U)
+#define USB_EP6R_EP_KIND_Msk (0x1U << USB_EP6R_EP_KIND_Pos) /*!< 0x00000100 */
+#define USB_EP6R_EP_KIND USB_EP6R_EP_KIND_Msk /*!< Endpoint Kind */
+
+#define USB_EP6R_EP_TYPE_Pos (9U)
+#define USB_EP6R_EP_TYPE_Msk (0x3U << USB_EP6R_EP_TYPE_Pos) /*!< 0x00000600 */
+#define USB_EP6R_EP_TYPE USB_EP6R_EP_TYPE_Msk /*!< EP_TYPE[1:0] bits (Endpoint type) */
+#define USB_EP6R_EP_TYPE_0 (0x1U << USB_EP6R_EP_TYPE_Pos) /*!< 0x00000200 */
+#define USB_EP6R_EP_TYPE_1 (0x2U << USB_EP6R_EP_TYPE_Pos) /*!< 0x00000400 */
+
+#define USB_EP6R_SETUP_Pos (11U)
+#define USB_EP6R_SETUP_Msk (0x1U << USB_EP6R_SETUP_Pos) /*!< 0x00000800 */
+#define USB_EP6R_SETUP USB_EP6R_SETUP_Msk /*!< Setup transaction completed */
+
+#define USB_EP6R_STAT_RX_Pos (12U)
+#define USB_EP6R_STAT_RX_Msk (0x3U << USB_EP6R_STAT_RX_Pos) /*!< 0x00003000 */
+#define USB_EP6R_STAT_RX USB_EP6R_STAT_RX_Msk /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */
+#define USB_EP6R_STAT_RX_0 (0x1U << USB_EP6R_STAT_RX_Pos) /*!< 0x00001000 */
+#define USB_EP6R_STAT_RX_1 (0x2U << USB_EP6R_STAT_RX_Pos) /*!< 0x00002000 */
+
+#define USB_EP6R_DTOG_RX_Pos (14U)
+#define USB_EP6R_DTOG_RX_Msk (0x1U << USB_EP6R_DTOG_RX_Pos) /*!< 0x00004000 */
+#define USB_EP6R_DTOG_RX USB_EP6R_DTOG_RX_Msk /*!< Data Toggle, for reception transfers */
+#define USB_EP6R_CTR_RX_Pos (15U)
+#define USB_EP6R_CTR_RX_Msk (0x1U << USB_EP6R_CTR_RX_Pos) /*!< 0x00008000 */
+#define USB_EP6R_CTR_RX USB_EP6R_CTR_RX_Msk /*!< Correct Transfer for reception */
+
+/******************* Bit definition for USB_EP7R register *******************/
+#define USB_EP7R_EA_Pos (0U)
+#define USB_EP7R_EA_Msk (0xFU << USB_EP7R_EA_Pos) /*!< 0x0000000F */
+#define USB_EP7R_EA USB_EP7R_EA_Msk /*!< Endpoint Address */
+
+#define USB_EP7R_STAT_TX_Pos (4U)
+#define USB_EP7R_STAT_TX_Msk (0x3U << USB_EP7R_STAT_TX_Pos) /*!< 0x00000030 */
+#define USB_EP7R_STAT_TX USB_EP7R_STAT_TX_Msk /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */
+#define USB_EP7R_STAT_TX_0 (0x1U << USB_EP7R_STAT_TX_Pos) /*!< 0x00000010 */
+#define USB_EP7R_STAT_TX_1 (0x2U << USB_EP7R_STAT_TX_Pos) /*!< 0x00000020 */
+
+#define USB_EP7R_DTOG_TX_Pos (6U)
+#define USB_EP7R_DTOG_TX_Msk (0x1U << USB_EP7R_DTOG_TX_Pos) /*!< 0x00000040 */
+#define USB_EP7R_DTOG_TX USB_EP7R_DTOG_TX_Msk /*!< Data Toggle, for transmission transfers */
+#define USB_EP7R_CTR_TX_Pos (7U)
+#define USB_EP7R_CTR_TX_Msk (0x1U << USB_EP7R_CTR_TX_Pos) /*!< 0x00000080 */
+#define USB_EP7R_CTR_TX USB_EP7R_CTR_TX_Msk /*!< Correct Transfer for transmission */
+#define USB_EP7R_EP_KIND_Pos (8U)
+#define USB_EP7R_EP_KIND_Msk (0x1U << USB_EP7R_EP_KIND_Pos) /*!< 0x00000100 */
+#define USB_EP7R_EP_KIND USB_EP7R_EP_KIND_Msk /*!< Endpoint Kind */
+
+#define USB_EP7R_EP_TYPE_Pos (9U)
+#define USB_EP7R_EP_TYPE_Msk (0x3U << USB_EP7R_EP_TYPE_Pos) /*!< 0x00000600 */
+#define USB_EP7R_EP_TYPE USB_EP7R_EP_TYPE_Msk /*!< EP_TYPE[1:0] bits (Endpoint type) */
+#define USB_EP7R_EP_TYPE_0 (0x1U << USB_EP7R_EP_TYPE_Pos) /*!< 0x00000200 */
+#define USB_EP7R_EP_TYPE_1 (0x2U << USB_EP7R_EP_TYPE_Pos) /*!< 0x00000400 */
+
+#define USB_EP7R_SETUP_Pos (11U)
+#define USB_EP7R_SETUP_Msk (0x1U << USB_EP7R_SETUP_Pos) /*!< 0x00000800 */
+#define USB_EP7R_SETUP USB_EP7R_SETUP_Msk /*!< Setup transaction completed */
+
+#define USB_EP7R_STAT_RX_Pos (12U)
+#define USB_EP7R_STAT_RX_Msk (0x3U << USB_EP7R_STAT_RX_Pos) /*!< 0x00003000 */
+#define USB_EP7R_STAT_RX USB_EP7R_STAT_RX_Msk /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */
+#define USB_EP7R_STAT_RX_0 (0x1U << USB_EP7R_STAT_RX_Pos) /*!< 0x00001000 */
+#define USB_EP7R_STAT_RX_1 (0x2U << USB_EP7R_STAT_RX_Pos) /*!< 0x00002000 */
+
+#define USB_EP7R_DTOG_RX_Pos (14U)
+#define USB_EP7R_DTOG_RX_Msk (0x1U << USB_EP7R_DTOG_RX_Pos) /*!< 0x00004000 */
+#define USB_EP7R_DTOG_RX USB_EP7R_DTOG_RX_Msk /*!< Data Toggle, for reception transfers */
+#define USB_EP7R_CTR_RX_Pos (15U)
+#define USB_EP7R_CTR_RX_Msk (0x1U << USB_EP7R_CTR_RX_Pos) /*!< 0x00008000 */
+#define USB_EP7R_CTR_RX USB_EP7R_CTR_RX_Msk /*!< Correct Transfer for reception */
+
+/*!< Common registers */
+/******************* Bit definition for USB_CNTR register *******************/
+#define USB_CNTR_FRES_Pos (0U)
+#define USB_CNTR_FRES_Msk (0x1U << USB_CNTR_FRES_Pos) /*!< 0x00000001 */
+#define USB_CNTR_FRES USB_CNTR_FRES_Msk /*!< Force USB Reset */
+#define USB_CNTR_PDWN_Pos (1U)
+#define USB_CNTR_PDWN_Msk (0x1U << USB_CNTR_PDWN_Pos) /*!< 0x00000002 */
+#define USB_CNTR_PDWN USB_CNTR_PDWN_Msk /*!< Power down */
+#define USB_CNTR_LP_MODE_Pos (2U)
+#define USB_CNTR_LP_MODE_Msk (0x1U << USB_CNTR_LP_MODE_Pos) /*!< 0x00000004 */
+#define USB_CNTR_LP_MODE USB_CNTR_LP_MODE_Msk /*!< Low-power mode */
+#define USB_CNTR_FSUSP_Pos (3U)
+#define USB_CNTR_FSUSP_Msk (0x1U << USB_CNTR_FSUSP_Pos) /*!< 0x00000008 */
+#define USB_CNTR_FSUSP USB_CNTR_FSUSP_Msk /*!< Force suspend */
+#define USB_CNTR_RESUME_Pos (4U)
+#define USB_CNTR_RESUME_Msk (0x1U << USB_CNTR_RESUME_Pos) /*!< 0x00000010 */
+#define USB_CNTR_RESUME USB_CNTR_RESUME_Msk /*!< Resume request */
+#define USB_CNTR_ESOFM_Pos (8U)
+#define USB_CNTR_ESOFM_Msk (0x1U << USB_CNTR_ESOFM_Pos) /*!< 0x00000100 */
+#define USB_CNTR_ESOFM USB_CNTR_ESOFM_Msk /*!< Expected Start Of Frame Interrupt Mask */
+#define USB_CNTR_SOFM_Pos (9U)
+#define USB_CNTR_SOFM_Msk (0x1U << USB_CNTR_SOFM_Pos) /*!< 0x00000200 */
+#define USB_CNTR_SOFM USB_CNTR_SOFM_Msk /*!< Start Of Frame Interrupt Mask */
+#define USB_CNTR_RESETM_Pos (10U)
+#define USB_CNTR_RESETM_Msk (0x1U << USB_CNTR_RESETM_Pos) /*!< 0x00000400 */
+#define USB_CNTR_RESETM USB_CNTR_RESETM_Msk /*!< RESET Interrupt Mask */
+#define USB_CNTR_SUSPM_Pos (11U)
+#define USB_CNTR_SUSPM_Msk (0x1U << USB_CNTR_SUSPM_Pos) /*!< 0x00000800 */
+#define USB_CNTR_SUSPM USB_CNTR_SUSPM_Msk /*!< Suspend mode Interrupt Mask */
+#define USB_CNTR_WKUPM_Pos (12U)
+#define USB_CNTR_WKUPM_Msk (0x1U << USB_CNTR_WKUPM_Pos) /*!< 0x00001000 */
+#define USB_CNTR_WKUPM USB_CNTR_WKUPM_Msk /*!< Wakeup Interrupt Mask */
+#define USB_CNTR_ERRM_Pos (13U)
+#define USB_CNTR_ERRM_Msk (0x1U << USB_CNTR_ERRM_Pos) /*!< 0x00002000 */
+#define USB_CNTR_ERRM USB_CNTR_ERRM_Msk /*!< Error Interrupt Mask */
+#define USB_CNTR_PMAOVRM_Pos (14U)
+#define USB_CNTR_PMAOVRM_Msk (0x1U << USB_CNTR_PMAOVRM_Pos) /*!< 0x00004000 */
+#define USB_CNTR_PMAOVRM USB_CNTR_PMAOVRM_Msk /*!< Packet Memory Area Over / Underrun Interrupt Mask */
+#define USB_CNTR_CTRM_Pos (15U)
+#define USB_CNTR_CTRM_Msk (0x1U << USB_CNTR_CTRM_Pos) /*!< 0x00008000 */
+#define USB_CNTR_CTRM USB_CNTR_CTRM_Msk /*!< Correct Transfer Interrupt Mask */
+
+/******************* Bit definition for USB_ISTR register *******************/
+#define USB_ISTR_EP_ID_Pos (0U)
+#define USB_ISTR_EP_ID_Msk (0xFU << USB_ISTR_EP_ID_Pos) /*!< 0x0000000F */
+#define USB_ISTR_EP_ID USB_ISTR_EP_ID_Msk /*!< Endpoint Identifier */
+#define USB_ISTR_DIR_Pos (4U)
+#define USB_ISTR_DIR_Msk (0x1U << USB_ISTR_DIR_Pos) /*!< 0x00000010 */
+#define USB_ISTR_DIR USB_ISTR_DIR_Msk /*!< Direction of transaction */
+#define USB_ISTR_ESOF_Pos (8U)
+#define USB_ISTR_ESOF_Msk (0x1U << USB_ISTR_ESOF_Pos) /*!< 0x00000100 */
+#define USB_ISTR_ESOF USB_ISTR_ESOF_Msk /*!< Expected Start Of Frame */
+#define USB_ISTR_SOF_Pos (9U)
+#define USB_ISTR_SOF_Msk (0x1U << USB_ISTR_SOF_Pos) /*!< 0x00000200 */
+#define USB_ISTR_SOF USB_ISTR_SOF_Msk /*!< Start Of Frame */
+#define USB_ISTR_RESET_Pos (10U)
+#define USB_ISTR_RESET_Msk (0x1U << USB_ISTR_RESET_Pos) /*!< 0x00000400 */
+#define USB_ISTR_RESET USB_ISTR_RESET_Msk /*!< USB RESET request */
+#define USB_ISTR_SUSP_Pos (11U)
+#define USB_ISTR_SUSP_Msk (0x1U << USB_ISTR_SUSP_Pos) /*!< 0x00000800 */
+#define USB_ISTR_SUSP USB_ISTR_SUSP_Msk /*!< Suspend mode request */
+#define USB_ISTR_WKUP_Pos (12U)
+#define USB_ISTR_WKUP_Msk (0x1U << USB_ISTR_WKUP_Pos) /*!< 0x00001000 */
+#define USB_ISTR_WKUP USB_ISTR_WKUP_Msk /*!< Wake up */
+#define USB_ISTR_ERR_Pos (13U)
+#define USB_ISTR_ERR_Msk (0x1U << USB_ISTR_ERR_Pos) /*!< 0x00002000 */
+#define USB_ISTR_ERR USB_ISTR_ERR_Msk /*!< Error */
+#define USB_ISTR_PMAOVR_Pos (14U)
+#define USB_ISTR_PMAOVR_Msk (0x1U << USB_ISTR_PMAOVR_Pos) /*!< 0x00004000 */
+#define USB_ISTR_PMAOVR USB_ISTR_PMAOVR_Msk /*!< Packet Memory Area Over / Underrun */
+#define USB_ISTR_CTR_Pos (15U)
+#define USB_ISTR_CTR_Msk (0x1U << USB_ISTR_CTR_Pos) /*!< 0x00008000 */
+#define USB_ISTR_CTR USB_ISTR_CTR_Msk /*!< Correct Transfer */
+
+/******************* Bit definition for USB_FNR register ********************/
+#define USB_FNR_FN_Pos (0U)
+#define USB_FNR_FN_Msk (0x7FFU << USB_FNR_FN_Pos) /*!< 0x000007FF */
+#define USB_FNR_FN USB_FNR_FN_Msk /*!< Frame Number */
+#define USB_FNR_LSOF_Pos (11U)
+#define USB_FNR_LSOF_Msk (0x3U << USB_FNR_LSOF_Pos) /*!< 0x00001800 */
+#define USB_FNR_LSOF USB_FNR_LSOF_Msk /*!< Lost SOF */
+#define USB_FNR_LCK_Pos (13U)
+#define USB_FNR_LCK_Msk (0x1U << USB_FNR_LCK_Pos) /*!< 0x00002000 */
+#define USB_FNR_LCK USB_FNR_LCK_Msk /*!< Locked */
+#define USB_FNR_RXDM_Pos (14U)
+#define USB_FNR_RXDM_Msk (0x1U << USB_FNR_RXDM_Pos) /*!< 0x00004000 */
+#define USB_FNR_RXDM USB_FNR_RXDM_Msk /*!< Receive Data - Line Status */
+#define USB_FNR_RXDP_Pos (15U)
+#define USB_FNR_RXDP_Msk (0x1U << USB_FNR_RXDP_Pos) /*!< 0x00008000 */
+#define USB_FNR_RXDP USB_FNR_RXDP_Msk /*!< Receive Data + Line Status */
+
+/****************** Bit definition for USB_DADDR register *******************/
+#define USB_DADDR_ADD_Pos (0U)
+#define USB_DADDR_ADD_Msk (0x7FU << USB_DADDR_ADD_Pos) /*!< 0x0000007F */
+#define USB_DADDR_ADD USB_DADDR_ADD_Msk /*!< ADD[6:0] bits (Device Address) */
+#define USB_DADDR_ADD0_Pos (0U)
+#define USB_DADDR_ADD0_Msk (0x1U << USB_DADDR_ADD0_Pos) /*!< 0x00000001 */
+#define USB_DADDR_ADD0 USB_DADDR_ADD0_Msk /*!< Bit 0 */
+#define USB_DADDR_ADD1_Pos (1U)
+#define USB_DADDR_ADD1_Msk (0x1U << USB_DADDR_ADD1_Pos) /*!< 0x00000002 */
+#define USB_DADDR_ADD1 USB_DADDR_ADD1_Msk /*!< Bit 1 */
+#define USB_DADDR_ADD2_Pos (2U)
+#define USB_DADDR_ADD2_Msk (0x1U << USB_DADDR_ADD2_Pos) /*!< 0x00000004 */
+#define USB_DADDR_ADD2 USB_DADDR_ADD2_Msk /*!< Bit 2 */
+#define USB_DADDR_ADD3_Pos (3U)
+#define USB_DADDR_ADD3_Msk (0x1U << USB_DADDR_ADD3_Pos) /*!< 0x00000008 */
+#define USB_DADDR_ADD3 USB_DADDR_ADD3_Msk /*!< Bit 3 */
+#define USB_DADDR_ADD4_Pos (4U)
+#define USB_DADDR_ADD4_Msk (0x1U << USB_DADDR_ADD4_Pos) /*!< 0x00000010 */
+#define USB_DADDR_ADD4 USB_DADDR_ADD4_Msk /*!< Bit 4 */
+#define USB_DADDR_ADD5_Pos (5U)
+#define USB_DADDR_ADD5_Msk (0x1U << USB_DADDR_ADD5_Pos) /*!< 0x00000020 */
+#define USB_DADDR_ADD5 USB_DADDR_ADD5_Msk /*!< Bit 5 */
+#define USB_DADDR_ADD6_Pos (6U)
+#define USB_DADDR_ADD6_Msk (0x1U << USB_DADDR_ADD6_Pos) /*!< 0x00000040 */
+#define USB_DADDR_ADD6 USB_DADDR_ADD6_Msk /*!< Bit 6 */
+
+#define USB_DADDR_EF_Pos (7U)
+#define USB_DADDR_EF_Msk (0x1U << USB_DADDR_EF_Pos) /*!< 0x00000080 */
+#define USB_DADDR_EF USB_DADDR_EF_Msk /*!< Enable Function */
+
+/****************** Bit definition for USB_BTABLE register ******************/
+#define USB_BTABLE_BTABLE_Pos (3U)
+#define USB_BTABLE_BTABLE_Msk (0x1FFFU << USB_BTABLE_BTABLE_Pos) /*!< 0x0000FFF8 */
+#define USB_BTABLE_BTABLE USB_BTABLE_BTABLE_Msk /*!< Buffer Table */
+
+/*!< Buffer descriptor table */
+/***************** Bit definition for USB_ADDR0_TX register *****************/
+#define USB_ADDR0_TX_ADDR0_TX_Pos (1U)
+#define USB_ADDR0_TX_ADDR0_TX_Msk (0x7FFFU << USB_ADDR0_TX_ADDR0_TX_Pos) /*!< 0x0000FFFE */
+#define USB_ADDR0_TX_ADDR0_TX USB_ADDR0_TX_ADDR0_TX_Msk /*!< Transmission Buffer Address 0 */
+
+/***************** Bit definition for USB_ADDR1_TX register *****************/
+#define USB_ADDR1_TX_ADDR1_TX_Pos (1U)
+#define USB_ADDR1_TX_ADDR1_TX_Msk (0x7FFFU << USB_ADDR1_TX_ADDR1_TX_Pos) /*!< 0x0000FFFE */
+#define USB_ADDR1_TX_ADDR1_TX USB_ADDR1_TX_ADDR1_TX_Msk /*!< Transmission Buffer Address 1 */
+
+/***************** Bit definition for USB_ADDR2_TX register *****************/
+#define USB_ADDR2_TX_ADDR2_TX_Pos (1U)
+#define USB_ADDR2_TX_ADDR2_TX_Msk (0x7FFFU << USB_ADDR2_TX_ADDR2_TX_Pos) /*!< 0x0000FFFE */
+#define USB_ADDR2_TX_ADDR2_TX USB_ADDR2_TX_ADDR2_TX_Msk /*!< Transmission Buffer Address 2 */
+
+/***************** Bit definition for USB_ADDR3_TX register *****************/
+#define USB_ADDR3_TX_ADDR3_TX_Pos (1U)
+#define USB_ADDR3_TX_ADDR3_TX_Msk (0x7FFFU << USB_ADDR3_TX_ADDR3_TX_Pos) /*!< 0x0000FFFE */
+#define USB_ADDR3_TX_ADDR3_TX USB_ADDR3_TX_ADDR3_TX_Msk /*!< Transmission Buffer Address 3 */
+
+/***************** Bit definition for USB_ADDR4_TX register *****************/
+#define USB_ADDR4_TX_ADDR4_TX_Pos (1U)
+#define USB_ADDR4_TX_ADDR4_TX_Msk (0x7FFFU << USB_ADDR4_TX_ADDR4_TX_Pos) /*!< 0x0000FFFE */
+#define USB_ADDR4_TX_ADDR4_TX USB_ADDR4_TX_ADDR4_TX_Msk /*!< Transmission Buffer Address 4 */
+
+/***************** Bit definition for USB_ADDR5_TX register *****************/
+#define USB_ADDR5_TX_ADDR5_TX_Pos (1U)
+#define USB_ADDR5_TX_ADDR5_TX_Msk (0x7FFFU << USB_ADDR5_TX_ADDR5_TX_Pos) /*!< 0x0000FFFE */
+#define USB_ADDR5_TX_ADDR5_TX USB_ADDR5_TX_ADDR5_TX_Msk /*!< Transmission Buffer Address 5 */
+
+/***************** Bit definition for USB_ADDR6_TX register *****************/
+#define USB_ADDR6_TX_ADDR6_TX_Pos (1U)
+#define USB_ADDR6_TX_ADDR6_TX_Msk (0x7FFFU << USB_ADDR6_TX_ADDR6_TX_Pos) /*!< 0x0000FFFE */
+#define USB_ADDR6_TX_ADDR6_TX USB_ADDR6_TX_ADDR6_TX_Msk /*!< Transmission Buffer Address 6 */
+
+/***************** Bit definition for USB_ADDR7_TX register *****************/
+#define USB_ADDR7_TX_ADDR7_TX_Pos (1U)
+#define USB_ADDR7_TX_ADDR7_TX_Msk (0x7FFFU << USB_ADDR7_TX_ADDR7_TX_Pos) /*!< 0x0000FFFE */
+#define USB_ADDR7_TX_ADDR7_TX USB_ADDR7_TX_ADDR7_TX_Msk /*!< Transmission Buffer Address 7 */
+
+/*----------------------------------------------------------------------------*/
+
+/***************** Bit definition for USB_COUNT0_TX register ****************/
+#define USB_COUNT0_TX_COUNT0_TX_Pos (0U)
+#define USB_COUNT0_TX_COUNT0_TX_Msk (0x3FFU << USB_COUNT0_TX_COUNT0_TX_Pos) /*!< 0x000003FF */
+#define USB_COUNT0_TX_COUNT0_TX USB_COUNT0_TX_COUNT0_TX_Msk /*!< Transmission Byte Count 0 */
+
+/***************** Bit definition for USB_COUNT1_TX register ****************/
+#define USB_COUNT1_TX_COUNT1_TX_Pos (0U)
+#define USB_COUNT1_TX_COUNT1_TX_Msk (0x3FFU << USB_COUNT1_TX_COUNT1_TX_Pos) /*!< 0x000003FF */
+#define USB_COUNT1_TX_COUNT1_TX USB_COUNT1_TX_COUNT1_TX_Msk /*!< Transmission Byte Count 1 */
+
+/***************** Bit definition for USB_COUNT2_TX register ****************/
+#define USB_COUNT2_TX_COUNT2_TX_Pos (0U)
+#define USB_COUNT2_TX_COUNT2_TX_Msk (0x3FFU << USB_COUNT2_TX_COUNT2_TX_Pos) /*!< 0x000003FF */
+#define USB_COUNT2_TX_COUNT2_TX USB_COUNT2_TX_COUNT2_TX_Msk /*!< Transmission Byte Count 2 */
+
+/***************** Bit definition for USB_COUNT3_TX register ****************/
+#define USB_COUNT3_TX_COUNT3_TX_Pos (0U)
+#define USB_COUNT3_TX_COUNT3_TX_Msk (0x3FFU << USB_COUNT3_TX_COUNT3_TX_Pos) /*!< 0x000003FF */
+#define USB_COUNT3_TX_COUNT3_TX USB_COUNT3_TX_COUNT3_TX_Msk /*!< Transmission Byte Count 3 */
+
+/***************** Bit definition for USB_COUNT4_TX register ****************/
+#define USB_COUNT4_TX_COUNT4_TX_Pos (0U)
+#define USB_COUNT4_TX_COUNT4_TX_Msk (0x3FFU << USB_COUNT4_TX_COUNT4_TX_Pos) /*!< 0x000003FF */
+#define USB_COUNT4_TX_COUNT4_TX USB_COUNT4_TX_COUNT4_TX_Msk /*!< Transmission Byte Count 4 */
+
+/***************** Bit definition for USB_COUNT5_TX register ****************/
+#define USB_COUNT5_TX_COUNT5_TX_Pos (0U)
+#define USB_COUNT5_TX_COUNT5_TX_Msk (0x3FFU << USB_COUNT5_TX_COUNT5_TX_Pos) /*!< 0x000003FF */
+#define USB_COUNT5_TX_COUNT5_TX USB_COUNT5_TX_COUNT5_TX_Msk /*!< Transmission Byte Count 5 */
+
+/***************** Bit definition for USB_COUNT6_TX register ****************/
+#define USB_COUNT6_TX_COUNT6_TX_Pos (0U)
+#define USB_COUNT6_TX_COUNT6_TX_Msk (0x3FFU << USB_COUNT6_TX_COUNT6_TX_Pos) /*!< 0x000003FF */
+#define USB_COUNT6_TX_COUNT6_TX USB_COUNT6_TX_COUNT6_TX_Msk /*!< Transmission Byte Count 6 */
+
+/***************** Bit definition for USB_COUNT7_TX register ****************/
+#define USB_COUNT7_TX_COUNT7_TX_Pos (0U)
+#define USB_COUNT7_TX_COUNT7_TX_Msk (0x3FFU << USB_COUNT7_TX_COUNT7_TX_Pos) /*!< 0x000003FF */
+#define USB_COUNT7_TX_COUNT7_TX USB_COUNT7_TX_COUNT7_TX_Msk /*!< Transmission Byte Count 7 */
+
+/*----------------------------------------------------------------------------*/
+
+/**************** Bit definition for USB_COUNT0_TX_0 register ***************/
+#define USB_COUNT0_TX_0_COUNT0_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 0 (low) */
+
+/**************** Bit definition for USB_COUNT0_TX_1 register ***************/
+#define USB_COUNT0_TX_1_COUNT0_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 0 (high) */
+
+/**************** Bit definition for USB_COUNT1_TX_0 register ***************/
+#define USB_COUNT1_TX_0_COUNT1_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 1 (low) */
+
+/**************** Bit definition for USB_COUNT1_TX_1 register ***************/
+#define USB_COUNT1_TX_1_COUNT1_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 1 (high) */
+
+/**************** Bit definition for USB_COUNT2_TX_0 register ***************/
+#define USB_COUNT2_TX_0_COUNT2_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 2 (low) */
+
+/**************** Bit definition for USB_COUNT2_TX_1 register ***************/
+#define USB_COUNT2_TX_1_COUNT2_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 2 (high) */
+
+/**************** Bit definition for USB_COUNT3_TX_0 register ***************/
+#define USB_COUNT3_TX_0_COUNT3_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 3 (low) */
+
+/**************** Bit definition for USB_COUNT3_TX_1 register ***************/
+#define USB_COUNT3_TX_1_COUNT3_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 3 (high) */
+
+/**************** Bit definition for USB_COUNT4_TX_0 register ***************/
+#define USB_COUNT4_TX_0_COUNT4_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 4 (low) */
+
+/**************** Bit definition for USB_COUNT4_TX_1 register ***************/
+#define USB_COUNT4_TX_1_COUNT4_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 4 (high) */
+
+/**************** Bit definition for USB_COUNT5_TX_0 register ***************/
+#define USB_COUNT5_TX_0_COUNT5_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 5 (low) */
+
+/**************** Bit definition for USB_COUNT5_TX_1 register ***************/
+#define USB_COUNT5_TX_1_COUNT5_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 5 (high) */
+
+/**************** Bit definition for USB_COUNT6_TX_0 register ***************/
+#define USB_COUNT6_TX_0_COUNT6_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 6 (low) */
+
+/**************** Bit definition for USB_COUNT6_TX_1 register ***************/
+#define USB_COUNT6_TX_1_COUNT6_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 6 (high) */
+
+/**************** Bit definition for USB_COUNT7_TX_0 register ***************/
+#define USB_COUNT7_TX_0_COUNT7_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 7 (low) */
+
+/**************** Bit definition for USB_COUNT7_TX_1 register ***************/
+#define USB_COUNT7_TX_1_COUNT7_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 7 (high) */
+
+/*----------------------------------------------------------------------------*/
+
+/***************** Bit definition for USB_ADDR0_RX register *****************/
+#define USB_ADDR0_RX_ADDR0_RX_Pos (1U)
+#define USB_ADDR0_RX_ADDR0_RX_Msk (0x7FFFU << USB_ADDR0_RX_ADDR0_RX_Pos) /*!< 0x0000FFFE */
+#define USB_ADDR0_RX_ADDR0_RX USB_ADDR0_RX_ADDR0_RX_Msk /*!< Reception Buffer Address 0 */
+
+/***************** Bit definition for USB_ADDR1_RX register *****************/
+#define USB_ADDR1_RX_ADDR1_RX_Pos (1U)
+#define USB_ADDR1_RX_ADDR1_RX_Msk (0x7FFFU << USB_ADDR1_RX_ADDR1_RX_Pos) /*!< 0x0000FFFE */
+#define USB_ADDR1_RX_ADDR1_RX USB_ADDR1_RX_ADDR1_RX_Msk /*!< Reception Buffer Address 1 */
+
+/***************** Bit definition for USB_ADDR2_RX register *****************/
+#define USB_ADDR2_RX_ADDR2_RX_Pos (1U)
+#define USB_ADDR2_RX_ADDR2_RX_Msk (0x7FFFU << USB_ADDR2_RX_ADDR2_RX_Pos) /*!< 0x0000FFFE */
+#define USB_ADDR2_RX_ADDR2_RX USB_ADDR2_RX_ADDR2_RX_Msk /*!< Reception Buffer Address 2 */
+
+/***************** Bit definition for USB_ADDR3_RX register *****************/
+#define USB_ADDR3_RX_ADDR3_RX_Pos (1U)
+#define USB_ADDR3_RX_ADDR3_RX_Msk (0x7FFFU << USB_ADDR3_RX_ADDR3_RX_Pos) /*!< 0x0000FFFE */
+#define USB_ADDR3_RX_ADDR3_RX USB_ADDR3_RX_ADDR3_RX_Msk /*!< Reception Buffer Address 3 */
+
+/***************** Bit definition for USB_ADDR4_RX register *****************/
+#define USB_ADDR4_RX_ADDR4_RX_Pos (1U)
+#define USB_ADDR4_RX_ADDR4_RX_Msk (0x7FFFU << USB_ADDR4_RX_ADDR4_RX_Pos) /*!< 0x0000FFFE */
+#define USB_ADDR4_RX_ADDR4_RX USB_ADDR4_RX_ADDR4_RX_Msk /*!< Reception Buffer Address 4 */
+
+/***************** Bit definition for USB_ADDR5_RX register *****************/
+#define USB_ADDR5_RX_ADDR5_RX_Pos (1U)
+#define USB_ADDR5_RX_ADDR5_RX_Msk (0x7FFFU << USB_ADDR5_RX_ADDR5_RX_Pos) /*!< 0x0000FFFE */
+#define USB_ADDR5_RX_ADDR5_RX USB_ADDR5_RX_ADDR5_RX_Msk /*!< Reception Buffer Address 5 */
+
+/***************** Bit definition for USB_ADDR6_RX register *****************/
+#define USB_ADDR6_RX_ADDR6_RX_Pos (1U)
+#define USB_ADDR6_RX_ADDR6_RX_Msk (0x7FFFU << USB_ADDR6_RX_ADDR6_RX_Pos) /*!< 0x0000FFFE */
+#define USB_ADDR6_RX_ADDR6_RX USB_ADDR6_RX_ADDR6_RX_Msk /*!< Reception Buffer Address 6 */
+
+/***************** Bit definition for USB_ADDR7_RX register *****************/
+#define USB_ADDR7_RX_ADDR7_RX_Pos (1U)
+#define USB_ADDR7_RX_ADDR7_RX_Msk (0x7FFFU << USB_ADDR7_RX_ADDR7_RX_Pos) /*!< 0x0000FFFE */
+#define USB_ADDR7_RX_ADDR7_RX USB_ADDR7_RX_ADDR7_RX_Msk /*!< Reception Buffer Address 7 */
+
+/*----------------------------------------------------------------------------*/
+
+/***************** Bit definition for USB_COUNT0_RX register ****************/
+#define USB_COUNT0_RX_COUNT0_RX_Pos (0U)
+#define USB_COUNT0_RX_COUNT0_RX_Msk (0x3FFU << USB_COUNT0_RX_COUNT0_RX_Pos) /*!< 0x000003FF */
+#define USB_COUNT0_RX_COUNT0_RX USB_COUNT0_RX_COUNT0_RX_Msk /*!< Reception Byte Count */
+
+#define USB_COUNT0_RX_NUM_BLOCK_Pos (10U)
+#define USB_COUNT0_RX_NUM_BLOCK_Msk (0x1FU << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
+#define USB_COUNT0_RX_NUM_BLOCK USB_COUNT0_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
+#define USB_COUNT0_RX_NUM_BLOCK_0 (0x01U << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
+#define USB_COUNT0_RX_NUM_BLOCK_1 (0x02U << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
+#define USB_COUNT0_RX_NUM_BLOCK_2 (0x04U << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
+#define USB_COUNT0_RX_NUM_BLOCK_3 (0x08U << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
+#define USB_COUNT0_RX_NUM_BLOCK_4 (0x10U << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
+
+#define USB_COUNT0_RX_BLSIZE_Pos (15U)
+#define USB_COUNT0_RX_BLSIZE_Msk (0x1U << USB_COUNT0_RX_BLSIZE_Pos) /*!< 0x00008000 */
+#define USB_COUNT0_RX_BLSIZE USB_COUNT0_RX_BLSIZE_Msk /*!< BLock SIZE */
+
+/***************** Bit definition for USB_COUNT1_RX register ****************/
+#define USB_COUNT1_RX_COUNT1_RX_Pos (0U)
+#define USB_COUNT1_RX_COUNT1_RX_Msk (0x3FFU << USB_COUNT1_RX_COUNT1_RX_Pos) /*!< 0x000003FF */
+#define USB_COUNT1_RX_COUNT1_RX USB_COUNT1_RX_COUNT1_RX_Msk /*!< Reception Byte Count */
+
+#define USB_COUNT1_RX_NUM_BLOCK_Pos (10U)
+#define USB_COUNT1_RX_NUM_BLOCK_Msk (0x1FU << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
+#define USB_COUNT1_RX_NUM_BLOCK USB_COUNT1_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
+#define USB_COUNT1_RX_NUM_BLOCK_0 (0x01U << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
+#define USB_COUNT1_RX_NUM_BLOCK_1 (0x02U << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
+#define USB_COUNT1_RX_NUM_BLOCK_2 (0x04U << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
+#define USB_COUNT1_RX_NUM_BLOCK_3 (0x08U << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
+#define USB_COUNT1_RX_NUM_BLOCK_4 (0x10U << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
+
+#define USB_COUNT1_RX_BLSIZE_Pos (15U)
+#define USB_COUNT1_RX_BLSIZE_Msk (0x1U << USB_COUNT1_RX_BLSIZE_Pos) /*!< 0x00008000 */
+#define USB_COUNT1_RX_BLSIZE USB_COUNT1_RX_BLSIZE_Msk /*!< BLock SIZE */
+
+/***************** Bit definition for USB_COUNT2_RX register ****************/
+#define USB_COUNT2_RX_COUNT2_RX_Pos (0U)
+#define USB_COUNT2_RX_COUNT2_RX_Msk (0x3FFU << USB_COUNT2_RX_COUNT2_RX_Pos) /*!< 0x000003FF */
+#define USB_COUNT2_RX_COUNT2_RX USB_COUNT2_RX_COUNT2_RX_Msk /*!< Reception Byte Count */
+
+#define USB_COUNT2_RX_NUM_BLOCK_Pos (10U)
+#define USB_COUNT2_RX_NUM_BLOCK_Msk (0x1FU << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
+#define USB_COUNT2_RX_NUM_BLOCK USB_COUNT2_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
+#define USB_COUNT2_RX_NUM_BLOCK_0 (0x01U << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
+#define USB_COUNT2_RX_NUM_BLOCK_1 (0x02U << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
+#define USB_COUNT2_RX_NUM_BLOCK_2 (0x04U << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
+#define USB_COUNT2_RX_NUM_BLOCK_3 (0x08U << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
+#define USB_COUNT2_RX_NUM_BLOCK_4 (0x10U << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
+
+#define USB_COUNT2_RX_BLSIZE_Pos (15U)
+#define USB_COUNT2_RX_BLSIZE_Msk (0x1U << USB_COUNT2_RX_BLSIZE_Pos) /*!< 0x00008000 */
+#define USB_COUNT2_RX_BLSIZE USB_COUNT2_RX_BLSIZE_Msk /*!< BLock SIZE */
+
+/***************** Bit definition for USB_COUNT3_RX register ****************/
+#define USB_COUNT3_RX_COUNT3_RX_Pos (0U)
+#define USB_COUNT3_RX_COUNT3_RX_Msk (0x3FFU << USB_COUNT3_RX_COUNT3_RX_Pos) /*!< 0x000003FF */
+#define USB_COUNT3_RX_COUNT3_RX USB_COUNT3_RX_COUNT3_RX_Msk /*!< Reception Byte Count */
+
+#define USB_COUNT3_RX_NUM_BLOCK_Pos (10U)
+#define USB_COUNT3_RX_NUM_BLOCK_Msk (0x1FU << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
+#define USB_COUNT3_RX_NUM_BLOCK USB_COUNT3_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
+#define USB_COUNT3_RX_NUM_BLOCK_0 (0x01U << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
+#define USB_COUNT3_RX_NUM_BLOCK_1 (0x02U << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
+#define USB_COUNT3_RX_NUM_BLOCK_2 (0x04U << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
+#define USB_COUNT3_RX_NUM_BLOCK_3 (0x08U << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
+#define USB_COUNT3_RX_NUM_BLOCK_4 (0x10U << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
+
+#define USB_COUNT3_RX_BLSIZE_Pos (15U)
+#define USB_COUNT3_RX_BLSIZE_Msk (0x1U << USB_COUNT3_RX_BLSIZE_Pos) /*!< 0x00008000 */
+#define USB_COUNT3_RX_BLSIZE USB_COUNT3_RX_BLSIZE_Msk /*!< BLock SIZE */
+
+/***************** Bit definition for USB_COUNT4_RX register ****************/
+#define USB_COUNT4_RX_COUNT4_RX_Pos (0U)
+#define USB_COUNT4_RX_COUNT4_RX_Msk (0x3FFU << USB_COUNT4_RX_COUNT4_RX_Pos) /*!< 0x000003FF */
+#define USB_COUNT4_RX_COUNT4_RX USB_COUNT4_RX_COUNT4_RX_Msk /*!< Reception Byte Count */
+
+#define USB_COUNT4_RX_NUM_BLOCK_Pos (10U)
+#define USB_COUNT4_RX_NUM_BLOCK_Msk (0x1FU << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
+#define USB_COUNT4_RX_NUM_BLOCK USB_COUNT4_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
+#define USB_COUNT4_RX_NUM_BLOCK_0 (0x01U << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
+#define USB_COUNT4_RX_NUM_BLOCK_1 (0x02U << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
+#define USB_COUNT4_RX_NUM_BLOCK_2 (0x04U << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
+#define USB_COUNT4_RX_NUM_BLOCK_3 (0x08U << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
+#define USB_COUNT4_RX_NUM_BLOCK_4 (0x10U << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
+
+#define USB_COUNT4_RX_BLSIZE_Pos (15U)
+#define USB_COUNT4_RX_BLSIZE_Msk (0x1U << USB_COUNT4_RX_BLSIZE_Pos) /*!< 0x00008000 */
+#define USB_COUNT4_RX_BLSIZE USB_COUNT4_RX_BLSIZE_Msk /*!< BLock SIZE */
+
+/***************** Bit definition for USB_COUNT5_RX register ****************/
+#define USB_COUNT5_RX_COUNT5_RX_Pos (0U)
+#define USB_COUNT5_RX_COUNT5_RX_Msk (0x3FFU << USB_COUNT5_RX_COUNT5_RX_Pos) /*!< 0x000003FF */
+#define USB_COUNT5_RX_COUNT5_RX USB_COUNT5_RX_COUNT5_RX_Msk /*!< Reception Byte Count */
+
+#define USB_COUNT5_RX_NUM_BLOCK_Pos (10U)
+#define USB_COUNT5_RX_NUM_BLOCK_Msk (0x1FU << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
+#define USB_COUNT5_RX_NUM_BLOCK USB_COUNT5_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
+#define USB_COUNT5_RX_NUM_BLOCK_0 (0x01U << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
+#define USB_COUNT5_RX_NUM_BLOCK_1 (0x02U << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
+#define USB_COUNT5_RX_NUM_BLOCK_2 (0x04U << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
+#define USB_COUNT5_RX_NUM_BLOCK_3 (0x08U << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
+#define USB_COUNT5_RX_NUM_BLOCK_4 (0x10U << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
+
+#define USB_COUNT5_RX_BLSIZE_Pos (15U)
+#define USB_COUNT5_RX_BLSIZE_Msk (0x1U << USB_COUNT5_RX_BLSIZE_Pos) /*!< 0x00008000 */
+#define USB_COUNT5_RX_BLSIZE USB_COUNT5_RX_BLSIZE_Msk /*!< BLock SIZE */
+
+/***************** Bit definition for USB_COUNT6_RX register ****************/
+#define USB_COUNT6_RX_COUNT6_RX_Pos (0U)
+#define USB_COUNT6_RX_COUNT6_RX_Msk (0x3FFU << USB_COUNT6_RX_COUNT6_RX_Pos) /*!< 0x000003FF */
+#define USB_COUNT6_RX_COUNT6_RX USB_COUNT6_RX_COUNT6_RX_Msk /*!< Reception Byte Count */
+
+#define USB_COUNT6_RX_NUM_BLOCK_Pos (10U)
+#define USB_COUNT6_RX_NUM_BLOCK_Msk (0x1FU << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
+#define USB_COUNT6_RX_NUM_BLOCK USB_COUNT6_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
+#define USB_COUNT6_RX_NUM_BLOCK_0 (0x01U << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
+#define USB_COUNT6_RX_NUM_BLOCK_1 (0x02U << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
+#define USB_COUNT6_RX_NUM_BLOCK_2 (0x04U << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
+#define USB_COUNT6_RX_NUM_BLOCK_3 (0x08U << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
+#define USB_COUNT6_RX_NUM_BLOCK_4 (0x10U << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
+
+#define USB_COUNT6_RX_BLSIZE_Pos (15U)
+#define USB_COUNT6_RX_BLSIZE_Msk (0x1U << USB_COUNT6_RX_BLSIZE_Pos) /*!< 0x00008000 */
+#define USB_COUNT6_RX_BLSIZE USB_COUNT6_RX_BLSIZE_Msk /*!< BLock SIZE */
+
+/***************** Bit definition for USB_COUNT7_RX register ****************/
+#define USB_COUNT7_RX_COUNT7_RX_Pos (0U)
+#define USB_COUNT7_RX_COUNT7_RX_Msk (0x3FFU << USB_COUNT7_RX_COUNT7_RX_Pos) /*!< 0x000003FF */
+#define USB_COUNT7_RX_COUNT7_RX USB_COUNT7_RX_COUNT7_RX_Msk /*!< Reception Byte Count */
+
+#define USB_COUNT7_RX_NUM_BLOCK_Pos (10U)
+#define USB_COUNT7_RX_NUM_BLOCK_Msk (0x1FU << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
+#define USB_COUNT7_RX_NUM_BLOCK USB_COUNT7_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
+#define USB_COUNT7_RX_NUM_BLOCK_0 (0x01U << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
+#define USB_COUNT7_RX_NUM_BLOCK_1 (0x02U << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
+#define USB_COUNT7_RX_NUM_BLOCK_2 (0x04U << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
+#define USB_COUNT7_RX_NUM_BLOCK_3 (0x08U << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
+#define USB_COUNT7_RX_NUM_BLOCK_4 (0x10U << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
+
+#define USB_COUNT7_RX_BLSIZE_Pos (15U)
+#define USB_COUNT7_RX_BLSIZE_Msk (0x1U << USB_COUNT7_RX_BLSIZE_Pos) /*!< 0x00008000 */
+#define USB_COUNT7_RX_BLSIZE USB_COUNT7_RX_BLSIZE_Msk /*!< BLock SIZE */
+
+/*----------------------------------------------------------------------------*/
+
+/**************** Bit definition for USB_COUNT0_RX_0 register ***************/
+#define USB_COUNT0_RX_0_COUNT0_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */
+
+#define USB_COUNT0_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
+#define USB_COUNT0_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */
+#define USB_COUNT0_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */
+#define USB_COUNT0_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */
+#define USB_COUNT0_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */
+#define USB_COUNT0_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */
+
+#define USB_COUNT0_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */
+
+/**************** Bit definition for USB_COUNT0_RX_1 register ***************/
+#define USB_COUNT0_RX_1_COUNT0_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */
+
+#define USB_COUNT0_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
+#define USB_COUNT0_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 1 */
+#define USB_COUNT0_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */
+#define USB_COUNT0_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */
+#define USB_COUNT0_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */
+#define USB_COUNT0_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */
+
+#define USB_COUNT0_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */
+
+/**************** Bit definition for USB_COUNT1_RX_0 register ***************/
+#define USB_COUNT1_RX_0_COUNT1_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */
+
+#define USB_COUNT1_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
+#define USB_COUNT1_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */
+#define USB_COUNT1_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */
+#define USB_COUNT1_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */
+#define USB_COUNT1_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */
+#define USB_COUNT1_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */
+
+#define USB_COUNT1_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */
+
+/**************** Bit definition for USB_COUNT1_RX_1 register ***************/
+#define USB_COUNT1_RX_1_COUNT1_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */
+
+#define USB_COUNT1_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
+#define USB_COUNT1_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */
+#define USB_COUNT1_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */
+#define USB_COUNT1_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */
+#define USB_COUNT1_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */
+#define USB_COUNT1_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */
+
+#define USB_COUNT1_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */
+
+/**************** Bit definition for USB_COUNT2_RX_0 register ***************/
+#define USB_COUNT2_RX_0_COUNT2_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */
+
+#define USB_COUNT2_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
+#define USB_COUNT2_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */
+#define USB_COUNT2_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */
+#define USB_COUNT2_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */
+#define USB_COUNT2_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */
+#define USB_COUNT2_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */
+
+#define USB_COUNT2_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */
+
+/**************** Bit definition for USB_COUNT2_RX_1 register ***************/
+#define USB_COUNT2_RX_1_COUNT2_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */
+
+#define USB_COUNT2_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
+#define USB_COUNT2_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */
+#define USB_COUNT2_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */
+#define USB_COUNT2_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */
+#define USB_COUNT2_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */
+#define USB_COUNT2_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */
+
+#define USB_COUNT2_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */
+
+/**************** Bit definition for USB_COUNT3_RX_0 register ***************/
+#define USB_COUNT3_RX_0_COUNT3_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */
+
+#define USB_COUNT3_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
+#define USB_COUNT3_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */
+#define USB_COUNT3_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */
+#define USB_COUNT3_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */
+#define USB_COUNT3_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */
+#define USB_COUNT3_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */
+
+#define USB_COUNT3_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */
+
+/**************** Bit definition for USB_COUNT3_RX_1 register ***************/
+#define USB_COUNT3_RX_1_COUNT3_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */
+
+#define USB_COUNT3_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
+#define USB_COUNT3_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */
+#define USB_COUNT3_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */
+#define USB_COUNT3_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */
+#define USB_COUNT3_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */
+#define USB_COUNT3_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */
+
+#define USB_COUNT3_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */
+
+/**************** Bit definition for USB_COUNT4_RX_0 register ***************/
+#define USB_COUNT4_RX_0_COUNT4_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */
+
+#define USB_COUNT4_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
+#define USB_COUNT4_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */
+#define USB_COUNT4_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */
+#define USB_COUNT4_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */
+#define USB_COUNT4_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */
+#define USB_COUNT4_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */
+
+#define USB_COUNT4_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */
+
+/**************** Bit definition for USB_COUNT4_RX_1 register ***************/
+#define USB_COUNT4_RX_1_COUNT4_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */
+
+#define USB_COUNT4_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
+#define USB_COUNT4_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */
+#define USB_COUNT4_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */
+#define USB_COUNT4_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */
+#define USB_COUNT4_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */
+#define USB_COUNT4_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */
+
+#define USB_COUNT4_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */
+
+/**************** Bit definition for USB_COUNT5_RX_0 register ***************/
+#define USB_COUNT5_RX_0_COUNT5_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */
+
+#define USB_COUNT5_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
+#define USB_COUNT5_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */
+#define USB_COUNT5_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */
+#define USB_COUNT5_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */
+#define USB_COUNT5_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */
+#define USB_COUNT5_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */
+
+#define USB_COUNT5_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */
+
+/**************** Bit definition for USB_COUNT5_RX_1 register ***************/
+#define USB_COUNT5_RX_1_COUNT5_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */
+
+#define USB_COUNT5_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
+#define USB_COUNT5_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */
+#define USB_COUNT5_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */
+#define USB_COUNT5_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */
+#define USB_COUNT5_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */
+#define USB_COUNT5_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */
+
+#define USB_COUNT5_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */
+
+/*************** Bit definition for USB_COUNT6_RX_0 register ***************/
+#define USB_COUNT6_RX_0_COUNT6_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */
+
+#define USB_COUNT6_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
+#define USB_COUNT6_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */
+#define USB_COUNT6_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */
+#define USB_COUNT6_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */
+#define USB_COUNT6_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */
+#define USB_COUNT6_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */
+
+#define USB_COUNT6_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */
+
+/**************** Bit definition for USB_COUNT6_RX_1 register ***************/
+#define USB_COUNT6_RX_1_COUNT6_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */
+
+#define USB_COUNT6_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
+#define USB_COUNT6_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */
+#define USB_COUNT6_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */
+#define USB_COUNT6_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */
+#define USB_COUNT6_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */
+#define USB_COUNT6_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */
+
+#define USB_COUNT6_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */
+
+/*************** Bit definition for USB_COUNT7_RX_0 register ****************/
+#define USB_COUNT7_RX_0_COUNT7_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */
+
+#define USB_COUNT7_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
+#define USB_COUNT7_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */
+#define USB_COUNT7_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */
+#define USB_COUNT7_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */
+#define USB_COUNT7_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */
+#define USB_COUNT7_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */
+
+#define USB_COUNT7_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */
+
+/*************** Bit definition for USB_COUNT7_RX_1 register ****************/
+#define USB_COUNT7_RX_1_COUNT7_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */
+
+#define USB_COUNT7_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
+#define USB_COUNT7_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */
+#define USB_COUNT7_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */
+#define USB_COUNT7_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */
+#define USB_COUNT7_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */
+#define USB_COUNT7_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */
+
+#define USB_COUNT7_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */
+
+/******************************************************************************/
+/* */
+/* Controller Area Network */
+/* */
+/******************************************************************************/
+
+/*!< CAN control and status registers */
+/******************* Bit definition for CAN_MCR register ********************/
+#define CAN_MCR_INRQ_Pos (0U)
+#define CAN_MCR_INRQ_Msk (0x1U << CAN_MCR_INRQ_Pos) /*!< 0x00000001 */
+#define CAN_MCR_INRQ CAN_MCR_INRQ_Msk /*!< Initialization Request */
+#define CAN_MCR_SLEEP_Pos (1U)
+#define CAN_MCR_SLEEP_Msk (0x1U << CAN_MCR_SLEEP_Pos) /*!< 0x00000002 */
+#define CAN_MCR_SLEEP CAN_MCR_SLEEP_Msk /*!< Sleep Mode Request */
+#define CAN_MCR_TXFP_Pos (2U)
+#define CAN_MCR_TXFP_Msk (0x1U << CAN_MCR_TXFP_Pos) /*!< 0x00000004 */
+#define CAN_MCR_TXFP CAN_MCR_TXFP_Msk /*!< Transmit FIFO Priority */
+#define CAN_MCR_RFLM_Pos (3U)
+#define CAN_MCR_RFLM_Msk (0x1U << CAN_MCR_RFLM_Pos) /*!< 0x00000008 */
+#define CAN_MCR_RFLM CAN_MCR_RFLM_Msk /*!< Receive FIFO Locked Mode */
+#define CAN_MCR_NART_Pos (4U)
+#define CAN_MCR_NART_Msk (0x1U << CAN_MCR_NART_Pos) /*!< 0x00000010 */
+#define CAN_MCR_NART CAN_MCR_NART_Msk /*!< No Automatic Retransmission */
+#define CAN_MCR_AWUM_Pos (5U)
+#define CAN_MCR_AWUM_Msk (0x1U << CAN_MCR_AWUM_Pos) /*!< 0x00000020 */
+#define CAN_MCR_AWUM CAN_MCR_AWUM_Msk /*!< Automatic Wakeup Mode */
+#define CAN_MCR_ABOM_Pos (6U)
+#define CAN_MCR_ABOM_Msk (0x1U << CAN_MCR_ABOM_Pos) /*!< 0x00000040 */
+#define CAN_MCR_ABOM CAN_MCR_ABOM_Msk /*!< Automatic Bus-Off Management */
+#define CAN_MCR_TTCM_Pos (7U)
+#define CAN_MCR_TTCM_Msk (0x1U << CAN_MCR_TTCM_Pos) /*!< 0x00000080 */
+#define CAN_MCR_TTCM CAN_MCR_TTCM_Msk /*!< Time Triggered Communication Mode */
+#define CAN_MCR_RESET_Pos (15U)
+#define CAN_MCR_RESET_Msk (0x1U << CAN_MCR_RESET_Pos) /*!< 0x00008000 */
+#define CAN_MCR_RESET CAN_MCR_RESET_Msk /*!< CAN software master reset */
+#define CAN_MCR_DBF_Pos (16U)
+#define CAN_MCR_DBF_Msk (0x1U << CAN_MCR_DBF_Pos) /*!< 0x00010000 */
+#define CAN_MCR_DBF CAN_MCR_DBF_Msk /*!< CAN Debug freeze */
+
+/******************* Bit definition for CAN_MSR register ********************/
+#define CAN_MSR_INAK_Pos (0U)
+#define CAN_MSR_INAK_Msk (0x1U << CAN_MSR_INAK_Pos) /*!< 0x00000001 */
+#define CAN_MSR_INAK CAN_MSR_INAK_Msk /*!< Initialization Acknowledge */
+#define CAN_MSR_SLAK_Pos (1U)
+#define CAN_MSR_SLAK_Msk (0x1U << CAN_MSR_SLAK_Pos) /*!< 0x00000002 */
+#define CAN_MSR_SLAK CAN_MSR_SLAK_Msk /*!< Sleep Acknowledge */
+#define CAN_MSR_ERRI_Pos (2U)
+#define CAN_MSR_ERRI_Msk (0x1U << CAN_MSR_ERRI_Pos) /*!< 0x00000004 */
+#define CAN_MSR_ERRI CAN_MSR_ERRI_Msk /*!< Error Interrupt */
+#define CAN_MSR_WKUI_Pos (3U)
+#define CAN_MSR_WKUI_Msk (0x1U << CAN_MSR_WKUI_Pos) /*!< 0x00000008 */
+#define CAN_MSR_WKUI CAN_MSR_WKUI_Msk /*!< Wakeup Interrupt */
+#define CAN_MSR_SLAKI_Pos (4U)
+#define CAN_MSR_SLAKI_Msk (0x1U << CAN_MSR_SLAKI_Pos) /*!< 0x00000010 */
+#define CAN_MSR_SLAKI CAN_MSR_SLAKI_Msk /*!< Sleep Acknowledge Interrupt */
+#define CAN_MSR_TXM_Pos (8U)
+#define CAN_MSR_TXM_Msk (0x1U << CAN_MSR_TXM_Pos) /*!< 0x00000100 */
+#define CAN_MSR_TXM CAN_MSR_TXM_Msk /*!< Transmit Mode */
+#define CAN_MSR_RXM_Pos (9U)
+#define CAN_MSR_RXM_Msk (0x1U << CAN_MSR_RXM_Pos) /*!< 0x00000200 */
+#define CAN_MSR_RXM CAN_MSR_RXM_Msk /*!< Receive Mode */
+#define CAN_MSR_SAMP_Pos (10U)
+#define CAN_MSR_SAMP_Msk (0x1U << CAN_MSR_SAMP_Pos) /*!< 0x00000400 */
+#define CAN_MSR_SAMP CAN_MSR_SAMP_Msk /*!< Last Sample Point */
+#define CAN_MSR_RX_Pos (11U)
+#define CAN_MSR_RX_Msk (0x1U << CAN_MSR_RX_Pos) /*!< 0x00000800 */
+#define CAN_MSR_RX CAN_MSR_RX_Msk /*!< CAN Rx Signal */
+
+/******************* Bit definition for CAN_TSR register ********************/
+#define CAN_TSR_RQCP0_Pos (0U)
+#define CAN_TSR_RQCP0_Msk (0x1U << CAN_TSR_RQCP0_Pos) /*!< 0x00000001 */
+#define CAN_TSR_RQCP0 CAN_TSR_RQCP0_Msk /*!< Request Completed Mailbox0 */
+#define CAN_TSR_TXOK0_Pos (1U)
+#define CAN_TSR_TXOK0_Msk (0x1U << CAN_TSR_TXOK0_Pos) /*!< 0x00000002 */
+#define CAN_TSR_TXOK0 CAN_TSR_TXOK0_Msk /*!< Transmission OK of Mailbox0 */
+#define CAN_TSR_ALST0_Pos (2U)
+#define CAN_TSR_ALST0_Msk (0x1U << CAN_TSR_ALST0_Pos) /*!< 0x00000004 */
+#define CAN_TSR_ALST0 CAN_TSR_ALST0_Msk /*!< Arbitration Lost for Mailbox0 */
+#define CAN_TSR_TERR0_Pos (3U)
+#define CAN_TSR_TERR0_Msk (0x1U << CAN_TSR_TERR0_Pos) /*!< 0x00000008 */
+#define CAN_TSR_TERR0 CAN_TSR_TERR0_Msk /*!< Transmission Error of Mailbox0 */
+#define CAN_TSR_ABRQ0_Pos (7U)
+#define CAN_TSR_ABRQ0_Msk (0x1U << CAN_TSR_ABRQ0_Pos) /*!< 0x00000080 */
+#define CAN_TSR_ABRQ0 CAN_TSR_ABRQ0_Msk /*!< Abort Request for Mailbox0 */
+#define CAN_TSR_RQCP1_Pos (8U)
+#define CAN_TSR_RQCP1_Msk (0x1U << CAN_TSR_RQCP1_Pos) /*!< 0x00000100 */
+#define CAN_TSR_RQCP1 CAN_TSR_RQCP1_Msk /*!< Request Completed Mailbox1 */
+#define CAN_TSR_TXOK1_Pos (9U)
+#define CAN_TSR_TXOK1_Msk (0x1U << CAN_TSR_TXOK1_Pos) /*!< 0x00000200 */
+#define CAN_TSR_TXOK1 CAN_TSR_TXOK1_Msk /*!< Transmission OK of Mailbox1 */
+#define CAN_TSR_ALST1_Pos (10U)
+#define CAN_TSR_ALST1_Msk (0x1U << CAN_TSR_ALST1_Pos) /*!< 0x00000400 */
+#define CAN_TSR_ALST1 CAN_TSR_ALST1_Msk /*!< Arbitration Lost for Mailbox1 */
+#define CAN_TSR_TERR1_Pos (11U)
+#define CAN_TSR_TERR1_Msk (0x1U << CAN_TSR_TERR1_Pos) /*!< 0x00000800 */
+#define CAN_TSR_TERR1 CAN_TSR_TERR1_Msk /*!< Transmission Error of Mailbox1 */
+#define CAN_TSR_ABRQ1_Pos (15U)
+#define CAN_TSR_ABRQ1_Msk (0x1U << CAN_TSR_ABRQ1_Pos) /*!< 0x00008000 */
+#define CAN_TSR_ABRQ1 CAN_TSR_ABRQ1_Msk /*!< Abort Request for Mailbox 1 */
+#define CAN_TSR_RQCP2_Pos (16U)
+#define CAN_TSR_RQCP2_Msk (0x1U << CAN_TSR_RQCP2_Pos) /*!< 0x00010000 */
+#define CAN_TSR_RQCP2 CAN_TSR_RQCP2_Msk /*!< Request Completed Mailbox2 */
+#define CAN_TSR_TXOK2_Pos (17U)
+#define CAN_TSR_TXOK2_Msk (0x1U << CAN_TSR_TXOK2_Pos) /*!< 0x00020000 */
+#define CAN_TSR_TXOK2 CAN_TSR_TXOK2_Msk /*!< Transmission OK of Mailbox 2 */
+#define CAN_TSR_ALST2_Pos (18U)
+#define CAN_TSR_ALST2_Msk (0x1U << CAN_TSR_ALST2_Pos) /*!< 0x00040000 */
+#define CAN_TSR_ALST2 CAN_TSR_ALST2_Msk /*!< Arbitration Lost for mailbox 2 */
+#define CAN_TSR_TERR2_Pos (19U)
+#define CAN_TSR_TERR2_Msk (0x1U << CAN_TSR_TERR2_Pos) /*!< 0x00080000 */
+#define CAN_TSR_TERR2 CAN_TSR_TERR2_Msk /*!< Transmission Error of Mailbox 2 */
+#define CAN_TSR_ABRQ2_Pos (23U)
+#define CAN_TSR_ABRQ2_Msk (0x1U << CAN_TSR_ABRQ2_Pos) /*!< 0x00800000 */
+#define CAN_TSR_ABRQ2 CAN_TSR_ABRQ2_Msk /*!< Abort Request for Mailbox 2 */
+#define CAN_TSR_CODE_Pos (24U)
+#define CAN_TSR_CODE_Msk (0x3U << CAN_TSR_CODE_Pos) /*!< 0x03000000 */
+#define CAN_TSR_CODE CAN_TSR_CODE_Msk /*!< Mailbox Code */
+
+#define CAN_TSR_TME_Pos (26U)
+#define CAN_TSR_TME_Msk (0x7U << CAN_TSR_TME_Pos) /*!< 0x1C000000 */
+#define CAN_TSR_TME CAN_TSR_TME_Msk /*!< TME[2:0] bits */
+#define CAN_TSR_TME0_Pos (26U)
+#define CAN_TSR_TME0_Msk (0x1U << CAN_TSR_TME0_Pos) /*!< 0x04000000 */
+#define CAN_TSR_TME0 CAN_TSR_TME0_Msk /*!< Transmit Mailbox 0 Empty */
+#define CAN_TSR_TME1_Pos (27U)
+#define CAN_TSR_TME1_Msk (0x1U << CAN_TSR_TME1_Pos) /*!< 0x08000000 */
+#define CAN_TSR_TME1 CAN_TSR_TME1_Msk /*!< Transmit Mailbox 1 Empty */
+#define CAN_TSR_TME2_Pos (28U)
+#define CAN_TSR_TME2_Msk (0x1U << CAN_TSR_TME2_Pos) /*!< 0x10000000 */
+#define CAN_TSR_TME2 CAN_TSR_TME2_Msk /*!< Transmit Mailbox 2 Empty */
+
+#define CAN_TSR_LOW_Pos (29U)
+#define CAN_TSR_LOW_Msk (0x7U << CAN_TSR_LOW_Pos) /*!< 0xE0000000 */
+#define CAN_TSR_LOW CAN_TSR_LOW_Msk /*!< LOW[2:0] bits */
+#define CAN_TSR_LOW0_Pos (29U)
+#define CAN_TSR_LOW0_Msk (0x1U << CAN_TSR_LOW0_Pos) /*!< 0x20000000 */
+#define CAN_TSR_LOW0 CAN_TSR_LOW0_Msk /*!< Lowest Priority Flag for Mailbox 0 */
+#define CAN_TSR_LOW1_Pos (30U)
+#define CAN_TSR_LOW1_Msk (0x1U << CAN_TSR_LOW1_Pos) /*!< 0x40000000 */
+#define CAN_TSR_LOW1 CAN_TSR_LOW1_Msk /*!< Lowest Priority Flag for Mailbox 1 */
+#define CAN_TSR_LOW2_Pos (31U)
+#define CAN_TSR_LOW2_Msk (0x1U << CAN_TSR_LOW2_Pos) /*!< 0x80000000 */
+#define CAN_TSR_LOW2 CAN_TSR_LOW2_Msk /*!< Lowest Priority Flag for Mailbox 2 */
+
+/******************* Bit definition for CAN_RF0R register *******************/
+#define CAN_RF0R_FMP0_Pos (0U)
+#define CAN_RF0R_FMP0_Msk (0x3U << CAN_RF0R_FMP0_Pos) /*!< 0x00000003 */
+#define CAN_RF0R_FMP0 CAN_RF0R_FMP0_Msk /*!< FIFO 0 Message Pending */
+#define CAN_RF0R_FULL0_Pos (3U)
+#define CAN_RF0R_FULL0_Msk (0x1U << CAN_RF0R_FULL0_Pos) /*!< 0x00000008 */
+#define CAN_RF0R_FULL0 CAN_RF0R_FULL0_Msk /*!< FIFO 0 Full */
+#define CAN_RF0R_FOVR0_Pos (4U)
+#define CAN_RF0R_FOVR0_Msk (0x1U << CAN_RF0R_FOVR0_Pos) /*!< 0x00000010 */
+#define CAN_RF0R_FOVR0 CAN_RF0R_FOVR0_Msk /*!< FIFO 0 Overrun */
+#define CAN_RF0R_RFOM0_Pos (5U)
+#define CAN_RF0R_RFOM0_Msk (0x1U << CAN_RF0R_RFOM0_Pos) /*!< 0x00000020 */
+#define CAN_RF0R_RFOM0 CAN_RF0R_RFOM0_Msk /*!< Release FIFO 0 Output Mailbox */
+
+/******************* Bit definition for CAN_RF1R register *******************/
+#define CAN_RF1R_FMP1_Pos (0U)
+#define CAN_RF1R_FMP1_Msk (0x3U << CAN_RF1R_FMP1_Pos) /*!< 0x00000003 */
+#define CAN_RF1R_FMP1 CAN_RF1R_FMP1_Msk /*!< FIFO 1 Message Pending */
+#define CAN_RF1R_FULL1_Pos (3U)
+#define CAN_RF1R_FULL1_Msk (0x1U << CAN_RF1R_FULL1_Pos) /*!< 0x00000008 */
+#define CAN_RF1R_FULL1 CAN_RF1R_FULL1_Msk /*!< FIFO 1 Full */
+#define CAN_RF1R_FOVR1_Pos (4U)
+#define CAN_RF1R_FOVR1_Msk (0x1U << CAN_RF1R_FOVR1_Pos) /*!< 0x00000010 */
+#define CAN_RF1R_FOVR1 CAN_RF1R_FOVR1_Msk /*!< FIFO 1 Overrun */
+#define CAN_RF1R_RFOM1_Pos (5U)
+#define CAN_RF1R_RFOM1_Msk (0x1U << CAN_RF1R_RFOM1_Pos) /*!< 0x00000020 */
+#define CAN_RF1R_RFOM1 CAN_RF1R_RFOM1_Msk /*!< Release FIFO 1 Output Mailbox */
+
+/******************** Bit definition for CAN_IER register *******************/
+#define CAN_IER_TMEIE_Pos (0U)
+#define CAN_IER_TMEIE_Msk (0x1U << CAN_IER_TMEIE_Pos) /*!< 0x00000001 */
+#define CAN_IER_TMEIE CAN_IER_TMEIE_Msk /*!< Transmit Mailbox Empty Interrupt Enable */
+#define CAN_IER_FMPIE0_Pos (1U)
+#define CAN_IER_FMPIE0_Msk (0x1U << CAN_IER_FMPIE0_Pos) /*!< 0x00000002 */
+#define CAN_IER_FMPIE0 CAN_IER_FMPIE0_Msk /*!< FIFO Message Pending Interrupt Enable */
+#define CAN_IER_FFIE0_Pos (2U)
+#define CAN_IER_FFIE0_Msk (0x1U << CAN_IER_FFIE0_Pos) /*!< 0x00000004 */
+#define CAN_IER_FFIE0 CAN_IER_FFIE0_Msk /*!< FIFO Full Interrupt Enable */
+#define CAN_IER_FOVIE0_Pos (3U)
+#define CAN_IER_FOVIE0_Msk (0x1U << CAN_IER_FOVIE0_Pos) /*!< 0x00000008 */
+#define CAN_IER_FOVIE0 CAN_IER_FOVIE0_Msk /*!< FIFO Overrun Interrupt Enable */
+#define CAN_IER_FMPIE1_Pos (4U)
+#define CAN_IER_FMPIE1_Msk (0x1U << CAN_IER_FMPIE1_Pos) /*!< 0x00000010 */
+#define CAN_IER_FMPIE1 CAN_IER_FMPIE1_Msk /*!< FIFO Message Pending Interrupt Enable */
+#define CAN_IER_FFIE1_Pos (5U)
+#define CAN_IER_FFIE1_Msk (0x1U << CAN_IER_FFIE1_Pos) /*!< 0x00000020 */
+#define CAN_IER_FFIE1 CAN_IER_FFIE1_Msk /*!< FIFO Full Interrupt Enable */
+#define CAN_IER_FOVIE1_Pos (6U)
+#define CAN_IER_FOVIE1_Msk (0x1U << CAN_IER_FOVIE1_Pos) /*!< 0x00000040 */
+#define CAN_IER_FOVIE1 CAN_IER_FOVIE1_Msk /*!< FIFO Overrun Interrupt Enable */
+#define CAN_IER_EWGIE_Pos (8U)
+#define CAN_IER_EWGIE_Msk (0x1U << CAN_IER_EWGIE_Pos) /*!< 0x00000100 */
+#define CAN_IER_EWGIE CAN_IER_EWGIE_Msk /*!< Error Warning Interrupt Enable */
+#define CAN_IER_EPVIE_Pos (9U)
+#define CAN_IER_EPVIE_Msk (0x1U << CAN_IER_EPVIE_Pos) /*!< 0x00000200 */
+#define CAN_IER_EPVIE CAN_IER_EPVIE_Msk /*!< Error Passive Interrupt Enable */
+#define CAN_IER_BOFIE_Pos (10U)
+#define CAN_IER_BOFIE_Msk (0x1U << CAN_IER_BOFIE_Pos) /*!< 0x00000400 */
+#define CAN_IER_BOFIE CAN_IER_BOFIE_Msk /*!< Bus-Off Interrupt Enable */
+#define CAN_IER_LECIE_Pos (11U)
+#define CAN_IER_LECIE_Msk (0x1U << CAN_IER_LECIE_Pos) /*!< 0x00000800 */
+#define CAN_IER_LECIE CAN_IER_LECIE_Msk /*!< Last Error Code Interrupt Enable */
+#define CAN_IER_ERRIE_Pos (15U)
+#define CAN_IER_ERRIE_Msk (0x1U << CAN_IER_ERRIE_Pos) /*!< 0x00008000 */
+#define CAN_IER_ERRIE CAN_IER_ERRIE_Msk /*!< Error Interrupt Enable */
+#define CAN_IER_WKUIE_Pos (16U)
+#define CAN_IER_WKUIE_Msk (0x1U << CAN_IER_WKUIE_Pos) /*!< 0x00010000 */
+#define CAN_IER_WKUIE CAN_IER_WKUIE_Msk /*!< Wakeup Interrupt Enable */
+#define CAN_IER_SLKIE_Pos (17U)
+#define CAN_IER_SLKIE_Msk (0x1U << CAN_IER_SLKIE_Pos) /*!< 0x00020000 */
+#define CAN_IER_SLKIE CAN_IER_SLKIE_Msk /*!< Sleep Interrupt Enable */
+
+/******************** Bit definition for CAN_ESR register *******************/
+#define CAN_ESR_EWGF_Pos (0U)
+#define CAN_ESR_EWGF_Msk (0x1U << CAN_ESR_EWGF_Pos) /*!< 0x00000001 */
+#define CAN_ESR_EWGF CAN_ESR_EWGF_Msk /*!< Error Warning Flag */
+#define CAN_ESR_EPVF_Pos (1U)
+#define CAN_ESR_EPVF_Msk (0x1U << CAN_ESR_EPVF_Pos) /*!< 0x00000002 */
+#define CAN_ESR_EPVF CAN_ESR_EPVF_Msk /*!< Error Passive Flag */
+#define CAN_ESR_BOFF_Pos (2U)
+#define CAN_ESR_BOFF_Msk (0x1U << CAN_ESR_BOFF_Pos) /*!< 0x00000004 */
+#define CAN_ESR_BOFF CAN_ESR_BOFF_Msk /*!< Bus-Off Flag */
+
+#define CAN_ESR_LEC_Pos (4U)
+#define CAN_ESR_LEC_Msk (0x7U << CAN_ESR_LEC_Pos) /*!< 0x00000070 */
+#define CAN_ESR_LEC CAN_ESR_LEC_Msk /*!< LEC[2:0] bits (Last Error Code) */
+#define CAN_ESR_LEC_0 (0x1U << CAN_ESR_LEC_Pos) /*!< 0x00000010 */
+#define CAN_ESR_LEC_1 (0x2U << CAN_ESR_LEC_Pos) /*!< 0x00000020 */
+#define CAN_ESR_LEC_2 (0x4U << CAN_ESR_LEC_Pos) /*!< 0x00000040 */
+
+#define CAN_ESR_TEC_Pos (16U)
+#define CAN_ESR_TEC_Msk (0xFFU << CAN_ESR_TEC_Pos) /*!< 0x00FF0000 */
+#define CAN_ESR_TEC CAN_ESR_TEC_Msk /*!< Least significant byte of the 9-bit Transmit Error Counter */
+#define CAN_ESR_REC_Pos (24U)
+#define CAN_ESR_REC_Msk (0xFFU << CAN_ESR_REC_Pos) /*!< 0xFF000000 */
+#define CAN_ESR_REC CAN_ESR_REC_Msk /*!< Receive Error Counter */
+
+/******************* Bit definition for CAN_BTR register ********************/
+#define CAN_BTR_BRP_Pos (0U)
+#define CAN_BTR_BRP_Msk (0x3FFU << CAN_BTR_BRP_Pos) /*!< 0x000003FF */
+#define CAN_BTR_BRP CAN_BTR_BRP_Msk /*!<Baud Rate Prescaler */
+#define CAN_BTR_TS1_Pos (16U)
+#define CAN_BTR_TS1_Msk (0xFU << CAN_BTR_TS1_Pos) /*!< 0x000F0000 */
+#define CAN_BTR_TS1 CAN_BTR_TS1_Msk /*!<Time Segment 1 */
+#define CAN_BTR_TS1_0 (0x1U << CAN_BTR_TS1_Pos) /*!< 0x00010000 */
+#define CAN_BTR_TS1_1 (0x2U << CAN_BTR_TS1_Pos) /*!< 0x00020000 */
+#define CAN_BTR_TS1_2 (0x4U << CAN_BTR_TS1_Pos) /*!< 0x00040000 */
+#define CAN_BTR_TS1_3 (0x8U << CAN_BTR_TS1_Pos) /*!< 0x00080000 */
+#define CAN_BTR_TS2_Pos (20U)
+#define CAN_BTR_TS2_Msk (0x7U << CAN_BTR_TS2_Pos) /*!< 0x00700000 */
+#define CAN_BTR_TS2 CAN_BTR_TS2_Msk /*!<Time Segment 2 */
+#define CAN_BTR_TS2_0 (0x1U << CAN_BTR_TS2_Pos) /*!< 0x00100000 */
+#define CAN_BTR_TS2_1 (0x2U << CAN_BTR_TS2_Pos) /*!< 0x00200000 */
+#define CAN_BTR_TS2_2 (0x4U << CAN_BTR_TS2_Pos) /*!< 0x00400000 */
+#define CAN_BTR_SJW_Pos (24U)
+#define CAN_BTR_SJW_Msk (0x3U << CAN_BTR_SJW_Pos) /*!< 0x03000000 */
+#define CAN_BTR_SJW CAN_BTR_SJW_Msk /*!<Resynchronization Jump Width */
+#define CAN_BTR_SJW_0 (0x1U << CAN_BTR_SJW_Pos) /*!< 0x01000000 */
+#define CAN_BTR_SJW_1 (0x2U << CAN_BTR_SJW_Pos) /*!< 0x02000000 */
+#define CAN_BTR_LBKM_Pos (30U)
+#define CAN_BTR_LBKM_Msk (0x1U << CAN_BTR_LBKM_Pos) /*!< 0x40000000 */
+#define CAN_BTR_LBKM CAN_BTR_LBKM_Msk /*!<Loop Back Mode (Debug) */
+#define CAN_BTR_SILM_Pos (31U)
+#define CAN_BTR_SILM_Msk (0x1U << CAN_BTR_SILM_Pos) /*!< 0x80000000 */
+#define CAN_BTR_SILM CAN_BTR_SILM_Msk /*!<Silent Mode */
+
+/*!< Mailbox registers */
+/****************** Bit definition for CAN_TI0R register ********************/
+#define CAN_TI0R_TXRQ_Pos (0U)
+#define CAN_TI0R_TXRQ_Msk (0x1U << CAN_TI0R_TXRQ_Pos) /*!< 0x00000001 */
+#define CAN_TI0R_TXRQ CAN_TI0R_TXRQ_Msk /*!< Transmit Mailbox Request */
+#define CAN_TI0R_RTR_Pos (1U)
+#define CAN_TI0R_RTR_Msk (0x1U << CAN_TI0R_RTR_Pos) /*!< 0x00000002 */
+#define CAN_TI0R_RTR CAN_TI0R_RTR_Msk /*!< Remote Transmission Request */
+#define CAN_TI0R_IDE_Pos (2U)
+#define CAN_TI0R_IDE_Msk (0x1U << CAN_TI0R_IDE_Pos) /*!< 0x00000004 */
+#define CAN_TI0R_IDE CAN_TI0R_IDE_Msk /*!< Identifier Extension */
+#define CAN_TI0R_EXID_Pos (3U)
+#define CAN_TI0R_EXID_Msk (0x3FFFFU << CAN_TI0R_EXID_Pos) /*!< 0x001FFFF8 */
+#define CAN_TI0R_EXID CAN_TI0R_EXID_Msk /*!< Extended Identifier */
+#define CAN_TI0R_STID_Pos (21U)
+#define CAN_TI0R_STID_Msk (0x7FFU << CAN_TI0R_STID_Pos) /*!< 0xFFE00000 */
+#define CAN_TI0R_STID CAN_TI0R_STID_Msk /*!< Standard Identifier or Extended Identifier */
+
+/****************** Bit definition for CAN_TDT0R register *******************/
+#define CAN_TDT0R_DLC_Pos (0U)
+#define CAN_TDT0R_DLC_Msk (0xFU << CAN_TDT0R_DLC_Pos) /*!< 0x0000000F */
+#define CAN_TDT0R_DLC CAN_TDT0R_DLC_Msk /*!< Data Length Code */
+#define CAN_TDT0R_TGT_Pos (8U)
+#define CAN_TDT0R_TGT_Msk (0x1U << CAN_TDT0R_TGT_Pos) /*!< 0x00000100 */
+#define CAN_TDT0R_TGT CAN_TDT0R_TGT_Msk /*!< Transmit Global Time */
+#define CAN_TDT0R_TIME_Pos (16U)
+#define CAN_TDT0R_TIME_Msk (0xFFFFU << CAN_TDT0R_TIME_Pos) /*!< 0xFFFF0000 */
+#define CAN_TDT0R_TIME CAN_TDT0R_TIME_Msk /*!< Message Time Stamp */
+
+/****************** Bit definition for CAN_TDL0R register *******************/
+#define CAN_TDL0R_DATA0_Pos (0U)
+#define CAN_TDL0R_DATA0_Msk (0xFFU << CAN_TDL0R_DATA0_Pos) /*!< 0x000000FF */
+#define CAN_TDL0R_DATA0 CAN_TDL0R_DATA0_Msk /*!< Data byte 0 */
+#define CAN_TDL0R_DATA1_Pos (8U)
+#define CAN_TDL0R_DATA1_Msk (0xFFU << CAN_TDL0R_DATA1_Pos) /*!< 0x0000FF00 */
+#define CAN_TDL0R_DATA1 CAN_TDL0R_DATA1_Msk /*!< Data byte 1 */
+#define CAN_TDL0R_DATA2_Pos (16U)
+#define CAN_TDL0R_DATA2_Msk (0xFFU << CAN_TDL0R_DATA2_Pos) /*!< 0x00FF0000 */
+#define CAN_TDL0R_DATA2 CAN_TDL0R_DATA2_Msk /*!< Data byte 2 */
+#define CAN_TDL0R_DATA3_Pos (24U)
+#define CAN_TDL0R_DATA3_Msk (0xFFU << CAN_TDL0R_DATA3_Pos) /*!< 0xFF000000 */
+#define CAN_TDL0R_DATA3 CAN_TDL0R_DATA3_Msk /*!< Data byte 3 */
+
+/****************** Bit definition for CAN_TDH0R register *******************/
+#define CAN_TDH0R_DATA4_Pos (0U)
+#define CAN_TDH0R_DATA4_Msk (0xFFU << CAN_TDH0R_DATA4_Pos) /*!< 0x000000FF */
+#define CAN_TDH0R_DATA4 CAN_TDH0R_DATA4_Msk /*!< Data byte 4 */
+#define CAN_TDH0R_DATA5_Pos (8U)
+#define CAN_TDH0R_DATA5_Msk (0xFFU << CAN_TDH0R_DATA5_Pos) /*!< 0x0000FF00 */
+#define CAN_TDH0R_DATA5 CAN_TDH0R_DATA5_Msk /*!< Data byte 5 */
+#define CAN_TDH0R_DATA6_Pos (16U)
+#define CAN_TDH0R_DATA6_Msk (0xFFU << CAN_TDH0R_DATA6_Pos) /*!< 0x00FF0000 */
+#define CAN_TDH0R_DATA6 CAN_TDH0R_DATA6_Msk /*!< Data byte 6 */
+#define CAN_TDH0R_DATA7_Pos (24U)
+#define CAN_TDH0R_DATA7_Msk (0xFFU << CAN_TDH0R_DATA7_Pos) /*!< 0xFF000000 */
+#define CAN_TDH0R_DATA7 CAN_TDH0R_DATA7_Msk /*!< Data byte 7 */
+
+/******************* Bit definition for CAN_TI1R register *******************/
+#define CAN_TI1R_TXRQ_Pos (0U)
+#define CAN_TI1R_TXRQ_Msk (0x1U << CAN_TI1R_TXRQ_Pos) /*!< 0x00000001 */
+#define CAN_TI1R_TXRQ CAN_TI1R_TXRQ_Msk /*!< Transmit Mailbox Request */
+#define CAN_TI1R_RTR_Pos (1U)
+#define CAN_TI1R_RTR_Msk (0x1U << CAN_TI1R_RTR_Pos) /*!< 0x00000002 */
+#define CAN_TI1R_RTR CAN_TI1R_RTR_Msk /*!< Remote Transmission Request */
+#define CAN_TI1R_IDE_Pos (2U)
+#define CAN_TI1R_IDE_Msk (0x1U << CAN_TI1R_IDE_Pos) /*!< 0x00000004 */
+#define CAN_TI1R_IDE CAN_TI1R_IDE_Msk /*!< Identifier Extension */
+#define CAN_TI1R_EXID_Pos (3U)
+#define CAN_TI1R_EXID_Msk (0x3FFFFU << CAN_TI1R_EXID_Pos) /*!< 0x001FFFF8 */
+#define CAN_TI1R_EXID CAN_TI1R_EXID_Msk /*!< Extended Identifier */
+#define CAN_TI1R_STID_Pos (21U)
+#define CAN_TI1R_STID_Msk (0x7FFU << CAN_TI1R_STID_Pos) /*!< 0xFFE00000 */
+#define CAN_TI1R_STID CAN_TI1R_STID_Msk /*!< Standard Identifier or Extended Identifier */
+
+/******************* Bit definition for CAN_TDT1R register ******************/
+#define CAN_TDT1R_DLC_Pos (0U)
+#define CAN_TDT1R_DLC_Msk (0xFU << CAN_TDT1R_DLC_Pos) /*!< 0x0000000F */
+#define CAN_TDT1R_DLC CAN_TDT1R_DLC_Msk /*!< Data Length Code */
+#define CAN_TDT1R_TGT_Pos (8U)
+#define CAN_TDT1R_TGT_Msk (0x1U << CAN_TDT1R_TGT_Pos) /*!< 0x00000100 */
+#define CAN_TDT1R_TGT CAN_TDT1R_TGT_Msk /*!< Transmit Global Time */
+#define CAN_TDT1R_TIME_Pos (16U)
+#define CAN_TDT1R_TIME_Msk (0xFFFFU << CAN_TDT1R_TIME_Pos) /*!< 0xFFFF0000 */
+#define CAN_TDT1R_TIME CAN_TDT1R_TIME_Msk /*!< Message Time Stamp */
+
+/******************* Bit definition for CAN_TDL1R register ******************/
+#define CAN_TDL1R_DATA0_Pos (0U)
+#define CAN_TDL1R_DATA0_Msk (0xFFU << CAN_TDL1R_DATA0_Pos) /*!< 0x000000FF */
+#define CAN_TDL1R_DATA0 CAN_TDL1R_DATA0_Msk /*!< Data byte 0 */
+#define CAN_TDL1R_DATA1_Pos (8U)
+#define CAN_TDL1R_DATA1_Msk (0xFFU << CAN_TDL1R_DATA1_Pos) /*!< 0x0000FF00 */
+#define CAN_TDL1R_DATA1 CAN_TDL1R_DATA1_Msk /*!< Data byte 1 */
+#define CAN_TDL1R_DATA2_Pos (16U)
+#define CAN_TDL1R_DATA2_Msk (0xFFU << CAN_TDL1R_DATA2_Pos) /*!< 0x00FF0000 */
+#define CAN_TDL1R_DATA2 CAN_TDL1R_DATA2_Msk /*!< Data byte 2 */
+#define CAN_TDL1R_DATA3_Pos (24U)
+#define CAN_TDL1R_DATA3_Msk (0xFFU << CAN_TDL1R_DATA3_Pos) /*!< 0xFF000000 */
+#define CAN_TDL1R_DATA3 CAN_TDL1R_DATA3_Msk /*!< Data byte 3 */
+
+/******************* Bit definition for CAN_TDH1R register ******************/
+#define CAN_TDH1R_DATA4_Pos (0U)
+#define CAN_TDH1R_DATA4_Msk (0xFFU << CAN_TDH1R_DATA4_Pos) /*!< 0x000000FF */
+#define CAN_TDH1R_DATA4 CAN_TDH1R_DATA4_Msk /*!< Data byte 4 */
+#define CAN_TDH1R_DATA5_Pos (8U)
+#define CAN_TDH1R_DATA5_Msk (0xFFU << CAN_TDH1R_DATA5_Pos) /*!< 0x0000FF00 */
+#define CAN_TDH1R_DATA5 CAN_TDH1R_DATA5_Msk /*!< Data byte 5 */
+#define CAN_TDH1R_DATA6_Pos (16U)
+#define CAN_TDH1R_DATA6_Msk (0xFFU << CAN_TDH1R_DATA6_Pos) /*!< 0x00FF0000 */
+#define CAN_TDH1R_DATA6 CAN_TDH1R_DATA6_Msk /*!< Data byte 6 */
+#define CAN_TDH1R_DATA7_Pos (24U)
+#define CAN_TDH1R_DATA7_Msk (0xFFU << CAN_TDH1R_DATA7_Pos) /*!< 0xFF000000 */
+#define CAN_TDH1R_DATA7 CAN_TDH1R_DATA7_Msk /*!< Data byte 7 */
+
+/******************* Bit definition for CAN_TI2R register *******************/
+#define CAN_TI2R_TXRQ_Pos (0U)
+#define CAN_TI2R_TXRQ_Msk (0x1U << CAN_TI2R_TXRQ_Pos) /*!< 0x00000001 */
+#define CAN_TI2R_TXRQ CAN_TI2R_TXRQ_Msk /*!< Transmit Mailbox Request */
+#define CAN_TI2R_RTR_Pos (1U)
+#define CAN_TI2R_RTR_Msk (0x1U << CAN_TI2R_RTR_Pos) /*!< 0x00000002 */
+#define CAN_TI2R_RTR CAN_TI2R_RTR_Msk /*!< Remote Transmission Request */
+#define CAN_TI2R_IDE_Pos (2U)
+#define CAN_TI2R_IDE_Msk (0x1U << CAN_TI2R_IDE_Pos) /*!< 0x00000004 */
+#define CAN_TI2R_IDE CAN_TI2R_IDE_Msk /*!< Identifier Extension */
+#define CAN_TI2R_EXID_Pos (3U)
+#define CAN_TI2R_EXID_Msk (0x3FFFFU << CAN_TI2R_EXID_Pos) /*!< 0x001FFFF8 */
+#define CAN_TI2R_EXID CAN_TI2R_EXID_Msk /*!< Extended identifier */
+#define CAN_TI2R_STID_Pos (21U)
+#define CAN_TI2R_STID_Msk (0x7FFU << CAN_TI2R_STID_Pos) /*!< 0xFFE00000 */
+#define CAN_TI2R_STID CAN_TI2R_STID_Msk /*!< Standard Identifier or Extended Identifier */
+
+/******************* Bit definition for CAN_TDT2R register ******************/
+#define CAN_TDT2R_DLC_Pos (0U)
+#define CAN_TDT2R_DLC_Msk (0xFU << CAN_TDT2R_DLC_Pos) /*!< 0x0000000F */
+#define CAN_TDT2R_DLC CAN_TDT2R_DLC_Msk /*!< Data Length Code */
+#define CAN_TDT2R_TGT_Pos (8U)
+#define CAN_TDT2R_TGT_Msk (0x1U << CAN_TDT2R_TGT_Pos) /*!< 0x00000100 */
+#define CAN_TDT2R_TGT CAN_TDT2R_TGT_Msk /*!< Transmit Global Time */
+#define CAN_TDT2R_TIME_Pos (16U)
+#define CAN_TDT2R_TIME_Msk (0xFFFFU << CAN_TDT2R_TIME_Pos) /*!< 0xFFFF0000 */
+#define CAN_TDT2R_TIME CAN_TDT2R_TIME_Msk /*!< Message Time Stamp */
+
+/******************* Bit definition for CAN_TDL2R register ******************/
+#define CAN_TDL2R_DATA0_Pos (0U)
+#define CAN_TDL2R_DATA0_Msk (0xFFU << CAN_TDL2R_DATA0_Pos) /*!< 0x000000FF */
+#define CAN_TDL2R_DATA0 CAN_TDL2R_DATA0_Msk /*!< Data byte 0 */
+#define CAN_TDL2R_DATA1_Pos (8U)
+#define CAN_TDL2R_DATA1_Msk (0xFFU << CAN_TDL2R_DATA1_Pos) /*!< 0x0000FF00 */
+#define CAN_TDL2R_DATA1 CAN_TDL2R_DATA1_Msk /*!< Data byte 1 */
+#define CAN_TDL2R_DATA2_Pos (16U)
+#define CAN_TDL2R_DATA2_Msk (0xFFU << CAN_TDL2R_DATA2_Pos) /*!< 0x00FF0000 */
+#define CAN_TDL2R_DATA2 CAN_TDL2R_DATA2_Msk /*!< Data byte 2 */
+#define CAN_TDL2R_DATA3_Pos (24U)
+#define CAN_TDL2R_DATA3_Msk (0xFFU << CAN_TDL2R_DATA3_Pos) /*!< 0xFF000000 */
+#define CAN_TDL2R_DATA3 CAN_TDL2R_DATA3_Msk /*!< Data byte 3 */
+
+/******************* Bit definition for CAN_TDH2R register ******************/
+#define CAN_TDH2R_DATA4_Pos (0U)
+#define CAN_TDH2R_DATA4_Msk (0xFFU << CAN_TDH2R_DATA4_Pos) /*!< 0x000000FF */
+#define CAN_TDH2R_DATA4 CAN_TDH2R_DATA4_Msk /*!< Data byte 4 */
+#define CAN_TDH2R_DATA5_Pos (8U)
+#define CAN_TDH2R_DATA5_Msk (0xFFU << CAN_TDH2R_DATA5_Pos) /*!< 0x0000FF00 */
+#define CAN_TDH2R_DATA5 CAN_TDH2R_DATA5_Msk /*!< Data byte 5 */
+#define CAN_TDH2R_DATA6_Pos (16U)
+#define CAN_TDH2R_DATA6_Msk (0xFFU << CAN_TDH2R_DATA6_Pos) /*!< 0x00FF0000 */
+#define CAN_TDH2R_DATA6 CAN_TDH2R_DATA6_Msk /*!< Data byte 6 */
+#define CAN_TDH2R_DATA7_Pos (24U)
+#define CAN_TDH2R_DATA7_Msk (0xFFU << CAN_TDH2R_DATA7_Pos) /*!< 0xFF000000 */
+#define CAN_TDH2R_DATA7 CAN_TDH2R_DATA7_Msk /*!< Data byte 7 */
+
+/******************* Bit definition for CAN_RI0R register *******************/
+#define CAN_RI0R_RTR_Pos (1U)
+#define CAN_RI0R_RTR_Msk (0x1U << CAN_RI0R_RTR_Pos) /*!< 0x00000002 */
+#define CAN_RI0R_RTR CAN_RI0R_RTR_Msk /*!< Remote Transmission Request */
+#define CAN_RI0R_IDE_Pos (2U)
+#define CAN_RI0R_IDE_Msk (0x1U << CAN_RI0R_IDE_Pos) /*!< 0x00000004 */
+#define CAN_RI0R_IDE CAN_RI0R_IDE_Msk /*!< Identifier Extension */
+#define CAN_RI0R_EXID_Pos (3U)
+#define CAN_RI0R_EXID_Msk (0x3FFFFU << CAN_RI0R_EXID_Pos) /*!< 0x001FFFF8 */
+#define CAN_RI0R_EXID CAN_RI0R_EXID_Msk /*!< Extended Identifier */
+#define CAN_RI0R_STID_Pos (21U)
+#define CAN_RI0R_STID_Msk (0x7FFU << CAN_RI0R_STID_Pos) /*!< 0xFFE00000 */
+#define CAN_RI0R_STID CAN_RI0R_STID_Msk /*!< Standard Identifier or Extended Identifier */
+
+/******************* Bit definition for CAN_RDT0R register ******************/
+#define CAN_RDT0R_DLC_Pos (0U)
+#define CAN_RDT0R_DLC_Msk (0xFU << CAN_RDT0R_DLC_Pos) /*!< 0x0000000F */
+#define CAN_RDT0R_DLC CAN_RDT0R_DLC_Msk /*!< Data Length Code */
+#define CAN_RDT0R_FMI_Pos (8U)
+#define CAN_RDT0R_FMI_Msk (0xFFU << CAN_RDT0R_FMI_Pos) /*!< 0x0000FF00 */
+#define CAN_RDT0R_FMI CAN_RDT0R_FMI_Msk /*!< Filter Match Index */
+#define CAN_RDT0R_TIME_Pos (16U)
+#define CAN_RDT0R_TIME_Msk (0xFFFFU << CAN_RDT0R_TIME_Pos) /*!< 0xFFFF0000 */
+#define CAN_RDT0R_TIME CAN_RDT0R_TIME_Msk /*!< Message Time Stamp */
+
+/******************* Bit definition for CAN_RDL0R register ******************/
+#define CAN_RDL0R_DATA0_Pos (0U)
+#define CAN_RDL0R_DATA0_Msk (0xFFU << CAN_RDL0R_DATA0_Pos) /*!< 0x000000FF */
+#define CAN_RDL0R_DATA0 CAN_RDL0R_DATA0_Msk /*!< Data byte 0 */
+#define CAN_RDL0R_DATA1_Pos (8U)
+#define CAN_RDL0R_DATA1_Msk (0xFFU << CAN_RDL0R_DATA1_Pos) /*!< 0x0000FF00 */
+#define CAN_RDL0R_DATA1 CAN_RDL0R_DATA1_Msk /*!< Data byte 1 */
+#define CAN_RDL0R_DATA2_Pos (16U)
+#define CAN_RDL0R_DATA2_Msk (0xFFU << CAN_RDL0R_DATA2_Pos) /*!< 0x00FF0000 */
+#define CAN_RDL0R_DATA2 CAN_RDL0R_DATA2_Msk /*!< Data byte 2 */
+#define CAN_RDL0R_DATA3_Pos (24U)
+#define CAN_RDL0R_DATA3_Msk (0xFFU << CAN_RDL0R_DATA3_Pos) /*!< 0xFF000000 */
+#define CAN_RDL0R_DATA3 CAN_RDL0R_DATA3_Msk /*!< Data byte 3 */
+
+/******************* Bit definition for CAN_RDH0R register ******************/
+#define CAN_RDH0R_DATA4_Pos (0U)
+#define CAN_RDH0R_DATA4_Msk (0xFFU << CAN_RDH0R_DATA4_Pos) /*!< 0x000000FF */
+#define CAN_RDH0R_DATA4 CAN_RDH0R_DATA4_Msk /*!< Data byte 4 */
+#define CAN_RDH0R_DATA5_Pos (8U)
+#define CAN_RDH0R_DATA5_Msk (0xFFU << CAN_RDH0R_DATA5_Pos) /*!< 0x0000FF00 */
+#define CAN_RDH0R_DATA5 CAN_RDH0R_DATA5_Msk /*!< Data byte 5 */
+#define CAN_RDH0R_DATA6_Pos (16U)
+#define CAN_RDH0R_DATA6_Msk (0xFFU << CAN_RDH0R_DATA6_Pos) /*!< 0x00FF0000 */
+#define CAN_RDH0R_DATA6 CAN_RDH0R_DATA6_Msk /*!< Data byte 6 */
+#define CAN_RDH0R_DATA7_Pos (24U)
+#define CAN_RDH0R_DATA7_Msk (0xFFU << CAN_RDH0R_DATA7_Pos) /*!< 0xFF000000 */
+#define CAN_RDH0R_DATA7 CAN_RDH0R_DATA7_Msk /*!< Data byte 7 */
+
+/******************* Bit definition for CAN_RI1R register *******************/
+#define CAN_RI1R_RTR_Pos (1U)
+#define CAN_RI1R_RTR_Msk (0x1U << CAN_RI1R_RTR_Pos) /*!< 0x00000002 */
+#define CAN_RI1R_RTR CAN_RI1R_RTR_Msk /*!< Remote Transmission Request */
+#define CAN_RI1R_IDE_Pos (2U)
+#define CAN_RI1R_IDE_Msk (0x1U << CAN_RI1R_IDE_Pos) /*!< 0x00000004 */
+#define CAN_RI1R_IDE CAN_RI1R_IDE_Msk /*!< Identifier Extension */
+#define CAN_RI1R_EXID_Pos (3U)
+#define CAN_RI1R_EXID_Msk (0x3FFFFU << CAN_RI1R_EXID_Pos) /*!< 0x001FFFF8 */
+#define CAN_RI1R_EXID CAN_RI1R_EXID_Msk /*!< Extended identifier */
+#define CAN_RI1R_STID_Pos (21U)
+#define CAN_RI1R_STID_Msk (0x7FFU << CAN_RI1R_STID_Pos) /*!< 0xFFE00000 */
+#define CAN_RI1R_STID CAN_RI1R_STID_Msk /*!< Standard Identifier or Extended Identifier */
+
+/******************* Bit definition for CAN_RDT1R register ******************/
+#define CAN_RDT1R_DLC_Pos (0U)
+#define CAN_RDT1R_DLC_Msk (0xFU << CAN_RDT1R_DLC_Pos) /*!< 0x0000000F */
+#define CAN_RDT1R_DLC CAN_RDT1R_DLC_Msk /*!< Data Length Code */
+#define CAN_RDT1R_FMI_Pos (8U)
+#define CAN_RDT1R_FMI_Msk (0xFFU << CAN_RDT1R_FMI_Pos) /*!< 0x0000FF00 */
+#define CAN_RDT1R_FMI CAN_RDT1R_FMI_Msk /*!< Filter Match Index */
+#define CAN_RDT1R_TIME_Pos (16U)
+#define CAN_RDT1R_TIME_Msk (0xFFFFU << CAN_RDT1R_TIME_Pos) /*!< 0xFFFF0000 */
+#define CAN_RDT1R_TIME CAN_RDT1R_TIME_Msk /*!< Message Time Stamp */
+
+/******************* Bit definition for CAN_RDL1R register ******************/
+#define CAN_RDL1R_DATA0_Pos (0U)
+#define CAN_RDL1R_DATA0_Msk (0xFFU << CAN_RDL1R_DATA0_Pos) /*!< 0x000000FF */
+#define CAN_RDL1R_DATA0 CAN_RDL1R_DATA0_Msk /*!< Data byte 0 */
+#define CAN_RDL1R_DATA1_Pos (8U)
+#define CAN_RDL1R_DATA1_Msk (0xFFU << CAN_RDL1R_DATA1_Pos) /*!< 0x0000FF00 */
+#define CAN_RDL1R_DATA1 CAN_RDL1R_DATA1_Msk /*!< Data byte 1 */
+#define CAN_RDL1R_DATA2_Pos (16U)
+#define CAN_RDL1R_DATA2_Msk (0xFFU << CAN_RDL1R_DATA2_Pos) /*!< 0x00FF0000 */
+#define CAN_RDL1R_DATA2 CAN_RDL1R_DATA2_Msk /*!< Data byte 2 */
+#define CAN_RDL1R_DATA3_Pos (24U)
+#define CAN_RDL1R_DATA3_Msk (0xFFU << CAN_RDL1R_DATA3_Pos) /*!< 0xFF000000 */
+#define CAN_RDL1R_DATA3 CAN_RDL1R_DATA3_Msk /*!< Data byte 3 */
+
+/******************* Bit definition for CAN_RDH1R register ******************/
+#define CAN_RDH1R_DATA4_Pos (0U)
+#define CAN_RDH1R_DATA4_Msk (0xFFU << CAN_RDH1R_DATA4_Pos) /*!< 0x000000FF */
+#define CAN_RDH1R_DATA4 CAN_RDH1R_DATA4_Msk /*!< Data byte 4 */
+#define CAN_RDH1R_DATA5_Pos (8U)
+#define CAN_RDH1R_DATA5_Msk (0xFFU << CAN_RDH1R_DATA5_Pos) /*!< 0x0000FF00 */
+#define CAN_RDH1R_DATA5 CAN_RDH1R_DATA5_Msk /*!< Data byte 5 */
+#define CAN_RDH1R_DATA6_Pos (16U)
+#define CAN_RDH1R_DATA6_Msk (0xFFU << CAN_RDH1R_DATA6_Pos) /*!< 0x00FF0000 */
+#define CAN_RDH1R_DATA6 CAN_RDH1R_DATA6_Msk /*!< Data byte 6 */
+#define CAN_RDH1R_DATA7_Pos (24U)
+#define CAN_RDH1R_DATA7_Msk (0xFFU << CAN_RDH1R_DATA7_Pos) /*!< 0xFF000000 */
+#define CAN_RDH1R_DATA7 CAN_RDH1R_DATA7_Msk /*!< Data byte 7 */
+
+/*!< CAN filter registers */
+/******************* Bit definition for CAN_FMR register ********************/
+#define CAN_FMR_FINIT_Pos (0U)
+#define CAN_FMR_FINIT_Msk (0x1U << CAN_FMR_FINIT_Pos) /*!< 0x00000001 */
+#define CAN_FMR_FINIT CAN_FMR_FINIT_Msk /*!< Filter Init Mode */
+#define CAN_FMR_CAN2SB_Pos (8U)
+#define CAN_FMR_CAN2SB_Msk (0x3FU << CAN_FMR_CAN2SB_Pos) /*!< 0x00003F00 */
+#define CAN_FMR_CAN2SB CAN_FMR_CAN2SB_Msk /*!< CAN2 start bank */
+
+/******************* Bit definition for CAN_FM1R register *******************/
+#define CAN_FM1R_FBM_Pos (0U)
+#define CAN_FM1R_FBM_Msk (0x3FFFU << CAN_FM1R_FBM_Pos) /*!< 0x00003FFF */
+#define CAN_FM1R_FBM CAN_FM1R_FBM_Msk /*!< Filter Mode */
+#define CAN_FM1R_FBM0_Pos (0U)
+#define CAN_FM1R_FBM0_Msk (0x1U << CAN_FM1R_FBM0_Pos) /*!< 0x00000001 */
+#define CAN_FM1R_FBM0 CAN_FM1R_FBM0_Msk /*!< Filter Init Mode for filter 0 */
+#define CAN_FM1R_FBM1_Pos (1U)
+#define CAN_FM1R_FBM1_Msk (0x1U << CAN_FM1R_FBM1_Pos) /*!< 0x00000002 */
+#define CAN_FM1R_FBM1 CAN_FM1R_FBM1_Msk /*!< Filter Init Mode for filter 1 */
+#define CAN_FM1R_FBM2_Pos (2U)
+#define CAN_FM1R_FBM2_Msk (0x1U << CAN_FM1R_FBM2_Pos) /*!< 0x00000004 */
+#define CAN_FM1R_FBM2 CAN_FM1R_FBM2_Msk /*!< Filter Init Mode for filter 2 */
+#define CAN_FM1R_FBM3_Pos (3U)
+#define CAN_FM1R_FBM3_Msk (0x1U << CAN_FM1R_FBM3_Pos) /*!< 0x00000008 */
+#define CAN_FM1R_FBM3 CAN_FM1R_FBM3_Msk /*!< Filter Init Mode for filter 3 */
+#define CAN_FM1R_FBM4_Pos (4U)
+#define CAN_FM1R_FBM4_Msk (0x1U << CAN_FM1R_FBM4_Pos) /*!< 0x00000010 */
+#define CAN_FM1R_FBM4 CAN_FM1R_FBM4_Msk /*!< Filter Init Mode for filter 4 */
+#define CAN_FM1R_FBM5_Pos (5U)
+#define CAN_FM1R_FBM5_Msk (0x1U << CAN_FM1R_FBM5_Pos) /*!< 0x00000020 */
+#define CAN_FM1R_FBM5 CAN_FM1R_FBM5_Msk /*!< Filter Init Mode for filter 5 */
+#define CAN_FM1R_FBM6_Pos (6U)
+#define CAN_FM1R_FBM6_Msk (0x1U << CAN_FM1R_FBM6_Pos) /*!< 0x00000040 */
+#define CAN_FM1R_FBM6 CAN_FM1R_FBM6_Msk /*!< Filter Init Mode for filter 6 */
+#define CAN_FM1R_FBM7_Pos (7U)
+#define CAN_FM1R_FBM7_Msk (0x1U << CAN_FM1R_FBM7_Pos) /*!< 0x00000080 */
+#define CAN_FM1R_FBM7 CAN_FM1R_FBM7_Msk /*!< Filter Init Mode for filter 7 */
+#define CAN_FM1R_FBM8_Pos (8U)
+#define CAN_FM1R_FBM8_Msk (0x1U << CAN_FM1R_FBM8_Pos) /*!< 0x00000100 */
+#define CAN_FM1R_FBM8 CAN_FM1R_FBM8_Msk /*!< Filter Init Mode for filter 8 */
+#define CAN_FM1R_FBM9_Pos (9U)
+#define CAN_FM1R_FBM9_Msk (0x1U << CAN_FM1R_FBM9_Pos) /*!< 0x00000200 */
+#define CAN_FM1R_FBM9 CAN_FM1R_FBM9_Msk /*!< Filter Init Mode for filter 9 */
+#define CAN_FM1R_FBM10_Pos (10U)
+#define CAN_FM1R_FBM10_Msk (0x1U << CAN_FM1R_FBM10_Pos) /*!< 0x00000400 */
+#define CAN_FM1R_FBM10 CAN_FM1R_FBM10_Msk /*!< Filter Init Mode for filter 10 */
+#define CAN_FM1R_FBM11_Pos (11U)
+#define CAN_FM1R_FBM11_Msk (0x1U << CAN_FM1R_FBM11_Pos) /*!< 0x00000800 */
+#define CAN_FM1R_FBM11 CAN_FM1R_FBM11_Msk /*!< Filter Init Mode for filter 11 */
+#define CAN_FM1R_FBM12_Pos (12U)
+#define CAN_FM1R_FBM12_Msk (0x1U << CAN_FM1R_FBM12_Pos) /*!< 0x00001000 */
+#define CAN_FM1R_FBM12 CAN_FM1R_FBM12_Msk /*!< Filter Init Mode for filter 12 */
+#define CAN_FM1R_FBM13_Pos (13U)
+#define CAN_FM1R_FBM13_Msk (0x1U << CAN_FM1R_FBM13_Pos) /*!< 0x00002000 */
+#define CAN_FM1R_FBM13 CAN_FM1R_FBM13_Msk /*!< Filter Init Mode for filter 13 */
+
+/******************* Bit definition for CAN_FS1R register *******************/
+#define CAN_FS1R_FSC_Pos (0U)
+#define CAN_FS1R_FSC_Msk (0x3FFFU << CAN_FS1R_FSC_Pos) /*!< 0x00003FFF */
+#define CAN_FS1R_FSC CAN_FS1R_FSC_Msk /*!< Filter Scale Configuration */
+#define CAN_FS1R_FSC0_Pos (0U)
+#define CAN_FS1R_FSC0_Msk (0x1U << CAN_FS1R_FSC0_Pos) /*!< 0x00000001 */
+#define CAN_FS1R_FSC0 CAN_FS1R_FSC0_Msk /*!< Filter Scale Configuration for filter 0 */
+#define CAN_FS1R_FSC1_Pos (1U)
+#define CAN_FS1R_FSC1_Msk (0x1U << CAN_FS1R_FSC1_Pos) /*!< 0x00000002 */
+#define CAN_FS1R_FSC1 CAN_FS1R_FSC1_Msk /*!< Filter Scale Configuration for filter 1 */
+#define CAN_FS1R_FSC2_Pos (2U)
+#define CAN_FS1R_FSC2_Msk (0x1U << CAN_FS1R_FSC2_Pos) /*!< 0x00000004 */
+#define CAN_FS1R_FSC2 CAN_FS1R_FSC2_Msk /*!< Filter Scale Configuration for filter 2 */
+#define CAN_FS1R_FSC3_Pos (3U)
+#define CAN_FS1R_FSC3_Msk (0x1U << CAN_FS1R_FSC3_Pos) /*!< 0x00000008 */
+#define CAN_FS1R_FSC3 CAN_FS1R_FSC3_Msk /*!< Filter Scale Configuration for filter 3 */
+#define CAN_FS1R_FSC4_Pos (4U)
+#define CAN_FS1R_FSC4_Msk (0x1U << CAN_FS1R_FSC4_Pos) /*!< 0x00000010 */
+#define CAN_FS1R_FSC4 CAN_FS1R_FSC4_Msk /*!< Filter Scale Configuration for filter 4 */
+#define CAN_FS1R_FSC5_Pos (5U)
+#define CAN_FS1R_FSC5_Msk (0x1U << CAN_FS1R_FSC5_Pos) /*!< 0x00000020 */
+#define CAN_FS1R_FSC5 CAN_FS1R_FSC5_Msk /*!< Filter Scale Configuration for filter 5 */
+#define CAN_FS1R_FSC6_Pos (6U)
+#define CAN_FS1R_FSC6_Msk (0x1U << CAN_FS1R_FSC6_Pos) /*!< 0x00000040 */
+#define CAN_FS1R_FSC6 CAN_FS1R_FSC6_Msk /*!< Filter Scale Configuration for filter 6 */
+#define CAN_FS1R_FSC7_Pos (7U)
+#define CAN_FS1R_FSC7_Msk (0x1U << CAN_FS1R_FSC7_Pos) /*!< 0x00000080 */
+#define CAN_FS1R_FSC7 CAN_FS1R_FSC7_Msk /*!< Filter Scale Configuration for filter 7 */
+#define CAN_FS1R_FSC8_Pos (8U)
+#define CAN_FS1R_FSC8_Msk (0x1U << CAN_FS1R_FSC8_Pos) /*!< 0x00000100 */
+#define CAN_FS1R_FSC8 CAN_FS1R_FSC8_Msk /*!< Filter Scale Configuration for filter 8 */
+#define CAN_FS1R_FSC9_Pos (9U)
+#define CAN_FS1R_FSC9_Msk (0x1U << CAN_FS1R_FSC9_Pos) /*!< 0x00000200 */
+#define CAN_FS1R_FSC9 CAN_FS1R_FSC9_Msk /*!< Filter Scale Configuration for filter 9 */
+#define CAN_FS1R_FSC10_Pos (10U)
+#define CAN_FS1R_FSC10_Msk (0x1U << CAN_FS1R_FSC10_Pos) /*!< 0x00000400 */
+#define CAN_FS1R_FSC10 CAN_FS1R_FSC10_Msk /*!< Filter Scale Configuration for filter 10 */
+#define CAN_FS1R_FSC11_Pos (11U)
+#define CAN_FS1R_FSC11_Msk (0x1U << CAN_FS1R_FSC11_Pos) /*!< 0x00000800 */
+#define CAN_FS1R_FSC11 CAN_FS1R_FSC11_Msk /*!< Filter Scale Configuration for filter 11 */
+#define CAN_FS1R_FSC12_Pos (12U)
+#define CAN_FS1R_FSC12_Msk (0x1U << CAN_FS1R_FSC12_Pos) /*!< 0x00001000 */
+#define CAN_FS1R_FSC12 CAN_FS1R_FSC12_Msk /*!< Filter Scale Configuration for filter 12 */
+#define CAN_FS1R_FSC13_Pos (13U)
+#define CAN_FS1R_FSC13_Msk (0x1U << CAN_FS1R_FSC13_Pos) /*!< 0x00002000 */
+#define CAN_FS1R_FSC13 CAN_FS1R_FSC13_Msk /*!< Filter Scale Configuration for filter 13 */
+
+/****************** Bit definition for CAN_FFA1R register *******************/
+#define CAN_FFA1R_FFA_Pos (0U)
+#define CAN_FFA1R_FFA_Msk (0x3FFFU << CAN_FFA1R_FFA_Pos) /*!< 0x00003FFF */
+#define CAN_FFA1R_FFA CAN_FFA1R_FFA_Msk /*!< Filter FIFO Assignment */
+#define CAN_FFA1R_FFA0_Pos (0U)
+#define CAN_FFA1R_FFA0_Msk (0x1U << CAN_FFA1R_FFA0_Pos) /*!< 0x00000001 */
+#define CAN_FFA1R_FFA0 CAN_FFA1R_FFA0_Msk /*!< Filter FIFO Assignment for filter 0 */
+#define CAN_FFA1R_FFA1_Pos (1U)
+#define CAN_FFA1R_FFA1_Msk (0x1U << CAN_FFA1R_FFA1_Pos) /*!< 0x00000002 */
+#define CAN_FFA1R_FFA1 CAN_FFA1R_FFA1_Msk /*!< Filter FIFO Assignment for filter 1 */
+#define CAN_FFA1R_FFA2_Pos (2U)
+#define CAN_FFA1R_FFA2_Msk (0x1U << CAN_FFA1R_FFA2_Pos) /*!< 0x00000004 */
+#define CAN_FFA1R_FFA2 CAN_FFA1R_FFA2_Msk /*!< Filter FIFO Assignment for filter 2 */
+#define CAN_FFA1R_FFA3_Pos (3U)
+#define CAN_FFA1R_FFA3_Msk (0x1U << CAN_FFA1R_FFA3_Pos) /*!< 0x00000008 */
+#define CAN_FFA1R_FFA3 CAN_FFA1R_FFA3_Msk /*!< Filter FIFO Assignment for filter 3 */
+#define CAN_FFA1R_FFA4_Pos (4U)
+#define CAN_FFA1R_FFA4_Msk (0x1U << CAN_FFA1R_FFA4_Pos) /*!< 0x00000010 */
+#define CAN_FFA1R_FFA4 CAN_FFA1R_FFA4_Msk /*!< Filter FIFO Assignment for filter 4 */
+#define CAN_FFA1R_FFA5_Pos (5U)
+#define CAN_FFA1R_FFA5_Msk (0x1U << CAN_FFA1R_FFA5_Pos) /*!< 0x00000020 */
+#define CAN_FFA1R_FFA5 CAN_FFA1R_FFA5_Msk /*!< Filter FIFO Assignment for filter 5 */
+#define CAN_FFA1R_FFA6_Pos (6U)
+#define CAN_FFA1R_FFA6_Msk (0x1U << CAN_FFA1R_FFA6_Pos) /*!< 0x00000040 */
+#define CAN_FFA1R_FFA6 CAN_FFA1R_FFA6_Msk /*!< Filter FIFO Assignment for filter 6 */
+#define CAN_FFA1R_FFA7_Pos (7U)
+#define CAN_FFA1R_FFA7_Msk (0x1U << CAN_FFA1R_FFA7_Pos) /*!< 0x00000080 */
+#define CAN_FFA1R_FFA7 CAN_FFA1R_FFA7_Msk /*!< Filter FIFO Assignment for filter 7 */
+#define CAN_FFA1R_FFA8_Pos (8U)
+#define CAN_FFA1R_FFA8_Msk (0x1U << CAN_FFA1R_FFA8_Pos) /*!< 0x00000100 */
+#define CAN_FFA1R_FFA8 CAN_FFA1R_FFA8_Msk /*!< Filter FIFO Assignment for filter 8 */
+#define CAN_FFA1R_FFA9_Pos (9U)
+#define CAN_FFA1R_FFA9_Msk (0x1U << CAN_FFA1R_FFA9_Pos) /*!< 0x00000200 */
+#define CAN_FFA1R_FFA9 CAN_FFA1R_FFA9_Msk /*!< Filter FIFO Assignment for filter 9 */
+#define CAN_FFA1R_FFA10_Pos (10U)
+#define CAN_FFA1R_FFA10_Msk (0x1U << CAN_FFA1R_FFA10_Pos) /*!< 0x00000400 */
+#define CAN_FFA1R_FFA10 CAN_FFA1R_FFA10_Msk /*!< Filter FIFO Assignment for filter 10 */
+#define CAN_FFA1R_FFA11_Pos (11U)
+#define CAN_FFA1R_FFA11_Msk (0x1U << CAN_FFA1R_FFA11_Pos) /*!< 0x00000800 */
+#define CAN_FFA1R_FFA11 CAN_FFA1R_FFA11_Msk /*!< Filter FIFO Assignment for filter 11 */
+#define CAN_FFA1R_FFA12_Pos (12U)
+#define CAN_FFA1R_FFA12_Msk (0x1U << CAN_FFA1R_FFA12_Pos) /*!< 0x00001000 */
+#define CAN_FFA1R_FFA12 CAN_FFA1R_FFA12_Msk /*!< Filter FIFO Assignment for filter 12 */
+#define CAN_FFA1R_FFA13_Pos (13U)
+#define CAN_FFA1R_FFA13_Msk (0x1U << CAN_FFA1R_FFA13_Pos) /*!< 0x00002000 */
+#define CAN_FFA1R_FFA13 CAN_FFA1R_FFA13_Msk /*!< Filter FIFO Assignment for filter 13 */
+
+/******************* Bit definition for CAN_FA1R register *******************/
+#define CAN_FA1R_FACT_Pos (0U)
+#define CAN_FA1R_FACT_Msk (0x3FFFU << CAN_FA1R_FACT_Pos) /*!< 0x00003FFF */
+#define CAN_FA1R_FACT CAN_FA1R_FACT_Msk /*!< Filter Active */
+#define CAN_FA1R_FACT0_Pos (0U)
+#define CAN_FA1R_FACT0_Msk (0x1U << CAN_FA1R_FACT0_Pos) /*!< 0x00000001 */
+#define CAN_FA1R_FACT0 CAN_FA1R_FACT0_Msk /*!< Filter 0 Active */
+#define CAN_FA1R_FACT1_Pos (1U)
+#define CAN_FA1R_FACT1_Msk (0x1U << CAN_FA1R_FACT1_Pos) /*!< 0x00000002 */
+#define CAN_FA1R_FACT1 CAN_FA1R_FACT1_Msk /*!< Filter 1 Active */
+#define CAN_FA1R_FACT2_Pos (2U)
+#define CAN_FA1R_FACT2_Msk (0x1U << CAN_FA1R_FACT2_Pos) /*!< 0x00000004 */
+#define CAN_FA1R_FACT2 CAN_FA1R_FACT2_Msk /*!< Filter 2 Active */
+#define CAN_FA1R_FACT3_Pos (3U)
+#define CAN_FA1R_FACT3_Msk (0x1U << CAN_FA1R_FACT3_Pos) /*!< 0x00000008 */
+#define CAN_FA1R_FACT3 CAN_FA1R_FACT3_Msk /*!< Filter 3 Active */
+#define CAN_FA1R_FACT4_Pos (4U)
+#define CAN_FA1R_FACT4_Msk (0x1U << CAN_FA1R_FACT4_Pos) /*!< 0x00000010 */
+#define CAN_FA1R_FACT4 CAN_FA1R_FACT4_Msk /*!< Filter 4 Active */
+#define CAN_FA1R_FACT5_Pos (5U)
+#define CAN_FA1R_FACT5_Msk (0x1U << CAN_FA1R_FACT5_Pos) /*!< 0x00000020 */
+#define CAN_FA1R_FACT5 CAN_FA1R_FACT5_Msk /*!< Filter 5 Active */
+#define CAN_FA1R_FACT6_Pos (6U)
+#define CAN_FA1R_FACT6_Msk (0x1U << CAN_FA1R_FACT6_Pos) /*!< 0x00000040 */
+#define CAN_FA1R_FACT6 CAN_FA1R_FACT6_Msk /*!< Filter 6 Active */
+#define CAN_FA1R_FACT7_Pos (7U)
+#define CAN_FA1R_FACT7_Msk (0x1U << CAN_FA1R_FACT7_Pos) /*!< 0x00000080 */
+#define CAN_FA1R_FACT7 CAN_FA1R_FACT7_Msk /*!< Filter 7 Active */
+#define CAN_FA1R_FACT8_Pos (8U)
+#define CAN_FA1R_FACT8_Msk (0x1U << CAN_FA1R_FACT8_Pos) /*!< 0x00000100 */
+#define CAN_FA1R_FACT8 CAN_FA1R_FACT8_Msk /*!< Filter 8 Active */
+#define CAN_FA1R_FACT9_Pos (9U)
+#define CAN_FA1R_FACT9_Msk (0x1U << CAN_FA1R_FACT9_Pos) /*!< 0x00000200 */
+#define CAN_FA1R_FACT9 CAN_FA1R_FACT9_Msk /*!< Filter 9 Active */
+#define CAN_FA1R_FACT10_Pos (10U)
+#define CAN_FA1R_FACT10_Msk (0x1U << CAN_FA1R_FACT10_Pos) /*!< 0x00000400 */
+#define CAN_FA1R_FACT10 CAN_FA1R_FACT10_Msk /*!< Filter 10 Active */
+#define CAN_FA1R_FACT11_Pos (11U)
+#define CAN_FA1R_FACT11_Msk (0x1U << CAN_FA1R_FACT11_Pos) /*!< 0x00000800 */
+#define CAN_FA1R_FACT11 CAN_FA1R_FACT11_Msk /*!< Filter 11 Active */
+#define CAN_FA1R_FACT12_Pos (12U)
+#define CAN_FA1R_FACT12_Msk (0x1U << CAN_FA1R_FACT12_Pos) /*!< 0x00001000 */
+#define CAN_FA1R_FACT12 CAN_FA1R_FACT12_Msk /*!< Filter 12 Active */
+#define CAN_FA1R_FACT13_Pos (13U)
+#define CAN_FA1R_FACT13_Msk (0x1U << CAN_FA1R_FACT13_Pos) /*!< 0x00002000 */
+#define CAN_FA1R_FACT13 CAN_FA1R_FACT13_Msk /*!< Filter 13 Active */
+
+/******************* Bit definition for CAN_F0R1 register *******************/
+#define CAN_F0R1_FB0_Pos (0U)
+#define CAN_F0R1_FB0_Msk (0x1U << CAN_F0R1_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F0R1_FB0 CAN_F0R1_FB0_Msk /*!< Filter bit 0 */
+#define CAN_F0R1_FB1_Pos (1U)
+#define CAN_F0R1_FB1_Msk (0x1U << CAN_F0R1_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F0R1_FB1 CAN_F0R1_FB1_Msk /*!< Filter bit 1 */
+#define CAN_F0R1_FB2_Pos (2U)
+#define CAN_F0R1_FB2_Msk (0x1U << CAN_F0R1_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F0R1_FB2 CAN_F0R1_FB2_Msk /*!< Filter bit 2 */
+#define CAN_F0R1_FB3_Pos (3U)
+#define CAN_F0R1_FB3_Msk (0x1U << CAN_F0R1_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F0R1_FB3 CAN_F0R1_FB3_Msk /*!< Filter bit 3 */
+#define CAN_F0R1_FB4_Pos (4U)
+#define CAN_F0R1_FB4_Msk (0x1U << CAN_F0R1_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F0R1_FB4 CAN_F0R1_FB4_Msk /*!< Filter bit 4 */
+#define CAN_F0R1_FB5_Pos (5U)
+#define CAN_F0R1_FB5_Msk (0x1U << CAN_F0R1_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F0R1_FB5 CAN_F0R1_FB5_Msk /*!< Filter bit 5 */
+#define CAN_F0R1_FB6_Pos (6U)
+#define CAN_F0R1_FB6_Msk (0x1U << CAN_F0R1_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F0R1_FB6 CAN_F0R1_FB6_Msk /*!< Filter bit 6 */
+#define CAN_F0R1_FB7_Pos (7U)
+#define CAN_F0R1_FB7_Msk (0x1U << CAN_F0R1_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F0R1_FB7 CAN_F0R1_FB7_Msk /*!< Filter bit 7 */
+#define CAN_F0R1_FB8_Pos (8U)
+#define CAN_F0R1_FB8_Msk (0x1U << CAN_F0R1_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F0R1_FB8 CAN_F0R1_FB8_Msk /*!< Filter bit 8 */
+#define CAN_F0R1_FB9_Pos (9U)
+#define CAN_F0R1_FB9_Msk (0x1U << CAN_F0R1_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F0R1_FB9 CAN_F0R1_FB9_Msk /*!< Filter bit 9 */
+#define CAN_F0R1_FB10_Pos (10U)
+#define CAN_F0R1_FB10_Msk (0x1U << CAN_F0R1_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F0R1_FB10 CAN_F0R1_FB10_Msk /*!< Filter bit 10 */
+#define CAN_F0R1_FB11_Pos (11U)
+#define CAN_F0R1_FB11_Msk (0x1U << CAN_F0R1_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F0R1_FB11 CAN_F0R1_FB11_Msk /*!< Filter bit 11 */
+#define CAN_F0R1_FB12_Pos (12U)
+#define CAN_F0R1_FB12_Msk (0x1U << CAN_F0R1_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F0R1_FB12 CAN_F0R1_FB12_Msk /*!< Filter bit 12 */
+#define CAN_F0R1_FB13_Pos (13U)
+#define CAN_F0R1_FB13_Msk (0x1U << CAN_F0R1_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F0R1_FB13 CAN_F0R1_FB13_Msk /*!< Filter bit 13 */
+#define CAN_F0R1_FB14_Pos (14U)
+#define CAN_F0R1_FB14_Msk (0x1U << CAN_F0R1_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F0R1_FB14 CAN_F0R1_FB14_Msk /*!< Filter bit 14 */
+#define CAN_F0R1_FB15_Pos (15U)
+#define CAN_F0R1_FB15_Msk (0x1U << CAN_F0R1_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F0R1_FB15 CAN_F0R1_FB15_Msk /*!< Filter bit 15 */
+#define CAN_F0R1_FB16_Pos (16U)
+#define CAN_F0R1_FB16_Msk (0x1U << CAN_F0R1_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F0R1_FB16 CAN_F0R1_FB16_Msk /*!< Filter bit 16 */
+#define CAN_F0R1_FB17_Pos (17U)
+#define CAN_F0R1_FB17_Msk (0x1U << CAN_F0R1_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F0R1_FB17 CAN_F0R1_FB17_Msk /*!< Filter bit 17 */
+#define CAN_F0R1_FB18_Pos (18U)
+#define CAN_F0R1_FB18_Msk (0x1U << CAN_F0R1_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F0R1_FB18 CAN_F0R1_FB18_Msk /*!< Filter bit 18 */
+#define CAN_F0R1_FB19_Pos (19U)
+#define CAN_F0R1_FB19_Msk (0x1U << CAN_F0R1_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F0R1_FB19 CAN_F0R1_FB19_Msk /*!< Filter bit 19 */
+#define CAN_F0R1_FB20_Pos (20U)
+#define CAN_F0R1_FB20_Msk (0x1U << CAN_F0R1_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F0R1_FB20 CAN_F0R1_FB20_Msk /*!< Filter bit 20 */
+#define CAN_F0R1_FB21_Pos (21U)
+#define CAN_F0R1_FB21_Msk (0x1U << CAN_F0R1_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F0R1_FB21 CAN_F0R1_FB21_Msk /*!< Filter bit 21 */
+#define CAN_F0R1_FB22_Pos (22U)
+#define CAN_F0R1_FB22_Msk (0x1U << CAN_F0R1_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F0R1_FB22 CAN_F0R1_FB22_Msk /*!< Filter bit 22 */
+#define CAN_F0R1_FB23_Pos (23U)
+#define CAN_F0R1_FB23_Msk (0x1U << CAN_F0R1_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F0R1_FB23 CAN_F0R1_FB23_Msk /*!< Filter bit 23 */
+#define CAN_F0R1_FB24_Pos (24U)
+#define CAN_F0R1_FB24_Msk (0x1U << CAN_F0R1_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F0R1_FB24 CAN_F0R1_FB24_Msk /*!< Filter bit 24 */
+#define CAN_F0R1_FB25_Pos (25U)
+#define CAN_F0R1_FB25_Msk (0x1U << CAN_F0R1_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F0R1_FB25 CAN_F0R1_FB25_Msk /*!< Filter bit 25 */
+#define CAN_F0R1_FB26_Pos (26U)
+#define CAN_F0R1_FB26_Msk (0x1U << CAN_F0R1_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F0R1_FB26 CAN_F0R1_FB26_Msk /*!< Filter bit 26 */
+#define CAN_F0R1_FB27_Pos (27U)
+#define CAN_F0R1_FB27_Msk (0x1U << CAN_F0R1_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F0R1_FB27 CAN_F0R1_FB27_Msk /*!< Filter bit 27 */
+#define CAN_F0R1_FB28_Pos (28U)
+#define CAN_F0R1_FB28_Msk (0x1U << CAN_F0R1_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F0R1_FB28 CAN_F0R1_FB28_Msk /*!< Filter bit 28 */
+#define CAN_F0R1_FB29_Pos (29U)
+#define CAN_F0R1_FB29_Msk (0x1U << CAN_F0R1_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F0R1_FB29 CAN_F0R1_FB29_Msk /*!< Filter bit 29 */
+#define CAN_F0R1_FB30_Pos (30U)
+#define CAN_F0R1_FB30_Msk (0x1U << CAN_F0R1_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F0R1_FB30 CAN_F0R1_FB30_Msk /*!< Filter bit 30 */
+#define CAN_F0R1_FB31_Pos (31U)
+#define CAN_F0R1_FB31_Msk (0x1U << CAN_F0R1_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F0R1_FB31 CAN_F0R1_FB31_Msk /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F1R1 register *******************/
+#define CAN_F1R1_FB0_Pos (0U)
+#define CAN_F1R1_FB0_Msk (0x1U << CAN_F1R1_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F1R1_FB0 CAN_F1R1_FB0_Msk /*!< Filter bit 0 */
+#define CAN_F1R1_FB1_Pos (1U)
+#define CAN_F1R1_FB1_Msk (0x1U << CAN_F1R1_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F1R1_FB1 CAN_F1R1_FB1_Msk /*!< Filter bit 1 */
+#define CAN_F1R1_FB2_Pos (2U)
+#define CAN_F1R1_FB2_Msk (0x1U << CAN_F1R1_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F1R1_FB2 CAN_F1R1_FB2_Msk /*!< Filter bit 2 */
+#define CAN_F1R1_FB3_Pos (3U)
+#define CAN_F1R1_FB3_Msk (0x1U << CAN_F1R1_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F1R1_FB3 CAN_F1R1_FB3_Msk /*!< Filter bit 3 */
+#define CAN_F1R1_FB4_Pos (4U)
+#define CAN_F1R1_FB4_Msk (0x1U << CAN_F1R1_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F1R1_FB4 CAN_F1R1_FB4_Msk /*!< Filter bit 4 */
+#define CAN_F1R1_FB5_Pos (5U)
+#define CAN_F1R1_FB5_Msk (0x1U << CAN_F1R1_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F1R1_FB5 CAN_F1R1_FB5_Msk /*!< Filter bit 5 */
+#define CAN_F1R1_FB6_Pos (6U)
+#define CAN_F1R1_FB6_Msk (0x1U << CAN_F1R1_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F1R1_FB6 CAN_F1R1_FB6_Msk /*!< Filter bit 6 */
+#define CAN_F1R1_FB7_Pos (7U)
+#define CAN_F1R1_FB7_Msk (0x1U << CAN_F1R1_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F1R1_FB7 CAN_F1R1_FB7_Msk /*!< Filter bit 7 */
+#define CAN_F1R1_FB8_Pos (8U)
+#define CAN_F1R1_FB8_Msk (0x1U << CAN_F1R1_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F1R1_FB8 CAN_F1R1_FB8_Msk /*!< Filter bit 8 */
+#define CAN_F1R1_FB9_Pos (9U)
+#define CAN_F1R1_FB9_Msk (0x1U << CAN_F1R1_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F1R1_FB9 CAN_F1R1_FB9_Msk /*!< Filter bit 9 */
+#define CAN_F1R1_FB10_Pos (10U)
+#define CAN_F1R1_FB10_Msk (0x1U << CAN_F1R1_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F1R1_FB10 CAN_F1R1_FB10_Msk /*!< Filter bit 10 */
+#define CAN_F1R1_FB11_Pos (11U)
+#define CAN_F1R1_FB11_Msk (0x1U << CAN_F1R1_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F1R1_FB11 CAN_F1R1_FB11_Msk /*!< Filter bit 11 */
+#define CAN_F1R1_FB12_Pos (12U)
+#define CAN_F1R1_FB12_Msk (0x1U << CAN_F1R1_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F1R1_FB12 CAN_F1R1_FB12_Msk /*!< Filter bit 12 */
+#define CAN_F1R1_FB13_Pos (13U)
+#define CAN_F1R1_FB13_Msk (0x1U << CAN_F1R1_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F1R1_FB13 CAN_F1R1_FB13_Msk /*!< Filter bit 13 */
+#define CAN_F1R1_FB14_Pos (14U)
+#define CAN_F1R1_FB14_Msk (0x1U << CAN_F1R1_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F1R1_FB14 CAN_F1R1_FB14_Msk /*!< Filter bit 14 */
+#define CAN_F1R1_FB15_Pos (15U)
+#define CAN_F1R1_FB15_Msk (0x1U << CAN_F1R1_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F1R1_FB15 CAN_F1R1_FB15_Msk /*!< Filter bit 15 */
+#define CAN_F1R1_FB16_Pos (16U)
+#define CAN_F1R1_FB16_Msk (0x1U << CAN_F1R1_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F1R1_FB16 CAN_F1R1_FB16_Msk /*!< Filter bit 16 */
+#define CAN_F1R1_FB17_Pos (17U)
+#define CAN_F1R1_FB17_Msk (0x1U << CAN_F1R1_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F1R1_FB17 CAN_F1R1_FB17_Msk /*!< Filter bit 17 */
+#define CAN_F1R1_FB18_Pos (18U)
+#define CAN_F1R1_FB18_Msk (0x1U << CAN_F1R1_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F1R1_FB18 CAN_F1R1_FB18_Msk /*!< Filter bit 18 */
+#define CAN_F1R1_FB19_Pos (19U)
+#define CAN_F1R1_FB19_Msk (0x1U << CAN_F1R1_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F1R1_FB19 CAN_F1R1_FB19_Msk /*!< Filter bit 19 */
+#define CAN_F1R1_FB20_Pos (20U)
+#define CAN_F1R1_FB20_Msk (0x1U << CAN_F1R1_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F1R1_FB20 CAN_F1R1_FB20_Msk /*!< Filter bit 20 */
+#define CAN_F1R1_FB21_Pos (21U)
+#define CAN_F1R1_FB21_Msk (0x1U << CAN_F1R1_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F1R1_FB21 CAN_F1R1_FB21_Msk /*!< Filter bit 21 */
+#define CAN_F1R1_FB22_Pos (22U)
+#define CAN_F1R1_FB22_Msk (0x1U << CAN_F1R1_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F1R1_FB22 CAN_F1R1_FB22_Msk /*!< Filter bit 22 */
+#define CAN_F1R1_FB23_Pos (23U)
+#define CAN_F1R1_FB23_Msk (0x1U << CAN_F1R1_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F1R1_FB23 CAN_F1R1_FB23_Msk /*!< Filter bit 23 */
+#define CAN_F1R1_FB24_Pos (24U)
+#define CAN_F1R1_FB24_Msk (0x1U << CAN_F1R1_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F1R1_FB24 CAN_F1R1_FB24_Msk /*!< Filter bit 24 */
+#define CAN_F1R1_FB25_Pos (25U)
+#define CAN_F1R1_FB25_Msk (0x1U << CAN_F1R1_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F1R1_FB25 CAN_F1R1_FB25_Msk /*!< Filter bit 25 */
+#define CAN_F1R1_FB26_Pos (26U)
+#define CAN_F1R1_FB26_Msk (0x1U << CAN_F1R1_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F1R1_FB26 CAN_F1R1_FB26_Msk /*!< Filter bit 26 */
+#define CAN_F1R1_FB27_Pos (27U)
+#define CAN_F1R1_FB27_Msk (0x1U << CAN_F1R1_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F1R1_FB27 CAN_F1R1_FB27_Msk /*!< Filter bit 27 */
+#define CAN_F1R1_FB28_Pos (28U)
+#define CAN_F1R1_FB28_Msk (0x1U << CAN_F1R1_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F1R1_FB28 CAN_F1R1_FB28_Msk /*!< Filter bit 28 */
+#define CAN_F1R1_FB29_Pos (29U)
+#define CAN_F1R1_FB29_Msk (0x1U << CAN_F1R1_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F1R1_FB29 CAN_F1R1_FB29_Msk /*!< Filter bit 29 */
+#define CAN_F1R1_FB30_Pos (30U)
+#define CAN_F1R1_FB30_Msk (0x1U << CAN_F1R1_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F1R1_FB30 CAN_F1R1_FB30_Msk /*!< Filter bit 30 */
+#define CAN_F1R1_FB31_Pos (31U)
+#define CAN_F1R1_FB31_Msk (0x1U << CAN_F1R1_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F1R1_FB31 CAN_F1R1_FB31_Msk /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F2R1 register *******************/
+#define CAN_F2R1_FB0_Pos (0U)
+#define CAN_F2R1_FB0_Msk (0x1U << CAN_F2R1_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F2R1_FB0 CAN_F2R1_FB0_Msk /*!< Filter bit 0 */
+#define CAN_F2R1_FB1_Pos (1U)
+#define CAN_F2R1_FB1_Msk (0x1U << CAN_F2R1_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F2R1_FB1 CAN_F2R1_FB1_Msk /*!< Filter bit 1 */
+#define CAN_F2R1_FB2_Pos (2U)
+#define CAN_F2R1_FB2_Msk (0x1U << CAN_F2R1_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F2R1_FB2 CAN_F2R1_FB2_Msk /*!< Filter bit 2 */
+#define CAN_F2R1_FB3_Pos (3U)
+#define CAN_F2R1_FB3_Msk (0x1U << CAN_F2R1_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F2R1_FB3 CAN_F2R1_FB3_Msk /*!< Filter bit 3 */
+#define CAN_F2R1_FB4_Pos (4U)
+#define CAN_F2R1_FB4_Msk (0x1U << CAN_F2R1_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F2R1_FB4 CAN_F2R1_FB4_Msk /*!< Filter bit 4 */
+#define CAN_F2R1_FB5_Pos (5U)
+#define CAN_F2R1_FB5_Msk (0x1U << CAN_F2R1_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F2R1_FB5 CAN_F2R1_FB5_Msk /*!< Filter bit 5 */
+#define CAN_F2R1_FB6_Pos (6U)
+#define CAN_F2R1_FB6_Msk (0x1U << CAN_F2R1_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F2R1_FB6 CAN_F2R1_FB6_Msk /*!< Filter bit 6 */
+#define CAN_F2R1_FB7_Pos (7U)
+#define CAN_F2R1_FB7_Msk (0x1U << CAN_F2R1_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F2R1_FB7 CAN_F2R1_FB7_Msk /*!< Filter bit 7 */
+#define CAN_F2R1_FB8_Pos (8U)
+#define CAN_F2R1_FB8_Msk (0x1U << CAN_F2R1_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F2R1_FB8 CAN_F2R1_FB8_Msk /*!< Filter bit 8 */
+#define CAN_F2R1_FB9_Pos (9U)
+#define CAN_F2R1_FB9_Msk (0x1U << CAN_F2R1_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F2R1_FB9 CAN_F2R1_FB9_Msk /*!< Filter bit 9 */
+#define CAN_F2R1_FB10_Pos (10U)
+#define CAN_F2R1_FB10_Msk (0x1U << CAN_F2R1_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F2R1_FB10 CAN_F2R1_FB10_Msk /*!< Filter bit 10 */
+#define CAN_F2R1_FB11_Pos (11U)
+#define CAN_F2R1_FB11_Msk (0x1U << CAN_F2R1_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F2R1_FB11 CAN_F2R1_FB11_Msk /*!< Filter bit 11 */
+#define CAN_F2R1_FB12_Pos (12U)
+#define CAN_F2R1_FB12_Msk (0x1U << CAN_F2R1_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F2R1_FB12 CAN_F2R1_FB12_Msk /*!< Filter bit 12 */
+#define CAN_F2R1_FB13_Pos (13U)
+#define CAN_F2R1_FB13_Msk (0x1U << CAN_F2R1_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F2R1_FB13 CAN_F2R1_FB13_Msk /*!< Filter bit 13 */
+#define CAN_F2R1_FB14_Pos (14U)
+#define CAN_F2R1_FB14_Msk (0x1U << CAN_F2R1_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F2R1_FB14 CAN_F2R1_FB14_Msk /*!< Filter bit 14 */
+#define CAN_F2R1_FB15_Pos (15U)
+#define CAN_F2R1_FB15_Msk (0x1U << CAN_F2R1_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F2R1_FB15 CAN_F2R1_FB15_Msk /*!< Filter bit 15 */
+#define CAN_F2R1_FB16_Pos (16U)
+#define CAN_F2R1_FB16_Msk (0x1U << CAN_F2R1_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F2R1_FB16 CAN_F2R1_FB16_Msk /*!< Filter bit 16 */
+#define CAN_F2R1_FB17_Pos (17U)
+#define CAN_F2R1_FB17_Msk (0x1U << CAN_F2R1_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F2R1_FB17 CAN_F2R1_FB17_Msk /*!< Filter bit 17 */
+#define CAN_F2R1_FB18_Pos (18U)
+#define CAN_F2R1_FB18_Msk (0x1U << CAN_F2R1_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F2R1_FB18 CAN_F2R1_FB18_Msk /*!< Filter bit 18 */
+#define CAN_F2R1_FB19_Pos (19U)
+#define CAN_F2R1_FB19_Msk (0x1U << CAN_F2R1_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F2R1_FB19 CAN_F2R1_FB19_Msk /*!< Filter bit 19 */
+#define CAN_F2R1_FB20_Pos (20U)
+#define CAN_F2R1_FB20_Msk (0x1U << CAN_F2R1_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F2R1_FB20 CAN_F2R1_FB20_Msk /*!< Filter bit 20 */
+#define CAN_F2R1_FB21_Pos (21U)
+#define CAN_F2R1_FB21_Msk (0x1U << CAN_F2R1_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F2R1_FB21 CAN_F2R1_FB21_Msk /*!< Filter bit 21 */
+#define CAN_F2R1_FB22_Pos (22U)
+#define CAN_F2R1_FB22_Msk (0x1U << CAN_F2R1_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F2R1_FB22 CAN_F2R1_FB22_Msk /*!< Filter bit 22 */
+#define CAN_F2R1_FB23_Pos (23U)
+#define CAN_F2R1_FB23_Msk (0x1U << CAN_F2R1_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F2R1_FB23 CAN_F2R1_FB23_Msk /*!< Filter bit 23 */
+#define CAN_F2R1_FB24_Pos (24U)
+#define CAN_F2R1_FB24_Msk (0x1U << CAN_F2R1_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F2R1_FB24 CAN_F2R1_FB24_Msk /*!< Filter bit 24 */
+#define CAN_F2R1_FB25_Pos (25U)
+#define CAN_F2R1_FB25_Msk (0x1U << CAN_F2R1_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F2R1_FB25 CAN_F2R1_FB25_Msk /*!< Filter bit 25 */
+#define CAN_F2R1_FB26_Pos (26U)
+#define CAN_F2R1_FB26_Msk (0x1U << CAN_F2R1_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F2R1_FB26 CAN_F2R1_FB26_Msk /*!< Filter bit 26 */
+#define CAN_F2R1_FB27_Pos (27U)
+#define CAN_F2R1_FB27_Msk (0x1U << CAN_F2R1_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F2R1_FB27 CAN_F2R1_FB27_Msk /*!< Filter bit 27 */
+#define CAN_F2R1_FB28_Pos (28U)
+#define CAN_F2R1_FB28_Msk (0x1U << CAN_F2R1_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F2R1_FB28 CAN_F2R1_FB28_Msk /*!< Filter bit 28 */
+#define CAN_F2R1_FB29_Pos (29U)
+#define CAN_F2R1_FB29_Msk (0x1U << CAN_F2R1_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F2R1_FB29 CAN_F2R1_FB29_Msk /*!< Filter bit 29 */
+#define CAN_F2R1_FB30_Pos (30U)
+#define CAN_F2R1_FB30_Msk (0x1U << CAN_F2R1_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F2R1_FB30 CAN_F2R1_FB30_Msk /*!< Filter bit 30 */
+#define CAN_F2R1_FB31_Pos (31U)
+#define CAN_F2R1_FB31_Msk (0x1U << CAN_F2R1_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F2R1_FB31 CAN_F2R1_FB31_Msk /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F3R1 register *******************/
+#define CAN_F3R1_FB0_Pos (0U)
+#define CAN_F3R1_FB0_Msk (0x1U << CAN_F3R1_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F3R1_FB0 CAN_F3R1_FB0_Msk /*!< Filter bit 0 */
+#define CAN_F3R1_FB1_Pos (1U)
+#define CAN_F3R1_FB1_Msk (0x1U << CAN_F3R1_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F3R1_FB1 CAN_F3R1_FB1_Msk /*!< Filter bit 1 */
+#define CAN_F3R1_FB2_Pos (2U)
+#define CAN_F3R1_FB2_Msk (0x1U << CAN_F3R1_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F3R1_FB2 CAN_F3R1_FB2_Msk /*!< Filter bit 2 */
+#define CAN_F3R1_FB3_Pos (3U)
+#define CAN_F3R1_FB3_Msk (0x1U << CAN_F3R1_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F3R1_FB3 CAN_F3R1_FB3_Msk /*!< Filter bit 3 */
+#define CAN_F3R1_FB4_Pos (4U)
+#define CAN_F3R1_FB4_Msk (0x1U << CAN_F3R1_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F3R1_FB4 CAN_F3R1_FB4_Msk /*!< Filter bit 4 */
+#define CAN_F3R1_FB5_Pos (5U)
+#define CAN_F3R1_FB5_Msk (0x1U << CAN_F3R1_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F3R1_FB5 CAN_F3R1_FB5_Msk /*!< Filter bit 5 */
+#define CAN_F3R1_FB6_Pos (6U)
+#define CAN_F3R1_FB6_Msk (0x1U << CAN_F3R1_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F3R1_FB6 CAN_F3R1_FB6_Msk /*!< Filter bit 6 */
+#define CAN_F3R1_FB7_Pos (7U)
+#define CAN_F3R1_FB7_Msk (0x1U << CAN_F3R1_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F3R1_FB7 CAN_F3R1_FB7_Msk /*!< Filter bit 7 */
+#define CAN_F3R1_FB8_Pos (8U)
+#define CAN_F3R1_FB8_Msk (0x1U << CAN_F3R1_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F3R1_FB8 CAN_F3R1_FB8_Msk /*!< Filter bit 8 */
+#define CAN_F3R1_FB9_Pos (9U)
+#define CAN_F3R1_FB9_Msk (0x1U << CAN_F3R1_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F3R1_FB9 CAN_F3R1_FB9_Msk /*!< Filter bit 9 */
+#define CAN_F3R1_FB10_Pos (10U)
+#define CAN_F3R1_FB10_Msk (0x1U << CAN_F3R1_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F3R1_FB10 CAN_F3R1_FB10_Msk /*!< Filter bit 10 */
+#define CAN_F3R1_FB11_Pos (11U)
+#define CAN_F3R1_FB11_Msk (0x1U << CAN_F3R1_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F3R1_FB11 CAN_F3R1_FB11_Msk /*!< Filter bit 11 */
+#define CAN_F3R1_FB12_Pos (12U)
+#define CAN_F3R1_FB12_Msk (0x1U << CAN_F3R1_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F3R1_FB12 CAN_F3R1_FB12_Msk /*!< Filter bit 12 */
+#define CAN_F3R1_FB13_Pos (13U)
+#define CAN_F3R1_FB13_Msk (0x1U << CAN_F3R1_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F3R1_FB13 CAN_F3R1_FB13_Msk /*!< Filter bit 13 */
+#define CAN_F3R1_FB14_Pos (14U)
+#define CAN_F3R1_FB14_Msk (0x1U << CAN_F3R1_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F3R1_FB14 CAN_F3R1_FB14_Msk /*!< Filter bit 14 */
+#define CAN_F3R1_FB15_Pos (15U)
+#define CAN_F3R1_FB15_Msk (0x1U << CAN_F3R1_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F3R1_FB15 CAN_F3R1_FB15_Msk /*!< Filter bit 15 */
+#define CAN_F3R1_FB16_Pos (16U)
+#define CAN_F3R1_FB16_Msk (0x1U << CAN_F3R1_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F3R1_FB16 CAN_F3R1_FB16_Msk /*!< Filter bit 16 */
+#define CAN_F3R1_FB17_Pos (17U)
+#define CAN_F3R1_FB17_Msk (0x1U << CAN_F3R1_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F3R1_FB17 CAN_F3R1_FB17_Msk /*!< Filter bit 17 */
+#define CAN_F3R1_FB18_Pos (18U)
+#define CAN_F3R1_FB18_Msk (0x1U << CAN_F3R1_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F3R1_FB18 CAN_F3R1_FB18_Msk /*!< Filter bit 18 */
+#define CAN_F3R1_FB19_Pos (19U)
+#define CAN_F3R1_FB19_Msk (0x1U << CAN_F3R1_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F3R1_FB19 CAN_F3R1_FB19_Msk /*!< Filter bit 19 */
+#define CAN_F3R1_FB20_Pos (20U)
+#define CAN_F3R1_FB20_Msk (0x1U << CAN_F3R1_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F3R1_FB20 CAN_F3R1_FB20_Msk /*!< Filter bit 20 */
+#define CAN_F3R1_FB21_Pos (21U)
+#define CAN_F3R1_FB21_Msk (0x1U << CAN_F3R1_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F3R1_FB21 CAN_F3R1_FB21_Msk /*!< Filter bit 21 */
+#define CAN_F3R1_FB22_Pos (22U)
+#define CAN_F3R1_FB22_Msk (0x1U << CAN_F3R1_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F3R1_FB22 CAN_F3R1_FB22_Msk /*!< Filter bit 22 */
+#define CAN_F3R1_FB23_Pos (23U)
+#define CAN_F3R1_FB23_Msk (0x1U << CAN_F3R1_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F3R1_FB23 CAN_F3R1_FB23_Msk /*!< Filter bit 23 */
+#define CAN_F3R1_FB24_Pos (24U)
+#define CAN_F3R1_FB24_Msk (0x1U << CAN_F3R1_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F3R1_FB24 CAN_F3R1_FB24_Msk /*!< Filter bit 24 */
+#define CAN_F3R1_FB25_Pos (25U)
+#define CAN_F3R1_FB25_Msk (0x1U << CAN_F3R1_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F3R1_FB25 CAN_F3R1_FB25_Msk /*!< Filter bit 25 */
+#define CAN_F3R1_FB26_Pos (26U)
+#define CAN_F3R1_FB26_Msk (0x1U << CAN_F3R1_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F3R1_FB26 CAN_F3R1_FB26_Msk /*!< Filter bit 26 */
+#define CAN_F3R1_FB27_Pos (27U)
+#define CAN_F3R1_FB27_Msk (0x1U << CAN_F3R1_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F3R1_FB27 CAN_F3R1_FB27_Msk /*!< Filter bit 27 */
+#define CAN_F3R1_FB28_Pos (28U)
+#define CAN_F3R1_FB28_Msk (0x1U << CAN_F3R1_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F3R1_FB28 CAN_F3R1_FB28_Msk /*!< Filter bit 28 */
+#define CAN_F3R1_FB29_Pos (29U)
+#define CAN_F3R1_FB29_Msk (0x1U << CAN_F3R1_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F3R1_FB29 CAN_F3R1_FB29_Msk /*!< Filter bit 29 */
+#define CAN_F3R1_FB30_Pos (30U)
+#define CAN_F3R1_FB30_Msk (0x1U << CAN_F3R1_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F3R1_FB30 CAN_F3R1_FB30_Msk /*!< Filter bit 30 */
+#define CAN_F3R1_FB31_Pos (31U)
+#define CAN_F3R1_FB31_Msk (0x1U << CAN_F3R1_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F3R1_FB31 CAN_F3R1_FB31_Msk /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F4R1 register *******************/
+#define CAN_F4R1_FB0_Pos (0U)
+#define CAN_F4R1_FB0_Msk (0x1U << CAN_F4R1_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F4R1_FB0 CAN_F4R1_FB0_Msk /*!< Filter bit 0 */
+#define CAN_F4R1_FB1_Pos (1U)
+#define CAN_F4R1_FB1_Msk (0x1U << CAN_F4R1_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F4R1_FB1 CAN_F4R1_FB1_Msk /*!< Filter bit 1 */
+#define CAN_F4R1_FB2_Pos (2U)
+#define CAN_F4R1_FB2_Msk (0x1U << CAN_F4R1_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F4R1_FB2 CAN_F4R1_FB2_Msk /*!< Filter bit 2 */
+#define CAN_F4R1_FB3_Pos (3U)
+#define CAN_F4R1_FB3_Msk (0x1U << CAN_F4R1_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F4R1_FB3 CAN_F4R1_FB3_Msk /*!< Filter bit 3 */
+#define CAN_F4R1_FB4_Pos (4U)
+#define CAN_F4R1_FB4_Msk (0x1U << CAN_F4R1_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F4R1_FB4 CAN_F4R1_FB4_Msk /*!< Filter bit 4 */
+#define CAN_F4R1_FB5_Pos (5U)
+#define CAN_F4R1_FB5_Msk (0x1U << CAN_F4R1_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F4R1_FB5 CAN_F4R1_FB5_Msk /*!< Filter bit 5 */
+#define CAN_F4R1_FB6_Pos (6U)
+#define CAN_F4R1_FB6_Msk (0x1U << CAN_F4R1_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F4R1_FB6 CAN_F4R1_FB6_Msk /*!< Filter bit 6 */
+#define CAN_F4R1_FB7_Pos (7U)
+#define CAN_F4R1_FB7_Msk (0x1U << CAN_F4R1_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F4R1_FB7 CAN_F4R1_FB7_Msk /*!< Filter bit 7 */
+#define CAN_F4R1_FB8_Pos (8U)
+#define CAN_F4R1_FB8_Msk (0x1U << CAN_F4R1_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F4R1_FB8 CAN_F4R1_FB8_Msk /*!< Filter bit 8 */
+#define CAN_F4R1_FB9_Pos (9U)
+#define CAN_F4R1_FB9_Msk (0x1U << CAN_F4R1_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F4R1_FB9 CAN_F4R1_FB9_Msk /*!< Filter bit 9 */
+#define CAN_F4R1_FB10_Pos (10U)
+#define CAN_F4R1_FB10_Msk (0x1U << CAN_F4R1_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F4R1_FB10 CAN_F4R1_FB10_Msk /*!< Filter bit 10 */
+#define CAN_F4R1_FB11_Pos (11U)
+#define CAN_F4R1_FB11_Msk (0x1U << CAN_F4R1_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F4R1_FB11 CAN_F4R1_FB11_Msk /*!< Filter bit 11 */
+#define CAN_F4R1_FB12_Pos (12U)
+#define CAN_F4R1_FB12_Msk (0x1U << CAN_F4R1_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F4R1_FB12 CAN_F4R1_FB12_Msk /*!< Filter bit 12 */
+#define CAN_F4R1_FB13_Pos (13U)
+#define CAN_F4R1_FB13_Msk (0x1U << CAN_F4R1_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F4R1_FB13 CAN_F4R1_FB13_Msk /*!< Filter bit 13 */
+#define CAN_F4R1_FB14_Pos (14U)
+#define CAN_F4R1_FB14_Msk (0x1U << CAN_F4R1_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F4R1_FB14 CAN_F4R1_FB14_Msk /*!< Filter bit 14 */
+#define CAN_F4R1_FB15_Pos (15U)
+#define CAN_F4R1_FB15_Msk (0x1U << CAN_F4R1_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F4R1_FB15 CAN_F4R1_FB15_Msk /*!< Filter bit 15 */
+#define CAN_F4R1_FB16_Pos (16U)
+#define CAN_F4R1_FB16_Msk (0x1U << CAN_F4R1_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F4R1_FB16 CAN_F4R1_FB16_Msk /*!< Filter bit 16 */
+#define CAN_F4R1_FB17_Pos (17U)
+#define CAN_F4R1_FB17_Msk (0x1U << CAN_F4R1_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F4R1_FB17 CAN_F4R1_FB17_Msk /*!< Filter bit 17 */
+#define CAN_F4R1_FB18_Pos (18U)
+#define CAN_F4R1_FB18_Msk (0x1U << CAN_F4R1_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F4R1_FB18 CAN_F4R1_FB18_Msk /*!< Filter bit 18 */
+#define CAN_F4R1_FB19_Pos (19U)
+#define CAN_F4R1_FB19_Msk (0x1U << CAN_F4R1_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F4R1_FB19 CAN_F4R1_FB19_Msk /*!< Filter bit 19 */
+#define CAN_F4R1_FB20_Pos (20U)
+#define CAN_F4R1_FB20_Msk (0x1U << CAN_F4R1_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F4R1_FB20 CAN_F4R1_FB20_Msk /*!< Filter bit 20 */
+#define CAN_F4R1_FB21_Pos (21U)
+#define CAN_F4R1_FB21_Msk (0x1U << CAN_F4R1_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F4R1_FB21 CAN_F4R1_FB21_Msk /*!< Filter bit 21 */
+#define CAN_F4R1_FB22_Pos (22U)
+#define CAN_F4R1_FB22_Msk (0x1U << CAN_F4R1_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F4R1_FB22 CAN_F4R1_FB22_Msk /*!< Filter bit 22 */
+#define CAN_F4R1_FB23_Pos (23U)
+#define CAN_F4R1_FB23_Msk (0x1U << CAN_F4R1_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F4R1_FB23 CAN_F4R1_FB23_Msk /*!< Filter bit 23 */
+#define CAN_F4R1_FB24_Pos (24U)
+#define CAN_F4R1_FB24_Msk (0x1U << CAN_F4R1_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F4R1_FB24 CAN_F4R1_FB24_Msk /*!< Filter bit 24 */
+#define CAN_F4R1_FB25_Pos (25U)
+#define CAN_F4R1_FB25_Msk (0x1U << CAN_F4R1_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F4R1_FB25 CAN_F4R1_FB25_Msk /*!< Filter bit 25 */
+#define CAN_F4R1_FB26_Pos (26U)
+#define CAN_F4R1_FB26_Msk (0x1U << CAN_F4R1_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F4R1_FB26 CAN_F4R1_FB26_Msk /*!< Filter bit 26 */
+#define CAN_F4R1_FB27_Pos (27U)
+#define CAN_F4R1_FB27_Msk (0x1U << CAN_F4R1_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F4R1_FB27 CAN_F4R1_FB27_Msk /*!< Filter bit 27 */
+#define CAN_F4R1_FB28_Pos (28U)
+#define CAN_F4R1_FB28_Msk (0x1U << CAN_F4R1_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F4R1_FB28 CAN_F4R1_FB28_Msk /*!< Filter bit 28 */
+#define CAN_F4R1_FB29_Pos (29U)
+#define CAN_F4R1_FB29_Msk (0x1U << CAN_F4R1_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F4R1_FB29 CAN_F4R1_FB29_Msk /*!< Filter bit 29 */
+#define CAN_F4R1_FB30_Pos (30U)
+#define CAN_F4R1_FB30_Msk (0x1U << CAN_F4R1_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F4R1_FB30 CAN_F4R1_FB30_Msk /*!< Filter bit 30 */
+#define CAN_F4R1_FB31_Pos (31U)
+#define CAN_F4R1_FB31_Msk (0x1U << CAN_F4R1_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F4R1_FB31 CAN_F4R1_FB31_Msk /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F5R1 register *******************/
+#define CAN_F5R1_FB0_Pos (0U)
+#define CAN_F5R1_FB0_Msk (0x1U << CAN_F5R1_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F5R1_FB0 CAN_F5R1_FB0_Msk /*!< Filter bit 0 */
+#define CAN_F5R1_FB1_Pos (1U)
+#define CAN_F5R1_FB1_Msk (0x1U << CAN_F5R1_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F5R1_FB1 CAN_F5R1_FB1_Msk /*!< Filter bit 1 */
+#define CAN_F5R1_FB2_Pos (2U)
+#define CAN_F5R1_FB2_Msk (0x1U << CAN_F5R1_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F5R1_FB2 CAN_F5R1_FB2_Msk /*!< Filter bit 2 */
+#define CAN_F5R1_FB3_Pos (3U)
+#define CAN_F5R1_FB3_Msk (0x1U << CAN_F5R1_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F5R1_FB3 CAN_F5R1_FB3_Msk /*!< Filter bit 3 */
+#define CAN_F5R1_FB4_Pos (4U)
+#define CAN_F5R1_FB4_Msk (0x1U << CAN_F5R1_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F5R1_FB4 CAN_F5R1_FB4_Msk /*!< Filter bit 4 */
+#define CAN_F5R1_FB5_Pos (5U)
+#define CAN_F5R1_FB5_Msk (0x1U << CAN_F5R1_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F5R1_FB5 CAN_F5R1_FB5_Msk /*!< Filter bit 5 */
+#define CAN_F5R1_FB6_Pos (6U)
+#define CAN_F5R1_FB6_Msk (0x1U << CAN_F5R1_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F5R1_FB6 CAN_F5R1_FB6_Msk /*!< Filter bit 6 */
+#define CAN_F5R1_FB7_Pos (7U)
+#define CAN_F5R1_FB7_Msk (0x1U << CAN_F5R1_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F5R1_FB7 CAN_F5R1_FB7_Msk /*!< Filter bit 7 */
+#define CAN_F5R1_FB8_Pos (8U)
+#define CAN_F5R1_FB8_Msk (0x1U << CAN_F5R1_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F5R1_FB8 CAN_F5R1_FB8_Msk /*!< Filter bit 8 */
+#define CAN_F5R1_FB9_Pos (9U)
+#define CAN_F5R1_FB9_Msk (0x1U << CAN_F5R1_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F5R1_FB9 CAN_F5R1_FB9_Msk /*!< Filter bit 9 */
+#define CAN_F5R1_FB10_Pos (10U)
+#define CAN_F5R1_FB10_Msk (0x1U << CAN_F5R1_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F5R1_FB10 CAN_F5R1_FB10_Msk /*!< Filter bit 10 */
+#define CAN_F5R1_FB11_Pos (11U)
+#define CAN_F5R1_FB11_Msk (0x1U << CAN_F5R1_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F5R1_FB11 CAN_F5R1_FB11_Msk /*!< Filter bit 11 */
+#define CAN_F5R1_FB12_Pos (12U)
+#define CAN_F5R1_FB12_Msk (0x1U << CAN_F5R1_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F5R1_FB12 CAN_F5R1_FB12_Msk /*!< Filter bit 12 */
+#define CAN_F5R1_FB13_Pos (13U)
+#define CAN_F5R1_FB13_Msk (0x1U << CAN_F5R1_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F5R1_FB13 CAN_F5R1_FB13_Msk /*!< Filter bit 13 */
+#define CAN_F5R1_FB14_Pos (14U)
+#define CAN_F5R1_FB14_Msk (0x1U << CAN_F5R1_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F5R1_FB14 CAN_F5R1_FB14_Msk /*!< Filter bit 14 */
+#define CAN_F5R1_FB15_Pos (15U)
+#define CAN_F5R1_FB15_Msk (0x1U << CAN_F5R1_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F5R1_FB15 CAN_F5R1_FB15_Msk /*!< Filter bit 15 */
+#define CAN_F5R1_FB16_Pos (16U)
+#define CAN_F5R1_FB16_Msk (0x1U << CAN_F5R1_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F5R1_FB16 CAN_F5R1_FB16_Msk /*!< Filter bit 16 */
+#define CAN_F5R1_FB17_Pos (17U)
+#define CAN_F5R1_FB17_Msk (0x1U << CAN_F5R1_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F5R1_FB17 CAN_F5R1_FB17_Msk /*!< Filter bit 17 */
+#define CAN_F5R1_FB18_Pos (18U)
+#define CAN_F5R1_FB18_Msk (0x1U << CAN_F5R1_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F5R1_FB18 CAN_F5R1_FB18_Msk /*!< Filter bit 18 */
+#define CAN_F5R1_FB19_Pos (19U)
+#define CAN_F5R1_FB19_Msk (0x1U << CAN_F5R1_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F5R1_FB19 CAN_F5R1_FB19_Msk /*!< Filter bit 19 */
+#define CAN_F5R1_FB20_Pos (20U)
+#define CAN_F5R1_FB20_Msk (0x1U << CAN_F5R1_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F5R1_FB20 CAN_F5R1_FB20_Msk /*!< Filter bit 20 */
+#define CAN_F5R1_FB21_Pos (21U)
+#define CAN_F5R1_FB21_Msk (0x1U << CAN_F5R1_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F5R1_FB21 CAN_F5R1_FB21_Msk /*!< Filter bit 21 */
+#define CAN_F5R1_FB22_Pos (22U)
+#define CAN_F5R1_FB22_Msk (0x1U << CAN_F5R1_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F5R1_FB22 CAN_F5R1_FB22_Msk /*!< Filter bit 22 */
+#define CAN_F5R1_FB23_Pos (23U)
+#define CAN_F5R1_FB23_Msk (0x1U << CAN_F5R1_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F5R1_FB23 CAN_F5R1_FB23_Msk /*!< Filter bit 23 */
+#define CAN_F5R1_FB24_Pos (24U)
+#define CAN_F5R1_FB24_Msk (0x1U << CAN_F5R1_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F5R1_FB24 CAN_F5R1_FB24_Msk /*!< Filter bit 24 */
+#define CAN_F5R1_FB25_Pos (25U)
+#define CAN_F5R1_FB25_Msk (0x1U << CAN_F5R1_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F5R1_FB25 CAN_F5R1_FB25_Msk /*!< Filter bit 25 */
+#define CAN_F5R1_FB26_Pos (26U)
+#define CAN_F5R1_FB26_Msk (0x1U << CAN_F5R1_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F5R1_FB26 CAN_F5R1_FB26_Msk /*!< Filter bit 26 */
+#define CAN_F5R1_FB27_Pos (27U)
+#define CAN_F5R1_FB27_Msk (0x1U << CAN_F5R1_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F5R1_FB27 CAN_F5R1_FB27_Msk /*!< Filter bit 27 */
+#define CAN_F5R1_FB28_Pos (28U)
+#define CAN_F5R1_FB28_Msk (0x1U << CAN_F5R1_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F5R1_FB28 CAN_F5R1_FB28_Msk /*!< Filter bit 28 */
+#define CAN_F5R1_FB29_Pos (29U)
+#define CAN_F5R1_FB29_Msk (0x1U << CAN_F5R1_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F5R1_FB29 CAN_F5R1_FB29_Msk /*!< Filter bit 29 */
+#define CAN_F5R1_FB30_Pos (30U)
+#define CAN_F5R1_FB30_Msk (0x1U << CAN_F5R1_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F5R1_FB30 CAN_F5R1_FB30_Msk /*!< Filter bit 30 */
+#define CAN_F5R1_FB31_Pos (31U)
+#define CAN_F5R1_FB31_Msk (0x1U << CAN_F5R1_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F5R1_FB31 CAN_F5R1_FB31_Msk /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F6R1 register *******************/
+#define CAN_F6R1_FB0_Pos (0U)
+#define CAN_F6R1_FB0_Msk (0x1U << CAN_F6R1_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F6R1_FB0 CAN_F6R1_FB0_Msk /*!< Filter bit 0 */
+#define CAN_F6R1_FB1_Pos (1U)
+#define CAN_F6R1_FB1_Msk (0x1U << CAN_F6R1_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F6R1_FB1 CAN_F6R1_FB1_Msk /*!< Filter bit 1 */
+#define CAN_F6R1_FB2_Pos (2U)
+#define CAN_F6R1_FB2_Msk (0x1U << CAN_F6R1_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F6R1_FB2 CAN_F6R1_FB2_Msk /*!< Filter bit 2 */
+#define CAN_F6R1_FB3_Pos (3U)
+#define CAN_F6R1_FB3_Msk (0x1U << CAN_F6R1_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F6R1_FB3 CAN_F6R1_FB3_Msk /*!< Filter bit 3 */
+#define CAN_F6R1_FB4_Pos (4U)
+#define CAN_F6R1_FB4_Msk (0x1U << CAN_F6R1_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F6R1_FB4 CAN_F6R1_FB4_Msk /*!< Filter bit 4 */
+#define CAN_F6R1_FB5_Pos (5U)
+#define CAN_F6R1_FB5_Msk (0x1U << CAN_F6R1_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F6R1_FB5 CAN_F6R1_FB5_Msk /*!< Filter bit 5 */
+#define CAN_F6R1_FB6_Pos (6U)
+#define CAN_F6R1_FB6_Msk (0x1U << CAN_F6R1_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F6R1_FB6 CAN_F6R1_FB6_Msk /*!< Filter bit 6 */
+#define CAN_F6R1_FB7_Pos (7U)
+#define CAN_F6R1_FB7_Msk (0x1U << CAN_F6R1_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F6R1_FB7 CAN_F6R1_FB7_Msk /*!< Filter bit 7 */
+#define CAN_F6R1_FB8_Pos (8U)
+#define CAN_F6R1_FB8_Msk (0x1U << CAN_F6R1_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F6R1_FB8 CAN_F6R1_FB8_Msk /*!< Filter bit 8 */
+#define CAN_F6R1_FB9_Pos (9U)
+#define CAN_F6R1_FB9_Msk (0x1U << CAN_F6R1_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F6R1_FB9 CAN_F6R1_FB9_Msk /*!< Filter bit 9 */
+#define CAN_F6R1_FB10_Pos (10U)
+#define CAN_F6R1_FB10_Msk (0x1U << CAN_F6R1_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F6R1_FB10 CAN_F6R1_FB10_Msk /*!< Filter bit 10 */
+#define CAN_F6R1_FB11_Pos (11U)
+#define CAN_F6R1_FB11_Msk (0x1U << CAN_F6R1_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F6R1_FB11 CAN_F6R1_FB11_Msk /*!< Filter bit 11 */
+#define CAN_F6R1_FB12_Pos (12U)
+#define CAN_F6R1_FB12_Msk (0x1U << CAN_F6R1_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F6R1_FB12 CAN_F6R1_FB12_Msk /*!< Filter bit 12 */
+#define CAN_F6R1_FB13_Pos (13U)
+#define CAN_F6R1_FB13_Msk (0x1U << CAN_F6R1_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F6R1_FB13 CAN_F6R1_FB13_Msk /*!< Filter bit 13 */
+#define CAN_F6R1_FB14_Pos (14U)
+#define CAN_F6R1_FB14_Msk (0x1U << CAN_F6R1_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F6R1_FB14 CAN_F6R1_FB14_Msk /*!< Filter bit 14 */
+#define CAN_F6R1_FB15_Pos (15U)
+#define CAN_F6R1_FB15_Msk (0x1U << CAN_F6R1_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F6R1_FB15 CAN_F6R1_FB15_Msk /*!< Filter bit 15 */
+#define CAN_F6R1_FB16_Pos (16U)
+#define CAN_F6R1_FB16_Msk (0x1U << CAN_F6R1_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F6R1_FB16 CAN_F6R1_FB16_Msk /*!< Filter bit 16 */
+#define CAN_F6R1_FB17_Pos (17U)
+#define CAN_F6R1_FB17_Msk (0x1U << CAN_F6R1_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F6R1_FB17 CAN_F6R1_FB17_Msk /*!< Filter bit 17 */
+#define CAN_F6R1_FB18_Pos (18U)
+#define CAN_F6R1_FB18_Msk (0x1U << CAN_F6R1_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F6R1_FB18 CAN_F6R1_FB18_Msk /*!< Filter bit 18 */
+#define CAN_F6R1_FB19_Pos (19U)
+#define CAN_F6R1_FB19_Msk (0x1U << CAN_F6R1_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F6R1_FB19 CAN_F6R1_FB19_Msk /*!< Filter bit 19 */
+#define CAN_F6R1_FB20_Pos (20U)
+#define CAN_F6R1_FB20_Msk (0x1U << CAN_F6R1_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F6R1_FB20 CAN_F6R1_FB20_Msk /*!< Filter bit 20 */
+#define CAN_F6R1_FB21_Pos (21U)
+#define CAN_F6R1_FB21_Msk (0x1U << CAN_F6R1_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F6R1_FB21 CAN_F6R1_FB21_Msk /*!< Filter bit 21 */
+#define CAN_F6R1_FB22_Pos (22U)
+#define CAN_F6R1_FB22_Msk (0x1U << CAN_F6R1_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F6R1_FB22 CAN_F6R1_FB22_Msk /*!< Filter bit 22 */
+#define CAN_F6R1_FB23_Pos (23U)
+#define CAN_F6R1_FB23_Msk (0x1U << CAN_F6R1_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F6R1_FB23 CAN_F6R1_FB23_Msk /*!< Filter bit 23 */
+#define CAN_F6R1_FB24_Pos (24U)
+#define CAN_F6R1_FB24_Msk (0x1U << CAN_F6R1_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F6R1_FB24 CAN_F6R1_FB24_Msk /*!< Filter bit 24 */
+#define CAN_F6R1_FB25_Pos (25U)
+#define CAN_F6R1_FB25_Msk (0x1U << CAN_F6R1_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F6R1_FB25 CAN_F6R1_FB25_Msk /*!< Filter bit 25 */
+#define CAN_F6R1_FB26_Pos (26U)
+#define CAN_F6R1_FB26_Msk (0x1U << CAN_F6R1_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F6R1_FB26 CAN_F6R1_FB26_Msk /*!< Filter bit 26 */
+#define CAN_F6R1_FB27_Pos (27U)
+#define CAN_F6R1_FB27_Msk (0x1U << CAN_F6R1_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F6R1_FB27 CAN_F6R1_FB27_Msk /*!< Filter bit 27 */
+#define CAN_F6R1_FB28_Pos (28U)
+#define CAN_F6R1_FB28_Msk (0x1U << CAN_F6R1_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F6R1_FB28 CAN_F6R1_FB28_Msk /*!< Filter bit 28 */
+#define CAN_F6R1_FB29_Pos (29U)
+#define CAN_F6R1_FB29_Msk (0x1U << CAN_F6R1_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F6R1_FB29 CAN_F6R1_FB29_Msk /*!< Filter bit 29 */
+#define CAN_F6R1_FB30_Pos (30U)
+#define CAN_F6R1_FB30_Msk (0x1U << CAN_F6R1_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F6R1_FB30 CAN_F6R1_FB30_Msk /*!< Filter bit 30 */
+#define CAN_F6R1_FB31_Pos (31U)
+#define CAN_F6R1_FB31_Msk (0x1U << CAN_F6R1_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F6R1_FB31 CAN_F6R1_FB31_Msk /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F7R1 register *******************/
+#define CAN_F7R1_FB0_Pos (0U)
+#define CAN_F7R1_FB0_Msk (0x1U << CAN_F7R1_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F7R1_FB0 CAN_F7R1_FB0_Msk /*!< Filter bit 0 */
+#define CAN_F7R1_FB1_Pos (1U)
+#define CAN_F7R1_FB1_Msk (0x1U << CAN_F7R1_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F7R1_FB1 CAN_F7R1_FB1_Msk /*!< Filter bit 1 */
+#define CAN_F7R1_FB2_Pos (2U)
+#define CAN_F7R1_FB2_Msk (0x1U << CAN_F7R1_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F7R1_FB2 CAN_F7R1_FB2_Msk /*!< Filter bit 2 */
+#define CAN_F7R1_FB3_Pos (3U)
+#define CAN_F7R1_FB3_Msk (0x1U << CAN_F7R1_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F7R1_FB3 CAN_F7R1_FB3_Msk /*!< Filter bit 3 */
+#define CAN_F7R1_FB4_Pos (4U)
+#define CAN_F7R1_FB4_Msk (0x1U << CAN_F7R1_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F7R1_FB4 CAN_F7R1_FB4_Msk /*!< Filter bit 4 */
+#define CAN_F7R1_FB5_Pos (5U)
+#define CAN_F7R1_FB5_Msk (0x1U << CAN_F7R1_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F7R1_FB5 CAN_F7R1_FB5_Msk /*!< Filter bit 5 */
+#define CAN_F7R1_FB6_Pos (6U)
+#define CAN_F7R1_FB6_Msk (0x1U << CAN_F7R1_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F7R1_FB6 CAN_F7R1_FB6_Msk /*!< Filter bit 6 */
+#define CAN_F7R1_FB7_Pos (7U)
+#define CAN_F7R1_FB7_Msk (0x1U << CAN_F7R1_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F7R1_FB7 CAN_F7R1_FB7_Msk /*!< Filter bit 7 */
+#define CAN_F7R1_FB8_Pos (8U)
+#define CAN_F7R1_FB8_Msk (0x1U << CAN_F7R1_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F7R1_FB8 CAN_F7R1_FB8_Msk /*!< Filter bit 8 */
+#define CAN_F7R1_FB9_Pos (9U)
+#define CAN_F7R1_FB9_Msk (0x1U << CAN_F7R1_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F7R1_FB9 CAN_F7R1_FB9_Msk /*!< Filter bit 9 */
+#define CAN_F7R1_FB10_Pos (10U)
+#define CAN_F7R1_FB10_Msk (0x1U << CAN_F7R1_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F7R1_FB10 CAN_F7R1_FB10_Msk /*!< Filter bit 10 */
+#define CAN_F7R1_FB11_Pos (11U)
+#define CAN_F7R1_FB11_Msk (0x1U << CAN_F7R1_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F7R1_FB11 CAN_F7R1_FB11_Msk /*!< Filter bit 11 */
+#define CAN_F7R1_FB12_Pos (12U)
+#define CAN_F7R1_FB12_Msk (0x1U << CAN_F7R1_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F7R1_FB12 CAN_F7R1_FB12_Msk /*!< Filter bit 12 */
+#define CAN_F7R1_FB13_Pos (13U)
+#define CAN_F7R1_FB13_Msk (0x1U << CAN_F7R1_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F7R1_FB13 CAN_F7R1_FB13_Msk /*!< Filter bit 13 */
+#define CAN_F7R1_FB14_Pos (14U)
+#define CAN_F7R1_FB14_Msk (0x1U << CAN_F7R1_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F7R1_FB14 CAN_F7R1_FB14_Msk /*!< Filter bit 14 */
+#define CAN_F7R1_FB15_Pos (15U)
+#define CAN_F7R1_FB15_Msk (0x1U << CAN_F7R1_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F7R1_FB15 CAN_F7R1_FB15_Msk /*!< Filter bit 15 */
+#define CAN_F7R1_FB16_Pos (16U)
+#define CAN_F7R1_FB16_Msk (0x1U << CAN_F7R1_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F7R1_FB16 CAN_F7R1_FB16_Msk /*!< Filter bit 16 */
+#define CAN_F7R1_FB17_Pos (17U)
+#define CAN_F7R1_FB17_Msk (0x1U << CAN_F7R1_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F7R1_FB17 CAN_F7R1_FB17_Msk /*!< Filter bit 17 */
+#define CAN_F7R1_FB18_Pos (18U)
+#define CAN_F7R1_FB18_Msk (0x1U << CAN_F7R1_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F7R1_FB18 CAN_F7R1_FB18_Msk /*!< Filter bit 18 */
+#define CAN_F7R1_FB19_Pos (19U)
+#define CAN_F7R1_FB19_Msk (0x1U << CAN_F7R1_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F7R1_FB19 CAN_F7R1_FB19_Msk /*!< Filter bit 19 */
+#define CAN_F7R1_FB20_Pos (20U)
+#define CAN_F7R1_FB20_Msk (0x1U << CAN_F7R1_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F7R1_FB20 CAN_F7R1_FB20_Msk /*!< Filter bit 20 */
+#define CAN_F7R1_FB21_Pos (21U)
+#define CAN_F7R1_FB21_Msk (0x1U << CAN_F7R1_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F7R1_FB21 CAN_F7R1_FB21_Msk /*!< Filter bit 21 */
+#define CAN_F7R1_FB22_Pos (22U)
+#define CAN_F7R1_FB22_Msk (0x1U << CAN_F7R1_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F7R1_FB22 CAN_F7R1_FB22_Msk /*!< Filter bit 22 */
+#define CAN_F7R1_FB23_Pos (23U)
+#define CAN_F7R1_FB23_Msk (0x1U << CAN_F7R1_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F7R1_FB23 CAN_F7R1_FB23_Msk /*!< Filter bit 23 */
+#define CAN_F7R1_FB24_Pos (24U)
+#define CAN_F7R1_FB24_Msk (0x1U << CAN_F7R1_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F7R1_FB24 CAN_F7R1_FB24_Msk /*!< Filter bit 24 */
+#define CAN_F7R1_FB25_Pos (25U)
+#define CAN_F7R1_FB25_Msk (0x1U << CAN_F7R1_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F7R1_FB25 CAN_F7R1_FB25_Msk /*!< Filter bit 25 */
+#define CAN_F7R1_FB26_Pos (26U)
+#define CAN_F7R1_FB26_Msk (0x1U << CAN_F7R1_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F7R1_FB26 CAN_F7R1_FB26_Msk /*!< Filter bit 26 */
+#define CAN_F7R1_FB27_Pos (27U)
+#define CAN_F7R1_FB27_Msk (0x1U << CAN_F7R1_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F7R1_FB27 CAN_F7R1_FB27_Msk /*!< Filter bit 27 */
+#define CAN_F7R1_FB28_Pos (28U)
+#define CAN_F7R1_FB28_Msk (0x1U << CAN_F7R1_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F7R1_FB28 CAN_F7R1_FB28_Msk /*!< Filter bit 28 */
+#define CAN_F7R1_FB29_Pos (29U)
+#define CAN_F7R1_FB29_Msk (0x1U << CAN_F7R1_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F7R1_FB29 CAN_F7R1_FB29_Msk /*!< Filter bit 29 */
+#define CAN_F7R1_FB30_Pos (30U)
+#define CAN_F7R1_FB30_Msk (0x1U << CAN_F7R1_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F7R1_FB30 CAN_F7R1_FB30_Msk /*!< Filter bit 30 */
+#define CAN_F7R1_FB31_Pos (31U)
+#define CAN_F7R1_FB31_Msk (0x1U << CAN_F7R1_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F7R1_FB31 CAN_F7R1_FB31_Msk /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F8R1 register *******************/
+#define CAN_F8R1_FB0_Pos (0U)
+#define CAN_F8R1_FB0_Msk (0x1U << CAN_F8R1_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F8R1_FB0 CAN_F8R1_FB0_Msk /*!< Filter bit 0 */
+#define CAN_F8R1_FB1_Pos (1U)
+#define CAN_F8R1_FB1_Msk (0x1U << CAN_F8R1_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F8R1_FB1 CAN_F8R1_FB1_Msk /*!< Filter bit 1 */
+#define CAN_F8R1_FB2_Pos (2U)
+#define CAN_F8R1_FB2_Msk (0x1U << CAN_F8R1_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F8R1_FB2 CAN_F8R1_FB2_Msk /*!< Filter bit 2 */
+#define CAN_F8R1_FB3_Pos (3U)
+#define CAN_F8R1_FB3_Msk (0x1U << CAN_F8R1_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F8R1_FB3 CAN_F8R1_FB3_Msk /*!< Filter bit 3 */
+#define CAN_F8R1_FB4_Pos (4U)
+#define CAN_F8R1_FB4_Msk (0x1U << CAN_F8R1_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F8R1_FB4 CAN_F8R1_FB4_Msk /*!< Filter bit 4 */
+#define CAN_F8R1_FB5_Pos (5U)
+#define CAN_F8R1_FB5_Msk (0x1U << CAN_F8R1_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F8R1_FB5 CAN_F8R1_FB5_Msk /*!< Filter bit 5 */
+#define CAN_F8R1_FB6_Pos (6U)
+#define CAN_F8R1_FB6_Msk (0x1U << CAN_F8R1_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F8R1_FB6 CAN_F8R1_FB6_Msk /*!< Filter bit 6 */
+#define CAN_F8R1_FB7_Pos (7U)
+#define CAN_F8R1_FB7_Msk (0x1U << CAN_F8R1_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F8R1_FB7 CAN_F8R1_FB7_Msk /*!< Filter bit 7 */
+#define CAN_F8R1_FB8_Pos (8U)
+#define CAN_F8R1_FB8_Msk (0x1U << CAN_F8R1_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F8R1_FB8 CAN_F8R1_FB8_Msk /*!< Filter bit 8 */
+#define CAN_F8R1_FB9_Pos (9U)
+#define CAN_F8R1_FB9_Msk (0x1U << CAN_F8R1_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F8R1_FB9 CAN_F8R1_FB9_Msk /*!< Filter bit 9 */
+#define CAN_F8R1_FB10_Pos (10U)
+#define CAN_F8R1_FB10_Msk (0x1U << CAN_F8R1_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F8R1_FB10 CAN_F8R1_FB10_Msk /*!< Filter bit 10 */
+#define CAN_F8R1_FB11_Pos (11U)
+#define CAN_F8R1_FB11_Msk (0x1U << CAN_F8R1_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F8R1_FB11 CAN_F8R1_FB11_Msk /*!< Filter bit 11 */
+#define CAN_F8R1_FB12_Pos (12U)
+#define CAN_F8R1_FB12_Msk (0x1U << CAN_F8R1_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F8R1_FB12 CAN_F8R1_FB12_Msk /*!< Filter bit 12 */
+#define CAN_F8R1_FB13_Pos (13U)
+#define CAN_F8R1_FB13_Msk (0x1U << CAN_F8R1_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F8R1_FB13 CAN_F8R1_FB13_Msk /*!< Filter bit 13 */
+#define CAN_F8R1_FB14_Pos (14U)
+#define CAN_F8R1_FB14_Msk (0x1U << CAN_F8R1_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F8R1_FB14 CAN_F8R1_FB14_Msk /*!< Filter bit 14 */
+#define CAN_F8R1_FB15_Pos (15U)
+#define CAN_F8R1_FB15_Msk (0x1U << CAN_F8R1_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F8R1_FB15 CAN_F8R1_FB15_Msk /*!< Filter bit 15 */
+#define CAN_F8R1_FB16_Pos (16U)
+#define CAN_F8R1_FB16_Msk (0x1U << CAN_F8R1_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F8R1_FB16 CAN_F8R1_FB16_Msk /*!< Filter bit 16 */
+#define CAN_F8R1_FB17_Pos (17U)
+#define CAN_F8R1_FB17_Msk (0x1U << CAN_F8R1_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F8R1_FB17 CAN_F8R1_FB17_Msk /*!< Filter bit 17 */
+#define CAN_F8R1_FB18_Pos (18U)
+#define CAN_F8R1_FB18_Msk (0x1U << CAN_F8R1_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F8R1_FB18 CAN_F8R1_FB18_Msk /*!< Filter bit 18 */
+#define CAN_F8R1_FB19_Pos (19U)
+#define CAN_F8R1_FB19_Msk (0x1U << CAN_F8R1_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F8R1_FB19 CAN_F8R1_FB19_Msk /*!< Filter bit 19 */
+#define CAN_F8R1_FB20_Pos (20U)
+#define CAN_F8R1_FB20_Msk (0x1U << CAN_F8R1_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F8R1_FB20 CAN_F8R1_FB20_Msk /*!< Filter bit 20 */
+#define CAN_F8R1_FB21_Pos (21U)
+#define CAN_F8R1_FB21_Msk (0x1U << CAN_F8R1_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F8R1_FB21 CAN_F8R1_FB21_Msk /*!< Filter bit 21 */
+#define CAN_F8R1_FB22_Pos (22U)
+#define CAN_F8R1_FB22_Msk (0x1U << CAN_F8R1_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F8R1_FB22 CAN_F8R1_FB22_Msk /*!< Filter bit 22 */
+#define CAN_F8R1_FB23_Pos (23U)
+#define CAN_F8R1_FB23_Msk (0x1U << CAN_F8R1_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F8R1_FB23 CAN_F8R1_FB23_Msk /*!< Filter bit 23 */
+#define CAN_F8R1_FB24_Pos (24U)
+#define CAN_F8R1_FB24_Msk (0x1U << CAN_F8R1_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F8R1_FB24 CAN_F8R1_FB24_Msk /*!< Filter bit 24 */
+#define CAN_F8R1_FB25_Pos (25U)
+#define CAN_F8R1_FB25_Msk (0x1U << CAN_F8R1_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F8R1_FB25 CAN_F8R1_FB25_Msk /*!< Filter bit 25 */
+#define CAN_F8R1_FB26_Pos (26U)
+#define CAN_F8R1_FB26_Msk (0x1U << CAN_F8R1_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F8R1_FB26 CAN_F8R1_FB26_Msk /*!< Filter bit 26 */
+#define CAN_F8R1_FB27_Pos (27U)
+#define CAN_F8R1_FB27_Msk (0x1U << CAN_F8R1_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F8R1_FB27 CAN_F8R1_FB27_Msk /*!< Filter bit 27 */
+#define CAN_F8R1_FB28_Pos (28U)
+#define CAN_F8R1_FB28_Msk (0x1U << CAN_F8R1_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F8R1_FB28 CAN_F8R1_FB28_Msk /*!< Filter bit 28 */
+#define CAN_F8R1_FB29_Pos (29U)
+#define CAN_F8R1_FB29_Msk (0x1U << CAN_F8R1_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F8R1_FB29 CAN_F8R1_FB29_Msk /*!< Filter bit 29 */
+#define CAN_F8R1_FB30_Pos (30U)
+#define CAN_F8R1_FB30_Msk (0x1U << CAN_F8R1_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F8R1_FB30 CAN_F8R1_FB30_Msk /*!< Filter bit 30 */
+#define CAN_F8R1_FB31_Pos (31U)
+#define CAN_F8R1_FB31_Msk (0x1U << CAN_F8R1_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F8R1_FB31 CAN_F8R1_FB31_Msk /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F9R1 register *******************/
+#define CAN_F9R1_FB0_Pos (0U)
+#define CAN_F9R1_FB0_Msk (0x1U << CAN_F9R1_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F9R1_FB0 CAN_F9R1_FB0_Msk /*!< Filter bit 0 */
+#define CAN_F9R1_FB1_Pos (1U)
+#define CAN_F9R1_FB1_Msk (0x1U << CAN_F9R1_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F9R1_FB1 CAN_F9R1_FB1_Msk /*!< Filter bit 1 */
+#define CAN_F9R1_FB2_Pos (2U)
+#define CAN_F9R1_FB2_Msk (0x1U << CAN_F9R1_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F9R1_FB2 CAN_F9R1_FB2_Msk /*!< Filter bit 2 */
+#define CAN_F9R1_FB3_Pos (3U)
+#define CAN_F9R1_FB3_Msk (0x1U << CAN_F9R1_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F9R1_FB3 CAN_F9R1_FB3_Msk /*!< Filter bit 3 */
+#define CAN_F9R1_FB4_Pos (4U)
+#define CAN_F9R1_FB4_Msk (0x1U << CAN_F9R1_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F9R1_FB4 CAN_F9R1_FB4_Msk /*!< Filter bit 4 */
+#define CAN_F9R1_FB5_Pos (5U)
+#define CAN_F9R1_FB5_Msk (0x1U << CAN_F9R1_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F9R1_FB5 CAN_F9R1_FB5_Msk /*!< Filter bit 5 */
+#define CAN_F9R1_FB6_Pos (6U)
+#define CAN_F9R1_FB6_Msk (0x1U << CAN_F9R1_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F9R1_FB6 CAN_F9R1_FB6_Msk /*!< Filter bit 6 */
+#define CAN_F9R1_FB7_Pos (7U)
+#define CAN_F9R1_FB7_Msk (0x1U << CAN_F9R1_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F9R1_FB7 CAN_F9R1_FB7_Msk /*!< Filter bit 7 */
+#define CAN_F9R1_FB8_Pos (8U)
+#define CAN_F9R1_FB8_Msk (0x1U << CAN_F9R1_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F9R1_FB8 CAN_F9R1_FB8_Msk /*!< Filter bit 8 */
+#define CAN_F9R1_FB9_Pos (9U)
+#define CAN_F9R1_FB9_Msk (0x1U << CAN_F9R1_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F9R1_FB9 CAN_F9R1_FB9_Msk /*!< Filter bit 9 */
+#define CAN_F9R1_FB10_Pos (10U)
+#define CAN_F9R1_FB10_Msk (0x1U << CAN_F9R1_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F9R1_FB10 CAN_F9R1_FB10_Msk /*!< Filter bit 10 */
+#define CAN_F9R1_FB11_Pos (11U)
+#define CAN_F9R1_FB11_Msk (0x1U << CAN_F9R1_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F9R1_FB11 CAN_F9R1_FB11_Msk /*!< Filter bit 11 */
+#define CAN_F9R1_FB12_Pos (12U)
+#define CAN_F9R1_FB12_Msk (0x1U << CAN_F9R1_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F9R1_FB12 CAN_F9R1_FB12_Msk /*!< Filter bit 12 */
+#define CAN_F9R1_FB13_Pos (13U)
+#define CAN_F9R1_FB13_Msk (0x1U << CAN_F9R1_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F9R1_FB13 CAN_F9R1_FB13_Msk /*!< Filter bit 13 */
+#define CAN_F9R1_FB14_Pos (14U)
+#define CAN_F9R1_FB14_Msk (0x1U << CAN_F9R1_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F9R1_FB14 CAN_F9R1_FB14_Msk /*!< Filter bit 14 */
+#define CAN_F9R1_FB15_Pos (15U)
+#define CAN_F9R1_FB15_Msk (0x1U << CAN_F9R1_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F9R1_FB15 CAN_F9R1_FB15_Msk /*!< Filter bit 15 */
+#define CAN_F9R1_FB16_Pos (16U)
+#define CAN_F9R1_FB16_Msk (0x1U << CAN_F9R1_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F9R1_FB16 CAN_F9R1_FB16_Msk /*!< Filter bit 16 */
+#define CAN_F9R1_FB17_Pos (17U)
+#define CAN_F9R1_FB17_Msk (0x1U << CAN_F9R1_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F9R1_FB17 CAN_F9R1_FB17_Msk /*!< Filter bit 17 */
+#define CAN_F9R1_FB18_Pos (18U)
+#define CAN_F9R1_FB18_Msk (0x1U << CAN_F9R1_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F9R1_FB18 CAN_F9R1_FB18_Msk /*!< Filter bit 18 */
+#define CAN_F9R1_FB19_Pos (19U)
+#define CAN_F9R1_FB19_Msk (0x1U << CAN_F9R1_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F9R1_FB19 CAN_F9R1_FB19_Msk /*!< Filter bit 19 */
+#define CAN_F9R1_FB20_Pos (20U)
+#define CAN_F9R1_FB20_Msk (0x1U << CAN_F9R1_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F9R1_FB20 CAN_F9R1_FB20_Msk /*!< Filter bit 20 */
+#define CAN_F9R1_FB21_Pos (21U)
+#define CAN_F9R1_FB21_Msk (0x1U << CAN_F9R1_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F9R1_FB21 CAN_F9R1_FB21_Msk /*!< Filter bit 21 */
+#define CAN_F9R1_FB22_Pos (22U)
+#define CAN_F9R1_FB22_Msk (0x1U << CAN_F9R1_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F9R1_FB22 CAN_F9R1_FB22_Msk /*!< Filter bit 22 */
+#define CAN_F9R1_FB23_Pos (23U)
+#define CAN_F9R1_FB23_Msk (0x1U << CAN_F9R1_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F9R1_FB23 CAN_F9R1_FB23_Msk /*!< Filter bit 23 */
+#define CAN_F9R1_FB24_Pos (24U)
+#define CAN_F9R1_FB24_Msk (0x1U << CAN_F9R1_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F9R1_FB24 CAN_F9R1_FB24_Msk /*!< Filter bit 24 */
+#define CAN_F9R1_FB25_Pos (25U)
+#define CAN_F9R1_FB25_Msk (0x1U << CAN_F9R1_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F9R1_FB25 CAN_F9R1_FB25_Msk /*!< Filter bit 25 */
+#define CAN_F9R1_FB26_Pos (26U)
+#define CAN_F9R1_FB26_Msk (0x1U << CAN_F9R1_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F9R1_FB26 CAN_F9R1_FB26_Msk /*!< Filter bit 26 */
+#define CAN_F9R1_FB27_Pos (27U)
+#define CAN_F9R1_FB27_Msk (0x1U << CAN_F9R1_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F9R1_FB27 CAN_F9R1_FB27_Msk /*!< Filter bit 27 */
+#define CAN_F9R1_FB28_Pos (28U)
+#define CAN_F9R1_FB28_Msk (0x1U << CAN_F9R1_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F9R1_FB28 CAN_F9R1_FB28_Msk /*!< Filter bit 28 */
+#define CAN_F9R1_FB29_Pos (29U)
+#define CAN_F9R1_FB29_Msk (0x1U << CAN_F9R1_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F9R1_FB29 CAN_F9R1_FB29_Msk /*!< Filter bit 29 */
+#define CAN_F9R1_FB30_Pos (30U)
+#define CAN_F9R1_FB30_Msk (0x1U << CAN_F9R1_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F9R1_FB30 CAN_F9R1_FB30_Msk /*!< Filter bit 30 */
+#define CAN_F9R1_FB31_Pos (31U)
+#define CAN_F9R1_FB31_Msk (0x1U << CAN_F9R1_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F9R1_FB31 CAN_F9R1_FB31_Msk /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F10R1 register ******************/
+#define CAN_F10R1_FB0_Pos (0U)
+#define CAN_F10R1_FB0_Msk (0x1U << CAN_F10R1_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F10R1_FB0 CAN_F10R1_FB0_Msk /*!< Filter bit 0 */
+#define CAN_F10R1_FB1_Pos (1U)
+#define CAN_F10R1_FB1_Msk (0x1U << CAN_F10R1_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F10R1_FB1 CAN_F10R1_FB1_Msk /*!< Filter bit 1 */
+#define CAN_F10R1_FB2_Pos (2U)
+#define CAN_F10R1_FB2_Msk (0x1U << CAN_F10R1_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F10R1_FB2 CAN_F10R1_FB2_Msk /*!< Filter bit 2 */
+#define CAN_F10R1_FB3_Pos (3U)
+#define CAN_F10R1_FB3_Msk (0x1U << CAN_F10R1_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F10R1_FB3 CAN_F10R1_FB3_Msk /*!< Filter bit 3 */
+#define CAN_F10R1_FB4_Pos (4U)
+#define CAN_F10R1_FB4_Msk (0x1U << CAN_F10R1_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F10R1_FB4 CAN_F10R1_FB4_Msk /*!< Filter bit 4 */
+#define CAN_F10R1_FB5_Pos (5U)
+#define CAN_F10R1_FB5_Msk (0x1U << CAN_F10R1_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F10R1_FB5 CAN_F10R1_FB5_Msk /*!< Filter bit 5 */
+#define CAN_F10R1_FB6_Pos (6U)
+#define CAN_F10R1_FB6_Msk (0x1U << CAN_F10R1_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F10R1_FB6 CAN_F10R1_FB6_Msk /*!< Filter bit 6 */
+#define CAN_F10R1_FB7_Pos (7U)
+#define CAN_F10R1_FB7_Msk (0x1U << CAN_F10R1_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F10R1_FB7 CAN_F10R1_FB7_Msk /*!< Filter bit 7 */
+#define CAN_F10R1_FB8_Pos (8U)
+#define CAN_F10R1_FB8_Msk (0x1U << CAN_F10R1_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F10R1_FB8 CAN_F10R1_FB8_Msk /*!< Filter bit 8 */
+#define CAN_F10R1_FB9_Pos (9U)
+#define CAN_F10R1_FB9_Msk (0x1U << CAN_F10R1_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F10R1_FB9 CAN_F10R1_FB9_Msk /*!< Filter bit 9 */
+#define CAN_F10R1_FB10_Pos (10U)
+#define CAN_F10R1_FB10_Msk (0x1U << CAN_F10R1_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F10R1_FB10 CAN_F10R1_FB10_Msk /*!< Filter bit 10 */
+#define CAN_F10R1_FB11_Pos (11U)
+#define CAN_F10R1_FB11_Msk (0x1U << CAN_F10R1_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F10R1_FB11 CAN_F10R1_FB11_Msk /*!< Filter bit 11 */
+#define CAN_F10R1_FB12_Pos (12U)
+#define CAN_F10R1_FB12_Msk (0x1U << CAN_F10R1_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F10R1_FB12 CAN_F10R1_FB12_Msk /*!< Filter bit 12 */
+#define CAN_F10R1_FB13_Pos (13U)
+#define CAN_F10R1_FB13_Msk (0x1U << CAN_F10R1_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F10R1_FB13 CAN_F10R1_FB13_Msk /*!< Filter bit 13 */
+#define CAN_F10R1_FB14_Pos (14U)
+#define CAN_F10R1_FB14_Msk (0x1U << CAN_F10R1_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F10R1_FB14 CAN_F10R1_FB14_Msk /*!< Filter bit 14 */
+#define CAN_F10R1_FB15_Pos (15U)
+#define CAN_F10R1_FB15_Msk (0x1U << CAN_F10R1_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F10R1_FB15 CAN_F10R1_FB15_Msk /*!< Filter bit 15 */
+#define CAN_F10R1_FB16_Pos (16U)
+#define CAN_F10R1_FB16_Msk (0x1U << CAN_F10R1_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F10R1_FB16 CAN_F10R1_FB16_Msk /*!< Filter bit 16 */
+#define CAN_F10R1_FB17_Pos (17U)
+#define CAN_F10R1_FB17_Msk (0x1U << CAN_F10R1_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F10R1_FB17 CAN_F10R1_FB17_Msk /*!< Filter bit 17 */
+#define CAN_F10R1_FB18_Pos (18U)
+#define CAN_F10R1_FB18_Msk (0x1U << CAN_F10R1_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F10R1_FB18 CAN_F10R1_FB18_Msk /*!< Filter bit 18 */
+#define CAN_F10R1_FB19_Pos (19U)
+#define CAN_F10R1_FB19_Msk (0x1U << CAN_F10R1_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F10R1_FB19 CAN_F10R1_FB19_Msk /*!< Filter bit 19 */
+#define CAN_F10R1_FB20_Pos (20U)
+#define CAN_F10R1_FB20_Msk (0x1U << CAN_F10R1_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F10R1_FB20 CAN_F10R1_FB20_Msk /*!< Filter bit 20 */
+#define CAN_F10R1_FB21_Pos (21U)
+#define CAN_F10R1_FB21_Msk (0x1U << CAN_F10R1_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F10R1_FB21 CAN_F10R1_FB21_Msk /*!< Filter bit 21 */
+#define CAN_F10R1_FB22_Pos (22U)
+#define CAN_F10R1_FB22_Msk (0x1U << CAN_F10R1_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F10R1_FB22 CAN_F10R1_FB22_Msk /*!< Filter bit 22 */
+#define CAN_F10R1_FB23_Pos (23U)
+#define CAN_F10R1_FB23_Msk (0x1U << CAN_F10R1_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F10R1_FB23 CAN_F10R1_FB23_Msk /*!< Filter bit 23 */
+#define CAN_F10R1_FB24_Pos (24U)
+#define CAN_F10R1_FB24_Msk (0x1U << CAN_F10R1_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F10R1_FB24 CAN_F10R1_FB24_Msk /*!< Filter bit 24 */
+#define CAN_F10R1_FB25_Pos (25U)
+#define CAN_F10R1_FB25_Msk (0x1U << CAN_F10R1_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F10R1_FB25 CAN_F10R1_FB25_Msk /*!< Filter bit 25 */
+#define CAN_F10R1_FB26_Pos (26U)
+#define CAN_F10R1_FB26_Msk (0x1U << CAN_F10R1_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F10R1_FB26 CAN_F10R1_FB26_Msk /*!< Filter bit 26 */
+#define CAN_F10R1_FB27_Pos (27U)
+#define CAN_F10R1_FB27_Msk (0x1U << CAN_F10R1_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F10R1_FB27 CAN_F10R1_FB27_Msk /*!< Filter bit 27 */
+#define CAN_F10R1_FB28_Pos (28U)
+#define CAN_F10R1_FB28_Msk (0x1U << CAN_F10R1_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F10R1_FB28 CAN_F10R1_FB28_Msk /*!< Filter bit 28 */
+#define CAN_F10R1_FB29_Pos (29U)
+#define CAN_F10R1_FB29_Msk (0x1U << CAN_F10R1_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F10R1_FB29 CAN_F10R1_FB29_Msk /*!< Filter bit 29 */
+#define CAN_F10R1_FB30_Pos (30U)
+#define CAN_F10R1_FB30_Msk (0x1U << CAN_F10R1_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F10R1_FB30 CAN_F10R1_FB30_Msk /*!< Filter bit 30 */
+#define CAN_F10R1_FB31_Pos (31U)
+#define CAN_F10R1_FB31_Msk (0x1U << CAN_F10R1_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F10R1_FB31 CAN_F10R1_FB31_Msk /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F11R1 register ******************/
+#define CAN_F11R1_FB0_Pos (0U)
+#define CAN_F11R1_FB0_Msk (0x1U << CAN_F11R1_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F11R1_FB0 CAN_F11R1_FB0_Msk /*!< Filter bit 0 */
+#define CAN_F11R1_FB1_Pos (1U)
+#define CAN_F11R1_FB1_Msk (0x1U << CAN_F11R1_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F11R1_FB1 CAN_F11R1_FB1_Msk /*!< Filter bit 1 */
+#define CAN_F11R1_FB2_Pos (2U)
+#define CAN_F11R1_FB2_Msk (0x1U << CAN_F11R1_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F11R1_FB2 CAN_F11R1_FB2_Msk /*!< Filter bit 2 */
+#define CAN_F11R1_FB3_Pos (3U)
+#define CAN_F11R1_FB3_Msk (0x1U << CAN_F11R1_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F11R1_FB3 CAN_F11R1_FB3_Msk /*!< Filter bit 3 */
+#define CAN_F11R1_FB4_Pos (4U)
+#define CAN_F11R1_FB4_Msk (0x1U << CAN_F11R1_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F11R1_FB4 CAN_F11R1_FB4_Msk /*!< Filter bit 4 */
+#define CAN_F11R1_FB5_Pos (5U)
+#define CAN_F11R1_FB5_Msk (0x1U << CAN_F11R1_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F11R1_FB5 CAN_F11R1_FB5_Msk /*!< Filter bit 5 */
+#define CAN_F11R1_FB6_Pos (6U)
+#define CAN_F11R1_FB6_Msk (0x1U << CAN_F11R1_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F11R1_FB6 CAN_F11R1_FB6_Msk /*!< Filter bit 6 */
+#define CAN_F11R1_FB7_Pos (7U)
+#define CAN_F11R1_FB7_Msk (0x1U << CAN_F11R1_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F11R1_FB7 CAN_F11R1_FB7_Msk /*!< Filter bit 7 */
+#define CAN_F11R1_FB8_Pos (8U)
+#define CAN_F11R1_FB8_Msk (0x1U << CAN_F11R1_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F11R1_FB8 CAN_F11R1_FB8_Msk /*!< Filter bit 8 */
+#define CAN_F11R1_FB9_Pos (9U)
+#define CAN_F11R1_FB9_Msk (0x1U << CAN_F11R1_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F11R1_FB9 CAN_F11R1_FB9_Msk /*!< Filter bit 9 */
+#define CAN_F11R1_FB10_Pos (10U)
+#define CAN_F11R1_FB10_Msk (0x1U << CAN_F11R1_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F11R1_FB10 CAN_F11R1_FB10_Msk /*!< Filter bit 10 */
+#define CAN_F11R1_FB11_Pos (11U)
+#define CAN_F11R1_FB11_Msk (0x1U << CAN_F11R1_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F11R1_FB11 CAN_F11R1_FB11_Msk /*!< Filter bit 11 */
+#define CAN_F11R1_FB12_Pos (12U)
+#define CAN_F11R1_FB12_Msk (0x1U << CAN_F11R1_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F11R1_FB12 CAN_F11R1_FB12_Msk /*!< Filter bit 12 */
+#define CAN_F11R1_FB13_Pos (13U)
+#define CAN_F11R1_FB13_Msk (0x1U << CAN_F11R1_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F11R1_FB13 CAN_F11R1_FB13_Msk /*!< Filter bit 13 */
+#define CAN_F11R1_FB14_Pos (14U)
+#define CAN_F11R1_FB14_Msk (0x1U << CAN_F11R1_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F11R1_FB14 CAN_F11R1_FB14_Msk /*!< Filter bit 14 */
+#define CAN_F11R1_FB15_Pos (15U)
+#define CAN_F11R1_FB15_Msk (0x1U << CAN_F11R1_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F11R1_FB15 CAN_F11R1_FB15_Msk /*!< Filter bit 15 */
+#define CAN_F11R1_FB16_Pos (16U)
+#define CAN_F11R1_FB16_Msk (0x1U << CAN_F11R1_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F11R1_FB16 CAN_F11R1_FB16_Msk /*!< Filter bit 16 */
+#define CAN_F11R1_FB17_Pos (17U)
+#define CAN_F11R1_FB17_Msk (0x1U << CAN_F11R1_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F11R1_FB17 CAN_F11R1_FB17_Msk /*!< Filter bit 17 */
+#define CAN_F11R1_FB18_Pos (18U)
+#define CAN_F11R1_FB18_Msk (0x1U << CAN_F11R1_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F11R1_FB18 CAN_F11R1_FB18_Msk /*!< Filter bit 18 */
+#define CAN_F11R1_FB19_Pos (19U)
+#define CAN_F11R1_FB19_Msk (0x1U << CAN_F11R1_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F11R1_FB19 CAN_F11R1_FB19_Msk /*!< Filter bit 19 */
+#define CAN_F11R1_FB20_Pos (20U)
+#define CAN_F11R1_FB20_Msk (0x1U << CAN_F11R1_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F11R1_FB20 CAN_F11R1_FB20_Msk /*!< Filter bit 20 */
+#define CAN_F11R1_FB21_Pos (21U)
+#define CAN_F11R1_FB21_Msk (0x1U << CAN_F11R1_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F11R1_FB21 CAN_F11R1_FB21_Msk /*!< Filter bit 21 */
+#define CAN_F11R1_FB22_Pos (22U)
+#define CAN_F11R1_FB22_Msk (0x1U << CAN_F11R1_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F11R1_FB22 CAN_F11R1_FB22_Msk /*!< Filter bit 22 */
+#define CAN_F11R1_FB23_Pos (23U)
+#define CAN_F11R1_FB23_Msk (0x1U << CAN_F11R1_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F11R1_FB23 CAN_F11R1_FB23_Msk /*!< Filter bit 23 */
+#define CAN_F11R1_FB24_Pos (24U)
+#define CAN_F11R1_FB24_Msk (0x1U << CAN_F11R1_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F11R1_FB24 CAN_F11R1_FB24_Msk /*!< Filter bit 24 */
+#define CAN_F11R1_FB25_Pos (25U)
+#define CAN_F11R1_FB25_Msk (0x1U << CAN_F11R1_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F11R1_FB25 CAN_F11R1_FB25_Msk /*!< Filter bit 25 */
+#define CAN_F11R1_FB26_Pos (26U)
+#define CAN_F11R1_FB26_Msk (0x1U << CAN_F11R1_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F11R1_FB26 CAN_F11R1_FB26_Msk /*!< Filter bit 26 */
+#define CAN_F11R1_FB27_Pos (27U)
+#define CAN_F11R1_FB27_Msk (0x1U << CAN_F11R1_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F11R1_FB27 CAN_F11R1_FB27_Msk /*!< Filter bit 27 */
+#define CAN_F11R1_FB28_Pos (28U)
+#define CAN_F11R1_FB28_Msk (0x1U << CAN_F11R1_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F11R1_FB28 CAN_F11R1_FB28_Msk /*!< Filter bit 28 */
+#define CAN_F11R1_FB29_Pos (29U)
+#define CAN_F11R1_FB29_Msk (0x1U << CAN_F11R1_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F11R1_FB29 CAN_F11R1_FB29_Msk /*!< Filter bit 29 */
+#define CAN_F11R1_FB30_Pos (30U)
+#define CAN_F11R1_FB30_Msk (0x1U << CAN_F11R1_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F11R1_FB30 CAN_F11R1_FB30_Msk /*!< Filter bit 30 */
+#define CAN_F11R1_FB31_Pos (31U)
+#define CAN_F11R1_FB31_Msk (0x1U << CAN_F11R1_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F11R1_FB31 CAN_F11R1_FB31_Msk /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F12R1 register ******************/
+#define CAN_F12R1_FB0_Pos (0U)
+#define CAN_F12R1_FB0_Msk (0x1U << CAN_F12R1_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F12R1_FB0 CAN_F12R1_FB0_Msk /*!< Filter bit 0 */
+#define CAN_F12R1_FB1_Pos (1U)
+#define CAN_F12R1_FB1_Msk (0x1U << CAN_F12R1_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F12R1_FB1 CAN_F12R1_FB1_Msk /*!< Filter bit 1 */
+#define CAN_F12R1_FB2_Pos (2U)
+#define CAN_F12R1_FB2_Msk (0x1U << CAN_F12R1_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F12R1_FB2 CAN_F12R1_FB2_Msk /*!< Filter bit 2 */
+#define CAN_F12R1_FB3_Pos (3U)
+#define CAN_F12R1_FB3_Msk (0x1U << CAN_F12R1_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F12R1_FB3 CAN_F12R1_FB3_Msk /*!< Filter bit 3 */
+#define CAN_F12R1_FB4_Pos (4U)
+#define CAN_F12R1_FB4_Msk (0x1U << CAN_F12R1_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F12R1_FB4 CAN_F12R1_FB4_Msk /*!< Filter bit 4 */
+#define CAN_F12R1_FB5_Pos (5U)
+#define CAN_F12R1_FB5_Msk (0x1U << CAN_F12R1_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F12R1_FB5 CAN_F12R1_FB5_Msk /*!< Filter bit 5 */
+#define CAN_F12R1_FB6_Pos (6U)
+#define CAN_F12R1_FB6_Msk (0x1U << CAN_F12R1_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F12R1_FB6 CAN_F12R1_FB6_Msk /*!< Filter bit 6 */
+#define CAN_F12R1_FB7_Pos (7U)
+#define CAN_F12R1_FB7_Msk (0x1U << CAN_F12R1_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F12R1_FB7 CAN_F12R1_FB7_Msk /*!< Filter bit 7 */
+#define CAN_F12R1_FB8_Pos (8U)
+#define CAN_F12R1_FB8_Msk (0x1U << CAN_F12R1_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F12R1_FB8 CAN_F12R1_FB8_Msk /*!< Filter bit 8 */
+#define CAN_F12R1_FB9_Pos (9U)
+#define CAN_F12R1_FB9_Msk (0x1U << CAN_F12R1_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F12R1_FB9 CAN_F12R1_FB9_Msk /*!< Filter bit 9 */
+#define CAN_F12R1_FB10_Pos (10U)
+#define CAN_F12R1_FB10_Msk (0x1U << CAN_F12R1_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F12R1_FB10 CAN_F12R1_FB10_Msk /*!< Filter bit 10 */
+#define CAN_F12R1_FB11_Pos (11U)
+#define CAN_F12R1_FB11_Msk (0x1U << CAN_F12R1_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F12R1_FB11 CAN_F12R1_FB11_Msk /*!< Filter bit 11 */
+#define CAN_F12R1_FB12_Pos (12U)
+#define CAN_F12R1_FB12_Msk (0x1U << CAN_F12R1_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F12R1_FB12 CAN_F12R1_FB12_Msk /*!< Filter bit 12 */
+#define CAN_F12R1_FB13_Pos (13U)
+#define CAN_F12R1_FB13_Msk (0x1U << CAN_F12R1_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F12R1_FB13 CAN_F12R1_FB13_Msk /*!< Filter bit 13 */
+#define CAN_F12R1_FB14_Pos (14U)
+#define CAN_F12R1_FB14_Msk (0x1U << CAN_F12R1_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F12R1_FB14 CAN_F12R1_FB14_Msk /*!< Filter bit 14 */
+#define CAN_F12R1_FB15_Pos (15U)
+#define CAN_F12R1_FB15_Msk (0x1U << CAN_F12R1_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F12R1_FB15 CAN_F12R1_FB15_Msk /*!< Filter bit 15 */
+#define CAN_F12R1_FB16_Pos (16U)
+#define CAN_F12R1_FB16_Msk (0x1U << CAN_F12R1_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F12R1_FB16 CAN_F12R1_FB16_Msk /*!< Filter bit 16 */
+#define CAN_F12R1_FB17_Pos (17U)
+#define CAN_F12R1_FB17_Msk (0x1U << CAN_F12R1_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F12R1_FB17 CAN_F12R1_FB17_Msk /*!< Filter bit 17 */
+#define CAN_F12R1_FB18_Pos (18U)
+#define CAN_F12R1_FB18_Msk (0x1U << CAN_F12R1_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F12R1_FB18 CAN_F12R1_FB18_Msk /*!< Filter bit 18 */
+#define CAN_F12R1_FB19_Pos (19U)
+#define CAN_F12R1_FB19_Msk (0x1U << CAN_F12R1_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F12R1_FB19 CAN_F12R1_FB19_Msk /*!< Filter bit 19 */
+#define CAN_F12R1_FB20_Pos (20U)
+#define CAN_F12R1_FB20_Msk (0x1U << CAN_F12R1_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F12R1_FB20 CAN_F12R1_FB20_Msk /*!< Filter bit 20 */
+#define CAN_F12R1_FB21_Pos (21U)
+#define CAN_F12R1_FB21_Msk (0x1U << CAN_F12R1_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F12R1_FB21 CAN_F12R1_FB21_Msk /*!< Filter bit 21 */
+#define CAN_F12R1_FB22_Pos (22U)
+#define CAN_F12R1_FB22_Msk (0x1U << CAN_F12R1_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F12R1_FB22 CAN_F12R1_FB22_Msk /*!< Filter bit 22 */
+#define CAN_F12R1_FB23_Pos (23U)
+#define CAN_F12R1_FB23_Msk (0x1U << CAN_F12R1_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F12R1_FB23 CAN_F12R1_FB23_Msk /*!< Filter bit 23 */
+#define CAN_F12R1_FB24_Pos (24U)
+#define CAN_F12R1_FB24_Msk (0x1U << CAN_F12R1_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F12R1_FB24 CAN_F12R1_FB24_Msk /*!< Filter bit 24 */
+#define CAN_F12R1_FB25_Pos (25U)
+#define CAN_F12R1_FB25_Msk (0x1U << CAN_F12R1_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F12R1_FB25 CAN_F12R1_FB25_Msk /*!< Filter bit 25 */
+#define CAN_F12R1_FB26_Pos (26U)
+#define CAN_F12R1_FB26_Msk (0x1U << CAN_F12R1_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F12R1_FB26 CAN_F12R1_FB26_Msk /*!< Filter bit 26 */
+#define CAN_F12R1_FB27_Pos (27U)
+#define CAN_F12R1_FB27_Msk (0x1U << CAN_F12R1_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F12R1_FB27 CAN_F12R1_FB27_Msk /*!< Filter bit 27 */
+#define CAN_F12R1_FB28_Pos (28U)
+#define CAN_F12R1_FB28_Msk (0x1U << CAN_F12R1_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F12R1_FB28 CAN_F12R1_FB28_Msk /*!< Filter bit 28 */
+#define CAN_F12R1_FB29_Pos (29U)
+#define CAN_F12R1_FB29_Msk (0x1U << CAN_F12R1_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F12R1_FB29 CAN_F12R1_FB29_Msk /*!< Filter bit 29 */
+#define CAN_F12R1_FB30_Pos (30U)
+#define CAN_F12R1_FB30_Msk (0x1U << CAN_F12R1_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F12R1_FB30 CAN_F12R1_FB30_Msk /*!< Filter bit 30 */
+#define CAN_F12R1_FB31_Pos (31U)
+#define CAN_F12R1_FB31_Msk (0x1U << CAN_F12R1_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F12R1_FB31 CAN_F12R1_FB31_Msk /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F13R1 register ******************/
+#define CAN_F13R1_FB0_Pos (0U)
+#define CAN_F13R1_FB0_Msk (0x1U << CAN_F13R1_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F13R1_FB0 CAN_F13R1_FB0_Msk /*!< Filter bit 0 */
+#define CAN_F13R1_FB1_Pos (1U)
+#define CAN_F13R1_FB1_Msk (0x1U << CAN_F13R1_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F13R1_FB1 CAN_F13R1_FB1_Msk /*!< Filter bit 1 */
+#define CAN_F13R1_FB2_Pos (2U)
+#define CAN_F13R1_FB2_Msk (0x1U << CAN_F13R1_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F13R1_FB2 CAN_F13R1_FB2_Msk /*!< Filter bit 2 */
+#define CAN_F13R1_FB3_Pos (3U)
+#define CAN_F13R1_FB3_Msk (0x1U << CAN_F13R1_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F13R1_FB3 CAN_F13R1_FB3_Msk /*!< Filter bit 3 */
+#define CAN_F13R1_FB4_Pos (4U)
+#define CAN_F13R1_FB4_Msk (0x1U << CAN_F13R1_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F13R1_FB4 CAN_F13R1_FB4_Msk /*!< Filter bit 4 */
+#define CAN_F13R1_FB5_Pos (5U)
+#define CAN_F13R1_FB5_Msk (0x1U << CAN_F13R1_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F13R1_FB5 CAN_F13R1_FB5_Msk /*!< Filter bit 5 */
+#define CAN_F13R1_FB6_Pos (6U)
+#define CAN_F13R1_FB6_Msk (0x1U << CAN_F13R1_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F13R1_FB6 CAN_F13R1_FB6_Msk /*!< Filter bit 6 */
+#define CAN_F13R1_FB7_Pos (7U)
+#define CAN_F13R1_FB7_Msk (0x1U << CAN_F13R1_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F13R1_FB7 CAN_F13R1_FB7_Msk /*!< Filter bit 7 */
+#define CAN_F13R1_FB8_Pos (8U)
+#define CAN_F13R1_FB8_Msk (0x1U << CAN_F13R1_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F13R1_FB8 CAN_F13R1_FB8_Msk /*!< Filter bit 8 */
+#define CAN_F13R1_FB9_Pos (9U)
+#define CAN_F13R1_FB9_Msk (0x1U << CAN_F13R1_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F13R1_FB9 CAN_F13R1_FB9_Msk /*!< Filter bit 9 */
+#define CAN_F13R1_FB10_Pos (10U)
+#define CAN_F13R1_FB10_Msk (0x1U << CAN_F13R1_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F13R1_FB10 CAN_F13R1_FB10_Msk /*!< Filter bit 10 */
+#define CAN_F13R1_FB11_Pos (11U)
+#define CAN_F13R1_FB11_Msk (0x1U << CAN_F13R1_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F13R1_FB11 CAN_F13R1_FB11_Msk /*!< Filter bit 11 */
+#define CAN_F13R1_FB12_Pos (12U)
+#define CAN_F13R1_FB12_Msk (0x1U << CAN_F13R1_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F13R1_FB12 CAN_F13R1_FB12_Msk /*!< Filter bit 12 */
+#define CAN_F13R1_FB13_Pos (13U)
+#define CAN_F13R1_FB13_Msk (0x1U << CAN_F13R1_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F13R1_FB13 CAN_F13R1_FB13_Msk /*!< Filter bit 13 */
+#define CAN_F13R1_FB14_Pos (14U)
+#define CAN_F13R1_FB14_Msk (0x1U << CAN_F13R1_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F13R1_FB14 CAN_F13R1_FB14_Msk /*!< Filter bit 14 */
+#define CAN_F13R1_FB15_Pos (15U)
+#define CAN_F13R1_FB15_Msk (0x1U << CAN_F13R1_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F13R1_FB15 CAN_F13R1_FB15_Msk /*!< Filter bit 15 */
+#define CAN_F13R1_FB16_Pos (16U)
+#define CAN_F13R1_FB16_Msk (0x1U << CAN_F13R1_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F13R1_FB16 CAN_F13R1_FB16_Msk /*!< Filter bit 16 */
+#define CAN_F13R1_FB17_Pos (17U)
+#define CAN_F13R1_FB17_Msk (0x1U << CAN_F13R1_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F13R1_FB17 CAN_F13R1_FB17_Msk /*!< Filter bit 17 */
+#define CAN_F13R1_FB18_Pos (18U)
+#define CAN_F13R1_FB18_Msk (0x1U << CAN_F13R1_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F13R1_FB18 CAN_F13R1_FB18_Msk /*!< Filter bit 18 */
+#define CAN_F13R1_FB19_Pos (19U)
+#define CAN_F13R1_FB19_Msk (0x1U << CAN_F13R1_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F13R1_FB19 CAN_F13R1_FB19_Msk /*!< Filter bit 19 */
+#define CAN_F13R1_FB20_Pos (20U)
+#define CAN_F13R1_FB20_Msk (0x1U << CAN_F13R1_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F13R1_FB20 CAN_F13R1_FB20_Msk /*!< Filter bit 20 */
+#define CAN_F13R1_FB21_Pos (21U)
+#define CAN_F13R1_FB21_Msk (0x1U << CAN_F13R1_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F13R1_FB21 CAN_F13R1_FB21_Msk /*!< Filter bit 21 */
+#define CAN_F13R1_FB22_Pos (22U)
+#define CAN_F13R1_FB22_Msk (0x1U << CAN_F13R1_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F13R1_FB22 CAN_F13R1_FB22_Msk /*!< Filter bit 22 */
+#define CAN_F13R1_FB23_Pos (23U)
+#define CAN_F13R1_FB23_Msk (0x1U << CAN_F13R1_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F13R1_FB23 CAN_F13R1_FB23_Msk /*!< Filter bit 23 */
+#define CAN_F13R1_FB24_Pos (24U)
+#define CAN_F13R1_FB24_Msk (0x1U << CAN_F13R1_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F13R1_FB24 CAN_F13R1_FB24_Msk /*!< Filter bit 24 */
+#define CAN_F13R1_FB25_Pos (25U)
+#define CAN_F13R1_FB25_Msk (0x1U << CAN_F13R1_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F13R1_FB25 CAN_F13R1_FB25_Msk /*!< Filter bit 25 */
+#define CAN_F13R1_FB26_Pos (26U)
+#define CAN_F13R1_FB26_Msk (0x1U << CAN_F13R1_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F13R1_FB26 CAN_F13R1_FB26_Msk /*!< Filter bit 26 */
+#define CAN_F13R1_FB27_Pos (27U)
+#define CAN_F13R1_FB27_Msk (0x1U << CAN_F13R1_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F13R1_FB27 CAN_F13R1_FB27_Msk /*!< Filter bit 27 */
+#define CAN_F13R1_FB28_Pos (28U)
+#define CAN_F13R1_FB28_Msk (0x1U << CAN_F13R1_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F13R1_FB28 CAN_F13R1_FB28_Msk /*!< Filter bit 28 */
+#define CAN_F13R1_FB29_Pos (29U)
+#define CAN_F13R1_FB29_Msk (0x1U << CAN_F13R1_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F13R1_FB29 CAN_F13R1_FB29_Msk /*!< Filter bit 29 */
+#define CAN_F13R1_FB30_Pos (30U)
+#define CAN_F13R1_FB30_Msk (0x1U << CAN_F13R1_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F13R1_FB30 CAN_F13R1_FB30_Msk /*!< Filter bit 30 */
+#define CAN_F13R1_FB31_Pos (31U)
+#define CAN_F13R1_FB31_Msk (0x1U << CAN_F13R1_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F13R1_FB31 CAN_F13R1_FB31_Msk /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F0R2 register *******************/
+#define CAN_F0R2_FB0_Pos (0U)
+#define CAN_F0R2_FB0_Msk (0x1U << CAN_F0R2_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F0R2_FB0 CAN_F0R2_FB0_Msk /*!< Filter bit 0 */
+#define CAN_F0R2_FB1_Pos (1U)
+#define CAN_F0R2_FB1_Msk (0x1U << CAN_F0R2_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F0R2_FB1 CAN_F0R2_FB1_Msk /*!< Filter bit 1 */
+#define CAN_F0R2_FB2_Pos (2U)
+#define CAN_F0R2_FB2_Msk (0x1U << CAN_F0R2_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F0R2_FB2 CAN_F0R2_FB2_Msk /*!< Filter bit 2 */
+#define CAN_F0R2_FB3_Pos (3U)
+#define CAN_F0R2_FB3_Msk (0x1U << CAN_F0R2_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F0R2_FB3 CAN_F0R2_FB3_Msk /*!< Filter bit 3 */
+#define CAN_F0R2_FB4_Pos (4U)
+#define CAN_F0R2_FB4_Msk (0x1U << CAN_F0R2_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F0R2_FB4 CAN_F0R2_FB4_Msk /*!< Filter bit 4 */
+#define CAN_F0R2_FB5_Pos (5U)
+#define CAN_F0R2_FB5_Msk (0x1U << CAN_F0R2_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F0R2_FB5 CAN_F0R2_FB5_Msk /*!< Filter bit 5 */
+#define CAN_F0R2_FB6_Pos (6U)
+#define CAN_F0R2_FB6_Msk (0x1U << CAN_F0R2_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F0R2_FB6 CAN_F0R2_FB6_Msk /*!< Filter bit 6 */
+#define CAN_F0R2_FB7_Pos (7U)
+#define CAN_F0R2_FB7_Msk (0x1U << CAN_F0R2_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F0R2_FB7 CAN_F0R2_FB7_Msk /*!< Filter bit 7 */
+#define CAN_F0R2_FB8_Pos (8U)
+#define CAN_F0R2_FB8_Msk (0x1U << CAN_F0R2_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F0R2_FB8 CAN_F0R2_FB8_Msk /*!< Filter bit 8 */
+#define CAN_F0R2_FB9_Pos (9U)
+#define CAN_F0R2_FB9_Msk (0x1U << CAN_F0R2_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F0R2_FB9 CAN_F0R2_FB9_Msk /*!< Filter bit 9 */
+#define CAN_F0R2_FB10_Pos (10U)
+#define CAN_F0R2_FB10_Msk (0x1U << CAN_F0R2_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F0R2_FB10 CAN_F0R2_FB10_Msk /*!< Filter bit 10 */
+#define CAN_F0R2_FB11_Pos (11U)
+#define CAN_F0R2_FB11_Msk (0x1U << CAN_F0R2_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F0R2_FB11 CAN_F0R2_FB11_Msk /*!< Filter bit 11 */
+#define CAN_F0R2_FB12_Pos (12U)
+#define CAN_F0R2_FB12_Msk (0x1U << CAN_F0R2_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F0R2_FB12 CAN_F0R2_FB12_Msk /*!< Filter bit 12 */
+#define CAN_F0R2_FB13_Pos (13U)
+#define CAN_F0R2_FB13_Msk (0x1U << CAN_F0R2_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F0R2_FB13 CAN_F0R2_FB13_Msk /*!< Filter bit 13 */
+#define CAN_F0R2_FB14_Pos (14U)
+#define CAN_F0R2_FB14_Msk (0x1U << CAN_F0R2_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F0R2_FB14 CAN_F0R2_FB14_Msk /*!< Filter bit 14 */
+#define CAN_F0R2_FB15_Pos (15U)
+#define CAN_F0R2_FB15_Msk (0x1U << CAN_F0R2_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F0R2_FB15 CAN_F0R2_FB15_Msk /*!< Filter bit 15 */
+#define CAN_F0R2_FB16_Pos (16U)
+#define CAN_F0R2_FB16_Msk (0x1U << CAN_F0R2_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F0R2_FB16 CAN_F0R2_FB16_Msk /*!< Filter bit 16 */
+#define CAN_F0R2_FB17_Pos (17U)
+#define CAN_F0R2_FB17_Msk (0x1U << CAN_F0R2_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F0R2_FB17 CAN_F0R2_FB17_Msk /*!< Filter bit 17 */
+#define CAN_F0R2_FB18_Pos (18U)
+#define CAN_F0R2_FB18_Msk (0x1U << CAN_F0R2_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F0R2_FB18 CAN_F0R2_FB18_Msk /*!< Filter bit 18 */
+#define CAN_F0R2_FB19_Pos (19U)
+#define CAN_F0R2_FB19_Msk (0x1U << CAN_F0R2_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F0R2_FB19 CAN_F0R2_FB19_Msk /*!< Filter bit 19 */
+#define CAN_F0R2_FB20_Pos (20U)
+#define CAN_F0R2_FB20_Msk (0x1U << CAN_F0R2_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F0R2_FB20 CAN_F0R2_FB20_Msk /*!< Filter bit 20 */
+#define CAN_F0R2_FB21_Pos (21U)
+#define CAN_F0R2_FB21_Msk (0x1U << CAN_F0R2_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F0R2_FB21 CAN_F0R2_FB21_Msk /*!< Filter bit 21 */
+#define CAN_F0R2_FB22_Pos (22U)
+#define CAN_F0R2_FB22_Msk (0x1U << CAN_F0R2_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F0R2_FB22 CAN_F0R2_FB22_Msk /*!< Filter bit 22 */
+#define CAN_F0R2_FB23_Pos (23U)
+#define CAN_F0R2_FB23_Msk (0x1U << CAN_F0R2_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F0R2_FB23 CAN_F0R2_FB23_Msk /*!< Filter bit 23 */
+#define CAN_F0R2_FB24_Pos (24U)
+#define CAN_F0R2_FB24_Msk (0x1U << CAN_F0R2_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F0R2_FB24 CAN_F0R2_FB24_Msk /*!< Filter bit 24 */
+#define CAN_F0R2_FB25_Pos (25U)
+#define CAN_F0R2_FB25_Msk (0x1U << CAN_F0R2_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F0R2_FB25 CAN_F0R2_FB25_Msk /*!< Filter bit 25 */
+#define CAN_F0R2_FB26_Pos (26U)
+#define CAN_F0R2_FB26_Msk (0x1U << CAN_F0R2_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F0R2_FB26 CAN_F0R2_FB26_Msk /*!< Filter bit 26 */
+#define CAN_F0R2_FB27_Pos (27U)
+#define CAN_F0R2_FB27_Msk (0x1U << CAN_F0R2_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F0R2_FB27 CAN_F0R2_FB27_Msk /*!< Filter bit 27 */
+#define CAN_F0R2_FB28_Pos (28U)
+#define CAN_F0R2_FB28_Msk (0x1U << CAN_F0R2_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F0R2_FB28 CAN_F0R2_FB28_Msk /*!< Filter bit 28 */
+#define CAN_F0R2_FB29_Pos (29U)
+#define CAN_F0R2_FB29_Msk (0x1U << CAN_F0R2_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F0R2_FB29 CAN_F0R2_FB29_Msk /*!< Filter bit 29 */
+#define CAN_F0R2_FB30_Pos (30U)
+#define CAN_F0R2_FB30_Msk (0x1U << CAN_F0R2_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F0R2_FB30 CAN_F0R2_FB30_Msk /*!< Filter bit 30 */
+#define CAN_F0R2_FB31_Pos (31U)
+#define CAN_F0R2_FB31_Msk (0x1U << CAN_F0R2_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F0R2_FB31 CAN_F0R2_FB31_Msk /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F1R2 register *******************/
+#define CAN_F1R2_FB0_Pos (0U)
+#define CAN_F1R2_FB0_Msk (0x1U << CAN_F1R2_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F1R2_FB0 CAN_F1R2_FB0_Msk /*!< Filter bit 0 */
+#define CAN_F1R2_FB1_Pos (1U)
+#define CAN_F1R2_FB1_Msk (0x1U << CAN_F1R2_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F1R2_FB1 CAN_F1R2_FB1_Msk /*!< Filter bit 1 */
+#define CAN_F1R2_FB2_Pos (2U)
+#define CAN_F1R2_FB2_Msk (0x1U << CAN_F1R2_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F1R2_FB2 CAN_F1R2_FB2_Msk /*!< Filter bit 2 */
+#define CAN_F1R2_FB3_Pos (3U)
+#define CAN_F1R2_FB3_Msk (0x1U << CAN_F1R2_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F1R2_FB3 CAN_F1R2_FB3_Msk /*!< Filter bit 3 */
+#define CAN_F1R2_FB4_Pos (4U)
+#define CAN_F1R2_FB4_Msk (0x1U << CAN_F1R2_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F1R2_FB4 CAN_F1R2_FB4_Msk /*!< Filter bit 4 */
+#define CAN_F1R2_FB5_Pos (5U)
+#define CAN_F1R2_FB5_Msk (0x1U << CAN_F1R2_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F1R2_FB5 CAN_F1R2_FB5_Msk /*!< Filter bit 5 */
+#define CAN_F1R2_FB6_Pos (6U)
+#define CAN_F1R2_FB6_Msk (0x1U << CAN_F1R2_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F1R2_FB6 CAN_F1R2_FB6_Msk /*!< Filter bit 6 */
+#define CAN_F1R2_FB7_Pos (7U)
+#define CAN_F1R2_FB7_Msk (0x1U << CAN_F1R2_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F1R2_FB7 CAN_F1R2_FB7_Msk /*!< Filter bit 7 */
+#define CAN_F1R2_FB8_Pos (8U)
+#define CAN_F1R2_FB8_Msk (0x1U << CAN_F1R2_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F1R2_FB8 CAN_F1R2_FB8_Msk /*!< Filter bit 8 */
+#define CAN_F1R2_FB9_Pos (9U)
+#define CAN_F1R2_FB9_Msk (0x1U << CAN_F1R2_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F1R2_FB9 CAN_F1R2_FB9_Msk /*!< Filter bit 9 */
+#define CAN_F1R2_FB10_Pos (10U)
+#define CAN_F1R2_FB10_Msk (0x1U << CAN_F1R2_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F1R2_FB10 CAN_F1R2_FB10_Msk /*!< Filter bit 10 */
+#define CAN_F1R2_FB11_Pos (11U)
+#define CAN_F1R2_FB11_Msk (0x1U << CAN_F1R2_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F1R2_FB11 CAN_F1R2_FB11_Msk /*!< Filter bit 11 */
+#define CAN_F1R2_FB12_Pos (12U)
+#define CAN_F1R2_FB12_Msk (0x1U << CAN_F1R2_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F1R2_FB12 CAN_F1R2_FB12_Msk /*!< Filter bit 12 */
+#define CAN_F1R2_FB13_Pos (13U)
+#define CAN_F1R2_FB13_Msk (0x1U << CAN_F1R2_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F1R2_FB13 CAN_F1R2_FB13_Msk /*!< Filter bit 13 */
+#define CAN_F1R2_FB14_Pos (14U)
+#define CAN_F1R2_FB14_Msk (0x1U << CAN_F1R2_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F1R2_FB14 CAN_F1R2_FB14_Msk /*!< Filter bit 14 */
+#define CAN_F1R2_FB15_Pos (15U)
+#define CAN_F1R2_FB15_Msk (0x1U << CAN_F1R2_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F1R2_FB15 CAN_F1R2_FB15_Msk /*!< Filter bit 15 */
+#define CAN_F1R2_FB16_Pos (16U)
+#define CAN_F1R2_FB16_Msk (0x1U << CAN_F1R2_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F1R2_FB16 CAN_F1R2_FB16_Msk /*!< Filter bit 16 */
+#define CAN_F1R2_FB17_Pos (17U)
+#define CAN_F1R2_FB17_Msk (0x1U << CAN_F1R2_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F1R2_FB17 CAN_F1R2_FB17_Msk /*!< Filter bit 17 */
+#define CAN_F1R2_FB18_Pos (18U)
+#define CAN_F1R2_FB18_Msk (0x1U << CAN_F1R2_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F1R2_FB18 CAN_F1R2_FB18_Msk /*!< Filter bit 18 */
+#define CAN_F1R2_FB19_Pos (19U)
+#define CAN_F1R2_FB19_Msk (0x1U << CAN_F1R2_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F1R2_FB19 CAN_F1R2_FB19_Msk /*!< Filter bit 19 */
+#define CAN_F1R2_FB20_Pos (20U)
+#define CAN_F1R2_FB20_Msk (0x1U << CAN_F1R2_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F1R2_FB20 CAN_F1R2_FB20_Msk /*!< Filter bit 20 */
+#define CAN_F1R2_FB21_Pos (21U)
+#define CAN_F1R2_FB21_Msk (0x1U << CAN_F1R2_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F1R2_FB21 CAN_F1R2_FB21_Msk /*!< Filter bit 21 */
+#define CAN_F1R2_FB22_Pos (22U)
+#define CAN_F1R2_FB22_Msk (0x1U << CAN_F1R2_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F1R2_FB22 CAN_F1R2_FB22_Msk /*!< Filter bit 22 */
+#define CAN_F1R2_FB23_Pos (23U)
+#define CAN_F1R2_FB23_Msk (0x1U << CAN_F1R2_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F1R2_FB23 CAN_F1R2_FB23_Msk /*!< Filter bit 23 */
+#define CAN_F1R2_FB24_Pos (24U)
+#define CAN_F1R2_FB24_Msk (0x1U << CAN_F1R2_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F1R2_FB24 CAN_F1R2_FB24_Msk /*!< Filter bit 24 */
+#define CAN_F1R2_FB25_Pos (25U)
+#define CAN_F1R2_FB25_Msk (0x1U << CAN_F1R2_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F1R2_FB25 CAN_F1R2_FB25_Msk /*!< Filter bit 25 */
+#define CAN_F1R2_FB26_Pos (26U)
+#define CAN_F1R2_FB26_Msk (0x1U << CAN_F1R2_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F1R2_FB26 CAN_F1R2_FB26_Msk /*!< Filter bit 26 */
+#define CAN_F1R2_FB27_Pos (27U)
+#define CAN_F1R2_FB27_Msk (0x1U << CAN_F1R2_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F1R2_FB27 CAN_F1R2_FB27_Msk /*!< Filter bit 27 */
+#define CAN_F1R2_FB28_Pos (28U)
+#define CAN_F1R2_FB28_Msk (0x1U << CAN_F1R2_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F1R2_FB28 CAN_F1R2_FB28_Msk /*!< Filter bit 28 */
+#define CAN_F1R2_FB29_Pos (29U)
+#define CAN_F1R2_FB29_Msk (0x1U << CAN_F1R2_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F1R2_FB29 CAN_F1R2_FB29_Msk /*!< Filter bit 29 */
+#define CAN_F1R2_FB30_Pos (30U)
+#define CAN_F1R2_FB30_Msk (0x1U << CAN_F1R2_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F1R2_FB30 CAN_F1R2_FB30_Msk /*!< Filter bit 30 */
+#define CAN_F1R2_FB31_Pos (31U)
+#define CAN_F1R2_FB31_Msk (0x1U << CAN_F1R2_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F1R2_FB31 CAN_F1R2_FB31_Msk /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F2R2 register *******************/
+#define CAN_F2R2_FB0_Pos (0U)
+#define CAN_F2R2_FB0_Msk (0x1U << CAN_F2R2_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F2R2_FB0 CAN_F2R2_FB0_Msk /*!< Filter bit 0 */
+#define CAN_F2R2_FB1_Pos (1U)
+#define CAN_F2R2_FB1_Msk (0x1U << CAN_F2R2_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F2R2_FB1 CAN_F2R2_FB1_Msk /*!< Filter bit 1 */
+#define CAN_F2R2_FB2_Pos (2U)
+#define CAN_F2R2_FB2_Msk (0x1U << CAN_F2R2_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F2R2_FB2 CAN_F2R2_FB2_Msk /*!< Filter bit 2 */
+#define CAN_F2R2_FB3_Pos (3U)
+#define CAN_F2R2_FB3_Msk (0x1U << CAN_F2R2_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F2R2_FB3 CAN_F2R2_FB3_Msk /*!< Filter bit 3 */
+#define CAN_F2R2_FB4_Pos (4U)
+#define CAN_F2R2_FB4_Msk (0x1U << CAN_F2R2_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F2R2_FB4 CAN_F2R2_FB4_Msk /*!< Filter bit 4 */
+#define CAN_F2R2_FB5_Pos (5U)
+#define CAN_F2R2_FB5_Msk (0x1U << CAN_F2R2_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F2R2_FB5 CAN_F2R2_FB5_Msk /*!< Filter bit 5 */
+#define CAN_F2R2_FB6_Pos (6U)
+#define CAN_F2R2_FB6_Msk (0x1U << CAN_F2R2_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F2R2_FB6 CAN_F2R2_FB6_Msk /*!< Filter bit 6 */
+#define CAN_F2R2_FB7_Pos (7U)
+#define CAN_F2R2_FB7_Msk (0x1U << CAN_F2R2_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F2R2_FB7 CAN_F2R2_FB7_Msk /*!< Filter bit 7 */
+#define CAN_F2R2_FB8_Pos (8U)
+#define CAN_F2R2_FB8_Msk (0x1U << CAN_F2R2_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F2R2_FB8 CAN_F2R2_FB8_Msk /*!< Filter bit 8 */
+#define CAN_F2R2_FB9_Pos (9U)
+#define CAN_F2R2_FB9_Msk (0x1U << CAN_F2R2_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F2R2_FB9 CAN_F2R2_FB9_Msk /*!< Filter bit 9 */
+#define CAN_F2R2_FB10_Pos (10U)
+#define CAN_F2R2_FB10_Msk (0x1U << CAN_F2R2_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F2R2_FB10 CAN_F2R2_FB10_Msk /*!< Filter bit 10 */
+#define CAN_F2R2_FB11_Pos (11U)
+#define CAN_F2R2_FB11_Msk (0x1U << CAN_F2R2_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F2R2_FB11 CAN_F2R2_FB11_Msk /*!< Filter bit 11 */
+#define CAN_F2R2_FB12_Pos (12U)
+#define CAN_F2R2_FB12_Msk (0x1U << CAN_F2R2_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F2R2_FB12 CAN_F2R2_FB12_Msk /*!< Filter bit 12 */
+#define CAN_F2R2_FB13_Pos (13U)
+#define CAN_F2R2_FB13_Msk (0x1U << CAN_F2R2_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F2R2_FB13 CAN_F2R2_FB13_Msk /*!< Filter bit 13 */
+#define CAN_F2R2_FB14_Pos (14U)
+#define CAN_F2R2_FB14_Msk (0x1U << CAN_F2R2_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F2R2_FB14 CAN_F2R2_FB14_Msk /*!< Filter bit 14 */
+#define CAN_F2R2_FB15_Pos (15U)
+#define CAN_F2R2_FB15_Msk (0x1U << CAN_F2R2_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F2R2_FB15 CAN_F2R2_FB15_Msk /*!< Filter bit 15 */
+#define CAN_F2R2_FB16_Pos (16U)
+#define CAN_F2R2_FB16_Msk (0x1U << CAN_F2R2_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F2R2_FB16 CAN_F2R2_FB16_Msk /*!< Filter bit 16 */
+#define CAN_F2R2_FB17_Pos (17U)
+#define CAN_F2R2_FB17_Msk (0x1U << CAN_F2R2_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F2R2_FB17 CAN_F2R2_FB17_Msk /*!< Filter bit 17 */
+#define CAN_F2R2_FB18_Pos (18U)
+#define CAN_F2R2_FB18_Msk (0x1U << CAN_F2R2_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F2R2_FB18 CAN_F2R2_FB18_Msk /*!< Filter bit 18 */
+#define CAN_F2R2_FB19_Pos (19U)
+#define CAN_F2R2_FB19_Msk (0x1U << CAN_F2R2_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F2R2_FB19 CAN_F2R2_FB19_Msk /*!< Filter bit 19 */
+#define CAN_F2R2_FB20_Pos (20U)
+#define CAN_F2R2_FB20_Msk (0x1U << CAN_F2R2_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F2R2_FB20 CAN_F2R2_FB20_Msk /*!< Filter bit 20 */
+#define CAN_F2R2_FB21_Pos (21U)
+#define CAN_F2R2_FB21_Msk (0x1U << CAN_F2R2_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F2R2_FB21 CAN_F2R2_FB21_Msk /*!< Filter bit 21 */
+#define CAN_F2R2_FB22_Pos (22U)
+#define CAN_F2R2_FB22_Msk (0x1U << CAN_F2R2_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F2R2_FB22 CAN_F2R2_FB22_Msk /*!< Filter bit 22 */
+#define CAN_F2R2_FB23_Pos (23U)
+#define CAN_F2R2_FB23_Msk (0x1U << CAN_F2R2_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F2R2_FB23 CAN_F2R2_FB23_Msk /*!< Filter bit 23 */
+#define CAN_F2R2_FB24_Pos (24U)
+#define CAN_F2R2_FB24_Msk (0x1U << CAN_F2R2_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F2R2_FB24 CAN_F2R2_FB24_Msk /*!< Filter bit 24 */
+#define CAN_F2R2_FB25_Pos (25U)
+#define CAN_F2R2_FB25_Msk (0x1U << CAN_F2R2_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F2R2_FB25 CAN_F2R2_FB25_Msk /*!< Filter bit 25 */
+#define CAN_F2R2_FB26_Pos (26U)
+#define CAN_F2R2_FB26_Msk (0x1U << CAN_F2R2_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F2R2_FB26 CAN_F2R2_FB26_Msk /*!< Filter bit 26 */
+#define CAN_F2R2_FB27_Pos (27U)
+#define CAN_F2R2_FB27_Msk (0x1U << CAN_F2R2_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F2R2_FB27 CAN_F2R2_FB27_Msk /*!< Filter bit 27 */
+#define CAN_F2R2_FB28_Pos (28U)
+#define CAN_F2R2_FB28_Msk (0x1U << CAN_F2R2_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F2R2_FB28 CAN_F2R2_FB28_Msk /*!< Filter bit 28 */
+#define CAN_F2R2_FB29_Pos (29U)
+#define CAN_F2R2_FB29_Msk (0x1U << CAN_F2R2_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F2R2_FB29 CAN_F2R2_FB29_Msk /*!< Filter bit 29 */
+#define CAN_F2R2_FB30_Pos (30U)
+#define CAN_F2R2_FB30_Msk (0x1U << CAN_F2R2_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F2R2_FB30 CAN_F2R2_FB30_Msk /*!< Filter bit 30 */
+#define CAN_F2R2_FB31_Pos (31U)
+#define CAN_F2R2_FB31_Msk (0x1U << CAN_F2R2_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F2R2_FB31 CAN_F2R2_FB31_Msk /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F3R2 register *******************/
+#define CAN_F3R2_FB0_Pos (0U)
+#define CAN_F3R2_FB0_Msk (0x1U << CAN_F3R2_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F3R2_FB0 CAN_F3R2_FB0_Msk /*!< Filter bit 0 */
+#define CAN_F3R2_FB1_Pos (1U)
+#define CAN_F3R2_FB1_Msk (0x1U << CAN_F3R2_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F3R2_FB1 CAN_F3R2_FB1_Msk /*!< Filter bit 1 */
+#define CAN_F3R2_FB2_Pos (2U)
+#define CAN_F3R2_FB2_Msk (0x1U << CAN_F3R2_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F3R2_FB2 CAN_F3R2_FB2_Msk /*!< Filter bit 2 */
+#define CAN_F3R2_FB3_Pos (3U)
+#define CAN_F3R2_FB3_Msk (0x1U << CAN_F3R2_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F3R2_FB3 CAN_F3R2_FB3_Msk /*!< Filter bit 3 */
+#define CAN_F3R2_FB4_Pos (4U)
+#define CAN_F3R2_FB4_Msk (0x1U << CAN_F3R2_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F3R2_FB4 CAN_F3R2_FB4_Msk /*!< Filter bit 4 */
+#define CAN_F3R2_FB5_Pos (5U)
+#define CAN_F3R2_FB5_Msk (0x1U << CAN_F3R2_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F3R2_FB5 CAN_F3R2_FB5_Msk /*!< Filter bit 5 */
+#define CAN_F3R2_FB6_Pos (6U)
+#define CAN_F3R2_FB6_Msk (0x1U << CAN_F3R2_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F3R2_FB6 CAN_F3R2_FB6_Msk /*!< Filter bit 6 */
+#define CAN_F3R2_FB7_Pos (7U)
+#define CAN_F3R2_FB7_Msk (0x1U << CAN_F3R2_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F3R2_FB7 CAN_F3R2_FB7_Msk /*!< Filter bit 7 */
+#define CAN_F3R2_FB8_Pos (8U)
+#define CAN_F3R2_FB8_Msk (0x1U << CAN_F3R2_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F3R2_FB8 CAN_F3R2_FB8_Msk /*!< Filter bit 8 */
+#define CAN_F3R2_FB9_Pos (9U)
+#define CAN_F3R2_FB9_Msk (0x1U << CAN_F3R2_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F3R2_FB9 CAN_F3R2_FB9_Msk /*!< Filter bit 9 */
+#define CAN_F3R2_FB10_Pos (10U)
+#define CAN_F3R2_FB10_Msk (0x1U << CAN_F3R2_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F3R2_FB10 CAN_F3R2_FB10_Msk /*!< Filter bit 10 */
+#define CAN_F3R2_FB11_Pos (11U)
+#define CAN_F3R2_FB11_Msk (0x1U << CAN_F3R2_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F3R2_FB11 CAN_F3R2_FB11_Msk /*!< Filter bit 11 */
+#define CAN_F3R2_FB12_Pos (12U)
+#define CAN_F3R2_FB12_Msk (0x1U << CAN_F3R2_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F3R2_FB12 CAN_F3R2_FB12_Msk /*!< Filter bit 12 */
+#define CAN_F3R2_FB13_Pos (13U)
+#define CAN_F3R2_FB13_Msk (0x1U << CAN_F3R2_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F3R2_FB13 CAN_F3R2_FB13_Msk /*!< Filter bit 13 */
+#define CAN_F3R2_FB14_Pos (14U)
+#define CAN_F3R2_FB14_Msk (0x1U << CAN_F3R2_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F3R2_FB14 CAN_F3R2_FB14_Msk /*!< Filter bit 14 */
+#define CAN_F3R2_FB15_Pos (15U)
+#define CAN_F3R2_FB15_Msk (0x1U << CAN_F3R2_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F3R2_FB15 CAN_F3R2_FB15_Msk /*!< Filter bit 15 */
+#define CAN_F3R2_FB16_Pos (16U)
+#define CAN_F3R2_FB16_Msk (0x1U << CAN_F3R2_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F3R2_FB16 CAN_F3R2_FB16_Msk /*!< Filter bit 16 */
+#define CAN_F3R2_FB17_Pos (17U)
+#define CAN_F3R2_FB17_Msk (0x1U << CAN_F3R2_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F3R2_FB17 CAN_F3R2_FB17_Msk /*!< Filter bit 17 */
+#define CAN_F3R2_FB18_Pos (18U)
+#define CAN_F3R2_FB18_Msk (0x1U << CAN_F3R2_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F3R2_FB18 CAN_F3R2_FB18_Msk /*!< Filter bit 18 */
+#define CAN_F3R2_FB19_Pos (19U)
+#define CAN_F3R2_FB19_Msk (0x1U << CAN_F3R2_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F3R2_FB19 CAN_F3R2_FB19_Msk /*!< Filter bit 19 */
+#define CAN_F3R2_FB20_Pos (20U)
+#define CAN_F3R2_FB20_Msk (0x1U << CAN_F3R2_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F3R2_FB20 CAN_F3R2_FB20_Msk /*!< Filter bit 20 */
+#define CAN_F3R2_FB21_Pos (21U)
+#define CAN_F3R2_FB21_Msk (0x1U << CAN_F3R2_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F3R2_FB21 CAN_F3R2_FB21_Msk /*!< Filter bit 21 */
+#define CAN_F3R2_FB22_Pos (22U)
+#define CAN_F3R2_FB22_Msk (0x1U << CAN_F3R2_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F3R2_FB22 CAN_F3R2_FB22_Msk /*!< Filter bit 22 */
+#define CAN_F3R2_FB23_Pos (23U)
+#define CAN_F3R2_FB23_Msk (0x1U << CAN_F3R2_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F3R2_FB23 CAN_F3R2_FB23_Msk /*!< Filter bit 23 */
+#define CAN_F3R2_FB24_Pos (24U)
+#define CAN_F3R2_FB24_Msk (0x1U << CAN_F3R2_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F3R2_FB24 CAN_F3R2_FB24_Msk /*!< Filter bit 24 */
+#define CAN_F3R2_FB25_Pos (25U)
+#define CAN_F3R2_FB25_Msk (0x1U << CAN_F3R2_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F3R2_FB25 CAN_F3R2_FB25_Msk /*!< Filter bit 25 */
+#define CAN_F3R2_FB26_Pos (26U)
+#define CAN_F3R2_FB26_Msk (0x1U << CAN_F3R2_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F3R2_FB26 CAN_F3R2_FB26_Msk /*!< Filter bit 26 */
+#define CAN_F3R2_FB27_Pos (27U)
+#define CAN_F3R2_FB27_Msk (0x1U << CAN_F3R2_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F3R2_FB27 CAN_F3R2_FB27_Msk /*!< Filter bit 27 */
+#define CAN_F3R2_FB28_Pos (28U)
+#define CAN_F3R2_FB28_Msk (0x1U << CAN_F3R2_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F3R2_FB28 CAN_F3R2_FB28_Msk /*!< Filter bit 28 */
+#define CAN_F3R2_FB29_Pos (29U)
+#define CAN_F3R2_FB29_Msk (0x1U << CAN_F3R2_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F3R2_FB29 CAN_F3R2_FB29_Msk /*!< Filter bit 29 */
+#define CAN_F3R2_FB30_Pos (30U)
+#define CAN_F3R2_FB30_Msk (0x1U << CAN_F3R2_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F3R2_FB30 CAN_F3R2_FB30_Msk /*!< Filter bit 30 */
+#define CAN_F3R2_FB31_Pos (31U)
+#define CAN_F3R2_FB31_Msk (0x1U << CAN_F3R2_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F3R2_FB31 CAN_F3R2_FB31_Msk /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F4R2 register *******************/
+#define CAN_F4R2_FB0_Pos (0U)
+#define CAN_F4R2_FB0_Msk (0x1U << CAN_F4R2_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F4R2_FB0 CAN_F4R2_FB0_Msk /*!< Filter bit 0 */
+#define CAN_F4R2_FB1_Pos (1U)
+#define CAN_F4R2_FB1_Msk (0x1U << CAN_F4R2_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F4R2_FB1 CAN_F4R2_FB1_Msk /*!< Filter bit 1 */
+#define CAN_F4R2_FB2_Pos (2U)
+#define CAN_F4R2_FB2_Msk (0x1U << CAN_F4R2_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F4R2_FB2 CAN_F4R2_FB2_Msk /*!< Filter bit 2 */
+#define CAN_F4R2_FB3_Pos (3U)
+#define CAN_F4R2_FB3_Msk (0x1U << CAN_F4R2_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F4R2_FB3 CAN_F4R2_FB3_Msk /*!< Filter bit 3 */
+#define CAN_F4R2_FB4_Pos (4U)
+#define CAN_F4R2_FB4_Msk (0x1U << CAN_F4R2_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F4R2_FB4 CAN_F4R2_FB4_Msk /*!< Filter bit 4 */
+#define CAN_F4R2_FB5_Pos (5U)
+#define CAN_F4R2_FB5_Msk (0x1U << CAN_F4R2_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F4R2_FB5 CAN_F4R2_FB5_Msk /*!< Filter bit 5 */
+#define CAN_F4R2_FB6_Pos (6U)
+#define CAN_F4R2_FB6_Msk (0x1U << CAN_F4R2_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F4R2_FB6 CAN_F4R2_FB6_Msk /*!< Filter bit 6 */
+#define CAN_F4R2_FB7_Pos (7U)
+#define CAN_F4R2_FB7_Msk (0x1U << CAN_F4R2_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F4R2_FB7 CAN_F4R2_FB7_Msk /*!< Filter bit 7 */
+#define CAN_F4R2_FB8_Pos (8U)
+#define CAN_F4R2_FB8_Msk (0x1U << CAN_F4R2_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F4R2_FB8 CAN_F4R2_FB8_Msk /*!< Filter bit 8 */
+#define CAN_F4R2_FB9_Pos (9U)
+#define CAN_F4R2_FB9_Msk (0x1U << CAN_F4R2_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F4R2_FB9 CAN_F4R2_FB9_Msk /*!< Filter bit 9 */
+#define CAN_F4R2_FB10_Pos (10U)
+#define CAN_F4R2_FB10_Msk (0x1U << CAN_F4R2_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F4R2_FB10 CAN_F4R2_FB10_Msk /*!< Filter bit 10 */
+#define CAN_F4R2_FB11_Pos (11U)
+#define CAN_F4R2_FB11_Msk (0x1U << CAN_F4R2_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F4R2_FB11 CAN_F4R2_FB11_Msk /*!< Filter bit 11 */
+#define CAN_F4R2_FB12_Pos (12U)
+#define CAN_F4R2_FB12_Msk (0x1U << CAN_F4R2_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F4R2_FB12 CAN_F4R2_FB12_Msk /*!< Filter bit 12 */
+#define CAN_F4R2_FB13_Pos (13U)
+#define CAN_F4R2_FB13_Msk (0x1U << CAN_F4R2_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F4R2_FB13 CAN_F4R2_FB13_Msk /*!< Filter bit 13 */
+#define CAN_F4R2_FB14_Pos (14U)
+#define CAN_F4R2_FB14_Msk (0x1U << CAN_F4R2_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F4R2_FB14 CAN_F4R2_FB14_Msk /*!< Filter bit 14 */
+#define CAN_F4R2_FB15_Pos (15U)
+#define CAN_F4R2_FB15_Msk (0x1U << CAN_F4R2_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F4R2_FB15 CAN_F4R2_FB15_Msk /*!< Filter bit 15 */
+#define CAN_F4R2_FB16_Pos (16U)
+#define CAN_F4R2_FB16_Msk (0x1U << CAN_F4R2_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F4R2_FB16 CAN_F4R2_FB16_Msk /*!< Filter bit 16 */
+#define CAN_F4R2_FB17_Pos (17U)
+#define CAN_F4R2_FB17_Msk (0x1U << CAN_F4R2_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F4R2_FB17 CAN_F4R2_FB17_Msk /*!< Filter bit 17 */
+#define CAN_F4R2_FB18_Pos (18U)
+#define CAN_F4R2_FB18_Msk (0x1U << CAN_F4R2_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F4R2_FB18 CAN_F4R2_FB18_Msk /*!< Filter bit 18 */
+#define CAN_F4R2_FB19_Pos (19U)
+#define CAN_F4R2_FB19_Msk (0x1U << CAN_F4R2_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F4R2_FB19 CAN_F4R2_FB19_Msk /*!< Filter bit 19 */
+#define CAN_F4R2_FB20_Pos (20U)
+#define CAN_F4R2_FB20_Msk (0x1U << CAN_F4R2_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F4R2_FB20 CAN_F4R2_FB20_Msk /*!< Filter bit 20 */
+#define CAN_F4R2_FB21_Pos (21U)
+#define CAN_F4R2_FB21_Msk (0x1U << CAN_F4R2_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F4R2_FB21 CAN_F4R2_FB21_Msk /*!< Filter bit 21 */
+#define CAN_F4R2_FB22_Pos (22U)
+#define CAN_F4R2_FB22_Msk (0x1U << CAN_F4R2_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F4R2_FB22 CAN_F4R2_FB22_Msk /*!< Filter bit 22 */
+#define CAN_F4R2_FB23_Pos (23U)
+#define CAN_F4R2_FB23_Msk (0x1U << CAN_F4R2_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F4R2_FB23 CAN_F4R2_FB23_Msk /*!< Filter bit 23 */
+#define CAN_F4R2_FB24_Pos (24U)
+#define CAN_F4R2_FB24_Msk (0x1U << CAN_F4R2_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F4R2_FB24 CAN_F4R2_FB24_Msk /*!< Filter bit 24 */
+#define CAN_F4R2_FB25_Pos (25U)
+#define CAN_F4R2_FB25_Msk (0x1U << CAN_F4R2_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F4R2_FB25 CAN_F4R2_FB25_Msk /*!< Filter bit 25 */
+#define CAN_F4R2_FB26_Pos (26U)
+#define CAN_F4R2_FB26_Msk (0x1U << CAN_F4R2_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F4R2_FB26 CAN_F4R2_FB26_Msk /*!< Filter bit 26 */
+#define CAN_F4R2_FB27_Pos (27U)
+#define CAN_F4R2_FB27_Msk (0x1U << CAN_F4R2_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F4R2_FB27 CAN_F4R2_FB27_Msk /*!< Filter bit 27 */
+#define CAN_F4R2_FB28_Pos (28U)
+#define CAN_F4R2_FB28_Msk (0x1U << CAN_F4R2_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F4R2_FB28 CAN_F4R2_FB28_Msk /*!< Filter bit 28 */
+#define CAN_F4R2_FB29_Pos (29U)
+#define CAN_F4R2_FB29_Msk (0x1U << CAN_F4R2_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F4R2_FB29 CAN_F4R2_FB29_Msk /*!< Filter bit 29 */
+#define CAN_F4R2_FB30_Pos (30U)
+#define CAN_F4R2_FB30_Msk (0x1U << CAN_F4R2_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F4R2_FB30 CAN_F4R2_FB30_Msk /*!< Filter bit 30 */
+#define CAN_F4R2_FB31_Pos (31U)
+#define CAN_F4R2_FB31_Msk (0x1U << CAN_F4R2_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F4R2_FB31 CAN_F4R2_FB31_Msk /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F5R2 register *******************/
+#define CAN_F5R2_FB0_Pos (0U)
+#define CAN_F5R2_FB0_Msk (0x1U << CAN_F5R2_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F5R2_FB0 CAN_F5R2_FB0_Msk /*!< Filter bit 0 */
+#define CAN_F5R2_FB1_Pos (1U)
+#define CAN_F5R2_FB1_Msk (0x1U << CAN_F5R2_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F5R2_FB1 CAN_F5R2_FB1_Msk /*!< Filter bit 1 */
+#define CAN_F5R2_FB2_Pos (2U)
+#define CAN_F5R2_FB2_Msk (0x1U << CAN_F5R2_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F5R2_FB2 CAN_F5R2_FB2_Msk /*!< Filter bit 2 */
+#define CAN_F5R2_FB3_Pos (3U)
+#define CAN_F5R2_FB3_Msk (0x1U << CAN_F5R2_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F5R2_FB3 CAN_F5R2_FB3_Msk /*!< Filter bit 3 */
+#define CAN_F5R2_FB4_Pos (4U)
+#define CAN_F5R2_FB4_Msk (0x1U << CAN_F5R2_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F5R2_FB4 CAN_F5R2_FB4_Msk /*!< Filter bit 4 */
+#define CAN_F5R2_FB5_Pos (5U)
+#define CAN_F5R2_FB5_Msk (0x1U << CAN_F5R2_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F5R2_FB5 CAN_F5R2_FB5_Msk /*!< Filter bit 5 */
+#define CAN_F5R2_FB6_Pos (6U)
+#define CAN_F5R2_FB6_Msk (0x1U << CAN_F5R2_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F5R2_FB6 CAN_F5R2_FB6_Msk /*!< Filter bit 6 */
+#define CAN_F5R2_FB7_Pos (7U)
+#define CAN_F5R2_FB7_Msk (0x1U << CAN_F5R2_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F5R2_FB7 CAN_F5R2_FB7_Msk /*!< Filter bit 7 */
+#define CAN_F5R2_FB8_Pos (8U)
+#define CAN_F5R2_FB8_Msk (0x1U << CAN_F5R2_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F5R2_FB8 CAN_F5R2_FB8_Msk /*!< Filter bit 8 */
+#define CAN_F5R2_FB9_Pos (9U)
+#define CAN_F5R2_FB9_Msk (0x1U << CAN_F5R2_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F5R2_FB9 CAN_F5R2_FB9_Msk /*!< Filter bit 9 */
+#define CAN_F5R2_FB10_Pos (10U)
+#define CAN_F5R2_FB10_Msk (0x1U << CAN_F5R2_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F5R2_FB10 CAN_F5R2_FB10_Msk /*!< Filter bit 10 */
+#define CAN_F5R2_FB11_Pos (11U)
+#define CAN_F5R2_FB11_Msk (0x1U << CAN_F5R2_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F5R2_FB11 CAN_F5R2_FB11_Msk /*!< Filter bit 11 */
+#define CAN_F5R2_FB12_Pos (12U)
+#define CAN_F5R2_FB12_Msk (0x1U << CAN_F5R2_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F5R2_FB12 CAN_F5R2_FB12_Msk /*!< Filter bit 12 */
+#define CAN_F5R2_FB13_Pos (13U)
+#define CAN_F5R2_FB13_Msk (0x1U << CAN_F5R2_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F5R2_FB13 CAN_F5R2_FB13_Msk /*!< Filter bit 13 */
+#define CAN_F5R2_FB14_Pos (14U)
+#define CAN_F5R2_FB14_Msk (0x1U << CAN_F5R2_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F5R2_FB14 CAN_F5R2_FB14_Msk /*!< Filter bit 14 */
+#define CAN_F5R2_FB15_Pos (15U)
+#define CAN_F5R2_FB15_Msk (0x1U << CAN_F5R2_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F5R2_FB15 CAN_F5R2_FB15_Msk /*!< Filter bit 15 */
+#define CAN_F5R2_FB16_Pos (16U)
+#define CAN_F5R2_FB16_Msk (0x1U << CAN_F5R2_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F5R2_FB16 CAN_F5R2_FB16_Msk /*!< Filter bit 16 */
+#define CAN_F5R2_FB17_Pos (17U)
+#define CAN_F5R2_FB17_Msk (0x1U << CAN_F5R2_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F5R2_FB17 CAN_F5R2_FB17_Msk /*!< Filter bit 17 */
+#define CAN_F5R2_FB18_Pos (18U)
+#define CAN_F5R2_FB18_Msk (0x1U << CAN_F5R2_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F5R2_FB18 CAN_F5R2_FB18_Msk /*!< Filter bit 18 */
+#define CAN_F5R2_FB19_Pos (19U)
+#define CAN_F5R2_FB19_Msk (0x1U << CAN_F5R2_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F5R2_FB19 CAN_F5R2_FB19_Msk /*!< Filter bit 19 */
+#define CAN_F5R2_FB20_Pos (20U)
+#define CAN_F5R2_FB20_Msk (0x1U << CAN_F5R2_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F5R2_FB20 CAN_F5R2_FB20_Msk /*!< Filter bit 20 */
+#define CAN_F5R2_FB21_Pos (21U)
+#define CAN_F5R2_FB21_Msk (0x1U << CAN_F5R2_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F5R2_FB21 CAN_F5R2_FB21_Msk /*!< Filter bit 21 */
+#define CAN_F5R2_FB22_Pos (22U)
+#define CAN_F5R2_FB22_Msk (0x1U << CAN_F5R2_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F5R2_FB22 CAN_F5R2_FB22_Msk /*!< Filter bit 22 */
+#define CAN_F5R2_FB23_Pos (23U)
+#define CAN_F5R2_FB23_Msk (0x1U << CAN_F5R2_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F5R2_FB23 CAN_F5R2_FB23_Msk /*!< Filter bit 23 */
+#define CAN_F5R2_FB24_Pos (24U)
+#define CAN_F5R2_FB24_Msk (0x1U << CAN_F5R2_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F5R2_FB24 CAN_F5R2_FB24_Msk /*!< Filter bit 24 */
+#define CAN_F5R2_FB25_Pos (25U)
+#define CAN_F5R2_FB25_Msk (0x1U << CAN_F5R2_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F5R2_FB25 CAN_F5R2_FB25_Msk /*!< Filter bit 25 */
+#define CAN_F5R2_FB26_Pos (26U)
+#define CAN_F5R2_FB26_Msk (0x1U << CAN_F5R2_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F5R2_FB26 CAN_F5R2_FB26_Msk /*!< Filter bit 26 */
+#define CAN_F5R2_FB27_Pos (27U)
+#define CAN_F5R2_FB27_Msk (0x1U << CAN_F5R2_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F5R2_FB27 CAN_F5R2_FB27_Msk /*!< Filter bit 27 */
+#define CAN_F5R2_FB28_Pos (28U)
+#define CAN_F5R2_FB28_Msk (0x1U << CAN_F5R2_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F5R2_FB28 CAN_F5R2_FB28_Msk /*!< Filter bit 28 */
+#define CAN_F5R2_FB29_Pos (29U)
+#define CAN_F5R2_FB29_Msk (0x1U << CAN_F5R2_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F5R2_FB29 CAN_F5R2_FB29_Msk /*!< Filter bit 29 */
+#define CAN_F5R2_FB30_Pos (30U)
+#define CAN_F5R2_FB30_Msk (0x1U << CAN_F5R2_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F5R2_FB30 CAN_F5R2_FB30_Msk /*!< Filter bit 30 */
+#define CAN_F5R2_FB31_Pos (31U)
+#define CAN_F5R2_FB31_Msk (0x1U << CAN_F5R2_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F5R2_FB31 CAN_F5R2_FB31_Msk /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F6R2 register *******************/
+#define CAN_F6R2_FB0_Pos (0U)
+#define CAN_F6R2_FB0_Msk (0x1U << CAN_F6R2_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F6R2_FB0 CAN_F6R2_FB0_Msk /*!< Filter bit 0 */
+#define CAN_F6R2_FB1_Pos (1U)
+#define CAN_F6R2_FB1_Msk (0x1U << CAN_F6R2_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F6R2_FB1 CAN_F6R2_FB1_Msk /*!< Filter bit 1 */
+#define CAN_F6R2_FB2_Pos (2U)
+#define CAN_F6R2_FB2_Msk (0x1U << CAN_F6R2_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F6R2_FB2 CAN_F6R2_FB2_Msk /*!< Filter bit 2 */
+#define CAN_F6R2_FB3_Pos (3U)
+#define CAN_F6R2_FB3_Msk (0x1U << CAN_F6R2_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F6R2_FB3 CAN_F6R2_FB3_Msk /*!< Filter bit 3 */
+#define CAN_F6R2_FB4_Pos (4U)
+#define CAN_F6R2_FB4_Msk (0x1U << CAN_F6R2_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F6R2_FB4 CAN_F6R2_FB4_Msk /*!< Filter bit 4 */
+#define CAN_F6R2_FB5_Pos (5U)
+#define CAN_F6R2_FB5_Msk (0x1U << CAN_F6R2_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F6R2_FB5 CAN_F6R2_FB5_Msk /*!< Filter bit 5 */
+#define CAN_F6R2_FB6_Pos (6U)
+#define CAN_F6R2_FB6_Msk (0x1U << CAN_F6R2_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F6R2_FB6 CAN_F6R2_FB6_Msk /*!< Filter bit 6 */
+#define CAN_F6R2_FB7_Pos (7U)
+#define CAN_F6R2_FB7_Msk (0x1U << CAN_F6R2_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F6R2_FB7 CAN_F6R2_FB7_Msk /*!< Filter bit 7 */
+#define CAN_F6R2_FB8_Pos (8U)
+#define CAN_F6R2_FB8_Msk (0x1U << CAN_F6R2_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F6R2_FB8 CAN_F6R2_FB8_Msk /*!< Filter bit 8 */
+#define CAN_F6R2_FB9_Pos (9U)
+#define CAN_F6R2_FB9_Msk (0x1U << CAN_F6R2_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F6R2_FB9 CAN_F6R2_FB9_Msk /*!< Filter bit 9 */
+#define CAN_F6R2_FB10_Pos (10U)
+#define CAN_F6R2_FB10_Msk (0x1U << CAN_F6R2_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F6R2_FB10 CAN_F6R2_FB10_Msk /*!< Filter bit 10 */
+#define CAN_F6R2_FB11_Pos (11U)
+#define CAN_F6R2_FB11_Msk (0x1U << CAN_F6R2_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F6R2_FB11 CAN_F6R2_FB11_Msk /*!< Filter bit 11 */
+#define CAN_F6R2_FB12_Pos (12U)
+#define CAN_F6R2_FB12_Msk (0x1U << CAN_F6R2_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F6R2_FB12 CAN_F6R2_FB12_Msk /*!< Filter bit 12 */
+#define CAN_F6R2_FB13_Pos (13U)
+#define CAN_F6R2_FB13_Msk (0x1U << CAN_F6R2_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F6R2_FB13 CAN_F6R2_FB13_Msk /*!< Filter bit 13 */
+#define CAN_F6R2_FB14_Pos (14U)
+#define CAN_F6R2_FB14_Msk (0x1U << CAN_F6R2_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F6R2_FB14 CAN_F6R2_FB14_Msk /*!< Filter bit 14 */
+#define CAN_F6R2_FB15_Pos (15U)
+#define CAN_F6R2_FB15_Msk (0x1U << CAN_F6R2_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F6R2_FB15 CAN_F6R2_FB15_Msk /*!< Filter bit 15 */
+#define CAN_F6R2_FB16_Pos (16U)
+#define CAN_F6R2_FB16_Msk (0x1U << CAN_F6R2_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F6R2_FB16 CAN_F6R2_FB16_Msk /*!< Filter bit 16 */
+#define CAN_F6R2_FB17_Pos (17U)
+#define CAN_F6R2_FB17_Msk (0x1U << CAN_F6R2_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F6R2_FB17 CAN_F6R2_FB17_Msk /*!< Filter bit 17 */
+#define CAN_F6R2_FB18_Pos (18U)
+#define CAN_F6R2_FB18_Msk (0x1U << CAN_F6R2_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F6R2_FB18 CAN_F6R2_FB18_Msk /*!< Filter bit 18 */
+#define CAN_F6R2_FB19_Pos (19U)
+#define CAN_F6R2_FB19_Msk (0x1U << CAN_F6R2_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F6R2_FB19 CAN_F6R2_FB19_Msk /*!< Filter bit 19 */
+#define CAN_F6R2_FB20_Pos (20U)
+#define CAN_F6R2_FB20_Msk (0x1U << CAN_F6R2_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F6R2_FB20 CAN_F6R2_FB20_Msk /*!< Filter bit 20 */
+#define CAN_F6R2_FB21_Pos (21U)
+#define CAN_F6R2_FB21_Msk (0x1U << CAN_F6R2_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F6R2_FB21 CAN_F6R2_FB21_Msk /*!< Filter bit 21 */
+#define CAN_F6R2_FB22_Pos (22U)
+#define CAN_F6R2_FB22_Msk (0x1U << CAN_F6R2_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F6R2_FB22 CAN_F6R2_FB22_Msk /*!< Filter bit 22 */
+#define CAN_F6R2_FB23_Pos (23U)
+#define CAN_F6R2_FB23_Msk (0x1U << CAN_F6R2_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F6R2_FB23 CAN_F6R2_FB23_Msk /*!< Filter bit 23 */
+#define CAN_F6R2_FB24_Pos (24U)
+#define CAN_F6R2_FB24_Msk (0x1U << CAN_F6R2_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F6R2_FB24 CAN_F6R2_FB24_Msk /*!< Filter bit 24 */
+#define CAN_F6R2_FB25_Pos (25U)
+#define CAN_F6R2_FB25_Msk (0x1U << CAN_F6R2_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F6R2_FB25 CAN_F6R2_FB25_Msk /*!< Filter bit 25 */
+#define CAN_F6R2_FB26_Pos (26U)
+#define CAN_F6R2_FB26_Msk (0x1U << CAN_F6R2_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F6R2_FB26 CAN_F6R2_FB26_Msk /*!< Filter bit 26 */
+#define CAN_F6R2_FB27_Pos (27U)
+#define CAN_F6R2_FB27_Msk (0x1U << CAN_F6R2_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F6R2_FB27 CAN_F6R2_FB27_Msk /*!< Filter bit 27 */
+#define CAN_F6R2_FB28_Pos (28U)
+#define CAN_F6R2_FB28_Msk (0x1U << CAN_F6R2_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F6R2_FB28 CAN_F6R2_FB28_Msk /*!< Filter bit 28 */
+#define CAN_F6R2_FB29_Pos (29U)
+#define CAN_F6R2_FB29_Msk (0x1U << CAN_F6R2_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F6R2_FB29 CAN_F6R2_FB29_Msk /*!< Filter bit 29 */
+#define CAN_F6R2_FB30_Pos (30U)
+#define CAN_F6R2_FB30_Msk (0x1U << CAN_F6R2_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F6R2_FB30 CAN_F6R2_FB30_Msk /*!< Filter bit 30 */
+#define CAN_F6R2_FB31_Pos (31U)
+#define CAN_F6R2_FB31_Msk (0x1U << CAN_F6R2_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F6R2_FB31 CAN_F6R2_FB31_Msk /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F7R2 register *******************/
+#define CAN_F7R2_FB0_Pos (0U)
+#define CAN_F7R2_FB0_Msk (0x1U << CAN_F7R2_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F7R2_FB0 CAN_F7R2_FB0_Msk /*!< Filter bit 0 */
+#define CAN_F7R2_FB1_Pos (1U)
+#define CAN_F7R2_FB1_Msk (0x1U << CAN_F7R2_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F7R2_FB1 CAN_F7R2_FB1_Msk /*!< Filter bit 1 */
+#define CAN_F7R2_FB2_Pos (2U)
+#define CAN_F7R2_FB2_Msk (0x1U << CAN_F7R2_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F7R2_FB2 CAN_F7R2_FB2_Msk /*!< Filter bit 2 */
+#define CAN_F7R2_FB3_Pos (3U)
+#define CAN_F7R2_FB3_Msk (0x1U << CAN_F7R2_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F7R2_FB3 CAN_F7R2_FB3_Msk /*!< Filter bit 3 */
+#define CAN_F7R2_FB4_Pos (4U)
+#define CAN_F7R2_FB4_Msk (0x1U << CAN_F7R2_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F7R2_FB4 CAN_F7R2_FB4_Msk /*!< Filter bit 4 */
+#define CAN_F7R2_FB5_Pos (5U)
+#define CAN_F7R2_FB5_Msk (0x1U << CAN_F7R2_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F7R2_FB5 CAN_F7R2_FB5_Msk /*!< Filter bit 5 */
+#define CAN_F7R2_FB6_Pos (6U)
+#define CAN_F7R2_FB6_Msk (0x1U << CAN_F7R2_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F7R2_FB6 CAN_F7R2_FB6_Msk /*!< Filter bit 6 */
+#define CAN_F7R2_FB7_Pos (7U)
+#define CAN_F7R2_FB7_Msk (0x1U << CAN_F7R2_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F7R2_FB7 CAN_F7R2_FB7_Msk /*!< Filter bit 7 */
+#define CAN_F7R2_FB8_Pos (8U)
+#define CAN_F7R2_FB8_Msk (0x1U << CAN_F7R2_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F7R2_FB8 CAN_F7R2_FB8_Msk /*!< Filter bit 8 */
+#define CAN_F7R2_FB9_Pos (9U)
+#define CAN_F7R2_FB9_Msk (0x1U << CAN_F7R2_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F7R2_FB9 CAN_F7R2_FB9_Msk /*!< Filter bit 9 */
+#define CAN_F7R2_FB10_Pos (10U)
+#define CAN_F7R2_FB10_Msk (0x1U << CAN_F7R2_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F7R2_FB10 CAN_F7R2_FB10_Msk /*!< Filter bit 10 */
+#define CAN_F7R2_FB11_Pos (11U)
+#define CAN_F7R2_FB11_Msk (0x1U << CAN_F7R2_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F7R2_FB11 CAN_F7R2_FB11_Msk /*!< Filter bit 11 */
+#define CAN_F7R2_FB12_Pos (12U)
+#define CAN_F7R2_FB12_Msk (0x1U << CAN_F7R2_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F7R2_FB12 CAN_F7R2_FB12_Msk /*!< Filter bit 12 */
+#define CAN_F7R2_FB13_Pos (13U)
+#define CAN_F7R2_FB13_Msk (0x1U << CAN_F7R2_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F7R2_FB13 CAN_F7R2_FB13_Msk /*!< Filter bit 13 */
+#define CAN_F7R2_FB14_Pos (14U)
+#define CAN_F7R2_FB14_Msk (0x1U << CAN_F7R2_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F7R2_FB14 CAN_F7R2_FB14_Msk /*!< Filter bit 14 */
+#define CAN_F7R2_FB15_Pos (15U)
+#define CAN_F7R2_FB15_Msk (0x1U << CAN_F7R2_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F7R2_FB15 CAN_F7R2_FB15_Msk /*!< Filter bit 15 */
+#define CAN_F7R2_FB16_Pos (16U)
+#define CAN_F7R2_FB16_Msk (0x1U << CAN_F7R2_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F7R2_FB16 CAN_F7R2_FB16_Msk /*!< Filter bit 16 */
+#define CAN_F7R2_FB17_Pos (17U)
+#define CAN_F7R2_FB17_Msk (0x1U << CAN_F7R2_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F7R2_FB17 CAN_F7R2_FB17_Msk /*!< Filter bit 17 */
+#define CAN_F7R2_FB18_Pos (18U)
+#define CAN_F7R2_FB18_Msk (0x1U << CAN_F7R2_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F7R2_FB18 CAN_F7R2_FB18_Msk /*!< Filter bit 18 */
+#define CAN_F7R2_FB19_Pos (19U)
+#define CAN_F7R2_FB19_Msk (0x1U << CAN_F7R2_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F7R2_FB19 CAN_F7R2_FB19_Msk /*!< Filter bit 19 */
+#define CAN_F7R2_FB20_Pos (20U)
+#define CAN_F7R2_FB20_Msk (0x1U << CAN_F7R2_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F7R2_FB20 CAN_F7R2_FB20_Msk /*!< Filter bit 20 */
+#define CAN_F7R2_FB21_Pos (21U)
+#define CAN_F7R2_FB21_Msk (0x1U << CAN_F7R2_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F7R2_FB21 CAN_F7R2_FB21_Msk /*!< Filter bit 21 */
+#define CAN_F7R2_FB22_Pos (22U)
+#define CAN_F7R2_FB22_Msk (0x1U << CAN_F7R2_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F7R2_FB22 CAN_F7R2_FB22_Msk /*!< Filter bit 22 */
+#define CAN_F7R2_FB23_Pos (23U)
+#define CAN_F7R2_FB23_Msk (0x1U << CAN_F7R2_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F7R2_FB23 CAN_F7R2_FB23_Msk /*!< Filter bit 23 */
+#define CAN_F7R2_FB24_Pos (24U)
+#define CAN_F7R2_FB24_Msk (0x1U << CAN_F7R2_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F7R2_FB24 CAN_F7R2_FB24_Msk /*!< Filter bit 24 */
+#define CAN_F7R2_FB25_Pos (25U)
+#define CAN_F7R2_FB25_Msk (0x1U << CAN_F7R2_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F7R2_FB25 CAN_F7R2_FB25_Msk /*!< Filter bit 25 */
+#define CAN_F7R2_FB26_Pos (26U)
+#define CAN_F7R2_FB26_Msk (0x1U << CAN_F7R2_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F7R2_FB26 CAN_F7R2_FB26_Msk /*!< Filter bit 26 */
+#define CAN_F7R2_FB27_Pos (27U)
+#define CAN_F7R2_FB27_Msk (0x1U << CAN_F7R2_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F7R2_FB27 CAN_F7R2_FB27_Msk /*!< Filter bit 27 */
+#define CAN_F7R2_FB28_Pos (28U)
+#define CAN_F7R2_FB28_Msk (0x1U << CAN_F7R2_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F7R2_FB28 CAN_F7R2_FB28_Msk /*!< Filter bit 28 */
+#define CAN_F7R2_FB29_Pos (29U)
+#define CAN_F7R2_FB29_Msk (0x1U << CAN_F7R2_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F7R2_FB29 CAN_F7R2_FB29_Msk /*!< Filter bit 29 */
+#define CAN_F7R2_FB30_Pos (30U)
+#define CAN_F7R2_FB30_Msk (0x1U << CAN_F7R2_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F7R2_FB30 CAN_F7R2_FB30_Msk /*!< Filter bit 30 */
+#define CAN_F7R2_FB31_Pos (31U)
+#define CAN_F7R2_FB31_Msk (0x1U << CAN_F7R2_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F7R2_FB31 CAN_F7R2_FB31_Msk /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F8R2 register *******************/
+#define CAN_F8R2_FB0_Pos (0U)
+#define CAN_F8R2_FB0_Msk (0x1U << CAN_F8R2_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F8R2_FB0 CAN_F8R2_FB0_Msk /*!< Filter bit 0 */
+#define CAN_F8R2_FB1_Pos (1U)
+#define CAN_F8R2_FB1_Msk (0x1U << CAN_F8R2_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F8R2_FB1 CAN_F8R2_FB1_Msk /*!< Filter bit 1 */
+#define CAN_F8R2_FB2_Pos (2U)
+#define CAN_F8R2_FB2_Msk (0x1U << CAN_F8R2_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F8R2_FB2 CAN_F8R2_FB2_Msk /*!< Filter bit 2 */
+#define CAN_F8R2_FB3_Pos (3U)
+#define CAN_F8R2_FB3_Msk (0x1U << CAN_F8R2_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F8R2_FB3 CAN_F8R2_FB3_Msk /*!< Filter bit 3 */
+#define CAN_F8R2_FB4_Pos (4U)
+#define CAN_F8R2_FB4_Msk (0x1U << CAN_F8R2_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F8R2_FB4 CAN_F8R2_FB4_Msk /*!< Filter bit 4 */
+#define CAN_F8R2_FB5_Pos (5U)
+#define CAN_F8R2_FB5_Msk (0x1U << CAN_F8R2_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F8R2_FB5 CAN_F8R2_FB5_Msk /*!< Filter bit 5 */
+#define CAN_F8R2_FB6_Pos (6U)
+#define CAN_F8R2_FB6_Msk (0x1U << CAN_F8R2_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F8R2_FB6 CAN_F8R2_FB6_Msk /*!< Filter bit 6 */
+#define CAN_F8R2_FB7_Pos (7U)
+#define CAN_F8R2_FB7_Msk (0x1U << CAN_F8R2_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F8R2_FB7 CAN_F8R2_FB7_Msk /*!< Filter bit 7 */
+#define CAN_F8R2_FB8_Pos (8U)
+#define CAN_F8R2_FB8_Msk (0x1U << CAN_F8R2_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F8R2_FB8 CAN_F8R2_FB8_Msk /*!< Filter bit 8 */
+#define CAN_F8R2_FB9_Pos (9U)
+#define CAN_F8R2_FB9_Msk (0x1U << CAN_F8R2_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F8R2_FB9 CAN_F8R2_FB9_Msk /*!< Filter bit 9 */
+#define CAN_F8R2_FB10_Pos (10U)
+#define CAN_F8R2_FB10_Msk (0x1U << CAN_F8R2_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F8R2_FB10 CAN_F8R2_FB10_Msk /*!< Filter bit 10 */
+#define CAN_F8R2_FB11_Pos (11U)
+#define CAN_F8R2_FB11_Msk (0x1U << CAN_F8R2_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F8R2_FB11 CAN_F8R2_FB11_Msk /*!< Filter bit 11 */
+#define CAN_F8R2_FB12_Pos (12U)
+#define CAN_F8R2_FB12_Msk (0x1U << CAN_F8R2_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F8R2_FB12 CAN_F8R2_FB12_Msk /*!< Filter bit 12 */
+#define CAN_F8R2_FB13_Pos (13U)
+#define CAN_F8R2_FB13_Msk (0x1U << CAN_F8R2_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F8R2_FB13 CAN_F8R2_FB13_Msk /*!< Filter bit 13 */
+#define CAN_F8R2_FB14_Pos (14U)
+#define CAN_F8R2_FB14_Msk (0x1U << CAN_F8R2_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F8R2_FB14 CAN_F8R2_FB14_Msk /*!< Filter bit 14 */
+#define CAN_F8R2_FB15_Pos (15U)
+#define CAN_F8R2_FB15_Msk (0x1U << CAN_F8R2_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F8R2_FB15 CAN_F8R2_FB15_Msk /*!< Filter bit 15 */
+#define CAN_F8R2_FB16_Pos (16U)
+#define CAN_F8R2_FB16_Msk (0x1U << CAN_F8R2_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F8R2_FB16 CAN_F8R2_FB16_Msk /*!< Filter bit 16 */
+#define CAN_F8R2_FB17_Pos (17U)
+#define CAN_F8R2_FB17_Msk (0x1U << CAN_F8R2_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F8R2_FB17 CAN_F8R2_FB17_Msk /*!< Filter bit 17 */
+#define CAN_F8R2_FB18_Pos (18U)
+#define CAN_F8R2_FB18_Msk (0x1U << CAN_F8R2_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F8R2_FB18 CAN_F8R2_FB18_Msk /*!< Filter bit 18 */
+#define CAN_F8R2_FB19_Pos (19U)
+#define CAN_F8R2_FB19_Msk (0x1U << CAN_F8R2_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F8R2_FB19 CAN_F8R2_FB19_Msk /*!< Filter bit 19 */
+#define CAN_F8R2_FB20_Pos (20U)
+#define CAN_F8R2_FB20_Msk (0x1U << CAN_F8R2_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F8R2_FB20 CAN_F8R2_FB20_Msk /*!< Filter bit 20 */
+#define CAN_F8R2_FB21_Pos (21U)
+#define CAN_F8R2_FB21_Msk (0x1U << CAN_F8R2_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F8R2_FB21 CAN_F8R2_FB21_Msk /*!< Filter bit 21 */
+#define CAN_F8R2_FB22_Pos (22U)
+#define CAN_F8R2_FB22_Msk (0x1U << CAN_F8R2_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F8R2_FB22 CAN_F8R2_FB22_Msk /*!< Filter bit 22 */
+#define CAN_F8R2_FB23_Pos (23U)
+#define CAN_F8R2_FB23_Msk (0x1U << CAN_F8R2_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F8R2_FB23 CAN_F8R2_FB23_Msk /*!< Filter bit 23 */
+#define CAN_F8R2_FB24_Pos (24U)
+#define CAN_F8R2_FB24_Msk (0x1U << CAN_F8R2_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F8R2_FB24 CAN_F8R2_FB24_Msk /*!< Filter bit 24 */
+#define CAN_F8R2_FB25_Pos (25U)
+#define CAN_F8R2_FB25_Msk (0x1U << CAN_F8R2_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F8R2_FB25 CAN_F8R2_FB25_Msk /*!< Filter bit 25 */
+#define CAN_F8R2_FB26_Pos (26U)
+#define CAN_F8R2_FB26_Msk (0x1U << CAN_F8R2_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F8R2_FB26 CAN_F8R2_FB26_Msk /*!< Filter bit 26 */
+#define CAN_F8R2_FB27_Pos (27U)
+#define CAN_F8R2_FB27_Msk (0x1U << CAN_F8R2_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F8R2_FB27 CAN_F8R2_FB27_Msk /*!< Filter bit 27 */
+#define CAN_F8R2_FB28_Pos (28U)
+#define CAN_F8R2_FB28_Msk (0x1U << CAN_F8R2_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F8R2_FB28 CAN_F8R2_FB28_Msk /*!< Filter bit 28 */
+#define CAN_F8R2_FB29_Pos (29U)
+#define CAN_F8R2_FB29_Msk (0x1U << CAN_F8R2_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F8R2_FB29 CAN_F8R2_FB29_Msk /*!< Filter bit 29 */
+#define CAN_F8R2_FB30_Pos (30U)
+#define CAN_F8R2_FB30_Msk (0x1U << CAN_F8R2_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F8R2_FB30 CAN_F8R2_FB30_Msk /*!< Filter bit 30 */
+#define CAN_F8R2_FB31_Pos (31U)
+#define CAN_F8R2_FB31_Msk (0x1U << CAN_F8R2_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F8R2_FB31 CAN_F8R2_FB31_Msk /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F9R2 register *******************/
+#define CAN_F9R2_FB0_Pos (0U)
+#define CAN_F9R2_FB0_Msk (0x1U << CAN_F9R2_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F9R2_FB0 CAN_F9R2_FB0_Msk /*!< Filter bit 0 */
+#define CAN_F9R2_FB1_Pos (1U)
+#define CAN_F9R2_FB1_Msk (0x1U << CAN_F9R2_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F9R2_FB1 CAN_F9R2_FB1_Msk /*!< Filter bit 1 */
+#define CAN_F9R2_FB2_Pos (2U)
+#define CAN_F9R2_FB2_Msk (0x1U << CAN_F9R2_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F9R2_FB2 CAN_F9R2_FB2_Msk /*!< Filter bit 2 */
+#define CAN_F9R2_FB3_Pos (3U)
+#define CAN_F9R2_FB3_Msk (0x1U << CAN_F9R2_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F9R2_FB3 CAN_F9R2_FB3_Msk /*!< Filter bit 3 */
+#define CAN_F9R2_FB4_Pos (4U)
+#define CAN_F9R2_FB4_Msk (0x1U << CAN_F9R2_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F9R2_FB4 CAN_F9R2_FB4_Msk /*!< Filter bit 4 */
+#define CAN_F9R2_FB5_Pos (5U)
+#define CAN_F9R2_FB5_Msk (0x1U << CAN_F9R2_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F9R2_FB5 CAN_F9R2_FB5_Msk /*!< Filter bit 5 */
+#define CAN_F9R2_FB6_Pos (6U)
+#define CAN_F9R2_FB6_Msk (0x1U << CAN_F9R2_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F9R2_FB6 CAN_F9R2_FB6_Msk /*!< Filter bit 6 */
+#define CAN_F9R2_FB7_Pos (7U)
+#define CAN_F9R2_FB7_Msk (0x1U << CAN_F9R2_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F9R2_FB7 CAN_F9R2_FB7_Msk /*!< Filter bit 7 */
+#define CAN_F9R2_FB8_Pos (8U)
+#define CAN_F9R2_FB8_Msk (0x1U << CAN_F9R2_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F9R2_FB8 CAN_F9R2_FB8_Msk /*!< Filter bit 8 */
+#define CAN_F9R2_FB9_Pos (9U)
+#define CAN_F9R2_FB9_Msk (0x1U << CAN_F9R2_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F9R2_FB9 CAN_F9R2_FB9_Msk /*!< Filter bit 9 */
+#define CAN_F9R2_FB10_Pos (10U)
+#define CAN_F9R2_FB10_Msk (0x1U << CAN_F9R2_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F9R2_FB10 CAN_F9R2_FB10_Msk /*!< Filter bit 10 */
+#define CAN_F9R2_FB11_Pos (11U)
+#define CAN_F9R2_FB11_Msk (0x1U << CAN_F9R2_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F9R2_FB11 CAN_F9R2_FB11_Msk /*!< Filter bit 11 */
+#define CAN_F9R2_FB12_Pos (12U)
+#define CAN_F9R2_FB12_Msk (0x1U << CAN_F9R2_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F9R2_FB12 CAN_F9R2_FB12_Msk /*!< Filter bit 12 */
+#define CAN_F9R2_FB13_Pos (13U)
+#define CAN_F9R2_FB13_Msk (0x1U << CAN_F9R2_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F9R2_FB13 CAN_F9R2_FB13_Msk /*!< Filter bit 13 */
+#define CAN_F9R2_FB14_Pos (14U)
+#define CAN_F9R2_FB14_Msk (0x1U << CAN_F9R2_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F9R2_FB14 CAN_F9R2_FB14_Msk /*!< Filter bit 14 */
+#define CAN_F9R2_FB15_Pos (15U)
+#define CAN_F9R2_FB15_Msk (0x1U << CAN_F9R2_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F9R2_FB15 CAN_F9R2_FB15_Msk /*!< Filter bit 15 */
+#define CAN_F9R2_FB16_Pos (16U)
+#define CAN_F9R2_FB16_Msk (0x1U << CAN_F9R2_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F9R2_FB16 CAN_F9R2_FB16_Msk /*!< Filter bit 16 */
+#define CAN_F9R2_FB17_Pos (17U)
+#define CAN_F9R2_FB17_Msk (0x1U << CAN_F9R2_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F9R2_FB17 CAN_F9R2_FB17_Msk /*!< Filter bit 17 */
+#define CAN_F9R2_FB18_Pos (18U)
+#define CAN_F9R2_FB18_Msk (0x1U << CAN_F9R2_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F9R2_FB18 CAN_F9R2_FB18_Msk /*!< Filter bit 18 */
+#define CAN_F9R2_FB19_Pos (19U)
+#define CAN_F9R2_FB19_Msk (0x1U << CAN_F9R2_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F9R2_FB19 CAN_F9R2_FB19_Msk /*!< Filter bit 19 */
+#define CAN_F9R2_FB20_Pos (20U)
+#define CAN_F9R2_FB20_Msk (0x1U << CAN_F9R2_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F9R2_FB20 CAN_F9R2_FB20_Msk /*!< Filter bit 20 */
+#define CAN_F9R2_FB21_Pos (21U)
+#define CAN_F9R2_FB21_Msk (0x1U << CAN_F9R2_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F9R2_FB21 CAN_F9R2_FB21_Msk /*!< Filter bit 21 */
+#define CAN_F9R2_FB22_Pos (22U)
+#define CAN_F9R2_FB22_Msk (0x1U << CAN_F9R2_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F9R2_FB22 CAN_F9R2_FB22_Msk /*!< Filter bit 22 */
+#define CAN_F9R2_FB23_Pos (23U)
+#define CAN_F9R2_FB23_Msk (0x1U << CAN_F9R2_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F9R2_FB23 CAN_F9R2_FB23_Msk /*!< Filter bit 23 */
+#define CAN_F9R2_FB24_Pos (24U)
+#define CAN_F9R2_FB24_Msk (0x1U << CAN_F9R2_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F9R2_FB24 CAN_F9R2_FB24_Msk /*!< Filter bit 24 */
+#define CAN_F9R2_FB25_Pos (25U)
+#define CAN_F9R2_FB25_Msk (0x1U << CAN_F9R2_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F9R2_FB25 CAN_F9R2_FB25_Msk /*!< Filter bit 25 */
+#define CAN_F9R2_FB26_Pos (26U)
+#define CAN_F9R2_FB26_Msk (0x1U << CAN_F9R2_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F9R2_FB26 CAN_F9R2_FB26_Msk /*!< Filter bit 26 */
+#define CAN_F9R2_FB27_Pos (27U)
+#define CAN_F9R2_FB27_Msk (0x1U << CAN_F9R2_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F9R2_FB27 CAN_F9R2_FB27_Msk /*!< Filter bit 27 */
+#define CAN_F9R2_FB28_Pos (28U)
+#define CAN_F9R2_FB28_Msk (0x1U << CAN_F9R2_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F9R2_FB28 CAN_F9R2_FB28_Msk /*!< Filter bit 28 */
+#define CAN_F9R2_FB29_Pos (29U)
+#define CAN_F9R2_FB29_Msk (0x1U << CAN_F9R2_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F9R2_FB29 CAN_F9R2_FB29_Msk /*!< Filter bit 29 */
+#define CAN_F9R2_FB30_Pos (30U)
+#define CAN_F9R2_FB30_Msk (0x1U << CAN_F9R2_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F9R2_FB30 CAN_F9R2_FB30_Msk /*!< Filter bit 30 */
+#define CAN_F9R2_FB31_Pos (31U)
+#define CAN_F9R2_FB31_Msk (0x1U << CAN_F9R2_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F9R2_FB31 CAN_F9R2_FB31_Msk /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F10R2 register ******************/
+#define CAN_F10R2_FB0_Pos (0U)
+#define CAN_F10R2_FB0_Msk (0x1U << CAN_F10R2_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F10R2_FB0 CAN_F10R2_FB0_Msk /*!< Filter bit 0 */
+#define CAN_F10R2_FB1_Pos (1U)
+#define CAN_F10R2_FB1_Msk (0x1U << CAN_F10R2_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F10R2_FB1 CAN_F10R2_FB1_Msk /*!< Filter bit 1 */
+#define CAN_F10R2_FB2_Pos (2U)
+#define CAN_F10R2_FB2_Msk (0x1U << CAN_F10R2_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F10R2_FB2 CAN_F10R2_FB2_Msk /*!< Filter bit 2 */
+#define CAN_F10R2_FB3_Pos (3U)
+#define CAN_F10R2_FB3_Msk (0x1U << CAN_F10R2_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F10R2_FB3 CAN_F10R2_FB3_Msk /*!< Filter bit 3 */
+#define CAN_F10R2_FB4_Pos (4U)
+#define CAN_F10R2_FB4_Msk (0x1U << CAN_F10R2_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F10R2_FB4 CAN_F10R2_FB4_Msk /*!< Filter bit 4 */
+#define CAN_F10R2_FB5_Pos (5U)
+#define CAN_F10R2_FB5_Msk (0x1U << CAN_F10R2_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F10R2_FB5 CAN_F10R2_FB5_Msk /*!< Filter bit 5 */
+#define CAN_F10R2_FB6_Pos (6U)
+#define CAN_F10R2_FB6_Msk (0x1U << CAN_F10R2_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F10R2_FB6 CAN_F10R2_FB6_Msk /*!< Filter bit 6 */
+#define CAN_F10R2_FB7_Pos (7U)
+#define CAN_F10R2_FB7_Msk (0x1U << CAN_F10R2_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F10R2_FB7 CAN_F10R2_FB7_Msk /*!< Filter bit 7 */
+#define CAN_F10R2_FB8_Pos (8U)
+#define CAN_F10R2_FB8_Msk (0x1U << CAN_F10R2_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F10R2_FB8 CAN_F10R2_FB8_Msk /*!< Filter bit 8 */
+#define CAN_F10R2_FB9_Pos (9U)
+#define CAN_F10R2_FB9_Msk (0x1U << CAN_F10R2_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F10R2_FB9 CAN_F10R2_FB9_Msk /*!< Filter bit 9 */
+#define CAN_F10R2_FB10_Pos (10U)
+#define CAN_F10R2_FB10_Msk (0x1U << CAN_F10R2_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F10R2_FB10 CAN_F10R2_FB10_Msk /*!< Filter bit 10 */
+#define CAN_F10R2_FB11_Pos (11U)
+#define CAN_F10R2_FB11_Msk (0x1U << CAN_F10R2_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F10R2_FB11 CAN_F10R2_FB11_Msk /*!< Filter bit 11 */
+#define CAN_F10R2_FB12_Pos (12U)
+#define CAN_F10R2_FB12_Msk (0x1U << CAN_F10R2_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F10R2_FB12 CAN_F10R2_FB12_Msk /*!< Filter bit 12 */
+#define CAN_F10R2_FB13_Pos (13U)
+#define CAN_F10R2_FB13_Msk (0x1U << CAN_F10R2_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F10R2_FB13 CAN_F10R2_FB13_Msk /*!< Filter bit 13 */
+#define CAN_F10R2_FB14_Pos (14U)
+#define CAN_F10R2_FB14_Msk (0x1U << CAN_F10R2_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F10R2_FB14 CAN_F10R2_FB14_Msk /*!< Filter bit 14 */
+#define CAN_F10R2_FB15_Pos (15U)
+#define CAN_F10R2_FB15_Msk (0x1U << CAN_F10R2_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F10R2_FB15 CAN_F10R2_FB15_Msk /*!< Filter bit 15 */
+#define CAN_F10R2_FB16_Pos (16U)
+#define CAN_F10R2_FB16_Msk (0x1U << CAN_F10R2_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F10R2_FB16 CAN_F10R2_FB16_Msk /*!< Filter bit 16 */
+#define CAN_F10R2_FB17_Pos (17U)
+#define CAN_F10R2_FB17_Msk (0x1U << CAN_F10R2_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F10R2_FB17 CAN_F10R2_FB17_Msk /*!< Filter bit 17 */
+#define CAN_F10R2_FB18_Pos (18U)
+#define CAN_F10R2_FB18_Msk (0x1U << CAN_F10R2_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F10R2_FB18 CAN_F10R2_FB18_Msk /*!< Filter bit 18 */
+#define CAN_F10R2_FB19_Pos (19U)
+#define CAN_F10R2_FB19_Msk (0x1U << CAN_F10R2_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F10R2_FB19 CAN_F10R2_FB19_Msk /*!< Filter bit 19 */
+#define CAN_F10R2_FB20_Pos (20U)
+#define CAN_F10R2_FB20_Msk (0x1U << CAN_F10R2_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F10R2_FB20 CAN_F10R2_FB20_Msk /*!< Filter bit 20 */
+#define CAN_F10R2_FB21_Pos (21U)
+#define CAN_F10R2_FB21_Msk (0x1U << CAN_F10R2_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F10R2_FB21 CAN_F10R2_FB21_Msk /*!< Filter bit 21 */
+#define CAN_F10R2_FB22_Pos (22U)
+#define CAN_F10R2_FB22_Msk (0x1U << CAN_F10R2_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F10R2_FB22 CAN_F10R2_FB22_Msk /*!< Filter bit 22 */
+#define CAN_F10R2_FB23_Pos (23U)
+#define CAN_F10R2_FB23_Msk (0x1U << CAN_F10R2_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F10R2_FB23 CAN_F10R2_FB23_Msk /*!< Filter bit 23 */
+#define CAN_F10R2_FB24_Pos (24U)
+#define CAN_F10R2_FB24_Msk (0x1U << CAN_F10R2_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F10R2_FB24 CAN_F10R2_FB24_Msk /*!< Filter bit 24 */
+#define CAN_F10R2_FB25_Pos (25U)
+#define CAN_F10R2_FB25_Msk (0x1U << CAN_F10R2_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F10R2_FB25 CAN_F10R2_FB25_Msk /*!< Filter bit 25 */
+#define CAN_F10R2_FB26_Pos (26U)
+#define CAN_F10R2_FB26_Msk (0x1U << CAN_F10R2_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F10R2_FB26 CAN_F10R2_FB26_Msk /*!< Filter bit 26 */
+#define CAN_F10R2_FB27_Pos (27U)
+#define CAN_F10R2_FB27_Msk (0x1U << CAN_F10R2_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F10R2_FB27 CAN_F10R2_FB27_Msk /*!< Filter bit 27 */
+#define CAN_F10R2_FB28_Pos (28U)
+#define CAN_F10R2_FB28_Msk (0x1U << CAN_F10R2_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F10R2_FB28 CAN_F10R2_FB28_Msk /*!< Filter bit 28 */
+#define CAN_F10R2_FB29_Pos (29U)
+#define CAN_F10R2_FB29_Msk (0x1U << CAN_F10R2_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F10R2_FB29 CAN_F10R2_FB29_Msk /*!< Filter bit 29 */
+#define CAN_F10R2_FB30_Pos (30U)
+#define CAN_F10R2_FB30_Msk (0x1U << CAN_F10R2_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F10R2_FB30 CAN_F10R2_FB30_Msk /*!< Filter bit 30 */
+#define CAN_F10R2_FB31_Pos (31U)
+#define CAN_F10R2_FB31_Msk (0x1U << CAN_F10R2_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F10R2_FB31 CAN_F10R2_FB31_Msk /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F11R2 register ******************/
+#define CAN_F11R2_FB0_Pos (0U)
+#define CAN_F11R2_FB0_Msk (0x1U << CAN_F11R2_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F11R2_FB0 CAN_F11R2_FB0_Msk /*!< Filter bit 0 */
+#define CAN_F11R2_FB1_Pos (1U)
+#define CAN_F11R2_FB1_Msk (0x1U << CAN_F11R2_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F11R2_FB1 CAN_F11R2_FB1_Msk /*!< Filter bit 1 */
+#define CAN_F11R2_FB2_Pos (2U)
+#define CAN_F11R2_FB2_Msk (0x1U << CAN_F11R2_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F11R2_FB2 CAN_F11R2_FB2_Msk /*!< Filter bit 2 */
+#define CAN_F11R2_FB3_Pos (3U)
+#define CAN_F11R2_FB3_Msk (0x1U << CAN_F11R2_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F11R2_FB3 CAN_F11R2_FB3_Msk /*!< Filter bit 3 */
+#define CAN_F11R2_FB4_Pos (4U)
+#define CAN_F11R2_FB4_Msk (0x1U << CAN_F11R2_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F11R2_FB4 CAN_F11R2_FB4_Msk /*!< Filter bit 4 */
+#define CAN_F11R2_FB5_Pos (5U)
+#define CAN_F11R2_FB5_Msk (0x1U << CAN_F11R2_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F11R2_FB5 CAN_F11R2_FB5_Msk /*!< Filter bit 5 */
+#define CAN_F11R2_FB6_Pos (6U)
+#define CAN_F11R2_FB6_Msk (0x1U << CAN_F11R2_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F11R2_FB6 CAN_F11R2_FB6_Msk /*!< Filter bit 6 */
+#define CAN_F11R2_FB7_Pos (7U)
+#define CAN_F11R2_FB7_Msk (0x1U << CAN_F11R2_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F11R2_FB7 CAN_F11R2_FB7_Msk /*!< Filter bit 7 */
+#define CAN_F11R2_FB8_Pos (8U)
+#define CAN_F11R2_FB8_Msk (0x1U << CAN_F11R2_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F11R2_FB8 CAN_F11R2_FB8_Msk /*!< Filter bit 8 */
+#define CAN_F11R2_FB9_Pos (9U)
+#define CAN_F11R2_FB9_Msk (0x1U << CAN_F11R2_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F11R2_FB9 CAN_F11R2_FB9_Msk /*!< Filter bit 9 */
+#define CAN_F11R2_FB10_Pos (10U)
+#define CAN_F11R2_FB10_Msk (0x1U << CAN_F11R2_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F11R2_FB10 CAN_F11R2_FB10_Msk /*!< Filter bit 10 */
+#define CAN_F11R2_FB11_Pos (11U)
+#define CAN_F11R2_FB11_Msk (0x1U << CAN_F11R2_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F11R2_FB11 CAN_F11R2_FB11_Msk /*!< Filter bit 11 */
+#define CAN_F11R2_FB12_Pos (12U)
+#define CAN_F11R2_FB12_Msk (0x1U << CAN_F11R2_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F11R2_FB12 CAN_F11R2_FB12_Msk /*!< Filter bit 12 */
+#define CAN_F11R2_FB13_Pos (13U)
+#define CAN_F11R2_FB13_Msk (0x1U << CAN_F11R2_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F11R2_FB13 CAN_F11R2_FB13_Msk /*!< Filter bit 13 */
+#define CAN_F11R2_FB14_Pos (14U)
+#define CAN_F11R2_FB14_Msk (0x1U << CAN_F11R2_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F11R2_FB14 CAN_F11R2_FB14_Msk /*!< Filter bit 14 */
+#define CAN_F11R2_FB15_Pos (15U)
+#define CAN_F11R2_FB15_Msk (0x1U << CAN_F11R2_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F11R2_FB15 CAN_F11R2_FB15_Msk /*!< Filter bit 15 */
+#define CAN_F11R2_FB16_Pos (16U)
+#define CAN_F11R2_FB16_Msk (0x1U << CAN_F11R2_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F11R2_FB16 CAN_F11R2_FB16_Msk /*!< Filter bit 16 */
+#define CAN_F11R2_FB17_Pos (17U)
+#define CAN_F11R2_FB17_Msk (0x1U << CAN_F11R2_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F11R2_FB17 CAN_F11R2_FB17_Msk /*!< Filter bit 17 */
+#define CAN_F11R2_FB18_Pos (18U)
+#define CAN_F11R2_FB18_Msk (0x1U << CAN_F11R2_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F11R2_FB18 CAN_F11R2_FB18_Msk /*!< Filter bit 18 */
+#define CAN_F11R2_FB19_Pos (19U)
+#define CAN_F11R2_FB19_Msk (0x1U << CAN_F11R2_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F11R2_FB19 CAN_F11R2_FB19_Msk /*!< Filter bit 19 */
+#define CAN_F11R2_FB20_Pos (20U)
+#define CAN_F11R2_FB20_Msk (0x1U << CAN_F11R2_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F11R2_FB20 CAN_F11R2_FB20_Msk /*!< Filter bit 20 */
+#define CAN_F11R2_FB21_Pos (21U)
+#define CAN_F11R2_FB21_Msk (0x1U << CAN_F11R2_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F11R2_FB21 CAN_F11R2_FB21_Msk /*!< Filter bit 21 */
+#define CAN_F11R2_FB22_Pos (22U)
+#define CAN_F11R2_FB22_Msk (0x1U << CAN_F11R2_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F11R2_FB22 CAN_F11R2_FB22_Msk /*!< Filter bit 22 */
+#define CAN_F11R2_FB23_Pos (23U)
+#define CAN_F11R2_FB23_Msk (0x1U << CAN_F11R2_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F11R2_FB23 CAN_F11R2_FB23_Msk /*!< Filter bit 23 */
+#define CAN_F11R2_FB24_Pos (24U)
+#define CAN_F11R2_FB24_Msk (0x1U << CAN_F11R2_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F11R2_FB24 CAN_F11R2_FB24_Msk /*!< Filter bit 24 */
+#define CAN_F11R2_FB25_Pos (25U)
+#define CAN_F11R2_FB25_Msk (0x1U << CAN_F11R2_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F11R2_FB25 CAN_F11R2_FB25_Msk /*!< Filter bit 25 */
+#define CAN_F11R2_FB26_Pos (26U)
+#define CAN_F11R2_FB26_Msk (0x1U << CAN_F11R2_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F11R2_FB26 CAN_F11R2_FB26_Msk /*!< Filter bit 26 */
+#define CAN_F11R2_FB27_Pos (27U)
+#define CAN_F11R2_FB27_Msk (0x1U << CAN_F11R2_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F11R2_FB27 CAN_F11R2_FB27_Msk /*!< Filter bit 27 */
+#define CAN_F11R2_FB28_Pos (28U)
+#define CAN_F11R2_FB28_Msk (0x1U << CAN_F11R2_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F11R2_FB28 CAN_F11R2_FB28_Msk /*!< Filter bit 28 */
+#define CAN_F11R2_FB29_Pos (29U)
+#define CAN_F11R2_FB29_Msk (0x1U << CAN_F11R2_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F11R2_FB29 CAN_F11R2_FB29_Msk /*!< Filter bit 29 */
+#define CAN_F11R2_FB30_Pos (30U)
+#define CAN_F11R2_FB30_Msk (0x1U << CAN_F11R2_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F11R2_FB30 CAN_F11R2_FB30_Msk /*!< Filter bit 30 */
+#define CAN_F11R2_FB31_Pos (31U)
+#define CAN_F11R2_FB31_Msk (0x1U << CAN_F11R2_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F11R2_FB31 CAN_F11R2_FB31_Msk /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F12R2 register ******************/
+#define CAN_F12R2_FB0_Pos (0U)
+#define CAN_F12R2_FB0_Msk (0x1U << CAN_F12R2_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F12R2_FB0 CAN_F12R2_FB0_Msk /*!< Filter bit 0 */
+#define CAN_F12R2_FB1_Pos (1U)
+#define CAN_F12R2_FB1_Msk (0x1U << CAN_F12R2_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F12R2_FB1 CAN_F12R2_FB1_Msk /*!< Filter bit 1 */
+#define CAN_F12R2_FB2_Pos (2U)
+#define CAN_F12R2_FB2_Msk (0x1U << CAN_F12R2_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F12R2_FB2 CAN_F12R2_FB2_Msk /*!< Filter bit 2 */
+#define CAN_F12R2_FB3_Pos (3U)
+#define CAN_F12R2_FB3_Msk (0x1U << CAN_F12R2_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F12R2_FB3 CAN_F12R2_FB3_Msk /*!< Filter bit 3 */
+#define CAN_F12R2_FB4_Pos (4U)
+#define CAN_F12R2_FB4_Msk (0x1U << CAN_F12R2_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F12R2_FB4 CAN_F12R2_FB4_Msk /*!< Filter bit 4 */
+#define CAN_F12R2_FB5_Pos (5U)
+#define CAN_F12R2_FB5_Msk (0x1U << CAN_F12R2_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F12R2_FB5 CAN_F12R2_FB5_Msk /*!< Filter bit 5 */
+#define CAN_F12R2_FB6_Pos (6U)
+#define CAN_F12R2_FB6_Msk (0x1U << CAN_F12R2_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F12R2_FB6 CAN_F12R2_FB6_Msk /*!< Filter bit 6 */
+#define CAN_F12R2_FB7_Pos (7U)
+#define CAN_F12R2_FB7_Msk (0x1U << CAN_F12R2_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F12R2_FB7 CAN_F12R2_FB7_Msk /*!< Filter bit 7 */
+#define CAN_F12R2_FB8_Pos (8U)
+#define CAN_F12R2_FB8_Msk (0x1U << CAN_F12R2_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F12R2_FB8 CAN_F12R2_FB8_Msk /*!< Filter bit 8 */
+#define CAN_F12R2_FB9_Pos (9U)
+#define CAN_F12R2_FB9_Msk (0x1U << CAN_F12R2_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F12R2_FB9 CAN_F12R2_FB9_Msk /*!< Filter bit 9 */
+#define CAN_F12R2_FB10_Pos (10U)
+#define CAN_F12R2_FB10_Msk (0x1U << CAN_F12R2_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F12R2_FB10 CAN_F12R2_FB10_Msk /*!< Filter bit 10 */
+#define CAN_F12R2_FB11_Pos (11U)
+#define CAN_F12R2_FB11_Msk (0x1U << CAN_F12R2_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F12R2_FB11 CAN_F12R2_FB11_Msk /*!< Filter bit 11 */
+#define CAN_F12R2_FB12_Pos (12U)
+#define CAN_F12R2_FB12_Msk (0x1U << CAN_F12R2_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F12R2_FB12 CAN_F12R2_FB12_Msk /*!< Filter bit 12 */
+#define CAN_F12R2_FB13_Pos (13U)
+#define CAN_F12R2_FB13_Msk (0x1U << CAN_F12R2_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F12R2_FB13 CAN_F12R2_FB13_Msk /*!< Filter bit 13 */
+#define CAN_F12R2_FB14_Pos (14U)
+#define CAN_F12R2_FB14_Msk (0x1U << CAN_F12R2_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F12R2_FB14 CAN_F12R2_FB14_Msk /*!< Filter bit 14 */
+#define CAN_F12R2_FB15_Pos (15U)
+#define CAN_F12R2_FB15_Msk (0x1U << CAN_F12R2_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F12R2_FB15 CAN_F12R2_FB15_Msk /*!< Filter bit 15 */
+#define CAN_F12R2_FB16_Pos (16U)
+#define CAN_F12R2_FB16_Msk (0x1U << CAN_F12R2_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F12R2_FB16 CAN_F12R2_FB16_Msk /*!< Filter bit 16 */
+#define CAN_F12R2_FB17_Pos (17U)
+#define CAN_F12R2_FB17_Msk (0x1U << CAN_F12R2_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F12R2_FB17 CAN_F12R2_FB17_Msk /*!< Filter bit 17 */
+#define CAN_F12R2_FB18_Pos (18U)
+#define CAN_F12R2_FB18_Msk (0x1U << CAN_F12R2_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F12R2_FB18 CAN_F12R2_FB18_Msk /*!< Filter bit 18 */
+#define CAN_F12R2_FB19_Pos (19U)
+#define CAN_F12R2_FB19_Msk (0x1U << CAN_F12R2_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F12R2_FB19 CAN_F12R2_FB19_Msk /*!< Filter bit 19 */
+#define CAN_F12R2_FB20_Pos (20U)
+#define CAN_F12R2_FB20_Msk (0x1U << CAN_F12R2_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F12R2_FB20 CAN_F12R2_FB20_Msk /*!< Filter bit 20 */
+#define CAN_F12R2_FB21_Pos (21U)
+#define CAN_F12R2_FB21_Msk (0x1U << CAN_F12R2_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F12R2_FB21 CAN_F12R2_FB21_Msk /*!< Filter bit 21 */
+#define CAN_F12R2_FB22_Pos (22U)
+#define CAN_F12R2_FB22_Msk (0x1U << CAN_F12R2_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F12R2_FB22 CAN_F12R2_FB22_Msk /*!< Filter bit 22 */
+#define CAN_F12R2_FB23_Pos (23U)
+#define CAN_F12R2_FB23_Msk (0x1U << CAN_F12R2_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F12R2_FB23 CAN_F12R2_FB23_Msk /*!< Filter bit 23 */
+#define CAN_F12R2_FB24_Pos (24U)
+#define CAN_F12R2_FB24_Msk (0x1U << CAN_F12R2_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F12R2_FB24 CAN_F12R2_FB24_Msk /*!< Filter bit 24 */
+#define CAN_F12R2_FB25_Pos (25U)
+#define CAN_F12R2_FB25_Msk (0x1U << CAN_F12R2_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F12R2_FB25 CAN_F12R2_FB25_Msk /*!< Filter bit 25 */
+#define CAN_F12R2_FB26_Pos (26U)
+#define CAN_F12R2_FB26_Msk (0x1U << CAN_F12R2_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F12R2_FB26 CAN_F12R2_FB26_Msk /*!< Filter bit 26 */
+#define CAN_F12R2_FB27_Pos (27U)
+#define CAN_F12R2_FB27_Msk (0x1U << CAN_F12R2_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F12R2_FB27 CAN_F12R2_FB27_Msk /*!< Filter bit 27 */
+#define CAN_F12R2_FB28_Pos (28U)
+#define CAN_F12R2_FB28_Msk (0x1U << CAN_F12R2_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F12R2_FB28 CAN_F12R2_FB28_Msk /*!< Filter bit 28 */
+#define CAN_F12R2_FB29_Pos (29U)
+#define CAN_F12R2_FB29_Msk (0x1U << CAN_F12R2_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F12R2_FB29 CAN_F12R2_FB29_Msk /*!< Filter bit 29 */
+#define CAN_F12R2_FB30_Pos (30U)
+#define CAN_F12R2_FB30_Msk (0x1U << CAN_F12R2_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F12R2_FB30 CAN_F12R2_FB30_Msk /*!< Filter bit 30 */
+#define CAN_F12R2_FB31_Pos (31U)
+#define CAN_F12R2_FB31_Msk (0x1U << CAN_F12R2_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F12R2_FB31 CAN_F12R2_FB31_Msk /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F13R2 register ******************/
+#define CAN_F13R2_FB0_Pos (0U)
+#define CAN_F13R2_FB0_Msk (0x1U << CAN_F13R2_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F13R2_FB0 CAN_F13R2_FB0_Msk /*!< Filter bit 0 */
+#define CAN_F13R2_FB1_Pos (1U)
+#define CAN_F13R2_FB1_Msk (0x1U << CAN_F13R2_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F13R2_FB1 CAN_F13R2_FB1_Msk /*!< Filter bit 1 */
+#define CAN_F13R2_FB2_Pos (2U)
+#define CAN_F13R2_FB2_Msk (0x1U << CAN_F13R2_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F13R2_FB2 CAN_F13R2_FB2_Msk /*!< Filter bit 2 */
+#define CAN_F13R2_FB3_Pos (3U)
+#define CAN_F13R2_FB3_Msk (0x1U << CAN_F13R2_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F13R2_FB3 CAN_F13R2_FB3_Msk /*!< Filter bit 3 */
+#define CAN_F13R2_FB4_Pos (4U)
+#define CAN_F13R2_FB4_Msk (0x1U << CAN_F13R2_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F13R2_FB4 CAN_F13R2_FB4_Msk /*!< Filter bit 4 */
+#define CAN_F13R2_FB5_Pos (5U)
+#define CAN_F13R2_FB5_Msk (0x1U << CAN_F13R2_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F13R2_FB5 CAN_F13R2_FB5_Msk /*!< Filter bit 5 */
+#define CAN_F13R2_FB6_Pos (6U)
+#define CAN_F13R2_FB6_Msk (0x1U << CAN_F13R2_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F13R2_FB6 CAN_F13R2_FB6_Msk /*!< Filter bit 6 */
+#define CAN_F13R2_FB7_Pos (7U)
+#define CAN_F13R2_FB7_Msk (0x1U << CAN_F13R2_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F13R2_FB7 CAN_F13R2_FB7_Msk /*!< Filter bit 7 */
+#define CAN_F13R2_FB8_Pos (8U)
+#define CAN_F13R2_FB8_Msk (0x1U << CAN_F13R2_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F13R2_FB8 CAN_F13R2_FB8_Msk /*!< Filter bit 8 */
+#define CAN_F13R2_FB9_Pos (9U)
+#define CAN_F13R2_FB9_Msk (0x1U << CAN_F13R2_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F13R2_FB9 CAN_F13R2_FB9_Msk /*!< Filter bit 9 */
+#define CAN_F13R2_FB10_Pos (10U)
+#define CAN_F13R2_FB10_Msk (0x1U << CAN_F13R2_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F13R2_FB10 CAN_F13R2_FB10_Msk /*!< Filter bit 10 */
+#define CAN_F13R2_FB11_Pos (11U)
+#define CAN_F13R2_FB11_Msk (0x1U << CAN_F13R2_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F13R2_FB11 CAN_F13R2_FB11_Msk /*!< Filter bit 11 */
+#define CAN_F13R2_FB12_Pos (12U)
+#define CAN_F13R2_FB12_Msk (0x1U << CAN_F13R2_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F13R2_FB12 CAN_F13R2_FB12_Msk /*!< Filter bit 12 */
+#define CAN_F13R2_FB13_Pos (13U)
+#define CAN_F13R2_FB13_Msk (0x1U << CAN_F13R2_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F13R2_FB13 CAN_F13R2_FB13_Msk /*!< Filter bit 13 */
+#define CAN_F13R2_FB14_Pos (14U)
+#define CAN_F13R2_FB14_Msk (0x1U << CAN_F13R2_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F13R2_FB14 CAN_F13R2_FB14_Msk /*!< Filter bit 14 */
+#define CAN_F13R2_FB15_Pos (15U)
+#define CAN_F13R2_FB15_Msk (0x1U << CAN_F13R2_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F13R2_FB15 CAN_F13R2_FB15_Msk /*!< Filter bit 15 */
+#define CAN_F13R2_FB16_Pos (16U)
+#define CAN_F13R2_FB16_Msk (0x1U << CAN_F13R2_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F13R2_FB16 CAN_F13R2_FB16_Msk /*!< Filter bit 16 */
+#define CAN_F13R2_FB17_Pos (17U)
+#define CAN_F13R2_FB17_Msk (0x1U << CAN_F13R2_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F13R2_FB17 CAN_F13R2_FB17_Msk /*!< Filter bit 17 */
+#define CAN_F13R2_FB18_Pos (18U)
+#define CAN_F13R2_FB18_Msk (0x1U << CAN_F13R2_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F13R2_FB18 CAN_F13R2_FB18_Msk /*!< Filter bit 18 */
+#define CAN_F13R2_FB19_Pos (19U)
+#define CAN_F13R2_FB19_Msk (0x1U << CAN_F13R2_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F13R2_FB19 CAN_F13R2_FB19_Msk /*!< Filter bit 19 */
+#define CAN_F13R2_FB20_Pos (20U)
+#define CAN_F13R2_FB20_Msk (0x1U << CAN_F13R2_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F13R2_FB20 CAN_F13R2_FB20_Msk /*!< Filter bit 20 */
+#define CAN_F13R2_FB21_Pos (21U)
+#define CAN_F13R2_FB21_Msk (0x1U << CAN_F13R2_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F13R2_FB21 CAN_F13R2_FB21_Msk /*!< Filter bit 21 */
+#define CAN_F13R2_FB22_Pos (22U)
+#define CAN_F13R2_FB22_Msk (0x1U << CAN_F13R2_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F13R2_FB22 CAN_F13R2_FB22_Msk /*!< Filter bit 22 */
+#define CAN_F13R2_FB23_Pos (23U)
+#define CAN_F13R2_FB23_Msk (0x1U << CAN_F13R2_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F13R2_FB23 CAN_F13R2_FB23_Msk /*!< Filter bit 23 */
+#define CAN_F13R2_FB24_Pos (24U)
+#define CAN_F13R2_FB24_Msk (0x1U << CAN_F13R2_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F13R2_FB24 CAN_F13R2_FB24_Msk /*!< Filter bit 24 */
+#define CAN_F13R2_FB25_Pos (25U)
+#define CAN_F13R2_FB25_Msk (0x1U << CAN_F13R2_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F13R2_FB25 CAN_F13R2_FB25_Msk /*!< Filter bit 25 */
+#define CAN_F13R2_FB26_Pos (26U)
+#define CAN_F13R2_FB26_Msk (0x1U << CAN_F13R2_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F13R2_FB26 CAN_F13R2_FB26_Msk /*!< Filter bit 26 */
+#define CAN_F13R2_FB27_Pos (27U)
+#define CAN_F13R2_FB27_Msk (0x1U << CAN_F13R2_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F13R2_FB27 CAN_F13R2_FB27_Msk /*!< Filter bit 27 */
+#define CAN_F13R2_FB28_Pos (28U)
+#define CAN_F13R2_FB28_Msk (0x1U << CAN_F13R2_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F13R2_FB28 CAN_F13R2_FB28_Msk /*!< Filter bit 28 */
+#define CAN_F13R2_FB29_Pos (29U)
+#define CAN_F13R2_FB29_Msk (0x1U << CAN_F13R2_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F13R2_FB29 CAN_F13R2_FB29_Msk /*!< Filter bit 29 */
+#define CAN_F13R2_FB30_Pos (30U)
+#define CAN_F13R2_FB30_Msk (0x1U << CAN_F13R2_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F13R2_FB30 CAN_F13R2_FB30_Msk /*!< Filter bit 30 */
+#define CAN_F13R2_FB31_Pos (31U)
+#define CAN_F13R2_FB31_Msk (0x1U << CAN_F13R2_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F13R2_FB31 CAN_F13R2_FB31_Msk /*!< Filter bit 31 */
+
+/******************************************************************************/
+/* */
+/* Serial Peripheral Interface */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for SPI_CR1 register ********************/
+#define SPI_CR1_CPHA_Pos (0U)
+#define SPI_CR1_CPHA_Msk (0x1U << SPI_CR1_CPHA_Pos) /*!< 0x00000001 */
+#define SPI_CR1_CPHA SPI_CR1_CPHA_Msk /*!< Clock Phase */
+#define SPI_CR1_CPOL_Pos (1U)
+#define SPI_CR1_CPOL_Msk (0x1U << SPI_CR1_CPOL_Pos) /*!< 0x00000002 */
+#define SPI_CR1_CPOL SPI_CR1_CPOL_Msk /*!< Clock Polarity */
+#define SPI_CR1_MSTR_Pos (2U)
+#define SPI_CR1_MSTR_Msk (0x1U << SPI_CR1_MSTR_Pos) /*!< 0x00000004 */
+#define SPI_CR1_MSTR SPI_CR1_MSTR_Msk /*!< Master Selection */
+
+#define SPI_CR1_BR_Pos (3U)
+#define SPI_CR1_BR_Msk (0x7U << SPI_CR1_BR_Pos) /*!< 0x00000038 */
+#define SPI_CR1_BR SPI_CR1_BR_Msk /*!< BR[2:0] bits (Baud Rate Control) */
+#define SPI_CR1_BR_0 (0x1U << SPI_CR1_BR_Pos) /*!< 0x00000008 */
+#define SPI_CR1_BR_1 (0x2U << SPI_CR1_BR_Pos) /*!< 0x00000010 */
+#define SPI_CR1_BR_2 (0x4U << SPI_CR1_BR_Pos) /*!< 0x00000020 */
+
+#define SPI_CR1_SPE_Pos (6U)
+#define SPI_CR1_SPE_Msk (0x1U << SPI_CR1_SPE_Pos) /*!< 0x00000040 */
+#define SPI_CR1_SPE SPI_CR1_SPE_Msk /*!< SPI Enable */
+#define SPI_CR1_LSBFIRST_Pos (7U)
+#define SPI_CR1_LSBFIRST_Msk (0x1U << SPI_CR1_LSBFIRST_Pos) /*!< 0x00000080 */
+#define SPI_CR1_LSBFIRST SPI_CR1_LSBFIRST_Msk /*!< Frame Format */
+#define SPI_CR1_SSI_Pos (8U)
+#define SPI_CR1_SSI_Msk (0x1U << SPI_CR1_SSI_Pos) /*!< 0x00000100 */
+#define SPI_CR1_SSI SPI_CR1_SSI_Msk /*!< Internal slave select */
+#define SPI_CR1_SSM_Pos (9U)
+#define SPI_CR1_SSM_Msk (0x1U << SPI_CR1_SSM_Pos) /*!< 0x00000200 */
+#define SPI_CR1_SSM SPI_CR1_SSM_Msk /*!< Software slave management */
+#define SPI_CR1_RXONLY_Pos (10U)
+#define SPI_CR1_RXONLY_Msk (0x1U << SPI_CR1_RXONLY_Pos) /*!< 0x00000400 */
+#define SPI_CR1_RXONLY SPI_CR1_RXONLY_Msk /*!< Receive only */
+#define SPI_CR1_DFF_Pos (11U)
+#define SPI_CR1_DFF_Msk (0x1U << SPI_CR1_DFF_Pos) /*!< 0x00000800 */
+#define SPI_CR1_DFF SPI_CR1_DFF_Msk /*!< Data Frame Format */
+#define SPI_CR1_CRCNEXT_Pos (12U)
+#define SPI_CR1_CRCNEXT_Msk (0x1U << SPI_CR1_CRCNEXT_Pos) /*!< 0x00001000 */
+#define SPI_CR1_CRCNEXT SPI_CR1_CRCNEXT_Msk /*!< Transmit CRC next */
+#define SPI_CR1_CRCEN_Pos (13U)
+#define SPI_CR1_CRCEN_Msk (0x1U << SPI_CR1_CRCEN_Pos) /*!< 0x00002000 */
+#define SPI_CR1_CRCEN SPI_CR1_CRCEN_Msk /*!< Hardware CRC calculation enable */
+#define SPI_CR1_BIDIOE_Pos (14U)
+#define SPI_CR1_BIDIOE_Msk (0x1U << SPI_CR1_BIDIOE_Pos) /*!< 0x00004000 */
+#define SPI_CR1_BIDIOE SPI_CR1_BIDIOE_Msk /*!< Output enable in bidirectional mode */
+#define SPI_CR1_BIDIMODE_Pos (15U)
+#define SPI_CR1_BIDIMODE_Msk (0x1U << SPI_CR1_BIDIMODE_Pos) /*!< 0x00008000 */
+#define SPI_CR1_BIDIMODE SPI_CR1_BIDIMODE_Msk /*!< Bidirectional data mode enable */
+
+/******************* Bit definition for SPI_CR2 register ********************/
+#define SPI_CR2_RXDMAEN_Pos (0U)
+#define SPI_CR2_RXDMAEN_Msk (0x1U << SPI_CR2_RXDMAEN_Pos) /*!< 0x00000001 */
+#define SPI_CR2_RXDMAEN SPI_CR2_RXDMAEN_Msk /*!< Rx Buffer DMA Enable */
+#define SPI_CR2_TXDMAEN_Pos (1U)
+#define SPI_CR2_TXDMAEN_Msk (0x1U << SPI_CR2_TXDMAEN_Pos) /*!< 0x00000002 */
+#define SPI_CR2_TXDMAEN SPI_CR2_TXDMAEN_Msk /*!< Tx Buffer DMA Enable */
+#define SPI_CR2_SSOE_Pos (2U)
+#define SPI_CR2_SSOE_Msk (0x1U << SPI_CR2_SSOE_Pos) /*!< 0x00000004 */
+#define SPI_CR2_SSOE SPI_CR2_SSOE_Msk /*!< SS Output Enable */
+#define SPI_CR2_ERRIE_Pos (5U)
+#define SPI_CR2_ERRIE_Msk (0x1U << SPI_CR2_ERRIE_Pos) /*!< 0x00000020 */
+#define SPI_CR2_ERRIE SPI_CR2_ERRIE_Msk /*!< Error Interrupt Enable */
+#define SPI_CR2_RXNEIE_Pos (6U)
+#define SPI_CR2_RXNEIE_Msk (0x1U << SPI_CR2_RXNEIE_Pos) /*!< 0x00000040 */
+#define SPI_CR2_RXNEIE SPI_CR2_RXNEIE_Msk /*!< RX buffer Not Empty Interrupt Enable */
+#define SPI_CR2_TXEIE_Pos (7U)
+#define SPI_CR2_TXEIE_Msk (0x1U << SPI_CR2_TXEIE_Pos) /*!< 0x00000080 */
+#define SPI_CR2_TXEIE SPI_CR2_TXEIE_Msk /*!< Tx buffer Empty Interrupt Enable */
+
+/******************** Bit definition for SPI_SR register ********************/
+#define SPI_SR_RXNE_Pos (0U)
+#define SPI_SR_RXNE_Msk (0x1U << SPI_SR_RXNE_Pos) /*!< 0x00000001 */
+#define SPI_SR_RXNE SPI_SR_RXNE_Msk /*!< Receive buffer Not Empty */
+#define SPI_SR_TXE_Pos (1U)
+#define SPI_SR_TXE_Msk (0x1U << SPI_SR_TXE_Pos) /*!< 0x00000002 */
+#define SPI_SR_TXE SPI_SR_TXE_Msk /*!< Transmit buffer Empty */
+#define SPI_SR_CHSIDE_Pos (2U)
+#define SPI_SR_CHSIDE_Msk (0x1U << SPI_SR_CHSIDE_Pos) /*!< 0x00000004 */
+#define SPI_SR_CHSIDE SPI_SR_CHSIDE_Msk /*!< Channel side */
+#define SPI_SR_UDR_Pos (3U)
+#define SPI_SR_UDR_Msk (0x1U << SPI_SR_UDR_Pos) /*!< 0x00000008 */
+#define SPI_SR_UDR SPI_SR_UDR_Msk /*!< Underrun flag */
+#define SPI_SR_CRCERR_Pos (4U)
+#define SPI_SR_CRCERR_Msk (0x1U << SPI_SR_CRCERR_Pos) /*!< 0x00000010 */
+#define SPI_SR_CRCERR SPI_SR_CRCERR_Msk /*!< CRC Error flag */
+#define SPI_SR_MODF_Pos (5U)
+#define SPI_SR_MODF_Msk (0x1U << SPI_SR_MODF_Pos) /*!< 0x00000020 */
+#define SPI_SR_MODF SPI_SR_MODF_Msk /*!< Mode fault */
+#define SPI_SR_OVR_Pos (6U)
+#define SPI_SR_OVR_Msk (0x1U << SPI_SR_OVR_Pos) /*!< 0x00000040 */
+#define SPI_SR_OVR SPI_SR_OVR_Msk /*!< Overrun flag */
+#define SPI_SR_BSY_Pos (7U)
+#define SPI_SR_BSY_Msk (0x1U << SPI_SR_BSY_Pos) /*!< 0x00000080 */
+#define SPI_SR_BSY SPI_SR_BSY_Msk /*!< Busy flag */
+
+/******************** Bit definition for SPI_DR register ********************/
+#define SPI_DR_DR_Pos (0U)
+#define SPI_DR_DR_Msk (0xFFFFU << SPI_DR_DR_Pos) /*!< 0x0000FFFF */
+#define SPI_DR_DR SPI_DR_DR_Msk /*!< Data Register */
+
+/******************* Bit definition for SPI_CRCPR register ******************/
+#define SPI_CRCPR_CRCPOLY_Pos (0U)
+#define SPI_CRCPR_CRCPOLY_Msk (0xFFFFU << SPI_CRCPR_CRCPOLY_Pos) /*!< 0x0000FFFF */
+#define SPI_CRCPR_CRCPOLY SPI_CRCPR_CRCPOLY_Msk /*!< CRC polynomial register */
+
+/****************** Bit definition for SPI_RXCRCR register ******************/
+#define SPI_RXCRCR_RXCRC_Pos (0U)
+#define SPI_RXCRCR_RXCRC_Msk (0xFFFFU << SPI_RXCRCR_RXCRC_Pos) /*!< 0x0000FFFF */
+#define SPI_RXCRCR_RXCRC SPI_RXCRCR_RXCRC_Msk /*!< Rx CRC Register */
+
+/****************** Bit definition for SPI_TXCRCR register ******************/
+#define SPI_TXCRCR_TXCRC_Pos (0U)
+#define SPI_TXCRCR_TXCRC_Msk (0xFFFFU << SPI_TXCRCR_TXCRC_Pos) /*!< 0x0000FFFF */
+#define SPI_TXCRCR_TXCRC SPI_TXCRCR_TXCRC_Msk /*!< Tx CRC Register */
+
+/****************** Bit definition for SPI_I2SCFGR register *****************/
+#define SPI_I2SCFGR_I2SMOD_Pos (11U)
+#define SPI_I2SCFGR_I2SMOD_Msk (0x1U << SPI_I2SCFGR_I2SMOD_Pos) /*!< 0x00000800 */
+#define SPI_I2SCFGR_I2SMOD SPI_I2SCFGR_I2SMOD_Msk /*!< I2S mode selection */
+
+
+/******************************************************************************/
+/* */
+/* Inter-integrated Circuit Interface */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for I2C_CR1 register ********************/
+#define I2C_CR1_PE_Pos (0U)
+#define I2C_CR1_PE_Msk (0x1U << I2C_CR1_PE_Pos) /*!< 0x00000001 */
+#define I2C_CR1_PE I2C_CR1_PE_Msk /*!< Peripheral Enable */
+#define I2C_CR1_SMBUS_Pos (1U)
+#define I2C_CR1_SMBUS_Msk (0x1U << I2C_CR1_SMBUS_Pos) /*!< 0x00000002 */
+#define I2C_CR1_SMBUS I2C_CR1_SMBUS_Msk /*!< SMBus Mode */
+#define I2C_CR1_SMBTYPE_Pos (3U)
+#define I2C_CR1_SMBTYPE_Msk (0x1U << I2C_CR1_SMBTYPE_Pos) /*!< 0x00000008 */
+#define I2C_CR1_SMBTYPE I2C_CR1_SMBTYPE_Msk /*!< SMBus Type */
+#define I2C_CR1_ENARP_Pos (4U)
+#define I2C_CR1_ENARP_Msk (0x1U << I2C_CR1_ENARP_Pos) /*!< 0x00000010 */
+#define I2C_CR1_ENARP I2C_CR1_ENARP_Msk /*!< ARP Enable */
+#define I2C_CR1_ENPEC_Pos (5U)
+#define I2C_CR1_ENPEC_Msk (0x1U << I2C_CR1_ENPEC_Pos) /*!< 0x00000020 */
+#define I2C_CR1_ENPEC I2C_CR1_ENPEC_Msk /*!< PEC Enable */
+#define I2C_CR1_ENGC_Pos (6U)
+#define I2C_CR1_ENGC_Msk (0x1U << I2C_CR1_ENGC_Pos) /*!< 0x00000040 */
+#define I2C_CR1_ENGC I2C_CR1_ENGC_Msk /*!< General Call Enable */
+#define I2C_CR1_NOSTRETCH_Pos (7U)
+#define I2C_CR1_NOSTRETCH_Msk (0x1U << I2C_CR1_NOSTRETCH_Pos) /*!< 0x00000080 */
+#define I2C_CR1_NOSTRETCH I2C_CR1_NOSTRETCH_Msk /*!< Clock Stretching Disable (Slave mode) */
+#define I2C_CR1_START_Pos (8U)
+#define I2C_CR1_START_Msk (0x1U << I2C_CR1_START_Pos) /*!< 0x00000100 */
+#define I2C_CR1_START I2C_CR1_START_Msk /*!< Start Generation */
+#define I2C_CR1_STOP_Pos (9U)
+#define I2C_CR1_STOP_Msk (0x1U << I2C_CR1_STOP_Pos) /*!< 0x00000200 */
+#define I2C_CR1_STOP I2C_CR1_STOP_Msk /*!< Stop Generation */
+#define I2C_CR1_ACK_Pos (10U)
+#define I2C_CR1_ACK_Msk (0x1U << I2C_CR1_ACK_Pos) /*!< 0x00000400 */
+#define I2C_CR1_ACK I2C_CR1_ACK_Msk /*!< Acknowledge Enable */
+#define I2C_CR1_POS_Pos (11U)
+#define I2C_CR1_POS_Msk (0x1U << I2C_CR1_POS_Pos) /*!< 0x00000800 */
+#define I2C_CR1_POS I2C_CR1_POS_Msk /*!< Acknowledge/PEC Position (for data reception) */
+#define I2C_CR1_PEC_Pos (12U)
+#define I2C_CR1_PEC_Msk (0x1U << I2C_CR1_PEC_Pos) /*!< 0x00001000 */
+#define I2C_CR1_PEC I2C_CR1_PEC_Msk /*!< Packet Error Checking */
+#define I2C_CR1_ALERT_Pos (13U)
+#define I2C_CR1_ALERT_Msk (0x1U << I2C_CR1_ALERT_Pos) /*!< 0x00002000 */
+#define I2C_CR1_ALERT I2C_CR1_ALERT_Msk /*!< SMBus Alert */
+#define I2C_CR1_SWRST_Pos (15U)
+#define I2C_CR1_SWRST_Msk (0x1U << I2C_CR1_SWRST_Pos) /*!< 0x00008000 */
+#define I2C_CR1_SWRST I2C_CR1_SWRST_Msk /*!< Software Reset */
+
+/******************* Bit definition for I2C_CR2 register ********************/
+#define I2C_CR2_FREQ_Pos (0U)
+#define I2C_CR2_FREQ_Msk (0x3FU << I2C_CR2_FREQ_Pos) /*!< 0x0000003F */
+#define I2C_CR2_FREQ I2C_CR2_FREQ_Msk /*!< FREQ[5:0] bits (Peripheral Clock Frequency) */
+#define I2C_CR2_FREQ_0 (0x01U << I2C_CR2_FREQ_Pos) /*!< 0x00000001 */
+#define I2C_CR2_FREQ_1 (0x02U << I2C_CR2_FREQ_Pos) /*!< 0x00000002 */
+#define I2C_CR2_FREQ_2 (0x04U << I2C_CR2_FREQ_Pos) /*!< 0x00000004 */
+#define I2C_CR2_FREQ_3 (0x08U << I2C_CR2_FREQ_Pos) /*!< 0x00000008 */
+#define I2C_CR2_FREQ_4 (0x10U << I2C_CR2_FREQ_Pos) /*!< 0x00000010 */
+#define I2C_CR2_FREQ_5 (0x20U << I2C_CR2_FREQ_Pos) /*!< 0x00000020 */
+
+#define I2C_CR2_ITERREN_Pos (8U)
+#define I2C_CR2_ITERREN_Msk (0x1U << I2C_CR2_ITERREN_Pos) /*!< 0x00000100 */
+#define I2C_CR2_ITERREN I2C_CR2_ITERREN_Msk /*!< Error Interrupt Enable */
+#define I2C_CR2_ITEVTEN_Pos (9U)
+#define I2C_CR2_ITEVTEN_Msk (0x1U << I2C_CR2_ITEVTEN_Pos) /*!< 0x00000200 */
+#define I2C_CR2_ITEVTEN I2C_CR2_ITEVTEN_Msk /*!< Event Interrupt Enable */
+#define I2C_CR2_ITBUFEN_Pos (10U)
+#define I2C_CR2_ITBUFEN_Msk (0x1U << I2C_CR2_ITBUFEN_Pos) /*!< 0x00000400 */
+#define I2C_CR2_ITBUFEN I2C_CR2_ITBUFEN_Msk /*!< Buffer Interrupt Enable */
+#define I2C_CR2_DMAEN_Pos (11U)
+#define I2C_CR2_DMAEN_Msk (0x1U << I2C_CR2_DMAEN_Pos) /*!< 0x00000800 */
+#define I2C_CR2_DMAEN I2C_CR2_DMAEN_Msk /*!< DMA Requests Enable */
+#define I2C_CR2_LAST_Pos (12U)
+#define I2C_CR2_LAST_Msk (0x1U << I2C_CR2_LAST_Pos) /*!< 0x00001000 */
+#define I2C_CR2_LAST I2C_CR2_LAST_Msk /*!< DMA Last Transfer */
+
+/******************* Bit definition for I2C_OAR1 register *******************/
+#define I2C_OAR1_ADD1_7 ((uint32_t)0x000000FE) /*!< Interface Address */
+#define I2C_OAR1_ADD8_9 ((uint32_t)0x00000300) /*!< Interface Address */
+
+#define I2C_OAR1_ADD0_Pos (0U)
+#define I2C_OAR1_ADD0_Msk (0x1U << I2C_OAR1_ADD0_Pos) /*!< 0x00000001 */
+#define I2C_OAR1_ADD0 I2C_OAR1_ADD0_Msk /*!< Bit 0 */
+#define I2C_OAR1_ADD1_Pos (1U)
+#define I2C_OAR1_ADD1_Msk (0x1U << I2C_OAR1_ADD1_Pos) /*!< 0x00000002 */
+#define I2C_OAR1_ADD1 I2C_OAR1_ADD1_Msk /*!< Bit 1 */
+#define I2C_OAR1_ADD2_Pos (2U)
+#define I2C_OAR1_ADD2_Msk (0x1U << I2C_OAR1_ADD2_Pos) /*!< 0x00000004 */
+#define I2C_OAR1_ADD2 I2C_OAR1_ADD2_Msk /*!< Bit 2 */
+#define I2C_OAR1_ADD3_Pos (3U)
+#define I2C_OAR1_ADD3_Msk (0x1U << I2C_OAR1_ADD3_Pos) /*!< 0x00000008 */
+#define I2C_OAR1_ADD3 I2C_OAR1_ADD3_Msk /*!< Bit 3 */
+#define I2C_OAR1_ADD4_Pos (4U)
+#define I2C_OAR1_ADD4_Msk (0x1U << I2C_OAR1_ADD4_Pos) /*!< 0x00000010 */
+#define I2C_OAR1_ADD4 I2C_OAR1_ADD4_Msk /*!< Bit 4 */
+#define I2C_OAR1_ADD5_Pos (5U)
+#define I2C_OAR1_ADD5_Msk (0x1U << I2C_OAR1_ADD5_Pos) /*!< 0x00000020 */
+#define I2C_OAR1_ADD5 I2C_OAR1_ADD5_Msk /*!< Bit 5 */
+#define I2C_OAR1_ADD6_Pos (6U)
+#define I2C_OAR1_ADD6_Msk (0x1U << I2C_OAR1_ADD6_Pos) /*!< 0x00000040 */
+#define I2C_OAR1_ADD6 I2C_OAR1_ADD6_Msk /*!< Bit 6 */
+#define I2C_OAR1_ADD7_Pos (7U)
+#define I2C_OAR1_ADD7_Msk (0x1U << I2C_OAR1_ADD7_Pos) /*!< 0x00000080 */
+#define I2C_OAR1_ADD7 I2C_OAR1_ADD7_Msk /*!< Bit 7 */
+#define I2C_OAR1_ADD8_Pos (8U)
+#define I2C_OAR1_ADD8_Msk (0x1U << I2C_OAR1_ADD8_Pos) /*!< 0x00000100 */
+#define I2C_OAR1_ADD8 I2C_OAR1_ADD8_Msk /*!< Bit 8 */
+#define I2C_OAR1_ADD9_Pos (9U)
+#define I2C_OAR1_ADD9_Msk (0x1U << I2C_OAR1_ADD9_Pos) /*!< 0x00000200 */
+#define I2C_OAR1_ADD9 I2C_OAR1_ADD9_Msk /*!< Bit 9 */
+
+#define I2C_OAR1_ADDMODE_Pos (15U)
+#define I2C_OAR1_ADDMODE_Msk (0x1U << I2C_OAR1_ADDMODE_Pos) /*!< 0x00008000 */
+#define I2C_OAR1_ADDMODE I2C_OAR1_ADDMODE_Msk /*!< Addressing Mode (Slave mode) */
+
+/******************* Bit definition for I2C_OAR2 register *******************/
+#define I2C_OAR2_ENDUAL_Pos (0U)
+#define I2C_OAR2_ENDUAL_Msk (0x1U << I2C_OAR2_ENDUAL_Pos) /*!< 0x00000001 */
+#define I2C_OAR2_ENDUAL I2C_OAR2_ENDUAL_Msk /*!< Dual addressing mode enable */
+#define I2C_OAR2_ADD2_Pos (1U)
+#define I2C_OAR2_ADD2_Msk (0x7FU << I2C_OAR2_ADD2_Pos) /*!< 0x000000FE */
+#define I2C_OAR2_ADD2 I2C_OAR2_ADD2_Msk /*!< Interface address */
+
+/******************* Bit definition for I2C_SR1 register ********************/
+#define I2C_SR1_SB_Pos (0U)
+#define I2C_SR1_SB_Msk (0x1U << I2C_SR1_SB_Pos) /*!< 0x00000001 */
+#define I2C_SR1_SB I2C_SR1_SB_Msk /*!< Start Bit (Master mode) */
+#define I2C_SR1_ADDR_Pos (1U)
+#define I2C_SR1_ADDR_Msk (0x1U << I2C_SR1_ADDR_Pos) /*!< 0x00000002 */
+#define I2C_SR1_ADDR I2C_SR1_ADDR_Msk /*!< Address sent (master mode)/matched (slave mode) */
+#define I2C_SR1_BTF_Pos (2U)
+#define I2C_SR1_BTF_Msk (0x1U << I2C_SR1_BTF_Pos) /*!< 0x00000004 */
+#define I2C_SR1_BTF I2C_SR1_BTF_Msk /*!< Byte Transfer Finished */
+#define I2C_SR1_ADD10_Pos (3U)
+#define I2C_SR1_ADD10_Msk (0x1U << I2C_SR1_ADD10_Pos) /*!< 0x00000008 */
+#define I2C_SR1_ADD10 I2C_SR1_ADD10_Msk /*!< 10-bit header sent (Master mode) */
+#define I2C_SR1_STOPF_Pos (4U)
+#define I2C_SR1_STOPF_Msk (0x1U << I2C_SR1_STOPF_Pos) /*!< 0x00000010 */
+#define I2C_SR1_STOPF I2C_SR1_STOPF_Msk /*!< Stop detection (Slave mode) */
+#define I2C_SR1_RXNE_Pos (6U)
+#define I2C_SR1_RXNE_Msk (0x1U << I2C_SR1_RXNE_Pos) /*!< 0x00000040 */
+#define I2C_SR1_RXNE I2C_SR1_RXNE_Msk /*!< Data Register not Empty (receivers) */
+#define I2C_SR1_TXE_Pos (7U)
+#define I2C_SR1_TXE_Msk (0x1U << I2C_SR1_TXE_Pos) /*!< 0x00000080 */
+#define I2C_SR1_TXE I2C_SR1_TXE_Msk /*!< Data Register Empty (transmitters) */
+#define I2C_SR1_BERR_Pos (8U)
+#define I2C_SR1_BERR_Msk (0x1U << I2C_SR1_BERR_Pos) /*!< 0x00000100 */
+#define I2C_SR1_BERR I2C_SR1_BERR_Msk /*!< Bus Error */
+#define I2C_SR1_ARLO_Pos (9U)
+#define I2C_SR1_ARLO_Msk (0x1U << I2C_SR1_ARLO_Pos) /*!< 0x00000200 */
+#define I2C_SR1_ARLO I2C_SR1_ARLO_Msk /*!< Arbitration Lost (master mode) */
+#define I2C_SR1_AF_Pos (10U)
+#define I2C_SR1_AF_Msk (0x1U << I2C_SR1_AF_Pos) /*!< 0x00000400 */
+#define I2C_SR1_AF I2C_SR1_AF_Msk /*!< Acknowledge Failure */
+#define I2C_SR1_OVR_Pos (11U)
+#define I2C_SR1_OVR_Msk (0x1U << I2C_SR1_OVR_Pos) /*!< 0x00000800 */
+#define I2C_SR1_OVR I2C_SR1_OVR_Msk /*!< Overrun/Underrun */
+#define I2C_SR1_PECERR_Pos (12U)
+#define I2C_SR1_PECERR_Msk (0x1U << I2C_SR1_PECERR_Pos) /*!< 0x00001000 */
+#define I2C_SR1_PECERR I2C_SR1_PECERR_Msk /*!< PEC Error in reception */
+#define I2C_SR1_TIMEOUT_Pos (14U)
+#define I2C_SR1_TIMEOUT_Msk (0x1U << I2C_SR1_TIMEOUT_Pos) /*!< 0x00004000 */
+#define I2C_SR1_TIMEOUT I2C_SR1_TIMEOUT_Msk /*!< Timeout or Tlow Error */
+#define I2C_SR1_SMBALERT_Pos (15U)
+#define I2C_SR1_SMBALERT_Msk (0x1U << I2C_SR1_SMBALERT_Pos) /*!< 0x00008000 */
+#define I2C_SR1_SMBALERT I2C_SR1_SMBALERT_Msk /*!< SMBus Alert */
+
+/******************* Bit definition for I2C_SR2 register ********************/
+#define I2C_SR2_MSL_Pos (0U)
+#define I2C_SR2_MSL_Msk (0x1U << I2C_SR2_MSL_Pos) /*!< 0x00000001 */
+#define I2C_SR2_MSL I2C_SR2_MSL_Msk /*!< Master/Slave */
+#define I2C_SR2_BUSY_Pos (1U)
+#define I2C_SR2_BUSY_Msk (0x1U << I2C_SR2_BUSY_Pos) /*!< 0x00000002 */
+#define I2C_SR2_BUSY I2C_SR2_BUSY_Msk /*!< Bus Busy */
+#define I2C_SR2_TRA_Pos (2U)
+#define I2C_SR2_TRA_Msk (0x1U << I2C_SR2_TRA_Pos) /*!< 0x00000004 */
+#define I2C_SR2_TRA I2C_SR2_TRA_Msk /*!< Transmitter/Receiver */
+#define I2C_SR2_GENCALL_Pos (4U)
+#define I2C_SR2_GENCALL_Msk (0x1U << I2C_SR2_GENCALL_Pos) /*!< 0x00000010 */
+#define I2C_SR2_GENCALL I2C_SR2_GENCALL_Msk /*!< General Call Address (Slave mode) */
+#define I2C_SR2_SMBDEFAULT_Pos (5U)
+#define I2C_SR2_SMBDEFAULT_Msk (0x1U << I2C_SR2_SMBDEFAULT_Pos) /*!< 0x00000020 */
+#define I2C_SR2_SMBDEFAULT I2C_SR2_SMBDEFAULT_Msk /*!< SMBus Device Default Address (Slave mode) */
+#define I2C_SR2_SMBHOST_Pos (6U)
+#define I2C_SR2_SMBHOST_Msk (0x1U << I2C_SR2_SMBHOST_Pos) /*!< 0x00000040 */
+#define I2C_SR2_SMBHOST I2C_SR2_SMBHOST_Msk /*!< SMBus Host Header (Slave mode) */
+#define I2C_SR2_DUALF_Pos (7U)
+#define I2C_SR2_DUALF_Msk (0x1U << I2C_SR2_DUALF_Pos) /*!< 0x00000080 */
+#define I2C_SR2_DUALF I2C_SR2_DUALF_Msk /*!< Dual Flag (Slave mode) */
+#define I2C_SR2_PEC_Pos (8U)
+#define I2C_SR2_PEC_Msk (0xFFU << I2C_SR2_PEC_Pos) /*!< 0x0000FF00 */
+#define I2C_SR2_PEC I2C_SR2_PEC_Msk /*!< Packet Error Checking Register */
+
+/******************* Bit definition for I2C_CCR register ********************/
+#define I2C_CCR_CCR_Pos (0U)
+#define I2C_CCR_CCR_Msk (0xFFFU << I2C_CCR_CCR_Pos) /*!< 0x00000FFF */
+#define I2C_CCR_CCR I2C_CCR_CCR_Msk /*!< Clock Control Register in Fast/Standard mode (Master mode) */
+#define I2C_CCR_DUTY_Pos (14U)
+#define I2C_CCR_DUTY_Msk (0x1U << I2C_CCR_DUTY_Pos) /*!< 0x00004000 */
+#define I2C_CCR_DUTY I2C_CCR_DUTY_Msk /*!< Fast Mode Duty Cycle */
+#define I2C_CCR_FS_Pos (15U)
+#define I2C_CCR_FS_Msk (0x1U << I2C_CCR_FS_Pos) /*!< 0x00008000 */
+#define I2C_CCR_FS I2C_CCR_FS_Msk /*!< I2C Master Mode Selection */
+
+/****************** Bit definition for I2C_TRISE register *******************/
+#define I2C_TRISE_TRISE_Pos (0U)
+#define I2C_TRISE_TRISE_Msk (0x3FU << I2C_TRISE_TRISE_Pos) /*!< 0x0000003F */
+#define I2C_TRISE_TRISE I2C_TRISE_TRISE_Msk /*!< Maximum Rise Time in Fast/Standard mode (Master mode) */
+
+/******************************************************************************/
+/* */
+/* Universal Synchronous Asynchronous Receiver Transmitter */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for USART_SR register *******************/
+#define USART_SR_PE_Pos (0U)
+#define USART_SR_PE_Msk (0x1U << USART_SR_PE_Pos) /*!< 0x00000001 */
+#define USART_SR_PE USART_SR_PE_Msk /*!< Parity Error */
+#define USART_SR_FE_Pos (1U)
+#define USART_SR_FE_Msk (0x1U << USART_SR_FE_Pos) /*!< 0x00000002 */
+#define USART_SR_FE USART_SR_FE_Msk /*!< Framing Error */
+#define USART_SR_NE_Pos (2U)
+#define USART_SR_NE_Msk (0x1U << USART_SR_NE_Pos) /*!< 0x00000004 */
+#define USART_SR_NE USART_SR_NE_Msk /*!< Noise Error Flag */
+#define USART_SR_ORE_Pos (3U)
+#define USART_SR_ORE_Msk (0x1U << USART_SR_ORE_Pos) /*!< 0x00000008 */
+#define USART_SR_ORE USART_SR_ORE_Msk /*!< OverRun Error */
+#define USART_SR_IDLE_Pos (4U)
+#define USART_SR_IDLE_Msk (0x1U << USART_SR_IDLE_Pos) /*!< 0x00000010 */
+#define USART_SR_IDLE USART_SR_IDLE_Msk /*!< IDLE line detected */
+#define USART_SR_RXNE_Pos (5U)
+#define USART_SR_RXNE_Msk (0x1U << USART_SR_RXNE_Pos) /*!< 0x00000020 */
+#define USART_SR_RXNE USART_SR_RXNE_Msk /*!< Read Data Register Not Empty */
+#define USART_SR_TC_Pos (6U)
+#define USART_SR_TC_Msk (0x1U << USART_SR_TC_Pos) /*!< 0x00000040 */
+#define USART_SR_TC USART_SR_TC_Msk /*!< Transmission Complete */
+#define USART_SR_TXE_Pos (7U)
+#define USART_SR_TXE_Msk (0x1U << USART_SR_TXE_Pos) /*!< 0x00000080 */
+#define USART_SR_TXE USART_SR_TXE_Msk /*!< Transmit Data Register Empty */
+#define USART_SR_LBD_Pos (8U)
+#define USART_SR_LBD_Msk (0x1U << USART_SR_LBD_Pos) /*!< 0x00000100 */
+#define USART_SR_LBD USART_SR_LBD_Msk /*!< LIN Break Detection Flag */
+#define USART_SR_CTS_Pos (9U)
+#define USART_SR_CTS_Msk (0x1U << USART_SR_CTS_Pos) /*!< 0x00000200 */
+#define USART_SR_CTS USART_SR_CTS_Msk /*!< CTS Flag */
+
+/******************* Bit definition for USART_DR register *******************/
+#define USART_DR_DR_Pos (0U)
+#define USART_DR_DR_Msk (0x1FFU << USART_DR_DR_Pos) /*!< 0x000001FF */
+#define USART_DR_DR USART_DR_DR_Msk /*!< Data value */
+
+/****************** Bit definition for USART_BRR register *******************/
+#define USART_BRR_DIV_Fraction_Pos (0U)
+#define USART_BRR_DIV_Fraction_Msk (0xFU << USART_BRR_DIV_Fraction_Pos) /*!< 0x0000000F */
+#define USART_BRR_DIV_Fraction USART_BRR_DIV_Fraction_Msk /*!< Fraction of USARTDIV */
+#define USART_BRR_DIV_Mantissa_Pos (4U)
+#define USART_BRR_DIV_Mantissa_Msk (0xFFFU << USART_BRR_DIV_Mantissa_Pos) /*!< 0x0000FFF0 */
+#define USART_BRR_DIV_Mantissa USART_BRR_DIV_Mantissa_Msk /*!< Mantissa of USARTDIV */
+
+/****************** Bit definition for USART_CR1 register *******************/
+#define USART_CR1_SBK_Pos (0U)
+#define USART_CR1_SBK_Msk (0x1U << USART_CR1_SBK_Pos) /*!< 0x00000001 */
+#define USART_CR1_SBK USART_CR1_SBK_Msk /*!< Send Break */
+#define USART_CR1_RWU_Pos (1U)
+#define USART_CR1_RWU_Msk (0x1U << USART_CR1_RWU_Pos) /*!< 0x00000002 */
+#define USART_CR1_RWU USART_CR1_RWU_Msk /*!< Receiver wakeup */
+#define USART_CR1_RE_Pos (2U)
+#define USART_CR1_RE_Msk (0x1U << USART_CR1_RE_Pos) /*!< 0x00000004 */
+#define USART_CR1_RE USART_CR1_RE_Msk /*!< Receiver Enable */
+#define USART_CR1_TE_Pos (3U)
+#define USART_CR1_TE_Msk (0x1U << USART_CR1_TE_Pos) /*!< 0x00000008 */
+#define USART_CR1_TE USART_CR1_TE_Msk /*!< Transmitter Enable */
+#define USART_CR1_IDLEIE_Pos (4U)
+#define USART_CR1_IDLEIE_Msk (0x1U << USART_CR1_IDLEIE_Pos) /*!< 0x00000010 */
+#define USART_CR1_IDLEIE USART_CR1_IDLEIE_Msk /*!< IDLE Interrupt Enable */
+#define USART_CR1_RXNEIE_Pos (5U)
+#define USART_CR1_RXNEIE_Msk (0x1U << USART_CR1_RXNEIE_Pos) /*!< 0x00000020 */
+#define USART_CR1_RXNEIE USART_CR1_RXNEIE_Msk /*!< RXNE Interrupt Enable */
+#define USART_CR1_TCIE_Pos (6U)
+#define USART_CR1_TCIE_Msk (0x1U << USART_CR1_TCIE_Pos) /*!< 0x00000040 */
+#define USART_CR1_TCIE USART_CR1_TCIE_Msk /*!< Transmission Complete Interrupt Enable */
+#define USART_CR1_TXEIE_Pos (7U)
+#define USART_CR1_TXEIE_Msk (0x1U << USART_CR1_TXEIE_Pos) /*!< 0x00000080 */
+#define USART_CR1_TXEIE USART_CR1_TXEIE_Msk /*!< PE Interrupt Enable */
+#define USART_CR1_PEIE_Pos (8U)
+#define USART_CR1_PEIE_Msk (0x1U << USART_CR1_PEIE_Pos) /*!< 0x00000100 */
+#define USART_CR1_PEIE USART_CR1_PEIE_Msk /*!< PE Interrupt Enable */
+#define USART_CR1_PS_Pos (9U)
+#define USART_CR1_PS_Msk (0x1U << USART_CR1_PS_Pos) /*!< 0x00000200 */
+#define USART_CR1_PS USART_CR1_PS_Msk /*!< Parity Selection */
+#define USART_CR1_PCE_Pos (10U)
+#define USART_CR1_PCE_Msk (0x1U << USART_CR1_PCE_Pos) /*!< 0x00000400 */
+#define USART_CR1_PCE USART_CR1_PCE_Msk /*!< Parity Control Enable */
+#define USART_CR1_WAKE_Pos (11U)
+#define USART_CR1_WAKE_Msk (0x1U << USART_CR1_WAKE_Pos) /*!< 0x00000800 */
+#define USART_CR1_WAKE USART_CR1_WAKE_Msk /*!< Wakeup method */
+#define USART_CR1_M_Pos (12U)
+#define USART_CR1_M_Msk (0x1U << USART_CR1_M_Pos) /*!< 0x00001000 */
+#define USART_CR1_M USART_CR1_M_Msk /*!< Word length */
+#define USART_CR1_UE_Pos (13U)
+#define USART_CR1_UE_Msk (0x1U << USART_CR1_UE_Pos) /*!< 0x00002000 */
+#define USART_CR1_UE USART_CR1_UE_Msk /*!< USART Enable */
+
+/****************** Bit definition for USART_CR2 register *******************/
+#define USART_CR2_ADD_Pos (0U)
+#define USART_CR2_ADD_Msk (0xFU << USART_CR2_ADD_Pos) /*!< 0x0000000F */
+#define USART_CR2_ADD USART_CR2_ADD_Msk /*!< Address of the USART node */
+#define USART_CR2_LBDL_Pos (5U)
+#define USART_CR2_LBDL_Msk (0x1U << USART_CR2_LBDL_Pos) /*!< 0x00000020 */
+#define USART_CR2_LBDL USART_CR2_LBDL_Msk /*!< LIN Break Detection Length */
+#define USART_CR2_LBDIE_Pos (6U)
+#define USART_CR2_LBDIE_Msk (0x1U << USART_CR2_LBDIE_Pos) /*!< 0x00000040 */
+#define USART_CR2_LBDIE USART_CR2_LBDIE_Msk /*!< LIN Break Detection Interrupt Enable */
+#define USART_CR2_LBCL_Pos (8U)
+#define USART_CR2_LBCL_Msk (0x1U << USART_CR2_LBCL_Pos) /*!< 0x00000100 */
+#define USART_CR2_LBCL USART_CR2_LBCL_Msk /*!< Last Bit Clock pulse */
+#define USART_CR2_CPHA_Pos (9U)
+#define USART_CR2_CPHA_Msk (0x1U << USART_CR2_CPHA_Pos) /*!< 0x00000200 */
+#define USART_CR2_CPHA USART_CR2_CPHA_Msk /*!< Clock Phase */
+#define USART_CR2_CPOL_Pos (10U)
+#define USART_CR2_CPOL_Msk (0x1U << USART_CR2_CPOL_Pos) /*!< 0x00000400 */
+#define USART_CR2_CPOL USART_CR2_CPOL_Msk /*!< Clock Polarity */
+#define USART_CR2_CLKEN_Pos (11U)
+#define USART_CR2_CLKEN_Msk (0x1U << USART_CR2_CLKEN_Pos) /*!< 0x00000800 */
+#define USART_CR2_CLKEN USART_CR2_CLKEN_Msk /*!< Clock Enable */
+
+#define USART_CR2_STOP_Pos (12U)
+#define USART_CR2_STOP_Msk (0x3U << USART_CR2_STOP_Pos) /*!< 0x00003000 */
+#define USART_CR2_STOP USART_CR2_STOP_Msk /*!< STOP[1:0] bits (STOP bits) */
+#define USART_CR2_STOP_0 (0x1U << USART_CR2_STOP_Pos) /*!< 0x00001000 */
+#define USART_CR2_STOP_1 (0x2U << USART_CR2_STOP_Pos) /*!< 0x00002000 */
+
+#define USART_CR2_LINEN_Pos (14U)
+#define USART_CR2_LINEN_Msk (0x1U << USART_CR2_LINEN_Pos) /*!< 0x00004000 */
+#define USART_CR2_LINEN USART_CR2_LINEN_Msk /*!< LIN mode enable */
+
+/****************** Bit definition for USART_CR3 register *******************/
+#define USART_CR3_EIE_Pos (0U)
+#define USART_CR3_EIE_Msk (0x1U << USART_CR3_EIE_Pos) /*!< 0x00000001 */
+#define USART_CR3_EIE USART_CR3_EIE_Msk /*!< Error Interrupt Enable */
+#define USART_CR3_IREN_Pos (1U)
+#define USART_CR3_IREN_Msk (0x1U << USART_CR3_IREN_Pos) /*!< 0x00000002 */
+#define USART_CR3_IREN USART_CR3_IREN_Msk /*!< IrDA mode Enable */
+#define USART_CR3_IRLP_Pos (2U)
+#define USART_CR3_IRLP_Msk (0x1U << USART_CR3_IRLP_Pos) /*!< 0x00000004 */
+#define USART_CR3_IRLP USART_CR3_IRLP_Msk /*!< IrDA Low-Power */
+#define USART_CR3_HDSEL_Pos (3U)
+#define USART_CR3_HDSEL_Msk (0x1U << USART_CR3_HDSEL_Pos) /*!< 0x00000008 */
+#define USART_CR3_HDSEL USART_CR3_HDSEL_Msk /*!< Half-Duplex Selection */
+#define USART_CR3_NACK_Pos (4U)
+#define USART_CR3_NACK_Msk (0x1U << USART_CR3_NACK_Pos) /*!< 0x00000010 */
+#define USART_CR3_NACK USART_CR3_NACK_Msk /*!< Smartcard NACK enable */
+#define USART_CR3_SCEN_Pos (5U)
+#define USART_CR3_SCEN_Msk (0x1U << USART_CR3_SCEN_Pos) /*!< 0x00000020 */
+#define USART_CR3_SCEN USART_CR3_SCEN_Msk /*!< Smartcard mode enable */
+#define USART_CR3_DMAR_Pos (6U)
+#define USART_CR3_DMAR_Msk (0x1U << USART_CR3_DMAR_Pos) /*!< 0x00000040 */
+#define USART_CR3_DMAR USART_CR3_DMAR_Msk /*!< DMA Enable Receiver */
+#define USART_CR3_DMAT_Pos (7U)
+#define USART_CR3_DMAT_Msk (0x1U << USART_CR3_DMAT_Pos) /*!< 0x00000080 */
+#define USART_CR3_DMAT USART_CR3_DMAT_Msk /*!< DMA Enable Transmitter */
+#define USART_CR3_RTSE_Pos (8U)
+#define USART_CR3_RTSE_Msk (0x1U << USART_CR3_RTSE_Pos) /*!< 0x00000100 */
+#define USART_CR3_RTSE USART_CR3_RTSE_Msk /*!< RTS Enable */
+#define USART_CR3_CTSE_Pos (9U)
+#define USART_CR3_CTSE_Msk (0x1U << USART_CR3_CTSE_Pos) /*!< 0x00000200 */
+#define USART_CR3_CTSE USART_CR3_CTSE_Msk /*!< CTS Enable */
+#define USART_CR3_CTSIE_Pos (10U)
+#define USART_CR3_CTSIE_Msk (0x1U << USART_CR3_CTSIE_Pos) /*!< 0x00000400 */
+#define USART_CR3_CTSIE USART_CR3_CTSIE_Msk /*!< CTS Interrupt Enable */
+
+/****************** Bit definition for USART_GTPR register ******************/
+#define USART_GTPR_PSC_Pos (0U)
+#define USART_GTPR_PSC_Msk (0xFFU << USART_GTPR_PSC_Pos) /*!< 0x000000FF */
+#define USART_GTPR_PSC USART_GTPR_PSC_Msk /*!< PSC[7:0] bits (Prescaler value) */
+#define USART_GTPR_PSC_0 (0x01U << USART_GTPR_PSC_Pos) /*!< 0x00000001 */
+#define USART_GTPR_PSC_1 (0x02U << USART_GTPR_PSC_Pos) /*!< 0x00000002 */
+#define USART_GTPR_PSC_2 (0x04U << USART_GTPR_PSC_Pos) /*!< 0x00000004 */
+#define USART_GTPR_PSC_3 (0x08U << USART_GTPR_PSC_Pos) /*!< 0x00000008 */
+#define USART_GTPR_PSC_4 (0x10U << USART_GTPR_PSC_Pos) /*!< 0x00000010 */
+#define USART_GTPR_PSC_5 (0x20U << USART_GTPR_PSC_Pos) /*!< 0x00000020 */
+#define USART_GTPR_PSC_6 (0x40U << USART_GTPR_PSC_Pos) /*!< 0x00000040 */
+#define USART_GTPR_PSC_7 (0x80U << USART_GTPR_PSC_Pos) /*!< 0x00000080 */
+
+#define USART_GTPR_GT_Pos (8U)
+#define USART_GTPR_GT_Msk (0xFFU << USART_GTPR_GT_Pos) /*!< 0x0000FF00 */
+#define USART_GTPR_GT USART_GTPR_GT_Msk /*!< Guard time value */
+
+/******************************************************************************/
+/* */
+/* Debug MCU */
+/* */
+/******************************************************************************/
+
+/**************** Bit definition for DBGMCU_IDCODE register *****************/
+#define DBGMCU_IDCODE_DEV_ID_Pos (0U)
+#define DBGMCU_IDCODE_DEV_ID_Msk (0xFFFU << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */
+#define DBGMCU_IDCODE_DEV_ID DBGMCU_IDCODE_DEV_ID_Msk /*!< Device Identifier */
+
+#define DBGMCU_IDCODE_REV_ID_Pos (16U)
+#define DBGMCU_IDCODE_REV_ID_Msk (0xFFFFU << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */
+#define DBGMCU_IDCODE_REV_ID DBGMCU_IDCODE_REV_ID_Msk /*!< REV_ID[15:0] bits (Revision Identifier) */
+#define DBGMCU_IDCODE_REV_ID_0 (0x0001U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00010000 */
+#define DBGMCU_IDCODE_REV_ID_1 (0x0002U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00020000 */
+#define DBGMCU_IDCODE_REV_ID_2 (0x0004U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00040000 */
+#define DBGMCU_IDCODE_REV_ID_3 (0x0008U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00080000 */
+#define DBGMCU_IDCODE_REV_ID_4 (0x0010U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00100000 */
+#define DBGMCU_IDCODE_REV_ID_5 (0x0020U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00200000 */
+#define DBGMCU_IDCODE_REV_ID_6 (0x0040U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00400000 */
+#define DBGMCU_IDCODE_REV_ID_7 (0x0080U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00800000 */
+#define DBGMCU_IDCODE_REV_ID_8 (0x0100U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x01000000 */
+#define DBGMCU_IDCODE_REV_ID_9 (0x0200U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x02000000 */
+#define DBGMCU_IDCODE_REV_ID_10 (0x0400U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x04000000 */
+#define DBGMCU_IDCODE_REV_ID_11 (0x0800U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x08000000 */
+#define DBGMCU_IDCODE_REV_ID_12 (0x1000U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x10000000 */
+#define DBGMCU_IDCODE_REV_ID_13 (0x2000U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x20000000 */
+#define DBGMCU_IDCODE_REV_ID_14 (0x4000U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x40000000 */
+#define DBGMCU_IDCODE_REV_ID_15 (0x8000U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x80000000 */
+
+/****************** Bit definition for DBGMCU_CR register *******************/
+#define DBGMCU_CR_DBG_SLEEP_Pos (0U)
+#define DBGMCU_CR_DBG_SLEEP_Msk (0x1U << DBGMCU_CR_DBG_SLEEP_Pos) /*!< 0x00000001 */
+#define DBGMCU_CR_DBG_SLEEP DBGMCU_CR_DBG_SLEEP_Msk /*!< Debug Sleep Mode */
+#define DBGMCU_CR_DBG_STOP_Pos (1U)
+#define DBGMCU_CR_DBG_STOP_Msk (0x1U << DBGMCU_CR_DBG_STOP_Pos) /*!< 0x00000002 */
+#define DBGMCU_CR_DBG_STOP DBGMCU_CR_DBG_STOP_Msk /*!< Debug Stop Mode */
+#define DBGMCU_CR_DBG_STANDBY_Pos (2U)
+#define DBGMCU_CR_DBG_STANDBY_Msk (0x1U << DBGMCU_CR_DBG_STANDBY_Pos) /*!< 0x00000004 */
+#define DBGMCU_CR_DBG_STANDBY DBGMCU_CR_DBG_STANDBY_Msk /*!< Debug Standby mode */
+#define DBGMCU_CR_TRACE_IOEN_Pos (5U)
+#define DBGMCU_CR_TRACE_IOEN_Msk (0x1U << DBGMCU_CR_TRACE_IOEN_Pos) /*!< 0x00000020 */
+#define DBGMCU_CR_TRACE_IOEN DBGMCU_CR_TRACE_IOEN_Msk /*!< Trace Pin Assignment Control */
+
+#define DBGMCU_CR_TRACE_MODE_Pos (6U)
+#define DBGMCU_CR_TRACE_MODE_Msk (0x3U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x000000C0 */
+#define DBGMCU_CR_TRACE_MODE DBGMCU_CR_TRACE_MODE_Msk /*!< TRACE_MODE[1:0] bits (Trace Pin Assignment Control) */
+#define DBGMCU_CR_TRACE_MODE_0 (0x1U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000040 */
+#define DBGMCU_CR_TRACE_MODE_1 (0x2U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000080 */
+
+#define DBGMCU_CR_DBG_IWDG_STOP_Pos (8U)
+#define DBGMCU_CR_DBG_IWDG_STOP_Msk (0x1U << DBGMCU_CR_DBG_IWDG_STOP_Pos) /*!< 0x00000100 */
+#define DBGMCU_CR_DBG_IWDG_STOP DBGMCU_CR_DBG_IWDG_STOP_Msk /*!< Debug Independent Watchdog stopped when Core is halted */
+#define DBGMCU_CR_DBG_WWDG_STOP_Pos (9U)
+#define DBGMCU_CR_DBG_WWDG_STOP_Msk (0x1U << DBGMCU_CR_DBG_WWDG_STOP_Pos) /*!< 0x00000200 */
+#define DBGMCU_CR_DBG_WWDG_STOP DBGMCU_CR_DBG_WWDG_STOP_Msk /*!< Debug Window Watchdog stopped when Core is halted */
+#define DBGMCU_CR_DBG_TIM1_STOP_Pos (10U)
+#define DBGMCU_CR_DBG_TIM1_STOP_Msk (0x1U << DBGMCU_CR_DBG_TIM1_STOP_Pos) /*!< 0x00000400 */
+#define DBGMCU_CR_DBG_TIM1_STOP DBGMCU_CR_DBG_TIM1_STOP_Msk /*!< TIM1 counter stopped when core is halted */
+#define DBGMCU_CR_DBG_TIM2_STOP_Pos (11U)
+#define DBGMCU_CR_DBG_TIM2_STOP_Msk (0x1U << DBGMCU_CR_DBG_TIM2_STOP_Pos) /*!< 0x00000800 */
+#define DBGMCU_CR_DBG_TIM2_STOP DBGMCU_CR_DBG_TIM2_STOP_Msk /*!< TIM2 counter stopped when core is halted */
+#define DBGMCU_CR_DBG_TIM3_STOP_Pos (12U)
+#define DBGMCU_CR_DBG_TIM3_STOP_Msk (0x1U << DBGMCU_CR_DBG_TIM3_STOP_Pos) /*!< 0x00001000 */
+#define DBGMCU_CR_DBG_TIM3_STOP DBGMCU_CR_DBG_TIM3_STOP_Msk /*!< TIM3 counter stopped when core is halted */
+#define DBGMCU_CR_DBG_CAN1_STOP_Pos (14U)
+#define DBGMCU_CR_DBG_CAN1_STOP_Msk (0x1U << DBGMCU_CR_DBG_CAN1_STOP_Pos) /*!< 0x00004000 */
+#define DBGMCU_CR_DBG_CAN1_STOP DBGMCU_CR_DBG_CAN1_STOP_Msk /*!< Debug CAN1 stopped when Core is halted */
+#define DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT_Pos (15U)
+#define DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT_Msk (0x1U << DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT_Pos) /*!< 0x00008000 */
+#define DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT_Msk /*!< SMBUS timeout mode stopped when Core is halted */
+
+/******************************************************************************/
+/* */
+/* FLASH and Option Bytes Registers */
+/* */
+/******************************************************************************/
+/******************* Bit definition for FLASH_ACR register ******************/
+#define FLASH_ACR_LATENCY_Pos (0U)
+#define FLASH_ACR_LATENCY_Msk (0x7U << FLASH_ACR_LATENCY_Pos) /*!< 0x00000007 */
+#define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk /*!< LATENCY[2:0] bits (Latency) */
+#define FLASH_ACR_LATENCY_0 (0x1U << FLASH_ACR_LATENCY_Pos) /*!< 0x00000001 */
+#define FLASH_ACR_LATENCY_1 (0x2U << FLASH_ACR_LATENCY_Pos) /*!< 0x00000002 */
+#define FLASH_ACR_LATENCY_2 (0x4U << FLASH_ACR_LATENCY_Pos) /*!< 0x00000004 */
+
+#define FLASH_ACR_HLFCYA_Pos (3U)
+#define FLASH_ACR_HLFCYA_Msk (0x1U << FLASH_ACR_HLFCYA_Pos) /*!< 0x00000008 */
+#define FLASH_ACR_HLFCYA FLASH_ACR_HLFCYA_Msk /*!< Flash Half Cycle Access Enable */
+#define FLASH_ACR_PRFTBE_Pos (4U)
+#define FLASH_ACR_PRFTBE_Msk (0x1U << FLASH_ACR_PRFTBE_Pos) /*!< 0x00000010 */
+#define FLASH_ACR_PRFTBE FLASH_ACR_PRFTBE_Msk /*!< Prefetch Buffer Enable */
+#define FLASH_ACR_PRFTBS_Pos (5U)
+#define FLASH_ACR_PRFTBS_Msk (0x1U << FLASH_ACR_PRFTBS_Pos) /*!< 0x00000020 */
+#define FLASH_ACR_PRFTBS FLASH_ACR_PRFTBS_Msk /*!< Prefetch Buffer Status */
+
+/****************** Bit definition for FLASH_KEYR register ******************/
+#define FLASH_KEYR_FKEYR_Pos (0U)
+#define FLASH_KEYR_FKEYR_Msk (0xFFFFFFFFU << FLASH_KEYR_FKEYR_Pos) /*!< 0xFFFFFFFF */
+#define FLASH_KEYR_FKEYR FLASH_KEYR_FKEYR_Msk /*!< FPEC Key */
+
+#define RDP_KEY_Pos (0U)
+#define RDP_KEY_Msk (0xA5U << RDP_KEY_Pos) /*!< 0x000000A5 */
+#define RDP_KEY RDP_KEY_Msk /*!< RDP Key */
+#define FLASH_KEY1_Pos (0U)
+#define FLASH_KEY1_Msk (0x45670123U << FLASH_KEY1_Pos) /*!< 0x45670123 */
+#define FLASH_KEY1 FLASH_KEY1_Msk /*!< FPEC Key1 */
+#define FLASH_KEY2_Pos (0U)
+#define FLASH_KEY2_Msk (0xCDEF89ABU << FLASH_KEY2_Pos) /*!< 0xCDEF89AB */
+#define FLASH_KEY2 FLASH_KEY2_Msk /*!< FPEC Key2 */
+
+/***************** Bit definition for FLASH_OPTKEYR register ****************/
+#define FLASH_OPTKEYR_OPTKEYR_Pos (0U)
+#define FLASH_OPTKEYR_OPTKEYR_Msk (0xFFFFFFFFU << FLASH_OPTKEYR_OPTKEYR_Pos) /*!< 0xFFFFFFFF */
+#define FLASH_OPTKEYR_OPTKEYR FLASH_OPTKEYR_OPTKEYR_Msk /*!< Option Byte Key */
+
+#define FLASH_OPTKEY1 FLASH_KEY1 /*!< Option Byte Key1 */
+#define FLASH_OPTKEY2 FLASH_KEY2 /*!< Option Byte Key2 */
+
+/****************** Bit definition for FLASH_SR register ********************/
+#define FLASH_SR_BSY_Pos (0U)
+#define FLASH_SR_BSY_Msk (0x1U << FLASH_SR_BSY_Pos) /*!< 0x00000001 */
+#define FLASH_SR_BSY FLASH_SR_BSY_Msk /*!< Busy */
+#define FLASH_SR_PGERR_Pos (2U)
+#define FLASH_SR_PGERR_Msk (0x1U << FLASH_SR_PGERR_Pos) /*!< 0x00000004 */
+#define FLASH_SR_PGERR FLASH_SR_PGERR_Msk /*!< Programming Error */
+#define FLASH_SR_WRPRTERR_Pos (4U)
+#define FLASH_SR_WRPRTERR_Msk (0x1U << FLASH_SR_WRPRTERR_Pos) /*!< 0x00000010 */
+#define FLASH_SR_WRPRTERR FLASH_SR_WRPRTERR_Msk /*!< Write Protection Error */
+#define FLASH_SR_EOP_Pos (5U)
+#define FLASH_SR_EOP_Msk (0x1U << FLASH_SR_EOP_Pos) /*!< 0x00000020 */
+#define FLASH_SR_EOP FLASH_SR_EOP_Msk /*!< End of operation */
+
+/******************* Bit definition for FLASH_CR register *******************/
+#define FLASH_CR_PG_Pos (0U)
+#define FLASH_CR_PG_Msk (0x1U << FLASH_CR_PG_Pos) /*!< 0x00000001 */
+#define FLASH_CR_PG FLASH_CR_PG_Msk /*!< Programming */
+#define FLASH_CR_PER_Pos (1U)
+#define FLASH_CR_PER_Msk (0x1U << FLASH_CR_PER_Pos) /*!< 0x00000002 */
+#define FLASH_CR_PER FLASH_CR_PER_Msk /*!< Page Erase */
+#define FLASH_CR_MER_Pos (2U)
+#define FLASH_CR_MER_Msk (0x1U << FLASH_CR_MER_Pos) /*!< 0x00000004 */
+#define FLASH_CR_MER FLASH_CR_MER_Msk /*!< Mass Erase */
+#define FLASH_CR_OPTPG_Pos (4U)
+#define FLASH_CR_OPTPG_Msk (0x1U << FLASH_CR_OPTPG_Pos) /*!< 0x00000010 */
+#define FLASH_CR_OPTPG FLASH_CR_OPTPG_Msk /*!< Option Byte Programming */
+#define FLASH_CR_OPTER_Pos (5U)
+#define FLASH_CR_OPTER_Msk (0x1U << FLASH_CR_OPTER_Pos) /*!< 0x00000020 */
+#define FLASH_CR_OPTER FLASH_CR_OPTER_Msk /*!< Option Byte Erase */
+#define FLASH_CR_STRT_Pos (6U)
+#define FLASH_CR_STRT_Msk (0x1U << FLASH_CR_STRT_Pos) /*!< 0x00000040 */
+#define FLASH_CR_STRT FLASH_CR_STRT_Msk /*!< Start */
+#define FLASH_CR_LOCK_Pos (7U)
+#define FLASH_CR_LOCK_Msk (0x1U << FLASH_CR_LOCK_Pos) /*!< 0x00000080 */
+#define FLASH_CR_LOCK FLASH_CR_LOCK_Msk /*!< Lock */
+#define FLASH_CR_OPTWRE_Pos (9U)
+#define FLASH_CR_OPTWRE_Msk (0x1U << FLASH_CR_OPTWRE_Pos) /*!< 0x00000200 */
+#define FLASH_CR_OPTWRE FLASH_CR_OPTWRE_Msk /*!< Option Bytes Write Enable */
+#define FLASH_CR_ERRIE_Pos (10U)
+#define FLASH_CR_ERRIE_Msk (0x1U << FLASH_CR_ERRIE_Pos) /*!< 0x00000400 */
+#define FLASH_CR_ERRIE FLASH_CR_ERRIE_Msk /*!< Error Interrupt Enable */
+#define FLASH_CR_EOPIE_Pos (12U)
+#define FLASH_CR_EOPIE_Msk (0x1U << FLASH_CR_EOPIE_Pos) /*!< 0x00001000 */
+#define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk /*!< End of operation interrupt enable */
+
+/******************* Bit definition for FLASH_AR register *******************/
+#define FLASH_AR_FAR_Pos (0U)
+#define FLASH_AR_FAR_Msk (0xFFFFFFFFU << FLASH_AR_FAR_Pos) /*!< 0xFFFFFFFF */
+#define FLASH_AR_FAR FLASH_AR_FAR_Msk /*!< Flash Address */
+
+/****************** Bit definition for FLASH_OBR register *******************/
+#define FLASH_OBR_OPTERR_Pos (0U)
+#define FLASH_OBR_OPTERR_Msk (0x1U << FLASH_OBR_OPTERR_Pos) /*!< 0x00000001 */
+#define FLASH_OBR_OPTERR FLASH_OBR_OPTERR_Msk /*!< Option Byte Error */
+#define FLASH_OBR_RDPRT_Pos (1U)
+#define FLASH_OBR_RDPRT_Msk (0x1U << FLASH_OBR_RDPRT_Pos) /*!< 0x00000002 */
+#define FLASH_OBR_RDPRT FLASH_OBR_RDPRT_Msk /*!< Read protection */
+
+#define FLASH_OBR_IWDG_SW_Pos (2U)
+#define FLASH_OBR_IWDG_SW_Msk (0x1U << FLASH_OBR_IWDG_SW_Pos) /*!< 0x00000004 */
+#define FLASH_OBR_IWDG_SW FLASH_OBR_IWDG_SW_Msk /*!< IWDG SW */
+#define FLASH_OBR_nRST_STOP_Pos (3U)
+#define FLASH_OBR_nRST_STOP_Msk (0x1U << FLASH_OBR_nRST_STOP_Pos) /*!< 0x00000008 */
+#define FLASH_OBR_nRST_STOP FLASH_OBR_nRST_STOP_Msk /*!< nRST_STOP */
+#define FLASH_OBR_nRST_STDBY_Pos (4U)
+#define FLASH_OBR_nRST_STDBY_Msk (0x1U << FLASH_OBR_nRST_STDBY_Pos) /*!< 0x00000010 */
+#define FLASH_OBR_nRST_STDBY FLASH_OBR_nRST_STDBY_Msk /*!< nRST_STDBY */
+#define FLASH_OBR_USER_Pos (2U)
+#define FLASH_OBR_USER_Msk (0x7U << FLASH_OBR_USER_Pos) /*!< 0x0000001C */
+#define FLASH_OBR_USER FLASH_OBR_USER_Msk /*!< User Option Bytes */
+#define FLASH_OBR_DATA0_Pos (10U)
+#define FLASH_OBR_DATA0_Msk (0xFFU << FLASH_OBR_DATA0_Pos) /*!< 0x0003FC00 */
+#define FLASH_OBR_DATA0 FLASH_OBR_DATA0_Msk /*!< Data0 */
+#define FLASH_OBR_DATA1_Pos (18U)
+#define FLASH_OBR_DATA1_Msk (0xFFU << FLASH_OBR_DATA1_Pos) /*!< 0x03FC0000 */
+#define FLASH_OBR_DATA1 FLASH_OBR_DATA1_Msk /*!< Data1 */
+
+/****************** Bit definition for FLASH_WRPR register ******************/
+#define FLASH_WRPR_WRP_Pos (0U)
+#define FLASH_WRPR_WRP_Msk (0xFFFFFFFFU << FLASH_WRPR_WRP_Pos) /*!< 0xFFFFFFFF */
+#define FLASH_WRPR_WRP FLASH_WRPR_WRP_Msk /*!< Write Protect */
+
+/*----------------------------------------------------------------------------*/
+
+/****************** Bit definition for FLASH_RDP register *******************/
+#define FLASH_RDP_RDP_Pos (0U)
+#define FLASH_RDP_RDP_Msk (0xFFU << FLASH_RDP_RDP_Pos) /*!< 0x000000FF */
+#define FLASH_RDP_RDP FLASH_RDP_RDP_Msk /*!< Read protection option byte */
+#define FLASH_RDP_nRDP_Pos (8U)
+#define FLASH_RDP_nRDP_Msk (0xFFU << FLASH_RDP_nRDP_Pos) /*!< 0x0000FF00 */
+#define FLASH_RDP_nRDP FLASH_RDP_nRDP_Msk /*!< Read protection complemented option byte */
+
+/****************** Bit definition for FLASH_USER register ******************/
+#define FLASH_USER_USER_Pos (16U)
+#define FLASH_USER_USER_Msk (0xFFU << FLASH_USER_USER_Pos) /*!< 0x00FF0000 */
+#define FLASH_USER_USER FLASH_USER_USER_Msk /*!< User option byte */
+#define FLASH_USER_nUSER_Pos (24U)
+#define FLASH_USER_nUSER_Msk (0xFFU << FLASH_USER_nUSER_Pos) /*!< 0xFF000000 */
+#define FLASH_USER_nUSER FLASH_USER_nUSER_Msk /*!< User complemented option byte */
+
+/****************** Bit definition for FLASH_Data0 register *****************/
+#define FLASH_DATA0_DATA0_Pos (0U)
+#define FLASH_DATA0_DATA0_Msk (0xFFU << FLASH_DATA0_DATA0_Pos) /*!< 0x000000FF */
+#define FLASH_DATA0_DATA0 FLASH_DATA0_DATA0_Msk /*!< User data storage option byte */
+#define FLASH_DATA0_nDATA0_Pos (8U)
+#define FLASH_DATA0_nDATA0_Msk (0xFFU << FLASH_DATA0_nDATA0_Pos) /*!< 0x0000FF00 */
+#define FLASH_DATA0_nDATA0 FLASH_DATA0_nDATA0_Msk /*!< User data storage complemented option byte */
+
+/****************** Bit definition for FLASH_Data1 register *****************/
+#define FLASH_DATA1_DATA1_Pos (16U)
+#define FLASH_DATA1_DATA1_Msk (0xFFU << FLASH_DATA1_DATA1_Pos) /*!< 0x00FF0000 */
+#define FLASH_DATA1_DATA1 FLASH_DATA1_DATA1_Msk /*!< User data storage option byte */
+#define FLASH_DATA1_nDATA1_Pos (24U)
+#define FLASH_DATA1_nDATA1_Msk (0xFFU << FLASH_DATA1_nDATA1_Pos) /*!< 0xFF000000 */
+#define FLASH_DATA1_nDATA1 FLASH_DATA1_nDATA1_Msk /*!< User data storage complemented option byte */
+
+/****************** Bit definition for FLASH_WRP0 register ******************/
+#define FLASH_WRP0_WRP0_Pos (0U)
+#define FLASH_WRP0_WRP0_Msk (0xFFU << FLASH_WRP0_WRP0_Pos) /*!< 0x000000FF */
+#define FLASH_WRP0_WRP0 FLASH_WRP0_WRP0_Msk /*!< Flash memory write protection option bytes */
+#define FLASH_WRP0_nWRP0_Pos (8U)
+#define FLASH_WRP0_nWRP0_Msk (0xFFU << FLASH_WRP0_nWRP0_Pos) /*!< 0x0000FF00 */
+#define FLASH_WRP0_nWRP0 FLASH_WRP0_nWRP0_Msk /*!< Flash memory write protection complemented option bytes */
+
+
+
+/**
+ * @}
+*/
+
+/**
+ * @}
+*/
+
+/** @addtogroup Exported_macro
+ * @{
+ */
+
+/****************************** ADC Instances *********************************/
+#define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) || \
+ ((INSTANCE) == ADC2))
+
+#define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC12_COMMON)
+
+#define IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
+
+#define IS_ADC_DMA_CAPABILITY_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
+
+/****************************** CAN Instances *********************************/
+#define IS_CAN_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CAN1)
+
+/****************************** CRC Instances *********************************/
+#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
+
+/****************************** DAC Instances *********************************/
+
+/****************************** DMA Instances *********************************/
+#define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \
+ ((INSTANCE) == DMA1_Channel2) || \
+ ((INSTANCE) == DMA1_Channel3) || \
+ ((INSTANCE) == DMA1_Channel4) || \
+ ((INSTANCE) == DMA1_Channel5) || \
+ ((INSTANCE) == DMA1_Channel6) || \
+ ((INSTANCE) == DMA1_Channel7))
+
+/******************************* GPIO Instances *******************************/
+#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
+ ((INSTANCE) == GPIOB) || \
+ ((INSTANCE) == GPIOC) || \
+ ((INSTANCE) == GPIOD))
+
+/**************************** GPIO Alternate Function Instances ***************/
+#define IS_GPIO_AF_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
+
+/**************************** GPIO Lock Instances *****************************/
+#define IS_GPIO_LOCK_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
+
+/******************************** I2C Instances *******************************/
+#define IS_I2C_ALL_INSTANCE(INSTANCE) ((INSTANCE) == I2C1)
+
+/****************************** IWDG Instances ********************************/
+#define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
+
+/******************************** SPI Instances *******************************/
+#define IS_SPI_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SPI1)
+
+/****************************** START TIM Instances ***************************/
+/****************************** TIM Instances *********************************/
+#define IS_TIM_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3))
+
+#define IS_TIM_CC1_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3))
+
+#define IS_TIM_CC2_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3))
+
+#define IS_TIM_CC3_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3))
+
+#define IS_TIM_CC4_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3))
+
+#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3))
+
+#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3))
+
+#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3))
+
+#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3))
+
+#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3))
+
+#define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3))
+
+#define IS_TIM_XOR_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3))
+
+#define IS_TIM_MASTER_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3))
+
+#define IS_TIM_SLAVE_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3))
+
+#define IS_TIM_DMABURST_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3))
+
+#define IS_TIM_BREAK_INSTANCE(INSTANCE)\
+ ((INSTANCE) == TIM1)
+
+#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
+ ((((INSTANCE) == TIM1) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM2) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM3) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))))
+
+#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
+ (((INSTANCE) == TIM1) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3)))
+
+#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3))
+
+#define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE)\
+ ((INSTANCE) == TIM1)
+
+#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3))
+
+#define IS_TIM_DMA_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3))
+
+#define IS_TIM_DMA_CC_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3))
+
+#define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE)\
+ ((INSTANCE) == TIM1)
+
+/****************************** END TIM Instances *****************************/
+
+
+/******************** USART Instances : Synchronous mode **********************/
+#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2))
+
+/******************** UART Instances : Asynchronous mode **********************/
+#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) )
+
+/******************** UART Instances : Half-Duplex mode **********************/
+#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) )
+
+/******************** UART Instances : LIN mode **********************/
+#define IS_UART_LIN_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) )
+
+/****************** UART Instances : Hardware Flow control ********************/
+#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) )
+
+/********************* UART Instances : Smard card mode ***********************/
+#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) )
+
+/*********************** UART Instances : IRDA mode ***************************/
+#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) )
+
+/***************** UART Instances : Multi-Processor mode **********************/
+#define IS_UART_MULTIPROCESSOR_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) )
+
+/***************** UART Instances : DMA mode available **********************/
+#define IS_UART_DMA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) )
+
+/****************************** RTC Instances *********************************/
+#define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
+
+/**************************** WWDG Instances *****************************/
+#define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
+
+/****************************** USB Instances ********************************/
+#define IS_USB_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB)
+
+
+
+
+/**
+ * @}
+*/
+/******************************************************************************/
+/* For a painless codes migration between the STM32F1xx device product */
+/* lines, the aliases defined below are put in place to overcome the */
+/* differences in the interrupt handlers and IRQn definitions. */
+/* No need to update developed interrupt code when moving across */
+/* product lines within the same STM32F1 Family */
+/******************************************************************************/
+
+/* Aliases for __IRQn */
+#define ADC1_IRQn ADC1_2_IRQn
+#define TIM1_BRK_TIM15_IRQn TIM1_BRK_IRQn
+#define TIM1_BRK_TIM9_IRQn TIM1_BRK_IRQn
+#define TIM9_IRQn TIM1_BRK_IRQn
+#define TIM1_TRG_COM_TIM11_IRQn TIM1_TRG_COM_IRQn
+#define TIM1_TRG_COM_TIM17_IRQn TIM1_TRG_COM_IRQn
+#define TIM11_IRQn TIM1_TRG_COM_IRQn
+#define TIM10_IRQn TIM1_UP_IRQn
+#define TIM1_UP_TIM16_IRQn TIM1_UP_IRQn
+#define TIM1_UP_TIM10_IRQn TIM1_UP_IRQn
+#define CEC_IRQn USBWakeUp_IRQn
+#define OTG_FS_WKUP_IRQn USBWakeUp_IRQn
+#define CAN1_TX_IRQn USB_HP_CAN1_TX_IRQn
+#define USB_HP_IRQn USB_HP_CAN1_TX_IRQn
+#define USB_LP_IRQn USB_LP_CAN1_RX0_IRQn
+#define CAN1_RX0_IRQn USB_LP_CAN1_RX0_IRQn
+
+
+/* Aliases for __IRQHandler */
+#define ADC1_IRQHandler ADC1_2_IRQHandler
+#define TIM1_BRK_TIM15_IRQHandler TIM1_BRK_IRQHandler
+#define TIM1_BRK_TIM9_IRQHandler TIM1_BRK_IRQHandler
+#define TIM9_IRQHandler TIM1_BRK_IRQHandler
+#define TIM1_TRG_COM_TIM11_IRQHandler TIM1_TRG_COM_IRQHandler
+#define TIM1_TRG_COM_TIM17_IRQHandler TIM1_TRG_COM_IRQHandler
+#define TIM11_IRQHandler TIM1_TRG_COM_IRQHandler
+#define TIM10_IRQHandler TIM1_UP_IRQHandler
+#define TIM1_UP_TIM16_IRQHandler TIM1_UP_IRQHandler
+#define TIM1_UP_TIM10_IRQHandler TIM1_UP_IRQHandler
+#define CEC_IRQHandler USBWakeUp_IRQHandler
+#define OTG_FS_WKUP_IRQHandler USBWakeUp_IRQHandler
+#define CAN1_TX_IRQHandler USB_HP_CAN1_TX_IRQHandler
+#define USB_HP_IRQHandler USB_HP_CAN1_TX_IRQHandler
+#define USB_LP_IRQHandler USB_LP_CAN1_RX0_IRQHandler
+#define CAN1_RX0_IRQHandler USB_LP_CAN1_RX0_IRQHandler
+
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+
+#ifdef __cplusplus
+ }
+#endif /* __cplusplus */
+
+#endif /* __STM32F103x6_H */
+
+
+
+ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Device/ST/STM32F1xx/Include/stm32f103xb.h b/Device/ST/STM32F1xx/Include/stm32f103xb.h
new file mode 100644
index 0000000..77cbd67
--- /dev/null
+++ b/Device/ST/STM32F1xx/Include/stm32f103xb.h
@@ -0,0 +1,11073 @@
+/**
+ ******************************************************************************
+ * @file stm32f103xb.h
+ * @author MCD Application Team
+ * @version V4.1.0
+ * @date 29-April-2016
+ * @brief CMSIS Cortex-M3 Device Peripheral Access Layer Header File.
+ * This file contains all the peripheral register's definitions, bits
+ * definitions and memory mapping for STM32F1xx devices.
+ *
+ * This file contains:
+ * - Data structures and the address mapping for all peripherals
+ * - Peripheral's registers declarations and bits definition
+ * - Macros to access peripheral’s registers hardware
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+
+/** @addtogroup CMSIS
+ * @{
+ */
+
+/** @addtogroup stm32f103xb
+ * @{
+ */
+
+#ifndef __STM32F103xB_H
+#define __STM32F103xB_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/** @addtogroup Configuration_section_for_CMSIS
+ * @{
+ */
+/**
+ * @brief Configuration of the Cortex-M3 Processor and Core Peripherals
+ */
+ #define __MPU_PRESENT 0 /*!< Other STM32 devices does not provide an MPU */
+#define __CM3_REV 0x0200 /*!< Core Revision r2p0 */
+#define __NVIC_PRIO_BITS 4 /*!< STM32 uses 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
+
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_interrupt_number_definition
+ * @{
+ */
+
+/**
+ * @brief STM32F10x Interrupt Number Definition, according to the selected device
+ * in @ref Library_configuration_section
+ */
+
+ /*!< Interrupt Number Definition */
+typedef enum
+{
+/****** Cortex-M3 Processor Exceptions Numbers ***************************************************/
+ NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
+ HardFault_IRQn = -13, /*!< 3 Cortex-M3 Hard Fault Interrupt */
+ MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */
+ BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */
+ UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */
+ SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */
+ DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */
+ PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */
+ SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */
+
+/****** STM32 specific Interrupt Numbers *********************************************************/
+ WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
+ PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */
+ TAMPER_IRQn = 2, /*!< Tamper Interrupt */
+ RTC_IRQn = 3, /*!< RTC global Interrupt */
+ FLASH_IRQn = 4, /*!< FLASH global Interrupt */
+ RCC_IRQn = 5, /*!< RCC global Interrupt */
+ EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */
+ EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */
+ EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */
+ EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */
+ EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */
+ DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 global Interrupt */
+ DMA1_Channel2_IRQn = 12, /*!< DMA1 Channel 2 global Interrupt */
+ DMA1_Channel3_IRQn = 13, /*!< DMA1 Channel 3 global Interrupt */
+ DMA1_Channel4_IRQn = 14, /*!< DMA1 Channel 4 global Interrupt */
+ DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 global Interrupt */
+ DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 global Interrupt */
+ DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 global Interrupt */
+ ADC1_2_IRQn = 18, /*!< ADC1 and ADC2 global Interrupt */
+ USB_HP_CAN1_TX_IRQn = 19, /*!< USB Device High Priority or CAN1 TX Interrupts */
+ USB_LP_CAN1_RX0_IRQn = 20, /*!< USB Device Low Priority or CAN1 RX0 Interrupts */
+ CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */
+ CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */
+ EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
+ TIM1_BRK_IRQn = 24, /*!< TIM1 Break Interrupt */
+ TIM1_UP_IRQn = 25, /*!< TIM1 Update Interrupt */
+ TIM1_TRG_COM_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt */
+ TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
+ TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
+ TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
+ TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
+ I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
+ I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
+ I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
+ I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
+ SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
+ SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
+ USART1_IRQn = 37, /*!< USART1 global Interrupt */
+ USART2_IRQn = 38, /*!< USART2 global Interrupt */
+ USART3_IRQn = 39, /*!< USART3 global Interrupt */
+ EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
+ RTC_Alarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */
+ USBWakeUp_IRQn = 42, /*!< USB Device WakeUp from suspend through EXTI Line Interrupt */
+} IRQn_Type;
+
+
+/**
+ * @}
+ */
+
+#include "core_cm3.h"
+#include "system_stm32f1xx.h"
+#include <stdint.h>
+
+/** @addtogroup Peripheral_registers_structures
+ * @{
+ */
+
+/**
+ * @brief Analog to Digital Converter
+ */
+
+typedef struct
+{
+ __IO uint32_t SR;
+ __IO uint32_t CR1;
+ __IO uint32_t CR2;
+ __IO uint32_t SMPR1;
+ __IO uint32_t SMPR2;
+ __IO uint32_t JOFR1;
+ __IO uint32_t JOFR2;
+ __IO uint32_t JOFR3;
+ __IO uint32_t JOFR4;
+ __IO uint32_t HTR;
+ __IO uint32_t LTR;
+ __IO uint32_t SQR1;
+ __IO uint32_t SQR2;
+ __IO uint32_t SQR3;
+ __IO uint32_t JSQR;
+ __IO uint32_t JDR1;
+ __IO uint32_t JDR2;
+ __IO uint32_t JDR3;
+ __IO uint32_t JDR4;
+ __IO uint32_t DR;
+} ADC_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t SR; /*!< ADC status register, used for ADC multimode (bits common to several ADC instances). Address offset: ADC1 base address */
+ __IO uint32_t CR1; /*!< ADC control register 1, used for ADC multimode (bits common to several ADC instances). Address offset: ADC1 base address + 0x04 */
+ __IO uint32_t CR2; /*!< ADC control register 2, used for ADC multimode (bits common to several ADC instances). Address offset: ADC1 base address + 0x08 */
+ uint32_t RESERVED[16];
+ __IO uint32_t DR; /*!< ADC data register, used for ADC multimode (bits common to several ADC instances). Address offset: ADC1 base address + 0x4C */
+} ADC_Common_TypeDef;
+
+/**
+ * @brief Backup Registers
+ */
+
+typedef struct
+{
+ uint32_t RESERVED0;
+ __IO uint32_t DR1;
+ __IO uint32_t DR2;
+ __IO uint32_t DR3;
+ __IO uint32_t DR4;
+ __IO uint32_t DR5;
+ __IO uint32_t DR6;
+ __IO uint32_t DR7;
+ __IO uint32_t DR8;
+ __IO uint32_t DR9;
+ __IO uint32_t DR10;
+ __IO uint32_t RTCCR;
+ __IO uint32_t CR;
+ __IO uint32_t CSR;
+} BKP_TypeDef;
+
+/**
+ * @brief Controller Area Network TxMailBox
+ */
+
+typedef struct
+{
+ __IO uint32_t TIR;
+ __IO uint32_t TDTR;
+ __IO uint32_t TDLR;
+ __IO uint32_t TDHR;
+} CAN_TxMailBox_TypeDef;
+
+/**
+ * @brief Controller Area Network FIFOMailBox
+ */
+
+typedef struct
+{
+ __IO uint32_t RIR;
+ __IO uint32_t RDTR;
+ __IO uint32_t RDLR;
+ __IO uint32_t RDHR;
+} CAN_FIFOMailBox_TypeDef;
+
+/**
+ * @brief Controller Area Network FilterRegister
+ */
+
+typedef struct
+{
+ __IO uint32_t FR1;
+ __IO uint32_t FR2;
+} CAN_FilterRegister_TypeDef;
+
+/**
+ * @brief Controller Area Network
+ */
+
+typedef struct
+{
+ __IO uint32_t MCR;
+ __IO uint32_t MSR;
+ __IO uint32_t TSR;
+ __IO uint32_t RF0R;
+ __IO uint32_t RF1R;
+ __IO uint32_t IER;
+ __IO uint32_t ESR;
+ __IO uint32_t BTR;
+ uint32_t RESERVED0[88];
+ CAN_TxMailBox_TypeDef sTxMailBox[3];
+ CAN_FIFOMailBox_TypeDef sFIFOMailBox[2];
+ uint32_t RESERVED1[12];
+ __IO uint32_t FMR;
+ __IO uint32_t FM1R;
+ uint32_t RESERVED2;
+ __IO uint32_t FS1R;
+ uint32_t RESERVED3;
+ __IO uint32_t FFA1R;
+ uint32_t RESERVED4;
+ __IO uint32_t FA1R;
+ uint32_t RESERVED5[8];
+ CAN_FilterRegister_TypeDef sFilterRegister[14];
+} CAN_TypeDef;
+
+/**
+ * @brief CRC calculation unit
+ */
+
+typedef struct
+{
+ __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
+ __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
+ uint8_t RESERVED0; /*!< Reserved, Address offset: 0x05 */
+ uint16_t RESERVED1; /*!< Reserved, Address offset: 0x06 */
+ __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
+} CRC_TypeDef;
+
+
+/**
+ * @brief Debug MCU
+ */
+
+typedef struct
+{
+ __IO uint32_t IDCODE;
+ __IO uint32_t CR;
+}DBGMCU_TypeDef;
+
+/**
+ * @brief DMA Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t CCR;
+ __IO uint32_t CNDTR;
+ __IO uint32_t CPAR;
+ __IO uint32_t CMAR;
+} DMA_Channel_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t ISR;
+ __IO uint32_t IFCR;
+} DMA_TypeDef;
+
+
+
+/**
+ * @brief External Interrupt/Event Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t IMR;
+ __IO uint32_t EMR;
+ __IO uint32_t RTSR;
+ __IO uint32_t FTSR;
+ __IO uint32_t SWIER;
+ __IO uint32_t PR;
+} EXTI_TypeDef;
+
+/**
+ * @brief FLASH Registers
+ */
+
+typedef struct
+{
+ __IO uint32_t ACR;
+ __IO uint32_t KEYR;
+ __IO uint32_t OPTKEYR;
+ __IO uint32_t SR;
+ __IO uint32_t CR;
+ __IO uint32_t AR;
+ __IO uint32_t RESERVED;
+ __IO uint32_t OBR;
+ __IO uint32_t WRPR;
+} FLASH_TypeDef;
+
+/**
+ * @brief Option Bytes Registers
+ */
+
+typedef struct
+{
+ __IO uint16_t RDP;
+ __IO uint16_t USER;
+ __IO uint16_t Data0;
+ __IO uint16_t Data1;
+ __IO uint16_t WRP0;
+ __IO uint16_t WRP1;
+ __IO uint16_t WRP2;
+ __IO uint16_t WRP3;
+} OB_TypeDef;
+
+/**
+ * @brief General Purpose I/O
+ */
+
+typedef struct
+{
+ __IO uint32_t CRL;
+ __IO uint32_t CRH;
+ __IO uint32_t IDR;
+ __IO uint32_t ODR;
+ __IO uint32_t BSRR;
+ __IO uint32_t BRR;
+ __IO uint32_t LCKR;
+} GPIO_TypeDef;
+
+/**
+ * @brief Alternate Function I/O
+ */
+
+typedef struct
+{
+ __IO uint32_t EVCR;
+ __IO uint32_t MAPR;
+ __IO uint32_t EXTICR[4];
+ uint32_t RESERVED0;
+ __IO uint32_t MAPR2;
+} AFIO_TypeDef;
+/**
+ * @brief Inter Integrated Circuit Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t CR1;
+ __IO uint32_t CR2;
+ __IO uint32_t OAR1;
+ __IO uint32_t OAR2;
+ __IO uint32_t DR;
+ __IO uint32_t SR1;
+ __IO uint32_t SR2;
+ __IO uint32_t CCR;
+ __IO uint32_t TRISE;
+} I2C_TypeDef;
+
+/**
+ * @brief Independent WATCHDOG
+ */
+
+typedef struct
+{
+ __IO uint32_t KR; /*!< Key register, Address offset: 0x00 */
+ __IO uint32_t PR; /*!< Prescaler register, Address offset: 0x04 */
+ __IO uint32_t RLR; /*!< Reload register, Address offset: 0x08 */
+ __IO uint32_t SR; /*!< Status register, Address offset: 0x0C */
+} IWDG_TypeDef;
+
+/**
+ * @brief Power Control
+ */
+
+typedef struct
+{
+ __IO uint32_t CR;
+ __IO uint32_t CSR;
+} PWR_TypeDef;
+
+/**
+ * @brief Reset and Clock Control
+ */
+
+typedef struct
+{
+ __IO uint32_t CR;
+ __IO uint32_t CFGR;
+ __IO uint32_t CIR;
+ __IO uint32_t APB2RSTR;
+ __IO uint32_t APB1RSTR;
+ __IO uint32_t AHBENR;
+ __IO uint32_t APB2ENR;
+ __IO uint32_t APB1ENR;
+ __IO uint32_t BDCR;
+ __IO uint32_t CSR;
+
+
+} RCC_TypeDef;
+
+/**
+ * @brief Real-Time Clock
+ */
+
+typedef struct
+{
+ __IO uint32_t CRH;
+ __IO uint32_t CRL;
+ __IO uint32_t PRLH;
+ __IO uint32_t PRLL;
+ __IO uint32_t DIVH;
+ __IO uint32_t DIVL;
+ __IO uint32_t CNTH;
+ __IO uint32_t CNTL;
+ __IO uint32_t ALRH;
+ __IO uint32_t ALRL;
+} RTC_TypeDef;
+
+/**
+ * @brief SD host Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t POWER;
+ __IO uint32_t CLKCR;
+ __IO uint32_t ARG;
+ __IO uint32_t CMD;
+ __I uint32_t RESPCMD;
+ __I uint32_t RESP1;
+ __I uint32_t RESP2;
+ __I uint32_t RESP3;
+ __I uint32_t RESP4;
+ __IO uint32_t DTIMER;
+ __IO uint32_t DLEN;
+ __IO uint32_t DCTRL;
+ __I uint32_t DCOUNT;
+ __I uint32_t STA;
+ __IO uint32_t ICR;
+ __IO uint32_t MASK;
+ uint32_t RESERVED0[2];
+ __I uint32_t FIFOCNT;
+ uint32_t RESERVED1[13];
+ __IO uint32_t FIFO;
+} SDIO_TypeDef;
+
+/**
+ * @brief Serial Peripheral Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t CR1;
+ __IO uint32_t CR2;
+ __IO uint32_t SR;
+ __IO uint32_t DR;
+ __IO uint32_t CRCPR;
+ __IO uint32_t RXCRCR;
+ __IO uint32_t TXCRCR;
+ __IO uint32_t I2SCFGR;
+} SPI_TypeDef;
+
+/**
+ * @brief TIM Timers
+ */
+typedef struct
+{
+ __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
+ __IO uint32_t SMCR; /*!< TIM slave Mode Control register, Address offset: 0x08 */
+ __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
+ __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
+ __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
+ __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
+ __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
+ __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
+ __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
+ __IO uint32_t PSC; /*!< TIM prescaler register, Address offset: 0x28 */
+ __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
+ __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */
+ __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
+ __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
+ __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
+ __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
+ __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
+ __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
+ __IO uint32_t DMAR; /*!< TIM DMA address for full transfer register, Address offset: 0x4C */
+ __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */
+}TIM_TypeDef;
+
+
+/**
+ * @brief Universal Synchronous Asynchronous Receiver Transmitter
+ */
+
+typedef struct
+{
+ __IO uint32_t SR; /*!< USART Status register, Address offset: 0x00 */
+ __IO uint32_t DR; /*!< USART Data register, Address offset: 0x04 */
+ __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x08 */
+ __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x0C */
+ __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x10 */
+ __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x14 */
+ __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x18 */
+} USART_TypeDef;
+
+/**
+ * @brief Universal Serial Bus Full Speed Device
+ */
+
+typedef struct
+{
+ __IO uint16_t EP0R; /*!< USB Endpoint 0 register, Address offset: 0x00 */
+ __IO uint16_t RESERVED0; /*!< Reserved */
+ __IO uint16_t EP1R; /*!< USB Endpoint 1 register, Address offset: 0x04 */
+ __IO uint16_t RESERVED1; /*!< Reserved */
+ __IO uint16_t EP2R; /*!< USB Endpoint 2 register, Address offset: 0x08 */
+ __IO uint16_t RESERVED2; /*!< Reserved */
+ __IO uint16_t EP3R; /*!< USB Endpoint 3 register, Address offset: 0x0C */
+ __IO uint16_t RESERVED3; /*!< Reserved */
+ __IO uint16_t EP4R; /*!< USB Endpoint 4 register, Address offset: 0x10 */
+ __IO uint16_t RESERVED4; /*!< Reserved */
+ __IO uint16_t EP5R; /*!< USB Endpoint 5 register, Address offset: 0x14 */
+ __IO uint16_t RESERVED5; /*!< Reserved */
+ __IO uint16_t EP6R; /*!< USB Endpoint 6 register, Address offset: 0x18 */
+ __IO uint16_t RESERVED6; /*!< Reserved */
+ __IO uint16_t EP7R; /*!< USB Endpoint 7 register, Address offset: 0x1C */
+ __IO uint16_t RESERVED7[17]; /*!< Reserved */
+ __IO uint16_t CNTR; /*!< Control register, Address offset: 0x40 */
+ __IO uint16_t RESERVED8; /*!< Reserved */
+ __IO uint16_t ISTR; /*!< Interrupt status register, Address offset: 0x44 */
+ __IO uint16_t RESERVED9; /*!< Reserved */
+ __IO uint16_t FNR; /*!< Frame number register, Address offset: 0x48 */
+ __IO uint16_t RESERVEDA; /*!< Reserved */
+ __IO uint16_t DADDR; /*!< Device address register, Address offset: 0x4C */
+ __IO uint16_t RESERVEDB; /*!< Reserved */
+ __IO uint16_t BTABLE; /*!< Buffer Table address register, Address offset: 0x50 */
+ __IO uint16_t RESERVEDC; /*!< Reserved */
+} USB_TypeDef;
+
+
+/**
+ * @brief Window WATCHDOG
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
+ __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
+ __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
+} WWDG_TypeDef;
+
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_memory_map
+ * @{
+ */
+
+
+#define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH base address in the alias region */
+#define FLASH_BANK1_END ((uint32_t)0x0801FFFF) /*!< FLASH END address of bank1 */
+#define SRAM_BASE ((uint32_t)0x20000000) /*!< SRAM base address in the alias region */
+#define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */
+
+#define SRAM_BB_BASE ((uint32_t)0x22000000) /*!< SRAM base address in the bit-band region */
+#define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */
+
+
+/*!< Peripheral memory map */
+#define APB1PERIPH_BASE PERIPH_BASE
+#define APB2PERIPH_BASE (PERIPH_BASE + 0x10000)
+#define AHBPERIPH_BASE (PERIPH_BASE + 0x20000)
+
+#define TIM2_BASE (APB1PERIPH_BASE + 0x0000)
+#define TIM3_BASE (APB1PERIPH_BASE + 0x0400)
+#define TIM4_BASE (APB1PERIPH_BASE + 0x0800)
+#define RTC_BASE (APB1PERIPH_BASE + 0x2800)
+#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00)
+#define IWDG_BASE (APB1PERIPH_BASE + 0x3000)
+#define SPI2_BASE (APB1PERIPH_BASE + 0x3800)
+#define USART2_BASE (APB1PERIPH_BASE + 0x4400)
+#define USART3_BASE (APB1PERIPH_BASE + 0x4800)
+#define I2C1_BASE (APB1PERIPH_BASE + 0x5400)
+#define I2C2_BASE (APB1PERIPH_BASE + 0x5800)
+#define CAN1_BASE (APB1PERIPH_BASE + 0x6400)
+#define BKP_BASE (APB1PERIPH_BASE + 0x6C00)
+#define PWR_BASE (APB1PERIPH_BASE + 0x7000)
+#define AFIO_BASE (APB2PERIPH_BASE + 0x0000)
+#define EXTI_BASE (APB2PERIPH_BASE + 0x0400)
+#define GPIOA_BASE (APB2PERIPH_BASE + 0x0800)
+#define GPIOB_BASE (APB2PERIPH_BASE + 0x0C00)
+#define GPIOC_BASE (APB2PERIPH_BASE + 0x1000)
+#define GPIOD_BASE (APB2PERIPH_BASE + 0x1400)
+#define GPIOE_BASE (APB2PERIPH_BASE + 0x1800)
+#define ADC1_BASE (APB2PERIPH_BASE + 0x2400)
+#define ADC2_BASE (APB2PERIPH_BASE + 0x2800)
+#define TIM1_BASE (APB2PERIPH_BASE + 0x2C00)
+#define SPI1_BASE (APB2PERIPH_BASE + 0x3000)
+#define USART1_BASE (APB2PERIPH_BASE + 0x3800)
+
+#define SDIO_BASE (PERIPH_BASE + 0x18000)
+
+#define DMA1_BASE (AHBPERIPH_BASE + 0x0000)
+#define DMA1_Channel1_BASE (AHBPERIPH_BASE + 0x0008)
+#define DMA1_Channel2_BASE (AHBPERIPH_BASE + 0x001C)
+#define DMA1_Channel3_BASE (AHBPERIPH_BASE + 0x0030)
+#define DMA1_Channel4_BASE (AHBPERIPH_BASE + 0x0044)
+#define DMA1_Channel5_BASE (AHBPERIPH_BASE + 0x0058)
+#define DMA1_Channel6_BASE (AHBPERIPH_BASE + 0x006C)
+#define DMA1_Channel7_BASE (AHBPERIPH_BASE + 0x0080)
+#define RCC_BASE (AHBPERIPH_BASE + 0x1000)
+#define CRC_BASE (AHBPERIPH_BASE + 0x3000)
+
+#define FLASH_R_BASE (AHBPERIPH_BASE + 0x2000) /*!< Flash registers base address */
+#define FLASHSIZE_BASE ((uint32_t)0x1FFFF7E0) /*!< FLASH Size register base address */
+#define UID_BASE ((uint32_t)0x1FFFF7E8) /*!< Unique device ID register base address */
+#define OB_BASE ((uint32_t)0x1FFFF800) /*!< Flash Option Bytes base address */
+
+
+
+#define DBGMCU_BASE ((uint32_t)0xE0042000) /*!< Debug MCU registers base address */
+
+/* USB device FS */
+#define USB_BASE (APB1PERIPH_BASE + 0x00005C00) /*!< USB_IP Peripheral Registers base address */
+#define USB_PMAADDR (APB1PERIPH_BASE + 0x00006000) /*!< USB_IP Packet Memory Area base address */
+
+
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_declaration
+ * @{
+ */
+
+#define TIM2 ((TIM_TypeDef *) TIM2_BASE)
+#define TIM3 ((TIM_TypeDef *) TIM3_BASE)
+#define TIM4 ((TIM_TypeDef *) TIM4_BASE)
+#define RTC ((RTC_TypeDef *) RTC_BASE)
+#define WWDG ((WWDG_TypeDef *) WWDG_BASE)
+#define IWDG ((IWDG_TypeDef *) IWDG_BASE)
+#define SPI2 ((SPI_TypeDef *) SPI2_BASE)
+#define USART2 ((USART_TypeDef *) USART2_BASE)
+#define USART3 ((USART_TypeDef *) USART3_BASE)
+#define I2C1 ((I2C_TypeDef *) I2C1_BASE)
+#define I2C2 ((I2C_TypeDef *) I2C2_BASE)
+#define USB ((USB_TypeDef *) USB_BASE)
+#define CAN1 ((CAN_TypeDef *) CAN1_BASE)
+#define BKP ((BKP_TypeDef *) BKP_BASE)
+#define PWR ((PWR_TypeDef *) PWR_BASE)
+#define AFIO ((AFIO_TypeDef *) AFIO_BASE)
+#define EXTI ((EXTI_TypeDef *) EXTI_BASE)
+#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
+#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
+#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
+#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
+#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
+#define ADC1 ((ADC_TypeDef *) ADC1_BASE)
+#define ADC2 ((ADC_TypeDef *) ADC2_BASE)
+#define ADC12_COMMON ((ADC_Common_TypeDef *) ADC1_BASE)
+#define TIM1 ((TIM_TypeDef *) TIM1_BASE)
+#define SPI1 ((SPI_TypeDef *) SPI1_BASE)
+#define USART1 ((USART_TypeDef *) USART1_BASE)
+#define SDIO ((SDIO_TypeDef *) SDIO_BASE)
+#define DMA1 ((DMA_TypeDef *) DMA1_BASE)
+#define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
+#define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
+#define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
+#define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
+#define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
+#define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
+#define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
+#define RCC ((RCC_TypeDef *) RCC_BASE)
+#define CRC ((CRC_TypeDef *) CRC_BASE)
+#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
+#define OB ((OB_TypeDef *) OB_BASE)
+#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
+
+
+/**
+ * @}
+ */
+
+/** @addtogroup Exported_constants
+ * @{
+ */
+
+ /** @addtogroup Peripheral_Registers_Bits_Definition
+ * @{
+ */
+
+/******************************************************************************/
+/* Peripheral Registers_Bits_Definition */
+/******************************************************************************/
+
+/******************************************************************************/
+/* */
+/* CRC calculation unit (CRC) */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for CRC_DR register *********************/
+#define CRC_DR_DR_Pos (0U)
+#define CRC_DR_DR_Msk (0xFFFFFFFFU << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */
+#define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */
+
+/******************* Bit definition for CRC_IDR register ********************/
+#define CRC_IDR_IDR_Pos (0U)
+#define CRC_IDR_IDR_Msk (0xFFU << CRC_IDR_IDR_Pos) /*!< 0x000000FF */
+#define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 8-bit data register bits */
+
+/******************** Bit definition for CRC_CR register ********************/
+#define CRC_CR_RESET_Pos (0U)
+#define CRC_CR_RESET_Msk (0x1U << CRC_CR_RESET_Pos) /*!< 0x00000001 */
+#define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET bit */
+
+/******************************************************************************/
+/* */
+/* Power Control */
+/* */
+/******************************************************************************/
+
+/******************** Bit definition for PWR_CR register ********************/
+#define PWR_CR_LPDS_Pos (0U)
+#define PWR_CR_LPDS_Msk (0x1U << PWR_CR_LPDS_Pos) /*!< 0x00000001 */
+#define PWR_CR_LPDS PWR_CR_LPDS_Msk /*!< Low-Power Deepsleep */
+#define PWR_CR_PDDS_Pos (1U)
+#define PWR_CR_PDDS_Msk (0x1U << PWR_CR_PDDS_Pos) /*!< 0x00000002 */
+#define PWR_CR_PDDS PWR_CR_PDDS_Msk /*!< Power Down Deepsleep */
+#define PWR_CR_CWUF_Pos (2U)
+#define PWR_CR_CWUF_Msk (0x1U << PWR_CR_CWUF_Pos) /*!< 0x00000004 */
+#define PWR_CR_CWUF PWR_CR_CWUF_Msk /*!< Clear Wakeup Flag */
+#define PWR_CR_CSBF_Pos (3U)
+#define PWR_CR_CSBF_Msk (0x1U << PWR_CR_CSBF_Pos) /*!< 0x00000008 */
+#define PWR_CR_CSBF PWR_CR_CSBF_Msk /*!< Clear Standby Flag */
+#define PWR_CR_PVDE_Pos (4U)
+#define PWR_CR_PVDE_Msk (0x1U << PWR_CR_PVDE_Pos) /*!< 0x00000010 */
+#define PWR_CR_PVDE PWR_CR_PVDE_Msk /*!< Power Voltage Detector Enable */
+
+#define PWR_CR_PLS_Pos (5U)
+#define PWR_CR_PLS_Msk (0x7U << PWR_CR_PLS_Pos) /*!< 0x000000E0 */
+#define PWR_CR_PLS PWR_CR_PLS_Msk /*!< PLS[2:0] bits (PVD Level Selection) */
+#define PWR_CR_PLS_0 (0x1U << PWR_CR_PLS_Pos) /*!< 0x00000020 */
+#define PWR_CR_PLS_1 (0x2U << PWR_CR_PLS_Pos) /*!< 0x00000040 */
+#define PWR_CR_PLS_2 (0x4U << PWR_CR_PLS_Pos) /*!< 0x00000080 */
+
+/*!< PVD level configuration */
+#define PWR_CR_PLS_2V2 ((uint32_t)0x00000000) /*!< PVD level 2.2V */
+#define PWR_CR_PLS_2V3 ((uint32_t)0x00000020) /*!< PVD level 2.3V */
+#define PWR_CR_PLS_2V4 ((uint32_t)0x00000040) /*!< PVD level 2.4V */
+#define PWR_CR_PLS_2V5 ((uint32_t)0x00000060) /*!< PVD level 2.5V */
+#define PWR_CR_PLS_2V6 ((uint32_t)0x00000080) /*!< PVD level 2.6V */
+#define PWR_CR_PLS_2V7 ((uint32_t)0x000000A0) /*!< PVD level 2.7V */
+#define PWR_CR_PLS_2V8 ((uint32_t)0x000000C0) /*!< PVD level 2.8V */
+#define PWR_CR_PLS_2V9 ((uint32_t)0x000000E0) /*!< PVD level 2.9V */
+
+#define PWR_CR_DBP_Pos (8U)
+#define PWR_CR_DBP_Msk (0x1U << PWR_CR_DBP_Pos) /*!< 0x00000100 */
+#define PWR_CR_DBP PWR_CR_DBP_Msk /*!< Disable Backup Domain write protection */
+
+
+/******************* Bit definition for PWR_CSR register ********************/
+#define PWR_CSR_WUF_Pos (0U)
+#define PWR_CSR_WUF_Msk (0x1U << PWR_CSR_WUF_Pos) /*!< 0x00000001 */
+#define PWR_CSR_WUF PWR_CSR_WUF_Msk /*!< Wakeup Flag */
+#define PWR_CSR_SBF_Pos (1U)
+#define PWR_CSR_SBF_Msk (0x1U << PWR_CSR_SBF_Pos) /*!< 0x00000002 */
+#define PWR_CSR_SBF PWR_CSR_SBF_Msk /*!< Standby Flag */
+#define PWR_CSR_PVDO_Pos (2U)
+#define PWR_CSR_PVDO_Msk (0x1U << PWR_CSR_PVDO_Pos) /*!< 0x00000004 */
+#define PWR_CSR_PVDO PWR_CSR_PVDO_Msk /*!< PVD Output */
+#define PWR_CSR_EWUP_Pos (8U)
+#define PWR_CSR_EWUP_Msk (0x1U << PWR_CSR_EWUP_Pos) /*!< 0x00000100 */
+#define PWR_CSR_EWUP PWR_CSR_EWUP_Msk /*!< Enable WKUP pin */
+
+/******************************************************************************/
+/* */
+/* Backup registers */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for BKP_DR1 register ********************/
+#define BKP_DR1_D_Pos (0U)
+#define BKP_DR1_D_Msk (0xFFFFU << BKP_DR1_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR1_D BKP_DR1_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR2 register ********************/
+#define BKP_DR2_D_Pos (0U)
+#define BKP_DR2_D_Msk (0xFFFFU << BKP_DR2_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR2_D BKP_DR2_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR3 register ********************/
+#define BKP_DR3_D_Pos (0U)
+#define BKP_DR3_D_Msk (0xFFFFU << BKP_DR3_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR3_D BKP_DR3_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR4 register ********************/
+#define BKP_DR4_D_Pos (0U)
+#define BKP_DR4_D_Msk (0xFFFFU << BKP_DR4_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR4_D BKP_DR4_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR5 register ********************/
+#define BKP_DR5_D_Pos (0U)
+#define BKP_DR5_D_Msk (0xFFFFU << BKP_DR5_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR5_D BKP_DR5_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR6 register ********************/
+#define BKP_DR6_D_Pos (0U)
+#define BKP_DR6_D_Msk (0xFFFFU << BKP_DR6_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR6_D BKP_DR6_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR7 register ********************/
+#define BKP_DR7_D_Pos (0U)
+#define BKP_DR7_D_Msk (0xFFFFU << BKP_DR7_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR7_D BKP_DR7_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR8 register ********************/
+#define BKP_DR8_D_Pos (0U)
+#define BKP_DR8_D_Msk (0xFFFFU << BKP_DR8_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR8_D BKP_DR8_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR9 register ********************/
+#define BKP_DR9_D_Pos (0U)
+#define BKP_DR9_D_Msk (0xFFFFU << BKP_DR9_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR9_D BKP_DR9_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR10 register *******************/
+#define BKP_DR10_D_Pos (0U)
+#define BKP_DR10_D_Msk (0xFFFFU << BKP_DR10_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR10_D BKP_DR10_D_Msk /*!< Backup data */
+
+#define RTC_BKP_NUMBER 10
+
+/****************** Bit definition for BKP_RTCCR register *******************/
+#define BKP_RTCCR_CAL_Pos (0U)
+#define BKP_RTCCR_CAL_Msk (0x7FU << BKP_RTCCR_CAL_Pos) /*!< 0x0000007F */
+#define BKP_RTCCR_CAL BKP_RTCCR_CAL_Msk /*!< Calibration value */
+#define BKP_RTCCR_CCO_Pos (7U)
+#define BKP_RTCCR_CCO_Msk (0x1U << BKP_RTCCR_CCO_Pos) /*!< 0x00000080 */
+#define BKP_RTCCR_CCO BKP_RTCCR_CCO_Msk /*!< Calibration Clock Output */
+#define BKP_RTCCR_ASOE_Pos (8U)
+#define BKP_RTCCR_ASOE_Msk (0x1U << BKP_RTCCR_ASOE_Pos) /*!< 0x00000100 */
+#define BKP_RTCCR_ASOE BKP_RTCCR_ASOE_Msk /*!< Alarm or Second Output Enable */
+#define BKP_RTCCR_ASOS_Pos (9U)
+#define BKP_RTCCR_ASOS_Msk (0x1U << BKP_RTCCR_ASOS_Pos) /*!< 0x00000200 */
+#define BKP_RTCCR_ASOS BKP_RTCCR_ASOS_Msk /*!< Alarm or Second Output Selection */
+
+/******************** Bit definition for BKP_CR register ********************/
+#define BKP_CR_TPE_Pos (0U)
+#define BKP_CR_TPE_Msk (0x1U << BKP_CR_TPE_Pos) /*!< 0x00000001 */
+#define BKP_CR_TPE BKP_CR_TPE_Msk /*!< TAMPER pin enable */
+#define BKP_CR_TPAL_Pos (1U)
+#define BKP_CR_TPAL_Msk (0x1U << BKP_CR_TPAL_Pos) /*!< 0x00000002 */
+#define BKP_CR_TPAL BKP_CR_TPAL_Msk /*!< TAMPER pin active level */
+
+/******************* Bit definition for BKP_CSR register ********************/
+#define BKP_CSR_CTE_Pos (0U)
+#define BKP_CSR_CTE_Msk (0x1U << BKP_CSR_CTE_Pos) /*!< 0x00000001 */
+#define BKP_CSR_CTE BKP_CSR_CTE_Msk /*!< Clear Tamper event */
+#define BKP_CSR_CTI_Pos (1U)
+#define BKP_CSR_CTI_Msk (0x1U << BKP_CSR_CTI_Pos) /*!< 0x00000002 */
+#define BKP_CSR_CTI BKP_CSR_CTI_Msk /*!< Clear Tamper Interrupt */
+#define BKP_CSR_TPIE_Pos (2U)
+#define BKP_CSR_TPIE_Msk (0x1U << BKP_CSR_TPIE_Pos) /*!< 0x00000004 */
+#define BKP_CSR_TPIE BKP_CSR_TPIE_Msk /*!< TAMPER Pin interrupt enable */
+#define BKP_CSR_TEF_Pos (8U)
+#define BKP_CSR_TEF_Msk (0x1U << BKP_CSR_TEF_Pos) /*!< 0x00000100 */
+#define BKP_CSR_TEF BKP_CSR_TEF_Msk /*!< Tamper Event Flag */
+#define BKP_CSR_TIF_Pos (9U)
+#define BKP_CSR_TIF_Msk (0x1U << BKP_CSR_TIF_Pos) /*!< 0x00000200 */
+#define BKP_CSR_TIF BKP_CSR_TIF_Msk /*!< Tamper Interrupt Flag */
+
+/******************************************************************************/
+/* */
+/* Reset and Clock Control */
+/* */
+/******************************************************************************/
+
+/******************** Bit definition for RCC_CR register ********************/
+#define RCC_CR_HSION_Pos (0U)
+#define RCC_CR_HSION_Msk (0x1U << RCC_CR_HSION_Pos) /*!< 0x00000001 */
+#define RCC_CR_HSION RCC_CR_HSION_Msk /*!< Internal High Speed clock enable */
+#define RCC_CR_HSIRDY_Pos (1U)
+#define RCC_CR_HSIRDY_Msk (0x1U << RCC_CR_HSIRDY_Pos) /*!< 0x00000002 */
+#define RCC_CR_HSIRDY RCC_CR_HSIRDY_Msk /*!< Internal High Speed clock ready flag */
+#define RCC_CR_HSITRIM_Pos (3U)
+#define RCC_CR_HSITRIM_Msk (0x1FU << RCC_CR_HSITRIM_Pos) /*!< 0x000000F8 */
+#define RCC_CR_HSITRIM RCC_CR_HSITRIM_Msk /*!< Internal High Speed clock trimming */
+#define RCC_CR_HSICAL_Pos (8U)
+#define RCC_CR_HSICAL_Msk (0xFFU << RCC_CR_HSICAL_Pos) /*!< 0x0000FF00 */
+#define RCC_CR_HSICAL RCC_CR_HSICAL_Msk /*!< Internal High Speed clock Calibration */
+#define RCC_CR_HSEON_Pos (16U)
+#define RCC_CR_HSEON_Msk (0x1U << RCC_CR_HSEON_Pos) /*!< 0x00010000 */
+#define RCC_CR_HSEON RCC_CR_HSEON_Msk /*!< External High Speed clock enable */
+#define RCC_CR_HSERDY_Pos (17U)
+#define RCC_CR_HSERDY_Msk (0x1U << RCC_CR_HSERDY_Pos) /*!< 0x00020000 */
+#define RCC_CR_HSERDY RCC_CR_HSERDY_Msk /*!< External High Speed clock ready flag */
+#define RCC_CR_HSEBYP_Pos (18U)
+#define RCC_CR_HSEBYP_Msk (0x1U << RCC_CR_HSEBYP_Pos) /*!< 0x00040000 */
+#define RCC_CR_HSEBYP RCC_CR_HSEBYP_Msk /*!< External High Speed clock Bypass */
+#define RCC_CR_CSSON_Pos (19U)
+#define RCC_CR_CSSON_Msk (0x1U << RCC_CR_CSSON_Pos) /*!< 0x00080000 */
+#define RCC_CR_CSSON RCC_CR_CSSON_Msk /*!< Clock Security System enable */
+#define RCC_CR_PLLON_Pos (24U)
+#define RCC_CR_PLLON_Msk (0x1U << RCC_CR_PLLON_Pos) /*!< 0x01000000 */
+#define RCC_CR_PLLON RCC_CR_PLLON_Msk /*!< PLL enable */
+#define RCC_CR_PLLRDY_Pos (25U)
+#define RCC_CR_PLLRDY_Msk (0x1U << RCC_CR_PLLRDY_Pos) /*!< 0x02000000 */
+#define RCC_CR_PLLRDY RCC_CR_PLLRDY_Msk /*!< PLL clock ready flag */
+
+
+/******************* Bit definition for RCC_CFGR register *******************/
+/*!< SW configuration */
+#define RCC_CFGR_SW_Pos (0U)
+#define RCC_CFGR_SW_Msk (0x3U << RCC_CFGR_SW_Pos) /*!< 0x00000003 */
+#define RCC_CFGR_SW RCC_CFGR_SW_Msk /*!< SW[1:0] bits (System clock Switch) */
+#define RCC_CFGR_SW_0 (0x1U << RCC_CFGR_SW_Pos) /*!< 0x00000001 */
+#define RCC_CFGR_SW_1 (0x2U << RCC_CFGR_SW_Pos) /*!< 0x00000002 */
+
+#define RCC_CFGR_SW_HSI ((uint32_t)0x00000000) /*!< HSI selected as system clock */
+#define RCC_CFGR_SW_HSE ((uint32_t)0x00000001) /*!< HSE selected as system clock */
+#define RCC_CFGR_SW_PLL ((uint32_t)0x00000002) /*!< PLL selected as system clock */
+
+/*!< SWS configuration */
+#define RCC_CFGR_SWS_Pos (2U)
+#define RCC_CFGR_SWS_Msk (0x3U << RCC_CFGR_SWS_Pos) /*!< 0x0000000C */
+#define RCC_CFGR_SWS RCC_CFGR_SWS_Msk /*!< SWS[1:0] bits (System Clock Switch Status) */
+#define RCC_CFGR_SWS_0 (0x1U << RCC_CFGR_SWS_Pos) /*!< 0x00000004 */
+#define RCC_CFGR_SWS_1 (0x2U << RCC_CFGR_SWS_Pos) /*!< 0x00000008 */
+
+#define RCC_CFGR_SWS_HSI ((uint32_t)0x00000000) /*!< HSI oscillator used as system clock */
+#define RCC_CFGR_SWS_HSE ((uint32_t)0x00000004) /*!< HSE oscillator used as system clock */
+#define RCC_CFGR_SWS_PLL ((uint32_t)0x00000008) /*!< PLL used as system clock */
+
+/*!< HPRE configuration */
+#define RCC_CFGR_HPRE_Pos (4U)
+#define RCC_CFGR_HPRE_Msk (0xFU << RCC_CFGR_HPRE_Pos) /*!< 0x000000F0 */
+#define RCC_CFGR_HPRE RCC_CFGR_HPRE_Msk /*!< HPRE[3:0] bits (AHB prescaler) */
+#define RCC_CFGR_HPRE_0 (0x1U << RCC_CFGR_HPRE_Pos) /*!< 0x00000010 */
+#define RCC_CFGR_HPRE_1 (0x2U << RCC_CFGR_HPRE_Pos) /*!< 0x00000020 */
+#define RCC_CFGR_HPRE_2 (0x4U << RCC_CFGR_HPRE_Pos) /*!< 0x00000040 */
+#define RCC_CFGR_HPRE_3 (0x8U << RCC_CFGR_HPRE_Pos) /*!< 0x00000080 */
+
+#define RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000) /*!< SYSCLK not divided */
+#define RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080) /*!< SYSCLK divided by 2 */
+#define RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090) /*!< SYSCLK divided by 4 */
+#define RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0) /*!< SYSCLK divided by 8 */
+#define RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0) /*!< SYSCLK divided by 16 */
+#define RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0) /*!< SYSCLK divided by 64 */
+#define RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0) /*!< SYSCLK divided by 128 */
+#define RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0) /*!< SYSCLK divided by 256 */
+#define RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0) /*!< SYSCLK divided by 512 */
+
+/*!< PPRE1 configuration */
+#define RCC_CFGR_PPRE1_Pos (8U)
+#define RCC_CFGR_PPRE1_Msk (0x7U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000700 */
+#define RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_Msk /*!< PRE1[2:0] bits (APB1 prescaler) */
+#define RCC_CFGR_PPRE1_0 (0x1U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000100 */
+#define RCC_CFGR_PPRE1_1 (0x2U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000200 */
+#define RCC_CFGR_PPRE1_2 (0x4U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000400 */
+
+#define RCC_CFGR_PPRE1_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */
+#define RCC_CFGR_PPRE1_DIV2 ((uint32_t)0x00000400) /*!< HCLK divided by 2 */
+#define RCC_CFGR_PPRE1_DIV4 ((uint32_t)0x00000500) /*!< HCLK divided by 4 */
+#define RCC_CFGR_PPRE1_DIV8 ((uint32_t)0x00000600) /*!< HCLK divided by 8 */
+#define RCC_CFGR_PPRE1_DIV16 ((uint32_t)0x00000700) /*!< HCLK divided by 16 */
+
+/*!< PPRE2 configuration */
+#define RCC_CFGR_PPRE2_Pos (11U)
+#define RCC_CFGR_PPRE2_Msk (0x7U << RCC_CFGR_PPRE2_Pos) /*!< 0x00003800 */
+#define RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_Msk /*!< PRE2[2:0] bits (APB2 prescaler) */
+#define RCC_CFGR_PPRE2_0 (0x1U << RCC_CFGR_PPRE2_Pos) /*!< 0x00000800 */
+#define RCC_CFGR_PPRE2_1 (0x2U << RCC_CFGR_PPRE2_Pos) /*!< 0x00001000 */
+#define RCC_CFGR_PPRE2_2 (0x4U << RCC_CFGR_PPRE2_Pos) /*!< 0x00002000 */
+
+#define RCC_CFGR_PPRE2_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */
+#define RCC_CFGR_PPRE2_DIV2 ((uint32_t)0x00002000) /*!< HCLK divided by 2 */
+#define RCC_CFGR_PPRE2_DIV4 ((uint32_t)0x00002800) /*!< HCLK divided by 4 */
+#define RCC_CFGR_PPRE2_DIV8 ((uint32_t)0x00003000) /*!< HCLK divided by 8 */
+#define RCC_CFGR_PPRE2_DIV16 ((uint32_t)0x00003800) /*!< HCLK divided by 16 */
+
+/*!< ADCPPRE configuration */
+#define RCC_CFGR_ADCPRE_Pos (14U)
+#define RCC_CFGR_ADCPRE_Msk (0x3U << RCC_CFGR_ADCPRE_Pos) /*!< 0x0000C000 */
+#define RCC_CFGR_ADCPRE RCC_CFGR_ADCPRE_Msk /*!< ADCPRE[1:0] bits (ADC prescaler) */
+#define RCC_CFGR_ADCPRE_0 (0x1U << RCC_CFGR_ADCPRE_Pos) /*!< 0x00004000 */
+#define RCC_CFGR_ADCPRE_1 (0x2U << RCC_CFGR_ADCPRE_Pos) /*!< 0x00008000 */
+
+#define RCC_CFGR_ADCPRE_DIV2 ((uint32_t)0x00000000) /*!< PCLK2 divided by 2 */
+#define RCC_CFGR_ADCPRE_DIV4 ((uint32_t)0x00004000) /*!< PCLK2 divided by 4 */
+#define RCC_CFGR_ADCPRE_DIV6 ((uint32_t)0x00008000) /*!< PCLK2 divided by 6 */
+#define RCC_CFGR_ADCPRE_DIV8 ((uint32_t)0x0000C000) /*!< PCLK2 divided by 8 */
+
+#define RCC_CFGR_PLLSRC_Pos (16U)
+#define RCC_CFGR_PLLSRC_Msk (0x1U << RCC_CFGR_PLLSRC_Pos) /*!< 0x00010000 */
+#define RCC_CFGR_PLLSRC RCC_CFGR_PLLSRC_Msk /*!< PLL entry clock source */
+
+#define RCC_CFGR_PLLXTPRE_Pos (17U)
+#define RCC_CFGR_PLLXTPRE_Msk (0x1U << RCC_CFGR_PLLXTPRE_Pos) /*!< 0x00020000 */
+#define RCC_CFGR_PLLXTPRE RCC_CFGR_PLLXTPRE_Msk /*!< HSE divider for PLL entry */
+
+/*!< PLLMUL configuration */
+#define RCC_CFGR_PLLMULL_Pos (18U)
+#define RCC_CFGR_PLLMULL_Msk (0xFU << RCC_CFGR_PLLMULL_Pos) /*!< 0x003C0000 */
+#define RCC_CFGR_PLLMULL RCC_CFGR_PLLMULL_Msk /*!< PLLMUL[3:0] bits (PLL multiplication factor) */
+#define RCC_CFGR_PLLMULL_0 (0x1U << RCC_CFGR_PLLMULL_Pos) /*!< 0x00040000 */
+#define RCC_CFGR_PLLMULL_1 (0x2U << RCC_CFGR_PLLMULL_Pos) /*!< 0x00080000 */
+#define RCC_CFGR_PLLMULL_2 (0x4U << RCC_CFGR_PLLMULL_Pos) /*!< 0x00100000 */
+#define RCC_CFGR_PLLMULL_3 (0x8U << RCC_CFGR_PLLMULL_Pos) /*!< 0x00200000 */
+
+#define RCC_CFGR_PLLXTPRE_HSE ((uint32_t)0x00000000) /*!< HSE clock not divided for PLL entry */
+#define RCC_CFGR_PLLXTPRE_HSE_DIV2 ((uint32_t)0x00020000) /*!< HSE clock divided by 2 for PLL entry */
+
+#define RCC_CFGR_PLLMULL2 ((uint32_t)0x00000000) /*!< PLL input clock*2 */
+#define RCC_CFGR_PLLMULL3_Pos (18U)
+#define RCC_CFGR_PLLMULL3_Msk (0x1U << RCC_CFGR_PLLMULL3_Pos) /*!< 0x00040000 */
+#define RCC_CFGR_PLLMULL3 RCC_CFGR_PLLMULL3_Msk /*!< PLL input clock*3 */
+#define RCC_CFGR_PLLMULL4_Pos (19U)
+#define RCC_CFGR_PLLMULL4_Msk (0x1U << RCC_CFGR_PLLMULL4_Pos) /*!< 0x00080000 */
+#define RCC_CFGR_PLLMULL4 RCC_CFGR_PLLMULL4_Msk /*!< PLL input clock*4 */
+#define RCC_CFGR_PLLMULL5_Pos (18U)
+#define RCC_CFGR_PLLMULL5_Msk (0x3U << RCC_CFGR_PLLMULL5_Pos) /*!< 0x000C0000 */
+#define RCC_CFGR_PLLMULL5 RCC_CFGR_PLLMULL5_Msk /*!< PLL input clock*5 */
+#define RCC_CFGR_PLLMULL6_Pos (20U)
+#define RCC_CFGR_PLLMULL6_Msk (0x1U << RCC_CFGR_PLLMULL6_Pos) /*!< 0x00100000 */
+#define RCC_CFGR_PLLMULL6 RCC_CFGR_PLLMULL6_Msk /*!< PLL input clock*6 */
+#define RCC_CFGR_PLLMULL7_Pos (18U)
+#define RCC_CFGR_PLLMULL7_Msk (0x5U << RCC_CFGR_PLLMULL7_Pos) /*!< 0x00140000 */
+#define RCC_CFGR_PLLMULL7 RCC_CFGR_PLLMULL7_Msk /*!< PLL input clock*7 */
+#define RCC_CFGR_PLLMULL8_Pos (19U)
+#define RCC_CFGR_PLLMULL8_Msk (0x3U << RCC_CFGR_PLLMULL8_Pos) /*!< 0x00180000 */
+#define RCC_CFGR_PLLMULL8 RCC_CFGR_PLLMULL8_Msk /*!< PLL input clock*8 */
+#define RCC_CFGR_PLLMULL9_Pos (18U)
+#define RCC_CFGR_PLLMULL9_Msk (0x7U << RCC_CFGR_PLLMULL9_Pos) /*!< 0x001C0000 */
+#define RCC_CFGR_PLLMULL9 RCC_CFGR_PLLMULL9_Msk /*!< PLL input clock*9 */
+#define RCC_CFGR_PLLMULL10_Pos (21U)
+#define RCC_CFGR_PLLMULL10_Msk (0x1U << RCC_CFGR_PLLMULL10_Pos) /*!< 0x00200000 */
+#define RCC_CFGR_PLLMULL10 RCC_CFGR_PLLMULL10_Msk /*!< PLL input clock10 */
+#define RCC_CFGR_PLLMULL11_Pos (18U)
+#define RCC_CFGR_PLLMULL11_Msk (0x9U << RCC_CFGR_PLLMULL11_Pos) /*!< 0x00240000 */
+#define RCC_CFGR_PLLMULL11 RCC_CFGR_PLLMULL11_Msk /*!< PLL input clock*11 */
+#define RCC_CFGR_PLLMULL12_Pos (19U)
+#define RCC_CFGR_PLLMULL12_Msk (0x5U << RCC_CFGR_PLLMULL12_Pos) /*!< 0x00280000 */
+#define RCC_CFGR_PLLMULL12 RCC_CFGR_PLLMULL12_Msk /*!< PLL input clock*12 */
+#define RCC_CFGR_PLLMULL13_Pos (18U)
+#define RCC_CFGR_PLLMULL13_Msk (0xBU << RCC_CFGR_PLLMULL13_Pos) /*!< 0x002C0000 */
+#define RCC_CFGR_PLLMULL13 RCC_CFGR_PLLMULL13_Msk /*!< PLL input clock*13 */
+#define RCC_CFGR_PLLMULL14_Pos (20U)
+#define RCC_CFGR_PLLMULL14_Msk (0x3U << RCC_CFGR_PLLMULL14_Pos) /*!< 0x00300000 */
+#define RCC_CFGR_PLLMULL14 RCC_CFGR_PLLMULL14_Msk /*!< PLL input clock*14 */
+#define RCC_CFGR_PLLMULL15_Pos (18U)
+#define RCC_CFGR_PLLMULL15_Msk (0xDU << RCC_CFGR_PLLMULL15_Pos) /*!< 0x00340000 */
+#define RCC_CFGR_PLLMULL15 RCC_CFGR_PLLMULL15_Msk /*!< PLL input clock*15 */
+#define RCC_CFGR_PLLMULL16_Pos (19U)
+#define RCC_CFGR_PLLMULL16_Msk (0x7U << RCC_CFGR_PLLMULL16_Pos) /*!< 0x00380000 */
+#define RCC_CFGR_PLLMULL16 RCC_CFGR_PLLMULL16_Msk /*!< PLL input clock*16 */
+#define RCC_CFGR_USBPRE_Pos (22U)
+#define RCC_CFGR_USBPRE_Msk (0x1U << RCC_CFGR_USBPRE_Pos) /*!< 0x00400000 */
+#define RCC_CFGR_USBPRE RCC_CFGR_USBPRE_Msk /*!< USB Device prescaler */
+
+/*!< MCO configuration */
+#define RCC_CFGR_MCO_Pos (24U)
+#define RCC_CFGR_MCO_Msk (0x7U << RCC_CFGR_MCO_Pos) /*!< 0x07000000 */
+#define RCC_CFGR_MCO RCC_CFGR_MCO_Msk /*!< MCO[2:0] bits (Microcontroller Clock Output) */
+#define RCC_CFGR_MCO_0 (0x1U << RCC_CFGR_MCO_Pos) /*!< 0x01000000 */
+#define RCC_CFGR_MCO_1 (0x2U << RCC_CFGR_MCO_Pos) /*!< 0x02000000 */
+#define RCC_CFGR_MCO_2 (0x4U << RCC_CFGR_MCO_Pos) /*!< 0x04000000 */
+
+#define RCC_CFGR_MCO_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */
+#define RCC_CFGR_MCO_SYSCLK ((uint32_t)0x04000000) /*!< System clock selected as MCO source */
+#define RCC_CFGR_MCO_HSI ((uint32_t)0x05000000) /*!< HSI clock selected as MCO source */
+#define RCC_CFGR_MCO_HSE ((uint32_t)0x06000000) /*!< HSE clock selected as MCO source */
+#define RCC_CFGR_MCO_PLLCLK_DIV2 ((uint32_t)0x07000000) /*!< PLL clock divided by 2 selected as MCO source */
+
+ /* Reference defines */
+ #define RCC_CFGR_MCOSEL RCC_CFGR_MCO
+ #define RCC_CFGR_MCOSEL_0 RCC_CFGR_MCO_0
+ #define RCC_CFGR_MCOSEL_1 RCC_CFGR_MCO_1
+ #define RCC_CFGR_MCOSEL_2 RCC_CFGR_MCO_2
+ #define RCC_CFGR_MCOSEL_NOCLOCK RCC_CFGR_MCO_NOCLOCK
+ #define RCC_CFGR_MCOSEL_SYSCLK RCC_CFGR_MCO_SYSCLK
+ #define RCC_CFGR_MCOSEL_HSI RCC_CFGR_MCO_HSI
+ #define RCC_CFGR_MCOSEL_HSE RCC_CFGR_MCO_HSE
+ #define RCC_CFGR_MCOSEL_PLL_DIV2 RCC_CFGR_MCO_PLLCLK_DIV2
+
+/*!<****************** Bit definition for RCC_CIR register ********************/
+#define RCC_CIR_LSIRDYF_Pos (0U)
+#define RCC_CIR_LSIRDYF_Msk (0x1U << RCC_CIR_LSIRDYF_Pos) /*!< 0x00000001 */
+#define RCC_CIR_LSIRDYF RCC_CIR_LSIRDYF_Msk /*!< LSI Ready Interrupt flag */
+#define RCC_CIR_LSERDYF_Pos (1U)
+#define RCC_CIR_LSERDYF_Msk (0x1U << RCC_CIR_LSERDYF_Pos) /*!< 0x00000002 */
+#define RCC_CIR_LSERDYF RCC_CIR_LSERDYF_Msk /*!< LSE Ready Interrupt flag */
+#define RCC_CIR_HSIRDYF_Pos (2U)
+#define RCC_CIR_HSIRDYF_Msk (0x1U << RCC_CIR_HSIRDYF_Pos) /*!< 0x00000004 */
+#define RCC_CIR_HSIRDYF RCC_CIR_HSIRDYF_Msk /*!< HSI Ready Interrupt flag */
+#define RCC_CIR_HSERDYF_Pos (3U)
+#define RCC_CIR_HSERDYF_Msk (0x1U << RCC_CIR_HSERDYF_Pos) /*!< 0x00000008 */
+#define RCC_CIR_HSERDYF RCC_CIR_HSERDYF_Msk /*!< HSE Ready Interrupt flag */
+#define RCC_CIR_PLLRDYF_Pos (4U)
+#define RCC_CIR_PLLRDYF_Msk (0x1U << RCC_CIR_PLLRDYF_Pos) /*!< 0x00000010 */
+#define RCC_CIR_PLLRDYF RCC_CIR_PLLRDYF_Msk /*!< PLL Ready Interrupt flag */
+#define RCC_CIR_CSSF_Pos (7U)
+#define RCC_CIR_CSSF_Msk (0x1U << RCC_CIR_CSSF_Pos) /*!< 0x00000080 */
+#define RCC_CIR_CSSF RCC_CIR_CSSF_Msk /*!< Clock Security System Interrupt flag */
+#define RCC_CIR_LSIRDYIE_Pos (8U)
+#define RCC_CIR_LSIRDYIE_Msk (0x1U << RCC_CIR_LSIRDYIE_Pos) /*!< 0x00000100 */
+#define RCC_CIR_LSIRDYIE RCC_CIR_LSIRDYIE_Msk /*!< LSI Ready Interrupt Enable */
+#define RCC_CIR_LSERDYIE_Pos (9U)
+#define RCC_CIR_LSERDYIE_Msk (0x1U << RCC_CIR_LSERDYIE_Pos) /*!< 0x00000200 */
+#define RCC_CIR_LSERDYIE RCC_CIR_LSERDYIE_Msk /*!< LSE Ready Interrupt Enable */
+#define RCC_CIR_HSIRDYIE_Pos (10U)
+#define RCC_CIR_HSIRDYIE_Msk (0x1U << RCC_CIR_HSIRDYIE_Pos) /*!< 0x00000400 */
+#define RCC_CIR_HSIRDYIE RCC_CIR_HSIRDYIE_Msk /*!< HSI Ready Interrupt Enable */
+#define RCC_CIR_HSERDYIE_Pos (11U)
+#define RCC_CIR_HSERDYIE_Msk (0x1U << RCC_CIR_HSERDYIE_Pos) /*!< 0x00000800 */
+#define RCC_CIR_HSERDYIE RCC_CIR_HSERDYIE_Msk /*!< HSE Ready Interrupt Enable */
+#define RCC_CIR_PLLRDYIE_Pos (12U)
+#define RCC_CIR_PLLRDYIE_Msk (0x1U << RCC_CIR_PLLRDYIE_Pos) /*!< 0x00001000 */
+#define RCC_CIR_PLLRDYIE RCC_CIR_PLLRDYIE_Msk /*!< PLL Ready Interrupt Enable */
+#define RCC_CIR_LSIRDYC_Pos (16U)
+#define RCC_CIR_LSIRDYC_Msk (0x1U << RCC_CIR_LSIRDYC_Pos) /*!< 0x00010000 */
+#define RCC_CIR_LSIRDYC RCC_CIR_LSIRDYC_Msk /*!< LSI Ready Interrupt Clear */
+#define RCC_CIR_LSERDYC_Pos (17U)
+#define RCC_CIR_LSERDYC_Msk (0x1U << RCC_CIR_LSERDYC_Pos) /*!< 0x00020000 */
+#define RCC_CIR_LSERDYC RCC_CIR_LSERDYC_Msk /*!< LSE Ready Interrupt Clear */
+#define RCC_CIR_HSIRDYC_Pos (18U)
+#define RCC_CIR_HSIRDYC_Msk (0x1U << RCC_CIR_HSIRDYC_Pos) /*!< 0x00040000 */
+#define RCC_CIR_HSIRDYC RCC_CIR_HSIRDYC_Msk /*!< HSI Ready Interrupt Clear */
+#define RCC_CIR_HSERDYC_Pos (19U)
+#define RCC_CIR_HSERDYC_Msk (0x1U << RCC_CIR_HSERDYC_Pos) /*!< 0x00080000 */
+#define RCC_CIR_HSERDYC RCC_CIR_HSERDYC_Msk /*!< HSE Ready Interrupt Clear */
+#define RCC_CIR_PLLRDYC_Pos (20U)
+#define RCC_CIR_PLLRDYC_Msk (0x1U << RCC_CIR_PLLRDYC_Pos) /*!< 0x00100000 */
+#define RCC_CIR_PLLRDYC RCC_CIR_PLLRDYC_Msk /*!< PLL Ready Interrupt Clear */
+#define RCC_CIR_CSSC_Pos (23U)
+#define RCC_CIR_CSSC_Msk (0x1U << RCC_CIR_CSSC_Pos) /*!< 0x00800000 */
+#define RCC_CIR_CSSC RCC_CIR_CSSC_Msk /*!< Clock Security System Interrupt Clear */
+
+
+/***************** Bit definition for RCC_APB2RSTR register *****************/
+#define RCC_APB2RSTR_AFIORST_Pos (0U)
+#define RCC_APB2RSTR_AFIORST_Msk (0x1U << RCC_APB2RSTR_AFIORST_Pos) /*!< 0x00000001 */
+#define RCC_APB2RSTR_AFIORST RCC_APB2RSTR_AFIORST_Msk /*!< Alternate Function I/O reset */
+#define RCC_APB2RSTR_IOPARST_Pos (2U)
+#define RCC_APB2RSTR_IOPARST_Msk (0x1U << RCC_APB2RSTR_IOPARST_Pos) /*!< 0x00000004 */
+#define RCC_APB2RSTR_IOPARST RCC_APB2RSTR_IOPARST_Msk /*!< I/O port A reset */
+#define RCC_APB2RSTR_IOPBRST_Pos (3U)
+#define RCC_APB2RSTR_IOPBRST_Msk (0x1U << RCC_APB2RSTR_IOPBRST_Pos) /*!< 0x00000008 */
+#define RCC_APB2RSTR_IOPBRST RCC_APB2RSTR_IOPBRST_Msk /*!< I/O port B reset */
+#define RCC_APB2RSTR_IOPCRST_Pos (4U)
+#define RCC_APB2RSTR_IOPCRST_Msk (0x1U << RCC_APB2RSTR_IOPCRST_Pos) /*!< 0x00000010 */
+#define RCC_APB2RSTR_IOPCRST RCC_APB2RSTR_IOPCRST_Msk /*!< I/O port C reset */
+#define RCC_APB2RSTR_IOPDRST_Pos (5U)
+#define RCC_APB2RSTR_IOPDRST_Msk (0x1U << RCC_APB2RSTR_IOPDRST_Pos) /*!< 0x00000020 */
+#define RCC_APB2RSTR_IOPDRST RCC_APB2RSTR_IOPDRST_Msk /*!< I/O port D reset */
+#define RCC_APB2RSTR_ADC1RST_Pos (9U)
+#define RCC_APB2RSTR_ADC1RST_Msk (0x1U << RCC_APB2RSTR_ADC1RST_Pos) /*!< 0x00000200 */
+#define RCC_APB2RSTR_ADC1RST RCC_APB2RSTR_ADC1RST_Msk /*!< ADC 1 interface reset */
+
+#define RCC_APB2RSTR_ADC2RST_Pos (10U)
+#define RCC_APB2RSTR_ADC2RST_Msk (0x1U << RCC_APB2RSTR_ADC2RST_Pos) /*!< 0x00000400 */
+#define RCC_APB2RSTR_ADC2RST RCC_APB2RSTR_ADC2RST_Msk /*!< ADC 2 interface reset */
+
+#define RCC_APB2RSTR_TIM1RST_Pos (11U)
+#define RCC_APB2RSTR_TIM1RST_Msk (0x1U << RCC_APB2RSTR_TIM1RST_Pos) /*!< 0x00000800 */
+#define RCC_APB2RSTR_TIM1RST RCC_APB2RSTR_TIM1RST_Msk /*!< TIM1 Timer reset */
+#define RCC_APB2RSTR_SPI1RST_Pos (12U)
+#define RCC_APB2RSTR_SPI1RST_Msk (0x1U << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */
+#define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk /*!< SPI 1 reset */
+#define RCC_APB2RSTR_USART1RST_Pos (14U)
+#define RCC_APB2RSTR_USART1RST_Msk (0x1U << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00004000 */
+#define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk /*!< USART1 reset */
+
+
+#define RCC_APB2RSTR_IOPERST_Pos (6U)
+#define RCC_APB2RSTR_IOPERST_Msk (0x1U << RCC_APB2RSTR_IOPERST_Pos) /*!< 0x00000040 */
+#define RCC_APB2RSTR_IOPERST RCC_APB2RSTR_IOPERST_Msk /*!< I/O port E reset */
+
+
+
+
+/***************** Bit definition for RCC_APB1RSTR register *****************/
+#define RCC_APB1RSTR_TIM2RST_Pos (0U)
+#define RCC_APB1RSTR_TIM2RST_Msk (0x1U << RCC_APB1RSTR_TIM2RST_Pos) /*!< 0x00000001 */
+#define RCC_APB1RSTR_TIM2RST RCC_APB1RSTR_TIM2RST_Msk /*!< Timer 2 reset */
+#define RCC_APB1RSTR_TIM3RST_Pos (1U)
+#define RCC_APB1RSTR_TIM3RST_Msk (0x1U << RCC_APB1RSTR_TIM3RST_Pos) /*!< 0x00000002 */
+#define RCC_APB1RSTR_TIM3RST RCC_APB1RSTR_TIM3RST_Msk /*!< Timer 3 reset */
+#define RCC_APB1RSTR_WWDGRST_Pos (11U)
+#define RCC_APB1RSTR_WWDGRST_Msk (0x1U << RCC_APB1RSTR_WWDGRST_Pos) /*!< 0x00000800 */
+#define RCC_APB1RSTR_WWDGRST RCC_APB1RSTR_WWDGRST_Msk /*!< Window Watchdog reset */
+#define RCC_APB1RSTR_USART2RST_Pos (17U)
+#define RCC_APB1RSTR_USART2RST_Msk (0x1U << RCC_APB1RSTR_USART2RST_Pos) /*!< 0x00020000 */
+#define RCC_APB1RSTR_USART2RST RCC_APB1RSTR_USART2RST_Msk /*!< USART 2 reset */
+#define RCC_APB1RSTR_I2C1RST_Pos (21U)
+#define RCC_APB1RSTR_I2C1RST_Msk (0x1U << RCC_APB1RSTR_I2C1RST_Pos) /*!< 0x00200000 */
+#define RCC_APB1RSTR_I2C1RST RCC_APB1RSTR_I2C1RST_Msk /*!< I2C 1 reset */
+
+#define RCC_APB1RSTR_CAN1RST_Pos (25U)
+#define RCC_APB1RSTR_CAN1RST_Msk (0x1U << RCC_APB1RSTR_CAN1RST_Pos) /*!< 0x02000000 */
+#define RCC_APB1RSTR_CAN1RST RCC_APB1RSTR_CAN1RST_Msk /*!< CAN1 reset */
+
+#define RCC_APB1RSTR_BKPRST_Pos (27U)
+#define RCC_APB1RSTR_BKPRST_Msk (0x1U << RCC_APB1RSTR_BKPRST_Pos) /*!< 0x08000000 */
+#define RCC_APB1RSTR_BKPRST RCC_APB1RSTR_BKPRST_Msk /*!< Backup interface reset */
+#define RCC_APB1RSTR_PWRRST_Pos (28U)
+#define RCC_APB1RSTR_PWRRST_Msk (0x1U << RCC_APB1RSTR_PWRRST_Pos) /*!< 0x10000000 */
+#define RCC_APB1RSTR_PWRRST RCC_APB1RSTR_PWRRST_Msk /*!< Power interface reset */
+
+#define RCC_APB1RSTR_TIM4RST_Pos (2U)
+#define RCC_APB1RSTR_TIM4RST_Msk (0x1U << RCC_APB1RSTR_TIM4RST_Pos) /*!< 0x00000004 */
+#define RCC_APB1RSTR_TIM4RST RCC_APB1RSTR_TIM4RST_Msk /*!< Timer 4 reset */
+#define RCC_APB1RSTR_SPI2RST_Pos (14U)
+#define RCC_APB1RSTR_SPI2RST_Msk (0x1U << RCC_APB1RSTR_SPI2RST_Pos) /*!< 0x00004000 */
+#define RCC_APB1RSTR_SPI2RST RCC_APB1RSTR_SPI2RST_Msk /*!< SPI 2 reset */
+#define RCC_APB1RSTR_USART3RST_Pos (18U)
+#define RCC_APB1RSTR_USART3RST_Msk (0x1U << RCC_APB1RSTR_USART3RST_Pos) /*!< 0x00040000 */
+#define RCC_APB1RSTR_USART3RST RCC_APB1RSTR_USART3RST_Msk /*!< USART 3 reset */
+#define RCC_APB1RSTR_I2C2RST_Pos (22U)
+#define RCC_APB1RSTR_I2C2RST_Msk (0x1U << RCC_APB1RSTR_I2C2RST_Pos) /*!< 0x00400000 */
+#define RCC_APB1RSTR_I2C2RST RCC_APB1RSTR_I2C2RST_Msk /*!< I2C 2 reset */
+
+#define RCC_APB1RSTR_USBRST_Pos (23U)
+#define RCC_APB1RSTR_USBRST_Msk (0x1U << RCC_APB1RSTR_USBRST_Pos) /*!< 0x00800000 */
+#define RCC_APB1RSTR_USBRST RCC_APB1RSTR_USBRST_Msk /*!< USB Device reset */
+
+
+
+
+
+
+/****************** Bit definition for RCC_AHBENR register ******************/
+#define RCC_AHBENR_DMA1EN_Pos (0U)
+#define RCC_AHBENR_DMA1EN_Msk (0x1U << RCC_AHBENR_DMA1EN_Pos) /*!< 0x00000001 */
+#define RCC_AHBENR_DMA1EN RCC_AHBENR_DMA1EN_Msk /*!< DMA1 clock enable */
+#define RCC_AHBENR_SRAMEN_Pos (2U)
+#define RCC_AHBENR_SRAMEN_Msk (0x1U << RCC_AHBENR_SRAMEN_Pos) /*!< 0x00000004 */
+#define RCC_AHBENR_SRAMEN RCC_AHBENR_SRAMEN_Msk /*!< SRAM interface clock enable */
+#define RCC_AHBENR_FLITFEN_Pos (4U)
+#define RCC_AHBENR_FLITFEN_Msk (0x1U << RCC_AHBENR_FLITFEN_Pos) /*!< 0x00000010 */
+#define RCC_AHBENR_FLITFEN RCC_AHBENR_FLITFEN_Msk /*!< FLITF clock enable */
+#define RCC_AHBENR_CRCEN_Pos (6U)
+#define RCC_AHBENR_CRCEN_Msk (0x1U << RCC_AHBENR_CRCEN_Pos) /*!< 0x00000040 */
+#define RCC_AHBENR_CRCEN RCC_AHBENR_CRCEN_Msk /*!< CRC clock enable */
+
+
+
+
+/****************** Bit definition for RCC_APB2ENR register *****************/
+#define RCC_APB2ENR_AFIOEN_Pos (0U)
+#define RCC_APB2ENR_AFIOEN_Msk (0x1U << RCC_APB2ENR_AFIOEN_Pos) /*!< 0x00000001 */
+#define RCC_APB2ENR_AFIOEN RCC_APB2ENR_AFIOEN_Msk /*!< Alternate Function I/O clock enable */
+#define RCC_APB2ENR_IOPAEN_Pos (2U)
+#define RCC_APB2ENR_IOPAEN_Msk (0x1U << RCC_APB2ENR_IOPAEN_Pos) /*!< 0x00000004 */
+#define RCC_APB2ENR_IOPAEN RCC_APB2ENR_IOPAEN_Msk /*!< I/O port A clock enable */
+#define RCC_APB2ENR_IOPBEN_Pos (3U)
+#define RCC_APB2ENR_IOPBEN_Msk (0x1U << RCC_APB2ENR_IOPBEN_Pos) /*!< 0x00000008 */
+#define RCC_APB2ENR_IOPBEN RCC_APB2ENR_IOPBEN_Msk /*!< I/O port B clock enable */
+#define RCC_APB2ENR_IOPCEN_Pos (4U)
+#define RCC_APB2ENR_IOPCEN_Msk (0x1U << RCC_APB2ENR_IOPCEN_Pos) /*!< 0x00000010 */
+#define RCC_APB2ENR_IOPCEN RCC_APB2ENR_IOPCEN_Msk /*!< I/O port C clock enable */
+#define RCC_APB2ENR_IOPDEN_Pos (5U)
+#define RCC_APB2ENR_IOPDEN_Msk (0x1U << RCC_APB2ENR_IOPDEN_Pos) /*!< 0x00000020 */
+#define RCC_APB2ENR_IOPDEN RCC_APB2ENR_IOPDEN_Msk /*!< I/O port D clock enable */
+#define RCC_APB2ENR_ADC1EN_Pos (9U)
+#define RCC_APB2ENR_ADC1EN_Msk (0x1U << RCC_APB2ENR_ADC1EN_Pos) /*!< 0x00000200 */
+#define RCC_APB2ENR_ADC1EN RCC_APB2ENR_ADC1EN_Msk /*!< ADC 1 interface clock enable */
+
+#define RCC_APB2ENR_ADC2EN_Pos (10U)
+#define RCC_APB2ENR_ADC2EN_Msk (0x1U << RCC_APB2ENR_ADC2EN_Pos) /*!< 0x00000400 */
+#define RCC_APB2ENR_ADC2EN RCC_APB2ENR_ADC2EN_Msk /*!< ADC 2 interface clock enable */
+
+#define RCC_APB2ENR_TIM1EN_Pos (11U)
+#define RCC_APB2ENR_TIM1EN_Msk (0x1U << RCC_APB2ENR_TIM1EN_Pos) /*!< 0x00000800 */
+#define RCC_APB2ENR_TIM1EN RCC_APB2ENR_TIM1EN_Msk /*!< TIM1 Timer clock enable */
+#define RCC_APB2ENR_SPI1EN_Pos (12U)
+#define RCC_APB2ENR_SPI1EN_Msk (0x1U << RCC_APB2ENR_SPI1EN_Pos) /*!< 0x00001000 */
+#define RCC_APB2ENR_SPI1EN RCC_APB2ENR_SPI1EN_Msk /*!< SPI 1 clock enable */
+#define RCC_APB2ENR_USART1EN_Pos (14U)
+#define RCC_APB2ENR_USART1EN_Msk (0x1U << RCC_APB2ENR_USART1EN_Pos) /*!< 0x00004000 */
+#define RCC_APB2ENR_USART1EN RCC_APB2ENR_USART1EN_Msk /*!< USART1 clock enable */
+
+
+#define RCC_APB2ENR_IOPEEN_Pos (6U)
+#define RCC_APB2ENR_IOPEEN_Msk (0x1U << RCC_APB2ENR_IOPEEN_Pos) /*!< 0x00000040 */
+#define RCC_APB2ENR_IOPEEN RCC_APB2ENR_IOPEEN_Msk /*!< I/O port E clock enable */
+
+
+
+
+/***************** Bit definition for RCC_APB1ENR register ******************/
+#define RCC_APB1ENR_TIM2EN_Pos (0U)
+#define RCC_APB1ENR_TIM2EN_Msk (0x1U << RCC_APB1ENR_TIM2EN_Pos) /*!< 0x00000001 */
+#define RCC_APB1ENR_TIM2EN RCC_APB1ENR_TIM2EN_Msk /*!< Timer 2 clock enabled*/
+#define RCC_APB1ENR_TIM3EN_Pos (1U)
+#define RCC_APB1ENR_TIM3EN_Msk (0x1U << RCC_APB1ENR_TIM3EN_Pos) /*!< 0x00000002 */
+#define RCC_APB1ENR_TIM3EN RCC_APB1ENR_TIM3EN_Msk /*!< Timer 3 clock enable */
+#define RCC_APB1ENR_WWDGEN_Pos (11U)
+#define RCC_APB1ENR_WWDGEN_Msk (0x1U << RCC_APB1ENR_WWDGEN_Pos) /*!< 0x00000800 */
+#define RCC_APB1ENR_WWDGEN RCC_APB1ENR_WWDGEN_Msk /*!< Window Watchdog clock enable */
+#define RCC_APB1ENR_USART2EN_Pos (17U)
+#define RCC_APB1ENR_USART2EN_Msk (0x1U << RCC_APB1ENR_USART2EN_Pos) /*!< 0x00020000 */
+#define RCC_APB1ENR_USART2EN RCC_APB1ENR_USART2EN_Msk /*!< USART 2 clock enable */
+#define RCC_APB1ENR_I2C1EN_Pos (21U)
+#define RCC_APB1ENR_I2C1EN_Msk (0x1U << RCC_APB1ENR_I2C1EN_Pos) /*!< 0x00200000 */
+#define RCC_APB1ENR_I2C1EN RCC_APB1ENR_I2C1EN_Msk /*!< I2C 1 clock enable */
+
+#define RCC_APB1ENR_CAN1EN_Pos (25U)
+#define RCC_APB1ENR_CAN1EN_Msk (0x1U << RCC_APB1ENR_CAN1EN_Pos) /*!< 0x02000000 */
+#define RCC_APB1ENR_CAN1EN RCC_APB1ENR_CAN1EN_Msk /*!< CAN1 clock enable */
+
+#define RCC_APB1ENR_BKPEN_Pos (27U)
+#define RCC_APB1ENR_BKPEN_Msk (0x1U << RCC_APB1ENR_BKPEN_Pos) /*!< 0x08000000 */
+#define RCC_APB1ENR_BKPEN RCC_APB1ENR_BKPEN_Msk /*!< Backup interface clock enable */
+#define RCC_APB1ENR_PWREN_Pos (28U)
+#define RCC_APB1ENR_PWREN_Msk (0x1U << RCC_APB1ENR_PWREN_Pos) /*!< 0x10000000 */
+#define RCC_APB1ENR_PWREN RCC_APB1ENR_PWREN_Msk /*!< Power interface clock enable */
+
+#define RCC_APB1ENR_TIM4EN_Pos (2U)
+#define RCC_APB1ENR_TIM4EN_Msk (0x1U << RCC_APB1ENR_TIM4EN_Pos) /*!< 0x00000004 */
+#define RCC_APB1ENR_TIM4EN RCC_APB1ENR_TIM4EN_Msk /*!< Timer 4 clock enable */
+#define RCC_APB1ENR_SPI2EN_Pos (14U)
+#define RCC_APB1ENR_SPI2EN_Msk (0x1U << RCC_APB1ENR_SPI2EN_Pos) /*!< 0x00004000 */
+#define RCC_APB1ENR_SPI2EN RCC_APB1ENR_SPI2EN_Msk /*!< SPI 2 clock enable */
+#define RCC_APB1ENR_USART3EN_Pos (18U)
+#define RCC_APB1ENR_USART3EN_Msk (0x1U << RCC_APB1ENR_USART3EN_Pos) /*!< 0x00040000 */
+#define RCC_APB1ENR_USART3EN RCC_APB1ENR_USART3EN_Msk /*!< USART 3 clock enable */
+#define RCC_APB1ENR_I2C2EN_Pos (22U)
+#define RCC_APB1ENR_I2C2EN_Msk (0x1U << RCC_APB1ENR_I2C2EN_Pos) /*!< 0x00400000 */
+#define RCC_APB1ENR_I2C2EN RCC_APB1ENR_I2C2EN_Msk /*!< I2C 2 clock enable */
+
+#define RCC_APB1ENR_USBEN_Pos (23U)
+#define RCC_APB1ENR_USBEN_Msk (0x1U << RCC_APB1ENR_USBEN_Pos) /*!< 0x00800000 */
+#define RCC_APB1ENR_USBEN RCC_APB1ENR_USBEN_Msk /*!< USB Device clock enable */
+
+
+
+
+
+
+/******************* Bit definition for RCC_BDCR register *******************/
+#define RCC_BDCR_LSEON_Pos (0U)
+#define RCC_BDCR_LSEON_Msk (0x1U << RCC_BDCR_LSEON_Pos) /*!< 0x00000001 */
+#define RCC_BDCR_LSEON RCC_BDCR_LSEON_Msk /*!< External Low Speed oscillator enable */
+#define RCC_BDCR_LSERDY_Pos (1U)
+#define RCC_BDCR_LSERDY_Msk (0x1U << RCC_BDCR_LSERDY_Pos) /*!< 0x00000002 */
+#define RCC_BDCR_LSERDY RCC_BDCR_LSERDY_Msk /*!< External Low Speed oscillator Ready */
+#define RCC_BDCR_LSEBYP_Pos (2U)
+#define RCC_BDCR_LSEBYP_Msk (0x1U << RCC_BDCR_LSEBYP_Pos) /*!< 0x00000004 */
+#define RCC_BDCR_LSEBYP RCC_BDCR_LSEBYP_Msk /*!< External Low Speed oscillator Bypass */
+
+#define RCC_BDCR_RTCSEL_Pos (8U)
+#define RCC_BDCR_RTCSEL_Msk (0x3U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000300 */
+#define RCC_BDCR_RTCSEL RCC_BDCR_RTCSEL_Msk /*!< RTCSEL[1:0] bits (RTC clock source selection) */
+#define RCC_BDCR_RTCSEL_0 (0x1U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000100 */
+#define RCC_BDCR_RTCSEL_1 (0x2U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000200 */
+
+/*!< RTC congiguration */
+#define RCC_BDCR_RTCSEL_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */
+#define RCC_BDCR_RTCSEL_LSE ((uint32_t)0x00000100) /*!< LSE oscillator clock used as RTC clock */
+#define RCC_BDCR_RTCSEL_LSI ((uint32_t)0x00000200) /*!< LSI oscillator clock used as RTC clock */
+#define RCC_BDCR_RTCSEL_HSE ((uint32_t)0x00000300) /*!< HSE oscillator clock divided by 128 used as RTC clock */
+
+#define RCC_BDCR_RTCEN_Pos (15U)
+#define RCC_BDCR_RTCEN_Msk (0x1U << RCC_BDCR_RTCEN_Pos) /*!< 0x00008000 */
+#define RCC_BDCR_RTCEN RCC_BDCR_RTCEN_Msk /*!< RTC clock enable */
+#define RCC_BDCR_BDRST_Pos (16U)
+#define RCC_BDCR_BDRST_Msk (0x1U << RCC_BDCR_BDRST_Pos) /*!< 0x00010000 */
+#define RCC_BDCR_BDRST RCC_BDCR_BDRST_Msk /*!< Backup domain software reset */
+
+/******************* Bit definition for RCC_CSR register ********************/
+#define RCC_CSR_LSION_Pos (0U)
+#define RCC_CSR_LSION_Msk (0x1U << RCC_CSR_LSION_Pos) /*!< 0x00000001 */
+#define RCC_CSR_LSION RCC_CSR_LSION_Msk /*!< Internal Low Speed oscillator enable */
+#define RCC_CSR_LSIRDY_Pos (1U)
+#define RCC_CSR_LSIRDY_Msk (0x1U << RCC_CSR_LSIRDY_Pos) /*!< 0x00000002 */
+#define RCC_CSR_LSIRDY RCC_CSR_LSIRDY_Msk /*!< Internal Low Speed oscillator Ready */
+#define RCC_CSR_RMVF_Pos (24U)
+#define RCC_CSR_RMVF_Msk (0x1U << RCC_CSR_RMVF_Pos) /*!< 0x01000000 */
+#define RCC_CSR_RMVF RCC_CSR_RMVF_Msk /*!< Remove reset flag */
+#define RCC_CSR_PINRSTF_Pos (26U)
+#define RCC_CSR_PINRSTF_Msk (0x1U << RCC_CSR_PINRSTF_Pos) /*!< 0x04000000 */
+#define RCC_CSR_PINRSTF RCC_CSR_PINRSTF_Msk /*!< PIN reset flag */
+#define RCC_CSR_PORRSTF_Pos (27U)
+#define RCC_CSR_PORRSTF_Msk (0x1U << RCC_CSR_PORRSTF_Pos) /*!< 0x08000000 */
+#define RCC_CSR_PORRSTF RCC_CSR_PORRSTF_Msk /*!< POR/PDR reset flag */
+#define RCC_CSR_SFTRSTF_Pos (28U)
+#define RCC_CSR_SFTRSTF_Msk (0x1U << RCC_CSR_SFTRSTF_Pos) /*!< 0x10000000 */
+#define RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF_Msk /*!< Software Reset flag */
+#define RCC_CSR_IWDGRSTF_Pos (29U)
+#define RCC_CSR_IWDGRSTF_Msk (0x1U << RCC_CSR_IWDGRSTF_Pos) /*!< 0x20000000 */
+#define RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF_Msk /*!< Independent Watchdog reset flag */
+#define RCC_CSR_WWDGRSTF_Pos (30U)
+#define RCC_CSR_WWDGRSTF_Msk (0x1U << RCC_CSR_WWDGRSTF_Pos) /*!< 0x40000000 */
+#define RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF_Msk /*!< Window watchdog reset flag */
+#define RCC_CSR_LPWRRSTF_Pos (31U)
+#define RCC_CSR_LPWRRSTF_Msk (0x1U << RCC_CSR_LPWRRSTF_Pos) /*!< 0x80000000 */
+#define RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF_Msk /*!< Low-Power reset flag */
+
+
+
+/******************************************************************************/
+/* */
+/* General Purpose and Alternate Function I/O */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for GPIO_CRL register *******************/
+#define GPIO_CRL_MODE_Pos (0U)
+#define GPIO_CRL_MODE_Msk (0x33333333U << GPIO_CRL_MODE_Pos) /*!< 0x33333333 */
+#define GPIO_CRL_MODE GPIO_CRL_MODE_Msk /*!< Port x mode bits */
+
+#define GPIO_CRL_MODE0_Pos (0U)
+#define GPIO_CRL_MODE0_Msk (0x3U << GPIO_CRL_MODE0_Pos) /*!< 0x00000003 */
+#define GPIO_CRL_MODE0 GPIO_CRL_MODE0_Msk /*!< MODE0[1:0] bits (Port x mode bits, pin 0) */
+#define GPIO_CRL_MODE0_0 (0x1U << GPIO_CRL_MODE0_Pos) /*!< 0x00000001 */
+#define GPIO_CRL_MODE0_1 (0x2U << GPIO_CRL_MODE0_Pos) /*!< 0x00000002 */
+
+#define GPIO_CRL_MODE1_Pos (4U)
+#define GPIO_CRL_MODE1_Msk (0x3U << GPIO_CRL_MODE1_Pos) /*!< 0x00000030 */
+#define GPIO_CRL_MODE1 GPIO_CRL_MODE1_Msk /*!< MODE1[1:0] bits (Port x mode bits, pin 1) */
+#define GPIO_CRL_MODE1_0 (0x1U << GPIO_CRL_MODE1_Pos) /*!< 0x00000010 */
+#define GPIO_CRL_MODE1_1 (0x2U << GPIO_CRL_MODE1_Pos) /*!< 0x00000020 */
+
+#define GPIO_CRL_MODE2_Pos (8U)
+#define GPIO_CRL_MODE2_Msk (0x3U << GPIO_CRL_MODE2_Pos) /*!< 0x00000300 */
+#define GPIO_CRL_MODE2 GPIO_CRL_MODE2_Msk /*!< MODE2[1:0] bits (Port x mode bits, pin 2) */
+#define GPIO_CRL_MODE2_0 (0x1U << GPIO_CRL_MODE2_Pos) /*!< 0x00000100 */
+#define GPIO_CRL_MODE2_1 (0x2U << GPIO_CRL_MODE2_Pos) /*!< 0x00000200 */
+
+#define GPIO_CRL_MODE3_Pos (12U)
+#define GPIO_CRL_MODE3_Msk (0x3U << GPIO_CRL_MODE3_Pos) /*!< 0x00003000 */
+#define GPIO_CRL_MODE3 GPIO_CRL_MODE3_Msk /*!< MODE3[1:0] bits (Port x mode bits, pin 3) */
+#define GPIO_CRL_MODE3_0 (0x1U << GPIO_CRL_MODE3_Pos) /*!< 0x00001000 */
+#define GPIO_CRL_MODE3_1 (0x2U << GPIO_CRL_MODE3_Pos) /*!< 0x00002000 */
+
+#define GPIO_CRL_MODE4_Pos (16U)
+#define GPIO_CRL_MODE4_Msk (0x3U << GPIO_CRL_MODE4_Pos) /*!< 0x00030000 */
+#define GPIO_CRL_MODE4 GPIO_CRL_MODE4_Msk /*!< MODE4[1:0] bits (Port x mode bits, pin 4) */
+#define GPIO_CRL_MODE4_0 (0x1U << GPIO_CRL_MODE4_Pos) /*!< 0x00010000 */
+#define GPIO_CRL_MODE4_1 (0x2U << GPIO_CRL_MODE4_Pos) /*!< 0x00020000 */
+
+#define GPIO_CRL_MODE5_Pos (20U)
+#define GPIO_CRL_MODE5_Msk (0x3U << GPIO_CRL_MODE5_Pos) /*!< 0x00300000 */
+#define GPIO_CRL_MODE5 GPIO_CRL_MODE5_Msk /*!< MODE5[1:0] bits (Port x mode bits, pin 5) */
+#define GPIO_CRL_MODE5_0 (0x1U << GPIO_CRL_MODE5_Pos) /*!< 0x00100000 */
+#define GPIO_CRL_MODE5_1 (0x2U << GPIO_CRL_MODE5_Pos) /*!< 0x00200000 */
+
+#define GPIO_CRL_MODE6_Pos (24U)
+#define GPIO_CRL_MODE6_Msk (0x3U << GPIO_CRL_MODE6_Pos) /*!< 0x03000000 */
+#define GPIO_CRL_MODE6 GPIO_CRL_MODE6_Msk /*!< MODE6[1:0] bits (Port x mode bits, pin 6) */
+#define GPIO_CRL_MODE6_0 (0x1U << GPIO_CRL_MODE6_Pos) /*!< 0x01000000 */
+#define GPIO_CRL_MODE6_1 (0x2U << GPIO_CRL_MODE6_Pos) /*!< 0x02000000 */
+
+#define GPIO_CRL_MODE7_Pos (28U)
+#define GPIO_CRL_MODE7_Msk (0x3U << GPIO_CRL_MODE7_Pos) /*!< 0x30000000 */
+#define GPIO_CRL_MODE7 GPIO_CRL_MODE7_Msk /*!< MODE7[1:0] bits (Port x mode bits, pin 7) */
+#define GPIO_CRL_MODE7_0 (0x1U << GPIO_CRL_MODE7_Pos) /*!< 0x10000000 */
+#define GPIO_CRL_MODE7_1 (0x2U << GPIO_CRL_MODE7_Pos) /*!< 0x20000000 */
+
+#define GPIO_CRL_CNF_Pos (2U)
+#define GPIO_CRL_CNF_Msk (0x33333333U << GPIO_CRL_CNF_Pos) /*!< 0xCCCCCCCC */
+#define GPIO_CRL_CNF GPIO_CRL_CNF_Msk /*!< Port x configuration bits */
+
+#define GPIO_CRL_CNF0_Pos (2U)
+#define GPIO_CRL_CNF0_Msk (0x3U << GPIO_CRL_CNF0_Pos) /*!< 0x0000000C */
+#define GPIO_CRL_CNF0 GPIO_CRL_CNF0_Msk /*!< CNF0[1:0] bits (Port x configuration bits, pin 0) */
+#define GPIO_CRL_CNF0_0 (0x1U << GPIO_CRL_CNF0_Pos) /*!< 0x00000004 */
+#define GPIO_CRL_CNF0_1 (0x2U << GPIO_CRL_CNF0_Pos) /*!< 0x00000008 */
+
+#define GPIO_CRL_CNF1_Pos (6U)
+#define GPIO_CRL_CNF1_Msk (0x3U << GPIO_CRL_CNF1_Pos) /*!< 0x000000C0 */
+#define GPIO_CRL_CNF1 GPIO_CRL_CNF1_Msk /*!< CNF1[1:0] bits (Port x configuration bits, pin 1) */
+#define GPIO_CRL_CNF1_0 (0x1U << GPIO_CRL_CNF1_Pos) /*!< 0x00000040 */
+#define GPIO_CRL_CNF1_1 (0x2U << GPIO_CRL_CNF1_Pos) /*!< 0x00000080 */
+
+#define GPIO_CRL_CNF2_Pos (10U)
+#define GPIO_CRL_CNF2_Msk (0x3U << GPIO_CRL_CNF2_Pos) /*!< 0x00000C00 */
+#define GPIO_CRL_CNF2 GPIO_CRL_CNF2_Msk /*!< CNF2[1:0] bits (Port x configuration bits, pin 2) */
+#define GPIO_CRL_CNF2_0 (0x1U << GPIO_CRL_CNF2_Pos) /*!< 0x00000400 */
+#define GPIO_CRL_CNF2_1 (0x2U << GPIO_CRL_CNF2_Pos) /*!< 0x00000800 */
+
+#define GPIO_CRL_CNF3_Pos (14U)
+#define GPIO_CRL_CNF3_Msk (0x3U << GPIO_CRL_CNF3_Pos) /*!< 0x0000C000 */
+#define GPIO_CRL_CNF3 GPIO_CRL_CNF3_Msk /*!< CNF3[1:0] bits (Port x configuration bits, pin 3) */
+#define GPIO_CRL_CNF3_0 (0x1U << GPIO_CRL_CNF3_Pos) /*!< 0x00004000 */
+#define GPIO_CRL_CNF3_1 (0x2U << GPIO_CRL_CNF3_Pos) /*!< 0x00008000 */
+
+#define GPIO_CRL_CNF4_Pos (18U)
+#define GPIO_CRL_CNF4_Msk (0x3U << GPIO_CRL_CNF4_Pos) /*!< 0x000C0000 */
+#define GPIO_CRL_CNF4 GPIO_CRL_CNF4_Msk /*!< CNF4[1:0] bits (Port x configuration bits, pin 4) */
+#define GPIO_CRL_CNF4_0 (0x1U << GPIO_CRL_CNF4_Pos) /*!< 0x00040000 */
+#define GPIO_CRL_CNF4_1 (0x2U << GPIO_CRL_CNF4_Pos) /*!< 0x00080000 */
+
+#define GPIO_CRL_CNF5_Pos (22U)
+#define GPIO_CRL_CNF5_Msk (0x3U << GPIO_CRL_CNF5_Pos) /*!< 0x00C00000 */
+#define GPIO_CRL_CNF5 GPIO_CRL_CNF5_Msk /*!< CNF5[1:0] bits (Port x configuration bits, pin 5) */
+#define GPIO_CRL_CNF5_0 (0x1U << GPIO_CRL_CNF5_Pos) /*!< 0x00400000 */
+#define GPIO_CRL_CNF5_1 (0x2U << GPIO_CRL_CNF5_Pos) /*!< 0x00800000 */
+
+#define GPIO_CRL_CNF6_Pos (26U)
+#define GPIO_CRL_CNF6_Msk (0x3U << GPIO_CRL_CNF6_Pos) /*!< 0x0C000000 */
+#define GPIO_CRL_CNF6 GPIO_CRL_CNF6_Msk /*!< CNF6[1:0] bits (Port x configuration bits, pin 6) */
+#define GPIO_CRL_CNF6_0 (0x1U << GPIO_CRL_CNF6_Pos) /*!< 0x04000000 */
+#define GPIO_CRL_CNF6_1 (0x2U << GPIO_CRL_CNF6_Pos) /*!< 0x08000000 */
+
+#define GPIO_CRL_CNF7_Pos (30U)
+#define GPIO_CRL_CNF7_Msk (0x3U << GPIO_CRL_CNF7_Pos) /*!< 0xC0000000 */
+#define GPIO_CRL_CNF7 GPIO_CRL_CNF7_Msk /*!< CNF7[1:0] bits (Port x configuration bits, pin 7) */
+#define GPIO_CRL_CNF7_0 (0x1U << GPIO_CRL_CNF7_Pos) /*!< 0x40000000 */
+#define GPIO_CRL_CNF7_1 (0x2U << GPIO_CRL_CNF7_Pos) /*!< 0x80000000 */
+
+/******************* Bit definition for GPIO_CRH register *******************/
+#define GPIO_CRH_MODE_Pos (0U)
+#define GPIO_CRH_MODE_Msk (0x33333333U << GPIO_CRH_MODE_Pos) /*!< 0x33333333 */
+#define GPIO_CRH_MODE GPIO_CRH_MODE_Msk /*!< Port x mode bits */
+
+#define GPIO_CRH_MODE8_Pos (0U)
+#define GPIO_CRH_MODE8_Msk (0x3U << GPIO_CRH_MODE8_Pos) /*!< 0x00000003 */
+#define GPIO_CRH_MODE8 GPIO_CRH_MODE8_Msk /*!< MODE8[1:0] bits (Port x mode bits, pin 8) */
+#define GPIO_CRH_MODE8_0 (0x1U << GPIO_CRH_MODE8_Pos) /*!< 0x00000001 */
+#define GPIO_CRH_MODE8_1 (0x2U << GPIO_CRH_MODE8_Pos) /*!< 0x00000002 */
+
+#define GPIO_CRH_MODE9_Pos (4U)
+#define GPIO_CRH_MODE9_Msk (0x3U << GPIO_CRH_MODE9_Pos) /*!< 0x00000030 */
+#define GPIO_CRH_MODE9 GPIO_CRH_MODE9_Msk /*!< MODE9[1:0] bits (Port x mode bits, pin 9) */
+#define GPIO_CRH_MODE9_0 (0x1U << GPIO_CRH_MODE9_Pos) /*!< 0x00000010 */
+#define GPIO_CRH_MODE9_1 (0x2U << GPIO_CRH_MODE9_Pos) /*!< 0x00000020 */
+
+#define GPIO_CRH_MODE10_Pos (8U)
+#define GPIO_CRH_MODE10_Msk (0x3U << GPIO_CRH_MODE10_Pos) /*!< 0x00000300 */
+#define GPIO_CRH_MODE10 GPIO_CRH_MODE10_Msk /*!< MODE10[1:0] bits (Port x mode bits, pin 10) */
+#define GPIO_CRH_MODE10_0 (0x1U << GPIO_CRH_MODE10_Pos) /*!< 0x00000100 */
+#define GPIO_CRH_MODE10_1 (0x2U << GPIO_CRH_MODE10_Pos) /*!< 0x00000200 */
+
+#define GPIO_CRH_MODE11_Pos (12U)
+#define GPIO_CRH_MODE11_Msk (0x3U << GPIO_CRH_MODE11_Pos) /*!< 0x00003000 */
+#define GPIO_CRH_MODE11 GPIO_CRH_MODE11_Msk /*!< MODE11[1:0] bits (Port x mode bits, pin 11) */
+#define GPIO_CRH_MODE11_0 (0x1U << GPIO_CRH_MODE11_Pos) /*!< 0x00001000 */
+#define GPIO_CRH_MODE11_1 (0x2U << GPIO_CRH_MODE11_Pos) /*!< 0x00002000 */
+
+#define GPIO_CRH_MODE12_Pos (16U)
+#define GPIO_CRH_MODE12_Msk (0x3U << GPIO_CRH_MODE12_Pos) /*!< 0x00030000 */
+#define GPIO_CRH_MODE12 GPIO_CRH_MODE12_Msk /*!< MODE12[1:0] bits (Port x mode bits, pin 12) */
+#define GPIO_CRH_MODE12_0 (0x1U << GPIO_CRH_MODE12_Pos) /*!< 0x00010000 */
+#define GPIO_CRH_MODE12_1 (0x2U << GPIO_CRH_MODE12_Pos) /*!< 0x00020000 */
+
+#define GPIO_CRH_MODE13_Pos (20U)
+#define GPIO_CRH_MODE13_Msk (0x3U << GPIO_CRH_MODE13_Pos) /*!< 0x00300000 */
+#define GPIO_CRH_MODE13 GPIO_CRH_MODE13_Msk /*!< MODE13[1:0] bits (Port x mode bits, pin 13) */
+#define GPIO_CRH_MODE13_0 (0x1U << GPIO_CRH_MODE13_Pos) /*!< 0x00100000 */
+#define GPIO_CRH_MODE13_1 (0x2U << GPIO_CRH_MODE13_Pos) /*!< 0x00200000 */
+
+#define GPIO_CRH_MODE14_Pos (24U)
+#define GPIO_CRH_MODE14_Msk (0x3U << GPIO_CRH_MODE14_Pos) /*!< 0x03000000 */
+#define GPIO_CRH_MODE14 GPIO_CRH_MODE14_Msk /*!< MODE14[1:0] bits (Port x mode bits, pin 14) */
+#define GPIO_CRH_MODE14_0 (0x1U << GPIO_CRH_MODE14_Pos) /*!< 0x01000000 */
+#define GPIO_CRH_MODE14_1 (0x2U << GPIO_CRH_MODE14_Pos) /*!< 0x02000000 */
+
+#define GPIO_CRH_MODE15_Pos (28U)
+#define GPIO_CRH_MODE15_Msk (0x3U << GPIO_CRH_MODE15_Pos) /*!< 0x30000000 */
+#define GPIO_CRH_MODE15 GPIO_CRH_MODE15_Msk /*!< MODE15[1:0] bits (Port x mode bits, pin 15) */
+#define GPIO_CRH_MODE15_0 (0x1U << GPIO_CRH_MODE15_Pos) /*!< 0x10000000 */
+#define GPIO_CRH_MODE15_1 (0x2U << GPIO_CRH_MODE15_Pos) /*!< 0x20000000 */
+
+#define GPIO_CRH_CNF_Pos (2U)
+#define GPIO_CRH_CNF_Msk (0x33333333U << GPIO_CRH_CNF_Pos) /*!< 0xCCCCCCCC */
+#define GPIO_CRH_CNF GPIO_CRH_CNF_Msk /*!< Port x configuration bits */
+
+#define GPIO_CRH_CNF8_Pos (2U)
+#define GPIO_CRH_CNF8_Msk (0x3U << GPIO_CRH_CNF8_Pos) /*!< 0x0000000C */
+#define GPIO_CRH_CNF8 GPIO_CRH_CNF8_Msk /*!< CNF8[1:0] bits (Port x configuration bits, pin 8) */
+#define GPIO_CRH_CNF8_0 (0x1U << GPIO_CRH_CNF8_Pos) /*!< 0x00000004 */
+#define GPIO_CRH_CNF8_1 (0x2U << GPIO_CRH_CNF8_Pos) /*!< 0x00000008 */
+
+#define GPIO_CRH_CNF9_Pos (6U)
+#define GPIO_CRH_CNF9_Msk (0x3U << GPIO_CRH_CNF9_Pos) /*!< 0x000000C0 */
+#define GPIO_CRH_CNF9 GPIO_CRH_CNF9_Msk /*!< CNF9[1:0] bits (Port x configuration bits, pin 9) */
+#define GPIO_CRH_CNF9_0 (0x1U << GPIO_CRH_CNF9_Pos) /*!< 0x00000040 */
+#define GPIO_CRH_CNF9_1 (0x2U << GPIO_CRH_CNF9_Pos) /*!< 0x00000080 */
+
+#define GPIO_CRH_CNF10_Pos (10U)
+#define GPIO_CRH_CNF10_Msk (0x3U << GPIO_CRH_CNF10_Pos) /*!< 0x00000C00 */
+#define GPIO_CRH_CNF10 GPIO_CRH_CNF10_Msk /*!< CNF10[1:0] bits (Port x configuration bits, pin 10) */
+#define GPIO_CRH_CNF10_0 (0x1U << GPIO_CRH_CNF10_Pos) /*!< 0x00000400 */
+#define GPIO_CRH_CNF10_1 (0x2U << GPIO_CRH_CNF10_Pos) /*!< 0x00000800 */
+
+#define GPIO_CRH_CNF11_Pos (14U)
+#define GPIO_CRH_CNF11_Msk (0x3U << GPIO_CRH_CNF11_Pos) /*!< 0x0000C000 */
+#define GPIO_CRH_CNF11 GPIO_CRH_CNF11_Msk /*!< CNF11[1:0] bits (Port x configuration bits, pin 11) */
+#define GPIO_CRH_CNF11_0 (0x1U << GPIO_CRH_CNF11_Pos) /*!< 0x00004000 */
+#define GPIO_CRH_CNF11_1 (0x2U << GPIO_CRH_CNF11_Pos) /*!< 0x00008000 */
+
+#define GPIO_CRH_CNF12_Pos (18U)
+#define GPIO_CRH_CNF12_Msk (0x3U << GPIO_CRH_CNF12_Pos) /*!< 0x000C0000 */
+#define GPIO_CRH_CNF12 GPIO_CRH_CNF12_Msk /*!< CNF12[1:0] bits (Port x configuration bits, pin 12) */
+#define GPIO_CRH_CNF12_0 (0x1U << GPIO_CRH_CNF12_Pos) /*!< 0x00040000 */
+#define GPIO_CRH_CNF12_1 (0x2U << GPIO_CRH_CNF12_Pos) /*!< 0x00080000 */
+
+#define GPIO_CRH_CNF13_Pos (22U)
+#define GPIO_CRH_CNF13_Msk (0x3U << GPIO_CRH_CNF13_Pos) /*!< 0x00C00000 */
+#define GPIO_CRH_CNF13 GPIO_CRH_CNF13_Msk /*!< CNF13[1:0] bits (Port x configuration bits, pin 13) */
+#define GPIO_CRH_CNF13_0 (0x1U << GPIO_CRH_CNF13_Pos) /*!< 0x00400000 */
+#define GPIO_CRH_CNF13_1 (0x2U << GPIO_CRH_CNF13_Pos) /*!< 0x00800000 */
+
+#define GPIO_CRH_CNF14_Pos (26U)
+#define GPIO_CRH_CNF14_Msk (0x3U << GPIO_CRH_CNF14_Pos) /*!< 0x0C000000 */
+#define GPIO_CRH_CNF14 GPIO_CRH_CNF14_Msk /*!< CNF14[1:0] bits (Port x configuration bits, pin 14) */
+#define GPIO_CRH_CNF14_0 (0x1U << GPIO_CRH_CNF14_Pos) /*!< 0x04000000 */
+#define GPIO_CRH_CNF14_1 (0x2U << GPIO_CRH_CNF14_Pos) /*!< 0x08000000 */
+
+#define GPIO_CRH_CNF15_Pos (30U)
+#define GPIO_CRH_CNF15_Msk (0x3U << GPIO_CRH_CNF15_Pos) /*!< 0xC0000000 */
+#define GPIO_CRH_CNF15 GPIO_CRH_CNF15_Msk /*!< CNF15[1:0] bits (Port x configuration bits, pin 15) */
+#define GPIO_CRH_CNF15_0 (0x1U << GPIO_CRH_CNF15_Pos) /*!< 0x40000000 */
+#define GPIO_CRH_CNF15_1 (0x2U << GPIO_CRH_CNF15_Pos) /*!< 0x80000000 */
+
+/*!<****************** Bit definition for GPIO_IDR register *******************/
+#define GPIO_IDR_IDR0_Pos (0U)
+#define GPIO_IDR_IDR0_Msk (0x1U << GPIO_IDR_IDR0_Pos) /*!< 0x00000001 */
+#define GPIO_IDR_IDR0 GPIO_IDR_IDR0_Msk /*!< Port input data, bit 0 */
+#define GPIO_IDR_IDR1_Pos (1U)
+#define GPIO_IDR_IDR1_Msk (0x1U << GPIO_IDR_IDR1_Pos) /*!< 0x00000002 */
+#define GPIO_IDR_IDR1 GPIO_IDR_IDR1_Msk /*!< Port input data, bit 1 */
+#define GPIO_IDR_IDR2_Pos (2U)
+#define GPIO_IDR_IDR2_Msk (0x1U << GPIO_IDR_IDR2_Pos) /*!< 0x00000004 */
+#define GPIO_IDR_IDR2 GPIO_IDR_IDR2_Msk /*!< Port input data, bit 2 */
+#define GPIO_IDR_IDR3_Pos (3U)
+#define GPIO_IDR_IDR3_Msk (0x1U << GPIO_IDR_IDR3_Pos) /*!< 0x00000008 */
+#define GPIO_IDR_IDR3 GPIO_IDR_IDR3_Msk /*!< Port input data, bit 3 */
+#define GPIO_IDR_IDR4_Pos (4U)
+#define GPIO_IDR_IDR4_Msk (0x1U << GPIO_IDR_IDR4_Pos) /*!< 0x00000010 */
+#define GPIO_IDR_IDR4 GPIO_IDR_IDR4_Msk /*!< Port input data, bit 4 */
+#define GPIO_IDR_IDR5_Pos (5U)
+#define GPIO_IDR_IDR5_Msk (0x1U << GPIO_IDR_IDR5_Pos) /*!< 0x00000020 */
+#define GPIO_IDR_IDR5 GPIO_IDR_IDR5_Msk /*!< Port input data, bit 5 */
+#define GPIO_IDR_IDR6_Pos (6U)
+#define GPIO_IDR_IDR6_Msk (0x1U << GPIO_IDR_IDR6_Pos) /*!< 0x00000040 */
+#define GPIO_IDR_IDR6 GPIO_IDR_IDR6_Msk /*!< Port input data, bit 6 */
+#define GPIO_IDR_IDR7_Pos (7U)
+#define GPIO_IDR_IDR7_Msk (0x1U << GPIO_IDR_IDR7_Pos) /*!< 0x00000080 */
+#define GPIO_IDR_IDR7 GPIO_IDR_IDR7_Msk /*!< Port input data, bit 7 */
+#define GPIO_IDR_IDR8_Pos (8U)
+#define GPIO_IDR_IDR8_Msk (0x1U << GPIO_IDR_IDR8_Pos) /*!< 0x00000100 */
+#define GPIO_IDR_IDR8 GPIO_IDR_IDR8_Msk /*!< Port input data, bit 8 */
+#define GPIO_IDR_IDR9_Pos (9U)
+#define GPIO_IDR_IDR9_Msk (0x1U << GPIO_IDR_IDR9_Pos) /*!< 0x00000200 */
+#define GPIO_IDR_IDR9 GPIO_IDR_IDR9_Msk /*!< Port input data, bit 9 */
+#define GPIO_IDR_IDR10_Pos (10U)
+#define GPIO_IDR_IDR10_Msk (0x1U << GPIO_IDR_IDR10_Pos) /*!< 0x00000400 */
+#define GPIO_IDR_IDR10 GPIO_IDR_IDR10_Msk /*!< Port input data, bit 10 */
+#define GPIO_IDR_IDR11_Pos (11U)
+#define GPIO_IDR_IDR11_Msk (0x1U << GPIO_IDR_IDR11_Pos) /*!< 0x00000800 */
+#define GPIO_IDR_IDR11 GPIO_IDR_IDR11_Msk /*!< Port input data, bit 11 */
+#define GPIO_IDR_IDR12_Pos (12U)
+#define GPIO_IDR_IDR12_Msk (0x1U << GPIO_IDR_IDR12_Pos) /*!< 0x00001000 */
+#define GPIO_IDR_IDR12 GPIO_IDR_IDR12_Msk /*!< Port input data, bit 12 */
+#define GPIO_IDR_IDR13_Pos (13U)
+#define GPIO_IDR_IDR13_Msk (0x1U << GPIO_IDR_IDR13_Pos) /*!< 0x00002000 */
+#define GPIO_IDR_IDR13 GPIO_IDR_IDR13_Msk /*!< Port input data, bit 13 */
+#define GPIO_IDR_IDR14_Pos (14U)
+#define GPIO_IDR_IDR14_Msk (0x1U << GPIO_IDR_IDR14_Pos) /*!< 0x00004000 */
+#define GPIO_IDR_IDR14 GPIO_IDR_IDR14_Msk /*!< Port input data, bit 14 */
+#define GPIO_IDR_IDR15_Pos (15U)
+#define GPIO_IDR_IDR15_Msk (0x1U << GPIO_IDR_IDR15_Pos) /*!< 0x00008000 */
+#define GPIO_IDR_IDR15 GPIO_IDR_IDR15_Msk /*!< Port input data, bit 15 */
+
+/******************* Bit definition for GPIO_ODR register *******************/
+#define GPIO_ODR_ODR0_Pos (0U)
+#define GPIO_ODR_ODR0_Msk (0x1U << GPIO_ODR_ODR0_Pos) /*!< 0x00000001 */
+#define GPIO_ODR_ODR0 GPIO_ODR_ODR0_Msk /*!< Port output data, bit 0 */
+#define GPIO_ODR_ODR1_Pos (1U)
+#define GPIO_ODR_ODR1_Msk (0x1U << GPIO_ODR_ODR1_Pos) /*!< 0x00000002 */
+#define GPIO_ODR_ODR1 GPIO_ODR_ODR1_Msk /*!< Port output data, bit 1 */
+#define GPIO_ODR_ODR2_Pos (2U)
+#define GPIO_ODR_ODR2_Msk (0x1U << GPIO_ODR_ODR2_Pos) /*!< 0x00000004 */
+#define GPIO_ODR_ODR2 GPIO_ODR_ODR2_Msk /*!< Port output data, bit 2 */
+#define GPIO_ODR_ODR3_Pos (3U)
+#define GPIO_ODR_ODR3_Msk (0x1U << GPIO_ODR_ODR3_Pos) /*!< 0x00000008 */
+#define GPIO_ODR_ODR3 GPIO_ODR_ODR3_Msk /*!< Port output data, bit 3 */
+#define GPIO_ODR_ODR4_Pos (4U)
+#define GPIO_ODR_ODR4_Msk (0x1U << GPIO_ODR_ODR4_Pos) /*!< 0x00000010 */
+#define GPIO_ODR_ODR4 GPIO_ODR_ODR4_Msk /*!< Port output data, bit 4 */
+#define GPIO_ODR_ODR5_Pos (5U)
+#define GPIO_ODR_ODR5_Msk (0x1U << GPIO_ODR_ODR5_Pos) /*!< 0x00000020 */
+#define GPIO_ODR_ODR5 GPIO_ODR_ODR5_Msk /*!< Port output data, bit 5 */
+#define GPIO_ODR_ODR6_Pos (6U)
+#define GPIO_ODR_ODR6_Msk (0x1U << GPIO_ODR_ODR6_Pos) /*!< 0x00000040 */
+#define GPIO_ODR_ODR6 GPIO_ODR_ODR6_Msk /*!< Port output data, bit 6 */
+#define GPIO_ODR_ODR7_Pos (7U)
+#define GPIO_ODR_ODR7_Msk (0x1U << GPIO_ODR_ODR7_Pos) /*!< 0x00000080 */
+#define GPIO_ODR_ODR7 GPIO_ODR_ODR7_Msk /*!< Port output data, bit 7 */
+#define GPIO_ODR_ODR8_Pos (8U)
+#define GPIO_ODR_ODR8_Msk (0x1U << GPIO_ODR_ODR8_Pos) /*!< 0x00000100 */
+#define GPIO_ODR_ODR8 GPIO_ODR_ODR8_Msk /*!< Port output data, bit 8 */
+#define GPIO_ODR_ODR9_Pos (9U)
+#define GPIO_ODR_ODR9_Msk (0x1U << GPIO_ODR_ODR9_Pos) /*!< 0x00000200 */
+#define GPIO_ODR_ODR9 GPIO_ODR_ODR9_Msk /*!< Port output data, bit 9 */
+#define GPIO_ODR_ODR10_Pos (10U)
+#define GPIO_ODR_ODR10_Msk (0x1U << GPIO_ODR_ODR10_Pos) /*!< 0x00000400 */
+#define GPIO_ODR_ODR10 GPIO_ODR_ODR10_Msk /*!< Port output data, bit 10 */
+#define GPIO_ODR_ODR11_Pos (11U)
+#define GPIO_ODR_ODR11_Msk (0x1U << GPIO_ODR_ODR11_Pos) /*!< 0x00000800 */
+#define GPIO_ODR_ODR11 GPIO_ODR_ODR11_Msk /*!< Port output data, bit 11 */
+#define GPIO_ODR_ODR12_Pos (12U)
+#define GPIO_ODR_ODR12_Msk (0x1U << GPIO_ODR_ODR12_Pos) /*!< 0x00001000 */
+#define GPIO_ODR_ODR12 GPIO_ODR_ODR12_Msk /*!< Port output data, bit 12 */
+#define GPIO_ODR_ODR13_Pos (13U)
+#define GPIO_ODR_ODR13_Msk (0x1U << GPIO_ODR_ODR13_Pos) /*!< 0x00002000 */
+#define GPIO_ODR_ODR13 GPIO_ODR_ODR13_Msk /*!< Port output data, bit 13 */
+#define GPIO_ODR_ODR14_Pos (14U)
+#define GPIO_ODR_ODR14_Msk (0x1U << GPIO_ODR_ODR14_Pos) /*!< 0x00004000 */
+#define GPIO_ODR_ODR14 GPIO_ODR_ODR14_Msk /*!< Port output data, bit 14 */
+#define GPIO_ODR_ODR15_Pos (15U)
+#define GPIO_ODR_ODR15_Msk (0x1U << GPIO_ODR_ODR15_Pos) /*!< 0x00008000 */
+#define GPIO_ODR_ODR15 GPIO_ODR_ODR15_Msk /*!< Port output data, bit 15 */
+
+/****************** Bit definition for GPIO_BSRR register *******************/
+#define GPIO_BSRR_BS0_Pos (0U)
+#define GPIO_BSRR_BS0_Msk (0x1U << GPIO_BSRR_BS0_Pos) /*!< 0x00000001 */
+#define GPIO_BSRR_BS0 GPIO_BSRR_BS0_Msk /*!< Port x Set bit 0 */
+#define GPIO_BSRR_BS1_Pos (1U)
+#define GPIO_BSRR_BS1_Msk (0x1U << GPIO_BSRR_BS1_Pos) /*!< 0x00000002 */
+#define GPIO_BSRR_BS1 GPIO_BSRR_BS1_Msk /*!< Port x Set bit 1 */
+#define GPIO_BSRR_BS2_Pos (2U)
+#define GPIO_BSRR_BS2_Msk (0x1U << GPIO_BSRR_BS2_Pos) /*!< 0x00000004 */
+#define GPIO_BSRR_BS2 GPIO_BSRR_BS2_Msk /*!< Port x Set bit 2 */
+#define GPIO_BSRR_BS3_Pos (3U)
+#define GPIO_BSRR_BS3_Msk (0x1U << GPIO_BSRR_BS3_Pos) /*!< 0x00000008 */
+#define GPIO_BSRR_BS3 GPIO_BSRR_BS3_Msk /*!< Port x Set bit 3 */
+#define GPIO_BSRR_BS4_Pos (4U)
+#define GPIO_BSRR_BS4_Msk (0x1U << GPIO_BSRR_BS4_Pos) /*!< 0x00000010 */
+#define GPIO_BSRR_BS4 GPIO_BSRR_BS4_Msk /*!< Port x Set bit 4 */
+#define GPIO_BSRR_BS5_Pos (5U)
+#define GPIO_BSRR_BS5_Msk (0x1U << GPIO_BSRR_BS5_Pos) /*!< 0x00000020 */
+#define GPIO_BSRR_BS5 GPIO_BSRR_BS5_Msk /*!< Port x Set bit 5 */
+#define GPIO_BSRR_BS6_Pos (6U)
+#define GPIO_BSRR_BS6_Msk (0x1U << GPIO_BSRR_BS6_Pos) /*!< 0x00000040 */
+#define GPIO_BSRR_BS6 GPIO_BSRR_BS6_Msk /*!< Port x Set bit 6 */
+#define GPIO_BSRR_BS7_Pos (7U)
+#define GPIO_BSRR_BS7_Msk (0x1U << GPIO_BSRR_BS7_Pos) /*!< 0x00000080 */
+#define GPIO_BSRR_BS7 GPIO_BSRR_BS7_Msk /*!< Port x Set bit 7 */
+#define GPIO_BSRR_BS8_Pos (8U)
+#define GPIO_BSRR_BS8_Msk (0x1U << GPIO_BSRR_BS8_Pos) /*!< 0x00000100 */
+#define GPIO_BSRR_BS8 GPIO_BSRR_BS8_Msk /*!< Port x Set bit 8 */
+#define GPIO_BSRR_BS9_Pos (9U)
+#define GPIO_BSRR_BS9_Msk (0x1U << GPIO_BSRR_BS9_Pos) /*!< 0x00000200 */
+#define GPIO_BSRR_BS9 GPIO_BSRR_BS9_Msk /*!< Port x Set bit 9 */
+#define GPIO_BSRR_BS10_Pos (10U)
+#define GPIO_BSRR_BS10_Msk (0x1U << GPIO_BSRR_BS10_Pos) /*!< 0x00000400 */
+#define GPIO_BSRR_BS10 GPIO_BSRR_BS10_Msk /*!< Port x Set bit 10 */
+#define GPIO_BSRR_BS11_Pos (11U)
+#define GPIO_BSRR_BS11_Msk (0x1U << GPIO_BSRR_BS11_Pos) /*!< 0x00000800 */
+#define GPIO_BSRR_BS11 GPIO_BSRR_BS11_Msk /*!< Port x Set bit 11 */
+#define GPIO_BSRR_BS12_Pos (12U)
+#define GPIO_BSRR_BS12_Msk (0x1U << GPIO_BSRR_BS12_Pos) /*!< 0x00001000 */
+#define GPIO_BSRR_BS12 GPIO_BSRR_BS12_Msk /*!< Port x Set bit 12 */
+#define GPIO_BSRR_BS13_Pos (13U)
+#define GPIO_BSRR_BS13_Msk (0x1U << GPIO_BSRR_BS13_Pos) /*!< 0x00002000 */
+#define GPIO_BSRR_BS13 GPIO_BSRR_BS13_Msk /*!< Port x Set bit 13 */
+#define GPIO_BSRR_BS14_Pos (14U)
+#define GPIO_BSRR_BS14_Msk (0x1U << GPIO_BSRR_BS14_Pos) /*!< 0x00004000 */
+#define GPIO_BSRR_BS14 GPIO_BSRR_BS14_Msk /*!< Port x Set bit 14 */
+#define GPIO_BSRR_BS15_Pos (15U)
+#define GPIO_BSRR_BS15_Msk (0x1U << GPIO_BSRR_BS15_Pos) /*!< 0x00008000 */
+#define GPIO_BSRR_BS15 GPIO_BSRR_BS15_Msk /*!< Port x Set bit 15 */
+
+#define GPIO_BSRR_BR0_Pos (16U)
+#define GPIO_BSRR_BR0_Msk (0x1U << GPIO_BSRR_BR0_Pos) /*!< 0x00010000 */
+#define GPIO_BSRR_BR0 GPIO_BSRR_BR0_Msk /*!< Port x Reset bit 0 */
+#define GPIO_BSRR_BR1_Pos (17U)
+#define GPIO_BSRR_BR1_Msk (0x1U << GPIO_BSRR_BR1_Pos) /*!< 0x00020000 */
+#define GPIO_BSRR_BR1 GPIO_BSRR_BR1_Msk /*!< Port x Reset bit 1 */
+#define GPIO_BSRR_BR2_Pos (18U)
+#define GPIO_BSRR_BR2_Msk (0x1U << GPIO_BSRR_BR2_Pos) /*!< 0x00040000 */
+#define GPIO_BSRR_BR2 GPIO_BSRR_BR2_Msk /*!< Port x Reset bit 2 */
+#define GPIO_BSRR_BR3_Pos (19U)
+#define GPIO_BSRR_BR3_Msk (0x1U << GPIO_BSRR_BR3_Pos) /*!< 0x00080000 */
+#define GPIO_BSRR_BR3 GPIO_BSRR_BR3_Msk /*!< Port x Reset bit 3 */
+#define GPIO_BSRR_BR4_Pos (20U)
+#define GPIO_BSRR_BR4_Msk (0x1U << GPIO_BSRR_BR4_Pos) /*!< 0x00100000 */
+#define GPIO_BSRR_BR4 GPIO_BSRR_BR4_Msk /*!< Port x Reset bit 4 */
+#define GPIO_BSRR_BR5_Pos (21U)
+#define GPIO_BSRR_BR5_Msk (0x1U << GPIO_BSRR_BR5_Pos) /*!< 0x00200000 */
+#define GPIO_BSRR_BR5 GPIO_BSRR_BR5_Msk /*!< Port x Reset bit 5 */
+#define GPIO_BSRR_BR6_Pos (22U)
+#define GPIO_BSRR_BR6_Msk (0x1U << GPIO_BSRR_BR6_Pos) /*!< 0x00400000 */
+#define GPIO_BSRR_BR6 GPIO_BSRR_BR6_Msk /*!< Port x Reset bit 6 */
+#define GPIO_BSRR_BR7_Pos (23U)
+#define GPIO_BSRR_BR7_Msk (0x1U << GPIO_BSRR_BR7_Pos) /*!< 0x00800000 */
+#define GPIO_BSRR_BR7 GPIO_BSRR_BR7_Msk /*!< Port x Reset bit 7 */
+#define GPIO_BSRR_BR8_Pos (24U)
+#define GPIO_BSRR_BR8_Msk (0x1U << GPIO_BSRR_BR8_Pos) /*!< 0x01000000 */
+#define GPIO_BSRR_BR8 GPIO_BSRR_BR8_Msk /*!< Port x Reset bit 8 */
+#define GPIO_BSRR_BR9_Pos (25U)
+#define GPIO_BSRR_BR9_Msk (0x1U << GPIO_BSRR_BR9_Pos) /*!< 0x02000000 */
+#define GPIO_BSRR_BR9 GPIO_BSRR_BR9_Msk /*!< Port x Reset bit 9 */
+#define GPIO_BSRR_BR10_Pos (26U)
+#define GPIO_BSRR_BR10_Msk (0x1U << GPIO_BSRR_BR10_Pos) /*!< 0x04000000 */
+#define GPIO_BSRR_BR10 GPIO_BSRR_BR10_Msk /*!< Port x Reset bit 10 */
+#define GPIO_BSRR_BR11_Pos (27U)
+#define GPIO_BSRR_BR11_Msk (0x1U << GPIO_BSRR_BR11_Pos) /*!< 0x08000000 */
+#define GPIO_BSRR_BR11 GPIO_BSRR_BR11_Msk /*!< Port x Reset bit 11 */
+#define GPIO_BSRR_BR12_Pos (28U)
+#define GPIO_BSRR_BR12_Msk (0x1U << GPIO_BSRR_BR12_Pos) /*!< 0x10000000 */
+#define GPIO_BSRR_BR12 GPIO_BSRR_BR12_Msk /*!< Port x Reset bit 12 */
+#define GPIO_BSRR_BR13_Pos (29U)
+#define GPIO_BSRR_BR13_Msk (0x1U << GPIO_BSRR_BR13_Pos) /*!< 0x20000000 */
+#define GPIO_BSRR_BR13 GPIO_BSRR_BR13_Msk /*!< Port x Reset bit 13 */
+#define GPIO_BSRR_BR14_Pos (30U)
+#define GPIO_BSRR_BR14_Msk (0x1U << GPIO_BSRR_BR14_Pos) /*!< 0x40000000 */
+#define GPIO_BSRR_BR14 GPIO_BSRR_BR14_Msk /*!< Port x Reset bit 14 */
+#define GPIO_BSRR_BR15_Pos (31U)
+#define GPIO_BSRR_BR15_Msk (0x1U << GPIO_BSRR_BR15_Pos) /*!< 0x80000000 */
+#define GPIO_BSRR_BR15 GPIO_BSRR_BR15_Msk /*!< Port x Reset bit 15 */
+
+/******************* Bit definition for GPIO_BRR register *******************/
+#define GPIO_BRR_BR0_Pos (0U)
+#define GPIO_BRR_BR0_Msk (0x1U << GPIO_BRR_BR0_Pos) /*!< 0x00000001 */
+#define GPIO_BRR_BR0 GPIO_BRR_BR0_Msk /*!< Port x Reset bit 0 */
+#define GPIO_BRR_BR1_Pos (1U)
+#define GPIO_BRR_BR1_Msk (0x1U << GPIO_BRR_BR1_Pos) /*!< 0x00000002 */
+#define GPIO_BRR_BR1 GPIO_BRR_BR1_Msk /*!< Port x Reset bit 1 */
+#define GPIO_BRR_BR2_Pos (2U)
+#define GPIO_BRR_BR2_Msk (0x1U << GPIO_BRR_BR2_Pos) /*!< 0x00000004 */
+#define GPIO_BRR_BR2 GPIO_BRR_BR2_Msk /*!< Port x Reset bit 2 */
+#define GPIO_BRR_BR3_Pos (3U)
+#define GPIO_BRR_BR3_Msk (0x1U << GPIO_BRR_BR3_Pos) /*!< 0x00000008 */
+#define GPIO_BRR_BR3 GPIO_BRR_BR3_Msk /*!< Port x Reset bit 3 */
+#define GPIO_BRR_BR4_Pos (4U)
+#define GPIO_BRR_BR4_Msk (0x1U << GPIO_BRR_BR4_Pos) /*!< 0x00000010 */
+#define GPIO_BRR_BR4 GPIO_BRR_BR4_Msk /*!< Port x Reset bit 4 */
+#define GPIO_BRR_BR5_Pos (5U)
+#define GPIO_BRR_BR5_Msk (0x1U << GPIO_BRR_BR5_Pos) /*!< 0x00000020 */
+#define GPIO_BRR_BR5 GPIO_BRR_BR5_Msk /*!< Port x Reset bit 5 */
+#define GPIO_BRR_BR6_Pos (6U)
+#define GPIO_BRR_BR6_Msk (0x1U << GPIO_BRR_BR6_Pos) /*!< 0x00000040 */
+#define GPIO_BRR_BR6 GPIO_BRR_BR6_Msk /*!< Port x Reset bit 6 */
+#define GPIO_BRR_BR7_Pos (7U)
+#define GPIO_BRR_BR7_Msk (0x1U << GPIO_BRR_BR7_Pos) /*!< 0x00000080 */
+#define GPIO_BRR_BR7 GPIO_BRR_BR7_Msk /*!< Port x Reset bit 7 */
+#define GPIO_BRR_BR8_Pos (8U)
+#define GPIO_BRR_BR8_Msk (0x1U << GPIO_BRR_BR8_Pos) /*!< 0x00000100 */
+#define GPIO_BRR_BR8 GPIO_BRR_BR8_Msk /*!< Port x Reset bit 8 */
+#define GPIO_BRR_BR9_Pos (9U)
+#define GPIO_BRR_BR9_Msk (0x1U << GPIO_BRR_BR9_Pos) /*!< 0x00000200 */
+#define GPIO_BRR_BR9 GPIO_BRR_BR9_Msk /*!< Port x Reset bit 9 */
+#define GPIO_BRR_BR10_Pos (10U)
+#define GPIO_BRR_BR10_Msk (0x1U << GPIO_BRR_BR10_Pos) /*!< 0x00000400 */
+#define GPIO_BRR_BR10 GPIO_BRR_BR10_Msk /*!< Port x Reset bit 10 */
+#define GPIO_BRR_BR11_Pos (11U)
+#define GPIO_BRR_BR11_Msk (0x1U << GPIO_BRR_BR11_Pos) /*!< 0x00000800 */
+#define GPIO_BRR_BR11 GPIO_BRR_BR11_Msk /*!< Port x Reset bit 11 */
+#define GPIO_BRR_BR12_Pos (12U)
+#define GPIO_BRR_BR12_Msk (0x1U << GPIO_BRR_BR12_Pos) /*!< 0x00001000 */
+#define GPIO_BRR_BR12 GPIO_BRR_BR12_Msk /*!< Port x Reset bit 12 */
+#define GPIO_BRR_BR13_Pos (13U)
+#define GPIO_BRR_BR13_Msk (0x1U << GPIO_BRR_BR13_Pos) /*!< 0x00002000 */
+#define GPIO_BRR_BR13 GPIO_BRR_BR13_Msk /*!< Port x Reset bit 13 */
+#define GPIO_BRR_BR14_Pos (14U)
+#define GPIO_BRR_BR14_Msk (0x1U << GPIO_BRR_BR14_Pos) /*!< 0x00004000 */
+#define GPIO_BRR_BR14 GPIO_BRR_BR14_Msk /*!< Port x Reset bit 14 */
+#define GPIO_BRR_BR15_Pos (15U)
+#define GPIO_BRR_BR15_Msk (0x1U << GPIO_BRR_BR15_Pos) /*!< 0x00008000 */
+#define GPIO_BRR_BR15 GPIO_BRR_BR15_Msk /*!< Port x Reset bit 15 */
+
+/****************** Bit definition for GPIO_LCKR register *******************/
+#define GPIO_LCKR_LCK0_Pos (0U)
+#define GPIO_LCKR_LCK0_Msk (0x1U << GPIO_LCKR_LCK0_Pos) /*!< 0x00000001 */
+#define GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk /*!< Port x Lock bit 0 */
+#define GPIO_LCKR_LCK1_Pos (1U)
+#define GPIO_LCKR_LCK1_Msk (0x1U << GPIO_LCKR_LCK1_Pos) /*!< 0x00000002 */
+#define GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk /*!< Port x Lock bit 1 */
+#define GPIO_LCKR_LCK2_Pos (2U)
+#define GPIO_LCKR_LCK2_Msk (0x1U << GPIO_LCKR_LCK2_Pos) /*!< 0x00000004 */
+#define GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk /*!< Port x Lock bit 2 */
+#define GPIO_LCKR_LCK3_Pos (3U)
+#define GPIO_LCKR_LCK3_Msk (0x1U << GPIO_LCKR_LCK3_Pos) /*!< 0x00000008 */
+#define GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk /*!< Port x Lock bit 3 */
+#define GPIO_LCKR_LCK4_Pos (4U)
+#define GPIO_LCKR_LCK4_Msk (0x1U << GPIO_LCKR_LCK4_Pos) /*!< 0x00000010 */
+#define GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk /*!< Port x Lock bit 4 */
+#define GPIO_LCKR_LCK5_Pos (5U)
+#define GPIO_LCKR_LCK5_Msk (0x1U << GPIO_LCKR_LCK5_Pos) /*!< 0x00000020 */
+#define GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk /*!< Port x Lock bit 5 */
+#define GPIO_LCKR_LCK6_Pos (6U)
+#define GPIO_LCKR_LCK6_Msk (0x1U << GPIO_LCKR_LCK6_Pos) /*!< 0x00000040 */
+#define GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk /*!< Port x Lock bit 6 */
+#define GPIO_LCKR_LCK7_Pos (7U)
+#define GPIO_LCKR_LCK7_Msk (0x1U << GPIO_LCKR_LCK7_Pos) /*!< 0x00000080 */
+#define GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk /*!< Port x Lock bit 7 */
+#define GPIO_LCKR_LCK8_Pos (8U)
+#define GPIO_LCKR_LCK8_Msk (0x1U << GPIO_LCKR_LCK8_Pos) /*!< 0x00000100 */
+#define GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk /*!< Port x Lock bit 8 */
+#define GPIO_LCKR_LCK9_Pos (9U)
+#define GPIO_LCKR_LCK9_Msk (0x1U << GPIO_LCKR_LCK9_Pos) /*!< 0x00000200 */
+#define GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk /*!< Port x Lock bit 9 */
+#define GPIO_LCKR_LCK10_Pos (10U)
+#define GPIO_LCKR_LCK10_Msk (0x1U << GPIO_LCKR_LCK10_Pos) /*!< 0x00000400 */
+#define GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk /*!< Port x Lock bit 10 */
+#define GPIO_LCKR_LCK11_Pos (11U)
+#define GPIO_LCKR_LCK11_Msk (0x1U << GPIO_LCKR_LCK11_Pos) /*!< 0x00000800 */
+#define GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk /*!< Port x Lock bit 11 */
+#define GPIO_LCKR_LCK12_Pos (12U)
+#define GPIO_LCKR_LCK12_Msk (0x1U << GPIO_LCKR_LCK12_Pos) /*!< 0x00001000 */
+#define GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk /*!< Port x Lock bit 12 */
+#define GPIO_LCKR_LCK13_Pos (13U)
+#define GPIO_LCKR_LCK13_Msk (0x1U << GPIO_LCKR_LCK13_Pos) /*!< 0x00002000 */
+#define GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk /*!< Port x Lock bit 13 */
+#define GPIO_LCKR_LCK14_Pos (14U)
+#define GPIO_LCKR_LCK14_Msk (0x1U << GPIO_LCKR_LCK14_Pos) /*!< 0x00004000 */
+#define GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk /*!< Port x Lock bit 14 */
+#define GPIO_LCKR_LCK15_Pos (15U)
+#define GPIO_LCKR_LCK15_Msk (0x1U << GPIO_LCKR_LCK15_Pos) /*!< 0x00008000 */
+#define GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk /*!< Port x Lock bit 15 */
+#define GPIO_LCKR_LCKK_Pos (16U)
+#define GPIO_LCKR_LCKK_Msk (0x1U << GPIO_LCKR_LCKK_Pos) /*!< 0x00010000 */
+#define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk /*!< Lock key */
+
+/*----------------------------------------------------------------------------*/
+
+/****************** Bit definition for AFIO_EVCR register *******************/
+#define AFIO_EVCR_PIN_Pos (0U)
+#define AFIO_EVCR_PIN_Msk (0xFU << AFIO_EVCR_PIN_Pos) /*!< 0x0000000F */
+#define AFIO_EVCR_PIN AFIO_EVCR_PIN_Msk /*!< PIN[3:0] bits (Pin selection) */
+#define AFIO_EVCR_PIN_0 (0x1U << AFIO_EVCR_PIN_Pos) /*!< 0x00000001 */
+#define AFIO_EVCR_PIN_1 (0x2U << AFIO_EVCR_PIN_Pos) /*!< 0x00000002 */
+#define AFIO_EVCR_PIN_2 (0x4U << AFIO_EVCR_PIN_Pos) /*!< 0x00000004 */
+#define AFIO_EVCR_PIN_3 (0x8U << AFIO_EVCR_PIN_Pos) /*!< 0x00000008 */
+
+/*!< PIN configuration */
+#define AFIO_EVCR_PIN_PX0 ((uint32_t)0x00000000) /*!< Pin 0 selected */
+#define AFIO_EVCR_PIN_PX1_Pos (0U)
+#define AFIO_EVCR_PIN_PX1_Msk (0x1U << AFIO_EVCR_PIN_PX1_Pos) /*!< 0x00000001 */
+#define AFIO_EVCR_PIN_PX1 AFIO_EVCR_PIN_PX1_Msk /*!< Pin 1 selected */
+#define AFIO_EVCR_PIN_PX2_Pos (1U)
+#define AFIO_EVCR_PIN_PX2_Msk (0x1U << AFIO_EVCR_PIN_PX2_Pos) /*!< 0x00000002 */
+#define AFIO_EVCR_PIN_PX2 AFIO_EVCR_PIN_PX2_Msk /*!< Pin 2 selected */
+#define AFIO_EVCR_PIN_PX3_Pos (0U)
+#define AFIO_EVCR_PIN_PX3_Msk (0x3U << AFIO_EVCR_PIN_PX3_Pos) /*!< 0x00000003 */
+#define AFIO_EVCR_PIN_PX3 AFIO_EVCR_PIN_PX3_Msk /*!< Pin 3 selected */
+#define AFIO_EVCR_PIN_PX4_Pos (2U)
+#define AFIO_EVCR_PIN_PX4_Msk (0x1U << AFIO_EVCR_PIN_PX4_Pos) /*!< 0x00000004 */
+#define AFIO_EVCR_PIN_PX4 AFIO_EVCR_PIN_PX4_Msk /*!< Pin 4 selected */
+#define AFIO_EVCR_PIN_PX5_Pos (0U)
+#define AFIO_EVCR_PIN_PX5_Msk (0x5U << AFIO_EVCR_PIN_PX5_Pos) /*!< 0x00000005 */
+#define AFIO_EVCR_PIN_PX5 AFIO_EVCR_PIN_PX5_Msk /*!< Pin 5 selected */
+#define AFIO_EVCR_PIN_PX6_Pos (1U)
+#define AFIO_EVCR_PIN_PX6_Msk (0x3U << AFIO_EVCR_PIN_PX6_Pos) /*!< 0x00000006 */
+#define AFIO_EVCR_PIN_PX6 AFIO_EVCR_PIN_PX6_Msk /*!< Pin 6 selected */
+#define AFIO_EVCR_PIN_PX7_Pos (0U)
+#define AFIO_EVCR_PIN_PX7_Msk (0x7U << AFIO_EVCR_PIN_PX7_Pos) /*!< 0x00000007 */
+#define AFIO_EVCR_PIN_PX7 AFIO_EVCR_PIN_PX7_Msk /*!< Pin 7 selected */
+#define AFIO_EVCR_PIN_PX8_Pos (3U)
+#define AFIO_EVCR_PIN_PX8_Msk (0x1U << AFIO_EVCR_PIN_PX8_Pos) /*!< 0x00000008 */
+#define AFIO_EVCR_PIN_PX8 AFIO_EVCR_PIN_PX8_Msk /*!< Pin 8 selected */
+#define AFIO_EVCR_PIN_PX9_Pos (0U)
+#define AFIO_EVCR_PIN_PX9_Msk (0x9U << AFIO_EVCR_PIN_PX9_Pos) /*!< 0x00000009 */
+#define AFIO_EVCR_PIN_PX9 AFIO_EVCR_PIN_PX9_Msk /*!< Pin 9 selected */
+#define AFIO_EVCR_PIN_PX10_Pos (1U)
+#define AFIO_EVCR_PIN_PX10_Msk (0x5U << AFIO_EVCR_PIN_PX10_Pos) /*!< 0x0000000A */
+#define AFIO_EVCR_PIN_PX10 AFIO_EVCR_PIN_PX10_Msk /*!< Pin 10 selected */
+#define AFIO_EVCR_PIN_PX11_Pos (0U)
+#define AFIO_EVCR_PIN_PX11_Msk (0xBU << AFIO_EVCR_PIN_PX11_Pos) /*!< 0x0000000B */
+#define AFIO_EVCR_PIN_PX11 AFIO_EVCR_PIN_PX11_Msk /*!< Pin 11 selected */
+#define AFIO_EVCR_PIN_PX12_Pos (2U)
+#define AFIO_EVCR_PIN_PX12_Msk (0x3U << AFIO_EVCR_PIN_PX12_Pos) /*!< 0x0000000C */
+#define AFIO_EVCR_PIN_PX12 AFIO_EVCR_PIN_PX12_Msk /*!< Pin 12 selected */
+#define AFIO_EVCR_PIN_PX13_Pos (0U)
+#define AFIO_EVCR_PIN_PX13_Msk (0xDU << AFIO_EVCR_PIN_PX13_Pos) /*!< 0x0000000D */
+#define AFIO_EVCR_PIN_PX13 AFIO_EVCR_PIN_PX13_Msk /*!< Pin 13 selected */
+#define AFIO_EVCR_PIN_PX14_Pos (1U)
+#define AFIO_EVCR_PIN_PX14_Msk (0x7U << AFIO_EVCR_PIN_PX14_Pos) /*!< 0x0000000E */
+#define AFIO_EVCR_PIN_PX14 AFIO_EVCR_PIN_PX14_Msk /*!< Pin 14 selected */
+#define AFIO_EVCR_PIN_PX15_Pos (0U)
+#define AFIO_EVCR_PIN_PX15_Msk (0xFU << AFIO_EVCR_PIN_PX15_Pos) /*!< 0x0000000F */
+#define AFIO_EVCR_PIN_PX15 AFIO_EVCR_PIN_PX15_Msk /*!< Pin 15 selected */
+
+#define AFIO_EVCR_PORT_Pos (4U)
+#define AFIO_EVCR_PORT_Msk (0x7U << AFIO_EVCR_PORT_Pos) /*!< 0x00000070 */
+#define AFIO_EVCR_PORT AFIO_EVCR_PORT_Msk /*!< PORT[2:0] bits (Port selection) */
+#define AFIO_EVCR_PORT_0 (0x1U << AFIO_EVCR_PORT_Pos) /*!< 0x00000010 */
+#define AFIO_EVCR_PORT_1 (0x2U << AFIO_EVCR_PORT_Pos) /*!< 0x00000020 */
+#define AFIO_EVCR_PORT_2 (0x4U << AFIO_EVCR_PORT_Pos) /*!< 0x00000040 */
+
+/*!< PORT configuration */
+#define AFIO_EVCR_PORT_PA ((uint32_t)0x00000000) /*!< Port A selected */
+#define AFIO_EVCR_PORT_PB_Pos (4U)
+#define AFIO_EVCR_PORT_PB_Msk (0x1U << AFIO_EVCR_PORT_PB_Pos) /*!< 0x00000010 */
+#define AFIO_EVCR_PORT_PB AFIO_EVCR_PORT_PB_Msk /*!< Port B selected */
+#define AFIO_EVCR_PORT_PC_Pos (5U)
+#define AFIO_EVCR_PORT_PC_Msk (0x1U << AFIO_EVCR_PORT_PC_Pos) /*!< 0x00000020 */
+#define AFIO_EVCR_PORT_PC AFIO_EVCR_PORT_PC_Msk /*!< Port C selected */
+#define AFIO_EVCR_PORT_PD_Pos (4U)
+#define AFIO_EVCR_PORT_PD_Msk (0x3U << AFIO_EVCR_PORT_PD_Pos) /*!< 0x00000030 */
+#define AFIO_EVCR_PORT_PD AFIO_EVCR_PORT_PD_Msk /*!< Port D selected */
+#define AFIO_EVCR_PORT_PE_Pos (6U)
+#define AFIO_EVCR_PORT_PE_Msk (0x1U << AFIO_EVCR_PORT_PE_Pos) /*!< 0x00000040 */
+#define AFIO_EVCR_PORT_PE AFIO_EVCR_PORT_PE_Msk /*!< Port E selected */
+
+#define AFIO_EVCR_EVOE_Pos (7U)
+#define AFIO_EVCR_EVOE_Msk (0x1U << AFIO_EVCR_EVOE_Pos) /*!< 0x00000080 */
+#define AFIO_EVCR_EVOE AFIO_EVCR_EVOE_Msk /*!< Event Output Enable */
+
+/****************** Bit definition for AFIO_MAPR register *******************/
+#define AFIO_MAPR_SPI1_REMAP_Pos (0U)
+#define AFIO_MAPR_SPI1_REMAP_Msk (0x1U << AFIO_MAPR_SPI1_REMAP_Pos) /*!< 0x00000001 */
+#define AFIO_MAPR_SPI1_REMAP AFIO_MAPR_SPI1_REMAP_Msk /*!< SPI1 remapping */
+#define AFIO_MAPR_I2C1_REMAP_Pos (1U)
+#define AFIO_MAPR_I2C1_REMAP_Msk (0x1U << AFIO_MAPR_I2C1_REMAP_Pos) /*!< 0x00000002 */
+#define AFIO_MAPR_I2C1_REMAP AFIO_MAPR_I2C1_REMAP_Msk /*!< I2C1 remapping */
+#define AFIO_MAPR_USART1_REMAP_Pos (2U)
+#define AFIO_MAPR_USART1_REMAP_Msk (0x1U << AFIO_MAPR_USART1_REMAP_Pos) /*!< 0x00000004 */
+#define AFIO_MAPR_USART1_REMAP AFIO_MAPR_USART1_REMAP_Msk /*!< USART1 remapping */
+#define AFIO_MAPR_USART2_REMAP_Pos (3U)
+#define AFIO_MAPR_USART2_REMAP_Msk (0x1U << AFIO_MAPR_USART2_REMAP_Pos) /*!< 0x00000008 */
+#define AFIO_MAPR_USART2_REMAP AFIO_MAPR_USART2_REMAP_Msk /*!< USART2 remapping */
+
+#define AFIO_MAPR_USART3_REMAP_Pos (4U)
+#define AFIO_MAPR_USART3_REMAP_Msk (0x3U << AFIO_MAPR_USART3_REMAP_Pos) /*!< 0x00000030 */
+#define AFIO_MAPR_USART3_REMAP AFIO_MAPR_USART3_REMAP_Msk /*!< USART3_REMAP[1:0] bits (USART3 remapping) */
+#define AFIO_MAPR_USART3_REMAP_0 (0x1U << AFIO_MAPR_USART3_REMAP_Pos) /*!< 0x00000010 */
+#define AFIO_MAPR_USART3_REMAP_1 (0x2U << AFIO_MAPR_USART3_REMAP_Pos) /*!< 0x00000020 */
+
+/* USART3_REMAP configuration */
+#define AFIO_MAPR_USART3_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14) */
+#define AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Pos (4U)
+#define AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Msk (0x1U << AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Pos) /*!< 0x00000010 */
+#define AFIO_MAPR_USART3_REMAP_PARTIALREMAP AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Msk /*!< Partial remap (TX/PC10, RX/PC11, CK/PC12, CTS/PB13, RTS/PB14) */
+#define AFIO_MAPR_USART3_REMAP_FULLREMAP_Pos (4U)
+#define AFIO_MAPR_USART3_REMAP_FULLREMAP_Msk (0x3U << AFIO_MAPR_USART3_REMAP_FULLREMAP_Pos) /*!< 0x00000030 */
+#define AFIO_MAPR_USART3_REMAP_FULLREMAP AFIO_MAPR_USART3_REMAP_FULLREMAP_Msk /*!< Full remap (TX/PD8, RX/PD9, CK/PD10, CTS/PD11, RTS/PD12) */
+
+#define AFIO_MAPR_TIM1_REMAP_Pos (6U)
+#define AFIO_MAPR_TIM1_REMAP_Msk (0x3U << AFIO_MAPR_TIM1_REMAP_Pos) /*!< 0x000000C0 */
+#define AFIO_MAPR_TIM1_REMAP AFIO_MAPR_TIM1_REMAP_Msk /*!< TIM1_REMAP[1:0] bits (TIM1 remapping) */
+#define AFIO_MAPR_TIM1_REMAP_0 (0x1U << AFIO_MAPR_TIM1_REMAP_Pos) /*!< 0x00000040 */
+#define AFIO_MAPR_TIM1_REMAP_1 (0x2U << AFIO_MAPR_TIM1_REMAP_Pos) /*!< 0x00000080 */
+
+/*!< TIM1_REMAP configuration */
+#define AFIO_MAPR_TIM1_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15) */
+#define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Pos (6U)
+#define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Msk (0x1U << AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Pos) /*!< 0x00000040 */
+#define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Msk /*!< Partial remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PA6, CH1N/PA7, CH2N/PB0, CH3N/PB1) */
+#define AFIO_MAPR_TIM1_REMAP_FULLREMAP_Pos (6U)
+#define AFIO_MAPR_TIM1_REMAP_FULLREMAP_Msk (0x3U << AFIO_MAPR_TIM1_REMAP_FULLREMAP_Pos) /*!< 0x000000C0 */
+#define AFIO_MAPR_TIM1_REMAP_FULLREMAP AFIO_MAPR_TIM1_REMAP_FULLREMAP_Msk /*!< Full remap (ETR/PE7, CH1/PE9, CH2/PE11, CH3/PE13, CH4/PE14, BKIN/PE15, CH1N/PE8, CH2N/PE10, CH3N/PE12) */
+
+#define AFIO_MAPR_TIM2_REMAP_Pos (8U)
+#define AFIO_MAPR_TIM2_REMAP_Msk (0x3U << AFIO_MAPR_TIM2_REMAP_Pos) /*!< 0x00000300 */
+#define AFIO_MAPR_TIM2_REMAP AFIO_MAPR_TIM2_REMAP_Msk /*!< TIM2_REMAP[1:0] bits (TIM2 remapping) */
+#define AFIO_MAPR_TIM2_REMAP_0 (0x1U << AFIO_MAPR_TIM2_REMAP_Pos) /*!< 0x00000100 */
+#define AFIO_MAPR_TIM2_REMAP_1 (0x2U << AFIO_MAPR_TIM2_REMAP_Pos) /*!< 0x00000200 */
+
+/*!< TIM2_REMAP configuration */
+#define AFIO_MAPR_TIM2_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3) */
+#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Pos (8U)
+#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Msk (0x1U << AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Pos) /*!< 0x00000100 */
+#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1 AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Msk /*!< Partial remap (CH1/ETR/PA15, CH2/PB3, CH3/PA2, CH4/PA3) */
+#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2_Pos (9U)
+#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2_Msk (0x1U << AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2_Pos) /*!< 0x00000200 */
+#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2 AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2_Msk /*!< Partial remap (CH1/ETR/PA0, CH2/PA1, CH3/PB10, CH4/PB11) */
+#define AFIO_MAPR_TIM2_REMAP_FULLREMAP_Pos (8U)
+#define AFIO_MAPR_TIM2_REMAP_FULLREMAP_Msk (0x3U << AFIO_MAPR_TIM2_REMAP_FULLREMAP_Pos) /*!< 0x00000300 */
+#define AFIO_MAPR_TIM2_REMAP_FULLREMAP AFIO_MAPR_TIM2_REMAP_FULLREMAP_Msk /*!< Full remap (CH1/ETR/PA15, CH2/PB3, CH3/PB10, CH4/PB11) */
+
+#define AFIO_MAPR_TIM3_REMAP_Pos (10U)
+#define AFIO_MAPR_TIM3_REMAP_Msk (0x3U << AFIO_MAPR_TIM3_REMAP_Pos) /*!< 0x00000C00 */
+#define AFIO_MAPR_TIM3_REMAP AFIO_MAPR_TIM3_REMAP_Msk /*!< TIM3_REMAP[1:0] bits (TIM3 remapping) */
+#define AFIO_MAPR_TIM3_REMAP_0 (0x1U << AFIO_MAPR_TIM3_REMAP_Pos) /*!< 0x00000400 */
+#define AFIO_MAPR_TIM3_REMAP_1 (0x2U << AFIO_MAPR_TIM3_REMAP_Pos) /*!< 0x00000800 */
+
+/*!< TIM3_REMAP configuration */
+#define AFIO_MAPR_TIM3_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1) */
+#define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Pos (11U)
+#define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Msk (0x1U << AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Pos) /*!< 0x00000800 */
+#define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Msk /*!< Partial remap (CH1/PB4, CH2/PB5, CH3/PB0, CH4/PB1) */
+#define AFIO_MAPR_TIM3_REMAP_FULLREMAP_Pos (10U)
+#define AFIO_MAPR_TIM3_REMAP_FULLREMAP_Msk (0x3U << AFIO_MAPR_TIM3_REMAP_FULLREMAP_Pos) /*!< 0x00000C00 */
+#define AFIO_MAPR_TIM3_REMAP_FULLREMAP AFIO_MAPR_TIM3_REMAP_FULLREMAP_Msk /*!< Full remap (CH1/PC6, CH2/PC7, CH3/PC8, CH4/PC9) */
+
+#define AFIO_MAPR_TIM4_REMAP_Pos (12U)
+#define AFIO_MAPR_TIM4_REMAP_Msk (0x1U << AFIO_MAPR_TIM4_REMAP_Pos) /*!< 0x00001000 */
+#define AFIO_MAPR_TIM4_REMAP AFIO_MAPR_TIM4_REMAP_Msk /*!< TIM4_REMAP bit (TIM4 remapping) */
+
+#define AFIO_MAPR_CAN_REMAP_Pos (13U)
+#define AFIO_MAPR_CAN_REMAP_Msk (0x3U << AFIO_MAPR_CAN_REMAP_Pos) /*!< 0x00006000 */
+#define AFIO_MAPR_CAN_REMAP AFIO_MAPR_CAN_REMAP_Msk /*!< CAN_REMAP[1:0] bits (CAN Alternate function remapping) */
+#define AFIO_MAPR_CAN_REMAP_0 (0x1U << AFIO_MAPR_CAN_REMAP_Pos) /*!< 0x00002000 */
+#define AFIO_MAPR_CAN_REMAP_1 (0x2U << AFIO_MAPR_CAN_REMAP_Pos) /*!< 0x00004000 */
+
+/*!< CAN_REMAP configuration */
+#define AFIO_MAPR_CAN_REMAP_REMAP1 ((uint32_t)0x00000000) /*!< CANRX mapped to PA11, CANTX mapped to PA12 */
+#define AFIO_MAPR_CAN_REMAP_REMAP2_Pos (14U)
+#define AFIO_MAPR_CAN_REMAP_REMAP2_Msk (0x1U << AFIO_MAPR_CAN_REMAP_REMAP2_Pos) /*!< 0x00004000 */
+#define AFIO_MAPR_CAN_REMAP_REMAP2 AFIO_MAPR_CAN_REMAP_REMAP2_Msk /*!< CANRX mapped to PB8, CANTX mapped to PB9 */
+#define AFIO_MAPR_CAN_REMAP_REMAP3_Pos (13U)
+#define AFIO_MAPR_CAN_REMAP_REMAP3_Msk (0x3U << AFIO_MAPR_CAN_REMAP_REMAP3_Pos) /*!< 0x00006000 */
+#define AFIO_MAPR_CAN_REMAP_REMAP3 AFIO_MAPR_CAN_REMAP_REMAP3_Msk /*!< CANRX mapped to PD0, CANTX mapped to PD1 */
+
+#define AFIO_MAPR_PD01_REMAP_Pos (15U)
+#define AFIO_MAPR_PD01_REMAP_Msk (0x1U << AFIO_MAPR_PD01_REMAP_Pos) /*!< 0x00008000 */
+#define AFIO_MAPR_PD01_REMAP AFIO_MAPR_PD01_REMAP_Msk /*!< Port D0/Port D1 mapping on OSC_IN/OSC_OUT */
+
+/*!< SWJ_CFG configuration */
+#define AFIO_MAPR_SWJ_CFG_Pos (24U)
+#define AFIO_MAPR_SWJ_CFG_Msk (0x7U << AFIO_MAPR_SWJ_CFG_Pos) /*!< 0x07000000 */
+#define AFIO_MAPR_SWJ_CFG AFIO_MAPR_SWJ_CFG_Msk /*!< SWJ_CFG[2:0] bits (Serial Wire JTAG configuration) */
+#define AFIO_MAPR_SWJ_CFG_0 (0x1U << AFIO_MAPR_SWJ_CFG_Pos) /*!< 0x01000000 */
+#define AFIO_MAPR_SWJ_CFG_1 (0x2U << AFIO_MAPR_SWJ_CFG_Pos) /*!< 0x02000000 */
+#define AFIO_MAPR_SWJ_CFG_2 (0x4U << AFIO_MAPR_SWJ_CFG_Pos) /*!< 0x04000000 */
+
+#define AFIO_MAPR_SWJ_CFG_RESET ((uint32_t)0x00000000) /*!< Full SWJ (JTAG-DP + SW-DP) : Reset State */
+#define AFIO_MAPR_SWJ_CFG_NOJNTRST_Pos (24U)
+#define AFIO_MAPR_SWJ_CFG_NOJNTRST_Msk (0x1U << AFIO_MAPR_SWJ_CFG_NOJNTRST_Pos) /*!< 0x01000000 */
+#define AFIO_MAPR_SWJ_CFG_NOJNTRST AFIO_MAPR_SWJ_CFG_NOJNTRST_Msk /*!< Full SWJ (JTAG-DP + SW-DP) but without JNTRST */
+#define AFIO_MAPR_SWJ_CFG_JTAGDISABLE_Pos (25U)
+#define AFIO_MAPR_SWJ_CFG_JTAGDISABLE_Msk (0x1U << AFIO_MAPR_SWJ_CFG_JTAGDISABLE_Pos) /*!< 0x02000000 */
+#define AFIO_MAPR_SWJ_CFG_JTAGDISABLE AFIO_MAPR_SWJ_CFG_JTAGDISABLE_Msk /*!< JTAG-DP Disabled and SW-DP Enabled */
+#define AFIO_MAPR_SWJ_CFG_DISABLE_Pos (26U)
+#define AFIO_MAPR_SWJ_CFG_DISABLE_Msk (0x1U << AFIO_MAPR_SWJ_CFG_DISABLE_Pos) /*!< 0x04000000 */
+#define AFIO_MAPR_SWJ_CFG_DISABLE AFIO_MAPR_SWJ_CFG_DISABLE_Msk /*!< JTAG-DP Disabled and SW-DP Disabled */
+
+
+/***************** Bit definition for AFIO_EXTICR1 register *****************/
+#define AFIO_EXTICR1_EXTI0_Pos (0U)
+#define AFIO_EXTICR1_EXTI0_Msk (0xFU << AFIO_EXTICR1_EXTI0_Pos) /*!< 0x0000000F */
+#define AFIO_EXTICR1_EXTI0 AFIO_EXTICR1_EXTI0_Msk /*!< EXTI 0 configuration */
+#define AFIO_EXTICR1_EXTI1_Pos (4U)
+#define AFIO_EXTICR1_EXTI1_Msk (0xFU << AFIO_EXTICR1_EXTI1_Pos) /*!< 0x000000F0 */
+#define AFIO_EXTICR1_EXTI1 AFIO_EXTICR1_EXTI1_Msk /*!< EXTI 1 configuration */
+#define AFIO_EXTICR1_EXTI2_Pos (8U)
+#define AFIO_EXTICR1_EXTI2_Msk (0xFU << AFIO_EXTICR1_EXTI2_Pos) /*!< 0x00000F00 */
+#define AFIO_EXTICR1_EXTI2 AFIO_EXTICR1_EXTI2_Msk /*!< EXTI 2 configuration */
+#define AFIO_EXTICR1_EXTI3_Pos (12U)
+#define AFIO_EXTICR1_EXTI3_Msk (0xFU << AFIO_EXTICR1_EXTI3_Pos) /*!< 0x0000F000 */
+#define AFIO_EXTICR1_EXTI3 AFIO_EXTICR1_EXTI3_Msk /*!< EXTI 3 configuration */
+
+/*!< EXTI0 configuration */
+#define AFIO_EXTICR1_EXTI0_PA ((uint32_t)0x00000000) /*!< PA[0] pin */
+#define AFIO_EXTICR1_EXTI0_PB_Pos (0U)
+#define AFIO_EXTICR1_EXTI0_PB_Msk (0x1U << AFIO_EXTICR1_EXTI0_PB_Pos) /*!< 0x00000001 */
+#define AFIO_EXTICR1_EXTI0_PB AFIO_EXTICR1_EXTI0_PB_Msk /*!< PB[0] pin */
+#define AFIO_EXTICR1_EXTI0_PC_Pos (1U)
+#define AFIO_EXTICR1_EXTI0_PC_Msk (0x1U << AFIO_EXTICR1_EXTI0_PC_Pos) /*!< 0x00000002 */
+#define AFIO_EXTICR1_EXTI0_PC AFIO_EXTICR1_EXTI0_PC_Msk /*!< PC[0] pin */
+#define AFIO_EXTICR1_EXTI0_PD_Pos (0U)
+#define AFIO_EXTICR1_EXTI0_PD_Msk (0x3U << AFIO_EXTICR1_EXTI0_PD_Pos) /*!< 0x00000003 */
+#define AFIO_EXTICR1_EXTI0_PD AFIO_EXTICR1_EXTI0_PD_Msk /*!< PD[0] pin */
+#define AFIO_EXTICR1_EXTI0_PE_Pos (2U)
+#define AFIO_EXTICR1_EXTI0_PE_Msk (0x1U << AFIO_EXTICR1_EXTI0_PE_Pos) /*!< 0x00000004 */
+#define AFIO_EXTICR1_EXTI0_PE AFIO_EXTICR1_EXTI0_PE_Msk /*!< PE[0] pin */
+#define AFIO_EXTICR1_EXTI0_PF_Pos (0U)
+#define AFIO_EXTICR1_EXTI0_PF_Msk (0x5U << AFIO_EXTICR1_EXTI0_PF_Pos) /*!< 0x00000005 */
+#define AFIO_EXTICR1_EXTI0_PF AFIO_EXTICR1_EXTI0_PF_Msk /*!< PF[0] pin */
+#define AFIO_EXTICR1_EXTI0_PG_Pos (1U)
+#define AFIO_EXTICR1_EXTI0_PG_Msk (0x3U << AFIO_EXTICR1_EXTI0_PG_Pos) /*!< 0x00000006 */
+#define AFIO_EXTICR1_EXTI0_PG AFIO_EXTICR1_EXTI0_PG_Msk /*!< PG[0] pin */
+
+/*!< EXTI1 configuration */
+#define AFIO_EXTICR1_EXTI1_PA ((uint32_t)0x00000000) /*!< PA[1] pin */
+#define AFIO_EXTICR1_EXTI1_PB_Pos (4U)
+#define AFIO_EXTICR1_EXTI1_PB_Msk (0x1U << AFIO_EXTICR1_EXTI1_PB_Pos) /*!< 0x00000010 */
+#define AFIO_EXTICR1_EXTI1_PB AFIO_EXTICR1_EXTI1_PB_Msk /*!< PB[1] pin */
+#define AFIO_EXTICR1_EXTI1_PC_Pos (5U)
+#define AFIO_EXTICR1_EXTI1_PC_Msk (0x1U << AFIO_EXTICR1_EXTI1_PC_Pos) /*!< 0x00000020 */
+#define AFIO_EXTICR1_EXTI1_PC AFIO_EXTICR1_EXTI1_PC_Msk /*!< PC[1] pin */
+#define AFIO_EXTICR1_EXTI1_PD_Pos (4U)
+#define AFIO_EXTICR1_EXTI1_PD_Msk (0x3U << AFIO_EXTICR1_EXTI1_PD_Pos) /*!< 0x00000030 */
+#define AFIO_EXTICR1_EXTI1_PD AFIO_EXTICR1_EXTI1_PD_Msk /*!< PD[1] pin */
+#define AFIO_EXTICR1_EXTI1_PE_Pos (6U)
+#define AFIO_EXTICR1_EXTI1_PE_Msk (0x1U << AFIO_EXTICR1_EXTI1_PE_Pos) /*!< 0x00000040 */
+#define AFIO_EXTICR1_EXTI1_PE AFIO_EXTICR1_EXTI1_PE_Msk /*!< PE[1] pin */
+#define AFIO_EXTICR1_EXTI1_PF_Pos (4U)
+#define AFIO_EXTICR1_EXTI1_PF_Msk (0x5U << AFIO_EXTICR1_EXTI1_PF_Pos) /*!< 0x00000050 */
+#define AFIO_EXTICR1_EXTI1_PF AFIO_EXTICR1_EXTI1_PF_Msk /*!< PF[1] pin */
+#define AFIO_EXTICR1_EXTI1_PG_Pos (5U)
+#define AFIO_EXTICR1_EXTI1_PG_Msk (0x3U << AFIO_EXTICR1_EXTI1_PG_Pos) /*!< 0x00000060 */
+#define AFIO_EXTICR1_EXTI1_PG AFIO_EXTICR1_EXTI1_PG_Msk /*!< PG[1] pin */
+
+/*!< EXTI2 configuration */
+#define AFIO_EXTICR1_EXTI2_PA ((uint32_t)0x00000000) /*!< PA[2] pin */
+#define AFIO_EXTICR1_EXTI2_PB_Pos (8U)
+#define AFIO_EXTICR1_EXTI2_PB_Msk (0x1U << AFIO_EXTICR1_EXTI2_PB_Pos) /*!< 0x00000100 */
+#define AFIO_EXTICR1_EXTI2_PB AFIO_EXTICR1_EXTI2_PB_Msk /*!< PB[2] pin */
+#define AFIO_EXTICR1_EXTI2_PC_Pos (9U)
+#define AFIO_EXTICR1_EXTI2_PC_Msk (0x1U << AFIO_EXTICR1_EXTI2_PC_Pos) /*!< 0x00000200 */
+#define AFIO_EXTICR1_EXTI2_PC AFIO_EXTICR1_EXTI2_PC_Msk /*!< PC[2] pin */
+#define AFIO_EXTICR1_EXTI2_PD_Pos (8U)
+#define AFIO_EXTICR1_EXTI2_PD_Msk (0x3U << AFIO_EXTICR1_EXTI2_PD_Pos) /*!< 0x00000300 */
+#define AFIO_EXTICR1_EXTI2_PD AFIO_EXTICR1_EXTI2_PD_Msk /*!< PD[2] pin */
+#define AFIO_EXTICR1_EXTI2_PE_Pos (10U)
+#define AFIO_EXTICR1_EXTI2_PE_Msk (0x1U << AFIO_EXTICR1_EXTI2_PE_Pos) /*!< 0x00000400 */
+#define AFIO_EXTICR1_EXTI2_PE AFIO_EXTICR1_EXTI2_PE_Msk /*!< PE[2] pin */
+#define AFIO_EXTICR1_EXTI2_PF_Pos (8U)
+#define AFIO_EXTICR1_EXTI2_PF_Msk (0x5U << AFIO_EXTICR1_EXTI2_PF_Pos) /*!< 0x00000500 */
+#define AFIO_EXTICR1_EXTI2_PF AFIO_EXTICR1_EXTI2_PF_Msk /*!< PF[2] pin */
+#define AFIO_EXTICR1_EXTI2_PG_Pos (9U)
+#define AFIO_EXTICR1_EXTI2_PG_Msk (0x3U << AFIO_EXTICR1_EXTI2_PG_Pos) /*!< 0x00000600 */
+#define AFIO_EXTICR1_EXTI2_PG AFIO_EXTICR1_EXTI2_PG_Msk /*!< PG[2] pin */
+
+/*!< EXTI3 configuration */
+#define AFIO_EXTICR1_EXTI3_PA ((uint32_t)0x00000000) /*!< PA[3] pin */
+#define AFIO_EXTICR1_EXTI3_PB_Pos (12U)
+#define AFIO_EXTICR1_EXTI3_PB_Msk (0x1U << AFIO_EXTICR1_EXTI3_PB_Pos) /*!< 0x00001000 */
+#define AFIO_EXTICR1_EXTI3_PB AFIO_EXTICR1_EXTI3_PB_Msk /*!< PB[3] pin */
+#define AFIO_EXTICR1_EXTI3_PC_Pos (13U)
+#define AFIO_EXTICR1_EXTI3_PC_Msk (0x1U << AFIO_EXTICR1_EXTI3_PC_Pos) /*!< 0x00002000 */
+#define AFIO_EXTICR1_EXTI3_PC AFIO_EXTICR1_EXTI3_PC_Msk /*!< PC[3] pin */
+#define AFIO_EXTICR1_EXTI3_PD_Pos (12U)
+#define AFIO_EXTICR1_EXTI3_PD_Msk (0x3U << AFIO_EXTICR1_EXTI3_PD_Pos) /*!< 0x00003000 */
+#define AFIO_EXTICR1_EXTI3_PD AFIO_EXTICR1_EXTI3_PD_Msk /*!< PD[3] pin */
+#define AFIO_EXTICR1_EXTI3_PE_Pos (14U)
+#define AFIO_EXTICR1_EXTI3_PE_Msk (0x1U << AFIO_EXTICR1_EXTI3_PE_Pos) /*!< 0x00004000 */
+#define AFIO_EXTICR1_EXTI3_PE AFIO_EXTICR1_EXTI3_PE_Msk /*!< PE[3] pin */
+#define AFIO_EXTICR1_EXTI3_PF_Pos (12U)
+#define AFIO_EXTICR1_EXTI3_PF_Msk (0x5U << AFIO_EXTICR1_EXTI3_PF_Pos) /*!< 0x00005000 */
+#define AFIO_EXTICR1_EXTI3_PF AFIO_EXTICR1_EXTI3_PF_Msk /*!< PF[3] pin */
+#define AFIO_EXTICR1_EXTI3_PG_Pos (13U)
+#define AFIO_EXTICR1_EXTI3_PG_Msk (0x3U << AFIO_EXTICR1_EXTI3_PG_Pos) /*!< 0x00006000 */
+#define AFIO_EXTICR1_EXTI3_PG AFIO_EXTICR1_EXTI3_PG_Msk /*!< PG[3] pin */
+
+/***************** Bit definition for AFIO_EXTICR2 register *****************/
+#define AFIO_EXTICR2_EXTI4_Pos (0U)
+#define AFIO_EXTICR2_EXTI4_Msk (0xFU << AFIO_EXTICR2_EXTI4_Pos) /*!< 0x0000000F */
+#define AFIO_EXTICR2_EXTI4 AFIO_EXTICR2_EXTI4_Msk /*!< EXTI 4 configuration */
+#define AFIO_EXTICR2_EXTI5_Pos (4U)
+#define AFIO_EXTICR2_EXTI5_Msk (0xFU << AFIO_EXTICR2_EXTI5_Pos) /*!< 0x000000F0 */
+#define AFIO_EXTICR2_EXTI5 AFIO_EXTICR2_EXTI5_Msk /*!< EXTI 5 configuration */
+#define AFIO_EXTICR2_EXTI6_Pos (8U)
+#define AFIO_EXTICR2_EXTI6_Msk (0xFU << AFIO_EXTICR2_EXTI6_Pos) /*!< 0x00000F00 */
+#define AFIO_EXTICR2_EXTI6 AFIO_EXTICR2_EXTI6_Msk /*!< EXTI 6 configuration */
+#define AFIO_EXTICR2_EXTI7_Pos (12U)
+#define AFIO_EXTICR2_EXTI7_Msk (0xFU << AFIO_EXTICR2_EXTI7_Pos) /*!< 0x0000F000 */
+#define AFIO_EXTICR2_EXTI7 AFIO_EXTICR2_EXTI7_Msk /*!< EXTI 7 configuration */
+
+/*!< EXTI4 configuration */
+#define AFIO_EXTICR2_EXTI4_PA ((uint32_t)0x00000000) /*!< PA[4] pin */
+#define AFIO_EXTICR2_EXTI4_PB_Pos (0U)
+#define AFIO_EXTICR2_EXTI4_PB_Msk (0x1U << AFIO_EXTICR2_EXTI4_PB_Pos) /*!< 0x00000001 */
+#define AFIO_EXTICR2_EXTI4_PB AFIO_EXTICR2_EXTI4_PB_Msk /*!< PB[4] pin */
+#define AFIO_EXTICR2_EXTI4_PC_Pos (1U)
+#define AFIO_EXTICR2_EXTI4_PC_Msk (0x1U << AFIO_EXTICR2_EXTI4_PC_Pos) /*!< 0x00000002 */
+#define AFIO_EXTICR2_EXTI4_PC AFIO_EXTICR2_EXTI4_PC_Msk /*!< PC[4] pin */
+#define AFIO_EXTICR2_EXTI4_PD_Pos (0U)
+#define AFIO_EXTICR2_EXTI4_PD_Msk (0x3U << AFIO_EXTICR2_EXTI4_PD_Pos) /*!< 0x00000003 */
+#define AFIO_EXTICR2_EXTI4_PD AFIO_EXTICR2_EXTI4_PD_Msk /*!< PD[4] pin */
+#define AFIO_EXTICR2_EXTI4_PE_Pos (2U)
+#define AFIO_EXTICR2_EXTI4_PE_Msk (0x1U << AFIO_EXTICR2_EXTI4_PE_Pos) /*!< 0x00000004 */
+#define AFIO_EXTICR2_EXTI4_PE AFIO_EXTICR2_EXTI4_PE_Msk /*!< PE[4] pin */
+#define AFIO_EXTICR2_EXTI4_PF_Pos (0U)
+#define AFIO_EXTICR2_EXTI4_PF_Msk (0x5U << AFIO_EXTICR2_EXTI4_PF_Pos) /*!< 0x00000005 */
+#define AFIO_EXTICR2_EXTI4_PF AFIO_EXTICR2_EXTI4_PF_Msk /*!< PF[4] pin */
+#define AFIO_EXTICR2_EXTI4_PG_Pos (1U)
+#define AFIO_EXTICR2_EXTI4_PG_Msk (0x3U << AFIO_EXTICR2_EXTI4_PG_Pos) /*!< 0x00000006 */
+#define AFIO_EXTICR2_EXTI4_PG AFIO_EXTICR2_EXTI4_PG_Msk /*!< PG[4] pin */
+
+/* EXTI5 configuration */
+#define AFIO_EXTICR2_EXTI5_PA ((uint32_t)0x00000000) /*!< PA[5] pin */
+#define AFIO_EXTICR2_EXTI5_PB_Pos (4U)
+#define AFIO_EXTICR2_EXTI5_PB_Msk (0x1U << AFIO_EXTICR2_EXTI5_PB_Pos) /*!< 0x00000010 */
+#define AFIO_EXTICR2_EXTI5_PB AFIO_EXTICR2_EXTI5_PB_Msk /*!< PB[5] pin */
+#define AFIO_EXTICR2_EXTI5_PC_Pos (5U)
+#define AFIO_EXTICR2_EXTI5_PC_Msk (0x1U << AFIO_EXTICR2_EXTI5_PC_Pos) /*!< 0x00000020 */
+#define AFIO_EXTICR2_EXTI5_PC AFIO_EXTICR2_EXTI5_PC_Msk /*!< PC[5] pin */
+#define AFIO_EXTICR2_EXTI5_PD_Pos (4U)
+#define AFIO_EXTICR2_EXTI5_PD_Msk (0x3U << AFIO_EXTICR2_EXTI5_PD_Pos) /*!< 0x00000030 */
+#define AFIO_EXTICR2_EXTI5_PD AFIO_EXTICR2_EXTI5_PD_Msk /*!< PD[5] pin */
+#define AFIO_EXTICR2_EXTI5_PE_Pos (6U)
+#define AFIO_EXTICR2_EXTI5_PE_Msk (0x1U << AFIO_EXTICR2_EXTI5_PE_Pos) /*!< 0x00000040 */
+#define AFIO_EXTICR2_EXTI5_PE AFIO_EXTICR2_EXTI5_PE_Msk /*!< PE[5] pin */
+#define AFIO_EXTICR2_EXTI5_PF_Pos (4U)
+#define AFIO_EXTICR2_EXTI5_PF_Msk (0x5U << AFIO_EXTICR2_EXTI5_PF_Pos) /*!< 0x00000050 */
+#define AFIO_EXTICR2_EXTI5_PF AFIO_EXTICR2_EXTI5_PF_Msk /*!< PF[5] pin */
+#define AFIO_EXTICR2_EXTI5_PG_Pos (5U)
+#define AFIO_EXTICR2_EXTI5_PG_Msk (0x3U << AFIO_EXTICR2_EXTI5_PG_Pos) /*!< 0x00000060 */
+#define AFIO_EXTICR2_EXTI5_PG AFIO_EXTICR2_EXTI5_PG_Msk /*!< PG[5] pin */
+
+/*!< EXTI6 configuration */
+#define AFIO_EXTICR2_EXTI6_PA ((uint32_t)0x00000000) /*!< PA[6] pin */
+#define AFIO_EXTICR2_EXTI6_PB_Pos (8U)
+#define AFIO_EXTICR2_EXTI6_PB_Msk (0x1U << AFIO_EXTICR2_EXTI6_PB_Pos) /*!< 0x00000100 */
+#define AFIO_EXTICR2_EXTI6_PB AFIO_EXTICR2_EXTI6_PB_Msk /*!< PB[6] pin */
+#define AFIO_EXTICR2_EXTI6_PC_Pos (9U)
+#define AFIO_EXTICR2_EXTI6_PC_Msk (0x1U << AFIO_EXTICR2_EXTI6_PC_Pos) /*!< 0x00000200 */
+#define AFIO_EXTICR2_EXTI6_PC AFIO_EXTICR2_EXTI6_PC_Msk /*!< PC[6] pin */
+#define AFIO_EXTICR2_EXTI6_PD_Pos (8U)
+#define AFIO_EXTICR2_EXTI6_PD_Msk (0x3U << AFIO_EXTICR2_EXTI6_PD_Pos) /*!< 0x00000300 */
+#define AFIO_EXTICR2_EXTI6_PD AFIO_EXTICR2_EXTI6_PD_Msk /*!< PD[6] pin */
+#define AFIO_EXTICR2_EXTI6_PE_Pos (10U)
+#define AFIO_EXTICR2_EXTI6_PE_Msk (0x1U << AFIO_EXTICR2_EXTI6_PE_Pos) /*!< 0x00000400 */
+#define AFIO_EXTICR2_EXTI6_PE AFIO_EXTICR2_EXTI6_PE_Msk /*!< PE[6] pin */
+#define AFIO_EXTICR2_EXTI6_PF_Pos (8U)
+#define AFIO_EXTICR2_EXTI6_PF_Msk (0x5U << AFIO_EXTICR2_EXTI6_PF_Pos) /*!< 0x00000500 */
+#define AFIO_EXTICR2_EXTI6_PF AFIO_EXTICR2_EXTI6_PF_Msk /*!< PF[6] pin */
+#define AFIO_EXTICR2_EXTI6_PG_Pos (9U)
+#define AFIO_EXTICR2_EXTI6_PG_Msk (0x3U << AFIO_EXTICR2_EXTI6_PG_Pos) /*!< 0x00000600 */
+#define AFIO_EXTICR2_EXTI6_PG AFIO_EXTICR2_EXTI6_PG_Msk /*!< PG[6] pin */
+
+/*!< EXTI7 configuration */
+#define AFIO_EXTICR2_EXTI7_PA ((uint32_t)0x00000000) /*!< PA[7] pin */
+#define AFIO_EXTICR2_EXTI7_PB_Pos (12U)
+#define AFIO_EXTICR2_EXTI7_PB_Msk (0x1U << AFIO_EXTICR2_EXTI7_PB_Pos) /*!< 0x00001000 */
+#define AFIO_EXTICR2_EXTI7_PB AFIO_EXTICR2_EXTI7_PB_Msk /*!< PB[7] pin */
+#define AFIO_EXTICR2_EXTI7_PC_Pos (13U)
+#define AFIO_EXTICR2_EXTI7_PC_Msk (0x1U << AFIO_EXTICR2_EXTI7_PC_Pos) /*!< 0x00002000 */
+#define AFIO_EXTICR2_EXTI7_PC AFIO_EXTICR2_EXTI7_PC_Msk /*!< PC[7] pin */
+#define AFIO_EXTICR2_EXTI7_PD_Pos (12U)
+#define AFIO_EXTICR2_EXTI7_PD_Msk (0x3U << AFIO_EXTICR2_EXTI7_PD_Pos) /*!< 0x00003000 */
+#define AFIO_EXTICR2_EXTI7_PD AFIO_EXTICR2_EXTI7_PD_Msk /*!< PD[7] pin */
+#define AFIO_EXTICR2_EXTI7_PE_Pos (14U)
+#define AFIO_EXTICR2_EXTI7_PE_Msk (0x1U << AFIO_EXTICR2_EXTI7_PE_Pos) /*!< 0x00004000 */
+#define AFIO_EXTICR2_EXTI7_PE AFIO_EXTICR2_EXTI7_PE_Msk /*!< PE[7] pin */
+#define AFIO_EXTICR2_EXTI7_PF_Pos (12U)
+#define AFIO_EXTICR2_EXTI7_PF_Msk (0x5U << AFIO_EXTICR2_EXTI7_PF_Pos) /*!< 0x00005000 */
+#define AFIO_EXTICR2_EXTI7_PF AFIO_EXTICR2_EXTI7_PF_Msk /*!< PF[7] pin */
+#define AFIO_EXTICR2_EXTI7_PG_Pos (13U)
+#define AFIO_EXTICR2_EXTI7_PG_Msk (0x3U << AFIO_EXTICR2_EXTI7_PG_Pos) /*!< 0x00006000 */
+#define AFIO_EXTICR2_EXTI7_PG AFIO_EXTICR2_EXTI7_PG_Msk /*!< PG[7] pin */
+
+/***************** Bit definition for AFIO_EXTICR3 register *****************/
+#define AFIO_EXTICR3_EXTI8_Pos (0U)
+#define AFIO_EXTICR3_EXTI8_Msk (0xFU << AFIO_EXTICR3_EXTI8_Pos) /*!< 0x0000000F */
+#define AFIO_EXTICR3_EXTI8 AFIO_EXTICR3_EXTI8_Msk /*!< EXTI 8 configuration */
+#define AFIO_EXTICR3_EXTI9_Pos (4U)
+#define AFIO_EXTICR3_EXTI9_Msk (0xFU << AFIO_EXTICR3_EXTI9_Pos) /*!< 0x000000F0 */
+#define AFIO_EXTICR3_EXTI9 AFIO_EXTICR3_EXTI9_Msk /*!< EXTI 9 configuration */
+#define AFIO_EXTICR3_EXTI10_Pos (8U)
+#define AFIO_EXTICR3_EXTI10_Msk (0xFU << AFIO_EXTICR3_EXTI10_Pos) /*!< 0x00000F00 */
+#define AFIO_EXTICR3_EXTI10 AFIO_EXTICR3_EXTI10_Msk /*!< EXTI 10 configuration */
+#define AFIO_EXTICR3_EXTI11_Pos (12U)
+#define AFIO_EXTICR3_EXTI11_Msk (0xFU << AFIO_EXTICR3_EXTI11_Pos) /*!< 0x0000F000 */
+#define AFIO_EXTICR3_EXTI11 AFIO_EXTICR3_EXTI11_Msk /*!< EXTI 11 configuration */
+
+/*!< EXTI8 configuration */
+#define AFIO_EXTICR3_EXTI8_PA ((uint32_t)0x00000000) /*!< PA[8] pin */
+#define AFIO_EXTICR3_EXTI8_PB_Pos (0U)
+#define AFIO_EXTICR3_EXTI8_PB_Msk (0x1U << AFIO_EXTICR3_EXTI8_PB_Pos) /*!< 0x00000001 */
+#define AFIO_EXTICR3_EXTI8_PB AFIO_EXTICR3_EXTI8_PB_Msk /*!< PB[8] pin */
+#define AFIO_EXTICR3_EXTI8_PC_Pos (1U)
+#define AFIO_EXTICR3_EXTI8_PC_Msk (0x1U << AFIO_EXTICR3_EXTI8_PC_Pos) /*!< 0x00000002 */
+#define AFIO_EXTICR3_EXTI8_PC AFIO_EXTICR3_EXTI8_PC_Msk /*!< PC[8] pin */
+#define AFIO_EXTICR3_EXTI8_PD_Pos (0U)
+#define AFIO_EXTICR3_EXTI8_PD_Msk (0x3U << AFIO_EXTICR3_EXTI8_PD_Pos) /*!< 0x00000003 */
+#define AFIO_EXTICR3_EXTI8_PD AFIO_EXTICR3_EXTI8_PD_Msk /*!< PD[8] pin */
+#define AFIO_EXTICR3_EXTI8_PE_Pos (2U)
+#define AFIO_EXTICR3_EXTI8_PE_Msk (0x1U << AFIO_EXTICR3_EXTI8_PE_Pos) /*!< 0x00000004 */
+#define AFIO_EXTICR3_EXTI8_PE AFIO_EXTICR3_EXTI8_PE_Msk /*!< PE[8] pin */
+#define AFIO_EXTICR3_EXTI8_PF_Pos (0U)
+#define AFIO_EXTICR3_EXTI8_PF_Msk (0x5U << AFIO_EXTICR3_EXTI8_PF_Pos) /*!< 0x00000005 */
+#define AFIO_EXTICR3_EXTI8_PF AFIO_EXTICR3_EXTI8_PF_Msk /*!< PF[8] pin */
+#define AFIO_EXTICR3_EXTI8_PG_Pos (1U)
+#define AFIO_EXTICR3_EXTI8_PG_Msk (0x3U << AFIO_EXTICR3_EXTI8_PG_Pos) /*!< 0x00000006 */
+#define AFIO_EXTICR3_EXTI8_PG AFIO_EXTICR3_EXTI8_PG_Msk /*!< PG[8] pin */
+
+/*!< EXTI9 configuration */
+#define AFIO_EXTICR3_EXTI9_PA ((uint32_t)0x00000000) /*!< PA[9] pin */
+#define AFIO_EXTICR3_EXTI9_PB_Pos (4U)
+#define AFIO_EXTICR3_EXTI9_PB_Msk (0x1U << AFIO_EXTICR3_EXTI9_PB_Pos) /*!< 0x00000010 */
+#define AFIO_EXTICR3_EXTI9_PB AFIO_EXTICR3_EXTI9_PB_Msk /*!< PB[9] pin */
+#define AFIO_EXTICR3_EXTI9_PC_Pos (5U)
+#define AFIO_EXTICR3_EXTI9_PC_Msk (0x1U << AFIO_EXTICR3_EXTI9_PC_Pos) /*!< 0x00000020 */
+#define AFIO_EXTICR3_EXTI9_PC AFIO_EXTICR3_EXTI9_PC_Msk /*!< PC[9] pin */
+#define AFIO_EXTICR3_EXTI9_PD_Pos (4U)
+#define AFIO_EXTICR3_EXTI9_PD_Msk (0x3U << AFIO_EXTICR3_EXTI9_PD_Pos) /*!< 0x00000030 */
+#define AFIO_EXTICR3_EXTI9_PD AFIO_EXTICR3_EXTI9_PD_Msk /*!< PD[9] pin */
+#define AFIO_EXTICR3_EXTI9_PE_Pos (6U)
+#define AFIO_EXTICR3_EXTI9_PE_Msk (0x1U << AFIO_EXTICR3_EXTI9_PE_Pos) /*!< 0x00000040 */
+#define AFIO_EXTICR3_EXTI9_PE AFIO_EXTICR3_EXTI9_PE_Msk /*!< PE[9] pin */
+#define AFIO_EXTICR3_EXTI9_PF_Pos (4U)
+#define AFIO_EXTICR3_EXTI9_PF_Msk (0x5U << AFIO_EXTICR3_EXTI9_PF_Pos) /*!< 0x00000050 */
+#define AFIO_EXTICR3_EXTI9_PF AFIO_EXTICR3_EXTI9_PF_Msk /*!< PF[9] pin */
+#define AFIO_EXTICR3_EXTI9_PG_Pos (5U)
+#define AFIO_EXTICR3_EXTI9_PG_Msk (0x3U << AFIO_EXTICR3_EXTI9_PG_Pos) /*!< 0x00000060 */
+#define AFIO_EXTICR3_EXTI9_PG AFIO_EXTICR3_EXTI9_PG_Msk /*!< PG[9] pin */
+
+/*!< EXTI10 configuration */
+#define AFIO_EXTICR3_EXTI10_PA ((uint32_t)0x00000000) /*!< PA[10] pin */
+#define AFIO_EXTICR3_EXTI10_PB_Pos (8U)
+#define AFIO_EXTICR3_EXTI10_PB_Msk (0x1U << AFIO_EXTICR3_EXTI10_PB_Pos) /*!< 0x00000100 */
+#define AFIO_EXTICR3_EXTI10_PB AFIO_EXTICR3_EXTI10_PB_Msk /*!< PB[10] pin */
+#define AFIO_EXTICR3_EXTI10_PC_Pos (9U)
+#define AFIO_EXTICR3_EXTI10_PC_Msk (0x1U << AFIO_EXTICR3_EXTI10_PC_Pos) /*!< 0x00000200 */
+#define AFIO_EXTICR3_EXTI10_PC AFIO_EXTICR3_EXTI10_PC_Msk /*!< PC[10] pin */
+#define AFIO_EXTICR3_EXTI10_PD_Pos (8U)
+#define AFIO_EXTICR3_EXTI10_PD_Msk (0x3U << AFIO_EXTICR3_EXTI10_PD_Pos) /*!< 0x00000300 */
+#define AFIO_EXTICR3_EXTI10_PD AFIO_EXTICR3_EXTI10_PD_Msk /*!< PD[10] pin */
+#define AFIO_EXTICR3_EXTI10_PE_Pos (10U)
+#define AFIO_EXTICR3_EXTI10_PE_Msk (0x1U << AFIO_EXTICR3_EXTI10_PE_Pos) /*!< 0x00000400 */
+#define AFIO_EXTICR3_EXTI10_PE AFIO_EXTICR3_EXTI10_PE_Msk /*!< PE[10] pin */
+#define AFIO_EXTICR3_EXTI10_PF_Pos (8U)
+#define AFIO_EXTICR3_EXTI10_PF_Msk (0x5U << AFIO_EXTICR3_EXTI10_PF_Pos) /*!< 0x00000500 */
+#define AFIO_EXTICR3_EXTI10_PF AFIO_EXTICR3_EXTI10_PF_Msk /*!< PF[10] pin */
+#define AFIO_EXTICR3_EXTI10_PG_Pos (9U)
+#define AFIO_EXTICR3_EXTI10_PG_Msk (0x3U << AFIO_EXTICR3_EXTI10_PG_Pos) /*!< 0x00000600 */
+#define AFIO_EXTICR3_EXTI10_PG AFIO_EXTICR3_EXTI10_PG_Msk /*!< PG[10] pin */
+
+/*!< EXTI11 configuration */
+#define AFIO_EXTICR3_EXTI11_PA ((uint32_t)0x00000000) /*!< PA[11] pin */
+#define AFIO_EXTICR3_EXTI11_PB_Pos (12U)
+#define AFIO_EXTICR3_EXTI11_PB_Msk (0x1U << AFIO_EXTICR3_EXTI11_PB_Pos) /*!< 0x00001000 */
+#define AFIO_EXTICR3_EXTI11_PB AFIO_EXTICR3_EXTI11_PB_Msk /*!< PB[11] pin */
+#define AFIO_EXTICR3_EXTI11_PC_Pos (13U)
+#define AFIO_EXTICR3_EXTI11_PC_Msk (0x1U << AFIO_EXTICR3_EXTI11_PC_Pos) /*!< 0x00002000 */
+#define AFIO_EXTICR3_EXTI11_PC AFIO_EXTICR3_EXTI11_PC_Msk /*!< PC[11] pin */
+#define AFIO_EXTICR3_EXTI11_PD_Pos (12U)
+#define AFIO_EXTICR3_EXTI11_PD_Msk (0x3U << AFIO_EXTICR3_EXTI11_PD_Pos) /*!< 0x00003000 */
+#define AFIO_EXTICR3_EXTI11_PD AFIO_EXTICR3_EXTI11_PD_Msk /*!< PD[11] pin */
+#define AFIO_EXTICR3_EXTI11_PE_Pos (14U)
+#define AFIO_EXTICR3_EXTI11_PE_Msk (0x1U << AFIO_EXTICR3_EXTI11_PE_Pos) /*!< 0x00004000 */
+#define AFIO_EXTICR3_EXTI11_PE AFIO_EXTICR3_EXTI11_PE_Msk /*!< PE[11] pin */
+#define AFIO_EXTICR3_EXTI11_PF_Pos (12U)
+#define AFIO_EXTICR3_EXTI11_PF_Msk (0x5U << AFIO_EXTICR3_EXTI11_PF_Pos) /*!< 0x00005000 */
+#define AFIO_EXTICR3_EXTI11_PF AFIO_EXTICR3_EXTI11_PF_Msk /*!< PF[11] pin */
+#define AFIO_EXTICR3_EXTI11_PG_Pos (13U)
+#define AFIO_EXTICR3_EXTI11_PG_Msk (0x3U << AFIO_EXTICR3_EXTI11_PG_Pos) /*!< 0x00006000 */
+#define AFIO_EXTICR3_EXTI11_PG AFIO_EXTICR3_EXTI11_PG_Msk /*!< PG[11] pin */
+
+/***************** Bit definition for AFIO_EXTICR4 register *****************/
+#define AFIO_EXTICR4_EXTI12_Pos (0U)
+#define AFIO_EXTICR4_EXTI12_Msk (0xFU << AFIO_EXTICR4_EXTI12_Pos) /*!< 0x0000000F */
+#define AFIO_EXTICR4_EXTI12 AFIO_EXTICR4_EXTI12_Msk /*!< EXTI 12 configuration */
+#define AFIO_EXTICR4_EXTI13_Pos (4U)
+#define AFIO_EXTICR4_EXTI13_Msk (0xFU << AFIO_EXTICR4_EXTI13_Pos) /*!< 0x000000F0 */
+#define AFIO_EXTICR4_EXTI13 AFIO_EXTICR4_EXTI13_Msk /*!< EXTI 13 configuration */
+#define AFIO_EXTICR4_EXTI14_Pos (8U)
+#define AFIO_EXTICR4_EXTI14_Msk (0xFU << AFIO_EXTICR4_EXTI14_Pos) /*!< 0x00000F00 */
+#define AFIO_EXTICR4_EXTI14 AFIO_EXTICR4_EXTI14_Msk /*!< EXTI 14 configuration */
+#define AFIO_EXTICR4_EXTI15_Pos (12U)
+#define AFIO_EXTICR4_EXTI15_Msk (0xFU << AFIO_EXTICR4_EXTI15_Pos) /*!< 0x0000F000 */
+#define AFIO_EXTICR4_EXTI15 AFIO_EXTICR4_EXTI15_Msk /*!< EXTI 15 configuration */
+
+/* EXTI12 configuration */
+#define AFIO_EXTICR4_EXTI12_PA ((uint32_t)0x00000000) /*!< PA[12] pin */
+#define AFIO_EXTICR4_EXTI12_PB_Pos (0U)
+#define AFIO_EXTICR4_EXTI12_PB_Msk (0x1U << AFIO_EXTICR4_EXTI12_PB_Pos) /*!< 0x00000001 */
+#define AFIO_EXTICR4_EXTI12_PB AFIO_EXTICR4_EXTI12_PB_Msk /*!< PB[12] pin */
+#define AFIO_EXTICR4_EXTI12_PC_Pos (1U)
+#define AFIO_EXTICR4_EXTI12_PC_Msk (0x1U << AFIO_EXTICR4_EXTI12_PC_Pos) /*!< 0x00000002 */
+#define AFIO_EXTICR4_EXTI12_PC AFIO_EXTICR4_EXTI12_PC_Msk /*!< PC[12] pin */
+#define AFIO_EXTICR4_EXTI12_PD_Pos (0U)
+#define AFIO_EXTICR4_EXTI12_PD_Msk (0x3U << AFIO_EXTICR4_EXTI12_PD_Pos) /*!< 0x00000003 */
+#define AFIO_EXTICR4_EXTI12_PD AFIO_EXTICR4_EXTI12_PD_Msk /*!< PD[12] pin */
+#define AFIO_EXTICR4_EXTI12_PE_Pos (2U)
+#define AFIO_EXTICR4_EXTI12_PE_Msk (0x1U << AFIO_EXTICR4_EXTI12_PE_Pos) /*!< 0x00000004 */
+#define AFIO_EXTICR4_EXTI12_PE AFIO_EXTICR4_EXTI12_PE_Msk /*!< PE[12] pin */
+#define AFIO_EXTICR4_EXTI12_PF_Pos (0U)
+#define AFIO_EXTICR4_EXTI12_PF_Msk (0x5U << AFIO_EXTICR4_EXTI12_PF_Pos) /*!< 0x00000005 */
+#define AFIO_EXTICR4_EXTI12_PF AFIO_EXTICR4_EXTI12_PF_Msk /*!< PF[12] pin */
+#define AFIO_EXTICR4_EXTI12_PG_Pos (1U)
+#define AFIO_EXTICR4_EXTI12_PG_Msk (0x3U << AFIO_EXTICR4_EXTI12_PG_Pos) /*!< 0x00000006 */
+#define AFIO_EXTICR4_EXTI12_PG AFIO_EXTICR4_EXTI12_PG_Msk /*!< PG[12] pin */
+
+/* EXTI13 configuration */
+#define AFIO_EXTICR4_EXTI13_PA ((uint32_t)0x00000000) /*!< PA[13] pin */
+#define AFIO_EXTICR4_EXTI13_PB_Pos (4U)
+#define AFIO_EXTICR4_EXTI13_PB_Msk (0x1U << AFIO_EXTICR4_EXTI13_PB_Pos) /*!< 0x00000010 */
+#define AFIO_EXTICR4_EXTI13_PB AFIO_EXTICR4_EXTI13_PB_Msk /*!< PB[13] pin */
+#define AFIO_EXTICR4_EXTI13_PC_Pos (5U)
+#define AFIO_EXTICR4_EXTI13_PC_Msk (0x1U << AFIO_EXTICR4_EXTI13_PC_Pos) /*!< 0x00000020 */
+#define AFIO_EXTICR4_EXTI13_PC AFIO_EXTICR4_EXTI13_PC_Msk /*!< PC[13] pin */
+#define AFIO_EXTICR4_EXTI13_PD_Pos (4U)
+#define AFIO_EXTICR4_EXTI13_PD_Msk (0x3U << AFIO_EXTICR4_EXTI13_PD_Pos) /*!< 0x00000030 */
+#define AFIO_EXTICR4_EXTI13_PD AFIO_EXTICR4_EXTI13_PD_Msk /*!< PD[13] pin */
+#define AFIO_EXTICR4_EXTI13_PE_Pos (6U)
+#define AFIO_EXTICR4_EXTI13_PE_Msk (0x1U << AFIO_EXTICR4_EXTI13_PE_Pos) /*!< 0x00000040 */
+#define AFIO_EXTICR4_EXTI13_PE AFIO_EXTICR4_EXTI13_PE_Msk /*!< PE[13] pin */
+#define AFIO_EXTICR4_EXTI13_PF_Pos (4U)
+#define AFIO_EXTICR4_EXTI13_PF_Msk (0x5U << AFIO_EXTICR4_EXTI13_PF_Pos) /*!< 0x00000050 */
+#define AFIO_EXTICR4_EXTI13_PF AFIO_EXTICR4_EXTI13_PF_Msk /*!< PF[13] pin */
+#define AFIO_EXTICR4_EXTI13_PG_Pos (5U)
+#define AFIO_EXTICR4_EXTI13_PG_Msk (0x3U << AFIO_EXTICR4_EXTI13_PG_Pos) /*!< 0x00000060 */
+#define AFIO_EXTICR4_EXTI13_PG AFIO_EXTICR4_EXTI13_PG_Msk /*!< PG[13] pin */
+
+/*!< EXTI14 configuration */
+#define AFIO_EXTICR4_EXTI14_PA ((uint32_t)0x00000000) /*!< PA[14] pin */
+#define AFIO_EXTICR4_EXTI14_PB_Pos (8U)
+#define AFIO_EXTICR4_EXTI14_PB_Msk (0x1U << AFIO_EXTICR4_EXTI14_PB_Pos) /*!< 0x00000100 */
+#define AFIO_EXTICR4_EXTI14_PB AFIO_EXTICR4_EXTI14_PB_Msk /*!< PB[14] pin */
+#define AFIO_EXTICR4_EXTI14_PC_Pos (9U)
+#define AFIO_EXTICR4_EXTI14_PC_Msk (0x1U << AFIO_EXTICR4_EXTI14_PC_Pos) /*!< 0x00000200 */
+#define AFIO_EXTICR4_EXTI14_PC AFIO_EXTICR4_EXTI14_PC_Msk /*!< PC[14] pin */
+#define AFIO_EXTICR4_EXTI14_PD_Pos (8U)
+#define AFIO_EXTICR4_EXTI14_PD_Msk (0x3U << AFIO_EXTICR4_EXTI14_PD_Pos) /*!< 0x00000300 */
+#define AFIO_EXTICR4_EXTI14_PD AFIO_EXTICR4_EXTI14_PD_Msk /*!< PD[14] pin */
+#define AFIO_EXTICR4_EXTI14_PE_Pos (10U)
+#define AFIO_EXTICR4_EXTI14_PE_Msk (0x1U << AFIO_EXTICR4_EXTI14_PE_Pos) /*!< 0x00000400 */
+#define AFIO_EXTICR4_EXTI14_PE AFIO_EXTICR4_EXTI14_PE_Msk /*!< PE[14] pin */
+#define AFIO_EXTICR4_EXTI14_PF_Pos (8U)
+#define AFIO_EXTICR4_EXTI14_PF_Msk (0x5U << AFIO_EXTICR4_EXTI14_PF_Pos) /*!< 0x00000500 */
+#define AFIO_EXTICR4_EXTI14_PF AFIO_EXTICR4_EXTI14_PF_Msk /*!< PF[14] pin */
+#define AFIO_EXTICR4_EXTI14_PG_Pos (9U)
+#define AFIO_EXTICR4_EXTI14_PG_Msk (0x3U << AFIO_EXTICR4_EXTI14_PG_Pos) /*!< 0x00000600 */
+#define AFIO_EXTICR4_EXTI14_PG AFIO_EXTICR4_EXTI14_PG_Msk /*!< PG[14] pin */
+
+/*!< EXTI15 configuration */
+#define AFIO_EXTICR4_EXTI15_PA ((uint32_t)0x00000000) /*!< PA[15] pin */
+#define AFIO_EXTICR4_EXTI15_PB_Pos (12U)
+#define AFIO_EXTICR4_EXTI15_PB_Msk (0x1U << AFIO_EXTICR4_EXTI15_PB_Pos) /*!< 0x00001000 */
+#define AFIO_EXTICR4_EXTI15_PB AFIO_EXTICR4_EXTI15_PB_Msk /*!< PB[15] pin */
+#define AFIO_EXTICR4_EXTI15_PC_Pos (13U)
+#define AFIO_EXTICR4_EXTI15_PC_Msk (0x1U << AFIO_EXTICR4_EXTI15_PC_Pos) /*!< 0x00002000 */
+#define AFIO_EXTICR4_EXTI15_PC AFIO_EXTICR4_EXTI15_PC_Msk /*!< PC[15] pin */
+#define AFIO_EXTICR4_EXTI15_PD_Pos (12U)
+#define AFIO_EXTICR4_EXTI15_PD_Msk (0x3U << AFIO_EXTICR4_EXTI15_PD_Pos) /*!< 0x00003000 */
+#define AFIO_EXTICR4_EXTI15_PD AFIO_EXTICR4_EXTI15_PD_Msk /*!< PD[15] pin */
+#define AFIO_EXTICR4_EXTI15_PE_Pos (14U)
+#define AFIO_EXTICR4_EXTI15_PE_Msk (0x1U << AFIO_EXTICR4_EXTI15_PE_Pos) /*!< 0x00004000 */
+#define AFIO_EXTICR4_EXTI15_PE AFIO_EXTICR4_EXTI15_PE_Msk /*!< PE[15] pin */
+#define AFIO_EXTICR4_EXTI15_PF_Pos (12U)
+#define AFIO_EXTICR4_EXTI15_PF_Msk (0x5U << AFIO_EXTICR4_EXTI15_PF_Pos) /*!< 0x00005000 */
+#define AFIO_EXTICR4_EXTI15_PF AFIO_EXTICR4_EXTI15_PF_Msk /*!< PF[15] pin */
+#define AFIO_EXTICR4_EXTI15_PG_Pos (13U)
+#define AFIO_EXTICR4_EXTI15_PG_Msk (0x3U << AFIO_EXTICR4_EXTI15_PG_Pos) /*!< 0x00006000 */
+#define AFIO_EXTICR4_EXTI15_PG AFIO_EXTICR4_EXTI15_PG_Msk /*!< PG[15] pin */
+
+/****************** Bit definition for AFIO_MAPR2 register ******************/
+
+
+
+/******************************************************************************/
+/* */
+/* SystemTick */
+/* */
+/******************************************************************************/
+
+/***************** Bit definition for SysTick_CTRL register *****************/
+#define SysTick_CTRL_ENABLE ((uint32_t)0x00000001) /*!< Counter enable */
+#define SysTick_CTRL_TICKINT ((uint32_t)0x00000002) /*!< Counting down to 0 pends the SysTick handler */
+#define SysTick_CTRL_CLKSOURCE ((uint32_t)0x00000004) /*!< Clock source */
+#define SysTick_CTRL_COUNTFLAG ((uint32_t)0x00010000) /*!< Count Flag */
+
+/***************** Bit definition for SysTick_LOAD register *****************/
+#define SysTick_LOAD_RELOAD ((uint32_t)0x00FFFFFF) /*!< Value to load into the SysTick Current Value Register when the counter reaches 0 */
+
+/***************** Bit definition for SysTick_VAL register ******************/
+#define SysTick_VAL_CURRENT ((uint32_t)0x00FFFFFF) /*!< Current value at the time the register is accessed */
+
+/***************** Bit definition for SysTick_CALIB register ****************/
+#define SysTick_CALIB_TENMS ((uint32_t)0x00FFFFFF) /*!< Reload value to use for 10ms timing */
+#define SysTick_CALIB_SKEW ((uint32_t)0x40000000) /*!< Calibration value is not exactly 10 ms */
+#define SysTick_CALIB_NOREF ((uint32_t)0x80000000) /*!< The reference clock is not provided */
+
+/******************************************************************************/
+/* */
+/* Nested Vectored Interrupt Controller */
+/* */
+/******************************************************************************/
+
+/****************** Bit definition for NVIC_ISER register *******************/
+#define NVIC_ISER_SETENA_Pos (0U)
+#define NVIC_ISER_SETENA_Msk (0xFFFFFFFFU << NVIC_ISER_SETENA_Pos) /*!< 0xFFFFFFFF */
+#define NVIC_ISER_SETENA NVIC_ISER_SETENA_Msk /*!< Interrupt set enable bits */
+#define NVIC_ISER_SETENA_0 (0x00000001U << NVIC_ISER_SETENA_Pos) /*!< 0x00000001 */
+#define NVIC_ISER_SETENA_1 (0x00000002U << NVIC_ISER_SETENA_Pos) /*!< 0x00000002 */
+#define NVIC_ISER_SETENA_2 (0x00000004U << NVIC_ISER_SETENA_Pos) /*!< 0x00000004 */
+#define NVIC_ISER_SETENA_3 (0x00000008U << NVIC_ISER_SETENA_Pos) /*!< 0x00000008 */
+#define NVIC_ISER_SETENA_4 (0x00000010U << NVIC_ISER_SETENA_Pos) /*!< 0x00000010 */
+#define NVIC_ISER_SETENA_5 (0x00000020U << NVIC_ISER_SETENA_Pos) /*!< 0x00000020 */
+#define NVIC_ISER_SETENA_6 (0x00000040U << NVIC_ISER_SETENA_Pos) /*!< 0x00000040 */
+#define NVIC_ISER_SETENA_7 (0x00000080U << NVIC_ISER_SETENA_Pos) /*!< 0x00000080 */
+#define NVIC_ISER_SETENA_8 (0x00000100U << NVIC_ISER_SETENA_Pos) /*!< 0x00000100 */
+#define NVIC_ISER_SETENA_9 (0x00000200U << NVIC_ISER_SETENA_Pos) /*!< 0x00000200 */
+#define NVIC_ISER_SETENA_10 (0x00000400U << NVIC_ISER_SETENA_Pos) /*!< 0x00000400 */
+#define NVIC_ISER_SETENA_11 (0x00000800U << NVIC_ISER_SETENA_Pos) /*!< 0x00000800 */
+#define NVIC_ISER_SETENA_12 (0x00001000U << NVIC_ISER_SETENA_Pos) /*!< 0x00001000 */
+#define NVIC_ISER_SETENA_13 (0x00002000U << NVIC_ISER_SETENA_Pos) /*!< 0x00002000 */
+#define NVIC_ISER_SETENA_14 (0x00004000U << NVIC_ISER_SETENA_Pos) /*!< 0x00004000 */
+#define NVIC_ISER_SETENA_15 (0x00008000U << NVIC_ISER_SETENA_Pos) /*!< 0x00008000 */
+#define NVIC_ISER_SETENA_16 (0x00010000U << NVIC_ISER_SETENA_Pos) /*!< 0x00010000 */
+#define NVIC_ISER_SETENA_17 (0x00020000U << NVIC_ISER_SETENA_Pos) /*!< 0x00020000 */
+#define NVIC_ISER_SETENA_18 (0x00040000U << NVIC_ISER_SETENA_Pos) /*!< 0x00040000 */
+#define NVIC_ISER_SETENA_19 (0x00080000U << NVIC_ISER_SETENA_Pos) /*!< 0x00080000 */
+#define NVIC_ISER_SETENA_20 (0x00100000U << NVIC_ISER_SETENA_Pos) /*!< 0x00100000 */
+#define NVIC_ISER_SETENA_21 (0x00200000U << NVIC_ISER_SETENA_Pos) /*!< 0x00200000 */
+#define NVIC_ISER_SETENA_22 (0x00400000U << NVIC_ISER_SETENA_Pos) /*!< 0x00400000 */
+#define NVIC_ISER_SETENA_23 (0x00800000U << NVIC_ISER_SETENA_Pos) /*!< 0x00800000 */
+#define NVIC_ISER_SETENA_24 (0x01000000U << NVIC_ISER_SETENA_Pos) /*!< 0x01000000 */
+#define NVIC_ISER_SETENA_25 (0x02000000U << NVIC_ISER_SETENA_Pos) /*!< 0x02000000 */
+#define NVIC_ISER_SETENA_26 (0x04000000U << NVIC_ISER_SETENA_Pos) /*!< 0x04000000 */
+#define NVIC_ISER_SETENA_27 (0x08000000U << NVIC_ISER_SETENA_Pos) /*!< 0x08000000 */
+#define NVIC_ISER_SETENA_28 (0x10000000U << NVIC_ISER_SETENA_Pos) /*!< 0x10000000 */
+#define NVIC_ISER_SETENA_29 (0x20000000U << NVIC_ISER_SETENA_Pos) /*!< 0x20000000 */
+#define NVIC_ISER_SETENA_30 (0x40000000U << NVIC_ISER_SETENA_Pos) /*!< 0x40000000 */
+#define NVIC_ISER_SETENA_31 (0x80000000U << NVIC_ISER_SETENA_Pos) /*!< 0x80000000 */
+
+/****************** Bit definition for NVIC_ICER register *******************/
+#define NVIC_ICER_CLRENA_Pos (0U)
+#define NVIC_ICER_CLRENA_Msk (0xFFFFFFFFU << NVIC_ICER_CLRENA_Pos) /*!< 0xFFFFFFFF */
+#define NVIC_ICER_CLRENA NVIC_ICER_CLRENA_Msk /*!< Interrupt clear-enable bits */
+#define NVIC_ICER_CLRENA_0 (0x00000001U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000001 */
+#define NVIC_ICER_CLRENA_1 (0x00000002U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000002 */
+#define NVIC_ICER_CLRENA_2 (0x00000004U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000004 */
+#define NVIC_ICER_CLRENA_3 (0x00000008U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000008 */
+#define NVIC_ICER_CLRENA_4 (0x00000010U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000010 */
+#define NVIC_ICER_CLRENA_5 (0x00000020U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000020 */
+#define NVIC_ICER_CLRENA_6 (0x00000040U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000040 */
+#define NVIC_ICER_CLRENA_7 (0x00000080U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000080 */
+#define NVIC_ICER_CLRENA_8 (0x00000100U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000100 */
+#define NVIC_ICER_CLRENA_9 (0x00000200U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000200 */
+#define NVIC_ICER_CLRENA_10 (0x00000400U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000400 */
+#define NVIC_ICER_CLRENA_11 (0x00000800U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000800 */
+#define NVIC_ICER_CLRENA_12 (0x00001000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00001000 */
+#define NVIC_ICER_CLRENA_13 (0x00002000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00002000 */
+#define NVIC_ICER_CLRENA_14 (0x00004000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00004000 */
+#define NVIC_ICER_CLRENA_15 (0x00008000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00008000 */
+#define NVIC_ICER_CLRENA_16 (0x00010000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00010000 */
+#define NVIC_ICER_CLRENA_17 (0x00020000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00020000 */
+#define NVIC_ICER_CLRENA_18 (0x00040000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00040000 */
+#define NVIC_ICER_CLRENA_19 (0x00080000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00080000 */
+#define NVIC_ICER_CLRENA_20 (0x00100000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00100000 */
+#define NVIC_ICER_CLRENA_21 (0x00200000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00200000 */
+#define NVIC_ICER_CLRENA_22 (0x00400000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00400000 */
+#define NVIC_ICER_CLRENA_23 (0x00800000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00800000 */
+#define NVIC_ICER_CLRENA_24 (0x01000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x01000000 */
+#define NVIC_ICER_CLRENA_25 (0x02000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x02000000 */
+#define NVIC_ICER_CLRENA_26 (0x04000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x04000000 */
+#define NVIC_ICER_CLRENA_27 (0x08000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x08000000 */
+#define NVIC_ICER_CLRENA_28 (0x10000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x10000000 */
+#define NVIC_ICER_CLRENA_29 (0x20000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x20000000 */
+#define NVIC_ICER_CLRENA_30 (0x40000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x40000000 */
+#define NVIC_ICER_CLRENA_31 (0x80000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x80000000 */
+
+/****************** Bit definition for NVIC_ISPR register *******************/
+#define NVIC_ISPR_SETPEND_Pos (0U)
+#define NVIC_ISPR_SETPEND_Msk (0xFFFFFFFFU << NVIC_ISPR_SETPEND_Pos) /*!< 0xFFFFFFFF */
+#define NVIC_ISPR_SETPEND NVIC_ISPR_SETPEND_Msk /*!< Interrupt set-pending bits */
+#define NVIC_ISPR_SETPEND_0 (0x00000001U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000001 */
+#define NVIC_ISPR_SETPEND_1 (0x00000002U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000002 */
+#define NVIC_ISPR_SETPEND_2 (0x00000004U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000004 */
+#define NVIC_ISPR_SETPEND_3 (0x00000008U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000008 */
+#define NVIC_ISPR_SETPEND_4 (0x00000010U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000010 */
+#define NVIC_ISPR_SETPEND_5 (0x00000020U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000020 */
+#define NVIC_ISPR_SETPEND_6 (0x00000040U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000040 */
+#define NVIC_ISPR_SETPEND_7 (0x00000080U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000080 */
+#define NVIC_ISPR_SETPEND_8 (0x00000100U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000100 */
+#define NVIC_ISPR_SETPEND_9 (0x00000200U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000200 */
+#define NVIC_ISPR_SETPEND_10 (0x00000400U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000400 */
+#define NVIC_ISPR_SETPEND_11 (0x00000800U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000800 */
+#define NVIC_ISPR_SETPEND_12 (0x00001000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00001000 */
+#define NVIC_ISPR_SETPEND_13 (0x00002000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00002000 */
+#define NVIC_ISPR_SETPEND_14 (0x00004000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00004000 */
+#define NVIC_ISPR_SETPEND_15 (0x00008000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00008000 */
+#define NVIC_ISPR_SETPEND_16 (0x00010000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00010000 */
+#define NVIC_ISPR_SETPEND_17 (0x00020000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00020000 */
+#define NVIC_ISPR_SETPEND_18 (0x00040000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00040000 */
+#define NVIC_ISPR_SETPEND_19 (0x00080000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00080000 */
+#define NVIC_ISPR_SETPEND_20 (0x00100000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00100000 */
+#define NVIC_ISPR_SETPEND_21 (0x00200000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00200000 */
+#define NVIC_ISPR_SETPEND_22 (0x00400000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00400000 */
+#define NVIC_ISPR_SETPEND_23 (0x00800000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00800000 */
+#define NVIC_ISPR_SETPEND_24 (0x01000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x01000000 */
+#define NVIC_ISPR_SETPEND_25 (0x02000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x02000000 */
+#define NVIC_ISPR_SETPEND_26 (0x04000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x04000000 */
+#define NVIC_ISPR_SETPEND_27 (0x08000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x08000000 */
+#define NVIC_ISPR_SETPEND_28 (0x10000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x10000000 */
+#define NVIC_ISPR_SETPEND_29 (0x20000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x20000000 */
+#define NVIC_ISPR_SETPEND_30 (0x40000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x40000000 */
+#define NVIC_ISPR_SETPEND_31 (0x80000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x80000000 */
+
+/****************** Bit definition for NVIC_ICPR register *******************/
+#define NVIC_ICPR_CLRPEND_Pos (0U)
+#define NVIC_ICPR_CLRPEND_Msk (0xFFFFFFFFU << NVIC_ICPR_CLRPEND_Pos) /*!< 0xFFFFFFFF */
+#define NVIC_ICPR_CLRPEND NVIC_ICPR_CLRPEND_Msk /*!< Interrupt clear-pending bits */
+#define NVIC_ICPR_CLRPEND_0 (0x00000001U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000001 */
+#define NVIC_ICPR_CLRPEND_1 (0x00000002U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000002 */
+#define NVIC_ICPR_CLRPEND_2 (0x00000004U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000004 */
+#define NVIC_ICPR_CLRPEND_3 (0x00000008U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000008 */
+#define NVIC_ICPR_CLRPEND_4 (0x00000010U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000010 */
+#define NVIC_ICPR_CLRPEND_5 (0x00000020U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000020 */
+#define NVIC_ICPR_CLRPEND_6 (0x00000040U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000040 */
+#define NVIC_ICPR_CLRPEND_7 (0x00000080U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000080 */
+#define NVIC_ICPR_CLRPEND_8 (0x00000100U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000100 */
+#define NVIC_ICPR_CLRPEND_9 (0x00000200U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000200 */
+#define NVIC_ICPR_CLRPEND_10 (0x00000400U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000400 */
+#define NVIC_ICPR_CLRPEND_11 (0x00000800U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000800 */
+#define NVIC_ICPR_CLRPEND_12 (0x00001000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00001000 */
+#define NVIC_ICPR_CLRPEND_13 (0x00002000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00002000 */
+#define NVIC_ICPR_CLRPEND_14 (0x00004000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00004000 */
+#define NVIC_ICPR_CLRPEND_15 (0x00008000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00008000 */
+#define NVIC_ICPR_CLRPEND_16 (0x00010000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00010000 */
+#define NVIC_ICPR_CLRPEND_17 (0x00020000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00020000 */
+#define NVIC_ICPR_CLRPEND_18 (0x00040000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00040000 */
+#define NVIC_ICPR_CLRPEND_19 (0x00080000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00080000 */
+#define NVIC_ICPR_CLRPEND_20 (0x00100000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00100000 */
+#define NVIC_ICPR_CLRPEND_21 (0x00200000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00200000 */
+#define NVIC_ICPR_CLRPEND_22 (0x00400000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00400000 */
+#define NVIC_ICPR_CLRPEND_23 (0x00800000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00800000 */
+#define NVIC_ICPR_CLRPEND_24 (0x01000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x01000000 */
+#define NVIC_ICPR_CLRPEND_25 (0x02000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x02000000 */
+#define NVIC_ICPR_CLRPEND_26 (0x04000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x04000000 */
+#define NVIC_ICPR_CLRPEND_27 (0x08000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x08000000 */
+#define NVIC_ICPR_CLRPEND_28 (0x10000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x10000000 */
+#define NVIC_ICPR_CLRPEND_29 (0x20000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x20000000 */
+#define NVIC_ICPR_CLRPEND_30 (0x40000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x40000000 */
+#define NVIC_ICPR_CLRPEND_31 (0x80000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x80000000 */
+
+/****************** Bit definition for NVIC_IABR register *******************/
+#define NVIC_IABR_ACTIVE_Pos (0U)
+#define NVIC_IABR_ACTIVE_Msk (0xFFFFFFFFU << NVIC_IABR_ACTIVE_Pos) /*!< 0xFFFFFFFF */
+#define NVIC_IABR_ACTIVE NVIC_IABR_ACTIVE_Msk /*!< Interrupt active flags */
+#define NVIC_IABR_ACTIVE_0 (0x00000001U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000001 */
+#define NVIC_IABR_ACTIVE_1 (0x00000002U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000002 */
+#define NVIC_IABR_ACTIVE_2 (0x00000004U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000004 */
+#define NVIC_IABR_ACTIVE_3 (0x00000008U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000008 */
+#define NVIC_IABR_ACTIVE_4 (0x00000010U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000010 */
+#define NVIC_IABR_ACTIVE_5 (0x00000020U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000020 */
+#define NVIC_IABR_ACTIVE_6 (0x00000040U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000040 */
+#define NVIC_IABR_ACTIVE_7 (0x00000080U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000080 */
+#define NVIC_IABR_ACTIVE_8 (0x00000100U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000100 */
+#define NVIC_IABR_ACTIVE_9 (0x00000200U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000200 */
+#define NVIC_IABR_ACTIVE_10 (0x00000400U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000400 */
+#define NVIC_IABR_ACTIVE_11 (0x00000800U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000800 */
+#define NVIC_IABR_ACTIVE_12 (0x00001000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00001000 */
+#define NVIC_IABR_ACTIVE_13 (0x00002000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00002000 */
+#define NVIC_IABR_ACTIVE_14 (0x00004000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00004000 */
+#define NVIC_IABR_ACTIVE_15 (0x00008000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00008000 */
+#define NVIC_IABR_ACTIVE_16 (0x00010000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00010000 */
+#define NVIC_IABR_ACTIVE_17 (0x00020000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00020000 */
+#define NVIC_IABR_ACTIVE_18 (0x00040000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00040000 */
+#define NVIC_IABR_ACTIVE_19 (0x00080000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00080000 */
+#define NVIC_IABR_ACTIVE_20 (0x00100000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00100000 */
+#define NVIC_IABR_ACTIVE_21 (0x00200000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00200000 */
+#define NVIC_IABR_ACTIVE_22 (0x00400000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00400000 */
+#define NVIC_IABR_ACTIVE_23 (0x00800000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00800000 */
+#define NVIC_IABR_ACTIVE_24 (0x01000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x01000000 */
+#define NVIC_IABR_ACTIVE_25 (0x02000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x02000000 */
+#define NVIC_IABR_ACTIVE_26 (0x04000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x04000000 */
+#define NVIC_IABR_ACTIVE_27 (0x08000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x08000000 */
+#define NVIC_IABR_ACTIVE_28 (0x10000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x10000000 */
+#define NVIC_IABR_ACTIVE_29 (0x20000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x20000000 */
+#define NVIC_IABR_ACTIVE_30 (0x40000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x40000000 */
+#define NVIC_IABR_ACTIVE_31 (0x80000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x80000000 */
+
+/****************** Bit definition for NVIC_PRI0 register *******************/
+#define NVIC_IPR0_PRI_0 ((uint32_t)0x000000FF) /*!< Priority of interrupt 0 */
+#define NVIC_IPR0_PRI_1 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 1 */
+#define NVIC_IPR0_PRI_2 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 2 */
+#define NVIC_IPR0_PRI_3 ((uint32_t)0xFF000000) /*!< Priority of interrupt 3 */
+
+/****************** Bit definition for NVIC_PRI1 register *******************/
+#define NVIC_IPR1_PRI_4 ((uint32_t)0x000000FF) /*!< Priority of interrupt 4 */
+#define NVIC_IPR1_PRI_5 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 5 */
+#define NVIC_IPR1_PRI_6 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 6 */
+#define NVIC_IPR1_PRI_7 ((uint32_t)0xFF000000) /*!< Priority of interrupt 7 */
+
+/****************** Bit definition for NVIC_PRI2 register *******************/
+#define NVIC_IPR2_PRI_8 ((uint32_t)0x000000FF) /*!< Priority of interrupt 8 */
+#define NVIC_IPR2_PRI_9 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 9 */
+#define NVIC_IPR2_PRI_10 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 10 */
+#define NVIC_IPR2_PRI_11 ((uint32_t)0xFF000000) /*!< Priority of interrupt 11 */
+
+/****************** Bit definition for NVIC_PRI3 register *******************/
+#define NVIC_IPR3_PRI_12 ((uint32_t)0x000000FF) /*!< Priority of interrupt 12 */
+#define NVIC_IPR3_PRI_13 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 13 */
+#define NVIC_IPR3_PRI_14 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 14 */
+#define NVIC_IPR3_PRI_15 ((uint32_t)0xFF000000) /*!< Priority of interrupt 15 */
+
+/****************** Bit definition for NVIC_PRI4 register *******************/
+#define NVIC_IPR4_PRI_16 ((uint32_t)0x000000FF) /*!< Priority of interrupt 16 */
+#define NVIC_IPR4_PRI_17 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 17 */
+#define NVIC_IPR4_PRI_18 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 18 */
+#define NVIC_IPR4_PRI_19 ((uint32_t)0xFF000000) /*!< Priority of interrupt 19 */
+
+/****************** Bit definition for NVIC_PRI5 register *******************/
+#define NVIC_IPR5_PRI_20 ((uint32_t)0x000000FF) /*!< Priority of interrupt 20 */
+#define NVIC_IPR5_PRI_21 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 21 */
+#define NVIC_IPR5_PRI_22 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 22 */
+#define NVIC_IPR5_PRI_23 ((uint32_t)0xFF000000) /*!< Priority of interrupt 23 */
+
+/****************** Bit definition for NVIC_PRI6 register *******************/
+#define NVIC_IPR6_PRI_24 ((uint32_t)0x000000FF) /*!< Priority of interrupt 24 */
+#define NVIC_IPR6_PRI_25 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 25 */
+#define NVIC_IPR6_PRI_26 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 26 */
+#define NVIC_IPR6_PRI_27 ((uint32_t)0xFF000000) /*!< Priority of interrupt 27 */
+
+/****************** Bit definition for NVIC_PRI7 register *******************/
+#define NVIC_IPR7_PRI_28 ((uint32_t)0x000000FF) /*!< Priority of interrupt 28 */
+#define NVIC_IPR7_PRI_29 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 29 */
+#define NVIC_IPR7_PRI_30 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 30 */
+#define NVIC_IPR7_PRI_31 ((uint32_t)0xFF000000) /*!< Priority of interrupt 31 */
+
+/****************** Bit definition for SCB_CPUID register *******************/
+#define SCB_CPUID_REVISION ((uint32_t)0x0000000F) /*!< Implementation defined revision number */
+#define SCB_CPUID_PARTNO ((uint32_t)0x0000FFF0) /*!< Number of processor within family */
+#define SCB_CPUID_Constant ((uint32_t)0x000F0000) /*!< Reads as 0x0F */
+#define SCB_CPUID_VARIANT ((uint32_t)0x00F00000) /*!< Implementation defined variant number */
+#define SCB_CPUID_IMPLEMENTER ((uint32_t)0xFF000000) /*!< Implementer code. ARM is 0x41 */
+
+/******************* Bit definition for SCB_ICSR register *******************/
+#define SCB_ICSR_VECTACTIVE ((uint32_t)0x000001FF) /*!< Active ISR number field */
+#define SCB_ICSR_RETTOBASE ((uint32_t)0x00000800) /*!< All active exceptions minus the IPSR_current_exception yields the empty set */
+#define SCB_ICSR_VECTPENDING ((uint32_t)0x003FF000) /*!< Pending ISR number field */
+#define SCB_ICSR_ISRPENDING ((uint32_t)0x00400000) /*!< Interrupt pending flag */
+#define SCB_ICSR_ISRPREEMPT ((uint32_t)0x00800000) /*!< It indicates that a pending interrupt becomes active in the next running cycle */
+#define SCB_ICSR_PENDSTCLR ((uint32_t)0x02000000) /*!< Clear pending SysTick bit */
+#define SCB_ICSR_PENDSTSET ((uint32_t)0x04000000) /*!< Set pending SysTick bit */
+#define SCB_ICSR_PENDSVCLR ((uint32_t)0x08000000) /*!< Clear pending pendSV bit */
+#define SCB_ICSR_PENDSVSET ((uint32_t)0x10000000) /*!< Set pending pendSV bit */
+#define SCB_ICSR_NMIPENDSET ((uint32_t)0x80000000) /*!< Set pending NMI bit */
+
+/******************* Bit definition for SCB_VTOR register *******************/
+#define SCB_VTOR_TBLOFF ((uint32_t)0x1FFFFF80) /*!< Vector table base offset field */
+#define SCB_VTOR_TBLBASE ((uint32_t)0x20000000) /*!< Table base in code(0) or RAM(1) */
+
+/*!<***************** Bit definition for SCB_AIRCR register *******************/
+#define SCB_AIRCR_VECTRESET ((uint32_t)0x00000001) /*!< System Reset bit */
+#define SCB_AIRCR_VECTCLRACTIVE ((uint32_t)0x00000002) /*!< Clear active vector bit */
+#define SCB_AIRCR_SYSRESETREQ ((uint32_t)0x00000004) /*!< Requests chip control logic to generate a reset */
+
+#define SCB_AIRCR_PRIGROUP ((uint32_t)0x00000700) /*!< PRIGROUP[2:0] bits (Priority group) */
+#define SCB_AIRCR_PRIGROUP_0 ((uint32_t)0x00000100) /*!< Bit 0 */
+#define SCB_AIRCR_PRIGROUP_1 ((uint32_t)0x00000200) /*!< Bit 1 */
+#define SCB_AIRCR_PRIGROUP_2 ((uint32_t)0x00000400) /*!< Bit 2 */
+
+/* prority group configuration */
+#define SCB_AIRCR_PRIGROUP0 ((uint32_t)0x00000000) /*!< Priority group=0 (7 bits of pre-emption priority, 1 bit of subpriority) */
+#define SCB_AIRCR_PRIGROUP1 ((uint32_t)0x00000100) /*!< Priority group=1 (6 bits of pre-emption priority, 2 bits of subpriority) */
+#define SCB_AIRCR_PRIGROUP2 ((uint32_t)0x00000200) /*!< Priority group=2 (5 bits of pre-emption priority, 3 bits of subpriority) */
+#define SCB_AIRCR_PRIGROUP3 ((uint32_t)0x00000300) /*!< Priority group=3 (4 bits of pre-emption priority, 4 bits of subpriority) */
+#define SCB_AIRCR_PRIGROUP4 ((uint32_t)0x00000400) /*!< Priority group=4 (3 bits of pre-emption priority, 5 bits of subpriority) */
+#define SCB_AIRCR_PRIGROUP5 ((uint32_t)0x00000500) /*!< Priority group=5 (2 bits of pre-emption priority, 6 bits of subpriority) */
+#define SCB_AIRCR_PRIGROUP6 ((uint32_t)0x00000600) /*!< Priority group=6 (1 bit of pre-emption priority, 7 bits of subpriority) */
+#define SCB_AIRCR_PRIGROUP7 ((uint32_t)0x00000700) /*!< Priority group=7 (no pre-emption priority, 8 bits of subpriority) */
+
+#define SCB_AIRCR_ENDIANESS ((uint32_t)0x00008000) /*!< Data endianness bit */
+#define SCB_AIRCR_VECTKEY ((uint32_t)0xFFFF0000) /*!< Register key (VECTKEY) - Reads as 0xFA05 (VECTKEYSTAT) */
+
+/******************* Bit definition for SCB_SCR register ********************/
+#define SCB_SCR_SLEEPONEXIT ((uint32_t)0x00000002) /*!< Sleep on exit bit */
+#define SCB_SCR_SLEEPDEEP ((uint32_t)0x00000004) /*!< Sleep deep bit */
+#define SCB_SCR_SEVONPEND ((uint32_t)0x00000010) /*!< Wake up from WFE */
+
+/******************** Bit definition for SCB_CCR register *******************/
+#define SCB_CCR_NONBASETHRDENA ((uint32_t)0x00000001) /*!< Thread mode can be entered from any level in Handler mode by controlled return value */
+#define SCB_CCR_USERSETMPEND ((uint32_t)0x00000002) /*!< Enables user code to write the Software Trigger Interrupt register to trigger (pend) a Main exception */
+#define SCB_CCR_UNALIGN_TRP ((uint32_t)0x00000008) /*!< Trap for unaligned access */
+#define SCB_CCR_DIV_0_TRP ((uint32_t)0x00000010) /*!< Trap on Divide by 0 */
+#define SCB_CCR_BFHFNMIGN ((uint32_t)0x00000100) /*!< Handlers running at priority -1 and -2 */
+#define SCB_CCR_STKALIGN ((uint32_t)0x00000200) /*!< On exception entry, the SP used prior to the exception is adjusted to be 8-byte aligned */
+
+/******************* Bit definition for SCB_SHPR register ********************/
+#define SCB_SHPR_PRI_N_Pos (0U)
+#define SCB_SHPR_PRI_N_Msk (0xFFU << SCB_SHPR_PRI_N_Pos) /*!< 0x000000FF */
+#define SCB_SHPR_PRI_N SCB_SHPR_PRI_N_Msk /*!< Priority of system handler 4,8, and 12. Mem Manage, reserved and Debug Monitor */
+#define SCB_SHPR_PRI_N1_Pos (8U)
+#define SCB_SHPR_PRI_N1_Msk (0xFFU << SCB_SHPR_PRI_N1_Pos) /*!< 0x0000FF00 */
+#define SCB_SHPR_PRI_N1 SCB_SHPR_PRI_N1_Msk /*!< Priority of system handler 5,9, and 13. Bus Fault, reserved and reserved */
+#define SCB_SHPR_PRI_N2_Pos (16U)
+#define SCB_SHPR_PRI_N2_Msk (0xFFU << SCB_SHPR_PRI_N2_Pos) /*!< 0x00FF0000 */
+#define SCB_SHPR_PRI_N2 SCB_SHPR_PRI_N2_Msk /*!< Priority of system handler 6,10, and 14. Usage Fault, reserved and PendSV */
+#define SCB_SHPR_PRI_N3_Pos (24U)
+#define SCB_SHPR_PRI_N3_Msk (0xFFU << SCB_SHPR_PRI_N3_Pos) /*!< 0xFF000000 */
+#define SCB_SHPR_PRI_N3 SCB_SHPR_PRI_N3_Msk /*!< Priority of system handler 7,11, and 15. Reserved, SVCall and SysTick */
+
+/****************** Bit definition for SCB_SHCSR register *******************/
+#define SCB_SHCSR_MEMFAULTACT ((uint32_t)0x00000001) /*!< MemManage is active */
+#define SCB_SHCSR_BUSFAULTACT ((uint32_t)0x00000002) /*!< BusFault is active */
+#define SCB_SHCSR_USGFAULTACT ((uint32_t)0x00000008) /*!< UsageFault is active */
+#define SCB_SHCSR_SVCALLACT ((uint32_t)0x00000080) /*!< SVCall is active */
+#define SCB_SHCSR_MONITORACT ((uint32_t)0x00000100) /*!< Monitor is active */
+#define SCB_SHCSR_PENDSVACT ((uint32_t)0x00000400) /*!< PendSV is active */
+#define SCB_SHCSR_SYSTICKACT ((uint32_t)0x00000800) /*!< SysTick is active */
+#define SCB_SHCSR_USGFAULTPENDED ((uint32_t)0x00001000) /*!< Usage Fault is pended */
+#define SCB_SHCSR_MEMFAULTPENDED ((uint32_t)0x00002000) /*!< MemManage is pended */
+#define SCB_SHCSR_BUSFAULTPENDED ((uint32_t)0x00004000) /*!< Bus Fault is pended */
+#define SCB_SHCSR_SVCALLPENDED ((uint32_t)0x00008000) /*!< SVCall is pended */
+#define SCB_SHCSR_MEMFAULTENA ((uint32_t)0x00010000) /*!< MemManage enable */
+#define SCB_SHCSR_BUSFAULTENA ((uint32_t)0x00020000) /*!< Bus Fault enable */
+#define SCB_SHCSR_USGFAULTENA ((uint32_t)0x00040000) /*!< UsageFault enable */
+
+/******************* Bit definition for SCB_CFSR register *******************/
+/*!< MFSR */
+#define SCB_CFSR_IACCVIOL_Pos (0U)
+#define SCB_CFSR_IACCVIOL_Msk (0x1U << SCB_CFSR_IACCVIOL_Pos) /*!< 0x00000001 */
+#define SCB_CFSR_IACCVIOL SCB_CFSR_IACCVIOL_Msk /*!< Instruction access violation */
+#define SCB_CFSR_DACCVIOL_Pos (1U)
+#define SCB_CFSR_DACCVIOL_Msk (0x1U << SCB_CFSR_DACCVIOL_Pos) /*!< 0x00000002 */
+#define SCB_CFSR_DACCVIOL SCB_CFSR_DACCVIOL_Msk /*!< Data access violation */
+#define SCB_CFSR_MUNSTKERR_Pos (3U)
+#define SCB_CFSR_MUNSTKERR_Msk (0x1U << SCB_CFSR_MUNSTKERR_Pos) /*!< 0x00000008 */
+#define SCB_CFSR_MUNSTKERR SCB_CFSR_MUNSTKERR_Msk /*!< Unstacking error */
+#define SCB_CFSR_MSTKERR_Pos (4U)
+#define SCB_CFSR_MSTKERR_Msk (0x1U << SCB_CFSR_MSTKERR_Pos) /*!< 0x00000010 */
+#define SCB_CFSR_MSTKERR SCB_CFSR_MSTKERR_Msk /*!< Stacking error */
+#define SCB_CFSR_MMARVALID_Pos (7U)
+#define SCB_CFSR_MMARVALID_Msk (0x1U << SCB_CFSR_MMARVALID_Pos) /*!< 0x00000080 */
+#define SCB_CFSR_MMARVALID SCB_CFSR_MMARVALID_Msk /*!< Memory Manage Address Register address valid flag */
+/*!< BFSR */
+#define SCB_CFSR_IBUSERR_Pos (8U)
+#define SCB_CFSR_IBUSERR_Msk (0x1U << SCB_CFSR_IBUSERR_Pos) /*!< 0x00000100 */
+#define SCB_CFSR_IBUSERR SCB_CFSR_IBUSERR_Msk /*!< Instruction bus error flag */
+#define SCB_CFSR_PRECISERR_Pos (9U)
+#define SCB_CFSR_PRECISERR_Msk (0x1U << SCB_CFSR_PRECISERR_Pos) /*!< 0x00000200 */
+#define SCB_CFSR_PRECISERR SCB_CFSR_PRECISERR_Msk /*!< Precise data bus error */
+#define SCB_CFSR_IMPRECISERR_Pos (10U)
+#define SCB_CFSR_IMPRECISERR_Msk (0x1U << SCB_CFSR_IMPRECISERR_Pos) /*!< 0x00000400 */
+#define SCB_CFSR_IMPRECISERR SCB_CFSR_IMPRECISERR_Msk /*!< Imprecise data bus error */
+#define SCB_CFSR_UNSTKERR_Pos (11U)
+#define SCB_CFSR_UNSTKERR_Msk (0x1U << SCB_CFSR_UNSTKERR_Pos) /*!< 0x00000800 */
+#define SCB_CFSR_UNSTKERR SCB_CFSR_UNSTKERR_Msk /*!< Unstacking error */
+#define SCB_CFSR_STKERR_Pos (12U)
+#define SCB_CFSR_STKERR_Msk (0x1U << SCB_CFSR_STKERR_Pos) /*!< 0x00001000 */
+#define SCB_CFSR_STKERR SCB_CFSR_STKERR_Msk /*!< Stacking error */
+#define SCB_CFSR_BFARVALID_Pos (15U)
+#define SCB_CFSR_BFARVALID_Msk (0x1U << SCB_CFSR_BFARVALID_Pos) /*!< 0x00008000 */
+#define SCB_CFSR_BFARVALID SCB_CFSR_BFARVALID_Msk /*!< Bus Fault Address Register address valid flag */
+/*!< UFSR */
+#define SCB_CFSR_UNDEFINSTR_Pos (16U)
+#define SCB_CFSR_UNDEFINSTR_Msk (0x1U << SCB_CFSR_UNDEFINSTR_Pos) /*!< 0x00010000 */
+#define SCB_CFSR_UNDEFINSTR SCB_CFSR_UNDEFINSTR_Msk /*!< The processor attempt to execute an undefined instruction */
+#define SCB_CFSR_INVSTATE_Pos (17U)
+#define SCB_CFSR_INVSTATE_Msk (0x1U << SCB_CFSR_INVSTATE_Pos) /*!< 0x00020000 */
+#define SCB_CFSR_INVSTATE SCB_CFSR_INVSTATE_Msk /*!< Invalid combination of EPSR and instruction */
+#define SCB_CFSR_INVPC_Pos (18U)
+#define SCB_CFSR_INVPC_Msk (0x1U << SCB_CFSR_INVPC_Pos) /*!< 0x00040000 */
+#define SCB_CFSR_INVPC SCB_CFSR_INVPC_Msk /*!< Attempt to load EXC_RETURN into pc illegally */
+#define SCB_CFSR_NOCP_Pos (19U)
+#define SCB_CFSR_NOCP_Msk (0x1U << SCB_CFSR_NOCP_Pos) /*!< 0x00080000 */
+#define SCB_CFSR_NOCP SCB_CFSR_NOCP_Msk /*!< Attempt to use a coprocessor instruction */
+#define SCB_CFSR_UNALIGNED_Pos (24U)
+#define SCB_CFSR_UNALIGNED_Msk (0x1U << SCB_CFSR_UNALIGNED_Pos) /*!< 0x01000000 */
+#define SCB_CFSR_UNALIGNED SCB_CFSR_UNALIGNED_Msk /*!< Fault occurs when there is an attempt to make an unaligned memory access */
+#define SCB_CFSR_DIVBYZERO_Pos (25U)
+#define SCB_CFSR_DIVBYZERO_Msk (0x1U << SCB_CFSR_DIVBYZERO_Pos) /*!< 0x02000000 */
+#define SCB_CFSR_DIVBYZERO SCB_CFSR_DIVBYZERO_Msk /*!< Fault occurs when SDIV or DIV instruction is used with a divisor of 0 */
+
+/******************* Bit definition for SCB_HFSR register *******************/
+#define SCB_HFSR_VECTTBL ((uint32_t)0x00000002) /*!< Fault occurs because of vector table read on exception processing */
+#define SCB_HFSR_FORCED ((uint32_t)0x40000000) /*!< Hard Fault activated when a configurable Fault was received and cannot activate */
+#define SCB_HFSR_DEBUGEVT ((uint32_t)0x80000000) /*!< Fault related to debug */
+
+/******************* Bit definition for SCB_DFSR register *******************/
+#define SCB_DFSR_HALTED ((uint32_t)0x00000001) /*!< Halt request flag */
+#define SCB_DFSR_BKPT ((uint32_t)0x00000002) /*!< BKPT flag */
+#define SCB_DFSR_DWTTRAP ((uint32_t)0x00000004) /*!< Data Watchpoint and Trace (DWT) flag */
+#define SCB_DFSR_VCATCH ((uint32_t)0x00000008) /*!< Vector catch flag */
+#define SCB_DFSR_EXTERNAL ((uint32_t)0x00000010) /*!< External debug request flag */
+
+/******************* Bit definition for SCB_MMFAR register ******************/
+#define SCB_MMFAR_ADDRESS_Pos (0U)
+#define SCB_MMFAR_ADDRESS_Msk (0xFFFFFFFFU << SCB_MMFAR_ADDRESS_Pos) /*!< 0xFFFFFFFF */
+#define SCB_MMFAR_ADDRESS SCB_MMFAR_ADDRESS_Msk /*!< Mem Manage fault address field */
+
+/******************* Bit definition for SCB_BFAR register *******************/
+#define SCB_BFAR_ADDRESS_Pos (0U)
+#define SCB_BFAR_ADDRESS_Msk (0xFFFFFFFFU << SCB_BFAR_ADDRESS_Pos) /*!< 0xFFFFFFFF */
+#define SCB_BFAR_ADDRESS SCB_BFAR_ADDRESS_Msk /*!< Bus fault address field */
+
+/******************* Bit definition for SCB_afsr register *******************/
+#define SCB_AFSR_IMPDEF_Pos (0U)
+#define SCB_AFSR_IMPDEF_Msk (0xFFFFFFFFU << SCB_AFSR_IMPDEF_Pos) /*!< 0xFFFFFFFF */
+#define SCB_AFSR_IMPDEF SCB_AFSR_IMPDEF_Msk /*!< Implementation defined */
+
+/******************************************************************************/
+/* */
+/* External Interrupt/Event Controller */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for EXTI_IMR register *******************/
+#define EXTI_IMR_MR0_Pos (0U)
+#define EXTI_IMR_MR0_Msk (0x1U << EXTI_IMR_MR0_Pos) /*!< 0x00000001 */
+#define EXTI_IMR_MR0 EXTI_IMR_MR0_Msk /*!< Interrupt Mask on line 0 */
+#define EXTI_IMR_MR1_Pos (1U)
+#define EXTI_IMR_MR1_Msk (0x1U << EXTI_IMR_MR1_Pos) /*!< 0x00000002 */
+#define EXTI_IMR_MR1 EXTI_IMR_MR1_Msk /*!< Interrupt Mask on line 1 */
+#define EXTI_IMR_MR2_Pos (2U)
+#define EXTI_IMR_MR2_Msk (0x1U << EXTI_IMR_MR2_Pos) /*!< 0x00000004 */
+#define EXTI_IMR_MR2 EXTI_IMR_MR2_Msk /*!< Interrupt Mask on line 2 */
+#define EXTI_IMR_MR3_Pos (3U)
+#define EXTI_IMR_MR3_Msk (0x1U << EXTI_IMR_MR3_Pos) /*!< 0x00000008 */
+#define EXTI_IMR_MR3 EXTI_IMR_MR3_Msk /*!< Interrupt Mask on line 3 */
+#define EXTI_IMR_MR4_Pos (4U)
+#define EXTI_IMR_MR4_Msk (0x1U << EXTI_IMR_MR4_Pos) /*!< 0x00000010 */
+#define EXTI_IMR_MR4 EXTI_IMR_MR4_Msk /*!< Interrupt Mask on line 4 */
+#define EXTI_IMR_MR5_Pos (5U)
+#define EXTI_IMR_MR5_Msk (0x1U << EXTI_IMR_MR5_Pos) /*!< 0x00000020 */
+#define EXTI_IMR_MR5 EXTI_IMR_MR5_Msk /*!< Interrupt Mask on line 5 */
+#define EXTI_IMR_MR6_Pos (6U)
+#define EXTI_IMR_MR6_Msk (0x1U << EXTI_IMR_MR6_Pos) /*!< 0x00000040 */
+#define EXTI_IMR_MR6 EXTI_IMR_MR6_Msk /*!< Interrupt Mask on line 6 */
+#define EXTI_IMR_MR7_Pos (7U)
+#define EXTI_IMR_MR7_Msk (0x1U << EXTI_IMR_MR7_Pos) /*!< 0x00000080 */
+#define EXTI_IMR_MR7 EXTI_IMR_MR7_Msk /*!< Interrupt Mask on line 7 */
+#define EXTI_IMR_MR8_Pos (8U)
+#define EXTI_IMR_MR8_Msk (0x1U << EXTI_IMR_MR8_Pos) /*!< 0x00000100 */
+#define EXTI_IMR_MR8 EXTI_IMR_MR8_Msk /*!< Interrupt Mask on line 8 */
+#define EXTI_IMR_MR9_Pos (9U)
+#define EXTI_IMR_MR9_Msk (0x1U << EXTI_IMR_MR9_Pos) /*!< 0x00000200 */
+#define EXTI_IMR_MR9 EXTI_IMR_MR9_Msk /*!< Interrupt Mask on line 9 */
+#define EXTI_IMR_MR10_Pos (10U)
+#define EXTI_IMR_MR10_Msk (0x1U << EXTI_IMR_MR10_Pos) /*!< 0x00000400 */
+#define EXTI_IMR_MR10 EXTI_IMR_MR10_Msk /*!< Interrupt Mask on line 10 */
+#define EXTI_IMR_MR11_Pos (11U)
+#define EXTI_IMR_MR11_Msk (0x1U << EXTI_IMR_MR11_Pos) /*!< 0x00000800 */
+#define EXTI_IMR_MR11 EXTI_IMR_MR11_Msk /*!< Interrupt Mask on line 11 */
+#define EXTI_IMR_MR12_Pos (12U)
+#define EXTI_IMR_MR12_Msk (0x1U << EXTI_IMR_MR12_Pos) /*!< 0x00001000 */
+#define EXTI_IMR_MR12 EXTI_IMR_MR12_Msk /*!< Interrupt Mask on line 12 */
+#define EXTI_IMR_MR13_Pos (13U)
+#define EXTI_IMR_MR13_Msk (0x1U << EXTI_IMR_MR13_Pos) /*!< 0x00002000 */
+#define EXTI_IMR_MR13 EXTI_IMR_MR13_Msk /*!< Interrupt Mask on line 13 */
+#define EXTI_IMR_MR14_Pos (14U)
+#define EXTI_IMR_MR14_Msk (0x1U << EXTI_IMR_MR14_Pos) /*!< 0x00004000 */
+#define EXTI_IMR_MR14 EXTI_IMR_MR14_Msk /*!< Interrupt Mask on line 14 */
+#define EXTI_IMR_MR15_Pos (15U)
+#define EXTI_IMR_MR15_Msk (0x1U << EXTI_IMR_MR15_Pos) /*!< 0x00008000 */
+#define EXTI_IMR_MR15 EXTI_IMR_MR15_Msk /*!< Interrupt Mask on line 15 */
+#define EXTI_IMR_MR16_Pos (16U)
+#define EXTI_IMR_MR16_Msk (0x1U << EXTI_IMR_MR16_Pos) /*!< 0x00010000 */
+#define EXTI_IMR_MR16 EXTI_IMR_MR16_Msk /*!< Interrupt Mask on line 16 */
+#define EXTI_IMR_MR17_Pos (17U)
+#define EXTI_IMR_MR17_Msk (0x1U << EXTI_IMR_MR17_Pos) /*!< 0x00020000 */
+#define EXTI_IMR_MR17 EXTI_IMR_MR17_Msk /*!< Interrupt Mask on line 17 */
+#define EXTI_IMR_MR18_Pos (18U)
+#define EXTI_IMR_MR18_Msk (0x1U << EXTI_IMR_MR18_Pos) /*!< 0x00040000 */
+#define EXTI_IMR_MR18 EXTI_IMR_MR18_Msk /*!< Interrupt Mask on line 18 */
+#define EXTI_IMR_MR19_Pos (19U)
+#define EXTI_IMR_MR19_Msk (0x1U << EXTI_IMR_MR19_Pos) /*!< 0x00080000 */
+#define EXTI_IMR_MR19 EXTI_IMR_MR19_Msk /*!< Interrupt Mask on line 19 */
+
+/* References Defines */
+#define EXTI_IMR_IM0 EXTI_IMR_MR0
+#define EXTI_IMR_IM1 EXTI_IMR_MR1
+#define EXTI_IMR_IM2 EXTI_IMR_MR2
+#define EXTI_IMR_IM3 EXTI_IMR_MR3
+#define EXTI_IMR_IM4 EXTI_IMR_MR4
+#define EXTI_IMR_IM5 EXTI_IMR_MR5
+#define EXTI_IMR_IM6 EXTI_IMR_MR6
+#define EXTI_IMR_IM7 EXTI_IMR_MR7
+#define EXTI_IMR_IM8 EXTI_IMR_MR8
+#define EXTI_IMR_IM9 EXTI_IMR_MR9
+#define EXTI_IMR_IM10 EXTI_IMR_MR10
+#define EXTI_IMR_IM11 EXTI_IMR_MR11
+#define EXTI_IMR_IM12 EXTI_IMR_MR12
+#define EXTI_IMR_IM13 EXTI_IMR_MR13
+#define EXTI_IMR_IM14 EXTI_IMR_MR14
+#define EXTI_IMR_IM15 EXTI_IMR_MR15
+#define EXTI_IMR_IM16 EXTI_IMR_MR16
+#define EXTI_IMR_IM17 EXTI_IMR_MR17
+#define EXTI_IMR_IM18 EXTI_IMR_MR18
+#define EXTI_IMR_IM19 EXTI_IMR_MR19
+
+/******************* Bit definition for EXTI_EMR register *******************/
+#define EXTI_EMR_MR0_Pos (0U)
+#define EXTI_EMR_MR0_Msk (0x1U << EXTI_EMR_MR0_Pos) /*!< 0x00000001 */
+#define EXTI_EMR_MR0 EXTI_EMR_MR0_Msk /*!< Event Mask on line 0 */
+#define EXTI_EMR_MR1_Pos (1U)
+#define EXTI_EMR_MR1_Msk (0x1U << EXTI_EMR_MR1_Pos) /*!< 0x00000002 */
+#define EXTI_EMR_MR1 EXTI_EMR_MR1_Msk /*!< Event Mask on line 1 */
+#define EXTI_EMR_MR2_Pos (2U)
+#define EXTI_EMR_MR2_Msk (0x1U << EXTI_EMR_MR2_Pos) /*!< 0x00000004 */
+#define EXTI_EMR_MR2 EXTI_EMR_MR2_Msk /*!< Event Mask on line 2 */
+#define EXTI_EMR_MR3_Pos (3U)
+#define EXTI_EMR_MR3_Msk (0x1U << EXTI_EMR_MR3_Pos) /*!< 0x00000008 */
+#define EXTI_EMR_MR3 EXTI_EMR_MR3_Msk /*!< Event Mask on line 3 */
+#define EXTI_EMR_MR4_Pos (4U)
+#define EXTI_EMR_MR4_Msk (0x1U << EXTI_EMR_MR4_Pos) /*!< 0x00000010 */
+#define EXTI_EMR_MR4 EXTI_EMR_MR4_Msk /*!< Event Mask on line 4 */
+#define EXTI_EMR_MR5_Pos (5U)
+#define EXTI_EMR_MR5_Msk (0x1U << EXTI_EMR_MR5_Pos) /*!< 0x00000020 */
+#define EXTI_EMR_MR5 EXTI_EMR_MR5_Msk /*!< Event Mask on line 5 */
+#define EXTI_EMR_MR6_Pos (6U)
+#define EXTI_EMR_MR6_Msk (0x1U << EXTI_EMR_MR6_Pos) /*!< 0x00000040 */
+#define EXTI_EMR_MR6 EXTI_EMR_MR6_Msk /*!< Event Mask on line 6 */
+#define EXTI_EMR_MR7_Pos (7U)
+#define EXTI_EMR_MR7_Msk (0x1U << EXTI_EMR_MR7_Pos) /*!< 0x00000080 */
+#define EXTI_EMR_MR7 EXTI_EMR_MR7_Msk /*!< Event Mask on line 7 */
+#define EXTI_EMR_MR8_Pos (8U)
+#define EXTI_EMR_MR8_Msk (0x1U << EXTI_EMR_MR8_Pos) /*!< 0x00000100 */
+#define EXTI_EMR_MR8 EXTI_EMR_MR8_Msk /*!< Event Mask on line 8 */
+#define EXTI_EMR_MR9_Pos (9U)
+#define EXTI_EMR_MR9_Msk (0x1U << EXTI_EMR_MR9_Pos) /*!< 0x00000200 */
+#define EXTI_EMR_MR9 EXTI_EMR_MR9_Msk /*!< Event Mask on line 9 */
+#define EXTI_EMR_MR10_Pos (10U)
+#define EXTI_EMR_MR10_Msk (0x1U << EXTI_EMR_MR10_Pos) /*!< 0x00000400 */
+#define EXTI_EMR_MR10 EXTI_EMR_MR10_Msk /*!< Event Mask on line 10 */
+#define EXTI_EMR_MR11_Pos (11U)
+#define EXTI_EMR_MR11_Msk (0x1U << EXTI_EMR_MR11_Pos) /*!< 0x00000800 */
+#define EXTI_EMR_MR11 EXTI_EMR_MR11_Msk /*!< Event Mask on line 11 */
+#define EXTI_EMR_MR12_Pos (12U)
+#define EXTI_EMR_MR12_Msk (0x1U << EXTI_EMR_MR12_Pos) /*!< 0x00001000 */
+#define EXTI_EMR_MR12 EXTI_EMR_MR12_Msk /*!< Event Mask on line 12 */
+#define EXTI_EMR_MR13_Pos (13U)
+#define EXTI_EMR_MR13_Msk (0x1U << EXTI_EMR_MR13_Pos) /*!< 0x00002000 */
+#define EXTI_EMR_MR13 EXTI_EMR_MR13_Msk /*!< Event Mask on line 13 */
+#define EXTI_EMR_MR14_Pos (14U)
+#define EXTI_EMR_MR14_Msk (0x1U << EXTI_EMR_MR14_Pos) /*!< 0x00004000 */
+#define EXTI_EMR_MR14 EXTI_EMR_MR14_Msk /*!< Event Mask on line 14 */
+#define EXTI_EMR_MR15_Pos (15U)
+#define EXTI_EMR_MR15_Msk (0x1U << EXTI_EMR_MR15_Pos) /*!< 0x00008000 */
+#define EXTI_EMR_MR15 EXTI_EMR_MR15_Msk /*!< Event Mask on line 15 */
+#define EXTI_EMR_MR16_Pos (16U)
+#define EXTI_EMR_MR16_Msk (0x1U << EXTI_EMR_MR16_Pos) /*!< 0x00010000 */
+#define EXTI_EMR_MR16 EXTI_EMR_MR16_Msk /*!< Event Mask on line 16 */
+#define EXTI_EMR_MR17_Pos (17U)
+#define EXTI_EMR_MR17_Msk (0x1U << EXTI_EMR_MR17_Pos) /*!< 0x00020000 */
+#define EXTI_EMR_MR17 EXTI_EMR_MR17_Msk /*!< Event Mask on line 17 */
+#define EXTI_EMR_MR18_Pos (18U)
+#define EXTI_EMR_MR18_Msk (0x1U << EXTI_EMR_MR18_Pos) /*!< 0x00040000 */
+#define EXTI_EMR_MR18 EXTI_EMR_MR18_Msk /*!< Event Mask on line 18 */
+#define EXTI_EMR_MR19_Pos (19U)
+#define EXTI_EMR_MR19_Msk (0x1U << EXTI_EMR_MR19_Pos) /*!< 0x00080000 */
+#define EXTI_EMR_MR19 EXTI_EMR_MR19_Msk /*!< Event Mask on line 19 */
+
+/* References Defines */
+#define EXTI_EMR_EM0 EXTI_EMR_MR0
+#define EXTI_EMR_EM1 EXTI_EMR_MR1
+#define EXTI_EMR_EM2 EXTI_EMR_MR2
+#define EXTI_EMR_EM3 EXTI_EMR_MR3
+#define EXTI_EMR_EM4 EXTI_EMR_MR4
+#define EXTI_EMR_EM5 EXTI_EMR_MR5
+#define EXTI_EMR_EM6 EXTI_EMR_MR6
+#define EXTI_EMR_EM7 EXTI_EMR_MR7
+#define EXTI_EMR_EM8 EXTI_EMR_MR8
+#define EXTI_EMR_EM9 EXTI_EMR_MR9
+#define EXTI_EMR_EM10 EXTI_EMR_MR10
+#define EXTI_EMR_EM11 EXTI_EMR_MR11
+#define EXTI_EMR_EM12 EXTI_EMR_MR12
+#define EXTI_EMR_EM13 EXTI_EMR_MR13
+#define EXTI_EMR_EM14 EXTI_EMR_MR14
+#define EXTI_EMR_EM15 EXTI_EMR_MR15
+#define EXTI_EMR_EM16 EXTI_EMR_MR16
+#define EXTI_EMR_EM17 EXTI_EMR_MR17
+#define EXTI_EMR_EM18 EXTI_EMR_MR18
+#define EXTI_EMR_EM19 EXTI_EMR_MR19
+
+/****************** Bit definition for EXTI_RTSR register *******************/
+#define EXTI_RTSR_TR0_Pos (0U)
+#define EXTI_RTSR_TR0_Msk (0x1U << EXTI_RTSR_TR0_Pos) /*!< 0x00000001 */
+#define EXTI_RTSR_TR0 EXTI_RTSR_TR0_Msk /*!< Rising trigger event configuration bit of line 0 */
+#define EXTI_RTSR_TR1_Pos (1U)
+#define EXTI_RTSR_TR1_Msk (0x1U << EXTI_RTSR_TR1_Pos) /*!< 0x00000002 */
+#define EXTI_RTSR_TR1 EXTI_RTSR_TR1_Msk /*!< Rising trigger event configuration bit of line 1 */
+#define EXTI_RTSR_TR2_Pos (2U)
+#define EXTI_RTSR_TR2_Msk (0x1U << EXTI_RTSR_TR2_Pos) /*!< 0x00000004 */
+#define EXTI_RTSR_TR2 EXTI_RTSR_TR2_Msk /*!< Rising trigger event configuration bit of line 2 */
+#define EXTI_RTSR_TR3_Pos (3U)
+#define EXTI_RTSR_TR3_Msk (0x1U << EXTI_RTSR_TR3_Pos) /*!< 0x00000008 */
+#define EXTI_RTSR_TR3 EXTI_RTSR_TR3_Msk /*!< Rising trigger event configuration bit of line 3 */
+#define EXTI_RTSR_TR4_Pos (4U)
+#define EXTI_RTSR_TR4_Msk (0x1U << EXTI_RTSR_TR4_Pos) /*!< 0x00000010 */
+#define EXTI_RTSR_TR4 EXTI_RTSR_TR4_Msk /*!< Rising trigger event configuration bit of line 4 */
+#define EXTI_RTSR_TR5_Pos (5U)
+#define EXTI_RTSR_TR5_Msk (0x1U << EXTI_RTSR_TR5_Pos) /*!< 0x00000020 */
+#define EXTI_RTSR_TR5 EXTI_RTSR_TR5_Msk /*!< Rising trigger event configuration bit of line 5 */
+#define EXTI_RTSR_TR6_Pos (6U)
+#define EXTI_RTSR_TR6_Msk (0x1U << EXTI_RTSR_TR6_Pos) /*!< 0x00000040 */
+#define EXTI_RTSR_TR6 EXTI_RTSR_TR6_Msk /*!< Rising trigger event configuration bit of line 6 */
+#define EXTI_RTSR_TR7_Pos (7U)
+#define EXTI_RTSR_TR7_Msk (0x1U << EXTI_RTSR_TR7_Pos) /*!< 0x00000080 */
+#define EXTI_RTSR_TR7 EXTI_RTSR_TR7_Msk /*!< Rising trigger event configuration bit of line 7 */
+#define EXTI_RTSR_TR8_Pos (8U)
+#define EXTI_RTSR_TR8_Msk (0x1U << EXTI_RTSR_TR8_Pos) /*!< 0x00000100 */
+#define EXTI_RTSR_TR8 EXTI_RTSR_TR8_Msk /*!< Rising trigger event configuration bit of line 8 */
+#define EXTI_RTSR_TR9_Pos (9U)
+#define EXTI_RTSR_TR9_Msk (0x1U << EXTI_RTSR_TR9_Pos) /*!< 0x00000200 */
+#define EXTI_RTSR_TR9 EXTI_RTSR_TR9_Msk /*!< Rising trigger event configuration bit of line 9 */
+#define EXTI_RTSR_TR10_Pos (10U)
+#define EXTI_RTSR_TR10_Msk (0x1U << EXTI_RTSR_TR10_Pos) /*!< 0x00000400 */
+#define EXTI_RTSR_TR10 EXTI_RTSR_TR10_Msk /*!< Rising trigger event configuration bit of line 10 */
+#define EXTI_RTSR_TR11_Pos (11U)
+#define EXTI_RTSR_TR11_Msk (0x1U << EXTI_RTSR_TR11_Pos) /*!< 0x00000800 */
+#define EXTI_RTSR_TR11 EXTI_RTSR_TR11_Msk /*!< Rising trigger event configuration bit of line 11 */
+#define EXTI_RTSR_TR12_Pos (12U)
+#define EXTI_RTSR_TR12_Msk (0x1U << EXTI_RTSR_TR12_Pos) /*!< 0x00001000 */
+#define EXTI_RTSR_TR12 EXTI_RTSR_TR12_Msk /*!< Rising trigger event configuration bit of line 12 */
+#define EXTI_RTSR_TR13_Pos (13U)
+#define EXTI_RTSR_TR13_Msk (0x1U << EXTI_RTSR_TR13_Pos) /*!< 0x00002000 */
+#define EXTI_RTSR_TR13 EXTI_RTSR_TR13_Msk /*!< Rising trigger event configuration bit of line 13 */
+#define EXTI_RTSR_TR14_Pos (14U)
+#define EXTI_RTSR_TR14_Msk (0x1U << EXTI_RTSR_TR14_Pos) /*!< 0x00004000 */
+#define EXTI_RTSR_TR14 EXTI_RTSR_TR14_Msk /*!< Rising trigger event configuration bit of line 14 */
+#define EXTI_RTSR_TR15_Pos (15U)
+#define EXTI_RTSR_TR15_Msk (0x1U << EXTI_RTSR_TR15_Pos) /*!< 0x00008000 */
+#define EXTI_RTSR_TR15 EXTI_RTSR_TR15_Msk /*!< Rising trigger event configuration bit of line 15 */
+#define EXTI_RTSR_TR16_Pos (16U)
+#define EXTI_RTSR_TR16_Msk (0x1U << EXTI_RTSR_TR16_Pos) /*!< 0x00010000 */
+#define EXTI_RTSR_TR16 EXTI_RTSR_TR16_Msk /*!< Rising trigger event configuration bit of line 16 */
+#define EXTI_RTSR_TR17_Pos (17U)
+#define EXTI_RTSR_TR17_Msk (0x1U << EXTI_RTSR_TR17_Pos) /*!< 0x00020000 */
+#define EXTI_RTSR_TR17 EXTI_RTSR_TR17_Msk /*!< Rising trigger event configuration bit of line 17 */
+#define EXTI_RTSR_TR18_Pos (18U)
+#define EXTI_RTSR_TR18_Msk (0x1U << EXTI_RTSR_TR18_Pos) /*!< 0x00040000 */
+#define EXTI_RTSR_TR18 EXTI_RTSR_TR18_Msk /*!< Rising trigger event configuration bit of line 18 */
+#define EXTI_RTSR_TR19_Pos (19U)
+#define EXTI_RTSR_TR19_Msk (0x1U << EXTI_RTSR_TR19_Pos) /*!< 0x00080000 */
+#define EXTI_RTSR_TR19 EXTI_RTSR_TR19_Msk /*!< Rising trigger event configuration bit of line 19 */
+
+/* References Defines */
+#define EXTI_RTSR_RT0 EXTI_RTSR_TR0
+#define EXTI_RTSR_RT1 EXTI_RTSR_TR1
+#define EXTI_RTSR_RT2 EXTI_RTSR_TR2
+#define EXTI_RTSR_RT3 EXTI_RTSR_TR3
+#define EXTI_RTSR_RT4 EXTI_RTSR_TR4
+#define EXTI_RTSR_RT5 EXTI_RTSR_TR5
+#define EXTI_RTSR_RT6 EXTI_RTSR_TR6
+#define EXTI_RTSR_RT7 EXTI_RTSR_TR7
+#define EXTI_RTSR_RT8 EXTI_RTSR_TR8
+#define EXTI_RTSR_RT9 EXTI_RTSR_TR9
+#define EXTI_RTSR_RT10 EXTI_RTSR_TR10
+#define EXTI_RTSR_RT11 EXTI_RTSR_TR11
+#define EXTI_RTSR_RT12 EXTI_RTSR_TR12
+#define EXTI_RTSR_RT13 EXTI_RTSR_TR13
+#define EXTI_RTSR_RT14 EXTI_RTSR_TR14
+#define EXTI_RTSR_RT15 EXTI_RTSR_TR15
+#define EXTI_RTSR_RT16 EXTI_RTSR_TR16
+#define EXTI_RTSR_RT17 EXTI_RTSR_TR17
+#define EXTI_RTSR_RT18 EXTI_RTSR_TR18
+#define EXTI_RTSR_RT19 EXTI_RTSR_TR19
+
+/****************** Bit definition for EXTI_FTSR register *******************/
+#define EXTI_FTSR_TR0_Pos (0U)
+#define EXTI_FTSR_TR0_Msk (0x1U << EXTI_FTSR_TR0_Pos) /*!< 0x00000001 */
+#define EXTI_FTSR_TR0 EXTI_FTSR_TR0_Msk /*!< Falling trigger event configuration bit of line 0 */
+#define EXTI_FTSR_TR1_Pos (1U)
+#define EXTI_FTSR_TR1_Msk (0x1U << EXTI_FTSR_TR1_Pos) /*!< 0x00000002 */
+#define EXTI_FTSR_TR1 EXTI_FTSR_TR1_Msk /*!< Falling trigger event configuration bit of line 1 */
+#define EXTI_FTSR_TR2_Pos (2U)
+#define EXTI_FTSR_TR2_Msk (0x1U << EXTI_FTSR_TR2_Pos) /*!< 0x00000004 */
+#define EXTI_FTSR_TR2 EXTI_FTSR_TR2_Msk /*!< Falling trigger event configuration bit of line 2 */
+#define EXTI_FTSR_TR3_Pos (3U)
+#define EXTI_FTSR_TR3_Msk (0x1U << EXTI_FTSR_TR3_Pos) /*!< 0x00000008 */
+#define EXTI_FTSR_TR3 EXTI_FTSR_TR3_Msk /*!< Falling trigger event configuration bit of line 3 */
+#define EXTI_FTSR_TR4_Pos (4U)
+#define EXTI_FTSR_TR4_Msk (0x1U << EXTI_FTSR_TR4_Pos) /*!< 0x00000010 */
+#define EXTI_FTSR_TR4 EXTI_FTSR_TR4_Msk /*!< Falling trigger event configuration bit of line 4 */
+#define EXTI_FTSR_TR5_Pos (5U)
+#define EXTI_FTSR_TR5_Msk (0x1U << EXTI_FTSR_TR5_Pos) /*!< 0x00000020 */
+#define EXTI_FTSR_TR5 EXTI_FTSR_TR5_Msk /*!< Falling trigger event configuration bit of line 5 */
+#define EXTI_FTSR_TR6_Pos (6U)
+#define EXTI_FTSR_TR6_Msk (0x1U << EXTI_FTSR_TR6_Pos) /*!< 0x00000040 */
+#define EXTI_FTSR_TR6 EXTI_FTSR_TR6_Msk /*!< Falling trigger event configuration bit of line 6 */
+#define EXTI_FTSR_TR7_Pos (7U)
+#define EXTI_FTSR_TR7_Msk (0x1U << EXTI_FTSR_TR7_Pos) /*!< 0x00000080 */
+#define EXTI_FTSR_TR7 EXTI_FTSR_TR7_Msk /*!< Falling trigger event configuration bit of line 7 */
+#define EXTI_FTSR_TR8_Pos (8U)
+#define EXTI_FTSR_TR8_Msk (0x1U << EXTI_FTSR_TR8_Pos) /*!< 0x00000100 */
+#define EXTI_FTSR_TR8 EXTI_FTSR_TR8_Msk /*!< Falling trigger event configuration bit of line 8 */
+#define EXTI_FTSR_TR9_Pos (9U)
+#define EXTI_FTSR_TR9_Msk (0x1U << EXTI_FTSR_TR9_Pos) /*!< 0x00000200 */
+#define EXTI_FTSR_TR9 EXTI_FTSR_TR9_Msk /*!< Falling trigger event configuration bit of line 9 */
+#define EXTI_FTSR_TR10_Pos (10U)
+#define EXTI_FTSR_TR10_Msk (0x1U << EXTI_FTSR_TR10_Pos) /*!< 0x00000400 */
+#define EXTI_FTSR_TR10 EXTI_FTSR_TR10_Msk /*!< Falling trigger event configuration bit of line 10 */
+#define EXTI_FTSR_TR11_Pos (11U)
+#define EXTI_FTSR_TR11_Msk (0x1U << EXTI_FTSR_TR11_Pos) /*!< 0x00000800 */
+#define EXTI_FTSR_TR11 EXTI_FTSR_TR11_Msk /*!< Falling trigger event configuration bit of line 11 */
+#define EXTI_FTSR_TR12_Pos (12U)
+#define EXTI_FTSR_TR12_Msk (0x1U << EXTI_FTSR_TR12_Pos) /*!< 0x00001000 */
+#define EXTI_FTSR_TR12 EXTI_FTSR_TR12_Msk /*!< Falling trigger event configuration bit of line 12 */
+#define EXTI_FTSR_TR13_Pos (13U)
+#define EXTI_FTSR_TR13_Msk (0x1U << EXTI_FTSR_TR13_Pos) /*!< 0x00002000 */
+#define EXTI_FTSR_TR13 EXTI_FTSR_TR13_Msk /*!< Falling trigger event configuration bit of line 13 */
+#define EXTI_FTSR_TR14_Pos (14U)
+#define EXTI_FTSR_TR14_Msk (0x1U << EXTI_FTSR_TR14_Pos) /*!< 0x00004000 */
+#define EXTI_FTSR_TR14 EXTI_FTSR_TR14_Msk /*!< Falling trigger event configuration bit of line 14 */
+#define EXTI_FTSR_TR15_Pos (15U)
+#define EXTI_FTSR_TR15_Msk (0x1U << EXTI_FTSR_TR15_Pos) /*!< 0x00008000 */
+#define EXTI_FTSR_TR15 EXTI_FTSR_TR15_Msk /*!< Falling trigger event configuration bit of line 15 */
+#define EXTI_FTSR_TR16_Pos (16U)
+#define EXTI_FTSR_TR16_Msk (0x1U << EXTI_FTSR_TR16_Pos) /*!< 0x00010000 */
+#define EXTI_FTSR_TR16 EXTI_FTSR_TR16_Msk /*!< Falling trigger event configuration bit of line 16 */
+#define EXTI_FTSR_TR17_Pos (17U)
+#define EXTI_FTSR_TR17_Msk (0x1U << EXTI_FTSR_TR17_Pos) /*!< 0x00020000 */
+#define EXTI_FTSR_TR17 EXTI_FTSR_TR17_Msk /*!< Falling trigger event configuration bit of line 17 */
+#define EXTI_FTSR_TR18_Pos (18U)
+#define EXTI_FTSR_TR18_Msk (0x1U << EXTI_FTSR_TR18_Pos) /*!< 0x00040000 */
+#define EXTI_FTSR_TR18 EXTI_FTSR_TR18_Msk /*!< Falling trigger event configuration bit of line 18 */
+#define EXTI_FTSR_TR19_Pos (19U)
+#define EXTI_FTSR_TR19_Msk (0x1U << EXTI_FTSR_TR19_Pos) /*!< 0x00080000 */
+#define EXTI_FTSR_TR19 EXTI_FTSR_TR19_Msk /*!< Falling trigger event configuration bit of line 19 */
+
+/* References Defines */
+#define EXTI_FTSR_FT0 EXTI_FTSR_TR0
+#define EXTI_FTSR_FT1 EXTI_FTSR_TR1
+#define EXTI_FTSR_FT2 EXTI_FTSR_TR2
+#define EXTI_FTSR_FT3 EXTI_FTSR_TR3
+#define EXTI_FTSR_FT4 EXTI_FTSR_TR4
+#define EXTI_FTSR_FT5 EXTI_FTSR_TR5
+#define EXTI_FTSR_FT6 EXTI_FTSR_TR6
+#define EXTI_FTSR_FT7 EXTI_FTSR_TR7
+#define EXTI_FTSR_FT8 EXTI_FTSR_TR8
+#define EXTI_FTSR_FT9 EXTI_FTSR_TR9
+#define EXTI_FTSR_FT10 EXTI_FTSR_TR10
+#define EXTI_FTSR_FT11 EXTI_FTSR_TR11
+#define EXTI_FTSR_FT12 EXTI_FTSR_TR12
+#define EXTI_FTSR_FT13 EXTI_FTSR_TR13
+#define EXTI_FTSR_FT14 EXTI_FTSR_TR14
+#define EXTI_FTSR_FT15 EXTI_FTSR_TR15
+#define EXTI_FTSR_FT16 EXTI_FTSR_TR16
+#define EXTI_FTSR_FT17 EXTI_FTSR_TR17
+#define EXTI_FTSR_FT18 EXTI_FTSR_TR18
+#define EXTI_FTSR_FT19 EXTI_FTSR_TR19
+
+/****************** Bit definition for EXTI_SWIER register ******************/
+#define EXTI_SWIER_SWIER0_Pos (0U)
+#define EXTI_SWIER_SWIER0_Msk (0x1U << EXTI_SWIER_SWIER0_Pos) /*!< 0x00000001 */
+#define EXTI_SWIER_SWIER0 EXTI_SWIER_SWIER0_Msk /*!< Software Interrupt on line 0 */
+#define EXTI_SWIER_SWIER1_Pos (1U)
+#define EXTI_SWIER_SWIER1_Msk (0x1U << EXTI_SWIER_SWIER1_Pos) /*!< 0x00000002 */
+#define EXTI_SWIER_SWIER1 EXTI_SWIER_SWIER1_Msk /*!< Software Interrupt on line 1 */
+#define EXTI_SWIER_SWIER2_Pos (2U)
+#define EXTI_SWIER_SWIER2_Msk (0x1U << EXTI_SWIER_SWIER2_Pos) /*!< 0x00000004 */
+#define EXTI_SWIER_SWIER2 EXTI_SWIER_SWIER2_Msk /*!< Software Interrupt on line 2 */
+#define EXTI_SWIER_SWIER3_Pos (3U)
+#define EXTI_SWIER_SWIER3_Msk (0x1U << EXTI_SWIER_SWIER3_Pos) /*!< 0x00000008 */
+#define EXTI_SWIER_SWIER3 EXTI_SWIER_SWIER3_Msk /*!< Software Interrupt on line 3 */
+#define EXTI_SWIER_SWIER4_Pos (4U)
+#define EXTI_SWIER_SWIER4_Msk (0x1U << EXTI_SWIER_SWIER4_Pos) /*!< 0x00000010 */
+#define EXTI_SWIER_SWIER4 EXTI_SWIER_SWIER4_Msk /*!< Software Interrupt on line 4 */
+#define EXTI_SWIER_SWIER5_Pos (5U)
+#define EXTI_SWIER_SWIER5_Msk (0x1U << EXTI_SWIER_SWIER5_Pos) /*!< 0x00000020 */
+#define EXTI_SWIER_SWIER5 EXTI_SWIER_SWIER5_Msk /*!< Software Interrupt on line 5 */
+#define EXTI_SWIER_SWIER6_Pos (6U)
+#define EXTI_SWIER_SWIER6_Msk (0x1U << EXTI_SWIER_SWIER6_Pos) /*!< 0x00000040 */
+#define EXTI_SWIER_SWIER6 EXTI_SWIER_SWIER6_Msk /*!< Software Interrupt on line 6 */
+#define EXTI_SWIER_SWIER7_Pos (7U)
+#define EXTI_SWIER_SWIER7_Msk (0x1U << EXTI_SWIER_SWIER7_Pos) /*!< 0x00000080 */
+#define EXTI_SWIER_SWIER7 EXTI_SWIER_SWIER7_Msk /*!< Software Interrupt on line 7 */
+#define EXTI_SWIER_SWIER8_Pos (8U)
+#define EXTI_SWIER_SWIER8_Msk (0x1U << EXTI_SWIER_SWIER8_Pos) /*!< 0x00000100 */
+#define EXTI_SWIER_SWIER8 EXTI_SWIER_SWIER8_Msk /*!< Software Interrupt on line 8 */
+#define EXTI_SWIER_SWIER9_Pos (9U)
+#define EXTI_SWIER_SWIER9_Msk (0x1U << EXTI_SWIER_SWIER9_Pos) /*!< 0x00000200 */
+#define EXTI_SWIER_SWIER9 EXTI_SWIER_SWIER9_Msk /*!< Software Interrupt on line 9 */
+#define EXTI_SWIER_SWIER10_Pos (10U)
+#define EXTI_SWIER_SWIER10_Msk (0x1U << EXTI_SWIER_SWIER10_Pos) /*!< 0x00000400 */
+#define EXTI_SWIER_SWIER10 EXTI_SWIER_SWIER10_Msk /*!< Software Interrupt on line 10 */
+#define EXTI_SWIER_SWIER11_Pos (11U)
+#define EXTI_SWIER_SWIER11_Msk (0x1U << EXTI_SWIER_SWIER11_Pos) /*!< 0x00000800 */
+#define EXTI_SWIER_SWIER11 EXTI_SWIER_SWIER11_Msk /*!< Software Interrupt on line 11 */
+#define EXTI_SWIER_SWIER12_Pos (12U)
+#define EXTI_SWIER_SWIER12_Msk (0x1U << EXTI_SWIER_SWIER12_Pos) /*!< 0x00001000 */
+#define EXTI_SWIER_SWIER12 EXTI_SWIER_SWIER12_Msk /*!< Software Interrupt on line 12 */
+#define EXTI_SWIER_SWIER13_Pos (13U)
+#define EXTI_SWIER_SWIER13_Msk (0x1U << EXTI_SWIER_SWIER13_Pos) /*!< 0x00002000 */
+#define EXTI_SWIER_SWIER13 EXTI_SWIER_SWIER13_Msk /*!< Software Interrupt on line 13 */
+#define EXTI_SWIER_SWIER14_Pos (14U)
+#define EXTI_SWIER_SWIER14_Msk (0x1U << EXTI_SWIER_SWIER14_Pos) /*!< 0x00004000 */
+#define EXTI_SWIER_SWIER14 EXTI_SWIER_SWIER14_Msk /*!< Software Interrupt on line 14 */
+#define EXTI_SWIER_SWIER15_Pos (15U)
+#define EXTI_SWIER_SWIER15_Msk (0x1U << EXTI_SWIER_SWIER15_Pos) /*!< 0x00008000 */
+#define EXTI_SWIER_SWIER15 EXTI_SWIER_SWIER15_Msk /*!< Software Interrupt on line 15 */
+#define EXTI_SWIER_SWIER16_Pos (16U)
+#define EXTI_SWIER_SWIER16_Msk (0x1U << EXTI_SWIER_SWIER16_Pos) /*!< 0x00010000 */
+#define EXTI_SWIER_SWIER16 EXTI_SWIER_SWIER16_Msk /*!< Software Interrupt on line 16 */
+#define EXTI_SWIER_SWIER17_Pos (17U)
+#define EXTI_SWIER_SWIER17_Msk (0x1U << EXTI_SWIER_SWIER17_Pos) /*!< 0x00020000 */
+#define EXTI_SWIER_SWIER17 EXTI_SWIER_SWIER17_Msk /*!< Software Interrupt on line 17 */
+#define EXTI_SWIER_SWIER18_Pos (18U)
+#define EXTI_SWIER_SWIER18_Msk (0x1U << EXTI_SWIER_SWIER18_Pos) /*!< 0x00040000 */
+#define EXTI_SWIER_SWIER18 EXTI_SWIER_SWIER18_Msk /*!< Software Interrupt on line 18 */
+#define EXTI_SWIER_SWIER19_Pos (19U)
+#define EXTI_SWIER_SWIER19_Msk (0x1U << EXTI_SWIER_SWIER19_Pos) /*!< 0x00080000 */
+#define EXTI_SWIER_SWIER19 EXTI_SWIER_SWIER19_Msk /*!< Software Interrupt on line 19 */
+
+/* References Defines */
+#define EXTI_SWIER_SWI0 EXTI_SWIER_SWIER0
+#define EXTI_SWIER_SWI1 EXTI_SWIER_SWIER1
+#define EXTI_SWIER_SWI2 EXTI_SWIER_SWIER2
+#define EXTI_SWIER_SWI3 EXTI_SWIER_SWIER3
+#define EXTI_SWIER_SWI4 EXTI_SWIER_SWIER4
+#define EXTI_SWIER_SWI5 EXTI_SWIER_SWIER5
+#define EXTI_SWIER_SWI6 EXTI_SWIER_SWIER6
+#define EXTI_SWIER_SWI7 EXTI_SWIER_SWIER7
+#define EXTI_SWIER_SWI8 EXTI_SWIER_SWIER8
+#define EXTI_SWIER_SWI9 EXTI_SWIER_SWIER9
+#define EXTI_SWIER_SWI10 EXTI_SWIER_SWIER10
+#define EXTI_SWIER_SWI11 EXTI_SWIER_SWIER11
+#define EXTI_SWIER_SWI12 EXTI_SWIER_SWIER12
+#define EXTI_SWIER_SWI13 EXTI_SWIER_SWIER13
+#define EXTI_SWIER_SWI14 EXTI_SWIER_SWIER14
+#define EXTI_SWIER_SWI15 EXTI_SWIER_SWIER15
+#define EXTI_SWIER_SWI16 EXTI_SWIER_SWIER16
+#define EXTI_SWIER_SWI17 EXTI_SWIER_SWIER17
+#define EXTI_SWIER_SWI18 EXTI_SWIER_SWIER18
+#define EXTI_SWIER_SWI19 EXTI_SWIER_SWIER19
+
+/******************* Bit definition for EXTI_PR register ********************/
+#define EXTI_PR_PR0_Pos (0U)
+#define EXTI_PR_PR0_Msk (0x1U << EXTI_PR_PR0_Pos) /*!< 0x00000001 */
+#define EXTI_PR_PR0 EXTI_PR_PR0_Msk /*!< Pending bit for line 0 */
+#define EXTI_PR_PR1_Pos (1U)
+#define EXTI_PR_PR1_Msk (0x1U << EXTI_PR_PR1_Pos) /*!< 0x00000002 */
+#define EXTI_PR_PR1 EXTI_PR_PR1_Msk /*!< Pending bit for line 1 */
+#define EXTI_PR_PR2_Pos (2U)
+#define EXTI_PR_PR2_Msk (0x1U << EXTI_PR_PR2_Pos) /*!< 0x00000004 */
+#define EXTI_PR_PR2 EXTI_PR_PR2_Msk /*!< Pending bit for line 2 */
+#define EXTI_PR_PR3_Pos (3U)
+#define EXTI_PR_PR3_Msk (0x1U << EXTI_PR_PR3_Pos) /*!< 0x00000008 */
+#define EXTI_PR_PR3 EXTI_PR_PR3_Msk /*!< Pending bit for line 3 */
+#define EXTI_PR_PR4_Pos (4U)
+#define EXTI_PR_PR4_Msk (0x1U << EXTI_PR_PR4_Pos) /*!< 0x00000010 */
+#define EXTI_PR_PR4 EXTI_PR_PR4_Msk /*!< Pending bit for line 4 */
+#define EXTI_PR_PR5_Pos (5U)
+#define EXTI_PR_PR5_Msk (0x1U << EXTI_PR_PR5_Pos) /*!< 0x00000020 */
+#define EXTI_PR_PR5 EXTI_PR_PR5_Msk /*!< Pending bit for line 5 */
+#define EXTI_PR_PR6_Pos (6U)
+#define EXTI_PR_PR6_Msk (0x1U << EXTI_PR_PR6_Pos) /*!< 0x00000040 */
+#define EXTI_PR_PR6 EXTI_PR_PR6_Msk /*!< Pending bit for line 6 */
+#define EXTI_PR_PR7_Pos (7U)
+#define EXTI_PR_PR7_Msk (0x1U << EXTI_PR_PR7_Pos) /*!< 0x00000080 */
+#define EXTI_PR_PR7 EXTI_PR_PR7_Msk /*!< Pending bit for line 7 */
+#define EXTI_PR_PR8_Pos (8U)
+#define EXTI_PR_PR8_Msk (0x1U << EXTI_PR_PR8_Pos) /*!< 0x00000100 */
+#define EXTI_PR_PR8 EXTI_PR_PR8_Msk /*!< Pending bit for line 8 */
+#define EXTI_PR_PR9_Pos (9U)
+#define EXTI_PR_PR9_Msk (0x1U << EXTI_PR_PR9_Pos) /*!< 0x00000200 */
+#define EXTI_PR_PR9 EXTI_PR_PR9_Msk /*!< Pending bit for line 9 */
+#define EXTI_PR_PR10_Pos (10U)
+#define EXTI_PR_PR10_Msk (0x1U << EXTI_PR_PR10_Pos) /*!< 0x00000400 */
+#define EXTI_PR_PR10 EXTI_PR_PR10_Msk /*!< Pending bit for line 10 */
+#define EXTI_PR_PR11_Pos (11U)
+#define EXTI_PR_PR11_Msk (0x1U << EXTI_PR_PR11_Pos) /*!< 0x00000800 */
+#define EXTI_PR_PR11 EXTI_PR_PR11_Msk /*!< Pending bit for line 11 */
+#define EXTI_PR_PR12_Pos (12U)
+#define EXTI_PR_PR12_Msk (0x1U << EXTI_PR_PR12_Pos) /*!< 0x00001000 */
+#define EXTI_PR_PR12 EXTI_PR_PR12_Msk /*!< Pending bit for line 12 */
+#define EXTI_PR_PR13_Pos (13U)
+#define EXTI_PR_PR13_Msk (0x1U << EXTI_PR_PR13_Pos) /*!< 0x00002000 */
+#define EXTI_PR_PR13 EXTI_PR_PR13_Msk /*!< Pending bit for line 13 */
+#define EXTI_PR_PR14_Pos (14U)
+#define EXTI_PR_PR14_Msk (0x1U << EXTI_PR_PR14_Pos) /*!< 0x00004000 */
+#define EXTI_PR_PR14 EXTI_PR_PR14_Msk /*!< Pending bit for line 14 */
+#define EXTI_PR_PR15_Pos (15U)
+#define EXTI_PR_PR15_Msk (0x1U << EXTI_PR_PR15_Pos) /*!< 0x00008000 */
+#define EXTI_PR_PR15 EXTI_PR_PR15_Msk /*!< Pending bit for line 15 */
+#define EXTI_PR_PR16_Pos (16U)
+#define EXTI_PR_PR16_Msk (0x1U << EXTI_PR_PR16_Pos) /*!< 0x00010000 */
+#define EXTI_PR_PR16 EXTI_PR_PR16_Msk /*!< Pending bit for line 16 */
+#define EXTI_PR_PR17_Pos (17U)
+#define EXTI_PR_PR17_Msk (0x1U << EXTI_PR_PR17_Pos) /*!< 0x00020000 */
+#define EXTI_PR_PR17 EXTI_PR_PR17_Msk /*!< Pending bit for line 17 */
+#define EXTI_PR_PR18_Pos (18U)
+#define EXTI_PR_PR18_Msk (0x1U << EXTI_PR_PR18_Pos) /*!< 0x00040000 */
+#define EXTI_PR_PR18 EXTI_PR_PR18_Msk /*!< Pending bit for line 18 */
+#define EXTI_PR_PR19_Pos (19U)
+#define EXTI_PR_PR19_Msk (0x1U << EXTI_PR_PR19_Pos) /*!< 0x00080000 */
+#define EXTI_PR_PR19 EXTI_PR_PR19_Msk /*!< Pending bit for line 19 */
+
+/* References Defines */
+#define EXTI_PR_PIF0 EXTI_PR_PR0
+#define EXTI_PR_PIF1 EXTI_PR_PR1
+#define EXTI_PR_PIF2 EXTI_PR_PR2
+#define EXTI_PR_PIF3 EXTI_PR_PR3
+#define EXTI_PR_PIF4 EXTI_PR_PR4
+#define EXTI_PR_PIF5 EXTI_PR_PR5
+#define EXTI_PR_PIF6 EXTI_PR_PR6
+#define EXTI_PR_PIF7 EXTI_PR_PR7
+#define EXTI_PR_PIF8 EXTI_PR_PR8
+#define EXTI_PR_PIF9 EXTI_PR_PR9
+#define EXTI_PR_PIF10 EXTI_PR_PR10
+#define EXTI_PR_PIF11 EXTI_PR_PR11
+#define EXTI_PR_PIF12 EXTI_PR_PR12
+#define EXTI_PR_PIF13 EXTI_PR_PR13
+#define EXTI_PR_PIF14 EXTI_PR_PR14
+#define EXTI_PR_PIF15 EXTI_PR_PR15
+#define EXTI_PR_PIF16 EXTI_PR_PR16
+#define EXTI_PR_PIF17 EXTI_PR_PR17
+#define EXTI_PR_PIF18 EXTI_PR_PR18
+#define EXTI_PR_PIF19 EXTI_PR_PR19
+
+/******************************************************************************/
+/* */
+/* DMA Controller */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for DMA_ISR register ********************/
+#define DMA_ISR_GIF1_Pos (0U)
+#define DMA_ISR_GIF1_Msk (0x1U << DMA_ISR_GIF1_Pos) /*!< 0x00000001 */
+#define DMA_ISR_GIF1 DMA_ISR_GIF1_Msk /*!< Channel 1 Global interrupt flag */
+#define DMA_ISR_TCIF1_Pos (1U)
+#define DMA_ISR_TCIF1_Msk (0x1U << DMA_ISR_TCIF1_Pos) /*!< 0x00000002 */
+#define DMA_ISR_TCIF1 DMA_ISR_TCIF1_Msk /*!< Channel 1 Transfer Complete flag */
+#define DMA_ISR_HTIF1_Pos (2U)
+#define DMA_ISR_HTIF1_Msk (0x1U << DMA_ISR_HTIF1_Pos) /*!< 0x00000004 */
+#define DMA_ISR_HTIF1 DMA_ISR_HTIF1_Msk /*!< Channel 1 Half Transfer flag */
+#define DMA_ISR_TEIF1_Pos (3U)
+#define DMA_ISR_TEIF1_Msk (0x1U << DMA_ISR_TEIF1_Pos) /*!< 0x00000008 */
+#define DMA_ISR_TEIF1 DMA_ISR_TEIF1_Msk /*!< Channel 1 Transfer Error flag */
+#define DMA_ISR_GIF2_Pos (4U)
+#define DMA_ISR_GIF2_Msk (0x1U << DMA_ISR_GIF2_Pos) /*!< 0x00000010 */
+#define DMA_ISR_GIF2 DMA_ISR_GIF2_Msk /*!< Channel 2 Global interrupt flag */
+#define DMA_ISR_TCIF2_Pos (5U)
+#define DMA_ISR_TCIF2_Msk (0x1U << DMA_ISR_TCIF2_Pos) /*!< 0x00000020 */
+#define DMA_ISR_TCIF2 DMA_ISR_TCIF2_Msk /*!< Channel 2 Transfer Complete flag */
+#define DMA_ISR_HTIF2_Pos (6U)
+#define DMA_ISR_HTIF2_Msk (0x1U << DMA_ISR_HTIF2_Pos) /*!< 0x00000040 */
+#define DMA_ISR_HTIF2 DMA_ISR_HTIF2_Msk /*!< Channel 2 Half Transfer flag */
+#define DMA_ISR_TEIF2_Pos (7U)
+#define DMA_ISR_TEIF2_Msk (0x1U << DMA_ISR_TEIF2_Pos) /*!< 0x00000080 */
+#define DMA_ISR_TEIF2 DMA_ISR_TEIF2_Msk /*!< Channel 2 Transfer Error flag */
+#define DMA_ISR_GIF3_Pos (8U)
+#define DMA_ISR_GIF3_Msk (0x1U << DMA_ISR_GIF3_Pos) /*!< 0x00000100 */
+#define DMA_ISR_GIF3 DMA_ISR_GIF3_Msk /*!< Channel 3 Global interrupt flag */
+#define DMA_ISR_TCIF3_Pos (9U)
+#define DMA_ISR_TCIF3_Msk (0x1U << DMA_ISR_TCIF3_Pos) /*!< 0x00000200 */
+#define DMA_ISR_TCIF3 DMA_ISR_TCIF3_Msk /*!< Channel 3 Transfer Complete flag */
+#define DMA_ISR_HTIF3_Pos (10U)
+#define DMA_ISR_HTIF3_Msk (0x1U << DMA_ISR_HTIF3_Pos) /*!< 0x00000400 */
+#define DMA_ISR_HTIF3 DMA_ISR_HTIF3_Msk /*!< Channel 3 Half Transfer flag */
+#define DMA_ISR_TEIF3_Pos (11U)
+#define DMA_ISR_TEIF3_Msk (0x1U << DMA_ISR_TEIF3_Pos) /*!< 0x00000800 */
+#define DMA_ISR_TEIF3 DMA_ISR_TEIF3_Msk /*!< Channel 3 Transfer Error flag */
+#define DMA_ISR_GIF4_Pos (12U)
+#define DMA_ISR_GIF4_Msk (0x1U << DMA_ISR_GIF4_Pos) /*!< 0x00001000 */
+#define DMA_ISR_GIF4 DMA_ISR_GIF4_Msk /*!< Channel 4 Global interrupt flag */
+#define DMA_ISR_TCIF4_Pos (13U)
+#define DMA_ISR_TCIF4_Msk (0x1U << DMA_ISR_TCIF4_Pos) /*!< 0x00002000 */
+#define DMA_ISR_TCIF4 DMA_ISR_TCIF4_Msk /*!< Channel 4 Transfer Complete flag */
+#define DMA_ISR_HTIF4_Pos (14U)
+#define DMA_ISR_HTIF4_Msk (0x1U << DMA_ISR_HTIF4_Pos) /*!< 0x00004000 */
+#define DMA_ISR_HTIF4 DMA_ISR_HTIF4_Msk /*!< Channel 4 Half Transfer flag */
+#define DMA_ISR_TEIF4_Pos (15U)
+#define DMA_ISR_TEIF4_Msk (0x1U << DMA_ISR_TEIF4_Pos) /*!< 0x00008000 */
+#define DMA_ISR_TEIF4 DMA_ISR_TEIF4_Msk /*!< Channel 4 Transfer Error flag */
+#define DMA_ISR_GIF5_Pos (16U)
+#define DMA_ISR_GIF5_Msk (0x1U << DMA_ISR_GIF5_Pos) /*!< 0x00010000 */
+#define DMA_ISR_GIF5 DMA_ISR_GIF5_Msk /*!< Channel 5 Global interrupt flag */
+#define DMA_ISR_TCIF5_Pos (17U)
+#define DMA_ISR_TCIF5_Msk (0x1U << DMA_ISR_TCIF5_Pos) /*!< 0x00020000 */
+#define DMA_ISR_TCIF5 DMA_ISR_TCIF5_Msk /*!< Channel 5 Transfer Complete flag */
+#define DMA_ISR_HTIF5_Pos (18U)
+#define DMA_ISR_HTIF5_Msk (0x1U << DMA_ISR_HTIF5_Pos) /*!< 0x00040000 */
+#define DMA_ISR_HTIF5 DMA_ISR_HTIF5_Msk /*!< Channel 5 Half Transfer flag */
+#define DMA_ISR_TEIF5_Pos (19U)
+#define DMA_ISR_TEIF5_Msk (0x1U << DMA_ISR_TEIF5_Pos) /*!< 0x00080000 */
+#define DMA_ISR_TEIF5 DMA_ISR_TEIF5_Msk /*!< Channel 5 Transfer Error flag */
+#define DMA_ISR_GIF6_Pos (20U)
+#define DMA_ISR_GIF6_Msk (0x1U << DMA_ISR_GIF6_Pos) /*!< 0x00100000 */
+#define DMA_ISR_GIF6 DMA_ISR_GIF6_Msk /*!< Channel 6 Global interrupt flag */
+#define DMA_ISR_TCIF6_Pos (21U)
+#define DMA_ISR_TCIF6_Msk (0x1U << DMA_ISR_TCIF6_Pos) /*!< 0x00200000 */
+#define DMA_ISR_TCIF6 DMA_ISR_TCIF6_Msk /*!< Channel 6 Transfer Complete flag */
+#define DMA_ISR_HTIF6_Pos (22U)
+#define DMA_ISR_HTIF6_Msk (0x1U << DMA_ISR_HTIF6_Pos) /*!< 0x00400000 */
+#define DMA_ISR_HTIF6 DMA_ISR_HTIF6_Msk /*!< Channel 6 Half Transfer flag */
+#define DMA_ISR_TEIF6_Pos (23U)
+#define DMA_ISR_TEIF6_Msk (0x1U << DMA_ISR_TEIF6_Pos) /*!< 0x00800000 */
+#define DMA_ISR_TEIF6 DMA_ISR_TEIF6_Msk /*!< Channel 6 Transfer Error flag */
+#define DMA_ISR_GIF7_Pos (24U)
+#define DMA_ISR_GIF7_Msk (0x1U << DMA_ISR_GIF7_Pos) /*!< 0x01000000 */
+#define DMA_ISR_GIF7 DMA_ISR_GIF7_Msk /*!< Channel 7 Global interrupt flag */
+#define DMA_ISR_TCIF7_Pos (25U)
+#define DMA_ISR_TCIF7_Msk (0x1U << DMA_ISR_TCIF7_Pos) /*!< 0x02000000 */
+#define DMA_ISR_TCIF7 DMA_ISR_TCIF7_Msk /*!< Channel 7 Transfer Complete flag */
+#define DMA_ISR_HTIF7_Pos (26U)
+#define DMA_ISR_HTIF7_Msk (0x1U << DMA_ISR_HTIF7_Pos) /*!< 0x04000000 */
+#define DMA_ISR_HTIF7 DMA_ISR_HTIF7_Msk /*!< Channel 7 Half Transfer flag */
+#define DMA_ISR_TEIF7_Pos (27U)
+#define DMA_ISR_TEIF7_Msk (0x1U << DMA_ISR_TEIF7_Pos) /*!< 0x08000000 */
+#define DMA_ISR_TEIF7 DMA_ISR_TEIF7_Msk /*!< Channel 7 Transfer Error flag */
+
+/******************* Bit definition for DMA_IFCR register *******************/
+#define DMA_IFCR_CGIF1_Pos (0U)
+#define DMA_IFCR_CGIF1_Msk (0x1U << DMA_IFCR_CGIF1_Pos) /*!< 0x00000001 */
+#define DMA_IFCR_CGIF1 DMA_IFCR_CGIF1_Msk /*!< Channel 1 Global interrupt clear */
+#define DMA_IFCR_CTCIF1_Pos (1U)
+#define DMA_IFCR_CTCIF1_Msk (0x1U << DMA_IFCR_CTCIF1_Pos) /*!< 0x00000002 */
+#define DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF1_Msk /*!< Channel 1 Transfer Complete clear */
+#define DMA_IFCR_CHTIF1_Pos (2U)
+#define DMA_IFCR_CHTIF1_Msk (0x1U << DMA_IFCR_CHTIF1_Pos) /*!< 0x00000004 */
+#define DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF1_Msk /*!< Channel 1 Half Transfer clear */
+#define DMA_IFCR_CTEIF1_Pos (3U)
+#define DMA_IFCR_CTEIF1_Msk (0x1U << DMA_IFCR_CTEIF1_Pos) /*!< 0x00000008 */
+#define DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF1_Msk /*!< Channel 1 Transfer Error clear */
+#define DMA_IFCR_CGIF2_Pos (4U)
+#define DMA_IFCR_CGIF2_Msk (0x1U << DMA_IFCR_CGIF2_Pos) /*!< 0x00000010 */
+#define DMA_IFCR_CGIF2 DMA_IFCR_CGIF2_Msk /*!< Channel 2 Global interrupt clear */
+#define DMA_IFCR_CTCIF2_Pos (5U)
+#define DMA_IFCR_CTCIF2_Msk (0x1U << DMA_IFCR_CTCIF2_Pos) /*!< 0x00000020 */
+#define DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF2_Msk /*!< Channel 2 Transfer Complete clear */
+#define DMA_IFCR_CHTIF2_Pos (6U)
+#define DMA_IFCR_CHTIF2_Msk (0x1U << DMA_IFCR_CHTIF2_Pos) /*!< 0x00000040 */
+#define DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF2_Msk /*!< Channel 2 Half Transfer clear */
+#define DMA_IFCR_CTEIF2_Pos (7U)
+#define DMA_IFCR_CTEIF2_Msk (0x1U << DMA_IFCR_CTEIF2_Pos) /*!< 0x00000080 */
+#define DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF2_Msk /*!< Channel 2 Transfer Error clear */
+#define DMA_IFCR_CGIF3_Pos (8U)
+#define DMA_IFCR_CGIF3_Msk (0x1U << DMA_IFCR_CGIF3_Pos) /*!< 0x00000100 */
+#define DMA_IFCR_CGIF3 DMA_IFCR_CGIF3_Msk /*!< Channel 3 Global interrupt clear */
+#define DMA_IFCR_CTCIF3_Pos (9U)
+#define DMA_IFCR_CTCIF3_Msk (0x1U << DMA_IFCR_CTCIF3_Pos) /*!< 0x00000200 */
+#define DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF3_Msk /*!< Channel 3 Transfer Complete clear */
+#define DMA_IFCR_CHTIF3_Pos (10U)
+#define DMA_IFCR_CHTIF3_Msk (0x1U << DMA_IFCR_CHTIF3_Pos) /*!< 0x00000400 */
+#define DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF3_Msk /*!< Channel 3 Half Transfer clear */
+#define DMA_IFCR_CTEIF3_Pos (11U)
+#define DMA_IFCR_CTEIF3_Msk (0x1U << DMA_IFCR_CTEIF3_Pos) /*!< 0x00000800 */
+#define DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF3_Msk /*!< Channel 3 Transfer Error clear */
+#define DMA_IFCR_CGIF4_Pos (12U)
+#define DMA_IFCR_CGIF4_Msk (0x1U << DMA_IFCR_CGIF4_Pos) /*!< 0x00001000 */
+#define DMA_IFCR_CGIF4 DMA_IFCR_CGIF4_Msk /*!< Channel 4 Global interrupt clear */
+#define DMA_IFCR_CTCIF4_Pos (13U)
+#define DMA_IFCR_CTCIF4_Msk (0x1U << DMA_IFCR_CTCIF4_Pos) /*!< 0x00002000 */
+#define DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF4_Msk /*!< Channel 4 Transfer Complete clear */
+#define DMA_IFCR_CHTIF4_Pos (14U)
+#define DMA_IFCR_CHTIF4_Msk (0x1U << DMA_IFCR_CHTIF4_Pos) /*!< 0x00004000 */
+#define DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF4_Msk /*!< Channel 4 Half Transfer clear */
+#define DMA_IFCR_CTEIF4_Pos (15U)
+#define DMA_IFCR_CTEIF4_Msk (0x1U << DMA_IFCR_CTEIF4_Pos) /*!< 0x00008000 */
+#define DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF4_Msk /*!< Channel 4 Transfer Error clear */
+#define DMA_IFCR_CGIF5_Pos (16U)
+#define DMA_IFCR_CGIF5_Msk (0x1U << DMA_IFCR_CGIF5_Pos) /*!< 0x00010000 */
+#define DMA_IFCR_CGIF5 DMA_IFCR_CGIF5_Msk /*!< Channel 5 Global interrupt clear */
+#define DMA_IFCR_CTCIF5_Pos (17U)
+#define DMA_IFCR_CTCIF5_Msk (0x1U << DMA_IFCR_CTCIF5_Pos) /*!< 0x00020000 */
+#define DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF5_Msk /*!< Channel 5 Transfer Complete clear */
+#define DMA_IFCR_CHTIF5_Pos (18U)
+#define DMA_IFCR_CHTIF5_Msk (0x1U << DMA_IFCR_CHTIF5_Pos) /*!< 0x00040000 */
+#define DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5_Msk /*!< Channel 5 Half Transfer clear */
+#define DMA_IFCR_CTEIF5_Pos (19U)
+#define DMA_IFCR_CTEIF5_Msk (0x1U << DMA_IFCR_CTEIF5_Pos) /*!< 0x00080000 */
+#define DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF5_Msk /*!< Channel 5 Transfer Error clear */
+#define DMA_IFCR_CGIF6_Pos (20U)
+#define DMA_IFCR_CGIF6_Msk (0x1U << DMA_IFCR_CGIF6_Pos) /*!< 0x00100000 */
+#define DMA_IFCR_CGIF6 DMA_IFCR_CGIF6_Msk /*!< Channel 6 Global interrupt clear */
+#define DMA_IFCR_CTCIF6_Pos (21U)
+#define DMA_IFCR_CTCIF6_Msk (0x1U << DMA_IFCR_CTCIF6_Pos) /*!< 0x00200000 */
+#define DMA_IFCR_CTCIF6 DMA_IFCR_CTCIF6_Msk /*!< Channel 6 Transfer Complete clear */
+#define DMA_IFCR_CHTIF6_Pos (22U)
+#define DMA_IFCR_CHTIF6_Msk (0x1U << DMA_IFCR_CHTIF6_Pos) /*!< 0x00400000 */
+#define DMA_IFCR_CHTIF6 DMA_IFCR_CHTIF6_Msk /*!< Channel 6 Half Transfer clear */
+#define DMA_IFCR_CTEIF6_Pos (23U)
+#define DMA_IFCR_CTEIF6_Msk (0x1U << DMA_IFCR_CTEIF6_Pos) /*!< 0x00800000 */
+#define DMA_IFCR_CTEIF6 DMA_IFCR_CTEIF6_Msk /*!< Channel 6 Transfer Error clear */
+#define DMA_IFCR_CGIF7_Pos (24U)
+#define DMA_IFCR_CGIF7_Msk (0x1U << DMA_IFCR_CGIF7_Pos) /*!< 0x01000000 */
+#define DMA_IFCR_CGIF7 DMA_IFCR_CGIF7_Msk /*!< Channel 7 Global interrupt clear */
+#define DMA_IFCR_CTCIF7_Pos (25U)
+#define DMA_IFCR_CTCIF7_Msk (0x1U << DMA_IFCR_CTCIF7_Pos) /*!< 0x02000000 */
+#define DMA_IFCR_CTCIF7 DMA_IFCR_CTCIF7_Msk /*!< Channel 7 Transfer Complete clear */
+#define DMA_IFCR_CHTIF7_Pos (26U)
+#define DMA_IFCR_CHTIF7_Msk (0x1U << DMA_IFCR_CHTIF7_Pos) /*!< 0x04000000 */
+#define DMA_IFCR_CHTIF7 DMA_IFCR_CHTIF7_Msk /*!< Channel 7 Half Transfer clear */
+#define DMA_IFCR_CTEIF7_Pos (27U)
+#define DMA_IFCR_CTEIF7_Msk (0x1U << DMA_IFCR_CTEIF7_Pos) /*!< 0x08000000 */
+#define DMA_IFCR_CTEIF7 DMA_IFCR_CTEIF7_Msk /*!< Channel 7 Transfer Error clear */
+
+/******************* Bit definition for DMA_CCR register *******************/
+#define DMA_CCR_EN_Pos (0U)
+#define DMA_CCR_EN_Msk (0x1U << DMA_CCR_EN_Pos) /*!< 0x00000001 */
+#define DMA_CCR_EN DMA_CCR_EN_Msk /*!< Channel enable */
+#define DMA_CCR_TCIE_Pos (1U)
+#define DMA_CCR_TCIE_Msk (0x1U << DMA_CCR_TCIE_Pos) /*!< 0x00000002 */
+#define DMA_CCR_TCIE DMA_CCR_TCIE_Msk /*!< Transfer complete interrupt enable */
+#define DMA_CCR_HTIE_Pos (2U)
+#define DMA_CCR_HTIE_Msk (0x1U << DMA_CCR_HTIE_Pos) /*!< 0x00000004 */
+#define DMA_CCR_HTIE DMA_CCR_HTIE_Msk /*!< Half Transfer interrupt enable */
+#define DMA_CCR_TEIE_Pos (3U)
+#define DMA_CCR_TEIE_Msk (0x1U << DMA_CCR_TEIE_Pos) /*!< 0x00000008 */
+#define DMA_CCR_TEIE DMA_CCR_TEIE_Msk /*!< Transfer error interrupt enable */
+#define DMA_CCR_DIR_Pos (4U)
+#define DMA_CCR_DIR_Msk (0x1U << DMA_CCR_DIR_Pos) /*!< 0x00000010 */
+#define DMA_CCR_DIR DMA_CCR_DIR_Msk /*!< Data transfer direction */
+#define DMA_CCR_CIRC_Pos (5U)
+#define DMA_CCR_CIRC_Msk (0x1U << DMA_CCR_CIRC_Pos) /*!< 0x00000020 */
+#define DMA_CCR_CIRC DMA_CCR_CIRC_Msk /*!< Circular mode */
+#define DMA_CCR_PINC_Pos (6U)
+#define DMA_CCR_PINC_Msk (0x1U << DMA_CCR_PINC_Pos) /*!< 0x00000040 */
+#define DMA_CCR_PINC DMA_CCR_PINC_Msk /*!< Peripheral increment mode */
+#define DMA_CCR_MINC_Pos (7U)
+#define DMA_CCR_MINC_Msk (0x1U << DMA_CCR_MINC_Pos) /*!< 0x00000080 */
+#define DMA_CCR_MINC DMA_CCR_MINC_Msk /*!< Memory increment mode */
+
+#define DMA_CCR_PSIZE_Pos (8U)
+#define DMA_CCR_PSIZE_Msk (0x3U << DMA_CCR_PSIZE_Pos) /*!< 0x00000300 */
+#define DMA_CCR_PSIZE DMA_CCR_PSIZE_Msk /*!< PSIZE[1:0] bits (Peripheral size) */
+#define DMA_CCR_PSIZE_0 (0x1U << DMA_CCR_PSIZE_Pos) /*!< 0x00000100 */
+#define DMA_CCR_PSIZE_1 (0x2U << DMA_CCR_PSIZE_Pos) /*!< 0x00000200 */
+
+#define DMA_CCR_MSIZE_Pos (10U)
+#define DMA_CCR_MSIZE_Msk (0x3U << DMA_CCR_MSIZE_Pos) /*!< 0x00000C00 */
+#define DMA_CCR_MSIZE DMA_CCR_MSIZE_Msk /*!< MSIZE[1:0] bits (Memory size) */
+#define DMA_CCR_MSIZE_0 (0x1U << DMA_CCR_MSIZE_Pos) /*!< 0x00000400 */
+#define DMA_CCR_MSIZE_1 (0x2U << DMA_CCR_MSIZE_Pos) /*!< 0x00000800 */
+
+#define DMA_CCR_PL_Pos (12U)
+#define DMA_CCR_PL_Msk (0x3U << DMA_CCR_PL_Pos) /*!< 0x00003000 */
+#define DMA_CCR_PL DMA_CCR_PL_Msk /*!< PL[1:0] bits(Channel Priority level) */
+#define DMA_CCR_PL_0 (0x1U << DMA_CCR_PL_Pos) /*!< 0x00001000 */
+#define DMA_CCR_PL_1 (0x2U << DMA_CCR_PL_Pos) /*!< 0x00002000 */
+
+#define DMA_CCR_MEM2MEM_Pos (14U)
+#define DMA_CCR_MEM2MEM_Msk (0x1U << DMA_CCR_MEM2MEM_Pos) /*!< 0x00004000 */
+#define DMA_CCR_MEM2MEM DMA_CCR_MEM2MEM_Msk /*!< Memory to memory mode */
+
+/****************** Bit definition for DMA_CNDTR register ******************/
+#define DMA_CNDTR_NDT_Pos (0U)
+#define DMA_CNDTR_NDT_Msk (0xFFFFU << DMA_CNDTR_NDT_Pos) /*!< 0x0000FFFF */
+#define DMA_CNDTR_NDT DMA_CNDTR_NDT_Msk /*!< Number of data to Transfer */
+
+/****************** Bit definition for DMA_CPAR register *******************/
+#define DMA_CPAR_PA_Pos (0U)
+#define DMA_CPAR_PA_Msk (0xFFFFFFFFU << DMA_CPAR_PA_Pos) /*!< 0xFFFFFFFF */
+#define DMA_CPAR_PA DMA_CPAR_PA_Msk /*!< Peripheral Address */
+
+/****************** Bit definition for DMA_CMAR register *******************/
+#define DMA_CMAR_MA_Pos (0U)
+#define DMA_CMAR_MA_Msk (0xFFFFFFFFU << DMA_CMAR_MA_Pos) /*!< 0xFFFFFFFF */
+#define DMA_CMAR_MA DMA_CMAR_MA_Msk /*!< Memory Address */
+
+/******************************************************************************/
+/* */
+/* Analog to Digital Converter (ADC) */
+/* */
+/******************************************************************************/
+
+/*
+ * @brief Specific device feature definitions (not present on all devices in the STM32F1 family)
+ */
+#define ADC_MULTIMODE_SUPPORT /*!< ADC feature available only on specific devices: multimode available on devices with several ADC instances */
+
+/******************** Bit definition for ADC_SR register ********************/
+#define ADC_SR_AWD_Pos (0U)
+#define ADC_SR_AWD_Msk (0x1U << ADC_SR_AWD_Pos) /*!< 0x00000001 */
+#define ADC_SR_AWD ADC_SR_AWD_Msk /*!< ADC analog watchdog 1 flag */
+#define ADC_SR_EOS_Pos (1U)
+#define ADC_SR_EOS_Msk (0x1U << ADC_SR_EOS_Pos) /*!< 0x00000002 */
+#define ADC_SR_EOS ADC_SR_EOS_Msk /*!< ADC group regular end of sequence conversions flag */
+#define ADC_SR_JEOS_Pos (2U)
+#define ADC_SR_JEOS_Msk (0x1U << ADC_SR_JEOS_Pos) /*!< 0x00000004 */
+#define ADC_SR_JEOS ADC_SR_JEOS_Msk /*!< ADC group injected end of sequence conversions flag */
+#define ADC_SR_JSTRT_Pos (3U)
+#define ADC_SR_JSTRT_Msk (0x1U << ADC_SR_JSTRT_Pos) /*!< 0x00000008 */
+#define ADC_SR_JSTRT ADC_SR_JSTRT_Msk /*!< ADC group injected conversion start flag */
+#define ADC_SR_STRT_Pos (4U)
+#define ADC_SR_STRT_Msk (0x1U << ADC_SR_STRT_Pos) /*!< 0x00000010 */
+#define ADC_SR_STRT ADC_SR_STRT_Msk /*!< ADC group regular conversion start flag */
+
+/* Legacy defines */
+#define ADC_SR_EOC (ADC_SR_EOS)
+#define ADC_SR_JEOC (ADC_SR_JEOS)
+
+/******************* Bit definition for ADC_CR1 register ********************/
+#define ADC_CR1_AWDCH_Pos (0U)
+#define ADC_CR1_AWDCH_Msk (0x1FU << ADC_CR1_AWDCH_Pos) /*!< 0x0000001F */
+#define ADC_CR1_AWDCH ADC_CR1_AWDCH_Msk /*!< ADC analog watchdog 1 monitored channel selection */
+#define ADC_CR1_AWDCH_0 (0x01U << ADC_CR1_AWDCH_Pos) /*!< 0x00000001 */
+#define ADC_CR1_AWDCH_1 (0x02U << ADC_CR1_AWDCH_Pos) /*!< 0x00000002 */
+#define ADC_CR1_AWDCH_2 (0x04U << ADC_CR1_AWDCH_Pos) /*!< 0x00000004 */
+#define ADC_CR1_AWDCH_3 (0x08U << ADC_CR1_AWDCH_Pos) /*!< 0x00000008 */
+#define ADC_CR1_AWDCH_4 (0x10U << ADC_CR1_AWDCH_Pos) /*!< 0x00000010 */
+
+#define ADC_CR1_EOSIE_Pos (5U)
+#define ADC_CR1_EOSIE_Msk (0x1U << ADC_CR1_EOSIE_Pos) /*!< 0x00000020 */
+#define ADC_CR1_EOSIE ADC_CR1_EOSIE_Msk /*!< ADC group regular end of sequence conversions interrupt */
+#define ADC_CR1_AWDIE_Pos (6U)
+#define ADC_CR1_AWDIE_Msk (0x1U << ADC_CR1_AWDIE_Pos) /*!< 0x00000040 */
+#define ADC_CR1_AWDIE ADC_CR1_AWDIE_Msk /*!< ADC analog watchdog 1 interrupt */
+#define ADC_CR1_JEOSIE_Pos (7U)
+#define ADC_CR1_JEOSIE_Msk (0x1U << ADC_CR1_JEOSIE_Pos) /*!< 0x00000080 */
+#define ADC_CR1_JEOSIE ADC_CR1_JEOSIE_Msk /*!< ADC group injected end of sequence conversions interrupt */
+#define ADC_CR1_SCAN_Pos (8U)
+#define ADC_CR1_SCAN_Msk (0x1U << ADC_CR1_SCAN_Pos) /*!< 0x00000100 */
+#define ADC_CR1_SCAN ADC_CR1_SCAN_Msk /*!< ADC scan mode */
+#define ADC_CR1_AWDSGL_Pos (9U)
+#define ADC_CR1_AWDSGL_Msk (0x1U << ADC_CR1_AWDSGL_Pos) /*!< 0x00000200 */
+#define ADC_CR1_AWDSGL ADC_CR1_AWDSGL_Msk /*!< ADC analog watchdog 1 monitoring a single channel or all channels */
+#define ADC_CR1_JAUTO_Pos (10U)
+#define ADC_CR1_JAUTO_Msk (0x1U << ADC_CR1_JAUTO_Pos) /*!< 0x00000400 */
+#define ADC_CR1_JAUTO ADC_CR1_JAUTO_Msk /*!< ADC group injected automatic trigger mode */
+#define ADC_CR1_DISCEN_Pos (11U)
+#define ADC_CR1_DISCEN_Msk (0x1U << ADC_CR1_DISCEN_Pos) /*!< 0x00000800 */
+#define ADC_CR1_DISCEN ADC_CR1_DISCEN_Msk /*!< ADC group regular sequencer discontinuous mode */
+#define ADC_CR1_JDISCEN_Pos (12U)
+#define ADC_CR1_JDISCEN_Msk (0x1U << ADC_CR1_JDISCEN_Pos) /*!< 0x00001000 */
+#define ADC_CR1_JDISCEN ADC_CR1_JDISCEN_Msk /*!< ADC group injected sequencer discontinuous mode */
+
+#define ADC_CR1_DISCNUM_Pos (13U)
+#define ADC_CR1_DISCNUM_Msk (0x7U << ADC_CR1_DISCNUM_Pos) /*!< 0x0000E000 */
+#define ADC_CR1_DISCNUM ADC_CR1_DISCNUM_Msk /*!< ADC group regular sequencer discontinuous number of ranks */
+#define ADC_CR1_DISCNUM_0 (0x1U << ADC_CR1_DISCNUM_Pos) /*!< 0x00002000 */
+#define ADC_CR1_DISCNUM_1 (0x2U << ADC_CR1_DISCNUM_Pos) /*!< 0x00004000 */
+#define ADC_CR1_DISCNUM_2 (0x4U << ADC_CR1_DISCNUM_Pos) /*!< 0x00008000 */
+
+#define ADC_CR1_DUALMOD_Pos (16U)
+#define ADC_CR1_DUALMOD_Msk (0xFU << ADC_CR1_DUALMOD_Pos) /*!< 0x000F0000 */
+#define ADC_CR1_DUALMOD ADC_CR1_DUALMOD_Msk /*!< ADC multimode mode selection */
+#define ADC_CR1_DUALMOD_0 (0x1U << ADC_CR1_DUALMOD_Pos) /*!< 0x00010000 */
+#define ADC_CR1_DUALMOD_1 (0x2U << ADC_CR1_DUALMOD_Pos) /*!< 0x00020000 */
+#define ADC_CR1_DUALMOD_2 (0x4U << ADC_CR1_DUALMOD_Pos) /*!< 0x00040000 */
+#define ADC_CR1_DUALMOD_3 (0x8U << ADC_CR1_DUALMOD_Pos) /*!< 0x00080000 */
+
+#define ADC_CR1_JAWDEN_Pos (22U)
+#define ADC_CR1_JAWDEN_Msk (0x1U << ADC_CR1_JAWDEN_Pos) /*!< 0x00400000 */
+#define ADC_CR1_JAWDEN ADC_CR1_JAWDEN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group injected */
+#define ADC_CR1_AWDEN_Pos (23U)
+#define ADC_CR1_AWDEN_Msk (0x1U << ADC_CR1_AWDEN_Pos) /*!< 0x00800000 */
+#define ADC_CR1_AWDEN ADC_CR1_AWDEN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group regular */
+
+/* Legacy defines */
+#define ADC_CR1_EOCIE (ADC_CR1_EOSIE)
+#define ADC_CR1_JEOCIE (ADC_CR1_JEOSIE)
+
+/******************* Bit definition for ADC_CR2 register ********************/
+#define ADC_CR2_ADON_Pos (0U)
+#define ADC_CR2_ADON_Msk (0x1U << ADC_CR2_ADON_Pos) /*!< 0x00000001 */
+#define ADC_CR2_ADON ADC_CR2_ADON_Msk /*!< ADC enable */
+#define ADC_CR2_CONT_Pos (1U)
+#define ADC_CR2_CONT_Msk (0x1U << ADC_CR2_CONT_Pos) /*!< 0x00000002 */
+#define ADC_CR2_CONT ADC_CR2_CONT_Msk /*!< ADC group regular continuous conversion mode */
+#define ADC_CR2_CAL_Pos (2U)
+#define ADC_CR2_CAL_Msk (0x1U << ADC_CR2_CAL_Pos) /*!< 0x00000004 */
+#define ADC_CR2_CAL ADC_CR2_CAL_Msk /*!< ADC calibration start */
+#define ADC_CR2_RSTCAL_Pos (3U)
+#define ADC_CR2_RSTCAL_Msk (0x1U << ADC_CR2_RSTCAL_Pos) /*!< 0x00000008 */
+#define ADC_CR2_RSTCAL ADC_CR2_RSTCAL_Msk /*!< ADC calibration reset */
+#define ADC_CR2_DMA_Pos (8U)
+#define ADC_CR2_DMA_Msk (0x1U << ADC_CR2_DMA_Pos) /*!< 0x00000100 */
+#define ADC_CR2_DMA ADC_CR2_DMA_Msk /*!< ADC DMA transfer enable */
+#define ADC_CR2_ALIGN_Pos (11U)
+#define ADC_CR2_ALIGN_Msk (0x1U << ADC_CR2_ALIGN_Pos) /*!< 0x00000800 */
+#define ADC_CR2_ALIGN ADC_CR2_ALIGN_Msk /*!< ADC data alignement */
+
+#define ADC_CR2_JEXTSEL_Pos (12U)
+#define ADC_CR2_JEXTSEL_Msk (0x7U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00007000 */
+#define ADC_CR2_JEXTSEL ADC_CR2_JEXTSEL_Msk /*!< ADC group injected external trigger source */
+#define ADC_CR2_JEXTSEL_0 (0x1U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00001000 */
+#define ADC_CR2_JEXTSEL_1 (0x2U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00002000 */
+#define ADC_CR2_JEXTSEL_2 (0x4U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00004000 */
+
+#define ADC_CR2_JEXTTRIG_Pos (15U)
+#define ADC_CR2_JEXTTRIG_Msk (0x1U << ADC_CR2_JEXTTRIG_Pos) /*!< 0x00008000 */
+#define ADC_CR2_JEXTTRIG ADC_CR2_JEXTTRIG_Msk /*!< ADC group injected external trigger enable */
+
+#define ADC_CR2_EXTSEL_Pos (17U)
+#define ADC_CR2_EXTSEL_Msk (0x7U << ADC_CR2_EXTSEL_Pos) /*!< 0x000E0000 */
+#define ADC_CR2_EXTSEL ADC_CR2_EXTSEL_Msk /*!< ADC group regular external trigger source */
+#define ADC_CR2_EXTSEL_0 (0x1U << ADC_CR2_EXTSEL_Pos) /*!< 0x00020000 */
+#define ADC_CR2_EXTSEL_1 (0x2U << ADC_CR2_EXTSEL_Pos) /*!< 0x00040000 */
+#define ADC_CR2_EXTSEL_2 (0x4U << ADC_CR2_EXTSEL_Pos) /*!< 0x00080000 */
+
+#define ADC_CR2_EXTTRIG_Pos (20U)
+#define ADC_CR2_EXTTRIG_Msk (0x1U << ADC_CR2_EXTTRIG_Pos) /*!< 0x00100000 */
+#define ADC_CR2_EXTTRIG ADC_CR2_EXTTRIG_Msk /*!< ADC group regular external trigger enable */
+#define ADC_CR2_JSWSTART_Pos (21U)
+#define ADC_CR2_JSWSTART_Msk (0x1U << ADC_CR2_JSWSTART_Pos) /*!< 0x00200000 */
+#define ADC_CR2_JSWSTART ADC_CR2_JSWSTART_Msk /*!< ADC group injected conversion start */
+#define ADC_CR2_SWSTART_Pos (22U)
+#define ADC_CR2_SWSTART_Msk (0x1U << ADC_CR2_SWSTART_Pos) /*!< 0x00400000 */
+#define ADC_CR2_SWSTART ADC_CR2_SWSTART_Msk /*!< ADC group regular conversion start */
+#define ADC_CR2_TSVREFE_Pos (23U)
+#define ADC_CR2_TSVREFE_Msk (0x1U << ADC_CR2_TSVREFE_Pos) /*!< 0x00800000 */
+#define ADC_CR2_TSVREFE ADC_CR2_TSVREFE_Msk /*!< ADC internal path to VrefInt and temperature sensor enable */
+
+/****************** Bit definition for ADC_SMPR1 register *******************/
+#define ADC_SMPR1_SMP10_Pos (0U)
+#define ADC_SMPR1_SMP10_Msk (0x7U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000007 */
+#define ADC_SMPR1_SMP10 ADC_SMPR1_SMP10_Msk /*!< ADC channel 10 sampling time selection */
+#define ADC_SMPR1_SMP10_0 (0x1U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000001 */
+#define ADC_SMPR1_SMP10_1 (0x2U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000002 */
+#define ADC_SMPR1_SMP10_2 (0x4U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000004 */
+
+#define ADC_SMPR1_SMP11_Pos (3U)
+#define ADC_SMPR1_SMP11_Msk (0x7U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000038 */
+#define ADC_SMPR1_SMP11 ADC_SMPR1_SMP11_Msk /*!< ADC channel 11 sampling time selection */
+#define ADC_SMPR1_SMP11_0 (0x1U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000008 */
+#define ADC_SMPR1_SMP11_1 (0x2U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000010 */
+#define ADC_SMPR1_SMP11_2 (0x4U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000020 */
+
+#define ADC_SMPR1_SMP12_Pos (6U)
+#define ADC_SMPR1_SMP12_Msk (0x7U << ADC_SMPR1_SMP12_Pos) /*!< 0x000001C0 */
+#define ADC_SMPR1_SMP12 ADC_SMPR1_SMP12_Msk /*!< ADC channel 12 sampling time selection */
+#define ADC_SMPR1_SMP12_0 (0x1U << ADC_SMPR1_SMP12_Pos) /*!< 0x00000040 */
+#define ADC_SMPR1_SMP12_1 (0x2U << ADC_SMPR1_SMP12_Pos) /*!< 0x00000080 */
+#define ADC_SMPR1_SMP12_2 (0x4U << ADC_SMPR1_SMP12_Pos) /*!< 0x00000100 */
+
+#define ADC_SMPR1_SMP13_Pos (9U)
+#define ADC_SMPR1_SMP13_Msk (0x7U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000E00 */
+#define ADC_SMPR1_SMP13 ADC_SMPR1_SMP13_Msk /*!< ADC channel 13 sampling time selection */
+#define ADC_SMPR1_SMP13_0 (0x1U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000200 */
+#define ADC_SMPR1_SMP13_1 (0x2U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000400 */
+#define ADC_SMPR1_SMP13_2 (0x4U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000800 */
+
+#define ADC_SMPR1_SMP14_Pos (12U)
+#define ADC_SMPR1_SMP14_Msk (0x7U << ADC_SMPR1_SMP14_Pos) /*!< 0x00007000 */
+#define ADC_SMPR1_SMP14 ADC_SMPR1_SMP14_Msk /*!< ADC channel 14 sampling time selection */
+#define ADC_SMPR1_SMP14_0 (0x1U << ADC_SMPR1_SMP14_Pos) /*!< 0x00001000 */
+#define ADC_SMPR1_SMP14_1 (0x2U << ADC_SMPR1_SMP14_Pos) /*!< 0x00002000 */
+#define ADC_SMPR1_SMP14_2 (0x4U << ADC_SMPR1_SMP14_Pos) /*!< 0x00004000 */
+
+#define ADC_SMPR1_SMP15_Pos (15U)
+#define ADC_SMPR1_SMP15_Msk (0x7U << ADC_SMPR1_SMP15_Pos) /*!< 0x00038000 */
+#define ADC_SMPR1_SMP15 ADC_SMPR1_SMP15_Msk /*!< ADC channel 15 sampling time selection */
+#define ADC_SMPR1_SMP15_0 (0x1U << ADC_SMPR1_SMP15_Pos) /*!< 0x00008000 */
+#define ADC_SMPR1_SMP15_1 (0x2U << ADC_SMPR1_SMP15_Pos) /*!< 0x00010000 */
+#define ADC_SMPR1_SMP15_2 (0x4U << ADC_SMPR1_SMP15_Pos) /*!< 0x00020000 */
+
+#define ADC_SMPR1_SMP16_Pos (18U)
+#define ADC_SMPR1_SMP16_Msk (0x7U << ADC_SMPR1_SMP16_Pos) /*!< 0x001C0000 */
+#define ADC_SMPR1_SMP16 ADC_SMPR1_SMP16_Msk /*!< ADC channel 16 sampling time selection */
+#define ADC_SMPR1_SMP16_0 (0x1U << ADC_SMPR1_SMP16_Pos) /*!< 0x00040000 */
+#define ADC_SMPR1_SMP16_1 (0x2U << ADC_SMPR1_SMP16_Pos) /*!< 0x00080000 */
+#define ADC_SMPR1_SMP16_2 (0x4U << ADC_SMPR1_SMP16_Pos) /*!< 0x00100000 */
+
+#define ADC_SMPR1_SMP17_Pos (21U)
+#define ADC_SMPR1_SMP17_Msk (0x7U << ADC_SMPR1_SMP17_Pos) /*!< 0x00E00000 */
+#define ADC_SMPR1_SMP17 ADC_SMPR1_SMP17_Msk /*!< ADC channel 17 sampling time selection */
+#define ADC_SMPR1_SMP17_0 (0x1U << ADC_SMPR1_SMP17_Pos) /*!< 0x00200000 */
+#define ADC_SMPR1_SMP17_1 (0x2U << ADC_SMPR1_SMP17_Pos) /*!< 0x00400000 */
+#define ADC_SMPR1_SMP17_2 (0x4U << ADC_SMPR1_SMP17_Pos) /*!< 0x00800000 */
+
+/****************** Bit definition for ADC_SMPR2 register *******************/
+#define ADC_SMPR2_SMP0_Pos (0U)
+#define ADC_SMPR2_SMP0_Msk (0x7U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000007 */
+#define ADC_SMPR2_SMP0 ADC_SMPR2_SMP0_Msk /*!< ADC channel 0 sampling time selection */
+#define ADC_SMPR2_SMP0_0 (0x1U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000001 */
+#define ADC_SMPR2_SMP0_1 (0x2U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000002 */
+#define ADC_SMPR2_SMP0_2 (0x4U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000004 */
+
+#define ADC_SMPR2_SMP1_Pos (3U)
+#define ADC_SMPR2_SMP1_Msk (0x7U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000038 */
+#define ADC_SMPR2_SMP1 ADC_SMPR2_SMP1_Msk /*!< ADC channel 1 sampling time selection */
+#define ADC_SMPR2_SMP1_0 (0x1U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000008 */
+#define ADC_SMPR2_SMP1_1 (0x2U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000010 */
+#define ADC_SMPR2_SMP1_2 (0x4U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000020 */
+
+#define ADC_SMPR2_SMP2_Pos (6U)
+#define ADC_SMPR2_SMP2_Msk (0x7U << ADC_SMPR2_SMP2_Pos) /*!< 0x000001C0 */
+#define ADC_SMPR2_SMP2 ADC_SMPR2_SMP2_Msk /*!< ADC channel 2 sampling time selection */
+#define ADC_SMPR2_SMP2_0 (0x1U << ADC_SMPR2_SMP2_Pos) /*!< 0x00000040 */
+#define ADC_SMPR2_SMP2_1 (0x2U << ADC_SMPR2_SMP2_Pos) /*!< 0x00000080 */
+#define ADC_SMPR2_SMP2_2 (0x4U << ADC_SMPR2_SMP2_Pos) /*!< 0x00000100 */
+
+#define ADC_SMPR2_SMP3_Pos (9U)
+#define ADC_SMPR2_SMP3_Msk (0x7U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000E00 */
+#define ADC_SMPR2_SMP3 ADC_SMPR2_SMP3_Msk /*!< ADC channel 3 sampling time selection */
+#define ADC_SMPR2_SMP3_0 (0x1U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000200 */
+#define ADC_SMPR2_SMP3_1 (0x2U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000400 */
+#define ADC_SMPR2_SMP3_2 (0x4U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000800 */
+
+#define ADC_SMPR2_SMP4_Pos (12U)
+#define ADC_SMPR2_SMP4_Msk (0x7U << ADC_SMPR2_SMP4_Pos) /*!< 0x00007000 */
+#define ADC_SMPR2_SMP4 ADC_SMPR2_SMP4_Msk /*!< ADC channel 4 sampling time selection */
+#define ADC_SMPR2_SMP4_0 (0x1U << ADC_SMPR2_SMP4_Pos) /*!< 0x00001000 */
+#define ADC_SMPR2_SMP4_1 (0x2U << ADC_SMPR2_SMP4_Pos) /*!< 0x00002000 */
+#define ADC_SMPR2_SMP4_2 (0x4U << ADC_SMPR2_SMP4_Pos) /*!< 0x00004000 */
+
+#define ADC_SMPR2_SMP5_Pos (15U)
+#define ADC_SMPR2_SMP5_Msk (0x7U << ADC_SMPR2_SMP5_Pos) /*!< 0x00038000 */
+#define ADC_SMPR2_SMP5 ADC_SMPR2_SMP5_Msk /*!< ADC channel 5 sampling time selection */
+#define ADC_SMPR2_SMP5_0 (0x1U << ADC_SMPR2_SMP5_Pos) /*!< 0x00008000 */
+#define ADC_SMPR2_SMP5_1 (0x2U << ADC_SMPR2_SMP5_Pos) /*!< 0x00010000 */
+#define ADC_SMPR2_SMP5_2 (0x4U << ADC_SMPR2_SMP5_Pos) /*!< 0x00020000 */
+
+#define ADC_SMPR2_SMP6_Pos (18U)
+#define ADC_SMPR2_SMP6_Msk (0x7U << ADC_SMPR2_SMP6_Pos) /*!< 0x001C0000 */
+#define ADC_SMPR2_SMP6 ADC_SMPR2_SMP6_Msk /*!< ADC channel 6 sampling time selection */
+#define ADC_SMPR2_SMP6_0 (0x1U << ADC_SMPR2_SMP6_Pos) /*!< 0x00040000 */
+#define ADC_SMPR2_SMP6_1 (0x2U << ADC_SMPR2_SMP6_Pos) /*!< 0x00080000 */
+#define ADC_SMPR2_SMP6_2 (0x4U << ADC_SMPR2_SMP6_Pos) /*!< 0x00100000 */
+
+#define ADC_SMPR2_SMP7_Pos (21U)
+#define ADC_SMPR2_SMP7_Msk (0x7U << ADC_SMPR2_SMP7_Pos) /*!< 0x00E00000 */
+#define ADC_SMPR2_SMP7 ADC_SMPR2_SMP7_Msk /*!< ADC channel 7 sampling time selection */
+#define ADC_SMPR2_SMP7_0 (0x1U << ADC_SMPR2_SMP7_Pos) /*!< 0x00200000 */
+#define ADC_SMPR2_SMP7_1 (0x2U << ADC_SMPR2_SMP7_Pos) /*!< 0x00400000 */
+#define ADC_SMPR2_SMP7_2 (0x4U << ADC_SMPR2_SMP7_Pos) /*!< 0x00800000 */
+
+#define ADC_SMPR2_SMP8_Pos (24U)
+#define ADC_SMPR2_SMP8_Msk (0x7U << ADC_SMPR2_SMP8_Pos) /*!< 0x07000000 */
+#define ADC_SMPR2_SMP8 ADC_SMPR2_SMP8_Msk /*!< ADC channel 8 sampling time selection */
+#define ADC_SMPR2_SMP8_0 (0x1U << ADC_SMPR2_SMP8_Pos) /*!< 0x01000000 */
+#define ADC_SMPR2_SMP8_1 (0x2U << ADC_SMPR2_SMP8_Pos) /*!< 0x02000000 */
+#define ADC_SMPR2_SMP8_2 (0x4U << ADC_SMPR2_SMP8_Pos) /*!< 0x04000000 */
+
+#define ADC_SMPR2_SMP9_Pos (27U)
+#define ADC_SMPR2_SMP9_Msk (0x7U << ADC_SMPR2_SMP9_Pos) /*!< 0x38000000 */
+#define ADC_SMPR2_SMP9 ADC_SMPR2_SMP9_Msk /*!< ADC channel 9 sampling time selection */
+#define ADC_SMPR2_SMP9_0 (0x1U << ADC_SMPR2_SMP9_Pos) /*!< 0x08000000 */
+#define ADC_SMPR2_SMP9_1 (0x2U << ADC_SMPR2_SMP9_Pos) /*!< 0x10000000 */
+#define ADC_SMPR2_SMP9_2 (0x4U << ADC_SMPR2_SMP9_Pos) /*!< 0x20000000 */
+
+/****************** Bit definition for ADC_JOFR1 register *******************/
+#define ADC_JOFR1_JOFFSET1_Pos (0U)
+#define ADC_JOFR1_JOFFSET1_Msk (0xFFFU << ADC_JOFR1_JOFFSET1_Pos) /*!< 0x00000FFF */
+#define ADC_JOFR1_JOFFSET1 ADC_JOFR1_JOFFSET1_Msk /*!< ADC group injected sequencer rank 1 offset value */
+
+/****************** Bit definition for ADC_JOFR2 register *******************/
+#define ADC_JOFR2_JOFFSET2_Pos (0U)
+#define ADC_JOFR2_JOFFSET2_Msk (0xFFFU << ADC_JOFR2_JOFFSET2_Pos) /*!< 0x00000FFF */
+#define ADC_JOFR2_JOFFSET2 ADC_JOFR2_JOFFSET2_Msk /*!< ADC group injected sequencer rank 2 offset value */
+
+/****************** Bit definition for ADC_JOFR3 register *******************/
+#define ADC_JOFR3_JOFFSET3_Pos (0U)
+#define ADC_JOFR3_JOFFSET3_Msk (0xFFFU << ADC_JOFR3_JOFFSET3_Pos) /*!< 0x00000FFF */
+#define ADC_JOFR3_JOFFSET3 ADC_JOFR3_JOFFSET3_Msk /*!< ADC group injected sequencer rank 3 offset value */
+
+/****************** Bit definition for ADC_JOFR4 register *******************/
+#define ADC_JOFR4_JOFFSET4_Pos (0U)
+#define ADC_JOFR4_JOFFSET4_Msk (0xFFFU << ADC_JOFR4_JOFFSET4_Pos) /*!< 0x00000FFF */
+#define ADC_JOFR4_JOFFSET4 ADC_JOFR4_JOFFSET4_Msk /*!< ADC group injected sequencer rank 4 offset value */
+
+/******************* Bit definition for ADC_HTR register ********************/
+#define ADC_HTR_HT_Pos (0U)
+#define ADC_HTR_HT_Msk (0xFFFU << ADC_HTR_HT_Pos) /*!< 0x00000FFF */
+#define ADC_HTR_HT ADC_HTR_HT_Msk /*!< ADC analog watchdog 1 threshold high */
+
+/******************* Bit definition for ADC_LTR register ********************/
+#define ADC_LTR_LT_Pos (0U)
+#define ADC_LTR_LT_Msk (0xFFFU << ADC_LTR_LT_Pos) /*!< 0x00000FFF */
+#define ADC_LTR_LT ADC_LTR_LT_Msk /*!< ADC analog watchdog 1 threshold low */
+
+/******************* Bit definition for ADC_SQR1 register *******************/
+#define ADC_SQR1_SQ13_Pos (0U)
+#define ADC_SQR1_SQ13_Msk (0x1FU << ADC_SQR1_SQ13_Pos) /*!< 0x0000001F */
+#define ADC_SQR1_SQ13 ADC_SQR1_SQ13_Msk /*!< ADC group regular sequencer rank 13 */
+#define ADC_SQR1_SQ13_0 (0x01U << ADC_SQR1_SQ13_Pos) /*!< 0x00000001 */
+#define ADC_SQR1_SQ13_1 (0x02U << ADC_SQR1_SQ13_Pos) /*!< 0x00000002 */
+#define ADC_SQR1_SQ13_2 (0x04U << ADC_SQR1_SQ13_Pos) /*!< 0x00000004 */
+#define ADC_SQR1_SQ13_3 (0x08U << ADC_SQR1_SQ13_Pos) /*!< 0x00000008 */
+#define ADC_SQR1_SQ13_4 (0x10U << ADC_SQR1_SQ13_Pos) /*!< 0x00000010 */
+
+#define ADC_SQR1_SQ14_Pos (5U)
+#define ADC_SQR1_SQ14_Msk (0x1FU << ADC_SQR1_SQ14_Pos) /*!< 0x000003E0 */
+#define ADC_SQR1_SQ14 ADC_SQR1_SQ14_Msk /*!< ADC group regular sequencer rank 14 */
+#define ADC_SQR1_SQ14_0 (0x01U << ADC_SQR1_SQ14_Pos) /*!< 0x00000020 */
+#define ADC_SQR1_SQ14_1 (0x02U << ADC_SQR1_SQ14_Pos) /*!< 0x00000040 */
+#define ADC_SQR1_SQ14_2 (0x04U << ADC_SQR1_SQ14_Pos) /*!< 0x00000080 */
+#define ADC_SQR1_SQ14_3 (0x08U << ADC_SQR1_SQ14_Pos) /*!< 0x00000100 */
+#define ADC_SQR1_SQ14_4 (0x10U << ADC_SQR1_SQ14_Pos) /*!< 0x00000200 */
+
+#define ADC_SQR1_SQ15_Pos (10U)
+#define ADC_SQR1_SQ15_Msk (0x1FU << ADC_SQR1_SQ15_Pos) /*!< 0x00007C00 */
+#define ADC_SQR1_SQ15 ADC_SQR1_SQ15_Msk /*!< ADC group regular sequencer rank 15 */
+#define ADC_SQR1_SQ15_0 (0x01U << ADC_SQR1_SQ15_Pos) /*!< 0x00000400 */
+#define ADC_SQR1_SQ15_1 (0x02U << ADC_SQR1_SQ15_Pos) /*!< 0x00000800 */
+#define ADC_SQR1_SQ15_2 (0x04U << ADC_SQR1_SQ15_Pos) /*!< 0x00001000 */
+#define ADC_SQR1_SQ15_3 (0x08U << ADC_SQR1_SQ15_Pos) /*!< 0x00002000 */
+#define ADC_SQR1_SQ15_4 (0x10U << ADC_SQR1_SQ15_Pos) /*!< 0x00004000 */
+
+#define ADC_SQR1_SQ16_Pos (15U)
+#define ADC_SQR1_SQ16_Msk (0x1FU << ADC_SQR1_SQ16_Pos) /*!< 0x000F8000 */
+#define ADC_SQR1_SQ16 ADC_SQR1_SQ16_Msk /*!< ADC group regular sequencer rank 16 */
+#define ADC_SQR1_SQ16_0 (0x01U << ADC_SQR1_SQ16_Pos) /*!< 0x00008000 */
+#define ADC_SQR1_SQ16_1 (0x02U << ADC_SQR1_SQ16_Pos) /*!< 0x00010000 */
+#define ADC_SQR1_SQ16_2 (0x04U << ADC_SQR1_SQ16_Pos) /*!< 0x00020000 */
+#define ADC_SQR1_SQ16_3 (0x08U << ADC_SQR1_SQ16_Pos) /*!< 0x00040000 */
+#define ADC_SQR1_SQ16_4 (0x10U << ADC_SQR1_SQ16_Pos) /*!< 0x00080000 */
+
+#define ADC_SQR1_L_Pos (20U)
+#define ADC_SQR1_L_Msk (0xFU << ADC_SQR1_L_Pos) /*!< 0x00F00000 */
+#define ADC_SQR1_L ADC_SQR1_L_Msk /*!< ADC group regular sequencer scan length */
+#define ADC_SQR1_L_0 (0x1U << ADC_SQR1_L_Pos) /*!< 0x00100000 */
+#define ADC_SQR1_L_1 (0x2U << ADC_SQR1_L_Pos) /*!< 0x00200000 */
+#define ADC_SQR1_L_2 (0x4U << ADC_SQR1_L_Pos) /*!< 0x00400000 */
+#define ADC_SQR1_L_3 (0x8U << ADC_SQR1_L_Pos) /*!< 0x00800000 */
+
+/******************* Bit definition for ADC_SQR2 register *******************/
+#define ADC_SQR2_SQ7_Pos (0U)
+#define ADC_SQR2_SQ7_Msk (0x1FU << ADC_SQR2_SQ7_Pos) /*!< 0x0000001F */
+#define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk /*!< ADC group regular sequencer rank 7 */
+#define ADC_SQR2_SQ7_0 (0x01U << ADC_SQR2_SQ7_Pos) /*!< 0x00000001 */
+#define ADC_SQR2_SQ7_1 (0x02U << ADC_SQR2_SQ7_Pos) /*!< 0x00000002 */
+#define ADC_SQR2_SQ7_2 (0x04U << ADC_SQR2_SQ7_Pos) /*!< 0x00000004 */
+#define ADC_SQR2_SQ7_3 (0x08U << ADC_SQR2_SQ7_Pos) /*!< 0x00000008 */
+#define ADC_SQR2_SQ7_4 (0x10U << ADC_SQR2_SQ7_Pos) /*!< 0x00000010 */
+
+#define ADC_SQR2_SQ8_Pos (5U)
+#define ADC_SQR2_SQ8_Msk (0x1FU << ADC_SQR2_SQ8_Pos) /*!< 0x000003E0 */
+#define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk /*!< ADC group regular sequencer rank 8 */
+#define ADC_SQR2_SQ8_0 (0x01U << ADC_SQR2_SQ8_Pos) /*!< 0x00000020 */
+#define ADC_SQR2_SQ8_1 (0x02U << ADC_SQR2_SQ8_Pos) /*!< 0x00000040 */
+#define ADC_SQR2_SQ8_2 (0x04U << ADC_SQR2_SQ8_Pos) /*!< 0x00000080 */
+#define ADC_SQR2_SQ8_3 (0x08U << ADC_SQR2_SQ8_Pos) /*!< 0x00000100 */
+#define ADC_SQR2_SQ8_4 (0x10U << ADC_SQR2_SQ8_Pos) /*!< 0x00000200 */
+
+#define ADC_SQR2_SQ9_Pos (10U)
+#define ADC_SQR2_SQ9_Msk (0x1FU << ADC_SQR2_SQ9_Pos) /*!< 0x00007C00 */
+#define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk /*!< ADC group regular sequencer rank 9 */
+#define ADC_SQR2_SQ9_0 (0x01U << ADC_SQR2_SQ9_Pos) /*!< 0x00000400 */
+#define ADC_SQR2_SQ9_1 (0x02U << ADC_SQR2_SQ9_Pos) /*!< 0x00000800 */
+#define ADC_SQR2_SQ9_2 (0x04U << ADC_SQR2_SQ9_Pos) /*!< 0x00001000 */
+#define ADC_SQR2_SQ9_3 (0x08U << ADC_SQR2_SQ9_Pos) /*!< 0x00002000 */
+#define ADC_SQR2_SQ9_4 (0x10U << ADC_SQR2_SQ9_Pos) /*!< 0x00004000 */
+
+#define ADC_SQR2_SQ10_Pos (15U)
+#define ADC_SQR2_SQ10_Msk (0x1FU << ADC_SQR2_SQ10_Pos) /*!< 0x000F8000 */
+#define ADC_SQR2_SQ10 ADC_SQR2_SQ10_Msk /*!< ADC group regular sequencer rank 10 */
+#define ADC_SQR2_SQ10_0 (0x01U << ADC_SQR2_SQ10_Pos) /*!< 0x00008000 */
+#define ADC_SQR2_SQ10_1 (0x02U << ADC_SQR2_SQ10_Pos) /*!< 0x00010000 */
+#define ADC_SQR2_SQ10_2 (0x04U << ADC_SQR2_SQ10_Pos) /*!< 0x00020000 */
+#define ADC_SQR2_SQ10_3 (0x08U << ADC_SQR2_SQ10_Pos) /*!< 0x00040000 */
+#define ADC_SQR2_SQ10_4 (0x10U << ADC_SQR2_SQ10_Pos) /*!< 0x00080000 */
+
+#define ADC_SQR2_SQ11_Pos (20U)
+#define ADC_SQR2_SQ11_Msk (0x1FU << ADC_SQR2_SQ11_Pos) /*!< 0x01F00000 */
+#define ADC_SQR2_SQ11 ADC_SQR2_SQ11_Msk /*!< ADC group regular sequencer rank 1 */
+#define ADC_SQR2_SQ11_0 (0x01U << ADC_SQR2_SQ11_Pos) /*!< 0x00100000 */
+#define ADC_SQR2_SQ11_1 (0x02U << ADC_SQR2_SQ11_Pos) /*!< 0x00200000 */
+#define ADC_SQR2_SQ11_2 (0x04U << ADC_SQR2_SQ11_Pos) /*!< 0x00400000 */
+#define ADC_SQR2_SQ11_3 (0x08U << ADC_SQR2_SQ11_Pos) /*!< 0x00800000 */
+#define ADC_SQR2_SQ11_4 (0x10U << ADC_SQR2_SQ11_Pos) /*!< 0x01000000 */
+
+#define ADC_SQR2_SQ12_Pos (25U)
+#define ADC_SQR2_SQ12_Msk (0x1FU << ADC_SQR2_SQ12_Pos) /*!< 0x3E000000 */
+#define ADC_SQR2_SQ12 ADC_SQR2_SQ12_Msk /*!< ADC group regular sequencer rank 12 */
+#define ADC_SQR2_SQ12_0 (0x01U << ADC_SQR2_SQ12_Pos) /*!< 0x02000000 */
+#define ADC_SQR2_SQ12_1 (0x02U << ADC_SQR2_SQ12_Pos) /*!< 0x04000000 */
+#define ADC_SQR2_SQ12_2 (0x04U << ADC_SQR2_SQ12_Pos) /*!< 0x08000000 */
+#define ADC_SQR2_SQ12_3 (0x08U << ADC_SQR2_SQ12_Pos) /*!< 0x10000000 */
+#define ADC_SQR2_SQ12_4 (0x10U << ADC_SQR2_SQ12_Pos) /*!< 0x20000000 */
+
+/******************* Bit definition for ADC_SQR3 register *******************/
+#define ADC_SQR3_SQ1_Pos (0U)
+#define ADC_SQR3_SQ1_Msk (0x1FU << ADC_SQR3_SQ1_Pos) /*!< 0x0000001F */
+#define ADC_SQR3_SQ1 ADC_SQR3_SQ1_Msk /*!< ADC group regular sequencer rank 1 */
+#define ADC_SQR3_SQ1_0 (0x01U << ADC_SQR3_SQ1_Pos) /*!< 0x00000001 */
+#define ADC_SQR3_SQ1_1 (0x02U << ADC_SQR3_SQ1_Pos) /*!< 0x00000002 */
+#define ADC_SQR3_SQ1_2 (0x04U << ADC_SQR3_SQ1_Pos) /*!< 0x00000004 */
+#define ADC_SQR3_SQ1_3 (0x08U << ADC_SQR3_SQ1_Pos) /*!< 0x00000008 */
+#define ADC_SQR3_SQ1_4 (0x10U << ADC_SQR3_SQ1_Pos) /*!< 0x00000010 */
+
+#define ADC_SQR3_SQ2_Pos (5U)
+#define ADC_SQR3_SQ2_Msk (0x1FU << ADC_SQR3_SQ2_Pos) /*!< 0x000003E0 */
+#define ADC_SQR3_SQ2 ADC_SQR3_SQ2_Msk /*!< ADC group regular sequencer rank 2 */
+#define ADC_SQR3_SQ2_0 (0x01U << ADC_SQR3_SQ2_Pos) /*!< 0x00000020 */
+#define ADC_SQR3_SQ2_1 (0x02U << ADC_SQR3_SQ2_Pos) /*!< 0x00000040 */
+#define ADC_SQR3_SQ2_2 (0x04U << ADC_SQR3_SQ2_Pos) /*!< 0x00000080 */
+#define ADC_SQR3_SQ2_3 (0x08U << ADC_SQR3_SQ2_Pos) /*!< 0x00000100 */
+#define ADC_SQR3_SQ2_4 (0x10U << ADC_SQR3_SQ2_Pos) /*!< 0x00000200 */
+
+#define ADC_SQR3_SQ3_Pos (10U)
+#define ADC_SQR3_SQ3_Msk (0x1FU << ADC_SQR3_SQ3_Pos) /*!< 0x00007C00 */
+#define ADC_SQR3_SQ3 ADC_SQR3_SQ3_Msk /*!< ADC group regular sequencer rank 3 */
+#define ADC_SQR3_SQ3_0 (0x01U << ADC_SQR3_SQ3_Pos) /*!< 0x00000400 */
+#define ADC_SQR3_SQ3_1 (0x02U << ADC_SQR3_SQ3_Pos) /*!< 0x00000800 */
+#define ADC_SQR3_SQ3_2 (0x04U << ADC_SQR3_SQ3_Pos) /*!< 0x00001000 */
+#define ADC_SQR3_SQ3_3 (0x08U << ADC_SQR3_SQ3_Pos) /*!< 0x00002000 */
+#define ADC_SQR3_SQ3_4 (0x10U << ADC_SQR3_SQ3_Pos) /*!< 0x00004000 */
+
+#define ADC_SQR3_SQ4_Pos (15U)
+#define ADC_SQR3_SQ4_Msk (0x1FU << ADC_SQR3_SQ4_Pos) /*!< 0x000F8000 */
+#define ADC_SQR3_SQ4 ADC_SQR3_SQ4_Msk /*!< ADC group regular sequencer rank 4 */
+#define ADC_SQR3_SQ4_0 (0x01U << ADC_SQR3_SQ4_Pos) /*!< 0x00008000 */
+#define ADC_SQR3_SQ4_1 (0x02U << ADC_SQR3_SQ4_Pos) /*!< 0x00010000 */
+#define ADC_SQR3_SQ4_2 (0x04U << ADC_SQR3_SQ4_Pos) /*!< 0x00020000 */
+#define ADC_SQR3_SQ4_3 (0x08U << ADC_SQR3_SQ4_Pos) /*!< 0x00040000 */
+#define ADC_SQR3_SQ4_4 (0x10U << ADC_SQR3_SQ4_Pos) /*!< 0x00080000 */
+
+#define ADC_SQR3_SQ5_Pos (20U)
+#define ADC_SQR3_SQ5_Msk (0x1FU << ADC_SQR3_SQ5_Pos) /*!< 0x01F00000 */
+#define ADC_SQR3_SQ5 ADC_SQR3_SQ5_Msk /*!< ADC group regular sequencer rank 5 */
+#define ADC_SQR3_SQ5_0 (0x01U << ADC_SQR3_SQ5_Pos) /*!< 0x00100000 */
+#define ADC_SQR3_SQ5_1 (0x02U << ADC_SQR3_SQ5_Pos) /*!< 0x00200000 */
+#define ADC_SQR3_SQ5_2 (0x04U << ADC_SQR3_SQ5_Pos) /*!< 0x00400000 */
+#define ADC_SQR3_SQ5_3 (0x08U << ADC_SQR3_SQ5_Pos) /*!< 0x00800000 */
+#define ADC_SQR3_SQ5_4 (0x10U << ADC_SQR3_SQ5_Pos) /*!< 0x01000000 */
+
+#define ADC_SQR3_SQ6_Pos (25U)
+#define ADC_SQR3_SQ6_Msk (0x1FU << ADC_SQR3_SQ6_Pos) /*!< 0x3E000000 */
+#define ADC_SQR3_SQ6 ADC_SQR3_SQ6_Msk /*!< ADC group regular sequencer rank 6 */
+#define ADC_SQR3_SQ6_0 (0x01U << ADC_SQR3_SQ6_Pos) /*!< 0x02000000 */
+#define ADC_SQR3_SQ6_1 (0x02U << ADC_SQR3_SQ6_Pos) /*!< 0x04000000 */
+#define ADC_SQR3_SQ6_2 (0x04U << ADC_SQR3_SQ6_Pos) /*!< 0x08000000 */
+#define ADC_SQR3_SQ6_3 (0x08U << ADC_SQR3_SQ6_Pos) /*!< 0x10000000 */
+#define ADC_SQR3_SQ6_4 (0x10U << ADC_SQR3_SQ6_Pos) /*!< 0x20000000 */
+
+/******************* Bit definition for ADC_JSQR register *******************/
+#define ADC_JSQR_JSQ1_Pos (0U)
+#define ADC_JSQR_JSQ1_Msk (0x1FU << ADC_JSQR_JSQ1_Pos) /*!< 0x0000001F */
+#define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!< ADC group injected sequencer rank 1 */
+#define ADC_JSQR_JSQ1_0 (0x01U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000001 */
+#define ADC_JSQR_JSQ1_1 (0x02U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000002 */
+#define ADC_JSQR_JSQ1_2 (0x04U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000004 */
+#define ADC_JSQR_JSQ1_3 (0x08U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000008 */
+#define ADC_JSQR_JSQ1_4 (0x10U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000010 */
+
+#define ADC_JSQR_JSQ2_Pos (5U)
+#define ADC_JSQR_JSQ2_Msk (0x1FU << ADC_JSQR_JSQ2_Pos) /*!< 0x000003E0 */
+#define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!< ADC group injected sequencer rank 2 */
+#define ADC_JSQR_JSQ2_0 (0x01U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000020 */
+#define ADC_JSQR_JSQ2_1 (0x02U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000040 */
+#define ADC_JSQR_JSQ2_2 (0x04U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000080 */
+#define ADC_JSQR_JSQ2_3 (0x08U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000100 */
+#define ADC_JSQR_JSQ2_4 (0x10U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000200 */
+
+#define ADC_JSQR_JSQ3_Pos (10U)
+#define ADC_JSQR_JSQ3_Msk (0x1FU << ADC_JSQR_JSQ3_Pos) /*!< 0x00007C00 */
+#define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!< ADC group injected sequencer rank 3 */
+#define ADC_JSQR_JSQ3_0 (0x01U << ADC_JSQR_JSQ3_Pos) /*!< 0x00000400 */
+#define ADC_JSQR_JSQ3_1 (0x02U << ADC_JSQR_JSQ3_Pos) /*!< 0x00000800 */
+#define ADC_JSQR_JSQ3_2 (0x04U << ADC_JSQR_JSQ3_Pos) /*!< 0x00001000 */
+#define ADC_JSQR_JSQ3_3 (0x08U << ADC_JSQR_JSQ3_Pos) /*!< 0x00002000 */
+#define ADC_JSQR_JSQ3_4 (0x10U << ADC_JSQR_JSQ3_Pos) /*!< 0x00004000 */
+
+#define ADC_JSQR_JSQ4_Pos (15U)
+#define ADC_JSQR_JSQ4_Msk (0x1FU << ADC_JSQR_JSQ4_Pos) /*!< 0x000F8000 */
+#define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!< ADC group injected sequencer rank 4 */
+#define ADC_JSQR_JSQ4_0 (0x01U << ADC_JSQR_JSQ4_Pos) /*!< 0x00008000 */
+#define ADC_JSQR_JSQ4_1 (0x02U << ADC_JSQR_JSQ4_Pos) /*!< 0x00010000 */
+#define ADC_JSQR_JSQ4_2 (0x04U << ADC_JSQR_JSQ4_Pos) /*!< 0x00020000 */
+#define ADC_JSQR_JSQ4_3 (0x08U << ADC_JSQR_JSQ4_Pos) /*!< 0x00040000 */
+#define ADC_JSQR_JSQ4_4 (0x10U << ADC_JSQR_JSQ4_Pos) /*!< 0x00080000 */
+
+#define ADC_JSQR_JL_Pos (20U)
+#define ADC_JSQR_JL_Msk (0x3U << ADC_JSQR_JL_Pos) /*!< 0x00300000 */
+#define ADC_JSQR_JL ADC_JSQR_JL_Msk /*!< ADC group injected sequencer scan length */
+#define ADC_JSQR_JL_0 (0x1U << ADC_JSQR_JL_Pos) /*!< 0x00100000 */
+#define ADC_JSQR_JL_1 (0x2U << ADC_JSQR_JL_Pos) /*!< 0x00200000 */
+
+/******************* Bit definition for ADC_JDR1 register *******************/
+#define ADC_JDR1_JDATA_Pos (0U)
+#define ADC_JDR1_JDATA_Msk (0xFFFFU << ADC_JDR1_JDATA_Pos) /*!< 0x0000FFFF */
+#define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!< ADC group injected sequencer rank 1 conversion data */
+
+/******************* Bit definition for ADC_JDR2 register *******************/
+#define ADC_JDR2_JDATA_Pos (0U)
+#define ADC_JDR2_JDATA_Msk (0xFFFFU << ADC_JDR2_JDATA_Pos) /*!< 0x0000FFFF */
+#define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!< ADC group injected sequencer rank 2 conversion data */
+
+/******************* Bit definition for ADC_JDR3 register *******************/
+#define ADC_JDR3_JDATA_Pos (0U)
+#define ADC_JDR3_JDATA_Msk (0xFFFFU << ADC_JDR3_JDATA_Pos) /*!< 0x0000FFFF */
+#define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!< ADC group injected sequencer rank 3 conversion data */
+
+/******************* Bit definition for ADC_JDR4 register *******************/
+#define ADC_JDR4_JDATA_Pos (0U)
+#define ADC_JDR4_JDATA_Msk (0xFFFFU << ADC_JDR4_JDATA_Pos) /*!< 0x0000FFFF */
+#define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!< ADC group injected sequencer rank 4 conversion data */
+
+/******************** Bit definition for ADC_DR register ********************/
+#define ADC_DR_DATA_Pos (0U)
+#define ADC_DR_DATA_Msk (0xFFFFU << ADC_DR_DATA_Pos) /*!< 0x0000FFFF */
+#define ADC_DR_DATA ADC_DR_DATA_Msk /*!< ADC group regular conversion data */
+#define ADC_DR_ADC2DATA_Pos (16U)
+#define ADC_DR_ADC2DATA_Msk (0xFFFFU << ADC_DR_ADC2DATA_Pos) /*!< 0xFFFF0000 */
+#define ADC_DR_ADC2DATA ADC_DR_ADC2DATA_Msk /*!< ADC group regular conversion data for ADC slave, in multimode */
+
+
+/*****************************************************************************/
+/* */
+/* Timers (TIM) */
+/* */
+/*****************************************************************************/
+/******************* Bit definition for TIM_CR1 register *******************/
+#define TIM_CR1_CEN_Pos (0U)
+#define TIM_CR1_CEN_Msk (0x1U << TIM_CR1_CEN_Pos) /*!< 0x00000001 */
+#define TIM_CR1_CEN TIM_CR1_CEN_Msk /*!<Counter enable */
+#define TIM_CR1_UDIS_Pos (1U)
+#define TIM_CR1_UDIS_Msk (0x1U << TIM_CR1_UDIS_Pos) /*!< 0x00000002 */
+#define TIM_CR1_UDIS TIM_CR1_UDIS_Msk /*!<Update disable */
+#define TIM_CR1_URS_Pos (2U)
+#define TIM_CR1_URS_Msk (0x1U << TIM_CR1_URS_Pos) /*!< 0x00000004 */
+#define TIM_CR1_URS TIM_CR1_URS_Msk /*!<Update request source */
+#define TIM_CR1_OPM_Pos (3U)
+#define TIM_CR1_OPM_Msk (0x1U << TIM_CR1_OPM_Pos) /*!< 0x00000008 */
+#define TIM_CR1_OPM TIM_CR1_OPM_Msk /*!<One pulse mode */
+#define TIM_CR1_DIR_Pos (4U)
+#define TIM_CR1_DIR_Msk (0x1U << TIM_CR1_DIR_Pos) /*!< 0x00000010 */
+#define TIM_CR1_DIR TIM_CR1_DIR_Msk /*!<Direction */
+
+#define TIM_CR1_CMS_Pos (5U)
+#define TIM_CR1_CMS_Msk (0x3U << TIM_CR1_CMS_Pos) /*!< 0x00000060 */
+#define TIM_CR1_CMS TIM_CR1_CMS_Msk /*!<CMS[1:0] bits (Center-aligned mode selection) */
+#define TIM_CR1_CMS_0 (0x1U << TIM_CR1_CMS_Pos) /*!< 0x00000020 */
+#define TIM_CR1_CMS_1 (0x2U << TIM_CR1_CMS_Pos) /*!< 0x00000040 */
+
+#define TIM_CR1_ARPE_Pos (7U)
+#define TIM_CR1_ARPE_Msk (0x1U << TIM_CR1_ARPE_Pos) /*!< 0x00000080 */
+#define TIM_CR1_ARPE TIM_CR1_ARPE_Msk /*!<Auto-reload preload enable */
+
+#define TIM_CR1_CKD_Pos (8U)
+#define TIM_CR1_CKD_Msk (0x3U << TIM_CR1_CKD_Pos) /*!< 0x00000300 */
+#define TIM_CR1_CKD TIM_CR1_CKD_Msk /*!<CKD[1:0] bits (clock division) */
+#define TIM_CR1_CKD_0 (0x1U << TIM_CR1_CKD_Pos) /*!< 0x00000100 */
+#define TIM_CR1_CKD_1 (0x2U << TIM_CR1_CKD_Pos) /*!< 0x00000200 */
+
+/******************* Bit definition for TIM_CR2 register *******************/
+#define TIM_CR2_CCPC_Pos (0U)
+#define TIM_CR2_CCPC_Msk (0x1U << TIM_CR2_CCPC_Pos) /*!< 0x00000001 */
+#define TIM_CR2_CCPC TIM_CR2_CCPC_Msk /*!<Capture/Compare Preloaded Control */
+#define TIM_CR2_CCUS_Pos (2U)
+#define TIM_CR2_CCUS_Msk (0x1U << TIM_CR2_CCUS_Pos) /*!< 0x00000004 */
+#define TIM_CR2_CCUS TIM_CR2_CCUS_Msk /*!<Capture/Compare Control Update Selection */
+#define TIM_CR2_CCDS_Pos (3U)
+#define TIM_CR2_CCDS_Msk (0x1U << TIM_CR2_CCDS_Pos) /*!< 0x00000008 */
+#define TIM_CR2_CCDS TIM_CR2_CCDS_Msk /*!<Capture/Compare DMA Selection */
+
+#define TIM_CR2_MMS_Pos (4U)
+#define TIM_CR2_MMS_Msk (0x7U << TIM_CR2_MMS_Pos) /*!< 0x00000070 */
+#define TIM_CR2_MMS TIM_CR2_MMS_Msk /*!<MMS[2:0] bits (Master Mode Selection) */
+#define TIM_CR2_MMS_0 (0x1U << TIM_CR2_MMS_Pos) /*!< 0x00000010 */
+#define TIM_CR2_MMS_1 (0x2U << TIM_CR2_MMS_Pos) /*!< 0x00000020 */
+#define TIM_CR2_MMS_2 (0x4U << TIM_CR2_MMS_Pos) /*!< 0x00000040 */
+
+#define TIM_CR2_TI1S_Pos (7U)
+#define TIM_CR2_TI1S_Msk (0x1U << TIM_CR2_TI1S_Pos) /*!< 0x00000080 */
+#define TIM_CR2_TI1S TIM_CR2_TI1S_Msk /*!<TI1 Selection */
+#define TIM_CR2_OIS1_Pos (8U)
+#define TIM_CR2_OIS1_Msk (0x1U << TIM_CR2_OIS1_Pos) /*!< 0x00000100 */
+#define TIM_CR2_OIS1 TIM_CR2_OIS1_Msk /*!<Output Idle state 1 (OC1 output) */
+#define TIM_CR2_OIS1N_Pos (9U)
+#define TIM_CR2_OIS1N_Msk (0x1U << TIM_CR2_OIS1N_Pos) /*!< 0x00000200 */
+#define TIM_CR2_OIS1N TIM_CR2_OIS1N_Msk /*!<Output Idle state 1 (OC1N output) */
+#define TIM_CR2_OIS2_Pos (10U)
+#define TIM_CR2_OIS2_Msk (0x1U << TIM_CR2_OIS2_Pos) /*!< 0x00000400 */
+#define TIM_CR2_OIS2 TIM_CR2_OIS2_Msk /*!<Output Idle state 2 (OC2 output) */
+#define TIM_CR2_OIS2N_Pos (11U)
+#define TIM_CR2_OIS2N_Msk (0x1U << TIM_CR2_OIS2N_Pos) /*!< 0x00000800 */
+#define TIM_CR2_OIS2N TIM_CR2_OIS2N_Msk /*!<Output Idle state 2 (OC2N output) */
+#define TIM_CR2_OIS3_Pos (12U)
+#define TIM_CR2_OIS3_Msk (0x1U << TIM_CR2_OIS3_Pos) /*!< 0x00001000 */
+#define TIM_CR2_OIS3 TIM_CR2_OIS3_Msk /*!<Output Idle state 3 (OC3 output) */
+#define TIM_CR2_OIS3N_Pos (13U)
+#define TIM_CR2_OIS3N_Msk (0x1U << TIM_CR2_OIS3N_Pos) /*!< 0x00002000 */
+#define TIM_CR2_OIS3N TIM_CR2_OIS3N_Msk /*!<Output Idle state 3 (OC3N output) */
+#define TIM_CR2_OIS4_Pos (14U)
+#define TIM_CR2_OIS4_Msk (0x1U << TIM_CR2_OIS4_Pos) /*!< 0x00004000 */
+#define TIM_CR2_OIS4 TIM_CR2_OIS4_Msk /*!<Output Idle state 4 (OC4 output) */
+
+/******************* Bit definition for TIM_SMCR register ******************/
+#define TIM_SMCR_SMS_Pos (0U)
+#define TIM_SMCR_SMS_Msk (0x7U << TIM_SMCR_SMS_Pos) /*!< 0x00000007 */
+#define TIM_SMCR_SMS TIM_SMCR_SMS_Msk /*!<SMS[2:0] bits (Slave mode selection) */
+#define TIM_SMCR_SMS_0 (0x1U << TIM_SMCR_SMS_Pos) /*!< 0x00000001 */
+#define TIM_SMCR_SMS_1 (0x2U << TIM_SMCR_SMS_Pos) /*!< 0x00000002 */
+#define TIM_SMCR_SMS_2 (0x4U << TIM_SMCR_SMS_Pos) /*!< 0x00000004 */
+
+#define TIM_SMCR_OCCS_Pos (3U)
+#define TIM_SMCR_OCCS_Msk (0x1U << TIM_SMCR_OCCS_Pos) /*!< 0x00000008 */
+#define TIM_SMCR_OCCS TIM_SMCR_OCCS_Msk /*!< OCREF clear selection */
+
+#define TIM_SMCR_TS_Pos (4U)
+#define TIM_SMCR_TS_Msk (0x7U << TIM_SMCR_TS_Pos) /*!< 0x00000070 */
+#define TIM_SMCR_TS TIM_SMCR_TS_Msk /*!<TS[2:0] bits (Trigger selection) */
+#define TIM_SMCR_TS_0 (0x1U << TIM_SMCR_TS_Pos) /*!< 0x00000010 */
+#define TIM_SMCR_TS_1 (0x2U << TIM_SMCR_TS_Pos) /*!< 0x00000020 */
+#define TIM_SMCR_TS_2 (0x4U << TIM_SMCR_TS_Pos) /*!< 0x00000040 */
+
+#define TIM_SMCR_MSM_Pos (7U)
+#define TIM_SMCR_MSM_Msk (0x1U << TIM_SMCR_MSM_Pos) /*!< 0x00000080 */
+#define TIM_SMCR_MSM TIM_SMCR_MSM_Msk /*!<Master/slave mode */
+
+#define TIM_SMCR_ETF_Pos (8U)
+#define TIM_SMCR_ETF_Msk (0xFU << TIM_SMCR_ETF_Pos) /*!< 0x00000F00 */
+#define TIM_SMCR_ETF TIM_SMCR_ETF_Msk /*!<ETF[3:0] bits (External trigger filter) */
+#define TIM_SMCR_ETF_0 (0x1U << TIM_SMCR_ETF_Pos) /*!< 0x00000100 */
+#define TIM_SMCR_ETF_1 (0x2U << TIM_SMCR_ETF_Pos) /*!< 0x00000200 */
+#define TIM_SMCR_ETF_2 (0x4U << TIM_SMCR_ETF_Pos) /*!< 0x00000400 */
+#define TIM_SMCR_ETF_3 (0x8U << TIM_SMCR_ETF_Pos) /*!< 0x00000800 */
+
+#define TIM_SMCR_ETPS_Pos (12U)
+#define TIM_SMCR_ETPS_Msk (0x3U << TIM_SMCR_ETPS_Pos) /*!< 0x00003000 */
+#define TIM_SMCR_ETPS TIM_SMCR_ETPS_Msk /*!<ETPS[1:0] bits (External trigger prescaler) */
+#define TIM_SMCR_ETPS_0 (0x1U << TIM_SMCR_ETPS_Pos) /*!< 0x00001000 */
+#define TIM_SMCR_ETPS_1 (0x2U << TIM_SMCR_ETPS_Pos) /*!< 0x00002000 */
+
+#define TIM_SMCR_ECE_Pos (14U)
+#define TIM_SMCR_ECE_Msk (0x1U << TIM_SMCR_ECE_Pos) /*!< 0x00004000 */
+#define TIM_SMCR_ECE TIM_SMCR_ECE_Msk /*!<External clock enable */
+#define TIM_SMCR_ETP_Pos (15U)
+#define TIM_SMCR_ETP_Msk (0x1U << TIM_SMCR_ETP_Pos) /*!< 0x00008000 */
+#define TIM_SMCR_ETP TIM_SMCR_ETP_Msk /*!<External trigger polarity */
+
+/******************* Bit definition for TIM_DIER register ******************/
+#define TIM_DIER_UIE_Pos (0U)
+#define TIM_DIER_UIE_Msk (0x1U << TIM_DIER_UIE_Pos) /*!< 0x00000001 */
+#define TIM_DIER_UIE TIM_DIER_UIE_Msk /*!<Update interrupt enable */
+#define TIM_DIER_CC1IE_Pos (1U)
+#define TIM_DIER_CC1IE_Msk (0x1U << TIM_DIER_CC1IE_Pos) /*!< 0x00000002 */
+#define TIM_DIER_CC1IE TIM_DIER_CC1IE_Msk /*!<Capture/Compare 1 interrupt enable */
+#define TIM_DIER_CC2IE_Pos (2U)
+#define TIM_DIER_CC2IE_Msk (0x1U << TIM_DIER_CC2IE_Pos) /*!< 0x00000004 */
+#define TIM_DIER_CC2IE TIM_DIER_CC2IE_Msk /*!<Capture/Compare 2 interrupt enable */
+#define TIM_DIER_CC3IE_Pos (3U)
+#define TIM_DIER_CC3IE_Msk (0x1U << TIM_DIER_CC3IE_Pos) /*!< 0x00000008 */
+#define TIM_DIER_CC3IE TIM_DIER_CC3IE_Msk /*!<Capture/Compare 3 interrupt enable */
+#define TIM_DIER_CC4IE_Pos (4U)
+#define TIM_DIER_CC4IE_Msk (0x1U << TIM_DIER_CC4IE_Pos) /*!< 0x00000010 */
+#define TIM_DIER_CC4IE TIM_DIER_CC4IE_Msk /*!<Capture/Compare 4 interrupt enable */
+#define TIM_DIER_COMIE_Pos (5U)
+#define TIM_DIER_COMIE_Msk (0x1U << TIM_DIER_COMIE_Pos) /*!< 0x00000020 */
+#define TIM_DIER_COMIE TIM_DIER_COMIE_Msk /*!<COM interrupt enable */
+#define TIM_DIER_TIE_Pos (6U)
+#define TIM_DIER_TIE_Msk (0x1U << TIM_DIER_TIE_Pos) /*!< 0x00000040 */
+#define TIM_DIER_TIE TIM_DIER_TIE_Msk /*!<Trigger interrupt enable */
+#define TIM_DIER_BIE_Pos (7U)
+#define TIM_DIER_BIE_Msk (0x1U << TIM_DIER_BIE_Pos) /*!< 0x00000080 */
+#define TIM_DIER_BIE TIM_DIER_BIE_Msk /*!<Break interrupt enable */
+#define TIM_DIER_UDE_Pos (8U)
+#define TIM_DIER_UDE_Msk (0x1U << TIM_DIER_UDE_Pos) /*!< 0x00000100 */
+#define TIM_DIER_UDE TIM_DIER_UDE_Msk /*!<Update DMA request enable */
+#define TIM_DIER_CC1DE_Pos (9U)
+#define TIM_DIER_CC1DE_Msk (0x1U << TIM_DIER_CC1DE_Pos) /*!< 0x00000200 */
+#define TIM_DIER_CC1DE TIM_DIER_CC1DE_Msk /*!<Capture/Compare 1 DMA request enable */
+#define TIM_DIER_CC2DE_Pos (10U)
+#define TIM_DIER_CC2DE_Msk (0x1U << TIM_DIER_CC2DE_Pos) /*!< 0x00000400 */
+#define TIM_DIER_CC2DE TIM_DIER_CC2DE_Msk /*!<Capture/Compare 2 DMA request enable */
+#define TIM_DIER_CC3DE_Pos (11U)
+#define TIM_DIER_CC3DE_Msk (0x1U << TIM_DIER_CC3DE_Pos) /*!< 0x00000800 */
+#define TIM_DIER_CC3DE TIM_DIER_CC3DE_Msk /*!<Capture/Compare 3 DMA request enable */
+#define TIM_DIER_CC4DE_Pos (12U)
+#define TIM_DIER_CC4DE_Msk (0x1U << TIM_DIER_CC4DE_Pos) /*!< 0x00001000 */
+#define TIM_DIER_CC4DE TIM_DIER_CC4DE_Msk /*!<Capture/Compare 4 DMA request enable */
+#define TIM_DIER_COMDE_Pos (13U)
+#define TIM_DIER_COMDE_Msk (0x1U << TIM_DIER_COMDE_Pos) /*!< 0x00002000 */
+#define TIM_DIER_COMDE TIM_DIER_COMDE_Msk /*!<COM DMA request enable */
+#define TIM_DIER_TDE_Pos (14U)
+#define TIM_DIER_TDE_Msk (0x1U << TIM_DIER_TDE_Pos) /*!< 0x00004000 */
+#define TIM_DIER_TDE TIM_DIER_TDE_Msk /*!<Trigger DMA request enable */
+
+/******************** Bit definition for TIM_SR register *******************/
+#define TIM_SR_UIF_Pos (0U)
+#define TIM_SR_UIF_Msk (0x1U << TIM_SR_UIF_Pos) /*!< 0x00000001 */
+#define TIM_SR_UIF TIM_SR_UIF_Msk /*!<Update interrupt Flag */
+#define TIM_SR_CC1IF_Pos (1U)
+#define TIM_SR_CC1IF_Msk (0x1U << TIM_SR_CC1IF_Pos) /*!< 0x00000002 */
+#define TIM_SR_CC1IF TIM_SR_CC1IF_Msk /*!<Capture/Compare 1 interrupt Flag */
+#define TIM_SR_CC2IF_Pos (2U)
+#define TIM_SR_CC2IF_Msk (0x1U << TIM_SR_CC2IF_Pos) /*!< 0x00000004 */
+#define TIM_SR_CC2IF TIM_SR_CC2IF_Msk /*!<Capture/Compare 2 interrupt Flag */
+#define TIM_SR_CC3IF_Pos (3U)
+#define TIM_SR_CC3IF_Msk (0x1U << TIM_SR_CC3IF_Pos) /*!< 0x00000008 */
+#define TIM_SR_CC3IF TIM_SR_CC3IF_Msk /*!<Capture/Compare 3 interrupt Flag */
+#define TIM_SR_CC4IF_Pos (4U)
+#define TIM_SR_CC4IF_Msk (0x1U << TIM_SR_CC4IF_Pos) /*!< 0x00000010 */
+#define TIM_SR_CC4IF TIM_SR_CC4IF_Msk /*!<Capture/Compare 4 interrupt Flag */
+#define TIM_SR_COMIF_Pos (5U)
+#define TIM_SR_COMIF_Msk (0x1U << TIM_SR_COMIF_Pos) /*!< 0x00000020 */
+#define TIM_SR_COMIF TIM_SR_COMIF_Msk /*!<COM interrupt Flag */
+#define TIM_SR_TIF_Pos (6U)
+#define TIM_SR_TIF_Msk (0x1U << TIM_SR_TIF_Pos) /*!< 0x00000040 */
+#define TIM_SR_TIF TIM_SR_TIF_Msk /*!<Trigger interrupt Flag */
+#define TIM_SR_BIF_Pos (7U)
+#define TIM_SR_BIF_Msk (0x1U << TIM_SR_BIF_Pos) /*!< 0x00000080 */
+#define TIM_SR_BIF TIM_SR_BIF_Msk /*!<Break interrupt Flag */
+#define TIM_SR_CC1OF_Pos (9U)
+#define TIM_SR_CC1OF_Msk (0x1U << TIM_SR_CC1OF_Pos) /*!< 0x00000200 */
+#define TIM_SR_CC1OF TIM_SR_CC1OF_Msk /*!<Capture/Compare 1 Overcapture Flag */
+#define TIM_SR_CC2OF_Pos (10U)
+#define TIM_SR_CC2OF_Msk (0x1U << TIM_SR_CC2OF_Pos) /*!< 0x00000400 */
+#define TIM_SR_CC2OF TIM_SR_CC2OF_Msk /*!<Capture/Compare 2 Overcapture Flag */
+#define TIM_SR_CC3OF_Pos (11U)
+#define TIM_SR_CC3OF_Msk (0x1U << TIM_SR_CC3OF_Pos) /*!< 0x00000800 */
+#define TIM_SR_CC3OF TIM_SR_CC3OF_Msk /*!<Capture/Compare 3 Overcapture Flag */
+#define TIM_SR_CC4OF_Pos (12U)
+#define TIM_SR_CC4OF_Msk (0x1U << TIM_SR_CC4OF_Pos) /*!< 0x00001000 */
+#define TIM_SR_CC4OF TIM_SR_CC4OF_Msk /*!<Capture/Compare 4 Overcapture Flag */
+
+/******************* Bit definition for TIM_EGR register *******************/
+#define TIM_EGR_UG_Pos (0U)
+#define TIM_EGR_UG_Msk (0x1U << TIM_EGR_UG_Pos) /*!< 0x00000001 */
+#define TIM_EGR_UG TIM_EGR_UG_Msk /*!<Update Generation */
+#define TIM_EGR_CC1G_Pos (1U)
+#define TIM_EGR_CC1G_Msk (0x1U << TIM_EGR_CC1G_Pos) /*!< 0x00000002 */
+#define TIM_EGR_CC1G TIM_EGR_CC1G_Msk /*!<Capture/Compare 1 Generation */
+#define TIM_EGR_CC2G_Pos (2U)
+#define TIM_EGR_CC2G_Msk (0x1U << TIM_EGR_CC2G_Pos) /*!< 0x00000004 */
+#define TIM_EGR_CC2G TIM_EGR_CC2G_Msk /*!<Capture/Compare 2 Generation */
+#define TIM_EGR_CC3G_Pos (3U)
+#define TIM_EGR_CC3G_Msk (0x1U << TIM_EGR_CC3G_Pos) /*!< 0x00000008 */
+#define TIM_EGR_CC3G TIM_EGR_CC3G_Msk /*!<Capture/Compare 3 Generation */
+#define TIM_EGR_CC4G_Pos (4U)
+#define TIM_EGR_CC4G_Msk (0x1U << TIM_EGR_CC4G_Pos) /*!< 0x00000010 */
+#define TIM_EGR_CC4G TIM_EGR_CC4G_Msk /*!<Capture/Compare 4 Generation */
+#define TIM_EGR_COMG_Pos (5U)
+#define TIM_EGR_COMG_Msk (0x1U << TIM_EGR_COMG_Pos) /*!< 0x00000020 */
+#define TIM_EGR_COMG TIM_EGR_COMG_Msk /*!<Capture/Compare Control Update Generation */
+#define TIM_EGR_TG_Pos (6U)
+#define TIM_EGR_TG_Msk (0x1U << TIM_EGR_TG_Pos) /*!< 0x00000040 */
+#define TIM_EGR_TG TIM_EGR_TG_Msk /*!<Trigger Generation */
+#define TIM_EGR_BG_Pos (7U)
+#define TIM_EGR_BG_Msk (0x1U << TIM_EGR_BG_Pos) /*!< 0x00000080 */
+#define TIM_EGR_BG TIM_EGR_BG_Msk /*!<Break Generation */
+
+/****************** Bit definition for TIM_CCMR1 register ******************/
+#define TIM_CCMR1_CC1S_Pos (0U)
+#define TIM_CCMR1_CC1S_Msk (0x3U << TIM_CCMR1_CC1S_Pos) /*!< 0x00000003 */
+#define TIM_CCMR1_CC1S TIM_CCMR1_CC1S_Msk /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
+#define TIM_CCMR1_CC1S_0 (0x1U << TIM_CCMR1_CC1S_Pos) /*!< 0x00000001 */
+#define TIM_CCMR1_CC1S_1 (0x2U << TIM_CCMR1_CC1S_Pos) /*!< 0x00000002 */
+
+#define TIM_CCMR1_OC1FE_Pos (2U)
+#define TIM_CCMR1_OC1FE_Msk (0x1U << TIM_CCMR1_OC1FE_Pos) /*!< 0x00000004 */
+#define TIM_CCMR1_OC1FE TIM_CCMR1_OC1FE_Msk /*!<Output Compare 1 Fast enable */
+#define TIM_CCMR1_OC1PE_Pos (3U)
+#define TIM_CCMR1_OC1PE_Msk (0x1U << TIM_CCMR1_OC1PE_Pos) /*!< 0x00000008 */
+#define TIM_CCMR1_OC1PE TIM_CCMR1_OC1PE_Msk /*!<Output Compare 1 Preload enable */
+
+#define TIM_CCMR1_OC1M_Pos (4U)
+#define TIM_CCMR1_OC1M_Msk (0x7U << TIM_CCMR1_OC1M_Pos) /*!< 0x00000070 */
+#define TIM_CCMR1_OC1M TIM_CCMR1_OC1M_Msk /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
+#define TIM_CCMR1_OC1M_0 (0x1U << TIM_CCMR1_OC1M_Pos) /*!< 0x00000010 */
+#define TIM_CCMR1_OC1M_1 (0x2U << TIM_CCMR1_OC1M_Pos) /*!< 0x00000020 */
+#define TIM_CCMR1_OC1M_2 (0x4U << TIM_CCMR1_OC1M_Pos) /*!< 0x00000040 */
+
+#define TIM_CCMR1_OC1CE_Pos (7U)
+#define TIM_CCMR1_OC1CE_Msk (0x1U << TIM_CCMR1_OC1CE_Pos) /*!< 0x00000080 */
+#define TIM_CCMR1_OC1CE TIM_CCMR1_OC1CE_Msk /*!<Output Compare 1Clear Enable */
+
+#define TIM_CCMR1_CC2S_Pos (8U)
+#define TIM_CCMR1_CC2S_Msk (0x3U << TIM_CCMR1_CC2S_Pos) /*!< 0x00000300 */
+#define TIM_CCMR1_CC2S TIM_CCMR1_CC2S_Msk /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
+#define TIM_CCMR1_CC2S_0 (0x1U << TIM_CCMR1_CC2S_Pos) /*!< 0x00000100 */
+#define TIM_CCMR1_CC2S_1 (0x2U << TIM_CCMR1_CC2S_Pos) /*!< 0x00000200 */
+
+#define TIM_CCMR1_OC2FE_Pos (10U)
+#define TIM_CCMR1_OC2FE_Msk (0x1U << TIM_CCMR1_OC2FE_Pos) /*!< 0x00000400 */
+#define TIM_CCMR1_OC2FE TIM_CCMR1_OC2FE_Msk /*!<Output Compare 2 Fast enable */
+#define TIM_CCMR1_OC2PE_Pos (11U)
+#define TIM_CCMR1_OC2PE_Msk (0x1U << TIM_CCMR1_OC2PE_Pos) /*!< 0x00000800 */
+#define TIM_CCMR1_OC2PE TIM_CCMR1_OC2PE_Msk /*!<Output Compare 2 Preload enable */
+
+#define TIM_CCMR1_OC2M_Pos (12U)
+#define TIM_CCMR1_OC2M_Msk (0x7U << TIM_CCMR1_OC2M_Pos) /*!< 0x00007000 */
+#define TIM_CCMR1_OC2M TIM_CCMR1_OC2M_Msk /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
+#define TIM_CCMR1_OC2M_0 (0x1U << TIM_CCMR1_OC2M_Pos) /*!< 0x00001000 */
+#define TIM_CCMR1_OC2M_1 (0x2U << TIM_CCMR1_OC2M_Pos) /*!< 0x00002000 */
+#define TIM_CCMR1_OC2M_2 (0x4U << TIM_CCMR1_OC2M_Pos) /*!< 0x00004000 */
+
+#define TIM_CCMR1_OC2CE_Pos (15U)
+#define TIM_CCMR1_OC2CE_Msk (0x1U << TIM_CCMR1_OC2CE_Pos) /*!< 0x00008000 */
+#define TIM_CCMR1_OC2CE TIM_CCMR1_OC2CE_Msk /*!<Output Compare 2 Clear Enable */
+
+/*---------------------------------------------------------------------------*/
+
+#define TIM_CCMR1_IC1PSC_Pos (2U)
+#define TIM_CCMR1_IC1PSC_Msk (0x3U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x0000000C */
+#define TIM_CCMR1_IC1PSC TIM_CCMR1_IC1PSC_Msk /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
+#define TIM_CCMR1_IC1PSC_0 (0x1U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x00000004 */
+#define TIM_CCMR1_IC1PSC_1 (0x2U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x00000008 */
+
+#define TIM_CCMR1_IC1F_Pos (4U)
+#define TIM_CCMR1_IC1F_Msk (0xFU << TIM_CCMR1_IC1F_Pos) /*!< 0x000000F0 */
+#define TIM_CCMR1_IC1F TIM_CCMR1_IC1F_Msk /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
+#define TIM_CCMR1_IC1F_0 (0x1U << TIM_CCMR1_IC1F_Pos) /*!< 0x00000010 */
+#define TIM_CCMR1_IC1F_1 (0x2U << TIM_CCMR1_IC1F_Pos) /*!< 0x00000020 */
+#define TIM_CCMR1_IC1F_2 (0x4U << TIM_CCMR1_IC1F_Pos) /*!< 0x00000040 */
+#define TIM_CCMR1_IC1F_3 (0x8U << TIM_CCMR1_IC1F_Pos) /*!< 0x00000080 */
+
+#define TIM_CCMR1_IC2PSC_Pos (10U)
+#define TIM_CCMR1_IC2PSC_Msk (0x3U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000C00 */
+#define TIM_CCMR1_IC2PSC TIM_CCMR1_IC2PSC_Msk /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
+#define TIM_CCMR1_IC2PSC_0 (0x1U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000400 */
+#define TIM_CCMR1_IC2PSC_1 (0x2U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000800 */
+
+#define TIM_CCMR1_IC2F_Pos (12U)
+#define TIM_CCMR1_IC2F_Msk (0xFU << TIM_CCMR1_IC2F_Pos) /*!< 0x0000F000 */
+#define TIM_CCMR1_IC2F TIM_CCMR1_IC2F_Msk /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
+#define TIM_CCMR1_IC2F_0 (0x1U << TIM_CCMR1_IC2F_Pos) /*!< 0x00001000 */
+#define TIM_CCMR1_IC2F_1 (0x2U << TIM_CCMR1_IC2F_Pos) /*!< 0x00002000 */
+#define TIM_CCMR1_IC2F_2 (0x4U << TIM_CCMR1_IC2F_Pos) /*!< 0x00004000 */
+#define TIM_CCMR1_IC2F_3 (0x8U << TIM_CCMR1_IC2F_Pos) /*!< 0x00008000 */
+
+/****************** Bit definition for TIM_CCMR2 register ******************/
+#define TIM_CCMR2_CC3S_Pos (0U)
+#define TIM_CCMR2_CC3S_Msk (0x3U << TIM_CCMR2_CC3S_Pos) /*!< 0x00000003 */
+#define TIM_CCMR2_CC3S TIM_CCMR2_CC3S_Msk /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
+#define TIM_CCMR2_CC3S_0 (0x1U << TIM_CCMR2_CC3S_Pos) /*!< 0x00000001 */
+#define TIM_CCMR2_CC3S_1 (0x2U << TIM_CCMR2_CC3S_Pos) /*!< 0x00000002 */
+
+#define TIM_CCMR2_OC3FE_Pos (2U)
+#define TIM_CCMR2_OC3FE_Msk (0x1U << TIM_CCMR2_OC3FE_Pos) /*!< 0x00000004 */
+#define TIM_CCMR2_OC3FE TIM_CCMR2_OC3FE_Msk /*!<Output Compare 3 Fast enable */
+#define TIM_CCMR2_OC3PE_Pos (3U)
+#define TIM_CCMR2_OC3PE_Msk (0x1U << TIM_CCMR2_OC3PE_Pos) /*!< 0x00000008 */
+#define TIM_CCMR2_OC3PE TIM_CCMR2_OC3PE_Msk /*!<Output Compare 3 Preload enable */
+
+#define TIM_CCMR2_OC3M_Pos (4U)
+#define TIM_CCMR2_OC3M_Msk (0x7U << TIM_CCMR2_OC3M_Pos) /*!< 0x00000070 */
+#define TIM_CCMR2_OC3M TIM_CCMR2_OC3M_Msk /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
+#define TIM_CCMR2_OC3M_0 (0x1U << TIM_CCMR2_OC3M_Pos) /*!< 0x00000010 */
+#define TIM_CCMR2_OC3M_1 (0x2U << TIM_CCMR2_OC3M_Pos) /*!< 0x00000020 */
+#define TIM_CCMR2_OC3M_2 (0x4U << TIM_CCMR2_OC3M_Pos) /*!< 0x00000040 */
+
+#define TIM_CCMR2_OC3CE_Pos (7U)
+#define TIM_CCMR2_OC3CE_Msk (0x1U << TIM_CCMR2_OC3CE_Pos) /*!< 0x00000080 */
+#define TIM_CCMR2_OC3CE TIM_CCMR2_OC3CE_Msk /*!<Output Compare 3 Clear Enable */
+
+#define TIM_CCMR2_CC4S_Pos (8U)
+#define TIM_CCMR2_CC4S_Msk (0x3U << TIM_CCMR2_CC4S_Pos) /*!< 0x00000300 */
+#define TIM_CCMR2_CC4S TIM_CCMR2_CC4S_Msk /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
+#define TIM_CCMR2_CC4S_0 (0x1U << TIM_CCMR2_CC4S_Pos) /*!< 0x00000100 */
+#define TIM_CCMR2_CC4S_1 (0x2U << TIM_CCMR2_CC4S_Pos) /*!< 0x00000200 */
+
+#define TIM_CCMR2_OC4FE_Pos (10U)
+#define TIM_CCMR2_OC4FE_Msk (0x1U << TIM_CCMR2_OC4FE_Pos) /*!< 0x00000400 */
+#define TIM_CCMR2_OC4FE TIM_CCMR2_OC4FE_Msk /*!<Output Compare 4 Fast enable */
+#define TIM_CCMR2_OC4PE_Pos (11U)
+#define TIM_CCMR2_OC4PE_Msk (0x1U << TIM_CCMR2_OC4PE_Pos) /*!< 0x00000800 */
+#define TIM_CCMR2_OC4PE TIM_CCMR2_OC4PE_Msk /*!<Output Compare 4 Preload enable */
+
+#define TIM_CCMR2_OC4M_Pos (12U)
+#define TIM_CCMR2_OC4M_Msk (0x7U << TIM_CCMR2_OC4M_Pos) /*!< 0x00007000 */
+#define TIM_CCMR2_OC4M TIM_CCMR2_OC4M_Msk /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
+#define TIM_CCMR2_OC4M_0 (0x1U << TIM_CCMR2_OC4M_Pos) /*!< 0x00001000 */
+#define TIM_CCMR2_OC4M_1 (0x2U << TIM_CCMR2_OC4M_Pos) /*!< 0x00002000 */
+#define TIM_CCMR2_OC4M_2 (0x4U << TIM_CCMR2_OC4M_Pos) /*!< 0x00004000 */
+
+#define TIM_CCMR2_OC4CE_Pos (15U)
+#define TIM_CCMR2_OC4CE_Msk (0x1U << TIM_CCMR2_OC4CE_Pos) /*!< 0x00008000 */
+#define TIM_CCMR2_OC4CE TIM_CCMR2_OC4CE_Msk /*!<Output Compare 4 Clear Enable */
+
+/*---------------------------------------------------------------------------*/
+
+#define TIM_CCMR2_IC3PSC_Pos (2U)
+#define TIM_CCMR2_IC3PSC_Msk (0x3U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x0000000C */
+#define TIM_CCMR2_IC3PSC TIM_CCMR2_IC3PSC_Msk /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
+#define TIM_CCMR2_IC3PSC_0 (0x1U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x00000004 */
+#define TIM_CCMR2_IC3PSC_1 (0x2U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x00000008 */
+
+#define TIM_CCMR2_IC3F_Pos (4U)
+#define TIM_CCMR2_IC3F_Msk (0xFU << TIM_CCMR2_IC3F_Pos) /*!< 0x000000F0 */
+#define TIM_CCMR2_IC3F TIM_CCMR2_IC3F_Msk /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
+#define TIM_CCMR2_IC3F_0 (0x1U << TIM_CCMR2_IC3F_Pos) /*!< 0x00000010 */
+#define TIM_CCMR2_IC3F_1 (0x2U << TIM_CCMR2_IC3F_Pos) /*!< 0x00000020 */
+#define TIM_CCMR2_IC3F_2 (0x4U << TIM_CCMR2_IC3F_Pos) /*!< 0x00000040 */
+#define TIM_CCMR2_IC3F_3 (0x8U << TIM_CCMR2_IC3F_Pos) /*!< 0x00000080 */
+
+#define TIM_CCMR2_IC4PSC_Pos (10U)
+#define TIM_CCMR2_IC4PSC_Msk (0x3U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000C00 */
+#define TIM_CCMR2_IC4PSC TIM_CCMR2_IC4PSC_Msk /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
+#define TIM_CCMR2_IC4PSC_0 (0x1U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000400 */
+#define TIM_CCMR2_IC4PSC_1 (0x2U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000800 */
+
+#define TIM_CCMR2_IC4F_Pos (12U)
+#define TIM_CCMR2_IC4F_Msk (0xFU << TIM_CCMR2_IC4F_Pos) /*!< 0x0000F000 */
+#define TIM_CCMR2_IC4F TIM_CCMR2_IC4F_Msk /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
+#define TIM_CCMR2_IC4F_0 (0x1U << TIM_CCMR2_IC4F_Pos) /*!< 0x00001000 */
+#define TIM_CCMR2_IC4F_1 (0x2U << TIM_CCMR2_IC4F_Pos) /*!< 0x00002000 */
+#define TIM_CCMR2_IC4F_2 (0x4U << TIM_CCMR2_IC4F_Pos) /*!< 0x00004000 */
+#define TIM_CCMR2_IC4F_3 (0x8U << TIM_CCMR2_IC4F_Pos) /*!< 0x00008000 */
+
+/******************* Bit definition for TIM_CCER register ******************/
+#define TIM_CCER_CC1E_Pos (0U)
+#define TIM_CCER_CC1E_Msk (0x1U << TIM_CCER_CC1E_Pos) /*!< 0x00000001 */
+#define TIM_CCER_CC1E TIM_CCER_CC1E_Msk /*!<Capture/Compare 1 output enable */
+#define TIM_CCER_CC1P_Pos (1U)
+#define TIM_CCER_CC1P_Msk (0x1U << TIM_CCER_CC1P_Pos) /*!< 0x00000002 */
+#define TIM_CCER_CC1P TIM_CCER_CC1P_Msk /*!<Capture/Compare 1 output Polarity */
+#define TIM_CCER_CC1NE_Pos (2U)
+#define TIM_CCER_CC1NE_Msk (0x1U << TIM_CCER_CC1NE_Pos) /*!< 0x00000004 */
+#define TIM_CCER_CC1NE TIM_CCER_CC1NE_Msk /*!<Capture/Compare 1 Complementary output enable */
+#define TIM_CCER_CC1NP_Pos (3U)
+#define TIM_CCER_CC1NP_Msk (0x1U << TIM_CCER_CC1NP_Pos) /*!< 0x00000008 */
+#define TIM_CCER_CC1NP TIM_CCER_CC1NP_Msk /*!<Capture/Compare 1 Complementary output Polarity */
+#define TIM_CCER_CC2E_Pos (4U)
+#define TIM_CCER_CC2E_Msk (0x1U << TIM_CCER_CC2E_Pos) /*!< 0x00000010 */
+#define TIM_CCER_CC2E TIM_CCER_CC2E_Msk /*!<Capture/Compare 2 output enable */
+#define TIM_CCER_CC2P_Pos (5U)
+#define TIM_CCER_CC2P_Msk (0x1U << TIM_CCER_CC2P_Pos) /*!< 0x00000020 */
+#define TIM_CCER_CC2P TIM_CCER_CC2P_Msk /*!<Capture/Compare 2 output Polarity */
+#define TIM_CCER_CC2NE_Pos (6U)
+#define TIM_CCER_CC2NE_Msk (0x1U << TIM_CCER_CC2NE_Pos) /*!< 0x00000040 */
+#define TIM_CCER_CC2NE TIM_CCER_CC2NE_Msk /*!<Capture/Compare 2 Complementary output enable */
+#define TIM_CCER_CC2NP_Pos (7U)
+#define TIM_CCER_CC2NP_Msk (0x1U << TIM_CCER_CC2NP_Pos) /*!< 0x00000080 */
+#define TIM_CCER_CC2NP TIM_CCER_CC2NP_Msk /*!<Capture/Compare 2 Complementary output Polarity */
+#define TIM_CCER_CC3E_Pos (8U)
+#define TIM_CCER_CC3E_Msk (0x1U << TIM_CCER_CC3E_Pos) /*!< 0x00000100 */
+#define TIM_CCER_CC3E TIM_CCER_CC3E_Msk /*!<Capture/Compare 3 output enable */
+#define TIM_CCER_CC3P_Pos (9U)
+#define TIM_CCER_CC3P_Msk (0x1U << TIM_CCER_CC3P_Pos) /*!< 0x00000200 */
+#define TIM_CCER_CC3P TIM_CCER_CC3P_Msk /*!<Capture/Compare 3 output Polarity */
+#define TIM_CCER_CC3NE_Pos (10U)
+#define TIM_CCER_CC3NE_Msk (0x1U << TIM_CCER_CC3NE_Pos) /*!< 0x00000400 */
+#define TIM_CCER_CC3NE TIM_CCER_CC3NE_Msk /*!<Capture/Compare 3 Complementary output enable */
+#define TIM_CCER_CC3NP_Pos (11U)
+#define TIM_CCER_CC3NP_Msk (0x1U << TIM_CCER_CC3NP_Pos) /*!< 0x00000800 */
+#define TIM_CCER_CC3NP TIM_CCER_CC3NP_Msk /*!<Capture/Compare 3 Complementary output Polarity */
+#define TIM_CCER_CC4E_Pos (12U)
+#define TIM_CCER_CC4E_Msk (0x1U << TIM_CCER_CC4E_Pos) /*!< 0x00001000 */
+#define TIM_CCER_CC4E TIM_CCER_CC4E_Msk /*!<Capture/Compare 4 output enable */
+#define TIM_CCER_CC4P_Pos (13U)
+#define TIM_CCER_CC4P_Msk (0x1U << TIM_CCER_CC4P_Pos) /*!< 0x00002000 */
+#define TIM_CCER_CC4P TIM_CCER_CC4P_Msk /*!<Capture/Compare 4 output Polarity */
+#define TIM_CCER_CC4NP_Pos (15U)
+#define TIM_CCER_CC4NP_Msk (0x1U << TIM_CCER_CC4NP_Pos) /*!< 0x00008000 */
+#define TIM_CCER_CC4NP TIM_CCER_CC4NP_Msk /*!<Capture/Compare 4 Complementary output Polarity */
+
+/******************* Bit definition for TIM_CNT register *******************/
+#define TIM_CNT_CNT_Pos (0U)
+#define TIM_CNT_CNT_Msk (0xFFFFFFFFU << TIM_CNT_CNT_Pos) /*!< 0xFFFFFFFF */
+#define TIM_CNT_CNT TIM_CNT_CNT_Msk /*!<Counter Value */
+
+/******************* Bit definition for TIM_PSC register *******************/
+#define TIM_PSC_PSC_Pos (0U)
+#define TIM_PSC_PSC_Msk (0xFFFFU << TIM_PSC_PSC_Pos) /*!< 0x0000FFFF */
+#define TIM_PSC_PSC TIM_PSC_PSC_Msk /*!<Prescaler Value */
+
+/******************* Bit definition for TIM_ARR register *******************/
+#define TIM_ARR_ARR_Pos (0U)
+#define TIM_ARR_ARR_Msk (0xFFFFFFFFU << TIM_ARR_ARR_Pos) /*!< 0xFFFFFFFF */
+#define TIM_ARR_ARR TIM_ARR_ARR_Msk /*!<actual auto-reload Value */
+
+/******************* Bit definition for TIM_RCR register *******************/
+#define TIM_RCR_REP_Pos (0U)
+#define TIM_RCR_REP_Msk (0xFFU << TIM_RCR_REP_Pos) /*!< 0x000000FF */
+#define TIM_RCR_REP TIM_RCR_REP_Msk /*!<Repetition Counter Value */
+
+/******************* Bit definition for TIM_CCR1 register ******************/
+#define TIM_CCR1_CCR1_Pos (0U)
+#define TIM_CCR1_CCR1_Msk (0xFFFFU << TIM_CCR1_CCR1_Pos) /*!< 0x0000FFFF */
+#define TIM_CCR1_CCR1 TIM_CCR1_CCR1_Msk /*!<Capture/Compare 1 Value */
+
+/******************* Bit definition for TIM_CCR2 register ******************/
+#define TIM_CCR2_CCR2_Pos (0U)
+#define TIM_CCR2_CCR2_Msk (0xFFFFU << TIM_CCR2_CCR2_Pos) /*!< 0x0000FFFF */
+#define TIM_CCR2_CCR2 TIM_CCR2_CCR2_Msk /*!<Capture/Compare 2 Value */
+
+/******************* Bit definition for TIM_CCR3 register ******************/
+#define TIM_CCR3_CCR3_Pos (0U)
+#define TIM_CCR3_CCR3_Msk (0xFFFFU << TIM_CCR3_CCR3_Pos) /*!< 0x0000FFFF */
+#define TIM_CCR3_CCR3 TIM_CCR3_CCR3_Msk /*!<Capture/Compare 3 Value */
+
+/******************* Bit definition for TIM_CCR4 register ******************/
+#define TIM_CCR4_CCR4_Pos (0U)
+#define TIM_CCR4_CCR4_Msk (0xFFFFU << TIM_CCR4_CCR4_Pos) /*!< 0x0000FFFF */
+#define TIM_CCR4_CCR4 TIM_CCR4_CCR4_Msk /*!<Capture/Compare 4 Value */
+
+/******************* Bit definition for TIM_BDTR register ******************/
+#define TIM_BDTR_DTG_Pos (0U)
+#define TIM_BDTR_DTG_Msk (0xFFU << TIM_BDTR_DTG_Pos) /*!< 0x000000FF */
+#define TIM_BDTR_DTG TIM_BDTR_DTG_Msk /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
+#define TIM_BDTR_DTG_0 (0x01U << TIM_BDTR_DTG_Pos) /*!< 0x00000001 */
+#define TIM_BDTR_DTG_1 (0x02U << TIM_BDTR_DTG_Pos) /*!< 0x00000002 */
+#define TIM_BDTR_DTG_2 (0x04U << TIM_BDTR_DTG_Pos) /*!< 0x00000004 */
+#define TIM_BDTR_DTG_3 (0x08U << TIM_BDTR_DTG_Pos) /*!< 0x00000008 */
+#define TIM_BDTR_DTG_4 (0x10U << TIM_BDTR_DTG_Pos) /*!< 0x00000010 */
+#define TIM_BDTR_DTG_5 (0x20U << TIM_BDTR_DTG_Pos) /*!< 0x00000020 */
+#define TIM_BDTR_DTG_6 (0x40U << TIM_BDTR_DTG_Pos) /*!< 0x00000040 */
+#define TIM_BDTR_DTG_7 (0x80U << TIM_BDTR_DTG_Pos) /*!< 0x00000080 */
+
+#define TIM_BDTR_LOCK_Pos (8U)
+#define TIM_BDTR_LOCK_Msk (0x3U << TIM_BDTR_LOCK_Pos) /*!< 0x00000300 */
+#define TIM_BDTR_LOCK TIM_BDTR_LOCK_Msk /*!<LOCK[1:0] bits (Lock Configuration) */
+#define TIM_BDTR_LOCK_0 (0x1U << TIM_BDTR_LOCK_Pos) /*!< 0x00000100 */
+#define TIM_BDTR_LOCK_1 (0x2U << TIM_BDTR_LOCK_Pos) /*!< 0x00000200 */
+
+#define TIM_BDTR_OSSI_Pos (10U)
+#define TIM_BDTR_OSSI_Msk (0x1U << TIM_BDTR_OSSI_Pos) /*!< 0x00000400 */
+#define TIM_BDTR_OSSI TIM_BDTR_OSSI_Msk /*!<Off-State Selection for Idle mode */
+#define TIM_BDTR_OSSR_Pos (11U)
+#define TIM_BDTR_OSSR_Msk (0x1U << TIM_BDTR_OSSR_Pos) /*!< 0x00000800 */
+#define TIM_BDTR_OSSR TIM_BDTR_OSSR_Msk /*!<Off-State Selection for Run mode */
+#define TIM_BDTR_BKE_Pos (12U)
+#define TIM_BDTR_BKE_Msk (0x1U << TIM_BDTR_BKE_Pos) /*!< 0x00001000 */
+#define TIM_BDTR_BKE TIM_BDTR_BKE_Msk /*!<Break enable */
+#define TIM_BDTR_BKP_Pos (13U)
+#define TIM_BDTR_BKP_Msk (0x1U << TIM_BDTR_BKP_Pos) /*!< 0x00002000 */
+#define TIM_BDTR_BKP TIM_BDTR_BKP_Msk /*!<Break Polarity */
+#define TIM_BDTR_AOE_Pos (14U)
+#define TIM_BDTR_AOE_Msk (0x1U << TIM_BDTR_AOE_Pos) /*!< 0x00004000 */
+#define TIM_BDTR_AOE TIM_BDTR_AOE_Msk /*!<Automatic Output enable */
+#define TIM_BDTR_MOE_Pos (15U)
+#define TIM_BDTR_MOE_Msk (0x1U << TIM_BDTR_MOE_Pos) /*!< 0x00008000 */
+#define TIM_BDTR_MOE TIM_BDTR_MOE_Msk /*!<Main Output enable */
+
+/******************* Bit definition for TIM_DCR register *******************/
+#define TIM_DCR_DBA_Pos (0U)
+#define TIM_DCR_DBA_Msk (0x1FU << TIM_DCR_DBA_Pos) /*!< 0x0000001F */
+#define TIM_DCR_DBA TIM_DCR_DBA_Msk /*!<DBA[4:0] bits (DMA Base Address) */
+#define TIM_DCR_DBA_0 (0x01U << TIM_DCR_DBA_Pos) /*!< 0x00000001 */
+#define TIM_DCR_DBA_1 (0x02U << TIM_DCR_DBA_Pos) /*!< 0x00000002 */
+#define TIM_DCR_DBA_2 (0x04U << TIM_DCR_DBA_Pos) /*!< 0x00000004 */
+#define TIM_DCR_DBA_3 (0x08U << TIM_DCR_DBA_Pos) /*!< 0x00000008 */
+#define TIM_DCR_DBA_4 (0x10U << TIM_DCR_DBA_Pos) /*!< 0x00000010 */
+
+#define TIM_DCR_DBL_Pos (8U)
+#define TIM_DCR_DBL_Msk (0x1FU << TIM_DCR_DBL_Pos) /*!< 0x00001F00 */
+#define TIM_DCR_DBL TIM_DCR_DBL_Msk /*!<DBL[4:0] bits (DMA Burst Length) */
+#define TIM_DCR_DBL_0 (0x01U << TIM_DCR_DBL_Pos) /*!< 0x00000100 */
+#define TIM_DCR_DBL_1 (0x02U << TIM_DCR_DBL_Pos) /*!< 0x00000200 */
+#define TIM_DCR_DBL_2 (0x04U << TIM_DCR_DBL_Pos) /*!< 0x00000400 */
+#define TIM_DCR_DBL_3 (0x08U << TIM_DCR_DBL_Pos) /*!< 0x00000800 */
+#define TIM_DCR_DBL_4 (0x10U << TIM_DCR_DBL_Pos) /*!< 0x00001000 */
+
+/******************* Bit definition for TIM_DMAR register ******************/
+#define TIM_DMAR_DMAB_Pos (0U)
+#define TIM_DMAR_DMAB_Msk (0xFFFFU << TIM_DMAR_DMAB_Pos) /*!< 0x0000FFFF */
+#define TIM_DMAR_DMAB TIM_DMAR_DMAB_Msk /*!<DMA register for burst accesses */
+
+/******************* Bit definition for TIM_OR register ********************/
+
+/******************************************************************************/
+/* */
+/* Real-Time Clock */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for RTC_CRH register ********************/
+#define RTC_CRH_SECIE_Pos (0U)
+#define RTC_CRH_SECIE_Msk (0x1U << RTC_CRH_SECIE_Pos) /*!< 0x00000001 */
+#define RTC_CRH_SECIE RTC_CRH_SECIE_Msk /*!< Second Interrupt Enable */
+#define RTC_CRH_ALRIE_Pos (1U)
+#define RTC_CRH_ALRIE_Msk (0x1U << RTC_CRH_ALRIE_Pos) /*!< 0x00000002 */
+#define RTC_CRH_ALRIE RTC_CRH_ALRIE_Msk /*!< Alarm Interrupt Enable */
+#define RTC_CRH_OWIE_Pos (2U)
+#define RTC_CRH_OWIE_Msk (0x1U << RTC_CRH_OWIE_Pos) /*!< 0x00000004 */
+#define RTC_CRH_OWIE RTC_CRH_OWIE_Msk /*!< OverfloW Interrupt Enable */
+
+/******************* Bit definition for RTC_CRL register ********************/
+#define RTC_CRL_SECF_Pos (0U)
+#define RTC_CRL_SECF_Msk (0x1U << RTC_CRL_SECF_Pos) /*!< 0x00000001 */
+#define RTC_CRL_SECF RTC_CRL_SECF_Msk /*!< Second Flag */
+#define RTC_CRL_ALRF_Pos (1U)
+#define RTC_CRL_ALRF_Msk (0x1U << RTC_CRL_ALRF_Pos) /*!< 0x00000002 */
+#define RTC_CRL_ALRF RTC_CRL_ALRF_Msk /*!< Alarm Flag */
+#define RTC_CRL_OWF_Pos (2U)
+#define RTC_CRL_OWF_Msk (0x1U << RTC_CRL_OWF_Pos) /*!< 0x00000004 */
+#define RTC_CRL_OWF RTC_CRL_OWF_Msk /*!< OverfloW Flag */
+#define RTC_CRL_RSF_Pos (3U)
+#define RTC_CRL_RSF_Msk (0x1U << RTC_CRL_RSF_Pos) /*!< 0x00000008 */
+#define RTC_CRL_RSF RTC_CRL_RSF_Msk /*!< Registers Synchronized Flag */
+#define RTC_CRL_CNF_Pos (4U)
+#define RTC_CRL_CNF_Msk (0x1U << RTC_CRL_CNF_Pos) /*!< 0x00000010 */
+#define RTC_CRL_CNF RTC_CRL_CNF_Msk /*!< Configuration Flag */
+#define RTC_CRL_RTOFF_Pos (5U)
+#define RTC_CRL_RTOFF_Msk (0x1U << RTC_CRL_RTOFF_Pos) /*!< 0x00000020 */
+#define RTC_CRL_RTOFF RTC_CRL_RTOFF_Msk /*!< RTC operation OFF */
+
+/******************* Bit definition for RTC_PRLH register *******************/
+#define RTC_PRLH_PRL_Pos (0U)
+#define RTC_PRLH_PRL_Msk (0xFU << RTC_PRLH_PRL_Pos) /*!< 0x0000000F */
+#define RTC_PRLH_PRL RTC_PRLH_PRL_Msk /*!< RTC Prescaler Reload Value High */
+
+/******************* Bit definition for RTC_PRLL register *******************/
+#define RTC_PRLL_PRL_Pos (0U)
+#define RTC_PRLL_PRL_Msk (0xFFFFU << RTC_PRLL_PRL_Pos) /*!< 0x0000FFFF */
+#define RTC_PRLL_PRL RTC_PRLL_PRL_Msk /*!< RTC Prescaler Reload Value Low */
+
+/******************* Bit definition for RTC_DIVH register *******************/
+#define RTC_DIVH_RTC_DIV_Pos (0U)
+#define RTC_DIVH_RTC_DIV_Msk (0xFU << RTC_DIVH_RTC_DIV_Pos) /*!< 0x0000000F */
+#define RTC_DIVH_RTC_DIV RTC_DIVH_RTC_DIV_Msk /*!< RTC Clock Divider High */
+
+/******************* Bit definition for RTC_DIVL register *******************/
+#define RTC_DIVL_RTC_DIV_Pos (0U)
+#define RTC_DIVL_RTC_DIV_Msk (0xFFFFU << RTC_DIVL_RTC_DIV_Pos) /*!< 0x0000FFFF */
+#define RTC_DIVL_RTC_DIV RTC_DIVL_RTC_DIV_Msk /*!< RTC Clock Divider Low */
+
+/******************* Bit definition for RTC_CNTH register *******************/
+#define RTC_CNTH_RTC_CNT_Pos (0U)
+#define RTC_CNTH_RTC_CNT_Msk (0xFFFFU << RTC_CNTH_RTC_CNT_Pos) /*!< 0x0000FFFF */
+#define RTC_CNTH_RTC_CNT RTC_CNTH_RTC_CNT_Msk /*!< RTC Counter High */
+
+/******************* Bit definition for RTC_CNTL register *******************/
+#define RTC_CNTL_RTC_CNT_Pos (0U)
+#define RTC_CNTL_RTC_CNT_Msk (0xFFFFU << RTC_CNTL_RTC_CNT_Pos) /*!< 0x0000FFFF */
+#define RTC_CNTL_RTC_CNT RTC_CNTL_RTC_CNT_Msk /*!< RTC Counter Low */
+
+/******************* Bit definition for RTC_ALRH register *******************/
+#define RTC_ALRH_RTC_ALR_Pos (0U)
+#define RTC_ALRH_RTC_ALR_Msk (0xFFFFU << RTC_ALRH_RTC_ALR_Pos) /*!< 0x0000FFFF */
+#define RTC_ALRH_RTC_ALR RTC_ALRH_RTC_ALR_Msk /*!< RTC Alarm High */
+
+/******************* Bit definition for RTC_ALRL register *******************/
+#define RTC_ALRL_RTC_ALR_Pos (0U)
+#define RTC_ALRL_RTC_ALR_Msk (0xFFFFU << RTC_ALRL_RTC_ALR_Pos) /*!< 0x0000FFFF */
+#define RTC_ALRL_RTC_ALR RTC_ALRL_RTC_ALR_Msk /*!< RTC Alarm Low */
+
+/******************************************************************************/
+/* */
+/* Independent WATCHDOG (IWDG) */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for IWDG_KR register ********************/
+#define IWDG_KR_KEY_Pos (0U)
+#define IWDG_KR_KEY_Msk (0xFFFFU << IWDG_KR_KEY_Pos) /*!< 0x0000FFFF */
+#define IWDG_KR_KEY IWDG_KR_KEY_Msk /*!< Key value (write only, read 0000h) */
+
+/******************* Bit definition for IWDG_PR register ********************/
+#define IWDG_PR_PR_Pos (0U)
+#define IWDG_PR_PR_Msk (0x7U << IWDG_PR_PR_Pos) /*!< 0x00000007 */
+#define IWDG_PR_PR IWDG_PR_PR_Msk /*!< PR[2:0] (Prescaler divider) */
+#define IWDG_PR_PR_0 (0x1U << IWDG_PR_PR_Pos) /*!< 0x00000001 */
+#define IWDG_PR_PR_1 (0x2U << IWDG_PR_PR_Pos) /*!< 0x00000002 */
+#define IWDG_PR_PR_2 (0x4U << IWDG_PR_PR_Pos) /*!< 0x00000004 */
+
+/******************* Bit definition for IWDG_RLR register *******************/
+#define IWDG_RLR_RL_Pos (0U)
+#define IWDG_RLR_RL_Msk (0xFFFU << IWDG_RLR_RL_Pos) /*!< 0x00000FFF */
+#define IWDG_RLR_RL IWDG_RLR_RL_Msk /*!< Watchdog counter reload value */
+
+/******************* Bit definition for IWDG_SR register ********************/
+#define IWDG_SR_PVU_Pos (0U)
+#define IWDG_SR_PVU_Msk (0x1U << IWDG_SR_PVU_Pos) /*!< 0x00000001 */
+#define IWDG_SR_PVU IWDG_SR_PVU_Msk /*!< Watchdog prescaler value update */
+#define IWDG_SR_RVU_Pos (1U)
+#define IWDG_SR_RVU_Msk (0x1U << IWDG_SR_RVU_Pos) /*!< 0x00000002 */
+#define IWDG_SR_RVU IWDG_SR_RVU_Msk /*!< Watchdog counter reload value update */
+
+/******************************************************************************/
+/* */
+/* Window WATCHDOG (WWDG) */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for WWDG_CR register ********************/
+#define WWDG_CR_T_Pos (0U)
+#define WWDG_CR_T_Msk (0x7FU << WWDG_CR_T_Pos) /*!< 0x0000007F */
+#define WWDG_CR_T WWDG_CR_T_Msk /*!< T[6:0] bits (7-Bit counter (MSB to LSB)) */
+#define WWDG_CR_T_0 (0x01U << WWDG_CR_T_Pos) /*!< 0x00000001 */
+#define WWDG_CR_T_1 (0x02U << WWDG_CR_T_Pos) /*!< 0x00000002 */
+#define WWDG_CR_T_2 (0x04U << WWDG_CR_T_Pos) /*!< 0x00000004 */
+#define WWDG_CR_T_3 (0x08U << WWDG_CR_T_Pos) /*!< 0x00000008 */
+#define WWDG_CR_T_4 (0x10U << WWDG_CR_T_Pos) /*!< 0x00000010 */
+#define WWDG_CR_T_5 (0x20U << WWDG_CR_T_Pos) /*!< 0x00000020 */
+#define WWDG_CR_T_6 (0x40U << WWDG_CR_T_Pos) /*!< 0x00000040 */
+
+/* Legacy defines */
+#define WWDG_CR_T0 WWDG_CR_T_0
+#define WWDG_CR_T1 WWDG_CR_T_1
+#define WWDG_CR_T2 WWDG_CR_T_2
+#define WWDG_CR_T3 WWDG_CR_T_3
+#define WWDG_CR_T4 WWDG_CR_T_4
+#define WWDG_CR_T5 WWDG_CR_T_5
+#define WWDG_CR_T6 WWDG_CR_T_6
+
+#define WWDG_CR_WDGA_Pos (7U)
+#define WWDG_CR_WDGA_Msk (0x1U << WWDG_CR_WDGA_Pos) /*!< 0x00000080 */
+#define WWDG_CR_WDGA WWDG_CR_WDGA_Msk /*!< Activation bit */
+
+/******************* Bit definition for WWDG_CFR register *******************/
+#define WWDG_CFR_W_Pos (0U)
+#define WWDG_CFR_W_Msk (0x7FU << WWDG_CFR_W_Pos) /*!< 0x0000007F */
+#define WWDG_CFR_W WWDG_CFR_W_Msk /*!< W[6:0] bits (7-bit window value) */
+#define WWDG_CFR_W_0 (0x01U << WWDG_CFR_W_Pos) /*!< 0x00000001 */
+#define WWDG_CFR_W_1 (0x02U << WWDG_CFR_W_Pos) /*!< 0x00000002 */
+#define WWDG_CFR_W_2 (0x04U << WWDG_CFR_W_Pos) /*!< 0x00000004 */
+#define WWDG_CFR_W_3 (0x08U << WWDG_CFR_W_Pos) /*!< 0x00000008 */
+#define WWDG_CFR_W_4 (0x10U << WWDG_CFR_W_Pos) /*!< 0x00000010 */
+#define WWDG_CFR_W_5 (0x20U << WWDG_CFR_W_Pos) /*!< 0x00000020 */
+#define WWDG_CFR_W_6 (0x40U << WWDG_CFR_W_Pos) /*!< 0x00000040 */
+
+/* Legacy defines */
+#define WWDG_CFR_W0 WWDG_CFR_W_0
+#define WWDG_CFR_W1 WWDG_CFR_W_1
+#define WWDG_CFR_W2 WWDG_CFR_W_2
+#define WWDG_CFR_W3 WWDG_CFR_W_3
+#define WWDG_CFR_W4 WWDG_CFR_W_4
+#define WWDG_CFR_W5 WWDG_CFR_W_5
+#define WWDG_CFR_W6 WWDG_CFR_W_6
+
+#define WWDG_CFR_WDGTB_Pos (7U)
+#define WWDG_CFR_WDGTB_Msk (0x3U << WWDG_CFR_WDGTB_Pos) /*!< 0x00000180 */
+#define WWDG_CFR_WDGTB WWDG_CFR_WDGTB_Msk /*!< WDGTB[1:0] bits (Timer Base) */
+#define WWDG_CFR_WDGTB_0 (0x1U << WWDG_CFR_WDGTB_Pos) /*!< 0x00000080 */
+#define WWDG_CFR_WDGTB_1 (0x2U << WWDG_CFR_WDGTB_Pos) /*!< 0x00000100 */
+
+/* Legacy defines */
+#define WWDG_CFR_WDGTB0 WWDG_CFR_WDGTB_0
+#define WWDG_CFR_WDGTB1 WWDG_CFR_WDGTB_1
+
+#define WWDG_CFR_EWI_Pos (9U)
+#define WWDG_CFR_EWI_Msk (0x1U << WWDG_CFR_EWI_Pos) /*!< 0x00000200 */
+#define WWDG_CFR_EWI WWDG_CFR_EWI_Msk /*!< Early Wakeup Interrupt */
+
+/******************* Bit definition for WWDG_SR register ********************/
+#define WWDG_SR_EWIF_Pos (0U)
+#define WWDG_SR_EWIF_Msk (0x1U << WWDG_SR_EWIF_Pos) /*!< 0x00000001 */
+#define WWDG_SR_EWIF WWDG_SR_EWIF_Msk /*!< Early Wakeup Interrupt Flag */
+
+
+/******************************************************************************/
+/* */
+/* SD host Interface */
+/* */
+/******************************************************************************/
+
+/****************** Bit definition for SDIO_POWER register ******************/
+#define SDIO_POWER_PWRCTRL_Pos (0U)
+#define SDIO_POWER_PWRCTRL_Msk (0x3U << SDIO_POWER_PWRCTRL_Pos) /*!< 0x00000003 */
+#define SDIO_POWER_PWRCTRL SDIO_POWER_PWRCTRL_Msk /*!< PWRCTRL[1:0] bits (Power supply control bits) */
+#define SDIO_POWER_PWRCTRL_0 (0x1U << SDIO_POWER_PWRCTRL_Pos) /*!< 0x01 */
+#define SDIO_POWER_PWRCTRL_1 (0x2U << SDIO_POWER_PWRCTRL_Pos) /*!< 0x02 */
+
+/****************** Bit definition for SDIO_CLKCR register ******************/
+#define SDIO_CLKCR_CLKDIV_Pos (0U)
+#define SDIO_CLKCR_CLKDIV_Msk (0xFFU << SDIO_CLKCR_CLKDIV_Pos) /*!< 0x000000FF */
+#define SDIO_CLKCR_CLKDIV SDIO_CLKCR_CLKDIV_Msk /*!< Clock divide factor */
+#define SDIO_CLKCR_CLKEN_Pos (8U)
+#define SDIO_CLKCR_CLKEN_Msk (0x1U << SDIO_CLKCR_CLKEN_Pos) /*!< 0x00000100 */
+#define SDIO_CLKCR_CLKEN SDIO_CLKCR_CLKEN_Msk /*!< Clock enable bit */
+#define SDIO_CLKCR_PWRSAV_Pos (9U)
+#define SDIO_CLKCR_PWRSAV_Msk (0x1U << SDIO_CLKCR_PWRSAV_Pos) /*!< 0x00000200 */
+#define SDIO_CLKCR_PWRSAV SDIO_CLKCR_PWRSAV_Msk /*!< Power saving configuration bit */
+#define SDIO_CLKCR_BYPASS_Pos (10U)
+#define SDIO_CLKCR_BYPASS_Msk (0x1U << SDIO_CLKCR_BYPASS_Pos) /*!< 0x00000400 */
+#define SDIO_CLKCR_BYPASS SDIO_CLKCR_BYPASS_Msk /*!< Clock divider bypass enable bit */
+
+#define SDIO_CLKCR_WIDBUS_Pos (11U)
+#define SDIO_CLKCR_WIDBUS_Msk (0x3U << SDIO_CLKCR_WIDBUS_Pos) /*!< 0x00001800 */
+#define SDIO_CLKCR_WIDBUS SDIO_CLKCR_WIDBUS_Msk /*!< WIDBUS[1:0] bits (Wide bus mode enable bit) */
+#define SDIO_CLKCR_WIDBUS_0 (0x1U << SDIO_CLKCR_WIDBUS_Pos) /*!< 0x0800 */
+#define SDIO_CLKCR_WIDBUS_1 (0x2U << SDIO_CLKCR_WIDBUS_Pos) /*!< 0x1000 */
+
+#define SDIO_CLKCR_NEGEDGE_Pos (13U)
+#define SDIO_CLKCR_NEGEDGE_Msk (0x1U << SDIO_CLKCR_NEGEDGE_Pos) /*!< 0x00002000 */
+#define SDIO_CLKCR_NEGEDGE SDIO_CLKCR_NEGEDGE_Msk /*!< SDIO_CK dephasing selection bit */
+#define SDIO_CLKCR_HWFC_EN_Pos (14U)
+#define SDIO_CLKCR_HWFC_EN_Msk (0x1U << SDIO_CLKCR_HWFC_EN_Pos) /*!< 0x00004000 */
+#define SDIO_CLKCR_HWFC_EN SDIO_CLKCR_HWFC_EN_Msk /*!< HW Flow Control enable */
+
+/******************* Bit definition for SDIO_ARG register *******************/
+#define SDIO_ARG_CMDARG_Pos (0U)
+#define SDIO_ARG_CMDARG_Msk (0xFFFFFFFFU << SDIO_ARG_CMDARG_Pos) /*!< 0xFFFFFFFF */
+#define SDIO_ARG_CMDARG SDIO_ARG_CMDARG_Msk /*!< Command argument */
+
+/******************* Bit definition for SDIO_CMD register *******************/
+#define SDIO_CMD_CMDINDEX_Pos (0U)
+#define SDIO_CMD_CMDINDEX_Msk (0x3FU << SDIO_CMD_CMDINDEX_Pos) /*!< 0x0000003F */
+#define SDIO_CMD_CMDINDEX SDIO_CMD_CMDINDEX_Msk /*!< Command Index */
+
+#define SDIO_CMD_WAITRESP_Pos (6U)
+#define SDIO_CMD_WAITRESP_Msk (0x3U << SDIO_CMD_WAITRESP_Pos) /*!< 0x000000C0 */
+#define SDIO_CMD_WAITRESP SDIO_CMD_WAITRESP_Msk /*!< WAITRESP[1:0] bits (Wait for response bits) */
+#define SDIO_CMD_WAITRESP_0 (0x1U << SDIO_CMD_WAITRESP_Pos) /*!< 0x0040 */
+#define SDIO_CMD_WAITRESP_1 (0x2U << SDIO_CMD_WAITRESP_Pos) /*!< 0x0080 */
+
+#define SDIO_CMD_WAITINT_Pos (8U)
+#define SDIO_CMD_WAITINT_Msk (0x1U << SDIO_CMD_WAITINT_Pos) /*!< 0x00000100 */
+#define SDIO_CMD_WAITINT SDIO_CMD_WAITINT_Msk /*!< CPSM Waits for Interrupt Request */
+#define SDIO_CMD_WAITPEND_Pos (9U)
+#define SDIO_CMD_WAITPEND_Msk (0x1U << SDIO_CMD_WAITPEND_Pos) /*!< 0x00000200 */
+#define SDIO_CMD_WAITPEND SDIO_CMD_WAITPEND_Msk /*!< CPSM Waits for ends of data transfer (CmdPend internal signal) */
+#define SDIO_CMD_CPSMEN_Pos (10U)
+#define SDIO_CMD_CPSMEN_Msk (0x1U << SDIO_CMD_CPSMEN_Pos) /*!< 0x00000400 */
+#define SDIO_CMD_CPSMEN SDIO_CMD_CPSMEN_Msk /*!< Command path state machine (CPSM) Enable bit */
+#define SDIO_CMD_SDIOSUSPEND_Pos (11U)
+#define SDIO_CMD_SDIOSUSPEND_Msk (0x1U << SDIO_CMD_SDIOSUSPEND_Pos) /*!< 0x00000800 */
+#define SDIO_CMD_SDIOSUSPEND SDIO_CMD_SDIOSUSPEND_Msk /*!< SD I/O suspend command */
+#define SDIO_CMD_ENCMDCOMPL_Pos (12U)
+#define SDIO_CMD_ENCMDCOMPL_Msk (0x1U << SDIO_CMD_ENCMDCOMPL_Pos) /*!< 0x00001000 */
+#define SDIO_CMD_ENCMDCOMPL SDIO_CMD_ENCMDCOMPL_Msk /*!< Enable CMD completion */
+#define SDIO_CMD_NIEN_Pos (13U)
+#define SDIO_CMD_NIEN_Msk (0x1U << SDIO_CMD_NIEN_Pos) /*!< 0x00002000 */
+#define SDIO_CMD_NIEN SDIO_CMD_NIEN_Msk /*!< Not Interrupt Enable */
+#define SDIO_CMD_CEATACMD_Pos (14U)
+#define SDIO_CMD_CEATACMD_Msk (0x1U << SDIO_CMD_CEATACMD_Pos) /*!< 0x00004000 */
+#define SDIO_CMD_CEATACMD SDIO_CMD_CEATACMD_Msk /*!< CE-ATA command */
+
+/***************** Bit definition for SDIO_RESPCMD register *****************/
+#define SDIO_RESPCMD_RESPCMD_Pos (0U)
+#define SDIO_RESPCMD_RESPCMD_Msk (0x3FU << SDIO_RESPCMD_RESPCMD_Pos) /*!< 0x0000003F */
+#define SDIO_RESPCMD_RESPCMD SDIO_RESPCMD_RESPCMD_Msk /*!< Response command index */
+
+/****************** Bit definition for SDIO_RESP0 register ******************/
+#define SDIO_RESP0_CARDSTATUS0_Pos (0U)
+#define SDIO_RESP0_CARDSTATUS0_Msk (0xFFFFFFFFU << SDIO_RESP0_CARDSTATUS0_Pos) /*!< 0xFFFFFFFF */
+#define SDIO_RESP0_CARDSTATUS0 SDIO_RESP0_CARDSTATUS0_Msk /*!< Card Status */
+
+/****************** Bit definition for SDIO_RESP1 register ******************/
+#define SDIO_RESP1_CARDSTATUS1_Pos (0U)
+#define SDIO_RESP1_CARDSTATUS1_Msk (0xFFFFFFFFU << SDIO_RESP1_CARDSTATUS1_Pos) /*!< 0xFFFFFFFF */
+#define SDIO_RESP1_CARDSTATUS1 SDIO_RESP1_CARDSTATUS1_Msk /*!< Card Status */
+
+/****************** Bit definition for SDIO_RESP2 register ******************/
+#define SDIO_RESP2_CARDSTATUS2_Pos (0U)
+#define SDIO_RESP2_CARDSTATUS2_Msk (0xFFFFFFFFU << SDIO_RESP2_CARDSTATUS2_Pos) /*!< 0xFFFFFFFF */
+#define SDIO_RESP2_CARDSTATUS2 SDIO_RESP2_CARDSTATUS2_Msk /*!< Card Status */
+
+/****************** Bit definition for SDIO_RESP3 register ******************/
+#define SDIO_RESP3_CARDSTATUS3_Pos (0U)
+#define SDIO_RESP3_CARDSTATUS3_Msk (0xFFFFFFFFU << SDIO_RESP3_CARDSTATUS3_Pos) /*!< 0xFFFFFFFF */
+#define SDIO_RESP3_CARDSTATUS3 SDIO_RESP3_CARDSTATUS3_Msk /*!< Card Status */
+
+/****************** Bit definition for SDIO_RESP4 register ******************/
+#define SDIO_RESP4_CARDSTATUS4_Pos (0U)
+#define SDIO_RESP4_CARDSTATUS4_Msk (0xFFFFFFFFU << SDIO_RESP4_CARDSTATUS4_Pos) /*!< 0xFFFFFFFF */
+#define SDIO_RESP4_CARDSTATUS4 SDIO_RESP4_CARDSTATUS4_Msk /*!< Card Status */
+
+/****************** Bit definition for SDIO_DTIMER register *****************/
+#define SDIO_DTIMER_DATATIME_Pos (0U)
+#define SDIO_DTIMER_DATATIME_Msk (0xFFFFFFFFU << SDIO_DTIMER_DATATIME_Pos) /*!< 0xFFFFFFFF */
+#define SDIO_DTIMER_DATATIME SDIO_DTIMER_DATATIME_Msk /*!< Data timeout period. */
+
+/****************** Bit definition for SDIO_DLEN register *******************/
+#define SDIO_DLEN_DATALENGTH_Pos (0U)
+#define SDIO_DLEN_DATALENGTH_Msk (0x1FFFFFFU << SDIO_DLEN_DATALENGTH_Pos) /*!< 0x01FFFFFF */
+#define SDIO_DLEN_DATALENGTH SDIO_DLEN_DATALENGTH_Msk /*!< Data length value */
+
+/****************** Bit definition for SDIO_DCTRL register ******************/
+#define SDIO_DCTRL_DTEN_Pos (0U)
+#define SDIO_DCTRL_DTEN_Msk (0x1U << SDIO_DCTRL_DTEN_Pos) /*!< 0x00000001 */
+#define SDIO_DCTRL_DTEN SDIO_DCTRL_DTEN_Msk /*!< Data transfer enabled bit */
+#define SDIO_DCTRL_DTDIR_Pos (1U)
+#define SDIO_DCTRL_DTDIR_Msk (0x1U << SDIO_DCTRL_DTDIR_Pos) /*!< 0x00000002 */
+#define SDIO_DCTRL_DTDIR SDIO_DCTRL_DTDIR_Msk /*!< Data transfer direction selection */
+#define SDIO_DCTRL_DTMODE_Pos (2U)
+#define SDIO_DCTRL_DTMODE_Msk (0x1U << SDIO_DCTRL_DTMODE_Pos) /*!< 0x00000004 */
+#define SDIO_DCTRL_DTMODE SDIO_DCTRL_DTMODE_Msk /*!< Data transfer mode selection */
+#define SDIO_DCTRL_DMAEN_Pos (3U)
+#define SDIO_DCTRL_DMAEN_Msk (0x1U << SDIO_DCTRL_DMAEN_Pos) /*!< 0x00000008 */
+#define SDIO_DCTRL_DMAEN SDIO_DCTRL_DMAEN_Msk /*!< DMA enabled bit */
+
+#define SDIO_DCTRL_DBLOCKSIZE_Pos (4U)
+#define SDIO_DCTRL_DBLOCKSIZE_Msk (0xFU << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x000000F0 */
+#define SDIO_DCTRL_DBLOCKSIZE SDIO_DCTRL_DBLOCKSIZE_Msk /*!< DBLOCKSIZE[3:0] bits (Data block size) */
+#define SDIO_DCTRL_DBLOCKSIZE_0 (0x1U << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0010 */
+#define SDIO_DCTRL_DBLOCKSIZE_1 (0x2U << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0020 */
+#define SDIO_DCTRL_DBLOCKSIZE_2 (0x4U << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0040 */
+#define SDIO_DCTRL_DBLOCKSIZE_3 (0x8U << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0080 */
+
+#define SDIO_DCTRL_RWSTART_Pos (8U)
+#define SDIO_DCTRL_RWSTART_Msk (0x1U << SDIO_DCTRL_RWSTART_Pos) /*!< 0x00000100 */
+#define SDIO_DCTRL_RWSTART SDIO_DCTRL_RWSTART_Msk /*!< Read wait start */
+#define SDIO_DCTRL_RWSTOP_Pos (9U)
+#define SDIO_DCTRL_RWSTOP_Msk (0x1U << SDIO_DCTRL_RWSTOP_Pos) /*!< 0x00000200 */
+#define SDIO_DCTRL_RWSTOP SDIO_DCTRL_RWSTOP_Msk /*!< Read wait stop */
+#define SDIO_DCTRL_RWMOD_Pos (10U)
+#define SDIO_DCTRL_RWMOD_Msk (0x1U << SDIO_DCTRL_RWMOD_Pos) /*!< 0x00000400 */
+#define SDIO_DCTRL_RWMOD SDIO_DCTRL_RWMOD_Msk /*!< Read wait mode */
+#define SDIO_DCTRL_SDIOEN_Pos (11U)
+#define SDIO_DCTRL_SDIOEN_Msk (0x1U << SDIO_DCTRL_SDIOEN_Pos) /*!< 0x00000800 */
+#define SDIO_DCTRL_SDIOEN SDIO_DCTRL_SDIOEN_Msk /*!< SD I/O enable functions */
+
+/****************** Bit definition for SDIO_DCOUNT register *****************/
+#define SDIO_DCOUNT_DATACOUNT_Pos (0U)
+#define SDIO_DCOUNT_DATACOUNT_Msk (0x1FFFFFFU << SDIO_DCOUNT_DATACOUNT_Pos) /*!< 0x01FFFFFF */
+#define SDIO_DCOUNT_DATACOUNT SDIO_DCOUNT_DATACOUNT_Msk /*!< Data count value */
+
+/****************** Bit definition for SDIO_STA register ********************/
+#define SDIO_STA_CCRCFAIL_Pos (0U)
+#define SDIO_STA_CCRCFAIL_Msk (0x1U << SDIO_STA_CCRCFAIL_Pos) /*!< 0x00000001 */
+#define SDIO_STA_CCRCFAIL SDIO_STA_CCRCFAIL_Msk /*!< Command response received (CRC check failed) */
+#define SDIO_STA_DCRCFAIL_Pos (1U)
+#define SDIO_STA_DCRCFAIL_Msk (0x1U << SDIO_STA_DCRCFAIL_Pos) /*!< 0x00000002 */
+#define SDIO_STA_DCRCFAIL SDIO_STA_DCRCFAIL_Msk /*!< Data block sent/received (CRC check failed) */
+#define SDIO_STA_CTIMEOUT_Pos (2U)
+#define SDIO_STA_CTIMEOUT_Msk (0x1U << SDIO_STA_CTIMEOUT_Pos) /*!< 0x00000004 */
+#define SDIO_STA_CTIMEOUT SDIO_STA_CTIMEOUT_Msk /*!< Command response timeout */
+#define SDIO_STA_DTIMEOUT_Pos (3U)
+#define SDIO_STA_DTIMEOUT_Msk (0x1U << SDIO_STA_DTIMEOUT_Pos) /*!< 0x00000008 */
+#define SDIO_STA_DTIMEOUT SDIO_STA_DTIMEOUT_Msk /*!< Data timeout */
+#define SDIO_STA_TXUNDERR_Pos (4U)
+#define SDIO_STA_TXUNDERR_Msk (0x1U << SDIO_STA_TXUNDERR_Pos) /*!< 0x00000010 */
+#define SDIO_STA_TXUNDERR SDIO_STA_TXUNDERR_Msk /*!< Transmit FIFO underrun error */
+#define SDIO_STA_RXOVERR_Pos (5U)
+#define SDIO_STA_RXOVERR_Msk (0x1U << SDIO_STA_RXOVERR_Pos) /*!< 0x00000020 */
+#define SDIO_STA_RXOVERR SDIO_STA_RXOVERR_Msk /*!< Received FIFO overrun error */
+#define SDIO_STA_CMDREND_Pos (6U)
+#define SDIO_STA_CMDREND_Msk (0x1U << SDIO_STA_CMDREND_Pos) /*!< 0x00000040 */
+#define SDIO_STA_CMDREND SDIO_STA_CMDREND_Msk /*!< Command response received (CRC check passed) */
+#define SDIO_STA_CMDSENT_Pos (7U)
+#define SDIO_STA_CMDSENT_Msk (0x1U << SDIO_STA_CMDSENT_Pos) /*!< 0x00000080 */
+#define SDIO_STA_CMDSENT SDIO_STA_CMDSENT_Msk /*!< Command sent (no response required) */
+#define SDIO_STA_DATAEND_Pos (8U)
+#define SDIO_STA_DATAEND_Msk (0x1U << SDIO_STA_DATAEND_Pos) /*!< 0x00000100 */
+#define SDIO_STA_DATAEND SDIO_STA_DATAEND_Msk /*!< Data end (data counter, SDIDCOUNT, is zero) */
+#define SDIO_STA_STBITERR_Pos (9U)
+#define SDIO_STA_STBITERR_Msk (0x1U << SDIO_STA_STBITERR_Pos) /*!< 0x00000200 */
+#define SDIO_STA_STBITERR SDIO_STA_STBITERR_Msk /*!< Start bit not detected on all data signals in wide bus mode */
+#define SDIO_STA_DBCKEND_Pos (10U)
+#define SDIO_STA_DBCKEND_Msk (0x1U << SDIO_STA_DBCKEND_Pos) /*!< 0x00000400 */
+#define SDIO_STA_DBCKEND SDIO_STA_DBCKEND_Msk /*!< Data block sent/received (CRC check passed) */
+#define SDIO_STA_CMDACT_Pos (11U)
+#define SDIO_STA_CMDACT_Msk (0x1U << SDIO_STA_CMDACT_Pos) /*!< 0x00000800 */
+#define SDIO_STA_CMDACT SDIO_STA_CMDACT_Msk /*!< Command transfer in progress */
+#define SDIO_STA_TXACT_Pos (12U)
+#define SDIO_STA_TXACT_Msk (0x1U << SDIO_STA_TXACT_Pos) /*!< 0x00001000 */
+#define SDIO_STA_TXACT SDIO_STA_TXACT_Msk /*!< Data transmit in progress */
+#define SDIO_STA_RXACT_Pos (13U)
+#define SDIO_STA_RXACT_Msk (0x1U << SDIO_STA_RXACT_Pos) /*!< 0x00002000 */
+#define SDIO_STA_RXACT SDIO_STA_RXACT_Msk /*!< Data receive in progress */
+#define SDIO_STA_TXFIFOHE_Pos (14U)
+#define SDIO_STA_TXFIFOHE_Msk (0x1U << SDIO_STA_TXFIFOHE_Pos) /*!< 0x00004000 */
+#define SDIO_STA_TXFIFOHE SDIO_STA_TXFIFOHE_Msk /*!< Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
+#define SDIO_STA_RXFIFOHF_Pos (15U)
+#define SDIO_STA_RXFIFOHF_Msk (0x1U << SDIO_STA_RXFIFOHF_Pos) /*!< 0x00008000 */
+#define SDIO_STA_RXFIFOHF SDIO_STA_RXFIFOHF_Msk /*!< Receive FIFO Half Full: there are at least 8 words in the FIFO */
+#define SDIO_STA_TXFIFOF_Pos (16U)
+#define SDIO_STA_TXFIFOF_Msk (0x1U << SDIO_STA_TXFIFOF_Pos) /*!< 0x00010000 */
+#define SDIO_STA_TXFIFOF SDIO_STA_TXFIFOF_Msk /*!< Transmit FIFO full */
+#define SDIO_STA_RXFIFOF_Pos (17U)
+#define SDIO_STA_RXFIFOF_Msk (0x1U << SDIO_STA_RXFIFOF_Pos) /*!< 0x00020000 */
+#define SDIO_STA_RXFIFOF SDIO_STA_RXFIFOF_Msk /*!< Receive FIFO full */
+#define SDIO_STA_TXFIFOE_Pos (18U)
+#define SDIO_STA_TXFIFOE_Msk (0x1U << SDIO_STA_TXFIFOE_Pos) /*!< 0x00040000 */
+#define SDIO_STA_TXFIFOE SDIO_STA_TXFIFOE_Msk /*!< Transmit FIFO empty */
+#define SDIO_STA_RXFIFOE_Pos (19U)
+#define SDIO_STA_RXFIFOE_Msk (0x1U << SDIO_STA_RXFIFOE_Pos) /*!< 0x00080000 */
+#define SDIO_STA_RXFIFOE SDIO_STA_RXFIFOE_Msk /*!< Receive FIFO empty */
+#define SDIO_STA_TXDAVL_Pos (20U)
+#define SDIO_STA_TXDAVL_Msk (0x1U << SDIO_STA_TXDAVL_Pos) /*!< 0x00100000 */
+#define SDIO_STA_TXDAVL SDIO_STA_TXDAVL_Msk /*!< Data available in transmit FIFO */
+#define SDIO_STA_RXDAVL_Pos (21U)
+#define SDIO_STA_RXDAVL_Msk (0x1U << SDIO_STA_RXDAVL_Pos) /*!< 0x00200000 */
+#define SDIO_STA_RXDAVL SDIO_STA_RXDAVL_Msk /*!< Data available in receive FIFO */
+#define SDIO_STA_SDIOIT_Pos (22U)
+#define SDIO_STA_SDIOIT_Msk (0x1U << SDIO_STA_SDIOIT_Pos) /*!< 0x00400000 */
+#define SDIO_STA_SDIOIT SDIO_STA_SDIOIT_Msk /*!< SDIO interrupt received */
+#define SDIO_STA_CEATAEND_Pos (23U)
+#define SDIO_STA_CEATAEND_Msk (0x1U << SDIO_STA_CEATAEND_Pos) /*!< 0x00800000 */
+#define SDIO_STA_CEATAEND SDIO_STA_CEATAEND_Msk /*!< CE-ATA command completion signal received for CMD61 */
+
+/******************* Bit definition for SDIO_ICR register *******************/
+#define SDIO_ICR_CCRCFAILC_Pos (0U)
+#define SDIO_ICR_CCRCFAILC_Msk (0x1U << SDIO_ICR_CCRCFAILC_Pos) /*!< 0x00000001 */
+#define SDIO_ICR_CCRCFAILC SDIO_ICR_CCRCFAILC_Msk /*!< CCRCFAIL flag clear bit */
+#define SDIO_ICR_DCRCFAILC_Pos (1U)
+#define SDIO_ICR_DCRCFAILC_Msk (0x1U << SDIO_ICR_DCRCFAILC_Pos) /*!< 0x00000002 */
+#define SDIO_ICR_DCRCFAILC SDIO_ICR_DCRCFAILC_Msk /*!< DCRCFAIL flag clear bit */
+#define SDIO_ICR_CTIMEOUTC_Pos (2U)
+#define SDIO_ICR_CTIMEOUTC_Msk (0x1U << SDIO_ICR_CTIMEOUTC_Pos) /*!< 0x00000004 */
+#define SDIO_ICR_CTIMEOUTC SDIO_ICR_CTIMEOUTC_Msk /*!< CTIMEOUT flag clear bit */
+#define SDIO_ICR_DTIMEOUTC_Pos (3U)
+#define SDIO_ICR_DTIMEOUTC_Msk (0x1U << SDIO_ICR_DTIMEOUTC_Pos) /*!< 0x00000008 */
+#define SDIO_ICR_DTIMEOUTC SDIO_ICR_DTIMEOUTC_Msk /*!< DTIMEOUT flag clear bit */
+#define SDIO_ICR_TXUNDERRC_Pos (4U)
+#define SDIO_ICR_TXUNDERRC_Msk (0x1U << SDIO_ICR_TXUNDERRC_Pos) /*!< 0x00000010 */
+#define SDIO_ICR_TXUNDERRC SDIO_ICR_TXUNDERRC_Msk /*!< TXUNDERR flag clear bit */
+#define SDIO_ICR_RXOVERRC_Pos (5U)
+#define SDIO_ICR_RXOVERRC_Msk (0x1U << SDIO_ICR_RXOVERRC_Pos) /*!< 0x00000020 */
+#define SDIO_ICR_RXOVERRC SDIO_ICR_RXOVERRC_Msk /*!< RXOVERR flag clear bit */
+#define SDIO_ICR_CMDRENDC_Pos (6U)
+#define SDIO_ICR_CMDRENDC_Msk (0x1U << SDIO_ICR_CMDRENDC_Pos) /*!< 0x00000040 */
+#define SDIO_ICR_CMDRENDC SDIO_ICR_CMDRENDC_Msk /*!< CMDREND flag clear bit */
+#define SDIO_ICR_CMDSENTC_Pos (7U)
+#define SDIO_ICR_CMDSENTC_Msk (0x1U << SDIO_ICR_CMDSENTC_Pos) /*!< 0x00000080 */
+#define SDIO_ICR_CMDSENTC SDIO_ICR_CMDSENTC_Msk /*!< CMDSENT flag clear bit */
+#define SDIO_ICR_DATAENDC_Pos (8U)
+#define SDIO_ICR_DATAENDC_Msk (0x1U << SDIO_ICR_DATAENDC_Pos) /*!< 0x00000100 */
+#define SDIO_ICR_DATAENDC SDIO_ICR_DATAENDC_Msk /*!< DATAEND flag clear bit */
+#define SDIO_ICR_STBITERRC_Pos (9U)
+#define SDIO_ICR_STBITERRC_Msk (0x1U << SDIO_ICR_STBITERRC_Pos) /*!< 0x00000200 */
+#define SDIO_ICR_STBITERRC SDIO_ICR_STBITERRC_Msk /*!< STBITERR flag clear bit */
+#define SDIO_ICR_DBCKENDC_Pos (10U)
+#define SDIO_ICR_DBCKENDC_Msk (0x1U << SDIO_ICR_DBCKENDC_Pos) /*!< 0x00000400 */
+#define SDIO_ICR_DBCKENDC SDIO_ICR_DBCKENDC_Msk /*!< DBCKEND flag clear bit */
+#define SDIO_ICR_SDIOITC_Pos (22U)
+#define SDIO_ICR_SDIOITC_Msk (0x1U << SDIO_ICR_SDIOITC_Pos) /*!< 0x00400000 */
+#define SDIO_ICR_SDIOITC SDIO_ICR_SDIOITC_Msk /*!< SDIOIT flag clear bit */
+#define SDIO_ICR_CEATAENDC_Pos (23U)
+#define SDIO_ICR_CEATAENDC_Msk (0x1U << SDIO_ICR_CEATAENDC_Pos) /*!< 0x00800000 */
+#define SDIO_ICR_CEATAENDC SDIO_ICR_CEATAENDC_Msk /*!< CEATAEND flag clear bit */
+
+/****************** Bit definition for SDIO_MASK register *******************/
+#define SDIO_MASK_CCRCFAILIE_Pos (0U)
+#define SDIO_MASK_CCRCFAILIE_Msk (0x1U << SDIO_MASK_CCRCFAILIE_Pos) /*!< 0x00000001 */
+#define SDIO_MASK_CCRCFAILIE SDIO_MASK_CCRCFAILIE_Msk /*!< Command CRC Fail Interrupt Enable */
+#define SDIO_MASK_DCRCFAILIE_Pos (1U)
+#define SDIO_MASK_DCRCFAILIE_Msk (0x1U << SDIO_MASK_DCRCFAILIE_Pos) /*!< 0x00000002 */
+#define SDIO_MASK_DCRCFAILIE SDIO_MASK_DCRCFAILIE_Msk /*!< Data CRC Fail Interrupt Enable */
+#define SDIO_MASK_CTIMEOUTIE_Pos (2U)
+#define SDIO_MASK_CTIMEOUTIE_Msk (0x1U << SDIO_MASK_CTIMEOUTIE_Pos) /*!< 0x00000004 */
+#define SDIO_MASK_CTIMEOUTIE SDIO_MASK_CTIMEOUTIE_Msk /*!< Command TimeOut Interrupt Enable */
+#define SDIO_MASK_DTIMEOUTIE_Pos (3U)
+#define SDIO_MASK_DTIMEOUTIE_Msk (0x1U << SDIO_MASK_DTIMEOUTIE_Pos) /*!< 0x00000008 */
+#define SDIO_MASK_DTIMEOUTIE SDIO_MASK_DTIMEOUTIE_Msk /*!< Data TimeOut Interrupt Enable */
+#define SDIO_MASK_TXUNDERRIE_Pos (4U)
+#define SDIO_MASK_TXUNDERRIE_Msk (0x1U << SDIO_MASK_TXUNDERRIE_Pos) /*!< 0x00000010 */
+#define SDIO_MASK_TXUNDERRIE SDIO_MASK_TXUNDERRIE_Msk /*!< Tx FIFO UnderRun Error Interrupt Enable */
+#define SDIO_MASK_RXOVERRIE_Pos (5U)
+#define SDIO_MASK_RXOVERRIE_Msk (0x1U << SDIO_MASK_RXOVERRIE_Pos) /*!< 0x00000020 */
+#define SDIO_MASK_RXOVERRIE SDIO_MASK_RXOVERRIE_Msk /*!< Rx FIFO OverRun Error Interrupt Enable */
+#define SDIO_MASK_CMDRENDIE_Pos (6U)
+#define SDIO_MASK_CMDRENDIE_Msk (0x1U << SDIO_MASK_CMDRENDIE_Pos) /*!< 0x00000040 */
+#define SDIO_MASK_CMDRENDIE SDIO_MASK_CMDRENDIE_Msk /*!< Command Response Received Interrupt Enable */
+#define SDIO_MASK_CMDSENTIE_Pos (7U)
+#define SDIO_MASK_CMDSENTIE_Msk (0x1U << SDIO_MASK_CMDSENTIE_Pos) /*!< 0x00000080 */
+#define SDIO_MASK_CMDSENTIE SDIO_MASK_CMDSENTIE_Msk /*!< Command Sent Interrupt Enable */
+#define SDIO_MASK_DATAENDIE_Pos (8U)
+#define SDIO_MASK_DATAENDIE_Msk (0x1U << SDIO_MASK_DATAENDIE_Pos) /*!< 0x00000100 */
+#define SDIO_MASK_DATAENDIE SDIO_MASK_DATAENDIE_Msk /*!< Data End Interrupt Enable */
+#define SDIO_MASK_STBITERRIE_Pos (9U)
+#define SDIO_MASK_STBITERRIE_Msk (0x1U << SDIO_MASK_STBITERRIE_Pos) /*!< 0x00000200 */
+#define SDIO_MASK_STBITERRIE SDIO_MASK_STBITERRIE_Msk /*!< Start Bit Error Interrupt Enable */
+#define SDIO_MASK_DBCKENDIE_Pos (10U)
+#define SDIO_MASK_DBCKENDIE_Msk (0x1U << SDIO_MASK_DBCKENDIE_Pos) /*!< 0x00000400 */
+#define SDIO_MASK_DBCKENDIE SDIO_MASK_DBCKENDIE_Msk /*!< Data Block End Interrupt Enable */
+#define SDIO_MASK_CMDACTIE_Pos (11U)
+#define SDIO_MASK_CMDACTIE_Msk (0x1U << SDIO_MASK_CMDACTIE_Pos) /*!< 0x00000800 */
+#define SDIO_MASK_CMDACTIE SDIO_MASK_CMDACTIE_Msk /*!< Command Acting Interrupt Enable */
+#define SDIO_MASK_TXACTIE_Pos (12U)
+#define SDIO_MASK_TXACTIE_Msk (0x1U << SDIO_MASK_TXACTIE_Pos) /*!< 0x00001000 */
+#define SDIO_MASK_TXACTIE SDIO_MASK_TXACTIE_Msk /*!< Data Transmit Acting Interrupt Enable */
+#define SDIO_MASK_RXACTIE_Pos (13U)
+#define SDIO_MASK_RXACTIE_Msk (0x1U << SDIO_MASK_RXACTIE_Pos) /*!< 0x00002000 */
+#define SDIO_MASK_RXACTIE SDIO_MASK_RXACTIE_Msk /*!< Data receive acting interrupt enabled */
+#define SDIO_MASK_TXFIFOHEIE_Pos (14U)
+#define SDIO_MASK_TXFIFOHEIE_Msk (0x1U << SDIO_MASK_TXFIFOHEIE_Pos) /*!< 0x00004000 */
+#define SDIO_MASK_TXFIFOHEIE SDIO_MASK_TXFIFOHEIE_Msk /*!< Tx FIFO Half Empty interrupt Enable */
+#define SDIO_MASK_RXFIFOHFIE_Pos (15U)
+#define SDIO_MASK_RXFIFOHFIE_Msk (0x1U << SDIO_MASK_RXFIFOHFIE_Pos) /*!< 0x00008000 */
+#define SDIO_MASK_RXFIFOHFIE SDIO_MASK_RXFIFOHFIE_Msk /*!< Rx FIFO Half Full interrupt Enable */
+#define SDIO_MASK_TXFIFOFIE_Pos (16U)
+#define SDIO_MASK_TXFIFOFIE_Msk (0x1U << SDIO_MASK_TXFIFOFIE_Pos) /*!< 0x00010000 */
+#define SDIO_MASK_TXFIFOFIE SDIO_MASK_TXFIFOFIE_Msk /*!< Tx FIFO Full interrupt Enable */
+#define SDIO_MASK_RXFIFOFIE_Pos (17U)
+#define SDIO_MASK_RXFIFOFIE_Msk (0x1U << SDIO_MASK_RXFIFOFIE_Pos) /*!< 0x00020000 */
+#define SDIO_MASK_RXFIFOFIE SDIO_MASK_RXFIFOFIE_Msk /*!< Rx FIFO Full interrupt Enable */
+#define SDIO_MASK_TXFIFOEIE_Pos (18U)
+#define SDIO_MASK_TXFIFOEIE_Msk (0x1U << SDIO_MASK_TXFIFOEIE_Pos) /*!< 0x00040000 */
+#define SDIO_MASK_TXFIFOEIE SDIO_MASK_TXFIFOEIE_Msk /*!< Tx FIFO Empty interrupt Enable */
+#define SDIO_MASK_RXFIFOEIE_Pos (19U)
+#define SDIO_MASK_RXFIFOEIE_Msk (0x1U << SDIO_MASK_RXFIFOEIE_Pos) /*!< 0x00080000 */
+#define SDIO_MASK_RXFIFOEIE SDIO_MASK_RXFIFOEIE_Msk /*!< Rx FIFO Empty interrupt Enable */
+#define SDIO_MASK_TXDAVLIE_Pos (20U)
+#define SDIO_MASK_TXDAVLIE_Msk (0x1U << SDIO_MASK_TXDAVLIE_Pos) /*!< 0x00100000 */
+#define SDIO_MASK_TXDAVLIE SDIO_MASK_TXDAVLIE_Msk /*!< Data available in Tx FIFO interrupt Enable */
+#define SDIO_MASK_RXDAVLIE_Pos (21U)
+#define SDIO_MASK_RXDAVLIE_Msk (0x1U << SDIO_MASK_RXDAVLIE_Pos) /*!< 0x00200000 */
+#define SDIO_MASK_RXDAVLIE SDIO_MASK_RXDAVLIE_Msk /*!< Data available in Rx FIFO interrupt Enable */
+#define SDIO_MASK_SDIOITIE_Pos (22U)
+#define SDIO_MASK_SDIOITIE_Msk (0x1U << SDIO_MASK_SDIOITIE_Pos) /*!< 0x00400000 */
+#define SDIO_MASK_SDIOITIE SDIO_MASK_SDIOITIE_Msk /*!< SDIO Mode Interrupt Received interrupt Enable */
+#define SDIO_MASK_CEATAENDIE_Pos (23U)
+#define SDIO_MASK_CEATAENDIE_Msk (0x1U << SDIO_MASK_CEATAENDIE_Pos) /*!< 0x00800000 */
+#define SDIO_MASK_CEATAENDIE SDIO_MASK_CEATAENDIE_Msk /*!< CE-ATA command completion signal received Interrupt Enable */
+
+/***************** Bit definition for SDIO_FIFOCNT register *****************/
+#define SDIO_FIFOCNT_FIFOCOUNT_Pos (0U)
+#define SDIO_FIFOCNT_FIFOCOUNT_Msk (0xFFFFFFU << SDIO_FIFOCNT_FIFOCOUNT_Pos) /*!< 0x00FFFFFF */
+#define SDIO_FIFOCNT_FIFOCOUNT SDIO_FIFOCNT_FIFOCOUNT_Msk /*!< Remaining number of words to be written to or read from the FIFO */
+
+/****************** Bit definition for SDIO_FIFO register *******************/
+#define SDIO_FIFO_FIFODATA_Pos (0U)
+#define SDIO_FIFO_FIFODATA_Msk (0xFFFFFFFFU << SDIO_FIFO_FIFODATA_Pos) /*!< 0xFFFFFFFF */
+#define SDIO_FIFO_FIFODATA SDIO_FIFO_FIFODATA_Msk /*!< Receive and transmit FIFO data */
+
+/******************************************************************************/
+/* */
+/* USB Device FS */
+/* */
+/******************************************************************************/
+
+/*!< Endpoint-specific registers */
+#define USB_EP0R USB_BASE /*!< Endpoint 0 register address */
+#define USB_EP1R (USB_BASE + 0x00000004) /*!< Endpoint 1 register address */
+#define USB_EP2R (USB_BASE + 0x00000008) /*!< Endpoint 2 register address */
+#define USB_EP3R (USB_BASE + 0x0000000C) /*!< Endpoint 3 register address */
+#define USB_EP4R (USB_BASE + 0x00000010) /*!< Endpoint 4 register address */
+#define USB_EP5R (USB_BASE + 0x00000014) /*!< Endpoint 5 register address */
+#define USB_EP6R (USB_BASE + 0x00000018) /*!< Endpoint 6 register address */
+#define USB_EP7R (USB_BASE + 0x0000001C) /*!< Endpoint 7 register address */
+
+/* bit positions */
+#define USB_EP_CTR_RX_Pos (15U)
+#define USB_EP_CTR_RX_Msk (0x1U << USB_EP_CTR_RX_Pos) /*!< 0x00008000 */
+#define USB_EP_CTR_RX USB_EP_CTR_RX_Msk /*!< EndPoint Correct TRansfer RX */
+#define USB_EP_DTOG_RX_Pos (14U)
+#define USB_EP_DTOG_RX_Msk (0x1U << USB_EP_DTOG_RX_Pos) /*!< 0x00004000 */
+#define USB_EP_DTOG_RX USB_EP_DTOG_RX_Msk /*!< EndPoint Data TOGGLE RX */
+#define USB_EPRX_STAT_Pos (12U)
+#define USB_EPRX_STAT_Msk (0x3U << USB_EPRX_STAT_Pos) /*!< 0x00003000 */
+#define USB_EPRX_STAT USB_EPRX_STAT_Msk /*!< EndPoint RX STATus bit field */
+#define USB_EP_SETUP_Pos (11U)
+#define USB_EP_SETUP_Msk (0x1U << USB_EP_SETUP_Pos) /*!< 0x00000800 */
+#define USB_EP_SETUP USB_EP_SETUP_Msk /*!< EndPoint SETUP */
+#define USB_EP_T_FIELD_Pos (9U)
+#define USB_EP_T_FIELD_Msk (0x3U << USB_EP_T_FIELD_Pos) /*!< 0x00000600 */
+#define USB_EP_T_FIELD USB_EP_T_FIELD_Msk /*!< EndPoint TYPE */
+#define USB_EP_KIND_Pos (8U)
+#define USB_EP_KIND_Msk (0x1U << USB_EP_KIND_Pos) /*!< 0x00000100 */
+#define USB_EP_KIND USB_EP_KIND_Msk /*!< EndPoint KIND */
+#define USB_EP_CTR_TX_Pos (7U)
+#define USB_EP_CTR_TX_Msk (0x1U << USB_EP_CTR_TX_Pos) /*!< 0x00000080 */
+#define USB_EP_CTR_TX USB_EP_CTR_TX_Msk /*!< EndPoint Correct TRansfer TX */
+#define USB_EP_DTOG_TX_Pos (6U)
+#define USB_EP_DTOG_TX_Msk (0x1U << USB_EP_DTOG_TX_Pos) /*!< 0x00000040 */
+#define USB_EP_DTOG_TX USB_EP_DTOG_TX_Msk /*!< EndPoint Data TOGGLE TX */
+#define USB_EPTX_STAT_Pos (4U)
+#define USB_EPTX_STAT_Msk (0x3U << USB_EPTX_STAT_Pos) /*!< 0x00000030 */
+#define USB_EPTX_STAT USB_EPTX_STAT_Msk /*!< EndPoint TX STATus bit field */
+#define USB_EPADDR_FIELD_Pos (0U)
+#define USB_EPADDR_FIELD_Msk (0xFU << USB_EPADDR_FIELD_Pos) /*!< 0x0000000F */
+#define USB_EPADDR_FIELD USB_EPADDR_FIELD_Msk /*!< EndPoint ADDRess FIELD */
+
+/* EndPoint REGister MASK (no toggle fields) */
+#define USB_EPREG_MASK (USB_EP_CTR_RX|USB_EP_SETUP|USB_EP_T_FIELD|USB_EP_KIND|USB_EP_CTR_TX|USB_EPADDR_FIELD)
+ /*!< EP_TYPE[1:0] EndPoint TYPE */
+#define USB_EP_TYPE_MASK_Pos (9U)
+#define USB_EP_TYPE_MASK_Msk (0x3U << USB_EP_TYPE_MASK_Pos) /*!< 0x00000600 */
+#define USB_EP_TYPE_MASK USB_EP_TYPE_MASK_Msk /*!< EndPoint TYPE Mask */
+#define USB_EP_BULK ((uint32_t)0x00000000) /*!< EndPoint BULK */
+#define USB_EP_CONTROL ((uint32_t)0x00000200) /*!< EndPoint CONTROL */
+#define USB_EP_ISOCHRONOUS ((uint32_t)0x00000400) /*!< EndPoint ISOCHRONOUS */
+#define USB_EP_INTERRUPT ((uint32_t)0x00000600) /*!< EndPoint INTERRUPT */
+#define USB_EP_T_MASK (~USB_EP_T_FIELD & USB_EPREG_MASK)
+
+#define USB_EPKIND_MASK (~USB_EP_KIND & USB_EPREG_MASK) /*!< EP_KIND EndPoint KIND */
+ /*!< STAT_TX[1:0] STATus for TX transfer */
+#define USB_EP_TX_DIS ((uint32_t)0x00000000) /*!< EndPoint TX DISabled */
+#define USB_EP_TX_STALL ((uint32_t)0x00000010) /*!< EndPoint TX STALLed */
+#define USB_EP_TX_NAK ((uint32_t)0x00000020) /*!< EndPoint TX NAKed */
+#define USB_EP_TX_VALID ((uint32_t)0x00000030) /*!< EndPoint TX VALID */
+#define USB_EPTX_DTOG1 ((uint32_t)0x00000010) /*!< EndPoint TX Data TOGgle bit1 */
+#define USB_EPTX_DTOG2 ((uint32_t)0x00000020) /*!< EndPoint TX Data TOGgle bit2 */
+#define USB_EPTX_DTOGMASK (USB_EPTX_STAT|USB_EPREG_MASK)
+ /*!< STAT_RX[1:0] STATus for RX transfer */
+#define USB_EP_RX_DIS ((uint32_t)0x00000000) /*!< EndPoint RX DISabled */
+#define USB_EP_RX_STALL ((uint32_t)0x00001000) /*!< EndPoint RX STALLed */
+#define USB_EP_RX_NAK ((uint32_t)0x00002000) /*!< EndPoint RX NAKed */
+#define USB_EP_RX_VALID ((uint32_t)0x00003000) /*!< EndPoint RX VALID */
+#define USB_EPRX_DTOG1 ((uint32_t)0x00001000) /*!< EndPoint RX Data TOGgle bit1 */
+#define USB_EPRX_DTOG2 ((uint32_t)0x00002000) /*!< EndPoint RX Data TOGgle bit1 */
+#define USB_EPRX_DTOGMASK (USB_EPRX_STAT|USB_EPREG_MASK)
+
+/******************* Bit definition for USB_EP0R register *******************/
+#define USB_EP0R_EA_Pos (0U)
+#define USB_EP0R_EA_Msk (0xFU << USB_EP0R_EA_Pos) /*!< 0x0000000F */
+#define USB_EP0R_EA USB_EP0R_EA_Msk /*!< Endpoint Address */
+
+#define USB_EP0R_STAT_TX_Pos (4U)
+#define USB_EP0R_STAT_TX_Msk (0x3U << USB_EP0R_STAT_TX_Pos) /*!< 0x00000030 */
+#define USB_EP0R_STAT_TX USB_EP0R_STAT_TX_Msk /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */
+#define USB_EP0R_STAT_TX_0 (0x1U << USB_EP0R_STAT_TX_Pos) /*!< 0x00000010 */
+#define USB_EP0R_STAT_TX_1 (0x2U << USB_EP0R_STAT_TX_Pos) /*!< 0x00000020 */
+
+#define USB_EP0R_DTOG_TX_Pos (6U)
+#define USB_EP0R_DTOG_TX_Msk (0x1U << USB_EP0R_DTOG_TX_Pos) /*!< 0x00000040 */
+#define USB_EP0R_DTOG_TX USB_EP0R_DTOG_TX_Msk /*!< Data Toggle, for transmission transfers */
+#define USB_EP0R_CTR_TX_Pos (7U)
+#define USB_EP0R_CTR_TX_Msk (0x1U << USB_EP0R_CTR_TX_Pos) /*!< 0x00000080 */
+#define USB_EP0R_CTR_TX USB_EP0R_CTR_TX_Msk /*!< Correct Transfer for transmission */
+#define USB_EP0R_EP_KIND_Pos (8U)
+#define USB_EP0R_EP_KIND_Msk (0x1U << USB_EP0R_EP_KIND_Pos) /*!< 0x00000100 */
+#define USB_EP0R_EP_KIND USB_EP0R_EP_KIND_Msk /*!< Endpoint Kind */
+
+#define USB_EP0R_EP_TYPE_Pos (9U)
+#define USB_EP0R_EP_TYPE_Msk (0x3U << USB_EP0R_EP_TYPE_Pos) /*!< 0x00000600 */
+#define USB_EP0R_EP_TYPE USB_EP0R_EP_TYPE_Msk /*!< EP_TYPE[1:0] bits (Endpoint type) */
+#define USB_EP0R_EP_TYPE_0 (0x1U << USB_EP0R_EP_TYPE_Pos) /*!< 0x00000200 */
+#define USB_EP0R_EP_TYPE_1 (0x2U << USB_EP0R_EP_TYPE_Pos) /*!< 0x00000400 */
+
+#define USB_EP0R_SETUP_Pos (11U)
+#define USB_EP0R_SETUP_Msk (0x1U << USB_EP0R_SETUP_Pos) /*!< 0x00000800 */
+#define USB_EP0R_SETUP USB_EP0R_SETUP_Msk /*!< Setup transaction completed */
+
+#define USB_EP0R_STAT_RX_Pos (12U)
+#define USB_EP0R_STAT_RX_Msk (0x3U << USB_EP0R_STAT_RX_Pos) /*!< 0x00003000 */
+#define USB_EP0R_STAT_RX USB_EP0R_STAT_RX_Msk /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */
+#define USB_EP0R_STAT_RX_0 (0x1U << USB_EP0R_STAT_RX_Pos) /*!< 0x00001000 */
+#define USB_EP0R_STAT_RX_1 (0x2U << USB_EP0R_STAT_RX_Pos) /*!< 0x00002000 */
+
+#define USB_EP0R_DTOG_RX_Pos (14U)
+#define USB_EP0R_DTOG_RX_Msk (0x1U << USB_EP0R_DTOG_RX_Pos) /*!< 0x00004000 */
+#define USB_EP0R_DTOG_RX USB_EP0R_DTOG_RX_Msk /*!< Data Toggle, for reception transfers */
+#define USB_EP0R_CTR_RX_Pos (15U)
+#define USB_EP0R_CTR_RX_Msk (0x1U << USB_EP0R_CTR_RX_Pos) /*!< 0x00008000 */
+#define USB_EP0R_CTR_RX USB_EP0R_CTR_RX_Msk /*!< Correct Transfer for reception */
+
+/******************* Bit definition for USB_EP1R register *******************/
+#define USB_EP1R_EA_Pos (0U)
+#define USB_EP1R_EA_Msk (0xFU << USB_EP1R_EA_Pos) /*!< 0x0000000F */
+#define USB_EP1R_EA USB_EP1R_EA_Msk /*!< Endpoint Address */
+
+#define USB_EP1R_STAT_TX_Pos (4U)
+#define USB_EP1R_STAT_TX_Msk (0x3U << USB_EP1R_STAT_TX_Pos) /*!< 0x00000030 */
+#define USB_EP1R_STAT_TX USB_EP1R_STAT_TX_Msk /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */
+#define USB_EP1R_STAT_TX_0 (0x1U << USB_EP1R_STAT_TX_Pos) /*!< 0x00000010 */
+#define USB_EP1R_STAT_TX_1 (0x2U << USB_EP1R_STAT_TX_Pos) /*!< 0x00000020 */
+
+#define USB_EP1R_DTOG_TX_Pos (6U)
+#define USB_EP1R_DTOG_TX_Msk (0x1U << USB_EP1R_DTOG_TX_Pos) /*!< 0x00000040 */
+#define USB_EP1R_DTOG_TX USB_EP1R_DTOG_TX_Msk /*!< Data Toggle, for transmission transfers */
+#define USB_EP1R_CTR_TX_Pos (7U)
+#define USB_EP1R_CTR_TX_Msk (0x1U << USB_EP1R_CTR_TX_Pos) /*!< 0x00000080 */
+#define USB_EP1R_CTR_TX USB_EP1R_CTR_TX_Msk /*!< Correct Transfer for transmission */
+#define USB_EP1R_EP_KIND_Pos (8U)
+#define USB_EP1R_EP_KIND_Msk (0x1U << USB_EP1R_EP_KIND_Pos) /*!< 0x00000100 */
+#define USB_EP1R_EP_KIND USB_EP1R_EP_KIND_Msk /*!< Endpoint Kind */
+
+#define USB_EP1R_EP_TYPE_Pos (9U)
+#define USB_EP1R_EP_TYPE_Msk (0x3U << USB_EP1R_EP_TYPE_Pos) /*!< 0x00000600 */
+#define USB_EP1R_EP_TYPE USB_EP1R_EP_TYPE_Msk /*!< EP_TYPE[1:0] bits (Endpoint type) */
+#define USB_EP1R_EP_TYPE_0 (0x1U << USB_EP1R_EP_TYPE_Pos) /*!< 0x00000200 */
+#define USB_EP1R_EP_TYPE_1 (0x2U << USB_EP1R_EP_TYPE_Pos) /*!< 0x00000400 */
+
+#define USB_EP1R_SETUP_Pos (11U)
+#define USB_EP1R_SETUP_Msk (0x1U << USB_EP1R_SETUP_Pos) /*!< 0x00000800 */
+#define USB_EP1R_SETUP USB_EP1R_SETUP_Msk /*!< Setup transaction completed */
+
+#define USB_EP1R_STAT_RX_Pos (12U)
+#define USB_EP1R_STAT_RX_Msk (0x3U << USB_EP1R_STAT_RX_Pos) /*!< 0x00003000 */
+#define USB_EP1R_STAT_RX USB_EP1R_STAT_RX_Msk /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */
+#define USB_EP1R_STAT_RX_0 (0x1U << USB_EP1R_STAT_RX_Pos) /*!< 0x00001000 */
+#define USB_EP1R_STAT_RX_1 (0x2U << USB_EP1R_STAT_RX_Pos) /*!< 0x00002000 */
+
+#define USB_EP1R_DTOG_RX_Pos (14U)
+#define USB_EP1R_DTOG_RX_Msk (0x1U << USB_EP1R_DTOG_RX_Pos) /*!< 0x00004000 */
+#define USB_EP1R_DTOG_RX USB_EP1R_DTOG_RX_Msk /*!< Data Toggle, for reception transfers */
+#define USB_EP1R_CTR_RX_Pos (15U)
+#define USB_EP1R_CTR_RX_Msk (0x1U << USB_EP1R_CTR_RX_Pos) /*!< 0x00008000 */
+#define USB_EP1R_CTR_RX USB_EP1R_CTR_RX_Msk /*!< Correct Transfer for reception */
+
+/******************* Bit definition for USB_EP2R register *******************/
+#define USB_EP2R_EA_Pos (0U)
+#define USB_EP2R_EA_Msk (0xFU << USB_EP2R_EA_Pos) /*!< 0x0000000F */
+#define USB_EP2R_EA USB_EP2R_EA_Msk /*!< Endpoint Address */
+
+#define USB_EP2R_STAT_TX_Pos (4U)
+#define USB_EP2R_STAT_TX_Msk (0x3U << USB_EP2R_STAT_TX_Pos) /*!< 0x00000030 */
+#define USB_EP2R_STAT_TX USB_EP2R_STAT_TX_Msk /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */
+#define USB_EP2R_STAT_TX_0 (0x1U << USB_EP2R_STAT_TX_Pos) /*!< 0x00000010 */
+#define USB_EP2R_STAT_TX_1 (0x2U << USB_EP2R_STAT_TX_Pos) /*!< 0x00000020 */
+
+#define USB_EP2R_DTOG_TX_Pos (6U)
+#define USB_EP2R_DTOG_TX_Msk (0x1U << USB_EP2R_DTOG_TX_Pos) /*!< 0x00000040 */
+#define USB_EP2R_DTOG_TX USB_EP2R_DTOG_TX_Msk /*!< Data Toggle, for transmission transfers */
+#define USB_EP2R_CTR_TX_Pos (7U)
+#define USB_EP2R_CTR_TX_Msk (0x1U << USB_EP2R_CTR_TX_Pos) /*!< 0x00000080 */
+#define USB_EP2R_CTR_TX USB_EP2R_CTR_TX_Msk /*!< Correct Transfer for transmission */
+#define USB_EP2R_EP_KIND_Pos (8U)
+#define USB_EP2R_EP_KIND_Msk (0x1U << USB_EP2R_EP_KIND_Pos) /*!< 0x00000100 */
+#define USB_EP2R_EP_KIND USB_EP2R_EP_KIND_Msk /*!< Endpoint Kind */
+
+#define USB_EP2R_EP_TYPE_Pos (9U)
+#define USB_EP2R_EP_TYPE_Msk (0x3U << USB_EP2R_EP_TYPE_Pos) /*!< 0x00000600 */
+#define USB_EP2R_EP_TYPE USB_EP2R_EP_TYPE_Msk /*!< EP_TYPE[1:0] bits (Endpoint type) */
+#define USB_EP2R_EP_TYPE_0 (0x1U << USB_EP2R_EP_TYPE_Pos) /*!< 0x00000200 */
+#define USB_EP2R_EP_TYPE_1 (0x2U << USB_EP2R_EP_TYPE_Pos) /*!< 0x00000400 */
+
+#define USB_EP2R_SETUP_Pos (11U)
+#define USB_EP2R_SETUP_Msk (0x1U << USB_EP2R_SETUP_Pos) /*!< 0x00000800 */
+#define USB_EP2R_SETUP USB_EP2R_SETUP_Msk /*!< Setup transaction completed */
+
+#define USB_EP2R_STAT_RX_Pos (12U)
+#define USB_EP2R_STAT_RX_Msk (0x3U << USB_EP2R_STAT_RX_Pos) /*!< 0x00003000 */
+#define USB_EP2R_STAT_RX USB_EP2R_STAT_RX_Msk /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */
+#define USB_EP2R_STAT_RX_0 (0x1U << USB_EP2R_STAT_RX_Pos) /*!< 0x00001000 */
+#define USB_EP2R_STAT_RX_1 (0x2U << USB_EP2R_STAT_RX_Pos) /*!< 0x00002000 */
+
+#define USB_EP2R_DTOG_RX_Pos (14U)
+#define USB_EP2R_DTOG_RX_Msk (0x1U << USB_EP2R_DTOG_RX_Pos) /*!< 0x00004000 */
+#define USB_EP2R_DTOG_RX USB_EP2R_DTOG_RX_Msk /*!< Data Toggle, for reception transfers */
+#define USB_EP2R_CTR_RX_Pos (15U)
+#define USB_EP2R_CTR_RX_Msk (0x1U << USB_EP2R_CTR_RX_Pos) /*!< 0x00008000 */
+#define USB_EP2R_CTR_RX USB_EP2R_CTR_RX_Msk /*!< Correct Transfer for reception */
+
+/******************* Bit definition for USB_EP3R register *******************/
+#define USB_EP3R_EA_Pos (0U)
+#define USB_EP3R_EA_Msk (0xFU << USB_EP3R_EA_Pos) /*!< 0x0000000F */
+#define USB_EP3R_EA USB_EP3R_EA_Msk /*!< Endpoint Address */
+
+#define USB_EP3R_STAT_TX_Pos (4U)
+#define USB_EP3R_STAT_TX_Msk (0x3U << USB_EP3R_STAT_TX_Pos) /*!< 0x00000030 */
+#define USB_EP3R_STAT_TX USB_EP3R_STAT_TX_Msk /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */
+#define USB_EP3R_STAT_TX_0 (0x1U << USB_EP3R_STAT_TX_Pos) /*!< 0x00000010 */
+#define USB_EP3R_STAT_TX_1 (0x2U << USB_EP3R_STAT_TX_Pos) /*!< 0x00000020 */
+
+#define USB_EP3R_DTOG_TX_Pos (6U)
+#define USB_EP3R_DTOG_TX_Msk (0x1U << USB_EP3R_DTOG_TX_Pos) /*!< 0x00000040 */
+#define USB_EP3R_DTOG_TX USB_EP3R_DTOG_TX_Msk /*!< Data Toggle, for transmission transfers */
+#define USB_EP3R_CTR_TX_Pos (7U)
+#define USB_EP3R_CTR_TX_Msk (0x1U << USB_EP3R_CTR_TX_Pos) /*!< 0x00000080 */
+#define USB_EP3R_CTR_TX USB_EP3R_CTR_TX_Msk /*!< Correct Transfer for transmission */
+#define USB_EP3R_EP_KIND_Pos (8U)
+#define USB_EP3R_EP_KIND_Msk (0x1U << USB_EP3R_EP_KIND_Pos) /*!< 0x00000100 */
+#define USB_EP3R_EP_KIND USB_EP3R_EP_KIND_Msk /*!< Endpoint Kind */
+
+#define USB_EP3R_EP_TYPE_Pos (9U)
+#define USB_EP3R_EP_TYPE_Msk (0x3U << USB_EP3R_EP_TYPE_Pos) /*!< 0x00000600 */
+#define USB_EP3R_EP_TYPE USB_EP3R_EP_TYPE_Msk /*!< EP_TYPE[1:0] bits (Endpoint type) */
+#define USB_EP3R_EP_TYPE_0 (0x1U << USB_EP3R_EP_TYPE_Pos) /*!< 0x00000200 */
+#define USB_EP3R_EP_TYPE_1 (0x2U << USB_EP3R_EP_TYPE_Pos) /*!< 0x00000400 */
+
+#define USB_EP3R_SETUP_Pos (11U)
+#define USB_EP3R_SETUP_Msk (0x1U << USB_EP3R_SETUP_Pos) /*!< 0x00000800 */
+#define USB_EP3R_SETUP USB_EP3R_SETUP_Msk /*!< Setup transaction completed */
+
+#define USB_EP3R_STAT_RX_Pos (12U)
+#define USB_EP3R_STAT_RX_Msk (0x3U << USB_EP3R_STAT_RX_Pos) /*!< 0x00003000 */
+#define USB_EP3R_STAT_RX USB_EP3R_STAT_RX_Msk /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */
+#define USB_EP3R_STAT_RX_0 (0x1U << USB_EP3R_STAT_RX_Pos) /*!< 0x00001000 */
+#define USB_EP3R_STAT_RX_1 (0x2U << USB_EP3R_STAT_RX_Pos) /*!< 0x00002000 */
+
+#define USB_EP3R_DTOG_RX_Pos (14U)
+#define USB_EP3R_DTOG_RX_Msk (0x1U << USB_EP3R_DTOG_RX_Pos) /*!< 0x00004000 */
+#define USB_EP3R_DTOG_RX USB_EP3R_DTOG_RX_Msk /*!< Data Toggle, for reception transfers */
+#define USB_EP3R_CTR_RX_Pos (15U)
+#define USB_EP3R_CTR_RX_Msk (0x1U << USB_EP3R_CTR_RX_Pos) /*!< 0x00008000 */
+#define USB_EP3R_CTR_RX USB_EP3R_CTR_RX_Msk /*!< Correct Transfer for reception */
+
+/******************* Bit definition for USB_EP4R register *******************/
+#define USB_EP4R_EA_Pos (0U)
+#define USB_EP4R_EA_Msk (0xFU << USB_EP4R_EA_Pos) /*!< 0x0000000F */
+#define USB_EP4R_EA USB_EP4R_EA_Msk /*!< Endpoint Address */
+
+#define USB_EP4R_STAT_TX_Pos (4U)
+#define USB_EP4R_STAT_TX_Msk (0x3U << USB_EP4R_STAT_TX_Pos) /*!< 0x00000030 */
+#define USB_EP4R_STAT_TX USB_EP4R_STAT_TX_Msk /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */
+#define USB_EP4R_STAT_TX_0 (0x1U << USB_EP4R_STAT_TX_Pos) /*!< 0x00000010 */
+#define USB_EP4R_STAT_TX_1 (0x2U << USB_EP4R_STAT_TX_Pos) /*!< 0x00000020 */
+
+#define USB_EP4R_DTOG_TX_Pos (6U)
+#define USB_EP4R_DTOG_TX_Msk (0x1U << USB_EP4R_DTOG_TX_Pos) /*!< 0x00000040 */
+#define USB_EP4R_DTOG_TX USB_EP4R_DTOG_TX_Msk /*!< Data Toggle, for transmission transfers */
+#define USB_EP4R_CTR_TX_Pos (7U)
+#define USB_EP4R_CTR_TX_Msk (0x1U << USB_EP4R_CTR_TX_Pos) /*!< 0x00000080 */
+#define USB_EP4R_CTR_TX USB_EP4R_CTR_TX_Msk /*!< Correct Transfer for transmission */
+#define USB_EP4R_EP_KIND_Pos (8U)
+#define USB_EP4R_EP_KIND_Msk (0x1U << USB_EP4R_EP_KIND_Pos) /*!< 0x00000100 */
+#define USB_EP4R_EP_KIND USB_EP4R_EP_KIND_Msk /*!< Endpoint Kind */
+
+#define USB_EP4R_EP_TYPE_Pos (9U)
+#define USB_EP4R_EP_TYPE_Msk (0x3U << USB_EP4R_EP_TYPE_Pos) /*!< 0x00000600 */
+#define USB_EP4R_EP_TYPE USB_EP4R_EP_TYPE_Msk /*!< EP_TYPE[1:0] bits (Endpoint type) */
+#define USB_EP4R_EP_TYPE_0 (0x1U << USB_EP4R_EP_TYPE_Pos) /*!< 0x00000200 */
+#define USB_EP4R_EP_TYPE_1 (0x2U << USB_EP4R_EP_TYPE_Pos) /*!< 0x00000400 */
+
+#define USB_EP4R_SETUP_Pos (11U)
+#define USB_EP4R_SETUP_Msk (0x1U << USB_EP4R_SETUP_Pos) /*!< 0x00000800 */
+#define USB_EP4R_SETUP USB_EP4R_SETUP_Msk /*!< Setup transaction completed */
+
+#define USB_EP4R_STAT_RX_Pos (12U)
+#define USB_EP4R_STAT_RX_Msk (0x3U << USB_EP4R_STAT_RX_Pos) /*!< 0x00003000 */
+#define USB_EP4R_STAT_RX USB_EP4R_STAT_RX_Msk /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */
+#define USB_EP4R_STAT_RX_0 (0x1U << USB_EP4R_STAT_RX_Pos) /*!< 0x00001000 */
+#define USB_EP4R_STAT_RX_1 (0x2U << USB_EP4R_STAT_RX_Pos) /*!< 0x00002000 */
+
+#define USB_EP4R_DTOG_RX_Pos (14U)
+#define USB_EP4R_DTOG_RX_Msk (0x1U << USB_EP4R_DTOG_RX_Pos) /*!< 0x00004000 */
+#define USB_EP4R_DTOG_RX USB_EP4R_DTOG_RX_Msk /*!< Data Toggle, for reception transfers */
+#define USB_EP4R_CTR_RX_Pos (15U)
+#define USB_EP4R_CTR_RX_Msk (0x1U << USB_EP4R_CTR_RX_Pos) /*!< 0x00008000 */
+#define USB_EP4R_CTR_RX USB_EP4R_CTR_RX_Msk /*!< Correct Transfer for reception */
+
+/******************* Bit definition for USB_EP5R register *******************/
+#define USB_EP5R_EA_Pos (0U)
+#define USB_EP5R_EA_Msk (0xFU << USB_EP5R_EA_Pos) /*!< 0x0000000F */
+#define USB_EP5R_EA USB_EP5R_EA_Msk /*!< Endpoint Address */
+
+#define USB_EP5R_STAT_TX_Pos (4U)
+#define USB_EP5R_STAT_TX_Msk (0x3U << USB_EP5R_STAT_TX_Pos) /*!< 0x00000030 */
+#define USB_EP5R_STAT_TX USB_EP5R_STAT_TX_Msk /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */
+#define USB_EP5R_STAT_TX_0 (0x1U << USB_EP5R_STAT_TX_Pos) /*!< 0x00000010 */
+#define USB_EP5R_STAT_TX_1 (0x2U << USB_EP5R_STAT_TX_Pos) /*!< 0x00000020 */
+
+#define USB_EP5R_DTOG_TX_Pos (6U)
+#define USB_EP5R_DTOG_TX_Msk (0x1U << USB_EP5R_DTOG_TX_Pos) /*!< 0x00000040 */
+#define USB_EP5R_DTOG_TX USB_EP5R_DTOG_TX_Msk /*!< Data Toggle, for transmission transfers */
+#define USB_EP5R_CTR_TX_Pos (7U)
+#define USB_EP5R_CTR_TX_Msk (0x1U << USB_EP5R_CTR_TX_Pos) /*!< 0x00000080 */
+#define USB_EP5R_CTR_TX USB_EP5R_CTR_TX_Msk /*!< Correct Transfer for transmission */
+#define USB_EP5R_EP_KIND_Pos (8U)
+#define USB_EP5R_EP_KIND_Msk (0x1U << USB_EP5R_EP_KIND_Pos) /*!< 0x00000100 */
+#define USB_EP5R_EP_KIND USB_EP5R_EP_KIND_Msk /*!< Endpoint Kind */
+
+#define USB_EP5R_EP_TYPE_Pos (9U)
+#define USB_EP5R_EP_TYPE_Msk (0x3U << USB_EP5R_EP_TYPE_Pos) /*!< 0x00000600 */
+#define USB_EP5R_EP_TYPE USB_EP5R_EP_TYPE_Msk /*!< EP_TYPE[1:0] bits (Endpoint type) */
+#define USB_EP5R_EP_TYPE_0 (0x1U << USB_EP5R_EP_TYPE_Pos) /*!< 0x00000200 */
+#define USB_EP5R_EP_TYPE_1 (0x2U << USB_EP5R_EP_TYPE_Pos) /*!< 0x00000400 */
+
+#define USB_EP5R_SETUP_Pos (11U)
+#define USB_EP5R_SETUP_Msk (0x1U << USB_EP5R_SETUP_Pos) /*!< 0x00000800 */
+#define USB_EP5R_SETUP USB_EP5R_SETUP_Msk /*!< Setup transaction completed */
+
+#define USB_EP5R_STAT_RX_Pos (12U)
+#define USB_EP5R_STAT_RX_Msk (0x3U << USB_EP5R_STAT_RX_Pos) /*!< 0x00003000 */
+#define USB_EP5R_STAT_RX USB_EP5R_STAT_RX_Msk /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */
+#define USB_EP5R_STAT_RX_0 (0x1U << USB_EP5R_STAT_RX_Pos) /*!< 0x00001000 */
+#define USB_EP5R_STAT_RX_1 (0x2U << USB_EP5R_STAT_RX_Pos) /*!< 0x00002000 */
+
+#define USB_EP5R_DTOG_RX_Pos (14U)
+#define USB_EP5R_DTOG_RX_Msk (0x1U << USB_EP5R_DTOG_RX_Pos) /*!< 0x00004000 */
+#define USB_EP5R_DTOG_RX USB_EP5R_DTOG_RX_Msk /*!< Data Toggle, for reception transfers */
+#define USB_EP5R_CTR_RX_Pos (15U)
+#define USB_EP5R_CTR_RX_Msk (0x1U << USB_EP5R_CTR_RX_Pos) /*!< 0x00008000 */
+#define USB_EP5R_CTR_RX USB_EP5R_CTR_RX_Msk /*!< Correct Transfer for reception */
+
+/******************* Bit definition for USB_EP6R register *******************/
+#define USB_EP6R_EA_Pos (0U)
+#define USB_EP6R_EA_Msk (0xFU << USB_EP6R_EA_Pos) /*!< 0x0000000F */
+#define USB_EP6R_EA USB_EP6R_EA_Msk /*!< Endpoint Address */
+
+#define USB_EP6R_STAT_TX_Pos (4U)
+#define USB_EP6R_STAT_TX_Msk (0x3U << USB_EP6R_STAT_TX_Pos) /*!< 0x00000030 */
+#define USB_EP6R_STAT_TX USB_EP6R_STAT_TX_Msk /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */
+#define USB_EP6R_STAT_TX_0 (0x1U << USB_EP6R_STAT_TX_Pos) /*!< 0x00000010 */
+#define USB_EP6R_STAT_TX_1 (0x2U << USB_EP6R_STAT_TX_Pos) /*!< 0x00000020 */
+
+#define USB_EP6R_DTOG_TX_Pos (6U)
+#define USB_EP6R_DTOG_TX_Msk (0x1U << USB_EP6R_DTOG_TX_Pos) /*!< 0x00000040 */
+#define USB_EP6R_DTOG_TX USB_EP6R_DTOG_TX_Msk /*!< Data Toggle, for transmission transfers */
+#define USB_EP6R_CTR_TX_Pos (7U)
+#define USB_EP6R_CTR_TX_Msk (0x1U << USB_EP6R_CTR_TX_Pos) /*!< 0x00000080 */
+#define USB_EP6R_CTR_TX USB_EP6R_CTR_TX_Msk /*!< Correct Transfer for transmission */
+#define USB_EP6R_EP_KIND_Pos (8U)
+#define USB_EP6R_EP_KIND_Msk (0x1U << USB_EP6R_EP_KIND_Pos) /*!< 0x00000100 */
+#define USB_EP6R_EP_KIND USB_EP6R_EP_KIND_Msk /*!< Endpoint Kind */
+
+#define USB_EP6R_EP_TYPE_Pos (9U)
+#define USB_EP6R_EP_TYPE_Msk (0x3U << USB_EP6R_EP_TYPE_Pos) /*!< 0x00000600 */
+#define USB_EP6R_EP_TYPE USB_EP6R_EP_TYPE_Msk /*!< EP_TYPE[1:0] bits (Endpoint type) */
+#define USB_EP6R_EP_TYPE_0 (0x1U << USB_EP6R_EP_TYPE_Pos) /*!< 0x00000200 */
+#define USB_EP6R_EP_TYPE_1 (0x2U << USB_EP6R_EP_TYPE_Pos) /*!< 0x00000400 */
+
+#define USB_EP6R_SETUP_Pos (11U)
+#define USB_EP6R_SETUP_Msk (0x1U << USB_EP6R_SETUP_Pos) /*!< 0x00000800 */
+#define USB_EP6R_SETUP USB_EP6R_SETUP_Msk /*!< Setup transaction completed */
+
+#define USB_EP6R_STAT_RX_Pos (12U)
+#define USB_EP6R_STAT_RX_Msk (0x3U << USB_EP6R_STAT_RX_Pos) /*!< 0x00003000 */
+#define USB_EP6R_STAT_RX USB_EP6R_STAT_RX_Msk /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */
+#define USB_EP6R_STAT_RX_0 (0x1U << USB_EP6R_STAT_RX_Pos) /*!< 0x00001000 */
+#define USB_EP6R_STAT_RX_1 (0x2U << USB_EP6R_STAT_RX_Pos) /*!< 0x00002000 */
+
+#define USB_EP6R_DTOG_RX_Pos (14U)
+#define USB_EP6R_DTOG_RX_Msk (0x1U << USB_EP6R_DTOG_RX_Pos) /*!< 0x00004000 */
+#define USB_EP6R_DTOG_RX USB_EP6R_DTOG_RX_Msk /*!< Data Toggle, for reception transfers */
+#define USB_EP6R_CTR_RX_Pos (15U)
+#define USB_EP6R_CTR_RX_Msk (0x1U << USB_EP6R_CTR_RX_Pos) /*!< 0x00008000 */
+#define USB_EP6R_CTR_RX USB_EP6R_CTR_RX_Msk /*!< Correct Transfer for reception */
+
+/******************* Bit definition for USB_EP7R register *******************/
+#define USB_EP7R_EA_Pos (0U)
+#define USB_EP7R_EA_Msk (0xFU << USB_EP7R_EA_Pos) /*!< 0x0000000F */
+#define USB_EP7R_EA USB_EP7R_EA_Msk /*!< Endpoint Address */
+
+#define USB_EP7R_STAT_TX_Pos (4U)
+#define USB_EP7R_STAT_TX_Msk (0x3U << USB_EP7R_STAT_TX_Pos) /*!< 0x00000030 */
+#define USB_EP7R_STAT_TX USB_EP7R_STAT_TX_Msk /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */
+#define USB_EP7R_STAT_TX_0 (0x1U << USB_EP7R_STAT_TX_Pos) /*!< 0x00000010 */
+#define USB_EP7R_STAT_TX_1 (0x2U << USB_EP7R_STAT_TX_Pos) /*!< 0x00000020 */
+
+#define USB_EP7R_DTOG_TX_Pos (6U)
+#define USB_EP7R_DTOG_TX_Msk (0x1U << USB_EP7R_DTOG_TX_Pos) /*!< 0x00000040 */
+#define USB_EP7R_DTOG_TX USB_EP7R_DTOG_TX_Msk /*!< Data Toggle, for transmission transfers */
+#define USB_EP7R_CTR_TX_Pos (7U)
+#define USB_EP7R_CTR_TX_Msk (0x1U << USB_EP7R_CTR_TX_Pos) /*!< 0x00000080 */
+#define USB_EP7R_CTR_TX USB_EP7R_CTR_TX_Msk /*!< Correct Transfer for transmission */
+#define USB_EP7R_EP_KIND_Pos (8U)
+#define USB_EP7R_EP_KIND_Msk (0x1U << USB_EP7R_EP_KIND_Pos) /*!< 0x00000100 */
+#define USB_EP7R_EP_KIND USB_EP7R_EP_KIND_Msk /*!< Endpoint Kind */
+
+#define USB_EP7R_EP_TYPE_Pos (9U)
+#define USB_EP7R_EP_TYPE_Msk (0x3U << USB_EP7R_EP_TYPE_Pos) /*!< 0x00000600 */
+#define USB_EP7R_EP_TYPE USB_EP7R_EP_TYPE_Msk /*!< EP_TYPE[1:0] bits (Endpoint type) */
+#define USB_EP7R_EP_TYPE_0 (0x1U << USB_EP7R_EP_TYPE_Pos) /*!< 0x00000200 */
+#define USB_EP7R_EP_TYPE_1 (0x2U << USB_EP7R_EP_TYPE_Pos) /*!< 0x00000400 */
+
+#define USB_EP7R_SETUP_Pos (11U)
+#define USB_EP7R_SETUP_Msk (0x1U << USB_EP7R_SETUP_Pos) /*!< 0x00000800 */
+#define USB_EP7R_SETUP USB_EP7R_SETUP_Msk /*!< Setup transaction completed */
+
+#define USB_EP7R_STAT_RX_Pos (12U)
+#define USB_EP7R_STAT_RX_Msk (0x3U << USB_EP7R_STAT_RX_Pos) /*!< 0x00003000 */
+#define USB_EP7R_STAT_RX USB_EP7R_STAT_RX_Msk /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */
+#define USB_EP7R_STAT_RX_0 (0x1U << USB_EP7R_STAT_RX_Pos) /*!< 0x00001000 */
+#define USB_EP7R_STAT_RX_1 (0x2U << USB_EP7R_STAT_RX_Pos) /*!< 0x00002000 */
+
+#define USB_EP7R_DTOG_RX_Pos (14U)
+#define USB_EP7R_DTOG_RX_Msk (0x1U << USB_EP7R_DTOG_RX_Pos) /*!< 0x00004000 */
+#define USB_EP7R_DTOG_RX USB_EP7R_DTOG_RX_Msk /*!< Data Toggle, for reception transfers */
+#define USB_EP7R_CTR_RX_Pos (15U)
+#define USB_EP7R_CTR_RX_Msk (0x1U << USB_EP7R_CTR_RX_Pos) /*!< 0x00008000 */
+#define USB_EP7R_CTR_RX USB_EP7R_CTR_RX_Msk /*!< Correct Transfer for reception */
+
+/*!< Common registers */
+/******************* Bit definition for USB_CNTR register *******************/
+#define USB_CNTR_FRES_Pos (0U)
+#define USB_CNTR_FRES_Msk (0x1U << USB_CNTR_FRES_Pos) /*!< 0x00000001 */
+#define USB_CNTR_FRES USB_CNTR_FRES_Msk /*!< Force USB Reset */
+#define USB_CNTR_PDWN_Pos (1U)
+#define USB_CNTR_PDWN_Msk (0x1U << USB_CNTR_PDWN_Pos) /*!< 0x00000002 */
+#define USB_CNTR_PDWN USB_CNTR_PDWN_Msk /*!< Power down */
+#define USB_CNTR_LP_MODE_Pos (2U)
+#define USB_CNTR_LP_MODE_Msk (0x1U << USB_CNTR_LP_MODE_Pos) /*!< 0x00000004 */
+#define USB_CNTR_LP_MODE USB_CNTR_LP_MODE_Msk /*!< Low-power mode */
+#define USB_CNTR_FSUSP_Pos (3U)
+#define USB_CNTR_FSUSP_Msk (0x1U << USB_CNTR_FSUSP_Pos) /*!< 0x00000008 */
+#define USB_CNTR_FSUSP USB_CNTR_FSUSP_Msk /*!< Force suspend */
+#define USB_CNTR_RESUME_Pos (4U)
+#define USB_CNTR_RESUME_Msk (0x1U << USB_CNTR_RESUME_Pos) /*!< 0x00000010 */
+#define USB_CNTR_RESUME USB_CNTR_RESUME_Msk /*!< Resume request */
+#define USB_CNTR_ESOFM_Pos (8U)
+#define USB_CNTR_ESOFM_Msk (0x1U << USB_CNTR_ESOFM_Pos) /*!< 0x00000100 */
+#define USB_CNTR_ESOFM USB_CNTR_ESOFM_Msk /*!< Expected Start Of Frame Interrupt Mask */
+#define USB_CNTR_SOFM_Pos (9U)
+#define USB_CNTR_SOFM_Msk (0x1U << USB_CNTR_SOFM_Pos) /*!< 0x00000200 */
+#define USB_CNTR_SOFM USB_CNTR_SOFM_Msk /*!< Start Of Frame Interrupt Mask */
+#define USB_CNTR_RESETM_Pos (10U)
+#define USB_CNTR_RESETM_Msk (0x1U << USB_CNTR_RESETM_Pos) /*!< 0x00000400 */
+#define USB_CNTR_RESETM USB_CNTR_RESETM_Msk /*!< RESET Interrupt Mask */
+#define USB_CNTR_SUSPM_Pos (11U)
+#define USB_CNTR_SUSPM_Msk (0x1U << USB_CNTR_SUSPM_Pos) /*!< 0x00000800 */
+#define USB_CNTR_SUSPM USB_CNTR_SUSPM_Msk /*!< Suspend mode Interrupt Mask */
+#define USB_CNTR_WKUPM_Pos (12U)
+#define USB_CNTR_WKUPM_Msk (0x1U << USB_CNTR_WKUPM_Pos) /*!< 0x00001000 */
+#define USB_CNTR_WKUPM USB_CNTR_WKUPM_Msk /*!< Wakeup Interrupt Mask */
+#define USB_CNTR_ERRM_Pos (13U)
+#define USB_CNTR_ERRM_Msk (0x1U << USB_CNTR_ERRM_Pos) /*!< 0x00002000 */
+#define USB_CNTR_ERRM USB_CNTR_ERRM_Msk /*!< Error Interrupt Mask */
+#define USB_CNTR_PMAOVRM_Pos (14U)
+#define USB_CNTR_PMAOVRM_Msk (0x1U << USB_CNTR_PMAOVRM_Pos) /*!< 0x00004000 */
+#define USB_CNTR_PMAOVRM USB_CNTR_PMAOVRM_Msk /*!< Packet Memory Area Over / Underrun Interrupt Mask */
+#define USB_CNTR_CTRM_Pos (15U)
+#define USB_CNTR_CTRM_Msk (0x1U << USB_CNTR_CTRM_Pos) /*!< 0x00008000 */
+#define USB_CNTR_CTRM USB_CNTR_CTRM_Msk /*!< Correct Transfer Interrupt Mask */
+
+/******************* Bit definition for USB_ISTR register *******************/
+#define USB_ISTR_EP_ID_Pos (0U)
+#define USB_ISTR_EP_ID_Msk (0xFU << USB_ISTR_EP_ID_Pos) /*!< 0x0000000F */
+#define USB_ISTR_EP_ID USB_ISTR_EP_ID_Msk /*!< Endpoint Identifier */
+#define USB_ISTR_DIR_Pos (4U)
+#define USB_ISTR_DIR_Msk (0x1U << USB_ISTR_DIR_Pos) /*!< 0x00000010 */
+#define USB_ISTR_DIR USB_ISTR_DIR_Msk /*!< Direction of transaction */
+#define USB_ISTR_ESOF_Pos (8U)
+#define USB_ISTR_ESOF_Msk (0x1U << USB_ISTR_ESOF_Pos) /*!< 0x00000100 */
+#define USB_ISTR_ESOF USB_ISTR_ESOF_Msk /*!< Expected Start Of Frame */
+#define USB_ISTR_SOF_Pos (9U)
+#define USB_ISTR_SOF_Msk (0x1U << USB_ISTR_SOF_Pos) /*!< 0x00000200 */
+#define USB_ISTR_SOF USB_ISTR_SOF_Msk /*!< Start Of Frame */
+#define USB_ISTR_RESET_Pos (10U)
+#define USB_ISTR_RESET_Msk (0x1U << USB_ISTR_RESET_Pos) /*!< 0x00000400 */
+#define USB_ISTR_RESET USB_ISTR_RESET_Msk /*!< USB RESET request */
+#define USB_ISTR_SUSP_Pos (11U)
+#define USB_ISTR_SUSP_Msk (0x1U << USB_ISTR_SUSP_Pos) /*!< 0x00000800 */
+#define USB_ISTR_SUSP USB_ISTR_SUSP_Msk /*!< Suspend mode request */
+#define USB_ISTR_WKUP_Pos (12U)
+#define USB_ISTR_WKUP_Msk (0x1U << USB_ISTR_WKUP_Pos) /*!< 0x00001000 */
+#define USB_ISTR_WKUP USB_ISTR_WKUP_Msk /*!< Wake up */
+#define USB_ISTR_ERR_Pos (13U)
+#define USB_ISTR_ERR_Msk (0x1U << USB_ISTR_ERR_Pos) /*!< 0x00002000 */
+#define USB_ISTR_ERR USB_ISTR_ERR_Msk /*!< Error */
+#define USB_ISTR_PMAOVR_Pos (14U)
+#define USB_ISTR_PMAOVR_Msk (0x1U << USB_ISTR_PMAOVR_Pos) /*!< 0x00004000 */
+#define USB_ISTR_PMAOVR USB_ISTR_PMAOVR_Msk /*!< Packet Memory Area Over / Underrun */
+#define USB_ISTR_CTR_Pos (15U)
+#define USB_ISTR_CTR_Msk (0x1U << USB_ISTR_CTR_Pos) /*!< 0x00008000 */
+#define USB_ISTR_CTR USB_ISTR_CTR_Msk /*!< Correct Transfer */
+
+/******************* Bit definition for USB_FNR register ********************/
+#define USB_FNR_FN_Pos (0U)
+#define USB_FNR_FN_Msk (0x7FFU << USB_FNR_FN_Pos) /*!< 0x000007FF */
+#define USB_FNR_FN USB_FNR_FN_Msk /*!< Frame Number */
+#define USB_FNR_LSOF_Pos (11U)
+#define USB_FNR_LSOF_Msk (0x3U << USB_FNR_LSOF_Pos) /*!< 0x00001800 */
+#define USB_FNR_LSOF USB_FNR_LSOF_Msk /*!< Lost SOF */
+#define USB_FNR_LCK_Pos (13U)
+#define USB_FNR_LCK_Msk (0x1U << USB_FNR_LCK_Pos) /*!< 0x00002000 */
+#define USB_FNR_LCK USB_FNR_LCK_Msk /*!< Locked */
+#define USB_FNR_RXDM_Pos (14U)
+#define USB_FNR_RXDM_Msk (0x1U << USB_FNR_RXDM_Pos) /*!< 0x00004000 */
+#define USB_FNR_RXDM USB_FNR_RXDM_Msk /*!< Receive Data - Line Status */
+#define USB_FNR_RXDP_Pos (15U)
+#define USB_FNR_RXDP_Msk (0x1U << USB_FNR_RXDP_Pos) /*!< 0x00008000 */
+#define USB_FNR_RXDP USB_FNR_RXDP_Msk /*!< Receive Data + Line Status */
+
+/****************** Bit definition for USB_DADDR register *******************/
+#define USB_DADDR_ADD_Pos (0U)
+#define USB_DADDR_ADD_Msk (0x7FU << USB_DADDR_ADD_Pos) /*!< 0x0000007F */
+#define USB_DADDR_ADD USB_DADDR_ADD_Msk /*!< ADD[6:0] bits (Device Address) */
+#define USB_DADDR_ADD0_Pos (0U)
+#define USB_DADDR_ADD0_Msk (0x1U << USB_DADDR_ADD0_Pos) /*!< 0x00000001 */
+#define USB_DADDR_ADD0 USB_DADDR_ADD0_Msk /*!< Bit 0 */
+#define USB_DADDR_ADD1_Pos (1U)
+#define USB_DADDR_ADD1_Msk (0x1U << USB_DADDR_ADD1_Pos) /*!< 0x00000002 */
+#define USB_DADDR_ADD1 USB_DADDR_ADD1_Msk /*!< Bit 1 */
+#define USB_DADDR_ADD2_Pos (2U)
+#define USB_DADDR_ADD2_Msk (0x1U << USB_DADDR_ADD2_Pos) /*!< 0x00000004 */
+#define USB_DADDR_ADD2 USB_DADDR_ADD2_Msk /*!< Bit 2 */
+#define USB_DADDR_ADD3_Pos (3U)
+#define USB_DADDR_ADD3_Msk (0x1U << USB_DADDR_ADD3_Pos) /*!< 0x00000008 */
+#define USB_DADDR_ADD3 USB_DADDR_ADD3_Msk /*!< Bit 3 */
+#define USB_DADDR_ADD4_Pos (4U)
+#define USB_DADDR_ADD4_Msk (0x1U << USB_DADDR_ADD4_Pos) /*!< 0x00000010 */
+#define USB_DADDR_ADD4 USB_DADDR_ADD4_Msk /*!< Bit 4 */
+#define USB_DADDR_ADD5_Pos (5U)
+#define USB_DADDR_ADD5_Msk (0x1U << USB_DADDR_ADD5_Pos) /*!< 0x00000020 */
+#define USB_DADDR_ADD5 USB_DADDR_ADD5_Msk /*!< Bit 5 */
+#define USB_DADDR_ADD6_Pos (6U)
+#define USB_DADDR_ADD6_Msk (0x1U << USB_DADDR_ADD6_Pos) /*!< 0x00000040 */
+#define USB_DADDR_ADD6 USB_DADDR_ADD6_Msk /*!< Bit 6 */
+
+#define USB_DADDR_EF_Pos (7U)
+#define USB_DADDR_EF_Msk (0x1U << USB_DADDR_EF_Pos) /*!< 0x00000080 */
+#define USB_DADDR_EF USB_DADDR_EF_Msk /*!< Enable Function */
+
+/****************** Bit definition for USB_BTABLE register ******************/
+#define USB_BTABLE_BTABLE_Pos (3U)
+#define USB_BTABLE_BTABLE_Msk (0x1FFFU << USB_BTABLE_BTABLE_Pos) /*!< 0x0000FFF8 */
+#define USB_BTABLE_BTABLE USB_BTABLE_BTABLE_Msk /*!< Buffer Table */
+
+/*!< Buffer descriptor table */
+/***************** Bit definition for USB_ADDR0_TX register *****************/
+#define USB_ADDR0_TX_ADDR0_TX_Pos (1U)
+#define USB_ADDR0_TX_ADDR0_TX_Msk (0x7FFFU << USB_ADDR0_TX_ADDR0_TX_Pos) /*!< 0x0000FFFE */
+#define USB_ADDR0_TX_ADDR0_TX USB_ADDR0_TX_ADDR0_TX_Msk /*!< Transmission Buffer Address 0 */
+
+/***************** Bit definition for USB_ADDR1_TX register *****************/
+#define USB_ADDR1_TX_ADDR1_TX_Pos (1U)
+#define USB_ADDR1_TX_ADDR1_TX_Msk (0x7FFFU << USB_ADDR1_TX_ADDR1_TX_Pos) /*!< 0x0000FFFE */
+#define USB_ADDR1_TX_ADDR1_TX USB_ADDR1_TX_ADDR1_TX_Msk /*!< Transmission Buffer Address 1 */
+
+/***************** Bit definition for USB_ADDR2_TX register *****************/
+#define USB_ADDR2_TX_ADDR2_TX_Pos (1U)
+#define USB_ADDR2_TX_ADDR2_TX_Msk (0x7FFFU << USB_ADDR2_TX_ADDR2_TX_Pos) /*!< 0x0000FFFE */
+#define USB_ADDR2_TX_ADDR2_TX USB_ADDR2_TX_ADDR2_TX_Msk /*!< Transmission Buffer Address 2 */
+
+/***************** Bit definition for USB_ADDR3_TX register *****************/
+#define USB_ADDR3_TX_ADDR3_TX_Pos (1U)
+#define USB_ADDR3_TX_ADDR3_TX_Msk (0x7FFFU << USB_ADDR3_TX_ADDR3_TX_Pos) /*!< 0x0000FFFE */
+#define USB_ADDR3_TX_ADDR3_TX USB_ADDR3_TX_ADDR3_TX_Msk /*!< Transmission Buffer Address 3 */
+
+/***************** Bit definition for USB_ADDR4_TX register *****************/
+#define USB_ADDR4_TX_ADDR4_TX_Pos (1U)
+#define USB_ADDR4_TX_ADDR4_TX_Msk (0x7FFFU << USB_ADDR4_TX_ADDR4_TX_Pos) /*!< 0x0000FFFE */
+#define USB_ADDR4_TX_ADDR4_TX USB_ADDR4_TX_ADDR4_TX_Msk /*!< Transmission Buffer Address 4 */
+
+/***************** Bit definition for USB_ADDR5_TX register *****************/
+#define USB_ADDR5_TX_ADDR5_TX_Pos (1U)
+#define USB_ADDR5_TX_ADDR5_TX_Msk (0x7FFFU << USB_ADDR5_TX_ADDR5_TX_Pos) /*!< 0x0000FFFE */
+#define USB_ADDR5_TX_ADDR5_TX USB_ADDR5_TX_ADDR5_TX_Msk /*!< Transmission Buffer Address 5 */
+
+/***************** Bit definition for USB_ADDR6_TX register *****************/
+#define USB_ADDR6_TX_ADDR6_TX_Pos (1U)
+#define USB_ADDR6_TX_ADDR6_TX_Msk (0x7FFFU << USB_ADDR6_TX_ADDR6_TX_Pos) /*!< 0x0000FFFE */
+#define USB_ADDR6_TX_ADDR6_TX USB_ADDR6_TX_ADDR6_TX_Msk /*!< Transmission Buffer Address 6 */
+
+/***************** Bit definition for USB_ADDR7_TX register *****************/
+#define USB_ADDR7_TX_ADDR7_TX_Pos (1U)
+#define USB_ADDR7_TX_ADDR7_TX_Msk (0x7FFFU << USB_ADDR7_TX_ADDR7_TX_Pos) /*!< 0x0000FFFE */
+#define USB_ADDR7_TX_ADDR7_TX USB_ADDR7_TX_ADDR7_TX_Msk /*!< Transmission Buffer Address 7 */
+
+/*----------------------------------------------------------------------------*/
+
+/***************** Bit definition for USB_COUNT0_TX register ****************/
+#define USB_COUNT0_TX_COUNT0_TX_Pos (0U)
+#define USB_COUNT0_TX_COUNT0_TX_Msk (0x3FFU << USB_COUNT0_TX_COUNT0_TX_Pos) /*!< 0x000003FF */
+#define USB_COUNT0_TX_COUNT0_TX USB_COUNT0_TX_COUNT0_TX_Msk /*!< Transmission Byte Count 0 */
+
+/***************** Bit definition for USB_COUNT1_TX register ****************/
+#define USB_COUNT1_TX_COUNT1_TX_Pos (0U)
+#define USB_COUNT1_TX_COUNT1_TX_Msk (0x3FFU << USB_COUNT1_TX_COUNT1_TX_Pos) /*!< 0x000003FF */
+#define USB_COUNT1_TX_COUNT1_TX USB_COUNT1_TX_COUNT1_TX_Msk /*!< Transmission Byte Count 1 */
+
+/***************** Bit definition for USB_COUNT2_TX register ****************/
+#define USB_COUNT2_TX_COUNT2_TX_Pos (0U)
+#define USB_COUNT2_TX_COUNT2_TX_Msk (0x3FFU << USB_COUNT2_TX_COUNT2_TX_Pos) /*!< 0x000003FF */
+#define USB_COUNT2_TX_COUNT2_TX USB_COUNT2_TX_COUNT2_TX_Msk /*!< Transmission Byte Count 2 */
+
+/***************** Bit definition for USB_COUNT3_TX register ****************/
+#define USB_COUNT3_TX_COUNT3_TX_Pos (0U)
+#define USB_COUNT3_TX_COUNT3_TX_Msk (0x3FFU << USB_COUNT3_TX_COUNT3_TX_Pos) /*!< 0x000003FF */
+#define USB_COUNT3_TX_COUNT3_TX USB_COUNT3_TX_COUNT3_TX_Msk /*!< Transmission Byte Count 3 */
+
+/***************** Bit definition for USB_COUNT4_TX register ****************/
+#define USB_COUNT4_TX_COUNT4_TX_Pos (0U)
+#define USB_COUNT4_TX_COUNT4_TX_Msk (0x3FFU << USB_COUNT4_TX_COUNT4_TX_Pos) /*!< 0x000003FF */
+#define USB_COUNT4_TX_COUNT4_TX USB_COUNT4_TX_COUNT4_TX_Msk /*!< Transmission Byte Count 4 */
+
+/***************** Bit definition for USB_COUNT5_TX register ****************/
+#define USB_COUNT5_TX_COUNT5_TX_Pos (0U)
+#define USB_COUNT5_TX_COUNT5_TX_Msk (0x3FFU << USB_COUNT5_TX_COUNT5_TX_Pos) /*!< 0x000003FF */
+#define USB_COUNT5_TX_COUNT5_TX USB_COUNT5_TX_COUNT5_TX_Msk /*!< Transmission Byte Count 5 */
+
+/***************** Bit definition for USB_COUNT6_TX register ****************/
+#define USB_COUNT6_TX_COUNT6_TX_Pos (0U)
+#define USB_COUNT6_TX_COUNT6_TX_Msk (0x3FFU << USB_COUNT6_TX_COUNT6_TX_Pos) /*!< 0x000003FF */
+#define USB_COUNT6_TX_COUNT6_TX USB_COUNT6_TX_COUNT6_TX_Msk /*!< Transmission Byte Count 6 */
+
+/***************** Bit definition for USB_COUNT7_TX register ****************/
+#define USB_COUNT7_TX_COUNT7_TX_Pos (0U)
+#define USB_COUNT7_TX_COUNT7_TX_Msk (0x3FFU << USB_COUNT7_TX_COUNT7_TX_Pos) /*!< 0x000003FF */
+#define USB_COUNT7_TX_COUNT7_TX USB_COUNT7_TX_COUNT7_TX_Msk /*!< Transmission Byte Count 7 */
+
+/*----------------------------------------------------------------------------*/
+
+/**************** Bit definition for USB_COUNT0_TX_0 register ***************/
+#define USB_COUNT0_TX_0_COUNT0_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 0 (low) */
+
+/**************** Bit definition for USB_COUNT0_TX_1 register ***************/
+#define USB_COUNT0_TX_1_COUNT0_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 0 (high) */
+
+/**************** Bit definition for USB_COUNT1_TX_0 register ***************/
+#define USB_COUNT1_TX_0_COUNT1_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 1 (low) */
+
+/**************** Bit definition for USB_COUNT1_TX_1 register ***************/
+#define USB_COUNT1_TX_1_COUNT1_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 1 (high) */
+
+/**************** Bit definition for USB_COUNT2_TX_0 register ***************/
+#define USB_COUNT2_TX_0_COUNT2_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 2 (low) */
+
+/**************** Bit definition for USB_COUNT2_TX_1 register ***************/
+#define USB_COUNT2_TX_1_COUNT2_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 2 (high) */
+
+/**************** Bit definition for USB_COUNT3_TX_0 register ***************/
+#define USB_COUNT3_TX_0_COUNT3_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 3 (low) */
+
+/**************** Bit definition for USB_COUNT3_TX_1 register ***************/
+#define USB_COUNT3_TX_1_COUNT3_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 3 (high) */
+
+/**************** Bit definition for USB_COUNT4_TX_0 register ***************/
+#define USB_COUNT4_TX_0_COUNT4_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 4 (low) */
+
+/**************** Bit definition for USB_COUNT4_TX_1 register ***************/
+#define USB_COUNT4_TX_1_COUNT4_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 4 (high) */
+
+/**************** Bit definition for USB_COUNT5_TX_0 register ***************/
+#define USB_COUNT5_TX_0_COUNT5_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 5 (low) */
+
+/**************** Bit definition for USB_COUNT5_TX_1 register ***************/
+#define USB_COUNT5_TX_1_COUNT5_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 5 (high) */
+
+/**************** Bit definition for USB_COUNT6_TX_0 register ***************/
+#define USB_COUNT6_TX_0_COUNT6_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 6 (low) */
+
+/**************** Bit definition for USB_COUNT6_TX_1 register ***************/
+#define USB_COUNT6_TX_1_COUNT6_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 6 (high) */
+
+/**************** Bit definition for USB_COUNT7_TX_0 register ***************/
+#define USB_COUNT7_TX_0_COUNT7_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 7 (low) */
+
+/**************** Bit definition for USB_COUNT7_TX_1 register ***************/
+#define USB_COUNT7_TX_1_COUNT7_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 7 (high) */
+
+/*----------------------------------------------------------------------------*/
+
+/***************** Bit definition for USB_ADDR0_RX register *****************/
+#define USB_ADDR0_RX_ADDR0_RX_Pos (1U)
+#define USB_ADDR0_RX_ADDR0_RX_Msk (0x7FFFU << USB_ADDR0_RX_ADDR0_RX_Pos) /*!< 0x0000FFFE */
+#define USB_ADDR0_RX_ADDR0_RX USB_ADDR0_RX_ADDR0_RX_Msk /*!< Reception Buffer Address 0 */
+
+/***************** Bit definition for USB_ADDR1_RX register *****************/
+#define USB_ADDR1_RX_ADDR1_RX_Pos (1U)
+#define USB_ADDR1_RX_ADDR1_RX_Msk (0x7FFFU << USB_ADDR1_RX_ADDR1_RX_Pos) /*!< 0x0000FFFE */
+#define USB_ADDR1_RX_ADDR1_RX USB_ADDR1_RX_ADDR1_RX_Msk /*!< Reception Buffer Address 1 */
+
+/***************** Bit definition for USB_ADDR2_RX register *****************/
+#define USB_ADDR2_RX_ADDR2_RX_Pos (1U)
+#define USB_ADDR2_RX_ADDR2_RX_Msk (0x7FFFU << USB_ADDR2_RX_ADDR2_RX_Pos) /*!< 0x0000FFFE */
+#define USB_ADDR2_RX_ADDR2_RX USB_ADDR2_RX_ADDR2_RX_Msk /*!< Reception Buffer Address 2 */
+
+/***************** Bit definition for USB_ADDR3_RX register *****************/
+#define USB_ADDR3_RX_ADDR3_RX_Pos (1U)
+#define USB_ADDR3_RX_ADDR3_RX_Msk (0x7FFFU << USB_ADDR3_RX_ADDR3_RX_Pos) /*!< 0x0000FFFE */
+#define USB_ADDR3_RX_ADDR3_RX USB_ADDR3_RX_ADDR3_RX_Msk /*!< Reception Buffer Address 3 */
+
+/***************** Bit definition for USB_ADDR4_RX register *****************/
+#define USB_ADDR4_RX_ADDR4_RX_Pos (1U)
+#define USB_ADDR4_RX_ADDR4_RX_Msk (0x7FFFU << USB_ADDR4_RX_ADDR4_RX_Pos) /*!< 0x0000FFFE */
+#define USB_ADDR4_RX_ADDR4_RX USB_ADDR4_RX_ADDR4_RX_Msk /*!< Reception Buffer Address 4 */
+
+/***************** Bit definition for USB_ADDR5_RX register *****************/
+#define USB_ADDR5_RX_ADDR5_RX_Pos (1U)
+#define USB_ADDR5_RX_ADDR5_RX_Msk (0x7FFFU << USB_ADDR5_RX_ADDR5_RX_Pos) /*!< 0x0000FFFE */
+#define USB_ADDR5_RX_ADDR5_RX USB_ADDR5_RX_ADDR5_RX_Msk /*!< Reception Buffer Address 5 */
+
+/***************** Bit definition for USB_ADDR6_RX register *****************/
+#define USB_ADDR6_RX_ADDR6_RX_Pos (1U)
+#define USB_ADDR6_RX_ADDR6_RX_Msk (0x7FFFU << USB_ADDR6_RX_ADDR6_RX_Pos) /*!< 0x0000FFFE */
+#define USB_ADDR6_RX_ADDR6_RX USB_ADDR6_RX_ADDR6_RX_Msk /*!< Reception Buffer Address 6 */
+
+/***************** Bit definition for USB_ADDR7_RX register *****************/
+#define USB_ADDR7_RX_ADDR7_RX_Pos (1U)
+#define USB_ADDR7_RX_ADDR7_RX_Msk (0x7FFFU << USB_ADDR7_RX_ADDR7_RX_Pos) /*!< 0x0000FFFE */
+#define USB_ADDR7_RX_ADDR7_RX USB_ADDR7_RX_ADDR7_RX_Msk /*!< Reception Buffer Address 7 */
+
+/*----------------------------------------------------------------------------*/
+
+/***************** Bit definition for USB_COUNT0_RX register ****************/
+#define USB_COUNT0_RX_COUNT0_RX_Pos (0U)
+#define USB_COUNT0_RX_COUNT0_RX_Msk (0x3FFU << USB_COUNT0_RX_COUNT0_RX_Pos) /*!< 0x000003FF */
+#define USB_COUNT0_RX_COUNT0_RX USB_COUNT0_RX_COUNT0_RX_Msk /*!< Reception Byte Count */
+
+#define USB_COUNT0_RX_NUM_BLOCK_Pos (10U)
+#define USB_COUNT0_RX_NUM_BLOCK_Msk (0x1FU << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
+#define USB_COUNT0_RX_NUM_BLOCK USB_COUNT0_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
+#define USB_COUNT0_RX_NUM_BLOCK_0 (0x01U << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
+#define USB_COUNT0_RX_NUM_BLOCK_1 (0x02U << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
+#define USB_COUNT0_RX_NUM_BLOCK_2 (0x04U << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
+#define USB_COUNT0_RX_NUM_BLOCK_3 (0x08U << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
+#define USB_COUNT0_RX_NUM_BLOCK_4 (0x10U << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
+
+#define USB_COUNT0_RX_BLSIZE_Pos (15U)
+#define USB_COUNT0_RX_BLSIZE_Msk (0x1U << USB_COUNT0_RX_BLSIZE_Pos) /*!< 0x00008000 */
+#define USB_COUNT0_RX_BLSIZE USB_COUNT0_RX_BLSIZE_Msk /*!< BLock SIZE */
+
+/***************** Bit definition for USB_COUNT1_RX register ****************/
+#define USB_COUNT1_RX_COUNT1_RX_Pos (0U)
+#define USB_COUNT1_RX_COUNT1_RX_Msk (0x3FFU << USB_COUNT1_RX_COUNT1_RX_Pos) /*!< 0x000003FF */
+#define USB_COUNT1_RX_COUNT1_RX USB_COUNT1_RX_COUNT1_RX_Msk /*!< Reception Byte Count */
+
+#define USB_COUNT1_RX_NUM_BLOCK_Pos (10U)
+#define USB_COUNT1_RX_NUM_BLOCK_Msk (0x1FU << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
+#define USB_COUNT1_RX_NUM_BLOCK USB_COUNT1_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
+#define USB_COUNT1_RX_NUM_BLOCK_0 (0x01U << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
+#define USB_COUNT1_RX_NUM_BLOCK_1 (0x02U << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
+#define USB_COUNT1_RX_NUM_BLOCK_2 (0x04U << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
+#define USB_COUNT1_RX_NUM_BLOCK_3 (0x08U << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
+#define USB_COUNT1_RX_NUM_BLOCK_4 (0x10U << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
+
+#define USB_COUNT1_RX_BLSIZE_Pos (15U)
+#define USB_COUNT1_RX_BLSIZE_Msk (0x1U << USB_COUNT1_RX_BLSIZE_Pos) /*!< 0x00008000 */
+#define USB_COUNT1_RX_BLSIZE USB_COUNT1_RX_BLSIZE_Msk /*!< BLock SIZE */
+
+/***************** Bit definition for USB_COUNT2_RX register ****************/
+#define USB_COUNT2_RX_COUNT2_RX_Pos (0U)
+#define USB_COUNT2_RX_COUNT2_RX_Msk (0x3FFU << USB_COUNT2_RX_COUNT2_RX_Pos) /*!< 0x000003FF */
+#define USB_COUNT2_RX_COUNT2_RX USB_COUNT2_RX_COUNT2_RX_Msk /*!< Reception Byte Count */
+
+#define USB_COUNT2_RX_NUM_BLOCK_Pos (10U)
+#define USB_COUNT2_RX_NUM_BLOCK_Msk (0x1FU << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
+#define USB_COUNT2_RX_NUM_BLOCK USB_COUNT2_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
+#define USB_COUNT2_RX_NUM_BLOCK_0 (0x01U << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
+#define USB_COUNT2_RX_NUM_BLOCK_1 (0x02U << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
+#define USB_COUNT2_RX_NUM_BLOCK_2 (0x04U << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
+#define USB_COUNT2_RX_NUM_BLOCK_3 (0x08U << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
+#define USB_COUNT2_RX_NUM_BLOCK_4 (0x10U << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
+
+#define USB_COUNT2_RX_BLSIZE_Pos (15U)
+#define USB_COUNT2_RX_BLSIZE_Msk (0x1U << USB_COUNT2_RX_BLSIZE_Pos) /*!< 0x00008000 */
+#define USB_COUNT2_RX_BLSIZE USB_COUNT2_RX_BLSIZE_Msk /*!< BLock SIZE */
+
+/***************** Bit definition for USB_COUNT3_RX register ****************/
+#define USB_COUNT3_RX_COUNT3_RX_Pos (0U)
+#define USB_COUNT3_RX_COUNT3_RX_Msk (0x3FFU << USB_COUNT3_RX_COUNT3_RX_Pos) /*!< 0x000003FF */
+#define USB_COUNT3_RX_COUNT3_RX USB_COUNT3_RX_COUNT3_RX_Msk /*!< Reception Byte Count */
+
+#define USB_COUNT3_RX_NUM_BLOCK_Pos (10U)
+#define USB_COUNT3_RX_NUM_BLOCK_Msk (0x1FU << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
+#define USB_COUNT3_RX_NUM_BLOCK USB_COUNT3_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
+#define USB_COUNT3_RX_NUM_BLOCK_0 (0x01U << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
+#define USB_COUNT3_RX_NUM_BLOCK_1 (0x02U << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
+#define USB_COUNT3_RX_NUM_BLOCK_2 (0x04U << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
+#define USB_COUNT3_RX_NUM_BLOCK_3 (0x08U << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
+#define USB_COUNT3_RX_NUM_BLOCK_4 (0x10U << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
+
+#define USB_COUNT3_RX_BLSIZE_Pos (15U)
+#define USB_COUNT3_RX_BLSIZE_Msk (0x1U << USB_COUNT3_RX_BLSIZE_Pos) /*!< 0x00008000 */
+#define USB_COUNT3_RX_BLSIZE USB_COUNT3_RX_BLSIZE_Msk /*!< BLock SIZE */
+
+/***************** Bit definition for USB_COUNT4_RX register ****************/
+#define USB_COUNT4_RX_COUNT4_RX_Pos (0U)
+#define USB_COUNT4_RX_COUNT4_RX_Msk (0x3FFU << USB_COUNT4_RX_COUNT4_RX_Pos) /*!< 0x000003FF */
+#define USB_COUNT4_RX_COUNT4_RX USB_COUNT4_RX_COUNT4_RX_Msk /*!< Reception Byte Count */
+
+#define USB_COUNT4_RX_NUM_BLOCK_Pos (10U)
+#define USB_COUNT4_RX_NUM_BLOCK_Msk (0x1FU << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
+#define USB_COUNT4_RX_NUM_BLOCK USB_COUNT4_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
+#define USB_COUNT4_RX_NUM_BLOCK_0 (0x01U << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
+#define USB_COUNT4_RX_NUM_BLOCK_1 (0x02U << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
+#define USB_COUNT4_RX_NUM_BLOCK_2 (0x04U << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
+#define USB_COUNT4_RX_NUM_BLOCK_3 (0x08U << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
+#define USB_COUNT4_RX_NUM_BLOCK_4 (0x10U << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
+
+#define USB_COUNT4_RX_BLSIZE_Pos (15U)
+#define USB_COUNT4_RX_BLSIZE_Msk (0x1U << USB_COUNT4_RX_BLSIZE_Pos) /*!< 0x00008000 */
+#define USB_COUNT4_RX_BLSIZE USB_COUNT4_RX_BLSIZE_Msk /*!< BLock SIZE */
+
+/***************** Bit definition for USB_COUNT5_RX register ****************/
+#define USB_COUNT5_RX_COUNT5_RX_Pos (0U)
+#define USB_COUNT5_RX_COUNT5_RX_Msk (0x3FFU << USB_COUNT5_RX_COUNT5_RX_Pos) /*!< 0x000003FF */
+#define USB_COUNT5_RX_COUNT5_RX USB_COUNT5_RX_COUNT5_RX_Msk /*!< Reception Byte Count */
+
+#define USB_COUNT5_RX_NUM_BLOCK_Pos (10U)
+#define USB_COUNT5_RX_NUM_BLOCK_Msk (0x1FU << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
+#define USB_COUNT5_RX_NUM_BLOCK USB_COUNT5_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
+#define USB_COUNT5_RX_NUM_BLOCK_0 (0x01U << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
+#define USB_COUNT5_RX_NUM_BLOCK_1 (0x02U << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
+#define USB_COUNT5_RX_NUM_BLOCK_2 (0x04U << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
+#define USB_COUNT5_RX_NUM_BLOCK_3 (0x08U << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
+#define USB_COUNT5_RX_NUM_BLOCK_4 (0x10U << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
+
+#define USB_COUNT5_RX_BLSIZE_Pos (15U)
+#define USB_COUNT5_RX_BLSIZE_Msk (0x1U << USB_COUNT5_RX_BLSIZE_Pos) /*!< 0x00008000 */
+#define USB_COUNT5_RX_BLSIZE USB_COUNT5_RX_BLSIZE_Msk /*!< BLock SIZE */
+
+/***************** Bit definition for USB_COUNT6_RX register ****************/
+#define USB_COUNT6_RX_COUNT6_RX_Pos (0U)
+#define USB_COUNT6_RX_COUNT6_RX_Msk (0x3FFU << USB_COUNT6_RX_COUNT6_RX_Pos) /*!< 0x000003FF */
+#define USB_COUNT6_RX_COUNT6_RX USB_COUNT6_RX_COUNT6_RX_Msk /*!< Reception Byte Count */
+
+#define USB_COUNT6_RX_NUM_BLOCK_Pos (10U)
+#define USB_COUNT6_RX_NUM_BLOCK_Msk (0x1FU << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
+#define USB_COUNT6_RX_NUM_BLOCK USB_COUNT6_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
+#define USB_COUNT6_RX_NUM_BLOCK_0 (0x01U << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
+#define USB_COUNT6_RX_NUM_BLOCK_1 (0x02U << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
+#define USB_COUNT6_RX_NUM_BLOCK_2 (0x04U << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
+#define USB_COUNT6_RX_NUM_BLOCK_3 (0x08U << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
+#define USB_COUNT6_RX_NUM_BLOCK_4 (0x10U << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
+
+#define USB_COUNT6_RX_BLSIZE_Pos (15U)
+#define USB_COUNT6_RX_BLSIZE_Msk (0x1U << USB_COUNT6_RX_BLSIZE_Pos) /*!< 0x00008000 */
+#define USB_COUNT6_RX_BLSIZE USB_COUNT6_RX_BLSIZE_Msk /*!< BLock SIZE */
+
+/***************** Bit definition for USB_COUNT7_RX register ****************/
+#define USB_COUNT7_RX_COUNT7_RX_Pos (0U)
+#define USB_COUNT7_RX_COUNT7_RX_Msk (0x3FFU << USB_COUNT7_RX_COUNT7_RX_Pos) /*!< 0x000003FF */
+#define USB_COUNT7_RX_COUNT7_RX USB_COUNT7_RX_COUNT7_RX_Msk /*!< Reception Byte Count */
+
+#define USB_COUNT7_RX_NUM_BLOCK_Pos (10U)
+#define USB_COUNT7_RX_NUM_BLOCK_Msk (0x1FU << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
+#define USB_COUNT7_RX_NUM_BLOCK USB_COUNT7_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
+#define USB_COUNT7_RX_NUM_BLOCK_0 (0x01U << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
+#define USB_COUNT7_RX_NUM_BLOCK_1 (0x02U << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
+#define USB_COUNT7_RX_NUM_BLOCK_2 (0x04U << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
+#define USB_COUNT7_RX_NUM_BLOCK_3 (0x08U << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
+#define USB_COUNT7_RX_NUM_BLOCK_4 (0x10U << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
+
+#define USB_COUNT7_RX_BLSIZE_Pos (15U)
+#define USB_COUNT7_RX_BLSIZE_Msk (0x1U << USB_COUNT7_RX_BLSIZE_Pos) /*!< 0x00008000 */
+#define USB_COUNT7_RX_BLSIZE USB_COUNT7_RX_BLSIZE_Msk /*!< BLock SIZE */
+
+/*----------------------------------------------------------------------------*/
+
+/**************** Bit definition for USB_COUNT0_RX_0 register ***************/
+#define USB_COUNT0_RX_0_COUNT0_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */
+
+#define USB_COUNT0_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
+#define USB_COUNT0_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */
+#define USB_COUNT0_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */
+#define USB_COUNT0_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */
+#define USB_COUNT0_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */
+#define USB_COUNT0_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */
+
+#define USB_COUNT0_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */
+
+/**************** Bit definition for USB_COUNT0_RX_1 register ***************/
+#define USB_COUNT0_RX_1_COUNT0_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */
+
+#define USB_COUNT0_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
+#define USB_COUNT0_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 1 */
+#define USB_COUNT0_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */
+#define USB_COUNT0_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */
+#define USB_COUNT0_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */
+#define USB_COUNT0_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */
+
+#define USB_COUNT0_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */
+
+/**************** Bit definition for USB_COUNT1_RX_0 register ***************/
+#define USB_COUNT1_RX_0_COUNT1_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */
+
+#define USB_COUNT1_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
+#define USB_COUNT1_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */
+#define USB_COUNT1_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */
+#define USB_COUNT1_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */
+#define USB_COUNT1_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */
+#define USB_COUNT1_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */
+
+#define USB_COUNT1_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */
+
+/**************** Bit definition for USB_COUNT1_RX_1 register ***************/
+#define USB_COUNT1_RX_1_COUNT1_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */
+
+#define USB_COUNT1_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
+#define USB_COUNT1_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */
+#define USB_COUNT1_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */
+#define USB_COUNT1_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */
+#define USB_COUNT1_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */
+#define USB_COUNT1_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */
+
+#define USB_COUNT1_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */
+
+/**************** Bit definition for USB_COUNT2_RX_0 register ***************/
+#define USB_COUNT2_RX_0_COUNT2_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */
+
+#define USB_COUNT2_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
+#define USB_COUNT2_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */
+#define USB_COUNT2_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */
+#define USB_COUNT2_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */
+#define USB_COUNT2_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */
+#define USB_COUNT2_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */
+
+#define USB_COUNT2_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */
+
+/**************** Bit definition for USB_COUNT2_RX_1 register ***************/
+#define USB_COUNT2_RX_1_COUNT2_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */
+
+#define USB_COUNT2_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
+#define USB_COUNT2_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */
+#define USB_COUNT2_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */
+#define USB_COUNT2_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */
+#define USB_COUNT2_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */
+#define USB_COUNT2_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */
+
+#define USB_COUNT2_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */
+
+/**************** Bit definition for USB_COUNT3_RX_0 register ***************/
+#define USB_COUNT3_RX_0_COUNT3_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */
+
+#define USB_COUNT3_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
+#define USB_COUNT3_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */
+#define USB_COUNT3_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */
+#define USB_COUNT3_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */
+#define USB_COUNT3_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */
+#define USB_COUNT3_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */
+
+#define USB_COUNT3_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */
+
+/**************** Bit definition for USB_COUNT3_RX_1 register ***************/
+#define USB_COUNT3_RX_1_COUNT3_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */
+
+#define USB_COUNT3_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
+#define USB_COUNT3_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */
+#define USB_COUNT3_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */
+#define USB_COUNT3_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */
+#define USB_COUNT3_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */
+#define USB_COUNT3_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */
+
+#define USB_COUNT3_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */
+
+/**************** Bit definition for USB_COUNT4_RX_0 register ***************/
+#define USB_COUNT4_RX_0_COUNT4_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */
+
+#define USB_COUNT4_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
+#define USB_COUNT4_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */
+#define USB_COUNT4_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */
+#define USB_COUNT4_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */
+#define USB_COUNT4_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */
+#define USB_COUNT4_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */
+
+#define USB_COUNT4_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */
+
+/**************** Bit definition for USB_COUNT4_RX_1 register ***************/
+#define USB_COUNT4_RX_1_COUNT4_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */
+
+#define USB_COUNT4_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
+#define USB_COUNT4_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */
+#define USB_COUNT4_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */
+#define USB_COUNT4_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */
+#define USB_COUNT4_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */
+#define USB_COUNT4_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */
+
+#define USB_COUNT4_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */
+
+/**************** Bit definition for USB_COUNT5_RX_0 register ***************/
+#define USB_COUNT5_RX_0_COUNT5_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */
+
+#define USB_COUNT5_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
+#define USB_COUNT5_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */
+#define USB_COUNT5_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */
+#define USB_COUNT5_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */
+#define USB_COUNT5_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */
+#define USB_COUNT5_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */
+
+#define USB_COUNT5_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */
+
+/**************** Bit definition for USB_COUNT5_RX_1 register ***************/
+#define USB_COUNT5_RX_1_COUNT5_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */
+
+#define USB_COUNT5_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
+#define USB_COUNT5_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */
+#define USB_COUNT5_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */
+#define USB_COUNT5_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */
+#define USB_COUNT5_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */
+#define USB_COUNT5_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */
+
+#define USB_COUNT5_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */
+
+/*************** Bit definition for USB_COUNT6_RX_0 register ***************/
+#define USB_COUNT6_RX_0_COUNT6_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */
+
+#define USB_COUNT6_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
+#define USB_COUNT6_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */
+#define USB_COUNT6_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */
+#define USB_COUNT6_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */
+#define USB_COUNT6_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */
+#define USB_COUNT6_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */
+
+#define USB_COUNT6_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */
+
+/**************** Bit definition for USB_COUNT6_RX_1 register ***************/
+#define USB_COUNT6_RX_1_COUNT6_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */
+
+#define USB_COUNT6_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
+#define USB_COUNT6_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */
+#define USB_COUNT6_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */
+#define USB_COUNT6_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */
+#define USB_COUNT6_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */
+#define USB_COUNT6_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */
+
+#define USB_COUNT6_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */
+
+/*************** Bit definition for USB_COUNT7_RX_0 register ****************/
+#define USB_COUNT7_RX_0_COUNT7_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */
+
+#define USB_COUNT7_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
+#define USB_COUNT7_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */
+#define USB_COUNT7_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */
+#define USB_COUNT7_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */
+#define USB_COUNT7_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */
+#define USB_COUNT7_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */
+
+#define USB_COUNT7_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */
+
+/*************** Bit definition for USB_COUNT7_RX_1 register ****************/
+#define USB_COUNT7_RX_1_COUNT7_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */
+
+#define USB_COUNT7_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
+#define USB_COUNT7_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */
+#define USB_COUNT7_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */
+#define USB_COUNT7_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */
+#define USB_COUNT7_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */
+#define USB_COUNT7_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */
+
+#define USB_COUNT7_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */
+
+/******************************************************************************/
+/* */
+/* Controller Area Network */
+/* */
+/******************************************************************************/
+
+/*!< CAN control and status registers */
+/******************* Bit definition for CAN_MCR register ********************/
+#define CAN_MCR_INRQ_Pos (0U)
+#define CAN_MCR_INRQ_Msk (0x1U << CAN_MCR_INRQ_Pos) /*!< 0x00000001 */
+#define CAN_MCR_INRQ CAN_MCR_INRQ_Msk /*!< Initialization Request */
+#define CAN_MCR_SLEEP_Pos (1U)
+#define CAN_MCR_SLEEP_Msk (0x1U << CAN_MCR_SLEEP_Pos) /*!< 0x00000002 */
+#define CAN_MCR_SLEEP CAN_MCR_SLEEP_Msk /*!< Sleep Mode Request */
+#define CAN_MCR_TXFP_Pos (2U)
+#define CAN_MCR_TXFP_Msk (0x1U << CAN_MCR_TXFP_Pos) /*!< 0x00000004 */
+#define CAN_MCR_TXFP CAN_MCR_TXFP_Msk /*!< Transmit FIFO Priority */
+#define CAN_MCR_RFLM_Pos (3U)
+#define CAN_MCR_RFLM_Msk (0x1U << CAN_MCR_RFLM_Pos) /*!< 0x00000008 */
+#define CAN_MCR_RFLM CAN_MCR_RFLM_Msk /*!< Receive FIFO Locked Mode */
+#define CAN_MCR_NART_Pos (4U)
+#define CAN_MCR_NART_Msk (0x1U << CAN_MCR_NART_Pos) /*!< 0x00000010 */
+#define CAN_MCR_NART CAN_MCR_NART_Msk /*!< No Automatic Retransmission */
+#define CAN_MCR_AWUM_Pos (5U)
+#define CAN_MCR_AWUM_Msk (0x1U << CAN_MCR_AWUM_Pos) /*!< 0x00000020 */
+#define CAN_MCR_AWUM CAN_MCR_AWUM_Msk /*!< Automatic Wakeup Mode */
+#define CAN_MCR_ABOM_Pos (6U)
+#define CAN_MCR_ABOM_Msk (0x1U << CAN_MCR_ABOM_Pos) /*!< 0x00000040 */
+#define CAN_MCR_ABOM CAN_MCR_ABOM_Msk /*!< Automatic Bus-Off Management */
+#define CAN_MCR_TTCM_Pos (7U)
+#define CAN_MCR_TTCM_Msk (0x1U << CAN_MCR_TTCM_Pos) /*!< 0x00000080 */
+#define CAN_MCR_TTCM CAN_MCR_TTCM_Msk /*!< Time Triggered Communication Mode */
+#define CAN_MCR_RESET_Pos (15U)
+#define CAN_MCR_RESET_Msk (0x1U << CAN_MCR_RESET_Pos) /*!< 0x00008000 */
+#define CAN_MCR_RESET CAN_MCR_RESET_Msk /*!< CAN software master reset */
+#define CAN_MCR_DBF_Pos (16U)
+#define CAN_MCR_DBF_Msk (0x1U << CAN_MCR_DBF_Pos) /*!< 0x00010000 */
+#define CAN_MCR_DBF CAN_MCR_DBF_Msk /*!< CAN Debug freeze */
+
+/******************* Bit definition for CAN_MSR register ********************/
+#define CAN_MSR_INAK_Pos (0U)
+#define CAN_MSR_INAK_Msk (0x1U << CAN_MSR_INAK_Pos) /*!< 0x00000001 */
+#define CAN_MSR_INAK CAN_MSR_INAK_Msk /*!< Initialization Acknowledge */
+#define CAN_MSR_SLAK_Pos (1U)
+#define CAN_MSR_SLAK_Msk (0x1U << CAN_MSR_SLAK_Pos) /*!< 0x00000002 */
+#define CAN_MSR_SLAK CAN_MSR_SLAK_Msk /*!< Sleep Acknowledge */
+#define CAN_MSR_ERRI_Pos (2U)
+#define CAN_MSR_ERRI_Msk (0x1U << CAN_MSR_ERRI_Pos) /*!< 0x00000004 */
+#define CAN_MSR_ERRI CAN_MSR_ERRI_Msk /*!< Error Interrupt */
+#define CAN_MSR_WKUI_Pos (3U)
+#define CAN_MSR_WKUI_Msk (0x1U << CAN_MSR_WKUI_Pos) /*!< 0x00000008 */
+#define CAN_MSR_WKUI CAN_MSR_WKUI_Msk /*!< Wakeup Interrupt */
+#define CAN_MSR_SLAKI_Pos (4U)
+#define CAN_MSR_SLAKI_Msk (0x1U << CAN_MSR_SLAKI_Pos) /*!< 0x00000010 */
+#define CAN_MSR_SLAKI CAN_MSR_SLAKI_Msk /*!< Sleep Acknowledge Interrupt */
+#define CAN_MSR_TXM_Pos (8U)
+#define CAN_MSR_TXM_Msk (0x1U << CAN_MSR_TXM_Pos) /*!< 0x00000100 */
+#define CAN_MSR_TXM CAN_MSR_TXM_Msk /*!< Transmit Mode */
+#define CAN_MSR_RXM_Pos (9U)
+#define CAN_MSR_RXM_Msk (0x1U << CAN_MSR_RXM_Pos) /*!< 0x00000200 */
+#define CAN_MSR_RXM CAN_MSR_RXM_Msk /*!< Receive Mode */
+#define CAN_MSR_SAMP_Pos (10U)
+#define CAN_MSR_SAMP_Msk (0x1U << CAN_MSR_SAMP_Pos) /*!< 0x00000400 */
+#define CAN_MSR_SAMP CAN_MSR_SAMP_Msk /*!< Last Sample Point */
+#define CAN_MSR_RX_Pos (11U)
+#define CAN_MSR_RX_Msk (0x1U << CAN_MSR_RX_Pos) /*!< 0x00000800 */
+#define CAN_MSR_RX CAN_MSR_RX_Msk /*!< CAN Rx Signal */
+
+/******************* Bit definition for CAN_TSR register ********************/
+#define CAN_TSR_RQCP0_Pos (0U)
+#define CAN_TSR_RQCP0_Msk (0x1U << CAN_TSR_RQCP0_Pos) /*!< 0x00000001 */
+#define CAN_TSR_RQCP0 CAN_TSR_RQCP0_Msk /*!< Request Completed Mailbox0 */
+#define CAN_TSR_TXOK0_Pos (1U)
+#define CAN_TSR_TXOK0_Msk (0x1U << CAN_TSR_TXOK0_Pos) /*!< 0x00000002 */
+#define CAN_TSR_TXOK0 CAN_TSR_TXOK0_Msk /*!< Transmission OK of Mailbox0 */
+#define CAN_TSR_ALST0_Pos (2U)
+#define CAN_TSR_ALST0_Msk (0x1U << CAN_TSR_ALST0_Pos) /*!< 0x00000004 */
+#define CAN_TSR_ALST0 CAN_TSR_ALST0_Msk /*!< Arbitration Lost for Mailbox0 */
+#define CAN_TSR_TERR0_Pos (3U)
+#define CAN_TSR_TERR0_Msk (0x1U << CAN_TSR_TERR0_Pos) /*!< 0x00000008 */
+#define CAN_TSR_TERR0 CAN_TSR_TERR0_Msk /*!< Transmission Error of Mailbox0 */
+#define CAN_TSR_ABRQ0_Pos (7U)
+#define CAN_TSR_ABRQ0_Msk (0x1U << CAN_TSR_ABRQ0_Pos) /*!< 0x00000080 */
+#define CAN_TSR_ABRQ0 CAN_TSR_ABRQ0_Msk /*!< Abort Request for Mailbox0 */
+#define CAN_TSR_RQCP1_Pos (8U)
+#define CAN_TSR_RQCP1_Msk (0x1U << CAN_TSR_RQCP1_Pos) /*!< 0x00000100 */
+#define CAN_TSR_RQCP1 CAN_TSR_RQCP1_Msk /*!< Request Completed Mailbox1 */
+#define CAN_TSR_TXOK1_Pos (9U)
+#define CAN_TSR_TXOK1_Msk (0x1U << CAN_TSR_TXOK1_Pos) /*!< 0x00000200 */
+#define CAN_TSR_TXOK1 CAN_TSR_TXOK1_Msk /*!< Transmission OK of Mailbox1 */
+#define CAN_TSR_ALST1_Pos (10U)
+#define CAN_TSR_ALST1_Msk (0x1U << CAN_TSR_ALST1_Pos) /*!< 0x00000400 */
+#define CAN_TSR_ALST1 CAN_TSR_ALST1_Msk /*!< Arbitration Lost for Mailbox1 */
+#define CAN_TSR_TERR1_Pos (11U)
+#define CAN_TSR_TERR1_Msk (0x1U << CAN_TSR_TERR1_Pos) /*!< 0x00000800 */
+#define CAN_TSR_TERR1 CAN_TSR_TERR1_Msk /*!< Transmission Error of Mailbox1 */
+#define CAN_TSR_ABRQ1_Pos (15U)
+#define CAN_TSR_ABRQ1_Msk (0x1U << CAN_TSR_ABRQ1_Pos) /*!< 0x00008000 */
+#define CAN_TSR_ABRQ1 CAN_TSR_ABRQ1_Msk /*!< Abort Request for Mailbox 1 */
+#define CAN_TSR_RQCP2_Pos (16U)
+#define CAN_TSR_RQCP2_Msk (0x1U << CAN_TSR_RQCP2_Pos) /*!< 0x00010000 */
+#define CAN_TSR_RQCP2 CAN_TSR_RQCP2_Msk /*!< Request Completed Mailbox2 */
+#define CAN_TSR_TXOK2_Pos (17U)
+#define CAN_TSR_TXOK2_Msk (0x1U << CAN_TSR_TXOK2_Pos) /*!< 0x00020000 */
+#define CAN_TSR_TXOK2 CAN_TSR_TXOK2_Msk /*!< Transmission OK of Mailbox 2 */
+#define CAN_TSR_ALST2_Pos (18U)
+#define CAN_TSR_ALST2_Msk (0x1U << CAN_TSR_ALST2_Pos) /*!< 0x00040000 */
+#define CAN_TSR_ALST2 CAN_TSR_ALST2_Msk /*!< Arbitration Lost for mailbox 2 */
+#define CAN_TSR_TERR2_Pos (19U)
+#define CAN_TSR_TERR2_Msk (0x1U << CAN_TSR_TERR2_Pos) /*!< 0x00080000 */
+#define CAN_TSR_TERR2 CAN_TSR_TERR2_Msk /*!< Transmission Error of Mailbox 2 */
+#define CAN_TSR_ABRQ2_Pos (23U)
+#define CAN_TSR_ABRQ2_Msk (0x1U << CAN_TSR_ABRQ2_Pos) /*!< 0x00800000 */
+#define CAN_TSR_ABRQ2 CAN_TSR_ABRQ2_Msk /*!< Abort Request for Mailbox 2 */
+#define CAN_TSR_CODE_Pos (24U)
+#define CAN_TSR_CODE_Msk (0x3U << CAN_TSR_CODE_Pos) /*!< 0x03000000 */
+#define CAN_TSR_CODE CAN_TSR_CODE_Msk /*!< Mailbox Code */
+
+#define CAN_TSR_TME_Pos (26U)
+#define CAN_TSR_TME_Msk (0x7U << CAN_TSR_TME_Pos) /*!< 0x1C000000 */
+#define CAN_TSR_TME CAN_TSR_TME_Msk /*!< TME[2:0] bits */
+#define CAN_TSR_TME0_Pos (26U)
+#define CAN_TSR_TME0_Msk (0x1U << CAN_TSR_TME0_Pos) /*!< 0x04000000 */
+#define CAN_TSR_TME0 CAN_TSR_TME0_Msk /*!< Transmit Mailbox 0 Empty */
+#define CAN_TSR_TME1_Pos (27U)
+#define CAN_TSR_TME1_Msk (0x1U << CAN_TSR_TME1_Pos) /*!< 0x08000000 */
+#define CAN_TSR_TME1 CAN_TSR_TME1_Msk /*!< Transmit Mailbox 1 Empty */
+#define CAN_TSR_TME2_Pos (28U)
+#define CAN_TSR_TME2_Msk (0x1U << CAN_TSR_TME2_Pos) /*!< 0x10000000 */
+#define CAN_TSR_TME2 CAN_TSR_TME2_Msk /*!< Transmit Mailbox 2 Empty */
+
+#define CAN_TSR_LOW_Pos (29U)
+#define CAN_TSR_LOW_Msk (0x7U << CAN_TSR_LOW_Pos) /*!< 0xE0000000 */
+#define CAN_TSR_LOW CAN_TSR_LOW_Msk /*!< LOW[2:0] bits */
+#define CAN_TSR_LOW0_Pos (29U)
+#define CAN_TSR_LOW0_Msk (0x1U << CAN_TSR_LOW0_Pos) /*!< 0x20000000 */
+#define CAN_TSR_LOW0 CAN_TSR_LOW0_Msk /*!< Lowest Priority Flag for Mailbox 0 */
+#define CAN_TSR_LOW1_Pos (30U)
+#define CAN_TSR_LOW1_Msk (0x1U << CAN_TSR_LOW1_Pos) /*!< 0x40000000 */
+#define CAN_TSR_LOW1 CAN_TSR_LOW1_Msk /*!< Lowest Priority Flag for Mailbox 1 */
+#define CAN_TSR_LOW2_Pos (31U)
+#define CAN_TSR_LOW2_Msk (0x1U << CAN_TSR_LOW2_Pos) /*!< 0x80000000 */
+#define CAN_TSR_LOW2 CAN_TSR_LOW2_Msk /*!< Lowest Priority Flag for Mailbox 2 */
+
+/******************* Bit definition for CAN_RF0R register *******************/
+#define CAN_RF0R_FMP0_Pos (0U)
+#define CAN_RF0R_FMP0_Msk (0x3U << CAN_RF0R_FMP0_Pos) /*!< 0x00000003 */
+#define CAN_RF0R_FMP0 CAN_RF0R_FMP0_Msk /*!< FIFO 0 Message Pending */
+#define CAN_RF0R_FULL0_Pos (3U)
+#define CAN_RF0R_FULL0_Msk (0x1U << CAN_RF0R_FULL0_Pos) /*!< 0x00000008 */
+#define CAN_RF0R_FULL0 CAN_RF0R_FULL0_Msk /*!< FIFO 0 Full */
+#define CAN_RF0R_FOVR0_Pos (4U)
+#define CAN_RF0R_FOVR0_Msk (0x1U << CAN_RF0R_FOVR0_Pos) /*!< 0x00000010 */
+#define CAN_RF0R_FOVR0 CAN_RF0R_FOVR0_Msk /*!< FIFO 0 Overrun */
+#define CAN_RF0R_RFOM0_Pos (5U)
+#define CAN_RF0R_RFOM0_Msk (0x1U << CAN_RF0R_RFOM0_Pos) /*!< 0x00000020 */
+#define CAN_RF0R_RFOM0 CAN_RF0R_RFOM0_Msk /*!< Release FIFO 0 Output Mailbox */
+
+/******************* Bit definition for CAN_RF1R register *******************/
+#define CAN_RF1R_FMP1_Pos (0U)
+#define CAN_RF1R_FMP1_Msk (0x3U << CAN_RF1R_FMP1_Pos) /*!< 0x00000003 */
+#define CAN_RF1R_FMP1 CAN_RF1R_FMP1_Msk /*!< FIFO 1 Message Pending */
+#define CAN_RF1R_FULL1_Pos (3U)
+#define CAN_RF1R_FULL1_Msk (0x1U << CAN_RF1R_FULL1_Pos) /*!< 0x00000008 */
+#define CAN_RF1R_FULL1 CAN_RF1R_FULL1_Msk /*!< FIFO 1 Full */
+#define CAN_RF1R_FOVR1_Pos (4U)
+#define CAN_RF1R_FOVR1_Msk (0x1U << CAN_RF1R_FOVR1_Pos) /*!< 0x00000010 */
+#define CAN_RF1R_FOVR1 CAN_RF1R_FOVR1_Msk /*!< FIFO 1 Overrun */
+#define CAN_RF1R_RFOM1_Pos (5U)
+#define CAN_RF1R_RFOM1_Msk (0x1U << CAN_RF1R_RFOM1_Pos) /*!< 0x00000020 */
+#define CAN_RF1R_RFOM1 CAN_RF1R_RFOM1_Msk /*!< Release FIFO 1 Output Mailbox */
+
+/******************** Bit definition for CAN_IER register *******************/
+#define CAN_IER_TMEIE_Pos (0U)
+#define CAN_IER_TMEIE_Msk (0x1U << CAN_IER_TMEIE_Pos) /*!< 0x00000001 */
+#define CAN_IER_TMEIE CAN_IER_TMEIE_Msk /*!< Transmit Mailbox Empty Interrupt Enable */
+#define CAN_IER_FMPIE0_Pos (1U)
+#define CAN_IER_FMPIE0_Msk (0x1U << CAN_IER_FMPIE0_Pos) /*!< 0x00000002 */
+#define CAN_IER_FMPIE0 CAN_IER_FMPIE0_Msk /*!< FIFO Message Pending Interrupt Enable */
+#define CAN_IER_FFIE0_Pos (2U)
+#define CAN_IER_FFIE0_Msk (0x1U << CAN_IER_FFIE0_Pos) /*!< 0x00000004 */
+#define CAN_IER_FFIE0 CAN_IER_FFIE0_Msk /*!< FIFO Full Interrupt Enable */
+#define CAN_IER_FOVIE0_Pos (3U)
+#define CAN_IER_FOVIE0_Msk (0x1U << CAN_IER_FOVIE0_Pos) /*!< 0x00000008 */
+#define CAN_IER_FOVIE0 CAN_IER_FOVIE0_Msk /*!< FIFO Overrun Interrupt Enable */
+#define CAN_IER_FMPIE1_Pos (4U)
+#define CAN_IER_FMPIE1_Msk (0x1U << CAN_IER_FMPIE1_Pos) /*!< 0x00000010 */
+#define CAN_IER_FMPIE1 CAN_IER_FMPIE1_Msk /*!< FIFO Message Pending Interrupt Enable */
+#define CAN_IER_FFIE1_Pos (5U)
+#define CAN_IER_FFIE1_Msk (0x1U << CAN_IER_FFIE1_Pos) /*!< 0x00000020 */
+#define CAN_IER_FFIE1 CAN_IER_FFIE1_Msk /*!< FIFO Full Interrupt Enable */
+#define CAN_IER_FOVIE1_Pos (6U)
+#define CAN_IER_FOVIE1_Msk (0x1U << CAN_IER_FOVIE1_Pos) /*!< 0x00000040 */
+#define CAN_IER_FOVIE1 CAN_IER_FOVIE1_Msk /*!< FIFO Overrun Interrupt Enable */
+#define CAN_IER_EWGIE_Pos (8U)
+#define CAN_IER_EWGIE_Msk (0x1U << CAN_IER_EWGIE_Pos) /*!< 0x00000100 */
+#define CAN_IER_EWGIE CAN_IER_EWGIE_Msk /*!< Error Warning Interrupt Enable */
+#define CAN_IER_EPVIE_Pos (9U)
+#define CAN_IER_EPVIE_Msk (0x1U << CAN_IER_EPVIE_Pos) /*!< 0x00000200 */
+#define CAN_IER_EPVIE CAN_IER_EPVIE_Msk /*!< Error Passive Interrupt Enable */
+#define CAN_IER_BOFIE_Pos (10U)
+#define CAN_IER_BOFIE_Msk (0x1U << CAN_IER_BOFIE_Pos) /*!< 0x00000400 */
+#define CAN_IER_BOFIE CAN_IER_BOFIE_Msk /*!< Bus-Off Interrupt Enable */
+#define CAN_IER_LECIE_Pos (11U)
+#define CAN_IER_LECIE_Msk (0x1U << CAN_IER_LECIE_Pos) /*!< 0x00000800 */
+#define CAN_IER_LECIE CAN_IER_LECIE_Msk /*!< Last Error Code Interrupt Enable */
+#define CAN_IER_ERRIE_Pos (15U)
+#define CAN_IER_ERRIE_Msk (0x1U << CAN_IER_ERRIE_Pos) /*!< 0x00008000 */
+#define CAN_IER_ERRIE CAN_IER_ERRIE_Msk /*!< Error Interrupt Enable */
+#define CAN_IER_WKUIE_Pos (16U)
+#define CAN_IER_WKUIE_Msk (0x1U << CAN_IER_WKUIE_Pos) /*!< 0x00010000 */
+#define CAN_IER_WKUIE CAN_IER_WKUIE_Msk /*!< Wakeup Interrupt Enable */
+#define CAN_IER_SLKIE_Pos (17U)
+#define CAN_IER_SLKIE_Msk (0x1U << CAN_IER_SLKIE_Pos) /*!< 0x00020000 */
+#define CAN_IER_SLKIE CAN_IER_SLKIE_Msk /*!< Sleep Interrupt Enable */
+
+/******************** Bit definition for CAN_ESR register *******************/
+#define CAN_ESR_EWGF_Pos (0U)
+#define CAN_ESR_EWGF_Msk (0x1U << CAN_ESR_EWGF_Pos) /*!< 0x00000001 */
+#define CAN_ESR_EWGF CAN_ESR_EWGF_Msk /*!< Error Warning Flag */
+#define CAN_ESR_EPVF_Pos (1U)
+#define CAN_ESR_EPVF_Msk (0x1U << CAN_ESR_EPVF_Pos) /*!< 0x00000002 */
+#define CAN_ESR_EPVF CAN_ESR_EPVF_Msk /*!< Error Passive Flag */
+#define CAN_ESR_BOFF_Pos (2U)
+#define CAN_ESR_BOFF_Msk (0x1U << CAN_ESR_BOFF_Pos) /*!< 0x00000004 */
+#define CAN_ESR_BOFF CAN_ESR_BOFF_Msk /*!< Bus-Off Flag */
+
+#define CAN_ESR_LEC_Pos (4U)
+#define CAN_ESR_LEC_Msk (0x7U << CAN_ESR_LEC_Pos) /*!< 0x00000070 */
+#define CAN_ESR_LEC CAN_ESR_LEC_Msk /*!< LEC[2:0] bits (Last Error Code) */
+#define CAN_ESR_LEC_0 (0x1U << CAN_ESR_LEC_Pos) /*!< 0x00000010 */
+#define CAN_ESR_LEC_1 (0x2U << CAN_ESR_LEC_Pos) /*!< 0x00000020 */
+#define CAN_ESR_LEC_2 (0x4U << CAN_ESR_LEC_Pos) /*!< 0x00000040 */
+
+#define CAN_ESR_TEC_Pos (16U)
+#define CAN_ESR_TEC_Msk (0xFFU << CAN_ESR_TEC_Pos) /*!< 0x00FF0000 */
+#define CAN_ESR_TEC CAN_ESR_TEC_Msk /*!< Least significant byte of the 9-bit Transmit Error Counter */
+#define CAN_ESR_REC_Pos (24U)
+#define CAN_ESR_REC_Msk (0xFFU << CAN_ESR_REC_Pos) /*!< 0xFF000000 */
+#define CAN_ESR_REC CAN_ESR_REC_Msk /*!< Receive Error Counter */
+
+/******************* Bit definition for CAN_BTR register ********************/
+#define CAN_BTR_BRP_Pos (0U)
+#define CAN_BTR_BRP_Msk (0x3FFU << CAN_BTR_BRP_Pos) /*!< 0x000003FF */
+#define CAN_BTR_BRP CAN_BTR_BRP_Msk /*!<Baud Rate Prescaler */
+#define CAN_BTR_TS1_Pos (16U)
+#define CAN_BTR_TS1_Msk (0xFU << CAN_BTR_TS1_Pos) /*!< 0x000F0000 */
+#define CAN_BTR_TS1 CAN_BTR_TS1_Msk /*!<Time Segment 1 */
+#define CAN_BTR_TS1_0 (0x1U << CAN_BTR_TS1_Pos) /*!< 0x00010000 */
+#define CAN_BTR_TS1_1 (0x2U << CAN_BTR_TS1_Pos) /*!< 0x00020000 */
+#define CAN_BTR_TS1_2 (0x4U << CAN_BTR_TS1_Pos) /*!< 0x00040000 */
+#define CAN_BTR_TS1_3 (0x8U << CAN_BTR_TS1_Pos) /*!< 0x00080000 */
+#define CAN_BTR_TS2_Pos (20U)
+#define CAN_BTR_TS2_Msk (0x7U << CAN_BTR_TS2_Pos) /*!< 0x00700000 */
+#define CAN_BTR_TS2 CAN_BTR_TS2_Msk /*!<Time Segment 2 */
+#define CAN_BTR_TS2_0 (0x1U << CAN_BTR_TS2_Pos) /*!< 0x00100000 */
+#define CAN_BTR_TS2_1 (0x2U << CAN_BTR_TS2_Pos) /*!< 0x00200000 */
+#define CAN_BTR_TS2_2 (0x4U << CAN_BTR_TS2_Pos) /*!< 0x00400000 */
+#define CAN_BTR_SJW_Pos (24U)
+#define CAN_BTR_SJW_Msk (0x3U << CAN_BTR_SJW_Pos) /*!< 0x03000000 */
+#define CAN_BTR_SJW CAN_BTR_SJW_Msk /*!<Resynchronization Jump Width */
+#define CAN_BTR_SJW_0 (0x1U << CAN_BTR_SJW_Pos) /*!< 0x01000000 */
+#define CAN_BTR_SJW_1 (0x2U << CAN_BTR_SJW_Pos) /*!< 0x02000000 */
+#define CAN_BTR_LBKM_Pos (30U)
+#define CAN_BTR_LBKM_Msk (0x1U << CAN_BTR_LBKM_Pos) /*!< 0x40000000 */
+#define CAN_BTR_LBKM CAN_BTR_LBKM_Msk /*!<Loop Back Mode (Debug) */
+#define CAN_BTR_SILM_Pos (31U)
+#define CAN_BTR_SILM_Msk (0x1U << CAN_BTR_SILM_Pos) /*!< 0x80000000 */
+#define CAN_BTR_SILM CAN_BTR_SILM_Msk /*!<Silent Mode */
+
+/*!< Mailbox registers */
+/****************** Bit definition for CAN_TI0R register ********************/
+#define CAN_TI0R_TXRQ_Pos (0U)
+#define CAN_TI0R_TXRQ_Msk (0x1U << CAN_TI0R_TXRQ_Pos) /*!< 0x00000001 */
+#define CAN_TI0R_TXRQ CAN_TI0R_TXRQ_Msk /*!< Transmit Mailbox Request */
+#define CAN_TI0R_RTR_Pos (1U)
+#define CAN_TI0R_RTR_Msk (0x1U << CAN_TI0R_RTR_Pos) /*!< 0x00000002 */
+#define CAN_TI0R_RTR CAN_TI0R_RTR_Msk /*!< Remote Transmission Request */
+#define CAN_TI0R_IDE_Pos (2U)
+#define CAN_TI0R_IDE_Msk (0x1U << CAN_TI0R_IDE_Pos) /*!< 0x00000004 */
+#define CAN_TI0R_IDE CAN_TI0R_IDE_Msk /*!< Identifier Extension */
+#define CAN_TI0R_EXID_Pos (3U)
+#define CAN_TI0R_EXID_Msk (0x3FFFFU << CAN_TI0R_EXID_Pos) /*!< 0x001FFFF8 */
+#define CAN_TI0R_EXID CAN_TI0R_EXID_Msk /*!< Extended Identifier */
+#define CAN_TI0R_STID_Pos (21U)
+#define CAN_TI0R_STID_Msk (0x7FFU << CAN_TI0R_STID_Pos) /*!< 0xFFE00000 */
+#define CAN_TI0R_STID CAN_TI0R_STID_Msk /*!< Standard Identifier or Extended Identifier */
+
+/****************** Bit definition for CAN_TDT0R register *******************/
+#define CAN_TDT0R_DLC_Pos (0U)
+#define CAN_TDT0R_DLC_Msk (0xFU << CAN_TDT0R_DLC_Pos) /*!< 0x0000000F */
+#define CAN_TDT0R_DLC CAN_TDT0R_DLC_Msk /*!< Data Length Code */
+#define CAN_TDT0R_TGT_Pos (8U)
+#define CAN_TDT0R_TGT_Msk (0x1U << CAN_TDT0R_TGT_Pos) /*!< 0x00000100 */
+#define CAN_TDT0R_TGT CAN_TDT0R_TGT_Msk /*!< Transmit Global Time */
+#define CAN_TDT0R_TIME_Pos (16U)
+#define CAN_TDT0R_TIME_Msk (0xFFFFU << CAN_TDT0R_TIME_Pos) /*!< 0xFFFF0000 */
+#define CAN_TDT0R_TIME CAN_TDT0R_TIME_Msk /*!< Message Time Stamp */
+
+/****************** Bit definition for CAN_TDL0R register *******************/
+#define CAN_TDL0R_DATA0_Pos (0U)
+#define CAN_TDL0R_DATA0_Msk (0xFFU << CAN_TDL0R_DATA0_Pos) /*!< 0x000000FF */
+#define CAN_TDL0R_DATA0 CAN_TDL0R_DATA0_Msk /*!< Data byte 0 */
+#define CAN_TDL0R_DATA1_Pos (8U)
+#define CAN_TDL0R_DATA1_Msk (0xFFU << CAN_TDL0R_DATA1_Pos) /*!< 0x0000FF00 */
+#define CAN_TDL0R_DATA1 CAN_TDL0R_DATA1_Msk /*!< Data byte 1 */
+#define CAN_TDL0R_DATA2_Pos (16U)
+#define CAN_TDL0R_DATA2_Msk (0xFFU << CAN_TDL0R_DATA2_Pos) /*!< 0x00FF0000 */
+#define CAN_TDL0R_DATA2 CAN_TDL0R_DATA2_Msk /*!< Data byte 2 */
+#define CAN_TDL0R_DATA3_Pos (24U)
+#define CAN_TDL0R_DATA3_Msk (0xFFU << CAN_TDL0R_DATA3_Pos) /*!< 0xFF000000 */
+#define CAN_TDL0R_DATA3 CAN_TDL0R_DATA3_Msk /*!< Data byte 3 */
+
+/****************** Bit definition for CAN_TDH0R register *******************/
+#define CAN_TDH0R_DATA4_Pos (0U)
+#define CAN_TDH0R_DATA4_Msk (0xFFU << CAN_TDH0R_DATA4_Pos) /*!< 0x000000FF */
+#define CAN_TDH0R_DATA4 CAN_TDH0R_DATA4_Msk /*!< Data byte 4 */
+#define CAN_TDH0R_DATA5_Pos (8U)
+#define CAN_TDH0R_DATA5_Msk (0xFFU << CAN_TDH0R_DATA5_Pos) /*!< 0x0000FF00 */
+#define CAN_TDH0R_DATA5 CAN_TDH0R_DATA5_Msk /*!< Data byte 5 */
+#define CAN_TDH0R_DATA6_Pos (16U)
+#define CAN_TDH0R_DATA6_Msk (0xFFU << CAN_TDH0R_DATA6_Pos) /*!< 0x00FF0000 */
+#define CAN_TDH0R_DATA6 CAN_TDH0R_DATA6_Msk /*!< Data byte 6 */
+#define CAN_TDH0R_DATA7_Pos (24U)
+#define CAN_TDH0R_DATA7_Msk (0xFFU << CAN_TDH0R_DATA7_Pos) /*!< 0xFF000000 */
+#define CAN_TDH0R_DATA7 CAN_TDH0R_DATA7_Msk /*!< Data byte 7 */
+
+/******************* Bit definition for CAN_TI1R register *******************/
+#define CAN_TI1R_TXRQ_Pos (0U)
+#define CAN_TI1R_TXRQ_Msk (0x1U << CAN_TI1R_TXRQ_Pos) /*!< 0x00000001 */
+#define CAN_TI1R_TXRQ CAN_TI1R_TXRQ_Msk /*!< Transmit Mailbox Request */
+#define CAN_TI1R_RTR_Pos (1U)
+#define CAN_TI1R_RTR_Msk (0x1U << CAN_TI1R_RTR_Pos) /*!< 0x00000002 */
+#define CAN_TI1R_RTR CAN_TI1R_RTR_Msk /*!< Remote Transmission Request */
+#define CAN_TI1R_IDE_Pos (2U)
+#define CAN_TI1R_IDE_Msk (0x1U << CAN_TI1R_IDE_Pos) /*!< 0x00000004 */
+#define CAN_TI1R_IDE CAN_TI1R_IDE_Msk /*!< Identifier Extension */
+#define CAN_TI1R_EXID_Pos (3U)
+#define CAN_TI1R_EXID_Msk (0x3FFFFU << CAN_TI1R_EXID_Pos) /*!< 0x001FFFF8 */
+#define CAN_TI1R_EXID CAN_TI1R_EXID_Msk /*!< Extended Identifier */
+#define CAN_TI1R_STID_Pos (21U)
+#define CAN_TI1R_STID_Msk (0x7FFU << CAN_TI1R_STID_Pos) /*!< 0xFFE00000 */
+#define CAN_TI1R_STID CAN_TI1R_STID_Msk /*!< Standard Identifier or Extended Identifier */
+
+/******************* Bit definition for CAN_TDT1R register ******************/
+#define CAN_TDT1R_DLC_Pos (0U)
+#define CAN_TDT1R_DLC_Msk (0xFU << CAN_TDT1R_DLC_Pos) /*!< 0x0000000F */
+#define CAN_TDT1R_DLC CAN_TDT1R_DLC_Msk /*!< Data Length Code */
+#define CAN_TDT1R_TGT_Pos (8U)
+#define CAN_TDT1R_TGT_Msk (0x1U << CAN_TDT1R_TGT_Pos) /*!< 0x00000100 */
+#define CAN_TDT1R_TGT CAN_TDT1R_TGT_Msk /*!< Transmit Global Time */
+#define CAN_TDT1R_TIME_Pos (16U)
+#define CAN_TDT1R_TIME_Msk (0xFFFFU << CAN_TDT1R_TIME_Pos) /*!< 0xFFFF0000 */
+#define CAN_TDT1R_TIME CAN_TDT1R_TIME_Msk /*!< Message Time Stamp */
+
+/******************* Bit definition for CAN_TDL1R register ******************/
+#define CAN_TDL1R_DATA0_Pos (0U)
+#define CAN_TDL1R_DATA0_Msk (0xFFU << CAN_TDL1R_DATA0_Pos) /*!< 0x000000FF */
+#define CAN_TDL1R_DATA0 CAN_TDL1R_DATA0_Msk /*!< Data byte 0 */
+#define CAN_TDL1R_DATA1_Pos (8U)
+#define CAN_TDL1R_DATA1_Msk (0xFFU << CAN_TDL1R_DATA1_Pos) /*!< 0x0000FF00 */
+#define CAN_TDL1R_DATA1 CAN_TDL1R_DATA1_Msk /*!< Data byte 1 */
+#define CAN_TDL1R_DATA2_Pos (16U)
+#define CAN_TDL1R_DATA2_Msk (0xFFU << CAN_TDL1R_DATA2_Pos) /*!< 0x00FF0000 */
+#define CAN_TDL1R_DATA2 CAN_TDL1R_DATA2_Msk /*!< Data byte 2 */
+#define CAN_TDL1R_DATA3_Pos (24U)
+#define CAN_TDL1R_DATA3_Msk (0xFFU << CAN_TDL1R_DATA3_Pos) /*!< 0xFF000000 */
+#define CAN_TDL1R_DATA3 CAN_TDL1R_DATA3_Msk /*!< Data byte 3 */
+
+/******************* Bit definition for CAN_TDH1R register ******************/
+#define CAN_TDH1R_DATA4_Pos (0U)
+#define CAN_TDH1R_DATA4_Msk (0xFFU << CAN_TDH1R_DATA4_Pos) /*!< 0x000000FF */
+#define CAN_TDH1R_DATA4 CAN_TDH1R_DATA4_Msk /*!< Data byte 4 */
+#define CAN_TDH1R_DATA5_Pos (8U)
+#define CAN_TDH1R_DATA5_Msk (0xFFU << CAN_TDH1R_DATA5_Pos) /*!< 0x0000FF00 */
+#define CAN_TDH1R_DATA5 CAN_TDH1R_DATA5_Msk /*!< Data byte 5 */
+#define CAN_TDH1R_DATA6_Pos (16U)
+#define CAN_TDH1R_DATA6_Msk (0xFFU << CAN_TDH1R_DATA6_Pos) /*!< 0x00FF0000 */
+#define CAN_TDH1R_DATA6 CAN_TDH1R_DATA6_Msk /*!< Data byte 6 */
+#define CAN_TDH1R_DATA7_Pos (24U)
+#define CAN_TDH1R_DATA7_Msk (0xFFU << CAN_TDH1R_DATA7_Pos) /*!< 0xFF000000 */
+#define CAN_TDH1R_DATA7 CAN_TDH1R_DATA7_Msk /*!< Data byte 7 */
+
+/******************* Bit definition for CAN_TI2R register *******************/
+#define CAN_TI2R_TXRQ_Pos (0U)
+#define CAN_TI2R_TXRQ_Msk (0x1U << CAN_TI2R_TXRQ_Pos) /*!< 0x00000001 */
+#define CAN_TI2R_TXRQ CAN_TI2R_TXRQ_Msk /*!< Transmit Mailbox Request */
+#define CAN_TI2R_RTR_Pos (1U)
+#define CAN_TI2R_RTR_Msk (0x1U << CAN_TI2R_RTR_Pos) /*!< 0x00000002 */
+#define CAN_TI2R_RTR CAN_TI2R_RTR_Msk /*!< Remote Transmission Request */
+#define CAN_TI2R_IDE_Pos (2U)
+#define CAN_TI2R_IDE_Msk (0x1U << CAN_TI2R_IDE_Pos) /*!< 0x00000004 */
+#define CAN_TI2R_IDE CAN_TI2R_IDE_Msk /*!< Identifier Extension */
+#define CAN_TI2R_EXID_Pos (3U)
+#define CAN_TI2R_EXID_Msk (0x3FFFFU << CAN_TI2R_EXID_Pos) /*!< 0x001FFFF8 */
+#define CAN_TI2R_EXID CAN_TI2R_EXID_Msk /*!< Extended identifier */
+#define CAN_TI2R_STID_Pos (21U)
+#define CAN_TI2R_STID_Msk (0x7FFU << CAN_TI2R_STID_Pos) /*!< 0xFFE00000 */
+#define CAN_TI2R_STID CAN_TI2R_STID_Msk /*!< Standard Identifier or Extended Identifier */
+
+/******************* Bit definition for CAN_TDT2R register ******************/
+#define CAN_TDT2R_DLC_Pos (0U)
+#define CAN_TDT2R_DLC_Msk (0xFU << CAN_TDT2R_DLC_Pos) /*!< 0x0000000F */
+#define CAN_TDT2R_DLC CAN_TDT2R_DLC_Msk /*!< Data Length Code */
+#define CAN_TDT2R_TGT_Pos (8U)
+#define CAN_TDT2R_TGT_Msk (0x1U << CAN_TDT2R_TGT_Pos) /*!< 0x00000100 */
+#define CAN_TDT2R_TGT CAN_TDT2R_TGT_Msk /*!< Transmit Global Time */
+#define CAN_TDT2R_TIME_Pos (16U)
+#define CAN_TDT2R_TIME_Msk (0xFFFFU << CAN_TDT2R_TIME_Pos) /*!< 0xFFFF0000 */
+#define CAN_TDT2R_TIME CAN_TDT2R_TIME_Msk /*!< Message Time Stamp */
+
+/******************* Bit definition for CAN_TDL2R register ******************/
+#define CAN_TDL2R_DATA0_Pos (0U)
+#define CAN_TDL2R_DATA0_Msk (0xFFU << CAN_TDL2R_DATA0_Pos) /*!< 0x000000FF */
+#define CAN_TDL2R_DATA0 CAN_TDL2R_DATA0_Msk /*!< Data byte 0 */
+#define CAN_TDL2R_DATA1_Pos (8U)
+#define CAN_TDL2R_DATA1_Msk (0xFFU << CAN_TDL2R_DATA1_Pos) /*!< 0x0000FF00 */
+#define CAN_TDL2R_DATA1 CAN_TDL2R_DATA1_Msk /*!< Data byte 1 */
+#define CAN_TDL2R_DATA2_Pos (16U)
+#define CAN_TDL2R_DATA2_Msk (0xFFU << CAN_TDL2R_DATA2_Pos) /*!< 0x00FF0000 */
+#define CAN_TDL2R_DATA2 CAN_TDL2R_DATA2_Msk /*!< Data byte 2 */
+#define CAN_TDL2R_DATA3_Pos (24U)
+#define CAN_TDL2R_DATA3_Msk (0xFFU << CAN_TDL2R_DATA3_Pos) /*!< 0xFF000000 */
+#define CAN_TDL2R_DATA3 CAN_TDL2R_DATA3_Msk /*!< Data byte 3 */
+
+/******************* Bit definition for CAN_TDH2R register ******************/
+#define CAN_TDH2R_DATA4_Pos (0U)
+#define CAN_TDH2R_DATA4_Msk (0xFFU << CAN_TDH2R_DATA4_Pos) /*!< 0x000000FF */
+#define CAN_TDH2R_DATA4 CAN_TDH2R_DATA4_Msk /*!< Data byte 4 */
+#define CAN_TDH2R_DATA5_Pos (8U)
+#define CAN_TDH2R_DATA5_Msk (0xFFU << CAN_TDH2R_DATA5_Pos) /*!< 0x0000FF00 */
+#define CAN_TDH2R_DATA5 CAN_TDH2R_DATA5_Msk /*!< Data byte 5 */
+#define CAN_TDH2R_DATA6_Pos (16U)
+#define CAN_TDH2R_DATA6_Msk (0xFFU << CAN_TDH2R_DATA6_Pos) /*!< 0x00FF0000 */
+#define CAN_TDH2R_DATA6 CAN_TDH2R_DATA6_Msk /*!< Data byte 6 */
+#define CAN_TDH2R_DATA7_Pos (24U)
+#define CAN_TDH2R_DATA7_Msk (0xFFU << CAN_TDH2R_DATA7_Pos) /*!< 0xFF000000 */
+#define CAN_TDH2R_DATA7 CAN_TDH2R_DATA7_Msk /*!< Data byte 7 */
+
+/******************* Bit definition for CAN_RI0R register *******************/
+#define CAN_RI0R_RTR_Pos (1U)
+#define CAN_RI0R_RTR_Msk (0x1U << CAN_RI0R_RTR_Pos) /*!< 0x00000002 */
+#define CAN_RI0R_RTR CAN_RI0R_RTR_Msk /*!< Remote Transmission Request */
+#define CAN_RI0R_IDE_Pos (2U)
+#define CAN_RI0R_IDE_Msk (0x1U << CAN_RI0R_IDE_Pos) /*!< 0x00000004 */
+#define CAN_RI0R_IDE CAN_RI0R_IDE_Msk /*!< Identifier Extension */
+#define CAN_RI0R_EXID_Pos (3U)
+#define CAN_RI0R_EXID_Msk (0x3FFFFU << CAN_RI0R_EXID_Pos) /*!< 0x001FFFF8 */
+#define CAN_RI0R_EXID CAN_RI0R_EXID_Msk /*!< Extended Identifier */
+#define CAN_RI0R_STID_Pos (21U)
+#define CAN_RI0R_STID_Msk (0x7FFU << CAN_RI0R_STID_Pos) /*!< 0xFFE00000 */
+#define CAN_RI0R_STID CAN_RI0R_STID_Msk /*!< Standard Identifier or Extended Identifier */
+
+/******************* Bit definition for CAN_RDT0R register ******************/
+#define CAN_RDT0R_DLC_Pos (0U)
+#define CAN_RDT0R_DLC_Msk (0xFU << CAN_RDT0R_DLC_Pos) /*!< 0x0000000F */
+#define CAN_RDT0R_DLC CAN_RDT0R_DLC_Msk /*!< Data Length Code */
+#define CAN_RDT0R_FMI_Pos (8U)
+#define CAN_RDT0R_FMI_Msk (0xFFU << CAN_RDT0R_FMI_Pos) /*!< 0x0000FF00 */
+#define CAN_RDT0R_FMI CAN_RDT0R_FMI_Msk /*!< Filter Match Index */
+#define CAN_RDT0R_TIME_Pos (16U)
+#define CAN_RDT0R_TIME_Msk (0xFFFFU << CAN_RDT0R_TIME_Pos) /*!< 0xFFFF0000 */
+#define CAN_RDT0R_TIME CAN_RDT0R_TIME_Msk /*!< Message Time Stamp */
+
+/******************* Bit definition for CAN_RDL0R register ******************/
+#define CAN_RDL0R_DATA0_Pos (0U)
+#define CAN_RDL0R_DATA0_Msk (0xFFU << CAN_RDL0R_DATA0_Pos) /*!< 0x000000FF */
+#define CAN_RDL0R_DATA0 CAN_RDL0R_DATA0_Msk /*!< Data byte 0 */
+#define CAN_RDL0R_DATA1_Pos (8U)
+#define CAN_RDL0R_DATA1_Msk (0xFFU << CAN_RDL0R_DATA1_Pos) /*!< 0x0000FF00 */
+#define CAN_RDL0R_DATA1 CAN_RDL0R_DATA1_Msk /*!< Data byte 1 */
+#define CAN_RDL0R_DATA2_Pos (16U)
+#define CAN_RDL0R_DATA2_Msk (0xFFU << CAN_RDL0R_DATA2_Pos) /*!< 0x00FF0000 */
+#define CAN_RDL0R_DATA2 CAN_RDL0R_DATA2_Msk /*!< Data byte 2 */
+#define CAN_RDL0R_DATA3_Pos (24U)
+#define CAN_RDL0R_DATA3_Msk (0xFFU << CAN_RDL0R_DATA3_Pos) /*!< 0xFF000000 */
+#define CAN_RDL0R_DATA3 CAN_RDL0R_DATA3_Msk /*!< Data byte 3 */
+
+/******************* Bit definition for CAN_RDH0R register ******************/
+#define CAN_RDH0R_DATA4_Pos (0U)
+#define CAN_RDH0R_DATA4_Msk (0xFFU << CAN_RDH0R_DATA4_Pos) /*!< 0x000000FF */
+#define CAN_RDH0R_DATA4 CAN_RDH0R_DATA4_Msk /*!< Data byte 4 */
+#define CAN_RDH0R_DATA5_Pos (8U)
+#define CAN_RDH0R_DATA5_Msk (0xFFU << CAN_RDH0R_DATA5_Pos) /*!< 0x0000FF00 */
+#define CAN_RDH0R_DATA5 CAN_RDH0R_DATA5_Msk /*!< Data byte 5 */
+#define CAN_RDH0R_DATA6_Pos (16U)
+#define CAN_RDH0R_DATA6_Msk (0xFFU << CAN_RDH0R_DATA6_Pos) /*!< 0x00FF0000 */
+#define CAN_RDH0R_DATA6 CAN_RDH0R_DATA6_Msk /*!< Data byte 6 */
+#define CAN_RDH0R_DATA7_Pos (24U)
+#define CAN_RDH0R_DATA7_Msk (0xFFU << CAN_RDH0R_DATA7_Pos) /*!< 0xFF000000 */
+#define CAN_RDH0R_DATA7 CAN_RDH0R_DATA7_Msk /*!< Data byte 7 */
+
+/******************* Bit definition for CAN_RI1R register *******************/
+#define CAN_RI1R_RTR_Pos (1U)
+#define CAN_RI1R_RTR_Msk (0x1U << CAN_RI1R_RTR_Pos) /*!< 0x00000002 */
+#define CAN_RI1R_RTR CAN_RI1R_RTR_Msk /*!< Remote Transmission Request */
+#define CAN_RI1R_IDE_Pos (2U)
+#define CAN_RI1R_IDE_Msk (0x1U << CAN_RI1R_IDE_Pos) /*!< 0x00000004 */
+#define CAN_RI1R_IDE CAN_RI1R_IDE_Msk /*!< Identifier Extension */
+#define CAN_RI1R_EXID_Pos (3U)
+#define CAN_RI1R_EXID_Msk (0x3FFFFU << CAN_RI1R_EXID_Pos) /*!< 0x001FFFF8 */
+#define CAN_RI1R_EXID CAN_RI1R_EXID_Msk /*!< Extended identifier */
+#define CAN_RI1R_STID_Pos (21U)
+#define CAN_RI1R_STID_Msk (0x7FFU << CAN_RI1R_STID_Pos) /*!< 0xFFE00000 */
+#define CAN_RI1R_STID CAN_RI1R_STID_Msk /*!< Standard Identifier or Extended Identifier */
+
+/******************* Bit definition for CAN_RDT1R register ******************/
+#define CAN_RDT1R_DLC_Pos (0U)
+#define CAN_RDT1R_DLC_Msk (0xFU << CAN_RDT1R_DLC_Pos) /*!< 0x0000000F */
+#define CAN_RDT1R_DLC CAN_RDT1R_DLC_Msk /*!< Data Length Code */
+#define CAN_RDT1R_FMI_Pos (8U)
+#define CAN_RDT1R_FMI_Msk (0xFFU << CAN_RDT1R_FMI_Pos) /*!< 0x0000FF00 */
+#define CAN_RDT1R_FMI CAN_RDT1R_FMI_Msk /*!< Filter Match Index */
+#define CAN_RDT1R_TIME_Pos (16U)
+#define CAN_RDT1R_TIME_Msk (0xFFFFU << CAN_RDT1R_TIME_Pos) /*!< 0xFFFF0000 */
+#define CAN_RDT1R_TIME CAN_RDT1R_TIME_Msk /*!< Message Time Stamp */
+
+/******************* Bit definition for CAN_RDL1R register ******************/
+#define CAN_RDL1R_DATA0_Pos (0U)
+#define CAN_RDL1R_DATA0_Msk (0xFFU << CAN_RDL1R_DATA0_Pos) /*!< 0x000000FF */
+#define CAN_RDL1R_DATA0 CAN_RDL1R_DATA0_Msk /*!< Data byte 0 */
+#define CAN_RDL1R_DATA1_Pos (8U)
+#define CAN_RDL1R_DATA1_Msk (0xFFU << CAN_RDL1R_DATA1_Pos) /*!< 0x0000FF00 */
+#define CAN_RDL1R_DATA1 CAN_RDL1R_DATA1_Msk /*!< Data byte 1 */
+#define CAN_RDL1R_DATA2_Pos (16U)
+#define CAN_RDL1R_DATA2_Msk (0xFFU << CAN_RDL1R_DATA2_Pos) /*!< 0x00FF0000 */
+#define CAN_RDL1R_DATA2 CAN_RDL1R_DATA2_Msk /*!< Data byte 2 */
+#define CAN_RDL1R_DATA3_Pos (24U)
+#define CAN_RDL1R_DATA3_Msk (0xFFU << CAN_RDL1R_DATA3_Pos) /*!< 0xFF000000 */
+#define CAN_RDL1R_DATA3 CAN_RDL1R_DATA3_Msk /*!< Data byte 3 */
+
+/******************* Bit definition for CAN_RDH1R register ******************/
+#define CAN_RDH1R_DATA4_Pos (0U)
+#define CAN_RDH1R_DATA4_Msk (0xFFU << CAN_RDH1R_DATA4_Pos) /*!< 0x000000FF */
+#define CAN_RDH1R_DATA4 CAN_RDH1R_DATA4_Msk /*!< Data byte 4 */
+#define CAN_RDH1R_DATA5_Pos (8U)
+#define CAN_RDH1R_DATA5_Msk (0xFFU << CAN_RDH1R_DATA5_Pos) /*!< 0x0000FF00 */
+#define CAN_RDH1R_DATA5 CAN_RDH1R_DATA5_Msk /*!< Data byte 5 */
+#define CAN_RDH1R_DATA6_Pos (16U)
+#define CAN_RDH1R_DATA6_Msk (0xFFU << CAN_RDH1R_DATA6_Pos) /*!< 0x00FF0000 */
+#define CAN_RDH1R_DATA6 CAN_RDH1R_DATA6_Msk /*!< Data byte 6 */
+#define CAN_RDH1R_DATA7_Pos (24U)
+#define CAN_RDH1R_DATA7_Msk (0xFFU << CAN_RDH1R_DATA7_Pos) /*!< 0xFF000000 */
+#define CAN_RDH1R_DATA7 CAN_RDH1R_DATA7_Msk /*!< Data byte 7 */
+
+/*!< CAN filter registers */
+/******************* Bit definition for CAN_FMR register ********************/
+#define CAN_FMR_FINIT_Pos (0U)
+#define CAN_FMR_FINIT_Msk (0x1U << CAN_FMR_FINIT_Pos) /*!< 0x00000001 */
+#define CAN_FMR_FINIT CAN_FMR_FINIT_Msk /*!< Filter Init Mode */
+#define CAN_FMR_CAN2SB_Pos (8U)
+#define CAN_FMR_CAN2SB_Msk (0x3FU << CAN_FMR_CAN2SB_Pos) /*!< 0x00003F00 */
+#define CAN_FMR_CAN2SB CAN_FMR_CAN2SB_Msk /*!< CAN2 start bank */
+
+/******************* Bit definition for CAN_FM1R register *******************/
+#define CAN_FM1R_FBM_Pos (0U)
+#define CAN_FM1R_FBM_Msk (0x3FFFU << CAN_FM1R_FBM_Pos) /*!< 0x00003FFF */
+#define CAN_FM1R_FBM CAN_FM1R_FBM_Msk /*!< Filter Mode */
+#define CAN_FM1R_FBM0_Pos (0U)
+#define CAN_FM1R_FBM0_Msk (0x1U << CAN_FM1R_FBM0_Pos) /*!< 0x00000001 */
+#define CAN_FM1R_FBM0 CAN_FM1R_FBM0_Msk /*!< Filter Init Mode for filter 0 */
+#define CAN_FM1R_FBM1_Pos (1U)
+#define CAN_FM1R_FBM1_Msk (0x1U << CAN_FM1R_FBM1_Pos) /*!< 0x00000002 */
+#define CAN_FM1R_FBM1 CAN_FM1R_FBM1_Msk /*!< Filter Init Mode for filter 1 */
+#define CAN_FM1R_FBM2_Pos (2U)
+#define CAN_FM1R_FBM2_Msk (0x1U << CAN_FM1R_FBM2_Pos) /*!< 0x00000004 */
+#define CAN_FM1R_FBM2 CAN_FM1R_FBM2_Msk /*!< Filter Init Mode for filter 2 */
+#define CAN_FM1R_FBM3_Pos (3U)
+#define CAN_FM1R_FBM3_Msk (0x1U << CAN_FM1R_FBM3_Pos) /*!< 0x00000008 */
+#define CAN_FM1R_FBM3 CAN_FM1R_FBM3_Msk /*!< Filter Init Mode for filter 3 */
+#define CAN_FM1R_FBM4_Pos (4U)
+#define CAN_FM1R_FBM4_Msk (0x1U << CAN_FM1R_FBM4_Pos) /*!< 0x00000010 */
+#define CAN_FM1R_FBM4 CAN_FM1R_FBM4_Msk /*!< Filter Init Mode for filter 4 */
+#define CAN_FM1R_FBM5_Pos (5U)
+#define CAN_FM1R_FBM5_Msk (0x1U << CAN_FM1R_FBM5_Pos) /*!< 0x00000020 */
+#define CAN_FM1R_FBM5 CAN_FM1R_FBM5_Msk /*!< Filter Init Mode for filter 5 */
+#define CAN_FM1R_FBM6_Pos (6U)
+#define CAN_FM1R_FBM6_Msk (0x1U << CAN_FM1R_FBM6_Pos) /*!< 0x00000040 */
+#define CAN_FM1R_FBM6 CAN_FM1R_FBM6_Msk /*!< Filter Init Mode for filter 6 */
+#define CAN_FM1R_FBM7_Pos (7U)
+#define CAN_FM1R_FBM7_Msk (0x1U << CAN_FM1R_FBM7_Pos) /*!< 0x00000080 */
+#define CAN_FM1R_FBM7 CAN_FM1R_FBM7_Msk /*!< Filter Init Mode for filter 7 */
+#define CAN_FM1R_FBM8_Pos (8U)
+#define CAN_FM1R_FBM8_Msk (0x1U << CAN_FM1R_FBM8_Pos) /*!< 0x00000100 */
+#define CAN_FM1R_FBM8 CAN_FM1R_FBM8_Msk /*!< Filter Init Mode for filter 8 */
+#define CAN_FM1R_FBM9_Pos (9U)
+#define CAN_FM1R_FBM9_Msk (0x1U << CAN_FM1R_FBM9_Pos) /*!< 0x00000200 */
+#define CAN_FM1R_FBM9 CAN_FM1R_FBM9_Msk /*!< Filter Init Mode for filter 9 */
+#define CAN_FM1R_FBM10_Pos (10U)
+#define CAN_FM1R_FBM10_Msk (0x1U << CAN_FM1R_FBM10_Pos) /*!< 0x00000400 */
+#define CAN_FM1R_FBM10 CAN_FM1R_FBM10_Msk /*!< Filter Init Mode for filter 10 */
+#define CAN_FM1R_FBM11_Pos (11U)
+#define CAN_FM1R_FBM11_Msk (0x1U << CAN_FM1R_FBM11_Pos) /*!< 0x00000800 */
+#define CAN_FM1R_FBM11 CAN_FM1R_FBM11_Msk /*!< Filter Init Mode for filter 11 */
+#define CAN_FM1R_FBM12_Pos (12U)
+#define CAN_FM1R_FBM12_Msk (0x1U << CAN_FM1R_FBM12_Pos) /*!< 0x00001000 */
+#define CAN_FM1R_FBM12 CAN_FM1R_FBM12_Msk /*!< Filter Init Mode for filter 12 */
+#define CAN_FM1R_FBM13_Pos (13U)
+#define CAN_FM1R_FBM13_Msk (0x1U << CAN_FM1R_FBM13_Pos) /*!< 0x00002000 */
+#define CAN_FM1R_FBM13 CAN_FM1R_FBM13_Msk /*!< Filter Init Mode for filter 13 */
+
+/******************* Bit definition for CAN_FS1R register *******************/
+#define CAN_FS1R_FSC_Pos (0U)
+#define CAN_FS1R_FSC_Msk (0x3FFFU << CAN_FS1R_FSC_Pos) /*!< 0x00003FFF */
+#define CAN_FS1R_FSC CAN_FS1R_FSC_Msk /*!< Filter Scale Configuration */
+#define CAN_FS1R_FSC0_Pos (0U)
+#define CAN_FS1R_FSC0_Msk (0x1U << CAN_FS1R_FSC0_Pos) /*!< 0x00000001 */
+#define CAN_FS1R_FSC0 CAN_FS1R_FSC0_Msk /*!< Filter Scale Configuration for filter 0 */
+#define CAN_FS1R_FSC1_Pos (1U)
+#define CAN_FS1R_FSC1_Msk (0x1U << CAN_FS1R_FSC1_Pos) /*!< 0x00000002 */
+#define CAN_FS1R_FSC1 CAN_FS1R_FSC1_Msk /*!< Filter Scale Configuration for filter 1 */
+#define CAN_FS1R_FSC2_Pos (2U)
+#define CAN_FS1R_FSC2_Msk (0x1U << CAN_FS1R_FSC2_Pos) /*!< 0x00000004 */
+#define CAN_FS1R_FSC2 CAN_FS1R_FSC2_Msk /*!< Filter Scale Configuration for filter 2 */
+#define CAN_FS1R_FSC3_Pos (3U)
+#define CAN_FS1R_FSC3_Msk (0x1U << CAN_FS1R_FSC3_Pos) /*!< 0x00000008 */
+#define CAN_FS1R_FSC3 CAN_FS1R_FSC3_Msk /*!< Filter Scale Configuration for filter 3 */
+#define CAN_FS1R_FSC4_Pos (4U)
+#define CAN_FS1R_FSC4_Msk (0x1U << CAN_FS1R_FSC4_Pos) /*!< 0x00000010 */
+#define CAN_FS1R_FSC4 CAN_FS1R_FSC4_Msk /*!< Filter Scale Configuration for filter 4 */
+#define CAN_FS1R_FSC5_Pos (5U)
+#define CAN_FS1R_FSC5_Msk (0x1U << CAN_FS1R_FSC5_Pos) /*!< 0x00000020 */
+#define CAN_FS1R_FSC5 CAN_FS1R_FSC5_Msk /*!< Filter Scale Configuration for filter 5 */
+#define CAN_FS1R_FSC6_Pos (6U)
+#define CAN_FS1R_FSC6_Msk (0x1U << CAN_FS1R_FSC6_Pos) /*!< 0x00000040 */
+#define CAN_FS1R_FSC6 CAN_FS1R_FSC6_Msk /*!< Filter Scale Configuration for filter 6 */
+#define CAN_FS1R_FSC7_Pos (7U)
+#define CAN_FS1R_FSC7_Msk (0x1U << CAN_FS1R_FSC7_Pos) /*!< 0x00000080 */
+#define CAN_FS1R_FSC7 CAN_FS1R_FSC7_Msk /*!< Filter Scale Configuration for filter 7 */
+#define CAN_FS1R_FSC8_Pos (8U)
+#define CAN_FS1R_FSC8_Msk (0x1U << CAN_FS1R_FSC8_Pos) /*!< 0x00000100 */
+#define CAN_FS1R_FSC8 CAN_FS1R_FSC8_Msk /*!< Filter Scale Configuration for filter 8 */
+#define CAN_FS1R_FSC9_Pos (9U)
+#define CAN_FS1R_FSC9_Msk (0x1U << CAN_FS1R_FSC9_Pos) /*!< 0x00000200 */
+#define CAN_FS1R_FSC9 CAN_FS1R_FSC9_Msk /*!< Filter Scale Configuration for filter 9 */
+#define CAN_FS1R_FSC10_Pos (10U)
+#define CAN_FS1R_FSC10_Msk (0x1U << CAN_FS1R_FSC10_Pos) /*!< 0x00000400 */
+#define CAN_FS1R_FSC10 CAN_FS1R_FSC10_Msk /*!< Filter Scale Configuration for filter 10 */
+#define CAN_FS1R_FSC11_Pos (11U)
+#define CAN_FS1R_FSC11_Msk (0x1U << CAN_FS1R_FSC11_Pos) /*!< 0x00000800 */
+#define CAN_FS1R_FSC11 CAN_FS1R_FSC11_Msk /*!< Filter Scale Configuration for filter 11 */
+#define CAN_FS1R_FSC12_Pos (12U)
+#define CAN_FS1R_FSC12_Msk (0x1U << CAN_FS1R_FSC12_Pos) /*!< 0x00001000 */
+#define CAN_FS1R_FSC12 CAN_FS1R_FSC12_Msk /*!< Filter Scale Configuration for filter 12 */
+#define CAN_FS1R_FSC13_Pos (13U)
+#define CAN_FS1R_FSC13_Msk (0x1U << CAN_FS1R_FSC13_Pos) /*!< 0x00002000 */
+#define CAN_FS1R_FSC13 CAN_FS1R_FSC13_Msk /*!< Filter Scale Configuration for filter 13 */
+
+/****************** Bit definition for CAN_FFA1R register *******************/
+#define CAN_FFA1R_FFA_Pos (0U)
+#define CAN_FFA1R_FFA_Msk (0x3FFFU << CAN_FFA1R_FFA_Pos) /*!< 0x00003FFF */
+#define CAN_FFA1R_FFA CAN_FFA1R_FFA_Msk /*!< Filter FIFO Assignment */
+#define CAN_FFA1R_FFA0_Pos (0U)
+#define CAN_FFA1R_FFA0_Msk (0x1U << CAN_FFA1R_FFA0_Pos) /*!< 0x00000001 */
+#define CAN_FFA1R_FFA0 CAN_FFA1R_FFA0_Msk /*!< Filter FIFO Assignment for filter 0 */
+#define CAN_FFA1R_FFA1_Pos (1U)
+#define CAN_FFA1R_FFA1_Msk (0x1U << CAN_FFA1R_FFA1_Pos) /*!< 0x00000002 */
+#define CAN_FFA1R_FFA1 CAN_FFA1R_FFA1_Msk /*!< Filter FIFO Assignment for filter 1 */
+#define CAN_FFA1R_FFA2_Pos (2U)
+#define CAN_FFA1R_FFA2_Msk (0x1U << CAN_FFA1R_FFA2_Pos) /*!< 0x00000004 */
+#define CAN_FFA1R_FFA2 CAN_FFA1R_FFA2_Msk /*!< Filter FIFO Assignment for filter 2 */
+#define CAN_FFA1R_FFA3_Pos (3U)
+#define CAN_FFA1R_FFA3_Msk (0x1U << CAN_FFA1R_FFA3_Pos) /*!< 0x00000008 */
+#define CAN_FFA1R_FFA3 CAN_FFA1R_FFA3_Msk /*!< Filter FIFO Assignment for filter 3 */
+#define CAN_FFA1R_FFA4_Pos (4U)
+#define CAN_FFA1R_FFA4_Msk (0x1U << CAN_FFA1R_FFA4_Pos) /*!< 0x00000010 */
+#define CAN_FFA1R_FFA4 CAN_FFA1R_FFA4_Msk /*!< Filter FIFO Assignment for filter 4 */
+#define CAN_FFA1R_FFA5_Pos (5U)
+#define CAN_FFA1R_FFA5_Msk (0x1U << CAN_FFA1R_FFA5_Pos) /*!< 0x00000020 */
+#define CAN_FFA1R_FFA5 CAN_FFA1R_FFA5_Msk /*!< Filter FIFO Assignment for filter 5 */
+#define CAN_FFA1R_FFA6_Pos (6U)
+#define CAN_FFA1R_FFA6_Msk (0x1U << CAN_FFA1R_FFA6_Pos) /*!< 0x00000040 */
+#define CAN_FFA1R_FFA6 CAN_FFA1R_FFA6_Msk /*!< Filter FIFO Assignment for filter 6 */
+#define CAN_FFA1R_FFA7_Pos (7U)
+#define CAN_FFA1R_FFA7_Msk (0x1U << CAN_FFA1R_FFA7_Pos) /*!< 0x00000080 */
+#define CAN_FFA1R_FFA7 CAN_FFA1R_FFA7_Msk /*!< Filter FIFO Assignment for filter 7 */
+#define CAN_FFA1R_FFA8_Pos (8U)
+#define CAN_FFA1R_FFA8_Msk (0x1U << CAN_FFA1R_FFA8_Pos) /*!< 0x00000100 */
+#define CAN_FFA1R_FFA8 CAN_FFA1R_FFA8_Msk /*!< Filter FIFO Assignment for filter 8 */
+#define CAN_FFA1R_FFA9_Pos (9U)
+#define CAN_FFA1R_FFA9_Msk (0x1U << CAN_FFA1R_FFA9_Pos) /*!< 0x00000200 */
+#define CAN_FFA1R_FFA9 CAN_FFA1R_FFA9_Msk /*!< Filter FIFO Assignment for filter 9 */
+#define CAN_FFA1R_FFA10_Pos (10U)
+#define CAN_FFA1R_FFA10_Msk (0x1U << CAN_FFA1R_FFA10_Pos) /*!< 0x00000400 */
+#define CAN_FFA1R_FFA10 CAN_FFA1R_FFA10_Msk /*!< Filter FIFO Assignment for filter 10 */
+#define CAN_FFA1R_FFA11_Pos (11U)
+#define CAN_FFA1R_FFA11_Msk (0x1U << CAN_FFA1R_FFA11_Pos) /*!< 0x00000800 */
+#define CAN_FFA1R_FFA11 CAN_FFA1R_FFA11_Msk /*!< Filter FIFO Assignment for filter 11 */
+#define CAN_FFA1R_FFA12_Pos (12U)
+#define CAN_FFA1R_FFA12_Msk (0x1U << CAN_FFA1R_FFA12_Pos) /*!< 0x00001000 */
+#define CAN_FFA1R_FFA12 CAN_FFA1R_FFA12_Msk /*!< Filter FIFO Assignment for filter 12 */
+#define CAN_FFA1R_FFA13_Pos (13U)
+#define CAN_FFA1R_FFA13_Msk (0x1U << CAN_FFA1R_FFA13_Pos) /*!< 0x00002000 */
+#define CAN_FFA1R_FFA13 CAN_FFA1R_FFA13_Msk /*!< Filter FIFO Assignment for filter 13 */
+
+/******************* Bit definition for CAN_FA1R register *******************/
+#define CAN_FA1R_FACT_Pos (0U)
+#define CAN_FA1R_FACT_Msk (0x3FFFU << CAN_FA1R_FACT_Pos) /*!< 0x00003FFF */
+#define CAN_FA1R_FACT CAN_FA1R_FACT_Msk /*!< Filter Active */
+#define CAN_FA1R_FACT0_Pos (0U)
+#define CAN_FA1R_FACT0_Msk (0x1U << CAN_FA1R_FACT0_Pos) /*!< 0x00000001 */
+#define CAN_FA1R_FACT0 CAN_FA1R_FACT0_Msk /*!< Filter 0 Active */
+#define CAN_FA1R_FACT1_Pos (1U)
+#define CAN_FA1R_FACT1_Msk (0x1U << CAN_FA1R_FACT1_Pos) /*!< 0x00000002 */
+#define CAN_FA1R_FACT1 CAN_FA1R_FACT1_Msk /*!< Filter 1 Active */
+#define CAN_FA1R_FACT2_Pos (2U)
+#define CAN_FA1R_FACT2_Msk (0x1U << CAN_FA1R_FACT2_Pos) /*!< 0x00000004 */
+#define CAN_FA1R_FACT2 CAN_FA1R_FACT2_Msk /*!< Filter 2 Active */
+#define CAN_FA1R_FACT3_Pos (3U)
+#define CAN_FA1R_FACT3_Msk (0x1U << CAN_FA1R_FACT3_Pos) /*!< 0x00000008 */
+#define CAN_FA1R_FACT3 CAN_FA1R_FACT3_Msk /*!< Filter 3 Active */
+#define CAN_FA1R_FACT4_Pos (4U)
+#define CAN_FA1R_FACT4_Msk (0x1U << CAN_FA1R_FACT4_Pos) /*!< 0x00000010 */
+#define CAN_FA1R_FACT4 CAN_FA1R_FACT4_Msk /*!< Filter 4 Active */
+#define CAN_FA1R_FACT5_Pos (5U)
+#define CAN_FA1R_FACT5_Msk (0x1U << CAN_FA1R_FACT5_Pos) /*!< 0x00000020 */
+#define CAN_FA1R_FACT5 CAN_FA1R_FACT5_Msk /*!< Filter 5 Active */
+#define CAN_FA1R_FACT6_Pos (6U)
+#define CAN_FA1R_FACT6_Msk (0x1U << CAN_FA1R_FACT6_Pos) /*!< 0x00000040 */
+#define CAN_FA1R_FACT6 CAN_FA1R_FACT6_Msk /*!< Filter 6 Active */
+#define CAN_FA1R_FACT7_Pos (7U)
+#define CAN_FA1R_FACT7_Msk (0x1U << CAN_FA1R_FACT7_Pos) /*!< 0x00000080 */
+#define CAN_FA1R_FACT7 CAN_FA1R_FACT7_Msk /*!< Filter 7 Active */
+#define CAN_FA1R_FACT8_Pos (8U)
+#define CAN_FA1R_FACT8_Msk (0x1U << CAN_FA1R_FACT8_Pos) /*!< 0x00000100 */
+#define CAN_FA1R_FACT8 CAN_FA1R_FACT8_Msk /*!< Filter 8 Active */
+#define CAN_FA1R_FACT9_Pos (9U)
+#define CAN_FA1R_FACT9_Msk (0x1U << CAN_FA1R_FACT9_Pos) /*!< 0x00000200 */
+#define CAN_FA1R_FACT9 CAN_FA1R_FACT9_Msk /*!< Filter 9 Active */
+#define CAN_FA1R_FACT10_Pos (10U)
+#define CAN_FA1R_FACT10_Msk (0x1U << CAN_FA1R_FACT10_Pos) /*!< 0x00000400 */
+#define CAN_FA1R_FACT10 CAN_FA1R_FACT10_Msk /*!< Filter 10 Active */
+#define CAN_FA1R_FACT11_Pos (11U)
+#define CAN_FA1R_FACT11_Msk (0x1U << CAN_FA1R_FACT11_Pos) /*!< 0x00000800 */
+#define CAN_FA1R_FACT11 CAN_FA1R_FACT11_Msk /*!< Filter 11 Active */
+#define CAN_FA1R_FACT12_Pos (12U)
+#define CAN_FA1R_FACT12_Msk (0x1U << CAN_FA1R_FACT12_Pos) /*!< 0x00001000 */
+#define CAN_FA1R_FACT12 CAN_FA1R_FACT12_Msk /*!< Filter 12 Active */
+#define CAN_FA1R_FACT13_Pos (13U)
+#define CAN_FA1R_FACT13_Msk (0x1U << CAN_FA1R_FACT13_Pos) /*!< 0x00002000 */
+#define CAN_FA1R_FACT13 CAN_FA1R_FACT13_Msk /*!< Filter 13 Active */
+
+/******************* Bit definition for CAN_F0R1 register *******************/
+#define CAN_F0R1_FB0_Pos (0U)
+#define CAN_F0R1_FB0_Msk (0x1U << CAN_F0R1_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F0R1_FB0 CAN_F0R1_FB0_Msk /*!< Filter bit 0 */
+#define CAN_F0R1_FB1_Pos (1U)
+#define CAN_F0R1_FB1_Msk (0x1U << CAN_F0R1_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F0R1_FB1 CAN_F0R1_FB1_Msk /*!< Filter bit 1 */
+#define CAN_F0R1_FB2_Pos (2U)
+#define CAN_F0R1_FB2_Msk (0x1U << CAN_F0R1_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F0R1_FB2 CAN_F0R1_FB2_Msk /*!< Filter bit 2 */
+#define CAN_F0R1_FB3_Pos (3U)
+#define CAN_F0R1_FB3_Msk (0x1U << CAN_F0R1_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F0R1_FB3 CAN_F0R1_FB3_Msk /*!< Filter bit 3 */
+#define CAN_F0R1_FB4_Pos (4U)
+#define CAN_F0R1_FB4_Msk (0x1U << CAN_F0R1_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F0R1_FB4 CAN_F0R1_FB4_Msk /*!< Filter bit 4 */
+#define CAN_F0R1_FB5_Pos (5U)
+#define CAN_F0R1_FB5_Msk (0x1U << CAN_F0R1_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F0R1_FB5 CAN_F0R1_FB5_Msk /*!< Filter bit 5 */
+#define CAN_F0R1_FB6_Pos (6U)
+#define CAN_F0R1_FB6_Msk (0x1U << CAN_F0R1_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F0R1_FB6 CAN_F0R1_FB6_Msk /*!< Filter bit 6 */
+#define CAN_F0R1_FB7_Pos (7U)
+#define CAN_F0R1_FB7_Msk (0x1U << CAN_F0R1_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F0R1_FB7 CAN_F0R1_FB7_Msk /*!< Filter bit 7 */
+#define CAN_F0R1_FB8_Pos (8U)
+#define CAN_F0R1_FB8_Msk (0x1U << CAN_F0R1_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F0R1_FB8 CAN_F0R1_FB8_Msk /*!< Filter bit 8 */
+#define CAN_F0R1_FB9_Pos (9U)
+#define CAN_F0R1_FB9_Msk (0x1U << CAN_F0R1_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F0R1_FB9 CAN_F0R1_FB9_Msk /*!< Filter bit 9 */
+#define CAN_F0R1_FB10_Pos (10U)
+#define CAN_F0R1_FB10_Msk (0x1U << CAN_F0R1_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F0R1_FB10 CAN_F0R1_FB10_Msk /*!< Filter bit 10 */
+#define CAN_F0R1_FB11_Pos (11U)
+#define CAN_F0R1_FB11_Msk (0x1U << CAN_F0R1_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F0R1_FB11 CAN_F0R1_FB11_Msk /*!< Filter bit 11 */
+#define CAN_F0R1_FB12_Pos (12U)
+#define CAN_F0R1_FB12_Msk (0x1U << CAN_F0R1_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F0R1_FB12 CAN_F0R1_FB12_Msk /*!< Filter bit 12 */
+#define CAN_F0R1_FB13_Pos (13U)
+#define CAN_F0R1_FB13_Msk (0x1U << CAN_F0R1_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F0R1_FB13 CAN_F0R1_FB13_Msk /*!< Filter bit 13 */
+#define CAN_F0R1_FB14_Pos (14U)
+#define CAN_F0R1_FB14_Msk (0x1U << CAN_F0R1_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F0R1_FB14 CAN_F0R1_FB14_Msk /*!< Filter bit 14 */
+#define CAN_F0R1_FB15_Pos (15U)
+#define CAN_F0R1_FB15_Msk (0x1U << CAN_F0R1_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F0R1_FB15 CAN_F0R1_FB15_Msk /*!< Filter bit 15 */
+#define CAN_F0R1_FB16_Pos (16U)
+#define CAN_F0R1_FB16_Msk (0x1U << CAN_F0R1_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F0R1_FB16 CAN_F0R1_FB16_Msk /*!< Filter bit 16 */
+#define CAN_F0R1_FB17_Pos (17U)
+#define CAN_F0R1_FB17_Msk (0x1U << CAN_F0R1_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F0R1_FB17 CAN_F0R1_FB17_Msk /*!< Filter bit 17 */
+#define CAN_F0R1_FB18_Pos (18U)
+#define CAN_F0R1_FB18_Msk (0x1U << CAN_F0R1_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F0R1_FB18 CAN_F0R1_FB18_Msk /*!< Filter bit 18 */
+#define CAN_F0R1_FB19_Pos (19U)
+#define CAN_F0R1_FB19_Msk (0x1U << CAN_F0R1_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F0R1_FB19 CAN_F0R1_FB19_Msk /*!< Filter bit 19 */
+#define CAN_F0R1_FB20_Pos (20U)
+#define CAN_F0R1_FB20_Msk (0x1U << CAN_F0R1_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F0R1_FB20 CAN_F0R1_FB20_Msk /*!< Filter bit 20 */
+#define CAN_F0R1_FB21_Pos (21U)
+#define CAN_F0R1_FB21_Msk (0x1U << CAN_F0R1_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F0R1_FB21 CAN_F0R1_FB21_Msk /*!< Filter bit 21 */
+#define CAN_F0R1_FB22_Pos (22U)
+#define CAN_F0R1_FB22_Msk (0x1U << CAN_F0R1_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F0R1_FB22 CAN_F0R1_FB22_Msk /*!< Filter bit 22 */
+#define CAN_F0R1_FB23_Pos (23U)
+#define CAN_F0R1_FB23_Msk (0x1U << CAN_F0R1_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F0R1_FB23 CAN_F0R1_FB23_Msk /*!< Filter bit 23 */
+#define CAN_F0R1_FB24_Pos (24U)
+#define CAN_F0R1_FB24_Msk (0x1U << CAN_F0R1_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F0R1_FB24 CAN_F0R1_FB24_Msk /*!< Filter bit 24 */
+#define CAN_F0R1_FB25_Pos (25U)
+#define CAN_F0R1_FB25_Msk (0x1U << CAN_F0R1_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F0R1_FB25 CAN_F0R1_FB25_Msk /*!< Filter bit 25 */
+#define CAN_F0R1_FB26_Pos (26U)
+#define CAN_F0R1_FB26_Msk (0x1U << CAN_F0R1_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F0R1_FB26 CAN_F0R1_FB26_Msk /*!< Filter bit 26 */
+#define CAN_F0R1_FB27_Pos (27U)
+#define CAN_F0R1_FB27_Msk (0x1U << CAN_F0R1_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F0R1_FB27 CAN_F0R1_FB27_Msk /*!< Filter bit 27 */
+#define CAN_F0R1_FB28_Pos (28U)
+#define CAN_F0R1_FB28_Msk (0x1U << CAN_F0R1_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F0R1_FB28 CAN_F0R1_FB28_Msk /*!< Filter bit 28 */
+#define CAN_F0R1_FB29_Pos (29U)
+#define CAN_F0R1_FB29_Msk (0x1U << CAN_F0R1_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F0R1_FB29 CAN_F0R1_FB29_Msk /*!< Filter bit 29 */
+#define CAN_F0R1_FB30_Pos (30U)
+#define CAN_F0R1_FB30_Msk (0x1U << CAN_F0R1_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F0R1_FB30 CAN_F0R1_FB30_Msk /*!< Filter bit 30 */
+#define CAN_F0R1_FB31_Pos (31U)
+#define CAN_F0R1_FB31_Msk (0x1U << CAN_F0R1_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F0R1_FB31 CAN_F0R1_FB31_Msk /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F1R1 register *******************/
+#define CAN_F1R1_FB0_Pos (0U)
+#define CAN_F1R1_FB0_Msk (0x1U << CAN_F1R1_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F1R1_FB0 CAN_F1R1_FB0_Msk /*!< Filter bit 0 */
+#define CAN_F1R1_FB1_Pos (1U)
+#define CAN_F1R1_FB1_Msk (0x1U << CAN_F1R1_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F1R1_FB1 CAN_F1R1_FB1_Msk /*!< Filter bit 1 */
+#define CAN_F1R1_FB2_Pos (2U)
+#define CAN_F1R1_FB2_Msk (0x1U << CAN_F1R1_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F1R1_FB2 CAN_F1R1_FB2_Msk /*!< Filter bit 2 */
+#define CAN_F1R1_FB3_Pos (3U)
+#define CAN_F1R1_FB3_Msk (0x1U << CAN_F1R1_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F1R1_FB3 CAN_F1R1_FB3_Msk /*!< Filter bit 3 */
+#define CAN_F1R1_FB4_Pos (4U)
+#define CAN_F1R1_FB4_Msk (0x1U << CAN_F1R1_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F1R1_FB4 CAN_F1R1_FB4_Msk /*!< Filter bit 4 */
+#define CAN_F1R1_FB5_Pos (5U)
+#define CAN_F1R1_FB5_Msk (0x1U << CAN_F1R1_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F1R1_FB5 CAN_F1R1_FB5_Msk /*!< Filter bit 5 */
+#define CAN_F1R1_FB6_Pos (6U)
+#define CAN_F1R1_FB6_Msk (0x1U << CAN_F1R1_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F1R1_FB6 CAN_F1R1_FB6_Msk /*!< Filter bit 6 */
+#define CAN_F1R1_FB7_Pos (7U)
+#define CAN_F1R1_FB7_Msk (0x1U << CAN_F1R1_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F1R1_FB7 CAN_F1R1_FB7_Msk /*!< Filter bit 7 */
+#define CAN_F1R1_FB8_Pos (8U)
+#define CAN_F1R1_FB8_Msk (0x1U << CAN_F1R1_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F1R1_FB8 CAN_F1R1_FB8_Msk /*!< Filter bit 8 */
+#define CAN_F1R1_FB9_Pos (9U)
+#define CAN_F1R1_FB9_Msk (0x1U << CAN_F1R1_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F1R1_FB9 CAN_F1R1_FB9_Msk /*!< Filter bit 9 */
+#define CAN_F1R1_FB10_Pos (10U)
+#define CAN_F1R1_FB10_Msk (0x1U << CAN_F1R1_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F1R1_FB10 CAN_F1R1_FB10_Msk /*!< Filter bit 10 */
+#define CAN_F1R1_FB11_Pos (11U)
+#define CAN_F1R1_FB11_Msk (0x1U << CAN_F1R1_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F1R1_FB11 CAN_F1R1_FB11_Msk /*!< Filter bit 11 */
+#define CAN_F1R1_FB12_Pos (12U)
+#define CAN_F1R1_FB12_Msk (0x1U << CAN_F1R1_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F1R1_FB12 CAN_F1R1_FB12_Msk /*!< Filter bit 12 */
+#define CAN_F1R1_FB13_Pos (13U)
+#define CAN_F1R1_FB13_Msk (0x1U << CAN_F1R1_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F1R1_FB13 CAN_F1R1_FB13_Msk /*!< Filter bit 13 */
+#define CAN_F1R1_FB14_Pos (14U)
+#define CAN_F1R1_FB14_Msk (0x1U << CAN_F1R1_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F1R1_FB14 CAN_F1R1_FB14_Msk /*!< Filter bit 14 */
+#define CAN_F1R1_FB15_Pos (15U)
+#define CAN_F1R1_FB15_Msk (0x1U << CAN_F1R1_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F1R1_FB15 CAN_F1R1_FB15_Msk /*!< Filter bit 15 */
+#define CAN_F1R1_FB16_Pos (16U)
+#define CAN_F1R1_FB16_Msk (0x1U << CAN_F1R1_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F1R1_FB16 CAN_F1R1_FB16_Msk /*!< Filter bit 16 */
+#define CAN_F1R1_FB17_Pos (17U)
+#define CAN_F1R1_FB17_Msk (0x1U << CAN_F1R1_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F1R1_FB17 CAN_F1R1_FB17_Msk /*!< Filter bit 17 */
+#define CAN_F1R1_FB18_Pos (18U)
+#define CAN_F1R1_FB18_Msk (0x1U << CAN_F1R1_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F1R1_FB18 CAN_F1R1_FB18_Msk /*!< Filter bit 18 */
+#define CAN_F1R1_FB19_Pos (19U)
+#define CAN_F1R1_FB19_Msk (0x1U << CAN_F1R1_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F1R1_FB19 CAN_F1R1_FB19_Msk /*!< Filter bit 19 */
+#define CAN_F1R1_FB20_Pos (20U)
+#define CAN_F1R1_FB20_Msk (0x1U << CAN_F1R1_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F1R1_FB20 CAN_F1R1_FB20_Msk /*!< Filter bit 20 */
+#define CAN_F1R1_FB21_Pos (21U)
+#define CAN_F1R1_FB21_Msk (0x1U << CAN_F1R1_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F1R1_FB21 CAN_F1R1_FB21_Msk /*!< Filter bit 21 */
+#define CAN_F1R1_FB22_Pos (22U)
+#define CAN_F1R1_FB22_Msk (0x1U << CAN_F1R1_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F1R1_FB22 CAN_F1R1_FB22_Msk /*!< Filter bit 22 */
+#define CAN_F1R1_FB23_Pos (23U)
+#define CAN_F1R1_FB23_Msk (0x1U << CAN_F1R1_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F1R1_FB23 CAN_F1R1_FB23_Msk /*!< Filter bit 23 */
+#define CAN_F1R1_FB24_Pos (24U)
+#define CAN_F1R1_FB24_Msk (0x1U << CAN_F1R1_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F1R1_FB24 CAN_F1R1_FB24_Msk /*!< Filter bit 24 */
+#define CAN_F1R1_FB25_Pos (25U)
+#define CAN_F1R1_FB25_Msk (0x1U << CAN_F1R1_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F1R1_FB25 CAN_F1R1_FB25_Msk /*!< Filter bit 25 */
+#define CAN_F1R1_FB26_Pos (26U)
+#define CAN_F1R1_FB26_Msk (0x1U << CAN_F1R1_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F1R1_FB26 CAN_F1R1_FB26_Msk /*!< Filter bit 26 */
+#define CAN_F1R1_FB27_Pos (27U)
+#define CAN_F1R1_FB27_Msk (0x1U << CAN_F1R1_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F1R1_FB27 CAN_F1R1_FB27_Msk /*!< Filter bit 27 */
+#define CAN_F1R1_FB28_Pos (28U)
+#define CAN_F1R1_FB28_Msk (0x1U << CAN_F1R1_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F1R1_FB28 CAN_F1R1_FB28_Msk /*!< Filter bit 28 */
+#define CAN_F1R1_FB29_Pos (29U)
+#define CAN_F1R1_FB29_Msk (0x1U << CAN_F1R1_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F1R1_FB29 CAN_F1R1_FB29_Msk /*!< Filter bit 29 */
+#define CAN_F1R1_FB30_Pos (30U)
+#define CAN_F1R1_FB30_Msk (0x1U << CAN_F1R1_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F1R1_FB30 CAN_F1R1_FB30_Msk /*!< Filter bit 30 */
+#define CAN_F1R1_FB31_Pos (31U)
+#define CAN_F1R1_FB31_Msk (0x1U << CAN_F1R1_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F1R1_FB31 CAN_F1R1_FB31_Msk /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F2R1 register *******************/
+#define CAN_F2R1_FB0_Pos (0U)
+#define CAN_F2R1_FB0_Msk (0x1U << CAN_F2R1_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F2R1_FB0 CAN_F2R1_FB0_Msk /*!< Filter bit 0 */
+#define CAN_F2R1_FB1_Pos (1U)
+#define CAN_F2R1_FB1_Msk (0x1U << CAN_F2R1_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F2R1_FB1 CAN_F2R1_FB1_Msk /*!< Filter bit 1 */
+#define CAN_F2R1_FB2_Pos (2U)
+#define CAN_F2R1_FB2_Msk (0x1U << CAN_F2R1_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F2R1_FB2 CAN_F2R1_FB2_Msk /*!< Filter bit 2 */
+#define CAN_F2R1_FB3_Pos (3U)
+#define CAN_F2R1_FB3_Msk (0x1U << CAN_F2R1_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F2R1_FB3 CAN_F2R1_FB3_Msk /*!< Filter bit 3 */
+#define CAN_F2R1_FB4_Pos (4U)
+#define CAN_F2R1_FB4_Msk (0x1U << CAN_F2R1_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F2R1_FB4 CAN_F2R1_FB4_Msk /*!< Filter bit 4 */
+#define CAN_F2R1_FB5_Pos (5U)
+#define CAN_F2R1_FB5_Msk (0x1U << CAN_F2R1_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F2R1_FB5 CAN_F2R1_FB5_Msk /*!< Filter bit 5 */
+#define CAN_F2R1_FB6_Pos (6U)
+#define CAN_F2R1_FB6_Msk (0x1U << CAN_F2R1_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F2R1_FB6 CAN_F2R1_FB6_Msk /*!< Filter bit 6 */
+#define CAN_F2R1_FB7_Pos (7U)
+#define CAN_F2R1_FB7_Msk (0x1U << CAN_F2R1_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F2R1_FB7 CAN_F2R1_FB7_Msk /*!< Filter bit 7 */
+#define CAN_F2R1_FB8_Pos (8U)
+#define CAN_F2R1_FB8_Msk (0x1U << CAN_F2R1_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F2R1_FB8 CAN_F2R1_FB8_Msk /*!< Filter bit 8 */
+#define CAN_F2R1_FB9_Pos (9U)
+#define CAN_F2R1_FB9_Msk (0x1U << CAN_F2R1_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F2R1_FB9 CAN_F2R1_FB9_Msk /*!< Filter bit 9 */
+#define CAN_F2R1_FB10_Pos (10U)
+#define CAN_F2R1_FB10_Msk (0x1U << CAN_F2R1_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F2R1_FB10 CAN_F2R1_FB10_Msk /*!< Filter bit 10 */
+#define CAN_F2R1_FB11_Pos (11U)
+#define CAN_F2R1_FB11_Msk (0x1U << CAN_F2R1_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F2R1_FB11 CAN_F2R1_FB11_Msk /*!< Filter bit 11 */
+#define CAN_F2R1_FB12_Pos (12U)
+#define CAN_F2R1_FB12_Msk (0x1U << CAN_F2R1_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F2R1_FB12 CAN_F2R1_FB12_Msk /*!< Filter bit 12 */
+#define CAN_F2R1_FB13_Pos (13U)
+#define CAN_F2R1_FB13_Msk (0x1U << CAN_F2R1_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F2R1_FB13 CAN_F2R1_FB13_Msk /*!< Filter bit 13 */
+#define CAN_F2R1_FB14_Pos (14U)
+#define CAN_F2R1_FB14_Msk (0x1U << CAN_F2R1_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F2R1_FB14 CAN_F2R1_FB14_Msk /*!< Filter bit 14 */
+#define CAN_F2R1_FB15_Pos (15U)
+#define CAN_F2R1_FB15_Msk (0x1U << CAN_F2R1_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F2R1_FB15 CAN_F2R1_FB15_Msk /*!< Filter bit 15 */
+#define CAN_F2R1_FB16_Pos (16U)
+#define CAN_F2R1_FB16_Msk (0x1U << CAN_F2R1_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F2R1_FB16 CAN_F2R1_FB16_Msk /*!< Filter bit 16 */
+#define CAN_F2R1_FB17_Pos (17U)
+#define CAN_F2R1_FB17_Msk (0x1U << CAN_F2R1_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F2R1_FB17 CAN_F2R1_FB17_Msk /*!< Filter bit 17 */
+#define CAN_F2R1_FB18_Pos (18U)
+#define CAN_F2R1_FB18_Msk (0x1U << CAN_F2R1_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F2R1_FB18 CAN_F2R1_FB18_Msk /*!< Filter bit 18 */
+#define CAN_F2R1_FB19_Pos (19U)
+#define CAN_F2R1_FB19_Msk (0x1U << CAN_F2R1_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F2R1_FB19 CAN_F2R1_FB19_Msk /*!< Filter bit 19 */
+#define CAN_F2R1_FB20_Pos (20U)
+#define CAN_F2R1_FB20_Msk (0x1U << CAN_F2R1_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F2R1_FB20 CAN_F2R1_FB20_Msk /*!< Filter bit 20 */
+#define CAN_F2R1_FB21_Pos (21U)
+#define CAN_F2R1_FB21_Msk (0x1U << CAN_F2R1_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F2R1_FB21 CAN_F2R1_FB21_Msk /*!< Filter bit 21 */
+#define CAN_F2R1_FB22_Pos (22U)
+#define CAN_F2R1_FB22_Msk (0x1U << CAN_F2R1_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F2R1_FB22 CAN_F2R1_FB22_Msk /*!< Filter bit 22 */
+#define CAN_F2R1_FB23_Pos (23U)
+#define CAN_F2R1_FB23_Msk (0x1U << CAN_F2R1_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F2R1_FB23 CAN_F2R1_FB23_Msk /*!< Filter bit 23 */
+#define CAN_F2R1_FB24_Pos (24U)
+#define CAN_F2R1_FB24_Msk (0x1U << CAN_F2R1_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F2R1_FB24 CAN_F2R1_FB24_Msk /*!< Filter bit 24 */
+#define CAN_F2R1_FB25_Pos (25U)
+#define CAN_F2R1_FB25_Msk (0x1U << CAN_F2R1_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F2R1_FB25 CAN_F2R1_FB25_Msk /*!< Filter bit 25 */
+#define CAN_F2R1_FB26_Pos (26U)
+#define CAN_F2R1_FB26_Msk (0x1U << CAN_F2R1_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F2R1_FB26 CAN_F2R1_FB26_Msk /*!< Filter bit 26 */
+#define CAN_F2R1_FB27_Pos (27U)
+#define CAN_F2R1_FB27_Msk (0x1U << CAN_F2R1_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F2R1_FB27 CAN_F2R1_FB27_Msk /*!< Filter bit 27 */
+#define CAN_F2R1_FB28_Pos (28U)
+#define CAN_F2R1_FB28_Msk (0x1U << CAN_F2R1_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F2R1_FB28 CAN_F2R1_FB28_Msk /*!< Filter bit 28 */
+#define CAN_F2R1_FB29_Pos (29U)
+#define CAN_F2R1_FB29_Msk (0x1U << CAN_F2R1_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F2R1_FB29 CAN_F2R1_FB29_Msk /*!< Filter bit 29 */
+#define CAN_F2R1_FB30_Pos (30U)
+#define CAN_F2R1_FB30_Msk (0x1U << CAN_F2R1_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F2R1_FB30 CAN_F2R1_FB30_Msk /*!< Filter bit 30 */
+#define CAN_F2R1_FB31_Pos (31U)
+#define CAN_F2R1_FB31_Msk (0x1U << CAN_F2R1_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F2R1_FB31 CAN_F2R1_FB31_Msk /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F3R1 register *******************/
+#define CAN_F3R1_FB0_Pos (0U)
+#define CAN_F3R1_FB0_Msk (0x1U << CAN_F3R1_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F3R1_FB0 CAN_F3R1_FB0_Msk /*!< Filter bit 0 */
+#define CAN_F3R1_FB1_Pos (1U)
+#define CAN_F3R1_FB1_Msk (0x1U << CAN_F3R1_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F3R1_FB1 CAN_F3R1_FB1_Msk /*!< Filter bit 1 */
+#define CAN_F3R1_FB2_Pos (2U)
+#define CAN_F3R1_FB2_Msk (0x1U << CAN_F3R1_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F3R1_FB2 CAN_F3R1_FB2_Msk /*!< Filter bit 2 */
+#define CAN_F3R1_FB3_Pos (3U)
+#define CAN_F3R1_FB3_Msk (0x1U << CAN_F3R1_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F3R1_FB3 CAN_F3R1_FB3_Msk /*!< Filter bit 3 */
+#define CAN_F3R1_FB4_Pos (4U)
+#define CAN_F3R1_FB4_Msk (0x1U << CAN_F3R1_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F3R1_FB4 CAN_F3R1_FB4_Msk /*!< Filter bit 4 */
+#define CAN_F3R1_FB5_Pos (5U)
+#define CAN_F3R1_FB5_Msk (0x1U << CAN_F3R1_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F3R1_FB5 CAN_F3R1_FB5_Msk /*!< Filter bit 5 */
+#define CAN_F3R1_FB6_Pos (6U)
+#define CAN_F3R1_FB6_Msk (0x1U << CAN_F3R1_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F3R1_FB6 CAN_F3R1_FB6_Msk /*!< Filter bit 6 */
+#define CAN_F3R1_FB7_Pos (7U)
+#define CAN_F3R1_FB7_Msk (0x1U << CAN_F3R1_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F3R1_FB7 CAN_F3R1_FB7_Msk /*!< Filter bit 7 */
+#define CAN_F3R1_FB8_Pos (8U)
+#define CAN_F3R1_FB8_Msk (0x1U << CAN_F3R1_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F3R1_FB8 CAN_F3R1_FB8_Msk /*!< Filter bit 8 */
+#define CAN_F3R1_FB9_Pos (9U)
+#define CAN_F3R1_FB9_Msk (0x1U << CAN_F3R1_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F3R1_FB9 CAN_F3R1_FB9_Msk /*!< Filter bit 9 */
+#define CAN_F3R1_FB10_Pos (10U)
+#define CAN_F3R1_FB10_Msk (0x1U << CAN_F3R1_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F3R1_FB10 CAN_F3R1_FB10_Msk /*!< Filter bit 10 */
+#define CAN_F3R1_FB11_Pos (11U)
+#define CAN_F3R1_FB11_Msk (0x1U << CAN_F3R1_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F3R1_FB11 CAN_F3R1_FB11_Msk /*!< Filter bit 11 */
+#define CAN_F3R1_FB12_Pos (12U)
+#define CAN_F3R1_FB12_Msk (0x1U << CAN_F3R1_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F3R1_FB12 CAN_F3R1_FB12_Msk /*!< Filter bit 12 */
+#define CAN_F3R1_FB13_Pos (13U)
+#define CAN_F3R1_FB13_Msk (0x1U << CAN_F3R1_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F3R1_FB13 CAN_F3R1_FB13_Msk /*!< Filter bit 13 */
+#define CAN_F3R1_FB14_Pos (14U)
+#define CAN_F3R1_FB14_Msk (0x1U << CAN_F3R1_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F3R1_FB14 CAN_F3R1_FB14_Msk /*!< Filter bit 14 */
+#define CAN_F3R1_FB15_Pos (15U)
+#define CAN_F3R1_FB15_Msk (0x1U << CAN_F3R1_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F3R1_FB15 CAN_F3R1_FB15_Msk /*!< Filter bit 15 */
+#define CAN_F3R1_FB16_Pos (16U)
+#define CAN_F3R1_FB16_Msk (0x1U << CAN_F3R1_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F3R1_FB16 CAN_F3R1_FB16_Msk /*!< Filter bit 16 */
+#define CAN_F3R1_FB17_Pos (17U)
+#define CAN_F3R1_FB17_Msk (0x1U << CAN_F3R1_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F3R1_FB17 CAN_F3R1_FB17_Msk /*!< Filter bit 17 */
+#define CAN_F3R1_FB18_Pos (18U)
+#define CAN_F3R1_FB18_Msk (0x1U << CAN_F3R1_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F3R1_FB18 CAN_F3R1_FB18_Msk /*!< Filter bit 18 */
+#define CAN_F3R1_FB19_Pos (19U)
+#define CAN_F3R1_FB19_Msk (0x1U << CAN_F3R1_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F3R1_FB19 CAN_F3R1_FB19_Msk /*!< Filter bit 19 */
+#define CAN_F3R1_FB20_Pos (20U)
+#define CAN_F3R1_FB20_Msk (0x1U << CAN_F3R1_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F3R1_FB20 CAN_F3R1_FB20_Msk /*!< Filter bit 20 */
+#define CAN_F3R1_FB21_Pos (21U)
+#define CAN_F3R1_FB21_Msk (0x1U << CAN_F3R1_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F3R1_FB21 CAN_F3R1_FB21_Msk /*!< Filter bit 21 */
+#define CAN_F3R1_FB22_Pos (22U)
+#define CAN_F3R1_FB22_Msk (0x1U << CAN_F3R1_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F3R1_FB22 CAN_F3R1_FB22_Msk /*!< Filter bit 22 */
+#define CAN_F3R1_FB23_Pos (23U)
+#define CAN_F3R1_FB23_Msk (0x1U << CAN_F3R1_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F3R1_FB23 CAN_F3R1_FB23_Msk /*!< Filter bit 23 */
+#define CAN_F3R1_FB24_Pos (24U)
+#define CAN_F3R1_FB24_Msk (0x1U << CAN_F3R1_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F3R1_FB24 CAN_F3R1_FB24_Msk /*!< Filter bit 24 */
+#define CAN_F3R1_FB25_Pos (25U)
+#define CAN_F3R1_FB25_Msk (0x1U << CAN_F3R1_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F3R1_FB25 CAN_F3R1_FB25_Msk /*!< Filter bit 25 */
+#define CAN_F3R1_FB26_Pos (26U)
+#define CAN_F3R1_FB26_Msk (0x1U << CAN_F3R1_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F3R1_FB26 CAN_F3R1_FB26_Msk /*!< Filter bit 26 */
+#define CAN_F3R1_FB27_Pos (27U)
+#define CAN_F3R1_FB27_Msk (0x1U << CAN_F3R1_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F3R1_FB27 CAN_F3R1_FB27_Msk /*!< Filter bit 27 */
+#define CAN_F3R1_FB28_Pos (28U)
+#define CAN_F3R1_FB28_Msk (0x1U << CAN_F3R1_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F3R1_FB28 CAN_F3R1_FB28_Msk /*!< Filter bit 28 */
+#define CAN_F3R1_FB29_Pos (29U)
+#define CAN_F3R1_FB29_Msk (0x1U << CAN_F3R1_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F3R1_FB29 CAN_F3R1_FB29_Msk /*!< Filter bit 29 */
+#define CAN_F3R1_FB30_Pos (30U)
+#define CAN_F3R1_FB30_Msk (0x1U << CAN_F3R1_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F3R1_FB30 CAN_F3R1_FB30_Msk /*!< Filter bit 30 */
+#define CAN_F3R1_FB31_Pos (31U)
+#define CAN_F3R1_FB31_Msk (0x1U << CAN_F3R1_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F3R1_FB31 CAN_F3R1_FB31_Msk /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F4R1 register *******************/
+#define CAN_F4R1_FB0_Pos (0U)
+#define CAN_F4R1_FB0_Msk (0x1U << CAN_F4R1_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F4R1_FB0 CAN_F4R1_FB0_Msk /*!< Filter bit 0 */
+#define CAN_F4R1_FB1_Pos (1U)
+#define CAN_F4R1_FB1_Msk (0x1U << CAN_F4R1_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F4R1_FB1 CAN_F4R1_FB1_Msk /*!< Filter bit 1 */
+#define CAN_F4R1_FB2_Pos (2U)
+#define CAN_F4R1_FB2_Msk (0x1U << CAN_F4R1_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F4R1_FB2 CAN_F4R1_FB2_Msk /*!< Filter bit 2 */
+#define CAN_F4R1_FB3_Pos (3U)
+#define CAN_F4R1_FB3_Msk (0x1U << CAN_F4R1_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F4R1_FB3 CAN_F4R1_FB3_Msk /*!< Filter bit 3 */
+#define CAN_F4R1_FB4_Pos (4U)
+#define CAN_F4R1_FB4_Msk (0x1U << CAN_F4R1_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F4R1_FB4 CAN_F4R1_FB4_Msk /*!< Filter bit 4 */
+#define CAN_F4R1_FB5_Pos (5U)
+#define CAN_F4R1_FB5_Msk (0x1U << CAN_F4R1_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F4R1_FB5 CAN_F4R1_FB5_Msk /*!< Filter bit 5 */
+#define CAN_F4R1_FB6_Pos (6U)
+#define CAN_F4R1_FB6_Msk (0x1U << CAN_F4R1_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F4R1_FB6 CAN_F4R1_FB6_Msk /*!< Filter bit 6 */
+#define CAN_F4R1_FB7_Pos (7U)
+#define CAN_F4R1_FB7_Msk (0x1U << CAN_F4R1_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F4R1_FB7 CAN_F4R1_FB7_Msk /*!< Filter bit 7 */
+#define CAN_F4R1_FB8_Pos (8U)
+#define CAN_F4R1_FB8_Msk (0x1U << CAN_F4R1_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F4R1_FB8 CAN_F4R1_FB8_Msk /*!< Filter bit 8 */
+#define CAN_F4R1_FB9_Pos (9U)
+#define CAN_F4R1_FB9_Msk (0x1U << CAN_F4R1_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F4R1_FB9 CAN_F4R1_FB9_Msk /*!< Filter bit 9 */
+#define CAN_F4R1_FB10_Pos (10U)
+#define CAN_F4R1_FB10_Msk (0x1U << CAN_F4R1_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F4R1_FB10 CAN_F4R1_FB10_Msk /*!< Filter bit 10 */
+#define CAN_F4R1_FB11_Pos (11U)
+#define CAN_F4R1_FB11_Msk (0x1U << CAN_F4R1_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F4R1_FB11 CAN_F4R1_FB11_Msk /*!< Filter bit 11 */
+#define CAN_F4R1_FB12_Pos (12U)
+#define CAN_F4R1_FB12_Msk (0x1U << CAN_F4R1_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F4R1_FB12 CAN_F4R1_FB12_Msk /*!< Filter bit 12 */
+#define CAN_F4R1_FB13_Pos (13U)
+#define CAN_F4R1_FB13_Msk (0x1U << CAN_F4R1_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F4R1_FB13 CAN_F4R1_FB13_Msk /*!< Filter bit 13 */
+#define CAN_F4R1_FB14_Pos (14U)
+#define CAN_F4R1_FB14_Msk (0x1U << CAN_F4R1_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F4R1_FB14 CAN_F4R1_FB14_Msk /*!< Filter bit 14 */
+#define CAN_F4R1_FB15_Pos (15U)
+#define CAN_F4R1_FB15_Msk (0x1U << CAN_F4R1_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F4R1_FB15 CAN_F4R1_FB15_Msk /*!< Filter bit 15 */
+#define CAN_F4R1_FB16_Pos (16U)
+#define CAN_F4R1_FB16_Msk (0x1U << CAN_F4R1_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F4R1_FB16 CAN_F4R1_FB16_Msk /*!< Filter bit 16 */
+#define CAN_F4R1_FB17_Pos (17U)
+#define CAN_F4R1_FB17_Msk (0x1U << CAN_F4R1_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F4R1_FB17 CAN_F4R1_FB17_Msk /*!< Filter bit 17 */
+#define CAN_F4R1_FB18_Pos (18U)
+#define CAN_F4R1_FB18_Msk (0x1U << CAN_F4R1_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F4R1_FB18 CAN_F4R1_FB18_Msk /*!< Filter bit 18 */
+#define CAN_F4R1_FB19_Pos (19U)
+#define CAN_F4R1_FB19_Msk (0x1U << CAN_F4R1_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F4R1_FB19 CAN_F4R1_FB19_Msk /*!< Filter bit 19 */
+#define CAN_F4R1_FB20_Pos (20U)
+#define CAN_F4R1_FB20_Msk (0x1U << CAN_F4R1_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F4R1_FB20 CAN_F4R1_FB20_Msk /*!< Filter bit 20 */
+#define CAN_F4R1_FB21_Pos (21U)
+#define CAN_F4R1_FB21_Msk (0x1U << CAN_F4R1_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F4R1_FB21 CAN_F4R1_FB21_Msk /*!< Filter bit 21 */
+#define CAN_F4R1_FB22_Pos (22U)
+#define CAN_F4R1_FB22_Msk (0x1U << CAN_F4R1_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F4R1_FB22 CAN_F4R1_FB22_Msk /*!< Filter bit 22 */
+#define CAN_F4R1_FB23_Pos (23U)
+#define CAN_F4R1_FB23_Msk (0x1U << CAN_F4R1_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F4R1_FB23 CAN_F4R1_FB23_Msk /*!< Filter bit 23 */
+#define CAN_F4R1_FB24_Pos (24U)
+#define CAN_F4R1_FB24_Msk (0x1U << CAN_F4R1_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F4R1_FB24 CAN_F4R1_FB24_Msk /*!< Filter bit 24 */
+#define CAN_F4R1_FB25_Pos (25U)
+#define CAN_F4R1_FB25_Msk (0x1U << CAN_F4R1_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F4R1_FB25 CAN_F4R1_FB25_Msk /*!< Filter bit 25 */
+#define CAN_F4R1_FB26_Pos (26U)
+#define CAN_F4R1_FB26_Msk (0x1U << CAN_F4R1_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F4R1_FB26 CAN_F4R1_FB26_Msk /*!< Filter bit 26 */
+#define CAN_F4R1_FB27_Pos (27U)
+#define CAN_F4R1_FB27_Msk (0x1U << CAN_F4R1_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F4R1_FB27 CAN_F4R1_FB27_Msk /*!< Filter bit 27 */
+#define CAN_F4R1_FB28_Pos (28U)
+#define CAN_F4R1_FB28_Msk (0x1U << CAN_F4R1_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F4R1_FB28 CAN_F4R1_FB28_Msk /*!< Filter bit 28 */
+#define CAN_F4R1_FB29_Pos (29U)
+#define CAN_F4R1_FB29_Msk (0x1U << CAN_F4R1_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F4R1_FB29 CAN_F4R1_FB29_Msk /*!< Filter bit 29 */
+#define CAN_F4R1_FB30_Pos (30U)
+#define CAN_F4R1_FB30_Msk (0x1U << CAN_F4R1_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F4R1_FB30 CAN_F4R1_FB30_Msk /*!< Filter bit 30 */
+#define CAN_F4R1_FB31_Pos (31U)
+#define CAN_F4R1_FB31_Msk (0x1U << CAN_F4R1_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F4R1_FB31 CAN_F4R1_FB31_Msk /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F5R1 register *******************/
+#define CAN_F5R1_FB0_Pos (0U)
+#define CAN_F5R1_FB0_Msk (0x1U << CAN_F5R1_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F5R1_FB0 CAN_F5R1_FB0_Msk /*!< Filter bit 0 */
+#define CAN_F5R1_FB1_Pos (1U)
+#define CAN_F5R1_FB1_Msk (0x1U << CAN_F5R1_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F5R1_FB1 CAN_F5R1_FB1_Msk /*!< Filter bit 1 */
+#define CAN_F5R1_FB2_Pos (2U)
+#define CAN_F5R1_FB2_Msk (0x1U << CAN_F5R1_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F5R1_FB2 CAN_F5R1_FB2_Msk /*!< Filter bit 2 */
+#define CAN_F5R1_FB3_Pos (3U)
+#define CAN_F5R1_FB3_Msk (0x1U << CAN_F5R1_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F5R1_FB3 CAN_F5R1_FB3_Msk /*!< Filter bit 3 */
+#define CAN_F5R1_FB4_Pos (4U)
+#define CAN_F5R1_FB4_Msk (0x1U << CAN_F5R1_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F5R1_FB4 CAN_F5R1_FB4_Msk /*!< Filter bit 4 */
+#define CAN_F5R1_FB5_Pos (5U)
+#define CAN_F5R1_FB5_Msk (0x1U << CAN_F5R1_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F5R1_FB5 CAN_F5R1_FB5_Msk /*!< Filter bit 5 */
+#define CAN_F5R1_FB6_Pos (6U)
+#define CAN_F5R1_FB6_Msk (0x1U << CAN_F5R1_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F5R1_FB6 CAN_F5R1_FB6_Msk /*!< Filter bit 6 */
+#define CAN_F5R1_FB7_Pos (7U)
+#define CAN_F5R1_FB7_Msk (0x1U << CAN_F5R1_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F5R1_FB7 CAN_F5R1_FB7_Msk /*!< Filter bit 7 */
+#define CAN_F5R1_FB8_Pos (8U)
+#define CAN_F5R1_FB8_Msk (0x1U << CAN_F5R1_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F5R1_FB8 CAN_F5R1_FB8_Msk /*!< Filter bit 8 */
+#define CAN_F5R1_FB9_Pos (9U)
+#define CAN_F5R1_FB9_Msk (0x1U << CAN_F5R1_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F5R1_FB9 CAN_F5R1_FB9_Msk /*!< Filter bit 9 */
+#define CAN_F5R1_FB10_Pos (10U)
+#define CAN_F5R1_FB10_Msk (0x1U << CAN_F5R1_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F5R1_FB10 CAN_F5R1_FB10_Msk /*!< Filter bit 10 */
+#define CAN_F5R1_FB11_Pos (11U)
+#define CAN_F5R1_FB11_Msk (0x1U << CAN_F5R1_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F5R1_FB11 CAN_F5R1_FB11_Msk /*!< Filter bit 11 */
+#define CAN_F5R1_FB12_Pos (12U)
+#define CAN_F5R1_FB12_Msk (0x1U << CAN_F5R1_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F5R1_FB12 CAN_F5R1_FB12_Msk /*!< Filter bit 12 */
+#define CAN_F5R1_FB13_Pos (13U)
+#define CAN_F5R1_FB13_Msk (0x1U << CAN_F5R1_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F5R1_FB13 CAN_F5R1_FB13_Msk /*!< Filter bit 13 */
+#define CAN_F5R1_FB14_Pos (14U)
+#define CAN_F5R1_FB14_Msk (0x1U << CAN_F5R1_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F5R1_FB14 CAN_F5R1_FB14_Msk /*!< Filter bit 14 */
+#define CAN_F5R1_FB15_Pos (15U)
+#define CAN_F5R1_FB15_Msk (0x1U << CAN_F5R1_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F5R1_FB15 CAN_F5R1_FB15_Msk /*!< Filter bit 15 */
+#define CAN_F5R1_FB16_Pos (16U)
+#define CAN_F5R1_FB16_Msk (0x1U << CAN_F5R1_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F5R1_FB16 CAN_F5R1_FB16_Msk /*!< Filter bit 16 */
+#define CAN_F5R1_FB17_Pos (17U)
+#define CAN_F5R1_FB17_Msk (0x1U << CAN_F5R1_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F5R1_FB17 CAN_F5R1_FB17_Msk /*!< Filter bit 17 */
+#define CAN_F5R1_FB18_Pos (18U)
+#define CAN_F5R1_FB18_Msk (0x1U << CAN_F5R1_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F5R1_FB18 CAN_F5R1_FB18_Msk /*!< Filter bit 18 */
+#define CAN_F5R1_FB19_Pos (19U)
+#define CAN_F5R1_FB19_Msk (0x1U << CAN_F5R1_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F5R1_FB19 CAN_F5R1_FB19_Msk /*!< Filter bit 19 */
+#define CAN_F5R1_FB20_Pos (20U)
+#define CAN_F5R1_FB20_Msk (0x1U << CAN_F5R1_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F5R1_FB20 CAN_F5R1_FB20_Msk /*!< Filter bit 20 */
+#define CAN_F5R1_FB21_Pos (21U)
+#define CAN_F5R1_FB21_Msk (0x1U << CAN_F5R1_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F5R1_FB21 CAN_F5R1_FB21_Msk /*!< Filter bit 21 */
+#define CAN_F5R1_FB22_Pos (22U)
+#define CAN_F5R1_FB22_Msk (0x1U << CAN_F5R1_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F5R1_FB22 CAN_F5R1_FB22_Msk /*!< Filter bit 22 */
+#define CAN_F5R1_FB23_Pos (23U)
+#define CAN_F5R1_FB23_Msk (0x1U << CAN_F5R1_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F5R1_FB23 CAN_F5R1_FB23_Msk /*!< Filter bit 23 */
+#define CAN_F5R1_FB24_Pos (24U)
+#define CAN_F5R1_FB24_Msk (0x1U << CAN_F5R1_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F5R1_FB24 CAN_F5R1_FB24_Msk /*!< Filter bit 24 */
+#define CAN_F5R1_FB25_Pos (25U)
+#define CAN_F5R1_FB25_Msk (0x1U << CAN_F5R1_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F5R1_FB25 CAN_F5R1_FB25_Msk /*!< Filter bit 25 */
+#define CAN_F5R1_FB26_Pos (26U)
+#define CAN_F5R1_FB26_Msk (0x1U << CAN_F5R1_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F5R1_FB26 CAN_F5R1_FB26_Msk /*!< Filter bit 26 */
+#define CAN_F5R1_FB27_Pos (27U)
+#define CAN_F5R1_FB27_Msk (0x1U << CAN_F5R1_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F5R1_FB27 CAN_F5R1_FB27_Msk /*!< Filter bit 27 */
+#define CAN_F5R1_FB28_Pos (28U)
+#define CAN_F5R1_FB28_Msk (0x1U << CAN_F5R1_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F5R1_FB28 CAN_F5R1_FB28_Msk /*!< Filter bit 28 */
+#define CAN_F5R1_FB29_Pos (29U)
+#define CAN_F5R1_FB29_Msk (0x1U << CAN_F5R1_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F5R1_FB29 CAN_F5R1_FB29_Msk /*!< Filter bit 29 */
+#define CAN_F5R1_FB30_Pos (30U)
+#define CAN_F5R1_FB30_Msk (0x1U << CAN_F5R1_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F5R1_FB30 CAN_F5R1_FB30_Msk /*!< Filter bit 30 */
+#define CAN_F5R1_FB31_Pos (31U)
+#define CAN_F5R1_FB31_Msk (0x1U << CAN_F5R1_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F5R1_FB31 CAN_F5R1_FB31_Msk /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F6R1 register *******************/
+#define CAN_F6R1_FB0_Pos (0U)
+#define CAN_F6R1_FB0_Msk (0x1U << CAN_F6R1_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F6R1_FB0 CAN_F6R1_FB0_Msk /*!< Filter bit 0 */
+#define CAN_F6R1_FB1_Pos (1U)
+#define CAN_F6R1_FB1_Msk (0x1U << CAN_F6R1_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F6R1_FB1 CAN_F6R1_FB1_Msk /*!< Filter bit 1 */
+#define CAN_F6R1_FB2_Pos (2U)
+#define CAN_F6R1_FB2_Msk (0x1U << CAN_F6R1_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F6R1_FB2 CAN_F6R1_FB2_Msk /*!< Filter bit 2 */
+#define CAN_F6R1_FB3_Pos (3U)
+#define CAN_F6R1_FB3_Msk (0x1U << CAN_F6R1_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F6R1_FB3 CAN_F6R1_FB3_Msk /*!< Filter bit 3 */
+#define CAN_F6R1_FB4_Pos (4U)
+#define CAN_F6R1_FB4_Msk (0x1U << CAN_F6R1_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F6R1_FB4 CAN_F6R1_FB4_Msk /*!< Filter bit 4 */
+#define CAN_F6R1_FB5_Pos (5U)
+#define CAN_F6R1_FB5_Msk (0x1U << CAN_F6R1_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F6R1_FB5 CAN_F6R1_FB5_Msk /*!< Filter bit 5 */
+#define CAN_F6R1_FB6_Pos (6U)
+#define CAN_F6R1_FB6_Msk (0x1U << CAN_F6R1_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F6R1_FB6 CAN_F6R1_FB6_Msk /*!< Filter bit 6 */
+#define CAN_F6R1_FB7_Pos (7U)
+#define CAN_F6R1_FB7_Msk (0x1U << CAN_F6R1_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F6R1_FB7 CAN_F6R1_FB7_Msk /*!< Filter bit 7 */
+#define CAN_F6R1_FB8_Pos (8U)
+#define CAN_F6R1_FB8_Msk (0x1U << CAN_F6R1_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F6R1_FB8 CAN_F6R1_FB8_Msk /*!< Filter bit 8 */
+#define CAN_F6R1_FB9_Pos (9U)
+#define CAN_F6R1_FB9_Msk (0x1U << CAN_F6R1_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F6R1_FB9 CAN_F6R1_FB9_Msk /*!< Filter bit 9 */
+#define CAN_F6R1_FB10_Pos (10U)
+#define CAN_F6R1_FB10_Msk (0x1U << CAN_F6R1_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F6R1_FB10 CAN_F6R1_FB10_Msk /*!< Filter bit 10 */
+#define CAN_F6R1_FB11_Pos (11U)
+#define CAN_F6R1_FB11_Msk (0x1U << CAN_F6R1_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F6R1_FB11 CAN_F6R1_FB11_Msk /*!< Filter bit 11 */
+#define CAN_F6R1_FB12_Pos (12U)
+#define CAN_F6R1_FB12_Msk (0x1U << CAN_F6R1_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F6R1_FB12 CAN_F6R1_FB12_Msk /*!< Filter bit 12 */
+#define CAN_F6R1_FB13_Pos (13U)
+#define CAN_F6R1_FB13_Msk (0x1U << CAN_F6R1_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F6R1_FB13 CAN_F6R1_FB13_Msk /*!< Filter bit 13 */
+#define CAN_F6R1_FB14_Pos (14U)
+#define CAN_F6R1_FB14_Msk (0x1U << CAN_F6R1_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F6R1_FB14 CAN_F6R1_FB14_Msk /*!< Filter bit 14 */
+#define CAN_F6R1_FB15_Pos (15U)
+#define CAN_F6R1_FB15_Msk (0x1U << CAN_F6R1_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F6R1_FB15 CAN_F6R1_FB15_Msk /*!< Filter bit 15 */
+#define CAN_F6R1_FB16_Pos (16U)
+#define CAN_F6R1_FB16_Msk (0x1U << CAN_F6R1_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F6R1_FB16 CAN_F6R1_FB16_Msk /*!< Filter bit 16 */
+#define CAN_F6R1_FB17_Pos (17U)
+#define CAN_F6R1_FB17_Msk (0x1U << CAN_F6R1_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F6R1_FB17 CAN_F6R1_FB17_Msk /*!< Filter bit 17 */
+#define CAN_F6R1_FB18_Pos (18U)
+#define CAN_F6R1_FB18_Msk (0x1U << CAN_F6R1_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F6R1_FB18 CAN_F6R1_FB18_Msk /*!< Filter bit 18 */
+#define CAN_F6R1_FB19_Pos (19U)
+#define CAN_F6R1_FB19_Msk (0x1U << CAN_F6R1_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F6R1_FB19 CAN_F6R1_FB19_Msk /*!< Filter bit 19 */
+#define CAN_F6R1_FB20_Pos (20U)
+#define CAN_F6R1_FB20_Msk (0x1U << CAN_F6R1_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F6R1_FB20 CAN_F6R1_FB20_Msk /*!< Filter bit 20 */
+#define CAN_F6R1_FB21_Pos (21U)
+#define CAN_F6R1_FB21_Msk (0x1U << CAN_F6R1_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F6R1_FB21 CAN_F6R1_FB21_Msk /*!< Filter bit 21 */
+#define CAN_F6R1_FB22_Pos (22U)
+#define CAN_F6R1_FB22_Msk (0x1U << CAN_F6R1_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F6R1_FB22 CAN_F6R1_FB22_Msk /*!< Filter bit 22 */
+#define CAN_F6R1_FB23_Pos (23U)
+#define CAN_F6R1_FB23_Msk (0x1U << CAN_F6R1_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F6R1_FB23 CAN_F6R1_FB23_Msk /*!< Filter bit 23 */
+#define CAN_F6R1_FB24_Pos (24U)
+#define CAN_F6R1_FB24_Msk (0x1U << CAN_F6R1_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F6R1_FB24 CAN_F6R1_FB24_Msk /*!< Filter bit 24 */
+#define CAN_F6R1_FB25_Pos (25U)
+#define CAN_F6R1_FB25_Msk (0x1U << CAN_F6R1_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F6R1_FB25 CAN_F6R1_FB25_Msk /*!< Filter bit 25 */
+#define CAN_F6R1_FB26_Pos (26U)
+#define CAN_F6R1_FB26_Msk (0x1U << CAN_F6R1_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F6R1_FB26 CAN_F6R1_FB26_Msk /*!< Filter bit 26 */
+#define CAN_F6R1_FB27_Pos (27U)
+#define CAN_F6R1_FB27_Msk (0x1U << CAN_F6R1_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F6R1_FB27 CAN_F6R1_FB27_Msk /*!< Filter bit 27 */
+#define CAN_F6R1_FB28_Pos (28U)
+#define CAN_F6R1_FB28_Msk (0x1U << CAN_F6R1_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F6R1_FB28 CAN_F6R1_FB28_Msk /*!< Filter bit 28 */
+#define CAN_F6R1_FB29_Pos (29U)
+#define CAN_F6R1_FB29_Msk (0x1U << CAN_F6R1_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F6R1_FB29 CAN_F6R1_FB29_Msk /*!< Filter bit 29 */
+#define CAN_F6R1_FB30_Pos (30U)
+#define CAN_F6R1_FB30_Msk (0x1U << CAN_F6R1_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F6R1_FB30 CAN_F6R1_FB30_Msk /*!< Filter bit 30 */
+#define CAN_F6R1_FB31_Pos (31U)
+#define CAN_F6R1_FB31_Msk (0x1U << CAN_F6R1_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F6R1_FB31 CAN_F6R1_FB31_Msk /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F7R1 register *******************/
+#define CAN_F7R1_FB0_Pos (0U)
+#define CAN_F7R1_FB0_Msk (0x1U << CAN_F7R1_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F7R1_FB0 CAN_F7R1_FB0_Msk /*!< Filter bit 0 */
+#define CAN_F7R1_FB1_Pos (1U)
+#define CAN_F7R1_FB1_Msk (0x1U << CAN_F7R1_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F7R1_FB1 CAN_F7R1_FB1_Msk /*!< Filter bit 1 */
+#define CAN_F7R1_FB2_Pos (2U)
+#define CAN_F7R1_FB2_Msk (0x1U << CAN_F7R1_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F7R1_FB2 CAN_F7R1_FB2_Msk /*!< Filter bit 2 */
+#define CAN_F7R1_FB3_Pos (3U)
+#define CAN_F7R1_FB3_Msk (0x1U << CAN_F7R1_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F7R1_FB3 CAN_F7R1_FB3_Msk /*!< Filter bit 3 */
+#define CAN_F7R1_FB4_Pos (4U)
+#define CAN_F7R1_FB4_Msk (0x1U << CAN_F7R1_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F7R1_FB4 CAN_F7R1_FB4_Msk /*!< Filter bit 4 */
+#define CAN_F7R1_FB5_Pos (5U)
+#define CAN_F7R1_FB5_Msk (0x1U << CAN_F7R1_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F7R1_FB5 CAN_F7R1_FB5_Msk /*!< Filter bit 5 */
+#define CAN_F7R1_FB6_Pos (6U)
+#define CAN_F7R1_FB6_Msk (0x1U << CAN_F7R1_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F7R1_FB6 CAN_F7R1_FB6_Msk /*!< Filter bit 6 */
+#define CAN_F7R1_FB7_Pos (7U)
+#define CAN_F7R1_FB7_Msk (0x1U << CAN_F7R1_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F7R1_FB7 CAN_F7R1_FB7_Msk /*!< Filter bit 7 */
+#define CAN_F7R1_FB8_Pos (8U)
+#define CAN_F7R1_FB8_Msk (0x1U << CAN_F7R1_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F7R1_FB8 CAN_F7R1_FB8_Msk /*!< Filter bit 8 */
+#define CAN_F7R1_FB9_Pos (9U)
+#define CAN_F7R1_FB9_Msk (0x1U << CAN_F7R1_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F7R1_FB9 CAN_F7R1_FB9_Msk /*!< Filter bit 9 */
+#define CAN_F7R1_FB10_Pos (10U)
+#define CAN_F7R1_FB10_Msk (0x1U << CAN_F7R1_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F7R1_FB10 CAN_F7R1_FB10_Msk /*!< Filter bit 10 */
+#define CAN_F7R1_FB11_Pos (11U)
+#define CAN_F7R1_FB11_Msk (0x1U << CAN_F7R1_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F7R1_FB11 CAN_F7R1_FB11_Msk /*!< Filter bit 11 */
+#define CAN_F7R1_FB12_Pos (12U)
+#define CAN_F7R1_FB12_Msk (0x1U << CAN_F7R1_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F7R1_FB12 CAN_F7R1_FB12_Msk /*!< Filter bit 12 */
+#define CAN_F7R1_FB13_Pos (13U)
+#define CAN_F7R1_FB13_Msk (0x1U << CAN_F7R1_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F7R1_FB13 CAN_F7R1_FB13_Msk /*!< Filter bit 13 */
+#define CAN_F7R1_FB14_Pos (14U)
+#define CAN_F7R1_FB14_Msk (0x1U << CAN_F7R1_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F7R1_FB14 CAN_F7R1_FB14_Msk /*!< Filter bit 14 */
+#define CAN_F7R1_FB15_Pos (15U)
+#define CAN_F7R1_FB15_Msk (0x1U << CAN_F7R1_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F7R1_FB15 CAN_F7R1_FB15_Msk /*!< Filter bit 15 */
+#define CAN_F7R1_FB16_Pos (16U)
+#define CAN_F7R1_FB16_Msk (0x1U << CAN_F7R1_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F7R1_FB16 CAN_F7R1_FB16_Msk /*!< Filter bit 16 */
+#define CAN_F7R1_FB17_Pos (17U)
+#define CAN_F7R1_FB17_Msk (0x1U << CAN_F7R1_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F7R1_FB17 CAN_F7R1_FB17_Msk /*!< Filter bit 17 */
+#define CAN_F7R1_FB18_Pos (18U)
+#define CAN_F7R1_FB18_Msk (0x1U << CAN_F7R1_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F7R1_FB18 CAN_F7R1_FB18_Msk /*!< Filter bit 18 */
+#define CAN_F7R1_FB19_Pos (19U)
+#define CAN_F7R1_FB19_Msk (0x1U << CAN_F7R1_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F7R1_FB19 CAN_F7R1_FB19_Msk /*!< Filter bit 19 */
+#define CAN_F7R1_FB20_Pos (20U)
+#define CAN_F7R1_FB20_Msk (0x1U << CAN_F7R1_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F7R1_FB20 CAN_F7R1_FB20_Msk /*!< Filter bit 20 */
+#define CAN_F7R1_FB21_Pos (21U)
+#define CAN_F7R1_FB21_Msk (0x1U << CAN_F7R1_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F7R1_FB21 CAN_F7R1_FB21_Msk /*!< Filter bit 21 */
+#define CAN_F7R1_FB22_Pos (22U)
+#define CAN_F7R1_FB22_Msk (0x1U << CAN_F7R1_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F7R1_FB22 CAN_F7R1_FB22_Msk /*!< Filter bit 22 */
+#define CAN_F7R1_FB23_Pos (23U)
+#define CAN_F7R1_FB23_Msk (0x1U << CAN_F7R1_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F7R1_FB23 CAN_F7R1_FB23_Msk /*!< Filter bit 23 */
+#define CAN_F7R1_FB24_Pos (24U)
+#define CAN_F7R1_FB24_Msk (0x1U << CAN_F7R1_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F7R1_FB24 CAN_F7R1_FB24_Msk /*!< Filter bit 24 */
+#define CAN_F7R1_FB25_Pos (25U)
+#define CAN_F7R1_FB25_Msk (0x1U << CAN_F7R1_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F7R1_FB25 CAN_F7R1_FB25_Msk /*!< Filter bit 25 */
+#define CAN_F7R1_FB26_Pos (26U)
+#define CAN_F7R1_FB26_Msk (0x1U << CAN_F7R1_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F7R1_FB26 CAN_F7R1_FB26_Msk /*!< Filter bit 26 */
+#define CAN_F7R1_FB27_Pos (27U)
+#define CAN_F7R1_FB27_Msk (0x1U << CAN_F7R1_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F7R1_FB27 CAN_F7R1_FB27_Msk /*!< Filter bit 27 */
+#define CAN_F7R1_FB28_Pos (28U)
+#define CAN_F7R1_FB28_Msk (0x1U << CAN_F7R1_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F7R1_FB28 CAN_F7R1_FB28_Msk /*!< Filter bit 28 */
+#define CAN_F7R1_FB29_Pos (29U)
+#define CAN_F7R1_FB29_Msk (0x1U << CAN_F7R1_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F7R1_FB29 CAN_F7R1_FB29_Msk /*!< Filter bit 29 */
+#define CAN_F7R1_FB30_Pos (30U)
+#define CAN_F7R1_FB30_Msk (0x1U << CAN_F7R1_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F7R1_FB30 CAN_F7R1_FB30_Msk /*!< Filter bit 30 */
+#define CAN_F7R1_FB31_Pos (31U)
+#define CAN_F7R1_FB31_Msk (0x1U << CAN_F7R1_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F7R1_FB31 CAN_F7R1_FB31_Msk /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F8R1 register *******************/
+#define CAN_F8R1_FB0_Pos (0U)
+#define CAN_F8R1_FB0_Msk (0x1U << CAN_F8R1_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F8R1_FB0 CAN_F8R1_FB0_Msk /*!< Filter bit 0 */
+#define CAN_F8R1_FB1_Pos (1U)
+#define CAN_F8R1_FB1_Msk (0x1U << CAN_F8R1_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F8R1_FB1 CAN_F8R1_FB1_Msk /*!< Filter bit 1 */
+#define CAN_F8R1_FB2_Pos (2U)
+#define CAN_F8R1_FB2_Msk (0x1U << CAN_F8R1_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F8R1_FB2 CAN_F8R1_FB2_Msk /*!< Filter bit 2 */
+#define CAN_F8R1_FB3_Pos (3U)
+#define CAN_F8R1_FB3_Msk (0x1U << CAN_F8R1_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F8R1_FB3 CAN_F8R1_FB3_Msk /*!< Filter bit 3 */
+#define CAN_F8R1_FB4_Pos (4U)
+#define CAN_F8R1_FB4_Msk (0x1U << CAN_F8R1_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F8R1_FB4 CAN_F8R1_FB4_Msk /*!< Filter bit 4 */
+#define CAN_F8R1_FB5_Pos (5U)
+#define CAN_F8R1_FB5_Msk (0x1U << CAN_F8R1_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F8R1_FB5 CAN_F8R1_FB5_Msk /*!< Filter bit 5 */
+#define CAN_F8R1_FB6_Pos (6U)
+#define CAN_F8R1_FB6_Msk (0x1U << CAN_F8R1_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F8R1_FB6 CAN_F8R1_FB6_Msk /*!< Filter bit 6 */
+#define CAN_F8R1_FB7_Pos (7U)
+#define CAN_F8R1_FB7_Msk (0x1U << CAN_F8R1_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F8R1_FB7 CAN_F8R1_FB7_Msk /*!< Filter bit 7 */
+#define CAN_F8R1_FB8_Pos (8U)
+#define CAN_F8R1_FB8_Msk (0x1U << CAN_F8R1_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F8R1_FB8 CAN_F8R1_FB8_Msk /*!< Filter bit 8 */
+#define CAN_F8R1_FB9_Pos (9U)
+#define CAN_F8R1_FB9_Msk (0x1U << CAN_F8R1_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F8R1_FB9 CAN_F8R1_FB9_Msk /*!< Filter bit 9 */
+#define CAN_F8R1_FB10_Pos (10U)
+#define CAN_F8R1_FB10_Msk (0x1U << CAN_F8R1_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F8R1_FB10 CAN_F8R1_FB10_Msk /*!< Filter bit 10 */
+#define CAN_F8R1_FB11_Pos (11U)
+#define CAN_F8R1_FB11_Msk (0x1U << CAN_F8R1_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F8R1_FB11 CAN_F8R1_FB11_Msk /*!< Filter bit 11 */
+#define CAN_F8R1_FB12_Pos (12U)
+#define CAN_F8R1_FB12_Msk (0x1U << CAN_F8R1_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F8R1_FB12 CAN_F8R1_FB12_Msk /*!< Filter bit 12 */
+#define CAN_F8R1_FB13_Pos (13U)
+#define CAN_F8R1_FB13_Msk (0x1U << CAN_F8R1_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F8R1_FB13 CAN_F8R1_FB13_Msk /*!< Filter bit 13 */
+#define CAN_F8R1_FB14_Pos (14U)
+#define CAN_F8R1_FB14_Msk (0x1U << CAN_F8R1_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F8R1_FB14 CAN_F8R1_FB14_Msk /*!< Filter bit 14 */
+#define CAN_F8R1_FB15_Pos (15U)
+#define CAN_F8R1_FB15_Msk (0x1U << CAN_F8R1_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F8R1_FB15 CAN_F8R1_FB15_Msk /*!< Filter bit 15 */
+#define CAN_F8R1_FB16_Pos (16U)
+#define CAN_F8R1_FB16_Msk (0x1U << CAN_F8R1_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F8R1_FB16 CAN_F8R1_FB16_Msk /*!< Filter bit 16 */
+#define CAN_F8R1_FB17_Pos (17U)
+#define CAN_F8R1_FB17_Msk (0x1U << CAN_F8R1_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F8R1_FB17 CAN_F8R1_FB17_Msk /*!< Filter bit 17 */
+#define CAN_F8R1_FB18_Pos (18U)
+#define CAN_F8R1_FB18_Msk (0x1U << CAN_F8R1_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F8R1_FB18 CAN_F8R1_FB18_Msk /*!< Filter bit 18 */
+#define CAN_F8R1_FB19_Pos (19U)
+#define CAN_F8R1_FB19_Msk (0x1U << CAN_F8R1_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F8R1_FB19 CAN_F8R1_FB19_Msk /*!< Filter bit 19 */
+#define CAN_F8R1_FB20_Pos (20U)
+#define CAN_F8R1_FB20_Msk (0x1U << CAN_F8R1_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F8R1_FB20 CAN_F8R1_FB20_Msk /*!< Filter bit 20 */
+#define CAN_F8R1_FB21_Pos (21U)
+#define CAN_F8R1_FB21_Msk (0x1U << CAN_F8R1_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F8R1_FB21 CAN_F8R1_FB21_Msk /*!< Filter bit 21 */
+#define CAN_F8R1_FB22_Pos (22U)
+#define CAN_F8R1_FB22_Msk (0x1U << CAN_F8R1_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F8R1_FB22 CAN_F8R1_FB22_Msk /*!< Filter bit 22 */
+#define CAN_F8R1_FB23_Pos (23U)
+#define CAN_F8R1_FB23_Msk (0x1U << CAN_F8R1_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F8R1_FB23 CAN_F8R1_FB23_Msk /*!< Filter bit 23 */
+#define CAN_F8R1_FB24_Pos (24U)
+#define CAN_F8R1_FB24_Msk (0x1U << CAN_F8R1_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F8R1_FB24 CAN_F8R1_FB24_Msk /*!< Filter bit 24 */
+#define CAN_F8R1_FB25_Pos (25U)
+#define CAN_F8R1_FB25_Msk (0x1U << CAN_F8R1_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F8R1_FB25 CAN_F8R1_FB25_Msk /*!< Filter bit 25 */
+#define CAN_F8R1_FB26_Pos (26U)
+#define CAN_F8R1_FB26_Msk (0x1U << CAN_F8R1_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F8R1_FB26 CAN_F8R1_FB26_Msk /*!< Filter bit 26 */
+#define CAN_F8R1_FB27_Pos (27U)
+#define CAN_F8R1_FB27_Msk (0x1U << CAN_F8R1_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F8R1_FB27 CAN_F8R1_FB27_Msk /*!< Filter bit 27 */
+#define CAN_F8R1_FB28_Pos (28U)
+#define CAN_F8R1_FB28_Msk (0x1U << CAN_F8R1_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F8R1_FB28 CAN_F8R1_FB28_Msk /*!< Filter bit 28 */
+#define CAN_F8R1_FB29_Pos (29U)
+#define CAN_F8R1_FB29_Msk (0x1U << CAN_F8R1_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F8R1_FB29 CAN_F8R1_FB29_Msk /*!< Filter bit 29 */
+#define CAN_F8R1_FB30_Pos (30U)
+#define CAN_F8R1_FB30_Msk (0x1U << CAN_F8R1_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F8R1_FB30 CAN_F8R1_FB30_Msk /*!< Filter bit 30 */
+#define CAN_F8R1_FB31_Pos (31U)
+#define CAN_F8R1_FB31_Msk (0x1U << CAN_F8R1_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F8R1_FB31 CAN_F8R1_FB31_Msk /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F9R1 register *******************/
+#define CAN_F9R1_FB0_Pos (0U)
+#define CAN_F9R1_FB0_Msk (0x1U << CAN_F9R1_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F9R1_FB0 CAN_F9R1_FB0_Msk /*!< Filter bit 0 */
+#define CAN_F9R1_FB1_Pos (1U)
+#define CAN_F9R1_FB1_Msk (0x1U << CAN_F9R1_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F9R1_FB1 CAN_F9R1_FB1_Msk /*!< Filter bit 1 */
+#define CAN_F9R1_FB2_Pos (2U)
+#define CAN_F9R1_FB2_Msk (0x1U << CAN_F9R1_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F9R1_FB2 CAN_F9R1_FB2_Msk /*!< Filter bit 2 */
+#define CAN_F9R1_FB3_Pos (3U)
+#define CAN_F9R1_FB3_Msk (0x1U << CAN_F9R1_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F9R1_FB3 CAN_F9R1_FB3_Msk /*!< Filter bit 3 */
+#define CAN_F9R1_FB4_Pos (4U)
+#define CAN_F9R1_FB4_Msk (0x1U << CAN_F9R1_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F9R1_FB4 CAN_F9R1_FB4_Msk /*!< Filter bit 4 */
+#define CAN_F9R1_FB5_Pos (5U)
+#define CAN_F9R1_FB5_Msk (0x1U << CAN_F9R1_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F9R1_FB5 CAN_F9R1_FB5_Msk /*!< Filter bit 5 */
+#define CAN_F9R1_FB6_Pos (6U)
+#define CAN_F9R1_FB6_Msk (0x1U << CAN_F9R1_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F9R1_FB6 CAN_F9R1_FB6_Msk /*!< Filter bit 6 */
+#define CAN_F9R1_FB7_Pos (7U)
+#define CAN_F9R1_FB7_Msk (0x1U << CAN_F9R1_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F9R1_FB7 CAN_F9R1_FB7_Msk /*!< Filter bit 7 */
+#define CAN_F9R1_FB8_Pos (8U)
+#define CAN_F9R1_FB8_Msk (0x1U << CAN_F9R1_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F9R1_FB8 CAN_F9R1_FB8_Msk /*!< Filter bit 8 */
+#define CAN_F9R1_FB9_Pos (9U)
+#define CAN_F9R1_FB9_Msk (0x1U << CAN_F9R1_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F9R1_FB9 CAN_F9R1_FB9_Msk /*!< Filter bit 9 */
+#define CAN_F9R1_FB10_Pos (10U)
+#define CAN_F9R1_FB10_Msk (0x1U << CAN_F9R1_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F9R1_FB10 CAN_F9R1_FB10_Msk /*!< Filter bit 10 */
+#define CAN_F9R1_FB11_Pos (11U)
+#define CAN_F9R1_FB11_Msk (0x1U << CAN_F9R1_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F9R1_FB11 CAN_F9R1_FB11_Msk /*!< Filter bit 11 */
+#define CAN_F9R1_FB12_Pos (12U)
+#define CAN_F9R1_FB12_Msk (0x1U << CAN_F9R1_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F9R1_FB12 CAN_F9R1_FB12_Msk /*!< Filter bit 12 */
+#define CAN_F9R1_FB13_Pos (13U)
+#define CAN_F9R1_FB13_Msk (0x1U << CAN_F9R1_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F9R1_FB13 CAN_F9R1_FB13_Msk /*!< Filter bit 13 */
+#define CAN_F9R1_FB14_Pos (14U)
+#define CAN_F9R1_FB14_Msk (0x1U << CAN_F9R1_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F9R1_FB14 CAN_F9R1_FB14_Msk /*!< Filter bit 14 */
+#define CAN_F9R1_FB15_Pos (15U)
+#define CAN_F9R1_FB15_Msk (0x1U << CAN_F9R1_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F9R1_FB15 CAN_F9R1_FB15_Msk /*!< Filter bit 15 */
+#define CAN_F9R1_FB16_Pos (16U)
+#define CAN_F9R1_FB16_Msk (0x1U << CAN_F9R1_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F9R1_FB16 CAN_F9R1_FB16_Msk /*!< Filter bit 16 */
+#define CAN_F9R1_FB17_Pos (17U)
+#define CAN_F9R1_FB17_Msk (0x1U << CAN_F9R1_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F9R1_FB17 CAN_F9R1_FB17_Msk /*!< Filter bit 17 */
+#define CAN_F9R1_FB18_Pos (18U)
+#define CAN_F9R1_FB18_Msk (0x1U << CAN_F9R1_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F9R1_FB18 CAN_F9R1_FB18_Msk /*!< Filter bit 18 */
+#define CAN_F9R1_FB19_Pos (19U)
+#define CAN_F9R1_FB19_Msk (0x1U << CAN_F9R1_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F9R1_FB19 CAN_F9R1_FB19_Msk /*!< Filter bit 19 */
+#define CAN_F9R1_FB20_Pos (20U)
+#define CAN_F9R1_FB20_Msk (0x1U << CAN_F9R1_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F9R1_FB20 CAN_F9R1_FB20_Msk /*!< Filter bit 20 */
+#define CAN_F9R1_FB21_Pos (21U)
+#define CAN_F9R1_FB21_Msk (0x1U << CAN_F9R1_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F9R1_FB21 CAN_F9R1_FB21_Msk /*!< Filter bit 21 */
+#define CAN_F9R1_FB22_Pos (22U)
+#define CAN_F9R1_FB22_Msk (0x1U << CAN_F9R1_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F9R1_FB22 CAN_F9R1_FB22_Msk /*!< Filter bit 22 */
+#define CAN_F9R1_FB23_Pos (23U)
+#define CAN_F9R1_FB23_Msk (0x1U << CAN_F9R1_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F9R1_FB23 CAN_F9R1_FB23_Msk /*!< Filter bit 23 */
+#define CAN_F9R1_FB24_Pos (24U)
+#define CAN_F9R1_FB24_Msk (0x1U << CAN_F9R1_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F9R1_FB24 CAN_F9R1_FB24_Msk /*!< Filter bit 24 */
+#define CAN_F9R1_FB25_Pos (25U)
+#define CAN_F9R1_FB25_Msk (0x1U << CAN_F9R1_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F9R1_FB25 CAN_F9R1_FB25_Msk /*!< Filter bit 25 */
+#define CAN_F9R1_FB26_Pos (26U)
+#define CAN_F9R1_FB26_Msk (0x1U << CAN_F9R1_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F9R1_FB26 CAN_F9R1_FB26_Msk /*!< Filter bit 26 */
+#define CAN_F9R1_FB27_Pos (27U)
+#define CAN_F9R1_FB27_Msk (0x1U << CAN_F9R1_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F9R1_FB27 CAN_F9R1_FB27_Msk /*!< Filter bit 27 */
+#define CAN_F9R1_FB28_Pos (28U)
+#define CAN_F9R1_FB28_Msk (0x1U << CAN_F9R1_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F9R1_FB28 CAN_F9R1_FB28_Msk /*!< Filter bit 28 */
+#define CAN_F9R1_FB29_Pos (29U)
+#define CAN_F9R1_FB29_Msk (0x1U << CAN_F9R1_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F9R1_FB29 CAN_F9R1_FB29_Msk /*!< Filter bit 29 */
+#define CAN_F9R1_FB30_Pos (30U)
+#define CAN_F9R1_FB30_Msk (0x1U << CAN_F9R1_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F9R1_FB30 CAN_F9R1_FB30_Msk /*!< Filter bit 30 */
+#define CAN_F9R1_FB31_Pos (31U)
+#define CAN_F9R1_FB31_Msk (0x1U << CAN_F9R1_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F9R1_FB31 CAN_F9R1_FB31_Msk /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F10R1 register ******************/
+#define CAN_F10R1_FB0_Pos (0U)
+#define CAN_F10R1_FB0_Msk (0x1U << CAN_F10R1_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F10R1_FB0 CAN_F10R1_FB0_Msk /*!< Filter bit 0 */
+#define CAN_F10R1_FB1_Pos (1U)
+#define CAN_F10R1_FB1_Msk (0x1U << CAN_F10R1_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F10R1_FB1 CAN_F10R1_FB1_Msk /*!< Filter bit 1 */
+#define CAN_F10R1_FB2_Pos (2U)
+#define CAN_F10R1_FB2_Msk (0x1U << CAN_F10R1_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F10R1_FB2 CAN_F10R1_FB2_Msk /*!< Filter bit 2 */
+#define CAN_F10R1_FB3_Pos (3U)
+#define CAN_F10R1_FB3_Msk (0x1U << CAN_F10R1_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F10R1_FB3 CAN_F10R1_FB3_Msk /*!< Filter bit 3 */
+#define CAN_F10R1_FB4_Pos (4U)
+#define CAN_F10R1_FB4_Msk (0x1U << CAN_F10R1_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F10R1_FB4 CAN_F10R1_FB4_Msk /*!< Filter bit 4 */
+#define CAN_F10R1_FB5_Pos (5U)
+#define CAN_F10R1_FB5_Msk (0x1U << CAN_F10R1_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F10R1_FB5 CAN_F10R1_FB5_Msk /*!< Filter bit 5 */
+#define CAN_F10R1_FB6_Pos (6U)
+#define CAN_F10R1_FB6_Msk (0x1U << CAN_F10R1_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F10R1_FB6 CAN_F10R1_FB6_Msk /*!< Filter bit 6 */
+#define CAN_F10R1_FB7_Pos (7U)
+#define CAN_F10R1_FB7_Msk (0x1U << CAN_F10R1_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F10R1_FB7 CAN_F10R1_FB7_Msk /*!< Filter bit 7 */
+#define CAN_F10R1_FB8_Pos (8U)
+#define CAN_F10R1_FB8_Msk (0x1U << CAN_F10R1_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F10R1_FB8 CAN_F10R1_FB8_Msk /*!< Filter bit 8 */
+#define CAN_F10R1_FB9_Pos (9U)
+#define CAN_F10R1_FB9_Msk (0x1U << CAN_F10R1_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F10R1_FB9 CAN_F10R1_FB9_Msk /*!< Filter bit 9 */
+#define CAN_F10R1_FB10_Pos (10U)
+#define CAN_F10R1_FB10_Msk (0x1U << CAN_F10R1_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F10R1_FB10 CAN_F10R1_FB10_Msk /*!< Filter bit 10 */
+#define CAN_F10R1_FB11_Pos (11U)
+#define CAN_F10R1_FB11_Msk (0x1U << CAN_F10R1_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F10R1_FB11 CAN_F10R1_FB11_Msk /*!< Filter bit 11 */
+#define CAN_F10R1_FB12_Pos (12U)
+#define CAN_F10R1_FB12_Msk (0x1U << CAN_F10R1_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F10R1_FB12 CAN_F10R1_FB12_Msk /*!< Filter bit 12 */
+#define CAN_F10R1_FB13_Pos (13U)
+#define CAN_F10R1_FB13_Msk (0x1U << CAN_F10R1_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F10R1_FB13 CAN_F10R1_FB13_Msk /*!< Filter bit 13 */
+#define CAN_F10R1_FB14_Pos (14U)
+#define CAN_F10R1_FB14_Msk (0x1U << CAN_F10R1_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F10R1_FB14 CAN_F10R1_FB14_Msk /*!< Filter bit 14 */
+#define CAN_F10R1_FB15_Pos (15U)
+#define CAN_F10R1_FB15_Msk (0x1U << CAN_F10R1_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F10R1_FB15 CAN_F10R1_FB15_Msk /*!< Filter bit 15 */
+#define CAN_F10R1_FB16_Pos (16U)
+#define CAN_F10R1_FB16_Msk (0x1U << CAN_F10R1_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F10R1_FB16 CAN_F10R1_FB16_Msk /*!< Filter bit 16 */
+#define CAN_F10R1_FB17_Pos (17U)
+#define CAN_F10R1_FB17_Msk (0x1U << CAN_F10R1_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F10R1_FB17 CAN_F10R1_FB17_Msk /*!< Filter bit 17 */
+#define CAN_F10R1_FB18_Pos (18U)
+#define CAN_F10R1_FB18_Msk (0x1U << CAN_F10R1_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F10R1_FB18 CAN_F10R1_FB18_Msk /*!< Filter bit 18 */
+#define CAN_F10R1_FB19_Pos (19U)
+#define CAN_F10R1_FB19_Msk (0x1U << CAN_F10R1_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F10R1_FB19 CAN_F10R1_FB19_Msk /*!< Filter bit 19 */
+#define CAN_F10R1_FB20_Pos (20U)
+#define CAN_F10R1_FB20_Msk (0x1U << CAN_F10R1_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F10R1_FB20 CAN_F10R1_FB20_Msk /*!< Filter bit 20 */
+#define CAN_F10R1_FB21_Pos (21U)
+#define CAN_F10R1_FB21_Msk (0x1U << CAN_F10R1_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F10R1_FB21 CAN_F10R1_FB21_Msk /*!< Filter bit 21 */
+#define CAN_F10R1_FB22_Pos (22U)
+#define CAN_F10R1_FB22_Msk (0x1U << CAN_F10R1_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F10R1_FB22 CAN_F10R1_FB22_Msk /*!< Filter bit 22 */
+#define CAN_F10R1_FB23_Pos (23U)
+#define CAN_F10R1_FB23_Msk (0x1U << CAN_F10R1_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F10R1_FB23 CAN_F10R1_FB23_Msk /*!< Filter bit 23 */
+#define CAN_F10R1_FB24_Pos (24U)
+#define CAN_F10R1_FB24_Msk (0x1U << CAN_F10R1_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F10R1_FB24 CAN_F10R1_FB24_Msk /*!< Filter bit 24 */
+#define CAN_F10R1_FB25_Pos (25U)
+#define CAN_F10R1_FB25_Msk (0x1U << CAN_F10R1_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F10R1_FB25 CAN_F10R1_FB25_Msk /*!< Filter bit 25 */
+#define CAN_F10R1_FB26_Pos (26U)
+#define CAN_F10R1_FB26_Msk (0x1U << CAN_F10R1_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F10R1_FB26 CAN_F10R1_FB26_Msk /*!< Filter bit 26 */
+#define CAN_F10R1_FB27_Pos (27U)
+#define CAN_F10R1_FB27_Msk (0x1U << CAN_F10R1_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F10R1_FB27 CAN_F10R1_FB27_Msk /*!< Filter bit 27 */
+#define CAN_F10R1_FB28_Pos (28U)
+#define CAN_F10R1_FB28_Msk (0x1U << CAN_F10R1_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F10R1_FB28 CAN_F10R1_FB28_Msk /*!< Filter bit 28 */
+#define CAN_F10R1_FB29_Pos (29U)
+#define CAN_F10R1_FB29_Msk (0x1U << CAN_F10R1_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F10R1_FB29 CAN_F10R1_FB29_Msk /*!< Filter bit 29 */
+#define CAN_F10R1_FB30_Pos (30U)
+#define CAN_F10R1_FB30_Msk (0x1U << CAN_F10R1_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F10R1_FB30 CAN_F10R1_FB30_Msk /*!< Filter bit 30 */
+#define CAN_F10R1_FB31_Pos (31U)
+#define CAN_F10R1_FB31_Msk (0x1U << CAN_F10R1_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F10R1_FB31 CAN_F10R1_FB31_Msk /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F11R1 register ******************/
+#define CAN_F11R1_FB0_Pos (0U)
+#define CAN_F11R1_FB0_Msk (0x1U << CAN_F11R1_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F11R1_FB0 CAN_F11R1_FB0_Msk /*!< Filter bit 0 */
+#define CAN_F11R1_FB1_Pos (1U)
+#define CAN_F11R1_FB1_Msk (0x1U << CAN_F11R1_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F11R1_FB1 CAN_F11R1_FB1_Msk /*!< Filter bit 1 */
+#define CAN_F11R1_FB2_Pos (2U)
+#define CAN_F11R1_FB2_Msk (0x1U << CAN_F11R1_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F11R1_FB2 CAN_F11R1_FB2_Msk /*!< Filter bit 2 */
+#define CAN_F11R1_FB3_Pos (3U)
+#define CAN_F11R1_FB3_Msk (0x1U << CAN_F11R1_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F11R1_FB3 CAN_F11R1_FB3_Msk /*!< Filter bit 3 */
+#define CAN_F11R1_FB4_Pos (4U)
+#define CAN_F11R1_FB4_Msk (0x1U << CAN_F11R1_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F11R1_FB4 CAN_F11R1_FB4_Msk /*!< Filter bit 4 */
+#define CAN_F11R1_FB5_Pos (5U)
+#define CAN_F11R1_FB5_Msk (0x1U << CAN_F11R1_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F11R1_FB5 CAN_F11R1_FB5_Msk /*!< Filter bit 5 */
+#define CAN_F11R1_FB6_Pos (6U)
+#define CAN_F11R1_FB6_Msk (0x1U << CAN_F11R1_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F11R1_FB6 CAN_F11R1_FB6_Msk /*!< Filter bit 6 */
+#define CAN_F11R1_FB7_Pos (7U)
+#define CAN_F11R1_FB7_Msk (0x1U << CAN_F11R1_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F11R1_FB7 CAN_F11R1_FB7_Msk /*!< Filter bit 7 */
+#define CAN_F11R1_FB8_Pos (8U)
+#define CAN_F11R1_FB8_Msk (0x1U << CAN_F11R1_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F11R1_FB8 CAN_F11R1_FB8_Msk /*!< Filter bit 8 */
+#define CAN_F11R1_FB9_Pos (9U)
+#define CAN_F11R1_FB9_Msk (0x1U << CAN_F11R1_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F11R1_FB9 CAN_F11R1_FB9_Msk /*!< Filter bit 9 */
+#define CAN_F11R1_FB10_Pos (10U)
+#define CAN_F11R1_FB10_Msk (0x1U << CAN_F11R1_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F11R1_FB10 CAN_F11R1_FB10_Msk /*!< Filter bit 10 */
+#define CAN_F11R1_FB11_Pos (11U)
+#define CAN_F11R1_FB11_Msk (0x1U << CAN_F11R1_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F11R1_FB11 CAN_F11R1_FB11_Msk /*!< Filter bit 11 */
+#define CAN_F11R1_FB12_Pos (12U)
+#define CAN_F11R1_FB12_Msk (0x1U << CAN_F11R1_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F11R1_FB12 CAN_F11R1_FB12_Msk /*!< Filter bit 12 */
+#define CAN_F11R1_FB13_Pos (13U)
+#define CAN_F11R1_FB13_Msk (0x1U << CAN_F11R1_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F11R1_FB13 CAN_F11R1_FB13_Msk /*!< Filter bit 13 */
+#define CAN_F11R1_FB14_Pos (14U)
+#define CAN_F11R1_FB14_Msk (0x1U << CAN_F11R1_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F11R1_FB14 CAN_F11R1_FB14_Msk /*!< Filter bit 14 */
+#define CAN_F11R1_FB15_Pos (15U)
+#define CAN_F11R1_FB15_Msk (0x1U << CAN_F11R1_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F11R1_FB15 CAN_F11R1_FB15_Msk /*!< Filter bit 15 */
+#define CAN_F11R1_FB16_Pos (16U)
+#define CAN_F11R1_FB16_Msk (0x1U << CAN_F11R1_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F11R1_FB16 CAN_F11R1_FB16_Msk /*!< Filter bit 16 */
+#define CAN_F11R1_FB17_Pos (17U)
+#define CAN_F11R1_FB17_Msk (0x1U << CAN_F11R1_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F11R1_FB17 CAN_F11R1_FB17_Msk /*!< Filter bit 17 */
+#define CAN_F11R1_FB18_Pos (18U)
+#define CAN_F11R1_FB18_Msk (0x1U << CAN_F11R1_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F11R1_FB18 CAN_F11R1_FB18_Msk /*!< Filter bit 18 */
+#define CAN_F11R1_FB19_Pos (19U)
+#define CAN_F11R1_FB19_Msk (0x1U << CAN_F11R1_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F11R1_FB19 CAN_F11R1_FB19_Msk /*!< Filter bit 19 */
+#define CAN_F11R1_FB20_Pos (20U)
+#define CAN_F11R1_FB20_Msk (0x1U << CAN_F11R1_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F11R1_FB20 CAN_F11R1_FB20_Msk /*!< Filter bit 20 */
+#define CAN_F11R1_FB21_Pos (21U)
+#define CAN_F11R1_FB21_Msk (0x1U << CAN_F11R1_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F11R1_FB21 CAN_F11R1_FB21_Msk /*!< Filter bit 21 */
+#define CAN_F11R1_FB22_Pos (22U)
+#define CAN_F11R1_FB22_Msk (0x1U << CAN_F11R1_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F11R1_FB22 CAN_F11R1_FB22_Msk /*!< Filter bit 22 */
+#define CAN_F11R1_FB23_Pos (23U)
+#define CAN_F11R1_FB23_Msk (0x1U << CAN_F11R1_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F11R1_FB23 CAN_F11R1_FB23_Msk /*!< Filter bit 23 */
+#define CAN_F11R1_FB24_Pos (24U)
+#define CAN_F11R1_FB24_Msk (0x1U << CAN_F11R1_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F11R1_FB24 CAN_F11R1_FB24_Msk /*!< Filter bit 24 */
+#define CAN_F11R1_FB25_Pos (25U)
+#define CAN_F11R1_FB25_Msk (0x1U << CAN_F11R1_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F11R1_FB25 CAN_F11R1_FB25_Msk /*!< Filter bit 25 */
+#define CAN_F11R1_FB26_Pos (26U)
+#define CAN_F11R1_FB26_Msk (0x1U << CAN_F11R1_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F11R1_FB26 CAN_F11R1_FB26_Msk /*!< Filter bit 26 */
+#define CAN_F11R1_FB27_Pos (27U)
+#define CAN_F11R1_FB27_Msk (0x1U << CAN_F11R1_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F11R1_FB27 CAN_F11R1_FB27_Msk /*!< Filter bit 27 */
+#define CAN_F11R1_FB28_Pos (28U)
+#define CAN_F11R1_FB28_Msk (0x1U << CAN_F11R1_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F11R1_FB28 CAN_F11R1_FB28_Msk /*!< Filter bit 28 */
+#define CAN_F11R1_FB29_Pos (29U)
+#define CAN_F11R1_FB29_Msk (0x1U << CAN_F11R1_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F11R1_FB29 CAN_F11R1_FB29_Msk /*!< Filter bit 29 */
+#define CAN_F11R1_FB30_Pos (30U)
+#define CAN_F11R1_FB30_Msk (0x1U << CAN_F11R1_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F11R1_FB30 CAN_F11R1_FB30_Msk /*!< Filter bit 30 */
+#define CAN_F11R1_FB31_Pos (31U)
+#define CAN_F11R1_FB31_Msk (0x1U << CAN_F11R1_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F11R1_FB31 CAN_F11R1_FB31_Msk /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F12R1 register ******************/
+#define CAN_F12R1_FB0_Pos (0U)
+#define CAN_F12R1_FB0_Msk (0x1U << CAN_F12R1_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F12R1_FB0 CAN_F12R1_FB0_Msk /*!< Filter bit 0 */
+#define CAN_F12R1_FB1_Pos (1U)
+#define CAN_F12R1_FB1_Msk (0x1U << CAN_F12R1_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F12R1_FB1 CAN_F12R1_FB1_Msk /*!< Filter bit 1 */
+#define CAN_F12R1_FB2_Pos (2U)
+#define CAN_F12R1_FB2_Msk (0x1U << CAN_F12R1_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F12R1_FB2 CAN_F12R1_FB2_Msk /*!< Filter bit 2 */
+#define CAN_F12R1_FB3_Pos (3U)
+#define CAN_F12R1_FB3_Msk (0x1U << CAN_F12R1_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F12R1_FB3 CAN_F12R1_FB3_Msk /*!< Filter bit 3 */
+#define CAN_F12R1_FB4_Pos (4U)
+#define CAN_F12R1_FB4_Msk (0x1U << CAN_F12R1_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F12R1_FB4 CAN_F12R1_FB4_Msk /*!< Filter bit 4 */
+#define CAN_F12R1_FB5_Pos (5U)
+#define CAN_F12R1_FB5_Msk (0x1U << CAN_F12R1_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F12R1_FB5 CAN_F12R1_FB5_Msk /*!< Filter bit 5 */
+#define CAN_F12R1_FB6_Pos (6U)
+#define CAN_F12R1_FB6_Msk (0x1U << CAN_F12R1_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F12R1_FB6 CAN_F12R1_FB6_Msk /*!< Filter bit 6 */
+#define CAN_F12R1_FB7_Pos (7U)
+#define CAN_F12R1_FB7_Msk (0x1U << CAN_F12R1_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F12R1_FB7 CAN_F12R1_FB7_Msk /*!< Filter bit 7 */
+#define CAN_F12R1_FB8_Pos (8U)
+#define CAN_F12R1_FB8_Msk (0x1U << CAN_F12R1_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F12R1_FB8 CAN_F12R1_FB8_Msk /*!< Filter bit 8 */
+#define CAN_F12R1_FB9_Pos (9U)
+#define CAN_F12R1_FB9_Msk (0x1U << CAN_F12R1_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F12R1_FB9 CAN_F12R1_FB9_Msk /*!< Filter bit 9 */
+#define CAN_F12R1_FB10_Pos (10U)
+#define CAN_F12R1_FB10_Msk (0x1U << CAN_F12R1_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F12R1_FB10 CAN_F12R1_FB10_Msk /*!< Filter bit 10 */
+#define CAN_F12R1_FB11_Pos (11U)
+#define CAN_F12R1_FB11_Msk (0x1U << CAN_F12R1_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F12R1_FB11 CAN_F12R1_FB11_Msk /*!< Filter bit 11 */
+#define CAN_F12R1_FB12_Pos (12U)
+#define CAN_F12R1_FB12_Msk (0x1U << CAN_F12R1_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F12R1_FB12 CAN_F12R1_FB12_Msk /*!< Filter bit 12 */
+#define CAN_F12R1_FB13_Pos (13U)
+#define CAN_F12R1_FB13_Msk (0x1U << CAN_F12R1_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F12R1_FB13 CAN_F12R1_FB13_Msk /*!< Filter bit 13 */
+#define CAN_F12R1_FB14_Pos (14U)
+#define CAN_F12R1_FB14_Msk (0x1U << CAN_F12R1_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F12R1_FB14 CAN_F12R1_FB14_Msk /*!< Filter bit 14 */
+#define CAN_F12R1_FB15_Pos (15U)
+#define CAN_F12R1_FB15_Msk (0x1U << CAN_F12R1_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F12R1_FB15 CAN_F12R1_FB15_Msk /*!< Filter bit 15 */
+#define CAN_F12R1_FB16_Pos (16U)
+#define CAN_F12R1_FB16_Msk (0x1U << CAN_F12R1_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F12R1_FB16 CAN_F12R1_FB16_Msk /*!< Filter bit 16 */
+#define CAN_F12R1_FB17_Pos (17U)
+#define CAN_F12R1_FB17_Msk (0x1U << CAN_F12R1_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F12R1_FB17 CAN_F12R1_FB17_Msk /*!< Filter bit 17 */
+#define CAN_F12R1_FB18_Pos (18U)
+#define CAN_F12R1_FB18_Msk (0x1U << CAN_F12R1_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F12R1_FB18 CAN_F12R1_FB18_Msk /*!< Filter bit 18 */
+#define CAN_F12R1_FB19_Pos (19U)
+#define CAN_F12R1_FB19_Msk (0x1U << CAN_F12R1_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F12R1_FB19 CAN_F12R1_FB19_Msk /*!< Filter bit 19 */
+#define CAN_F12R1_FB20_Pos (20U)
+#define CAN_F12R1_FB20_Msk (0x1U << CAN_F12R1_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F12R1_FB20 CAN_F12R1_FB20_Msk /*!< Filter bit 20 */
+#define CAN_F12R1_FB21_Pos (21U)
+#define CAN_F12R1_FB21_Msk (0x1U << CAN_F12R1_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F12R1_FB21 CAN_F12R1_FB21_Msk /*!< Filter bit 21 */
+#define CAN_F12R1_FB22_Pos (22U)
+#define CAN_F12R1_FB22_Msk (0x1U << CAN_F12R1_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F12R1_FB22 CAN_F12R1_FB22_Msk /*!< Filter bit 22 */
+#define CAN_F12R1_FB23_Pos (23U)
+#define CAN_F12R1_FB23_Msk (0x1U << CAN_F12R1_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F12R1_FB23 CAN_F12R1_FB23_Msk /*!< Filter bit 23 */
+#define CAN_F12R1_FB24_Pos (24U)
+#define CAN_F12R1_FB24_Msk (0x1U << CAN_F12R1_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F12R1_FB24 CAN_F12R1_FB24_Msk /*!< Filter bit 24 */
+#define CAN_F12R1_FB25_Pos (25U)
+#define CAN_F12R1_FB25_Msk (0x1U << CAN_F12R1_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F12R1_FB25 CAN_F12R1_FB25_Msk /*!< Filter bit 25 */
+#define CAN_F12R1_FB26_Pos (26U)
+#define CAN_F12R1_FB26_Msk (0x1U << CAN_F12R1_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F12R1_FB26 CAN_F12R1_FB26_Msk /*!< Filter bit 26 */
+#define CAN_F12R1_FB27_Pos (27U)
+#define CAN_F12R1_FB27_Msk (0x1U << CAN_F12R1_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F12R1_FB27 CAN_F12R1_FB27_Msk /*!< Filter bit 27 */
+#define CAN_F12R1_FB28_Pos (28U)
+#define CAN_F12R1_FB28_Msk (0x1U << CAN_F12R1_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F12R1_FB28 CAN_F12R1_FB28_Msk /*!< Filter bit 28 */
+#define CAN_F12R1_FB29_Pos (29U)
+#define CAN_F12R1_FB29_Msk (0x1U << CAN_F12R1_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F12R1_FB29 CAN_F12R1_FB29_Msk /*!< Filter bit 29 */
+#define CAN_F12R1_FB30_Pos (30U)
+#define CAN_F12R1_FB30_Msk (0x1U << CAN_F12R1_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F12R1_FB30 CAN_F12R1_FB30_Msk /*!< Filter bit 30 */
+#define CAN_F12R1_FB31_Pos (31U)
+#define CAN_F12R1_FB31_Msk (0x1U << CAN_F12R1_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F12R1_FB31 CAN_F12R1_FB31_Msk /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F13R1 register ******************/
+#define CAN_F13R1_FB0_Pos (0U)
+#define CAN_F13R1_FB0_Msk (0x1U << CAN_F13R1_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F13R1_FB0 CAN_F13R1_FB0_Msk /*!< Filter bit 0 */
+#define CAN_F13R1_FB1_Pos (1U)
+#define CAN_F13R1_FB1_Msk (0x1U << CAN_F13R1_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F13R1_FB1 CAN_F13R1_FB1_Msk /*!< Filter bit 1 */
+#define CAN_F13R1_FB2_Pos (2U)
+#define CAN_F13R1_FB2_Msk (0x1U << CAN_F13R1_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F13R1_FB2 CAN_F13R1_FB2_Msk /*!< Filter bit 2 */
+#define CAN_F13R1_FB3_Pos (3U)
+#define CAN_F13R1_FB3_Msk (0x1U << CAN_F13R1_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F13R1_FB3 CAN_F13R1_FB3_Msk /*!< Filter bit 3 */
+#define CAN_F13R1_FB4_Pos (4U)
+#define CAN_F13R1_FB4_Msk (0x1U << CAN_F13R1_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F13R1_FB4 CAN_F13R1_FB4_Msk /*!< Filter bit 4 */
+#define CAN_F13R1_FB5_Pos (5U)
+#define CAN_F13R1_FB5_Msk (0x1U << CAN_F13R1_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F13R1_FB5 CAN_F13R1_FB5_Msk /*!< Filter bit 5 */
+#define CAN_F13R1_FB6_Pos (6U)
+#define CAN_F13R1_FB6_Msk (0x1U << CAN_F13R1_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F13R1_FB6 CAN_F13R1_FB6_Msk /*!< Filter bit 6 */
+#define CAN_F13R1_FB7_Pos (7U)
+#define CAN_F13R1_FB7_Msk (0x1U << CAN_F13R1_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F13R1_FB7 CAN_F13R1_FB7_Msk /*!< Filter bit 7 */
+#define CAN_F13R1_FB8_Pos (8U)
+#define CAN_F13R1_FB8_Msk (0x1U << CAN_F13R1_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F13R1_FB8 CAN_F13R1_FB8_Msk /*!< Filter bit 8 */
+#define CAN_F13R1_FB9_Pos (9U)
+#define CAN_F13R1_FB9_Msk (0x1U << CAN_F13R1_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F13R1_FB9 CAN_F13R1_FB9_Msk /*!< Filter bit 9 */
+#define CAN_F13R1_FB10_Pos (10U)
+#define CAN_F13R1_FB10_Msk (0x1U << CAN_F13R1_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F13R1_FB10 CAN_F13R1_FB10_Msk /*!< Filter bit 10 */
+#define CAN_F13R1_FB11_Pos (11U)
+#define CAN_F13R1_FB11_Msk (0x1U << CAN_F13R1_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F13R1_FB11 CAN_F13R1_FB11_Msk /*!< Filter bit 11 */
+#define CAN_F13R1_FB12_Pos (12U)
+#define CAN_F13R1_FB12_Msk (0x1U << CAN_F13R1_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F13R1_FB12 CAN_F13R1_FB12_Msk /*!< Filter bit 12 */
+#define CAN_F13R1_FB13_Pos (13U)
+#define CAN_F13R1_FB13_Msk (0x1U << CAN_F13R1_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F13R1_FB13 CAN_F13R1_FB13_Msk /*!< Filter bit 13 */
+#define CAN_F13R1_FB14_Pos (14U)
+#define CAN_F13R1_FB14_Msk (0x1U << CAN_F13R1_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F13R1_FB14 CAN_F13R1_FB14_Msk /*!< Filter bit 14 */
+#define CAN_F13R1_FB15_Pos (15U)
+#define CAN_F13R1_FB15_Msk (0x1U << CAN_F13R1_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F13R1_FB15 CAN_F13R1_FB15_Msk /*!< Filter bit 15 */
+#define CAN_F13R1_FB16_Pos (16U)
+#define CAN_F13R1_FB16_Msk (0x1U << CAN_F13R1_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F13R1_FB16 CAN_F13R1_FB16_Msk /*!< Filter bit 16 */
+#define CAN_F13R1_FB17_Pos (17U)
+#define CAN_F13R1_FB17_Msk (0x1U << CAN_F13R1_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F13R1_FB17 CAN_F13R1_FB17_Msk /*!< Filter bit 17 */
+#define CAN_F13R1_FB18_Pos (18U)
+#define CAN_F13R1_FB18_Msk (0x1U << CAN_F13R1_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F13R1_FB18 CAN_F13R1_FB18_Msk /*!< Filter bit 18 */
+#define CAN_F13R1_FB19_Pos (19U)
+#define CAN_F13R1_FB19_Msk (0x1U << CAN_F13R1_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F13R1_FB19 CAN_F13R1_FB19_Msk /*!< Filter bit 19 */
+#define CAN_F13R1_FB20_Pos (20U)
+#define CAN_F13R1_FB20_Msk (0x1U << CAN_F13R1_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F13R1_FB20 CAN_F13R1_FB20_Msk /*!< Filter bit 20 */
+#define CAN_F13R1_FB21_Pos (21U)
+#define CAN_F13R1_FB21_Msk (0x1U << CAN_F13R1_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F13R1_FB21 CAN_F13R1_FB21_Msk /*!< Filter bit 21 */
+#define CAN_F13R1_FB22_Pos (22U)
+#define CAN_F13R1_FB22_Msk (0x1U << CAN_F13R1_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F13R1_FB22 CAN_F13R1_FB22_Msk /*!< Filter bit 22 */
+#define CAN_F13R1_FB23_Pos (23U)
+#define CAN_F13R1_FB23_Msk (0x1U << CAN_F13R1_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F13R1_FB23 CAN_F13R1_FB23_Msk /*!< Filter bit 23 */
+#define CAN_F13R1_FB24_Pos (24U)
+#define CAN_F13R1_FB24_Msk (0x1U << CAN_F13R1_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F13R1_FB24 CAN_F13R1_FB24_Msk /*!< Filter bit 24 */
+#define CAN_F13R1_FB25_Pos (25U)
+#define CAN_F13R1_FB25_Msk (0x1U << CAN_F13R1_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F13R1_FB25 CAN_F13R1_FB25_Msk /*!< Filter bit 25 */
+#define CAN_F13R1_FB26_Pos (26U)
+#define CAN_F13R1_FB26_Msk (0x1U << CAN_F13R1_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F13R1_FB26 CAN_F13R1_FB26_Msk /*!< Filter bit 26 */
+#define CAN_F13R1_FB27_Pos (27U)
+#define CAN_F13R1_FB27_Msk (0x1U << CAN_F13R1_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F13R1_FB27 CAN_F13R1_FB27_Msk /*!< Filter bit 27 */
+#define CAN_F13R1_FB28_Pos (28U)
+#define CAN_F13R1_FB28_Msk (0x1U << CAN_F13R1_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F13R1_FB28 CAN_F13R1_FB28_Msk /*!< Filter bit 28 */
+#define CAN_F13R1_FB29_Pos (29U)
+#define CAN_F13R1_FB29_Msk (0x1U << CAN_F13R1_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F13R1_FB29 CAN_F13R1_FB29_Msk /*!< Filter bit 29 */
+#define CAN_F13R1_FB30_Pos (30U)
+#define CAN_F13R1_FB30_Msk (0x1U << CAN_F13R1_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F13R1_FB30 CAN_F13R1_FB30_Msk /*!< Filter bit 30 */
+#define CAN_F13R1_FB31_Pos (31U)
+#define CAN_F13R1_FB31_Msk (0x1U << CAN_F13R1_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F13R1_FB31 CAN_F13R1_FB31_Msk /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F0R2 register *******************/
+#define CAN_F0R2_FB0_Pos (0U)
+#define CAN_F0R2_FB0_Msk (0x1U << CAN_F0R2_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F0R2_FB0 CAN_F0R2_FB0_Msk /*!< Filter bit 0 */
+#define CAN_F0R2_FB1_Pos (1U)
+#define CAN_F0R2_FB1_Msk (0x1U << CAN_F0R2_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F0R2_FB1 CAN_F0R2_FB1_Msk /*!< Filter bit 1 */
+#define CAN_F0R2_FB2_Pos (2U)
+#define CAN_F0R2_FB2_Msk (0x1U << CAN_F0R2_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F0R2_FB2 CAN_F0R2_FB2_Msk /*!< Filter bit 2 */
+#define CAN_F0R2_FB3_Pos (3U)
+#define CAN_F0R2_FB3_Msk (0x1U << CAN_F0R2_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F0R2_FB3 CAN_F0R2_FB3_Msk /*!< Filter bit 3 */
+#define CAN_F0R2_FB4_Pos (4U)
+#define CAN_F0R2_FB4_Msk (0x1U << CAN_F0R2_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F0R2_FB4 CAN_F0R2_FB4_Msk /*!< Filter bit 4 */
+#define CAN_F0R2_FB5_Pos (5U)
+#define CAN_F0R2_FB5_Msk (0x1U << CAN_F0R2_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F0R2_FB5 CAN_F0R2_FB5_Msk /*!< Filter bit 5 */
+#define CAN_F0R2_FB6_Pos (6U)
+#define CAN_F0R2_FB6_Msk (0x1U << CAN_F0R2_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F0R2_FB6 CAN_F0R2_FB6_Msk /*!< Filter bit 6 */
+#define CAN_F0R2_FB7_Pos (7U)
+#define CAN_F0R2_FB7_Msk (0x1U << CAN_F0R2_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F0R2_FB7 CAN_F0R2_FB7_Msk /*!< Filter bit 7 */
+#define CAN_F0R2_FB8_Pos (8U)
+#define CAN_F0R2_FB8_Msk (0x1U << CAN_F0R2_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F0R2_FB8 CAN_F0R2_FB8_Msk /*!< Filter bit 8 */
+#define CAN_F0R2_FB9_Pos (9U)
+#define CAN_F0R2_FB9_Msk (0x1U << CAN_F0R2_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F0R2_FB9 CAN_F0R2_FB9_Msk /*!< Filter bit 9 */
+#define CAN_F0R2_FB10_Pos (10U)
+#define CAN_F0R2_FB10_Msk (0x1U << CAN_F0R2_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F0R2_FB10 CAN_F0R2_FB10_Msk /*!< Filter bit 10 */
+#define CAN_F0R2_FB11_Pos (11U)
+#define CAN_F0R2_FB11_Msk (0x1U << CAN_F0R2_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F0R2_FB11 CAN_F0R2_FB11_Msk /*!< Filter bit 11 */
+#define CAN_F0R2_FB12_Pos (12U)
+#define CAN_F0R2_FB12_Msk (0x1U << CAN_F0R2_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F0R2_FB12 CAN_F0R2_FB12_Msk /*!< Filter bit 12 */
+#define CAN_F0R2_FB13_Pos (13U)
+#define CAN_F0R2_FB13_Msk (0x1U << CAN_F0R2_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F0R2_FB13 CAN_F0R2_FB13_Msk /*!< Filter bit 13 */
+#define CAN_F0R2_FB14_Pos (14U)
+#define CAN_F0R2_FB14_Msk (0x1U << CAN_F0R2_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F0R2_FB14 CAN_F0R2_FB14_Msk /*!< Filter bit 14 */
+#define CAN_F0R2_FB15_Pos (15U)
+#define CAN_F0R2_FB15_Msk (0x1U << CAN_F0R2_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F0R2_FB15 CAN_F0R2_FB15_Msk /*!< Filter bit 15 */
+#define CAN_F0R2_FB16_Pos (16U)
+#define CAN_F0R2_FB16_Msk (0x1U << CAN_F0R2_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F0R2_FB16 CAN_F0R2_FB16_Msk /*!< Filter bit 16 */
+#define CAN_F0R2_FB17_Pos (17U)
+#define CAN_F0R2_FB17_Msk (0x1U << CAN_F0R2_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F0R2_FB17 CAN_F0R2_FB17_Msk /*!< Filter bit 17 */
+#define CAN_F0R2_FB18_Pos (18U)
+#define CAN_F0R2_FB18_Msk (0x1U << CAN_F0R2_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F0R2_FB18 CAN_F0R2_FB18_Msk /*!< Filter bit 18 */
+#define CAN_F0R2_FB19_Pos (19U)
+#define CAN_F0R2_FB19_Msk (0x1U << CAN_F0R2_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F0R2_FB19 CAN_F0R2_FB19_Msk /*!< Filter bit 19 */
+#define CAN_F0R2_FB20_Pos (20U)
+#define CAN_F0R2_FB20_Msk (0x1U << CAN_F0R2_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F0R2_FB20 CAN_F0R2_FB20_Msk /*!< Filter bit 20 */
+#define CAN_F0R2_FB21_Pos (21U)
+#define CAN_F0R2_FB21_Msk (0x1U << CAN_F0R2_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F0R2_FB21 CAN_F0R2_FB21_Msk /*!< Filter bit 21 */
+#define CAN_F0R2_FB22_Pos (22U)
+#define CAN_F0R2_FB22_Msk (0x1U << CAN_F0R2_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F0R2_FB22 CAN_F0R2_FB22_Msk /*!< Filter bit 22 */
+#define CAN_F0R2_FB23_Pos (23U)
+#define CAN_F0R2_FB23_Msk (0x1U << CAN_F0R2_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F0R2_FB23 CAN_F0R2_FB23_Msk /*!< Filter bit 23 */
+#define CAN_F0R2_FB24_Pos (24U)
+#define CAN_F0R2_FB24_Msk (0x1U << CAN_F0R2_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F0R2_FB24 CAN_F0R2_FB24_Msk /*!< Filter bit 24 */
+#define CAN_F0R2_FB25_Pos (25U)
+#define CAN_F0R2_FB25_Msk (0x1U << CAN_F0R2_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F0R2_FB25 CAN_F0R2_FB25_Msk /*!< Filter bit 25 */
+#define CAN_F0R2_FB26_Pos (26U)
+#define CAN_F0R2_FB26_Msk (0x1U << CAN_F0R2_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F0R2_FB26 CAN_F0R2_FB26_Msk /*!< Filter bit 26 */
+#define CAN_F0R2_FB27_Pos (27U)
+#define CAN_F0R2_FB27_Msk (0x1U << CAN_F0R2_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F0R2_FB27 CAN_F0R2_FB27_Msk /*!< Filter bit 27 */
+#define CAN_F0R2_FB28_Pos (28U)
+#define CAN_F0R2_FB28_Msk (0x1U << CAN_F0R2_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F0R2_FB28 CAN_F0R2_FB28_Msk /*!< Filter bit 28 */
+#define CAN_F0R2_FB29_Pos (29U)
+#define CAN_F0R2_FB29_Msk (0x1U << CAN_F0R2_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F0R2_FB29 CAN_F0R2_FB29_Msk /*!< Filter bit 29 */
+#define CAN_F0R2_FB30_Pos (30U)
+#define CAN_F0R2_FB30_Msk (0x1U << CAN_F0R2_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F0R2_FB30 CAN_F0R2_FB30_Msk /*!< Filter bit 30 */
+#define CAN_F0R2_FB31_Pos (31U)
+#define CAN_F0R2_FB31_Msk (0x1U << CAN_F0R2_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F0R2_FB31 CAN_F0R2_FB31_Msk /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F1R2 register *******************/
+#define CAN_F1R2_FB0_Pos (0U)
+#define CAN_F1R2_FB0_Msk (0x1U << CAN_F1R2_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F1R2_FB0 CAN_F1R2_FB0_Msk /*!< Filter bit 0 */
+#define CAN_F1R2_FB1_Pos (1U)
+#define CAN_F1R2_FB1_Msk (0x1U << CAN_F1R2_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F1R2_FB1 CAN_F1R2_FB1_Msk /*!< Filter bit 1 */
+#define CAN_F1R2_FB2_Pos (2U)
+#define CAN_F1R2_FB2_Msk (0x1U << CAN_F1R2_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F1R2_FB2 CAN_F1R2_FB2_Msk /*!< Filter bit 2 */
+#define CAN_F1R2_FB3_Pos (3U)
+#define CAN_F1R2_FB3_Msk (0x1U << CAN_F1R2_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F1R2_FB3 CAN_F1R2_FB3_Msk /*!< Filter bit 3 */
+#define CAN_F1R2_FB4_Pos (4U)
+#define CAN_F1R2_FB4_Msk (0x1U << CAN_F1R2_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F1R2_FB4 CAN_F1R2_FB4_Msk /*!< Filter bit 4 */
+#define CAN_F1R2_FB5_Pos (5U)
+#define CAN_F1R2_FB5_Msk (0x1U << CAN_F1R2_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F1R2_FB5 CAN_F1R2_FB5_Msk /*!< Filter bit 5 */
+#define CAN_F1R2_FB6_Pos (6U)
+#define CAN_F1R2_FB6_Msk (0x1U << CAN_F1R2_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F1R2_FB6 CAN_F1R2_FB6_Msk /*!< Filter bit 6 */
+#define CAN_F1R2_FB7_Pos (7U)
+#define CAN_F1R2_FB7_Msk (0x1U << CAN_F1R2_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F1R2_FB7 CAN_F1R2_FB7_Msk /*!< Filter bit 7 */
+#define CAN_F1R2_FB8_Pos (8U)
+#define CAN_F1R2_FB8_Msk (0x1U << CAN_F1R2_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F1R2_FB8 CAN_F1R2_FB8_Msk /*!< Filter bit 8 */
+#define CAN_F1R2_FB9_Pos (9U)
+#define CAN_F1R2_FB9_Msk (0x1U << CAN_F1R2_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F1R2_FB9 CAN_F1R2_FB9_Msk /*!< Filter bit 9 */
+#define CAN_F1R2_FB10_Pos (10U)
+#define CAN_F1R2_FB10_Msk (0x1U << CAN_F1R2_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F1R2_FB10 CAN_F1R2_FB10_Msk /*!< Filter bit 10 */
+#define CAN_F1R2_FB11_Pos (11U)
+#define CAN_F1R2_FB11_Msk (0x1U << CAN_F1R2_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F1R2_FB11 CAN_F1R2_FB11_Msk /*!< Filter bit 11 */
+#define CAN_F1R2_FB12_Pos (12U)
+#define CAN_F1R2_FB12_Msk (0x1U << CAN_F1R2_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F1R2_FB12 CAN_F1R2_FB12_Msk /*!< Filter bit 12 */
+#define CAN_F1R2_FB13_Pos (13U)
+#define CAN_F1R2_FB13_Msk (0x1U << CAN_F1R2_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F1R2_FB13 CAN_F1R2_FB13_Msk /*!< Filter bit 13 */
+#define CAN_F1R2_FB14_Pos (14U)
+#define CAN_F1R2_FB14_Msk (0x1U << CAN_F1R2_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F1R2_FB14 CAN_F1R2_FB14_Msk /*!< Filter bit 14 */
+#define CAN_F1R2_FB15_Pos (15U)
+#define CAN_F1R2_FB15_Msk (0x1U << CAN_F1R2_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F1R2_FB15 CAN_F1R2_FB15_Msk /*!< Filter bit 15 */
+#define CAN_F1R2_FB16_Pos (16U)
+#define CAN_F1R2_FB16_Msk (0x1U << CAN_F1R2_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F1R2_FB16 CAN_F1R2_FB16_Msk /*!< Filter bit 16 */
+#define CAN_F1R2_FB17_Pos (17U)
+#define CAN_F1R2_FB17_Msk (0x1U << CAN_F1R2_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F1R2_FB17 CAN_F1R2_FB17_Msk /*!< Filter bit 17 */
+#define CAN_F1R2_FB18_Pos (18U)
+#define CAN_F1R2_FB18_Msk (0x1U << CAN_F1R2_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F1R2_FB18 CAN_F1R2_FB18_Msk /*!< Filter bit 18 */
+#define CAN_F1R2_FB19_Pos (19U)
+#define CAN_F1R2_FB19_Msk (0x1U << CAN_F1R2_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F1R2_FB19 CAN_F1R2_FB19_Msk /*!< Filter bit 19 */
+#define CAN_F1R2_FB20_Pos (20U)
+#define CAN_F1R2_FB20_Msk (0x1U << CAN_F1R2_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F1R2_FB20 CAN_F1R2_FB20_Msk /*!< Filter bit 20 */
+#define CAN_F1R2_FB21_Pos (21U)
+#define CAN_F1R2_FB21_Msk (0x1U << CAN_F1R2_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F1R2_FB21 CAN_F1R2_FB21_Msk /*!< Filter bit 21 */
+#define CAN_F1R2_FB22_Pos (22U)
+#define CAN_F1R2_FB22_Msk (0x1U << CAN_F1R2_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F1R2_FB22 CAN_F1R2_FB22_Msk /*!< Filter bit 22 */
+#define CAN_F1R2_FB23_Pos (23U)
+#define CAN_F1R2_FB23_Msk (0x1U << CAN_F1R2_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F1R2_FB23 CAN_F1R2_FB23_Msk /*!< Filter bit 23 */
+#define CAN_F1R2_FB24_Pos (24U)
+#define CAN_F1R2_FB24_Msk (0x1U << CAN_F1R2_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F1R2_FB24 CAN_F1R2_FB24_Msk /*!< Filter bit 24 */
+#define CAN_F1R2_FB25_Pos (25U)
+#define CAN_F1R2_FB25_Msk (0x1U << CAN_F1R2_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F1R2_FB25 CAN_F1R2_FB25_Msk /*!< Filter bit 25 */
+#define CAN_F1R2_FB26_Pos (26U)
+#define CAN_F1R2_FB26_Msk (0x1U << CAN_F1R2_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F1R2_FB26 CAN_F1R2_FB26_Msk /*!< Filter bit 26 */
+#define CAN_F1R2_FB27_Pos (27U)
+#define CAN_F1R2_FB27_Msk (0x1U << CAN_F1R2_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F1R2_FB27 CAN_F1R2_FB27_Msk /*!< Filter bit 27 */
+#define CAN_F1R2_FB28_Pos (28U)
+#define CAN_F1R2_FB28_Msk (0x1U << CAN_F1R2_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F1R2_FB28 CAN_F1R2_FB28_Msk /*!< Filter bit 28 */
+#define CAN_F1R2_FB29_Pos (29U)
+#define CAN_F1R2_FB29_Msk (0x1U << CAN_F1R2_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F1R2_FB29 CAN_F1R2_FB29_Msk /*!< Filter bit 29 */
+#define CAN_F1R2_FB30_Pos (30U)
+#define CAN_F1R2_FB30_Msk (0x1U << CAN_F1R2_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F1R2_FB30 CAN_F1R2_FB30_Msk /*!< Filter bit 30 */
+#define CAN_F1R2_FB31_Pos (31U)
+#define CAN_F1R2_FB31_Msk (0x1U << CAN_F1R2_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F1R2_FB31 CAN_F1R2_FB31_Msk /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F2R2 register *******************/
+#define CAN_F2R2_FB0_Pos (0U)
+#define CAN_F2R2_FB0_Msk (0x1U << CAN_F2R2_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F2R2_FB0 CAN_F2R2_FB0_Msk /*!< Filter bit 0 */
+#define CAN_F2R2_FB1_Pos (1U)
+#define CAN_F2R2_FB1_Msk (0x1U << CAN_F2R2_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F2R2_FB1 CAN_F2R2_FB1_Msk /*!< Filter bit 1 */
+#define CAN_F2R2_FB2_Pos (2U)
+#define CAN_F2R2_FB2_Msk (0x1U << CAN_F2R2_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F2R2_FB2 CAN_F2R2_FB2_Msk /*!< Filter bit 2 */
+#define CAN_F2R2_FB3_Pos (3U)
+#define CAN_F2R2_FB3_Msk (0x1U << CAN_F2R2_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F2R2_FB3 CAN_F2R2_FB3_Msk /*!< Filter bit 3 */
+#define CAN_F2R2_FB4_Pos (4U)
+#define CAN_F2R2_FB4_Msk (0x1U << CAN_F2R2_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F2R2_FB4 CAN_F2R2_FB4_Msk /*!< Filter bit 4 */
+#define CAN_F2R2_FB5_Pos (5U)
+#define CAN_F2R2_FB5_Msk (0x1U << CAN_F2R2_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F2R2_FB5 CAN_F2R2_FB5_Msk /*!< Filter bit 5 */
+#define CAN_F2R2_FB6_Pos (6U)
+#define CAN_F2R2_FB6_Msk (0x1U << CAN_F2R2_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F2R2_FB6 CAN_F2R2_FB6_Msk /*!< Filter bit 6 */
+#define CAN_F2R2_FB7_Pos (7U)
+#define CAN_F2R2_FB7_Msk (0x1U << CAN_F2R2_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F2R2_FB7 CAN_F2R2_FB7_Msk /*!< Filter bit 7 */
+#define CAN_F2R2_FB8_Pos (8U)
+#define CAN_F2R2_FB8_Msk (0x1U << CAN_F2R2_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F2R2_FB8 CAN_F2R2_FB8_Msk /*!< Filter bit 8 */
+#define CAN_F2R2_FB9_Pos (9U)
+#define CAN_F2R2_FB9_Msk (0x1U << CAN_F2R2_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F2R2_FB9 CAN_F2R2_FB9_Msk /*!< Filter bit 9 */
+#define CAN_F2R2_FB10_Pos (10U)
+#define CAN_F2R2_FB10_Msk (0x1U << CAN_F2R2_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F2R2_FB10 CAN_F2R2_FB10_Msk /*!< Filter bit 10 */
+#define CAN_F2R2_FB11_Pos (11U)
+#define CAN_F2R2_FB11_Msk (0x1U << CAN_F2R2_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F2R2_FB11 CAN_F2R2_FB11_Msk /*!< Filter bit 11 */
+#define CAN_F2R2_FB12_Pos (12U)
+#define CAN_F2R2_FB12_Msk (0x1U << CAN_F2R2_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F2R2_FB12 CAN_F2R2_FB12_Msk /*!< Filter bit 12 */
+#define CAN_F2R2_FB13_Pos (13U)
+#define CAN_F2R2_FB13_Msk (0x1U << CAN_F2R2_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F2R2_FB13 CAN_F2R2_FB13_Msk /*!< Filter bit 13 */
+#define CAN_F2R2_FB14_Pos (14U)
+#define CAN_F2R2_FB14_Msk (0x1U << CAN_F2R2_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F2R2_FB14 CAN_F2R2_FB14_Msk /*!< Filter bit 14 */
+#define CAN_F2R2_FB15_Pos (15U)
+#define CAN_F2R2_FB15_Msk (0x1U << CAN_F2R2_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F2R2_FB15 CAN_F2R2_FB15_Msk /*!< Filter bit 15 */
+#define CAN_F2R2_FB16_Pos (16U)
+#define CAN_F2R2_FB16_Msk (0x1U << CAN_F2R2_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F2R2_FB16 CAN_F2R2_FB16_Msk /*!< Filter bit 16 */
+#define CAN_F2R2_FB17_Pos (17U)
+#define CAN_F2R2_FB17_Msk (0x1U << CAN_F2R2_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F2R2_FB17 CAN_F2R2_FB17_Msk /*!< Filter bit 17 */
+#define CAN_F2R2_FB18_Pos (18U)
+#define CAN_F2R2_FB18_Msk (0x1U << CAN_F2R2_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F2R2_FB18 CAN_F2R2_FB18_Msk /*!< Filter bit 18 */
+#define CAN_F2R2_FB19_Pos (19U)
+#define CAN_F2R2_FB19_Msk (0x1U << CAN_F2R2_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F2R2_FB19 CAN_F2R2_FB19_Msk /*!< Filter bit 19 */
+#define CAN_F2R2_FB20_Pos (20U)
+#define CAN_F2R2_FB20_Msk (0x1U << CAN_F2R2_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F2R2_FB20 CAN_F2R2_FB20_Msk /*!< Filter bit 20 */
+#define CAN_F2R2_FB21_Pos (21U)
+#define CAN_F2R2_FB21_Msk (0x1U << CAN_F2R2_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F2R2_FB21 CAN_F2R2_FB21_Msk /*!< Filter bit 21 */
+#define CAN_F2R2_FB22_Pos (22U)
+#define CAN_F2R2_FB22_Msk (0x1U << CAN_F2R2_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F2R2_FB22 CAN_F2R2_FB22_Msk /*!< Filter bit 22 */
+#define CAN_F2R2_FB23_Pos (23U)
+#define CAN_F2R2_FB23_Msk (0x1U << CAN_F2R2_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F2R2_FB23 CAN_F2R2_FB23_Msk /*!< Filter bit 23 */
+#define CAN_F2R2_FB24_Pos (24U)
+#define CAN_F2R2_FB24_Msk (0x1U << CAN_F2R2_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F2R2_FB24 CAN_F2R2_FB24_Msk /*!< Filter bit 24 */
+#define CAN_F2R2_FB25_Pos (25U)
+#define CAN_F2R2_FB25_Msk (0x1U << CAN_F2R2_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F2R2_FB25 CAN_F2R2_FB25_Msk /*!< Filter bit 25 */
+#define CAN_F2R2_FB26_Pos (26U)
+#define CAN_F2R2_FB26_Msk (0x1U << CAN_F2R2_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F2R2_FB26 CAN_F2R2_FB26_Msk /*!< Filter bit 26 */
+#define CAN_F2R2_FB27_Pos (27U)
+#define CAN_F2R2_FB27_Msk (0x1U << CAN_F2R2_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F2R2_FB27 CAN_F2R2_FB27_Msk /*!< Filter bit 27 */
+#define CAN_F2R2_FB28_Pos (28U)
+#define CAN_F2R2_FB28_Msk (0x1U << CAN_F2R2_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F2R2_FB28 CAN_F2R2_FB28_Msk /*!< Filter bit 28 */
+#define CAN_F2R2_FB29_Pos (29U)
+#define CAN_F2R2_FB29_Msk (0x1U << CAN_F2R2_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F2R2_FB29 CAN_F2R2_FB29_Msk /*!< Filter bit 29 */
+#define CAN_F2R2_FB30_Pos (30U)
+#define CAN_F2R2_FB30_Msk (0x1U << CAN_F2R2_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F2R2_FB30 CAN_F2R2_FB30_Msk /*!< Filter bit 30 */
+#define CAN_F2R2_FB31_Pos (31U)
+#define CAN_F2R2_FB31_Msk (0x1U << CAN_F2R2_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F2R2_FB31 CAN_F2R2_FB31_Msk /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F3R2 register *******************/
+#define CAN_F3R2_FB0_Pos (0U)
+#define CAN_F3R2_FB0_Msk (0x1U << CAN_F3R2_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F3R2_FB0 CAN_F3R2_FB0_Msk /*!< Filter bit 0 */
+#define CAN_F3R2_FB1_Pos (1U)
+#define CAN_F3R2_FB1_Msk (0x1U << CAN_F3R2_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F3R2_FB1 CAN_F3R2_FB1_Msk /*!< Filter bit 1 */
+#define CAN_F3R2_FB2_Pos (2U)
+#define CAN_F3R2_FB2_Msk (0x1U << CAN_F3R2_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F3R2_FB2 CAN_F3R2_FB2_Msk /*!< Filter bit 2 */
+#define CAN_F3R2_FB3_Pos (3U)
+#define CAN_F3R2_FB3_Msk (0x1U << CAN_F3R2_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F3R2_FB3 CAN_F3R2_FB3_Msk /*!< Filter bit 3 */
+#define CAN_F3R2_FB4_Pos (4U)
+#define CAN_F3R2_FB4_Msk (0x1U << CAN_F3R2_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F3R2_FB4 CAN_F3R2_FB4_Msk /*!< Filter bit 4 */
+#define CAN_F3R2_FB5_Pos (5U)
+#define CAN_F3R2_FB5_Msk (0x1U << CAN_F3R2_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F3R2_FB5 CAN_F3R2_FB5_Msk /*!< Filter bit 5 */
+#define CAN_F3R2_FB6_Pos (6U)
+#define CAN_F3R2_FB6_Msk (0x1U << CAN_F3R2_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F3R2_FB6 CAN_F3R2_FB6_Msk /*!< Filter bit 6 */
+#define CAN_F3R2_FB7_Pos (7U)
+#define CAN_F3R2_FB7_Msk (0x1U << CAN_F3R2_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F3R2_FB7 CAN_F3R2_FB7_Msk /*!< Filter bit 7 */
+#define CAN_F3R2_FB8_Pos (8U)
+#define CAN_F3R2_FB8_Msk (0x1U << CAN_F3R2_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F3R2_FB8 CAN_F3R2_FB8_Msk /*!< Filter bit 8 */
+#define CAN_F3R2_FB9_Pos (9U)
+#define CAN_F3R2_FB9_Msk (0x1U << CAN_F3R2_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F3R2_FB9 CAN_F3R2_FB9_Msk /*!< Filter bit 9 */
+#define CAN_F3R2_FB10_Pos (10U)
+#define CAN_F3R2_FB10_Msk (0x1U << CAN_F3R2_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F3R2_FB10 CAN_F3R2_FB10_Msk /*!< Filter bit 10 */
+#define CAN_F3R2_FB11_Pos (11U)
+#define CAN_F3R2_FB11_Msk (0x1U << CAN_F3R2_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F3R2_FB11 CAN_F3R2_FB11_Msk /*!< Filter bit 11 */
+#define CAN_F3R2_FB12_Pos (12U)
+#define CAN_F3R2_FB12_Msk (0x1U << CAN_F3R2_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F3R2_FB12 CAN_F3R2_FB12_Msk /*!< Filter bit 12 */
+#define CAN_F3R2_FB13_Pos (13U)
+#define CAN_F3R2_FB13_Msk (0x1U << CAN_F3R2_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F3R2_FB13 CAN_F3R2_FB13_Msk /*!< Filter bit 13 */
+#define CAN_F3R2_FB14_Pos (14U)
+#define CAN_F3R2_FB14_Msk (0x1U << CAN_F3R2_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F3R2_FB14 CAN_F3R2_FB14_Msk /*!< Filter bit 14 */
+#define CAN_F3R2_FB15_Pos (15U)
+#define CAN_F3R2_FB15_Msk (0x1U << CAN_F3R2_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F3R2_FB15 CAN_F3R2_FB15_Msk /*!< Filter bit 15 */
+#define CAN_F3R2_FB16_Pos (16U)
+#define CAN_F3R2_FB16_Msk (0x1U << CAN_F3R2_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F3R2_FB16 CAN_F3R2_FB16_Msk /*!< Filter bit 16 */
+#define CAN_F3R2_FB17_Pos (17U)
+#define CAN_F3R2_FB17_Msk (0x1U << CAN_F3R2_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F3R2_FB17 CAN_F3R2_FB17_Msk /*!< Filter bit 17 */
+#define CAN_F3R2_FB18_Pos (18U)
+#define CAN_F3R2_FB18_Msk (0x1U << CAN_F3R2_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F3R2_FB18 CAN_F3R2_FB18_Msk /*!< Filter bit 18 */
+#define CAN_F3R2_FB19_Pos (19U)
+#define CAN_F3R2_FB19_Msk (0x1U << CAN_F3R2_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F3R2_FB19 CAN_F3R2_FB19_Msk /*!< Filter bit 19 */
+#define CAN_F3R2_FB20_Pos (20U)
+#define CAN_F3R2_FB20_Msk (0x1U << CAN_F3R2_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F3R2_FB20 CAN_F3R2_FB20_Msk /*!< Filter bit 20 */
+#define CAN_F3R2_FB21_Pos (21U)
+#define CAN_F3R2_FB21_Msk (0x1U << CAN_F3R2_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F3R2_FB21 CAN_F3R2_FB21_Msk /*!< Filter bit 21 */
+#define CAN_F3R2_FB22_Pos (22U)
+#define CAN_F3R2_FB22_Msk (0x1U << CAN_F3R2_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F3R2_FB22 CAN_F3R2_FB22_Msk /*!< Filter bit 22 */
+#define CAN_F3R2_FB23_Pos (23U)
+#define CAN_F3R2_FB23_Msk (0x1U << CAN_F3R2_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F3R2_FB23 CAN_F3R2_FB23_Msk /*!< Filter bit 23 */
+#define CAN_F3R2_FB24_Pos (24U)
+#define CAN_F3R2_FB24_Msk (0x1U << CAN_F3R2_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F3R2_FB24 CAN_F3R2_FB24_Msk /*!< Filter bit 24 */
+#define CAN_F3R2_FB25_Pos (25U)
+#define CAN_F3R2_FB25_Msk (0x1U << CAN_F3R2_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F3R2_FB25 CAN_F3R2_FB25_Msk /*!< Filter bit 25 */
+#define CAN_F3R2_FB26_Pos (26U)
+#define CAN_F3R2_FB26_Msk (0x1U << CAN_F3R2_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F3R2_FB26 CAN_F3R2_FB26_Msk /*!< Filter bit 26 */
+#define CAN_F3R2_FB27_Pos (27U)
+#define CAN_F3R2_FB27_Msk (0x1U << CAN_F3R2_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F3R2_FB27 CAN_F3R2_FB27_Msk /*!< Filter bit 27 */
+#define CAN_F3R2_FB28_Pos (28U)
+#define CAN_F3R2_FB28_Msk (0x1U << CAN_F3R2_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F3R2_FB28 CAN_F3R2_FB28_Msk /*!< Filter bit 28 */
+#define CAN_F3R2_FB29_Pos (29U)
+#define CAN_F3R2_FB29_Msk (0x1U << CAN_F3R2_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F3R2_FB29 CAN_F3R2_FB29_Msk /*!< Filter bit 29 */
+#define CAN_F3R2_FB30_Pos (30U)
+#define CAN_F3R2_FB30_Msk (0x1U << CAN_F3R2_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F3R2_FB30 CAN_F3R2_FB30_Msk /*!< Filter bit 30 */
+#define CAN_F3R2_FB31_Pos (31U)
+#define CAN_F3R2_FB31_Msk (0x1U << CAN_F3R2_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F3R2_FB31 CAN_F3R2_FB31_Msk /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F4R2 register *******************/
+#define CAN_F4R2_FB0_Pos (0U)
+#define CAN_F4R2_FB0_Msk (0x1U << CAN_F4R2_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F4R2_FB0 CAN_F4R2_FB0_Msk /*!< Filter bit 0 */
+#define CAN_F4R2_FB1_Pos (1U)
+#define CAN_F4R2_FB1_Msk (0x1U << CAN_F4R2_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F4R2_FB1 CAN_F4R2_FB1_Msk /*!< Filter bit 1 */
+#define CAN_F4R2_FB2_Pos (2U)
+#define CAN_F4R2_FB2_Msk (0x1U << CAN_F4R2_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F4R2_FB2 CAN_F4R2_FB2_Msk /*!< Filter bit 2 */
+#define CAN_F4R2_FB3_Pos (3U)
+#define CAN_F4R2_FB3_Msk (0x1U << CAN_F4R2_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F4R2_FB3 CAN_F4R2_FB3_Msk /*!< Filter bit 3 */
+#define CAN_F4R2_FB4_Pos (4U)
+#define CAN_F4R2_FB4_Msk (0x1U << CAN_F4R2_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F4R2_FB4 CAN_F4R2_FB4_Msk /*!< Filter bit 4 */
+#define CAN_F4R2_FB5_Pos (5U)
+#define CAN_F4R2_FB5_Msk (0x1U << CAN_F4R2_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F4R2_FB5 CAN_F4R2_FB5_Msk /*!< Filter bit 5 */
+#define CAN_F4R2_FB6_Pos (6U)
+#define CAN_F4R2_FB6_Msk (0x1U << CAN_F4R2_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F4R2_FB6 CAN_F4R2_FB6_Msk /*!< Filter bit 6 */
+#define CAN_F4R2_FB7_Pos (7U)
+#define CAN_F4R2_FB7_Msk (0x1U << CAN_F4R2_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F4R2_FB7 CAN_F4R2_FB7_Msk /*!< Filter bit 7 */
+#define CAN_F4R2_FB8_Pos (8U)
+#define CAN_F4R2_FB8_Msk (0x1U << CAN_F4R2_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F4R2_FB8 CAN_F4R2_FB8_Msk /*!< Filter bit 8 */
+#define CAN_F4R2_FB9_Pos (9U)
+#define CAN_F4R2_FB9_Msk (0x1U << CAN_F4R2_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F4R2_FB9 CAN_F4R2_FB9_Msk /*!< Filter bit 9 */
+#define CAN_F4R2_FB10_Pos (10U)
+#define CAN_F4R2_FB10_Msk (0x1U << CAN_F4R2_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F4R2_FB10 CAN_F4R2_FB10_Msk /*!< Filter bit 10 */
+#define CAN_F4R2_FB11_Pos (11U)
+#define CAN_F4R2_FB11_Msk (0x1U << CAN_F4R2_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F4R2_FB11 CAN_F4R2_FB11_Msk /*!< Filter bit 11 */
+#define CAN_F4R2_FB12_Pos (12U)
+#define CAN_F4R2_FB12_Msk (0x1U << CAN_F4R2_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F4R2_FB12 CAN_F4R2_FB12_Msk /*!< Filter bit 12 */
+#define CAN_F4R2_FB13_Pos (13U)
+#define CAN_F4R2_FB13_Msk (0x1U << CAN_F4R2_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F4R2_FB13 CAN_F4R2_FB13_Msk /*!< Filter bit 13 */
+#define CAN_F4R2_FB14_Pos (14U)
+#define CAN_F4R2_FB14_Msk (0x1U << CAN_F4R2_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F4R2_FB14 CAN_F4R2_FB14_Msk /*!< Filter bit 14 */
+#define CAN_F4R2_FB15_Pos (15U)
+#define CAN_F4R2_FB15_Msk (0x1U << CAN_F4R2_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F4R2_FB15 CAN_F4R2_FB15_Msk /*!< Filter bit 15 */
+#define CAN_F4R2_FB16_Pos (16U)
+#define CAN_F4R2_FB16_Msk (0x1U << CAN_F4R2_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F4R2_FB16 CAN_F4R2_FB16_Msk /*!< Filter bit 16 */
+#define CAN_F4R2_FB17_Pos (17U)
+#define CAN_F4R2_FB17_Msk (0x1U << CAN_F4R2_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F4R2_FB17 CAN_F4R2_FB17_Msk /*!< Filter bit 17 */
+#define CAN_F4R2_FB18_Pos (18U)
+#define CAN_F4R2_FB18_Msk (0x1U << CAN_F4R2_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F4R2_FB18 CAN_F4R2_FB18_Msk /*!< Filter bit 18 */
+#define CAN_F4R2_FB19_Pos (19U)
+#define CAN_F4R2_FB19_Msk (0x1U << CAN_F4R2_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F4R2_FB19 CAN_F4R2_FB19_Msk /*!< Filter bit 19 */
+#define CAN_F4R2_FB20_Pos (20U)
+#define CAN_F4R2_FB20_Msk (0x1U << CAN_F4R2_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F4R2_FB20 CAN_F4R2_FB20_Msk /*!< Filter bit 20 */
+#define CAN_F4R2_FB21_Pos (21U)
+#define CAN_F4R2_FB21_Msk (0x1U << CAN_F4R2_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F4R2_FB21 CAN_F4R2_FB21_Msk /*!< Filter bit 21 */
+#define CAN_F4R2_FB22_Pos (22U)
+#define CAN_F4R2_FB22_Msk (0x1U << CAN_F4R2_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F4R2_FB22 CAN_F4R2_FB22_Msk /*!< Filter bit 22 */
+#define CAN_F4R2_FB23_Pos (23U)
+#define CAN_F4R2_FB23_Msk (0x1U << CAN_F4R2_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F4R2_FB23 CAN_F4R2_FB23_Msk /*!< Filter bit 23 */
+#define CAN_F4R2_FB24_Pos (24U)
+#define CAN_F4R2_FB24_Msk (0x1U << CAN_F4R2_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F4R2_FB24 CAN_F4R2_FB24_Msk /*!< Filter bit 24 */
+#define CAN_F4R2_FB25_Pos (25U)
+#define CAN_F4R2_FB25_Msk (0x1U << CAN_F4R2_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F4R2_FB25 CAN_F4R2_FB25_Msk /*!< Filter bit 25 */
+#define CAN_F4R2_FB26_Pos (26U)
+#define CAN_F4R2_FB26_Msk (0x1U << CAN_F4R2_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F4R2_FB26 CAN_F4R2_FB26_Msk /*!< Filter bit 26 */
+#define CAN_F4R2_FB27_Pos (27U)
+#define CAN_F4R2_FB27_Msk (0x1U << CAN_F4R2_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F4R2_FB27 CAN_F4R2_FB27_Msk /*!< Filter bit 27 */
+#define CAN_F4R2_FB28_Pos (28U)
+#define CAN_F4R2_FB28_Msk (0x1U << CAN_F4R2_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F4R2_FB28 CAN_F4R2_FB28_Msk /*!< Filter bit 28 */
+#define CAN_F4R2_FB29_Pos (29U)
+#define CAN_F4R2_FB29_Msk (0x1U << CAN_F4R2_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F4R2_FB29 CAN_F4R2_FB29_Msk /*!< Filter bit 29 */
+#define CAN_F4R2_FB30_Pos (30U)
+#define CAN_F4R2_FB30_Msk (0x1U << CAN_F4R2_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F4R2_FB30 CAN_F4R2_FB30_Msk /*!< Filter bit 30 */
+#define CAN_F4R2_FB31_Pos (31U)
+#define CAN_F4R2_FB31_Msk (0x1U << CAN_F4R2_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F4R2_FB31 CAN_F4R2_FB31_Msk /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F5R2 register *******************/
+#define CAN_F5R2_FB0_Pos (0U)
+#define CAN_F5R2_FB0_Msk (0x1U << CAN_F5R2_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F5R2_FB0 CAN_F5R2_FB0_Msk /*!< Filter bit 0 */
+#define CAN_F5R2_FB1_Pos (1U)
+#define CAN_F5R2_FB1_Msk (0x1U << CAN_F5R2_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F5R2_FB1 CAN_F5R2_FB1_Msk /*!< Filter bit 1 */
+#define CAN_F5R2_FB2_Pos (2U)
+#define CAN_F5R2_FB2_Msk (0x1U << CAN_F5R2_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F5R2_FB2 CAN_F5R2_FB2_Msk /*!< Filter bit 2 */
+#define CAN_F5R2_FB3_Pos (3U)
+#define CAN_F5R2_FB3_Msk (0x1U << CAN_F5R2_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F5R2_FB3 CAN_F5R2_FB3_Msk /*!< Filter bit 3 */
+#define CAN_F5R2_FB4_Pos (4U)
+#define CAN_F5R2_FB4_Msk (0x1U << CAN_F5R2_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F5R2_FB4 CAN_F5R2_FB4_Msk /*!< Filter bit 4 */
+#define CAN_F5R2_FB5_Pos (5U)
+#define CAN_F5R2_FB5_Msk (0x1U << CAN_F5R2_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F5R2_FB5 CAN_F5R2_FB5_Msk /*!< Filter bit 5 */
+#define CAN_F5R2_FB6_Pos (6U)
+#define CAN_F5R2_FB6_Msk (0x1U << CAN_F5R2_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F5R2_FB6 CAN_F5R2_FB6_Msk /*!< Filter bit 6 */
+#define CAN_F5R2_FB7_Pos (7U)
+#define CAN_F5R2_FB7_Msk (0x1U << CAN_F5R2_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F5R2_FB7 CAN_F5R2_FB7_Msk /*!< Filter bit 7 */
+#define CAN_F5R2_FB8_Pos (8U)
+#define CAN_F5R2_FB8_Msk (0x1U << CAN_F5R2_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F5R2_FB8 CAN_F5R2_FB8_Msk /*!< Filter bit 8 */
+#define CAN_F5R2_FB9_Pos (9U)
+#define CAN_F5R2_FB9_Msk (0x1U << CAN_F5R2_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F5R2_FB9 CAN_F5R2_FB9_Msk /*!< Filter bit 9 */
+#define CAN_F5R2_FB10_Pos (10U)
+#define CAN_F5R2_FB10_Msk (0x1U << CAN_F5R2_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F5R2_FB10 CAN_F5R2_FB10_Msk /*!< Filter bit 10 */
+#define CAN_F5R2_FB11_Pos (11U)
+#define CAN_F5R2_FB11_Msk (0x1U << CAN_F5R2_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F5R2_FB11 CAN_F5R2_FB11_Msk /*!< Filter bit 11 */
+#define CAN_F5R2_FB12_Pos (12U)
+#define CAN_F5R2_FB12_Msk (0x1U << CAN_F5R2_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F5R2_FB12 CAN_F5R2_FB12_Msk /*!< Filter bit 12 */
+#define CAN_F5R2_FB13_Pos (13U)
+#define CAN_F5R2_FB13_Msk (0x1U << CAN_F5R2_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F5R2_FB13 CAN_F5R2_FB13_Msk /*!< Filter bit 13 */
+#define CAN_F5R2_FB14_Pos (14U)
+#define CAN_F5R2_FB14_Msk (0x1U << CAN_F5R2_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F5R2_FB14 CAN_F5R2_FB14_Msk /*!< Filter bit 14 */
+#define CAN_F5R2_FB15_Pos (15U)
+#define CAN_F5R2_FB15_Msk (0x1U << CAN_F5R2_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F5R2_FB15 CAN_F5R2_FB15_Msk /*!< Filter bit 15 */
+#define CAN_F5R2_FB16_Pos (16U)
+#define CAN_F5R2_FB16_Msk (0x1U << CAN_F5R2_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F5R2_FB16 CAN_F5R2_FB16_Msk /*!< Filter bit 16 */
+#define CAN_F5R2_FB17_Pos (17U)
+#define CAN_F5R2_FB17_Msk (0x1U << CAN_F5R2_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F5R2_FB17 CAN_F5R2_FB17_Msk /*!< Filter bit 17 */
+#define CAN_F5R2_FB18_Pos (18U)
+#define CAN_F5R2_FB18_Msk (0x1U << CAN_F5R2_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F5R2_FB18 CAN_F5R2_FB18_Msk /*!< Filter bit 18 */
+#define CAN_F5R2_FB19_Pos (19U)
+#define CAN_F5R2_FB19_Msk (0x1U << CAN_F5R2_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F5R2_FB19 CAN_F5R2_FB19_Msk /*!< Filter bit 19 */
+#define CAN_F5R2_FB20_Pos (20U)
+#define CAN_F5R2_FB20_Msk (0x1U << CAN_F5R2_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F5R2_FB20 CAN_F5R2_FB20_Msk /*!< Filter bit 20 */
+#define CAN_F5R2_FB21_Pos (21U)
+#define CAN_F5R2_FB21_Msk (0x1U << CAN_F5R2_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F5R2_FB21 CAN_F5R2_FB21_Msk /*!< Filter bit 21 */
+#define CAN_F5R2_FB22_Pos (22U)
+#define CAN_F5R2_FB22_Msk (0x1U << CAN_F5R2_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F5R2_FB22 CAN_F5R2_FB22_Msk /*!< Filter bit 22 */
+#define CAN_F5R2_FB23_Pos (23U)
+#define CAN_F5R2_FB23_Msk (0x1U << CAN_F5R2_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F5R2_FB23 CAN_F5R2_FB23_Msk /*!< Filter bit 23 */
+#define CAN_F5R2_FB24_Pos (24U)
+#define CAN_F5R2_FB24_Msk (0x1U << CAN_F5R2_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F5R2_FB24 CAN_F5R2_FB24_Msk /*!< Filter bit 24 */
+#define CAN_F5R2_FB25_Pos (25U)
+#define CAN_F5R2_FB25_Msk (0x1U << CAN_F5R2_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F5R2_FB25 CAN_F5R2_FB25_Msk /*!< Filter bit 25 */
+#define CAN_F5R2_FB26_Pos (26U)
+#define CAN_F5R2_FB26_Msk (0x1U << CAN_F5R2_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F5R2_FB26 CAN_F5R2_FB26_Msk /*!< Filter bit 26 */
+#define CAN_F5R2_FB27_Pos (27U)
+#define CAN_F5R2_FB27_Msk (0x1U << CAN_F5R2_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F5R2_FB27 CAN_F5R2_FB27_Msk /*!< Filter bit 27 */
+#define CAN_F5R2_FB28_Pos (28U)
+#define CAN_F5R2_FB28_Msk (0x1U << CAN_F5R2_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F5R2_FB28 CAN_F5R2_FB28_Msk /*!< Filter bit 28 */
+#define CAN_F5R2_FB29_Pos (29U)
+#define CAN_F5R2_FB29_Msk (0x1U << CAN_F5R2_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F5R2_FB29 CAN_F5R2_FB29_Msk /*!< Filter bit 29 */
+#define CAN_F5R2_FB30_Pos (30U)
+#define CAN_F5R2_FB30_Msk (0x1U << CAN_F5R2_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F5R2_FB30 CAN_F5R2_FB30_Msk /*!< Filter bit 30 */
+#define CAN_F5R2_FB31_Pos (31U)
+#define CAN_F5R2_FB31_Msk (0x1U << CAN_F5R2_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F5R2_FB31 CAN_F5R2_FB31_Msk /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F6R2 register *******************/
+#define CAN_F6R2_FB0_Pos (0U)
+#define CAN_F6R2_FB0_Msk (0x1U << CAN_F6R2_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F6R2_FB0 CAN_F6R2_FB0_Msk /*!< Filter bit 0 */
+#define CAN_F6R2_FB1_Pos (1U)
+#define CAN_F6R2_FB1_Msk (0x1U << CAN_F6R2_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F6R2_FB1 CAN_F6R2_FB1_Msk /*!< Filter bit 1 */
+#define CAN_F6R2_FB2_Pos (2U)
+#define CAN_F6R2_FB2_Msk (0x1U << CAN_F6R2_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F6R2_FB2 CAN_F6R2_FB2_Msk /*!< Filter bit 2 */
+#define CAN_F6R2_FB3_Pos (3U)
+#define CAN_F6R2_FB3_Msk (0x1U << CAN_F6R2_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F6R2_FB3 CAN_F6R2_FB3_Msk /*!< Filter bit 3 */
+#define CAN_F6R2_FB4_Pos (4U)
+#define CAN_F6R2_FB4_Msk (0x1U << CAN_F6R2_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F6R2_FB4 CAN_F6R2_FB4_Msk /*!< Filter bit 4 */
+#define CAN_F6R2_FB5_Pos (5U)
+#define CAN_F6R2_FB5_Msk (0x1U << CAN_F6R2_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F6R2_FB5 CAN_F6R2_FB5_Msk /*!< Filter bit 5 */
+#define CAN_F6R2_FB6_Pos (6U)
+#define CAN_F6R2_FB6_Msk (0x1U << CAN_F6R2_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F6R2_FB6 CAN_F6R2_FB6_Msk /*!< Filter bit 6 */
+#define CAN_F6R2_FB7_Pos (7U)
+#define CAN_F6R2_FB7_Msk (0x1U << CAN_F6R2_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F6R2_FB7 CAN_F6R2_FB7_Msk /*!< Filter bit 7 */
+#define CAN_F6R2_FB8_Pos (8U)
+#define CAN_F6R2_FB8_Msk (0x1U << CAN_F6R2_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F6R2_FB8 CAN_F6R2_FB8_Msk /*!< Filter bit 8 */
+#define CAN_F6R2_FB9_Pos (9U)
+#define CAN_F6R2_FB9_Msk (0x1U << CAN_F6R2_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F6R2_FB9 CAN_F6R2_FB9_Msk /*!< Filter bit 9 */
+#define CAN_F6R2_FB10_Pos (10U)
+#define CAN_F6R2_FB10_Msk (0x1U << CAN_F6R2_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F6R2_FB10 CAN_F6R2_FB10_Msk /*!< Filter bit 10 */
+#define CAN_F6R2_FB11_Pos (11U)
+#define CAN_F6R2_FB11_Msk (0x1U << CAN_F6R2_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F6R2_FB11 CAN_F6R2_FB11_Msk /*!< Filter bit 11 */
+#define CAN_F6R2_FB12_Pos (12U)
+#define CAN_F6R2_FB12_Msk (0x1U << CAN_F6R2_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F6R2_FB12 CAN_F6R2_FB12_Msk /*!< Filter bit 12 */
+#define CAN_F6R2_FB13_Pos (13U)
+#define CAN_F6R2_FB13_Msk (0x1U << CAN_F6R2_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F6R2_FB13 CAN_F6R2_FB13_Msk /*!< Filter bit 13 */
+#define CAN_F6R2_FB14_Pos (14U)
+#define CAN_F6R2_FB14_Msk (0x1U << CAN_F6R2_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F6R2_FB14 CAN_F6R2_FB14_Msk /*!< Filter bit 14 */
+#define CAN_F6R2_FB15_Pos (15U)
+#define CAN_F6R2_FB15_Msk (0x1U << CAN_F6R2_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F6R2_FB15 CAN_F6R2_FB15_Msk /*!< Filter bit 15 */
+#define CAN_F6R2_FB16_Pos (16U)
+#define CAN_F6R2_FB16_Msk (0x1U << CAN_F6R2_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F6R2_FB16 CAN_F6R2_FB16_Msk /*!< Filter bit 16 */
+#define CAN_F6R2_FB17_Pos (17U)
+#define CAN_F6R2_FB17_Msk (0x1U << CAN_F6R2_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F6R2_FB17 CAN_F6R2_FB17_Msk /*!< Filter bit 17 */
+#define CAN_F6R2_FB18_Pos (18U)
+#define CAN_F6R2_FB18_Msk (0x1U << CAN_F6R2_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F6R2_FB18 CAN_F6R2_FB18_Msk /*!< Filter bit 18 */
+#define CAN_F6R2_FB19_Pos (19U)
+#define CAN_F6R2_FB19_Msk (0x1U << CAN_F6R2_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F6R2_FB19 CAN_F6R2_FB19_Msk /*!< Filter bit 19 */
+#define CAN_F6R2_FB20_Pos (20U)
+#define CAN_F6R2_FB20_Msk (0x1U << CAN_F6R2_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F6R2_FB20 CAN_F6R2_FB20_Msk /*!< Filter bit 20 */
+#define CAN_F6R2_FB21_Pos (21U)
+#define CAN_F6R2_FB21_Msk (0x1U << CAN_F6R2_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F6R2_FB21 CAN_F6R2_FB21_Msk /*!< Filter bit 21 */
+#define CAN_F6R2_FB22_Pos (22U)
+#define CAN_F6R2_FB22_Msk (0x1U << CAN_F6R2_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F6R2_FB22 CAN_F6R2_FB22_Msk /*!< Filter bit 22 */
+#define CAN_F6R2_FB23_Pos (23U)
+#define CAN_F6R2_FB23_Msk (0x1U << CAN_F6R2_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F6R2_FB23 CAN_F6R2_FB23_Msk /*!< Filter bit 23 */
+#define CAN_F6R2_FB24_Pos (24U)
+#define CAN_F6R2_FB24_Msk (0x1U << CAN_F6R2_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F6R2_FB24 CAN_F6R2_FB24_Msk /*!< Filter bit 24 */
+#define CAN_F6R2_FB25_Pos (25U)
+#define CAN_F6R2_FB25_Msk (0x1U << CAN_F6R2_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F6R2_FB25 CAN_F6R2_FB25_Msk /*!< Filter bit 25 */
+#define CAN_F6R2_FB26_Pos (26U)
+#define CAN_F6R2_FB26_Msk (0x1U << CAN_F6R2_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F6R2_FB26 CAN_F6R2_FB26_Msk /*!< Filter bit 26 */
+#define CAN_F6R2_FB27_Pos (27U)
+#define CAN_F6R2_FB27_Msk (0x1U << CAN_F6R2_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F6R2_FB27 CAN_F6R2_FB27_Msk /*!< Filter bit 27 */
+#define CAN_F6R2_FB28_Pos (28U)
+#define CAN_F6R2_FB28_Msk (0x1U << CAN_F6R2_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F6R2_FB28 CAN_F6R2_FB28_Msk /*!< Filter bit 28 */
+#define CAN_F6R2_FB29_Pos (29U)
+#define CAN_F6R2_FB29_Msk (0x1U << CAN_F6R2_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F6R2_FB29 CAN_F6R2_FB29_Msk /*!< Filter bit 29 */
+#define CAN_F6R2_FB30_Pos (30U)
+#define CAN_F6R2_FB30_Msk (0x1U << CAN_F6R2_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F6R2_FB30 CAN_F6R2_FB30_Msk /*!< Filter bit 30 */
+#define CAN_F6R2_FB31_Pos (31U)
+#define CAN_F6R2_FB31_Msk (0x1U << CAN_F6R2_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F6R2_FB31 CAN_F6R2_FB31_Msk /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F7R2 register *******************/
+#define CAN_F7R2_FB0_Pos (0U)
+#define CAN_F7R2_FB0_Msk (0x1U << CAN_F7R2_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F7R2_FB0 CAN_F7R2_FB0_Msk /*!< Filter bit 0 */
+#define CAN_F7R2_FB1_Pos (1U)
+#define CAN_F7R2_FB1_Msk (0x1U << CAN_F7R2_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F7R2_FB1 CAN_F7R2_FB1_Msk /*!< Filter bit 1 */
+#define CAN_F7R2_FB2_Pos (2U)
+#define CAN_F7R2_FB2_Msk (0x1U << CAN_F7R2_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F7R2_FB2 CAN_F7R2_FB2_Msk /*!< Filter bit 2 */
+#define CAN_F7R2_FB3_Pos (3U)
+#define CAN_F7R2_FB3_Msk (0x1U << CAN_F7R2_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F7R2_FB3 CAN_F7R2_FB3_Msk /*!< Filter bit 3 */
+#define CAN_F7R2_FB4_Pos (4U)
+#define CAN_F7R2_FB4_Msk (0x1U << CAN_F7R2_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F7R2_FB4 CAN_F7R2_FB4_Msk /*!< Filter bit 4 */
+#define CAN_F7R2_FB5_Pos (5U)
+#define CAN_F7R2_FB5_Msk (0x1U << CAN_F7R2_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F7R2_FB5 CAN_F7R2_FB5_Msk /*!< Filter bit 5 */
+#define CAN_F7R2_FB6_Pos (6U)
+#define CAN_F7R2_FB6_Msk (0x1U << CAN_F7R2_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F7R2_FB6 CAN_F7R2_FB6_Msk /*!< Filter bit 6 */
+#define CAN_F7R2_FB7_Pos (7U)
+#define CAN_F7R2_FB7_Msk (0x1U << CAN_F7R2_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F7R2_FB7 CAN_F7R2_FB7_Msk /*!< Filter bit 7 */
+#define CAN_F7R2_FB8_Pos (8U)
+#define CAN_F7R2_FB8_Msk (0x1U << CAN_F7R2_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F7R2_FB8 CAN_F7R2_FB8_Msk /*!< Filter bit 8 */
+#define CAN_F7R2_FB9_Pos (9U)
+#define CAN_F7R2_FB9_Msk (0x1U << CAN_F7R2_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F7R2_FB9 CAN_F7R2_FB9_Msk /*!< Filter bit 9 */
+#define CAN_F7R2_FB10_Pos (10U)
+#define CAN_F7R2_FB10_Msk (0x1U << CAN_F7R2_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F7R2_FB10 CAN_F7R2_FB10_Msk /*!< Filter bit 10 */
+#define CAN_F7R2_FB11_Pos (11U)
+#define CAN_F7R2_FB11_Msk (0x1U << CAN_F7R2_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F7R2_FB11 CAN_F7R2_FB11_Msk /*!< Filter bit 11 */
+#define CAN_F7R2_FB12_Pos (12U)
+#define CAN_F7R2_FB12_Msk (0x1U << CAN_F7R2_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F7R2_FB12 CAN_F7R2_FB12_Msk /*!< Filter bit 12 */
+#define CAN_F7R2_FB13_Pos (13U)
+#define CAN_F7R2_FB13_Msk (0x1U << CAN_F7R2_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F7R2_FB13 CAN_F7R2_FB13_Msk /*!< Filter bit 13 */
+#define CAN_F7R2_FB14_Pos (14U)
+#define CAN_F7R2_FB14_Msk (0x1U << CAN_F7R2_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F7R2_FB14 CAN_F7R2_FB14_Msk /*!< Filter bit 14 */
+#define CAN_F7R2_FB15_Pos (15U)
+#define CAN_F7R2_FB15_Msk (0x1U << CAN_F7R2_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F7R2_FB15 CAN_F7R2_FB15_Msk /*!< Filter bit 15 */
+#define CAN_F7R2_FB16_Pos (16U)
+#define CAN_F7R2_FB16_Msk (0x1U << CAN_F7R2_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F7R2_FB16 CAN_F7R2_FB16_Msk /*!< Filter bit 16 */
+#define CAN_F7R2_FB17_Pos (17U)
+#define CAN_F7R2_FB17_Msk (0x1U << CAN_F7R2_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F7R2_FB17 CAN_F7R2_FB17_Msk /*!< Filter bit 17 */
+#define CAN_F7R2_FB18_Pos (18U)
+#define CAN_F7R2_FB18_Msk (0x1U << CAN_F7R2_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F7R2_FB18 CAN_F7R2_FB18_Msk /*!< Filter bit 18 */
+#define CAN_F7R2_FB19_Pos (19U)
+#define CAN_F7R2_FB19_Msk (0x1U << CAN_F7R2_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F7R2_FB19 CAN_F7R2_FB19_Msk /*!< Filter bit 19 */
+#define CAN_F7R2_FB20_Pos (20U)
+#define CAN_F7R2_FB20_Msk (0x1U << CAN_F7R2_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F7R2_FB20 CAN_F7R2_FB20_Msk /*!< Filter bit 20 */
+#define CAN_F7R2_FB21_Pos (21U)
+#define CAN_F7R2_FB21_Msk (0x1U << CAN_F7R2_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F7R2_FB21 CAN_F7R2_FB21_Msk /*!< Filter bit 21 */
+#define CAN_F7R2_FB22_Pos (22U)
+#define CAN_F7R2_FB22_Msk (0x1U << CAN_F7R2_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F7R2_FB22 CAN_F7R2_FB22_Msk /*!< Filter bit 22 */
+#define CAN_F7R2_FB23_Pos (23U)
+#define CAN_F7R2_FB23_Msk (0x1U << CAN_F7R2_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F7R2_FB23 CAN_F7R2_FB23_Msk /*!< Filter bit 23 */
+#define CAN_F7R2_FB24_Pos (24U)
+#define CAN_F7R2_FB24_Msk (0x1U << CAN_F7R2_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F7R2_FB24 CAN_F7R2_FB24_Msk /*!< Filter bit 24 */
+#define CAN_F7R2_FB25_Pos (25U)
+#define CAN_F7R2_FB25_Msk (0x1U << CAN_F7R2_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F7R2_FB25 CAN_F7R2_FB25_Msk /*!< Filter bit 25 */
+#define CAN_F7R2_FB26_Pos (26U)
+#define CAN_F7R2_FB26_Msk (0x1U << CAN_F7R2_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F7R2_FB26 CAN_F7R2_FB26_Msk /*!< Filter bit 26 */
+#define CAN_F7R2_FB27_Pos (27U)
+#define CAN_F7R2_FB27_Msk (0x1U << CAN_F7R2_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F7R2_FB27 CAN_F7R2_FB27_Msk /*!< Filter bit 27 */
+#define CAN_F7R2_FB28_Pos (28U)
+#define CAN_F7R2_FB28_Msk (0x1U << CAN_F7R2_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F7R2_FB28 CAN_F7R2_FB28_Msk /*!< Filter bit 28 */
+#define CAN_F7R2_FB29_Pos (29U)
+#define CAN_F7R2_FB29_Msk (0x1U << CAN_F7R2_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F7R2_FB29 CAN_F7R2_FB29_Msk /*!< Filter bit 29 */
+#define CAN_F7R2_FB30_Pos (30U)
+#define CAN_F7R2_FB30_Msk (0x1U << CAN_F7R2_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F7R2_FB30 CAN_F7R2_FB30_Msk /*!< Filter bit 30 */
+#define CAN_F7R2_FB31_Pos (31U)
+#define CAN_F7R2_FB31_Msk (0x1U << CAN_F7R2_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F7R2_FB31 CAN_F7R2_FB31_Msk /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F8R2 register *******************/
+#define CAN_F8R2_FB0_Pos (0U)
+#define CAN_F8R2_FB0_Msk (0x1U << CAN_F8R2_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F8R2_FB0 CAN_F8R2_FB0_Msk /*!< Filter bit 0 */
+#define CAN_F8R2_FB1_Pos (1U)
+#define CAN_F8R2_FB1_Msk (0x1U << CAN_F8R2_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F8R2_FB1 CAN_F8R2_FB1_Msk /*!< Filter bit 1 */
+#define CAN_F8R2_FB2_Pos (2U)
+#define CAN_F8R2_FB2_Msk (0x1U << CAN_F8R2_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F8R2_FB2 CAN_F8R2_FB2_Msk /*!< Filter bit 2 */
+#define CAN_F8R2_FB3_Pos (3U)
+#define CAN_F8R2_FB3_Msk (0x1U << CAN_F8R2_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F8R2_FB3 CAN_F8R2_FB3_Msk /*!< Filter bit 3 */
+#define CAN_F8R2_FB4_Pos (4U)
+#define CAN_F8R2_FB4_Msk (0x1U << CAN_F8R2_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F8R2_FB4 CAN_F8R2_FB4_Msk /*!< Filter bit 4 */
+#define CAN_F8R2_FB5_Pos (5U)
+#define CAN_F8R2_FB5_Msk (0x1U << CAN_F8R2_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F8R2_FB5 CAN_F8R2_FB5_Msk /*!< Filter bit 5 */
+#define CAN_F8R2_FB6_Pos (6U)
+#define CAN_F8R2_FB6_Msk (0x1U << CAN_F8R2_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F8R2_FB6 CAN_F8R2_FB6_Msk /*!< Filter bit 6 */
+#define CAN_F8R2_FB7_Pos (7U)
+#define CAN_F8R2_FB7_Msk (0x1U << CAN_F8R2_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F8R2_FB7 CAN_F8R2_FB7_Msk /*!< Filter bit 7 */
+#define CAN_F8R2_FB8_Pos (8U)
+#define CAN_F8R2_FB8_Msk (0x1U << CAN_F8R2_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F8R2_FB8 CAN_F8R2_FB8_Msk /*!< Filter bit 8 */
+#define CAN_F8R2_FB9_Pos (9U)
+#define CAN_F8R2_FB9_Msk (0x1U << CAN_F8R2_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F8R2_FB9 CAN_F8R2_FB9_Msk /*!< Filter bit 9 */
+#define CAN_F8R2_FB10_Pos (10U)
+#define CAN_F8R2_FB10_Msk (0x1U << CAN_F8R2_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F8R2_FB10 CAN_F8R2_FB10_Msk /*!< Filter bit 10 */
+#define CAN_F8R2_FB11_Pos (11U)
+#define CAN_F8R2_FB11_Msk (0x1U << CAN_F8R2_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F8R2_FB11 CAN_F8R2_FB11_Msk /*!< Filter bit 11 */
+#define CAN_F8R2_FB12_Pos (12U)
+#define CAN_F8R2_FB12_Msk (0x1U << CAN_F8R2_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F8R2_FB12 CAN_F8R2_FB12_Msk /*!< Filter bit 12 */
+#define CAN_F8R2_FB13_Pos (13U)
+#define CAN_F8R2_FB13_Msk (0x1U << CAN_F8R2_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F8R2_FB13 CAN_F8R2_FB13_Msk /*!< Filter bit 13 */
+#define CAN_F8R2_FB14_Pos (14U)
+#define CAN_F8R2_FB14_Msk (0x1U << CAN_F8R2_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F8R2_FB14 CAN_F8R2_FB14_Msk /*!< Filter bit 14 */
+#define CAN_F8R2_FB15_Pos (15U)
+#define CAN_F8R2_FB15_Msk (0x1U << CAN_F8R2_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F8R2_FB15 CAN_F8R2_FB15_Msk /*!< Filter bit 15 */
+#define CAN_F8R2_FB16_Pos (16U)
+#define CAN_F8R2_FB16_Msk (0x1U << CAN_F8R2_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F8R2_FB16 CAN_F8R2_FB16_Msk /*!< Filter bit 16 */
+#define CAN_F8R2_FB17_Pos (17U)
+#define CAN_F8R2_FB17_Msk (0x1U << CAN_F8R2_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F8R2_FB17 CAN_F8R2_FB17_Msk /*!< Filter bit 17 */
+#define CAN_F8R2_FB18_Pos (18U)
+#define CAN_F8R2_FB18_Msk (0x1U << CAN_F8R2_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F8R2_FB18 CAN_F8R2_FB18_Msk /*!< Filter bit 18 */
+#define CAN_F8R2_FB19_Pos (19U)
+#define CAN_F8R2_FB19_Msk (0x1U << CAN_F8R2_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F8R2_FB19 CAN_F8R2_FB19_Msk /*!< Filter bit 19 */
+#define CAN_F8R2_FB20_Pos (20U)
+#define CAN_F8R2_FB20_Msk (0x1U << CAN_F8R2_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F8R2_FB20 CAN_F8R2_FB20_Msk /*!< Filter bit 20 */
+#define CAN_F8R2_FB21_Pos (21U)
+#define CAN_F8R2_FB21_Msk (0x1U << CAN_F8R2_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F8R2_FB21 CAN_F8R2_FB21_Msk /*!< Filter bit 21 */
+#define CAN_F8R2_FB22_Pos (22U)
+#define CAN_F8R2_FB22_Msk (0x1U << CAN_F8R2_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F8R2_FB22 CAN_F8R2_FB22_Msk /*!< Filter bit 22 */
+#define CAN_F8R2_FB23_Pos (23U)
+#define CAN_F8R2_FB23_Msk (0x1U << CAN_F8R2_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F8R2_FB23 CAN_F8R2_FB23_Msk /*!< Filter bit 23 */
+#define CAN_F8R2_FB24_Pos (24U)
+#define CAN_F8R2_FB24_Msk (0x1U << CAN_F8R2_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F8R2_FB24 CAN_F8R2_FB24_Msk /*!< Filter bit 24 */
+#define CAN_F8R2_FB25_Pos (25U)
+#define CAN_F8R2_FB25_Msk (0x1U << CAN_F8R2_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F8R2_FB25 CAN_F8R2_FB25_Msk /*!< Filter bit 25 */
+#define CAN_F8R2_FB26_Pos (26U)
+#define CAN_F8R2_FB26_Msk (0x1U << CAN_F8R2_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F8R2_FB26 CAN_F8R2_FB26_Msk /*!< Filter bit 26 */
+#define CAN_F8R2_FB27_Pos (27U)
+#define CAN_F8R2_FB27_Msk (0x1U << CAN_F8R2_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F8R2_FB27 CAN_F8R2_FB27_Msk /*!< Filter bit 27 */
+#define CAN_F8R2_FB28_Pos (28U)
+#define CAN_F8R2_FB28_Msk (0x1U << CAN_F8R2_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F8R2_FB28 CAN_F8R2_FB28_Msk /*!< Filter bit 28 */
+#define CAN_F8R2_FB29_Pos (29U)
+#define CAN_F8R2_FB29_Msk (0x1U << CAN_F8R2_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F8R2_FB29 CAN_F8R2_FB29_Msk /*!< Filter bit 29 */
+#define CAN_F8R2_FB30_Pos (30U)
+#define CAN_F8R2_FB30_Msk (0x1U << CAN_F8R2_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F8R2_FB30 CAN_F8R2_FB30_Msk /*!< Filter bit 30 */
+#define CAN_F8R2_FB31_Pos (31U)
+#define CAN_F8R2_FB31_Msk (0x1U << CAN_F8R2_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F8R2_FB31 CAN_F8R2_FB31_Msk /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F9R2 register *******************/
+#define CAN_F9R2_FB0_Pos (0U)
+#define CAN_F9R2_FB0_Msk (0x1U << CAN_F9R2_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F9R2_FB0 CAN_F9R2_FB0_Msk /*!< Filter bit 0 */
+#define CAN_F9R2_FB1_Pos (1U)
+#define CAN_F9R2_FB1_Msk (0x1U << CAN_F9R2_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F9R2_FB1 CAN_F9R2_FB1_Msk /*!< Filter bit 1 */
+#define CAN_F9R2_FB2_Pos (2U)
+#define CAN_F9R2_FB2_Msk (0x1U << CAN_F9R2_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F9R2_FB2 CAN_F9R2_FB2_Msk /*!< Filter bit 2 */
+#define CAN_F9R2_FB3_Pos (3U)
+#define CAN_F9R2_FB3_Msk (0x1U << CAN_F9R2_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F9R2_FB3 CAN_F9R2_FB3_Msk /*!< Filter bit 3 */
+#define CAN_F9R2_FB4_Pos (4U)
+#define CAN_F9R2_FB4_Msk (0x1U << CAN_F9R2_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F9R2_FB4 CAN_F9R2_FB4_Msk /*!< Filter bit 4 */
+#define CAN_F9R2_FB5_Pos (5U)
+#define CAN_F9R2_FB5_Msk (0x1U << CAN_F9R2_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F9R2_FB5 CAN_F9R2_FB5_Msk /*!< Filter bit 5 */
+#define CAN_F9R2_FB6_Pos (6U)
+#define CAN_F9R2_FB6_Msk (0x1U << CAN_F9R2_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F9R2_FB6 CAN_F9R2_FB6_Msk /*!< Filter bit 6 */
+#define CAN_F9R2_FB7_Pos (7U)
+#define CAN_F9R2_FB7_Msk (0x1U << CAN_F9R2_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F9R2_FB7 CAN_F9R2_FB7_Msk /*!< Filter bit 7 */
+#define CAN_F9R2_FB8_Pos (8U)
+#define CAN_F9R2_FB8_Msk (0x1U << CAN_F9R2_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F9R2_FB8 CAN_F9R2_FB8_Msk /*!< Filter bit 8 */
+#define CAN_F9R2_FB9_Pos (9U)
+#define CAN_F9R2_FB9_Msk (0x1U << CAN_F9R2_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F9R2_FB9 CAN_F9R2_FB9_Msk /*!< Filter bit 9 */
+#define CAN_F9R2_FB10_Pos (10U)
+#define CAN_F9R2_FB10_Msk (0x1U << CAN_F9R2_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F9R2_FB10 CAN_F9R2_FB10_Msk /*!< Filter bit 10 */
+#define CAN_F9R2_FB11_Pos (11U)
+#define CAN_F9R2_FB11_Msk (0x1U << CAN_F9R2_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F9R2_FB11 CAN_F9R2_FB11_Msk /*!< Filter bit 11 */
+#define CAN_F9R2_FB12_Pos (12U)
+#define CAN_F9R2_FB12_Msk (0x1U << CAN_F9R2_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F9R2_FB12 CAN_F9R2_FB12_Msk /*!< Filter bit 12 */
+#define CAN_F9R2_FB13_Pos (13U)
+#define CAN_F9R2_FB13_Msk (0x1U << CAN_F9R2_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F9R2_FB13 CAN_F9R2_FB13_Msk /*!< Filter bit 13 */
+#define CAN_F9R2_FB14_Pos (14U)
+#define CAN_F9R2_FB14_Msk (0x1U << CAN_F9R2_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F9R2_FB14 CAN_F9R2_FB14_Msk /*!< Filter bit 14 */
+#define CAN_F9R2_FB15_Pos (15U)
+#define CAN_F9R2_FB15_Msk (0x1U << CAN_F9R2_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F9R2_FB15 CAN_F9R2_FB15_Msk /*!< Filter bit 15 */
+#define CAN_F9R2_FB16_Pos (16U)
+#define CAN_F9R2_FB16_Msk (0x1U << CAN_F9R2_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F9R2_FB16 CAN_F9R2_FB16_Msk /*!< Filter bit 16 */
+#define CAN_F9R2_FB17_Pos (17U)
+#define CAN_F9R2_FB17_Msk (0x1U << CAN_F9R2_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F9R2_FB17 CAN_F9R2_FB17_Msk /*!< Filter bit 17 */
+#define CAN_F9R2_FB18_Pos (18U)
+#define CAN_F9R2_FB18_Msk (0x1U << CAN_F9R2_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F9R2_FB18 CAN_F9R2_FB18_Msk /*!< Filter bit 18 */
+#define CAN_F9R2_FB19_Pos (19U)
+#define CAN_F9R2_FB19_Msk (0x1U << CAN_F9R2_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F9R2_FB19 CAN_F9R2_FB19_Msk /*!< Filter bit 19 */
+#define CAN_F9R2_FB20_Pos (20U)
+#define CAN_F9R2_FB20_Msk (0x1U << CAN_F9R2_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F9R2_FB20 CAN_F9R2_FB20_Msk /*!< Filter bit 20 */
+#define CAN_F9R2_FB21_Pos (21U)
+#define CAN_F9R2_FB21_Msk (0x1U << CAN_F9R2_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F9R2_FB21 CAN_F9R2_FB21_Msk /*!< Filter bit 21 */
+#define CAN_F9R2_FB22_Pos (22U)
+#define CAN_F9R2_FB22_Msk (0x1U << CAN_F9R2_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F9R2_FB22 CAN_F9R2_FB22_Msk /*!< Filter bit 22 */
+#define CAN_F9R2_FB23_Pos (23U)
+#define CAN_F9R2_FB23_Msk (0x1U << CAN_F9R2_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F9R2_FB23 CAN_F9R2_FB23_Msk /*!< Filter bit 23 */
+#define CAN_F9R2_FB24_Pos (24U)
+#define CAN_F9R2_FB24_Msk (0x1U << CAN_F9R2_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F9R2_FB24 CAN_F9R2_FB24_Msk /*!< Filter bit 24 */
+#define CAN_F9R2_FB25_Pos (25U)
+#define CAN_F9R2_FB25_Msk (0x1U << CAN_F9R2_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F9R2_FB25 CAN_F9R2_FB25_Msk /*!< Filter bit 25 */
+#define CAN_F9R2_FB26_Pos (26U)
+#define CAN_F9R2_FB26_Msk (0x1U << CAN_F9R2_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F9R2_FB26 CAN_F9R2_FB26_Msk /*!< Filter bit 26 */
+#define CAN_F9R2_FB27_Pos (27U)
+#define CAN_F9R2_FB27_Msk (0x1U << CAN_F9R2_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F9R2_FB27 CAN_F9R2_FB27_Msk /*!< Filter bit 27 */
+#define CAN_F9R2_FB28_Pos (28U)
+#define CAN_F9R2_FB28_Msk (0x1U << CAN_F9R2_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F9R2_FB28 CAN_F9R2_FB28_Msk /*!< Filter bit 28 */
+#define CAN_F9R2_FB29_Pos (29U)
+#define CAN_F9R2_FB29_Msk (0x1U << CAN_F9R2_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F9R2_FB29 CAN_F9R2_FB29_Msk /*!< Filter bit 29 */
+#define CAN_F9R2_FB30_Pos (30U)
+#define CAN_F9R2_FB30_Msk (0x1U << CAN_F9R2_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F9R2_FB30 CAN_F9R2_FB30_Msk /*!< Filter bit 30 */
+#define CAN_F9R2_FB31_Pos (31U)
+#define CAN_F9R2_FB31_Msk (0x1U << CAN_F9R2_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F9R2_FB31 CAN_F9R2_FB31_Msk /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F10R2 register ******************/
+#define CAN_F10R2_FB0_Pos (0U)
+#define CAN_F10R2_FB0_Msk (0x1U << CAN_F10R2_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F10R2_FB0 CAN_F10R2_FB0_Msk /*!< Filter bit 0 */
+#define CAN_F10R2_FB1_Pos (1U)
+#define CAN_F10R2_FB1_Msk (0x1U << CAN_F10R2_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F10R2_FB1 CAN_F10R2_FB1_Msk /*!< Filter bit 1 */
+#define CAN_F10R2_FB2_Pos (2U)
+#define CAN_F10R2_FB2_Msk (0x1U << CAN_F10R2_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F10R2_FB2 CAN_F10R2_FB2_Msk /*!< Filter bit 2 */
+#define CAN_F10R2_FB3_Pos (3U)
+#define CAN_F10R2_FB3_Msk (0x1U << CAN_F10R2_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F10R2_FB3 CAN_F10R2_FB3_Msk /*!< Filter bit 3 */
+#define CAN_F10R2_FB4_Pos (4U)
+#define CAN_F10R2_FB4_Msk (0x1U << CAN_F10R2_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F10R2_FB4 CAN_F10R2_FB4_Msk /*!< Filter bit 4 */
+#define CAN_F10R2_FB5_Pos (5U)
+#define CAN_F10R2_FB5_Msk (0x1U << CAN_F10R2_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F10R2_FB5 CAN_F10R2_FB5_Msk /*!< Filter bit 5 */
+#define CAN_F10R2_FB6_Pos (6U)
+#define CAN_F10R2_FB6_Msk (0x1U << CAN_F10R2_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F10R2_FB6 CAN_F10R2_FB6_Msk /*!< Filter bit 6 */
+#define CAN_F10R2_FB7_Pos (7U)
+#define CAN_F10R2_FB7_Msk (0x1U << CAN_F10R2_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F10R2_FB7 CAN_F10R2_FB7_Msk /*!< Filter bit 7 */
+#define CAN_F10R2_FB8_Pos (8U)
+#define CAN_F10R2_FB8_Msk (0x1U << CAN_F10R2_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F10R2_FB8 CAN_F10R2_FB8_Msk /*!< Filter bit 8 */
+#define CAN_F10R2_FB9_Pos (9U)
+#define CAN_F10R2_FB9_Msk (0x1U << CAN_F10R2_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F10R2_FB9 CAN_F10R2_FB9_Msk /*!< Filter bit 9 */
+#define CAN_F10R2_FB10_Pos (10U)
+#define CAN_F10R2_FB10_Msk (0x1U << CAN_F10R2_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F10R2_FB10 CAN_F10R2_FB10_Msk /*!< Filter bit 10 */
+#define CAN_F10R2_FB11_Pos (11U)
+#define CAN_F10R2_FB11_Msk (0x1U << CAN_F10R2_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F10R2_FB11 CAN_F10R2_FB11_Msk /*!< Filter bit 11 */
+#define CAN_F10R2_FB12_Pos (12U)
+#define CAN_F10R2_FB12_Msk (0x1U << CAN_F10R2_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F10R2_FB12 CAN_F10R2_FB12_Msk /*!< Filter bit 12 */
+#define CAN_F10R2_FB13_Pos (13U)
+#define CAN_F10R2_FB13_Msk (0x1U << CAN_F10R2_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F10R2_FB13 CAN_F10R2_FB13_Msk /*!< Filter bit 13 */
+#define CAN_F10R2_FB14_Pos (14U)
+#define CAN_F10R2_FB14_Msk (0x1U << CAN_F10R2_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F10R2_FB14 CAN_F10R2_FB14_Msk /*!< Filter bit 14 */
+#define CAN_F10R2_FB15_Pos (15U)
+#define CAN_F10R2_FB15_Msk (0x1U << CAN_F10R2_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F10R2_FB15 CAN_F10R2_FB15_Msk /*!< Filter bit 15 */
+#define CAN_F10R2_FB16_Pos (16U)
+#define CAN_F10R2_FB16_Msk (0x1U << CAN_F10R2_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F10R2_FB16 CAN_F10R2_FB16_Msk /*!< Filter bit 16 */
+#define CAN_F10R2_FB17_Pos (17U)
+#define CAN_F10R2_FB17_Msk (0x1U << CAN_F10R2_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F10R2_FB17 CAN_F10R2_FB17_Msk /*!< Filter bit 17 */
+#define CAN_F10R2_FB18_Pos (18U)
+#define CAN_F10R2_FB18_Msk (0x1U << CAN_F10R2_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F10R2_FB18 CAN_F10R2_FB18_Msk /*!< Filter bit 18 */
+#define CAN_F10R2_FB19_Pos (19U)
+#define CAN_F10R2_FB19_Msk (0x1U << CAN_F10R2_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F10R2_FB19 CAN_F10R2_FB19_Msk /*!< Filter bit 19 */
+#define CAN_F10R2_FB20_Pos (20U)
+#define CAN_F10R2_FB20_Msk (0x1U << CAN_F10R2_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F10R2_FB20 CAN_F10R2_FB20_Msk /*!< Filter bit 20 */
+#define CAN_F10R2_FB21_Pos (21U)
+#define CAN_F10R2_FB21_Msk (0x1U << CAN_F10R2_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F10R2_FB21 CAN_F10R2_FB21_Msk /*!< Filter bit 21 */
+#define CAN_F10R2_FB22_Pos (22U)
+#define CAN_F10R2_FB22_Msk (0x1U << CAN_F10R2_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F10R2_FB22 CAN_F10R2_FB22_Msk /*!< Filter bit 22 */
+#define CAN_F10R2_FB23_Pos (23U)
+#define CAN_F10R2_FB23_Msk (0x1U << CAN_F10R2_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F10R2_FB23 CAN_F10R2_FB23_Msk /*!< Filter bit 23 */
+#define CAN_F10R2_FB24_Pos (24U)
+#define CAN_F10R2_FB24_Msk (0x1U << CAN_F10R2_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F10R2_FB24 CAN_F10R2_FB24_Msk /*!< Filter bit 24 */
+#define CAN_F10R2_FB25_Pos (25U)
+#define CAN_F10R2_FB25_Msk (0x1U << CAN_F10R2_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F10R2_FB25 CAN_F10R2_FB25_Msk /*!< Filter bit 25 */
+#define CAN_F10R2_FB26_Pos (26U)
+#define CAN_F10R2_FB26_Msk (0x1U << CAN_F10R2_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F10R2_FB26 CAN_F10R2_FB26_Msk /*!< Filter bit 26 */
+#define CAN_F10R2_FB27_Pos (27U)
+#define CAN_F10R2_FB27_Msk (0x1U << CAN_F10R2_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F10R2_FB27 CAN_F10R2_FB27_Msk /*!< Filter bit 27 */
+#define CAN_F10R2_FB28_Pos (28U)
+#define CAN_F10R2_FB28_Msk (0x1U << CAN_F10R2_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F10R2_FB28 CAN_F10R2_FB28_Msk /*!< Filter bit 28 */
+#define CAN_F10R2_FB29_Pos (29U)
+#define CAN_F10R2_FB29_Msk (0x1U << CAN_F10R2_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F10R2_FB29 CAN_F10R2_FB29_Msk /*!< Filter bit 29 */
+#define CAN_F10R2_FB30_Pos (30U)
+#define CAN_F10R2_FB30_Msk (0x1U << CAN_F10R2_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F10R2_FB30 CAN_F10R2_FB30_Msk /*!< Filter bit 30 */
+#define CAN_F10R2_FB31_Pos (31U)
+#define CAN_F10R2_FB31_Msk (0x1U << CAN_F10R2_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F10R2_FB31 CAN_F10R2_FB31_Msk /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F11R2 register ******************/
+#define CAN_F11R2_FB0_Pos (0U)
+#define CAN_F11R2_FB0_Msk (0x1U << CAN_F11R2_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F11R2_FB0 CAN_F11R2_FB0_Msk /*!< Filter bit 0 */
+#define CAN_F11R2_FB1_Pos (1U)
+#define CAN_F11R2_FB1_Msk (0x1U << CAN_F11R2_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F11R2_FB1 CAN_F11R2_FB1_Msk /*!< Filter bit 1 */
+#define CAN_F11R2_FB2_Pos (2U)
+#define CAN_F11R2_FB2_Msk (0x1U << CAN_F11R2_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F11R2_FB2 CAN_F11R2_FB2_Msk /*!< Filter bit 2 */
+#define CAN_F11R2_FB3_Pos (3U)
+#define CAN_F11R2_FB3_Msk (0x1U << CAN_F11R2_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F11R2_FB3 CAN_F11R2_FB3_Msk /*!< Filter bit 3 */
+#define CAN_F11R2_FB4_Pos (4U)
+#define CAN_F11R2_FB4_Msk (0x1U << CAN_F11R2_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F11R2_FB4 CAN_F11R2_FB4_Msk /*!< Filter bit 4 */
+#define CAN_F11R2_FB5_Pos (5U)
+#define CAN_F11R2_FB5_Msk (0x1U << CAN_F11R2_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F11R2_FB5 CAN_F11R2_FB5_Msk /*!< Filter bit 5 */
+#define CAN_F11R2_FB6_Pos (6U)
+#define CAN_F11R2_FB6_Msk (0x1U << CAN_F11R2_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F11R2_FB6 CAN_F11R2_FB6_Msk /*!< Filter bit 6 */
+#define CAN_F11R2_FB7_Pos (7U)
+#define CAN_F11R2_FB7_Msk (0x1U << CAN_F11R2_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F11R2_FB7 CAN_F11R2_FB7_Msk /*!< Filter bit 7 */
+#define CAN_F11R2_FB8_Pos (8U)
+#define CAN_F11R2_FB8_Msk (0x1U << CAN_F11R2_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F11R2_FB8 CAN_F11R2_FB8_Msk /*!< Filter bit 8 */
+#define CAN_F11R2_FB9_Pos (9U)
+#define CAN_F11R2_FB9_Msk (0x1U << CAN_F11R2_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F11R2_FB9 CAN_F11R2_FB9_Msk /*!< Filter bit 9 */
+#define CAN_F11R2_FB10_Pos (10U)
+#define CAN_F11R2_FB10_Msk (0x1U << CAN_F11R2_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F11R2_FB10 CAN_F11R2_FB10_Msk /*!< Filter bit 10 */
+#define CAN_F11R2_FB11_Pos (11U)
+#define CAN_F11R2_FB11_Msk (0x1U << CAN_F11R2_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F11R2_FB11 CAN_F11R2_FB11_Msk /*!< Filter bit 11 */
+#define CAN_F11R2_FB12_Pos (12U)
+#define CAN_F11R2_FB12_Msk (0x1U << CAN_F11R2_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F11R2_FB12 CAN_F11R2_FB12_Msk /*!< Filter bit 12 */
+#define CAN_F11R2_FB13_Pos (13U)
+#define CAN_F11R2_FB13_Msk (0x1U << CAN_F11R2_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F11R2_FB13 CAN_F11R2_FB13_Msk /*!< Filter bit 13 */
+#define CAN_F11R2_FB14_Pos (14U)
+#define CAN_F11R2_FB14_Msk (0x1U << CAN_F11R2_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F11R2_FB14 CAN_F11R2_FB14_Msk /*!< Filter bit 14 */
+#define CAN_F11R2_FB15_Pos (15U)
+#define CAN_F11R2_FB15_Msk (0x1U << CAN_F11R2_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F11R2_FB15 CAN_F11R2_FB15_Msk /*!< Filter bit 15 */
+#define CAN_F11R2_FB16_Pos (16U)
+#define CAN_F11R2_FB16_Msk (0x1U << CAN_F11R2_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F11R2_FB16 CAN_F11R2_FB16_Msk /*!< Filter bit 16 */
+#define CAN_F11R2_FB17_Pos (17U)
+#define CAN_F11R2_FB17_Msk (0x1U << CAN_F11R2_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F11R2_FB17 CAN_F11R2_FB17_Msk /*!< Filter bit 17 */
+#define CAN_F11R2_FB18_Pos (18U)
+#define CAN_F11R2_FB18_Msk (0x1U << CAN_F11R2_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F11R2_FB18 CAN_F11R2_FB18_Msk /*!< Filter bit 18 */
+#define CAN_F11R2_FB19_Pos (19U)
+#define CAN_F11R2_FB19_Msk (0x1U << CAN_F11R2_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F11R2_FB19 CAN_F11R2_FB19_Msk /*!< Filter bit 19 */
+#define CAN_F11R2_FB20_Pos (20U)
+#define CAN_F11R2_FB20_Msk (0x1U << CAN_F11R2_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F11R2_FB20 CAN_F11R2_FB20_Msk /*!< Filter bit 20 */
+#define CAN_F11R2_FB21_Pos (21U)
+#define CAN_F11R2_FB21_Msk (0x1U << CAN_F11R2_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F11R2_FB21 CAN_F11R2_FB21_Msk /*!< Filter bit 21 */
+#define CAN_F11R2_FB22_Pos (22U)
+#define CAN_F11R2_FB22_Msk (0x1U << CAN_F11R2_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F11R2_FB22 CAN_F11R2_FB22_Msk /*!< Filter bit 22 */
+#define CAN_F11R2_FB23_Pos (23U)
+#define CAN_F11R2_FB23_Msk (0x1U << CAN_F11R2_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F11R2_FB23 CAN_F11R2_FB23_Msk /*!< Filter bit 23 */
+#define CAN_F11R2_FB24_Pos (24U)
+#define CAN_F11R2_FB24_Msk (0x1U << CAN_F11R2_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F11R2_FB24 CAN_F11R2_FB24_Msk /*!< Filter bit 24 */
+#define CAN_F11R2_FB25_Pos (25U)
+#define CAN_F11R2_FB25_Msk (0x1U << CAN_F11R2_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F11R2_FB25 CAN_F11R2_FB25_Msk /*!< Filter bit 25 */
+#define CAN_F11R2_FB26_Pos (26U)
+#define CAN_F11R2_FB26_Msk (0x1U << CAN_F11R2_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F11R2_FB26 CAN_F11R2_FB26_Msk /*!< Filter bit 26 */
+#define CAN_F11R2_FB27_Pos (27U)
+#define CAN_F11R2_FB27_Msk (0x1U << CAN_F11R2_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F11R2_FB27 CAN_F11R2_FB27_Msk /*!< Filter bit 27 */
+#define CAN_F11R2_FB28_Pos (28U)
+#define CAN_F11R2_FB28_Msk (0x1U << CAN_F11R2_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F11R2_FB28 CAN_F11R2_FB28_Msk /*!< Filter bit 28 */
+#define CAN_F11R2_FB29_Pos (29U)
+#define CAN_F11R2_FB29_Msk (0x1U << CAN_F11R2_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F11R2_FB29 CAN_F11R2_FB29_Msk /*!< Filter bit 29 */
+#define CAN_F11R2_FB30_Pos (30U)
+#define CAN_F11R2_FB30_Msk (0x1U << CAN_F11R2_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F11R2_FB30 CAN_F11R2_FB30_Msk /*!< Filter bit 30 */
+#define CAN_F11R2_FB31_Pos (31U)
+#define CAN_F11R2_FB31_Msk (0x1U << CAN_F11R2_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F11R2_FB31 CAN_F11R2_FB31_Msk /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F12R2 register ******************/
+#define CAN_F12R2_FB0_Pos (0U)
+#define CAN_F12R2_FB0_Msk (0x1U << CAN_F12R2_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F12R2_FB0 CAN_F12R2_FB0_Msk /*!< Filter bit 0 */
+#define CAN_F12R2_FB1_Pos (1U)
+#define CAN_F12R2_FB1_Msk (0x1U << CAN_F12R2_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F12R2_FB1 CAN_F12R2_FB1_Msk /*!< Filter bit 1 */
+#define CAN_F12R2_FB2_Pos (2U)
+#define CAN_F12R2_FB2_Msk (0x1U << CAN_F12R2_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F12R2_FB2 CAN_F12R2_FB2_Msk /*!< Filter bit 2 */
+#define CAN_F12R2_FB3_Pos (3U)
+#define CAN_F12R2_FB3_Msk (0x1U << CAN_F12R2_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F12R2_FB3 CAN_F12R2_FB3_Msk /*!< Filter bit 3 */
+#define CAN_F12R2_FB4_Pos (4U)
+#define CAN_F12R2_FB4_Msk (0x1U << CAN_F12R2_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F12R2_FB4 CAN_F12R2_FB4_Msk /*!< Filter bit 4 */
+#define CAN_F12R2_FB5_Pos (5U)
+#define CAN_F12R2_FB5_Msk (0x1U << CAN_F12R2_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F12R2_FB5 CAN_F12R2_FB5_Msk /*!< Filter bit 5 */
+#define CAN_F12R2_FB6_Pos (6U)
+#define CAN_F12R2_FB6_Msk (0x1U << CAN_F12R2_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F12R2_FB6 CAN_F12R2_FB6_Msk /*!< Filter bit 6 */
+#define CAN_F12R2_FB7_Pos (7U)
+#define CAN_F12R2_FB7_Msk (0x1U << CAN_F12R2_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F12R2_FB7 CAN_F12R2_FB7_Msk /*!< Filter bit 7 */
+#define CAN_F12R2_FB8_Pos (8U)
+#define CAN_F12R2_FB8_Msk (0x1U << CAN_F12R2_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F12R2_FB8 CAN_F12R2_FB8_Msk /*!< Filter bit 8 */
+#define CAN_F12R2_FB9_Pos (9U)
+#define CAN_F12R2_FB9_Msk (0x1U << CAN_F12R2_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F12R2_FB9 CAN_F12R2_FB9_Msk /*!< Filter bit 9 */
+#define CAN_F12R2_FB10_Pos (10U)
+#define CAN_F12R2_FB10_Msk (0x1U << CAN_F12R2_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F12R2_FB10 CAN_F12R2_FB10_Msk /*!< Filter bit 10 */
+#define CAN_F12R2_FB11_Pos (11U)
+#define CAN_F12R2_FB11_Msk (0x1U << CAN_F12R2_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F12R2_FB11 CAN_F12R2_FB11_Msk /*!< Filter bit 11 */
+#define CAN_F12R2_FB12_Pos (12U)
+#define CAN_F12R2_FB12_Msk (0x1U << CAN_F12R2_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F12R2_FB12 CAN_F12R2_FB12_Msk /*!< Filter bit 12 */
+#define CAN_F12R2_FB13_Pos (13U)
+#define CAN_F12R2_FB13_Msk (0x1U << CAN_F12R2_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F12R2_FB13 CAN_F12R2_FB13_Msk /*!< Filter bit 13 */
+#define CAN_F12R2_FB14_Pos (14U)
+#define CAN_F12R2_FB14_Msk (0x1U << CAN_F12R2_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F12R2_FB14 CAN_F12R2_FB14_Msk /*!< Filter bit 14 */
+#define CAN_F12R2_FB15_Pos (15U)
+#define CAN_F12R2_FB15_Msk (0x1U << CAN_F12R2_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F12R2_FB15 CAN_F12R2_FB15_Msk /*!< Filter bit 15 */
+#define CAN_F12R2_FB16_Pos (16U)
+#define CAN_F12R2_FB16_Msk (0x1U << CAN_F12R2_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F12R2_FB16 CAN_F12R2_FB16_Msk /*!< Filter bit 16 */
+#define CAN_F12R2_FB17_Pos (17U)
+#define CAN_F12R2_FB17_Msk (0x1U << CAN_F12R2_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F12R2_FB17 CAN_F12R2_FB17_Msk /*!< Filter bit 17 */
+#define CAN_F12R2_FB18_Pos (18U)
+#define CAN_F12R2_FB18_Msk (0x1U << CAN_F12R2_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F12R2_FB18 CAN_F12R2_FB18_Msk /*!< Filter bit 18 */
+#define CAN_F12R2_FB19_Pos (19U)
+#define CAN_F12R2_FB19_Msk (0x1U << CAN_F12R2_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F12R2_FB19 CAN_F12R2_FB19_Msk /*!< Filter bit 19 */
+#define CAN_F12R2_FB20_Pos (20U)
+#define CAN_F12R2_FB20_Msk (0x1U << CAN_F12R2_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F12R2_FB20 CAN_F12R2_FB20_Msk /*!< Filter bit 20 */
+#define CAN_F12R2_FB21_Pos (21U)
+#define CAN_F12R2_FB21_Msk (0x1U << CAN_F12R2_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F12R2_FB21 CAN_F12R2_FB21_Msk /*!< Filter bit 21 */
+#define CAN_F12R2_FB22_Pos (22U)
+#define CAN_F12R2_FB22_Msk (0x1U << CAN_F12R2_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F12R2_FB22 CAN_F12R2_FB22_Msk /*!< Filter bit 22 */
+#define CAN_F12R2_FB23_Pos (23U)
+#define CAN_F12R2_FB23_Msk (0x1U << CAN_F12R2_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F12R2_FB23 CAN_F12R2_FB23_Msk /*!< Filter bit 23 */
+#define CAN_F12R2_FB24_Pos (24U)
+#define CAN_F12R2_FB24_Msk (0x1U << CAN_F12R2_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F12R2_FB24 CAN_F12R2_FB24_Msk /*!< Filter bit 24 */
+#define CAN_F12R2_FB25_Pos (25U)
+#define CAN_F12R2_FB25_Msk (0x1U << CAN_F12R2_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F12R2_FB25 CAN_F12R2_FB25_Msk /*!< Filter bit 25 */
+#define CAN_F12R2_FB26_Pos (26U)
+#define CAN_F12R2_FB26_Msk (0x1U << CAN_F12R2_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F12R2_FB26 CAN_F12R2_FB26_Msk /*!< Filter bit 26 */
+#define CAN_F12R2_FB27_Pos (27U)
+#define CAN_F12R2_FB27_Msk (0x1U << CAN_F12R2_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F12R2_FB27 CAN_F12R2_FB27_Msk /*!< Filter bit 27 */
+#define CAN_F12R2_FB28_Pos (28U)
+#define CAN_F12R2_FB28_Msk (0x1U << CAN_F12R2_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F12R2_FB28 CAN_F12R2_FB28_Msk /*!< Filter bit 28 */
+#define CAN_F12R2_FB29_Pos (29U)
+#define CAN_F12R2_FB29_Msk (0x1U << CAN_F12R2_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F12R2_FB29 CAN_F12R2_FB29_Msk /*!< Filter bit 29 */
+#define CAN_F12R2_FB30_Pos (30U)
+#define CAN_F12R2_FB30_Msk (0x1U << CAN_F12R2_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F12R2_FB30 CAN_F12R2_FB30_Msk /*!< Filter bit 30 */
+#define CAN_F12R2_FB31_Pos (31U)
+#define CAN_F12R2_FB31_Msk (0x1U << CAN_F12R2_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F12R2_FB31 CAN_F12R2_FB31_Msk /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F13R2 register ******************/
+#define CAN_F13R2_FB0_Pos (0U)
+#define CAN_F13R2_FB0_Msk (0x1U << CAN_F13R2_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F13R2_FB0 CAN_F13R2_FB0_Msk /*!< Filter bit 0 */
+#define CAN_F13R2_FB1_Pos (1U)
+#define CAN_F13R2_FB1_Msk (0x1U << CAN_F13R2_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F13R2_FB1 CAN_F13R2_FB1_Msk /*!< Filter bit 1 */
+#define CAN_F13R2_FB2_Pos (2U)
+#define CAN_F13R2_FB2_Msk (0x1U << CAN_F13R2_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F13R2_FB2 CAN_F13R2_FB2_Msk /*!< Filter bit 2 */
+#define CAN_F13R2_FB3_Pos (3U)
+#define CAN_F13R2_FB3_Msk (0x1U << CAN_F13R2_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F13R2_FB3 CAN_F13R2_FB3_Msk /*!< Filter bit 3 */
+#define CAN_F13R2_FB4_Pos (4U)
+#define CAN_F13R2_FB4_Msk (0x1U << CAN_F13R2_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F13R2_FB4 CAN_F13R2_FB4_Msk /*!< Filter bit 4 */
+#define CAN_F13R2_FB5_Pos (5U)
+#define CAN_F13R2_FB5_Msk (0x1U << CAN_F13R2_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F13R2_FB5 CAN_F13R2_FB5_Msk /*!< Filter bit 5 */
+#define CAN_F13R2_FB6_Pos (6U)
+#define CAN_F13R2_FB6_Msk (0x1U << CAN_F13R2_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F13R2_FB6 CAN_F13R2_FB6_Msk /*!< Filter bit 6 */
+#define CAN_F13R2_FB7_Pos (7U)
+#define CAN_F13R2_FB7_Msk (0x1U << CAN_F13R2_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F13R2_FB7 CAN_F13R2_FB7_Msk /*!< Filter bit 7 */
+#define CAN_F13R2_FB8_Pos (8U)
+#define CAN_F13R2_FB8_Msk (0x1U << CAN_F13R2_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F13R2_FB8 CAN_F13R2_FB8_Msk /*!< Filter bit 8 */
+#define CAN_F13R2_FB9_Pos (9U)
+#define CAN_F13R2_FB9_Msk (0x1U << CAN_F13R2_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F13R2_FB9 CAN_F13R2_FB9_Msk /*!< Filter bit 9 */
+#define CAN_F13R2_FB10_Pos (10U)
+#define CAN_F13R2_FB10_Msk (0x1U << CAN_F13R2_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F13R2_FB10 CAN_F13R2_FB10_Msk /*!< Filter bit 10 */
+#define CAN_F13R2_FB11_Pos (11U)
+#define CAN_F13R2_FB11_Msk (0x1U << CAN_F13R2_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F13R2_FB11 CAN_F13R2_FB11_Msk /*!< Filter bit 11 */
+#define CAN_F13R2_FB12_Pos (12U)
+#define CAN_F13R2_FB12_Msk (0x1U << CAN_F13R2_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F13R2_FB12 CAN_F13R2_FB12_Msk /*!< Filter bit 12 */
+#define CAN_F13R2_FB13_Pos (13U)
+#define CAN_F13R2_FB13_Msk (0x1U << CAN_F13R2_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F13R2_FB13 CAN_F13R2_FB13_Msk /*!< Filter bit 13 */
+#define CAN_F13R2_FB14_Pos (14U)
+#define CAN_F13R2_FB14_Msk (0x1U << CAN_F13R2_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F13R2_FB14 CAN_F13R2_FB14_Msk /*!< Filter bit 14 */
+#define CAN_F13R2_FB15_Pos (15U)
+#define CAN_F13R2_FB15_Msk (0x1U << CAN_F13R2_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F13R2_FB15 CAN_F13R2_FB15_Msk /*!< Filter bit 15 */
+#define CAN_F13R2_FB16_Pos (16U)
+#define CAN_F13R2_FB16_Msk (0x1U << CAN_F13R2_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F13R2_FB16 CAN_F13R2_FB16_Msk /*!< Filter bit 16 */
+#define CAN_F13R2_FB17_Pos (17U)
+#define CAN_F13R2_FB17_Msk (0x1U << CAN_F13R2_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F13R2_FB17 CAN_F13R2_FB17_Msk /*!< Filter bit 17 */
+#define CAN_F13R2_FB18_Pos (18U)
+#define CAN_F13R2_FB18_Msk (0x1U << CAN_F13R2_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F13R2_FB18 CAN_F13R2_FB18_Msk /*!< Filter bit 18 */
+#define CAN_F13R2_FB19_Pos (19U)
+#define CAN_F13R2_FB19_Msk (0x1U << CAN_F13R2_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F13R2_FB19 CAN_F13R2_FB19_Msk /*!< Filter bit 19 */
+#define CAN_F13R2_FB20_Pos (20U)
+#define CAN_F13R2_FB20_Msk (0x1U << CAN_F13R2_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F13R2_FB20 CAN_F13R2_FB20_Msk /*!< Filter bit 20 */
+#define CAN_F13R2_FB21_Pos (21U)
+#define CAN_F13R2_FB21_Msk (0x1U << CAN_F13R2_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F13R2_FB21 CAN_F13R2_FB21_Msk /*!< Filter bit 21 */
+#define CAN_F13R2_FB22_Pos (22U)
+#define CAN_F13R2_FB22_Msk (0x1U << CAN_F13R2_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F13R2_FB22 CAN_F13R2_FB22_Msk /*!< Filter bit 22 */
+#define CAN_F13R2_FB23_Pos (23U)
+#define CAN_F13R2_FB23_Msk (0x1U << CAN_F13R2_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F13R2_FB23 CAN_F13R2_FB23_Msk /*!< Filter bit 23 */
+#define CAN_F13R2_FB24_Pos (24U)
+#define CAN_F13R2_FB24_Msk (0x1U << CAN_F13R2_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F13R2_FB24 CAN_F13R2_FB24_Msk /*!< Filter bit 24 */
+#define CAN_F13R2_FB25_Pos (25U)
+#define CAN_F13R2_FB25_Msk (0x1U << CAN_F13R2_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F13R2_FB25 CAN_F13R2_FB25_Msk /*!< Filter bit 25 */
+#define CAN_F13R2_FB26_Pos (26U)
+#define CAN_F13R2_FB26_Msk (0x1U << CAN_F13R2_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F13R2_FB26 CAN_F13R2_FB26_Msk /*!< Filter bit 26 */
+#define CAN_F13R2_FB27_Pos (27U)
+#define CAN_F13R2_FB27_Msk (0x1U << CAN_F13R2_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F13R2_FB27 CAN_F13R2_FB27_Msk /*!< Filter bit 27 */
+#define CAN_F13R2_FB28_Pos (28U)
+#define CAN_F13R2_FB28_Msk (0x1U << CAN_F13R2_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F13R2_FB28 CAN_F13R2_FB28_Msk /*!< Filter bit 28 */
+#define CAN_F13R2_FB29_Pos (29U)
+#define CAN_F13R2_FB29_Msk (0x1U << CAN_F13R2_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F13R2_FB29 CAN_F13R2_FB29_Msk /*!< Filter bit 29 */
+#define CAN_F13R2_FB30_Pos (30U)
+#define CAN_F13R2_FB30_Msk (0x1U << CAN_F13R2_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F13R2_FB30 CAN_F13R2_FB30_Msk /*!< Filter bit 30 */
+#define CAN_F13R2_FB31_Pos (31U)
+#define CAN_F13R2_FB31_Msk (0x1U << CAN_F13R2_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F13R2_FB31 CAN_F13R2_FB31_Msk /*!< Filter bit 31 */
+
+/******************************************************************************/
+/* */
+/* Serial Peripheral Interface */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for SPI_CR1 register ********************/
+#define SPI_CR1_CPHA_Pos (0U)
+#define SPI_CR1_CPHA_Msk (0x1U << SPI_CR1_CPHA_Pos) /*!< 0x00000001 */
+#define SPI_CR1_CPHA SPI_CR1_CPHA_Msk /*!< Clock Phase */
+#define SPI_CR1_CPOL_Pos (1U)
+#define SPI_CR1_CPOL_Msk (0x1U << SPI_CR1_CPOL_Pos) /*!< 0x00000002 */
+#define SPI_CR1_CPOL SPI_CR1_CPOL_Msk /*!< Clock Polarity */
+#define SPI_CR1_MSTR_Pos (2U)
+#define SPI_CR1_MSTR_Msk (0x1U << SPI_CR1_MSTR_Pos) /*!< 0x00000004 */
+#define SPI_CR1_MSTR SPI_CR1_MSTR_Msk /*!< Master Selection */
+
+#define SPI_CR1_BR_Pos (3U)
+#define SPI_CR1_BR_Msk (0x7U << SPI_CR1_BR_Pos) /*!< 0x00000038 */
+#define SPI_CR1_BR SPI_CR1_BR_Msk /*!< BR[2:0] bits (Baud Rate Control) */
+#define SPI_CR1_BR_0 (0x1U << SPI_CR1_BR_Pos) /*!< 0x00000008 */
+#define SPI_CR1_BR_1 (0x2U << SPI_CR1_BR_Pos) /*!< 0x00000010 */
+#define SPI_CR1_BR_2 (0x4U << SPI_CR1_BR_Pos) /*!< 0x00000020 */
+
+#define SPI_CR1_SPE_Pos (6U)
+#define SPI_CR1_SPE_Msk (0x1U << SPI_CR1_SPE_Pos) /*!< 0x00000040 */
+#define SPI_CR1_SPE SPI_CR1_SPE_Msk /*!< SPI Enable */
+#define SPI_CR1_LSBFIRST_Pos (7U)
+#define SPI_CR1_LSBFIRST_Msk (0x1U << SPI_CR1_LSBFIRST_Pos) /*!< 0x00000080 */
+#define SPI_CR1_LSBFIRST SPI_CR1_LSBFIRST_Msk /*!< Frame Format */
+#define SPI_CR1_SSI_Pos (8U)
+#define SPI_CR1_SSI_Msk (0x1U << SPI_CR1_SSI_Pos) /*!< 0x00000100 */
+#define SPI_CR1_SSI SPI_CR1_SSI_Msk /*!< Internal slave select */
+#define SPI_CR1_SSM_Pos (9U)
+#define SPI_CR1_SSM_Msk (0x1U << SPI_CR1_SSM_Pos) /*!< 0x00000200 */
+#define SPI_CR1_SSM SPI_CR1_SSM_Msk /*!< Software slave management */
+#define SPI_CR1_RXONLY_Pos (10U)
+#define SPI_CR1_RXONLY_Msk (0x1U << SPI_CR1_RXONLY_Pos) /*!< 0x00000400 */
+#define SPI_CR1_RXONLY SPI_CR1_RXONLY_Msk /*!< Receive only */
+#define SPI_CR1_DFF_Pos (11U)
+#define SPI_CR1_DFF_Msk (0x1U << SPI_CR1_DFF_Pos) /*!< 0x00000800 */
+#define SPI_CR1_DFF SPI_CR1_DFF_Msk /*!< Data Frame Format */
+#define SPI_CR1_CRCNEXT_Pos (12U)
+#define SPI_CR1_CRCNEXT_Msk (0x1U << SPI_CR1_CRCNEXT_Pos) /*!< 0x00001000 */
+#define SPI_CR1_CRCNEXT SPI_CR1_CRCNEXT_Msk /*!< Transmit CRC next */
+#define SPI_CR1_CRCEN_Pos (13U)
+#define SPI_CR1_CRCEN_Msk (0x1U << SPI_CR1_CRCEN_Pos) /*!< 0x00002000 */
+#define SPI_CR1_CRCEN SPI_CR1_CRCEN_Msk /*!< Hardware CRC calculation enable */
+#define SPI_CR1_BIDIOE_Pos (14U)
+#define SPI_CR1_BIDIOE_Msk (0x1U << SPI_CR1_BIDIOE_Pos) /*!< 0x00004000 */
+#define SPI_CR1_BIDIOE SPI_CR1_BIDIOE_Msk /*!< Output enable in bidirectional mode */
+#define SPI_CR1_BIDIMODE_Pos (15U)
+#define SPI_CR1_BIDIMODE_Msk (0x1U << SPI_CR1_BIDIMODE_Pos) /*!< 0x00008000 */
+#define SPI_CR1_BIDIMODE SPI_CR1_BIDIMODE_Msk /*!< Bidirectional data mode enable */
+
+/******************* Bit definition for SPI_CR2 register ********************/
+#define SPI_CR2_RXDMAEN_Pos (0U)
+#define SPI_CR2_RXDMAEN_Msk (0x1U << SPI_CR2_RXDMAEN_Pos) /*!< 0x00000001 */
+#define SPI_CR2_RXDMAEN SPI_CR2_RXDMAEN_Msk /*!< Rx Buffer DMA Enable */
+#define SPI_CR2_TXDMAEN_Pos (1U)
+#define SPI_CR2_TXDMAEN_Msk (0x1U << SPI_CR2_TXDMAEN_Pos) /*!< 0x00000002 */
+#define SPI_CR2_TXDMAEN SPI_CR2_TXDMAEN_Msk /*!< Tx Buffer DMA Enable */
+#define SPI_CR2_SSOE_Pos (2U)
+#define SPI_CR2_SSOE_Msk (0x1U << SPI_CR2_SSOE_Pos) /*!< 0x00000004 */
+#define SPI_CR2_SSOE SPI_CR2_SSOE_Msk /*!< SS Output Enable */
+#define SPI_CR2_ERRIE_Pos (5U)
+#define SPI_CR2_ERRIE_Msk (0x1U << SPI_CR2_ERRIE_Pos) /*!< 0x00000020 */
+#define SPI_CR2_ERRIE SPI_CR2_ERRIE_Msk /*!< Error Interrupt Enable */
+#define SPI_CR2_RXNEIE_Pos (6U)
+#define SPI_CR2_RXNEIE_Msk (0x1U << SPI_CR2_RXNEIE_Pos) /*!< 0x00000040 */
+#define SPI_CR2_RXNEIE SPI_CR2_RXNEIE_Msk /*!< RX buffer Not Empty Interrupt Enable */
+#define SPI_CR2_TXEIE_Pos (7U)
+#define SPI_CR2_TXEIE_Msk (0x1U << SPI_CR2_TXEIE_Pos) /*!< 0x00000080 */
+#define SPI_CR2_TXEIE SPI_CR2_TXEIE_Msk /*!< Tx buffer Empty Interrupt Enable */
+
+/******************** Bit definition for SPI_SR register ********************/
+#define SPI_SR_RXNE_Pos (0U)
+#define SPI_SR_RXNE_Msk (0x1U << SPI_SR_RXNE_Pos) /*!< 0x00000001 */
+#define SPI_SR_RXNE SPI_SR_RXNE_Msk /*!< Receive buffer Not Empty */
+#define SPI_SR_TXE_Pos (1U)
+#define SPI_SR_TXE_Msk (0x1U << SPI_SR_TXE_Pos) /*!< 0x00000002 */
+#define SPI_SR_TXE SPI_SR_TXE_Msk /*!< Transmit buffer Empty */
+#define SPI_SR_CHSIDE_Pos (2U)
+#define SPI_SR_CHSIDE_Msk (0x1U << SPI_SR_CHSIDE_Pos) /*!< 0x00000004 */
+#define SPI_SR_CHSIDE SPI_SR_CHSIDE_Msk /*!< Channel side */
+#define SPI_SR_UDR_Pos (3U)
+#define SPI_SR_UDR_Msk (0x1U << SPI_SR_UDR_Pos) /*!< 0x00000008 */
+#define SPI_SR_UDR SPI_SR_UDR_Msk /*!< Underrun flag */
+#define SPI_SR_CRCERR_Pos (4U)
+#define SPI_SR_CRCERR_Msk (0x1U << SPI_SR_CRCERR_Pos) /*!< 0x00000010 */
+#define SPI_SR_CRCERR SPI_SR_CRCERR_Msk /*!< CRC Error flag */
+#define SPI_SR_MODF_Pos (5U)
+#define SPI_SR_MODF_Msk (0x1U << SPI_SR_MODF_Pos) /*!< 0x00000020 */
+#define SPI_SR_MODF SPI_SR_MODF_Msk /*!< Mode fault */
+#define SPI_SR_OVR_Pos (6U)
+#define SPI_SR_OVR_Msk (0x1U << SPI_SR_OVR_Pos) /*!< 0x00000040 */
+#define SPI_SR_OVR SPI_SR_OVR_Msk /*!< Overrun flag */
+#define SPI_SR_BSY_Pos (7U)
+#define SPI_SR_BSY_Msk (0x1U << SPI_SR_BSY_Pos) /*!< 0x00000080 */
+#define SPI_SR_BSY SPI_SR_BSY_Msk /*!< Busy flag */
+
+/******************** Bit definition for SPI_DR register ********************/
+#define SPI_DR_DR_Pos (0U)
+#define SPI_DR_DR_Msk (0xFFFFU << SPI_DR_DR_Pos) /*!< 0x0000FFFF */
+#define SPI_DR_DR SPI_DR_DR_Msk /*!< Data Register */
+
+/******************* Bit definition for SPI_CRCPR register ******************/
+#define SPI_CRCPR_CRCPOLY_Pos (0U)
+#define SPI_CRCPR_CRCPOLY_Msk (0xFFFFU << SPI_CRCPR_CRCPOLY_Pos) /*!< 0x0000FFFF */
+#define SPI_CRCPR_CRCPOLY SPI_CRCPR_CRCPOLY_Msk /*!< CRC polynomial register */
+
+/****************** Bit definition for SPI_RXCRCR register ******************/
+#define SPI_RXCRCR_RXCRC_Pos (0U)
+#define SPI_RXCRCR_RXCRC_Msk (0xFFFFU << SPI_RXCRCR_RXCRC_Pos) /*!< 0x0000FFFF */
+#define SPI_RXCRCR_RXCRC SPI_RXCRCR_RXCRC_Msk /*!< Rx CRC Register */
+
+/****************** Bit definition for SPI_TXCRCR register ******************/
+#define SPI_TXCRCR_TXCRC_Pos (0U)
+#define SPI_TXCRCR_TXCRC_Msk (0xFFFFU << SPI_TXCRCR_TXCRC_Pos) /*!< 0x0000FFFF */
+#define SPI_TXCRCR_TXCRC SPI_TXCRCR_TXCRC_Msk /*!< Tx CRC Register */
+
+/****************** Bit definition for SPI_I2SCFGR register *****************/
+#define SPI_I2SCFGR_I2SMOD_Pos (11U)
+#define SPI_I2SCFGR_I2SMOD_Msk (0x1U << SPI_I2SCFGR_I2SMOD_Pos) /*!< 0x00000800 */
+#define SPI_I2SCFGR_I2SMOD SPI_I2SCFGR_I2SMOD_Msk /*!< I2S mode selection */
+
+
+/******************************************************************************/
+/* */
+/* Inter-integrated Circuit Interface */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for I2C_CR1 register ********************/
+#define I2C_CR1_PE_Pos (0U)
+#define I2C_CR1_PE_Msk (0x1U << I2C_CR1_PE_Pos) /*!< 0x00000001 */
+#define I2C_CR1_PE I2C_CR1_PE_Msk /*!< Peripheral Enable */
+#define I2C_CR1_SMBUS_Pos (1U)
+#define I2C_CR1_SMBUS_Msk (0x1U << I2C_CR1_SMBUS_Pos) /*!< 0x00000002 */
+#define I2C_CR1_SMBUS I2C_CR1_SMBUS_Msk /*!< SMBus Mode */
+#define I2C_CR1_SMBTYPE_Pos (3U)
+#define I2C_CR1_SMBTYPE_Msk (0x1U << I2C_CR1_SMBTYPE_Pos) /*!< 0x00000008 */
+#define I2C_CR1_SMBTYPE I2C_CR1_SMBTYPE_Msk /*!< SMBus Type */
+#define I2C_CR1_ENARP_Pos (4U)
+#define I2C_CR1_ENARP_Msk (0x1U << I2C_CR1_ENARP_Pos) /*!< 0x00000010 */
+#define I2C_CR1_ENARP I2C_CR1_ENARP_Msk /*!< ARP Enable */
+#define I2C_CR1_ENPEC_Pos (5U)
+#define I2C_CR1_ENPEC_Msk (0x1U << I2C_CR1_ENPEC_Pos) /*!< 0x00000020 */
+#define I2C_CR1_ENPEC I2C_CR1_ENPEC_Msk /*!< PEC Enable */
+#define I2C_CR1_ENGC_Pos (6U)
+#define I2C_CR1_ENGC_Msk (0x1U << I2C_CR1_ENGC_Pos) /*!< 0x00000040 */
+#define I2C_CR1_ENGC I2C_CR1_ENGC_Msk /*!< General Call Enable */
+#define I2C_CR1_NOSTRETCH_Pos (7U)
+#define I2C_CR1_NOSTRETCH_Msk (0x1U << I2C_CR1_NOSTRETCH_Pos) /*!< 0x00000080 */
+#define I2C_CR1_NOSTRETCH I2C_CR1_NOSTRETCH_Msk /*!< Clock Stretching Disable (Slave mode) */
+#define I2C_CR1_START_Pos (8U)
+#define I2C_CR1_START_Msk (0x1U << I2C_CR1_START_Pos) /*!< 0x00000100 */
+#define I2C_CR1_START I2C_CR1_START_Msk /*!< Start Generation */
+#define I2C_CR1_STOP_Pos (9U)
+#define I2C_CR1_STOP_Msk (0x1U << I2C_CR1_STOP_Pos) /*!< 0x00000200 */
+#define I2C_CR1_STOP I2C_CR1_STOP_Msk /*!< Stop Generation */
+#define I2C_CR1_ACK_Pos (10U)
+#define I2C_CR1_ACK_Msk (0x1U << I2C_CR1_ACK_Pos) /*!< 0x00000400 */
+#define I2C_CR1_ACK I2C_CR1_ACK_Msk /*!< Acknowledge Enable */
+#define I2C_CR1_POS_Pos (11U)
+#define I2C_CR1_POS_Msk (0x1U << I2C_CR1_POS_Pos) /*!< 0x00000800 */
+#define I2C_CR1_POS I2C_CR1_POS_Msk /*!< Acknowledge/PEC Position (for data reception) */
+#define I2C_CR1_PEC_Pos (12U)
+#define I2C_CR1_PEC_Msk (0x1U << I2C_CR1_PEC_Pos) /*!< 0x00001000 */
+#define I2C_CR1_PEC I2C_CR1_PEC_Msk /*!< Packet Error Checking */
+#define I2C_CR1_ALERT_Pos (13U)
+#define I2C_CR1_ALERT_Msk (0x1U << I2C_CR1_ALERT_Pos) /*!< 0x00002000 */
+#define I2C_CR1_ALERT I2C_CR1_ALERT_Msk /*!< SMBus Alert */
+#define I2C_CR1_SWRST_Pos (15U)
+#define I2C_CR1_SWRST_Msk (0x1U << I2C_CR1_SWRST_Pos) /*!< 0x00008000 */
+#define I2C_CR1_SWRST I2C_CR1_SWRST_Msk /*!< Software Reset */
+
+/******************* Bit definition for I2C_CR2 register ********************/
+#define I2C_CR2_FREQ_Pos (0U)
+#define I2C_CR2_FREQ_Msk (0x3FU << I2C_CR2_FREQ_Pos) /*!< 0x0000003F */
+#define I2C_CR2_FREQ I2C_CR2_FREQ_Msk /*!< FREQ[5:0] bits (Peripheral Clock Frequency) */
+#define I2C_CR2_FREQ_0 (0x01U << I2C_CR2_FREQ_Pos) /*!< 0x00000001 */
+#define I2C_CR2_FREQ_1 (0x02U << I2C_CR2_FREQ_Pos) /*!< 0x00000002 */
+#define I2C_CR2_FREQ_2 (0x04U << I2C_CR2_FREQ_Pos) /*!< 0x00000004 */
+#define I2C_CR2_FREQ_3 (0x08U << I2C_CR2_FREQ_Pos) /*!< 0x00000008 */
+#define I2C_CR2_FREQ_4 (0x10U << I2C_CR2_FREQ_Pos) /*!< 0x00000010 */
+#define I2C_CR2_FREQ_5 (0x20U << I2C_CR2_FREQ_Pos) /*!< 0x00000020 */
+
+#define I2C_CR2_ITERREN_Pos (8U)
+#define I2C_CR2_ITERREN_Msk (0x1U << I2C_CR2_ITERREN_Pos) /*!< 0x00000100 */
+#define I2C_CR2_ITERREN I2C_CR2_ITERREN_Msk /*!< Error Interrupt Enable */
+#define I2C_CR2_ITEVTEN_Pos (9U)
+#define I2C_CR2_ITEVTEN_Msk (0x1U << I2C_CR2_ITEVTEN_Pos) /*!< 0x00000200 */
+#define I2C_CR2_ITEVTEN I2C_CR2_ITEVTEN_Msk /*!< Event Interrupt Enable */
+#define I2C_CR2_ITBUFEN_Pos (10U)
+#define I2C_CR2_ITBUFEN_Msk (0x1U << I2C_CR2_ITBUFEN_Pos) /*!< 0x00000400 */
+#define I2C_CR2_ITBUFEN I2C_CR2_ITBUFEN_Msk /*!< Buffer Interrupt Enable */
+#define I2C_CR2_DMAEN_Pos (11U)
+#define I2C_CR2_DMAEN_Msk (0x1U << I2C_CR2_DMAEN_Pos) /*!< 0x00000800 */
+#define I2C_CR2_DMAEN I2C_CR2_DMAEN_Msk /*!< DMA Requests Enable */
+#define I2C_CR2_LAST_Pos (12U)
+#define I2C_CR2_LAST_Msk (0x1U << I2C_CR2_LAST_Pos) /*!< 0x00001000 */
+#define I2C_CR2_LAST I2C_CR2_LAST_Msk /*!< DMA Last Transfer */
+
+/******************* Bit definition for I2C_OAR1 register *******************/
+#define I2C_OAR1_ADD1_7 ((uint32_t)0x000000FE) /*!< Interface Address */
+#define I2C_OAR1_ADD8_9 ((uint32_t)0x00000300) /*!< Interface Address */
+
+#define I2C_OAR1_ADD0_Pos (0U)
+#define I2C_OAR1_ADD0_Msk (0x1U << I2C_OAR1_ADD0_Pos) /*!< 0x00000001 */
+#define I2C_OAR1_ADD0 I2C_OAR1_ADD0_Msk /*!< Bit 0 */
+#define I2C_OAR1_ADD1_Pos (1U)
+#define I2C_OAR1_ADD1_Msk (0x1U << I2C_OAR1_ADD1_Pos) /*!< 0x00000002 */
+#define I2C_OAR1_ADD1 I2C_OAR1_ADD1_Msk /*!< Bit 1 */
+#define I2C_OAR1_ADD2_Pos (2U)
+#define I2C_OAR1_ADD2_Msk (0x1U << I2C_OAR1_ADD2_Pos) /*!< 0x00000004 */
+#define I2C_OAR1_ADD2 I2C_OAR1_ADD2_Msk /*!< Bit 2 */
+#define I2C_OAR1_ADD3_Pos (3U)
+#define I2C_OAR1_ADD3_Msk (0x1U << I2C_OAR1_ADD3_Pos) /*!< 0x00000008 */
+#define I2C_OAR1_ADD3 I2C_OAR1_ADD3_Msk /*!< Bit 3 */
+#define I2C_OAR1_ADD4_Pos (4U)
+#define I2C_OAR1_ADD4_Msk (0x1U << I2C_OAR1_ADD4_Pos) /*!< 0x00000010 */
+#define I2C_OAR1_ADD4 I2C_OAR1_ADD4_Msk /*!< Bit 4 */
+#define I2C_OAR1_ADD5_Pos (5U)
+#define I2C_OAR1_ADD5_Msk (0x1U << I2C_OAR1_ADD5_Pos) /*!< 0x00000020 */
+#define I2C_OAR1_ADD5 I2C_OAR1_ADD5_Msk /*!< Bit 5 */
+#define I2C_OAR1_ADD6_Pos (6U)
+#define I2C_OAR1_ADD6_Msk (0x1U << I2C_OAR1_ADD6_Pos) /*!< 0x00000040 */
+#define I2C_OAR1_ADD6 I2C_OAR1_ADD6_Msk /*!< Bit 6 */
+#define I2C_OAR1_ADD7_Pos (7U)
+#define I2C_OAR1_ADD7_Msk (0x1U << I2C_OAR1_ADD7_Pos) /*!< 0x00000080 */
+#define I2C_OAR1_ADD7 I2C_OAR1_ADD7_Msk /*!< Bit 7 */
+#define I2C_OAR1_ADD8_Pos (8U)
+#define I2C_OAR1_ADD8_Msk (0x1U << I2C_OAR1_ADD8_Pos) /*!< 0x00000100 */
+#define I2C_OAR1_ADD8 I2C_OAR1_ADD8_Msk /*!< Bit 8 */
+#define I2C_OAR1_ADD9_Pos (9U)
+#define I2C_OAR1_ADD9_Msk (0x1U << I2C_OAR1_ADD9_Pos) /*!< 0x00000200 */
+#define I2C_OAR1_ADD9 I2C_OAR1_ADD9_Msk /*!< Bit 9 */
+
+#define I2C_OAR1_ADDMODE_Pos (15U)
+#define I2C_OAR1_ADDMODE_Msk (0x1U << I2C_OAR1_ADDMODE_Pos) /*!< 0x00008000 */
+#define I2C_OAR1_ADDMODE I2C_OAR1_ADDMODE_Msk /*!< Addressing Mode (Slave mode) */
+
+/******************* Bit definition for I2C_OAR2 register *******************/
+#define I2C_OAR2_ENDUAL_Pos (0U)
+#define I2C_OAR2_ENDUAL_Msk (0x1U << I2C_OAR2_ENDUAL_Pos) /*!< 0x00000001 */
+#define I2C_OAR2_ENDUAL I2C_OAR2_ENDUAL_Msk /*!< Dual addressing mode enable */
+#define I2C_OAR2_ADD2_Pos (1U)
+#define I2C_OAR2_ADD2_Msk (0x7FU << I2C_OAR2_ADD2_Pos) /*!< 0x000000FE */
+#define I2C_OAR2_ADD2 I2C_OAR2_ADD2_Msk /*!< Interface address */
+
+/******************* Bit definition for I2C_SR1 register ********************/
+#define I2C_SR1_SB_Pos (0U)
+#define I2C_SR1_SB_Msk (0x1U << I2C_SR1_SB_Pos) /*!< 0x00000001 */
+#define I2C_SR1_SB I2C_SR1_SB_Msk /*!< Start Bit (Master mode) */
+#define I2C_SR1_ADDR_Pos (1U)
+#define I2C_SR1_ADDR_Msk (0x1U << I2C_SR1_ADDR_Pos) /*!< 0x00000002 */
+#define I2C_SR1_ADDR I2C_SR1_ADDR_Msk /*!< Address sent (master mode)/matched (slave mode) */
+#define I2C_SR1_BTF_Pos (2U)
+#define I2C_SR1_BTF_Msk (0x1U << I2C_SR1_BTF_Pos) /*!< 0x00000004 */
+#define I2C_SR1_BTF I2C_SR1_BTF_Msk /*!< Byte Transfer Finished */
+#define I2C_SR1_ADD10_Pos (3U)
+#define I2C_SR1_ADD10_Msk (0x1U << I2C_SR1_ADD10_Pos) /*!< 0x00000008 */
+#define I2C_SR1_ADD10 I2C_SR1_ADD10_Msk /*!< 10-bit header sent (Master mode) */
+#define I2C_SR1_STOPF_Pos (4U)
+#define I2C_SR1_STOPF_Msk (0x1U << I2C_SR1_STOPF_Pos) /*!< 0x00000010 */
+#define I2C_SR1_STOPF I2C_SR1_STOPF_Msk /*!< Stop detection (Slave mode) */
+#define I2C_SR1_RXNE_Pos (6U)
+#define I2C_SR1_RXNE_Msk (0x1U << I2C_SR1_RXNE_Pos) /*!< 0x00000040 */
+#define I2C_SR1_RXNE I2C_SR1_RXNE_Msk /*!< Data Register not Empty (receivers) */
+#define I2C_SR1_TXE_Pos (7U)
+#define I2C_SR1_TXE_Msk (0x1U << I2C_SR1_TXE_Pos) /*!< 0x00000080 */
+#define I2C_SR1_TXE I2C_SR1_TXE_Msk /*!< Data Register Empty (transmitters) */
+#define I2C_SR1_BERR_Pos (8U)
+#define I2C_SR1_BERR_Msk (0x1U << I2C_SR1_BERR_Pos) /*!< 0x00000100 */
+#define I2C_SR1_BERR I2C_SR1_BERR_Msk /*!< Bus Error */
+#define I2C_SR1_ARLO_Pos (9U)
+#define I2C_SR1_ARLO_Msk (0x1U << I2C_SR1_ARLO_Pos) /*!< 0x00000200 */
+#define I2C_SR1_ARLO I2C_SR1_ARLO_Msk /*!< Arbitration Lost (master mode) */
+#define I2C_SR1_AF_Pos (10U)
+#define I2C_SR1_AF_Msk (0x1U << I2C_SR1_AF_Pos) /*!< 0x00000400 */
+#define I2C_SR1_AF I2C_SR1_AF_Msk /*!< Acknowledge Failure */
+#define I2C_SR1_OVR_Pos (11U)
+#define I2C_SR1_OVR_Msk (0x1U << I2C_SR1_OVR_Pos) /*!< 0x00000800 */
+#define I2C_SR1_OVR I2C_SR1_OVR_Msk /*!< Overrun/Underrun */
+#define I2C_SR1_PECERR_Pos (12U)
+#define I2C_SR1_PECERR_Msk (0x1U << I2C_SR1_PECERR_Pos) /*!< 0x00001000 */
+#define I2C_SR1_PECERR I2C_SR1_PECERR_Msk /*!< PEC Error in reception */
+#define I2C_SR1_TIMEOUT_Pos (14U)
+#define I2C_SR1_TIMEOUT_Msk (0x1U << I2C_SR1_TIMEOUT_Pos) /*!< 0x00004000 */
+#define I2C_SR1_TIMEOUT I2C_SR1_TIMEOUT_Msk /*!< Timeout or Tlow Error */
+#define I2C_SR1_SMBALERT_Pos (15U)
+#define I2C_SR1_SMBALERT_Msk (0x1U << I2C_SR1_SMBALERT_Pos) /*!< 0x00008000 */
+#define I2C_SR1_SMBALERT I2C_SR1_SMBALERT_Msk /*!< SMBus Alert */
+
+/******************* Bit definition for I2C_SR2 register ********************/
+#define I2C_SR2_MSL_Pos (0U)
+#define I2C_SR2_MSL_Msk (0x1U << I2C_SR2_MSL_Pos) /*!< 0x00000001 */
+#define I2C_SR2_MSL I2C_SR2_MSL_Msk /*!< Master/Slave */
+#define I2C_SR2_BUSY_Pos (1U)
+#define I2C_SR2_BUSY_Msk (0x1U << I2C_SR2_BUSY_Pos) /*!< 0x00000002 */
+#define I2C_SR2_BUSY I2C_SR2_BUSY_Msk /*!< Bus Busy */
+#define I2C_SR2_TRA_Pos (2U)
+#define I2C_SR2_TRA_Msk (0x1U << I2C_SR2_TRA_Pos) /*!< 0x00000004 */
+#define I2C_SR2_TRA I2C_SR2_TRA_Msk /*!< Transmitter/Receiver */
+#define I2C_SR2_GENCALL_Pos (4U)
+#define I2C_SR2_GENCALL_Msk (0x1U << I2C_SR2_GENCALL_Pos) /*!< 0x00000010 */
+#define I2C_SR2_GENCALL I2C_SR2_GENCALL_Msk /*!< General Call Address (Slave mode) */
+#define I2C_SR2_SMBDEFAULT_Pos (5U)
+#define I2C_SR2_SMBDEFAULT_Msk (0x1U << I2C_SR2_SMBDEFAULT_Pos) /*!< 0x00000020 */
+#define I2C_SR2_SMBDEFAULT I2C_SR2_SMBDEFAULT_Msk /*!< SMBus Device Default Address (Slave mode) */
+#define I2C_SR2_SMBHOST_Pos (6U)
+#define I2C_SR2_SMBHOST_Msk (0x1U << I2C_SR2_SMBHOST_Pos) /*!< 0x00000040 */
+#define I2C_SR2_SMBHOST I2C_SR2_SMBHOST_Msk /*!< SMBus Host Header (Slave mode) */
+#define I2C_SR2_DUALF_Pos (7U)
+#define I2C_SR2_DUALF_Msk (0x1U << I2C_SR2_DUALF_Pos) /*!< 0x00000080 */
+#define I2C_SR2_DUALF I2C_SR2_DUALF_Msk /*!< Dual Flag (Slave mode) */
+#define I2C_SR2_PEC_Pos (8U)
+#define I2C_SR2_PEC_Msk (0xFFU << I2C_SR2_PEC_Pos) /*!< 0x0000FF00 */
+#define I2C_SR2_PEC I2C_SR2_PEC_Msk /*!< Packet Error Checking Register */
+
+/******************* Bit definition for I2C_CCR register ********************/
+#define I2C_CCR_CCR_Pos (0U)
+#define I2C_CCR_CCR_Msk (0xFFFU << I2C_CCR_CCR_Pos) /*!< 0x00000FFF */
+#define I2C_CCR_CCR I2C_CCR_CCR_Msk /*!< Clock Control Register in Fast/Standard mode (Master mode) */
+#define I2C_CCR_DUTY_Pos (14U)
+#define I2C_CCR_DUTY_Msk (0x1U << I2C_CCR_DUTY_Pos) /*!< 0x00004000 */
+#define I2C_CCR_DUTY I2C_CCR_DUTY_Msk /*!< Fast Mode Duty Cycle */
+#define I2C_CCR_FS_Pos (15U)
+#define I2C_CCR_FS_Msk (0x1U << I2C_CCR_FS_Pos) /*!< 0x00008000 */
+#define I2C_CCR_FS I2C_CCR_FS_Msk /*!< I2C Master Mode Selection */
+
+/****************** Bit definition for I2C_TRISE register *******************/
+#define I2C_TRISE_TRISE_Pos (0U)
+#define I2C_TRISE_TRISE_Msk (0x3FU << I2C_TRISE_TRISE_Pos) /*!< 0x0000003F */
+#define I2C_TRISE_TRISE I2C_TRISE_TRISE_Msk /*!< Maximum Rise Time in Fast/Standard mode (Master mode) */
+
+/******************************************************************************/
+/* */
+/* Universal Synchronous Asynchronous Receiver Transmitter */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for USART_SR register *******************/
+#define USART_SR_PE_Pos (0U)
+#define USART_SR_PE_Msk (0x1U << USART_SR_PE_Pos) /*!< 0x00000001 */
+#define USART_SR_PE USART_SR_PE_Msk /*!< Parity Error */
+#define USART_SR_FE_Pos (1U)
+#define USART_SR_FE_Msk (0x1U << USART_SR_FE_Pos) /*!< 0x00000002 */
+#define USART_SR_FE USART_SR_FE_Msk /*!< Framing Error */
+#define USART_SR_NE_Pos (2U)
+#define USART_SR_NE_Msk (0x1U << USART_SR_NE_Pos) /*!< 0x00000004 */
+#define USART_SR_NE USART_SR_NE_Msk /*!< Noise Error Flag */
+#define USART_SR_ORE_Pos (3U)
+#define USART_SR_ORE_Msk (0x1U << USART_SR_ORE_Pos) /*!< 0x00000008 */
+#define USART_SR_ORE USART_SR_ORE_Msk /*!< OverRun Error */
+#define USART_SR_IDLE_Pos (4U)
+#define USART_SR_IDLE_Msk (0x1U << USART_SR_IDLE_Pos) /*!< 0x00000010 */
+#define USART_SR_IDLE USART_SR_IDLE_Msk /*!< IDLE line detected */
+#define USART_SR_RXNE_Pos (5U)
+#define USART_SR_RXNE_Msk (0x1U << USART_SR_RXNE_Pos) /*!< 0x00000020 */
+#define USART_SR_RXNE USART_SR_RXNE_Msk /*!< Read Data Register Not Empty */
+#define USART_SR_TC_Pos (6U)
+#define USART_SR_TC_Msk (0x1U << USART_SR_TC_Pos) /*!< 0x00000040 */
+#define USART_SR_TC USART_SR_TC_Msk /*!< Transmission Complete */
+#define USART_SR_TXE_Pos (7U)
+#define USART_SR_TXE_Msk (0x1U << USART_SR_TXE_Pos) /*!< 0x00000080 */
+#define USART_SR_TXE USART_SR_TXE_Msk /*!< Transmit Data Register Empty */
+#define USART_SR_LBD_Pos (8U)
+#define USART_SR_LBD_Msk (0x1U << USART_SR_LBD_Pos) /*!< 0x00000100 */
+#define USART_SR_LBD USART_SR_LBD_Msk /*!< LIN Break Detection Flag */
+#define USART_SR_CTS_Pos (9U)
+#define USART_SR_CTS_Msk (0x1U << USART_SR_CTS_Pos) /*!< 0x00000200 */
+#define USART_SR_CTS USART_SR_CTS_Msk /*!< CTS Flag */
+
+/******************* Bit definition for USART_DR register *******************/
+#define USART_DR_DR_Pos (0U)
+#define USART_DR_DR_Msk (0x1FFU << USART_DR_DR_Pos) /*!< 0x000001FF */
+#define USART_DR_DR USART_DR_DR_Msk /*!< Data value */
+
+/****************** Bit definition for USART_BRR register *******************/
+#define USART_BRR_DIV_Fraction_Pos (0U)
+#define USART_BRR_DIV_Fraction_Msk (0xFU << USART_BRR_DIV_Fraction_Pos) /*!< 0x0000000F */
+#define USART_BRR_DIV_Fraction USART_BRR_DIV_Fraction_Msk /*!< Fraction of USARTDIV */
+#define USART_BRR_DIV_Mantissa_Pos (4U)
+#define USART_BRR_DIV_Mantissa_Msk (0xFFFU << USART_BRR_DIV_Mantissa_Pos) /*!< 0x0000FFF0 */
+#define USART_BRR_DIV_Mantissa USART_BRR_DIV_Mantissa_Msk /*!< Mantissa of USARTDIV */
+
+/****************** Bit definition for USART_CR1 register *******************/
+#define USART_CR1_SBK_Pos (0U)
+#define USART_CR1_SBK_Msk (0x1U << USART_CR1_SBK_Pos) /*!< 0x00000001 */
+#define USART_CR1_SBK USART_CR1_SBK_Msk /*!< Send Break */
+#define USART_CR1_RWU_Pos (1U)
+#define USART_CR1_RWU_Msk (0x1U << USART_CR1_RWU_Pos) /*!< 0x00000002 */
+#define USART_CR1_RWU USART_CR1_RWU_Msk /*!< Receiver wakeup */
+#define USART_CR1_RE_Pos (2U)
+#define USART_CR1_RE_Msk (0x1U << USART_CR1_RE_Pos) /*!< 0x00000004 */
+#define USART_CR1_RE USART_CR1_RE_Msk /*!< Receiver Enable */
+#define USART_CR1_TE_Pos (3U)
+#define USART_CR1_TE_Msk (0x1U << USART_CR1_TE_Pos) /*!< 0x00000008 */
+#define USART_CR1_TE USART_CR1_TE_Msk /*!< Transmitter Enable */
+#define USART_CR1_IDLEIE_Pos (4U)
+#define USART_CR1_IDLEIE_Msk (0x1U << USART_CR1_IDLEIE_Pos) /*!< 0x00000010 */
+#define USART_CR1_IDLEIE USART_CR1_IDLEIE_Msk /*!< IDLE Interrupt Enable */
+#define USART_CR1_RXNEIE_Pos (5U)
+#define USART_CR1_RXNEIE_Msk (0x1U << USART_CR1_RXNEIE_Pos) /*!< 0x00000020 */
+#define USART_CR1_RXNEIE USART_CR1_RXNEIE_Msk /*!< RXNE Interrupt Enable */
+#define USART_CR1_TCIE_Pos (6U)
+#define USART_CR1_TCIE_Msk (0x1U << USART_CR1_TCIE_Pos) /*!< 0x00000040 */
+#define USART_CR1_TCIE USART_CR1_TCIE_Msk /*!< Transmission Complete Interrupt Enable */
+#define USART_CR1_TXEIE_Pos (7U)
+#define USART_CR1_TXEIE_Msk (0x1U << USART_CR1_TXEIE_Pos) /*!< 0x00000080 */
+#define USART_CR1_TXEIE USART_CR1_TXEIE_Msk /*!< PE Interrupt Enable */
+#define USART_CR1_PEIE_Pos (8U)
+#define USART_CR1_PEIE_Msk (0x1U << USART_CR1_PEIE_Pos) /*!< 0x00000100 */
+#define USART_CR1_PEIE USART_CR1_PEIE_Msk /*!< PE Interrupt Enable */
+#define USART_CR1_PS_Pos (9U)
+#define USART_CR1_PS_Msk (0x1U << USART_CR1_PS_Pos) /*!< 0x00000200 */
+#define USART_CR1_PS USART_CR1_PS_Msk /*!< Parity Selection */
+#define USART_CR1_PCE_Pos (10U)
+#define USART_CR1_PCE_Msk (0x1U << USART_CR1_PCE_Pos) /*!< 0x00000400 */
+#define USART_CR1_PCE USART_CR1_PCE_Msk /*!< Parity Control Enable */
+#define USART_CR1_WAKE_Pos (11U)
+#define USART_CR1_WAKE_Msk (0x1U << USART_CR1_WAKE_Pos) /*!< 0x00000800 */
+#define USART_CR1_WAKE USART_CR1_WAKE_Msk /*!< Wakeup method */
+#define USART_CR1_M_Pos (12U)
+#define USART_CR1_M_Msk (0x1U << USART_CR1_M_Pos) /*!< 0x00001000 */
+#define USART_CR1_M USART_CR1_M_Msk /*!< Word length */
+#define USART_CR1_UE_Pos (13U)
+#define USART_CR1_UE_Msk (0x1U << USART_CR1_UE_Pos) /*!< 0x00002000 */
+#define USART_CR1_UE USART_CR1_UE_Msk /*!< USART Enable */
+
+/****************** Bit definition for USART_CR2 register *******************/
+#define USART_CR2_ADD_Pos (0U)
+#define USART_CR2_ADD_Msk (0xFU << USART_CR2_ADD_Pos) /*!< 0x0000000F */
+#define USART_CR2_ADD USART_CR2_ADD_Msk /*!< Address of the USART node */
+#define USART_CR2_LBDL_Pos (5U)
+#define USART_CR2_LBDL_Msk (0x1U << USART_CR2_LBDL_Pos) /*!< 0x00000020 */
+#define USART_CR2_LBDL USART_CR2_LBDL_Msk /*!< LIN Break Detection Length */
+#define USART_CR2_LBDIE_Pos (6U)
+#define USART_CR2_LBDIE_Msk (0x1U << USART_CR2_LBDIE_Pos) /*!< 0x00000040 */
+#define USART_CR2_LBDIE USART_CR2_LBDIE_Msk /*!< LIN Break Detection Interrupt Enable */
+#define USART_CR2_LBCL_Pos (8U)
+#define USART_CR2_LBCL_Msk (0x1U << USART_CR2_LBCL_Pos) /*!< 0x00000100 */
+#define USART_CR2_LBCL USART_CR2_LBCL_Msk /*!< Last Bit Clock pulse */
+#define USART_CR2_CPHA_Pos (9U)
+#define USART_CR2_CPHA_Msk (0x1U << USART_CR2_CPHA_Pos) /*!< 0x00000200 */
+#define USART_CR2_CPHA USART_CR2_CPHA_Msk /*!< Clock Phase */
+#define USART_CR2_CPOL_Pos (10U)
+#define USART_CR2_CPOL_Msk (0x1U << USART_CR2_CPOL_Pos) /*!< 0x00000400 */
+#define USART_CR2_CPOL USART_CR2_CPOL_Msk /*!< Clock Polarity */
+#define USART_CR2_CLKEN_Pos (11U)
+#define USART_CR2_CLKEN_Msk (0x1U << USART_CR2_CLKEN_Pos) /*!< 0x00000800 */
+#define USART_CR2_CLKEN USART_CR2_CLKEN_Msk /*!< Clock Enable */
+
+#define USART_CR2_STOP_Pos (12U)
+#define USART_CR2_STOP_Msk (0x3U << USART_CR2_STOP_Pos) /*!< 0x00003000 */
+#define USART_CR2_STOP USART_CR2_STOP_Msk /*!< STOP[1:0] bits (STOP bits) */
+#define USART_CR2_STOP_0 (0x1U << USART_CR2_STOP_Pos) /*!< 0x00001000 */
+#define USART_CR2_STOP_1 (0x2U << USART_CR2_STOP_Pos) /*!< 0x00002000 */
+
+#define USART_CR2_LINEN_Pos (14U)
+#define USART_CR2_LINEN_Msk (0x1U << USART_CR2_LINEN_Pos) /*!< 0x00004000 */
+#define USART_CR2_LINEN USART_CR2_LINEN_Msk /*!< LIN mode enable */
+
+/****************** Bit definition for USART_CR3 register *******************/
+#define USART_CR3_EIE_Pos (0U)
+#define USART_CR3_EIE_Msk (0x1U << USART_CR3_EIE_Pos) /*!< 0x00000001 */
+#define USART_CR3_EIE USART_CR3_EIE_Msk /*!< Error Interrupt Enable */
+#define USART_CR3_IREN_Pos (1U)
+#define USART_CR3_IREN_Msk (0x1U << USART_CR3_IREN_Pos) /*!< 0x00000002 */
+#define USART_CR3_IREN USART_CR3_IREN_Msk /*!< IrDA mode Enable */
+#define USART_CR3_IRLP_Pos (2U)
+#define USART_CR3_IRLP_Msk (0x1U << USART_CR3_IRLP_Pos) /*!< 0x00000004 */
+#define USART_CR3_IRLP USART_CR3_IRLP_Msk /*!< IrDA Low-Power */
+#define USART_CR3_HDSEL_Pos (3U)
+#define USART_CR3_HDSEL_Msk (0x1U << USART_CR3_HDSEL_Pos) /*!< 0x00000008 */
+#define USART_CR3_HDSEL USART_CR3_HDSEL_Msk /*!< Half-Duplex Selection */
+#define USART_CR3_NACK_Pos (4U)
+#define USART_CR3_NACK_Msk (0x1U << USART_CR3_NACK_Pos) /*!< 0x00000010 */
+#define USART_CR3_NACK USART_CR3_NACK_Msk /*!< Smartcard NACK enable */
+#define USART_CR3_SCEN_Pos (5U)
+#define USART_CR3_SCEN_Msk (0x1U << USART_CR3_SCEN_Pos) /*!< 0x00000020 */
+#define USART_CR3_SCEN USART_CR3_SCEN_Msk /*!< Smartcard mode enable */
+#define USART_CR3_DMAR_Pos (6U)
+#define USART_CR3_DMAR_Msk (0x1U << USART_CR3_DMAR_Pos) /*!< 0x00000040 */
+#define USART_CR3_DMAR USART_CR3_DMAR_Msk /*!< DMA Enable Receiver */
+#define USART_CR3_DMAT_Pos (7U)
+#define USART_CR3_DMAT_Msk (0x1U << USART_CR3_DMAT_Pos) /*!< 0x00000080 */
+#define USART_CR3_DMAT USART_CR3_DMAT_Msk /*!< DMA Enable Transmitter */
+#define USART_CR3_RTSE_Pos (8U)
+#define USART_CR3_RTSE_Msk (0x1U << USART_CR3_RTSE_Pos) /*!< 0x00000100 */
+#define USART_CR3_RTSE USART_CR3_RTSE_Msk /*!< RTS Enable */
+#define USART_CR3_CTSE_Pos (9U)
+#define USART_CR3_CTSE_Msk (0x1U << USART_CR3_CTSE_Pos) /*!< 0x00000200 */
+#define USART_CR3_CTSE USART_CR3_CTSE_Msk /*!< CTS Enable */
+#define USART_CR3_CTSIE_Pos (10U)
+#define USART_CR3_CTSIE_Msk (0x1U << USART_CR3_CTSIE_Pos) /*!< 0x00000400 */
+#define USART_CR3_CTSIE USART_CR3_CTSIE_Msk /*!< CTS Interrupt Enable */
+
+/****************** Bit definition for USART_GTPR register ******************/
+#define USART_GTPR_PSC_Pos (0U)
+#define USART_GTPR_PSC_Msk (0xFFU << USART_GTPR_PSC_Pos) /*!< 0x000000FF */
+#define USART_GTPR_PSC USART_GTPR_PSC_Msk /*!< PSC[7:0] bits (Prescaler value) */
+#define USART_GTPR_PSC_0 (0x01U << USART_GTPR_PSC_Pos) /*!< 0x00000001 */
+#define USART_GTPR_PSC_1 (0x02U << USART_GTPR_PSC_Pos) /*!< 0x00000002 */
+#define USART_GTPR_PSC_2 (0x04U << USART_GTPR_PSC_Pos) /*!< 0x00000004 */
+#define USART_GTPR_PSC_3 (0x08U << USART_GTPR_PSC_Pos) /*!< 0x00000008 */
+#define USART_GTPR_PSC_4 (0x10U << USART_GTPR_PSC_Pos) /*!< 0x00000010 */
+#define USART_GTPR_PSC_5 (0x20U << USART_GTPR_PSC_Pos) /*!< 0x00000020 */
+#define USART_GTPR_PSC_6 (0x40U << USART_GTPR_PSC_Pos) /*!< 0x00000040 */
+#define USART_GTPR_PSC_7 (0x80U << USART_GTPR_PSC_Pos) /*!< 0x00000080 */
+
+#define USART_GTPR_GT_Pos (8U)
+#define USART_GTPR_GT_Msk (0xFFU << USART_GTPR_GT_Pos) /*!< 0x0000FF00 */
+#define USART_GTPR_GT USART_GTPR_GT_Msk /*!< Guard time value */
+
+/******************************************************************************/
+/* */
+/* Debug MCU */
+/* */
+/******************************************************************************/
+
+/**************** Bit definition for DBGMCU_IDCODE register *****************/
+#define DBGMCU_IDCODE_DEV_ID_Pos (0U)
+#define DBGMCU_IDCODE_DEV_ID_Msk (0xFFFU << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */
+#define DBGMCU_IDCODE_DEV_ID DBGMCU_IDCODE_DEV_ID_Msk /*!< Device Identifier */
+
+#define DBGMCU_IDCODE_REV_ID_Pos (16U)
+#define DBGMCU_IDCODE_REV_ID_Msk (0xFFFFU << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */
+#define DBGMCU_IDCODE_REV_ID DBGMCU_IDCODE_REV_ID_Msk /*!< REV_ID[15:0] bits (Revision Identifier) */
+#define DBGMCU_IDCODE_REV_ID_0 (0x0001U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00010000 */
+#define DBGMCU_IDCODE_REV_ID_1 (0x0002U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00020000 */
+#define DBGMCU_IDCODE_REV_ID_2 (0x0004U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00040000 */
+#define DBGMCU_IDCODE_REV_ID_3 (0x0008U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00080000 */
+#define DBGMCU_IDCODE_REV_ID_4 (0x0010U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00100000 */
+#define DBGMCU_IDCODE_REV_ID_5 (0x0020U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00200000 */
+#define DBGMCU_IDCODE_REV_ID_6 (0x0040U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00400000 */
+#define DBGMCU_IDCODE_REV_ID_7 (0x0080U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00800000 */
+#define DBGMCU_IDCODE_REV_ID_8 (0x0100U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x01000000 */
+#define DBGMCU_IDCODE_REV_ID_9 (0x0200U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x02000000 */
+#define DBGMCU_IDCODE_REV_ID_10 (0x0400U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x04000000 */
+#define DBGMCU_IDCODE_REV_ID_11 (0x0800U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x08000000 */
+#define DBGMCU_IDCODE_REV_ID_12 (0x1000U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x10000000 */
+#define DBGMCU_IDCODE_REV_ID_13 (0x2000U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x20000000 */
+#define DBGMCU_IDCODE_REV_ID_14 (0x4000U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x40000000 */
+#define DBGMCU_IDCODE_REV_ID_15 (0x8000U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x80000000 */
+
+/****************** Bit definition for DBGMCU_CR register *******************/
+#define DBGMCU_CR_DBG_SLEEP_Pos (0U)
+#define DBGMCU_CR_DBG_SLEEP_Msk (0x1U << DBGMCU_CR_DBG_SLEEP_Pos) /*!< 0x00000001 */
+#define DBGMCU_CR_DBG_SLEEP DBGMCU_CR_DBG_SLEEP_Msk /*!< Debug Sleep Mode */
+#define DBGMCU_CR_DBG_STOP_Pos (1U)
+#define DBGMCU_CR_DBG_STOP_Msk (0x1U << DBGMCU_CR_DBG_STOP_Pos) /*!< 0x00000002 */
+#define DBGMCU_CR_DBG_STOP DBGMCU_CR_DBG_STOP_Msk /*!< Debug Stop Mode */
+#define DBGMCU_CR_DBG_STANDBY_Pos (2U)
+#define DBGMCU_CR_DBG_STANDBY_Msk (0x1U << DBGMCU_CR_DBG_STANDBY_Pos) /*!< 0x00000004 */
+#define DBGMCU_CR_DBG_STANDBY DBGMCU_CR_DBG_STANDBY_Msk /*!< Debug Standby mode */
+#define DBGMCU_CR_TRACE_IOEN_Pos (5U)
+#define DBGMCU_CR_TRACE_IOEN_Msk (0x1U << DBGMCU_CR_TRACE_IOEN_Pos) /*!< 0x00000020 */
+#define DBGMCU_CR_TRACE_IOEN DBGMCU_CR_TRACE_IOEN_Msk /*!< Trace Pin Assignment Control */
+
+#define DBGMCU_CR_TRACE_MODE_Pos (6U)
+#define DBGMCU_CR_TRACE_MODE_Msk (0x3U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x000000C0 */
+#define DBGMCU_CR_TRACE_MODE DBGMCU_CR_TRACE_MODE_Msk /*!< TRACE_MODE[1:0] bits (Trace Pin Assignment Control) */
+#define DBGMCU_CR_TRACE_MODE_0 (0x1U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000040 */
+#define DBGMCU_CR_TRACE_MODE_1 (0x2U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000080 */
+
+#define DBGMCU_CR_DBG_IWDG_STOP_Pos (8U)
+#define DBGMCU_CR_DBG_IWDG_STOP_Msk (0x1U << DBGMCU_CR_DBG_IWDG_STOP_Pos) /*!< 0x00000100 */
+#define DBGMCU_CR_DBG_IWDG_STOP DBGMCU_CR_DBG_IWDG_STOP_Msk /*!< Debug Independent Watchdog stopped when Core is halted */
+#define DBGMCU_CR_DBG_WWDG_STOP_Pos (9U)
+#define DBGMCU_CR_DBG_WWDG_STOP_Msk (0x1U << DBGMCU_CR_DBG_WWDG_STOP_Pos) /*!< 0x00000200 */
+#define DBGMCU_CR_DBG_WWDG_STOP DBGMCU_CR_DBG_WWDG_STOP_Msk /*!< Debug Window Watchdog stopped when Core is halted */
+#define DBGMCU_CR_DBG_TIM1_STOP_Pos (10U)
+#define DBGMCU_CR_DBG_TIM1_STOP_Msk (0x1U << DBGMCU_CR_DBG_TIM1_STOP_Pos) /*!< 0x00000400 */
+#define DBGMCU_CR_DBG_TIM1_STOP DBGMCU_CR_DBG_TIM1_STOP_Msk /*!< TIM1 counter stopped when core is halted */
+#define DBGMCU_CR_DBG_TIM2_STOP_Pos (11U)
+#define DBGMCU_CR_DBG_TIM2_STOP_Msk (0x1U << DBGMCU_CR_DBG_TIM2_STOP_Pos) /*!< 0x00000800 */
+#define DBGMCU_CR_DBG_TIM2_STOP DBGMCU_CR_DBG_TIM2_STOP_Msk /*!< TIM2 counter stopped when core is halted */
+#define DBGMCU_CR_DBG_TIM3_STOP_Pos (12U)
+#define DBGMCU_CR_DBG_TIM3_STOP_Msk (0x1U << DBGMCU_CR_DBG_TIM3_STOP_Pos) /*!< 0x00001000 */
+#define DBGMCU_CR_DBG_TIM3_STOP DBGMCU_CR_DBG_TIM3_STOP_Msk /*!< TIM3 counter stopped when core is halted */
+#define DBGMCU_CR_DBG_TIM4_STOP_Pos (13U)
+#define DBGMCU_CR_DBG_TIM4_STOP_Msk (0x1U << DBGMCU_CR_DBG_TIM4_STOP_Pos) /*!< 0x00002000 */
+#define DBGMCU_CR_DBG_TIM4_STOP DBGMCU_CR_DBG_TIM4_STOP_Msk /*!< TIM4 counter stopped when core is halted */
+#define DBGMCU_CR_DBG_CAN1_STOP_Pos (14U)
+#define DBGMCU_CR_DBG_CAN1_STOP_Msk (0x1U << DBGMCU_CR_DBG_CAN1_STOP_Pos) /*!< 0x00004000 */
+#define DBGMCU_CR_DBG_CAN1_STOP DBGMCU_CR_DBG_CAN1_STOP_Msk /*!< Debug CAN1 stopped when Core is halted */
+#define DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT_Pos (15U)
+#define DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT_Msk (0x1U << DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT_Pos) /*!< 0x00008000 */
+#define DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT_Msk /*!< SMBUS timeout mode stopped when Core is halted */
+#define DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT_Pos (16U)
+#define DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT_Msk (0x1U << DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT_Pos) /*!< 0x00010000 */
+#define DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT_Msk /*!< SMBUS timeout mode stopped when Core is halted */
+
+/******************************************************************************/
+/* */
+/* FLASH and Option Bytes Registers */
+/* */
+/******************************************************************************/
+/******************* Bit definition for FLASH_ACR register ******************/
+#define FLASH_ACR_LATENCY_Pos (0U)
+#define FLASH_ACR_LATENCY_Msk (0x7U << FLASH_ACR_LATENCY_Pos) /*!< 0x00000007 */
+#define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk /*!< LATENCY[2:0] bits (Latency) */
+#define FLASH_ACR_LATENCY_0 (0x1U << FLASH_ACR_LATENCY_Pos) /*!< 0x00000001 */
+#define FLASH_ACR_LATENCY_1 (0x2U << FLASH_ACR_LATENCY_Pos) /*!< 0x00000002 */
+#define FLASH_ACR_LATENCY_2 (0x4U << FLASH_ACR_LATENCY_Pos) /*!< 0x00000004 */
+
+#define FLASH_ACR_HLFCYA_Pos (3U)
+#define FLASH_ACR_HLFCYA_Msk (0x1U << FLASH_ACR_HLFCYA_Pos) /*!< 0x00000008 */
+#define FLASH_ACR_HLFCYA FLASH_ACR_HLFCYA_Msk /*!< Flash Half Cycle Access Enable */
+#define FLASH_ACR_PRFTBE_Pos (4U)
+#define FLASH_ACR_PRFTBE_Msk (0x1U << FLASH_ACR_PRFTBE_Pos) /*!< 0x00000010 */
+#define FLASH_ACR_PRFTBE FLASH_ACR_PRFTBE_Msk /*!< Prefetch Buffer Enable */
+#define FLASH_ACR_PRFTBS_Pos (5U)
+#define FLASH_ACR_PRFTBS_Msk (0x1U << FLASH_ACR_PRFTBS_Pos) /*!< 0x00000020 */
+#define FLASH_ACR_PRFTBS FLASH_ACR_PRFTBS_Msk /*!< Prefetch Buffer Status */
+
+/****************** Bit definition for FLASH_KEYR register ******************/
+#define FLASH_KEYR_FKEYR_Pos (0U)
+#define FLASH_KEYR_FKEYR_Msk (0xFFFFFFFFU << FLASH_KEYR_FKEYR_Pos) /*!< 0xFFFFFFFF */
+#define FLASH_KEYR_FKEYR FLASH_KEYR_FKEYR_Msk /*!< FPEC Key */
+
+#define RDP_KEY_Pos (0U)
+#define RDP_KEY_Msk (0xA5U << RDP_KEY_Pos) /*!< 0x000000A5 */
+#define RDP_KEY RDP_KEY_Msk /*!< RDP Key */
+#define FLASH_KEY1_Pos (0U)
+#define FLASH_KEY1_Msk (0x45670123U << FLASH_KEY1_Pos) /*!< 0x45670123 */
+#define FLASH_KEY1 FLASH_KEY1_Msk /*!< FPEC Key1 */
+#define FLASH_KEY2_Pos (0U)
+#define FLASH_KEY2_Msk (0xCDEF89ABU << FLASH_KEY2_Pos) /*!< 0xCDEF89AB */
+#define FLASH_KEY2 FLASH_KEY2_Msk /*!< FPEC Key2 */
+
+/***************** Bit definition for FLASH_OPTKEYR register ****************/
+#define FLASH_OPTKEYR_OPTKEYR_Pos (0U)
+#define FLASH_OPTKEYR_OPTKEYR_Msk (0xFFFFFFFFU << FLASH_OPTKEYR_OPTKEYR_Pos) /*!< 0xFFFFFFFF */
+#define FLASH_OPTKEYR_OPTKEYR FLASH_OPTKEYR_OPTKEYR_Msk /*!< Option Byte Key */
+
+#define FLASH_OPTKEY1 FLASH_KEY1 /*!< Option Byte Key1 */
+#define FLASH_OPTKEY2 FLASH_KEY2 /*!< Option Byte Key2 */
+
+/****************** Bit definition for FLASH_SR register ********************/
+#define FLASH_SR_BSY_Pos (0U)
+#define FLASH_SR_BSY_Msk (0x1U << FLASH_SR_BSY_Pos) /*!< 0x00000001 */
+#define FLASH_SR_BSY FLASH_SR_BSY_Msk /*!< Busy */
+#define FLASH_SR_PGERR_Pos (2U)
+#define FLASH_SR_PGERR_Msk (0x1U << FLASH_SR_PGERR_Pos) /*!< 0x00000004 */
+#define FLASH_SR_PGERR FLASH_SR_PGERR_Msk /*!< Programming Error */
+#define FLASH_SR_WRPRTERR_Pos (4U)
+#define FLASH_SR_WRPRTERR_Msk (0x1U << FLASH_SR_WRPRTERR_Pos) /*!< 0x00000010 */
+#define FLASH_SR_WRPRTERR FLASH_SR_WRPRTERR_Msk /*!< Write Protection Error */
+#define FLASH_SR_EOP_Pos (5U)
+#define FLASH_SR_EOP_Msk (0x1U << FLASH_SR_EOP_Pos) /*!< 0x00000020 */
+#define FLASH_SR_EOP FLASH_SR_EOP_Msk /*!< End of operation */
+
+/******************* Bit definition for FLASH_CR register *******************/
+#define FLASH_CR_PG_Pos (0U)
+#define FLASH_CR_PG_Msk (0x1U << FLASH_CR_PG_Pos) /*!< 0x00000001 */
+#define FLASH_CR_PG FLASH_CR_PG_Msk /*!< Programming */
+#define FLASH_CR_PER_Pos (1U)
+#define FLASH_CR_PER_Msk (0x1U << FLASH_CR_PER_Pos) /*!< 0x00000002 */
+#define FLASH_CR_PER FLASH_CR_PER_Msk /*!< Page Erase */
+#define FLASH_CR_MER_Pos (2U)
+#define FLASH_CR_MER_Msk (0x1U << FLASH_CR_MER_Pos) /*!< 0x00000004 */
+#define FLASH_CR_MER FLASH_CR_MER_Msk /*!< Mass Erase */
+#define FLASH_CR_OPTPG_Pos (4U)
+#define FLASH_CR_OPTPG_Msk (0x1U << FLASH_CR_OPTPG_Pos) /*!< 0x00000010 */
+#define FLASH_CR_OPTPG FLASH_CR_OPTPG_Msk /*!< Option Byte Programming */
+#define FLASH_CR_OPTER_Pos (5U)
+#define FLASH_CR_OPTER_Msk (0x1U << FLASH_CR_OPTER_Pos) /*!< 0x00000020 */
+#define FLASH_CR_OPTER FLASH_CR_OPTER_Msk /*!< Option Byte Erase */
+#define FLASH_CR_STRT_Pos (6U)
+#define FLASH_CR_STRT_Msk (0x1U << FLASH_CR_STRT_Pos) /*!< 0x00000040 */
+#define FLASH_CR_STRT FLASH_CR_STRT_Msk /*!< Start */
+#define FLASH_CR_LOCK_Pos (7U)
+#define FLASH_CR_LOCK_Msk (0x1U << FLASH_CR_LOCK_Pos) /*!< 0x00000080 */
+#define FLASH_CR_LOCK FLASH_CR_LOCK_Msk /*!< Lock */
+#define FLASH_CR_OPTWRE_Pos (9U)
+#define FLASH_CR_OPTWRE_Msk (0x1U << FLASH_CR_OPTWRE_Pos) /*!< 0x00000200 */
+#define FLASH_CR_OPTWRE FLASH_CR_OPTWRE_Msk /*!< Option Bytes Write Enable */
+#define FLASH_CR_ERRIE_Pos (10U)
+#define FLASH_CR_ERRIE_Msk (0x1U << FLASH_CR_ERRIE_Pos) /*!< 0x00000400 */
+#define FLASH_CR_ERRIE FLASH_CR_ERRIE_Msk /*!< Error Interrupt Enable */
+#define FLASH_CR_EOPIE_Pos (12U)
+#define FLASH_CR_EOPIE_Msk (0x1U << FLASH_CR_EOPIE_Pos) /*!< 0x00001000 */
+#define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk /*!< End of operation interrupt enable */
+
+/******************* Bit definition for FLASH_AR register *******************/
+#define FLASH_AR_FAR_Pos (0U)
+#define FLASH_AR_FAR_Msk (0xFFFFFFFFU << FLASH_AR_FAR_Pos) /*!< 0xFFFFFFFF */
+#define FLASH_AR_FAR FLASH_AR_FAR_Msk /*!< Flash Address */
+
+/****************** Bit definition for FLASH_OBR register *******************/
+#define FLASH_OBR_OPTERR_Pos (0U)
+#define FLASH_OBR_OPTERR_Msk (0x1U << FLASH_OBR_OPTERR_Pos) /*!< 0x00000001 */
+#define FLASH_OBR_OPTERR FLASH_OBR_OPTERR_Msk /*!< Option Byte Error */
+#define FLASH_OBR_RDPRT_Pos (1U)
+#define FLASH_OBR_RDPRT_Msk (0x1U << FLASH_OBR_RDPRT_Pos) /*!< 0x00000002 */
+#define FLASH_OBR_RDPRT FLASH_OBR_RDPRT_Msk /*!< Read protection */
+
+#define FLASH_OBR_IWDG_SW_Pos (2U)
+#define FLASH_OBR_IWDG_SW_Msk (0x1U << FLASH_OBR_IWDG_SW_Pos) /*!< 0x00000004 */
+#define FLASH_OBR_IWDG_SW FLASH_OBR_IWDG_SW_Msk /*!< IWDG SW */
+#define FLASH_OBR_nRST_STOP_Pos (3U)
+#define FLASH_OBR_nRST_STOP_Msk (0x1U << FLASH_OBR_nRST_STOP_Pos) /*!< 0x00000008 */
+#define FLASH_OBR_nRST_STOP FLASH_OBR_nRST_STOP_Msk /*!< nRST_STOP */
+#define FLASH_OBR_nRST_STDBY_Pos (4U)
+#define FLASH_OBR_nRST_STDBY_Msk (0x1U << FLASH_OBR_nRST_STDBY_Pos) /*!< 0x00000010 */
+#define FLASH_OBR_nRST_STDBY FLASH_OBR_nRST_STDBY_Msk /*!< nRST_STDBY */
+#define FLASH_OBR_USER_Pos (2U)
+#define FLASH_OBR_USER_Msk (0x7U << FLASH_OBR_USER_Pos) /*!< 0x0000001C */
+#define FLASH_OBR_USER FLASH_OBR_USER_Msk /*!< User Option Bytes */
+#define FLASH_OBR_DATA0_Pos (10U)
+#define FLASH_OBR_DATA0_Msk (0xFFU << FLASH_OBR_DATA0_Pos) /*!< 0x0003FC00 */
+#define FLASH_OBR_DATA0 FLASH_OBR_DATA0_Msk /*!< Data0 */
+#define FLASH_OBR_DATA1_Pos (18U)
+#define FLASH_OBR_DATA1_Msk (0xFFU << FLASH_OBR_DATA1_Pos) /*!< 0x03FC0000 */
+#define FLASH_OBR_DATA1 FLASH_OBR_DATA1_Msk /*!< Data1 */
+
+/****************** Bit definition for FLASH_WRPR register ******************/
+#define FLASH_WRPR_WRP_Pos (0U)
+#define FLASH_WRPR_WRP_Msk (0xFFFFFFFFU << FLASH_WRPR_WRP_Pos) /*!< 0xFFFFFFFF */
+#define FLASH_WRPR_WRP FLASH_WRPR_WRP_Msk /*!< Write Protect */
+
+/*----------------------------------------------------------------------------*/
+
+/****************** Bit definition for FLASH_RDP register *******************/
+#define FLASH_RDP_RDP_Pos (0U)
+#define FLASH_RDP_RDP_Msk (0xFFU << FLASH_RDP_RDP_Pos) /*!< 0x000000FF */
+#define FLASH_RDP_RDP FLASH_RDP_RDP_Msk /*!< Read protection option byte */
+#define FLASH_RDP_nRDP_Pos (8U)
+#define FLASH_RDP_nRDP_Msk (0xFFU << FLASH_RDP_nRDP_Pos) /*!< 0x0000FF00 */
+#define FLASH_RDP_nRDP FLASH_RDP_nRDP_Msk /*!< Read protection complemented option byte */
+
+/****************** Bit definition for FLASH_USER register ******************/
+#define FLASH_USER_USER_Pos (16U)
+#define FLASH_USER_USER_Msk (0xFFU << FLASH_USER_USER_Pos) /*!< 0x00FF0000 */
+#define FLASH_USER_USER FLASH_USER_USER_Msk /*!< User option byte */
+#define FLASH_USER_nUSER_Pos (24U)
+#define FLASH_USER_nUSER_Msk (0xFFU << FLASH_USER_nUSER_Pos) /*!< 0xFF000000 */
+#define FLASH_USER_nUSER FLASH_USER_nUSER_Msk /*!< User complemented option byte */
+
+/****************** Bit definition for FLASH_Data0 register *****************/
+#define FLASH_DATA0_DATA0_Pos (0U)
+#define FLASH_DATA0_DATA0_Msk (0xFFU << FLASH_DATA0_DATA0_Pos) /*!< 0x000000FF */
+#define FLASH_DATA0_DATA0 FLASH_DATA0_DATA0_Msk /*!< User data storage option byte */
+#define FLASH_DATA0_nDATA0_Pos (8U)
+#define FLASH_DATA0_nDATA0_Msk (0xFFU << FLASH_DATA0_nDATA0_Pos) /*!< 0x0000FF00 */
+#define FLASH_DATA0_nDATA0 FLASH_DATA0_nDATA0_Msk /*!< User data storage complemented option byte */
+
+/****************** Bit definition for FLASH_Data1 register *****************/
+#define FLASH_DATA1_DATA1_Pos (16U)
+#define FLASH_DATA1_DATA1_Msk (0xFFU << FLASH_DATA1_DATA1_Pos) /*!< 0x00FF0000 */
+#define FLASH_DATA1_DATA1 FLASH_DATA1_DATA1_Msk /*!< User data storage option byte */
+#define FLASH_DATA1_nDATA1_Pos (24U)
+#define FLASH_DATA1_nDATA1_Msk (0xFFU << FLASH_DATA1_nDATA1_Pos) /*!< 0xFF000000 */
+#define FLASH_DATA1_nDATA1 FLASH_DATA1_nDATA1_Msk /*!< User data storage complemented option byte */
+
+/****************** Bit definition for FLASH_WRP0 register ******************/
+#define FLASH_WRP0_WRP0_Pos (0U)
+#define FLASH_WRP0_WRP0_Msk (0xFFU << FLASH_WRP0_WRP0_Pos) /*!< 0x000000FF */
+#define FLASH_WRP0_WRP0 FLASH_WRP0_WRP0_Msk /*!< Flash memory write protection option bytes */
+#define FLASH_WRP0_nWRP0_Pos (8U)
+#define FLASH_WRP0_nWRP0_Msk (0xFFU << FLASH_WRP0_nWRP0_Pos) /*!< 0x0000FF00 */
+#define FLASH_WRP0_nWRP0 FLASH_WRP0_nWRP0_Msk /*!< Flash memory write protection complemented option bytes */
+
+/****************** Bit definition for FLASH_WRP1 register ******************/
+#define FLASH_WRP1_WRP1_Pos (16U)
+#define FLASH_WRP1_WRP1_Msk (0xFFU << FLASH_WRP1_WRP1_Pos) /*!< 0x00FF0000 */
+#define FLASH_WRP1_WRP1 FLASH_WRP1_WRP1_Msk /*!< Flash memory write protection option bytes */
+#define FLASH_WRP1_nWRP1_Pos (24U)
+#define FLASH_WRP1_nWRP1_Msk (0xFFU << FLASH_WRP1_nWRP1_Pos) /*!< 0xFF000000 */
+#define FLASH_WRP1_nWRP1 FLASH_WRP1_nWRP1_Msk /*!< Flash memory write protection complemented option bytes */
+
+/****************** Bit definition for FLASH_WRP2 register ******************/
+#define FLASH_WRP2_WRP2_Pos (0U)
+#define FLASH_WRP2_WRP2_Msk (0xFFU << FLASH_WRP2_WRP2_Pos) /*!< 0x000000FF */
+#define FLASH_WRP2_WRP2 FLASH_WRP2_WRP2_Msk /*!< Flash memory write protection option bytes */
+#define FLASH_WRP2_nWRP2_Pos (8U)
+#define FLASH_WRP2_nWRP2_Msk (0xFFU << FLASH_WRP2_nWRP2_Pos) /*!< 0x0000FF00 */
+#define FLASH_WRP2_nWRP2 FLASH_WRP2_nWRP2_Msk /*!< Flash memory write protection complemented option bytes */
+
+/****************** Bit definition for FLASH_WRP3 register ******************/
+#define FLASH_WRP3_WRP3_Pos (16U)
+#define FLASH_WRP3_WRP3_Msk (0xFFU << FLASH_WRP3_WRP3_Pos) /*!< 0x00FF0000 */
+#define FLASH_WRP3_WRP3 FLASH_WRP3_WRP3_Msk /*!< Flash memory write protection option bytes */
+#define FLASH_WRP3_nWRP3_Pos (24U)
+#define FLASH_WRP3_nWRP3_Msk (0xFFU << FLASH_WRP3_nWRP3_Pos) /*!< 0xFF000000 */
+#define FLASH_WRP3_nWRP3 FLASH_WRP3_nWRP3_Msk /*!< Flash memory write protection complemented option bytes */
+
+
+
+/**
+ * @}
+*/
+
+/**
+ * @}
+*/
+
+/** @addtogroup Exported_macro
+ * @{
+ */
+
+/****************************** ADC Instances *********************************/
+#define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) || \
+ ((INSTANCE) == ADC2))
+
+#define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC12_COMMON)
+
+#define IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
+
+#define IS_ADC_DMA_CAPABILITY_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
+
+/****************************** CAN Instances *********************************/
+#define IS_CAN_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CAN1)
+
+/****************************** CRC Instances *********************************/
+#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
+
+/****************************** DAC Instances *********************************/
+
+/****************************** DMA Instances *********************************/
+#define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \
+ ((INSTANCE) == DMA1_Channel2) || \
+ ((INSTANCE) == DMA1_Channel3) || \
+ ((INSTANCE) == DMA1_Channel4) || \
+ ((INSTANCE) == DMA1_Channel5) || \
+ ((INSTANCE) == DMA1_Channel6) || \
+ ((INSTANCE) == DMA1_Channel7))
+
+/******************************* GPIO Instances *******************************/
+#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
+ ((INSTANCE) == GPIOB) || \
+ ((INSTANCE) == GPIOC) || \
+ ((INSTANCE) == GPIOD) || \
+ ((INSTANCE) == GPIOE))
+
+/**************************** GPIO Alternate Function Instances ***************/
+#define IS_GPIO_AF_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
+
+/**************************** GPIO Lock Instances *****************************/
+#define IS_GPIO_LOCK_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
+
+/******************************** I2C Instances *******************************/
+#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
+ ((INSTANCE) == I2C2))
+
+/****************************** IWDG Instances ********************************/
+#define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
+
+/******************************** SPI Instances *******************************/
+#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
+ ((INSTANCE) == SPI2))
+
+/****************************** START TIM Instances ***************************/
+/****************************** TIM Instances *********************************/
+#define IS_TIM_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4))
+
+#define IS_TIM_CC1_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4))
+
+#define IS_TIM_CC2_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4))
+
+#define IS_TIM_CC3_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4))
+
+#define IS_TIM_CC4_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4))
+
+#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4))
+
+#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4))
+
+#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4))
+
+#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4))
+
+#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4))
+
+#define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4))
+
+#define IS_TIM_XOR_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4))
+
+#define IS_TIM_MASTER_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4))
+
+#define IS_TIM_SLAVE_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4))
+
+#define IS_TIM_DMABURST_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4))
+
+#define IS_TIM_BREAK_INSTANCE(INSTANCE)\
+ ((INSTANCE) == TIM1)
+
+#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
+ ((((INSTANCE) == TIM1) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM2) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM3) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM4) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))))
+
+#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
+ (((INSTANCE) == TIM1) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3)))
+
+#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4))
+
+#define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE)\
+ ((INSTANCE) == TIM1)
+
+#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4))
+
+#define IS_TIM_DMA_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4))
+
+#define IS_TIM_DMA_CC_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4))
+
+#define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE)\
+ ((INSTANCE) == TIM1)
+
+/****************************** END TIM Instances *****************************/
+
+
+/******************** USART Instances : Synchronous mode **********************/
+#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3))
+
+/******************** UART Instances : Asynchronous mode **********************/
+#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3))
+
+/******************** UART Instances : Half-Duplex mode **********************/
+#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3))
+
+/******************** UART Instances : LIN mode **********************/
+#define IS_UART_LIN_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3))
+
+/****************** UART Instances : Hardware Flow control ********************/
+#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3))
+
+/********************* UART Instances : Smard card mode ***********************/
+#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3))
+
+/*********************** UART Instances : IRDA mode ***************************/
+#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3))
+
+/***************** UART Instances : Multi-Processor mode **********************/
+#define IS_UART_MULTIPROCESSOR_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3))
+
+/***************** UART Instances : DMA mode available **********************/
+#define IS_UART_DMA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3))
+
+/****************************** RTC Instances *********************************/
+#define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
+
+/**************************** WWDG Instances *****************************/
+#define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
+
+/****************************** USB Instances ********************************/
+#define IS_USB_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB)
+
+
+
+
+/**
+ * @}
+*/
+/******************************************************************************/
+/* For a painless codes migration between the STM32F1xx device product */
+/* lines, the aliases defined below are put in place to overcome the */
+/* differences in the interrupt handlers and IRQn definitions. */
+/* No need to update developed interrupt code when moving across */
+/* product lines within the same STM32F1 Family */
+/******************************************************************************/
+
+/* Aliases for __IRQn */
+#define ADC1_IRQn ADC1_2_IRQn
+#define TIM1_BRK_TIM15_IRQn TIM1_BRK_IRQn
+#define TIM1_BRK_TIM9_IRQn TIM1_BRK_IRQn
+#define TIM9_IRQn TIM1_BRK_IRQn
+#define TIM1_TRG_COM_TIM11_IRQn TIM1_TRG_COM_IRQn
+#define TIM1_TRG_COM_TIM17_IRQn TIM1_TRG_COM_IRQn
+#define TIM11_IRQn TIM1_TRG_COM_IRQn
+#define TIM10_IRQn TIM1_UP_IRQn
+#define TIM1_UP_TIM16_IRQn TIM1_UP_IRQn
+#define TIM1_UP_TIM10_IRQn TIM1_UP_IRQn
+#define CEC_IRQn USBWakeUp_IRQn
+#define OTG_FS_WKUP_IRQn USBWakeUp_IRQn
+#define CAN1_TX_IRQn USB_HP_CAN1_TX_IRQn
+#define USB_HP_IRQn USB_HP_CAN1_TX_IRQn
+#define USB_LP_IRQn USB_LP_CAN1_RX0_IRQn
+#define CAN1_RX0_IRQn USB_LP_CAN1_RX0_IRQn
+
+
+/* Aliases for __IRQHandler */
+#define ADC1_IRQHandler ADC1_2_IRQHandler
+#define TIM1_BRK_TIM15_IRQHandler TIM1_BRK_IRQHandler
+#define TIM1_BRK_TIM9_IRQHandler TIM1_BRK_IRQHandler
+#define TIM9_IRQHandler TIM1_BRK_IRQHandler
+#define TIM1_TRG_COM_TIM11_IRQHandler TIM1_TRG_COM_IRQHandler
+#define TIM1_TRG_COM_TIM17_IRQHandler TIM1_TRG_COM_IRQHandler
+#define TIM11_IRQHandler TIM1_TRG_COM_IRQHandler
+#define TIM10_IRQHandler TIM1_UP_IRQHandler
+#define TIM1_UP_TIM16_IRQHandler TIM1_UP_IRQHandler
+#define TIM1_UP_TIM10_IRQHandler TIM1_UP_IRQHandler
+#define CEC_IRQHandler USBWakeUp_IRQHandler
+#define OTG_FS_WKUP_IRQHandler USBWakeUp_IRQHandler
+#define CAN1_TX_IRQHandler USB_HP_CAN1_TX_IRQHandler
+#define USB_HP_IRQHandler USB_HP_CAN1_TX_IRQHandler
+#define USB_LP_IRQHandler USB_LP_CAN1_RX0_IRQHandler
+#define CAN1_RX0_IRQHandler USB_LP_CAN1_RX0_IRQHandler
+
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+
+#ifdef __cplusplus
+ }
+#endif /* __cplusplus */
+
+#endif /* __STM32F103xB_H */
+
+
+
+ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Device/ST/STM32F1xx/Include/stm32f103xe.h b/Device/ST/STM32F1xx/Include/stm32f103xe.h
new file mode 100644
index 0000000..464e82c
--- /dev/null
+++ b/Device/ST/STM32F1xx/Include/stm32f103xe.h
@@ -0,0 +1,12199 @@
+/**
+ ******************************************************************************
+ * @file stm32f103xe.h
+ * @author MCD Application Team
+ * @version V4.1.0
+ * @date 29-April-2016
+ * @brief CMSIS Cortex-M3 Device Peripheral Access Layer Header File.
+ * This file contains all the peripheral register's definitions, bits
+ * definitions and memory mapping for STM32F1xx devices.
+ *
+ * This file contains:
+ * - Data structures and the address mapping for all peripherals
+ * - Peripheral's registers declarations and bits definition
+ * - Macros to access peripheral’s registers hardware
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+
+/** @addtogroup CMSIS
+ * @{
+ */
+
+/** @addtogroup stm32f103xe
+ * @{
+ */
+
+#ifndef __STM32F103xE_H
+#define __STM32F103xE_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/** @addtogroup Configuration_section_for_CMSIS
+ * @{
+ */
+/**
+ * @brief Configuration of the Cortex-M3 Processor and Core Peripherals
+ */
+ #define __MPU_PRESENT 0 /*!< Other STM32 devices does not provide an MPU */
+#define __CM3_REV 0x0200 /*!< Core Revision r2p0 */
+#define __NVIC_PRIO_BITS 4 /*!< STM32 uses 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
+
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_interrupt_number_definition
+ * @{
+ */
+
+/**
+ * @brief STM32F10x Interrupt Number Definition, according to the selected device
+ * in @ref Library_configuration_section
+ */
+
+ /*!< Interrupt Number Definition */
+typedef enum
+{
+/****** Cortex-M3 Processor Exceptions Numbers ***************************************************/
+ NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
+ HardFault_IRQn = -13, /*!< 3 Cortex-M3 Hard Fault Interrupt */
+ MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */
+ BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */
+ UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */
+ SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */
+ DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */
+ PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */
+ SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */
+
+/****** STM32 specific Interrupt Numbers *********************************************************/
+ WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
+ PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */
+ TAMPER_IRQn = 2, /*!< Tamper Interrupt */
+ RTC_IRQn = 3, /*!< RTC global Interrupt */
+ FLASH_IRQn = 4, /*!< FLASH global Interrupt */
+ RCC_IRQn = 5, /*!< RCC global Interrupt */
+ EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */
+ EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */
+ EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */
+ EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */
+ EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */
+ DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 global Interrupt */
+ DMA1_Channel2_IRQn = 12, /*!< DMA1 Channel 2 global Interrupt */
+ DMA1_Channel3_IRQn = 13, /*!< DMA1 Channel 3 global Interrupt */
+ DMA1_Channel4_IRQn = 14, /*!< DMA1 Channel 4 global Interrupt */
+ DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 global Interrupt */
+ DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 global Interrupt */
+ DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 global Interrupt */
+ ADC1_2_IRQn = 18, /*!< ADC1 and ADC2 global Interrupt */
+ USB_HP_CAN1_TX_IRQn = 19, /*!< USB Device High Priority or CAN1 TX Interrupts */
+ USB_LP_CAN1_RX0_IRQn = 20, /*!< USB Device Low Priority or CAN1 RX0 Interrupts */
+ CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */
+ CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */
+ EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
+ TIM1_BRK_IRQn = 24, /*!< TIM1 Break Interrupt */
+ TIM1_UP_IRQn = 25, /*!< TIM1 Update Interrupt */
+ TIM1_TRG_COM_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt */
+ TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
+ TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
+ TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
+ TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
+ I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
+ I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
+ I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
+ I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
+ SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
+ SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
+ USART1_IRQn = 37, /*!< USART1 global Interrupt */
+ USART2_IRQn = 38, /*!< USART2 global Interrupt */
+ USART3_IRQn = 39, /*!< USART3 global Interrupt */
+ EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
+ RTC_Alarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */
+ USBWakeUp_IRQn = 42, /*!< USB Device WakeUp from suspend through EXTI Line Interrupt */
+ TIM8_BRK_IRQn = 43, /*!< TIM8 Break Interrupt */
+ TIM8_UP_IRQn = 44, /*!< TIM8 Update Interrupt */
+ TIM8_TRG_COM_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt */
+ TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */
+ ADC3_IRQn = 47, /*!< ADC3 global Interrupt */
+ FSMC_IRQn = 48, /*!< FSMC global Interrupt */
+ SDIO_IRQn = 49, /*!< SDIO global Interrupt */
+ TIM5_IRQn = 50, /*!< TIM5 global Interrupt */
+ SPI3_IRQn = 51, /*!< SPI3 global Interrupt */
+ UART4_IRQn = 52, /*!< UART4 global Interrupt */
+ UART5_IRQn = 53, /*!< UART5 global Interrupt */
+ TIM6_IRQn = 54, /*!< TIM6 global Interrupt */
+ TIM7_IRQn = 55, /*!< TIM7 global Interrupt */
+ DMA2_Channel1_IRQn = 56, /*!< DMA2 Channel 1 global Interrupt */
+ DMA2_Channel2_IRQn = 57, /*!< DMA2 Channel 2 global Interrupt */
+ DMA2_Channel3_IRQn = 58, /*!< DMA2 Channel 3 global Interrupt */
+ DMA2_Channel4_5_IRQn = 59, /*!< DMA2 Channel 4 and Channel 5 global Interrupt */
+} IRQn_Type;
+
+
+/**
+ * @}
+ */
+
+#include "core_cm3.h"
+#include "system_stm32f1xx.h"
+#include <stdint.h>
+
+/** @addtogroup Peripheral_registers_structures
+ * @{
+ */
+
+/**
+ * @brief Analog to Digital Converter
+ */
+
+typedef struct
+{
+ __IO uint32_t SR;
+ __IO uint32_t CR1;
+ __IO uint32_t CR2;
+ __IO uint32_t SMPR1;
+ __IO uint32_t SMPR2;
+ __IO uint32_t JOFR1;
+ __IO uint32_t JOFR2;
+ __IO uint32_t JOFR3;
+ __IO uint32_t JOFR4;
+ __IO uint32_t HTR;
+ __IO uint32_t LTR;
+ __IO uint32_t SQR1;
+ __IO uint32_t SQR2;
+ __IO uint32_t SQR3;
+ __IO uint32_t JSQR;
+ __IO uint32_t JDR1;
+ __IO uint32_t JDR2;
+ __IO uint32_t JDR3;
+ __IO uint32_t JDR4;
+ __IO uint32_t DR;
+} ADC_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t SR; /*!< ADC status register, used for ADC multimode (bits common to several ADC instances). Address offset: ADC1 base address */
+ __IO uint32_t CR1; /*!< ADC control register 1, used for ADC multimode (bits common to several ADC instances). Address offset: ADC1 base address + 0x04 */
+ __IO uint32_t CR2; /*!< ADC control register 2, used for ADC multimode (bits common to several ADC instances). Address offset: ADC1 base address + 0x08 */
+ uint32_t RESERVED[16];
+ __IO uint32_t DR; /*!< ADC data register, used for ADC multimode (bits common to several ADC instances). Address offset: ADC1 base address + 0x4C */
+} ADC_Common_TypeDef;
+
+/**
+ * @brief Backup Registers
+ */
+
+typedef struct
+{
+ uint32_t RESERVED0;
+ __IO uint32_t DR1;
+ __IO uint32_t DR2;
+ __IO uint32_t DR3;
+ __IO uint32_t DR4;
+ __IO uint32_t DR5;
+ __IO uint32_t DR6;
+ __IO uint32_t DR7;
+ __IO uint32_t DR8;
+ __IO uint32_t DR9;
+ __IO uint32_t DR10;
+ __IO uint32_t RTCCR;
+ __IO uint32_t CR;
+ __IO uint32_t CSR;
+ uint32_t RESERVED13[2];
+ __IO uint32_t DR11;
+ __IO uint32_t DR12;
+ __IO uint32_t DR13;
+ __IO uint32_t DR14;
+ __IO uint32_t DR15;
+ __IO uint32_t DR16;
+ __IO uint32_t DR17;
+ __IO uint32_t DR18;
+ __IO uint32_t DR19;
+ __IO uint32_t DR20;
+ __IO uint32_t DR21;
+ __IO uint32_t DR22;
+ __IO uint32_t DR23;
+ __IO uint32_t DR24;
+ __IO uint32_t DR25;
+ __IO uint32_t DR26;
+ __IO uint32_t DR27;
+ __IO uint32_t DR28;
+ __IO uint32_t DR29;
+ __IO uint32_t DR30;
+ __IO uint32_t DR31;
+ __IO uint32_t DR32;
+ __IO uint32_t DR33;
+ __IO uint32_t DR34;
+ __IO uint32_t DR35;
+ __IO uint32_t DR36;
+ __IO uint32_t DR37;
+ __IO uint32_t DR38;
+ __IO uint32_t DR39;
+ __IO uint32_t DR40;
+ __IO uint32_t DR41;
+ __IO uint32_t DR42;
+} BKP_TypeDef;
+
+/**
+ * @brief Controller Area Network TxMailBox
+ */
+
+typedef struct
+{
+ __IO uint32_t TIR;
+ __IO uint32_t TDTR;
+ __IO uint32_t TDLR;
+ __IO uint32_t TDHR;
+} CAN_TxMailBox_TypeDef;
+
+/**
+ * @brief Controller Area Network FIFOMailBox
+ */
+
+typedef struct
+{
+ __IO uint32_t RIR;
+ __IO uint32_t RDTR;
+ __IO uint32_t RDLR;
+ __IO uint32_t RDHR;
+} CAN_FIFOMailBox_TypeDef;
+
+/**
+ * @brief Controller Area Network FilterRegister
+ */
+
+typedef struct
+{
+ __IO uint32_t FR1;
+ __IO uint32_t FR2;
+} CAN_FilterRegister_TypeDef;
+
+/**
+ * @brief Controller Area Network
+ */
+
+typedef struct
+{
+ __IO uint32_t MCR;
+ __IO uint32_t MSR;
+ __IO uint32_t TSR;
+ __IO uint32_t RF0R;
+ __IO uint32_t RF1R;
+ __IO uint32_t IER;
+ __IO uint32_t ESR;
+ __IO uint32_t BTR;
+ uint32_t RESERVED0[88];
+ CAN_TxMailBox_TypeDef sTxMailBox[3];
+ CAN_FIFOMailBox_TypeDef sFIFOMailBox[2];
+ uint32_t RESERVED1[12];
+ __IO uint32_t FMR;
+ __IO uint32_t FM1R;
+ uint32_t RESERVED2;
+ __IO uint32_t FS1R;
+ uint32_t RESERVED3;
+ __IO uint32_t FFA1R;
+ uint32_t RESERVED4;
+ __IO uint32_t FA1R;
+ uint32_t RESERVED5[8];
+ CAN_FilterRegister_TypeDef sFilterRegister[14];
+} CAN_TypeDef;
+
+/**
+ * @brief CRC calculation unit
+ */
+
+typedef struct
+{
+ __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
+ __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
+ uint8_t RESERVED0; /*!< Reserved, Address offset: 0x05 */
+ uint16_t RESERVED1; /*!< Reserved, Address offset: 0x06 */
+ __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
+} CRC_TypeDef;
+
+/**
+ * @brief Digital to Analog Converter
+ */
+
+typedef struct
+{
+ __IO uint32_t CR;
+ __IO uint32_t SWTRIGR;
+ __IO uint32_t DHR12R1;
+ __IO uint32_t DHR12L1;
+ __IO uint32_t DHR8R1;
+ __IO uint32_t DHR12R2;
+ __IO uint32_t DHR12L2;
+ __IO uint32_t DHR8R2;
+ __IO uint32_t DHR12RD;
+ __IO uint32_t DHR12LD;
+ __IO uint32_t DHR8RD;
+ __IO uint32_t DOR1;
+ __IO uint32_t DOR2;
+} DAC_TypeDef;
+
+/**
+ * @brief Debug MCU
+ */
+
+typedef struct
+{
+ __IO uint32_t IDCODE;
+ __IO uint32_t CR;
+}DBGMCU_TypeDef;
+
+/**
+ * @brief DMA Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t CCR;
+ __IO uint32_t CNDTR;
+ __IO uint32_t CPAR;
+ __IO uint32_t CMAR;
+} DMA_Channel_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t ISR;
+ __IO uint32_t IFCR;
+} DMA_TypeDef;
+
+
+
+/**
+ * @brief External Interrupt/Event Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t IMR;
+ __IO uint32_t EMR;
+ __IO uint32_t RTSR;
+ __IO uint32_t FTSR;
+ __IO uint32_t SWIER;
+ __IO uint32_t PR;
+} EXTI_TypeDef;
+
+/**
+ * @brief FLASH Registers
+ */
+
+typedef struct
+{
+ __IO uint32_t ACR;
+ __IO uint32_t KEYR;
+ __IO uint32_t OPTKEYR;
+ __IO uint32_t SR;
+ __IO uint32_t CR;
+ __IO uint32_t AR;
+ __IO uint32_t RESERVED;
+ __IO uint32_t OBR;
+ __IO uint32_t WRPR;
+} FLASH_TypeDef;
+
+/**
+ * @brief Option Bytes Registers
+ */
+
+typedef struct
+{
+ __IO uint16_t RDP;
+ __IO uint16_t USER;
+ __IO uint16_t Data0;
+ __IO uint16_t Data1;
+ __IO uint16_t WRP0;
+ __IO uint16_t WRP1;
+ __IO uint16_t WRP2;
+ __IO uint16_t WRP3;
+} OB_TypeDef;
+
+/**
+ * @brief Flexible Static Memory Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t BTCR[8];
+} FSMC_Bank1_TypeDef;
+
+/**
+ * @brief Flexible Static Memory Controller Bank1E
+ */
+
+typedef struct
+{
+ __IO uint32_t BWTR[7];
+} FSMC_Bank1E_TypeDef;
+
+/**
+ * @brief Flexible Static Memory Controller Bank2
+ */
+
+typedef struct
+{
+ __IO uint32_t PCR2; /*!< NAND Flash control register 2, Address offset: 0x60 */
+ __IO uint32_t SR2; /*!< NAND Flash FIFO status and interrupt register 2, Address offset: 0x64 */
+ __IO uint32_t PMEM2; /*!< NAND Flash Common memory space timing register 2, Address offset: 0x68 */
+ __IO uint32_t PATT2; /*!< NAND Flash Attribute memory space timing register 2, Address offset: 0x6C */
+ uint32_t RESERVED0; /*!< Reserved, 0x70 */
+ __IO uint32_t ECCR2; /*!< NAND Flash ECC result registers 2, Address offset: 0x74 */
+ uint32_t RESERVED1; /*!< Reserved, 0x78 */
+ uint32_t RESERVED2; /*!< Reserved, 0x7C */
+ __IO uint32_t PCR3; /*!< NAND Flash control register 3, Address offset: 0x80 */
+ __IO uint32_t SR3; /*!< NAND Flash FIFO status and interrupt register 3, Address offset: 0x84 */
+ __IO uint32_t PMEM3; /*!< NAND Flash Common memory space timing register 3, Address offset: 0x88 */
+ __IO uint32_t PATT3; /*!< NAND Flash Attribute memory space timing register 3, Address offset: 0x8C */
+ uint32_t RESERVED3; /*!< Reserved, 0x90 */
+ __IO uint32_t ECCR3; /*!< NAND Flash ECC result registers 3, Address offset: 0x94 */
+} FSMC_Bank2_3_TypeDef;
+
+/**
+ * @brief Flexible Static Memory Controller Bank4
+ */
+
+typedef struct
+{
+ __IO uint32_t PCR4;
+ __IO uint32_t SR4;
+ __IO uint32_t PMEM4;
+ __IO uint32_t PATT4;
+ __IO uint32_t PIO4;
+} FSMC_Bank4_TypeDef;
+
+/**
+ * @brief General Purpose I/O
+ */
+
+typedef struct
+{
+ __IO uint32_t CRL;
+ __IO uint32_t CRH;
+ __IO uint32_t IDR;
+ __IO uint32_t ODR;
+ __IO uint32_t BSRR;
+ __IO uint32_t BRR;
+ __IO uint32_t LCKR;
+} GPIO_TypeDef;
+
+/**
+ * @brief Alternate Function I/O
+ */
+
+typedef struct
+{
+ __IO uint32_t EVCR;
+ __IO uint32_t MAPR;
+ __IO uint32_t EXTICR[4];
+ uint32_t RESERVED0;
+ __IO uint32_t MAPR2;
+} AFIO_TypeDef;
+/**
+ * @brief Inter Integrated Circuit Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t CR1;
+ __IO uint32_t CR2;
+ __IO uint32_t OAR1;
+ __IO uint32_t OAR2;
+ __IO uint32_t DR;
+ __IO uint32_t SR1;
+ __IO uint32_t SR2;
+ __IO uint32_t CCR;
+ __IO uint32_t TRISE;
+} I2C_TypeDef;
+
+/**
+ * @brief Independent WATCHDOG
+ */
+
+typedef struct
+{
+ __IO uint32_t KR; /*!< Key register, Address offset: 0x00 */
+ __IO uint32_t PR; /*!< Prescaler register, Address offset: 0x04 */
+ __IO uint32_t RLR; /*!< Reload register, Address offset: 0x08 */
+ __IO uint32_t SR; /*!< Status register, Address offset: 0x0C */
+} IWDG_TypeDef;
+
+/**
+ * @brief Power Control
+ */
+
+typedef struct
+{
+ __IO uint32_t CR;
+ __IO uint32_t CSR;
+} PWR_TypeDef;
+
+/**
+ * @brief Reset and Clock Control
+ */
+
+typedef struct
+{
+ __IO uint32_t CR;
+ __IO uint32_t CFGR;
+ __IO uint32_t CIR;
+ __IO uint32_t APB2RSTR;
+ __IO uint32_t APB1RSTR;
+ __IO uint32_t AHBENR;
+ __IO uint32_t APB2ENR;
+ __IO uint32_t APB1ENR;
+ __IO uint32_t BDCR;
+ __IO uint32_t CSR;
+
+
+} RCC_TypeDef;
+
+/**
+ * @brief Real-Time Clock
+ */
+
+typedef struct
+{
+ __IO uint32_t CRH;
+ __IO uint32_t CRL;
+ __IO uint32_t PRLH;
+ __IO uint32_t PRLL;
+ __IO uint32_t DIVH;
+ __IO uint32_t DIVL;
+ __IO uint32_t CNTH;
+ __IO uint32_t CNTL;
+ __IO uint32_t ALRH;
+ __IO uint32_t ALRL;
+} RTC_TypeDef;
+
+/**
+ * @brief SD host Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t POWER;
+ __IO uint32_t CLKCR;
+ __IO uint32_t ARG;
+ __IO uint32_t CMD;
+ __I uint32_t RESPCMD;
+ __I uint32_t RESP1;
+ __I uint32_t RESP2;
+ __I uint32_t RESP3;
+ __I uint32_t RESP4;
+ __IO uint32_t DTIMER;
+ __IO uint32_t DLEN;
+ __IO uint32_t DCTRL;
+ __I uint32_t DCOUNT;
+ __I uint32_t STA;
+ __IO uint32_t ICR;
+ __IO uint32_t MASK;
+ uint32_t RESERVED0[2];
+ __I uint32_t FIFOCNT;
+ uint32_t RESERVED1[13];
+ __IO uint32_t FIFO;
+} SDIO_TypeDef;
+
+/**
+ * @brief Serial Peripheral Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t CR1;
+ __IO uint32_t CR2;
+ __IO uint32_t SR;
+ __IO uint32_t DR;
+ __IO uint32_t CRCPR;
+ __IO uint32_t RXCRCR;
+ __IO uint32_t TXCRCR;
+ __IO uint32_t I2SCFGR;
+ __IO uint32_t I2SPR;
+} SPI_TypeDef;
+
+/**
+ * @brief TIM Timers
+ */
+typedef struct
+{
+ __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
+ __IO uint32_t SMCR; /*!< TIM slave Mode Control register, Address offset: 0x08 */
+ __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
+ __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
+ __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
+ __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
+ __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
+ __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
+ __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
+ __IO uint32_t PSC; /*!< TIM prescaler register, Address offset: 0x28 */
+ __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
+ __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */
+ __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
+ __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
+ __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
+ __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
+ __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
+ __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
+ __IO uint32_t DMAR; /*!< TIM DMA address for full transfer register, Address offset: 0x4C */
+ __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */
+}TIM_TypeDef;
+
+
+/**
+ * @brief Universal Synchronous Asynchronous Receiver Transmitter
+ */
+
+typedef struct
+{
+ __IO uint32_t SR; /*!< USART Status register, Address offset: 0x00 */
+ __IO uint32_t DR; /*!< USART Data register, Address offset: 0x04 */
+ __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x08 */
+ __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x0C */
+ __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x10 */
+ __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x14 */
+ __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x18 */
+} USART_TypeDef;
+
+/**
+ * @brief Universal Serial Bus Full Speed Device
+ */
+
+typedef struct
+{
+ __IO uint16_t EP0R; /*!< USB Endpoint 0 register, Address offset: 0x00 */
+ __IO uint16_t RESERVED0; /*!< Reserved */
+ __IO uint16_t EP1R; /*!< USB Endpoint 1 register, Address offset: 0x04 */
+ __IO uint16_t RESERVED1; /*!< Reserved */
+ __IO uint16_t EP2R; /*!< USB Endpoint 2 register, Address offset: 0x08 */
+ __IO uint16_t RESERVED2; /*!< Reserved */
+ __IO uint16_t EP3R; /*!< USB Endpoint 3 register, Address offset: 0x0C */
+ __IO uint16_t RESERVED3; /*!< Reserved */
+ __IO uint16_t EP4R; /*!< USB Endpoint 4 register, Address offset: 0x10 */
+ __IO uint16_t RESERVED4; /*!< Reserved */
+ __IO uint16_t EP5R; /*!< USB Endpoint 5 register, Address offset: 0x14 */
+ __IO uint16_t RESERVED5; /*!< Reserved */
+ __IO uint16_t EP6R; /*!< USB Endpoint 6 register, Address offset: 0x18 */
+ __IO uint16_t RESERVED6; /*!< Reserved */
+ __IO uint16_t EP7R; /*!< USB Endpoint 7 register, Address offset: 0x1C */
+ __IO uint16_t RESERVED7[17]; /*!< Reserved */
+ __IO uint16_t CNTR; /*!< Control register, Address offset: 0x40 */
+ __IO uint16_t RESERVED8; /*!< Reserved */
+ __IO uint16_t ISTR; /*!< Interrupt status register, Address offset: 0x44 */
+ __IO uint16_t RESERVED9; /*!< Reserved */
+ __IO uint16_t FNR; /*!< Frame number register, Address offset: 0x48 */
+ __IO uint16_t RESERVEDA; /*!< Reserved */
+ __IO uint16_t DADDR; /*!< Device address register, Address offset: 0x4C */
+ __IO uint16_t RESERVEDB; /*!< Reserved */
+ __IO uint16_t BTABLE; /*!< Buffer Table address register, Address offset: 0x50 */
+ __IO uint16_t RESERVEDC; /*!< Reserved */
+} USB_TypeDef;
+
+
+/**
+ * @brief Window WATCHDOG
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
+ __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
+ __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
+} WWDG_TypeDef;
+
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_memory_map
+ * @{
+ */
+
+
+#define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH base address in the alias region */
+#define FLASH_BANK1_END ((uint32_t)0x0807FFFF) /*!< FLASH END address of bank1 */
+#define SRAM_BASE ((uint32_t)0x20000000) /*!< SRAM base address in the alias region */
+#define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */
+
+#define SRAM_BB_BASE ((uint32_t)0x22000000) /*!< SRAM base address in the bit-band region */
+#define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */
+
+#define FSMC_BASE ((uint32_t)0x60000000) /*!< FSMC base address */
+#define FSMC_R_BASE ((uint32_t)0xA0000000) /*!< FSMC registers base address */
+
+/*!< Peripheral memory map */
+#define APB1PERIPH_BASE PERIPH_BASE
+#define APB2PERIPH_BASE (PERIPH_BASE + 0x10000)
+#define AHBPERIPH_BASE (PERIPH_BASE + 0x20000)
+
+#define TIM2_BASE (APB1PERIPH_BASE + 0x0000)
+#define TIM3_BASE (APB1PERIPH_BASE + 0x0400)
+#define TIM4_BASE (APB1PERIPH_BASE + 0x0800)
+#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00)
+#define TIM6_BASE (APB1PERIPH_BASE + 0x1000)
+#define TIM7_BASE (APB1PERIPH_BASE + 0x1400)
+#define RTC_BASE (APB1PERIPH_BASE + 0x2800)
+#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00)
+#define IWDG_BASE (APB1PERIPH_BASE + 0x3000)
+#define SPI2_BASE (APB1PERIPH_BASE + 0x3800)
+#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00)
+#define USART2_BASE (APB1PERIPH_BASE + 0x4400)
+#define USART3_BASE (APB1PERIPH_BASE + 0x4800)
+#define UART4_BASE (APB1PERIPH_BASE + 0x4C00)
+#define UART5_BASE (APB1PERIPH_BASE + 0x5000)
+#define I2C1_BASE (APB1PERIPH_BASE + 0x5400)
+#define I2C2_BASE (APB1PERIPH_BASE + 0x5800)
+#define CAN1_BASE (APB1PERIPH_BASE + 0x6400)
+#define BKP_BASE (APB1PERIPH_BASE + 0x6C00)
+#define PWR_BASE (APB1PERIPH_BASE + 0x7000)
+#define DAC_BASE (APB1PERIPH_BASE + 0x7400)
+#define AFIO_BASE (APB2PERIPH_BASE + 0x0000)
+#define EXTI_BASE (APB2PERIPH_BASE + 0x0400)
+#define GPIOA_BASE (APB2PERIPH_BASE + 0x0800)
+#define GPIOB_BASE (APB2PERIPH_BASE + 0x0C00)
+#define GPIOC_BASE (APB2PERIPH_BASE + 0x1000)
+#define GPIOD_BASE (APB2PERIPH_BASE + 0x1400)
+#define GPIOE_BASE (APB2PERIPH_BASE + 0x1800)
+#define GPIOF_BASE (APB2PERIPH_BASE + 0x1C00)
+#define GPIOG_BASE (APB2PERIPH_BASE + 0x2000)
+#define ADC1_BASE (APB2PERIPH_BASE + 0x2400)
+#define ADC2_BASE (APB2PERIPH_BASE + 0x2800)
+#define TIM1_BASE (APB2PERIPH_BASE + 0x2C00)
+#define SPI1_BASE (APB2PERIPH_BASE + 0x3000)
+#define TIM8_BASE (APB2PERIPH_BASE + 0x3400)
+#define USART1_BASE (APB2PERIPH_BASE + 0x3800)
+#define ADC3_BASE (APB2PERIPH_BASE + 0x3C00)
+
+#define SDIO_BASE (PERIPH_BASE + 0x18000)
+
+#define DMA1_BASE (AHBPERIPH_BASE + 0x0000)
+#define DMA1_Channel1_BASE (AHBPERIPH_BASE + 0x0008)
+#define DMA1_Channel2_BASE (AHBPERIPH_BASE + 0x001C)
+#define DMA1_Channel3_BASE (AHBPERIPH_BASE + 0x0030)
+#define DMA1_Channel4_BASE (AHBPERIPH_BASE + 0x0044)
+#define DMA1_Channel5_BASE (AHBPERIPH_BASE + 0x0058)
+#define DMA1_Channel6_BASE (AHBPERIPH_BASE + 0x006C)
+#define DMA1_Channel7_BASE (AHBPERIPH_BASE + 0x0080)
+#define DMA2_BASE (AHBPERIPH_BASE + 0x0400)
+#define DMA2_Channel1_BASE (AHBPERIPH_BASE + 0x0408)
+#define DMA2_Channel2_BASE (AHBPERIPH_BASE + 0x041C)
+#define DMA2_Channel3_BASE (AHBPERIPH_BASE + 0x0430)
+#define DMA2_Channel4_BASE (AHBPERIPH_BASE + 0x0444)
+#define DMA2_Channel5_BASE (AHBPERIPH_BASE + 0x0458)
+#define RCC_BASE (AHBPERIPH_BASE + 0x1000)
+#define CRC_BASE (AHBPERIPH_BASE + 0x3000)
+
+#define FLASH_R_BASE (AHBPERIPH_BASE + 0x2000) /*!< Flash registers base address */
+#define FLASHSIZE_BASE ((uint32_t)0x1FFFF7E0) /*!< FLASH Size register base address */
+#define UID_BASE ((uint32_t)0x1FFFF7E8) /*!< Unique device ID register base address */
+#define OB_BASE ((uint32_t)0x1FFFF800) /*!< Flash Option Bytes base address */
+
+
+#define FSMC_BANK1 (FSMC_BASE) /*!< FSMC Bank1 base address */
+#define FSMC_BANK1_1 (FSMC_BANK1) /*!< FSMC Bank1_1 base address */
+#define FSMC_BANK1_2 (FSMC_BANK1 + 0x04000000) /*!< FSMC Bank1_2 base address */
+#define FSMC_BANK1_3 (FSMC_BANK1 + 0x08000000) /*!< FSMC Bank1_3 base address */
+#define FSMC_BANK1_4 (FSMC_BANK1 + 0x0C000000) /*!< FSMC Bank1_4 base address */
+
+#define FSMC_BANK2 (FSMC_BASE + 0x10000000) /*!< FSMC Bank2 base address */
+#define FSMC_BANK3 (FSMC_BASE + 0x20000000) /*!< FSMC Bank3 base address */
+#define FSMC_BANK4 (FSMC_BASE + 0x30000000) /*!< FSMC Bank4 base address */
+
+#define FSMC_BANK1_R_BASE (FSMC_R_BASE + 0x0000) /*!< FSMC Bank1 registers base address */
+#define FSMC_BANK1E_R_BASE (FSMC_R_BASE + 0x0104) /*!< FSMC Bank1E registers base address */
+#define FSMC_BANK2_3_R_BASE (FSMC_R_BASE + 0x0060) /*!< FSMC Bank2/Bank3 registers base address */
+#define FSMC_BANK4_R_BASE (FSMC_R_BASE + 0x00A0) /*!< FSMC Bank4 registers base address */
+
+#define DBGMCU_BASE ((uint32_t)0xE0042000) /*!< Debug MCU registers base address */
+
+/* USB device FS */
+#define USB_BASE (APB1PERIPH_BASE + 0x00005C00) /*!< USB_IP Peripheral Registers base address */
+#define USB_PMAADDR (APB1PERIPH_BASE + 0x00006000) /*!< USB_IP Packet Memory Area base address */
+
+
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_declaration
+ * @{
+ */
+
+#define TIM2 ((TIM_TypeDef *) TIM2_BASE)
+#define TIM3 ((TIM_TypeDef *) TIM3_BASE)
+#define TIM4 ((TIM_TypeDef *) TIM4_BASE)
+#define TIM5 ((TIM_TypeDef *) TIM5_BASE)
+#define TIM6 ((TIM_TypeDef *) TIM6_BASE)
+#define TIM7 ((TIM_TypeDef *) TIM7_BASE)
+#define RTC ((RTC_TypeDef *) RTC_BASE)
+#define WWDG ((WWDG_TypeDef *) WWDG_BASE)
+#define IWDG ((IWDG_TypeDef *) IWDG_BASE)
+#define SPI2 ((SPI_TypeDef *) SPI2_BASE)
+#define SPI3 ((SPI_TypeDef *) SPI3_BASE)
+#define USART2 ((USART_TypeDef *) USART2_BASE)
+#define USART3 ((USART_TypeDef *) USART3_BASE)
+#define UART4 ((USART_TypeDef *) UART4_BASE)
+#define UART5 ((USART_TypeDef *) UART5_BASE)
+#define I2C1 ((I2C_TypeDef *) I2C1_BASE)
+#define I2C2 ((I2C_TypeDef *) I2C2_BASE)
+#define USB ((USB_TypeDef *) USB_BASE)
+#define CAN1 ((CAN_TypeDef *) CAN1_BASE)
+#define BKP ((BKP_TypeDef *) BKP_BASE)
+#define PWR ((PWR_TypeDef *) PWR_BASE)
+#define DAC ((DAC_TypeDef *) DAC_BASE)
+#define AFIO ((AFIO_TypeDef *) AFIO_BASE)
+#define EXTI ((EXTI_TypeDef *) EXTI_BASE)
+#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
+#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
+#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
+#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
+#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
+#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
+#define GPIOG ((GPIO_TypeDef *) GPIOG_BASE)
+#define ADC1 ((ADC_TypeDef *) ADC1_BASE)
+#define ADC2 ((ADC_TypeDef *) ADC2_BASE)
+#define ADC3 ((ADC_TypeDef *) ADC3_BASE)
+#define ADC12_COMMON ((ADC_Common_TypeDef *) ADC1_BASE)
+#define TIM1 ((TIM_TypeDef *) TIM1_BASE)
+#define SPI1 ((SPI_TypeDef *) SPI1_BASE)
+#define TIM8 ((TIM_TypeDef *) TIM8_BASE)
+#define USART1 ((USART_TypeDef *) USART1_BASE)
+#define SDIO ((SDIO_TypeDef *) SDIO_BASE)
+#define DMA1 ((DMA_TypeDef *) DMA1_BASE)
+#define DMA2 ((DMA_TypeDef *) DMA2_BASE)
+#define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
+#define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
+#define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
+#define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
+#define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
+#define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
+#define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
+#define DMA2_Channel1 ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE)
+#define DMA2_Channel2 ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE)
+#define DMA2_Channel3 ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE)
+#define DMA2_Channel4 ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE)
+#define DMA2_Channel5 ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE)
+#define RCC ((RCC_TypeDef *) RCC_BASE)
+#define CRC ((CRC_TypeDef *) CRC_BASE)
+#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
+#define OB ((OB_TypeDef *) OB_BASE)
+#define FSMC_Bank1 ((FSMC_Bank1_TypeDef *) FSMC_BANK1_R_BASE)
+#define FSMC_Bank1E ((FSMC_Bank1E_TypeDef *) FSMC_BANK1E_R_BASE)
+#define FSMC_Bank2_3 ((FSMC_Bank2_3_TypeDef *) FSMC_BANK2_3_R_BASE)
+#define FSMC_Bank4 ((FSMC_Bank4_TypeDef *) FSMC_BANK4_R_BASE)
+#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
+
+
+/**
+ * @}
+ */
+
+/** @addtogroup Exported_constants
+ * @{
+ */
+
+ /** @addtogroup Peripheral_Registers_Bits_Definition
+ * @{
+ */
+
+/******************************************************************************/
+/* Peripheral Registers_Bits_Definition */
+/******************************************************************************/
+
+/******************************************************************************/
+/* */
+/* CRC calculation unit (CRC) */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for CRC_DR register *********************/
+#define CRC_DR_DR_Pos (0U)
+#define CRC_DR_DR_Msk (0xFFFFFFFFU << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */
+#define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */
+
+/******************* Bit definition for CRC_IDR register ********************/
+#define CRC_IDR_IDR_Pos (0U)
+#define CRC_IDR_IDR_Msk (0xFFU << CRC_IDR_IDR_Pos) /*!< 0x000000FF */
+#define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 8-bit data register bits */
+
+/******************** Bit definition for CRC_CR register ********************/
+#define CRC_CR_RESET_Pos (0U)
+#define CRC_CR_RESET_Msk (0x1U << CRC_CR_RESET_Pos) /*!< 0x00000001 */
+#define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET bit */
+
+/******************************************************************************/
+/* */
+/* Power Control */
+/* */
+/******************************************************************************/
+
+/******************** Bit definition for PWR_CR register ********************/
+#define PWR_CR_LPDS_Pos (0U)
+#define PWR_CR_LPDS_Msk (0x1U << PWR_CR_LPDS_Pos) /*!< 0x00000001 */
+#define PWR_CR_LPDS PWR_CR_LPDS_Msk /*!< Low-Power Deepsleep */
+#define PWR_CR_PDDS_Pos (1U)
+#define PWR_CR_PDDS_Msk (0x1U << PWR_CR_PDDS_Pos) /*!< 0x00000002 */
+#define PWR_CR_PDDS PWR_CR_PDDS_Msk /*!< Power Down Deepsleep */
+#define PWR_CR_CWUF_Pos (2U)
+#define PWR_CR_CWUF_Msk (0x1U << PWR_CR_CWUF_Pos) /*!< 0x00000004 */
+#define PWR_CR_CWUF PWR_CR_CWUF_Msk /*!< Clear Wakeup Flag */
+#define PWR_CR_CSBF_Pos (3U)
+#define PWR_CR_CSBF_Msk (0x1U << PWR_CR_CSBF_Pos) /*!< 0x00000008 */
+#define PWR_CR_CSBF PWR_CR_CSBF_Msk /*!< Clear Standby Flag */
+#define PWR_CR_PVDE_Pos (4U)
+#define PWR_CR_PVDE_Msk (0x1U << PWR_CR_PVDE_Pos) /*!< 0x00000010 */
+#define PWR_CR_PVDE PWR_CR_PVDE_Msk /*!< Power Voltage Detector Enable */
+
+#define PWR_CR_PLS_Pos (5U)
+#define PWR_CR_PLS_Msk (0x7U << PWR_CR_PLS_Pos) /*!< 0x000000E0 */
+#define PWR_CR_PLS PWR_CR_PLS_Msk /*!< PLS[2:0] bits (PVD Level Selection) */
+#define PWR_CR_PLS_0 (0x1U << PWR_CR_PLS_Pos) /*!< 0x00000020 */
+#define PWR_CR_PLS_1 (0x2U << PWR_CR_PLS_Pos) /*!< 0x00000040 */
+#define PWR_CR_PLS_2 (0x4U << PWR_CR_PLS_Pos) /*!< 0x00000080 */
+
+/*!< PVD level configuration */
+#define PWR_CR_PLS_2V2 ((uint32_t)0x00000000) /*!< PVD level 2.2V */
+#define PWR_CR_PLS_2V3 ((uint32_t)0x00000020) /*!< PVD level 2.3V */
+#define PWR_CR_PLS_2V4 ((uint32_t)0x00000040) /*!< PVD level 2.4V */
+#define PWR_CR_PLS_2V5 ((uint32_t)0x00000060) /*!< PVD level 2.5V */
+#define PWR_CR_PLS_2V6 ((uint32_t)0x00000080) /*!< PVD level 2.6V */
+#define PWR_CR_PLS_2V7 ((uint32_t)0x000000A0) /*!< PVD level 2.7V */
+#define PWR_CR_PLS_2V8 ((uint32_t)0x000000C0) /*!< PVD level 2.8V */
+#define PWR_CR_PLS_2V9 ((uint32_t)0x000000E0) /*!< PVD level 2.9V */
+
+#define PWR_CR_DBP_Pos (8U)
+#define PWR_CR_DBP_Msk (0x1U << PWR_CR_DBP_Pos) /*!< 0x00000100 */
+#define PWR_CR_DBP PWR_CR_DBP_Msk /*!< Disable Backup Domain write protection */
+
+
+/******************* Bit definition for PWR_CSR register ********************/
+#define PWR_CSR_WUF_Pos (0U)
+#define PWR_CSR_WUF_Msk (0x1U << PWR_CSR_WUF_Pos) /*!< 0x00000001 */
+#define PWR_CSR_WUF PWR_CSR_WUF_Msk /*!< Wakeup Flag */
+#define PWR_CSR_SBF_Pos (1U)
+#define PWR_CSR_SBF_Msk (0x1U << PWR_CSR_SBF_Pos) /*!< 0x00000002 */
+#define PWR_CSR_SBF PWR_CSR_SBF_Msk /*!< Standby Flag */
+#define PWR_CSR_PVDO_Pos (2U)
+#define PWR_CSR_PVDO_Msk (0x1U << PWR_CSR_PVDO_Pos) /*!< 0x00000004 */
+#define PWR_CSR_PVDO PWR_CSR_PVDO_Msk /*!< PVD Output */
+#define PWR_CSR_EWUP_Pos (8U)
+#define PWR_CSR_EWUP_Msk (0x1U << PWR_CSR_EWUP_Pos) /*!< 0x00000100 */
+#define PWR_CSR_EWUP PWR_CSR_EWUP_Msk /*!< Enable WKUP pin */
+
+/******************************************************************************/
+/* */
+/* Backup registers */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for BKP_DR1 register ********************/
+#define BKP_DR1_D_Pos (0U)
+#define BKP_DR1_D_Msk (0xFFFFU << BKP_DR1_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR1_D BKP_DR1_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR2 register ********************/
+#define BKP_DR2_D_Pos (0U)
+#define BKP_DR2_D_Msk (0xFFFFU << BKP_DR2_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR2_D BKP_DR2_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR3 register ********************/
+#define BKP_DR3_D_Pos (0U)
+#define BKP_DR3_D_Msk (0xFFFFU << BKP_DR3_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR3_D BKP_DR3_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR4 register ********************/
+#define BKP_DR4_D_Pos (0U)
+#define BKP_DR4_D_Msk (0xFFFFU << BKP_DR4_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR4_D BKP_DR4_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR5 register ********************/
+#define BKP_DR5_D_Pos (0U)
+#define BKP_DR5_D_Msk (0xFFFFU << BKP_DR5_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR5_D BKP_DR5_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR6 register ********************/
+#define BKP_DR6_D_Pos (0U)
+#define BKP_DR6_D_Msk (0xFFFFU << BKP_DR6_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR6_D BKP_DR6_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR7 register ********************/
+#define BKP_DR7_D_Pos (0U)
+#define BKP_DR7_D_Msk (0xFFFFU << BKP_DR7_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR7_D BKP_DR7_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR8 register ********************/
+#define BKP_DR8_D_Pos (0U)
+#define BKP_DR8_D_Msk (0xFFFFU << BKP_DR8_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR8_D BKP_DR8_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR9 register ********************/
+#define BKP_DR9_D_Pos (0U)
+#define BKP_DR9_D_Msk (0xFFFFU << BKP_DR9_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR9_D BKP_DR9_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR10 register *******************/
+#define BKP_DR10_D_Pos (0U)
+#define BKP_DR10_D_Msk (0xFFFFU << BKP_DR10_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR10_D BKP_DR10_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR11 register *******************/
+#define BKP_DR11_D_Pos (0U)
+#define BKP_DR11_D_Msk (0xFFFFU << BKP_DR11_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR11_D BKP_DR11_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR12 register *******************/
+#define BKP_DR12_D_Pos (0U)
+#define BKP_DR12_D_Msk (0xFFFFU << BKP_DR12_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR12_D BKP_DR12_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR13 register *******************/
+#define BKP_DR13_D_Pos (0U)
+#define BKP_DR13_D_Msk (0xFFFFU << BKP_DR13_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR13_D BKP_DR13_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR14 register *******************/
+#define BKP_DR14_D_Pos (0U)
+#define BKP_DR14_D_Msk (0xFFFFU << BKP_DR14_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR14_D BKP_DR14_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR15 register *******************/
+#define BKP_DR15_D_Pos (0U)
+#define BKP_DR15_D_Msk (0xFFFFU << BKP_DR15_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR15_D BKP_DR15_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR16 register *******************/
+#define BKP_DR16_D_Pos (0U)
+#define BKP_DR16_D_Msk (0xFFFFU << BKP_DR16_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR16_D BKP_DR16_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR17 register *******************/
+#define BKP_DR17_D_Pos (0U)
+#define BKP_DR17_D_Msk (0xFFFFU << BKP_DR17_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR17_D BKP_DR17_D_Msk /*!< Backup data */
+
+/****************** Bit definition for BKP_DR18 register ********************/
+#define BKP_DR18_D_Pos (0U)
+#define BKP_DR18_D_Msk (0xFFFFU << BKP_DR18_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR18_D BKP_DR18_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR19 register *******************/
+#define BKP_DR19_D_Pos (0U)
+#define BKP_DR19_D_Msk (0xFFFFU << BKP_DR19_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR19_D BKP_DR19_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR20 register *******************/
+#define BKP_DR20_D_Pos (0U)
+#define BKP_DR20_D_Msk (0xFFFFU << BKP_DR20_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR20_D BKP_DR20_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR21 register *******************/
+#define BKP_DR21_D_Pos (0U)
+#define BKP_DR21_D_Msk (0xFFFFU << BKP_DR21_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR21_D BKP_DR21_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR22 register *******************/
+#define BKP_DR22_D_Pos (0U)
+#define BKP_DR22_D_Msk (0xFFFFU << BKP_DR22_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR22_D BKP_DR22_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR23 register *******************/
+#define BKP_DR23_D_Pos (0U)
+#define BKP_DR23_D_Msk (0xFFFFU << BKP_DR23_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR23_D BKP_DR23_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR24 register *******************/
+#define BKP_DR24_D_Pos (0U)
+#define BKP_DR24_D_Msk (0xFFFFU << BKP_DR24_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR24_D BKP_DR24_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR25 register *******************/
+#define BKP_DR25_D_Pos (0U)
+#define BKP_DR25_D_Msk (0xFFFFU << BKP_DR25_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR25_D BKP_DR25_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR26 register *******************/
+#define BKP_DR26_D_Pos (0U)
+#define BKP_DR26_D_Msk (0xFFFFU << BKP_DR26_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR26_D BKP_DR26_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR27 register *******************/
+#define BKP_DR27_D_Pos (0U)
+#define BKP_DR27_D_Msk (0xFFFFU << BKP_DR27_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR27_D BKP_DR27_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR28 register *******************/
+#define BKP_DR28_D_Pos (0U)
+#define BKP_DR28_D_Msk (0xFFFFU << BKP_DR28_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR28_D BKP_DR28_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR29 register *******************/
+#define BKP_DR29_D_Pos (0U)
+#define BKP_DR29_D_Msk (0xFFFFU << BKP_DR29_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR29_D BKP_DR29_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR30 register *******************/
+#define BKP_DR30_D_Pos (0U)
+#define BKP_DR30_D_Msk (0xFFFFU << BKP_DR30_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR30_D BKP_DR30_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR31 register *******************/
+#define BKP_DR31_D_Pos (0U)
+#define BKP_DR31_D_Msk (0xFFFFU << BKP_DR31_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR31_D BKP_DR31_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR32 register *******************/
+#define BKP_DR32_D_Pos (0U)
+#define BKP_DR32_D_Msk (0xFFFFU << BKP_DR32_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR32_D BKP_DR32_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR33 register *******************/
+#define BKP_DR33_D_Pos (0U)
+#define BKP_DR33_D_Msk (0xFFFFU << BKP_DR33_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR33_D BKP_DR33_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR34 register *******************/
+#define BKP_DR34_D_Pos (0U)
+#define BKP_DR34_D_Msk (0xFFFFU << BKP_DR34_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR34_D BKP_DR34_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR35 register *******************/
+#define BKP_DR35_D_Pos (0U)
+#define BKP_DR35_D_Msk (0xFFFFU << BKP_DR35_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR35_D BKP_DR35_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR36 register *******************/
+#define BKP_DR36_D_Pos (0U)
+#define BKP_DR36_D_Msk (0xFFFFU << BKP_DR36_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR36_D BKP_DR36_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR37 register *******************/
+#define BKP_DR37_D_Pos (0U)
+#define BKP_DR37_D_Msk (0xFFFFU << BKP_DR37_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR37_D BKP_DR37_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR38 register *******************/
+#define BKP_DR38_D_Pos (0U)
+#define BKP_DR38_D_Msk (0xFFFFU << BKP_DR38_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR38_D BKP_DR38_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR39 register *******************/
+#define BKP_DR39_D_Pos (0U)
+#define BKP_DR39_D_Msk (0xFFFFU << BKP_DR39_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR39_D BKP_DR39_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR40 register *******************/
+#define BKP_DR40_D_Pos (0U)
+#define BKP_DR40_D_Msk (0xFFFFU << BKP_DR40_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR40_D BKP_DR40_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR41 register *******************/
+#define BKP_DR41_D_Pos (0U)
+#define BKP_DR41_D_Msk (0xFFFFU << BKP_DR41_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR41_D BKP_DR41_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR42 register *******************/
+#define BKP_DR42_D_Pos (0U)
+#define BKP_DR42_D_Msk (0xFFFFU << BKP_DR42_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR42_D BKP_DR42_D_Msk /*!< Backup data */
+
+#define RTC_BKP_NUMBER 42
+
+/****************** Bit definition for BKP_RTCCR register *******************/
+#define BKP_RTCCR_CAL_Pos (0U)
+#define BKP_RTCCR_CAL_Msk (0x7FU << BKP_RTCCR_CAL_Pos) /*!< 0x0000007F */
+#define BKP_RTCCR_CAL BKP_RTCCR_CAL_Msk /*!< Calibration value */
+#define BKP_RTCCR_CCO_Pos (7U)
+#define BKP_RTCCR_CCO_Msk (0x1U << BKP_RTCCR_CCO_Pos) /*!< 0x00000080 */
+#define BKP_RTCCR_CCO BKP_RTCCR_CCO_Msk /*!< Calibration Clock Output */
+#define BKP_RTCCR_ASOE_Pos (8U)
+#define BKP_RTCCR_ASOE_Msk (0x1U << BKP_RTCCR_ASOE_Pos) /*!< 0x00000100 */
+#define BKP_RTCCR_ASOE BKP_RTCCR_ASOE_Msk /*!< Alarm or Second Output Enable */
+#define BKP_RTCCR_ASOS_Pos (9U)
+#define BKP_RTCCR_ASOS_Msk (0x1U << BKP_RTCCR_ASOS_Pos) /*!< 0x00000200 */
+#define BKP_RTCCR_ASOS BKP_RTCCR_ASOS_Msk /*!< Alarm or Second Output Selection */
+
+/******************** Bit definition for BKP_CR register ********************/
+#define BKP_CR_TPE_Pos (0U)
+#define BKP_CR_TPE_Msk (0x1U << BKP_CR_TPE_Pos) /*!< 0x00000001 */
+#define BKP_CR_TPE BKP_CR_TPE_Msk /*!< TAMPER pin enable */
+#define BKP_CR_TPAL_Pos (1U)
+#define BKP_CR_TPAL_Msk (0x1U << BKP_CR_TPAL_Pos) /*!< 0x00000002 */
+#define BKP_CR_TPAL BKP_CR_TPAL_Msk /*!< TAMPER pin active level */
+
+/******************* Bit definition for BKP_CSR register ********************/
+#define BKP_CSR_CTE_Pos (0U)
+#define BKP_CSR_CTE_Msk (0x1U << BKP_CSR_CTE_Pos) /*!< 0x00000001 */
+#define BKP_CSR_CTE BKP_CSR_CTE_Msk /*!< Clear Tamper event */
+#define BKP_CSR_CTI_Pos (1U)
+#define BKP_CSR_CTI_Msk (0x1U << BKP_CSR_CTI_Pos) /*!< 0x00000002 */
+#define BKP_CSR_CTI BKP_CSR_CTI_Msk /*!< Clear Tamper Interrupt */
+#define BKP_CSR_TPIE_Pos (2U)
+#define BKP_CSR_TPIE_Msk (0x1U << BKP_CSR_TPIE_Pos) /*!< 0x00000004 */
+#define BKP_CSR_TPIE BKP_CSR_TPIE_Msk /*!< TAMPER Pin interrupt enable */
+#define BKP_CSR_TEF_Pos (8U)
+#define BKP_CSR_TEF_Msk (0x1U << BKP_CSR_TEF_Pos) /*!< 0x00000100 */
+#define BKP_CSR_TEF BKP_CSR_TEF_Msk /*!< Tamper Event Flag */
+#define BKP_CSR_TIF_Pos (9U)
+#define BKP_CSR_TIF_Msk (0x1U << BKP_CSR_TIF_Pos) /*!< 0x00000200 */
+#define BKP_CSR_TIF BKP_CSR_TIF_Msk /*!< Tamper Interrupt Flag */
+
+/******************************************************************************/
+/* */
+/* Reset and Clock Control */
+/* */
+/******************************************************************************/
+
+/******************** Bit definition for RCC_CR register ********************/
+#define RCC_CR_HSION_Pos (0U)
+#define RCC_CR_HSION_Msk (0x1U << RCC_CR_HSION_Pos) /*!< 0x00000001 */
+#define RCC_CR_HSION RCC_CR_HSION_Msk /*!< Internal High Speed clock enable */
+#define RCC_CR_HSIRDY_Pos (1U)
+#define RCC_CR_HSIRDY_Msk (0x1U << RCC_CR_HSIRDY_Pos) /*!< 0x00000002 */
+#define RCC_CR_HSIRDY RCC_CR_HSIRDY_Msk /*!< Internal High Speed clock ready flag */
+#define RCC_CR_HSITRIM_Pos (3U)
+#define RCC_CR_HSITRIM_Msk (0x1FU << RCC_CR_HSITRIM_Pos) /*!< 0x000000F8 */
+#define RCC_CR_HSITRIM RCC_CR_HSITRIM_Msk /*!< Internal High Speed clock trimming */
+#define RCC_CR_HSICAL_Pos (8U)
+#define RCC_CR_HSICAL_Msk (0xFFU << RCC_CR_HSICAL_Pos) /*!< 0x0000FF00 */
+#define RCC_CR_HSICAL RCC_CR_HSICAL_Msk /*!< Internal High Speed clock Calibration */
+#define RCC_CR_HSEON_Pos (16U)
+#define RCC_CR_HSEON_Msk (0x1U << RCC_CR_HSEON_Pos) /*!< 0x00010000 */
+#define RCC_CR_HSEON RCC_CR_HSEON_Msk /*!< External High Speed clock enable */
+#define RCC_CR_HSERDY_Pos (17U)
+#define RCC_CR_HSERDY_Msk (0x1U << RCC_CR_HSERDY_Pos) /*!< 0x00020000 */
+#define RCC_CR_HSERDY RCC_CR_HSERDY_Msk /*!< External High Speed clock ready flag */
+#define RCC_CR_HSEBYP_Pos (18U)
+#define RCC_CR_HSEBYP_Msk (0x1U << RCC_CR_HSEBYP_Pos) /*!< 0x00040000 */
+#define RCC_CR_HSEBYP RCC_CR_HSEBYP_Msk /*!< External High Speed clock Bypass */
+#define RCC_CR_CSSON_Pos (19U)
+#define RCC_CR_CSSON_Msk (0x1U << RCC_CR_CSSON_Pos) /*!< 0x00080000 */
+#define RCC_CR_CSSON RCC_CR_CSSON_Msk /*!< Clock Security System enable */
+#define RCC_CR_PLLON_Pos (24U)
+#define RCC_CR_PLLON_Msk (0x1U << RCC_CR_PLLON_Pos) /*!< 0x01000000 */
+#define RCC_CR_PLLON RCC_CR_PLLON_Msk /*!< PLL enable */
+#define RCC_CR_PLLRDY_Pos (25U)
+#define RCC_CR_PLLRDY_Msk (0x1U << RCC_CR_PLLRDY_Pos) /*!< 0x02000000 */
+#define RCC_CR_PLLRDY RCC_CR_PLLRDY_Msk /*!< PLL clock ready flag */
+
+
+/******************* Bit definition for RCC_CFGR register *******************/
+/*!< SW configuration */
+#define RCC_CFGR_SW_Pos (0U)
+#define RCC_CFGR_SW_Msk (0x3U << RCC_CFGR_SW_Pos) /*!< 0x00000003 */
+#define RCC_CFGR_SW RCC_CFGR_SW_Msk /*!< SW[1:0] bits (System clock Switch) */
+#define RCC_CFGR_SW_0 (0x1U << RCC_CFGR_SW_Pos) /*!< 0x00000001 */
+#define RCC_CFGR_SW_1 (0x2U << RCC_CFGR_SW_Pos) /*!< 0x00000002 */
+
+#define RCC_CFGR_SW_HSI ((uint32_t)0x00000000) /*!< HSI selected as system clock */
+#define RCC_CFGR_SW_HSE ((uint32_t)0x00000001) /*!< HSE selected as system clock */
+#define RCC_CFGR_SW_PLL ((uint32_t)0x00000002) /*!< PLL selected as system clock */
+
+/*!< SWS configuration */
+#define RCC_CFGR_SWS_Pos (2U)
+#define RCC_CFGR_SWS_Msk (0x3U << RCC_CFGR_SWS_Pos) /*!< 0x0000000C */
+#define RCC_CFGR_SWS RCC_CFGR_SWS_Msk /*!< SWS[1:0] bits (System Clock Switch Status) */
+#define RCC_CFGR_SWS_0 (0x1U << RCC_CFGR_SWS_Pos) /*!< 0x00000004 */
+#define RCC_CFGR_SWS_1 (0x2U << RCC_CFGR_SWS_Pos) /*!< 0x00000008 */
+
+#define RCC_CFGR_SWS_HSI ((uint32_t)0x00000000) /*!< HSI oscillator used as system clock */
+#define RCC_CFGR_SWS_HSE ((uint32_t)0x00000004) /*!< HSE oscillator used as system clock */
+#define RCC_CFGR_SWS_PLL ((uint32_t)0x00000008) /*!< PLL used as system clock */
+
+/*!< HPRE configuration */
+#define RCC_CFGR_HPRE_Pos (4U)
+#define RCC_CFGR_HPRE_Msk (0xFU << RCC_CFGR_HPRE_Pos) /*!< 0x000000F0 */
+#define RCC_CFGR_HPRE RCC_CFGR_HPRE_Msk /*!< HPRE[3:0] bits (AHB prescaler) */
+#define RCC_CFGR_HPRE_0 (0x1U << RCC_CFGR_HPRE_Pos) /*!< 0x00000010 */
+#define RCC_CFGR_HPRE_1 (0x2U << RCC_CFGR_HPRE_Pos) /*!< 0x00000020 */
+#define RCC_CFGR_HPRE_2 (0x4U << RCC_CFGR_HPRE_Pos) /*!< 0x00000040 */
+#define RCC_CFGR_HPRE_3 (0x8U << RCC_CFGR_HPRE_Pos) /*!< 0x00000080 */
+
+#define RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000) /*!< SYSCLK not divided */
+#define RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080) /*!< SYSCLK divided by 2 */
+#define RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090) /*!< SYSCLK divided by 4 */
+#define RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0) /*!< SYSCLK divided by 8 */
+#define RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0) /*!< SYSCLK divided by 16 */
+#define RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0) /*!< SYSCLK divided by 64 */
+#define RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0) /*!< SYSCLK divided by 128 */
+#define RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0) /*!< SYSCLK divided by 256 */
+#define RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0) /*!< SYSCLK divided by 512 */
+
+/*!< PPRE1 configuration */
+#define RCC_CFGR_PPRE1_Pos (8U)
+#define RCC_CFGR_PPRE1_Msk (0x7U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000700 */
+#define RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_Msk /*!< PRE1[2:0] bits (APB1 prescaler) */
+#define RCC_CFGR_PPRE1_0 (0x1U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000100 */
+#define RCC_CFGR_PPRE1_1 (0x2U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000200 */
+#define RCC_CFGR_PPRE1_2 (0x4U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000400 */
+
+#define RCC_CFGR_PPRE1_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */
+#define RCC_CFGR_PPRE1_DIV2 ((uint32_t)0x00000400) /*!< HCLK divided by 2 */
+#define RCC_CFGR_PPRE1_DIV4 ((uint32_t)0x00000500) /*!< HCLK divided by 4 */
+#define RCC_CFGR_PPRE1_DIV8 ((uint32_t)0x00000600) /*!< HCLK divided by 8 */
+#define RCC_CFGR_PPRE1_DIV16 ((uint32_t)0x00000700) /*!< HCLK divided by 16 */
+
+/*!< PPRE2 configuration */
+#define RCC_CFGR_PPRE2_Pos (11U)
+#define RCC_CFGR_PPRE2_Msk (0x7U << RCC_CFGR_PPRE2_Pos) /*!< 0x00003800 */
+#define RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_Msk /*!< PRE2[2:0] bits (APB2 prescaler) */
+#define RCC_CFGR_PPRE2_0 (0x1U << RCC_CFGR_PPRE2_Pos) /*!< 0x00000800 */
+#define RCC_CFGR_PPRE2_1 (0x2U << RCC_CFGR_PPRE2_Pos) /*!< 0x00001000 */
+#define RCC_CFGR_PPRE2_2 (0x4U << RCC_CFGR_PPRE2_Pos) /*!< 0x00002000 */
+
+#define RCC_CFGR_PPRE2_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */
+#define RCC_CFGR_PPRE2_DIV2 ((uint32_t)0x00002000) /*!< HCLK divided by 2 */
+#define RCC_CFGR_PPRE2_DIV4 ((uint32_t)0x00002800) /*!< HCLK divided by 4 */
+#define RCC_CFGR_PPRE2_DIV8 ((uint32_t)0x00003000) /*!< HCLK divided by 8 */
+#define RCC_CFGR_PPRE2_DIV16 ((uint32_t)0x00003800) /*!< HCLK divided by 16 */
+
+/*!< ADCPPRE configuration */
+#define RCC_CFGR_ADCPRE_Pos (14U)
+#define RCC_CFGR_ADCPRE_Msk (0x3U << RCC_CFGR_ADCPRE_Pos) /*!< 0x0000C000 */
+#define RCC_CFGR_ADCPRE RCC_CFGR_ADCPRE_Msk /*!< ADCPRE[1:0] bits (ADC prescaler) */
+#define RCC_CFGR_ADCPRE_0 (0x1U << RCC_CFGR_ADCPRE_Pos) /*!< 0x00004000 */
+#define RCC_CFGR_ADCPRE_1 (0x2U << RCC_CFGR_ADCPRE_Pos) /*!< 0x00008000 */
+
+#define RCC_CFGR_ADCPRE_DIV2 ((uint32_t)0x00000000) /*!< PCLK2 divided by 2 */
+#define RCC_CFGR_ADCPRE_DIV4 ((uint32_t)0x00004000) /*!< PCLK2 divided by 4 */
+#define RCC_CFGR_ADCPRE_DIV6 ((uint32_t)0x00008000) /*!< PCLK2 divided by 6 */
+#define RCC_CFGR_ADCPRE_DIV8 ((uint32_t)0x0000C000) /*!< PCLK2 divided by 8 */
+
+#define RCC_CFGR_PLLSRC_Pos (16U)
+#define RCC_CFGR_PLLSRC_Msk (0x1U << RCC_CFGR_PLLSRC_Pos) /*!< 0x00010000 */
+#define RCC_CFGR_PLLSRC RCC_CFGR_PLLSRC_Msk /*!< PLL entry clock source */
+
+#define RCC_CFGR_PLLXTPRE_Pos (17U)
+#define RCC_CFGR_PLLXTPRE_Msk (0x1U << RCC_CFGR_PLLXTPRE_Pos) /*!< 0x00020000 */
+#define RCC_CFGR_PLLXTPRE RCC_CFGR_PLLXTPRE_Msk /*!< HSE divider for PLL entry */
+
+/*!< PLLMUL configuration */
+#define RCC_CFGR_PLLMULL_Pos (18U)
+#define RCC_CFGR_PLLMULL_Msk (0xFU << RCC_CFGR_PLLMULL_Pos) /*!< 0x003C0000 */
+#define RCC_CFGR_PLLMULL RCC_CFGR_PLLMULL_Msk /*!< PLLMUL[3:0] bits (PLL multiplication factor) */
+#define RCC_CFGR_PLLMULL_0 (0x1U << RCC_CFGR_PLLMULL_Pos) /*!< 0x00040000 */
+#define RCC_CFGR_PLLMULL_1 (0x2U << RCC_CFGR_PLLMULL_Pos) /*!< 0x00080000 */
+#define RCC_CFGR_PLLMULL_2 (0x4U << RCC_CFGR_PLLMULL_Pos) /*!< 0x00100000 */
+#define RCC_CFGR_PLLMULL_3 (0x8U << RCC_CFGR_PLLMULL_Pos) /*!< 0x00200000 */
+
+#define RCC_CFGR_PLLXTPRE_HSE ((uint32_t)0x00000000) /*!< HSE clock not divided for PLL entry */
+#define RCC_CFGR_PLLXTPRE_HSE_DIV2 ((uint32_t)0x00020000) /*!< HSE clock divided by 2 for PLL entry */
+
+#define RCC_CFGR_PLLMULL2 ((uint32_t)0x00000000) /*!< PLL input clock*2 */
+#define RCC_CFGR_PLLMULL3_Pos (18U)
+#define RCC_CFGR_PLLMULL3_Msk (0x1U << RCC_CFGR_PLLMULL3_Pos) /*!< 0x00040000 */
+#define RCC_CFGR_PLLMULL3 RCC_CFGR_PLLMULL3_Msk /*!< PLL input clock*3 */
+#define RCC_CFGR_PLLMULL4_Pos (19U)
+#define RCC_CFGR_PLLMULL4_Msk (0x1U << RCC_CFGR_PLLMULL4_Pos) /*!< 0x00080000 */
+#define RCC_CFGR_PLLMULL4 RCC_CFGR_PLLMULL4_Msk /*!< PLL input clock*4 */
+#define RCC_CFGR_PLLMULL5_Pos (18U)
+#define RCC_CFGR_PLLMULL5_Msk (0x3U << RCC_CFGR_PLLMULL5_Pos) /*!< 0x000C0000 */
+#define RCC_CFGR_PLLMULL5 RCC_CFGR_PLLMULL5_Msk /*!< PLL input clock*5 */
+#define RCC_CFGR_PLLMULL6_Pos (20U)
+#define RCC_CFGR_PLLMULL6_Msk (0x1U << RCC_CFGR_PLLMULL6_Pos) /*!< 0x00100000 */
+#define RCC_CFGR_PLLMULL6 RCC_CFGR_PLLMULL6_Msk /*!< PLL input clock*6 */
+#define RCC_CFGR_PLLMULL7_Pos (18U)
+#define RCC_CFGR_PLLMULL7_Msk (0x5U << RCC_CFGR_PLLMULL7_Pos) /*!< 0x00140000 */
+#define RCC_CFGR_PLLMULL7 RCC_CFGR_PLLMULL7_Msk /*!< PLL input clock*7 */
+#define RCC_CFGR_PLLMULL8_Pos (19U)
+#define RCC_CFGR_PLLMULL8_Msk (0x3U << RCC_CFGR_PLLMULL8_Pos) /*!< 0x00180000 */
+#define RCC_CFGR_PLLMULL8 RCC_CFGR_PLLMULL8_Msk /*!< PLL input clock*8 */
+#define RCC_CFGR_PLLMULL9_Pos (18U)
+#define RCC_CFGR_PLLMULL9_Msk (0x7U << RCC_CFGR_PLLMULL9_Pos) /*!< 0x001C0000 */
+#define RCC_CFGR_PLLMULL9 RCC_CFGR_PLLMULL9_Msk /*!< PLL input clock*9 */
+#define RCC_CFGR_PLLMULL10_Pos (21U)
+#define RCC_CFGR_PLLMULL10_Msk (0x1U << RCC_CFGR_PLLMULL10_Pos) /*!< 0x00200000 */
+#define RCC_CFGR_PLLMULL10 RCC_CFGR_PLLMULL10_Msk /*!< PLL input clock10 */
+#define RCC_CFGR_PLLMULL11_Pos (18U)
+#define RCC_CFGR_PLLMULL11_Msk (0x9U << RCC_CFGR_PLLMULL11_Pos) /*!< 0x00240000 */
+#define RCC_CFGR_PLLMULL11 RCC_CFGR_PLLMULL11_Msk /*!< PLL input clock*11 */
+#define RCC_CFGR_PLLMULL12_Pos (19U)
+#define RCC_CFGR_PLLMULL12_Msk (0x5U << RCC_CFGR_PLLMULL12_Pos) /*!< 0x00280000 */
+#define RCC_CFGR_PLLMULL12 RCC_CFGR_PLLMULL12_Msk /*!< PLL input clock*12 */
+#define RCC_CFGR_PLLMULL13_Pos (18U)
+#define RCC_CFGR_PLLMULL13_Msk (0xBU << RCC_CFGR_PLLMULL13_Pos) /*!< 0x002C0000 */
+#define RCC_CFGR_PLLMULL13 RCC_CFGR_PLLMULL13_Msk /*!< PLL input clock*13 */
+#define RCC_CFGR_PLLMULL14_Pos (20U)
+#define RCC_CFGR_PLLMULL14_Msk (0x3U << RCC_CFGR_PLLMULL14_Pos) /*!< 0x00300000 */
+#define RCC_CFGR_PLLMULL14 RCC_CFGR_PLLMULL14_Msk /*!< PLL input clock*14 */
+#define RCC_CFGR_PLLMULL15_Pos (18U)
+#define RCC_CFGR_PLLMULL15_Msk (0xDU << RCC_CFGR_PLLMULL15_Pos) /*!< 0x00340000 */
+#define RCC_CFGR_PLLMULL15 RCC_CFGR_PLLMULL15_Msk /*!< PLL input clock*15 */
+#define RCC_CFGR_PLLMULL16_Pos (19U)
+#define RCC_CFGR_PLLMULL16_Msk (0x7U << RCC_CFGR_PLLMULL16_Pos) /*!< 0x00380000 */
+#define RCC_CFGR_PLLMULL16 RCC_CFGR_PLLMULL16_Msk /*!< PLL input clock*16 */
+#define RCC_CFGR_USBPRE_Pos (22U)
+#define RCC_CFGR_USBPRE_Msk (0x1U << RCC_CFGR_USBPRE_Pos) /*!< 0x00400000 */
+#define RCC_CFGR_USBPRE RCC_CFGR_USBPRE_Msk /*!< USB Device prescaler */
+
+/*!< MCO configuration */
+#define RCC_CFGR_MCO_Pos (24U)
+#define RCC_CFGR_MCO_Msk (0x7U << RCC_CFGR_MCO_Pos) /*!< 0x07000000 */
+#define RCC_CFGR_MCO RCC_CFGR_MCO_Msk /*!< MCO[2:0] bits (Microcontroller Clock Output) */
+#define RCC_CFGR_MCO_0 (0x1U << RCC_CFGR_MCO_Pos) /*!< 0x01000000 */
+#define RCC_CFGR_MCO_1 (0x2U << RCC_CFGR_MCO_Pos) /*!< 0x02000000 */
+#define RCC_CFGR_MCO_2 (0x4U << RCC_CFGR_MCO_Pos) /*!< 0x04000000 */
+
+#define RCC_CFGR_MCO_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */
+#define RCC_CFGR_MCO_SYSCLK ((uint32_t)0x04000000) /*!< System clock selected as MCO source */
+#define RCC_CFGR_MCO_HSI ((uint32_t)0x05000000) /*!< HSI clock selected as MCO source */
+#define RCC_CFGR_MCO_HSE ((uint32_t)0x06000000) /*!< HSE clock selected as MCO source */
+#define RCC_CFGR_MCO_PLLCLK_DIV2 ((uint32_t)0x07000000) /*!< PLL clock divided by 2 selected as MCO source */
+
+ /* Reference defines */
+ #define RCC_CFGR_MCOSEL RCC_CFGR_MCO
+ #define RCC_CFGR_MCOSEL_0 RCC_CFGR_MCO_0
+ #define RCC_CFGR_MCOSEL_1 RCC_CFGR_MCO_1
+ #define RCC_CFGR_MCOSEL_2 RCC_CFGR_MCO_2
+ #define RCC_CFGR_MCOSEL_NOCLOCK RCC_CFGR_MCO_NOCLOCK
+ #define RCC_CFGR_MCOSEL_SYSCLK RCC_CFGR_MCO_SYSCLK
+ #define RCC_CFGR_MCOSEL_HSI RCC_CFGR_MCO_HSI
+ #define RCC_CFGR_MCOSEL_HSE RCC_CFGR_MCO_HSE
+ #define RCC_CFGR_MCOSEL_PLL_DIV2 RCC_CFGR_MCO_PLLCLK_DIV2
+
+/*!<****************** Bit definition for RCC_CIR register ********************/
+#define RCC_CIR_LSIRDYF_Pos (0U)
+#define RCC_CIR_LSIRDYF_Msk (0x1U << RCC_CIR_LSIRDYF_Pos) /*!< 0x00000001 */
+#define RCC_CIR_LSIRDYF RCC_CIR_LSIRDYF_Msk /*!< LSI Ready Interrupt flag */
+#define RCC_CIR_LSERDYF_Pos (1U)
+#define RCC_CIR_LSERDYF_Msk (0x1U << RCC_CIR_LSERDYF_Pos) /*!< 0x00000002 */
+#define RCC_CIR_LSERDYF RCC_CIR_LSERDYF_Msk /*!< LSE Ready Interrupt flag */
+#define RCC_CIR_HSIRDYF_Pos (2U)
+#define RCC_CIR_HSIRDYF_Msk (0x1U << RCC_CIR_HSIRDYF_Pos) /*!< 0x00000004 */
+#define RCC_CIR_HSIRDYF RCC_CIR_HSIRDYF_Msk /*!< HSI Ready Interrupt flag */
+#define RCC_CIR_HSERDYF_Pos (3U)
+#define RCC_CIR_HSERDYF_Msk (0x1U << RCC_CIR_HSERDYF_Pos) /*!< 0x00000008 */
+#define RCC_CIR_HSERDYF RCC_CIR_HSERDYF_Msk /*!< HSE Ready Interrupt flag */
+#define RCC_CIR_PLLRDYF_Pos (4U)
+#define RCC_CIR_PLLRDYF_Msk (0x1U << RCC_CIR_PLLRDYF_Pos) /*!< 0x00000010 */
+#define RCC_CIR_PLLRDYF RCC_CIR_PLLRDYF_Msk /*!< PLL Ready Interrupt flag */
+#define RCC_CIR_CSSF_Pos (7U)
+#define RCC_CIR_CSSF_Msk (0x1U << RCC_CIR_CSSF_Pos) /*!< 0x00000080 */
+#define RCC_CIR_CSSF RCC_CIR_CSSF_Msk /*!< Clock Security System Interrupt flag */
+#define RCC_CIR_LSIRDYIE_Pos (8U)
+#define RCC_CIR_LSIRDYIE_Msk (0x1U << RCC_CIR_LSIRDYIE_Pos) /*!< 0x00000100 */
+#define RCC_CIR_LSIRDYIE RCC_CIR_LSIRDYIE_Msk /*!< LSI Ready Interrupt Enable */
+#define RCC_CIR_LSERDYIE_Pos (9U)
+#define RCC_CIR_LSERDYIE_Msk (0x1U << RCC_CIR_LSERDYIE_Pos) /*!< 0x00000200 */
+#define RCC_CIR_LSERDYIE RCC_CIR_LSERDYIE_Msk /*!< LSE Ready Interrupt Enable */
+#define RCC_CIR_HSIRDYIE_Pos (10U)
+#define RCC_CIR_HSIRDYIE_Msk (0x1U << RCC_CIR_HSIRDYIE_Pos) /*!< 0x00000400 */
+#define RCC_CIR_HSIRDYIE RCC_CIR_HSIRDYIE_Msk /*!< HSI Ready Interrupt Enable */
+#define RCC_CIR_HSERDYIE_Pos (11U)
+#define RCC_CIR_HSERDYIE_Msk (0x1U << RCC_CIR_HSERDYIE_Pos) /*!< 0x00000800 */
+#define RCC_CIR_HSERDYIE RCC_CIR_HSERDYIE_Msk /*!< HSE Ready Interrupt Enable */
+#define RCC_CIR_PLLRDYIE_Pos (12U)
+#define RCC_CIR_PLLRDYIE_Msk (0x1U << RCC_CIR_PLLRDYIE_Pos) /*!< 0x00001000 */
+#define RCC_CIR_PLLRDYIE RCC_CIR_PLLRDYIE_Msk /*!< PLL Ready Interrupt Enable */
+#define RCC_CIR_LSIRDYC_Pos (16U)
+#define RCC_CIR_LSIRDYC_Msk (0x1U << RCC_CIR_LSIRDYC_Pos) /*!< 0x00010000 */
+#define RCC_CIR_LSIRDYC RCC_CIR_LSIRDYC_Msk /*!< LSI Ready Interrupt Clear */
+#define RCC_CIR_LSERDYC_Pos (17U)
+#define RCC_CIR_LSERDYC_Msk (0x1U << RCC_CIR_LSERDYC_Pos) /*!< 0x00020000 */
+#define RCC_CIR_LSERDYC RCC_CIR_LSERDYC_Msk /*!< LSE Ready Interrupt Clear */
+#define RCC_CIR_HSIRDYC_Pos (18U)
+#define RCC_CIR_HSIRDYC_Msk (0x1U << RCC_CIR_HSIRDYC_Pos) /*!< 0x00040000 */
+#define RCC_CIR_HSIRDYC RCC_CIR_HSIRDYC_Msk /*!< HSI Ready Interrupt Clear */
+#define RCC_CIR_HSERDYC_Pos (19U)
+#define RCC_CIR_HSERDYC_Msk (0x1U << RCC_CIR_HSERDYC_Pos) /*!< 0x00080000 */
+#define RCC_CIR_HSERDYC RCC_CIR_HSERDYC_Msk /*!< HSE Ready Interrupt Clear */
+#define RCC_CIR_PLLRDYC_Pos (20U)
+#define RCC_CIR_PLLRDYC_Msk (0x1U << RCC_CIR_PLLRDYC_Pos) /*!< 0x00100000 */
+#define RCC_CIR_PLLRDYC RCC_CIR_PLLRDYC_Msk /*!< PLL Ready Interrupt Clear */
+#define RCC_CIR_CSSC_Pos (23U)
+#define RCC_CIR_CSSC_Msk (0x1U << RCC_CIR_CSSC_Pos) /*!< 0x00800000 */
+#define RCC_CIR_CSSC RCC_CIR_CSSC_Msk /*!< Clock Security System Interrupt Clear */
+
+
+/***************** Bit definition for RCC_APB2RSTR register *****************/
+#define RCC_APB2RSTR_AFIORST_Pos (0U)
+#define RCC_APB2RSTR_AFIORST_Msk (0x1U << RCC_APB2RSTR_AFIORST_Pos) /*!< 0x00000001 */
+#define RCC_APB2RSTR_AFIORST RCC_APB2RSTR_AFIORST_Msk /*!< Alternate Function I/O reset */
+#define RCC_APB2RSTR_IOPARST_Pos (2U)
+#define RCC_APB2RSTR_IOPARST_Msk (0x1U << RCC_APB2RSTR_IOPARST_Pos) /*!< 0x00000004 */
+#define RCC_APB2RSTR_IOPARST RCC_APB2RSTR_IOPARST_Msk /*!< I/O port A reset */
+#define RCC_APB2RSTR_IOPBRST_Pos (3U)
+#define RCC_APB2RSTR_IOPBRST_Msk (0x1U << RCC_APB2RSTR_IOPBRST_Pos) /*!< 0x00000008 */
+#define RCC_APB2RSTR_IOPBRST RCC_APB2RSTR_IOPBRST_Msk /*!< I/O port B reset */
+#define RCC_APB2RSTR_IOPCRST_Pos (4U)
+#define RCC_APB2RSTR_IOPCRST_Msk (0x1U << RCC_APB2RSTR_IOPCRST_Pos) /*!< 0x00000010 */
+#define RCC_APB2RSTR_IOPCRST RCC_APB2RSTR_IOPCRST_Msk /*!< I/O port C reset */
+#define RCC_APB2RSTR_IOPDRST_Pos (5U)
+#define RCC_APB2RSTR_IOPDRST_Msk (0x1U << RCC_APB2RSTR_IOPDRST_Pos) /*!< 0x00000020 */
+#define RCC_APB2RSTR_IOPDRST RCC_APB2RSTR_IOPDRST_Msk /*!< I/O port D reset */
+#define RCC_APB2RSTR_ADC1RST_Pos (9U)
+#define RCC_APB2RSTR_ADC1RST_Msk (0x1U << RCC_APB2RSTR_ADC1RST_Pos) /*!< 0x00000200 */
+#define RCC_APB2RSTR_ADC1RST RCC_APB2RSTR_ADC1RST_Msk /*!< ADC 1 interface reset */
+
+#define RCC_APB2RSTR_ADC2RST_Pos (10U)
+#define RCC_APB2RSTR_ADC2RST_Msk (0x1U << RCC_APB2RSTR_ADC2RST_Pos) /*!< 0x00000400 */
+#define RCC_APB2RSTR_ADC2RST RCC_APB2RSTR_ADC2RST_Msk /*!< ADC 2 interface reset */
+
+#define RCC_APB2RSTR_TIM1RST_Pos (11U)
+#define RCC_APB2RSTR_TIM1RST_Msk (0x1U << RCC_APB2RSTR_TIM1RST_Pos) /*!< 0x00000800 */
+#define RCC_APB2RSTR_TIM1RST RCC_APB2RSTR_TIM1RST_Msk /*!< TIM1 Timer reset */
+#define RCC_APB2RSTR_SPI1RST_Pos (12U)
+#define RCC_APB2RSTR_SPI1RST_Msk (0x1U << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */
+#define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk /*!< SPI 1 reset */
+#define RCC_APB2RSTR_USART1RST_Pos (14U)
+#define RCC_APB2RSTR_USART1RST_Msk (0x1U << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00004000 */
+#define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk /*!< USART1 reset */
+
+
+#define RCC_APB2RSTR_IOPERST_Pos (6U)
+#define RCC_APB2RSTR_IOPERST_Msk (0x1U << RCC_APB2RSTR_IOPERST_Pos) /*!< 0x00000040 */
+#define RCC_APB2RSTR_IOPERST RCC_APB2RSTR_IOPERST_Msk /*!< I/O port E reset */
+
+#define RCC_APB2RSTR_IOPFRST_Pos (7U)
+#define RCC_APB2RSTR_IOPFRST_Msk (0x1U << RCC_APB2RSTR_IOPFRST_Pos) /*!< 0x00000080 */
+#define RCC_APB2RSTR_IOPFRST RCC_APB2RSTR_IOPFRST_Msk /*!< I/O port F reset */
+#define RCC_APB2RSTR_IOPGRST_Pos (8U)
+#define RCC_APB2RSTR_IOPGRST_Msk (0x1U << RCC_APB2RSTR_IOPGRST_Pos) /*!< 0x00000100 */
+#define RCC_APB2RSTR_IOPGRST RCC_APB2RSTR_IOPGRST_Msk /*!< I/O port G reset */
+#define RCC_APB2RSTR_TIM8RST_Pos (13U)
+#define RCC_APB2RSTR_TIM8RST_Msk (0x1U << RCC_APB2RSTR_TIM8RST_Pos) /*!< 0x00002000 */
+#define RCC_APB2RSTR_TIM8RST RCC_APB2RSTR_TIM8RST_Msk /*!< TIM8 Timer reset */
+#define RCC_APB2RSTR_ADC3RST_Pos (15U)
+#define RCC_APB2RSTR_ADC3RST_Msk (0x1U << RCC_APB2RSTR_ADC3RST_Pos) /*!< 0x00008000 */
+#define RCC_APB2RSTR_ADC3RST RCC_APB2RSTR_ADC3RST_Msk /*!< ADC3 interface reset */
+
+
+
+/***************** Bit definition for RCC_APB1RSTR register *****************/
+#define RCC_APB1RSTR_TIM2RST_Pos (0U)
+#define RCC_APB1RSTR_TIM2RST_Msk (0x1U << RCC_APB1RSTR_TIM2RST_Pos) /*!< 0x00000001 */
+#define RCC_APB1RSTR_TIM2RST RCC_APB1RSTR_TIM2RST_Msk /*!< Timer 2 reset */
+#define RCC_APB1RSTR_TIM3RST_Pos (1U)
+#define RCC_APB1RSTR_TIM3RST_Msk (0x1U << RCC_APB1RSTR_TIM3RST_Pos) /*!< 0x00000002 */
+#define RCC_APB1RSTR_TIM3RST RCC_APB1RSTR_TIM3RST_Msk /*!< Timer 3 reset */
+#define RCC_APB1RSTR_WWDGRST_Pos (11U)
+#define RCC_APB1RSTR_WWDGRST_Msk (0x1U << RCC_APB1RSTR_WWDGRST_Pos) /*!< 0x00000800 */
+#define RCC_APB1RSTR_WWDGRST RCC_APB1RSTR_WWDGRST_Msk /*!< Window Watchdog reset */
+#define RCC_APB1RSTR_USART2RST_Pos (17U)
+#define RCC_APB1RSTR_USART2RST_Msk (0x1U << RCC_APB1RSTR_USART2RST_Pos) /*!< 0x00020000 */
+#define RCC_APB1RSTR_USART2RST RCC_APB1RSTR_USART2RST_Msk /*!< USART 2 reset */
+#define RCC_APB1RSTR_I2C1RST_Pos (21U)
+#define RCC_APB1RSTR_I2C1RST_Msk (0x1U << RCC_APB1RSTR_I2C1RST_Pos) /*!< 0x00200000 */
+#define RCC_APB1RSTR_I2C1RST RCC_APB1RSTR_I2C1RST_Msk /*!< I2C 1 reset */
+
+#define RCC_APB1RSTR_CAN1RST_Pos (25U)
+#define RCC_APB1RSTR_CAN1RST_Msk (0x1U << RCC_APB1RSTR_CAN1RST_Pos) /*!< 0x02000000 */
+#define RCC_APB1RSTR_CAN1RST RCC_APB1RSTR_CAN1RST_Msk /*!< CAN1 reset */
+
+#define RCC_APB1RSTR_BKPRST_Pos (27U)
+#define RCC_APB1RSTR_BKPRST_Msk (0x1U << RCC_APB1RSTR_BKPRST_Pos) /*!< 0x08000000 */
+#define RCC_APB1RSTR_BKPRST RCC_APB1RSTR_BKPRST_Msk /*!< Backup interface reset */
+#define RCC_APB1RSTR_PWRRST_Pos (28U)
+#define RCC_APB1RSTR_PWRRST_Msk (0x1U << RCC_APB1RSTR_PWRRST_Pos) /*!< 0x10000000 */
+#define RCC_APB1RSTR_PWRRST RCC_APB1RSTR_PWRRST_Msk /*!< Power interface reset */
+
+#define RCC_APB1RSTR_TIM4RST_Pos (2U)
+#define RCC_APB1RSTR_TIM4RST_Msk (0x1U << RCC_APB1RSTR_TIM4RST_Pos) /*!< 0x00000004 */
+#define RCC_APB1RSTR_TIM4RST RCC_APB1RSTR_TIM4RST_Msk /*!< Timer 4 reset */
+#define RCC_APB1RSTR_SPI2RST_Pos (14U)
+#define RCC_APB1RSTR_SPI2RST_Msk (0x1U << RCC_APB1RSTR_SPI2RST_Pos) /*!< 0x00004000 */
+#define RCC_APB1RSTR_SPI2RST RCC_APB1RSTR_SPI2RST_Msk /*!< SPI 2 reset */
+#define RCC_APB1RSTR_USART3RST_Pos (18U)
+#define RCC_APB1RSTR_USART3RST_Msk (0x1U << RCC_APB1RSTR_USART3RST_Pos) /*!< 0x00040000 */
+#define RCC_APB1RSTR_USART3RST RCC_APB1RSTR_USART3RST_Msk /*!< USART 3 reset */
+#define RCC_APB1RSTR_I2C2RST_Pos (22U)
+#define RCC_APB1RSTR_I2C2RST_Msk (0x1U << RCC_APB1RSTR_I2C2RST_Pos) /*!< 0x00400000 */
+#define RCC_APB1RSTR_I2C2RST RCC_APB1RSTR_I2C2RST_Msk /*!< I2C 2 reset */
+
+#define RCC_APB1RSTR_USBRST_Pos (23U)
+#define RCC_APB1RSTR_USBRST_Msk (0x1U << RCC_APB1RSTR_USBRST_Pos) /*!< 0x00800000 */
+#define RCC_APB1RSTR_USBRST RCC_APB1RSTR_USBRST_Msk /*!< USB Device reset */
+
+#define RCC_APB1RSTR_TIM5RST_Pos (3U)
+#define RCC_APB1RSTR_TIM5RST_Msk (0x1U << RCC_APB1RSTR_TIM5RST_Pos) /*!< 0x00000008 */
+#define RCC_APB1RSTR_TIM5RST RCC_APB1RSTR_TIM5RST_Msk /*!< Timer 5 reset */
+#define RCC_APB1RSTR_TIM6RST_Pos (4U)
+#define RCC_APB1RSTR_TIM6RST_Msk (0x1U << RCC_APB1RSTR_TIM6RST_Pos) /*!< 0x00000010 */
+#define RCC_APB1RSTR_TIM6RST RCC_APB1RSTR_TIM6RST_Msk /*!< Timer 6 reset */
+#define RCC_APB1RSTR_TIM7RST_Pos (5U)
+#define RCC_APB1RSTR_TIM7RST_Msk (0x1U << RCC_APB1RSTR_TIM7RST_Pos) /*!< 0x00000020 */
+#define RCC_APB1RSTR_TIM7RST RCC_APB1RSTR_TIM7RST_Msk /*!< Timer 7 reset */
+#define RCC_APB1RSTR_SPI3RST_Pos (15U)
+#define RCC_APB1RSTR_SPI3RST_Msk (0x1U << RCC_APB1RSTR_SPI3RST_Pos) /*!< 0x00008000 */
+#define RCC_APB1RSTR_SPI3RST RCC_APB1RSTR_SPI3RST_Msk /*!< SPI 3 reset */
+#define RCC_APB1RSTR_UART4RST_Pos (19U)
+#define RCC_APB1RSTR_UART4RST_Msk (0x1U << RCC_APB1RSTR_UART4RST_Pos) /*!< 0x00080000 */
+#define RCC_APB1RSTR_UART4RST RCC_APB1RSTR_UART4RST_Msk /*!< UART 4 reset */
+#define RCC_APB1RSTR_UART5RST_Pos (20U)
+#define RCC_APB1RSTR_UART5RST_Msk (0x1U << RCC_APB1RSTR_UART5RST_Pos) /*!< 0x00100000 */
+#define RCC_APB1RSTR_UART5RST RCC_APB1RSTR_UART5RST_Msk /*!< UART 5 reset */
+
+
+
+
+#define RCC_APB1RSTR_DACRST_Pos (29U)
+#define RCC_APB1RSTR_DACRST_Msk (0x1U << RCC_APB1RSTR_DACRST_Pos) /*!< 0x20000000 */
+#define RCC_APB1RSTR_DACRST RCC_APB1RSTR_DACRST_Msk /*!< DAC interface reset */
+
+/****************** Bit definition for RCC_AHBENR register ******************/
+#define RCC_AHBENR_DMA1EN_Pos (0U)
+#define RCC_AHBENR_DMA1EN_Msk (0x1U << RCC_AHBENR_DMA1EN_Pos) /*!< 0x00000001 */
+#define RCC_AHBENR_DMA1EN RCC_AHBENR_DMA1EN_Msk /*!< DMA1 clock enable */
+#define RCC_AHBENR_SRAMEN_Pos (2U)
+#define RCC_AHBENR_SRAMEN_Msk (0x1U << RCC_AHBENR_SRAMEN_Pos) /*!< 0x00000004 */
+#define RCC_AHBENR_SRAMEN RCC_AHBENR_SRAMEN_Msk /*!< SRAM interface clock enable */
+#define RCC_AHBENR_FLITFEN_Pos (4U)
+#define RCC_AHBENR_FLITFEN_Msk (0x1U << RCC_AHBENR_FLITFEN_Pos) /*!< 0x00000010 */
+#define RCC_AHBENR_FLITFEN RCC_AHBENR_FLITFEN_Msk /*!< FLITF clock enable */
+#define RCC_AHBENR_CRCEN_Pos (6U)
+#define RCC_AHBENR_CRCEN_Msk (0x1U << RCC_AHBENR_CRCEN_Pos) /*!< 0x00000040 */
+#define RCC_AHBENR_CRCEN RCC_AHBENR_CRCEN_Msk /*!< CRC clock enable */
+
+#define RCC_AHBENR_DMA2EN_Pos (1U)
+#define RCC_AHBENR_DMA2EN_Msk (0x1U << RCC_AHBENR_DMA2EN_Pos) /*!< 0x00000002 */
+#define RCC_AHBENR_DMA2EN RCC_AHBENR_DMA2EN_Msk /*!< DMA2 clock enable */
+
+#define RCC_AHBENR_FSMCEN_Pos (8U)
+#define RCC_AHBENR_FSMCEN_Msk (0x1U << RCC_AHBENR_FSMCEN_Pos) /*!< 0x00000100 */
+#define RCC_AHBENR_FSMCEN RCC_AHBENR_FSMCEN_Msk /*!< FSMC clock enable */
+#define RCC_AHBENR_SDIOEN_Pos (10U)
+#define RCC_AHBENR_SDIOEN_Msk (0x1U << RCC_AHBENR_SDIOEN_Pos) /*!< 0x00000400 */
+#define RCC_AHBENR_SDIOEN RCC_AHBENR_SDIOEN_Msk /*!< SDIO clock enable */
+
+
+/****************** Bit definition for RCC_APB2ENR register *****************/
+#define RCC_APB2ENR_AFIOEN_Pos (0U)
+#define RCC_APB2ENR_AFIOEN_Msk (0x1U << RCC_APB2ENR_AFIOEN_Pos) /*!< 0x00000001 */
+#define RCC_APB2ENR_AFIOEN RCC_APB2ENR_AFIOEN_Msk /*!< Alternate Function I/O clock enable */
+#define RCC_APB2ENR_IOPAEN_Pos (2U)
+#define RCC_APB2ENR_IOPAEN_Msk (0x1U << RCC_APB2ENR_IOPAEN_Pos) /*!< 0x00000004 */
+#define RCC_APB2ENR_IOPAEN RCC_APB2ENR_IOPAEN_Msk /*!< I/O port A clock enable */
+#define RCC_APB2ENR_IOPBEN_Pos (3U)
+#define RCC_APB2ENR_IOPBEN_Msk (0x1U << RCC_APB2ENR_IOPBEN_Pos) /*!< 0x00000008 */
+#define RCC_APB2ENR_IOPBEN RCC_APB2ENR_IOPBEN_Msk /*!< I/O port B clock enable */
+#define RCC_APB2ENR_IOPCEN_Pos (4U)
+#define RCC_APB2ENR_IOPCEN_Msk (0x1U << RCC_APB2ENR_IOPCEN_Pos) /*!< 0x00000010 */
+#define RCC_APB2ENR_IOPCEN RCC_APB2ENR_IOPCEN_Msk /*!< I/O port C clock enable */
+#define RCC_APB2ENR_IOPDEN_Pos (5U)
+#define RCC_APB2ENR_IOPDEN_Msk (0x1U << RCC_APB2ENR_IOPDEN_Pos) /*!< 0x00000020 */
+#define RCC_APB2ENR_IOPDEN RCC_APB2ENR_IOPDEN_Msk /*!< I/O port D clock enable */
+#define RCC_APB2ENR_ADC1EN_Pos (9U)
+#define RCC_APB2ENR_ADC1EN_Msk (0x1U << RCC_APB2ENR_ADC1EN_Pos) /*!< 0x00000200 */
+#define RCC_APB2ENR_ADC1EN RCC_APB2ENR_ADC1EN_Msk /*!< ADC 1 interface clock enable */
+
+#define RCC_APB2ENR_ADC2EN_Pos (10U)
+#define RCC_APB2ENR_ADC2EN_Msk (0x1U << RCC_APB2ENR_ADC2EN_Pos) /*!< 0x00000400 */
+#define RCC_APB2ENR_ADC2EN RCC_APB2ENR_ADC2EN_Msk /*!< ADC 2 interface clock enable */
+
+#define RCC_APB2ENR_TIM1EN_Pos (11U)
+#define RCC_APB2ENR_TIM1EN_Msk (0x1U << RCC_APB2ENR_TIM1EN_Pos) /*!< 0x00000800 */
+#define RCC_APB2ENR_TIM1EN RCC_APB2ENR_TIM1EN_Msk /*!< TIM1 Timer clock enable */
+#define RCC_APB2ENR_SPI1EN_Pos (12U)
+#define RCC_APB2ENR_SPI1EN_Msk (0x1U << RCC_APB2ENR_SPI1EN_Pos) /*!< 0x00001000 */
+#define RCC_APB2ENR_SPI1EN RCC_APB2ENR_SPI1EN_Msk /*!< SPI 1 clock enable */
+#define RCC_APB2ENR_USART1EN_Pos (14U)
+#define RCC_APB2ENR_USART1EN_Msk (0x1U << RCC_APB2ENR_USART1EN_Pos) /*!< 0x00004000 */
+#define RCC_APB2ENR_USART1EN RCC_APB2ENR_USART1EN_Msk /*!< USART1 clock enable */
+
+
+#define RCC_APB2ENR_IOPEEN_Pos (6U)
+#define RCC_APB2ENR_IOPEEN_Msk (0x1U << RCC_APB2ENR_IOPEEN_Pos) /*!< 0x00000040 */
+#define RCC_APB2ENR_IOPEEN RCC_APB2ENR_IOPEEN_Msk /*!< I/O port E clock enable */
+
+#define RCC_APB2ENR_IOPFEN_Pos (7U)
+#define RCC_APB2ENR_IOPFEN_Msk (0x1U << RCC_APB2ENR_IOPFEN_Pos) /*!< 0x00000080 */
+#define RCC_APB2ENR_IOPFEN RCC_APB2ENR_IOPFEN_Msk /*!< I/O port F clock enable */
+#define RCC_APB2ENR_IOPGEN_Pos (8U)
+#define RCC_APB2ENR_IOPGEN_Msk (0x1U << RCC_APB2ENR_IOPGEN_Pos) /*!< 0x00000100 */
+#define RCC_APB2ENR_IOPGEN RCC_APB2ENR_IOPGEN_Msk /*!< I/O port G clock enable */
+#define RCC_APB2ENR_TIM8EN_Pos (13U)
+#define RCC_APB2ENR_TIM8EN_Msk (0x1U << RCC_APB2ENR_TIM8EN_Pos) /*!< 0x00002000 */
+#define RCC_APB2ENR_TIM8EN RCC_APB2ENR_TIM8EN_Msk /*!< TIM8 Timer clock enable */
+#define RCC_APB2ENR_ADC3EN_Pos (15U)
+#define RCC_APB2ENR_ADC3EN_Msk (0x1U << RCC_APB2ENR_ADC3EN_Pos) /*!< 0x00008000 */
+#define RCC_APB2ENR_ADC3EN RCC_APB2ENR_ADC3EN_Msk /*!< DMA1 clock enable */
+
+
+
+/***************** Bit definition for RCC_APB1ENR register ******************/
+#define RCC_APB1ENR_TIM2EN_Pos (0U)
+#define RCC_APB1ENR_TIM2EN_Msk (0x1U << RCC_APB1ENR_TIM2EN_Pos) /*!< 0x00000001 */
+#define RCC_APB1ENR_TIM2EN RCC_APB1ENR_TIM2EN_Msk /*!< Timer 2 clock enabled*/
+#define RCC_APB1ENR_TIM3EN_Pos (1U)
+#define RCC_APB1ENR_TIM3EN_Msk (0x1U << RCC_APB1ENR_TIM3EN_Pos) /*!< 0x00000002 */
+#define RCC_APB1ENR_TIM3EN RCC_APB1ENR_TIM3EN_Msk /*!< Timer 3 clock enable */
+#define RCC_APB1ENR_WWDGEN_Pos (11U)
+#define RCC_APB1ENR_WWDGEN_Msk (0x1U << RCC_APB1ENR_WWDGEN_Pos) /*!< 0x00000800 */
+#define RCC_APB1ENR_WWDGEN RCC_APB1ENR_WWDGEN_Msk /*!< Window Watchdog clock enable */
+#define RCC_APB1ENR_USART2EN_Pos (17U)
+#define RCC_APB1ENR_USART2EN_Msk (0x1U << RCC_APB1ENR_USART2EN_Pos) /*!< 0x00020000 */
+#define RCC_APB1ENR_USART2EN RCC_APB1ENR_USART2EN_Msk /*!< USART 2 clock enable */
+#define RCC_APB1ENR_I2C1EN_Pos (21U)
+#define RCC_APB1ENR_I2C1EN_Msk (0x1U << RCC_APB1ENR_I2C1EN_Pos) /*!< 0x00200000 */
+#define RCC_APB1ENR_I2C1EN RCC_APB1ENR_I2C1EN_Msk /*!< I2C 1 clock enable */
+
+#define RCC_APB1ENR_CAN1EN_Pos (25U)
+#define RCC_APB1ENR_CAN1EN_Msk (0x1U << RCC_APB1ENR_CAN1EN_Pos) /*!< 0x02000000 */
+#define RCC_APB1ENR_CAN1EN RCC_APB1ENR_CAN1EN_Msk /*!< CAN1 clock enable */
+
+#define RCC_APB1ENR_BKPEN_Pos (27U)
+#define RCC_APB1ENR_BKPEN_Msk (0x1U << RCC_APB1ENR_BKPEN_Pos) /*!< 0x08000000 */
+#define RCC_APB1ENR_BKPEN RCC_APB1ENR_BKPEN_Msk /*!< Backup interface clock enable */
+#define RCC_APB1ENR_PWREN_Pos (28U)
+#define RCC_APB1ENR_PWREN_Msk (0x1U << RCC_APB1ENR_PWREN_Pos) /*!< 0x10000000 */
+#define RCC_APB1ENR_PWREN RCC_APB1ENR_PWREN_Msk /*!< Power interface clock enable */
+
+#define RCC_APB1ENR_TIM4EN_Pos (2U)
+#define RCC_APB1ENR_TIM4EN_Msk (0x1U << RCC_APB1ENR_TIM4EN_Pos) /*!< 0x00000004 */
+#define RCC_APB1ENR_TIM4EN RCC_APB1ENR_TIM4EN_Msk /*!< Timer 4 clock enable */
+#define RCC_APB1ENR_SPI2EN_Pos (14U)
+#define RCC_APB1ENR_SPI2EN_Msk (0x1U << RCC_APB1ENR_SPI2EN_Pos) /*!< 0x00004000 */
+#define RCC_APB1ENR_SPI2EN RCC_APB1ENR_SPI2EN_Msk /*!< SPI 2 clock enable */
+#define RCC_APB1ENR_USART3EN_Pos (18U)
+#define RCC_APB1ENR_USART3EN_Msk (0x1U << RCC_APB1ENR_USART3EN_Pos) /*!< 0x00040000 */
+#define RCC_APB1ENR_USART3EN RCC_APB1ENR_USART3EN_Msk /*!< USART 3 clock enable */
+#define RCC_APB1ENR_I2C2EN_Pos (22U)
+#define RCC_APB1ENR_I2C2EN_Msk (0x1U << RCC_APB1ENR_I2C2EN_Pos) /*!< 0x00400000 */
+#define RCC_APB1ENR_I2C2EN RCC_APB1ENR_I2C2EN_Msk /*!< I2C 2 clock enable */
+
+#define RCC_APB1ENR_USBEN_Pos (23U)
+#define RCC_APB1ENR_USBEN_Msk (0x1U << RCC_APB1ENR_USBEN_Pos) /*!< 0x00800000 */
+#define RCC_APB1ENR_USBEN RCC_APB1ENR_USBEN_Msk /*!< USB Device clock enable */
+
+#define RCC_APB1ENR_TIM5EN_Pos (3U)
+#define RCC_APB1ENR_TIM5EN_Msk (0x1U << RCC_APB1ENR_TIM5EN_Pos) /*!< 0x00000008 */
+#define RCC_APB1ENR_TIM5EN RCC_APB1ENR_TIM5EN_Msk /*!< Timer 5 clock enable */
+#define RCC_APB1ENR_TIM6EN_Pos (4U)
+#define RCC_APB1ENR_TIM6EN_Msk (0x1U << RCC_APB1ENR_TIM6EN_Pos) /*!< 0x00000010 */
+#define RCC_APB1ENR_TIM6EN RCC_APB1ENR_TIM6EN_Msk /*!< Timer 6 clock enable */
+#define RCC_APB1ENR_TIM7EN_Pos (5U)
+#define RCC_APB1ENR_TIM7EN_Msk (0x1U << RCC_APB1ENR_TIM7EN_Pos) /*!< 0x00000020 */
+#define RCC_APB1ENR_TIM7EN RCC_APB1ENR_TIM7EN_Msk /*!< Timer 7 clock enable */
+#define RCC_APB1ENR_SPI3EN_Pos (15U)
+#define RCC_APB1ENR_SPI3EN_Msk (0x1U << RCC_APB1ENR_SPI3EN_Pos) /*!< 0x00008000 */
+#define RCC_APB1ENR_SPI3EN RCC_APB1ENR_SPI3EN_Msk /*!< SPI 3 clock enable */
+#define RCC_APB1ENR_UART4EN_Pos (19U)
+#define RCC_APB1ENR_UART4EN_Msk (0x1U << RCC_APB1ENR_UART4EN_Pos) /*!< 0x00080000 */
+#define RCC_APB1ENR_UART4EN RCC_APB1ENR_UART4EN_Msk /*!< UART 4 clock enable */
+#define RCC_APB1ENR_UART5EN_Pos (20U)
+#define RCC_APB1ENR_UART5EN_Msk (0x1U << RCC_APB1ENR_UART5EN_Pos) /*!< 0x00100000 */
+#define RCC_APB1ENR_UART5EN RCC_APB1ENR_UART5EN_Msk /*!< UART 5 clock enable */
+
+
+
+
+#define RCC_APB1ENR_DACEN_Pos (29U)
+#define RCC_APB1ENR_DACEN_Msk (0x1U << RCC_APB1ENR_DACEN_Pos) /*!< 0x20000000 */
+#define RCC_APB1ENR_DACEN RCC_APB1ENR_DACEN_Msk /*!< DAC interface clock enable */
+
+/******************* Bit definition for RCC_BDCR register *******************/
+#define RCC_BDCR_LSEON_Pos (0U)
+#define RCC_BDCR_LSEON_Msk (0x1U << RCC_BDCR_LSEON_Pos) /*!< 0x00000001 */
+#define RCC_BDCR_LSEON RCC_BDCR_LSEON_Msk /*!< External Low Speed oscillator enable */
+#define RCC_BDCR_LSERDY_Pos (1U)
+#define RCC_BDCR_LSERDY_Msk (0x1U << RCC_BDCR_LSERDY_Pos) /*!< 0x00000002 */
+#define RCC_BDCR_LSERDY RCC_BDCR_LSERDY_Msk /*!< External Low Speed oscillator Ready */
+#define RCC_BDCR_LSEBYP_Pos (2U)
+#define RCC_BDCR_LSEBYP_Msk (0x1U << RCC_BDCR_LSEBYP_Pos) /*!< 0x00000004 */
+#define RCC_BDCR_LSEBYP RCC_BDCR_LSEBYP_Msk /*!< External Low Speed oscillator Bypass */
+
+#define RCC_BDCR_RTCSEL_Pos (8U)
+#define RCC_BDCR_RTCSEL_Msk (0x3U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000300 */
+#define RCC_BDCR_RTCSEL RCC_BDCR_RTCSEL_Msk /*!< RTCSEL[1:0] bits (RTC clock source selection) */
+#define RCC_BDCR_RTCSEL_0 (0x1U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000100 */
+#define RCC_BDCR_RTCSEL_1 (0x2U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000200 */
+
+/*!< RTC congiguration */
+#define RCC_BDCR_RTCSEL_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */
+#define RCC_BDCR_RTCSEL_LSE ((uint32_t)0x00000100) /*!< LSE oscillator clock used as RTC clock */
+#define RCC_BDCR_RTCSEL_LSI ((uint32_t)0x00000200) /*!< LSI oscillator clock used as RTC clock */
+#define RCC_BDCR_RTCSEL_HSE ((uint32_t)0x00000300) /*!< HSE oscillator clock divided by 128 used as RTC clock */
+
+#define RCC_BDCR_RTCEN_Pos (15U)
+#define RCC_BDCR_RTCEN_Msk (0x1U << RCC_BDCR_RTCEN_Pos) /*!< 0x00008000 */
+#define RCC_BDCR_RTCEN RCC_BDCR_RTCEN_Msk /*!< RTC clock enable */
+#define RCC_BDCR_BDRST_Pos (16U)
+#define RCC_BDCR_BDRST_Msk (0x1U << RCC_BDCR_BDRST_Pos) /*!< 0x00010000 */
+#define RCC_BDCR_BDRST RCC_BDCR_BDRST_Msk /*!< Backup domain software reset */
+
+/******************* Bit definition for RCC_CSR register ********************/
+#define RCC_CSR_LSION_Pos (0U)
+#define RCC_CSR_LSION_Msk (0x1U << RCC_CSR_LSION_Pos) /*!< 0x00000001 */
+#define RCC_CSR_LSION RCC_CSR_LSION_Msk /*!< Internal Low Speed oscillator enable */
+#define RCC_CSR_LSIRDY_Pos (1U)
+#define RCC_CSR_LSIRDY_Msk (0x1U << RCC_CSR_LSIRDY_Pos) /*!< 0x00000002 */
+#define RCC_CSR_LSIRDY RCC_CSR_LSIRDY_Msk /*!< Internal Low Speed oscillator Ready */
+#define RCC_CSR_RMVF_Pos (24U)
+#define RCC_CSR_RMVF_Msk (0x1U << RCC_CSR_RMVF_Pos) /*!< 0x01000000 */
+#define RCC_CSR_RMVF RCC_CSR_RMVF_Msk /*!< Remove reset flag */
+#define RCC_CSR_PINRSTF_Pos (26U)
+#define RCC_CSR_PINRSTF_Msk (0x1U << RCC_CSR_PINRSTF_Pos) /*!< 0x04000000 */
+#define RCC_CSR_PINRSTF RCC_CSR_PINRSTF_Msk /*!< PIN reset flag */
+#define RCC_CSR_PORRSTF_Pos (27U)
+#define RCC_CSR_PORRSTF_Msk (0x1U << RCC_CSR_PORRSTF_Pos) /*!< 0x08000000 */
+#define RCC_CSR_PORRSTF RCC_CSR_PORRSTF_Msk /*!< POR/PDR reset flag */
+#define RCC_CSR_SFTRSTF_Pos (28U)
+#define RCC_CSR_SFTRSTF_Msk (0x1U << RCC_CSR_SFTRSTF_Pos) /*!< 0x10000000 */
+#define RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF_Msk /*!< Software Reset flag */
+#define RCC_CSR_IWDGRSTF_Pos (29U)
+#define RCC_CSR_IWDGRSTF_Msk (0x1U << RCC_CSR_IWDGRSTF_Pos) /*!< 0x20000000 */
+#define RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF_Msk /*!< Independent Watchdog reset flag */
+#define RCC_CSR_WWDGRSTF_Pos (30U)
+#define RCC_CSR_WWDGRSTF_Msk (0x1U << RCC_CSR_WWDGRSTF_Pos) /*!< 0x40000000 */
+#define RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF_Msk /*!< Window watchdog reset flag */
+#define RCC_CSR_LPWRRSTF_Pos (31U)
+#define RCC_CSR_LPWRRSTF_Msk (0x1U << RCC_CSR_LPWRRSTF_Pos) /*!< 0x80000000 */
+#define RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF_Msk /*!< Low-Power reset flag */
+
+
+
+/******************************************************************************/
+/* */
+/* General Purpose and Alternate Function I/O */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for GPIO_CRL register *******************/
+#define GPIO_CRL_MODE_Pos (0U)
+#define GPIO_CRL_MODE_Msk (0x33333333U << GPIO_CRL_MODE_Pos) /*!< 0x33333333 */
+#define GPIO_CRL_MODE GPIO_CRL_MODE_Msk /*!< Port x mode bits */
+
+#define GPIO_CRL_MODE0_Pos (0U)
+#define GPIO_CRL_MODE0_Msk (0x3U << GPIO_CRL_MODE0_Pos) /*!< 0x00000003 */
+#define GPIO_CRL_MODE0 GPIO_CRL_MODE0_Msk /*!< MODE0[1:0] bits (Port x mode bits, pin 0) */
+#define GPIO_CRL_MODE0_0 (0x1U << GPIO_CRL_MODE0_Pos) /*!< 0x00000001 */
+#define GPIO_CRL_MODE0_1 (0x2U << GPIO_CRL_MODE0_Pos) /*!< 0x00000002 */
+
+#define GPIO_CRL_MODE1_Pos (4U)
+#define GPIO_CRL_MODE1_Msk (0x3U << GPIO_CRL_MODE1_Pos) /*!< 0x00000030 */
+#define GPIO_CRL_MODE1 GPIO_CRL_MODE1_Msk /*!< MODE1[1:0] bits (Port x mode bits, pin 1) */
+#define GPIO_CRL_MODE1_0 (0x1U << GPIO_CRL_MODE1_Pos) /*!< 0x00000010 */
+#define GPIO_CRL_MODE1_1 (0x2U << GPIO_CRL_MODE1_Pos) /*!< 0x00000020 */
+
+#define GPIO_CRL_MODE2_Pos (8U)
+#define GPIO_CRL_MODE2_Msk (0x3U << GPIO_CRL_MODE2_Pos) /*!< 0x00000300 */
+#define GPIO_CRL_MODE2 GPIO_CRL_MODE2_Msk /*!< MODE2[1:0] bits (Port x mode bits, pin 2) */
+#define GPIO_CRL_MODE2_0 (0x1U << GPIO_CRL_MODE2_Pos) /*!< 0x00000100 */
+#define GPIO_CRL_MODE2_1 (0x2U << GPIO_CRL_MODE2_Pos) /*!< 0x00000200 */
+
+#define GPIO_CRL_MODE3_Pos (12U)
+#define GPIO_CRL_MODE3_Msk (0x3U << GPIO_CRL_MODE3_Pos) /*!< 0x00003000 */
+#define GPIO_CRL_MODE3 GPIO_CRL_MODE3_Msk /*!< MODE3[1:0] bits (Port x mode bits, pin 3) */
+#define GPIO_CRL_MODE3_0 (0x1U << GPIO_CRL_MODE3_Pos) /*!< 0x00001000 */
+#define GPIO_CRL_MODE3_1 (0x2U << GPIO_CRL_MODE3_Pos) /*!< 0x00002000 */
+
+#define GPIO_CRL_MODE4_Pos (16U)
+#define GPIO_CRL_MODE4_Msk (0x3U << GPIO_CRL_MODE4_Pos) /*!< 0x00030000 */
+#define GPIO_CRL_MODE4 GPIO_CRL_MODE4_Msk /*!< MODE4[1:0] bits (Port x mode bits, pin 4) */
+#define GPIO_CRL_MODE4_0 (0x1U << GPIO_CRL_MODE4_Pos) /*!< 0x00010000 */
+#define GPIO_CRL_MODE4_1 (0x2U << GPIO_CRL_MODE4_Pos) /*!< 0x00020000 */
+
+#define GPIO_CRL_MODE5_Pos (20U)
+#define GPIO_CRL_MODE5_Msk (0x3U << GPIO_CRL_MODE5_Pos) /*!< 0x00300000 */
+#define GPIO_CRL_MODE5 GPIO_CRL_MODE5_Msk /*!< MODE5[1:0] bits (Port x mode bits, pin 5) */
+#define GPIO_CRL_MODE5_0 (0x1U << GPIO_CRL_MODE5_Pos) /*!< 0x00100000 */
+#define GPIO_CRL_MODE5_1 (0x2U << GPIO_CRL_MODE5_Pos) /*!< 0x00200000 */
+
+#define GPIO_CRL_MODE6_Pos (24U)
+#define GPIO_CRL_MODE6_Msk (0x3U << GPIO_CRL_MODE6_Pos) /*!< 0x03000000 */
+#define GPIO_CRL_MODE6 GPIO_CRL_MODE6_Msk /*!< MODE6[1:0] bits (Port x mode bits, pin 6) */
+#define GPIO_CRL_MODE6_0 (0x1U << GPIO_CRL_MODE6_Pos) /*!< 0x01000000 */
+#define GPIO_CRL_MODE6_1 (0x2U << GPIO_CRL_MODE6_Pos) /*!< 0x02000000 */
+
+#define GPIO_CRL_MODE7_Pos (28U)
+#define GPIO_CRL_MODE7_Msk (0x3U << GPIO_CRL_MODE7_Pos) /*!< 0x30000000 */
+#define GPIO_CRL_MODE7 GPIO_CRL_MODE7_Msk /*!< MODE7[1:0] bits (Port x mode bits, pin 7) */
+#define GPIO_CRL_MODE7_0 (0x1U << GPIO_CRL_MODE7_Pos) /*!< 0x10000000 */
+#define GPIO_CRL_MODE7_1 (0x2U << GPIO_CRL_MODE7_Pos) /*!< 0x20000000 */
+
+#define GPIO_CRL_CNF_Pos (2U)
+#define GPIO_CRL_CNF_Msk (0x33333333U << GPIO_CRL_CNF_Pos) /*!< 0xCCCCCCCC */
+#define GPIO_CRL_CNF GPIO_CRL_CNF_Msk /*!< Port x configuration bits */
+
+#define GPIO_CRL_CNF0_Pos (2U)
+#define GPIO_CRL_CNF0_Msk (0x3U << GPIO_CRL_CNF0_Pos) /*!< 0x0000000C */
+#define GPIO_CRL_CNF0 GPIO_CRL_CNF0_Msk /*!< CNF0[1:0] bits (Port x configuration bits, pin 0) */
+#define GPIO_CRL_CNF0_0 (0x1U << GPIO_CRL_CNF0_Pos) /*!< 0x00000004 */
+#define GPIO_CRL_CNF0_1 (0x2U << GPIO_CRL_CNF0_Pos) /*!< 0x00000008 */
+
+#define GPIO_CRL_CNF1_Pos (6U)
+#define GPIO_CRL_CNF1_Msk (0x3U << GPIO_CRL_CNF1_Pos) /*!< 0x000000C0 */
+#define GPIO_CRL_CNF1 GPIO_CRL_CNF1_Msk /*!< CNF1[1:0] bits (Port x configuration bits, pin 1) */
+#define GPIO_CRL_CNF1_0 (0x1U << GPIO_CRL_CNF1_Pos) /*!< 0x00000040 */
+#define GPIO_CRL_CNF1_1 (0x2U << GPIO_CRL_CNF1_Pos) /*!< 0x00000080 */
+
+#define GPIO_CRL_CNF2_Pos (10U)
+#define GPIO_CRL_CNF2_Msk (0x3U << GPIO_CRL_CNF2_Pos) /*!< 0x00000C00 */
+#define GPIO_CRL_CNF2 GPIO_CRL_CNF2_Msk /*!< CNF2[1:0] bits (Port x configuration bits, pin 2) */
+#define GPIO_CRL_CNF2_0 (0x1U << GPIO_CRL_CNF2_Pos) /*!< 0x00000400 */
+#define GPIO_CRL_CNF2_1 (0x2U << GPIO_CRL_CNF2_Pos) /*!< 0x00000800 */
+
+#define GPIO_CRL_CNF3_Pos (14U)
+#define GPIO_CRL_CNF3_Msk (0x3U << GPIO_CRL_CNF3_Pos) /*!< 0x0000C000 */
+#define GPIO_CRL_CNF3 GPIO_CRL_CNF3_Msk /*!< CNF3[1:0] bits (Port x configuration bits, pin 3) */
+#define GPIO_CRL_CNF3_0 (0x1U << GPIO_CRL_CNF3_Pos) /*!< 0x00004000 */
+#define GPIO_CRL_CNF3_1 (0x2U << GPIO_CRL_CNF3_Pos) /*!< 0x00008000 */
+
+#define GPIO_CRL_CNF4_Pos (18U)
+#define GPIO_CRL_CNF4_Msk (0x3U << GPIO_CRL_CNF4_Pos) /*!< 0x000C0000 */
+#define GPIO_CRL_CNF4 GPIO_CRL_CNF4_Msk /*!< CNF4[1:0] bits (Port x configuration bits, pin 4) */
+#define GPIO_CRL_CNF4_0 (0x1U << GPIO_CRL_CNF4_Pos) /*!< 0x00040000 */
+#define GPIO_CRL_CNF4_1 (0x2U << GPIO_CRL_CNF4_Pos) /*!< 0x00080000 */
+
+#define GPIO_CRL_CNF5_Pos (22U)
+#define GPIO_CRL_CNF5_Msk (0x3U << GPIO_CRL_CNF5_Pos) /*!< 0x00C00000 */
+#define GPIO_CRL_CNF5 GPIO_CRL_CNF5_Msk /*!< CNF5[1:0] bits (Port x configuration bits, pin 5) */
+#define GPIO_CRL_CNF5_0 (0x1U << GPIO_CRL_CNF5_Pos) /*!< 0x00400000 */
+#define GPIO_CRL_CNF5_1 (0x2U << GPIO_CRL_CNF5_Pos) /*!< 0x00800000 */
+
+#define GPIO_CRL_CNF6_Pos (26U)
+#define GPIO_CRL_CNF6_Msk (0x3U << GPIO_CRL_CNF6_Pos) /*!< 0x0C000000 */
+#define GPIO_CRL_CNF6 GPIO_CRL_CNF6_Msk /*!< CNF6[1:0] bits (Port x configuration bits, pin 6) */
+#define GPIO_CRL_CNF6_0 (0x1U << GPIO_CRL_CNF6_Pos) /*!< 0x04000000 */
+#define GPIO_CRL_CNF6_1 (0x2U << GPIO_CRL_CNF6_Pos) /*!< 0x08000000 */
+
+#define GPIO_CRL_CNF7_Pos (30U)
+#define GPIO_CRL_CNF7_Msk (0x3U << GPIO_CRL_CNF7_Pos) /*!< 0xC0000000 */
+#define GPIO_CRL_CNF7 GPIO_CRL_CNF7_Msk /*!< CNF7[1:0] bits (Port x configuration bits, pin 7) */
+#define GPIO_CRL_CNF7_0 (0x1U << GPIO_CRL_CNF7_Pos) /*!< 0x40000000 */
+#define GPIO_CRL_CNF7_1 (0x2U << GPIO_CRL_CNF7_Pos) /*!< 0x80000000 */
+
+/******************* Bit definition for GPIO_CRH register *******************/
+#define GPIO_CRH_MODE_Pos (0U)
+#define GPIO_CRH_MODE_Msk (0x33333333U << GPIO_CRH_MODE_Pos) /*!< 0x33333333 */
+#define GPIO_CRH_MODE GPIO_CRH_MODE_Msk /*!< Port x mode bits */
+
+#define GPIO_CRH_MODE8_Pos (0U)
+#define GPIO_CRH_MODE8_Msk (0x3U << GPIO_CRH_MODE8_Pos) /*!< 0x00000003 */
+#define GPIO_CRH_MODE8 GPIO_CRH_MODE8_Msk /*!< MODE8[1:0] bits (Port x mode bits, pin 8) */
+#define GPIO_CRH_MODE8_0 (0x1U << GPIO_CRH_MODE8_Pos) /*!< 0x00000001 */
+#define GPIO_CRH_MODE8_1 (0x2U << GPIO_CRH_MODE8_Pos) /*!< 0x00000002 */
+
+#define GPIO_CRH_MODE9_Pos (4U)
+#define GPIO_CRH_MODE9_Msk (0x3U << GPIO_CRH_MODE9_Pos) /*!< 0x00000030 */
+#define GPIO_CRH_MODE9 GPIO_CRH_MODE9_Msk /*!< MODE9[1:0] bits (Port x mode bits, pin 9) */
+#define GPIO_CRH_MODE9_0 (0x1U << GPIO_CRH_MODE9_Pos) /*!< 0x00000010 */
+#define GPIO_CRH_MODE9_1 (0x2U << GPIO_CRH_MODE9_Pos) /*!< 0x00000020 */
+
+#define GPIO_CRH_MODE10_Pos (8U)
+#define GPIO_CRH_MODE10_Msk (0x3U << GPIO_CRH_MODE10_Pos) /*!< 0x00000300 */
+#define GPIO_CRH_MODE10 GPIO_CRH_MODE10_Msk /*!< MODE10[1:0] bits (Port x mode bits, pin 10) */
+#define GPIO_CRH_MODE10_0 (0x1U << GPIO_CRH_MODE10_Pos) /*!< 0x00000100 */
+#define GPIO_CRH_MODE10_1 (0x2U << GPIO_CRH_MODE10_Pos) /*!< 0x00000200 */
+
+#define GPIO_CRH_MODE11_Pos (12U)
+#define GPIO_CRH_MODE11_Msk (0x3U << GPIO_CRH_MODE11_Pos) /*!< 0x00003000 */
+#define GPIO_CRH_MODE11 GPIO_CRH_MODE11_Msk /*!< MODE11[1:0] bits (Port x mode bits, pin 11) */
+#define GPIO_CRH_MODE11_0 (0x1U << GPIO_CRH_MODE11_Pos) /*!< 0x00001000 */
+#define GPIO_CRH_MODE11_1 (0x2U << GPIO_CRH_MODE11_Pos) /*!< 0x00002000 */
+
+#define GPIO_CRH_MODE12_Pos (16U)
+#define GPIO_CRH_MODE12_Msk (0x3U << GPIO_CRH_MODE12_Pos) /*!< 0x00030000 */
+#define GPIO_CRH_MODE12 GPIO_CRH_MODE12_Msk /*!< MODE12[1:0] bits (Port x mode bits, pin 12) */
+#define GPIO_CRH_MODE12_0 (0x1U << GPIO_CRH_MODE12_Pos) /*!< 0x00010000 */
+#define GPIO_CRH_MODE12_1 (0x2U << GPIO_CRH_MODE12_Pos) /*!< 0x00020000 */
+
+#define GPIO_CRH_MODE13_Pos (20U)
+#define GPIO_CRH_MODE13_Msk (0x3U << GPIO_CRH_MODE13_Pos) /*!< 0x00300000 */
+#define GPIO_CRH_MODE13 GPIO_CRH_MODE13_Msk /*!< MODE13[1:0] bits (Port x mode bits, pin 13) */
+#define GPIO_CRH_MODE13_0 (0x1U << GPIO_CRH_MODE13_Pos) /*!< 0x00100000 */
+#define GPIO_CRH_MODE13_1 (0x2U << GPIO_CRH_MODE13_Pos) /*!< 0x00200000 */
+
+#define GPIO_CRH_MODE14_Pos (24U)
+#define GPIO_CRH_MODE14_Msk (0x3U << GPIO_CRH_MODE14_Pos) /*!< 0x03000000 */
+#define GPIO_CRH_MODE14 GPIO_CRH_MODE14_Msk /*!< MODE14[1:0] bits (Port x mode bits, pin 14) */
+#define GPIO_CRH_MODE14_0 (0x1U << GPIO_CRH_MODE14_Pos) /*!< 0x01000000 */
+#define GPIO_CRH_MODE14_1 (0x2U << GPIO_CRH_MODE14_Pos) /*!< 0x02000000 */
+
+#define GPIO_CRH_MODE15_Pos (28U)
+#define GPIO_CRH_MODE15_Msk (0x3U << GPIO_CRH_MODE15_Pos) /*!< 0x30000000 */
+#define GPIO_CRH_MODE15 GPIO_CRH_MODE15_Msk /*!< MODE15[1:0] bits (Port x mode bits, pin 15) */
+#define GPIO_CRH_MODE15_0 (0x1U << GPIO_CRH_MODE15_Pos) /*!< 0x10000000 */
+#define GPIO_CRH_MODE15_1 (0x2U << GPIO_CRH_MODE15_Pos) /*!< 0x20000000 */
+
+#define GPIO_CRH_CNF_Pos (2U)
+#define GPIO_CRH_CNF_Msk (0x33333333U << GPIO_CRH_CNF_Pos) /*!< 0xCCCCCCCC */
+#define GPIO_CRH_CNF GPIO_CRH_CNF_Msk /*!< Port x configuration bits */
+
+#define GPIO_CRH_CNF8_Pos (2U)
+#define GPIO_CRH_CNF8_Msk (0x3U << GPIO_CRH_CNF8_Pos) /*!< 0x0000000C */
+#define GPIO_CRH_CNF8 GPIO_CRH_CNF8_Msk /*!< CNF8[1:0] bits (Port x configuration bits, pin 8) */
+#define GPIO_CRH_CNF8_0 (0x1U << GPIO_CRH_CNF8_Pos) /*!< 0x00000004 */
+#define GPIO_CRH_CNF8_1 (0x2U << GPIO_CRH_CNF8_Pos) /*!< 0x00000008 */
+
+#define GPIO_CRH_CNF9_Pos (6U)
+#define GPIO_CRH_CNF9_Msk (0x3U << GPIO_CRH_CNF9_Pos) /*!< 0x000000C0 */
+#define GPIO_CRH_CNF9 GPIO_CRH_CNF9_Msk /*!< CNF9[1:0] bits (Port x configuration bits, pin 9) */
+#define GPIO_CRH_CNF9_0 (0x1U << GPIO_CRH_CNF9_Pos) /*!< 0x00000040 */
+#define GPIO_CRH_CNF9_1 (0x2U << GPIO_CRH_CNF9_Pos) /*!< 0x00000080 */
+
+#define GPIO_CRH_CNF10_Pos (10U)
+#define GPIO_CRH_CNF10_Msk (0x3U << GPIO_CRH_CNF10_Pos) /*!< 0x00000C00 */
+#define GPIO_CRH_CNF10 GPIO_CRH_CNF10_Msk /*!< CNF10[1:0] bits (Port x configuration bits, pin 10) */
+#define GPIO_CRH_CNF10_0 (0x1U << GPIO_CRH_CNF10_Pos) /*!< 0x00000400 */
+#define GPIO_CRH_CNF10_1 (0x2U << GPIO_CRH_CNF10_Pos) /*!< 0x00000800 */
+
+#define GPIO_CRH_CNF11_Pos (14U)
+#define GPIO_CRH_CNF11_Msk (0x3U << GPIO_CRH_CNF11_Pos) /*!< 0x0000C000 */
+#define GPIO_CRH_CNF11 GPIO_CRH_CNF11_Msk /*!< CNF11[1:0] bits (Port x configuration bits, pin 11) */
+#define GPIO_CRH_CNF11_0 (0x1U << GPIO_CRH_CNF11_Pos) /*!< 0x00004000 */
+#define GPIO_CRH_CNF11_1 (0x2U << GPIO_CRH_CNF11_Pos) /*!< 0x00008000 */
+
+#define GPIO_CRH_CNF12_Pos (18U)
+#define GPIO_CRH_CNF12_Msk (0x3U << GPIO_CRH_CNF12_Pos) /*!< 0x000C0000 */
+#define GPIO_CRH_CNF12 GPIO_CRH_CNF12_Msk /*!< CNF12[1:0] bits (Port x configuration bits, pin 12) */
+#define GPIO_CRH_CNF12_0 (0x1U << GPIO_CRH_CNF12_Pos) /*!< 0x00040000 */
+#define GPIO_CRH_CNF12_1 (0x2U << GPIO_CRH_CNF12_Pos) /*!< 0x00080000 */
+
+#define GPIO_CRH_CNF13_Pos (22U)
+#define GPIO_CRH_CNF13_Msk (0x3U << GPIO_CRH_CNF13_Pos) /*!< 0x00C00000 */
+#define GPIO_CRH_CNF13 GPIO_CRH_CNF13_Msk /*!< CNF13[1:0] bits (Port x configuration bits, pin 13) */
+#define GPIO_CRH_CNF13_0 (0x1U << GPIO_CRH_CNF13_Pos) /*!< 0x00400000 */
+#define GPIO_CRH_CNF13_1 (0x2U << GPIO_CRH_CNF13_Pos) /*!< 0x00800000 */
+
+#define GPIO_CRH_CNF14_Pos (26U)
+#define GPIO_CRH_CNF14_Msk (0x3U << GPIO_CRH_CNF14_Pos) /*!< 0x0C000000 */
+#define GPIO_CRH_CNF14 GPIO_CRH_CNF14_Msk /*!< CNF14[1:0] bits (Port x configuration bits, pin 14) */
+#define GPIO_CRH_CNF14_0 (0x1U << GPIO_CRH_CNF14_Pos) /*!< 0x04000000 */
+#define GPIO_CRH_CNF14_1 (0x2U << GPIO_CRH_CNF14_Pos) /*!< 0x08000000 */
+
+#define GPIO_CRH_CNF15_Pos (30U)
+#define GPIO_CRH_CNF15_Msk (0x3U << GPIO_CRH_CNF15_Pos) /*!< 0xC0000000 */
+#define GPIO_CRH_CNF15 GPIO_CRH_CNF15_Msk /*!< CNF15[1:0] bits (Port x configuration bits, pin 15) */
+#define GPIO_CRH_CNF15_0 (0x1U << GPIO_CRH_CNF15_Pos) /*!< 0x40000000 */
+#define GPIO_CRH_CNF15_1 (0x2U << GPIO_CRH_CNF15_Pos) /*!< 0x80000000 */
+
+/*!<****************** Bit definition for GPIO_IDR register *******************/
+#define GPIO_IDR_IDR0_Pos (0U)
+#define GPIO_IDR_IDR0_Msk (0x1U << GPIO_IDR_IDR0_Pos) /*!< 0x00000001 */
+#define GPIO_IDR_IDR0 GPIO_IDR_IDR0_Msk /*!< Port input data, bit 0 */
+#define GPIO_IDR_IDR1_Pos (1U)
+#define GPIO_IDR_IDR1_Msk (0x1U << GPIO_IDR_IDR1_Pos) /*!< 0x00000002 */
+#define GPIO_IDR_IDR1 GPIO_IDR_IDR1_Msk /*!< Port input data, bit 1 */
+#define GPIO_IDR_IDR2_Pos (2U)
+#define GPIO_IDR_IDR2_Msk (0x1U << GPIO_IDR_IDR2_Pos) /*!< 0x00000004 */
+#define GPIO_IDR_IDR2 GPIO_IDR_IDR2_Msk /*!< Port input data, bit 2 */
+#define GPIO_IDR_IDR3_Pos (3U)
+#define GPIO_IDR_IDR3_Msk (0x1U << GPIO_IDR_IDR3_Pos) /*!< 0x00000008 */
+#define GPIO_IDR_IDR3 GPIO_IDR_IDR3_Msk /*!< Port input data, bit 3 */
+#define GPIO_IDR_IDR4_Pos (4U)
+#define GPIO_IDR_IDR4_Msk (0x1U << GPIO_IDR_IDR4_Pos) /*!< 0x00000010 */
+#define GPIO_IDR_IDR4 GPIO_IDR_IDR4_Msk /*!< Port input data, bit 4 */
+#define GPIO_IDR_IDR5_Pos (5U)
+#define GPIO_IDR_IDR5_Msk (0x1U << GPIO_IDR_IDR5_Pos) /*!< 0x00000020 */
+#define GPIO_IDR_IDR5 GPIO_IDR_IDR5_Msk /*!< Port input data, bit 5 */
+#define GPIO_IDR_IDR6_Pos (6U)
+#define GPIO_IDR_IDR6_Msk (0x1U << GPIO_IDR_IDR6_Pos) /*!< 0x00000040 */
+#define GPIO_IDR_IDR6 GPIO_IDR_IDR6_Msk /*!< Port input data, bit 6 */
+#define GPIO_IDR_IDR7_Pos (7U)
+#define GPIO_IDR_IDR7_Msk (0x1U << GPIO_IDR_IDR7_Pos) /*!< 0x00000080 */
+#define GPIO_IDR_IDR7 GPIO_IDR_IDR7_Msk /*!< Port input data, bit 7 */
+#define GPIO_IDR_IDR8_Pos (8U)
+#define GPIO_IDR_IDR8_Msk (0x1U << GPIO_IDR_IDR8_Pos) /*!< 0x00000100 */
+#define GPIO_IDR_IDR8 GPIO_IDR_IDR8_Msk /*!< Port input data, bit 8 */
+#define GPIO_IDR_IDR9_Pos (9U)
+#define GPIO_IDR_IDR9_Msk (0x1U << GPIO_IDR_IDR9_Pos) /*!< 0x00000200 */
+#define GPIO_IDR_IDR9 GPIO_IDR_IDR9_Msk /*!< Port input data, bit 9 */
+#define GPIO_IDR_IDR10_Pos (10U)
+#define GPIO_IDR_IDR10_Msk (0x1U << GPIO_IDR_IDR10_Pos) /*!< 0x00000400 */
+#define GPIO_IDR_IDR10 GPIO_IDR_IDR10_Msk /*!< Port input data, bit 10 */
+#define GPIO_IDR_IDR11_Pos (11U)
+#define GPIO_IDR_IDR11_Msk (0x1U << GPIO_IDR_IDR11_Pos) /*!< 0x00000800 */
+#define GPIO_IDR_IDR11 GPIO_IDR_IDR11_Msk /*!< Port input data, bit 11 */
+#define GPIO_IDR_IDR12_Pos (12U)
+#define GPIO_IDR_IDR12_Msk (0x1U << GPIO_IDR_IDR12_Pos) /*!< 0x00001000 */
+#define GPIO_IDR_IDR12 GPIO_IDR_IDR12_Msk /*!< Port input data, bit 12 */
+#define GPIO_IDR_IDR13_Pos (13U)
+#define GPIO_IDR_IDR13_Msk (0x1U << GPIO_IDR_IDR13_Pos) /*!< 0x00002000 */
+#define GPIO_IDR_IDR13 GPIO_IDR_IDR13_Msk /*!< Port input data, bit 13 */
+#define GPIO_IDR_IDR14_Pos (14U)
+#define GPIO_IDR_IDR14_Msk (0x1U << GPIO_IDR_IDR14_Pos) /*!< 0x00004000 */
+#define GPIO_IDR_IDR14 GPIO_IDR_IDR14_Msk /*!< Port input data, bit 14 */
+#define GPIO_IDR_IDR15_Pos (15U)
+#define GPIO_IDR_IDR15_Msk (0x1U << GPIO_IDR_IDR15_Pos) /*!< 0x00008000 */
+#define GPIO_IDR_IDR15 GPIO_IDR_IDR15_Msk /*!< Port input data, bit 15 */
+
+/******************* Bit definition for GPIO_ODR register *******************/
+#define GPIO_ODR_ODR0_Pos (0U)
+#define GPIO_ODR_ODR0_Msk (0x1U << GPIO_ODR_ODR0_Pos) /*!< 0x00000001 */
+#define GPIO_ODR_ODR0 GPIO_ODR_ODR0_Msk /*!< Port output data, bit 0 */
+#define GPIO_ODR_ODR1_Pos (1U)
+#define GPIO_ODR_ODR1_Msk (0x1U << GPIO_ODR_ODR1_Pos) /*!< 0x00000002 */
+#define GPIO_ODR_ODR1 GPIO_ODR_ODR1_Msk /*!< Port output data, bit 1 */
+#define GPIO_ODR_ODR2_Pos (2U)
+#define GPIO_ODR_ODR2_Msk (0x1U << GPIO_ODR_ODR2_Pos) /*!< 0x00000004 */
+#define GPIO_ODR_ODR2 GPIO_ODR_ODR2_Msk /*!< Port output data, bit 2 */
+#define GPIO_ODR_ODR3_Pos (3U)
+#define GPIO_ODR_ODR3_Msk (0x1U << GPIO_ODR_ODR3_Pos) /*!< 0x00000008 */
+#define GPIO_ODR_ODR3 GPIO_ODR_ODR3_Msk /*!< Port output data, bit 3 */
+#define GPIO_ODR_ODR4_Pos (4U)
+#define GPIO_ODR_ODR4_Msk (0x1U << GPIO_ODR_ODR4_Pos) /*!< 0x00000010 */
+#define GPIO_ODR_ODR4 GPIO_ODR_ODR4_Msk /*!< Port output data, bit 4 */
+#define GPIO_ODR_ODR5_Pos (5U)
+#define GPIO_ODR_ODR5_Msk (0x1U << GPIO_ODR_ODR5_Pos) /*!< 0x00000020 */
+#define GPIO_ODR_ODR5 GPIO_ODR_ODR5_Msk /*!< Port output data, bit 5 */
+#define GPIO_ODR_ODR6_Pos (6U)
+#define GPIO_ODR_ODR6_Msk (0x1U << GPIO_ODR_ODR6_Pos) /*!< 0x00000040 */
+#define GPIO_ODR_ODR6 GPIO_ODR_ODR6_Msk /*!< Port output data, bit 6 */
+#define GPIO_ODR_ODR7_Pos (7U)
+#define GPIO_ODR_ODR7_Msk (0x1U << GPIO_ODR_ODR7_Pos) /*!< 0x00000080 */
+#define GPIO_ODR_ODR7 GPIO_ODR_ODR7_Msk /*!< Port output data, bit 7 */
+#define GPIO_ODR_ODR8_Pos (8U)
+#define GPIO_ODR_ODR8_Msk (0x1U << GPIO_ODR_ODR8_Pos) /*!< 0x00000100 */
+#define GPIO_ODR_ODR8 GPIO_ODR_ODR8_Msk /*!< Port output data, bit 8 */
+#define GPIO_ODR_ODR9_Pos (9U)
+#define GPIO_ODR_ODR9_Msk (0x1U << GPIO_ODR_ODR9_Pos) /*!< 0x00000200 */
+#define GPIO_ODR_ODR9 GPIO_ODR_ODR9_Msk /*!< Port output data, bit 9 */
+#define GPIO_ODR_ODR10_Pos (10U)
+#define GPIO_ODR_ODR10_Msk (0x1U << GPIO_ODR_ODR10_Pos) /*!< 0x00000400 */
+#define GPIO_ODR_ODR10 GPIO_ODR_ODR10_Msk /*!< Port output data, bit 10 */
+#define GPIO_ODR_ODR11_Pos (11U)
+#define GPIO_ODR_ODR11_Msk (0x1U << GPIO_ODR_ODR11_Pos) /*!< 0x00000800 */
+#define GPIO_ODR_ODR11 GPIO_ODR_ODR11_Msk /*!< Port output data, bit 11 */
+#define GPIO_ODR_ODR12_Pos (12U)
+#define GPIO_ODR_ODR12_Msk (0x1U << GPIO_ODR_ODR12_Pos) /*!< 0x00001000 */
+#define GPIO_ODR_ODR12 GPIO_ODR_ODR12_Msk /*!< Port output data, bit 12 */
+#define GPIO_ODR_ODR13_Pos (13U)
+#define GPIO_ODR_ODR13_Msk (0x1U << GPIO_ODR_ODR13_Pos) /*!< 0x00002000 */
+#define GPIO_ODR_ODR13 GPIO_ODR_ODR13_Msk /*!< Port output data, bit 13 */
+#define GPIO_ODR_ODR14_Pos (14U)
+#define GPIO_ODR_ODR14_Msk (0x1U << GPIO_ODR_ODR14_Pos) /*!< 0x00004000 */
+#define GPIO_ODR_ODR14 GPIO_ODR_ODR14_Msk /*!< Port output data, bit 14 */
+#define GPIO_ODR_ODR15_Pos (15U)
+#define GPIO_ODR_ODR15_Msk (0x1U << GPIO_ODR_ODR15_Pos) /*!< 0x00008000 */
+#define GPIO_ODR_ODR15 GPIO_ODR_ODR15_Msk /*!< Port output data, bit 15 */
+
+/****************** Bit definition for GPIO_BSRR register *******************/
+#define GPIO_BSRR_BS0_Pos (0U)
+#define GPIO_BSRR_BS0_Msk (0x1U << GPIO_BSRR_BS0_Pos) /*!< 0x00000001 */
+#define GPIO_BSRR_BS0 GPIO_BSRR_BS0_Msk /*!< Port x Set bit 0 */
+#define GPIO_BSRR_BS1_Pos (1U)
+#define GPIO_BSRR_BS1_Msk (0x1U << GPIO_BSRR_BS1_Pos) /*!< 0x00000002 */
+#define GPIO_BSRR_BS1 GPIO_BSRR_BS1_Msk /*!< Port x Set bit 1 */
+#define GPIO_BSRR_BS2_Pos (2U)
+#define GPIO_BSRR_BS2_Msk (0x1U << GPIO_BSRR_BS2_Pos) /*!< 0x00000004 */
+#define GPIO_BSRR_BS2 GPIO_BSRR_BS2_Msk /*!< Port x Set bit 2 */
+#define GPIO_BSRR_BS3_Pos (3U)
+#define GPIO_BSRR_BS3_Msk (0x1U << GPIO_BSRR_BS3_Pos) /*!< 0x00000008 */
+#define GPIO_BSRR_BS3 GPIO_BSRR_BS3_Msk /*!< Port x Set bit 3 */
+#define GPIO_BSRR_BS4_Pos (4U)
+#define GPIO_BSRR_BS4_Msk (0x1U << GPIO_BSRR_BS4_Pos) /*!< 0x00000010 */
+#define GPIO_BSRR_BS4 GPIO_BSRR_BS4_Msk /*!< Port x Set bit 4 */
+#define GPIO_BSRR_BS5_Pos (5U)
+#define GPIO_BSRR_BS5_Msk (0x1U << GPIO_BSRR_BS5_Pos) /*!< 0x00000020 */
+#define GPIO_BSRR_BS5 GPIO_BSRR_BS5_Msk /*!< Port x Set bit 5 */
+#define GPIO_BSRR_BS6_Pos (6U)
+#define GPIO_BSRR_BS6_Msk (0x1U << GPIO_BSRR_BS6_Pos) /*!< 0x00000040 */
+#define GPIO_BSRR_BS6 GPIO_BSRR_BS6_Msk /*!< Port x Set bit 6 */
+#define GPIO_BSRR_BS7_Pos (7U)
+#define GPIO_BSRR_BS7_Msk (0x1U << GPIO_BSRR_BS7_Pos) /*!< 0x00000080 */
+#define GPIO_BSRR_BS7 GPIO_BSRR_BS7_Msk /*!< Port x Set bit 7 */
+#define GPIO_BSRR_BS8_Pos (8U)
+#define GPIO_BSRR_BS8_Msk (0x1U << GPIO_BSRR_BS8_Pos) /*!< 0x00000100 */
+#define GPIO_BSRR_BS8 GPIO_BSRR_BS8_Msk /*!< Port x Set bit 8 */
+#define GPIO_BSRR_BS9_Pos (9U)
+#define GPIO_BSRR_BS9_Msk (0x1U << GPIO_BSRR_BS9_Pos) /*!< 0x00000200 */
+#define GPIO_BSRR_BS9 GPIO_BSRR_BS9_Msk /*!< Port x Set bit 9 */
+#define GPIO_BSRR_BS10_Pos (10U)
+#define GPIO_BSRR_BS10_Msk (0x1U << GPIO_BSRR_BS10_Pos) /*!< 0x00000400 */
+#define GPIO_BSRR_BS10 GPIO_BSRR_BS10_Msk /*!< Port x Set bit 10 */
+#define GPIO_BSRR_BS11_Pos (11U)
+#define GPIO_BSRR_BS11_Msk (0x1U << GPIO_BSRR_BS11_Pos) /*!< 0x00000800 */
+#define GPIO_BSRR_BS11 GPIO_BSRR_BS11_Msk /*!< Port x Set bit 11 */
+#define GPIO_BSRR_BS12_Pos (12U)
+#define GPIO_BSRR_BS12_Msk (0x1U << GPIO_BSRR_BS12_Pos) /*!< 0x00001000 */
+#define GPIO_BSRR_BS12 GPIO_BSRR_BS12_Msk /*!< Port x Set bit 12 */
+#define GPIO_BSRR_BS13_Pos (13U)
+#define GPIO_BSRR_BS13_Msk (0x1U << GPIO_BSRR_BS13_Pos) /*!< 0x00002000 */
+#define GPIO_BSRR_BS13 GPIO_BSRR_BS13_Msk /*!< Port x Set bit 13 */
+#define GPIO_BSRR_BS14_Pos (14U)
+#define GPIO_BSRR_BS14_Msk (0x1U << GPIO_BSRR_BS14_Pos) /*!< 0x00004000 */
+#define GPIO_BSRR_BS14 GPIO_BSRR_BS14_Msk /*!< Port x Set bit 14 */
+#define GPIO_BSRR_BS15_Pos (15U)
+#define GPIO_BSRR_BS15_Msk (0x1U << GPIO_BSRR_BS15_Pos) /*!< 0x00008000 */
+#define GPIO_BSRR_BS15 GPIO_BSRR_BS15_Msk /*!< Port x Set bit 15 */
+
+#define GPIO_BSRR_BR0_Pos (16U)
+#define GPIO_BSRR_BR0_Msk (0x1U << GPIO_BSRR_BR0_Pos) /*!< 0x00010000 */
+#define GPIO_BSRR_BR0 GPIO_BSRR_BR0_Msk /*!< Port x Reset bit 0 */
+#define GPIO_BSRR_BR1_Pos (17U)
+#define GPIO_BSRR_BR1_Msk (0x1U << GPIO_BSRR_BR1_Pos) /*!< 0x00020000 */
+#define GPIO_BSRR_BR1 GPIO_BSRR_BR1_Msk /*!< Port x Reset bit 1 */
+#define GPIO_BSRR_BR2_Pos (18U)
+#define GPIO_BSRR_BR2_Msk (0x1U << GPIO_BSRR_BR2_Pos) /*!< 0x00040000 */
+#define GPIO_BSRR_BR2 GPIO_BSRR_BR2_Msk /*!< Port x Reset bit 2 */
+#define GPIO_BSRR_BR3_Pos (19U)
+#define GPIO_BSRR_BR3_Msk (0x1U << GPIO_BSRR_BR3_Pos) /*!< 0x00080000 */
+#define GPIO_BSRR_BR3 GPIO_BSRR_BR3_Msk /*!< Port x Reset bit 3 */
+#define GPIO_BSRR_BR4_Pos (20U)
+#define GPIO_BSRR_BR4_Msk (0x1U << GPIO_BSRR_BR4_Pos) /*!< 0x00100000 */
+#define GPIO_BSRR_BR4 GPIO_BSRR_BR4_Msk /*!< Port x Reset bit 4 */
+#define GPIO_BSRR_BR5_Pos (21U)
+#define GPIO_BSRR_BR5_Msk (0x1U << GPIO_BSRR_BR5_Pos) /*!< 0x00200000 */
+#define GPIO_BSRR_BR5 GPIO_BSRR_BR5_Msk /*!< Port x Reset bit 5 */
+#define GPIO_BSRR_BR6_Pos (22U)
+#define GPIO_BSRR_BR6_Msk (0x1U << GPIO_BSRR_BR6_Pos) /*!< 0x00400000 */
+#define GPIO_BSRR_BR6 GPIO_BSRR_BR6_Msk /*!< Port x Reset bit 6 */
+#define GPIO_BSRR_BR7_Pos (23U)
+#define GPIO_BSRR_BR7_Msk (0x1U << GPIO_BSRR_BR7_Pos) /*!< 0x00800000 */
+#define GPIO_BSRR_BR7 GPIO_BSRR_BR7_Msk /*!< Port x Reset bit 7 */
+#define GPIO_BSRR_BR8_Pos (24U)
+#define GPIO_BSRR_BR8_Msk (0x1U << GPIO_BSRR_BR8_Pos) /*!< 0x01000000 */
+#define GPIO_BSRR_BR8 GPIO_BSRR_BR8_Msk /*!< Port x Reset bit 8 */
+#define GPIO_BSRR_BR9_Pos (25U)
+#define GPIO_BSRR_BR9_Msk (0x1U << GPIO_BSRR_BR9_Pos) /*!< 0x02000000 */
+#define GPIO_BSRR_BR9 GPIO_BSRR_BR9_Msk /*!< Port x Reset bit 9 */
+#define GPIO_BSRR_BR10_Pos (26U)
+#define GPIO_BSRR_BR10_Msk (0x1U << GPIO_BSRR_BR10_Pos) /*!< 0x04000000 */
+#define GPIO_BSRR_BR10 GPIO_BSRR_BR10_Msk /*!< Port x Reset bit 10 */
+#define GPIO_BSRR_BR11_Pos (27U)
+#define GPIO_BSRR_BR11_Msk (0x1U << GPIO_BSRR_BR11_Pos) /*!< 0x08000000 */
+#define GPIO_BSRR_BR11 GPIO_BSRR_BR11_Msk /*!< Port x Reset bit 11 */
+#define GPIO_BSRR_BR12_Pos (28U)
+#define GPIO_BSRR_BR12_Msk (0x1U << GPIO_BSRR_BR12_Pos) /*!< 0x10000000 */
+#define GPIO_BSRR_BR12 GPIO_BSRR_BR12_Msk /*!< Port x Reset bit 12 */
+#define GPIO_BSRR_BR13_Pos (29U)
+#define GPIO_BSRR_BR13_Msk (0x1U << GPIO_BSRR_BR13_Pos) /*!< 0x20000000 */
+#define GPIO_BSRR_BR13 GPIO_BSRR_BR13_Msk /*!< Port x Reset bit 13 */
+#define GPIO_BSRR_BR14_Pos (30U)
+#define GPIO_BSRR_BR14_Msk (0x1U << GPIO_BSRR_BR14_Pos) /*!< 0x40000000 */
+#define GPIO_BSRR_BR14 GPIO_BSRR_BR14_Msk /*!< Port x Reset bit 14 */
+#define GPIO_BSRR_BR15_Pos (31U)
+#define GPIO_BSRR_BR15_Msk (0x1U << GPIO_BSRR_BR15_Pos) /*!< 0x80000000 */
+#define GPIO_BSRR_BR15 GPIO_BSRR_BR15_Msk /*!< Port x Reset bit 15 */
+
+/******************* Bit definition for GPIO_BRR register *******************/
+#define GPIO_BRR_BR0_Pos (0U)
+#define GPIO_BRR_BR0_Msk (0x1U << GPIO_BRR_BR0_Pos) /*!< 0x00000001 */
+#define GPIO_BRR_BR0 GPIO_BRR_BR0_Msk /*!< Port x Reset bit 0 */
+#define GPIO_BRR_BR1_Pos (1U)
+#define GPIO_BRR_BR1_Msk (0x1U << GPIO_BRR_BR1_Pos) /*!< 0x00000002 */
+#define GPIO_BRR_BR1 GPIO_BRR_BR1_Msk /*!< Port x Reset bit 1 */
+#define GPIO_BRR_BR2_Pos (2U)
+#define GPIO_BRR_BR2_Msk (0x1U << GPIO_BRR_BR2_Pos) /*!< 0x00000004 */
+#define GPIO_BRR_BR2 GPIO_BRR_BR2_Msk /*!< Port x Reset bit 2 */
+#define GPIO_BRR_BR3_Pos (3U)
+#define GPIO_BRR_BR3_Msk (0x1U << GPIO_BRR_BR3_Pos) /*!< 0x00000008 */
+#define GPIO_BRR_BR3 GPIO_BRR_BR3_Msk /*!< Port x Reset bit 3 */
+#define GPIO_BRR_BR4_Pos (4U)
+#define GPIO_BRR_BR4_Msk (0x1U << GPIO_BRR_BR4_Pos) /*!< 0x00000010 */
+#define GPIO_BRR_BR4 GPIO_BRR_BR4_Msk /*!< Port x Reset bit 4 */
+#define GPIO_BRR_BR5_Pos (5U)
+#define GPIO_BRR_BR5_Msk (0x1U << GPIO_BRR_BR5_Pos) /*!< 0x00000020 */
+#define GPIO_BRR_BR5 GPIO_BRR_BR5_Msk /*!< Port x Reset bit 5 */
+#define GPIO_BRR_BR6_Pos (6U)
+#define GPIO_BRR_BR6_Msk (0x1U << GPIO_BRR_BR6_Pos) /*!< 0x00000040 */
+#define GPIO_BRR_BR6 GPIO_BRR_BR6_Msk /*!< Port x Reset bit 6 */
+#define GPIO_BRR_BR7_Pos (7U)
+#define GPIO_BRR_BR7_Msk (0x1U << GPIO_BRR_BR7_Pos) /*!< 0x00000080 */
+#define GPIO_BRR_BR7 GPIO_BRR_BR7_Msk /*!< Port x Reset bit 7 */
+#define GPIO_BRR_BR8_Pos (8U)
+#define GPIO_BRR_BR8_Msk (0x1U << GPIO_BRR_BR8_Pos) /*!< 0x00000100 */
+#define GPIO_BRR_BR8 GPIO_BRR_BR8_Msk /*!< Port x Reset bit 8 */
+#define GPIO_BRR_BR9_Pos (9U)
+#define GPIO_BRR_BR9_Msk (0x1U << GPIO_BRR_BR9_Pos) /*!< 0x00000200 */
+#define GPIO_BRR_BR9 GPIO_BRR_BR9_Msk /*!< Port x Reset bit 9 */
+#define GPIO_BRR_BR10_Pos (10U)
+#define GPIO_BRR_BR10_Msk (0x1U << GPIO_BRR_BR10_Pos) /*!< 0x00000400 */
+#define GPIO_BRR_BR10 GPIO_BRR_BR10_Msk /*!< Port x Reset bit 10 */
+#define GPIO_BRR_BR11_Pos (11U)
+#define GPIO_BRR_BR11_Msk (0x1U << GPIO_BRR_BR11_Pos) /*!< 0x00000800 */
+#define GPIO_BRR_BR11 GPIO_BRR_BR11_Msk /*!< Port x Reset bit 11 */
+#define GPIO_BRR_BR12_Pos (12U)
+#define GPIO_BRR_BR12_Msk (0x1U << GPIO_BRR_BR12_Pos) /*!< 0x00001000 */
+#define GPIO_BRR_BR12 GPIO_BRR_BR12_Msk /*!< Port x Reset bit 12 */
+#define GPIO_BRR_BR13_Pos (13U)
+#define GPIO_BRR_BR13_Msk (0x1U << GPIO_BRR_BR13_Pos) /*!< 0x00002000 */
+#define GPIO_BRR_BR13 GPIO_BRR_BR13_Msk /*!< Port x Reset bit 13 */
+#define GPIO_BRR_BR14_Pos (14U)
+#define GPIO_BRR_BR14_Msk (0x1U << GPIO_BRR_BR14_Pos) /*!< 0x00004000 */
+#define GPIO_BRR_BR14 GPIO_BRR_BR14_Msk /*!< Port x Reset bit 14 */
+#define GPIO_BRR_BR15_Pos (15U)
+#define GPIO_BRR_BR15_Msk (0x1U << GPIO_BRR_BR15_Pos) /*!< 0x00008000 */
+#define GPIO_BRR_BR15 GPIO_BRR_BR15_Msk /*!< Port x Reset bit 15 */
+
+/****************** Bit definition for GPIO_LCKR register *******************/
+#define GPIO_LCKR_LCK0_Pos (0U)
+#define GPIO_LCKR_LCK0_Msk (0x1U << GPIO_LCKR_LCK0_Pos) /*!< 0x00000001 */
+#define GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk /*!< Port x Lock bit 0 */
+#define GPIO_LCKR_LCK1_Pos (1U)
+#define GPIO_LCKR_LCK1_Msk (0x1U << GPIO_LCKR_LCK1_Pos) /*!< 0x00000002 */
+#define GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk /*!< Port x Lock bit 1 */
+#define GPIO_LCKR_LCK2_Pos (2U)
+#define GPIO_LCKR_LCK2_Msk (0x1U << GPIO_LCKR_LCK2_Pos) /*!< 0x00000004 */
+#define GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk /*!< Port x Lock bit 2 */
+#define GPIO_LCKR_LCK3_Pos (3U)
+#define GPIO_LCKR_LCK3_Msk (0x1U << GPIO_LCKR_LCK3_Pos) /*!< 0x00000008 */
+#define GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk /*!< Port x Lock bit 3 */
+#define GPIO_LCKR_LCK4_Pos (4U)
+#define GPIO_LCKR_LCK4_Msk (0x1U << GPIO_LCKR_LCK4_Pos) /*!< 0x00000010 */
+#define GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk /*!< Port x Lock bit 4 */
+#define GPIO_LCKR_LCK5_Pos (5U)
+#define GPIO_LCKR_LCK5_Msk (0x1U << GPIO_LCKR_LCK5_Pos) /*!< 0x00000020 */
+#define GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk /*!< Port x Lock bit 5 */
+#define GPIO_LCKR_LCK6_Pos (6U)
+#define GPIO_LCKR_LCK6_Msk (0x1U << GPIO_LCKR_LCK6_Pos) /*!< 0x00000040 */
+#define GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk /*!< Port x Lock bit 6 */
+#define GPIO_LCKR_LCK7_Pos (7U)
+#define GPIO_LCKR_LCK7_Msk (0x1U << GPIO_LCKR_LCK7_Pos) /*!< 0x00000080 */
+#define GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk /*!< Port x Lock bit 7 */
+#define GPIO_LCKR_LCK8_Pos (8U)
+#define GPIO_LCKR_LCK8_Msk (0x1U << GPIO_LCKR_LCK8_Pos) /*!< 0x00000100 */
+#define GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk /*!< Port x Lock bit 8 */
+#define GPIO_LCKR_LCK9_Pos (9U)
+#define GPIO_LCKR_LCK9_Msk (0x1U << GPIO_LCKR_LCK9_Pos) /*!< 0x00000200 */
+#define GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk /*!< Port x Lock bit 9 */
+#define GPIO_LCKR_LCK10_Pos (10U)
+#define GPIO_LCKR_LCK10_Msk (0x1U << GPIO_LCKR_LCK10_Pos) /*!< 0x00000400 */
+#define GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk /*!< Port x Lock bit 10 */
+#define GPIO_LCKR_LCK11_Pos (11U)
+#define GPIO_LCKR_LCK11_Msk (0x1U << GPIO_LCKR_LCK11_Pos) /*!< 0x00000800 */
+#define GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk /*!< Port x Lock bit 11 */
+#define GPIO_LCKR_LCK12_Pos (12U)
+#define GPIO_LCKR_LCK12_Msk (0x1U << GPIO_LCKR_LCK12_Pos) /*!< 0x00001000 */
+#define GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk /*!< Port x Lock bit 12 */
+#define GPIO_LCKR_LCK13_Pos (13U)
+#define GPIO_LCKR_LCK13_Msk (0x1U << GPIO_LCKR_LCK13_Pos) /*!< 0x00002000 */
+#define GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk /*!< Port x Lock bit 13 */
+#define GPIO_LCKR_LCK14_Pos (14U)
+#define GPIO_LCKR_LCK14_Msk (0x1U << GPIO_LCKR_LCK14_Pos) /*!< 0x00004000 */
+#define GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk /*!< Port x Lock bit 14 */
+#define GPIO_LCKR_LCK15_Pos (15U)
+#define GPIO_LCKR_LCK15_Msk (0x1U << GPIO_LCKR_LCK15_Pos) /*!< 0x00008000 */
+#define GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk /*!< Port x Lock bit 15 */
+#define GPIO_LCKR_LCKK_Pos (16U)
+#define GPIO_LCKR_LCKK_Msk (0x1U << GPIO_LCKR_LCKK_Pos) /*!< 0x00010000 */
+#define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk /*!< Lock key */
+
+/*----------------------------------------------------------------------------*/
+
+/****************** Bit definition for AFIO_EVCR register *******************/
+#define AFIO_EVCR_PIN_Pos (0U)
+#define AFIO_EVCR_PIN_Msk (0xFU << AFIO_EVCR_PIN_Pos) /*!< 0x0000000F */
+#define AFIO_EVCR_PIN AFIO_EVCR_PIN_Msk /*!< PIN[3:0] bits (Pin selection) */
+#define AFIO_EVCR_PIN_0 (0x1U << AFIO_EVCR_PIN_Pos) /*!< 0x00000001 */
+#define AFIO_EVCR_PIN_1 (0x2U << AFIO_EVCR_PIN_Pos) /*!< 0x00000002 */
+#define AFIO_EVCR_PIN_2 (0x4U << AFIO_EVCR_PIN_Pos) /*!< 0x00000004 */
+#define AFIO_EVCR_PIN_3 (0x8U << AFIO_EVCR_PIN_Pos) /*!< 0x00000008 */
+
+/*!< PIN configuration */
+#define AFIO_EVCR_PIN_PX0 ((uint32_t)0x00000000) /*!< Pin 0 selected */
+#define AFIO_EVCR_PIN_PX1_Pos (0U)
+#define AFIO_EVCR_PIN_PX1_Msk (0x1U << AFIO_EVCR_PIN_PX1_Pos) /*!< 0x00000001 */
+#define AFIO_EVCR_PIN_PX1 AFIO_EVCR_PIN_PX1_Msk /*!< Pin 1 selected */
+#define AFIO_EVCR_PIN_PX2_Pos (1U)
+#define AFIO_EVCR_PIN_PX2_Msk (0x1U << AFIO_EVCR_PIN_PX2_Pos) /*!< 0x00000002 */
+#define AFIO_EVCR_PIN_PX2 AFIO_EVCR_PIN_PX2_Msk /*!< Pin 2 selected */
+#define AFIO_EVCR_PIN_PX3_Pos (0U)
+#define AFIO_EVCR_PIN_PX3_Msk (0x3U << AFIO_EVCR_PIN_PX3_Pos) /*!< 0x00000003 */
+#define AFIO_EVCR_PIN_PX3 AFIO_EVCR_PIN_PX3_Msk /*!< Pin 3 selected */
+#define AFIO_EVCR_PIN_PX4_Pos (2U)
+#define AFIO_EVCR_PIN_PX4_Msk (0x1U << AFIO_EVCR_PIN_PX4_Pos) /*!< 0x00000004 */
+#define AFIO_EVCR_PIN_PX4 AFIO_EVCR_PIN_PX4_Msk /*!< Pin 4 selected */
+#define AFIO_EVCR_PIN_PX5_Pos (0U)
+#define AFIO_EVCR_PIN_PX5_Msk (0x5U << AFIO_EVCR_PIN_PX5_Pos) /*!< 0x00000005 */
+#define AFIO_EVCR_PIN_PX5 AFIO_EVCR_PIN_PX5_Msk /*!< Pin 5 selected */
+#define AFIO_EVCR_PIN_PX6_Pos (1U)
+#define AFIO_EVCR_PIN_PX6_Msk (0x3U << AFIO_EVCR_PIN_PX6_Pos) /*!< 0x00000006 */
+#define AFIO_EVCR_PIN_PX6 AFIO_EVCR_PIN_PX6_Msk /*!< Pin 6 selected */
+#define AFIO_EVCR_PIN_PX7_Pos (0U)
+#define AFIO_EVCR_PIN_PX7_Msk (0x7U << AFIO_EVCR_PIN_PX7_Pos) /*!< 0x00000007 */
+#define AFIO_EVCR_PIN_PX7 AFIO_EVCR_PIN_PX7_Msk /*!< Pin 7 selected */
+#define AFIO_EVCR_PIN_PX8_Pos (3U)
+#define AFIO_EVCR_PIN_PX8_Msk (0x1U << AFIO_EVCR_PIN_PX8_Pos) /*!< 0x00000008 */
+#define AFIO_EVCR_PIN_PX8 AFIO_EVCR_PIN_PX8_Msk /*!< Pin 8 selected */
+#define AFIO_EVCR_PIN_PX9_Pos (0U)
+#define AFIO_EVCR_PIN_PX9_Msk (0x9U << AFIO_EVCR_PIN_PX9_Pos) /*!< 0x00000009 */
+#define AFIO_EVCR_PIN_PX9 AFIO_EVCR_PIN_PX9_Msk /*!< Pin 9 selected */
+#define AFIO_EVCR_PIN_PX10_Pos (1U)
+#define AFIO_EVCR_PIN_PX10_Msk (0x5U << AFIO_EVCR_PIN_PX10_Pos) /*!< 0x0000000A */
+#define AFIO_EVCR_PIN_PX10 AFIO_EVCR_PIN_PX10_Msk /*!< Pin 10 selected */
+#define AFIO_EVCR_PIN_PX11_Pos (0U)
+#define AFIO_EVCR_PIN_PX11_Msk (0xBU << AFIO_EVCR_PIN_PX11_Pos) /*!< 0x0000000B */
+#define AFIO_EVCR_PIN_PX11 AFIO_EVCR_PIN_PX11_Msk /*!< Pin 11 selected */
+#define AFIO_EVCR_PIN_PX12_Pos (2U)
+#define AFIO_EVCR_PIN_PX12_Msk (0x3U << AFIO_EVCR_PIN_PX12_Pos) /*!< 0x0000000C */
+#define AFIO_EVCR_PIN_PX12 AFIO_EVCR_PIN_PX12_Msk /*!< Pin 12 selected */
+#define AFIO_EVCR_PIN_PX13_Pos (0U)
+#define AFIO_EVCR_PIN_PX13_Msk (0xDU << AFIO_EVCR_PIN_PX13_Pos) /*!< 0x0000000D */
+#define AFIO_EVCR_PIN_PX13 AFIO_EVCR_PIN_PX13_Msk /*!< Pin 13 selected */
+#define AFIO_EVCR_PIN_PX14_Pos (1U)
+#define AFIO_EVCR_PIN_PX14_Msk (0x7U << AFIO_EVCR_PIN_PX14_Pos) /*!< 0x0000000E */
+#define AFIO_EVCR_PIN_PX14 AFIO_EVCR_PIN_PX14_Msk /*!< Pin 14 selected */
+#define AFIO_EVCR_PIN_PX15_Pos (0U)
+#define AFIO_EVCR_PIN_PX15_Msk (0xFU << AFIO_EVCR_PIN_PX15_Pos) /*!< 0x0000000F */
+#define AFIO_EVCR_PIN_PX15 AFIO_EVCR_PIN_PX15_Msk /*!< Pin 15 selected */
+
+#define AFIO_EVCR_PORT_Pos (4U)
+#define AFIO_EVCR_PORT_Msk (0x7U << AFIO_EVCR_PORT_Pos) /*!< 0x00000070 */
+#define AFIO_EVCR_PORT AFIO_EVCR_PORT_Msk /*!< PORT[2:0] bits (Port selection) */
+#define AFIO_EVCR_PORT_0 (0x1U << AFIO_EVCR_PORT_Pos) /*!< 0x00000010 */
+#define AFIO_EVCR_PORT_1 (0x2U << AFIO_EVCR_PORT_Pos) /*!< 0x00000020 */
+#define AFIO_EVCR_PORT_2 (0x4U << AFIO_EVCR_PORT_Pos) /*!< 0x00000040 */
+
+/*!< PORT configuration */
+#define AFIO_EVCR_PORT_PA ((uint32_t)0x00000000) /*!< Port A selected */
+#define AFIO_EVCR_PORT_PB_Pos (4U)
+#define AFIO_EVCR_PORT_PB_Msk (0x1U << AFIO_EVCR_PORT_PB_Pos) /*!< 0x00000010 */
+#define AFIO_EVCR_PORT_PB AFIO_EVCR_PORT_PB_Msk /*!< Port B selected */
+#define AFIO_EVCR_PORT_PC_Pos (5U)
+#define AFIO_EVCR_PORT_PC_Msk (0x1U << AFIO_EVCR_PORT_PC_Pos) /*!< 0x00000020 */
+#define AFIO_EVCR_PORT_PC AFIO_EVCR_PORT_PC_Msk /*!< Port C selected */
+#define AFIO_EVCR_PORT_PD_Pos (4U)
+#define AFIO_EVCR_PORT_PD_Msk (0x3U << AFIO_EVCR_PORT_PD_Pos) /*!< 0x00000030 */
+#define AFIO_EVCR_PORT_PD AFIO_EVCR_PORT_PD_Msk /*!< Port D selected */
+#define AFIO_EVCR_PORT_PE_Pos (6U)
+#define AFIO_EVCR_PORT_PE_Msk (0x1U << AFIO_EVCR_PORT_PE_Pos) /*!< 0x00000040 */
+#define AFIO_EVCR_PORT_PE AFIO_EVCR_PORT_PE_Msk /*!< Port E selected */
+
+#define AFIO_EVCR_EVOE_Pos (7U)
+#define AFIO_EVCR_EVOE_Msk (0x1U << AFIO_EVCR_EVOE_Pos) /*!< 0x00000080 */
+#define AFIO_EVCR_EVOE AFIO_EVCR_EVOE_Msk /*!< Event Output Enable */
+
+/****************** Bit definition for AFIO_MAPR register *******************/
+#define AFIO_MAPR_SPI1_REMAP_Pos (0U)
+#define AFIO_MAPR_SPI1_REMAP_Msk (0x1U << AFIO_MAPR_SPI1_REMAP_Pos) /*!< 0x00000001 */
+#define AFIO_MAPR_SPI1_REMAP AFIO_MAPR_SPI1_REMAP_Msk /*!< SPI1 remapping */
+#define AFIO_MAPR_I2C1_REMAP_Pos (1U)
+#define AFIO_MAPR_I2C1_REMAP_Msk (0x1U << AFIO_MAPR_I2C1_REMAP_Pos) /*!< 0x00000002 */
+#define AFIO_MAPR_I2C1_REMAP AFIO_MAPR_I2C1_REMAP_Msk /*!< I2C1 remapping */
+#define AFIO_MAPR_USART1_REMAP_Pos (2U)
+#define AFIO_MAPR_USART1_REMAP_Msk (0x1U << AFIO_MAPR_USART1_REMAP_Pos) /*!< 0x00000004 */
+#define AFIO_MAPR_USART1_REMAP AFIO_MAPR_USART1_REMAP_Msk /*!< USART1 remapping */
+#define AFIO_MAPR_USART2_REMAP_Pos (3U)
+#define AFIO_MAPR_USART2_REMAP_Msk (0x1U << AFIO_MAPR_USART2_REMAP_Pos) /*!< 0x00000008 */
+#define AFIO_MAPR_USART2_REMAP AFIO_MAPR_USART2_REMAP_Msk /*!< USART2 remapping */
+
+#define AFIO_MAPR_USART3_REMAP_Pos (4U)
+#define AFIO_MAPR_USART3_REMAP_Msk (0x3U << AFIO_MAPR_USART3_REMAP_Pos) /*!< 0x00000030 */
+#define AFIO_MAPR_USART3_REMAP AFIO_MAPR_USART3_REMAP_Msk /*!< USART3_REMAP[1:0] bits (USART3 remapping) */
+#define AFIO_MAPR_USART3_REMAP_0 (0x1U << AFIO_MAPR_USART3_REMAP_Pos) /*!< 0x00000010 */
+#define AFIO_MAPR_USART3_REMAP_1 (0x2U << AFIO_MAPR_USART3_REMAP_Pos) /*!< 0x00000020 */
+
+/* USART3_REMAP configuration */
+#define AFIO_MAPR_USART3_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14) */
+#define AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Pos (4U)
+#define AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Msk (0x1U << AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Pos) /*!< 0x00000010 */
+#define AFIO_MAPR_USART3_REMAP_PARTIALREMAP AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Msk /*!< Partial remap (TX/PC10, RX/PC11, CK/PC12, CTS/PB13, RTS/PB14) */
+#define AFIO_MAPR_USART3_REMAP_FULLREMAP_Pos (4U)
+#define AFIO_MAPR_USART3_REMAP_FULLREMAP_Msk (0x3U << AFIO_MAPR_USART3_REMAP_FULLREMAP_Pos) /*!< 0x00000030 */
+#define AFIO_MAPR_USART3_REMAP_FULLREMAP AFIO_MAPR_USART3_REMAP_FULLREMAP_Msk /*!< Full remap (TX/PD8, RX/PD9, CK/PD10, CTS/PD11, RTS/PD12) */
+
+#define AFIO_MAPR_TIM1_REMAP_Pos (6U)
+#define AFIO_MAPR_TIM1_REMAP_Msk (0x3U << AFIO_MAPR_TIM1_REMAP_Pos) /*!< 0x000000C0 */
+#define AFIO_MAPR_TIM1_REMAP AFIO_MAPR_TIM1_REMAP_Msk /*!< TIM1_REMAP[1:0] bits (TIM1 remapping) */
+#define AFIO_MAPR_TIM1_REMAP_0 (0x1U << AFIO_MAPR_TIM1_REMAP_Pos) /*!< 0x00000040 */
+#define AFIO_MAPR_TIM1_REMAP_1 (0x2U << AFIO_MAPR_TIM1_REMAP_Pos) /*!< 0x00000080 */
+
+/*!< TIM1_REMAP configuration */
+#define AFIO_MAPR_TIM1_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15) */
+#define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Pos (6U)
+#define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Msk (0x1U << AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Pos) /*!< 0x00000040 */
+#define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Msk /*!< Partial remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PA6, CH1N/PA7, CH2N/PB0, CH3N/PB1) */
+#define AFIO_MAPR_TIM1_REMAP_FULLREMAP_Pos (6U)
+#define AFIO_MAPR_TIM1_REMAP_FULLREMAP_Msk (0x3U << AFIO_MAPR_TIM1_REMAP_FULLREMAP_Pos) /*!< 0x000000C0 */
+#define AFIO_MAPR_TIM1_REMAP_FULLREMAP AFIO_MAPR_TIM1_REMAP_FULLREMAP_Msk /*!< Full remap (ETR/PE7, CH1/PE9, CH2/PE11, CH3/PE13, CH4/PE14, BKIN/PE15, CH1N/PE8, CH2N/PE10, CH3N/PE12) */
+
+#define AFIO_MAPR_TIM2_REMAP_Pos (8U)
+#define AFIO_MAPR_TIM2_REMAP_Msk (0x3U << AFIO_MAPR_TIM2_REMAP_Pos) /*!< 0x00000300 */
+#define AFIO_MAPR_TIM2_REMAP AFIO_MAPR_TIM2_REMAP_Msk /*!< TIM2_REMAP[1:0] bits (TIM2 remapping) */
+#define AFIO_MAPR_TIM2_REMAP_0 (0x1U << AFIO_MAPR_TIM2_REMAP_Pos) /*!< 0x00000100 */
+#define AFIO_MAPR_TIM2_REMAP_1 (0x2U << AFIO_MAPR_TIM2_REMAP_Pos) /*!< 0x00000200 */
+
+/*!< TIM2_REMAP configuration */
+#define AFIO_MAPR_TIM2_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3) */
+#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Pos (8U)
+#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Msk (0x1U << AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Pos) /*!< 0x00000100 */
+#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1 AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Msk /*!< Partial remap (CH1/ETR/PA15, CH2/PB3, CH3/PA2, CH4/PA3) */
+#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2_Pos (9U)
+#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2_Msk (0x1U << AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2_Pos) /*!< 0x00000200 */
+#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2 AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2_Msk /*!< Partial remap (CH1/ETR/PA0, CH2/PA1, CH3/PB10, CH4/PB11) */
+#define AFIO_MAPR_TIM2_REMAP_FULLREMAP_Pos (8U)
+#define AFIO_MAPR_TIM2_REMAP_FULLREMAP_Msk (0x3U << AFIO_MAPR_TIM2_REMAP_FULLREMAP_Pos) /*!< 0x00000300 */
+#define AFIO_MAPR_TIM2_REMAP_FULLREMAP AFIO_MAPR_TIM2_REMAP_FULLREMAP_Msk /*!< Full remap (CH1/ETR/PA15, CH2/PB3, CH3/PB10, CH4/PB11) */
+
+#define AFIO_MAPR_TIM3_REMAP_Pos (10U)
+#define AFIO_MAPR_TIM3_REMAP_Msk (0x3U << AFIO_MAPR_TIM3_REMAP_Pos) /*!< 0x00000C00 */
+#define AFIO_MAPR_TIM3_REMAP AFIO_MAPR_TIM3_REMAP_Msk /*!< TIM3_REMAP[1:0] bits (TIM3 remapping) */
+#define AFIO_MAPR_TIM3_REMAP_0 (0x1U << AFIO_MAPR_TIM3_REMAP_Pos) /*!< 0x00000400 */
+#define AFIO_MAPR_TIM3_REMAP_1 (0x2U << AFIO_MAPR_TIM3_REMAP_Pos) /*!< 0x00000800 */
+
+/*!< TIM3_REMAP configuration */
+#define AFIO_MAPR_TIM3_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1) */
+#define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Pos (11U)
+#define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Msk (0x1U << AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Pos) /*!< 0x00000800 */
+#define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Msk /*!< Partial remap (CH1/PB4, CH2/PB5, CH3/PB0, CH4/PB1) */
+#define AFIO_MAPR_TIM3_REMAP_FULLREMAP_Pos (10U)
+#define AFIO_MAPR_TIM3_REMAP_FULLREMAP_Msk (0x3U << AFIO_MAPR_TIM3_REMAP_FULLREMAP_Pos) /*!< 0x00000C00 */
+#define AFIO_MAPR_TIM3_REMAP_FULLREMAP AFIO_MAPR_TIM3_REMAP_FULLREMAP_Msk /*!< Full remap (CH1/PC6, CH2/PC7, CH3/PC8, CH4/PC9) */
+
+#define AFIO_MAPR_TIM4_REMAP_Pos (12U)
+#define AFIO_MAPR_TIM4_REMAP_Msk (0x1U << AFIO_MAPR_TIM4_REMAP_Pos) /*!< 0x00001000 */
+#define AFIO_MAPR_TIM4_REMAP AFIO_MAPR_TIM4_REMAP_Msk /*!< TIM4_REMAP bit (TIM4 remapping) */
+
+#define AFIO_MAPR_CAN_REMAP_Pos (13U)
+#define AFIO_MAPR_CAN_REMAP_Msk (0x3U << AFIO_MAPR_CAN_REMAP_Pos) /*!< 0x00006000 */
+#define AFIO_MAPR_CAN_REMAP AFIO_MAPR_CAN_REMAP_Msk /*!< CAN_REMAP[1:0] bits (CAN Alternate function remapping) */
+#define AFIO_MAPR_CAN_REMAP_0 (0x1U << AFIO_MAPR_CAN_REMAP_Pos) /*!< 0x00002000 */
+#define AFIO_MAPR_CAN_REMAP_1 (0x2U << AFIO_MAPR_CAN_REMAP_Pos) /*!< 0x00004000 */
+
+/*!< CAN_REMAP configuration */
+#define AFIO_MAPR_CAN_REMAP_REMAP1 ((uint32_t)0x00000000) /*!< CANRX mapped to PA11, CANTX mapped to PA12 */
+#define AFIO_MAPR_CAN_REMAP_REMAP2_Pos (14U)
+#define AFIO_MAPR_CAN_REMAP_REMAP2_Msk (0x1U << AFIO_MAPR_CAN_REMAP_REMAP2_Pos) /*!< 0x00004000 */
+#define AFIO_MAPR_CAN_REMAP_REMAP2 AFIO_MAPR_CAN_REMAP_REMAP2_Msk /*!< CANRX mapped to PB8, CANTX mapped to PB9 */
+#define AFIO_MAPR_CAN_REMAP_REMAP3_Pos (13U)
+#define AFIO_MAPR_CAN_REMAP_REMAP3_Msk (0x3U << AFIO_MAPR_CAN_REMAP_REMAP3_Pos) /*!< 0x00006000 */
+#define AFIO_MAPR_CAN_REMAP_REMAP3 AFIO_MAPR_CAN_REMAP_REMAP3_Msk /*!< CANRX mapped to PD0, CANTX mapped to PD1 */
+
+#define AFIO_MAPR_PD01_REMAP_Pos (15U)
+#define AFIO_MAPR_PD01_REMAP_Msk (0x1U << AFIO_MAPR_PD01_REMAP_Pos) /*!< 0x00008000 */
+#define AFIO_MAPR_PD01_REMAP AFIO_MAPR_PD01_REMAP_Msk /*!< Port D0/Port D1 mapping on OSC_IN/OSC_OUT */
+#define AFIO_MAPR_TIM5CH4_IREMAP_Pos (16U)
+#define AFIO_MAPR_TIM5CH4_IREMAP_Msk (0x1U << AFIO_MAPR_TIM5CH4_IREMAP_Pos) /*!< 0x00010000 */
+#define AFIO_MAPR_TIM5CH4_IREMAP AFIO_MAPR_TIM5CH4_IREMAP_Msk /*!< TIM5 Channel4 Internal Remap */
+#define AFIO_MAPR_ADC1_ETRGINJ_REMAP_Pos (17U)
+#define AFIO_MAPR_ADC1_ETRGINJ_REMAP_Msk (0x1U << AFIO_MAPR_ADC1_ETRGINJ_REMAP_Pos) /*!< 0x00020000 */
+#define AFIO_MAPR_ADC1_ETRGINJ_REMAP AFIO_MAPR_ADC1_ETRGINJ_REMAP_Msk /*!< ADC 1 External Trigger Injected Conversion remapping */
+#define AFIO_MAPR_ADC1_ETRGREG_REMAP_Pos (18U)
+#define AFIO_MAPR_ADC1_ETRGREG_REMAP_Msk (0x1U << AFIO_MAPR_ADC1_ETRGREG_REMAP_Pos) /*!< 0x00040000 */
+#define AFIO_MAPR_ADC1_ETRGREG_REMAP AFIO_MAPR_ADC1_ETRGREG_REMAP_Msk /*!< ADC 1 External Trigger Regular Conversion remapping */
+#define AFIO_MAPR_ADC2_ETRGINJ_REMAP_Pos (19U)
+#define AFIO_MAPR_ADC2_ETRGINJ_REMAP_Msk (0x1U << AFIO_MAPR_ADC2_ETRGINJ_REMAP_Pos) /*!< 0x00080000 */
+#define AFIO_MAPR_ADC2_ETRGINJ_REMAP AFIO_MAPR_ADC2_ETRGINJ_REMAP_Msk /*!< ADC 2 External Trigger Injected Conversion remapping */
+#define AFIO_MAPR_ADC2_ETRGREG_REMAP_Pos (20U)
+#define AFIO_MAPR_ADC2_ETRGREG_REMAP_Msk (0x1U << AFIO_MAPR_ADC2_ETRGREG_REMAP_Pos) /*!< 0x00100000 */
+#define AFIO_MAPR_ADC2_ETRGREG_REMAP AFIO_MAPR_ADC2_ETRGREG_REMAP_Msk /*!< ADC 2 External Trigger Regular Conversion remapping */
+
+/*!< SWJ_CFG configuration */
+#define AFIO_MAPR_SWJ_CFG_Pos (24U)
+#define AFIO_MAPR_SWJ_CFG_Msk (0x7U << AFIO_MAPR_SWJ_CFG_Pos) /*!< 0x07000000 */
+#define AFIO_MAPR_SWJ_CFG AFIO_MAPR_SWJ_CFG_Msk /*!< SWJ_CFG[2:0] bits (Serial Wire JTAG configuration) */
+#define AFIO_MAPR_SWJ_CFG_0 (0x1U << AFIO_MAPR_SWJ_CFG_Pos) /*!< 0x01000000 */
+#define AFIO_MAPR_SWJ_CFG_1 (0x2U << AFIO_MAPR_SWJ_CFG_Pos) /*!< 0x02000000 */
+#define AFIO_MAPR_SWJ_CFG_2 (0x4U << AFIO_MAPR_SWJ_CFG_Pos) /*!< 0x04000000 */
+
+#define AFIO_MAPR_SWJ_CFG_RESET ((uint32_t)0x00000000) /*!< Full SWJ (JTAG-DP + SW-DP) : Reset State */
+#define AFIO_MAPR_SWJ_CFG_NOJNTRST_Pos (24U)
+#define AFIO_MAPR_SWJ_CFG_NOJNTRST_Msk (0x1U << AFIO_MAPR_SWJ_CFG_NOJNTRST_Pos) /*!< 0x01000000 */
+#define AFIO_MAPR_SWJ_CFG_NOJNTRST AFIO_MAPR_SWJ_CFG_NOJNTRST_Msk /*!< Full SWJ (JTAG-DP + SW-DP) but without JNTRST */
+#define AFIO_MAPR_SWJ_CFG_JTAGDISABLE_Pos (25U)
+#define AFIO_MAPR_SWJ_CFG_JTAGDISABLE_Msk (0x1U << AFIO_MAPR_SWJ_CFG_JTAGDISABLE_Pos) /*!< 0x02000000 */
+#define AFIO_MAPR_SWJ_CFG_JTAGDISABLE AFIO_MAPR_SWJ_CFG_JTAGDISABLE_Msk /*!< JTAG-DP Disabled and SW-DP Enabled */
+#define AFIO_MAPR_SWJ_CFG_DISABLE_Pos (26U)
+#define AFIO_MAPR_SWJ_CFG_DISABLE_Msk (0x1U << AFIO_MAPR_SWJ_CFG_DISABLE_Pos) /*!< 0x04000000 */
+#define AFIO_MAPR_SWJ_CFG_DISABLE AFIO_MAPR_SWJ_CFG_DISABLE_Msk /*!< JTAG-DP Disabled and SW-DP Disabled */
+
+
+/***************** Bit definition for AFIO_EXTICR1 register *****************/
+#define AFIO_EXTICR1_EXTI0_Pos (0U)
+#define AFIO_EXTICR1_EXTI0_Msk (0xFU << AFIO_EXTICR1_EXTI0_Pos) /*!< 0x0000000F */
+#define AFIO_EXTICR1_EXTI0 AFIO_EXTICR1_EXTI0_Msk /*!< EXTI 0 configuration */
+#define AFIO_EXTICR1_EXTI1_Pos (4U)
+#define AFIO_EXTICR1_EXTI1_Msk (0xFU << AFIO_EXTICR1_EXTI1_Pos) /*!< 0x000000F0 */
+#define AFIO_EXTICR1_EXTI1 AFIO_EXTICR1_EXTI1_Msk /*!< EXTI 1 configuration */
+#define AFIO_EXTICR1_EXTI2_Pos (8U)
+#define AFIO_EXTICR1_EXTI2_Msk (0xFU << AFIO_EXTICR1_EXTI2_Pos) /*!< 0x00000F00 */
+#define AFIO_EXTICR1_EXTI2 AFIO_EXTICR1_EXTI2_Msk /*!< EXTI 2 configuration */
+#define AFIO_EXTICR1_EXTI3_Pos (12U)
+#define AFIO_EXTICR1_EXTI3_Msk (0xFU << AFIO_EXTICR1_EXTI3_Pos) /*!< 0x0000F000 */
+#define AFIO_EXTICR1_EXTI3 AFIO_EXTICR1_EXTI3_Msk /*!< EXTI 3 configuration */
+
+/*!< EXTI0 configuration */
+#define AFIO_EXTICR1_EXTI0_PA ((uint32_t)0x00000000) /*!< PA[0] pin */
+#define AFIO_EXTICR1_EXTI0_PB_Pos (0U)
+#define AFIO_EXTICR1_EXTI0_PB_Msk (0x1U << AFIO_EXTICR1_EXTI0_PB_Pos) /*!< 0x00000001 */
+#define AFIO_EXTICR1_EXTI0_PB AFIO_EXTICR1_EXTI0_PB_Msk /*!< PB[0] pin */
+#define AFIO_EXTICR1_EXTI0_PC_Pos (1U)
+#define AFIO_EXTICR1_EXTI0_PC_Msk (0x1U << AFIO_EXTICR1_EXTI0_PC_Pos) /*!< 0x00000002 */
+#define AFIO_EXTICR1_EXTI0_PC AFIO_EXTICR1_EXTI0_PC_Msk /*!< PC[0] pin */
+#define AFIO_EXTICR1_EXTI0_PD_Pos (0U)
+#define AFIO_EXTICR1_EXTI0_PD_Msk (0x3U << AFIO_EXTICR1_EXTI0_PD_Pos) /*!< 0x00000003 */
+#define AFIO_EXTICR1_EXTI0_PD AFIO_EXTICR1_EXTI0_PD_Msk /*!< PD[0] pin */
+#define AFIO_EXTICR1_EXTI0_PE_Pos (2U)
+#define AFIO_EXTICR1_EXTI0_PE_Msk (0x1U << AFIO_EXTICR1_EXTI0_PE_Pos) /*!< 0x00000004 */
+#define AFIO_EXTICR1_EXTI0_PE AFIO_EXTICR1_EXTI0_PE_Msk /*!< PE[0] pin */
+#define AFIO_EXTICR1_EXTI0_PF_Pos (0U)
+#define AFIO_EXTICR1_EXTI0_PF_Msk (0x5U << AFIO_EXTICR1_EXTI0_PF_Pos) /*!< 0x00000005 */
+#define AFIO_EXTICR1_EXTI0_PF AFIO_EXTICR1_EXTI0_PF_Msk /*!< PF[0] pin */
+#define AFIO_EXTICR1_EXTI0_PG_Pos (1U)
+#define AFIO_EXTICR1_EXTI0_PG_Msk (0x3U << AFIO_EXTICR1_EXTI0_PG_Pos) /*!< 0x00000006 */
+#define AFIO_EXTICR1_EXTI0_PG AFIO_EXTICR1_EXTI0_PG_Msk /*!< PG[0] pin */
+
+/*!< EXTI1 configuration */
+#define AFIO_EXTICR1_EXTI1_PA ((uint32_t)0x00000000) /*!< PA[1] pin */
+#define AFIO_EXTICR1_EXTI1_PB_Pos (4U)
+#define AFIO_EXTICR1_EXTI1_PB_Msk (0x1U << AFIO_EXTICR1_EXTI1_PB_Pos) /*!< 0x00000010 */
+#define AFIO_EXTICR1_EXTI1_PB AFIO_EXTICR1_EXTI1_PB_Msk /*!< PB[1] pin */
+#define AFIO_EXTICR1_EXTI1_PC_Pos (5U)
+#define AFIO_EXTICR1_EXTI1_PC_Msk (0x1U << AFIO_EXTICR1_EXTI1_PC_Pos) /*!< 0x00000020 */
+#define AFIO_EXTICR1_EXTI1_PC AFIO_EXTICR1_EXTI1_PC_Msk /*!< PC[1] pin */
+#define AFIO_EXTICR1_EXTI1_PD_Pos (4U)
+#define AFIO_EXTICR1_EXTI1_PD_Msk (0x3U << AFIO_EXTICR1_EXTI1_PD_Pos) /*!< 0x00000030 */
+#define AFIO_EXTICR1_EXTI1_PD AFIO_EXTICR1_EXTI1_PD_Msk /*!< PD[1] pin */
+#define AFIO_EXTICR1_EXTI1_PE_Pos (6U)
+#define AFIO_EXTICR1_EXTI1_PE_Msk (0x1U << AFIO_EXTICR1_EXTI1_PE_Pos) /*!< 0x00000040 */
+#define AFIO_EXTICR1_EXTI1_PE AFIO_EXTICR1_EXTI1_PE_Msk /*!< PE[1] pin */
+#define AFIO_EXTICR1_EXTI1_PF_Pos (4U)
+#define AFIO_EXTICR1_EXTI1_PF_Msk (0x5U << AFIO_EXTICR1_EXTI1_PF_Pos) /*!< 0x00000050 */
+#define AFIO_EXTICR1_EXTI1_PF AFIO_EXTICR1_EXTI1_PF_Msk /*!< PF[1] pin */
+#define AFIO_EXTICR1_EXTI1_PG_Pos (5U)
+#define AFIO_EXTICR1_EXTI1_PG_Msk (0x3U << AFIO_EXTICR1_EXTI1_PG_Pos) /*!< 0x00000060 */
+#define AFIO_EXTICR1_EXTI1_PG AFIO_EXTICR1_EXTI1_PG_Msk /*!< PG[1] pin */
+
+/*!< EXTI2 configuration */
+#define AFIO_EXTICR1_EXTI2_PA ((uint32_t)0x00000000) /*!< PA[2] pin */
+#define AFIO_EXTICR1_EXTI2_PB_Pos (8U)
+#define AFIO_EXTICR1_EXTI2_PB_Msk (0x1U << AFIO_EXTICR1_EXTI2_PB_Pos) /*!< 0x00000100 */
+#define AFIO_EXTICR1_EXTI2_PB AFIO_EXTICR1_EXTI2_PB_Msk /*!< PB[2] pin */
+#define AFIO_EXTICR1_EXTI2_PC_Pos (9U)
+#define AFIO_EXTICR1_EXTI2_PC_Msk (0x1U << AFIO_EXTICR1_EXTI2_PC_Pos) /*!< 0x00000200 */
+#define AFIO_EXTICR1_EXTI2_PC AFIO_EXTICR1_EXTI2_PC_Msk /*!< PC[2] pin */
+#define AFIO_EXTICR1_EXTI2_PD_Pos (8U)
+#define AFIO_EXTICR1_EXTI2_PD_Msk (0x3U << AFIO_EXTICR1_EXTI2_PD_Pos) /*!< 0x00000300 */
+#define AFIO_EXTICR1_EXTI2_PD AFIO_EXTICR1_EXTI2_PD_Msk /*!< PD[2] pin */
+#define AFIO_EXTICR1_EXTI2_PE_Pos (10U)
+#define AFIO_EXTICR1_EXTI2_PE_Msk (0x1U << AFIO_EXTICR1_EXTI2_PE_Pos) /*!< 0x00000400 */
+#define AFIO_EXTICR1_EXTI2_PE AFIO_EXTICR1_EXTI2_PE_Msk /*!< PE[2] pin */
+#define AFIO_EXTICR1_EXTI2_PF_Pos (8U)
+#define AFIO_EXTICR1_EXTI2_PF_Msk (0x5U << AFIO_EXTICR1_EXTI2_PF_Pos) /*!< 0x00000500 */
+#define AFIO_EXTICR1_EXTI2_PF AFIO_EXTICR1_EXTI2_PF_Msk /*!< PF[2] pin */
+#define AFIO_EXTICR1_EXTI2_PG_Pos (9U)
+#define AFIO_EXTICR1_EXTI2_PG_Msk (0x3U << AFIO_EXTICR1_EXTI2_PG_Pos) /*!< 0x00000600 */
+#define AFIO_EXTICR1_EXTI2_PG AFIO_EXTICR1_EXTI2_PG_Msk /*!< PG[2] pin */
+
+/*!< EXTI3 configuration */
+#define AFIO_EXTICR1_EXTI3_PA ((uint32_t)0x00000000) /*!< PA[3] pin */
+#define AFIO_EXTICR1_EXTI3_PB_Pos (12U)
+#define AFIO_EXTICR1_EXTI3_PB_Msk (0x1U << AFIO_EXTICR1_EXTI3_PB_Pos) /*!< 0x00001000 */
+#define AFIO_EXTICR1_EXTI3_PB AFIO_EXTICR1_EXTI3_PB_Msk /*!< PB[3] pin */
+#define AFIO_EXTICR1_EXTI3_PC_Pos (13U)
+#define AFIO_EXTICR1_EXTI3_PC_Msk (0x1U << AFIO_EXTICR1_EXTI3_PC_Pos) /*!< 0x00002000 */
+#define AFIO_EXTICR1_EXTI3_PC AFIO_EXTICR1_EXTI3_PC_Msk /*!< PC[3] pin */
+#define AFIO_EXTICR1_EXTI3_PD_Pos (12U)
+#define AFIO_EXTICR1_EXTI3_PD_Msk (0x3U << AFIO_EXTICR1_EXTI3_PD_Pos) /*!< 0x00003000 */
+#define AFIO_EXTICR1_EXTI3_PD AFIO_EXTICR1_EXTI3_PD_Msk /*!< PD[3] pin */
+#define AFIO_EXTICR1_EXTI3_PE_Pos (14U)
+#define AFIO_EXTICR1_EXTI3_PE_Msk (0x1U << AFIO_EXTICR1_EXTI3_PE_Pos) /*!< 0x00004000 */
+#define AFIO_EXTICR1_EXTI3_PE AFIO_EXTICR1_EXTI3_PE_Msk /*!< PE[3] pin */
+#define AFIO_EXTICR1_EXTI3_PF_Pos (12U)
+#define AFIO_EXTICR1_EXTI3_PF_Msk (0x5U << AFIO_EXTICR1_EXTI3_PF_Pos) /*!< 0x00005000 */
+#define AFIO_EXTICR1_EXTI3_PF AFIO_EXTICR1_EXTI3_PF_Msk /*!< PF[3] pin */
+#define AFIO_EXTICR1_EXTI3_PG_Pos (13U)
+#define AFIO_EXTICR1_EXTI3_PG_Msk (0x3U << AFIO_EXTICR1_EXTI3_PG_Pos) /*!< 0x00006000 */
+#define AFIO_EXTICR1_EXTI3_PG AFIO_EXTICR1_EXTI3_PG_Msk /*!< PG[3] pin */
+
+/***************** Bit definition for AFIO_EXTICR2 register *****************/
+#define AFIO_EXTICR2_EXTI4_Pos (0U)
+#define AFIO_EXTICR2_EXTI4_Msk (0xFU << AFIO_EXTICR2_EXTI4_Pos) /*!< 0x0000000F */
+#define AFIO_EXTICR2_EXTI4 AFIO_EXTICR2_EXTI4_Msk /*!< EXTI 4 configuration */
+#define AFIO_EXTICR2_EXTI5_Pos (4U)
+#define AFIO_EXTICR2_EXTI5_Msk (0xFU << AFIO_EXTICR2_EXTI5_Pos) /*!< 0x000000F0 */
+#define AFIO_EXTICR2_EXTI5 AFIO_EXTICR2_EXTI5_Msk /*!< EXTI 5 configuration */
+#define AFIO_EXTICR2_EXTI6_Pos (8U)
+#define AFIO_EXTICR2_EXTI6_Msk (0xFU << AFIO_EXTICR2_EXTI6_Pos) /*!< 0x00000F00 */
+#define AFIO_EXTICR2_EXTI6 AFIO_EXTICR2_EXTI6_Msk /*!< EXTI 6 configuration */
+#define AFIO_EXTICR2_EXTI7_Pos (12U)
+#define AFIO_EXTICR2_EXTI7_Msk (0xFU << AFIO_EXTICR2_EXTI7_Pos) /*!< 0x0000F000 */
+#define AFIO_EXTICR2_EXTI7 AFIO_EXTICR2_EXTI7_Msk /*!< EXTI 7 configuration */
+
+/*!< EXTI4 configuration */
+#define AFIO_EXTICR2_EXTI4_PA ((uint32_t)0x00000000) /*!< PA[4] pin */
+#define AFIO_EXTICR2_EXTI4_PB_Pos (0U)
+#define AFIO_EXTICR2_EXTI4_PB_Msk (0x1U << AFIO_EXTICR2_EXTI4_PB_Pos) /*!< 0x00000001 */
+#define AFIO_EXTICR2_EXTI4_PB AFIO_EXTICR2_EXTI4_PB_Msk /*!< PB[4] pin */
+#define AFIO_EXTICR2_EXTI4_PC_Pos (1U)
+#define AFIO_EXTICR2_EXTI4_PC_Msk (0x1U << AFIO_EXTICR2_EXTI4_PC_Pos) /*!< 0x00000002 */
+#define AFIO_EXTICR2_EXTI4_PC AFIO_EXTICR2_EXTI4_PC_Msk /*!< PC[4] pin */
+#define AFIO_EXTICR2_EXTI4_PD_Pos (0U)
+#define AFIO_EXTICR2_EXTI4_PD_Msk (0x3U << AFIO_EXTICR2_EXTI4_PD_Pos) /*!< 0x00000003 */
+#define AFIO_EXTICR2_EXTI4_PD AFIO_EXTICR2_EXTI4_PD_Msk /*!< PD[4] pin */
+#define AFIO_EXTICR2_EXTI4_PE_Pos (2U)
+#define AFIO_EXTICR2_EXTI4_PE_Msk (0x1U << AFIO_EXTICR2_EXTI4_PE_Pos) /*!< 0x00000004 */
+#define AFIO_EXTICR2_EXTI4_PE AFIO_EXTICR2_EXTI4_PE_Msk /*!< PE[4] pin */
+#define AFIO_EXTICR2_EXTI4_PF_Pos (0U)
+#define AFIO_EXTICR2_EXTI4_PF_Msk (0x5U << AFIO_EXTICR2_EXTI4_PF_Pos) /*!< 0x00000005 */
+#define AFIO_EXTICR2_EXTI4_PF AFIO_EXTICR2_EXTI4_PF_Msk /*!< PF[4] pin */
+#define AFIO_EXTICR2_EXTI4_PG_Pos (1U)
+#define AFIO_EXTICR2_EXTI4_PG_Msk (0x3U << AFIO_EXTICR2_EXTI4_PG_Pos) /*!< 0x00000006 */
+#define AFIO_EXTICR2_EXTI4_PG AFIO_EXTICR2_EXTI4_PG_Msk /*!< PG[4] pin */
+
+/* EXTI5 configuration */
+#define AFIO_EXTICR2_EXTI5_PA ((uint32_t)0x00000000) /*!< PA[5] pin */
+#define AFIO_EXTICR2_EXTI5_PB_Pos (4U)
+#define AFIO_EXTICR2_EXTI5_PB_Msk (0x1U << AFIO_EXTICR2_EXTI5_PB_Pos) /*!< 0x00000010 */
+#define AFIO_EXTICR2_EXTI5_PB AFIO_EXTICR2_EXTI5_PB_Msk /*!< PB[5] pin */
+#define AFIO_EXTICR2_EXTI5_PC_Pos (5U)
+#define AFIO_EXTICR2_EXTI5_PC_Msk (0x1U << AFIO_EXTICR2_EXTI5_PC_Pos) /*!< 0x00000020 */
+#define AFIO_EXTICR2_EXTI5_PC AFIO_EXTICR2_EXTI5_PC_Msk /*!< PC[5] pin */
+#define AFIO_EXTICR2_EXTI5_PD_Pos (4U)
+#define AFIO_EXTICR2_EXTI5_PD_Msk (0x3U << AFIO_EXTICR2_EXTI5_PD_Pos) /*!< 0x00000030 */
+#define AFIO_EXTICR2_EXTI5_PD AFIO_EXTICR2_EXTI5_PD_Msk /*!< PD[5] pin */
+#define AFIO_EXTICR2_EXTI5_PE_Pos (6U)
+#define AFIO_EXTICR2_EXTI5_PE_Msk (0x1U << AFIO_EXTICR2_EXTI5_PE_Pos) /*!< 0x00000040 */
+#define AFIO_EXTICR2_EXTI5_PE AFIO_EXTICR2_EXTI5_PE_Msk /*!< PE[5] pin */
+#define AFIO_EXTICR2_EXTI5_PF_Pos (4U)
+#define AFIO_EXTICR2_EXTI5_PF_Msk (0x5U << AFIO_EXTICR2_EXTI5_PF_Pos) /*!< 0x00000050 */
+#define AFIO_EXTICR2_EXTI5_PF AFIO_EXTICR2_EXTI5_PF_Msk /*!< PF[5] pin */
+#define AFIO_EXTICR2_EXTI5_PG_Pos (5U)
+#define AFIO_EXTICR2_EXTI5_PG_Msk (0x3U << AFIO_EXTICR2_EXTI5_PG_Pos) /*!< 0x00000060 */
+#define AFIO_EXTICR2_EXTI5_PG AFIO_EXTICR2_EXTI5_PG_Msk /*!< PG[5] pin */
+
+/*!< EXTI6 configuration */
+#define AFIO_EXTICR2_EXTI6_PA ((uint32_t)0x00000000) /*!< PA[6] pin */
+#define AFIO_EXTICR2_EXTI6_PB_Pos (8U)
+#define AFIO_EXTICR2_EXTI6_PB_Msk (0x1U << AFIO_EXTICR2_EXTI6_PB_Pos) /*!< 0x00000100 */
+#define AFIO_EXTICR2_EXTI6_PB AFIO_EXTICR2_EXTI6_PB_Msk /*!< PB[6] pin */
+#define AFIO_EXTICR2_EXTI6_PC_Pos (9U)
+#define AFIO_EXTICR2_EXTI6_PC_Msk (0x1U << AFIO_EXTICR2_EXTI6_PC_Pos) /*!< 0x00000200 */
+#define AFIO_EXTICR2_EXTI6_PC AFIO_EXTICR2_EXTI6_PC_Msk /*!< PC[6] pin */
+#define AFIO_EXTICR2_EXTI6_PD_Pos (8U)
+#define AFIO_EXTICR2_EXTI6_PD_Msk (0x3U << AFIO_EXTICR2_EXTI6_PD_Pos) /*!< 0x00000300 */
+#define AFIO_EXTICR2_EXTI6_PD AFIO_EXTICR2_EXTI6_PD_Msk /*!< PD[6] pin */
+#define AFIO_EXTICR2_EXTI6_PE_Pos (10U)
+#define AFIO_EXTICR2_EXTI6_PE_Msk (0x1U << AFIO_EXTICR2_EXTI6_PE_Pos) /*!< 0x00000400 */
+#define AFIO_EXTICR2_EXTI6_PE AFIO_EXTICR2_EXTI6_PE_Msk /*!< PE[6] pin */
+#define AFIO_EXTICR2_EXTI6_PF_Pos (8U)
+#define AFIO_EXTICR2_EXTI6_PF_Msk (0x5U << AFIO_EXTICR2_EXTI6_PF_Pos) /*!< 0x00000500 */
+#define AFIO_EXTICR2_EXTI6_PF AFIO_EXTICR2_EXTI6_PF_Msk /*!< PF[6] pin */
+#define AFIO_EXTICR2_EXTI6_PG_Pos (9U)
+#define AFIO_EXTICR2_EXTI6_PG_Msk (0x3U << AFIO_EXTICR2_EXTI6_PG_Pos) /*!< 0x00000600 */
+#define AFIO_EXTICR2_EXTI6_PG AFIO_EXTICR2_EXTI6_PG_Msk /*!< PG[6] pin */
+
+/*!< EXTI7 configuration */
+#define AFIO_EXTICR2_EXTI7_PA ((uint32_t)0x00000000) /*!< PA[7] pin */
+#define AFIO_EXTICR2_EXTI7_PB_Pos (12U)
+#define AFIO_EXTICR2_EXTI7_PB_Msk (0x1U << AFIO_EXTICR2_EXTI7_PB_Pos) /*!< 0x00001000 */
+#define AFIO_EXTICR2_EXTI7_PB AFIO_EXTICR2_EXTI7_PB_Msk /*!< PB[7] pin */
+#define AFIO_EXTICR2_EXTI7_PC_Pos (13U)
+#define AFIO_EXTICR2_EXTI7_PC_Msk (0x1U << AFIO_EXTICR2_EXTI7_PC_Pos) /*!< 0x00002000 */
+#define AFIO_EXTICR2_EXTI7_PC AFIO_EXTICR2_EXTI7_PC_Msk /*!< PC[7] pin */
+#define AFIO_EXTICR2_EXTI7_PD_Pos (12U)
+#define AFIO_EXTICR2_EXTI7_PD_Msk (0x3U << AFIO_EXTICR2_EXTI7_PD_Pos) /*!< 0x00003000 */
+#define AFIO_EXTICR2_EXTI7_PD AFIO_EXTICR2_EXTI7_PD_Msk /*!< PD[7] pin */
+#define AFIO_EXTICR2_EXTI7_PE_Pos (14U)
+#define AFIO_EXTICR2_EXTI7_PE_Msk (0x1U << AFIO_EXTICR2_EXTI7_PE_Pos) /*!< 0x00004000 */
+#define AFIO_EXTICR2_EXTI7_PE AFIO_EXTICR2_EXTI7_PE_Msk /*!< PE[7] pin */
+#define AFIO_EXTICR2_EXTI7_PF_Pos (12U)
+#define AFIO_EXTICR2_EXTI7_PF_Msk (0x5U << AFIO_EXTICR2_EXTI7_PF_Pos) /*!< 0x00005000 */
+#define AFIO_EXTICR2_EXTI7_PF AFIO_EXTICR2_EXTI7_PF_Msk /*!< PF[7] pin */
+#define AFIO_EXTICR2_EXTI7_PG_Pos (13U)
+#define AFIO_EXTICR2_EXTI7_PG_Msk (0x3U << AFIO_EXTICR2_EXTI7_PG_Pos) /*!< 0x00006000 */
+#define AFIO_EXTICR2_EXTI7_PG AFIO_EXTICR2_EXTI7_PG_Msk /*!< PG[7] pin */
+
+/***************** Bit definition for AFIO_EXTICR3 register *****************/
+#define AFIO_EXTICR3_EXTI8_Pos (0U)
+#define AFIO_EXTICR3_EXTI8_Msk (0xFU << AFIO_EXTICR3_EXTI8_Pos) /*!< 0x0000000F */
+#define AFIO_EXTICR3_EXTI8 AFIO_EXTICR3_EXTI8_Msk /*!< EXTI 8 configuration */
+#define AFIO_EXTICR3_EXTI9_Pos (4U)
+#define AFIO_EXTICR3_EXTI9_Msk (0xFU << AFIO_EXTICR3_EXTI9_Pos) /*!< 0x000000F0 */
+#define AFIO_EXTICR3_EXTI9 AFIO_EXTICR3_EXTI9_Msk /*!< EXTI 9 configuration */
+#define AFIO_EXTICR3_EXTI10_Pos (8U)
+#define AFIO_EXTICR3_EXTI10_Msk (0xFU << AFIO_EXTICR3_EXTI10_Pos) /*!< 0x00000F00 */
+#define AFIO_EXTICR3_EXTI10 AFIO_EXTICR3_EXTI10_Msk /*!< EXTI 10 configuration */
+#define AFIO_EXTICR3_EXTI11_Pos (12U)
+#define AFIO_EXTICR3_EXTI11_Msk (0xFU << AFIO_EXTICR3_EXTI11_Pos) /*!< 0x0000F000 */
+#define AFIO_EXTICR3_EXTI11 AFIO_EXTICR3_EXTI11_Msk /*!< EXTI 11 configuration */
+
+/*!< EXTI8 configuration */
+#define AFIO_EXTICR3_EXTI8_PA ((uint32_t)0x00000000) /*!< PA[8] pin */
+#define AFIO_EXTICR3_EXTI8_PB_Pos (0U)
+#define AFIO_EXTICR3_EXTI8_PB_Msk (0x1U << AFIO_EXTICR3_EXTI8_PB_Pos) /*!< 0x00000001 */
+#define AFIO_EXTICR3_EXTI8_PB AFIO_EXTICR3_EXTI8_PB_Msk /*!< PB[8] pin */
+#define AFIO_EXTICR3_EXTI8_PC_Pos (1U)
+#define AFIO_EXTICR3_EXTI8_PC_Msk (0x1U << AFIO_EXTICR3_EXTI8_PC_Pos) /*!< 0x00000002 */
+#define AFIO_EXTICR3_EXTI8_PC AFIO_EXTICR3_EXTI8_PC_Msk /*!< PC[8] pin */
+#define AFIO_EXTICR3_EXTI8_PD_Pos (0U)
+#define AFIO_EXTICR3_EXTI8_PD_Msk (0x3U << AFIO_EXTICR3_EXTI8_PD_Pos) /*!< 0x00000003 */
+#define AFIO_EXTICR3_EXTI8_PD AFIO_EXTICR3_EXTI8_PD_Msk /*!< PD[8] pin */
+#define AFIO_EXTICR3_EXTI8_PE_Pos (2U)
+#define AFIO_EXTICR3_EXTI8_PE_Msk (0x1U << AFIO_EXTICR3_EXTI8_PE_Pos) /*!< 0x00000004 */
+#define AFIO_EXTICR3_EXTI8_PE AFIO_EXTICR3_EXTI8_PE_Msk /*!< PE[8] pin */
+#define AFIO_EXTICR3_EXTI8_PF_Pos (0U)
+#define AFIO_EXTICR3_EXTI8_PF_Msk (0x5U << AFIO_EXTICR3_EXTI8_PF_Pos) /*!< 0x00000005 */
+#define AFIO_EXTICR3_EXTI8_PF AFIO_EXTICR3_EXTI8_PF_Msk /*!< PF[8] pin */
+#define AFIO_EXTICR3_EXTI8_PG_Pos (1U)
+#define AFIO_EXTICR3_EXTI8_PG_Msk (0x3U << AFIO_EXTICR3_EXTI8_PG_Pos) /*!< 0x00000006 */
+#define AFIO_EXTICR3_EXTI8_PG AFIO_EXTICR3_EXTI8_PG_Msk /*!< PG[8] pin */
+
+/*!< EXTI9 configuration */
+#define AFIO_EXTICR3_EXTI9_PA ((uint32_t)0x00000000) /*!< PA[9] pin */
+#define AFIO_EXTICR3_EXTI9_PB_Pos (4U)
+#define AFIO_EXTICR3_EXTI9_PB_Msk (0x1U << AFIO_EXTICR3_EXTI9_PB_Pos) /*!< 0x00000010 */
+#define AFIO_EXTICR3_EXTI9_PB AFIO_EXTICR3_EXTI9_PB_Msk /*!< PB[9] pin */
+#define AFIO_EXTICR3_EXTI9_PC_Pos (5U)
+#define AFIO_EXTICR3_EXTI9_PC_Msk (0x1U << AFIO_EXTICR3_EXTI9_PC_Pos) /*!< 0x00000020 */
+#define AFIO_EXTICR3_EXTI9_PC AFIO_EXTICR3_EXTI9_PC_Msk /*!< PC[9] pin */
+#define AFIO_EXTICR3_EXTI9_PD_Pos (4U)
+#define AFIO_EXTICR3_EXTI9_PD_Msk (0x3U << AFIO_EXTICR3_EXTI9_PD_Pos) /*!< 0x00000030 */
+#define AFIO_EXTICR3_EXTI9_PD AFIO_EXTICR3_EXTI9_PD_Msk /*!< PD[9] pin */
+#define AFIO_EXTICR3_EXTI9_PE_Pos (6U)
+#define AFIO_EXTICR3_EXTI9_PE_Msk (0x1U << AFIO_EXTICR3_EXTI9_PE_Pos) /*!< 0x00000040 */
+#define AFIO_EXTICR3_EXTI9_PE AFIO_EXTICR3_EXTI9_PE_Msk /*!< PE[9] pin */
+#define AFIO_EXTICR3_EXTI9_PF_Pos (4U)
+#define AFIO_EXTICR3_EXTI9_PF_Msk (0x5U << AFIO_EXTICR3_EXTI9_PF_Pos) /*!< 0x00000050 */
+#define AFIO_EXTICR3_EXTI9_PF AFIO_EXTICR3_EXTI9_PF_Msk /*!< PF[9] pin */
+#define AFIO_EXTICR3_EXTI9_PG_Pos (5U)
+#define AFIO_EXTICR3_EXTI9_PG_Msk (0x3U << AFIO_EXTICR3_EXTI9_PG_Pos) /*!< 0x00000060 */
+#define AFIO_EXTICR3_EXTI9_PG AFIO_EXTICR3_EXTI9_PG_Msk /*!< PG[9] pin */
+
+/*!< EXTI10 configuration */
+#define AFIO_EXTICR3_EXTI10_PA ((uint32_t)0x00000000) /*!< PA[10] pin */
+#define AFIO_EXTICR3_EXTI10_PB_Pos (8U)
+#define AFIO_EXTICR3_EXTI10_PB_Msk (0x1U << AFIO_EXTICR3_EXTI10_PB_Pos) /*!< 0x00000100 */
+#define AFIO_EXTICR3_EXTI10_PB AFIO_EXTICR3_EXTI10_PB_Msk /*!< PB[10] pin */
+#define AFIO_EXTICR3_EXTI10_PC_Pos (9U)
+#define AFIO_EXTICR3_EXTI10_PC_Msk (0x1U << AFIO_EXTICR3_EXTI10_PC_Pos) /*!< 0x00000200 */
+#define AFIO_EXTICR3_EXTI10_PC AFIO_EXTICR3_EXTI10_PC_Msk /*!< PC[10] pin */
+#define AFIO_EXTICR3_EXTI10_PD_Pos (8U)
+#define AFIO_EXTICR3_EXTI10_PD_Msk (0x3U << AFIO_EXTICR3_EXTI10_PD_Pos) /*!< 0x00000300 */
+#define AFIO_EXTICR3_EXTI10_PD AFIO_EXTICR3_EXTI10_PD_Msk /*!< PD[10] pin */
+#define AFIO_EXTICR3_EXTI10_PE_Pos (10U)
+#define AFIO_EXTICR3_EXTI10_PE_Msk (0x1U << AFIO_EXTICR3_EXTI10_PE_Pos) /*!< 0x00000400 */
+#define AFIO_EXTICR3_EXTI10_PE AFIO_EXTICR3_EXTI10_PE_Msk /*!< PE[10] pin */
+#define AFIO_EXTICR3_EXTI10_PF_Pos (8U)
+#define AFIO_EXTICR3_EXTI10_PF_Msk (0x5U << AFIO_EXTICR3_EXTI10_PF_Pos) /*!< 0x00000500 */
+#define AFIO_EXTICR3_EXTI10_PF AFIO_EXTICR3_EXTI10_PF_Msk /*!< PF[10] pin */
+#define AFIO_EXTICR3_EXTI10_PG_Pos (9U)
+#define AFIO_EXTICR3_EXTI10_PG_Msk (0x3U << AFIO_EXTICR3_EXTI10_PG_Pos) /*!< 0x00000600 */
+#define AFIO_EXTICR3_EXTI10_PG AFIO_EXTICR3_EXTI10_PG_Msk /*!< PG[10] pin */
+
+/*!< EXTI11 configuration */
+#define AFIO_EXTICR3_EXTI11_PA ((uint32_t)0x00000000) /*!< PA[11] pin */
+#define AFIO_EXTICR3_EXTI11_PB_Pos (12U)
+#define AFIO_EXTICR3_EXTI11_PB_Msk (0x1U << AFIO_EXTICR3_EXTI11_PB_Pos) /*!< 0x00001000 */
+#define AFIO_EXTICR3_EXTI11_PB AFIO_EXTICR3_EXTI11_PB_Msk /*!< PB[11] pin */
+#define AFIO_EXTICR3_EXTI11_PC_Pos (13U)
+#define AFIO_EXTICR3_EXTI11_PC_Msk (0x1U << AFIO_EXTICR3_EXTI11_PC_Pos) /*!< 0x00002000 */
+#define AFIO_EXTICR3_EXTI11_PC AFIO_EXTICR3_EXTI11_PC_Msk /*!< PC[11] pin */
+#define AFIO_EXTICR3_EXTI11_PD_Pos (12U)
+#define AFIO_EXTICR3_EXTI11_PD_Msk (0x3U << AFIO_EXTICR3_EXTI11_PD_Pos) /*!< 0x00003000 */
+#define AFIO_EXTICR3_EXTI11_PD AFIO_EXTICR3_EXTI11_PD_Msk /*!< PD[11] pin */
+#define AFIO_EXTICR3_EXTI11_PE_Pos (14U)
+#define AFIO_EXTICR3_EXTI11_PE_Msk (0x1U << AFIO_EXTICR3_EXTI11_PE_Pos) /*!< 0x00004000 */
+#define AFIO_EXTICR3_EXTI11_PE AFIO_EXTICR3_EXTI11_PE_Msk /*!< PE[11] pin */
+#define AFIO_EXTICR3_EXTI11_PF_Pos (12U)
+#define AFIO_EXTICR3_EXTI11_PF_Msk (0x5U << AFIO_EXTICR3_EXTI11_PF_Pos) /*!< 0x00005000 */
+#define AFIO_EXTICR3_EXTI11_PF AFIO_EXTICR3_EXTI11_PF_Msk /*!< PF[11] pin */
+#define AFIO_EXTICR3_EXTI11_PG_Pos (13U)
+#define AFIO_EXTICR3_EXTI11_PG_Msk (0x3U << AFIO_EXTICR3_EXTI11_PG_Pos) /*!< 0x00006000 */
+#define AFIO_EXTICR3_EXTI11_PG AFIO_EXTICR3_EXTI11_PG_Msk /*!< PG[11] pin */
+
+/***************** Bit definition for AFIO_EXTICR4 register *****************/
+#define AFIO_EXTICR4_EXTI12_Pos (0U)
+#define AFIO_EXTICR4_EXTI12_Msk (0xFU << AFIO_EXTICR4_EXTI12_Pos) /*!< 0x0000000F */
+#define AFIO_EXTICR4_EXTI12 AFIO_EXTICR4_EXTI12_Msk /*!< EXTI 12 configuration */
+#define AFIO_EXTICR4_EXTI13_Pos (4U)
+#define AFIO_EXTICR4_EXTI13_Msk (0xFU << AFIO_EXTICR4_EXTI13_Pos) /*!< 0x000000F0 */
+#define AFIO_EXTICR4_EXTI13 AFIO_EXTICR4_EXTI13_Msk /*!< EXTI 13 configuration */
+#define AFIO_EXTICR4_EXTI14_Pos (8U)
+#define AFIO_EXTICR4_EXTI14_Msk (0xFU << AFIO_EXTICR4_EXTI14_Pos) /*!< 0x00000F00 */
+#define AFIO_EXTICR4_EXTI14 AFIO_EXTICR4_EXTI14_Msk /*!< EXTI 14 configuration */
+#define AFIO_EXTICR4_EXTI15_Pos (12U)
+#define AFIO_EXTICR4_EXTI15_Msk (0xFU << AFIO_EXTICR4_EXTI15_Pos) /*!< 0x0000F000 */
+#define AFIO_EXTICR4_EXTI15 AFIO_EXTICR4_EXTI15_Msk /*!< EXTI 15 configuration */
+
+/* EXTI12 configuration */
+#define AFIO_EXTICR4_EXTI12_PA ((uint32_t)0x00000000) /*!< PA[12] pin */
+#define AFIO_EXTICR4_EXTI12_PB_Pos (0U)
+#define AFIO_EXTICR4_EXTI12_PB_Msk (0x1U << AFIO_EXTICR4_EXTI12_PB_Pos) /*!< 0x00000001 */
+#define AFIO_EXTICR4_EXTI12_PB AFIO_EXTICR4_EXTI12_PB_Msk /*!< PB[12] pin */
+#define AFIO_EXTICR4_EXTI12_PC_Pos (1U)
+#define AFIO_EXTICR4_EXTI12_PC_Msk (0x1U << AFIO_EXTICR4_EXTI12_PC_Pos) /*!< 0x00000002 */
+#define AFIO_EXTICR4_EXTI12_PC AFIO_EXTICR4_EXTI12_PC_Msk /*!< PC[12] pin */
+#define AFIO_EXTICR4_EXTI12_PD_Pos (0U)
+#define AFIO_EXTICR4_EXTI12_PD_Msk (0x3U << AFIO_EXTICR4_EXTI12_PD_Pos) /*!< 0x00000003 */
+#define AFIO_EXTICR4_EXTI12_PD AFIO_EXTICR4_EXTI12_PD_Msk /*!< PD[12] pin */
+#define AFIO_EXTICR4_EXTI12_PE_Pos (2U)
+#define AFIO_EXTICR4_EXTI12_PE_Msk (0x1U << AFIO_EXTICR4_EXTI12_PE_Pos) /*!< 0x00000004 */
+#define AFIO_EXTICR4_EXTI12_PE AFIO_EXTICR4_EXTI12_PE_Msk /*!< PE[12] pin */
+#define AFIO_EXTICR4_EXTI12_PF_Pos (0U)
+#define AFIO_EXTICR4_EXTI12_PF_Msk (0x5U << AFIO_EXTICR4_EXTI12_PF_Pos) /*!< 0x00000005 */
+#define AFIO_EXTICR4_EXTI12_PF AFIO_EXTICR4_EXTI12_PF_Msk /*!< PF[12] pin */
+#define AFIO_EXTICR4_EXTI12_PG_Pos (1U)
+#define AFIO_EXTICR4_EXTI12_PG_Msk (0x3U << AFIO_EXTICR4_EXTI12_PG_Pos) /*!< 0x00000006 */
+#define AFIO_EXTICR4_EXTI12_PG AFIO_EXTICR4_EXTI12_PG_Msk /*!< PG[12] pin */
+
+/* EXTI13 configuration */
+#define AFIO_EXTICR4_EXTI13_PA ((uint32_t)0x00000000) /*!< PA[13] pin */
+#define AFIO_EXTICR4_EXTI13_PB_Pos (4U)
+#define AFIO_EXTICR4_EXTI13_PB_Msk (0x1U << AFIO_EXTICR4_EXTI13_PB_Pos) /*!< 0x00000010 */
+#define AFIO_EXTICR4_EXTI13_PB AFIO_EXTICR4_EXTI13_PB_Msk /*!< PB[13] pin */
+#define AFIO_EXTICR4_EXTI13_PC_Pos (5U)
+#define AFIO_EXTICR4_EXTI13_PC_Msk (0x1U << AFIO_EXTICR4_EXTI13_PC_Pos) /*!< 0x00000020 */
+#define AFIO_EXTICR4_EXTI13_PC AFIO_EXTICR4_EXTI13_PC_Msk /*!< PC[13] pin */
+#define AFIO_EXTICR4_EXTI13_PD_Pos (4U)
+#define AFIO_EXTICR4_EXTI13_PD_Msk (0x3U << AFIO_EXTICR4_EXTI13_PD_Pos) /*!< 0x00000030 */
+#define AFIO_EXTICR4_EXTI13_PD AFIO_EXTICR4_EXTI13_PD_Msk /*!< PD[13] pin */
+#define AFIO_EXTICR4_EXTI13_PE_Pos (6U)
+#define AFIO_EXTICR4_EXTI13_PE_Msk (0x1U << AFIO_EXTICR4_EXTI13_PE_Pos) /*!< 0x00000040 */
+#define AFIO_EXTICR4_EXTI13_PE AFIO_EXTICR4_EXTI13_PE_Msk /*!< PE[13] pin */
+#define AFIO_EXTICR4_EXTI13_PF_Pos (4U)
+#define AFIO_EXTICR4_EXTI13_PF_Msk (0x5U << AFIO_EXTICR4_EXTI13_PF_Pos) /*!< 0x00000050 */
+#define AFIO_EXTICR4_EXTI13_PF AFIO_EXTICR4_EXTI13_PF_Msk /*!< PF[13] pin */
+#define AFIO_EXTICR4_EXTI13_PG_Pos (5U)
+#define AFIO_EXTICR4_EXTI13_PG_Msk (0x3U << AFIO_EXTICR4_EXTI13_PG_Pos) /*!< 0x00000060 */
+#define AFIO_EXTICR4_EXTI13_PG AFIO_EXTICR4_EXTI13_PG_Msk /*!< PG[13] pin */
+
+/*!< EXTI14 configuration */
+#define AFIO_EXTICR4_EXTI14_PA ((uint32_t)0x00000000) /*!< PA[14] pin */
+#define AFIO_EXTICR4_EXTI14_PB_Pos (8U)
+#define AFIO_EXTICR4_EXTI14_PB_Msk (0x1U << AFIO_EXTICR4_EXTI14_PB_Pos) /*!< 0x00000100 */
+#define AFIO_EXTICR4_EXTI14_PB AFIO_EXTICR4_EXTI14_PB_Msk /*!< PB[14] pin */
+#define AFIO_EXTICR4_EXTI14_PC_Pos (9U)
+#define AFIO_EXTICR4_EXTI14_PC_Msk (0x1U << AFIO_EXTICR4_EXTI14_PC_Pos) /*!< 0x00000200 */
+#define AFIO_EXTICR4_EXTI14_PC AFIO_EXTICR4_EXTI14_PC_Msk /*!< PC[14] pin */
+#define AFIO_EXTICR4_EXTI14_PD_Pos (8U)
+#define AFIO_EXTICR4_EXTI14_PD_Msk (0x3U << AFIO_EXTICR4_EXTI14_PD_Pos) /*!< 0x00000300 */
+#define AFIO_EXTICR4_EXTI14_PD AFIO_EXTICR4_EXTI14_PD_Msk /*!< PD[14] pin */
+#define AFIO_EXTICR4_EXTI14_PE_Pos (10U)
+#define AFIO_EXTICR4_EXTI14_PE_Msk (0x1U << AFIO_EXTICR4_EXTI14_PE_Pos) /*!< 0x00000400 */
+#define AFIO_EXTICR4_EXTI14_PE AFIO_EXTICR4_EXTI14_PE_Msk /*!< PE[14] pin */
+#define AFIO_EXTICR4_EXTI14_PF_Pos (8U)
+#define AFIO_EXTICR4_EXTI14_PF_Msk (0x5U << AFIO_EXTICR4_EXTI14_PF_Pos) /*!< 0x00000500 */
+#define AFIO_EXTICR4_EXTI14_PF AFIO_EXTICR4_EXTI14_PF_Msk /*!< PF[14] pin */
+#define AFIO_EXTICR4_EXTI14_PG_Pos (9U)
+#define AFIO_EXTICR4_EXTI14_PG_Msk (0x3U << AFIO_EXTICR4_EXTI14_PG_Pos) /*!< 0x00000600 */
+#define AFIO_EXTICR4_EXTI14_PG AFIO_EXTICR4_EXTI14_PG_Msk /*!< PG[14] pin */
+
+/*!< EXTI15 configuration */
+#define AFIO_EXTICR4_EXTI15_PA ((uint32_t)0x00000000) /*!< PA[15] pin */
+#define AFIO_EXTICR4_EXTI15_PB_Pos (12U)
+#define AFIO_EXTICR4_EXTI15_PB_Msk (0x1U << AFIO_EXTICR4_EXTI15_PB_Pos) /*!< 0x00001000 */
+#define AFIO_EXTICR4_EXTI15_PB AFIO_EXTICR4_EXTI15_PB_Msk /*!< PB[15] pin */
+#define AFIO_EXTICR4_EXTI15_PC_Pos (13U)
+#define AFIO_EXTICR4_EXTI15_PC_Msk (0x1U << AFIO_EXTICR4_EXTI15_PC_Pos) /*!< 0x00002000 */
+#define AFIO_EXTICR4_EXTI15_PC AFIO_EXTICR4_EXTI15_PC_Msk /*!< PC[15] pin */
+#define AFIO_EXTICR4_EXTI15_PD_Pos (12U)
+#define AFIO_EXTICR4_EXTI15_PD_Msk (0x3U << AFIO_EXTICR4_EXTI15_PD_Pos) /*!< 0x00003000 */
+#define AFIO_EXTICR4_EXTI15_PD AFIO_EXTICR4_EXTI15_PD_Msk /*!< PD[15] pin */
+#define AFIO_EXTICR4_EXTI15_PE_Pos (14U)
+#define AFIO_EXTICR4_EXTI15_PE_Msk (0x1U << AFIO_EXTICR4_EXTI15_PE_Pos) /*!< 0x00004000 */
+#define AFIO_EXTICR4_EXTI15_PE AFIO_EXTICR4_EXTI15_PE_Msk /*!< PE[15] pin */
+#define AFIO_EXTICR4_EXTI15_PF_Pos (12U)
+#define AFIO_EXTICR4_EXTI15_PF_Msk (0x5U << AFIO_EXTICR4_EXTI15_PF_Pos) /*!< 0x00005000 */
+#define AFIO_EXTICR4_EXTI15_PF AFIO_EXTICR4_EXTI15_PF_Msk /*!< PF[15] pin */
+#define AFIO_EXTICR4_EXTI15_PG_Pos (13U)
+#define AFIO_EXTICR4_EXTI15_PG_Msk (0x3U << AFIO_EXTICR4_EXTI15_PG_Pos) /*!< 0x00006000 */
+#define AFIO_EXTICR4_EXTI15_PG AFIO_EXTICR4_EXTI15_PG_Msk /*!< PG[15] pin */
+
+/****************** Bit definition for AFIO_MAPR2 register ******************/
+
+
+#define AFIO_MAPR2_FSMC_NADV_REMAP_Pos (10U)
+#define AFIO_MAPR2_FSMC_NADV_REMAP_Msk (0x1U << AFIO_MAPR2_FSMC_NADV_REMAP_Pos) /*!< 0x00000400 */
+#define AFIO_MAPR2_FSMC_NADV_REMAP AFIO_MAPR2_FSMC_NADV_REMAP_Msk /*!< FSMC NADV remapping */
+
+/******************************************************************************/
+/* */
+/* SystemTick */
+/* */
+/******************************************************************************/
+
+/***************** Bit definition for SysTick_CTRL register *****************/
+#define SysTick_CTRL_ENABLE ((uint32_t)0x00000001) /*!< Counter enable */
+#define SysTick_CTRL_TICKINT ((uint32_t)0x00000002) /*!< Counting down to 0 pends the SysTick handler */
+#define SysTick_CTRL_CLKSOURCE ((uint32_t)0x00000004) /*!< Clock source */
+#define SysTick_CTRL_COUNTFLAG ((uint32_t)0x00010000) /*!< Count Flag */
+
+/***************** Bit definition for SysTick_LOAD register *****************/
+#define SysTick_LOAD_RELOAD ((uint32_t)0x00FFFFFF) /*!< Value to load into the SysTick Current Value Register when the counter reaches 0 */
+
+/***************** Bit definition for SysTick_VAL register ******************/
+#define SysTick_VAL_CURRENT ((uint32_t)0x00FFFFFF) /*!< Current value at the time the register is accessed */
+
+/***************** Bit definition for SysTick_CALIB register ****************/
+#define SysTick_CALIB_TENMS ((uint32_t)0x00FFFFFF) /*!< Reload value to use for 10ms timing */
+#define SysTick_CALIB_SKEW ((uint32_t)0x40000000) /*!< Calibration value is not exactly 10 ms */
+#define SysTick_CALIB_NOREF ((uint32_t)0x80000000) /*!< The reference clock is not provided */
+
+/******************************************************************************/
+/* */
+/* Nested Vectored Interrupt Controller */
+/* */
+/******************************************************************************/
+
+/****************** Bit definition for NVIC_ISER register *******************/
+#define NVIC_ISER_SETENA_Pos (0U)
+#define NVIC_ISER_SETENA_Msk (0xFFFFFFFFU << NVIC_ISER_SETENA_Pos) /*!< 0xFFFFFFFF */
+#define NVIC_ISER_SETENA NVIC_ISER_SETENA_Msk /*!< Interrupt set enable bits */
+#define NVIC_ISER_SETENA_0 (0x00000001U << NVIC_ISER_SETENA_Pos) /*!< 0x00000001 */
+#define NVIC_ISER_SETENA_1 (0x00000002U << NVIC_ISER_SETENA_Pos) /*!< 0x00000002 */
+#define NVIC_ISER_SETENA_2 (0x00000004U << NVIC_ISER_SETENA_Pos) /*!< 0x00000004 */
+#define NVIC_ISER_SETENA_3 (0x00000008U << NVIC_ISER_SETENA_Pos) /*!< 0x00000008 */
+#define NVIC_ISER_SETENA_4 (0x00000010U << NVIC_ISER_SETENA_Pos) /*!< 0x00000010 */
+#define NVIC_ISER_SETENA_5 (0x00000020U << NVIC_ISER_SETENA_Pos) /*!< 0x00000020 */
+#define NVIC_ISER_SETENA_6 (0x00000040U << NVIC_ISER_SETENA_Pos) /*!< 0x00000040 */
+#define NVIC_ISER_SETENA_7 (0x00000080U << NVIC_ISER_SETENA_Pos) /*!< 0x00000080 */
+#define NVIC_ISER_SETENA_8 (0x00000100U << NVIC_ISER_SETENA_Pos) /*!< 0x00000100 */
+#define NVIC_ISER_SETENA_9 (0x00000200U << NVIC_ISER_SETENA_Pos) /*!< 0x00000200 */
+#define NVIC_ISER_SETENA_10 (0x00000400U << NVIC_ISER_SETENA_Pos) /*!< 0x00000400 */
+#define NVIC_ISER_SETENA_11 (0x00000800U << NVIC_ISER_SETENA_Pos) /*!< 0x00000800 */
+#define NVIC_ISER_SETENA_12 (0x00001000U << NVIC_ISER_SETENA_Pos) /*!< 0x00001000 */
+#define NVIC_ISER_SETENA_13 (0x00002000U << NVIC_ISER_SETENA_Pos) /*!< 0x00002000 */
+#define NVIC_ISER_SETENA_14 (0x00004000U << NVIC_ISER_SETENA_Pos) /*!< 0x00004000 */
+#define NVIC_ISER_SETENA_15 (0x00008000U << NVIC_ISER_SETENA_Pos) /*!< 0x00008000 */
+#define NVIC_ISER_SETENA_16 (0x00010000U << NVIC_ISER_SETENA_Pos) /*!< 0x00010000 */
+#define NVIC_ISER_SETENA_17 (0x00020000U << NVIC_ISER_SETENA_Pos) /*!< 0x00020000 */
+#define NVIC_ISER_SETENA_18 (0x00040000U << NVIC_ISER_SETENA_Pos) /*!< 0x00040000 */
+#define NVIC_ISER_SETENA_19 (0x00080000U << NVIC_ISER_SETENA_Pos) /*!< 0x00080000 */
+#define NVIC_ISER_SETENA_20 (0x00100000U << NVIC_ISER_SETENA_Pos) /*!< 0x00100000 */
+#define NVIC_ISER_SETENA_21 (0x00200000U << NVIC_ISER_SETENA_Pos) /*!< 0x00200000 */
+#define NVIC_ISER_SETENA_22 (0x00400000U << NVIC_ISER_SETENA_Pos) /*!< 0x00400000 */
+#define NVIC_ISER_SETENA_23 (0x00800000U << NVIC_ISER_SETENA_Pos) /*!< 0x00800000 */
+#define NVIC_ISER_SETENA_24 (0x01000000U << NVIC_ISER_SETENA_Pos) /*!< 0x01000000 */
+#define NVIC_ISER_SETENA_25 (0x02000000U << NVIC_ISER_SETENA_Pos) /*!< 0x02000000 */
+#define NVIC_ISER_SETENA_26 (0x04000000U << NVIC_ISER_SETENA_Pos) /*!< 0x04000000 */
+#define NVIC_ISER_SETENA_27 (0x08000000U << NVIC_ISER_SETENA_Pos) /*!< 0x08000000 */
+#define NVIC_ISER_SETENA_28 (0x10000000U << NVIC_ISER_SETENA_Pos) /*!< 0x10000000 */
+#define NVIC_ISER_SETENA_29 (0x20000000U << NVIC_ISER_SETENA_Pos) /*!< 0x20000000 */
+#define NVIC_ISER_SETENA_30 (0x40000000U << NVIC_ISER_SETENA_Pos) /*!< 0x40000000 */
+#define NVIC_ISER_SETENA_31 (0x80000000U << NVIC_ISER_SETENA_Pos) /*!< 0x80000000 */
+
+/****************** Bit definition for NVIC_ICER register *******************/
+#define NVIC_ICER_CLRENA_Pos (0U)
+#define NVIC_ICER_CLRENA_Msk (0xFFFFFFFFU << NVIC_ICER_CLRENA_Pos) /*!< 0xFFFFFFFF */
+#define NVIC_ICER_CLRENA NVIC_ICER_CLRENA_Msk /*!< Interrupt clear-enable bits */
+#define NVIC_ICER_CLRENA_0 (0x00000001U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000001 */
+#define NVIC_ICER_CLRENA_1 (0x00000002U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000002 */
+#define NVIC_ICER_CLRENA_2 (0x00000004U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000004 */
+#define NVIC_ICER_CLRENA_3 (0x00000008U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000008 */
+#define NVIC_ICER_CLRENA_4 (0x00000010U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000010 */
+#define NVIC_ICER_CLRENA_5 (0x00000020U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000020 */
+#define NVIC_ICER_CLRENA_6 (0x00000040U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000040 */
+#define NVIC_ICER_CLRENA_7 (0x00000080U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000080 */
+#define NVIC_ICER_CLRENA_8 (0x00000100U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000100 */
+#define NVIC_ICER_CLRENA_9 (0x00000200U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000200 */
+#define NVIC_ICER_CLRENA_10 (0x00000400U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000400 */
+#define NVIC_ICER_CLRENA_11 (0x00000800U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000800 */
+#define NVIC_ICER_CLRENA_12 (0x00001000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00001000 */
+#define NVIC_ICER_CLRENA_13 (0x00002000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00002000 */
+#define NVIC_ICER_CLRENA_14 (0x00004000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00004000 */
+#define NVIC_ICER_CLRENA_15 (0x00008000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00008000 */
+#define NVIC_ICER_CLRENA_16 (0x00010000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00010000 */
+#define NVIC_ICER_CLRENA_17 (0x00020000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00020000 */
+#define NVIC_ICER_CLRENA_18 (0x00040000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00040000 */
+#define NVIC_ICER_CLRENA_19 (0x00080000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00080000 */
+#define NVIC_ICER_CLRENA_20 (0x00100000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00100000 */
+#define NVIC_ICER_CLRENA_21 (0x00200000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00200000 */
+#define NVIC_ICER_CLRENA_22 (0x00400000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00400000 */
+#define NVIC_ICER_CLRENA_23 (0x00800000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00800000 */
+#define NVIC_ICER_CLRENA_24 (0x01000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x01000000 */
+#define NVIC_ICER_CLRENA_25 (0x02000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x02000000 */
+#define NVIC_ICER_CLRENA_26 (0x04000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x04000000 */
+#define NVIC_ICER_CLRENA_27 (0x08000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x08000000 */
+#define NVIC_ICER_CLRENA_28 (0x10000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x10000000 */
+#define NVIC_ICER_CLRENA_29 (0x20000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x20000000 */
+#define NVIC_ICER_CLRENA_30 (0x40000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x40000000 */
+#define NVIC_ICER_CLRENA_31 (0x80000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x80000000 */
+
+/****************** Bit definition for NVIC_ISPR register *******************/
+#define NVIC_ISPR_SETPEND_Pos (0U)
+#define NVIC_ISPR_SETPEND_Msk (0xFFFFFFFFU << NVIC_ISPR_SETPEND_Pos) /*!< 0xFFFFFFFF */
+#define NVIC_ISPR_SETPEND NVIC_ISPR_SETPEND_Msk /*!< Interrupt set-pending bits */
+#define NVIC_ISPR_SETPEND_0 (0x00000001U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000001 */
+#define NVIC_ISPR_SETPEND_1 (0x00000002U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000002 */
+#define NVIC_ISPR_SETPEND_2 (0x00000004U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000004 */
+#define NVIC_ISPR_SETPEND_3 (0x00000008U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000008 */
+#define NVIC_ISPR_SETPEND_4 (0x00000010U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000010 */
+#define NVIC_ISPR_SETPEND_5 (0x00000020U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000020 */
+#define NVIC_ISPR_SETPEND_6 (0x00000040U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000040 */
+#define NVIC_ISPR_SETPEND_7 (0x00000080U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000080 */
+#define NVIC_ISPR_SETPEND_8 (0x00000100U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000100 */
+#define NVIC_ISPR_SETPEND_9 (0x00000200U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000200 */
+#define NVIC_ISPR_SETPEND_10 (0x00000400U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000400 */
+#define NVIC_ISPR_SETPEND_11 (0x00000800U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000800 */
+#define NVIC_ISPR_SETPEND_12 (0x00001000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00001000 */
+#define NVIC_ISPR_SETPEND_13 (0x00002000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00002000 */
+#define NVIC_ISPR_SETPEND_14 (0x00004000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00004000 */
+#define NVIC_ISPR_SETPEND_15 (0x00008000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00008000 */
+#define NVIC_ISPR_SETPEND_16 (0x00010000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00010000 */
+#define NVIC_ISPR_SETPEND_17 (0x00020000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00020000 */
+#define NVIC_ISPR_SETPEND_18 (0x00040000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00040000 */
+#define NVIC_ISPR_SETPEND_19 (0x00080000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00080000 */
+#define NVIC_ISPR_SETPEND_20 (0x00100000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00100000 */
+#define NVIC_ISPR_SETPEND_21 (0x00200000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00200000 */
+#define NVIC_ISPR_SETPEND_22 (0x00400000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00400000 */
+#define NVIC_ISPR_SETPEND_23 (0x00800000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00800000 */
+#define NVIC_ISPR_SETPEND_24 (0x01000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x01000000 */
+#define NVIC_ISPR_SETPEND_25 (0x02000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x02000000 */
+#define NVIC_ISPR_SETPEND_26 (0x04000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x04000000 */
+#define NVIC_ISPR_SETPEND_27 (0x08000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x08000000 */
+#define NVIC_ISPR_SETPEND_28 (0x10000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x10000000 */
+#define NVIC_ISPR_SETPEND_29 (0x20000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x20000000 */
+#define NVIC_ISPR_SETPEND_30 (0x40000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x40000000 */
+#define NVIC_ISPR_SETPEND_31 (0x80000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x80000000 */
+
+/****************** Bit definition for NVIC_ICPR register *******************/
+#define NVIC_ICPR_CLRPEND_Pos (0U)
+#define NVIC_ICPR_CLRPEND_Msk (0xFFFFFFFFU << NVIC_ICPR_CLRPEND_Pos) /*!< 0xFFFFFFFF */
+#define NVIC_ICPR_CLRPEND NVIC_ICPR_CLRPEND_Msk /*!< Interrupt clear-pending bits */
+#define NVIC_ICPR_CLRPEND_0 (0x00000001U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000001 */
+#define NVIC_ICPR_CLRPEND_1 (0x00000002U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000002 */
+#define NVIC_ICPR_CLRPEND_2 (0x00000004U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000004 */
+#define NVIC_ICPR_CLRPEND_3 (0x00000008U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000008 */
+#define NVIC_ICPR_CLRPEND_4 (0x00000010U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000010 */
+#define NVIC_ICPR_CLRPEND_5 (0x00000020U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000020 */
+#define NVIC_ICPR_CLRPEND_6 (0x00000040U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000040 */
+#define NVIC_ICPR_CLRPEND_7 (0x00000080U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000080 */
+#define NVIC_ICPR_CLRPEND_8 (0x00000100U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000100 */
+#define NVIC_ICPR_CLRPEND_9 (0x00000200U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000200 */
+#define NVIC_ICPR_CLRPEND_10 (0x00000400U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000400 */
+#define NVIC_ICPR_CLRPEND_11 (0x00000800U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000800 */
+#define NVIC_ICPR_CLRPEND_12 (0x00001000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00001000 */
+#define NVIC_ICPR_CLRPEND_13 (0x00002000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00002000 */
+#define NVIC_ICPR_CLRPEND_14 (0x00004000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00004000 */
+#define NVIC_ICPR_CLRPEND_15 (0x00008000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00008000 */
+#define NVIC_ICPR_CLRPEND_16 (0x00010000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00010000 */
+#define NVIC_ICPR_CLRPEND_17 (0x00020000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00020000 */
+#define NVIC_ICPR_CLRPEND_18 (0x00040000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00040000 */
+#define NVIC_ICPR_CLRPEND_19 (0x00080000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00080000 */
+#define NVIC_ICPR_CLRPEND_20 (0x00100000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00100000 */
+#define NVIC_ICPR_CLRPEND_21 (0x00200000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00200000 */
+#define NVIC_ICPR_CLRPEND_22 (0x00400000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00400000 */
+#define NVIC_ICPR_CLRPEND_23 (0x00800000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00800000 */
+#define NVIC_ICPR_CLRPEND_24 (0x01000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x01000000 */
+#define NVIC_ICPR_CLRPEND_25 (0x02000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x02000000 */
+#define NVIC_ICPR_CLRPEND_26 (0x04000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x04000000 */
+#define NVIC_ICPR_CLRPEND_27 (0x08000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x08000000 */
+#define NVIC_ICPR_CLRPEND_28 (0x10000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x10000000 */
+#define NVIC_ICPR_CLRPEND_29 (0x20000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x20000000 */
+#define NVIC_ICPR_CLRPEND_30 (0x40000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x40000000 */
+#define NVIC_ICPR_CLRPEND_31 (0x80000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x80000000 */
+
+/****************** Bit definition for NVIC_IABR register *******************/
+#define NVIC_IABR_ACTIVE_Pos (0U)
+#define NVIC_IABR_ACTIVE_Msk (0xFFFFFFFFU << NVIC_IABR_ACTIVE_Pos) /*!< 0xFFFFFFFF */
+#define NVIC_IABR_ACTIVE NVIC_IABR_ACTIVE_Msk /*!< Interrupt active flags */
+#define NVIC_IABR_ACTIVE_0 (0x00000001U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000001 */
+#define NVIC_IABR_ACTIVE_1 (0x00000002U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000002 */
+#define NVIC_IABR_ACTIVE_2 (0x00000004U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000004 */
+#define NVIC_IABR_ACTIVE_3 (0x00000008U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000008 */
+#define NVIC_IABR_ACTIVE_4 (0x00000010U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000010 */
+#define NVIC_IABR_ACTIVE_5 (0x00000020U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000020 */
+#define NVIC_IABR_ACTIVE_6 (0x00000040U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000040 */
+#define NVIC_IABR_ACTIVE_7 (0x00000080U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000080 */
+#define NVIC_IABR_ACTIVE_8 (0x00000100U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000100 */
+#define NVIC_IABR_ACTIVE_9 (0x00000200U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000200 */
+#define NVIC_IABR_ACTIVE_10 (0x00000400U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000400 */
+#define NVIC_IABR_ACTIVE_11 (0x00000800U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000800 */
+#define NVIC_IABR_ACTIVE_12 (0x00001000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00001000 */
+#define NVIC_IABR_ACTIVE_13 (0x00002000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00002000 */
+#define NVIC_IABR_ACTIVE_14 (0x00004000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00004000 */
+#define NVIC_IABR_ACTIVE_15 (0x00008000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00008000 */
+#define NVIC_IABR_ACTIVE_16 (0x00010000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00010000 */
+#define NVIC_IABR_ACTIVE_17 (0x00020000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00020000 */
+#define NVIC_IABR_ACTIVE_18 (0x00040000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00040000 */
+#define NVIC_IABR_ACTIVE_19 (0x00080000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00080000 */
+#define NVIC_IABR_ACTIVE_20 (0x00100000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00100000 */
+#define NVIC_IABR_ACTIVE_21 (0x00200000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00200000 */
+#define NVIC_IABR_ACTIVE_22 (0x00400000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00400000 */
+#define NVIC_IABR_ACTIVE_23 (0x00800000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00800000 */
+#define NVIC_IABR_ACTIVE_24 (0x01000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x01000000 */
+#define NVIC_IABR_ACTIVE_25 (0x02000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x02000000 */
+#define NVIC_IABR_ACTIVE_26 (0x04000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x04000000 */
+#define NVIC_IABR_ACTIVE_27 (0x08000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x08000000 */
+#define NVIC_IABR_ACTIVE_28 (0x10000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x10000000 */
+#define NVIC_IABR_ACTIVE_29 (0x20000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x20000000 */
+#define NVIC_IABR_ACTIVE_30 (0x40000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x40000000 */
+#define NVIC_IABR_ACTIVE_31 (0x80000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x80000000 */
+
+/****************** Bit definition for NVIC_PRI0 register *******************/
+#define NVIC_IPR0_PRI_0 ((uint32_t)0x000000FF) /*!< Priority of interrupt 0 */
+#define NVIC_IPR0_PRI_1 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 1 */
+#define NVIC_IPR0_PRI_2 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 2 */
+#define NVIC_IPR0_PRI_3 ((uint32_t)0xFF000000) /*!< Priority of interrupt 3 */
+
+/****************** Bit definition for NVIC_PRI1 register *******************/
+#define NVIC_IPR1_PRI_4 ((uint32_t)0x000000FF) /*!< Priority of interrupt 4 */
+#define NVIC_IPR1_PRI_5 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 5 */
+#define NVIC_IPR1_PRI_6 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 6 */
+#define NVIC_IPR1_PRI_7 ((uint32_t)0xFF000000) /*!< Priority of interrupt 7 */
+
+/****************** Bit definition for NVIC_PRI2 register *******************/
+#define NVIC_IPR2_PRI_8 ((uint32_t)0x000000FF) /*!< Priority of interrupt 8 */
+#define NVIC_IPR2_PRI_9 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 9 */
+#define NVIC_IPR2_PRI_10 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 10 */
+#define NVIC_IPR2_PRI_11 ((uint32_t)0xFF000000) /*!< Priority of interrupt 11 */
+
+/****************** Bit definition for NVIC_PRI3 register *******************/
+#define NVIC_IPR3_PRI_12 ((uint32_t)0x000000FF) /*!< Priority of interrupt 12 */
+#define NVIC_IPR3_PRI_13 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 13 */
+#define NVIC_IPR3_PRI_14 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 14 */
+#define NVIC_IPR3_PRI_15 ((uint32_t)0xFF000000) /*!< Priority of interrupt 15 */
+
+/****************** Bit definition for NVIC_PRI4 register *******************/
+#define NVIC_IPR4_PRI_16 ((uint32_t)0x000000FF) /*!< Priority of interrupt 16 */
+#define NVIC_IPR4_PRI_17 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 17 */
+#define NVIC_IPR4_PRI_18 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 18 */
+#define NVIC_IPR4_PRI_19 ((uint32_t)0xFF000000) /*!< Priority of interrupt 19 */
+
+/****************** Bit definition for NVIC_PRI5 register *******************/
+#define NVIC_IPR5_PRI_20 ((uint32_t)0x000000FF) /*!< Priority of interrupt 20 */
+#define NVIC_IPR5_PRI_21 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 21 */
+#define NVIC_IPR5_PRI_22 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 22 */
+#define NVIC_IPR5_PRI_23 ((uint32_t)0xFF000000) /*!< Priority of interrupt 23 */
+
+/****************** Bit definition for NVIC_PRI6 register *******************/
+#define NVIC_IPR6_PRI_24 ((uint32_t)0x000000FF) /*!< Priority of interrupt 24 */
+#define NVIC_IPR6_PRI_25 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 25 */
+#define NVIC_IPR6_PRI_26 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 26 */
+#define NVIC_IPR6_PRI_27 ((uint32_t)0xFF000000) /*!< Priority of interrupt 27 */
+
+/****************** Bit definition for NVIC_PRI7 register *******************/
+#define NVIC_IPR7_PRI_28 ((uint32_t)0x000000FF) /*!< Priority of interrupt 28 */
+#define NVIC_IPR7_PRI_29 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 29 */
+#define NVIC_IPR7_PRI_30 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 30 */
+#define NVIC_IPR7_PRI_31 ((uint32_t)0xFF000000) /*!< Priority of interrupt 31 */
+
+/****************** Bit definition for SCB_CPUID register *******************/
+#define SCB_CPUID_REVISION ((uint32_t)0x0000000F) /*!< Implementation defined revision number */
+#define SCB_CPUID_PARTNO ((uint32_t)0x0000FFF0) /*!< Number of processor within family */
+#define SCB_CPUID_Constant ((uint32_t)0x000F0000) /*!< Reads as 0x0F */
+#define SCB_CPUID_VARIANT ((uint32_t)0x00F00000) /*!< Implementation defined variant number */
+#define SCB_CPUID_IMPLEMENTER ((uint32_t)0xFF000000) /*!< Implementer code. ARM is 0x41 */
+
+/******************* Bit definition for SCB_ICSR register *******************/
+#define SCB_ICSR_VECTACTIVE ((uint32_t)0x000001FF) /*!< Active ISR number field */
+#define SCB_ICSR_RETTOBASE ((uint32_t)0x00000800) /*!< All active exceptions minus the IPSR_current_exception yields the empty set */
+#define SCB_ICSR_VECTPENDING ((uint32_t)0x003FF000) /*!< Pending ISR number field */
+#define SCB_ICSR_ISRPENDING ((uint32_t)0x00400000) /*!< Interrupt pending flag */
+#define SCB_ICSR_ISRPREEMPT ((uint32_t)0x00800000) /*!< It indicates that a pending interrupt becomes active in the next running cycle */
+#define SCB_ICSR_PENDSTCLR ((uint32_t)0x02000000) /*!< Clear pending SysTick bit */
+#define SCB_ICSR_PENDSTSET ((uint32_t)0x04000000) /*!< Set pending SysTick bit */
+#define SCB_ICSR_PENDSVCLR ((uint32_t)0x08000000) /*!< Clear pending pendSV bit */
+#define SCB_ICSR_PENDSVSET ((uint32_t)0x10000000) /*!< Set pending pendSV bit */
+#define SCB_ICSR_NMIPENDSET ((uint32_t)0x80000000) /*!< Set pending NMI bit */
+
+/******************* Bit definition for SCB_VTOR register *******************/
+#define SCB_VTOR_TBLOFF ((uint32_t)0x1FFFFF80) /*!< Vector table base offset field */
+#define SCB_VTOR_TBLBASE ((uint32_t)0x20000000) /*!< Table base in code(0) or RAM(1) */
+
+/*!<***************** Bit definition for SCB_AIRCR register *******************/
+#define SCB_AIRCR_VECTRESET ((uint32_t)0x00000001) /*!< System Reset bit */
+#define SCB_AIRCR_VECTCLRACTIVE ((uint32_t)0x00000002) /*!< Clear active vector bit */
+#define SCB_AIRCR_SYSRESETREQ ((uint32_t)0x00000004) /*!< Requests chip control logic to generate a reset */
+
+#define SCB_AIRCR_PRIGROUP ((uint32_t)0x00000700) /*!< PRIGROUP[2:0] bits (Priority group) */
+#define SCB_AIRCR_PRIGROUP_0 ((uint32_t)0x00000100) /*!< Bit 0 */
+#define SCB_AIRCR_PRIGROUP_1 ((uint32_t)0x00000200) /*!< Bit 1 */
+#define SCB_AIRCR_PRIGROUP_2 ((uint32_t)0x00000400) /*!< Bit 2 */
+
+/* prority group configuration */
+#define SCB_AIRCR_PRIGROUP0 ((uint32_t)0x00000000) /*!< Priority group=0 (7 bits of pre-emption priority, 1 bit of subpriority) */
+#define SCB_AIRCR_PRIGROUP1 ((uint32_t)0x00000100) /*!< Priority group=1 (6 bits of pre-emption priority, 2 bits of subpriority) */
+#define SCB_AIRCR_PRIGROUP2 ((uint32_t)0x00000200) /*!< Priority group=2 (5 bits of pre-emption priority, 3 bits of subpriority) */
+#define SCB_AIRCR_PRIGROUP3 ((uint32_t)0x00000300) /*!< Priority group=3 (4 bits of pre-emption priority, 4 bits of subpriority) */
+#define SCB_AIRCR_PRIGROUP4 ((uint32_t)0x00000400) /*!< Priority group=4 (3 bits of pre-emption priority, 5 bits of subpriority) */
+#define SCB_AIRCR_PRIGROUP5 ((uint32_t)0x00000500) /*!< Priority group=5 (2 bits of pre-emption priority, 6 bits of subpriority) */
+#define SCB_AIRCR_PRIGROUP6 ((uint32_t)0x00000600) /*!< Priority group=6 (1 bit of pre-emption priority, 7 bits of subpriority) */
+#define SCB_AIRCR_PRIGROUP7 ((uint32_t)0x00000700) /*!< Priority group=7 (no pre-emption priority, 8 bits of subpriority) */
+
+#define SCB_AIRCR_ENDIANESS ((uint32_t)0x00008000) /*!< Data endianness bit */
+#define SCB_AIRCR_VECTKEY ((uint32_t)0xFFFF0000) /*!< Register key (VECTKEY) - Reads as 0xFA05 (VECTKEYSTAT) */
+
+/******************* Bit definition for SCB_SCR register ********************/
+#define SCB_SCR_SLEEPONEXIT ((uint32_t)0x00000002) /*!< Sleep on exit bit */
+#define SCB_SCR_SLEEPDEEP ((uint32_t)0x00000004) /*!< Sleep deep bit */
+#define SCB_SCR_SEVONPEND ((uint32_t)0x00000010) /*!< Wake up from WFE */
+
+/******************** Bit definition for SCB_CCR register *******************/
+#define SCB_CCR_NONBASETHRDENA ((uint32_t)0x00000001) /*!< Thread mode can be entered from any level in Handler mode by controlled return value */
+#define SCB_CCR_USERSETMPEND ((uint32_t)0x00000002) /*!< Enables user code to write the Software Trigger Interrupt register to trigger (pend) a Main exception */
+#define SCB_CCR_UNALIGN_TRP ((uint32_t)0x00000008) /*!< Trap for unaligned access */
+#define SCB_CCR_DIV_0_TRP ((uint32_t)0x00000010) /*!< Trap on Divide by 0 */
+#define SCB_CCR_BFHFNMIGN ((uint32_t)0x00000100) /*!< Handlers running at priority -1 and -2 */
+#define SCB_CCR_STKALIGN ((uint32_t)0x00000200) /*!< On exception entry, the SP used prior to the exception is adjusted to be 8-byte aligned */
+
+/******************* Bit definition for SCB_SHPR register ********************/
+#define SCB_SHPR_PRI_N_Pos (0U)
+#define SCB_SHPR_PRI_N_Msk (0xFFU << SCB_SHPR_PRI_N_Pos) /*!< 0x000000FF */
+#define SCB_SHPR_PRI_N SCB_SHPR_PRI_N_Msk /*!< Priority of system handler 4,8, and 12. Mem Manage, reserved and Debug Monitor */
+#define SCB_SHPR_PRI_N1_Pos (8U)
+#define SCB_SHPR_PRI_N1_Msk (0xFFU << SCB_SHPR_PRI_N1_Pos) /*!< 0x0000FF00 */
+#define SCB_SHPR_PRI_N1 SCB_SHPR_PRI_N1_Msk /*!< Priority of system handler 5,9, and 13. Bus Fault, reserved and reserved */
+#define SCB_SHPR_PRI_N2_Pos (16U)
+#define SCB_SHPR_PRI_N2_Msk (0xFFU << SCB_SHPR_PRI_N2_Pos) /*!< 0x00FF0000 */
+#define SCB_SHPR_PRI_N2 SCB_SHPR_PRI_N2_Msk /*!< Priority of system handler 6,10, and 14. Usage Fault, reserved and PendSV */
+#define SCB_SHPR_PRI_N3_Pos (24U)
+#define SCB_SHPR_PRI_N3_Msk (0xFFU << SCB_SHPR_PRI_N3_Pos) /*!< 0xFF000000 */
+#define SCB_SHPR_PRI_N3 SCB_SHPR_PRI_N3_Msk /*!< Priority of system handler 7,11, and 15. Reserved, SVCall and SysTick */
+
+/****************** Bit definition for SCB_SHCSR register *******************/
+#define SCB_SHCSR_MEMFAULTACT ((uint32_t)0x00000001) /*!< MemManage is active */
+#define SCB_SHCSR_BUSFAULTACT ((uint32_t)0x00000002) /*!< BusFault is active */
+#define SCB_SHCSR_USGFAULTACT ((uint32_t)0x00000008) /*!< UsageFault is active */
+#define SCB_SHCSR_SVCALLACT ((uint32_t)0x00000080) /*!< SVCall is active */
+#define SCB_SHCSR_MONITORACT ((uint32_t)0x00000100) /*!< Monitor is active */
+#define SCB_SHCSR_PENDSVACT ((uint32_t)0x00000400) /*!< PendSV is active */
+#define SCB_SHCSR_SYSTICKACT ((uint32_t)0x00000800) /*!< SysTick is active */
+#define SCB_SHCSR_USGFAULTPENDED ((uint32_t)0x00001000) /*!< Usage Fault is pended */
+#define SCB_SHCSR_MEMFAULTPENDED ((uint32_t)0x00002000) /*!< MemManage is pended */
+#define SCB_SHCSR_BUSFAULTPENDED ((uint32_t)0x00004000) /*!< Bus Fault is pended */
+#define SCB_SHCSR_SVCALLPENDED ((uint32_t)0x00008000) /*!< SVCall is pended */
+#define SCB_SHCSR_MEMFAULTENA ((uint32_t)0x00010000) /*!< MemManage enable */
+#define SCB_SHCSR_BUSFAULTENA ((uint32_t)0x00020000) /*!< Bus Fault enable */
+#define SCB_SHCSR_USGFAULTENA ((uint32_t)0x00040000) /*!< UsageFault enable */
+
+/******************* Bit definition for SCB_CFSR register *******************/
+/*!< MFSR */
+#define SCB_CFSR_IACCVIOL_Pos (0U)
+#define SCB_CFSR_IACCVIOL_Msk (0x1U << SCB_CFSR_IACCVIOL_Pos) /*!< 0x00000001 */
+#define SCB_CFSR_IACCVIOL SCB_CFSR_IACCVIOL_Msk /*!< Instruction access violation */
+#define SCB_CFSR_DACCVIOL_Pos (1U)
+#define SCB_CFSR_DACCVIOL_Msk (0x1U << SCB_CFSR_DACCVIOL_Pos) /*!< 0x00000002 */
+#define SCB_CFSR_DACCVIOL SCB_CFSR_DACCVIOL_Msk /*!< Data access violation */
+#define SCB_CFSR_MUNSTKERR_Pos (3U)
+#define SCB_CFSR_MUNSTKERR_Msk (0x1U << SCB_CFSR_MUNSTKERR_Pos) /*!< 0x00000008 */
+#define SCB_CFSR_MUNSTKERR SCB_CFSR_MUNSTKERR_Msk /*!< Unstacking error */
+#define SCB_CFSR_MSTKERR_Pos (4U)
+#define SCB_CFSR_MSTKERR_Msk (0x1U << SCB_CFSR_MSTKERR_Pos) /*!< 0x00000010 */
+#define SCB_CFSR_MSTKERR SCB_CFSR_MSTKERR_Msk /*!< Stacking error */
+#define SCB_CFSR_MMARVALID_Pos (7U)
+#define SCB_CFSR_MMARVALID_Msk (0x1U << SCB_CFSR_MMARVALID_Pos) /*!< 0x00000080 */
+#define SCB_CFSR_MMARVALID SCB_CFSR_MMARVALID_Msk /*!< Memory Manage Address Register address valid flag */
+/*!< BFSR */
+#define SCB_CFSR_IBUSERR_Pos (8U)
+#define SCB_CFSR_IBUSERR_Msk (0x1U << SCB_CFSR_IBUSERR_Pos) /*!< 0x00000100 */
+#define SCB_CFSR_IBUSERR SCB_CFSR_IBUSERR_Msk /*!< Instruction bus error flag */
+#define SCB_CFSR_PRECISERR_Pos (9U)
+#define SCB_CFSR_PRECISERR_Msk (0x1U << SCB_CFSR_PRECISERR_Pos) /*!< 0x00000200 */
+#define SCB_CFSR_PRECISERR SCB_CFSR_PRECISERR_Msk /*!< Precise data bus error */
+#define SCB_CFSR_IMPRECISERR_Pos (10U)
+#define SCB_CFSR_IMPRECISERR_Msk (0x1U << SCB_CFSR_IMPRECISERR_Pos) /*!< 0x00000400 */
+#define SCB_CFSR_IMPRECISERR SCB_CFSR_IMPRECISERR_Msk /*!< Imprecise data bus error */
+#define SCB_CFSR_UNSTKERR_Pos (11U)
+#define SCB_CFSR_UNSTKERR_Msk (0x1U << SCB_CFSR_UNSTKERR_Pos) /*!< 0x00000800 */
+#define SCB_CFSR_UNSTKERR SCB_CFSR_UNSTKERR_Msk /*!< Unstacking error */
+#define SCB_CFSR_STKERR_Pos (12U)
+#define SCB_CFSR_STKERR_Msk (0x1U << SCB_CFSR_STKERR_Pos) /*!< 0x00001000 */
+#define SCB_CFSR_STKERR SCB_CFSR_STKERR_Msk /*!< Stacking error */
+#define SCB_CFSR_BFARVALID_Pos (15U)
+#define SCB_CFSR_BFARVALID_Msk (0x1U << SCB_CFSR_BFARVALID_Pos) /*!< 0x00008000 */
+#define SCB_CFSR_BFARVALID SCB_CFSR_BFARVALID_Msk /*!< Bus Fault Address Register address valid flag */
+/*!< UFSR */
+#define SCB_CFSR_UNDEFINSTR_Pos (16U)
+#define SCB_CFSR_UNDEFINSTR_Msk (0x1U << SCB_CFSR_UNDEFINSTR_Pos) /*!< 0x00010000 */
+#define SCB_CFSR_UNDEFINSTR SCB_CFSR_UNDEFINSTR_Msk /*!< The processor attempt to execute an undefined instruction */
+#define SCB_CFSR_INVSTATE_Pos (17U)
+#define SCB_CFSR_INVSTATE_Msk (0x1U << SCB_CFSR_INVSTATE_Pos) /*!< 0x00020000 */
+#define SCB_CFSR_INVSTATE SCB_CFSR_INVSTATE_Msk /*!< Invalid combination of EPSR and instruction */
+#define SCB_CFSR_INVPC_Pos (18U)
+#define SCB_CFSR_INVPC_Msk (0x1U << SCB_CFSR_INVPC_Pos) /*!< 0x00040000 */
+#define SCB_CFSR_INVPC SCB_CFSR_INVPC_Msk /*!< Attempt to load EXC_RETURN into pc illegally */
+#define SCB_CFSR_NOCP_Pos (19U)
+#define SCB_CFSR_NOCP_Msk (0x1U << SCB_CFSR_NOCP_Pos) /*!< 0x00080000 */
+#define SCB_CFSR_NOCP SCB_CFSR_NOCP_Msk /*!< Attempt to use a coprocessor instruction */
+#define SCB_CFSR_UNALIGNED_Pos (24U)
+#define SCB_CFSR_UNALIGNED_Msk (0x1U << SCB_CFSR_UNALIGNED_Pos) /*!< 0x01000000 */
+#define SCB_CFSR_UNALIGNED SCB_CFSR_UNALIGNED_Msk /*!< Fault occurs when there is an attempt to make an unaligned memory access */
+#define SCB_CFSR_DIVBYZERO_Pos (25U)
+#define SCB_CFSR_DIVBYZERO_Msk (0x1U << SCB_CFSR_DIVBYZERO_Pos) /*!< 0x02000000 */
+#define SCB_CFSR_DIVBYZERO SCB_CFSR_DIVBYZERO_Msk /*!< Fault occurs when SDIV or DIV instruction is used with a divisor of 0 */
+
+/******************* Bit definition for SCB_HFSR register *******************/
+#define SCB_HFSR_VECTTBL ((uint32_t)0x00000002) /*!< Fault occurs because of vector table read on exception processing */
+#define SCB_HFSR_FORCED ((uint32_t)0x40000000) /*!< Hard Fault activated when a configurable Fault was received and cannot activate */
+#define SCB_HFSR_DEBUGEVT ((uint32_t)0x80000000) /*!< Fault related to debug */
+
+/******************* Bit definition for SCB_DFSR register *******************/
+#define SCB_DFSR_HALTED ((uint32_t)0x00000001) /*!< Halt request flag */
+#define SCB_DFSR_BKPT ((uint32_t)0x00000002) /*!< BKPT flag */
+#define SCB_DFSR_DWTTRAP ((uint32_t)0x00000004) /*!< Data Watchpoint and Trace (DWT) flag */
+#define SCB_DFSR_VCATCH ((uint32_t)0x00000008) /*!< Vector catch flag */
+#define SCB_DFSR_EXTERNAL ((uint32_t)0x00000010) /*!< External debug request flag */
+
+/******************* Bit definition for SCB_MMFAR register ******************/
+#define SCB_MMFAR_ADDRESS_Pos (0U)
+#define SCB_MMFAR_ADDRESS_Msk (0xFFFFFFFFU << SCB_MMFAR_ADDRESS_Pos) /*!< 0xFFFFFFFF */
+#define SCB_MMFAR_ADDRESS SCB_MMFAR_ADDRESS_Msk /*!< Mem Manage fault address field */
+
+/******************* Bit definition for SCB_BFAR register *******************/
+#define SCB_BFAR_ADDRESS_Pos (0U)
+#define SCB_BFAR_ADDRESS_Msk (0xFFFFFFFFU << SCB_BFAR_ADDRESS_Pos) /*!< 0xFFFFFFFF */
+#define SCB_BFAR_ADDRESS SCB_BFAR_ADDRESS_Msk /*!< Bus fault address field */
+
+/******************* Bit definition for SCB_afsr register *******************/
+#define SCB_AFSR_IMPDEF_Pos (0U)
+#define SCB_AFSR_IMPDEF_Msk (0xFFFFFFFFU << SCB_AFSR_IMPDEF_Pos) /*!< 0xFFFFFFFF */
+#define SCB_AFSR_IMPDEF SCB_AFSR_IMPDEF_Msk /*!< Implementation defined */
+
+/******************************************************************************/
+/* */
+/* External Interrupt/Event Controller */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for EXTI_IMR register *******************/
+#define EXTI_IMR_MR0_Pos (0U)
+#define EXTI_IMR_MR0_Msk (0x1U << EXTI_IMR_MR0_Pos) /*!< 0x00000001 */
+#define EXTI_IMR_MR0 EXTI_IMR_MR0_Msk /*!< Interrupt Mask on line 0 */
+#define EXTI_IMR_MR1_Pos (1U)
+#define EXTI_IMR_MR1_Msk (0x1U << EXTI_IMR_MR1_Pos) /*!< 0x00000002 */
+#define EXTI_IMR_MR1 EXTI_IMR_MR1_Msk /*!< Interrupt Mask on line 1 */
+#define EXTI_IMR_MR2_Pos (2U)
+#define EXTI_IMR_MR2_Msk (0x1U << EXTI_IMR_MR2_Pos) /*!< 0x00000004 */
+#define EXTI_IMR_MR2 EXTI_IMR_MR2_Msk /*!< Interrupt Mask on line 2 */
+#define EXTI_IMR_MR3_Pos (3U)
+#define EXTI_IMR_MR3_Msk (0x1U << EXTI_IMR_MR3_Pos) /*!< 0x00000008 */
+#define EXTI_IMR_MR3 EXTI_IMR_MR3_Msk /*!< Interrupt Mask on line 3 */
+#define EXTI_IMR_MR4_Pos (4U)
+#define EXTI_IMR_MR4_Msk (0x1U << EXTI_IMR_MR4_Pos) /*!< 0x00000010 */
+#define EXTI_IMR_MR4 EXTI_IMR_MR4_Msk /*!< Interrupt Mask on line 4 */
+#define EXTI_IMR_MR5_Pos (5U)
+#define EXTI_IMR_MR5_Msk (0x1U << EXTI_IMR_MR5_Pos) /*!< 0x00000020 */
+#define EXTI_IMR_MR5 EXTI_IMR_MR5_Msk /*!< Interrupt Mask on line 5 */
+#define EXTI_IMR_MR6_Pos (6U)
+#define EXTI_IMR_MR6_Msk (0x1U << EXTI_IMR_MR6_Pos) /*!< 0x00000040 */
+#define EXTI_IMR_MR6 EXTI_IMR_MR6_Msk /*!< Interrupt Mask on line 6 */
+#define EXTI_IMR_MR7_Pos (7U)
+#define EXTI_IMR_MR7_Msk (0x1U << EXTI_IMR_MR7_Pos) /*!< 0x00000080 */
+#define EXTI_IMR_MR7 EXTI_IMR_MR7_Msk /*!< Interrupt Mask on line 7 */
+#define EXTI_IMR_MR8_Pos (8U)
+#define EXTI_IMR_MR8_Msk (0x1U << EXTI_IMR_MR8_Pos) /*!< 0x00000100 */
+#define EXTI_IMR_MR8 EXTI_IMR_MR8_Msk /*!< Interrupt Mask on line 8 */
+#define EXTI_IMR_MR9_Pos (9U)
+#define EXTI_IMR_MR9_Msk (0x1U << EXTI_IMR_MR9_Pos) /*!< 0x00000200 */
+#define EXTI_IMR_MR9 EXTI_IMR_MR9_Msk /*!< Interrupt Mask on line 9 */
+#define EXTI_IMR_MR10_Pos (10U)
+#define EXTI_IMR_MR10_Msk (0x1U << EXTI_IMR_MR10_Pos) /*!< 0x00000400 */
+#define EXTI_IMR_MR10 EXTI_IMR_MR10_Msk /*!< Interrupt Mask on line 10 */
+#define EXTI_IMR_MR11_Pos (11U)
+#define EXTI_IMR_MR11_Msk (0x1U << EXTI_IMR_MR11_Pos) /*!< 0x00000800 */
+#define EXTI_IMR_MR11 EXTI_IMR_MR11_Msk /*!< Interrupt Mask on line 11 */
+#define EXTI_IMR_MR12_Pos (12U)
+#define EXTI_IMR_MR12_Msk (0x1U << EXTI_IMR_MR12_Pos) /*!< 0x00001000 */
+#define EXTI_IMR_MR12 EXTI_IMR_MR12_Msk /*!< Interrupt Mask on line 12 */
+#define EXTI_IMR_MR13_Pos (13U)
+#define EXTI_IMR_MR13_Msk (0x1U << EXTI_IMR_MR13_Pos) /*!< 0x00002000 */
+#define EXTI_IMR_MR13 EXTI_IMR_MR13_Msk /*!< Interrupt Mask on line 13 */
+#define EXTI_IMR_MR14_Pos (14U)
+#define EXTI_IMR_MR14_Msk (0x1U << EXTI_IMR_MR14_Pos) /*!< 0x00004000 */
+#define EXTI_IMR_MR14 EXTI_IMR_MR14_Msk /*!< Interrupt Mask on line 14 */
+#define EXTI_IMR_MR15_Pos (15U)
+#define EXTI_IMR_MR15_Msk (0x1U << EXTI_IMR_MR15_Pos) /*!< 0x00008000 */
+#define EXTI_IMR_MR15 EXTI_IMR_MR15_Msk /*!< Interrupt Mask on line 15 */
+#define EXTI_IMR_MR16_Pos (16U)
+#define EXTI_IMR_MR16_Msk (0x1U << EXTI_IMR_MR16_Pos) /*!< 0x00010000 */
+#define EXTI_IMR_MR16 EXTI_IMR_MR16_Msk /*!< Interrupt Mask on line 16 */
+#define EXTI_IMR_MR17_Pos (17U)
+#define EXTI_IMR_MR17_Msk (0x1U << EXTI_IMR_MR17_Pos) /*!< 0x00020000 */
+#define EXTI_IMR_MR17 EXTI_IMR_MR17_Msk /*!< Interrupt Mask on line 17 */
+#define EXTI_IMR_MR18_Pos (18U)
+#define EXTI_IMR_MR18_Msk (0x1U << EXTI_IMR_MR18_Pos) /*!< 0x00040000 */
+#define EXTI_IMR_MR18 EXTI_IMR_MR18_Msk /*!< Interrupt Mask on line 18 */
+#define EXTI_IMR_MR19_Pos (19U)
+#define EXTI_IMR_MR19_Msk (0x1U << EXTI_IMR_MR19_Pos) /*!< 0x00080000 */
+#define EXTI_IMR_MR19 EXTI_IMR_MR19_Msk /*!< Interrupt Mask on line 19 */
+
+/* References Defines */
+#define EXTI_IMR_IM0 EXTI_IMR_MR0
+#define EXTI_IMR_IM1 EXTI_IMR_MR1
+#define EXTI_IMR_IM2 EXTI_IMR_MR2
+#define EXTI_IMR_IM3 EXTI_IMR_MR3
+#define EXTI_IMR_IM4 EXTI_IMR_MR4
+#define EXTI_IMR_IM5 EXTI_IMR_MR5
+#define EXTI_IMR_IM6 EXTI_IMR_MR6
+#define EXTI_IMR_IM7 EXTI_IMR_MR7
+#define EXTI_IMR_IM8 EXTI_IMR_MR8
+#define EXTI_IMR_IM9 EXTI_IMR_MR9
+#define EXTI_IMR_IM10 EXTI_IMR_MR10
+#define EXTI_IMR_IM11 EXTI_IMR_MR11
+#define EXTI_IMR_IM12 EXTI_IMR_MR12
+#define EXTI_IMR_IM13 EXTI_IMR_MR13
+#define EXTI_IMR_IM14 EXTI_IMR_MR14
+#define EXTI_IMR_IM15 EXTI_IMR_MR15
+#define EXTI_IMR_IM16 EXTI_IMR_MR16
+#define EXTI_IMR_IM17 EXTI_IMR_MR17
+#define EXTI_IMR_IM18 EXTI_IMR_MR18
+#define EXTI_IMR_IM19 EXTI_IMR_MR19
+
+/******************* Bit definition for EXTI_EMR register *******************/
+#define EXTI_EMR_MR0_Pos (0U)
+#define EXTI_EMR_MR0_Msk (0x1U << EXTI_EMR_MR0_Pos) /*!< 0x00000001 */
+#define EXTI_EMR_MR0 EXTI_EMR_MR0_Msk /*!< Event Mask on line 0 */
+#define EXTI_EMR_MR1_Pos (1U)
+#define EXTI_EMR_MR1_Msk (0x1U << EXTI_EMR_MR1_Pos) /*!< 0x00000002 */
+#define EXTI_EMR_MR1 EXTI_EMR_MR1_Msk /*!< Event Mask on line 1 */
+#define EXTI_EMR_MR2_Pos (2U)
+#define EXTI_EMR_MR2_Msk (0x1U << EXTI_EMR_MR2_Pos) /*!< 0x00000004 */
+#define EXTI_EMR_MR2 EXTI_EMR_MR2_Msk /*!< Event Mask on line 2 */
+#define EXTI_EMR_MR3_Pos (3U)
+#define EXTI_EMR_MR3_Msk (0x1U << EXTI_EMR_MR3_Pos) /*!< 0x00000008 */
+#define EXTI_EMR_MR3 EXTI_EMR_MR3_Msk /*!< Event Mask on line 3 */
+#define EXTI_EMR_MR4_Pos (4U)
+#define EXTI_EMR_MR4_Msk (0x1U << EXTI_EMR_MR4_Pos) /*!< 0x00000010 */
+#define EXTI_EMR_MR4 EXTI_EMR_MR4_Msk /*!< Event Mask on line 4 */
+#define EXTI_EMR_MR5_Pos (5U)
+#define EXTI_EMR_MR5_Msk (0x1U << EXTI_EMR_MR5_Pos) /*!< 0x00000020 */
+#define EXTI_EMR_MR5 EXTI_EMR_MR5_Msk /*!< Event Mask on line 5 */
+#define EXTI_EMR_MR6_Pos (6U)
+#define EXTI_EMR_MR6_Msk (0x1U << EXTI_EMR_MR6_Pos) /*!< 0x00000040 */
+#define EXTI_EMR_MR6 EXTI_EMR_MR6_Msk /*!< Event Mask on line 6 */
+#define EXTI_EMR_MR7_Pos (7U)
+#define EXTI_EMR_MR7_Msk (0x1U << EXTI_EMR_MR7_Pos) /*!< 0x00000080 */
+#define EXTI_EMR_MR7 EXTI_EMR_MR7_Msk /*!< Event Mask on line 7 */
+#define EXTI_EMR_MR8_Pos (8U)
+#define EXTI_EMR_MR8_Msk (0x1U << EXTI_EMR_MR8_Pos) /*!< 0x00000100 */
+#define EXTI_EMR_MR8 EXTI_EMR_MR8_Msk /*!< Event Mask on line 8 */
+#define EXTI_EMR_MR9_Pos (9U)
+#define EXTI_EMR_MR9_Msk (0x1U << EXTI_EMR_MR9_Pos) /*!< 0x00000200 */
+#define EXTI_EMR_MR9 EXTI_EMR_MR9_Msk /*!< Event Mask on line 9 */
+#define EXTI_EMR_MR10_Pos (10U)
+#define EXTI_EMR_MR10_Msk (0x1U << EXTI_EMR_MR10_Pos) /*!< 0x00000400 */
+#define EXTI_EMR_MR10 EXTI_EMR_MR10_Msk /*!< Event Mask on line 10 */
+#define EXTI_EMR_MR11_Pos (11U)
+#define EXTI_EMR_MR11_Msk (0x1U << EXTI_EMR_MR11_Pos) /*!< 0x00000800 */
+#define EXTI_EMR_MR11 EXTI_EMR_MR11_Msk /*!< Event Mask on line 11 */
+#define EXTI_EMR_MR12_Pos (12U)
+#define EXTI_EMR_MR12_Msk (0x1U << EXTI_EMR_MR12_Pos) /*!< 0x00001000 */
+#define EXTI_EMR_MR12 EXTI_EMR_MR12_Msk /*!< Event Mask on line 12 */
+#define EXTI_EMR_MR13_Pos (13U)
+#define EXTI_EMR_MR13_Msk (0x1U << EXTI_EMR_MR13_Pos) /*!< 0x00002000 */
+#define EXTI_EMR_MR13 EXTI_EMR_MR13_Msk /*!< Event Mask on line 13 */
+#define EXTI_EMR_MR14_Pos (14U)
+#define EXTI_EMR_MR14_Msk (0x1U << EXTI_EMR_MR14_Pos) /*!< 0x00004000 */
+#define EXTI_EMR_MR14 EXTI_EMR_MR14_Msk /*!< Event Mask on line 14 */
+#define EXTI_EMR_MR15_Pos (15U)
+#define EXTI_EMR_MR15_Msk (0x1U << EXTI_EMR_MR15_Pos) /*!< 0x00008000 */
+#define EXTI_EMR_MR15 EXTI_EMR_MR15_Msk /*!< Event Mask on line 15 */
+#define EXTI_EMR_MR16_Pos (16U)
+#define EXTI_EMR_MR16_Msk (0x1U << EXTI_EMR_MR16_Pos) /*!< 0x00010000 */
+#define EXTI_EMR_MR16 EXTI_EMR_MR16_Msk /*!< Event Mask on line 16 */
+#define EXTI_EMR_MR17_Pos (17U)
+#define EXTI_EMR_MR17_Msk (0x1U << EXTI_EMR_MR17_Pos) /*!< 0x00020000 */
+#define EXTI_EMR_MR17 EXTI_EMR_MR17_Msk /*!< Event Mask on line 17 */
+#define EXTI_EMR_MR18_Pos (18U)
+#define EXTI_EMR_MR18_Msk (0x1U << EXTI_EMR_MR18_Pos) /*!< 0x00040000 */
+#define EXTI_EMR_MR18 EXTI_EMR_MR18_Msk /*!< Event Mask on line 18 */
+#define EXTI_EMR_MR19_Pos (19U)
+#define EXTI_EMR_MR19_Msk (0x1U << EXTI_EMR_MR19_Pos) /*!< 0x00080000 */
+#define EXTI_EMR_MR19 EXTI_EMR_MR19_Msk /*!< Event Mask on line 19 */
+
+/* References Defines */
+#define EXTI_EMR_EM0 EXTI_EMR_MR0
+#define EXTI_EMR_EM1 EXTI_EMR_MR1
+#define EXTI_EMR_EM2 EXTI_EMR_MR2
+#define EXTI_EMR_EM3 EXTI_EMR_MR3
+#define EXTI_EMR_EM4 EXTI_EMR_MR4
+#define EXTI_EMR_EM5 EXTI_EMR_MR5
+#define EXTI_EMR_EM6 EXTI_EMR_MR6
+#define EXTI_EMR_EM7 EXTI_EMR_MR7
+#define EXTI_EMR_EM8 EXTI_EMR_MR8
+#define EXTI_EMR_EM9 EXTI_EMR_MR9
+#define EXTI_EMR_EM10 EXTI_EMR_MR10
+#define EXTI_EMR_EM11 EXTI_EMR_MR11
+#define EXTI_EMR_EM12 EXTI_EMR_MR12
+#define EXTI_EMR_EM13 EXTI_EMR_MR13
+#define EXTI_EMR_EM14 EXTI_EMR_MR14
+#define EXTI_EMR_EM15 EXTI_EMR_MR15
+#define EXTI_EMR_EM16 EXTI_EMR_MR16
+#define EXTI_EMR_EM17 EXTI_EMR_MR17
+#define EXTI_EMR_EM18 EXTI_EMR_MR18
+#define EXTI_EMR_EM19 EXTI_EMR_MR19
+
+/****************** Bit definition for EXTI_RTSR register *******************/
+#define EXTI_RTSR_TR0_Pos (0U)
+#define EXTI_RTSR_TR0_Msk (0x1U << EXTI_RTSR_TR0_Pos) /*!< 0x00000001 */
+#define EXTI_RTSR_TR0 EXTI_RTSR_TR0_Msk /*!< Rising trigger event configuration bit of line 0 */
+#define EXTI_RTSR_TR1_Pos (1U)
+#define EXTI_RTSR_TR1_Msk (0x1U << EXTI_RTSR_TR1_Pos) /*!< 0x00000002 */
+#define EXTI_RTSR_TR1 EXTI_RTSR_TR1_Msk /*!< Rising trigger event configuration bit of line 1 */
+#define EXTI_RTSR_TR2_Pos (2U)
+#define EXTI_RTSR_TR2_Msk (0x1U << EXTI_RTSR_TR2_Pos) /*!< 0x00000004 */
+#define EXTI_RTSR_TR2 EXTI_RTSR_TR2_Msk /*!< Rising trigger event configuration bit of line 2 */
+#define EXTI_RTSR_TR3_Pos (3U)
+#define EXTI_RTSR_TR3_Msk (0x1U << EXTI_RTSR_TR3_Pos) /*!< 0x00000008 */
+#define EXTI_RTSR_TR3 EXTI_RTSR_TR3_Msk /*!< Rising trigger event configuration bit of line 3 */
+#define EXTI_RTSR_TR4_Pos (4U)
+#define EXTI_RTSR_TR4_Msk (0x1U << EXTI_RTSR_TR4_Pos) /*!< 0x00000010 */
+#define EXTI_RTSR_TR4 EXTI_RTSR_TR4_Msk /*!< Rising trigger event configuration bit of line 4 */
+#define EXTI_RTSR_TR5_Pos (5U)
+#define EXTI_RTSR_TR5_Msk (0x1U << EXTI_RTSR_TR5_Pos) /*!< 0x00000020 */
+#define EXTI_RTSR_TR5 EXTI_RTSR_TR5_Msk /*!< Rising trigger event configuration bit of line 5 */
+#define EXTI_RTSR_TR6_Pos (6U)
+#define EXTI_RTSR_TR6_Msk (0x1U << EXTI_RTSR_TR6_Pos) /*!< 0x00000040 */
+#define EXTI_RTSR_TR6 EXTI_RTSR_TR6_Msk /*!< Rising trigger event configuration bit of line 6 */
+#define EXTI_RTSR_TR7_Pos (7U)
+#define EXTI_RTSR_TR7_Msk (0x1U << EXTI_RTSR_TR7_Pos) /*!< 0x00000080 */
+#define EXTI_RTSR_TR7 EXTI_RTSR_TR7_Msk /*!< Rising trigger event configuration bit of line 7 */
+#define EXTI_RTSR_TR8_Pos (8U)
+#define EXTI_RTSR_TR8_Msk (0x1U << EXTI_RTSR_TR8_Pos) /*!< 0x00000100 */
+#define EXTI_RTSR_TR8 EXTI_RTSR_TR8_Msk /*!< Rising trigger event configuration bit of line 8 */
+#define EXTI_RTSR_TR9_Pos (9U)
+#define EXTI_RTSR_TR9_Msk (0x1U << EXTI_RTSR_TR9_Pos) /*!< 0x00000200 */
+#define EXTI_RTSR_TR9 EXTI_RTSR_TR9_Msk /*!< Rising trigger event configuration bit of line 9 */
+#define EXTI_RTSR_TR10_Pos (10U)
+#define EXTI_RTSR_TR10_Msk (0x1U << EXTI_RTSR_TR10_Pos) /*!< 0x00000400 */
+#define EXTI_RTSR_TR10 EXTI_RTSR_TR10_Msk /*!< Rising trigger event configuration bit of line 10 */
+#define EXTI_RTSR_TR11_Pos (11U)
+#define EXTI_RTSR_TR11_Msk (0x1U << EXTI_RTSR_TR11_Pos) /*!< 0x00000800 */
+#define EXTI_RTSR_TR11 EXTI_RTSR_TR11_Msk /*!< Rising trigger event configuration bit of line 11 */
+#define EXTI_RTSR_TR12_Pos (12U)
+#define EXTI_RTSR_TR12_Msk (0x1U << EXTI_RTSR_TR12_Pos) /*!< 0x00001000 */
+#define EXTI_RTSR_TR12 EXTI_RTSR_TR12_Msk /*!< Rising trigger event configuration bit of line 12 */
+#define EXTI_RTSR_TR13_Pos (13U)
+#define EXTI_RTSR_TR13_Msk (0x1U << EXTI_RTSR_TR13_Pos) /*!< 0x00002000 */
+#define EXTI_RTSR_TR13 EXTI_RTSR_TR13_Msk /*!< Rising trigger event configuration bit of line 13 */
+#define EXTI_RTSR_TR14_Pos (14U)
+#define EXTI_RTSR_TR14_Msk (0x1U << EXTI_RTSR_TR14_Pos) /*!< 0x00004000 */
+#define EXTI_RTSR_TR14 EXTI_RTSR_TR14_Msk /*!< Rising trigger event configuration bit of line 14 */
+#define EXTI_RTSR_TR15_Pos (15U)
+#define EXTI_RTSR_TR15_Msk (0x1U << EXTI_RTSR_TR15_Pos) /*!< 0x00008000 */
+#define EXTI_RTSR_TR15 EXTI_RTSR_TR15_Msk /*!< Rising trigger event configuration bit of line 15 */
+#define EXTI_RTSR_TR16_Pos (16U)
+#define EXTI_RTSR_TR16_Msk (0x1U << EXTI_RTSR_TR16_Pos) /*!< 0x00010000 */
+#define EXTI_RTSR_TR16 EXTI_RTSR_TR16_Msk /*!< Rising trigger event configuration bit of line 16 */
+#define EXTI_RTSR_TR17_Pos (17U)
+#define EXTI_RTSR_TR17_Msk (0x1U << EXTI_RTSR_TR17_Pos) /*!< 0x00020000 */
+#define EXTI_RTSR_TR17 EXTI_RTSR_TR17_Msk /*!< Rising trigger event configuration bit of line 17 */
+#define EXTI_RTSR_TR18_Pos (18U)
+#define EXTI_RTSR_TR18_Msk (0x1U << EXTI_RTSR_TR18_Pos) /*!< 0x00040000 */
+#define EXTI_RTSR_TR18 EXTI_RTSR_TR18_Msk /*!< Rising trigger event configuration bit of line 18 */
+#define EXTI_RTSR_TR19_Pos (19U)
+#define EXTI_RTSR_TR19_Msk (0x1U << EXTI_RTSR_TR19_Pos) /*!< 0x00080000 */
+#define EXTI_RTSR_TR19 EXTI_RTSR_TR19_Msk /*!< Rising trigger event configuration bit of line 19 */
+
+/* References Defines */
+#define EXTI_RTSR_RT0 EXTI_RTSR_TR0
+#define EXTI_RTSR_RT1 EXTI_RTSR_TR1
+#define EXTI_RTSR_RT2 EXTI_RTSR_TR2
+#define EXTI_RTSR_RT3 EXTI_RTSR_TR3
+#define EXTI_RTSR_RT4 EXTI_RTSR_TR4
+#define EXTI_RTSR_RT5 EXTI_RTSR_TR5
+#define EXTI_RTSR_RT6 EXTI_RTSR_TR6
+#define EXTI_RTSR_RT7 EXTI_RTSR_TR7
+#define EXTI_RTSR_RT8 EXTI_RTSR_TR8
+#define EXTI_RTSR_RT9 EXTI_RTSR_TR9
+#define EXTI_RTSR_RT10 EXTI_RTSR_TR10
+#define EXTI_RTSR_RT11 EXTI_RTSR_TR11
+#define EXTI_RTSR_RT12 EXTI_RTSR_TR12
+#define EXTI_RTSR_RT13 EXTI_RTSR_TR13
+#define EXTI_RTSR_RT14 EXTI_RTSR_TR14
+#define EXTI_RTSR_RT15 EXTI_RTSR_TR15
+#define EXTI_RTSR_RT16 EXTI_RTSR_TR16
+#define EXTI_RTSR_RT17 EXTI_RTSR_TR17
+#define EXTI_RTSR_RT18 EXTI_RTSR_TR18
+#define EXTI_RTSR_RT19 EXTI_RTSR_TR19
+
+/****************** Bit definition for EXTI_FTSR register *******************/
+#define EXTI_FTSR_TR0_Pos (0U)
+#define EXTI_FTSR_TR0_Msk (0x1U << EXTI_FTSR_TR0_Pos) /*!< 0x00000001 */
+#define EXTI_FTSR_TR0 EXTI_FTSR_TR0_Msk /*!< Falling trigger event configuration bit of line 0 */
+#define EXTI_FTSR_TR1_Pos (1U)
+#define EXTI_FTSR_TR1_Msk (0x1U << EXTI_FTSR_TR1_Pos) /*!< 0x00000002 */
+#define EXTI_FTSR_TR1 EXTI_FTSR_TR1_Msk /*!< Falling trigger event configuration bit of line 1 */
+#define EXTI_FTSR_TR2_Pos (2U)
+#define EXTI_FTSR_TR2_Msk (0x1U << EXTI_FTSR_TR2_Pos) /*!< 0x00000004 */
+#define EXTI_FTSR_TR2 EXTI_FTSR_TR2_Msk /*!< Falling trigger event configuration bit of line 2 */
+#define EXTI_FTSR_TR3_Pos (3U)
+#define EXTI_FTSR_TR3_Msk (0x1U << EXTI_FTSR_TR3_Pos) /*!< 0x00000008 */
+#define EXTI_FTSR_TR3 EXTI_FTSR_TR3_Msk /*!< Falling trigger event configuration bit of line 3 */
+#define EXTI_FTSR_TR4_Pos (4U)
+#define EXTI_FTSR_TR4_Msk (0x1U << EXTI_FTSR_TR4_Pos) /*!< 0x00000010 */
+#define EXTI_FTSR_TR4 EXTI_FTSR_TR4_Msk /*!< Falling trigger event configuration bit of line 4 */
+#define EXTI_FTSR_TR5_Pos (5U)
+#define EXTI_FTSR_TR5_Msk (0x1U << EXTI_FTSR_TR5_Pos) /*!< 0x00000020 */
+#define EXTI_FTSR_TR5 EXTI_FTSR_TR5_Msk /*!< Falling trigger event configuration bit of line 5 */
+#define EXTI_FTSR_TR6_Pos (6U)
+#define EXTI_FTSR_TR6_Msk (0x1U << EXTI_FTSR_TR6_Pos) /*!< 0x00000040 */
+#define EXTI_FTSR_TR6 EXTI_FTSR_TR6_Msk /*!< Falling trigger event configuration bit of line 6 */
+#define EXTI_FTSR_TR7_Pos (7U)
+#define EXTI_FTSR_TR7_Msk (0x1U << EXTI_FTSR_TR7_Pos) /*!< 0x00000080 */
+#define EXTI_FTSR_TR7 EXTI_FTSR_TR7_Msk /*!< Falling trigger event configuration bit of line 7 */
+#define EXTI_FTSR_TR8_Pos (8U)
+#define EXTI_FTSR_TR8_Msk (0x1U << EXTI_FTSR_TR8_Pos) /*!< 0x00000100 */
+#define EXTI_FTSR_TR8 EXTI_FTSR_TR8_Msk /*!< Falling trigger event configuration bit of line 8 */
+#define EXTI_FTSR_TR9_Pos (9U)
+#define EXTI_FTSR_TR9_Msk (0x1U << EXTI_FTSR_TR9_Pos) /*!< 0x00000200 */
+#define EXTI_FTSR_TR9 EXTI_FTSR_TR9_Msk /*!< Falling trigger event configuration bit of line 9 */
+#define EXTI_FTSR_TR10_Pos (10U)
+#define EXTI_FTSR_TR10_Msk (0x1U << EXTI_FTSR_TR10_Pos) /*!< 0x00000400 */
+#define EXTI_FTSR_TR10 EXTI_FTSR_TR10_Msk /*!< Falling trigger event configuration bit of line 10 */
+#define EXTI_FTSR_TR11_Pos (11U)
+#define EXTI_FTSR_TR11_Msk (0x1U << EXTI_FTSR_TR11_Pos) /*!< 0x00000800 */
+#define EXTI_FTSR_TR11 EXTI_FTSR_TR11_Msk /*!< Falling trigger event configuration bit of line 11 */
+#define EXTI_FTSR_TR12_Pos (12U)
+#define EXTI_FTSR_TR12_Msk (0x1U << EXTI_FTSR_TR12_Pos) /*!< 0x00001000 */
+#define EXTI_FTSR_TR12 EXTI_FTSR_TR12_Msk /*!< Falling trigger event configuration bit of line 12 */
+#define EXTI_FTSR_TR13_Pos (13U)
+#define EXTI_FTSR_TR13_Msk (0x1U << EXTI_FTSR_TR13_Pos) /*!< 0x00002000 */
+#define EXTI_FTSR_TR13 EXTI_FTSR_TR13_Msk /*!< Falling trigger event configuration bit of line 13 */
+#define EXTI_FTSR_TR14_Pos (14U)
+#define EXTI_FTSR_TR14_Msk (0x1U << EXTI_FTSR_TR14_Pos) /*!< 0x00004000 */
+#define EXTI_FTSR_TR14 EXTI_FTSR_TR14_Msk /*!< Falling trigger event configuration bit of line 14 */
+#define EXTI_FTSR_TR15_Pos (15U)
+#define EXTI_FTSR_TR15_Msk (0x1U << EXTI_FTSR_TR15_Pos) /*!< 0x00008000 */
+#define EXTI_FTSR_TR15 EXTI_FTSR_TR15_Msk /*!< Falling trigger event configuration bit of line 15 */
+#define EXTI_FTSR_TR16_Pos (16U)
+#define EXTI_FTSR_TR16_Msk (0x1U << EXTI_FTSR_TR16_Pos) /*!< 0x00010000 */
+#define EXTI_FTSR_TR16 EXTI_FTSR_TR16_Msk /*!< Falling trigger event configuration bit of line 16 */
+#define EXTI_FTSR_TR17_Pos (17U)
+#define EXTI_FTSR_TR17_Msk (0x1U << EXTI_FTSR_TR17_Pos) /*!< 0x00020000 */
+#define EXTI_FTSR_TR17 EXTI_FTSR_TR17_Msk /*!< Falling trigger event configuration bit of line 17 */
+#define EXTI_FTSR_TR18_Pos (18U)
+#define EXTI_FTSR_TR18_Msk (0x1U << EXTI_FTSR_TR18_Pos) /*!< 0x00040000 */
+#define EXTI_FTSR_TR18 EXTI_FTSR_TR18_Msk /*!< Falling trigger event configuration bit of line 18 */
+#define EXTI_FTSR_TR19_Pos (19U)
+#define EXTI_FTSR_TR19_Msk (0x1U << EXTI_FTSR_TR19_Pos) /*!< 0x00080000 */
+#define EXTI_FTSR_TR19 EXTI_FTSR_TR19_Msk /*!< Falling trigger event configuration bit of line 19 */
+
+/* References Defines */
+#define EXTI_FTSR_FT0 EXTI_FTSR_TR0
+#define EXTI_FTSR_FT1 EXTI_FTSR_TR1
+#define EXTI_FTSR_FT2 EXTI_FTSR_TR2
+#define EXTI_FTSR_FT3 EXTI_FTSR_TR3
+#define EXTI_FTSR_FT4 EXTI_FTSR_TR4
+#define EXTI_FTSR_FT5 EXTI_FTSR_TR5
+#define EXTI_FTSR_FT6 EXTI_FTSR_TR6
+#define EXTI_FTSR_FT7 EXTI_FTSR_TR7
+#define EXTI_FTSR_FT8 EXTI_FTSR_TR8
+#define EXTI_FTSR_FT9 EXTI_FTSR_TR9
+#define EXTI_FTSR_FT10 EXTI_FTSR_TR10
+#define EXTI_FTSR_FT11 EXTI_FTSR_TR11
+#define EXTI_FTSR_FT12 EXTI_FTSR_TR12
+#define EXTI_FTSR_FT13 EXTI_FTSR_TR13
+#define EXTI_FTSR_FT14 EXTI_FTSR_TR14
+#define EXTI_FTSR_FT15 EXTI_FTSR_TR15
+#define EXTI_FTSR_FT16 EXTI_FTSR_TR16
+#define EXTI_FTSR_FT17 EXTI_FTSR_TR17
+#define EXTI_FTSR_FT18 EXTI_FTSR_TR18
+#define EXTI_FTSR_FT19 EXTI_FTSR_TR19
+
+/****************** Bit definition for EXTI_SWIER register ******************/
+#define EXTI_SWIER_SWIER0_Pos (0U)
+#define EXTI_SWIER_SWIER0_Msk (0x1U << EXTI_SWIER_SWIER0_Pos) /*!< 0x00000001 */
+#define EXTI_SWIER_SWIER0 EXTI_SWIER_SWIER0_Msk /*!< Software Interrupt on line 0 */
+#define EXTI_SWIER_SWIER1_Pos (1U)
+#define EXTI_SWIER_SWIER1_Msk (0x1U << EXTI_SWIER_SWIER1_Pos) /*!< 0x00000002 */
+#define EXTI_SWIER_SWIER1 EXTI_SWIER_SWIER1_Msk /*!< Software Interrupt on line 1 */
+#define EXTI_SWIER_SWIER2_Pos (2U)
+#define EXTI_SWIER_SWIER2_Msk (0x1U << EXTI_SWIER_SWIER2_Pos) /*!< 0x00000004 */
+#define EXTI_SWIER_SWIER2 EXTI_SWIER_SWIER2_Msk /*!< Software Interrupt on line 2 */
+#define EXTI_SWIER_SWIER3_Pos (3U)
+#define EXTI_SWIER_SWIER3_Msk (0x1U << EXTI_SWIER_SWIER3_Pos) /*!< 0x00000008 */
+#define EXTI_SWIER_SWIER3 EXTI_SWIER_SWIER3_Msk /*!< Software Interrupt on line 3 */
+#define EXTI_SWIER_SWIER4_Pos (4U)
+#define EXTI_SWIER_SWIER4_Msk (0x1U << EXTI_SWIER_SWIER4_Pos) /*!< 0x00000010 */
+#define EXTI_SWIER_SWIER4 EXTI_SWIER_SWIER4_Msk /*!< Software Interrupt on line 4 */
+#define EXTI_SWIER_SWIER5_Pos (5U)
+#define EXTI_SWIER_SWIER5_Msk (0x1U << EXTI_SWIER_SWIER5_Pos) /*!< 0x00000020 */
+#define EXTI_SWIER_SWIER5 EXTI_SWIER_SWIER5_Msk /*!< Software Interrupt on line 5 */
+#define EXTI_SWIER_SWIER6_Pos (6U)
+#define EXTI_SWIER_SWIER6_Msk (0x1U << EXTI_SWIER_SWIER6_Pos) /*!< 0x00000040 */
+#define EXTI_SWIER_SWIER6 EXTI_SWIER_SWIER6_Msk /*!< Software Interrupt on line 6 */
+#define EXTI_SWIER_SWIER7_Pos (7U)
+#define EXTI_SWIER_SWIER7_Msk (0x1U << EXTI_SWIER_SWIER7_Pos) /*!< 0x00000080 */
+#define EXTI_SWIER_SWIER7 EXTI_SWIER_SWIER7_Msk /*!< Software Interrupt on line 7 */
+#define EXTI_SWIER_SWIER8_Pos (8U)
+#define EXTI_SWIER_SWIER8_Msk (0x1U << EXTI_SWIER_SWIER8_Pos) /*!< 0x00000100 */
+#define EXTI_SWIER_SWIER8 EXTI_SWIER_SWIER8_Msk /*!< Software Interrupt on line 8 */
+#define EXTI_SWIER_SWIER9_Pos (9U)
+#define EXTI_SWIER_SWIER9_Msk (0x1U << EXTI_SWIER_SWIER9_Pos) /*!< 0x00000200 */
+#define EXTI_SWIER_SWIER9 EXTI_SWIER_SWIER9_Msk /*!< Software Interrupt on line 9 */
+#define EXTI_SWIER_SWIER10_Pos (10U)
+#define EXTI_SWIER_SWIER10_Msk (0x1U << EXTI_SWIER_SWIER10_Pos) /*!< 0x00000400 */
+#define EXTI_SWIER_SWIER10 EXTI_SWIER_SWIER10_Msk /*!< Software Interrupt on line 10 */
+#define EXTI_SWIER_SWIER11_Pos (11U)
+#define EXTI_SWIER_SWIER11_Msk (0x1U << EXTI_SWIER_SWIER11_Pos) /*!< 0x00000800 */
+#define EXTI_SWIER_SWIER11 EXTI_SWIER_SWIER11_Msk /*!< Software Interrupt on line 11 */
+#define EXTI_SWIER_SWIER12_Pos (12U)
+#define EXTI_SWIER_SWIER12_Msk (0x1U << EXTI_SWIER_SWIER12_Pos) /*!< 0x00001000 */
+#define EXTI_SWIER_SWIER12 EXTI_SWIER_SWIER12_Msk /*!< Software Interrupt on line 12 */
+#define EXTI_SWIER_SWIER13_Pos (13U)
+#define EXTI_SWIER_SWIER13_Msk (0x1U << EXTI_SWIER_SWIER13_Pos) /*!< 0x00002000 */
+#define EXTI_SWIER_SWIER13 EXTI_SWIER_SWIER13_Msk /*!< Software Interrupt on line 13 */
+#define EXTI_SWIER_SWIER14_Pos (14U)
+#define EXTI_SWIER_SWIER14_Msk (0x1U << EXTI_SWIER_SWIER14_Pos) /*!< 0x00004000 */
+#define EXTI_SWIER_SWIER14 EXTI_SWIER_SWIER14_Msk /*!< Software Interrupt on line 14 */
+#define EXTI_SWIER_SWIER15_Pos (15U)
+#define EXTI_SWIER_SWIER15_Msk (0x1U << EXTI_SWIER_SWIER15_Pos) /*!< 0x00008000 */
+#define EXTI_SWIER_SWIER15 EXTI_SWIER_SWIER15_Msk /*!< Software Interrupt on line 15 */
+#define EXTI_SWIER_SWIER16_Pos (16U)
+#define EXTI_SWIER_SWIER16_Msk (0x1U << EXTI_SWIER_SWIER16_Pos) /*!< 0x00010000 */
+#define EXTI_SWIER_SWIER16 EXTI_SWIER_SWIER16_Msk /*!< Software Interrupt on line 16 */
+#define EXTI_SWIER_SWIER17_Pos (17U)
+#define EXTI_SWIER_SWIER17_Msk (0x1U << EXTI_SWIER_SWIER17_Pos) /*!< 0x00020000 */
+#define EXTI_SWIER_SWIER17 EXTI_SWIER_SWIER17_Msk /*!< Software Interrupt on line 17 */
+#define EXTI_SWIER_SWIER18_Pos (18U)
+#define EXTI_SWIER_SWIER18_Msk (0x1U << EXTI_SWIER_SWIER18_Pos) /*!< 0x00040000 */
+#define EXTI_SWIER_SWIER18 EXTI_SWIER_SWIER18_Msk /*!< Software Interrupt on line 18 */
+#define EXTI_SWIER_SWIER19_Pos (19U)
+#define EXTI_SWIER_SWIER19_Msk (0x1U << EXTI_SWIER_SWIER19_Pos) /*!< 0x00080000 */
+#define EXTI_SWIER_SWIER19 EXTI_SWIER_SWIER19_Msk /*!< Software Interrupt on line 19 */
+
+/* References Defines */
+#define EXTI_SWIER_SWI0 EXTI_SWIER_SWIER0
+#define EXTI_SWIER_SWI1 EXTI_SWIER_SWIER1
+#define EXTI_SWIER_SWI2 EXTI_SWIER_SWIER2
+#define EXTI_SWIER_SWI3 EXTI_SWIER_SWIER3
+#define EXTI_SWIER_SWI4 EXTI_SWIER_SWIER4
+#define EXTI_SWIER_SWI5 EXTI_SWIER_SWIER5
+#define EXTI_SWIER_SWI6 EXTI_SWIER_SWIER6
+#define EXTI_SWIER_SWI7 EXTI_SWIER_SWIER7
+#define EXTI_SWIER_SWI8 EXTI_SWIER_SWIER8
+#define EXTI_SWIER_SWI9 EXTI_SWIER_SWIER9
+#define EXTI_SWIER_SWI10 EXTI_SWIER_SWIER10
+#define EXTI_SWIER_SWI11 EXTI_SWIER_SWIER11
+#define EXTI_SWIER_SWI12 EXTI_SWIER_SWIER12
+#define EXTI_SWIER_SWI13 EXTI_SWIER_SWIER13
+#define EXTI_SWIER_SWI14 EXTI_SWIER_SWIER14
+#define EXTI_SWIER_SWI15 EXTI_SWIER_SWIER15
+#define EXTI_SWIER_SWI16 EXTI_SWIER_SWIER16
+#define EXTI_SWIER_SWI17 EXTI_SWIER_SWIER17
+#define EXTI_SWIER_SWI18 EXTI_SWIER_SWIER18
+#define EXTI_SWIER_SWI19 EXTI_SWIER_SWIER19
+
+/******************* Bit definition for EXTI_PR register ********************/
+#define EXTI_PR_PR0_Pos (0U)
+#define EXTI_PR_PR0_Msk (0x1U << EXTI_PR_PR0_Pos) /*!< 0x00000001 */
+#define EXTI_PR_PR0 EXTI_PR_PR0_Msk /*!< Pending bit for line 0 */
+#define EXTI_PR_PR1_Pos (1U)
+#define EXTI_PR_PR1_Msk (0x1U << EXTI_PR_PR1_Pos) /*!< 0x00000002 */
+#define EXTI_PR_PR1 EXTI_PR_PR1_Msk /*!< Pending bit for line 1 */
+#define EXTI_PR_PR2_Pos (2U)
+#define EXTI_PR_PR2_Msk (0x1U << EXTI_PR_PR2_Pos) /*!< 0x00000004 */
+#define EXTI_PR_PR2 EXTI_PR_PR2_Msk /*!< Pending bit for line 2 */
+#define EXTI_PR_PR3_Pos (3U)
+#define EXTI_PR_PR3_Msk (0x1U << EXTI_PR_PR3_Pos) /*!< 0x00000008 */
+#define EXTI_PR_PR3 EXTI_PR_PR3_Msk /*!< Pending bit for line 3 */
+#define EXTI_PR_PR4_Pos (4U)
+#define EXTI_PR_PR4_Msk (0x1U << EXTI_PR_PR4_Pos) /*!< 0x00000010 */
+#define EXTI_PR_PR4 EXTI_PR_PR4_Msk /*!< Pending bit for line 4 */
+#define EXTI_PR_PR5_Pos (5U)
+#define EXTI_PR_PR5_Msk (0x1U << EXTI_PR_PR5_Pos) /*!< 0x00000020 */
+#define EXTI_PR_PR5 EXTI_PR_PR5_Msk /*!< Pending bit for line 5 */
+#define EXTI_PR_PR6_Pos (6U)
+#define EXTI_PR_PR6_Msk (0x1U << EXTI_PR_PR6_Pos) /*!< 0x00000040 */
+#define EXTI_PR_PR6 EXTI_PR_PR6_Msk /*!< Pending bit for line 6 */
+#define EXTI_PR_PR7_Pos (7U)
+#define EXTI_PR_PR7_Msk (0x1U << EXTI_PR_PR7_Pos) /*!< 0x00000080 */
+#define EXTI_PR_PR7 EXTI_PR_PR7_Msk /*!< Pending bit for line 7 */
+#define EXTI_PR_PR8_Pos (8U)
+#define EXTI_PR_PR8_Msk (0x1U << EXTI_PR_PR8_Pos) /*!< 0x00000100 */
+#define EXTI_PR_PR8 EXTI_PR_PR8_Msk /*!< Pending bit for line 8 */
+#define EXTI_PR_PR9_Pos (9U)
+#define EXTI_PR_PR9_Msk (0x1U << EXTI_PR_PR9_Pos) /*!< 0x00000200 */
+#define EXTI_PR_PR9 EXTI_PR_PR9_Msk /*!< Pending bit for line 9 */
+#define EXTI_PR_PR10_Pos (10U)
+#define EXTI_PR_PR10_Msk (0x1U << EXTI_PR_PR10_Pos) /*!< 0x00000400 */
+#define EXTI_PR_PR10 EXTI_PR_PR10_Msk /*!< Pending bit for line 10 */
+#define EXTI_PR_PR11_Pos (11U)
+#define EXTI_PR_PR11_Msk (0x1U << EXTI_PR_PR11_Pos) /*!< 0x00000800 */
+#define EXTI_PR_PR11 EXTI_PR_PR11_Msk /*!< Pending bit for line 11 */
+#define EXTI_PR_PR12_Pos (12U)
+#define EXTI_PR_PR12_Msk (0x1U << EXTI_PR_PR12_Pos) /*!< 0x00001000 */
+#define EXTI_PR_PR12 EXTI_PR_PR12_Msk /*!< Pending bit for line 12 */
+#define EXTI_PR_PR13_Pos (13U)
+#define EXTI_PR_PR13_Msk (0x1U << EXTI_PR_PR13_Pos) /*!< 0x00002000 */
+#define EXTI_PR_PR13 EXTI_PR_PR13_Msk /*!< Pending bit for line 13 */
+#define EXTI_PR_PR14_Pos (14U)
+#define EXTI_PR_PR14_Msk (0x1U << EXTI_PR_PR14_Pos) /*!< 0x00004000 */
+#define EXTI_PR_PR14 EXTI_PR_PR14_Msk /*!< Pending bit for line 14 */
+#define EXTI_PR_PR15_Pos (15U)
+#define EXTI_PR_PR15_Msk (0x1U << EXTI_PR_PR15_Pos) /*!< 0x00008000 */
+#define EXTI_PR_PR15 EXTI_PR_PR15_Msk /*!< Pending bit for line 15 */
+#define EXTI_PR_PR16_Pos (16U)
+#define EXTI_PR_PR16_Msk (0x1U << EXTI_PR_PR16_Pos) /*!< 0x00010000 */
+#define EXTI_PR_PR16 EXTI_PR_PR16_Msk /*!< Pending bit for line 16 */
+#define EXTI_PR_PR17_Pos (17U)
+#define EXTI_PR_PR17_Msk (0x1U << EXTI_PR_PR17_Pos) /*!< 0x00020000 */
+#define EXTI_PR_PR17 EXTI_PR_PR17_Msk /*!< Pending bit for line 17 */
+#define EXTI_PR_PR18_Pos (18U)
+#define EXTI_PR_PR18_Msk (0x1U << EXTI_PR_PR18_Pos) /*!< 0x00040000 */
+#define EXTI_PR_PR18 EXTI_PR_PR18_Msk /*!< Pending bit for line 18 */
+#define EXTI_PR_PR19_Pos (19U)
+#define EXTI_PR_PR19_Msk (0x1U << EXTI_PR_PR19_Pos) /*!< 0x00080000 */
+#define EXTI_PR_PR19 EXTI_PR_PR19_Msk /*!< Pending bit for line 19 */
+
+/* References Defines */
+#define EXTI_PR_PIF0 EXTI_PR_PR0
+#define EXTI_PR_PIF1 EXTI_PR_PR1
+#define EXTI_PR_PIF2 EXTI_PR_PR2
+#define EXTI_PR_PIF3 EXTI_PR_PR3
+#define EXTI_PR_PIF4 EXTI_PR_PR4
+#define EXTI_PR_PIF5 EXTI_PR_PR5
+#define EXTI_PR_PIF6 EXTI_PR_PR6
+#define EXTI_PR_PIF7 EXTI_PR_PR7
+#define EXTI_PR_PIF8 EXTI_PR_PR8
+#define EXTI_PR_PIF9 EXTI_PR_PR9
+#define EXTI_PR_PIF10 EXTI_PR_PR10
+#define EXTI_PR_PIF11 EXTI_PR_PR11
+#define EXTI_PR_PIF12 EXTI_PR_PR12
+#define EXTI_PR_PIF13 EXTI_PR_PR13
+#define EXTI_PR_PIF14 EXTI_PR_PR14
+#define EXTI_PR_PIF15 EXTI_PR_PR15
+#define EXTI_PR_PIF16 EXTI_PR_PR16
+#define EXTI_PR_PIF17 EXTI_PR_PR17
+#define EXTI_PR_PIF18 EXTI_PR_PR18
+#define EXTI_PR_PIF19 EXTI_PR_PR19
+
+/******************************************************************************/
+/* */
+/* DMA Controller */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for DMA_ISR register ********************/
+#define DMA_ISR_GIF1_Pos (0U)
+#define DMA_ISR_GIF1_Msk (0x1U << DMA_ISR_GIF1_Pos) /*!< 0x00000001 */
+#define DMA_ISR_GIF1 DMA_ISR_GIF1_Msk /*!< Channel 1 Global interrupt flag */
+#define DMA_ISR_TCIF1_Pos (1U)
+#define DMA_ISR_TCIF1_Msk (0x1U << DMA_ISR_TCIF1_Pos) /*!< 0x00000002 */
+#define DMA_ISR_TCIF1 DMA_ISR_TCIF1_Msk /*!< Channel 1 Transfer Complete flag */
+#define DMA_ISR_HTIF1_Pos (2U)
+#define DMA_ISR_HTIF1_Msk (0x1U << DMA_ISR_HTIF1_Pos) /*!< 0x00000004 */
+#define DMA_ISR_HTIF1 DMA_ISR_HTIF1_Msk /*!< Channel 1 Half Transfer flag */
+#define DMA_ISR_TEIF1_Pos (3U)
+#define DMA_ISR_TEIF1_Msk (0x1U << DMA_ISR_TEIF1_Pos) /*!< 0x00000008 */
+#define DMA_ISR_TEIF1 DMA_ISR_TEIF1_Msk /*!< Channel 1 Transfer Error flag */
+#define DMA_ISR_GIF2_Pos (4U)
+#define DMA_ISR_GIF2_Msk (0x1U << DMA_ISR_GIF2_Pos) /*!< 0x00000010 */
+#define DMA_ISR_GIF2 DMA_ISR_GIF2_Msk /*!< Channel 2 Global interrupt flag */
+#define DMA_ISR_TCIF2_Pos (5U)
+#define DMA_ISR_TCIF2_Msk (0x1U << DMA_ISR_TCIF2_Pos) /*!< 0x00000020 */
+#define DMA_ISR_TCIF2 DMA_ISR_TCIF2_Msk /*!< Channel 2 Transfer Complete flag */
+#define DMA_ISR_HTIF2_Pos (6U)
+#define DMA_ISR_HTIF2_Msk (0x1U << DMA_ISR_HTIF2_Pos) /*!< 0x00000040 */
+#define DMA_ISR_HTIF2 DMA_ISR_HTIF2_Msk /*!< Channel 2 Half Transfer flag */
+#define DMA_ISR_TEIF2_Pos (7U)
+#define DMA_ISR_TEIF2_Msk (0x1U << DMA_ISR_TEIF2_Pos) /*!< 0x00000080 */
+#define DMA_ISR_TEIF2 DMA_ISR_TEIF2_Msk /*!< Channel 2 Transfer Error flag */
+#define DMA_ISR_GIF3_Pos (8U)
+#define DMA_ISR_GIF3_Msk (0x1U << DMA_ISR_GIF3_Pos) /*!< 0x00000100 */
+#define DMA_ISR_GIF3 DMA_ISR_GIF3_Msk /*!< Channel 3 Global interrupt flag */
+#define DMA_ISR_TCIF3_Pos (9U)
+#define DMA_ISR_TCIF3_Msk (0x1U << DMA_ISR_TCIF3_Pos) /*!< 0x00000200 */
+#define DMA_ISR_TCIF3 DMA_ISR_TCIF3_Msk /*!< Channel 3 Transfer Complete flag */
+#define DMA_ISR_HTIF3_Pos (10U)
+#define DMA_ISR_HTIF3_Msk (0x1U << DMA_ISR_HTIF3_Pos) /*!< 0x00000400 */
+#define DMA_ISR_HTIF3 DMA_ISR_HTIF3_Msk /*!< Channel 3 Half Transfer flag */
+#define DMA_ISR_TEIF3_Pos (11U)
+#define DMA_ISR_TEIF3_Msk (0x1U << DMA_ISR_TEIF3_Pos) /*!< 0x00000800 */
+#define DMA_ISR_TEIF3 DMA_ISR_TEIF3_Msk /*!< Channel 3 Transfer Error flag */
+#define DMA_ISR_GIF4_Pos (12U)
+#define DMA_ISR_GIF4_Msk (0x1U << DMA_ISR_GIF4_Pos) /*!< 0x00001000 */
+#define DMA_ISR_GIF4 DMA_ISR_GIF4_Msk /*!< Channel 4 Global interrupt flag */
+#define DMA_ISR_TCIF4_Pos (13U)
+#define DMA_ISR_TCIF4_Msk (0x1U << DMA_ISR_TCIF4_Pos) /*!< 0x00002000 */
+#define DMA_ISR_TCIF4 DMA_ISR_TCIF4_Msk /*!< Channel 4 Transfer Complete flag */
+#define DMA_ISR_HTIF4_Pos (14U)
+#define DMA_ISR_HTIF4_Msk (0x1U << DMA_ISR_HTIF4_Pos) /*!< 0x00004000 */
+#define DMA_ISR_HTIF4 DMA_ISR_HTIF4_Msk /*!< Channel 4 Half Transfer flag */
+#define DMA_ISR_TEIF4_Pos (15U)
+#define DMA_ISR_TEIF4_Msk (0x1U << DMA_ISR_TEIF4_Pos) /*!< 0x00008000 */
+#define DMA_ISR_TEIF4 DMA_ISR_TEIF4_Msk /*!< Channel 4 Transfer Error flag */
+#define DMA_ISR_GIF5_Pos (16U)
+#define DMA_ISR_GIF5_Msk (0x1U << DMA_ISR_GIF5_Pos) /*!< 0x00010000 */
+#define DMA_ISR_GIF5 DMA_ISR_GIF5_Msk /*!< Channel 5 Global interrupt flag */
+#define DMA_ISR_TCIF5_Pos (17U)
+#define DMA_ISR_TCIF5_Msk (0x1U << DMA_ISR_TCIF5_Pos) /*!< 0x00020000 */
+#define DMA_ISR_TCIF5 DMA_ISR_TCIF5_Msk /*!< Channel 5 Transfer Complete flag */
+#define DMA_ISR_HTIF5_Pos (18U)
+#define DMA_ISR_HTIF5_Msk (0x1U << DMA_ISR_HTIF5_Pos) /*!< 0x00040000 */
+#define DMA_ISR_HTIF5 DMA_ISR_HTIF5_Msk /*!< Channel 5 Half Transfer flag */
+#define DMA_ISR_TEIF5_Pos (19U)
+#define DMA_ISR_TEIF5_Msk (0x1U << DMA_ISR_TEIF5_Pos) /*!< 0x00080000 */
+#define DMA_ISR_TEIF5 DMA_ISR_TEIF5_Msk /*!< Channel 5 Transfer Error flag */
+#define DMA_ISR_GIF6_Pos (20U)
+#define DMA_ISR_GIF6_Msk (0x1U << DMA_ISR_GIF6_Pos) /*!< 0x00100000 */
+#define DMA_ISR_GIF6 DMA_ISR_GIF6_Msk /*!< Channel 6 Global interrupt flag */
+#define DMA_ISR_TCIF6_Pos (21U)
+#define DMA_ISR_TCIF6_Msk (0x1U << DMA_ISR_TCIF6_Pos) /*!< 0x00200000 */
+#define DMA_ISR_TCIF6 DMA_ISR_TCIF6_Msk /*!< Channel 6 Transfer Complete flag */
+#define DMA_ISR_HTIF6_Pos (22U)
+#define DMA_ISR_HTIF6_Msk (0x1U << DMA_ISR_HTIF6_Pos) /*!< 0x00400000 */
+#define DMA_ISR_HTIF6 DMA_ISR_HTIF6_Msk /*!< Channel 6 Half Transfer flag */
+#define DMA_ISR_TEIF6_Pos (23U)
+#define DMA_ISR_TEIF6_Msk (0x1U << DMA_ISR_TEIF6_Pos) /*!< 0x00800000 */
+#define DMA_ISR_TEIF6 DMA_ISR_TEIF6_Msk /*!< Channel 6 Transfer Error flag */
+#define DMA_ISR_GIF7_Pos (24U)
+#define DMA_ISR_GIF7_Msk (0x1U << DMA_ISR_GIF7_Pos) /*!< 0x01000000 */
+#define DMA_ISR_GIF7 DMA_ISR_GIF7_Msk /*!< Channel 7 Global interrupt flag */
+#define DMA_ISR_TCIF7_Pos (25U)
+#define DMA_ISR_TCIF7_Msk (0x1U << DMA_ISR_TCIF7_Pos) /*!< 0x02000000 */
+#define DMA_ISR_TCIF7 DMA_ISR_TCIF7_Msk /*!< Channel 7 Transfer Complete flag */
+#define DMA_ISR_HTIF7_Pos (26U)
+#define DMA_ISR_HTIF7_Msk (0x1U << DMA_ISR_HTIF7_Pos) /*!< 0x04000000 */
+#define DMA_ISR_HTIF7 DMA_ISR_HTIF7_Msk /*!< Channel 7 Half Transfer flag */
+#define DMA_ISR_TEIF7_Pos (27U)
+#define DMA_ISR_TEIF7_Msk (0x1U << DMA_ISR_TEIF7_Pos) /*!< 0x08000000 */
+#define DMA_ISR_TEIF7 DMA_ISR_TEIF7_Msk /*!< Channel 7 Transfer Error flag */
+
+/******************* Bit definition for DMA_IFCR register *******************/
+#define DMA_IFCR_CGIF1_Pos (0U)
+#define DMA_IFCR_CGIF1_Msk (0x1U << DMA_IFCR_CGIF1_Pos) /*!< 0x00000001 */
+#define DMA_IFCR_CGIF1 DMA_IFCR_CGIF1_Msk /*!< Channel 1 Global interrupt clear */
+#define DMA_IFCR_CTCIF1_Pos (1U)
+#define DMA_IFCR_CTCIF1_Msk (0x1U << DMA_IFCR_CTCIF1_Pos) /*!< 0x00000002 */
+#define DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF1_Msk /*!< Channel 1 Transfer Complete clear */
+#define DMA_IFCR_CHTIF1_Pos (2U)
+#define DMA_IFCR_CHTIF1_Msk (0x1U << DMA_IFCR_CHTIF1_Pos) /*!< 0x00000004 */
+#define DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF1_Msk /*!< Channel 1 Half Transfer clear */
+#define DMA_IFCR_CTEIF1_Pos (3U)
+#define DMA_IFCR_CTEIF1_Msk (0x1U << DMA_IFCR_CTEIF1_Pos) /*!< 0x00000008 */
+#define DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF1_Msk /*!< Channel 1 Transfer Error clear */
+#define DMA_IFCR_CGIF2_Pos (4U)
+#define DMA_IFCR_CGIF2_Msk (0x1U << DMA_IFCR_CGIF2_Pos) /*!< 0x00000010 */
+#define DMA_IFCR_CGIF2 DMA_IFCR_CGIF2_Msk /*!< Channel 2 Global interrupt clear */
+#define DMA_IFCR_CTCIF2_Pos (5U)
+#define DMA_IFCR_CTCIF2_Msk (0x1U << DMA_IFCR_CTCIF2_Pos) /*!< 0x00000020 */
+#define DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF2_Msk /*!< Channel 2 Transfer Complete clear */
+#define DMA_IFCR_CHTIF2_Pos (6U)
+#define DMA_IFCR_CHTIF2_Msk (0x1U << DMA_IFCR_CHTIF2_Pos) /*!< 0x00000040 */
+#define DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF2_Msk /*!< Channel 2 Half Transfer clear */
+#define DMA_IFCR_CTEIF2_Pos (7U)
+#define DMA_IFCR_CTEIF2_Msk (0x1U << DMA_IFCR_CTEIF2_Pos) /*!< 0x00000080 */
+#define DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF2_Msk /*!< Channel 2 Transfer Error clear */
+#define DMA_IFCR_CGIF3_Pos (8U)
+#define DMA_IFCR_CGIF3_Msk (0x1U << DMA_IFCR_CGIF3_Pos) /*!< 0x00000100 */
+#define DMA_IFCR_CGIF3 DMA_IFCR_CGIF3_Msk /*!< Channel 3 Global interrupt clear */
+#define DMA_IFCR_CTCIF3_Pos (9U)
+#define DMA_IFCR_CTCIF3_Msk (0x1U << DMA_IFCR_CTCIF3_Pos) /*!< 0x00000200 */
+#define DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF3_Msk /*!< Channel 3 Transfer Complete clear */
+#define DMA_IFCR_CHTIF3_Pos (10U)
+#define DMA_IFCR_CHTIF3_Msk (0x1U << DMA_IFCR_CHTIF3_Pos) /*!< 0x00000400 */
+#define DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF3_Msk /*!< Channel 3 Half Transfer clear */
+#define DMA_IFCR_CTEIF3_Pos (11U)
+#define DMA_IFCR_CTEIF3_Msk (0x1U << DMA_IFCR_CTEIF3_Pos) /*!< 0x00000800 */
+#define DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF3_Msk /*!< Channel 3 Transfer Error clear */
+#define DMA_IFCR_CGIF4_Pos (12U)
+#define DMA_IFCR_CGIF4_Msk (0x1U << DMA_IFCR_CGIF4_Pos) /*!< 0x00001000 */
+#define DMA_IFCR_CGIF4 DMA_IFCR_CGIF4_Msk /*!< Channel 4 Global interrupt clear */
+#define DMA_IFCR_CTCIF4_Pos (13U)
+#define DMA_IFCR_CTCIF4_Msk (0x1U << DMA_IFCR_CTCIF4_Pos) /*!< 0x00002000 */
+#define DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF4_Msk /*!< Channel 4 Transfer Complete clear */
+#define DMA_IFCR_CHTIF4_Pos (14U)
+#define DMA_IFCR_CHTIF4_Msk (0x1U << DMA_IFCR_CHTIF4_Pos) /*!< 0x00004000 */
+#define DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF4_Msk /*!< Channel 4 Half Transfer clear */
+#define DMA_IFCR_CTEIF4_Pos (15U)
+#define DMA_IFCR_CTEIF4_Msk (0x1U << DMA_IFCR_CTEIF4_Pos) /*!< 0x00008000 */
+#define DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF4_Msk /*!< Channel 4 Transfer Error clear */
+#define DMA_IFCR_CGIF5_Pos (16U)
+#define DMA_IFCR_CGIF5_Msk (0x1U << DMA_IFCR_CGIF5_Pos) /*!< 0x00010000 */
+#define DMA_IFCR_CGIF5 DMA_IFCR_CGIF5_Msk /*!< Channel 5 Global interrupt clear */
+#define DMA_IFCR_CTCIF5_Pos (17U)
+#define DMA_IFCR_CTCIF5_Msk (0x1U << DMA_IFCR_CTCIF5_Pos) /*!< 0x00020000 */
+#define DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF5_Msk /*!< Channel 5 Transfer Complete clear */
+#define DMA_IFCR_CHTIF5_Pos (18U)
+#define DMA_IFCR_CHTIF5_Msk (0x1U << DMA_IFCR_CHTIF5_Pos) /*!< 0x00040000 */
+#define DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5_Msk /*!< Channel 5 Half Transfer clear */
+#define DMA_IFCR_CTEIF5_Pos (19U)
+#define DMA_IFCR_CTEIF5_Msk (0x1U << DMA_IFCR_CTEIF5_Pos) /*!< 0x00080000 */
+#define DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF5_Msk /*!< Channel 5 Transfer Error clear */
+#define DMA_IFCR_CGIF6_Pos (20U)
+#define DMA_IFCR_CGIF6_Msk (0x1U << DMA_IFCR_CGIF6_Pos) /*!< 0x00100000 */
+#define DMA_IFCR_CGIF6 DMA_IFCR_CGIF6_Msk /*!< Channel 6 Global interrupt clear */
+#define DMA_IFCR_CTCIF6_Pos (21U)
+#define DMA_IFCR_CTCIF6_Msk (0x1U << DMA_IFCR_CTCIF6_Pos) /*!< 0x00200000 */
+#define DMA_IFCR_CTCIF6 DMA_IFCR_CTCIF6_Msk /*!< Channel 6 Transfer Complete clear */
+#define DMA_IFCR_CHTIF6_Pos (22U)
+#define DMA_IFCR_CHTIF6_Msk (0x1U << DMA_IFCR_CHTIF6_Pos) /*!< 0x00400000 */
+#define DMA_IFCR_CHTIF6 DMA_IFCR_CHTIF6_Msk /*!< Channel 6 Half Transfer clear */
+#define DMA_IFCR_CTEIF6_Pos (23U)
+#define DMA_IFCR_CTEIF6_Msk (0x1U << DMA_IFCR_CTEIF6_Pos) /*!< 0x00800000 */
+#define DMA_IFCR_CTEIF6 DMA_IFCR_CTEIF6_Msk /*!< Channel 6 Transfer Error clear */
+#define DMA_IFCR_CGIF7_Pos (24U)
+#define DMA_IFCR_CGIF7_Msk (0x1U << DMA_IFCR_CGIF7_Pos) /*!< 0x01000000 */
+#define DMA_IFCR_CGIF7 DMA_IFCR_CGIF7_Msk /*!< Channel 7 Global interrupt clear */
+#define DMA_IFCR_CTCIF7_Pos (25U)
+#define DMA_IFCR_CTCIF7_Msk (0x1U << DMA_IFCR_CTCIF7_Pos) /*!< 0x02000000 */
+#define DMA_IFCR_CTCIF7 DMA_IFCR_CTCIF7_Msk /*!< Channel 7 Transfer Complete clear */
+#define DMA_IFCR_CHTIF7_Pos (26U)
+#define DMA_IFCR_CHTIF7_Msk (0x1U << DMA_IFCR_CHTIF7_Pos) /*!< 0x04000000 */
+#define DMA_IFCR_CHTIF7 DMA_IFCR_CHTIF7_Msk /*!< Channel 7 Half Transfer clear */
+#define DMA_IFCR_CTEIF7_Pos (27U)
+#define DMA_IFCR_CTEIF7_Msk (0x1U << DMA_IFCR_CTEIF7_Pos) /*!< 0x08000000 */
+#define DMA_IFCR_CTEIF7 DMA_IFCR_CTEIF7_Msk /*!< Channel 7 Transfer Error clear */
+
+/******************* Bit definition for DMA_CCR register *******************/
+#define DMA_CCR_EN_Pos (0U)
+#define DMA_CCR_EN_Msk (0x1U << DMA_CCR_EN_Pos) /*!< 0x00000001 */
+#define DMA_CCR_EN DMA_CCR_EN_Msk /*!< Channel enable */
+#define DMA_CCR_TCIE_Pos (1U)
+#define DMA_CCR_TCIE_Msk (0x1U << DMA_CCR_TCIE_Pos) /*!< 0x00000002 */
+#define DMA_CCR_TCIE DMA_CCR_TCIE_Msk /*!< Transfer complete interrupt enable */
+#define DMA_CCR_HTIE_Pos (2U)
+#define DMA_CCR_HTIE_Msk (0x1U << DMA_CCR_HTIE_Pos) /*!< 0x00000004 */
+#define DMA_CCR_HTIE DMA_CCR_HTIE_Msk /*!< Half Transfer interrupt enable */
+#define DMA_CCR_TEIE_Pos (3U)
+#define DMA_CCR_TEIE_Msk (0x1U << DMA_CCR_TEIE_Pos) /*!< 0x00000008 */
+#define DMA_CCR_TEIE DMA_CCR_TEIE_Msk /*!< Transfer error interrupt enable */
+#define DMA_CCR_DIR_Pos (4U)
+#define DMA_CCR_DIR_Msk (0x1U << DMA_CCR_DIR_Pos) /*!< 0x00000010 */
+#define DMA_CCR_DIR DMA_CCR_DIR_Msk /*!< Data transfer direction */
+#define DMA_CCR_CIRC_Pos (5U)
+#define DMA_CCR_CIRC_Msk (0x1U << DMA_CCR_CIRC_Pos) /*!< 0x00000020 */
+#define DMA_CCR_CIRC DMA_CCR_CIRC_Msk /*!< Circular mode */
+#define DMA_CCR_PINC_Pos (6U)
+#define DMA_CCR_PINC_Msk (0x1U << DMA_CCR_PINC_Pos) /*!< 0x00000040 */
+#define DMA_CCR_PINC DMA_CCR_PINC_Msk /*!< Peripheral increment mode */
+#define DMA_CCR_MINC_Pos (7U)
+#define DMA_CCR_MINC_Msk (0x1U << DMA_CCR_MINC_Pos) /*!< 0x00000080 */
+#define DMA_CCR_MINC DMA_CCR_MINC_Msk /*!< Memory increment mode */
+
+#define DMA_CCR_PSIZE_Pos (8U)
+#define DMA_CCR_PSIZE_Msk (0x3U << DMA_CCR_PSIZE_Pos) /*!< 0x00000300 */
+#define DMA_CCR_PSIZE DMA_CCR_PSIZE_Msk /*!< PSIZE[1:0] bits (Peripheral size) */
+#define DMA_CCR_PSIZE_0 (0x1U << DMA_CCR_PSIZE_Pos) /*!< 0x00000100 */
+#define DMA_CCR_PSIZE_1 (0x2U << DMA_CCR_PSIZE_Pos) /*!< 0x00000200 */
+
+#define DMA_CCR_MSIZE_Pos (10U)
+#define DMA_CCR_MSIZE_Msk (0x3U << DMA_CCR_MSIZE_Pos) /*!< 0x00000C00 */
+#define DMA_CCR_MSIZE DMA_CCR_MSIZE_Msk /*!< MSIZE[1:0] bits (Memory size) */
+#define DMA_CCR_MSIZE_0 (0x1U << DMA_CCR_MSIZE_Pos) /*!< 0x00000400 */
+#define DMA_CCR_MSIZE_1 (0x2U << DMA_CCR_MSIZE_Pos) /*!< 0x00000800 */
+
+#define DMA_CCR_PL_Pos (12U)
+#define DMA_CCR_PL_Msk (0x3U << DMA_CCR_PL_Pos) /*!< 0x00003000 */
+#define DMA_CCR_PL DMA_CCR_PL_Msk /*!< PL[1:0] bits(Channel Priority level) */
+#define DMA_CCR_PL_0 (0x1U << DMA_CCR_PL_Pos) /*!< 0x00001000 */
+#define DMA_CCR_PL_1 (0x2U << DMA_CCR_PL_Pos) /*!< 0x00002000 */
+
+#define DMA_CCR_MEM2MEM_Pos (14U)
+#define DMA_CCR_MEM2MEM_Msk (0x1U << DMA_CCR_MEM2MEM_Pos) /*!< 0x00004000 */
+#define DMA_CCR_MEM2MEM DMA_CCR_MEM2MEM_Msk /*!< Memory to memory mode */
+
+/****************** Bit definition for DMA_CNDTR register ******************/
+#define DMA_CNDTR_NDT_Pos (0U)
+#define DMA_CNDTR_NDT_Msk (0xFFFFU << DMA_CNDTR_NDT_Pos) /*!< 0x0000FFFF */
+#define DMA_CNDTR_NDT DMA_CNDTR_NDT_Msk /*!< Number of data to Transfer */
+
+/****************** Bit definition for DMA_CPAR register *******************/
+#define DMA_CPAR_PA_Pos (0U)
+#define DMA_CPAR_PA_Msk (0xFFFFFFFFU << DMA_CPAR_PA_Pos) /*!< 0xFFFFFFFF */
+#define DMA_CPAR_PA DMA_CPAR_PA_Msk /*!< Peripheral Address */
+
+/****************** Bit definition for DMA_CMAR register *******************/
+#define DMA_CMAR_MA_Pos (0U)
+#define DMA_CMAR_MA_Msk (0xFFFFFFFFU << DMA_CMAR_MA_Pos) /*!< 0xFFFFFFFF */
+#define DMA_CMAR_MA DMA_CMAR_MA_Msk /*!< Memory Address */
+
+/******************************************************************************/
+/* */
+/* Analog to Digital Converter (ADC) */
+/* */
+/******************************************************************************/
+
+/*
+ * @brief Specific device feature definitions (not present on all devices in the STM32F1 family)
+ */
+#define ADC_MULTIMODE_SUPPORT /*!< ADC feature available only on specific devices: multimode available on devices with several ADC instances */
+
+/******************** Bit definition for ADC_SR register ********************/
+#define ADC_SR_AWD_Pos (0U)
+#define ADC_SR_AWD_Msk (0x1U << ADC_SR_AWD_Pos) /*!< 0x00000001 */
+#define ADC_SR_AWD ADC_SR_AWD_Msk /*!< ADC analog watchdog 1 flag */
+#define ADC_SR_EOS_Pos (1U)
+#define ADC_SR_EOS_Msk (0x1U << ADC_SR_EOS_Pos) /*!< 0x00000002 */
+#define ADC_SR_EOS ADC_SR_EOS_Msk /*!< ADC group regular end of sequence conversions flag */
+#define ADC_SR_JEOS_Pos (2U)
+#define ADC_SR_JEOS_Msk (0x1U << ADC_SR_JEOS_Pos) /*!< 0x00000004 */
+#define ADC_SR_JEOS ADC_SR_JEOS_Msk /*!< ADC group injected end of sequence conversions flag */
+#define ADC_SR_JSTRT_Pos (3U)
+#define ADC_SR_JSTRT_Msk (0x1U << ADC_SR_JSTRT_Pos) /*!< 0x00000008 */
+#define ADC_SR_JSTRT ADC_SR_JSTRT_Msk /*!< ADC group injected conversion start flag */
+#define ADC_SR_STRT_Pos (4U)
+#define ADC_SR_STRT_Msk (0x1U << ADC_SR_STRT_Pos) /*!< 0x00000010 */
+#define ADC_SR_STRT ADC_SR_STRT_Msk /*!< ADC group regular conversion start flag */
+
+/* Legacy defines */
+#define ADC_SR_EOC (ADC_SR_EOS)
+#define ADC_SR_JEOC (ADC_SR_JEOS)
+
+/******************* Bit definition for ADC_CR1 register ********************/
+#define ADC_CR1_AWDCH_Pos (0U)
+#define ADC_CR1_AWDCH_Msk (0x1FU << ADC_CR1_AWDCH_Pos) /*!< 0x0000001F */
+#define ADC_CR1_AWDCH ADC_CR1_AWDCH_Msk /*!< ADC analog watchdog 1 monitored channel selection */
+#define ADC_CR1_AWDCH_0 (0x01U << ADC_CR1_AWDCH_Pos) /*!< 0x00000001 */
+#define ADC_CR1_AWDCH_1 (0x02U << ADC_CR1_AWDCH_Pos) /*!< 0x00000002 */
+#define ADC_CR1_AWDCH_2 (0x04U << ADC_CR1_AWDCH_Pos) /*!< 0x00000004 */
+#define ADC_CR1_AWDCH_3 (0x08U << ADC_CR1_AWDCH_Pos) /*!< 0x00000008 */
+#define ADC_CR1_AWDCH_4 (0x10U << ADC_CR1_AWDCH_Pos) /*!< 0x00000010 */
+
+#define ADC_CR1_EOSIE_Pos (5U)
+#define ADC_CR1_EOSIE_Msk (0x1U << ADC_CR1_EOSIE_Pos) /*!< 0x00000020 */
+#define ADC_CR1_EOSIE ADC_CR1_EOSIE_Msk /*!< ADC group regular end of sequence conversions interrupt */
+#define ADC_CR1_AWDIE_Pos (6U)
+#define ADC_CR1_AWDIE_Msk (0x1U << ADC_CR1_AWDIE_Pos) /*!< 0x00000040 */
+#define ADC_CR1_AWDIE ADC_CR1_AWDIE_Msk /*!< ADC analog watchdog 1 interrupt */
+#define ADC_CR1_JEOSIE_Pos (7U)
+#define ADC_CR1_JEOSIE_Msk (0x1U << ADC_CR1_JEOSIE_Pos) /*!< 0x00000080 */
+#define ADC_CR1_JEOSIE ADC_CR1_JEOSIE_Msk /*!< ADC group injected end of sequence conversions interrupt */
+#define ADC_CR1_SCAN_Pos (8U)
+#define ADC_CR1_SCAN_Msk (0x1U << ADC_CR1_SCAN_Pos) /*!< 0x00000100 */
+#define ADC_CR1_SCAN ADC_CR1_SCAN_Msk /*!< ADC scan mode */
+#define ADC_CR1_AWDSGL_Pos (9U)
+#define ADC_CR1_AWDSGL_Msk (0x1U << ADC_CR1_AWDSGL_Pos) /*!< 0x00000200 */
+#define ADC_CR1_AWDSGL ADC_CR1_AWDSGL_Msk /*!< ADC analog watchdog 1 monitoring a single channel or all channels */
+#define ADC_CR1_JAUTO_Pos (10U)
+#define ADC_CR1_JAUTO_Msk (0x1U << ADC_CR1_JAUTO_Pos) /*!< 0x00000400 */
+#define ADC_CR1_JAUTO ADC_CR1_JAUTO_Msk /*!< ADC group injected automatic trigger mode */
+#define ADC_CR1_DISCEN_Pos (11U)
+#define ADC_CR1_DISCEN_Msk (0x1U << ADC_CR1_DISCEN_Pos) /*!< 0x00000800 */
+#define ADC_CR1_DISCEN ADC_CR1_DISCEN_Msk /*!< ADC group regular sequencer discontinuous mode */
+#define ADC_CR1_JDISCEN_Pos (12U)
+#define ADC_CR1_JDISCEN_Msk (0x1U << ADC_CR1_JDISCEN_Pos) /*!< 0x00001000 */
+#define ADC_CR1_JDISCEN ADC_CR1_JDISCEN_Msk /*!< ADC group injected sequencer discontinuous mode */
+
+#define ADC_CR1_DISCNUM_Pos (13U)
+#define ADC_CR1_DISCNUM_Msk (0x7U << ADC_CR1_DISCNUM_Pos) /*!< 0x0000E000 */
+#define ADC_CR1_DISCNUM ADC_CR1_DISCNUM_Msk /*!< ADC group regular sequencer discontinuous number of ranks */
+#define ADC_CR1_DISCNUM_0 (0x1U << ADC_CR1_DISCNUM_Pos) /*!< 0x00002000 */
+#define ADC_CR1_DISCNUM_1 (0x2U << ADC_CR1_DISCNUM_Pos) /*!< 0x00004000 */
+#define ADC_CR1_DISCNUM_2 (0x4U << ADC_CR1_DISCNUM_Pos) /*!< 0x00008000 */
+
+#define ADC_CR1_DUALMOD_Pos (16U)
+#define ADC_CR1_DUALMOD_Msk (0xFU << ADC_CR1_DUALMOD_Pos) /*!< 0x000F0000 */
+#define ADC_CR1_DUALMOD ADC_CR1_DUALMOD_Msk /*!< ADC multimode mode selection */
+#define ADC_CR1_DUALMOD_0 (0x1U << ADC_CR1_DUALMOD_Pos) /*!< 0x00010000 */
+#define ADC_CR1_DUALMOD_1 (0x2U << ADC_CR1_DUALMOD_Pos) /*!< 0x00020000 */
+#define ADC_CR1_DUALMOD_2 (0x4U << ADC_CR1_DUALMOD_Pos) /*!< 0x00040000 */
+#define ADC_CR1_DUALMOD_3 (0x8U << ADC_CR1_DUALMOD_Pos) /*!< 0x00080000 */
+
+#define ADC_CR1_JAWDEN_Pos (22U)
+#define ADC_CR1_JAWDEN_Msk (0x1U << ADC_CR1_JAWDEN_Pos) /*!< 0x00400000 */
+#define ADC_CR1_JAWDEN ADC_CR1_JAWDEN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group injected */
+#define ADC_CR1_AWDEN_Pos (23U)
+#define ADC_CR1_AWDEN_Msk (0x1U << ADC_CR1_AWDEN_Pos) /*!< 0x00800000 */
+#define ADC_CR1_AWDEN ADC_CR1_AWDEN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group regular */
+
+/* Legacy defines */
+#define ADC_CR1_EOCIE (ADC_CR1_EOSIE)
+#define ADC_CR1_JEOCIE (ADC_CR1_JEOSIE)
+
+/******************* Bit definition for ADC_CR2 register ********************/
+#define ADC_CR2_ADON_Pos (0U)
+#define ADC_CR2_ADON_Msk (0x1U << ADC_CR2_ADON_Pos) /*!< 0x00000001 */
+#define ADC_CR2_ADON ADC_CR2_ADON_Msk /*!< ADC enable */
+#define ADC_CR2_CONT_Pos (1U)
+#define ADC_CR2_CONT_Msk (0x1U << ADC_CR2_CONT_Pos) /*!< 0x00000002 */
+#define ADC_CR2_CONT ADC_CR2_CONT_Msk /*!< ADC group regular continuous conversion mode */
+#define ADC_CR2_CAL_Pos (2U)
+#define ADC_CR2_CAL_Msk (0x1U << ADC_CR2_CAL_Pos) /*!< 0x00000004 */
+#define ADC_CR2_CAL ADC_CR2_CAL_Msk /*!< ADC calibration start */
+#define ADC_CR2_RSTCAL_Pos (3U)
+#define ADC_CR2_RSTCAL_Msk (0x1U << ADC_CR2_RSTCAL_Pos) /*!< 0x00000008 */
+#define ADC_CR2_RSTCAL ADC_CR2_RSTCAL_Msk /*!< ADC calibration reset */
+#define ADC_CR2_DMA_Pos (8U)
+#define ADC_CR2_DMA_Msk (0x1U << ADC_CR2_DMA_Pos) /*!< 0x00000100 */
+#define ADC_CR2_DMA ADC_CR2_DMA_Msk /*!< ADC DMA transfer enable */
+#define ADC_CR2_ALIGN_Pos (11U)
+#define ADC_CR2_ALIGN_Msk (0x1U << ADC_CR2_ALIGN_Pos) /*!< 0x00000800 */
+#define ADC_CR2_ALIGN ADC_CR2_ALIGN_Msk /*!< ADC data alignement */
+
+#define ADC_CR2_JEXTSEL_Pos (12U)
+#define ADC_CR2_JEXTSEL_Msk (0x7U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00007000 */
+#define ADC_CR2_JEXTSEL ADC_CR2_JEXTSEL_Msk /*!< ADC group injected external trigger source */
+#define ADC_CR2_JEXTSEL_0 (0x1U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00001000 */
+#define ADC_CR2_JEXTSEL_1 (0x2U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00002000 */
+#define ADC_CR2_JEXTSEL_2 (0x4U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00004000 */
+
+#define ADC_CR2_JEXTTRIG_Pos (15U)
+#define ADC_CR2_JEXTTRIG_Msk (0x1U << ADC_CR2_JEXTTRIG_Pos) /*!< 0x00008000 */
+#define ADC_CR2_JEXTTRIG ADC_CR2_JEXTTRIG_Msk /*!< ADC group injected external trigger enable */
+
+#define ADC_CR2_EXTSEL_Pos (17U)
+#define ADC_CR2_EXTSEL_Msk (0x7U << ADC_CR2_EXTSEL_Pos) /*!< 0x000E0000 */
+#define ADC_CR2_EXTSEL ADC_CR2_EXTSEL_Msk /*!< ADC group regular external trigger source */
+#define ADC_CR2_EXTSEL_0 (0x1U << ADC_CR2_EXTSEL_Pos) /*!< 0x00020000 */
+#define ADC_CR2_EXTSEL_1 (0x2U << ADC_CR2_EXTSEL_Pos) /*!< 0x00040000 */
+#define ADC_CR2_EXTSEL_2 (0x4U << ADC_CR2_EXTSEL_Pos) /*!< 0x00080000 */
+
+#define ADC_CR2_EXTTRIG_Pos (20U)
+#define ADC_CR2_EXTTRIG_Msk (0x1U << ADC_CR2_EXTTRIG_Pos) /*!< 0x00100000 */
+#define ADC_CR2_EXTTRIG ADC_CR2_EXTTRIG_Msk /*!< ADC group regular external trigger enable */
+#define ADC_CR2_JSWSTART_Pos (21U)
+#define ADC_CR2_JSWSTART_Msk (0x1U << ADC_CR2_JSWSTART_Pos) /*!< 0x00200000 */
+#define ADC_CR2_JSWSTART ADC_CR2_JSWSTART_Msk /*!< ADC group injected conversion start */
+#define ADC_CR2_SWSTART_Pos (22U)
+#define ADC_CR2_SWSTART_Msk (0x1U << ADC_CR2_SWSTART_Pos) /*!< 0x00400000 */
+#define ADC_CR2_SWSTART ADC_CR2_SWSTART_Msk /*!< ADC group regular conversion start */
+#define ADC_CR2_TSVREFE_Pos (23U)
+#define ADC_CR2_TSVREFE_Msk (0x1U << ADC_CR2_TSVREFE_Pos) /*!< 0x00800000 */
+#define ADC_CR2_TSVREFE ADC_CR2_TSVREFE_Msk /*!< ADC internal path to VrefInt and temperature sensor enable */
+
+/****************** Bit definition for ADC_SMPR1 register *******************/
+#define ADC_SMPR1_SMP10_Pos (0U)
+#define ADC_SMPR1_SMP10_Msk (0x7U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000007 */
+#define ADC_SMPR1_SMP10 ADC_SMPR1_SMP10_Msk /*!< ADC channel 10 sampling time selection */
+#define ADC_SMPR1_SMP10_0 (0x1U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000001 */
+#define ADC_SMPR1_SMP10_1 (0x2U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000002 */
+#define ADC_SMPR1_SMP10_2 (0x4U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000004 */
+
+#define ADC_SMPR1_SMP11_Pos (3U)
+#define ADC_SMPR1_SMP11_Msk (0x7U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000038 */
+#define ADC_SMPR1_SMP11 ADC_SMPR1_SMP11_Msk /*!< ADC channel 11 sampling time selection */
+#define ADC_SMPR1_SMP11_0 (0x1U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000008 */
+#define ADC_SMPR1_SMP11_1 (0x2U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000010 */
+#define ADC_SMPR1_SMP11_2 (0x4U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000020 */
+
+#define ADC_SMPR1_SMP12_Pos (6U)
+#define ADC_SMPR1_SMP12_Msk (0x7U << ADC_SMPR1_SMP12_Pos) /*!< 0x000001C0 */
+#define ADC_SMPR1_SMP12 ADC_SMPR1_SMP12_Msk /*!< ADC channel 12 sampling time selection */
+#define ADC_SMPR1_SMP12_0 (0x1U << ADC_SMPR1_SMP12_Pos) /*!< 0x00000040 */
+#define ADC_SMPR1_SMP12_1 (0x2U << ADC_SMPR1_SMP12_Pos) /*!< 0x00000080 */
+#define ADC_SMPR1_SMP12_2 (0x4U << ADC_SMPR1_SMP12_Pos) /*!< 0x00000100 */
+
+#define ADC_SMPR1_SMP13_Pos (9U)
+#define ADC_SMPR1_SMP13_Msk (0x7U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000E00 */
+#define ADC_SMPR1_SMP13 ADC_SMPR1_SMP13_Msk /*!< ADC channel 13 sampling time selection */
+#define ADC_SMPR1_SMP13_0 (0x1U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000200 */
+#define ADC_SMPR1_SMP13_1 (0x2U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000400 */
+#define ADC_SMPR1_SMP13_2 (0x4U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000800 */
+
+#define ADC_SMPR1_SMP14_Pos (12U)
+#define ADC_SMPR1_SMP14_Msk (0x7U << ADC_SMPR1_SMP14_Pos) /*!< 0x00007000 */
+#define ADC_SMPR1_SMP14 ADC_SMPR1_SMP14_Msk /*!< ADC channel 14 sampling time selection */
+#define ADC_SMPR1_SMP14_0 (0x1U << ADC_SMPR1_SMP14_Pos) /*!< 0x00001000 */
+#define ADC_SMPR1_SMP14_1 (0x2U << ADC_SMPR1_SMP14_Pos) /*!< 0x00002000 */
+#define ADC_SMPR1_SMP14_2 (0x4U << ADC_SMPR1_SMP14_Pos) /*!< 0x00004000 */
+
+#define ADC_SMPR1_SMP15_Pos (15U)
+#define ADC_SMPR1_SMP15_Msk (0x7U << ADC_SMPR1_SMP15_Pos) /*!< 0x00038000 */
+#define ADC_SMPR1_SMP15 ADC_SMPR1_SMP15_Msk /*!< ADC channel 15 sampling time selection */
+#define ADC_SMPR1_SMP15_0 (0x1U << ADC_SMPR1_SMP15_Pos) /*!< 0x00008000 */
+#define ADC_SMPR1_SMP15_1 (0x2U << ADC_SMPR1_SMP15_Pos) /*!< 0x00010000 */
+#define ADC_SMPR1_SMP15_2 (0x4U << ADC_SMPR1_SMP15_Pos) /*!< 0x00020000 */
+
+#define ADC_SMPR1_SMP16_Pos (18U)
+#define ADC_SMPR1_SMP16_Msk (0x7U << ADC_SMPR1_SMP16_Pos) /*!< 0x001C0000 */
+#define ADC_SMPR1_SMP16 ADC_SMPR1_SMP16_Msk /*!< ADC channel 16 sampling time selection */
+#define ADC_SMPR1_SMP16_0 (0x1U << ADC_SMPR1_SMP16_Pos) /*!< 0x00040000 */
+#define ADC_SMPR1_SMP16_1 (0x2U << ADC_SMPR1_SMP16_Pos) /*!< 0x00080000 */
+#define ADC_SMPR1_SMP16_2 (0x4U << ADC_SMPR1_SMP16_Pos) /*!< 0x00100000 */
+
+#define ADC_SMPR1_SMP17_Pos (21U)
+#define ADC_SMPR1_SMP17_Msk (0x7U << ADC_SMPR1_SMP17_Pos) /*!< 0x00E00000 */
+#define ADC_SMPR1_SMP17 ADC_SMPR1_SMP17_Msk /*!< ADC channel 17 sampling time selection */
+#define ADC_SMPR1_SMP17_0 (0x1U << ADC_SMPR1_SMP17_Pos) /*!< 0x00200000 */
+#define ADC_SMPR1_SMP17_1 (0x2U << ADC_SMPR1_SMP17_Pos) /*!< 0x00400000 */
+#define ADC_SMPR1_SMP17_2 (0x4U << ADC_SMPR1_SMP17_Pos) /*!< 0x00800000 */
+
+/****************** Bit definition for ADC_SMPR2 register *******************/
+#define ADC_SMPR2_SMP0_Pos (0U)
+#define ADC_SMPR2_SMP0_Msk (0x7U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000007 */
+#define ADC_SMPR2_SMP0 ADC_SMPR2_SMP0_Msk /*!< ADC channel 0 sampling time selection */
+#define ADC_SMPR2_SMP0_0 (0x1U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000001 */
+#define ADC_SMPR2_SMP0_1 (0x2U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000002 */
+#define ADC_SMPR2_SMP0_2 (0x4U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000004 */
+
+#define ADC_SMPR2_SMP1_Pos (3U)
+#define ADC_SMPR2_SMP1_Msk (0x7U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000038 */
+#define ADC_SMPR2_SMP1 ADC_SMPR2_SMP1_Msk /*!< ADC channel 1 sampling time selection */
+#define ADC_SMPR2_SMP1_0 (0x1U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000008 */
+#define ADC_SMPR2_SMP1_1 (0x2U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000010 */
+#define ADC_SMPR2_SMP1_2 (0x4U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000020 */
+
+#define ADC_SMPR2_SMP2_Pos (6U)
+#define ADC_SMPR2_SMP2_Msk (0x7U << ADC_SMPR2_SMP2_Pos) /*!< 0x000001C0 */
+#define ADC_SMPR2_SMP2 ADC_SMPR2_SMP2_Msk /*!< ADC channel 2 sampling time selection */
+#define ADC_SMPR2_SMP2_0 (0x1U << ADC_SMPR2_SMP2_Pos) /*!< 0x00000040 */
+#define ADC_SMPR2_SMP2_1 (0x2U << ADC_SMPR2_SMP2_Pos) /*!< 0x00000080 */
+#define ADC_SMPR2_SMP2_2 (0x4U << ADC_SMPR2_SMP2_Pos) /*!< 0x00000100 */
+
+#define ADC_SMPR2_SMP3_Pos (9U)
+#define ADC_SMPR2_SMP3_Msk (0x7U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000E00 */
+#define ADC_SMPR2_SMP3 ADC_SMPR2_SMP3_Msk /*!< ADC channel 3 sampling time selection */
+#define ADC_SMPR2_SMP3_0 (0x1U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000200 */
+#define ADC_SMPR2_SMP3_1 (0x2U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000400 */
+#define ADC_SMPR2_SMP3_2 (0x4U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000800 */
+
+#define ADC_SMPR2_SMP4_Pos (12U)
+#define ADC_SMPR2_SMP4_Msk (0x7U << ADC_SMPR2_SMP4_Pos) /*!< 0x00007000 */
+#define ADC_SMPR2_SMP4 ADC_SMPR2_SMP4_Msk /*!< ADC channel 4 sampling time selection */
+#define ADC_SMPR2_SMP4_0 (0x1U << ADC_SMPR2_SMP4_Pos) /*!< 0x00001000 */
+#define ADC_SMPR2_SMP4_1 (0x2U << ADC_SMPR2_SMP4_Pos) /*!< 0x00002000 */
+#define ADC_SMPR2_SMP4_2 (0x4U << ADC_SMPR2_SMP4_Pos) /*!< 0x00004000 */
+
+#define ADC_SMPR2_SMP5_Pos (15U)
+#define ADC_SMPR2_SMP5_Msk (0x7U << ADC_SMPR2_SMP5_Pos) /*!< 0x00038000 */
+#define ADC_SMPR2_SMP5 ADC_SMPR2_SMP5_Msk /*!< ADC channel 5 sampling time selection */
+#define ADC_SMPR2_SMP5_0 (0x1U << ADC_SMPR2_SMP5_Pos) /*!< 0x00008000 */
+#define ADC_SMPR2_SMP5_1 (0x2U << ADC_SMPR2_SMP5_Pos) /*!< 0x00010000 */
+#define ADC_SMPR2_SMP5_2 (0x4U << ADC_SMPR2_SMP5_Pos) /*!< 0x00020000 */
+
+#define ADC_SMPR2_SMP6_Pos (18U)
+#define ADC_SMPR2_SMP6_Msk (0x7U << ADC_SMPR2_SMP6_Pos) /*!< 0x001C0000 */
+#define ADC_SMPR2_SMP6 ADC_SMPR2_SMP6_Msk /*!< ADC channel 6 sampling time selection */
+#define ADC_SMPR2_SMP6_0 (0x1U << ADC_SMPR2_SMP6_Pos) /*!< 0x00040000 */
+#define ADC_SMPR2_SMP6_1 (0x2U << ADC_SMPR2_SMP6_Pos) /*!< 0x00080000 */
+#define ADC_SMPR2_SMP6_2 (0x4U << ADC_SMPR2_SMP6_Pos) /*!< 0x00100000 */
+
+#define ADC_SMPR2_SMP7_Pos (21U)
+#define ADC_SMPR2_SMP7_Msk (0x7U << ADC_SMPR2_SMP7_Pos) /*!< 0x00E00000 */
+#define ADC_SMPR2_SMP7 ADC_SMPR2_SMP7_Msk /*!< ADC channel 7 sampling time selection */
+#define ADC_SMPR2_SMP7_0 (0x1U << ADC_SMPR2_SMP7_Pos) /*!< 0x00200000 */
+#define ADC_SMPR2_SMP7_1 (0x2U << ADC_SMPR2_SMP7_Pos) /*!< 0x00400000 */
+#define ADC_SMPR2_SMP7_2 (0x4U << ADC_SMPR2_SMP7_Pos) /*!< 0x00800000 */
+
+#define ADC_SMPR2_SMP8_Pos (24U)
+#define ADC_SMPR2_SMP8_Msk (0x7U << ADC_SMPR2_SMP8_Pos) /*!< 0x07000000 */
+#define ADC_SMPR2_SMP8 ADC_SMPR2_SMP8_Msk /*!< ADC channel 8 sampling time selection */
+#define ADC_SMPR2_SMP8_0 (0x1U << ADC_SMPR2_SMP8_Pos) /*!< 0x01000000 */
+#define ADC_SMPR2_SMP8_1 (0x2U << ADC_SMPR2_SMP8_Pos) /*!< 0x02000000 */
+#define ADC_SMPR2_SMP8_2 (0x4U << ADC_SMPR2_SMP8_Pos) /*!< 0x04000000 */
+
+#define ADC_SMPR2_SMP9_Pos (27U)
+#define ADC_SMPR2_SMP9_Msk (0x7U << ADC_SMPR2_SMP9_Pos) /*!< 0x38000000 */
+#define ADC_SMPR2_SMP9 ADC_SMPR2_SMP9_Msk /*!< ADC channel 9 sampling time selection */
+#define ADC_SMPR2_SMP9_0 (0x1U << ADC_SMPR2_SMP9_Pos) /*!< 0x08000000 */
+#define ADC_SMPR2_SMP9_1 (0x2U << ADC_SMPR2_SMP9_Pos) /*!< 0x10000000 */
+#define ADC_SMPR2_SMP9_2 (0x4U << ADC_SMPR2_SMP9_Pos) /*!< 0x20000000 */
+
+/****************** Bit definition for ADC_JOFR1 register *******************/
+#define ADC_JOFR1_JOFFSET1_Pos (0U)
+#define ADC_JOFR1_JOFFSET1_Msk (0xFFFU << ADC_JOFR1_JOFFSET1_Pos) /*!< 0x00000FFF */
+#define ADC_JOFR1_JOFFSET1 ADC_JOFR1_JOFFSET1_Msk /*!< ADC group injected sequencer rank 1 offset value */
+
+/****************** Bit definition for ADC_JOFR2 register *******************/
+#define ADC_JOFR2_JOFFSET2_Pos (0U)
+#define ADC_JOFR2_JOFFSET2_Msk (0xFFFU << ADC_JOFR2_JOFFSET2_Pos) /*!< 0x00000FFF */
+#define ADC_JOFR2_JOFFSET2 ADC_JOFR2_JOFFSET2_Msk /*!< ADC group injected sequencer rank 2 offset value */
+
+/****************** Bit definition for ADC_JOFR3 register *******************/
+#define ADC_JOFR3_JOFFSET3_Pos (0U)
+#define ADC_JOFR3_JOFFSET3_Msk (0xFFFU << ADC_JOFR3_JOFFSET3_Pos) /*!< 0x00000FFF */
+#define ADC_JOFR3_JOFFSET3 ADC_JOFR3_JOFFSET3_Msk /*!< ADC group injected sequencer rank 3 offset value */
+
+/****************** Bit definition for ADC_JOFR4 register *******************/
+#define ADC_JOFR4_JOFFSET4_Pos (0U)
+#define ADC_JOFR4_JOFFSET4_Msk (0xFFFU << ADC_JOFR4_JOFFSET4_Pos) /*!< 0x00000FFF */
+#define ADC_JOFR4_JOFFSET4 ADC_JOFR4_JOFFSET4_Msk /*!< ADC group injected sequencer rank 4 offset value */
+
+/******************* Bit definition for ADC_HTR register ********************/
+#define ADC_HTR_HT_Pos (0U)
+#define ADC_HTR_HT_Msk (0xFFFU << ADC_HTR_HT_Pos) /*!< 0x00000FFF */
+#define ADC_HTR_HT ADC_HTR_HT_Msk /*!< ADC analog watchdog 1 threshold high */
+
+/******************* Bit definition for ADC_LTR register ********************/
+#define ADC_LTR_LT_Pos (0U)
+#define ADC_LTR_LT_Msk (0xFFFU << ADC_LTR_LT_Pos) /*!< 0x00000FFF */
+#define ADC_LTR_LT ADC_LTR_LT_Msk /*!< ADC analog watchdog 1 threshold low */
+
+/******************* Bit definition for ADC_SQR1 register *******************/
+#define ADC_SQR1_SQ13_Pos (0U)
+#define ADC_SQR1_SQ13_Msk (0x1FU << ADC_SQR1_SQ13_Pos) /*!< 0x0000001F */
+#define ADC_SQR1_SQ13 ADC_SQR1_SQ13_Msk /*!< ADC group regular sequencer rank 13 */
+#define ADC_SQR1_SQ13_0 (0x01U << ADC_SQR1_SQ13_Pos) /*!< 0x00000001 */
+#define ADC_SQR1_SQ13_1 (0x02U << ADC_SQR1_SQ13_Pos) /*!< 0x00000002 */
+#define ADC_SQR1_SQ13_2 (0x04U << ADC_SQR1_SQ13_Pos) /*!< 0x00000004 */
+#define ADC_SQR1_SQ13_3 (0x08U << ADC_SQR1_SQ13_Pos) /*!< 0x00000008 */
+#define ADC_SQR1_SQ13_4 (0x10U << ADC_SQR1_SQ13_Pos) /*!< 0x00000010 */
+
+#define ADC_SQR1_SQ14_Pos (5U)
+#define ADC_SQR1_SQ14_Msk (0x1FU << ADC_SQR1_SQ14_Pos) /*!< 0x000003E0 */
+#define ADC_SQR1_SQ14 ADC_SQR1_SQ14_Msk /*!< ADC group regular sequencer rank 14 */
+#define ADC_SQR1_SQ14_0 (0x01U << ADC_SQR1_SQ14_Pos) /*!< 0x00000020 */
+#define ADC_SQR1_SQ14_1 (0x02U << ADC_SQR1_SQ14_Pos) /*!< 0x00000040 */
+#define ADC_SQR1_SQ14_2 (0x04U << ADC_SQR1_SQ14_Pos) /*!< 0x00000080 */
+#define ADC_SQR1_SQ14_3 (0x08U << ADC_SQR1_SQ14_Pos) /*!< 0x00000100 */
+#define ADC_SQR1_SQ14_4 (0x10U << ADC_SQR1_SQ14_Pos) /*!< 0x00000200 */
+
+#define ADC_SQR1_SQ15_Pos (10U)
+#define ADC_SQR1_SQ15_Msk (0x1FU << ADC_SQR1_SQ15_Pos) /*!< 0x00007C00 */
+#define ADC_SQR1_SQ15 ADC_SQR1_SQ15_Msk /*!< ADC group regular sequencer rank 15 */
+#define ADC_SQR1_SQ15_0 (0x01U << ADC_SQR1_SQ15_Pos) /*!< 0x00000400 */
+#define ADC_SQR1_SQ15_1 (0x02U << ADC_SQR1_SQ15_Pos) /*!< 0x00000800 */
+#define ADC_SQR1_SQ15_2 (0x04U << ADC_SQR1_SQ15_Pos) /*!< 0x00001000 */
+#define ADC_SQR1_SQ15_3 (0x08U << ADC_SQR1_SQ15_Pos) /*!< 0x00002000 */
+#define ADC_SQR1_SQ15_4 (0x10U << ADC_SQR1_SQ15_Pos) /*!< 0x00004000 */
+
+#define ADC_SQR1_SQ16_Pos (15U)
+#define ADC_SQR1_SQ16_Msk (0x1FU << ADC_SQR1_SQ16_Pos) /*!< 0x000F8000 */
+#define ADC_SQR1_SQ16 ADC_SQR1_SQ16_Msk /*!< ADC group regular sequencer rank 16 */
+#define ADC_SQR1_SQ16_0 (0x01U << ADC_SQR1_SQ16_Pos) /*!< 0x00008000 */
+#define ADC_SQR1_SQ16_1 (0x02U << ADC_SQR1_SQ16_Pos) /*!< 0x00010000 */
+#define ADC_SQR1_SQ16_2 (0x04U << ADC_SQR1_SQ16_Pos) /*!< 0x00020000 */
+#define ADC_SQR1_SQ16_3 (0x08U << ADC_SQR1_SQ16_Pos) /*!< 0x00040000 */
+#define ADC_SQR1_SQ16_4 (0x10U << ADC_SQR1_SQ16_Pos) /*!< 0x00080000 */
+
+#define ADC_SQR1_L_Pos (20U)
+#define ADC_SQR1_L_Msk (0xFU << ADC_SQR1_L_Pos) /*!< 0x00F00000 */
+#define ADC_SQR1_L ADC_SQR1_L_Msk /*!< ADC group regular sequencer scan length */
+#define ADC_SQR1_L_0 (0x1U << ADC_SQR1_L_Pos) /*!< 0x00100000 */
+#define ADC_SQR1_L_1 (0x2U << ADC_SQR1_L_Pos) /*!< 0x00200000 */
+#define ADC_SQR1_L_2 (0x4U << ADC_SQR1_L_Pos) /*!< 0x00400000 */
+#define ADC_SQR1_L_3 (0x8U << ADC_SQR1_L_Pos) /*!< 0x00800000 */
+
+/******************* Bit definition for ADC_SQR2 register *******************/
+#define ADC_SQR2_SQ7_Pos (0U)
+#define ADC_SQR2_SQ7_Msk (0x1FU << ADC_SQR2_SQ7_Pos) /*!< 0x0000001F */
+#define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk /*!< ADC group regular sequencer rank 7 */
+#define ADC_SQR2_SQ7_0 (0x01U << ADC_SQR2_SQ7_Pos) /*!< 0x00000001 */
+#define ADC_SQR2_SQ7_1 (0x02U << ADC_SQR2_SQ7_Pos) /*!< 0x00000002 */
+#define ADC_SQR2_SQ7_2 (0x04U << ADC_SQR2_SQ7_Pos) /*!< 0x00000004 */
+#define ADC_SQR2_SQ7_3 (0x08U << ADC_SQR2_SQ7_Pos) /*!< 0x00000008 */
+#define ADC_SQR2_SQ7_4 (0x10U << ADC_SQR2_SQ7_Pos) /*!< 0x00000010 */
+
+#define ADC_SQR2_SQ8_Pos (5U)
+#define ADC_SQR2_SQ8_Msk (0x1FU << ADC_SQR2_SQ8_Pos) /*!< 0x000003E0 */
+#define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk /*!< ADC group regular sequencer rank 8 */
+#define ADC_SQR2_SQ8_0 (0x01U << ADC_SQR2_SQ8_Pos) /*!< 0x00000020 */
+#define ADC_SQR2_SQ8_1 (0x02U << ADC_SQR2_SQ8_Pos) /*!< 0x00000040 */
+#define ADC_SQR2_SQ8_2 (0x04U << ADC_SQR2_SQ8_Pos) /*!< 0x00000080 */
+#define ADC_SQR2_SQ8_3 (0x08U << ADC_SQR2_SQ8_Pos) /*!< 0x00000100 */
+#define ADC_SQR2_SQ8_4 (0x10U << ADC_SQR2_SQ8_Pos) /*!< 0x00000200 */
+
+#define ADC_SQR2_SQ9_Pos (10U)
+#define ADC_SQR2_SQ9_Msk (0x1FU << ADC_SQR2_SQ9_Pos) /*!< 0x00007C00 */
+#define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk /*!< ADC group regular sequencer rank 9 */
+#define ADC_SQR2_SQ9_0 (0x01U << ADC_SQR2_SQ9_Pos) /*!< 0x00000400 */
+#define ADC_SQR2_SQ9_1 (0x02U << ADC_SQR2_SQ9_Pos) /*!< 0x00000800 */
+#define ADC_SQR2_SQ9_2 (0x04U << ADC_SQR2_SQ9_Pos) /*!< 0x00001000 */
+#define ADC_SQR2_SQ9_3 (0x08U << ADC_SQR2_SQ9_Pos) /*!< 0x00002000 */
+#define ADC_SQR2_SQ9_4 (0x10U << ADC_SQR2_SQ9_Pos) /*!< 0x00004000 */
+
+#define ADC_SQR2_SQ10_Pos (15U)
+#define ADC_SQR2_SQ10_Msk (0x1FU << ADC_SQR2_SQ10_Pos) /*!< 0x000F8000 */
+#define ADC_SQR2_SQ10 ADC_SQR2_SQ10_Msk /*!< ADC group regular sequencer rank 10 */
+#define ADC_SQR2_SQ10_0 (0x01U << ADC_SQR2_SQ10_Pos) /*!< 0x00008000 */
+#define ADC_SQR2_SQ10_1 (0x02U << ADC_SQR2_SQ10_Pos) /*!< 0x00010000 */
+#define ADC_SQR2_SQ10_2 (0x04U << ADC_SQR2_SQ10_Pos) /*!< 0x00020000 */
+#define ADC_SQR2_SQ10_3 (0x08U << ADC_SQR2_SQ10_Pos) /*!< 0x00040000 */
+#define ADC_SQR2_SQ10_4 (0x10U << ADC_SQR2_SQ10_Pos) /*!< 0x00080000 */
+
+#define ADC_SQR2_SQ11_Pos (20U)
+#define ADC_SQR2_SQ11_Msk (0x1FU << ADC_SQR2_SQ11_Pos) /*!< 0x01F00000 */
+#define ADC_SQR2_SQ11 ADC_SQR2_SQ11_Msk /*!< ADC group regular sequencer rank 1 */
+#define ADC_SQR2_SQ11_0 (0x01U << ADC_SQR2_SQ11_Pos) /*!< 0x00100000 */
+#define ADC_SQR2_SQ11_1 (0x02U << ADC_SQR2_SQ11_Pos) /*!< 0x00200000 */
+#define ADC_SQR2_SQ11_2 (0x04U << ADC_SQR2_SQ11_Pos) /*!< 0x00400000 */
+#define ADC_SQR2_SQ11_3 (0x08U << ADC_SQR2_SQ11_Pos) /*!< 0x00800000 */
+#define ADC_SQR2_SQ11_4 (0x10U << ADC_SQR2_SQ11_Pos) /*!< 0x01000000 */
+
+#define ADC_SQR2_SQ12_Pos (25U)
+#define ADC_SQR2_SQ12_Msk (0x1FU << ADC_SQR2_SQ12_Pos) /*!< 0x3E000000 */
+#define ADC_SQR2_SQ12 ADC_SQR2_SQ12_Msk /*!< ADC group regular sequencer rank 12 */
+#define ADC_SQR2_SQ12_0 (0x01U << ADC_SQR2_SQ12_Pos) /*!< 0x02000000 */
+#define ADC_SQR2_SQ12_1 (0x02U << ADC_SQR2_SQ12_Pos) /*!< 0x04000000 */
+#define ADC_SQR2_SQ12_2 (0x04U << ADC_SQR2_SQ12_Pos) /*!< 0x08000000 */
+#define ADC_SQR2_SQ12_3 (0x08U << ADC_SQR2_SQ12_Pos) /*!< 0x10000000 */
+#define ADC_SQR2_SQ12_4 (0x10U << ADC_SQR2_SQ12_Pos) /*!< 0x20000000 */
+
+/******************* Bit definition for ADC_SQR3 register *******************/
+#define ADC_SQR3_SQ1_Pos (0U)
+#define ADC_SQR3_SQ1_Msk (0x1FU << ADC_SQR3_SQ1_Pos) /*!< 0x0000001F */
+#define ADC_SQR3_SQ1 ADC_SQR3_SQ1_Msk /*!< ADC group regular sequencer rank 1 */
+#define ADC_SQR3_SQ1_0 (0x01U << ADC_SQR3_SQ1_Pos) /*!< 0x00000001 */
+#define ADC_SQR3_SQ1_1 (0x02U << ADC_SQR3_SQ1_Pos) /*!< 0x00000002 */
+#define ADC_SQR3_SQ1_2 (0x04U << ADC_SQR3_SQ1_Pos) /*!< 0x00000004 */
+#define ADC_SQR3_SQ1_3 (0x08U << ADC_SQR3_SQ1_Pos) /*!< 0x00000008 */
+#define ADC_SQR3_SQ1_4 (0x10U << ADC_SQR3_SQ1_Pos) /*!< 0x00000010 */
+
+#define ADC_SQR3_SQ2_Pos (5U)
+#define ADC_SQR3_SQ2_Msk (0x1FU << ADC_SQR3_SQ2_Pos) /*!< 0x000003E0 */
+#define ADC_SQR3_SQ2 ADC_SQR3_SQ2_Msk /*!< ADC group regular sequencer rank 2 */
+#define ADC_SQR3_SQ2_0 (0x01U << ADC_SQR3_SQ2_Pos) /*!< 0x00000020 */
+#define ADC_SQR3_SQ2_1 (0x02U << ADC_SQR3_SQ2_Pos) /*!< 0x00000040 */
+#define ADC_SQR3_SQ2_2 (0x04U << ADC_SQR3_SQ2_Pos) /*!< 0x00000080 */
+#define ADC_SQR3_SQ2_3 (0x08U << ADC_SQR3_SQ2_Pos) /*!< 0x00000100 */
+#define ADC_SQR3_SQ2_4 (0x10U << ADC_SQR3_SQ2_Pos) /*!< 0x00000200 */
+
+#define ADC_SQR3_SQ3_Pos (10U)
+#define ADC_SQR3_SQ3_Msk (0x1FU << ADC_SQR3_SQ3_Pos) /*!< 0x00007C00 */
+#define ADC_SQR3_SQ3 ADC_SQR3_SQ3_Msk /*!< ADC group regular sequencer rank 3 */
+#define ADC_SQR3_SQ3_0 (0x01U << ADC_SQR3_SQ3_Pos) /*!< 0x00000400 */
+#define ADC_SQR3_SQ3_1 (0x02U << ADC_SQR3_SQ3_Pos) /*!< 0x00000800 */
+#define ADC_SQR3_SQ3_2 (0x04U << ADC_SQR3_SQ3_Pos) /*!< 0x00001000 */
+#define ADC_SQR3_SQ3_3 (0x08U << ADC_SQR3_SQ3_Pos) /*!< 0x00002000 */
+#define ADC_SQR3_SQ3_4 (0x10U << ADC_SQR3_SQ3_Pos) /*!< 0x00004000 */
+
+#define ADC_SQR3_SQ4_Pos (15U)
+#define ADC_SQR3_SQ4_Msk (0x1FU << ADC_SQR3_SQ4_Pos) /*!< 0x000F8000 */
+#define ADC_SQR3_SQ4 ADC_SQR3_SQ4_Msk /*!< ADC group regular sequencer rank 4 */
+#define ADC_SQR3_SQ4_0 (0x01U << ADC_SQR3_SQ4_Pos) /*!< 0x00008000 */
+#define ADC_SQR3_SQ4_1 (0x02U << ADC_SQR3_SQ4_Pos) /*!< 0x00010000 */
+#define ADC_SQR3_SQ4_2 (0x04U << ADC_SQR3_SQ4_Pos) /*!< 0x00020000 */
+#define ADC_SQR3_SQ4_3 (0x08U << ADC_SQR3_SQ4_Pos) /*!< 0x00040000 */
+#define ADC_SQR3_SQ4_4 (0x10U << ADC_SQR3_SQ4_Pos) /*!< 0x00080000 */
+
+#define ADC_SQR3_SQ5_Pos (20U)
+#define ADC_SQR3_SQ5_Msk (0x1FU << ADC_SQR3_SQ5_Pos) /*!< 0x01F00000 */
+#define ADC_SQR3_SQ5 ADC_SQR3_SQ5_Msk /*!< ADC group regular sequencer rank 5 */
+#define ADC_SQR3_SQ5_0 (0x01U << ADC_SQR3_SQ5_Pos) /*!< 0x00100000 */
+#define ADC_SQR3_SQ5_1 (0x02U << ADC_SQR3_SQ5_Pos) /*!< 0x00200000 */
+#define ADC_SQR3_SQ5_2 (0x04U << ADC_SQR3_SQ5_Pos) /*!< 0x00400000 */
+#define ADC_SQR3_SQ5_3 (0x08U << ADC_SQR3_SQ5_Pos) /*!< 0x00800000 */
+#define ADC_SQR3_SQ5_4 (0x10U << ADC_SQR3_SQ5_Pos) /*!< 0x01000000 */
+
+#define ADC_SQR3_SQ6_Pos (25U)
+#define ADC_SQR3_SQ6_Msk (0x1FU << ADC_SQR3_SQ6_Pos) /*!< 0x3E000000 */
+#define ADC_SQR3_SQ6 ADC_SQR3_SQ6_Msk /*!< ADC group regular sequencer rank 6 */
+#define ADC_SQR3_SQ6_0 (0x01U << ADC_SQR3_SQ6_Pos) /*!< 0x02000000 */
+#define ADC_SQR3_SQ6_1 (0x02U << ADC_SQR3_SQ6_Pos) /*!< 0x04000000 */
+#define ADC_SQR3_SQ6_2 (0x04U << ADC_SQR3_SQ6_Pos) /*!< 0x08000000 */
+#define ADC_SQR3_SQ6_3 (0x08U << ADC_SQR3_SQ6_Pos) /*!< 0x10000000 */
+#define ADC_SQR3_SQ6_4 (0x10U << ADC_SQR3_SQ6_Pos) /*!< 0x20000000 */
+
+/******************* Bit definition for ADC_JSQR register *******************/
+#define ADC_JSQR_JSQ1_Pos (0U)
+#define ADC_JSQR_JSQ1_Msk (0x1FU << ADC_JSQR_JSQ1_Pos) /*!< 0x0000001F */
+#define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!< ADC group injected sequencer rank 1 */
+#define ADC_JSQR_JSQ1_0 (0x01U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000001 */
+#define ADC_JSQR_JSQ1_1 (0x02U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000002 */
+#define ADC_JSQR_JSQ1_2 (0x04U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000004 */
+#define ADC_JSQR_JSQ1_3 (0x08U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000008 */
+#define ADC_JSQR_JSQ1_4 (0x10U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000010 */
+
+#define ADC_JSQR_JSQ2_Pos (5U)
+#define ADC_JSQR_JSQ2_Msk (0x1FU << ADC_JSQR_JSQ2_Pos) /*!< 0x000003E0 */
+#define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!< ADC group injected sequencer rank 2 */
+#define ADC_JSQR_JSQ2_0 (0x01U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000020 */
+#define ADC_JSQR_JSQ2_1 (0x02U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000040 */
+#define ADC_JSQR_JSQ2_2 (0x04U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000080 */
+#define ADC_JSQR_JSQ2_3 (0x08U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000100 */
+#define ADC_JSQR_JSQ2_4 (0x10U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000200 */
+
+#define ADC_JSQR_JSQ3_Pos (10U)
+#define ADC_JSQR_JSQ3_Msk (0x1FU << ADC_JSQR_JSQ3_Pos) /*!< 0x00007C00 */
+#define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!< ADC group injected sequencer rank 3 */
+#define ADC_JSQR_JSQ3_0 (0x01U << ADC_JSQR_JSQ3_Pos) /*!< 0x00000400 */
+#define ADC_JSQR_JSQ3_1 (0x02U << ADC_JSQR_JSQ3_Pos) /*!< 0x00000800 */
+#define ADC_JSQR_JSQ3_2 (0x04U << ADC_JSQR_JSQ3_Pos) /*!< 0x00001000 */
+#define ADC_JSQR_JSQ3_3 (0x08U << ADC_JSQR_JSQ3_Pos) /*!< 0x00002000 */
+#define ADC_JSQR_JSQ3_4 (0x10U << ADC_JSQR_JSQ3_Pos) /*!< 0x00004000 */
+
+#define ADC_JSQR_JSQ4_Pos (15U)
+#define ADC_JSQR_JSQ4_Msk (0x1FU << ADC_JSQR_JSQ4_Pos) /*!< 0x000F8000 */
+#define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!< ADC group injected sequencer rank 4 */
+#define ADC_JSQR_JSQ4_0 (0x01U << ADC_JSQR_JSQ4_Pos) /*!< 0x00008000 */
+#define ADC_JSQR_JSQ4_1 (0x02U << ADC_JSQR_JSQ4_Pos) /*!< 0x00010000 */
+#define ADC_JSQR_JSQ4_2 (0x04U << ADC_JSQR_JSQ4_Pos) /*!< 0x00020000 */
+#define ADC_JSQR_JSQ4_3 (0x08U << ADC_JSQR_JSQ4_Pos) /*!< 0x00040000 */
+#define ADC_JSQR_JSQ4_4 (0x10U << ADC_JSQR_JSQ4_Pos) /*!< 0x00080000 */
+
+#define ADC_JSQR_JL_Pos (20U)
+#define ADC_JSQR_JL_Msk (0x3U << ADC_JSQR_JL_Pos) /*!< 0x00300000 */
+#define ADC_JSQR_JL ADC_JSQR_JL_Msk /*!< ADC group injected sequencer scan length */
+#define ADC_JSQR_JL_0 (0x1U << ADC_JSQR_JL_Pos) /*!< 0x00100000 */
+#define ADC_JSQR_JL_1 (0x2U << ADC_JSQR_JL_Pos) /*!< 0x00200000 */
+
+/******************* Bit definition for ADC_JDR1 register *******************/
+#define ADC_JDR1_JDATA_Pos (0U)
+#define ADC_JDR1_JDATA_Msk (0xFFFFU << ADC_JDR1_JDATA_Pos) /*!< 0x0000FFFF */
+#define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!< ADC group injected sequencer rank 1 conversion data */
+
+/******************* Bit definition for ADC_JDR2 register *******************/
+#define ADC_JDR2_JDATA_Pos (0U)
+#define ADC_JDR2_JDATA_Msk (0xFFFFU << ADC_JDR2_JDATA_Pos) /*!< 0x0000FFFF */
+#define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!< ADC group injected sequencer rank 2 conversion data */
+
+/******************* Bit definition for ADC_JDR3 register *******************/
+#define ADC_JDR3_JDATA_Pos (0U)
+#define ADC_JDR3_JDATA_Msk (0xFFFFU << ADC_JDR3_JDATA_Pos) /*!< 0x0000FFFF */
+#define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!< ADC group injected sequencer rank 3 conversion data */
+
+/******************* Bit definition for ADC_JDR4 register *******************/
+#define ADC_JDR4_JDATA_Pos (0U)
+#define ADC_JDR4_JDATA_Msk (0xFFFFU << ADC_JDR4_JDATA_Pos) /*!< 0x0000FFFF */
+#define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!< ADC group injected sequencer rank 4 conversion data */
+
+/******************** Bit definition for ADC_DR register ********************/
+#define ADC_DR_DATA_Pos (0U)
+#define ADC_DR_DATA_Msk (0xFFFFU << ADC_DR_DATA_Pos) /*!< 0x0000FFFF */
+#define ADC_DR_DATA ADC_DR_DATA_Msk /*!< ADC group regular conversion data */
+#define ADC_DR_ADC2DATA_Pos (16U)
+#define ADC_DR_ADC2DATA_Msk (0xFFFFU << ADC_DR_ADC2DATA_Pos) /*!< 0xFFFF0000 */
+#define ADC_DR_ADC2DATA ADC_DR_ADC2DATA_Msk /*!< ADC group regular conversion data for ADC slave, in multimode */
+/******************************************************************************/
+/* */
+/* Digital to Analog Converter */
+/* */
+/******************************************************************************/
+
+/******************** Bit definition for DAC_CR register ********************/
+#define DAC_CR_EN1_Pos (0U)
+#define DAC_CR_EN1_Msk (0x1U << DAC_CR_EN1_Pos) /*!< 0x00000001 */
+#define DAC_CR_EN1 DAC_CR_EN1_Msk /*!< DAC channel1 enable */
+#define DAC_CR_BOFF1_Pos (1U)
+#define DAC_CR_BOFF1_Msk (0x1U << DAC_CR_BOFF1_Pos) /*!< 0x00000002 */
+#define DAC_CR_BOFF1 DAC_CR_BOFF1_Msk /*!< DAC channel1 output buffer disable */
+#define DAC_CR_TEN1_Pos (2U)
+#define DAC_CR_TEN1_Msk (0x1U << DAC_CR_TEN1_Pos) /*!< 0x00000004 */
+#define DAC_CR_TEN1 DAC_CR_TEN1_Msk /*!< DAC channel1 Trigger enable */
+
+#define DAC_CR_TSEL1_Pos (3U)
+#define DAC_CR_TSEL1_Msk (0x7U << DAC_CR_TSEL1_Pos) /*!< 0x00000038 */
+#define DAC_CR_TSEL1 DAC_CR_TSEL1_Msk /*!< TSEL1[2:0] (DAC channel1 Trigger selection) */
+#define DAC_CR_TSEL1_0 (0x1U << DAC_CR_TSEL1_Pos) /*!< 0x00000008 */
+#define DAC_CR_TSEL1_1 (0x2U << DAC_CR_TSEL1_Pos) /*!< 0x00000010 */
+#define DAC_CR_TSEL1_2 (0x4U << DAC_CR_TSEL1_Pos) /*!< 0x00000020 */
+
+#define DAC_CR_WAVE1_Pos (6U)
+#define DAC_CR_WAVE1_Msk (0x3U << DAC_CR_WAVE1_Pos) /*!< 0x000000C0 */
+#define DAC_CR_WAVE1 DAC_CR_WAVE1_Msk /*!< WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
+#define DAC_CR_WAVE1_0 (0x1U << DAC_CR_WAVE1_Pos) /*!< 0x00000040 */
+#define DAC_CR_WAVE1_1 (0x2U << DAC_CR_WAVE1_Pos) /*!< 0x00000080 */
+
+#define DAC_CR_MAMP1_Pos (8U)
+#define DAC_CR_MAMP1_Msk (0xFU << DAC_CR_MAMP1_Pos) /*!< 0x00000F00 */
+#define DAC_CR_MAMP1 DAC_CR_MAMP1_Msk /*!< MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
+#define DAC_CR_MAMP1_0 (0x1U << DAC_CR_MAMP1_Pos) /*!< 0x00000100 */
+#define DAC_CR_MAMP1_1 (0x2U << DAC_CR_MAMP1_Pos) /*!< 0x00000200 */
+#define DAC_CR_MAMP1_2 (0x4U << DAC_CR_MAMP1_Pos) /*!< 0x00000400 */
+#define DAC_CR_MAMP1_3 (0x8U << DAC_CR_MAMP1_Pos) /*!< 0x00000800 */
+
+#define DAC_CR_DMAEN1_Pos (12U)
+#define DAC_CR_DMAEN1_Msk (0x1U << DAC_CR_DMAEN1_Pos) /*!< 0x00001000 */
+#define DAC_CR_DMAEN1 DAC_CR_DMAEN1_Msk /*!< DAC channel1 DMA enable */
+#define DAC_CR_EN2_Pos (16U)
+#define DAC_CR_EN2_Msk (0x1U << DAC_CR_EN2_Pos) /*!< 0x00010000 */
+#define DAC_CR_EN2 DAC_CR_EN2_Msk /*!< DAC channel2 enable */
+#define DAC_CR_BOFF2_Pos (17U)
+#define DAC_CR_BOFF2_Msk (0x1U << DAC_CR_BOFF2_Pos) /*!< 0x00020000 */
+#define DAC_CR_BOFF2 DAC_CR_BOFF2_Msk /*!< DAC channel2 output buffer disable */
+#define DAC_CR_TEN2_Pos (18U)
+#define DAC_CR_TEN2_Msk (0x1U << DAC_CR_TEN2_Pos) /*!< 0x00040000 */
+#define DAC_CR_TEN2 DAC_CR_TEN2_Msk /*!< DAC channel2 Trigger enable */
+
+#define DAC_CR_TSEL2_Pos (19U)
+#define DAC_CR_TSEL2_Msk (0x7U << DAC_CR_TSEL2_Pos) /*!< 0x00380000 */
+#define DAC_CR_TSEL2 DAC_CR_TSEL2_Msk /*!< TSEL2[2:0] (DAC channel2 Trigger selection) */
+#define DAC_CR_TSEL2_0 (0x1U << DAC_CR_TSEL2_Pos) /*!< 0x00080000 */
+#define DAC_CR_TSEL2_1 (0x2U << DAC_CR_TSEL2_Pos) /*!< 0x00100000 */
+#define DAC_CR_TSEL2_2 (0x4U << DAC_CR_TSEL2_Pos) /*!< 0x00200000 */
+
+#define DAC_CR_WAVE2_Pos (22U)
+#define DAC_CR_WAVE2_Msk (0x3U << DAC_CR_WAVE2_Pos) /*!< 0x00C00000 */
+#define DAC_CR_WAVE2 DAC_CR_WAVE2_Msk /*!< WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
+#define DAC_CR_WAVE2_0 (0x1U << DAC_CR_WAVE2_Pos) /*!< 0x00400000 */
+#define DAC_CR_WAVE2_1 (0x2U << DAC_CR_WAVE2_Pos) /*!< 0x00800000 */
+
+#define DAC_CR_MAMP2_Pos (24U)
+#define DAC_CR_MAMP2_Msk (0xFU << DAC_CR_MAMP2_Pos) /*!< 0x0F000000 */
+#define DAC_CR_MAMP2 DAC_CR_MAMP2_Msk /*!< MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
+#define DAC_CR_MAMP2_0 (0x1U << DAC_CR_MAMP2_Pos) /*!< 0x01000000 */
+#define DAC_CR_MAMP2_1 (0x2U << DAC_CR_MAMP2_Pos) /*!< 0x02000000 */
+#define DAC_CR_MAMP2_2 (0x4U << DAC_CR_MAMP2_Pos) /*!< 0x04000000 */
+#define DAC_CR_MAMP2_3 (0x8U << DAC_CR_MAMP2_Pos) /*!< 0x08000000 */
+
+#define DAC_CR_DMAEN2_Pos (28U)
+#define DAC_CR_DMAEN2_Msk (0x1U << DAC_CR_DMAEN2_Pos) /*!< 0x10000000 */
+#define DAC_CR_DMAEN2 DAC_CR_DMAEN2_Msk /*!< DAC channel2 DMA enabled */
+
+
+/***************** Bit definition for DAC_SWTRIGR register ******************/
+#define DAC_SWTRIGR_SWTRIG1_Pos (0U)
+#define DAC_SWTRIGR_SWTRIG1_Msk (0x1U << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */
+#define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /*!< DAC channel1 software trigger */
+#define DAC_SWTRIGR_SWTRIG2_Pos (1U)
+#define DAC_SWTRIGR_SWTRIG2_Msk (0x1U << DAC_SWTRIGR_SWTRIG2_Pos) /*!< 0x00000002 */
+#define DAC_SWTRIGR_SWTRIG2 DAC_SWTRIGR_SWTRIG2_Msk /*!< DAC channel2 software trigger */
+
+/***************** Bit definition for DAC_DHR12R1 register ******************/
+#define DAC_DHR12R1_DACC1DHR_Pos (0U)
+#define DAC_DHR12R1_DACC1DHR_Msk (0xFFFU << DAC_DHR12R1_DACC1DHR_Pos) /*!< 0x00000FFF */
+#define DAC_DHR12R1_DACC1DHR DAC_DHR12R1_DACC1DHR_Msk /*!< DAC channel1 12-bit Right aligned data */
+
+/***************** Bit definition for DAC_DHR12L1 register ******************/
+#define DAC_DHR12L1_DACC1DHR_Pos (4U)
+#define DAC_DHR12L1_DACC1DHR_Msk (0xFFFU << DAC_DHR12L1_DACC1DHR_Pos) /*!< 0x0000FFF0 */
+#define DAC_DHR12L1_DACC1DHR DAC_DHR12L1_DACC1DHR_Msk /*!< DAC channel1 12-bit Left aligned data */
+
+/****************** Bit definition for DAC_DHR8R1 register ******************/
+#define DAC_DHR8R1_DACC1DHR_Pos (0U)
+#define DAC_DHR8R1_DACC1DHR_Msk (0xFFU << DAC_DHR8R1_DACC1DHR_Pos) /*!< 0x000000FF */
+#define DAC_DHR8R1_DACC1DHR DAC_DHR8R1_DACC1DHR_Msk /*!< DAC channel1 8-bit Right aligned data */
+
+/***************** Bit definition for DAC_DHR12R2 register ******************/
+#define DAC_DHR12R2_DACC2DHR_Pos (0U)
+#define DAC_DHR12R2_DACC2DHR_Msk (0xFFFU << DAC_DHR12R2_DACC2DHR_Pos) /*!< 0x00000FFF */
+#define DAC_DHR12R2_DACC2DHR DAC_DHR12R2_DACC2DHR_Msk /*!< DAC channel2 12-bit Right aligned data */
+
+/***************** Bit definition for DAC_DHR12L2 register ******************/
+#define DAC_DHR12L2_DACC2DHR_Pos (4U)
+#define DAC_DHR12L2_DACC2DHR_Msk (0xFFFU << DAC_DHR12L2_DACC2DHR_Pos) /*!< 0x0000FFF0 */
+#define DAC_DHR12L2_DACC2DHR DAC_DHR12L2_DACC2DHR_Msk /*!< DAC channel2 12-bit Left aligned data */
+
+/****************** Bit definition for DAC_DHR8R2 register ******************/
+#define DAC_DHR8R2_DACC2DHR_Pos (0U)
+#define DAC_DHR8R2_DACC2DHR_Msk (0xFFU << DAC_DHR8R2_DACC2DHR_Pos) /*!< 0x000000FF */
+#define DAC_DHR8R2_DACC2DHR DAC_DHR8R2_DACC2DHR_Msk /*!< DAC channel2 8-bit Right aligned data */
+
+/***************** Bit definition for DAC_DHR12RD register ******************/
+#define DAC_DHR12RD_DACC1DHR_Pos (0U)
+#define DAC_DHR12RD_DACC1DHR_Msk (0xFFFU << DAC_DHR12RD_DACC1DHR_Pos) /*!< 0x00000FFF */
+#define DAC_DHR12RD_DACC1DHR DAC_DHR12RD_DACC1DHR_Msk /*!< DAC channel1 12-bit Right aligned data */
+#define DAC_DHR12RD_DACC2DHR_Pos (16U)
+#define DAC_DHR12RD_DACC2DHR_Msk (0xFFFU << DAC_DHR12RD_DACC2DHR_Pos) /*!< 0x0FFF0000 */
+#define DAC_DHR12RD_DACC2DHR DAC_DHR12RD_DACC2DHR_Msk /*!< DAC channel2 12-bit Right aligned data */
+
+/***************** Bit definition for DAC_DHR12LD register ******************/
+#define DAC_DHR12LD_DACC1DHR_Pos (4U)
+#define DAC_DHR12LD_DACC1DHR_Msk (0xFFFU << DAC_DHR12LD_DACC1DHR_Pos) /*!< 0x0000FFF0 */
+#define DAC_DHR12LD_DACC1DHR DAC_DHR12LD_DACC1DHR_Msk /*!< DAC channel1 12-bit Left aligned data */
+#define DAC_DHR12LD_DACC2DHR_Pos (20U)
+#define DAC_DHR12LD_DACC2DHR_Msk (0xFFFU << DAC_DHR12LD_DACC2DHR_Pos) /*!< 0xFFF00000 */
+#define DAC_DHR12LD_DACC2DHR DAC_DHR12LD_DACC2DHR_Msk /*!< DAC channel2 12-bit Left aligned data */
+
+/****************** Bit definition for DAC_DHR8RD register ******************/
+#define DAC_DHR8RD_DACC1DHR_Pos (0U)
+#define DAC_DHR8RD_DACC1DHR_Msk (0xFFU << DAC_DHR8RD_DACC1DHR_Pos) /*!< 0x000000FF */
+#define DAC_DHR8RD_DACC1DHR DAC_DHR8RD_DACC1DHR_Msk /*!< DAC channel1 8-bit Right aligned data */
+#define DAC_DHR8RD_DACC2DHR_Pos (8U)
+#define DAC_DHR8RD_DACC2DHR_Msk (0xFFU << DAC_DHR8RD_DACC2DHR_Pos) /*!< 0x0000FF00 */
+#define DAC_DHR8RD_DACC2DHR DAC_DHR8RD_DACC2DHR_Msk /*!< DAC channel2 8-bit Right aligned data */
+
+/******************* Bit definition for DAC_DOR1 register *******************/
+#define DAC_DOR1_DACC1DOR_Pos (0U)
+#define DAC_DOR1_DACC1DOR_Msk (0xFFFU << DAC_DOR1_DACC1DOR_Pos) /*!< 0x00000FFF */
+#define DAC_DOR1_DACC1DOR DAC_DOR1_DACC1DOR_Msk /*!< DAC channel1 data output */
+
+/******************* Bit definition for DAC_DOR2 register *******************/
+#define DAC_DOR2_DACC2DOR_Pos (0U)
+#define DAC_DOR2_DACC2DOR_Msk (0xFFFU << DAC_DOR2_DACC2DOR_Pos) /*!< 0x00000FFF */
+#define DAC_DOR2_DACC2DOR DAC_DOR2_DACC2DOR_Msk /*!< DAC channel2 data output */
+
+
+
+/*****************************************************************************/
+/* */
+/* Timers (TIM) */
+/* */
+/*****************************************************************************/
+/******************* Bit definition for TIM_CR1 register *******************/
+#define TIM_CR1_CEN_Pos (0U)
+#define TIM_CR1_CEN_Msk (0x1U << TIM_CR1_CEN_Pos) /*!< 0x00000001 */
+#define TIM_CR1_CEN TIM_CR1_CEN_Msk /*!<Counter enable */
+#define TIM_CR1_UDIS_Pos (1U)
+#define TIM_CR1_UDIS_Msk (0x1U << TIM_CR1_UDIS_Pos) /*!< 0x00000002 */
+#define TIM_CR1_UDIS TIM_CR1_UDIS_Msk /*!<Update disable */
+#define TIM_CR1_URS_Pos (2U)
+#define TIM_CR1_URS_Msk (0x1U << TIM_CR1_URS_Pos) /*!< 0x00000004 */
+#define TIM_CR1_URS TIM_CR1_URS_Msk /*!<Update request source */
+#define TIM_CR1_OPM_Pos (3U)
+#define TIM_CR1_OPM_Msk (0x1U << TIM_CR1_OPM_Pos) /*!< 0x00000008 */
+#define TIM_CR1_OPM TIM_CR1_OPM_Msk /*!<One pulse mode */
+#define TIM_CR1_DIR_Pos (4U)
+#define TIM_CR1_DIR_Msk (0x1U << TIM_CR1_DIR_Pos) /*!< 0x00000010 */
+#define TIM_CR1_DIR TIM_CR1_DIR_Msk /*!<Direction */
+
+#define TIM_CR1_CMS_Pos (5U)
+#define TIM_CR1_CMS_Msk (0x3U << TIM_CR1_CMS_Pos) /*!< 0x00000060 */
+#define TIM_CR1_CMS TIM_CR1_CMS_Msk /*!<CMS[1:0] bits (Center-aligned mode selection) */
+#define TIM_CR1_CMS_0 (0x1U << TIM_CR1_CMS_Pos) /*!< 0x00000020 */
+#define TIM_CR1_CMS_1 (0x2U << TIM_CR1_CMS_Pos) /*!< 0x00000040 */
+
+#define TIM_CR1_ARPE_Pos (7U)
+#define TIM_CR1_ARPE_Msk (0x1U << TIM_CR1_ARPE_Pos) /*!< 0x00000080 */
+#define TIM_CR1_ARPE TIM_CR1_ARPE_Msk /*!<Auto-reload preload enable */
+
+#define TIM_CR1_CKD_Pos (8U)
+#define TIM_CR1_CKD_Msk (0x3U << TIM_CR1_CKD_Pos) /*!< 0x00000300 */
+#define TIM_CR1_CKD TIM_CR1_CKD_Msk /*!<CKD[1:0] bits (clock division) */
+#define TIM_CR1_CKD_0 (0x1U << TIM_CR1_CKD_Pos) /*!< 0x00000100 */
+#define TIM_CR1_CKD_1 (0x2U << TIM_CR1_CKD_Pos) /*!< 0x00000200 */
+
+/******************* Bit definition for TIM_CR2 register *******************/
+#define TIM_CR2_CCPC_Pos (0U)
+#define TIM_CR2_CCPC_Msk (0x1U << TIM_CR2_CCPC_Pos) /*!< 0x00000001 */
+#define TIM_CR2_CCPC TIM_CR2_CCPC_Msk /*!<Capture/Compare Preloaded Control */
+#define TIM_CR2_CCUS_Pos (2U)
+#define TIM_CR2_CCUS_Msk (0x1U << TIM_CR2_CCUS_Pos) /*!< 0x00000004 */
+#define TIM_CR2_CCUS TIM_CR2_CCUS_Msk /*!<Capture/Compare Control Update Selection */
+#define TIM_CR2_CCDS_Pos (3U)
+#define TIM_CR2_CCDS_Msk (0x1U << TIM_CR2_CCDS_Pos) /*!< 0x00000008 */
+#define TIM_CR2_CCDS TIM_CR2_CCDS_Msk /*!<Capture/Compare DMA Selection */
+
+#define TIM_CR2_MMS_Pos (4U)
+#define TIM_CR2_MMS_Msk (0x7U << TIM_CR2_MMS_Pos) /*!< 0x00000070 */
+#define TIM_CR2_MMS TIM_CR2_MMS_Msk /*!<MMS[2:0] bits (Master Mode Selection) */
+#define TIM_CR2_MMS_0 (0x1U << TIM_CR2_MMS_Pos) /*!< 0x00000010 */
+#define TIM_CR2_MMS_1 (0x2U << TIM_CR2_MMS_Pos) /*!< 0x00000020 */
+#define TIM_CR2_MMS_2 (0x4U << TIM_CR2_MMS_Pos) /*!< 0x00000040 */
+
+#define TIM_CR2_TI1S_Pos (7U)
+#define TIM_CR2_TI1S_Msk (0x1U << TIM_CR2_TI1S_Pos) /*!< 0x00000080 */
+#define TIM_CR2_TI1S TIM_CR2_TI1S_Msk /*!<TI1 Selection */
+#define TIM_CR2_OIS1_Pos (8U)
+#define TIM_CR2_OIS1_Msk (0x1U << TIM_CR2_OIS1_Pos) /*!< 0x00000100 */
+#define TIM_CR2_OIS1 TIM_CR2_OIS1_Msk /*!<Output Idle state 1 (OC1 output) */
+#define TIM_CR2_OIS1N_Pos (9U)
+#define TIM_CR2_OIS1N_Msk (0x1U << TIM_CR2_OIS1N_Pos) /*!< 0x00000200 */
+#define TIM_CR2_OIS1N TIM_CR2_OIS1N_Msk /*!<Output Idle state 1 (OC1N output) */
+#define TIM_CR2_OIS2_Pos (10U)
+#define TIM_CR2_OIS2_Msk (0x1U << TIM_CR2_OIS2_Pos) /*!< 0x00000400 */
+#define TIM_CR2_OIS2 TIM_CR2_OIS2_Msk /*!<Output Idle state 2 (OC2 output) */
+#define TIM_CR2_OIS2N_Pos (11U)
+#define TIM_CR2_OIS2N_Msk (0x1U << TIM_CR2_OIS2N_Pos) /*!< 0x00000800 */
+#define TIM_CR2_OIS2N TIM_CR2_OIS2N_Msk /*!<Output Idle state 2 (OC2N output) */
+#define TIM_CR2_OIS3_Pos (12U)
+#define TIM_CR2_OIS3_Msk (0x1U << TIM_CR2_OIS3_Pos) /*!< 0x00001000 */
+#define TIM_CR2_OIS3 TIM_CR2_OIS3_Msk /*!<Output Idle state 3 (OC3 output) */
+#define TIM_CR2_OIS3N_Pos (13U)
+#define TIM_CR2_OIS3N_Msk (0x1U << TIM_CR2_OIS3N_Pos) /*!< 0x00002000 */
+#define TIM_CR2_OIS3N TIM_CR2_OIS3N_Msk /*!<Output Idle state 3 (OC3N output) */
+#define TIM_CR2_OIS4_Pos (14U)
+#define TIM_CR2_OIS4_Msk (0x1U << TIM_CR2_OIS4_Pos) /*!< 0x00004000 */
+#define TIM_CR2_OIS4 TIM_CR2_OIS4_Msk /*!<Output Idle state 4 (OC4 output) */
+
+/******************* Bit definition for TIM_SMCR register ******************/
+#define TIM_SMCR_SMS_Pos (0U)
+#define TIM_SMCR_SMS_Msk (0x7U << TIM_SMCR_SMS_Pos) /*!< 0x00000007 */
+#define TIM_SMCR_SMS TIM_SMCR_SMS_Msk /*!<SMS[2:0] bits (Slave mode selection) */
+#define TIM_SMCR_SMS_0 (0x1U << TIM_SMCR_SMS_Pos) /*!< 0x00000001 */
+#define TIM_SMCR_SMS_1 (0x2U << TIM_SMCR_SMS_Pos) /*!< 0x00000002 */
+#define TIM_SMCR_SMS_2 (0x4U << TIM_SMCR_SMS_Pos) /*!< 0x00000004 */
+
+#define TIM_SMCR_OCCS_Pos (3U)
+#define TIM_SMCR_OCCS_Msk (0x1U << TIM_SMCR_OCCS_Pos) /*!< 0x00000008 */
+#define TIM_SMCR_OCCS TIM_SMCR_OCCS_Msk /*!< OCREF clear selection */
+
+#define TIM_SMCR_TS_Pos (4U)
+#define TIM_SMCR_TS_Msk (0x7U << TIM_SMCR_TS_Pos) /*!< 0x00000070 */
+#define TIM_SMCR_TS TIM_SMCR_TS_Msk /*!<TS[2:0] bits (Trigger selection) */
+#define TIM_SMCR_TS_0 (0x1U << TIM_SMCR_TS_Pos) /*!< 0x00000010 */
+#define TIM_SMCR_TS_1 (0x2U << TIM_SMCR_TS_Pos) /*!< 0x00000020 */
+#define TIM_SMCR_TS_2 (0x4U << TIM_SMCR_TS_Pos) /*!< 0x00000040 */
+
+#define TIM_SMCR_MSM_Pos (7U)
+#define TIM_SMCR_MSM_Msk (0x1U << TIM_SMCR_MSM_Pos) /*!< 0x00000080 */
+#define TIM_SMCR_MSM TIM_SMCR_MSM_Msk /*!<Master/slave mode */
+
+#define TIM_SMCR_ETF_Pos (8U)
+#define TIM_SMCR_ETF_Msk (0xFU << TIM_SMCR_ETF_Pos) /*!< 0x00000F00 */
+#define TIM_SMCR_ETF TIM_SMCR_ETF_Msk /*!<ETF[3:0] bits (External trigger filter) */
+#define TIM_SMCR_ETF_0 (0x1U << TIM_SMCR_ETF_Pos) /*!< 0x00000100 */
+#define TIM_SMCR_ETF_1 (0x2U << TIM_SMCR_ETF_Pos) /*!< 0x00000200 */
+#define TIM_SMCR_ETF_2 (0x4U << TIM_SMCR_ETF_Pos) /*!< 0x00000400 */
+#define TIM_SMCR_ETF_3 (0x8U << TIM_SMCR_ETF_Pos) /*!< 0x00000800 */
+
+#define TIM_SMCR_ETPS_Pos (12U)
+#define TIM_SMCR_ETPS_Msk (0x3U << TIM_SMCR_ETPS_Pos) /*!< 0x00003000 */
+#define TIM_SMCR_ETPS TIM_SMCR_ETPS_Msk /*!<ETPS[1:0] bits (External trigger prescaler) */
+#define TIM_SMCR_ETPS_0 (0x1U << TIM_SMCR_ETPS_Pos) /*!< 0x00001000 */
+#define TIM_SMCR_ETPS_1 (0x2U << TIM_SMCR_ETPS_Pos) /*!< 0x00002000 */
+
+#define TIM_SMCR_ECE_Pos (14U)
+#define TIM_SMCR_ECE_Msk (0x1U << TIM_SMCR_ECE_Pos) /*!< 0x00004000 */
+#define TIM_SMCR_ECE TIM_SMCR_ECE_Msk /*!<External clock enable */
+#define TIM_SMCR_ETP_Pos (15U)
+#define TIM_SMCR_ETP_Msk (0x1U << TIM_SMCR_ETP_Pos) /*!< 0x00008000 */
+#define TIM_SMCR_ETP TIM_SMCR_ETP_Msk /*!<External trigger polarity */
+
+/******************* Bit definition for TIM_DIER register ******************/
+#define TIM_DIER_UIE_Pos (0U)
+#define TIM_DIER_UIE_Msk (0x1U << TIM_DIER_UIE_Pos) /*!< 0x00000001 */
+#define TIM_DIER_UIE TIM_DIER_UIE_Msk /*!<Update interrupt enable */
+#define TIM_DIER_CC1IE_Pos (1U)
+#define TIM_DIER_CC1IE_Msk (0x1U << TIM_DIER_CC1IE_Pos) /*!< 0x00000002 */
+#define TIM_DIER_CC1IE TIM_DIER_CC1IE_Msk /*!<Capture/Compare 1 interrupt enable */
+#define TIM_DIER_CC2IE_Pos (2U)
+#define TIM_DIER_CC2IE_Msk (0x1U << TIM_DIER_CC2IE_Pos) /*!< 0x00000004 */
+#define TIM_DIER_CC2IE TIM_DIER_CC2IE_Msk /*!<Capture/Compare 2 interrupt enable */
+#define TIM_DIER_CC3IE_Pos (3U)
+#define TIM_DIER_CC3IE_Msk (0x1U << TIM_DIER_CC3IE_Pos) /*!< 0x00000008 */
+#define TIM_DIER_CC3IE TIM_DIER_CC3IE_Msk /*!<Capture/Compare 3 interrupt enable */
+#define TIM_DIER_CC4IE_Pos (4U)
+#define TIM_DIER_CC4IE_Msk (0x1U << TIM_DIER_CC4IE_Pos) /*!< 0x00000010 */
+#define TIM_DIER_CC4IE TIM_DIER_CC4IE_Msk /*!<Capture/Compare 4 interrupt enable */
+#define TIM_DIER_COMIE_Pos (5U)
+#define TIM_DIER_COMIE_Msk (0x1U << TIM_DIER_COMIE_Pos) /*!< 0x00000020 */
+#define TIM_DIER_COMIE TIM_DIER_COMIE_Msk /*!<COM interrupt enable */
+#define TIM_DIER_TIE_Pos (6U)
+#define TIM_DIER_TIE_Msk (0x1U << TIM_DIER_TIE_Pos) /*!< 0x00000040 */
+#define TIM_DIER_TIE TIM_DIER_TIE_Msk /*!<Trigger interrupt enable */
+#define TIM_DIER_BIE_Pos (7U)
+#define TIM_DIER_BIE_Msk (0x1U << TIM_DIER_BIE_Pos) /*!< 0x00000080 */
+#define TIM_DIER_BIE TIM_DIER_BIE_Msk /*!<Break interrupt enable */
+#define TIM_DIER_UDE_Pos (8U)
+#define TIM_DIER_UDE_Msk (0x1U << TIM_DIER_UDE_Pos) /*!< 0x00000100 */
+#define TIM_DIER_UDE TIM_DIER_UDE_Msk /*!<Update DMA request enable */
+#define TIM_DIER_CC1DE_Pos (9U)
+#define TIM_DIER_CC1DE_Msk (0x1U << TIM_DIER_CC1DE_Pos) /*!< 0x00000200 */
+#define TIM_DIER_CC1DE TIM_DIER_CC1DE_Msk /*!<Capture/Compare 1 DMA request enable */
+#define TIM_DIER_CC2DE_Pos (10U)
+#define TIM_DIER_CC2DE_Msk (0x1U << TIM_DIER_CC2DE_Pos) /*!< 0x00000400 */
+#define TIM_DIER_CC2DE TIM_DIER_CC2DE_Msk /*!<Capture/Compare 2 DMA request enable */
+#define TIM_DIER_CC3DE_Pos (11U)
+#define TIM_DIER_CC3DE_Msk (0x1U << TIM_DIER_CC3DE_Pos) /*!< 0x00000800 */
+#define TIM_DIER_CC3DE TIM_DIER_CC3DE_Msk /*!<Capture/Compare 3 DMA request enable */
+#define TIM_DIER_CC4DE_Pos (12U)
+#define TIM_DIER_CC4DE_Msk (0x1U << TIM_DIER_CC4DE_Pos) /*!< 0x00001000 */
+#define TIM_DIER_CC4DE TIM_DIER_CC4DE_Msk /*!<Capture/Compare 4 DMA request enable */
+#define TIM_DIER_COMDE_Pos (13U)
+#define TIM_DIER_COMDE_Msk (0x1U << TIM_DIER_COMDE_Pos) /*!< 0x00002000 */
+#define TIM_DIER_COMDE TIM_DIER_COMDE_Msk /*!<COM DMA request enable */
+#define TIM_DIER_TDE_Pos (14U)
+#define TIM_DIER_TDE_Msk (0x1U << TIM_DIER_TDE_Pos) /*!< 0x00004000 */
+#define TIM_DIER_TDE TIM_DIER_TDE_Msk /*!<Trigger DMA request enable */
+
+/******************** Bit definition for TIM_SR register *******************/
+#define TIM_SR_UIF_Pos (0U)
+#define TIM_SR_UIF_Msk (0x1U << TIM_SR_UIF_Pos) /*!< 0x00000001 */
+#define TIM_SR_UIF TIM_SR_UIF_Msk /*!<Update interrupt Flag */
+#define TIM_SR_CC1IF_Pos (1U)
+#define TIM_SR_CC1IF_Msk (0x1U << TIM_SR_CC1IF_Pos) /*!< 0x00000002 */
+#define TIM_SR_CC1IF TIM_SR_CC1IF_Msk /*!<Capture/Compare 1 interrupt Flag */
+#define TIM_SR_CC2IF_Pos (2U)
+#define TIM_SR_CC2IF_Msk (0x1U << TIM_SR_CC2IF_Pos) /*!< 0x00000004 */
+#define TIM_SR_CC2IF TIM_SR_CC2IF_Msk /*!<Capture/Compare 2 interrupt Flag */
+#define TIM_SR_CC3IF_Pos (3U)
+#define TIM_SR_CC3IF_Msk (0x1U << TIM_SR_CC3IF_Pos) /*!< 0x00000008 */
+#define TIM_SR_CC3IF TIM_SR_CC3IF_Msk /*!<Capture/Compare 3 interrupt Flag */
+#define TIM_SR_CC4IF_Pos (4U)
+#define TIM_SR_CC4IF_Msk (0x1U << TIM_SR_CC4IF_Pos) /*!< 0x00000010 */
+#define TIM_SR_CC4IF TIM_SR_CC4IF_Msk /*!<Capture/Compare 4 interrupt Flag */
+#define TIM_SR_COMIF_Pos (5U)
+#define TIM_SR_COMIF_Msk (0x1U << TIM_SR_COMIF_Pos) /*!< 0x00000020 */
+#define TIM_SR_COMIF TIM_SR_COMIF_Msk /*!<COM interrupt Flag */
+#define TIM_SR_TIF_Pos (6U)
+#define TIM_SR_TIF_Msk (0x1U << TIM_SR_TIF_Pos) /*!< 0x00000040 */
+#define TIM_SR_TIF TIM_SR_TIF_Msk /*!<Trigger interrupt Flag */
+#define TIM_SR_BIF_Pos (7U)
+#define TIM_SR_BIF_Msk (0x1U << TIM_SR_BIF_Pos) /*!< 0x00000080 */
+#define TIM_SR_BIF TIM_SR_BIF_Msk /*!<Break interrupt Flag */
+#define TIM_SR_CC1OF_Pos (9U)
+#define TIM_SR_CC1OF_Msk (0x1U << TIM_SR_CC1OF_Pos) /*!< 0x00000200 */
+#define TIM_SR_CC1OF TIM_SR_CC1OF_Msk /*!<Capture/Compare 1 Overcapture Flag */
+#define TIM_SR_CC2OF_Pos (10U)
+#define TIM_SR_CC2OF_Msk (0x1U << TIM_SR_CC2OF_Pos) /*!< 0x00000400 */
+#define TIM_SR_CC2OF TIM_SR_CC2OF_Msk /*!<Capture/Compare 2 Overcapture Flag */
+#define TIM_SR_CC3OF_Pos (11U)
+#define TIM_SR_CC3OF_Msk (0x1U << TIM_SR_CC3OF_Pos) /*!< 0x00000800 */
+#define TIM_SR_CC3OF TIM_SR_CC3OF_Msk /*!<Capture/Compare 3 Overcapture Flag */
+#define TIM_SR_CC4OF_Pos (12U)
+#define TIM_SR_CC4OF_Msk (0x1U << TIM_SR_CC4OF_Pos) /*!< 0x00001000 */
+#define TIM_SR_CC4OF TIM_SR_CC4OF_Msk /*!<Capture/Compare 4 Overcapture Flag */
+
+/******************* Bit definition for TIM_EGR register *******************/
+#define TIM_EGR_UG_Pos (0U)
+#define TIM_EGR_UG_Msk (0x1U << TIM_EGR_UG_Pos) /*!< 0x00000001 */
+#define TIM_EGR_UG TIM_EGR_UG_Msk /*!<Update Generation */
+#define TIM_EGR_CC1G_Pos (1U)
+#define TIM_EGR_CC1G_Msk (0x1U << TIM_EGR_CC1G_Pos) /*!< 0x00000002 */
+#define TIM_EGR_CC1G TIM_EGR_CC1G_Msk /*!<Capture/Compare 1 Generation */
+#define TIM_EGR_CC2G_Pos (2U)
+#define TIM_EGR_CC2G_Msk (0x1U << TIM_EGR_CC2G_Pos) /*!< 0x00000004 */
+#define TIM_EGR_CC2G TIM_EGR_CC2G_Msk /*!<Capture/Compare 2 Generation */
+#define TIM_EGR_CC3G_Pos (3U)
+#define TIM_EGR_CC3G_Msk (0x1U << TIM_EGR_CC3G_Pos) /*!< 0x00000008 */
+#define TIM_EGR_CC3G TIM_EGR_CC3G_Msk /*!<Capture/Compare 3 Generation */
+#define TIM_EGR_CC4G_Pos (4U)
+#define TIM_EGR_CC4G_Msk (0x1U << TIM_EGR_CC4G_Pos) /*!< 0x00000010 */
+#define TIM_EGR_CC4G TIM_EGR_CC4G_Msk /*!<Capture/Compare 4 Generation */
+#define TIM_EGR_COMG_Pos (5U)
+#define TIM_EGR_COMG_Msk (0x1U << TIM_EGR_COMG_Pos) /*!< 0x00000020 */
+#define TIM_EGR_COMG TIM_EGR_COMG_Msk /*!<Capture/Compare Control Update Generation */
+#define TIM_EGR_TG_Pos (6U)
+#define TIM_EGR_TG_Msk (0x1U << TIM_EGR_TG_Pos) /*!< 0x00000040 */
+#define TIM_EGR_TG TIM_EGR_TG_Msk /*!<Trigger Generation */
+#define TIM_EGR_BG_Pos (7U)
+#define TIM_EGR_BG_Msk (0x1U << TIM_EGR_BG_Pos) /*!< 0x00000080 */
+#define TIM_EGR_BG TIM_EGR_BG_Msk /*!<Break Generation */
+
+/****************** Bit definition for TIM_CCMR1 register ******************/
+#define TIM_CCMR1_CC1S_Pos (0U)
+#define TIM_CCMR1_CC1S_Msk (0x3U << TIM_CCMR1_CC1S_Pos) /*!< 0x00000003 */
+#define TIM_CCMR1_CC1S TIM_CCMR1_CC1S_Msk /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
+#define TIM_CCMR1_CC1S_0 (0x1U << TIM_CCMR1_CC1S_Pos) /*!< 0x00000001 */
+#define TIM_CCMR1_CC1S_1 (0x2U << TIM_CCMR1_CC1S_Pos) /*!< 0x00000002 */
+
+#define TIM_CCMR1_OC1FE_Pos (2U)
+#define TIM_CCMR1_OC1FE_Msk (0x1U << TIM_CCMR1_OC1FE_Pos) /*!< 0x00000004 */
+#define TIM_CCMR1_OC1FE TIM_CCMR1_OC1FE_Msk /*!<Output Compare 1 Fast enable */
+#define TIM_CCMR1_OC1PE_Pos (3U)
+#define TIM_CCMR1_OC1PE_Msk (0x1U << TIM_CCMR1_OC1PE_Pos) /*!< 0x00000008 */
+#define TIM_CCMR1_OC1PE TIM_CCMR1_OC1PE_Msk /*!<Output Compare 1 Preload enable */
+
+#define TIM_CCMR1_OC1M_Pos (4U)
+#define TIM_CCMR1_OC1M_Msk (0x7U << TIM_CCMR1_OC1M_Pos) /*!< 0x00000070 */
+#define TIM_CCMR1_OC1M TIM_CCMR1_OC1M_Msk /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
+#define TIM_CCMR1_OC1M_0 (0x1U << TIM_CCMR1_OC1M_Pos) /*!< 0x00000010 */
+#define TIM_CCMR1_OC1M_1 (0x2U << TIM_CCMR1_OC1M_Pos) /*!< 0x00000020 */
+#define TIM_CCMR1_OC1M_2 (0x4U << TIM_CCMR1_OC1M_Pos) /*!< 0x00000040 */
+
+#define TIM_CCMR1_OC1CE_Pos (7U)
+#define TIM_CCMR1_OC1CE_Msk (0x1U << TIM_CCMR1_OC1CE_Pos) /*!< 0x00000080 */
+#define TIM_CCMR1_OC1CE TIM_CCMR1_OC1CE_Msk /*!<Output Compare 1Clear Enable */
+
+#define TIM_CCMR1_CC2S_Pos (8U)
+#define TIM_CCMR1_CC2S_Msk (0x3U << TIM_CCMR1_CC2S_Pos) /*!< 0x00000300 */
+#define TIM_CCMR1_CC2S TIM_CCMR1_CC2S_Msk /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
+#define TIM_CCMR1_CC2S_0 (0x1U << TIM_CCMR1_CC2S_Pos) /*!< 0x00000100 */
+#define TIM_CCMR1_CC2S_1 (0x2U << TIM_CCMR1_CC2S_Pos) /*!< 0x00000200 */
+
+#define TIM_CCMR1_OC2FE_Pos (10U)
+#define TIM_CCMR1_OC2FE_Msk (0x1U << TIM_CCMR1_OC2FE_Pos) /*!< 0x00000400 */
+#define TIM_CCMR1_OC2FE TIM_CCMR1_OC2FE_Msk /*!<Output Compare 2 Fast enable */
+#define TIM_CCMR1_OC2PE_Pos (11U)
+#define TIM_CCMR1_OC2PE_Msk (0x1U << TIM_CCMR1_OC2PE_Pos) /*!< 0x00000800 */
+#define TIM_CCMR1_OC2PE TIM_CCMR1_OC2PE_Msk /*!<Output Compare 2 Preload enable */
+
+#define TIM_CCMR1_OC2M_Pos (12U)
+#define TIM_CCMR1_OC2M_Msk (0x7U << TIM_CCMR1_OC2M_Pos) /*!< 0x00007000 */
+#define TIM_CCMR1_OC2M TIM_CCMR1_OC2M_Msk /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
+#define TIM_CCMR1_OC2M_0 (0x1U << TIM_CCMR1_OC2M_Pos) /*!< 0x00001000 */
+#define TIM_CCMR1_OC2M_1 (0x2U << TIM_CCMR1_OC2M_Pos) /*!< 0x00002000 */
+#define TIM_CCMR1_OC2M_2 (0x4U << TIM_CCMR1_OC2M_Pos) /*!< 0x00004000 */
+
+#define TIM_CCMR1_OC2CE_Pos (15U)
+#define TIM_CCMR1_OC2CE_Msk (0x1U << TIM_CCMR1_OC2CE_Pos) /*!< 0x00008000 */
+#define TIM_CCMR1_OC2CE TIM_CCMR1_OC2CE_Msk /*!<Output Compare 2 Clear Enable */
+
+/*---------------------------------------------------------------------------*/
+
+#define TIM_CCMR1_IC1PSC_Pos (2U)
+#define TIM_CCMR1_IC1PSC_Msk (0x3U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x0000000C */
+#define TIM_CCMR1_IC1PSC TIM_CCMR1_IC1PSC_Msk /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
+#define TIM_CCMR1_IC1PSC_0 (0x1U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x00000004 */
+#define TIM_CCMR1_IC1PSC_1 (0x2U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x00000008 */
+
+#define TIM_CCMR1_IC1F_Pos (4U)
+#define TIM_CCMR1_IC1F_Msk (0xFU << TIM_CCMR1_IC1F_Pos) /*!< 0x000000F0 */
+#define TIM_CCMR1_IC1F TIM_CCMR1_IC1F_Msk /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
+#define TIM_CCMR1_IC1F_0 (0x1U << TIM_CCMR1_IC1F_Pos) /*!< 0x00000010 */
+#define TIM_CCMR1_IC1F_1 (0x2U << TIM_CCMR1_IC1F_Pos) /*!< 0x00000020 */
+#define TIM_CCMR1_IC1F_2 (0x4U << TIM_CCMR1_IC1F_Pos) /*!< 0x00000040 */
+#define TIM_CCMR1_IC1F_3 (0x8U << TIM_CCMR1_IC1F_Pos) /*!< 0x00000080 */
+
+#define TIM_CCMR1_IC2PSC_Pos (10U)
+#define TIM_CCMR1_IC2PSC_Msk (0x3U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000C00 */
+#define TIM_CCMR1_IC2PSC TIM_CCMR1_IC2PSC_Msk /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
+#define TIM_CCMR1_IC2PSC_0 (0x1U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000400 */
+#define TIM_CCMR1_IC2PSC_1 (0x2U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000800 */
+
+#define TIM_CCMR1_IC2F_Pos (12U)
+#define TIM_CCMR1_IC2F_Msk (0xFU << TIM_CCMR1_IC2F_Pos) /*!< 0x0000F000 */
+#define TIM_CCMR1_IC2F TIM_CCMR1_IC2F_Msk /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
+#define TIM_CCMR1_IC2F_0 (0x1U << TIM_CCMR1_IC2F_Pos) /*!< 0x00001000 */
+#define TIM_CCMR1_IC2F_1 (0x2U << TIM_CCMR1_IC2F_Pos) /*!< 0x00002000 */
+#define TIM_CCMR1_IC2F_2 (0x4U << TIM_CCMR1_IC2F_Pos) /*!< 0x00004000 */
+#define TIM_CCMR1_IC2F_3 (0x8U << TIM_CCMR1_IC2F_Pos) /*!< 0x00008000 */
+
+/****************** Bit definition for TIM_CCMR2 register ******************/
+#define TIM_CCMR2_CC3S_Pos (0U)
+#define TIM_CCMR2_CC3S_Msk (0x3U << TIM_CCMR2_CC3S_Pos) /*!< 0x00000003 */
+#define TIM_CCMR2_CC3S TIM_CCMR2_CC3S_Msk /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
+#define TIM_CCMR2_CC3S_0 (0x1U << TIM_CCMR2_CC3S_Pos) /*!< 0x00000001 */
+#define TIM_CCMR2_CC3S_1 (0x2U << TIM_CCMR2_CC3S_Pos) /*!< 0x00000002 */
+
+#define TIM_CCMR2_OC3FE_Pos (2U)
+#define TIM_CCMR2_OC3FE_Msk (0x1U << TIM_CCMR2_OC3FE_Pos) /*!< 0x00000004 */
+#define TIM_CCMR2_OC3FE TIM_CCMR2_OC3FE_Msk /*!<Output Compare 3 Fast enable */
+#define TIM_CCMR2_OC3PE_Pos (3U)
+#define TIM_CCMR2_OC3PE_Msk (0x1U << TIM_CCMR2_OC3PE_Pos) /*!< 0x00000008 */
+#define TIM_CCMR2_OC3PE TIM_CCMR2_OC3PE_Msk /*!<Output Compare 3 Preload enable */
+
+#define TIM_CCMR2_OC3M_Pos (4U)
+#define TIM_CCMR2_OC3M_Msk (0x7U << TIM_CCMR2_OC3M_Pos) /*!< 0x00000070 */
+#define TIM_CCMR2_OC3M TIM_CCMR2_OC3M_Msk /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
+#define TIM_CCMR2_OC3M_0 (0x1U << TIM_CCMR2_OC3M_Pos) /*!< 0x00000010 */
+#define TIM_CCMR2_OC3M_1 (0x2U << TIM_CCMR2_OC3M_Pos) /*!< 0x00000020 */
+#define TIM_CCMR2_OC3M_2 (0x4U << TIM_CCMR2_OC3M_Pos) /*!< 0x00000040 */
+
+#define TIM_CCMR2_OC3CE_Pos (7U)
+#define TIM_CCMR2_OC3CE_Msk (0x1U << TIM_CCMR2_OC3CE_Pos) /*!< 0x00000080 */
+#define TIM_CCMR2_OC3CE TIM_CCMR2_OC3CE_Msk /*!<Output Compare 3 Clear Enable */
+
+#define TIM_CCMR2_CC4S_Pos (8U)
+#define TIM_CCMR2_CC4S_Msk (0x3U << TIM_CCMR2_CC4S_Pos) /*!< 0x00000300 */
+#define TIM_CCMR2_CC4S TIM_CCMR2_CC4S_Msk /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
+#define TIM_CCMR2_CC4S_0 (0x1U << TIM_CCMR2_CC4S_Pos) /*!< 0x00000100 */
+#define TIM_CCMR2_CC4S_1 (0x2U << TIM_CCMR2_CC4S_Pos) /*!< 0x00000200 */
+
+#define TIM_CCMR2_OC4FE_Pos (10U)
+#define TIM_CCMR2_OC4FE_Msk (0x1U << TIM_CCMR2_OC4FE_Pos) /*!< 0x00000400 */
+#define TIM_CCMR2_OC4FE TIM_CCMR2_OC4FE_Msk /*!<Output Compare 4 Fast enable */
+#define TIM_CCMR2_OC4PE_Pos (11U)
+#define TIM_CCMR2_OC4PE_Msk (0x1U << TIM_CCMR2_OC4PE_Pos) /*!< 0x00000800 */
+#define TIM_CCMR2_OC4PE TIM_CCMR2_OC4PE_Msk /*!<Output Compare 4 Preload enable */
+
+#define TIM_CCMR2_OC4M_Pos (12U)
+#define TIM_CCMR2_OC4M_Msk (0x7U << TIM_CCMR2_OC4M_Pos) /*!< 0x00007000 */
+#define TIM_CCMR2_OC4M TIM_CCMR2_OC4M_Msk /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
+#define TIM_CCMR2_OC4M_0 (0x1U << TIM_CCMR2_OC4M_Pos) /*!< 0x00001000 */
+#define TIM_CCMR2_OC4M_1 (0x2U << TIM_CCMR2_OC4M_Pos) /*!< 0x00002000 */
+#define TIM_CCMR2_OC4M_2 (0x4U << TIM_CCMR2_OC4M_Pos) /*!< 0x00004000 */
+
+#define TIM_CCMR2_OC4CE_Pos (15U)
+#define TIM_CCMR2_OC4CE_Msk (0x1U << TIM_CCMR2_OC4CE_Pos) /*!< 0x00008000 */
+#define TIM_CCMR2_OC4CE TIM_CCMR2_OC4CE_Msk /*!<Output Compare 4 Clear Enable */
+
+/*---------------------------------------------------------------------------*/
+
+#define TIM_CCMR2_IC3PSC_Pos (2U)
+#define TIM_CCMR2_IC3PSC_Msk (0x3U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x0000000C */
+#define TIM_CCMR2_IC3PSC TIM_CCMR2_IC3PSC_Msk /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
+#define TIM_CCMR2_IC3PSC_0 (0x1U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x00000004 */
+#define TIM_CCMR2_IC3PSC_1 (0x2U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x00000008 */
+
+#define TIM_CCMR2_IC3F_Pos (4U)
+#define TIM_CCMR2_IC3F_Msk (0xFU << TIM_CCMR2_IC3F_Pos) /*!< 0x000000F0 */
+#define TIM_CCMR2_IC3F TIM_CCMR2_IC3F_Msk /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
+#define TIM_CCMR2_IC3F_0 (0x1U << TIM_CCMR2_IC3F_Pos) /*!< 0x00000010 */
+#define TIM_CCMR2_IC3F_1 (0x2U << TIM_CCMR2_IC3F_Pos) /*!< 0x00000020 */
+#define TIM_CCMR2_IC3F_2 (0x4U << TIM_CCMR2_IC3F_Pos) /*!< 0x00000040 */
+#define TIM_CCMR2_IC3F_3 (0x8U << TIM_CCMR2_IC3F_Pos) /*!< 0x00000080 */
+
+#define TIM_CCMR2_IC4PSC_Pos (10U)
+#define TIM_CCMR2_IC4PSC_Msk (0x3U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000C00 */
+#define TIM_CCMR2_IC4PSC TIM_CCMR2_IC4PSC_Msk /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
+#define TIM_CCMR2_IC4PSC_0 (0x1U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000400 */
+#define TIM_CCMR2_IC4PSC_1 (0x2U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000800 */
+
+#define TIM_CCMR2_IC4F_Pos (12U)
+#define TIM_CCMR2_IC4F_Msk (0xFU << TIM_CCMR2_IC4F_Pos) /*!< 0x0000F000 */
+#define TIM_CCMR2_IC4F TIM_CCMR2_IC4F_Msk /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
+#define TIM_CCMR2_IC4F_0 (0x1U << TIM_CCMR2_IC4F_Pos) /*!< 0x00001000 */
+#define TIM_CCMR2_IC4F_1 (0x2U << TIM_CCMR2_IC4F_Pos) /*!< 0x00002000 */
+#define TIM_CCMR2_IC4F_2 (0x4U << TIM_CCMR2_IC4F_Pos) /*!< 0x00004000 */
+#define TIM_CCMR2_IC4F_3 (0x8U << TIM_CCMR2_IC4F_Pos) /*!< 0x00008000 */
+
+/******************* Bit definition for TIM_CCER register ******************/
+#define TIM_CCER_CC1E_Pos (0U)
+#define TIM_CCER_CC1E_Msk (0x1U << TIM_CCER_CC1E_Pos) /*!< 0x00000001 */
+#define TIM_CCER_CC1E TIM_CCER_CC1E_Msk /*!<Capture/Compare 1 output enable */
+#define TIM_CCER_CC1P_Pos (1U)
+#define TIM_CCER_CC1P_Msk (0x1U << TIM_CCER_CC1P_Pos) /*!< 0x00000002 */
+#define TIM_CCER_CC1P TIM_CCER_CC1P_Msk /*!<Capture/Compare 1 output Polarity */
+#define TIM_CCER_CC1NE_Pos (2U)
+#define TIM_CCER_CC1NE_Msk (0x1U << TIM_CCER_CC1NE_Pos) /*!< 0x00000004 */
+#define TIM_CCER_CC1NE TIM_CCER_CC1NE_Msk /*!<Capture/Compare 1 Complementary output enable */
+#define TIM_CCER_CC1NP_Pos (3U)
+#define TIM_CCER_CC1NP_Msk (0x1U << TIM_CCER_CC1NP_Pos) /*!< 0x00000008 */
+#define TIM_CCER_CC1NP TIM_CCER_CC1NP_Msk /*!<Capture/Compare 1 Complementary output Polarity */
+#define TIM_CCER_CC2E_Pos (4U)
+#define TIM_CCER_CC2E_Msk (0x1U << TIM_CCER_CC2E_Pos) /*!< 0x00000010 */
+#define TIM_CCER_CC2E TIM_CCER_CC2E_Msk /*!<Capture/Compare 2 output enable */
+#define TIM_CCER_CC2P_Pos (5U)
+#define TIM_CCER_CC2P_Msk (0x1U << TIM_CCER_CC2P_Pos) /*!< 0x00000020 */
+#define TIM_CCER_CC2P TIM_CCER_CC2P_Msk /*!<Capture/Compare 2 output Polarity */
+#define TIM_CCER_CC2NE_Pos (6U)
+#define TIM_CCER_CC2NE_Msk (0x1U << TIM_CCER_CC2NE_Pos) /*!< 0x00000040 */
+#define TIM_CCER_CC2NE TIM_CCER_CC2NE_Msk /*!<Capture/Compare 2 Complementary output enable */
+#define TIM_CCER_CC2NP_Pos (7U)
+#define TIM_CCER_CC2NP_Msk (0x1U << TIM_CCER_CC2NP_Pos) /*!< 0x00000080 */
+#define TIM_CCER_CC2NP TIM_CCER_CC2NP_Msk /*!<Capture/Compare 2 Complementary output Polarity */
+#define TIM_CCER_CC3E_Pos (8U)
+#define TIM_CCER_CC3E_Msk (0x1U << TIM_CCER_CC3E_Pos) /*!< 0x00000100 */
+#define TIM_CCER_CC3E TIM_CCER_CC3E_Msk /*!<Capture/Compare 3 output enable */
+#define TIM_CCER_CC3P_Pos (9U)
+#define TIM_CCER_CC3P_Msk (0x1U << TIM_CCER_CC3P_Pos) /*!< 0x00000200 */
+#define TIM_CCER_CC3P TIM_CCER_CC3P_Msk /*!<Capture/Compare 3 output Polarity */
+#define TIM_CCER_CC3NE_Pos (10U)
+#define TIM_CCER_CC3NE_Msk (0x1U << TIM_CCER_CC3NE_Pos) /*!< 0x00000400 */
+#define TIM_CCER_CC3NE TIM_CCER_CC3NE_Msk /*!<Capture/Compare 3 Complementary output enable */
+#define TIM_CCER_CC3NP_Pos (11U)
+#define TIM_CCER_CC3NP_Msk (0x1U << TIM_CCER_CC3NP_Pos) /*!< 0x00000800 */
+#define TIM_CCER_CC3NP TIM_CCER_CC3NP_Msk /*!<Capture/Compare 3 Complementary output Polarity */
+#define TIM_CCER_CC4E_Pos (12U)
+#define TIM_CCER_CC4E_Msk (0x1U << TIM_CCER_CC4E_Pos) /*!< 0x00001000 */
+#define TIM_CCER_CC4E TIM_CCER_CC4E_Msk /*!<Capture/Compare 4 output enable */
+#define TIM_CCER_CC4P_Pos (13U)
+#define TIM_CCER_CC4P_Msk (0x1U << TIM_CCER_CC4P_Pos) /*!< 0x00002000 */
+#define TIM_CCER_CC4P TIM_CCER_CC4P_Msk /*!<Capture/Compare 4 output Polarity */
+#define TIM_CCER_CC4NP_Pos (15U)
+#define TIM_CCER_CC4NP_Msk (0x1U << TIM_CCER_CC4NP_Pos) /*!< 0x00008000 */
+#define TIM_CCER_CC4NP TIM_CCER_CC4NP_Msk /*!<Capture/Compare 4 Complementary output Polarity */
+
+/******************* Bit definition for TIM_CNT register *******************/
+#define TIM_CNT_CNT_Pos (0U)
+#define TIM_CNT_CNT_Msk (0xFFFFFFFFU << TIM_CNT_CNT_Pos) /*!< 0xFFFFFFFF */
+#define TIM_CNT_CNT TIM_CNT_CNT_Msk /*!<Counter Value */
+
+/******************* Bit definition for TIM_PSC register *******************/
+#define TIM_PSC_PSC_Pos (0U)
+#define TIM_PSC_PSC_Msk (0xFFFFU << TIM_PSC_PSC_Pos) /*!< 0x0000FFFF */
+#define TIM_PSC_PSC TIM_PSC_PSC_Msk /*!<Prescaler Value */
+
+/******************* Bit definition for TIM_ARR register *******************/
+#define TIM_ARR_ARR_Pos (0U)
+#define TIM_ARR_ARR_Msk (0xFFFFFFFFU << TIM_ARR_ARR_Pos) /*!< 0xFFFFFFFF */
+#define TIM_ARR_ARR TIM_ARR_ARR_Msk /*!<actual auto-reload Value */
+
+/******************* Bit definition for TIM_RCR register *******************/
+#define TIM_RCR_REP_Pos (0U)
+#define TIM_RCR_REP_Msk (0xFFU << TIM_RCR_REP_Pos) /*!< 0x000000FF */
+#define TIM_RCR_REP TIM_RCR_REP_Msk /*!<Repetition Counter Value */
+
+/******************* Bit definition for TIM_CCR1 register ******************/
+#define TIM_CCR1_CCR1_Pos (0U)
+#define TIM_CCR1_CCR1_Msk (0xFFFFU << TIM_CCR1_CCR1_Pos) /*!< 0x0000FFFF */
+#define TIM_CCR1_CCR1 TIM_CCR1_CCR1_Msk /*!<Capture/Compare 1 Value */
+
+/******************* Bit definition for TIM_CCR2 register ******************/
+#define TIM_CCR2_CCR2_Pos (0U)
+#define TIM_CCR2_CCR2_Msk (0xFFFFU << TIM_CCR2_CCR2_Pos) /*!< 0x0000FFFF */
+#define TIM_CCR2_CCR2 TIM_CCR2_CCR2_Msk /*!<Capture/Compare 2 Value */
+
+/******************* Bit definition for TIM_CCR3 register ******************/
+#define TIM_CCR3_CCR3_Pos (0U)
+#define TIM_CCR3_CCR3_Msk (0xFFFFU << TIM_CCR3_CCR3_Pos) /*!< 0x0000FFFF */
+#define TIM_CCR3_CCR3 TIM_CCR3_CCR3_Msk /*!<Capture/Compare 3 Value */
+
+/******************* Bit definition for TIM_CCR4 register ******************/
+#define TIM_CCR4_CCR4_Pos (0U)
+#define TIM_CCR4_CCR4_Msk (0xFFFFU << TIM_CCR4_CCR4_Pos) /*!< 0x0000FFFF */
+#define TIM_CCR4_CCR4 TIM_CCR4_CCR4_Msk /*!<Capture/Compare 4 Value */
+
+/******************* Bit definition for TIM_BDTR register ******************/
+#define TIM_BDTR_DTG_Pos (0U)
+#define TIM_BDTR_DTG_Msk (0xFFU << TIM_BDTR_DTG_Pos) /*!< 0x000000FF */
+#define TIM_BDTR_DTG TIM_BDTR_DTG_Msk /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
+#define TIM_BDTR_DTG_0 (0x01U << TIM_BDTR_DTG_Pos) /*!< 0x00000001 */
+#define TIM_BDTR_DTG_1 (0x02U << TIM_BDTR_DTG_Pos) /*!< 0x00000002 */
+#define TIM_BDTR_DTG_2 (0x04U << TIM_BDTR_DTG_Pos) /*!< 0x00000004 */
+#define TIM_BDTR_DTG_3 (0x08U << TIM_BDTR_DTG_Pos) /*!< 0x00000008 */
+#define TIM_BDTR_DTG_4 (0x10U << TIM_BDTR_DTG_Pos) /*!< 0x00000010 */
+#define TIM_BDTR_DTG_5 (0x20U << TIM_BDTR_DTG_Pos) /*!< 0x00000020 */
+#define TIM_BDTR_DTG_6 (0x40U << TIM_BDTR_DTG_Pos) /*!< 0x00000040 */
+#define TIM_BDTR_DTG_7 (0x80U << TIM_BDTR_DTG_Pos) /*!< 0x00000080 */
+
+#define TIM_BDTR_LOCK_Pos (8U)
+#define TIM_BDTR_LOCK_Msk (0x3U << TIM_BDTR_LOCK_Pos) /*!< 0x00000300 */
+#define TIM_BDTR_LOCK TIM_BDTR_LOCK_Msk /*!<LOCK[1:0] bits (Lock Configuration) */
+#define TIM_BDTR_LOCK_0 (0x1U << TIM_BDTR_LOCK_Pos) /*!< 0x00000100 */
+#define TIM_BDTR_LOCK_1 (0x2U << TIM_BDTR_LOCK_Pos) /*!< 0x00000200 */
+
+#define TIM_BDTR_OSSI_Pos (10U)
+#define TIM_BDTR_OSSI_Msk (0x1U << TIM_BDTR_OSSI_Pos) /*!< 0x00000400 */
+#define TIM_BDTR_OSSI TIM_BDTR_OSSI_Msk /*!<Off-State Selection for Idle mode */
+#define TIM_BDTR_OSSR_Pos (11U)
+#define TIM_BDTR_OSSR_Msk (0x1U << TIM_BDTR_OSSR_Pos) /*!< 0x00000800 */
+#define TIM_BDTR_OSSR TIM_BDTR_OSSR_Msk /*!<Off-State Selection for Run mode */
+#define TIM_BDTR_BKE_Pos (12U)
+#define TIM_BDTR_BKE_Msk (0x1U << TIM_BDTR_BKE_Pos) /*!< 0x00001000 */
+#define TIM_BDTR_BKE TIM_BDTR_BKE_Msk /*!<Break enable */
+#define TIM_BDTR_BKP_Pos (13U)
+#define TIM_BDTR_BKP_Msk (0x1U << TIM_BDTR_BKP_Pos) /*!< 0x00002000 */
+#define TIM_BDTR_BKP TIM_BDTR_BKP_Msk /*!<Break Polarity */
+#define TIM_BDTR_AOE_Pos (14U)
+#define TIM_BDTR_AOE_Msk (0x1U << TIM_BDTR_AOE_Pos) /*!< 0x00004000 */
+#define TIM_BDTR_AOE TIM_BDTR_AOE_Msk /*!<Automatic Output enable */
+#define TIM_BDTR_MOE_Pos (15U)
+#define TIM_BDTR_MOE_Msk (0x1U << TIM_BDTR_MOE_Pos) /*!< 0x00008000 */
+#define TIM_BDTR_MOE TIM_BDTR_MOE_Msk /*!<Main Output enable */
+
+/******************* Bit definition for TIM_DCR register *******************/
+#define TIM_DCR_DBA_Pos (0U)
+#define TIM_DCR_DBA_Msk (0x1FU << TIM_DCR_DBA_Pos) /*!< 0x0000001F */
+#define TIM_DCR_DBA TIM_DCR_DBA_Msk /*!<DBA[4:0] bits (DMA Base Address) */
+#define TIM_DCR_DBA_0 (0x01U << TIM_DCR_DBA_Pos) /*!< 0x00000001 */
+#define TIM_DCR_DBA_1 (0x02U << TIM_DCR_DBA_Pos) /*!< 0x00000002 */
+#define TIM_DCR_DBA_2 (0x04U << TIM_DCR_DBA_Pos) /*!< 0x00000004 */
+#define TIM_DCR_DBA_3 (0x08U << TIM_DCR_DBA_Pos) /*!< 0x00000008 */
+#define TIM_DCR_DBA_4 (0x10U << TIM_DCR_DBA_Pos) /*!< 0x00000010 */
+
+#define TIM_DCR_DBL_Pos (8U)
+#define TIM_DCR_DBL_Msk (0x1FU << TIM_DCR_DBL_Pos) /*!< 0x00001F00 */
+#define TIM_DCR_DBL TIM_DCR_DBL_Msk /*!<DBL[4:0] bits (DMA Burst Length) */
+#define TIM_DCR_DBL_0 (0x01U << TIM_DCR_DBL_Pos) /*!< 0x00000100 */
+#define TIM_DCR_DBL_1 (0x02U << TIM_DCR_DBL_Pos) /*!< 0x00000200 */
+#define TIM_DCR_DBL_2 (0x04U << TIM_DCR_DBL_Pos) /*!< 0x00000400 */
+#define TIM_DCR_DBL_3 (0x08U << TIM_DCR_DBL_Pos) /*!< 0x00000800 */
+#define TIM_DCR_DBL_4 (0x10U << TIM_DCR_DBL_Pos) /*!< 0x00001000 */
+
+/******************* Bit definition for TIM_DMAR register ******************/
+#define TIM_DMAR_DMAB_Pos (0U)
+#define TIM_DMAR_DMAB_Msk (0xFFFFU << TIM_DMAR_DMAB_Pos) /*!< 0x0000FFFF */
+#define TIM_DMAR_DMAB TIM_DMAR_DMAB_Msk /*!<DMA register for burst accesses */
+
+/******************* Bit definition for TIM_OR register ********************/
+
+/******************************************************************************/
+/* */
+/* Real-Time Clock */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for RTC_CRH register ********************/
+#define RTC_CRH_SECIE_Pos (0U)
+#define RTC_CRH_SECIE_Msk (0x1U << RTC_CRH_SECIE_Pos) /*!< 0x00000001 */
+#define RTC_CRH_SECIE RTC_CRH_SECIE_Msk /*!< Second Interrupt Enable */
+#define RTC_CRH_ALRIE_Pos (1U)
+#define RTC_CRH_ALRIE_Msk (0x1U << RTC_CRH_ALRIE_Pos) /*!< 0x00000002 */
+#define RTC_CRH_ALRIE RTC_CRH_ALRIE_Msk /*!< Alarm Interrupt Enable */
+#define RTC_CRH_OWIE_Pos (2U)
+#define RTC_CRH_OWIE_Msk (0x1U << RTC_CRH_OWIE_Pos) /*!< 0x00000004 */
+#define RTC_CRH_OWIE RTC_CRH_OWIE_Msk /*!< OverfloW Interrupt Enable */
+
+/******************* Bit definition for RTC_CRL register ********************/
+#define RTC_CRL_SECF_Pos (0U)
+#define RTC_CRL_SECF_Msk (0x1U << RTC_CRL_SECF_Pos) /*!< 0x00000001 */
+#define RTC_CRL_SECF RTC_CRL_SECF_Msk /*!< Second Flag */
+#define RTC_CRL_ALRF_Pos (1U)
+#define RTC_CRL_ALRF_Msk (0x1U << RTC_CRL_ALRF_Pos) /*!< 0x00000002 */
+#define RTC_CRL_ALRF RTC_CRL_ALRF_Msk /*!< Alarm Flag */
+#define RTC_CRL_OWF_Pos (2U)
+#define RTC_CRL_OWF_Msk (0x1U << RTC_CRL_OWF_Pos) /*!< 0x00000004 */
+#define RTC_CRL_OWF RTC_CRL_OWF_Msk /*!< OverfloW Flag */
+#define RTC_CRL_RSF_Pos (3U)
+#define RTC_CRL_RSF_Msk (0x1U << RTC_CRL_RSF_Pos) /*!< 0x00000008 */
+#define RTC_CRL_RSF RTC_CRL_RSF_Msk /*!< Registers Synchronized Flag */
+#define RTC_CRL_CNF_Pos (4U)
+#define RTC_CRL_CNF_Msk (0x1U << RTC_CRL_CNF_Pos) /*!< 0x00000010 */
+#define RTC_CRL_CNF RTC_CRL_CNF_Msk /*!< Configuration Flag */
+#define RTC_CRL_RTOFF_Pos (5U)
+#define RTC_CRL_RTOFF_Msk (0x1U << RTC_CRL_RTOFF_Pos) /*!< 0x00000020 */
+#define RTC_CRL_RTOFF RTC_CRL_RTOFF_Msk /*!< RTC operation OFF */
+
+/******************* Bit definition for RTC_PRLH register *******************/
+#define RTC_PRLH_PRL_Pos (0U)
+#define RTC_PRLH_PRL_Msk (0xFU << RTC_PRLH_PRL_Pos) /*!< 0x0000000F */
+#define RTC_PRLH_PRL RTC_PRLH_PRL_Msk /*!< RTC Prescaler Reload Value High */
+
+/******************* Bit definition for RTC_PRLL register *******************/
+#define RTC_PRLL_PRL_Pos (0U)
+#define RTC_PRLL_PRL_Msk (0xFFFFU << RTC_PRLL_PRL_Pos) /*!< 0x0000FFFF */
+#define RTC_PRLL_PRL RTC_PRLL_PRL_Msk /*!< RTC Prescaler Reload Value Low */
+
+/******************* Bit definition for RTC_DIVH register *******************/
+#define RTC_DIVH_RTC_DIV_Pos (0U)
+#define RTC_DIVH_RTC_DIV_Msk (0xFU << RTC_DIVH_RTC_DIV_Pos) /*!< 0x0000000F */
+#define RTC_DIVH_RTC_DIV RTC_DIVH_RTC_DIV_Msk /*!< RTC Clock Divider High */
+
+/******************* Bit definition for RTC_DIVL register *******************/
+#define RTC_DIVL_RTC_DIV_Pos (0U)
+#define RTC_DIVL_RTC_DIV_Msk (0xFFFFU << RTC_DIVL_RTC_DIV_Pos) /*!< 0x0000FFFF */
+#define RTC_DIVL_RTC_DIV RTC_DIVL_RTC_DIV_Msk /*!< RTC Clock Divider Low */
+
+/******************* Bit definition for RTC_CNTH register *******************/
+#define RTC_CNTH_RTC_CNT_Pos (0U)
+#define RTC_CNTH_RTC_CNT_Msk (0xFFFFU << RTC_CNTH_RTC_CNT_Pos) /*!< 0x0000FFFF */
+#define RTC_CNTH_RTC_CNT RTC_CNTH_RTC_CNT_Msk /*!< RTC Counter High */
+
+/******************* Bit definition for RTC_CNTL register *******************/
+#define RTC_CNTL_RTC_CNT_Pos (0U)
+#define RTC_CNTL_RTC_CNT_Msk (0xFFFFU << RTC_CNTL_RTC_CNT_Pos) /*!< 0x0000FFFF */
+#define RTC_CNTL_RTC_CNT RTC_CNTL_RTC_CNT_Msk /*!< RTC Counter Low */
+
+/******************* Bit definition for RTC_ALRH register *******************/
+#define RTC_ALRH_RTC_ALR_Pos (0U)
+#define RTC_ALRH_RTC_ALR_Msk (0xFFFFU << RTC_ALRH_RTC_ALR_Pos) /*!< 0x0000FFFF */
+#define RTC_ALRH_RTC_ALR RTC_ALRH_RTC_ALR_Msk /*!< RTC Alarm High */
+
+/******************* Bit definition for RTC_ALRL register *******************/
+#define RTC_ALRL_RTC_ALR_Pos (0U)
+#define RTC_ALRL_RTC_ALR_Msk (0xFFFFU << RTC_ALRL_RTC_ALR_Pos) /*!< 0x0000FFFF */
+#define RTC_ALRL_RTC_ALR RTC_ALRL_RTC_ALR_Msk /*!< RTC Alarm Low */
+
+/******************************************************************************/
+/* */
+/* Independent WATCHDOG (IWDG) */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for IWDG_KR register ********************/
+#define IWDG_KR_KEY_Pos (0U)
+#define IWDG_KR_KEY_Msk (0xFFFFU << IWDG_KR_KEY_Pos) /*!< 0x0000FFFF */
+#define IWDG_KR_KEY IWDG_KR_KEY_Msk /*!< Key value (write only, read 0000h) */
+
+/******************* Bit definition for IWDG_PR register ********************/
+#define IWDG_PR_PR_Pos (0U)
+#define IWDG_PR_PR_Msk (0x7U << IWDG_PR_PR_Pos) /*!< 0x00000007 */
+#define IWDG_PR_PR IWDG_PR_PR_Msk /*!< PR[2:0] (Prescaler divider) */
+#define IWDG_PR_PR_0 (0x1U << IWDG_PR_PR_Pos) /*!< 0x00000001 */
+#define IWDG_PR_PR_1 (0x2U << IWDG_PR_PR_Pos) /*!< 0x00000002 */
+#define IWDG_PR_PR_2 (0x4U << IWDG_PR_PR_Pos) /*!< 0x00000004 */
+
+/******************* Bit definition for IWDG_RLR register *******************/
+#define IWDG_RLR_RL_Pos (0U)
+#define IWDG_RLR_RL_Msk (0xFFFU << IWDG_RLR_RL_Pos) /*!< 0x00000FFF */
+#define IWDG_RLR_RL IWDG_RLR_RL_Msk /*!< Watchdog counter reload value */
+
+/******************* Bit definition for IWDG_SR register ********************/
+#define IWDG_SR_PVU_Pos (0U)
+#define IWDG_SR_PVU_Msk (0x1U << IWDG_SR_PVU_Pos) /*!< 0x00000001 */
+#define IWDG_SR_PVU IWDG_SR_PVU_Msk /*!< Watchdog prescaler value update */
+#define IWDG_SR_RVU_Pos (1U)
+#define IWDG_SR_RVU_Msk (0x1U << IWDG_SR_RVU_Pos) /*!< 0x00000002 */
+#define IWDG_SR_RVU IWDG_SR_RVU_Msk /*!< Watchdog counter reload value update */
+
+/******************************************************************************/
+/* */
+/* Window WATCHDOG (WWDG) */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for WWDG_CR register ********************/
+#define WWDG_CR_T_Pos (0U)
+#define WWDG_CR_T_Msk (0x7FU << WWDG_CR_T_Pos) /*!< 0x0000007F */
+#define WWDG_CR_T WWDG_CR_T_Msk /*!< T[6:0] bits (7-Bit counter (MSB to LSB)) */
+#define WWDG_CR_T_0 (0x01U << WWDG_CR_T_Pos) /*!< 0x00000001 */
+#define WWDG_CR_T_1 (0x02U << WWDG_CR_T_Pos) /*!< 0x00000002 */
+#define WWDG_CR_T_2 (0x04U << WWDG_CR_T_Pos) /*!< 0x00000004 */
+#define WWDG_CR_T_3 (0x08U << WWDG_CR_T_Pos) /*!< 0x00000008 */
+#define WWDG_CR_T_4 (0x10U << WWDG_CR_T_Pos) /*!< 0x00000010 */
+#define WWDG_CR_T_5 (0x20U << WWDG_CR_T_Pos) /*!< 0x00000020 */
+#define WWDG_CR_T_6 (0x40U << WWDG_CR_T_Pos) /*!< 0x00000040 */
+
+/* Legacy defines */
+#define WWDG_CR_T0 WWDG_CR_T_0
+#define WWDG_CR_T1 WWDG_CR_T_1
+#define WWDG_CR_T2 WWDG_CR_T_2
+#define WWDG_CR_T3 WWDG_CR_T_3
+#define WWDG_CR_T4 WWDG_CR_T_4
+#define WWDG_CR_T5 WWDG_CR_T_5
+#define WWDG_CR_T6 WWDG_CR_T_6
+
+#define WWDG_CR_WDGA_Pos (7U)
+#define WWDG_CR_WDGA_Msk (0x1U << WWDG_CR_WDGA_Pos) /*!< 0x00000080 */
+#define WWDG_CR_WDGA WWDG_CR_WDGA_Msk /*!< Activation bit */
+
+/******************* Bit definition for WWDG_CFR register *******************/
+#define WWDG_CFR_W_Pos (0U)
+#define WWDG_CFR_W_Msk (0x7FU << WWDG_CFR_W_Pos) /*!< 0x0000007F */
+#define WWDG_CFR_W WWDG_CFR_W_Msk /*!< W[6:0] bits (7-bit window value) */
+#define WWDG_CFR_W_0 (0x01U << WWDG_CFR_W_Pos) /*!< 0x00000001 */
+#define WWDG_CFR_W_1 (0x02U << WWDG_CFR_W_Pos) /*!< 0x00000002 */
+#define WWDG_CFR_W_2 (0x04U << WWDG_CFR_W_Pos) /*!< 0x00000004 */
+#define WWDG_CFR_W_3 (0x08U << WWDG_CFR_W_Pos) /*!< 0x00000008 */
+#define WWDG_CFR_W_4 (0x10U << WWDG_CFR_W_Pos) /*!< 0x00000010 */
+#define WWDG_CFR_W_5 (0x20U << WWDG_CFR_W_Pos) /*!< 0x00000020 */
+#define WWDG_CFR_W_6 (0x40U << WWDG_CFR_W_Pos) /*!< 0x00000040 */
+
+/* Legacy defines */
+#define WWDG_CFR_W0 WWDG_CFR_W_0
+#define WWDG_CFR_W1 WWDG_CFR_W_1
+#define WWDG_CFR_W2 WWDG_CFR_W_2
+#define WWDG_CFR_W3 WWDG_CFR_W_3
+#define WWDG_CFR_W4 WWDG_CFR_W_4
+#define WWDG_CFR_W5 WWDG_CFR_W_5
+#define WWDG_CFR_W6 WWDG_CFR_W_6
+
+#define WWDG_CFR_WDGTB_Pos (7U)
+#define WWDG_CFR_WDGTB_Msk (0x3U << WWDG_CFR_WDGTB_Pos) /*!< 0x00000180 */
+#define WWDG_CFR_WDGTB WWDG_CFR_WDGTB_Msk /*!< WDGTB[1:0] bits (Timer Base) */
+#define WWDG_CFR_WDGTB_0 (0x1U << WWDG_CFR_WDGTB_Pos) /*!< 0x00000080 */
+#define WWDG_CFR_WDGTB_1 (0x2U << WWDG_CFR_WDGTB_Pos) /*!< 0x00000100 */
+
+/* Legacy defines */
+#define WWDG_CFR_WDGTB0 WWDG_CFR_WDGTB_0
+#define WWDG_CFR_WDGTB1 WWDG_CFR_WDGTB_1
+
+#define WWDG_CFR_EWI_Pos (9U)
+#define WWDG_CFR_EWI_Msk (0x1U << WWDG_CFR_EWI_Pos) /*!< 0x00000200 */
+#define WWDG_CFR_EWI WWDG_CFR_EWI_Msk /*!< Early Wakeup Interrupt */
+
+/******************* Bit definition for WWDG_SR register ********************/
+#define WWDG_SR_EWIF_Pos (0U)
+#define WWDG_SR_EWIF_Msk (0x1U << WWDG_SR_EWIF_Pos) /*!< 0x00000001 */
+#define WWDG_SR_EWIF WWDG_SR_EWIF_Msk /*!< Early Wakeup Interrupt Flag */
+
+/******************************************************************************/
+/* */
+/* Flexible Static Memory Controller */
+/* */
+/******************************************************************************/
+
+/****************** Bit definition for FSMC_BCRx (x=1..4) register **********/
+#define FSMC_BCRx_MBKEN_Pos (0U)
+#define FSMC_BCRx_MBKEN_Msk (0x1U << FSMC_BCRx_MBKEN_Pos) /*!< 0x00000001 */
+#define FSMC_BCRx_MBKEN FSMC_BCRx_MBKEN_Msk /*!< Memory bank enable bit */
+#define FSMC_BCRx_MUXEN_Pos (1U)
+#define FSMC_BCRx_MUXEN_Msk (0x1U << FSMC_BCRx_MUXEN_Pos) /*!< 0x00000002 */
+#define FSMC_BCRx_MUXEN FSMC_BCRx_MUXEN_Msk /*!< Address/data multiplexing enable bit */
+
+#define FSMC_BCRx_MTYP_Pos (2U)
+#define FSMC_BCRx_MTYP_Msk (0x3U << FSMC_BCRx_MTYP_Pos) /*!< 0x0000000C */
+#define FSMC_BCRx_MTYP FSMC_BCRx_MTYP_Msk /*!< MTYP[1:0] bits (Memory type) */
+#define FSMC_BCRx_MTYP_0 (0x1U << FSMC_BCRx_MTYP_Pos) /*!< 0x00000004 */
+#define FSMC_BCRx_MTYP_1 (0x2U << FSMC_BCRx_MTYP_Pos) /*!< 0x00000008 */
+
+#define FSMC_BCRx_MWID_Pos (4U)
+#define FSMC_BCRx_MWID_Msk (0x3U << FSMC_BCRx_MWID_Pos) /*!< 0x00000030 */
+#define FSMC_BCRx_MWID FSMC_BCRx_MWID_Msk /*!< MWID[1:0] bits (Memory data bus width) */
+#define FSMC_BCRx_MWID_0 (0x1U << FSMC_BCRx_MWID_Pos) /*!< 0x00000010 */
+#define FSMC_BCRx_MWID_1 (0x2U << FSMC_BCRx_MWID_Pos) /*!< 0x00000020 */
+
+#define FSMC_BCRx_FACCEN_Pos (6U)
+#define FSMC_BCRx_FACCEN_Msk (0x1U << FSMC_BCRx_FACCEN_Pos) /*!< 0x00000040 */
+#define FSMC_BCRx_FACCEN FSMC_BCRx_FACCEN_Msk /*!< Flash access enable */
+#define FSMC_BCRx_BURSTEN_Pos (8U)
+#define FSMC_BCRx_BURSTEN_Msk (0x1U << FSMC_BCRx_BURSTEN_Pos) /*!< 0x00000100 */
+#define FSMC_BCRx_BURSTEN FSMC_BCRx_BURSTEN_Msk /*!< Burst enable bit */
+#define FSMC_BCRx_WAITPOL_Pos (9U)
+#define FSMC_BCRx_WAITPOL_Msk (0x1U << FSMC_BCRx_WAITPOL_Pos) /*!< 0x00000200 */
+#define FSMC_BCRx_WAITPOL FSMC_BCRx_WAITPOL_Msk /*!< Wait signal polarity bit */
+#define FSMC_BCRx_WRAPMOD_Pos (10U)
+#define FSMC_BCRx_WRAPMOD_Msk (0x1U << FSMC_BCRx_WRAPMOD_Pos) /*!< 0x00000400 */
+#define FSMC_BCRx_WRAPMOD FSMC_BCRx_WRAPMOD_Msk /*!< Wrapped burst mode support */
+#define FSMC_BCRx_WAITCFG_Pos (11U)
+#define FSMC_BCRx_WAITCFG_Msk (0x1U << FSMC_BCRx_WAITCFG_Pos) /*!< 0x00000800 */
+#define FSMC_BCRx_WAITCFG FSMC_BCRx_WAITCFG_Msk /*!< Wait timing configuration */
+#define FSMC_BCRx_WREN_Pos (12U)
+#define FSMC_BCRx_WREN_Msk (0x1U << FSMC_BCRx_WREN_Pos) /*!< 0x00001000 */
+#define FSMC_BCRx_WREN FSMC_BCRx_WREN_Msk /*!< Write enable bit */
+#define FSMC_BCRx_WAITEN_Pos (13U)
+#define FSMC_BCRx_WAITEN_Msk (0x1U << FSMC_BCRx_WAITEN_Pos) /*!< 0x00002000 */
+#define FSMC_BCRx_WAITEN FSMC_BCRx_WAITEN_Msk /*!< Wait enable bit */
+#define FSMC_BCRx_EXTMOD_Pos (14U)
+#define FSMC_BCRx_EXTMOD_Msk (0x1U << FSMC_BCRx_EXTMOD_Pos) /*!< 0x00004000 */
+#define FSMC_BCRx_EXTMOD FSMC_BCRx_EXTMOD_Msk /*!< Extended mode enable */
+#define FSMC_BCRx_ASYNCWAIT_Pos (15U)
+#define FSMC_BCRx_ASYNCWAIT_Msk (0x1U << FSMC_BCRx_ASYNCWAIT_Pos) /*!< 0x00008000 */
+#define FSMC_BCRx_ASYNCWAIT FSMC_BCRx_ASYNCWAIT_Msk /*!< Asynchronous wait */
+#define FSMC_BCRx_CBURSTRW_Pos (19U)
+#define FSMC_BCRx_CBURSTRW_Msk (0x1U << FSMC_BCRx_CBURSTRW_Pos) /*!< 0x00080000 */
+#define FSMC_BCRx_CBURSTRW FSMC_BCRx_CBURSTRW_Msk /*!< Write burst enable */
+
+/****************** Bit definition for FSMC_BTRx (x=1..4) register ******/
+#define FSMC_BTRx_ADDSET_Pos (0U)
+#define FSMC_BTRx_ADDSET_Msk (0xFU << FSMC_BTRx_ADDSET_Pos) /*!< 0x0000000F */
+#define FSMC_BTRx_ADDSET FSMC_BTRx_ADDSET_Msk /*!< ADDSET[3:0] bits (Address setup phase duration) */
+#define FSMC_BTRx_ADDSET_0 (0x1U << FSMC_BTRx_ADDSET_Pos) /*!< 0x00000001 */
+#define FSMC_BTRx_ADDSET_1 (0x2U << FSMC_BTRx_ADDSET_Pos) /*!< 0x00000002 */
+#define FSMC_BTRx_ADDSET_2 (0x4U << FSMC_BTRx_ADDSET_Pos) /*!< 0x00000004 */
+#define FSMC_BTRx_ADDSET_3 (0x8U << FSMC_BTRx_ADDSET_Pos) /*!< 0x00000008 */
+
+#define FSMC_BTRx_ADDHLD_Pos (4U)
+#define FSMC_BTRx_ADDHLD_Msk (0xFU << FSMC_BTRx_ADDHLD_Pos) /*!< 0x000000F0 */
+#define FSMC_BTRx_ADDHLD FSMC_BTRx_ADDHLD_Msk /*!< ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FSMC_BTRx_ADDHLD_0 (0x1U << FSMC_BTRx_ADDHLD_Pos) /*!< 0x00000010 */
+#define FSMC_BTRx_ADDHLD_1 (0x2U << FSMC_BTRx_ADDHLD_Pos) /*!< 0x00000020 */
+#define FSMC_BTRx_ADDHLD_2 (0x4U << FSMC_BTRx_ADDHLD_Pos) /*!< 0x00000040 */
+#define FSMC_BTRx_ADDHLD_3 (0x8U << FSMC_BTRx_ADDHLD_Pos) /*!< 0x00000080 */
+
+#define FSMC_BTRx_DATAST_Pos (8U)
+#define FSMC_BTRx_DATAST_Msk (0xFFU << FSMC_BTRx_DATAST_Pos) /*!< 0x0000FF00 */
+#define FSMC_BTRx_DATAST FSMC_BTRx_DATAST_Msk /*!< DATAST [3:0] bits (Data-phase duration) */
+#define FSMC_BTRx_DATAST_0 (0x01U << FSMC_BTRx_DATAST_Pos) /*!< 0x00000100 */
+#define FSMC_BTRx_DATAST_1 (0x02U << FSMC_BTRx_DATAST_Pos) /*!< 0x00000200 */
+#define FSMC_BTRx_DATAST_2 (0x04U << FSMC_BTRx_DATAST_Pos) /*!< 0x00000400 */
+#define FSMC_BTRx_DATAST_3 (0x08U << FSMC_BTRx_DATAST_Pos) /*!< 0x00000800 */
+#define FSMC_BTRx_DATAST_4 (0x10U << FSMC_BTRx_DATAST_Pos) /*!< 0x00001000 */
+#define FSMC_BTRx_DATAST_5 (0x20U << FSMC_BTRx_DATAST_Pos) /*!< 0x00002000 */
+#define FSMC_BTRx_DATAST_6 (0x40U << FSMC_BTRx_DATAST_Pos) /*!< 0x00004000 */
+#define FSMC_BTRx_DATAST_7 (0x80U << FSMC_BTRx_DATAST_Pos) /*!< 0x00008000 */
+
+#define FSMC_BTRx_BUSTURN_Pos (16U)
+#define FSMC_BTRx_BUSTURN_Msk (0xFU << FSMC_BTRx_BUSTURN_Pos) /*!< 0x000F0000 */
+#define FSMC_BTRx_BUSTURN FSMC_BTRx_BUSTURN_Msk /*!< BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define FSMC_BTRx_BUSTURN_0 (0x1U << FSMC_BTRx_BUSTURN_Pos) /*!< 0x00010000 */
+#define FSMC_BTRx_BUSTURN_1 (0x2U << FSMC_BTRx_BUSTURN_Pos) /*!< 0x00020000 */
+#define FSMC_BTRx_BUSTURN_2 (0x4U << FSMC_BTRx_BUSTURN_Pos) /*!< 0x00040000 */
+#define FSMC_BTRx_BUSTURN_3 (0x8U << FSMC_BTRx_BUSTURN_Pos) /*!< 0x00080000 */
+
+#define FSMC_BTRx_CLKDIV_Pos (20U)
+#define FSMC_BTRx_CLKDIV_Msk (0xFU << FSMC_BTRx_CLKDIV_Pos) /*!< 0x00F00000 */
+#define FSMC_BTRx_CLKDIV FSMC_BTRx_CLKDIV_Msk /*!< CLKDIV[3:0] bits (Clock divide ratio) */
+#define FSMC_BTRx_CLKDIV_0 (0x1U << FSMC_BTRx_CLKDIV_Pos) /*!< 0x00100000 */
+#define FSMC_BTRx_CLKDIV_1 (0x2U << FSMC_BTRx_CLKDIV_Pos) /*!< 0x00200000 */
+#define FSMC_BTRx_CLKDIV_2 (0x4U << FSMC_BTRx_CLKDIV_Pos) /*!< 0x00400000 */
+#define FSMC_BTRx_CLKDIV_3 (0x8U << FSMC_BTRx_CLKDIV_Pos) /*!< 0x00800000 */
+
+#define FSMC_BTRx_DATLAT_Pos (24U)
+#define FSMC_BTRx_DATLAT_Msk (0xFU << FSMC_BTRx_DATLAT_Pos) /*!< 0x0F000000 */
+#define FSMC_BTRx_DATLAT FSMC_BTRx_DATLAT_Msk /*!< DATLA[3:0] bits (Data latency) */
+#define FSMC_BTRx_DATLAT_0 (0x1U << FSMC_BTRx_DATLAT_Pos) /*!< 0x01000000 */
+#define FSMC_BTRx_DATLAT_1 (0x2U << FSMC_BTRx_DATLAT_Pos) /*!< 0x02000000 */
+#define FSMC_BTRx_DATLAT_2 (0x4U << FSMC_BTRx_DATLAT_Pos) /*!< 0x04000000 */
+#define FSMC_BTRx_DATLAT_3 (0x8U << FSMC_BTRx_DATLAT_Pos) /*!< 0x08000000 */
+
+#define FSMC_BTRx_ACCMOD_Pos (28U)
+#define FSMC_BTRx_ACCMOD_Msk (0x3U << FSMC_BTRx_ACCMOD_Pos) /*!< 0x30000000 */
+#define FSMC_BTRx_ACCMOD FSMC_BTRx_ACCMOD_Msk /*!< ACCMOD[1:0] bits (Access mode) */
+#define FSMC_BTRx_ACCMOD_0 (0x1U << FSMC_BTRx_ACCMOD_Pos) /*!< 0x10000000 */
+#define FSMC_BTRx_ACCMOD_1 (0x2U << FSMC_BTRx_ACCMOD_Pos) /*!< 0x20000000 */
+
+/****************** Bit definition for FSMC_BWTRx (x=1..4) register ******/
+#define FSMC_BWTRx_ADDSET_Pos (0U)
+#define FSMC_BWTRx_ADDSET_Msk (0xFU << FSMC_BWTRx_ADDSET_Pos) /*!< 0x0000000F */
+#define FSMC_BWTRx_ADDSET FSMC_BWTRx_ADDSET_Msk /*!< ADDSET[3:0] bits (Address setup phase duration) */
+#define FSMC_BWTRx_ADDSET_0 (0x1U << FSMC_BWTRx_ADDSET_Pos) /*!< 0x00000001 */
+#define FSMC_BWTRx_ADDSET_1 (0x2U << FSMC_BWTRx_ADDSET_Pos) /*!< 0x00000002 */
+#define FSMC_BWTRx_ADDSET_2 (0x4U << FSMC_BWTRx_ADDSET_Pos) /*!< 0x00000004 */
+#define FSMC_BWTRx_ADDSET_3 (0x8U << FSMC_BWTRx_ADDSET_Pos) /*!< 0x00000008 */
+
+#define FSMC_BWTRx_ADDHLD_Pos (4U)
+#define FSMC_BWTRx_ADDHLD_Msk (0xFU << FSMC_BWTRx_ADDHLD_Pos) /*!< 0x000000F0 */
+#define FSMC_BWTRx_ADDHLD FSMC_BWTRx_ADDHLD_Msk /*!< ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FSMC_BWTRx_ADDHLD_0 (0x1U << FSMC_BWTRx_ADDHLD_Pos) /*!< 0x00000010 */
+#define FSMC_BWTRx_ADDHLD_1 (0x2U << FSMC_BWTRx_ADDHLD_Pos) /*!< 0x00000020 */
+#define FSMC_BWTRx_ADDHLD_2 (0x4U << FSMC_BWTRx_ADDHLD_Pos) /*!< 0x00000040 */
+#define FSMC_BWTRx_ADDHLD_3 (0x8U << FSMC_BWTRx_ADDHLD_Pos) /*!< 0x00000080 */
+
+#define FSMC_BWTRx_DATAST_Pos (8U)
+#define FSMC_BWTRx_DATAST_Msk (0xFFU << FSMC_BWTRx_DATAST_Pos) /*!< 0x0000FF00 */
+#define FSMC_BWTRx_DATAST FSMC_BWTRx_DATAST_Msk /*!< DATAST [3:0] bits (Data-phase duration) */
+#define FSMC_BWTRx_DATAST_0 (0x01U << FSMC_BWTRx_DATAST_Pos) /*!< 0x00000100 */
+#define FSMC_BWTRx_DATAST_1 (0x02U << FSMC_BWTRx_DATAST_Pos) /*!< 0x00000200 */
+#define FSMC_BWTRx_DATAST_2 (0x04U << FSMC_BWTRx_DATAST_Pos) /*!< 0x00000400 */
+#define FSMC_BWTRx_DATAST_3 (0x08U << FSMC_BWTRx_DATAST_Pos) /*!< 0x00000800 */
+#define FSMC_BWTRx_DATAST_4 (0x10U << FSMC_BWTRx_DATAST_Pos) /*!< 0x00001000 */
+#define FSMC_BWTRx_DATAST_5 (0x20U << FSMC_BWTRx_DATAST_Pos) /*!< 0x00002000 */
+#define FSMC_BWTRx_DATAST_6 (0x40U << FSMC_BWTRx_DATAST_Pos) /*!< 0x00004000 */
+#define FSMC_BWTRx_DATAST_7 (0x80U << FSMC_BWTRx_DATAST_Pos) /*!< 0x00008000 */
+
+#define FSMC_BWTRx_BUSTURN_Pos (16U)
+#define FSMC_BWTRx_BUSTURN_Msk (0xFU << FSMC_BWTRx_BUSTURN_Pos) /*!< 0x000F0000 */
+#define FSMC_BWTRx_BUSTURN FSMC_BWTRx_BUSTURN_Msk /*!< BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define FSMC_BWTRx_BUSTURN_0 (0x1U << FSMC_BWTRx_BUSTURN_Pos) /*!< 0x00010000 */
+#define FSMC_BWTRx_BUSTURN_1 (0x2U << FSMC_BWTRx_BUSTURN_Pos) /*!< 0x00020000 */
+#define FSMC_BWTRx_BUSTURN_2 (0x4U << FSMC_BWTRx_BUSTURN_Pos) /*!< 0x00040000 */
+#define FSMC_BWTRx_BUSTURN_3 (0x8U << FSMC_BWTRx_BUSTURN_Pos) /*!< 0x00080000 */
+
+#define FSMC_BWTRx_ACCMOD_Pos (28U)
+#define FSMC_BWTRx_ACCMOD_Msk (0x3U << FSMC_BWTRx_ACCMOD_Pos) /*!< 0x30000000 */
+#define FSMC_BWTRx_ACCMOD FSMC_BWTRx_ACCMOD_Msk /*!< ACCMOD[1:0] bits (Access mode) */
+#define FSMC_BWTRx_ACCMOD_0 (0x1U << FSMC_BWTRx_ACCMOD_Pos) /*!< 0x10000000 */
+#define FSMC_BWTRx_ACCMOD_1 (0x2U << FSMC_BWTRx_ACCMOD_Pos) /*!< 0x20000000 */
+
+/****************** Bit definition for FSMC_PCRx (x = 2 to 4) register *******************/
+#define FSMC_PCRx_PWAITEN_Pos (1U)
+#define FSMC_PCRx_PWAITEN_Msk (0x1U << FSMC_PCRx_PWAITEN_Pos) /*!< 0x00000002 */
+#define FSMC_PCRx_PWAITEN FSMC_PCRx_PWAITEN_Msk /*!< Wait feature enable bit */
+#define FSMC_PCRx_PBKEN_Pos (2U)
+#define FSMC_PCRx_PBKEN_Msk (0x1U << FSMC_PCRx_PBKEN_Pos) /*!< 0x00000004 */
+#define FSMC_PCRx_PBKEN FSMC_PCRx_PBKEN_Msk /*!< PC Card/NAND Flash memory bank enable bit */
+#define FSMC_PCRx_PTYP_Pos (3U)
+#define FSMC_PCRx_PTYP_Msk (0x1U << FSMC_PCRx_PTYP_Pos) /*!< 0x00000008 */
+#define FSMC_PCRx_PTYP FSMC_PCRx_PTYP_Msk /*!< Memory type */
+
+#define FSMC_PCRx_PWID_Pos (4U)
+#define FSMC_PCRx_PWID_Msk (0x3U << FSMC_PCRx_PWID_Pos) /*!< 0x00000030 */
+#define FSMC_PCRx_PWID FSMC_PCRx_PWID_Msk /*!< PWID[1:0] bits (NAND Flash databus width) */
+#define FSMC_PCRx_PWID_0 (0x1U << FSMC_PCRx_PWID_Pos) /*!< 0x00000010 */
+#define FSMC_PCRx_PWID_1 (0x2U << FSMC_PCRx_PWID_Pos) /*!< 0x00000020 */
+
+#define FSMC_PCRx_ECCEN_Pos (6U)
+#define FSMC_PCRx_ECCEN_Msk (0x1U << FSMC_PCRx_ECCEN_Pos) /*!< 0x00000040 */
+#define FSMC_PCRx_ECCEN FSMC_PCRx_ECCEN_Msk /*!< ECC computation logic enable bit */
+
+#define FSMC_PCRx_TCLR_Pos (9U)
+#define FSMC_PCRx_TCLR_Msk (0xFU << FSMC_PCRx_TCLR_Pos) /*!< 0x00001E00 */
+#define FSMC_PCRx_TCLR FSMC_PCRx_TCLR_Msk /*!< TCLR[3:0] bits (CLE to RE delay) */
+#define FSMC_PCRx_TCLR_0 (0x1U << FSMC_PCRx_TCLR_Pos) /*!< 0x00000200 */
+#define FSMC_PCRx_TCLR_1 (0x2U << FSMC_PCRx_TCLR_Pos) /*!< 0x00000400 */
+#define FSMC_PCRx_TCLR_2 (0x4U << FSMC_PCRx_TCLR_Pos) /*!< 0x00000800 */
+#define FSMC_PCRx_TCLR_3 (0x8U << FSMC_PCRx_TCLR_Pos) /*!< 0x00001000 */
+
+#define FSMC_PCRx_TAR_Pos (13U)
+#define FSMC_PCRx_TAR_Msk (0xFU << FSMC_PCRx_TAR_Pos) /*!< 0x0001E000 */
+#define FSMC_PCRx_TAR FSMC_PCRx_TAR_Msk /*!< TAR[3:0] bits (ALE to RE delay) */
+#define FSMC_PCRx_TAR_0 (0x1U << FSMC_PCRx_TAR_Pos) /*!< 0x00002000 */
+#define FSMC_PCRx_TAR_1 (0x2U << FSMC_PCRx_TAR_Pos) /*!< 0x00004000 */
+#define FSMC_PCRx_TAR_2 (0x4U << FSMC_PCRx_TAR_Pos) /*!< 0x00008000 */
+#define FSMC_PCRx_TAR_3 (0x8U << FSMC_PCRx_TAR_Pos) /*!< 0x00010000 */
+
+#define FSMC_PCRx_ECCPS_Pos (17U)
+#define FSMC_PCRx_ECCPS_Msk (0x7U << FSMC_PCRx_ECCPS_Pos) /*!< 0x000E0000 */
+#define FSMC_PCRx_ECCPS FSMC_PCRx_ECCPS_Msk /*!< ECCPS[1:0] bits (ECC page size) */
+#define FSMC_PCRx_ECCPS_0 (0x1U << FSMC_PCRx_ECCPS_Pos) /*!< 0x00020000 */
+#define FSMC_PCRx_ECCPS_1 (0x2U << FSMC_PCRx_ECCPS_Pos) /*!< 0x00040000 */
+#define FSMC_PCRx_ECCPS_2 (0x4U << FSMC_PCRx_ECCPS_Pos) /*!< 0x00080000 */
+
+/******************* Bit definition for FSMC_SRx (x = 2 to 4) register *******************/
+#define FSMC_SRx_IRS_Pos (0U)
+#define FSMC_SRx_IRS_Msk (0x1U << FSMC_SRx_IRS_Pos) /*!< 0x00000001 */
+#define FSMC_SRx_IRS FSMC_SRx_IRS_Msk /*!< Interrupt Rising Edge status */
+#define FSMC_SRx_ILS_Pos (1U)
+#define FSMC_SRx_ILS_Msk (0x1U << FSMC_SRx_ILS_Pos) /*!< 0x00000002 */
+#define FSMC_SRx_ILS FSMC_SRx_ILS_Msk /*!< Interrupt Level status */
+#define FSMC_SRx_IFS_Pos (2U)
+#define FSMC_SRx_IFS_Msk (0x1U << FSMC_SRx_IFS_Pos) /*!< 0x00000004 */
+#define FSMC_SRx_IFS FSMC_SRx_IFS_Msk /*!< Interrupt Falling Edge status */
+#define FSMC_SRx_IREN_Pos (3U)
+#define FSMC_SRx_IREN_Msk (0x1U << FSMC_SRx_IREN_Pos) /*!< 0x00000008 */
+#define FSMC_SRx_IREN FSMC_SRx_IREN_Msk /*!< Interrupt Rising Edge detection Enable bit */
+#define FSMC_SRx_ILEN_Pos (4U)
+#define FSMC_SRx_ILEN_Msk (0x1U << FSMC_SRx_ILEN_Pos) /*!< 0x00000010 */
+#define FSMC_SRx_ILEN FSMC_SRx_ILEN_Msk /*!< Interrupt Level detection Enable bit */
+#define FSMC_SRx_IFEN_Pos (5U)
+#define FSMC_SRx_IFEN_Msk (0x1U << FSMC_SRx_IFEN_Pos) /*!< 0x00000020 */
+#define FSMC_SRx_IFEN FSMC_SRx_IFEN_Msk /*!< Interrupt Falling Edge detection Enable bit */
+#define FSMC_SRx_FEMPT_Pos (6U)
+#define FSMC_SRx_FEMPT_Msk (0x1U << FSMC_SRx_FEMPT_Pos) /*!< 0x00000040 */
+#define FSMC_SRx_FEMPT FSMC_SRx_FEMPT_Msk /*!< FIFO empty */
+
+/****************** Bit definition for FSMC_PMEMx (x = 2 to 4) register ******************/
+#define FSMC_PMEMx_MEMSETx_Pos (0U)
+#define FSMC_PMEMx_MEMSETx_Msk (0xFFU << FSMC_PMEMx_MEMSETx_Pos) /*!< 0x000000FF */
+#define FSMC_PMEMx_MEMSETx FSMC_PMEMx_MEMSETx_Msk /*!< MEMSETx[7:0] bits (Common memory x setup time) */
+#define FSMC_PMEMx_MEMSETx_0 (0x01U << FSMC_PMEMx_MEMSETx_Pos) /*!< 0x00000001 */
+#define FSMC_PMEMx_MEMSETx_1 (0x02U << FSMC_PMEMx_MEMSETx_Pos) /*!< 0x00000002 */
+#define FSMC_PMEMx_MEMSETx_2 (0x04U << FSMC_PMEMx_MEMSETx_Pos) /*!< 0x00000004 */
+#define FSMC_PMEMx_MEMSETx_3 (0x08U << FSMC_PMEMx_MEMSETx_Pos) /*!< 0x00000008 */
+#define FSMC_PMEMx_MEMSETx_4 (0x10U << FSMC_PMEMx_MEMSETx_Pos) /*!< 0x00000010 */
+#define FSMC_PMEMx_MEMSETx_5 (0x20U << FSMC_PMEMx_MEMSETx_Pos) /*!< 0x00000020 */
+#define FSMC_PMEMx_MEMSETx_6 (0x40U << FSMC_PMEMx_MEMSETx_Pos) /*!< 0x00000040 */
+#define FSMC_PMEMx_MEMSETx_7 (0x80U << FSMC_PMEMx_MEMSETx_Pos) /*!< 0x00000080 */
+
+#define FSMC_PMEMx_MEMWAITx_Pos (8U)
+#define FSMC_PMEMx_MEMWAITx_Msk (0xFFU << FSMC_PMEMx_MEMWAITx_Pos) /*!< 0x0000FF00 */
+#define FSMC_PMEMx_MEMWAITx FSMC_PMEMx_MEMWAITx_Msk /*!< MEMWAITx[7:0] bits (Common memory x wait time) */
+#define FSMC_PMEMx_MEMWAIT2_0 ((uint32_t)0x00000100) /*!< Bit 0 */
+#define FSMC_PMEMx_MEMWAITx_1 ((uint32_t)0x00000200) /*!< Bit 1 */
+#define FSMC_PMEMx_MEMWAITx_2 ((uint32_t)0x00000400) /*!< Bit 2 */
+#define FSMC_PMEMx_MEMWAITx_3 ((uint32_t)0x00000800) /*!< Bit 3 */
+#define FSMC_PMEMx_MEMWAITx_4 ((uint32_t)0x00001000) /*!< Bit 4 */
+#define FSMC_PMEMx_MEMWAITx_5 ((uint32_t)0x00002000) /*!< Bit 5 */
+#define FSMC_PMEMx_MEMWAITx_6 ((uint32_t)0x00004000) /*!< Bit 6 */
+#define FSMC_PMEMx_MEMWAITx_7 ((uint32_t)0x00008000) /*!< Bit 7 */
+
+#define FSMC_PMEMx_MEMHOLDx_Pos (16U)
+#define FSMC_PMEMx_MEMHOLDx_Msk (0xFFU << FSMC_PMEMx_MEMHOLDx_Pos) /*!< 0x00FF0000 */
+#define FSMC_PMEMx_MEMHOLDx FSMC_PMEMx_MEMHOLDx_Msk /*!< MEMHOLDx[7:0] bits (Common memory x hold time) */
+#define FSMC_PMEMx_MEMHOLDx_0 (0x01U << FSMC_PMEMx_MEMHOLDx_Pos) /*!< 0x00010000 */
+#define FSMC_PMEMx_MEMHOLDx_1 (0x02U << FSMC_PMEMx_MEMHOLDx_Pos) /*!< 0x00020000 */
+#define FSMC_PMEMx_MEMHOLDx_2 (0x04U << FSMC_PMEMx_MEMHOLDx_Pos) /*!< 0x00040000 */
+#define FSMC_PMEMx_MEMHOLDx_3 (0x08U << FSMC_PMEMx_MEMHOLDx_Pos) /*!< 0x00080000 */
+#define FSMC_PMEMx_MEMHOLDx_4 (0x10U << FSMC_PMEMx_MEMHOLDx_Pos) /*!< 0x00100000 */
+#define FSMC_PMEMx_MEMHOLDx_5 (0x20U << FSMC_PMEMx_MEMHOLDx_Pos) /*!< 0x00200000 */
+#define FSMC_PMEMx_MEMHOLDx_6 (0x40U << FSMC_PMEMx_MEMHOLDx_Pos) /*!< 0x00400000 */
+#define FSMC_PMEMx_MEMHOLDx_7 (0x80U << FSMC_PMEMx_MEMHOLDx_Pos) /*!< 0x00800000 */
+
+#define FSMC_PMEMx_MEMHIZx_Pos (24U)
+#define FSMC_PMEMx_MEMHIZx_Msk (0xFFU << FSMC_PMEMx_MEMHIZx_Pos) /*!< 0xFF000000 */
+#define FSMC_PMEMx_MEMHIZx FSMC_PMEMx_MEMHIZx_Msk /*!< MEMHIZx[7:0] bits (Common memory x databus HiZ time) */
+#define FSMC_PMEMx_MEMHIZx_0 (0x01U << FSMC_PMEMx_MEMHIZx_Pos) /*!< 0x01000000 */
+#define FSMC_PMEMx_MEMHIZx_1 (0x02U << FSMC_PMEMx_MEMHIZx_Pos) /*!< 0x02000000 */
+#define FSMC_PMEMx_MEMHIZx_2 (0x04U << FSMC_PMEMx_MEMHIZx_Pos) /*!< 0x04000000 */
+#define FSMC_PMEMx_MEMHIZx_3 (0x08U << FSMC_PMEMx_MEMHIZx_Pos) /*!< 0x08000000 */
+#define FSMC_PMEMx_MEMHIZx_4 (0x10U << FSMC_PMEMx_MEMHIZx_Pos) /*!< 0x10000000 */
+#define FSMC_PMEMx_MEMHIZx_5 (0x20U << FSMC_PMEMx_MEMHIZx_Pos) /*!< 0x20000000 */
+#define FSMC_PMEMx_MEMHIZx_6 (0x40U << FSMC_PMEMx_MEMHIZx_Pos) /*!< 0x40000000 */
+#define FSMC_PMEMx_MEMHIZx_7 (0x80U << FSMC_PMEMx_MEMHIZx_Pos) /*!< 0x80000000 */
+
+/****************** Bit definition for FSMC_PATTx (x = 2 to 4) register ******************/
+#define FSMC_PATTx_ATTSETx_Pos (0U)
+#define FSMC_PATTx_ATTSETx_Msk (0xFFU << FSMC_PATTx_ATTSETx_Pos) /*!< 0x000000FF */
+#define FSMC_PATTx_ATTSETx FSMC_PATTx_ATTSETx_Msk /*!< ATTSETx[7:0] bits (Attribute memory x setup time) */
+#define FSMC_PATTx_ATTSETx_0 (0x01U << FSMC_PATTx_ATTSETx_Pos) /*!< 0x00000001 */
+#define FSMC_PATTx_ATTSETx_1 (0x02U << FSMC_PATTx_ATTSETx_Pos) /*!< 0x00000002 */
+#define FSMC_PATTx_ATTSETx_2 (0x04U << FSMC_PATTx_ATTSETx_Pos) /*!< 0x00000004 */
+#define FSMC_PATTx_ATTSETx_3 (0x08U << FSMC_PATTx_ATTSETx_Pos) /*!< 0x00000008 */
+#define FSMC_PATTx_ATTSETx_4 (0x10U << FSMC_PATTx_ATTSETx_Pos) /*!< 0x00000010 */
+#define FSMC_PATTx_ATTSETx_5 (0x20U << FSMC_PATTx_ATTSETx_Pos) /*!< 0x00000020 */
+#define FSMC_PATTx_ATTSETx_6 (0x40U << FSMC_PATTx_ATTSETx_Pos) /*!< 0x00000040 */
+#define FSMC_PATTx_ATTSETx_7 (0x80U << FSMC_PATTx_ATTSETx_Pos) /*!< 0x00000080 */
+
+#define FSMC_PATTx_ATTWAITx_Pos (8U)
+#define FSMC_PATTx_ATTWAITx_Msk (0xFFU << FSMC_PATTx_ATTWAITx_Pos) /*!< 0x0000FF00 */
+#define FSMC_PATTx_ATTWAITx FSMC_PATTx_ATTWAITx_Msk /*!< ATTWAITx[7:0] bits (Attribute memory x wait time) */
+#define FSMC_PATTx_ATTWAITx_0 (0x01U << FSMC_PATTx_ATTWAITx_Pos) /*!< 0x00000100 */
+#define FSMC_PATTx_ATTWAITx_1 (0x02U << FSMC_PATTx_ATTWAITx_Pos) /*!< 0x00000200 */
+#define FSMC_PATTx_ATTWAITx_2 (0x04U << FSMC_PATTx_ATTWAITx_Pos) /*!< 0x00000400 */
+#define FSMC_PATTx_ATTWAITx_3 (0x08U << FSMC_PATTx_ATTWAITx_Pos) /*!< 0x00000800 */
+#define FSMC_PATTx_ATTWAITx_4 (0x10U << FSMC_PATTx_ATTWAITx_Pos) /*!< 0x00001000 */
+#define FSMC_PATTx_ATTWAITx_5 (0x20U << FSMC_PATTx_ATTWAITx_Pos) /*!< 0x00002000 */
+#define FSMC_PATTx_ATTWAITx_6 (0x40U << FSMC_PATTx_ATTWAITx_Pos) /*!< 0x00004000 */
+#define FSMC_PATTx_ATTWAITx_7 (0x80U << FSMC_PATTx_ATTWAITx_Pos) /*!< 0x00008000 */
+
+#define FSMC_PATTx_ATTHOLDx_Pos (16U)
+#define FSMC_PATTx_ATTHOLDx_Msk (0xFFU << FSMC_PATTx_ATTHOLDx_Pos) /*!< 0x00FF0000 */
+#define FSMC_PATTx_ATTHOLDx FSMC_PATTx_ATTHOLDx_Msk /*!< ATTHOLDx[7:0] bits (Attribute memory x hold time) */
+#define FSMC_PATTx_ATTHOLDx_0 (0x01U << FSMC_PATTx_ATTHOLDx_Pos) /*!< 0x00010000 */
+#define FSMC_PATTx_ATTHOLDx_1 (0x02U << FSMC_PATTx_ATTHOLDx_Pos) /*!< 0x00020000 */
+#define FSMC_PATTx_ATTHOLDx_2 (0x04U << FSMC_PATTx_ATTHOLDx_Pos) /*!< 0x00040000 */
+#define FSMC_PATTx_ATTHOLDx_3 (0x08U << FSMC_PATTx_ATTHOLDx_Pos) /*!< 0x00080000 */
+#define FSMC_PATTx_ATTHOLDx_4 (0x10U << FSMC_PATTx_ATTHOLDx_Pos) /*!< 0x00100000 */
+#define FSMC_PATTx_ATTHOLDx_5 (0x20U << FSMC_PATTx_ATTHOLDx_Pos) /*!< 0x00200000 */
+#define FSMC_PATTx_ATTHOLDx_6 (0x40U << FSMC_PATTx_ATTHOLDx_Pos) /*!< 0x00400000 */
+#define FSMC_PATTx_ATTHOLDx_7 (0x80U << FSMC_PATTx_ATTHOLDx_Pos) /*!< 0x00800000 */
+
+#define FSMC_PATTx_ATTHIZx_Pos (24U)
+#define FSMC_PATTx_ATTHIZx_Msk (0xFFU << FSMC_PATTx_ATTHIZx_Pos) /*!< 0xFF000000 */
+#define FSMC_PATTx_ATTHIZx FSMC_PATTx_ATTHIZx_Msk /*!< ATTHIZx[7:0] bits (Attribute memory x databus HiZ time) */
+#define FSMC_PATTx_ATTHIZx_0 (0x01U << FSMC_PATTx_ATTHIZx_Pos) /*!< 0x01000000 */
+#define FSMC_PATTx_ATTHIZx_1 (0x02U << FSMC_PATTx_ATTHIZx_Pos) /*!< 0x02000000 */
+#define FSMC_PATTx_ATTHIZx_2 (0x04U << FSMC_PATTx_ATTHIZx_Pos) /*!< 0x04000000 */
+#define FSMC_PATTx_ATTHIZx_3 (0x08U << FSMC_PATTx_ATTHIZx_Pos) /*!< 0x08000000 */
+#define FSMC_PATTx_ATTHIZx_4 (0x10U << FSMC_PATTx_ATTHIZx_Pos) /*!< 0x10000000 */
+#define FSMC_PATTx_ATTHIZx_5 (0x20U << FSMC_PATTx_ATTHIZx_Pos) /*!< 0x20000000 */
+#define FSMC_PATTx_ATTHIZx_6 (0x40U << FSMC_PATTx_ATTHIZx_Pos) /*!< 0x40000000 */
+#define FSMC_PATTx_ATTHIZx_7 (0x80U << FSMC_PATTx_ATTHIZx_Pos) /*!< 0x80000000 */
+
+/****************** Bit definition for FSMC_PIO4 register *******************/
+#define FSMC_PIO4_IOSET4_Pos (0U)
+#define FSMC_PIO4_IOSET4_Msk (0xFFU << FSMC_PIO4_IOSET4_Pos) /*!< 0x000000FF */
+#define FSMC_PIO4_IOSET4 FSMC_PIO4_IOSET4_Msk /*!< IOSET4[7:0] bits (I/O 4 setup time) */
+#define FSMC_PIO4_IOSET4_0 (0x01U << FSMC_PIO4_IOSET4_Pos) /*!< 0x00000001 */
+#define FSMC_PIO4_IOSET4_1 (0x02U << FSMC_PIO4_IOSET4_Pos) /*!< 0x00000002 */
+#define FSMC_PIO4_IOSET4_2 (0x04U << FSMC_PIO4_IOSET4_Pos) /*!< 0x00000004 */
+#define FSMC_PIO4_IOSET4_3 (0x08U << FSMC_PIO4_IOSET4_Pos) /*!< 0x00000008 */
+#define FSMC_PIO4_IOSET4_4 (0x10U << FSMC_PIO4_IOSET4_Pos) /*!< 0x00000010 */
+#define FSMC_PIO4_IOSET4_5 (0x20U << FSMC_PIO4_IOSET4_Pos) /*!< 0x00000020 */
+#define FSMC_PIO4_IOSET4_6 (0x40U << FSMC_PIO4_IOSET4_Pos) /*!< 0x00000040 */
+#define FSMC_PIO4_IOSET4_7 (0x80U << FSMC_PIO4_IOSET4_Pos) /*!< 0x00000080 */
+
+#define FSMC_PIO4_IOWAIT4_Pos (8U)
+#define FSMC_PIO4_IOWAIT4_Msk (0xFFU << FSMC_PIO4_IOWAIT4_Pos) /*!< 0x0000FF00 */
+#define FSMC_PIO4_IOWAIT4 FSMC_PIO4_IOWAIT4_Msk /*!< IOWAIT4[7:0] bits (I/O 4 wait time) */
+#define FSMC_PIO4_IOWAIT4_0 (0x01U << FSMC_PIO4_IOWAIT4_Pos) /*!< 0x00000100 */
+#define FSMC_PIO4_IOWAIT4_1 (0x02U << FSMC_PIO4_IOWAIT4_Pos) /*!< 0x00000200 */
+#define FSMC_PIO4_IOWAIT4_2 (0x04U << FSMC_PIO4_IOWAIT4_Pos) /*!< 0x00000400 */
+#define FSMC_PIO4_IOWAIT4_3 (0x08U << FSMC_PIO4_IOWAIT4_Pos) /*!< 0x00000800 */
+#define FSMC_PIO4_IOWAIT4_4 (0x10U << FSMC_PIO4_IOWAIT4_Pos) /*!< 0x00001000 */
+#define FSMC_PIO4_IOWAIT4_5 (0x20U << FSMC_PIO4_IOWAIT4_Pos) /*!< 0x00002000 */
+#define FSMC_PIO4_IOWAIT4_6 (0x40U << FSMC_PIO4_IOWAIT4_Pos) /*!< 0x00004000 */
+#define FSMC_PIO4_IOWAIT4_7 (0x80U << FSMC_PIO4_IOWAIT4_Pos) /*!< 0x00008000 */
+
+#define FSMC_PIO4_IOHOLD4_Pos (16U)
+#define FSMC_PIO4_IOHOLD4_Msk (0xFFU << FSMC_PIO4_IOHOLD4_Pos) /*!< 0x00FF0000 */
+#define FSMC_PIO4_IOHOLD4 FSMC_PIO4_IOHOLD4_Msk /*!< IOHOLD4[7:0] bits (I/O 4 hold time) */
+#define FSMC_PIO4_IOHOLD4_0 (0x01U << FSMC_PIO4_IOHOLD4_Pos) /*!< 0x00010000 */
+#define FSMC_PIO4_IOHOLD4_1 (0x02U << FSMC_PIO4_IOHOLD4_Pos) /*!< 0x00020000 */
+#define FSMC_PIO4_IOHOLD4_2 (0x04U << FSMC_PIO4_IOHOLD4_Pos) /*!< 0x00040000 */
+#define FSMC_PIO4_IOHOLD4_3 (0x08U << FSMC_PIO4_IOHOLD4_Pos) /*!< 0x00080000 */
+#define FSMC_PIO4_IOHOLD4_4 (0x10U << FSMC_PIO4_IOHOLD4_Pos) /*!< 0x00100000 */
+#define FSMC_PIO4_IOHOLD4_5 (0x20U << FSMC_PIO4_IOHOLD4_Pos) /*!< 0x00200000 */
+#define FSMC_PIO4_IOHOLD4_6 (0x40U << FSMC_PIO4_IOHOLD4_Pos) /*!< 0x00400000 */
+#define FSMC_PIO4_IOHOLD4_7 (0x80U << FSMC_PIO4_IOHOLD4_Pos) /*!< 0x00800000 */
+
+#define FSMC_PIO4_IOHIZ4_Pos (24U)
+#define FSMC_PIO4_IOHIZ4_Msk (0xFFU << FSMC_PIO4_IOHIZ4_Pos) /*!< 0xFF000000 */
+#define FSMC_PIO4_IOHIZ4 FSMC_PIO4_IOHIZ4_Msk /*!< IOHIZ4[7:0] bits (I/O 4 databus HiZ time) */
+#define FSMC_PIO4_IOHIZ4_0 (0x01U << FSMC_PIO4_IOHIZ4_Pos) /*!< 0x01000000 */
+#define FSMC_PIO4_IOHIZ4_1 (0x02U << FSMC_PIO4_IOHIZ4_Pos) /*!< 0x02000000 */
+#define FSMC_PIO4_IOHIZ4_2 (0x04U << FSMC_PIO4_IOHIZ4_Pos) /*!< 0x04000000 */
+#define FSMC_PIO4_IOHIZ4_3 (0x08U << FSMC_PIO4_IOHIZ4_Pos) /*!< 0x08000000 */
+#define FSMC_PIO4_IOHIZ4_4 (0x10U << FSMC_PIO4_IOHIZ4_Pos) /*!< 0x10000000 */
+#define FSMC_PIO4_IOHIZ4_5 (0x20U << FSMC_PIO4_IOHIZ4_Pos) /*!< 0x20000000 */
+#define FSMC_PIO4_IOHIZ4_6 (0x40U << FSMC_PIO4_IOHIZ4_Pos) /*!< 0x40000000 */
+#define FSMC_PIO4_IOHIZ4_7 (0x80U << FSMC_PIO4_IOHIZ4_Pos) /*!< 0x80000000 */
+
+/****************** Bit definition for FSMC_ECCR2 register ******************/
+#define FSMC_ECCR2_ECC2_Pos (0U)
+#define FSMC_ECCR2_ECC2_Msk (0xFFFFFFFFU << FSMC_ECCR2_ECC2_Pos) /*!< 0xFFFFFFFF */
+#define FSMC_ECCR2_ECC2 FSMC_ECCR2_ECC2_Msk /*!< ECC result */
+
+/****************** Bit definition for FSMC_ECCR3 register ******************/
+#define FSMC_ECCR3_ECC3_Pos (0U)
+#define FSMC_ECCR3_ECC3_Msk (0xFFFFFFFFU << FSMC_ECCR3_ECC3_Pos) /*!< 0xFFFFFFFF */
+#define FSMC_ECCR3_ECC3 FSMC_ECCR3_ECC3_Msk /*!< ECC result */
+
+/******************************************************************************/
+/* */
+/* SD host Interface */
+/* */
+/******************************************************************************/
+
+/****************** Bit definition for SDIO_POWER register ******************/
+#define SDIO_POWER_PWRCTRL_Pos (0U)
+#define SDIO_POWER_PWRCTRL_Msk (0x3U << SDIO_POWER_PWRCTRL_Pos) /*!< 0x00000003 */
+#define SDIO_POWER_PWRCTRL SDIO_POWER_PWRCTRL_Msk /*!< PWRCTRL[1:0] bits (Power supply control bits) */
+#define SDIO_POWER_PWRCTRL_0 (0x1U << SDIO_POWER_PWRCTRL_Pos) /*!< 0x01 */
+#define SDIO_POWER_PWRCTRL_1 (0x2U << SDIO_POWER_PWRCTRL_Pos) /*!< 0x02 */
+
+/****************** Bit definition for SDIO_CLKCR register ******************/
+#define SDIO_CLKCR_CLKDIV_Pos (0U)
+#define SDIO_CLKCR_CLKDIV_Msk (0xFFU << SDIO_CLKCR_CLKDIV_Pos) /*!< 0x000000FF */
+#define SDIO_CLKCR_CLKDIV SDIO_CLKCR_CLKDIV_Msk /*!< Clock divide factor */
+#define SDIO_CLKCR_CLKEN_Pos (8U)
+#define SDIO_CLKCR_CLKEN_Msk (0x1U << SDIO_CLKCR_CLKEN_Pos) /*!< 0x00000100 */
+#define SDIO_CLKCR_CLKEN SDIO_CLKCR_CLKEN_Msk /*!< Clock enable bit */
+#define SDIO_CLKCR_PWRSAV_Pos (9U)
+#define SDIO_CLKCR_PWRSAV_Msk (0x1U << SDIO_CLKCR_PWRSAV_Pos) /*!< 0x00000200 */
+#define SDIO_CLKCR_PWRSAV SDIO_CLKCR_PWRSAV_Msk /*!< Power saving configuration bit */
+#define SDIO_CLKCR_BYPASS_Pos (10U)
+#define SDIO_CLKCR_BYPASS_Msk (0x1U << SDIO_CLKCR_BYPASS_Pos) /*!< 0x00000400 */
+#define SDIO_CLKCR_BYPASS SDIO_CLKCR_BYPASS_Msk /*!< Clock divider bypass enable bit */
+
+#define SDIO_CLKCR_WIDBUS_Pos (11U)
+#define SDIO_CLKCR_WIDBUS_Msk (0x3U << SDIO_CLKCR_WIDBUS_Pos) /*!< 0x00001800 */
+#define SDIO_CLKCR_WIDBUS SDIO_CLKCR_WIDBUS_Msk /*!< WIDBUS[1:0] bits (Wide bus mode enable bit) */
+#define SDIO_CLKCR_WIDBUS_0 (0x1U << SDIO_CLKCR_WIDBUS_Pos) /*!< 0x0800 */
+#define SDIO_CLKCR_WIDBUS_1 (0x2U << SDIO_CLKCR_WIDBUS_Pos) /*!< 0x1000 */
+
+#define SDIO_CLKCR_NEGEDGE_Pos (13U)
+#define SDIO_CLKCR_NEGEDGE_Msk (0x1U << SDIO_CLKCR_NEGEDGE_Pos) /*!< 0x00002000 */
+#define SDIO_CLKCR_NEGEDGE SDIO_CLKCR_NEGEDGE_Msk /*!< SDIO_CK dephasing selection bit */
+#define SDIO_CLKCR_HWFC_EN_Pos (14U)
+#define SDIO_CLKCR_HWFC_EN_Msk (0x1U << SDIO_CLKCR_HWFC_EN_Pos) /*!< 0x00004000 */
+#define SDIO_CLKCR_HWFC_EN SDIO_CLKCR_HWFC_EN_Msk /*!< HW Flow Control enable */
+
+/******************* Bit definition for SDIO_ARG register *******************/
+#define SDIO_ARG_CMDARG_Pos (0U)
+#define SDIO_ARG_CMDARG_Msk (0xFFFFFFFFU << SDIO_ARG_CMDARG_Pos) /*!< 0xFFFFFFFF */
+#define SDIO_ARG_CMDARG SDIO_ARG_CMDARG_Msk /*!< Command argument */
+
+/******************* Bit definition for SDIO_CMD register *******************/
+#define SDIO_CMD_CMDINDEX_Pos (0U)
+#define SDIO_CMD_CMDINDEX_Msk (0x3FU << SDIO_CMD_CMDINDEX_Pos) /*!< 0x0000003F */
+#define SDIO_CMD_CMDINDEX SDIO_CMD_CMDINDEX_Msk /*!< Command Index */
+
+#define SDIO_CMD_WAITRESP_Pos (6U)
+#define SDIO_CMD_WAITRESP_Msk (0x3U << SDIO_CMD_WAITRESP_Pos) /*!< 0x000000C0 */
+#define SDIO_CMD_WAITRESP SDIO_CMD_WAITRESP_Msk /*!< WAITRESP[1:0] bits (Wait for response bits) */
+#define SDIO_CMD_WAITRESP_0 (0x1U << SDIO_CMD_WAITRESP_Pos) /*!< 0x0040 */
+#define SDIO_CMD_WAITRESP_1 (0x2U << SDIO_CMD_WAITRESP_Pos) /*!< 0x0080 */
+
+#define SDIO_CMD_WAITINT_Pos (8U)
+#define SDIO_CMD_WAITINT_Msk (0x1U << SDIO_CMD_WAITINT_Pos) /*!< 0x00000100 */
+#define SDIO_CMD_WAITINT SDIO_CMD_WAITINT_Msk /*!< CPSM Waits for Interrupt Request */
+#define SDIO_CMD_WAITPEND_Pos (9U)
+#define SDIO_CMD_WAITPEND_Msk (0x1U << SDIO_CMD_WAITPEND_Pos) /*!< 0x00000200 */
+#define SDIO_CMD_WAITPEND SDIO_CMD_WAITPEND_Msk /*!< CPSM Waits for ends of data transfer (CmdPend internal signal) */
+#define SDIO_CMD_CPSMEN_Pos (10U)
+#define SDIO_CMD_CPSMEN_Msk (0x1U << SDIO_CMD_CPSMEN_Pos) /*!< 0x00000400 */
+#define SDIO_CMD_CPSMEN SDIO_CMD_CPSMEN_Msk /*!< Command path state machine (CPSM) Enable bit */
+#define SDIO_CMD_SDIOSUSPEND_Pos (11U)
+#define SDIO_CMD_SDIOSUSPEND_Msk (0x1U << SDIO_CMD_SDIOSUSPEND_Pos) /*!< 0x00000800 */
+#define SDIO_CMD_SDIOSUSPEND SDIO_CMD_SDIOSUSPEND_Msk /*!< SD I/O suspend command */
+#define SDIO_CMD_ENCMDCOMPL_Pos (12U)
+#define SDIO_CMD_ENCMDCOMPL_Msk (0x1U << SDIO_CMD_ENCMDCOMPL_Pos) /*!< 0x00001000 */
+#define SDIO_CMD_ENCMDCOMPL SDIO_CMD_ENCMDCOMPL_Msk /*!< Enable CMD completion */
+#define SDIO_CMD_NIEN_Pos (13U)
+#define SDIO_CMD_NIEN_Msk (0x1U << SDIO_CMD_NIEN_Pos) /*!< 0x00002000 */
+#define SDIO_CMD_NIEN SDIO_CMD_NIEN_Msk /*!< Not Interrupt Enable */
+#define SDIO_CMD_CEATACMD_Pos (14U)
+#define SDIO_CMD_CEATACMD_Msk (0x1U << SDIO_CMD_CEATACMD_Pos) /*!< 0x00004000 */
+#define SDIO_CMD_CEATACMD SDIO_CMD_CEATACMD_Msk /*!< CE-ATA command */
+
+/***************** Bit definition for SDIO_RESPCMD register *****************/
+#define SDIO_RESPCMD_RESPCMD_Pos (0U)
+#define SDIO_RESPCMD_RESPCMD_Msk (0x3FU << SDIO_RESPCMD_RESPCMD_Pos) /*!< 0x0000003F */
+#define SDIO_RESPCMD_RESPCMD SDIO_RESPCMD_RESPCMD_Msk /*!< Response command index */
+
+/****************** Bit definition for SDIO_RESP0 register ******************/
+#define SDIO_RESP0_CARDSTATUS0_Pos (0U)
+#define SDIO_RESP0_CARDSTATUS0_Msk (0xFFFFFFFFU << SDIO_RESP0_CARDSTATUS0_Pos) /*!< 0xFFFFFFFF */
+#define SDIO_RESP0_CARDSTATUS0 SDIO_RESP0_CARDSTATUS0_Msk /*!< Card Status */
+
+/****************** Bit definition for SDIO_RESP1 register ******************/
+#define SDIO_RESP1_CARDSTATUS1_Pos (0U)
+#define SDIO_RESP1_CARDSTATUS1_Msk (0xFFFFFFFFU << SDIO_RESP1_CARDSTATUS1_Pos) /*!< 0xFFFFFFFF */
+#define SDIO_RESP1_CARDSTATUS1 SDIO_RESP1_CARDSTATUS1_Msk /*!< Card Status */
+
+/****************** Bit definition for SDIO_RESP2 register ******************/
+#define SDIO_RESP2_CARDSTATUS2_Pos (0U)
+#define SDIO_RESP2_CARDSTATUS2_Msk (0xFFFFFFFFU << SDIO_RESP2_CARDSTATUS2_Pos) /*!< 0xFFFFFFFF */
+#define SDIO_RESP2_CARDSTATUS2 SDIO_RESP2_CARDSTATUS2_Msk /*!< Card Status */
+
+/****************** Bit definition for SDIO_RESP3 register ******************/
+#define SDIO_RESP3_CARDSTATUS3_Pos (0U)
+#define SDIO_RESP3_CARDSTATUS3_Msk (0xFFFFFFFFU << SDIO_RESP3_CARDSTATUS3_Pos) /*!< 0xFFFFFFFF */
+#define SDIO_RESP3_CARDSTATUS3 SDIO_RESP3_CARDSTATUS3_Msk /*!< Card Status */
+
+/****************** Bit definition for SDIO_RESP4 register ******************/
+#define SDIO_RESP4_CARDSTATUS4_Pos (0U)
+#define SDIO_RESP4_CARDSTATUS4_Msk (0xFFFFFFFFU << SDIO_RESP4_CARDSTATUS4_Pos) /*!< 0xFFFFFFFF */
+#define SDIO_RESP4_CARDSTATUS4 SDIO_RESP4_CARDSTATUS4_Msk /*!< Card Status */
+
+/****************** Bit definition for SDIO_DTIMER register *****************/
+#define SDIO_DTIMER_DATATIME_Pos (0U)
+#define SDIO_DTIMER_DATATIME_Msk (0xFFFFFFFFU << SDIO_DTIMER_DATATIME_Pos) /*!< 0xFFFFFFFF */
+#define SDIO_DTIMER_DATATIME SDIO_DTIMER_DATATIME_Msk /*!< Data timeout period. */
+
+/****************** Bit definition for SDIO_DLEN register *******************/
+#define SDIO_DLEN_DATALENGTH_Pos (0U)
+#define SDIO_DLEN_DATALENGTH_Msk (0x1FFFFFFU << SDIO_DLEN_DATALENGTH_Pos) /*!< 0x01FFFFFF */
+#define SDIO_DLEN_DATALENGTH SDIO_DLEN_DATALENGTH_Msk /*!< Data length value */
+
+/****************** Bit definition for SDIO_DCTRL register ******************/
+#define SDIO_DCTRL_DTEN_Pos (0U)
+#define SDIO_DCTRL_DTEN_Msk (0x1U << SDIO_DCTRL_DTEN_Pos) /*!< 0x00000001 */
+#define SDIO_DCTRL_DTEN SDIO_DCTRL_DTEN_Msk /*!< Data transfer enabled bit */
+#define SDIO_DCTRL_DTDIR_Pos (1U)
+#define SDIO_DCTRL_DTDIR_Msk (0x1U << SDIO_DCTRL_DTDIR_Pos) /*!< 0x00000002 */
+#define SDIO_DCTRL_DTDIR SDIO_DCTRL_DTDIR_Msk /*!< Data transfer direction selection */
+#define SDIO_DCTRL_DTMODE_Pos (2U)
+#define SDIO_DCTRL_DTMODE_Msk (0x1U << SDIO_DCTRL_DTMODE_Pos) /*!< 0x00000004 */
+#define SDIO_DCTRL_DTMODE SDIO_DCTRL_DTMODE_Msk /*!< Data transfer mode selection */
+#define SDIO_DCTRL_DMAEN_Pos (3U)
+#define SDIO_DCTRL_DMAEN_Msk (0x1U << SDIO_DCTRL_DMAEN_Pos) /*!< 0x00000008 */
+#define SDIO_DCTRL_DMAEN SDIO_DCTRL_DMAEN_Msk /*!< DMA enabled bit */
+
+#define SDIO_DCTRL_DBLOCKSIZE_Pos (4U)
+#define SDIO_DCTRL_DBLOCKSIZE_Msk (0xFU << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x000000F0 */
+#define SDIO_DCTRL_DBLOCKSIZE SDIO_DCTRL_DBLOCKSIZE_Msk /*!< DBLOCKSIZE[3:0] bits (Data block size) */
+#define SDIO_DCTRL_DBLOCKSIZE_0 (0x1U << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0010 */
+#define SDIO_DCTRL_DBLOCKSIZE_1 (0x2U << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0020 */
+#define SDIO_DCTRL_DBLOCKSIZE_2 (0x4U << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0040 */
+#define SDIO_DCTRL_DBLOCKSIZE_3 (0x8U << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0080 */
+
+#define SDIO_DCTRL_RWSTART_Pos (8U)
+#define SDIO_DCTRL_RWSTART_Msk (0x1U << SDIO_DCTRL_RWSTART_Pos) /*!< 0x00000100 */
+#define SDIO_DCTRL_RWSTART SDIO_DCTRL_RWSTART_Msk /*!< Read wait start */
+#define SDIO_DCTRL_RWSTOP_Pos (9U)
+#define SDIO_DCTRL_RWSTOP_Msk (0x1U << SDIO_DCTRL_RWSTOP_Pos) /*!< 0x00000200 */
+#define SDIO_DCTRL_RWSTOP SDIO_DCTRL_RWSTOP_Msk /*!< Read wait stop */
+#define SDIO_DCTRL_RWMOD_Pos (10U)
+#define SDIO_DCTRL_RWMOD_Msk (0x1U << SDIO_DCTRL_RWMOD_Pos) /*!< 0x00000400 */
+#define SDIO_DCTRL_RWMOD SDIO_DCTRL_RWMOD_Msk /*!< Read wait mode */
+#define SDIO_DCTRL_SDIOEN_Pos (11U)
+#define SDIO_DCTRL_SDIOEN_Msk (0x1U << SDIO_DCTRL_SDIOEN_Pos) /*!< 0x00000800 */
+#define SDIO_DCTRL_SDIOEN SDIO_DCTRL_SDIOEN_Msk /*!< SD I/O enable functions */
+
+/****************** Bit definition for SDIO_DCOUNT register *****************/
+#define SDIO_DCOUNT_DATACOUNT_Pos (0U)
+#define SDIO_DCOUNT_DATACOUNT_Msk (0x1FFFFFFU << SDIO_DCOUNT_DATACOUNT_Pos) /*!< 0x01FFFFFF */
+#define SDIO_DCOUNT_DATACOUNT SDIO_DCOUNT_DATACOUNT_Msk /*!< Data count value */
+
+/****************** Bit definition for SDIO_STA register ********************/
+#define SDIO_STA_CCRCFAIL_Pos (0U)
+#define SDIO_STA_CCRCFAIL_Msk (0x1U << SDIO_STA_CCRCFAIL_Pos) /*!< 0x00000001 */
+#define SDIO_STA_CCRCFAIL SDIO_STA_CCRCFAIL_Msk /*!< Command response received (CRC check failed) */
+#define SDIO_STA_DCRCFAIL_Pos (1U)
+#define SDIO_STA_DCRCFAIL_Msk (0x1U << SDIO_STA_DCRCFAIL_Pos) /*!< 0x00000002 */
+#define SDIO_STA_DCRCFAIL SDIO_STA_DCRCFAIL_Msk /*!< Data block sent/received (CRC check failed) */
+#define SDIO_STA_CTIMEOUT_Pos (2U)
+#define SDIO_STA_CTIMEOUT_Msk (0x1U << SDIO_STA_CTIMEOUT_Pos) /*!< 0x00000004 */
+#define SDIO_STA_CTIMEOUT SDIO_STA_CTIMEOUT_Msk /*!< Command response timeout */
+#define SDIO_STA_DTIMEOUT_Pos (3U)
+#define SDIO_STA_DTIMEOUT_Msk (0x1U << SDIO_STA_DTIMEOUT_Pos) /*!< 0x00000008 */
+#define SDIO_STA_DTIMEOUT SDIO_STA_DTIMEOUT_Msk /*!< Data timeout */
+#define SDIO_STA_TXUNDERR_Pos (4U)
+#define SDIO_STA_TXUNDERR_Msk (0x1U << SDIO_STA_TXUNDERR_Pos) /*!< 0x00000010 */
+#define SDIO_STA_TXUNDERR SDIO_STA_TXUNDERR_Msk /*!< Transmit FIFO underrun error */
+#define SDIO_STA_RXOVERR_Pos (5U)
+#define SDIO_STA_RXOVERR_Msk (0x1U << SDIO_STA_RXOVERR_Pos) /*!< 0x00000020 */
+#define SDIO_STA_RXOVERR SDIO_STA_RXOVERR_Msk /*!< Received FIFO overrun error */
+#define SDIO_STA_CMDREND_Pos (6U)
+#define SDIO_STA_CMDREND_Msk (0x1U << SDIO_STA_CMDREND_Pos) /*!< 0x00000040 */
+#define SDIO_STA_CMDREND SDIO_STA_CMDREND_Msk /*!< Command response received (CRC check passed) */
+#define SDIO_STA_CMDSENT_Pos (7U)
+#define SDIO_STA_CMDSENT_Msk (0x1U << SDIO_STA_CMDSENT_Pos) /*!< 0x00000080 */
+#define SDIO_STA_CMDSENT SDIO_STA_CMDSENT_Msk /*!< Command sent (no response required) */
+#define SDIO_STA_DATAEND_Pos (8U)
+#define SDIO_STA_DATAEND_Msk (0x1U << SDIO_STA_DATAEND_Pos) /*!< 0x00000100 */
+#define SDIO_STA_DATAEND SDIO_STA_DATAEND_Msk /*!< Data end (data counter, SDIDCOUNT, is zero) */
+#define SDIO_STA_STBITERR_Pos (9U)
+#define SDIO_STA_STBITERR_Msk (0x1U << SDIO_STA_STBITERR_Pos) /*!< 0x00000200 */
+#define SDIO_STA_STBITERR SDIO_STA_STBITERR_Msk /*!< Start bit not detected on all data signals in wide bus mode */
+#define SDIO_STA_DBCKEND_Pos (10U)
+#define SDIO_STA_DBCKEND_Msk (0x1U << SDIO_STA_DBCKEND_Pos) /*!< 0x00000400 */
+#define SDIO_STA_DBCKEND SDIO_STA_DBCKEND_Msk /*!< Data block sent/received (CRC check passed) */
+#define SDIO_STA_CMDACT_Pos (11U)
+#define SDIO_STA_CMDACT_Msk (0x1U << SDIO_STA_CMDACT_Pos) /*!< 0x00000800 */
+#define SDIO_STA_CMDACT SDIO_STA_CMDACT_Msk /*!< Command transfer in progress */
+#define SDIO_STA_TXACT_Pos (12U)
+#define SDIO_STA_TXACT_Msk (0x1U << SDIO_STA_TXACT_Pos) /*!< 0x00001000 */
+#define SDIO_STA_TXACT SDIO_STA_TXACT_Msk /*!< Data transmit in progress */
+#define SDIO_STA_RXACT_Pos (13U)
+#define SDIO_STA_RXACT_Msk (0x1U << SDIO_STA_RXACT_Pos) /*!< 0x00002000 */
+#define SDIO_STA_RXACT SDIO_STA_RXACT_Msk /*!< Data receive in progress */
+#define SDIO_STA_TXFIFOHE_Pos (14U)
+#define SDIO_STA_TXFIFOHE_Msk (0x1U << SDIO_STA_TXFIFOHE_Pos) /*!< 0x00004000 */
+#define SDIO_STA_TXFIFOHE SDIO_STA_TXFIFOHE_Msk /*!< Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
+#define SDIO_STA_RXFIFOHF_Pos (15U)
+#define SDIO_STA_RXFIFOHF_Msk (0x1U << SDIO_STA_RXFIFOHF_Pos) /*!< 0x00008000 */
+#define SDIO_STA_RXFIFOHF SDIO_STA_RXFIFOHF_Msk /*!< Receive FIFO Half Full: there are at least 8 words in the FIFO */
+#define SDIO_STA_TXFIFOF_Pos (16U)
+#define SDIO_STA_TXFIFOF_Msk (0x1U << SDIO_STA_TXFIFOF_Pos) /*!< 0x00010000 */
+#define SDIO_STA_TXFIFOF SDIO_STA_TXFIFOF_Msk /*!< Transmit FIFO full */
+#define SDIO_STA_RXFIFOF_Pos (17U)
+#define SDIO_STA_RXFIFOF_Msk (0x1U << SDIO_STA_RXFIFOF_Pos) /*!< 0x00020000 */
+#define SDIO_STA_RXFIFOF SDIO_STA_RXFIFOF_Msk /*!< Receive FIFO full */
+#define SDIO_STA_TXFIFOE_Pos (18U)
+#define SDIO_STA_TXFIFOE_Msk (0x1U << SDIO_STA_TXFIFOE_Pos) /*!< 0x00040000 */
+#define SDIO_STA_TXFIFOE SDIO_STA_TXFIFOE_Msk /*!< Transmit FIFO empty */
+#define SDIO_STA_RXFIFOE_Pos (19U)
+#define SDIO_STA_RXFIFOE_Msk (0x1U << SDIO_STA_RXFIFOE_Pos) /*!< 0x00080000 */
+#define SDIO_STA_RXFIFOE SDIO_STA_RXFIFOE_Msk /*!< Receive FIFO empty */
+#define SDIO_STA_TXDAVL_Pos (20U)
+#define SDIO_STA_TXDAVL_Msk (0x1U << SDIO_STA_TXDAVL_Pos) /*!< 0x00100000 */
+#define SDIO_STA_TXDAVL SDIO_STA_TXDAVL_Msk /*!< Data available in transmit FIFO */
+#define SDIO_STA_RXDAVL_Pos (21U)
+#define SDIO_STA_RXDAVL_Msk (0x1U << SDIO_STA_RXDAVL_Pos) /*!< 0x00200000 */
+#define SDIO_STA_RXDAVL SDIO_STA_RXDAVL_Msk /*!< Data available in receive FIFO */
+#define SDIO_STA_SDIOIT_Pos (22U)
+#define SDIO_STA_SDIOIT_Msk (0x1U << SDIO_STA_SDIOIT_Pos) /*!< 0x00400000 */
+#define SDIO_STA_SDIOIT SDIO_STA_SDIOIT_Msk /*!< SDIO interrupt received */
+#define SDIO_STA_CEATAEND_Pos (23U)
+#define SDIO_STA_CEATAEND_Msk (0x1U << SDIO_STA_CEATAEND_Pos) /*!< 0x00800000 */
+#define SDIO_STA_CEATAEND SDIO_STA_CEATAEND_Msk /*!< CE-ATA command completion signal received for CMD61 */
+
+/******************* Bit definition for SDIO_ICR register *******************/
+#define SDIO_ICR_CCRCFAILC_Pos (0U)
+#define SDIO_ICR_CCRCFAILC_Msk (0x1U << SDIO_ICR_CCRCFAILC_Pos) /*!< 0x00000001 */
+#define SDIO_ICR_CCRCFAILC SDIO_ICR_CCRCFAILC_Msk /*!< CCRCFAIL flag clear bit */
+#define SDIO_ICR_DCRCFAILC_Pos (1U)
+#define SDIO_ICR_DCRCFAILC_Msk (0x1U << SDIO_ICR_DCRCFAILC_Pos) /*!< 0x00000002 */
+#define SDIO_ICR_DCRCFAILC SDIO_ICR_DCRCFAILC_Msk /*!< DCRCFAIL flag clear bit */
+#define SDIO_ICR_CTIMEOUTC_Pos (2U)
+#define SDIO_ICR_CTIMEOUTC_Msk (0x1U << SDIO_ICR_CTIMEOUTC_Pos) /*!< 0x00000004 */
+#define SDIO_ICR_CTIMEOUTC SDIO_ICR_CTIMEOUTC_Msk /*!< CTIMEOUT flag clear bit */
+#define SDIO_ICR_DTIMEOUTC_Pos (3U)
+#define SDIO_ICR_DTIMEOUTC_Msk (0x1U << SDIO_ICR_DTIMEOUTC_Pos) /*!< 0x00000008 */
+#define SDIO_ICR_DTIMEOUTC SDIO_ICR_DTIMEOUTC_Msk /*!< DTIMEOUT flag clear bit */
+#define SDIO_ICR_TXUNDERRC_Pos (4U)
+#define SDIO_ICR_TXUNDERRC_Msk (0x1U << SDIO_ICR_TXUNDERRC_Pos) /*!< 0x00000010 */
+#define SDIO_ICR_TXUNDERRC SDIO_ICR_TXUNDERRC_Msk /*!< TXUNDERR flag clear bit */
+#define SDIO_ICR_RXOVERRC_Pos (5U)
+#define SDIO_ICR_RXOVERRC_Msk (0x1U << SDIO_ICR_RXOVERRC_Pos) /*!< 0x00000020 */
+#define SDIO_ICR_RXOVERRC SDIO_ICR_RXOVERRC_Msk /*!< RXOVERR flag clear bit */
+#define SDIO_ICR_CMDRENDC_Pos (6U)
+#define SDIO_ICR_CMDRENDC_Msk (0x1U << SDIO_ICR_CMDRENDC_Pos) /*!< 0x00000040 */
+#define SDIO_ICR_CMDRENDC SDIO_ICR_CMDRENDC_Msk /*!< CMDREND flag clear bit */
+#define SDIO_ICR_CMDSENTC_Pos (7U)
+#define SDIO_ICR_CMDSENTC_Msk (0x1U << SDIO_ICR_CMDSENTC_Pos) /*!< 0x00000080 */
+#define SDIO_ICR_CMDSENTC SDIO_ICR_CMDSENTC_Msk /*!< CMDSENT flag clear bit */
+#define SDIO_ICR_DATAENDC_Pos (8U)
+#define SDIO_ICR_DATAENDC_Msk (0x1U << SDIO_ICR_DATAENDC_Pos) /*!< 0x00000100 */
+#define SDIO_ICR_DATAENDC SDIO_ICR_DATAENDC_Msk /*!< DATAEND flag clear bit */
+#define SDIO_ICR_STBITERRC_Pos (9U)
+#define SDIO_ICR_STBITERRC_Msk (0x1U << SDIO_ICR_STBITERRC_Pos) /*!< 0x00000200 */
+#define SDIO_ICR_STBITERRC SDIO_ICR_STBITERRC_Msk /*!< STBITERR flag clear bit */
+#define SDIO_ICR_DBCKENDC_Pos (10U)
+#define SDIO_ICR_DBCKENDC_Msk (0x1U << SDIO_ICR_DBCKENDC_Pos) /*!< 0x00000400 */
+#define SDIO_ICR_DBCKENDC SDIO_ICR_DBCKENDC_Msk /*!< DBCKEND flag clear bit */
+#define SDIO_ICR_SDIOITC_Pos (22U)
+#define SDIO_ICR_SDIOITC_Msk (0x1U << SDIO_ICR_SDIOITC_Pos) /*!< 0x00400000 */
+#define SDIO_ICR_SDIOITC SDIO_ICR_SDIOITC_Msk /*!< SDIOIT flag clear bit */
+#define SDIO_ICR_CEATAENDC_Pos (23U)
+#define SDIO_ICR_CEATAENDC_Msk (0x1U << SDIO_ICR_CEATAENDC_Pos) /*!< 0x00800000 */
+#define SDIO_ICR_CEATAENDC SDIO_ICR_CEATAENDC_Msk /*!< CEATAEND flag clear bit */
+
+/****************** Bit definition for SDIO_MASK register *******************/
+#define SDIO_MASK_CCRCFAILIE_Pos (0U)
+#define SDIO_MASK_CCRCFAILIE_Msk (0x1U << SDIO_MASK_CCRCFAILIE_Pos) /*!< 0x00000001 */
+#define SDIO_MASK_CCRCFAILIE SDIO_MASK_CCRCFAILIE_Msk /*!< Command CRC Fail Interrupt Enable */
+#define SDIO_MASK_DCRCFAILIE_Pos (1U)
+#define SDIO_MASK_DCRCFAILIE_Msk (0x1U << SDIO_MASK_DCRCFAILIE_Pos) /*!< 0x00000002 */
+#define SDIO_MASK_DCRCFAILIE SDIO_MASK_DCRCFAILIE_Msk /*!< Data CRC Fail Interrupt Enable */
+#define SDIO_MASK_CTIMEOUTIE_Pos (2U)
+#define SDIO_MASK_CTIMEOUTIE_Msk (0x1U << SDIO_MASK_CTIMEOUTIE_Pos) /*!< 0x00000004 */
+#define SDIO_MASK_CTIMEOUTIE SDIO_MASK_CTIMEOUTIE_Msk /*!< Command TimeOut Interrupt Enable */
+#define SDIO_MASK_DTIMEOUTIE_Pos (3U)
+#define SDIO_MASK_DTIMEOUTIE_Msk (0x1U << SDIO_MASK_DTIMEOUTIE_Pos) /*!< 0x00000008 */
+#define SDIO_MASK_DTIMEOUTIE SDIO_MASK_DTIMEOUTIE_Msk /*!< Data TimeOut Interrupt Enable */
+#define SDIO_MASK_TXUNDERRIE_Pos (4U)
+#define SDIO_MASK_TXUNDERRIE_Msk (0x1U << SDIO_MASK_TXUNDERRIE_Pos) /*!< 0x00000010 */
+#define SDIO_MASK_TXUNDERRIE SDIO_MASK_TXUNDERRIE_Msk /*!< Tx FIFO UnderRun Error Interrupt Enable */
+#define SDIO_MASK_RXOVERRIE_Pos (5U)
+#define SDIO_MASK_RXOVERRIE_Msk (0x1U << SDIO_MASK_RXOVERRIE_Pos) /*!< 0x00000020 */
+#define SDIO_MASK_RXOVERRIE SDIO_MASK_RXOVERRIE_Msk /*!< Rx FIFO OverRun Error Interrupt Enable */
+#define SDIO_MASK_CMDRENDIE_Pos (6U)
+#define SDIO_MASK_CMDRENDIE_Msk (0x1U << SDIO_MASK_CMDRENDIE_Pos) /*!< 0x00000040 */
+#define SDIO_MASK_CMDRENDIE SDIO_MASK_CMDRENDIE_Msk /*!< Command Response Received Interrupt Enable */
+#define SDIO_MASK_CMDSENTIE_Pos (7U)
+#define SDIO_MASK_CMDSENTIE_Msk (0x1U << SDIO_MASK_CMDSENTIE_Pos) /*!< 0x00000080 */
+#define SDIO_MASK_CMDSENTIE SDIO_MASK_CMDSENTIE_Msk /*!< Command Sent Interrupt Enable */
+#define SDIO_MASK_DATAENDIE_Pos (8U)
+#define SDIO_MASK_DATAENDIE_Msk (0x1U << SDIO_MASK_DATAENDIE_Pos) /*!< 0x00000100 */
+#define SDIO_MASK_DATAENDIE SDIO_MASK_DATAENDIE_Msk /*!< Data End Interrupt Enable */
+#define SDIO_MASK_STBITERRIE_Pos (9U)
+#define SDIO_MASK_STBITERRIE_Msk (0x1U << SDIO_MASK_STBITERRIE_Pos) /*!< 0x00000200 */
+#define SDIO_MASK_STBITERRIE SDIO_MASK_STBITERRIE_Msk /*!< Start Bit Error Interrupt Enable */
+#define SDIO_MASK_DBCKENDIE_Pos (10U)
+#define SDIO_MASK_DBCKENDIE_Msk (0x1U << SDIO_MASK_DBCKENDIE_Pos) /*!< 0x00000400 */
+#define SDIO_MASK_DBCKENDIE SDIO_MASK_DBCKENDIE_Msk /*!< Data Block End Interrupt Enable */
+#define SDIO_MASK_CMDACTIE_Pos (11U)
+#define SDIO_MASK_CMDACTIE_Msk (0x1U << SDIO_MASK_CMDACTIE_Pos) /*!< 0x00000800 */
+#define SDIO_MASK_CMDACTIE SDIO_MASK_CMDACTIE_Msk /*!< Command Acting Interrupt Enable */
+#define SDIO_MASK_TXACTIE_Pos (12U)
+#define SDIO_MASK_TXACTIE_Msk (0x1U << SDIO_MASK_TXACTIE_Pos) /*!< 0x00001000 */
+#define SDIO_MASK_TXACTIE SDIO_MASK_TXACTIE_Msk /*!< Data Transmit Acting Interrupt Enable */
+#define SDIO_MASK_RXACTIE_Pos (13U)
+#define SDIO_MASK_RXACTIE_Msk (0x1U << SDIO_MASK_RXACTIE_Pos) /*!< 0x00002000 */
+#define SDIO_MASK_RXACTIE SDIO_MASK_RXACTIE_Msk /*!< Data receive acting interrupt enabled */
+#define SDIO_MASK_TXFIFOHEIE_Pos (14U)
+#define SDIO_MASK_TXFIFOHEIE_Msk (0x1U << SDIO_MASK_TXFIFOHEIE_Pos) /*!< 0x00004000 */
+#define SDIO_MASK_TXFIFOHEIE SDIO_MASK_TXFIFOHEIE_Msk /*!< Tx FIFO Half Empty interrupt Enable */
+#define SDIO_MASK_RXFIFOHFIE_Pos (15U)
+#define SDIO_MASK_RXFIFOHFIE_Msk (0x1U << SDIO_MASK_RXFIFOHFIE_Pos) /*!< 0x00008000 */
+#define SDIO_MASK_RXFIFOHFIE SDIO_MASK_RXFIFOHFIE_Msk /*!< Rx FIFO Half Full interrupt Enable */
+#define SDIO_MASK_TXFIFOFIE_Pos (16U)
+#define SDIO_MASK_TXFIFOFIE_Msk (0x1U << SDIO_MASK_TXFIFOFIE_Pos) /*!< 0x00010000 */
+#define SDIO_MASK_TXFIFOFIE SDIO_MASK_TXFIFOFIE_Msk /*!< Tx FIFO Full interrupt Enable */
+#define SDIO_MASK_RXFIFOFIE_Pos (17U)
+#define SDIO_MASK_RXFIFOFIE_Msk (0x1U << SDIO_MASK_RXFIFOFIE_Pos) /*!< 0x00020000 */
+#define SDIO_MASK_RXFIFOFIE SDIO_MASK_RXFIFOFIE_Msk /*!< Rx FIFO Full interrupt Enable */
+#define SDIO_MASK_TXFIFOEIE_Pos (18U)
+#define SDIO_MASK_TXFIFOEIE_Msk (0x1U << SDIO_MASK_TXFIFOEIE_Pos) /*!< 0x00040000 */
+#define SDIO_MASK_TXFIFOEIE SDIO_MASK_TXFIFOEIE_Msk /*!< Tx FIFO Empty interrupt Enable */
+#define SDIO_MASK_RXFIFOEIE_Pos (19U)
+#define SDIO_MASK_RXFIFOEIE_Msk (0x1U << SDIO_MASK_RXFIFOEIE_Pos) /*!< 0x00080000 */
+#define SDIO_MASK_RXFIFOEIE SDIO_MASK_RXFIFOEIE_Msk /*!< Rx FIFO Empty interrupt Enable */
+#define SDIO_MASK_TXDAVLIE_Pos (20U)
+#define SDIO_MASK_TXDAVLIE_Msk (0x1U << SDIO_MASK_TXDAVLIE_Pos) /*!< 0x00100000 */
+#define SDIO_MASK_TXDAVLIE SDIO_MASK_TXDAVLIE_Msk /*!< Data available in Tx FIFO interrupt Enable */
+#define SDIO_MASK_RXDAVLIE_Pos (21U)
+#define SDIO_MASK_RXDAVLIE_Msk (0x1U << SDIO_MASK_RXDAVLIE_Pos) /*!< 0x00200000 */
+#define SDIO_MASK_RXDAVLIE SDIO_MASK_RXDAVLIE_Msk /*!< Data available in Rx FIFO interrupt Enable */
+#define SDIO_MASK_SDIOITIE_Pos (22U)
+#define SDIO_MASK_SDIOITIE_Msk (0x1U << SDIO_MASK_SDIOITIE_Pos) /*!< 0x00400000 */
+#define SDIO_MASK_SDIOITIE SDIO_MASK_SDIOITIE_Msk /*!< SDIO Mode Interrupt Received interrupt Enable */
+#define SDIO_MASK_CEATAENDIE_Pos (23U)
+#define SDIO_MASK_CEATAENDIE_Msk (0x1U << SDIO_MASK_CEATAENDIE_Pos) /*!< 0x00800000 */
+#define SDIO_MASK_CEATAENDIE SDIO_MASK_CEATAENDIE_Msk /*!< CE-ATA command completion signal received Interrupt Enable */
+
+/***************** Bit definition for SDIO_FIFOCNT register *****************/
+#define SDIO_FIFOCNT_FIFOCOUNT_Pos (0U)
+#define SDIO_FIFOCNT_FIFOCOUNT_Msk (0xFFFFFFU << SDIO_FIFOCNT_FIFOCOUNT_Pos) /*!< 0x00FFFFFF */
+#define SDIO_FIFOCNT_FIFOCOUNT SDIO_FIFOCNT_FIFOCOUNT_Msk /*!< Remaining number of words to be written to or read from the FIFO */
+
+/****************** Bit definition for SDIO_FIFO register *******************/
+#define SDIO_FIFO_FIFODATA_Pos (0U)
+#define SDIO_FIFO_FIFODATA_Msk (0xFFFFFFFFU << SDIO_FIFO_FIFODATA_Pos) /*!< 0xFFFFFFFF */
+#define SDIO_FIFO_FIFODATA SDIO_FIFO_FIFODATA_Msk /*!< Receive and transmit FIFO data */
+
+/******************************************************************************/
+/* */
+/* USB Device FS */
+/* */
+/******************************************************************************/
+
+/*!< Endpoint-specific registers */
+#define USB_EP0R USB_BASE /*!< Endpoint 0 register address */
+#define USB_EP1R (USB_BASE + 0x00000004) /*!< Endpoint 1 register address */
+#define USB_EP2R (USB_BASE + 0x00000008) /*!< Endpoint 2 register address */
+#define USB_EP3R (USB_BASE + 0x0000000C) /*!< Endpoint 3 register address */
+#define USB_EP4R (USB_BASE + 0x00000010) /*!< Endpoint 4 register address */
+#define USB_EP5R (USB_BASE + 0x00000014) /*!< Endpoint 5 register address */
+#define USB_EP6R (USB_BASE + 0x00000018) /*!< Endpoint 6 register address */
+#define USB_EP7R (USB_BASE + 0x0000001C) /*!< Endpoint 7 register address */
+
+/* bit positions */
+#define USB_EP_CTR_RX_Pos (15U)
+#define USB_EP_CTR_RX_Msk (0x1U << USB_EP_CTR_RX_Pos) /*!< 0x00008000 */
+#define USB_EP_CTR_RX USB_EP_CTR_RX_Msk /*!< EndPoint Correct TRansfer RX */
+#define USB_EP_DTOG_RX_Pos (14U)
+#define USB_EP_DTOG_RX_Msk (0x1U << USB_EP_DTOG_RX_Pos) /*!< 0x00004000 */
+#define USB_EP_DTOG_RX USB_EP_DTOG_RX_Msk /*!< EndPoint Data TOGGLE RX */
+#define USB_EPRX_STAT_Pos (12U)
+#define USB_EPRX_STAT_Msk (0x3U << USB_EPRX_STAT_Pos) /*!< 0x00003000 */
+#define USB_EPRX_STAT USB_EPRX_STAT_Msk /*!< EndPoint RX STATus bit field */
+#define USB_EP_SETUP_Pos (11U)
+#define USB_EP_SETUP_Msk (0x1U << USB_EP_SETUP_Pos) /*!< 0x00000800 */
+#define USB_EP_SETUP USB_EP_SETUP_Msk /*!< EndPoint SETUP */
+#define USB_EP_T_FIELD_Pos (9U)
+#define USB_EP_T_FIELD_Msk (0x3U << USB_EP_T_FIELD_Pos) /*!< 0x00000600 */
+#define USB_EP_T_FIELD USB_EP_T_FIELD_Msk /*!< EndPoint TYPE */
+#define USB_EP_KIND_Pos (8U)
+#define USB_EP_KIND_Msk (0x1U << USB_EP_KIND_Pos) /*!< 0x00000100 */
+#define USB_EP_KIND USB_EP_KIND_Msk /*!< EndPoint KIND */
+#define USB_EP_CTR_TX_Pos (7U)
+#define USB_EP_CTR_TX_Msk (0x1U << USB_EP_CTR_TX_Pos) /*!< 0x00000080 */
+#define USB_EP_CTR_TX USB_EP_CTR_TX_Msk /*!< EndPoint Correct TRansfer TX */
+#define USB_EP_DTOG_TX_Pos (6U)
+#define USB_EP_DTOG_TX_Msk (0x1U << USB_EP_DTOG_TX_Pos) /*!< 0x00000040 */
+#define USB_EP_DTOG_TX USB_EP_DTOG_TX_Msk /*!< EndPoint Data TOGGLE TX */
+#define USB_EPTX_STAT_Pos (4U)
+#define USB_EPTX_STAT_Msk (0x3U << USB_EPTX_STAT_Pos) /*!< 0x00000030 */
+#define USB_EPTX_STAT USB_EPTX_STAT_Msk /*!< EndPoint TX STATus bit field */
+#define USB_EPADDR_FIELD_Pos (0U)
+#define USB_EPADDR_FIELD_Msk (0xFU << USB_EPADDR_FIELD_Pos) /*!< 0x0000000F */
+#define USB_EPADDR_FIELD USB_EPADDR_FIELD_Msk /*!< EndPoint ADDRess FIELD */
+
+/* EndPoint REGister MASK (no toggle fields) */
+#define USB_EPREG_MASK (USB_EP_CTR_RX|USB_EP_SETUP|USB_EP_T_FIELD|USB_EP_KIND|USB_EP_CTR_TX|USB_EPADDR_FIELD)
+ /*!< EP_TYPE[1:0] EndPoint TYPE */
+#define USB_EP_TYPE_MASK_Pos (9U)
+#define USB_EP_TYPE_MASK_Msk (0x3U << USB_EP_TYPE_MASK_Pos) /*!< 0x00000600 */
+#define USB_EP_TYPE_MASK USB_EP_TYPE_MASK_Msk /*!< EndPoint TYPE Mask */
+#define USB_EP_BULK ((uint32_t)0x00000000) /*!< EndPoint BULK */
+#define USB_EP_CONTROL ((uint32_t)0x00000200) /*!< EndPoint CONTROL */
+#define USB_EP_ISOCHRONOUS ((uint32_t)0x00000400) /*!< EndPoint ISOCHRONOUS */
+#define USB_EP_INTERRUPT ((uint32_t)0x00000600) /*!< EndPoint INTERRUPT */
+#define USB_EP_T_MASK (~USB_EP_T_FIELD & USB_EPREG_MASK)
+
+#define USB_EPKIND_MASK (~USB_EP_KIND & USB_EPREG_MASK) /*!< EP_KIND EndPoint KIND */
+ /*!< STAT_TX[1:0] STATus for TX transfer */
+#define USB_EP_TX_DIS ((uint32_t)0x00000000) /*!< EndPoint TX DISabled */
+#define USB_EP_TX_STALL ((uint32_t)0x00000010) /*!< EndPoint TX STALLed */
+#define USB_EP_TX_NAK ((uint32_t)0x00000020) /*!< EndPoint TX NAKed */
+#define USB_EP_TX_VALID ((uint32_t)0x00000030) /*!< EndPoint TX VALID */
+#define USB_EPTX_DTOG1 ((uint32_t)0x00000010) /*!< EndPoint TX Data TOGgle bit1 */
+#define USB_EPTX_DTOG2 ((uint32_t)0x00000020) /*!< EndPoint TX Data TOGgle bit2 */
+#define USB_EPTX_DTOGMASK (USB_EPTX_STAT|USB_EPREG_MASK)
+ /*!< STAT_RX[1:0] STATus for RX transfer */
+#define USB_EP_RX_DIS ((uint32_t)0x00000000) /*!< EndPoint RX DISabled */
+#define USB_EP_RX_STALL ((uint32_t)0x00001000) /*!< EndPoint RX STALLed */
+#define USB_EP_RX_NAK ((uint32_t)0x00002000) /*!< EndPoint RX NAKed */
+#define USB_EP_RX_VALID ((uint32_t)0x00003000) /*!< EndPoint RX VALID */
+#define USB_EPRX_DTOG1 ((uint32_t)0x00001000) /*!< EndPoint RX Data TOGgle bit1 */
+#define USB_EPRX_DTOG2 ((uint32_t)0x00002000) /*!< EndPoint RX Data TOGgle bit1 */
+#define USB_EPRX_DTOGMASK (USB_EPRX_STAT|USB_EPREG_MASK)
+
+/******************* Bit definition for USB_EP0R register *******************/
+#define USB_EP0R_EA_Pos (0U)
+#define USB_EP0R_EA_Msk (0xFU << USB_EP0R_EA_Pos) /*!< 0x0000000F */
+#define USB_EP0R_EA USB_EP0R_EA_Msk /*!< Endpoint Address */
+
+#define USB_EP0R_STAT_TX_Pos (4U)
+#define USB_EP0R_STAT_TX_Msk (0x3U << USB_EP0R_STAT_TX_Pos) /*!< 0x00000030 */
+#define USB_EP0R_STAT_TX USB_EP0R_STAT_TX_Msk /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */
+#define USB_EP0R_STAT_TX_0 (0x1U << USB_EP0R_STAT_TX_Pos) /*!< 0x00000010 */
+#define USB_EP0R_STAT_TX_1 (0x2U << USB_EP0R_STAT_TX_Pos) /*!< 0x00000020 */
+
+#define USB_EP0R_DTOG_TX_Pos (6U)
+#define USB_EP0R_DTOG_TX_Msk (0x1U << USB_EP0R_DTOG_TX_Pos) /*!< 0x00000040 */
+#define USB_EP0R_DTOG_TX USB_EP0R_DTOG_TX_Msk /*!< Data Toggle, for transmission transfers */
+#define USB_EP0R_CTR_TX_Pos (7U)
+#define USB_EP0R_CTR_TX_Msk (0x1U << USB_EP0R_CTR_TX_Pos) /*!< 0x00000080 */
+#define USB_EP0R_CTR_TX USB_EP0R_CTR_TX_Msk /*!< Correct Transfer for transmission */
+#define USB_EP0R_EP_KIND_Pos (8U)
+#define USB_EP0R_EP_KIND_Msk (0x1U << USB_EP0R_EP_KIND_Pos) /*!< 0x00000100 */
+#define USB_EP0R_EP_KIND USB_EP0R_EP_KIND_Msk /*!< Endpoint Kind */
+
+#define USB_EP0R_EP_TYPE_Pos (9U)
+#define USB_EP0R_EP_TYPE_Msk (0x3U << USB_EP0R_EP_TYPE_Pos) /*!< 0x00000600 */
+#define USB_EP0R_EP_TYPE USB_EP0R_EP_TYPE_Msk /*!< EP_TYPE[1:0] bits (Endpoint type) */
+#define USB_EP0R_EP_TYPE_0 (0x1U << USB_EP0R_EP_TYPE_Pos) /*!< 0x00000200 */
+#define USB_EP0R_EP_TYPE_1 (0x2U << USB_EP0R_EP_TYPE_Pos) /*!< 0x00000400 */
+
+#define USB_EP0R_SETUP_Pos (11U)
+#define USB_EP0R_SETUP_Msk (0x1U << USB_EP0R_SETUP_Pos) /*!< 0x00000800 */
+#define USB_EP0R_SETUP USB_EP0R_SETUP_Msk /*!< Setup transaction completed */
+
+#define USB_EP0R_STAT_RX_Pos (12U)
+#define USB_EP0R_STAT_RX_Msk (0x3U << USB_EP0R_STAT_RX_Pos) /*!< 0x00003000 */
+#define USB_EP0R_STAT_RX USB_EP0R_STAT_RX_Msk /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */
+#define USB_EP0R_STAT_RX_0 (0x1U << USB_EP0R_STAT_RX_Pos) /*!< 0x00001000 */
+#define USB_EP0R_STAT_RX_1 (0x2U << USB_EP0R_STAT_RX_Pos) /*!< 0x00002000 */
+
+#define USB_EP0R_DTOG_RX_Pos (14U)
+#define USB_EP0R_DTOG_RX_Msk (0x1U << USB_EP0R_DTOG_RX_Pos) /*!< 0x00004000 */
+#define USB_EP0R_DTOG_RX USB_EP0R_DTOG_RX_Msk /*!< Data Toggle, for reception transfers */
+#define USB_EP0R_CTR_RX_Pos (15U)
+#define USB_EP0R_CTR_RX_Msk (0x1U << USB_EP0R_CTR_RX_Pos) /*!< 0x00008000 */
+#define USB_EP0R_CTR_RX USB_EP0R_CTR_RX_Msk /*!< Correct Transfer for reception */
+
+/******************* Bit definition for USB_EP1R register *******************/
+#define USB_EP1R_EA_Pos (0U)
+#define USB_EP1R_EA_Msk (0xFU << USB_EP1R_EA_Pos) /*!< 0x0000000F */
+#define USB_EP1R_EA USB_EP1R_EA_Msk /*!< Endpoint Address */
+
+#define USB_EP1R_STAT_TX_Pos (4U)
+#define USB_EP1R_STAT_TX_Msk (0x3U << USB_EP1R_STAT_TX_Pos) /*!< 0x00000030 */
+#define USB_EP1R_STAT_TX USB_EP1R_STAT_TX_Msk /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */
+#define USB_EP1R_STAT_TX_0 (0x1U << USB_EP1R_STAT_TX_Pos) /*!< 0x00000010 */
+#define USB_EP1R_STAT_TX_1 (0x2U << USB_EP1R_STAT_TX_Pos) /*!< 0x00000020 */
+
+#define USB_EP1R_DTOG_TX_Pos (6U)
+#define USB_EP1R_DTOG_TX_Msk (0x1U << USB_EP1R_DTOG_TX_Pos) /*!< 0x00000040 */
+#define USB_EP1R_DTOG_TX USB_EP1R_DTOG_TX_Msk /*!< Data Toggle, for transmission transfers */
+#define USB_EP1R_CTR_TX_Pos (7U)
+#define USB_EP1R_CTR_TX_Msk (0x1U << USB_EP1R_CTR_TX_Pos) /*!< 0x00000080 */
+#define USB_EP1R_CTR_TX USB_EP1R_CTR_TX_Msk /*!< Correct Transfer for transmission */
+#define USB_EP1R_EP_KIND_Pos (8U)
+#define USB_EP1R_EP_KIND_Msk (0x1U << USB_EP1R_EP_KIND_Pos) /*!< 0x00000100 */
+#define USB_EP1R_EP_KIND USB_EP1R_EP_KIND_Msk /*!< Endpoint Kind */
+
+#define USB_EP1R_EP_TYPE_Pos (9U)
+#define USB_EP1R_EP_TYPE_Msk (0x3U << USB_EP1R_EP_TYPE_Pos) /*!< 0x00000600 */
+#define USB_EP1R_EP_TYPE USB_EP1R_EP_TYPE_Msk /*!< EP_TYPE[1:0] bits (Endpoint type) */
+#define USB_EP1R_EP_TYPE_0 (0x1U << USB_EP1R_EP_TYPE_Pos) /*!< 0x00000200 */
+#define USB_EP1R_EP_TYPE_1 (0x2U << USB_EP1R_EP_TYPE_Pos) /*!< 0x00000400 */
+
+#define USB_EP1R_SETUP_Pos (11U)
+#define USB_EP1R_SETUP_Msk (0x1U << USB_EP1R_SETUP_Pos) /*!< 0x00000800 */
+#define USB_EP1R_SETUP USB_EP1R_SETUP_Msk /*!< Setup transaction completed */
+
+#define USB_EP1R_STAT_RX_Pos (12U)
+#define USB_EP1R_STAT_RX_Msk (0x3U << USB_EP1R_STAT_RX_Pos) /*!< 0x00003000 */
+#define USB_EP1R_STAT_RX USB_EP1R_STAT_RX_Msk /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */
+#define USB_EP1R_STAT_RX_0 (0x1U << USB_EP1R_STAT_RX_Pos) /*!< 0x00001000 */
+#define USB_EP1R_STAT_RX_1 (0x2U << USB_EP1R_STAT_RX_Pos) /*!< 0x00002000 */
+
+#define USB_EP1R_DTOG_RX_Pos (14U)
+#define USB_EP1R_DTOG_RX_Msk (0x1U << USB_EP1R_DTOG_RX_Pos) /*!< 0x00004000 */
+#define USB_EP1R_DTOG_RX USB_EP1R_DTOG_RX_Msk /*!< Data Toggle, for reception transfers */
+#define USB_EP1R_CTR_RX_Pos (15U)
+#define USB_EP1R_CTR_RX_Msk (0x1U << USB_EP1R_CTR_RX_Pos) /*!< 0x00008000 */
+#define USB_EP1R_CTR_RX USB_EP1R_CTR_RX_Msk /*!< Correct Transfer for reception */
+
+/******************* Bit definition for USB_EP2R register *******************/
+#define USB_EP2R_EA_Pos (0U)
+#define USB_EP2R_EA_Msk (0xFU << USB_EP2R_EA_Pos) /*!< 0x0000000F */
+#define USB_EP2R_EA USB_EP2R_EA_Msk /*!< Endpoint Address */
+
+#define USB_EP2R_STAT_TX_Pos (4U)
+#define USB_EP2R_STAT_TX_Msk (0x3U << USB_EP2R_STAT_TX_Pos) /*!< 0x00000030 */
+#define USB_EP2R_STAT_TX USB_EP2R_STAT_TX_Msk /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */
+#define USB_EP2R_STAT_TX_0 (0x1U << USB_EP2R_STAT_TX_Pos) /*!< 0x00000010 */
+#define USB_EP2R_STAT_TX_1 (0x2U << USB_EP2R_STAT_TX_Pos) /*!< 0x00000020 */
+
+#define USB_EP2R_DTOG_TX_Pos (6U)
+#define USB_EP2R_DTOG_TX_Msk (0x1U << USB_EP2R_DTOG_TX_Pos) /*!< 0x00000040 */
+#define USB_EP2R_DTOG_TX USB_EP2R_DTOG_TX_Msk /*!< Data Toggle, for transmission transfers */
+#define USB_EP2R_CTR_TX_Pos (7U)
+#define USB_EP2R_CTR_TX_Msk (0x1U << USB_EP2R_CTR_TX_Pos) /*!< 0x00000080 */
+#define USB_EP2R_CTR_TX USB_EP2R_CTR_TX_Msk /*!< Correct Transfer for transmission */
+#define USB_EP2R_EP_KIND_Pos (8U)
+#define USB_EP2R_EP_KIND_Msk (0x1U << USB_EP2R_EP_KIND_Pos) /*!< 0x00000100 */
+#define USB_EP2R_EP_KIND USB_EP2R_EP_KIND_Msk /*!< Endpoint Kind */
+
+#define USB_EP2R_EP_TYPE_Pos (9U)
+#define USB_EP2R_EP_TYPE_Msk (0x3U << USB_EP2R_EP_TYPE_Pos) /*!< 0x00000600 */
+#define USB_EP2R_EP_TYPE USB_EP2R_EP_TYPE_Msk /*!< EP_TYPE[1:0] bits (Endpoint type) */
+#define USB_EP2R_EP_TYPE_0 (0x1U << USB_EP2R_EP_TYPE_Pos) /*!< 0x00000200 */
+#define USB_EP2R_EP_TYPE_1 (0x2U << USB_EP2R_EP_TYPE_Pos) /*!< 0x00000400 */
+
+#define USB_EP2R_SETUP_Pos (11U)
+#define USB_EP2R_SETUP_Msk (0x1U << USB_EP2R_SETUP_Pos) /*!< 0x00000800 */
+#define USB_EP2R_SETUP USB_EP2R_SETUP_Msk /*!< Setup transaction completed */
+
+#define USB_EP2R_STAT_RX_Pos (12U)
+#define USB_EP2R_STAT_RX_Msk (0x3U << USB_EP2R_STAT_RX_Pos) /*!< 0x00003000 */
+#define USB_EP2R_STAT_RX USB_EP2R_STAT_RX_Msk /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */
+#define USB_EP2R_STAT_RX_0 (0x1U << USB_EP2R_STAT_RX_Pos) /*!< 0x00001000 */
+#define USB_EP2R_STAT_RX_1 (0x2U << USB_EP2R_STAT_RX_Pos) /*!< 0x00002000 */
+
+#define USB_EP2R_DTOG_RX_Pos (14U)
+#define USB_EP2R_DTOG_RX_Msk (0x1U << USB_EP2R_DTOG_RX_Pos) /*!< 0x00004000 */
+#define USB_EP2R_DTOG_RX USB_EP2R_DTOG_RX_Msk /*!< Data Toggle, for reception transfers */
+#define USB_EP2R_CTR_RX_Pos (15U)
+#define USB_EP2R_CTR_RX_Msk (0x1U << USB_EP2R_CTR_RX_Pos) /*!< 0x00008000 */
+#define USB_EP2R_CTR_RX USB_EP2R_CTR_RX_Msk /*!< Correct Transfer for reception */
+
+/******************* Bit definition for USB_EP3R register *******************/
+#define USB_EP3R_EA_Pos (0U)
+#define USB_EP3R_EA_Msk (0xFU << USB_EP3R_EA_Pos) /*!< 0x0000000F */
+#define USB_EP3R_EA USB_EP3R_EA_Msk /*!< Endpoint Address */
+
+#define USB_EP3R_STAT_TX_Pos (4U)
+#define USB_EP3R_STAT_TX_Msk (0x3U << USB_EP3R_STAT_TX_Pos) /*!< 0x00000030 */
+#define USB_EP3R_STAT_TX USB_EP3R_STAT_TX_Msk /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */
+#define USB_EP3R_STAT_TX_0 (0x1U << USB_EP3R_STAT_TX_Pos) /*!< 0x00000010 */
+#define USB_EP3R_STAT_TX_1 (0x2U << USB_EP3R_STAT_TX_Pos) /*!< 0x00000020 */
+
+#define USB_EP3R_DTOG_TX_Pos (6U)
+#define USB_EP3R_DTOG_TX_Msk (0x1U << USB_EP3R_DTOG_TX_Pos) /*!< 0x00000040 */
+#define USB_EP3R_DTOG_TX USB_EP3R_DTOG_TX_Msk /*!< Data Toggle, for transmission transfers */
+#define USB_EP3R_CTR_TX_Pos (7U)
+#define USB_EP3R_CTR_TX_Msk (0x1U << USB_EP3R_CTR_TX_Pos) /*!< 0x00000080 */
+#define USB_EP3R_CTR_TX USB_EP3R_CTR_TX_Msk /*!< Correct Transfer for transmission */
+#define USB_EP3R_EP_KIND_Pos (8U)
+#define USB_EP3R_EP_KIND_Msk (0x1U << USB_EP3R_EP_KIND_Pos) /*!< 0x00000100 */
+#define USB_EP3R_EP_KIND USB_EP3R_EP_KIND_Msk /*!< Endpoint Kind */
+
+#define USB_EP3R_EP_TYPE_Pos (9U)
+#define USB_EP3R_EP_TYPE_Msk (0x3U << USB_EP3R_EP_TYPE_Pos) /*!< 0x00000600 */
+#define USB_EP3R_EP_TYPE USB_EP3R_EP_TYPE_Msk /*!< EP_TYPE[1:0] bits (Endpoint type) */
+#define USB_EP3R_EP_TYPE_0 (0x1U << USB_EP3R_EP_TYPE_Pos) /*!< 0x00000200 */
+#define USB_EP3R_EP_TYPE_1 (0x2U << USB_EP3R_EP_TYPE_Pos) /*!< 0x00000400 */
+
+#define USB_EP3R_SETUP_Pos (11U)
+#define USB_EP3R_SETUP_Msk (0x1U << USB_EP3R_SETUP_Pos) /*!< 0x00000800 */
+#define USB_EP3R_SETUP USB_EP3R_SETUP_Msk /*!< Setup transaction completed */
+
+#define USB_EP3R_STAT_RX_Pos (12U)
+#define USB_EP3R_STAT_RX_Msk (0x3U << USB_EP3R_STAT_RX_Pos) /*!< 0x00003000 */
+#define USB_EP3R_STAT_RX USB_EP3R_STAT_RX_Msk /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */
+#define USB_EP3R_STAT_RX_0 (0x1U << USB_EP3R_STAT_RX_Pos) /*!< 0x00001000 */
+#define USB_EP3R_STAT_RX_1 (0x2U << USB_EP3R_STAT_RX_Pos) /*!< 0x00002000 */
+
+#define USB_EP3R_DTOG_RX_Pos (14U)
+#define USB_EP3R_DTOG_RX_Msk (0x1U << USB_EP3R_DTOG_RX_Pos) /*!< 0x00004000 */
+#define USB_EP3R_DTOG_RX USB_EP3R_DTOG_RX_Msk /*!< Data Toggle, for reception transfers */
+#define USB_EP3R_CTR_RX_Pos (15U)
+#define USB_EP3R_CTR_RX_Msk (0x1U << USB_EP3R_CTR_RX_Pos) /*!< 0x00008000 */
+#define USB_EP3R_CTR_RX USB_EP3R_CTR_RX_Msk /*!< Correct Transfer for reception */
+
+/******************* Bit definition for USB_EP4R register *******************/
+#define USB_EP4R_EA_Pos (0U)
+#define USB_EP4R_EA_Msk (0xFU << USB_EP4R_EA_Pos) /*!< 0x0000000F */
+#define USB_EP4R_EA USB_EP4R_EA_Msk /*!< Endpoint Address */
+
+#define USB_EP4R_STAT_TX_Pos (4U)
+#define USB_EP4R_STAT_TX_Msk (0x3U << USB_EP4R_STAT_TX_Pos) /*!< 0x00000030 */
+#define USB_EP4R_STAT_TX USB_EP4R_STAT_TX_Msk /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */
+#define USB_EP4R_STAT_TX_0 (0x1U << USB_EP4R_STAT_TX_Pos) /*!< 0x00000010 */
+#define USB_EP4R_STAT_TX_1 (0x2U << USB_EP4R_STAT_TX_Pos) /*!< 0x00000020 */
+
+#define USB_EP4R_DTOG_TX_Pos (6U)
+#define USB_EP4R_DTOG_TX_Msk (0x1U << USB_EP4R_DTOG_TX_Pos) /*!< 0x00000040 */
+#define USB_EP4R_DTOG_TX USB_EP4R_DTOG_TX_Msk /*!< Data Toggle, for transmission transfers */
+#define USB_EP4R_CTR_TX_Pos (7U)
+#define USB_EP4R_CTR_TX_Msk (0x1U << USB_EP4R_CTR_TX_Pos) /*!< 0x00000080 */
+#define USB_EP4R_CTR_TX USB_EP4R_CTR_TX_Msk /*!< Correct Transfer for transmission */
+#define USB_EP4R_EP_KIND_Pos (8U)
+#define USB_EP4R_EP_KIND_Msk (0x1U << USB_EP4R_EP_KIND_Pos) /*!< 0x00000100 */
+#define USB_EP4R_EP_KIND USB_EP4R_EP_KIND_Msk /*!< Endpoint Kind */
+
+#define USB_EP4R_EP_TYPE_Pos (9U)
+#define USB_EP4R_EP_TYPE_Msk (0x3U << USB_EP4R_EP_TYPE_Pos) /*!< 0x00000600 */
+#define USB_EP4R_EP_TYPE USB_EP4R_EP_TYPE_Msk /*!< EP_TYPE[1:0] bits (Endpoint type) */
+#define USB_EP4R_EP_TYPE_0 (0x1U << USB_EP4R_EP_TYPE_Pos) /*!< 0x00000200 */
+#define USB_EP4R_EP_TYPE_1 (0x2U << USB_EP4R_EP_TYPE_Pos) /*!< 0x00000400 */
+
+#define USB_EP4R_SETUP_Pos (11U)
+#define USB_EP4R_SETUP_Msk (0x1U << USB_EP4R_SETUP_Pos) /*!< 0x00000800 */
+#define USB_EP4R_SETUP USB_EP4R_SETUP_Msk /*!< Setup transaction completed */
+
+#define USB_EP4R_STAT_RX_Pos (12U)
+#define USB_EP4R_STAT_RX_Msk (0x3U << USB_EP4R_STAT_RX_Pos) /*!< 0x00003000 */
+#define USB_EP4R_STAT_RX USB_EP4R_STAT_RX_Msk /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */
+#define USB_EP4R_STAT_RX_0 (0x1U << USB_EP4R_STAT_RX_Pos) /*!< 0x00001000 */
+#define USB_EP4R_STAT_RX_1 (0x2U << USB_EP4R_STAT_RX_Pos) /*!< 0x00002000 */
+
+#define USB_EP4R_DTOG_RX_Pos (14U)
+#define USB_EP4R_DTOG_RX_Msk (0x1U << USB_EP4R_DTOG_RX_Pos) /*!< 0x00004000 */
+#define USB_EP4R_DTOG_RX USB_EP4R_DTOG_RX_Msk /*!< Data Toggle, for reception transfers */
+#define USB_EP4R_CTR_RX_Pos (15U)
+#define USB_EP4R_CTR_RX_Msk (0x1U << USB_EP4R_CTR_RX_Pos) /*!< 0x00008000 */
+#define USB_EP4R_CTR_RX USB_EP4R_CTR_RX_Msk /*!< Correct Transfer for reception */
+
+/******************* Bit definition for USB_EP5R register *******************/
+#define USB_EP5R_EA_Pos (0U)
+#define USB_EP5R_EA_Msk (0xFU << USB_EP5R_EA_Pos) /*!< 0x0000000F */
+#define USB_EP5R_EA USB_EP5R_EA_Msk /*!< Endpoint Address */
+
+#define USB_EP5R_STAT_TX_Pos (4U)
+#define USB_EP5R_STAT_TX_Msk (0x3U << USB_EP5R_STAT_TX_Pos) /*!< 0x00000030 */
+#define USB_EP5R_STAT_TX USB_EP5R_STAT_TX_Msk /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */
+#define USB_EP5R_STAT_TX_0 (0x1U << USB_EP5R_STAT_TX_Pos) /*!< 0x00000010 */
+#define USB_EP5R_STAT_TX_1 (0x2U << USB_EP5R_STAT_TX_Pos) /*!< 0x00000020 */
+
+#define USB_EP5R_DTOG_TX_Pos (6U)
+#define USB_EP5R_DTOG_TX_Msk (0x1U << USB_EP5R_DTOG_TX_Pos) /*!< 0x00000040 */
+#define USB_EP5R_DTOG_TX USB_EP5R_DTOG_TX_Msk /*!< Data Toggle, for transmission transfers */
+#define USB_EP5R_CTR_TX_Pos (7U)
+#define USB_EP5R_CTR_TX_Msk (0x1U << USB_EP5R_CTR_TX_Pos) /*!< 0x00000080 */
+#define USB_EP5R_CTR_TX USB_EP5R_CTR_TX_Msk /*!< Correct Transfer for transmission */
+#define USB_EP5R_EP_KIND_Pos (8U)
+#define USB_EP5R_EP_KIND_Msk (0x1U << USB_EP5R_EP_KIND_Pos) /*!< 0x00000100 */
+#define USB_EP5R_EP_KIND USB_EP5R_EP_KIND_Msk /*!< Endpoint Kind */
+
+#define USB_EP5R_EP_TYPE_Pos (9U)
+#define USB_EP5R_EP_TYPE_Msk (0x3U << USB_EP5R_EP_TYPE_Pos) /*!< 0x00000600 */
+#define USB_EP5R_EP_TYPE USB_EP5R_EP_TYPE_Msk /*!< EP_TYPE[1:0] bits (Endpoint type) */
+#define USB_EP5R_EP_TYPE_0 (0x1U << USB_EP5R_EP_TYPE_Pos) /*!< 0x00000200 */
+#define USB_EP5R_EP_TYPE_1 (0x2U << USB_EP5R_EP_TYPE_Pos) /*!< 0x00000400 */
+
+#define USB_EP5R_SETUP_Pos (11U)
+#define USB_EP5R_SETUP_Msk (0x1U << USB_EP5R_SETUP_Pos) /*!< 0x00000800 */
+#define USB_EP5R_SETUP USB_EP5R_SETUP_Msk /*!< Setup transaction completed */
+
+#define USB_EP5R_STAT_RX_Pos (12U)
+#define USB_EP5R_STAT_RX_Msk (0x3U << USB_EP5R_STAT_RX_Pos) /*!< 0x00003000 */
+#define USB_EP5R_STAT_RX USB_EP5R_STAT_RX_Msk /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */
+#define USB_EP5R_STAT_RX_0 (0x1U << USB_EP5R_STAT_RX_Pos) /*!< 0x00001000 */
+#define USB_EP5R_STAT_RX_1 (0x2U << USB_EP5R_STAT_RX_Pos) /*!< 0x00002000 */
+
+#define USB_EP5R_DTOG_RX_Pos (14U)
+#define USB_EP5R_DTOG_RX_Msk (0x1U << USB_EP5R_DTOG_RX_Pos) /*!< 0x00004000 */
+#define USB_EP5R_DTOG_RX USB_EP5R_DTOG_RX_Msk /*!< Data Toggle, for reception transfers */
+#define USB_EP5R_CTR_RX_Pos (15U)
+#define USB_EP5R_CTR_RX_Msk (0x1U << USB_EP5R_CTR_RX_Pos) /*!< 0x00008000 */
+#define USB_EP5R_CTR_RX USB_EP5R_CTR_RX_Msk /*!< Correct Transfer for reception */
+
+/******************* Bit definition for USB_EP6R register *******************/
+#define USB_EP6R_EA_Pos (0U)
+#define USB_EP6R_EA_Msk (0xFU << USB_EP6R_EA_Pos) /*!< 0x0000000F */
+#define USB_EP6R_EA USB_EP6R_EA_Msk /*!< Endpoint Address */
+
+#define USB_EP6R_STAT_TX_Pos (4U)
+#define USB_EP6R_STAT_TX_Msk (0x3U << USB_EP6R_STAT_TX_Pos) /*!< 0x00000030 */
+#define USB_EP6R_STAT_TX USB_EP6R_STAT_TX_Msk /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */
+#define USB_EP6R_STAT_TX_0 (0x1U << USB_EP6R_STAT_TX_Pos) /*!< 0x00000010 */
+#define USB_EP6R_STAT_TX_1 (0x2U << USB_EP6R_STAT_TX_Pos) /*!< 0x00000020 */
+
+#define USB_EP6R_DTOG_TX_Pos (6U)
+#define USB_EP6R_DTOG_TX_Msk (0x1U << USB_EP6R_DTOG_TX_Pos) /*!< 0x00000040 */
+#define USB_EP6R_DTOG_TX USB_EP6R_DTOG_TX_Msk /*!< Data Toggle, for transmission transfers */
+#define USB_EP6R_CTR_TX_Pos (7U)
+#define USB_EP6R_CTR_TX_Msk (0x1U << USB_EP6R_CTR_TX_Pos) /*!< 0x00000080 */
+#define USB_EP6R_CTR_TX USB_EP6R_CTR_TX_Msk /*!< Correct Transfer for transmission */
+#define USB_EP6R_EP_KIND_Pos (8U)
+#define USB_EP6R_EP_KIND_Msk (0x1U << USB_EP6R_EP_KIND_Pos) /*!< 0x00000100 */
+#define USB_EP6R_EP_KIND USB_EP6R_EP_KIND_Msk /*!< Endpoint Kind */
+
+#define USB_EP6R_EP_TYPE_Pos (9U)
+#define USB_EP6R_EP_TYPE_Msk (0x3U << USB_EP6R_EP_TYPE_Pos) /*!< 0x00000600 */
+#define USB_EP6R_EP_TYPE USB_EP6R_EP_TYPE_Msk /*!< EP_TYPE[1:0] bits (Endpoint type) */
+#define USB_EP6R_EP_TYPE_0 (0x1U << USB_EP6R_EP_TYPE_Pos) /*!< 0x00000200 */
+#define USB_EP6R_EP_TYPE_1 (0x2U << USB_EP6R_EP_TYPE_Pos) /*!< 0x00000400 */
+
+#define USB_EP6R_SETUP_Pos (11U)
+#define USB_EP6R_SETUP_Msk (0x1U << USB_EP6R_SETUP_Pos) /*!< 0x00000800 */
+#define USB_EP6R_SETUP USB_EP6R_SETUP_Msk /*!< Setup transaction completed */
+
+#define USB_EP6R_STAT_RX_Pos (12U)
+#define USB_EP6R_STAT_RX_Msk (0x3U << USB_EP6R_STAT_RX_Pos) /*!< 0x00003000 */
+#define USB_EP6R_STAT_RX USB_EP6R_STAT_RX_Msk /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */
+#define USB_EP6R_STAT_RX_0 (0x1U << USB_EP6R_STAT_RX_Pos) /*!< 0x00001000 */
+#define USB_EP6R_STAT_RX_1 (0x2U << USB_EP6R_STAT_RX_Pos) /*!< 0x00002000 */
+
+#define USB_EP6R_DTOG_RX_Pos (14U)
+#define USB_EP6R_DTOG_RX_Msk (0x1U << USB_EP6R_DTOG_RX_Pos) /*!< 0x00004000 */
+#define USB_EP6R_DTOG_RX USB_EP6R_DTOG_RX_Msk /*!< Data Toggle, for reception transfers */
+#define USB_EP6R_CTR_RX_Pos (15U)
+#define USB_EP6R_CTR_RX_Msk (0x1U << USB_EP6R_CTR_RX_Pos) /*!< 0x00008000 */
+#define USB_EP6R_CTR_RX USB_EP6R_CTR_RX_Msk /*!< Correct Transfer for reception */
+
+/******************* Bit definition for USB_EP7R register *******************/
+#define USB_EP7R_EA_Pos (0U)
+#define USB_EP7R_EA_Msk (0xFU << USB_EP7R_EA_Pos) /*!< 0x0000000F */
+#define USB_EP7R_EA USB_EP7R_EA_Msk /*!< Endpoint Address */
+
+#define USB_EP7R_STAT_TX_Pos (4U)
+#define USB_EP7R_STAT_TX_Msk (0x3U << USB_EP7R_STAT_TX_Pos) /*!< 0x00000030 */
+#define USB_EP7R_STAT_TX USB_EP7R_STAT_TX_Msk /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */
+#define USB_EP7R_STAT_TX_0 (0x1U << USB_EP7R_STAT_TX_Pos) /*!< 0x00000010 */
+#define USB_EP7R_STAT_TX_1 (0x2U << USB_EP7R_STAT_TX_Pos) /*!< 0x00000020 */
+
+#define USB_EP7R_DTOG_TX_Pos (6U)
+#define USB_EP7R_DTOG_TX_Msk (0x1U << USB_EP7R_DTOG_TX_Pos) /*!< 0x00000040 */
+#define USB_EP7R_DTOG_TX USB_EP7R_DTOG_TX_Msk /*!< Data Toggle, for transmission transfers */
+#define USB_EP7R_CTR_TX_Pos (7U)
+#define USB_EP7R_CTR_TX_Msk (0x1U << USB_EP7R_CTR_TX_Pos) /*!< 0x00000080 */
+#define USB_EP7R_CTR_TX USB_EP7R_CTR_TX_Msk /*!< Correct Transfer for transmission */
+#define USB_EP7R_EP_KIND_Pos (8U)
+#define USB_EP7R_EP_KIND_Msk (0x1U << USB_EP7R_EP_KIND_Pos) /*!< 0x00000100 */
+#define USB_EP7R_EP_KIND USB_EP7R_EP_KIND_Msk /*!< Endpoint Kind */
+
+#define USB_EP7R_EP_TYPE_Pos (9U)
+#define USB_EP7R_EP_TYPE_Msk (0x3U << USB_EP7R_EP_TYPE_Pos) /*!< 0x00000600 */
+#define USB_EP7R_EP_TYPE USB_EP7R_EP_TYPE_Msk /*!< EP_TYPE[1:0] bits (Endpoint type) */
+#define USB_EP7R_EP_TYPE_0 (0x1U << USB_EP7R_EP_TYPE_Pos) /*!< 0x00000200 */
+#define USB_EP7R_EP_TYPE_1 (0x2U << USB_EP7R_EP_TYPE_Pos) /*!< 0x00000400 */
+
+#define USB_EP7R_SETUP_Pos (11U)
+#define USB_EP7R_SETUP_Msk (0x1U << USB_EP7R_SETUP_Pos) /*!< 0x00000800 */
+#define USB_EP7R_SETUP USB_EP7R_SETUP_Msk /*!< Setup transaction completed */
+
+#define USB_EP7R_STAT_RX_Pos (12U)
+#define USB_EP7R_STAT_RX_Msk (0x3U << USB_EP7R_STAT_RX_Pos) /*!< 0x00003000 */
+#define USB_EP7R_STAT_RX USB_EP7R_STAT_RX_Msk /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */
+#define USB_EP7R_STAT_RX_0 (0x1U << USB_EP7R_STAT_RX_Pos) /*!< 0x00001000 */
+#define USB_EP7R_STAT_RX_1 (0x2U << USB_EP7R_STAT_RX_Pos) /*!< 0x00002000 */
+
+#define USB_EP7R_DTOG_RX_Pos (14U)
+#define USB_EP7R_DTOG_RX_Msk (0x1U << USB_EP7R_DTOG_RX_Pos) /*!< 0x00004000 */
+#define USB_EP7R_DTOG_RX USB_EP7R_DTOG_RX_Msk /*!< Data Toggle, for reception transfers */
+#define USB_EP7R_CTR_RX_Pos (15U)
+#define USB_EP7R_CTR_RX_Msk (0x1U << USB_EP7R_CTR_RX_Pos) /*!< 0x00008000 */
+#define USB_EP7R_CTR_RX USB_EP7R_CTR_RX_Msk /*!< Correct Transfer for reception */
+
+/*!< Common registers */
+/******************* Bit definition for USB_CNTR register *******************/
+#define USB_CNTR_FRES_Pos (0U)
+#define USB_CNTR_FRES_Msk (0x1U << USB_CNTR_FRES_Pos) /*!< 0x00000001 */
+#define USB_CNTR_FRES USB_CNTR_FRES_Msk /*!< Force USB Reset */
+#define USB_CNTR_PDWN_Pos (1U)
+#define USB_CNTR_PDWN_Msk (0x1U << USB_CNTR_PDWN_Pos) /*!< 0x00000002 */
+#define USB_CNTR_PDWN USB_CNTR_PDWN_Msk /*!< Power down */
+#define USB_CNTR_LP_MODE_Pos (2U)
+#define USB_CNTR_LP_MODE_Msk (0x1U << USB_CNTR_LP_MODE_Pos) /*!< 0x00000004 */
+#define USB_CNTR_LP_MODE USB_CNTR_LP_MODE_Msk /*!< Low-power mode */
+#define USB_CNTR_FSUSP_Pos (3U)
+#define USB_CNTR_FSUSP_Msk (0x1U << USB_CNTR_FSUSP_Pos) /*!< 0x00000008 */
+#define USB_CNTR_FSUSP USB_CNTR_FSUSP_Msk /*!< Force suspend */
+#define USB_CNTR_RESUME_Pos (4U)
+#define USB_CNTR_RESUME_Msk (0x1U << USB_CNTR_RESUME_Pos) /*!< 0x00000010 */
+#define USB_CNTR_RESUME USB_CNTR_RESUME_Msk /*!< Resume request */
+#define USB_CNTR_ESOFM_Pos (8U)
+#define USB_CNTR_ESOFM_Msk (0x1U << USB_CNTR_ESOFM_Pos) /*!< 0x00000100 */
+#define USB_CNTR_ESOFM USB_CNTR_ESOFM_Msk /*!< Expected Start Of Frame Interrupt Mask */
+#define USB_CNTR_SOFM_Pos (9U)
+#define USB_CNTR_SOFM_Msk (0x1U << USB_CNTR_SOFM_Pos) /*!< 0x00000200 */
+#define USB_CNTR_SOFM USB_CNTR_SOFM_Msk /*!< Start Of Frame Interrupt Mask */
+#define USB_CNTR_RESETM_Pos (10U)
+#define USB_CNTR_RESETM_Msk (0x1U << USB_CNTR_RESETM_Pos) /*!< 0x00000400 */
+#define USB_CNTR_RESETM USB_CNTR_RESETM_Msk /*!< RESET Interrupt Mask */
+#define USB_CNTR_SUSPM_Pos (11U)
+#define USB_CNTR_SUSPM_Msk (0x1U << USB_CNTR_SUSPM_Pos) /*!< 0x00000800 */
+#define USB_CNTR_SUSPM USB_CNTR_SUSPM_Msk /*!< Suspend mode Interrupt Mask */
+#define USB_CNTR_WKUPM_Pos (12U)
+#define USB_CNTR_WKUPM_Msk (0x1U << USB_CNTR_WKUPM_Pos) /*!< 0x00001000 */
+#define USB_CNTR_WKUPM USB_CNTR_WKUPM_Msk /*!< Wakeup Interrupt Mask */
+#define USB_CNTR_ERRM_Pos (13U)
+#define USB_CNTR_ERRM_Msk (0x1U << USB_CNTR_ERRM_Pos) /*!< 0x00002000 */
+#define USB_CNTR_ERRM USB_CNTR_ERRM_Msk /*!< Error Interrupt Mask */
+#define USB_CNTR_PMAOVRM_Pos (14U)
+#define USB_CNTR_PMAOVRM_Msk (0x1U << USB_CNTR_PMAOVRM_Pos) /*!< 0x00004000 */
+#define USB_CNTR_PMAOVRM USB_CNTR_PMAOVRM_Msk /*!< Packet Memory Area Over / Underrun Interrupt Mask */
+#define USB_CNTR_CTRM_Pos (15U)
+#define USB_CNTR_CTRM_Msk (0x1U << USB_CNTR_CTRM_Pos) /*!< 0x00008000 */
+#define USB_CNTR_CTRM USB_CNTR_CTRM_Msk /*!< Correct Transfer Interrupt Mask */
+
+/******************* Bit definition for USB_ISTR register *******************/
+#define USB_ISTR_EP_ID_Pos (0U)
+#define USB_ISTR_EP_ID_Msk (0xFU << USB_ISTR_EP_ID_Pos) /*!< 0x0000000F */
+#define USB_ISTR_EP_ID USB_ISTR_EP_ID_Msk /*!< Endpoint Identifier */
+#define USB_ISTR_DIR_Pos (4U)
+#define USB_ISTR_DIR_Msk (0x1U << USB_ISTR_DIR_Pos) /*!< 0x00000010 */
+#define USB_ISTR_DIR USB_ISTR_DIR_Msk /*!< Direction of transaction */
+#define USB_ISTR_ESOF_Pos (8U)
+#define USB_ISTR_ESOF_Msk (0x1U << USB_ISTR_ESOF_Pos) /*!< 0x00000100 */
+#define USB_ISTR_ESOF USB_ISTR_ESOF_Msk /*!< Expected Start Of Frame */
+#define USB_ISTR_SOF_Pos (9U)
+#define USB_ISTR_SOF_Msk (0x1U << USB_ISTR_SOF_Pos) /*!< 0x00000200 */
+#define USB_ISTR_SOF USB_ISTR_SOF_Msk /*!< Start Of Frame */
+#define USB_ISTR_RESET_Pos (10U)
+#define USB_ISTR_RESET_Msk (0x1U << USB_ISTR_RESET_Pos) /*!< 0x00000400 */
+#define USB_ISTR_RESET USB_ISTR_RESET_Msk /*!< USB RESET request */
+#define USB_ISTR_SUSP_Pos (11U)
+#define USB_ISTR_SUSP_Msk (0x1U << USB_ISTR_SUSP_Pos) /*!< 0x00000800 */
+#define USB_ISTR_SUSP USB_ISTR_SUSP_Msk /*!< Suspend mode request */
+#define USB_ISTR_WKUP_Pos (12U)
+#define USB_ISTR_WKUP_Msk (0x1U << USB_ISTR_WKUP_Pos) /*!< 0x00001000 */
+#define USB_ISTR_WKUP USB_ISTR_WKUP_Msk /*!< Wake up */
+#define USB_ISTR_ERR_Pos (13U)
+#define USB_ISTR_ERR_Msk (0x1U << USB_ISTR_ERR_Pos) /*!< 0x00002000 */
+#define USB_ISTR_ERR USB_ISTR_ERR_Msk /*!< Error */
+#define USB_ISTR_PMAOVR_Pos (14U)
+#define USB_ISTR_PMAOVR_Msk (0x1U << USB_ISTR_PMAOVR_Pos) /*!< 0x00004000 */
+#define USB_ISTR_PMAOVR USB_ISTR_PMAOVR_Msk /*!< Packet Memory Area Over / Underrun */
+#define USB_ISTR_CTR_Pos (15U)
+#define USB_ISTR_CTR_Msk (0x1U << USB_ISTR_CTR_Pos) /*!< 0x00008000 */
+#define USB_ISTR_CTR USB_ISTR_CTR_Msk /*!< Correct Transfer */
+
+/******************* Bit definition for USB_FNR register ********************/
+#define USB_FNR_FN_Pos (0U)
+#define USB_FNR_FN_Msk (0x7FFU << USB_FNR_FN_Pos) /*!< 0x000007FF */
+#define USB_FNR_FN USB_FNR_FN_Msk /*!< Frame Number */
+#define USB_FNR_LSOF_Pos (11U)
+#define USB_FNR_LSOF_Msk (0x3U << USB_FNR_LSOF_Pos) /*!< 0x00001800 */
+#define USB_FNR_LSOF USB_FNR_LSOF_Msk /*!< Lost SOF */
+#define USB_FNR_LCK_Pos (13U)
+#define USB_FNR_LCK_Msk (0x1U << USB_FNR_LCK_Pos) /*!< 0x00002000 */
+#define USB_FNR_LCK USB_FNR_LCK_Msk /*!< Locked */
+#define USB_FNR_RXDM_Pos (14U)
+#define USB_FNR_RXDM_Msk (0x1U << USB_FNR_RXDM_Pos) /*!< 0x00004000 */
+#define USB_FNR_RXDM USB_FNR_RXDM_Msk /*!< Receive Data - Line Status */
+#define USB_FNR_RXDP_Pos (15U)
+#define USB_FNR_RXDP_Msk (0x1U << USB_FNR_RXDP_Pos) /*!< 0x00008000 */
+#define USB_FNR_RXDP USB_FNR_RXDP_Msk /*!< Receive Data + Line Status */
+
+/****************** Bit definition for USB_DADDR register *******************/
+#define USB_DADDR_ADD_Pos (0U)
+#define USB_DADDR_ADD_Msk (0x7FU << USB_DADDR_ADD_Pos) /*!< 0x0000007F */
+#define USB_DADDR_ADD USB_DADDR_ADD_Msk /*!< ADD[6:0] bits (Device Address) */
+#define USB_DADDR_ADD0_Pos (0U)
+#define USB_DADDR_ADD0_Msk (0x1U << USB_DADDR_ADD0_Pos) /*!< 0x00000001 */
+#define USB_DADDR_ADD0 USB_DADDR_ADD0_Msk /*!< Bit 0 */
+#define USB_DADDR_ADD1_Pos (1U)
+#define USB_DADDR_ADD1_Msk (0x1U << USB_DADDR_ADD1_Pos) /*!< 0x00000002 */
+#define USB_DADDR_ADD1 USB_DADDR_ADD1_Msk /*!< Bit 1 */
+#define USB_DADDR_ADD2_Pos (2U)
+#define USB_DADDR_ADD2_Msk (0x1U << USB_DADDR_ADD2_Pos) /*!< 0x00000004 */
+#define USB_DADDR_ADD2 USB_DADDR_ADD2_Msk /*!< Bit 2 */
+#define USB_DADDR_ADD3_Pos (3U)
+#define USB_DADDR_ADD3_Msk (0x1U << USB_DADDR_ADD3_Pos) /*!< 0x00000008 */
+#define USB_DADDR_ADD3 USB_DADDR_ADD3_Msk /*!< Bit 3 */
+#define USB_DADDR_ADD4_Pos (4U)
+#define USB_DADDR_ADD4_Msk (0x1U << USB_DADDR_ADD4_Pos) /*!< 0x00000010 */
+#define USB_DADDR_ADD4 USB_DADDR_ADD4_Msk /*!< Bit 4 */
+#define USB_DADDR_ADD5_Pos (5U)
+#define USB_DADDR_ADD5_Msk (0x1U << USB_DADDR_ADD5_Pos) /*!< 0x00000020 */
+#define USB_DADDR_ADD5 USB_DADDR_ADD5_Msk /*!< Bit 5 */
+#define USB_DADDR_ADD6_Pos (6U)
+#define USB_DADDR_ADD6_Msk (0x1U << USB_DADDR_ADD6_Pos) /*!< 0x00000040 */
+#define USB_DADDR_ADD6 USB_DADDR_ADD6_Msk /*!< Bit 6 */
+
+#define USB_DADDR_EF_Pos (7U)
+#define USB_DADDR_EF_Msk (0x1U << USB_DADDR_EF_Pos) /*!< 0x00000080 */
+#define USB_DADDR_EF USB_DADDR_EF_Msk /*!< Enable Function */
+
+/****************** Bit definition for USB_BTABLE register ******************/
+#define USB_BTABLE_BTABLE_Pos (3U)
+#define USB_BTABLE_BTABLE_Msk (0x1FFFU << USB_BTABLE_BTABLE_Pos) /*!< 0x0000FFF8 */
+#define USB_BTABLE_BTABLE USB_BTABLE_BTABLE_Msk /*!< Buffer Table */
+
+/*!< Buffer descriptor table */
+/***************** Bit definition for USB_ADDR0_TX register *****************/
+#define USB_ADDR0_TX_ADDR0_TX_Pos (1U)
+#define USB_ADDR0_TX_ADDR0_TX_Msk (0x7FFFU << USB_ADDR0_TX_ADDR0_TX_Pos) /*!< 0x0000FFFE */
+#define USB_ADDR0_TX_ADDR0_TX USB_ADDR0_TX_ADDR0_TX_Msk /*!< Transmission Buffer Address 0 */
+
+/***************** Bit definition for USB_ADDR1_TX register *****************/
+#define USB_ADDR1_TX_ADDR1_TX_Pos (1U)
+#define USB_ADDR1_TX_ADDR1_TX_Msk (0x7FFFU << USB_ADDR1_TX_ADDR1_TX_Pos) /*!< 0x0000FFFE */
+#define USB_ADDR1_TX_ADDR1_TX USB_ADDR1_TX_ADDR1_TX_Msk /*!< Transmission Buffer Address 1 */
+
+/***************** Bit definition for USB_ADDR2_TX register *****************/
+#define USB_ADDR2_TX_ADDR2_TX_Pos (1U)
+#define USB_ADDR2_TX_ADDR2_TX_Msk (0x7FFFU << USB_ADDR2_TX_ADDR2_TX_Pos) /*!< 0x0000FFFE */
+#define USB_ADDR2_TX_ADDR2_TX USB_ADDR2_TX_ADDR2_TX_Msk /*!< Transmission Buffer Address 2 */
+
+/***************** Bit definition for USB_ADDR3_TX register *****************/
+#define USB_ADDR3_TX_ADDR3_TX_Pos (1U)
+#define USB_ADDR3_TX_ADDR3_TX_Msk (0x7FFFU << USB_ADDR3_TX_ADDR3_TX_Pos) /*!< 0x0000FFFE */
+#define USB_ADDR3_TX_ADDR3_TX USB_ADDR3_TX_ADDR3_TX_Msk /*!< Transmission Buffer Address 3 */
+
+/***************** Bit definition for USB_ADDR4_TX register *****************/
+#define USB_ADDR4_TX_ADDR4_TX_Pos (1U)
+#define USB_ADDR4_TX_ADDR4_TX_Msk (0x7FFFU << USB_ADDR4_TX_ADDR4_TX_Pos) /*!< 0x0000FFFE */
+#define USB_ADDR4_TX_ADDR4_TX USB_ADDR4_TX_ADDR4_TX_Msk /*!< Transmission Buffer Address 4 */
+
+/***************** Bit definition for USB_ADDR5_TX register *****************/
+#define USB_ADDR5_TX_ADDR5_TX_Pos (1U)
+#define USB_ADDR5_TX_ADDR5_TX_Msk (0x7FFFU << USB_ADDR5_TX_ADDR5_TX_Pos) /*!< 0x0000FFFE */
+#define USB_ADDR5_TX_ADDR5_TX USB_ADDR5_TX_ADDR5_TX_Msk /*!< Transmission Buffer Address 5 */
+
+/***************** Bit definition for USB_ADDR6_TX register *****************/
+#define USB_ADDR6_TX_ADDR6_TX_Pos (1U)
+#define USB_ADDR6_TX_ADDR6_TX_Msk (0x7FFFU << USB_ADDR6_TX_ADDR6_TX_Pos) /*!< 0x0000FFFE */
+#define USB_ADDR6_TX_ADDR6_TX USB_ADDR6_TX_ADDR6_TX_Msk /*!< Transmission Buffer Address 6 */
+
+/***************** Bit definition for USB_ADDR7_TX register *****************/
+#define USB_ADDR7_TX_ADDR7_TX_Pos (1U)
+#define USB_ADDR7_TX_ADDR7_TX_Msk (0x7FFFU << USB_ADDR7_TX_ADDR7_TX_Pos) /*!< 0x0000FFFE */
+#define USB_ADDR7_TX_ADDR7_TX USB_ADDR7_TX_ADDR7_TX_Msk /*!< Transmission Buffer Address 7 */
+
+/*----------------------------------------------------------------------------*/
+
+/***************** Bit definition for USB_COUNT0_TX register ****************/
+#define USB_COUNT0_TX_COUNT0_TX_Pos (0U)
+#define USB_COUNT0_TX_COUNT0_TX_Msk (0x3FFU << USB_COUNT0_TX_COUNT0_TX_Pos) /*!< 0x000003FF */
+#define USB_COUNT0_TX_COUNT0_TX USB_COUNT0_TX_COUNT0_TX_Msk /*!< Transmission Byte Count 0 */
+
+/***************** Bit definition for USB_COUNT1_TX register ****************/
+#define USB_COUNT1_TX_COUNT1_TX_Pos (0U)
+#define USB_COUNT1_TX_COUNT1_TX_Msk (0x3FFU << USB_COUNT1_TX_COUNT1_TX_Pos) /*!< 0x000003FF */
+#define USB_COUNT1_TX_COUNT1_TX USB_COUNT1_TX_COUNT1_TX_Msk /*!< Transmission Byte Count 1 */
+
+/***************** Bit definition for USB_COUNT2_TX register ****************/
+#define USB_COUNT2_TX_COUNT2_TX_Pos (0U)
+#define USB_COUNT2_TX_COUNT2_TX_Msk (0x3FFU << USB_COUNT2_TX_COUNT2_TX_Pos) /*!< 0x000003FF */
+#define USB_COUNT2_TX_COUNT2_TX USB_COUNT2_TX_COUNT2_TX_Msk /*!< Transmission Byte Count 2 */
+
+/***************** Bit definition for USB_COUNT3_TX register ****************/
+#define USB_COUNT3_TX_COUNT3_TX_Pos (0U)
+#define USB_COUNT3_TX_COUNT3_TX_Msk (0x3FFU << USB_COUNT3_TX_COUNT3_TX_Pos) /*!< 0x000003FF */
+#define USB_COUNT3_TX_COUNT3_TX USB_COUNT3_TX_COUNT3_TX_Msk /*!< Transmission Byte Count 3 */
+
+/***************** Bit definition for USB_COUNT4_TX register ****************/
+#define USB_COUNT4_TX_COUNT4_TX_Pos (0U)
+#define USB_COUNT4_TX_COUNT4_TX_Msk (0x3FFU << USB_COUNT4_TX_COUNT4_TX_Pos) /*!< 0x000003FF */
+#define USB_COUNT4_TX_COUNT4_TX USB_COUNT4_TX_COUNT4_TX_Msk /*!< Transmission Byte Count 4 */
+
+/***************** Bit definition for USB_COUNT5_TX register ****************/
+#define USB_COUNT5_TX_COUNT5_TX_Pos (0U)
+#define USB_COUNT5_TX_COUNT5_TX_Msk (0x3FFU << USB_COUNT5_TX_COUNT5_TX_Pos) /*!< 0x000003FF */
+#define USB_COUNT5_TX_COUNT5_TX USB_COUNT5_TX_COUNT5_TX_Msk /*!< Transmission Byte Count 5 */
+
+/***************** Bit definition for USB_COUNT6_TX register ****************/
+#define USB_COUNT6_TX_COUNT6_TX_Pos (0U)
+#define USB_COUNT6_TX_COUNT6_TX_Msk (0x3FFU << USB_COUNT6_TX_COUNT6_TX_Pos) /*!< 0x000003FF */
+#define USB_COUNT6_TX_COUNT6_TX USB_COUNT6_TX_COUNT6_TX_Msk /*!< Transmission Byte Count 6 */
+
+/***************** Bit definition for USB_COUNT7_TX register ****************/
+#define USB_COUNT7_TX_COUNT7_TX_Pos (0U)
+#define USB_COUNT7_TX_COUNT7_TX_Msk (0x3FFU << USB_COUNT7_TX_COUNT7_TX_Pos) /*!< 0x000003FF */
+#define USB_COUNT7_TX_COUNT7_TX USB_COUNT7_TX_COUNT7_TX_Msk /*!< Transmission Byte Count 7 */
+
+/*----------------------------------------------------------------------------*/
+
+/**************** Bit definition for USB_COUNT0_TX_0 register ***************/
+#define USB_COUNT0_TX_0_COUNT0_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 0 (low) */
+
+/**************** Bit definition for USB_COUNT0_TX_1 register ***************/
+#define USB_COUNT0_TX_1_COUNT0_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 0 (high) */
+
+/**************** Bit definition for USB_COUNT1_TX_0 register ***************/
+#define USB_COUNT1_TX_0_COUNT1_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 1 (low) */
+
+/**************** Bit definition for USB_COUNT1_TX_1 register ***************/
+#define USB_COUNT1_TX_1_COUNT1_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 1 (high) */
+
+/**************** Bit definition for USB_COUNT2_TX_0 register ***************/
+#define USB_COUNT2_TX_0_COUNT2_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 2 (low) */
+
+/**************** Bit definition for USB_COUNT2_TX_1 register ***************/
+#define USB_COUNT2_TX_1_COUNT2_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 2 (high) */
+
+/**************** Bit definition for USB_COUNT3_TX_0 register ***************/
+#define USB_COUNT3_TX_0_COUNT3_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 3 (low) */
+
+/**************** Bit definition for USB_COUNT3_TX_1 register ***************/
+#define USB_COUNT3_TX_1_COUNT3_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 3 (high) */
+
+/**************** Bit definition for USB_COUNT4_TX_0 register ***************/
+#define USB_COUNT4_TX_0_COUNT4_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 4 (low) */
+
+/**************** Bit definition for USB_COUNT4_TX_1 register ***************/
+#define USB_COUNT4_TX_1_COUNT4_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 4 (high) */
+
+/**************** Bit definition for USB_COUNT5_TX_0 register ***************/
+#define USB_COUNT5_TX_0_COUNT5_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 5 (low) */
+
+/**************** Bit definition for USB_COUNT5_TX_1 register ***************/
+#define USB_COUNT5_TX_1_COUNT5_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 5 (high) */
+
+/**************** Bit definition for USB_COUNT6_TX_0 register ***************/
+#define USB_COUNT6_TX_0_COUNT6_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 6 (low) */
+
+/**************** Bit definition for USB_COUNT6_TX_1 register ***************/
+#define USB_COUNT6_TX_1_COUNT6_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 6 (high) */
+
+/**************** Bit definition for USB_COUNT7_TX_0 register ***************/
+#define USB_COUNT7_TX_0_COUNT7_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 7 (low) */
+
+/**************** Bit definition for USB_COUNT7_TX_1 register ***************/
+#define USB_COUNT7_TX_1_COUNT7_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 7 (high) */
+
+/*----------------------------------------------------------------------------*/
+
+/***************** Bit definition for USB_ADDR0_RX register *****************/
+#define USB_ADDR0_RX_ADDR0_RX_Pos (1U)
+#define USB_ADDR0_RX_ADDR0_RX_Msk (0x7FFFU << USB_ADDR0_RX_ADDR0_RX_Pos) /*!< 0x0000FFFE */
+#define USB_ADDR0_RX_ADDR0_RX USB_ADDR0_RX_ADDR0_RX_Msk /*!< Reception Buffer Address 0 */
+
+/***************** Bit definition for USB_ADDR1_RX register *****************/
+#define USB_ADDR1_RX_ADDR1_RX_Pos (1U)
+#define USB_ADDR1_RX_ADDR1_RX_Msk (0x7FFFU << USB_ADDR1_RX_ADDR1_RX_Pos) /*!< 0x0000FFFE */
+#define USB_ADDR1_RX_ADDR1_RX USB_ADDR1_RX_ADDR1_RX_Msk /*!< Reception Buffer Address 1 */
+
+/***************** Bit definition for USB_ADDR2_RX register *****************/
+#define USB_ADDR2_RX_ADDR2_RX_Pos (1U)
+#define USB_ADDR2_RX_ADDR2_RX_Msk (0x7FFFU << USB_ADDR2_RX_ADDR2_RX_Pos) /*!< 0x0000FFFE */
+#define USB_ADDR2_RX_ADDR2_RX USB_ADDR2_RX_ADDR2_RX_Msk /*!< Reception Buffer Address 2 */
+
+/***************** Bit definition for USB_ADDR3_RX register *****************/
+#define USB_ADDR3_RX_ADDR3_RX_Pos (1U)
+#define USB_ADDR3_RX_ADDR3_RX_Msk (0x7FFFU << USB_ADDR3_RX_ADDR3_RX_Pos) /*!< 0x0000FFFE */
+#define USB_ADDR3_RX_ADDR3_RX USB_ADDR3_RX_ADDR3_RX_Msk /*!< Reception Buffer Address 3 */
+
+/***************** Bit definition for USB_ADDR4_RX register *****************/
+#define USB_ADDR4_RX_ADDR4_RX_Pos (1U)
+#define USB_ADDR4_RX_ADDR4_RX_Msk (0x7FFFU << USB_ADDR4_RX_ADDR4_RX_Pos) /*!< 0x0000FFFE */
+#define USB_ADDR4_RX_ADDR4_RX USB_ADDR4_RX_ADDR4_RX_Msk /*!< Reception Buffer Address 4 */
+
+/***************** Bit definition for USB_ADDR5_RX register *****************/
+#define USB_ADDR5_RX_ADDR5_RX_Pos (1U)
+#define USB_ADDR5_RX_ADDR5_RX_Msk (0x7FFFU << USB_ADDR5_RX_ADDR5_RX_Pos) /*!< 0x0000FFFE */
+#define USB_ADDR5_RX_ADDR5_RX USB_ADDR5_RX_ADDR5_RX_Msk /*!< Reception Buffer Address 5 */
+
+/***************** Bit definition for USB_ADDR6_RX register *****************/
+#define USB_ADDR6_RX_ADDR6_RX_Pos (1U)
+#define USB_ADDR6_RX_ADDR6_RX_Msk (0x7FFFU << USB_ADDR6_RX_ADDR6_RX_Pos) /*!< 0x0000FFFE */
+#define USB_ADDR6_RX_ADDR6_RX USB_ADDR6_RX_ADDR6_RX_Msk /*!< Reception Buffer Address 6 */
+
+/***************** Bit definition for USB_ADDR7_RX register *****************/
+#define USB_ADDR7_RX_ADDR7_RX_Pos (1U)
+#define USB_ADDR7_RX_ADDR7_RX_Msk (0x7FFFU << USB_ADDR7_RX_ADDR7_RX_Pos) /*!< 0x0000FFFE */
+#define USB_ADDR7_RX_ADDR7_RX USB_ADDR7_RX_ADDR7_RX_Msk /*!< Reception Buffer Address 7 */
+
+/*----------------------------------------------------------------------------*/
+
+/***************** Bit definition for USB_COUNT0_RX register ****************/
+#define USB_COUNT0_RX_COUNT0_RX_Pos (0U)
+#define USB_COUNT0_RX_COUNT0_RX_Msk (0x3FFU << USB_COUNT0_RX_COUNT0_RX_Pos) /*!< 0x000003FF */
+#define USB_COUNT0_RX_COUNT0_RX USB_COUNT0_RX_COUNT0_RX_Msk /*!< Reception Byte Count */
+
+#define USB_COUNT0_RX_NUM_BLOCK_Pos (10U)
+#define USB_COUNT0_RX_NUM_BLOCK_Msk (0x1FU << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
+#define USB_COUNT0_RX_NUM_BLOCK USB_COUNT0_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
+#define USB_COUNT0_RX_NUM_BLOCK_0 (0x01U << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
+#define USB_COUNT0_RX_NUM_BLOCK_1 (0x02U << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
+#define USB_COUNT0_RX_NUM_BLOCK_2 (0x04U << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
+#define USB_COUNT0_RX_NUM_BLOCK_3 (0x08U << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
+#define USB_COUNT0_RX_NUM_BLOCK_4 (0x10U << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
+
+#define USB_COUNT0_RX_BLSIZE_Pos (15U)
+#define USB_COUNT0_RX_BLSIZE_Msk (0x1U << USB_COUNT0_RX_BLSIZE_Pos) /*!< 0x00008000 */
+#define USB_COUNT0_RX_BLSIZE USB_COUNT0_RX_BLSIZE_Msk /*!< BLock SIZE */
+
+/***************** Bit definition for USB_COUNT1_RX register ****************/
+#define USB_COUNT1_RX_COUNT1_RX_Pos (0U)
+#define USB_COUNT1_RX_COUNT1_RX_Msk (0x3FFU << USB_COUNT1_RX_COUNT1_RX_Pos) /*!< 0x000003FF */
+#define USB_COUNT1_RX_COUNT1_RX USB_COUNT1_RX_COUNT1_RX_Msk /*!< Reception Byte Count */
+
+#define USB_COUNT1_RX_NUM_BLOCK_Pos (10U)
+#define USB_COUNT1_RX_NUM_BLOCK_Msk (0x1FU << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
+#define USB_COUNT1_RX_NUM_BLOCK USB_COUNT1_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
+#define USB_COUNT1_RX_NUM_BLOCK_0 (0x01U << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
+#define USB_COUNT1_RX_NUM_BLOCK_1 (0x02U << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
+#define USB_COUNT1_RX_NUM_BLOCK_2 (0x04U << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
+#define USB_COUNT1_RX_NUM_BLOCK_3 (0x08U << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
+#define USB_COUNT1_RX_NUM_BLOCK_4 (0x10U << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
+
+#define USB_COUNT1_RX_BLSIZE_Pos (15U)
+#define USB_COUNT1_RX_BLSIZE_Msk (0x1U << USB_COUNT1_RX_BLSIZE_Pos) /*!< 0x00008000 */
+#define USB_COUNT1_RX_BLSIZE USB_COUNT1_RX_BLSIZE_Msk /*!< BLock SIZE */
+
+/***************** Bit definition for USB_COUNT2_RX register ****************/
+#define USB_COUNT2_RX_COUNT2_RX_Pos (0U)
+#define USB_COUNT2_RX_COUNT2_RX_Msk (0x3FFU << USB_COUNT2_RX_COUNT2_RX_Pos) /*!< 0x000003FF */
+#define USB_COUNT2_RX_COUNT2_RX USB_COUNT2_RX_COUNT2_RX_Msk /*!< Reception Byte Count */
+
+#define USB_COUNT2_RX_NUM_BLOCK_Pos (10U)
+#define USB_COUNT2_RX_NUM_BLOCK_Msk (0x1FU << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
+#define USB_COUNT2_RX_NUM_BLOCK USB_COUNT2_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
+#define USB_COUNT2_RX_NUM_BLOCK_0 (0x01U << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
+#define USB_COUNT2_RX_NUM_BLOCK_1 (0x02U << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
+#define USB_COUNT2_RX_NUM_BLOCK_2 (0x04U << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
+#define USB_COUNT2_RX_NUM_BLOCK_3 (0x08U << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
+#define USB_COUNT2_RX_NUM_BLOCK_4 (0x10U << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
+
+#define USB_COUNT2_RX_BLSIZE_Pos (15U)
+#define USB_COUNT2_RX_BLSIZE_Msk (0x1U << USB_COUNT2_RX_BLSIZE_Pos) /*!< 0x00008000 */
+#define USB_COUNT2_RX_BLSIZE USB_COUNT2_RX_BLSIZE_Msk /*!< BLock SIZE */
+
+/***************** Bit definition for USB_COUNT3_RX register ****************/
+#define USB_COUNT3_RX_COUNT3_RX_Pos (0U)
+#define USB_COUNT3_RX_COUNT3_RX_Msk (0x3FFU << USB_COUNT3_RX_COUNT3_RX_Pos) /*!< 0x000003FF */
+#define USB_COUNT3_RX_COUNT3_RX USB_COUNT3_RX_COUNT3_RX_Msk /*!< Reception Byte Count */
+
+#define USB_COUNT3_RX_NUM_BLOCK_Pos (10U)
+#define USB_COUNT3_RX_NUM_BLOCK_Msk (0x1FU << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
+#define USB_COUNT3_RX_NUM_BLOCK USB_COUNT3_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
+#define USB_COUNT3_RX_NUM_BLOCK_0 (0x01U << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
+#define USB_COUNT3_RX_NUM_BLOCK_1 (0x02U << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
+#define USB_COUNT3_RX_NUM_BLOCK_2 (0x04U << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
+#define USB_COUNT3_RX_NUM_BLOCK_3 (0x08U << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
+#define USB_COUNT3_RX_NUM_BLOCK_4 (0x10U << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
+
+#define USB_COUNT3_RX_BLSIZE_Pos (15U)
+#define USB_COUNT3_RX_BLSIZE_Msk (0x1U << USB_COUNT3_RX_BLSIZE_Pos) /*!< 0x00008000 */
+#define USB_COUNT3_RX_BLSIZE USB_COUNT3_RX_BLSIZE_Msk /*!< BLock SIZE */
+
+/***************** Bit definition for USB_COUNT4_RX register ****************/
+#define USB_COUNT4_RX_COUNT4_RX_Pos (0U)
+#define USB_COUNT4_RX_COUNT4_RX_Msk (0x3FFU << USB_COUNT4_RX_COUNT4_RX_Pos) /*!< 0x000003FF */
+#define USB_COUNT4_RX_COUNT4_RX USB_COUNT4_RX_COUNT4_RX_Msk /*!< Reception Byte Count */
+
+#define USB_COUNT4_RX_NUM_BLOCK_Pos (10U)
+#define USB_COUNT4_RX_NUM_BLOCK_Msk (0x1FU << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
+#define USB_COUNT4_RX_NUM_BLOCK USB_COUNT4_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
+#define USB_COUNT4_RX_NUM_BLOCK_0 (0x01U << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
+#define USB_COUNT4_RX_NUM_BLOCK_1 (0x02U << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
+#define USB_COUNT4_RX_NUM_BLOCK_2 (0x04U << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
+#define USB_COUNT4_RX_NUM_BLOCK_3 (0x08U << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
+#define USB_COUNT4_RX_NUM_BLOCK_4 (0x10U << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
+
+#define USB_COUNT4_RX_BLSIZE_Pos (15U)
+#define USB_COUNT4_RX_BLSIZE_Msk (0x1U << USB_COUNT4_RX_BLSIZE_Pos) /*!< 0x00008000 */
+#define USB_COUNT4_RX_BLSIZE USB_COUNT4_RX_BLSIZE_Msk /*!< BLock SIZE */
+
+/***************** Bit definition for USB_COUNT5_RX register ****************/
+#define USB_COUNT5_RX_COUNT5_RX_Pos (0U)
+#define USB_COUNT5_RX_COUNT5_RX_Msk (0x3FFU << USB_COUNT5_RX_COUNT5_RX_Pos) /*!< 0x000003FF */
+#define USB_COUNT5_RX_COUNT5_RX USB_COUNT5_RX_COUNT5_RX_Msk /*!< Reception Byte Count */
+
+#define USB_COUNT5_RX_NUM_BLOCK_Pos (10U)
+#define USB_COUNT5_RX_NUM_BLOCK_Msk (0x1FU << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
+#define USB_COUNT5_RX_NUM_BLOCK USB_COUNT5_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
+#define USB_COUNT5_RX_NUM_BLOCK_0 (0x01U << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
+#define USB_COUNT5_RX_NUM_BLOCK_1 (0x02U << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
+#define USB_COUNT5_RX_NUM_BLOCK_2 (0x04U << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
+#define USB_COUNT5_RX_NUM_BLOCK_3 (0x08U << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
+#define USB_COUNT5_RX_NUM_BLOCK_4 (0x10U << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
+
+#define USB_COUNT5_RX_BLSIZE_Pos (15U)
+#define USB_COUNT5_RX_BLSIZE_Msk (0x1U << USB_COUNT5_RX_BLSIZE_Pos) /*!< 0x00008000 */
+#define USB_COUNT5_RX_BLSIZE USB_COUNT5_RX_BLSIZE_Msk /*!< BLock SIZE */
+
+/***************** Bit definition for USB_COUNT6_RX register ****************/
+#define USB_COUNT6_RX_COUNT6_RX_Pos (0U)
+#define USB_COUNT6_RX_COUNT6_RX_Msk (0x3FFU << USB_COUNT6_RX_COUNT6_RX_Pos) /*!< 0x000003FF */
+#define USB_COUNT6_RX_COUNT6_RX USB_COUNT6_RX_COUNT6_RX_Msk /*!< Reception Byte Count */
+
+#define USB_COUNT6_RX_NUM_BLOCK_Pos (10U)
+#define USB_COUNT6_RX_NUM_BLOCK_Msk (0x1FU << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
+#define USB_COUNT6_RX_NUM_BLOCK USB_COUNT6_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
+#define USB_COUNT6_RX_NUM_BLOCK_0 (0x01U << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
+#define USB_COUNT6_RX_NUM_BLOCK_1 (0x02U << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
+#define USB_COUNT6_RX_NUM_BLOCK_2 (0x04U << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
+#define USB_COUNT6_RX_NUM_BLOCK_3 (0x08U << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
+#define USB_COUNT6_RX_NUM_BLOCK_4 (0x10U << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
+
+#define USB_COUNT6_RX_BLSIZE_Pos (15U)
+#define USB_COUNT6_RX_BLSIZE_Msk (0x1U << USB_COUNT6_RX_BLSIZE_Pos) /*!< 0x00008000 */
+#define USB_COUNT6_RX_BLSIZE USB_COUNT6_RX_BLSIZE_Msk /*!< BLock SIZE */
+
+/***************** Bit definition for USB_COUNT7_RX register ****************/
+#define USB_COUNT7_RX_COUNT7_RX_Pos (0U)
+#define USB_COUNT7_RX_COUNT7_RX_Msk (0x3FFU << USB_COUNT7_RX_COUNT7_RX_Pos) /*!< 0x000003FF */
+#define USB_COUNT7_RX_COUNT7_RX USB_COUNT7_RX_COUNT7_RX_Msk /*!< Reception Byte Count */
+
+#define USB_COUNT7_RX_NUM_BLOCK_Pos (10U)
+#define USB_COUNT7_RX_NUM_BLOCK_Msk (0x1FU << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
+#define USB_COUNT7_RX_NUM_BLOCK USB_COUNT7_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
+#define USB_COUNT7_RX_NUM_BLOCK_0 (0x01U << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
+#define USB_COUNT7_RX_NUM_BLOCK_1 (0x02U << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
+#define USB_COUNT7_RX_NUM_BLOCK_2 (0x04U << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
+#define USB_COUNT7_RX_NUM_BLOCK_3 (0x08U << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
+#define USB_COUNT7_RX_NUM_BLOCK_4 (0x10U << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
+
+#define USB_COUNT7_RX_BLSIZE_Pos (15U)
+#define USB_COUNT7_RX_BLSIZE_Msk (0x1U << USB_COUNT7_RX_BLSIZE_Pos) /*!< 0x00008000 */
+#define USB_COUNT7_RX_BLSIZE USB_COUNT7_RX_BLSIZE_Msk /*!< BLock SIZE */
+
+/*----------------------------------------------------------------------------*/
+
+/**************** Bit definition for USB_COUNT0_RX_0 register ***************/
+#define USB_COUNT0_RX_0_COUNT0_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */
+
+#define USB_COUNT0_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
+#define USB_COUNT0_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */
+#define USB_COUNT0_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */
+#define USB_COUNT0_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */
+#define USB_COUNT0_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */
+#define USB_COUNT0_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */
+
+#define USB_COUNT0_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */
+
+/**************** Bit definition for USB_COUNT0_RX_1 register ***************/
+#define USB_COUNT0_RX_1_COUNT0_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */
+
+#define USB_COUNT0_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
+#define USB_COUNT0_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 1 */
+#define USB_COUNT0_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */
+#define USB_COUNT0_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */
+#define USB_COUNT0_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */
+#define USB_COUNT0_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */
+
+#define USB_COUNT0_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */
+
+/**************** Bit definition for USB_COUNT1_RX_0 register ***************/
+#define USB_COUNT1_RX_0_COUNT1_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */
+
+#define USB_COUNT1_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
+#define USB_COUNT1_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */
+#define USB_COUNT1_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */
+#define USB_COUNT1_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */
+#define USB_COUNT1_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */
+#define USB_COUNT1_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */
+
+#define USB_COUNT1_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */
+
+/**************** Bit definition for USB_COUNT1_RX_1 register ***************/
+#define USB_COUNT1_RX_1_COUNT1_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */
+
+#define USB_COUNT1_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
+#define USB_COUNT1_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */
+#define USB_COUNT1_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */
+#define USB_COUNT1_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */
+#define USB_COUNT1_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */
+#define USB_COUNT1_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */
+
+#define USB_COUNT1_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */
+
+/**************** Bit definition for USB_COUNT2_RX_0 register ***************/
+#define USB_COUNT2_RX_0_COUNT2_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */
+
+#define USB_COUNT2_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
+#define USB_COUNT2_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */
+#define USB_COUNT2_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */
+#define USB_COUNT2_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */
+#define USB_COUNT2_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */
+#define USB_COUNT2_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */
+
+#define USB_COUNT2_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */
+
+/**************** Bit definition for USB_COUNT2_RX_1 register ***************/
+#define USB_COUNT2_RX_1_COUNT2_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */
+
+#define USB_COUNT2_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
+#define USB_COUNT2_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */
+#define USB_COUNT2_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */
+#define USB_COUNT2_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */
+#define USB_COUNT2_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */
+#define USB_COUNT2_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */
+
+#define USB_COUNT2_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */
+
+/**************** Bit definition for USB_COUNT3_RX_0 register ***************/
+#define USB_COUNT3_RX_0_COUNT3_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */
+
+#define USB_COUNT3_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
+#define USB_COUNT3_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */
+#define USB_COUNT3_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */
+#define USB_COUNT3_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */
+#define USB_COUNT3_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */
+#define USB_COUNT3_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */
+
+#define USB_COUNT3_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */
+
+/**************** Bit definition for USB_COUNT3_RX_1 register ***************/
+#define USB_COUNT3_RX_1_COUNT3_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */
+
+#define USB_COUNT3_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
+#define USB_COUNT3_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */
+#define USB_COUNT3_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */
+#define USB_COUNT3_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */
+#define USB_COUNT3_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */
+#define USB_COUNT3_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */
+
+#define USB_COUNT3_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */
+
+/**************** Bit definition for USB_COUNT4_RX_0 register ***************/
+#define USB_COUNT4_RX_0_COUNT4_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */
+
+#define USB_COUNT4_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
+#define USB_COUNT4_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */
+#define USB_COUNT4_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */
+#define USB_COUNT4_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */
+#define USB_COUNT4_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */
+#define USB_COUNT4_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */
+
+#define USB_COUNT4_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */
+
+/**************** Bit definition for USB_COUNT4_RX_1 register ***************/
+#define USB_COUNT4_RX_1_COUNT4_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */
+
+#define USB_COUNT4_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
+#define USB_COUNT4_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */
+#define USB_COUNT4_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */
+#define USB_COUNT4_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */
+#define USB_COUNT4_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */
+#define USB_COUNT4_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */
+
+#define USB_COUNT4_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */
+
+/**************** Bit definition for USB_COUNT5_RX_0 register ***************/
+#define USB_COUNT5_RX_0_COUNT5_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */
+
+#define USB_COUNT5_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
+#define USB_COUNT5_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */
+#define USB_COUNT5_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */
+#define USB_COUNT5_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */
+#define USB_COUNT5_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */
+#define USB_COUNT5_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */
+
+#define USB_COUNT5_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */
+
+/**************** Bit definition for USB_COUNT5_RX_1 register ***************/
+#define USB_COUNT5_RX_1_COUNT5_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */
+
+#define USB_COUNT5_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
+#define USB_COUNT5_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */
+#define USB_COUNT5_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */
+#define USB_COUNT5_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */
+#define USB_COUNT5_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */
+#define USB_COUNT5_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */
+
+#define USB_COUNT5_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */
+
+/*************** Bit definition for USB_COUNT6_RX_0 register ***************/
+#define USB_COUNT6_RX_0_COUNT6_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */
+
+#define USB_COUNT6_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
+#define USB_COUNT6_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */
+#define USB_COUNT6_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */
+#define USB_COUNT6_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */
+#define USB_COUNT6_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */
+#define USB_COUNT6_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */
+
+#define USB_COUNT6_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */
+
+/**************** Bit definition for USB_COUNT6_RX_1 register ***************/
+#define USB_COUNT6_RX_1_COUNT6_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */
+
+#define USB_COUNT6_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
+#define USB_COUNT6_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */
+#define USB_COUNT6_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */
+#define USB_COUNT6_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */
+#define USB_COUNT6_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */
+#define USB_COUNT6_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */
+
+#define USB_COUNT6_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */
+
+/*************** Bit definition for USB_COUNT7_RX_0 register ****************/
+#define USB_COUNT7_RX_0_COUNT7_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */
+
+#define USB_COUNT7_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
+#define USB_COUNT7_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */
+#define USB_COUNT7_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */
+#define USB_COUNT7_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */
+#define USB_COUNT7_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */
+#define USB_COUNT7_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */
+
+#define USB_COUNT7_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */
+
+/*************** Bit definition for USB_COUNT7_RX_1 register ****************/
+#define USB_COUNT7_RX_1_COUNT7_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */
+
+#define USB_COUNT7_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
+#define USB_COUNT7_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */
+#define USB_COUNT7_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */
+#define USB_COUNT7_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */
+#define USB_COUNT7_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */
+#define USB_COUNT7_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */
+
+#define USB_COUNT7_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */
+
+/******************************************************************************/
+/* */
+/* Controller Area Network */
+/* */
+/******************************************************************************/
+
+/*!< CAN control and status registers */
+/******************* Bit definition for CAN_MCR register ********************/
+#define CAN_MCR_INRQ_Pos (0U)
+#define CAN_MCR_INRQ_Msk (0x1U << CAN_MCR_INRQ_Pos) /*!< 0x00000001 */
+#define CAN_MCR_INRQ CAN_MCR_INRQ_Msk /*!< Initialization Request */
+#define CAN_MCR_SLEEP_Pos (1U)
+#define CAN_MCR_SLEEP_Msk (0x1U << CAN_MCR_SLEEP_Pos) /*!< 0x00000002 */
+#define CAN_MCR_SLEEP CAN_MCR_SLEEP_Msk /*!< Sleep Mode Request */
+#define CAN_MCR_TXFP_Pos (2U)
+#define CAN_MCR_TXFP_Msk (0x1U << CAN_MCR_TXFP_Pos) /*!< 0x00000004 */
+#define CAN_MCR_TXFP CAN_MCR_TXFP_Msk /*!< Transmit FIFO Priority */
+#define CAN_MCR_RFLM_Pos (3U)
+#define CAN_MCR_RFLM_Msk (0x1U << CAN_MCR_RFLM_Pos) /*!< 0x00000008 */
+#define CAN_MCR_RFLM CAN_MCR_RFLM_Msk /*!< Receive FIFO Locked Mode */
+#define CAN_MCR_NART_Pos (4U)
+#define CAN_MCR_NART_Msk (0x1U << CAN_MCR_NART_Pos) /*!< 0x00000010 */
+#define CAN_MCR_NART CAN_MCR_NART_Msk /*!< No Automatic Retransmission */
+#define CAN_MCR_AWUM_Pos (5U)
+#define CAN_MCR_AWUM_Msk (0x1U << CAN_MCR_AWUM_Pos) /*!< 0x00000020 */
+#define CAN_MCR_AWUM CAN_MCR_AWUM_Msk /*!< Automatic Wakeup Mode */
+#define CAN_MCR_ABOM_Pos (6U)
+#define CAN_MCR_ABOM_Msk (0x1U << CAN_MCR_ABOM_Pos) /*!< 0x00000040 */
+#define CAN_MCR_ABOM CAN_MCR_ABOM_Msk /*!< Automatic Bus-Off Management */
+#define CAN_MCR_TTCM_Pos (7U)
+#define CAN_MCR_TTCM_Msk (0x1U << CAN_MCR_TTCM_Pos) /*!< 0x00000080 */
+#define CAN_MCR_TTCM CAN_MCR_TTCM_Msk /*!< Time Triggered Communication Mode */
+#define CAN_MCR_RESET_Pos (15U)
+#define CAN_MCR_RESET_Msk (0x1U << CAN_MCR_RESET_Pos) /*!< 0x00008000 */
+#define CAN_MCR_RESET CAN_MCR_RESET_Msk /*!< CAN software master reset */
+#define CAN_MCR_DBF_Pos (16U)
+#define CAN_MCR_DBF_Msk (0x1U << CAN_MCR_DBF_Pos) /*!< 0x00010000 */
+#define CAN_MCR_DBF CAN_MCR_DBF_Msk /*!< CAN Debug freeze */
+
+/******************* Bit definition for CAN_MSR register ********************/
+#define CAN_MSR_INAK_Pos (0U)
+#define CAN_MSR_INAK_Msk (0x1U << CAN_MSR_INAK_Pos) /*!< 0x00000001 */
+#define CAN_MSR_INAK CAN_MSR_INAK_Msk /*!< Initialization Acknowledge */
+#define CAN_MSR_SLAK_Pos (1U)
+#define CAN_MSR_SLAK_Msk (0x1U << CAN_MSR_SLAK_Pos) /*!< 0x00000002 */
+#define CAN_MSR_SLAK CAN_MSR_SLAK_Msk /*!< Sleep Acknowledge */
+#define CAN_MSR_ERRI_Pos (2U)
+#define CAN_MSR_ERRI_Msk (0x1U << CAN_MSR_ERRI_Pos) /*!< 0x00000004 */
+#define CAN_MSR_ERRI CAN_MSR_ERRI_Msk /*!< Error Interrupt */
+#define CAN_MSR_WKUI_Pos (3U)
+#define CAN_MSR_WKUI_Msk (0x1U << CAN_MSR_WKUI_Pos) /*!< 0x00000008 */
+#define CAN_MSR_WKUI CAN_MSR_WKUI_Msk /*!< Wakeup Interrupt */
+#define CAN_MSR_SLAKI_Pos (4U)
+#define CAN_MSR_SLAKI_Msk (0x1U << CAN_MSR_SLAKI_Pos) /*!< 0x00000010 */
+#define CAN_MSR_SLAKI CAN_MSR_SLAKI_Msk /*!< Sleep Acknowledge Interrupt */
+#define CAN_MSR_TXM_Pos (8U)
+#define CAN_MSR_TXM_Msk (0x1U << CAN_MSR_TXM_Pos) /*!< 0x00000100 */
+#define CAN_MSR_TXM CAN_MSR_TXM_Msk /*!< Transmit Mode */
+#define CAN_MSR_RXM_Pos (9U)
+#define CAN_MSR_RXM_Msk (0x1U << CAN_MSR_RXM_Pos) /*!< 0x00000200 */
+#define CAN_MSR_RXM CAN_MSR_RXM_Msk /*!< Receive Mode */
+#define CAN_MSR_SAMP_Pos (10U)
+#define CAN_MSR_SAMP_Msk (0x1U << CAN_MSR_SAMP_Pos) /*!< 0x00000400 */
+#define CAN_MSR_SAMP CAN_MSR_SAMP_Msk /*!< Last Sample Point */
+#define CAN_MSR_RX_Pos (11U)
+#define CAN_MSR_RX_Msk (0x1U << CAN_MSR_RX_Pos) /*!< 0x00000800 */
+#define CAN_MSR_RX CAN_MSR_RX_Msk /*!< CAN Rx Signal */
+
+/******************* Bit definition for CAN_TSR register ********************/
+#define CAN_TSR_RQCP0_Pos (0U)
+#define CAN_TSR_RQCP0_Msk (0x1U << CAN_TSR_RQCP0_Pos) /*!< 0x00000001 */
+#define CAN_TSR_RQCP0 CAN_TSR_RQCP0_Msk /*!< Request Completed Mailbox0 */
+#define CAN_TSR_TXOK0_Pos (1U)
+#define CAN_TSR_TXOK0_Msk (0x1U << CAN_TSR_TXOK0_Pos) /*!< 0x00000002 */
+#define CAN_TSR_TXOK0 CAN_TSR_TXOK0_Msk /*!< Transmission OK of Mailbox0 */
+#define CAN_TSR_ALST0_Pos (2U)
+#define CAN_TSR_ALST0_Msk (0x1U << CAN_TSR_ALST0_Pos) /*!< 0x00000004 */
+#define CAN_TSR_ALST0 CAN_TSR_ALST0_Msk /*!< Arbitration Lost for Mailbox0 */
+#define CAN_TSR_TERR0_Pos (3U)
+#define CAN_TSR_TERR0_Msk (0x1U << CAN_TSR_TERR0_Pos) /*!< 0x00000008 */
+#define CAN_TSR_TERR0 CAN_TSR_TERR0_Msk /*!< Transmission Error of Mailbox0 */
+#define CAN_TSR_ABRQ0_Pos (7U)
+#define CAN_TSR_ABRQ0_Msk (0x1U << CAN_TSR_ABRQ0_Pos) /*!< 0x00000080 */
+#define CAN_TSR_ABRQ0 CAN_TSR_ABRQ0_Msk /*!< Abort Request for Mailbox0 */
+#define CAN_TSR_RQCP1_Pos (8U)
+#define CAN_TSR_RQCP1_Msk (0x1U << CAN_TSR_RQCP1_Pos) /*!< 0x00000100 */
+#define CAN_TSR_RQCP1 CAN_TSR_RQCP1_Msk /*!< Request Completed Mailbox1 */
+#define CAN_TSR_TXOK1_Pos (9U)
+#define CAN_TSR_TXOK1_Msk (0x1U << CAN_TSR_TXOK1_Pos) /*!< 0x00000200 */
+#define CAN_TSR_TXOK1 CAN_TSR_TXOK1_Msk /*!< Transmission OK of Mailbox1 */
+#define CAN_TSR_ALST1_Pos (10U)
+#define CAN_TSR_ALST1_Msk (0x1U << CAN_TSR_ALST1_Pos) /*!< 0x00000400 */
+#define CAN_TSR_ALST1 CAN_TSR_ALST1_Msk /*!< Arbitration Lost for Mailbox1 */
+#define CAN_TSR_TERR1_Pos (11U)
+#define CAN_TSR_TERR1_Msk (0x1U << CAN_TSR_TERR1_Pos) /*!< 0x00000800 */
+#define CAN_TSR_TERR1 CAN_TSR_TERR1_Msk /*!< Transmission Error of Mailbox1 */
+#define CAN_TSR_ABRQ1_Pos (15U)
+#define CAN_TSR_ABRQ1_Msk (0x1U << CAN_TSR_ABRQ1_Pos) /*!< 0x00008000 */
+#define CAN_TSR_ABRQ1 CAN_TSR_ABRQ1_Msk /*!< Abort Request for Mailbox 1 */
+#define CAN_TSR_RQCP2_Pos (16U)
+#define CAN_TSR_RQCP2_Msk (0x1U << CAN_TSR_RQCP2_Pos) /*!< 0x00010000 */
+#define CAN_TSR_RQCP2 CAN_TSR_RQCP2_Msk /*!< Request Completed Mailbox2 */
+#define CAN_TSR_TXOK2_Pos (17U)
+#define CAN_TSR_TXOK2_Msk (0x1U << CAN_TSR_TXOK2_Pos) /*!< 0x00020000 */
+#define CAN_TSR_TXOK2 CAN_TSR_TXOK2_Msk /*!< Transmission OK of Mailbox 2 */
+#define CAN_TSR_ALST2_Pos (18U)
+#define CAN_TSR_ALST2_Msk (0x1U << CAN_TSR_ALST2_Pos) /*!< 0x00040000 */
+#define CAN_TSR_ALST2 CAN_TSR_ALST2_Msk /*!< Arbitration Lost for mailbox 2 */
+#define CAN_TSR_TERR2_Pos (19U)
+#define CAN_TSR_TERR2_Msk (0x1U << CAN_TSR_TERR2_Pos) /*!< 0x00080000 */
+#define CAN_TSR_TERR2 CAN_TSR_TERR2_Msk /*!< Transmission Error of Mailbox 2 */
+#define CAN_TSR_ABRQ2_Pos (23U)
+#define CAN_TSR_ABRQ2_Msk (0x1U << CAN_TSR_ABRQ2_Pos) /*!< 0x00800000 */
+#define CAN_TSR_ABRQ2 CAN_TSR_ABRQ2_Msk /*!< Abort Request for Mailbox 2 */
+#define CAN_TSR_CODE_Pos (24U)
+#define CAN_TSR_CODE_Msk (0x3U << CAN_TSR_CODE_Pos) /*!< 0x03000000 */
+#define CAN_TSR_CODE CAN_TSR_CODE_Msk /*!< Mailbox Code */
+
+#define CAN_TSR_TME_Pos (26U)
+#define CAN_TSR_TME_Msk (0x7U << CAN_TSR_TME_Pos) /*!< 0x1C000000 */
+#define CAN_TSR_TME CAN_TSR_TME_Msk /*!< TME[2:0] bits */
+#define CAN_TSR_TME0_Pos (26U)
+#define CAN_TSR_TME0_Msk (0x1U << CAN_TSR_TME0_Pos) /*!< 0x04000000 */
+#define CAN_TSR_TME0 CAN_TSR_TME0_Msk /*!< Transmit Mailbox 0 Empty */
+#define CAN_TSR_TME1_Pos (27U)
+#define CAN_TSR_TME1_Msk (0x1U << CAN_TSR_TME1_Pos) /*!< 0x08000000 */
+#define CAN_TSR_TME1 CAN_TSR_TME1_Msk /*!< Transmit Mailbox 1 Empty */
+#define CAN_TSR_TME2_Pos (28U)
+#define CAN_TSR_TME2_Msk (0x1U << CAN_TSR_TME2_Pos) /*!< 0x10000000 */
+#define CAN_TSR_TME2 CAN_TSR_TME2_Msk /*!< Transmit Mailbox 2 Empty */
+
+#define CAN_TSR_LOW_Pos (29U)
+#define CAN_TSR_LOW_Msk (0x7U << CAN_TSR_LOW_Pos) /*!< 0xE0000000 */
+#define CAN_TSR_LOW CAN_TSR_LOW_Msk /*!< LOW[2:0] bits */
+#define CAN_TSR_LOW0_Pos (29U)
+#define CAN_TSR_LOW0_Msk (0x1U << CAN_TSR_LOW0_Pos) /*!< 0x20000000 */
+#define CAN_TSR_LOW0 CAN_TSR_LOW0_Msk /*!< Lowest Priority Flag for Mailbox 0 */
+#define CAN_TSR_LOW1_Pos (30U)
+#define CAN_TSR_LOW1_Msk (0x1U << CAN_TSR_LOW1_Pos) /*!< 0x40000000 */
+#define CAN_TSR_LOW1 CAN_TSR_LOW1_Msk /*!< Lowest Priority Flag for Mailbox 1 */
+#define CAN_TSR_LOW2_Pos (31U)
+#define CAN_TSR_LOW2_Msk (0x1U << CAN_TSR_LOW2_Pos) /*!< 0x80000000 */
+#define CAN_TSR_LOW2 CAN_TSR_LOW2_Msk /*!< Lowest Priority Flag for Mailbox 2 */
+
+/******************* Bit definition for CAN_RF0R register *******************/
+#define CAN_RF0R_FMP0_Pos (0U)
+#define CAN_RF0R_FMP0_Msk (0x3U << CAN_RF0R_FMP0_Pos) /*!< 0x00000003 */
+#define CAN_RF0R_FMP0 CAN_RF0R_FMP0_Msk /*!< FIFO 0 Message Pending */
+#define CAN_RF0R_FULL0_Pos (3U)
+#define CAN_RF0R_FULL0_Msk (0x1U << CAN_RF0R_FULL0_Pos) /*!< 0x00000008 */
+#define CAN_RF0R_FULL0 CAN_RF0R_FULL0_Msk /*!< FIFO 0 Full */
+#define CAN_RF0R_FOVR0_Pos (4U)
+#define CAN_RF0R_FOVR0_Msk (0x1U << CAN_RF0R_FOVR0_Pos) /*!< 0x00000010 */
+#define CAN_RF0R_FOVR0 CAN_RF0R_FOVR0_Msk /*!< FIFO 0 Overrun */
+#define CAN_RF0R_RFOM0_Pos (5U)
+#define CAN_RF0R_RFOM0_Msk (0x1U << CAN_RF0R_RFOM0_Pos) /*!< 0x00000020 */
+#define CAN_RF0R_RFOM0 CAN_RF0R_RFOM0_Msk /*!< Release FIFO 0 Output Mailbox */
+
+/******************* Bit definition for CAN_RF1R register *******************/
+#define CAN_RF1R_FMP1_Pos (0U)
+#define CAN_RF1R_FMP1_Msk (0x3U << CAN_RF1R_FMP1_Pos) /*!< 0x00000003 */
+#define CAN_RF1R_FMP1 CAN_RF1R_FMP1_Msk /*!< FIFO 1 Message Pending */
+#define CAN_RF1R_FULL1_Pos (3U)
+#define CAN_RF1R_FULL1_Msk (0x1U << CAN_RF1R_FULL1_Pos) /*!< 0x00000008 */
+#define CAN_RF1R_FULL1 CAN_RF1R_FULL1_Msk /*!< FIFO 1 Full */
+#define CAN_RF1R_FOVR1_Pos (4U)
+#define CAN_RF1R_FOVR1_Msk (0x1U << CAN_RF1R_FOVR1_Pos) /*!< 0x00000010 */
+#define CAN_RF1R_FOVR1 CAN_RF1R_FOVR1_Msk /*!< FIFO 1 Overrun */
+#define CAN_RF1R_RFOM1_Pos (5U)
+#define CAN_RF1R_RFOM1_Msk (0x1U << CAN_RF1R_RFOM1_Pos) /*!< 0x00000020 */
+#define CAN_RF1R_RFOM1 CAN_RF1R_RFOM1_Msk /*!< Release FIFO 1 Output Mailbox */
+
+/******************** Bit definition for CAN_IER register *******************/
+#define CAN_IER_TMEIE_Pos (0U)
+#define CAN_IER_TMEIE_Msk (0x1U << CAN_IER_TMEIE_Pos) /*!< 0x00000001 */
+#define CAN_IER_TMEIE CAN_IER_TMEIE_Msk /*!< Transmit Mailbox Empty Interrupt Enable */
+#define CAN_IER_FMPIE0_Pos (1U)
+#define CAN_IER_FMPIE0_Msk (0x1U << CAN_IER_FMPIE0_Pos) /*!< 0x00000002 */
+#define CAN_IER_FMPIE0 CAN_IER_FMPIE0_Msk /*!< FIFO Message Pending Interrupt Enable */
+#define CAN_IER_FFIE0_Pos (2U)
+#define CAN_IER_FFIE0_Msk (0x1U << CAN_IER_FFIE0_Pos) /*!< 0x00000004 */
+#define CAN_IER_FFIE0 CAN_IER_FFIE0_Msk /*!< FIFO Full Interrupt Enable */
+#define CAN_IER_FOVIE0_Pos (3U)
+#define CAN_IER_FOVIE0_Msk (0x1U << CAN_IER_FOVIE0_Pos) /*!< 0x00000008 */
+#define CAN_IER_FOVIE0 CAN_IER_FOVIE0_Msk /*!< FIFO Overrun Interrupt Enable */
+#define CAN_IER_FMPIE1_Pos (4U)
+#define CAN_IER_FMPIE1_Msk (0x1U << CAN_IER_FMPIE1_Pos) /*!< 0x00000010 */
+#define CAN_IER_FMPIE1 CAN_IER_FMPIE1_Msk /*!< FIFO Message Pending Interrupt Enable */
+#define CAN_IER_FFIE1_Pos (5U)
+#define CAN_IER_FFIE1_Msk (0x1U << CAN_IER_FFIE1_Pos) /*!< 0x00000020 */
+#define CAN_IER_FFIE1 CAN_IER_FFIE1_Msk /*!< FIFO Full Interrupt Enable */
+#define CAN_IER_FOVIE1_Pos (6U)
+#define CAN_IER_FOVIE1_Msk (0x1U << CAN_IER_FOVIE1_Pos) /*!< 0x00000040 */
+#define CAN_IER_FOVIE1 CAN_IER_FOVIE1_Msk /*!< FIFO Overrun Interrupt Enable */
+#define CAN_IER_EWGIE_Pos (8U)
+#define CAN_IER_EWGIE_Msk (0x1U << CAN_IER_EWGIE_Pos) /*!< 0x00000100 */
+#define CAN_IER_EWGIE CAN_IER_EWGIE_Msk /*!< Error Warning Interrupt Enable */
+#define CAN_IER_EPVIE_Pos (9U)
+#define CAN_IER_EPVIE_Msk (0x1U << CAN_IER_EPVIE_Pos) /*!< 0x00000200 */
+#define CAN_IER_EPVIE CAN_IER_EPVIE_Msk /*!< Error Passive Interrupt Enable */
+#define CAN_IER_BOFIE_Pos (10U)
+#define CAN_IER_BOFIE_Msk (0x1U << CAN_IER_BOFIE_Pos) /*!< 0x00000400 */
+#define CAN_IER_BOFIE CAN_IER_BOFIE_Msk /*!< Bus-Off Interrupt Enable */
+#define CAN_IER_LECIE_Pos (11U)
+#define CAN_IER_LECIE_Msk (0x1U << CAN_IER_LECIE_Pos) /*!< 0x00000800 */
+#define CAN_IER_LECIE CAN_IER_LECIE_Msk /*!< Last Error Code Interrupt Enable */
+#define CAN_IER_ERRIE_Pos (15U)
+#define CAN_IER_ERRIE_Msk (0x1U << CAN_IER_ERRIE_Pos) /*!< 0x00008000 */
+#define CAN_IER_ERRIE CAN_IER_ERRIE_Msk /*!< Error Interrupt Enable */
+#define CAN_IER_WKUIE_Pos (16U)
+#define CAN_IER_WKUIE_Msk (0x1U << CAN_IER_WKUIE_Pos) /*!< 0x00010000 */
+#define CAN_IER_WKUIE CAN_IER_WKUIE_Msk /*!< Wakeup Interrupt Enable */
+#define CAN_IER_SLKIE_Pos (17U)
+#define CAN_IER_SLKIE_Msk (0x1U << CAN_IER_SLKIE_Pos) /*!< 0x00020000 */
+#define CAN_IER_SLKIE CAN_IER_SLKIE_Msk /*!< Sleep Interrupt Enable */
+
+/******************** Bit definition for CAN_ESR register *******************/
+#define CAN_ESR_EWGF_Pos (0U)
+#define CAN_ESR_EWGF_Msk (0x1U << CAN_ESR_EWGF_Pos) /*!< 0x00000001 */
+#define CAN_ESR_EWGF CAN_ESR_EWGF_Msk /*!< Error Warning Flag */
+#define CAN_ESR_EPVF_Pos (1U)
+#define CAN_ESR_EPVF_Msk (0x1U << CAN_ESR_EPVF_Pos) /*!< 0x00000002 */
+#define CAN_ESR_EPVF CAN_ESR_EPVF_Msk /*!< Error Passive Flag */
+#define CAN_ESR_BOFF_Pos (2U)
+#define CAN_ESR_BOFF_Msk (0x1U << CAN_ESR_BOFF_Pos) /*!< 0x00000004 */
+#define CAN_ESR_BOFF CAN_ESR_BOFF_Msk /*!< Bus-Off Flag */
+
+#define CAN_ESR_LEC_Pos (4U)
+#define CAN_ESR_LEC_Msk (0x7U << CAN_ESR_LEC_Pos) /*!< 0x00000070 */
+#define CAN_ESR_LEC CAN_ESR_LEC_Msk /*!< LEC[2:0] bits (Last Error Code) */
+#define CAN_ESR_LEC_0 (0x1U << CAN_ESR_LEC_Pos) /*!< 0x00000010 */
+#define CAN_ESR_LEC_1 (0x2U << CAN_ESR_LEC_Pos) /*!< 0x00000020 */
+#define CAN_ESR_LEC_2 (0x4U << CAN_ESR_LEC_Pos) /*!< 0x00000040 */
+
+#define CAN_ESR_TEC_Pos (16U)
+#define CAN_ESR_TEC_Msk (0xFFU << CAN_ESR_TEC_Pos) /*!< 0x00FF0000 */
+#define CAN_ESR_TEC CAN_ESR_TEC_Msk /*!< Least significant byte of the 9-bit Transmit Error Counter */
+#define CAN_ESR_REC_Pos (24U)
+#define CAN_ESR_REC_Msk (0xFFU << CAN_ESR_REC_Pos) /*!< 0xFF000000 */
+#define CAN_ESR_REC CAN_ESR_REC_Msk /*!< Receive Error Counter */
+
+/******************* Bit definition for CAN_BTR register ********************/
+#define CAN_BTR_BRP_Pos (0U)
+#define CAN_BTR_BRP_Msk (0x3FFU << CAN_BTR_BRP_Pos) /*!< 0x000003FF */
+#define CAN_BTR_BRP CAN_BTR_BRP_Msk /*!<Baud Rate Prescaler */
+#define CAN_BTR_TS1_Pos (16U)
+#define CAN_BTR_TS1_Msk (0xFU << CAN_BTR_TS1_Pos) /*!< 0x000F0000 */
+#define CAN_BTR_TS1 CAN_BTR_TS1_Msk /*!<Time Segment 1 */
+#define CAN_BTR_TS1_0 (0x1U << CAN_BTR_TS1_Pos) /*!< 0x00010000 */
+#define CAN_BTR_TS1_1 (0x2U << CAN_BTR_TS1_Pos) /*!< 0x00020000 */
+#define CAN_BTR_TS1_2 (0x4U << CAN_BTR_TS1_Pos) /*!< 0x00040000 */
+#define CAN_BTR_TS1_3 (0x8U << CAN_BTR_TS1_Pos) /*!< 0x00080000 */
+#define CAN_BTR_TS2_Pos (20U)
+#define CAN_BTR_TS2_Msk (0x7U << CAN_BTR_TS2_Pos) /*!< 0x00700000 */
+#define CAN_BTR_TS2 CAN_BTR_TS2_Msk /*!<Time Segment 2 */
+#define CAN_BTR_TS2_0 (0x1U << CAN_BTR_TS2_Pos) /*!< 0x00100000 */
+#define CAN_BTR_TS2_1 (0x2U << CAN_BTR_TS2_Pos) /*!< 0x00200000 */
+#define CAN_BTR_TS2_2 (0x4U << CAN_BTR_TS2_Pos) /*!< 0x00400000 */
+#define CAN_BTR_SJW_Pos (24U)
+#define CAN_BTR_SJW_Msk (0x3U << CAN_BTR_SJW_Pos) /*!< 0x03000000 */
+#define CAN_BTR_SJW CAN_BTR_SJW_Msk /*!<Resynchronization Jump Width */
+#define CAN_BTR_SJW_0 (0x1U << CAN_BTR_SJW_Pos) /*!< 0x01000000 */
+#define CAN_BTR_SJW_1 (0x2U << CAN_BTR_SJW_Pos) /*!< 0x02000000 */
+#define CAN_BTR_LBKM_Pos (30U)
+#define CAN_BTR_LBKM_Msk (0x1U << CAN_BTR_LBKM_Pos) /*!< 0x40000000 */
+#define CAN_BTR_LBKM CAN_BTR_LBKM_Msk /*!<Loop Back Mode (Debug) */
+#define CAN_BTR_SILM_Pos (31U)
+#define CAN_BTR_SILM_Msk (0x1U << CAN_BTR_SILM_Pos) /*!< 0x80000000 */
+#define CAN_BTR_SILM CAN_BTR_SILM_Msk /*!<Silent Mode */
+
+/*!< Mailbox registers */
+/****************** Bit definition for CAN_TI0R register ********************/
+#define CAN_TI0R_TXRQ_Pos (0U)
+#define CAN_TI0R_TXRQ_Msk (0x1U << CAN_TI0R_TXRQ_Pos) /*!< 0x00000001 */
+#define CAN_TI0R_TXRQ CAN_TI0R_TXRQ_Msk /*!< Transmit Mailbox Request */
+#define CAN_TI0R_RTR_Pos (1U)
+#define CAN_TI0R_RTR_Msk (0x1U << CAN_TI0R_RTR_Pos) /*!< 0x00000002 */
+#define CAN_TI0R_RTR CAN_TI0R_RTR_Msk /*!< Remote Transmission Request */
+#define CAN_TI0R_IDE_Pos (2U)
+#define CAN_TI0R_IDE_Msk (0x1U << CAN_TI0R_IDE_Pos) /*!< 0x00000004 */
+#define CAN_TI0R_IDE CAN_TI0R_IDE_Msk /*!< Identifier Extension */
+#define CAN_TI0R_EXID_Pos (3U)
+#define CAN_TI0R_EXID_Msk (0x3FFFFU << CAN_TI0R_EXID_Pos) /*!< 0x001FFFF8 */
+#define CAN_TI0R_EXID CAN_TI0R_EXID_Msk /*!< Extended Identifier */
+#define CAN_TI0R_STID_Pos (21U)
+#define CAN_TI0R_STID_Msk (0x7FFU << CAN_TI0R_STID_Pos) /*!< 0xFFE00000 */
+#define CAN_TI0R_STID CAN_TI0R_STID_Msk /*!< Standard Identifier or Extended Identifier */
+
+/****************** Bit definition for CAN_TDT0R register *******************/
+#define CAN_TDT0R_DLC_Pos (0U)
+#define CAN_TDT0R_DLC_Msk (0xFU << CAN_TDT0R_DLC_Pos) /*!< 0x0000000F */
+#define CAN_TDT0R_DLC CAN_TDT0R_DLC_Msk /*!< Data Length Code */
+#define CAN_TDT0R_TGT_Pos (8U)
+#define CAN_TDT0R_TGT_Msk (0x1U << CAN_TDT0R_TGT_Pos) /*!< 0x00000100 */
+#define CAN_TDT0R_TGT CAN_TDT0R_TGT_Msk /*!< Transmit Global Time */
+#define CAN_TDT0R_TIME_Pos (16U)
+#define CAN_TDT0R_TIME_Msk (0xFFFFU << CAN_TDT0R_TIME_Pos) /*!< 0xFFFF0000 */
+#define CAN_TDT0R_TIME CAN_TDT0R_TIME_Msk /*!< Message Time Stamp */
+
+/****************** Bit definition for CAN_TDL0R register *******************/
+#define CAN_TDL0R_DATA0_Pos (0U)
+#define CAN_TDL0R_DATA0_Msk (0xFFU << CAN_TDL0R_DATA0_Pos) /*!< 0x000000FF */
+#define CAN_TDL0R_DATA0 CAN_TDL0R_DATA0_Msk /*!< Data byte 0 */
+#define CAN_TDL0R_DATA1_Pos (8U)
+#define CAN_TDL0R_DATA1_Msk (0xFFU << CAN_TDL0R_DATA1_Pos) /*!< 0x0000FF00 */
+#define CAN_TDL0R_DATA1 CAN_TDL0R_DATA1_Msk /*!< Data byte 1 */
+#define CAN_TDL0R_DATA2_Pos (16U)
+#define CAN_TDL0R_DATA2_Msk (0xFFU << CAN_TDL0R_DATA2_Pos) /*!< 0x00FF0000 */
+#define CAN_TDL0R_DATA2 CAN_TDL0R_DATA2_Msk /*!< Data byte 2 */
+#define CAN_TDL0R_DATA3_Pos (24U)
+#define CAN_TDL0R_DATA3_Msk (0xFFU << CAN_TDL0R_DATA3_Pos) /*!< 0xFF000000 */
+#define CAN_TDL0R_DATA3 CAN_TDL0R_DATA3_Msk /*!< Data byte 3 */
+
+/****************** Bit definition for CAN_TDH0R register *******************/
+#define CAN_TDH0R_DATA4_Pos (0U)
+#define CAN_TDH0R_DATA4_Msk (0xFFU << CAN_TDH0R_DATA4_Pos) /*!< 0x000000FF */
+#define CAN_TDH0R_DATA4 CAN_TDH0R_DATA4_Msk /*!< Data byte 4 */
+#define CAN_TDH0R_DATA5_Pos (8U)
+#define CAN_TDH0R_DATA5_Msk (0xFFU << CAN_TDH0R_DATA5_Pos) /*!< 0x0000FF00 */
+#define CAN_TDH0R_DATA5 CAN_TDH0R_DATA5_Msk /*!< Data byte 5 */
+#define CAN_TDH0R_DATA6_Pos (16U)
+#define CAN_TDH0R_DATA6_Msk (0xFFU << CAN_TDH0R_DATA6_Pos) /*!< 0x00FF0000 */
+#define CAN_TDH0R_DATA6 CAN_TDH0R_DATA6_Msk /*!< Data byte 6 */
+#define CAN_TDH0R_DATA7_Pos (24U)
+#define CAN_TDH0R_DATA7_Msk (0xFFU << CAN_TDH0R_DATA7_Pos) /*!< 0xFF000000 */
+#define CAN_TDH0R_DATA7 CAN_TDH0R_DATA7_Msk /*!< Data byte 7 */
+
+/******************* Bit definition for CAN_TI1R register *******************/
+#define CAN_TI1R_TXRQ_Pos (0U)
+#define CAN_TI1R_TXRQ_Msk (0x1U << CAN_TI1R_TXRQ_Pos) /*!< 0x00000001 */
+#define CAN_TI1R_TXRQ CAN_TI1R_TXRQ_Msk /*!< Transmit Mailbox Request */
+#define CAN_TI1R_RTR_Pos (1U)
+#define CAN_TI1R_RTR_Msk (0x1U << CAN_TI1R_RTR_Pos) /*!< 0x00000002 */
+#define CAN_TI1R_RTR CAN_TI1R_RTR_Msk /*!< Remote Transmission Request */
+#define CAN_TI1R_IDE_Pos (2U)
+#define CAN_TI1R_IDE_Msk (0x1U << CAN_TI1R_IDE_Pos) /*!< 0x00000004 */
+#define CAN_TI1R_IDE CAN_TI1R_IDE_Msk /*!< Identifier Extension */
+#define CAN_TI1R_EXID_Pos (3U)
+#define CAN_TI1R_EXID_Msk (0x3FFFFU << CAN_TI1R_EXID_Pos) /*!< 0x001FFFF8 */
+#define CAN_TI1R_EXID CAN_TI1R_EXID_Msk /*!< Extended Identifier */
+#define CAN_TI1R_STID_Pos (21U)
+#define CAN_TI1R_STID_Msk (0x7FFU << CAN_TI1R_STID_Pos) /*!< 0xFFE00000 */
+#define CAN_TI1R_STID CAN_TI1R_STID_Msk /*!< Standard Identifier or Extended Identifier */
+
+/******************* Bit definition for CAN_TDT1R register ******************/
+#define CAN_TDT1R_DLC_Pos (0U)
+#define CAN_TDT1R_DLC_Msk (0xFU << CAN_TDT1R_DLC_Pos) /*!< 0x0000000F */
+#define CAN_TDT1R_DLC CAN_TDT1R_DLC_Msk /*!< Data Length Code */
+#define CAN_TDT1R_TGT_Pos (8U)
+#define CAN_TDT1R_TGT_Msk (0x1U << CAN_TDT1R_TGT_Pos) /*!< 0x00000100 */
+#define CAN_TDT1R_TGT CAN_TDT1R_TGT_Msk /*!< Transmit Global Time */
+#define CAN_TDT1R_TIME_Pos (16U)
+#define CAN_TDT1R_TIME_Msk (0xFFFFU << CAN_TDT1R_TIME_Pos) /*!< 0xFFFF0000 */
+#define CAN_TDT1R_TIME CAN_TDT1R_TIME_Msk /*!< Message Time Stamp */
+
+/******************* Bit definition for CAN_TDL1R register ******************/
+#define CAN_TDL1R_DATA0_Pos (0U)
+#define CAN_TDL1R_DATA0_Msk (0xFFU << CAN_TDL1R_DATA0_Pos) /*!< 0x000000FF */
+#define CAN_TDL1R_DATA0 CAN_TDL1R_DATA0_Msk /*!< Data byte 0 */
+#define CAN_TDL1R_DATA1_Pos (8U)
+#define CAN_TDL1R_DATA1_Msk (0xFFU << CAN_TDL1R_DATA1_Pos) /*!< 0x0000FF00 */
+#define CAN_TDL1R_DATA1 CAN_TDL1R_DATA1_Msk /*!< Data byte 1 */
+#define CAN_TDL1R_DATA2_Pos (16U)
+#define CAN_TDL1R_DATA2_Msk (0xFFU << CAN_TDL1R_DATA2_Pos) /*!< 0x00FF0000 */
+#define CAN_TDL1R_DATA2 CAN_TDL1R_DATA2_Msk /*!< Data byte 2 */
+#define CAN_TDL1R_DATA3_Pos (24U)
+#define CAN_TDL1R_DATA3_Msk (0xFFU << CAN_TDL1R_DATA3_Pos) /*!< 0xFF000000 */
+#define CAN_TDL1R_DATA3 CAN_TDL1R_DATA3_Msk /*!< Data byte 3 */
+
+/******************* Bit definition for CAN_TDH1R register ******************/
+#define CAN_TDH1R_DATA4_Pos (0U)
+#define CAN_TDH1R_DATA4_Msk (0xFFU << CAN_TDH1R_DATA4_Pos) /*!< 0x000000FF */
+#define CAN_TDH1R_DATA4 CAN_TDH1R_DATA4_Msk /*!< Data byte 4 */
+#define CAN_TDH1R_DATA5_Pos (8U)
+#define CAN_TDH1R_DATA5_Msk (0xFFU << CAN_TDH1R_DATA5_Pos) /*!< 0x0000FF00 */
+#define CAN_TDH1R_DATA5 CAN_TDH1R_DATA5_Msk /*!< Data byte 5 */
+#define CAN_TDH1R_DATA6_Pos (16U)
+#define CAN_TDH1R_DATA6_Msk (0xFFU << CAN_TDH1R_DATA6_Pos) /*!< 0x00FF0000 */
+#define CAN_TDH1R_DATA6 CAN_TDH1R_DATA6_Msk /*!< Data byte 6 */
+#define CAN_TDH1R_DATA7_Pos (24U)
+#define CAN_TDH1R_DATA7_Msk (0xFFU << CAN_TDH1R_DATA7_Pos) /*!< 0xFF000000 */
+#define CAN_TDH1R_DATA7 CAN_TDH1R_DATA7_Msk /*!< Data byte 7 */
+
+/******************* Bit definition for CAN_TI2R register *******************/
+#define CAN_TI2R_TXRQ_Pos (0U)
+#define CAN_TI2R_TXRQ_Msk (0x1U << CAN_TI2R_TXRQ_Pos) /*!< 0x00000001 */
+#define CAN_TI2R_TXRQ CAN_TI2R_TXRQ_Msk /*!< Transmit Mailbox Request */
+#define CAN_TI2R_RTR_Pos (1U)
+#define CAN_TI2R_RTR_Msk (0x1U << CAN_TI2R_RTR_Pos) /*!< 0x00000002 */
+#define CAN_TI2R_RTR CAN_TI2R_RTR_Msk /*!< Remote Transmission Request */
+#define CAN_TI2R_IDE_Pos (2U)
+#define CAN_TI2R_IDE_Msk (0x1U << CAN_TI2R_IDE_Pos) /*!< 0x00000004 */
+#define CAN_TI2R_IDE CAN_TI2R_IDE_Msk /*!< Identifier Extension */
+#define CAN_TI2R_EXID_Pos (3U)
+#define CAN_TI2R_EXID_Msk (0x3FFFFU << CAN_TI2R_EXID_Pos) /*!< 0x001FFFF8 */
+#define CAN_TI2R_EXID CAN_TI2R_EXID_Msk /*!< Extended identifier */
+#define CAN_TI2R_STID_Pos (21U)
+#define CAN_TI2R_STID_Msk (0x7FFU << CAN_TI2R_STID_Pos) /*!< 0xFFE00000 */
+#define CAN_TI2R_STID CAN_TI2R_STID_Msk /*!< Standard Identifier or Extended Identifier */
+
+/******************* Bit definition for CAN_TDT2R register ******************/
+#define CAN_TDT2R_DLC_Pos (0U)
+#define CAN_TDT2R_DLC_Msk (0xFU << CAN_TDT2R_DLC_Pos) /*!< 0x0000000F */
+#define CAN_TDT2R_DLC CAN_TDT2R_DLC_Msk /*!< Data Length Code */
+#define CAN_TDT2R_TGT_Pos (8U)
+#define CAN_TDT2R_TGT_Msk (0x1U << CAN_TDT2R_TGT_Pos) /*!< 0x00000100 */
+#define CAN_TDT2R_TGT CAN_TDT2R_TGT_Msk /*!< Transmit Global Time */
+#define CAN_TDT2R_TIME_Pos (16U)
+#define CAN_TDT2R_TIME_Msk (0xFFFFU << CAN_TDT2R_TIME_Pos) /*!< 0xFFFF0000 */
+#define CAN_TDT2R_TIME CAN_TDT2R_TIME_Msk /*!< Message Time Stamp */
+
+/******************* Bit definition for CAN_TDL2R register ******************/
+#define CAN_TDL2R_DATA0_Pos (0U)
+#define CAN_TDL2R_DATA0_Msk (0xFFU << CAN_TDL2R_DATA0_Pos) /*!< 0x000000FF */
+#define CAN_TDL2R_DATA0 CAN_TDL2R_DATA0_Msk /*!< Data byte 0 */
+#define CAN_TDL2R_DATA1_Pos (8U)
+#define CAN_TDL2R_DATA1_Msk (0xFFU << CAN_TDL2R_DATA1_Pos) /*!< 0x0000FF00 */
+#define CAN_TDL2R_DATA1 CAN_TDL2R_DATA1_Msk /*!< Data byte 1 */
+#define CAN_TDL2R_DATA2_Pos (16U)
+#define CAN_TDL2R_DATA2_Msk (0xFFU << CAN_TDL2R_DATA2_Pos) /*!< 0x00FF0000 */
+#define CAN_TDL2R_DATA2 CAN_TDL2R_DATA2_Msk /*!< Data byte 2 */
+#define CAN_TDL2R_DATA3_Pos (24U)
+#define CAN_TDL2R_DATA3_Msk (0xFFU << CAN_TDL2R_DATA3_Pos) /*!< 0xFF000000 */
+#define CAN_TDL2R_DATA3 CAN_TDL2R_DATA3_Msk /*!< Data byte 3 */
+
+/******************* Bit definition for CAN_TDH2R register ******************/
+#define CAN_TDH2R_DATA4_Pos (0U)
+#define CAN_TDH2R_DATA4_Msk (0xFFU << CAN_TDH2R_DATA4_Pos) /*!< 0x000000FF */
+#define CAN_TDH2R_DATA4 CAN_TDH2R_DATA4_Msk /*!< Data byte 4 */
+#define CAN_TDH2R_DATA5_Pos (8U)
+#define CAN_TDH2R_DATA5_Msk (0xFFU << CAN_TDH2R_DATA5_Pos) /*!< 0x0000FF00 */
+#define CAN_TDH2R_DATA5 CAN_TDH2R_DATA5_Msk /*!< Data byte 5 */
+#define CAN_TDH2R_DATA6_Pos (16U)
+#define CAN_TDH2R_DATA6_Msk (0xFFU << CAN_TDH2R_DATA6_Pos) /*!< 0x00FF0000 */
+#define CAN_TDH2R_DATA6 CAN_TDH2R_DATA6_Msk /*!< Data byte 6 */
+#define CAN_TDH2R_DATA7_Pos (24U)
+#define CAN_TDH2R_DATA7_Msk (0xFFU << CAN_TDH2R_DATA7_Pos) /*!< 0xFF000000 */
+#define CAN_TDH2R_DATA7 CAN_TDH2R_DATA7_Msk /*!< Data byte 7 */
+
+/******************* Bit definition for CAN_RI0R register *******************/
+#define CAN_RI0R_RTR_Pos (1U)
+#define CAN_RI0R_RTR_Msk (0x1U << CAN_RI0R_RTR_Pos) /*!< 0x00000002 */
+#define CAN_RI0R_RTR CAN_RI0R_RTR_Msk /*!< Remote Transmission Request */
+#define CAN_RI0R_IDE_Pos (2U)
+#define CAN_RI0R_IDE_Msk (0x1U << CAN_RI0R_IDE_Pos) /*!< 0x00000004 */
+#define CAN_RI0R_IDE CAN_RI0R_IDE_Msk /*!< Identifier Extension */
+#define CAN_RI0R_EXID_Pos (3U)
+#define CAN_RI0R_EXID_Msk (0x3FFFFU << CAN_RI0R_EXID_Pos) /*!< 0x001FFFF8 */
+#define CAN_RI0R_EXID CAN_RI0R_EXID_Msk /*!< Extended Identifier */
+#define CAN_RI0R_STID_Pos (21U)
+#define CAN_RI0R_STID_Msk (0x7FFU << CAN_RI0R_STID_Pos) /*!< 0xFFE00000 */
+#define CAN_RI0R_STID CAN_RI0R_STID_Msk /*!< Standard Identifier or Extended Identifier */
+
+/******************* Bit definition for CAN_RDT0R register ******************/
+#define CAN_RDT0R_DLC_Pos (0U)
+#define CAN_RDT0R_DLC_Msk (0xFU << CAN_RDT0R_DLC_Pos) /*!< 0x0000000F */
+#define CAN_RDT0R_DLC CAN_RDT0R_DLC_Msk /*!< Data Length Code */
+#define CAN_RDT0R_FMI_Pos (8U)
+#define CAN_RDT0R_FMI_Msk (0xFFU << CAN_RDT0R_FMI_Pos) /*!< 0x0000FF00 */
+#define CAN_RDT0R_FMI CAN_RDT0R_FMI_Msk /*!< Filter Match Index */
+#define CAN_RDT0R_TIME_Pos (16U)
+#define CAN_RDT0R_TIME_Msk (0xFFFFU << CAN_RDT0R_TIME_Pos) /*!< 0xFFFF0000 */
+#define CAN_RDT0R_TIME CAN_RDT0R_TIME_Msk /*!< Message Time Stamp */
+
+/******************* Bit definition for CAN_RDL0R register ******************/
+#define CAN_RDL0R_DATA0_Pos (0U)
+#define CAN_RDL0R_DATA0_Msk (0xFFU << CAN_RDL0R_DATA0_Pos) /*!< 0x000000FF */
+#define CAN_RDL0R_DATA0 CAN_RDL0R_DATA0_Msk /*!< Data byte 0 */
+#define CAN_RDL0R_DATA1_Pos (8U)
+#define CAN_RDL0R_DATA1_Msk (0xFFU << CAN_RDL0R_DATA1_Pos) /*!< 0x0000FF00 */
+#define CAN_RDL0R_DATA1 CAN_RDL0R_DATA1_Msk /*!< Data byte 1 */
+#define CAN_RDL0R_DATA2_Pos (16U)
+#define CAN_RDL0R_DATA2_Msk (0xFFU << CAN_RDL0R_DATA2_Pos) /*!< 0x00FF0000 */
+#define CAN_RDL0R_DATA2 CAN_RDL0R_DATA2_Msk /*!< Data byte 2 */
+#define CAN_RDL0R_DATA3_Pos (24U)
+#define CAN_RDL0R_DATA3_Msk (0xFFU << CAN_RDL0R_DATA3_Pos) /*!< 0xFF000000 */
+#define CAN_RDL0R_DATA3 CAN_RDL0R_DATA3_Msk /*!< Data byte 3 */
+
+/******************* Bit definition for CAN_RDH0R register ******************/
+#define CAN_RDH0R_DATA4_Pos (0U)
+#define CAN_RDH0R_DATA4_Msk (0xFFU << CAN_RDH0R_DATA4_Pos) /*!< 0x000000FF */
+#define CAN_RDH0R_DATA4 CAN_RDH0R_DATA4_Msk /*!< Data byte 4 */
+#define CAN_RDH0R_DATA5_Pos (8U)
+#define CAN_RDH0R_DATA5_Msk (0xFFU << CAN_RDH0R_DATA5_Pos) /*!< 0x0000FF00 */
+#define CAN_RDH0R_DATA5 CAN_RDH0R_DATA5_Msk /*!< Data byte 5 */
+#define CAN_RDH0R_DATA6_Pos (16U)
+#define CAN_RDH0R_DATA6_Msk (0xFFU << CAN_RDH0R_DATA6_Pos) /*!< 0x00FF0000 */
+#define CAN_RDH0R_DATA6 CAN_RDH0R_DATA6_Msk /*!< Data byte 6 */
+#define CAN_RDH0R_DATA7_Pos (24U)
+#define CAN_RDH0R_DATA7_Msk (0xFFU << CAN_RDH0R_DATA7_Pos) /*!< 0xFF000000 */
+#define CAN_RDH0R_DATA7 CAN_RDH0R_DATA7_Msk /*!< Data byte 7 */
+
+/******************* Bit definition for CAN_RI1R register *******************/
+#define CAN_RI1R_RTR_Pos (1U)
+#define CAN_RI1R_RTR_Msk (0x1U << CAN_RI1R_RTR_Pos) /*!< 0x00000002 */
+#define CAN_RI1R_RTR CAN_RI1R_RTR_Msk /*!< Remote Transmission Request */
+#define CAN_RI1R_IDE_Pos (2U)
+#define CAN_RI1R_IDE_Msk (0x1U << CAN_RI1R_IDE_Pos) /*!< 0x00000004 */
+#define CAN_RI1R_IDE CAN_RI1R_IDE_Msk /*!< Identifier Extension */
+#define CAN_RI1R_EXID_Pos (3U)
+#define CAN_RI1R_EXID_Msk (0x3FFFFU << CAN_RI1R_EXID_Pos) /*!< 0x001FFFF8 */
+#define CAN_RI1R_EXID CAN_RI1R_EXID_Msk /*!< Extended identifier */
+#define CAN_RI1R_STID_Pos (21U)
+#define CAN_RI1R_STID_Msk (0x7FFU << CAN_RI1R_STID_Pos) /*!< 0xFFE00000 */
+#define CAN_RI1R_STID CAN_RI1R_STID_Msk /*!< Standard Identifier or Extended Identifier */
+
+/******************* Bit definition for CAN_RDT1R register ******************/
+#define CAN_RDT1R_DLC_Pos (0U)
+#define CAN_RDT1R_DLC_Msk (0xFU << CAN_RDT1R_DLC_Pos) /*!< 0x0000000F */
+#define CAN_RDT1R_DLC CAN_RDT1R_DLC_Msk /*!< Data Length Code */
+#define CAN_RDT1R_FMI_Pos (8U)
+#define CAN_RDT1R_FMI_Msk (0xFFU << CAN_RDT1R_FMI_Pos) /*!< 0x0000FF00 */
+#define CAN_RDT1R_FMI CAN_RDT1R_FMI_Msk /*!< Filter Match Index */
+#define CAN_RDT1R_TIME_Pos (16U)
+#define CAN_RDT1R_TIME_Msk (0xFFFFU << CAN_RDT1R_TIME_Pos) /*!< 0xFFFF0000 */
+#define CAN_RDT1R_TIME CAN_RDT1R_TIME_Msk /*!< Message Time Stamp */
+
+/******************* Bit definition for CAN_RDL1R register ******************/
+#define CAN_RDL1R_DATA0_Pos (0U)
+#define CAN_RDL1R_DATA0_Msk (0xFFU << CAN_RDL1R_DATA0_Pos) /*!< 0x000000FF */
+#define CAN_RDL1R_DATA0 CAN_RDL1R_DATA0_Msk /*!< Data byte 0 */
+#define CAN_RDL1R_DATA1_Pos (8U)
+#define CAN_RDL1R_DATA1_Msk (0xFFU << CAN_RDL1R_DATA1_Pos) /*!< 0x0000FF00 */
+#define CAN_RDL1R_DATA1 CAN_RDL1R_DATA1_Msk /*!< Data byte 1 */
+#define CAN_RDL1R_DATA2_Pos (16U)
+#define CAN_RDL1R_DATA2_Msk (0xFFU << CAN_RDL1R_DATA2_Pos) /*!< 0x00FF0000 */
+#define CAN_RDL1R_DATA2 CAN_RDL1R_DATA2_Msk /*!< Data byte 2 */
+#define CAN_RDL1R_DATA3_Pos (24U)
+#define CAN_RDL1R_DATA3_Msk (0xFFU << CAN_RDL1R_DATA3_Pos) /*!< 0xFF000000 */
+#define CAN_RDL1R_DATA3 CAN_RDL1R_DATA3_Msk /*!< Data byte 3 */
+
+/******************* Bit definition for CAN_RDH1R register ******************/
+#define CAN_RDH1R_DATA4_Pos (0U)
+#define CAN_RDH1R_DATA4_Msk (0xFFU << CAN_RDH1R_DATA4_Pos) /*!< 0x000000FF */
+#define CAN_RDH1R_DATA4 CAN_RDH1R_DATA4_Msk /*!< Data byte 4 */
+#define CAN_RDH1R_DATA5_Pos (8U)
+#define CAN_RDH1R_DATA5_Msk (0xFFU << CAN_RDH1R_DATA5_Pos) /*!< 0x0000FF00 */
+#define CAN_RDH1R_DATA5 CAN_RDH1R_DATA5_Msk /*!< Data byte 5 */
+#define CAN_RDH1R_DATA6_Pos (16U)
+#define CAN_RDH1R_DATA6_Msk (0xFFU << CAN_RDH1R_DATA6_Pos) /*!< 0x00FF0000 */
+#define CAN_RDH1R_DATA6 CAN_RDH1R_DATA6_Msk /*!< Data byte 6 */
+#define CAN_RDH1R_DATA7_Pos (24U)
+#define CAN_RDH1R_DATA7_Msk (0xFFU << CAN_RDH1R_DATA7_Pos) /*!< 0xFF000000 */
+#define CAN_RDH1R_DATA7 CAN_RDH1R_DATA7_Msk /*!< Data byte 7 */
+
+/*!< CAN filter registers */
+/******************* Bit definition for CAN_FMR register ********************/
+#define CAN_FMR_FINIT_Pos (0U)
+#define CAN_FMR_FINIT_Msk (0x1U << CAN_FMR_FINIT_Pos) /*!< 0x00000001 */
+#define CAN_FMR_FINIT CAN_FMR_FINIT_Msk /*!< Filter Init Mode */
+#define CAN_FMR_CAN2SB_Pos (8U)
+#define CAN_FMR_CAN2SB_Msk (0x3FU << CAN_FMR_CAN2SB_Pos) /*!< 0x00003F00 */
+#define CAN_FMR_CAN2SB CAN_FMR_CAN2SB_Msk /*!< CAN2 start bank */
+
+/******************* Bit definition for CAN_FM1R register *******************/
+#define CAN_FM1R_FBM_Pos (0U)
+#define CAN_FM1R_FBM_Msk (0x3FFFU << CAN_FM1R_FBM_Pos) /*!< 0x00003FFF */
+#define CAN_FM1R_FBM CAN_FM1R_FBM_Msk /*!< Filter Mode */
+#define CAN_FM1R_FBM0_Pos (0U)
+#define CAN_FM1R_FBM0_Msk (0x1U << CAN_FM1R_FBM0_Pos) /*!< 0x00000001 */
+#define CAN_FM1R_FBM0 CAN_FM1R_FBM0_Msk /*!< Filter Init Mode for filter 0 */
+#define CAN_FM1R_FBM1_Pos (1U)
+#define CAN_FM1R_FBM1_Msk (0x1U << CAN_FM1R_FBM1_Pos) /*!< 0x00000002 */
+#define CAN_FM1R_FBM1 CAN_FM1R_FBM1_Msk /*!< Filter Init Mode for filter 1 */
+#define CAN_FM1R_FBM2_Pos (2U)
+#define CAN_FM1R_FBM2_Msk (0x1U << CAN_FM1R_FBM2_Pos) /*!< 0x00000004 */
+#define CAN_FM1R_FBM2 CAN_FM1R_FBM2_Msk /*!< Filter Init Mode for filter 2 */
+#define CAN_FM1R_FBM3_Pos (3U)
+#define CAN_FM1R_FBM3_Msk (0x1U << CAN_FM1R_FBM3_Pos) /*!< 0x00000008 */
+#define CAN_FM1R_FBM3 CAN_FM1R_FBM3_Msk /*!< Filter Init Mode for filter 3 */
+#define CAN_FM1R_FBM4_Pos (4U)
+#define CAN_FM1R_FBM4_Msk (0x1U << CAN_FM1R_FBM4_Pos) /*!< 0x00000010 */
+#define CAN_FM1R_FBM4 CAN_FM1R_FBM4_Msk /*!< Filter Init Mode for filter 4 */
+#define CAN_FM1R_FBM5_Pos (5U)
+#define CAN_FM1R_FBM5_Msk (0x1U << CAN_FM1R_FBM5_Pos) /*!< 0x00000020 */
+#define CAN_FM1R_FBM5 CAN_FM1R_FBM5_Msk /*!< Filter Init Mode for filter 5 */
+#define CAN_FM1R_FBM6_Pos (6U)
+#define CAN_FM1R_FBM6_Msk (0x1U << CAN_FM1R_FBM6_Pos) /*!< 0x00000040 */
+#define CAN_FM1R_FBM6 CAN_FM1R_FBM6_Msk /*!< Filter Init Mode for filter 6 */
+#define CAN_FM1R_FBM7_Pos (7U)
+#define CAN_FM1R_FBM7_Msk (0x1U << CAN_FM1R_FBM7_Pos) /*!< 0x00000080 */
+#define CAN_FM1R_FBM7 CAN_FM1R_FBM7_Msk /*!< Filter Init Mode for filter 7 */
+#define CAN_FM1R_FBM8_Pos (8U)
+#define CAN_FM1R_FBM8_Msk (0x1U << CAN_FM1R_FBM8_Pos) /*!< 0x00000100 */
+#define CAN_FM1R_FBM8 CAN_FM1R_FBM8_Msk /*!< Filter Init Mode for filter 8 */
+#define CAN_FM1R_FBM9_Pos (9U)
+#define CAN_FM1R_FBM9_Msk (0x1U << CAN_FM1R_FBM9_Pos) /*!< 0x00000200 */
+#define CAN_FM1R_FBM9 CAN_FM1R_FBM9_Msk /*!< Filter Init Mode for filter 9 */
+#define CAN_FM1R_FBM10_Pos (10U)
+#define CAN_FM1R_FBM10_Msk (0x1U << CAN_FM1R_FBM10_Pos) /*!< 0x00000400 */
+#define CAN_FM1R_FBM10 CAN_FM1R_FBM10_Msk /*!< Filter Init Mode for filter 10 */
+#define CAN_FM1R_FBM11_Pos (11U)
+#define CAN_FM1R_FBM11_Msk (0x1U << CAN_FM1R_FBM11_Pos) /*!< 0x00000800 */
+#define CAN_FM1R_FBM11 CAN_FM1R_FBM11_Msk /*!< Filter Init Mode for filter 11 */
+#define CAN_FM1R_FBM12_Pos (12U)
+#define CAN_FM1R_FBM12_Msk (0x1U << CAN_FM1R_FBM12_Pos) /*!< 0x00001000 */
+#define CAN_FM1R_FBM12 CAN_FM1R_FBM12_Msk /*!< Filter Init Mode for filter 12 */
+#define CAN_FM1R_FBM13_Pos (13U)
+#define CAN_FM1R_FBM13_Msk (0x1U << CAN_FM1R_FBM13_Pos) /*!< 0x00002000 */
+#define CAN_FM1R_FBM13 CAN_FM1R_FBM13_Msk /*!< Filter Init Mode for filter 13 */
+
+/******************* Bit definition for CAN_FS1R register *******************/
+#define CAN_FS1R_FSC_Pos (0U)
+#define CAN_FS1R_FSC_Msk (0x3FFFU << CAN_FS1R_FSC_Pos) /*!< 0x00003FFF */
+#define CAN_FS1R_FSC CAN_FS1R_FSC_Msk /*!< Filter Scale Configuration */
+#define CAN_FS1R_FSC0_Pos (0U)
+#define CAN_FS1R_FSC0_Msk (0x1U << CAN_FS1R_FSC0_Pos) /*!< 0x00000001 */
+#define CAN_FS1R_FSC0 CAN_FS1R_FSC0_Msk /*!< Filter Scale Configuration for filter 0 */
+#define CAN_FS1R_FSC1_Pos (1U)
+#define CAN_FS1R_FSC1_Msk (0x1U << CAN_FS1R_FSC1_Pos) /*!< 0x00000002 */
+#define CAN_FS1R_FSC1 CAN_FS1R_FSC1_Msk /*!< Filter Scale Configuration for filter 1 */
+#define CAN_FS1R_FSC2_Pos (2U)
+#define CAN_FS1R_FSC2_Msk (0x1U << CAN_FS1R_FSC2_Pos) /*!< 0x00000004 */
+#define CAN_FS1R_FSC2 CAN_FS1R_FSC2_Msk /*!< Filter Scale Configuration for filter 2 */
+#define CAN_FS1R_FSC3_Pos (3U)
+#define CAN_FS1R_FSC3_Msk (0x1U << CAN_FS1R_FSC3_Pos) /*!< 0x00000008 */
+#define CAN_FS1R_FSC3 CAN_FS1R_FSC3_Msk /*!< Filter Scale Configuration for filter 3 */
+#define CAN_FS1R_FSC4_Pos (4U)
+#define CAN_FS1R_FSC4_Msk (0x1U << CAN_FS1R_FSC4_Pos) /*!< 0x00000010 */
+#define CAN_FS1R_FSC4 CAN_FS1R_FSC4_Msk /*!< Filter Scale Configuration for filter 4 */
+#define CAN_FS1R_FSC5_Pos (5U)
+#define CAN_FS1R_FSC5_Msk (0x1U << CAN_FS1R_FSC5_Pos) /*!< 0x00000020 */
+#define CAN_FS1R_FSC5 CAN_FS1R_FSC5_Msk /*!< Filter Scale Configuration for filter 5 */
+#define CAN_FS1R_FSC6_Pos (6U)
+#define CAN_FS1R_FSC6_Msk (0x1U << CAN_FS1R_FSC6_Pos) /*!< 0x00000040 */
+#define CAN_FS1R_FSC6 CAN_FS1R_FSC6_Msk /*!< Filter Scale Configuration for filter 6 */
+#define CAN_FS1R_FSC7_Pos (7U)
+#define CAN_FS1R_FSC7_Msk (0x1U << CAN_FS1R_FSC7_Pos) /*!< 0x00000080 */
+#define CAN_FS1R_FSC7 CAN_FS1R_FSC7_Msk /*!< Filter Scale Configuration for filter 7 */
+#define CAN_FS1R_FSC8_Pos (8U)
+#define CAN_FS1R_FSC8_Msk (0x1U << CAN_FS1R_FSC8_Pos) /*!< 0x00000100 */
+#define CAN_FS1R_FSC8 CAN_FS1R_FSC8_Msk /*!< Filter Scale Configuration for filter 8 */
+#define CAN_FS1R_FSC9_Pos (9U)
+#define CAN_FS1R_FSC9_Msk (0x1U << CAN_FS1R_FSC9_Pos) /*!< 0x00000200 */
+#define CAN_FS1R_FSC9 CAN_FS1R_FSC9_Msk /*!< Filter Scale Configuration for filter 9 */
+#define CAN_FS1R_FSC10_Pos (10U)
+#define CAN_FS1R_FSC10_Msk (0x1U << CAN_FS1R_FSC10_Pos) /*!< 0x00000400 */
+#define CAN_FS1R_FSC10 CAN_FS1R_FSC10_Msk /*!< Filter Scale Configuration for filter 10 */
+#define CAN_FS1R_FSC11_Pos (11U)
+#define CAN_FS1R_FSC11_Msk (0x1U << CAN_FS1R_FSC11_Pos) /*!< 0x00000800 */
+#define CAN_FS1R_FSC11 CAN_FS1R_FSC11_Msk /*!< Filter Scale Configuration for filter 11 */
+#define CAN_FS1R_FSC12_Pos (12U)
+#define CAN_FS1R_FSC12_Msk (0x1U << CAN_FS1R_FSC12_Pos) /*!< 0x00001000 */
+#define CAN_FS1R_FSC12 CAN_FS1R_FSC12_Msk /*!< Filter Scale Configuration for filter 12 */
+#define CAN_FS1R_FSC13_Pos (13U)
+#define CAN_FS1R_FSC13_Msk (0x1U << CAN_FS1R_FSC13_Pos) /*!< 0x00002000 */
+#define CAN_FS1R_FSC13 CAN_FS1R_FSC13_Msk /*!< Filter Scale Configuration for filter 13 */
+
+/****************** Bit definition for CAN_FFA1R register *******************/
+#define CAN_FFA1R_FFA_Pos (0U)
+#define CAN_FFA1R_FFA_Msk (0x3FFFU << CAN_FFA1R_FFA_Pos) /*!< 0x00003FFF */
+#define CAN_FFA1R_FFA CAN_FFA1R_FFA_Msk /*!< Filter FIFO Assignment */
+#define CAN_FFA1R_FFA0_Pos (0U)
+#define CAN_FFA1R_FFA0_Msk (0x1U << CAN_FFA1R_FFA0_Pos) /*!< 0x00000001 */
+#define CAN_FFA1R_FFA0 CAN_FFA1R_FFA0_Msk /*!< Filter FIFO Assignment for filter 0 */
+#define CAN_FFA1R_FFA1_Pos (1U)
+#define CAN_FFA1R_FFA1_Msk (0x1U << CAN_FFA1R_FFA1_Pos) /*!< 0x00000002 */
+#define CAN_FFA1R_FFA1 CAN_FFA1R_FFA1_Msk /*!< Filter FIFO Assignment for filter 1 */
+#define CAN_FFA1R_FFA2_Pos (2U)
+#define CAN_FFA1R_FFA2_Msk (0x1U << CAN_FFA1R_FFA2_Pos) /*!< 0x00000004 */
+#define CAN_FFA1R_FFA2 CAN_FFA1R_FFA2_Msk /*!< Filter FIFO Assignment for filter 2 */
+#define CAN_FFA1R_FFA3_Pos (3U)
+#define CAN_FFA1R_FFA3_Msk (0x1U << CAN_FFA1R_FFA3_Pos) /*!< 0x00000008 */
+#define CAN_FFA1R_FFA3 CAN_FFA1R_FFA3_Msk /*!< Filter FIFO Assignment for filter 3 */
+#define CAN_FFA1R_FFA4_Pos (4U)
+#define CAN_FFA1R_FFA4_Msk (0x1U << CAN_FFA1R_FFA4_Pos) /*!< 0x00000010 */
+#define CAN_FFA1R_FFA4 CAN_FFA1R_FFA4_Msk /*!< Filter FIFO Assignment for filter 4 */
+#define CAN_FFA1R_FFA5_Pos (5U)
+#define CAN_FFA1R_FFA5_Msk (0x1U << CAN_FFA1R_FFA5_Pos) /*!< 0x00000020 */
+#define CAN_FFA1R_FFA5 CAN_FFA1R_FFA5_Msk /*!< Filter FIFO Assignment for filter 5 */
+#define CAN_FFA1R_FFA6_Pos (6U)
+#define CAN_FFA1R_FFA6_Msk (0x1U << CAN_FFA1R_FFA6_Pos) /*!< 0x00000040 */
+#define CAN_FFA1R_FFA6 CAN_FFA1R_FFA6_Msk /*!< Filter FIFO Assignment for filter 6 */
+#define CAN_FFA1R_FFA7_Pos (7U)
+#define CAN_FFA1R_FFA7_Msk (0x1U << CAN_FFA1R_FFA7_Pos) /*!< 0x00000080 */
+#define CAN_FFA1R_FFA7 CAN_FFA1R_FFA7_Msk /*!< Filter FIFO Assignment for filter 7 */
+#define CAN_FFA1R_FFA8_Pos (8U)
+#define CAN_FFA1R_FFA8_Msk (0x1U << CAN_FFA1R_FFA8_Pos) /*!< 0x00000100 */
+#define CAN_FFA1R_FFA8 CAN_FFA1R_FFA8_Msk /*!< Filter FIFO Assignment for filter 8 */
+#define CAN_FFA1R_FFA9_Pos (9U)
+#define CAN_FFA1R_FFA9_Msk (0x1U << CAN_FFA1R_FFA9_Pos) /*!< 0x00000200 */
+#define CAN_FFA1R_FFA9 CAN_FFA1R_FFA9_Msk /*!< Filter FIFO Assignment for filter 9 */
+#define CAN_FFA1R_FFA10_Pos (10U)
+#define CAN_FFA1R_FFA10_Msk (0x1U << CAN_FFA1R_FFA10_Pos) /*!< 0x00000400 */
+#define CAN_FFA1R_FFA10 CAN_FFA1R_FFA10_Msk /*!< Filter FIFO Assignment for filter 10 */
+#define CAN_FFA1R_FFA11_Pos (11U)
+#define CAN_FFA1R_FFA11_Msk (0x1U << CAN_FFA1R_FFA11_Pos) /*!< 0x00000800 */
+#define CAN_FFA1R_FFA11 CAN_FFA1R_FFA11_Msk /*!< Filter FIFO Assignment for filter 11 */
+#define CAN_FFA1R_FFA12_Pos (12U)
+#define CAN_FFA1R_FFA12_Msk (0x1U << CAN_FFA1R_FFA12_Pos) /*!< 0x00001000 */
+#define CAN_FFA1R_FFA12 CAN_FFA1R_FFA12_Msk /*!< Filter FIFO Assignment for filter 12 */
+#define CAN_FFA1R_FFA13_Pos (13U)
+#define CAN_FFA1R_FFA13_Msk (0x1U << CAN_FFA1R_FFA13_Pos) /*!< 0x00002000 */
+#define CAN_FFA1R_FFA13 CAN_FFA1R_FFA13_Msk /*!< Filter FIFO Assignment for filter 13 */
+
+/******************* Bit definition for CAN_FA1R register *******************/
+#define CAN_FA1R_FACT_Pos (0U)
+#define CAN_FA1R_FACT_Msk (0x3FFFU << CAN_FA1R_FACT_Pos) /*!< 0x00003FFF */
+#define CAN_FA1R_FACT CAN_FA1R_FACT_Msk /*!< Filter Active */
+#define CAN_FA1R_FACT0_Pos (0U)
+#define CAN_FA1R_FACT0_Msk (0x1U << CAN_FA1R_FACT0_Pos) /*!< 0x00000001 */
+#define CAN_FA1R_FACT0 CAN_FA1R_FACT0_Msk /*!< Filter 0 Active */
+#define CAN_FA1R_FACT1_Pos (1U)
+#define CAN_FA1R_FACT1_Msk (0x1U << CAN_FA1R_FACT1_Pos) /*!< 0x00000002 */
+#define CAN_FA1R_FACT1 CAN_FA1R_FACT1_Msk /*!< Filter 1 Active */
+#define CAN_FA1R_FACT2_Pos (2U)
+#define CAN_FA1R_FACT2_Msk (0x1U << CAN_FA1R_FACT2_Pos) /*!< 0x00000004 */
+#define CAN_FA1R_FACT2 CAN_FA1R_FACT2_Msk /*!< Filter 2 Active */
+#define CAN_FA1R_FACT3_Pos (3U)
+#define CAN_FA1R_FACT3_Msk (0x1U << CAN_FA1R_FACT3_Pos) /*!< 0x00000008 */
+#define CAN_FA1R_FACT3 CAN_FA1R_FACT3_Msk /*!< Filter 3 Active */
+#define CAN_FA1R_FACT4_Pos (4U)
+#define CAN_FA1R_FACT4_Msk (0x1U << CAN_FA1R_FACT4_Pos) /*!< 0x00000010 */
+#define CAN_FA1R_FACT4 CAN_FA1R_FACT4_Msk /*!< Filter 4 Active */
+#define CAN_FA1R_FACT5_Pos (5U)
+#define CAN_FA1R_FACT5_Msk (0x1U << CAN_FA1R_FACT5_Pos) /*!< 0x00000020 */
+#define CAN_FA1R_FACT5 CAN_FA1R_FACT5_Msk /*!< Filter 5 Active */
+#define CAN_FA1R_FACT6_Pos (6U)
+#define CAN_FA1R_FACT6_Msk (0x1U << CAN_FA1R_FACT6_Pos) /*!< 0x00000040 */
+#define CAN_FA1R_FACT6 CAN_FA1R_FACT6_Msk /*!< Filter 6 Active */
+#define CAN_FA1R_FACT7_Pos (7U)
+#define CAN_FA1R_FACT7_Msk (0x1U << CAN_FA1R_FACT7_Pos) /*!< 0x00000080 */
+#define CAN_FA1R_FACT7 CAN_FA1R_FACT7_Msk /*!< Filter 7 Active */
+#define CAN_FA1R_FACT8_Pos (8U)
+#define CAN_FA1R_FACT8_Msk (0x1U << CAN_FA1R_FACT8_Pos) /*!< 0x00000100 */
+#define CAN_FA1R_FACT8 CAN_FA1R_FACT8_Msk /*!< Filter 8 Active */
+#define CAN_FA1R_FACT9_Pos (9U)
+#define CAN_FA1R_FACT9_Msk (0x1U << CAN_FA1R_FACT9_Pos) /*!< 0x00000200 */
+#define CAN_FA1R_FACT9 CAN_FA1R_FACT9_Msk /*!< Filter 9 Active */
+#define CAN_FA1R_FACT10_Pos (10U)
+#define CAN_FA1R_FACT10_Msk (0x1U << CAN_FA1R_FACT10_Pos) /*!< 0x00000400 */
+#define CAN_FA1R_FACT10 CAN_FA1R_FACT10_Msk /*!< Filter 10 Active */
+#define CAN_FA1R_FACT11_Pos (11U)
+#define CAN_FA1R_FACT11_Msk (0x1U << CAN_FA1R_FACT11_Pos) /*!< 0x00000800 */
+#define CAN_FA1R_FACT11 CAN_FA1R_FACT11_Msk /*!< Filter 11 Active */
+#define CAN_FA1R_FACT12_Pos (12U)
+#define CAN_FA1R_FACT12_Msk (0x1U << CAN_FA1R_FACT12_Pos) /*!< 0x00001000 */
+#define CAN_FA1R_FACT12 CAN_FA1R_FACT12_Msk /*!< Filter 12 Active */
+#define CAN_FA1R_FACT13_Pos (13U)
+#define CAN_FA1R_FACT13_Msk (0x1U << CAN_FA1R_FACT13_Pos) /*!< 0x00002000 */
+#define CAN_FA1R_FACT13 CAN_FA1R_FACT13_Msk /*!< Filter 13 Active */
+
+/******************* Bit definition for CAN_F0R1 register *******************/
+#define CAN_F0R1_FB0_Pos (0U)
+#define CAN_F0R1_FB0_Msk (0x1U << CAN_F0R1_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F0R1_FB0 CAN_F0R1_FB0_Msk /*!< Filter bit 0 */
+#define CAN_F0R1_FB1_Pos (1U)
+#define CAN_F0R1_FB1_Msk (0x1U << CAN_F0R1_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F0R1_FB1 CAN_F0R1_FB1_Msk /*!< Filter bit 1 */
+#define CAN_F0R1_FB2_Pos (2U)
+#define CAN_F0R1_FB2_Msk (0x1U << CAN_F0R1_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F0R1_FB2 CAN_F0R1_FB2_Msk /*!< Filter bit 2 */
+#define CAN_F0R1_FB3_Pos (3U)
+#define CAN_F0R1_FB3_Msk (0x1U << CAN_F0R1_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F0R1_FB3 CAN_F0R1_FB3_Msk /*!< Filter bit 3 */
+#define CAN_F0R1_FB4_Pos (4U)
+#define CAN_F0R1_FB4_Msk (0x1U << CAN_F0R1_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F0R1_FB4 CAN_F0R1_FB4_Msk /*!< Filter bit 4 */
+#define CAN_F0R1_FB5_Pos (5U)
+#define CAN_F0R1_FB5_Msk (0x1U << CAN_F0R1_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F0R1_FB5 CAN_F0R1_FB5_Msk /*!< Filter bit 5 */
+#define CAN_F0R1_FB6_Pos (6U)
+#define CAN_F0R1_FB6_Msk (0x1U << CAN_F0R1_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F0R1_FB6 CAN_F0R1_FB6_Msk /*!< Filter bit 6 */
+#define CAN_F0R1_FB7_Pos (7U)
+#define CAN_F0R1_FB7_Msk (0x1U << CAN_F0R1_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F0R1_FB7 CAN_F0R1_FB7_Msk /*!< Filter bit 7 */
+#define CAN_F0R1_FB8_Pos (8U)
+#define CAN_F0R1_FB8_Msk (0x1U << CAN_F0R1_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F0R1_FB8 CAN_F0R1_FB8_Msk /*!< Filter bit 8 */
+#define CAN_F0R1_FB9_Pos (9U)
+#define CAN_F0R1_FB9_Msk (0x1U << CAN_F0R1_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F0R1_FB9 CAN_F0R1_FB9_Msk /*!< Filter bit 9 */
+#define CAN_F0R1_FB10_Pos (10U)
+#define CAN_F0R1_FB10_Msk (0x1U << CAN_F0R1_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F0R1_FB10 CAN_F0R1_FB10_Msk /*!< Filter bit 10 */
+#define CAN_F0R1_FB11_Pos (11U)
+#define CAN_F0R1_FB11_Msk (0x1U << CAN_F0R1_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F0R1_FB11 CAN_F0R1_FB11_Msk /*!< Filter bit 11 */
+#define CAN_F0R1_FB12_Pos (12U)
+#define CAN_F0R1_FB12_Msk (0x1U << CAN_F0R1_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F0R1_FB12 CAN_F0R1_FB12_Msk /*!< Filter bit 12 */
+#define CAN_F0R1_FB13_Pos (13U)
+#define CAN_F0R1_FB13_Msk (0x1U << CAN_F0R1_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F0R1_FB13 CAN_F0R1_FB13_Msk /*!< Filter bit 13 */
+#define CAN_F0R1_FB14_Pos (14U)
+#define CAN_F0R1_FB14_Msk (0x1U << CAN_F0R1_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F0R1_FB14 CAN_F0R1_FB14_Msk /*!< Filter bit 14 */
+#define CAN_F0R1_FB15_Pos (15U)
+#define CAN_F0R1_FB15_Msk (0x1U << CAN_F0R1_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F0R1_FB15 CAN_F0R1_FB15_Msk /*!< Filter bit 15 */
+#define CAN_F0R1_FB16_Pos (16U)
+#define CAN_F0R1_FB16_Msk (0x1U << CAN_F0R1_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F0R1_FB16 CAN_F0R1_FB16_Msk /*!< Filter bit 16 */
+#define CAN_F0R1_FB17_Pos (17U)
+#define CAN_F0R1_FB17_Msk (0x1U << CAN_F0R1_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F0R1_FB17 CAN_F0R1_FB17_Msk /*!< Filter bit 17 */
+#define CAN_F0R1_FB18_Pos (18U)
+#define CAN_F0R1_FB18_Msk (0x1U << CAN_F0R1_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F0R1_FB18 CAN_F0R1_FB18_Msk /*!< Filter bit 18 */
+#define CAN_F0R1_FB19_Pos (19U)
+#define CAN_F0R1_FB19_Msk (0x1U << CAN_F0R1_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F0R1_FB19 CAN_F0R1_FB19_Msk /*!< Filter bit 19 */
+#define CAN_F0R1_FB20_Pos (20U)
+#define CAN_F0R1_FB20_Msk (0x1U << CAN_F0R1_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F0R1_FB20 CAN_F0R1_FB20_Msk /*!< Filter bit 20 */
+#define CAN_F0R1_FB21_Pos (21U)
+#define CAN_F0R1_FB21_Msk (0x1U << CAN_F0R1_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F0R1_FB21 CAN_F0R1_FB21_Msk /*!< Filter bit 21 */
+#define CAN_F0R1_FB22_Pos (22U)
+#define CAN_F0R1_FB22_Msk (0x1U << CAN_F0R1_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F0R1_FB22 CAN_F0R1_FB22_Msk /*!< Filter bit 22 */
+#define CAN_F0R1_FB23_Pos (23U)
+#define CAN_F0R1_FB23_Msk (0x1U << CAN_F0R1_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F0R1_FB23 CAN_F0R1_FB23_Msk /*!< Filter bit 23 */
+#define CAN_F0R1_FB24_Pos (24U)
+#define CAN_F0R1_FB24_Msk (0x1U << CAN_F0R1_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F0R1_FB24 CAN_F0R1_FB24_Msk /*!< Filter bit 24 */
+#define CAN_F0R1_FB25_Pos (25U)
+#define CAN_F0R1_FB25_Msk (0x1U << CAN_F0R1_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F0R1_FB25 CAN_F0R1_FB25_Msk /*!< Filter bit 25 */
+#define CAN_F0R1_FB26_Pos (26U)
+#define CAN_F0R1_FB26_Msk (0x1U << CAN_F0R1_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F0R1_FB26 CAN_F0R1_FB26_Msk /*!< Filter bit 26 */
+#define CAN_F0R1_FB27_Pos (27U)
+#define CAN_F0R1_FB27_Msk (0x1U << CAN_F0R1_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F0R1_FB27 CAN_F0R1_FB27_Msk /*!< Filter bit 27 */
+#define CAN_F0R1_FB28_Pos (28U)
+#define CAN_F0R1_FB28_Msk (0x1U << CAN_F0R1_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F0R1_FB28 CAN_F0R1_FB28_Msk /*!< Filter bit 28 */
+#define CAN_F0R1_FB29_Pos (29U)
+#define CAN_F0R1_FB29_Msk (0x1U << CAN_F0R1_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F0R1_FB29 CAN_F0R1_FB29_Msk /*!< Filter bit 29 */
+#define CAN_F0R1_FB30_Pos (30U)
+#define CAN_F0R1_FB30_Msk (0x1U << CAN_F0R1_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F0R1_FB30 CAN_F0R1_FB30_Msk /*!< Filter bit 30 */
+#define CAN_F0R1_FB31_Pos (31U)
+#define CAN_F0R1_FB31_Msk (0x1U << CAN_F0R1_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F0R1_FB31 CAN_F0R1_FB31_Msk /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F1R1 register *******************/
+#define CAN_F1R1_FB0_Pos (0U)
+#define CAN_F1R1_FB0_Msk (0x1U << CAN_F1R1_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F1R1_FB0 CAN_F1R1_FB0_Msk /*!< Filter bit 0 */
+#define CAN_F1R1_FB1_Pos (1U)
+#define CAN_F1R1_FB1_Msk (0x1U << CAN_F1R1_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F1R1_FB1 CAN_F1R1_FB1_Msk /*!< Filter bit 1 */
+#define CAN_F1R1_FB2_Pos (2U)
+#define CAN_F1R1_FB2_Msk (0x1U << CAN_F1R1_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F1R1_FB2 CAN_F1R1_FB2_Msk /*!< Filter bit 2 */
+#define CAN_F1R1_FB3_Pos (3U)
+#define CAN_F1R1_FB3_Msk (0x1U << CAN_F1R1_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F1R1_FB3 CAN_F1R1_FB3_Msk /*!< Filter bit 3 */
+#define CAN_F1R1_FB4_Pos (4U)
+#define CAN_F1R1_FB4_Msk (0x1U << CAN_F1R1_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F1R1_FB4 CAN_F1R1_FB4_Msk /*!< Filter bit 4 */
+#define CAN_F1R1_FB5_Pos (5U)
+#define CAN_F1R1_FB5_Msk (0x1U << CAN_F1R1_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F1R1_FB5 CAN_F1R1_FB5_Msk /*!< Filter bit 5 */
+#define CAN_F1R1_FB6_Pos (6U)
+#define CAN_F1R1_FB6_Msk (0x1U << CAN_F1R1_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F1R1_FB6 CAN_F1R1_FB6_Msk /*!< Filter bit 6 */
+#define CAN_F1R1_FB7_Pos (7U)
+#define CAN_F1R1_FB7_Msk (0x1U << CAN_F1R1_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F1R1_FB7 CAN_F1R1_FB7_Msk /*!< Filter bit 7 */
+#define CAN_F1R1_FB8_Pos (8U)
+#define CAN_F1R1_FB8_Msk (0x1U << CAN_F1R1_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F1R1_FB8 CAN_F1R1_FB8_Msk /*!< Filter bit 8 */
+#define CAN_F1R1_FB9_Pos (9U)
+#define CAN_F1R1_FB9_Msk (0x1U << CAN_F1R1_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F1R1_FB9 CAN_F1R1_FB9_Msk /*!< Filter bit 9 */
+#define CAN_F1R1_FB10_Pos (10U)
+#define CAN_F1R1_FB10_Msk (0x1U << CAN_F1R1_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F1R1_FB10 CAN_F1R1_FB10_Msk /*!< Filter bit 10 */
+#define CAN_F1R1_FB11_Pos (11U)
+#define CAN_F1R1_FB11_Msk (0x1U << CAN_F1R1_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F1R1_FB11 CAN_F1R1_FB11_Msk /*!< Filter bit 11 */
+#define CAN_F1R1_FB12_Pos (12U)
+#define CAN_F1R1_FB12_Msk (0x1U << CAN_F1R1_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F1R1_FB12 CAN_F1R1_FB12_Msk /*!< Filter bit 12 */
+#define CAN_F1R1_FB13_Pos (13U)
+#define CAN_F1R1_FB13_Msk (0x1U << CAN_F1R1_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F1R1_FB13 CAN_F1R1_FB13_Msk /*!< Filter bit 13 */
+#define CAN_F1R1_FB14_Pos (14U)
+#define CAN_F1R1_FB14_Msk (0x1U << CAN_F1R1_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F1R1_FB14 CAN_F1R1_FB14_Msk /*!< Filter bit 14 */
+#define CAN_F1R1_FB15_Pos (15U)
+#define CAN_F1R1_FB15_Msk (0x1U << CAN_F1R1_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F1R1_FB15 CAN_F1R1_FB15_Msk /*!< Filter bit 15 */
+#define CAN_F1R1_FB16_Pos (16U)
+#define CAN_F1R1_FB16_Msk (0x1U << CAN_F1R1_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F1R1_FB16 CAN_F1R1_FB16_Msk /*!< Filter bit 16 */
+#define CAN_F1R1_FB17_Pos (17U)
+#define CAN_F1R1_FB17_Msk (0x1U << CAN_F1R1_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F1R1_FB17 CAN_F1R1_FB17_Msk /*!< Filter bit 17 */
+#define CAN_F1R1_FB18_Pos (18U)
+#define CAN_F1R1_FB18_Msk (0x1U << CAN_F1R1_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F1R1_FB18 CAN_F1R1_FB18_Msk /*!< Filter bit 18 */
+#define CAN_F1R1_FB19_Pos (19U)
+#define CAN_F1R1_FB19_Msk (0x1U << CAN_F1R1_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F1R1_FB19 CAN_F1R1_FB19_Msk /*!< Filter bit 19 */
+#define CAN_F1R1_FB20_Pos (20U)
+#define CAN_F1R1_FB20_Msk (0x1U << CAN_F1R1_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F1R1_FB20 CAN_F1R1_FB20_Msk /*!< Filter bit 20 */
+#define CAN_F1R1_FB21_Pos (21U)
+#define CAN_F1R1_FB21_Msk (0x1U << CAN_F1R1_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F1R1_FB21 CAN_F1R1_FB21_Msk /*!< Filter bit 21 */
+#define CAN_F1R1_FB22_Pos (22U)
+#define CAN_F1R1_FB22_Msk (0x1U << CAN_F1R1_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F1R1_FB22 CAN_F1R1_FB22_Msk /*!< Filter bit 22 */
+#define CAN_F1R1_FB23_Pos (23U)
+#define CAN_F1R1_FB23_Msk (0x1U << CAN_F1R1_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F1R1_FB23 CAN_F1R1_FB23_Msk /*!< Filter bit 23 */
+#define CAN_F1R1_FB24_Pos (24U)
+#define CAN_F1R1_FB24_Msk (0x1U << CAN_F1R1_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F1R1_FB24 CAN_F1R1_FB24_Msk /*!< Filter bit 24 */
+#define CAN_F1R1_FB25_Pos (25U)
+#define CAN_F1R1_FB25_Msk (0x1U << CAN_F1R1_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F1R1_FB25 CAN_F1R1_FB25_Msk /*!< Filter bit 25 */
+#define CAN_F1R1_FB26_Pos (26U)
+#define CAN_F1R1_FB26_Msk (0x1U << CAN_F1R1_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F1R1_FB26 CAN_F1R1_FB26_Msk /*!< Filter bit 26 */
+#define CAN_F1R1_FB27_Pos (27U)
+#define CAN_F1R1_FB27_Msk (0x1U << CAN_F1R1_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F1R1_FB27 CAN_F1R1_FB27_Msk /*!< Filter bit 27 */
+#define CAN_F1R1_FB28_Pos (28U)
+#define CAN_F1R1_FB28_Msk (0x1U << CAN_F1R1_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F1R1_FB28 CAN_F1R1_FB28_Msk /*!< Filter bit 28 */
+#define CAN_F1R1_FB29_Pos (29U)
+#define CAN_F1R1_FB29_Msk (0x1U << CAN_F1R1_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F1R1_FB29 CAN_F1R1_FB29_Msk /*!< Filter bit 29 */
+#define CAN_F1R1_FB30_Pos (30U)
+#define CAN_F1R1_FB30_Msk (0x1U << CAN_F1R1_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F1R1_FB30 CAN_F1R1_FB30_Msk /*!< Filter bit 30 */
+#define CAN_F1R1_FB31_Pos (31U)
+#define CAN_F1R1_FB31_Msk (0x1U << CAN_F1R1_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F1R1_FB31 CAN_F1R1_FB31_Msk /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F2R1 register *******************/
+#define CAN_F2R1_FB0_Pos (0U)
+#define CAN_F2R1_FB0_Msk (0x1U << CAN_F2R1_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F2R1_FB0 CAN_F2R1_FB0_Msk /*!< Filter bit 0 */
+#define CAN_F2R1_FB1_Pos (1U)
+#define CAN_F2R1_FB1_Msk (0x1U << CAN_F2R1_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F2R1_FB1 CAN_F2R1_FB1_Msk /*!< Filter bit 1 */
+#define CAN_F2R1_FB2_Pos (2U)
+#define CAN_F2R1_FB2_Msk (0x1U << CAN_F2R1_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F2R1_FB2 CAN_F2R1_FB2_Msk /*!< Filter bit 2 */
+#define CAN_F2R1_FB3_Pos (3U)
+#define CAN_F2R1_FB3_Msk (0x1U << CAN_F2R1_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F2R1_FB3 CAN_F2R1_FB3_Msk /*!< Filter bit 3 */
+#define CAN_F2R1_FB4_Pos (4U)
+#define CAN_F2R1_FB4_Msk (0x1U << CAN_F2R1_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F2R1_FB4 CAN_F2R1_FB4_Msk /*!< Filter bit 4 */
+#define CAN_F2R1_FB5_Pos (5U)
+#define CAN_F2R1_FB5_Msk (0x1U << CAN_F2R1_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F2R1_FB5 CAN_F2R1_FB5_Msk /*!< Filter bit 5 */
+#define CAN_F2R1_FB6_Pos (6U)
+#define CAN_F2R1_FB6_Msk (0x1U << CAN_F2R1_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F2R1_FB6 CAN_F2R1_FB6_Msk /*!< Filter bit 6 */
+#define CAN_F2R1_FB7_Pos (7U)
+#define CAN_F2R1_FB7_Msk (0x1U << CAN_F2R1_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F2R1_FB7 CAN_F2R1_FB7_Msk /*!< Filter bit 7 */
+#define CAN_F2R1_FB8_Pos (8U)
+#define CAN_F2R1_FB8_Msk (0x1U << CAN_F2R1_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F2R1_FB8 CAN_F2R1_FB8_Msk /*!< Filter bit 8 */
+#define CAN_F2R1_FB9_Pos (9U)
+#define CAN_F2R1_FB9_Msk (0x1U << CAN_F2R1_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F2R1_FB9 CAN_F2R1_FB9_Msk /*!< Filter bit 9 */
+#define CAN_F2R1_FB10_Pos (10U)
+#define CAN_F2R1_FB10_Msk (0x1U << CAN_F2R1_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F2R1_FB10 CAN_F2R1_FB10_Msk /*!< Filter bit 10 */
+#define CAN_F2R1_FB11_Pos (11U)
+#define CAN_F2R1_FB11_Msk (0x1U << CAN_F2R1_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F2R1_FB11 CAN_F2R1_FB11_Msk /*!< Filter bit 11 */
+#define CAN_F2R1_FB12_Pos (12U)
+#define CAN_F2R1_FB12_Msk (0x1U << CAN_F2R1_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F2R1_FB12 CAN_F2R1_FB12_Msk /*!< Filter bit 12 */
+#define CAN_F2R1_FB13_Pos (13U)
+#define CAN_F2R1_FB13_Msk (0x1U << CAN_F2R1_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F2R1_FB13 CAN_F2R1_FB13_Msk /*!< Filter bit 13 */
+#define CAN_F2R1_FB14_Pos (14U)
+#define CAN_F2R1_FB14_Msk (0x1U << CAN_F2R1_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F2R1_FB14 CAN_F2R1_FB14_Msk /*!< Filter bit 14 */
+#define CAN_F2R1_FB15_Pos (15U)
+#define CAN_F2R1_FB15_Msk (0x1U << CAN_F2R1_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F2R1_FB15 CAN_F2R1_FB15_Msk /*!< Filter bit 15 */
+#define CAN_F2R1_FB16_Pos (16U)
+#define CAN_F2R1_FB16_Msk (0x1U << CAN_F2R1_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F2R1_FB16 CAN_F2R1_FB16_Msk /*!< Filter bit 16 */
+#define CAN_F2R1_FB17_Pos (17U)
+#define CAN_F2R1_FB17_Msk (0x1U << CAN_F2R1_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F2R1_FB17 CAN_F2R1_FB17_Msk /*!< Filter bit 17 */
+#define CAN_F2R1_FB18_Pos (18U)
+#define CAN_F2R1_FB18_Msk (0x1U << CAN_F2R1_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F2R1_FB18 CAN_F2R1_FB18_Msk /*!< Filter bit 18 */
+#define CAN_F2R1_FB19_Pos (19U)
+#define CAN_F2R1_FB19_Msk (0x1U << CAN_F2R1_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F2R1_FB19 CAN_F2R1_FB19_Msk /*!< Filter bit 19 */
+#define CAN_F2R1_FB20_Pos (20U)
+#define CAN_F2R1_FB20_Msk (0x1U << CAN_F2R1_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F2R1_FB20 CAN_F2R1_FB20_Msk /*!< Filter bit 20 */
+#define CAN_F2R1_FB21_Pos (21U)
+#define CAN_F2R1_FB21_Msk (0x1U << CAN_F2R1_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F2R1_FB21 CAN_F2R1_FB21_Msk /*!< Filter bit 21 */
+#define CAN_F2R1_FB22_Pos (22U)
+#define CAN_F2R1_FB22_Msk (0x1U << CAN_F2R1_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F2R1_FB22 CAN_F2R1_FB22_Msk /*!< Filter bit 22 */
+#define CAN_F2R1_FB23_Pos (23U)
+#define CAN_F2R1_FB23_Msk (0x1U << CAN_F2R1_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F2R1_FB23 CAN_F2R1_FB23_Msk /*!< Filter bit 23 */
+#define CAN_F2R1_FB24_Pos (24U)
+#define CAN_F2R1_FB24_Msk (0x1U << CAN_F2R1_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F2R1_FB24 CAN_F2R1_FB24_Msk /*!< Filter bit 24 */
+#define CAN_F2R1_FB25_Pos (25U)
+#define CAN_F2R1_FB25_Msk (0x1U << CAN_F2R1_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F2R1_FB25 CAN_F2R1_FB25_Msk /*!< Filter bit 25 */
+#define CAN_F2R1_FB26_Pos (26U)
+#define CAN_F2R1_FB26_Msk (0x1U << CAN_F2R1_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F2R1_FB26 CAN_F2R1_FB26_Msk /*!< Filter bit 26 */
+#define CAN_F2R1_FB27_Pos (27U)
+#define CAN_F2R1_FB27_Msk (0x1U << CAN_F2R1_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F2R1_FB27 CAN_F2R1_FB27_Msk /*!< Filter bit 27 */
+#define CAN_F2R1_FB28_Pos (28U)
+#define CAN_F2R1_FB28_Msk (0x1U << CAN_F2R1_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F2R1_FB28 CAN_F2R1_FB28_Msk /*!< Filter bit 28 */
+#define CAN_F2R1_FB29_Pos (29U)
+#define CAN_F2R1_FB29_Msk (0x1U << CAN_F2R1_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F2R1_FB29 CAN_F2R1_FB29_Msk /*!< Filter bit 29 */
+#define CAN_F2R1_FB30_Pos (30U)
+#define CAN_F2R1_FB30_Msk (0x1U << CAN_F2R1_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F2R1_FB30 CAN_F2R1_FB30_Msk /*!< Filter bit 30 */
+#define CAN_F2R1_FB31_Pos (31U)
+#define CAN_F2R1_FB31_Msk (0x1U << CAN_F2R1_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F2R1_FB31 CAN_F2R1_FB31_Msk /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F3R1 register *******************/
+#define CAN_F3R1_FB0_Pos (0U)
+#define CAN_F3R1_FB0_Msk (0x1U << CAN_F3R1_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F3R1_FB0 CAN_F3R1_FB0_Msk /*!< Filter bit 0 */
+#define CAN_F3R1_FB1_Pos (1U)
+#define CAN_F3R1_FB1_Msk (0x1U << CAN_F3R1_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F3R1_FB1 CAN_F3R1_FB1_Msk /*!< Filter bit 1 */
+#define CAN_F3R1_FB2_Pos (2U)
+#define CAN_F3R1_FB2_Msk (0x1U << CAN_F3R1_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F3R1_FB2 CAN_F3R1_FB2_Msk /*!< Filter bit 2 */
+#define CAN_F3R1_FB3_Pos (3U)
+#define CAN_F3R1_FB3_Msk (0x1U << CAN_F3R1_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F3R1_FB3 CAN_F3R1_FB3_Msk /*!< Filter bit 3 */
+#define CAN_F3R1_FB4_Pos (4U)
+#define CAN_F3R1_FB4_Msk (0x1U << CAN_F3R1_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F3R1_FB4 CAN_F3R1_FB4_Msk /*!< Filter bit 4 */
+#define CAN_F3R1_FB5_Pos (5U)
+#define CAN_F3R1_FB5_Msk (0x1U << CAN_F3R1_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F3R1_FB5 CAN_F3R1_FB5_Msk /*!< Filter bit 5 */
+#define CAN_F3R1_FB6_Pos (6U)
+#define CAN_F3R1_FB6_Msk (0x1U << CAN_F3R1_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F3R1_FB6 CAN_F3R1_FB6_Msk /*!< Filter bit 6 */
+#define CAN_F3R1_FB7_Pos (7U)
+#define CAN_F3R1_FB7_Msk (0x1U << CAN_F3R1_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F3R1_FB7 CAN_F3R1_FB7_Msk /*!< Filter bit 7 */
+#define CAN_F3R1_FB8_Pos (8U)
+#define CAN_F3R1_FB8_Msk (0x1U << CAN_F3R1_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F3R1_FB8 CAN_F3R1_FB8_Msk /*!< Filter bit 8 */
+#define CAN_F3R1_FB9_Pos (9U)
+#define CAN_F3R1_FB9_Msk (0x1U << CAN_F3R1_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F3R1_FB9 CAN_F3R1_FB9_Msk /*!< Filter bit 9 */
+#define CAN_F3R1_FB10_Pos (10U)
+#define CAN_F3R1_FB10_Msk (0x1U << CAN_F3R1_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F3R1_FB10 CAN_F3R1_FB10_Msk /*!< Filter bit 10 */
+#define CAN_F3R1_FB11_Pos (11U)
+#define CAN_F3R1_FB11_Msk (0x1U << CAN_F3R1_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F3R1_FB11 CAN_F3R1_FB11_Msk /*!< Filter bit 11 */
+#define CAN_F3R1_FB12_Pos (12U)
+#define CAN_F3R1_FB12_Msk (0x1U << CAN_F3R1_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F3R1_FB12 CAN_F3R1_FB12_Msk /*!< Filter bit 12 */
+#define CAN_F3R1_FB13_Pos (13U)
+#define CAN_F3R1_FB13_Msk (0x1U << CAN_F3R1_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F3R1_FB13 CAN_F3R1_FB13_Msk /*!< Filter bit 13 */
+#define CAN_F3R1_FB14_Pos (14U)
+#define CAN_F3R1_FB14_Msk (0x1U << CAN_F3R1_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F3R1_FB14 CAN_F3R1_FB14_Msk /*!< Filter bit 14 */
+#define CAN_F3R1_FB15_Pos (15U)
+#define CAN_F3R1_FB15_Msk (0x1U << CAN_F3R1_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F3R1_FB15 CAN_F3R1_FB15_Msk /*!< Filter bit 15 */
+#define CAN_F3R1_FB16_Pos (16U)
+#define CAN_F3R1_FB16_Msk (0x1U << CAN_F3R1_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F3R1_FB16 CAN_F3R1_FB16_Msk /*!< Filter bit 16 */
+#define CAN_F3R1_FB17_Pos (17U)
+#define CAN_F3R1_FB17_Msk (0x1U << CAN_F3R1_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F3R1_FB17 CAN_F3R1_FB17_Msk /*!< Filter bit 17 */
+#define CAN_F3R1_FB18_Pos (18U)
+#define CAN_F3R1_FB18_Msk (0x1U << CAN_F3R1_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F3R1_FB18 CAN_F3R1_FB18_Msk /*!< Filter bit 18 */
+#define CAN_F3R1_FB19_Pos (19U)
+#define CAN_F3R1_FB19_Msk (0x1U << CAN_F3R1_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F3R1_FB19 CAN_F3R1_FB19_Msk /*!< Filter bit 19 */
+#define CAN_F3R1_FB20_Pos (20U)
+#define CAN_F3R1_FB20_Msk (0x1U << CAN_F3R1_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F3R1_FB20 CAN_F3R1_FB20_Msk /*!< Filter bit 20 */
+#define CAN_F3R1_FB21_Pos (21U)
+#define CAN_F3R1_FB21_Msk (0x1U << CAN_F3R1_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F3R1_FB21 CAN_F3R1_FB21_Msk /*!< Filter bit 21 */
+#define CAN_F3R1_FB22_Pos (22U)
+#define CAN_F3R1_FB22_Msk (0x1U << CAN_F3R1_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F3R1_FB22 CAN_F3R1_FB22_Msk /*!< Filter bit 22 */
+#define CAN_F3R1_FB23_Pos (23U)
+#define CAN_F3R1_FB23_Msk (0x1U << CAN_F3R1_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F3R1_FB23 CAN_F3R1_FB23_Msk /*!< Filter bit 23 */
+#define CAN_F3R1_FB24_Pos (24U)
+#define CAN_F3R1_FB24_Msk (0x1U << CAN_F3R1_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F3R1_FB24 CAN_F3R1_FB24_Msk /*!< Filter bit 24 */
+#define CAN_F3R1_FB25_Pos (25U)
+#define CAN_F3R1_FB25_Msk (0x1U << CAN_F3R1_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F3R1_FB25 CAN_F3R1_FB25_Msk /*!< Filter bit 25 */
+#define CAN_F3R1_FB26_Pos (26U)
+#define CAN_F3R1_FB26_Msk (0x1U << CAN_F3R1_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F3R1_FB26 CAN_F3R1_FB26_Msk /*!< Filter bit 26 */
+#define CAN_F3R1_FB27_Pos (27U)
+#define CAN_F3R1_FB27_Msk (0x1U << CAN_F3R1_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F3R1_FB27 CAN_F3R1_FB27_Msk /*!< Filter bit 27 */
+#define CAN_F3R1_FB28_Pos (28U)
+#define CAN_F3R1_FB28_Msk (0x1U << CAN_F3R1_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F3R1_FB28 CAN_F3R1_FB28_Msk /*!< Filter bit 28 */
+#define CAN_F3R1_FB29_Pos (29U)
+#define CAN_F3R1_FB29_Msk (0x1U << CAN_F3R1_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F3R1_FB29 CAN_F3R1_FB29_Msk /*!< Filter bit 29 */
+#define CAN_F3R1_FB30_Pos (30U)
+#define CAN_F3R1_FB30_Msk (0x1U << CAN_F3R1_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F3R1_FB30 CAN_F3R1_FB30_Msk /*!< Filter bit 30 */
+#define CAN_F3R1_FB31_Pos (31U)
+#define CAN_F3R1_FB31_Msk (0x1U << CAN_F3R1_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F3R1_FB31 CAN_F3R1_FB31_Msk /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F4R1 register *******************/
+#define CAN_F4R1_FB0_Pos (0U)
+#define CAN_F4R1_FB0_Msk (0x1U << CAN_F4R1_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F4R1_FB0 CAN_F4R1_FB0_Msk /*!< Filter bit 0 */
+#define CAN_F4R1_FB1_Pos (1U)
+#define CAN_F4R1_FB1_Msk (0x1U << CAN_F4R1_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F4R1_FB1 CAN_F4R1_FB1_Msk /*!< Filter bit 1 */
+#define CAN_F4R1_FB2_Pos (2U)
+#define CAN_F4R1_FB2_Msk (0x1U << CAN_F4R1_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F4R1_FB2 CAN_F4R1_FB2_Msk /*!< Filter bit 2 */
+#define CAN_F4R1_FB3_Pos (3U)
+#define CAN_F4R1_FB3_Msk (0x1U << CAN_F4R1_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F4R1_FB3 CAN_F4R1_FB3_Msk /*!< Filter bit 3 */
+#define CAN_F4R1_FB4_Pos (4U)
+#define CAN_F4R1_FB4_Msk (0x1U << CAN_F4R1_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F4R1_FB4 CAN_F4R1_FB4_Msk /*!< Filter bit 4 */
+#define CAN_F4R1_FB5_Pos (5U)
+#define CAN_F4R1_FB5_Msk (0x1U << CAN_F4R1_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F4R1_FB5 CAN_F4R1_FB5_Msk /*!< Filter bit 5 */
+#define CAN_F4R1_FB6_Pos (6U)
+#define CAN_F4R1_FB6_Msk (0x1U << CAN_F4R1_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F4R1_FB6 CAN_F4R1_FB6_Msk /*!< Filter bit 6 */
+#define CAN_F4R1_FB7_Pos (7U)
+#define CAN_F4R1_FB7_Msk (0x1U << CAN_F4R1_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F4R1_FB7 CAN_F4R1_FB7_Msk /*!< Filter bit 7 */
+#define CAN_F4R1_FB8_Pos (8U)
+#define CAN_F4R1_FB8_Msk (0x1U << CAN_F4R1_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F4R1_FB8 CAN_F4R1_FB8_Msk /*!< Filter bit 8 */
+#define CAN_F4R1_FB9_Pos (9U)
+#define CAN_F4R1_FB9_Msk (0x1U << CAN_F4R1_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F4R1_FB9 CAN_F4R1_FB9_Msk /*!< Filter bit 9 */
+#define CAN_F4R1_FB10_Pos (10U)
+#define CAN_F4R1_FB10_Msk (0x1U << CAN_F4R1_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F4R1_FB10 CAN_F4R1_FB10_Msk /*!< Filter bit 10 */
+#define CAN_F4R1_FB11_Pos (11U)
+#define CAN_F4R1_FB11_Msk (0x1U << CAN_F4R1_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F4R1_FB11 CAN_F4R1_FB11_Msk /*!< Filter bit 11 */
+#define CAN_F4R1_FB12_Pos (12U)
+#define CAN_F4R1_FB12_Msk (0x1U << CAN_F4R1_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F4R1_FB12 CAN_F4R1_FB12_Msk /*!< Filter bit 12 */
+#define CAN_F4R1_FB13_Pos (13U)
+#define CAN_F4R1_FB13_Msk (0x1U << CAN_F4R1_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F4R1_FB13 CAN_F4R1_FB13_Msk /*!< Filter bit 13 */
+#define CAN_F4R1_FB14_Pos (14U)
+#define CAN_F4R1_FB14_Msk (0x1U << CAN_F4R1_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F4R1_FB14 CAN_F4R1_FB14_Msk /*!< Filter bit 14 */
+#define CAN_F4R1_FB15_Pos (15U)
+#define CAN_F4R1_FB15_Msk (0x1U << CAN_F4R1_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F4R1_FB15 CAN_F4R1_FB15_Msk /*!< Filter bit 15 */
+#define CAN_F4R1_FB16_Pos (16U)
+#define CAN_F4R1_FB16_Msk (0x1U << CAN_F4R1_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F4R1_FB16 CAN_F4R1_FB16_Msk /*!< Filter bit 16 */
+#define CAN_F4R1_FB17_Pos (17U)
+#define CAN_F4R1_FB17_Msk (0x1U << CAN_F4R1_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F4R1_FB17 CAN_F4R1_FB17_Msk /*!< Filter bit 17 */
+#define CAN_F4R1_FB18_Pos (18U)
+#define CAN_F4R1_FB18_Msk (0x1U << CAN_F4R1_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F4R1_FB18 CAN_F4R1_FB18_Msk /*!< Filter bit 18 */
+#define CAN_F4R1_FB19_Pos (19U)
+#define CAN_F4R1_FB19_Msk (0x1U << CAN_F4R1_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F4R1_FB19 CAN_F4R1_FB19_Msk /*!< Filter bit 19 */
+#define CAN_F4R1_FB20_Pos (20U)
+#define CAN_F4R1_FB20_Msk (0x1U << CAN_F4R1_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F4R1_FB20 CAN_F4R1_FB20_Msk /*!< Filter bit 20 */
+#define CAN_F4R1_FB21_Pos (21U)
+#define CAN_F4R1_FB21_Msk (0x1U << CAN_F4R1_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F4R1_FB21 CAN_F4R1_FB21_Msk /*!< Filter bit 21 */
+#define CAN_F4R1_FB22_Pos (22U)
+#define CAN_F4R1_FB22_Msk (0x1U << CAN_F4R1_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F4R1_FB22 CAN_F4R1_FB22_Msk /*!< Filter bit 22 */
+#define CAN_F4R1_FB23_Pos (23U)
+#define CAN_F4R1_FB23_Msk (0x1U << CAN_F4R1_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F4R1_FB23 CAN_F4R1_FB23_Msk /*!< Filter bit 23 */
+#define CAN_F4R1_FB24_Pos (24U)
+#define CAN_F4R1_FB24_Msk (0x1U << CAN_F4R1_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F4R1_FB24 CAN_F4R1_FB24_Msk /*!< Filter bit 24 */
+#define CAN_F4R1_FB25_Pos (25U)
+#define CAN_F4R1_FB25_Msk (0x1U << CAN_F4R1_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F4R1_FB25 CAN_F4R1_FB25_Msk /*!< Filter bit 25 */
+#define CAN_F4R1_FB26_Pos (26U)
+#define CAN_F4R1_FB26_Msk (0x1U << CAN_F4R1_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F4R1_FB26 CAN_F4R1_FB26_Msk /*!< Filter bit 26 */
+#define CAN_F4R1_FB27_Pos (27U)
+#define CAN_F4R1_FB27_Msk (0x1U << CAN_F4R1_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F4R1_FB27 CAN_F4R1_FB27_Msk /*!< Filter bit 27 */
+#define CAN_F4R1_FB28_Pos (28U)
+#define CAN_F4R1_FB28_Msk (0x1U << CAN_F4R1_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F4R1_FB28 CAN_F4R1_FB28_Msk /*!< Filter bit 28 */
+#define CAN_F4R1_FB29_Pos (29U)
+#define CAN_F4R1_FB29_Msk (0x1U << CAN_F4R1_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F4R1_FB29 CAN_F4R1_FB29_Msk /*!< Filter bit 29 */
+#define CAN_F4R1_FB30_Pos (30U)
+#define CAN_F4R1_FB30_Msk (0x1U << CAN_F4R1_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F4R1_FB30 CAN_F4R1_FB30_Msk /*!< Filter bit 30 */
+#define CAN_F4R1_FB31_Pos (31U)
+#define CAN_F4R1_FB31_Msk (0x1U << CAN_F4R1_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F4R1_FB31 CAN_F4R1_FB31_Msk /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F5R1 register *******************/
+#define CAN_F5R1_FB0_Pos (0U)
+#define CAN_F5R1_FB0_Msk (0x1U << CAN_F5R1_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F5R1_FB0 CAN_F5R1_FB0_Msk /*!< Filter bit 0 */
+#define CAN_F5R1_FB1_Pos (1U)
+#define CAN_F5R1_FB1_Msk (0x1U << CAN_F5R1_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F5R1_FB1 CAN_F5R1_FB1_Msk /*!< Filter bit 1 */
+#define CAN_F5R1_FB2_Pos (2U)
+#define CAN_F5R1_FB2_Msk (0x1U << CAN_F5R1_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F5R1_FB2 CAN_F5R1_FB2_Msk /*!< Filter bit 2 */
+#define CAN_F5R1_FB3_Pos (3U)
+#define CAN_F5R1_FB3_Msk (0x1U << CAN_F5R1_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F5R1_FB3 CAN_F5R1_FB3_Msk /*!< Filter bit 3 */
+#define CAN_F5R1_FB4_Pos (4U)
+#define CAN_F5R1_FB4_Msk (0x1U << CAN_F5R1_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F5R1_FB4 CAN_F5R1_FB4_Msk /*!< Filter bit 4 */
+#define CAN_F5R1_FB5_Pos (5U)
+#define CAN_F5R1_FB5_Msk (0x1U << CAN_F5R1_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F5R1_FB5 CAN_F5R1_FB5_Msk /*!< Filter bit 5 */
+#define CAN_F5R1_FB6_Pos (6U)
+#define CAN_F5R1_FB6_Msk (0x1U << CAN_F5R1_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F5R1_FB6 CAN_F5R1_FB6_Msk /*!< Filter bit 6 */
+#define CAN_F5R1_FB7_Pos (7U)
+#define CAN_F5R1_FB7_Msk (0x1U << CAN_F5R1_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F5R1_FB7 CAN_F5R1_FB7_Msk /*!< Filter bit 7 */
+#define CAN_F5R1_FB8_Pos (8U)
+#define CAN_F5R1_FB8_Msk (0x1U << CAN_F5R1_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F5R1_FB8 CAN_F5R1_FB8_Msk /*!< Filter bit 8 */
+#define CAN_F5R1_FB9_Pos (9U)
+#define CAN_F5R1_FB9_Msk (0x1U << CAN_F5R1_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F5R1_FB9 CAN_F5R1_FB9_Msk /*!< Filter bit 9 */
+#define CAN_F5R1_FB10_Pos (10U)
+#define CAN_F5R1_FB10_Msk (0x1U << CAN_F5R1_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F5R1_FB10 CAN_F5R1_FB10_Msk /*!< Filter bit 10 */
+#define CAN_F5R1_FB11_Pos (11U)
+#define CAN_F5R1_FB11_Msk (0x1U << CAN_F5R1_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F5R1_FB11 CAN_F5R1_FB11_Msk /*!< Filter bit 11 */
+#define CAN_F5R1_FB12_Pos (12U)
+#define CAN_F5R1_FB12_Msk (0x1U << CAN_F5R1_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F5R1_FB12 CAN_F5R1_FB12_Msk /*!< Filter bit 12 */
+#define CAN_F5R1_FB13_Pos (13U)
+#define CAN_F5R1_FB13_Msk (0x1U << CAN_F5R1_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F5R1_FB13 CAN_F5R1_FB13_Msk /*!< Filter bit 13 */
+#define CAN_F5R1_FB14_Pos (14U)
+#define CAN_F5R1_FB14_Msk (0x1U << CAN_F5R1_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F5R1_FB14 CAN_F5R1_FB14_Msk /*!< Filter bit 14 */
+#define CAN_F5R1_FB15_Pos (15U)
+#define CAN_F5R1_FB15_Msk (0x1U << CAN_F5R1_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F5R1_FB15 CAN_F5R1_FB15_Msk /*!< Filter bit 15 */
+#define CAN_F5R1_FB16_Pos (16U)
+#define CAN_F5R1_FB16_Msk (0x1U << CAN_F5R1_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F5R1_FB16 CAN_F5R1_FB16_Msk /*!< Filter bit 16 */
+#define CAN_F5R1_FB17_Pos (17U)
+#define CAN_F5R1_FB17_Msk (0x1U << CAN_F5R1_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F5R1_FB17 CAN_F5R1_FB17_Msk /*!< Filter bit 17 */
+#define CAN_F5R1_FB18_Pos (18U)
+#define CAN_F5R1_FB18_Msk (0x1U << CAN_F5R1_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F5R1_FB18 CAN_F5R1_FB18_Msk /*!< Filter bit 18 */
+#define CAN_F5R1_FB19_Pos (19U)
+#define CAN_F5R1_FB19_Msk (0x1U << CAN_F5R1_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F5R1_FB19 CAN_F5R1_FB19_Msk /*!< Filter bit 19 */
+#define CAN_F5R1_FB20_Pos (20U)
+#define CAN_F5R1_FB20_Msk (0x1U << CAN_F5R1_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F5R1_FB20 CAN_F5R1_FB20_Msk /*!< Filter bit 20 */
+#define CAN_F5R1_FB21_Pos (21U)
+#define CAN_F5R1_FB21_Msk (0x1U << CAN_F5R1_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F5R1_FB21 CAN_F5R1_FB21_Msk /*!< Filter bit 21 */
+#define CAN_F5R1_FB22_Pos (22U)
+#define CAN_F5R1_FB22_Msk (0x1U << CAN_F5R1_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F5R1_FB22 CAN_F5R1_FB22_Msk /*!< Filter bit 22 */
+#define CAN_F5R1_FB23_Pos (23U)
+#define CAN_F5R1_FB23_Msk (0x1U << CAN_F5R1_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F5R1_FB23 CAN_F5R1_FB23_Msk /*!< Filter bit 23 */
+#define CAN_F5R1_FB24_Pos (24U)
+#define CAN_F5R1_FB24_Msk (0x1U << CAN_F5R1_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F5R1_FB24 CAN_F5R1_FB24_Msk /*!< Filter bit 24 */
+#define CAN_F5R1_FB25_Pos (25U)
+#define CAN_F5R1_FB25_Msk (0x1U << CAN_F5R1_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F5R1_FB25 CAN_F5R1_FB25_Msk /*!< Filter bit 25 */
+#define CAN_F5R1_FB26_Pos (26U)
+#define CAN_F5R1_FB26_Msk (0x1U << CAN_F5R1_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F5R1_FB26 CAN_F5R1_FB26_Msk /*!< Filter bit 26 */
+#define CAN_F5R1_FB27_Pos (27U)
+#define CAN_F5R1_FB27_Msk (0x1U << CAN_F5R1_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F5R1_FB27 CAN_F5R1_FB27_Msk /*!< Filter bit 27 */
+#define CAN_F5R1_FB28_Pos (28U)
+#define CAN_F5R1_FB28_Msk (0x1U << CAN_F5R1_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F5R1_FB28 CAN_F5R1_FB28_Msk /*!< Filter bit 28 */
+#define CAN_F5R1_FB29_Pos (29U)
+#define CAN_F5R1_FB29_Msk (0x1U << CAN_F5R1_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F5R1_FB29 CAN_F5R1_FB29_Msk /*!< Filter bit 29 */
+#define CAN_F5R1_FB30_Pos (30U)
+#define CAN_F5R1_FB30_Msk (0x1U << CAN_F5R1_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F5R1_FB30 CAN_F5R1_FB30_Msk /*!< Filter bit 30 */
+#define CAN_F5R1_FB31_Pos (31U)
+#define CAN_F5R1_FB31_Msk (0x1U << CAN_F5R1_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F5R1_FB31 CAN_F5R1_FB31_Msk /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F6R1 register *******************/
+#define CAN_F6R1_FB0_Pos (0U)
+#define CAN_F6R1_FB0_Msk (0x1U << CAN_F6R1_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F6R1_FB0 CAN_F6R1_FB0_Msk /*!< Filter bit 0 */
+#define CAN_F6R1_FB1_Pos (1U)
+#define CAN_F6R1_FB1_Msk (0x1U << CAN_F6R1_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F6R1_FB1 CAN_F6R1_FB1_Msk /*!< Filter bit 1 */
+#define CAN_F6R1_FB2_Pos (2U)
+#define CAN_F6R1_FB2_Msk (0x1U << CAN_F6R1_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F6R1_FB2 CAN_F6R1_FB2_Msk /*!< Filter bit 2 */
+#define CAN_F6R1_FB3_Pos (3U)
+#define CAN_F6R1_FB3_Msk (0x1U << CAN_F6R1_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F6R1_FB3 CAN_F6R1_FB3_Msk /*!< Filter bit 3 */
+#define CAN_F6R1_FB4_Pos (4U)
+#define CAN_F6R1_FB4_Msk (0x1U << CAN_F6R1_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F6R1_FB4 CAN_F6R1_FB4_Msk /*!< Filter bit 4 */
+#define CAN_F6R1_FB5_Pos (5U)
+#define CAN_F6R1_FB5_Msk (0x1U << CAN_F6R1_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F6R1_FB5 CAN_F6R1_FB5_Msk /*!< Filter bit 5 */
+#define CAN_F6R1_FB6_Pos (6U)
+#define CAN_F6R1_FB6_Msk (0x1U << CAN_F6R1_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F6R1_FB6 CAN_F6R1_FB6_Msk /*!< Filter bit 6 */
+#define CAN_F6R1_FB7_Pos (7U)
+#define CAN_F6R1_FB7_Msk (0x1U << CAN_F6R1_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F6R1_FB7 CAN_F6R1_FB7_Msk /*!< Filter bit 7 */
+#define CAN_F6R1_FB8_Pos (8U)
+#define CAN_F6R1_FB8_Msk (0x1U << CAN_F6R1_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F6R1_FB8 CAN_F6R1_FB8_Msk /*!< Filter bit 8 */
+#define CAN_F6R1_FB9_Pos (9U)
+#define CAN_F6R1_FB9_Msk (0x1U << CAN_F6R1_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F6R1_FB9 CAN_F6R1_FB9_Msk /*!< Filter bit 9 */
+#define CAN_F6R1_FB10_Pos (10U)
+#define CAN_F6R1_FB10_Msk (0x1U << CAN_F6R1_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F6R1_FB10 CAN_F6R1_FB10_Msk /*!< Filter bit 10 */
+#define CAN_F6R1_FB11_Pos (11U)
+#define CAN_F6R1_FB11_Msk (0x1U << CAN_F6R1_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F6R1_FB11 CAN_F6R1_FB11_Msk /*!< Filter bit 11 */
+#define CAN_F6R1_FB12_Pos (12U)
+#define CAN_F6R1_FB12_Msk (0x1U << CAN_F6R1_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F6R1_FB12 CAN_F6R1_FB12_Msk /*!< Filter bit 12 */
+#define CAN_F6R1_FB13_Pos (13U)
+#define CAN_F6R1_FB13_Msk (0x1U << CAN_F6R1_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F6R1_FB13 CAN_F6R1_FB13_Msk /*!< Filter bit 13 */
+#define CAN_F6R1_FB14_Pos (14U)
+#define CAN_F6R1_FB14_Msk (0x1U << CAN_F6R1_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F6R1_FB14 CAN_F6R1_FB14_Msk /*!< Filter bit 14 */
+#define CAN_F6R1_FB15_Pos (15U)
+#define CAN_F6R1_FB15_Msk (0x1U << CAN_F6R1_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F6R1_FB15 CAN_F6R1_FB15_Msk /*!< Filter bit 15 */
+#define CAN_F6R1_FB16_Pos (16U)
+#define CAN_F6R1_FB16_Msk (0x1U << CAN_F6R1_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F6R1_FB16 CAN_F6R1_FB16_Msk /*!< Filter bit 16 */
+#define CAN_F6R1_FB17_Pos (17U)
+#define CAN_F6R1_FB17_Msk (0x1U << CAN_F6R1_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F6R1_FB17 CAN_F6R1_FB17_Msk /*!< Filter bit 17 */
+#define CAN_F6R1_FB18_Pos (18U)
+#define CAN_F6R1_FB18_Msk (0x1U << CAN_F6R1_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F6R1_FB18 CAN_F6R1_FB18_Msk /*!< Filter bit 18 */
+#define CAN_F6R1_FB19_Pos (19U)
+#define CAN_F6R1_FB19_Msk (0x1U << CAN_F6R1_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F6R1_FB19 CAN_F6R1_FB19_Msk /*!< Filter bit 19 */
+#define CAN_F6R1_FB20_Pos (20U)
+#define CAN_F6R1_FB20_Msk (0x1U << CAN_F6R1_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F6R1_FB20 CAN_F6R1_FB20_Msk /*!< Filter bit 20 */
+#define CAN_F6R1_FB21_Pos (21U)
+#define CAN_F6R1_FB21_Msk (0x1U << CAN_F6R1_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F6R1_FB21 CAN_F6R1_FB21_Msk /*!< Filter bit 21 */
+#define CAN_F6R1_FB22_Pos (22U)
+#define CAN_F6R1_FB22_Msk (0x1U << CAN_F6R1_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F6R1_FB22 CAN_F6R1_FB22_Msk /*!< Filter bit 22 */
+#define CAN_F6R1_FB23_Pos (23U)
+#define CAN_F6R1_FB23_Msk (0x1U << CAN_F6R1_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F6R1_FB23 CAN_F6R1_FB23_Msk /*!< Filter bit 23 */
+#define CAN_F6R1_FB24_Pos (24U)
+#define CAN_F6R1_FB24_Msk (0x1U << CAN_F6R1_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F6R1_FB24 CAN_F6R1_FB24_Msk /*!< Filter bit 24 */
+#define CAN_F6R1_FB25_Pos (25U)
+#define CAN_F6R1_FB25_Msk (0x1U << CAN_F6R1_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F6R1_FB25 CAN_F6R1_FB25_Msk /*!< Filter bit 25 */
+#define CAN_F6R1_FB26_Pos (26U)
+#define CAN_F6R1_FB26_Msk (0x1U << CAN_F6R1_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F6R1_FB26 CAN_F6R1_FB26_Msk /*!< Filter bit 26 */
+#define CAN_F6R1_FB27_Pos (27U)
+#define CAN_F6R1_FB27_Msk (0x1U << CAN_F6R1_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F6R1_FB27 CAN_F6R1_FB27_Msk /*!< Filter bit 27 */
+#define CAN_F6R1_FB28_Pos (28U)
+#define CAN_F6R1_FB28_Msk (0x1U << CAN_F6R1_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F6R1_FB28 CAN_F6R1_FB28_Msk /*!< Filter bit 28 */
+#define CAN_F6R1_FB29_Pos (29U)
+#define CAN_F6R1_FB29_Msk (0x1U << CAN_F6R1_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F6R1_FB29 CAN_F6R1_FB29_Msk /*!< Filter bit 29 */
+#define CAN_F6R1_FB30_Pos (30U)
+#define CAN_F6R1_FB30_Msk (0x1U << CAN_F6R1_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F6R1_FB30 CAN_F6R1_FB30_Msk /*!< Filter bit 30 */
+#define CAN_F6R1_FB31_Pos (31U)
+#define CAN_F6R1_FB31_Msk (0x1U << CAN_F6R1_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F6R1_FB31 CAN_F6R1_FB31_Msk /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F7R1 register *******************/
+#define CAN_F7R1_FB0_Pos (0U)
+#define CAN_F7R1_FB0_Msk (0x1U << CAN_F7R1_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F7R1_FB0 CAN_F7R1_FB0_Msk /*!< Filter bit 0 */
+#define CAN_F7R1_FB1_Pos (1U)
+#define CAN_F7R1_FB1_Msk (0x1U << CAN_F7R1_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F7R1_FB1 CAN_F7R1_FB1_Msk /*!< Filter bit 1 */
+#define CAN_F7R1_FB2_Pos (2U)
+#define CAN_F7R1_FB2_Msk (0x1U << CAN_F7R1_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F7R1_FB2 CAN_F7R1_FB2_Msk /*!< Filter bit 2 */
+#define CAN_F7R1_FB3_Pos (3U)
+#define CAN_F7R1_FB3_Msk (0x1U << CAN_F7R1_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F7R1_FB3 CAN_F7R1_FB3_Msk /*!< Filter bit 3 */
+#define CAN_F7R1_FB4_Pos (4U)
+#define CAN_F7R1_FB4_Msk (0x1U << CAN_F7R1_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F7R1_FB4 CAN_F7R1_FB4_Msk /*!< Filter bit 4 */
+#define CAN_F7R1_FB5_Pos (5U)
+#define CAN_F7R1_FB5_Msk (0x1U << CAN_F7R1_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F7R1_FB5 CAN_F7R1_FB5_Msk /*!< Filter bit 5 */
+#define CAN_F7R1_FB6_Pos (6U)
+#define CAN_F7R1_FB6_Msk (0x1U << CAN_F7R1_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F7R1_FB6 CAN_F7R1_FB6_Msk /*!< Filter bit 6 */
+#define CAN_F7R1_FB7_Pos (7U)
+#define CAN_F7R1_FB7_Msk (0x1U << CAN_F7R1_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F7R1_FB7 CAN_F7R1_FB7_Msk /*!< Filter bit 7 */
+#define CAN_F7R1_FB8_Pos (8U)
+#define CAN_F7R1_FB8_Msk (0x1U << CAN_F7R1_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F7R1_FB8 CAN_F7R1_FB8_Msk /*!< Filter bit 8 */
+#define CAN_F7R1_FB9_Pos (9U)
+#define CAN_F7R1_FB9_Msk (0x1U << CAN_F7R1_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F7R1_FB9 CAN_F7R1_FB9_Msk /*!< Filter bit 9 */
+#define CAN_F7R1_FB10_Pos (10U)
+#define CAN_F7R1_FB10_Msk (0x1U << CAN_F7R1_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F7R1_FB10 CAN_F7R1_FB10_Msk /*!< Filter bit 10 */
+#define CAN_F7R1_FB11_Pos (11U)
+#define CAN_F7R1_FB11_Msk (0x1U << CAN_F7R1_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F7R1_FB11 CAN_F7R1_FB11_Msk /*!< Filter bit 11 */
+#define CAN_F7R1_FB12_Pos (12U)
+#define CAN_F7R1_FB12_Msk (0x1U << CAN_F7R1_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F7R1_FB12 CAN_F7R1_FB12_Msk /*!< Filter bit 12 */
+#define CAN_F7R1_FB13_Pos (13U)
+#define CAN_F7R1_FB13_Msk (0x1U << CAN_F7R1_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F7R1_FB13 CAN_F7R1_FB13_Msk /*!< Filter bit 13 */
+#define CAN_F7R1_FB14_Pos (14U)
+#define CAN_F7R1_FB14_Msk (0x1U << CAN_F7R1_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F7R1_FB14 CAN_F7R1_FB14_Msk /*!< Filter bit 14 */
+#define CAN_F7R1_FB15_Pos (15U)
+#define CAN_F7R1_FB15_Msk (0x1U << CAN_F7R1_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F7R1_FB15 CAN_F7R1_FB15_Msk /*!< Filter bit 15 */
+#define CAN_F7R1_FB16_Pos (16U)
+#define CAN_F7R1_FB16_Msk (0x1U << CAN_F7R1_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F7R1_FB16 CAN_F7R1_FB16_Msk /*!< Filter bit 16 */
+#define CAN_F7R1_FB17_Pos (17U)
+#define CAN_F7R1_FB17_Msk (0x1U << CAN_F7R1_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F7R1_FB17 CAN_F7R1_FB17_Msk /*!< Filter bit 17 */
+#define CAN_F7R1_FB18_Pos (18U)
+#define CAN_F7R1_FB18_Msk (0x1U << CAN_F7R1_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F7R1_FB18 CAN_F7R1_FB18_Msk /*!< Filter bit 18 */
+#define CAN_F7R1_FB19_Pos (19U)
+#define CAN_F7R1_FB19_Msk (0x1U << CAN_F7R1_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F7R1_FB19 CAN_F7R1_FB19_Msk /*!< Filter bit 19 */
+#define CAN_F7R1_FB20_Pos (20U)
+#define CAN_F7R1_FB20_Msk (0x1U << CAN_F7R1_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F7R1_FB20 CAN_F7R1_FB20_Msk /*!< Filter bit 20 */
+#define CAN_F7R1_FB21_Pos (21U)
+#define CAN_F7R1_FB21_Msk (0x1U << CAN_F7R1_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F7R1_FB21 CAN_F7R1_FB21_Msk /*!< Filter bit 21 */
+#define CAN_F7R1_FB22_Pos (22U)
+#define CAN_F7R1_FB22_Msk (0x1U << CAN_F7R1_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F7R1_FB22 CAN_F7R1_FB22_Msk /*!< Filter bit 22 */
+#define CAN_F7R1_FB23_Pos (23U)
+#define CAN_F7R1_FB23_Msk (0x1U << CAN_F7R1_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F7R1_FB23 CAN_F7R1_FB23_Msk /*!< Filter bit 23 */
+#define CAN_F7R1_FB24_Pos (24U)
+#define CAN_F7R1_FB24_Msk (0x1U << CAN_F7R1_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F7R1_FB24 CAN_F7R1_FB24_Msk /*!< Filter bit 24 */
+#define CAN_F7R1_FB25_Pos (25U)
+#define CAN_F7R1_FB25_Msk (0x1U << CAN_F7R1_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F7R1_FB25 CAN_F7R1_FB25_Msk /*!< Filter bit 25 */
+#define CAN_F7R1_FB26_Pos (26U)
+#define CAN_F7R1_FB26_Msk (0x1U << CAN_F7R1_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F7R1_FB26 CAN_F7R1_FB26_Msk /*!< Filter bit 26 */
+#define CAN_F7R1_FB27_Pos (27U)
+#define CAN_F7R1_FB27_Msk (0x1U << CAN_F7R1_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F7R1_FB27 CAN_F7R1_FB27_Msk /*!< Filter bit 27 */
+#define CAN_F7R1_FB28_Pos (28U)
+#define CAN_F7R1_FB28_Msk (0x1U << CAN_F7R1_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F7R1_FB28 CAN_F7R1_FB28_Msk /*!< Filter bit 28 */
+#define CAN_F7R1_FB29_Pos (29U)
+#define CAN_F7R1_FB29_Msk (0x1U << CAN_F7R1_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F7R1_FB29 CAN_F7R1_FB29_Msk /*!< Filter bit 29 */
+#define CAN_F7R1_FB30_Pos (30U)
+#define CAN_F7R1_FB30_Msk (0x1U << CAN_F7R1_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F7R1_FB30 CAN_F7R1_FB30_Msk /*!< Filter bit 30 */
+#define CAN_F7R1_FB31_Pos (31U)
+#define CAN_F7R1_FB31_Msk (0x1U << CAN_F7R1_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F7R1_FB31 CAN_F7R1_FB31_Msk /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F8R1 register *******************/
+#define CAN_F8R1_FB0_Pos (0U)
+#define CAN_F8R1_FB0_Msk (0x1U << CAN_F8R1_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F8R1_FB0 CAN_F8R1_FB0_Msk /*!< Filter bit 0 */
+#define CAN_F8R1_FB1_Pos (1U)
+#define CAN_F8R1_FB1_Msk (0x1U << CAN_F8R1_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F8R1_FB1 CAN_F8R1_FB1_Msk /*!< Filter bit 1 */
+#define CAN_F8R1_FB2_Pos (2U)
+#define CAN_F8R1_FB2_Msk (0x1U << CAN_F8R1_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F8R1_FB2 CAN_F8R1_FB2_Msk /*!< Filter bit 2 */
+#define CAN_F8R1_FB3_Pos (3U)
+#define CAN_F8R1_FB3_Msk (0x1U << CAN_F8R1_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F8R1_FB3 CAN_F8R1_FB3_Msk /*!< Filter bit 3 */
+#define CAN_F8R1_FB4_Pos (4U)
+#define CAN_F8R1_FB4_Msk (0x1U << CAN_F8R1_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F8R1_FB4 CAN_F8R1_FB4_Msk /*!< Filter bit 4 */
+#define CAN_F8R1_FB5_Pos (5U)
+#define CAN_F8R1_FB5_Msk (0x1U << CAN_F8R1_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F8R1_FB5 CAN_F8R1_FB5_Msk /*!< Filter bit 5 */
+#define CAN_F8R1_FB6_Pos (6U)
+#define CAN_F8R1_FB6_Msk (0x1U << CAN_F8R1_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F8R1_FB6 CAN_F8R1_FB6_Msk /*!< Filter bit 6 */
+#define CAN_F8R1_FB7_Pos (7U)
+#define CAN_F8R1_FB7_Msk (0x1U << CAN_F8R1_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F8R1_FB7 CAN_F8R1_FB7_Msk /*!< Filter bit 7 */
+#define CAN_F8R1_FB8_Pos (8U)
+#define CAN_F8R1_FB8_Msk (0x1U << CAN_F8R1_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F8R1_FB8 CAN_F8R1_FB8_Msk /*!< Filter bit 8 */
+#define CAN_F8R1_FB9_Pos (9U)
+#define CAN_F8R1_FB9_Msk (0x1U << CAN_F8R1_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F8R1_FB9 CAN_F8R1_FB9_Msk /*!< Filter bit 9 */
+#define CAN_F8R1_FB10_Pos (10U)
+#define CAN_F8R1_FB10_Msk (0x1U << CAN_F8R1_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F8R1_FB10 CAN_F8R1_FB10_Msk /*!< Filter bit 10 */
+#define CAN_F8R1_FB11_Pos (11U)
+#define CAN_F8R1_FB11_Msk (0x1U << CAN_F8R1_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F8R1_FB11 CAN_F8R1_FB11_Msk /*!< Filter bit 11 */
+#define CAN_F8R1_FB12_Pos (12U)
+#define CAN_F8R1_FB12_Msk (0x1U << CAN_F8R1_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F8R1_FB12 CAN_F8R1_FB12_Msk /*!< Filter bit 12 */
+#define CAN_F8R1_FB13_Pos (13U)
+#define CAN_F8R1_FB13_Msk (0x1U << CAN_F8R1_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F8R1_FB13 CAN_F8R1_FB13_Msk /*!< Filter bit 13 */
+#define CAN_F8R1_FB14_Pos (14U)
+#define CAN_F8R1_FB14_Msk (0x1U << CAN_F8R1_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F8R1_FB14 CAN_F8R1_FB14_Msk /*!< Filter bit 14 */
+#define CAN_F8R1_FB15_Pos (15U)
+#define CAN_F8R1_FB15_Msk (0x1U << CAN_F8R1_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F8R1_FB15 CAN_F8R1_FB15_Msk /*!< Filter bit 15 */
+#define CAN_F8R1_FB16_Pos (16U)
+#define CAN_F8R1_FB16_Msk (0x1U << CAN_F8R1_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F8R1_FB16 CAN_F8R1_FB16_Msk /*!< Filter bit 16 */
+#define CAN_F8R1_FB17_Pos (17U)
+#define CAN_F8R1_FB17_Msk (0x1U << CAN_F8R1_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F8R1_FB17 CAN_F8R1_FB17_Msk /*!< Filter bit 17 */
+#define CAN_F8R1_FB18_Pos (18U)
+#define CAN_F8R1_FB18_Msk (0x1U << CAN_F8R1_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F8R1_FB18 CAN_F8R1_FB18_Msk /*!< Filter bit 18 */
+#define CAN_F8R1_FB19_Pos (19U)
+#define CAN_F8R1_FB19_Msk (0x1U << CAN_F8R1_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F8R1_FB19 CAN_F8R1_FB19_Msk /*!< Filter bit 19 */
+#define CAN_F8R1_FB20_Pos (20U)
+#define CAN_F8R1_FB20_Msk (0x1U << CAN_F8R1_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F8R1_FB20 CAN_F8R1_FB20_Msk /*!< Filter bit 20 */
+#define CAN_F8R1_FB21_Pos (21U)
+#define CAN_F8R1_FB21_Msk (0x1U << CAN_F8R1_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F8R1_FB21 CAN_F8R1_FB21_Msk /*!< Filter bit 21 */
+#define CAN_F8R1_FB22_Pos (22U)
+#define CAN_F8R1_FB22_Msk (0x1U << CAN_F8R1_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F8R1_FB22 CAN_F8R1_FB22_Msk /*!< Filter bit 22 */
+#define CAN_F8R1_FB23_Pos (23U)
+#define CAN_F8R1_FB23_Msk (0x1U << CAN_F8R1_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F8R1_FB23 CAN_F8R1_FB23_Msk /*!< Filter bit 23 */
+#define CAN_F8R1_FB24_Pos (24U)
+#define CAN_F8R1_FB24_Msk (0x1U << CAN_F8R1_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F8R1_FB24 CAN_F8R1_FB24_Msk /*!< Filter bit 24 */
+#define CAN_F8R1_FB25_Pos (25U)
+#define CAN_F8R1_FB25_Msk (0x1U << CAN_F8R1_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F8R1_FB25 CAN_F8R1_FB25_Msk /*!< Filter bit 25 */
+#define CAN_F8R1_FB26_Pos (26U)
+#define CAN_F8R1_FB26_Msk (0x1U << CAN_F8R1_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F8R1_FB26 CAN_F8R1_FB26_Msk /*!< Filter bit 26 */
+#define CAN_F8R1_FB27_Pos (27U)
+#define CAN_F8R1_FB27_Msk (0x1U << CAN_F8R1_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F8R1_FB27 CAN_F8R1_FB27_Msk /*!< Filter bit 27 */
+#define CAN_F8R1_FB28_Pos (28U)
+#define CAN_F8R1_FB28_Msk (0x1U << CAN_F8R1_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F8R1_FB28 CAN_F8R1_FB28_Msk /*!< Filter bit 28 */
+#define CAN_F8R1_FB29_Pos (29U)
+#define CAN_F8R1_FB29_Msk (0x1U << CAN_F8R1_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F8R1_FB29 CAN_F8R1_FB29_Msk /*!< Filter bit 29 */
+#define CAN_F8R1_FB30_Pos (30U)
+#define CAN_F8R1_FB30_Msk (0x1U << CAN_F8R1_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F8R1_FB30 CAN_F8R1_FB30_Msk /*!< Filter bit 30 */
+#define CAN_F8R1_FB31_Pos (31U)
+#define CAN_F8R1_FB31_Msk (0x1U << CAN_F8R1_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F8R1_FB31 CAN_F8R1_FB31_Msk /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F9R1 register *******************/
+#define CAN_F9R1_FB0_Pos (0U)
+#define CAN_F9R1_FB0_Msk (0x1U << CAN_F9R1_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F9R1_FB0 CAN_F9R1_FB0_Msk /*!< Filter bit 0 */
+#define CAN_F9R1_FB1_Pos (1U)
+#define CAN_F9R1_FB1_Msk (0x1U << CAN_F9R1_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F9R1_FB1 CAN_F9R1_FB1_Msk /*!< Filter bit 1 */
+#define CAN_F9R1_FB2_Pos (2U)
+#define CAN_F9R1_FB2_Msk (0x1U << CAN_F9R1_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F9R1_FB2 CAN_F9R1_FB2_Msk /*!< Filter bit 2 */
+#define CAN_F9R1_FB3_Pos (3U)
+#define CAN_F9R1_FB3_Msk (0x1U << CAN_F9R1_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F9R1_FB3 CAN_F9R1_FB3_Msk /*!< Filter bit 3 */
+#define CAN_F9R1_FB4_Pos (4U)
+#define CAN_F9R1_FB4_Msk (0x1U << CAN_F9R1_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F9R1_FB4 CAN_F9R1_FB4_Msk /*!< Filter bit 4 */
+#define CAN_F9R1_FB5_Pos (5U)
+#define CAN_F9R1_FB5_Msk (0x1U << CAN_F9R1_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F9R1_FB5 CAN_F9R1_FB5_Msk /*!< Filter bit 5 */
+#define CAN_F9R1_FB6_Pos (6U)
+#define CAN_F9R1_FB6_Msk (0x1U << CAN_F9R1_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F9R1_FB6 CAN_F9R1_FB6_Msk /*!< Filter bit 6 */
+#define CAN_F9R1_FB7_Pos (7U)
+#define CAN_F9R1_FB7_Msk (0x1U << CAN_F9R1_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F9R1_FB7 CAN_F9R1_FB7_Msk /*!< Filter bit 7 */
+#define CAN_F9R1_FB8_Pos (8U)
+#define CAN_F9R1_FB8_Msk (0x1U << CAN_F9R1_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F9R1_FB8 CAN_F9R1_FB8_Msk /*!< Filter bit 8 */
+#define CAN_F9R1_FB9_Pos (9U)
+#define CAN_F9R1_FB9_Msk (0x1U << CAN_F9R1_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F9R1_FB9 CAN_F9R1_FB9_Msk /*!< Filter bit 9 */
+#define CAN_F9R1_FB10_Pos (10U)
+#define CAN_F9R1_FB10_Msk (0x1U << CAN_F9R1_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F9R1_FB10 CAN_F9R1_FB10_Msk /*!< Filter bit 10 */
+#define CAN_F9R1_FB11_Pos (11U)
+#define CAN_F9R1_FB11_Msk (0x1U << CAN_F9R1_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F9R1_FB11 CAN_F9R1_FB11_Msk /*!< Filter bit 11 */
+#define CAN_F9R1_FB12_Pos (12U)
+#define CAN_F9R1_FB12_Msk (0x1U << CAN_F9R1_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F9R1_FB12 CAN_F9R1_FB12_Msk /*!< Filter bit 12 */
+#define CAN_F9R1_FB13_Pos (13U)
+#define CAN_F9R1_FB13_Msk (0x1U << CAN_F9R1_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F9R1_FB13 CAN_F9R1_FB13_Msk /*!< Filter bit 13 */
+#define CAN_F9R1_FB14_Pos (14U)
+#define CAN_F9R1_FB14_Msk (0x1U << CAN_F9R1_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F9R1_FB14 CAN_F9R1_FB14_Msk /*!< Filter bit 14 */
+#define CAN_F9R1_FB15_Pos (15U)
+#define CAN_F9R1_FB15_Msk (0x1U << CAN_F9R1_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F9R1_FB15 CAN_F9R1_FB15_Msk /*!< Filter bit 15 */
+#define CAN_F9R1_FB16_Pos (16U)
+#define CAN_F9R1_FB16_Msk (0x1U << CAN_F9R1_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F9R1_FB16 CAN_F9R1_FB16_Msk /*!< Filter bit 16 */
+#define CAN_F9R1_FB17_Pos (17U)
+#define CAN_F9R1_FB17_Msk (0x1U << CAN_F9R1_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F9R1_FB17 CAN_F9R1_FB17_Msk /*!< Filter bit 17 */
+#define CAN_F9R1_FB18_Pos (18U)
+#define CAN_F9R1_FB18_Msk (0x1U << CAN_F9R1_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F9R1_FB18 CAN_F9R1_FB18_Msk /*!< Filter bit 18 */
+#define CAN_F9R1_FB19_Pos (19U)
+#define CAN_F9R1_FB19_Msk (0x1U << CAN_F9R1_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F9R1_FB19 CAN_F9R1_FB19_Msk /*!< Filter bit 19 */
+#define CAN_F9R1_FB20_Pos (20U)
+#define CAN_F9R1_FB20_Msk (0x1U << CAN_F9R1_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F9R1_FB20 CAN_F9R1_FB20_Msk /*!< Filter bit 20 */
+#define CAN_F9R1_FB21_Pos (21U)
+#define CAN_F9R1_FB21_Msk (0x1U << CAN_F9R1_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F9R1_FB21 CAN_F9R1_FB21_Msk /*!< Filter bit 21 */
+#define CAN_F9R1_FB22_Pos (22U)
+#define CAN_F9R1_FB22_Msk (0x1U << CAN_F9R1_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F9R1_FB22 CAN_F9R1_FB22_Msk /*!< Filter bit 22 */
+#define CAN_F9R1_FB23_Pos (23U)
+#define CAN_F9R1_FB23_Msk (0x1U << CAN_F9R1_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F9R1_FB23 CAN_F9R1_FB23_Msk /*!< Filter bit 23 */
+#define CAN_F9R1_FB24_Pos (24U)
+#define CAN_F9R1_FB24_Msk (0x1U << CAN_F9R1_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F9R1_FB24 CAN_F9R1_FB24_Msk /*!< Filter bit 24 */
+#define CAN_F9R1_FB25_Pos (25U)
+#define CAN_F9R1_FB25_Msk (0x1U << CAN_F9R1_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F9R1_FB25 CAN_F9R1_FB25_Msk /*!< Filter bit 25 */
+#define CAN_F9R1_FB26_Pos (26U)
+#define CAN_F9R1_FB26_Msk (0x1U << CAN_F9R1_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F9R1_FB26 CAN_F9R1_FB26_Msk /*!< Filter bit 26 */
+#define CAN_F9R1_FB27_Pos (27U)
+#define CAN_F9R1_FB27_Msk (0x1U << CAN_F9R1_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F9R1_FB27 CAN_F9R1_FB27_Msk /*!< Filter bit 27 */
+#define CAN_F9R1_FB28_Pos (28U)
+#define CAN_F9R1_FB28_Msk (0x1U << CAN_F9R1_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F9R1_FB28 CAN_F9R1_FB28_Msk /*!< Filter bit 28 */
+#define CAN_F9R1_FB29_Pos (29U)
+#define CAN_F9R1_FB29_Msk (0x1U << CAN_F9R1_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F9R1_FB29 CAN_F9R1_FB29_Msk /*!< Filter bit 29 */
+#define CAN_F9R1_FB30_Pos (30U)
+#define CAN_F9R1_FB30_Msk (0x1U << CAN_F9R1_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F9R1_FB30 CAN_F9R1_FB30_Msk /*!< Filter bit 30 */
+#define CAN_F9R1_FB31_Pos (31U)
+#define CAN_F9R1_FB31_Msk (0x1U << CAN_F9R1_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F9R1_FB31 CAN_F9R1_FB31_Msk /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F10R1 register ******************/
+#define CAN_F10R1_FB0_Pos (0U)
+#define CAN_F10R1_FB0_Msk (0x1U << CAN_F10R1_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F10R1_FB0 CAN_F10R1_FB0_Msk /*!< Filter bit 0 */
+#define CAN_F10R1_FB1_Pos (1U)
+#define CAN_F10R1_FB1_Msk (0x1U << CAN_F10R1_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F10R1_FB1 CAN_F10R1_FB1_Msk /*!< Filter bit 1 */
+#define CAN_F10R1_FB2_Pos (2U)
+#define CAN_F10R1_FB2_Msk (0x1U << CAN_F10R1_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F10R1_FB2 CAN_F10R1_FB2_Msk /*!< Filter bit 2 */
+#define CAN_F10R1_FB3_Pos (3U)
+#define CAN_F10R1_FB3_Msk (0x1U << CAN_F10R1_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F10R1_FB3 CAN_F10R1_FB3_Msk /*!< Filter bit 3 */
+#define CAN_F10R1_FB4_Pos (4U)
+#define CAN_F10R1_FB4_Msk (0x1U << CAN_F10R1_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F10R1_FB4 CAN_F10R1_FB4_Msk /*!< Filter bit 4 */
+#define CAN_F10R1_FB5_Pos (5U)
+#define CAN_F10R1_FB5_Msk (0x1U << CAN_F10R1_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F10R1_FB5 CAN_F10R1_FB5_Msk /*!< Filter bit 5 */
+#define CAN_F10R1_FB6_Pos (6U)
+#define CAN_F10R1_FB6_Msk (0x1U << CAN_F10R1_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F10R1_FB6 CAN_F10R1_FB6_Msk /*!< Filter bit 6 */
+#define CAN_F10R1_FB7_Pos (7U)
+#define CAN_F10R1_FB7_Msk (0x1U << CAN_F10R1_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F10R1_FB7 CAN_F10R1_FB7_Msk /*!< Filter bit 7 */
+#define CAN_F10R1_FB8_Pos (8U)
+#define CAN_F10R1_FB8_Msk (0x1U << CAN_F10R1_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F10R1_FB8 CAN_F10R1_FB8_Msk /*!< Filter bit 8 */
+#define CAN_F10R1_FB9_Pos (9U)
+#define CAN_F10R1_FB9_Msk (0x1U << CAN_F10R1_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F10R1_FB9 CAN_F10R1_FB9_Msk /*!< Filter bit 9 */
+#define CAN_F10R1_FB10_Pos (10U)
+#define CAN_F10R1_FB10_Msk (0x1U << CAN_F10R1_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F10R1_FB10 CAN_F10R1_FB10_Msk /*!< Filter bit 10 */
+#define CAN_F10R1_FB11_Pos (11U)
+#define CAN_F10R1_FB11_Msk (0x1U << CAN_F10R1_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F10R1_FB11 CAN_F10R1_FB11_Msk /*!< Filter bit 11 */
+#define CAN_F10R1_FB12_Pos (12U)
+#define CAN_F10R1_FB12_Msk (0x1U << CAN_F10R1_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F10R1_FB12 CAN_F10R1_FB12_Msk /*!< Filter bit 12 */
+#define CAN_F10R1_FB13_Pos (13U)
+#define CAN_F10R1_FB13_Msk (0x1U << CAN_F10R1_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F10R1_FB13 CAN_F10R1_FB13_Msk /*!< Filter bit 13 */
+#define CAN_F10R1_FB14_Pos (14U)
+#define CAN_F10R1_FB14_Msk (0x1U << CAN_F10R1_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F10R1_FB14 CAN_F10R1_FB14_Msk /*!< Filter bit 14 */
+#define CAN_F10R1_FB15_Pos (15U)
+#define CAN_F10R1_FB15_Msk (0x1U << CAN_F10R1_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F10R1_FB15 CAN_F10R1_FB15_Msk /*!< Filter bit 15 */
+#define CAN_F10R1_FB16_Pos (16U)
+#define CAN_F10R1_FB16_Msk (0x1U << CAN_F10R1_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F10R1_FB16 CAN_F10R1_FB16_Msk /*!< Filter bit 16 */
+#define CAN_F10R1_FB17_Pos (17U)
+#define CAN_F10R1_FB17_Msk (0x1U << CAN_F10R1_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F10R1_FB17 CAN_F10R1_FB17_Msk /*!< Filter bit 17 */
+#define CAN_F10R1_FB18_Pos (18U)
+#define CAN_F10R1_FB18_Msk (0x1U << CAN_F10R1_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F10R1_FB18 CAN_F10R1_FB18_Msk /*!< Filter bit 18 */
+#define CAN_F10R1_FB19_Pos (19U)
+#define CAN_F10R1_FB19_Msk (0x1U << CAN_F10R1_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F10R1_FB19 CAN_F10R1_FB19_Msk /*!< Filter bit 19 */
+#define CAN_F10R1_FB20_Pos (20U)
+#define CAN_F10R1_FB20_Msk (0x1U << CAN_F10R1_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F10R1_FB20 CAN_F10R1_FB20_Msk /*!< Filter bit 20 */
+#define CAN_F10R1_FB21_Pos (21U)
+#define CAN_F10R1_FB21_Msk (0x1U << CAN_F10R1_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F10R1_FB21 CAN_F10R1_FB21_Msk /*!< Filter bit 21 */
+#define CAN_F10R1_FB22_Pos (22U)
+#define CAN_F10R1_FB22_Msk (0x1U << CAN_F10R1_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F10R1_FB22 CAN_F10R1_FB22_Msk /*!< Filter bit 22 */
+#define CAN_F10R1_FB23_Pos (23U)
+#define CAN_F10R1_FB23_Msk (0x1U << CAN_F10R1_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F10R1_FB23 CAN_F10R1_FB23_Msk /*!< Filter bit 23 */
+#define CAN_F10R1_FB24_Pos (24U)
+#define CAN_F10R1_FB24_Msk (0x1U << CAN_F10R1_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F10R1_FB24 CAN_F10R1_FB24_Msk /*!< Filter bit 24 */
+#define CAN_F10R1_FB25_Pos (25U)
+#define CAN_F10R1_FB25_Msk (0x1U << CAN_F10R1_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F10R1_FB25 CAN_F10R1_FB25_Msk /*!< Filter bit 25 */
+#define CAN_F10R1_FB26_Pos (26U)
+#define CAN_F10R1_FB26_Msk (0x1U << CAN_F10R1_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F10R1_FB26 CAN_F10R1_FB26_Msk /*!< Filter bit 26 */
+#define CAN_F10R1_FB27_Pos (27U)
+#define CAN_F10R1_FB27_Msk (0x1U << CAN_F10R1_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F10R1_FB27 CAN_F10R1_FB27_Msk /*!< Filter bit 27 */
+#define CAN_F10R1_FB28_Pos (28U)
+#define CAN_F10R1_FB28_Msk (0x1U << CAN_F10R1_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F10R1_FB28 CAN_F10R1_FB28_Msk /*!< Filter bit 28 */
+#define CAN_F10R1_FB29_Pos (29U)
+#define CAN_F10R1_FB29_Msk (0x1U << CAN_F10R1_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F10R1_FB29 CAN_F10R1_FB29_Msk /*!< Filter bit 29 */
+#define CAN_F10R1_FB30_Pos (30U)
+#define CAN_F10R1_FB30_Msk (0x1U << CAN_F10R1_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F10R1_FB30 CAN_F10R1_FB30_Msk /*!< Filter bit 30 */
+#define CAN_F10R1_FB31_Pos (31U)
+#define CAN_F10R1_FB31_Msk (0x1U << CAN_F10R1_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F10R1_FB31 CAN_F10R1_FB31_Msk /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F11R1 register ******************/
+#define CAN_F11R1_FB0_Pos (0U)
+#define CAN_F11R1_FB0_Msk (0x1U << CAN_F11R1_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F11R1_FB0 CAN_F11R1_FB0_Msk /*!< Filter bit 0 */
+#define CAN_F11R1_FB1_Pos (1U)
+#define CAN_F11R1_FB1_Msk (0x1U << CAN_F11R1_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F11R1_FB1 CAN_F11R1_FB1_Msk /*!< Filter bit 1 */
+#define CAN_F11R1_FB2_Pos (2U)
+#define CAN_F11R1_FB2_Msk (0x1U << CAN_F11R1_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F11R1_FB2 CAN_F11R1_FB2_Msk /*!< Filter bit 2 */
+#define CAN_F11R1_FB3_Pos (3U)
+#define CAN_F11R1_FB3_Msk (0x1U << CAN_F11R1_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F11R1_FB3 CAN_F11R1_FB3_Msk /*!< Filter bit 3 */
+#define CAN_F11R1_FB4_Pos (4U)
+#define CAN_F11R1_FB4_Msk (0x1U << CAN_F11R1_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F11R1_FB4 CAN_F11R1_FB4_Msk /*!< Filter bit 4 */
+#define CAN_F11R1_FB5_Pos (5U)
+#define CAN_F11R1_FB5_Msk (0x1U << CAN_F11R1_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F11R1_FB5 CAN_F11R1_FB5_Msk /*!< Filter bit 5 */
+#define CAN_F11R1_FB6_Pos (6U)
+#define CAN_F11R1_FB6_Msk (0x1U << CAN_F11R1_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F11R1_FB6 CAN_F11R1_FB6_Msk /*!< Filter bit 6 */
+#define CAN_F11R1_FB7_Pos (7U)
+#define CAN_F11R1_FB7_Msk (0x1U << CAN_F11R1_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F11R1_FB7 CAN_F11R1_FB7_Msk /*!< Filter bit 7 */
+#define CAN_F11R1_FB8_Pos (8U)
+#define CAN_F11R1_FB8_Msk (0x1U << CAN_F11R1_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F11R1_FB8 CAN_F11R1_FB8_Msk /*!< Filter bit 8 */
+#define CAN_F11R1_FB9_Pos (9U)
+#define CAN_F11R1_FB9_Msk (0x1U << CAN_F11R1_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F11R1_FB9 CAN_F11R1_FB9_Msk /*!< Filter bit 9 */
+#define CAN_F11R1_FB10_Pos (10U)
+#define CAN_F11R1_FB10_Msk (0x1U << CAN_F11R1_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F11R1_FB10 CAN_F11R1_FB10_Msk /*!< Filter bit 10 */
+#define CAN_F11R1_FB11_Pos (11U)
+#define CAN_F11R1_FB11_Msk (0x1U << CAN_F11R1_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F11R1_FB11 CAN_F11R1_FB11_Msk /*!< Filter bit 11 */
+#define CAN_F11R1_FB12_Pos (12U)
+#define CAN_F11R1_FB12_Msk (0x1U << CAN_F11R1_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F11R1_FB12 CAN_F11R1_FB12_Msk /*!< Filter bit 12 */
+#define CAN_F11R1_FB13_Pos (13U)
+#define CAN_F11R1_FB13_Msk (0x1U << CAN_F11R1_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F11R1_FB13 CAN_F11R1_FB13_Msk /*!< Filter bit 13 */
+#define CAN_F11R1_FB14_Pos (14U)
+#define CAN_F11R1_FB14_Msk (0x1U << CAN_F11R1_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F11R1_FB14 CAN_F11R1_FB14_Msk /*!< Filter bit 14 */
+#define CAN_F11R1_FB15_Pos (15U)
+#define CAN_F11R1_FB15_Msk (0x1U << CAN_F11R1_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F11R1_FB15 CAN_F11R1_FB15_Msk /*!< Filter bit 15 */
+#define CAN_F11R1_FB16_Pos (16U)
+#define CAN_F11R1_FB16_Msk (0x1U << CAN_F11R1_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F11R1_FB16 CAN_F11R1_FB16_Msk /*!< Filter bit 16 */
+#define CAN_F11R1_FB17_Pos (17U)
+#define CAN_F11R1_FB17_Msk (0x1U << CAN_F11R1_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F11R1_FB17 CAN_F11R1_FB17_Msk /*!< Filter bit 17 */
+#define CAN_F11R1_FB18_Pos (18U)
+#define CAN_F11R1_FB18_Msk (0x1U << CAN_F11R1_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F11R1_FB18 CAN_F11R1_FB18_Msk /*!< Filter bit 18 */
+#define CAN_F11R1_FB19_Pos (19U)
+#define CAN_F11R1_FB19_Msk (0x1U << CAN_F11R1_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F11R1_FB19 CAN_F11R1_FB19_Msk /*!< Filter bit 19 */
+#define CAN_F11R1_FB20_Pos (20U)
+#define CAN_F11R1_FB20_Msk (0x1U << CAN_F11R1_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F11R1_FB20 CAN_F11R1_FB20_Msk /*!< Filter bit 20 */
+#define CAN_F11R1_FB21_Pos (21U)
+#define CAN_F11R1_FB21_Msk (0x1U << CAN_F11R1_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F11R1_FB21 CAN_F11R1_FB21_Msk /*!< Filter bit 21 */
+#define CAN_F11R1_FB22_Pos (22U)
+#define CAN_F11R1_FB22_Msk (0x1U << CAN_F11R1_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F11R1_FB22 CAN_F11R1_FB22_Msk /*!< Filter bit 22 */
+#define CAN_F11R1_FB23_Pos (23U)
+#define CAN_F11R1_FB23_Msk (0x1U << CAN_F11R1_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F11R1_FB23 CAN_F11R1_FB23_Msk /*!< Filter bit 23 */
+#define CAN_F11R1_FB24_Pos (24U)
+#define CAN_F11R1_FB24_Msk (0x1U << CAN_F11R1_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F11R1_FB24 CAN_F11R1_FB24_Msk /*!< Filter bit 24 */
+#define CAN_F11R1_FB25_Pos (25U)
+#define CAN_F11R1_FB25_Msk (0x1U << CAN_F11R1_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F11R1_FB25 CAN_F11R1_FB25_Msk /*!< Filter bit 25 */
+#define CAN_F11R1_FB26_Pos (26U)
+#define CAN_F11R1_FB26_Msk (0x1U << CAN_F11R1_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F11R1_FB26 CAN_F11R1_FB26_Msk /*!< Filter bit 26 */
+#define CAN_F11R1_FB27_Pos (27U)
+#define CAN_F11R1_FB27_Msk (0x1U << CAN_F11R1_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F11R1_FB27 CAN_F11R1_FB27_Msk /*!< Filter bit 27 */
+#define CAN_F11R1_FB28_Pos (28U)
+#define CAN_F11R1_FB28_Msk (0x1U << CAN_F11R1_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F11R1_FB28 CAN_F11R1_FB28_Msk /*!< Filter bit 28 */
+#define CAN_F11R1_FB29_Pos (29U)
+#define CAN_F11R1_FB29_Msk (0x1U << CAN_F11R1_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F11R1_FB29 CAN_F11R1_FB29_Msk /*!< Filter bit 29 */
+#define CAN_F11R1_FB30_Pos (30U)
+#define CAN_F11R1_FB30_Msk (0x1U << CAN_F11R1_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F11R1_FB30 CAN_F11R1_FB30_Msk /*!< Filter bit 30 */
+#define CAN_F11R1_FB31_Pos (31U)
+#define CAN_F11R1_FB31_Msk (0x1U << CAN_F11R1_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F11R1_FB31 CAN_F11R1_FB31_Msk /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F12R1 register ******************/
+#define CAN_F12R1_FB0_Pos (0U)
+#define CAN_F12R1_FB0_Msk (0x1U << CAN_F12R1_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F12R1_FB0 CAN_F12R1_FB0_Msk /*!< Filter bit 0 */
+#define CAN_F12R1_FB1_Pos (1U)
+#define CAN_F12R1_FB1_Msk (0x1U << CAN_F12R1_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F12R1_FB1 CAN_F12R1_FB1_Msk /*!< Filter bit 1 */
+#define CAN_F12R1_FB2_Pos (2U)
+#define CAN_F12R1_FB2_Msk (0x1U << CAN_F12R1_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F12R1_FB2 CAN_F12R1_FB2_Msk /*!< Filter bit 2 */
+#define CAN_F12R1_FB3_Pos (3U)
+#define CAN_F12R1_FB3_Msk (0x1U << CAN_F12R1_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F12R1_FB3 CAN_F12R1_FB3_Msk /*!< Filter bit 3 */
+#define CAN_F12R1_FB4_Pos (4U)
+#define CAN_F12R1_FB4_Msk (0x1U << CAN_F12R1_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F12R1_FB4 CAN_F12R1_FB4_Msk /*!< Filter bit 4 */
+#define CAN_F12R1_FB5_Pos (5U)
+#define CAN_F12R1_FB5_Msk (0x1U << CAN_F12R1_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F12R1_FB5 CAN_F12R1_FB5_Msk /*!< Filter bit 5 */
+#define CAN_F12R1_FB6_Pos (6U)
+#define CAN_F12R1_FB6_Msk (0x1U << CAN_F12R1_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F12R1_FB6 CAN_F12R1_FB6_Msk /*!< Filter bit 6 */
+#define CAN_F12R1_FB7_Pos (7U)
+#define CAN_F12R1_FB7_Msk (0x1U << CAN_F12R1_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F12R1_FB7 CAN_F12R1_FB7_Msk /*!< Filter bit 7 */
+#define CAN_F12R1_FB8_Pos (8U)
+#define CAN_F12R1_FB8_Msk (0x1U << CAN_F12R1_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F12R1_FB8 CAN_F12R1_FB8_Msk /*!< Filter bit 8 */
+#define CAN_F12R1_FB9_Pos (9U)
+#define CAN_F12R1_FB9_Msk (0x1U << CAN_F12R1_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F12R1_FB9 CAN_F12R1_FB9_Msk /*!< Filter bit 9 */
+#define CAN_F12R1_FB10_Pos (10U)
+#define CAN_F12R1_FB10_Msk (0x1U << CAN_F12R1_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F12R1_FB10 CAN_F12R1_FB10_Msk /*!< Filter bit 10 */
+#define CAN_F12R1_FB11_Pos (11U)
+#define CAN_F12R1_FB11_Msk (0x1U << CAN_F12R1_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F12R1_FB11 CAN_F12R1_FB11_Msk /*!< Filter bit 11 */
+#define CAN_F12R1_FB12_Pos (12U)
+#define CAN_F12R1_FB12_Msk (0x1U << CAN_F12R1_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F12R1_FB12 CAN_F12R1_FB12_Msk /*!< Filter bit 12 */
+#define CAN_F12R1_FB13_Pos (13U)
+#define CAN_F12R1_FB13_Msk (0x1U << CAN_F12R1_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F12R1_FB13 CAN_F12R1_FB13_Msk /*!< Filter bit 13 */
+#define CAN_F12R1_FB14_Pos (14U)
+#define CAN_F12R1_FB14_Msk (0x1U << CAN_F12R1_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F12R1_FB14 CAN_F12R1_FB14_Msk /*!< Filter bit 14 */
+#define CAN_F12R1_FB15_Pos (15U)
+#define CAN_F12R1_FB15_Msk (0x1U << CAN_F12R1_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F12R1_FB15 CAN_F12R1_FB15_Msk /*!< Filter bit 15 */
+#define CAN_F12R1_FB16_Pos (16U)
+#define CAN_F12R1_FB16_Msk (0x1U << CAN_F12R1_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F12R1_FB16 CAN_F12R1_FB16_Msk /*!< Filter bit 16 */
+#define CAN_F12R1_FB17_Pos (17U)
+#define CAN_F12R1_FB17_Msk (0x1U << CAN_F12R1_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F12R1_FB17 CAN_F12R1_FB17_Msk /*!< Filter bit 17 */
+#define CAN_F12R1_FB18_Pos (18U)
+#define CAN_F12R1_FB18_Msk (0x1U << CAN_F12R1_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F12R1_FB18 CAN_F12R1_FB18_Msk /*!< Filter bit 18 */
+#define CAN_F12R1_FB19_Pos (19U)
+#define CAN_F12R1_FB19_Msk (0x1U << CAN_F12R1_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F12R1_FB19 CAN_F12R1_FB19_Msk /*!< Filter bit 19 */
+#define CAN_F12R1_FB20_Pos (20U)
+#define CAN_F12R1_FB20_Msk (0x1U << CAN_F12R1_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F12R1_FB20 CAN_F12R1_FB20_Msk /*!< Filter bit 20 */
+#define CAN_F12R1_FB21_Pos (21U)
+#define CAN_F12R1_FB21_Msk (0x1U << CAN_F12R1_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F12R1_FB21 CAN_F12R1_FB21_Msk /*!< Filter bit 21 */
+#define CAN_F12R1_FB22_Pos (22U)
+#define CAN_F12R1_FB22_Msk (0x1U << CAN_F12R1_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F12R1_FB22 CAN_F12R1_FB22_Msk /*!< Filter bit 22 */
+#define CAN_F12R1_FB23_Pos (23U)
+#define CAN_F12R1_FB23_Msk (0x1U << CAN_F12R1_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F12R1_FB23 CAN_F12R1_FB23_Msk /*!< Filter bit 23 */
+#define CAN_F12R1_FB24_Pos (24U)
+#define CAN_F12R1_FB24_Msk (0x1U << CAN_F12R1_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F12R1_FB24 CAN_F12R1_FB24_Msk /*!< Filter bit 24 */
+#define CAN_F12R1_FB25_Pos (25U)
+#define CAN_F12R1_FB25_Msk (0x1U << CAN_F12R1_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F12R1_FB25 CAN_F12R1_FB25_Msk /*!< Filter bit 25 */
+#define CAN_F12R1_FB26_Pos (26U)
+#define CAN_F12R1_FB26_Msk (0x1U << CAN_F12R1_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F12R1_FB26 CAN_F12R1_FB26_Msk /*!< Filter bit 26 */
+#define CAN_F12R1_FB27_Pos (27U)
+#define CAN_F12R1_FB27_Msk (0x1U << CAN_F12R1_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F12R1_FB27 CAN_F12R1_FB27_Msk /*!< Filter bit 27 */
+#define CAN_F12R1_FB28_Pos (28U)
+#define CAN_F12R1_FB28_Msk (0x1U << CAN_F12R1_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F12R1_FB28 CAN_F12R1_FB28_Msk /*!< Filter bit 28 */
+#define CAN_F12R1_FB29_Pos (29U)
+#define CAN_F12R1_FB29_Msk (0x1U << CAN_F12R1_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F12R1_FB29 CAN_F12R1_FB29_Msk /*!< Filter bit 29 */
+#define CAN_F12R1_FB30_Pos (30U)
+#define CAN_F12R1_FB30_Msk (0x1U << CAN_F12R1_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F12R1_FB30 CAN_F12R1_FB30_Msk /*!< Filter bit 30 */
+#define CAN_F12R1_FB31_Pos (31U)
+#define CAN_F12R1_FB31_Msk (0x1U << CAN_F12R1_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F12R1_FB31 CAN_F12R1_FB31_Msk /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F13R1 register ******************/
+#define CAN_F13R1_FB0_Pos (0U)
+#define CAN_F13R1_FB0_Msk (0x1U << CAN_F13R1_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F13R1_FB0 CAN_F13R1_FB0_Msk /*!< Filter bit 0 */
+#define CAN_F13R1_FB1_Pos (1U)
+#define CAN_F13R1_FB1_Msk (0x1U << CAN_F13R1_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F13R1_FB1 CAN_F13R1_FB1_Msk /*!< Filter bit 1 */
+#define CAN_F13R1_FB2_Pos (2U)
+#define CAN_F13R1_FB2_Msk (0x1U << CAN_F13R1_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F13R1_FB2 CAN_F13R1_FB2_Msk /*!< Filter bit 2 */
+#define CAN_F13R1_FB3_Pos (3U)
+#define CAN_F13R1_FB3_Msk (0x1U << CAN_F13R1_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F13R1_FB3 CAN_F13R1_FB3_Msk /*!< Filter bit 3 */
+#define CAN_F13R1_FB4_Pos (4U)
+#define CAN_F13R1_FB4_Msk (0x1U << CAN_F13R1_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F13R1_FB4 CAN_F13R1_FB4_Msk /*!< Filter bit 4 */
+#define CAN_F13R1_FB5_Pos (5U)
+#define CAN_F13R1_FB5_Msk (0x1U << CAN_F13R1_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F13R1_FB5 CAN_F13R1_FB5_Msk /*!< Filter bit 5 */
+#define CAN_F13R1_FB6_Pos (6U)
+#define CAN_F13R1_FB6_Msk (0x1U << CAN_F13R1_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F13R1_FB6 CAN_F13R1_FB6_Msk /*!< Filter bit 6 */
+#define CAN_F13R1_FB7_Pos (7U)
+#define CAN_F13R1_FB7_Msk (0x1U << CAN_F13R1_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F13R1_FB7 CAN_F13R1_FB7_Msk /*!< Filter bit 7 */
+#define CAN_F13R1_FB8_Pos (8U)
+#define CAN_F13R1_FB8_Msk (0x1U << CAN_F13R1_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F13R1_FB8 CAN_F13R1_FB8_Msk /*!< Filter bit 8 */
+#define CAN_F13R1_FB9_Pos (9U)
+#define CAN_F13R1_FB9_Msk (0x1U << CAN_F13R1_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F13R1_FB9 CAN_F13R1_FB9_Msk /*!< Filter bit 9 */
+#define CAN_F13R1_FB10_Pos (10U)
+#define CAN_F13R1_FB10_Msk (0x1U << CAN_F13R1_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F13R1_FB10 CAN_F13R1_FB10_Msk /*!< Filter bit 10 */
+#define CAN_F13R1_FB11_Pos (11U)
+#define CAN_F13R1_FB11_Msk (0x1U << CAN_F13R1_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F13R1_FB11 CAN_F13R1_FB11_Msk /*!< Filter bit 11 */
+#define CAN_F13R1_FB12_Pos (12U)
+#define CAN_F13R1_FB12_Msk (0x1U << CAN_F13R1_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F13R1_FB12 CAN_F13R1_FB12_Msk /*!< Filter bit 12 */
+#define CAN_F13R1_FB13_Pos (13U)
+#define CAN_F13R1_FB13_Msk (0x1U << CAN_F13R1_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F13R1_FB13 CAN_F13R1_FB13_Msk /*!< Filter bit 13 */
+#define CAN_F13R1_FB14_Pos (14U)
+#define CAN_F13R1_FB14_Msk (0x1U << CAN_F13R1_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F13R1_FB14 CAN_F13R1_FB14_Msk /*!< Filter bit 14 */
+#define CAN_F13R1_FB15_Pos (15U)
+#define CAN_F13R1_FB15_Msk (0x1U << CAN_F13R1_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F13R1_FB15 CAN_F13R1_FB15_Msk /*!< Filter bit 15 */
+#define CAN_F13R1_FB16_Pos (16U)
+#define CAN_F13R1_FB16_Msk (0x1U << CAN_F13R1_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F13R1_FB16 CAN_F13R1_FB16_Msk /*!< Filter bit 16 */
+#define CAN_F13R1_FB17_Pos (17U)
+#define CAN_F13R1_FB17_Msk (0x1U << CAN_F13R1_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F13R1_FB17 CAN_F13R1_FB17_Msk /*!< Filter bit 17 */
+#define CAN_F13R1_FB18_Pos (18U)
+#define CAN_F13R1_FB18_Msk (0x1U << CAN_F13R1_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F13R1_FB18 CAN_F13R1_FB18_Msk /*!< Filter bit 18 */
+#define CAN_F13R1_FB19_Pos (19U)
+#define CAN_F13R1_FB19_Msk (0x1U << CAN_F13R1_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F13R1_FB19 CAN_F13R1_FB19_Msk /*!< Filter bit 19 */
+#define CAN_F13R1_FB20_Pos (20U)
+#define CAN_F13R1_FB20_Msk (0x1U << CAN_F13R1_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F13R1_FB20 CAN_F13R1_FB20_Msk /*!< Filter bit 20 */
+#define CAN_F13R1_FB21_Pos (21U)
+#define CAN_F13R1_FB21_Msk (0x1U << CAN_F13R1_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F13R1_FB21 CAN_F13R1_FB21_Msk /*!< Filter bit 21 */
+#define CAN_F13R1_FB22_Pos (22U)
+#define CAN_F13R1_FB22_Msk (0x1U << CAN_F13R1_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F13R1_FB22 CAN_F13R1_FB22_Msk /*!< Filter bit 22 */
+#define CAN_F13R1_FB23_Pos (23U)
+#define CAN_F13R1_FB23_Msk (0x1U << CAN_F13R1_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F13R1_FB23 CAN_F13R1_FB23_Msk /*!< Filter bit 23 */
+#define CAN_F13R1_FB24_Pos (24U)
+#define CAN_F13R1_FB24_Msk (0x1U << CAN_F13R1_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F13R1_FB24 CAN_F13R1_FB24_Msk /*!< Filter bit 24 */
+#define CAN_F13R1_FB25_Pos (25U)
+#define CAN_F13R1_FB25_Msk (0x1U << CAN_F13R1_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F13R1_FB25 CAN_F13R1_FB25_Msk /*!< Filter bit 25 */
+#define CAN_F13R1_FB26_Pos (26U)
+#define CAN_F13R1_FB26_Msk (0x1U << CAN_F13R1_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F13R1_FB26 CAN_F13R1_FB26_Msk /*!< Filter bit 26 */
+#define CAN_F13R1_FB27_Pos (27U)
+#define CAN_F13R1_FB27_Msk (0x1U << CAN_F13R1_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F13R1_FB27 CAN_F13R1_FB27_Msk /*!< Filter bit 27 */
+#define CAN_F13R1_FB28_Pos (28U)
+#define CAN_F13R1_FB28_Msk (0x1U << CAN_F13R1_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F13R1_FB28 CAN_F13R1_FB28_Msk /*!< Filter bit 28 */
+#define CAN_F13R1_FB29_Pos (29U)
+#define CAN_F13R1_FB29_Msk (0x1U << CAN_F13R1_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F13R1_FB29 CAN_F13R1_FB29_Msk /*!< Filter bit 29 */
+#define CAN_F13R1_FB30_Pos (30U)
+#define CAN_F13R1_FB30_Msk (0x1U << CAN_F13R1_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F13R1_FB30 CAN_F13R1_FB30_Msk /*!< Filter bit 30 */
+#define CAN_F13R1_FB31_Pos (31U)
+#define CAN_F13R1_FB31_Msk (0x1U << CAN_F13R1_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F13R1_FB31 CAN_F13R1_FB31_Msk /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F0R2 register *******************/
+#define CAN_F0R2_FB0_Pos (0U)
+#define CAN_F0R2_FB0_Msk (0x1U << CAN_F0R2_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F0R2_FB0 CAN_F0R2_FB0_Msk /*!< Filter bit 0 */
+#define CAN_F0R2_FB1_Pos (1U)
+#define CAN_F0R2_FB1_Msk (0x1U << CAN_F0R2_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F0R2_FB1 CAN_F0R2_FB1_Msk /*!< Filter bit 1 */
+#define CAN_F0R2_FB2_Pos (2U)
+#define CAN_F0R2_FB2_Msk (0x1U << CAN_F0R2_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F0R2_FB2 CAN_F0R2_FB2_Msk /*!< Filter bit 2 */
+#define CAN_F0R2_FB3_Pos (3U)
+#define CAN_F0R2_FB3_Msk (0x1U << CAN_F0R2_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F0R2_FB3 CAN_F0R2_FB3_Msk /*!< Filter bit 3 */
+#define CAN_F0R2_FB4_Pos (4U)
+#define CAN_F0R2_FB4_Msk (0x1U << CAN_F0R2_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F0R2_FB4 CAN_F0R2_FB4_Msk /*!< Filter bit 4 */
+#define CAN_F0R2_FB5_Pos (5U)
+#define CAN_F0R2_FB5_Msk (0x1U << CAN_F0R2_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F0R2_FB5 CAN_F0R2_FB5_Msk /*!< Filter bit 5 */
+#define CAN_F0R2_FB6_Pos (6U)
+#define CAN_F0R2_FB6_Msk (0x1U << CAN_F0R2_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F0R2_FB6 CAN_F0R2_FB6_Msk /*!< Filter bit 6 */
+#define CAN_F0R2_FB7_Pos (7U)
+#define CAN_F0R2_FB7_Msk (0x1U << CAN_F0R2_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F0R2_FB7 CAN_F0R2_FB7_Msk /*!< Filter bit 7 */
+#define CAN_F0R2_FB8_Pos (8U)
+#define CAN_F0R2_FB8_Msk (0x1U << CAN_F0R2_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F0R2_FB8 CAN_F0R2_FB8_Msk /*!< Filter bit 8 */
+#define CAN_F0R2_FB9_Pos (9U)
+#define CAN_F0R2_FB9_Msk (0x1U << CAN_F0R2_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F0R2_FB9 CAN_F0R2_FB9_Msk /*!< Filter bit 9 */
+#define CAN_F0R2_FB10_Pos (10U)
+#define CAN_F0R2_FB10_Msk (0x1U << CAN_F0R2_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F0R2_FB10 CAN_F0R2_FB10_Msk /*!< Filter bit 10 */
+#define CAN_F0R2_FB11_Pos (11U)
+#define CAN_F0R2_FB11_Msk (0x1U << CAN_F0R2_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F0R2_FB11 CAN_F0R2_FB11_Msk /*!< Filter bit 11 */
+#define CAN_F0R2_FB12_Pos (12U)
+#define CAN_F0R2_FB12_Msk (0x1U << CAN_F0R2_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F0R2_FB12 CAN_F0R2_FB12_Msk /*!< Filter bit 12 */
+#define CAN_F0R2_FB13_Pos (13U)
+#define CAN_F0R2_FB13_Msk (0x1U << CAN_F0R2_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F0R2_FB13 CAN_F0R2_FB13_Msk /*!< Filter bit 13 */
+#define CAN_F0R2_FB14_Pos (14U)
+#define CAN_F0R2_FB14_Msk (0x1U << CAN_F0R2_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F0R2_FB14 CAN_F0R2_FB14_Msk /*!< Filter bit 14 */
+#define CAN_F0R2_FB15_Pos (15U)
+#define CAN_F0R2_FB15_Msk (0x1U << CAN_F0R2_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F0R2_FB15 CAN_F0R2_FB15_Msk /*!< Filter bit 15 */
+#define CAN_F0R2_FB16_Pos (16U)
+#define CAN_F0R2_FB16_Msk (0x1U << CAN_F0R2_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F0R2_FB16 CAN_F0R2_FB16_Msk /*!< Filter bit 16 */
+#define CAN_F0R2_FB17_Pos (17U)
+#define CAN_F0R2_FB17_Msk (0x1U << CAN_F0R2_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F0R2_FB17 CAN_F0R2_FB17_Msk /*!< Filter bit 17 */
+#define CAN_F0R2_FB18_Pos (18U)
+#define CAN_F0R2_FB18_Msk (0x1U << CAN_F0R2_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F0R2_FB18 CAN_F0R2_FB18_Msk /*!< Filter bit 18 */
+#define CAN_F0R2_FB19_Pos (19U)
+#define CAN_F0R2_FB19_Msk (0x1U << CAN_F0R2_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F0R2_FB19 CAN_F0R2_FB19_Msk /*!< Filter bit 19 */
+#define CAN_F0R2_FB20_Pos (20U)
+#define CAN_F0R2_FB20_Msk (0x1U << CAN_F0R2_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F0R2_FB20 CAN_F0R2_FB20_Msk /*!< Filter bit 20 */
+#define CAN_F0R2_FB21_Pos (21U)
+#define CAN_F0R2_FB21_Msk (0x1U << CAN_F0R2_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F0R2_FB21 CAN_F0R2_FB21_Msk /*!< Filter bit 21 */
+#define CAN_F0R2_FB22_Pos (22U)
+#define CAN_F0R2_FB22_Msk (0x1U << CAN_F0R2_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F0R2_FB22 CAN_F0R2_FB22_Msk /*!< Filter bit 22 */
+#define CAN_F0R2_FB23_Pos (23U)
+#define CAN_F0R2_FB23_Msk (0x1U << CAN_F0R2_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F0R2_FB23 CAN_F0R2_FB23_Msk /*!< Filter bit 23 */
+#define CAN_F0R2_FB24_Pos (24U)
+#define CAN_F0R2_FB24_Msk (0x1U << CAN_F0R2_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F0R2_FB24 CAN_F0R2_FB24_Msk /*!< Filter bit 24 */
+#define CAN_F0R2_FB25_Pos (25U)
+#define CAN_F0R2_FB25_Msk (0x1U << CAN_F0R2_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F0R2_FB25 CAN_F0R2_FB25_Msk /*!< Filter bit 25 */
+#define CAN_F0R2_FB26_Pos (26U)
+#define CAN_F0R2_FB26_Msk (0x1U << CAN_F0R2_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F0R2_FB26 CAN_F0R2_FB26_Msk /*!< Filter bit 26 */
+#define CAN_F0R2_FB27_Pos (27U)
+#define CAN_F0R2_FB27_Msk (0x1U << CAN_F0R2_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F0R2_FB27 CAN_F0R2_FB27_Msk /*!< Filter bit 27 */
+#define CAN_F0R2_FB28_Pos (28U)
+#define CAN_F0R2_FB28_Msk (0x1U << CAN_F0R2_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F0R2_FB28 CAN_F0R2_FB28_Msk /*!< Filter bit 28 */
+#define CAN_F0R2_FB29_Pos (29U)
+#define CAN_F0R2_FB29_Msk (0x1U << CAN_F0R2_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F0R2_FB29 CAN_F0R2_FB29_Msk /*!< Filter bit 29 */
+#define CAN_F0R2_FB30_Pos (30U)
+#define CAN_F0R2_FB30_Msk (0x1U << CAN_F0R2_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F0R2_FB30 CAN_F0R2_FB30_Msk /*!< Filter bit 30 */
+#define CAN_F0R2_FB31_Pos (31U)
+#define CAN_F0R2_FB31_Msk (0x1U << CAN_F0R2_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F0R2_FB31 CAN_F0R2_FB31_Msk /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F1R2 register *******************/
+#define CAN_F1R2_FB0_Pos (0U)
+#define CAN_F1R2_FB0_Msk (0x1U << CAN_F1R2_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F1R2_FB0 CAN_F1R2_FB0_Msk /*!< Filter bit 0 */
+#define CAN_F1R2_FB1_Pos (1U)
+#define CAN_F1R2_FB1_Msk (0x1U << CAN_F1R2_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F1R2_FB1 CAN_F1R2_FB1_Msk /*!< Filter bit 1 */
+#define CAN_F1R2_FB2_Pos (2U)
+#define CAN_F1R2_FB2_Msk (0x1U << CAN_F1R2_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F1R2_FB2 CAN_F1R2_FB2_Msk /*!< Filter bit 2 */
+#define CAN_F1R2_FB3_Pos (3U)
+#define CAN_F1R2_FB3_Msk (0x1U << CAN_F1R2_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F1R2_FB3 CAN_F1R2_FB3_Msk /*!< Filter bit 3 */
+#define CAN_F1R2_FB4_Pos (4U)
+#define CAN_F1R2_FB4_Msk (0x1U << CAN_F1R2_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F1R2_FB4 CAN_F1R2_FB4_Msk /*!< Filter bit 4 */
+#define CAN_F1R2_FB5_Pos (5U)
+#define CAN_F1R2_FB5_Msk (0x1U << CAN_F1R2_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F1R2_FB5 CAN_F1R2_FB5_Msk /*!< Filter bit 5 */
+#define CAN_F1R2_FB6_Pos (6U)
+#define CAN_F1R2_FB6_Msk (0x1U << CAN_F1R2_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F1R2_FB6 CAN_F1R2_FB6_Msk /*!< Filter bit 6 */
+#define CAN_F1R2_FB7_Pos (7U)
+#define CAN_F1R2_FB7_Msk (0x1U << CAN_F1R2_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F1R2_FB7 CAN_F1R2_FB7_Msk /*!< Filter bit 7 */
+#define CAN_F1R2_FB8_Pos (8U)
+#define CAN_F1R2_FB8_Msk (0x1U << CAN_F1R2_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F1R2_FB8 CAN_F1R2_FB8_Msk /*!< Filter bit 8 */
+#define CAN_F1R2_FB9_Pos (9U)
+#define CAN_F1R2_FB9_Msk (0x1U << CAN_F1R2_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F1R2_FB9 CAN_F1R2_FB9_Msk /*!< Filter bit 9 */
+#define CAN_F1R2_FB10_Pos (10U)
+#define CAN_F1R2_FB10_Msk (0x1U << CAN_F1R2_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F1R2_FB10 CAN_F1R2_FB10_Msk /*!< Filter bit 10 */
+#define CAN_F1R2_FB11_Pos (11U)
+#define CAN_F1R2_FB11_Msk (0x1U << CAN_F1R2_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F1R2_FB11 CAN_F1R2_FB11_Msk /*!< Filter bit 11 */
+#define CAN_F1R2_FB12_Pos (12U)
+#define CAN_F1R2_FB12_Msk (0x1U << CAN_F1R2_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F1R2_FB12 CAN_F1R2_FB12_Msk /*!< Filter bit 12 */
+#define CAN_F1R2_FB13_Pos (13U)
+#define CAN_F1R2_FB13_Msk (0x1U << CAN_F1R2_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F1R2_FB13 CAN_F1R2_FB13_Msk /*!< Filter bit 13 */
+#define CAN_F1R2_FB14_Pos (14U)
+#define CAN_F1R2_FB14_Msk (0x1U << CAN_F1R2_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F1R2_FB14 CAN_F1R2_FB14_Msk /*!< Filter bit 14 */
+#define CAN_F1R2_FB15_Pos (15U)
+#define CAN_F1R2_FB15_Msk (0x1U << CAN_F1R2_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F1R2_FB15 CAN_F1R2_FB15_Msk /*!< Filter bit 15 */
+#define CAN_F1R2_FB16_Pos (16U)
+#define CAN_F1R2_FB16_Msk (0x1U << CAN_F1R2_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F1R2_FB16 CAN_F1R2_FB16_Msk /*!< Filter bit 16 */
+#define CAN_F1R2_FB17_Pos (17U)
+#define CAN_F1R2_FB17_Msk (0x1U << CAN_F1R2_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F1R2_FB17 CAN_F1R2_FB17_Msk /*!< Filter bit 17 */
+#define CAN_F1R2_FB18_Pos (18U)
+#define CAN_F1R2_FB18_Msk (0x1U << CAN_F1R2_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F1R2_FB18 CAN_F1R2_FB18_Msk /*!< Filter bit 18 */
+#define CAN_F1R2_FB19_Pos (19U)
+#define CAN_F1R2_FB19_Msk (0x1U << CAN_F1R2_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F1R2_FB19 CAN_F1R2_FB19_Msk /*!< Filter bit 19 */
+#define CAN_F1R2_FB20_Pos (20U)
+#define CAN_F1R2_FB20_Msk (0x1U << CAN_F1R2_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F1R2_FB20 CAN_F1R2_FB20_Msk /*!< Filter bit 20 */
+#define CAN_F1R2_FB21_Pos (21U)
+#define CAN_F1R2_FB21_Msk (0x1U << CAN_F1R2_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F1R2_FB21 CAN_F1R2_FB21_Msk /*!< Filter bit 21 */
+#define CAN_F1R2_FB22_Pos (22U)
+#define CAN_F1R2_FB22_Msk (0x1U << CAN_F1R2_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F1R2_FB22 CAN_F1R2_FB22_Msk /*!< Filter bit 22 */
+#define CAN_F1R2_FB23_Pos (23U)
+#define CAN_F1R2_FB23_Msk (0x1U << CAN_F1R2_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F1R2_FB23 CAN_F1R2_FB23_Msk /*!< Filter bit 23 */
+#define CAN_F1R2_FB24_Pos (24U)
+#define CAN_F1R2_FB24_Msk (0x1U << CAN_F1R2_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F1R2_FB24 CAN_F1R2_FB24_Msk /*!< Filter bit 24 */
+#define CAN_F1R2_FB25_Pos (25U)
+#define CAN_F1R2_FB25_Msk (0x1U << CAN_F1R2_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F1R2_FB25 CAN_F1R2_FB25_Msk /*!< Filter bit 25 */
+#define CAN_F1R2_FB26_Pos (26U)
+#define CAN_F1R2_FB26_Msk (0x1U << CAN_F1R2_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F1R2_FB26 CAN_F1R2_FB26_Msk /*!< Filter bit 26 */
+#define CAN_F1R2_FB27_Pos (27U)
+#define CAN_F1R2_FB27_Msk (0x1U << CAN_F1R2_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F1R2_FB27 CAN_F1R2_FB27_Msk /*!< Filter bit 27 */
+#define CAN_F1R2_FB28_Pos (28U)
+#define CAN_F1R2_FB28_Msk (0x1U << CAN_F1R2_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F1R2_FB28 CAN_F1R2_FB28_Msk /*!< Filter bit 28 */
+#define CAN_F1R2_FB29_Pos (29U)
+#define CAN_F1R2_FB29_Msk (0x1U << CAN_F1R2_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F1R2_FB29 CAN_F1R2_FB29_Msk /*!< Filter bit 29 */
+#define CAN_F1R2_FB30_Pos (30U)
+#define CAN_F1R2_FB30_Msk (0x1U << CAN_F1R2_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F1R2_FB30 CAN_F1R2_FB30_Msk /*!< Filter bit 30 */
+#define CAN_F1R2_FB31_Pos (31U)
+#define CAN_F1R2_FB31_Msk (0x1U << CAN_F1R2_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F1R2_FB31 CAN_F1R2_FB31_Msk /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F2R2 register *******************/
+#define CAN_F2R2_FB0_Pos (0U)
+#define CAN_F2R2_FB0_Msk (0x1U << CAN_F2R2_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F2R2_FB0 CAN_F2R2_FB0_Msk /*!< Filter bit 0 */
+#define CAN_F2R2_FB1_Pos (1U)
+#define CAN_F2R2_FB1_Msk (0x1U << CAN_F2R2_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F2R2_FB1 CAN_F2R2_FB1_Msk /*!< Filter bit 1 */
+#define CAN_F2R2_FB2_Pos (2U)
+#define CAN_F2R2_FB2_Msk (0x1U << CAN_F2R2_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F2R2_FB2 CAN_F2R2_FB2_Msk /*!< Filter bit 2 */
+#define CAN_F2R2_FB3_Pos (3U)
+#define CAN_F2R2_FB3_Msk (0x1U << CAN_F2R2_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F2R2_FB3 CAN_F2R2_FB3_Msk /*!< Filter bit 3 */
+#define CAN_F2R2_FB4_Pos (4U)
+#define CAN_F2R2_FB4_Msk (0x1U << CAN_F2R2_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F2R2_FB4 CAN_F2R2_FB4_Msk /*!< Filter bit 4 */
+#define CAN_F2R2_FB5_Pos (5U)
+#define CAN_F2R2_FB5_Msk (0x1U << CAN_F2R2_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F2R2_FB5 CAN_F2R2_FB5_Msk /*!< Filter bit 5 */
+#define CAN_F2R2_FB6_Pos (6U)
+#define CAN_F2R2_FB6_Msk (0x1U << CAN_F2R2_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F2R2_FB6 CAN_F2R2_FB6_Msk /*!< Filter bit 6 */
+#define CAN_F2R2_FB7_Pos (7U)
+#define CAN_F2R2_FB7_Msk (0x1U << CAN_F2R2_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F2R2_FB7 CAN_F2R2_FB7_Msk /*!< Filter bit 7 */
+#define CAN_F2R2_FB8_Pos (8U)
+#define CAN_F2R2_FB8_Msk (0x1U << CAN_F2R2_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F2R2_FB8 CAN_F2R2_FB8_Msk /*!< Filter bit 8 */
+#define CAN_F2R2_FB9_Pos (9U)
+#define CAN_F2R2_FB9_Msk (0x1U << CAN_F2R2_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F2R2_FB9 CAN_F2R2_FB9_Msk /*!< Filter bit 9 */
+#define CAN_F2R2_FB10_Pos (10U)
+#define CAN_F2R2_FB10_Msk (0x1U << CAN_F2R2_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F2R2_FB10 CAN_F2R2_FB10_Msk /*!< Filter bit 10 */
+#define CAN_F2R2_FB11_Pos (11U)
+#define CAN_F2R2_FB11_Msk (0x1U << CAN_F2R2_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F2R2_FB11 CAN_F2R2_FB11_Msk /*!< Filter bit 11 */
+#define CAN_F2R2_FB12_Pos (12U)
+#define CAN_F2R2_FB12_Msk (0x1U << CAN_F2R2_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F2R2_FB12 CAN_F2R2_FB12_Msk /*!< Filter bit 12 */
+#define CAN_F2R2_FB13_Pos (13U)
+#define CAN_F2R2_FB13_Msk (0x1U << CAN_F2R2_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F2R2_FB13 CAN_F2R2_FB13_Msk /*!< Filter bit 13 */
+#define CAN_F2R2_FB14_Pos (14U)
+#define CAN_F2R2_FB14_Msk (0x1U << CAN_F2R2_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F2R2_FB14 CAN_F2R2_FB14_Msk /*!< Filter bit 14 */
+#define CAN_F2R2_FB15_Pos (15U)
+#define CAN_F2R2_FB15_Msk (0x1U << CAN_F2R2_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F2R2_FB15 CAN_F2R2_FB15_Msk /*!< Filter bit 15 */
+#define CAN_F2R2_FB16_Pos (16U)
+#define CAN_F2R2_FB16_Msk (0x1U << CAN_F2R2_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F2R2_FB16 CAN_F2R2_FB16_Msk /*!< Filter bit 16 */
+#define CAN_F2R2_FB17_Pos (17U)
+#define CAN_F2R2_FB17_Msk (0x1U << CAN_F2R2_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F2R2_FB17 CAN_F2R2_FB17_Msk /*!< Filter bit 17 */
+#define CAN_F2R2_FB18_Pos (18U)
+#define CAN_F2R2_FB18_Msk (0x1U << CAN_F2R2_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F2R2_FB18 CAN_F2R2_FB18_Msk /*!< Filter bit 18 */
+#define CAN_F2R2_FB19_Pos (19U)
+#define CAN_F2R2_FB19_Msk (0x1U << CAN_F2R2_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F2R2_FB19 CAN_F2R2_FB19_Msk /*!< Filter bit 19 */
+#define CAN_F2R2_FB20_Pos (20U)
+#define CAN_F2R2_FB20_Msk (0x1U << CAN_F2R2_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F2R2_FB20 CAN_F2R2_FB20_Msk /*!< Filter bit 20 */
+#define CAN_F2R2_FB21_Pos (21U)
+#define CAN_F2R2_FB21_Msk (0x1U << CAN_F2R2_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F2R2_FB21 CAN_F2R2_FB21_Msk /*!< Filter bit 21 */
+#define CAN_F2R2_FB22_Pos (22U)
+#define CAN_F2R2_FB22_Msk (0x1U << CAN_F2R2_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F2R2_FB22 CAN_F2R2_FB22_Msk /*!< Filter bit 22 */
+#define CAN_F2R2_FB23_Pos (23U)
+#define CAN_F2R2_FB23_Msk (0x1U << CAN_F2R2_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F2R2_FB23 CAN_F2R2_FB23_Msk /*!< Filter bit 23 */
+#define CAN_F2R2_FB24_Pos (24U)
+#define CAN_F2R2_FB24_Msk (0x1U << CAN_F2R2_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F2R2_FB24 CAN_F2R2_FB24_Msk /*!< Filter bit 24 */
+#define CAN_F2R2_FB25_Pos (25U)
+#define CAN_F2R2_FB25_Msk (0x1U << CAN_F2R2_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F2R2_FB25 CAN_F2R2_FB25_Msk /*!< Filter bit 25 */
+#define CAN_F2R2_FB26_Pos (26U)
+#define CAN_F2R2_FB26_Msk (0x1U << CAN_F2R2_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F2R2_FB26 CAN_F2R2_FB26_Msk /*!< Filter bit 26 */
+#define CAN_F2R2_FB27_Pos (27U)
+#define CAN_F2R2_FB27_Msk (0x1U << CAN_F2R2_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F2R2_FB27 CAN_F2R2_FB27_Msk /*!< Filter bit 27 */
+#define CAN_F2R2_FB28_Pos (28U)
+#define CAN_F2R2_FB28_Msk (0x1U << CAN_F2R2_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F2R2_FB28 CAN_F2R2_FB28_Msk /*!< Filter bit 28 */
+#define CAN_F2R2_FB29_Pos (29U)
+#define CAN_F2R2_FB29_Msk (0x1U << CAN_F2R2_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F2R2_FB29 CAN_F2R2_FB29_Msk /*!< Filter bit 29 */
+#define CAN_F2R2_FB30_Pos (30U)
+#define CAN_F2R2_FB30_Msk (0x1U << CAN_F2R2_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F2R2_FB30 CAN_F2R2_FB30_Msk /*!< Filter bit 30 */
+#define CAN_F2R2_FB31_Pos (31U)
+#define CAN_F2R2_FB31_Msk (0x1U << CAN_F2R2_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F2R2_FB31 CAN_F2R2_FB31_Msk /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F3R2 register *******************/
+#define CAN_F3R2_FB0_Pos (0U)
+#define CAN_F3R2_FB0_Msk (0x1U << CAN_F3R2_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F3R2_FB0 CAN_F3R2_FB0_Msk /*!< Filter bit 0 */
+#define CAN_F3R2_FB1_Pos (1U)
+#define CAN_F3R2_FB1_Msk (0x1U << CAN_F3R2_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F3R2_FB1 CAN_F3R2_FB1_Msk /*!< Filter bit 1 */
+#define CAN_F3R2_FB2_Pos (2U)
+#define CAN_F3R2_FB2_Msk (0x1U << CAN_F3R2_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F3R2_FB2 CAN_F3R2_FB2_Msk /*!< Filter bit 2 */
+#define CAN_F3R2_FB3_Pos (3U)
+#define CAN_F3R2_FB3_Msk (0x1U << CAN_F3R2_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F3R2_FB3 CAN_F3R2_FB3_Msk /*!< Filter bit 3 */
+#define CAN_F3R2_FB4_Pos (4U)
+#define CAN_F3R2_FB4_Msk (0x1U << CAN_F3R2_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F3R2_FB4 CAN_F3R2_FB4_Msk /*!< Filter bit 4 */
+#define CAN_F3R2_FB5_Pos (5U)
+#define CAN_F3R2_FB5_Msk (0x1U << CAN_F3R2_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F3R2_FB5 CAN_F3R2_FB5_Msk /*!< Filter bit 5 */
+#define CAN_F3R2_FB6_Pos (6U)
+#define CAN_F3R2_FB6_Msk (0x1U << CAN_F3R2_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F3R2_FB6 CAN_F3R2_FB6_Msk /*!< Filter bit 6 */
+#define CAN_F3R2_FB7_Pos (7U)
+#define CAN_F3R2_FB7_Msk (0x1U << CAN_F3R2_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F3R2_FB7 CAN_F3R2_FB7_Msk /*!< Filter bit 7 */
+#define CAN_F3R2_FB8_Pos (8U)
+#define CAN_F3R2_FB8_Msk (0x1U << CAN_F3R2_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F3R2_FB8 CAN_F3R2_FB8_Msk /*!< Filter bit 8 */
+#define CAN_F3R2_FB9_Pos (9U)
+#define CAN_F3R2_FB9_Msk (0x1U << CAN_F3R2_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F3R2_FB9 CAN_F3R2_FB9_Msk /*!< Filter bit 9 */
+#define CAN_F3R2_FB10_Pos (10U)
+#define CAN_F3R2_FB10_Msk (0x1U << CAN_F3R2_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F3R2_FB10 CAN_F3R2_FB10_Msk /*!< Filter bit 10 */
+#define CAN_F3R2_FB11_Pos (11U)
+#define CAN_F3R2_FB11_Msk (0x1U << CAN_F3R2_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F3R2_FB11 CAN_F3R2_FB11_Msk /*!< Filter bit 11 */
+#define CAN_F3R2_FB12_Pos (12U)
+#define CAN_F3R2_FB12_Msk (0x1U << CAN_F3R2_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F3R2_FB12 CAN_F3R2_FB12_Msk /*!< Filter bit 12 */
+#define CAN_F3R2_FB13_Pos (13U)
+#define CAN_F3R2_FB13_Msk (0x1U << CAN_F3R2_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F3R2_FB13 CAN_F3R2_FB13_Msk /*!< Filter bit 13 */
+#define CAN_F3R2_FB14_Pos (14U)
+#define CAN_F3R2_FB14_Msk (0x1U << CAN_F3R2_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F3R2_FB14 CAN_F3R2_FB14_Msk /*!< Filter bit 14 */
+#define CAN_F3R2_FB15_Pos (15U)
+#define CAN_F3R2_FB15_Msk (0x1U << CAN_F3R2_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F3R2_FB15 CAN_F3R2_FB15_Msk /*!< Filter bit 15 */
+#define CAN_F3R2_FB16_Pos (16U)
+#define CAN_F3R2_FB16_Msk (0x1U << CAN_F3R2_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F3R2_FB16 CAN_F3R2_FB16_Msk /*!< Filter bit 16 */
+#define CAN_F3R2_FB17_Pos (17U)
+#define CAN_F3R2_FB17_Msk (0x1U << CAN_F3R2_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F3R2_FB17 CAN_F3R2_FB17_Msk /*!< Filter bit 17 */
+#define CAN_F3R2_FB18_Pos (18U)
+#define CAN_F3R2_FB18_Msk (0x1U << CAN_F3R2_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F3R2_FB18 CAN_F3R2_FB18_Msk /*!< Filter bit 18 */
+#define CAN_F3R2_FB19_Pos (19U)
+#define CAN_F3R2_FB19_Msk (0x1U << CAN_F3R2_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F3R2_FB19 CAN_F3R2_FB19_Msk /*!< Filter bit 19 */
+#define CAN_F3R2_FB20_Pos (20U)
+#define CAN_F3R2_FB20_Msk (0x1U << CAN_F3R2_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F3R2_FB20 CAN_F3R2_FB20_Msk /*!< Filter bit 20 */
+#define CAN_F3R2_FB21_Pos (21U)
+#define CAN_F3R2_FB21_Msk (0x1U << CAN_F3R2_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F3R2_FB21 CAN_F3R2_FB21_Msk /*!< Filter bit 21 */
+#define CAN_F3R2_FB22_Pos (22U)
+#define CAN_F3R2_FB22_Msk (0x1U << CAN_F3R2_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F3R2_FB22 CAN_F3R2_FB22_Msk /*!< Filter bit 22 */
+#define CAN_F3R2_FB23_Pos (23U)
+#define CAN_F3R2_FB23_Msk (0x1U << CAN_F3R2_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F3R2_FB23 CAN_F3R2_FB23_Msk /*!< Filter bit 23 */
+#define CAN_F3R2_FB24_Pos (24U)
+#define CAN_F3R2_FB24_Msk (0x1U << CAN_F3R2_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F3R2_FB24 CAN_F3R2_FB24_Msk /*!< Filter bit 24 */
+#define CAN_F3R2_FB25_Pos (25U)
+#define CAN_F3R2_FB25_Msk (0x1U << CAN_F3R2_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F3R2_FB25 CAN_F3R2_FB25_Msk /*!< Filter bit 25 */
+#define CAN_F3R2_FB26_Pos (26U)
+#define CAN_F3R2_FB26_Msk (0x1U << CAN_F3R2_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F3R2_FB26 CAN_F3R2_FB26_Msk /*!< Filter bit 26 */
+#define CAN_F3R2_FB27_Pos (27U)
+#define CAN_F3R2_FB27_Msk (0x1U << CAN_F3R2_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F3R2_FB27 CAN_F3R2_FB27_Msk /*!< Filter bit 27 */
+#define CAN_F3R2_FB28_Pos (28U)
+#define CAN_F3R2_FB28_Msk (0x1U << CAN_F3R2_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F3R2_FB28 CAN_F3R2_FB28_Msk /*!< Filter bit 28 */
+#define CAN_F3R2_FB29_Pos (29U)
+#define CAN_F3R2_FB29_Msk (0x1U << CAN_F3R2_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F3R2_FB29 CAN_F3R2_FB29_Msk /*!< Filter bit 29 */
+#define CAN_F3R2_FB30_Pos (30U)
+#define CAN_F3R2_FB30_Msk (0x1U << CAN_F3R2_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F3R2_FB30 CAN_F3R2_FB30_Msk /*!< Filter bit 30 */
+#define CAN_F3R2_FB31_Pos (31U)
+#define CAN_F3R2_FB31_Msk (0x1U << CAN_F3R2_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F3R2_FB31 CAN_F3R2_FB31_Msk /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F4R2 register *******************/
+#define CAN_F4R2_FB0_Pos (0U)
+#define CAN_F4R2_FB0_Msk (0x1U << CAN_F4R2_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F4R2_FB0 CAN_F4R2_FB0_Msk /*!< Filter bit 0 */
+#define CAN_F4R2_FB1_Pos (1U)
+#define CAN_F4R2_FB1_Msk (0x1U << CAN_F4R2_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F4R2_FB1 CAN_F4R2_FB1_Msk /*!< Filter bit 1 */
+#define CAN_F4R2_FB2_Pos (2U)
+#define CAN_F4R2_FB2_Msk (0x1U << CAN_F4R2_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F4R2_FB2 CAN_F4R2_FB2_Msk /*!< Filter bit 2 */
+#define CAN_F4R2_FB3_Pos (3U)
+#define CAN_F4R2_FB3_Msk (0x1U << CAN_F4R2_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F4R2_FB3 CAN_F4R2_FB3_Msk /*!< Filter bit 3 */
+#define CAN_F4R2_FB4_Pos (4U)
+#define CAN_F4R2_FB4_Msk (0x1U << CAN_F4R2_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F4R2_FB4 CAN_F4R2_FB4_Msk /*!< Filter bit 4 */
+#define CAN_F4R2_FB5_Pos (5U)
+#define CAN_F4R2_FB5_Msk (0x1U << CAN_F4R2_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F4R2_FB5 CAN_F4R2_FB5_Msk /*!< Filter bit 5 */
+#define CAN_F4R2_FB6_Pos (6U)
+#define CAN_F4R2_FB6_Msk (0x1U << CAN_F4R2_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F4R2_FB6 CAN_F4R2_FB6_Msk /*!< Filter bit 6 */
+#define CAN_F4R2_FB7_Pos (7U)
+#define CAN_F4R2_FB7_Msk (0x1U << CAN_F4R2_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F4R2_FB7 CAN_F4R2_FB7_Msk /*!< Filter bit 7 */
+#define CAN_F4R2_FB8_Pos (8U)
+#define CAN_F4R2_FB8_Msk (0x1U << CAN_F4R2_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F4R2_FB8 CAN_F4R2_FB8_Msk /*!< Filter bit 8 */
+#define CAN_F4R2_FB9_Pos (9U)
+#define CAN_F4R2_FB9_Msk (0x1U << CAN_F4R2_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F4R2_FB9 CAN_F4R2_FB9_Msk /*!< Filter bit 9 */
+#define CAN_F4R2_FB10_Pos (10U)
+#define CAN_F4R2_FB10_Msk (0x1U << CAN_F4R2_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F4R2_FB10 CAN_F4R2_FB10_Msk /*!< Filter bit 10 */
+#define CAN_F4R2_FB11_Pos (11U)
+#define CAN_F4R2_FB11_Msk (0x1U << CAN_F4R2_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F4R2_FB11 CAN_F4R2_FB11_Msk /*!< Filter bit 11 */
+#define CAN_F4R2_FB12_Pos (12U)
+#define CAN_F4R2_FB12_Msk (0x1U << CAN_F4R2_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F4R2_FB12 CAN_F4R2_FB12_Msk /*!< Filter bit 12 */
+#define CAN_F4R2_FB13_Pos (13U)
+#define CAN_F4R2_FB13_Msk (0x1U << CAN_F4R2_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F4R2_FB13 CAN_F4R2_FB13_Msk /*!< Filter bit 13 */
+#define CAN_F4R2_FB14_Pos (14U)
+#define CAN_F4R2_FB14_Msk (0x1U << CAN_F4R2_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F4R2_FB14 CAN_F4R2_FB14_Msk /*!< Filter bit 14 */
+#define CAN_F4R2_FB15_Pos (15U)
+#define CAN_F4R2_FB15_Msk (0x1U << CAN_F4R2_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F4R2_FB15 CAN_F4R2_FB15_Msk /*!< Filter bit 15 */
+#define CAN_F4R2_FB16_Pos (16U)
+#define CAN_F4R2_FB16_Msk (0x1U << CAN_F4R2_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F4R2_FB16 CAN_F4R2_FB16_Msk /*!< Filter bit 16 */
+#define CAN_F4R2_FB17_Pos (17U)
+#define CAN_F4R2_FB17_Msk (0x1U << CAN_F4R2_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F4R2_FB17 CAN_F4R2_FB17_Msk /*!< Filter bit 17 */
+#define CAN_F4R2_FB18_Pos (18U)
+#define CAN_F4R2_FB18_Msk (0x1U << CAN_F4R2_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F4R2_FB18 CAN_F4R2_FB18_Msk /*!< Filter bit 18 */
+#define CAN_F4R2_FB19_Pos (19U)
+#define CAN_F4R2_FB19_Msk (0x1U << CAN_F4R2_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F4R2_FB19 CAN_F4R2_FB19_Msk /*!< Filter bit 19 */
+#define CAN_F4R2_FB20_Pos (20U)
+#define CAN_F4R2_FB20_Msk (0x1U << CAN_F4R2_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F4R2_FB20 CAN_F4R2_FB20_Msk /*!< Filter bit 20 */
+#define CAN_F4R2_FB21_Pos (21U)
+#define CAN_F4R2_FB21_Msk (0x1U << CAN_F4R2_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F4R2_FB21 CAN_F4R2_FB21_Msk /*!< Filter bit 21 */
+#define CAN_F4R2_FB22_Pos (22U)
+#define CAN_F4R2_FB22_Msk (0x1U << CAN_F4R2_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F4R2_FB22 CAN_F4R2_FB22_Msk /*!< Filter bit 22 */
+#define CAN_F4R2_FB23_Pos (23U)
+#define CAN_F4R2_FB23_Msk (0x1U << CAN_F4R2_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F4R2_FB23 CAN_F4R2_FB23_Msk /*!< Filter bit 23 */
+#define CAN_F4R2_FB24_Pos (24U)
+#define CAN_F4R2_FB24_Msk (0x1U << CAN_F4R2_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F4R2_FB24 CAN_F4R2_FB24_Msk /*!< Filter bit 24 */
+#define CAN_F4R2_FB25_Pos (25U)
+#define CAN_F4R2_FB25_Msk (0x1U << CAN_F4R2_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F4R2_FB25 CAN_F4R2_FB25_Msk /*!< Filter bit 25 */
+#define CAN_F4R2_FB26_Pos (26U)
+#define CAN_F4R2_FB26_Msk (0x1U << CAN_F4R2_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F4R2_FB26 CAN_F4R2_FB26_Msk /*!< Filter bit 26 */
+#define CAN_F4R2_FB27_Pos (27U)
+#define CAN_F4R2_FB27_Msk (0x1U << CAN_F4R2_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F4R2_FB27 CAN_F4R2_FB27_Msk /*!< Filter bit 27 */
+#define CAN_F4R2_FB28_Pos (28U)
+#define CAN_F4R2_FB28_Msk (0x1U << CAN_F4R2_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F4R2_FB28 CAN_F4R2_FB28_Msk /*!< Filter bit 28 */
+#define CAN_F4R2_FB29_Pos (29U)
+#define CAN_F4R2_FB29_Msk (0x1U << CAN_F4R2_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F4R2_FB29 CAN_F4R2_FB29_Msk /*!< Filter bit 29 */
+#define CAN_F4R2_FB30_Pos (30U)
+#define CAN_F4R2_FB30_Msk (0x1U << CAN_F4R2_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F4R2_FB30 CAN_F4R2_FB30_Msk /*!< Filter bit 30 */
+#define CAN_F4R2_FB31_Pos (31U)
+#define CAN_F4R2_FB31_Msk (0x1U << CAN_F4R2_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F4R2_FB31 CAN_F4R2_FB31_Msk /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F5R2 register *******************/
+#define CAN_F5R2_FB0_Pos (0U)
+#define CAN_F5R2_FB0_Msk (0x1U << CAN_F5R2_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F5R2_FB0 CAN_F5R2_FB0_Msk /*!< Filter bit 0 */
+#define CAN_F5R2_FB1_Pos (1U)
+#define CAN_F5R2_FB1_Msk (0x1U << CAN_F5R2_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F5R2_FB1 CAN_F5R2_FB1_Msk /*!< Filter bit 1 */
+#define CAN_F5R2_FB2_Pos (2U)
+#define CAN_F5R2_FB2_Msk (0x1U << CAN_F5R2_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F5R2_FB2 CAN_F5R2_FB2_Msk /*!< Filter bit 2 */
+#define CAN_F5R2_FB3_Pos (3U)
+#define CAN_F5R2_FB3_Msk (0x1U << CAN_F5R2_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F5R2_FB3 CAN_F5R2_FB3_Msk /*!< Filter bit 3 */
+#define CAN_F5R2_FB4_Pos (4U)
+#define CAN_F5R2_FB4_Msk (0x1U << CAN_F5R2_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F5R2_FB4 CAN_F5R2_FB4_Msk /*!< Filter bit 4 */
+#define CAN_F5R2_FB5_Pos (5U)
+#define CAN_F5R2_FB5_Msk (0x1U << CAN_F5R2_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F5R2_FB5 CAN_F5R2_FB5_Msk /*!< Filter bit 5 */
+#define CAN_F5R2_FB6_Pos (6U)
+#define CAN_F5R2_FB6_Msk (0x1U << CAN_F5R2_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F5R2_FB6 CAN_F5R2_FB6_Msk /*!< Filter bit 6 */
+#define CAN_F5R2_FB7_Pos (7U)
+#define CAN_F5R2_FB7_Msk (0x1U << CAN_F5R2_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F5R2_FB7 CAN_F5R2_FB7_Msk /*!< Filter bit 7 */
+#define CAN_F5R2_FB8_Pos (8U)
+#define CAN_F5R2_FB8_Msk (0x1U << CAN_F5R2_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F5R2_FB8 CAN_F5R2_FB8_Msk /*!< Filter bit 8 */
+#define CAN_F5R2_FB9_Pos (9U)
+#define CAN_F5R2_FB9_Msk (0x1U << CAN_F5R2_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F5R2_FB9 CAN_F5R2_FB9_Msk /*!< Filter bit 9 */
+#define CAN_F5R2_FB10_Pos (10U)
+#define CAN_F5R2_FB10_Msk (0x1U << CAN_F5R2_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F5R2_FB10 CAN_F5R2_FB10_Msk /*!< Filter bit 10 */
+#define CAN_F5R2_FB11_Pos (11U)
+#define CAN_F5R2_FB11_Msk (0x1U << CAN_F5R2_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F5R2_FB11 CAN_F5R2_FB11_Msk /*!< Filter bit 11 */
+#define CAN_F5R2_FB12_Pos (12U)
+#define CAN_F5R2_FB12_Msk (0x1U << CAN_F5R2_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F5R2_FB12 CAN_F5R2_FB12_Msk /*!< Filter bit 12 */
+#define CAN_F5R2_FB13_Pos (13U)
+#define CAN_F5R2_FB13_Msk (0x1U << CAN_F5R2_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F5R2_FB13 CAN_F5R2_FB13_Msk /*!< Filter bit 13 */
+#define CAN_F5R2_FB14_Pos (14U)
+#define CAN_F5R2_FB14_Msk (0x1U << CAN_F5R2_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F5R2_FB14 CAN_F5R2_FB14_Msk /*!< Filter bit 14 */
+#define CAN_F5R2_FB15_Pos (15U)
+#define CAN_F5R2_FB15_Msk (0x1U << CAN_F5R2_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F5R2_FB15 CAN_F5R2_FB15_Msk /*!< Filter bit 15 */
+#define CAN_F5R2_FB16_Pos (16U)
+#define CAN_F5R2_FB16_Msk (0x1U << CAN_F5R2_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F5R2_FB16 CAN_F5R2_FB16_Msk /*!< Filter bit 16 */
+#define CAN_F5R2_FB17_Pos (17U)
+#define CAN_F5R2_FB17_Msk (0x1U << CAN_F5R2_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F5R2_FB17 CAN_F5R2_FB17_Msk /*!< Filter bit 17 */
+#define CAN_F5R2_FB18_Pos (18U)
+#define CAN_F5R2_FB18_Msk (0x1U << CAN_F5R2_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F5R2_FB18 CAN_F5R2_FB18_Msk /*!< Filter bit 18 */
+#define CAN_F5R2_FB19_Pos (19U)
+#define CAN_F5R2_FB19_Msk (0x1U << CAN_F5R2_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F5R2_FB19 CAN_F5R2_FB19_Msk /*!< Filter bit 19 */
+#define CAN_F5R2_FB20_Pos (20U)
+#define CAN_F5R2_FB20_Msk (0x1U << CAN_F5R2_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F5R2_FB20 CAN_F5R2_FB20_Msk /*!< Filter bit 20 */
+#define CAN_F5R2_FB21_Pos (21U)
+#define CAN_F5R2_FB21_Msk (0x1U << CAN_F5R2_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F5R2_FB21 CAN_F5R2_FB21_Msk /*!< Filter bit 21 */
+#define CAN_F5R2_FB22_Pos (22U)
+#define CAN_F5R2_FB22_Msk (0x1U << CAN_F5R2_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F5R2_FB22 CAN_F5R2_FB22_Msk /*!< Filter bit 22 */
+#define CAN_F5R2_FB23_Pos (23U)
+#define CAN_F5R2_FB23_Msk (0x1U << CAN_F5R2_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F5R2_FB23 CAN_F5R2_FB23_Msk /*!< Filter bit 23 */
+#define CAN_F5R2_FB24_Pos (24U)
+#define CAN_F5R2_FB24_Msk (0x1U << CAN_F5R2_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F5R2_FB24 CAN_F5R2_FB24_Msk /*!< Filter bit 24 */
+#define CAN_F5R2_FB25_Pos (25U)
+#define CAN_F5R2_FB25_Msk (0x1U << CAN_F5R2_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F5R2_FB25 CAN_F5R2_FB25_Msk /*!< Filter bit 25 */
+#define CAN_F5R2_FB26_Pos (26U)
+#define CAN_F5R2_FB26_Msk (0x1U << CAN_F5R2_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F5R2_FB26 CAN_F5R2_FB26_Msk /*!< Filter bit 26 */
+#define CAN_F5R2_FB27_Pos (27U)
+#define CAN_F5R2_FB27_Msk (0x1U << CAN_F5R2_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F5R2_FB27 CAN_F5R2_FB27_Msk /*!< Filter bit 27 */
+#define CAN_F5R2_FB28_Pos (28U)
+#define CAN_F5R2_FB28_Msk (0x1U << CAN_F5R2_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F5R2_FB28 CAN_F5R2_FB28_Msk /*!< Filter bit 28 */
+#define CAN_F5R2_FB29_Pos (29U)
+#define CAN_F5R2_FB29_Msk (0x1U << CAN_F5R2_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F5R2_FB29 CAN_F5R2_FB29_Msk /*!< Filter bit 29 */
+#define CAN_F5R2_FB30_Pos (30U)
+#define CAN_F5R2_FB30_Msk (0x1U << CAN_F5R2_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F5R2_FB30 CAN_F5R2_FB30_Msk /*!< Filter bit 30 */
+#define CAN_F5R2_FB31_Pos (31U)
+#define CAN_F5R2_FB31_Msk (0x1U << CAN_F5R2_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F5R2_FB31 CAN_F5R2_FB31_Msk /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F6R2 register *******************/
+#define CAN_F6R2_FB0_Pos (0U)
+#define CAN_F6R2_FB0_Msk (0x1U << CAN_F6R2_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F6R2_FB0 CAN_F6R2_FB0_Msk /*!< Filter bit 0 */
+#define CAN_F6R2_FB1_Pos (1U)
+#define CAN_F6R2_FB1_Msk (0x1U << CAN_F6R2_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F6R2_FB1 CAN_F6R2_FB1_Msk /*!< Filter bit 1 */
+#define CAN_F6R2_FB2_Pos (2U)
+#define CAN_F6R2_FB2_Msk (0x1U << CAN_F6R2_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F6R2_FB2 CAN_F6R2_FB2_Msk /*!< Filter bit 2 */
+#define CAN_F6R2_FB3_Pos (3U)
+#define CAN_F6R2_FB3_Msk (0x1U << CAN_F6R2_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F6R2_FB3 CAN_F6R2_FB3_Msk /*!< Filter bit 3 */
+#define CAN_F6R2_FB4_Pos (4U)
+#define CAN_F6R2_FB4_Msk (0x1U << CAN_F6R2_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F6R2_FB4 CAN_F6R2_FB4_Msk /*!< Filter bit 4 */
+#define CAN_F6R2_FB5_Pos (5U)
+#define CAN_F6R2_FB5_Msk (0x1U << CAN_F6R2_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F6R2_FB5 CAN_F6R2_FB5_Msk /*!< Filter bit 5 */
+#define CAN_F6R2_FB6_Pos (6U)
+#define CAN_F6R2_FB6_Msk (0x1U << CAN_F6R2_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F6R2_FB6 CAN_F6R2_FB6_Msk /*!< Filter bit 6 */
+#define CAN_F6R2_FB7_Pos (7U)
+#define CAN_F6R2_FB7_Msk (0x1U << CAN_F6R2_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F6R2_FB7 CAN_F6R2_FB7_Msk /*!< Filter bit 7 */
+#define CAN_F6R2_FB8_Pos (8U)
+#define CAN_F6R2_FB8_Msk (0x1U << CAN_F6R2_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F6R2_FB8 CAN_F6R2_FB8_Msk /*!< Filter bit 8 */
+#define CAN_F6R2_FB9_Pos (9U)
+#define CAN_F6R2_FB9_Msk (0x1U << CAN_F6R2_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F6R2_FB9 CAN_F6R2_FB9_Msk /*!< Filter bit 9 */
+#define CAN_F6R2_FB10_Pos (10U)
+#define CAN_F6R2_FB10_Msk (0x1U << CAN_F6R2_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F6R2_FB10 CAN_F6R2_FB10_Msk /*!< Filter bit 10 */
+#define CAN_F6R2_FB11_Pos (11U)
+#define CAN_F6R2_FB11_Msk (0x1U << CAN_F6R2_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F6R2_FB11 CAN_F6R2_FB11_Msk /*!< Filter bit 11 */
+#define CAN_F6R2_FB12_Pos (12U)
+#define CAN_F6R2_FB12_Msk (0x1U << CAN_F6R2_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F6R2_FB12 CAN_F6R2_FB12_Msk /*!< Filter bit 12 */
+#define CAN_F6R2_FB13_Pos (13U)
+#define CAN_F6R2_FB13_Msk (0x1U << CAN_F6R2_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F6R2_FB13 CAN_F6R2_FB13_Msk /*!< Filter bit 13 */
+#define CAN_F6R2_FB14_Pos (14U)
+#define CAN_F6R2_FB14_Msk (0x1U << CAN_F6R2_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F6R2_FB14 CAN_F6R2_FB14_Msk /*!< Filter bit 14 */
+#define CAN_F6R2_FB15_Pos (15U)
+#define CAN_F6R2_FB15_Msk (0x1U << CAN_F6R2_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F6R2_FB15 CAN_F6R2_FB15_Msk /*!< Filter bit 15 */
+#define CAN_F6R2_FB16_Pos (16U)
+#define CAN_F6R2_FB16_Msk (0x1U << CAN_F6R2_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F6R2_FB16 CAN_F6R2_FB16_Msk /*!< Filter bit 16 */
+#define CAN_F6R2_FB17_Pos (17U)
+#define CAN_F6R2_FB17_Msk (0x1U << CAN_F6R2_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F6R2_FB17 CAN_F6R2_FB17_Msk /*!< Filter bit 17 */
+#define CAN_F6R2_FB18_Pos (18U)
+#define CAN_F6R2_FB18_Msk (0x1U << CAN_F6R2_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F6R2_FB18 CAN_F6R2_FB18_Msk /*!< Filter bit 18 */
+#define CAN_F6R2_FB19_Pos (19U)
+#define CAN_F6R2_FB19_Msk (0x1U << CAN_F6R2_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F6R2_FB19 CAN_F6R2_FB19_Msk /*!< Filter bit 19 */
+#define CAN_F6R2_FB20_Pos (20U)
+#define CAN_F6R2_FB20_Msk (0x1U << CAN_F6R2_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F6R2_FB20 CAN_F6R2_FB20_Msk /*!< Filter bit 20 */
+#define CAN_F6R2_FB21_Pos (21U)
+#define CAN_F6R2_FB21_Msk (0x1U << CAN_F6R2_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F6R2_FB21 CAN_F6R2_FB21_Msk /*!< Filter bit 21 */
+#define CAN_F6R2_FB22_Pos (22U)
+#define CAN_F6R2_FB22_Msk (0x1U << CAN_F6R2_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F6R2_FB22 CAN_F6R2_FB22_Msk /*!< Filter bit 22 */
+#define CAN_F6R2_FB23_Pos (23U)
+#define CAN_F6R2_FB23_Msk (0x1U << CAN_F6R2_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F6R2_FB23 CAN_F6R2_FB23_Msk /*!< Filter bit 23 */
+#define CAN_F6R2_FB24_Pos (24U)
+#define CAN_F6R2_FB24_Msk (0x1U << CAN_F6R2_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F6R2_FB24 CAN_F6R2_FB24_Msk /*!< Filter bit 24 */
+#define CAN_F6R2_FB25_Pos (25U)
+#define CAN_F6R2_FB25_Msk (0x1U << CAN_F6R2_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F6R2_FB25 CAN_F6R2_FB25_Msk /*!< Filter bit 25 */
+#define CAN_F6R2_FB26_Pos (26U)
+#define CAN_F6R2_FB26_Msk (0x1U << CAN_F6R2_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F6R2_FB26 CAN_F6R2_FB26_Msk /*!< Filter bit 26 */
+#define CAN_F6R2_FB27_Pos (27U)
+#define CAN_F6R2_FB27_Msk (0x1U << CAN_F6R2_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F6R2_FB27 CAN_F6R2_FB27_Msk /*!< Filter bit 27 */
+#define CAN_F6R2_FB28_Pos (28U)
+#define CAN_F6R2_FB28_Msk (0x1U << CAN_F6R2_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F6R2_FB28 CAN_F6R2_FB28_Msk /*!< Filter bit 28 */
+#define CAN_F6R2_FB29_Pos (29U)
+#define CAN_F6R2_FB29_Msk (0x1U << CAN_F6R2_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F6R2_FB29 CAN_F6R2_FB29_Msk /*!< Filter bit 29 */
+#define CAN_F6R2_FB30_Pos (30U)
+#define CAN_F6R2_FB30_Msk (0x1U << CAN_F6R2_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F6R2_FB30 CAN_F6R2_FB30_Msk /*!< Filter bit 30 */
+#define CAN_F6R2_FB31_Pos (31U)
+#define CAN_F6R2_FB31_Msk (0x1U << CAN_F6R2_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F6R2_FB31 CAN_F6R2_FB31_Msk /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F7R2 register *******************/
+#define CAN_F7R2_FB0_Pos (0U)
+#define CAN_F7R2_FB0_Msk (0x1U << CAN_F7R2_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F7R2_FB0 CAN_F7R2_FB0_Msk /*!< Filter bit 0 */
+#define CAN_F7R2_FB1_Pos (1U)
+#define CAN_F7R2_FB1_Msk (0x1U << CAN_F7R2_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F7R2_FB1 CAN_F7R2_FB1_Msk /*!< Filter bit 1 */
+#define CAN_F7R2_FB2_Pos (2U)
+#define CAN_F7R2_FB2_Msk (0x1U << CAN_F7R2_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F7R2_FB2 CAN_F7R2_FB2_Msk /*!< Filter bit 2 */
+#define CAN_F7R2_FB3_Pos (3U)
+#define CAN_F7R2_FB3_Msk (0x1U << CAN_F7R2_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F7R2_FB3 CAN_F7R2_FB3_Msk /*!< Filter bit 3 */
+#define CAN_F7R2_FB4_Pos (4U)
+#define CAN_F7R2_FB4_Msk (0x1U << CAN_F7R2_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F7R2_FB4 CAN_F7R2_FB4_Msk /*!< Filter bit 4 */
+#define CAN_F7R2_FB5_Pos (5U)
+#define CAN_F7R2_FB5_Msk (0x1U << CAN_F7R2_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F7R2_FB5 CAN_F7R2_FB5_Msk /*!< Filter bit 5 */
+#define CAN_F7R2_FB6_Pos (6U)
+#define CAN_F7R2_FB6_Msk (0x1U << CAN_F7R2_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F7R2_FB6 CAN_F7R2_FB6_Msk /*!< Filter bit 6 */
+#define CAN_F7R2_FB7_Pos (7U)
+#define CAN_F7R2_FB7_Msk (0x1U << CAN_F7R2_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F7R2_FB7 CAN_F7R2_FB7_Msk /*!< Filter bit 7 */
+#define CAN_F7R2_FB8_Pos (8U)
+#define CAN_F7R2_FB8_Msk (0x1U << CAN_F7R2_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F7R2_FB8 CAN_F7R2_FB8_Msk /*!< Filter bit 8 */
+#define CAN_F7R2_FB9_Pos (9U)
+#define CAN_F7R2_FB9_Msk (0x1U << CAN_F7R2_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F7R2_FB9 CAN_F7R2_FB9_Msk /*!< Filter bit 9 */
+#define CAN_F7R2_FB10_Pos (10U)
+#define CAN_F7R2_FB10_Msk (0x1U << CAN_F7R2_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F7R2_FB10 CAN_F7R2_FB10_Msk /*!< Filter bit 10 */
+#define CAN_F7R2_FB11_Pos (11U)
+#define CAN_F7R2_FB11_Msk (0x1U << CAN_F7R2_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F7R2_FB11 CAN_F7R2_FB11_Msk /*!< Filter bit 11 */
+#define CAN_F7R2_FB12_Pos (12U)
+#define CAN_F7R2_FB12_Msk (0x1U << CAN_F7R2_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F7R2_FB12 CAN_F7R2_FB12_Msk /*!< Filter bit 12 */
+#define CAN_F7R2_FB13_Pos (13U)
+#define CAN_F7R2_FB13_Msk (0x1U << CAN_F7R2_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F7R2_FB13 CAN_F7R2_FB13_Msk /*!< Filter bit 13 */
+#define CAN_F7R2_FB14_Pos (14U)
+#define CAN_F7R2_FB14_Msk (0x1U << CAN_F7R2_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F7R2_FB14 CAN_F7R2_FB14_Msk /*!< Filter bit 14 */
+#define CAN_F7R2_FB15_Pos (15U)
+#define CAN_F7R2_FB15_Msk (0x1U << CAN_F7R2_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F7R2_FB15 CAN_F7R2_FB15_Msk /*!< Filter bit 15 */
+#define CAN_F7R2_FB16_Pos (16U)
+#define CAN_F7R2_FB16_Msk (0x1U << CAN_F7R2_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F7R2_FB16 CAN_F7R2_FB16_Msk /*!< Filter bit 16 */
+#define CAN_F7R2_FB17_Pos (17U)
+#define CAN_F7R2_FB17_Msk (0x1U << CAN_F7R2_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F7R2_FB17 CAN_F7R2_FB17_Msk /*!< Filter bit 17 */
+#define CAN_F7R2_FB18_Pos (18U)
+#define CAN_F7R2_FB18_Msk (0x1U << CAN_F7R2_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F7R2_FB18 CAN_F7R2_FB18_Msk /*!< Filter bit 18 */
+#define CAN_F7R2_FB19_Pos (19U)
+#define CAN_F7R2_FB19_Msk (0x1U << CAN_F7R2_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F7R2_FB19 CAN_F7R2_FB19_Msk /*!< Filter bit 19 */
+#define CAN_F7R2_FB20_Pos (20U)
+#define CAN_F7R2_FB20_Msk (0x1U << CAN_F7R2_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F7R2_FB20 CAN_F7R2_FB20_Msk /*!< Filter bit 20 */
+#define CAN_F7R2_FB21_Pos (21U)
+#define CAN_F7R2_FB21_Msk (0x1U << CAN_F7R2_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F7R2_FB21 CAN_F7R2_FB21_Msk /*!< Filter bit 21 */
+#define CAN_F7R2_FB22_Pos (22U)
+#define CAN_F7R2_FB22_Msk (0x1U << CAN_F7R2_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F7R2_FB22 CAN_F7R2_FB22_Msk /*!< Filter bit 22 */
+#define CAN_F7R2_FB23_Pos (23U)
+#define CAN_F7R2_FB23_Msk (0x1U << CAN_F7R2_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F7R2_FB23 CAN_F7R2_FB23_Msk /*!< Filter bit 23 */
+#define CAN_F7R2_FB24_Pos (24U)
+#define CAN_F7R2_FB24_Msk (0x1U << CAN_F7R2_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F7R2_FB24 CAN_F7R2_FB24_Msk /*!< Filter bit 24 */
+#define CAN_F7R2_FB25_Pos (25U)
+#define CAN_F7R2_FB25_Msk (0x1U << CAN_F7R2_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F7R2_FB25 CAN_F7R2_FB25_Msk /*!< Filter bit 25 */
+#define CAN_F7R2_FB26_Pos (26U)
+#define CAN_F7R2_FB26_Msk (0x1U << CAN_F7R2_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F7R2_FB26 CAN_F7R2_FB26_Msk /*!< Filter bit 26 */
+#define CAN_F7R2_FB27_Pos (27U)
+#define CAN_F7R2_FB27_Msk (0x1U << CAN_F7R2_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F7R2_FB27 CAN_F7R2_FB27_Msk /*!< Filter bit 27 */
+#define CAN_F7R2_FB28_Pos (28U)
+#define CAN_F7R2_FB28_Msk (0x1U << CAN_F7R2_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F7R2_FB28 CAN_F7R2_FB28_Msk /*!< Filter bit 28 */
+#define CAN_F7R2_FB29_Pos (29U)
+#define CAN_F7R2_FB29_Msk (0x1U << CAN_F7R2_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F7R2_FB29 CAN_F7R2_FB29_Msk /*!< Filter bit 29 */
+#define CAN_F7R2_FB30_Pos (30U)
+#define CAN_F7R2_FB30_Msk (0x1U << CAN_F7R2_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F7R2_FB30 CAN_F7R2_FB30_Msk /*!< Filter bit 30 */
+#define CAN_F7R2_FB31_Pos (31U)
+#define CAN_F7R2_FB31_Msk (0x1U << CAN_F7R2_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F7R2_FB31 CAN_F7R2_FB31_Msk /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F8R2 register *******************/
+#define CAN_F8R2_FB0_Pos (0U)
+#define CAN_F8R2_FB0_Msk (0x1U << CAN_F8R2_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F8R2_FB0 CAN_F8R2_FB0_Msk /*!< Filter bit 0 */
+#define CAN_F8R2_FB1_Pos (1U)
+#define CAN_F8R2_FB1_Msk (0x1U << CAN_F8R2_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F8R2_FB1 CAN_F8R2_FB1_Msk /*!< Filter bit 1 */
+#define CAN_F8R2_FB2_Pos (2U)
+#define CAN_F8R2_FB2_Msk (0x1U << CAN_F8R2_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F8R2_FB2 CAN_F8R2_FB2_Msk /*!< Filter bit 2 */
+#define CAN_F8R2_FB3_Pos (3U)
+#define CAN_F8R2_FB3_Msk (0x1U << CAN_F8R2_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F8R2_FB3 CAN_F8R2_FB3_Msk /*!< Filter bit 3 */
+#define CAN_F8R2_FB4_Pos (4U)
+#define CAN_F8R2_FB4_Msk (0x1U << CAN_F8R2_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F8R2_FB4 CAN_F8R2_FB4_Msk /*!< Filter bit 4 */
+#define CAN_F8R2_FB5_Pos (5U)
+#define CAN_F8R2_FB5_Msk (0x1U << CAN_F8R2_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F8R2_FB5 CAN_F8R2_FB5_Msk /*!< Filter bit 5 */
+#define CAN_F8R2_FB6_Pos (6U)
+#define CAN_F8R2_FB6_Msk (0x1U << CAN_F8R2_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F8R2_FB6 CAN_F8R2_FB6_Msk /*!< Filter bit 6 */
+#define CAN_F8R2_FB7_Pos (7U)
+#define CAN_F8R2_FB7_Msk (0x1U << CAN_F8R2_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F8R2_FB7 CAN_F8R2_FB7_Msk /*!< Filter bit 7 */
+#define CAN_F8R2_FB8_Pos (8U)
+#define CAN_F8R2_FB8_Msk (0x1U << CAN_F8R2_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F8R2_FB8 CAN_F8R2_FB8_Msk /*!< Filter bit 8 */
+#define CAN_F8R2_FB9_Pos (9U)
+#define CAN_F8R2_FB9_Msk (0x1U << CAN_F8R2_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F8R2_FB9 CAN_F8R2_FB9_Msk /*!< Filter bit 9 */
+#define CAN_F8R2_FB10_Pos (10U)
+#define CAN_F8R2_FB10_Msk (0x1U << CAN_F8R2_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F8R2_FB10 CAN_F8R2_FB10_Msk /*!< Filter bit 10 */
+#define CAN_F8R2_FB11_Pos (11U)
+#define CAN_F8R2_FB11_Msk (0x1U << CAN_F8R2_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F8R2_FB11 CAN_F8R2_FB11_Msk /*!< Filter bit 11 */
+#define CAN_F8R2_FB12_Pos (12U)
+#define CAN_F8R2_FB12_Msk (0x1U << CAN_F8R2_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F8R2_FB12 CAN_F8R2_FB12_Msk /*!< Filter bit 12 */
+#define CAN_F8R2_FB13_Pos (13U)
+#define CAN_F8R2_FB13_Msk (0x1U << CAN_F8R2_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F8R2_FB13 CAN_F8R2_FB13_Msk /*!< Filter bit 13 */
+#define CAN_F8R2_FB14_Pos (14U)
+#define CAN_F8R2_FB14_Msk (0x1U << CAN_F8R2_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F8R2_FB14 CAN_F8R2_FB14_Msk /*!< Filter bit 14 */
+#define CAN_F8R2_FB15_Pos (15U)
+#define CAN_F8R2_FB15_Msk (0x1U << CAN_F8R2_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F8R2_FB15 CAN_F8R2_FB15_Msk /*!< Filter bit 15 */
+#define CAN_F8R2_FB16_Pos (16U)
+#define CAN_F8R2_FB16_Msk (0x1U << CAN_F8R2_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F8R2_FB16 CAN_F8R2_FB16_Msk /*!< Filter bit 16 */
+#define CAN_F8R2_FB17_Pos (17U)
+#define CAN_F8R2_FB17_Msk (0x1U << CAN_F8R2_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F8R2_FB17 CAN_F8R2_FB17_Msk /*!< Filter bit 17 */
+#define CAN_F8R2_FB18_Pos (18U)
+#define CAN_F8R2_FB18_Msk (0x1U << CAN_F8R2_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F8R2_FB18 CAN_F8R2_FB18_Msk /*!< Filter bit 18 */
+#define CAN_F8R2_FB19_Pos (19U)
+#define CAN_F8R2_FB19_Msk (0x1U << CAN_F8R2_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F8R2_FB19 CAN_F8R2_FB19_Msk /*!< Filter bit 19 */
+#define CAN_F8R2_FB20_Pos (20U)
+#define CAN_F8R2_FB20_Msk (0x1U << CAN_F8R2_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F8R2_FB20 CAN_F8R2_FB20_Msk /*!< Filter bit 20 */
+#define CAN_F8R2_FB21_Pos (21U)
+#define CAN_F8R2_FB21_Msk (0x1U << CAN_F8R2_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F8R2_FB21 CAN_F8R2_FB21_Msk /*!< Filter bit 21 */
+#define CAN_F8R2_FB22_Pos (22U)
+#define CAN_F8R2_FB22_Msk (0x1U << CAN_F8R2_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F8R2_FB22 CAN_F8R2_FB22_Msk /*!< Filter bit 22 */
+#define CAN_F8R2_FB23_Pos (23U)
+#define CAN_F8R2_FB23_Msk (0x1U << CAN_F8R2_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F8R2_FB23 CAN_F8R2_FB23_Msk /*!< Filter bit 23 */
+#define CAN_F8R2_FB24_Pos (24U)
+#define CAN_F8R2_FB24_Msk (0x1U << CAN_F8R2_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F8R2_FB24 CAN_F8R2_FB24_Msk /*!< Filter bit 24 */
+#define CAN_F8R2_FB25_Pos (25U)
+#define CAN_F8R2_FB25_Msk (0x1U << CAN_F8R2_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F8R2_FB25 CAN_F8R2_FB25_Msk /*!< Filter bit 25 */
+#define CAN_F8R2_FB26_Pos (26U)
+#define CAN_F8R2_FB26_Msk (0x1U << CAN_F8R2_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F8R2_FB26 CAN_F8R2_FB26_Msk /*!< Filter bit 26 */
+#define CAN_F8R2_FB27_Pos (27U)
+#define CAN_F8R2_FB27_Msk (0x1U << CAN_F8R2_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F8R2_FB27 CAN_F8R2_FB27_Msk /*!< Filter bit 27 */
+#define CAN_F8R2_FB28_Pos (28U)
+#define CAN_F8R2_FB28_Msk (0x1U << CAN_F8R2_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F8R2_FB28 CAN_F8R2_FB28_Msk /*!< Filter bit 28 */
+#define CAN_F8R2_FB29_Pos (29U)
+#define CAN_F8R2_FB29_Msk (0x1U << CAN_F8R2_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F8R2_FB29 CAN_F8R2_FB29_Msk /*!< Filter bit 29 */
+#define CAN_F8R2_FB30_Pos (30U)
+#define CAN_F8R2_FB30_Msk (0x1U << CAN_F8R2_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F8R2_FB30 CAN_F8R2_FB30_Msk /*!< Filter bit 30 */
+#define CAN_F8R2_FB31_Pos (31U)
+#define CAN_F8R2_FB31_Msk (0x1U << CAN_F8R2_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F8R2_FB31 CAN_F8R2_FB31_Msk /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F9R2 register *******************/
+#define CAN_F9R2_FB0_Pos (0U)
+#define CAN_F9R2_FB0_Msk (0x1U << CAN_F9R2_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F9R2_FB0 CAN_F9R2_FB0_Msk /*!< Filter bit 0 */
+#define CAN_F9R2_FB1_Pos (1U)
+#define CAN_F9R2_FB1_Msk (0x1U << CAN_F9R2_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F9R2_FB1 CAN_F9R2_FB1_Msk /*!< Filter bit 1 */
+#define CAN_F9R2_FB2_Pos (2U)
+#define CAN_F9R2_FB2_Msk (0x1U << CAN_F9R2_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F9R2_FB2 CAN_F9R2_FB2_Msk /*!< Filter bit 2 */
+#define CAN_F9R2_FB3_Pos (3U)
+#define CAN_F9R2_FB3_Msk (0x1U << CAN_F9R2_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F9R2_FB3 CAN_F9R2_FB3_Msk /*!< Filter bit 3 */
+#define CAN_F9R2_FB4_Pos (4U)
+#define CAN_F9R2_FB4_Msk (0x1U << CAN_F9R2_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F9R2_FB4 CAN_F9R2_FB4_Msk /*!< Filter bit 4 */
+#define CAN_F9R2_FB5_Pos (5U)
+#define CAN_F9R2_FB5_Msk (0x1U << CAN_F9R2_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F9R2_FB5 CAN_F9R2_FB5_Msk /*!< Filter bit 5 */
+#define CAN_F9R2_FB6_Pos (6U)
+#define CAN_F9R2_FB6_Msk (0x1U << CAN_F9R2_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F9R2_FB6 CAN_F9R2_FB6_Msk /*!< Filter bit 6 */
+#define CAN_F9R2_FB7_Pos (7U)
+#define CAN_F9R2_FB7_Msk (0x1U << CAN_F9R2_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F9R2_FB7 CAN_F9R2_FB7_Msk /*!< Filter bit 7 */
+#define CAN_F9R2_FB8_Pos (8U)
+#define CAN_F9R2_FB8_Msk (0x1U << CAN_F9R2_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F9R2_FB8 CAN_F9R2_FB8_Msk /*!< Filter bit 8 */
+#define CAN_F9R2_FB9_Pos (9U)
+#define CAN_F9R2_FB9_Msk (0x1U << CAN_F9R2_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F9R2_FB9 CAN_F9R2_FB9_Msk /*!< Filter bit 9 */
+#define CAN_F9R2_FB10_Pos (10U)
+#define CAN_F9R2_FB10_Msk (0x1U << CAN_F9R2_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F9R2_FB10 CAN_F9R2_FB10_Msk /*!< Filter bit 10 */
+#define CAN_F9R2_FB11_Pos (11U)
+#define CAN_F9R2_FB11_Msk (0x1U << CAN_F9R2_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F9R2_FB11 CAN_F9R2_FB11_Msk /*!< Filter bit 11 */
+#define CAN_F9R2_FB12_Pos (12U)
+#define CAN_F9R2_FB12_Msk (0x1U << CAN_F9R2_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F9R2_FB12 CAN_F9R2_FB12_Msk /*!< Filter bit 12 */
+#define CAN_F9R2_FB13_Pos (13U)
+#define CAN_F9R2_FB13_Msk (0x1U << CAN_F9R2_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F9R2_FB13 CAN_F9R2_FB13_Msk /*!< Filter bit 13 */
+#define CAN_F9R2_FB14_Pos (14U)
+#define CAN_F9R2_FB14_Msk (0x1U << CAN_F9R2_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F9R2_FB14 CAN_F9R2_FB14_Msk /*!< Filter bit 14 */
+#define CAN_F9R2_FB15_Pos (15U)
+#define CAN_F9R2_FB15_Msk (0x1U << CAN_F9R2_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F9R2_FB15 CAN_F9R2_FB15_Msk /*!< Filter bit 15 */
+#define CAN_F9R2_FB16_Pos (16U)
+#define CAN_F9R2_FB16_Msk (0x1U << CAN_F9R2_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F9R2_FB16 CAN_F9R2_FB16_Msk /*!< Filter bit 16 */
+#define CAN_F9R2_FB17_Pos (17U)
+#define CAN_F9R2_FB17_Msk (0x1U << CAN_F9R2_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F9R2_FB17 CAN_F9R2_FB17_Msk /*!< Filter bit 17 */
+#define CAN_F9R2_FB18_Pos (18U)
+#define CAN_F9R2_FB18_Msk (0x1U << CAN_F9R2_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F9R2_FB18 CAN_F9R2_FB18_Msk /*!< Filter bit 18 */
+#define CAN_F9R2_FB19_Pos (19U)
+#define CAN_F9R2_FB19_Msk (0x1U << CAN_F9R2_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F9R2_FB19 CAN_F9R2_FB19_Msk /*!< Filter bit 19 */
+#define CAN_F9R2_FB20_Pos (20U)
+#define CAN_F9R2_FB20_Msk (0x1U << CAN_F9R2_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F9R2_FB20 CAN_F9R2_FB20_Msk /*!< Filter bit 20 */
+#define CAN_F9R2_FB21_Pos (21U)
+#define CAN_F9R2_FB21_Msk (0x1U << CAN_F9R2_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F9R2_FB21 CAN_F9R2_FB21_Msk /*!< Filter bit 21 */
+#define CAN_F9R2_FB22_Pos (22U)
+#define CAN_F9R2_FB22_Msk (0x1U << CAN_F9R2_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F9R2_FB22 CAN_F9R2_FB22_Msk /*!< Filter bit 22 */
+#define CAN_F9R2_FB23_Pos (23U)
+#define CAN_F9R2_FB23_Msk (0x1U << CAN_F9R2_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F9R2_FB23 CAN_F9R2_FB23_Msk /*!< Filter bit 23 */
+#define CAN_F9R2_FB24_Pos (24U)
+#define CAN_F9R2_FB24_Msk (0x1U << CAN_F9R2_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F9R2_FB24 CAN_F9R2_FB24_Msk /*!< Filter bit 24 */
+#define CAN_F9R2_FB25_Pos (25U)
+#define CAN_F9R2_FB25_Msk (0x1U << CAN_F9R2_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F9R2_FB25 CAN_F9R2_FB25_Msk /*!< Filter bit 25 */
+#define CAN_F9R2_FB26_Pos (26U)
+#define CAN_F9R2_FB26_Msk (0x1U << CAN_F9R2_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F9R2_FB26 CAN_F9R2_FB26_Msk /*!< Filter bit 26 */
+#define CAN_F9R2_FB27_Pos (27U)
+#define CAN_F9R2_FB27_Msk (0x1U << CAN_F9R2_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F9R2_FB27 CAN_F9R2_FB27_Msk /*!< Filter bit 27 */
+#define CAN_F9R2_FB28_Pos (28U)
+#define CAN_F9R2_FB28_Msk (0x1U << CAN_F9R2_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F9R2_FB28 CAN_F9R2_FB28_Msk /*!< Filter bit 28 */
+#define CAN_F9R2_FB29_Pos (29U)
+#define CAN_F9R2_FB29_Msk (0x1U << CAN_F9R2_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F9R2_FB29 CAN_F9R2_FB29_Msk /*!< Filter bit 29 */
+#define CAN_F9R2_FB30_Pos (30U)
+#define CAN_F9R2_FB30_Msk (0x1U << CAN_F9R2_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F9R2_FB30 CAN_F9R2_FB30_Msk /*!< Filter bit 30 */
+#define CAN_F9R2_FB31_Pos (31U)
+#define CAN_F9R2_FB31_Msk (0x1U << CAN_F9R2_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F9R2_FB31 CAN_F9R2_FB31_Msk /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F10R2 register ******************/
+#define CAN_F10R2_FB0_Pos (0U)
+#define CAN_F10R2_FB0_Msk (0x1U << CAN_F10R2_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F10R2_FB0 CAN_F10R2_FB0_Msk /*!< Filter bit 0 */
+#define CAN_F10R2_FB1_Pos (1U)
+#define CAN_F10R2_FB1_Msk (0x1U << CAN_F10R2_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F10R2_FB1 CAN_F10R2_FB1_Msk /*!< Filter bit 1 */
+#define CAN_F10R2_FB2_Pos (2U)
+#define CAN_F10R2_FB2_Msk (0x1U << CAN_F10R2_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F10R2_FB2 CAN_F10R2_FB2_Msk /*!< Filter bit 2 */
+#define CAN_F10R2_FB3_Pos (3U)
+#define CAN_F10R2_FB3_Msk (0x1U << CAN_F10R2_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F10R2_FB3 CAN_F10R2_FB3_Msk /*!< Filter bit 3 */
+#define CAN_F10R2_FB4_Pos (4U)
+#define CAN_F10R2_FB4_Msk (0x1U << CAN_F10R2_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F10R2_FB4 CAN_F10R2_FB4_Msk /*!< Filter bit 4 */
+#define CAN_F10R2_FB5_Pos (5U)
+#define CAN_F10R2_FB5_Msk (0x1U << CAN_F10R2_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F10R2_FB5 CAN_F10R2_FB5_Msk /*!< Filter bit 5 */
+#define CAN_F10R2_FB6_Pos (6U)
+#define CAN_F10R2_FB6_Msk (0x1U << CAN_F10R2_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F10R2_FB6 CAN_F10R2_FB6_Msk /*!< Filter bit 6 */
+#define CAN_F10R2_FB7_Pos (7U)
+#define CAN_F10R2_FB7_Msk (0x1U << CAN_F10R2_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F10R2_FB7 CAN_F10R2_FB7_Msk /*!< Filter bit 7 */
+#define CAN_F10R2_FB8_Pos (8U)
+#define CAN_F10R2_FB8_Msk (0x1U << CAN_F10R2_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F10R2_FB8 CAN_F10R2_FB8_Msk /*!< Filter bit 8 */
+#define CAN_F10R2_FB9_Pos (9U)
+#define CAN_F10R2_FB9_Msk (0x1U << CAN_F10R2_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F10R2_FB9 CAN_F10R2_FB9_Msk /*!< Filter bit 9 */
+#define CAN_F10R2_FB10_Pos (10U)
+#define CAN_F10R2_FB10_Msk (0x1U << CAN_F10R2_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F10R2_FB10 CAN_F10R2_FB10_Msk /*!< Filter bit 10 */
+#define CAN_F10R2_FB11_Pos (11U)
+#define CAN_F10R2_FB11_Msk (0x1U << CAN_F10R2_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F10R2_FB11 CAN_F10R2_FB11_Msk /*!< Filter bit 11 */
+#define CAN_F10R2_FB12_Pos (12U)
+#define CAN_F10R2_FB12_Msk (0x1U << CAN_F10R2_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F10R2_FB12 CAN_F10R2_FB12_Msk /*!< Filter bit 12 */
+#define CAN_F10R2_FB13_Pos (13U)
+#define CAN_F10R2_FB13_Msk (0x1U << CAN_F10R2_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F10R2_FB13 CAN_F10R2_FB13_Msk /*!< Filter bit 13 */
+#define CAN_F10R2_FB14_Pos (14U)
+#define CAN_F10R2_FB14_Msk (0x1U << CAN_F10R2_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F10R2_FB14 CAN_F10R2_FB14_Msk /*!< Filter bit 14 */
+#define CAN_F10R2_FB15_Pos (15U)
+#define CAN_F10R2_FB15_Msk (0x1U << CAN_F10R2_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F10R2_FB15 CAN_F10R2_FB15_Msk /*!< Filter bit 15 */
+#define CAN_F10R2_FB16_Pos (16U)
+#define CAN_F10R2_FB16_Msk (0x1U << CAN_F10R2_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F10R2_FB16 CAN_F10R2_FB16_Msk /*!< Filter bit 16 */
+#define CAN_F10R2_FB17_Pos (17U)
+#define CAN_F10R2_FB17_Msk (0x1U << CAN_F10R2_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F10R2_FB17 CAN_F10R2_FB17_Msk /*!< Filter bit 17 */
+#define CAN_F10R2_FB18_Pos (18U)
+#define CAN_F10R2_FB18_Msk (0x1U << CAN_F10R2_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F10R2_FB18 CAN_F10R2_FB18_Msk /*!< Filter bit 18 */
+#define CAN_F10R2_FB19_Pos (19U)
+#define CAN_F10R2_FB19_Msk (0x1U << CAN_F10R2_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F10R2_FB19 CAN_F10R2_FB19_Msk /*!< Filter bit 19 */
+#define CAN_F10R2_FB20_Pos (20U)
+#define CAN_F10R2_FB20_Msk (0x1U << CAN_F10R2_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F10R2_FB20 CAN_F10R2_FB20_Msk /*!< Filter bit 20 */
+#define CAN_F10R2_FB21_Pos (21U)
+#define CAN_F10R2_FB21_Msk (0x1U << CAN_F10R2_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F10R2_FB21 CAN_F10R2_FB21_Msk /*!< Filter bit 21 */
+#define CAN_F10R2_FB22_Pos (22U)
+#define CAN_F10R2_FB22_Msk (0x1U << CAN_F10R2_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F10R2_FB22 CAN_F10R2_FB22_Msk /*!< Filter bit 22 */
+#define CAN_F10R2_FB23_Pos (23U)
+#define CAN_F10R2_FB23_Msk (0x1U << CAN_F10R2_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F10R2_FB23 CAN_F10R2_FB23_Msk /*!< Filter bit 23 */
+#define CAN_F10R2_FB24_Pos (24U)
+#define CAN_F10R2_FB24_Msk (0x1U << CAN_F10R2_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F10R2_FB24 CAN_F10R2_FB24_Msk /*!< Filter bit 24 */
+#define CAN_F10R2_FB25_Pos (25U)
+#define CAN_F10R2_FB25_Msk (0x1U << CAN_F10R2_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F10R2_FB25 CAN_F10R2_FB25_Msk /*!< Filter bit 25 */
+#define CAN_F10R2_FB26_Pos (26U)
+#define CAN_F10R2_FB26_Msk (0x1U << CAN_F10R2_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F10R2_FB26 CAN_F10R2_FB26_Msk /*!< Filter bit 26 */
+#define CAN_F10R2_FB27_Pos (27U)
+#define CAN_F10R2_FB27_Msk (0x1U << CAN_F10R2_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F10R2_FB27 CAN_F10R2_FB27_Msk /*!< Filter bit 27 */
+#define CAN_F10R2_FB28_Pos (28U)
+#define CAN_F10R2_FB28_Msk (0x1U << CAN_F10R2_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F10R2_FB28 CAN_F10R2_FB28_Msk /*!< Filter bit 28 */
+#define CAN_F10R2_FB29_Pos (29U)
+#define CAN_F10R2_FB29_Msk (0x1U << CAN_F10R2_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F10R2_FB29 CAN_F10R2_FB29_Msk /*!< Filter bit 29 */
+#define CAN_F10R2_FB30_Pos (30U)
+#define CAN_F10R2_FB30_Msk (0x1U << CAN_F10R2_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F10R2_FB30 CAN_F10R2_FB30_Msk /*!< Filter bit 30 */
+#define CAN_F10R2_FB31_Pos (31U)
+#define CAN_F10R2_FB31_Msk (0x1U << CAN_F10R2_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F10R2_FB31 CAN_F10R2_FB31_Msk /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F11R2 register ******************/
+#define CAN_F11R2_FB0_Pos (0U)
+#define CAN_F11R2_FB0_Msk (0x1U << CAN_F11R2_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F11R2_FB0 CAN_F11R2_FB0_Msk /*!< Filter bit 0 */
+#define CAN_F11R2_FB1_Pos (1U)
+#define CAN_F11R2_FB1_Msk (0x1U << CAN_F11R2_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F11R2_FB1 CAN_F11R2_FB1_Msk /*!< Filter bit 1 */
+#define CAN_F11R2_FB2_Pos (2U)
+#define CAN_F11R2_FB2_Msk (0x1U << CAN_F11R2_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F11R2_FB2 CAN_F11R2_FB2_Msk /*!< Filter bit 2 */
+#define CAN_F11R2_FB3_Pos (3U)
+#define CAN_F11R2_FB3_Msk (0x1U << CAN_F11R2_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F11R2_FB3 CAN_F11R2_FB3_Msk /*!< Filter bit 3 */
+#define CAN_F11R2_FB4_Pos (4U)
+#define CAN_F11R2_FB4_Msk (0x1U << CAN_F11R2_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F11R2_FB4 CAN_F11R2_FB4_Msk /*!< Filter bit 4 */
+#define CAN_F11R2_FB5_Pos (5U)
+#define CAN_F11R2_FB5_Msk (0x1U << CAN_F11R2_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F11R2_FB5 CAN_F11R2_FB5_Msk /*!< Filter bit 5 */
+#define CAN_F11R2_FB6_Pos (6U)
+#define CAN_F11R2_FB6_Msk (0x1U << CAN_F11R2_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F11R2_FB6 CAN_F11R2_FB6_Msk /*!< Filter bit 6 */
+#define CAN_F11R2_FB7_Pos (7U)
+#define CAN_F11R2_FB7_Msk (0x1U << CAN_F11R2_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F11R2_FB7 CAN_F11R2_FB7_Msk /*!< Filter bit 7 */
+#define CAN_F11R2_FB8_Pos (8U)
+#define CAN_F11R2_FB8_Msk (0x1U << CAN_F11R2_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F11R2_FB8 CAN_F11R2_FB8_Msk /*!< Filter bit 8 */
+#define CAN_F11R2_FB9_Pos (9U)
+#define CAN_F11R2_FB9_Msk (0x1U << CAN_F11R2_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F11R2_FB9 CAN_F11R2_FB9_Msk /*!< Filter bit 9 */
+#define CAN_F11R2_FB10_Pos (10U)
+#define CAN_F11R2_FB10_Msk (0x1U << CAN_F11R2_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F11R2_FB10 CAN_F11R2_FB10_Msk /*!< Filter bit 10 */
+#define CAN_F11R2_FB11_Pos (11U)
+#define CAN_F11R2_FB11_Msk (0x1U << CAN_F11R2_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F11R2_FB11 CAN_F11R2_FB11_Msk /*!< Filter bit 11 */
+#define CAN_F11R2_FB12_Pos (12U)
+#define CAN_F11R2_FB12_Msk (0x1U << CAN_F11R2_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F11R2_FB12 CAN_F11R2_FB12_Msk /*!< Filter bit 12 */
+#define CAN_F11R2_FB13_Pos (13U)
+#define CAN_F11R2_FB13_Msk (0x1U << CAN_F11R2_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F11R2_FB13 CAN_F11R2_FB13_Msk /*!< Filter bit 13 */
+#define CAN_F11R2_FB14_Pos (14U)
+#define CAN_F11R2_FB14_Msk (0x1U << CAN_F11R2_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F11R2_FB14 CAN_F11R2_FB14_Msk /*!< Filter bit 14 */
+#define CAN_F11R2_FB15_Pos (15U)
+#define CAN_F11R2_FB15_Msk (0x1U << CAN_F11R2_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F11R2_FB15 CAN_F11R2_FB15_Msk /*!< Filter bit 15 */
+#define CAN_F11R2_FB16_Pos (16U)
+#define CAN_F11R2_FB16_Msk (0x1U << CAN_F11R2_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F11R2_FB16 CAN_F11R2_FB16_Msk /*!< Filter bit 16 */
+#define CAN_F11R2_FB17_Pos (17U)
+#define CAN_F11R2_FB17_Msk (0x1U << CAN_F11R2_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F11R2_FB17 CAN_F11R2_FB17_Msk /*!< Filter bit 17 */
+#define CAN_F11R2_FB18_Pos (18U)
+#define CAN_F11R2_FB18_Msk (0x1U << CAN_F11R2_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F11R2_FB18 CAN_F11R2_FB18_Msk /*!< Filter bit 18 */
+#define CAN_F11R2_FB19_Pos (19U)
+#define CAN_F11R2_FB19_Msk (0x1U << CAN_F11R2_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F11R2_FB19 CAN_F11R2_FB19_Msk /*!< Filter bit 19 */
+#define CAN_F11R2_FB20_Pos (20U)
+#define CAN_F11R2_FB20_Msk (0x1U << CAN_F11R2_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F11R2_FB20 CAN_F11R2_FB20_Msk /*!< Filter bit 20 */
+#define CAN_F11R2_FB21_Pos (21U)
+#define CAN_F11R2_FB21_Msk (0x1U << CAN_F11R2_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F11R2_FB21 CAN_F11R2_FB21_Msk /*!< Filter bit 21 */
+#define CAN_F11R2_FB22_Pos (22U)
+#define CAN_F11R2_FB22_Msk (0x1U << CAN_F11R2_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F11R2_FB22 CAN_F11R2_FB22_Msk /*!< Filter bit 22 */
+#define CAN_F11R2_FB23_Pos (23U)
+#define CAN_F11R2_FB23_Msk (0x1U << CAN_F11R2_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F11R2_FB23 CAN_F11R2_FB23_Msk /*!< Filter bit 23 */
+#define CAN_F11R2_FB24_Pos (24U)
+#define CAN_F11R2_FB24_Msk (0x1U << CAN_F11R2_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F11R2_FB24 CAN_F11R2_FB24_Msk /*!< Filter bit 24 */
+#define CAN_F11R2_FB25_Pos (25U)
+#define CAN_F11R2_FB25_Msk (0x1U << CAN_F11R2_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F11R2_FB25 CAN_F11R2_FB25_Msk /*!< Filter bit 25 */
+#define CAN_F11R2_FB26_Pos (26U)
+#define CAN_F11R2_FB26_Msk (0x1U << CAN_F11R2_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F11R2_FB26 CAN_F11R2_FB26_Msk /*!< Filter bit 26 */
+#define CAN_F11R2_FB27_Pos (27U)
+#define CAN_F11R2_FB27_Msk (0x1U << CAN_F11R2_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F11R2_FB27 CAN_F11R2_FB27_Msk /*!< Filter bit 27 */
+#define CAN_F11R2_FB28_Pos (28U)
+#define CAN_F11R2_FB28_Msk (0x1U << CAN_F11R2_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F11R2_FB28 CAN_F11R2_FB28_Msk /*!< Filter bit 28 */
+#define CAN_F11R2_FB29_Pos (29U)
+#define CAN_F11R2_FB29_Msk (0x1U << CAN_F11R2_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F11R2_FB29 CAN_F11R2_FB29_Msk /*!< Filter bit 29 */
+#define CAN_F11R2_FB30_Pos (30U)
+#define CAN_F11R2_FB30_Msk (0x1U << CAN_F11R2_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F11R2_FB30 CAN_F11R2_FB30_Msk /*!< Filter bit 30 */
+#define CAN_F11R2_FB31_Pos (31U)
+#define CAN_F11R2_FB31_Msk (0x1U << CAN_F11R2_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F11R2_FB31 CAN_F11R2_FB31_Msk /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F12R2 register ******************/
+#define CAN_F12R2_FB0_Pos (0U)
+#define CAN_F12R2_FB0_Msk (0x1U << CAN_F12R2_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F12R2_FB0 CAN_F12R2_FB0_Msk /*!< Filter bit 0 */
+#define CAN_F12R2_FB1_Pos (1U)
+#define CAN_F12R2_FB1_Msk (0x1U << CAN_F12R2_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F12R2_FB1 CAN_F12R2_FB1_Msk /*!< Filter bit 1 */
+#define CAN_F12R2_FB2_Pos (2U)
+#define CAN_F12R2_FB2_Msk (0x1U << CAN_F12R2_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F12R2_FB2 CAN_F12R2_FB2_Msk /*!< Filter bit 2 */
+#define CAN_F12R2_FB3_Pos (3U)
+#define CAN_F12R2_FB3_Msk (0x1U << CAN_F12R2_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F12R2_FB3 CAN_F12R2_FB3_Msk /*!< Filter bit 3 */
+#define CAN_F12R2_FB4_Pos (4U)
+#define CAN_F12R2_FB4_Msk (0x1U << CAN_F12R2_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F12R2_FB4 CAN_F12R2_FB4_Msk /*!< Filter bit 4 */
+#define CAN_F12R2_FB5_Pos (5U)
+#define CAN_F12R2_FB5_Msk (0x1U << CAN_F12R2_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F12R2_FB5 CAN_F12R2_FB5_Msk /*!< Filter bit 5 */
+#define CAN_F12R2_FB6_Pos (6U)
+#define CAN_F12R2_FB6_Msk (0x1U << CAN_F12R2_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F12R2_FB6 CAN_F12R2_FB6_Msk /*!< Filter bit 6 */
+#define CAN_F12R2_FB7_Pos (7U)
+#define CAN_F12R2_FB7_Msk (0x1U << CAN_F12R2_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F12R2_FB7 CAN_F12R2_FB7_Msk /*!< Filter bit 7 */
+#define CAN_F12R2_FB8_Pos (8U)
+#define CAN_F12R2_FB8_Msk (0x1U << CAN_F12R2_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F12R2_FB8 CAN_F12R2_FB8_Msk /*!< Filter bit 8 */
+#define CAN_F12R2_FB9_Pos (9U)
+#define CAN_F12R2_FB9_Msk (0x1U << CAN_F12R2_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F12R2_FB9 CAN_F12R2_FB9_Msk /*!< Filter bit 9 */
+#define CAN_F12R2_FB10_Pos (10U)
+#define CAN_F12R2_FB10_Msk (0x1U << CAN_F12R2_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F12R2_FB10 CAN_F12R2_FB10_Msk /*!< Filter bit 10 */
+#define CAN_F12R2_FB11_Pos (11U)
+#define CAN_F12R2_FB11_Msk (0x1U << CAN_F12R2_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F12R2_FB11 CAN_F12R2_FB11_Msk /*!< Filter bit 11 */
+#define CAN_F12R2_FB12_Pos (12U)
+#define CAN_F12R2_FB12_Msk (0x1U << CAN_F12R2_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F12R2_FB12 CAN_F12R2_FB12_Msk /*!< Filter bit 12 */
+#define CAN_F12R2_FB13_Pos (13U)
+#define CAN_F12R2_FB13_Msk (0x1U << CAN_F12R2_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F12R2_FB13 CAN_F12R2_FB13_Msk /*!< Filter bit 13 */
+#define CAN_F12R2_FB14_Pos (14U)
+#define CAN_F12R2_FB14_Msk (0x1U << CAN_F12R2_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F12R2_FB14 CAN_F12R2_FB14_Msk /*!< Filter bit 14 */
+#define CAN_F12R2_FB15_Pos (15U)
+#define CAN_F12R2_FB15_Msk (0x1U << CAN_F12R2_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F12R2_FB15 CAN_F12R2_FB15_Msk /*!< Filter bit 15 */
+#define CAN_F12R2_FB16_Pos (16U)
+#define CAN_F12R2_FB16_Msk (0x1U << CAN_F12R2_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F12R2_FB16 CAN_F12R2_FB16_Msk /*!< Filter bit 16 */
+#define CAN_F12R2_FB17_Pos (17U)
+#define CAN_F12R2_FB17_Msk (0x1U << CAN_F12R2_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F12R2_FB17 CAN_F12R2_FB17_Msk /*!< Filter bit 17 */
+#define CAN_F12R2_FB18_Pos (18U)
+#define CAN_F12R2_FB18_Msk (0x1U << CAN_F12R2_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F12R2_FB18 CAN_F12R2_FB18_Msk /*!< Filter bit 18 */
+#define CAN_F12R2_FB19_Pos (19U)
+#define CAN_F12R2_FB19_Msk (0x1U << CAN_F12R2_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F12R2_FB19 CAN_F12R2_FB19_Msk /*!< Filter bit 19 */
+#define CAN_F12R2_FB20_Pos (20U)
+#define CAN_F12R2_FB20_Msk (0x1U << CAN_F12R2_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F12R2_FB20 CAN_F12R2_FB20_Msk /*!< Filter bit 20 */
+#define CAN_F12R2_FB21_Pos (21U)
+#define CAN_F12R2_FB21_Msk (0x1U << CAN_F12R2_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F12R2_FB21 CAN_F12R2_FB21_Msk /*!< Filter bit 21 */
+#define CAN_F12R2_FB22_Pos (22U)
+#define CAN_F12R2_FB22_Msk (0x1U << CAN_F12R2_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F12R2_FB22 CAN_F12R2_FB22_Msk /*!< Filter bit 22 */
+#define CAN_F12R2_FB23_Pos (23U)
+#define CAN_F12R2_FB23_Msk (0x1U << CAN_F12R2_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F12R2_FB23 CAN_F12R2_FB23_Msk /*!< Filter bit 23 */
+#define CAN_F12R2_FB24_Pos (24U)
+#define CAN_F12R2_FB24_Msk (0x1U << CAN_F12R2_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F12R2_FB24 CAN_F12R2_FB24_Msk /*!< Filter bit 24 */
+#define CAN_F12R2_FB25_Pos (25U)
+#define CAN_F12R2_FB25_Msk (0x1U << CAN_F12R2_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F12R2_FB25 CAN_F12R2_FB25_Msk /*!< Filter bit 25 */
+#define CAN_F12R2_FB26_Pos (26U)
+#define CAN_F12R2_FB26_Msk (0x1U << CAN_F12R2_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F12R2_FB26 CAN_F12R2_FB26_Msk /*!< Filter bit 26 */
+#define CAN_F12R2_FB27_Pos (27U)
+#define CAN_F12R2_FB27_Msk (0x1U << CAN_F12R2_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F12R2_FB27 CAN_F12R2_FB27_Msk /*!< Filter bit 27 */
+#define CAN_F12R2_FB28_Pos (28U)
+#define CAN_F12R2_FB28_Msk (0x1U << CAN_F12R2_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F12R2_FB28 CAN_F12R2_FB28_Msk /*!< Filter bit 28 */
+#define CAN_F12R2_FB29_Pos (29U)
+#define CAN_F12R2_FB29_Msk (0x1U << CAN_F12R2_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F12R2_FB29 CAN_F12R2_FB29_Msk /*!< Filter bit 29 */
+#define CAN_F12R2_FB30_Pos (30U)
+#define CAN_F12R2_FB30_Msk (0x1U << CAN_F12R2_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F12R2_FB30 CAN_F12R2_FB30_Msk /*!< Filter bit 30 */
+#define CAN_F12R2_FB31_Pos (31U)
+#define CAN_F12R2_FB31_Msk (0x1U << CAN_F12R2_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F12R2_FB31 CAN_F12R2_FB31_Msk /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F13R2 register ******************/
+#define CAN_F13R2_FB0_Pos (0U)
+#define CAN_F13R2_FB0_Msk (0x1U << CAN_F13R2_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F13R2_FB0 CAN_F13R2_FB0_Msk /*!< Filter bit 0 */
+#define CAN_F13R2_FB1_Pos (1U)
+#define CAN_F13R2_FB1_Msk (0x1U << CAN_F13R2_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F13R2_FB1 CAN_F13R2_FB1_Msk /*!< Filter bit 1 */
+#define CAN_F13R2_FB2_Pos (2U)
+#define CAN_F13R2_FB2_Msk (0x1U << CAN_F13R2_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F13R2_FB2 CAN_F13R2_FB2_Msk /*!< Filter bit 2 */
+#define CAN_F13R2_FB3_Pos (3U)
+#define CAN_F13R2_FB3_Msk (0x1U << CAN_F13R2_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F13R2_FB3 CAN_F13R2_FB3_Msk /*!< Filter bit 3 */
+#define CAN_F13R2_FB4_Pos (4U)
+#define CAN_F13R2_FB4_Msk (0x1U << CAN_F13R2_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F13R2_FB4 CAN_F13R2_FB4_Msk /*!< Filter bit 4 */
+#define CAN_F13R2_FB5_Pos (5U)
+#define CAN_F13R2_FB5_Msk (0x1U << CAN_F13R2_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F13R2_FB5 CAN_F13R2_FB5_Msk /*!< Filter bit 5 */
+#define CAN_F13R2_FB6_Pos (6U)
+#define CAN_F13R2_FB6_Msk (0x1U << CAN_F13R2_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F13R2_FB6 CAN_F13R2_FB6_Msk /*!< Filter bit 6 */
+#define CAN_F13R2_FB7_Pos (7U)
+#define CAN_F13R2_FB7_Msk (0x1U << CAN_F13R2_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F13R2_FB7 CAN_F13R2_FB7_Msk /*!< Filter bit 7 */
+#define CAN_F13R2_FB8_Pos (8U)
+#define CAN_F13R2_FB8_Msk (0x1U << CAN_F13R2_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F13R2_FB8 CAN_F13R2_FB8_Msk /*!< Filter bit 8 */
+#define CAN_F13R2_FB9_Pos (9U)
+#define CAN_F13R2_FB9_Msk (0x1U << CAN_F13R2_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F13R2_FB9 CAN_F13R2_FB9_Msk /*!< Filter bit 9 */
+#define CAN_F13R2_FB10_Pos (10U)
+#define CAN_F13R2_FB10_Msk (0x1U << CAN_F13R2_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F13R2_FB10 CAN_F13R2_FB10_Msk /*!< Filter bit 10 */
+#define CAN_F13R2_FB11_Pos (11U)
+#define CAN_F13R2_FB11_Msk (0x1U << CAN_F13R2_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F13R2_FB11 CAN_F13R2_FB11_Msk /*!< Filter bit 11 */
+#define CAN_F13R2_FB12_Pos (12U)
+#define CAN_F13R2_FB12_Msk (0x1U << CAN_F13R2_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F13R2_FB12 CAN_F13R2_FB12_Msk /*!< Filter bit 12 */
+#define CAN_F13R2_FB13_Pos (13U)
+#define CAN_F13R2_FB13_Msk (0x1U << CAN_F13R2_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F13R2_FB13 CAN_F13R2_FB13_Msk /*!< Filter bit 13 */
+#define CAN_F13R2_FB14_Pos (14U)
+#define CAN_F13R2_FB14_Msk (0x1U << CAN_F13R2_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F13R2_FB14 CAN_F13R2_FB14_Msk /*!< Filter bit 14 */
+#define CAN_F13R2_FB15_Pos (15U)
+#define CAN_F13R2_FB15_Msk (0x1U << CAN_F13R2_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F13R2_FB15 CAN_F13R2_FB15_Msk /*!< Filter bit 15 */
+#define CAN_F13R2_FB16_Pos (16U)
+#define CAN_F13R2_FB16_Msk (0x1U << CAN_F13R2_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F13R2_FB16 CAN_F13R2_FB16_Msk /*!< Filter bit 16 */
+#define CAN_F13R2_FB17_Pos (17U)
+#define CAN_F13R2_FB17_Msk (0x1U << CAN_F13R2_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F13R2_FB17 CAN_F13R2_FB17_Msk /*!< Filter bit 17 */
+#define CAN_F13R2_FB18_Pos (18U)
+#define CAN_F13R2_FB18_Msk (0x1U << CAN_F13R2_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F13R2_FB18 CAN_F13R2_FB18_Msk /*!< Filter bit 18 */
+#define CAN_F13R2_FB19_Pos (19U)
+#define CAN_F13R2_FB19_Msk (0x1U << CAN_F13R2_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F13R2_FB19 CAN_F13R2_FB19_Msk /*!< Filter bit 19 */
+#define CAN_F13R2_FB20_Pos (20U)
+#define CAN_F13R2_FB20_Msk (0x1U << CAN_F13R2_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F13R2_FB20 CAN_F13R2_FB20_Msk /*!< Filter bit 20 */
+#define CAN_F13R2_FB21_Pos (21U)
+#define CAN_F13R2_FB21_Msk (0x1U << CAN_F13R2_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F13R2_FB21 CAN_F13R2_FB21_Msk /*!< Filter bit 21 */
+#define CAN_F13R2_FB22_Pos (22U)
+#define CAN_F13R2_FB22_Msk (0x1U << CAN_F13R2_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F13R2_FB22 CAN_F13R2_FB22_Msk /*!< Filter bit 22 */
+#define CAN_F13R2_FB23_Pos (23U)
+#define CAN_F13R2_FB23_Msk (0x1U << CAN_F13R2_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F13R2_FB23 CAN_F13R2_FB23_Msk /*!< Filter bit 23 */
+#define CAN_F13R2_FB24_Pos (24U)
+#define CAN_F13R2_FB24_Msk (0x1U << CAN_F13R2_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F13R2_FB24 CAN_F13R2_FB24_Msk /*!< Filter bit 24 */
+#define CAN_F13R2_FB25_Pos (25U)
+#define CAN_F13R2_FB25_Msk (0x1U << CAN_F13R2_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F13R2_FB25 CAN_F13R2_FB25_Msk /*!< Filter bit 25 */
+#define CAN_F13R2_FB26_Pos (26U)
+#define CAN_F13R2_FB26_Msk (0x1U << CAN_F13R2_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F13R2_FB26 CAN_F13R2_FB26_Msk /*!< Filter bit 26 */
+#define CAN_F13R2_FB27_Pos (27U)
+#define CAN_F13R2_FB27_Msk (0x1U << CAN_F13R2_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F13R2_FB27 CAN_F13R2_FB27_Msk /*!< Filter bit 27 */
+#define CAN_F13R2_FB28_Pos (28U)
+#define CAN_F13R2_FB28_Msk (0x1U << CAN_F13R2_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F13R2_FB28 CAN_F13R2_FB28_Msk /*!< Filter bit 28 */
+#define CAN_F13R2_FB29_Pos (29U)
+#define CAN_F13R2_FB29_Msk (0x1U << CAN_F13R2_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F13R2_FB29 CAN_F13R2_FB29_Msk /*!< Filter bit 29 */
+#define CAN_F13R2_FB30_Pos (30U)
+#define CAN_F13R2_FB30_Msk (0x1U << CAN_F13R2_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F13R2_FB30 CAN_F13R2_FB30_Msk /*!< Filter bit 30 */
+#define CAN_F13R2_FB31_Pos (31U)
+#define CAN_F13R2_FB31_Msk (0x1U << CAN_F13R2_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F13R2_FB31 CAN_F13R2_FB31_Msk /*!< Filter bit 31 */
+
+/******************************************************************************/
+/* */
+/* Serial Peripheral Interface */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for SPI_CR1 register ********************/
+#define SPI_CR1_CPHA_Pos (0U)
+#define SPI_CR1_CPHA_Msk (0x1U << SPI_CR1_CPHA_Pos) /*!< 0x00000001 */
+#define SPI_CR1_CPHA SPI_CR1_CPHA_Msk /*!< Clock Phase */
+#define SPI_CR1_CPOL_Pos (1U)
+#define SPI_CR1_CPOL_Msk (0x1U << SPI_CR1_CPOL_Pos) /*!< 0x00000002 */
+#define SPI_CR1_CPOL SPI_CR1_CPOL_Msk /*!< Clock Polarity */
+#define SPI_CR1_MSTR_Pos (2U)
+#define SPI_CR1_MSTR_Msk (0x1U << SPI_CR1_MSTR_Pos) /*!< 0x00000004 */
+#define SPI_CR1_MSTR SPI_CR1_MSTR_Msk /*!< Master Selection */
+
+#define SPI_CR1_BR_Pos (3U)
+#define SPI_CR1_BR_Msk (0x7U << SPI_CR1_BR_Pos) /*!< 0x00000038 */
+#define SPI_CR1_BR SPI_CR1_BR_Msk /*!< BR[2:0] bits (Baud Rate Control) */
+#define SPI_CR1_BR_0 (0x1U << SPI_CR1_BR_Pos) /*!< 0x00000008 */
+#define SPI_CR1_BR_1 (0x2U << SPI_CR1_BR_Pos) /*!< 0x00000010 */
+#define SPI_CR1_BR_2 (0x4U << SPI_CR1_BR_Pos) /*!< 0x00000020 */
+
+#define SPI_CR1_SPE_Pos (6U)
+#define SPI_CR1_SPE_Msk (0x1U << SPI_CR1_SPE_Pos) /*!< 0x00000040 */
+#define SPI_CR1_SPE SPI_CR1_SPE_Msk /*!< SPI Enable */
+#define SPI_CR1_LSBFIRST_Pos (7U)
+#define SPI_CR1_LSBFIRST_Msk (0x1U << SPI_CR1_LSBFIRST_Pos) /*!< 0x00000080 */
+#define SPI_CR1_LSBFIRST SPI_CR1_LSBFIRST_Msk /*!< Frame Format */
+#define SPI_CR1_SSI_Pos (8U)
+#define SPI_CR1_SSI_Msk (0x1U << SPI_CR1_SSI_Pos) /*!< 0x00000100 */
+#define SPI_CR1_SSI SPI_CR1_SSI_Msk /*!< Internal slave select */
+#define SPI_CR1_SSM_Pos (9U)
+#define SPI_CR1_SSM_Msk (0x1U << SPI_CR1_SSM_Pos) /*!< 0x00000200 */
+#define SPI_CR1_SSM SPI_CR1_SSM_Msk /*!< Software slave management */
+#define SPI_CR1_RXONLY_Pos (10U)
+#define SPI_CR1_RXONLY_Msk (0x1U << SPI_CR1_RXONLY_Pos) /*!< 0x00000400 */
+#define SPI_CR1_RXONLY SPI_CR1_RXONLY_Msk /*!< Receive only */
+#define SPI_CR1_DFF_Pos (11U)
+#define SPI_CR1_DFF_Msk (0x1U << SPI_CR1_DFF_Pos) /*!< 0x00000800 */
+#define SPI_CR1_DFF SPI_CR1_DFF_Msk /*!< Data Frame Format */
+#define SPI_CR1_CRCNEXT_Pos (12U)
+#define SPI_CR1_CRCNEXT_Msk (0x1U << SPI_CR1_CRCNEXT_Pos) /*!< 0x00001000 */
+#define SPI_CR1_CRCNEXT SPI_CR1_CRCNEXT_Msk /*!< Transmit CRC next */
+#define SPI_CR1_CRCEN_Pos (13U)
+#define SPI_CR1_CRCEN_Msk (0x1U << SPI_CR1_CRCEN_Pos) /*!< 0x00002000 */
+#define SPI_CR1_CRCEN SPI_CR1_CRCEN_Msk /*!< Hardware CRC calculation enable */
+#define SPI_CR1_BIDIOE_Pos (14U)
+#define SPI_CR1_BIDIOE_Msk (0x1U << SPI_CR1_BIDIOE_Pos) /*!< 0x00004000 */
+#define SPI_CR1_BIDIOE SPI_CR1_BIDIOE_Msk /*!< Output enable in bidirectional mode */
+#define SPI_CR1_BIDIMODE_Pos (15U)
+#define SPI_CR1_BIDIMODE_Msk (0x1U << SPI_CR1_BIDIMODE_Pos) /*!< 0x00008000 */
+#define SPI_CR1_BIDIMODE SPI_CR1_BIDIMODE_Msk /*!< Bidirectional data mode enable */
+
+/******************* Bit definition for SPI_CR2 register ********************/
+#define SPI_CR2_RXDMAEN_Pos (0U)
+#define SPI_CR2_RXDMAEN_Msk (0x1U << SPI_CR2_RXDMAEN_Pos) /*!< 0x00000001 */
+#define SPI_CR2_RXDMAEN SPI_CR2_RXDMAEN_Msk /*!< Rx Buffer DMA Enable */
+#define SPI_CR2_TXDMAEN_Pos (1U)
+#define SPI_CR2_TXDMAEN_Msk (0x1U << SPI_CR2_TXDMAEN_Pos) /*!< 0x00000002 */
+#define SPI_CR2_TXDMAEN SPI_CR2_TXDMAEN_Msk /*!< Tx Buffer DMA Enable */
+#define SPI_CR2_SSOE_Pos (2U)
+#define SPI_CR2_SSOE_Msk (0x1U << SPI_CR2_SSOE_Pos) /*!< 0x00000004 */
+#define SPI_CR2_SSOE SPI_CR2_SSOE_Msk /*!< SS Output Enable */
+#define SPI_CR2_ERRIE_Pos (5U)
+#define SPI_CR2_ERRIE_Msk (0x1U << SPI_CR2_ERRIE_Pos) /*!< 0x00000020 */
+#define SPI_CR2_ERRIE SPI_CR2_ERRIE_Msk /*!< Error Interrupt Enable */
+#define SPI_CR2_RXNEIE_Pos (6U)
+#define SPI_CR2_RXNEIE_Msk (0x1U << SPI_CR2_RXNEIE_Pos) /*!< 0x00000040 */
+#define SPI_CR2_RXNEIE SPI_CR2_RXNEIE_Msk /*!< RX buffer Not Empty Interrupt Enable */
+#define SPI_CR2_TXEIE_Pos (7U)
+#define SPI_CR2_TXEIE_Msk (0x1U << SPI_CR2_TXEIE_Pos) /*!< 0x00000080 */
+#define SPI_CR2_TXEIE SPI_CR2_TXEIE_Msk /*!< Tx buffer Empty Interrupt Enable */
+
+/******************** Bit definition for SPI_SR register ********************/
+#define SPI_SR_RXNE_Pos (0U)
+#define SPI_SR_RXNE_Msk (0x1U << SPI_SR_RXNE_Pos) /*!< 0x00000001 */
+#define SPI_SR_RXNE SPI_SR_RXNE_Msk /*!< Receive buffer Not Empty */
+#define SPI_SR_TXE_Pos (1U)
+#define SPI_SR_TXE_Msk (0x1U << SPI_SR_TXE_Pos) /*!< 0x00000002 */
+#define SPI_SR_TXE SPI_SR_TXE_Msk /*!< Transmit buffer Empty */
+#define SPI_SR_CHSIDE_Pos (2U)
+#define SPI_SR_CHSIDE_Msk (0x1U << SPI_SR_CHSIDE_Pos) /*!< 0x00000004 */
+#define SPI_SR_CHSIDE SPI_SR_CHSIDE_Msk /*!< Channel side */
+#define SPI_SR_UDR_Pos (3U)
+#define SPI_SR_UDR_Msk (0x1U << SPI_SR_UDR_Pos) /*!< 0x00000008 */
+#define SPI_SR_UDR SPI_SR_UDR_Msk /*!< Underrun flag */
+#define SPI_SR_CRCERR_Pos (4U)
+#define SPI_SR_CRCERR_Msk (0x1U << SPI_SR_CRCERR_Pos) /*!< 0x00000010 */
+#define SPI_SR_CRCERR SPI_SR_CRCERR_Msk /*!< CRC Error flag */
+#define SPI_SR_MODF_Pos (5U)
+#define SPI_SR_MODF_Msk (0x1U << SPI_SR_MODF_Pos) /*!< 0x00000020 */
+#define SPI_SR_MODF SPI_SR_MODF_Msk /*!< Mode fault */
+#define SPI_SR_OVR_Pos (6U)
+#define SPI_SR_OVR_Msk (0x1U << SPI_SR_OVR_Pos) /*!< 0x00000040 */
+#define SPI_SR_OVR SPI_SR_OVR_Msk /*!< Overrun flag */
+#define SPI_SR_BSY_Pos (7U)
+#define SPI_SR_BSY_Msk (0x1U << SPI_SR_BSY_Pos) /*!< 0x00000080 */
+#define SPI_SR_BSY SPI_SR_BSY_Msk /*!< Busy flag */
+
+/******************** Bit definition for SPI_DR register ********************/
+#define SPI_DR_DR_Pos (0U)
+#define SPI_DR_DR_Msk (0xFFFFU << SPI_DR_DR_Pos) /*!< 0x0000FFFF */
+#define SPI_DR_DR SPI_DR_DR_Msk /*!< Data Register */
+
+/******************* Bit definition for SPI_CRCPR register ******************/
+#define SPI_CRCPR_CRCPOLY_Pos (0U)
+#define SPI_CRCPR_CRCPOLY_Msk (0xFFFFU << SPI_CRCPR_CRCPOLY_Pos) /*!< 0x0000FFFF */
+#define SPI_CRCPR_CRCPOLY SPI_CRCPR_CRCPOLY_Msk /*!< CRC polynomial register */
+
+/****************** Bit definition for SPI_RXCRCR register ******************/
+#define SPI_RXCRCR_RXCRC_Pos (0U)
+#define SPI_RXCRCR_RXCRC_Msk (0xFFFFU << SPI_RXCRCR_RXCRC_Pos) /*!< 0x0000FFFF */
+#define SPI_RXCRCR_RXCRC SPI_RXCRCR_RXCRC_Msk /*!< Rx CRC Register */
+
+/****************** Bit definition for SPI_TXCRCR register ******************/
+#define SPI_TXCRCR_TXCRC_Pos (0U)
+#define SPI_TXCRCR_TXCRC_Msk (0xFFFFU << SPI_TXCRCR_TXCRC_Pos) /*!< 0x0000FFFF */
+#define SPI_TXCRCR_TXCRC SPI_TXCRCR_TXCRC_Msk /*!< Tx CRC Register */
+
+/****************** Bit definition for SPI_I2SCFGR register *****************/
+#define SPI_I2SCFGR_CHLEN_Pos (0U)
+#define SPI_I2SCFGR_CHLEN_Msk (0x1U << SPI_I2SCFGR_CHLEN_Pos) /*!< 0x00000001 */
+#define SPI_I2SCFGR_CHLEN SPI_I2SCFGR_CHLEN_Msk /*!< Channel length (number of bits per audio channel) */
+
+#define SPI_I2SCFGR_DATLEN_Pos (1U)
+#define SPI_I2SCFGR_DATLEN_Msk (0x3U << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000006 */
+#define SPI_I2SCFGR_DATLEN SPI_I2SCFGR_DATLEN_Msk /*!< DATLEN[1:0] bits (Data length to be transferred) */
+#define SPI_I2SCFGR_DATLEN_0 (0x1U << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000002 */
+#define SPI_I2SCFGR_DATLEN_1 (0x2U << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000004 */
+
+#define SPI_I2SCFGR_CKPOL_Pos (3U)
+#define SPI_I2SCFGR_CKPOL_Msk (0x1U << SPI_I2SCFGR_CKPOL_Pos) /*!< 0x00000008 */
+#define SPI_I2SCFGR_CKPOL SPI_I2SCFGR_CKPOL_Msk /*!< steady state clock polarity */
+
+#define SPI_I2SCFGR_I2SSTD_Pos (4U)
+#define SPI_I2SCFGR_I2SSTD_Msk (0x3U << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000030 */
+#define SPI_I2SCFGR_I2SSTD SPI_I2SCFGR_I2SSTD_Msk /*!< I2SSTD[1:0] bits (I2S standard selection) */
+#define SPI_I2SCFGR_I2SSTD_0 (0x1U << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000010 */
+#define SPI_I2SCFGR_I2SSTD_1 (0x2U << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000020 */
+
+#define SPI_I2SCFGR_PCMSYNC_Pos (7U)
+#define SPI_I2SCFGR_PCMSYNC_Msk (0x1U << SPI_I2SCFGR_PCMSYNC_Pos) /*!< 0x00000080 */
+#define SPI_I2SCFGR_PCMSYNC SPI_I2SCFGR_PCMSYNC_Msk /*!< PCM frame synchronization */
+
+#define SPI_I2SCFGR_I2SCFG_Pos (8U)
+#define SPI_I2SCFGR_I2SCFG_Msk (0x3U << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000300 */
+#define SPI_I2SCFGR_I2SCFG SPI_I2SCFGR_I2SCFG_Msk /*!< I2SCFG[1:0] bits (I2S configuration mode) */
+#define SPI_I2SCFGR_I2SCFG_0 (0x1U << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000100 */
+#define SPI_I2SCFGR_I2SCFG_1 (0x2U << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000200 */
+
+#define SPI_I2SCFGR_I2SE_Pos (10U)
+#define SPI_I2SCFGR_I2SE_Msk (0x1U << SPI_I2SCFGR_I2SE_Pos) /*!< 0x00000400 */
+#define SPI_I2SCFGR_I2SE SPI_I2SCFGR_I2SE_Msk /*!< I2S Enable */
+#define SPI_I2SCFGR_I2SMOD_Pos (11U)
+#define SPI_I2SCFGR_I2SMOD_Msk (0x1U << SPI_I2SCFGR_I2SMOD_Pos) /*!< 0x00000800 */
+#define SPI_I2SCFGR_I2SMOD SPI_I2SCFGR_I2SMOD_Msk /*!< I2S mode selection */
+
+/****************** Bit definition for SPI_I2SPR register *******************/
+#define SPI_I2SPR_I2SDIV_Pos (0U)
+#define SPI_I2SPR_I2SDIV_Msk (0xFFU << SPI_I2SPR_I2SDIV_Pos) /*!< 0x000000FF */
+#define SPI_I2SPR_I2SDIV SPI_I2SPR_I2SDIV_Msk /*!< I2S Linear prescaler */
+#define SPI_I2SPR_ODD_Pos (8U)
+#define SPI_I2SPR_ODD_Msk (0x1U << SPI_I2SPR_ODD_Pos) /*!< 0x00000100 */
+#define SPI_I2SPR_ODD SPI_I2SPR_ODD_Msk /*!< Odd factor for the prescaler */
+#define SPI_I2SPR_MCKOE_Pos (9U)
+#define SPI_I2SPR_MCKOE_Msk (0x1U << SPI_I2SPR_MCKOE_Pos) /*!< 0x00000200 */
+#define SPI_I2SPR_MCKOE SPI_I2SPR_MCKOE_Msk /*!< Master Clock Output Enable */
+
+/******************************************************************************/
+/* */
+/* Inter-integrated Circuit Interface */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for I2C_CR1 register ********************/
+#define I2C_CR1_PE_Pos (0U)
+#define I2C_CR1_PE_Msk (0x1U << I2C_CR1_PE_Pos) /*!< 0x00000001 */
+#define I2C_CR1_PE I2C_CR1_PE_Msk /*!< Peripheral Enable */
+#define I2C_CR1_SMBUS_Pos (1U)
+#define I2C_CR1_SMBUS_Msk (0x1U << I2C_CR1_SMBUS_Pos) /*!< 0x00000002 */
+#define I2C_CR1_SMBUS I2C_CR1_SMBUS_Msk /*!< SMBus Mode */
+#define I2C_CR1_SMBTYPE_Pos (3U)
+#define I2C_CR1_SMBTYPE_Msk (0x1U << I2C_CR1_SMBTYPE_Pos) /*!< 0x00000008 */
+#define I2C_CR1_SMBTYPE I2C_CR1_SMBTYPE_Msk /*!< SMBus Type */
+#define I2C_CR1_ENARP_Pos (4U)
+#define I2C_CR1_ENARP_Msk (0x1U << I2C_CR1_ENARP_Pos) /*!< 0x00000010 */
+#define I2C_CR1_ENARP I2C_CR1_ENARP_Msk /*!< ARP Enable */
+#define I2C_CR1_ENPEC_Pos (5U)
+#define I2C_CR1_ENPEC_Msk (0x1U << I2C_CR1_ENPEC_Pos) /*!< 0x00000020 */
+#define I2C_CR1_ENPEC I2C_CR1_ENPEC_Msk /*!< PEC Enable */
+#define I2C_CR1_ENGC_Pos (6U)
+#define I2C_CR1_ENGC_Msk (0x1U << I2C_CR1_ENGC_Pos) /*!< 0x00000040 */
+#define I2C_CR1_ENGC I2C_CR1_ENGC_Msk /*!< General Call Enable */
+#define I2C_CR1_NOSTRETCH_Pos (7U)
+#define I2C_CR1_NOSTRETCH_Msk (0x1U << I2C_CR1_NOSTRETCH_Pos) /*!< 0x00000080 */
+#define I2C_CR1_NOSTRETCH I2C_CR1_NOSTRETCH_Msk /*!< Clock Stretching Disable (Slave mode) */
+#define I2C_CR1_START_Pos (8U)
+#define I2C_CR1_START_Msk (0x1U << I2C_CR1_START_Pos) /*!< 0x00000100 */
+#define I2C_CR1_START I2C_CR1_START_Msk /*!< Start Generation */
+#define I2C_CR1_STOP_Pos (9U)
+#define I2C_CR1_STOP_Msk (0x1U << I2C_CR1_STOP_Pos) /*!< 0x00000200 */
+#define I2C_CR1_STOP I2C_CR1_STOP_Msk /*!< Stop Generation */
+#define I2C_CR1_ACK_Pos (10U)
+#define I2C_CR1_ACK_Msk (0x1U << I2C_CR1_ACK_Pos) /*!< 0x00000400 */
+#define I2C_CR1_ACK I2C_CR1_ACK_Msk /*!< Acknowledge Enable */
+#define I2C_CR1_POS_Pos (11U)
+#define I2C_CR1_POS_Msk (0x1U << I2C_CR1_POS_Pos) /*!< 0x00000800 */
+#define I2C_CR1_POS I2C_CR1_POS_Msk /*!< Acknowledge/PEC Position (for data reception) */
+#define I2C_CR1_PEC_Pos (12U)
+#define I2C_CR1_PEC_Msk (0x1U << I2C_CR1_PEC_Pos) /*!< 0x00001000 */
+#define I2C_CR1_PEC I2C_CR1_PEC_Msk /*!< Packet Error Checking */
+#define I2C_CR1_ALERT_Pos (13U)
+#define I2C_CR1_ALERT_Msk (0x1U << I2C_CR1_ALERT_Pos) /*!< 0x00002000 */
+#define I2C_CR1_ALERT I2C_CR1_ALERT_Msk /*!< SMBus Alert */
+#define I2C_CR1_SWRST_Pos (15U)
+#define I2C_CR1_SWRST_Msk (0x1U << I2C_CR1_SWRST_Pos) /*!< 0x00008000 */
+#define I2C_CR1_SWRST I2C_CR1_SWRST_Msk /*!< Software Reset */
+
+/******************* Bit definition for I2C_CR2 register ********************/
+#define I2C_CR2_FREQ_Pos (0U)
+#define I2C_CR2_FREQ_Msk (0x3FU << I2C_CR2_FREQ_Pos) /*!< 0x0000003F */
+#define I2C_CR2_FREQ I2C_CR2_FREQ_Msk /*!< FREQ[5:0] bits (Peripheral Clock Frequency) */
+#define I2C_CR2_FREQ_0 (0x01U << I2C_CR2_FREQ_Pos) /*!< 0x00000001 */
+#define I2C_CR2_FREQ_1 (0x02U << I2C_CR2_FREQ_Pos) /*!< 0x00000002 */
+#define I2C_CR2_FREQ_2 (0x04U << I2C_CR2_FREQ_Pos) /*!< 0x00000004 */
+#define I2C_CR2_FREQ_3 (0x08U << I2C_CR2_FREQ_Pos) /*!< 0x00000008 */
+#define I2C_CR2_FREQ_4 (0x10U << I2C_CR2_FREQ_Pos) /*!< 0x00000010 */
+#define I2C_CR2_FREQ_5 (0x20U << I2C_CR2_FREQ_Pos) /*!< 0x00000020 */
+
+#define I2C_CR2_ITERREN_Pos (8U)
+#define I2C_CR2_ITERREN_Msk (0x1U << I2C_CR2_ITERREN_Pos) /*!< 0x00000100 */
+#define I2C_CR2_ITERREN I2C_CR2_ITERREN_Msk /*!< Error Interrupt Enable */
+#define I2C_CR2_ITEVTEN_Pos (9U)
+#define I2C_CR2_ITEVTEN_Msk (0x1U << I2C_CR2_ITEVTEN_Pos) /*!< 0x00000200 */
+#define I2C_CR2_ITEVTEN I2C_CR2_ITEVTEN_Msk /*!< Event Interrupt Enable */
+#define I2C_CR2_ITBUFEN_Pos (10U)
+#define I2C_CR2_ITBUFEN_Msk (0x1U << I2C_CR2_ITBUFEN_Pos) /*!< 0x00000400 */
+#define I2C_CR2_ITBUFEN I2C_CR2_ITBUFEN_Msk /*!< Buffer Interrupt Enable */
+#define I2C_CR2_DMAEN_Pos (11U)
+#define I2C_CR2_DMAEN_Msk (0x1U << I2C_CR2_DMAEN_Pos) /*!< 0x00000800 */
+#define I2C_CR2_DMAEN I2C_CR2_DMAEN_Msk /*!< DMA Requests Enable */
+#define I2C_CR2_LAST_Pos (12U)
+#define I2C_CR2_LAST_Msk (0x1U << I2C_CR2_LAST_Pos) /*!< 0x00001000 */
+#define I2C_CR2_LAST I2C_CR2_LAST_Msk /*!< DMA Last Transfer */
+
+/******************* Bit definition for I2C_OAR1 register *******************/
+#define I2C_OAR1_ADD1_7 ((uint32_t)0x000000FE) /*!< Interface Address */
+#define I2C_OAR1_ADD8_9 ((uint32_t)0x00000300) /*!< Interface Address */
+
+#define I2C_OAR1_ADD0_Pos (0U)
+#define I2C_OAR1_ADD0_Msk (0x1U << I2C_OAR1_ADD0_Pos) /*!< 0x00000001 */
+#define I2C_OAR1_ADD0 I2C_OAR1_ADD0_Msk /*!< Bit 0 */
+#define I2C_OAR1_ADD1_Pos (1U)
+#define I2C_OAR1_ADD1_Msk (0x1U << I2C_OAR1_ADD1_Pos) /*!< 0x00000002 */
+#define I2C_OAR1_ADD1 I2C_OAR1_ADD1_Msk /*!< Bit 1 */
+#define I2C_OAR1_ADD2_Pos (2U)
+#define I2C_OAR1_ADD2_Msk (0x1U << I2C_OAR1_ADD2_Pos) /*!< 0x00000004 */
+#define I2C_OAR1_ADD2 I2C_OAR1_ADD2_Msk /*!< Bit 2 */
+#define I2C_OAR1_ADD3_Pos (3U)
+#define I2C_OAR1_ADD3_Msk (0x1U << I2C_OAR1_ADD3_Pos) /*!< 0x00000008 */
+#define I2C_OAR1_ADD3 I2C_OAR1_ADD3_Msk /*!< Bit 3 */
+#define I2C_OAR1_ADD4_Pos (4U)
+#define I2C_OAR1_ADD4_Msk (0x1U << I2C_OAR1_ADD4_Pos) /*!< 0x00000010 */
+#define I2C_OAR1_ADD4 I2C_OAR1_ADD4_Msk /*!< Bit 4 */
+#define I2C_OAR1_ADD5_Pos (5U)
+#define I2C_OAR1_ADD5_Msk (0x1U << I2C_OAR1_ADD5_Pos) /*!< 0x00000020 */
+#define I2C_OAR1_ADD5 I2C_OAR1_ADD5_Msk /*!< Bit 5 */
+#define I2C_OAR1_ADD6_Pos (6U)
+#define I2C_OAR1_ADD6_Msk (0x1U << I2C_OAR1_ADD6_Pos) /*!< 0x00000040 */
+#define I2C_OAR1_ADD6 I2C_OAR1_ADD6_Msk /*!< Bit 6 */
+#define I2C_OAR1_ADD7_Pos (7U)
+#define I2C_OAR1_ADD7_Msk (0x1U << I2C_OAR1_ADD7_Pos) /*!< 0x00000080 */
+#define I2C_OAR1_ADD7 I2C_OAR1_ADD7_Msk /*!< Bit 7 */
+#define I2C_OAR1_ADD8_Pos (8U)
+#define I2C_OAR1_ADD8_Msk (0x1U << I2C_OAR1_ADD8_Pos) /*!< 0x00000100 */
+#define I2C_OAR1_ADD8 I2C_OAR1_ADD8_Msk /*!< Bit 8 */
+#define I2C_OAR1_ADD9_Pos (9U)
+#define I2C_OAR1_ADD9_Msk (0x1U << I2C_OAR1_ADD9_Pos) /*!< 0x00000200 */
+#define I2C_OAR1_ADD9 I2C_OAR1_ADD9_Msk /*!< Bit 9 */
+
+#define I2C_OAR1_ADDMODE_Pos (15U)
+#define I2C_OAR1_ADDMODE_Msk (0x1U << I2C_OAR1_ADDMODE_Pos) /*!< 0x00008000 */
+#define I2C_OAR1_ADDMODE I2C_OAR1_ADDMODE_Msk /*!< Addressing Mode (Slave mode) */
+
+/******************* Bit definition for I2C_OAR2 register *******************/
+#define I2C_OAR2_ENDUAL_Pos (0U)
+#define I2C_OAR2_ENDUAL_Msk (0x1U << I2C_OAR2_ENDUAL_Pos) /*!< 0x00000001 */
+#define I2C_OAR2_ENDUAL I2C_OAR2_ENDUAL_Msk /*!< Dual addressing mode enable */
+#define I2C_OAR2_ADD2_Pos (1U)
+#define I2C_OAR2_ADD2_Msk (0x7FU << I2C_OAR2_ADD2_Pos) /*!< 0x000000FE */
+#define I2C_OAR2_ADD2 I2C_OAR2_ADD2_Msk /*!< Interface address */
+
+/******************* Bit definition for I2C_SR1 register ********************/
+#define I2C_SR1_SB_Pos (0U)
+#define I2C_SR1_SB_Msk (0x1U << I2C_SR1_SB_Pos) /*!< 0x00000001 */
+#define I2C_SR1_SB I2C_SR1_SB_Msk /*!< Start Bit (Master mode) */
+#define I2C_SR1_ADDR_Pos (1U)
+#define I2C_SR1_ADDR_Msk (0x1U << I2C_SR1_ADDR_Pos) /*!< 0x00000002 */
+#define I2C_SR1_ADDR I2C_SR1_ADDR_Msk /*!< Address sent (master mode)/matched (slave mode) */
+#define I2C_SR1_BTF_Pos (2U)
+#define I2C_SR1_BTF_Msk (0x1U << I2C_SR1_BTF_Pos) /*!< 0x00000004 */
+#define I2C_SR1_BTF I2C_SR1_BTF_Msk /*!< Byte Transfer Finished */
+#define I2C_SR1_ADD10_Pos (3U)
+#define I2C_SR1_ADD10_Msk (0x1U << I2C_SR1_ADD10_Pos) /*!< 0x00000008 */
+#define I2C_SR1_ADD10 I2C_SR1_ADD10_Msk /*!< 10-bit header sent (Master mode) */
+#define I2C_SR1_STOPF_Pos (4U)
+#define I2C_SR1_STOPF_Msk (0x1U << I2C_SR1_STOPF_Pos) /*!< 0x00000010 */
+#define I2C_SR1_STOPF I2C_SR1_STOPF_Msk /*!< Stop detection (Slave mode) */
+#define I2C_SR1_RXNE_Pos (6U)
+#define I2C_SR1_RXNE_Msk (0x1U << I2C_SR1_RXNE_Pos) /*!< 0x00000040 */
+#define I2C_SR1_RXNE I2C_SR1_RXNE_Msk /*!< Data Register not Empty (receivers) */
+#define I2C_SR1_TXE_Pos (7U)
+#define I2C_SR1_TXE_Msk (0x1U << I2C_SR1_TXE_Pos) /*!< 0x00000080 */
+#define I2C_SR1_TXE I2C_SR1_TXE_Msk /*!< Data Register Empty (transmitters) */
+#define I2C_SR1_BERR_Pos (8U)
+#define I2C_SR1_BERR_Msk (0x1U << I2C_SR1_BERR_Pos) /*!< 0x00000100 */
+#define I2C_SR1_BERR I2C_SR1_BERR_Msk /*!< Bus Error */
+#define I2C_SR1_ARLO_Pos (9U)
+#define I2C_SR1_ARLO_Msk (0x1U << I2C_SR1_ARLO_Pos) /*!< 0x00000200 */
+#define I2C_SR1_ARLO I2C_SR1_ARLO_Msk /*!< Arbitration Lost (master mode) */
+#define I2C_SR1_AF_Pos (10U)
+#define I2C_SR1_AF_Msk (0x1U << I2C_SR1_AF_Pos) /*!< 0x00000400 */
+#define I2C_SR1_AF I2C_SR1_AF_Msk /*!< Acknowledge Failure */
+#define I2C_SR1_OVR_Pos (11U)
+#define I2C_SR1_OVR_Msk (0x1U << I2C_SR1_OVR_Pos) /*!< 0x00000800 */
+#define I2C_SR1_OVR I2C_SR1_OVR_Msk /*!< Overrun/Underrun */
+#define I2C_SR1_PECERR_Pos (12U)
+#define I2C_SR1_PECERR_Msk (0x1U << I2C_SR1_PECERR_Pos) /*!< 0x00001000 */
+#define I2C_SR1_PECERR I2C_SR1_PECERR_Msk /*!< PEC Error in reception */
+#define I2C_SR1_TIMEOUT_Pos (14U)
+#define I2C_SR1_TIMEOUT_Msk (0x1U << I2C_SR1_TIMEOUT_Pos) /*!< 0x00004000 */
+#define I2C_SR1_TIMEOUT I2C_SR1_TIMEOUT_Msk /*!< Timeout or Tlow Error */
+#define I2C_SR1_SMBALERT_Pos (15U)
+#define I2C_SR1_SMBALERT_Msk (0x1U << I2C_SR1_SMBALERT_Pos) /*!< 0x00008000 */
+#define I2C_SR1_SMBALERT I2C_SR1_SMBALERT_Msk /*!< SMBus Alert */
+
+/******************* Bit definition for I2C_SR2 register ********************/
+#define I2C_SR2_MSL_Pos (0U)
+#define I2C_SR2_MSL_Msk (0x1U << I2C_SR2_MSL_Pos) /*!< 0x00000001 */
+#define I2C_SR2_MSL I2C_SR2_MSL_Msk /*!< Master/Slave */
+#define I2C_SR2_BUSY_Pos (1U)
+#define I2C_SR2_BUSY_Msk (0x1U << I2C_SR2_BUSY_Pos) /*!< 0x00000002 */
+#define I2C_SR2_BUSY I2C_SR2_BUSY_Msk /*!< Bus Busy */
+#define I2C_SR2_TRA_Pos (2U)
+#define I2C_SR2_TRA_Msk (0x1U << I2C_SR2_TRA_Pos) /*!< 0x00000004 */
+#define I2C_SR2_TRA I2C_SR2_TRA_Msk /*!< Transmitter/Receiver */
+#define I2C_SR2_GENCALL_Pos (4U)
+#define I2C_SR2_GENCALL_Msk (0x1U << I2C_SR2_GENCALL_Pos) /*!< 0x00000010 */
+#define I2C_SR2_GENCALL I2C_SR2_GENCALL_Msk /*!< General Call Address (Slave mode) */
+#define I2C_SR2_SMBDEFAULT_Pos (5U)
+#define I2C_SR2_SMBDEFAULT_Msk (0x1U << I2C_SR2_SMBDEFAULT_Pos) /*!< 0x00000020 */
+#define I2C_SR2_SMBDEFAULT I2C_SR2_SMBDEFAULT_Msk /*!< SMBus Device Default Address (Slave mode) */
+#define I2C_SR2_SMBHOST_Pos (6U)
+#define I2C_SR2_SMBHOST_Msk (0x1U << I2C_SR2_SMBHOST_Pos) /*!< 0x00000040 */
+#define I2C_SR2_SMBHOST I2C_SR2_SMBHOST_Msk /*!< SMBus Host Header (Slave mode) */
+#define I2C_SR2_DUALF_Pos (7U)
+#define I2C_SR2_DUALF_Msk (0x1U << I2C_SR2_DUALF_Pos) /*!< 0x00000080 */
+#define I2C_SR2_DUALF I2C_SR2_DUALF_Msk /*!< Dual Flag (Slave mode) */
+#define I2C_SR2_PEC_Pos (8U)
+#define I2C_SR2_PEC_Msk (0xFFU << I2C_SR2_PEC_Pos) /*!< 0x0000FF00 */
+#define I2C_SR2_PEC I2C_SR2_PEC_Msk /*!< Packet Error Checking Register */
+
+/******************* Bit definition for I2C_CCR register ********************/
+#define I2C_CCR_CCR_Pos (0U)
+#define I2C_CCR_CCR_Msk (0xFFFU << I2C_CCR_CCR_Pos) /*!< 0x00000FFF */
+#define I2C_CCR_CCR I2C_CCR_CCR_Msk /*!< Clock Control Register in Fast/Standard mode (Master mode) */
+#define I2C_CCR_DUTY_Pos (14U)
+#define I2C_CCR_DUTY_Msk (0x1U << I2C_CCR_DUTY_Pos) /*!< 0x00004000 */
+#define I2C_CCR_DUTY I2C_CCR_DUTY_Msk /*!< Fast Mode Duty Cycle */
+#define I2C_CCR_FS_Pos (15U)
+#define I2C_CCR_FS_Msk (0x1U << I2C_CCR_FS_Pos) /*!< 0x00008000 */
+#define I2C_CCR_FS I2C_CCR_FS_Msk /*!< I2C Master Mode Selection */
+
+/****************** Bit definition for I2C_TRISE register *******************/
+#define I2C_TRISE_TRISE_Pos (0U)
+#define I2C_TRISE_TRISE_Msk (0x3FU << I2C_TRISE_TRISE_Pos) /*!< 0x0000003F */
+#define I2C_TRISE_TRISE I2C_TRISE_TRISE_Msk /*!< Maximum Rise Time in Fast/Standard mode (Master mode) */
+
+/******************************************************************************/
+/* */
+/* Universal Synchronous Asynchronous Receiver Transmitter */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for USART_SR register *******************/
+#define USART_SR_PE_Pos (0U)
+#define USART_SR_PE_Msk (0x1U << USART_SR_PE_Pos) /*!< 0x00000001 */
+#define USART_SR_PE USART_SR_PE_Msk /*!< Parity Error */
+#define USART_SR_FE_Pos (1U)
+#define USART_SR_FE_Msk (0x1U << USART_SR_FE_Pos) /*!< 0x00000002 */
+#define USART_SR_FE USART_SR_FE_Msk /*!< Framing Error */
+#define USART_SR_NE_Pos (2U)
+#define USART_SR_NE_Msk (0x1U << USART_SR_NE_Pos) /*!< 0x00000004 */
+#define USART_SR_NE USART_SR_NE_Msk /*!< Noise Error Flag */
+#define USART_SR_ORE_Pos (3U)
+#define USART_SR_ORE_Msk (0x1U << USART_SR_ORE_Pos) /*!< 0x00000008 */
+#define USART_SR_ORE USART_SR_ORE_Msk /*!< OverRun Error */
+#define USART_SR_IDLE_Pos (4U)
+#define USART_SR_IDLE_Msk (0x1U << USART_SR_IDLE_Pos) /*!< 0x00000010 */
+#define USART_SR_IDLE USART_SR_IDLE_Msk /*!< IDLE line detected */
+#define USART_SR_RXNE_Pos (5U)
+#define USART_SR_RXNE_Msk (0x1U << USART_SR_RXNE_Pos) /*!< 0x00000020 */
+#define USART_SR_RXNE USART_SR_RXNE_Msk /*!< Read Data Register Not Empty */
+#define USART_SR_TC_Pos (6U)
+#define USART_SR_TC_Msk (0x1U << USART_SR_TC_Pos) /*!< 0x00000040 */
+#define USART_SR_TC USART_SR_TC_Msk /*!< Transmission Complete */
+#define USART_SR_TXE_Pos (7U)
+#define USART_SR_TXE_Msk (0x1U << USART_SR_TXE_Pos) /*!< 0x00000080 */
+#define USART_SR_TXE USART_SR_TXE_Msk /*!< Transmit Data Register Empty */
+#define USART_SR_LBD_Pos (8U)
+#define USART_SR_LBD_Msk (0x1U << USART_SR_LBD_Pos) /*!< 0x00000100 */
+#define USART_SR_LBD USART_SR_LBD_Msk /*!< LIN Break Detection Flag */
+#define USART_SR_CTS_Pos (9U)
+#define USART_SR_CTS_Msk (0x1U << USART_SR_CTS_Pos) /*!< 0x00000200 */
+#define USART_SR_CTS USART_SR_CTS_Msk /*!< CTS Flag */
+
+/******************* Bit definition for USART_DR register *******************/
+#define USART_DR_DR_Pos (0U)
+#define USART_DR_DR_Msk (0x1FFU << USART_DR_DR_Pos) /*!< 0x000001FF */
+#define USART_DR_DR USART_DR_DR_Msk /*!< Data value */
+
+/****************** Bit definition for USART_BRR register *******************/
+#define USART_BRR_DIV_Fraction_Pos (0U)
+#define USART_BRR_DIV_Fraction_Msk (0xFU << USART_BRR_DIV_Fraction_Pos) /*!< 0x0000000F */
+#define USART_BRR_DIV_Fraction USART_BRR_DIV_Fraction_Msk /*!< Fraction of USARTDIV */
+#define USART_BRR_DIV_Mantissa_Pos (4U)
+#define USART_BRR_DIV_Mantissa_Msk (0xFFFU << USART_BRR_DIV_Mantissa_Pos) /*!< 0x0000FFF0 */
+#define USART_BRR_DIV_Mantissa USART_BRR_DIV_Mantissa_Msk /*!< Mantissa of USARTDIV */
+
+/****************** Bit definition for USART_CR1 register *******************/
+#define USART_CR1_SBK_Pos (0U)
+#define USART_CR1_SBK_Msk (0x1U << USART_CR1_SBK_Pos) /*!< 0x00000001 */
+#define USART_CR1_SBK USART_CR1_SBK_Msk /*!< Send Break */
+#define USART_CR1_RWU_Pos (1U)
+#define USART_CR1_RWU_Msk (0x1U << USART_CR1_RWU_Pos) /*!< 0x00000002 */
+#define USART_CR1_RWU USART_CR1_RWU_Msk /*!< Receiver wakeup */
+#define USART_CR1_RE_Pos (2U)
+#define USART_CR1_RE_Msk (0x1U << USART_CR1_RE_Pos) /*!< 0x00000004 */
+#define USART_CR1_RE USART_CR1_RE_Msk /*!< Receiver Enable */
+#define USART_CR1_TE_Pos (3U)
+#define USART_CR1_TE_Msk (0x1U << USART_CR1_TE_Pos) /*!< 0x00000008 */
+#define USART_CR1_TE USART_CR1_TE_Msk /*!< Transmitter Enable */
+#define USART_CR1_IDLEIE_Pos (4U)
+#define USART_CR1_IDLEIE_Msk (0x1U << USART_CR1_IDLEIE_Pos) /*!< 0x00000010 */
+#define USART_CR1_IDLEIE USART_CR1_IDLEIE_Msk /*!< IDLE Interrupt Enable */
+#define USART_CR1_RXNEIE_Pos (5U)
+#define USART_CR1_RXNEIE_Msk (0x1U << USART_CR1_RXNEIE_Pos) /*!< 0x00000020 */
+#define USART_CR1_RXNEIE USART_CR1_RXNEIE_Msk /*!< RXNE Interrupt Enable */
+#define USART_CR1_TCIE_Pos (6U)
+#define USART_CR1_TCIE_Msk (0x1U << USART_CR1_TCIE_Pos) /*!< 0x00000040 */
+#define USART_CR1_TCIE USART_CR1_TCIE_Msk /*!< Transmission Complete Interrupt Enable */
+#define USART_CR1_TXEIE_Pos (7U)
+#define USART_CR1_TXEIE_Msk (0x1U << USART_CR1_TXEIE_Pos) /*!< 0x00000080 */
+#define USART_CR1_TXEIE USART_CR1_TXEIE_Msk /*!< PE Interrupt Enable */
+#define USART_CR1_PEIE_Pos (8U)
+#define USART_CR1_PEIE_Msk (0x1U << USART_CR1_PEIE_Pos) /*!< 0x00000100 */
+#define USART_CR1_PEIE USART_CR1_PEIE_Msk /*!< PE Interrupt Enable */
+#define USART_CR1_PS_Pos (9U)
+#define USART_CR1_PS_Msk (0x1U << USART_CR1_PS_Pos) /*!< 0x00000200 */
+#define USART_CR1_PS USART_CR1_PS_Msk /*!< Parity Selection */
+#define USART_CR1_PCE_Pos (10U)
+#define USART_CR1_PCE_Msk (0x1U << USART_CR1_PCE_Pos) /*!< 0x00000400 */
+#define USART_CR1_PCE USART_CR1_PCE_Msk /*!< Parity Control Enable */
+#define USART_CR1_WAKE_Pos (11U)
+#define USART_CR1_WAKE_Msk (0x1U << USART_CR1_WAKE_Pos) /*!< 0x00000800 */
+#define USART_CR1_WAKE USART_CR1_WAKE_Msk /*!< Wakeup method */
+#define USART_CR1_M_Pos (12U)
+#define USART_CR1_M_Msk (0x1U << USART_CR1_M_Pos) /*!< 0x00001000 */
+#define USART_CR1_M USART_CR1_M_Msk /*!< Word length */
+#define USART_CR1_UE_Pos (13U)
+#define USART_CR1_UE_Msk (0x1U << USART_CR1_UE_Pos) /*!< 0x00002000 */
+#define USART_CR1_UE USART_CR1_UE_Msk /*!< USART Enable */
+
+/****************** Bit definition for USART_CR2 register *******************/
+#define USART_CR2_ADD_Pos (0U)
+#define USART_CR2_ADD_Msk (0xFU << USART_CR2_ADD_Pos) /*!< 0x0000000F */
+#define USART_CR2_ADD USART_CR2_ADD_Msk /*!< Address of the USART node */
+#define USART_CR2_LBDL_Pos (5U)
+#define USART_CR2_LBDL_Msk (0x1U << USART_CR2_LBDL_Pos) /*!< 0x00000020 */
+#define USART_CR2_LBDL USART_CR2_LBDL_Msk /*!< LIN Break Detection Length */
+#define USART_CR2_LBDIE_Pos (6U)
+#define USART_CR2_LBDIE_Msk (0x1U << USART_CR2_LBDIE_Pos) /*!< 0x00000040 */
+#define USART_CR2_LBDIE USART_CR2_LBDIE_Msk /*!< LIN Break Detection Interrupt Enable */
+#define USART_CR2_LBCL_Pos (8U)
+#define USART_CR2_LBCL_Msk (0x1U << USART_CR2_LBCL_Pos) /*!< 0x00000100 */
+#define USART_CR2_LBCL USART_CR2_LBCL_Msk /*!< Last Bit Clock pulse */
+#define USART_CR2_CPHA_Pos (9U)
+#define USART_CR2_CPHA_Msk (0x1U << USART_CR2_CPHA_Pos) /*!< 0x00000200 */
+#define USART_CR2_CPHA USART_CR2_CPHA_Msk /*!< Clock Phase */
+#define USART_CR2_CPOL_Pos (10U)
+#define USART_CR2_CPOL_Msk (0x1U << USART_CR2_CPOL_Pos) /*!< 0x00000400 */
+#define USART_CR2_CPOL USART_CR2_CPOL_Msk /*!< Clock Polarity */
+#define USART_CR2_CLKEN_Pos (11U)
+#define USART_CR2_CLKEN_Msk (0x1U << USART_CR2_CLKEN_Pos) /*!< 0x00000800 */
+#define USART_CR2_CLKEN USART_CR2_CLKEN_Msk /*!< Clock Enable */
+
+#define USART_CR2_STOP_Pos (12U)
+#define USART_CR2_STOP_Msk (0x3U << USART_CR2_STOP_Pos) /*!< 0x00003000 */
+#define USART_CR2_STOP USART_CR2_STOP_Msk /*!< STOP[1:0] bits (STOP bits) */
+#define USART_CR2_STOP_0 (0x1U << USART_CR2_STOP_Pos) /*!< 0x00001000 */
+#define USART_CR2_STOP_1 (0x2U << USART_CR2_STOP_Pos) /*!< 0x00002000 */
+
+#define USART_CR2_LINEN_Pos (14U)
+#define USART_CR2_LINEN_Msk (0x1U << USART_CR2_LINEN_Pos) /*!< 0x00004000 */
+#define USART_CR2_LINEN USART_CR2_LINEN_Msk /*!< LIN mode enable */
+
+/****************** Bit definition for USART_CR3 register *******************/
+#define USART_CR3_EIE_Pos (0U)
+#define USART_CR3_EIE_Msk (0x1U << USART_CR3_EIE_Pos) /*!< 0x00000001 */
+#define USART_CR3_EIE USART_CR3_EIE_Msk /*!< Error Interrupt Enable */
+#define USART_CR3_IREN_Pos (1U)
+#define USART_CR3_IREN_Msk (0x1U << USART_CR3_IREN_Pos) /*!< 0x00000002 */
+#define USART_CR3_IREN USART_CR3_IREN_Msk /*!< IrDA mode Enable */
+#define USART_CR3_IRLP_Pos (2U)
+#define USART_CR3_IRLP_Msk (0x1U << USART_CR3_IRLP_Pos) /*!< 0x00000004 */
+#define USART_CR3_IRLP USART_CR3_IRLP_Msk /*!< IrDA Low-Power */
+#define USART_CR3_HDSEL_Pos (3U)
+#define USART_CR3_HDSEL_Msk (0x1U << USART_CR3_HDSEL_Pos) /*!< 0x00000008 */
+#define USART_CR3_HDSEL USART_CR3_HDSEL_Msk /*!< Half-Duplex Selection */
+#define USART_CR3_NACK_Pos (4U)
+#define USART_CR3_NACK_Msk (0x1U << USART_CR3_NACK_Pos) /*!< 0x00000010 */
+#define USART_CR3_NACK USART_CR3_NACK_Msk /*!< Smartcard NACK enable */
+#define USART_CR3_SCEN_Pos (5U)
+#define USART_CR3_SCEN_Msk (0x1U << USART_CR3_SCEN_Pos) /*!< 0x00000020 */
+#define USART_CR3_SCEN USART_CR3_SCEN_Msk /*!< Smartcard mode enable */
+#define USART_CR3_DMAR_Pos (6U)
+#define USART_CR3_DMAR_Msk (0x1U << USART_CR3_DMAR_Pos) /*!< 0x00000040 */
+#define USART_CR3_DMAR USART_CR3_DMAR_Msk /*!< DMA Enable Receiver */
+#define USART_CR3_DMAT_Pos (7U)
+#define USART_CR3_DMAT_Msk (0x1U << USART_CR3_DMAT_Pos) /*!< 0x00000080 */
+#define USART_CR3_DMAT USART_CR3_DMAT_Msk /*!< DMA Enable Transmitter */
+#define USART_CR3_RTSE_Pos (8U)
+#define USART_CR3_RTSE_Msk (0x1U << USART_CR3_RTSE_Pos) /*!< 0x00000100 */
+#define USART_CR3_RTSE USART_CR3_RTSE_Msk /*!< RTS Enable */
+#define USART_CR3_CTSE_Pos (9U)
+#define USART_CR3_CTSE_Msk (0x1U << USART_CR3_CTSE_Pos) /*!< 0x00000200 */
+#define USART_CR3_CTSE USART_CR3_CTSE_Msk /*!< CTS Enable */
+#define USART_CR3_CTSIE_Pos (10U)
+#define USART_CR3_CTSIE_Msk (0x1U << USART_CR3_CTSIE_Pos) /*!< 0x00000400 */
+#define USART_CR3_CTSIE USART_CR3_CTSIE_Msk /*!< CTS Interrupt Enable */
+
+/****************** Bit definition for USART_GTPR register ******************/
+#define USART_GTPR_PSC_Pos (0U)
+#define USART_GTPR_PSC_Msk (0xFFU << USART_GTPR_PSC_Pos) /*!< 0x000000FF */
+#define USART_GTPR_PSC USART_GTPR_PSC_Msk /*!< PSC[7:0] bits (Prescaler value) */
+#define USART_GTPR_PSC_0 (0x01U << USART_GTPR_PSC_Pos) /*!< 0x00000001 */
+#define USART_GTPR_PSC_1 (0x02U << USART_GTPR_PSC_Pos) /*!< 0x00000002 */
+#define USART_GTPR_PSC_2 (0x04U << USART_GTPR_PSC_Pos) /*!< 0x00000004 */
+#define USART_GTPR_PSC_3 (0x08U << USART_GTPR_PSC_Pos) /*!< 0x00000008 */
+#define USART_GTPR_PSC_4 (0x10U << USART_GTPR_PSC_Pos) /*!< 0x00000010 */
+#define USART_GTPR_PSC_5 (0x20U << USART_GTPR_PSC_Pos) /*!< 0x00000020 */
+#define USART_GTPR_PSC_6 (0x40U << USART_GTPR_PSC_Pos) /*!< 0x00000040 */
+#define USART_GTPR_PSC_7 (0x80U << USART_GTPR_PSC_Pos) /*!< 0x00000080 */
+
+#define USART_GTPR_GT_Pos (8U)
+#define USART_GTPR_GT_Msk (0xFFU << USART_GTPR_GT_Pos) /*!< 0x0000FF00 */
+#define USART_GTPR_GT USART_GTPR_GT_Msk /*!< Guard time value */
+
+/******************************************************************************/
+/* */
+/* Debug MCU */
+/* */
+/******************************************************************************/
+
+/**************** Bit definition for DBGMCU_IDCODE register *****************/
+#define DBGMCU_IDCODE_DEV_ID_Pos (0U)
+#define DBGMCU_IDCODE_DEV_ID_Msk (0xFFFU << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */
+#define DBGMCU_IDCODE_DEV_ID DBGMCU_IDCODE_DEV_ID_Msk /*!< Device Identifier */
+
+#define DBGMCU_IDCODE_REV_ID_Pos (16U)
+#define DBGMCU_IDCODE_REV_ID_Msk (0xFFFFU << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */
+#define DBGMCU_IDCODE_REV_ID DBGMCU_IDCODE_REV_ID_Msk /*!< REV_ID[15:0] bits (Revision Identifier) */
+#define DBGMCU_IDCODE_REV_ID_0 (0x0001U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00010000 */
+#define DBGMCU_IDCODE_REV_ID_1 (0x0002U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00020000 */
+#define DBGMCU_IDCODE_REV_ID_2 (0x0004U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00040000 */
+#define DBGMCU_IDCODE_REV_ID_3 (0x0008U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00080000 */
+#define DBGMCU_IDCODE_REV_ID_4 (0x0010U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00100000 */
+#define DBGMCU_IDCODE_REV_ID_5 (0x0020U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00200000 */
+#define DBGMCU_IDCODE_REV_ID_6 (0x0040U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00400000 */
+#define DBGMCU_IDCODE_REV_ID_7 (0x0080U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00800000 */
+#define DBGMCU_IDCODE_REV_ID_8 (0x0100U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x01000000 */
+#define DBGMCU_IDCODE_REV_ID_9 (0x0200U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x02000000 */
+#define DBGMCU_IDCODE_REV_ID_10 (0x0400U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x04000000 */
+#define DBGMCU_IDCODE_REV_ID_11 (0x0800U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x08000000 */
+#define DBGMCU_IDCODE_REV_ID_12 (0x1000U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x10000000 */
+#define DBGMCU_IDCODE_REV_ID_13 (0x2000U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x20000000 */
+#define DBGMCU_IDCODE_REV_ID_14 (0x4000U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x40000000 */
+#define DBGMCU_IDCODE_REV_ID_15 (0x8000U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x80000000 */
+
+/****************** Bit definition for DBGMCU_CR register *******************/
+#define DBGMCU_CR_DBG_SLEEP_Pos (0U)
+#define DBGMCU_CR_DBG_SLEEP_Msk (0x1U << DBGMCU_CR_DBG_SLEEP_Pos) /*!< 0x00000001 */
+#define DBGMCU_CR_DBG_SLEEP DBGMCU_CR_DBG_SLEEP_Msk /*!< Debug Sleep Mode */
+#define DBGMCU_CR_DBG_STOP_Pos (1U)
+#define DBGMCU_CR_DBG_STOP_Msk (0x1U << DBGMCU_CR_DBG_STOP_Pos) /*!< 0x00000002 */
+#define DBGMCU_CR_DBG_STOP DBGMCU_CR_DBG_STOP_Msk /*!< Debug Stop Mode */
+#define DBGMCU_CR_DBG_STANDBY_Pos (2U)
+#define DBGMCU_CR_DBG_STANDBY_Msk (0x1U << DBGMCU_CR_DBG_STANDBY_Pos) /*!< 0x00000004 */
+#define DBGMCU_CR_DBG_STANDBY DBGMCU_CR_DBG_STANDBY_Msk /*!< Debug Standby mode */
+#define DBGMCU_CR_TRACE_IOEN_Pos (5U)
+#define DBGMCU_CR_TRACE_IOEN_Msk (0x1U << DBGMCU_CR_TRACE_IOEN_Pos) /*!< 0x00000020 */
+#define DBGMCU_CR_TRACE_IOEN DBGMCU_CR_TRACE_IOEN_Msk /*!< Trace Pin Assignment Control */
+
+#define DBGMCU_CR_TRACE_MODE_Pos (6U)
+#define DBGMCU_CR_TRACE_MODE_Msk (0x3U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x000000C0 */
+#define DBGMCU_CR_TRACE_MODE DBGMCU_CR_TRACE_MODE_Msk /*!< TRACE_MODE[1:0] bits (Trace Pin Assignment Control) */
+#define DBGMCU_CR_TRACE_MODE_0 (0x1U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000040 */
+#define DBGMCU_CR_TRACE_MODE_1 (0x2U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000080 */
+
+#define DBGMCU_CR_DBG_IWDG_STOP_Pos (8U)
+#define DBGMCU_CR_DBG_IWDG_STOP_Msk (0x1U << DBGMCU_CR_DBG_IWDG_STOP_Pos) /*!< 0x00000100 */
+#define DBGMCU_CR_DBG_IWDG_STOP DBGMCU_CR_DBG_IWDG_STOP_Msk /*!< Debug Independent Watchdog stopped when Core is halted */
+#define DBGMCU_CR_DBG_WWDG_STOP_Pos (9U)
+#define DBGMCU_CR_DBG_WWDG_STOP_Msk (0x1U << DBGMCU_CR_DBG_WWDG_STOP_Pos) /*!< 0x00000200 */
+#define DBGMCU_CR_DBG_WWDG_STOP DBGMCU_CR_DBG_WWDG_STOP_Msk /*!< Debug Window Watchdog stopped when Core is halted */
+#define DBGMCU_CR_DBG_TIM1_STOP_Pos (10U)
+#define DBGMCU_CR_DBG_TIM1_STOP_Msk (0x1U << DBGMCU_CR_DBG_TIM1_STOP_Pos) /*!< 0x00000400 */
+#define DBGMCU_CR_DBG_TIM1_STOP DBGMCU_CR_DBG_TIM1_STOP_Msk /*!< TIM1 counter stopped when core is halted */
+#define DBGMCU_CR_DBG_TIM2_STOP_Pos (11U)
+#define DBGMCU_CR_DBG_TIM2_STOP_Msk (0x1U << DBGMCU_CR_DBG_TIM2_STOP_Pos) /*!< 0x00000800 */
+#define DBGMCU_CR_DBG_TIM2_STOP DBGMCU_CR_DBG_TIM2_STOP_Msk /*!< TIM2 counter stopped when core is halted */
+#define DBGMCU_CR_DBG_TIM3_STOP_Pos (12U)
+#define DBGMCU_CR_DBG_TIM3_STOP_Msk (0x1U << DBGMCU_CR_DBG_TIM3_STOP_Pos) /*!< 0x00001000 */
+#define DBGMCU_CR_DBG_TIM3_STOP DBGMCU_CR_DBG_TIM3_STOP_Msk /*!< TIM3 counter stopped when core is halted */
+#define DBGMCU_CR_DBG_TIM4_STOP_Pos (13U)
+#define DBGMCU_CR_DBG_TIM4_STOP_Msk (0x1U << DBGMCU_CR_DBG_TIM4_STOP_Pos) /*!< 0x00002000 */
+#define DBGMCU_CR_DBG_TIM4_STOP DBGMCU_CR_DBG_TIM4_STOP_Msk /*!< TIM4 counter stopped when core is halted */
+#define DBGMCU_CR_DBG_CAN1_STOP_Pos (14U)
+#define DBGMCU_CR_DBG_CAN1_STOP_Msk (0x1U << DBGMCU_CR_DBG_CAN1_STOP_Pos) /*!< 0x00004000 */
+#define DBGMCU_CR_DBG_CAN1_STOP DBGMCU_CR_DBG_CAN1_STOP_Msk /*!< Debug CAN1 stopped when Core is halted */
+#define DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT_Pos (15U)
+#define DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT_Msk (0x1U << DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT_Pos) /*!< 0x00008000 */
+#define DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT_Msk /*!< SMBUS timeout mode stopped when Core is halted */
+#define DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT_Pos (16U)
+#define DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT_Msk (0x1U << DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT_Pos) /*!< 0x00010000 */
+#define DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT_Msk /*!< SMBUS timeout mode stopped when Core is halted */
+#define DBGMCU_CR_DBG_TIM8_STOP_Pos (17U)
+#define DBGMCU_CR_DBG_TIM8_STOP_Msk (0x1U << DBGMCU_CR_DBG_TIM8_STOP_Pos) /*!< 0x00020000 */
+#define DBGMCU_CR_DBG_TIM8_STOP DBGMCU_CR_DBG_TIM8_STOP_Msk /*!< TIM8 counter stopped when core is halted */
+#define DBGMCU_CR_DBG_TIM5_STOP_Pos (18U)
+#define DBGMCU_CR_DBG_TIM5_STOP_Msk (0x1U << DBGMCU_CR_DBG_TIM5_STOP_Pos) /*!< 0x00040000 */
+#define DBGMCU_CR_DBG_TIM5_STOP DBGMCU_CR_DBG_TIM5_STOP_Msk /*!< TIM5 counter stopped when core is halted */
+#define DBGMCU_CR_DBG_TIM6_STOP_Pos (19U)
+#define DBGMCU_CR_DBG_TIM6_STOP_Msk (0x1U << DBGMCU_CR_DBG_TIM6_STOP_Pos) /*!< 0x00080000 */
+#define DBGMCU_CR_DBG_TIM6_STOP DBGMCU_CR_DBG_TIM6_STOP_Msk /*!< TIM6 counter stopped when core is halted */
+#define DBGMCU_CR_DBG_TIM7_STOP_Pos (20U)
+#define DBGMCU_CR_DBG_TIM7_STOP_Msk (0x1U << DBGMCU_CR_DBG_TIM7_STOP_Pos) /*!< 0x00100000 */
+#define DBGMCU_CR_DBG_TIM7_STOP DBGMCU_CR_DBG_TIM7_STOP_Msk /*!< TIM7 counter stopped when core is halted */
+
+/******************************************************************************/
+/* */
+/* FLASH and Option Bytes Registers */
+/* */
+/******************************************************************************/
+/******************* Bit definition for FLASH_ACR register ******************/
+#define FLASH_ACR_LATENCY_Pos (0U)
+#define FLASH_ACR_LATENCY_Msk (0x7U << FLASH_ACR_LATENCY_Pos) /*!< 0x00000007 */
+#define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk /*!< LATENCY[2:0] bits (Latency) */
+#define FLASH_ACR_LATENCY_0 (0x1U << FLASH_ACR_LATENCY_Pos) /*!< 0x00000001 */
+#define FLASH_ACR_LATENCY_1 (0x2U << FLASH_ACR_LATENCY_Pos) /*!< 0x00000002 */
+#define FLASH_ACR_LATENCY_2 (0x4U << FLASH_ACR_LATENCY_Pos) /*!< 0x00000004 */
+
+#define FLASH_ACR_HLFCYA_Pos (3U)
+#define FLASH_ACR_HLFCYA_Msk (0x1U << FLASH_ACR_HLFCYA_Pos) /*!< 0x00000008 */
+#define FLASH_ACR_HLFCYA FLASH_ACR_HLFCYA_Msk /*!< Flash Half Cycle Access Enable */
+#define FLASH_ACR_PRFTBE_Pos (4U)
+#define FLASH_ACR_PRFTBE_Msk (0x1U << FLASH_ACR_PRFTBE_Pos) /*!< 0x00000010 */
+#define FLASH_ACR_PRFTBE FLASH_ACR_PRFTBE_Msk /*!< Prefetch Buffer Enable */
+#define FLASH_ACR_PRFTBS_Pos (5U)
+#define FLASH_ACR_PRFTBS_Msk (0x1U << FLASH_ACR_PRFTBS_Pos) /*!< 0x00000020 */
+#define FLASH_ACR_PRFTBS FLASH_ACR_PRFTBS_Msk /*!< Prefetch Buffer Status */
+
+/****************** Bit definition for FLASH_KEYR register ******************/
+#define FLASH_KEYR_FKEYR_Pos (0U)
+#define FLASH_KEYR_FKEYR_Msk (0xFFFFFFFFU << FLASH_KEYR_FKEYR_Pos) /*!< 0xFFFFFFFF */
+#define FLASH_KEYR_FKEYR FLASH_KEYR_FKEYR_Msk /*!< FPEC Key */
+
+#define RDP_KEY_Pos (0U)
+#define RDP_KEY_Msk (0xA5U << RDP_KEY_Pos) /*!< 0x000000A5 */
+#define RDP_KEY RDP_KEY_Msk /*!< RDP Key */
+#define FLASH_KEY1_Pos (0U)
+#define FLASH_KEY1_Msk (0x45670123U << FLASH_KEY1_Pos) /*!< 0x45670123 */
+#define FLASH_KEY1 FLASH_KEY1_Msk /*!< FPEC Key1 */
+#define FLASH_KEY2_Pos (0U)
+#define FLASH_KEY2_Msk (0xCDEF89ABU << FLASH_KEY2_Pos) /*!< 0xCDEF89AB */
+#define FLASH_KEY2 FLASH_KEY2_Msk /*!< FPEC Key2 */
+
+/***************** Bit definition for FLASH_OPTKEYR register ****************/
+#define FLASH_OPTKEYR_OPTKEYR_Pos (0U)
+#define FLASH_OPTKEYR_OPTKEYR_Msk (0xFFFFFFFFU << FLASH_OPTKEYR_OPTKEYR_Pos) /*!< 0xFFFFFFFF */
+#define FLASH_OPTKEYR_OPTKEYR FLASH_OPTKEYR_OPTKEYR_Msk /*!< Option Byte Key */
+
+#define FLASH_OPTKEY1 FLASH_KEY1 /*!< Option Byte Key1 */
+#define FLASH_OPTKEY2 FLASH_KEY2 /*!< Option Byte Key2 */
+
+/****************** Bit definition for FLASH_SR register ********************/
+#define FLASH_SR_BSY_Pos (0U)
+#define FLASH_SR_BSY_Msk (0x1U << FLASH_SR_BSY_Pos) /*!< 0x00000001 */
+#define FLASH_SR_BSY FLASH_SR_BSY_Msk /*!< Busy */
+#define FLASH_SR_PGERR_Pos (2U)
+#define FLASH_SR_PGERR_Msk (0x1U << FLASH_SR_PGERR_Pos) /*!< 0x00000004 */
+#define FLASH_SR_PGERR FLASH_SR_PGERR_Msk /*!< Programming Error */
+#define FLASH_SR_WRPRTERR_Pos (4U)
+#define FLASH_SR_WRPRTERR_Msk (0x1U << FLASH_SR_WRPRTERR_Pos) /*!< 0x00000010 */
+#define FLASH_SR_WRPRTERR FLASH_SR_WRPRTERR_Msk /*!< Write Protection Error */
+#define FLASH_SR_EOP_Pos (5U)
+#define FLASH_SR_EOP_Msk (0x1U << FLASH_SR_EOP_Pos) /*!< 0x00000020 */
+#define FLASH_SR_EOP FLASH_SR_EOP_Msk /*!< End of operation */
+
+/******************* Bit definition for FLASH_CR register *******************/
+#define FLASH_CR_PG_Pos (0U)
+#define FLASH_CR_PG_Msk (0x1U << FLASH_CR_PG_Pos) /*!< 0x00000001 */
+#define FLASH_CR_PG FLASH_CR_PG_Msk /*!< Programming */
+#define FLASH_CR_PER_Pos (1U)
+#define FLASH_CR_PER_Msk (0x1U << FLASH_CR_PER_Pos) /*!< 0x00000002 */
+#define FLASH_CR_PER FLASH_CR_PER_Msk /*!< Page Erase */
+#define FLASH_CR_MER_Pos (2U)
+#define FLASH_CR_MER_Msk (0x1U << FLASH_CR_MER_Pos) /*!< 0x00000004 */
+#define FLASH_CR_MER FLASH_CR_MER_Msk /*!< Mass Erase */
+#define FLASH_CR_OPTPG_Pos (4U)
+#define FLASH_CR_OPTPG_Msk (0x1U << FLASH_CR_OPTPG_Pos) /*!< 0x00000010 */
+#define FLASH_CR_OPTPG FLASH_CR_OPTPG_Msk /*!< Option Byte Programming */
+#define FLASH_CR_OPTER_Pos (5U)
+#define FLASH_CR_OPTER_Msk (0x1U << FLASH_CR_OPTER_Pos) /*!< 0x00000020 */
+#define FLASH_CR_OPTER FLASH_CR_OPTER_Msk /*!< Option Byte Erase */
+#define FLASH_CR_STRT_Pos (6U)
+#define FLASH_CR_STRT_Msk (0x1U << FLASH_CR_STRT_Pos) /*!< 0x00000040 */
+#define FLASH_CR_STRT FLASH_CR_STRT_Msk /*!< Start */
+#define FLASH_CR_LOCK_Pos (7U)
+#define FLASH_CR_LOCK_Msk (0x1U << FLASH_CR_LOCK_Pos) /*!< 0x00000080 */
+#define FLASH_CR_LOCK FLASH_CR_LOCK_Msk /*!< Lock */
+#define FLASH_CR_OPTWRE_Pos (9U)
+#define FLASH_CR_OPTWRE_Msk (0x1U << FLASH_CR_OPTWRE_Pos) /*!< 0x00000200 */
+#define FLASH_CR_OPTWRE FLASH_CR_OPTWRE_Msk /*!< Option Bytes Write Enable */
+#define FLASH_CR_ERRIE_Pos (10U)
+#define FLASH_CR_ERRIE_Msk (0x1U << FLASH_CR_ERRIE_Pos) /*!< 0x00000400 */
+#define FLASH_CR_ERRIE FLASH_CR_ERRIE_Msk /*!< Error Interrupt Enable */
+#define FLASH_CR_EOPIE_Pos (12U)
+#define FLASH_CR_EOPIE_Msk (0x1U << FLASH_CR_EOPIE_Pos) /*!< 0x00001000 */
+#define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk /*!< End of operation interrupt enable */
+
+/******************* Bit definition for FLASH_AR register *******************/
+#define FLASH_AR_FAR_Pos (0U)
+#define FLASH_AR_FAR_Msk (0xFFFFFFFFU << FLASH_AR_FAR_Pos) /*!< 0xFFFFFFFF */
+#define FLASH_AR_FAR FLASH_AR_FAR_Msk /*!< Flash Address */
+
+/****************** Bit definition for FLASH_OBR register *******************/
+#define FLASH_OBR_OPTERR_Pos (0U)
+#define FLASH_OBR_OPTERR_Msk (0x1U << FLASH_OBR_OPTERR_Pos) /*!< 0x00000001 */
+#define FLASH_OBR_OPTERR FLASH_OBR_OPTERR_Msk /*!< Option Byte Error */
+#define FLASH_OBR_RDPRT_Pos (1U)
+#define FLASH_OBR_RDPRT_Msk (0x1U << FLASH_OBR_RDPRT_Pos) /*!< 0x00000002 */
+#define FLASH_OBR_RDPRT FLASH_OBR_RDPRT_Msk /*!< Read protection */
+
+#define FLASH_OBR_IWDG_SW_Pos (2U)
+#define FLASH_OBR_IWDG_SW_Msk (0x1U << FLASH_OBR_IWDG_SW_Pos) /*!< 0x00000004 */
+#define FLASH_OBR_IWDG_SW FLASH_OBR_IWDG_SW_Msk /*!< IWDG SW */
+#define FLASH_OBR_nRST_STOP_Pos (3U)
+#define FLASH_OBR_nRST_STOP_Msk (0x1U << FLASH_OBR_nRST_STOP_Pos) /*!< 0x00000008 */
+#define FLASH_OBR_nRST_STOP FLASH_OBR_nRST_STOP_Msk /*!< nRST_STOP */
+#define FLASH_OBR_nRST_STDBY_Pos (4U)
+#define FLASH_OBR_nRST_STDBY_Msk (0x1U << FLASH_OBR_nRST_STDBY_Pos) /*!< 0x00000010 */
+#define FLASH_OBR_nRST_STDBY FLASH_OBR_nRST_STDBY_Msk /*!< nRST_STDBY */
+#define FLASH_OBR_USER_Pos (2U)
+#define FLASH_OBR_USER_Msk (0x7U << FLASH_OBR_USER_Pos) /*!< 0x0000001C */
+#define FLASH_OBR_USER FLASH_OBR_USER_Msk /*!< User Option Bytes */
+#define FLASH_OBR_DATA0_Pos (10U)
+#define FLASH_OBR_DATA0_Msk (0xFFU << FLASH_OBR_DATA0_Pos) /*!< 0x0003FC00 */
+#define FLASH_OBR_DATA0 FLASH_OBR_DATA0_Msk /*!< Data0 */
+#define FLASH_OBR_DATA1_Pos (18U)
+#define FLASH_OBR_DATA1_Msk (0xFFU << FLASH_OBR_DATA1_Pos) /*!< 0x03FC0000 */
+#define FLASH_OBR_DATA1 FLASH_OBR_DATA1_Msk /*!< Data1 */
+
+/****************** Bit definition for FLASH_WRPR register ******************/
+#define FLASH_WRPR_WRP_Pos (0U)
+#define FLASH_WRPR_WRP_Msk (0xFFFFFFFFU << FLASH_WRPR_WRP_Pos) /*!< 0xFFFFFFFF */
+#define FLASH_WRPR_WRP FLASH_WRPR_WRP_Msk /*!< Write Protect */
+
+/*----------------------------------------------------------------------------*/
+
+/****************** Bit definition for FLASH_RDP register *******************/
+#define FLASH_RDP_RDP_Pos (0U)
+#define FLASH_RDP_RDP_Msk (0xFFU << FLASH_RDP_RDP_Pos) /*!< 0x000000FF */
+#define FLASH_RDP_RDP FLASH_RDP_RDP_Msk /*!< Read protection option byte */
+#define FLASH_RDP_nRDP_Pos (8U)
+#define FLASH_RDP_nRDP_Msk (0xFFU << FLASH_RDP_nRDP_Pos) /*!< 0x0000FF00 */
+#define FLASH_RDP_nRDP FLASH_RDP_nRDP_Msk /*!< Read protection complemented option byte */
+
+/****************** Bit definition for FLASH_USER register ******************/
+#define FLASH_USER_USER_Pos (16U)
+#define FLASH_USER_USER_Msk (0xFFU << FLASH_USER_USER_Pos) /*!< 0x00FF0000 */
+#define FLASH_USER_USER FLASH_USER_USER_Msk /*!< User option byte */
+#define FLASH_USER_nUSER_Pos (24U)
+#define FLASH_USER_nUSER_Msk (0xFFU << FLASH_USER_nUSER_Pos) /*!< 0xFF000000 */
+#define FLASH_USER_nUSER FLASH_USER_nUSER_Msk /*!< User complemented option byte */
+
+/****************** Bit definition for FLASH_Data0 register *****************/
+#define FLASH_DATA0_DATA0_Pos (0U)
+#define FLASH_DATA0_DATA0_Msk (0xFFU << FLASH_DATA0_DATA0_Pos) /*!< 0x000000FF */
+#define FLASH_DATA0_DATA0 FLASH_DATA0_DATA0_Msk /*!< User data storage option byte */
+#define FLASH_DATA0_nDATA0_Pos (8U)
+#define FLASH_DATA0_nDATA0_Msk (0xFFU << FLASH_DATA0_nDATA0_Pos) /*!< 0x0000FF00 */
+#define FLASH_DATA0_nDATA0 FLASH_DATA0_nDATA0_Msk /*!< User data storage complemented option byte */
+
+/****************** Bit definition for FLASH_Data1 register *****************/
+#define FLASH_DATA1_DATA1_Pos (16U)
+#define FLASH_DATA1_DATA1_Msk (0xFFU << FLASH_DATA1_DATA1_Pos) /*!< 0x00FF0000 */
+#define FLASH_DATA1_DATA1 FLASH_DATA1_DATA1_Msk /*!< User data storage option byte */
+#define FLASH_DATA1_nDATA1_Pos (24U)
+#define FLASH_DATA1_nDATA1_Msk (0xFFU << FLASH_DATA1_nDATA1_Pos) /*!< 0xFF000000 */
+#define FLASH_DATA1_nDATA1 FLASH_DATA1_nDATA1_Msk /*!< User data storage complemented option byte */
+
+/****************** Bit definition for FLASH_WRP0 register ******************/
+#define FLASH_WRP0_WRP0_Pos (0U)
+#define FLASH_WRP0_WRP0_Msk (0xFFU << FLASH_WRP0_WRP0_Pos) /*!< 0x000000FF */
+#define FLASH_WRP0_WRP0 FLASH_WRP0_WRP0_Msk /*!< Flash memory write protection option bytes */
+#define FLASH_WRP0_nWRP0_Pos (8U)
+#define FLASH_WRP0_nWRP0_Msk (0xFFU << FLASH_WRP0_nWRP0_Pos) /*!< 0x0000FF00 */
+#define FLASH_WRP0_nWRP0 FLASH_WRP0_nWRP0_Msk /*!< Flash memory write protection complemented option bytes */
+
+/****************** Bit definition for FLASH_WRP1 register ******************/
+#define FLASH_WRP1_WRP1_Pos (16U)
+#define FLASH_WRP1_WRP1_Msk (0xFFU << FLASH_WRP1_WRP1_Pos) /*!< 0x00FF0000 */
+#define FLASH_WRP1_WRP1 FLASH_WRP1_WRP1_Msk /*!< Flash memory write protection option bytes */
+#define FLASH_WRP1_nWRP1_Pos (24U)
+#define FLASH_WRP1_nWRP1_Msk (0xFFU << FLASH_WRP1_nWRP1_Pos) /*!< 0xFF000000 */
+#define FLASH_WRP1_nWRP1 FLASH_WRP1_nWRP1_Msk /*!< Flash memory write protection complemented option bytes */
+
+/****************** Bit definition for FLASH_WRP2 register ******************/
+#define FLASH_WRP2_WRP2_Pos (0U)
+#define FLASH_WRP2_WRP2_Msk (0xFFU << FLASH_WRP2_WRP2_Pos) /*!< 0x000000FF */
+#define FLASH_WRP2_WRP2 FLASH_WRP2_WRP2_Msk /*!< Flash memory write protection option bytes */
+#define FLASH_WRP2_nWRP2_Pos (8U)
+#define FLASH_WRP2_nWRP2_Msk (0xFFU << FLASH_WRP2_nWRP2_Pos) /*!< 0x0000FF00 */
+#define FLASH_WRP2_nWRP2 FLASH_WRP2_nWRP2_Msk /*!< Flash memory write protection complemented option bytes */
+
+/****************** Bit definition for FLASH_WRP3 register ******************/
+#define FLASH_WRP3_WRP3_Pos (16U)
+#define FLASH_WRP3_WRP3_Msk (0xFFU << FLASH_WRP3_WRP3_Pos) /*!< 0x00FF0000 */
+#define FLASH_WRP3_WRP3 FLASH_WRP3_WRP3_Msk /*!< Flash memory write protection option bytes */
+#define FLASH_WRP3_nWRP3_Pos (24U)
+#define FLASH_WRP3_nWRP3_Msk (0xFFU << FLASH_WRP3_nWRP3_Pos) /*!< 0xFF000000 */
+#define FLASH_WRP3_nWRP3 FLASH_WRP3_nWRP3_Msk /*!< Flash memory write protection complemented option bytes */
+
+
+
+/**
+ * @}
+*/
+
+/**
+ * @}
+*/
+
+/** @addtogroup Exported_macro
+ * @{
+ */
+
+/****************************** ADC Instances *********************************/
+#define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) || \
+ ((INSTANCE) == ADC2) || \
+ ((INSTANCE) == ADC3))
+
+#define IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
+
+#define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC12_COMMON)
+
+#define IS_ADC_DMA_CAPABILITY_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) || \
+ ((INSTANCE) == ADC3))
+
+/****************************** CAN Instances *********************************/
+#define IS_CAN_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CAN1)
+
+/****************************** CRC Instances *********************************/
+#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
+
+/****************************** DAC Instances *********************************/
+#define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC)
+
+/****************************** DMA Instances *********************************/
+#define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \
+ ((INSTANCE) == DMA1_Channel2) || \
+ ((INSTANCE) == DMA1_Channel3) || \
+ ((INSTANCE) == DMA1_Channel4) || \
+ ((INSTANCE) == DMA1_Channel5) || \
+ ((INSTANCE) == DMA1_Channel6) || \
+ ((INSTANCE) == DMA1_Channel7) || \
+ ((INSTANCE) == DMA2_Channel1) || \
+ ((INSTANCE) == DMA2_Channel2) || \
+ ((INSTANCE) == DMA2_Channel3) || \
+ ((INSTANCE) == DMA2_Channel4) || \
+ ((INSTANCE) == DMA2_Channel5))
+
+/******************************* GPIO Instances *******************************/
+#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
+ ((INSTANCE) == GPIOB) || \
+ ((INSTANCE) == GPIOC) || \
+ ((INSTANCE) == GPIOD) || \
+ ((INSTANCE) == GPIOE) || \
+ ((INSTANCE) == GPIOF) || \
+ ((INSTANCE) == GPIOG))
+
+/**************************** GPIO Alternate Function Instances ***************/
+#define IS_GPIO_AF_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
+
+/**************************** GPIO Lock Instances *****************************/
+#define IS_GPIO_LOCK_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
+
+/******************************** I2C Instances *******************************/
+#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
+ ((INSTANCE) == I2C2))
+
+/******************************** I2S Instances *******************************/
+#define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI2) || \
+ ((INSTANCE) == SPI3))
+
+/****************************** IWDG Instances ********************************/
+#define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
+
+/****************************** SDIO Instances *********************************/
+#define IS_SDIO_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SDIO)
+
+/******************************** SPI Instances *******************************/
+#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
+ ((INSTANCE) == SPI2) || \
+ ((INSTANCE) == SPI3))
+
+/****************************** START TIM Instances ***************************/
+/****************************** TIM Instances *********************************/
+#define IS_TIM_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM6) || \
+ ((INSTANCE) == TIM7))
+
+#define IS_TIM_CC1_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5))
+
+#define IS_TIM_CC2_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5))
+
+#define IS_TIM_CC3_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5))
+
+#define IS_TIM_CC4_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5))
+
+#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5))
+
+#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5))
+
+#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5))
+
+#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5))
+
+#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5))
+
+#define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5))
+
+#define IS_TIM_XOR_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5))
+
+#define IS_TIM_MASTER_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM6) || \
+ ((INSTANCE) == TIM7))
+
+#define IS_TIM_SLAVE_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5))
+
+#define IS_TIM_DMABURST_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5))
+
+#define IS_TIM_BREAK_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM8))
+
+#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
+ ((((INSTANCE) == TIM1) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM8) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM2) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM3) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM4) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM5) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))))
+
+#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
+ ((((INSTANCE) == TIM1) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3))) \
+ || \
+ (((INSTANCE) == TIM8) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3))))
+
+#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5))
+
+#define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM8))
+
+#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5))
+
+#define IS_TIM_DMA_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM6) || \
+ ((INSTANCE) == TIM7))
+
+#define IS_TIM_DMA_CC_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5))
+
+#define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM8))
+
+/****************************** END TIM Instances *****************************/
+
+
+/******************** USART Instances : Synchronous mode **********************/
+#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3))
+
+/******************** UART Instances : Asynchronous mode **********************/
+#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3) || \
+ ((INSTANCE) == UART4) || \
+ ((INSTANCE) == UART5))
+
+/******************** UART Instances : Half-Duplex mode **********************/
+#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3) || \
+ ((INSTANCE) == UART4) || \
+ ((INSTANCE) == UART5))
+
+/******************** UART Instances : LIN mode **********************/
+#define IS_UART_LIN_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3) || \
+ ((INSTANCE) == UART4) || \
+ ((INSTANCE) == UART5))
+
+/****************** UART Instances : Hardware Flow control ********************/
+#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3))
+
+/********************* UART Instances : Smard card mode ***********************/
+#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3))
+
+/*********************** UART Instances : IRDA mode ***************************/
+#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3) || \
+ ((INSTANCE) == UART4) || \
+ ((INSTANCE) == UART5))
+
+/***************** UART Instances : Multi-Processor mode **********************/
+#define IS_UART_MULTIPROCESSOR_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3) || \
+ ((INSTANCE) == UART4) || \
+ ((INSTANCE) == UART5))
+
+/***************** UART Instances : DMA mode available **********************/
+#define IS_UART_DMA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3) || \
+ ((INSTANCE) == UART4))
+
+/****************************** RTC Instances *********************************/
+#define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
+
+/**************************** WWDG Instances *****************************/
+#define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
+
+/****************************** USB Instances ********************************/
+#define IS_USB_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB)
+
+
+
+
+/**
+ * @}
+*/
+/******************************************************************************/
+/* For a painless codes migration between the STM32F1xx device product */
+/* lines, the aliases defined below are put in place to overcome the */
+/* differences in the interrupt handlers and IRQn definitions. */
+/* No need to update developed interrupt code when moving across */
+/* product lines within the same STM32F1 Family */
+/******************************************************************************/
+
+/* Aliases for __IRQn */
+#define ADC1_IRQn ADC1_2_IRQn
+#define DMA2_Channel4_IRQn DMA2_Channel4_5_IRQn
+#define TIM1_BRK_TIM15_IRQn TIM1_BRK_IRQn
+#define TIM1_BRK_TIM9_IRQn TIM1_BRK_IRQn
+#define TIM9_IRQn TIM1_BRK_IRQn
+#define TIM1_TRG_COM_TIM11_IRQn TIM1_TRG_COM_IRQn
+#define TIM1_TRG_COM_TIM17_IRQn TIM1_TRG_COM_IRQn
+#define TIM11_IRQn TIM1_TRG_COM_IRQn
+#define TIM10_IRQn TIM1_UP_IRQn
+#define TIM1_UP_TIM16_IRQn TIM1_UP_IRQn
+#define TIM1_UP_TIM10_IRQn TIM1_UP_IRQn
+#define TIM6_DAC_IRQn TIM6_IRQn
+#define TIM12_IRQn TIM8_BRK_IRQn
+#define TIM8_BRK_TIM12_IRQn TIM8_BRK_IRQn
+#define TIM14_IRQn TIM8_TRG_COM_IRQn
+#define TIM8_TRG_COM_TIM14_IRQn TIM8_TRG_COM_IRQn
+#define TIM8_UP_TIM13_IRQn TIM8_UP_IRQn
+#define TIM13_IRQn TIM8_UP_IRQn
+#define CEC_IRQn USBWakeUp_IRQn
+#define OTG_FS_WKUP_IRQn USBWakeUp_IRQn
+#define CAN1_TX_IRQn USB_HP_CAN1_TX_IRQn
+#define USB_HP_IRQn USB_HP_CAN1_TX_IRQn
+#define USB_LP_IRQn USB_LP_CAN1_RX0_IRQn
+#define CAN1_RX0_IRQn USB_LP_CAN1_RX0_IRQn
+
+
+/* Aliases for __IRQHandler */
+#define ADC1_IRQHandler ADC1_2_IRQHandler
+#define DMA2_Channel4_IRQHandler DMA2_Channel4_5_IRQHandler
+#define TIM1_BRK_TIM15_IRQHandler TIM1_BRK_IRQHandler
+#define TIM1_BRK_TIM9_IRQHandler TIM1_BRK_IRQHandler
+#define TIM9_IRQHandler TIM1_BRK_IRQHandler
+#define TIM1_TRG_COM_TIM11_IRQHandler TIM1_TRG_COM_IRQHandler
+#define TIM1_TRG_COM_TIM17_IRQHandler TIM1_TRG_COM_IRQHandler
+#define TIM11_IRQHandler TIM1_TRG_COM_IRQHandler
+#define TIM10_IRQHandler TIM1_UP_IRQHandler
+#define TIM1_UP_TIM16_IRQHandler TIM1_UP_IRQHandler
+#define TIM1_UP_TIM10_IRQHandler TIM1_UP_IRQHandler
+#define TIM6_DAC_IRQHandler TIM6_IRQHandler
+#define TIM12_IRQHandler TIM8_BRK_IRQHandler
+#define TIM8_BRK_TIM12_IRQHandler TIM8_BRK_IRQHandler
+#define TIM14_IRQHandler TIM8_TRG_COM_IRQHandler
+#define TIM8_TRG_COM_TIM14_IRQHandler TIM8_TRG_COM_IRQHandler
+#define TIM8_UP_TIM13_IRQHandler TIM8_UP_IRQHandler
+#define TIM13_IRQHandler TIM8_UP_IRQHandler
+#define CEC_IRQHandler USBWakeUp_IRQHandler
+#define OTG_FS_WKUP_IRQHandler USBWakeUp_IRQHandler
+#define CAN1_TX_IRQHandler USB_HP_CAN1_TX_IRQHandler
+#define USB_HP_IRQHandler USB_HP_CAN1_TX_IRQHandler
+#define USB_LP_IRQHandler USB_LP_CAN1_RX0_IRQHandler
+#define CAN1_RX0_IRQHandler USB_LP_CAN1_RX0_IRQHandler
+
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+
+#ifdef __cplusplus
+ }
+#endif /* __cplusplus */
+
+#endif /* __STM32F103xE_H */
+
+
+
+ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Device/ST/STM32F1xx/Include/stm32f103xg.h b/Device/ST/STM32F1xx/Include/stm32f103xg.h
new file mode 100644
index 0000000..1d30f78
--- /dev/null
+++ b/Device/ST/STM32F1xx/Include/stm32f103xg.h
@@ -0,0 +1,12383 @@
+/**
+ ******************************************************************************
+ * @file stm32f103xg.h
+ * @author MCD Application Team
+ * @version V4.1.0
+ * @date 29-April-2016
+ * @brief CMSIS Cortex-M3 Device Peripheral Access Layer Header File.
+ * This file contains all the peripheral register's definitions, bits
+ * definitions and memory mapping for STM32F1xx devices.
+ *
+ * This file contains:
+ * - Data structures and the address mapping for all peripherals
+ * - Peripheral's registers declarations and bits definition
+ * - Macros to access peripheral’s registers hardware
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+
+/** @addtogroup CMSIS
+ * @{
+ */
+
+/** @addtogroup stm32f103xg
+ * @{
+ */
+
+#ifndef __STM32F103xG_H
+#define __STM32F103xG_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/** @addtogroup Configuration_section_for_CMSIS
+ * @{
+ */
+/**
+ * @brief Configuration of the Cortex-M3 Processor and Core Peripherals
+ */
+ #define __MPU_PRESENT 1 /*!< STM32 XL-density devices provide an MPU */
+#define __CM3_REV 0x0200 /*!< Core Revision r2p0 */
+#define __NVIC_PRIO_BITS 4 /*!< STM32 uses 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
+
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_interrupt_number_definition
+ * @{
+ */
+
+/**
+ * @brief STM32F10x Interrupt Number Definition, according to the selected device
+ * in @ref Library_configuration_section
+ */
+
+ /*!< Interrupt Number Definition */
+typedef enum
+{
+/****** Cortex-M3 Processor Exceptions Numbers ***************************************************/
+ NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
+ HardFault_IRQn = -13, /*!< 3 Cortex-M3 Hard Fault Interrupt */
+ MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */
+ BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */
+ UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */
+ SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */
+ DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */
+ PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */
+ SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */
+
+/****** STM32 specific Interrupt Numbers *********************************************************/
+ WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
+ PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */
+ TAMPER_IRQn = 2, /*!< Tamper Interrupt */
+ RTC_IRQn = 3, /*!< RTC global Interrupt */
+ FLASH_IRQn = 4, /*!< FLASH global Interrupt */
+ RCC_IRQn = 5, /*!< RCC global Interrupt */
+ EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */
+ EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */
+ EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */
+ EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */
+ EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */
+ DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 global Interrupt */
+ DMA1_Channel2_IRQn = 12, /*!< DMA1 Channel 2 global Interrupt */
+ DMA1_Channel3_IRQn = 13, /*!< DMA1 Channel 3 global Interrupt */
+ DMA1_Channel4_IRQn = 14, /*!< DMA1 Channel 4 global Interrupt */
+ DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 global Interrupt */
+ DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 global Interrupt */
+ DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 global Interrupt */
+ ADC1_2_IRQn = 18, /*!< ADC1 and ADC2 global Interrupt */
+ USB_HP_CAN1_TX_IRQn = 19, /*!< USB Device High Priority or CAN1 TX Interrupts */
+ USB_LP_CAN1_RX0_IRQn = 20, /*!< USB Device Low Priority or CAN1 RX0 Interrupts */
+ CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */
+ CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */
+ EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
+ TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break Interrupt and TIM9 global Interrupt */
+ TIM1_UP_TIM10_IRQn = 25, /*!< TIM1 Update Interrupt and TIM10 global Interrupt */
+ TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */
+ TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
+ TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
+ TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
+ TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
+ I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
+ I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
+ I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
+ I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
+ SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
+ SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
+ USART1_IRQn = 37, /*!< USART1 global Interrupt */
+ USART2_IRQn = 38, /*!< USART2 global Interrupt */
+ USART3_IRQn = 39, /*!< USART3 global Interrupt */
+ EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
+ RTC_Alarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */
+ USBWakeUp_IRQn = 42, /*!< USB Device WakeUp from suspend through EXTI Line Interrupt */
+ TIM8_BRK_TIM12_IRQn = 43, /*!< TIM8 Break Interrupt and TIM12 global Interrupt */
+ TIM8_UP_TIM13_IRQn = 44, /*!< TIM8 Update Interrupt and TIM13 global Interrupt */
+ TIM8_TRG_COM_TIM14_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */
+ TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */
+ ADC3_IRQn = 47, /*!< ADC3 global Interrupt */
+ FSMC_IRQn = 48, /*!< FSMC global Interrupt */
+ SDIO_IRQn = 49, /*!< SDIO global Interrupt */
+ TIM5_IRQn = 50, /*!< TIM5 global Interrupt */
+ SPI3_IRQn = 51, /*!< SPI3 global Interrupt */
+ UART4_IRQn = 52, /*!< UART4 global Interrupt */
+ UART5_IRQn = 53, /*!< UART5 global Interrupt */
+ TIM6_IRQn = 54, /*!< TIM6 global Interrupt */
+ TIM7_IRQn = 55, /*!< TIM7 global Interrupt */
+ DMA2_Channel1_IRQn = 56, /*!< DMA2 Channel 1 global Interrupt */
+ DMA2_Channel2_IRQn = 57, /*!< DMA2 Channel 2 global Interrupt */
+ DMA2_Channel3_IRQn = 58, /*!< DMA2 Channel 3 global Interrupt */
+ DMA2_Channel4_5_IRQn = 59, /*!< DMA2 Channel 4 and Channel 5 global Interrupt */
+} IRQn_Type;
+
+
+/**
+ * @}
+ */
+
+#include "core_cm3.h"
+#include "system_stm32f1xx.h"
+#include <stdint.h>
+
+/** @addtogroup Peripheral_registers_structures
+ * @{
+ */
+
+/**
+ * @brief Analog to Digital Converter
+ */
+
+typedef struct
+{
+ __IO uint32_t SR;
+ __IO uint32_t CR1;
+ __IO uint32_t CR2;
+ __IO uint32_t SMPR1;
+ __IO uint32_t SMPR2;
+ __IO uint32_t JOFR1;
+ __IO uint32_t JOFR2;
+ __IO uint32_t JOFR3;
+ __IO uint32_t JOFR4;
+ __IO uint32_t HTR;
+ __IO uint32_t LTR;
+ __IO uint32_t SQR1;
+ __IO uint32_t SQR2;
+ __IO uint32_t SQR3;
+ __IO uint32_t JSQR;
+ __IO uint32_t JDR1;
+ __IO uint32_t JDR2;
+ __IO uint32_t JDR3;
+ __IO uint32_t JDR4;
+ __IO uint32_t DR;
+} ADC_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t SR; /*!< ADC status register, used for ADC multimode (bits common to several ADC instances). Address offset: ADC1 base address */
+ __IO uint32_t CR1; /*!< ADC control register 1, used for ADC multimode (bits common to several ADC instances). Address offset: ADC1 base address + 0x04 */
+ __IO uint32_t CR2; /*!< ADC control register 2, used for ADC multimode (bits common to several ADC instances). Address offset: ADC1 base address + 0x08 */
+ uint32_t RESERVED[16];
+ __IO uint32_t DR; /*!< ADC data register, used for ADC multimode (bits common to several ADC instances). Address offset: ADC1 base address + 0x4C */
+} ADC_Common_TypeDef;
+
+/**
+ * @brief Backup Registers
+ */
+
+typedef struct
+{
+ uint32_t RESERVED0;
+ __IO uint32_t DR1;
+ __IO uint32_t DR2;
+ __IO uint32_t DR3;
+ __IO uint32_t DR4;
+ __IO uint32_t DR5;
+ __IO uint32_t DR6;
+ __IO uint32_t DR7;
+ __IO uint32_t DR8;
+ __IO uint32_t DR9;
+ __IO uint32_t DR10;
+ __IO uint32_t RTCCR;
+ __IO uint32_t CR;
+ __IO uint32_t CSR;
+ uint32_t RESERVED13[2];
+ __IO uint32_t DR11;
+ __IO uint32_t DR12;
+ __IO uint32_t DR13;
+ __IO uint32_t DR14;
+ __IO uint32_t DR15;
+ __IO uint32_t DR16;
+ __IO uint32_t DR17;
+ __IO uint32_t DR18;
+ __IO uint32_t DR19;
+ __IO uint32_t DR20;
+ __IO uint32_t DR21;
+ __IO uint32_t DR22;
+ __IO uint32_t DR23;
+ __IO uint32_t DR24;
+ __IO uint32_t DR25;
+ __IO uint32_t DR26;
+ __IO uint32_t DR27;
+ __IO uint32_t DR28;
+ __IO uint32_t DR29;
+ __IO uint32_t DR30;
+ __IO uint32_t DR31;
+ __IO uint32_t DR32;
+ __IO uint32_t DR33;
+ __IO uint32_t DR34;
+ __IO uint32_t DR35;
+ __IO uint32_t DR36;
+ __IO uint32_t DR37;
+ __IO uint32_t DR38;
+ __IO uint32_t DR39;
+ __IO uint32_t DR40;
+ __IO uint32_t DR41;
+ __IO uint32_t DR42;
+} BKP_TypeDef;
+
+/**
+ * @brief Controller Area Network TxMailBox
+ */
+
+typedef struct
+{
+ __IO uint32_t TIR;
+ __IO uint32_t TDTR;
+ __IO uint32_t TDLR;
+ __IO uint32_t TDHR;
+} CAN_TxMailBox_TypeDef;
+
+/**
+ * @brief Controller Area Network FIFOMailBox
+ */
+
+typedef struct
+{
+ __IO uint32_t RIR;
+ __IO uint32_t RDTR;
+ __IO uint32_t RDLR;
+ __IO uint32_t RDHR;
+} CAN_FIFOMailBox_TypeDef;
+
+/**
+ * @brief Controller Area Network FilterRegister
+ */
+
+typedef struct
+{
+ __IO uint32_t FR1;
+ __IO uint32_t FR2;
+} CAN_FilterRegister_TypeDef;
+
+/**
+ * @brief Controller Area Network
+ */
+
+typedef struct
+{
+ __IO uint32_t MCR;
+ __IO uint32_t MSR;
+ __IO uint32_t TSR;
+ __IO uint32_t RF0R;
+ __IO uint32_t RF1R;
+ __IO uint32_t IER;
+ __IO uint32_t ESR;
+ __IO uint32_t BTR;
+ uint32_t RESERVED0[88];
+ CAN_TxMailBox_TypeDef sTxMailBox[3];
+ CAN_FIFOMailBox_TypeDef sFIFOMailBox[2];
+ uint32_t RESERVED1[12];
+ __IO uint32_t FMR;
+ __IO uint32_t FM1R;
+ uint32_t RESERVED2;
+ __IO uint32_t FS1R;
+ uint32_t RESERVED3;
+ __IO uint32_t FFA1R;
+ uint32_t RESERVED4;
+ __IO uint32_t FA1R;
+ uint32_t RESERVED5[8];
+ CAN_FilterRegister_TypeDef sFilterRegister[14];
+} CAN_TypeDef;
+
+/**
+ * @brief CRC calculation unit
+ */
+
+typedef struct
+{
+ __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
+ __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
+ uint8_t RESERVED0; /*!< Reserved, Address offset: 0x05 */
+ uint16_t RESERVED1; /*!< Reserved, Address offset: 0x06 */
+ __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
+} CRC_TypeDef;
+
+/**
+ * @brief Digital to Analog Converter
+ */
+
+typedef struct
+{
+ __IO uint32_t CR;
+ __IO uint32_t SWTRIGR;
+ __IO uint32_t DHR12R1;
+ __IO uint32_t DHR12L1;
+ __IO uint32_t DHR8R1;
+ __IO uint32_t DHR12R2;
+ __IO uint32_t DHR12L2;
+ __IO uint32_t DHR8R2;
+ __IO uint32_t DHR12RD;
+ __IO uint32_t DHR12LD;
+ __IO uint32_t DHR8RD;
+ __IO uint32_t DOR1;
+ __IO uint32_t DOR2;
+} DAC_TypeDef;
+
+/**
+ * @brief Debug MCU
+ */
+
+typedef struct
+{
+ __IO uint32_t IDCODE;
+ __IO uint32_t CR;
+}DBGMCU_TypeDef;
+
+/**
+ * @brief DMA Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t CCR;
+ __IO uint32_t CNDTR;
+ __IO uint32_t CPAR;
+ __IO uint32_t CMAR;
+} DMA_Channel_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t ISR;
+ __IO uint32_t IFCR;
+} DMA_TypeDef;
+
+
+
+/**
+ * @brief External Interrupt/Event Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t IMR;
+ __IO uint32_t EMR;
+ __IO uint32_t RTSR;
+ __IO uint32_t FTSR;
+ __IO uint32_t SWIER;
+ __IO uint32_t PR;
+} EXTI_TypeDef;
+
+/**
+ * @brief FLASH Registers
+ */
+
+typedef struct
+{
+ __IO uint32_t ACR;
+ __IO uint32_t KEYR;
+ __IO uint32_t OPTKEYR;
+ __IO uint32_t SR;
+ __IO uint32_t CR;
+ __IO uint32_t AR;
+ __IO uint32_t RESERVED;
+ __IO uint32_t OBR;
+ __IO uint32_t WRPR;
+ uint32_t RESERVED1[8];
+ __IO uint32_t KEYR2;
+ uint32_t RESERVED2;
+ __IO uint32_t SR2;
+ __IO uint32_t CR2;
+ __IO uint32_t AR2;
+} FLASH_TypeDef;
+
+/**
+ * @brief Option Bytes Registers
+ */
+
+typedef struct
+{
+ __IO uint16_t RDP;
+ __IO uint16_t USER;
+ __IO uint16_t Data0;
+ __IO uint16_t Data1;
+ __IO uint16_t WRP0;
+ __IO uint16_t WRP1;
+ __IO uint16_t WRP2;
+ __IO uint16_t WRP3;
+} OB_TypeDef;
+
+/**
+ * @brief Flexible Static Memory Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t BTCR[8];
+} FSMC_Bank1_TypeDef;
+
+/**
+ * @brief Flexible Static Memory Controller Bank1E
+ */
+
+typedef struct
+{
+ __IO uint32_t BWTR[7];
+} FSMC_Bank1E_TypeDef;
+
+/**
+ * @brief Flexible Static Memory Controller Bank2
+ */
+
+typedef struct
+{
+ __IO uint32_t PCR2; /*!< NAND Flash control register 2, Address offset: 0x60 */
+ __IO uint32_t SR2; /*!< NAND Flash FIFO status and interrupt register 2, Address offset: 0x64 */
+ __IO uint32_t PMEM2; /*!< NAND Flash Common memory space timing register 2, Address offset: 0x68 */
+ __IO uint32_t PATT2; /*!< NAND Flash Attribute memory space timing register 2, Address offset: 0x6C */
+ uint32_t RESERVED0; /*!< Reserved, 0x70 */
+ __IO uint32_t ECCR2; /*!< NAND Flash ECC result registers 2, Address offset: 0x74 */
+ uint32_t RESERVED1; /*!< Reserved, 0x78 */
+ uint32_t RESERVED2; /*!< Reserved, 0x7C */
+ __IO uint32_t PCR3; /*!< NAND Flash control register 3, Address offset: 0x80 */
+ __IO uint32_t SR3; /*!< NAND Flash FIFO status and interrupt register 3, Address offset: 0x84 */
+ __IO uint32_t PMEM3; /*!< NAND Flash Common memory space timing register 3, Address offset: 0x88 */
+ __IO uint32_t PATT3; /*!< NAND Flash Attribute memory space timing register 3, Address offset: 0x8C */
+ uint32_t RESERVED3; /*!< Reserved, 0x90 */
+ __IO uint32_t ECCR3; /*!< NAND Flash ECC result registers 3, Address offset: 0x94 */
+} FSMC_Bank2_3_TypeDef;
+
+/**
+ * @brief Flexible Static Memory Controller Bank4
+ */
+
+typedef struct
+{
+ __IO uint32_t PCR4;
+ __IO uint32_t SR4;
+ __IO uint32_t PMEM4;
+ __IO uint32_t PATT4;
+ __IO uint32_t PIO4;
+} FSMC_Bank4_TypeDef;
+
+/**
+ * @brief General Purpose I/O
+ */
+
+typedef struct
+{
+ __IO uint32_t CRL;
+ __IO uint32_t CRH;
+ __IO uint32_t IDR;
+ __IO uint32_t ODR;
+ __IO uint32_t BSRR;
+ __IO uint32_t BRR;
+ __IO uint32_t LCKR;
+} GPIO_TypeDef;
+
+/**
+ * @brief Alternate Function I/O
+ */
+
+typedef struct
+{
+ __IO uint32_t EVCR;
+ __IO uint32_t MAPR;
+ __IO uint32_t EXTICR[4];
+ uint32_t RESERVED0;
+ __IO uint32_t MAPR2;
+} AFIO_TypeDef;
+/**
+ * @brief Inter Integrated Circuit Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t CR1;
+ __IO uint32_t CR2;
+ __IO uint32_t OAR1;
+ __IO uint32_t OAR2;
+ __IO uint32_t DR;
+ __IO uint32_t SR1;
+ __IO uint32_t SR2;
+ __IO uint32_t CCR;
+ __IO uint32_t TRISE;
+} I2C_TypeDef;
+
+/**
+ * @brief Independent WATCHDOG
+ */
+
+typedef struct
+{
+ __IO uint32_t KR; /*!< Key register, Address offset: 0x00 */
+ __IO uint32_t PR; /*!< Prescaler register, Address offset: 0x04 */
+ __IO uint32_t RLR; /*!< Reload register, Address offset: 0x08 */
+ __IO uint32_t SR; /*!< Status register, Address offset: 0x0C */
+} IWDG_TypeDef;
+
+/**
+ * @brief Power Control
+ */
+
+typedef struct
+{
+ __IO uint32_t CR;
+ __IO uint32_t CSR;
+} PWR_TypeDef;
+
+/**
+ * @brief Reset and Clock Control
+ */
+
+typedef struct
+{
+ __IO uint32_t CR;
+ __IO uint32_t CFGR;
+ __IO uint32_t CIR;
+ __IO uint32_t APB2RSTR;
+ __IO uint32_t APB1RSTR;
+ __IO uint32_t AHBENR;
+ __IO uint32_t APB2ENR;
+ __IO uint32_t APB1ENR;
+ __IO uint32_t BDCR;
+ __IO uint32_t CSR;
+
+
+} RCC_TypeDef;
+
+/**
+ * @brief Real-Time Clock
+ */
+
+typedef struct
+{
+ __IO uint32_t CRH;
+ __IO uint32_t CRL;
+ __IO uint32_t PRLH;
+ __IO uint32_t PRLL;
+ __IO uint32_t DIVH;
+ __IO uint32_t DIVL;
+ __IO uint32_t CNTH;
+ __IO uint32_t CNTL;
+ __IO uint32_t ALRH;
+ __IO uint32_t ALRL;
+} RTC_TypeDef;
+
+/**
+ * @brief SD host Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t POWER;
+ __IO uint32_t CLKCR;
+ __IO uint32_t ARG;
+ __IO uint32_t CMD;
+ __I uint32_t RESPCMD;
+ __I uint32_t RESP1;
+ __I uint32_t RESP2;
+ __I uint32_t RESP3;
+ __I uint32_t RESP4;
+ __IO uint32_t DTIMER;
+ __IO uint32_t DLEN;
+ __IO uint32_t DCTRL;
+ __I uint32_t DCOUNT;
+ __I uint32_t STA;
+ __IO uint32_t ICR;
+ __IO uint32_t MASK;
+ uint32_t RESERVED0[2];
+ __I uint32_t FIFOCNT;
+ uint32_t RESERVED1[13];
+ __IO uint32_t FIFO;
+} SDIO_TypeDef;
+
+/**
+ * @brief Serial Peripheral Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t CR1;
+ __IO uint32_t CR2;
+ __IO uint32_t SR;
+ __IO uint32_t DR;
+ __IO uint32_t CRCPR;
+ __IO uint32_t RXCRCR;
+ __IO uint32_t TXCRCR;
+ __IO uint32_t I2SCFGR;
+ __IO uint32_t I2SPR;
+} SPI_TypeDef;
+
+/**
+ * @brief TIM Timers
+ */
+typedef struct
+{
+ __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
+ __IO uint32_t SMCR; /*!< TIM slave Mode Control register, Address offset: 0x08 */
+ __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
+ __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
+ __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
+ __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
+ __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
+ __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
+ __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
+ __IO uint32_t PSC; /*!< TIM prescaler register, Address offset: 0x28 */
+ __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
+ __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */
+ __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
+ __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
+ __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
+ __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
+ __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
+ __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
+ __IO uint32_t DMAR; /*!< TIM DMA address for full transfer register, Address offset: 0x4C */
+ __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */
+}TIM_TypeDef;
+
+
+/**
+ * @brief Universal Synchronous Asynchronous Receiver Transmitter
+ */
+
+typedef struct
+{
+ __IO uint32_t SR; /*!< USART Status register, Address offset: 0x00 */
+ __IO uint32_t DR; /*!< USART Data register, Address offset: 0x04 */
+ __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x08 */
+ __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x0C */
+ __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x10 */
+ __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x14 */
+ __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x18 */
+} USART_TypeDef;
+
+/**
+ * @brief Universal Serial Bus Full Speed Device
+ */
+
+typedef struct
+{
+ __IO uint16_t EP0R; /*!< USB Endpoint 0 register, Address offset: 0x00 */
+ __IO uint16_t RESERVED0; /*!< Reserved */
+ __IO uint16_t EP1R; /*!< USB Endpoint 1 register, Address offset: 0x04 */
+ __IO uint16_t RESERVED1; /*!< Reserved */
+ __IO uint16_t EP2R; /*!< USB Endpoint 2 register, Address offset: 0x08 */
+ __IO uint16_t RESERVED2; /*!< Reserved */
+ __IO uint16_t EP3R; /*!< USB Endpoint 3 register, Address offset: 0x0C */
+ __IO uint16_t RESERVED3; /*!< Reserved */
+ __IO uint16_t EP4R; /*!< USB Endpoint 4 register, Address offset: 0x10 */
+ __IO uint16_t RESERVED4; /*!< Reserved */
+ __IO uint16_t EP5R; /*!< USB Endpoint 5 register, Address offset: 0x14 */
+ __IO uint16_t RESERVED5; /*!< Reserved */
+ __IO uint16_t EP6R; /*!< USB Endpoint 6 register, Address offset: 0x18 */
+ __IO uint16_t RESERVED6; /*!< Reserved */
+ __IO uint16_t EP7R; /*!< USB Endpoint 7 register, Address offset: 0x1C */
+ __IO uint16_t RESERVED7[17]; /*!< Reserved */
+ __IO uint16_t CNTR; /*!< Control register, Address offset: 0x40 */
+ __IO uint16_t RESERVED8; /*!< Reserved */
+ __IO uint16_t ISTR; /*!< Interrupt status register, Address offset: 0x44 */
+ __IO uint16_t RESERVED9; /*!< Reserved */
+ __IO uint16_t FNR; /*!< Frame number register, Address offset: 0x48 */
+ __IO uint16_t RESERVEDA; /*!< Reserved */
+ __IO uint16_t DADDR; /*!< Device address register, Address offset: 0x4C */
+ __IO uint16_t RESERVEDB; /*!< Reserved */
+ __IO uint16_t BTABLE; /*!< Buffer Table address register, Address offset: 0x50 */
+ __IO uint16_t RESERVEDC; /*!< Reserved */
+} USB_TypeDef;
+
+
+/**
+ * @brief Window WATCHDOG
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
+ __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
+ __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
+} WWDG_TypeDef;
+
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_memory_map
+ * @{
+ */
+
+
+#define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH base address in the alias region */
+#define FLASH_BANK1_END ((uint32_t)0x0807FFFF) /*!< FLASH END address of bank1 */
+#define FLASH_BANK2_END ((uint32_t)0x080FFFFF) /*!< FLASH END address of bank2 */
+#define SRAM_BASE ((uint32_t)0x20000000) /*!< SRAM base address in the alias region */
+#define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */
+
+#define SRAM_BB_BASE ((uint32_t)0x22000000) /*!< SRAM base address in the bit-band region */
+#define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */
+
+#define FSMC_BASE ((uint32_t)0x60000000) /*!< FSMC base address */
+#define FSMC_R_BASE ((uint32_t)0xA0000000) /*!< FSMC registers base address */
+
+/*!< Peripheral memory map */
+#define APB1PERIPH_BASE PERIPH_BASE
+#define APB2PERIPH_BASE (PERIPH_BASE + 0x10000)
+#define AHBPERIPH_BASE (PERIPH_BASE + 0x20000)
+
+#define TIM2_BASE (APB1PERIPH_BASE + 0x0000)
+#define TIM3_BASE (APB1PERIPH_BASE + 0x0400)
+#define TIM4_BASE (APB1PERIPH_BASE + 0x0800)
+#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00)
+#define TIM6_BASE (APB1PERIPH_BASE + 0x1000)
+#define TIM7_BASE (APB1PERIPH_BASE + 0x1400)
+#define TIM12_BASE (APB1PERIPH_BASE + 0x1800)
+#define TIM13_BASE (APB1PERIPH_BASE + 0x1C00)
+#define TIM14_BASE (APB1PERIPH_BASE + 0x2000)
+#define RTC_BASE (APB1PERIPH_BASE + 0x2800)
+#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00)
+#define IWDG_BASE (APB1PERIPH_BASE + 0x3000)
+#define SPI2_BASE (APB1PERIPH_BASE + 0x3800)
+#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00)
+#define USART2_BASE (APB1PERIPH_BASE + 0x4400)
+#define USART3_BASE (APB1PERIPH_BASE + 0x4800)
+#define UART4_BASE (APB1PERIPH_BASE + 0x4C00)
+#define UART5_BASE (APB1PERIPH_BASE + 0x5000)
+#define I2C1_BASE (APB1PERIPH_BASE + 0x5400)
+#define I2C2_BASE (APB1PERIPH_BASE + 0x5800)
+#define CAN1_BASE (APB1PERIPH_BASE + 0x6400)
+#define BKP_BASE (APB1PERIPH_BASE + 0x6C00)
+#define PWR_BASE (APB1PERIPH_BASE + 0x7000)
+#define DAC_BASE (APB1PERIPH_BASE + 0x7400)
+#define AFIO_BASE (APB2PERIPH_BASE + 0x0000)
+#define EXTI_BASE (APB2PERIPH_BASE + 0x0400)
+#define GPIOA_BASE (APB2PERIPH_BASE + 0x0800)
+#define GPIOB_BASE (APB2PERIPH_BASE + 0x0C00)
+#define GPIOC_BASE (APB2PERIPH_BASE + 0x1000)
+#define GPIOD_BASE (APB2PERIPH_BASE + 0x1400)
+#define GPIOE_BASE (APB2PERIPH_BASE + 0x1800)
+#define GPIOF_BASE (APB2PERIPH_BASE + 0x1C00)
+#define GPIOG_BASE (APB2PERIPH_BASE + 0x2000)
+#define ADC1_BASE (APB2PERIPH_BASE + 0x2400)
+#define ADC2_BASE (APB2PERIPH_BASE + 0x2800)
+#define TIM1_BASE (APB2PERIPH_BASE + 0x2C00)
+#define SPI1_BASE (APB2PERIPH_BASE + 0x3000)
+#define TIM8_BASE (APB2PERIPH_BASE + 0x3400)
+#define USART1_BASE (APB2PERIPH_BASE + 0x3800)
+#define ADC3_BASE (APB2PERIPH_BASE + 0x3C00)
+#define TIM9_BASE (APB2PERIPH_BASE + 0x4C00)
+#define TIM10_BASE (APB2PERIPH_BASE + 0x5000)
+#define TIM11_BASE (APB2PERIPH_BASE + 0x5400)
+
+#define SDIO_BASE (PERIPH_BASE + 0x18000)
+
+#define DMA1_BASE (AHBPERIPH_BASE + 0x0000)
+#define DMA1_Channel1_BASE (AHBPERIPH_BASE + 0x0008)
+#define DMA1_Channel2_BASE (AHBPERIPH_BASE + 0x001C)
+#define DMA1_Channel3_BASE (AHBPERIPH_BASE + 0x0030)
+#define DMA1_Channel4_BASE (AHBPERIPH_BASE + 0x0044)
+#define DMA1_Channel5_BASE (AHBPERIPH_BASE + 0x0058)
+#define DMA1_Channel6_BASE (AHBPERIPH_BASE + 0x006C)
+#define DMA1_Channel7_BASE (AHBPERIPH_BASE + 0x0080)
+#define DMA2_BASE (AHBPERIPH_BASE + 0x0400)
+#define DMA2_Channel1_BASE (AHBPERIPH_BASE + 0x0408)
+#define DMA2_Channel2_BASE (AHBPERIPH_BASE + 0x041C)
+#define DMA2_Channel3_BASE (AHBPERIPH_BASE + 0x0430)
+#define DMA2_Channel4_BASE (AHBPERIPH_BASE + 0x0444)
+#define DMA2_Channel5_BASE (AHBPERIPH_BASE + 0x0458)
+#define RCC_BASE (AHBPERIPH_BASE + 0x1000)
+#define CRC_BASE (AHBPERIPH_BASE + 0x3000)
+
+#define FLASH_R_BASE (AHBPERIPH_BASE + 0x2000) /*!< Flash registers base address */
+#define FLASHSIZE_BASE ((uint32_t)0x1FFFF7E0) /*!< FLASH Size register base address */
+#define UID_BASE ((uint32_t)0x1FFFF7E8) /*!< Unique device ID register base address */
+#define OB_BASE ((uint32_t)0x1FFFF800) /*!< Flash Option Bytes base address */
+
+
+#define FSMC_BANK1 (FSMC_BASE) /*!< FSMC Bank1 base address */
+#define FSMC_BANK1_1 (FSMC_BANK1) /*!< FSMC Bank1_1 base address */
+#define FSMC_BANK1_2 (FSMC_BANK1 + 0x04000000) /*!< FSMC Bank1_2 base address */
+#define FSMC_BANK1_3 (FSMC_BANK1 + 0x08000000) /*!< FSMC Bank1_3 base address */
+#define FSMC_BANK1_4 (FSMC_BANK1 + 0x0C000000) /*!< FSMC Bank1_4 base address */
+
+#define FSMC_BANK2 (FSMC_BASE + 0x10000000) /*!< FSMC Bank2 base address */
+#define FSMC_BANK3 (FSMC_BASE + 0x20000000) /*!< FSMC Bank3 base address */
+#define FSMC_BANK4 (FSMC_BASE + 0x30000000) /*!< FSMC Bank4 base address */
+
+#define FSMC_BANK1_R_BASE (FSMC_R_BASE + 0x0000) /*!< FSMC Bank1 registers base address */
+#define FSMC_BANK1E_R_BASE (FSMC_R_BASE + 0x0104) /*!< FSMC Bank1E registers base address */
+#define FSMC_BANK2_3_R_BASE (FSMC_R_BASE + 0x0060) /*!< FSMC Bank2/Bank3 registers base address */
+#define FSMC_BANK4_R_BASE (FSMC_R_BASE + 0x00A0) /*!< FSMC Bank4 registers base address */
+
+#define DBGMCU_BASE ((uint32_t)0xE0042000) /*!< Debug MCU registers base address */
+
+/* USB device FS */
+#define USB_BASE (APB1PERIPH_BASE + 0x00005C00) /*!< USB_IP Peripheral Registers base address */
+#define USB_PMAADDR (APB1PERIPH_BASE + 0x00006000) /*!< USB_IP Packet Memory Area base address */
+
+
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_declaration
+ * @{
+ */
+
+#define TIM2 ((TIM_TypeDef *) TIM2_BASE)
+#define TIM3 ((TIM_TypeDef *) TIM3_BASE)
+#define TIM4 ((TIM_TypeDef *) TIM4_BASE)
+#define TIM5 ((TIM_TypeDef *) TIM5_BASE)
+#define TIM6 ((TIM_TypeDef *) TIM6_BASE)
+#define TIM7 ((TIM_TypeDef *) TIM7_BASE)
+#define TIM12 ((TIM_TypeDef *) TIM12_BASE)
+#define TIM13 ((TIM_TypeDef *) TIM13_BASE)
+#define TIM14 ((TIM_TypeDef *) TIM14_BASE)
+#define RTC ((RTC_TypeDef *) RTC_BASE)
+#define WWDG ((WWDG_TypeDef *) WWDG_BASE)
+#define IWDG ((IWDG_TypeDef *) IWDG_BASE)
+#define SPI2 ((SPI_TypeDef *) SPI2_BASE)
+#define SPI3 ((SPI_TypeDef *) SPI3_BASE)
+#define USART2 ((USART_TypeDef *) USART2_BASE)
+#define USART3 ((USART_TypeDef *) USART3_BASE)
+#define UART4 ((USART_TypeDef *) UART4_BASE)
+#define UART5 ((USART_TypeDef *) UART5_BASE)
+#define I2C1 ((I2C_TypeDef *) I2C1_BASE)
+#define I2C2 ((I2C_TypeDef *) I2C2_BASE)
+#define USB ((USB_TypeDef *) USB_BASE)
+#define CAN1 ((CAN_TypeDef *) CAN1_BASE)
+#define BKP ((BKP_TypeDef *) BKP_BASE)
+#define PWR ((PWR_TypeDef *) PWR_BASE)
+#define DAC ((DAC_TypeDef *) DAC_BASE)
+#define AFIO ((AFIO_TypeDef *) AFIO_BASE)
+#define EXTI ((EXTI_TypeDef *) EXTI_BASE)
+#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
+#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
+#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
+#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
+#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
+#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
+#define GPIOG ((GPIO_TypeDef *) GPIOG_BASE)
+#define ADC1 ((ADC_TypeDef *) ADC1_BASE)
+#define ADC2 ((ADC_TypeDef *) ADC2_BASE)
+#define ADC3 ((ADC_TypeDef *) ADC3_BASE)
+#define ADC12_COMMON ((ADC_Common_TypeDef *) ADC1_BASE)
+#define TIM1 ((TIM_TypeDef *) TIM1_BASE)
+#define SPI1 ((SPI_TypeDef *) SPI1_BASE)
+#define TIM8 ((TIM_TypeDef *) TIM8_BASE)
+#define USART1 ((USART_TypeDef *) USART1_BASE)
+#define TIM9 ((TIM_TypeDef *) TIM9_BASE)
+#define TIM10 ((TIM_TypeDef *) TIM10_BASE)
+#define TIM11 ((TIM_TypeDef *) TIM11_BASE)
+#define SDIO ((SDIO_TypeDef *) SDIO_BASE)
+#define DMA1 ((DMA_TypeDef *) DMA1_BASE)
+#define DMA2 ((DMA_TypeDef *) DMA2_BASE)
+#define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
+#define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
+#define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
+#define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
+#define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
+#define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
+#define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
+#define DMA2_Channel1 ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE)
+#define DMA2_Channel2 ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE)
+#define DMA2_Channel3 ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE)
+#define DMA2_Channel4 ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE)
+#define DMA2_Channel5 ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE)
+#define RCC ((RCC_TypeDef *) RCC_BASE)
+#define CRC ((CRC_TypeDef *) CRC_BASE)
+#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
+#define OB ((OB_TypeDef *) OB_BASE)
+#define FSMC_Bank1 ((FSMC_Bank1_TypeDef *) FSMC_BANK1_R_BASE)
+#define FSMC_Bank1E ((FSMC_Bank1E_TypeDef *) FSMC_BANK1E_R_BASE)
+#define FSMC_Bank2_3 ((FSMC_Bank2_3_TypeDef *) FSMC_BANK2_3_R_BASE)
+#define FSMC_Bank4 ((FSMC_Bank4_TypeDef *) FSMC_BANK4_R_BASE)
+#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
+
+
+/**
+ * @}
+ */
+
+/** @addtogroup Exported_constants
+ * @{
+ */
+
+ /** @addtogroup Peripheral_Registers_Bits_Definition
+ * @{
+ */
+
+/******************************************************************************/
+/* Peripheral Registers_Bits_Definition */
+/******************************************************************************/
+
+/******************************************************************************/
+/* */
+/* CRC calculation unit (CRC) */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for CRC_DR register *********************/
+#define CRC_DR_DR_Pos (0U)
+#define CRC_DR_DR_Msk (0xFFFFFFFFU << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */
+#define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */
+
+/******************* Bit definition for CRC_IDR register ********************/
+#define CRC_IDR_IDR_Pos (0U)
+#define CRC_IDR_IDR_Msk (0xFFU << CRC_IDR_IDR_Pos) /*!< 0x000000FF */
+#define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 8-bit data register bits */
+
+/******************** Bit definition for CRC_CR register ********************/
+#define CRC_CR_RESET_Pos (0U)
+#define CRC_CR_RESET_Msk (0x1U << CRC_CR_RESET_Pos) /*!< 0x00000001 */
+#define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET bit */
+
+/******************************************************************************/
+/* */
+/* Power Control */
+/* */
+/******************************************************************************/
+
+/******************** Bit definition for PWR_CR register ********************/
+#define PWR_CR_LPDS_Pos (0U)
+#define PWR_CR_LPDS_Msk (0x1U << PWR_CR_LPDS_Pos) /*!< 0x00000001 */
+#define PWR_CR_LPDS PWR_CR_LPDS_Msk /*!< Low-Power Deepsleep */
+#define PWR_CR_PDDS_Pos (1U)
+#define PWR_CR_PDDS_Msk (0x1U << PWR_CR_PDDS_Pos) /*!< 0x00000002 */
+#define PWR_CR_PDDS PWR_CR_PDDS_Msk /*!< Power Down Deepsleep */
+#define PWR_CR_CWUF_Pos (2U)
+#define PWR_CR_CWUF_Msk (0x1U << PWR_CR_CWUF_Pos) /*!< 0x00000004 */
+#define PWR_CR_CWUF PWR_CR_CWUF_Msk /*!< Clear Wakeup Flag */
+#define PWR_CR_CSBF_Pos (3U)
+#define PWR_CR_CSBF_Msk (0x1U << PWR_CR_CSBF_Pos) /*!< 0x00000008 */
+#define PWR_CR_CSBF PWR_CR_CSBF_Msk /*!< Clear Standby Flag */
+#define PWR_CR_PVDE_Pos (4U)
+#define PWR_CR_PVDE_Msk (0x1U << PWR_CR_PVDE_Pos) /*!< 0x00000010 */
+#define PWR_CR_PVDE PWR_CR_PVDE_Msk /*!< Power Voltage Detector Enable */
+
+#define PWR_CR_PLS_Pos (5U)
+#define PWR_CR_PLS_Msk (0x7U << PWR_CR_PLS_Pos) /*!< 0x000000E0 */
+#define PWR_CR_PLS PWR_CR_PLS_Msk /*!< PLS[2:0] bits (PVD Level Selection) */
+#define PWR_CR_PLS_0 (0x1U << PWR_CR_PLS_Pos) /*!< 0x00000020 */
+#define PWR_CR_PLS_1 (0x2U << PWR_CR_PLS_Pos) /*!< 0x00000040 */
+#define PWR_CR_PLS_2 (0x4U << PWR_CR_PLS_Pos) /*!< 0x00000080 */
+
+/*!< PVD level configuration */
+#define PWR_CR_PLS_2V2 ((uint32_t)0x00000000) /*!< PVD level 2.2V */
+#define PWR_CR_PLS_2V3 ((uint32_t)0x00000020) /*!< PVD level 2.3V */
+#define PWR_CR_PLS_2V4 ((uint32_t)0x00000040) /*!< PVD level 2.4V */
+#define PWR_CR_PLS_2V5 ((uint32_t)0x00000060) /*!< PVD level 2.5V */
+#define PWR_CR_PLS_2V6 ((uint32_t)0x00000080) /*!< PVD level 2.6V */
+#define PWR_CR_PLS_2V7 ((uint32_t)0x000000A0) /*!< PVD level 2.7V */
+#define PWR_CR_PLS_2V8 ((uint32_t)0x000000C0) /*!< PVD level 2.8V */
+#define PWR_CR_PLS_2V9 ((uint32_t)0x000000E0) /*!< PVD level 2.9V */
+
+#define PWR_CR_DBP_Pos (8U)
+#define PWR_CR_DBP_Msk (0x1U << PWR_CR_DBP_Pos) /*!< 0x00000100 */
+#define PWR_CR_DBP PWR_CR_DBP_Msk /*!< Disable Backup Domain write protection */
+
+
+/******************* Bit definition for PWR_CSR register ********************/
+#define PWR_CSR_WUF_Pos (0U)
+#define PWR_CSR_WUF_Msk (0x1U << PWR_CSR_WUF_Pos) /*!< 0x00000001 */
+#define PWR_CSR_WUF PWR_CSR_WUF_Msk /*!< Wakeup Flag */
+#define PWR_CSR_SBF_Pos (1U)
+#define PWR_CSR_SBF_Msk (0x1U << PWR_CSR_SBF_Pos) /*!< 0x00000002 */
+#define PWR_CSR_SBF PWR_CSR_SBF_Msk /*!< Standby Flag */
+#define PWR_CSR_PVDO_Pos (2U)
+#define PWR_CSR_PVDO_Msk (0x1U << PWR_CSR_PVDO_Pos) /*!< 0x00000004 */
+#define PWR_CSR_PVDO PWR_CSR_PVDO_Msk /*!< PVD Output */
+#define PWR_CSR_EWUP_Pos (8U)
+#define PWR_CSR_EWUP_Msk (0x1U << PWR_CSR_EWUP_Pos) /*!< 0x00000100 */
+#define PWR_CSR_EWUP PWR_CSR_EWUP_Msk /*!< Enable WKUP pin */
+
+/******************************************************************************/
+/* */
+/* Backup registers */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for BKP_DR1 register ********************/
+#define BKP_DR1_D_Pos (0U)
+#define BKP_DR1_D_Msk (0xFFFFU << BKP_DR1_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR1_D BKP_DR1_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR2 register ********************/
+#define BKP_DR2_D_Pos (0U)
+#define BKP_DR2_D_Msk (0xFFFFU << BKP_DR2_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR2_D BKP_DR2_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR3 register ********************/
+#define BKP_DR3_D_Pos (0U)
+#define BKP_DR3_D_Msk (0xFFFFU << BKP_DR3_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR3_D BKP_DR3_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR4 register ********************/
+#define BKP_DR4_D_Pos (0U)
+#define BKP_DR4_D_Msk (0xFFFFU << BKP_DR4_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR4_D BKP_DR4_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR5 register ********************/
+#define BKP_DR5_D_Pos (0U)
+#define BKP_DR5_D_Msk (0xFFFFU << BKP_DR5_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR5_D BKP_DR5_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR6 register ********************/
+#define BKP_DR6_D_Pos (0U)
+#define BKP_DR6_D_Msk (0xFFFFU << BKP_DR6_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR6_D BKP_DR6_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR7 register ********************/
+#define BKP_DR7_D_Pos (0U)
+#define BKP_DR7_D_Msk (0xFFFFU << BKP_DR7_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR7_D BKP_DR7_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR8 register ********************/
+#define BKP_DR8_D_Pos (0U)
+#define BKP_DR8_D_Msk (0xFFFFU << BKP_DR8_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR8_D BKP_DR8_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR9 register ********************/
+#define BKP_DR9_D_Pos (0U)
+#define BKP_DR9_D_Msk (0xFFFFU << BKP_DR9_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR9_D BKP_DR9_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR10 register *******************/
+#define BKP_DR10_D_Pos (0U)
+#define BKP_DR10_D_Msk (0xFFFFU << BKP_DR10_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR10_D BKP_DR10_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR11 register *******************/
+#define BKP_DR11_D_Pos (0U)
+#define BKP_DR11_D_Msk (0xFFFFU << BKP_DR11_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR11_D BKP_DR11_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR12 register *******************/
+#define BKP_DR12_D_Pos (0U)
+#define BKP_DR12_D_Msk (0xFFFFU << BKP_DR12_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR12_D BKP_DR12_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR13 register *******************/
+#define BKP_DR13_D_Pos (0U)
+#define BKP_DR13_D_Msk (0xFFFFU << BKP_DR13_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR13_D BKP_DR13_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR14 register *******************/
+#define BKP_DR14_D_Pos (0U)
+#define BKP_DR14_D_Msk (0xFFFFU << BKP_DR14_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR14_D BKP_DR14_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR15 register *******************/
+#define BKP_DR15_D_Pos (0U)
+#define BKP_DR15_D_Msk (0xFFFFU << BKP_DR15_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR15_D BKP_DR15_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR16 register *******************/
+#define BKP_DR16_D_Pos (0U)
+#define BKP_DR16_D_Msk (0xFFFFU << BKP_DR16_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR16_D BKP_DR16_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR17 register *******************/
+#define BKP_DR17_D_Pos (0U)
+#define BKP_DR17_D_Msk (0xFFFFU << BKP_DR17_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR17_D BKP_DR17_D_Msk /*!< Backup data */
+
+/****************** Bit definition for BKP_DR18 register ********************/
+#define BKP_DR18_D_Pos (0U)
+#define BKP_DR18_D_Msk (0xFFFFU << BKP_DR18_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR18_D BKP_DR18_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR19 register *******************/
+#define BKP_DR19_D_Pos (0U)
+#define BKP_DR19_D_Msk (0xFFFFU << BKP_DR19_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR19_D BKP_DR19_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR20 register *******************/
+#define BKP_DR20_D_Pos (0U)
+#define BKP_DR20_D_Msk (0xFFFFU << BKP_DR20_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR20_D BKP_DR20_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR21 register *******************/
+#define BKP_DR21_D_Pos (0U)
+#define BKP_DR21_D_Msk (0xFFFFU << BKP_DR21_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR21_D BKP_DR21_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR22 register *******************/
+#define BKP_DR22_D_Pos (0U)
+#define BKP_DR22_D_Msk (0xFFFFU << BKP_DR22_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR22_D BKP_DR22_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR23 register *******************/
+#define BKP_DR23_D_Pos (0U)
+#define BKP_DR23_D_Msk (0xFFFFU << BKP_DR23_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR23_D BKP_DR23_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR24 register *******************/
+#define BKP_DR24_D_Pos (0U)
+#define BKP_DR24_D_Msk (0xFFFFU << BKP_DR24_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR24_D BKP_DR24_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR25 register *******************/
+#define BKP_DR25_D_Pos (0U)
+#define BKP_DR25_D_Msk (0xFFFFU << BKP_DR25_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR25_D BKP_DR25_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR26 register *******************/
+#define BKP_DR26_D_Pos (0U)
+#define BKP_DR26_D_Msk (0xFFFFU << BKP_DR26_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR26_D BKP_DR26_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR27 register *******************/
+#define BKP_DR27_D_Pos (0U)
+#define BKP_DR27_D_Msk (0xFFFFU << BKP_DR27_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR27_D BKP_DR27_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR28 register *******************/
+#define BKP_DR28_D_Pos (0U)
+#define BKP_DR28_D_Msk (0xFFFFU << BKP_DR28_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR28_D BKP_DR28_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR29 register *******************/
+#define BKP_DR29_D_Pos (0U)
+#define BKP_DR29_D_Msk (0xFFFFU << BKP_DR29_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR29_D BKP_DR29_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR30 register *******************/
+#define BKP_DR30_D_Pos (0U)
+#define BKP_DR30_D_Msk (0xFFFFU << BKP_DR30_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR30_D BKP_DR30_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR31 register *******************/
+#define BKP_DR31_D_Pos (0U)
+#define BKP_DR31_D_Msk (0xFFFFU << BKP_DR31_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR31_D BKP_DR31_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR32 register *******************/
+#define BKP_DR32_D_Pos (0U)
+#define BKP_DR32_D_Msk (0xFFFFU << BKP_DR32_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR32_D BKP_DR32_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR33 register *******************/
+#define BKP_DR33_D_Pos (0U)
+#define BKP_DR33_D_Msk (0xFFFFU << BKP_DR33_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR33_D BKP_DR33_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR34 register *******************/
+#define BKP_DR34_D_Pos (0U)
+#define BKP_DR34_D_Msk (0xFFFFU << BKP_DR34_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR34_D BKP_DR34_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR35 register *******************/
+#define BKP_DR35_D_Pos (0U)
+#define BKP_DR35_D_Msk (0xFFFFU << BKP_DR35_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR35_D BKP_DR35_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR36 register *******************/
+#define BKP_DR36_D_Pos (0U)
+#define BKP_DR36_D_Msk (0xFFFFU << BKP_DR36_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR36_D BKP_DR36_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR37 register *******************/
+#define BKP_DR37_D_Pos (0U)
+#define BKP_DR37_D_Msk (0xFFFFU << BKP_DR37_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR37_D BKP_DR37_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR38 register *******************/
+#define BKP_DR38_D_Pos (0U)
+#define BKP_DR38_D_Msk (0xFFFFU << BKP_DR38_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR38_D BKP_DR38_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR39 register *******************/
+#define BKP_DR39_D_Pos (0U)
+#define BKP_DR39_D_Msk (0xFFFFU << BKP_DR39_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR39_D BKP_DR39_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR40 register *******************/
+#define BKP_DR40_D_Pos (0U)
+#define BKP_DR40_D_Msk (0xFFFFU << BKP_DR40_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR40_D BKP_DR40_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR41 register *******************/
+#define BKP_DR41_D_Pos (0U)
+#define BKP_DR41_D_Msk (0xFFFFU << BKP_DR41_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR41_D BKP_DR41_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR42 register *******************/
+#define BKP_DR42_D_Pos (0U)
+#define BKP_DR42_D_Msk (0xFFFFU << BKP_DR42_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR42_D BKP_DR42_D_Msk /*!< Backup data */
+
+#define RTC_BKP_NUMBER 42
+
+/****************** Bit definition for BKP_RTCCR register *******************/
+#define BKP_RTCCR_CAL_Pos (0U)
+#define BKP_RTCCR_CAL_Msk (0x7FU << BKP_RTCCR_CAL_Pos) /*!< 0x0000007F */
+#define BKP_RTCCR_CAL BKP_RTCCR_CAL_Msk /*!< Calibration value */
+#define BKP_RTCCR_CCO_Pos (7U)
+#define BKP_RTCCR_CCO_Msk (0x1U << BKP_RTCCR_CCO_Pos) /*!< 0x00000080 */
+#define BKP_RTCCR_CCO BKP_RTCCR_CCO_Msk /*!< Calibration Clock Output */
+#define BKP_RTCCR_ASOE_Pos (8U)
+#define BKP_RTCCR_ASOE_Msk (0x1U << BKP_RTCCR_ASOE_Pos) /*!< 0x00000100 */
+#define BKP_RTCCR_ASOE BKP_RTCCR_ASOE_Msk /*!< Alarm or Second Output Enable */
+#define BKP_RTCCR_ASOS_Pos (9U)
+#define BKP_RTCCR_ASOS_Msk (0x1U << BKP_RTCCR_ASOS_Pos) /*!< 0x00000200 */
+#define BKP_RTCCR_ASOS BKP_RTCCR_ASOS_Msk /*!< Alarm or Second Output Selection */
+
+/******************** Bit definition for BKP_CR register ********************/
+#define BKP_CR_TPE_Pos (0U)
+#define BKP_CR_TPE_Msk (0x1U << BKP_CR_TPE_Pos) /*!< 0x00000001 */
+#define BKP_CR_TPE BKP_CR_TPE_Msk /*!< TAMPER pin enable */
+#define BKP_CR_TPAL_Pos (1U)
+#define BKP_CR_TPAL_Msk (0x1U << BKP_CR_TPAL_Pos) /*!< 0x00000002 */
+#define BKP_CR_TPAL BKP_CR_TPAL_Msk /*!< TAMPER pin active level */
+
+/******************* Bit definition for BKP_CSR register ********************/
+#define BKP_CSR_CTE_Pos (0U)
+#define BKP_CSR_CTE_Msk (0x1U << BKP_CSR_CTE_Pos) /*!< 0x00000001 */
+#define BKP_CSR_CTE BKP_CSR_CTE_Msk /*!< Clear Tamper event */
+#define BKP_CSR_CTI_Pos (1U)
+#define BKP_CSR_CTI_Msk (0x1U << BKP_CSR_CTI_Pos) /*!< 0x00000002 */
+#define BKP_CSR_CTI BKP_CSR_CTI_Msk /*!< Clear Tamper Interrupt */
+#define BKP_CSR_TPIE_Pos (2U)
+#define BKP_CSR_TPIE_Msk (0x1U << BKP_CSR_TPIE_Pos) /*!< 0x00000004 */
+#define BKP_CSR_TPIE BKP_CSR_TPIE_Msk /*!< TAMPER Pin interrupt enable */
+#define BKP_CSR_TEF_Pos (8U)
+#define BKP_CSR_TEF_Msk (0x1U << BKP_CSR_TEF_Pos) /*!< 0x00000100 */
+#define BKP_CSR_TEF BKP_CSR_TEF_Msk /*!< Tamper Event Flag */
+#define BKP_CSR_TIF_Pos (9U)
+#define BKP_CSR_TIF_Msk (0x1U << BKP_CSR_TIF_Pos) /*!< 0x00000200 */
+#define BKP_CSR_TIF BKP_CSR_TIF_Msk /*!< Tamper Interrupt Flag */
+
+/******************************************************************************/
+/* */
+/* Reset and Clock Control */
+/* */
+/******************************************************************************/
+
+/******************** Bit definition for RCC_CR register ********************/
+#define RCC_CR_HSION_Pos (0U)
+#define RCC_CR_HSION_Msk (0x1U << RCC_CR_HSION_Pos) /*!< 0x00000001 */
+#define RCC_CR_HSION RCC_CR_HSION_Msk /*!< Internal High Speed clock enable */
+#define RCC_CR_HSIRDY_Pos (1U)
+#define RCC_CR_HSIRDY_Msk (0x1U << RCC_CR_HSIRDY_Pos) /*!< 0x00000002 */
+#define RCC_CR_HSIRDY RCC_CR_HSIRDY_Msk /*!< Internal High Speed clock ready flag */
+#define RCC_CR_HSITRIM_Pos (3U)
+#define RCC_CR_HSITRIM_Msk (0x1FU << RCC_CR_HSITRIM_Pos) /*!< 0x000000F8 */
+#define RCC_CR_HSITRIM RCC_CR_HSITRIM_Msk /*!< Internal High Speed clock trimming */
+#define RCC_CR_HSICAL_Pos (8U)
+#define RCC_CR_HSICAL_Msk (0xFFU << RCC_CR_HSICAL_Pos) /*!< 0x0000FF00 */
+#define RCC_CR_HSICAL RCC_CR_HSICAL_Msk /*!< Internal High Speed clock Calibration */
+#define RCC_CR_HSEON_Pos (16U)
+#define RCC_CR_HSEON_Msk (0x1U << RCC_CR_HSEON_Pos) /*!< 0x00010000 */
+#define RCC_CR_HSEON RCC_CR_HSEON_Msk /*!< External High Speed clock enable */
+#define RCC_CR_HSERDY_Pos (17U)
+#define RCC_CR_HSERDY_Msk (0x1U << RCC_CR_HSERDY_Pos) /*!< 0x00020000 */
+#define RCC_CR_HSERDY RCC_CR_HSERDY_Msk /*!< External High Speed clock ready flag */
+#define RCC_CR_HSEBYP_Pos (18U)
+#define RCC_CR_HSEBYP_Msk (0x1U << RCC_CR_HSEBYP_Pos) /*!< 0x00040000 */
+#define RCC_CR_HSEBYP RCC_CR_HSEBYP_Msk /*!< External High Speed clock Bypass */
+#define RCC_CR_CSSON_Pos (19U)
+#define RCC_CR_CSSON_Msk (0x1U << RCC_CR_CSSON_Pos) /*!< 0x00080000 */
+#define RCC_CR_CSSON RCC_CR_CSSON_Msk /*!< Clock Security System enable */
+#define RCC_CR_PLLON_Pos (24U)
+#define RCC_CR_PLLON_Msk (0x1U << RCC_CR_PLLON_Pos) /*!< 0x01000000 */
+#define RCC_CR_PLLON RCC_CR_PLLON_Msk /*!< PLL enable */
+#define RCC_CR_PLLRDY_Pos (25U)
+#define RCC_CR_PLLRDY_Msk (0x1U << RCC_CR_PLLRDY_Pos) /*!< 0x02000000 */
+#define RCC_CR_PLLRDY RCC_CR_PLLRDY_Msk /*!< PLL clock ready flag */
+
+
+/******************* Bit definition for RCC_CFGR register *******************/
+/*!< SW configuration */
+#define RCC_CFGR_SW_Pos (0U)
+#define RCC_CFGR_SW_Msk (0x3U << RCC_CFGR_SW_Pos) /*!< 0x00000003 */
+#define RCC_CFGR_SW RCC_CFGR_SW_Msk /*!< SW[1:0] bits (System clock Switch) */
+#define RCC_CFGR_SW_0 (0x1U << RCC_CFGR_SW_Pos) /*!< 0x00000001 */
+#define RCC_CFGR_SW_1 (0x2U << RCC_CFGR_SW_Pos) /*!< 0x00000002 */
+
+#define RCC_CFGR_SW_HSI ((uint32_t)0x00000000) /*!< HSI selected as system clock */
+#define RCC_CFGR_SW_HSE ((uint32_t)0x00000001) /*!< HSE selected as system clock */
+#define RCC_CFGR_SW_PLL ((uint32_t)0x00000002) /*!< PLL selected as system clock */
+
+/*!< SWS configuration */
+#define RCC_CFGR_SWS_Pos (2U)
+#define RCC_CFGR_SWS_Msk (0x3U << RCC_CFGR_SWS_Pos) /*!< 0x0000000C */
+#define RCC_CFGR_SWS RCC_CFGR_SWS_Msk /*!< SWS[1:0] bits (System Clock Switch Status) */
+#define RCC_CFGR_SWS_0 (0x1U << RCC_CFGR_SWS_Pos) /*!< 0x00000004 */
+#define RCC_CFGR_SWS_1 (0x2U << RCC_CFGR_SWS_Pos) /*!< 0x00000008 */
+
+#define RCC_CFGR_SWS_HSI ((uint32_t)0x00000000) /*!< HSI oscillator used as system clock */
+#define RCC_CFGR_SWS_HSE ((uint32_t)0x00000004) /*!< HSE oscillator used as system clock */
+#define RCC_CFGR_SWS_PLL ((uint32_t)0x00000008) /*!< PLL used as system clock */
+
+/*!< HPRE configuration */
+#define RCC_CFGR_HPRE_Pos (4U)
+#define RCC_CFGR_HPRE_Msk (0xFU << RCC_CFGR_HPRE_Pos) /*!< 0x000000F0 */
+#define RCC_CFGR_HPRE RCC_CFGR_HPRE_Msk /*!< HPRE[3:0] bits (AHB prescaler) */
+#define RCC_CFGR_HPRE_0 (0x1U << RCC_CFGR_HPRE_Pos) /*!< 0x00000010 */
+#define RCC_CFGR_HPRE_1 (0x2U << RCC_CFGR_HPRE_Pos) /*!< 0x00000020 */
+#define RCC_CFGR_HPRE_2 (0x4U << RCC_CFGR_HPRE_Pos) /*!< 0x00000040 */
+#define RCC_CFGR_HPRE_3 (0x8U << RCC_CFGR_HPRE_Pos) /*!< 0x00000080 */
+
+#define RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000) /*!< SYSCLK not divided */
+#define RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080) /*!< SYSCLK divided by 2 */
+#define RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090) /*!< SYSCLK divided by 4 */
+#define RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0) /*!< SYSCLK divided by 8 */
+#define RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0) /*!< SYSCLK divided by 16 */
+#define RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0) /*!< SYSCLK divided by 64 */
+#define RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0) /*!< SYSCLK divided by 128 */
+#define RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0) /*!< SYSCLK divided by 256 */
+#define RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0) /*!< SYSCLK divided by 512 */
+
+/*!< PPRE1 configuration */
+#define RCC_CFGR_PPRE1_Pos (8U)
+#define RCC_CFGR_PPRE1_Msk (0x7U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000700 */
+#define RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_Msk /*!< PRE1[2:0] bits (APB1 prescaler) */
+#define RCC_CFGR_PPRE1_0 (0x1U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000100 */
+#define RCC_CFGR_PPRE1_1 (0x2U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000200 */
+#define RCC_CFGR_PPRE1_2 (0x4U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000400 */
+
+#define RCC_CFGR_PPRE1_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */
+#define RCC_CFGR_PPRE1_DIV2 ((uint32_t)0x00000400) /*!< HCLK divided by 2 */
+#define RCC_CFGR_PPRE1_DIV4 ((uint32_t)0x00000500) /*!< HCLK divided by 4 */
+#define RCC_CFGR_PPRE1_DIV8 ((uint32_t)0x00000600) /*!< HCLK divided by 8 */
+#define RCC_CFGR_PPRE1_DIV16 ((uint32_t)0x00000700) /*!< HCLK divided by 16 */
+
+/*!< PPRE2 configuration */
+#define RCC_CFGR_PPRE2_Pos (11U)
+#define RCC_CFGR_PPRE2_Msk (0x7U << RCC_CFGR_PPRE2_Pos) /*!< 0x00003800 */
+#define RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_Msk /*!< PRE2[2:0] bits (APB2 prescaler) */
+#define RCC_CFGR_PPRE2_0 (0x1U << RCC_CFGR_PPRE2_Pos) /*!< 0x00000800 */
+#define RCC_CFGR_PPRE2_1 (0x2U << RCC_CFGR_PPRE2_Pos) /*!< 0x00001000 */
+#define RCC_CFGR_PPRE2_2 (0x4U << RCC_CFGR_PPRE2_Pos) /*!< 0x00002000 */
+
+#define RCC_CFGR_PPRE2_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */
+#define RCC_CFGR_PPRE2_DIV2 ((uint32_t)0x00002000) /*!< HCLK divided by 2 */
+#define RCC_CFGR_PPRE2_DIV4 ((uint32_t)0x00002800) /*!< HCLK divided by 4 */
+#define RCC_CFGR_PPRE2_DIV8 ((uint32_t)0x00003000) /*!< HCLK divided by 8 */
+#define RCC_CFGR_PPRE2_DIV16 ((uint32_t)0x00003800) /*!< HCLK divided by 16 */
+
+/*!< ADCPPRE configuration */
+#define RCC_CFGR_ADCPRE_Pos (14U)
+#define RCC_CFGR_ADCPRE_Msk (0x3U << RCC_CFGR_ADCPRE_Pos) /*!< 0x0000C000 */
+#define RCC_CFGR_ADCPRE RCC_CFGR_ADCPRE_Msk /*!< ADCPRE[1:0] bits (ADC prescaler) */
+#define RCC_CFGR_ADCPRE_0 (0x1U << RCC_CFGR_ADCPRE_Pos) /*!< 0x00004000 */
+#define RCC_CFGR_ADCPRE_1 (0x2U << RCC_CFGR_ADCPRE_Pos) /*!< 0x00008000 */
+
+#define RCC_CFGR_ADCPRE_DIV2 ((uint32_t)0x00000000) /*!< PCLK2 divided by 2 */
+#define RCC_CFGR_ADCPRE_DIV4 ((uint32_t)0x00004000) /*!< PCLK2 divided by 4 */
+#define RCC_CFGR_ADCPRE_DIV6 ((uint32_t)0x00008000) /*!< PCLK2 divided by 6 */
+#define RCC_CFGR_ADCPRE_DIV8 ((uint32_t)0x0000C000) /*!< PCLK2 divided by 8 */
+
+#define RCC_CFGR_PLLSRC_Pos (16U)
+#define RCC_CFGR_PLLSRC_Msk (0x1U << RCC_CFGR_PLLSRC_Pos) /*!< 0x00010000 */
+#define RCC_CFGR_PLLSRC RCC_CFGR_PLLSRC_Msk /*!< PLL entry clock source */
+
+#define RCC_CFGR_PLLXTPRE_Pos (17U)
+#define RCC_CFGR_PLLXTPRE_Msk (0x1U << RCC_CFGR_PLLXTPRE_Pos) /*!< 0x00020000 */
+#define RCC_CFGR_PLLXTPRE RCC_CFGR_PLLXTPRE_Msk /*!< HSE divider for PLL entry */
+
+/*!< PLLMUL configuration */
+#define RCC_CFGR_PLLMULL_Pos (18U)
+#define RCC_CFGR_PLLMULL_Msk (0xFU << RCC_CFGR_PLLMULL_Pos) /*!< 0x003C0000 */
+#define RCC_CFGR_PLLMULL RCC_CFGR_PLLMULL_Msk /*!< PLLMUL[3:0] bits (PLL multiplication factor) */
+#define RCC_CFGR_PLLMULL_0 (0x1U << RCC_CFGR_PLLMULL_Pos) /*!< 0x00040000 */
+#define RCC_CFGR_PLLMULL_1 (0x2U << RCC_CFGR_PLLMULL_Pos) /*!< 0x00080000 */
+#define RCC_CFGR_PLLMULL_2 (0x4U << RCC_CFGR_PLLMULL_Pos) /*!< 0x00100000 */
+#define RCC_CFGR_PLLMULL_3 (0x8U << RCC_CFGR_PLLMULL_Pos) /*!< 0x00200000 */
+
+#define RCC_CFGR_PLLXTPRE_HSE ((uint32_t)0x00000000) /*!< HSE clock not divided for PLL entry */
+#define RCC_CFGR_PLLXTPRE_HSE_DIV2 ((uint32_t)0x00020000) /*!< HSE clock divided by 2 for PLL entry */
+
+#define RCC_CFGR_PLLMULL2 ((uint32_t)0x00000000) /*!< PLL input clock*2 */
+#define RCC_CFGR_PLLMULL3_Pos (18U)
+#define RCC_CFGR_PLLMULL3_Msk (0x1U << RCC_CFGR_PLLMULL3_Pos) /*!< 0x00040000 */
+#define RCC_CFGR_PLLMULL3 RCC_CFGR_PLLMULL3_Msk /*!< PLL input clock*3 */
+#define RCC_CFGR_PLLMULL4_Pos (19U)
+#define RCC_CFGR_PLLMULL4_Msk (0x1U << RCC_CFGR_PLLMULL4_Pos) /*!< 0x00080000 */
+#define RCC_CFGR_PLLMULL4 RCC_CFGR_PLLMULL4_Msk /*!< PLL input clock*4 */
+#define RCC_CFGR_PLLMULL5_Pos (18U)
+#define RCC_CFGR_PLLMULL5_Msk (0x3U << RCC_CFGR_PLLMULL5_Pos) /*!< 0x000C0000 */
+#define RCC_CFGR_PLLMULL5 RCC_CFGR_PLLMULL5_Msk /*!< PLL input clock*5 */
+#define RCC_CFGR_PLLMULL6_Pos (20U)
+#define RCC_CFGR_PLLMULL6_Msk (0x1U << RCC_CFGR_PLLMULL6_Pos) /*!< 0x00100000 */
+#define RCC_CFGR_PLLMULL6 RCC_CFGR_PLLMULL6_Msk /*!< PLL input clock*6 */
+#define RCC_CFGR_PLLMULL7_Pos (18U)
+#define RCC_CFGR_PLLMULL7_Msk (0x5U << RCC_CFGR_PLLMULL7_Pos) /*!< 0x00140000 */
+#define RCC_CFGR_PLLMULL7 RCC_CFGR_PLLMULL7_Msk /*!< PLL input clock*7 */
+#define RCC_CFGR_PLLMULL8_Pos (19U)
+#define RCC_CFGR_PLLMULL8_Msk (0x3U << RCC_CFGR_PLLMULL8_Pos) /*!< 0x00180000 */
+#define RCC_CFGR_PLLMULL8 RCC_CFGR_PLLMULL8_Msk /*!< PLL input clock*8 */
+#define RCC_CFGR_PLLMULL9_Pos (18U)
+#define RCC_CFGR_PLLMULL9_Msk (0x7U << RCC_CFGR_PLLMULL9_Pos) /*!< 0x001C0000 */
+#define RCC_CFGR_PLLMULL9 RCC_CFGR_PLLMULL9_Msk /*!< PLL input clock*9 */
+#define RCC_CFGR_PLLMULL10_Pos (21U)
+#define RCC_CFGR_PLLMULL10_Msk (0x1U << RCC_CFGR_PLLMULL10_Pos) /*!< 0x00200000 */
+#define RCC_CFGR_PLLMULL10 RCC_CFGR_PLLMULL10_Msk /*!< PLL input clock10 */
+#define RCC_CFGR_PLLMULL11_Pos (18U)
+#define RCC_CFGR_PLLMULL11_Msk (0x9U << RCC_CFGR_PLLMULL11_Pos) /*!< 0x00240000 */
+#define RCC_CFGR_PLLMULL11 RCC_CFGR_PLLMULL11_Msk /*!< PLL input clock*11 */
+#define RCC_CFGR_PLLMULL12_Pos (19U)
+#define RCC_CFGR_PLLMULL12_Msk (0x5U << RCC_CFGR_PLLMULL12_Pos) /*!< 0x00280000 */
+#define RCC_CFGR_PLLMULL12 RCC_CFGR_PLLMULL12_Msk /*!< PLL input clock*12 */
+#define RCC_CFGR_PLLMULL13_Pos (18U)
+#define RCC_CFGR_PLLMULL13_Msk (0xBU << RCC_CFGR_PLLMULL13_Pos) /*!< 0x002C0000 */
+#define RCC_CFGR_PLLMULL13 RCC_CFGR_PLLMULL13_Msk /*!< PLL input clock*13 */
+#define RCC_CFGR_PLLMULL14_Pos (20U)
+#define RCC_CFGR_PLLMULL14_Msk (0x3U << RCC_CFGR_PLLMULL14_Pos) /*!< 0x00300000 */
+#define RCC_CFGR_PLLMULL14 RCC_CFGR_PLLMULL14_Msk /*!< PLL input clock*14 */
+#define RCC_CFGR_PLLMULL15_Pos (18U)
+#define RCC_CFGR_PLLMULL15_Msk (0xDU << RCC_CFGR_PLLMULL15_Pos) /*!< 0x00340000 */
+#define RCC_CFGR_PLLMULL15 RCC_CFGR_PLLMULL15_Msk /*!< PLL input clock*15 */
+#define RCC_CFGR_PLLMULL16_Pos (19U)
+#define RCC_CFGR_PLLMULL16_Msk (0x7U << RCC_CFGR_PLLMULL16_Pos) /*!< 0x00380000 */
+#define RCC_CFGR_PLLMULL16 RCC_CFGR_PLLMULL16_Msk /*!< PLL input clock*16 */
+#define RCC_CFGR_USBPRE_Pos (22U)
+#define RCC_CFGR_USBPRE_Msk (0x1U << RCC_CFGR_USBPRE_Pos) /*!< 0x00400000 */
+#define RCC_CFGR_USBPRE RCC_CFGR_USBPRE_Msk /*!< USB Device prescaler */
+
+/*!< MCO configuration */
+#define RCC_CFGR_MCO_Pos (24U)
+#define RCC_CFGR_MCO_Msk (0x7U << RCC_CFGR_MCO_Pos) /*!< 0x07000000 */
+#define RCC_CFGR_MCO RCC_CFGR_MCO_Msk /*!< MCO[2:0] bits (Microcontroller Clock Output) */
+#define RCC_CFGR_MCO_0 (0x1U << RCC_CFGR_MCO_Pos) /*!< 0x01000000 */
+#define RCC_CFGR_MCO_1 (0x2U << RCC_CFGR_MCO_Pos) /*!< 0x02000000 */
+#define RCC_CFGR_MCO_2 (0x4U << RCC_CFGR_MCO_Pos) /*!< 0x04000000 */
+
+#define RCC_CFGR_MCO_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */
+#define RCC_CFGR_MCO_SYSCLK ((uint32_t)0x04000000) /*!< System clock selected as MCO source */
+#define RCC_CFGR_MCO_HSI ((uint32_t)0x05000000) /*!< HSI clock selected as MCO source */
+#define RCC_CFGR_MCO_HSE ((uint32_t)0x06000000) /*!< HSE clock selected as MCO source */
+#define RCC_CFGR_MCO_PLLCLK_DIV2 ((uint32_t)0x07000000) /*!< PLL clock divided by 2 selected as MCO source */
+
+ /* Reference defines */
+ #define RCC_CFGR_MCOSEL RCC_CFGR_MCO
+ #define RCC_CFGR_MCOSEL_0 RCC_CFGR_MCO_0
+ #define RCC_CFGR_MCOSEL_1 RCC_CFGR_MCO_1
+ #define RCC_CFGR_MCOSEL_2 RCC_CFGR_MCO_2
+ #define RCC_CFGR_MCOSEL_NOCLOCK RCC_CFGR_MCO_NOCLOCK
+ #define RCC_CFGR_MCOSEL_SYSCLK RCC_CFGR_MCO_SYSCLK
+ #define RCC_CFGR_MCOSEL_HSI RCC_CFGR_MCO_HSI
+ #define RCC_CFGR_MCOSEL_HSE RCC_CFGR_MCO_HSE
+ #define RCC_CFGR_MCOSEL_PLL_DIV2 RCC_CFGR_MCO_PLLCLK_DIV2
+
+/*!<****************** Bit definition for RCC_CIR register ********************/
+#define RCC_CIR_LSIRDYF_Pos (0U)
+#define RCC_CIR_LSIRDYF_Msk (0x1U << RCC_CIR_LSIRDYF_Pos) /*!< 0x00000001 */
+#define RCC_CIR_LSIRDYF RCC_CIR_LSIRDYF_Msk /*!< LSI Ready Interrupt flag */
+#define RCC_CIR_LSERDYF_Pos (1U)
+#define RCC_CIR_LSERDYF_Msk (0x1U << RCC_CIR_LSERDYF_Pos) /*!< 0x00000002 */
+#define RCC_CIR_LSERDYF RCC_CIR_LSERDYF_Msk /*!< LSE Ready Interrupt flag */
+#define RCC_CIR_HSIRDYF_Pos (2U)
+#define RCC_CIR_HSIRDYF_Msk (0x1U << RCC_CIR_HSIRDYF_Pos) /*!< 0x00000004 */
+#define RCC_CIR_HSIRDYF RCC_CIR_HSIRDYF_Msk /*!< HSI Ready Interrupt flag */
+#define RCC_CIR_HSERDYF_Pos (3U)
+#define RCC_CIR_HSERDYF_Msk (0x1U << RCC_CIR_HSERDYF_Pos) /*!< 0x00000008 */
+#define RCC_CIR_HSERDYF RCC_CIR_HSERDYF_Msk /*!< HSE Ready Interrupt flag */
+#define RCC_CIR_PLLRDYF_Pos (4U)
+#define RCC_CIR_PLLRDYF_Msk (0x1U << RCC_CIR_PLLRDYF_Pos) /*!< 0x00000010 */
+#define RCC_CIR_PLLRDYF RCC_CIR_PLLRDYF_Msk /*!< PLL Ready Interrupt flag */
+#define RCC_CIR_CSSF_Pos (7U)
+#define RCC_CIR_CSSF_Msk (0x1U << RCC_CIR_CSSF_Pos) /*!< 0x00000080 */
+#define RCC_CIR_CSSF RCC_CIR_CSSF_Msk /*!< Clock Security System Interrupt flag */
+#define RCC_CIR_LSIRDYIE_Pos (8U)
+#define RCC_CIR_LSIRDYIE_Msk (0x1U << RCC_CIR_LSIRDYIE_Pos) /*!< 0x00000100 */
+#define RCC_CIR_LSIRDYIE RCC_CIR_LSIRDYIE_Msk /*!< LSI Ready Interrupt Enable */
+#define RCC_CIR_LSERDYIE_Pos (9U)
+#define RCC_CIR_LSERDYIE_Msk (0x1U << RCC_CIR_LSERDYIE_Pos) /*!< 0x00000200 */
+#define RCC_CIR_LSERDYIE RCC_CIR_LSERDYIE_Msk /*!< LSE Ready Interrupt Enable */
+#define RCC_CIR_HSIRDYIE_Pos (10U)
+#define RCC_CIR_HSIRDYIE_Msk (0x1U << RCC_CIR_HSIRDYIE_Pos) /*!< 0x00000400 */
+#define RCC_CIR_HSIRDYIE RCC_CIR_HSIRDYIE_Msk /*!< HSI Ready Interrupt Enable */
+#define RCC_CIR_HSERDYIE_Pos (11U)
+#define RCC_CIR_HSERDYIE_Msk (0x1U << RCC_CIR_HSERDYIE_Pos) /*!< 0x00000800 */
+#define RCC_CIR_HSERDYIE RCC_CIR_HSERDYIE_Msk /*!< HSE Ready Interrupt Enable */
+#define RCC_CIR_PLLRDYIE_Pos (12U)
+#define RCC_CIR_PLLRDYIE_Msk (0x1U << RCC_CIR_PLLRDYIE_Pos) /*!< 0x00001000 */
+#define RCC_CIR_PLLRDYIE RCC_CIR_PLLRDYIE_Msk /*!< PLL Ready Interrupt Enable */
+#define RCC_CIR_LSIRDYC_Pos (16U)
+#define RCC_CIR_LSIRDYC_Msk (0x1U << RCC_CIR_LSIRDYC_Pos) /*!< 0x00010000 */
+#define RCC_CIR_LSIRDYC RCC_CIR_LSIRDYC_Msk /*!< LSI Ready Interrupt Clear */
+#define RCC_CIR_LSERDYC_Pos (17U)
+#define RCC_CIR_LSERDYC_Msk (0x1U << RCC_CIR_LSERDYC_Pos) /*!< 0x00020000 */
+#define RCC_CIR_LSERDYC RCC_CIR_LSERDYC_Msk /*!< LSE Ready Interrupt Clear */
+#define RCC_CIR_HSIRDYC_Pos (18U)
+#define RCC_CIR_HSIRDYC_Msk (0x1U << RCC_CIR_HSIRDYC_Pos) /*!< 0x00040000 */
+#define RCC_CIR_HSIRDYC RCC_CIR_HSIRDYC_Msk /*!< HSI Ready Interrupt Clear */
+#define RCC_CIR_HSERDYC_Pos (19U)
+#define RCC_CIR_HSERDYC_Msk (0x1U << RCC_CIR_HSERDYC_Pos) /*!< 0x00080000 */
+#define RCC_CIR_HSERDYC RCC_CIR_HSERDYC_Msk /*!< HSE Ready Interrupt Clear */
+#define RCC_CIR_PLLRDYC_Pos (20U)
+#define RCC_CIR_PLLRDYC_Msk (0x1U << RCC_CIR_PLLRDYC_Pos) /*!< 0x00100000 */
+#define RCC_CIR_PLLRDYC RCC_CIR_PLLRDYC_Msk /*!< PLL Ready Interrupt Clear */
+#define RCC_CIR_CSSC_Pos (23U)
+#define RCC_CIR_CSSC_Msk (0x1U << RCC_CIR_CSSC_Pos) /*!< 0x00800000 */
+#define RCC_CIR_CSSC RCC_CIR_CSSC_Msk /*!< Clock Security System Interrupt Clear */
+
+
+/***************** Bit definition for RCC_APB2RSTR register *****************/
+#define RCC_APB2RSTR_AFIORST_Pos (0U)
+#define RCC_APB2RSTR_AFIORST_Msk (0x1U << RCC_APB2RSTR_AFIORST_Pos) /*!< 0x00000001 */
+#define RCC_APB2RSTR_AFIORST RCC_APB2RSTR_AFIORST_Msk /*!< Alternate Function I/O reset */
+#define RCC_APB2RSTR_IOPARST_Pos (2U)
+#define RCC_APB2RSTR_IOPARST_Msk (0x1U << RCC_APB2RSTR_IOPARST_Pos) /*!< 0x00000004 */
+#define RCC_APB2RSTR_IOPARST RCC_APB2RSTR_IOPARST_Msk /*!< I/O port A reset */
+#define RCC_APB2RSTR_IOPBRST_Pos (3U)
+#define RCC_APB2RSTR_IOPBRST_Msk (0x1U << RCC_APB2RSTR_IOPBRST_Pos) /*!< 0x00000008 */
+#define RCC_APB2RSTR_IOPBRST RCC_APB2RSTR_IOPBRST_Msk /*!< I/O port B reset */
+#define RCC_APB2RSTR_IOPCRST_Pos (4U)
+#define RCC_APB2RSTR_IOPCRST_Msk (0x1U << RCC_APB2RSTR_IOPCRST_Pos) /*!< 0x00000010 */
+#define RCC_APB2RSTR_IOPCRST RCC_APB2RSTR_IOPCRST_Msk /*!< I/O port C reset */
+#define RCC_APB2RSTR_IOPDRST_Pos (5U)
+#define RCC_APB2RSTR_IOPDRST_Msk (0x1U << RCC_APB2RSTR_IOPDRST_Pos) /*!< 0x00000020 */
+#define RCC_APB2RSTR_IOPDRST RCC_APB2RSTR_IOPDRST_Msk /*!< I/O port D reset */
+#define RCC_APB2RSTR_ADC1RST_Pos (9U)
+#define RCC_APB2RSTR_ADC1RST_Msk (0x1U << RCC_APB2RSTR_ADC1RST_Pos) /*!< 0x00000200 */
+#define RCC_APB2RSTR_ADC1RST RCC_APB2RSTR_ADC1RST_Msk /*!< ADC 1 interface reset */
+
+#define RCC_APB2RSTR_ADC2RST_Pos (10U)
+#define RCC_APB2RSTR_ADC2RST_Msk (0x1U << RCC_APB2RSTR_ADC2RST_Pos) /*!< 0x00000400 */
+#define RCC_APB2RSTR_ADC2RST RCC_APB2RSTR_ADC2RST_Msk /*!< ADC 2 interface reset */
+
+#define RCC_APB2RSTR_TIM1RST_Pos (11U)
+#define RCC_APB2RSTR_TIM1RST_Msk (0x1U << RCC_APB2RSTR_TIM1RST_Pos) /*!< 0x00000800 */
+#define RCC_APB2RSTR_TIM1RST RCC_APB2RSTR_TIM1RST_Msk /*!< TIM1 Timer reset */
+#define RCC_APB2RSTR_SPI1RST_Pos (12U)
+#define RCC_APB2RSTR_SPI1RST_Msk (0x1U << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */
+#define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk /*!< SPI 1 reset */
+#define RCC_APB2RSTR_USART1RST_Pos (14U)
+#define RCC_APB2RSTR_USART1RST_Msk (0x1U << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00004000 */
+#define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk /*!< USART1 reset */
+
+
+#define RCC_APB2RSTR_IOPERST_Pos (6U)
+#define RCC_APB2RSTR_IOPERST_Msk (0x1U << RCC_APB2RSTR_IOPERST_Pos) /*!< 0x00000040 */
+#define RCC_APB2RSTR_IOPERST RCC_APB2RSTR_IOPERST_Msk /*!< I/O port E reset */
+
+#define RCC_APB2RSTR_IOPFRST_Pos (7U)
+#define RCC_APB2RSTR_IOPFRST_Msk (0x1U << RCC_APB2RSTR_IOPFRST_Pos) /*!< 0x00000080 */
+#define RCC_APB2RSTR_IOPFRST RCC_APB2RSTR_IOPFRST_Msk /*!< I/O port F reset */
+#define RCC_APB2RSTR_IOPGRST_Pos (8U)
+#define RCC_APB2RSTR_IOPGRST_Msk (0x1U << RCC_APB2RSTR_IOPGRST_Pos) /*!< 0x00000100 */
+#define RCC_APB2RSTR_IOPGRST RCC_APB2RSTR_IOPGRST_Msk /*!< I/O port G reset */
+#define RCC_APB2RSTR_TIM8RST_Pos (13U)
+#define RCC_APB2RSTR_TIM8RST_Msk (0x1U << RCC_APB2RSTR_TIM8RST_Pos) /*!< 0x00002000 */
+#define RCC_APB2RSTR_TIM8RST RCC_APB2RSTR_TIM8RST_Msk /*!< TIM8 Timer reset */
+#define RCC_APB2RSTR_ADC3RST_Pos (15U)
+#define RCC_APB2RSTR_ADC3RST_Msk (0x1U << RCC_APB2RSTR_ADC3RST_Pos) /*!< 0x00008000 */
+#define RCC_APB2RSTR_ADC3RST RCC_APB2RSTR_ADC3RST_Msk /*!< ADC3 interface reset */
+
+
+#define RCC_APB2RSTR_TIM9RST_Pos (19U)
+#define RCC_APB2RSTR_TIM9RST_Msk (0x1U << RCC_APB2RSTR_TIM9RST_Pos) /*!< 0x00080000 */
+#define RCC_APB2RSTR_TIM9RST RCC_APB2RSTR_TIM9RST_Msk /*!< TIM9 Timer reset */
+#define RCC_APB2RSTR_TIM10RST_Pos (20U)
+#define RCC_APB2RSTR_TIM10RST_Msk (0x1U << RCC_APB2RSTR_TIM10RST_Pos) /*!< 0x00100000 */
+#define RCC_APB2RSTR_TIM10RST RCC_APB2RSTR_TIM10RST_Msk /*!< TIM10 Timer reset */
+#define RCC_APB2RSTR_TIM11RST_Pos (21U)
+#define RCC_APB2RSTR_TIM11RST_Msk (0x1U << RCC_APB2RSTR_TIM11RST_Pos) /*!< 0x00200000 */
+#define RCC_APB2RSTR_TIM11RST RCC_APB2RSTR_TIM11RST_Msk /*!< TIM11 Timer reset */
+
+/***************** Bit definition for RCC_APB1RSTR register *****************/
+#define RCC_APB1RSTR_TIM2RST_Pos (0U)
+#define RCC_APB1RSTR_TIM2RST_Msk (0x1U << RCC_APB1RSTR_TIM2RST_Pos) /*!< 0x00000001 */
+#define RCC_APB1RSTR_TIM2RST RCC_APB1RSTR_TIM2RST_Msk /*!< Timer 2 reset */
+#define RCC_APB1RSTR_TIM3RST_Pos (1U)
+#define RCC_APB1RSTR_TIM3RST_Msk (0x1U << RCC_APB1RSTR_TIM3RST_Pos) /*!< 0x00000002 */
+#define RCC_APB1RSTR_TIM3RST RCC_APB1RSTR_TIM3RST_Msk /*!< Timer 3 reset */
+#define RCC_APB1RSTR_WWDGRST_Pos (11U)
+#define RCC_APB1RSTR_WWDGRST_Msk (0x1U << RCC_APB1RSTR_WWDGRST_Pos) /*!< 0x00000800 */
+#define RCC_APB1RSTR_WWDGRST RCC_APB1RSTR_WWDGRST_Msk /*!< Window Watchdog reset */
+#define RCC_APB1RSTR_USART2RST_Pos (17U)
+#define RCC_APB1RSTR_USART2RST_Msk (0x1U << RCC_APB1RSTR_USART2RST_Pos) /*!< 0x00020000 */
+#define RCC_APB1RSTR_USART2RST RCC_APB1RSTR_USART2RST_Msk /*!< USART 2 reset */
+#define RCC_APB1RSTR_I2C1RST_Pos (21U)
+#define RCC_APB1RSTR_I2C1RST_Msk (0x1U << RCC_APB1RSTR_I2C1RST_Pos) /*!< 0x00200000 */
+#define RCC_APB1RSTR_I2C1RST RCC_APB1RSTR_I2C1RST_Msk /*!< I2C 1 reset */
+
+#define RCC_APB1RSTR_CAN1RST_Pos (25U)
+#define RCC_APB1RSTR_CAN1RST_Msk (0x1U << RCC_APB1RSTR_CAN1RST_Pos) /*!< 0x02000000 */
+#define RCC_APB1RSTR_CAN1RST RCC_APB1RSTR_CAN1RST_Msk /*!< CAN1 reset */
+
+#define RCC_APB1RSTR_BKPRST_Pos (27U)
+#define RCC_APB1RSTR_BKPRST_Msk (0x1U << RCC_APB1RSTR_BKPRST_Pos) /*!< 0x08000000 */
+#define RCC_APB1RSTR_BKPRST RCC_APB1RSTR_BKPRST_Msk /*!< Backup interface reset */
+#define RCC_APB1RSTR_PWRRST_Pos (28U)
+#define RCC_APB1RSTR_PWRRST_Msk (0x1U << RCC_APB1RSTR_PWRRST_Pos) /*!< 0x10000000 */
+#define RCC_APB1RSTR_PWRRST RCC_APB1RSTR_PWRRST_Msk /*!< Power interface reset */
+
+#define RCC_APB1RSTR_TIM4RST_Pos (2U)
+#define RCC_APB1RSTR_TIM4RST_Msk (0x1U << RCC_APB1RSTR_TIM4RST_Pos) /*!< 0x00000004 */
+#define RCC_APB1RSTR_TIM4RST RCC_APB1RSTR_TIM4RST_Msk /*!< Timer 4 reset */
+#define RCC_APB1RSTR_SPI2RST_Pos (14U)
+#define RCC_APB1RSTR_SPI2RST_Msk (0x1U << RCC_APB1RSTR_SPI2RST_Pos) /*!< 0x00004000 */
+#define RCC_APB1RSTR_SPI2RST RCC_APB1RSTR_SPI2RST_Msk /*!< SPI 2 reset */
+#define RCC_APB1RSTR_USART3RST_Pos (18U)
+#define RCC_APB1RSTR_USART3RST_Msk (0x1U << RCC_APB1RSTR_USART3RST_Pos) /*!< 0x00040000 */
+#define RCC_APB1RSTR_USART3RST RCC_APB1RSTR_USART3RST_Msk /*!< USART 3 reset */
+#define RCC_APB1RSTR_I2C2RST_Pos (22U)
+#define RCC_APB1RSTR_I2C2RST_Msk (0x1U << RCC_APB1RSTR_I2C2RST_Pos) /*!< 0x00400000 */
+#define RCC_APB1RSTR_I2C2RST RCC_APB1RSTR_I2C2RST_Msk /*!< I2C 2 reset */
+
+#define RCC_APB1RSTR_USBRST_Pos (23U)
+#define RCC_APB1RSTR_USBRST_Msk (0x1U << RCC_APB1RSTR_USBRST_Pos) /*!< 0x00800000 */
+#define RCC_APB1RSTR_USBRST RCC_APB1RSTR_USBRST_Msk /*!< USB Device reset */
+
+#define RCC_APB1RSTR_TIM5RST_Pos (3U)
+#define RCC_APB1RSTR_TIM5RST_Msk (0x1U << RCC_APB1RSTR_TIM5RST_Pos) /*!< 0x00000008 */
+#define RCC_APB1RSTR_TIM5RST RCC_APB1RSTR_TIM5RST_Msk /*!< Timer 5 reset */
+#define RCC_APB1RSTR_TIM6RST_Pos (4U)
+#define RCC_APB1RSTR_TIM6RST_Msk (0x1U << RCC_APB1RSTR_TIM6RST_Pos) /*!< 0x00000010 */
+#define RCC_APB1RSTR_TIM6RST RCC_APB1RSTR_TIM6RST_Msk /*!< Timer 6 reset */
+#define RCC_APB1RSTR_TIM7RST_Pos (5U)
+#define RCC_APB1RSTR_TIM7RST_Msk (0x1U << RCC_APB1RSTR_TIM7RST_Pos) /*!< 0x00000020 */
+#define RCC_APB1RSTR_TIM7RST RCC_APB1RSTR_TIM7RST_Msk /*!< Timer 7 reset */
+#define RCC_APB1RSTR_SPI3RST_Pos (15U)
+#define RCC_APB1RSTR_SPI3RST_Msk (0x1U << RCC_APB1RSTR_SPI3RST_Pos) /*!< 0x00008000 */
+#define RCC_APB1RSTR_SPI3RST RCC_APB1RSTR_SPI3RST_Msk /*!< SPI 3 reset */
+#define RCC_APB1RSTR_UART4RST_Pos (19U)
+#define RCC_APB1RSTR_UART4RST_Msk (0x1U << RCC_APB1RSTR_UART4RST_Pos) /*!< 0x00080000 */
+#define RCC_APB1RSTR_UART4RST RCC_APB1RSTR_UART4RST_Msk /*!< UART 4 reset */
+#define RCC_APB1RSTR_UART5RST_Pos (20U)
+#define RCC_APB1RSTR_UART5RST_Msk (0x1U << RCC_APB1RSTR_UART5RST_Pos) /*!< 0x00100000 */
+#define RCC_APB1RSTR_UART5RST RCC_APB1RSTR_UART5RST_Msk /*!< UART 5 reset */
+
+
+
+
+#define RCC_APB1RSTR_TIM12RST_Pos (6U)
+#define RCC_APB1RSTR_TIM12RST_Msk (0x1U << RCC_APB1RSTR_TIM12RST_Pos) /*!< 0x00000040 */
+#define RCC_APB1RSTR_TIM12RST RCC_APB1RSTR_TIM12RST_Msk /*!< TIM12 Timer reset */
+#define RCC_APB1RSTR_TIM13RST_Pos (7U)
+#define RCC_APB1RSTR_TIM13RST_Msk (0x1U << RCC_APB1RSTR_TIM13RST_Pos) /*!< 0x00000080 */
+#define RCC_APB1RSTR_TIM13RST RCC_APB1RSTR_TIM13RST_Msk /*!< TIM13 Timer reset */
+#define RCC_APB1RSTR_TIM14RST_Pos (8U)
+#define RCC_APB1RSTR_TIM14RST_Msk (0x1U << RCC_APB1RSTR_TIM14RST_Pos) /*!< 0x00000100 */
+#define RCC_APB1RSTR_TIM14RST RCC_APB1RSTR_TIM14RST_Msk /*!< TIM14 Timer reset */
+#define RCC_APB1RSTR_DACRST_Pos (29U)
+#define RCC_APB1RSTR_DACRST_Msk (0x1U << RCC_APB1RSTR_DACRST_Pos) /*!< 0x20000000 */
+#define RCC_APB1RSTR_DACRST RCC_APB1RSTR_DACRST_Msk /*!< DAC interface reset */
+
+/****************** Bit definition for RCC_AHBENR register ******************/
+#define RCC_AHBENR_DMA1EN_Pos (0U)
+#define RCC_AHBENR_DMA1EN_Msk (0x1U << RCC_AHBENR_DMA1EN_Pos) /*!< 0x00000001 */
+#define RCC_AHBENR_DMA1EN RCC_AHBENR_DMA1EN_Msk /*!< DMA1 clock enable */
+#define RCC_AHBENR_SRAMEN_Pos (2U)
+#define RCC_AHBENR_SRAMEN_Msk (0x1U << RCC_AHBENR_SRAMEN_Pos) /*!< 0x00000004 */
+#define RCC_AHBENR_SRAMEN RCC_AHBENR_SRAMEN_Msk /*!< SRAM interface clock enable */
+#define RCC_AHBENR_FLITFEN_Pos (4U)
+#define RCC_AHBENR_FLITFEN_Msk (0x1U << RCC_AHBENR_FLITFEN_Pos) /*!< 0x00000010 */
+#define RCC_AHBENR_FLITFEN RCC_AHBENR_FLITFEN_Msk /*!< FLITF clock enable */
+#define RCC_AHBENR_CRCEN_Pos (6U)
+#define RCC_AHBENR_CRCEN_Msk (0x1U << RCC_AHBENR_CRCEN_Pos) /*!< 0x00000040 */
+#define RCC_AHBENR_CRCEN RCC_AHBENR_CRCEN_Msk /*!< CRC clock enable */
+
+#define RCC_AHBENR_DMA2EN_Pos (1U)
+#define RCC_AHBENR_DMA2EN_Msk (0x1U << RCC_AHBENR_DMA2EN_Pos) /*!< 0x00000002 */
+#define RCC_AHBENR_DMA2EN RCC_AHBENR_DMA2EN_Msk /*!< DMA2 clock enable */
+
+#define RCC_AHBENR_FSMCEN_Pos (8U)
+#define RCC_AHBENR_FSMCEN_Msk (0x1U << RCC_AHBENR_FSMCEN_Pos) /*!< 0x00000100 */
+#define RCC_AHBENR_FSMCEN RCC_AHBENR_FSMCEN_Msk /*!< FSMC clock enable */
+#define RCC_AHBENR_SDIOEN_Pos (10U)
+#define RCC_AHBENR_SDIOEN_Msk (0x1U << RCC_AHBENR_SDIOEN_Pos) /*!< 0x00000400 */
+#define RCC_AHBENR_SDIOEN RCC_AHBENR_SDIOEN_Msk /*!< SDIO clock enable */
+
+
+/****************** Bit definition for RCC_APB2ENR register *****************/
+#define RCC_APB2ENR_AFIOEN_Pos (0U)
+#define RCC_APB2ENR_AFIOEN_Msk (0x1U << RCC_APB2ENR_AFIOEN_Pos) /*!< 0x00000001 */
+#define RCC_APB2ENR_AFIOEN RCC_APB2ENR_AFIOEN_Msk /*!< Alternate Function I/O clock enable */
+#define RCC_APB2ENR_IOPAEN_Pos (2U)
+#define RCC_APB2ENR_IOPAEN_Msk (0x1U << RCC_APB2ENR_IOPAEN_Pos) /*!< 0x00000004 */
+#define RCC_APB2ENR_IOPAEN RCC_APB2ENR_IOPAEN_Msk /*!< I/O port A clock enable */
+#define RCC_APB2ENR_IOPBEN_Pos (3U)
+#define RCC_APB2ENR_IOPBEN_Msk (0x1U << RCC_APB2ENR_IOPBEN_Pos) /*!< 0x00000008 */
+#define RCC_APB2ENR_IOPBEN RCC_APB2ENR_IOPBEN_Msk /*!< I/O port B clock enable */
+#define RCC_APB2ENR_IOPCEN_Pos (4U)
+#define RCC_APB2ENR_IOPCEN_Msk (0x1U << RCC_APB2ENR_IOPCEN_Pos) /*!< 0x00000010 */
+#define RCC_APB2ENR_IOPCEN RCC_APB2ENR_IOPCEN_Msk /*!< I/O port C clock enable */
+#define RCC_APB2ENR_IOPDEN_Pos (5U)
+#define RCC_APB2ENR_IOPDEN_Msk (0x1U << RCC_APB2ENR_IOPDEN_Pos) /*!< 0x00000020 */
+#define RCC_APB2ENR_IOPDEN RCC_APB2ENR_IOPDEN_Msk /*!< I/O port D clock enable */
+#define RCC_APB2ENR_ADC1EN_Pos (9U)
+#define RCC_APB2ENR_ADC1EN_Msk (0x1U << RCC_APB2ENR_ADC1EN_Pos) /*!< 0x00000200 */
+#define RCC_APB2ENR_ADC1EN RCC_APB2ENR_ADC1EN_Msk /*!< ADC 1 interface clock enable */
+
+#define RCC_APB2ENR_ADC2EN_Pos (10U)
+#define RCC_APB2ENR_ADC2EN_Msk (0x1U << RCC_APB2ENR_ADC2EN_Pos) /*!< 0x00000400 */
+#define RCC_APB2ENR_ADC2EN RCC_APB2ENR_ADC2EN_Msk /*!< ADC 2 interface clock enable */
+
+#define RCC_APB2ENR_TIM1EN_Pos (11U)
+#define RCC_APB2ENR_TIM1EN_Msk (0x1U << RCC_APB2ENR_TIM1EN_Pos) /*!< 0x00000800 */
+#define RCC_APB2ENR_TIM1EN RCC_APB2ENR_TIM1EN_Msk /*!< TIM1 Timer clock enable */
+#define RCC_APB2ENR_SPI1EN_Pos (12U)
+#define RCC_APB2ENR_SPI1EN_Msk (0x1U << RCC_APB2ENR_SPI1EN_Pos) /*!< 0x00001000 */
+#define RCC_APB2ENR_SPI1EN RCC_APB2ENR_SPI1EN_Msk /*!< SPI 1 clock enable */
+#define RCC_APB2ENR_USART1EN_Pos (14U)
+#define RCC_APB2ENR_USART1EN_Msk (0x1U << RCC_APB2ENR_USART1EN_Pos) /*!< 0x00004000 */
+#define RCC_APB2ENR_USART1EN RCC_APB2ENR_USART1EN_Msk /*!< USART1 clock enable */
+
+
+#define RCC_APB2ENR_IOPEEN_Pos (6U)
+#define RCC_APB2ENR_IOPEEN_Msk (0x1U << RCC_APB2ENR_IOPEEN_Pos) /*!< 0x00000040 */
+#define RCC_APB2ENR_IOPEEN RCC_APB2ENR_IOPEEN_Msk /*!< I/O port E clock enable */
+
+#define RCC_APB2ENR_IOPFEN_Pos (7U)
+#define RCC_APB2ENR_IOPFEN_Msk (0x1U << RCC_APB2ENR_IOPFEN_Pos) /*!< 0x00000080 */
+#define RCC_APB2ENR_IOPFEN RCC_APB2ENR_IOPFEN_Msk /*!< I/O port F clock enable */
+#define RCC_APB2ENR_IOPGEN_Pos (8U)
+#define RCC_APB2ENR_IOPGEN_Msk (0x1U << RCC_APB2ENR_IOPGEN_Pos) /*!< 0x00000100 */
+#define RCC_APB2ENR_IOPGEN RCC_APB2ENR_IOPGEN_Msk /*!< I/O port G clock enable */
+#define RCC_APB2ENR_TIM8EN_Pos (13U)
+#define RCC_APB2ENR_TIM8EN_Msk (0x1U << RCC_APB2ENR_TIM8EN_Pos) /*!< 0x00002000 */
+#define RCC_APB2ENR_TIM8EN RCC_APB2ENR_TIM8EN_Msk /*!< TIM8 Timer clock enable */
+#define RCC_APB2ENR_ADC3EN_Pos (15U)
+#define RCC_APB2ENR_ADC3EN_Msk (0x1U << RCC_APB2ENR_ADC3EN_Pos) /*!< 0x00008000 */
+#define RCC_APB2ENR_ADC3EN RCC_APB2ENR_ADC3EN_Msk /*!< DMA1 clock enable */
+
+
+#define RCC_APB2ENR_TIM9EN_Pos (19U)
+#define RCC_APB2ENR_TIM9EN_Msk (0x1U << RCC_APB2ENR_TIM9EN_Pos) /*!< 0x00080000 */
+#define RCC_APB2ENR_TIM9EN RCC_APB2ENR_TIM9EN_Msk /*!< TIM9 Timer clock enable */
+#define RCC_APB2ENR_TIM10EN_Pos (20U)
+#define RCC_APB2ENR_TIM10EN_Msk (0x1U << RCC_APB2ENR_TIM10EN_Pos) /*!< 0x00100000 */
+#define RCC_APB2ENR_TIM10EN RCC_APB2ENR_TIM10EN_Msk /*!< TIM10 Timer clock enable */
+#define RCC_APB2ENR_TIM11EN_Pos (21U)
+#define RCC_APB2ENR_TIM11EN_Msk (0x1U << RCC_APB2ENR_TIM11EN_Pos) /*!< 0x00200000 */
+#define RCC_APB2ENR_TIM11EN RCC_APB2ENR_TIM11EN_Msk /*!< TIM11 Timer clock enable */
+
+/***************** Bit definition for RCC_APB1ENR register ******************/
+#define RCC_APB1ENR_TIM2EN_Pos (0U)
+#define RCC_APB1ENR_TIM2EN_Msk (0x1U << RCC_APB1ENR_TIM2EN_Pos) /*!< 0x00000001 */
+#define RCC_APB1ENR_TIM2EN RCC_APB1ENR_TIM2EN_Msk /*!< Timer 2 clock enabled*/
+#define RCC_APB1ENR_TIM3EN_Pos (1U)
+#define RCC_APB1ENR_TIM3EN_Msk (0x1U << RCC_APB1ENR_TIM3EN_Pos) /*!< 0x00000002 */
+#define RCC_APB1ENR_TIM3EN RCC_APB1ENR_TIM3EN_Msk /*!< Timer 3 clock enable */
+#define RCC_APB1ENR_WWDGEN_Pos (11U)
+#define RCC_APB1ENR_WWDGEN_Msk (0x1U << RCC_APB1ENR_WWDGEN_Pos) /*!< 0x00000800 */
+#define RCC_APB1ENR_WWDGEN RCC_APB1ENR_WWDGEN_Msk /*!< Window Watchdog clock enable */
+#define RCC_APB1ENR_USART2EN_Pos (17U)
+#define RCC_APB1ENR_USART2EN_Msk (0x1U << RCC_APB1ENR_USART2EN_Pos) /*!< 0x00020000 */
+#define RCC_APB1ENR_USART2EN RCC_APB1ENR_USART2EN_Msk /*!< USART 2 clock enable */
+#define RCC_APB1ENR_I2C1EN_Pos (21U)
+#define RCC_APB1ENR_I2C1EN_Msk (0x1U << RCC_APB1ENR_I2C1EN_Pos) /*!< 0x00200000 */
+#define RCC_APB1ENR_I2C1EN RCC_APB1ENR_I2C1EN_Msk /*!< I2C 1 clock enable */
+
+#define RCC_APB1ENR_CAN1EN_Pos (25U)
+#define RCC_APB1ENR_CAN1EN_Msk (0x1U << RCC_APB1ENR_CAN1EN_Pos) /*!< 0x02000000 */
+#define RCC_APB1ENR_CAN1EN RCC_APB1ENR_CAN1EN_Msk /*!< CAN1 clock enable */
+
+#define RCC_APB1ENR_BKPEN_Pos (27U)
+#define RCC_APB1ENR_BKPEN_Msk (0x1U << RCC_APB1ENR_BKPEN_Pos) /*!< 0x08000000 */
+#define RCC_APB1ENR_BKPEN RCC_APB1ENR_BKPEN_Msk /*!< Backup interface clock enable */
+#define RCC_APB1ENR_PWREN_Pos (28U)
+#define RCC_APB1ENR_PWREN_Msk (0x1U << RCC_APB1ENR_PWREN_Pos) /*!< 0x10000000 */
+#define RCC_APB1ENR_PWREN RCC_APB1ENR_PWREN_Msk /*!< Power interface clock enable */
+
+#define RCC_APB1ENR_TIM4EN_Pos (2U)
+#define RCC_APB1ENR_TIM4EN_Msk (0x1U << RCC_APB1ENR_TIM4EN_Pos) /*!< 0x00000004 */
+#define RCC_APB1ENR_TIM4EN RCC_APB1ENR_TIM4EN_Msk /*!< Timer 4 clock enable */
+#define RCC_APB1ENR_SPI2EN_Pos (14U)
+#define RCC_APB1ENR_SPI2EN_Msk (0x1U << RCC_APB1ENR_SPI2EN_Pos) /*!< 0x00004000 */
+#define RCC_APB1ENR_SPI2EN RCC_APB1ENR_SPI2EN_Msk /*!< SPI 2 clock enable */
+#define RCC_APB1ENR_USART3EN_Pos (18U)
+#define RCC_APB1ENR_USART3EN_Msk (0x1U << RCC_APB1ENR_USART3EN_Pos) /*!< 0x00040000 */
+#define RCC_APB1ENR_USART3EN RCC_APB1ENR_USART3EN_Msk /*!< USART 3 clock enable */
+#define RCC_APB1ENR_I2C2EN_Pos (22U)
+#define RCC_APB1ENR_I2C2EN_Msk (0x1U << RCC_APB1ENR_I2C2EN_Pos) /*!< 0x00400000 */
+#define RCC_APB1ENR_I2C2EN RCC_APB1ENR_I2C2EN_Msk /*!< I2C 2 clock enable */
+
+#define RCC_APB1ENR_USBEN_Pos (23U)
+#define RCC_APB1ENR_USBEN_Msk (0x1U << RCC_APB1ENR_USBEN_Pos) /*!< 0x00800000 */
+#define RCC_APB1ENR_USBEN RCC_APB1ENR_USBEN_Msk /*!< USB Device clock enable */
+
+#define RCC_APB1ENR_TIM5EN_Pos (3U)
+#define RCC_APB1ENR_TIM5EN_Msk (0x1U << RCC_APB1ENR_TIM5EN_Pos) /*!< 0x00000008 */
+#define RCC_APB1ENR_TIM5EN RCC_APB1ENR_TIM5EN_Msk /*!< Timer 5 clock enable */
+#define RCC_APB1ENR_TIM6EN_Pos (4U)
+#define RCC_APB1ENR_TIM6EN_Msk (0x1U << RCC_APB1ENR_TIM6EN_Pos) /*!< 0x00000010 */
+#define RCC_APB1ENR_TIM6EN RCC_APB1ENR_TIM6EN_Msk /*!< Timer 6 clock enable */
+#define RCC_APB1ENR_TIM7EN_Pos (5U)
+#define RCC_APB1ENR_TIM7EN_Msk (0x1U << RCC_APB1ENR_TIM7EN_Pos) /*!< 0x00000020 */
+#define RCC_APB1ENR_TIM7EN RCC_APB1ENR_TIM7EN_Msk /*!< Timer 7 clock enable */
+#define RCC_APB1ENR_SPI3EN_Pos (15U)
+#define RCC_APB1ENR_SPI3EN_Msk (0x1U << RCC_APB1ENR_SPI3EN_Pos) /*!< 0x00008000 */
+#define RCC_APB1ENR_SPI3EN RCC_APB1ENR_SPI3EN_Msk /*!< SPI 3 clock enable */
+#define RCC_APB1ENR_UART4EN_Pos (19U)
+#define RCC_APB1ENR_UART4EN_Msk (0x1U << RCC_APB1ENR_UART4EN_Pos) /*!< 0x00080000 */
+#define RCC_APB1ENR_UART4EN RCC_APB1ENR_UART4EN_Msk /*!< UART 4 clock enable */
+#define RCC_APB1ENR_UART5EN_Pos (20U)
+#define RCC_APB1ENR_UART5EN_Msk (0x1U << RCC_APB1ENR_UART5EN_Pos) /*!< 0x00100000 */
+#define RCC_APB1ENR_UART5EN RCC_APB1ENR_UART5EN_Msk /*!< UART 5 clock enable */
+
+
+
+
+#define RCC_APB1ENR_TIM12EN_Pos (6U)
+#define RCC_APB1ENR_TIM12EN_Msk (0x1U << RCC_APB1ENR_TIM12EN_Pos) /*!< 0x00000040 */
+#define RCC_APB1ENR_TIM12EN RCC_APB1ENR_TIM12EN_Msk /*!< TIM12 Timer clock enable */
+#define RCC_APB1ENR_TIM13EN_Pos (7U)
+#define RCC_APB1ENR_TIM13EN_Msk (0x1U << RCC_APB1ENR_TIM13EN_Pos) /*!< 0x00000080 */
+#define RCC_APB1ENR_TIM13EN RCC_APB1ENR_TIM13EN_Msk /*!< TIM13 Timer clock enable */
+#define RCC_APB1ENR_TIM14EN_Pos (8U)
+#define RCC_APB1ENR_TIM14EN_Msk (0x1U << RCC_APB1ENR_TIM14EN_Pos) /*!< 0x00000100 */
+#define RCC_APB1ENR_TIM14EN RCC_APB1ENR_TIM14EN_Msk /*!< TIM14 Timer clock enable */
+#define RCC_APB1ENR_DACEN_Pos (29U)
+#define RCC_APB1ENR_DACEN_Msk (0x1U << RCC_APB1ENR_DACEN_Pos) /*!< 0x20000000 */
+#define RCC_APB1ENR_DACEN RCC_APB1ENR_DACEN_Msk /*!< DAC interface clock enable */
+
+/******************* Bit definition for RCC_BDCR register *******************/
+#define RCC_BDCR_LSEON_Pos (0U)
+#define RCC_BDCR_LSEON_Msk (0x1U << RCC_BDCR_LSEON_Pos) /*!< 0x00000001 */
+#define RCC_BDCR_LSEON RCC_BDCR_LSEON_Msk /*!< External Low Speed oscillator enable */
+#define RCC_BDCR_LSERDY_Pos (1U)
+#define RCC_BDCR_LSERDY_Msk (0x1U << RCC_BDCR_LSERDY_Pos) /*!< 0x00000002 */
+#define RCC_BDCR_LSERDY RCC_BDCR_LSERDY_Msk /*!< External Low Speed oscillator Ready */
+#define RCC_BDCR_LSEBYP_Pos (2U)
+#define RCC_BDCR_LSEBYP_Msk (0x1U << RCC_BDCR_LSEBYP_Pos) /*!< 0x00000004 */
+#define RCC_BDCR_LSEBYP RCC_BDCR_LSEBYP_Msk /*!< External Low Speed oscillator Bypass */
+
+#define RCC_BDCR_RTCSEL_Pos (8U)
+#define RCC_BDCR_RTCSEL_Msk (0x3U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000300 */
+#define RCC_BDCR_RTCSEL RCC_BDCR_RTCSEL_Msk /*!< RTCSEL[1:0] bits (RTC clock source selection) */
+#define RCC_BDCR_RTCSEL_0 (0x1U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000100 */
+#define RCC_BDCR_RTCSEL_1 (0x2U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000200 */
+
+/*!< RTC congiguration */
+#define RCC_BDCR_RTCSEL_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */
+#define RCC_BDCR_RTCSEL_LSE ((uint32_t)0x00000100) /*!< LSE oscillator clock used as RTC clock */
+#define RCC_BDCR_RTCSEL_LSI ((uint32_t)0x00000200) /*!< LSI oscillator clock used as RTC clock */
+#define RCC_BDCR_RTCSEL_HSE ((uint32_t)0x00000300) /*!< HSE oscillator clock divided by 128 used as RTC clock */
+
+#define RCC_BDCR_RTCEN_Pos (15U)
+#define RCC_BDCR_RTCEN_Msk (0x1U << RCC_BDCR_RTCEN_Pos) /*!< 0x00008000 */
+#define RCC_BDCR_RTCEN RCC_BDCR_RTCEN_Msk /*!< RTC clock enable */
+#define RCC_BDCR_BDRST_Pos (16U)
+#define RCC_BDCR_BDRST_Msk (0x1U << RCC_BDCR_BDRST_Pos) /*!< 0x00010000 */
+#define RCC_BDCR_BDRST RCC_BDCR_BDRST_Msk /*!< Backup domain software reset */
+
+/******************* Bit definition for RCC_CSR register ********************/
+#define RCC_CSR_LSION_Pos (0U)
+#define RCC_CSR_LSION_Msk (0x1U << RCC_CSR_LSION_Pos) /*!< 0x00000001 */
+#define RCC_CSR_LSION RCC_CSR_LSION_Msk /*!< Internal Low Speed oscillator enable */
+#define RCC_CSR_LSIRDY_Pos (1U)
+#define RCC_CSR_LSIRDY_Msk (0x1U << RCC_CSR_LSIRDY_Pos) /*!< 0x00000002 */
+#define RCC_CSR_LSIRDY RCC_CSR_LSIRDY_Msk /*!< Internal Low Speed oscillator Ready */
+#define RCC_CSR_RMVF_Pos (24U)
+#define RCC_CSR_RMVF_Msk (0x1U << RCC_CSR_RMVF_Pos) /*!< 0x01000000 */
+#define RCC_CSR_RMVF RCC_CSR_RMVF_Msk /*!< Remove reset flag */
+#define RCC_CSR_PINRSTF_Pos (26U)
+#define RCC_CSR_PINRSTF_Msk (0x1U << RCC_CSR_PINRSTF_Pos) /*!< 0x04000000 */
+#define RCC_CSR_PINRSTF RCC_CSR_PINRSTF_Msk /*!< PIN reset flag */
+#define RCC_CSR_PORRSTF_Pos (27U)
+#define RCC_CSR_PORRSTF_Msk (0x1U << RCC_CSR_PORRSTF_Pos) /*!< 0x08000000 */
+#define RCC_CSR_PORRSTF RCC_CSR_PORRSTF_Msk /*!< POR/PDR reset flag */
+#define RCC_CSR_SFTRSTF_Pos (28U)
+#define RCC_CSR_SFTRSTF_Msk (0x1U << RCC_CSR_SFTRSTF_Pos) /*!< 0x10000000 */
+#define RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF_Msk /*!< Software Reset flag */
+#define RCC_CSR_IWDGRSTF_Pos (29U)
+#define RCC_CSR_IWDGRSTF_Msk (0x1U << RCC_CSR_IWDGRSTF_Pos) /*!< 0x20000000 */
+#define RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF_Msk /*!< Independent Watchdog reset flag */
+#define RCC_CSR_WWDGRSTF_Pos (30U)
+#define RCC_CSR_WWDGRSTF_Msk (0x1U << RCC_CSR_WWDGRSTF_Pos) /*!< 0x40000000 */
+#define RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF_Msk /*!< Window watchdog reset flag */
+#define RCC_CSR_LPWRRSTF_Pos (31U)
+#define RCC_CSR_LPWRRSTF_Msk (0x1U << RCC_CSR_LPWRRSTF_Pos) /*!< 0x80000000 */
+#define RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF_Msk /*!< Low-Power reset flag */
+
+
+
+/******************************************************************************/
+/* */
+/* General Purpose and Alternate Function I/O */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for GPIO_CRL register *******************/
+#define GPIO_CRL_MODE_Pos (0U)
+#define GPIO_CRL_MODE_Msk (0x33333333U << GPIO_CRL_MODE_Pos) /*!< 0x33333333 */
+#define GPIO_CRL_MODE GPIO_CRL_MODE_Msk /*!< Port x mode bits */
+
+#define GPIO_CRL_MODE0_Pos (0U)
+#define GPIO_CRL_MODE0_Msk (0x3U << GPIO_CRL_MODE0_Pos) /*!< 0x00000003 */
+#define GPIO_CRL_MODE0 GPIO_CRL_MODE0_Msk /*!< MODE0[1:0] bits (Port x mode bits, pin 0) */
+#define GPIO_CRL_MODE0_0 (0x1U << GPIO_CRL_MODE0_Pos) /*!< 0x00000001 */
+#define GPIO_CRL_MODE0_1 (0x2U << GPIO_CRL_MODE0_Pos) /*!< 0x00000002 */
+
+#define GPIO_CRL_MODE1_Pos (4U)
+#define GPIO_CRL_MODE1_Msk (0x3U << GPIO_CRL_MODE1_Pos) /*!< 0x00000030 */
+#define GPIO_CRL_MODE1 GPIO_CRL_MODE1_Msk /*!< MODE1[1:0] bits (Port x mode bits, pin 1) */
+#define GPIO_CRL_MODE1_0 (0x1U << GPIO_CRL_MODE1_Pos) /*!< 0x00000010 */
+#define GPIO_CRL_MODE1_1 (0x2U << GPIO_CRL_MODE1_Pos) /*!< 0x00000020 */
+
+#define GPIO_CRL_MODE2_Pos (8U)
+#define GPIO_CRL_MODE2_Msk (0x3U << GPIO_CRL_MODE2_Pos) /*!< 0x00000300 */
+#define GPIO_CRL_MODE2 GPIO_CRL_MODE2_Msk /*!< MODE2[1:0] bits (Port x mode bits, pin 2) */
+#define GPIO_CRL_MODE2_0 (0x1U << GPIO_CRL_MODE2_Pos) /*!< 0x00000100 */
+#define GPIO_CRL_MODE2_1 (0x2U << GPIO_CRL_MODE2_Pos) /*!< 0x00000200 */
+
+#define GPIO_CRL_MODE3_Pos (12U)
+#define GPIO_CRL_MODE3_Msk (0x3U << GPIO_CRL_MODE3_Pos) /*!< 0x00003000 */
+#define GPIO_CRL_MODE3 GPIO_CRL_MODE3_Msk /*!< MODE3[1:0] bits (Port x mode bits, pin 3) */
+#define GPIO_CRL_MODE3_0 (0x1U << GPIO_CRL_MODE3_Pos) /*!< 0x00001000 */
+#define GPIO_CRL_MODE3_1 (0x2U << GPIO_CRL_MODE3_Pos) /*!< 0x00002000 */
+
+#define GPIO_CRL_MODE4_Pos (16U)
+#define GPIO_CRL_MODE4_Msk (0x3U << GPIO_CRL_MODE4_Pos) /*!< 0x00030000 */
+#define GPIO_CRL_MODE4 GPIO_CRL_MODE4_Msk /*!< MODE4[1:0] bits (Port x mode bits, pin 4) */
+#define GPIO_CRL_MODE4_0 (0x1U << GPIO_CRL_MODE4_Pos) /*!< 0x00010000 */
+#define GPIO_CRL_MODE4_1 (0x2U << GPIO_CRL_MODE4_Pos) /*!< 0x00020000 */
+
+#define GPIO_CRL_MODE5_Pos (20U)
+#define GPIO_CRL_MODE5_Msk (0x3U << GPIO_CRL_MODE5_Pos) /*!< 0x00300000 */
+#define GPIO_CRL_MODE5 GPIO_CRL_MODE5_Msk /*!< MODE5[1:0] bits (Port x mode bits, pin 5) */
+#define GPIO_CRL_MODE5_0 (0x1U << GPIO_CRL_MODE5_Pos) /*!< 0x00100000 */
+#define GPIO_CRL_MODE5_1 (0x2U << GPIO_CRL_MODE5_Pos) /*!< 0x00200000 */
+
+#define GPIO_CRL_MODE6_Pos (24U)
+#define GPIO_CRL_MODE6_Msk (0x3U << GPIO_CRL_MODE6_Pos) /*!< 0x03000000 */
+#define GPIO_CRL_MODE6 GPIO_CRL_MODE6_Msk /*!< MODE6[1:0] bits (Port x mode bits, pin 6) */
+#define GPIO_CRL_MODE6_0 (0x1U << GPIO_CRL_MODE6_Pos) /*!< 0x01000000 */
+#define GPIO_CRL_MODE6_1 (0x2U << GPIO_CRL_MODE6_Pos) /*!< 0x02000000 */
+
+#define GPIO_CRL_MODE7_Pos (28U)
+#define GPIO_CRL_MODE7_Msk (0x3U << GPIO_CRL_MODE7_Pos) /*!< 0x30000000 */
+#define GPIO_CRL_MODE7 GPIO_CRL_MODE7_Msk /*!< MODE7[1:0] bits (Port x mode bits, pin 7) */
+#define GPIO_CRL_MODE7_0 (0x1U << GPIO_CRL_MODE7_Pos) /*!< 0x10000000 */
+#define GPIO_CRL_MODE7_1 (0x2U << GPIO_CRL_MODE7_Pos) /*!< 0x20000000 */
+
+#define GPIO_CRL_CNF_Pos (2U)
+#define GPIO_CRL_CNF_Msk (0x33333333U << GPIO_CRL_CNF_Pos) /*!< 0xCCCCCCCC */
+#define GPIO_CRL_CNF GPIO_CRL_CNF_Msk /*!< Port x configuration bits */
+
+#define GPIO_CRL_CNF0_Pos (2U)
+#define GPIO_CRL_CNF0_Msk (0x3U << GPIO_CRL_CNF0_Pos) /*!< 0x0000000C */
+#define GPIO_CRL_CNF0 GPIO_CRL_CNF0_Msk /*!< CNF0[1:0] bits (Port x configuration bits, pin 0) */
+#define GPIO_CRL_CNF0_0 (0x1U << GPIO_CRL_CNF0_Pos) /*!< 0x00000004 */
+#define GPIO_CRL_CNF0_1 (0x2U << GPIO_CRL_CNF0_Pos) /*!< 0x00000008 */
+
+#define GPIO_CRL_CNF1_Pos (6U)
+#define GPIO_CRL_CNF1_Msk (0x3U << GPIO_CRL_CNF1_Pos) /*!< 0x000000C0 */
+#define GPIO_CRL_CNF1 GPIO_CRL_CNF1_Msk /*!< CNF1[1:0] bits (Port x configuration bits, pin 1) */
+#define GPIO_CRL_CNF1_0 (0x1U << GPIO_CRL_CNF1_Pos) /*!< 0x00000040 */
+#define GPIO_CRL_CNF1_1 (0x2U << GPIO_CRL_CNF1_Pos) /*!< 0x00000080 */
+
+#define GPIO_CRL_CNF2_Pos (10U)
+#define GPIO_CRL_CNF2_Msk (0x3U << GPIO_CRL_CNF2_Pos) /*!< 0x00000C00 */
+#define GPIO_CRL_CNF2 GPIO_CRL_CNF2_Msk /*!< CNF2[1:0] bits (Port x configuration bits, pin 2) */
+#define GPIO_CRL_CNF2_0 (0x1U << GPIO_CRL_CNF2_Pos) /*!< 0x00000400 */
+#define GPIO_CRL_CNF2_1 (0x2U << GPIO_CRL_CNF2_Pos) /*!< 0x00000800 */
+
+#define GPIO_CRL_CNF3_Pos (14U)
+#define GPIO_CRL_CNF3_Msk (0x3U << GPIO_CRL_CNF3_Pos) /*!< 0x0000C000 */
+#define GPIO_CRL_CNF3 GPIO_CRL_CNF3_Msk /*!< CNF3[1:0] bits (Port x configuration bits, pin 3) */
+#define GPIO_CRL_CNF3_0 (0x1U << GPIO_CRL_CNF3_Pos) /*!< 0x00004000 */
+#define GPIO_CRL_CNF3_1 (0x2U << GPIO_CRL_CNF3_Pos) /*!< 0x00008000 */
+
+#define GPIO_CRL_CNF4_Pos (18U)
+#define GPIO_CRL_CNF4_Msk (0x3U << GPIO_CRL_CNF4_Pos) /*!< 0x000C0000 */
+#define GPIO_CRL_CNF4 GPIO_CRL_CNF4_Msk /*!< CNF4[1:0] bits (Port x configuration bits, pin 4) */
+#define GPIO_CRL_CNF4_0 (0x1U << GPIO_CRL_CNF4_Pos) /*!< 0x00040000 */
+#define GPIO_CRL_CNF4_1 (0x2U << GPIO_CRL_CNF4_Pos) /*!< 0x00080000 */
+
+#define GPIO_CRL_CNF5_Pos (22U)
+#define GPIO_CRL_CNF5_Msk (0x3U << GPIO_CRL_CNF5_Pos) /*!< 0x00C00000 */
+#define GPIO_CRL_CNF5 GPIO_CRL_CNF5_Msk /*!< CNF5[1:0] bits (Port x configuration bits, pin 5) */
+#define GPIO_CRL_CNF5_0 (0x1U << GPIO_CRL_CNF5_Pos) /*!< 0x00400000 */
+#define GPIO_CRL_CNF5_1 (0x2U << GPIO_CRL_CNF5_Pos) /*!< 0x00800000 */
+
+#define GPIO_CRL_CNF6_Pos (26U)
+#define GPIO_CRL_CNF6_Msk (0x3U << GPIO_CRL_CNF6_Pos) /*!< 0x0C000000 */
+#define GPIO_CRL_CNF6 GPIO_CRL_CNF6_Msk /*!< CNF6[1:0] bits (Port x configuration bits, pin 6) */
+#define GPIO_CRL_CNF6_0 (0x1U << GPIO_CRL_CNF6_Pos) /*!< 0x04000000 */
+#define GPIO_CRL_CNF6_1 (0x2U << GPIO_CRL_CNF6_Pos) /*!< 0x08000000 */
+
+#define GPIO_CRL_CNF7_Pos (30U)
+#define GPIO_CRL_CNF7_Msk (0x3U << GPIO_CRL_CNF7_Pos) /*!< 0xC0000000 */
+#define GPIO_CRL_CNF7 GPIO_CRL_CNF7_Msk /*!< CNF7[1:0] bits (Port x configuration bits, pin 7) */
+#define GPIO_CRL_CNF7_0 (0x1U << GPIO_CRL_CNF7_Pos) /*!< 0x40000000 */
+#define GPIO_CRL_CNF7_1 (0x2U << GPIO_CRL_CNF7_Pos) /*!< 0x80000000 */
+
+/******************* Bit definition for GPIO_CRH register *******************/
+#define GPIO_CRH_MODE_Pos (0U)
+#define GPIO_CRH_MODE_Msk (0x33333333U << GPIO_CRH_MODE_Pos) /*!< 0x33333333 */
+#define GPIO_CRH_MODE GPIO_CRH_MODE_Msk /*!< Port x mode bits */
+
+#define GPIO_CRH_MODE8_Pos (0U)
+#define GPIO_CRH_MODE8_Msk (0x3U << GPIO_CRH_MODE8_Pos) /*!< 0x00000003 */
+#define GPIO_CRH_MODE8 GPIO_CRH_MODE8_Msk /*!< MODE8[1:0] bits (Port x mode bits, pin 8) */
+#define GPIO_CRH_MODE8_0 (0x1U << GPIO_CRH_MODE8_Pos) /*!< 0x00000001 */
+#define GPIO_CRH_MODE8_1 (0x2U << GPIO_CRH_MODE8_Pos) /*!< 0x00000002 */
+
+#define GPIO_CRH_MODE9_Pos (4U)
+#define GPIO_CRH_MODE9_Msk (0x3U << GPIO_CRH_MODE9_Pos) /*!< 0x00000030 */
+#define GPIO_CRH_MODE9 GPIO_CRH_MODE9_Msk /*!< MODE9[1:0] bits (Port x mode bits, pin 9) */
+#define GPIO_CRH_MODE9_0 (0x1U << GPIO_CRH_MODE9_Pos) /*!< 0x00000010 */
+#define GPIO_CRH_MODE9_1 (0x2U << GPIO_CRH_MODE9_Pos) /*!< 0x00000020 */
+
+#define GPIO_CRH_MODE10_Pos (8U)
+#define GPIO_CRH_MODE10_Msk (0x3U << GPIO_CRH_MODE10_Pos) /*!< 0x00000300 */
+#define GPIO_CRH_MODE10 GPIO_CRH_MODE10_Msk /*!< MODE10[1:0] bits (Port x mode bits, pin 10) */
+#define GPIO_CRH_MODE10_0 (0x1U << GPIO_CRH_MODE10_Pos) /*!< 0x00000100 */
+#define GPIO_CRH_MODE10_1 (0x2U << GPIO_CRH_MODE10_Pos) /*!< 0x00000200 */
+
+#define GPIO_CRH_MODE11_Pos (12U)
+#define GPIO_CRH_MODE11_Msk (0x3U << GPIO_CRH_MODE11_Pos) /*!< 0x00003000 */
+#define GPIO_CRH_MODE11 GPIO_CRH_MODE11_Msk /*!< MODE11[1:0] bits (Port x mode bits, pin 11) */
+#define GPIO_CRH_MODE11_0 (0x1U << GPIO_CRH_MODE11_Pos) /*!< 0x00001000 */
+#define GPIO_CRH_MODE11_1 (0x2U << GPIO_CRH_MODE11_Pos) /*!< 0x00002000 */
+
+#define GPIO_CRH_MODE12_Pos (16U)
+#define GPIO_CRH_MODE12_Msk (0x3U << GPIO_CRH_MODE12_Pos) /*!< 0x00030000 */
+#define GPIO_CRH_MODE12 GPIO_CRH_MODE12_Msk /*!< MODE12[1:0] bits (Port x mode bits, pin 12) */
+#define GPIO_CRH_MODE12_0 (0x1U << GPIO_CRH_MODE12_Pos) /*!< 0x00010000 */
+#define GPIO_CRH_MODE12_1 (0x2U << GPIO_CRH_MODE12_Pos) /*!< 0x00020000 */
+
+#define GPIO_CRH_MODE13_Pos (20U)
+#define GPIO_CRH_MODE13_Msk (0x3U << GPIO_CRH_MODE13_Pos) /*!< 0x00300000 */
+#define GPIO_CRH_MODE13 GPIO_CRH_MODE13_Msk /*!< MODE13[1:0] bits (Port x mode bits, pin 13) */
+#define GPIO_CRH_MODE13_0 (0x1U << GPIO_CRH_MODE13_Pos) /*!< 0x00100000 */
+#define GPIO_CRH_MODE13_1 (0x2U << GPIO_CRH_MODE13_Pos) /*!< 0x00200000 */
+
+#define GPIO_CRH_MODE14_Pos (24U)
+#define GPIO_CRH_MODE14_Msk (0x3U << GPIO_CRH_MODE14_Pos) /*!< 0x03000000 */
+#define GPIO_CRH_MODE14 GPIO_CRH_MODE14_Msk /*!< MODE14[1:0] bits (Port x mode bits, pin 14) */
+#define GPIO_CRH_MODE14_0 (0x1U << GPIO_CRH_MODE14_Pos) /*!< 0x01000000 */
+#define GPIO_CRH_MODE14_1 (0x2U << GPIO_CRH_MODE14_Pos) /*!< 0x02000000 */
+
+#define GPIO_CRH_MODE15_Pos (28U)
+#define GPIO_CRH_MODE15_Msk (0x3U << GPIO_CRH_MODE15_Pos) /*!< 0x30000000 */
+#define GPIO_CRH_MODE15 GPIO_CRH_MODE15_Msk /*!< MODE15[1:0] bits (Port x mode bits, pin 15) */
+#define GPIO_CRH_MODE15_0 (0x1U << GPIO_CRH_MODE15_Pos) /*!< 0x10000000 */
+#define GPIO_CRH_MODE15_1 (0x2U << GPIO_CRH_MODE15_Pos) /*!< 0x20000000 */
+
+#define GPIO_CRH_CNF_Pos (2U)
+#define GPIO_CRH_CNF_Msk (0x33333333U << GPIO_CRH_CNF_Pos) /*!< 0xCCCCCCCC */
+#define GPIO_CRH_CNF GPIO_CRH_CNF_Msk /*!< Port x configuration bits */
+
+#define GPIO_CRH_CNF8_Pos (2U)
+#define GPIO_CRH_CNF8_Msk (0x3U << GPIO_CRH_CNF8_Pos) /*!< 0x0000000C */
+#define GPIO_CRH_CNF8 GPIO_CRH_CNF8_Msk /*!< CNF8[1:0] bits (Port x configuration bits, pin 8) */
+#define GPIO_CRH_CNF8_0 (0x1U << GPIO_CRH_CNF8_Pos) /*!< 0x00000004 */
+#define GPIO_CRH_CNF8_1 (0x2U << GPIO_CRH_CNF8_Pos) /*!< 0x00000008 */
+
+#define GPIO_CRH_CNF9_Pos (6U)
+#define GPIO_CRH_CNF9_Msk (0x3U << GPIO_CRH_CNF9_Pos) /*!< 0x000000C0 */
+#define GPIO_CRH_CNF9 GPIO_CRH_CNF9_Msk /*!< CNF9[1:0] bits (Port x configuration bits, pin 9) */
+#define GPIO_CRH_CNF9_0 (0x1U << GPIO_CRH_CNF9_Pos) /*!< 0x00000040 */
+#define GPIO_CRH_CNF9_1 (0x2U << GPIO_CRH_CNF9_Pos) /*!< 0x00000080 */
+
+#define GPIO_CRH_CNF10_Pos (10U)
+#define GPIO_CRH_CNF10_Msk (0x3U << GPIO_CRH_CNF10_Pos) /*!< 0x00000C00 */
+#define GPIO_CRH_CNF10 GPIO_CRH_CNF10_Msk /*!< CNF10[1:0] bits (Port x configuration bits, pin 10) */
+#define GPIO_CRH_CNF10_0 (0x1U << GPIO_CRH_CNF10_Pos) /*!< 0x00000400 */
+#define GPIO_CRH_CNF10_1 (0x2U << GPIO_CRH_CNF10_Pos) /*!< 0x00000800 */
+
+#define GPIO_CRH_CNF11_Pos (14U)
+#define GPIO_CRH_CNF11_Msk (0x3U << GPIO_CRH_CNF11_Pos) /*!< 0x0000C000 */
+#define GPIO_CRH_CNF11 GPIO_CRH_CNF11_Msk /*!< CNF11[1:0] bits (Port x configuration bits, pin 11) */
+#define GPIO_CRH_CNF11_0 (0x1U << GPIO_CRH_CNF11_Pos) /*!< 0x00004000 */
+#define GPIO_CRH_CNF11_1 (0x2U << GPIO_CRH_CNF11_Pos) /*!< 0x00008000 */
+
+#define GPIO_CRH_CNF12_Pos (18U)
+#define GPIO_CRH_CNF12_Msk (0x3U << GPIO_CRH_CNF12_Pos) /*!< 0x000C0000 */
+#define GPIO_CRH_CNF12 GPIO_CRH_CNF12_Msk /*!< CNF12[1:0] bits (Port x configuration bits, pin 12) */
+#define GPIO_CRH_CNF12_0 (0x1U << GPIO_CRH_CNF12_Pos) /*!< 0x00040000 */
+#define GPIO_CRH_CNF12_1 (0x2U << GPIO_CRH_CNF12_Pos) /*!< 0x00080000 */
+
+#define GPIO_CRH_CNF13_Pos (22U)
+#define GPIO_CRH_CNF13_Msk (0x3U << GPIO_CRH_CNF13_Pos) /*!< 0x00C00000 */
+#define GPIO_CRH_CNF13 GPIO_CRH_CNF13_Msk /*!< CNF13[1:0] bits (Port x configuration bits, pin 13) */
+#define GPIO_CRH_CNF13_0 (0x1U << GPIO_CRH_CNF13_Pos) /*!< 0x00400000 */
+#define GPIO_CRH_CNF13_1 (0x2U << GPIO_CRH_CNF13_Pos) /*!< 0x00800000 */
+
+#define GPIO_CRH_CNF14_Pos (26U)
+#define GPIO_CRH_CNF14_Msk (0x3U << GPIO_CRH_CNF14_Pos) /*!< 0x0C000000 */
+#define GPIO_CRH_CNF14 GPIO_CRH_CNF14_Msk /*!< CNF14[1:0] bits (Port x configuration bits, pin 14) */
+#define GPIO_CRH_CNF14_0 (0x1U << GPIO_CRH_CNF14_Pos) /*!< 0x04000000 */
+#define GPIO_CRH_CNF14_1 (0x2U << GPIO_CRH_CNF14_Pos) /*!< 0x08000000 */
+
+#define GPIO_CRH_CNF15_Pos (30U)
+#define GPIO_CRH_CNF15_Msk (0x3U << GPIO_CRH_CNF15_Pos) /*!< 0xC0000000 */
+#define GPIO_CRH_CNF15 GPIO_CRH_CNF15_Msk /*!< CNF15[1:0] bits (Port x configuration bits, pin 15) */
+#define GPIO_CRH_CNF15_0 (0x1U << GPIO_CRH_CNF15_Pos) /*!< 0x40000000 */
+#define GPIO_CRH_CNF15_1 (0x2U << GPIO_CRH_CNF15_Pos) /*!< 0x80000000 */
+
+/*!<****************** Bit definition for GPIO_IDR register *******************/
+#define GPIO_IDR_IDR0_Pos (0U)
+#define GPIO_IDR_IDR0_Msk (0x1U << GPIO_IDR_IDR0_Pos) /*!< 0x00000001 */
+#define GPIO_IDR_IDR0 GPIO_IDR_IDR0_Msk /*!< Port input data, bit 0 */
+#define GPIO_IDR_IDR1_Pos (1U)
+#define GPIO_IDR_IDR1_Msk (0x1U << GPIO_IDR_IDR1_Pos) /*!< 0x00000002 */
+#define GPIO_IDR_IDR1 GPIO_IDR_IDR1_Msk /*!< Port input data, bit 1 */
+#define GPIO_IDR_IDR2_Pos (2U)
+#define GPIO_IDR_IDR2_Msk (0x1U << GPIO_IDR_IDR2_Pos) /*!< 0x00000004 */
+#define GPIO_IDR_IDR2 GPIO_IDR_IDR2_Msk /*!< Port input data, bit 2 */
+#define GPIO_IDR_IDR3_Pos (3U)
+#define GPIO_IDR_IDR3_Msk (0x1U << GPIO_IDR_IDR3_Pos) /*!< 0x00000008 */
+#define GPIO_IDR_IDR3 GPIO_IDR_IDR3_Msk /*!< Port input data, bit 3 */
+#define GPIO_IDR_IDR4_Pos (4U)
+#define GPIO_IDR_IDR4_Msk (0x1U << GPIO_IDR_IDR4_Pos) /*!< 0x00000010 */
+#define GPIO_IDR_IDR4 GPIO_IDR_IDR4_Msk /*!< Port input data, bit 4 */
+#define GPIO_IDR_IDR5_Pos (5U)
+#define GPIO_IDR_IDR5_Msk (0x1U << GPIO_IDR_IDR5_Pos) /*!< 0x00000020 */
+#define GPIO_IDR_IDR5 GPIO_IDR_IDR5_Msk /*!< Port input data, bit 5 */
+#define GPIO_IDR_IDR6_Pos (6U)
+#define GPIO_IDR_IDR6_Msk (0x1U << GPIO_IDR_IDR6_Pos) /*!< 0x00000040 */
+#define GPIO_IDR_IDR6 GPIO_IDR_IDR6_Msk /*!< Port input data, bit 6 */
+#define GPIO_IDR_IDR7_Pos (7U)
+#define GPIO_IDR_IDR7_Msk (0x1U << GPIO_IDR_IDR7_Pos) /*!< 0x00000080 */
+#define GPIO_IDR_IDR7 GPIO_IDR_IDR7_Msk /*!< Port input data, bit 7 */
+#define GPIO_IDR_IDR8_Pos (8U)
+#define GPIO_IDR_IDR8_Msk (0x1U << GPIO_IDR_IDR8_Pos) /*!< 0x00000100 */
+#define GPIO_IDR_IDR8 GPIO_IDR_IDR8_Msk /*!< Port input data, bit 8 */
+#define GPIO_IDR_IDR9_Pos (9U)
+#define GPIO_IDR_IDR9_Msk (0x1U << GPIO_IDR_IDR9_Pos) /*!< 0x00000200 */
+#define GPIO_IDR_IDR9 GPIO_IDR_IDR9_Msk /*!< Port input data, bit 9 */
+#define GPIO_IDR_IDR10_Pos (10U)
+#define GPIO_IDR_IDR10_Msk (0x1U << GPIO_IDR_IDR10_Pos) /*!< 0x00000400 */
+#define GPIO_IDR_IDR10 GPIO_IDR_IDR10_Msk /*!< Port input data, bit 10 */
+#define GPIO_IDR_IDR11_Pos (11U)
+#define GPIO_IDR_IDR11_Msk (0x1U << GPIO_IDR_IDR11_Pos) /*!< 0x00000800 */
+#define GPIO_IDR_IDR11 GPIO_IDR_IDR11_Msk /*!< Port input data, bit 11 */
+#define GPIO_IDR_IDR12_Pos (12U)
+#define GPIO_IDR_IDR12_Msk (0x1U << GPIO_IDR_IDR12_Pos) /*!< 0x00001000 */
+#define GPIO_IDR_IDR12 GPIO_IDR_IDR12_Msk /*!< Port input data, bit 12 */
+#define GPIO_IDR_IDR13_Pos (13U)
+#define GPIO_IDR_IDR13_Msk (0x1U << GPIO_IDR_IDR13_Pos) /*!< 0x00002000 */
+#define GPIO_IDR_IDR13 GPIO_IDR_IDR13_Msk /*!< Port input data, bit 13 */
+#define GPIO_IDR_IDR14_Pos (14U)
+#define GPIO_IDR_IDR14_Msk (0x1U << GPIO_IDR_IDR14_Pos) /*!< 0x00004000 */
+#define GPIO_IDR_IDR14 GPIO_IDR_IDR14_Msk /*!< Port input data, bit 14 */
+#define GPIO_IDR_IDR15_Pos (15U)
+#define GPIO_IDR_IDR15_Msk (0x1U << GPIO_IDR_IDR15_Pos) /*!< 0x00008000 */
+#define GPIO_IDR_IDR15 GPIO_IDR_IDR15_Msk /*!< Port input data, bit 15 */
+
+/******************* Bit definition for GPIO_ODR register *******************/
+#define GPIO_ODR_ODR0_Pos (0U)
+#define GPIO_ODR_ODR0_Msk (0x1U << GPIO_ODR_ODR0_Pos) /*!< 0x00000001 */
+#define GPIO_ODR_ODR0 GPIO_ODR_ODR0_Msk /*!< Port output data, bit 0 */
+#define GPIO_ODR_ODR1_Pos (1U)
+#define GPIO_ODR_ODR1_Msk (0x1U << GPIO_ODR_ODR1_Pos) /*!< 0x00000002 */
+#define GPIO_ODR_ODR1 GPIO_ODR_ODR1_Msk /*!< Port output data, bit 1 */
+#define GPIO_ODR_ODR2_Pos (2U)
+#define GPIO_ODR_ODR2_Msk (0x1U << GPIO_ODR_ODR2_Pos) /*!< 0x00000004 */
+#define GPIO_ODR_ODR2 GPIO_ODR_ODR2_Msk /*!< Port output data, bit 2 */
+#define GPIO_ODR_ODR3_Pos (3U)
+#define GPIO_ODR_ODR3_Msk (0x1U << GPIO_ODR_ODR3_Pos) /*!< 0x00000008 */
+#define GPIO_ODR_ODR3 GPIO_ODR_ODR3_Msk /*!< Port output data, bit 3 */
+#define GPIO_ODR_ODR4_Pos (4U)
+#define GPIO_ODR_ODR4_Msk (0x1U << GPIO_ODR_ODR4_Pos) /*!< 0x00000010 */
+#define GPIO_ODR_ODR4 GPIO_ODR_ODR4_Msk /*!< Port output data, bit 4 */
+#define GPIO_ODR_ODR5_Pos (5U)
+#define GPIO_ODR_ODR5_Msk (0x1U << GPIO_ODR_ODR5_Pos) /*!< 0x00000020 */
+#define GPIO_ODR_ODR5 GPIO_ODR_ODR5_Msk /*!< Port output data, bit 5 */
+#define GPIO_ODR_ODR6_Pos (6U)
+#define GPIO_ODR_ODR6_Msk (0x1U << GPIO_ODR_ODR6_Pos) /*!< 0x00000040 */
+#define GPIO_ODR_ODR6 GPIO_ODR_ODR6_Msk /*!< Port output data, bit 6 */
+#define GPIO_ODR_ODR7_Pos (7U)
+#define GPIO_ODR_ODR7_Msk (0x1U << GPIO_ODR_ODR7_Pos) /*!< 0x00000080 */
+#define GPIO_ODR_ODR7 GPIO_ODR_ODR7_Msk /*!< Port output data, bit 7 */
+#define GPIO_ODR_ODR8_Pos (8U)
+#define GPIO_ODR_ODR8_Msk (0x1U << GPIO_ODR_ODR8_Pos) /*!< 0x00000100 */
+#define GPIO_ODR_ODR8 GPIO_ODR_ODR8_Msk /*!< Port output data, bit 8 */
+#define GPIO_ODR_ODR9_Pos (9U)
+#define GPIO_ODR_ODR9_Msk (0x1U << GPIO_ODR_ODR9_Pos) /*!< 0x00000200 */
+#define GPIO_ODR_ODR9 GPIO_ODR_ODR9_Msk /*!< Port output data, bit 9 */
+#define GPIO_ODR_ODR10_Pos (10U)
+#define GPIO_ODR_ODR10_Msk (0x1U << GPIO_ODR_ODR10_Pos) /*!< 0x00000400 */
+#define GPIO_ODR_ODR10 GPIO_ODR_ODR10_Msk /*!< Port output data, bit 10 */
+#define GPIO_ODR_ODR11_Pos (11U)
+#define GPIO_ODR_ODR11_Msk (0x1U << GPIO_ODR_ODR11_Pos) /*!< 0x00000800 */
+#define GPIO_ODR_ODR11 GPIO_ODR_ODR11_Msk /*!< Port output data, bit 11 */
+#define GPIO_ODR_ODR12_Pos (12U)
+#define GPIO_ODR_ODR12_Msk (0x1U << GPIO_ODR_ODR12_Pos) /*!< 0x00001000 */
+#define GPIO_ODR_ODR12 GPIO_ODR_ODR12_Msk /*!< Port output data, bit 12 */
+#define GPIO_ODR_ODR13_Pos (13U)
+#define GPIO_ODR_ODR13_Msk (0x1U << GPIO_ODR_ODR13_Pos) /*!< 0x00002000 */
+#define GPIO_ODR_ODR13 GPIO_ODR_ODR13_Msk /*!< Port output data, bit 13 */
+#define GPIO_ODR_ODR14_Pos (14U)
+#define GPIO_ODR_ODR14_Msk (0x1U << GPIO_ODR_ODR14_Pos) /*!< 0x00004000 */
+#define GPIO_ODR_ODR14 GPIO_ODR_ODR14_Msk /*!< Port output data, bit 14 */
+#define GPIO_ODR_ODR15_Pos (15U)
+#define GPIO_ODR_ODR15_Msk (0x1U << GPIO_ODR_ODR15_Pos) /*!< 0x00008000 */
+#define GPIO_ODR_ODR15 GPIO_ODR_ODR15_Msk /*!< Port output data, bit 15 */
+
+/****************** Bit definition for GPIO_BSRR register *******************/
+#define GPIO_BSRR_BS0_Pos (0U)
+#define GPIO_BSRR_BS0_Msk (0x1U << GPIO_BSRR_BS0_Pos) /*!< 0x00000001 */
+#define GPIO_BSRR_BS0 GPIO_BSRR_BS0_Msk /*!< Port x Set bit 0 */
+#define GPIO_BSRR_BS1_Pos (1U)
+#define GPIO_BSRR_BS1_Msk (0x1U << GPIO_BSRR_BS1_Pos) /*!< 0x00000002 */
+#define GPIO_BSRR_BS1 GPIO_BSRR_BS1_Msk /*!< Port x Set bit 1 */
+#define GPIO_BSRR_BS2_Pos (2U)
+#define GPIO_BSRR_BS2_Msk (0x1U << GPIO_BSRR_BS2_Pos) /*!< 0x00000004 */
+#define GPIO_BSRR_BS2 GPIO_BSRR_BS2_Msk /*!< Port x Set bit 2 */
+#define GPIO_BSRR_BS3_Pos (3U)
+#define GPIO_BSRR_BS3_Msk (0x1U << GPIO_BSRR_BS3_Pos) /*!< 0x00000008 */
+#define GPIO_BSRR_BS3 GPIO_BSRR_BS3_Msk /*!< Port x Set bit 3 */
+#define GPIO_BSRR_BS4_Pos (4U)
+#define GPIO_BSRR_BS4_Msk (0x1U << GPIO_BSRR_BS4_Pos) /*!< 0x00000010 */
+#define GPIO_BSRR_BS4 GPIO_BSRR_BS4_Msk /*!< Port x Set bit 4 */
+#define GPIO_BSRR_BS5_Pos (5U)
+#define GPIO_BSRR_BS5_Msk (0x1U << GPIO_BSRR_BS5_Pos) /*!< 0x00000020 */
+#define GPIO_BSRR_BS5 GPIO_BSRR_BS5_Msk /*!< Port x Set bit 5 */
+#define GPIO_BSRR_BS6_Pos (6U)
+#define GPIO_BSRR_BS6_Msk (0x1U << GPIO_BSRR_BS6_Pos) /*!< 0x00000040 */
+#define GPIO_BSRR_BS6 GPIO_BSRR_BS6_Msk /*!< Port x Set bit 6 */
+#define GPIO_BSRR_BS7_Pos (7U)
+#define GPIO_BSRR_BS7_Msk (0x1U << GPIO_BSRR_BS7_Pos) /*!< 0x00000080 */
+#define GPIO_BSRR_BS7 GPIO_BSRR_BS7_Msk /*!< Port x Set bit 7 */
+#define GPIO_BSRR_BS8_Pos (8U)
+#define GPIO_BSRR_BS8_Msk (0x1U << GPIO_BSRR_BS8_Pos) /*!< 0x00000100 */
+#define GPIO_BSRR_BS8 GPIO_BSRR_BS8_Msk /*!< Port x Set bit 8 */
+#define GPIO_BSRR_BS9_Pos (9U)
+#define GPIO_BSRR_BS9_Msk (0x1U << GPIO_BSRR_BS9_Pos) /*!< 0x00000200 */
+#define GPIO_BSRR_BS9 GPIO_BSRR_BS9_Msk /*!< Port x Set bit 9 */
+#define GPIO_BSRR_BS10_Pos (10U)
+#define GPIO_BSRR_BS10_Msk (0x1U << GPIO_BSRR_BS10_Pos) /*!< 0x00000400 */
+#define GPIO_BSRR_BS10 GPIO_BSRR_BS10_Msk /*!< Port x Set bit 10 */
+#define GPIO_BSRR_BS11_Pos (11U)
+#define GPIO_BSRR_BS11_Msk (0x1U << GPIO_BSRR_BS11_Pos) /*!< 0x00000800 */
+#define GPIO_BSRR_BS11 GPIO_BSRR_BS11_Msk /*!< Port x Set bit 11 */
+#define GPIO_BSRR_BS12_Pos (12U)
+#define GPIO_BSRR_BS12_Msk (0x1U << GPIO_BSRR_BS12_Pos) /*!< 0x00001000 */
+#define GPIO_BSRR_BS12 GPIO_BSRR_BS12_Msk /*!< Port x Set bit 12 */
+#define GPIO_BSRR_BS13_Pos (13U)
+#define GPIO_BSRR_BS13_Msk (0x1U << GPIO_BSRR_BS13_Pos) /*!< 0x00002000 */
+#define GPIO_BSRR_BS13 GPIO_BSRR_BS13_Msk /*!< Port x Set bit 13 */
+#define GPIO_BSRR_BS14_Pos (14U)
+#define GPIO_BSRR_BS14_Msk (0x1U << GPIO_BSRR_BS14_Pos) /*!< 0x00004000 */
+#define GPIO_BSRR_BS14 GPIO_BSRR_BS14_Msk /*!< Port x Set bit 14 */
+#define GPIO_BSRR_BS15_Pos (15U)
+#define GPIO_BSRR_BS15_Msk (0x1U << GPIO_BSRR_BS15_Pos) /*!< 0x00008000 */
+#define GPIO_BSRR_BS15 GPIO_BSRR_BS15_Msk /*!< Port x Set bit 15 */
+
+#define GPIO_BSRR_BR0_Pos (16U)
+#define GPIO_BSRR_BR0_Msk (0x1U << GPIO_BSRR_BR0_Pos) /*!< 0x00010000 */
+#define GPIO_BSRR_BR0 GPIO_BSRR_BR0_Msk /*!< Port x Reset bit 0 */
+#define GPIO_BSRR_BR1_Pos (17U)
+#define GPIO_BSRR_BR1_Msk (0x1U << GPIO_BSRR_BR1_Pos) /*!< 0x00020000 */
+#define GPIO_BSRR_BR1 GPIO_BSRR_BR1_Msk /*!< Port x Reset bit 1 */
+#define GPIO_BSRR_BR2_Pos (18U)
+#define GPIO_BSRR_BR2_Msk (0x1U << GPIO_BSRR_BR2_Pos) /*!< 0x00040000 */
+#define GPIO_BSRR_BR2 GPIO_BSRR_BR2_Msk /*!< Port x Reset bit 2 */
+#define GPIO_BSRR_BR3_Pos (19U)
+#define GPIO_BSRR_BR3_Msk (0x1U << GPIO_BSRR_BR3_Pos) /*!< 0x00080000 */
+#define GPIO_BSRR_BR3 GPIO_BSRR_BR3_Msk /*!< Port x Reset bit 3 */
+#define GPIO_BSRR_BR4_Pos (20U)
+#define GPIO_BSRR_BR4_Msk (0x1U << GPIO_BSRR_BR4_Pos) /*!< 0x00100000 */
+#define GPIO_BSRR_BR4 GPIO_BSRR_BR4_Msk /*!< Port x Reset bit 4 */
+#define GPIO_BSRR_BR5_Pos (21U)
+#define GPIO_BSRR_BR5_Msk (0x1U << GPIO_BSRR_BR5_Pos) /*!< 0x00200000 */
+#define GPIO_BSRR_BR5 GPIO_BSRR_BR5_Msk /*!< Port x Reset bit 5 */
+#define GPIO_BSRR_BR6_Pos (22U)
+#define GPIO_BSRR_BR6_Msk (0x1U << GPIO_BSRR_BR6_Pos) /*!< 0x00400000 */
+#define GPIO_BSRR_BR6 GPIO_BSRR_BR6_Msk /*!< Port x Reset bit 6 */
+#define GPIO_BSRR_BR7_Pos (23U)
+#define GPIO_BSRR_BR7_Msk (0x1U << GPIO_BSRR_BR7_Pos) /*!< 0x00800000 */
+#define GPIO_BSRR_BR7 GPIO_BSRR_BR7_Msk /*!< Port x Reset bit 7 */
+#define GPIO_BSRR_BR8_Pos (24U)
+#define GPIO_BSRR_BR8_Msk (0x1U << GPIO_BSRR_BR8_Pos) /*!< 0x01000000 */
+#define GPIO_BSRR_BR8 GPIO_BSRR_BR8_Msk /*!< Port x Reset bit 8 */
+#define GPIO_BSRR_BR9_Pos (25U)
+#define GPIO_BSRR_BR9_Msk (0x1U << GPIO_BSRR_BR9_Pos) /*!< 0x02000000 */
+#define GPIO_BSRR_BR9 GPIO_BSRR_BR9_Msk /*!< Port x Reset bit 9 */
+#define GPIO_BSRR_BR10_Pos (26U)
+#define GPIO_BSRR_BR10_Msk (0x1U << GPIO_BSRR_BR10_Pos) /*!< 0x04000000 */
+#define GPIO_BSRR_BR10 GPIO_BSRR_BR10_Msk /*!< Port x Reset bit 10 */
+#define GPIO_BSRR_BR11_Pos (27U)
+#define GPIO_BSRR_BR11_Msk (0x1U << GPIO_BSRR_BR11_Pos) /*!< 0x08000000 */
+#define GPIO_BSRR_BR11 GPIO_BSRR_BR11_Msk /*!< Port x Reset bit 11 */
+#define GPIO_BSRR_BR12_Pos (28U)
+#define GPIO_BSRR_BR12_Msk (0x1U << GPIO_BSRR_BR12_Pos) /*!< 0x10000000 */
+#define GPIO_BSRR_BR12 GPIO_BSRR_BR12_Msk /*!< Port x Reset bit 12 */
+#define GPIO_BSRR_BR13_Pos (29U)
+#define GPIO_BSRR_BR13_Msk (0x1U << GPIO_BSRR_BR13_Pos) /*!< 0x20000000 */
+#define GPIO_BSRR_BR13 GPIO_BSRR_BR13_Msk /*!< Port x Reset bit 13 */
+#define GPIO_BSRR_BR14_Pos (30U)
+#define GPIO_BSRR_BR14_Msk (0x1U << GPIO_BSRR_BR14_Pos) /*!< 0x40000000 */
+#define GPIO_BSRR_BR14 GPIO_BSRR_BR14_Msk /*!< Port x Reset bit 14 */
+#define GPIO_BSRR_BR15_Pos (31U)
+#define GPIO_BSRR_BR15_Msk (0x1U << GPIO_BSRR_BR15_Pos) /*!< 0x80000000 */
+#define GPIO_BSRR_BR15 GPIO_BSRR_BR15_Msk /*!< Port x Reset bit 15 */
+
+/******************* Bit definition for GPIO_BRR register *******************/
+#define GPIO_BRR_BR0_Pos (0U)
+#define GPIO_BRR_BR0_Msk (0x1U << GPIO_BRR_BR0_Pos) /*!< 0x00000001 */
+#define GPIO_BRR_BR0 GPIO_BRR_BR0_Msk /*!< Port x Reset bit 0 */
+#define GPIO_BRR_BR1_Pos (1U)
+#define GPIO_BRR_BR1_Msk (0x1U << GPIO_BRR_BR1_Pos) /*!< 0x00000002 */
+#define GPIO_BRR_BR1 GPIO_BRR_BR1_Msk /*!< Port x Reset bit 1 */
+#define GPIO_BRR_BR2_Pos (2U)
+#define GPIO_BRR_BR2_Msk (0x1U << GPIO_BRR_BR2_Pos) /*!< 0x00000004 */
+#define GPIO_BRR_BR2 GPIO_BRR_BR2_Msk /*!< Port x Reset bit 2 */
+#define GPIO_BRR_BR3_Pos (3U)
+#define GPIO_BRR_BR3_Msk (0x1U << GPIO_BRR_BR3_Pos) /*!< 0x00000008 */
+#define GPIO_BRR_BR3 GPIO_BRR_BR3_Msk /*!< Port x Reset bit 3 */
+#define GPIO_BRR_BR4_Pos (4U)
+#define GPIO_BRR_BR4_Msk (0x1U << GPIO_BRR_BR4_Pos) /*!< 0x00000010 */
+#define GPIO_BRR_BR4 GPIO_BRR_BR4_Msk /*!< Port x Reset bit 4 */
+#define GPIO_BRR_BR5_Pos (5U)
+#define GPIO_BRR_BR5_Msk (0x1U << GPIO_BRR_BR5_Pos) /*!< 0x00000020 */
+#define GPIO_BRR_BR5 GPIO_BRR_BR5_Msk /*!< Port x Reset bit 5 */
+#define GPIO_BRR_BR6_Pos (6U)
+#define GPIO_BRR_BR6_Msk (0x1U << GPIO_BRR_BR6_Pos) /*!< 0x00000040 */
+#define GPIO_BRR_BR6 GPIO_BRR_BR6_Msk /*!< Port x Reset bit 6 */
+#define GPIO_BRR_BR7_Pos (7U)
+#define GPIO_BRR_BR7_Msk (0x1U << GPIO_BRR_BR7_Pos) /*!< 0x00000080 */
+#define GPIO_BRR_BR7 GPIO_BRR_BR7_Msk /*!< Port x Reset bit 7 */
+#define GPIO_BRR_BR8_Pos (8U)
+#define GPIO_BRR_BR8_Msk (0x1U << GPIO_BRR_BR8_Pos) /*!< 0x00000100 */
+#define GPIO_BRR_BR8 GPIO_BRR_BR8_Msk /*!< Port x Reset bit 8 */
+#define GPIO_BRR_BR9_Pos (9U)
+#define GPIO_BRR_BR9_Msk (0x1U << GPIO_BRR_BR9_Pos) /*!< 0x00000200 */
+#define GPIO_BRR_BR9 GPIO_BRR_BR9_Msk /*!< Port x Reset bit 9 */
+#define GPIO_BRR_BR10_Pos (10U)
+#define GPIO_BRR_BR10_Msk (0x1U << GPIO_BRR_BR10_Pos) /*!< 0x00000400 */
+#define GPIO_BRR_BR10 GPIO_BRR_BR10_Msk /*!< Port x Reset bit 10 */
+#define GPIO_BRR_BR11_Pos (11U)
+#define GPIO_BRR_BR11_Msk (0x1U << GPIO_BRR_BR11_Pos) /*!< 0x00000800 */
+#define GPIO_BRR_BR11 GPIO_BRR_BR11_Msk /*!< Port x Reset bit 11 */
+#define GPIO_BRR_BR12_Pos (12U)
+#define GPIO_BRR_BR12_Msk (0x1U << GPIO_BRR_BR12_Pos) /*!< 0x00001000 */
+#define GPIO_BRR_BR12 GPIO_BRR_BR12_Msk /*!< Port x Reset bit 12 */
+#define GPIO_BRR_BR13_Pos (13U)
+#define GPIO_BRR_BR13_Msk (0x1U << GPIO_BRR_BR13_Pos) /*!< 0x00002000 */
+#define GPIO_BRR_BR13 GPIO_BRR_BR13_Msk /*!< Port x Reset bit 13 */
+#define GPIO_BRR_BR14_Pos (14U)
+#define GPIO_BRR_BR14_Msk (0x1U << GPIO_BRR_BR14_Pos) /*!< 0x00004000 */
+#define GPIO_BRR_BR14 GPIO_BRR_BR14_Msk /*!< Port x Reset bit 14 */
+#define GPIO_BRR_BR15_Pos (15U)
+#define GPIO_BRR_BR15_Msk (0x1U << GPIO_BRR_BR15_Pos) /*!< 0x00008000 */
+#define GPIO_BRR_BR15 GPIO_BRR_BR15_Msk /*!< Port x Reset bit 15 */
+
+/****************** Bit definition for GPIO_LCKR register *******************/
+#define GPIO_LCKR_LCK0_Pos (0U)
+#define GPIO_LCKR_LCK0_Msk (0x1U << GPIO_LCKR_LCK0_Pos) /*!< 0x00000001 */
+#define GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk /*!< Port x Lock bit 0 */
+#define GPIO_LCKR_LCK1_Pos (1U)
+#define GPIO_LCKR_LCK1_Msk (0x1U << GPIO_LCKR_LCK1_Pos) /*!< 0x00000002 */
+#define GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk /*!< Port x Lock bit 1 */
+#define GPIO_LCKR_LCK2_Pos (2U)
+#define GPIO_LCKR_LCK2_Msk (0x1U << GPIO_LCKR_LCK2_Pos) /*!< 0x00000004 */
+#define GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk /*!< Port x Lock bit 2 */
+#define GPIO_LCKR_LCK3_Pos (3U)
+#define GPIO_LCKR_LCK3_Msk (0x1U << GPIO_LCKR_LCK3_Pos) /*!< 0x00000008 */
+#define GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk /*!< Port x Lock bit 3 */
+#define GPIO_LCKR_LCK4_Pos (4U)
+#define GPIO_LCKR_LCK4_Msk (0x1U << GPIO_LCKR_LCK4_Pos) /*!< 0x00000010 */
+#define GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk /*!< Port x Lock bit 4 */
+#define GPIO_LCKR_LCK5_Pos (5U)
+#define GPIO_LCKR_LCK5_Msk (0x1U << GPIO_LCKR_LCK5_Pos) /*!< 0x00000020 */
+#define GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk /*!< Port x Lock bit 5 */
+#define GPIO_LCKR_LCK6_Pos (6U)
+#define GPIO_LCKR_LCK6_Msk (0x1U << GPIO_LCKR_LCK6_Pos) /*!< 0x00000040 */
+#define GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk /*!< Port x Lock bit 6 */
+#define GPIO_LCKR_LCK7_Pos (7U)
+#define GPIO_LCKR_LCK7_Msk (0x1U << GPIO_LCKR_LCK7_Pos) /*!< 0x00000080 */
+#define GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk /*!< Port x Lock bit 7 */
+#define GPIO_LCKR_LCK8_Pos (8U)
+#define GPIO_LCKR_LCK8_Msk (0x1U << GPIO_LCKR_LCK8_Pos) /*!< 0x00000100 */
+#define GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk /*!< Port x Lock bit 8 */
+#define GPIO_LCKR_LCK9_Pos (9U)
+#define GPIO_LCKR_LCK9_Msk (0x1U << GPIO_LCKR_LCK9_Pos) /*!< 0x00000200 */
+#define GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk /*!< Port x Lock bit 9 */
+#define GPIO_LCKR_LCK10_Pos (10U)
+#define GPIO_LCKR_LCK10_Msk (0x1U << GPIO_LCKR_LCK10_Pos) /*!< 0x00000400 */
+#define GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk /*!< Port x Lock bit 10 */
+#define GPIO_LCKR_LCK11_Pos (11U)
+#define GPIO_LCKR_LCK11_Msk (0x1U << GPIO_LCKR_LCK11_Pos) /*!< 0x00000800 */
+#define GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk /*!< Port x Lock bit 11 */
+#define GPIO_LCKR_LCK12_Pos (12U)
+#define GPIO_LCKR_LCK12_Msk (0x1U << GPIO_LCKR_LCK12_Pos) /*!< 0x00001000 */
+#define GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk /*!< Port x Lock bit 12 */
+#define GPIO_LCKR_LCK13_Pos (13U)
+#define GPIO_LCKR_LCK13_Msk (0x1U << GPIO_LCKR_LCK13_Pos) /*!< 0x00002000 */
+#define GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk /*!< Port x Lock bit 13 */
+#define GPIO_LCKR_LCK14_Pos (14U)
+#define GPIO_LCKR_LCK14_Msk (0x1U << GPIO_LCKR_LCK14_Pos) /*!< 0x00004000 */
+#define GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk /*!< Port x Lock bit 14 */
+#define GPIO_LCKR_LCK15_Pos (15U)
+#define GPIO_LCKR_LCK15_Msk (0x1U << GPIO_LCKR_LCK15_Pos) /*!< 0x00008000 */
+#define GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk /*!< Port x Lock bit 15 */
+#define GPIO_LCKR_LCKK_Pos (16U)
+#define GPIO_LCKR_LCKK_Msk (0x1U << GPIO_LCKR_LCKK_Pos) /*!< 0x00010000 */
+#define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk /*!< Lock key */
+
+/*----------------------------------------------------------------------------*/
+
+/****************** Bit definition for AFIO_EVCR register *******************/
+#define AFIO_EVCR_PIN_Pos (0U)
+#define AFIO_EVCR_PIN_Msk (0xFU << AFIO_EVCR_PIN_Pos) /*!< 0x0000000F */
+#define AFIO_EVCR_PIN AFIO_EVCR_PIN_Msk /*!< PIN[3:0] bits (Pin selection) */
+#define AFIO_EVCR_PIN_0 (0x1U << AFIO_EVCR_PIN_Pos) /*!< 0x00000001 */
+#define AFIO_EVCR_PIN_1 (0x2U << AFIO_EVCR_PIN_Pos) /*!< 0x00000002 */
+#define AFIO_EVCR_PIN_2 (0x4U << AFIO_EVCR_PIN_Pos) /*!< 0x00000004 */
+#define AFIO_EVCR_PIN_3 (0x8U << AFIO_EVCR_PIN_Pos) /*!< 0x00000008 */
+
+/*!< PIN configuration */
+#define AFIO_EVCR_PIN_PX0 ((uint32_t)0x00000000) /*!< Pin 0 selected */
+#define AFIO_EVCR_PIN_PX1_Pos (0U)
+#define AFIO_EVCR_PIN_PX1_Msk (0x1U << AFIO_EVCR_PIN_PX1_Pos) /*!< 0x00000001 */
+#define AFIO_EVCR_PIN_PX1 AFIO_EVCR_PIN_PX1_Msk /*!< Pin 1 selected */
+#define AFIO_EVCR_PIN_PX2_Pos (1U)
+#define AFIO_EVCR_PIN_PX2_Msk (0x1U << AFIO_EVCR_PIN_PX2_Pos) /*!< 0x00000002 */
+#define AFIO_EVCR_PIN_PX2 AFIO_EVCR_PIN_PX2_Msk /*!< Pin 2 selected */
+#define AFIO_EVCR_PIN_PX3_Pos (0U)
+#define AFIO_EVCR_PIN_PX3_Msk (0x3U << AFIO_EVCR_PIN_PX3_Pos) /*!< 0x00000003 */
+#define AFIO_EVCR_PIN_PX3 AFIO_EVCR_PIN_PX3_Msk /*!< Pin 3 selected */
+#define AFIO_EVCR_PIN_PX4_Pos (2U)
+#define AFIO_EVCR_PIN_PX4_Msk (0x1U << AFIO_EVCR_PIN_PX4_Pos) /*!< 0x00000004 */
+#define AFIO_EVCR_PIN_PX4 AFIO_EVCR_PIN_PX4_Msk /*!< Pin 4 selected */
+#define AFIO_EVCR_PIN_PX5_Pos (0U)
+#define AFIO_EVCR_PIN_PX5_Msk (0x5U << AFIO_EVCR_PIN_PX5_Pos) /*!< 0x00000005 */
+#define AFIO_EVCR_PIN_PX5 AFIO_EVCR_PIN_PX5_Msk /*!< Pin 5 selected */
+#define AFIO_EVCR_PIN_PX6_Pos (1U)
+#define AFIO_EVCR_PIN_PX6_Msk (0x3U << AFIO_EVCR_PIN_PX6_Pos) /*!< 0x00000006 */
+#define AFIO_EVCR_PIN_PX6 AFIO_EVCR_PIN_PX6_Msk /*!< Pin 6 selected */
+#define AFIO_EVCR_PIN_PX7_Pos (0U)
+#define AFIO_EVCR_PIN_PX7_Msk (0x7U << AFIO_EVCR_PIN_PX7_Pos) /*!< 0x00000007 */
+#define AFIO_EVCR_PIN_PX7 AFIO_EVCR_PIN_PX7_Msk /*!< Pin 7 selected */
+#define AFIO_EVCR_PIN_PX8_Pos (3U)
+#define AFIO_EVCR_PIN_PX8_Msk (0x1U << AFIO_EVCR_PIN_PX8_Pos) /*!< 0x00000008 */
+#define AFIO_EVCR_PIN_PX8 AFIO_EVCR_PIN_PX8_Msk /*!< Pin 8 selected */
+#define AFIO_EVCR_PIN_PX9_Pos (0U)
+#define AFIO_EVCR_PIN_PX9_Msk (0x9U << AFIO_EVCR_PIN_PX9_Pos) /*!< 0x00000009 */
+#define AFIO_EVCR_PIN_PX9 AFIO_EVCR_PIN_PX9_Msk /*!< Pin 9 selected */
+#define AFIO_EVCR_PIN_PX10_Pos (1U)
+#define AFIO_EVCR_PIN_PX10_Msk (0x5U << AFIO_EVCR_PIN_PX10_Pos) /*!< 0x0000000A */
+#define AFIO_EVCR_PIN_PX10 AFIO_EVCR_PIN_PX10_Msk /*!< Pin 10 selected */
+#define AFIO_EVCR_PIN_PX11_Pos (0U)
+#define AFIO_EVCR_PIN_PX11_Msk (0xBU << AFIO_EVCR_PIN_PX11_Pos) /*!< 0x0000000B */
+#define AFIO_EVCR_PIN_PX11 AFIO_EVCR_PIN_PX11_Msk /*!< Pin 11 selected */
+#define AFIO_EVCR_PIN_PX12_Pos (2U)
+#define AFIO_EVCR_PIN_PX12_Msk (0x3U << AFIO_EVCR_PIN_PX12_Pos) /*!< 0x0000000C */
+#define AFIO_EVCR_PIN_PX12 AFIO_EVCR_PIN_PX12_Msk /*!< Pin 12 selected */
+#define AFIO_EVCR_PIN_PX13_Pos (0U)
+#define AFIO_EVCR_PIN_PX13_Msk (0xDU << AFIO_EVCR_PIN_PX13_Pos) /*!< 0x0000000D */
+#define AFIO_EVCR_PIN_PX13 AFIO_EVCR_PIN_PX13_Msk /*!< Pin 13 selected */
+#define AFIO_EVCR_PIN_PX14_Pos (1U)
+#define AFIO_EVCR_PIN_PX14_Msk (0x7U << AFIO_EVCR_PIN_PX14_Pos) /*!< 0x0000000E */
+#define AFIO_EVCR_PIN_PX14 AFIO_EVCR_PIN_PX14_Msk /*!< Pin 14 selected */
+#define AFIO_EVCR_PIN_PX15_Pos (0U)
+#define AFIO_EVCR_PIN_PX15_Msk (0xFU << AFIO_EVCR_PIN_PX15_Pos) /*!< 0x0000000F */
+#define AFIO_EVCR_PIN_PX15 AFIO_EVCR_PIN_PX15_Msk /*!< Pin 15 selected */
+
+#define AFIO_EVCR_PORT_Pos (4U)
+#define AFIO_EVCR_PORT_Msk (0x7U << AFIO_EVCR_PORT_Pos) /*!< 0x00000070 */
+#define AFIO_EVCR_PORT AFIO_EVCR_PORT_Msk /*!< PORT[2:0] bits (Port selection) */
+#define AFIO_EVCR_PORT_0 (0x1U << AFIO_EVCR_PORT_Pos) /*!< 0x00000010 */
+#define AFIO_EVCR_PORT_1 (0x2U << AFIO_EVCR_PORT_Pos) /*!< 0x00000020 */
+#define AFIO_EVCR_PORT_2 (0x4U << AFIO_EVCR_PORT_Pos) /*!< 0x00000040 */
+
+/*!< PORT configuration */
+#define AFIO_EVCR_PORT_PA ((uint32_t)0x00000000) /*!< Port A selected */
+#define AFIO_EVCR_PORT_PB_Pos (4U)
+#define AFIO_EVCR_PORT_PB_Msk (0x1U << AFIO_EVCR_PORT_PB_Pos) /*!< 0x00000010 */
+#define AFIO_EVCR_PORT_PB AFIO_EVCR_PORT_PB_Msk /*!< Port B selected */
+#define AFIO_EVCR_PORT_PC_Pos (5U)
+#define AFIO_EVCR_PORT_PC_Msk (0x1U << AFIO_EVCR_PORT_PC_Pos) /*!< 0x00000020 */
+#define AFIO_EVCR_PORT_PC AFIO_EVCR_PORT_PC_Msk /*!< Port C selected */
+#define AFIO_EVCR_PORT_PD_Pos (4U)
+#define AFIO_EVCR_PORT_PD_Msk (0x3U << AFIO_EVCR_PORT_PD_Pos) /*!< 0x00000030 */
+#define AFIO_EVCR_PORT_PD AFIO_EVCR_PORT_PD_Msk /*!< Port D selected */
+#define AFIO_EVCR_PORT_PE_Pos (6U)
+#define AFIO_EVCR_PORT_PE_Msk (0x1U << AFIO_EVCR_PORT_PE_Pos) /*!< 0x00000040 */
+#define AFIO_EVCR_PORT_PE AFIO_EVCR_PORT_PE_Msk /*!< Port E selected */
+
+#define AFIO_EVCR_EVOE_Pos (7U)
+#define AFIO_EVCR_EVOE_Msk (0x1U << AFIO_EVCR_EVOE_Pos) /*!< 0x00000080 */
+#define AFIO_EVCR_EVOE AFIO_EVCR_EVOE_Msk /*!< Event Output Enable */
+
+/****************** Bit definition for AFIO_MAPR register *******************/
+#define AFIO_MAPR_SPI1_REMAP_Pos (0U)
+#define AFIO_MAPR_SPI1_REMAP_Msk (0x1U << AFIO_MAPR_SPI1_REMAP_Pos) /*!< 0x00000001 */
+#define AFIO_MAPR_SPI1_REMAP AFIO_MAPR_SPI1_REMAP_Msk /*!< SPI1 remapping */
+#define AFIO_MAPR_I2C1_REMAP_Pos (1U)
+#define AFIO_MAPR_I2C1_REMAP_Msk (0x1U << AFIO_MAPR_I2C1_REMAP_Pos) /*!< 0x00000002 */
+#define AFIO_MAPR_I2C1_REMAP AFIO_MAPR_I2C1_REMAP_Msk /*!< I2C1 remapping */
+#define AFIO_MAPR_USART1_REMAP_Pos (2U)
+#define AFIO_MAPR_USART1_REMAP_Msk (0x1U << AFIO_MAPR_USART1_REMAP_Pos) /*!< 0x00000004 */
+#define AFIO_MAPR_USART1_REMAP AFIO_MAPR_USART1_REMAP_Msk /*!< USART1 remapping */
+#define AFIO_MAPR_USART2_REMAP_Pos (3U)
+#define AFIO_MAPR_USART2_REMAP_Msk (0x1U << AFIO_MAPR_USART2_REMAP_Pos) /*!< 0x00000008 */
+#define AFIO_MAPR_USART2_REMAP AFIO_MAPR_USART2_REMAP_Msk /*!< USART2 remapping */
+
+#define AFIO_MAPR_USART3_REMAP_Pos (4U)
+#define AFIO_MAPR_USART3_REMAP_Msk (0x3U << AFIO_MAPR_USART3_REMAP_Pos) /*!< 0x00000030 */
+#define AFIO_MAPR_USART3_REMAP AFIO_MAPR_USART3_REMAP_Msk /*!< USART3_REMAP[1:0] bits (USART3 remapping) */
+#define AFIO_MAPR_USART3_REMAP_0 (0x1U << AFIO_MAPR_USART3_REMAP_Pos) /*!< 0x00000010 */
+#define AFIO_MAPR_USART3_REMAP_1 (0x2U << AFIO_MAPR_USART3_REMAP_Pos) /*!< 0x00000020 */
+
+/* USART3_REMAP configuration */
+#define AFIO_MAPR_USART3_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14) */
+#define AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Pos (4U)
+#define AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Msk (0x1U << AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Pos) /*!< 0x00000010 */
+#define AFIO_MAPR_USART3_REMAP_PARTIALREMAP AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Msk /*!< Partial remap (TX/PC10, RX/PC11, CK/PC12, CTS/PB13, RTS/PB14) */
+#define AFIO_MAPR_USART3_REMAP_FULLREMAP_Pos (4U)
+#define AFIO_MAPR_USART3_REMAP_FULLREMAP_Msk (0x3U << AFIO_MAPR_USART3_REMAP_FULLREMAP_Pos) /*!< 0x00000030 */
+#define AFIO_MAPR_USART3_REMAP_FULLREMAP AFIO_MAPR_USART3_REMAP_FULLREMAP_Msk /*!< Full remap (TX/PD8, RX/PD9, CK/PD10, CTS/PD11, RTS/PD12) */
+
+#define AFIO_MAPR_TIM1_REMAP_Pos (6U)
+#define AFIO_MAPR_TIM1_REMAP_Msk (0x3U << AFIO_MAPR_TIM1_REMAP_Pos) /*!< 0x000000C0 */
+#define AFIO_MAPR_TIM1_REMAP AFIO_MAPR_TIM1_REMAP_Msk /*!< TIM1_REMAP[1:0] bits (TIM1 remapping) */
+#define AFIO_MAPR_TIM1_REMAP_0 (0x1U << AFIO_MAPR_TIM1_REMAP_Pos) /*!< 0x00000040 */
+#define AFIO_MAPR_TIM1_REMAP_1 (0x2U << AFIO_MAPR_TIM1_REMAP_Pos) /*!< 0x00000080 */
+
+/*!< TIM1_REMAP configuration */
+#define AFIO_MAPR_TIM1_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15) */
+#define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Pos (6U)
+#define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Msk (0x1U << AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Pos) /*!< 0x00000040 */
+#define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Msk /*!< Partial remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PA6, CH1N/PA7, CH2N/PB0, CH3N/PB1) */
+#define AFIO_MAPR_TIM1_REMAP_FULLREMAP_Pos (6U)
+#define AFIO_MAPR_TIM1_REMAP_FULLREMAP_Msk (0x3U << AFIO_MAPR_TIM1_REMAP_FULLREMAP_Pos) /*!< 0x000000C0 */
+#define AFIO_MAPR_TIM1_REMAP_FULLREMAP AFIO_MAPR_TIM1_REMAP_FULLREMAP_Msk /*!< Full remap (ETR/PE7, CH1/PE9, CH2/PE11, CH3/PE13, CH4/PE14, BKIN/PE15, CH1N/PE8, CH2N/PE10, CH3N/PE12) */
+
+#define AFIO_MAPR_TIM2_REMAP_Pos (8U)
+#define AFIO_MAPR_TIM2_REMAP_Msk (0x3U << AFIO_MAPR_TIM2_REMAP_Pos) /*!< 0x00000300 */
+#define AFIO_MAPR_TIM2_REMAP AFIO_MAPR_TIM2_REMAP_Msk /*!< TIM2_REMAP[1:0] bits (TIM2 remapping) */
+#define AFIO_MAPR_TIM2_REMAP_0 (0x1U << AFIO_MAPR_TIM2_REMAP_Pos) /*!< 0x00000100 */
+#define AFIO_MAPR_TIM2_REMAP_1 (0x2U << AFIO_MAPR_TIM2_REMAP_Pos) /*!< 0x00000200 */
+
+/*!< TIM2_REMAP configuration */
+#define AFIO_MAPR_TIM2_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3) */
+#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Pos (8U)
+#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Msk (0x1U << AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Pos) /*!< 0x00000100 */
+#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1 AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Msk /*!< Partial remap (CH1/ETR/PA15, CH2/PB3, CH3/PA2, CH4/PA3) */
+#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2_Pos (9U)
+#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2_Msk (0x1U << AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2_Pos) /*!< 0x00000200 */
+#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2 AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2_Msk /*!< Partial remap (CH1/ETR/PA0, CH2/PA1, CH3/PB10, CH4/PB11) */
+#define AFIO_MAPR_TIM2_REMAP_FULLREMAP_Pos (8U)
+#define AFIO_MAPR_TIM2_REMAP_FULLREMAP_Msk (0x3U << AFIO_MAPR_TIM2_REMAP_FULLREMAP_Pos) /*!< 0x00000300 */
+#define AFIO_MAPR_TIM2_REMAP_FULLREMAP AFIO_MAPR_TIM2_REMAP_FULLREMAP_Msk /*!< Full remap (CH1/ETR/PA15, CH2/PB3, CH3/PB10, CH4/PB11) */
+
+#define AFIO_MAPR_TIM3_REMAP_Pos (10U)
+#define AFIO_MAPR_TIM3_REMAP_Msk (0x3U << AFIO_MAPR_TIM3_REMAP_Pos) /*!< 0x00000C00 */
+#define AFIO_MAPR_TIM3_REMAP AFIO_MAPR_TIM3_REMAP_Msk /*!< TIM3_REMAP[1:0] bits (TIM3 remapping) */
+#define AFIO_MAPR_TIM3_REMAP_0 (0x1U << AFIO_MAPR_TIM3_REMAP_Pos) /*!< 0x00000400 */
+#define AFIO_MAPR_TIM3_REMAP_1 (0x2U << AFIO_MAPR_TIM3_REMAP_Pos) /*!< 0x00000800 */
+
+/*!< TIM3_REMAP configuration */
+#define AFIO_MAPR_TIM3_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1) */
+#define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Pos (11U)
+#define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Msk (0x1U << AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Pos) /*!< 0x00000800 */
+#define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Msk /*!< Partial remap (CH1/PB4, CH2/PB5, CH3/PB0, CH4/PB1) */
+#define AFIO_MAPR_TIM3_REMAP_FULLREMAP_Pos (10U)
+#define AFIO_MAPR_TIM3_REMAP_FULLREMAP_Msk (0x3U << AFIO_MAPR_TIM3_REMAP_FULLREMAP_Pos) /*!< 0x00000C00 */
+#define AFIO_MAPR_TIM3_REMAP_FULLREMAP AFIO_MAPR_TIM3_REMAP_FULLREMAP_Msk /*!< Full remap (CH1/PC6, CH2/PC7, CH3/PC8, CH4/PC9) */
+
+#define AFIO_MAPR_TIM4_REMAP_Pos (12U)
+#define AFIO_MAPR_TIM4_REMAP_Msk (0x1U << AFIO_MAPR_TIM4_REMAP_Pos) /*!< 0x00001000 */
+#define AFIO_MAPR_TIM4_REMAP AFIO_MAPR_TIM4_REMAP_Msk /*!< TIM4_REMAP bit (TIM4 remapping) */
+
+#define AFIO_MAPR_CAN_REMAP_Pos (13U)
+#define AFIO_MAPR_CAN_REMAP_Msk (0x3U << AFIO_MAPR_CAN_REMAP_Pos) /*!< 0x00006000 */
+#define AFIO_MAPR_CAN_REMAP AFIO_MAPR_CAN_REMAP_Msk /*!< CAN_REMAP[1:0] bits (CAN Alternate function remapping) */
+#define AFIO_MAPR_CAN_REMAP_0 (0x1U << AFIO_MAPR_CAN_REMAP_Pos) /*!< 0x00002000 */
+#define AFIO_MAPR_CAN_REMAP_1 (0x2U << AFIO_MAPR_CAN_REMAP_Pos) /*!< 0x00004000 */
+
+/*!< CAN_REMAP configuration */
+#define AFIO_MAPR_CAN_REMAP_REMAP1 ((uint32_t)0x00000000) /*!< CANRX mapped to PA11, CANTX mapped to PA12 */
+#define AFIO_MAPR_CAN_REMAP_REMAP2_Pos (14U)
+#define AFIO_MAPR_CAN_REMAP_REMAP2_Msk (0x1U << AFIO_MAPR_CAN_REMAP_REMAP2_Pos) /*!< 0x00004000 */
+#define AFIO_MAPR_CAN_REMAP_REMAP2 AFIO_MAPR_CAN_REMAP_REMAP2_Msk /*!< CANRX mapped to PB8, CANTX mapped to PB9 */
+#define AFIO_MAPR_CAN_REMAP_REMAP3_Pos (13U)
+#define AFIO_MAPR_CAN_REMAP_REMAP3_Msk (0x3U << AFIO_MAPR_CAN_REMAP_REMAP3_Pos) /*!< 0x00006000 */
+#define AFIO_MAPR_CAN_REMAP_REMAP3 AFIO_MAPR_CAN_REMAP_REMAP3_Msk /*!< CANRX mapped to PD0, CANTX mapped to PD1 */
+
+#define AFIO_MAPR_PD01_REMAP_Pos (15U)
+#define AFIO_MAPR_PD01_REMAP_Msk (0x1U << AFIO_MAPR_PD01_REMAP_Pos) /*!< 0x00008000 */
+#define AFIO_MAPR_PD01_REMAP AFIO_MAPR_PD01_REMAP_Msk /*!< Port D0/Port D1 mapping on OSC_IN/OSC_OUT */
+#define AFIO_MAPR_TIM5CH4_IREMAP_Pos (16U)
+#define AFIO_MAPR_TIM5CH4_IREMAP_Msk (0x1U << AFIO_MAPR_TIM5CH4_IREMAP_Pos) /*!< 0x00010000 */
+#define AFIO_MAPR_TIM5CH4_IREMAP AFIO_MAPR_TIM5CH4_IREMAP_Msk /*!< TIM5 Channel4 Internal Remap */
+#define AFIO_MAPR_ADC1_ETRGINJ_REMAP_Pos (17U)
+#define AFIO_MAPR_ADC1_ETRGINJ_REMAP_Msk (0x1U << AFIO_MAPR_ADC1_ETRGINJ_REMAP_Pos) /*!< 0x00020000 */
+#define AFIO_MAPR_ADC1_ETRGINJ_REMAP AFIO_MAPR_ADC1_ETRGINJ_REMAP_Msk /*!< ADC 1 External Trigger Injected Conversion remapping */
+#define AFIO_MAPR_ADC1_ETRGREG_REMAP_Pos (18U)
+#define AFIO_MAPR_ADC1_ETRGREG_REMAP_Msk (0x1U << AFIO_MAPR_ADC1_ETRGREG_REMAP_Pos) /*!< 0x00040000 */
+#define AFIO_MAPR_ADC1_ETRGREG_REMAP AFIO_MAPR_ADC1_ETRGREG_REMAP_Msk /*!< ADC 1 External Trigger Regular Conversion remapping */
+#define AFIO_MAPR_ADC2_ETRGINJ_REMAP_Pos (19U)
+#define AFIO_MAPR_ADC2_ETRGINJ_REMAP_Msk (0x1U << AFIO_MAPR_ADC2_ETRGINJ_REMAP_Pos) /*!< 0x00080000 */
+#define AFIO_MAPR_ADC2_ETRGINJ_REMAP AFIO_MAPR_ADC2_ETRGINJ_REMAP_Msk /*!< ADC 2 External Trigger Injected Conversion remapping */
+#define AFIO_MAPR_ADC2_ETRGREG_REMAP_Pos (20U)
+#define AFIO_MAPR_ADC2_ETRGREG_REMAP_Msk (0x1U << AFIO_MAPR_ADC2_ETRGREG_REMAP_Pos) /*!< 0x00100000 */
+#define AFIO_MAPR_ADC2_ETRGREG_REMAP AFIO_MAPR_ADC2_ETRGREG_REMAP_Msk /*!< ADC 2 External Trigger Regular Conversion remapping */
+
+/*!< SWJ_CFG configuration */
+#define AFIO_MAPR_SWJ_CFG_Pos (24U)
+#define AFIO_MAPR_SWJ_CFG_Msk (0x7U << AFIO_MAPR_SWJ_CFG_Pos) /*!< 0x07000000 */
+#define AFIO_MAPR_SWJ_CFG AFIO_MAPR_SWJ_CFG_Msk /*!< SWJ_CFG[2:0] bits (Serial Wire JTAG configuration) */
+#define AFIO_MAPR_SWJ_CFG_0 (0x1U << AFIO_MAPR_SWJ_CFG_Pos) /*!< 0x01000000 */
+#define AFIO_MAPR_SWJ_CFG_1 (0x2U << AFIO_MAPR_SWJ_CFG_Pos) /*!< 0x02000000 */
+#define AFIO_MAPR_SWJ_CFG_2 (0x4U << AFIO_MAPR_SWJ_CFG_Pos) /*!< 0x04000000 */
+
+#define AFIO_MAPR_SWJ_CFG_RESET ((uint32_t)0x00000000) /*!< Full SWJ (JTAG-DP + SW-DP) : Reset State */
+#define AFIO_MAPR_SWJ_CFG_NOJNTRST_Pos (24U)
+#define AFIO_MAPR_SWJ_CFG_NOJNTRST_Msk (0x1U << AFIO_MAPR_SWJ_CFG_NOJNTRST_Pos) /*!< 0x01000000 */
+#define AFIO_MAPR_SWJ_CFG_NOJNTRST AFIO_MAPR_SWJ_CFG_NOJNTRST_Msk /*!< Full SWJ (JTAG-DP + SW-DP) but without JNTRST */
+#define AFIO_MAPR_SWJ_CFG_JTAGDISABLE_Pos (25U)
+#define AFIO_MAPR_SWJ_CFG_JTAGDISABLE_Msk (0x1U << AFIO_MAPR_SWJ_CFG_JTAGDISABLE_Pos) /*!< 0x02000000 */
+#define AFIO_MAPR_SWJ_CFG_JTAGDISABLE AFIO_MAPR_SWJ_CFG_JTAGDISABLE_Msk /*!< JTAG-DP Disabled and SW-DP Enabled */
+#define AFIO_MAPR_SWJ_CFG_DISABLE_Pos (26U)
+#define AFIO_MAPR_SWJ_CFG_DISABLE_Msk (0x1U << AFIO_MAPR_SWJ_CFG_DISABLE_Pos) /*!< 0x04000000 */
+#define AFIO_MAPR_SWJ_CFG_DISABLE AFIO_MAPR_SWJ_CFG_DISABLE_Msk /*!< JTAG-DP Disabled and SW-DP Disabled */
+
+
+/***************** Bit definition for AFIO_EXTICR1 register *****************/
+#define AFIO_EXTICR1_EXTI0_Pos (0U)
+#define AFIO_EXTICR1_EXTI0_Msk (0xFU << AFIO_EXTICR1_EXTI0_Pos) /*!< 0x0000000F */
+#define AFIO_EXTICR1_EXTI0 AFIO_EXTICR1_EXTI0_Msk /*!< EXTI 0 configuration */
+#define AFIO_EXTICR1_EXTI1_Pos (4U)
+#define AFIO_EXTICR1_EXTI1_Msk (0xFU << AFIO_EXTICR1_EXTI1_Pos) /*!< 0x000000F0 */
+#define AFIO_EXTICR1_EXTI1 AFIO_EXTICR1_EXTI1_Msk /*!< EXTI 1 configuration */
+#define AFIO_EXTICR1_EXTI2_Pos (8U)
+#define AFIO_EXTICR1_EXTI2_Msk (0xFU << AFIO_EXTICR1_EXTI2_Pos) /*!< 0x00000F00 */
+#define AFIO_EXTICR1_EXTI2 AFIO_EXTICR1_EXTI2_Msk /*!< EXTI 2 configuration */
+#define AFIO_EXTICR1_EXTI3_Pos (12U)
+#define AFIO_EXTICR1_EXTI3_Msk (0xFU << AFIO_EXTICR1_EXTI3_Pos) /*!< 0x0000F000 */
+#define AFIO_EXTICR1_EXTI3 AFIO_EXTICR1_EXTI3_Msk /*!< EXTI 3 configuration */
+
+/*!< EXTI0 configuration */
+#define AFIO_EXTICR1_EXTI0_PA ((uint32_t)0x00000000) /*!< PA[0] pin */
+#define AFIO_EXTICR1_EXTI0_PB_Pos (0U)
+#define AFIO_EXTICR1_EXTI0_PB_Msk (0x1U << AFIO_EXTICR1_EXTI0_PB_Pos) /*!< 0x00000001 */
+#define AFIO_EXTICR1_EXTI0_PB AFIO_EXTICR1_EXTI0_PB_Msk /*!< PB[0] pin */
+#define AFIO_EXTICR1_EXTI0_PC_Pos (1U)
+#define AFIO_EXTICR1_EXTI0_PC_Msk (0x1U << AFIO_EXTICR1_EXTI0_PC_Pos) /*!< 0x00000002 */
+#define AFIO_EXTICR1_EXTI0_PC AFIO_EXTICR1_EXTI0_PC_Msk /*!< PC[0] pin */
+#define AFIO_EXTICR1_EXTI0_PD_Pos (0U)
+#define AFIO_EXTICR1_EXTI0_PD_Msk (0x3U << AFIO_EXTICR1_EXTI0_PD_Pos) /*!< 0x00000003 */
+#define AFIO_EXTICR1_EXTI0_PD AFIO_EXTICR1_EXTI0_PD_Msk /*!< PD[0] pin */
+#define AFIO_EXTICR1_EXTI0_PE_Pos (2U)
+#define AFIO_EXTICR1_EXTI0_PE_Msk (0x1U << AFIO_EXTICR1_EXTI0_PE_Pos) /*!< 0x00000004 */
+#define AFIO_EXTICR1_EXTI0_PE AFIO_EXTICR1_EXTI0_PE_Msk /*!< PE[0] pin */
+#define AFIO_EXTICR1_EXTI0_PF_Pos (0U)
+#define AFIO_EXTICR1_EXTI0_PF_Msk (0x5U << AFIO_EXTICR1_EXTI0_PF_Pos) /*!< 0x00000005 */
+#define AFIO_EXTICR1_EXTI0_PF AFIO_EXTICR1_EXTI0_PF_Msk /*!< PF[0] pin */
+#define AFIO_EXTICR1_EXTI0_PG_Pos (1U)
+#define AFIO_EXTICR1_EXTI0_PG_Msk (0x3U << AFIO_EXTICR1_EXTI0_PG_Pos) /*!< 0x00000006 */
+#define AFIO_EXTICR1_EXTI0_PG AFIO_EXTICR1_EXTI0_PG_Msk /*!< PG[0] pin */
+
+/*!< EXTI1 configuration */
+#define AFIO_EXTICR1_EXTI1_PA ((uint32_t)0x00000000) /*!< PA[1] pin */
+#define AFIO_EXTICR1_EXTI1_PB_Pos (4U)
+#define AFIO_EXTICR1_EXTI1_PB_Msk (0x1U << AFIO_EXTICR1_EXTI1_PB_Pos) /*!< 0x00000010 */
+#define AFIO_EXTICR1_EXTI1_PB AFIO_EXTICR1_EXTI1_PB_Msk /*!< PB[1] pin */
+#define AFIO_EXTICR1_EXTI1_PC_Pos (5U)
+#define AFIO_EXTICR1_EXTI1_PC_Msk (0x1U << AFIO_EXTICR1_EXTI1_PC_Pos) /*!< 0x00000020 */
+#define AFIO_EXTICR1_EXTI1_PC AFIO_EXTICR1_EXTI1_PC_Msk /*!< PC[1] pin */
+#define AFIO_EXTICR1_EXTI1_PD_Pos (4U)
+#define AFIO_EXTICR1_EXTI1_PD_Msk (0x3U << AFIO_EXTICR1_EXTI1_PD_Pos) /*!< 0x00000030 */
+#define AFIO_EXTICR1_EXTI1_PD AFIO_EXTICR1_EXTI1_PD_Msk /*!< PD[1] pin */
+#define AFIO_EXTICR1_EXTI1_PE_Pos (6U)
+#define AFIO_EXTICR1_EXTI1_PE_Msk (0x1U << AFIO_EXTICR1_EXTI1_PE_Pos) /*!< 0x00000040 */
+#define AFIO_EXTICR1_EXTI1_PE AFIO_EXTICR1_EXTI1_PE_Msk /*!< PE[1] pin */
+#define AFIO_EXTICR1_EXTI1_PF_Pos (4U)
+#define AFIO_EXTICR1_EXTI1_PF_Msk (0x5U << AFIO_EXTICR1_EXTI1_PF_Pos) /*!< 0x00000050 */
+#define AFIO_EXTICR1_EXTI1_PF AFIO_EXTICR1_EXTI1_PF_Msk /*!< PF[1] pin */
+#define AFIO_EXTICR1_EXTI1_PG_Pos (5U)
+#define AFIO_EXTICR1_EXTI1_PG_Msk (0x3U << AFIO_EXTICR1_EXTI1_PG_Pos) /*!< 0x00000060 */
+#define AFIO_EXTICR1_EXTI1_PG AFIO_EXTICR1_EXTI1_PG_Msk /*!< PG[1] pin */
+
+/*!< EXTI2 configuration */
+#define AFIO_EXTICR1_EXTI2_PA ((uint32_t)0x00000000) /*!< PA[2] pin */
+#define AFIO_EXTICR1_EXTI2_PB_Pos (8U)
+#define AFIO_EXTICR1_EXTI2_PB_Msk (0x1U << AFIO_EXTICR1_EXTI2_PB_Pos) /*!< 0x00000100 */
+#define AFIO_EXTICR1_EXTI2_PB AFIO_EXTICR1_EXTI2_PB_Msk /*!< PB[2] pin */
+#define AFIO_EXTICR1_EXTI2_PC_Pos (9U)
+#define AFIO_EXTICR1_EXTI2_PC_Msk (0x1U << AFIO_EXTICR1_EXTI2_PC_Pos) /*!< 0x00000200 */
+#define AFIO_EXTICR1_EXTI2_PC AFIO_EXTICR1_EXTI2_PC_Msk /*!< PC[2] pin */
+#define AFIO_EXTICR1_EXTI2_PD_Pos (8U)
+#define AFIO_EXTICR1_EXTI2_PD_Msk (0x3U << AFIO_EXTICR1_EXTI2_PD_Pos) /*!< 0x00000300 */
+#define AFIO_EXTICR1_EXTI2_PD AFIO_EXTICR1_EXTI2_PD_Msk /*!< PD[2] pin */
+#define AFIO_EXTICR1_EXTI2_PE_Pos (10U)
+#define AFIO_EXTICR1_EXTI2_PE_Msk (0x1U << AFIO_EXTICR1_EXTI2_PE_Pos) /*!< 0x00000400 */
+#define AFIO_EXTICR1_EXTI2_PE AFIO_EXTICR1_EXTI2_PE_Msk /*!< PE[2] pin */
+#define AFIO_EXTICR1_EXTI2_PF_Pos (8U)
+#define AFIO_EXTICR1_EXTI2_PF_Msk (0x5U << AFIO_EXTICR1_EXTI2_PF_Pos) /*!< 0x00000500 */
+#define AFIO_EXTICR1_EXTI2_PF AFIO_EXTICR1_EXTI2_PF_Msk /*!< PF[2] pin */
+#define AFIO_EXTICR1_EXTI2_PG_Pos (9U)
+#define AFIO_EXTICR1_EXTI2_PG_Msk (0x3U << AFIO_EXTICR1_EXTI2_PG_Pos) /*!< 0x00000600 */
+#define AFIO_EXTICR1_EXTI2_PG AFIO_EXTICR1_EXTI2_PG_Msk /*!< PG[2] pin */
+
+/*!< EXTI3 configuration */
+#define AFIO_EXTICR1_EXTI3_PA ((uint32_t)0x00000000) /*!< PA[3] pin */
+#define AFIO_EXTICR1_EXTI3_PB_Pos (12U)
+#define AFIO_EXTICR1_EXTI3_PB_Msk (0x1U << AFIO_EXTICR1_EXTI3_PB_Pos) /*!< 0x00001000 */
+#define AFIO_EXTICR1_EXTI3_PB AFIO_EXTICR1_EXTI3_PB_Msk /*!< PB[3] pin */
+#define AFIO_EXTICR1_EXTI3_PC_Pos (13U)
+#define AFIO_EXTICR1_EXTI3_PC_Msk (0x1U << AFIO_EXTICR1_EXTI3_PC_Pos) /*!< 0x00002000 */
+#define AFIO_EXTICR1_EXTI3_PC AFIO_EXTICR1_EXTI3_PC_Msk /*!< PC[3] pin */
+#define AFIO_EXTICR1_EXTI3_PD_Pos (12U)
+#define AFIO_EXTICR1_EXTI3_PD_Msk (0x3U << AFIO_EXTICR1_EXTI3_PD_Pos) /*!< 0x00003000 */
+#define AFIO_EXTICR1_EXTI3_PD AFIO_EXTICR1_EXTI3_PD_Msk /*!< PD[3] pin */
+#define AFIO_EXTICR1_EXTI3_PE_Pos (14U)
+#define AFIO_EXTICR1_EXTI3_PE_Msk (0x1U << AFIO_EXTICR1_EXTI3_PE_Pos) /*!< 0x00004000 */
+#define AFIO_EXTICR1_EXTI3_PE AFIO_EXTICR1_EXTI3_PE_Msk /*!< PE[3] pin */
+#define AFIO_EXTICR1_EXTI3_PF_Pos (12U)
+#define AFIO_EXTICR1_EXTI3_PF_Msk (0x5U << AFIO_EXTICR1_EXTI3_PF_Pos) /*!< 0x00005000 */
+#define AFIO_EXTICR1_EXTI3_PF AFIO_EXTICR1_EXTI3_PF_Msk /*!< PF[3] pin */
+#define AFIO_EXTICR1_EXTI3_PG_Pos (13U)
+#define AFIO_EXTICR1_EXTI3_PG_Msk (0x3U << AFIO_EXTICR1_EXTI3_PG_Pos) /*!< 0x00006000 */
+#define AFIO_EXTICR1_EXTI3_PG AFIO_EXTICR1_EXTI3_PG_Msk /*!< PG[3] pin */
+
+/***************** Bit definition for AFIO_EXTICR2 register *****************/
+#define AFIO_EXTICR2_EXTI4_Pos (0U)
+#define AFIO_EXTICR2_EXTI4_Msk (0xFU << AFIO_EXTICR2_EXTI4_Pos) /*!< 0x0000000F */
+#define AFIO_EXTICR2_EXTI4 AFIO_EXTICR2_EXTI4_Msk /*!< EXTI 4 configuration */
+#define AFIO_EXTICR2_EXTI5_Pos (4U)
+#define AFIO_EXTICR2_EXTI5_Msk (0xFU << AFIO_EXTICR2_EXTI5_Pos) /*!< 0x000000F0 */
+#define AFIO_EXTICR2_EXTI5 AFIO_EXTICR2_EXTI5_Msk /*!< EXTI 5 configuration */
+#define AFIO_EXTICR2_EXTI6_Pos (8U)
+#define AFIO_EXTICR2_EXTI6_Msk (0xFU << AFIO_EXTICR2_EXTI6_Pos) /*!< 0x00000F00 */
+#define AFIO_EXTICR2_EXTI6 AFIO_EXTICR2_EXTI6_Msk /*!< EXTI 6 configuration */
+#define AFIO_EXTICR2_EXTI7_Pos (12U)
+#define AFIO_EXTICR2_EXTI7_Msk (0xFU << AFIO_EXTICR2_EXTI7_Pos) /*!< 0x0000F000 */
+#define AFIO_EXTICR2_EXTI7 AFIO_EXTICR2_EXTI7_Msk /*!< EXTI 7 configuration */
+
+/*!< EXTI4 configuration */
+#define AFIO_EXTICR2_EXTI4_PA ((uint32_t)0x00000000) /*!< PA[4] pin */
+#define AFIO_EXTICR2_EXTI4_PB_Pos (0U)
+#define AFIO_EXTICR2_EXTI4_PB_Msk (0x1U << AFIO_EXTICR2_EXTI4_PB_Pos) /*!< 0x00000001 */
+#define AFIO_EXTICR2_EXTI4_PB AFIO_EXTICR2_EXTI4_PB_Msk /*!< PB[4] pin */
+#define AFIO_EXTICR2_EXTI4_PC_Pos (1U)
+#define AFIO_EXTICR2_EXTI4_PC_Msk (0x1U << AFIO_EXTICR2_EXTI4_PC_Pos) /*!< 0x00000002 */
+#define AFIO_EXTICR2_EXTI4_PC AFIO_EXTICR2_EXTI4_PC_Msk /*!< PC[4] pin */
+#define AFIO_EXTICR2_EXTI4_PD_Pos (0U)
+#define AFIO_EXTICR2_EXTI4_PD_Msk (0x3U << AFIO_EXTICR2_EXTI4_PD_Pos) /*!< 0x00000003 */
+#define AFIO_EXTICR2_EXTI4_PD AFIO_EXTICR2_EXTI4_PD_Msk /*!< PD[4] pin */
+#define AFIO_EXTICR2_EXTI4_PE_Pos (2U)
+#define AFIO_EXTICR2_EXTI4_PE_Msk (0x1U << AFIO_EXTICR2_EXTI4_PE_Pos) /*!< 0x00000004 */
+#define AFIO_EXTICR2_EXTI4_PE AFIO_EXTICR2_EXTI4_PE_Msk /*!< PE[4] pin */
+#define AFIO_EXTICR2_EXTI4_PF_Pos (0U)
+#define AFIO_EXTICR2_EXTI4_PF_Msk (0x5U << AFIO_EXTICR2_EXTI4_PF_Pos) /*!< 0x00000005 */
+#define AFIO_EXTICR2_EXTI4_PF AFIO_EXTICR2_EXTI4_PF_Msk /*!< PF[4] pin */
+#define AFIO_EXTICR2_EXTI4_PG_Pos (1U)
+#define AFIO_EXTICR2_EXTI4_PG_Msk (0x3U << AFIO_EXTICR2_EXTI4_PG_Pos) /*!< 0x00000006 */
+#define AFIO_EXTICR2_EXTI4_PG AFIO_EXTICR2_EXTI4_PG_Msk /*!< PG[4] pin */
+
+/* EXTI5 configuration */
+#define AFIO_EXTICR2_EXTI5_PA ((uint32_t)0x00000000) /*!< PA[5] pin */
+#define AFIO_EXTICR2_EXTI5_PB_Pos (4U)
+#define AFIO_EXTICR2_EXTI5_PB_Msk (0x1U << AFIO_EXTICR2_EXTI5_PB_Pos) /*!< 0x00000010 */
+#define AFIO_EXTICR2_EXTI5_PB AFIO_EXTICR2_EXTI5_PB_Msk /*!< PB[5] pin */
+#define AFIO_EXTICR2_EXTI5_PC_Pos (5U)
+#define AFIO_EXTICR2_EXTI5_PC_Msk (0x1U << AFIO_EXTICR2_EXTI5_PC_Pos) /*!< 0x00000020 */
+#define AFIO_EXTICR2_EXTI5_PC AFIO_EXTICR2_EXTI5_PC_Msk /*!< PC[5] pin */
+#define AFIO_EXTICR2_EXTI5_PD_Pos (4U)
+#define AFIO_EXTICR2_EXTI5_PD_Msk (0x3U << AFIO_EXTICR2_EXTI5_PD_Pos) /*!< 0x00000030 */
+#define AFIO_EXTICR2_EXTI5_PD AFIO_EXTICR2_EXTI5_PD_Msk /*!< PD[5] pin */
+#define AFIO_EXTICR2_EXTI5_PE_Pos (6U)
+#define AFIO_EXTICR2_EXTI5_PE_Msk (0x1U << AFIO_EXTICR2_EXTI5_PE_Pos) /*!< 0x00000040 */
+#define AFIO_EXTICR2_EXTI5_PE AFIO_EXTICR2_EXTI5_PE_Msk /*!< PE[5] pin */
+#define AFIO_EXTICR2_EXTI5_PF_Pos (4U)
+#define AFIO_EXTICR2_EXTI5_PF_Msk (0x5U << AFIO_EXTICR2_EXTI5_PF_Pos) /*!< 0x00000050 */
+#define AFIO_EXTICR2_EXTI5_PF AFIO_EXTICR2_EXTI5_PF_Msk /*!< PF[5] pin */
+#define AFIO_EXTICR2_EXTI5_PG_Pos (5U)
+#define AFIO_EXTICR2_EXTI5_PG_Msk (0x3U << AFIO_EXTICR2_EXTI5_PG_Pos) /*!< 0x00000060 */
+#define AFIO_EXTICR2_EXTI5_PG AFIO_EXTICR2_EXTI5_PG_Msk /*!< PG[5] pin */
+
+/*!< EXTI6 configuration */
+#define AFIO_EXTICR2_EXTI6_PA ((uint32_t)0x00000000) /*!< PA[6] pin */
+#define AFIO_EXTICR2_EXTI6_PB_Pos (8U)
+#define AFIO_EXTICR2_EXTI6_PB_Msk (0x1U << AFIO_EXTICR2_EXTI6_PB_Pos) /*!< 0x00000100 */
+#define AFIO_EXTICR2_EXTI6_PB AFIO_EXTICR2_EXTI6_PB_Msk /*!< PB[6] pin */
+#define AFIO_EXTICR2_EXTI6_PC_Pos (9U)
+#define AFIO_EXTICR2_EXTI6_PC_Msk (0x1U << AFIO_EXTICR2_EXTI6_PC_Pos) /*!< 0x00000200 */
+#define AFIO_EXTICR2_EXTI6_PC AFIO_EXTICR2_EXTI6_PC_Msk /*!< PC[6] pin */
+#define AFIO_EXTICR2_EXTI6_PD_Pos (8U)
+#define AFIO_EXTICR2_EXTI6_PD_Msk (0x3U << AFIO_EXTICR2_EXTI6_PD_Pos) /*!< 0x00000300 */
+#define AFIO_EXTICR2_EXTI6_PD AFIO_EXTICR2_EXTI6_PD_Msk /*!< PD[6] pin */
+#define AFIO_EXTICR2_EXTI6_PE_Pos (10U)
+#define AFIO_EXTICR2_EXTI6_PE_Msk (0x1U << AFIO_EXTICR2_EXTI6_PE_Pos) /*!< 0x00000400 */
+#define AFIO_EXTICR2_EXTI6_PE AFIO_EXTICR2_EXTI6_PE_Msk /*!< PE[6] pin */
+#define AFIO_EXTICR2_EXTI6_PF_Pos (8U)
+#define AFIO_EXTICR2_EXTI6_PF_Msk (0x5U << AFIO_EXTICR2_EXTI6_PF_Pos) /*!< 0x00000500 */
+#define AFIO_EXTICR2_EXTI6_PF AFIO_EXTICR2_EXTI6_PF_Msk /*!< PF[6] pin */
+#define AFIO_EXTICR2_EXTI6_PG_Pos (9U)
+#define AFIO_EXTICR2_EXTI6_PG_Msk (0x3U << AFIO_EXTICR2_EXTI6_PG_Pos) /*!< 0x00000600 */
+#define AFIO_EXTICR2_EXTI6_PG AFIO_EXTICR2_EXTI6_PG_Msk /*!< PG[6] pin */
+
+/*!< EXTI7 configuration */
+#define AFIO_EXTICR2_EXTI7_PA ((uint32_t)0x00000000) /*!< PA[7] pin */
+#define AFIO_EXTICR2_EXTI7_PB_Pos (12U)
+#define AFIO_EXTICR2_EXTI7_PB_Msk (0x1U << AFIO_EXTICR2_EXTI7_PB_Pos) /*!< 0x00001000 */
+#define AFIO_EXTICR2_EXTI7_PB AFIO_EXTICR2_EXTI7_PB_Msk /*!< PB[7] pin */
+#define AFIO_EXTICR2_EXTI7_PC_Pos (13U)
+#define AFIO_EXTICR2_EXTI7_PC_Msk (0x1U << AFIO_EXTICR2_EXTI7_PC_Pos) /*!< 0x00002000 */
+#define AFIO_EXTICR2_EXTI7_PC AFIO_EXTICR2_EXTI7_PC_Msk /*!< PC[7] pin */
+#define AFIO_EXTICR2_EXTI7_PD_Pos (12U)
+#define AFIO_EXTICR2_EXTI7_PD_Msk (0x3U << AFIO_EXTICR2_EXTI7_PD_Pos) /*!< 0x00003000 */
+#define AFIO_EXTICR2_EXTI7_PD AFIO_EXTICR2_EXTI7_PD_Msk /*!< PD[7] pin */
+#define AFIO_EXTICR2_EXTI7_PE_Pos (14U)
+#define AFIO_EXTICR2_EXTI7_PE_Msk (0x1U << AFIO_EXTICR2_EXTI7_PE_Pos) /*!< 0x00004000 */
+#define AFIO_EXTICR2_EXTI7_PE AFIO_EXTICR2_EXTI7_PE_Msk /*!< PE[7] pin */
+#define AFIO_EXTICR2_EXTI7_PF_Pos (12U)
+#define AFIO_EXTICR2_EXTI7_PF_Msk (0x5U << AFIO_EXTICR2_EXTI7_PF_Pos) /*!< 0x00005000 */
+#define AFIO_EXTICR2_EXTI7_PF AFIO_EXTICR2_EXTI7_PF_Msk /*!< PF[7] pin */
+#define AFIO_EXTICR2_EXTI7_PG_Pos (13U)
+#define AFIO_EXTICR2_EXTI7_PG_Msk (0x3U << AFIO_EXTICR2_EXTI7_PG_Pos) /*!< 0x00006000 */
+#define AFIO_EXTICR2_EXTI7_PG AFIO_EXTICR2_EXTI7_PG_Msk /*!< PG[7] pin */
+
+/***************** Bit definition for AFIO_EXTICR3 register *****************/
+#define AFIO_EXTICR3_EXTI8_Pos (0U)
+#define AFIO_EXTICR3_EXTI8_Msk (0xFU << AFIO_EXTICR3_EXTI8_Pos) /*!< 0x0000000F */
+#define AFIO_EXTICR3_EXTI8 AFIO_EXTICR3_EXTI8_Msk /*!< EXTI 8 configuration */
+#define AFIO_EXTICR3_EXTI9_Pos (4U)
+#define AFIO_EXTICR3_EXTI9_Msk (0xFU << AFIO_EXTICR3_EXTI9_Pos) /*!< 0x000000F0 */
+#define AFIO_EXTICR3_EXTI9 AFIO_EXTICR3_EXTI9_Msk /*!< EXTI 9 configuration */
+#define AFIO_EXTICR3_EXTI10_Pos (8U)
+#define AFIO_EXTICR3_EXTI10_Msk (0xFU << AFIO_EXTICR3_EXTI10_Pos) /*!< 0x00000F00 */
+#define AFIO_EXTICR3_EXTI10 AFIO_EXTICR3_EXTI10_Msk /*!< EXTI 10 configuration */
+#define AFIO_EXTICR3_EXTI11_Pos (12U)
+#define AFIO_EXTICR3_EXTI11_Msk (0xFU << AFIO_EXTICR3_EXTI11_Pos) /*!< 0x0000F000 */
+#define AFIO_EXTICR3_EXTI11 AFIO_EXTICR3_EXTI11_Msk /*!< EXTI 11 configuration */
+
+/*!< EXTI8 configuration */
+#define AFIO_EXTICR3_EXTI8_PA ((uint32_t)0x00000000) /*!< PA[8] pin */
+#define AFIO_EXTICR3_EXTI8_PB_Pos (0U)
+#define AFIO_EXTICR3_EXTI8_PB_Msk (0x1U << AFIO_EXTICR3_EXTI8_PB_Pos) /*!< 0x00000001 */
+#define AFIO_EXTICR3_EXTI8_PB AFIO_EXTICR3_EXTI8_PB_Msk /*!< PB[8] pin */
+#define AFIO_EXTICR3_EXTI8_PC_Pos (1U)
+#define AFIO_EXTICR3_EXTI8_PC_Msk (0x1U << AFIO_EXTICR3_EXTI8_PC_Pos) /*!< 0x00000002 */
+#define AFIO_EXTICR3_EXTI8_PC AFIO_EXTICR3_EXTI8_PC_Msk /*!< PC[8] pin */
+#define AFIO_EXTICR3_EXTI8_PD_Pos (0U)
+#define AFIO_EXTICR3_EXTI8_PD_Msk (0x3U << AFIO_EXTICR3_EXTI8_PD_Pos) /*!< 0x00000003 */
+#define AFIO_EXTICR3_EXTI8_PD AFIO_EXTICR3_EXTI8_PD_Msk /*!< PD[8] pin */
+#define AFIO_EXTICR3_EXTI8_PE_Pos (2U)
+#define AFIO_EXTICR3_EXTI8_PE_Msk (0x1U << AFIO_EXTICR3_EXTI8_PE_Pos) /*!< 0x00000004 */
+#define AFIO_EXTICR3_EXTI8_PE AFIO_EXTICR3_EXTI8_PE_Msk /*!< PE[8] pin */
+#define AFIO_EXTICR3_EXTI8_PF_Pos (0U)
+#define AFIO_EXTICR3_EXTI8_PF_Msk (0x5U << AFIO_EXTICR3_EXTI8_PF_Pos) /*!< 0x00000005 */
+#define AFIO_EXTICR3_EXTI8_PF AFIO_EXTICR3_EXTI8_PF_Msk /*!< PF[8] pin */
+#define AFIO_EXTICR3_EXTI8_PG_Pos (1U)
+#define AFIO_EXTICR3_EXTI8_PG_Msk (0x3U << AFIO_EXTICR3_EXTI8_PG_Pos) /*!< 0x00000006 */
+#define AFIO_EXTICR3_EXTI8_PG AFIO_EXTICR3_EXTI8_PG_Msk /*!< PG[8] pin */
+
+/*!< EXTI9 configuration */
+#define AFIO_EXTICR3_EXTI9_PA ((uint32_t)0x00000000) /*!< PA[9] pin */
+#define AFIO_EXTICR3_EXTI9_PB_Pos (4U)
+#define AFIO_EXTICR3_EXTI9_PB_Msk (0x1U << AFIO_EXTICR3_EXTI9_PB_Pos) /*!< 0x00000010 */
+#define AFIO_EXTICR3_EXTI9_PB AFIO_EXTICR3_EXTI9_PB_Msk /*!< PB[9] pin */
+#define AFIO_EXTICR3_EXTI9_PC_Pos (5U)
+#define AFIO_EXTICR3_EXTI9_PC_Msk (0x1U << AFIO_EXTICR3_EXTI9_PC_Pos) /*!< 0x00000020 */
+#define AFIO_EXTICR3_EXTI9_PC AFIO_EXTICR3_EXTI9_PC_Msk /*!< PC[9] pin */
+#define AFIO_EXTICR3_EXTI9_PD_Pos (4U)
+#define AFIO_EXTICR3_EXTI9_PD_Msk (0x3U << AFIO_EXTICR3_EXTI9_PD_Pos) /*!< 0x00000030 */
+#define AFIO_EXTICR3_EXTI9_PD AFIO_EXTICR3_EXTI9_PD_Msk /*!< PD[9] pin */
+#define AFIO_EXTICR3_EXTI9_PE_Pos (6U)
+#define AFIO_EXTICR3_EXTI9_PE_Msk (0x1U << AFIO_EXTICR3_EXTI9_PE_Pos) /*!< 0x00000040 */
+#define AFIO_EXTICR3_EXTI9_PE AFIO_EXTICR3_EXTI9_PE_Msk /*!< PE[9] pin */
+#define AFIO_EXTICR3_EXTI9_PF_Pos (4U)
+#define AFIO_EXTICR3_EXTI9_PF_Msk (0x5U << AFIO_EXTICR3_EXTI9_PF_Pos) /*!< 0x00000050 */
+#define AFIO_EXTICR3_EXTI9_PF AFIO_EXTICR3_EXTI9_PF_Msk /*!< PF[9] pin */
+#define AFIO_EXTICR3_EXTI9_PG_Pos (5U)
+#define AFIO_EXTICR3_EXTI9_PG_Msk (0x3U << AFIO_EXTICR3_EXTI9_PG_Pos) /*!< 0x00000060 */
+#define AFIO_EXTICR3_EXTI9_PG AFIO_EXTICR3_EXTI9_PG_Msk /*!< PG[9] pin */
+
+/*!< EXTI10 configuration */
+#define AFIO_EXTICR3_EXTI10_PA ((uint32_t)0x00000000) /*!< PA[10] pin */
+#define AFIO_EXTICR3_EXTI10_PB_Pos (8U)
+#define AFIO_EXTICR3_EXTI10_PB_Msk (0x1U << AFIO_EXTICR3_EXTI10_PB_Pos) /*!< 0x00000100 */
+#define AFIO_EXTICR3_EXTI10_PB AFIO_EXTICR3_EXTI10_PB_Msk /*!< PB[10] pin */
+#define AFIO_EXTICR3_EXTI10_PC_Pos (9U)
+#define AFIO_EXTICR3_EXTI10_PC_Msk (0x1U << AFIO_EXTICR3_EXTI10_PC_Pos) /*!< 0x00000200 */
+#define AFIO_EXTICR3_EXTI10_PC AFIO_EXTICR3_EXTI10_PC_Msk /*!< PC[10] pin */
+#define AFIO_EXTICR3_EXTI10_PD_Pos (8U)
+#define AFIO_EXTICR3_EXTI10_PD_Msk (0x3U << AFIO_EXTICR3_EXTI10_PD_Pos) /*!< 0x00000300 */
+#define AFIO_EXTICR3_EXTI10_PD AFIO_EXTICR3_EXTI10_PD_Msk /*!< PD[10] pin */
+#define AFIO_EXTICR3_EXTI10_PE_Pos (10U)
+#define AFIO_EXTICR3_EXTI10_PE_Msk (0x1U << AFIO_EXTICR3_EXTI10_PE_Pos) /*!< 0x00000400 */
+#define AFIO_EXTICR3_EXTI10_PE AFIO_EXTICR3_EXTI10_PE_Msk /*!< PE[10] pin */
+#define AFIO_EXTICR3_EXTI10_PF_Pos (8U)
+#define AFIO_EXTICR3_EXTI10_PF_Msk (0x5U << AFIO_EXTICR3_EXTI10_PF_Pos) /*!< 0x00000500 */
+#define AFIO_EXTICR3_EXTI10_PF AFIO_EXTICR3_EXTI10_PF_Msk /*!< PF[10] pin */
+#define AFIO_EXTICR3_EXTI10_PG_Pos (9U)
+#define AFIO_EXTICR3_EXTI10_PG_Msk (0x3U << AFIO_EXTICR3_EXTI10_PG_Pos) /*!< 0x00000600 */
+#define AFIO_EXTICR3_EXTI10_PG AFIO_EXTICR3_EXTI10_PG_Msk /*!< PG[10] pin */
+
+/*!< EXTI11 configuration */
+#define AFIO_EXTICR3_EXTI11_PA ((uint32_t)0x00000000) /*!< PA[11] pin */
+#define AFIO_EXTICR3_EXTI11_PB_Pos (12U)
+#define AFIO_EXTICR3_EXTI11_PB_Msk (0x1U << AFIO_EXTICR3_EXTI11_PB_Pos) /*!< 0x00001000 */
+#define AFIO_EXTICR3_EXTI11_PB AFIO_EXTICR3_EXTI11_PB_Msk /*!< PB[11] pin */
+#define AFIO_EXTICR3_EXTI11_PC_Pos (13U)
+#define AFIO_EXTICR3_EXTI11_PC_Msk (0x1U << AFIO_EXTICR3_EXTI11_PC_Pos) /*!< 0x00002000 */
+#define AFIO_EXTICR3_EXTI11_PC AFIO_EXTICR3_EXTI11_PC_Msk /*!< PC[11] pin */
+#define AFIO_EXTICR3_EXTI11_PD_Pos (12U)
+#define AFIO_EXTICR3_EXTI11_PD_Msk (0x3U << AFIO_EXTICR3_EXTI11_PD_Pos) /*!< 0x00003000 */
+#define AFIO_EXTICR3_EXTI11_PD AFIO_EXTICR3_EXTI11_PD_Msk /*!< PD[11] pin */
+#define AFIO_EXTICR3_EXTI11_PE_Pos (14U)
+#define AFIO_EXTICR3_EXTI11_PE_Msk (0x1U << AFIO_EXTICR3_EXTI11_PE_Pos) /*!< 0x00004000 */
+#define AFIO_EXTICR3_EXTI11_PE AFIO_EXTICR3_EXTI11_PE_Msk /*!< PE[11] pin */
+#define AFIO_EXTICR3_EXTI11_PF_Pos (12U)
+#define AFIO_EXTICR3_EXTI11_PF_Msk (0x5U << AFIO_EXTICR3_EXTI11_PF_Pos) /*!< 0x00005000 */
+#define AFIO_EXTICR3_EXTI11_PF AFIO_EXTICR3_EXTI11_PF_Msk /*!< PF[11] pin */
+#define AFIO_EXTICR3_EXTI11_PG_Pos (13U)
+#define AFIO_EXTICR3_EXTI11_PG_Msk (0x3U << AFIO_EXTICR3_EXTI11_PG_Pos) /*!< 0x00006000 */
+#define AFIO_EXTICR3_EXTI11_PG AFIO_EXTICR3_EXTI11_PG_Msk /*!< PG[11] pin */
+
+/***************** Bit definition for AFIO_EXTICR4 register *****************/
+#define AFIO_EXTICR4_EXTI12_Pos (0U)
+#define AFIO_EXTICR4_EXTI12_Msk (0xFU << AFIO_EXTICR4_EXTI12_Pos) /*!< 0x0000000F */
+#define AFIO_EXTICR4_EXTI12 AFIO_EXTICR4_EXTI12_Msk /*!< EXTI 12 configuration */
+#define AFIO_EXTICR4_EXTI13_Pos (4U)
+#define AFIO_EXTICR4_EXTI13_Msk (0xFU << AFIO_EXTICR4_EXTI13_Pos) /*!< 0x000000F0 */
+#define AFIO_EXTICR4_EXTI13 AFIO_EXTICR4_EXTI13_Msk /*!< EXTI 13 configuration */
+#define AFIO_EXTICR4_EXTI14_Pos (8U)
+#define AFIO_EXTICR4_EXTI14_Msk (0xFU << AFIO_EXTICR4_EXTI14_Pos) /*!< 0x00000F00 */
+#define AFIO_EXTICR4_EXTI14 AFIO_EXTICR4_EXTI14_Msk /*!< EXTI 14 configuration */
+#define AFIO_EXTICR4_EXTI15_Pos (12U)
+#define AFIO_EXTICR4_EXTI15_Msk (0xFU << AFIO_EXTICR4_EXTI15_Pos) /*!< 0x0000F000 */
+#define AFIO_EXTICR4_EXTI15 AFIO_EXTICR4_EXTI15_Msk /*!< EXTI 15 configuration */
+
+/* EXTI12 configuration */
+#define AFIO_EXTICR4_EXTI12_PA ((uint32_t)0x00000000) /*!< PA[12] pin */
+#define AFIO_EXTICR4_EXTI12_PB_Pos (0U)
+#define AFIO_EXTICR4_EXTI12_PB_Msk (0x1U << AFIO_EXTICR4_EXTI12_PB_Pos) /*!< 0x00000001 */
+#define AFIO_EXTICR4_EXTI12_PB AFIO_EXTICR4_EXTI12_PB_Msk /*!< PB[12] pin */
+#define AFIO_EXTICR4_EXTI12_PC_Pos (1U)
+#define AFIO_EXTICR4_EXTI12_PC_Msk (0x1U << AFIO_EXTICR4_EXTI12_PC_Pos) /*!< 0x00000002 */
+#define AFIO_EXTICR4_EXTI12_PC AFIO_EXTICR4_EXTI12_PC_Msk /*!< PC[12] pin */
+#define AFIO_EXTICR4_EXTI12_PD_Pos (0U)
+#define AFIO_EXTICR4_EXTI12_PD_Msk (0x3U << AFIO_EXTICR4_EXTI12_PD_Pos) /*!< 0x00000003 */
+#define AFIO_EXTICR4_EXTI12_PD AFIO_EXTICR4_EXTI12_PD_Msk /*!< PD[12] pin */
+#define AFIO_EXTICR4_EXTI12_PE_Pos (2U)
+#define AFIO_EXTICR4_EXTI12_PE_Msk (0x1U << AFIO_EXTICR4_EXTI12_PE_Pos) /*!< 0x00000004 */
+#define AFIO_EXTICR4_EXTI12_PE AFIO_EXTICR4_EXTI12_PE_Msk /*!< PE[12] pin */
+#define AFIO_EXTICR4_EXTI12_PF_Pos (0U)
+#define AFIO_EXTICR4_EXTI12_PF_Msk (0x5U << AFIO_EXTICR4_EXTI12_PF_Pos) /*!< 0x00000005 */
+#define AFIO_EXTICR4_EXTI12_PF AFIO_EXTICR4_EXTI12_PF_Msk /*!< PF[12] pin */
+#define AFIO_EXTICR4_EXTI12_PG_Pos (1U)
+#define AFIO_EXTICR4_EXTI12_PG_Msk (0x3U << AFIO_EXTICR4_EXTI12_PG_Pos) /*!< 0x00000006 */
+#define AFIO_EXTICR4_EXTI12_PG AFIO_EXTICR4_EXTI12_PG_Msk /*!< PG[12] pin */
+
+/* EXTI13 configuration */
+#define AFIO_EXTICR4_EXTI13_PA ((uint32_t)0x00000000) /*!< PA[13] pin */
+#define AFIO_EXTICR4_EXTI13_PB_Pos (4U)
+#define AFIO_EXTICR4_EXTI13_PB_Msk (0x1U << AFIO_EXTICR4_EXTI13_PB_Pos) /*!< 0x00000010 */
+#define AFIO_EXTICR4_EXTI13_PB AFIO_EXTICR4_EXTI13_PB_Msk /*!< PB[13] pin */
+#define AFIO_EXTICR4_EXTI13_PC_Pos (5U)
+#define AFIO_EXTICR4_EXTI13_PC_Msk (0x1U << AFIO_EXTICR4_EXTI13_PC_Pos) /*!< 0x00000020 */
+#define AFIO_EXTICR4_EXTI13_PC AFIO_EXTICR4_EXTI13_PC_Msk /*!< PC[13] pin */
+#define AFIO_EXTICR4_EXTI13_PD_Pos (4U)
+#define AFIO_EXTICR4_EXTI13_PD_Msk (0x3U << AFIO_EXTICR4_EXTI13_PD_Pos) /*!< 0x00000030 */
+#define AFIO_EXTICR4_EXTI13_PD AFIO_EXTICR4_EXTI13_PD_Msk /*!< PD[13] pin */
+#define AFIO_EXTICR4_EXTI13_PE_Pos (6U)
+#define AFIO_EXTICR4_EXTI13_PE_Msk (0x1U << AFIO_EXTICR4_EXTI13_PE_Pos) /*!< 0x00000040 */
+#define AFIO_EXTICR4_EXTI13_PE AFIO_EXTICR4_EXTI13_PE_Msk /*!< PE[13] pin */
+#define AFIO_EXTICR4_EXTI13_PF_Pos (4U)
+#define AFIO_EXTICR4_EXTI13_PF_Msk (0x5U << AFIO_EXTICR4_EXTI13_PF_Pos) /*!< 0x00000050 */
+#define AFIO_EXTICR4_EXTI13_PF AFIO_EXTICR4_EXTI13_PF_Msk /*!< PF[13] pin */
+#define AFIO_EXTICR4_EXTI13_PG_Pos (5U)
+#define AFIO_EXTICR4_EXTI13_PG_Msk (0x3U << AFIO_EXTICR4_EXTI13_PG_Pos) /*!< 0x00000060 */
+#define AFIO_EXTICR4_EXTI13_PG AFIO_EXTICR4_EXTI13_PG_Msk /*!< PG[13] pin */
+
+/*!< EXTI14 configuration */
+#define AFIO_EXTICR4_EXTI14_PA ((uint32_t)0x00000000) /*!< PA[14] pin */
+#define AFIO_EXTICR4_EXTI14_PB_Pos (8U)
+#define AFIO_EXTICR4_EXTI14_PB_Msk (0x1U << AFIO_EXTICR4_EXTI14_PB_Pos) /*!< 0x00000100 */
+#define AFIO_EXTICR4_EXTI14_PB AFIO_EXTICR4_EXTI14_PB_Msk /*!< PB[14] pin */
+#define AFIO_EXTICR4_EXTI14_PC_Pos (9U)
+#define AFIO_EXTICR4_EXTI14_PC_Msk (0x1U << AFIO_EXTICR4_EXTI14_PC_Pos) /*!< 0x00000200 */
+#define AFIO_EXTICR4_EXTI14_PC AFIO_EXTICR4_EXTI14_PC_Msk /*!< PC[14] pin */
+#define AFIO_EXTICR4_EXTI14_PD_Pos (8U)
+#define AFIO_EXTICR4_EXTI14_PD_Msk (0x3U << AFIO_EXTICR4_EXTI14_PD_Pos) /*!< 0x00000300 */
+#define AFIO_EXTICR4_EXTI14_PD AFIO_EXTICR4_EXTI14_PD_Msk /*!< PD[14] pin */
+#define AFIO_EXTICR4_EXTI14_PE_Pos (10U)
+#define AFIO_EXTICR4_EXTI14_PE_Msk (0x1U << AFIO_EXTICR4_EXTI14_PE_Pos) /*!< 0x00000400 */
+#define AFIO_EXTICR4_EXTI14_PE AFIO_EXTICR4_EXTI14_PE_Msk /*!< PE[14] pin */
+#define AFIO_EXTICR4_EXTI14_PF_Pos (8U)
+#define AFIO_EXTICR4_EXTI14_PF_Msk (0x5U << AFIO_EXTICR4_EXTI14_PF_Pos) /*!< 0x00000500 */
+#define AFIO_EXTICR4_EXTI14_PF AFIO_EXTICR4_EXTI14_PF_Msk /*!< PF[14] pin */
+#define AFIO_EXTICR4_EXTI14_PG_Pos (9U)
+#define AFIO_EXTICR4_EXTI14_PG_Msk (0x3U << AFIO_EXTICR4_EXTI14_PG_Pos) /*!< 0x00000600 */
+#define AFIO_EXTICR4_EXTI14_PG AFIO_EXTICR4_EXTI14_PG_Msk /*!< PG[14] pin */
+
+/*!< EXTI15 configuration */
+#define AFIO_EXTICR4_EXTI15_PA ((uint32_t)0x00000000) /*!< PA[15] pin */
+#define AFIO_EXTICR4_EXTI15_PB_Pos (12U)
+#define AFIO_EXTICR4_EXTI15_PB_Msk (0x1U << AFIO_EXTICR4_EXTI15_PB_Pos) /*!< 0x00001000 */
+#define AFIO_EXTICR4_EXTI15_PB AFIO_EXTICR4_EXTI15_PB_Msk /*!< PB[15] pin */
+#define AFIO_EXTICR4_EXTI15_PC_Pos (13U)
+#define AFIO_EXTICR4_EXTI15_PC_Msk (0x1U << AFIO_EXTICR4_EXTI15_PC_Pos) /*!< 0x00002000 */
+#define AFIO_EXTICR4_EXTI15_PC AFIO_EXTICR4_EXTI15_PC_Msk /*!< PC[15] pin */
+#define AFIO_EXTICR4_EXTI15_PD_Pos (12U)
+#define AFIO_EXTICR4_EXTI15_PD_Msk (0x3U << AFIO_EXTICR4_EXTI15_PD_Pos) /*!< 0x00003000 */
+#define AFIO_EXTICR4_EXTI15_PD AFIO_EXTICR4_EXTI15_PD_Msk /*!< PD[15] pin */
+#define AFIO_EXTICR4_EXTI15_PE_Pos (14U)
+#define AFIO_EXTICR4_EXTI15_PE_Msk (0x1U << AFIO_EXTICR4_EXTI15_PE_Pos) /*!< 0x00004000 */
+#define AFIO_EXTICR4_EXTI15_PE AFIO_EXTICR4_EXTI15_PE_Msk /*!< PE[15] pin */
+#define AFIO_EXTICR4_EXTI15_PF_Pos (12U)
+#define AFIO_EXTICR4_EXTI15_PF_Msk (0x5U << AFIO_EXTICR4_EXTI15_PF_Pos) /*!< 0x00005000 */
+#define AFIO_EXTICR4_EXTI15_PF AFIO_EXTICR4_EXTI15_PF_Msk /*!< PF[15] pin */
+#define AFIO_EXTICR4_EXTI15_PG_Pos (13U)
+#define AFIO_EXTICR4_EXTI15_PG_Msk (0x3U << AFIO_EXTICR4_EXTI15_PG_Pos) /*!< 0x00006000 */
+#define AFIO_EXTICR4_EXTI15_PG AFIO_EXTICR4_EXTI15_PG_Msk /*!< PG[15] pin */
+
+/****************** Bit definition for AFIO_MAPR2 register ******************/
+
+
+#define AFIO_MAPR2_TIM9_REMAP_Pos (5U)
+#define AFIO_MAPR2_TIM9_REMAP_Msk (0x1U << AFIO_MAPR2_TIM9_REMAP_Pos) /*!< 0x00000020 */
+#define AFIO_MAPR2_TIM9_REMAP AFIO_MAPR2_TIM9_REMAP_Msk /*!< TIM9 remapping */
+#define AFIO_MAPR2_TIM10_REMAP_Pos (6U)
+#define AFIO_MAPR2_TIM10_REMAP_Msk (0x1U << AFIO_MAPR2_TIM10_REMAP_Pos) /*!< 0x00000040 */
+#define AFIO_MAPR2_TIM10_REMAP AFIO_MAPR2_TIM10_REMAP_Msk /*!< TIM10 remapping */
+#define AFIO_MAPR2_TIM11_REMAP_Pos (7U)
+#define AFIO_MAPR2_TIM11_REMAP_Msk (0x1U << AFIO_MAPR2_TIM11_REMAP_Pos) /*!< 0x00000080 */
+#define AFIO_MAPR2_TIM11_REMAP AFIO_MAPR2_TIM11_REMAP_Msk /*!< TIM11 remapping */
+#define AFIO_MAPR2_TIM13_REMAP_Pos (8U)
+#define AFIO_MAPR2_TIM13_REMAP_Msk (0x1U << AFIO_MAPR2_TIM13_REMAP_Pos) /*!< 0x00000100 */
+#define AFIO_MAPR2_TIM13_REMAP AFIO_MAPR2_TIM13_REMAP_Msk /*!< TIM13 remapping */
+#define AFIO_MAPR2_TIM14_REMAP_Pos (9U)
+#define AFIO_MAPR2_TIM14_REMAP_Msk (0x1U << AFIO_MAPR2_TIM14_REMAP_Pos) /*!< 0x00000200 */
+#define AFIO_MAPR2_TIM14_REMAP AFIO_MAPR2_TIM14_REMAP_Msk /*!< TIM14 remapping */
+#define AFIO_MAPR2_FSMC_NADV_REMAP_Pos (10U)
+#define AFIO_MAPR2_FSMC_NADV_REMAP_Msk (0x1U << AFIO_MAPR2_FSMC_NADV_REMAP_Pos) /*!< 0x00000400 */
+#define AFIO_MAPR2_FSMC_NADV_REMAP AFIO_MAPR2_FSMC_NADV_REMAP_Msk /*!< FSMC NADV remapping */
+
+/******************************************************************************/
+/* */
+/* SystemTick */
+/* */
+/******************************************************************************/
+
+/***************** Bit definition for SysTick_CTRL register *****************/
+#define SysTick_CTRL_ENABLE ((uint32_t)0x00000001) /*!< Counter enable */
+#define SysTick_CTRL_TICKINT ((uint32_t)0x00000002) /*!< Counting down to 0 pends the SysTick handler */
+#define SysTick_CTRL_CLKSOURCE ((uint32_t)0x00000004) /*!< Clock source */
+#define SysTick_CTRL_COUNTFLAG ((uint32_t)0x00010000) /*!< Count Flag */
+
+/***************** Bit definition for SysTick_LOAD register *****************/
+#define SysTick_LOAD_RELOAD ((uint32_t)0x00FFFFFF) /*!< Value to load into the SysTick Current Value Register when the counter reaches 0 */
+
+/***************** Bit definition for SysTick_VAL register ******************/
+#define SysTick_VAL_CURRENT ((uint32_t)0x00FFFFFF) /*!< Current value at the time the register is accessed */
+
+/***************** Bit definition for SysTick_CALIB register ****************/
+#define SysTick_CALIB_TENMS ((uint32_t)0x00FFFFFF) /*!< Reload value to use for 10ms timing */
+#define SysTick_CALIB_SKEW ((uint32_t)0x40000000) /*!< Calibration value is not exactly 10 ms */
+#define SysTick_CALIB_NOREF ((uint32_t)0x80000000) /*!< The reference clock is not provided */
+
+/******************************************************************************/
+/* */
+/* Nested Vectored Interrupt Controller */
+/* */
+/******************************************************************************/
+
+/****************** Bit definition for NVIC_ISER register *******************/
+#define NVIC_ISER_SETENA_Pos (0U)
+#define NVIC_ISER_SETENA_Msk (0xFFFFFFFFU << NVIC_ISER_SETENA_Pos) /*!< 0xFFFFFFFF */
+#define NVIC_ISER_SETENA NVIC_ISER_SETENA_Msk /*!< Interrupt set enable bits */
+#define NVIC_ISER_SETENA_0 (0x00000001U << NVIC_ISER_SETENA_Pos) /*!< 0x00000001 */
+#define NVIC_ISER_SETENA_1 (0x00000002U << NVIC_ISER_SETENA_Pos) /*!< 0x00000002 */
+#define NVIC_ISER_SETENA_2 (0x00000004U << NVIC_ISER_SETENA_Pos) /*!< 0x00000004 */
+#define NVIC_ISER_SETENA_3 (0x00000008U << NVIC_ISER_SETENA_Pos) /*!< 0x00000008 */
+#define NVIC_ISER_SETENA_4 (0x00000010U << NVIC_ISER_SETENA_Pos) /*!< 0x00000010 */
+#define NVIC_ISER_SETENA_5 (0x00000020U << NVIC_ISER_SETENA_Pos) /*!< 0x00000020 */
+#define NVIC_ISER_SETENA_6 (0x00000040U << NVIC_ISER_SETENA_Pos) /*!< 0x00000040 */
+#define NVIC_ISER_SETENA_7 (0x00000080U << NVIC_ISER_SETENA_Pos) /*!< 0x00000080 */
+#define NVIC_ISER_SETENA_8 (0x00000100U << NVIC_ISER_SETENA_Pos) /*!< 0x00000100 */
+#define NVIC_ISER_SETENA_9 (0x00000200U << NVIC_ISER_SETENA_Pos) /*!< 0x00000200 */
+#define NVIC_ISER_SETENA_10 (0x00000400U << NVIC_ISER_SETENA_Pos) /*!< 0x00000400 */
+#define NVIC_ISER_SETENA_11 (0x00000800U << NVIC_ISER_SETENA_Pos) /*!< 0x00000800 */
+#define NVIC_ISER_SETENA_12 (0x00001000U << NVIC_ISER_SETENA_Pos) /*!< 0x00001000 */
+#define NVIC_ISER_SETENA_13 (0x00002000U << NVIC_ISER_SETENA_Pos) /*!< 0x00002000 */
+#define NVIC_ISER_SETENA_14 (0x00004000U << NVIC_ISER_SETENA_Pos) /*!< 0x00004000 */
+#define NVIC_ISER_SETENA_15 (0x00008000U << NVIC_ISER_SETENA_Pos) /*!< 0x00008000 */
+#define NVIC_ISER_SETENA_16 (0x00010000U << NVIC_ISER_SETENA_Pos) /*!< 0x00010000 */
+#define NVIC_ISER_SETENA_17 (0x00020000U << NVIC_ISER_SETENA_Pos) /*!< 0x00020000 */
+#define NVIC_ISER_SETENA_18 (0x00040000U << NVIC_ISER_SETENA_Pos) /*!< 0x00040000 */
+#define NVIC_ISER_SETENA_19 (0x00080000U << NVIC_ISER_SETENA_Pos) /*!< 0x00080000 */
+#define NVIC_ISER_SETENA_20 (0x00100000U << NVIC_ISER_SETENA_Pos) /*!< 0x00100000 */
+#define NVIC_ISER_SETENA_21 (0x00200000U << NVIC_ISER_SETENA_Pos) /*!< 0x00200000 */
+#define NVIC_ISER_SETENA_22 (0x00400000U << NVIC_ISER_SETENA_Pos) /*!< 0x00400000 */
+#define NVIC_ISER_SETENA_23 (0x00800000U << NVIC_ISER_SETENA_Pos) /*!< 0x00800000 */
+#define NVIC_ISER_SETENA_24 (0x01000000U << NVIC_ISER_SETENA_Pos) /*!< 0x01000000 */
+#define NVIC_ISER_SETENA_25 (0x02000000U << NVIC_ISER_SETENA_Pos) /*!< 0x02000000 */
+#define NVIC_ISER_SETENA_26 (0x04000000U << NVIC_ISER_SETENA_Pos) /*!< 0x04000000 */
+#define NVIC_ISER_SETENA_27 (0x08000000U << NVIC_ISER_SETENA_Pos) /*!< 0x08000000 */
+#define NVIC_ISER_SETENA_28 (0x10000000U << NVIC_ISER_SETENA_Pos) /*!< 0x10000000 */
+#define NVIC_ISER_SETENA_29 (0x20000000U << NVIC_ISER_SETENA_Pos) /*!< 0x20000000 */
+#define NVIC_ISER_SETENA_30 (0x40000000U << NVIC_ISER_SETENA_Pos) /*!< 0x40000000 */
+#define NVIC_ISER_SETENA_31 (0x80000000U << NVIC_ISER_SETENA_Pos) /*!< 0x80000000 */
+
+/****************** Bit definition for NVIC_ICER register *******************/
+#define NVIC_ICER_CLRENA_Pos (0U)
+#define NVIC_ICER_CLRENA_Msk (0xFFFFFFFFU << NVIC_ICER_CLRENA_Pos) /*!< 0xFFFFFFFF */
+#define NVIC_ICER_CLRENA NVIC_ICER_CLRENA_Msk /*!< Interrupt clear-enable bits */
+#define NVIC_ICER_CLRENA_0 (0x00000001U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000001 */
+#define NVIC_ICER_CLRENA_1 (0x00000002U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000002 */
+#define NVIC_ICER_CLRENA_2 (0x00000004U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000004 */
+#define NVIC_ICER_CLRENA_3 (0x00000008U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000008 */
+#define NVIC_ICER_CLRENA_4 (0x00000010U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000010 */
+#define NVIC_ICER_CLRENA_5 (0x00000020U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000020 */
+#define NVIC_ICER_CLRENA_6 (0x00000040U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000040 */
+#define NVIC_ICER_CLRENA_7 (0x00000080U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000080 */
+#define NVIC_ICER_CLRENA_8 (0x00000100U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000100 */
+#define NVIC_ICER_CLRENA_9 (0x00000200U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000200 */
+#define NVIC_ICER_CLRENA_10 (0x00000400U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000400 */
+#define NVIC_ICER_CLRENA_11 (0x00000800U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000800 */
+#define NVIC_ICER_CLRENA_12 (0x00001000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00001000 */
+#define NVIC_ICER_CLRENA_13 (0x00002000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00002000 */
+#define NVIC_ICER_CLRENA_14 (0x00004000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00004000 */
+#define NVIC_ICER_CLRENA_15 (0x00008000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00008000 */
+#define NVIC_ICER_CLRENA_16 (0x00010000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00010000 */
+#define NVIC_ICER_CLRENA_17 (0x00020000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00020000 */
+#define NVIC_ICER_CLRENA_18 (0x00040000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00040000 */
+#define NVIC_ICER_CLRENA_19 (0x00080000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00080000 */
+#define NVIC_ICER_CLRENA_20 (0x00100000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00100000 */
+#define NVIC_ICER_CLRENA_21 (0x00200000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00200000 */
+#define NVIC_ICER_CLRENA_22 (0x00400000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00400000 */
+#define NVIC_ICER_CLRENA_23 (0x00800000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00800000 */
+#define NVIC_ICER_CLRENA_24 (0x01000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x01000000 */
+#define NVIC_ICER_CLRENA_25 (0x02000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x02000000 */
+#define NVIC_ICER_CLRENA_26 (0x04000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x04000000 */
+#define NVIC_ICER_CLRENA_27 (0x08000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x08000000 */
+#define NVIC_ICER_CLRENA_28 (0x10000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x10000000 */
+#define NVIC_ICER_CLRENA_29 (0x20000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x20000000 */
+#define NVIC_ICER_CLRENA_30 (0x40000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x40000000 */
+#define NVIC_ICER_CLRENA_31 (0x80000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x80000000 */
+
+/****************** Bit definition for NVIC_ISPR register *******************/
+#define NVIC_ISPR_SETPEND_Pos (0U)
+#define NVIC_ISPR_SETPEND_Msk (0xFFFFFFFFU << NVIC_ISPR_SETPEND_Pos) /*!< 0xFFFFFFFF */
+#define NVIC_ISPR_SETPEND NVIC_ISPR_SETPEND_Msk /*!< Interrupt set-pending bits */
+#define NVIC_ISPR_SETPEND_0 (0x00000001U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000001 */
+#define NVIC_ISPR_SETPEND_1 (0x00000002U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000002 */
+#define NVIC_ISPR_SETPEND_2 (0x00000004U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000004 */
+#define NVIC_ISPR_SETPEND_3 (0x00000008U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000008 */
+#define NVIC_ISPR_SETPEND_4 (0x00000010U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000010 */
+#define NVIC_ISPR_SETPEND_5 (0x00000020U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000020 */
+#define NVIC_ISPR_SETPEND_6 (0x00000040U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000040 */
+#define NVIC_ISPR_SETPEND_7 (0x00000080U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000080 */
+#define NVIC_ISPR_SETPEND_8 (0x00000100U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000100 */
+#define NVIC_ISPR_SETPEND_9 (0x00000200U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000200 */
+#define NVIC_ISPR_SETPEND_10 (0x00000400U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000400 */
+#define NVIC_ISPR_SETPEND_11 (0x00000800U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000800 */
+#define NVIC_ISPR_SETPEND_12 (0x00001000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00001000 */
+#define NVIC_ISPR_SETPEND_13 (0x00002000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00002000 */
+#define NVIC_ISPR_SETPEND_14 (0x00004000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00004000 */
+#define NVIC_ISPR_SETPEND_15 (0x00008000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00008000 */
+#define NVIC_ISPR_SETPEND_16 (0x00010000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00010000 */
+#define NVIC_ISPR_SETPEND_17 (0x00020000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00020000 */
+#define NVIC_ISPR_SETPEND_18 (0x00040000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00040000 */
+#define NVIC_ISPR_SETPEND_19 (0x00080000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00080000 */
+#define NVIC_ISPR_SETPEND_20 (0x00100000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00100000 */
+#define NVIC_ISPR_SETPEND_21 (0x00200000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00200000 */
+#define NVIC_ISPR_SETPEND_22 (0x00400000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00400000 */
+#define NVIC_ISPR_SETPEND_23 (0x00800000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00800000 */
+#define NVIC_ISPR_SETPEND_24 (0x01000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x01000000 */
+#define NVIC_ISPR_SETPEND_25 (0x02000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x02000000 */
+#define NVIC_ISPR_SETPEND_26 (0x04000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x04000000 */
+#define NVIC_ISPR_SETPEND_27 (0x08000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x08000000 */
+#define NVIC_ISPR_SETPEND_28 (0x10000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x10000000 */
+#define NVIC_ISPR_SETPEND_29 (0x20000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x20000000 */
+#define NVIC_ISPR_SETPEND_30 (0x40000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x40000000 */
+#define NVIC_ISPR_SETPEND_31 (0x80000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x80000000 */
+
+/****************** Bit definition for NVIC_ICPR register *******************/
+#define NVIC_ICPR_CLRPEND_Pos (0U)
+#define NVIC_ICPR_CLRPEND_Msk (0xFFFFFFFFU << NVIC_ICPR_CLRPEND_Pos) /*!< 0xFFFFFFFF */
+#define NVIC_ICPR_CLRPEND NVIC_ICPR_CLRPEND_Msk /*!< Interrupt clear-pending bits */
+#define NVIC_ICPR_CLRPEND_0 (0x00000001U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000001 */
+#define NVIC_ICPR_CLRPEND_1 (0x00000002U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000002 */
+#define NVIC_ICPR_CLRPEND_2 (0x00000004U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000004 */
+#define NVIC_ICPR_CLRPEND_3 (0x00000008U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000008 */
+#define NVIC_ICPR_CLRPEND_4 (0x00000010U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000010 */
+#define NVIC_ICPR_CLRPEND_5 (0x00000020U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000020 */
+#define NVIC_ICPR_CLRPEND_6 (0x00000040U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000040 */
+#define NVIC_ICPR_CLRPEND_7 (0x00000080U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000080 */
+#define NVIC_ICPR_CLRPEND_8 (0x00000100U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000100 */
+#define NVIC_ICPR_CLRPEND_9 (0x00000200U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000200 */
+#define NVIC_ICPR_CLRPEND_10 (0x00000400U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000400 */
+#define NVIC_ICPR_CLRPEND_11 (0x00000800U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000800 */
+#define NVIC_ICPR_CLRPEND_12 (0x00001000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00001000 */
+#define NVIC_ICPR_CLRPEND_13 (0x00002000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00002000 */
+#define NVIC_ICPR_CLRPEND_14 (0x00004000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00004000 */
+#define NVIC_ICPR_CLRPEND_15 (0x00008000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00008000 */
+#define NVIC_ICPR_CLRPEND_16 (0x00010000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00010000 */
+#define NVIC_ICPR_CLRPEND_17 (0x00020000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00020000 */
+#define NVIC_ICPR_CLRPEND_18 (0x00040000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00040000 */
+#define NVIC_ICPR_CLRPEND_19 (0x00080000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00080000 */
+#define NVIC_ICPR_CLRPEND_20 (0x00100000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00100000 */
+#define NVIC_ICPR_CLRPEND_21 (0x00200000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00200000 */
+#define NVIC_ICPR_CLRPEND_22 (0x00400000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00400000 */
+#define NVIC_ICPR_CLRPEND_23 (0x00800000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00800000 */
+#define NVIC_ICPR_CLRPEND_24 (0x01000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x01000000 */
+#define NVIC_ICPR_CLRPEND_25 (0x02000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x02000000 */
+#define NVIC_ICPR_CLRPEND_26 (0x04000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x04000000 */
+#define NVIC_ICPR_CLRPEND_27 (0x08000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x08000000 */
+#define NVIC_ICPR_CLRPEND_28 (0x10000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x10000000 */
+#define NVIC_ICPR_CLRPEND_29 (0x20000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x20000000 */
+#define NVIC_ICPR_CLRPEND_30 (0x40000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x40000000 */
+#define NVIC_ICPR_CLRPEND_31 (0x80000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x80000000 */
+
+/****************** Bit definition for NVIC_IABR register *******************/
+#define NVIC_IABR_ACTIVE_Pos (0U)
+#define NVIC_IABR_ACTIVE_Msk (0xFFFFFFFFU << NVIC_IABR_ACTIVE_Pos) /*!< 0xFFFFFFFF */
+#define NVIC_IABR_ACTIVE NVIC_IABR_ACTIVE_Msk /*!< Interrupt active flags */
+#define NVIC_IABR_ACTIVE_0 (0x00000001U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000001 */
+#define NVIC_IABR_ACTIVE_1 (0x00000002U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000002 */
+#define NVIC_IABR_ACTIVE_2 (0x00000004U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000004 */
+#define NVIC_IABR_ACTIVE_3 (0x00000008U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000008 */
+#define NVIC_IABR_ACTIVE_4 (0x00000010U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000010 */
+#define NVIC_IABR_ACTIVE_5 (0x00000020U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000020 */
+#define NVIC_IABR_ACTIVE_6 (0x00000040U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000040 */
+#define NVIC_IABR_ACTIVE_7 (0x00000080U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000080 */
+#define NVIC_IABR_ACTIVE_8 (0x00000100U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000100 */
+#define NVIC_IABR_ACTIVE_9 (0x00000200U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000200 */
+#define NVIC_IABR_ACTIVE_10 (0x00000400U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000400 */
+#define NVIC_IABR_ACTIVE_11 (0x00000800U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000800 */
+#define NVIC_IABR_ACTIVE_12 (0x00001000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00001000 */
+#define NVIC_IABR_ACTIVE_13 (0x00002000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00002000 */
+#define NVIC_IABR_ACTIVE_14 (0x00004000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00004000 */
+#define NVIC_IABR_ACTIVE_15 (0x00008000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00008000 */
+#define NVIC_IABR_ACTIVE_16 (0x00010000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00010000 */
+#define NVIC_IABR_ACTIVE_17 (0x00020000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00020000 */
+#define NVIC_IABR_ACTIVE_18 (0x00040000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00040000 */
+#define NVIC_IABR_ACTIVE_19 (0x00080000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00080000 */
+#define NVIC_IABR_ACTIVE_20 (0x00100000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00100000 */
+#define NVIC_IABR_ACTIVE_21 (0x00200000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00200000 */
+#define NVIC_IABR_ACTIVE_22 (0x00400000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00400000 */
+#define NVIC_IABR_ACTIVE_23 (0x00800000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00800000 */
+#define NVIC_IABR_ACTIVE_24 (0x01000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x01000000 */
+#define NVIC_IABR_ACTIVE_25 (0x02000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x02000000 */
+#define NVIC_IABR_ACTIVE_26 (0x04000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x04000000 */
+#define NVIC_IABR_ACTIVE_27 (0x08000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x08000000 */
+#define NVIC_IABR_ACTIVE_28 (0x10000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x10000000 */
+#define NVIC_IABR_ACTIVE_29 (0x20000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x20000000 */
+#define NVIC_IABR_ACTIVE_30 (0x40000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x40000000 */
+#define NVIC_IABR_ACTIVE_31 (0x80000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x80000000 */
+
+/****************** Bit definition for NVIC_PRI0 register *******************/
+#define NVIC_IPR0_PRI_0 ((uint32_t)0x000000FF) /*!< Priority of interrupt 0 */
+#define NVIC_IPR0_PRI_1 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 1 */
+#define NVIC_IPR0_PRI_2 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 2 */
+#define NVIC_IPR0_PRI_3 ((uint32_t)0xFF000000) /*!< Priority of interrupt 3 */
+
+/****************** Bit definition for NVIC_PRI1 register *******************/
+#define NVIC_IPR1_PRI_4 ((uint32_t)0x000000FF) /*!< Priority of interrupt 4 */
+#define NVIC_IPR1_PRI_5 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 5 */
+#define NVIC_IPR1_PRI_6 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 6 */
+#define NVIC_IPR1_PRI_7 ((uint32_t)0xFF000000) /*!< Priority of interrupt 7 */
+
+/****************** Bit definition for NVIC_PRI2 register *******************/
+#define NVIC_IPR2_PRI_8 ((uint32_t)0x000000FF) /*!< Priority of interrupt 8 */
+#define NVIC_IPR2_PRI_9 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 9 */
+#define NVIC_IPR2_PRI_10 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 10 */
+#define NVIC_IPR2_PRI_11 ((uint32_t)0xFF000000) /*!< Priority of interrupt 11 */
+
+/****************** Bit definition for NVIC_PRI3 register *******************/
+#define NVIC_IPR3_PRI_12 ((uint32_t)0x000000FF) /*!< Priority of interrupt 12 */
+#define NVIC_IPR3_PRI_13 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 13 */
+#define NVIC_IPR3_PRI_14 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 14 */
+#define NVIC_IPR3_PRI_15 ((uint32_t)0xFF000000) /*!< Priority of interrupt 15 */
+
+/****************** Bit definition for NVIC_PRI4 register *******************/
+#define NVIC_IPR4_PRI_16 ((uint32_t)0x000000FF) /*!< Priority of interrupt 16 */
+#define NVIC_IPR4_PRI_17 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 17 */
+#define NVIC_IPR4_PRI_18 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 18 */
+#define NVIC_IPR4_PRI_19 ((uint32_t)0xFF000000) /*!< Priority of interrupt 19 */
+
+/****************** Bit definition for NVIC_PRI5 register *******************/
+#define NVIC_IPR5_PRI_20 ((uint32_t)0x000000FF) /*!< Priority of interrupt 20 */
+#define NVIC_IPR5_PRI_21 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 21 */
+#define NVIC_IPR5_PRI_22 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 22 */
+#define NVIC_IPR5_PRI_23 ((uint32_t)0xFF000000) /*!< Priority of interrupt 23 */
+
+/****************** Bit definition for NVIC_PRI6 register *******************/
+#define NVIC_IPR6_PRI_24 ((uint32_t)0x000000FF) /*!< Priority of interrupt 24 */
+#define NVIC_IPR6_PRI_25 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 25 */
+#define NVIC_IPR6_PRI_26 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 26 */
+#define NVIC_IPR6_PRI_27 ((uint32_t)0xFF000000) /*!< Priority of interrupt 27 */
+
+/****************** Bit definition for NVIC_PRI7 register *******************/
+#define NVIC_IPR7_PRI_28 ((uint32_t)0x000000FF) /*!< Priority of interrupt 28 */
+#define NVIC_IPR7_PRI_29 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 29 */
+#define NVIC_IPR7_PRI_30 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 30 */
+#define NVIC_IPR7_PRI_31 ((uint32_t)0xFF000000) /*!< Priority of interrupt 31 */
+
+/****************** Bit definition for SCB_CPUID register *******************/
+#define SCB_CPUID_REVISION ((uint32_t)0x0000000F) /*!< Implementation defined revision number */
+#define SCB_CPUID_PARTNO ((uint32_t)0x0000FFF0) /*!< Number of processor within family */
+#define SCB_CPUID_Constant ((uint32_t)0x000F0000) /*!< Reads as 0x0F */
+#define SCB_CPUID_VARIANT ((uint32_t)0x00F00000) /*!< Implementation defined variant number */
+#define SCB_CPUID_IMPLEMENTER ((uint32_t)0xFF000000) /*!< Implementer code. ARM is 0x41 */
+
+/******************* Bit definition for SCB_ICSR register *******************/
+#define SCB_ICSR_VECTACTIVE ((uint32_t)0x000001FF) /*!< Active ISR number field */
+#define SCB_ICSR_RETTOBASE ((uint32_t)0x00000800) /*!< All active exceptions minus the IPSR_current_exception yields the empty set */
+#define SCB_ICSR_VECTPENDING ((uint32_t)0x003FF000) /*!< Pending ISR number field */
+#define SCB_ICSR_ISRPENDING ((uint32_t)0x00400000) /*!< Interrupt pending flag */
+#define SCB_ICSR_ISRPREEMPT ((uint32_t)0x00800000) /*!< It indicates that a pending interrupt becomes active in the next running cycle */
+#define SCB_ICSR_PENDSTCLR ((uint32_t)0x02000000) /*!< Clear pending SysTick bit */
+#define SCB_ICSR_PENDSTSET ((uint32_t)0x04000000) /*!< Set pending SysTick bit */
+#define SCB_ICSR_PENDSVCLR ((uint32_t)0x08000000) /*!< Clear pending pendSV bit */
+#define SCB_ICSR_PENDSVSET ((uint32_t)0x10000000) /*!< Set pending pendSV bit */
+#define SCB_ICSR_NMIPENDSET ((uint32_t)0x80000000) /*!< Set pending NMI bit */
+
+/******************* Bit definition for SCB_VTOR register *******************/
+#define SCB_VTOR_TBLOFF ((uint32_t)0x1FFFFF80) /*!< Vector table base offset field */
+#define SCB_VTOR_TBLBASE ((uint32_t)0x20000000) /*!< Table base in code(0) or RAM(1) */
+
+/*!<***************** Bit definition for SCB_AIRCR register *******************/
+#define SCB_AIRCR_VECTRESET ((uint32_t)0x00000001) /*!< System Reset bit */
+#define SCB_AIRCR_VECTCLRACTIVE ((uint32_t)0x00000002) /*!< Clear active vector bit */
+#define SCB_AIRCR_SYSRESETREQ ((uint32_t)0x00000004) /*!< Requests chip control logic to generate a reset */
+
+#define SCB_AIRCR_PRIGROUP ((uint32_t)0x00000700) /*!< PRIGROUP[2:0] bits (Priority group) */
+#define SCB_AIRCR_PRIGROUP_0 ((uint32_t)0x00000100) /*!< Bit 0 */
+#define SCB_AIRCR_PRIGROUP_1 ((uint32_t)0x00000200) /*!< Bit 1 */
+#define SCB_AIRCR_PRIGROUP_2 ((uint32_t)0x00000400) /*!< Bit 2 */
+
+/* prority group configuration */
+#define SCB_AIRCR_PRIGROUP0 ((uint32_t)0x00000000) /*!< Priority group=0 (7 bits of pre-emption priority, 1 bit of subpriority) */
+#define SCB_AIRCR_PRIGROUP1 ((uint32_t)0x00000100) /*!< Priority group=1 (6 bits of pre-emption priority, 2 bits of subpriority) */
+#define SCB_AIRCR_PRIGROUP2 ((uint32_t)0x00000200) /*!< Priority group=2 (5 bits of pre-emption priority, 3 bits of subpriority) */
+#define SCB_AIRCR_PRIGROUP3 ((uint32_t)0x00000300) /*!< Priority group=3 (4 bits of pre-emption priority, 4 bits of subpriority) */
+#define SCB_AIRCR_PRIGROUP4 ((uint32_t)0x00000400) /*!< Priority group=4 (3 bits of pre-emption priority, 5 bits of subpriority) */
+#define SCB_AIRCR_PRIGROUP5 ((uint32_t)0x00000500) /*!< Priority group=5 (2 bits of pre-emption priority, 6 bits of subpriority) */
+#define SCB_AIRCR_PRIGROUP6 ((uint32_t)0x00000600) /*!< Priority group=6 (1 bit of pre-emption priority, 7 bits of subpriority) */
+#define SCB_AIRCR_PRIGROUP7 ((uint32_t)0x00000700) /*!< Priority group=7 (no pre-emption priority, 8 bits of subpriority) */
+
+#define SCB_AIRCR_ENDIANESS ((uint32_t)0x00008000) /*!< Data endianness bit */
+#define SCB_AIRCR_VECTKEY ((uint32_t)0xFFFF0000) /*!< Register key (VECTKEY) - Reads as 0xFA05 (VECTKEYSTAT) */
+
+/******************* Bit definition for SCB_SCR register ********************/
+#define SCB_SCR_SLEEPONEXIT ((uint32_t)0x00000002) /*!< Sleep on exit bit */
+#define SCB_SCR_SLEEPDEEP ((uint32_t)0x00000004) /*!< Sleep deep bit */
+#define SCB_SCR_SEVONPEND ((uint32_t)0x00000010) /*!< Wake up from WFE */
+
+/******************** Bit definition for SCB_CCR register *******************/
+#define SCB_CCR_NONBASETHRDENA ((uint32_t)0x00000001) /*!< Thread mode can be entered from any level in Handler mode by controlled return value */
+#define SCB_CCR_USERSETMPEND ((uint32_t)0x00000002) /*!< Enables user code to write the Software Trigger Interrupt register to trigger (pend) a Main exception */
+#define SCB_CCR_UNALIGN_TRP ((uint32_t)0x00000008) /*!< Trap for unaligned access */
+#define SCB_CCR_DIV_0_TRP ((uint32_t)0x00000010) /*!< Trap on Divide by 0 */
+#define SCB_CCR_BFHFNMIGN ((uint32_t)0x00000100) /*!< Handlers running at priority -1 and -2 */
+#define SCB_CCR_STKALIGN ((uint32_t)0x00000200) /*!< On exception entry, the SP used prior to the exception is adjusted to be 8-byte aligned */
+
+/******************* Bit definition for SCB_SHPR register ********************/
+#define SCB_SHPR_PRI_N_Pos (0U)
+#define SCB_SHPR_PRI_N_Msk (0xFFU << SCB_SHPR_PRI_N_Pos) /*!< 0x000000FF */
+#define SCB_SHPR_PRI_N SCB_SHPR_PRI_N_Msk /*!< Priority of system handler 4,8, and 12. Mem Manage, reserved and Debug Monitor */
+#define SCB_SHPR_PRI_N1_Pos (8U)
+#define SCB_SHPR_PRI_N1_Msk (0xFFU << SCB_SHPR_PRI_N1_Pos) /*!< 0x0000FF00 */
+#define SCB_SHPR_PRI_N1 SCB_SHPR_PRI_N1_Msk /*!< Priority of system handler 5,9, and 13. Bus Fault, reserved and reserved */
+#define SCB_SHPR_PRI_N2_Pos (16U)
+#define SCB_SHPR_PRI_N2_Msk (0xFFU << SCB_SHPR_PRI_N2_Pos) /*!< 0x00FF0000 */
+#define SCB_SHPR_PRI_N2 SCB_SHPR_PRI_N2_Msk /*!< Priority of system handler 6,10, and 14. Usage Fault, reserved and PendSV */
+#define SCB_SHPR_PRI_N3_Pos (24U)
+#define SCB_SHPR_PRI_N3_Msk (0xFFU << SCB_SHPR_PRI_N3_Pos) /*!< 0xFF000000 */
+#define SCB_SHPR_PRI_N3 SCB_SHPR_PRI_N3_Msk /*!< Priority of system handler 7,11, and 15. Reserved, SVCall and SysTick */
+
+/****************** Bit definition for SCB_SHCSR register *******************/
+#define SCB_SHCSR_MEMFAULTACT ((uint32_t)0x00000001) /*!< MemManage is active */
+#define SCB_SHCSR_BUSFAULTACT ((uint32_t)0x00000002) /*!< BusFault is active */
+#define SCB_SHCSR_USGFAULTACT ((uint32_t)0x00000008) /*!< UsageFault is active */
+#define SCB_SHCSR_SVCALLACT ((uint32_t)0x00000080) /*!< SVCall is active */
+#define SCB_SHCSR_MONITORACT ((uint32_t)0x00000100) /*!< Monitor is active */
+#define SCB_SHCSR_PENDSVACT ((uint32_t)0x00000400) /*!< PendSV is active */
+#define SCB_SHCSR_SYSTICKACT ((uint32_t)0x00000800) /*!< SysTick is active */
+#define SCB_SHCSR_USGFAULTPENDED ((uint32_t)0x00001000) /*!< Usage Fault is pended */
+#define SCB_SHCSR_MEMFAULTPENDED ((uint32_t)0x00002000) /*!< MemManage is pended */
+#define SCB_SHCSR_BUSFAULTPENDED ((uint32_t)0x00004000) /*!< Bus Fault is pended */
+#define SCB_SHCSR_SVCALLPENDED ((uint32_t)0x00008000) /*!< SVCall is pended */
+#define SCB_SHCSR_MEMFAULTENA ((uint32_t)0x00010000) /*!< MemManage enable */
+#define SCB_SHCSR_BUSFAULTENA ((uint32_t)0x00020000) /*!< Bus Fault enable */
+#define SCB_SHCSR_USGFAULTENA ((uint32_t)0x00040000) /*!< UsageFault enable */
+
+/******************* Bit definition for SCB_CFSR register *******************/
+/*!< MFSR */
+#define SCB_CFSR_IACCVIOL_Pos (0U)
+#define SCB_CFSR_IACCVIOL_Msk (0x1U << SCB_CFSR_IACCVIOL_Pos) /*!< 0x00000001 */
+#define SCB_CFSR_IACCVIOL SCB_CFSR_IACCVIOL_Msk /*!< Instruction access violation */
+#define SCB_CFSR_DACCVIOL_Pos (1U)
+#define SCB_CFSR_DACCVIOL_Msk (0x1U << SCB_CFSR_DACCVIOL_Pos) /*!< 0x00000002 */
+#define SCB_CFSR_DACCVIOL SCB_CFSR_DACCVIOL_Msk /*!< Data access violation */
+#define SCB_CFSR_MUNSTKERR_Pos (3U)
+#define SCB_CFSR_MUNSTKERR_Msk (0x1U << SCB_CFSR_MUNSTKERR_Pos) /*!< 0x00000008 */
+#define SCB_CFSR_MUNSTKERR SCB_CFSR_MUNSTKERR_Msk /*!< Unstacking error */
+#define SCB_CFSR_MSTKERR_Pos (4U)
+#define SCB_CFSR_MSTKERR_Msk (0x1U << SCB_CFSR_MSTKERR_Pos) /*!< 0x00000010 */
+#define SCB_CFSR_MSTKERR SCB_CFSR_MSTKERR_Msk /*!< Stacking error */
+#define SCB_CFSR_MMARVALID_Pos (7U)
+#define SCB_CFSR_MMARVALID_Msk (0x1U << SCB_CFSR_MMARVALID_Pos) /*!< 0x00000080 */
+#define SCB_CFSR_MMARVALID SCB_CFSR_MMARVALID_Msk /*!< Memory Manage Address Register address valid flag */
+/*!< BFSR */
+#define SCB_CFSR_IBUSERR_Pos (8U)
+#define SCB_CFSR_IBUSERR_Msk (0x1U << SCB_CFSR_IBUSERR_Pos) /*!< 0x00000100 */
+#define SCB_CFSR_IBUSERR SCB_CFSR_IBUSERR_Msk /*!< Instruction bus error flag */
+#define SCB_CFSR_PRECISERR_Pos (9U)
+#define SCB_CFSR_PRECISERR_Msk (0x1U << SCB_CFSR_PRECISERR_Pos) /*!< 0x00000200 */
+#define SCB_CFSR_PRECISERR SCB_CFSR_PRECISERR_Msk /*!< Precise data bus error */
+#define SCB_CFSR_IMPRECISERR_Pos (10U)
+#define SCB_CFSR_IMPRECISERR_Msk (0x1U << SCB_CFSR_IMPRECISERR_Pos) /*!< 0x00000400 */
+#define SCB_CFSR_IMPRECISERR SCB_CFSR_IMPRECISERR_Msk /*!< Imprecise data bus error */
+#define SCB_CFSR_UNSTKERR_Pos (11U)
+#define SCB_CFSR_UNSTKERR_Msk (0x1U << SCB_CFSR_UNSTKERR_Pos) /*!< 0x00000800 */
+#define SCB_CFSR_UNSTKERR SCB_CFSR_UNSTKERR_Msk /*!< Unstacking error */
+#define SCB_CFSR_STKERR_Pos (12U)
+#define SCB_CFSR_STKERR_Msk (0x1U << SCB_CFSR_STKERR_Pos) /*!< 0x00001000 */
+#define SCB_CFSR_STKERR SCB_CFSR_STKERR_Msk /*!< Stacking error */
+#define SCB_CFSR_BFARVALID_Pos (15U)
+#define SCB_CFSR_BFARVALID_Msk (0x1U << SCB_CFSR_BFARVALID_Pos) /*!< 0x00008000 */
+#define SCB_CFSR_BFARVALID SCB_CFSR_BFARVALID_Msk /*!< Bus Fault Address Register address valid flag */
+/*!< UFSR */
+#define SCB_CFSR_UNDEFINSTR_Pos (16U)
+#define SCB_CFSR_UNDEFINSTR_Msk (0x1U << SCB_CFSR_UNDEFINSTR_Pos) /*!< 0x00010000 */
+#define SCB_CFSR_UNDEFINSTR SCB_CFSR_UNDEFINSTR_Msk /*!< The processor attempt to execute an undefined instruction */
+#define SCB_CFSR_INVSTATE_Pos (17U)
+#define SCB_CFSR_INVSTATE_Msk (0x1U << SCB_CFSR_INVSTATE_Pos) /*!< 0x00020000 */
+#define SCB_CFSR_INVSTATE SCB_CFSR_INVSTATE_Msk /*!< Invalid combination of EPSR and instruction */
+#define SCB_CFSR_INVPC_Pos (18U)
+#define SCB_CFSR_INVPC_Msk (0x1U << SCB_CFSR_INVPC_Pos) /*!< 0x00040000 */
+#define SCB_CFSR_INVPC SCB_CFSR_INVPC_Msk /*!< Attempt to load EXC_RETURN into pc illegally */
+#define SCB_CFSR_NOCP_Pos (19U)
+#define SCB_CFSR_NOCP_Msk (0x1U << SCB_CFSR_NOCP_Pos) /*!< 0x00080000 */
+#define SCB_CFSR_NOCP SCB_CFSR_NOCP_Msk /*!< Attempt to use a coprocessor instruction */
+#define SCB_CFSR_UNALIGNED_Pos (24U)
+#define SCB_CFSR_UNALIGNED_Msk (0x1U << SCB_CFSR_UNALIGNED_Pos) /*!< 0x01000000 */
+#define SCB_CFSR_UNALIGNED SCB_CFSR_UNALIGNED_Msk /*!< Fault occurs when there is an attempt to make an unaligned memory access */
+#define SCB_CFSR_DIVBYZERO_Pos (25U)
+#define SCB_CFSR_DIVBYZERO_Msk (0x1U << SCB_CFSR_DIVBYZERO_Pos) /*!< 0x02000000 */
+#define SCB_CFSR_DIVBYZERO SCB_CFSR_DIVBYZERO_Msk /*!< Fault occurs when SDIV or DIV instruction is used with a divisor of 0 */
+
+/******************* Bit definition for SCB_HFSR register *******************/
+#define SCB_HFSR_VECTTBL ((uint32_t)0x00000002) /*!< Fault occurs because of vector table read on exception processing */
+#define SCB_HFSR_FORCED ((uint32_t)0x40000000) /*!< Hard Fault activated when a configurable Fault was received and cannot activate */
+#define SCB_HFSR_DEBUGEVT ((uint32_t)0x80000000) /*!< Fault related to debug */
+
+/******************* Bit definition for SCB_DFSR register *******************/
+#define SCB_DFSR_HALTED ((uint32_t)0x00000001) /*!< Halt request flag */
+#define SCB_DFSR_BKPT ((uint32_t)0x00000002) /*!< BKPT flag */
+#define SCB_DFSR_DWTTRAP ((uint32_t)0x00000004) /*!< Data Watchpoint and Trace (DWT) flag */
+#define SCB_DFSR_VCATCH ((uint32_t)0x00000008) /*!< Vector catch flag */
+#define SCB_DFSR_EXTERNAL ((uint32_t)0x00000010) /*!< External debug request flag */
+
+/******************* Bit definition for SCB_MMFAR register ******************/
+#define SCB_MMFAR_ADDRESS_Pos (0U)
+#define SCB_MMFAR_ADDRESS_Msk (0xFFFFFFFFU << SCB_MMFAR_ADDRESS_Pos) /*!< 0xFFFFFFFF */
+#define SCB_MMFAR_ADDRESS SCB_MMFAR_ADDRESS_Msk /*!< Mem Manage fault address field */
+
+/******************* Bit definition for SCB_BFAR register *******************/
+#define SCB_BFAR_ADDRESS_Pos (0U)
+#define SCB_BFAR_ADDRESS_Msk (0xFFFFFFFFU << SCB_BFAR_ADDRESS_Pos) /*!< 0xFFFFFFFF */
+#define SCB_BFAR_ADDRESS SCB_BFAR_ADDRESS_Msk /*!< Bus fault address field */
+
+/******************* Bit definition for SCB_afsr register *******************/
+#define SCB_AFSR_IMPDEF_Pos (0U)
+#define SCB_AFSR_IMPDEF_Msk (0xFFFFFFFFU << SCB_AFSR_IMPDEF_Pos) /*!< 0xFFFFFFFF */
+#define SCB_AFSR_IMPDEF SCB_AFSR_IMPDEF_Msk /*!< Implementation defined */
+
+/******************************************************************************/
+/* */
+/* External Interrupt/Event Controller */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for EXTI_IMR register *******************/
+#define EXTI_IMR_MR0_Pos (0U)
+#define EXTI_IMR_MR0_Msk (0x1U << EXTI_IMR_MR0_Pos) /*!< 0x00000001 */
+#define EXTI_IMR_MR0 EXTI_IMR_MR0_Msk /*!< Interrupt Mask on line 0 */
+#define EXTI_IMR_MR1_Pos (1U)
+#define EXTI_IMR_MR1_Msk (0x1U << EXTI_IMR_MR1_Pos) /*!< 0x00000002 */
+#define EXTI_IMR_MR1 EXTI_IMR_MR1_Msk /*!< Interrupt Mask on line 1 */
+#define EXTI_IMR_MR2_Pos (2U)
+#define EXTI_IMR_MR2_Msk (0x1U << EXTI_IMR_MR2_Pos) /*!< 0x00000004 */
+#define EXTI_IMR_MR2 EXTI_IMR_MR2_Msk /*!< Interrupt Mask on line 2 */
+#define EXTI_IMR_MR3_Pos (3U)
+#define EXTI_IMR_MR3_Msk (0x1U << EXTI_IMR_MR3_Pos) /*!< 0x00000008 */
+#define EXTI_IMR_MR3 EXTI_IMR_MR3_Msk /*!< Interrupt Mask on line 3 */
+#define EXTI_IMR_MR4_Pos (4U)
+#define EXTI_IMR_MR4_Msk (0x1U << EXTI_IMR_MR4_Pos) /*!< 0x00000010 */
+#define EXTI_IMR_MR4 EXTI_IMR_MR4_Msk /*!< Interrupt Mask on line 4 */
+#define EXTI_IMR_MR5_Pos (5U)
+#define EXTI_IMR_MR5_Msk (0x1U << EXTI_IMR_MR5_Pos) /*!< 0x00000020 */
+#define EXTI_IMR_MR5 EXTI_IMR_MR5_Msk /*!< Interrupt Mask on line 5 */
+#define EXTI_IMR_MR6_Pos (6U)
+#define EXTI_IMR_MR6_Msk (0x1U << EXTI_IMR_MR6_Pos) /*!< 0x00000040 */
+#define EXTI_IMR_MR6 EXTI_IMR_MR6_Msk /*!< Interrupt Mask on line 6 */
+#define EXTI_IMR_MR7_Pos (7U)
+#define EXTI_IMR_MR7_Msk (0x1U << EXTI_IMR_MR7_Pos) /*!< 0x00000080 */
+#define EXTI_IMR_MR7 EXTI_IMR_MR7_Msk /*!< Interrupt Mask on line 7 */
+#define EXTI_IMR_MR8_Pos (8U)
+#define EXTI_IMR_MR8_Msk (0x1U << EXTI_IMR_MR8_Pos) /*!< 0x00000100 */
+#define EXTI_IMR_MR8 EXTI_IMR_MR8_Msk /*!< Interrupt Mask on line 8 */
+#define EXTI_IMR_MR9_Pos (9U)
+#define EXTI_IMR_MR9_Msk (0x1U << EXTI_IMR_MR9_Pos) /*!< 0x00000200 */
+#define EXTI_IMR_MR9 EXTI_IMR_MR9_Msk /*!< Interrupt Mask on line 9 */
+#define EXTI_IMR_MR10_Pos (10U)
+#define EXTI_IMR_MR10_Msk (0x1U << EXTI_IMR_MR10_Pos) /*!< 0x00000400 */
+#define EXTI_IMR_MR10 EXTI_IMR_MR10_Msk /*!< Interrupt Mask on line 10 */
+#define EXTI_IMR_MR11_Pos (11U)
+#define EXTI_IMR_MR11_Msk (0x1U << EXTI_IMR_MR11_Pos) /*!< 0x00000800 */
+#define EXTI_IMR_MR11 EXTI_IMR_MR11_Msk /*!< Interrupt Mask on line 11 */
+#define EXTI_IMR_MR12_Pos (12U)
+#define EXTI_IMR_MR12_Msk (0x1U << EXTI_IMR_MR12_Pos) /*!< 0x00001000 */
+#define EXTI_IMR_MR12 EXTI_IMR_MR12_Msk /*!< Interrupt Mask on line 12 */
+#define EXTI_IMR_MR13_Pos (13U)
+#define EXTI_IMR_MR13_Msk (0x1U << EXTI_IMR_MR13_Pos) /*!< 0x00002000 */
+#define EXTI_IMR_MR13 EXTI_IMR_MR13_Msk /*!< Interrupt Mask on line 13 */
+#define EXTI_IMR_MR14_Pos (14U)
+#define EXTI_IMR_MR14_Msk (0x1U << EXTI_IMR_MR14_Pos) /*!< 0x00004000 */
+#define EXTI_IMR_MR14 EXTI_IMR_MR14_Msk /*!< Interrupt Mask on line 14 */
+#define EXTI_IMR_MR15_Pos (15U)
+#define EXTI_IMR_MR15_Msk (0x1U << EXTI_IMR_MR15_Pos) /*!< 0x00008000 */
+#define EXTI_IMR_MR15 EXTI_IMR_MR15_Msk /*!< Interrupt Mask on line 15 */
+#define EXTI_IMR_MR16_Pos (16U)
+#define EXTI_IMR_MR16_Msk (0x1U << EXTI_IMR_MR16_Pos) /*!< 0x00010000 */
+#define EXTI_IMR_MR16 EXTI_IMR_MR16_Msk /*!< Interrupt Mask on line 16 */
+#define EXTI_IMR_MR17_Pos (17U)
+#define EXTI_IMR_MR17_Msk (0x1U << EXTI_IMR_MR17_Pos) /*!< 0x00020000 */
+#define EXTI_IMR_MR17 EXTI_IMR_MR17_Msk /*!< Interrupt Mask on line 17 */
+#define EXTI_IMR_MR18_Pos (18U)
+#define EXTI_IMR_MR18_Msk (0x1U << EXTI_IMR_MR18_Pos) /*!< 0x00040000 */
+#define EXTI_IMR_MR18 EXTI_IMR_MR18_Msk /*!< Interrupt Mask on line 18 */
+#define EXTI_IMR_MR19_Pos (19U)
+#define EXTI_IMR_MR19_Msk (0x1U << EXTI_IMR_MR19_Pos) /*!< 0x00080000 */
+#define EXTI_IMR_MR19 EXTI_IMR_MR19_Msk /*!< Interrupt Mask on line 19 */
+
+/* References Defines */
+#define EXTI_IMR_IM0 EXTI_IMR_MR0
+#define EXTI_IMR_IM1 EXTI_IMR_MR1
+#define EXTI_IMR_IM2 EXTI_IMR_MR2
+#define EXTI_IMR_IM3 EXTI_IMR_MR3
+#define EXTI_IMR_IM4 EXTI_IMR_MR4
+#define EXTI_IMR_IM5 EXTI_IMR_MR5
+#define EXTI_IMR_IM6 EXTI_IMR_MR6
+#define EXTI_IMR_IM7 EXTI_IMR_MR7
+#define EXTI_IMR_IM8 EXTI_IMR_MR8
+#define EXTI_IMR_IM9 EXTI_IMR_MR9
+#define EXTI_IMR_IM10 EXTI_IMR_MR10
+#define EXTI_IMR_IM11 EXTI_IMR_MR11
+#define EXTI_IMR_IM12 EXTI_IMR_MR12
+#define EXTI_IMR_IM13 EXTI_IMR_MR13
+#define EXTI_IMR_IM14 EXTI_IMR_MR14
+#define EXTI_IMR_IM15 EXTI_IMR_MR15
+#define EXTI_IMR_IM16 EXTI_IMR_MR16
+#define EXTI_IMR_IM17 EXTI_IMR_MR17
+#define EXTI_IMR_IM18 EXTI_IMR_MR18
+#define EXTI_IMR_IM19 EXTI_IMR_MR19
+
+/******************* Bit definition for EXTI_EMR register *******************/
+#define EXTI_EMR_MR0_Pos (0U)
+#define EXTI_EMR_MR0_Msk (0x1U << EXTI_EMR_MR0_Pos) /*!< 0x00000001 */
+#define EXTI_EMR_MR0 EXTI_EMR_MR0_Msk /*!< Event Mask on line 0 */
+#define EXTI_EMR_MR1_Pos (1U)
+#define EXTI_EMR_MR1_Msk (0x1U << EXTI_EMR_MR1_Pos) /*!< 0x00000002 */
+#define EXTI_EMR_MR1 EXTI_EMR_MR1_Msk /*!< Event Mask on line 1 */
+#define EXTI_EMR_MR2_Pos (2U)
+#define EXTI_EMR_MR2_Msk (0x1U << EXTI_EMR_MR2_Pos) /*!< 0x00000004 */
+#define EXTI_EMR_MR2 EXTI_EMR_MR2_Msk /*!< Event Mask on line 2 */
+#define EXTI_EMR_MR3_Pos (3U)
+#define EXTI_EMR_MR3_Msk (0x1U << EXTI_EMR_MR3_Pos) /*!< 0x00000008 */
+#define EXTI_EMR_MR3 EXTI_EMR_MR3_Msk /*!< Event Mask on line 3 */
+#define EXTI_EMR_MR4_Pos (4U)
+#define EXTI_EMR_MR4_Msk (0x1U << EXTI_EMR_MR4_Pos) /*!< 0x00000010 */
+#define EXTI_EMR_MR4 EXTI_EMR_MR4_Msk /*!< Event Mask on line 4 */
+#define EXTI_EMR_MR5_Pos (5U)
+#define EXTI_EMR_MR5_Msk (0x1U << EXTI_EMR_MR5_Pos) /*!< 0x00000020 */
+#define EXTI_EMR_MR5 EXTI_EMR_MR5_Msk /*!< Event Mask on line 5 */
+#define EXTI_EMR_MR6_Pos (6U)
+#define EXTI_EMR_MR6_Msk (0x1U << EXTI_EMR_MR6_Pos) /*!< 0x00000040 */
+#define EXTI_EMR_MR6 EXTI_EMR_MR6_Msk /*!< Event Mask on line 6 */
+#define EXTI_EMR_MR7_Pos (7U)
+#define EXTI_EMR_MR7_Msk (0x1U << EXTI_EMR_MR7_Pos) /*!< 0x00000080 */
+#define EXTI_EMR_MR7 EXTI_EMR_MR7_Msk /*!< Event Mask on line 7 */
+#define EXTI_EMR_MR8_Pos (8U)
+#define EXTI_EMR_MR8_Msk (0x1U << EXTI_EMR_MR8_Pos) /*!< 0x00000100 */
+#define EXTI_EMR_MR8 EXTI_EMR_MR8_Msk /*!< Event Mask on line 8 */
+#define EXTI_EMR_MR9_Pos (9U)
+#define EXTI_EMR_MR9_Msk (0x1U << EXTI_EMR_MR9_Pos) /*!< 0x00000200 */
+#define EXTI_EMR_MR9 EXTI_EMR_MR9_Msk /*!< Event Mask on line 9 */
+#define EXTI_EMR_MR10_Pos (10U)
+#define EXTI_EMR_MR10_Msk (0x1U << EXTI_EMR_MR10_Pos) /*!< 0x00000400 */
+#define EXTI_EMR_MR10 EXTI_EMR_MR10_Msk /*!< Event Mask on line 10 */
+#define EXTI_EMR_MR11_Pos (11U)
+#define EXTI_EMR_MR11_Msk (0x1U << EXTI_EMR_MR11_Pos) /*!< 0x00000800 */
+#define EXTI_EMR_MR11 EXTI_EMR_MR11_Msk /*!< Event Mask on line 11 */
+#define EXTI_EMR_MR12_Pos (12U)
+#define EXTI_EMR_MR12_Msk (0x1U << EXTI_EMR_MR12_Pos) /*!< 0x00001000 */
+#define EXTI_EMR_MR12 EXTI_EMR_MR12_Msk /*!< Event Mask on line 12 */
+#define EXTI_EMR_MR13_Pos (13U)
+#define EXTI_EMR_MR13_Msk (0x1U << EXTI_EMR_MR13_Pos) /*!< 0x00002000 */
+#define EXTI_EMR_MR13 EXTI_EMR_MR13_Msk /*!< Event Mask on line 13 */
+#define EXTI_EMR_MR14_Pos (14U)
+#define EXTI_EMR_MR14_Msk (0x1U << EXTI_EMR_MR14_Pos) /*!< 0x00004000 */
+#define EXTI_EMR_MR14 EXTI_EMR_MR14_Msk /*!< Event Mask on line 14 */
+#define EXTI_EMR_MR15_Pos (15U)
+#define EXTI_EMR_MR15_Msk (0x1U << EXTI_EMR_MR15_Pos) /*!< 0x00008000 */
+#define EXTI_EMR_MR15 EXTI_EMR_MR15_Msk /*!< Event Mask on line 15 */
+#define EXTI_EMR_MR16_Pos (16U)
+#define EXTI_EMR_MR16_Msk (0x1U << EXTI_EMR_MR16_Pos) /*!< 0x00010000 */
+#define EXTI_EMR_MR16 EXTI_EMR_MR16_Msk /*!< Event Mask on line 16 */
+#define EXTI_EMR_MR17_Pos (17U)
+#define EXTI_EMR_MR17_Msk (0x1U << EXTI_EMR_MR17_Pos) /*!< 0x00020000 */
+#define EXTI_EMR_MR17 EXTI_EMR_MR17_Msk /*!< Event Mask on line 17 */
+#define EXTI_EMR_MR18_Pos (18U)
+#define EXTI_EMR_MR18_Msk (0x1U << EXTI_EMR_MR18_Pos) /*!< 0x00040000 */
+#define EXTI_EMR_MR18 EXTI_EMR_MR18_Msk /*!< Event Mask on line 18 */
+#define EXTI_EMR_MR19_Pos (19U)
+#define EXTI_EMR_MR19_Msk (0x1U << EXTI_EMR_MR19_Pos) /*!< 0x00080000 */
+#define EXTI_EMR_MR19 EXTI_EMR_MR19_Msk /*!< Event Mask on line 19 */
+
+/* References Defines */
+#define EXTI_EMR_EM0 EXTI_EMR_MR0
+#define EXTI_EMR_EM1 EXTI_EMR_MR1
+#define EXTI_EMR_EM2 EXTI_EMR_MR2
+#define EXTI_EMR_EM3 EXTI_EMR_MR3
+#define EXTI_EMR_EM4 EXTI_EMR_MR4
+#define EXTI_EMR_EM5 EXTI_EMR_MR5
+#define EXTI_EMR_EM6 EXTI_EMR_MR6
+#define EXTI_EMR_EM7 EXTI_EMR_MR7
+#define EXTI_EMR_EM8 EXTI_EMR_MR8
+#define EXTI_EMR_EM9 EXTI_EMR_MR9
+#define EXTI_EMR_EM10 EXTI_EMR_MR10
+#define EXTI_EMR_EM11 EXTI_EMR_MR11
+#define EXTI_EMR_EM12 EXTI_EMR_MR12
+#define EXTI_EMR_EM13 EXTI_EMR_MR13
+#define EXTI_EMR_EM14 EXTI_EMR_MR14
+#define EXTI_EMR_EM15 EXTI_EMR_MR15
+#define EXTI_EMR_EM16 EXTI_EMR_MR16
+#define EXTI_EMR_EM17 EXTI_EMR_MR17
+#define EXTI_EMR_EM18 EXTI_EMR_MR18
+#define EXTI_EMR_EM19 EXTI_EMR_MR19
+
+/****************** Bit definition for EXTI_RTSR register *******************/
+#define EXTI_RTSR_TR0_Pos (0U)
+#define EXTI_RTSR_TR0_Msk (0x1U << EXTI_RTSR_TR0_Pos) /*!< 0x00000001 */
+#define EXTI_RTSR_TR0 EXTI_RTSR_TR0_Msk /*!< Rising trigger event configuration bit of line 0 */
+#define EXTI_RTSR_TR1_Pos (1U)
+#define EXTI_RTSR_TR1_Msk (0x1U << EXTI_RTSR_TR1_Pos) /*!< 0x00000002 */
+#define EXTI_RTSR_TR1 EXTI_RTSR_TR1_Msk /*!< Rising trigger event configuration bit of line 1 */
+#define EXTI_RTSR_TR2_Pos (2U)
+#define EXTI_RTSR_TR2_Msk (0x1U << EXTI_RTSR_TR2_Pos) /*!< 0x00000004 */
+#define EXTI_RTSR_TR2 EXTI_RTSR_TR2_Msk /*!< Rising trigger event configuration bit of line 2 */
+#define EXTI_RTSR_TR3_Pos (3U)
+#define EXTI_RTSR_TR3_Msk (0x1U << EXTI_RTSR_TR3_Pos) /*!< 0x00000008 */
+#define EXTI_RTSR_TR3 EXTI_RTSR_TR3_Msk /*!< Rising trigger event configuration bit of line 3 */
+#define EXTI_RTSR_TR4_Pos (4U)
+#define EXTI_RTSR_TR4_Msk (0x1U << EXTI_RTSR_TR4_Pos) /*!< 0x00000010 */
+#define EXTI_RTSR_TR4 EXTI_RTSR_TR4_Msk /*!< Rising trigger event configuration bit of line 4 */
+#define EXTI_RTSR_TR5_Pos (5U)
+#define EXTI_RTSR_TR5_Msk (0x1U << EXTI_RTSR_TR5_Pos) /*!< 0x00000020 */
+#define EXTI_RTSR_TR5 EXTI_RTSR_TR5_Msk /*!< Rising trigger event configuration bit of line 5 */
+#define EXTI_RTSR_TR6_Pos (6U)
+#define EXTI_RTSR_TR6_Msk (0x1U << EXTI_RTSR_TR6_Pos) /*!< 0x00000040 */
+#define EXTI_RTSR_TR6 EXTI_RTSR_TR6_Msk /*!< Rising trigger event configuration bit of line 6 */
+#define EXTI_RTSR_TR7_Pos (7U)
+#define EXTI_RTSR_TR7_Msk (0x1U << EXTI_RTSR_TR7_Pos) /*!< 0x00000080 */
+#define EXTI_RTSR_TR7 EXTI_RTSR_TR7_Msk /*!< Rising trigger event configuration bit of line 7 */
+#define EXTI_RTSR_TR8_Pos (8U)
+#define EXTI_RTSR_TR8_Msk (0x1U << EXTI_RTSR_TR8_Pos) /*!< 0x00000100 */
+#define EXTI_RTSR_TR8 EXTI_RTSR_TR8_Msk /*!< Rising trigger event configuration bit of line 8 */
+#define EXTI_RTSR_TR9_Pos (9U)
+#define EXTI_RTSR_TR9_Msk (0x1U << EXTI_RTSR_TR9_Pos) /*!< 0x00000200 */
+#define EXTI_RTSR_TR9 EXTI_RTSR_TR9_Msk /*!< Rising trigger event configuration bit of line 9 */
+#define EXTI_RTSR_TR10_Pos (10U)
+#define EXTI_RTSR_TR10_Msk (0x1U << EXTI_RTSR_TR10_Pos) /*!< 0x00000400 */
+#define EXTI_RTSR_TR10 EXTI_RTSR_TR10_Msk /*!< Rising trigger event configuration bit of line 10 */
+#define EXTI_RTSR_TR11_Pos (11U)
+#define EXTI_RTSR_TR11_Msk (0x1U << EXTI_RTSR_TR11_Pos) /*!< 0x00000800 */
+#define EXTI_RTSR_TR11 EXTI_RTSR_TR11_Msk /*!< Rising trigger event configuration bit of line 11 */
+#define EXTI_RTSR_TR12_Pos (12U)
+#define EXTI_RTSR_TR12_Msk (0x1U << EXTI_RTSR_TR12_Pos) /*!< 0x00001000 */
+#define EXTI_RTSR_TR12 EXTI_RTSR_TR12_Msk /*!< Rising trigger event configuration bit of line 12 */
+#define EXTI_RTSR_TR13_Pos (13U)
+#define EXTI_RTSR_TR13_Msk (0x1U << EXTI_RTSR_TR13_Pos) /*!< 0x00002000 */
+#define EXTI_RTSR_TR13 EXTI_RTSR_TR13_Msk /*!< Rising trigger event configuration bit of line 13 */
+#define EXTI_RTSR_TR14_Pos (14U)
+#define EXTI_RTSR_TR14_Msk (0x1U << EXTI_RTSR_TR14_Pos) /*!< 0x00004000 */
+#define EXTI_RTSR_TR14 EXTI_RTSR_TR14_Msk /*!< Rising trigger event configuration bit of line 14 */
+#define EXTI_RTSR_TR15_Pos (15U)
+#define EXTI_RTSR_TR15_Msk (0x1U << EXTI_RTSR_TR15_Pos) /*!< 0x00008000 */
+#define EXTI_RTSR_TR15 EXTI_RTSR_TR15_Msk /*!< Rising trigger event configuration bit of line 15 */
+#define EXTI_RTSR_TR16_Pos (16U)
+#define EXTI_RTSR_TR16_Msk (0x1U << EXTI_RTSR_TR16_Pos) /*!< 0x00010000 */
+#define EXTI_RTSR_TR16 EXTI_RTSR_TR16_Msk /*!< Rising trigger event configuration bit of line 16 */
+#define EXTI_RTSR_TR17_Pos (17U)
+#define EXTI_RTSR_TR17_Msk (0x1U << EXTI_RTSR_TR17_Pos) /*!< 0x00020000 */
+#define EXTI_RTSR_TR17 EXTI_RTSR_TR17_Msk /*!< Rising trigger event configuration bit of line 17 */
+#define EXTI_RTSR_TR18_Pos (18U)
+#define EXTI_RTSR_TR18_Msk (0x1U << EXTI_RTSR_TR18_Pos) /*!< 0x00040000 */
+#define EXTI_RTSR_TR18 EXTI_RTSR_TR18_Msk /*!< Rising trigger event configuration bit of line 18 */
+#define EXTI_RTSR_TR19_Pos (19U)
+#define EXTI_RTSR_TR19_Msk (0x1U << EXTI_RTSR_TR19_Pos) /*!< 0x00080000 */
+#define EXTI_RTSR_TR19 EXTI_RTSR_TR19_Msk /*!< Rising trigger event configuration bit of line 19 */
+
+/* References Defines */
+#define EXTI_RTSR_RT0 EXTI_RTSR_TR0
+#define EXTI_RTSR_RT1 EXTI_RTSR_TR1
+#define EXTI_RTSR_RT2 EXTI_RTSR_TR2
+#define EXTI_RTSR_RT3 EXTI_RTSR_TR3
+#define EXTI_RTSR_RT4 EXTI_RTSR_TR4
+#define EXTI_RTSR_RT5 EXTI_RTSR_TR5
+#define EXTI_RTSR_RT6 EXTI_RTSR_TR6
+#define EXTI_RTSR_RT7 EXTI_RTSR_TR7
+#define EXTI_RTSR_RT8 EXTI_RTSR_TR8
+#define EXTI_RTSR_RT9 EXTI_RTSR_TR9
+#define EXTI_RTSR_RT10 EXTI_RTSR_TR10
+#define EXTI_RTSR_RT11 EXTI_RTSR_TR11
+#define EXTI_RTSR_RT12 EXTI_RTSR_TR12
+#define EXTI_RTSR_RT13 EXTI_RTSR_TR13
+#define EXTI_RTSR_RT14 EXTI_RTSR_TR14
+#define EXTI_RTSR_RT15 EXTI_RTSR_TR15
+#define EXTI_RTSR_RT16 EXTI_RTSR_TR16
+#define EXTI_RTSR_RT17 EXTI_RTSR_TR17
+#define EXTI_RTSR_RT18 EXTI_RTSR_TR18
+#define EXTI_RTSR_RT19 EXTI_RTSR_TR19
+
+/****************** Bit definition for EXTI_FTSR register *******************/
+#define EXTI_FTSR_TR0_Pos (0U)
+#define EXTI_FTSR_TR0_Msk (0x1U << EXTI_FTSR_TR0_Pos) /*!< 0x00000001 */
+#define EXTI_FTSR_TR0 EXTI_FTSR_TR0_Msk /*!< Falling trigger event configuration bit of line 0 */
+#define EXTI_FTSR_TR1_Pos (1U)
+#define EXTI_FTSR_TR1_Msk (0x1U << EXTI_FTSR_TR1_Pos) /*!< 0x00000002 */
+#define EXTI_FTSR_TR1 EXTI_FTSR_TR1_Msk /*!< Falling trigger event configuration bit of line 1 */
+#define EXTI_FTSR_TR2_Pos (2U)
+#define EXTI_FTSR_TR2_Msk (0x1U << EXTI_FTSR_TR2_Pos) /*!< 0x00000004 */
+#define EXTI_FTSR_TR2 EXTI_FTSR_TR2_Msk /*!< Falling trigger event configuration bit of line 2 */
+#define EXTI_FTSR_TR3_Pos (3U)
+#define EXTI_FTSR_TR3_Msk (0x1U << EXTI_FTSR_TR3_Pos) /*!< 0x00000008 */
+#define EXTI_FTSR_TR3 EXTI_FTSR_TR3_Msk /*!< Falling trigger event configuration bit of line 3 */
+#define EXTI_FTSR_TR4_Pos (4U)
+#define EXTI_FTSR_TR4_Msk (0x1U << EXTI_FTSR_TR4_Pos) /*!< 0x00000010 */
+#define EXTI_FTSR_TR4 EXTI_FTSR_TR4_Msk /*!< Falling trigger event configuration bit of line 4 */
+#define EXTI_FTSR_TR5_Pos (5U)
+#define EXTI_FTSR_TR5_Msk (0x1U << EXTI_FTSR_TR5_Pos) /*!< 0x00000020 */
+#define EXTI_FTSR_TR5 EXTI_FTSR_TR5_Msk /*!< Falling trigger event configuration bit of line 5 */
+#define EXTI_FTSR_TR6_Pos (6U)
+#define EXTI_FTSR_TR6_Msk (0x1U << EXTI_FTSR_TR6_Pos) /*!< 0x00000040 */
+#define EXTI_FTSR_TR6 EXTI_FTSR_TR6_Msk /*!< Falling trigger event configuration bit of line 6 */
+#define EXTI_FTSR_TR7_Pos (7U)
+#define EXTI_FTSR_TR7_Msk (0x1U << EXTI_FTSR_TR7_Pos) /*!< 0x00000080 */
+#define EXTI_FTSR_TR7 EXTI_FTSR_TR7_Msk /*!< Falling trigger event configuration bit of line 7 */
+#define EXTI_FTSR_TR8_Pos (8U)
+#define EXTI_FTSR_TR8_Msk (0x1U << EXTI_FTSR_TR8_Pos) /*!< 0x00000100 */
+#define EXTI_FTSR_TR8 EXTI_FTSR_TR8_Msk /*!< Falling trigger event configuration bit of line 8 */
+#define EXTI_FTSR_TR9_Pos (9U)
+#define EXTI_FTSR_TR9_Msk (0x1U << EXTI_FTSR_TR9_Pos) /*!< 0x00000200 */
+#define EXTI_FTSR_TR9 EXTI_FTSR_TR9_Msk /*!< Falling trigger event configuration bit of line 9 */
+#define EXTI_FTSR_TR10_Pos (10U)
+#define EXTI_FTSR_TR10_Msk (0x1U << EXTI_FTSR_TR10_Pos) /*!< 0x00000400 */
+#define EXTI_FTSR_TR10 EXTI_FTSR_TR10_Msk /*!< Falling trigger event configuration bit of line 10 */
+#define EXTI_FTSR_TR11_Pos (11U)
+#define EXTI_FTSR_TR11_Msk (0x1U << EXTI_FTSR_TR11_Pos) /*!< 0x00000800 */
+#define EXTI_FTSR_TR11 EXTI_FTSR_TR11_Msk /*!< Falling trigger event configuration bit of line 11 */
+#define EXTI_FTSR_TR12_Pos (12U)
+#define EXTI_FTSR_TR12_Msk (0x1U << EXTI_FTSR_TR12_Pos) /*!< 0x00001000 */
+#define EXTI_FTSR_TR12 EXTI_FTSR_TR12_Msk /*!< Falling trigger event configuration bit of line 12 */
+#define EXTI_FTSR_TR13_Pos (13U)
+#define EXTI_FTSR_TR13_Msk (0x1U << EXTI_FTSR_TR13_Pos) /*!< 0x00002000 */
+#define EXTI_FTSR_TR13 EXTI_FTSR_TR13_Msk /*!< Falling trigger event configuration bit of line 13 */
+#define EXTI_FTSR_TR14_Pos (14U)
+#define EXTI_FTSR_TR14_Msk (0x1U << EXTI_FTSR_TR14_Pos) /*!< 0x00004000 */
+#define EXTI_FTSR_TR14 EXTI_FTSR_TR14_Msk /*!< Falling trigger event configuration bit of line 14 */
+#define EXTI_FTSR_TR15_Pos (15U)
+#define EXTI_FTSR_TR15_Msk (0x1U << EXTI_FTSR_TR15_Pos) /*!< 0x00008000 */
+#define EXTI_FTSR_TR15 EXTI_FTSR_TR15_Msk /*!< Falling trigger event configuration bit of line 15 */
+#define EXTI_FTSR_TR16_Pos (16U)
+#define EXTI_FTSR_TR16_Msk (0x1U << EXTI_FTSR_TR16_Pos) /*!< 0x00010000 */
+#define EXTI_FTSR_TR16 EXTI_FTSR_TR16_Msk /*!< Falling trigger event configuration bit of line 16 */
+#define EXTI_FTSR_TR17_Pos (17U)
+#define EXTI_FTSR_TR17_Msk (0x1U << EXTI_FTSR_TR17_Pos) /*!< 0x00020000 */
+#define EXTI_FTSR_TR17 EXTI_FTSR_TR17_Msk /*!< Falling trigger event configuration bit of line 17 */
+#define EXTI_FTSR_TR18_Pos (18U)
+#define EXTI_FTSR_TR18_Msk (0x1U << EXTI_FTSR_TR18_Pos) /*!< 0x00040000 */
+#define EXTI_FTSR_TR18 EXTI_FTSR_TR18_Msk /*!< Falling trigger event configuration bit of line 18 */
+#define EXTI_FTSR_TR19_Pos (19U)
+#define EXTI_FTSR_TR19_Msk (0x1U << EXTI_FTSR_TR19_Pos) /*!< 0x00080000 */
+#define EXTI_FTSR_TR19 EXTI_FTSR_TR19_Msk /*!< Falling trigger event configuration bit of line 19 */
+
+/* References Defines */
+#define EXTI_FTSR_FT0 EXTI_FTSR_TR0
+#define EXTI_FTSR_FT1 EXTI_FTSR_TR1
+#define EXTI_FTSR_FT2 EXTI_FTSR_TR2
+#define EXTI_FTSR_FT3 EXTI_FTSR_TR3
+#define EXTI_FTSR_FT4 EXTI_FTSR_TR4
+#define EXTI_FTSR_FT5 EXTI_FTSR_TR5
+#define EXTI_FTSR_FT6 EXTI_FTSR_TR6
+#define EXTI_FTSR_FT7 EXTI_FTSR_TR7
+#define EXTI_FTSR_FT8 EXTI_FTSR_TR8
+#define EXTI_FTSR_FT9 EXTI_FTSR_TR9
+#define EXTI_FTSR_FT10 EXTI_FTSR_TR10
+#define EXTI_FTSR_FT11 EXTI_FTSR_TR11
+#define EXTI_FTSR_FT12 EXTI_FTSR_TR12
+#define EXTI_FTSR_FT13 EXTI_FTSR_TR13
+#define EXTI_FTSR_FT14 EXTI_FTSR_TR14
+#define EXTI_FTSR_FT15 EXTI_FTSR_TR15
+#define EXTI_FTSR_FT16 EXTI_FTSR_TR16
+#define EXTI_FTSR_FT17 EXTI_FTSR_TR17
+#define EXTI_FTSR_FT18 EXTI_FTSR_TR18
+#define EXTI_FTSR_FT19 EXTI_FTSR_TR19
+
+/****************** Bit definition for EXTI_SWIER register ******************/
+#define EXTI_SWIER_SWIER0_Pos (0U)
+#define EXTI_SWIER_SWIER0_Msk (0x1U << EXTI_SWIER_SWIER0_Pos) /*!< 0x00000001 */
+#define EXTI_SWIER_SWIER0 EXTI_SWIER_SWIER0_Msk /*!< Software Interrupt on line 0 */
+#define EXTI_SWIER_SWIER1_Pos (1U)
+#define EXTI_SWIER_SWIER1_Msk (0x1U << EXTI_SWIER_SWIER1_Pos) /*!< 0x00000002 */
+#define EXTI_SWIER_SWIER1 EXTI_SWIER_SWIER1_Msk /*!< Software Interrupt on line 1 */
+#define EXTI_SWIER_SWIER2_Pos (2U)
+#define EXTI_SWIER_SWIER2_Msk (0x1U << EXTI_SWIER_SWIER2_Pos) /*!< 0x00000004 */
+#define EXTI_SWIER_SWIER2 EXTI_SWIER_SWIER2_Msk /*!< Software Interrupt on line 2 */
+#define EXTI_SWIER_SWIER3_Pos (3U)
+#define EXTI_SWIER_SWIER3_Msk (0x1U << EXTI_SWIER_SWIER3_Pos) /*!< 0x00000008 */
+#define EXTI_SWIER_SWIER3 EXTI_SWIER_SWIER3_Msk /*!< Software Interrupt on line 3 */
+#define EXTI_SWIER_SWIER4_Pos (4U)
+#define EXTI_SWIER_SWIER4_Msk (0x1U << EXTI_SWIER_SWIER4_Pos) /*!< 0x00000010 */
+#define EXTI_SWIER_SWIER4 EXTI_SWIER_SWIER4_Msk /*!< Software Interrupt on line 4 */
+#define EXTI_SWIER_SWIER5_Pos (5U)
+#define EXTI_SWIER_SWIER5_Msk (0x1U << EXTI_SWIER_SWIER5_Pos) /*!< 0x00000020 */
+#define EXTI_SWIER_SWIER5 EXTI_SWIER_SWIER5_Msk /*!< Software Interrupt on line 5 */
+#define EXTI_SWIER_SWIER6_Pos (6U)
+#define EXTI_SWIER_SWIER6_Msk (0x1U << EXTI_SWIER_SWIER6_Pos) /*!< 0x00000040 */
+#define EXTI_SWIER_SWIER6 EXTI_SWIER_SWIER6_Msk /*!< Software Interrupt on line 6 */
+#define EXTI_SWIER_SWIER7_Pos (7U)
+#define EXTI_SWIER_SWIER7_Msk (0x1U << EXTI_SWIER_SWIER7_Pos) /*!< 0x00000080 */
+#define EXTI_SWIER_SWIER7 EXTI_SWIER_SWIER7_Msk /*!< Software Interrupt on line 7 */
+#define EXTI_SWIER_SWIER8_Pos (8U)
+#define EXTI_SWIER_SWIER8_Msk (0x1U << EXTI_SWIER_SWIER8_Pos) /*!< 0x00000100 */
+#define EXTI_SWIER_SWIER8 EXTI_SWIER_SWIER8_Msk /*!< Software Interrupt on line 8 */
+#define EXTI_SWIER_SWIER9_Pos (9U)
+#define EXTI_SWIER_SWIER9_Msk (0x1U << EXTI_SWIER_SWIER9_Pos) /*!< 0x00000200 */
+#define EXTI_SWIER_SWIER9 EXTI_SWIER_SWIER9_Msk /*!< Software Interrupt on line 9 */
+#define EXTI_SWIER_SWIER10_Pos (10U)
+#define EXTI_SWIER_SWIER10_Msk (0x1U << EXTI_SWIER_SWIER10_Pos) /*!< 0x00000400 */
+#define EXTI_SWIER_SWIER10 EXTI_SWIER_SWIER10_Msk /*!< Software Interrupt on line 10 */
+#define EXTI_SWIER_SWIER11_Pos (11U)
+#define EXTI_SWIER_SWIER11_Msk (0x1U << EXTI_SWIER_SWIER11_Pos) /*!< 0x00000800 */
+#define EXTI_SWIER_SWIER11 EXTI_SWIER_SWIER11_Msk /*!< Software Interrupt on line 11 */
+#define EXTI_SWIER_SWIER12_Pos (12U)
+#define EXTI_SWIER_SWIER12_Msk (0x1U << EXTI_SWIER_SWIER12_Pos) /*!< 0x00001000 */
+#define EXTI_SWIER_SWIER12 EXTI_SWIER_SWIER12_Msk /*!< Software Interrupt on line 12 */
+#define EXTI_SWIER_SWIER13_Pos (13U)
+#define EXTI_SWIER_SWIER13_Msk (0x1U << EXTI_SWIER_SWIER13_Pos) /*!< 0x00002000 */
+#define EXTI_SWIER_SWIER13 EXTI_SWIER_SWIER13_Msk /*!< Software Interrupt on line 13 */
+#define EXTI_SWIER_SWIER14_Pos (14U)
+#define EXTI_SWIER_SWIER14_Msk (0x1U << EXTI_SWIER_SWIER14_Pos) /*!< 0x00004000 */
+#define EXTI_SWIER_SWIER14 EXTI_SWIER_SWIER14_Msk /*!< Software Interrupt on line 14 */
+#define EXTI_SWIER_SWIER15_Pos (15U)
+#define EXTI_SWIER_SWIER15_Msk (0x1U << EXTI_SWIER_SWIER15_Pos) /*!< 0x00008000 */
+#define EXTI_SWIER_SWIER15 EXTI_SWIER_SWIER15_Msk /*!< Software Interrupt on line 15 */
+#define EXTI_SWIER_SWIER16_Pos (16U)
+#define EXTI_SWIER_SWIER16_Msk (0x1U << EXTI_SWIER_SWIER16_Pos) /*!< 0x00010000 */
+#define EXTI_SWIER_SWIER16 EXTI_SWIER_SWIER16_Msk /*!< Software Interrupt on line 16 */
+#define EXTI_SWIER_SWIER17_Pos (17U)
+#define EXTI_SWIER_SWIER17_Msk (0x1U << EXTI_SWIER_SWIER17_Pos) /*!< 0x00020000 */
+#define EXTI_SWIER_SWIER17 EXTI_SWIER_SWIER17_Msk /*!< Software Interrupt on line 17 */
+#define EXTI_SWIER_SWIER18_Pos (18U)
+#define EXTI_SWIER_SWIER18_Msk (0x1U << EXTI_SWIER_SWIER18_Pos) /*!< 0x00040000 */
+#define EXTI_SWIER_SWIER18 EXTI_SWIER_SWIER18_Msk /*!< Software Interrupt on line 18 */
+#define EXTI_SWIER_SWIER19_Pos (19U)
+#define EXTI_SWIER_SWIER19_Msk (0x1U << EXTI_SWIER_SWIER19_Pos) /*!< 0x00080000 */
+#define EXTI_SWIER_SWIER19 EXTI_SWIER_SWIER19_Msk /*!< Software Interrupt on line 19 */
+
+/* References Defines */
+#define EXTI_SWIER_SWI0 EXTI_SWIER_SWIER0
+#define EXTI_SWIER_SWI1 EXTI_SWIER_SWIER1
+#define EXTI_SWIER_SWI2 EXTI_SWIER_SWIER2
+#define EXTI_SWIER_SWI3 EXTI_SWIER_SWIER3
+#define EXTI_SWIER_SWI4 EXTI_SWIER_SWIER4
+#define EXTI_SWIER_SWI5 EXTI_SWIER_SWIER5
+#define EXTI_SWIER_SWI6 EXTI_SWIER_SWIER6
+#define EXTI_SWIER_SWI7 EXTI_SWIER_SWIER7
+#define EXTI_SWIER_SWI8 EXTI_SWIER_SWIER8
+#define EXTI_SWIER_SWI9 EXTI_SWIER_SWIER9
+#define EXTI_SWIER_SWI10 EXTI_SWIER_SWIER10
+#define EXTI_SWIER_SWI11 EXTI_SWIER_SWIER11
+#define EXTI_SWIER_SWI12 EXTI_SWIER_SWIER12
+#define EXTI_SWIER_SWI13 EXTI_SWIER_SWIER13
+#define EXTI_SWIER_SWI14 EXTI_SWIER_SWIER14
+#define EXTI_SWIER_SWI15 EXTI_SWIER_SWIER15
+#define EXTI_SWIER_SWI16 EXTI_SWIER_SWIER16
+#define EXTI_SWIER_SWI17 EXTI_SWIER_SWIER17
+#define EXTI_SWIER_SWI18 EXTI_SWIER_SWIER18
+#define EXTI_SWIER_SWI19 EXTI_SWIER_SWIER19
+
+/******************* Bit definition for EXTI_PR register ********************/
+#define EXTI_PR_PR0_Pos (0U)
+#define EXTI_PR_PR0_Msk (0x1U << EXTI_PR_PR0_Pos) /*!< 0x00000001 */
+#define EXTI_PR_PR0 EXTI_PR_PR0_Msk /*!< Pending bit for line 0 */
+#define EXTI_PR_PR1_Pos (1U)
+#define EXTI_PR_PR1_Msk (0x1U << EXTI_PR_PR1_Pos) /*!< 0x00000002 */
+#define EXTI_PR_PR1 EXTI_PR_PR1_Msk /*!< Pending bit for line 1 */
+#define EXTI_PR_PR2_Pos (2U)
+#define EXTI_PR_PR2_Msk (0x1U << EXTI_PR_PR2_Pos) /*!< 0x00000004 */
+#define EXTI_PR_PR2 EXTI_PR_PR2_Msk /*!< Pending bit for line 2 */
+#define EXTI_PR_PR3_Pos (3U)
+#define EXTI_PR_PR3_Msk (0x1U << EXTI_PR_PR3_Pos) /*!< 0x00000008 */
+#define EXTI_PR_PR3 EXTI_PR_PR3_Msk /*!< Pending bit for line 3 */
+#define EXTI_PR_PR4_Pos (4U)
+#define EXTI_PR_PR4_Msk (0x1U << EXTI_PR_PR4_Pos) /*!< 0x00000010 */
+#define EXTI_PR_PR4 EXTI_PR_PR4_Msk /*!< Pending bit for line 4 */
+#define EXTI_PR_PR5_Pos (5U)
+#define EXTI_PR_PR5_Msk (0x1U << EXTI_PR_PR5_Pos) /*!< 0x00000020 */
+#define EXTI_PR_PR5 EXTI_PR_PR5_Msk /*!< Pending bit for line 5 */
+#define EXTI_PR_PR6_Pos (6U)
+#define EXTI_PR_PR6_Msk (0x1U << EXTI_PR_PR6_Pos) /*!< 0x00000040 */
+#define EXTI_PR_PR6 EXTI_PR_PR6_Msk /*!< Pending bit for line 6 */
+#define EXTI_PR_PR7_Pos (7U)
+#define EXTI_PR_PR7_Msk (0x1U << EXTI_PR_PR7_Pos) /*!< 0x00000080 */
+#define EXTI_PR_PR7 EXTI_PR_PR7_Msk /*!< Pending bit for line 7 */
+#define EXTI_PR_PR8_Pos (8U)
+#define EXTI_PR_PR8_Msk (0x1U << EXTI_PR_PR8_Pos) /*!< 0x00000100 */
+#define EXTI_PR_PR8 EXTI_PR_PR8_Msk /*!< Pending bit for line 8 */
+#define EXTI_PR_PR9_Pos (9U)
+#define EXTI_PR_PR9_Msk (0x1U << EXTI_PR_PR9_Pos) /*!< 0x00000200 */
+#define EXTI_PR_PR9 EXTI_PR_PR9_Msk /*!< Pending bit for line 9 */
+#define EXTI_PR_PR10_Pos (10U)
+#define EXTI_PR_PR10_Msk (0x1U << EXTI_PR_PR10_Pos) /*!< 0x00000400 */
+#define EXTI_PR_PR10 EXTI_PR_PR10_Msk /*!< Pending bit for line 10 */
+#define EXTI_PR_PR11_Pos (11U)
+#define EXTI_PR_PR11_Msk (0x1U << EXTI_PR_PR11_Pos) /*!< 0x00000800 */
+#define EXTI_PR_PR11 EXTI_PR_PR11_Msk /*!< Pending bit for line 11 */
+#define EXTI_PR_PR12_Pos (12U)
+#define EXTI_PR_PR12_Msk (0x1U << EXTI_PR_PR12_Pos) /*!< 0x00001000 */
+#define EXTI_PR_PR12 EXTI_PR_PR12_Msk /*!< Pending bit for line 12 */
+#define EXTI_PR_PR13_Pos (13U)
+#define EXTI_PR_PR13_Msk (0x1U << EXTI_PR_PR13_Pos) /*!< 0x00002000 */
+#define EXTI_PR_PR13 EXTI_PR_PR13_Msk /*!< Pending bit for line 13 */
+#define EXTI_PR_PR14_Pos (14U)
+#define EXTI_PR_PR14_Msk (0x1U << EXTI_PR_PR14_Pos) /*!< 0x00004000 */
+#define EXTI_PR_PR14 EXTI_PR_PR14_Msk /*!< Pending bit for line 14 */
+#define EXTI_PR_PR15_Pos (15U)
+#define EXTI_PR_PR15_Msk (0x1U << EXTI_PR_PR15_Pos) /*!< 0x00008000 */
+#define EXTI_PR_PR15 EXTI_PR_PR15_Msk /*!< Pending bit for line 15 */
+#define EXTI_PR_PR16_Pos (16U)
+#define EXTI_PR_PR16_Msk (0x1U << EXTI_PR_PR16_Pos) /*!< 0x00010000 */
+#define EXTI_PR_PR16 EXTI_PR_PR16_Msk /*!< Pending bit for line 16 */
+#define EXTI_PR_PR17_Pos (17U)
+#define EXTI_PR_PR17_Msk (0x1U << EXTI_PR_PR17_Pos) /*!< 0x00020000 */
+#define EXTI_PR_PR17 EXTI_PR_PR17_Msk /*!< Pending bit for line 17 */
+#define EXTI_PR_PR18_Pos (18U)
+#define EXTI_PR_PR18_Msk (0x1U << EXTI_PR_PR18_Pos) /*!< 0x00040000 */
+#define EXTI_PR_PR18 EXTI_PR_PR18_Msk /*!< Pending bit for line 18 */
+#define EXTI_PR_PR19_Pos (19U)
+#define EXTI_PR_PR19_Msk (0x1U << EXTI_PR_PR19_Pos) /*!< 0x00080000 */
+#define EXTI_PR_PR19 EXTI_PR_PR19_Msk /*!< Pending bit for line 19 */
+
+/* References Defines */
+#define EXTI_PR_PIF0 EXTI_PR_PR0
+#define EXTI_PR_PIF1 EXTI_PR_PR1
+#define EXTI_PR_PIF2 EXTI_PR_PR2
+#define EXTI_PR_PIF3 EXTI_PR_PR3
+#define EXTI_PR_PIF4 EXTI_PR_PR4
+#define EXTI_PR_PIF5 EXTI_PR_PR5
+#define EXTI_PR_PIF6 EXTI_PR_PR6
+#define EXTI_PR_PIF7 EXTI_PR_PR7
+#define EXTI_PR_PIF8 EXTI_PR_PR8
+#define EXTI_PR_PIF9 EXTI_PR_PR9
+#define EXTI_PR_PIF10 EXTI_PR_PR10
+#define EXTI_PR_PIF11 EXTI_PR_PR11
+#define EXTI_PR_PIF12 EXTI_PR_PR12
+#define EXTI_PR_PIF13 EXTI_PR_PR13
+#define EXTI_PR_PIF14 EXTI_PR_PR14
+#define EXTI_PR_PIF15 EXTI_PR_PR15
+#define EXTI_PR_PIF16 EXTI_PR_PR16
+#define EXTI_PR_PIF17 EXTI_PR_PR17
+#define EXTI_PR_PIF18 EXTI_PR_PR18
+#define EXTI_PR_PIF19 EXTI_PR_PR19
+
+/******************************************************************************/
+/* */
+/* DMA Controller */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for DMA_ISR register ********************/
+#define DMA_ISR_GIF1_Pos (0U)
+#define DMA_ISR_GIF1_Msk (0x1U << DMA_ISR_GIF1_Pos) /*!< 0x00000001 */
+#define DMA_ISR_GIF1 DMA_ISR_GIF1_Msk /*!< Channel 1 Global interrupt flag */
+#define DMA_ISR_TCIF1_Pos (1U)
+#define DMA_ISR_TCIF1_Msk (0x1U << DMA_ISR_TCIF1_Pos) /*!< 0x00000002 */
+#define DMA_ISR_TCIF1 DMA_ISR_TCIF1_Msk /*!< Channel 1 Transfer Complete flag */
+#define DMA_ISR_HTIF1_Pos (2U)
+#define DMA_ISR_HTIF1_Msk (0x1U << DMA_ISR_HTIF1_Pos) /*!< 0x00000004 */
+#define DMA_ISR_HTIF1 DMA_ISR_HTIF1_Msk /*!< Channel 1 Half Transfer flag */
+#define DMA_ISR_TEIF1_Pos (3U)
+#define DMA_ISR_TEIF1_Msk (0x1U << DMA_ISR_TEIF1_Pos) /*!< 0x00000008 */
+#define DMA_ISR_TEIF1 DMA_ISR_TEIF1_Msk /*!< Channel 1 Transfer Error flag */
+#define DMA_ISR_GIF2_Pos (4U)
+#define DMA_ISR_GIF2_Msk (0x1U << DMA_ISR_GIF2_Pos) /*!< 0x00000010 */
+#define DMA_ISR_GIF2 DMA_ISR_GIF2_Msk /*!< Channel 2 Global interrupt flag */
+#define DMA_ISR_TCIF2_Pos (5U)
+#define DMA_ISR_TCIF2_Msk (0x1U << DMA_ISR_TCIF2_Pos) /*!< 0x00000020 */
+#define DMA_ISR_TCIF2 DMA_ISR_TCIF2_Msk /*!< Channel 2 Transfer Complete flag */
+#define DMA_ISR_HTIF2_Pos (6U)
+#define DMA_ISR_HTIF2_Msk (0x1U << DMA_ISR_HTIF2_Pos) /*!< 0x00000040 */
+#define DMA_ISR_HTIF2 DMA_ISR_HTIF2_Msk /*!< Channel 2 Half Transfer flag */
+#define DMA_ISR_TEIF2_Pos (7U)
+#define DMA_ISR_TEIF2_Msk (0x1U << DMA_ISR_TEIF2_Pos) /*!< 0x00000080 */
+#define DMA_ISR_TEIF2 DMA_ISR_TEIF2_Msk /*!< Channel 2 Transfer Error flag */
+#define DMA_ISR_GIF3_Pos (8U)
+#define DMA_ISR_GIF3_Msk (0x1U << DMA_ISR_GIF3_Pos) /*!< 0x00000100 */
+#define DMA_ISR_GIF3 DMA_ISR_GIF3_Msk /*!< Channel 3 Global interrupt flag */
+#define DMA_ISR_TCIF3_Pos (9U)
+#define DMA_ISR_TCIF3_Msk (0x1U << DMA_ISR_TCIF3_Pos) /*!< 0x00000200 */
+#define DMA_ISR_TCIF3 DMA_ISR_TCIF3_Msk /*!< Channel 3 Transfer Complete flag */
+#define DMA_ISR_HTIF3_Pos (10U)
+#define DMA_ISR_HTIF3_Msk (0x1U << DMA_ISR_HTIF3_Pos) /*!< 0x00000400 */
+#define DMA_ISR_HTIF3 DMA_ISR_HTIF3_Msk /*!< Channel 3 Half Transfer flag */
+#define DMA_ISR_TEIF3_Pos (11U)
+#define DMA_ISR_TEIF3_Msk (0x1U << DMA_ISR_TEIF3_Pos) /*!< 0x00000800 */
+#define DMA_ISR_TEIF3 DMA_ISR_TEIF3_Msk /*!< Channel 3 Transfer Error flag */
+#define DMA_ISR_GIF4_Pos (12U)
+#define DMA_ISR_GIF4_Msk (0x1U << DMA_ISR_GIF4_Pos) /*!< 0x00001000 */
+#define DMA_ISR_GIF4 DMA_ISR_GIF4_Msk /*!< Channel 4 Global interrupt flag */
+#define DMA_ISR_TCIF4_Pos (13U)
+#define DMA_ISR_TCIF4_Msk (0x1U << DMA_ISR_TCIF4_Pos) /*!< 0x00002000 */
+#define DMA_ISR_TCIF4 DMA_ISR_TCIF4_Msk /*!< Channel 4 Transfer Complete flag */
+#define DMA_ISR_HTIF4_Pos (14U)
+#define DMA_ISR_HTIF4_Msk (0x1U << DMA_ISR_HTIF4_Pos) /*!< 0x00004000 */
+#define DMA_ISR_HTIF4 DMA_ISR_HTIF4_Msk /*!< Channel 4 Half Transfer flag */
+#define DMA_ISR_TEIF4_Pos (15U)
+#define DMA_ISR_TEIF4_Msk (0x1U << DMA_ISR_TEIF4_Pos) /*!< 0x00008000 */
+#define DMA_ISR_TEIF4 DMA_ISR_TEIF4_Msk /*!< Channel 4 Transfer Error flag */
+#define DMA_ISR_GIF5_Pos (16U)
+#define DMA_ISR_GIF5_Msk (0x1U << DMA_ISR_GIF5_Pos) /*!< 0x00010000 */
+#define DMA_ISR_GIF5 DMA_ISR_GIF5_Msk /*!< Channel 5 Global interrupt flag */
+#define DMA_ISR_TCIF5_Pos (17U)
+#define DMA_ISR_TCIF5_Msk (0x1U << DMA_ISR_TCIF5_Pos) /*!< 0x00020000 */
+#define DMA_ISR_TCIF5 DMA_ISR_TCIF5_Msk /*!< Channel 5 Transfer Complete flag */
+#define DMA_ISR_HTIF5_Pos (18U)
+#define DMA_ISR_HTIF5_Msk (0x1U << DMA_ISR_HTIF5_Pos) /*!< 0x00040000 */
+#define DMA_ISR_HTIF5 DMA_ISR_HTIF5_Msk /*!< Channel 5 Half Transfer flag */
+#define DMA_ISR_TEIF5_Pos (19U)
+#define DMA_ISR_TEIF5_Msk (0x1U << DMA_ISR_TEIF5_Pos) /*!< 0x00080000 */
+#define DMA_ISR_TEIF5 DMA_ISR_TEIF5_Msk /*!< Channel 5 Transfer Error flag */
+#define DMA_ISR_GIF6_Pos (20U)
+#define DMA_ISR_GIF6_Msk (0x1U << DMA_ISR_GIF6_Pos) /*!< 0x00100000 */
+#define DMA_ISR_GIF6 DMA_ISR_GIF6_Msk /*!< Channel 6 Global interrupt flag */
+#define DMA_ISR_TCIF6_Pos (21U)
+#define DMA_ISR_TCIF6_Msk (0x1U << DMA_ISR_TCIF6_Pos) /*!< 0x00200000 */
+#define DMA_ISR_TCIF6 DMA_ISR_TCIF6_Msk /*!< Channel 6 Transfer Complete flag */
+#define DMA_ISR_HTIF6_Pos (22U)
+#define DMA_ISR_HTIF6_Msk (0x1U << DMA_ISR_HTIF6_Pos) /*!< 0x00400000 */
+#define DMA_ISR_HTIF6 DMA_ISR_HTIF6_Msk /*!< Channel 6 Half Transfer flag */
+#define DMA_ISR_TEIF6_Pos (23U)
+#define DMA_ISR_TEIF6_Msk (0x1U << DMA_ISR_TEIF6_Pos) /*!< 0x00800000 */
+#define DMA_ISR_TEIF6 DMA_ISR_TEIF6_Msk /*!< Channel 6 Transfer Error flag */
+#define DMA_ISR_GIF7_Pos (24U)
+#define DMA_ISR_GIF7_Msk (0x1U << DMA_ISR_GIF7_Pos) /*!< 0x01000000 */
+#define DMA_ISR_GIF7 DMA_ISR_GIF7_Msk /*!< Channel 7 Global interrupt flag */
+#define DMA_ISR_TCIF7_Pos (25U)
+#define DMA_ISR_TCIF7_Msk (0x1U << DMA_ISR_TCIF7_Pos) /*!< 0x02000000 */
+#define DMA_ISR_TCIF7 DMA_ISR_TCIF7_Msk /*!< Channel 7 Transfer Complete flag */
+#define DMA_ISR_HTIF7_Pos (26U)
+#define DMA_ISR_HTIF7_Msk (0x1U << DMA_ISR_HTIF7_Pos) /*!< 0x04000000 */
+#define DMA_ISR_HTIF7 DMA_ISR_HTIF7_Msk /*!< Channel 7 Half Transfer flag */
+#define DMA_ISR_TEIF7_Pos (27U)
+#define DMA_ISR_TEIF7_Msk (0x1U << DMA_ISR_TEIF7_Pos) /*!< 0x08000000 */
+#define DMA_ISR_TEIF7 DMA_ISR_TEIF7_Msk /*!< Channel 7 Transfer Error flag */
+
+/******************* Bit definition for DMA_IFCR register *******************/
+#define DMA_IFCR_CGIF1_Pos (0U)
+#define DMA_IFCR_CGIF1_Msk (0x1U << DMA_IFCR_CGIF1_Pos) /*!< 0x00000001 */
+#define DMA_IFCR_CGIF1 DMA_IFCR_CGIF1_Msk /*!< Channel 1 Global interrupt clear */
+#define DMA_IFCR_CTCIF1_Pos (1U)
+#define DMA_IFCR_CTCIF1_Msk (0x1U << DMA_IFCR_CTCIF1_Pos) /*!< 0x00000002 */
+#define DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF1_Msk /*!< Channel 1 Transfer Complete clear */
+#define DMA_IFCR_CHTIF1_Pos (2U)
+#define DMA_IFCR_CHTIF1_Msk (0x1U << DMA_IFCR_CHTIF1_Pos) /*!< 0x00000004 */
+#define DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF1_Msk /*!< Channel 1 Half Transfer clear */
+#define DMA_IFCR_CTEIF1_Pos (3U)
+#define DMA_IFCR_CTEIF1_Msk (0x1U << DMA_IFCR_CTEIF1_Pos) /*!< 0x00000008 */
+#define DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF1_Msk /*!< Channel 1 Transfer Error clear */
+#define DMA_IFCR_CGIF2_Pos (4U)
+#define DMA_IFCR_CGIF2_Msk (0x1U << DMA_IFCR_CGIF2_Pos) /*!< 0x00000010 */
+#define DMA_IFCR_CGIF2 DMA_IFCR_CGIF2_Msk /*!< Channel 2 Global interrupt clear */
+#define DMA_IFCR_CTCIF2_Pos (5U)
+#define DMA_IFCR_CTCIF2_Msk (0x1U << DMA_IFCR_CTCIF2_Pos) /*!< 0x00000020 */
+#define DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF2_Msk /*!< Channel 2 Transfer Complete clear */
+#define DMA_IFCR_CHTIF2_Pos (6U)
+#define DMA_IFCR_CHTIF2_Msk (0x1U << DMA_IFCR_CHTIF2_Pos) /*!< 0x00000040 */
+#define DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF2_Msk /*!< Channel 2 Half Transfer clear */
+#define DMA_IFCR_CTEIF2_Pos (7U)
+#define DMA_IFCR_CTEIF2_Msk (0x1U << DMA_IFCR_CTEIF2_Pos) /*!< 0x00000080 */
+#define DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF2_Msk /*!< Channel 2 Transfer Error clear */
+#define DMA_IFCR_CGIF3_Pos (8U)
+#define DMA_IFCR_CGIF3_Msk (0x1U << DMA_IFCR_CGIF3_Pos) /*!< 0x00000100 */
+#define DMA_IFCR_CGIF3 DMA_IFCR_CGIF3_Msk /*!< Channel 3 Global interrupt clear */
+#define DMA_IFCR_CTCIF3_Pos (9U)
+#define DMA_IFCR_CTCIF3_Msk (0x1U << DMA_IFCR_CTCIF3_Pos) /*!< 0x00000200 */
+#define DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF3_Msk /*!< Channel 3 Transfer Complete clear */
+#define DMA_IFCR_CHTIF3_Pos (10U)
+#define DMA_IFCR_CHTIF3_Msk (0x1U << DMA_IFCR_CHTIF3_Pos) /*!< 0x00000400 */
+#define DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF3_Msk /*!< Channel 3 Half Transfer clear */
+#define DMA_IFCR_CTEIF3_Pos (11U)
+#define DMA_IFCR_CTEIF3_Msk (0x1U << DMA_IFCR_CTEIF3_Pos) /*!< 0x00000800 */
+#define DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF3_Msk /*!< Channel 3 Transfer Error clear */
+#define DMA_IFCR_CGIF4_Pos (12U)
+#define DMA_IFCR_CGIF4_Msk (0x1U << DMA_IFCR_CGIF4_Pos) /*!< 0x00001000 */
+#define DMA_IFCR_CGIF4 DMA_IFCR_CGIF4_Msk /*!< Channel 4 Global interrupt clear */
+#define DMA_IFCR_CTCIF4_Pos (13U)
+#define DMA_IFCR_CTCIF4_Msk (0x1U << DMA_IFCR_CTCIF4_Pos) /*!< 0x00002000 */
+#define DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF4_Msk /*!< Channel 4 Transfer Complete clear */
+#define DMA_IFCR_CHTIF4_Pos (14U)
+#define DMA_IFCR_CHTIF4_Msk (0x1U << DMA_IFCR_CHTIF4_Pos) /*!< 0x00004000 */
+#define DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF4_Msk /*!< Channel 4 Half Transfer clear */
+#define DMA_IFCR_CTEIF4_Pos (15U)
+#define DMA_IFCR_CTEIF4_Msk (0x1U << DMA_IFCR_CTEIF4_Pos) /*!< 0x00008000 */
+#define DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF4_Msk /*!< Channel 4 Transfer Error clear */
+#define DMA_IFCR_CGIF5_Pos (16U)
+#define DMA_IFCR_CGIF5_Msk (0x1U << DMA_IFCR_CGIF5_Pos) /*!< 0x00010000 */
+#define DMA_IFCR_CGIF5 DMA_IFCR_CGIF5_Msk /*!< Channel 5 Global interrupt clear */
+#define DMA_IFCR_CTCIF5_Pos (17U)
+#define DMA_IFCR_CTCIF5_Msk (0x1U << DMA_IFCR_CTCIF5_Pos) /*!< 0x00020000 */
+#define DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF5_Msk /*!< Channel 5 Transfer Complete clear */
+#define DMA_IFCR_CHTIF5_Pos (18U)
+#define DMA_IFCR_CHTIF5_Msk (0x1U << DMA_IFCR_CHTIF5_Pos) /*!< 0x00040000 */
+#define DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5_Msk /*!< Channel 5 Half Transfer clear */
+#define DMA_IFCR_CTEIF5_Pos (19U)
+#define DMA_IFCR_CTEIF5_Msk (0x1U << DMA_IFCR_CTEIF5_Pos) /*!< 0x00080000 */
+#define DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF5_Msk /*!< Channel 5 Transfer Error clear */
+#define DMA_IFCR_CGIF6_Pos (20U)
+#define DMA_IFCR_CGIF6_Msk (0x1U << DMA_IFCR_CGIF6_Pos) /*!< 0x00100000 */
+#define DMA_IFCR_CGIF6 DMA_IFCR_CGIF6_Msk /*!< Channel 6 Global interrupt clear */
+#define DMA_IFCR_CTCIF6_Pos (21U)
+#define DMA_IFCR_CTCIF6_Msk (0x1U << DMA_IFCR_CTCIF6_Pos) /*!< 0x00200000 */
+#define DMA_IFCR_CTCIF6 DMA_IFCR_CTCIF6_Msk /*!< Channel 6 Transfer Complete clear */
+#define DMA_IFCR_CHTIF6_Pos (22U)
+#define DMA_IFCR_CHTIF6_Msk (0x1U << DMA_IFCR_CHTIF6_Pos) /*!< 0x00400000 */
+#define DMA_IFCR_CHTIF6 DMA_IFCR_CHTIF6_Msk /*!< Channel 6 Half Transfer clear */
+#define DMA_IFCR_CTEIF6_Pos (23U)
+#define DMA_IFCR_CTEIF6_Msk (0x1U << DMA_IFCR_CTEIF6_Pos) /*!< 0x00800000 */
+#define DMA_IFCR_CTEIF6 DMA_IFCR_CTEIF6_Msk /*!< Channel 6 Transfer Error clear */
+#define DMA_IFCR_CGIF7_Pos (24U)
+#define DMA_IFCR_CGIF7_Msk (0x1U << DMA_IFCR_CGIF7_Pos) /*!< 0x01000000 */
+#define DMA_IFCR_CGIF7 DMA_IFCR_CGIF7_Msk /*!< Channel 7 Global interrupt clear */
+#define DMA_IFCR_CTCIF7_Pos (25U)
+#define DMA_IFCR_CTCIF7_Msk (0x1U << DMA_IFCR_CTCIF7_Pos) /*!< 0x02000000 */
+#define DMA_IFCR_CTCIF7 DMA_IFCR_CTCIF7_Msk /*!< Channel 7 Transfer Complete clear */
+#define DMA_IFCR_CHTIF7_Pos (26U)
+#define DMA_IFCR_CHTIF7_Msk (0x1U << DMA_IFCR_CHTIF7_Pos) /*!< 0x04000000 */
+#define DMA_IFCR_CHTIF7 DMA_IFCR_CHTIF7_Msk /*!< Channel 7 Half Transfer clear */
+#define DMA_IFCR_CTEIF7_Pos (27U)
+#define DMA_IFCR_CTEIF7_Msk (0x1U << DMA_IFCR_CTEIF7_Pos) /*!< 0x08000000 */
+#define DMA_IFCR_CTEIF7 DMA_IFCR_CTEIF7_Msk /*!< Channel 7 Transfer Error clear */
+
+/******************* Bit definition for DMA_CCR register *******************/
+#define DMA_CCR_EN_Pos (0U)
+#define DMA_CCR_EN_Msk (0x1U << DMA_CCR_EN_Pos) /*!< 0x00000001 */
+#define DMA_CCR_EN DMA_CCR_EN_Msk /*!< Channel enable */
+#define DMA_CCR_TCIE_Pos (1U)
+#define DMA_CCR_TCIE_Msk (0x1U << DMA_CCR_TCIE_Pos) /*!< 0x00000002 */
+#define DMA_CCR_TCIE DMA_CCR_TCIE_Msk /*!< Transfer complete interrupt enable */
+#define DMA_CCR_HTIE_Pos (2U)
+#define DMA_CCR_HTIE_Msk (0x1U << DMA_CCR_HTIE_Pos) /*!< 0x00000004 */
+#define DMA_CCR_HTIE DMA_CCR_HTIE_Msk /*!< Half Transfer interrupt enable */
+#define DMA_CCR_TEIE_Pos (3U)
+#define DMA_CCR_TEIE_Msk (0x1U << DMA_CCR_TEIE_Pos) /*!< 0x00000008 */
+#define DMA_CCR_TEIE DMA_CCR_TEIE_Msk /*!< Transfer error interrupt enable */
+#define DMA_CCR_DIR_Pos (4U)
+#define DMA_CCR_DIR_Msk (0x1U << DMA_CCR_DIR_Pos) /*!< 0x00000010 */
+#define DMA_CCR_DIR DMA_CCR_DIR_Msk /*!< Data transfer direction */
+#define DMA_CCR_CIRC_Pos (5U)
+#define DMA_CCR_CIRC_Msk (0x1U << DMA_CCR_CIRC_Pos) /*!< 0x00000020 */
+#define DMA_CCR_CIRC DMA_CCR_CIRC_Msk /*!< Circular mode */
+#define DMA_CCR_PINC_Pos (6U)
+#define DMA_CCR_PINC_Msk (0x1U << DMA_CCR_PINC_Pos) /*!< 0x00000040 */
+#define DMA_CCR_PINC DMA_CCR_PINC_Msk /*!< Peripheral increment mode */
+#define DMA_CCR_MINC_Pos (7U)
+#define DMA_CCR_MINC_Msk (0x1U << DMA_CCR_MINC_Pos) /*!< 0x00000080 */
+#define DMA_CCR_MINC DMA_CCR_MINC_Msk /*!< Memory increment mode */
+
+#define DMA_CCR_PSIZE_Pos (8U)
+#define DMA_CCR_PSIZE_Msk (0x3U << DMA_CCR_PSIZE_Pos) /*!< 0x00000300 */
+#define DMA_CCR_PSIZE DMA_CCR_PSIZE_Msk /*!< PSIZE[1:0] bits (Peripheral size) */
+#define DMA_CCR_PSIZE_0 (0x1U << DMA_CCR_PSIZE_Pos) /*!< 0x00000100 */
+#define DMA_CCR_PSIZE_1 (0x2U << DMA_CCR_PSIZE_Pos) /*!< 0x00000200 */
+
+#define DMA_CCR_MSIZE_Pos (10U)
+#define DMA_CCR_MSIZE_Msk (0x3U << DMA_CCR_MSIZE_Pos) /*!< 0x00000C00 */
+#define DMA_CCR_MSIZE DMA_CCR_MSIZE_Msk /*!< MSIZE[1:0] bits (Memory size) */
+#define DMA_CCR_MSIZE_0 (0x1U << DMA_CCR_MSIZE_Pos) /*!< 0x00000400 */
+#define DMA_CCR_MSIZE_1 (0x2U << DMA_CCR_MSIZE_Pos) /*!< 0x00000800 */
+
+#define DMA_CCR_PL_Pos (12U)
+#define DMA_CCR_PL_Msk (0x3U << DMA_CCR_PL_Pos) /*!< 0x00003000 */
+#define DMA_CCR_PL DMA_CCR_PL_Msk /*!< PL[1:0] bits(Channel Priority level) */
+#define DMA_CCR_PL_0 (0x1U << DMA_CCR_PL_Pos) /*!< 0x00001000 */
+#define DMA_CCR_PL_1 (0x2U << DMA_CCR_PL_Pos) /*!< 0x00002000 */
+
+#define DMA_CCR_MEM2MEM_Pos (14U)
+#define DMA_CCR_MEM2MEM_Msk (0x1U << DMA_CCR_MEM2MEM_Pos) /*!< 0x00004000 */
+#define DMA_CCR_MEM2MEM DMA_CCR_MEM2MEM_Msk /*!< Memory to memory mode */
+
+/****************** Bit definition for DMA_CNDTR register ******************/
+#define DMA_CNDTR_NDT_Pos (0U)
+#define DMA_CNDTR_NDT_Msk (0xFFFFU << DMA_CNDTR_NDT_Pos) /*!< 0x0000FFFF */
+#define DMA_CNDTR_NDT DMA_CNDTR_NDT_Msk /*!< Number of data to Transfer */
+
+/****************** Bit definition for DMA_CPAR register *******************/
+#define DMA_CPAR_PA_Pos (0U)
+#define DMA_CPAR_PA_Msk (0xFFFFFFFFU << DMA_CPAR_PA_Pos) /*!< 0xFFFFFFFF */
+#define DMA_CPAR_PA DMA_CPAR_PA_Msk /*!< Peripheral Address */
+
+/****************** Bit definition for DMA_CMAR register *******************/
+#define DMA_CMAR_MA_Pos (0U)
+#define DMA_CMAR_MA_Msk (0xFFFFFFFFU << DMA_CMAR_MA_Pos) /*!< 0xFFFFFFFF */
+#define DMA_CMAR_MA DMA_CMAR_MA_Msk /*!< Memory Address */
+
+/******************************************************************************/
+/* */
+/* Analog to Digital Converter (ADC) */
+/* */
+/******************************************************************************/
+
+/*
+ * @brief Specific device feature definitions (not present on all devices in the STM32F1 family)
+ */
+#define ADC_MULTIMODE_SUPPORT /*!< ADC feature available only on specific devices: multimode available on devices with several ADC instances */
+
+/******************** Bit definition for ADC_SR register ********************/
+#define ADC_SR_AWD_Pos (0U)
+#define ADC_SR_AWD_Msk (0x1U << ADC_SR_AWD_Pos) /*!< 0x00000001 */
+#define ADC_SR_AWD ADC_SR_AWD_Msk /*!< ADC analog watchdog 1 flag */
+#define ADC_SR_EOS_Pos (1U)
+#define ADC_SR_EOS_Msk (0x1U << ADC_SR_EOS_Pos) /*!< 0x00000002 */
+#define ADC_SR_EOS ADC_SR_EOS_Msk /*!< ADC group regular end of sequence conversions flag */
+#define ADC_SR_JEOS_Pos (2U)
+#define ADC_SR_JEOS_Msk (0x1U << ADC_SR_JEOS_Pos) /*!< 0x00000004 */
+#define ADC_SR_JEOS ADC_SR_JEOS_Msk /*!< ADC group injected end of sequence conversions flag */
+#define ADC_SR_JSTRT_Pos (3U)
+#define ADC_SR_JSTRT_Msk (0x1U << ADC_SR_JSTRT_Pos) /*!< 0x00000008 */
+#define ADC_SR_JSTRT ADC_SR_JSTRT_Msk /*!< ADC group injected conversion start flag */
+#define ADC_SR_STRT_Pos (4U)
+#define ADC_SR_STRT_Msk (0x1U << ADC_SR_STRT_Pos) /*!< 0x00000010 */
+#define ADC_SR_STRT ADC_SR_STRT_Msk /*!< ADC group regular conversion start flag */
+
+/* Legacy defines */
+#define ADC_SR_EOC (ADC_SR_EOS)
+#define ADC_SR_JEOC (ADC_SR_JEOS)
+
+/******************* Bit definition for ADC_CR1 register ********************/
+#define ADC_CR1_AWDCH_Pos (0U)
+#define ADC_CR1_AWDCH_Msk (0x1FU << ADC_CR1_AWDCH_Pos) /*!< 0x0000001F */
+#define ADC_CR1_AWDCH ADC_CR1_AWDCH_Msk /*!< ADC analog watchdog 1 monitored channel selection */
+#define ADC_CR1_AWDCH_0 (0x01U << ADC_CR1_AWDCH_Pos) /*!< 0x00000001 */
+#define ADC_CR1_AWDCH_1 (0x02U << ADC_CR1_AWDCH_Pos) /*!< 0x00000002 */
+#define ADC_CR1_AWDCH_2 (0x04U << ADC_CR1_AWDCH_Pos) /*!< 0x00000004 */
+#define ADC_CR1_AWDCH_3 (0x08U << ADC_CR1_AWDCH_Pos) /*!< 0x00000008 */
+#define ADC_CR1_AWDCH_4 (0x10U << ADC_CR1_AWDCH_Pos) /*!< 0x00000010 */
+
+#define ADC_CR1_EOSIE_Pos (5U)
+#define ADC_CR1_EOSIE_Msk (0x1U << ADC_CR1_EOSIE_Pos) /*!< 0x00000020 */
+#define ADC_CR1_EOSIE ADC_CR1_EOSIE_Msk /*!< ADC group regular end of sequence conversions interrupt */
+#define ADC_CR1_AWDIE_Pos (6U)
+#define ADC_CR1_AWDIE_Msk (0x1U << ADC_CR1_AWDIE_Pos) /*!< 0x00000040 */
+#define ADC_CR1_AWDIE ADC_CR1_AWDIE_Msk /*!< ADC analog watchdog 1 interrupt */
+#define ADC_CR1_JEOSIE_Pos (7U)
+#define ADC_CR1_JEOSIE_Msk (0x1U << ADC_CR1_JEOSIE_Pos) /*!< 0x00000080 */
+#define ADC_CR1_JEOSIE ADC_CR1_JEOSIE_Msk /*!< ADC group injected end of sequence conversions interrupt */
+#define ADC_CR1_SCAN_Pos (8U)
+#define ADC_CR1_SCAN_Msk (0x1U << ADC_CR1_SCAN_Pos) /*!< 0x00000100 */
+#define ADC_CR1_SCAN ADC_CR1_SCAN_Msk /*!< ADC scan mode */
+#define ADC_CR1_AWDSGL_Pos (9U)
+#define ADC_CR1_AWDSGL_Msk (0x1U << ADC_CR1_AWDSGL_Pos) /*!< 0x00000200 */
+#define ADC_CR1_AWDSGL ADC_CR1_AWDSGL_Msk /*!< ADC analog watchdog 1 monitoring a single channel or all channels */
+#define ADC_CR1_JAUTO_Pos (10U)
+#define ADC_CR1_JAUTO_Msk (0x1U << ADC_CR1_JAUTO_Pos) /*!< 0x00000400 */
+#define ADC_CR1_JAUTO ADC_CR1_JAUTO_Msk /*!< ADC group injected automatic trigger mode */
+#define ADC_CR1_DISCEN_Pos (11U)
+#define ADC_CR1_DISCEN_Msk (0x1U << ADC_CR1_DISCEN_Pos) /*!< 0x00000800 */
+#define ADC_CR1_DISCEN ADC_CR1_DISCEN_Msk /*!< ADC group regular sequencer discontinuous mode */
+#define ADC_CR1_JDISCEN_Pos (12U)
+#define ADC_CR1_JDISCEN_Msk (0x1U << ADC_CR1_JDISCEN_Pos) /*!< 0x00001000 */
+#define ADC_CR1_JDISCEN ADC_CR1_JDISCEN_Msk /*!< ADC group injected sequencer discontinuous mode */
+
+#define ADC_CR1_DISCNUM_Pos (13U)
+#define ADC_CR1_DISCNUM_Msk (0x7U << ADC_CR1_DISCNUM_Pos) /*!< 0x0000E000 */
+#define ADC_CR1_DISCNUM ADC_CR1_DISCNUM_Msk /*!< ADC group regular sequencer discontinuous number of ranks */
+#define ADC_CR1_DISCNUM_0 (0x1U << ADC_CR1_DISCNUM_Pos) /*!< 0x00002000 */
+#define ADC_CR1_DISCNUM_1 (0x2U << ADC_CR1_DISCNUM_Pos) /*!< 0x00004000 */
+#define ADC_CR1_DISCNUM_2 (0x4U << ADC_CR1_DISCNUM_Pos) /*!< 0x00008000 */
+
+#define ADC_CR1_DUALMOD_Pos (16U)
+#define ADC_CR1_DUALMOD_Msk (0xFU << ADC_CR1_DUALMOD_Pos) /*!< 0x000F0000 */
+#define ADC_CR1_DUALMOD ADC_CR1_DUALMOD_Msk /*!< ADC multimode mode selection */
+#define ADC_CR1_DUALMOD_0 (0x1U << ADC_CR1_DUALMOD_Pos) /*!< 0x00010000 */
+#define ADC_CR1_DUALMOD_1 (0x2U << ADC_CR1_DUALMOD_Pos) /*!< 0x00020000 */
+#define ADC_CR1_DUALMOD_2 (0x4U << ADC_CR1_DUALMOD_Pos) /*!< 0x00040000 */
+#define ADC_CR1_DUALMOD_3 (0x8U << ADC_CR1_DUALMOD_Pos) /*!< 0x00080000 */
+
+#define ADC_CR1_JAWDEN_Pos (22U)
+#define ADC_CR1_JAWDEN_Msk (0x1U << ADC_CR1_JAWDEN_Pos) /*!< 0x00400000 */
+#define ADC_CR1_JAWDEN ADC_CR1_JAWDEN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group injected */
+#define ADC_CR1_AWDEN_Pos (23U)
+#define ADC_CR1_AWDEN_Msk (0x1U << ADC_CR1_AWDEN_Pos) /*!< 0x00800000 */
+#define ADC_CR1_AWDEN ADC_CR1_AWDEN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group regular */
+
+/* Legacy defines */
+#define ADC_CR1_EOCIE (ADC_CR1_EOSIE)
+#define ADC_CR1_JEOCIE (ADC_CR1_JEOSIE)
+
+/******************* Bit definition for ADC_CR2 register ********************/
+#define ADC_CR2_ADON_Pos (0U)
+#define ADC_CR2_ADON_Msk (0x1U << ADC_CR2_ADON_Pos) /*!< 0x00000001 */
+#define ADC_CR2_ADON ADC_CR2_ADON_Msk /*!< ADC enable */
+#define ADC_CR2_CONT_Pos (1U)
+#define ADC_CR2_CONT_Msk (0x1U << ADC_CR2_CONT_Pos) /*!< 0x00000002 */
+#define ADC_CR2_CONT ADC_CR2_CONT_Msk /*!< ADC group regular continuous conversion mode */
+#define ADC_CR2_CAL_Pos (2U)
+#define ADC_CR2_CAL_Msk (0x1U << ADC_CR2_CAL_Pos) /*!< 0x00000004 */
+#define ADC_CR2_CAL ADC_CR2_CAL_Msk /*!< ADC calibration start */
+#define ADC_CR2_RSTCAL_Pos (3U)
+#define ADC_CR2_RSTCAL_Msk (0x1U << ADC_CR2_RSTCAL_Pos) /*!< 0x00000008 */
+#define ADC_CR2_RSTCAL ADC_CR2_RSTCAL_Msk /*!< ADC calibration reset */
+#define ADC_CR2_DMA_Pos (8U)
+#define ADC_CR2_DMA_Msk (0x1U << ADC_CR2_DMA_Pos) /*!< 0x00000100 */
+#define ADC_CR2_DMA ADC_CR2_DMA_Msk /*!< ADC DMA transfer enable */
+#define ADC_CR2_ALIGN_Pos (11U)
+#define ADC_CR2_ALIGN_Msk (0x1U << ADC_CR2_ALIGN_Pos) /*!< 0x00000800 */
+#define ADC_CR2_ALIGN ADC_CR2_ALIGN_Msk /*!< ADC data alignement */
+
+#define ADC_CR2_JEXTSEL_Pos (12U)
+#define ADC_CR2_JEXTSEL_Msk (0x7U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00007000 */
+#define ADC_CR2_JEXTSEL ADC_CR2_JEXTSEL_Msk /*!< ADC group injected external trigger source */
+#define ADC_CR2_JEXTSEL_0 (0x1U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00001000 */
+#define ADC_CR2_JEXTSEL_1 (0x2U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00002000 */
+#define ADC_CR2_JEXTSEL_2 (0x4U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00004000 */
+
+#define ADC_CR2_JEXTTRIG_Pos (15U)
+#define ADC_CR2_JEXTTRIG_Msk (0x1U << ADC_CR2_JEXTTRIG_Pos) /*!< 0x00008000 */
+#define ADC_CR2_JEXTTRIG ADC_CR2_JEXTTRIG_Msk /*!< ADC group injected external trigger enable */
+
+#define ADC_CR2_EXTSEL_Pos (17U)
+#define ADC_CR2_EXTSEL_Msk (0x7U << ADC_CR2_EXTSEL_Pos) /*!< 0x000E0000 */
+#define ADC_CR2_EXTSEL ADC_CR2_EXTSEL_Msk /*!< ADC group regular external trigger source */
+#define ADC_CR2_EXTSEL_0 (0x1U << ADC_CR2_EXTSEL_Pos) /*!< 0x00020000 */
+#define ADC_CR2_EXTSEL_1 (0x2U << ADC_CR2_EXTSEL_Pos) /*!< 0x00040000 */
+#define ADC_CR2_EXTSEL_2 (0x4U << ADC_CR2_EXTSEL_Pos) /*!< 0x00080000 */
+
+#define ADC_CR2_EXTTRIG_Pos (20U)
+#define ADC_CR2_EXTTRIG_Msk (0x1U << ADC_CR2_EXTTRIG_Pos) /*!< 0x00100000 */
+#define ADC_CR2_EXTTRIG ADC_CR2_EXTTRIG_Msk /*!< ADC group regular external trigger enable */
+#define ADC_CR2_JSWSTART_Pos (21U)
+#define ADC_CR2_JSWSTART_Msk (0x1U << ADC_CR2_JSWSTART_Pos) /*!< 0x00200000 */
+#define ADC_CR2_JSWSTART ADC_CR2_JSWSTART_Msk /*!< ADC group injected conversion start */
+#define ADC_CR2_SWSTART_Pos (22U)
+#define ADC_CR2_SWSTART_Msk (0x1U << ADC_CR2_SWSTART_Pos) /*!< 0x00400000 */
+#define ADC_CR2_SWSTART ADC_CR2_SWSTART_Msk /*!< ADC group regular conversion start */
+#define ADC_CR2_TSVREFE_Pos (23U)
+#define ADC_CR2_TSVREFE_Msk (0x1U << ADC_CR2_TSVREFE_Pos) /*!< 0x00800000 */
+#define ADC_CR2_TSVREFE ADC_CR2_TSVREFE_Msk /*!< ADC internal path to VrefInt and temperature sensor enable */
+
+/****************** Bit definition for ADC_SMPR1 register *******************/
+#define ADC_SMPR1_SMP10_Pos (0U)
+#define ADC_SMPR1_SMP10_Msk (0x7U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000007 */
+#define ADC_SMPR1_SMP10 ADC_SMPR1_SMP10_Msk /*!< ADC channel 10 sampling time selection */
+#define ADC_SMPR1_SMP10_0 (0x1U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000001 */
+#define ADC_SMPR1_SMP10_1 (0x2U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000002 */
+#define ADC_SMPR1_SMP10_2 (0x4U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000004 */
+
+#define ADC_SMPR1_SMP11_Pos (3U)
+#define ADC_SMPR1_SMP11_Msk (0x7U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000038 */
+#define ADC_SMPR1_SMP11 ADC_SMPR1_SMP11_Msk /*!< ADC channel 11 sampling time selection */
+#define ADC_SMPR1_SMP11_0 (0x1U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000008 */
+#define ADC_SMPR1_SMP11_1 (0x2U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000010 */
+#define ADC_SMPR1_SMP11_2 (0x4U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000020 */
+
+#define ADC_SMPR1_SMP12_Pos (6U)
+#define ADC_SMPR1_SMP12_Msk (0x7U << ADC_SMPR1_SMP12_Pos) /*!< 0x000001C0 */
+#define ADC_SMPR1_SMP12 ADC_SMPR1_SMP12_Msk /*!< ADC channel 12 sampling time selection */
+#define ADC_SMPR1_SMP12_0 (0x1U << ADC_SMPR1_SMP12_Pos) /*!< 0x00000040 */
+#define ADC_SMPR1_SMP12_1 (0x2U << ADC_SMPR1_SMP12_Pos) /*!< 0x00000080 */
+#define ADC_SMPR1_SMP12_2 (0x4U << ADC_SMPR1_SMP12_Pos) /*!< 0x00000100 */
+
+#define ADC_SMPR1_SMP13_Pos (9U)
+#define ADC_SMPR1_SMP13_Msk (0x7U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000E00 */
+#define ADC_SMPR1_SMP13 ADC_SMPR1_SMP13_Msk /*!< ADC channel 13 sampling time selection */
+#define ADC_SMPR1_SMP13_0 (0x1U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000200 */
+#define ADC_SMPR1_SMP13_1 (0x2U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000400 */
+#define ADC_SMPR1_SMP13_2 (0x4U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000800 */
+
+#define ADC_SMPR1_SMP14_Pos (12U)
+#define ADC_SMPR1_SMP14_Msk (0x7U << ADC_SMPR1_SMP14_Pos) /*!< 0x00007000 */
+#define ADC_SMPR1_SMP14 ADC_SMPR1_SMP14_Msk /*!< ADC channel 14 sampling time selection */
+#define ADC_SMPR1_SMP14_0 (0x1U << ADC_SMPR1_SMP14_Pos) /*!< 0x00001000 */
+#define ADC_SMPR1_SMP14_1 (0x2U << ADC_SMPR1_SMP14_Pos) /*!< 0x00002000 */
+#define ADC_SMPR1_SMP14_2 (0x4U << ADC_SMPR1_SMP14_Pos) /*!< 0x00004000 */
+
+#define ADC_SMPR1_SMP15_Pos (15U)
+#define ADC_SMPR1_SMP15_Msk (0x7U << ADC_SMPR1_SMP15_Pos) /*!< 0x00038000 */
+#define ADC_SMPR1_SMP15 ADC_SMPR1_SMP15_Msk /*!< ADC channel 15 sampling time selection */
+#define ADC_SMPR1_SMP15_0 (0x1U << ADC_SMPR1_SMP15_Pos) /*!< 0x00008000 */
+#define ADC_SMPR1_SMP15_1 (0x2U << ADC_SMPR1_SMP15_Pos) /*!< 0x00010000 */
+#define ADC_SMPR1_SMP15_2 (0x4U << ADC_SMPR1_SMP15_Pos) /*!< 0x00020000 */
+
+#define ADC_SMPR1_SMP16_Pos (18U)
+#define ADC_SMPR1_SMP16_Msk (0x7U << ADC_SMPR1_SMP16_Pos) /*!< 0x001C0000 */
+#define ADC_SMPR1_SMP16 ADC_SMPR1_SMP16_Msk /*!< ADC channel 16 sampling time selection */
+#define ADC_SMPR1_SMP16_0 (0x1U << ADC_SMPR1_SMP16_Pos) /*!< 0x00040000 */
+#define ADC_SMPR1_SMP16_1 (0x2U << ADC_SMPR1_SMP16_Pos) /*!< 0x00080000 */
+#define ADC_SMPR1_SMP16_2 (0x4U << ADC_SMPR1_SMP16_Pos) /*!< 0x00100000 */
+
+#define ADC_SMPR1_SMP17_Pos (21U)
+#define ADC_SMPR1_SMP17_Msk (0x7U << ADC_SMPR1_SMP17_Pos) /*!< 0x00E00000 */
+#define ADC_SMPR1_SMP17 ADC_SMPR1_SMP17_Msk /*!< ADC channel 17 sampling time selection */
+#define ADC_SMPR1_SMP17_0 (0x1U << ADC_SMPR1_SMP17_Pos) /*!< 0x00200000 */
+#define ADC_SMPR1_SMP17_1 (0x2U << ADC_SMPR1_SMP17_Pos) /*!< 0x00400000 */
+#define ADC_SMPR1_SMP17_2 (0x4U << ADC_SMPR1_SMP17_Pos) /*!< 0x00800000 */
+
+/****************** Bit definition for ADC_SMPR2 register *******************/
+#define ADC_SMPR2_SMP0_Pos (0U)
+#define ADC_SMPR2_SMP0_Msk (0x7U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000007 */
+#define ADC_SMPR2_SMP0 ADC_SMPR2_SMP0_Msk /*!< ADC channel 0 sampling time selection */
+#define ADC_SMPR2_SMP0_0 (0x1U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000001 */
+#define ADC_SMPR2_SMP0_1 (0x2U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000002 */
+#define ADC_SMPR2_SMP0_2 (0x4U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000004 */
+
+#define ADC_SMPR2_SMP1_Pos (3U)
+#define ADC_SMPR2_SMP1_Msk (0x7U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000038 */
+#define ADC_SMPR2_SMP1 ADC_SMPR2_SMP1_Msk /*!< ADC channel 1 sampling time selection */
+#define ADC_SMPR2_SMP1_0 (0x1U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000008 */
+#define ADC_SMPR2_SMP1_1 (0x2U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000010 */
+#define ADC_SMPR2_SMP1_2 (0x4U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000020 */
+
+#define ADC_SMPR2_SMP2_Pos (6U)
+#define ADC_SMPR2_SMP2_Msk (0x7U << ADC_SMPR2_SMP2_Pos) /*!< 0x000001C0 */
+#define ADC_SMPR2_SMP2 ADC_SMPR2_SMP2_Msk /*!< ADC channel 2 sampling time selection */
+#define ADC_SMPR2_SMP2_0 (0x1U << ADC_SMPR2_SMP2_Pos) /*!< 0x00000040 */
+#define ADC_SMPR2_SMP2_1 (0x2U << ADC_SMPR2_SMP2_Pos) /*!< 0x00000080 */
+#define ADC_SMPR2_SMP2_2 (0x4U << ADC_SMPR2_SMP2_Pos) /*!< 0x00000100 */
+
+#define ADC_SMPR2_SMP3_Pos (9U)
+#define ADC_SMPR2_SMP3_Msk (0x7U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000E00 */
+#define ADC_SMPR2_SMP3 ADC_SMPR2_SMP3_Msk /*!< ADC channel 3 sampling time selection */
+#define ADC_SMPR2_SMP3_0 (0x1U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000200 */
+#define ADC_SMPR2_SMP3_1 (0x2U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000400 */
+#define ADC_SMPR2_SMP3_2 (0x4U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000800 */
+
+#define ADC_SMPR2_SMP4_Pos (12U)
+#define ADC_SMPR2_SMP4_Msk (0x7U << ADC_SMPR2_SMP4_Pos) /*!< 0x00007000 */
+#define ADC_SMPR2_SMP4 ADC_SMPR2_SMP4_Msk /*!< ADC channel 4 sampling time selection */
+#define ADC_SMPR2_SMP4_0 (0x1U << ADC_SMPR2_SMP4_Pos) /*!< 0x00001000 */
+#define ADC_SMPR2_SMP4_1 (0x2U << ADC_SMPR2_SMP4_Pos) /*!< 0x00002000 */
+#define ADC_SMPR2_SMP4_2 (0x4U << ADC_SMPR2_SMP4_Pos) /*!< 0x00004000 */
+
+#define ADC_SMPR2_SMP5_Pos (15U)
+#define ADC_SMPR2_SMP5_Msk (0x7U << ADC_SMPR2_SMP5_Pos) /*!< 0x00038000 */
+#define ADC_SMPR2_SMP5 ADC_SMPR2_SMP5_Msk /*!< ADC channel 5 sampling time selection */
+#define ADC_SMPR2_SMP5_0 (0x1U << ADC_SMPR2_SMP5_Pos) /*!< 0x00008000 */
+#define ADC_SMPR2_SMP5_1 (0x2U << ADC_SMPR2_SMP5_Pos) /*!< 0x00010000 */
+#define ADC_SMPR2_SMP5_2 (0x4U << ADC_SMPR2_SMP5_Pos) /*!< 0x00020000 */
+
+#define ADC_SMPR2_SMP6_Pos (18U)
+#define ADC_SMPR2_SMP6_Msk (0x7U << ADC_SMPR2_SMP6_Pos) /*!< 0x001C0000 */
+#define ADC_SMPR2_SMP6 ADC_SMPR2_SMP6_Msk /*!< ADC channel 6 sampling time selection */
+#define ADC_SMPR2_SMP6_0 (0x1U << ADC_SMPR2_SMP6_Pos) /*!< 0x00040000 */
+#define ADC_SMPR2_SMP6_1 (0x2U << ADC_SMPR2_SMP6_Pos) /*!< 0x00080000 */
+#define ADC_SMPR2_SMP6_2 (0x4U << ADC_SMPR2_SMP6_Pos) /*!< 0x00100000 */
+
+#define ADC_SMPR2_SMP7_Pos (21U)
+#define ADC_SMPR2_SMP7_Msk (0x7U << ADC_SMPR2_SMP7_Pos) /*!< 0x00E00000 */
+#define ADC_SMPR2_SMP7 ADC_SMPR2_SMP7_Msk /*!< ADC channel 7 sampling time selection */
+#define ADC_SMPR2_SMP7_0 (0x1U << ADC_SMPR2_SMP7_Pos) /*!< 0x00200000 */
+#define ADC_SMPR2_SMP7_1 (0x2U << ADC_SMPR2_SMP7_Pos) /*!< 0x00400000 */
+#define ADC_SMPR2_SMP7_2 (0x4U << ADC_SMPR2_SMP7_Pos) /*!< 0x00800000 */
+
+#define ADC_SMPR2_SMP8_Pos (24U)
+#define ADC_SMPR2_SMP8_Msk (0x7U << ADC_SMPR2_SMP8_Pos) /*!< 0x07000000 */
+#define ADC_SMPR2_SMP8 ADC_SMPR2_SMP8_Msk /*!< ADC channel 8 sampling time selection */
+#define ADC_SMPR2_SMP8_0 (0x1U << ADC_SMPR2_SMP8_Pos) /*!< 0x01000000 */
+#define ADC_SMPR2_SMP8_1 (0x2U << ADC_SMPR2_SMP8_Pos) /*!< 0x02000000 */
+#define ADC_SMPR2_SMP8_2 (0x4U << ADC_SMPR2_SMP8_Pos) /*!< 0x04000000 */
+
+#define ADC_SMPR2_SMP9_Pos (27U)
+#define ADC_SMPR2_SMP9_Msk (0x7U << ADC_SMPR2_SMP9_Pos) /*!< 0x38000000 */
+#define ADC_SMPR2_SMP9 ADC_SMPR2_SMP9_Msk /*!< ADC channel 9 sampling time selection */
+#define ADC_SMPR2_SMP9_0 (0x1U << ADC_SMPR2_SMP9_Pos) /*!< 0x08000000 */
+#define ADC_SMPR2_SMP9_1 (0x2U << ADC_SMPR2_SMP9_Pos) /*!< 0x10000000 */
+#define ADC_SMPR2_SMP9_2 (0x4U << ADC_SMPR2_SMP9_Pos) /*!< 0x20000000 */
+
+/****************** Bit definition for ADC_JOFR1 register *******************/
+#define ADC_JOFR1_JOFFSET1_Pos (0U)
+#define ADC_JOFR1_JOFFSET1_Msk (0xFFFU << ADC_JOFR1_JOFFSET1_Pos) /*!< 0x00000FFF */
+#define ADC_JOFR1_JOFFSET1 ADC_JOFR1_JOFFSET1_Msk /*!< ADC group injected sequencer rank 1 offset value */
+
+/****************** Bit definition for ADC_JOFR2 register *******************/
+#define ADC_JOFR2_JOFFSET2_Pos (0U)
+#define ADC_JOFR2_JOFFSET2_Msk (0xFFFU << ADC_JOFR2_JOFFSET2_Pos) /*!< 0x00000FFF */
+#define ADC_JOFR2_JOFFSET2 ADC_JOFR2_JOFFSET2_Msk /*!< ADC group injected sequencer rank 2 offset value */
+
+/****************** Bit definition for ADC_JOFR3 register *******************/
+#define ADC_JOFR3_JOFFSET3_Pos (0U)
+#define ADC_JOFR3_JOFFSET3_Msk (0xFFFU << ADC_JOFR3_JOFFSET3_Pos) /*!< 0x00000FFF */
+#define ADC_JOFR3_JOFFSET3 ADC_JOFR3_JOFFSET3_Msk /*!< ADC group injected sequencer rank 3 offset value */
+
+/****************** Bit definition for ADC_JOFR4 register *******************/
+#define ADC_JOFR4_JOFFSET4_Pos (0U)
+#define ADC_JOFR4_JOFFSET4_Msk (0xFFFU << ADC_JOFR4_JOFFSET4_Pos) /*!< 0x00000FFF */
+#define ADC_JOFR4_JOFFSET4 ADC_JOFR4_JOFFSET4_Msk /*!< ADC group injected sequencer rank 4 offset value */
+
+/******************* Bit definition for ADC_HTR register ********************/
+#define ADC_HTR_HT_Pos (0U)
+#define ADC_HTR_HT_Msk (0xFFFU << ADC_HTR_HT_Pos) /*!< 0x00000FFF */
+#define ADC_HTR_HT ADC_HTR_HT_Msk /*!< ADC analog watchdog 1 threshold high */
+
+/******************* Bit definition for ADC_LTR register ********************/
+#define ADC_LTR_LT_Pos (0U)
+#define ADC_LTR_LT_Msk (0xFFFU << ADC_LTR_LT_Pos) /*!< 0x00000FFF */
+#define ADC_LTR_LT ADC_LTR_LT_Msk /*!< ADC analog watchdog 1 threshold low */
+
+/******************* Bit definition for ADC_SQR1 register *******************/
+#define ADC_SQR1_SQ13_Pos (0U)
+#define ADC_SQR1_SQ13_Msk (0x1FU << ADC_SQR1_SQ13_Pos) /*!< 0x0000001F */
+#define ADC_SQR1_SQ13 ADC_SQR1_SQ13_Msk /*!< ADC group regular sequencer rank 13 */
+#define ADC_SQR1_SQ13_0 (0x01U << ADC_SQR1_SQ13_Pos) /*!< 0x00000001 */
+#define ADC_SQR1_SQ13_1 (0x02U << ADC_SQR1_SQ13_Pos) /*!< 0x00000002 */
+#define ADC_SQR1_SQ13_2 (0x04U << ADC_SQR1_SQ13_Pos) /*!< 0x00000004 */
+#define ADC_SQR1_SQ13_3 (0x08U << ADC_SQR1_SQ13_Pos) /*!< 0x00000008 */
+#define ADC_SQR1_SQ13_4 (0x10U << ADC_SQR1_SQ13_Pos) /*!< 0x00000010 */
+
+#define ADC_SQR1_SQ14_Pos (5U)
+#define ADC_SQR1_SQ14_Msk (0x1FU << ADC_SQR1_SQ14_Pos) /*!< 0x000003E0 */
+#define ADC_SQR1_SQ14 ADC_SQR1_SQ14_Msk /*!< ADC group regular sequencer rank 14 */
+#define ADC_SQR1_SQ14_0 (0x01U << ADC_SQR1_SQ14_Pos) /*!< 0x00000020 */
+#define ADC_SQR1_SQ14_1 (0x02U << ADC_SQR1_SQ14_Pos) /*!< 0x00000040 */
+#define ADC_SQR1_SQ14_2 (0x04U << ADC_SQR1_SQ14_Pos) /*!< 0x00000080 */
+#define ADC_SQR1_SQ14_3 (0x08U << ADC_SQR1_SQ14_Pos) /*!< 0x00000100 */
+#define ADC_SQR1_SQ14_4 (0x10U << ADC_SQR1_SQ14_Pos) /*!< 0x00000200 */
+
+#define ADC_SQR1_SQ15_Pos (10U)
+#define ADC_SQR1_SQ15_Msk (0x1FU << ADC_SQR1_SQ15_Pos) /*!< 0x00007C00 */
+#define ADC_SQR1_SQ15 ADC_SQR1_SQ15_Msk /*!< ADC group regular sequencer rank 15 */
+#define ADC_SQR1_SQ15_0 (0x01U << ADC_SQR1_SQ15_Pos) /*!< 0x00000400 */
+#define ADC_SQR1_SQ15_1 (0x02U << ADC_SQR1_SQ15_Pos) /*!< 0x00000800 */
+#define ADC_SQR1_SQ15_2 (0x04U << ADC_SQR1_SQ15_Pos) /*!< 0x00001000 */
+#define ADC_SQR1_SQ15_3 (0x08U << ADC_SQR1_SQ15_Pos) /*!< 0x00002000 */
+#define ADC_SQR1_SQ15_4 (0x10U << ADC_SQR1_SQ15_Pos) /*!< 0x00004000 */
+
+#define ADC_SQR1_SQ16_Pos (15U)
+#define ADC_SQR1_SQ16_Msk (0x1FU << ADC_SQR1_SQ16_Pos) /*!< 0x000F8000 */
+#define ADC_SQR1_SQ16 ADC_SQR1_SQ16_Msk /*!< ADC group regular sequencer rank 16 */
+#define ADC_SQR1_SQ16_0 (0x01U << ADC_SQR1_SQ16_Pos) /*!< 0x00008000 */
+#define ADC_SQR1_SQ16_1 (0x02U << ADC_SQR1_SQ16_Pos) /*!< 0x00010000 */
+#define ADC_SQR1_SQ16_2 (0x04U << ADC_SQR1_SQ16_Pos) /*!< 0x00020000 */
+#define ADC_SQR1_SQ16_3 (0x08U << ADC_SQR1_SQ16_Pos) /*!< 0x00040000 */
+#define ADC_SQR1_SQ16_4 (0x10U << ADC_SQR1_SQ16_Pos) /*!< 0x00080000 */
+
+#define ADC_SQR1_L_Pos (20U)
+#define ADC_SQR1_L_Msk (0xFU << ADC_SQR1_L_Pos) /*!< 0x00F00000 */
+#define ADC_SQR1_L ADC_SQR1_L_Msk /*!< ADC group regular sequencer scan length */
+#define ADC_SQR1_L_0 (0x1U << ADC_SQR1_L_Pos) /*!< 0x00100000 */
+#define ADC_SQR1_L_1 (0x2U << ADC_SQR1_L_Pos) /*!< 0x00200000 */
+#define ADC_SQR1_L_2 (0x4U << ADC_SQR1_L_Pos) /*!< 0x00400000 */
+#define ADC_SQR1_L_3 (0x8U << ADC_SQR1_L_Pos) /*!< 0x00800000 */
+
+/******************* Bit definition for ADC_SQR2 register *******************/
+#define ADC_SQR2_SQ7_Pos (0U)
+#define ADC_SQR2_SQ7_Msk (0x1FU << ADC_SQR2_SQ7_Pos) /*!< 0x0000001F */
+#define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk /*!< ADC group regular sequencer rank 7 */
+#define ADC_SQR2_SQ7_0 (0x01U << ADC_SQR2_SQ7_Pos) /*!< 0x00000001 */
+#define ADC_SQR2_SQ7_1 (0x02U << ADC_SQR2_SQ7_Pos) /*!< 0x00000002 */
+#define ADC_SQR2_SQ7_2 (0x04U << ADC_SQR2_SQ7_Pos) /*!< 0x00000004 */
+#define ADC_SQR2_SQ7_3 (0x08U << ADC_SQR2_SQ7_Pos) /*!< 0x00000008 */
+#define ADC_SQR2_SQ7_4 (0x10U << ADC_SQR2_SQ7_Pos) /*!< 0x00000010 */
+
+#define ADC_SQR2_SQ8_Pos (5U)
+#define ADC_SQR2_SQ8_Msk (0x1FU << ADC_SQR2_SQ8_Pos) /*!< 0x000003E0 */
+#define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk /*!< ADC group regular sequencer rank 8 */
+#define ADC_SQR2_SQ8_0 (0x01U << ADC_SQR2_SQ8_Pos) /*!< 0x00000020 */
+#define ADC_SQR2_SQ8_1 (0x02U << ADC_SQR2_SQ8_Pos) /*!< 0x00000040 */
+#define ADC_SQR2_SQ8_2 (0x04U << ADC_SQR2_SQ8_Pos) /*!< 0x00000080 */
+#define ADC_SQR2_SQ8_3 (0x08U << ADC_SQR2_SQ8_Pos) /*!< 0x00000100 */
+#define ADC_SQR2_SQ8_4 (0x10U << ADC_SQR2_SQ8_Pos) /*!< 0x00000200 */
+
+#define ADC_SQR2_SQ9_Pos (10U)
+#define ADC_SQR2_SQ9_Msk (0x1FU << ADC_SQR2_SQ9_Pos) /*!< 0x00007C00 */
+#define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk /*!< ADC group regular sequencer rank 9 */
+#define ADC_SQR2_SQ9_0 (0x01U << ADC_SQR2_SQ9_Pos) /*!< 0x00000400 */
+#define ADC_SQR2_SQ9_1 (0x02U << ADC_SQR2_SQ9_Pos) /*!< 0x00000800 */
+#define ADC_SQR2_SQ9_2 (0x04U << ADC_SQR2_SQ9_Pos) /*!< 0x00001000 */
+#define ADC_SQR2_SQ9_3 (0x08U << ADC_SQR2_SQ9_Pos) /*!< 0x00002000 */
+#define ADC_SQR2_SQ9_4 (0x10U << ADC_SQR2_SQ9_Pos) /*!< 0x00004000 */
+
+#define ADC_SQR2_SQ10_Pos (15U)
+#define ADC_SQR2_SQ10_Msk (0x1FU << ADC_SQR2_SQ10_Pos) /*!< 0x000F8000 */
+#define ADC_SQR2_SQ10 ADC_SQR2_SQ10_Msk /*!< ADC group regular sequencer rank 10 */
+#define ADC_SQR2_SQ10_0 (0x01U << ADC_SQR2_SQ10_Pos) /*!< 0x00008000 */
+#define ADC_SQR2_SQ10_1 (0x02U << ADC_SQR2_SQ10_Pos) /*!< 0x00010000 */
+#define ADC_SQR2_SQ10_2 (0x04U << ADC_SQR2_SQ10_Pos) /*!< 0x00020000 */
+#define ADC_SQR2_SQ10_3 (0x08U << ADC_SQR2_SQ10_Pos) /*!< 0x00040000 */
+#define ADC_SQR2_SQ10_4 (0x10U << ADC_SQR2_SQ10_Pos) /*!< 0x00080000 */
+
+#define ADC_SQR2_SQ11_Pos (20U)
+#define ADC_SQR2_SQ11_Msk (0x1FU << ADC_SQR2_SQ11_Pos) /*!< 0x01F00000 */
+#define ADC_SQR2_SQ11 ADC_SQR2_SQ11_Msk /*!< ADC group regular sequencer rank 1 */
+#define ADC_SQR2_SQ11_0 (0x01U << ADC_SQR2_SQ11_Pos) /*!< 0x00100000 */
+#define ADC_SQR2_SQ11_1 (0x02U << ADC_SQR2_SQ11_Pos) /*!< 0x00200000 */
+#define ADC_SQR2_SQ11_2 (0x04U << ADC_SQR2_SQ11_Pos) /*!< 0x00400000 */
+#define ADC_SQR2_SQ11_3 (0x08U << ADC_SQR2_SQ11_Pos) /*!< 0x00800000 */
+#define ADC_SQR2_SQ11_4 (0x10U << ADC_SQR2_SQ11_Pos) /*!< 0x01000000 */
+
+#define ADC_SQR2_SQ12_Pos (25U)
+#define ADC_SQR2_SQ12_Msk (0x1FU << ADC_SQR2_SQ12_Pos) /*!< 0x3E000000 */
+#define ADC_SQR2_SQ12 ADC_SQR2_SQ12_Msk /*!< ADC group regular sequencer rank 12 */
+#define ADC_SQR2_SQ12_0 (0x01U << ADC_SQR2_SQ12_Pos) /*!< 0x02000000 */
+#define ADC_SQR2_SQ12_1 (0x02U << ADC_SQR2_SQ12_Pos) /*!< 0x04000000 */
+#define ADC_SQR2_SQ12_2 (0x04U << ADC_SQR2_SQ12_Pos) /*!< 0x08000000 */
+#define ADC_SQR2_SQ12_3 (0x08U << ADC_SQR2_SQ12_Pos) /*!< 0x10000000 */
+#define ADC_SQR2_SQ12_4 (0x10U << ADC_SQR2_SQ12_Pos) /*!< 0x20000000 */
+
+/******************* Bit definition for ADC_SQR3 register *******************/
+#define ADC_SQR3_SQ1_Pos (0U)
+#define ADC_SQR3_SQ1_Msk (0x1FU << ADC_SQR3_SQ1_Pos) /*!< 0x0000001F */
+#define ADC_SQR3_SQ1 ADC_SQR3_SQ1_Msk /*!< ADC group regular sequencer rank 1 */
+#define ADC_SQR3_SQ1_0 (0x01U << ADC_SQR3_SQ1_Pos) /*!< 0x00000001 */
+#define ADC_SQR3_SQ1_1 (0x02U << ADC_SQR3_SQ1_Pos) /*!< 0x00000002 */
+#define ADC_SQR3_SQ1_2 (0x04U << ADC_SQR3_SQ1_Pos) /*!< 0x00000004 */
+#define ADC_SQR3_SQ1_3 (0x08U << ADC_SQR3_SQ1_Pos) /*!< 0x00000008 */
+#define ADC_SQR3_SQ1_4 (0x10U << ADC_SQR3_SQ1_Pos) /*!< 0x00000010 */
+
+#define ADC_SQR3_SQ2_Pos (5U)
+#define ADC_SQR3_SQ2_Msk (0x1FU << ADC_SQR3_SQ2_Pos) /*!< 0x000003E0 */
+#define ADC_SQR3_SQ2 ADC_SQR3_SQ2_Msk /*!< ADC group regular sequencer rank 2 */
+#define ADC_SQR3_SQ2_0 (0x01U << ADC_SQR3_SQ2_Pos) /*!< 0x00000020 */
+#define ADC_SQR3_SQ2_1 (0x02U << ADC_SQR3_SQ2_Pos) /*!< 0x00000040 */
+#define ADC_SQR3_SQ2_2 (0x04U << ADC_SQR3_SQ2_Pos) /*!< 0x00000080 */
+#define ADC_SQR3_SQ2_3 (0x08U << ADC_SQR3_SQ2_Pos) /*!< 0x00000100 */
+#define ADC_SQR3_SQ2_4 (0x10U << ADC_SQR3_SQ2_Pos) /*!< 0x00000200 */
+
+#define ADC_SQR3_SQ3_Pos (10U)
+#define ADC_SQR3_SQ3_Msk (0x1FU << ADC_SQR3_SQ3_Pos) /*!< 0x00007C00 */
+#define ADC_SQR3_SQ3 ADC_SQR3_SQ3_Msk /*!< ADC group regular sequencer rank 3 */
+#define ADC_SQR3_SQ3_0 (0x01U << ADC_SQR3_SQ3_Pos) /*!< 0x00000400 */
+#define ADC_SQR3_SQ3_1 (0x02U << ADC_SQR3_SQ3_Pos) /*!< 0x00000800 */
+#define ADC_SQR3_SQ3_2 (0x04U << ADC_SQR3_SQ3_Pos) /*!< 0x00001000 */
+#define ADC_SQR3_SQ3_3 (0x08U << ADC_SQR3_SQ3_Pos) /*!< 0x00002000 */
+#define ADC_SQR3_SQ3_4 (0x10U << ADC_SQR3_SQ3_Pos) /*!< 0x00004000 */
+
+#define ADC_SQR3_SQ4_Pos (15U)
+#define ADC_SQR3_SQ4_Msk (0x1FU << ADC_SQR3_SQ4_Pos) /*!< 0x000F8000 */
+#define ADC_SQR3_SQ4 ADC_SQR3_SQ4_Msk /*!< ADC group regular sequencer rank 4 */
+#define ADC_SQR3_SQ4_0 (0x01U << ADC_SQR3_SQ4_Pos) /*!< 0x00008000 */
+#define ADC_SQR3_SQ4_1 (0x02U << ADC_SQR3_SQ4_Pos) /*!< 0x00010000 */
+#define ADC_SQR3_SQ4_2 (0x04U << ADC_SQR3_SQ4_Pos) /*!< 0x00020000 */
+#define ADC_SQR3_SQ4_3 (0x08U << ADC_SQR3_SQ4_Pos) /*!< 0x00040000 */
+#define ADC_SQR3_SQ4_4 (0x10U << ADC_SQR3_SQ4_Pos) /*!< 0x00080000 */
+
+#define ADC_SQR3_SQ5_Pos (20U)
+#define ADC_SQR3_SQ5_Msk (0x1FU << ADC_SQR3_SQ5_Pos) /*!< 0x01F00000 */
+#define ADC_SQR3_SQ5 ADC_SQR3_SQ5_Msk /*!< ADC group regular sequencer rank 5 */
+#define ADC_SQR3_SQ5_0 (0x01U << ADC_SQR3_SQ5_Pos) /*!< 0x00100000 */
+#define ADC_SQR3_SQ5_1 (0x02U << ADC_SQR3_SQ5_Pos) /*!< 0x00200000 */
+#define ADC_SQR3_SQ5_2 (0x04U << ADC_SQR3_SQ5_Pos) /*!< 0x00400000 */
+#define ADC_SQR3_SQ5_3 (0x08U << ADC_SQR3_SQ5_Pos) /*!< 0x00800000 */
+#define ADC_SQR3_SQ5_4 (0x10U << ADC_SQR3_SQ5_Pos) /*!< 0x01000000 */
+
+#define ADC_SQR3_SQ6_Pos (25U)
+#define ADC_SQR3_SQ6_Msk (0x1FU << ADC_SQR3_SQ6_Pos) /*!< 0x3E000000 */
+#define ADC_SQR3_SQ6 ADC_SQR3_SQ6_Msk /*!< ADC group regular sequencer rank 6 */
+#define ADC_SQR3_SQ6_0 (0x01U << ADC_SQR3_SQ6_Pos) /*!< 0x02000000 */
+#define ADC_SQR3_SQ6_1 (0x02U << ADC_SQR3_SQ6_Pos) /*!< 0x04000000 */
+#define ADC_SQR3_SQ6_2 (0x04U << ADC_SQR3_SQ6_Pos) /*!< 0x08000000 */
+#define ADC_SQR3_SQ6_3 (0x08U << ADC_SQR3_SQ6_Pos) /*!< 0x10000000 */
+#define ADC_SQR3_SQ6_4 (0x10U << ADC_SQR3_SQ6_Pos) /*!< 0x20000000 */
+
+/******************* Bit definition for ADC_JSQR register *******************/
+#define ADC_JSQR_JSQ1_Pos (0U)
+#define ADC_JSQR_JSQ1_Msk (0x1FU << ADC_JSQR_JSQ1_Pos) /*!< 0x0000001F */
+#define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!< ADC group injected sequencer rank 1 */
+#define ADC_JSQR_JSQ1_0 (0x01U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000001 */
+#define ADC_JSQR_JSQ1_1 (0x02U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000002 */
+#define ADC_JSQR_JSQ1_2 (0x04U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000004 */
+#define ADC_JSQR_JSQ1_3 (0x08U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000008 */
+#define ADC_JSQR_JSQ1_4 (0x10U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000010 */
+
+#define ADC_JSQR_JSQ2_Pos (5U)
+#define ADC_JSQR_JSQ2_Msk (0x1FU << ADC_JSQR_JSQ2_Pos) /*!< 0x000003E0 */
+#define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!< ADC group injected sequencer rank 2 */
+#define ADC_JSQR_JSQ2_0 (0x01U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000020 */
+#define ADC_JSQR_JSQ2_1 (0x02U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000040 */
+#define ADC_JSQR_JSQ2_2 (0x04U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000080 */
+#define ADC_JSQR_JSQ2_3 (0x08U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000100 */
+#define ADC_JSQR_JSQ2_4 (0x10U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000200 */
+
+#define ADC_JSQR_JSQ3_Pos (10U)
+#define ADC_JSQR_JSQ3_Msk (0x1FU << ADC_JSQR_JSQ3_Pos) /*!< 0x00007C00 */
+#define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!< ADC group injected sequencer rank 3 */
+#define ADC_JSQR_JSQ3_0 (0x01U << ADC_JSQR_JSQ3_Pos) /*!< 0x00000400 */
+#define ADC_JSQR_JSQ3_1 (0x02U << ADC_JSQR_JSQ3_Pos) /*!< 0x00000800 */
+#define ADC_JSQR_JSQ3_2 (0x04U << ADC_JSQR_JSQ3_Pos) /*!< 0x00001000 */
+#define ADC_JSQR_JSQ3_3 (0x08U << ADC_JSQR_JSQ3_Pos) /*!< 0x00002000 */
+#define ADC_JSQR_JSQ3_4 (0x10U << ADC_JSQR_JSQ3_Pos) /*!< 0x00004000 */
+
+#define ADC_JSQR_JSQ4_Pos (15U)
+#define ADC_JSQR_JSQ4_Msk (0x1FU << ADC_JSQR_JSQ4_Pos) /*!< 0x000F8000 */
+#define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!< ADC group injected sequencer rank 4 */
+#define ADC_JSQR_JSQ4_0 (0x01U << ADC_JSQR_JSQ4_Pos) /*!< 0x00008000 */
+#define ADC_JSQR_JSQ4_1 (0x02U << ADC_JSQR_JSQ4_Pos) /*!< 0x00010000 */
+#define ADC_JSQR_JSQ4_2 (0x04U << ADC_JSQR_JSQ4_Pos) /*!< 0x00020000 */
+#define ADC_JSQR_JSQ4_3 (0x08U << ADC_JSQR_JSQ4_Pos) /*!< 0x00040000 */
+#define ADC_JSQR_JSQ4_4 (0x10U << ADC_JSQR_JSQ4_Pos) /*!< 0x00080000 */
+
+#define ADC_JSQR_JL_Pos (20U)
+#define ADC_JSQR_JL_Msk (0x3U << ADC_JSQR_JL_Pos) /*!< 0x00300000 */
+#define ADC_JSQR_JL ADC_JSQR_JL_Msk /*!< ADC group injected sequencer scan length */
+#define ADC_JSQR_JL_0 (0x1U << ADC_JSQR_JL_Pos) /*!< 0x00100000 */
+#define ADC_JSQR_JL_1 (0x2U << ADC_JSQR_JL_Pos) /*!< 0x00200000 */
+
+/******************* Bit definition for ADC_JDR1 register *******************/
+#define ADC_JDR1_JDATA_Pos (0U)
+#define ADC_JDR1_JDATA_Msk (0xFFFFU << ADC_JDR1_JDATA_Pos) /*!< 0x0000FFFF */
+#define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!< ADC group injected sequencer rank 1 conversion data */
+
+/******************* Bit definition for ADC_JDR2 register *******************/
+#define ADC_JDR2_JDATA_Pos (0U)
+#define ADC_JDR2_JDATA_Msk (0xFFFFU << ADC_JDR2_JDATA_Pos) /*!< 0x0000FFFF */
+#define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!< ADC group injected sequencer rank 2 conversion data */
+
+/******************* Bit definition for ADC_JDR3 register *******************/
+#define ADC_JDR3_JDATA_Pos (0U)
+#define ADC_JDR3_JDATA_Msk (0xFFFFU << ADC_JDR3_JDATA_Pos) /*!< 0x0000FFFF */
+#define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!< ADC group injected sequencer rank 3 conversion data */
+
+/******************* Bit definition for ADC_JDR4 register *******************/
+#define ADC_JDR4_JDATA_Pos (0U)
+#define ADC_JDR4_JDATA_Msk (0xFFFFU << ADC_JDR4_JDATA_Pos) /*!< 0x0000FFFF */
+#define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!< ADC group injected sequencer rank 4 conversion data */
+
+/******************** Bit definition for ADC_DR register ********************/
+#define ADC_DR_DATA_Pos (0U)
+#define ADC_DR_DATA_Msk (0xFFFFU << ADC_DR_DATA_Pos) /*!< 0x0000FFFF */
+#define ADC_DR_DATA ADC_DR_DATA_Msk /*!< ADC group regular conversion data */
+#define ADC_DR_ADC2DATA_Pos (16U)
+#define ADC_DR_ADC2DATA_Msk (0xFFFFU << ADC_DR_ADC2DATA_Pos) /*!< 0xFFFF0000 */
+#define ADC_DR_ADC2DATA ADC_DR_ADC2DATA_Msk /*!< ADC group regular conversion data for ADC slave, in multimode */
+/******************************************************************************/
+/* */
+/* Digital to Analog Converter */
+/* */
+/******************************************************************************/
+
+/******************** Bit definition for DAC_CR register ********************/
+#define DAC_CR_EN1_Pos (0U)
+#define DAC_CR_EN1_Msk (0x1U << DAC_CR_EN1_Pos) /*!< 0x00000001 */
+#define DAC_CR_EN1 DAC_CR_EN1_Msk /*!< DAC channel1 enable */
+#define DAC_CR_BOFF1_Pos (1U)
+#define DAC_CR_BOFF1_Msk (0x1U << DAC_CR_BOFF1_Pos) /*!< 0x00000002 */
+#define DAC_CR_BOFF1 DAC_CR_BOFF1_Msk /*!< DAC channel1 output buffer disable */
+#define DAC_CR_TEN1_Pos (2U)
+#define DAC_CR_TEN1_Msk (0x1U << DAC_CR_TEN1_Pos) /*!< 0x00000004 */
+#define DAC_CR_TEN1 DAC_CR_TEN1_Msk /*!< DAC channel1 Trigger enable */
+
+#define DAC_CR_TSEL1_Pos (3U)
+#define DAC_CR_TSEL1_Msk (0x7U << DAC_CR_TSEL1_Pos) /*!< 0x00000038 */
+#define DAC_CR_TSEL1 DAC_CR_TSEL1_Msk /*!< TSEL1[2:0] (DAC channel1 Trigger selection) */
+#define DAC_CR_TSEL1_0 (0x1U << DAC_CR_TSEL1_Pos) /*!< 0x00000008 */
+#define DAC_CR_TSEL1_1 (0x2U << DAC_CR_TSEL1_Pos) /*!< 0x00000010 */
+#define DAC_CR_TSEL1_2 (0x4U << DAC_CR_TSEL1_Pos) /*!< 0x00000020 */
+
+#define DAC_CR_WAVE1_Pos (6U)
+#define DAC_CR_WAVE1_Msk (0x3U << DAC_CR_WAVE1_Pos) /*!< 0x000000C0 */
+#define DAC_CR_WAVE1 DAC_CR_WAVE1_Msk /*!< WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
+#define DAC_CR_WAVE1_0 (0x1U << DAC_CR_WAVE1_Pos) /*!< 0x00000040 */
+#define DAC_CR_WAVE1_1 (0x2U << DAC_CR_WAVE1_Pos) /*!< 0x00000080 */
+
+#define DAC_CR_MAMP1_Pos (8U)
+#define DAC_CR_MAMP1_Msk (0xFU << DAC_CR_MAMP1_Pos) /*!< 0x00000F00 */
+#define DAC_CR_MAMP1 DAC_CR_MAMP1_Msk /*!< MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
+#define DAC_CR_MAMP1_0 (0x1U << DAC_CR_MAMP1_Pos) /*!< 0x00000100 */
+#define DAC_CR_MAMP1_1 (0x2U << DAC_CR_MAMP1_Pos) /*!< 0x00000200 */
+#define DAC_CR_MAMP1_2 (0x4U << DAC_CR_MAMP1_Pos) /*!< 0x00000400 */
+#define DAC_CR_MAMP1_3 (0x8U << DAC_CR_MAMP1_Pos) /*!< 0x00000800 */
+
+#define DAC_CR_DMAEN1_Pos (12U)
+#define DAC_CR_DMAEN1_Msk (0x1U << DAC_CR_DMAEN1_Pos) /*!< 0x00001000 */
+#define DAC_CR_DMAEN1 DAC_CR_DMAEN1_Msk /*!< DAC channel1 DMA enable */
+#define DAC_CR_EN2_Pos (16U)
+#define DAC_CR_EN2_Msk (0x1U << DAC_CR_EN2_Pos) /*!< 0x00010000 */
+#define DAC_CR_EN2 DAC_CR_EN2_Msk /*!< DAC channel2 enable */
+#define DAC_CR_BOFF2_Pos (17U)
+#define DAC_CR_BOFF2_Msk (0x1U << DAC_CR_BOFF2_Pos) /*!< 0x00020000 */
+#define DAC_CR_BOFF2 DAC_CR_BOFF2_Msk /*!< DAC channel2 output buffer disable */
+#define DAC_CR_TEN2_Pos (18U)
+#define DAC_CR_TEN2_Msk (0x1U << DAC_CR_TEN2_Pos) /*!< 0x00040000 */
+#define DAC_CR_TEN2 DAC_CR_TEN2_Msk /*!< DAC channel2 Trigger enable */
+
+#define DAC_CR_TSEL2_Pos (19U)
+#define DAC_CR_TSEL2_Msk (0x7U << DAC_CR_TSEL2_Pos) /*!< 0x00380000 */
+#define DAC_CR_TSEL2 DAC_CR_TSEL2_Msk /*!< TSEL2[2:0] (DAC channel2 Trigger selection) */
+#define DAC_CR_TSEL2_0 (0x1U << DAC_CR_TSEL2_Pos) /*!< 0x00080000 */
+#define DAC_CR_TSEL2_1 (0x2U << DAC_CR_TSEL2_Pos) /*!< 0x00100000 */
+#define DAC_CR_TSEL2_2 (0x4U << DAC_CR_TSEL2_Pos) /*!< 0x00200000 */
+
+#define DAC_CR_WAVE2_Pos (22U)
+#define DAC_CR_WAVE2_Msk (0x3U << DAC_CR_WAVE2_Pos) /*!< 0x00C00000 */
+#define DAC_CR_WAVE2 DAC_CR_WAVE2_Msk /*!< WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
+#define DAC_CR_WAVE2_0 (0x1U << DAC_CR_WAVE2_Pos) /*!< 0x00400000 */
+#define DAC_CR_WAVE2_1 (0x2U << DAC_CR_WAVE2_Pos) /*!< 0x00800000 */
+
+#define DAC_CR_MAMP2_Pos (24U)
+#define DAC_CR_MAMP2_Msk (0xFU << DAC_CR_MAMP2_Pos) /*!< 0x0F000000 */
+#define DAC_CR_MAMP2 DAC_CR_MAMP2_Msk /*!< MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
+#define DAC_CR_MAMP2_0 (0x1U << DAC_CR_MAMP2_Pos) /*!< 0x01000000 */
+#define DAC_CR_MAMP2_1 (0x2U << DAC_CR_MAMP2_Pos) /*!< 0x02000000 */
+#define DAC_CR_MAMP2_2 (0x4U << DAC_CR_MAMP2_Pos) /*!< 0x04000000 */
+#define DAC_CR_MAMP2_3 (0x8U << DAC_CR_MAMP2_Pos) /*!< 0x08000000 */
+
+#define DAC_CR_DMAEN2_Pos (28U)
+#define DAC_CR_DMAEN2_Msk (0x1U << DAC_CR_DMAEN2_Pos) /*!< 0x10000000 */
+#define DAC_CR_DMAEN2 DAC_CR_DMAEN2_Msk /*!< DAC channel2 DMA enabled */
+
+
+/***************** Bit definition for DAC_SWTRIGR register ******************/
+#define DAC_SWTRIGR_SWTRIG1_Pos (0U)
+#define DAC_SWTRIGR_SWTRIG1_Msk (0x1U << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */
+#define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /*!< DAC channel1 software trigger */
+#define DAC_SWTRIGR_SWTRIG2_Pos (1U)
+#define DAC_SWTRIGR_SWTRIG2_Msk (0x1U << DAC_SWTRIGR_SWTRIG2_Pos) /*!< 0x00000002 */
+#define DAC_SWTRIGR_SWTRIG2 DAC_SWTRIGR_SWTRIG2_Msk /*!< DAC channel2 software trigger */
+
+/***************** Bit definition for DAC_DHR12R1 register ******************/
+#define DAC_DHR12R1_DACC1DHR_Pos (0U)
+#define DAC_DHR12R1_DACC1DHR_Msk (0xFFFU << DAC_DHR12R1_DACC1DHR_Pos) /*!< 0x00000FFF */
+#define DAC_DHR12R1_DACC1DHR DAC_DHR12R1_DACC1DHR_Msk /*!< DAC channel1 12-bit Right aligned data */
+
+/***************** Bit definition for DAC_DHR12L1 register ******************/
+#define DAC_DHR12L1_DACC1DHR_Pos (4U)
+#define DAC_DHR12L1_DACC1DHR_Msk (0xFFFU << DAC_DHR12L1_DACC1DHR_Pos) /*!< 0x0000FFF0 */
+#define DAC_DHR12L1_DACC1DHR DAC_DHR12L1_DACC1DHR_Msk /*!< DAC channel1 12-bit Left aligned data */
+
+/****************** Bit definition for DAC_DHR8R1 register ******************/
+#define DAC_DHR8R1_DACC1DHR_Pos (0U)
+#define DAC_DHR8R1_DACC1DHR_Msk (0xFFU << DAC_DHR8R1_DACC1DHR_Pos) /*!< 0x000000FF */
+#define DAC_DHR8R1_DACC1DHR DAC_DHR8R1_DACC1DHR_Msk /*!< DAC channel1 8-bit Right aligned data */
+
+/***************** Bit definition for DAC_DHR12R2 register ******************/
+#define DAC_DHR12R2_DACC2DHR_Pos (0U)
+#define DAC_DHR12R2_DACC2DHR_Msk (0xFFFU << DAC_DHR12R2_DACC2DHR_Pos) /*!< 0x00000FFF */
+#define DAC_DHR12R2_DACC2DHR DAC_DHR12R2_DACC2DHR_Msk /*!< DAC channel2 12-bit Right aligned data */
+
+/***************** Bit definition for DAC_DHR12L2 register ******************/
+#define DAC_DHR12L2_DACC2DHR_Pos (4U)
+#define DAC_DHR12L2_DACC2DHR_Msk (0xFFFU << DAC_DHR12L2_DACC2DHR_Pos) /*!< 0x0000FFF0 */
+#define DAC_DHR12L2_DACC2DHR DAC_DHR12L2_DACC2DHR_Msk /*!< DAC channel2 12-bit Left aligned data */
+
+/****************** Bit definition for DAC_DHR8R2 register ******************/
+#define DAC_DHR8R2_DACC2DHR_Pos (0U)
+#define DAC_DHR8R2_DACC2DHR_Msk (0xFFU << DAC_DHR8R2_DACC2DHR_Pos) /*!< 0x000000FF */
+#define DAC_DHR8R2_DACC2DHR DAC_DHR8R2_DACC2DHR_Msk /*!< DAC channel2 8-bit Right aligned data */
+
+/***************** Bit definition for DAC_DHR12RD register ******************/
+#define DAC_DHR12RD_DACC1DHR_Pos (0U)
+#define DAC_DHR12RD_DACC1DHR_Msk (0xFFFU << DAC_DHR12RD_DACC1DHR_Pos) /*!< 0x00000FFF */
+#define DAC_DHR12RD_DACC1DHR DAC_DHR12RD_DACC1DHR_Msk /*!< DAC channel1 12-bit Right aligned data */
+#define DAC_DHR12RD_DACC2DHR_Pos (16U)
+#define DAC_DHR12RD_DACC2DHR_Msk (0xFFFU << DAC_DHR12RD_DACC2DHR_Pos) /*!< 0x0FFF0000 */
+#define DAC_DHR12RD_DACC2DHR DAC_DHR12RD_DACC2DHR_Msk /*!< DAC channel2 12-bit Right aligned data */
+
+/***************** Bit definition for DAC_DHR12LD register ******************/
+#define DAC_DHR12LD_DACC1DHR_Pos (4U)
+#define DAC_DHR12LD_DACC1DHR_Msk (0xFFFU << DAC_DHR12LD_DACC1DHR_Pos) /*!< 0x0000FFF0 */
+#define DAC_DHR12LD_DACC1DHR DAC_DHR12LD_DACC1DHR_Msk /*!< DAC channel1 12-bit Left aligned data */
+#define DAC_DHR12LD_DACC2DHR_Pos (20U)
+#define DAC_DHR12LD_DACC2DHR_Msk (0xFFFU << DAC_DHR12LD_DACC2DHR_Pos) /*!< 0xFFF00000 */
+#define DAC_DHR12LD_DACC2DHR DAC_DHR12LD_DACC2DHR_Msk /*!< DAC channel2 12-bit Left aligned data */
+
+/****************** Bit definition for DAC_DHR8RD register ******************/
+#define DAC_DHR8RD_DACC1DHR_Pos (0U)
+#define DAC_DHR8RD_DACC1DHR_Msk (0xFFU << DAC_DHR8RD_DACC1DHR_Pos) /*!< 0x000000FF */
+#define DAC_DHR8RD_DACC1DHR DAC_DHR8RD_DACC1DHR_Msk /*!< DAC channel1 8-bit Right aligned data */
+#define DAC_DHR8RD_DACC2DHR_Pos (8U)
+#define DAC_DHR8RD_DACC2DHR_Msk (0xFFU << DAC_DHR8RD_DACC2DHR_Pos) /*!< 0x0000FF00 */
+#define DAC_DHR8RD_DACC2DHR DAC_DHR8RD_DACC2DHR_Msk /*!< DAC channel2 8-bit Right aligned data */
+
+/******************* Bit definition for DAC_DOR1 register *******************/
+#define DAC_DOR1_DACC1DOR_Pos (0U)
+#define DAC_DOR1_DACC1DOR_Msk (0xFFFU << DAC_DOR1_DACC1DOR_Pos) /*!< 0x00000FFF */
+#define DAC_DOR1_DACC1DOR DAC_DOR1_DACC1DOR_Msk /*!< DAC channel1 data output */
+
+/******************* Bit definition for DAC_DOR2 register *******************/
+#define DAC_DOR2_DACC2DOR_Pos (0U)
+#define DAC_DOR2_DACC2DOR_Msk (0xFFFU << DAC_DOR2_DACC2DOR_Pos) /*!< 0x00000FFF */
+#define DAC_DOR2_DACC2DOR DAC_DOR2_DACC2DOR_Msk /*!< DAC channel2 data output */
+
+
+
+/*****************************************************************************/
+/* */
+/* Timers (TIM) */
+/* */
+/*****************************************************************************/
+/******************* Bit definition for TIM_CR1 register *******************/
+#define TIM_CR1_CEN_Pos (0U)
+#define TIM_CR1_CEN_Msk (0x1U << TIM_CR1_CEN_Pos) /*!< 0x00000001 */
+#define TIM_CR1_CEN TIM_CR1_CEN_Msk /*!<Counter enable */
+#define TIM_CR1_UDIS_Pos (1U)
+#define TIM_CR1_UDIS_Msk (0x1U << TIM_CR1_UDIS_Pos) /*!< 0x00000002 */
+#define TIM_CR1_UDIS TIM_CR1_UDIS_Msk /*!<Update disable */
+#define TIM_CR1_URS_Pos (2U)
+#define TIM_CR1_URS_Msk (0x1U << TIM_CR1_URS_Pos) /*!< 0x00000004 */
+#define TIM_CR1_URS TIM_CR1_URS_Msk /*!<Update request source */
+#define TIM_CR1_OPM_Pos (3U)
+#define TIM_CR1_OPM_Msk (0x1U << TIM_CR1_OPM_Pos) /*!< 0x00000008 */
+#define TIM_CR1_OPM TIM_CR1_OPM_Msk /*!<One pulse mode */
+#define TIM_CR1_DIR_Pos (4U)
+#define TIM_CR1_DIR_Msk (0x1U << TIM_CR1_DIR_Pos) /*!< 0x00000010 */
+#define TIM_CR1_DIR TIM_CR1_DIR_Msk /*!<Direction */
+
+#define TIM_CR1_CMS_Pos (5U)
+#define TIM_CR1_CMS_Msk (0x3U << TIM_CR1_CMS_Pos) /*!< 0x00000060 */
+#define TIM_CR1_CMS TIM_CR1_CMS_Msk /*!<CMS[1:0] bits (Center-aligned mode selection) */
+#define TIM_CR1_CMS_0 (0x1U << TIM_CR1_CMS_Pos) /*!< 0x00000020 */
+#define TIM_CR1_CMS_1 (0x2U << TIM_CR1_CMS_Pos) /*!< 0x00000040 */
+
+#define TIM_CR1_ARPE_Pos (7U)
+#define TIM_CR1_ARPE_Msk (0x1U << TIM_CR1_ARPE_Pos) /*!< 0x00000080 */
+#define TIM_CR1_ARPE TIM_CR1_ARPE_Msk /*!<Auto-reload preload enable */
+
+#define TIM_CR1_CKD_Pos (8U)
+#define TIM_CR1_CKD_Msk (0x3U << TIM_CR1_CKD_Pos) /*!< 0x00000300 */
+#define TIM_CR1_CKD TIM_CR1_CKD_Msk /*!<CKD[1:0] bits (clock division) */
+#define TIM_CR1_CKD_0 (0x1U << TIM_CR1_CKD_Pos) /*!< 0x00000100 */
+#define TIM_CR1_CKD_1 (0x2U << TIM_CR1_CKD_Pos) /*!< 0x00000200 */
+
+/******************* Bit definition for TIM_CR2 register *******************/
+#define TIM_CR2_CCPC_Pos (0U)
+#define TIM_CR2_CCPC_Msk (0x1U << TIM_CR2_CCPC_Pos) /*!< 0x00000001 */
+#define TIM_CR2_CCPC TIM_CR2_CCPC_Msk /*!<Capture/Compare Preloaded Control */
+#define TIM_CR2_CCUS_Pos (2U)
+#define TIM_CR2_CCUS_Msk (0x1U << TIM_CR2_CCUS_Pos) /*!< 0x00000004 */
+#define TIM_CR2_CCUS TIM_CR2_CCUS_Msk /*!<Capture/Compare Control Update Selection */
+#define TIM_CR2_CCDS_Pos (3U)
+#define TIM_CR2_CCDS_Msk (0x1U << TIM_CR2_CCDS_Pos) /*!< 0x00000008 */
+#define TIM_CR2_CCDS TIM_CR2_CCDS_Msk /*!<Capture/Compare DMA Selection */
+
+#define TIM_CR2_MMS_Pos (4U)
+#define TIM_CR2_MMS_Msk (0x7U << TIM_CR2_MMS_Pos) /*!< 0x00000070 */
+#define TIM_CR2_MMS TIM_CR2_MMS_Msk /*!<MMS[2:0] bits (Master Mode Selection) */
+#define TIM_CR2_MMS_0 (0x1U << TIM_CR2_MMS_Pos) /*!< 0x00000010 */
+#define TIM_CR2_MMS_1 (0x2U << TIM_CR2_MMS_Pos) /*!< 0x00000020 */
+#define TIM_CR2_MMS_2 (0x4U << TIM_CR2_MMS_Pos) /*!< 0x00000040 */
+
+#define TIM_CR2_TI1S_Pos (7U)
+#define TIM_CR2_TI1S_Msk (0x1U << TIM_CR2_TI1S_Pos) /*!< 0x00000080 */
+#define TIM_CR2_TI1S TIM_CR2_TI1S_Msk /*!<TI1 Selection */
+#define TIM_CR2_OIS1_Pos (8U)
+#define TIM_CR2_OIS1_Msk (0x1U << TIM_CR2_OIS1_Pos) /*!< 0x00000100 */
+#define TIM_CR2_OIS1 TIM_CR2_OIS1_Msk /*!<Output Idle state 1 (OC1 output) */
+#define TIM_CR2_OIS1N_Pos (9U)
+#define TIM_CR2_OIS1N_Msk (0x1U << TIM_CR2_OIS1N_Pos) /*!< 0x00000200 */
+#define TIM_CR2_OIS1N TIM_CR2_OIS1N_Msk /*!<Output Idle state 1 (OC1N output) */
+#define TIM_CR2_OIS2_Pos (10U)
+#define TIM_CR2_OIS2_Msk (0x1U << TIM_CR2_OIS2_Pos) /*!< 0x00000400 */
+#define TIM_CR2_OIS2 TIM_CR2_OIS2_Msk /*!<Output Idle state 2 (OC2 output) */
+#define TIM_CR2_OIS2N_Pos (11U)
+#define TIM_CR2_OIS2N_Msk (0x1U << TIM_CR2_OIS2N_Pos) /*!< 0x00000800 */
+#define TIM_CR2_OIS2N TIM_CR2_OIS2N_Msk /*!<Output Idle state 2 (OC2N output) */
+#define TIM_CR2_OIS3_Pos (12U)
+#define TIM_CR2_OIS3_Msk (0x1U << TIM_CR2_OIS3_Pos) /*!< 0x00001000 */
+#define TIM_CR2_OIS3 TIM_CR2_OIS3_Msk /*!<Output Idle state 3 (OC3 output) */
+#define TIM_CR2_OIS3N_Pos (13U)
+#define TIM_CR2_OIS3N_Msk (0x1U << TIM_CR2_OIS3N_Pos) /*!< 0x00002000 */
+#define TIM_CR2_OIS3N TIM_CR2_OIS3N_Msk /*!<Output Idle state 3 (OC3N output) */
+#define TIM_CR2_OIS4_Pos (14U)
+#define TIM_CR2_OIS4_Msk (0x1U << TIM_CR2_OIS4_Pos) /*!< 0x00004000 */
+#define TIM_CR2_OIS4 TIM_CR2_OIS4_Msk /*!<Output Idle state 4 (OC4 output) */
+
+/******************* Bit definition for TIM_SMCR register ******************/
+#define TIM_SMCR_SMS_Pos (0U)
+#define TIM_SMCR_SMS_Msk (0x7U << TIM_SMCR_SMS_Pos) /*!< 0x00000007 */
+#define TIM_SMCR_SMS TIM_SMCR_SMS_Msk /*!<SMS[2:0] bits (Slave mode selection) */
+#define TIM_SMCR_SMS_0 (0x1U << TIM_SMCR_SMS_Pos) /*!< 0x00000001 */
+#define TIM_SMCR_SMS_1 (0x2U << TIM_SMCR_SMS_Pos) /*!< 0x00000002 */
+#define TIM_SMCR_SMS_2 (0x4U << TIM_SMCR_SMS_Pos) /*!< 0x00000004 */
+
+#define TIM_SMCR_OCCS_Pos (3U)
+#define TIM_SMCR_OCCS_Msk (0x1U << TIM_SMCR_OCCS_Pos) /*!< 0x00000008 */
+#define TIM_SMCR_OCCS TIM_SMCR_OCCS_Msk /*!< OCREF clear selection */
+
+#define TIM_SMCR_TS_Pos (4U)
+#define TIM_SMCR_TS_Msk (0x7U << TIM_SMCR_TS_Pos) /*!< 0x00000070 */
+#define TIM_SMCR_TS TIM_SMCR_TS_Msk /*!<TS[2:0] bits (Trigger selection) */
+#define TIM_SMCR_TS_0 (0x1U << TIM_SMCR_TS_Pos) /*!< 0x00000010 */
+#define TIM_SMCR_TS_1 (0x2U << TIM_SMCR_TS_Pos) /*!< 0x00000020 */
+#define TIM_SMCR_TS_2 (0x4U << TIM_SMCR_TS_Pos) /*!< 0x00000040 */
+
+#define TIM_SMCR_MSM_Pos (7U)
+#define TIM_SMCR_MSM_Msk (0x1U << TIM_SMCR_MSM_Pos) /*!< 0x00000080 */
+#define TIM_SMCR_MSM TIM_SMCR_MSM_Msk /*!<Master/slave mode */
+
+#define TIM_SMCR_ETF_Pos (8U)
+#define TIM_SMCR_ETF_Msk (0xFU << TIM_SMCR_ETF_Pos) /*!< 0x00000F00 */
+#define TIM_SMCR_ETF TIM_SMCR_ETF_Msk /*!<ETF[3:0] bits (External trigger filter) */
+#define TIM_SMCR_ETF_0 (0x1U << TIM_SMCR_ETF_Pos) /*!< 0x00000100 */
+#define TIM_SMCR_ETF_1 (0x2U << TIM_SMCR_ETF_Pos) /*!< 0x00000200 */
+#define TIM_SMCR_ETF_2 (0x4U << TIM_SMCR_ETF_Pos) /*!< 0x00000400 */
+#define TIM_SMCR_ETF_3 (0x8U << TIM_SMCR_ETF_Pos) /*!< 0x00000800 */
+
+#define TIM_SMCR_ETPS_Pos (12U)
+#define TIM_SMCR_ETPS_Msk (0x3U << TIM_SMCR_ETPS_Pos) /*!< 0x00003000 */
+#define TIM_SMCR_ETPS TIM_SMCR_ETPS_Msk /*!<ETPS[1:0] bits (External trigger prescaler) */
+#define TIM_SMCR_ETPS_0 (0x1U << TIM_SMCR_ETPS_Pos) /*!< 0x00001000 */
+#define TIM_SMCR_ETPS_1 (0x2U << TIM_SMCR_ETPS_Pos) /*!< 0x00002000 */
+
+#define TIM_SMCR_ECE_Pos (14U)
+#define TIM_SMCR_ECE_Msk (0x1U << TIM_SMCR_ECE_Pos) /*!< 0x00004000 */
+#define TIM_SMCR_ECE TIM_SMCR_ECE_Msk /*!<External clock enable */
+#define TIM_SMCR_ETP_Pos (15U)
+#define TIM_SMCR_ETP_Msk (0x1U << TIM_SMCR_ETP_Pos) /*!< 0x00008000 */
+#define TIM_SMCR_ETP TIM_SMCR_ETP_Msk /*!<External trigger polarity */
+
+/******************* Bit definition for TIM_DIER register ******************/
+#define TIM_DIER_UIE_Pos (0U)
+#define TIM_DIER_UIE_Msk (0x1U << TIM_DIER_UIE_Pos) /*!< 0x00000001 */
+#define TIM_DIER_UIE TIM_DIER_UIE_Msk /*!<Update interrupt enable */
+#define TIM_DIER_CC1IE_Pos (1U)
+#define TIM_DIER_CC1IE_Msk (0x1U << TIM_DIER_CC1IE_Pos) /*!< 0x00000002 */
+#define TIM_DIER_CC1IE TIM_DIER_CC1IE_Msk /*!<Capture/Compare 1 interrupt enable */
+#define TIM_DIER_CC2IE_Pos (2U)
+#define TIM_DIER_CC2IE_Msk (0x1U << TIM_DIER_CC2IE_Pos) /*!< 0x00000004 */
+#define TIM_DIER_CC2IE TIM_DIER_CC2IE_Msk /*!<Capture/Compare 2 interrupt enable */
+#define TIM_DIER_CC3IE_Pos (3U)
+#define TIM_DIER_CC3IE_Msk (0x1U << TIM_DIER_CC3IE_Pos) /*!< 0x00000008 */
+#define TIM_DIER_CC3IE TIM_DIER_CC3IE_Msk /*!<Capture/Compare 3 interrupt enable */
+#define TIM_DIER_CC4IE_Pos (4U)
+#define TIM_DIER_CC4IE_Msk (0x1U << TIM_DIER_CC4IE_Pos) /*!< 0x00000010 */
+#define TIM_DIER_CC4IE TIM_DIER_CC4IE_Msk /*!<Capture/Compare 4 interrupt enable */
+#define TIM_DIER_COMIE_Pos (5U)
+#define TIM_DIER_COMIE_Msk (0x1U << TIM_DIER_COMIE_Pos) /*!< 0x00000020 */
+#define TIM_DIER_COMIE TIM_DIER_COMIE_Msk /*!<COM interrupt enable */
+#define TIM_DIER_TIE_Pos (6U)
+#define TIM_DIER_TIE_Msk (0x1U << TIM_DIER_TIE_Pos) /*!< 0x00000040 */
+#define TIM_DIER_TIE TIM_DIER_TIE_Msk /*!<Trigger interrupt enable */
+#define TIM_DIER_BIE_Pos (7U)
+#define TIM_DIER_BIE_Msk (0x1U << TIM_DIER_BIE_Pos) /*!< 0x00000080 */
+#define TIM_DIER_BIE TIM_DIER_BIE_Msk /*!<Break interrupt enable */
+#define TIM_DIER_UDE_Pos (8U)
+#define TIM_DIER_UDE_Msk (0x1U << TIM_DIER_UDE_Pos) /*!< 0x00000100 */
+#define TIM_DIER_UDE TIM_DIER_UDE_Msk /*!<Update DMA request enable */
+#define TIM_DIER_CC1DE_Pos (9U)
+#define TIM_DIER_CC1DE_Msk (0x1U << TIM_DIER_CC1DE_Pos) /*!< 0x00000200 */
+#define TIM_DIER_CC1DE TIM_DIER_CC1DE_Msk /*!<Capture/Compare 1 DMA request enable */
+#define TIM_DIER_CC2DE_Pos (10U)
+#define TIM_DIER_CC2DE_Msk (0x1U << TIM_DIER_CC2DE_Pos) /*!< 0x00000400 */
+#define TIM_DIER_CC2DE TIM_DIER_CC2DE_Msk /*!<Capture/Compare 2 DMA request enable */
+#define TIM_DIER_CC3DE_Pos (11U)
+#define TIM_DIER_CC3DE_Msk (0x1U << TIM_DIER_CC3DE_Pos) /*!< 0x00000800 */
+#define TIM_DIER_CC3DE TIM_DIER_CC3DE_Msk /*!<Capture/Compare 3 DMA request enable */
+#define TIM_DIER_CC4DE_Pos (12U)
+#define TIM_DIER_CC4DE_Msk (0x1U << TIM_DIER_CC4DE_Pos) /*!< 0x00001000 */
+#define TIM_DIER_CC4DE TIM_DIER_CC4DE_Msk /*!<Capture/Compare 4 DMA request enable */
+#define TIM_DIER_COMDE_Pos (13U)
+#define TIM_DIER_COMDE_Msk (0x1U << TIM_DIER_COMDE_Pos) /*!< 0x00002000 */
+#define TIM_DIER_COMDE TIM_DIER_COMDE_Msk /*!<COM DMA request enable */
+#define TIM_DIER_TDE_Pos (14U)
+#define TIM_DIER_TDE_Msk (0x1U << TIM_DIER_TDE_Pos) /*!< 0x00004000 */
+#define TIM_DIER_TDE TIM_DIER_TDE_Msk /*!<Trigger DMA request enable */
+
+/******************** Bit definition for TIM_SR register *******************/
+#define TIM_SR_UIF_Pos (0U)
+#define TIM_SR_UIF_Msk (0x1U << TIM_SR_UIF_Pos) /*!< 0x00000001 */
+#define TIM_SR_UIF TIM_SR_UIF_Msk /*!<Update interrupt Flag */
+#define TIM_SR_CC1IF_Pos (1U)
+#define TIM_SR_CC1IF_Msk (0x1U << TIM_SR_CC1IF_Pos) /*!< 0x00000002 */
+#define TIM_SR_CC1IF TIM_SR_CC1IF_Msk /*!<Capture/Compare 1 interrupt Flag */
+#define TIM_SR_CC2IF_Pos (2U)
+#define TIM_SR_CC2IF_Msk (0x1U << TIM_SR_CC2IF_Pos) /*!< 0x00000004 */
+#define TIM_SR_CC2IF TIM_SR_CC2IF_Msk /*!<Capture/Compare 2 interrupt Flag */
+#define TIM_SR_CC3IF_Pos (3U)
+#define TIM_SR_CC3IF_Msk (0x1U << TIM_SR_CC3IF_Pos) /*!< 0x00000008 */
+#define TIM_SR_CC3IF TIM_SR_CC3IF_Msk /*!<Capture/Compare 3 interrupt Flag */
+#define TIM_SR_CC4IF_Pos (4U)
+#define TIM_SR_CC4IF_Msk (0x1U << TIM_SR_CC4IF_Pos) /*!< 0x00000010 */
+#define TIM_SR_CC4IF TIM_SR_CC4IF_Msk /*!<Capture/Compare 4 interrupt Flag */
+#define TIM_SR_COMIF_Pos (5U)
+#define TIM_SR_COMIF_Msk (0x1U << TIM_SR_COMIF_Pos) /*!< 0x00000020 */
+#define TIM_SR_COMIF TIM_SR_COMIF_Msk /*!<COM interrupt Flag */
+#define TIM_SR_TIF_Pos (6U)
+#define TIM_SR_TIF_Msk (0x1U << TIM_SR_TIF_Pos) /*!< 0x00000040 */
+#define TIM_SR_TIF TIM_SR_TIF_Msk /*!<Trigger interrupt Flag */
+#define TIM_SR_BIF_Pos (7U)
+#define TIM_SR_BIF_Msk (0x1U << TIM_SR_BIF_Pos) /*!< 0x00000080 */
+#define TIM_SR_BIF TIM_SR_BIF_Msk /*!<Break interrupt Flag */
+#define TIM_SR_CC1OF_Pos (9U)
+#define TIM_SR_CC1OF_Msk (0x1U << TIM_SR_CC1OF_Pos) /*!< 0x00000200 */
+#define TIM_SR_CC1OF TIM_SR_CC1OF_Msk /*!<Capture/Compare 1 Overcapture Flag */
+#define TIM_SR_CC2OF_Pos (10U)
+#define TIM_SR_CC2OF_Msk (0x1U << TIM_SR_CC2OF_Pos) /*!< 0x00000400 */
+#define TIM_SR_CC2OF TIM_SR_CC2OF_Msk /*!<Capture/Compare 2 Overcapture Flag */
+#define TIM_SR_CC3OF_Pos (11U)
+#define TIM_SR_CC3OF_Msk (0x1U << TIM_SR_CC3OF_Pos) /*!< 0x00000800 */
+#define TIM_SR_CC3OF TIM_SR_CC3OF_Msk /*!<Capture/Compare 3 Overcapture Flag */
+#define TIM_SR_CC4OF_Pos (12U)
+#define TIM_SR_CC4OF_Msk (0x1U << TIM_SR_CC4OF_Pos) /*!< 0x00001000 */
+#define TIM_SR_CC4OF TIM_SR_CC4OF_Msk /*!<Capture/Compare 4 Overcapture Flag */
+
+/******************* Bit definition for TIM_EGR register *******************/
+#define TIM_EGR_UG_Pos (0U)
+#define TIM_EGR_UG_Msk (0x1U << TIM_EGR_UG_Pos) /*!< 0x00000001 */
+#define TIM_EGR_UG TIM_EGR_UG_Msk /*!<Update Generation */
+#define TIM_EGR_CC1G_Pos (1U)
+#define TIM_EGR_CC1G_Msk (0x1U << TIM_EGR_CC1G_Pos) /*!< 0x00000002 */
+#define TIM_EGR_CC1G TIM_EGR_CC1G_Msk /*!<Capture/Compare 1 Generation */
+#define TIM_EGR_CC2G_Pos (2U)
+#define TIM_EGR_CC2G_Msk (0x1U << TIM_EGR_CC2G_Pos) /*!< 0x00000004 */
+#define TIM_EGR_CC2G TIM_EGR_CC2G_Msk /*!<Capture/Compare 2 Generation */
+#define TIM_EGR_CC3G_Pos (3U)
+#define TIM_EGR_CC3G_Msk (0x1U << TIM_EGR_CC3G_Pos) /*!< 0x00000008 */
+#define TIM_EGR_CC3G TIM_EGR_CC3G_Msk /*!<Capture/Compare 3 Generation */
+#define TIM_EGR_CC4G_Pos (4U)
+#define TIM_EGR_CC4G_Msk (0x1U << TIM_EGR_CC4G_Pos) /*!< 0x00000010 */
+#define TIM_EGR_CC4G TIM_EGR_CC4G_Msk /*!<Capture/Compare 4 Generation */
+#define TIM_EGR_COMG_Pos (5U)
+#define TIM_EGR_COMG_Msk (0x1U << TIM_EGR_COMG_Pos) /*!< 0x00000020 */
+#define TIM_EGR_COMG TIM_EGR_COMG_Msk /*!<Capture/Compare Control Update Generation */
+#define TIM_EGR_TG_Pos (6U)
+#define TIM_EGR_TG_Msk (0x1U << TIM_EGR_TG_Pos) /*!< 0x00000040 */
+#define TIM_EGR_TG TIM_EGR_TG_Msk /*!<Trigger Generation */
+#define TIM_EGR_BG_Pos (7U)
+#define TIM_EGR_BG_Msk (0x1U << TIM_EGR_BG_Pos) /*!< 0x00000080 */
+#define TIM_EGR_BG TIM_EGR_BG_Msk /*!<Break Generation */
+
+/****************** Bit definition for TIM_CCMR1 register ******************/
+#define TIM_CCMR1_CC1S_Pos (0U)
+#define TIM_CCMR1_CC1S_Msk (0x3U << TIM_CCMR1_CC1S_Pos) /*!< 0x00000003 */
+#define TIM_CCMR1_CC1S TIM_CCMR1_CC1S_Msk /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
+#define TIM_CCMR1_CC1S_0 (0x1U << TIM_CCMR1_CC1S_Pos) /*!< 0x00000001 */
+#define TIM_CCMR1_CC1S_1 (0x2U << TIM_CCMR1_CC1S_Pos) /*!< 0x00000002 */
+
+#define TIM_CCMR1_OC1FE_Pos (2U)
+#define TIM_CCMR1_OC1FE_Msk (0x1U << TIM_CCMR1_OC1FE_Pos) /*!< 0x00000004 */
+#define TIM_CCMR1_OC1FE TIM_CCMR1_OC1FE_Msk /*!<Output Compare 1 Fast enable */
+#define TIM_CCMR1_OC1PE_Pos (3U)
+#define TIM_CCMR1_OC1PE_Msk (0x1U << TIM_CCMR1_OC1PE_Pos) /*!< 0x00000008 */
+#define TIM_CCMR1_OC1PE TIM_CCMR1_OC1PE_Msk /*!<Output Compare 1 Preload enable */
+
+#define TIM_CCMR1_OC1M_Pos (4U)
+#define TIM_CCMR1_OC1M_Msk (0x7U << TIM_CCMR1_OC1M_Pos) /*!< 0x00000070 */
+#define TIM_CCMR1_OC1M TIM_CCMR1_OC1M_Msk /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
+#define TIM_CCMR1_OC1M_0 (0x1U << TIM_CCMR1_OC1M_Pos) /*!< 0x00000010 */
+#define TIM_CCMR1_OC1M_1 (0x2U << TIM_CCMR1_OC1M_Pos) /*!< 0x00000020 */
+#define TIM_CCMR1_OC1M_2 (0x4U << TIM_CCMR1_OC1M_Pos) /*!< 0x00000040 */
+
+#define TIM_CCMR1_OC1CE_Pos (7U)
+#define TIM_CCMR1_OC1CE_Msk (0x1U << TIM_CCMR1_OC1CE_Pos) /*!< 0x00000080 */
+#define TIM_CCMR1_OC1CE TIM_CCMR1_OC1CE_Msk /*!<Output Compare 1Clear Enable */
+
+#define TIM_CCMR1_CC2S_Pos (8U)
+#define TIM_CCMR1_CC2S_Msk (0x3U << TIM_CCMR1_CC2S_Pos) /*!< 0x00000300 */
+#define TIM_CCMR1_CC2S TIM_CCMR1_CC2S_Msk /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
+#define TIM_CCMR1_CC2S_0 (0x1U << TIM_CCMR1_CC2S_Pos) /*!< 0x00000100 */
+#define TIM_CCMR1_CC2S_1 (0x2U << TIM_CCMR1_CC2S_Pos) /*!< 0x00000200 */
+
+#define TIM_CCMR1_OC2FE_Pos (10U)
+#define TIM_CCMR1_OC2FE_Msk (0x1U << TIM_CCMR1_OC2FE_Pos) /*!< 0x00000400 */
+#define TIM_CCMR1_OC2FE TIM_CCMR1_OC2FE_Msk /*!<Output Compare 2 Fast enable */
+#define TIM_CCMR1_OC2PE_Pos (11U)
+#define TIM_CCMR1_OC2PE_Msk (0x1U << TIM_CCMR1_OC2PE_Pos) /*!< 0x00000800 */
+#define TIM_CCMR1_OC2PE TIM_CCMR1_OC2PE_Msk /*!<Output Compare 2 Preload enable */
+
+#define TIM_CCMR1_OC2M_Pos (12U)
+#define TIM_CCMR1_OC2M_Msk (0x7U << TIM_CCMR1_OC2M_Pos) /*!< 0x00007000 */
+#define TIM_CCMR1_OC2M TIM_CCMR1_OC2M_Msk /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
+#define TIM_CCMR1_OC2M_0 (0x1U << TIM_CCMR1_OC2M_Pos) /*!< 0x00001000 */
+#define TIM_CCMR1_OC2M_1 (0x2U << TIM_CCMR1_OC2M_Pos) /*!< 0x00002000 */
+#define TIM_CCMR1_OC2M_2 (0x4U << TIM_CCMR1_OC2M_Pos) /*!< 0x00004000 */
+
+#define TIM_CCMR1_OC2CE_Pos (15U)
+#define TIM_CCMR1_OC2CE_Msk (0x1U << TIM_CCMR1_OC2CE_Pos) /*!< 0x00008000 */
+#define TIM_CCMR1_OC2CE TIM_CCMR1_OC2CE_Msk /*!<Output Compare 2 Clear Enable */
+
+/*---------------------------------------------------------------------------*/
+
+#define TIM_CCMR1_IC1PSC_Pos (2U)
+#define TIM_CCMR1_IC1PSC_Msk (0x3U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x0000000C */
+#define TIM_CCMR1_IC1PSC TIM_CCMR1_IC1PSC_Msk /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
+#define TIM_CCMR1_IC1PSC_0 (0x1U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x00000004 */
+#define TIM_CCMR1_IC1PSC_1 (0x2U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x00000008 */
+
+#define TIM_CCMR1_IC1F_Pos (4U)
+#define TIM_CCMR1_IC1F_Msk (0xFU << TIM_CCMR1_IC1F_Pos) /*!< 0x000000F0 */
+#define TIM_CCMR1_IC1F TIM_CCMR1_IC1F_Msk /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
+#define TIM_CCMR1_IC1F_0 (0x1U << TIM_CCMR1_IC1F_Pos) /*!< 0x00000010 */
+#define TIM_CCMR1_IC1F_1 (0x2U << TIM_CCMR1_IC1F_Pos) /*!< 0x00000020 */
+#define TIM_CCMR1_IC1F_2 (0x4U << TIM_CCMR1_IC1F_Pos) /*!< 0x00000040 */
+#define TIM_CCMR1_IC1F_3 (0x8U << TIM_CCMR1_IC1F_Pos) /*!< 0x00000080 */
+
+#define TIM_CCMR1_IC2PSC_Pos (10U)
+#define TIM_CCMR1_IC2PSC_Msk (0x3U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000C00 */
+#define TIM_CCMR1_IC2PSC TIM_CCMR1_IC2PSC_Msk /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
+#define TIM_CCMR1_IC2PSC_0 (0x1U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000400 */
+#define TIM_CCMR1_IC2PSC_1 (0x2U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000800 */
+
+#define TIM_CCMR1_IC2F_Pos (12U)
+#define TIM_CCMR1_IC2F_Msk (0xFU << TIM_CCMR1_IC2F_Pos) /*!< 0x0000F000 */
+#define TIM_CCMR1_IC2F TIM_CCMR1_IC2F_Msk /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
+#define TIM_CCMR1_IC2F_0 (0x1U << TIM_CCMR1_IC2F_Pos) /*!< 0x00001000 */
+#define TIM_CCMR1_IC2F_1 (0x2U << TIM_CCMR1_IC2F_Pos) /*!< 0x00002000 */
+#define TIM_CCMR1_IC2F_2 (0x4U << TIM_CCMR1_IC2F_Pos) /*!< 0x00004000 */
+#define TIM_CCMR1_IC2F_3 (0x8U << TIM_CCMR1_IC2F_Pos) /*!< 0x00008000 */
+
+/****************** Bit definition for TIM_CCMR2 register ******************/
+#define TIM_CCMR2_CC3S_Pos (0U)
+#define TIM_CCMR2_CC3S_Msk (0x3U << TIM_CCMR2_CC3S_Pos) /*!< 0x00000003 */
+#define TIM_CCMR2_CC3S TIM_CCMR2_CC3S_Msk /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
+#define TIM_CCMR2_CC3S_0 (0x1U << TIM_CCMR2_CC3S_Pos) /*!< 0x00000001 */
+#define TIM_CCMR2_CC3S_1 (0x2U << TIM_CCMR2_CC3S_Pos) /*!< 0x00000002 */
+
+#define TIM_CCMR2_OC3FE_Pos (2U)
+#define TIM_CCMR2_OC3FE_Msk (0x1U << TIM_CCMR2_OC3FE_Pos) /*!< 0x00000004 */
+#define TIM_CCMR2_OC3FE TIM_CCMR2_OC3FE_Msk /*!<Output Compare 3 Fast enable */
+#define TIM_CCMR2_OC3PE_Pos (3U)
+#define TIM_CCMR2_OC3PE_Msk (0x1U << TIM_CCMR2_OC3PE_Pos) /*!< 0x00000008 */
+#define TIM_CCMR2_OC3PE TIM_CCMR2_OC3PE_Msk /*!<Output Compare 3 Preload enable */
+
+#define TIM_CCMR2_OC3M_Pos (4U)
+#define TIM_CCMR2_OC3M_Msk (0x7U << TIM_CCMR2_OC3M_Pos) /*!< 0x00000070 */
+#define TIM_CCMR2_OC3M TIM_CCMR2_OC3M_Msk /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
+#define TIM_CCMR2_OC3M_0 (0x1U << TIM_CCMR2_OC3M_Pos) /*!< 0x00000010 */
+#define TIM_CCMR2_OC3M_1 (0x2U << TIM_CCMR2_OC3M_Pos) /*!< 0x00000020 */
+#define TIM_CCMR2_OC3M_2 (0x4U << TIM_CCMR2_OC3M_Pos) /*!< 0x00000040 */
+
+#define TIM_CCMR2_OC3CE_Pos (7U)
+#define TIM_CCMR2_OC3CE_Msk (0x1U << TIM_CCMR2_OC3CE_Pos) /*!< 0x00000080 */
+#define TIM_CCMR2_OC3CE TIM_CCMR2_OC3CE_Msk /*!<Output Compare 3 Clear Enable */
+
+#define TIM_CCMR2_CC4S_Pos (8U)
+#define TIM_CCMR2_CC4S_Msk (0x3U << TIM_CCMR2_CC4S_Pos) /*!< 0x00000300 */
+#define TIM_CCMR2_CC4S TIM_CCMR2_CC4S_Msk /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
+#define TIM_CCMR2_CC4S_0 (0x1U << TIM_CCMR2_CC4S_Pos) /*!< 0x00000100 */
+#define TIM_CCMR2_CC4S_1 (0x2U << TIM_CCMR2_CC4S_Pos) /*!< 0x00000200 */
+
+#define TIM_CCMR2_OC4FE_Pos (10U)
+#define TIM_CCMR2_OC4FE_Msk (0x1U << TIM_CCMR2_OC4FE_Pos) /*!< 0x00000400 */
+#define TIM_CCMR2_OC4FE TIM_CCMR2_OC4FE_Msk /*!<Output Compare 4 Fast enable */
+#define TIM_CCMR2_OC4PE_Pos (11U)
+#define TIM_CCMR2_OC4PE_Msk (0x1U << TIM_CCMR2_OC4PE_Pos) /*!< 0x00000800 */
+#define TIM_CCMR2_OC4PE TIM_CCMR2_OC4PE_Msk /*!<Output Compare 4 Preload enable */
+
+#define TIM_CCMR2_OC4M_Pos (12U)
+#define TIM_CCMR2_OC4M_Msk (0x7U << TIM_CCMR2_OC4M_Pos) /*!< 0x00007000 */
+#define TIM_CCMR2_OC4M TIM_CCMR2_OC4M_Msk /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
+#define TIM_CCMR2_OC4M_0 (0x1U << TIM_CCMR2_OC4M_Pos) /*!< 0x00001000 */
+#define TIM_CCMR2_OC4M_1 (0x2U << TIM_CCMR2_OC4M_Pos) /*!< 0x00002000 */
+#define TIM_CCMR2_OC4M_2 (0x4U << TIM_CCMR2_OC4M_Pos) /*!< 0x00004000 */
+
+#define TIM_CCMR2_OC4CE_Pos (15U)
+#define TIM_CCMR2_OC4CE_Msk (0x1U << TIM_CCMR2_OC4CE_Pos) /*!< 0x00008000 */
+#define TIM_CCMR2_OC4CE TIM_CCMR2_OC4CE_Msk /*!<Output Compare 4 Clear Enable */
+
+/*---------------------------------------------------------------------------*/
+
+#define TIM_CCMR2_IC3PSC_Pos (2U)
+#define TIM_CCMR2_IC3PSC_Msk (0x3U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x0000000C */
+#define TIM_CCMR2_IC3PSC TIM_CCMR2_IC3PSC_Msk /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
+#define TIM_CCMR2_IC3PSC_0 (0x1U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x00000004 */
+#define TIM_CCMR2_IC3PSC_1 (0x2U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x00000008 */
+
+#define TIM_CCMR2_IC3F_Pos (4U)
+#define TIM_CCMR2_IC3F_Msk (0xFU << TIM_CCMR2_IC3F_Pos) /*!< 0x000000F0 */
+#define TIM_CCMR2_IC3F TIM_CCMR2_IC3F_Msk /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
+#define TIM_CCMR2_IC3F_0 (0x1U << TIM_CCMR2_IC3F_Pos) /*!< 0x00000010 */
+#define TIM_CCMR2_IC3F_1 (0x2U << TIM_CCMR2_IC3F_Pos) /*!< 0x00000020 */
+#define TIM_CCMR2_IC3F_2 (0x4U << TIM_CCMR2_IC3F_Pos) /*!< 0x00000040 */
+#define TIM_CCMR2_IC3F_3 (0x8U << TIM_CCMR2_IC3F_Pos) /*!< 0x00000080 */
+
+#define TIM_CCMR2_IC4PSC_Pos (10U)
+#define TIM_CCMR2_IC4PSC_Msk (0x3U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000C00 */
+#define TIM_CCMR2_IC4PSC TIM_CCMR2_IC4PSC_Msk /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
+#define TIM_CCMR2_IC4PSC_0 (0x1U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000400 */
+#define TIM_CCMR2_IC4PSC_1 (0x2U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000800 */
+
+#define TIM_CCMR2_IC4F_Pos (12U)
+#define TIM_CCMR2_IC4F_Msk (0xFU << TIM_CCMR2_IC4F_Pos) /*!< 0x0000F000 */
+#define TIM_CCMR2_IC4F TIM_CCMR2_IC4F_Msk /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
+#define TIM_CCMR2_IC4F_0 (0x1U << TIM_CCMR2_IC4F_Pos) /*!< 0x00001000 */
+#define TIM_CCMR2_IC4F_1 (0x2U << TIM_CCMR2_IC4F_Pos) /*!< 0x00002000 */
+#define TIM_CCMR2_IC4F_2 (0x4U << TIM_CCMR2_IC4F_Pos) /*!< 0x00004000 */
+#define TIM_CCMR2_IC4F_3 (0x8U << TIM_CCMR2_IC4F_Pos) /*!< 0x00008000 */
+
+/******************* Bit definition for TIM_CCER register ******************/
+#define TIM_CCER_CC1E_Pos (0U)
+#define TIM_CCER_CC1E_Msk (0x1U << TIM_CCER_CC1E_Pos) /*!< 0x00000001 */
+#define TIM_CCER_CC1E TIM_CCER_CC1E_Msk /*!<Capture/Compare 1 output enable */
+#define TIM_CCER_CC1P_Pos (1U)
+#define TIM_CCER_CC1P_Msk (0x1U << TIM_CCER_CC1P_Pos) /*!< 0x00000002 */
+#define TIM_CCER_CC1P TIM_CCER_CC1P_Msk /*!<Capture/Compare 1 output Polarity */
+#define TIM_CCER_CC1NE_Pos (2U)
+#define TIM_CCER_CC1NE_Msk (0x1U << TIM_CCER_CC1NE_Pos) /*!< 0x00000004 */
+#define TIM_CCER_CC1NE TIM_CCER_CC1NE_Msk /*!<Capture/Compare 1 Complementary output enable */
+#define TIM_CCER_CC1NP_Pos (3U)
+#define TIM_CCER_CC1NP_Msk (0x1U << TIM_CCER_CC1NP_Pos) /*!< 0x00000008 */
+#define TIM_CCER_CC1NP TIM_CCER_CC1NP_Msk /*!<Capture/Compare 1 Complementary output Polarity */
+#define TIM_CCER_CC2E_Pos (4U)
+#define TIM_CCER_CC2E_Msk (0x1U << TIM_CCER_CC2E_Pos) /*!< 0x00000010 */
+#define TIM_CCER_CC2E TIM_CCER_CC2E_Msk /*!<Capture/Compare 2 output enable */
+#define TIM_CCER_CC2P_Pos (5U)
+#define TIM_CCER_CC2P_Msk (0x1U << TIM_CCER_CC2P_Pos) /*!< 0x00000020 */
+#define TIM_CCER_CC2P TIM_CCER_CC2P_Msk /*!<Capture/Compare 2 output Polarity */
+#define TIM_CCER_CC2NE_Pos (6U)
+#define TIM_CCER_CC2NE_Msk (0x1U << TIM_CCER_CC2NE_Pos) /*!< 0x00000040 */
+#define TIM_CCER_CC2NE TIM_CCER_CC2NE_Msk /*!<Capture/Compare 2 Complementary output enable */
+#define TIM_CCER_CC2NP_Pos (7U)
+#define TIM_CCER_CC2NP_Msk (0x1U << TIM_CCER_CC2NP_Pos) /*!< 0x00000080 */
+#define TIM_CCER_CC2NP TIM_CCER_CC2NP_Msk /*!<Capture/Compare 2 Complementary output Polarity */
+#define TIM_CCER_CC3E_Pos (8U)
+#define TIM_CCER_CC3E_Msk (0x1U << TIM_CCER_CC3E_Pos) /*!< 0x00000100 */
+#define TIM_CCER_CC3E TIM_CCER_CC3E_Msk /*!<Capture/Compare 3 output enable */
+#define TIM_CCER_CC3P_Pos (9U)
+#define TIM_CCER_CC3P_Msk (0x1U << TIM_CCER_CC3P_Pos) /*!< 0x00000200 */
+#define TIM_CCER_CC3P TIM_CCER_CC3P_Msk /*!<Capture/Compare 3 output Polarity */
+#define TIM_CCER_CC3NE_Pos (10U)
+#define TIM_CCER_CC3NE_Msk (0x1U << TIM_CCER_CC3NE_Pos) /*!< 0x00000400 */
+#define TIM_CCER_CC3NE TIM_CCER_CC3NE_Msk /*!<Capture/Compare 3 Complementary output enable */
+#define TIM_CCER_CC3NP_Pos (11U)
+#define TIM_CCER_CC3NP_Msk (0x1U << TIM_CCER_CC3NP_Pos) /*!< 0x00000800 */
+#define TIM_CCER_CC3NP TIM_CCER_CC3NP_Msk /*!<Capture/Compare 3 Complementary output Polarity */
+#define TIM_CCER_CC4E_Pos (12U)
+#define TIM_CCER_CC4E_Msk (0x1U << TIM_CCER_CC4E_Pos) /*!< 0x00001000 */
+#define TIM_CCER_CC4E TIM_CCER_CC4E_Msk /*!<Capture/Compare 4 output enable */
+#define TIM_CCER_CC4P_Pos (13U)
+#define TIM_CCER_CC4P_Msk (0x1U << TIM_CCER_CC4P_Pos) /*!< 0x00002000 */
+#define TIM_CCER_CC4P TIM_CCER_CC4P_Msk /*!<Capture/Compare 4 output Polarity */
+#define TIM_CCER_CC4NP_Pos (15U)
+#define TIM_CCER_CC4NP_Msk (0x1U << TIM_CCER_CC4NP_Pos) /*!< 0x00008000 */
+#define TIM_CCER_CC4NP TIM_CCER_CC4NP_Msk /*!<Capture/Compare 4 Complementary output Polarity */
+
+/******************* Bit definition for TIM_CNT register *******************/
+#define TIM_CNT_CNT_Pos (0U)
+#define TIM_CNT_CNT_Msk (0xFFFFFFFFU << TIM_CNT_CNT_Pos) /*!< 0xFFFFFFFF */
+#define TIM_CNT_CNT TIM_CNT_CNT_Msk /*!<Counter Value */
+
+/******************* Bit definition for TIM_PSC register *******************/
+#define TIM_PSC_PSC_Pos (0U)
+#define TIM_PSC_PSC_Msk (0xFFFFU << TIM_PSC_PSC_Pos) /*!< 0x0000FFFF */
+#define TIM_PSC_PSC TIM_PSC_PSC_Msk /*!<Prescaler Value */
+
+/******************* Bit definition for TIM_ARR register *******************/
+#define TIM_ARR_ARR_Pos (0U)
+#define TIM_ARR_ARR_Msk (0xFFFFFFFFU << TIM_ARR_ARR_Pos) /*!< 0xFFFFFFFF */
+#define TIM_ARR_ARR TIM_ARR_ARR_Msk /*!<actual auto-reload Value */
+
+/******************* Bit definition for TIM_RCR register *******************/
+#define TIM_RCR_REP_Pos (0U)
+#define TIM_RCR_REP_Msk (0xFFU << TIM_RCR_REP_Pos) /*!< 0x000000FF */
+#define TIM_RCR_REP TIM_RCR_REP_Msk /*!<Repetition Counter Value */
+
+/******************* Bit definition for TIM_CCR1 register ******************/
+#define TIM_CCR1_CCR1_Pos (0U)
+#define TIM_CCR1_CCR1_Msk (0xFFFFU << TIM_CCR1_CCR1_Pos) /*!< 0x0000FFFF */
+#define TIM_CCR1_CCR1 TIM_CCR1_CCR1_Msk /*!<Capture/Compare 1 Value */
+
+/******************* Bit definition for TIM_CCR2 register ******************/
+#define TIM_CCR2_CCR2_Pos (0U)
+#define TIM_CCR2_CCR2_Msk (0xFFFFU << TIM_CCR2_CCR2_Pos) /*!< 0x0000FFFF */
+#define TIM_CCR2_CCR2 TIM_CCR2_CCR2_Msk /*!<Capture/Compare 2 Value */
+
+/******************* Bit definition for TIM_CCR3 register ******************/
+#define TIM_CCR3_CCR3_Pos (0U)
+#define TIM_CCR3_CCR3_Msk (0xFFFFU << TIM_CCR3_CCR3_Pos) /*!< 0x0000FFFF */
+#define TIM_CCR3_CCR3 TIM_CCR3_CCR3_Msk /*!<Capture/Compare 3 Value */
+
+/******************* Bit definition for TIM_CCR4 register ******************/
+#define TIM_CCR4_CCR4_Pos (0U)
+#define TIM_CCR4_CCR4_Msk (0xFFFFU << TIM_CCR4_CCR4_Pos) /*!< 0x0000FFFF */
+#define TIM_CCR4_CCR4 TIM_CCR4_CCR4_Msk /*!<Capture/Compare 4 Value */
+
+/******************* Bit definition for TIM_BDTR register ******************/
+#define TIM_BDTR_DTG_Pos (0U)
+#define TIM_BDTR_DTG_Msk (0xFFU << TIM_BDTR_DTG_Pos) /*!< 0x000000FF */
+#define TIM_BDTR_DTG TIM_BDTR_DTG_Msk /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
+#define TIM_BDTR_DTG_0 (0x01U << TIM_BDTR_DTG_Pos) /*!< 0x00000001 */
+#define TIM_BDTR_DTG_1 (0x02U << TIM_BDTR_DTG_Pos) /*!< 0x00000002 */
+#define TIM_BDTR_DTG_2 (0x04U << TIM_BDTR_DTG_Pos) /*!< 0x00000004 */
+#define TIM_BDTR_DTG_3 (0x08U << TIM_BDTR_DTG_Pos) /*!< 0x00000008 */
+#define TIM_BDTR_DTG_4 (0x10U << TIM_BDTR_DTG_Pos) /*!< 0x00000010 */
+#define TIM_BDTR_DTG_5 (0x20U << TIM_BDTR_DTG_Pos) /*!< 0x00000020 */
+#define TIM_BDTR_DTG_6 (0x40U << TIM_BDTR_DTG_Pos) /*!< 0x00000040 */
+#define TIM_BDTR_DTG_7 (0x80U << TIM_BDTR_DTG_Pos) /*!< 0x00000080 */
+
+#define TIM_BDTR_LOCK_Pos (8U)
+#define TIM_BDTR_LOCK_Msk (0x3U << TIM_BDTR_LOCK_Pos) /*!< 0x00000300 */
+#define TIM_BDTR_LOCK TIM_BDTR_LOCK_Msk /*!<LOCK[1:0] bits (Lock Configuration) */
+#define TIM_BDTR_LOCK_0 (0x1U << TIM_BDTR_LOCK_Pos) /*!< 0x00000100 */
+#define TIM_BDTR_LOCK_1 (0x2U << TIM_BDTR_LOCK_Pos) /*!< 0x00000200 */
+
+#define TIM_BDTR_OSSI_Pos (10U)
+#define TIM_BDTR_OSSI_Msk (0x1U << TIM_BDTR_OSSI_Pos) /*!< 0x00000400 */
+#define TIM_BDTR_OSSI TIM_BDTR_OSSI_Msk /*!<Off-State Selection for Idle mode */
+#define TIM_BDTR_OSSR_Pos (11U)
+#define TIM_BDTR_OSSR_Msk (0x1U << TIM_BDTR_OSSR_Pos) /*!< 0x00000800 */
+#define TIM_BDTR_OSSR TIM_BDTR_OSSR_Msk /*!<Off-State Selection for Run mode */
+#define TIM_BDTR_BKE_Pos (12U)
+#define TIM_BDTR_BKE_Msk (0x1U << TIM_BDTR_BKE_Pos) /*!< 0x00001000 */
+#define TIM_BDTR_BKE TIM_BDTR_BKE_Msk /*!<Break enable */
+#define TIM_BDTR_BKP_Pos (13U)
+#define TIM_BDTR_BKP_Msk (0x1U << TIM_BDTR_BKP_Pos) /*!< 0x00002000 */
+#define TIM_BDTR_BKP TIM_BDTR_BKP_Msk /*!<Break Polarity */
+#define TIM_BDTR_AOE_Pos (14U)
+#define TIM_BDTR_AOE_Msk (0x1U << TIM_BDTR_AOE_Pos) /*!< 0x00004000 */
+#define TIM_BDTR_AOE TIM_BDTR_AOE_Msk /*!<Automatic Output enable */
+#define TIM_BDTR_MOE_Pos (15U)
+#define TIM_BDTR_MOE_Msk (0x1U << TIM_BDTR_MOE_Pos) /*!< 0x00008000 */
+#define TIM_BDTR_MOE TIM_BDTR_MOE_Msk /*!<Main Output enable */
+
+/******************* Bit definition for TIM_DCR register *******************/
+#define TIM_DCR_DBA_Pos (0U)
+#define TIM_DCR_DBA_Msk (0x1FU << TIM_DCR_DBA_Pos) /*!< 0x0000001F */
+#define TIM_DCR_DBA TIM_DCR_DBA_Msk /*!<DBA[4:0] bits (DMA Base Address) */
+#define TIM_DCR_DBA_0 (0x01U << TIM_DCR_DBA_Pos) /*!< 0x00000001 */
+#define TIM_DCR_DBA_1 (0x02U << TIM_DCR_DBA_Pos) /*!< 0x00000002 */
+#define TIM_DCR_DBA_2 (0x04U << TIM_DCR_DBA_Pos) /*!< 0x00000004 */
+#define TIM_DCR_DBA_3 (0x08U << TIM_DCR_DBA_Pos) /*!< 0x00000008 */
+#define TIM_DCR_DBA_4 (0x10U << TIM_DCR_DBA_Pos) /*!< 0x00000010 */
+
+#define TIM_DCR_DBL_Pos (8U)
+#define TIM_DCR_DBL_Msk (0x1FU << TIM_DCR_DBL_Pos) /*!< 0x00001F00 */
+#define TIM_DCR_DBL TIM_DCR_DBL_Msk /*!<DBL[4:0] bits (DMA Burst Length) */
+#define TIM_DCR_DBL_0 (0x01U << TIM_DCR_DBL_Pos) /*!< 0x00000100 */
+#define TIM_DCR_DBL_1 (0x02U << TIM_DCR_DBL_Pos) /*!< 0x00000200 */
+#define TIM_DCR_DBL_2 (0x04U << TIM_DCR_DBL_Pos) /*!< 0x00000400 */
+#define TIM_DCR_DBL_3 (0x08U << TIM_DCR_DBL_Pos) /*!< 0x00000800 */
+#define TIM_DCR_DBL_4 (0x10U << TIM_DCR_DBL_Pos) /*!< 0x00001000 */
+
+/******************* Bit definition for TIM_DMAR register ******************/
+#define TIM_DMAR_DMAB_Pos (0U)
+#define TIM_DMAR_DMAB_Msk (0xFFFFU << TIM_DMAR_DMAB_Pos) /*!< 0x0000FFFF */
+#define TIM_DMAR_DMAB TIM_DMAR_DMAB_Msk /*!<DMA register for burst accesses */
+
+/******************* Bit definition for TIM_OR register ********************/
+
+/******************************************************************************/
+/* */
+/* Real-Time Clock */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for RTC_CRH register ********************/
+#define RTC_CRH_SECIE_Pos (0U)
+#define RTC_CRH_SECIE_Msk (0x1U << RTC_CRH_SECIE_Pos) /*!< 0x00000001 */
+#define RTC_CRH_SECIE RTC_CRH_SECIE_Msk /*!< Second Interrupt Enable */
+#define RTC_CRH_ALRIE_Pos (1U)
+#define RTC_CRH_ALRIE_Msk (0x1U << RTC_CRH_ALRIE_Pos) /*!< 0x00000002 */
+#define RTC_CRH_ALRIE RTC_CRH_ALRIE_Msk /*!< Alarm Interrupt Enable */
+#define RTC_CRH_OWIE_Pos (2U)
+#define RTC_CRH_OWIE_Msk (0x1U << RTC_CRH_OWIE_Pos) /*!< 0x00000004 */
+#define RTC_CRH_OWIE RTC_CRH_OWIE_Msk /*!< OverfloW Interrupt Enable */
+
+/******************* Bit definition for RTC_CRL register ********************/
+#define RTC_CRL_SECF_Pos (0U)
+#define RTC_CRL_SECF_Msk (0x1U << RTC_CRL_SECF_Pos) /*!< 0x00000001 */
+#define RTC_CRL_SECF RTC_CRL_SECF_Msk /*!< Second Flag */
+#define RTC_CRL_ALRF_Pos (1U)
+#define RTC_CRL_ALRF_Msk (0x1U << RTC_CRL_ALRF_Pos) /*!< 0x00000002 */
+#define RTC_CRL_ALRF RTC_CRL_ALRF_Msk /*!< Alarm Flag */
+#define RTC_CRL_OWF_Pos (2U)
+#define RTC_CRL_OWF_Msk (0x1U << RTC_CRL_OWF_Pos) /*!< 0x00000004 */
+#define RTC_CRL_OWF RTC_CRL_OWF_Msk /*!< OverfloW Flag */
+#define RTC_CRL_RSF_Pos (3U)
+#define RTC_CRL_RSF_Msk (0x1U << RTC_CRL_RSF_Pos) /*!< 0x00000008 */
+#define RTC_CRL_RSF RTC_CRL_RSF_Msk /*!< Registers Synchronized Flag */
+#define RTC_CRL_CNF_Pos (4U)
+#define RTC_CRL_CNF_Msk (0x1U << RTC_CRL_CNF_Pos) /*!< 0x00000010 */
+#define RTC_CRL_CNF RTC_CRL_CNF_Msk /*!< Configuration Flag */
+#define RTC_CRL_RTOFF_Pos (5U)
+#define RTC_CRL_RTOFF_Msk (0x1U << RTC_CRL_RTOFF_Pos) /*!< 0x00000020 */
+#define RTC_CRL_RTOFF RTC_CRL_RTOFF_Msk /*!< RTC operation OFF */
+
+/******************* Bit definition for RTC_PRLH register *******************/
+#define RTC_PRLH_PRL_Pos (0U)
+#define RTC_PRLH_PRL_Msk (0xFU << RTC_PRLH_PRL_Pos) /*!< 0x0000000F */
+#define RTC_PRLH_PRL RTC_PRLH_PRL_Msk /*!< RTC Prescaler Reload Value High */
+
+/******************* Bit definition for RTC_PRLL register *******************/
+#define RTC_PRLL_PRL_Pos (0U)
+#define RTC_PRLL_PRL_Msk (0xFFFFU << RTC_PRLL_PRL_Pos) /*!< 0x0000FFFF */
+#define RTC_PRLL_PRL RTC_PRLL_PRL_Msk /*!< RTC Prescaler Reload Value Low */
+
+/******************* Bit definition for RTC_DIVH register *******************/
+#define RTC_DIVH_RTC_DIV_Pos (0U)
+#define RTC_DIVH_RTC_DIV_Msk (0xFU << RTC_DIVH_RTC_DIV_Pos) /*!< 0x0000000F */
+#define RTC_DIVH_RTC_DIV RTC_DIVH_RTC_DIV_Msk /*!< RTC Clock Divider High */
+
+/******************* Bit definition for RTC_DIVL register *******************/
+#define RTC_DIVL_RTC_DIV_Pos (0U)
+#define RTC_DIVL_RTC_DIV_Msk (0xFFFFU << RTC_DIVL_RTC_DIV_Pos) /*!< 0x0000FFFF */
+#define RTC_DIVL_RTC_DIV RTC_DIVL_RTC_DIV_Msk /*!< RTC Clock Divider Low */
+
+/******************* Bit definition for RTC_CNTH register *******************/
+#define RTC_CNTH_RTC_CNT_Pos (0U)
+#define RTC_CNTH_RTC_CNT_Msk (0xFFFFU << RTC_CNTH_RTC_CNT_Pos) /*!< 0x0000FFFF */
+#define RTC_CNTH_RTC_CNT RTC_CNTH_RTC_CNT_Msk /*!< RTC Counter High */
+
+/******************* Bit definition for RTC_CNTL register *******************/
+#define RTC_CNTL_RTC_CNT_Pos (0U)
+#define RTC_CNTL_RTC_CNT_Msk (0xFFFFU << RTC_CNTL_RTC_CNT_Pos) /*!< 0x0000FFFF */
+#define RTC_CNTL_RTC_CNT RTC_CNTL_RTC_CNT_Msk /*!< RTC Counter Low */
+
+/******************* Bit definition for RTC_ALRH register *******************/
+#define RTC_ALRH_RTC_ALR_Pos (0U)
+#define RTC_ALRH_RTC_ALR_Msk (0xFFFFU << RTC_ALRH_RTC_ALR_Pos) /*!< 0x0000FFFF */
+#define RTC_ALRH_RTC_ALR RTC_ALRH_RTC_ALR_Msk /*!< RTC Alarm High */
+
+/******************* Bit definition for RTC_ALRL register *******************/
+#define RTC_ALRL_RTC_ALR_Pos (0U)
+#define RTC_ALRL_RTC_ALR_Msk (0xFFFFU << RTC_ALRL_RTC_ALR_Pos) /*!< 0x0000FFFF */
+#define RTC_ALRL_RTC_ALR RTC_ALRL_RTC_ALR_Msk /*!< RTC Alarm Low */
+
+/******************************************************************************/
+/* */
+/* Independent WATCHDOG (IWDG) */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for IWDG_KR register ********************/
+#define IWDG_KR_KEY_Pos (0U)
+#define IWDG_KR_KEY_Msk (0xFFFFU << IWDG_KR_KEY_Pos) /*!< 0x0000FFFF */
+#define IWDG_KR_KEY IWDG_KR_KEY_Msk /*!< Key value (write only, read 0000h) */
+
+/******************* Bit definition for IWDG_PR register ********************/
+#define IWDG_PR_PR_Pos (0U)
+#define IWDG_PR_PR_Msk (0x7U << IWDG_PR_PR_Pos) /*!< 0x00000007 */
+#define IWDG_PR_PR IWDG_PR_PR_Msk /*!< PR[2:0] (Prescaler divider) */
+#define IWDG_PR_PR_0 (0x1U << IWDG_PR_PR_Pos) /*!< 0x00000001 */
+#define IWDG_PR_PR_1 (0x2U << IWDG_PR_PR_Pos) /*!< 0x00000002 */
+#define IWDG_PR_PR_2 (0x4U << IWDG_PR_PR_Pos) /*!< 0x00000004 */
+
+/******************* Bit definition for IWDG_RLR register *******************/
+#define IWDG_RLR_RL_Pos (0U)
+#define IWDG_RLR_RL_Msk (0xFFFU << IWDG_RLR_RL_Pos) /*!< 0x00000FFF */
+#define IWDG_RLR_RL IWDG_RLR_RL_Msk /*!< Watchdog counter reload value */
+
+/******************* Bit definition for IWDG_SR register ********************/
+#define IWDG_SR_PVU_Pos (0U)
+#define IWDG_SR_PVU_Msk (0x1U << IWDG_SR_PVU_Pos) /*!< 0x00000001 */
+#define IWDG_SR_PVU IWDG_SR_PVU_Msk /*!< Watchdog prescaler value update */
+#define IWDG_SR_RVU_Pos (1U)
+#define IWDG_SR_RVU_Msk (0x1U << IWDG_SR_RVU_Pos) /*!< 0x00000002 */
+#define IWDG_SR_RVU IWDG_SR_RVU_Msk /*!< Watchdog counter reload value update */
+
+/******************************************************************************/
+/* */
+/* Window WATCHDOG (WWDG) */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for WWDG_CR register ********************/
+#define WWDG_CR_T_Pos (0U)
+#define WWDG_CR_T_Msk (0x7FU << WWDG_CR_T_Pos) /*!< 0x0000007F */
+#define WWDG_CR_T WWDG_CR_T_Msk /*!< T[6:0] bits (7-Bit counter (MSB to LSB)) */
+#define WWDG_CR_T_0 (0x01U << WWDG_CR_T_Pos) /*!< 0x00000001 */
+#define WWDG_CR_T_1 (0x02U << WWDG_CR_T_Pos) /*!< 0x00000002 */
+#define WWDG_CR_T_2 (0x04U << WWDG_CR_T_Pos) /*!< 0x00000004 */
+#define WWDG_CR_T_3 (0x08U << WWDG_CR_T_Pos) /*!< 0x00000008 */
+#define WWDG_CR_T_4 (0x10U << WWDG_CR_T_Pos) /*!< 0x00000010 */
+#define WWDG_CR_T_5 (0x20U << WWDG_CR_T_Pos) /*!< 0x00000020 */
+#define WWDG_CR_T_6 (0x40U << WWDG_CR_T_Pos) /*!< 0x00000040 */
+
+/* Legacy defines */
+#define WWDG_CR_T0 WWDG_CR_T_0
+#define WWDG_CR_T1 WWDG_CR_T_1
+#define WWDG_CR_T2 WWDG_CR_T_2
+#define WWDG_CR_T3 WWDG_CR_T_3
+#define WWDG_CR_T4 WWDG_CR_T_4
+#define WWDG_CR_T5 WWDG_CR_T_5
+#define WWDG_CR_T6 WWDG_CR_T_6
+
+#define WWDG_CR_WDGA_Pos (7U)
+#define WWDG_CR_WDGA_Msk (0x1U << WWDG_CR_WDGA_Pos) /*!< 0x00000080 */
+#define WWDG_CR_WDGA WWDG_CR_WDGA_Msk /*!< Activation bit */
+
+/******************* Bit definition for WWDG_CFR register *******************/
+#define WWDG_CFR_W_Pos (0U)
+#define WWDG_CFR_W_Msk (0x7FU << WWDG_CFR_W_Pos) /*!< 0x0000007F */
+#define WWDG_CFR_W WWDG_CFR_W_Msk /*!< W[6:0] bits (7-bit window value) */
+#define WWDG_CFR_W_0 (0x01U << WWDG_CFR_W_Pos) /*!< 0x00000001 */
+#define WWDG_CFR_W_1 (0x02U << WWDG_CFR_W_Pos) /*!< 0x00000002 */
+#define WWDG_CFR_W_2 (0x04U << WWDG_CFR_W_Pos) /*!< 0x00000004 */
+#define WWDG_CFR_W_3 (0x08U << WWDG_CFR_W_Pos) /*!< 0x00000008 */
+#define WWDG_CFR_W_4 (0x10U << WWDG_CFR_W_Pos) /*!< 0x00000010 */
+#define WWDG_CFR_W_5 (0x20U << WWDG_CFR_W_Pos) /*!< 0x00000020 */
+#define WWDG_CFR_W_6 (0x40U << WWDG_CFR_W_Pos) /*!< 0x00000040 */
+
+/* Legacy defines */
+#define WWDG_CFR_W0 WWDG_CFR_W_0
+#define WWDG_CFR_W1 WWDG_CFR_W_1
+#define WWDG_CFR_W2 WWDG_CFR_W_2
+#define WWDG_CFR_W3 WWDG_CFR_W_3
+#define WWDG_CFR_W4 WWDG_CFR_W_4
+#define WWDG_CFR_W5 WWDG_CFR_W_5
+#define WWDG_CFR_W6 WWDG_CFR_W_6
+
+#define WWDG_CFR_WDGTB_Pos (7U)
+#define WWDG_CFR_WDGTB_Msk (0x3U << WWDG_CFR_WDGTB_Pos) /*!< 0x00000180 */
+#define WWDG_CFR_WDGTB WWDG_CFR_WDGTB_Msk /*!< WDGTB[1:0] bits (Timer Base) */
+#define WWDG_CFR_WDGTB_0 (0x1U << WWDG_CFR_WDGTB_Pos) /*!< 0x00000080 */
+#define WWDG_CFR_WDGTB_1 (0x2U << WWDG_CFR_WDGTB_Pos) /*!< 0x00000100 */
+
+/* Legacy defines */
+#define WWDG_CFR_WDGTB0 WWDG_CFR_WDGTB_0
+#define WWDG_CFR_WDGTB1 WWDG_CFR_WDGTB_1
+
+#define WWDG_CFR_EWI_Pos (9U)
+#define WWDG_CFR_EWI_Msk (0x1U << WWDG_CFR_EWI_Pos) /*!< 0x00000200 */
+#define WWDG_CFR_EWI WWDG_CFR_EWI_Msk /*!< Early Wakeup Interrupt */
+
+/******************* Bit definition for WWDG_SR register ********************/
+#define WWDG_SR_EWIF_Pos (0U)
+#define WWDG_SR_EWIF_Msk (0x1U << WWDG_SR_EWIF_Pos) /*!< 0x00000001 */
+#define WWDG_SR_EWIF WWDG_SR_EWIF_Msk /*!< Early Wakeup Interrupt Flag */
+
+/******************************************************************************/
+/* */
+/* Flexible Static Memory Controller */
+/* */
+/******************************************************************************/
+
+/****************** Bit definition for FSMC_BCRx (x=1..4) register **********/
+#define FSMC_BCRx_MBKEN_Pos (0U)
+#define FSMC_BCRx_MBKEN_Msk (0x1U << FSMC_BCRx_MBKEN_Pos) /*!< 0x00000001 */
+#define FSMC_BCRx_MBKEN FSMC_BCRx_MBKEN_Msk /*!< Memory bank enable bit */
+#define FSMC_BCRx_MUXEN_Pos (1U)
+#define FSMC_BCRx_MUXEN_Msk (0x1U << FSMC_BCRx_MUXEN_Pos) /*!< 0x00000002 */
+#define FSMC_BCRx_MUXEN FSMC_BCRx_MUXEN_Msk /*!< Address/data multiplexing enable bit */
+
+#define FSMC_BCRx_MTYP_Pos (2U)
+#define FSMC_BCRx_MTYP_Msk (0x3U << FSMC_BCRx_MTYP_Pos) /*!< 0x0000000C */
+#define FSMC_BCRx_MTYP FSMC_BCRx_MTYP_Msk /*!< MTYP[1:0] bits (Memory type) */
+#define FSMC_BCRx_MTYP_0 (0x1U << FSMC_BCRx_MTYP_Pos) /*!< 0x00000004 */
+#define FSMC_BCRx_MTYP_1 (0x2U << FSMC_BCRx_MTYP_Pos) /*!< 0x00000008 */
+
+#define FSMC_BCRx_MWID_Pos (4U)
+#define FSMC_BCRx_MWID_Msk (0x3U << FSMC_BCRx_MWID_Pos) /*!< 0x00000030 */
+#define FSMC_BCRx_MWID FSMC_BCRx_MWID_Msk /*!< MWID[1:0] bits (Memory data bus width) */
+#define FSMC_BCRx_MWID_0 (0x1U << FSMC_BCRx_MWID_Pos) /*!< 0x00000010 */
+#define FSMC_BCRx_MWID_1 (0x2U << FSMC_BCRx_MWID_Pos) /*!< 0x00000020 */
+
+#define FSMC_BCRx_FACCEN_Pos (6U)
+#define FSMC_BCRx_FACCEN_Msk (0x1U << FSMC_BCRx_FACCEN_Pos) /*!< 0x00000040 */
+#define FSMC_BCRx_FACCEN FSMC_BCRx_FACCEN_Msk /*!< Flash access enable */
+#define FSMC_BCRx_BURSTEN_Pos (8U)
+#define FSMC_BCRx_BURSTEN_Msk (0x1U << FSMC_BCRx_BURSTEN_Pos) /*!< 0x00000100 */
+#define FSMC_BCRx_BURSTEN FSMC_BCRx_BURSTEN_Msk /*!< Burst enable bit */
+#define FSMC_BCRx_WAITPOL_Pos (9U)
+#define FSMC_BCRx_WAITPOL_Msk (0x1U << FSMC_BCRx_WAITPOL_Pos) /*!< 0x00000200 */
+#define FSMC_BCRx_WAITPOL FSMC_BCRx_WAITPOL_Msk /*!< Wait signal polarity bit */
+#define FSMC_BCRx_WRAPMOD_Pos (10U)
+#define FSMC_BCRx_WRAPMOD_Msk (0x1U << FSMC_BCRx_WRAPMOD_Pos) /*!< 0x00000400 */
+#define FSMC_BCRx_WRAPMOD FSMC_BCRx_WRAPMOD_Msk /*!< Wrapped burst mode support */
+#define FSMC_BCRx_WAITCFG_Pos (11U)
+#define FSMC_BCRx_WAITCFG_Msk (0x1U << FSMC_BCRx_WAITCFG_Pos) /*!< 0x00000800 */
+#define FSMC_BCRx_WAITCFG FSMC_BCRx_WAITCFG_Msk /*!< Wait timing configuration */
+#define FSMC_BCRx_WREN_Pos (12U)
+#define FSMC_BCRx_WREN_Msk (0x1U << FSMC_BCRx_WREN_Pos) /*!< 0x00001000 */
+#define FSMC_BCRx_WREN FSMC_BCRx_WREN_Msk /*!< Write enable bit */
+#define FSMC_BCRx_WAITEN_Pos (13U)
+#define FSMC_BCRx_WAITEN_Msk (0x1U << FSMC_BCRx_WAITEN_Pos) /*!< 0x00002000 */
+#define FSMC_BCRx_WAITEN FSMC_BCRx_WAITEN_Msk /*!< Wait enable bit */
+#define FSMC_BCRx_EXTMOD_Pos (14U)
+#define FSMC_BCRx_EXTMOD_Msk (0x1U << FSMC_BCRx_EXTMOD_Pos) /*!< 0x00004000 */
+#define FSMC_BCRx_EXTMOD FSMC_BCRx_EXTMOD_Msk /*!< Extended mode enable */
+#define FSMC_BCRx_ASYNCWAIT_Pos (15U)
+#define FSMC_BCRx_ASYNCWAIT_Msk (0x1U << FSMC_BCRx_ASYNCWAIT_Pos) /*!< 0x00008000 */
+#define FSMC_BCRx_ASYNCWAIT FSMC_BCRx_ASYNCWAIT_Msk /*!< Asynchronous wait */
+#define FSMC_BCRx_CBURSTRW_Pos (19U)
+#define FSMC_BCRx_CBURSTRW_Msk (0x1U << FSMC_BCRx_CBURSTRW_Pos) /*!< 0x00080000 */
+#define FSMC_BCRx_CBURSTRW FSMC_BCRx_CBURSTRW_Msk /*!< Write burst enable */
+
+/****************** Bit definition for FSMC_BTRx (x=1..4) register ******/
+#define FSMC_BTRx_ADDSET_Pos (0U)
+#define FSMC_BTRx_ADDSET_Msk (0xFU << FSMC_BTRx_ADDSET_Pos) /*!< 0x0000000F */
+#define FSMC_BTRx_ADDSET FSMC_BTRx_ADDSET_Msk /*!< ADDSET[3:0] bits (Address setup phase duration) */
+#define FSMC_BTRx_ADDSET_0 (0x1U << FSMC_BTRx_ADDSET_Pos) /*!< 0x00000001 */
+#define FSMC_BTRx_ADDSET_1 (0x2U << FSMC_BTRx_ADDSET_Pos) /*!< 0x00000002 */
+#define FSMC_BTRx_ADDSET_2 (0x4U << FSMC_BTRx_ADDSET_Pos) /*!< 0x00000004 */
+#define FSMC_BTRx_ADDSET_3 (0x8U << FSMC_BTRx_ADDSET_Pos) /*!< 0x00000008 */
+
+#define FSMC_BTRx_ADDHLD_Pos (4U)
+#define FSMC_BTRx_ADDHLD_Msk (0xFU << FSMC_BTRx_ADDHLD_Pos) /*!< 0x000000F0 */
+#define FSMC_BTRx_ADDHLD FSMC_BTRx_ADDHLD_Msk /*!< ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FSMC_BTRx_ADDHLD_0 (0x1U << FSMC_BTRx_ADDHLD_Pos) /*!< 0x00000010 */
+#define FSMC_BTRx_ADDHLD_1 (0x2U << FSMC_BTRx_ADDHLD_Pos) /*!< 0x00000020 */
+#define FSMC_BTRx_ADDHLD_2 (0x4U << FSMC_BTRx_ADDHLD_Pos) /*!< 0x00000040 */
+#define FSMC_BTRx_ADDHLD_3 (0x8U << FSMC_BTRx_ADDHLD_Pos) /*!< 0x00000080 */
+
+#define FSMC_BTRx_DATAST_Pos (8U)
+#define FSMC_BTRx_DATAST_Msk (0xFFU << FSMC_BTRx_DATAST_Pos) /*!< 0x0000FF00 */
+#define FSMC_BTRx_DATAST FSMC_BTRx_DATAST_Msk /*!< DATAST [3:0] bits (Data-phase duration) */
+#define FSMC_BTRx_DATAST_0 (0x01U << FSMC_BTRx_DATAST_Pos) /*!< 0x00000100 */
+#define FSMC_BTRx_DATAST_1 (0x02U << FSMC_BTRx_DATAST_Pos) /*!< 0x00000200 */
+#define FSMC_BTRx_DATAST_2 (0x04U << FSMC_BTRx_DATAST_Pos) /*!< 0x00000400 */
+#define FSMC_BTRx_DATAST_3 (0x08U << FSMC_BTRx_DATAST_Pos) /*!< 0x00000800 */
+#define FSMC_BTRx_DATAST_4 (0x10U << FSMC_BTRx_DATAST_Pos) /*!< 0x00001000 */
+#define FSMC_BTRx_DATAST_5 (0x20U << FSMC_BTRx_DATAST_Pos) /*!< 0x00002000 */
+#define FSMC_BTRx_DATAST_6 (0x40U << FSMC_BTRx_DATAST_Pos) /*!< 0x00004000 */
+#define FSMC_BTRx_DATAST_7 (0x80U << FSMC_BTRx_DATAST_Pos) /*!< 0x00008000 */
+
+#define FSMC_BTRx_BUSTURN_Pos (16U)
+#define FSMC_BTRx_BUSTURN_Msk (0xFU << FSMC_BTRx_BUSTURN_Pos) /*!< 0x000F0000 */
+#define FSMC_BTRx_BUSTURN FSMC_BTRx_BUSTURN_Msk /*!< BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define FSMC_BTRx_BUSTURN_0 (0x1U << FSMC_BTRx_BUSTURN_Pos) /*!< 0x00010000 */
+#define FSMC_BTRx_BUSTURN_1 (0x2U << FSMC_BTRx_BUSTURN_Pos) /*!< 0x00020000 */
+#define FSMC_BTRx_BUSTURN_2 (0x4U << FSMC_BTRx_BUSTURN_Pos) /*!< 0x00040000 */
+#define FSMC_BTRx_BUSTURN_3 (0x8U << FSMC_BTRx_BUSTURN_Pos) /*!< 0x00080000 */
+
+#define FSMC_BTRx_CLKDIV_Pos (20U)
+#define FSMC_BTRx_CLKDIV_Msk (0xFU << FSMC_BTRx_CLKDIV_Pos) /*!< 0x00F00000 */
+#define FSMC_BTRx_CLKDIV FSMC_BTRx_CLKDIV_Msk /*!< CLKDIV[3:0] bits (Clock divide ratio) */
+#define FSMC_BTRx_CLKDIV_0 (0x1U << FSMC_BTRx_CLKDIV_Pos) /*!< 0x00100000 */
+#define FSMC_BTRx_CLKDIV_1 (0x2U << FSMC_BTRx_CLKDIV_Pos) /*!< 0x00200000 */
+#define FSMC_BTRx_CLKDIV_2 (0x4U << FSMC_BTRx_CLKDIV_Pos) /*!< 0x00400000 */
+#define FSMC_BTRx_CLKDIV_3 (0x8U << FSMC_BTRx_CLKDIV_Pos) /*!< 0x00800000 */
+
+#define FSMC_BTRx_DATLAT_Pos (24U)
+#define FSMC_BTRx_DATLAT_Msk (0xFU << FSMC_BTRx_DATLAT_Pos) /*!< 0x0F000000 */
+#define FSMC_BTRx_DATLAT FSMC_BTRx_DATLAT_Msk /*!< DATLA[3:0] bits (Data latency) */
+#define FSMC_BTRx_DATLAT_0 (0x1U << FSMC_BTRx_DATLAT_Pos) /*!< 0x01000000 */
+#define FSMC_BTRx_DATLAT_1 (0x2U << FSMC_BTRx_DATLAT_Pos) /*!< 0x02000000 */
+#define FSMC_BTRx_DATLAT_2 (0x4U << FSMC_BTRx_DATLAT_Pos) /*!< 0x04000000 */
+#define FSMC_BTRx_DATLAT_3 (0x8U << FSMC_BTRx_DATLAT_Pos) /*!< 0x08000000 */
+
+#define FSMC_BTRx_ACCMOD_Pos (28U)
+#define FSMC_BTRx_ACCMOD_Msk (0x3U << FSMC_BTRx_ACCMOD_Pos) /*!< 0x30000000 */
+#define FSMC_BTRx_ACCMOD FSMC_BTRx_ACCMOD_Msk /*!< ACCMOD[1:0] bits (Access mode) */
+#define FSMC_BTRx_ACCMOD_0 (0x1U << FSMC_BTRx_ACCMOD_Pos) /*!< 0x10000000 */
+#define FSMC_BTRx_ACCMOD_1 (0x2U << FSMC_BTRx_ACCMOD_Pos) /*!< 0x20000000 */
+
+/****************** Bit definition for FSMC_BWTRx (x=1..4) register ******/
+#define FSMC_BWTRx_ADDSET_Pos (0U)
+#define FSMC_BWTRx_ADDSET_Msk (0xFU << FSMC_BWTRx_ADDSET_Pos) /*!< 0x0000000F */
+#define FSMC_BWTRx_ADDSET FSMC_BWTRx_ADDSET_Msk /*!< ADDSET[3:0] bits (Address setup phase duration) */
+#define FSMC_BWTRx_ADDSET_0 (0x1U << FSMC_BWTRx_ADDSET_Pos) /*!< 0x00000001 */
+#define FSMC_BWTRx_ADDSET_1 (0x2U << FSMC_BWTRx_ADDSET_Pos) /*!< 0x00000002 */
+#define FSMC_BWTRx_ADDSET_2 (0x4U << FSMC_BWTRx_ADDSET_Pos) /*!< 0x00000004 */
+#define FSMC_BWTRx_ADDSET_3 (0x8U << FSMC_BWTRx_ADDSET_Pos) /*!< 0x00000008 */
+
+#define FSMC_BWTRx_ADDHLD_Pos (4U)
+#define FSMC_BWTRx_ADDHLD_Msk (0xFU << FSMC_BWTRx_ADDHLD_Pos) /*!< 0x000000F0 */
+#define FSMC_BWTRx_ADDHLD FSMC_BWTRx_ADDHLD_Msk /*!< ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FSMC_BWTRx_ADDHLD_0 (0x1U << FSMC_BWTRx_ADDHLD_Pos) /*!< 0x00000010 */
+#define FSMC_BWTRx_ADDHLD_1 (0x2U << FSMC_BWTRx_ADDHLD_Pos) /*!< 0x00000020 */
+#define FSMC_BWTRx_ADDHLD_2 (0x4U << FSMC_BWTRx_ADDHLD_Pos) /*!< 0x00000040 */
+#define FSMC_BWTRx_ADDHLD_3 (0x8U << FSMC_BWTRx_ADDHLD_Pos) /*!< 0x00000080 */
+
+#define FSMC_BWTRx_DATAST_Pos (8U)
+#define FSMC_BWTRx_DATAST_Msk (0xFFU << FSMC_BWTRx_DATAST_Pos) /*!< 0x0000FF00 */
+#define FSMC_BWTRx_DATAST FSMC_BWTRx_DATAST_Msk /*!< DATAST [3:0] bits (Data-phase duration) */
+#define FSMC_BWTRx_DATAST_0 (0x01U << FSMC_BWTRx_DATAST_Pos) /*!< 0x00000100 */
+#define FSMC_BWTRx_DATAST_1 (0x02U << FSMC_BWTRx_DATAST_Pos) /*!< 0x00000200 */
+#define FSMC_BWTRx_DATAST_2 (0x04U << FSMC_BWTRx_DATAST_Pos) /*!< 0x00000400 */
+#define FSMC_BWTRx_DATAST_3 (0x08U << FSMC_BWTRx_DATAST_Pos) /*!< 0x00000800 */
+#define FSMC_BWTRx_DATAST_4 (0x10U << FSMC_BWTRx_DATAST_Pos) /*!< 0x00001000 */
+#define FSMC_BWTRx_DATAST_5 (0x20U << FSMC_BWTRx_DATAST_Pos) /*!< 0x00002000 */
+#define FSMC_BWTRx_DATAST_6 (0x40U << FSMC_BWTRx_DATAST_Pos) /*!< 0x00004000 */
+#define FSMC_BWTRx_DATAST_7 (0x80U << FSMC_BWTRx_DATAST_Pos) /*!< 0x00008000 */
+
+#define FSMC_BWTRx_BUSTURN_Pos (16U)
+#define FSMC_BWTRx_BUSTURN_Msk (0xFU << FSMC_BWTRx_BUSTURN_Pos) /*!< 0x000F0000 */
+#define FSMC_BWTRx_BUSTURN FSMC_BWTRx_BUSTURN_Msk /*!< BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define FSMC_BWTRx_BUSTURN_0 (0x1U << FSMC_BWTRx_BUSTURN_Pos) /*!< 0x00010000 */
+#define FSMC_BWTRx_BUSTURN_1 (0x2U << FSMC_BWTRx_BUSTURN_Pos) /*!< 0x00020000 */
+#define FSMC_BWTRx_BUSTURN_2 (0x4U << FSMC_BWTRx_BUSTURN_Pos) /*!< 0x00040000 */
+#define FSMC_BWTRx_BUSTURN_3 (0x8U << FSMC_BWTRx_BUSTURN_Pos) /*!< 0x00080000 */
+
+#define FSMC_BWTRx_ACCMOD_Pos (28U)
+#define FSMC_BWTRx_ACCMOD_Msk (0x3U << FSMC_BWTRx_ACCMOD_Pos) /*!< 0x30000000 */
+#define FSMC_BWTRx_ACCMOD FSMC_BWTRx_ACCMOD_Msk /*!< ACCMOD[1:0] bits (Access mode) */
+#define FSMC_BWTRx_ACCMOD_0 (0x1U << FSMC_BWTRx_ACCMOD_Pos) /*!< 0x10000000 */
+#define FSMC_BWTRx_ACCMOD_1 (0x2U << FSMC_BWTRx_ACCMOD_Pos) /*!< 0x20000000 */
+
+/****************** Bit definition for FSMC_PCRx (x = 2 to 4) register *******************/
+#define FSMC_PCRx_PWAITEN_Pos (1U)
+#define FSMC_PCRx_PWAITEN_Msk (0x1U << FSMC_PCRx_PWAITEN_Pos) /*!< 0x00000002 */
+#define FSMC_PCRx_PWAITEN FSMC_PCRx_PWAITEN_Msk /*!< Wait feature enable bit */
+#define FSMC_PCRx_PBKEN_Pos (2U)
+#define FSMC_PCRx_PBKEN_Msk (0x1U << FSMC_PCRx_PBKEN_Pos) /*!< 0x00000004 */
+#define FSMC_PCRx_PBKEN FSMC_PCRx_PBKEN_Msk /*!< PC Card/NAND Flash memory bank enable bit */
+#define FSMC_PCRx_PTYP_Pos (3U)
+#define FSMC_PCRx_PTYP_Msk (0x1U << FSMC_PCRx_PTYP_Pos) /*!< 0x00000008 */
+#define FSMC_PCRx_PTYP FSMC_PCRx_PTYP_Msk /*!< Memory type */
+
+#define FSMC_PCRx_PWID_Pos (4U)
+#define FSMC_PCRx_PWID_Msk (0x3U << FSMC_PCRx_PWID_Pos) /*!< 0x00000030 */
+#define FSMC_PCRx_PWID FSMC_PCRx_PWID_Msk /*!< PWID[1:0] bits (NAND Flash databus width) */
+#define FSMC_PCRx_PWID_0 (0x1U << FSMC_PCRx_PWID_Pos) /*!< 0x00000010 */
+#define FSMC_PCRx_PWID_1 (0x2U << FSMC_PCRx_PWID_Pos) /*!< 0x00000020 */
+
+#define FSMC_PCRx_ECCEN_Pos (6U)
+#define FSMC_PCRx_ECCEN_Msk (0x1U << FSMC_PCRx_ECCEN_Pos) /*!< 0x00000040 */
+#define FSMC_PCRx_ECCEN FSMC_PCRx_ECCEN_Msk /*!< ECC computation logic enable bit */
+
+#define FSMC_PCRx_TCLR_Pos (9U)
+#define FSMC_PCRx_TCLR_Msk (0xFU << FSMC_PCRx_TCLR_Pos) /*!< 0x00001E00 */
+#define FSMC_PCRx_TCLR FSMC_PCRx_TCLR_Msk /*!< TCLR[3:0] bits (CLE to RE delay) */
+#define FSMC_PCRx_TCLR_0 (0x1U << FSMC_PCRx_TCLR_Pos) /*!< 0x00000200 */
+#define FSMC_PCRx_TCLR_1 (0x2U << FSMC_PCRx_TCLR_Pos) /*!< 0x00000400 */
+#define FSMC_PCRx_TCLR_2 (0x4U << FSMC_PCRx_TCLR_Pos) /*!< 0x00000800 */
+#define FSMC_PCRx_TCLR_3 (0x8U << FSMC_PCRx_TCLR_Pos) /*!< 0x00001000 */
+
+#define FSMC_PCRx_TAR_Pos (13U)
+#define FSMC_PCRx_TAR_Msk (0xFU << FSMC_PCRx_TAR_Pos) /*!< 0x0001E000 */
+#define FSMC_PCRx_TAR FSMC_PCRx_TAR_Msk /*!< TAR[3:0] bits (ALE to RE delay) */
+#define FSMC_PCRx_TAR_0 (0x1U << FSMC_PCRx_TAR_Pos) /*!< 0x00002000 */
+#define FSMC_PCRx_TAR_1 (0x2U << FSMC_PCRx_TAR_Pos) /*!< 0x00004000 */
+#define FSMC_PCRx_TAR_2 (0x4U << FSMC_PCRx_TAR_Pos) /*!< 0x00008000 */
+#define FSMC_PCRx_TAR_3 (0x8U << FSMC_PCRx_TAR_Pos) /*!< 0x00010000 */
+
+#define FSMC_PCRx_ECCPS_Pos (17U)
+#define FSMC_PCRx_ECCPS_Msk (0x7U << FSMC_PCRx_ECCPS_Pos) /*!< 0x000E0000 */
+#define FSMC_PCRx_ECCPS FSMC_PCRx_ECCPS_Msk /*!< ECCPS[1:0] bits (ECC page size) */
+#define FSMC_PCRx_ECCPS_0 (0x1U << FSMC_PCRx_ECCPS_Pos) /*!< 0x00020000 */
+#define FSMC_PCRx_ECCPS_1 (0x2U << FSMC_PCRx_ECCPS_Pos) /*!< 0x00040000 */
+#define FSMC_PCRx_ECCPS_2 (0x4U << FSMC_PCRx_ECCPS_Pos) /*!< 0x00080000 */
+
+/******************* Bit definition for FSMC_SRx (x = 2 to 4) register *******************/
+#define FSMC_SRx_IRS_Pos (0U)
+#define FSMC_SRx_IRS_Msk (0x1U << FSMC_SRx_IRS_Pos) /*!< 0x00000001 */
+#define FSMC_SRx_IRS FSMC_SRx_IRS_Msk /*!< Interrupt Rising Edge status */
+#define FSMC_SRx_ILS_Pos (1U)
+#define FSMC_SRx_ILS_Msk (0x1U << FSMC_SRx_ILS_Pos) /*!< 0x00000002 */
+#define FSMC_SRx_ILS FSMC_SRx_ILS_Msk /*!< Interrupt Level status */
+#define FSMC_SRx_IFS_Pos (2U)
+#define FSMC_SRx_IFS_Msk (0x1U << FSMC_SRx_IFS_Pos) /*!< 0x00000004 */
+#define FSMC_SRx_IFS FSMC_SRx_IFS_Msk /*!< Interrupt Falling Edge status */
+#define FSMC_SRx_IREN_Pos (3U)
+#define FSMC_SRx_IREN_Msk (0x1U << FSMC_SRx_IREN_Pos) /*!< 0x00000008 */
+#define FSMC_SRx_IREN FSMC_SRx_IREN_Msk /*!< Interrupt Rising Edge detection Enable bit */
+#define FSMC_SRx_ILEN_Pos (4U)
+#define FSMC_SRx_ILEN_Msk (0x1U << FSMC_SRx_ILEN_Pos) /*!< 0x00000010 */
+#define FSMC_SRx_ILEN FSMC_SRx_ILEN_Msk /*!< Interrupt Level detection Enable bit */
+#define FSMC_SRx_IFEN_Pos (5U)
+#define FSMC_SRx_IFEN_Msk (0x1U << FSMC_SRx_IFEN_Pos) /*!< 0x00000020 */
+#define FSMC_SRx_IFEN FSMC_SRx_IFEN_Msk /*!< Interrupt Falling Edge detection Enable bit */
+#define FSMC_SRx_FEMPT_Pos (6U)
+#define FSMC_SRx_FEMPT_Msk (0x1U << FSMC_SRx_FEMPT_Pos) /*!< 0x00000040 */
+#define FSMC_SRx_FEMPT FSMC_SRx_FEMPT_Msk /*!< FIFO empty */
+
+/****************** Bit definition for FSMC_PMEMx (x = 2 to 4) register ******************/
+#define FSMC_PMEMx_MEMSETx_Pos (0U)
+#define FSMC_PMEMx_MEMSETx_Msk (0xFFU << FSMC_PMEMx_MEMSETx_Pos) /*!< 0x000000FF */
+#define FSMC_PMEMx_MEMSETx FSMC_PMEMx_MEMSETx_Msk /*!< MEMSETx[7:0] bits (Common memory x setup time) */
+#define FSMC_PMEMx_MEMSETx_0 (0x01U << FSMC_PMEMx_MEMSETx_Pos) /*!< 0x00000001 */
+#define FSMC_PMEMx_MEMSETx_1 (0x02U << FSMC_PMEMx_MEMSETx_Pos) /*!< 0x00000002 */
+#define FSMC_PMEMx_MEMSETx_2 (0x04U << FSMC_PMEMx_MEMSETx_Pos) /*!< 0x00000004 */
+#define FSMC_PMEMx_MEMSETx_3 (0x08U << FSMC_PMEMx_MEMSETx_Pos) /*!< 0x00000008 */
+#define FSMC_PMEMx_MEMSETx_4 (0x10U << FSMC_PMEMx_MEMSETx_Pos) /*!< 0x00000010 */
+#define FSMC_PMEMx_MEMSETx_5 (0x20U << FSMC_PMEMx_MEMSETx_Pos) /*!< 0x00000020 */
+#define FSMC_PMEMx_MEMSETx_6 (0x40U << FSMC_PMEMx_MEMSETx_Pos) /*!< 0x00000040 */
+#define FSMC_PMEMx_MEMSETx_7 (0x80U << FSMC_PMEMx_MEMSETx_Pos) /*!< 0x00000080 */
+
+#define FSMC_PMEMx_MEMWAITx_Pos (8U)
+#define FSMC_PMEMx_MEMWAITx_Msk (0xFFU << FSMC_PMEMx_MEMWAITx_Pos) /*!< 0x0000FF00 */
+#define FSMC_PMEMx_MEMWAITx FSMC_PMEMx_MEMWAITx_Msk /*!< MEMWAITx[7:0] bits (Common memory x wait time) */
+#define FSMC_PMEMx_MEMWAIT2_0 ((uint32_t)0x00000100) /*!< Bit 0 */
+#define FSMC_PMEMx_MEMWAITx_1 ((uint32_t)0x00000200) /*!< Bit 1 */
+#define FSMC_PMEMx_MEMWAITx_2 ((uint32_t)0x00000400) /*!< Bit 2 */
+#define FSMC_PMEMx_MEMWAITx_3 ((uint32_t)0x00000800) /*!< Bit 3 */
+#define FSMC_PMEMx_MEMWAITx_4 ((uint32_t)0x00001000) /*!< Bit 4 */
+#define FSMC_PMEMx_MEMWAITx_5 ((uint32_t)0x00002000) /*!< Bit 5 */
+#define FSMC_PMEMx_MEMWAITx_6 ((uint32_t)0x00004000) /*!< Bit 6 */
+#define FSMC_PMEMx_MEMWAITx_7 ((uint32_t)0x00008000) /*!< Bit 7 */
+
+#define FSMC_PMEMx_MEMHOLDx_Pos (16U)
+#define FSMC_PMEMx_MEMHOLDx_Msk (0xFFU << FSMC_PMEMx_MEMHOLDx_Pos) /*!< 0x00FF0000 */
+#define FSMC_PMEMx_MEMHOLDx FSMC_PMEMx_MEMHOLDx_Msk /*!< MEMHOLDx[7:0] bits (Common memory x hold time) */
+#define FSMC_PMEMx_MEMHOLDx_0 (0x01U << FSMC_PMEMx_MEMHOLDx_Pos) /*!< 0x00010000 */
+#define FSMC_PMEMx_MEMHOLDx_1 (0x02U << FSMC_PMEMx_MEMHOLDx_Pos) /*!< 0x00020000 */
+#define FSMC_PMEMx_MEMHOLDx_2 (0x04U << FSMC_PMEMx_MEMHOLDx_Pos) /*!< 0x00040000 */
+#define FSMC_PMEMx_MEMHOLDx_3 (0x08U << FSMC_PMEMx_MEMHOLDx_Pos) /*!< 0x00080000 */
+#define FSMC_PMEMx_MEMHOLDx_4 (0x10U << FSMC_PMEMx_MEMHOLDx_Pos) /*!< 0x00100000 */
+#define FSMC_PMEMx_MEMHOLDx_5 (0x20U << FSMC_PMEMx_MEMHOLDx_Pos) /*!< 0x00200000 */
+#define FSMC_PMEMx_MEMHOLDx_6 (0x40U << FSMC_PMEMx_MEMHOLDx_Pos) /*!< 0x00400000 */
+#define FSMC_PMEMx_MEMHOLDx_7 (0x80U << FSMC_PMEMx_MEMHOLDx_Pos) /*!< 0x00800000 */
+
+#define FSMC_PMEMx_MEMHIZx_Pos (24U)
+#define FSMC_PMEMx_MEMHIZx_Msk (0xFFU << FSMC_PMEMx_MEMHIZx_Pos) /*!< 0xFF000000 */
+#define FSMC_PMEMx_MEMHIZx FSMC_PMEMx_MEMHIZx_Msk /*!< MEMHIZx[7:0] bits (Common memory x databus HiZ time) */
+#define FSMC_PMEMx_MEMHIZx_0 (0x01U << FSMC_PMEMx_MEMHIZx_Pos) /*!< 0x01000000 */
+#define FSMC_PMEMx_MEMHIZx_1 (0x02U << FSMC_PMEMx_MEMHIZx_Pos) /*!< 0x02000000 */
+#define FSMC_PMEMx_MEMHIZx_2 (0x04U << FSMC_PMEMx_MEMHIZx_Pos) /*!< 0x04000000 */
+#define FSMC_PMEMx_MEMHIZx_3 (0x08U << FSMC_PMEMx_MEMHIZx_Pos) /*!< 0x08000000 */
+#define FSMC_PMEMx_MEMHIZx_4 (0x10U << FSMC_PMEMx_MEMHIZx_Pos) /*!< 0x10000000 */
+#define FSMC_PMEMx_MEMHIZx_5 (0x20U << FSMC_PMEMx_MEMHIZx_Pos) /*!< 0x20000000 */
+#define FSMC_PMEMx_MEMHIZx_6 (0x40U << FSMC_PMEMx_MEMHIZx_Pos) /*!< 0x40000000 */
+#define FSMC_PMEMx_MEMHIZx_7 (0x80U << FSMC_PMEMx_MEMHIZx_Pos) /*!< 0x80000000 */
+
+/****************** Bit definition for FSMC_PATTx (x = 2 to 4) register ******************/
+#define FSMC_PATTx_ATTSETx_Pos (0U)
+#define FSMC_PATTx_ATTSETx_Msk (0xFFU << FSMC_PATTx_ATTSETx_Pos) /*!< 0x000000FF */
+#define FSMC_PATTx_ATTSETx FSMC_PATTx_ATTSETx_Msk /*!< ATTSETx[7:0] bits (Attribute memory x setup time) */
+#define FSMC_PATTx_ATTSETx_0 (0x01U << FSMC_PATTx_ATTSETx_Pos) /*!< 0x00000001 */
+#define FSMC_PATTx_ATTSETx_1 (0x02U << FSMC_PATTx_ATTSETx_Pos) /*!< 0x00000002 */
+#define FSMC_PATTx_ATTSETx_2 (0x04U << FSMC_PATTx_ATTSETx_Pos) /*!< 0x00000004 */
+#define FSMC_PATTx_ATTSETx_3 (0x08U << FSMC_PATTx_ATTSETx_Pos) /*!< 0x00000008 */
+#define FSMC_PATTx_ATTSETx_4 (0x10U << FSMC_PATTx_ATTSETx_Pos) /*!< 0x00000010 */
+#define FSMC_PATTx_ATTSETx_5 (0x20U << FSMC_PATTx_ATTSETx_Pos) /*!< 0x00000020 */
+#define FSMC_PATTx_ATTSETx_6 (0x40U << FSMC_PATTx_ATTSETx_Pos) /*!< 0x00000040 */
+#define FSMC_PATTx_ATTSETx_7 (0x80U << FSMC_PATTx_ATTSETx_Pos) /*!< 0x00000080 */
+
+#define FSMC_PATTx_ATTWAITx_Pos (8U)
+#define FSMC_PATTx_ATTWAITx_Msk (0xFFU << FSMC_PATTx_ATTWAITx_Pos) /*!< 0x0000FF00 */
+#define FSMC_PATTx_ATTWAITx FSMC_PATTx_ATTWAITx_Msk /*!< ATTWAITx[7:0] bits (Attribute memory x wait time) */
+#define FSMC_PATTx_ATTWAITx_0 (0x01U << FSMC_PATTx_ATTWAITx_Pos) /*!< 0x00000100 */
+#define FSMC_PATTx_ATTWAITx_1 (0x02U << FSMC_PATTx_ATTWAITx_Pos) /*!< 0x00000200 */
+#define FSMC_PATTx_ATTWAITx_2 (0x04U << FSMC_PATTx_ATTWAITx_Pos) /*!< 0x00000400 */
+#define FSMC_PATTx_ATTWAITx_3 (0x08U << FSMC_PATTx_ATTWAITx_Pos) /*!< 0x00000800 */
+#define FSMC_PATTx_ATTWAITx_4 (0x10U << FSMC_PATTx_ATTWAITx_Pos) /*!< 0x00001000 */
+#define FSMC_PATTx_ATTWAITx_5 (0x20U << FSMC_PATTx_ATTWAITx_Pos) /*!< 0x00002000 */
+#define FSMC_PATTx_ATTWAITx_6 (0x40U << FSMC_PATTx_ATTWAITx_Pos) /*!< 0x00004000 */
+#define FSMC_PATTx_ATTWAITx_7 (0x80U << FSMC_PATTx_ATTWAITx_Pos) /*!< 0x00008000 */
+
+#define FSMC_PATTx_ATTHOLDx_Pos (16U)
+#define FSMC_PATTx_ATTHOLDx_Msk (0xFFU << FSMC_PATTx_ATTHOLDx_Pos) /*!< 0x00FF0000 */
+#define FSMC_PATTx_ATTHOLDx FSMC_PATTx_ATTHOLDx_Msk /*!< ATTHOLDx[7:0] bits (Attribute memory x hold time) */
+#define FSMC_PATTx_ATTHOLDx_0 (0x01U << FSMC_PATTx_ATTHOLDx_Pos) /*!< 0x00010000 */
+#define FSMC_PATTx_ATTHOLDx_1 (0x02U << FSMC_PATTx_ATTHOLDx_Pos) /*!< 0x00020000 */
+#define FSMC_PATTx_ATTHOLDx_2 (0x04U << FSMC_PATTx_ATTHOLDx_Pos) /*!< 0x00040000 */
+#define FSMC_PATTx_ATTHOLDx_3 (0x08U << FSMC_PATTx_ATTHOLDx_Pos) /*!< 0x00080000 */
+#define FSMC_PATTx_ATTHOLDx_4 (0x10U << FSMC_PATTx_ATTHOLDx_Pos) /*!< 0x00100000 */
+#define FSMC_PATTx_ATTHOLDx_5 (0x20U << FSMC_PATTx_ATTHOLDx_Pos) /*!< 0x00200000 */
+#define FSMC_PATTx_ATTHOLDx_6 (0x40U << FSMC_PATTx_ATTHOLDx_Pos) /*!< 0x00400000 */
+#define FSMC_PATTx_ATTHOLDx_7 (0x80U << FSMC_PATTx_ATTHOLDx_Pos) /*!< 0x00800000 */
+
+#define FSMC_PATTx_ATTHIZx_Pos (24U)
+#define FSMC_PATTx_ATTHIZx_Msk (0xFFU << FSMC_PATTx_ATTHIZx_Pos) /*!< 0xFF000000 */
+#define FSMC_PATTx_ATTHIZx FSMC_PATTx_ATTHIZx_Msk /*!< ATTHIZx[7:0] bits (Attribute memory x databus HiZ time) */
+#define FSMC_PATTx_ATTHIZx_0 (0x01U << FSMC_PATTx_ATTHIZx_Pos) /*!< 0x01000000 */
+#define FSMC_PATTx_ATTHIZx_1 (0x02U << FSMC_PATTx_ATTHIZx_Pos) /*!< 0x02000000 */
+#define FSMC_PATTx_ATTHIZx_2 (0x04U << FSMC_PATTx_ATTHIZx_Pos) /*!< 0x04000000 */
+#define FSMC_PATTx_ATTHIZx_3 (0x08U << FSMC_PATTx_ATTHIZx_Pos) /*!< 0x08000000 */
+#define FSMC_PATTx_ATTHIZx_4 (0x10U << FSMC_PATTx_ATTHIZx_Pos) /*!< 0x10000000 */
+#define FSMC_PATTx_ATTHIZx_5 (0x20U << FSMC_PATTx_ATTHIZx_Pos) /*!< 0x20000000 */
+#define FSMC_PATTx_ATTHIZx_6 (0x40U << FSMC_PATTx_ATTHIZx_Pos) /*!< 0x40000000 */
+#define FSMC_PATTx_ATTHIZx_7 (0x80U << FSMC_PATTx_ATTHIZx_Pos) /*!< 0x80000000 */
+
+/****************** Bit definition for FSMC_PIO4 register *******************/
+#define FSMC_PIO4_IOSET4_Pos (0U)
+#define FSMC_PIO4_IOSET4_Msk (0xFFU << FSMC_PIO4_IOSET4_Pos) /*!< 0x000000FF */
+#define FSMC_PIO4_IOSET4 FSMC_PIO4_IOSET4_Msk /*!< IOSET4[7:0] bits (I/O 4 setup time) */
+#define FSMC_PIO4_IOSET4_0 (0x01U << FSMC_PIO4_IOSET4_Pos) /*!< 0x00000001 */
+#define FSMC_PIO4_IOSET4_1 (0x02U << FSMC_PIO4_IOSET4_Pos) /*!< 0x00000002 */
+#define FSMC_PIO4_IOSET4_2 (0x04U << FSMC_PIO4_IOSET4_Pos) /*!< 0x00000004 */
+#define FSMC_PIO4_IOSET4_3 (0x08U << FSMC_PIO4_IOSET4_Pos) /*!< 0x00000008 */
+#define FSMC_PIO4_IOSET4_4 (0x10U << FSMC_PIO4_IOSET4_Pos) /*!< 0x00000010 */
+#define FSMC_PIO4_IOSET4_5 (0x20U << FSMC_PIO4_IOSET4_Pos) /*!< 0x00000020 */
+#define FSMC_PIO4_IOSET4_6 (0x40U << FSMC_PIO4_IOSET4_Pos) /*!< 0x00000040 */
+#define FSMC_PIO4_IOSET4_7 (0x80U << FSMC_PIO4_IOSET4_Pos) /*!< 0x00000080 */
+
+#define FSMC_PIO4_IOWAIT4_Pos (8U)
+#define FSMC_PIO4_IOWAIT4_Msk (0xFFU << FSMC_PIO4_IOWAIT4_Pos) /*!< 0x0000FF00 */
+#define FSMC_PIO4_IOWAIT4 FSMC_PIO4_IOWAIT4_Msk /*!< IOWAIT4[7:0] bits (I/O 4 wait time) */
+#define FSMC_PIO4_IOWAIT4_0 (0x01U << FSMC_PIO4_IOWAIT4_Pos) /*!< 0x00000100 */
+#define FSMC_PIO4_IOWAIT4_1 (0x02U << FSMC_PIO4_IOWAIT4_Pos) /*!< 0x00000200 */
+#define FSMC_PIO4_IOWAIT4_2 (0x04U << FSMC_PIO4_IOWAIT4_Pos) /*!< 0x00000400 */
+#define FSMC_PIO4_IOWAIT4_3 (0x08U << FSMC_PIO4_IOWAIT4_Pos) /*!< 0x00000800 */
+#define FSMC_PIO4_IOWAIT4_4 (0x10U << FSMC_PIO4_IOWAIT4_Pos) /*!< 0x00001000 */
+#define FSMC_PIO4_IOWAIT4_5 (0x20U << FSMC_PIO4_IOWAIT4_Pos) /*!< 0x00002000 */
+#define FSMC_PIO4_IOWAIT4_6 (0x40U << FSMC_PIO4_IOWAIT4_Pos) /*!< 0x00004000 */
+#define FSMC_PIO4_IOWAIT4_7 (0x80U << FSMC_PIO4_IOWAIT4_Pos) /*!< 0x00008000 */
+
+#define FSMC_PIO4_IOHOLD4_Pos (16U)
+#define FSMC_PIO4_IOHOLD4_Msk (0xFFU << FSMC_PIO4_IOHOLD4_Pos) /*!< 0x00FF0000 */
+#define FSMC_PIO4_IOHOLD4 FSMC_PIO4_IOHOLD4_Msk /*!< IOHOLD4[7:0] bits (I/O 4 hold time) */
+#define FSMC_PIO4_IOHOLD4_0 (0x01U << FSMC_PIO4_IOHOLD4_Pos) /*!< 0x00010000 */
+#define FSMC_PIO4_IOHOLD4_1 (0x02U << FSMC_PIO4_IOHOLD4_Pos) /*!< 0x00020000 */
+#define FSMC_PIO4_IOHOLD4_2 (0x04U << FSMC_PIO4_IOHOLD4_Pos) /*!< 0x00040000 */
+#define FSMC_PIO4_IOHOLD4_3 (0x08U << FSMC_PIO4_IOHOLD4_Pos) /*!< 0x00080000 */
+#define FSMC_PIO4_IOHOLD4_4 (0x10U << FSMC_PIO4_IOHOLD4_Pos) /*!< 0x00100000 */
+#define FSMC_PIO4_IOHOLD4_5 (0x20U << FSMC_PIO4_IOHOLD4_Pos) /*!< 0x00200000 */
+#define FSMC_PIO4_IOHOLD4_6 (0x40U << FSMC_PIO4_IOHOLD4_Pos) /*!< 0x00400000 */
+#define FSMC_PIO4_IOHOLD4_7 (0x80U << FSMC_PIO4_IOHOLD4_Pos) /*!< 0x00800000 */
+
+#define FSMC_PIO4_IOHIZ4_Pos (24U)
+#define FSMC_PIO4_IOHIZ4_Msk (0xFFU << FSMC_PIO4_IOHIZ4_Pos) /*!< 0xFF000000 */
+#define FSMC_PIO4_IOHIZ4 FSMC_PIO4_IOHIZ4_Msk /*!< IOHIZ4[7:0] bits (I/O 4 databus HiZ time) */
+#define FSMC_PIO4_IOHIZ4_0 (0x01U << FSMC_PIO4_IOHIZ4_Pos) /*!< 0x01000000 */
+#define FSMC_PIO4_IOHIZ4_1 (0x02U << FSMC_PIO4_IOHIZ4_Pos) /*!< 0x02000000 */
+#define FSMC_PIO4_IOHIZ4_2 (0x04U << FSMC_PIO4_IOHIZ4_Pos) /*!< 0x04000000 */
+#define FSMC_PIO4_IOHIZ4_3 (0x08U << FSMC_PIO4_IOHIZ4_Pos) /*!< 0x08000000 */
+#define FSMC_PIO4_IOHIZ4_4 (0x10U << FSMC_PIO4_IOHIZ4_Pos) /*!< 0x10000000 */
+#define FSMC_PIO4_IOHIZ4_5 (0x20U << FSMC_PIO4_IOHIZ4_Pos) /*!< 0x20000000 */
+#define FSMC_PIO4_IOHIZ4_6 (0x40U << FSMC_PIO4_IOHIZ4_Pos) /*!< 0x40000000 */
+#define FSMC_PIO4_IOHIZ4_7 (0x80U << FSMC_PIO4_IOHIZ4_Pos) /*!< 0x80000000 */
+
+/****************** Bit definition for FSMC_ECCR2 register ******************/
+#define FSMC_ECCR2_ECC2_Pos (0U)
+#define FSMC_ECCR2_ECC2_Msk (0xFFFFFFFFU << FSMC_ECCR2_ECC2_Pos) /*!< 0xFFFFFFFF */
+#define FSMC_ECCR2_ECC2 FSMC_ECCR2_ECC2_Msk /*!< ECC result */
+
+/****************** Bit definition for FSMC_ECCR3 register ******************/
+#define FSMC_ECCR3_ECC3_Pos (0U)
+#define FSMC_ECCR3_ECC3_Msk (0xFFFFFFFFU << FSMC_ECCR3_ECC3_Pos) /*!< 0xFFFFFFFF */
+#define FSMC_ECCR3_ECC3 FSMC_ECCR3_ECC3_Msk /*!< ECC result */
+
+/******************************************************************************/
+/* */
+/* SD host Interface */
+/* */
+/******************************************************************************/
+
+/****************** Bit definition for SDIO_POWER register ******************/
+#define SDIO_POWER_PWRCTRL_Pos (0U)
+#define SDIO_POWER_PWRCTRL_Msk (0x3U << SDIO_POWER_PWRCTRL_Pos) /*!< 0x00000003 */
+#define SDIO_POWER_PWRCTRL SDIO_POWER_PWRCTRL_Msk /*!< PWRCTRL[1:0] bits (Power supply control bits) */
+#define SDIO_POWER_PWRCTRL_0 (0x1U << SDIO_POWER_PWRCTRL_Pos) /*!< 0x01 */
+#define SDIO_POWER_PWRCTRL_1 (0x2U << SDIO_POWER_PWRCTRL_Pos) /*!< 0x02 */
+
+/****************** Bit definition for SDIO_CLKCR register ******************/
+#define SDIO_CLKCR_CLKDIV_Pos (0U)
+#define SDIO_CLKCR_CLKDIV_Msk (0xFFU << SDIO_CLKCR_CLKDIV_Pos) /*!< 0x000000FF */
+#define SDIO_CLKCR_CLKDIV SDIO_CLKCR_CLKDIV_Msk /*!< Clock divide factor */
+#define SDIO_CLKCR_CLKEN_Pos (8U)
+#define SDIO_CLKCR_CLKEN_Msk (0x1U << SDIO_CLKCR_CLKEN_Pos) /*!< 0x00000100 */
+#define SDIO_CLKCR_CLKEN SDIO_CLKCR_CLKEN_Msk /*!< Clock enable bit */
+#define SDIO_CLKCR_PWRSAV_Pos (9U)
+#define SDIO_CLKCR_PWRSAV_Msk (0x1U << SDIO_CLKCR_PWRSAV_Pos) /*!< 0x00000200 */
+#define SDIO_CLKCR_PWRSAV SDIO_CLKCR_PWRSAV_Msk /*!< Power saving configuration bit */
+#define SDIO_CLKCR_BYPASS_Pos (10U)
+#define SDIO_CLKCR_BYPASS_Msk (0x1U << SDIO_CLKCR_BYPASS_Pos) /*!< 0x00000400 */
+#define SDIO_CLKCR_BYPASS SDIO_CLKCR_BYPASS_Msk /*!< Clock divider bypass enable bit */
+
+#define SDIO_CLKCR_WIDBUS_Pos (11U)
+#define SDIO_CLKCR_WIDBUS_Msk (0x3U << SDIO_CLKCR_WIDBUS_Pos) /*!< 0x00001800 */
+#define SDIO_CLKCR_WIDBUS SDIO_CLKCR_WIDBUS_Msk /*!< WIDBUS[1:0] bits (Wide bus mode enable bit) */
+#define SDIO_CLKCR_WIDBUS_0 (0x1U << SDIO_CLKCR_WIDBUS_Pos) /*!< 0x0800 */
+#define SDIO_CLKCR_WIDBUS_1 (0x2U << SDIO_CLKCR_WIDBUS_Pos) /*!< 0x1000 */
+
+#define SDIO_CLKCR_NEGEDGE_Pos (13U)
+#define SDIO_CLKCR_NEGEDGE_Msk (0x1U << SDIO_CLKCR_NEGEDGE_Pos) /*!< 0x00002000 */
+#define SDIO_CLKCR_NEGEDGE SDIO_CLKCR_NEGEDGE_Msk /*!< SDIO_CK dephasing selection bit */
+#define SDIO_CLKCR_HWFC_EN_Pos (14U)
+#define SDIO_CLKCR_HWFC_EN_Msk (0x1U << SDIO_CLKCR_HWFC_EN_Pos) /*!< 0x00004000 */
+#define SDIO_CLKCR_HWFC_EN SDIO_CLKCR_HWFC_EN_Msk /*!< HW Flow Control enable */
+
+/******************* Bit definition for SDIO_ARG register *******************/
+#define SDIO_ARG_CMDARG_Pos (0U)
+#define SDIO_ARG_CMDARG_Msk (0xFFFFFFFFU << SDIO_ARG_CMDARG_Pos) /*!< 0xFFFFFFFF */
+#define SDIO_ARG_CMDARG SDIO_ARG_CMDARG_Msk /*!< Command argument */
+
+/******************* Bit definition for SDIO_CMD register *******************/
+#define SDIO_CMD_CMDINDEX_Pos (0U)
+#define SDIO_CMD_CMDINDEX_Msk (0x3FU << SDIO_CMD_CMDINDEX_Pos) /*!< 0x0000003F */
+#define SDIO_CMD_CMDINDEX SDIO_CMD_CMDINDEX_Msk /*!< Command Index */
+
+#define SDIO_CMD_WAITRESP_Pos (6U)
+#define SDIO_CMD_WAITRESP_Msk (0x3U << SDIO_CMD_WAITRESP_Pos) /*!< 0x000000C0 */
+#define SDIO_CMD_WAITRESP SDIO_CMD_WAITRESP_Msk /*!< WAITRESP[1:0] bits (Wait for response bits) */
+#define SDIO_CMD_WAITRESP_0 (0x1U << SDIO_CMD_WAITRESP_Pos) /*!< 0x0040 */
+#define SDIO_CMD_WAITRESP_1 (0x2U << SDIO_CMD_WAITRESP_Pos) /*!< 0x0080 */
+
+#define SDIO_CMD_WAITINT_Pos (8U)
+#define SDIO_CMD_WAITINT_Msk (0x1U << SDIO_CMD_WAITINT_Pos) /*!< 0x00000100 */
+#define SDIO_CMD_WAITINT SDIO_CMD_WAITINT_Msk /*!< CPSM Waits for Interrupt Request */
+#define SDIO_CMD_WAITPEND_Pos (9U)
+#define SDIO_CMD_WAITPEND_Msk (0x1U << SDIO_CMD_WAITPEND_Pos) /*!< 0x00000200 */
+#define SDIO_CMD_WAITPEND SDIO_CMD_WAITPEND_Msk /*!< CPSM Waits for ends of data transfer (CmdPend internal signal) */
+#define SDIO_CMD_CPSMEN_Pos (10U)
+#define SDIO_CMD_CPSMEN_Msk (0x1U << SDIO_CMD_CPSMEN_Pos) /*!< 0x00000400 */
+#define SDIO_CMD_CPSMEN SDIO_CMD_CPSMEN_Msk /*!< Command path state machine (CPSM) Enable bit */
+#define SDIO_CMD_SDIOSUSPEND_Pos (11U)
+#define SDIO_CMD_SDIOSUSPEND_Msk (0x1U << SDIO_CMD_SDIOSUSPEND_Pos) /*!< 0x00000800 */
+#define SDIO_CMD_SDIOSUSPEND SDIO_CMD_SDIOSUSPEND_Msk /*!< SD I/O suspend command */
+#define SDIO_CMD_ENCMDCOMPL_Pos (12U)
+#define SDIO_CMD_ENCMDCOMPL_Msk (0x1U << SDIO_CMD_ENCMDCOMPL_Pos) /*!< 0x00001000 */
+#define SDIO_CMD_ENCMDCOMPL SDIO_CMD_ENCMDCOMPL_Msk /*!< Enable CMD completion */
+#define SDIO_CMD_NIEN_Pos (13U)
+#define SDIO_CMD_NIEN_Msk (0x1U << SDIO_CMD_NIEN_Pos) /*!< 0x00002000 */
+#define SDIO_CMD_NIEN SDIO_CMD_NIEN_Msk /*!< Not Interrupt Enable */
+#define SDIO_CMD_CEATACMD_Pos (14U)
+#define SDIO_CMD_CEATACMD_Msk (0x1U << SDIO_CMD_CEATACMD_Pos) /*!< 0x00004000 */
+#define SDIO_CMD_CEATACMD SDIO_CMD_CEATACMD_Msk /*!< CE-ATA command */
+
+/***************** Bit definition for SDIO_RESPCMD register *****************/
+#define SDIO_RESPCMD_RESPCMD_Pos (0U)
+#define SDIO_RESPCMD_RESPCMD_Msk (0x3FU << SDIO_RESPCMD_RESPCMD_Pos) /*!< 0x0000003F */
+#define SDIO_RESPCMD_RESPCMD SDIO_RESPCMD_RESPCMD_Msk /*!< Response command index */
+
+/****************** Bit definition for SDIO_RESP0 register ******************/
+#define SDIO_RESP0_CARDSTATUS0_Pos (0U)
+#define SDIO_RESP0_CARDSTATUS0_Msk (0xFFFFFFFFU << SDIO_RESP0_CARDSTATUS0_Pos) /*!< 0xFFFFFFFF */
+#define SDIO_RESP0_CARDSTATUS0 SDIO_RESP0_CARDSTATUS0_Msk /*!< Card Status */
+
+/****************** Bit definition for SDIO_RESP1 register ******************/
+#define SDIO_RESP1_CARDSTATUS1_Pos (0U)
+#define SDIO_RESP1_CARDSTATUS1_Msk (0xFFFFFFFFU << SDIO_RESP1_CARDSTATUS1_Pos) /*!< 0xFFFFFFFF */
+#define SDIO_RESP1_CARDSTATUS1 SDIO_RESP1_CARDSTATUS1_Msk /*!< Card Status */
+
+/****************** Bit definition for SDIO_RESP2 register ******************/
+#define SDIO_RESP2_CARDSTATUS2_Pos (0U)
+#define SDIO_RESP2_CARDSTATUS2_Msk (0xFFFFFFFFU << SDIO_RESP2_CARDSTATUS2_Pos) /*!< 0xFFFFFFFF */
+#define SDIO_RESP2_CARDSTATUS2 SDIO_RESP2_CARDSTATUS2_Msk /*!< Card Status */
+
+/****************** Bit definition for SDIO_RESP3 register ******************/
+#define SDIO_RESP3_CARDSTATUS3_Pos (0U)
+#define SDIO_RESP3_CARDSTATUS3_Msk (0xFFFFFFFFU << SDIO_RESP3_CARDSTATUS3_Pos) /*!< 0xFFFFFFFF */
+#define SDIO_RESP3_CARDSTATUS3 SDIO_RESP3_CARDSTATUS3_Msk /*!< Card Status */
+
+/****************** Bit definition for SDIO_RESP4 register ******************/
+#define SDIO_RESP4_CARDSTATUS4_Pos (0U)
+#define SDIO_RESP4_CARDSTATUS4_Msk (0xFFFFFFFFU << SDIO_RESP4_CARDSTATUS4_Pos) /*!< 0xFFFFFFFF */
+#define SDIO_RESP4_CARDSTATUS4 SDIO_RESP4_CARDSTATUS4_Msk /*!< Card Status */
+
+/****************** Bit definition for SDIO_DTIMER register *****************/
+#define SDIO_DTIMER_DATATIME_Pos (0U)
+#define SDIO_DTIMER_DATATIME_Msk (0xFFFFFFFFU << SDIO_DTIMER_DATATIME_Pos) /*!< 0xFFFFFFFF */
+#define SDIO_DTIMER_DATATIME SDIO_DTIMER_DATATIME_Msk /*!< Data timeout period. */
+
+/****************** Bit definition for SDIO_DLEN register *******************/
+#define SDIO_DLEN_DATALENGTH_Pos (0U)
+#define SDIO_DLEN_DATALENGTH_Msk (0x1FFFFFFU << SDIO_DLEN_DATALENGTH_Pos) /*!< 0x01FFFFFF */
+#define SDIO_DLEN_DATALENGTH SDIO_DLEN_DATALENGTH_Msk /*!< Data length value */
+
+/****************** Bit definition for SDIO_DCTRL register ******************/
+#define SDIO_DCTRL_DTEN_Pos (0U)
+#define SDIO_DCTRL_DTEN_Msk (0x1U << SDIO_DCTRL_DTEN_Pos) /*!< 0x00000001 */
+#define SDIO_DCTRL_DTEN SDIO_DCTRL_DTEN_Msk /*!< Data transfer enabled bit */
+#define SDIO_DCTRL_DTDIR_Pos (1U)
+#define SDIO_DCTRL_DTDIR_Msk (0x1U << SDIO_DCTRL_DTDIR_Pos) /*!< 0x00000002 */
+#define SDIO_DCTRL_DTDIR SDIO_DCTRL_DTDIR_Msk /*!< Data transfer direction selection */
+#define SDIO_DCTRL_DTMODE_Pos (2U)
+#define SDIO_DCTRL_DTMODE_Msk (0x1U << SDIO_DCTRL_DTMODE_Pos) /*!< 0x00000004 */
+#define SDIO_DCTRL_DTMODE SDIO_DCTRL_DTMODE_Msk /*!< Data transfer mode selection */
+#define SDIO_DCTRL_DMAEN_Pos (3U)
+#define SDIO_DCTRL_DMAEN_Msk (0x1U << SDIO_DCTRL_DMAEN_Pos) /*!< 0x00000008 */
+#define SDIO_DCTRL_DMAEN SDIO_DCTRL_DMAEN_Msk /*!< DMA enabled bit */
+
+#define SDIO_DCTRL_DBLOCKSIZE_Pos (4U)
+#define SDIO_DCTRL_DBLOCKSIZE_Msk (0xFU << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x000000F0 */
+#define SDIO_DCTRL_DBLOCKSIZE SDIO_DCTRL_DBLOCKSIZE_Msk /*!< DBLOCKSIZE[3:0] bits (Data block size) */
+#define SDIO_DCTRL_DBLOCKSIZE_0 (0x1U << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0010 */
+#define SDIO_DCTRL_DBLOCKSIZE_1 (0x2U << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0020 */
+#define SDIO_DCTRL_DBLOCKSIZE_2 (0x4U << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0040 */
+#define SDIO_DCTRL_DBLOCKSIZE_3 (0x8U << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0080 */
+
+#define SDIO_DCTRL_RWSTART_Pos (8U)
+#define SDIO_DCTRL_RWSTART_Msk (0x1U << SDIO_DCTRL_RWSTART_Pos) /*!< 0x00000100 */
+#define SDIO_DCTRL_RWSTART SDIO_DCTRL_RWSTART_Msk /*!< Read wait start */
+#define SDIO_DCTRL_RWSTOP_Pos (9U)
+#define SDIO_DCTRL_RWSTOP_Msk (0x1U << SDIO_DCTRL_RWSTOP_Pos) /*!< 0x00000200 */
+#define SDIO_DCTRL_RWSTOP SDIO_DCTRL_RWSTOP_Msk /*!< Read wait stop */
+#define SDIO_DCTRL_RWMOD_Pos (10U)
+#define SDIO_DCTRL_RWMOD_Msk (0x1U << SDIO_DCTRL_RWMOD_Pos) /*!< 0x00000400 */
+#define SDIO_DCTRL_RWMOD SDIO_DCTRL_RWMOD_Msk /*!< Read wait mode */
+#define SDIO_DCTRL_SDIOEN_Pos (11U)
+#define SDIO_DCTRL_SDIOEN_Msk (0x1U << SDIO_DCTRL_SDIOEN_Pos) /*!< 0x00000800 */
+#define SDIO_DCTRL_SDIOEN SDIO_DCTRL_SDIOEN_Msk /*!< SD I/O enable functions */
+
+/****************** Bit definition for SDIO_DCOUNT register *****************/
+#define SDIO_DCOUNT_DATACOUNT_Pos (0U)
+#define SDIO_DCOUNT_DATACOUNT_Msk (0x1FFFFFFU << SDIO_DCOUNT_DATACOUNT_Pos) /*!< 0x01FFFFFF */
+#define SDIO_DCOUNT_DATACOUNT SDIO_DCOUNT_DATACOUNT_Msk /*!< Data count value */
+
+/****************** Bit definition for SDIO_STA register ********************/
+#define SDIO_STA_CCRCFAIL_Pos (0U)
+#define SDIO_STA_CCRCFAIL_Msk (0x1U << SDIO_STA_CCRCFAIL_Pos) /*!< 0x00000001 */
+#define SDIO_STA_CCRCFAIL SDIO_STA_CCRCFAIL_Msk /*!< Command response received (CRC check failed) */
+#define SDIO_STA_DCRCFAIL_Pos (1U)
+#define SDIO_STA_DCRCFAIL_Msk (0x1U << SDIO_STA_DCRCFAIL_Pos) /*!< 0x00000002 */
+#define SDIO_STA_DCRCFAIL SDIO_STA_DCRCFAIL_Msk /*!< Data block sent/received (CRC check failed) */
+#define SDIO_STA_CTIMEOUT_Pos (2U)
+#define SDIO_STA_CTIMEOUT_Msk (0x1U << SDIO_STA_CTIMEOUT_Pos) /*!< 0x00000004 */
+#define SDIO_STA_CTIMEOUT SDIO_STA_CTIMEOUT_Msk /*!< Command response timeout */
+#define SDIO_STA_DTIMEOUT_Pos (3U)
+#define SDIO_STA_DTIMEOUT_Msk (0x1U << SDIO_STA_DTIMEOUT_Pos) /*!< 0x00000008 */
+#define SDIO_STA_DTIMEOUT SDIO_STA_DTIMEOUT_Msk /*!< Data timeout */
+#define SDIO_STA_TXUNDERR_Pos (4U)
+#define SDIO_STA_TXUNDERR_Msk (0x1U << SDIO_STA_TXUNDERR_Pos) /*!< 0x00000010 */
+#define SDIO_STA_TXUNDERR SDIO_STA_TXUNDERR_Msk /*!< Transmit FIFO underrun error */
+#define SDIO_STA_RXOVERR_Pos (5U)
+#define SDIO_STA_RXOVERR_Msk (0x1U << SDIO_STA_RXOVERR_Pos) /*!< 0x00000020 */
+#define SDIO_STA_RXOVERR SDIO_STA_RXOVERR_Msk /*!< Received FIFO overrun error */
+#define SDIO_STA_CMDREND_Pos (6U)
+#define SDIO_STA_CMDREND_Msk (0x1U << SDIO_STA_CMDREND_Pos) /*!< 0x00000040 */
+#define SDIO_STA_CMDREND SDIO_STA_CMDREND_Msk /*!< Command response received (CRC check passed) */
+#define SDIO_STA_CMDSENT_Pos (7U)
+#define SDIO_STA_CMDSENT_Msk (0x1U << SDIO_STA_CMDSENT_Pos) /*!< 0x00000080 */
+#define SDIO_STA_CMDSENT SDIO_STA_CMDSENT_Msk /*!< Command sent (no response required) */
+#define SDIO_STA_DATAEND_Pos (8U)
+#define SDIO_STA_DATAEND_Msk (0x1U << SDIO_STA_DATAEND_Pos) /*!< 0x00000100 */
+#define SDIO_STA_DATAEND SDIO_STA_DATAEND_Msk /*!< Data end (data counter, SDIDCOUNT, is zero) */
+#define SDIO_STA_STBITERR_Pos (9U)
+#define SDIO_STA_STBITERR_Msk (0x1U << SDIO_STA_STBITERR_Pos) /*!< 0x00000200 */
+#define SDIO_STA_STBITERR SDIO_STA_STBITERR_Msk /*!< Start bit not detected on all data signals in wide bus mode */
+#define SDIO_STA_DBCKEND_Pos (10U)
+#define SDIO_STA_DBCKEND_Msk (0x1U << SDIO_STA_DBCKEND_Pos) /*!< 0x00000400 */
+#define SDIO_STA_DBCKEND SDIO_STA_DBCKEND_Msk /*!< Data block sent/received (CRC check passed) */
+#define SDIO_STA_CMDACT_Pos (11U)
+#define SDIO_STA_CMDACT_Msk (0x1U << SDIO_STA_CMDACT_Pos) /*!< 0x00000800 */
+#define SDIO_STA_CMDACT SDIO_STA_CMDACT_Msk /*!< Command transfer in progress */
+#define SDIO_STA_TXACT_Pos (12U)
+#define SDIO_STA_TXACT_Msk (0x1U << SDIO_STA_TXACT_Pos) /*!< 0x00001000 */
+#define SDIO_STA_TXACT SDIO_STA_TXACT_Msk /*!< Data transmit in progress */
+#define SDIO_STA_RXACT_Pos (13U)
+#define SDIO_STA_RXACT_Msk (0x1U << SDIO_STA_RXACT_Pos) /*!< 0x00002000 */
+#define SDIO_STA_RXACT SDIO_STA_RXACT_Msk /*!< Data receive in progress */
+#define SDIO_STA_TXFIFOHE_Pos (14U)
+#define SDIO_STA_TXFIFOHE_Msk (0x1U << SDIO_STA_TXFIFOHE_Pos) /*!< 0x00004000 */
+#define SDIO_STA_TXFIFOHE SDIO_STA_TXFIFOHE_Msk /*!< Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
+#define SDIO_STA_RXFIFOHF_Pos (15U)
+#define SDIO_STA_RXFIFOHF_Msk (0x1U << SDIO_STA_RXFIFOHF_Pos) /*!< 0x00008000 */
+#define SDIO_STA_RXFIFOHF SDIO_STA_RXFIFOHF_Msk /*!< Receive FIFO Half Full: there are at least 8 words in the FIFO */
+#define SDIO_STA_TXFIFOF_Pos (16U)
+#define SDIO_STA_TXFIFOF_Msk (0x1U << SDIO_STA_TXFIFOF_Pos) /*!< 0x00010000 */
+#define SDIO_STA_TXFIFOF SDIO_STA_TXFIFOF_Msk /*!< Transmit FIFO full */
+#define SDIO_STA_RXFIFOF_Pos (17U)
+#define SDIO_STA_RXFIFOF_Msk (0x1U << SDIO_STA_RXFIFOF_Pos) /*!< 0x00020000 */
+#define SDIO_STA_RXFIFOF SDIO_STA_RXFIFOF_Msk /*!< Receive FIFO full */
+#define SDIO_STA_TXFIFOE_Pos (18U)
+#define SDIO_STA_TXFIFOE_Msk (0x1U << SDIO_STA_TXFIFOE_Pos) /*!< 0x00040000 */
+#define SDIO_STA_TXFIFOE SDIO_STA_TXFIFOE_Msk /*!< Transmit FIFO empty */
+#define SDIO_STA_RXFIFOE_Pos (19U)
+#define SDIO_STA_RXFIFOE_Msk (0x1U << SDIO_STA_RXFIFOE_Pos) /*!< 0x00080000 */
+#define SDIO_STA_RXFIFOE SDIO_STA_RXFIFOE_Msk /*!< Receive FIFO empty */
+#define SDIO_STA_TXDAVL_Pos (20U)
+#define SDIO_STA_TXDAVL_Msk (0x1U << SDIO_STA_TXDAVL_Pos) /*!< 0x00100000 */
+#define SDIO_STA_TXDAVL SDIO_STA_TXDAVL_Msk /*!< Data available in transmit FIFO */
+#define SDIO_STA_RXDAVL_Pos (21U)
+#define SDIO_STA_RXDAVL_Msk (0x1U << SDIO_STA_RXDAVL_Pos) /*!< 0x00200000 */
+#define SDIO_STA_RXDAVL SDIO_STA_RXDAVL_Msk /*!< Data available in receive FIFO */
+#define SDIO_STA_SDIOIT_Pos (22U)
+#define SDIO_STA_SDIOIT_Msk (0x1U << SDIO_STA_SDIOIT_Pos) /*!< 0x00400000 */
+#define SDIO_STA_SDIOIT SDIO_STA_SDIOIT_Msk /*!< SDIO interrupt received */
+#define SDIO_STA_CEATAEND_Pos (23U)
+#define SDIO_STA_CEATAEND_Msk (0x1U << SDIO_STA_CEATAEND_Pos) /*!< 0x00800000 */
+#define SDIO_STA_CEATAEND SDIO_STA_CEATAEND_Msk /*!< CE-ATA command completion signal received for CMD61 */
+
+/******************* Bit definition for SDIO_ICR register *******************/
+#define SDIO_ICR_CCRCFAILC_Pos (0U)
+#define SDIO_ICR_CCRCFAILC_Msk (0x1U << SDIO_ICR_CCRCFAILC_Pos) /*!< 0x00000001 */
+#define SDIO_ICR_CCRCFAILC SDIO_ICR_CCRCFAILC_Msk /*!< CCRCFAIL flag clear bit */
+#define SDIO_ICR_DCRCFAILC_Pos (1U)
+#define SDIO_ICR_DCRCFAILC_Msk (0x1U << SDIO_ICR_DCRCFAILC_Pos) /*!< 0x00000002 */
+#define SDIO_ICR_DCRCFAILC SDIO_ICR_DCRCFAILC_Msk /*!< DCRCFAIL flag clear bit */
+#define SDIO_ICR_CTIMEOUTC_Pos (2U)
+#define SDIO_ICR_CTIMEOUTC_Msk (0x1U << SDIO_ICR_CTIMEOUTC_Pos) /*!< 0x00000004 */
+#define SDIO_ICR_CTIMEOUTC SDIO_ICR_CTIMEOUTC_Msk /*!< CTIMEOUT flag clear bit */
+#define SDIO_ICR_DTIMEOUTC_Pos (3U)
+#define SDIO_ICR_DTIMEOUTC_Msk (0x1U << SDIO_ICR_DTIMEOUTC_Pos) /*!< 0x00000008 */
+#define SDIO_ICR_DTIMEOUTC SDIO_ICR_DTIMEOUTC_Msk /*!< DTIMEOUT flag clear bit */
+#define SDIO_ICR_TXUNDERRC_Pos (4U)
+#define SDIO_ICR_TXUNDERRC_Msk (0x1U << SDIO_ICR_TXUNDERRC_Pos) /*!< 0x00000010 */
+#define SDIO_ICR_TXUNDERRC SDIO_ICR_TXUNDERRC_Msk /*!< TXUNDERR flag clear bit */
+#define SDIO_ICR_RXOVERRC_Pos (5U)
+#define SDIO_ICR_RXOVERRC_Msk (0x1U << SDIO_ICR_RXOVERRC_Pos) /*!< 0x00000020 */
+#define SDIO_ICR_RXOVERRC SDIO_ICR_RXOVERRC_Msk /*!< RXOVERR flag clear bit */
+#define SDIO_ICR_CMDRENDC_Pos (6U)
+#define SDIO_ICR_CMDRENDC_Msk (0x1U << SDIO_ICR_CMDRENDC_Pos) /*!< 0x00000040 */
+#define SDIO_ICR_CMDRENDC SDIO_ICR_CMDRENDC_Msk /*!< CMDREND flag clear bit */
+#define SDIO_ICR_CMDSENTC_Pos (7U)
+#define SDIO_ICR_CMDSENTC_Msk (0x1U << SDIO_ICR_CMDSENTC_Pos) /*!< 0x00000080 */
+#define SDIO_ICR_CMDSENTC SDIO_ICR_CMDSENTC_Msk /*!< CMDSENT flag clear bit */
+#define SDIO_ICR_DATAENDC_Pos (8U)
+#define SDIO_ICR_DATAENDC_Msk (0x1U << SDIO_ICR_DATAENDC_Pos) /*!< 0x00000100 */
+#define SDIO_ICR_DATAENDC SDIO_ICR_DATAENDC_Msk /*!< DATAEND flag clear bit */
+#define SDIO_ICR_STBITERRC_Pos (9U)
+#define SDIO_ICR_STBITERRC_Msk (0x1U << SDIO_ICR_STBITERRC_Pos) /*!< 0x00000200 */
+#define SDIO_ICR_STBITERRC SDIO_ICR_STBITERRC_Msk /*!< STBITERR flag clear bit */
+#define SDIO_ICR_DBCKENDC_Pos (10U)
+#define SDIO_ICR_DBCKENDC_Msk (0x1U << SDIO_ICR_DBCKENDC_Pos) /*!< 0x00000400 */
+#define SDIO_ICR_DBCKENDC SDIO_ICR_DBCKENDC_Msk /*!< DBCKEND flag clear bit */
+#define SDIO_ICR_SDIOITC_Pos (22U)
+#define SDIO_ICR_SDIOITC_Msk (0x1U << SDIO_ICR_SDIOITC_Pos) /*!< 0x00400000 */
+#define SDIO_ICR_SDIOITC SDIO_ICR_SDIOITC_Msk /*!< SDIOIT flag clear bit */
+#define SDIO_ICR_CEATAENDC_Pos (23U)
+#define SDIO_ICR_CEATAENDC_Msk (0x1U << SDIO_ICR_CEATAENDC_Pos) /*!< 0x00800000 */
+#define SDIO_ICR_CEATAENDC SDIO_ICR_CEATAENDC_Msk /*!< CEATAEND flag clear bit */
+
+/****************** Bit definition for SDIO_MASK register *******************/
+#define SDIO_MASK_CCRCFAILIE_Pos (0U)
+#define SDIO_MASK_CCRCFAILIE_Msk (0x1U << SDIO_MASK_CCRCFAILIE_Pos) /*!< 0x00000001 */
+#define SDIO_MASK_CCRCFAILIE SDIO_MASK_CCRCFAILIE_Msk /*!< Command CRC Fail Interrupt Enable */
+#define SDIO_MASK_DCRCFAILIE_Pos (1U)
+#define SDIO_MASK_DCRCFAILIE_Msk (0x1U << SDIO_MASK_DCRCFAILIE_Pos) /*!< 0x00000002 */
+#define SDIO_MASK_DCRCFAILIE SDIO_MASK_DCRCFAILIE_Msk /*!< Data CRC Fail Interrupt Enable */
+#define SDIO_MASK_CTIMEOUTIE_Pos (2U)
+#define SDIO_MASK_CTIMEOUTIE_Msk (0x1U << SDIO_MASK_CTIMEOUTIE_Pos) /*!< 0x00000004 */
+#define SDIO_MASK_CTIMEOUTIE SDIO_MASK_CTIMEOUTIE_Msk /*!< Command TimeOut Interrupt Enable */
+#define SDIO_MASK_DTIMEOUTIE_Pos (3U)
+#define SDIO_MASK_DTIMEOUTIE_Msk (0x1U << SDIO_MASK_DTIMEOUTIE_Pos) /*!< 0x00000008 */
+#define SDIO_MASK_DTIMEOUTIE SDIO_MASK_DTIMEOUTIE_Msk /*!< Data TimeOut Interrupt Enable */
+#define SDIO_MASK_TXUNDERRIE_Pos (4U)
+#define SDIO_MASK_TXUNDERRIE_Msk (0x1U << SDIO_MASK_TXUNDERRIE_Pos) /*!< 0x00000010 */
+#define SDIO_MASK_TXUNDERRIE SDIO_MASK_TXUNDERRIE_Msk /*!< Tx FIFO UnderRun Error Interrupt Enable */
+#define SDIO_MASK_RXOVERRIE_Pos (5U)
+#define SDIO_MASK_RXOVERRIE_Msk (0x1U << SDIO_MASK_RXOVERRIE_Pos) /*!< 0x00000020 */
+#define SDIO_MASK_RXOVERRIE SDIO_MASK_RXOVERRIE_Msk /*!< Rx FIFO OverRun Error Interrupt Enable */
+#define SDIO_MASK_CMDRENDIE_Pos (6U)
+#define SDIO_MASK_CMDRENDIE_Msk (0x1U << SDIO_MASK_CMDRENDIE_Pos) /*!< 0x00000040 */
+#define SDIO_MASK_CMDRENDIE SDIO_MASK_CMDRENDIE_Msk /*!< Command Response Received Interrupt Enable */
+#define SDIO_MASK_CMDSENTIE_Pos (7U)
+#define SDIO_MASK_CMDSENTIE_Msk (0x1U << SDIO_MASK_CMDSENTIE_Pos) /*!< 0x00000080 */
+#define SDIO_MASK_CMDSENTIE SDIO_MASK_CMDSENTIE_Msk /*!< Command Sent Interrupt Enable */
+#define SDIO_MASK_DATAENDIE_Pos (8U)
+#define SDIO_MASK_DATAENDIE_Msk (0x1U << SDIO_MASK_DATAENDIE_Pos) /*!< 0x00000100 */
+#define SDIO_MASK_DATAENDIE SDIO_MASK_DATAENDIE_Msk /*!< Data End Interrupt Enable */
+#define SDIO_MASK_STBITERRIE_Pos (9U)
+#define SDIO_MASK_STBITERRIE_Msk (0x1U << SDIO_MASK_STBITERRIE_Pos) /*!< 0x00000200 */
+#define SDIO_MASK_STBITERRIE SDIO_MASK_STBITERRIE_Msk /*!< Start Bit Error Interrupt Enable */
+#define SDIO_MASK_DBCKENDIE_Pos (10U)
+#define SDIO_MASK_DBCKENDIE_Msk (0x1U << SDIO_MASK_DBCKENDIE_Pos) /*!< 0x00000400 */
+#define SDIO_MASK_DBCKENDIE SDIO_MASK_DBCKENDIE_Msk /*!< Data Block End Interrupt Enable */
+#define SDIO_MASK_CMDACTIE_Pos (11U)
+#define SDIO_MASK_CMDACTIE_Msk (0x1U << SDIO_MASK_CMDACTIE_Pos) /*!< 0x00000800 */
+#define SDIO_MASK_CMDACTIE SDIO_MASK_CMDACTIE_Msk /*!< Command Acting Interrupt Enable */
+#define SDIO_MASK_TXACTIE_Pos (12U)
+#define SDIO_MASK_TXACTIE_Msk (0x1U << SDIO_MASK_TXACTIE_Pos) /*!< 0x00001000 */
+#define SDIO_MASK_TXACTIE SDIO_MASK_TXACTIE_Msk /*!< Data Transmit Acting Interrupt Enable */
+#define SDIO_MASK_RXACTIE_Pos (13U)
+#define SDIO_MASK_RXACTIE_Msk (0x1U << SDIO_MASK_RXACTIE_Pos) /*!< 0x00002000 */
+#define SDIO_MASK_RXACTIE SDIO_MASK_RXACTIE_Msk /*!< Data receive acting interrupt enabled */
+#define SDIO_MASK_TXFIFOHEIE_Pos (14U)
+#define SDIO_MASK_TXFIFOHEIE_Msk (0x1U << SDIO_MASK_TXFIFOHEIE_Pos) /*!< 0x00004000 */
+#define SDIO_MASK_TXFIFOHEIE SDIO_MASK_TXFIFOHEIE_Msk /*!< Tx FIFO Half Empty interrupt Enable */
+#define SDIO_MASK_RXFIFOHFIE_Pos (15U)
+#define SDIO_MASK_RXFIFOHFIE_Msk (0x1U << SDIO_MASK_RXFIFOHFIE_Pos) /*!< 0x00008000 */
+#define SDIO_MASK_RXFIFOHFIE SDIO_MASK_RXFIFOHFIE_Msk /*!< Rx FIFO Half Full interrupt Enable */
+#define SDIO_MASK_TXFIFOFIE_Pos (16U)
+#define SDIO_MASK_TXFIFOFIE_Msk (0x1U << SDIO_MASK_TXFIFOFIE_Pos) /*!< 0x00010000 */
+#define SDIO_MASK_TXFIFOFIE SDIO_MASK_TXFIFOFIE_Msk /*!< Tx FIFO Full interrupt Enable */
+#define SDIO_MASK_RXFIFOFIE_Pos (17U)
+#define SDIO_MASK_RXFIFOFIE_Msk (0x1U << SDIO_MASK_RXFIFOFIE_Pos) /*!< 0x00020000 */
+#define SDIO_MASK_RXFIFOFIE SDIO_MASK_RXFIFOFIE_Msk /*!< Rx FIFO Full interrupt Enable */
+#define SDIO_MASK_TXFIFOEIE_Pos (18U)
+#define SDIO_MASK_TXFIFOEIE_Msk (0x1U << SDIO_MASK_TXFIFOEIE_Pos) /*!< 0x00040000 */
+#define SDIO_MASK_TXFIFOEIE SDIO_MASK_TXFIFOEIE_Msk /*!< Tx FIFO Empty interrupt Enable */
+#define SDIO_MASK_RXFIFOEIE_Pos (19U)
+#define SDIO_MASK_RXFIFOEIE_Msk (0x1U << SDIO_MASK_RXFIFOEIE_Pos) /*!< 0x00080000 */
+#define SDIO_MASK_RXFIFOEIE SDIO_MASK_RXFIFOEIE_Msk /*!< Rx FIFO Empty interrupt Enable */
+#define SDIO_MASK_TXDAVLIE_Pos (20U)
+#define SDIO_MASK_TXDAVLIE_Msk (0x1U << SDIO_MASK_TXDAVLIE_Pos) /*!< 0x00100000 */
+#define SDIO_MASK_TXDAVLIE SDIO_MASK_TXDAVLIE_Msk /*!< Data available in Tx FIFO interrupt Enable */
+#define SDIO_MASK_RXDAVLIE_Pos (21U)
+#define SDIO_MASK_RXDAVLIE_Msk (0x1U << SDIO_MASK_RXDAVLIE_Pos) /*!< 0x00200000 */
+#define SDIO_MASK_RXDAVLIE SDIO_MASK_RXDAVLIE_Msk /*!< Data available in Rx FIFO interrupt Enable */
+#define SDIO_MASK_SDIOITIE_Pos (22U)
+#define SDIO_MASK_SDIOITIE_Msk (0x1U << SDIO_MASK_SDIOITIE_Pos) /*!< 0x00400000 */
+#define SDIO_MASK_SDIOITIE SDIO_MASK_SDIOITIE_Msk /*!< SDIO Mode Interrupt Received interrupt Enable */
+#define SDIO_MASK_CEATAENDIE_Pos (23U)
+#define SDIO_MASK_CEATAENDIE_Msk (0x1U << SDIO_MASK_CEATAENDIE_Pos) /*!< 0x00800000 */
+#define SDIO_MASK_CEATAENDIE SDIO_MASK_CEATAENDIE_Msk /*!< CE-ATA command completion signal received Interrupt Enable */
+
+/***************** Bit definition for SDIO_FIFOCNT register *****************/
+#define SDIO_FIFOCNT_FIFOCOUNT_Pos (0U)
+#define SDIO_FIFOCNT_FIFOCOUNT_Msk (0xFFFFFFU << SDIO_FIFOCNT_FIFOCOUNT_Pos) /*!< 0x00FFFFFF */
+#define SDIO_FIFOCNT_FIFOCOUNT SDIO_FIFOCNT_FIFOCOUNT_Msk /*!< Remaining number of words to be written to or read from the FIFO */
+
+/****************** Bit definition for SDIO_FIFO register *******************/
+#define SDIO_FIFO_FIFODATA_Pos (0U)
+#define SDIO_FIFO_FIFODATA_Msk (0xFFFFFFFFU << SDIO_FIFO_FIFODATA_Pos) /*!< 0xFFFFFFFF */
+#define SDIO_FIFO_FIFODATA SDIO_FIFO_FIFODATA_Msk /*!< Receive and transmit FIFO data */
+
+/******************************************************************************/
+/* */
+/* USB Device FS */
+/* */
+/******************************************************************************/
+
+/*!< Endpoint-specific registers */
+#define USB_EP0R USB_BASE /*!< Endpoint 0 register address */
+#define USB_EP1R (USB_BASE + 0x00000004) /*!< Endpoint 1 register address */
+#define USB_EP2R (USB_BASE + 0x00000008) /*!< Endpoint 2 register address */
+#define USB_EP3R (USB_BASE + 0x0000000C) /*!< Endpoint 3 register address */
+#define USB_EP4R (USB_BASE + 0x00000010) /*!< Endpoint 4 register address */
+#define USB_EP5R (USB_BASE + 0x00000014) /*!< Endpoint 5 register address */
+#define USB_EP6R (USB_BASE + 0x00000018) /*!< Endpoint 6 register address */
+#define USB_EP7R (USB_BASE + 0x0000001C) /*!< Endpoint 7 register address */
+
+/* bit positions */
+#define USB_EP_CTR_RX_Pos (15U)
+#define USB_EP_CTR_RX_Msk (0x1U << USB_EP_CTR_RX_Pos) /*!< 0x00008000 */
+#define USB_EP_CTR_RX USB_EP_CTR_RX_Msk /*!< EndPoint Correct TRansfer RX */
+#define USB_EP_DTOG_RX_Pos (14U)
+#define USB_EP_DTOG_RX_Msk (0x1U << USB_EP_DTOG_RX_Pos) /*!< 0x00004000 */
+#define USB_EP_DTOG_RX USB_EP_DTOG_RX_Msk /*!< EndPoint Data TOGGLE RX */
+#define USB_EPRX_STAT_Pos (12U)
+#define USB_EPRX_STAT_Msk (0x3U << USB_EPRX_STAT_Pos) /*!< 0x00003000 */
+#define USB_EPRX_STAT USB_EPRX_STAT_Msk /*!< EndPoint RX STATus bit field */
+#define USB_EP_SETUP_Pos (11U)
+#define USB_EP_SETUP_Msk (0x1U << USB_EP_SETUP_Pos) /*!< 0x00000800 */
+#define USB_EP_SETUP USB_EP_SETUP_Msk /*!< EndPoint SETUP */
+#define USB_EP_T_FIELD_Pos (9U)
+#define USB_EP_T_FIELD_Msk (0x3U << USB_EP_T_FIELD_Pos) /*!< 0x00000600 */
+#define USB_EP_T_FIELD USB_EP_T_FIELD_Msk /*!< EndPoint TYPE */
+#define USB_EP_KIND_Pos (8U)
+#define USB_EP_KIND_Msk (0x1U << USB_EP_KIND_Pos) /*!< 0x00000100 */
+#define USB_EP_KIND USB_EP_KIND_Msk /*!< EndPoint KIND */
+#define USB_EP_CTR_TX_Pos (7U)
+#define USB_EP_CTR_TX_Msk (0x1U << USB_EP_CTR_TX_Pos) /*!< 0x00000080 */
+#define USB_EP_CTR_TX USB_EP_CTR_TX_Msk /*!< EndPoint Correct TRansfer TX */
+#define USB_EP_DTOG_TX_Pos (6U)
+#define USB_EP_DTOG_TX_Msk (0x1U << USB_EP_DTOG_TX_Pos) /*!< 0x00000040 */
+#define USB_EP_DTOG_TX USB_EP_DTOG_TX_Msk /*!< EndPoint Data TOGGLE TX */
+#define USB_EPTX_STAT_Pos (4U)
+#define USB_EPTX_STAT_Msk (0x3U << USB_EPTX_STAT_Pos) /*!< 0x00000030 */
+#define USB_EPTX_STAT USB_EPTX_STAT_Msk /*!< EndPoint TX STATus bit field */
+#define USB_EPADDR_FIELD_Pos (0U)
+#define USB_EPADDR_FIELD_Msk (0xFU << USB_EPADDR_FIELD_Pos) /*!< 0x0000000F */
+#define USB_EPADDR_FIELD USB_EPADDR_FIELD_Msk /*!< EndPoint ADDRess FIELD */
+
+/* EndPoint REGister MASK (no toggle fields) */
+#define USB_EPREG_MASK (USB_EP_CTR_RX|USB_EP_SETUP|USB_EP_T_FIELD|USB_EP_KIND|USB_EP_CTR_TX|USB_EPADDR_FIELD)
+ /*!< EP_TYPE[1:0] EndPoint TYPE */
+#define USB_EP_TYPE_MASK_Pos (9U)
+#define USB_EP_TYPE_MASK_Msk (0x3U << USB_EP_TYPE_MASK_Pos) /*!< 0x00000600 */
+#define USB_EP_TYPE_MASK USB_EP_TYPE_MASK_Msk /*!< EndPoint TYPE Mask */
+#define USB_EP_BULK ((uint32_t)0x00000000) /*!< EndPoint BULK */
+#define USB_EP_CONTROL ((uint32_t)0x00000200) /*!< EndPoint CONTROL */
+#define USB_EP_ISOCHRONOUS ((uint32_t)0x00000400) /*!< EndPoint ISOCHRONOUS */
+#define USB_EP_INTERRUPT ((uint32_t)0x00000600) /*!< EndPoint INTERRUPT */
+#define USB_EP_T_MASK (~USB_EP_T_FIELD & USB_EPREG_MASK)
+
+#define USB_EPKIND_MASK (~USB_EP_KIND & USB_EPREG_MASK) /*!< EP_KIND EndPoint KIND */
+ /*!< STAT_TX[1:0] STATus for TX transfer */
+#define USB_EP_TX_DIS ((uint32_t)0x00000000) /*!< EndPoint TX DISabled */
+#define USB_EP_TX_STALL ((uint32_t)0x00000010) /*!< EndPoint TX STALLed */
+#define USB_EP_TX_NAK ((uint32_t)0x00000020) /*!< EndPoint TX NAKed */
+#define USB_EP_TX_VALID ((uint32_t)0x00000030) /*!< EndPoint TX VALID */
+#define USB_EPTX_DTOG1 ((uint32_t)0x00000010) /*!< EndPoint TX Data TOGgle bit1 */
+#define USB_EPTX_DTOG2 ((uint32_t)0x00000020) /*!< EndPoint TX Data TOGgle bit2 */
+#define USB_EPTX_DTOGMASK (USB_EPTX_STAT|USB_EPREG_MASK)
+ /*!< STAT_RX[1:0] STATus for RX transfer */
+#define USB_EP_RX_DIS ((uint32_t)0x00000000) /*!< EndPoint RX DISabled */
+#define USB_EP_RX_STALL ((uint32_t)0x00001000) /*!< EndPoint RX STALLed */
+#define USB_EP_RX_NAK ((uint32_t)0x00002000) /*!< EndPoint RX NAKed */
+#define USB_EP_RX_VALID ((uint32_t)0x00003000) /*!< EndPoint RX VALID */
+#define USB_EPRX_DTOG1 ((uint32_t)0x00001000) /*!< EndPoint RX Data TOGgle bit1 */
+#define USB_EPRX_DTOG2 ((uint32_t)0x00002000) /*!< EndPoint RX Data TOGgle bit1 */
+#define USB_EPRX_DTOGMASK (USB_EPRX_STAT|USB_EPREG_MASK)
+
+/******************* Bit definition for USB_EP0R register *******************/
+#define USB_EP0R_EA_Pos (0U)
+#define USB_EP0R_EA_Msk (0xFU << USB_EP0R_EA_Pos) /*!< 0x0000000F */
+#define USB_EP0R_EA USB_EP0R_EA_Msk /*!< Endpoint Address */
+
+#define USB_EP0R_STAT_TX_Pos (4U)
+#define USB_EP0R_STAT_TX_Msk (0x3U << USB_EP0R_STAT_TX_Pos) /*!< 0x00000030 */
+#define USB_EP0R_STAT_TX USB_EP0R_STAT_TX_Msk /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */
+#define USB_EP0R_STAT_TX_0 (0x1U << USB_EP0R_STAT_TX_Pos) /*!< 0x00000010 */
+#define USB_EP0R_STAT_TX_1 (0x2U << USB_EP0R_STAT_TX_Pos) /*!< 0x00000020 */
+
+#define USB_EP0R_DTOG_TX_Pos (6U)
+#define USB_EP0R_DTOG_TX_Msk (0x1U << USB_EP0R_DTOG_TX_Pos) /*!< 0x00000040 */
+#define USB_EP0R_DTOG_TX USB_EP0R_DTOG_TX_Msk /*!< Data Toggle, for transmission transfers */
+#define USB_EP0R_CTR_TX_Pos (7U)
+#define USB_EP0R_CTR_TX_Msk (0x1U << USB_EP0R_CTR_TX_Pos) /*!< 0x00000080 */
+#define USB_EP0R_CTR_TX USB_EP0R_CTR_TX_Msk /*!< Correct Transfer for transmission */
+#define USB_EP0R_EP_KIND_Pos (8U)
+#define USB_EP0R_EP_KIND_Msk (0x1U << USB_EP0R_EP_KIND_Pos) /*!< 0x00000100 */
+#define USB_EP0R_EP_KIND USB_EP0R_EP_KIND_Msk /*!< Endpoint Kind */
+
+#define USB_EP0R_EP_TYPE_Pos (9U)
+#define USB_EP0R_EP_TYPE_Msk (0x3U << USB_EP0R_EP_TYPE_Pos) /*!< 0x00000600 */
+#define USB_EP0R_EP_TYPE USB_EP0R_EP_TYPE_Msk /*!< EP_TYPE[1:0] bits (Endpoint type) */
+#define USB_EP0R_EP_TYPE_0 (0x1U << USB_EP0R_EP_TYPE_Pos) /*!< 0x00000200 */
+#define USB_EP0R_EP_TYPE_1 (0x2U << USB_EP0R_EP_TYPE_Pos) /*!< 0x00000400 */
+
+#define USB_EP0R_SETUP_Pos (11U)
+#define USB_EP0R_SETUP_Msk (0x1U << USB_EP0R_SETUP_Pos) /*!< 0x00000800 */
+#define USB_EP0R_SETUP USB_EP0R_SETUP_Msk /*!< Setup transaction completed */
+
+#define USB_EP0R_STAT_RX_Pos (12U)
+#define USB_EP0R_STAT_RX_Msk (0x3U << USB_EP0R_STAT_RX_Pos) /*!< 0x00003000 */
+#define USB_EP0R_STAT_RX USB_EP0R_STAT_RX_Msk /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */
+#define USB_EP0R_STAT_RX_0 (0x1U << USB_EP0R_STAT_RX_Pos) /*!< 0x00001000 */
+#define USB_EP0R_STAT_RX_1 (0x2U << USB_EP0R_STAT_RX_Pos) /*!< 0x00002000 */
+
+#define USB_EP0R_DTOG_RX_Pos (14U)
+#define USB_EP0R_DTOG_RX_Msk (0x1U << USB_EP0R_DTOG_RX_Pos) /*!< 0x00004000 */
+#define USB_EP0R_DTOG_RX USB_EP0R_DTOG_RX_Msk /*!< Data Toggle, for reception transfers */
+#define USB_EP0R_CTR_RX_Pos (15U)
+#define USB_EP0R_CTR_RX_Msk (0x1U << USB_EP0R_CTR_RX_Pos) /*!< 0x00008000 */
+#define USB_EP0R_CTR_RX USB_EP0R_CTR_RX_Msk /*!< Correct Transfer for reception */
+
+/******************* Bit definition for USB_EP1R register *******************/
+#define USB_EP1R_EA_Pos (0U)
+#define USB_EP1R_EA_Msk (0xFU << USB_EP1R_EA_Pos) /*!< 0x0000000F */
+#define USB_EP1R_EA USB_EP1R_EA_Msk /*!< Endpoint Address */
+
+#define USB_EP1R_STAT_TX_Pos (4U)
+#define USB_EP1R_STAT_TX_Msk (0x3U << USB_EP1R_STAT_TX_Pos) /*!< 0x00000030 */
+#define USB_EP1R_STAT_TX USB_EP1R_STAT_TX_Msk /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */
+#define USB_EP1R_STAT_TX_0 (0x1U << USB_EP1R_STAT_TX_Pos) /*!< 0x00000010 */
+#define USB_EP1R_STAT_TX_1 (0x2U << USB_EP1R_STAT_TX_Pos) /*!< 0x00000020 */
+
+#define USB_EP1R_DTOG_TX_Pos (6U)
+#define USB_EP1R_DTOG_TX_Msk (0x1U << USB_EP1R_DTOG_TX_Pos) /*!< 0x00000040 */
+#define USB_EP1R_DTOG_TX USB_EP1R_DTOG_TX_Msk /*!< Data Toggle, for transmission transfers */
+#define USB_EP1R_CTR_TX_Pos (7U)
+#define USB_EP1R_CTR_TX_Msk (0x1U << USB_EP1R_CTR_TX_Pos) /*!< 0x00000080 */
+#define USB_EP1R_CTR_TX USB_EP1R_CTR_TX_Msk /*!< Correct Transfer for transmission */
+#define USB_EP1R_EP_KIND_Pos (8U)
+#define USB_EP1R_EP_KIND_Msk (0x1U << USB_EP1R_EP_KIND_Pos) /*!< 0x00000100 */
+#define USB_EP1R_EP_KIND USB_EP1R_EP_KIND_Msk /*!< Endpoint Kind */
+
+#define USB_EP1R_EP_TYPE_Pos (9U)
+#define USB_EP1R_EP_TYPE_Msk (0x3U << USB_EP1R_EP_TYPE_Pos) /*!< 0x00000600 */
+#define USB_EP1R_EP_TYPE USB_EP1R_EP_TYPE_Msk /*!< EP_TYPE[1:0] bits (Endpoint type) */
+#define USB_EP1R_EP_TYPE_0 (0x1U << USB_EP1R_EP_TYPE_Pos) /*!< 0x00000200 */
+#define USB_EP1R_EP_TYPE_1 (0x2U << USB_EP1R_EP_TYPE_Pos) /*!< 0x00000400 */
+
+#define USB_EP1R_SETUP_Pos (11U)
+#define USB_EP1R_SETUP_Msk (0x1U << USB_EP1R_SETUP_Pos) /*!< 0x00000800 */
+#define USB_EP1R_SETUP USB_EP1R_SETUP_Msk /*!< Setup transaction completed */
+
+#define USB_EP1R_STAT_RX_Pos (12U)
+#define USB_EP1R_STAT_RX_Msk (0x3U << USB_EP1R_STAT_RX_Pos) /*!< 0x00003000 */
+#define USB_EP1R_STAT_RX USB_EP1R_STAT_RX_Msk /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */
+#define USB_EP1R_STAT_RX_0 (0x1U << USB_EP1R_STAT_RX_Pos) /*!< 0x00001000 */
+#define USB_EP1R_STAT_RX_1 (0x2U << USB_EP1R_STAT_RX_Pos) /*!< 0x00002000 */
+
+#define USB_EP1R_DTOG_RX_Pos (14U)
+#define USB_EP1R_DTOG_RX_Msk (0x1U << USB_EP1R_DTOG_RX_Pos) /*!< 0x00004000 */
+#define USB_EP1R_DTOG_RX USB_EP1R_DTOG_RX_Msk /*!< Data Toggle, for reception transfers */
+#define USB_EP1R_CTR_RX_Pos (15U)
+#define USB_EP1R_CTR_RX_Msk (0x1U << USB_EP1R_CTR_RX_Pos) /*!< 0x00008000 */
+#define USB_EP1R_CTR_RX USB_EP1R_CTR_RX_Msk /*!< Correct Transfer for reception */
+
+/******************* Bit definition for USB_EP2R register *******************/
+#define USB_EP2R_EA_Pos (0U)
+#define USB_EP2R_EA_Msk (0xFU << USB_EP2R_EA_Pos) /*!< 0x0000000F */
+#define USB_EP2R_EA USB_EP2R_EA_Msk /*!< Endpoint Address */
+
+#define USB_EP2R_STAT_TX_Pos (4U)
+#define USB_EP2R_STAT_TX_Msk (0x3U << USB_EP2R_STAT_TX_Pos) /*!< 0x00000030 */
+#define USB_EP2R_STAT_TX USB_EP2R_STAT_TX_Msk /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */
+#define USB_EP2R_STAT_TX_0 (0x1U << USB_EP2R_STAT_TX_Pos) /*!< 0x00000010 */
+#define USB_EP2R_STAT_TX_1 (0x2U << USB_EP2R_STAT_TX_Pos) /*!< 0x00000020 */
+
+#define USB_EP2R_DTOG_TX_Pos (6U)
+#define USB_EP2R_DTOG_TX_Msk (0x1U << USB_EP2R_DTOG_TX_Pos) /*!< 0x00000040 */
+#define USB_EP2R_DTOG_TX USB_EP2R_DTOG_TX_Msk /*!< Data Toggle, for transmission transfers */
+#define USB_EP2R_CTR_TX_Pos (7U)
+#define USB_EP2R_CTR_TX_Msk (0x1U << USB_EP2R_CTR_TX_Pos) /*!< 0x00000080 */
+#define USB_EP2R_CTR_TX USB_EP2R_CTR_TX_Msk /*!< Correct Transfer for transmission */
+#define USB_EP2R_EP_KIND_Pos (8U)
+#define USB_EP2R_EP_KIND_Msk (0x1U << USB_EP2R_EP_KIND_Pos) /*!< 0x00000100 */
+#define USB_EP2R_EP_KIND USB_EP2R_EP_KIND_Msk /*!< Endpoint Kind */
+
+#define USB_EP2R_EP_TYPE_Pos (9U)
+#define USB_EP2R_EP_TYPE_Msk (0x3U << USB_EP2R_EP_TYPE_Pos) /*!< 0x00000600 */
+#define USB_EP2R_EP_TYPE USB_EP2R_EP_TYPE_Msk /*!< EP_TYPE[1:0] bits (Endpoint type) */
+#define USB_EP2R_EP_TYPE_0 (0x1U << USB_EP2R_EP_TYPE_Pos) /*!< 0x00000200 */
+#define USB_EP2R_EP_TYPE_1 (0x2U << USB_EP2R_EP_TYPE_Pos) /*!< 0x00000400 */
+
+#define USB_EP2R_SETUP_Pos (11U)
+#define USB_EP2R_SETUP_Msk (0x1U << USB_EP2R_SETUP_Pos) /*!< 0x00000800 */
+#define USB_EP2R_SETUP USB_EP2R_SETUP_Msk /*!< Setup transaction completed */
+
+#define USB_EP2R_STAT_RX_Pos (12U)
+#define USB_EP2R_STAT_RX_Msk (0x3U << USB_EP2R_STAT_RX_Pos) /*!< 0x00003000 */
+#define USB_EP2R_STAT_RX USB_EP2R_STAT_RX_Msk /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */
+#define USB_EP2R_STAT_RX_0 (0x1U << USB_EP2R_STAT_RX_Pos) /*!< 0x00001000 */
+#define USB_EP2R_STAT_RX_1 (0x2U << USB_EP2R_STAT_RX_Pos) /*!< 0x00002000 */
+
+#define USB_EP2R_DTOG_RX_Pos (14U)
+#define USB_EP2R_DTOG_RX_Msk (0x1U << USB_EP2R_DTOG_RX_Pos) /*!< 0x00004000 */
+#define USB_EP2R_DTOG_RX USB_EP2R_DTOG_RX_Msk /*!< Data Toggle, for reception transfers */
+#define USB_EP2R_CTR_RX_Pos (15U)
+#define USB_EP2R_CTR_RX_Msk (0x1U << USB_EP2R_CTR_RX_Pos) /*!< 0x00008000 */
+#define USB_EP2R_CTR_RX USB_EP2R_CTR_RX_Msk /*!< Correct Transfer for reception */
+
+/******************* Bit definition for USB_EP3R register *******************/
+#define USB_EP3R_EA_Pos (0U)
+#define USB_EP3R_EA_Msk (0xFU << USB_EP3R_EA_Pos) /*!< 0x0000000F */
+#define USB_EP3R_EA USB_EP3R_EA_Msk /*!< Endpoint Address */
+
+#define USB_EP3R_STAT_TX_Pos (4U)
+#define USB_EP3R_STAT_TX_Msk (0x3U << USB_EP3R_STAT_TX_Pos) /*!< 0x00000030 */
+#define USB_EP3R_STAT_TX USB_EP3R_STAT_TX_Msk /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */
+#define USB_EP3R_STAT_TX_0 (0x1U << USB_EP3R_STAT_TX_Pos) /*!< 0x00000010 */
+#define USB_EP3R_STAT_TX_1 (0x2U << USB_EP3R_STAT_TX_Pos) /*!< 0x00000020 */
+
+#define USB_EP3R_DTOG_TX_Pos (6U)
+#define USB_EP3R_DTOG_TX_Msk (0x1U << USB_EP3R_DTOG_TX_Pos) /*!< 0x00000040 */
+#define USB_EP3R_DTOG_TX USB_EP3R_DTOG_TX_Msk /*!< Data Toggle, for transmission transfers */
+#define USB_EP3R_CTR_TX_Pos (7U)
+#define USB_EP3R_CTR_TX_Msk (0x1U << USB_EP3R_CTR_TX_Pos) /*!< 0x00000080 */
+#define USB_EP3R_CTR_TX USB_EP3R_CTR_TX_Msk /*!< Correct Transfer for transmission */
+#define USB_EP3R_EP_KIND_Pos (8U)
+#define USB_EP3R_EP_KIND_Msk (0x1U << USB_EP3R_EP_KIND_Pos) /*!< 0x00000100 */
+#define USB_EP3R_EP_KIND USB_EP3R_EP_KIND_Msk /*!< Endpoint Kind */
+
+#define USB_EP3R_EP_TYPE_Pos (9U)
+#define USB_EP3R_EP_TYPE_Msk (0x3U << USB_EP3R_EP_TYPE_Pos) /*!< 0x00000600 */
+#define USB_EP3R_EP_TYPE USB_EP3R_EP_TYPE_Msk /*!< EP_TYPE[1:0] bits (Endpoint type) */
+#define USB_EP3R_EP_TYPE_0 (0x1U << USB_EP3R_EP_TYPE_Pos) /*!< 0x00000200 */
+#define USB_EP3R_EP_TYPE_1 (0x2U << USB_EP3R_EP_TYPE_Pos) /*!< 0x00000400 */
+
+#define USB_EP3R_SETUP_Pos (11U)
+#define USB_EP3R_SETUP_Msk (0x1U << USB_EP3R_SETUP_Pos) /*!< 0x00000800 */
+#define USB_EP3R_SETUP USB_EP3R_SETUP_Msk /*!< Setup transaction completed */
+
+#define USB_EP3R_STAT_RX_Pos (12U)
+#define USB_EP3R_STAT_RX_Msk (0x3U << USB_EP3R_STAT_RX_Pos) /*!< 0x00003000 */
+#define USB_EP3R_STAT_RX USB_EP3R_STAT_RX_Msk /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */
+#define USB_EP3R_STAT_RX_0 (0x1U << USB_EP3R_STAT_RX_Pos) /*!< 0x00001000 */
+#define USB_EP3R_STAT_RX_1 (0x2U << USB_EP3R_STAT_RX_Pos) /*!< 0x00002000 */
+
+#define USB_EP3R_DTOG_RX_Pos (14U)
+#define USB_EP3R_DTOG_RX_Msk (0x1U << USB_EP3R_DTOG_RX_Pos) /*!< 0x00004000 */
+#define USB_EP3R_DTOG_RX USB_EP3R_DTOG_RX_Msk /*!< Data Toggle, for reception transfers */
+#define USB_EP3R_CTR_RX_Pos (15U)
+#define USB_EP3R_CTR_RX_Msk (0x1U << USB_EP3R_CTR_RX_Pos) /*!< 0x00008000 */
+#define USB_EP3R_CTR_RX USB_EP3R_CTR_RX_Msk /*!< Correct Transfer for reception */
+
+/******************* Bit definition for USB_EP4R register *******************/
+#define USB_EP4R_EA_Pos (0U)
+#define USB_EP4R_EA_Msk (0xFU << USB_EP4R_EA_Pos) /*!< 0x0000000F */
+#define USB_EP4R_EA USB_EP4R_EA_Msk /*!< Endpoint Address */
+
+#define USB_EP4R_STAT_TX_Pos (4U)
+#define USB_EP4R_STAT_TX_Msk (0x3U << USB_EP4R_STAT_TX_Pos) /*!< 0x00000030 */
+#define USB_EP4R_STAT_TX USB_EP4R_STAT_TX_Msk /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */
+#define USB_EP4R_STAT_TX_0 (0x1U << USB_EP4R_STAT_TX_Pos) /*!< 0x00000010 */
+#define USB_EP4R_STAT_TX_1 (0x2U << USB_EP4R_STAT_TX_Pos) /*!< 0x00000020 */
+
+#define USB_EP4R_DTOG_TX_Pos (6U)
+#define USB_EP4R_DTOG_TX_Msk (0x1U << USB_EP4R_DTOG_TX_Pos) /*!< 0x00000040 */
+#define USB_EP4R_DTOG_TX USB_EP4R_DTOG_TX_Msk /*!< Data Toggle, for transmission transfers */
+#define USB_EP4R_CTR_TX_Pos (7U)
+#define USB_EP4R_CTR_TX_Msk (0x1U << USB_EP4R_CTR_TX_Pos) /*!< 0x00000080 */
+#define USB_EP4R_CTR_TX USB_EP4R_CTR_TX_Msk /*!< Correct Transfer for transmission */
+#define USB_EP4R_EP_KIND_Pos (8U)
+#define USB_EP4R_EP_KIND_Msk (0x1U << USB_EP4R_EP_KIND_Pos) /*!< 0x00000100 */
+#define USB_EP4R_EP_KIND USB_EP4R_EP_KIND_Msk /*!< Endpoint Kind */
+
+#define USB_EP4R_EP_TYPE_Pos (9U)
+#define USB_EP4R_EP_TYPE_Msk (0x3U << USB_EP4R_EP_TYPE_Pos) /*!< 0x00000600 */
+#define USB_EP4R_EP_TYPE USB_EP4R_EP_TYPE_Msk /*!< EP_TYPE[1:0] bits (Endpoint type) */
+#define USB_EP4R_EP_TYPE_0 (0x1U << USB_EP4R_EP_TYPE_Pos) /*!< 0x00000200 */
+#define USB_EP4R_EP_TYPE_1 (0x2U << USB_EP4R_EP_TYPE_Pos) /*!< 0x00000400 */
+
+#define USB_EP4R_SETUP_Pos (11U)
+#define USB_EP4R_SETUP_Msk (0x1U << USB_EP4R_SETUP_Pos) /*!< 0x00000800 */
+#define USB_EP4R_SETUP USB_EP4R_SETUP_Msk /*!< Setup transaction completed */
+
+#define USB_EP4R_STAT_RX_Pos (12U)
+#define USB_EP4R_STAT_RX_Msk (0x3U << USB_EP4R_STAT_RX_Pos) /*!< 0x00003000 */
+#define USB_EP4R_STAT_RX USB_EP4R_STAT_RX_Msk /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */
+#define USB_EP4R_STAT_RX_0 (0x1U << USB_EP4R_STAT_RX_Pos) /*!< 0x00001000 */
+#define USB_EP4R_STAT_RX_1 (0x2U << USB_EP4R_STAT_RX_Pos) /*!< 0x00002000 */
+
+#define USB_EP4R_DTOG_RX_Pos (14U)
+#define USB_EP4R_DTOG_RX_Msk (0x1U << USB_EP4R_DTOG_RX_Pos) /*!< 0x00004000 */
+#define USB_EP4R_DTOG_RX USB_EP4R_DTOG_RX_Msk /*!< Data Toggle, for reception transfers */
+#define USB_EP4R_CTR_RX_Pos (15U)
+#define USB_EP4R_CTR_RX_Msk (0x1U << USB_EP4R_CTR_RX_Pos) /*!< 0x00008000 */
+#define USB_EP4R_CTR_RX USB_EP4R_CTR_RX_Msk /*!< Correct Transfer for reception */
+
+/******************* Bit definition for USB_EP5R register *******************/
+#define USB_EP5R_EA_Pos (0U)
+#define USB_EP5R_EA_Msk (0xFU << USB_EP5R_EA_Pos) /*!< 0x0000000F */
+#define USB_EP5R_EA USB_EP5R_EA_Msk /*!< Endpoint Address */
+
+#define USB_EP5R_STAT_TX_Pos (4U)
+#define USB_EP5R_STAT_TX_Msk (0x3U << USB_EP5R_STAT_TX_Pos) /*!< 0x00000030 */
+#define USB_EP5R_STAT_TX USB_EP5R_STAT_TX_Msk /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */
+#define USB_EP5R_STAT_TX_0 (0x1U << USB_EP5R_STAT_TX_Pos) /*!< 0x00000010 */
+#define USB_EP5R_STAT_TX_1 (0x2U << USB_EP5R_STAT_TX_Pos) /*!< 0x00000020 */
+
+#define USB_EP5R_DTOG_TX_Pos (6U)
+#define USB_EP5R_DTOG_TX_Msk (0x1U << USB_EP5R_DTOG_TX_Pos) /*!< 0x00000040 */
+#define USB_EP5R_DTOG_TX USB_EP5R_DTOG_TX_Msk /*!< Data Toggle, for transmission transfers */
+#define USB_EP5R_CTR_TX_Pos (7U)
+#define USB_EP5R_CTR_TX_Msk (0x1U << USB_EP5R_CTR_TX_Pos) /*!< 0x00000080 */
+#define USB_EP5R_CTR_TX USB_EP5R_CTR_TX_Msk /*!< Correct Transfer for transmission */
+#define USB_EP5R_EP_KIND_Pos (8U)
+#define USB_EP5R_EP_KIND_Msk (0x1U << USB_EP5R_EP_KIND_Pos) /*!< 0x00000100 */
+#define USB_EP5R_EP_KIND USB_EP5R_EP_KIND_Msk /*!< Endpoint Kind */
+
+#define USB_EP5R_EP_TYPE_Pos (9U)
+#define USB_EP5R_EP_TYPE_Msk (0x3U << USB_EP5R_EP_TYPE_Pos) /*!< 0x00000600 */
+#define USB_EP5R_EP_TYPE USB_EP5R_EP_TYPE_Msk /*!< EP_TYPE[1:0] bits (Endpoint type) */
+#define USB_EP5R_EP_TYPE_0 (0x1U << USB_EP5R_EP_TYPE_Pos) /*!< 0x00000200 */
+#define USB_EP5R_EP_TYPE_1 (0x2U << USB_EP5R_EP_TYPE_Pos) /*!< 0x00000400 */
+
+#define USB_EP5R_SETUP_Pos (11U)
+#define USB_EP5R_SETUP_Msk (0x1U << USB_EP5R_SETUP_Pos) /*!< 0x00000800 */
+#define USB_EP5R_SETUP USB_EP5R_SETUP_Msk /*!< Setup transaction completed */
+
+#define USB_EP5R_STAT_RX_Pos (12U)
+#define USB_EP5R_STAT_RX_Msk (0x3U << USB_EP5R_STAT_RX_Pos) /*!< 0x00003000 */
+#define USB_EP5R_STAT_RX USB_EP5R_STAT_RX_Msk /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */
+#define USB_EP5R_STAT_RX_0 (0x1U << USB_EP5R_STAT_RX_Pos) /*!< 0x00001000 */
+#define USB_EP5R_STAT_RX_1 (0x2U << USB_EP5R_STAT_RX_Pos) /*!< 0x00002000 */
+
+#define USB_EP5R_DTOG_RX_Pos (14U)
+#define USB_EP5R_DTOG_RX_Msk (0x1U << USB_EP5R_DTOG_RX_Pos) /*!< 0x00004000 */
+#define USB_EP5R_DTOG_RX USB_EP5R_DTOG_RX_Msk /*!< Data Toggle, for reception transfers */
+#define USB_EP5R_CTR_RX_Pos (15U)
+#define USB_EP5R_CTR_RX_Msk (0x1U << USB_EP5R_CTR_RX_Pos) /*!< 0x00008000 */
+#define USB_EP5R_CTR_RX USB_EP5R_CTR_RX_Msk /*!< Correct Transfer for reception */
+
+/******************* Bit definition for USB_EP6R register *******************/
+#define USB_EP6R_EA_Pos (0U)
+#define USB_EP6R_EA_Msk (0xFU << USB_EP6R_EA_Pos) /*!< 0x0000000F */
+#define USB_EP6R_EA USB_EP6R_EA_Msk /*!< Endpoint Address */
+
+#define USB_EP6R_STAT_TX_Pos (4U)
+#define USB_EP6R_STAT_TX_Msk (0x3U << USB_EP6R_STAT_TX_Pos) /*!< 0x00000030 */
+#define USB_EP6R_STAT_TX USB_EP6R_STAT_TX_Msk /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */
+#define USB_EP6R_STAT_TX_0 (0x1U << USB_EP6R_STAT_TX_Pos) /*!< 0x00000010 */
+#define USB_EP6R_STAT_TX_1 (0x2U << USB_EP6R_STAT_TX_Pos) /*!< 0x00000020 */
+
+#define USB_EP6R_DTOG_TX_Pos (6U)
+#define USB_EP6R_DTOG_TX_Msk (0x1U << USB_EP6R_DTOG_TX_Pos) /*!< 0x00000040 */
+#define USB_EP6R_DTOG_TX USB_EP6R_DTOG_TX_Msk /*!< Data Toggle, for transmission transfers */
+#define USB_EP6R_CTR_TX_Pos (7U)
+#define USB_EP6R_CTR_TX_Msk (0x1U << USB_EP6R_CTR_TX_Pos) /*!< 0x00000080 */
+#define USB_EP6R_CTR_TX USB_EP6R_CTR_TX_Msk /*!< Correct Transfer for transmission */
+#define USB_EP6R_EP_KIND_Pos (8U)
+#define USB_EP6R_EP_KIND_Msk (0x1U << USB_EP6R_EP_KIND_Pos) /*!< 0x00000100 */
+#define USB_EP6R_EP_KIND USB_EP6R_EP_KIND_Msk /*!< Endpoint Kind */
+
+#define USB_EP6R_EP_TYPE_Pos (9U)
+#define USB_EP6R_EP_TYPE_Msk (0x3U << USB_EP6R_EP_TYPE_Pos) /*!< 0x00000600 */
+#define USB_EP6R_EP_TYPE USB_EP6R_EP_TYPE_Msk /*!< EP_TYPE[1:0] bits (Endpoint type) */
+#define USB_EP6R_EP_TYPE_0 (0x1U << USB_EP6R_EP_TYPE_Pos) /*!< 0x00000200 */
+#define USB_EP6R_EP_TYPE_1 (0x2U << USB_EP6R_EP_TYPE_Pos) /*!< 0x00000400 */
+
+#define USB_EP6R_SETUP_Pos (11U)
+#define USB_EP6R_SETUP_Msk (0x1U << USB_EP6R_SETUP_Pos) /*!< 0x00000800 */
+#define USB_EP6R_SETUP USB_EP6R_SETUP_Msk /*!< Setup transaction completed */
+
+#define USB_EP6R_STAT_RX_Pos (12U)
+#define USB_EP6R_STAT_RX_Msk (0x3U << USB_EP6R_STAT_RX_Pos) /*!< 0x00003000 */
+#define USB_EP6R_STAT_RX USB_EP6R_STAT_RX_Msk /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */
+#define USB_EP6R_STAT_RX_0 (0x1U << USB_EP6R_STAT_RX_Pos) /*!< 0x00001000 */
+#define USB_EP6R_STAT_RX_1 (0x2U << USB_EP6R_STAT_RX_Pos) /*!< 0x00002000 */
+
+#define USB_EP6R_DTOG_RX_Pos (14U)
+#define USB_EP6R_DTOG_RX_Msk (0x1U << USB_EP6R_DTOG_RX_Pos) /*!< 0x00004000 */
+#define USB_EP6R_DTOG_RX USB_EP6R_DTOG_RX_Msk /*!< Data Toggle, for reception transfers */
+#define USB_EP6R_CTR_RX_Pos (15U)
+#define USB_EP6R_CTR_RX_Msk (0x1U << USB_EP6R_CTR_RX_Pos) /*!< 0x00008000 */
+#define USB_EP6R_CTR_RX USB_EP6R_CTR_RX_Msk /*!< Correct Transfer for reception */
+
+/******************* Bit definition for USB_EP7R register *******************/
+#define USB_EP7R_EA_Pos (0U)
+#define USB_EP7R_EA_Msk (0xFU << USB_EP7R_EA_Pos) /*!< 0x0000000F */
+#define USB_EP7R_EA USB_EP7R_EA_Msk /*!< Endpoint Address */
+
+#define USB_EP7R_STAT_TX_Pos (4U)
+#define USB_EP7R_STAT_TX_Msk (0x3U << USB_EP7R_STAT_TX_Pos) /*!< 0x00000030 */
+#define USB_EP7R_STAT_TX USB_EP7R_STAT_TX_Msk /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */
+#define USB_EP7R_STAT_TX_0 (0x1U << USB_EP7R_STAT_TX_Pos) /*!< 0x00000010 */
+#define USB_EP7R_STAT_TX_1 (0x2U << USB_EP7R_STAT_TX_Pos) /*!< 0x00000020 */
+
+#define USB_EP7R_DTOG_TX_Pos (6U)
+#define USB_EP7R_DTOG_TX_Msk (0x1U << USB_EP7R_DTOG_TX_Pos) /*!< 0x00000040 */
+#define USB_EP7R_DTOG_TX USB_EP7R_DTOG_TX_Msk /*!< Data Toggle, for transmission transfers */
+#define USB_EP7R_CTR_TX_Pos (7U)
+#define USB_EP7R_CTR_TX_Msk (0x1U << USB_EP7R_CTR_TX_Pos) /*!< 0x00000080 */
+#define USB_EP7R_CTR_TX USB_EP7R_CTR_TX_Msk /*!< Correct Transfer for transmission */
+#define USB_EP7R_EP_KIND_Pos (8U)
+#define USB_EP7R_EP_KIND_Msk (0x1U << USB_EP7R_EP_KIND_Pos) /*!< 0x00000100 */
+#define USB_EP7R_EP_KIND USB_EP7R_EP_KIND_Msk /*!< Endpoint Kind */
+
+#define USB_EP7R_EP_TYPE_Pos (9U)
+#define USB_EP7R_EP_TYPE_Msk (0x3U << USB_EP7R_EP_TYPE_Pos) /*!< 0x00000600 */
+#define USB_EP7R_EP_TYPE USB_EP7R_EP_TYPE_Msk /*!< EP_TYPE[1:0] bits (Endpoint type) */
+#define USB_EP7R_EP_TYPE_0 (0x1U << USB_EP7R_EP_TYPE_Pos) /*!< 0x00000200 */
+#define USB_EP7R_EP_TYPE_1 (0x2U << USB_EP7R_EP_TYPE_Pos) /*!< 0x00000400 */
+
+#define USB_EP7R_SETUP_Pos (11U)
+#define USB_EP7R_SETUP_Msk (0x1U << USB_EP7R_SETUP_Pos) /*!< 0x00000800 */
+#define USB_EP7R_SETUP USB_EP7R_SETUP_Msk /*!< Setup transaction completed */
+
+#define USB_EP7R_STAT_RX_Pos (12U)
+#define USB_EP7R_STAT_RX_Msk (0x3U << USB_EP7R_STAT_RX_Pos) /*!< 0x00003000 */
+#define USB_EP7R_STAT_RX USB_EP7R_STAT_RX_Msk /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */
+#define USB_EP7R_STAT_RX_0 (0x1U << USB_EP7R_STAT_RX_Pos) /*!< 0x00001000 */
+#define USB_EP7R_STAT_RX_1 (0x2U << USB_EP7R_STAT_RX_Pos) /*!< 0x00002000 */
+
+#define USB_EP7R_DTOG_RX_Pos (14U)
+#define USB_EP7R_DTOG_RX_Msk (0x1U << USB_EP7R_DTOG_RX_Pos) /*!< 0x00004000 */
+#define USB_EP7R_DTOG_RX USB_EP7R_DTOG_RX_Msk /*!< Data Toggle, for reception transfers */
+#define USB_EP7R_CTR_RX_Pos (15U)
+#define USB_EP7R_CTR_RX_Msk (0x1U << USB_EP7R_CTR_RX_Pos) /*!< 0x00008000 */
+#define USB_EP7R_CTR_RX USB_EP7R_CTR_RX_Msk /*!< Correct Transfer for reception */
+
+/*!< Common registers */
+/******************* Bit definition for USB_CNTR register *******************/
+#define USB_CNTR_FRES_Pos (0U)
+#define USB_CNTR_FRES_Msk (0x1U << USB_CNTR_FRES_Pos) /*!< 0x00000001 */
+#define USB_CNTR_FRES USB_CNTR_FRES_Msk /*!< Force USB Reset */
+#define USB_CNTR_PDWN_Pos (1U)
+#define USB_CNTR_PDWN_Msk (0x1U << USB_CNTR_PDWN_Pos) /*!< 0x00000002 */
+#define USB_CNTR_PDWN USB_CNTR_PDWN_Msk /*!< Power down */
+#define USB_CNTR_LP_MODE_Pos (2U)
+#define USB_CNTR_LP_MODE_Msk (0x1U << USB_CNTR_LP_MODE_Pos) /*!< 0x00000004 */
+#define USB_CNTR_LP_MODE USB_CNTR_LP_MODE_Msk /*!< Low-power mode */
+#define USB_CNTR_FSUSP_Pos (3U)
+#define USB_CNTR_FSUSP_Msk (0x1U << USB_CNTR_FSUSP_Pos) /*!< 0x00000008 */
+#define USB_CNTR_FSUSP USB_CNTR_FSUSP_Msk /*!< Force suspend */
+#define USB_CNTR_RESUME_Pos (4U)
+#define USB_CNTR_RESUME_Msk (0x1U << USB_CNTR_RESUME_Pos) /*!< 0x00000010 */
+#define USB_CNTR_RESUME USB_CNTR_RESUME_Msk /*!< Resume request */
+#define USB_CNTR_ESOFM_Pos (8U)
+#define USB_CNTR_ESOFM_Msk (0x1U << USB_CNTR_ESOFM_Pos) /*!< 0x00000100 */
+#define USB_CNTR_ESOFM USB_CNTR_ESOFM_Msk /*!< Expected Start Of Frame Interrupt Mask */
+#define USB_CNTR_SOFM_Pos (9U)
+#define USB_CNTR_SOFM_Msk (0x1U << USB_CNTR_SOFM_Pos) /*!< 0x00000200 */
+#define USB_CNTR_SOFM USB_CNTR_SOFM_Msk /*!< Start Of Frame Interrupt Mask */
+#define USB_CNTR_RESETM_Pos (10U)
+#define USB_CNTR_RESETM_Msk (0x1U << USB_CNTR_RESETM_Pos) /*!< 0x00000400 */
+#define USB_CNTR_RESETM USB_CNTR_RESETM_Msk /*!< RESET Interrupt Mask */
+#define USB_CNTR_SUSPM_Pos (11U)
+#define USB_CNTR_SUSPM_Msk (0x1U << USB_CNTR_SUSPM_Pos) /*!< 0x00000800 */
+#define USB_CNTR_SUSPM USB_CNTR_SUSPM_Msk /*!< Suspend mode Interrupt Mask */
+#define USB_CNTR_WKUPM_Pos (12U)
+#define USB_CNTR_WKUPM_Msk (0x1U << USB_CNTR_WKUPM_Pos) /*!< 0x00001000 */
+#define USB_CNTR_WKUPM USB_CNTR_WKUPM_Msk /*!< Wakeup Interrupt Mask */
+#define USB_CNTR_ERRM_Pos (13U)
+#define USB_CNTR_ERRM_Msk (0x1U << USB_CNTR_ERRM_Pos) /*!< 0x00002000 */
+#define USB_CNTR_ERRM USB_CNTR_ERRM_Msk /*!< Error Interrupt Mask */
+#define USB_CNTR_PMAOVRM_Pos (14U)
+#define USB_CNTR_PMAOVRM_Msk (0x1U << USB_CNTR_PMAOVRM_Pos) /*!< 0x00004000 */
+#define USB_CNTR_PMAOVRM USB_CNTR_PMAOVRM_Msk /*!< Packet Memory Area Over / Underrun Interrupt Mask */
+#define USB_CNTR_CTRM_Pos (15U)
+#define USB_CNTR_CTRM_Msk (0x1U << USB_CNTR_CTRM_Pos) /*!< 0x00008000 */
+#define USB_CNTR_CTRM USB_CNTR_CTRM_Msk /*!< Correct Transfer Interrupt Mask */
+
+/******************* Bit definition for USB_ISTR register *******************/
+#define USB_ISTR_EP_ID_Pos (0U)
+#define USB_ISTR_EP_ID_Msk (0xFU << USB_ISTR_EP_ID_Pos) /*!< 0x0000000F */
+#define USB_ISTR_EP_ID USB_ISTR_EP_ID_Msk /*!< Endpoint Identifier */
+#define USB_ISTR_DIR_Pos (4U)
+#define USB_ISTR_DIR_Msk (0x1U << USB_ISTR_DIR_Pos) /*!< 0x00000010 */
+#define USB_ISTR_DIR USB_ISTR_DIR_Msk /*!< Direction of transaction */
+#define USB_ISTR_ESOF_Pos (8U)
+#define USB_ISTR_ESOF_Msk (0x1U << USB_ISTR_ESOF_Pos) /*!< 0x00000100 */
+#define USB_ISTR_ESOF USB_ISTR_ESOF_Msk /*!< Expected Start Of Frame */
+#define USB_ISTR_SOF_Pos (9U)
+#define USB_ISTR_SOF_Msk (0x1U << USB_ISTR_SOF_Pos) /*!< 0x00000200 */
+#define USB_ISTR_SOF USB_ISTR_SOF_Msk /*!< Start Of Frame */
+#define USB_ISTR_RESET_Pos (10U)
+#define USB_ISTR_RESET_Msk (0x1U << USB_ISTR_RESET_Pos) /*!< 0x00000400 */
+#define USB_ISTR_RESET USB_ISTR_RESET_Msk /*!< USB RESET request */
+#define USB_ISTR_SUSP_Pos (11U)
+#define USB_ISTR_SUSP_Msk (0x1U << USB_ISTR_SUSP_Pos) /*!< 0x00000800 */
+#define USB_ISTR_SUSP USB_ISTR_SUSP_Msk /*!< Suspend mode request */
+#define USB_ISTR_WKUP_Pos (12U)
+#define USB_ISTR_WKUP_Msk (0x1U << USB_ISTR_WKUP_Pos) /*!< 0x00001000 */
+#define USB_ISTR_WKUP USB_ISTR_WKUP_Msk /*!< Wake up */
+#define USB_ISTR_ERR_Pos (13U)
+#define USB_ISTR_ERR_Msk (0x1U << USB_ISTR_ERR_Pos) /*!< 0x00002000 */
+#define USB_ISTR_ERR USB_ISTR_ERR_Msk /*!< Error */
+#define USB_ISTR_PMAOVR_Pos (14U)
+#define USB_ISTR_PMAOVR_Msk (0x1U << USB_ISTR_PMAOVR_Pos) /*!< 0x00004000 */
+#define USB_ISTR_PMAOVR USB_ISTR_PMAOVR_Msk /*!< Packet Memory Area Over / Underrun */
+#define USB_ISTR_CTR_Pos (15U)
+#define USB_ISTR_CTR_Msk (0x1U << USB_ISTR_CTR_Pos) /*!< 0x00008000 */
+#define USB_ISTR_CTR USB_ISTR_CTR_Msk /*!< Correct Transfer */
+
+/******************* Bit definition for USB_FNR register ********************/
+#define USB_FNR_FN_Pos (0U)
+#define USB_FNR_FN_Msk (0x7FFU << USB_FNR_FN_Pos) /*!< 0x000007FF */
+#define USB_FNR_FN USB_FNR_FN_Msk /*!< Frame Number */
+#define USB_FNR_LSOF_Pos (11U)
+#define USB_FNR_LSOF_Msk (0x3U << USB_FNR_LSOF_Pos) /*!< 0x00001800 */
+#define USB_FNR_LSOF USB_FNR_LSOF_Msk /*!< Lost SOF */
+#define USB_FNR_LCK_Pos (13U)
+#define USB_FNR_LCK_Msk (0x1U << USB_FNR_LCK_Pos) /*!< 0x00002000 */
+#define USB_FNR_LCK USB_FNR_LCK_Msk /*!< Locked */
+#define USB_FNR_RXDM_Pos (14U)
+#define USB_FNR_RXDM_Msk (0x1U << USB_FNR_RXDM_Pos) /*!< 0x00004000 */
+#define USB_FNR_RXDM USB_FNR_RXDM_Msk /*!< Receive Data - Line Status */
+#define USB_FNR_RXDP_Pos (15U)
+#define USB_FNR_RXDP_Msk (0x1U << USB_FNR_RXDP_Pos) /*!< 0x00008000 */
+#define USB_FNR_RXDP USB_FNR_RXDP_Msk /*!< Receive Data + Line Status */
+
+/****************** Bit definition for USB_DADDR register *******************/
+#define USB_DADDR_ADD_Pos (0U)
+#define USB_DADDR_ADD_Msk (0x7FU << USB_DADDR_ADD_Pos) /*!< 0x0000007F */
+#define USB_DADDR_ADD USB_DADDR_ADD_Msk /*!< ADD[6:0] bits (Device Address) */
+#define USB_DADDR_ADD0_Pos (0U)
+#define USB_DADDR_ADD0_Msk (0x1U << USB_DADDR_ADD0_Pos) /*!< 0x00000001 */
+#define USB_DADDR_ADD0 USB_DADDR_ADD0_Msk /*!< Bit 0 */
+#define USB_DADDR_ADD1_Pos (1U)
+#define USB_DADDR_ADD1_Msk (0x1U << USB_DADDR_ADD1_Pos) /*!< 0x00000002 */
+#define USB_DADDR_ADD1 USB_DADDR_ADD1_Msk /*!< Bit 1 */
+#define USB_DADDR_ADD2_Pos (2U)
+#define USB_DADDR_ADD2_Msk (0x1U << USB_DADDR_ADD2_Pos) /*!< 0x00000004 */
+#define USB_DADDR_ADD2 USB_DADDR_ADD2_Msk /*!< Bit 2 */
+#define USB_DADDR_ADD3_Pos (3U)
+#define USB_DADDR_ADD3_Msk (0x1U << USB_DADDR_ADD3_Pos) /*!< 0x00000008 */
+#define USB_DADDR_ADD3 USB_DADDR_ADD3_Msk /*!< Bit 3 */
+#define USB_DADDR_ADD4_Pos (4U)
+#define USB_DADDR_ADD4_Msk (0x1U << USB_DADDR_ADD4_Pos) /*!< 0x00000010 */
+#define USB_DADDR_ADD4 USB_DADDR_ADD4_Msk /*!< Bit 4 */
+#define USB_DADDR_ADD5_Pos (5U)
+#define USB_DADDR_ADD5_Msk (0x1U << USB_DADDR_ADD5_Pos) /*!< 0x00000020 */
+#define USB_DADDR_ADD5 USB_DADDR_ADD5_Msk /*!< Bit 5 */
+#define USB_DADDR_ADD6_Pos (6U)
+#define USB_DADDR_ADD6_Msk (0x1U << USB_DADDR_ADD6_Pos) /*!< 0x00000040 */
+#define USB_DADDR_ADD6 USB_DADDR_ADD6_Msk /*!< Bit 6 */
+
+#define USB_DADDR_EF_Pos (7U)
+#define USB_DADDR_EF_Msk (0x1U << USB_DADDR_EF_Pos) /*!< 0x00000080 */
+#define USB_DADDR_EF USB_DADDR_EF_Msk /*!< Enable Function */
+
+/****************** Bit definition for USB_BTABLE register ******************/
+#define USB_BTABLE_BTABLE_Pos (3U)
+#define USB_BTABLE_BTABLE_Msk (0x1FFFU << USB_BTABLE_BTABLE_Pos) /*!< 0x0000FFF8 */
+#define USB_BTABLE_BTABLE USB_BTABLE_BTABLE_Msk /*!< Buffer Table */
+
+/*!< Buffer descriptor table */
+/***************** Bit definition for USB_ADDR0_TX register *****************/
+#define USB_ADDR0_TX_ADDR0_TX_Pos (1U)
+#define USB_ADDR0_TX_ADDR0_TX_Msk (0x7FFFU << USB_ADDR0_TX_ADDR0_TX_Pos) /*!< 0x0000FFFE */
+#define USB_ADDR0_TX_ADDR0_TX USB_ADDR0_TX_ADDR0_TX_Msk /*!< Transmission Buffer Address 0 */
+
+/***************** Bit definition for USB_ADDR1_TX register *****************/
+#define USB_ADDR1_TX_ADDR1_TX_Pos (1U)
+#define USB_ADDR1_TX_ADDR1_TX_Msk (0x7FFFU << USB_ADDR1_TX_ADDR1_TX_Pos) /*!< 0x0000FFFE */
+#define USB_ADDR1_TX_ADDR1_TX USB_ADDR1_TX_ADDR1_TX_Msk /*!< Transmission Buffer Address 1 */
+
+/***************** Bit definition for USB_ADDR2_TX register *****************/
+#define USB_ADDR2_TX_ADDR2_TX_Pos (1U)
+#define USB_ADDR2_TX_ADDR2_TX_Msk (0x7FFFU << USB_ADDR2_TX_ADDR2_TX_Pos) /*!< 0x0000FFFE */
+#define USB_ADDR2_TX_ADDR2_TX USB_ADDR2_TX_ADDR2_TX_Msk /*!< Transmission Buffer Address 2 */
+
+/***************** Bit definition for USB_ADDR3_TX register *****************/
+#define USB_ADDR3_TX_ADDR3_TX_Pos (1U)
+#define USB_ADDR3_TX_ADDR3_TX_Msk (0x7FFFU << USB_ADDR3_TX_ADDR3_TX_Pos) /*!< 0x0000FFFE */
+#define USB_ADDR3_TX_ADDR3_TX USB_ADDR3_TX_ADDR3_TX_Msk /*!< Transmission Buffer Address 3 */
+
+/***************** Bit definition for USB_ADDR4_TX register *****************/
+#define USB_ADDR4_TX_ADDR4_TX_Pos (1U)
+#define USB_ADDR4_TX_ADDR4_TX_Msk (0x7FFFU << USB_ADDR4_TX_ADDR4_TX_Pos) /*!< 0x0000FFFE */
+#define USB_ADDR4_TX_ADDR4_TX USB_ADDR4_TX_ADDR4_TX_Msk /*!< Transmission Buffer Address 4 */
+
+/***************** Bit definition for USB_ADDR5_TX register *****************/
+#define USB_ADDR5_TX_ADDR5_TX_Pos (1U)
+#define USB_ADDR5_TX_ADDR5_TX_Msk (0x7FFFU << USB_ADDR5_TX_ADDR5_TX_Pos) /*!< 0x0000FFFE */
+#define USB_ADDR5_TX_ADDR5_TX USB_ADDR5_TX_ADDR5_TX_Msk /*!< Transmission Buffer Address 5 */
+
+/***************** Bit definition for USB_ADDR6_TX register *****************/
+#define USB_ADDR6_TX_ADDR6_TX_Pos (1U)
+#define USB_ADDR6_TX_ADDR6_TX_Msk (0x7FFFU << USB_ADDR6_TX_ADDR6_TX_Pos) /*!< 0x0000FFFE */
+#define USB_ADDR6_TX_ADDR6_TX USB_ADDR6_TX_ADDR6_TX_Msk /*!< Transmission Buffer Address 6 */
+
+/***************** Bit definition for USB_ADDR7_TX register *****************/
+#define USB_ADDR7_TX_ADDR7_TX_Pos (1U)
+#define USB_ADDR7_TX_ADDR7_TX_Msk (0x7FFFU << USB_ADDR7_TX_ADDR7_TX_Pos) /*!< 0x0000FFFE */
+#define USB_ADDR7_TX_ADDR7_TX USB_ADDR7_TX_ADDR7_TX_Msk /*!< Transmission Buffer Address 7 */
+
+/*----------------------------------------------------------------------------*/
+
+/***************** Bit definition for USB_COUNT0_TX register ****************/
+#define USB_COUNT0_TX_COUNT0_TX_Pos (0U)
+#define USB_COUNT0_TX_COUNT0_TX_Msk (0x3FFU << USB_COUNT0_TX_COUNT0_TX_Pos) /*!< 0x000003FF */
+#define USB_COUNT0_TX_COUNT0_TX USB_COUNT0_TX_COUNT0_TX_Msk /*!< Transmission Byte Count 0 */
+
+/***************** Bit definition for USB_COUNT1_TX register ****************/
+#define USB_COUNT1_TX_COUNT1_TX_Pos (0U)
+#define USB_COUNT1_TX_COUNT1_TX_Msk (0x3FFU << USB_COUNT1_TX_COUNT1_TX_Pos) /*!< 0x000003FF */
+#define USB_COUNT1_TX_COUNT1_TX USB_COUNT1_TX_COUNT1_TX_Msk /*!< Transmission Byte Count 1 */
+
+/***************** Bit definition for USB_COUNT2_TX register ****************/
+#define USB_COUNT2_TX_COUNT2_TX_Pos (0U)
+#define USB_COUNT2_TX_COUNT2_TX_Msk (0x3FFU << USB_COUNT2_TX_COUNT2_TX_Pos) /*!< 0x000003FF */
+#define USB_COUNT2_TX_COUNT2_TX USB_COUNT2_TX_COUNT2_TX_Msk /*!< Transmission Byte Count 2 */
+
+/***************** Bit definition for USB_COUNT3_TX register ****************/
+#define USB_COUNT3_TX_COUNT3_TX_Pos (0U)
+#define USB_COUNT3_TX_COUNT3_TX_Msk (0x3FFU << USB_COUNT3_TX_COUNT3_TX_Pos) /*!< 0x000003FF */
+#define USB_COUNT3_TX_COUNT3_TX USB_COUNT3_TX_COUNT3_TX_Msk /*!< Transmission Byte Count 3 */
+
+/***************** Bit definition for USB_COUNT4_TX register ****************/
+#define USB_COUNT4_TX_COUNT4_TX_Pos (0U)
+#define USB_COUNT4_TX_COUNT4_TX_Msk (0x3FFU << USB_COUNT4_TX_COUNT4_TX_Pos) /*!< 0x000003FF */
+#define USB_COUNT4_TX_COUNT4_TX USB_COUNT4_TX_COUNT4_TX_Msk /*!< Transmission Byte Count 4 */
+
+/***************** Bit definition for USB_COUNT5_TX register ****************/
+#define USB_COUNT5_TX_COUNT5_TX_Pos (0U)
+#define USB_COUNT5_TX_COUNT5_TX_Msk (0x3FFU << USB_COUNT5_TX_COUNT5_TX_Pos) /*!< 0x000003FF */
+#define USB_COUNT5_TX_COUNT5_TX USB_COUNT5_TX_COUNT5_TX_Msk /*!< Transmission Byte Count 5 */
+
+/***************** Bit definition for USB_COUNT6_TX register ****************/
+#define USB_COUNT6_TX_COUNT6_TX_Pos (0U)
+#define USB_COUNT6_TX_COUNT6_TX_Msk (0x3FFU << USB_COUNT6_TX_COUNT6_TX_Pos) /*!< 0x000003FF */
+#define USB_COUNT6_TX_COUNT6_TX USB_COUNT6_TX_COUNT6_TX_Msk /*!< Transmission Byte Count 6 */
+
+/***************** Bit definition for USB_COUNT7_TX register ****************/
+#define USB_COUNT7_TX_COUNT7_TX_Pos (0U)
+#define USB_COUNT7_TX_COUNT7_TX_Msk (0x3FFU << USB_COUNT7_TX_COUNT7_TX_Pos) /*!< 0x000003FF */
+#define USB_COUNT7_TX_COUNT7_TX USB_COUNT7_TX_COUNT7_TX_Msk /*!< Transmission Byte Count 7 */
+
+/*----------------------------------------------------------------------------*/
+
+/**************** Bit definition for USB_COUNT0_TX_0 register ***************/
+#define USB_COUNT0_TX_0_COUNT0_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 0 (low) */
+
+/**************** Bit definition for USB_COUNT0_TX_1 register ***************/
+#define USB_COUNT0_TX_1_COUNT0_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 0 (high) */
+
+/**************** Bit definition for USB_COUNT1_TX_0 register ***************/
+#define USB_COUNT1_TX_0_COUNT1_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 1 (low) */
+
+/**************** Bit definition for USB_COUNT1_TX_1 register ***************/
+#define USB_COUNT1_TX_1_COUNT1_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 1 (high) */
+
+/**************** Bit definition for USB_COUNT2_TX_0 register ***************/
+#define USB_COUNT2_TX_0_COUNT2_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 2 (low) */
+
+/**************** Bit definition for USB_COUNT2_TX_1 register ***************/
+#define USB_COUNT2_TX_1_COUNT2_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 2 (high) */
+
+/**************** Bit definition for USB_COUNT3_TX_0 register ***************/
+#define USB_COUNT3_TX_0_COUNT3_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 3 (low) */
+
+/**************** Bit definition for USB_COUNT3_TX_1 register ***************/
+#define USB_COUNT3_TX_1_COUNT3_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 3 (high) */
+
+/**************** Bit definition for USB_COUNT4_TX_0 register ***************/
+#define USB_COUNT4_TX_0_COUNT4_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 4 (low) */
+
+/**************** Bit definition for USB_COUNT4_TX_1 register ***************/
+#define USB_COUNT4_TX_1_COUNT4_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 4 (high) */
+
+/**************** Bit definition for USB_COUNT5_TX_0 register ***************/
+#define USB_COUNT5_TX_0_COUNT5_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 5 (low) */
+
+/**************** Bit definition for USB_COUNT5_TX_1 register ***************/
+#define USB_COUNT5_TX_1_COUNT5_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 5 (high) */
+
+/**************** Bit definition for USB_COUNT6_TX_0 register ***************/
+#define USB_COUNT6_TX_0_COUNT6_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 6 (low) */
+
+/**************** Bit definition for USB_COUNT6_TX_1 register ***************/
+#define USB_COUNT6_TX_1_COUNT6_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 6 (high) */
+
+/**************** Bit definition for USB_COUNT7_TX_0 register ***************/
+#define USB_COUNT7_TX_0_COUNT7_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 7 (low) */
+
+/**************** Bit definition for USB_COUNT7_TX_1 register ***************/
+#define USB_COUNT7_TX_1_COUNT7_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 7 (high) */
+
+/*----------------------------------------------------------------------------*/
+
+/***************** Bit definition for USB_ADDR0_RX register *****************/
+#define USB_ADDR0_RX_ADDR0_RX_Pos (1U)
+#define USB_ADDR0_RX_ADDR0_RX_Msk (0x7FFFU << USB_ADDR0_RX_ADDR0_RX_Pos) /*!< 0x0000FFFE */
+#define USB_ADDR0_RX_ADDR0_RX USB_ADDR0_RX_ADDR0_RX_Msk /*!< Reception Buffer Address 0 */
+
+/***************** Bit definition for USB_ADDR1_RX register *****************/
+#define USB_ADDR1_RX_ADDR1_RX_Pos (1U)
+#define USB_ADDR1_RX_ADDR1_RX_Msk (0x7FFFU << USB_ADDR1_RX_ADDR1_RX_Pos) /*!< 0x0000FFFE */
+#define USB_ADDR1_RX_ADDR1_RX USB_ADDR1_RX_ADDR1_RX_Msk /*!< Reception Buffer Address 1 */
+
+/***************** Bit definition for USB_ADDR2_RX register *****************/
+#define USB_ADDR2_RX_ADDR2_RX_Pos (1U)
+#define USB_ADDR2_RX_ADDR2_RX_Msk (0x7FFFU << USB_ADDR2_RX_ADDR2_RX_Pos) /*!< 0x0000FFFE */
+#define USB_ADDR2_RX_ADDR2_RX USB_ADDR2_RX_ADDR2_RX_Msk /*!< Reception Buffer Address 2 */
+
+/***************** Bit definition for USB_ADDR3_RX register *****************/
+#define USB_ADDR3_RX_ADDR3_RX_Pos (1U)
+#define USB_ADDR3_RX_ADDR3_RX_Msk (0x7FFFU << USB_ADDR3_RX_ADDR3_RX_Pos) /*!< 0x0000FFFE */
+#define USB_ADDR3_RX_ADDR3_RX USB_ADDR3_RX_ADDR3_RX_Msk /*!< Reception Buffer Address 3 */
+
+/***************** Bit definition for USB_ADDR4_RX register *****************/
+#define USB_ADDR4_RX_ADDR4_RX_Pos (1U)
+#define USB_ADDR4_RX_ADDR4_RX_Msk (0x7FFFU << USB_ADDR4_RX_ADDR4_RX_Pos) /*!< 0x0000FFFE */
+#define USB_ADDR4_RX_ADDR4_RX USB_ADDR4_RX_ADDR4_RX_Msk /*!< Reception Buffer Address 4 */
+
+/***************** Bit definition for USB_ADDR5_RX register *****************/
+#define USB_ADDR5_RX_ADDR5_RX_Pos (1U)
+#define USB_ADDR5_RX_ADDR5_RX_Msk (0x7FFFU << USB_ADDR5_RX_ADDR5_RX_Pos) /*!< 0x0000FFFE */
+#define USB_ADDR5_RX_ADDR5_RX USB_ADDR5_RX_ADDR5_RX_Msk /*!< Reception Buffer Address 5 */
+
+/***************** Bit definition for USB_ADDR6_RX register *****************/
+#define USB_ADDR6_RX_ADDR6_RX_Pos (1U)
+#define USB_ADDR6_RX_ADDR6_RX_Msk (0x7FFFU << USB_ADDR6_RX_ADDR6_RX_Pos) /*!< 0x0000FFFE */
+#define USB_ADDR6_RX_ADDR6_RX USB_ADDR6_RX_ADDR6_RX_Msk /*!< Reception Buffer Address 6 */
+
+/***************** Bit definition for USB_ADDR7_RX register *****************/
+#define USB_ADDR7_RX_ADDR7_RX_Pos (1U)
+#define USB_ADDR7_RX_ADDR7_RX_Msk (0x7FFFU << USB_ADDR7_RX_ADDR7_RX_Pos) /*!< 0x0000FFFE */
+#define USB_ADDR7_RX_ADDR7_RX USB_ADDR7_RX_ADDR7_RX_Msk /*!< Reception Buffer Address 7 */
+
+/*----------------------------------------------------------------------------*/
+
+/***************** Bit definition for USB_COUNT0_RX register ****************/
+#define USB_COUNT0_RX_COUNT0_RX_Pos (0U)
+#define USB_COUNT0_RX_COUNT0_RX_Msk (0x3FFU << USB_COUNT0_RX_COUNT0_RX_Pos) /*!< 0x000003FF */
+#define USB_COUNT0_RX_COUNT0_RX USB_COUNT0_RX_COUNT0_RX_Msk /*!< Reception Byte Count */
+
+#define USB_COUNT0_RX_NUM_BLOCK_Pos (10U)
+#define USB_COUNT0_RX_NUM_BLOCK_Msk (0x1FU << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
+#define USB_COUNT0_RX_NUM_BLOCK USB_COUNT0_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
+#define USB_COUNT0_RX_NUM_BLOCK_0 (0x01U << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
+#define USB_COUNT0_RX_NUM_BLOCK_1 (0x02U << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
+#define USB_COUNT0_RX_NUM_BLOCK_2 (0x04U << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
+#define USB_COUNT0_RX_NUM_BLOCK_3 (0x08U << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
+#define USB_COUNT0_RX_NUM_BLOCK_4 (0x10U << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
+
+#define USB_COUNT0_RX_BLSIZE_Pos (15U)
+#define USB_COUNT0_RX_BLSIZE_Msk (0x1U << USB_COUNT0_RX_BLSIZE_Pos) /*!< 0x00008000 */
+#define USB_COUNT0_RX_BLSIZE USB_COUNT0_RX_BLSIZE_Msk /*!< BLock SIZE */
+
+/***************** Bit definition for USB_COUNT1_RX register ****************/
+#define USB_COUNT1_RX_COUNT1_RX_Pos (0U)
+#define USB_COUNT1_RX_COUNT1_RX_Msk (0x3FFU << USB_COUNT1_RX_COUNT1_RX_Pos) /*!< 0x000003FF */
+#define USB_COUNT1_RX_COUNT1_RX USB_COUNT1_RX_COUNT1_RX_Msk /*!< Reception Byte Count */
+
+#define USB_COUNT1_RX_NUM_BLOCK_Pos (10U)
+#define USB_COUNT1_RX_NUM_BLOCK_Msk (0x1FU << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
+#define USB_COUNT1_RX_NUM_BLOCK USB_COUNT1_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
+#define USB_COUNT1_RX_NUM_BLOCK_0 (0x01U << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
+#define USB_COUNT1_RX_NUM_BLOCK_1 (0x02U << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
+#define USB_COUNT1_RX_NUM_BLOCK_2 (0x04U << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
+#define USB_COUNT1_RX_NUM_BLOCK_3 (0x08U << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
+#define USB_COUNT1_RX_NUM_BLOCK_4 (0x10U << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
+
+#define USB_COUNT1_RX_BLSIZE_Pos (15U)
+#define USB_COUNT1_RX_BLSIZE_Msk (0x1U << USB_COUNT1_RX_BLSIZE_Pos) /*!< 0x00008000 */
+#define USB_COUNT1_RX_BLSIZE USB_COUNT1_RX_BLSIZE_Msk /*!< BLock SIZE */
+
+/***************** Bit definition for USB_COUNT2_RX register ****************/
+#define USB_COUNT2_RX_COUNT2_RX_Pos (0U)
+#define USB_COUNT2_RX_COUNT2_RX_Msk (0x3FFU << USB_COUNT2_RX_COUNT2_RX_Pos) /*!< 0x000003FF */
+#define USB_COUNT2_RX_COUNT2_RX USB_COUNT2_RX_COUNT2_RX_Msk /*!< Reception Byte Count */
+
+#define USB_COUNT2_RX_NUM_BLOCK_Pos (10U)
+#define USB_COUNT2_RX_NUM_BLOCK_Msk (0x1FU << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
+#define USB_COUNT2_RX_NUM_BLOCK USB_COUNT2_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
+#define USB_COUNT2_RX_NUM_BLOCK_0 (0x01U << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
+#define USB_COUNT2_RX_NUM_BLOCK_1 (0x02U << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
+#define USB_COUNT2_RX_NUM_BLOCK_2 (0x04U << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
+#define USB_COUNT2_RX_NUM_BLOCK_3 (0x08U << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
+#define USB_COUNT2_RX_NUM_BLOCK_4 (0x10U << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
+
+#define USB_COUNT2_RX_BLSIZE_Pos (15U)
+#define USB_COUNT2_RX_BLSIZE_Msk (0x1U << USB_COUNT2_RX_BLSIZE_Pos) /*!< 0x00008000 */
+#define USB_COUNT2_RX_BLSIZE USB_COUNT2_RX_BLSIZE_Msk /*!< BLock SIZE */
+
+/***************** Bit definition for USB_COUNT3_RX register ****************/
+#define USB_COUNT3_RX_COUNT3_RX_Pos (0U)
+#define USB_COUNT3_RX_COUNT3_RX_Msk (0x3FFU << USB_COUNT3_RX_COUNT3_RX_Pos) /*!< 0x000003FF */
+#define USB_COUNT3_RX_COUNT3_RX USB_COUNT3_RX_COUNT3_RX_Msk /*!< Reception Byte Count */
+
+#define USB_COUNT3_RX_NUM_BLOCK_Pos (10U)
+#define USB_COUNT3_RX_NUM_BLOCK_Msk (0x1FU << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
+#define USB_COUNT3_RX_NUM_BLOCK USB_COUNT3_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
+#define USB_COUNT3_RX_NUM_BLOCK_0 (0x01U << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
+#define USB_COUNT3_RX_NUM_BLOCK_1 (0x02U << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
+#define USB_COUNT3_RX_NUM_BLOCK_2 (0x04U << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
+#define USB_COUNT3_RX_NUM_BLOCK_3 (0x08U << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
+#define USB_COUNT3_RX_NUM_BLOCK_4 (0x10U << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
+
+#define USB_COUNT3_RX_BLSIZE_Pos (15U)
+#define USB_COUNT3_RX_BLSIZE_Msk (0x1U << USB_COUNT3_RX_BLSIZE_Pos) /*!< 0x00008000 */
+#define USB_COUNT3_RX_BLSIZE USB_COUNT3_RX_BLSIZE_Msk /*!< BLock SIZE */
+
+/***************** Bit definition for USB_COUNT4_RX register ****************/
+#define USB_COUNT4_RX_COUNT4_RX_Pos (0U)
+#define USB_COUNT4_RX_COUNT4_RX_Msk (0x3FFU << USB_COUNT4_RX_COUNT4_RX_Pos) /*!< 0x000003FF */
+#define USB_COUNT4_RX_COUNT4_RX USB_COUNT4_RX_COUNT4_RX_Msk /*!< Reception Byte Count */
+
+#define USB_COUNT4_RX_NUM_BLOCK_Pos (10U)
+#define USB_COUNT4_RX_NUM_BLOCK_Msk (0x1FU << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
+#define USB_COUNT4_RX_NUM_BLOCK USB_COUNT4_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
+#define USB_COUNT4_RX_NUM_BLOCK_0 (0x01U << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
+#define USB_COUNT4_RX_NUM_BLOCK_1 (0x02U << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
+#define USB_COUNT4_RX_NUM_BLOCK_2 (0x04U << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
+#define USB_COUNT4_RX_NUM_BLOCK_3 (0x08U << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
+#define USB_COUNT4_RX_NUM_BLOCK_4 (0x10U << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
+
+#define USB_COUNT4_RX_BLSIZE_Pos (15U)
+#define USB_COUNT4_RX_BLSIZE_Msk (0x1U << USB_COUNT4_RX_BLSIZE_Pos) /*!< 0x00008000 */
+#define USB_COUNT4_RX_BLSIZE USB_COUNT4_RX_BLSIZE_Msk /*!< BLock SIZE */
+
+/***************** Bit definition for USB_COUNT5_RX register ****************/
+#define USB_COUNT5_RX_COUNT5_RX_Pos (0U)
+#define USB_COUNT5_RX_COUNT5_RX_Msk (0x3FFU << USB_COUNT5_RX_COUNT5_RX_Pos) /*!< 0x000003FF */
+#define USB_COUNT5_RX_COUNT5_RX USB_COUNT5_RX_COUNT5_RX_Msk /*!< Reception Byte Count */
+
+#define USB_COUNT5_RX_NUM_BLOCK_Pos (10U)
+#define USB_COUNT5_RX_NUM_BLOCK_Msk (0x1FU << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
+#define USB_COUNT5_RX_NUM_BLOCK USB_COUNT5_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
+#define USB_COUNT5_RX_NUM_BLOCK_0 (0x01U << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
+#define USB_COUNT5_RX_NUM_BLOCK_1 (0x02U << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
+#define USB_COUNT5_RX_NUM_BLOCK_2 (0x04U << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
+#define USB_COUNT5_RX_NUM_BLOCK_3 (0x08U << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
+#define USB_COUNT5_RX_NUM_BLOCK_4 (0x10U << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
+
+#define USB_COUNT5_RX_BLSIZE_Pos (15U)
+#define USB_COUNT5_RX_BLSIZE_Msk (0x1U << USB_COUNT5_RX_BLSIZE_Pos) /*!< 0x00008000 */
+#define USB_COUNT5_RX_BLSIZE USB_COUNT5_RX_BLSIZE_Msk /*!< BLock SIZE */
+
+/***************** Bit definition for USB_COUNT6_RX register ****************/
+#define USB_COUNT6_RX_COUNT6_RX_Pos (0U)
+#define USB_COUNT6_RX_COUNT6_RX_Msk (0x3FFU << USB_COUNT6_RX_COUNT6_RX_Pos) /*!< 0x000003FF */
+#define USB_COUNT6_RX_COUNT6_RX USB_COUNT6_RX_COUNT6_RX_Msk /*!< Reception Byte Count */
+
+#define USB_COUNT6_RX_NUM_BLOCK_Pos (10U)
+#define USB_COUNT6_RX_NUM_BLOCK_Msk (0x1FU << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
+#define USB_COUNT6_RX_NUM_BLOCK USB_COUNT6_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
+#define USB_COUNT6_RX_NUM_BLOCK_0 (0x01U << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
+#define USB_COUNT6_RX_NUM_BLOCK_1 (0x02U << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
+#define USB_COUNT6_RX_NUM_BLOCK_2 (0x04U << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
+#define USB_COUNT6_RX_NUM_BLOCK_3 (0x08U << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
+#define USB_COUNT6_RX_NUM_BLOCK_4 (0x10U << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
+
+#define USB_COUNT6_RX_BLSIZE_Pos (15U)
+#define USB_COUNT6_RX_BLSIZE_Msk (0x1U << USB_COUNT6_RX_BLSIZE_Pos) /*!< 0x00008000 */
+#define USB_COUNT6_RX_BLSIZE USB_COUNT6_RX_BLSIZE_Msk /*!< BLock SIZE */
+
+/***************** Bit definition for USB_COUNT7_RX register ****************/
+#define USB_COUNT7_RX_COUNT7_RX_Pos (0U)
+#define USB_COUNT7_RX_COUNT7_RX_Msk (0x3FFU << USB_COUNT7_RX_COUNT7_RX_Pos) /*!< 0x000003FF */
+#define USB_COUNT7_RX_COUNT7_RX USB_COUNT7_RX_COUNT7_RX_Msk /*!< Reception Byte Count */
+
+#define USB_COUNT7_RX_NUM_BLOCK_Pos (10U)
+#define USB_COUNT7_RX_NUM_BLOCK_Msk (0x1FU << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
+#define USB_COUNT7_RX_NUM_BLOCK USB_COUNT7_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
+#define USB_COUNT7_RX_NUM_BLOCK_0 (0x01U << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
+#define USB_COUNT7_RX_NUM_BLOCK_1 (0x02U << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
+#define USB_COUNT7_RX_NUM_BLOCK_2 (0x04U << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
+#define USB_COUNT7_RX_NUM_BLOCK_3 (0x08U << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
+#define USB_COUNT7_RX_NUM_BLOCK_4 (0x10U << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
+
+#define USB_COUNT7_RX_BLSIZE_Pos (15U)
+#define USB_COUNT7_RX_BLSIZE_Msk (0x1U << USB_COUNT7_RX_BLSIZE_Pos) /*!< 0x00008000 */
+#define USB_COUNT7_RX_BLSIZE USB_COUNT7_RX_BLSIZE_Msk /*!< BLock SIZE */
+
+/*----------------------------------------------------------------------------*/
+
+/**************** Bit definition for USB_COUNT0_RX_0 register ***************/
+#define USB_COUNT0_RX_0_COUNT0_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */
+
+#define USB_COUNT0_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
+#define USB_COUNT0_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */
+#define USB_COUNT0_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */
+#define USB_COUNT0_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */
+#define USB_COUNT0_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */
+#define USB_COUNT0_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */
+
+#define USB_COUNT0_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */
+
+/**************** Bit definition for USB_COUNT0_RX_1 register ***************/
+#define USB_COUNT0_RX_1_COUNT0_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */
+
+#define USB_COUNT0_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
+#define USB_COUNT0_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 1 */
+#define USB_COUNT0_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */
+#define USB_COUNT0_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */
+#define USB_COUNT0_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */
+#define USB_COUNT0_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */
+
+#define USB_COUNT0_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */
+
+/**************** Bit definition for USB_COUNT1_RX_0 register ***************/
+#define USB_COUNT1_RX_0_COUNT1_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */
+
+#define USB_COUNT1_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
+#define USB_COUNT1_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */
+#define USB_COUNT1_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */
+#define USB_COUNT1_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */
+#define USB_COUNT1_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */
+#define USB_COUNT1_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */
+
+#define USB_COUNT1_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */
+
+/**************** Bit definition for USB_COUNT1_RX_1 register ***************/
+#define USB_COUNT1_RX_1_COUNT1_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */
+
+#define USB_COUNT1_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
+#define USB_COUNT1_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */
+#define USB_COUNT1_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */
+#define USB_COUNT1_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */
+#define USB_COUNT1_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */
+#define USB_COUNT1_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */
+
+#define USB_COUNT1_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */
+
+/**************** Bit definition for USB_COUNT2_RX_0 register ***************/
+#define USB_COUNT2_RX_0_COUNT2_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */
+
+#define USB_COUNT2_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
+#define USB_COUNT2_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */
+#define USB_COUNT2_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */
+#define USB_COUNT2_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */
+#define USB_COUNT2_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */
+#define USB_COUNT2_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */
+
+#define USB_COUNT2_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */
+
+/**************** Bit definition for USB_COUNT2_RX_1 register ***************/
+#define USB_COUNT2_RX_1_COUNT2_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */
+
+#define USB_COUNT2_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
+#define USB_COUNT2_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */
+#define USB_COUNT2_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */
+#define USB_COUNT2_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */
+#define USB_COUNT2_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */
+#define USB_COUNT2_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */
+
+#define USB_COUNT2_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */
+
+/**************** Bit definition for USB_COUNT3_RX_0 register ***************/
+#define USB_COUNT3_RX_0_COUNT3_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */
+
+#define USB_COUNT3_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
+#define USB_COUNT3_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */
+#define USB_COUNT3_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */
+#define USB_COUNT3_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */
+#define USB_COUNT3_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */
+#define USB_COUNT3_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */
+
+#define USB_COUNT3_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */
+
+/**************** Bit definition for USB_COUNT3_RX_1 register ***************/
+#define USB_COUNT3_RX_1_COUNT3_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */
+
+#define USB_COUNT3_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
+#define USB_COUNT3_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */
+#define USB_COUNT3_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */
+#define USB_COUNT3_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */
+#define USB_COUNT3_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */
+#define USB_COUNT3_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */
+
+#define USB_COUNT3_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */
+
+/**************** Bit definition for USB_COUNT4_RX_0 register ***************/
+#define USB_COUNT4_RX_0_COUNT4_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */
+
+#define USB_COUNT4_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
+#define USB_COUNT4_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */
+#define USB_COUNT4_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */
+#define USB_COUNT4_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */
+#define USB_COUNT4_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */
+#define USB_COUNT4_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */
+
+#define USB_COUNT4_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */
+
+/**************** Bit definition for USB_COUNT4_RX_1 register ***************/
+#define USB_COUNT4_RX_1_COUNT4_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */
+
+#define USB_COUNT4_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
+#define USB_COUNT4_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */
+#define USB_COUNT4_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */
+#define USB_COUNT4_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */
+#define USB_COUNT4_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */
+#define USB_COUNT4_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */
+
+#define USB_COUNT4_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */
+
+/**************** Bit definition for USB_COUNT5_RX_0 register ***************/
+#define USB_COUNT5_RX_0_COUNT5_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */
+
+#define USB_COUNT5_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
+#define USB_COUNT5_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */
+#define USB_COUNT5_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */
+#define USB_COUNT5_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */
+#define USB_COUNT5_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */
+#define USB_COUNT5_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */
+
+#define USB_COUNT5_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */
+
+/**************** Bit definition for USB_COUNT5_RX_1 register ***************/
+#define USB_COUNT5_RX_1_COUNT5_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */
+
+#define USB_COUNT5_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
+#define USB_COUNT5_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */
+#define USB_COUNT5_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */
+#define USB_COUNT5_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */
+#define USB_COUNT5_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */
+#define USB_COUNT5_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */
+
+#define USB_COUNT5_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */
+
+/*************** Bit definition for USB_COUNT6_RX_0 register ***************/
+#define USB_COUNT6_RX_0_COUNT6_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */
+
+#define USB_COUNT6_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
+#define USB_COUNT6_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */
+#define USB_COUNT6_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */
+#define USB_COUNT6_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */
+#define USB_COUNT6_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */
+#define USB_COUNT6_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */
+
+#define USB_COUNT6_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */
+
+/**************** Bit definition for USB_COUNT6_RX_1 register ***************/
+#define USB_COUNT6_RX_1_COUNT6_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */
+
+#define USB_COUNT6_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
+#define USB_COUNT6_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */
+#define USB_COUNT6_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */
+#define USB_COUNT6_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */
+#define USB_COUNT6_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */
+#define USB_COUNT6_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */
+
+#define USB_COUNT6_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */
+
+/*************** Bit definition for USB_COUNT7_RX_0 register ****************/
+#define USB_COUNT7_RX_0_COUNT7_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */
+
+#define USB_COUNT7_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
+#define USB_COUNT7_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */
+#define USB_COUNT7_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */
+#define USB_COUNT7_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */
+#define USB_COUNT7_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */
+#define USB_COUNT7_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */
+
+#define USB_COUNT7_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */
+
+/*************** Bit definition for USB_COUNT7_RX_1 register ****************/
+#define USB_COUNT7_RX_1_COUNT7_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */
+
+#define USB_COUNT7_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
+#define USB_COUNT7_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */
+#define USB_COUNT7_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */
+#define USB_COUNT7_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */
+#define USB_COUNT7_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */
+#define USB_COUNT7_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */
+
+#define USB_COUNT7_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */
+
+/******************************************************************************/
+/* */
+/* Controller Area Network */
+/* */
+/******************************************************************************/
+
+/*!< CAN control and status registers */
+/******************* Bit definition for CAN_MCR register ********************/
+#define CAN_MCR_INRQ_Pos (0U)
+#define CAN_MCR_INRQ_Msk (0x1U << CAN_MCR_INRQ_Pos) /*!< 0x00000001 */
+#define CAN_MCR_INRQ CAN_MCR_INRQ_Msk /*!< Initialization Request */
+#define CAN_MCR_SLEEP_Pos (1U)
+#define CAN_MCR_SLEEP_Msk (0x1U << CAN_MCR_SLEEP_Pos) /*!< 0x00000002 */
+#define CAN_MCR_SLEEP CAN_MCR_SLEEP_Msk /*!< Sleep Mode Request */
+#define CAN_MCR_TXFP_Pos (2U)
+#define CAN_MCR_TXFP_Msk (0x1U << CAN_MCR_TXFP_Pos) /*!< 0x00000004 */
+#define CAN_MCR_TXFP CAN_MCR_TXFP_Msk /*!< Transmit FIFO Priority */
+#define CAN_MCR_RFLM_Pos (3U)
+#define CAN_MCR_RFLM_Msk (0x1U << CAN_MCR_RFLM_Pos) /*!< 0x00000008 */
+#define CAN_MCR_RFLM CAN_MCR_RFLM_Msk /*!< Receive FIFO Locked Mode */
+#define CAN_MCR_NART_Pos (4U)
+#define CAN_MCR_NART_Msk (0x1U << CAN_MCR_NART_Pos) /*!< 0x00000010 */
+#define CAN_MCR_NART CAN_MCR_NART_Msk /*!< No Automatic Retransmission */
+#define CAN_MCR_AWUM_Pos (5U)
+#define CAN_MCR_AWUM_Msk (0x1U << CAN_MCR_AWUM_Pos) /*!< 0x00000020 */
+#define CAN_MCR_AWUM CAN_MCR_AWUM_Msk /*!< Automatic Wakeup Mode */
+#define CAN_MCR_ABOM_Pos (6U)
+#define CAN_MCR_ABOM_Msk (0x1U << CAN_MCR_ABOM_Pos) /*!< 0x00000040 */
+#define CAN_MCR_ABOM CAN_MCR_ABOM_Msk /*!< Automatic Bus-Off Management */
+#define CAN_MCR_TTCM_Pos (7U)
+#define CAN_MCR_TTCM_Msk (0x1U << CAN_MCR_TTCM_Pos) /*!< 0x00000080 */
+#define CAN_MCR_TTCM CAN_MCR_TTCM_Msk /*!< Time Triggered Communication Mode */
+#define CAN_MCR_RESET_Pos (15U)
+#define CAN_MCR_RESET_Msk (0x1U << CAN_MCR_RESET_Pos) /*!< 0x00008000 */
+#define CAN_MCR_RESET CAN_MCR_RESET_Msk /*!< CAN software master reset */
+#define CAN_MCR_DBF_Pos (16U)
+#define CAN_MCR_DBF_Msk (0x1U << CAN_MCR_DBF_Pos) /*!< 0x00010000 */
+#define CAN_MCR_DBF CAN_MCR_DBF_Msk /*!< CAN Debug freeze */
+
+/******************* Bit definition for CAN_MSR register ********************/
+#define CAN_MSR_INAK_Pos (0U)
+#define CAN_MSR_INAK_Msk (0x1U << CAN_MSR_INAK_Pos) /*!< 0x00000001 */
+#define CAN_MSR_INAK CAN_MSR_INAK_Msk /*!< Initialization Acknowledge */
+#define CAN_MSR_SLAK_Pos (1U)
+#define CAN_MSR_SLAK_Msk (0x1U << CAN_MSR_SLAK_Pos) /*!< 0x00000002 */
+#define CAN_MSR_SLAK CAN_MSR_SLAK_Msk /*!< Sleep Acknowledge */
+#define CAN_MSR_ERRI_Pos (2U)
+#define CAN_MSR_ERRI_Msk (0x1U << CAN_MSR_ERRI_Pos) /*!< 0x00000004 */
+#define CAN_MSR_ERRI CAN_MSR_ERRI_Msk /*!< Error Interrupt */
+#define CAN_MSR_WKUI_Pos (3U)
+#define CAN_MSR_WKUI_Msk (0x1U << CAN_MSR_WKUI_Pos) /*!< 0x00000008 */
+#define CAN_MSR_WKUI CAN_MSR_WKUI_Msk /*!< Wakeup Interrupt */
+#define CAN_MSR_SLAKI_Pos (4U)
+#define CAN_MSR_SLAKI_Msk (0x1U << CAN_MSR_SLAKI_Pos) /*!< 0x00000010 */
+#define CAN_MSR_SLAKI CAN_MSR_SLAKI_Msk /*!< Sleep Acknowledge Interrupt */
+#define CAN_MSR_TXM_Pos (8U)
+#define CAN_MSR_TXM_Msk (0x1U << CAN_MSR_TXM_Pos) /*!< 0x00000100 */
+#define CAN_MSR_TXM CAN_MSR_TXM_Msk /*!< Transmit Mode */
+#define CAN_MSR_RXM_Pos (9U)
+#define CAN_MSR_RXM_Msk (0x1U << CAN_MSR_RXM_Pos) /*!< 0x00000200 */
+#define CAN_MSR_RXM CAN_MSR_RXM_Msk /*!< Receive Mode */
+#define CAN_MSR_SAMP_Pos (10U)
+#define CAN_MSR_SAMP_Msk (0x1U << CAN_MSR_SAMP_Pos) /*!< 0x00000400 */
+#define CAN_MSR_SAMP CAN_MSR_SAMP_Msk /*!< Last Sample Point */
+#define CAN_MSR_RX_Pos (11U)
+#define CAN_MSR_RX_Msk (0x1U << CAN_MSR_RX_Pos) /*!< 0x00000800 */
+#define CAN_MSR_RX CAN_MSR_RX_Msk /*!< CAN Rx Signal */
+
+/******************* Bit definition for CAN_TSR register ********************/
+#define CAN_TSR_RQCP0_Pos (0U)
+#define CAN_TSR_RQCP0_Msk (0x1U << CAN_TSR_RQCP0_Pos) /*!< 0x00000001 */
+#define CAN_TSR_RQCP0 CAN_TSR_RQCP0_Msk /*!< Request Completed Mailbox0 */
+#define CAN_TSR_TXOK0_Pos (1U)
+#define CAN_TSR_TXOK0_Msk (0x1U << CAN_TSR_TXOK0_Pos) /*!< 0x00000002 */
+#define CAN_TSR_TXOK0 CAN_TSR_TXOK0_Msk /*!< Transmission OK of Mailbox0 */
+#define CAN_TSR_ALST0_Pos (2U)
+#define CAN_TSR_ALST0_Msk (0x1U << CAN_TSR_ALST0_Pos) /*!< 0x00000004 */
+#define CAN_TSR_ALST0 CAN_TSR_ALST0_Msk /*!< Arbitration Lost for Mailbox0 */
+#define CAN_TSR_TERR0_Pos (3U)
+#define CAN_TSR_TERR0_Msk (0x1U << CAN_TSR_TERR0_Pos) /*!< 0x00000008 */
+#define CAN_TSR_TERR0 CAN_TSR_TERR0_Msk /*!< Transmission Error of Mailbox0 */
+#define CAN_TSR_ABRQ0_Pos (7U)
+#define CAN_TSR_ABRQ0_Msk (0x1U << CAN_TSR_ABRQ0_Pos) /*!< 0x00000080 */
+#define CAN_TSR_ABRQ0 CAN_TSR_ABRQ0_Msk /*!< Abort Request for Mailbox0 */
+#define CAN_TSR_RQCP1_Pos (8U)
+#define CAN_TSR_RQCP1_Msk (0x1U << CAN_TSR_RQCP1_Pos) /*!< 0x00000100 */
+#define CAN_TSR_RQCP1 CAN_TSR_RQCP1_Msk /*!< Request Completed Mailbox1 */
+#define CAN_TSR_TXOK1_Pos (9U)
+#define CAN_TSR_TXOK1_Msk (0x1U << CAN_TSR_TXOK1_Pos) /*!< 0x00000200 */
+#define CAN_TSR_TXOK1 CAN_TSR_TXOK1_Msk /*!< Transmission OK of Mailbox1 */
+#define CAN_TSR_ALST1_Pos (10U)
+#define CAN_TSR_ALST1_Msk (0x1U << CAN_TSR_ALST1_Pos) /*!< 0x00000400 */
+#define CAN_TSR_ALST1 CAN_TSR_ALST1_Msk /*!< Arbitration Lost for Mailbox1 */
+#define CAN_TSR_TERR1_Pos (11U)
+#define CAN_TSR_TERR1_Msk (0x1U << CAN_TSR_TERR1_Pos) /*!< 0x00000800 */
+#define CAN_TSR_TERR1 CAN_TSR_TERR1_Msk /*!< Transmission Error of Mailbox1 */
+#define CAN_TSR_ABRQ1_Pos (15U)
+#define CAN_TSR_ABRQ1_Msk (0x1U << CAN_TSR_ABRQ1_Pos) /*!< 0x00008000 */
+#define CAN_TSR_ABRQ1 CAN_TSR_ABRQ1_Msk /*!< Abort Request for Mailbox 1 */
+#define CAN_TSR_RQCP2_Pos (16U)
+#define CAN_TSR_RQCP2_Msk (0x1U << CAN_TSR_RQCP2_Pos) /*!< 0x00010000 */
+#define CAN_TSR_RQCP2 CAN_TSR_RQCP2_Msk /*!< Request Completed Mailbox2 */
+#define CAN_TSR_TXOK2_Pos (17U)
+#define CAN_TSR_TXOK2_Msk (0x1U << CAN_TSR_TXOK2_Pos) /*!< 0x00020000 */
+#define CAN_TSR_TXOK2 CAN_TSR_TXOK2_Msk /*!< Transmission OK of Mailbox 2 */
+#define CAN_TSR_ALST2_Pos (18U)
+#define CAN_TSR_ALST2_Msk (0x1U << CAN_TSR_ALST2_Pos) /*!< 0x00040000 */
+#define CAN_TSR_ALST2 CAN_TSR_ALST2_Msk /*!< Arbitration Lost for mailbox 2 */
+#define CAN_TSR_TERR2_Pos (19U)
+#define CAN_TSR_TERR2_Msk (0x1U << CAN_TSR_TERR2_Pos) /*!< 0x00080000 */
+#define CAN_TSR_TERR2 CAN_TSR_TERR2_Msk /*!< Transmission Error of Mailbox 2 */
+#define CAN_TSR_ABRQ2_Pos (23U)
+#define CAN_TSR_ABRQ2_Msk (0x1U << CAN_TSR_ABRQ2_Pos) /*!< 0x00800000 */
+#define CAN_TSR_ABRQ2 CAN_TSR_ABRQ2_Msk /*!< Abort Request for Mailbox 2 */
+#define CAN_TSR_CODE_Pos (24U)
+#define CAN_TSR_CODE_Msk (0x3U << CAN_TSR_CODE_Pos) /*!< 0x03000000 */
+#define CAN_TSR_CODE CAN_TSR_CODE_Msk /*!< Mailbox Code */
+
+#define CAN_TSR_TME_Pos (26U)
+#define CAN_TSR_TME_Msk (0x7U << CAN_TSR_TME_Pos) /*!< 0x1C000000 */
+#define CAN_TSR_TME CAN_TSR_TME_Msk /*!< TME[2:0] bits */
+#define CAN_TSR_TME0_Pos (26U)
+#define CAN_TSR_TME0_Msk (0x1U << CAN_TSR_TME0_Pos) /*!< 0x04000000 */
+#define CAN_TSR_TME0 CAN_TSR_TME0_Msk /*!< Transmit Mailbox 0 Empty */
+#define CAN_TSR_TME1_Pos (27U)
+#define CAN_TSR_TME1_Msk (0x1U << CAN_TSR_TME1_Pos) /*!< 0x08000000 */
+#define CAN_TSR_TME1 CAN_TSR_TME1_Msk /*!< Transmit Mailbox 1 Empty */
+#define CAN_TSR_TME2_Pos (28U)
+#define CAN_TSR_TME2_Msk (0x1U << CAN_TSR_TME2_Pos) /*!< 0x10000000 */
+#define CAN_TSR_TME2 CAN_TSR_TME2_Msk /*!< Transmit Mailbox 2 Empty */
+
+#define CAN_TSR_LOW_Pos (29U)
+#define CAN_TSR_LOW_Msk (0x7U << CAN_TSR_LOW_Pos) /*!< 0xE0000000 */
+#define CAN_TSR_LOW CAN_TSR_LOW_Msk /*!< LOW[2:0] bits */
+#define CAN_TSR_LOW0_Pos (29U)
+#define CAN_TSR_LOW0_Msk (0x1U << CAN_TSR_LOW0_Pos) /*!< 0x20000000 */
+#define CAN_TSR_LOW0 CAN_TSR_LOW0_Msk /*!< Lowest Priority Flag for Mailbox 0 */
+#define CAN_TSR_LOW1_Pos (30U)
+#define CAN_TSR_LOW1_Msk (0x1U << CAN_TSR_LOW1_Pos) /*!< 0x40000000 */
+#define CAN_TSR_LOW1 CAN_TSR_LOW1_Msk /*!< Lowest Priority Flag for Mailbox 1 */
+#define CAN_TSR_LOW2_Pos (31U)
+#define CAN_TSR_LOW2_Msk (0x1U << CAN_TSR_LOW2_Pos) /*!< 0x80000000 */
+#define CAN_TSR_LOW2 CAN_TSR_LOW2_Msk /*!< Lowest Priority Flag for Mailbox 2 */
+
+/******************* Bit definition for CAN_RF0R register *******************/
+#define CAN_RF0R_FMP0_Pos (0U)
+#define CAN_RF0R_FMP0_Msk (0x3U << CAN_RF0R_FMP0_Pos) /*!< 0x00000003 */
+#define CAN_RF0R_FMP0 CAN_RF0R_FMP0_Msk /*!< FIFO 0 Message Pending */
+#define CAN_RF0R_FULL0_Pos (3U)
+#define CAN_RF0R_FULL0_Msk (0x1U << CAN_RF0R_FULL0_Pos) /*!< 0x00000008 */
+#define CAN_RF0R_FULL0 CAN_RF0R_FULL0_Msk /*!< FIFO 0 Full */
+#define CAN_RF0R_FOVR0_Pos (4U)
+#define CAN_RF0R_FOVR0_Msk (0x1U << CAN_RF0R_FOVR0_Pos) /*!< 0x00000010 */
+#define CAN_RF0R_FOVR0 CAN_RF0R_FOVR0_Msk /*!< FIFO 0 Overrun */
+#define CAN_RF0R_RFOM0_Pos (5U)
+#define CAN_RF0R_RFOM0_Msk (0x1U << CAN_RF0R_RFOM0_Pos) /*!< 0x00000020 */
+#define CAN_RF0R_RFOM0 CAN_RF0R_RFOM0_Msk /*!< Release FIFO 0 Output Mailbox */
+
+/******************* Bit definition for CAN_RF1R register *******************/
+#define CAN_RF1R_FMP1_Pos (0U)
+#define CAN_RF1R_FMP1_Msk (0x3U << CAN_RF1R_FMP1_Pos) /*!< 0x00000003 */
+#define CAN_RF1R_FMP1 CAN_RF1R_FMP1_Msk /*!< FIFO 1 Message Pending */
+#define CAN_RF1R_FULL1_Pos (3U)
+#define CAN_RF1R_FULL1_Msk (0x1U << CAN_RF1R_FULL1_Pos) /*!< 0x00000008 */
+#define CAN_RF1R_FULL1 CAN_RF1R_FULL1_Msk /*!< FIFO 1 Full */
+#define CAN_RF1R_FOVR1_Pos (4U)
+#define CAN_RF1R_FOVR1_Msk (0x1U << CAN_RF1R_FOVR1_Pos) /*!< 0x00000010 */
+#define CAN_RF1R_FOVR1 CAN_RF1R_FOVR1_Msk /*!< FIFO 1 Overrun */
+#define CAN_RF1R_RFOM1_Pos (5U)
+#define CAN_RF1R_RFOM1_Msk (0x1U << CAN_RF1R_RFOM1_Pos) /*!< 0x00000020 */
+#define CAN_RF1R_RFOM1 CAN_RF1R_RFOM1_Msk /*!< Release FIFO 1 Output Mailbox */
+
+/******************** Bit definition for CAN_IER register *******************/
+#define CAN_IER_TMEIE_Pos (0U)
+#define CAN_IER_TMEIE_Msk (0x1U << CAN_IER_TMEIE_Pos) /*!< 0x00000001 */
+#define CAN_IER_TMEIE CAN_IER_TMEIE_Msk /*!< Transmit Mailbox Empty Interrupt Enable */
+#define CAN_IER_FMPIE0_Pos (1U)
+#define CAN_IER_FMPIE0_Msk (0x1U << CAN_IER_FMPIE0_Pos) /*!< 0x00000002 */
+#define CAN_IER_FMPIE0 CAN_IER_FMPIE0_Msk /*!< FIFO Message Pending Interrupt Enable */
+#define CAN_IER_FFIE0_Pos (2U)
+#define CAN_IER_FFIE0_Msk (0x1U << CAN_IER_FFIE0_Pos) /*!< 0x00000004 */
+#define CAN_IER_FFIE0 CAN_IER_FFIE0_Msk /*!< FIFO Full Interrupt Enable */
+#define CAN_IER_FOVIE0_Pos (3U)
+#define CAN_IER_FOVIE0_Msk (0x1U << CAN_IER_FOVIE0_Pos) /*!< 0x00000008 */
+#define CAN_IER_FOVIE0 CAN_IER_FOVIE0_Msk /*!< FIFO Overrun Interrupt Enable */
+#define CAN_IER_FMPIE1_Pos (4U)
+#define CAN_IER_FMPIE1_Msk (0x1U << CAN_IER_FMPIE1_Pos) /*!< 0x00000010 */
+#define CAN_IER_FMPIE1 CAN_IER_FMPIE1_Msk /*!< FIFO Message Pending Interrupt Enable */
+#define CAN_IER_FFIE1_Pos (5U)
+#define CAN_IER_FFIE1_Msk (0x1U << CAN_IER_FFIE1_Pos) /*!< 0x00000020 */
+#define CAN_IER_FFIE1 CAN_IER_FFIE1_Msk /*!< FIFO Full Interrupt Enable */
+#define CAN_IER_FOVIE1_Pos (6U)
+#define CAN_IER_FOVIE1_Msk (0x1U << CAN_IER_FOVIE1_Pos) /*!< 0x00000040 */
+#define CAN_IER_FOVIE1 CAN_IER_FOVIE1_Msk /*!< FIFO Overrun Interrupt Enable */
+#define CAN_IER_EWGIE_Pos (8U)
+#define CAN_IER_EWGIE_Msk (0x1U << CAN_IER_EWGIE_Pos) /*!< 0x00000100 */
+#define CAN_IER_EWGIE CAN_IER_EWGIE_Msk /*!< Error Warning Interrupt Enable */
+#define CAN_IER_EPVIE_Pos (9U)
+#define CAN_IER_EPVIE_Msk (0x1U << CAN_IER_EPVIE_Pos) /*!< 0x00000200 */
+#define CAN_IER_EPVIE CAN_IER_EPVIE_Msk /*!< Error Passive Interrupt Enable */
+#define CAN_IER_BOFIE_Pos (10U)
+#define CAN_IER_BOFIE_Msk (0x1U << CAN_IER_BOFIE_Pos) /*!< 0x00000400 */
+#define CAN_IER_BOFIE CAN_IER_BOFIE_Msk /*!< Bus-Off Interrupt Enable */
+#define CAN_IER_LECIE_Pos (11U)
+#define CAN_IER_LECIE_Msk (0x1U << CAN_IER_LECIE_Pos) /*!< 0x00000800 */
+#define CAN_IER_LECIE CAN_IER_LECIE_Msk /*!< Last Error Code Interrupt Enable */
+#define CAN_IER_ERRIE_Pos (15U)
+#define CAN_IER_ERRIE_Msk (0x1U << CAN_IER_ERRIE_Pos) /*!< 0x00008000 */
+#define CAN_IER_ERRIE CAN_IER_ERRIE_Msk /*!< Error Interrupt Enable */
+#define CAN_IER_WKUIE_Pos (16U)
+#define CAN_IER_WKUIE_Msk (0x1U << CAN_IER_WKUIE_Pos) /*!< 0x00010000 */
+#define CAN_IER_WKUIE CAN_IER_WKUIE_Msk /*!< Wakeup Interrupt Enable */
+#define CAN_IER_SLKIE_Pos (17U)
+#define CAN_IER_SLKIE_Msk (0x1U << CAN_IER_SLKIE_Pos) /*!< 0x00020000 */
+#define CAN_IER_SLKIE CAN_IER_SLKIE_Msk /*!< Sleep Interrupt Enable */
+
+/******************** Bit definition for CAN_ESR register *******************/
+#define CAN_ESR_EWGF_Pos (0U)
+#define CAN_ESR_EWGF_Msk (0x1U << CAN_ESR_EWGF_Pos) /*!< 0x00000001 */
+#define CAN_ESR_EWGF CAN_ESR_EWGF_Msk /*!< Error Warning Flag */
+#define CAN_ESR_EPVF_Pos (1U)
+#define CAN_ESR_EPVF_Msk (0x1U << CAN_ESR_EPVF_Pos) /*!< 0x00000002 */
+#define CAN_ESR_EPVF CAN_ESR_EPVF_Msk /*!< Error Passive Flag */
+#define CAN_ESR_BOFF_Pos (2U)
+#define CAN_ESR_BOFF_Msk (0x1U << CAN_ESR_BOFF_Pos) /*!< 0x00000004 */
+#define CAN_ESR_BOFF CAN_ESR_BOFF_Msk /*!< Bus-Off Flag */
+
+#define CAN_ESR_LEC_Pos (4U)
+#define CAN_ESR_LEC_Msk (0x7U << CAN_ESR_LEC_Pos) /*!< 0x00000070 */
+#define CAN_ESR_LEC CAN_ESR_LEC_Msk /*!< LEC[2:0] bits (Last Error Code) */
+#define CAN_ESR_LEC_0 (0x1U << CAN_ESR_LEC_Pos) /*!< 0x00000010 */
+#define CAN_ESR_LEC_1 (0x2U << CAN_ESR_LEC_Pos) /*!< 0x00000020 */
+#define CAN_ESR_LEC_2 (0x4U << CAN_ESR_LEC_Pos) /*!< 0x00000040 */
+
+#define CAN_ESR_TEC_Pos (16U)
+#define CAN_ESR_TEC_Msk (0xFFU << CAN_ESR_TEC_Pos) /*!< 0x00FF0000 */
+#define CAN_ESR_TEC CAN_ESR_TEC_Msk /*!< Least significant byte of the 9-bit Transmit Error Counter */
+#define CAN_ESR_REC_Pos (24U)
+#define CAN_ESR_REC_Msk (0xFFU << CAN_ESR_REC_Pos) /*!< 0xFF000000 */
+#define CAN_ESR_REC CAN_ESR_REC_Msk /*!< Receive Error Counter */
+
+/******************* Bit definition for CAN_BTR register ********************/
+#define CAN_BTR_BRP_Pos (0U)
+#define CAN_BTR_BRP_Msk (0x3FFU << CAN_BTR_BRP_Pos) /*!< 0x000003FF */
+#define CAN_BTR_BRP CAN_BTR_BRP_Msk /*!<Baud Rate Prescaler */
+#define CAN_BTR_TS1_Pos (16U)
+#define CAN_BTR_TS1_Msk (0xFU << CAN_BTR_TS1_Pos) /*!< 0x000F0000 */
+#define CAN_BTR_TS1 CAN_BTR_TS1_Msk /*!<Time Segment 1 */
+#define CAN_BTR_TS1_0 (0x1U << CAN_BTR_TS1_Pos) /*!< 0x00010000 */
+#define CAN_BTR_TS1_1 (0x2U << CAN_BTR_TS1_Pos) /*!< 0x00020000 */
+#define CAN_BTR_TS1_2 (0x4U << CAN_BTR_TS1_Pos) /*!< 0x00040000 */
+#define CAN_BTR_TS1_3 (0x8U << CAN_BTR_TS1_Pos) /*!< 0x00080000 */
+#define CAN_BTR_TS2_Pos (20U)
+#define CAN_BTR_TS2_Msk (0x7U << CAN_BTR_TS2_Pos) /*!< 0x00700000 */
+#define CAN_BTR_TS2 CAN_BTR_TS2_Msk /*!<Time Segment 2 */
+#define CAN_BTR_TS2_0 (0x1U << CAN_BTR_TS2_Pos) /*!< 0x00100000 */
+#define CAN_BTR_TS2_1 (0x2U << CAN_BTR_TS2_Pos) /*!< 0x00200000 */
+#define CAN_BTR_TS2_2 (0x4U << CAN_BTR_TS2_Pos) /*!< 0x00400000 */
+#define CAN_BTR_SJW_Pos (24U)
+#define CAN_BTR_SJW_Msk (0x3U << CAN_BTR_SJW_Pos) /*!< 0x03000000 */
+#define CAN_BTR_SJW CAN_BTR_SJW_Msk /*!<Resynchronization Jump Width */
+#define CAN_BTR_SJW_0 (0x1U << CAN_BTR_SJW_Pos) /*!< 0x01000000 */
+#define CAN_BTR_SJW_1 (0x2U << CAN_BTR_SJW_Pos) /*!< 0x02000000 */
+#define CAN_BTR_LBKM_Pos (30U)
+#define CAN_BTR_LBKM_Msk (0x1U << CAN_BTR_LBKM_Pos) /*!< 0x40000000 */
+#define CAN_BTR_LBKM CAN_BTR_LBKM_Msk /*!<Loop Back Mode (Debug) */
+#define CAN_BTR_SILM_Pos (31U)
+#define CAN_BTR_SILM_Msk (0x1U << CAN_BTR_SILM_Pos) /*!< 0x80000000 */
+#define CAN_BTR_SILM CAN_BTR_SILM_Msk /*!<Silent Mode */
+
+/*!< Mailbox registers */
+/****************** Bit definition for CAN_TI0R register ********************/
+#define CAN_TI0R_TXRQ_Pos (0U)
+#define CAN_TI0R_TXRQ_Msk (0x1U << CAN_TI0R_TXRQ_Pos) /*!< 0x00000001 */
+#define CAN_TI0R_TXRQ CAN_TI0R_TXRQ_Msk /*!< Transmit Mailbox Request */
+#define CAN_TI0R_RTR_Pos (1U)
+#define CAN_TI0R_RTR_Msk (0x1U << CAN_TI0R_RTR_Pos) /*!< 0x00000002 */
+#define CAN_TI0R_RTR CAN_TI0R_RTR_Msk /*!< Remote Transmission Request */
+#define CAN_TI0R_IDE_Pos (2U)
+#define CAN_TI0R_IDE_Msk (0x1U << CAN_TI0R_IDE_Pos) /*!< 0x00000004 */
+#define CAN_TI0R_IDE CAN_TI0R_IDE_Msk /*!< Identifier Extension */
+#define CAN_TI0R_EXID_Pos (3U)
+#define CAN_TI0R_EXID_Msk (0x3FFFFU << CAN_TI0R_EXID_Pos) /*!< 0x001FFFF8 */
+#define CAN_TI0R_EXID CAN_TI0R_EXID_Msk /*!< Extended Identifier */
+#define CAN_TI0R_STID_Pos (21U)
+#define CAN_TI0R_STID_Msk (0x7FFU << CAN_TI0R_STID_Pos) /*!< 0xFFE00000 */
+#define CAN_TI0R_STID CAN_TI0R_STID_Msk /*!< Standard Identifier or Extended Identifier */
+
+/****************** Bit definition for CAN_TDT0R register *******************/
+#define CAN_TDT0R_DLC_Pos (0U)
+#define CAN_TDT0R_DLC_Msk (0xFU << CAN_TDT0R_DLC_Pos) /*!< 0x0000000F */
+#define CAN_TDT0R_DLC CAN_TDT0R_DLC_Msk /*!< Data Length Code */
+#define CAN_TDT0R_TGT_Pos (8U)
+#define CAN_TDT0R_TGT_Msk (0x1U << CAN_TDT0R_TGT_Pos) /*!< 0x00000100 */
+#define CAN_TDT0R_TGT CAN_TDT0R_TGT_Msk /*!< Transmit Global Time */
+#define CAN_TDT0R_TIME_Pos (16U)
+#define CAN_TDT0R_TIME_Msk (0xFFFFU << CAN_TDT0R_TIME_Pos) /*!< 0xFFFF0000 */
+#define CAN_TDT0R_TIME CAN_TDT0R_TIME_Msk /*!< Message Time Stamp */
+
+/****************** Bit definition for CAN_TDL0R register *******************/
+#define CAN_TDL0R_DATA0_Pos (0U)
+#define CAN_TDL0R_DATA0_Msk (0xFFU << CAN_TDL0R_DATA0_Pos) /*!< 0x000000FF */
+#define CAN_TDL0R_DATA0 CAN_TDL0R_DATA0_Msk /*!< Data byte 0 */
+#define CAN_TDL0R_DATA1_Pos (8U)
+#define CAN_TDL0R_DATA1_Msk (0xFFU << CAN_TDL0R_DATA1_Pos) /*!< 0x0000FF00 */
+#define CAN_TDL0R_DATA1 CAN_TDL0R_DATA1_Msk /*!< Data byte 1 */
+#define CAN_TDL0R_DATA2_Pos (16U)
+#define CAN_TDL0R_DATA2_Msk (0xFFU << CAN_TDL0R_DATA2_Pos) /*!< 0x00FF0000 */
+#define CAN_TDL0R_DATA2 CAN_TDL0R_DATA2_Msk /*!< Data byte 2 */
+#define CAN_TDL0R_DATA3_Pos (24U)
+#define CAN_TDL0R_DATA3_Msk (0xFFU << CAN_TDL0R_DATA3_Pos) /*!< 0xFF000000 */
+#define CAN_TDL0R_DATA3 CAN_TDL0R_DATA3_Msk /*!< Data byte 3 */
+
+/****************** Bit definition for CAN_TDH0R register *******************/
+#define CAN_TDH0R_DATA4_Pos (0U)
+#define CAN_TDH0R_DATA4_Msk (0xFFU << CAN_TDH0R_DATA4_Pos) /*!< 0x000000FF */
+#define CAN_TDH0R_DATA4 CAN_TDH0R_DATA4_Msk /*!< Data byte 4 */
+#define CAN_TDH0R_DATA5_Pos (8U)
+#define CAN_TDH0R_DATA5_Msk (0xFFU << CAN_TDH0R_DATA5_Pos) /*!< 0x0000FF00 */
+#define CAN_TDH0R_DATA5 CAN_TDH0R_DATA5_Msk /*!< Data byte 5 */
+#define CAN_TDH0R_DATA6_Pos (16U)
+#define CAN_TDH0R_DATA6_Msk (0xFFU << CAN_TDH0R_DATA6_Pos) /*!< 0x00FF0000 */
+#define CAN_TDH0R_DATA6 CAN_TDH0R_DATA6_Msk /*!< Data byte 6 */
+#define CAN_TDH0R_DATA7_Pos (24U)
+#define CAN_TDH0R_DATA7_Msk (0xFFU << CAN_TDH0R_DATA7_Pos) /*!< 0xFF000000 */
+#define CAN_TDH0R_DATA7 CAN_TDH0R_DATA7_Msk /*!< Data byte 7 */
+
+/******************* Bit definition for CAN_TI1R register *******************/
+#define CAN_TI1R_TXRQ_Pos (0U)
+#define CAN_TI1R_TXRQ_Msk (0x1U << CAN_TI1R_TXRQ_Pos) /*!< 0x00000001 */
+#define CAN_TI1R_TXRQ CAN_TI1R_TXRQ_Msk /*!< Transmit Mailbox Request */
+#define CAN_TI1R_RTR_Pos (1U)
+#define CAN_TI1R_RTR_Msk (0x1U << CAN_TI1R_RTR_Pos) /*!< 0x00000002 */
+#define CAN_TI1R_RTR CAN_TI1R_RTR_Msk /*!< Remote Transmission Request */
+#define CAN_TI1R_IDE_Pos (2U)
+#define CAN_TI1R_IDE_Msk (0x1U << CAN_TI1R_IDE_Pos) /*!< 0x00000004 */
+#define CAN_TI1R_IDE CAN_TI1R_IDE_Msk /*!< Identifier Extension */
+#define CAN_TI1R_EXID_Pos (3U)
+#define CAN_TI1R_EXID_Msk (0x3FFFFU << CAN_TI1R_EXID_Pos) /*!< 0x001FFFF8 */
+#define CAN_TI1R_EXID CAN_TI1R_EXID_Msk /*!< Extended Identifier */
+#define CAN_TI1R_STID_Pos (21U)
+#define CAN_TI1R_STID_Msk (0x7FFU << CAN_TI1R_STID_Pos) /*!< 0xFFE00000 */
+#define CAN_TI1R_STID CAN_TI1R_STID_Msk /*!< Standard Identifier or Extended Identifier */
+
+/******************* Bit definition for CAN_TDT1R register ******************/
+#define CAN_TDT1R_DLC_Pos (0U)
+#define CAN_TDT1R_DLC_Msk (0xFU << CAN_TDT1R_DLC_Pos) /*!< 0x0000000F */
+#define CAN_TDT1R_DLC CAN_TDT1R_DLC_Msk /*!< Data Length Code */
+#define CAN_TDT1R_TGT_Pos (8U)
+#define CAN_TDT1R_TGT_Msk (0x1U << CAN_TDT1R_TGT_Pos) /*!< 0x00000100 */
+#define CAN_TDT1R_TGT CAN_TDT1R_TGT_Msk /*!< Transmit Global Time */
+#define CAN_TDT1R_TIME_Pos (16U)
+#define CAN_TDT1R_TIME_Msk (0xFFFFU << CAN_TDT1R_TIME_Pos) /*!< 0xFFFF0000 */
+#define CAN_TDT1R_TIME CAN_TDT1R_TIME_Msk /*!< Message Time Stamp */
+
+/******************* Bit definition for CAN_TDL1R register ******************/
+#define CAN_TDL1R_DATA0_Pos (0U)
+#define CAN_TDL1R_DATA0_Msk (0xFFU << CAN_TDL1R_DATA0_Pos) /*!< 0x000000FF */
+#define CAN_TDL1R_DATA0 CAN_TDL1R_DATA0_Msk /*!< Data byte 0 */
+#define CAN_TDL1R_DATA1_Pos (8U)
+#define CAN_TDL1R_DATA1_Msk (0xFFU << CAN_TDL1R_DATA1_Pos) /*!< 0x0000FF00 */
+#define CAN_TDL1R_DATA1 CAN_TDL1R_DATA1_Msk /*!< Data byte 1 */
+#define CAN_TDL1R_DATA2_Pos (16U)
+#define CAN_TDL1R_DATA2_Msk (0xFFU << CAN_TDL1R_DATA2_Pos) /*!< 0x00FF0000 */
+#define CAN_TDL1R_DATA2 CAN_TDL1R_DATA2_Msk /*!< Data byte 2 */
+#define CAN_TDL1R_DATA3_Pos (24U)
+#define CAN_TDL1R_DATA3_Msk (0xFFU << CAN_TDL1R_DATA3_Pos) /*!< 0xFF000000 */
+#define CAN_TDL1R_DATA3 CAN_TDL1R_DATA3_Msk /*!< Data byte 3 */
+
+/******************* Bit definition for CAN_TDH1R register ******************/
+#define CAN_TDH1R_DATA4_Pos (0U)
+#define CAN_TDH1R_DATA4_Msk (0xFFU << CAN_TDH1R_DATA4_Pos) /*!< 0x000000FF */
+#define CAN_TDH1R_DATA4 CAN_TDH1R_DATA4_Msk /*!< Data byte 4 */
+#define CAN_TDH1R_DATA5_Pos (8U)
+#define CAN_TDH1R_DATA5_Msk (0xFFU << CAN_TDH1R_DATA5_Pos) /*!< 0x0000FF00 */
+#define CAN_TDH1R_DATA5 CAN_TDH1R_DATA5_Msk /*!< Data byte 5 */
+#define CAN_TDH1R_DATA6_Pos (16U)
+#define CAN_TDH1R_DATA6_Msk (0xFFU << CAN_TDH1R_DATA6_Pos) /*!< 0x00FF0000 */
+#define CAN_TDH1R_DATA6 CAN_TDH1R_DATA6_Msk /*!< Data byte 6 */
+#define CAN_TDH1R_DATA7_Pos (24U)
+#define CAN_TDH1R_DATA7_Msk (0xFFU << CAN_TDH1R_DATA7_Pos) /*!< 0xFF000000 */
+#define CAN_TDH1R_DATA7 CAN_TDH1R_DATA7_Msk /*!< Data byte 7 */
+
+/******************* Bit definition for CAN_TI2R register *******************/
+#define CAN_TI2R_TXRQ_Pos (0U)
+#define CAN_TI2R_TXRQ_Msk (0x1U << CAN_TI2R_TXRQ_Pos) /*!< 0x00000001 */
+#define CAN_TI2R_TXRQ CAN_TI2R_TXRQ_Msk /*!< Transmit Mailbox Request */
+#define CAN_TI2R_RTR_Pos (1U)
+#define CAN_TI2R_RTR_Msk (0x1U << CAN_TI2R_RTR_Pos) /*!< 0x00000002 */
+#define CAN_TI2R_RTR CAN_TI2R_RTR_Msk /*!< Remote Transmission Request */
+#define CAN_TI2R_IDE_Pos (2U)
+#define CAN_TI2R_IDE_Msk (0x1U << CAN_TI2R_IDE_Pos) /*!< 0x00000004 */
+#define CAN_TI2R_IDE CAN_TI2R_IDE_Msk /*!< Identifier Extension */
+#define CAN_TI2R_EXID_Pos (3U)
+#define CAN_TI2R_EXID_Msk (0x3FFFFU << CAN_TI2R_EXID_Pos) /*!< 0x001FFFF8 */
+#define CAN_TI2R_EXID CAN_TI2R_EXID_Msk /*!< Extended identifier */
+#define CAN_TI2R_STID_Pos (21U)
+#define CAN_TI2R_STID_Msk (0x7FFU << CAN_TI2R_STID_Pos) /*!< 0xFFE00000 */
+#define CAN_TI2R_STID CAN_TI2R_STID_Msk /*!< Standard Identifier or Extended Identifier */
+
+/******************* Bit definition for CAN_TDT2R register ******************/
+#define CAN_TDT2R_DLC_Pos (0U)
+#define CAN_TDT2R_DLC_Msk (0xFU << CAN_TDT2R_DLC_Pos) /*!< 0x0000000F */
+#define CAN_TDT2R_DLC CAN_TDT2R_DLC_Msk /*!< Data Length Code */
+#define CAN_TDT2R_TGT_Pos (8U)
+#define CAN_TDT2R_TGT_Msk (0x1U << CAN_TDT2R_TGT_Pos) /*!< 0x00000100 */
+#define CAN_TDT2R_TGT CAN_TDT2R_TGT_Msk /*!< Transmit Global Time */
+#define CAN_TDT2R_TIME_Pos (16U)
+#define CAN_TDT2R_TIME_Msk (0xFFFFU << CAN_TDT2R_TIME_Pos) /*!< 0xFFFF0000 */
+#define CAN_TDT2R_TIME CAN_TDT2R_TIME_Msk /*!< Message Time Stamp */
+
+/******************* Bit definition for CAN_TDL2R register ******************/
+#define CAN_TDL2R_DATA0_Pos (0U)
+#define CAN_TDL2R_DATA0_Msk (0xFFU << CAN_TDL2R_DATA0_Pos) /*!< 0x000000FF */
+#define CAN_TDL2R_DATA0 CAN_TDL2R_DATA0_Msk /*!< Data byte 0 */
+#define CAN_TDL2R_DATA1_Pos (8U)
+#define CAN_TDL2R_DATA1_Msk (0xFFU << CAN_TDL2R_DATA1_Pos) /*!< 0x0000FF00 */
+#define CAN_TDL2R_DATA1 CAN_TDL2R_DATA1_Msk /*!< Data byte 1 */
+#define CAN_TDL2R_DATA2_Pos (16U)
+#define CAN_TDL2R_DATA2_Msk (0xFFU << CAN_TDL2R_DATA2_Pos) /*!< 0x00FF0000 */
+#define CAN_TDL2R_DATA2 CAN_TDL2R_DATA2_Msk /*!< Data byte 2 */
+#define CAN_TDL2R_DATA3_Pos (24U)
+#define CAN_TDL2R_DATA3_Msk (0xFFU << CAN_TDL2R_DATA3_Pos) /*!< 0xFF000000 */
+#define CAN_TDL2R_DATA3 CAN_TDL2R_DATA3_Msk /*!< Data byte 3 */
+
+/******************* Bit definition for CAN_TDH2R register ******************/
+#define CAN_TDH2R_DATA4_Pos (0U)
+#define CAN_TDH2R_DATA4_Msk (0xFFU << CAN_TDH2R_DATA4_Pos) /*!< 0x000000FF */
+#define CAN_TDH2R_DATA4 CAN_TDH2R_DATA4_Msk /*!< Data byte 4 */
+#define CAN_TDH2R_DATA5_Pos (8U)
+#define CAN_TDH2R_DATA5_Msk (0xFFU << CAN_TDH2R_DATA5_Pos) /*!< 0x0000FF00 */
+#define CAN_TDH2R_DATA5 CAN_TDH2R_DATA5_Msk /*!< Data byte 5 */
+#define CAN_TDH2R_DATA6_Pos (16U)
+#define CAN_TDH2R_DATA6_Msk (0xFFU << CAN_TDH2R_DATA6_Pos) /*!< 0x00FF0000 */
+#define CAN_TDH2R_DATA6 CAN_TDH2R_DATA6_Msk /*!< Data byte 6 */
+#define CAN_TDH2R_DATA7_Pos (24U)
+#define CAN_TDH2R_DATA7_Msk (0xFFU << CAN_TDH2R_DATA7_Pos) /*!< 0xFF000000 */
+#define CAN_TDH2R_DATA7 CAN_TDH2R_DATA7_Msk /*!< Data byte 7 */
+
+/******************* Bit definition for CAN_RI0R register *******************/
+#define CAN_RI0R_RTR_Pos (1U)
+#define CAN_RI0R_RTR_Msk (0x1U << CAN_RI0R_RTR_Pos) /*!< 0x00000002 */
+#define CAN_RI0R_RTR CAN_RI0R_RTR_Msk /*!< Remote Transmission Request */
+#define CAN_RI0R_IDE_Pos (2U)
+#define CAN_RI0R_IDE_Msk (0x1U << CAN_RI0R_IDE_Pos) /*!< 0x00000004 */
+#define CAN_RI0R_IDE CAN_RI0R_IDE_Msk /*!< Identifier Extension */
+#define CAN_RI0R_EXID_Pos (3U)
+#define CAN_RI0R_EXID_Msk (0x3FFFFU << CAN_RI0R_EXID_Pos) /*!< 0x001FFFF8 */
+#define CAN_RI0R_EXID CAN_RI0R_EXID_Msk /*!< Extended Identifier */
+#define CAN_RI0R_STID_Pos (21U)
+#define CAN_RI0R_STID_Msk (0x7FFU << CAN_RI0R_STID_Pos) /*!< 0xFFE00000 */
+#define CAN_RI0R_STID CAN_RI0R_STID_Msk /*!< Standard Identifier or Extended Identifier */
+
+/******************* Bit definition for CAN_RDT0R register ******************/
+#define CAN_RDT0R_DLC_Pos (0U)
+#define CAN_RDT0R_DLC_Msk (0xFU << CAN_RDT0R_DLC_Pos) /*!< 0x0000000F */
+#define CAN_RDT0R_DLC CAN_RDT0R_DLC_Msk /*!< Data Length Code */
+#define CAN_RDT0R_FMI_Pos (8U)
+#define CAN_RDT0R_FMI_Msk (0xFFU << CAN_RDT0R_FMI_Pos) /*!< 0x0000FF00 */
+#define CAN_RDT0R_FMI CAN_RDT0R_FMI_Msk /*!< Filter Match Index */
+#define CAN_RDT0R_TIME_Pos (16U)
+#define CAN_RDT0R_TIME_Msk (0xFFFFU << CAN_RDT0R_TIME_Pos) /*!< 0xFFFF0000 */
+#define CAN_RDT0R_TIME CAN_RDT0R_TIME_Msk /*!< Message Time Stamp */
+
+/******************* Bit definition for CAN_RDL0R register ******************/
+#define CAN_RDL0R_DATA0_Pos (0U)
+#define CAN_RDL0R_DATA0_Msk (0xFFU << CAN_RDL0R_DATA0_Pos) /*!< 0x000000FF */
+#define CAN_RDL0R_DATA0 CAN_RDL0R_DATA0_Msk /*!< Data byte 0 */
+#define CAN_RDL0R_DATA1_Pos (8U)
+#define CAN_RDL0R_DATA1_Msk (0xFFU << CAN_RDL0R_DATA1_Pos) /*!< 0x0000FF00 */
+#define CAN_RDL0R_DATA1 CAN_RDL0R_DATA1_Msk /*!< Data byte 1 */
+#define CAN_RDL0R_DATA2_Pos (16U)
+#define CAN_RDL0R_DATA2_Msk (0xFFU << CAN_RDL0R_DATA2_Pos) /*!< 0x00FF0000 */
+#define CAN_RDL0R_DATA2 CAN_RDL0R_DATA2_Msk /*!< Data byte 2 */
+#define CAN_RDL0R_DATA3_Pos (24U)
+#define CAN_RDL0R_DATA3_Msk (0xFFU << CAN_RDL0R_DATA3_Pos) /*!< 0xFF000000 */
+#define CAN_RDL0R_DATA3 CAN_RDL0R_DATA3_Msk /*!< Data byte 3 */
+
+/******************* Bit definition for CAN_RDH0R register ******************/
+#define CAN_RDH0R_DATA4_Pos (0U)
+#define CAN_RDH0R_DATA4_Msk (0xFFU << CAN_RDH0R_DATA4_Pos) /*!< 0x000000FF */
+#define CAN_RDH0R_DATA4 CAN_RDH0R_DATA4_Msk /*!< Data byte 4 */
+#define CAN_RDH0R_DATA5_Pos (8U)
+#define CAN_RDH0R_DATA5_Msk (0xFFU << CAN_RDH0R_DATA5_Pos) /*!< 0x0000FF00 */
+#define CAN_RDH0R_DATA5 CAN_RDH0R_DATA5_Msk /*!< Data byte 5 */
+#define CAN_RDH0R_DATA6_Pos (16U)
+#define CAN_RDH0R_DATA6_Msk (0xFFU << CAN_RDH0R_DATA6_Pos) /*!< 0x00FF0000 */
+#define CAN_RDH0R_DATA6 CAN_RDH0R_DATA6_Msk /*!< Data byte 6 */
+#define CAN_RDH0R_DATA7_Pos (24U)
+#define CAN_RDH0R_DATA7_Msk (0xFFU << CAN_RDH0R_DATA7_Pos) /*!< 0xFF000000 */
+#define CAN_RDH0R_DATA7 CAN_RDH0R_DATA7_Msk /*!< Data byte 7 */
+
+/******************* Bit definition for CAN_RI1R register *******************/
+#define CAN_RI1R_RTR_Pos (1U)
+#define CAN_RI1R_RTR_Msk (0x1U << CAN_RI1R_RTR_Pos) /*!< 0x00000002 */
+#define CAN_RI1R_RTR CAN_RI1R_RTR_Msk /*!< Remote Transmission Request */
+#define CAN_RI1R_IDE_Pos (2U)
+#define CAN_RI1R_IDE_Msk (0x1U << CAN_RI1R_IDE_Pos) /*!< 0x00000004 */
+#define CAN_RI1R_IDE CAN_RI1R_IDE_Msk /*!< Identifier Extension */
+#define CAN_RI1R_EXID_Pos (3U)
+#define CAN_RI1R_EXID_Msk (0x3FFFFU << CAN_RI1R_EXID_Pos) /*!< 0x001FFFF8 */
+#define CAN_RI1R_EXID CAN_RI1R_EXID_Msk /*!< Extended identifier */
+#define CAN_RI1R_STID_Pos (21U)
+#define CAN_RI1R_STID_Msk (0x7FFU << CAN_RI1R_STID_Pos) /*!< 0xFFE00000 */
+#define CAN_RI1R_STID CAN_RI1R_STID_Msk /*!< Standard Identifier or Extended Identifier */
+
+/******************* Bit definition for CAN_RDT1R register ******************/
+#define CAN_RDT1R_DLC_Pos (0U)
+#define CAN_RDT1R_DLC_Msk (0xFU << CAN_RDT1R_DLC_Pos) /*!< 0x0000000F */
+#define CAN_RDT1R_DLC CAN_RDT1R_DLC_Msk /*!< Data Length Code */
+#define CAN_RDT1R_FMI_Pos (8U)
+#define CAN_RDT1R_FMI_Msk (0xFFU << CAN_RDT1R_FMI_Pos) /*!< 0x0000FF00 */
+#define CAN_RDT1R_FMI CAN_RDT1R_FMI_Msk /*!< Filter Match Index */
+#define CAN_RDT1R_TIME_Pos (16U)
+#define CAN_RDT1R_TIME_Msk (0xFFFFU << CAN_RDT1R_TIME_Pos) /*!< 0xFFFF0000 */
+#define CAN_RDT1R_TIME CAN_RDT1R_TIME_Msk /*!< Message Time Stamp */
+
+/******************* Bit definition for CAN_RDL1R register ******************/
+#define CAN_RDL1R_DATA0_Pos (0U)
+#define CAN_RDL1R_DATA0_Msk (0xFFU << CAN_RDL1R_DATA0_Pos) /*!< 0x000000FF */
+#define CAN_RDL1R_DATA0 CAN_RDL1R_DATA0_Msk /*!< Data byte 0 */
+#define CAN_RDL1R_DATA1_Pos (8U)
+#define CAN_RDL1R_DATA1_Msk (0xFFU << CAN_RDL1R_DATA1_Pos) /*!< 0x0000FF00 */
+#define CAN_RDL1R_DATA1 CAN_RDL1R_DATA1_Msk /*!< Data byte 1 */
+#define CAN_RDL1R_DATA2_Pos (16U)
+#define CAN_RDL1R_DATA2_Msk (0xFFU << CAN_RDL1R_DATA2_Pos) /*!< 0x00FF0000 */
+#define CAN_RDL1R_DATA2 CAN_RDL1R_DATA2_Msk /*!< Data byte 2 */
+#define CAN_RDL1R_DATA3_Pos (24U)
+#define CAN_RDL1R_DATA3_Msk (0xFFU << CAN_RDL1R_DATA3_Pos) /*!< 0xFF000000 */
+#define CAN_RDL1R_DATA3 CAN_RDL1R_DATA3_Msk /*!< Data byte 3 */
+
+/******************* Bit definition for CAN_RDH1R register ******************/
+#define CAN_RDH1R_DATA4_Pos (0U)
+#define CAN_RDH1R_DATA4_Msk (0xFFU << CAN_RDH1R_DATA4_Pos) /*!< 0x000000FF */
+#define CAN_RDH1R_DATA4 CAN_RDH1R_DATA4_Msk /*!< Data byte 4 */
+#define CAN_RDH1R_DATA5_Pos (8U)
+#define CAN_RDH1R_DATA5_Msk (0xFFU << CAN_RDH1R_DATA5_Pos) /*!< 0x0000FF00 */
+#define CAN_RDH1R_DATA5 CAN_RDH1R_DATA5_Msk /*!< Data byte 5 */
+#define CAN_RDH1R_DATA6_Pos (16U)
+#define CAN_RDH1R_DATA6_Msk (0xFFU << CAN_RDH1R_DATA6_Pos) /*!< 0x00FF0000 */
+#define CAN_RDH1R_DATA6 CAN_RDH1R_DATA6_Msk /*!< Data byte 6 */
+#define CAN_RDH1R_DATA7_Pos (24U)
+#define CAN_RDH1R_DATA7_Msk (0xFFU << CAN_RDH1R_DATA7_Pos) /*!< 0xFF000000 */
+#define CAN_RDH1R_DATA7 CAN_RDH1R_DATA7_Msk /*!< Data byte 7 */
+
+/*!< CAN filter registers */
+/******************* Bit definition for CAN_FMR register ********************/
+#define CAN_FMR_FINIT_Pos (0U)
+#define CAN_FMR_FINIT_Msk (0x1U << CAN_FMR_FINIT_Pos) /*!< 0x00000001 */
+#define CAN_FMR_FINIT CAN_FMR_FINIT_Msk /*!< Filter Init Mode */
+#define CAN_FMR_CAN2SB_Pos (8U)
+#define CAN_FMR_CAN2SB_Msk (0x3FU << CAN_FMR_CAN2SB_Pos) /*!< 0x00003F00 */
+#define CAN_FMR_CAN2SB CAN_FMR_CAN2SB_Msk /*!< CAN2 start bank */
+
+/******************* Bit definition for CAN_FM1R register *******************/
+#define CAN_FM1R_FBM_Pos (0U)
+#define CAN_FM1R_FBM_Msk (0x3FFFU << CAN_FM1R_FBM_Pos) /*!< 0x00003FFF */
+#define CAN_FM1R_FBM CAN_FM1R_FBM_Msk /*!< Filter Mode */
+#define CAN_FM1R_FBM0_Pos (0U)
+#define CAN_FM1R_FBM0_Msk (0x1U << CAN_FM1R_FBM0_Pos) /*!< 0x00000001 */
+#define CAN_FM1R_FBM0 CAN_FM1R_FBM0_Msk /*!< Filter Init Mode for filter 0 */
+#define CAN_FM1R_FBM1_Pos (1U)
+#define CAN_FM1R_FBM1_Msk (0x1U << CAN_FM1R_FBM1_Pos) /*!< 0x00000002 */
+#define CAN_FM1R_FBM1 CAN_FM1R_FBM1_Msk /*!< Filter Init Mode for filter 1 */
+#define CAN_FM1R_FBM2_Pos (2U)
+#define CAN_FM1R_FBM2_Msk (0x1U << CAN_FM1R_FBM2_Pos) /*!< 0x00000004 */
+#define CAN_FM1R_FBM2 CAN_FM1R_FBM2_Msk /*!< Filter Init Mode for filter 2 */
+#define CAN_FM1R_FBM3_Pos (3U)
+#define CAN_FM1R_FBM3_Msk (0x1U << CAN_FM1R_FBM3_Pos) /*!< 0x00000008 */
+#define CAN_FM1R_FBM3 CAN_FM1R_FBM3_Msk /*!< Filter Init Mode for filter 3 */
+#define CAN_FM1R_FBM4_Pos (4U)
+#define CAN_FM1R_FBM4_Msk (0x1U << CAN_FM1R_FBM4_Pos) /*!< 0x00000010 */
+#define CAN_FM1R_FBM4 CAN_FM1R_FBM4_Msk /*!< Filter Init Mode for filter 4 */
+#define CAN_FM1R_FBM5_Pos (5U)
+#define CAN_FM1R_FBM5_Msk (0x1U << CAN_FM1R_FBM5_Pos) /*!< 0x00000020 */
+#define CAN_FM1R_FBM5 CAN_FM1R_FBM5_Msk /*!< Filter Init Mode for filter 5 */
+#define CAN_FM1R_FBM6_Pos (6U)
+#define CAN_FM1R_FBM6_Msk (0x1U << CAN_FM1R_FBM6_Pos) /*!< 0x00000040 */
+#define CAN_FM1R_FBM6 CAN_FM1R_FBM6_Msk /*!< Filter Init Mode for filter 6 */
+#define CAN_FM1R_FBM7_Pos (7U)
+#define CAN_FM1R_FBM7_Msk (0x1U << CAN_FM1R_FBM7_Pos) /*!< 0x00000080 */
+#define CAN_FM1R_FBM7 CAN_FM1R_FBM7_Msk /*!< Filter Init Mode for filter 7 */
+#define CAN_FM1R_FBM8_Pos (8U)
+#define CAN_FM1R_FBM8_Msk (0x1U << CAN_FM1R_FBM8_Pos) /*!< 0x00000100 */
+#define CAN_FM1R_FBM8 CAN_FM1R_FBM8_Msk /*!< Filter Init Mode for filter 8 */
+#define CAN_FM1R_FBM9_Pos (9U)
+#define CAN_FM1R_FBM9_Msk (0x1U << CAN_FM1R_FBM9_Pos) /*!< 0x00000200 */
+#define CAN_FM1R_FBM9 CAN_FM1R_FBM9_Msk /*!< Filter Init Mode for filter 9 */
+#define CAN_FM1R_FBM10_Pos (10U)
+#define CAN_FM1R_FBM10_Msk (0x1U << CAN_FM1R_FBM10_Pos) /*!< 0x00000400 */
+#define CAN_FM1R_FBM10 CAN_FM1R_FBM10_Msk /*!< Filter Init Mode for filter 10 */
+#define CAN_FM1R_FBM11_Pos (11U)
+#define CAN_FM1R_FBM11_Msk (0x1U << CAN_FM1R_FBM11_Pos) /*!< 0x00000800 */
+#define CAN_FM1R_FBM11 CAN_FM1R_FBM11_Msk /*!< Filter Init Mode for filter 11 */
+#define CAN_FM1R_FBM12_Pos (12U)
+#define CAN_FM1R_FBM12_Msk (0x1U << CAN_FM1R_FBM12_Pos) /*!< 0x00001000 */
+#define CAN_FM1R_FBM12 CAN_FM1R_FBM12_Msk /*!< Filter Init Mode for filter 12 */
+#define CAN_FM1R_FBM13_Pos (13U)
+#define CAN_FM1R_FBM13_Msk (0x1U << CAN_FM1R_FBM13_Pos) /*!< 0x00002000 */
+#define CAN_FM1R_FBM13 CAN_FM1R_FBM13_Msk /*!< Filter Init Mode for filter 13 */
+
+/******************* Bit definition for CAN_FS1R register *******************/
+#define CAN_FS1R_FSC_Pos (0U)
+#define CAN_FS1R_FSC_Msk (0x3FFFU << CAN_FS1R_FSC_Pos) /*!< 0x00003FFF */
+#define CAN_FS1R_FSC CAN_FS1R_FSC_Msk /*!< Filter Scale Configuration */
+#define CAN_FS1R_FSC0_Pos (0U)
+#define CAN_FS1R_FSC0_Msk (0x1U << CAN_FS1R_FSC0_Pos) /*!< 0x00000001 */
+#define CAN_FS1R_FSC0 CAN_FS1R_FSC0_Msk /*!< Filter Scale Configuration for filter 0 */
+#define CAN_FS1R_FSC1_Pos (1U)
+#define CAN_FS1R_FSC1_Msk (0x1U << CAN_FS1R_FSC1_Pos) /*!< 0x00000002 */
+#define CAN_FS1R_FSC1 CAN_FS1R_FSC1_Msk /*!< Filter Scale Configuration for filter 1 */
+#define CAN_FS1R_FSC2_Pos (2U)
+#define CAN_FS1R_FSC2_Msk (0x1U << CAN_FS1R_FSC2_Pos) /*!< 0x00000004 */
+#define CAN_FS1R_FSC2 CAN_FS1R_FSC2_Msk /*!< Filter Scale Configuration for filter 2 */
+#define CAN_FS1R_FSC3_Pos (3U)
+#define CAN_FS1R_FSC3_Msk (0x1U << CAN_FS1R_FSC3_Pos) /*!< 0x00000008 */
+#define CAN_FS1R_FSC3 CAN_FS1R_FSC3_Msk /*!< Filter Scale Configuration for filter 3 */
+#define CAN_FS1R_FSC4_Pos (4U)
+#define CAN_FS1R_FSC4_Msk (0x1U << CAN_FS1R_FSC4_Pos) /*!< 0x00000010 */
+#define CAN_FS1R_FSC4 CAN_FS1R_FSC4_Msk /*!< Filter Scale Configuration for filter 4 */
+#define CAN_FS1R_FSC5_Pos (5U)
+#define CAN_FS1R_FSC5_Msk (0x1U << CAN_FS1R_FSC5_Pos) /*!< 0x00000020 */
+#define CAN_FS1R_FSC5 CAN_FS1R_FSC5_Msk /*!< Filter Scale Configuration for filter 5 */
+#define CAN_FS1R_FSC6_Pos (6U)
+#define CAN_FS1R_FSC6_Msk (0x1U << CAN_FS1R_FSC6_Pos) /*!< 0x00000040 */
+#define CAN_FS1R_FSC6 CAN_FS1R_FSC6_Msk /*!< Filter Scale Configuration for filter 6 */
+#define CAN_FS1R_FSC7_Pos (7U)
+#define CAN_FS1R_FSC7_Msk (0x1U << CAN_FS1R_FSC7_Pos) /*!< 0x00000080 */
+#define CAN_FS1R_FSC7 CAN_FS1R_FSC7_Msk /*!< Filter Scale Configuration for filter 7 */
+#define CAN_FS1R_FSC8_Pos (8U)
+#define CAN_FS1R_FSC8_Msk (0x1U << CAN_FS1R_FSC8_Pos) /*!< 0x00000100 */
+#define CAN_FS1R_FSC8 CAN_FS1R_FSC8_Msk /*!< Filter Scale Configuration for filter 8 */
+#define CAN_FS1R_FSC9_Pos (9U)
+#define CAN_FS1R_FSC9_Msk (0x1U << CAN_FS1R_FSC9_Pos) /*!< 0x00000200 */
+#define CAN_FS1R_FSC9 CAN_FS1R_FSC9_Msk /*!< Filter Scale Configuration for filter 9 */
+#define CAN_FS1R_FSC10_Pos (10U)
+#define CAN_FS1R_FSC10_Msk (0x1U << CAN_FS1R_FSC10_Pos) /*!< 0x00000400 */
+#define CAN_FS1R_FSC10 CAN_FS1R_FSC10_Msk /*!< Filter Scale Configuration for filter 10 */
+#define CAN_FS1R_FSC11_Pos (11U)
+#define CAN_FS1R_FSC11_Msk (0x1U << CAN_FS1R_FSC11_Pos) /*!< 0x00000800 */
+#define CAN_FS1R_FSC11 CAN_FS1R_FSC11_Msk /*!< Filter Scale Configuration for filter 11 */
+#define CAN_FS1R_FSC12_Pos (12U)
+#define CAN_FS1R_FSC12_Msk (0x1U << CAN_FS1R_FSC12_Pos) /*!< 0x00001000 */
+#define CAN_FS1R_FSC12 CAN_FS1R_FSC12_Msk /*!< Filter Scale Configuration for filter 12 */
+#define CAN_FS1R_FSC13_Pos (13U)
+#define CAN_FS1R_FSC13_Msk (0x1U << CAN_FS1R_FSC13_Pos) /*!< 0x00002000 */
+#define CAN_FS1R_FSC13 CAN_FS1R_FSC13_Msk /*!< Filter Scale Configuration for filter 13 */
+
+/****************** Bit definition for CAN_FFA1R register *******************/
+#define CAN_FFA1R_FFA_Pos (0U)
+#define CAN_FFA1R_FFA_Msk (0x3FFFU << CAN_FFA1R_FFA_Pos) /*!< 0x00003FFF */
+#define CAN_FFA1R_FFA CAN_FFA1R_FFA_Msk /*!< Filter FIFO Assignment */
+#define CAN_FFA1R_FFA0_Pos (0U)
+#define CAN_FFA1R_FFA0_Msk (0x1U << CAN_FFA1R_FFA0_Pos) /*!< 0x00000001 */
+#define CAN_FFA1R_FFA0 CAN_FFA1R_FFA0_Msk /*!< Filter FIFO Assignment for filter 0 */
+#define CAN_FFA1R_FFA1_Pos (1U)
+#define CAN_FFA1R_FFA1_Msk (0x1U << CAN_FFA1R_FFA1_Pos) /*!< 0x00000002 */
+#define CAN_FFA1R_FFA1 CAN_FFA1R_FFA1_Msk /*!< Filter FIFO Assignment for filter 1 */
+#define CAN_FFA1R_FFA2_Pos (2U)
+#define CAN_FFA1R_FFA2_Msk (0x1U << CAN_FFA1R_FFA2_Pos) /*!< 0x00000004 */
+#define CAN_FFA1R_FFA2 CAN_FFA1R_FFA2_Msk /*!< Filter FIFO Assignment for filter 2 */
+#define CAN_FFA1R_FFA3_Pos (3U)
+#define CAN_FFA1R_FFA3_Msk (0x1U << CAN_FFA1R_FFA3_Pos) /*!< 0x00000008 */
+#define CAN_FFA1R_FFA3 CAN_FFA1R_FFA3_Msk /*!< Filter FIFO Assignment for filter 3 */
+#define CAN_FFA1R_FFA4_Pos (4U)
+#define CAN_FFA1R_FFA4_Msk (0x1U << CAN_FFA1R_FFA4_Pos) /*!< 0x00000010 */
+#define CAN_FFA1R_FFA4 CAN_FFA1R_FFA4_Msk /*!< Filter FIFO Assignment for filter 4 */
+#define CAN_FFA1R_FFA5_Pos (5U)
+#define CAN_FFA1R_FFA5_Msk (0x1U << CAN_FFA1R_FFA5_Pos) /*!< 0x00000020 */
+#define CAN_FFA1R_FFA5 CAN_FFA1R_FFA5_Msk /*!< Filter FIFO Assignment for filter 5 */
+#define CAN_FFA1R_FFA6_Pos (6U)
+#define CAN_FFA1R_FFA6_Msk (0x1U << CAN_FFA1R_FFA6_Pos) /*!< 0x00000040 */
+#define CAN_FFA1R_FFA6 CAN_FFA1R_FFA6_Msk /*!< Filter FIFO Assignment for filter 6 */
+#define CAN_FFA1R_FFA7_Pos (7U)
+#define CAN_FFA1R_FFA7_Msk (0x1U << CAN_FFA1R_FFA7_Pos) /*!< 0x00000080 */
+#define CAN_FFA1R_FFA7 CAN_FFA1R_FFA7_Msk /*!< Filter FIFO Assignment for filter 7 */
+#define CAN_FFA1R_FFA8_Pos (8U)
+#define CAN_FFA1R_FFA8_Msk (0x1U << CAN_FFA1R_FFA8_Pos) /*!< 0x00000100 */
+#define CAN_FFA1R_FFA8 CAN_FFA1R_FFA8_Msk /*!< Filter FIFO Assignment for filter 8 */
+#define CAN_FFA1R_FFA9_Pos (9U)
+#define CAN_FFA1R_FFA9_Msk (0x1U << CAN_FFA1R_FFA9_Pos) /*!< 0x00000200 */
+#define CAN_FFA1R_FFA9 CAN_FFA1R_FFA9_Msk /*!< Filter FIFO Assignment for filter 9 */
+#define CAN_FFA1R_FFA10_Pos (10U)
+#define CAN_FFA1R_FFA10_Msk (0x1U << CAN_FFA1R_FFA10_Pos) /*!< 0x00000400 */
+#define CAN_FFA1R_FFA10 CAN_FFA1R_FFA10_Msk /*!< Filter FIFO Assignment for filter 10 */
+#define CAN_FFA1R_FFA11_Pos (11U)
+#define CAN_FFA1R_FFA11_Msk (0x1U << CAN_FFA1R_FFA11_Pos) /*!< 0x00000800 */
+#define CAN_FFA1R_FFA11 CAN_FFA1R_FFA11_Msk /*!< Filter FIFO Assignment for filter 11 */
+#define CAN_FFA1R_FFA12_Pos (12U)
+#define CAN_FFA1R_FFA12_Msk (0x1U << CAN_FFA1R_FFA12_Pos) /*!< 0x00001000 */
+#define CAN_FFA1R_FFA12 CAN_FFA1R_FFA12_Msk /*!< Filter FIFO Assignment for filter 12 */
+#define CAN_FFA1R_FFA13_Pos (13U)
+#define CAN_FFA1R_FFA13_Msk (0x1U << CAN_FFA1R_FFA13_Pos) /*!< 0x00002000 */
+#define CAN_FFA1R_FFA13 CAN_FFA1R_FFA13_Msk /*!< Filter FIFO Assignment for filter 13 */
+
+/******************* Bit definition for CAN_FA1R register *******************/
+#define CAN_FA1R_FACT_Pos (0U)
+#define CAN_FA1R_FACT_Msk (0x3FFFU << CAN_FA1R_FACT_Pos) /*!< 0x00003FFF */
+#define CAN_FA1R_FACT CAN_FA1R_FACT_Msk /*!< Filter Active */
+#define CAN_FA1R_FACT0_Pos (0U)
+#define CAN_FA1R_FACT0_Msk (0x1U << CAN_FA1R_FACT0_Pos) /*!< 0x00000001 */
+#define CAN_FA1R_FACT0 CAN_FA1R_FACT0_Msk /*!< Filter 0 Active */
+#define CAN_FA1R_FACT1_Pos (1U)
+#define CAN_FA1R_FACT1_Msk (0x1U << CAN_FA1R_FACT1_Pos) /*!< 0x00000002 */
+#define CAN_FA1R_FACT1 CAN_FA1R_FACT1_Msk /*!< Filter 1 Active */
+#define CAN_FA1R_FACT2_Pos (2U)
+#define CAN_FA1R_FACT2_Msk (0x1U << CAN_FA1R_FACT2_Pos) /*!< 0x00000004 */
+#define CAN_FA1R_FACT2 CAN_FA1R_FACT2_Msk /*!< Filter 2 Active */
+#define CAN_FA1R_FACT3_Pos (3U)
+#define CAN_FA1R_FACT3_Msk (0x1U << CAN_FA1R_FACT3_Pos) /*!< 0x00000008 */
+#define CAN_FA1R_FACT3 CAN_FA1R_FACT3_Msk /*!< Filter 3 Active */
+#define CAN_FA1R_FACT4_Pos (4U)
+#define CAN_FA1R_FACT4_Msk (0x1U << CAN_FA1R_FACT4_Pos) /*!< 0x00000010 */
+#define CAN_FA1R_FACT4 CAN_FA1R_FACT4_Msk /*!< Filter 4 Active */
+#define CAN_FA1R_FACT5_Pos (5U)
+#define CAN_FA1R_FACT5_Msk (0x1U << CAN_FA1R_FACT5_Pos) /*!< 0x00000020 */
+#define CAN_FA1R_FACT5 CAN_FA1R_FACT5_Msk /*!< Filter 5 Active */
+#define CAN_FA1R_FACT6_Pos (6U)
+#define CAN_FA1R_FACT6_Msk (0x1U << CAN_FA1R_FACT6_Pos) /*!< 0x00000040 */
+#define CAN_FA1R_FACT6 CAN_FA1R_FACT6_Msk /*!< Filter 6 Active */
+#define CAN_FA1R_FACT7_Pos (7U)
+#define CAN_FA1R_FACT7_Msk (0x1U << CAN_FA1R_FACT7_Pos) /*!< 0x00000080 */
+#define CAN_FA1R_FACT7 CAN_FA1R_FACT7_Msk /*!< Filter 7 Active */
+#define CAN_FA1R_FACT8_Pos (8U)
+#define CAN_FA1R_FACT8_Msk (0x1U << CAN_FA1R_FACT8_Pos) /*!< 0x00000100 */
+#define CAN_FA1R_FACT8 CAN_FA1R_FACT8_Msk /*!< Filter 8 Active */
+#define CAN_FA1R_FACT9_Pos (9U)
+#define CAN_FA1R_FACT9_Msk (0x1U << CAN_FA1R_FACT9_Pos) /*!< 0x00000200 */
+#define CAN_FA1R_FACT9 CAN_FA1R_FACT9_Msk /*!< Filter 9 Active */
+#define CAN_FA1R_FACT10_Pos (10U)
+#define CAN_FA1R_FACT10_Msk (0x1U << CAN_FA1R_FACT10_Pos) /*!< 0x00000400 */
+#define CAN_FA1R_FACT10 CAN_FA1R_FACT10_Msk /*!< Filter 10 Active */
+#define CAN_FA1R_FACT11_Pos (11U)
+#define CAN_FA1R_FACT11_Msk (0x1U << CAN_FA1R_FACT11_Pos) /*!< 0x00000800 */
+#define CAN_FA1R_FACT11 CAN_FA1R_FACT11_Msk /*!< Filter 11 Active */
+#define CAN_FA1R_FACT12_Pos (12U)
+#define CAN_FA1R_FACT12_Msk (0x1U << CAN_FA1R_FACT12_Pos) /*!< 0x00001000 */
+#define CAN_FA1R_FACT12 CAN_FA1R_FACT12_Msk /*!< Filter 12 Active */
+#define CAN_FA1R_FACT13_Pos (13U)
+#define CAN_FA1R_FACT13_Msk (0x1U << CAN_FA1R_FACT13_Pos) /*!< 0x00002000 */
+#define CAN_FA1R_FACT13 CAN_FA1R_FACT13_Msk /*!< Filter 13 Active */
+
+/******************* Bit definition for CAN_F0R1 register *******************/
+#define CAN_F0R1_FB0_Pos (0U)
+#define CAN_F0R1_FB0_Msk (0x1U << CAN_F0R1_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F0R1_FB0 CAN_F0R1_FB0_Msk /*!< Filter bit 0 */
+#define CAN_F0R1_FB1_Pos (1U)
+#define CAN_F0R1_FB1_Msk (0x1U << CAN_F0R1_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F0R1_FB1 CAN_F0R1_FB1_Msk /*!< Filter bit 1 */
+#define CAN_F0R1_FB2_Pos (2U)
+#define CAN_F0R1_FB2_Msk (0x1U << CAN_F0R1_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F0R1_FB2 CAN_F0R1_FB2_Msk /*!< Filter bit 2 */
+#define CAN_F0R1_FB3_Pos (3U)
+#define CAN_F0R1_FB3_Msk (0x1U << CAN_F0R1_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F0R1_FB3 CAN_F0R1_FB3_Msk /*!< Filter bit 3 */
+#define CAN_F0R1_FB4_Pos (4U)
+#define CAN_F0R1_FB4_Msk (0x1U << CAN_F0R1_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F0R1_FB4 CAN_F0R1_FB4_Msk /*!< Filter bit 4 */
+#define CAN_F0R1_FB5_Pos (5U)
+#define CAN_F0R1_FB5_Msk (0x1U << CAN_F0R1_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F0R1_FB5 CAN_F0R1_FB5_Msk /*!< Filter bit 5 */
+#define CAN_F0R1_FB6_Pos (6U)
+#define CAN_F0R1_FB6_Msk (0x1U << CAN_F0R1_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F0R1_FB6 CAN_F0R1_FB6_Msk /*!< Filter bit 6 */
+#define CAN_F0R1_FB7_Pos (7U)
+#define CAN_F0R1_FB7_Msk (0x1U << CAN_F0R1_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F0R1_FB7 CAN_F0R1_FB7_Msk /*!< Filter bit 7 */
+#define CAN_F0R1_FB8_Pos (8U)
+#define CAN_F0R1_FB8_Msk (0x1U << CAN_F0R1_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F0R1_FB8 CAN_F0R1_FB8_Msk /*!< Filter bit 8 */
+#define CAN_F0R1_FB9_Pos (9U)
+#define CAN_F0R1_FB9_Msk (0x1U << CAN_F0R1_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F0R1_FB9 CAN_F0R1_FB9_Msk /*!< Filter bit 9 */
+#define CAN_F0R1_FB10_Pos (10U)
+#define CAN_F0R1_FB10_Msk (0x1U << CAN_F0R1_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F0R1_FB10 CAN_F0R1_FB10_Msk /*!< Filter bit 10 */
+#define CAN_F0R1_FB11_Pos (11U)
+#define CAN_F0R1_FB11_Msk (0x1U << CAN_F0R1_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F0R1_FB11 CAN_F0R1_FB11_Msk /*!< Filter bit 11 */
+#define CAN_F0R1_FB12_Pos (12U)
+#define CAN_F0R1_FB12_Msk (0x1U << CAN_F0R1_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F0R1_FB12 CAN_F0R1_FB12_Msk /*!< Filter bit 12 */
+#define CAN_F0R1_FB13_Pos (13U)
+#define CAN_F0R1_FB13_Msk (0x1U << CAN_F0R1_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F0R1_FB13 CAN_F0R1_FB13_Msk /*!< Filter bit 13 */
+#define CAN_F0R1_FB14_Pos (14U)
+#define CAN_F0R1_FB14_Msk (0x1U << CAN_F0R1_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F0R1_FB14 CAN_F0R1_FB14_Msk /*!< Filter bit 14 */
+#define CAN_F0R1_FB15_Pos (15U)
+#define CAN_F0R1_FB15_Msk (0x1U << CAN_F0R1_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F0R1_FB15 CAN_F0R1_FB15_Msk /*!< Filter bit 15 */
+#define CAN_F0R1_FB16_Pos (16U)
+#define CAN_F0R1_FB16_Msk (0x1U << CAN_F0R1_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F0R1_FB16 CAN_F0R1_FB16_Msk /*!< Filter bit 16 */
+#define CAN_F0R1_FB17_Pos (17U)
+#define CAN_F0R1_FB17_Msk (0x1U << CAN_F0R1_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F0R1_FB17 CAN_F0R1_FB17_Msk /*!< Filter bit 17 */
+#define CAN_F0R1_FB18_Pos (18U)
+#define CAN_F0R1_FB18_Msk (0x1U << CAN_F0R1_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F0R1_FB18 CAN_F0R1_FB18_Msk /*!< Filter bit 18 */
+#define CAN_F0R1_FB19_Pos (19U)
+#define CAN_F0R1_FB19_Msk (0x1U << CAN_F0R1_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F0R1_FB19 CAN_F0R1_FB19_Msk /*!< Filter bit 19 */
+#define CAN_F0R1_FB20_Pos (20U)
+#define CAN_F0R1_FB20_Msk (0x1U << CAN_F0R1_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F0R1_FB20 CAN_F0R1_FB20_Msk /*!< Filter bit 20 */
+#define CAN_F0R1_FB21_Pos (21U)
+#define CAN_F0R1_FB21_Msk (0x1U << CAN_F0R1_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F0R1_FB21 CAN_F0R1_FB21_Msk /*!< Filter bit 21 */
+#define CAN_F0R1_FB22_Pos (22U)
+#define CAN_F0R1_FB22_Msk (0x1U << CAN_F0R1_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F0R1_FB22 CAN_F0R1_FB22_Msk /*!< Filter bit 22 */
+#define CAN_F0R1_FB23_Pos (23U)
+#define CAN_F0R1_FB23_Msk (0x1U << CAN_F0R1_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F0R1_FB23 CAN_F0R1_FB23_Msk /*!< Filter bit 23 */
+#define CAN_F0R1_FB24_Pos (24U)
+#define CAN_F0R1_FB24_Msk (0x1U << CAN_F0R1_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F0R1_FB24 CAN_F0R1_FB24_Msk /*!< Filter bit 24 */
+#define CAN_F0R1_FB25_Pos (25U)
+#define CAN_F0R1_FB25_Msk (0x1U << CAN_F0R1_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F0R1_FB25 CAN_F0R1_FB25_Msk /*!< Filter bit 25 */
+#define CAN_F0R1_FB26_Pos (26U)
+#define CAN_F0R1_FB26_Msk (0x1U << CAN_F0R1_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F0R1_FB26 CAN_F0R1_FB26_Msk /*!< Filter bit 26 */
+#define CAN_F0R1_FB27_Pos (27U)
+#define CAN_F0R1_FB27_Msk (0x1U << CAN_F0R1_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F0R1_FB27 CAN_F0R1_FB27_Msk /*!< Filter bit 27 */
+#define CAN_F0R1_FB28_Pos (28U)
+#define CAN_F0R1_FB28_Msk (0x1U << CAN_F0R1_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F0R1_FB28 CAN_F0R1_FB28_Msk /*!< Filter bit 28 */
+#define CAN_F0R1_FB29_Pos (29U)
+#define CAN_F0R1_FB29_Msk (0x1U << CAN_F0R1_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F0R1_FB29 CAN_F0R1_FB29_Msk /*!< Filter bit 29 */
+#define CAN_F0R1_FB30_Pos (30U)
+#define CAN_F0R1_FB30_Msk (0x1U << CAN_F0R1_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F0R1_FB30 CAN_F0R1_FB30_Msk /*!< Filter bit 30 */
+#define CAN_F0R1_FB31_Pos (31U)
+#define CAN_F0R1_FB31_Msk (0x1U << CAN_F0R1_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F0R1_FB31 CAN_F0R1_FB31_Msk /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F1R1 register *******************/
+#define CAN_F1R1_FB0_Pos (0U)
+#define CAN_F1R1_FB0_Msk (0x1U << CAN_F1R1_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F1R1_FB0 CAN_F1R1_FB0_Msk /*!< Filter bit 0 */
+#define CAN_F1R1_FB1_Pos (1U)
+#define CAN_F1R1_FB1_Msk (0x1U << CAN_F1R1_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F1R1_FB1 CAN_F1R1_FB1_Msk /*!< Filter bit 1 */
+#define CAN_F1R1_FB2_Pos (2U)
+#define CAN_F1R1_FB2_Msk (0x1U << CAN_F1R1_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F1R1_FB2 CAN_F1R1_FB2_Msk /*!< Filter bit 2 */
+#define CAN_F1R1_FB3_Pos (3U)
+#define CAN_F1R1_FB3_Msk (0x1U << CAN_F1R1_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F1R1_FB3 CAN_F1R1_FB3_Msk /*!< Filter bit 3 */
+#define CAN_F1R1_FB4_Pos (4U)
+#define CAN_F1R1_FB4_Msk (0x1U << CAN_F1R1_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F1R1_FB4 CAN_F1R1_FB4_Msk /*!< Filter bit 4 */
+#define CAN_F1R1_FB5_Pos (5U)
+#define CAN_F1R1_FB5_Msk (0x1U << CAN_F1R1_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F1R1_FB5 CAN_F1R1_FB5_Msk /*!< Filter bit 5 */
+#define CAN_F1R1_FB6_Pos (6U)
+#define CAN_F1R1_FB6_Msk (0x1U << CAN_F1R1_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F1R1_FB6 CAN_F1R1_FB6_Msk /*!< Filter bit 6 */
+#define CAN_F1R1_FB7_Pos (7U)
+#define CAN_F1R1_FB7_Msk (0x1U << CAN_F1R1_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F1R1_FB7 CAN_F1R1_FB7_Msk /*!< Filter bit 7 */
+#define CAN_F1R1_FB8_Pos (8U)
+#define CAN_F1R1_FB8_Msk (0x1U << CAN_F1R1_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F1R1_FB8 CAN_F1R1_FB8_Msk /*!< Filter bit 8 */
+#define CAN_F1R1_FB9_Pos (9U)
+#define CAN_F1R1_FB9_Msk (0x1U << CAN_F1R1_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F1R1_FB9 CAN_F1R1_FB9_Msk /*!< Filter bit 9 */
+#define CAN_F1R1_FB10_Pos (10U)
+#define CAN_F1R1_FB10_Msk (0x1U << CAN_F1R1_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F1R1_FB10 CAN_F1R1_FB10_Msk /*!< Filter bit 10 */
+#define CAN_F1R1_FB11_Pos (11U)
+#define CAN_F1R1_FB11_Msk (0x1U << CAN_F1R1_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F1R1_FB11 CAN_F1R1_FB11_Msk /*!< Filter bit 11 */
+#define CAN_F1R1_FB12_Pos (12U)
+#define CAN_F1R1_FB12_Msk (0x1U << CAN_F1R1_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F1R1_FB12 CAN_F1R1_FB12_Msk /*!< Filter bit 12 */
+#define CAN_F1R1_FB13_Pos (13U)
+#define CAN_F1R1_FB13_Msk (0x1U << CAN_F1R1_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F1R1_FB13 CAN_F1R1_FB13_Msk /*!< Filter bit 13 */
+#define CAN_F1R1_FB14_Pos (14U)
+#define CAN_F1R1_FB14_Msk (0x1U << CAN_F1R1_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F1R1_FB14 CAN_F1R1_FB14_Msk /*!< Filter bit 14 */
+#define CAN_F1R1_FB15_Pos (15U)
+#define CAN_F1R1_FB15_Msk (0x1U << CAN_F1R1_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F1R1_FB15 CAN_F1R1_FB15_Msk /*!< Filter bit 15 */
+#define CAN_F1R1_FB16_Pos (16U)
+#define CAN_F1R1_FB16_Msk (0x1U << CAN_F1R1_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F1R1_FB16 CAN_F1R1_FB16_Msk /*!< Filter bit 16 */
+#define CAN_F1R1_FB17_Pos (17U)
+#define CAN_F1R1_FB17_Msk (0x1U << CAN_F1R1_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F1R1_FB17 CAN_F1R1_FB17_Msk /*!< Filter bit 17 */
+#define CAN_F1R1_FB18_Pos (18U)
+#define CAN_F1R1_FB18_Msk (0x1U << CAN_F1R1_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F1R1_FB18 CAN_F1R1_FB18_Msk /*!< Filter bit 18 */
+#define CAN_F1R1_FB19_Pos (19U)
+#define CAN_F1R1_FB19_Msk (0x1U << CAN_F1R1_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F1R1_FB19 CAN_F1R1_FB19_Msk /*!< Filter bit 19 */
+#define CAN_F1R1_FB20_Pos (20U)
+#define CAN_F1R1_FB20_Msk (0x1U << CAN_F1R1_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F1R1_FB20 CAN_F1R1_FB20_Msk /*!< Filter bit 20 */
+#define CAN_F1R1_FB21_Pos (21U)
+#define CAN_F1R1_FB21_Msk (0x1U << CAN_F1R1_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F1R1_FB21 CAN_F1R1_FB21_Msk /*!< Filter bit 21 */
+#define CAN_F1R1_FB22_Pos (22U)
+#define CAN_F1R1_FB22_Msk (0x1U << CAN_F1R1_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F1R1_FB22 CAN_F1R1_FB22_Msk /*!< Filter bit 22 */
+#define CAN_F1R1_FB23_Pos (23U)
+#define CAN_F1R1_FB23_Msk (0x1U << CAN_F1R1_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F1R1_FB23 CAN_F1R1_FB23_Msk /*!< Filter bit 23 */
+#define CAN_F1R1_FB24_Pos (24U)
+#define CAN_F1R1_FB24_Msk (0x1U << CAN_F1R1_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F1R1_FB24 CAN_F1R1_FB24_Msk /*!< Filter bit 24 */
+#define CAN_F1R1_FB25_Pos (25U)
+#define CAN_F1R1_FB25_Msk (0x1U << CAN_F1R1_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F1R1_FB25 CAN_F1R1_FB25_Msk /*!< Filter bit 25 */
+#define CAN_F1R1_FB26_Pos (26U)
+#define CAN_F1R1_FB26_Msk (0x1U << CAN_F1R1_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F1R1_FB26 CAN_F1R1_FB26_Msk /*!< Filter bit 26 */
+#define CAN_F1R1_FB27_Pos (27U)
+#define CAN_F1R1_FB27_Msk (0x1U << CAN_F1R1_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F1R1_FB27 CAN_F1R1_FB27_Msk /*!< Filter bit 27 */
+#define CAN_F1R1_FB28_Pos (28U)
+#define CAN_F1R1_FB28_Msk (0x1U << CAN_F1R1_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F1R1_FB28 CAN_F1R1_FB28_Msk /*!< Filter bit 28 */
+#define CAN_F1R1_FB29_Pos (29U)
+#define CAN_F1R1_FB29_Msk (0x1U << CAN_F1R1_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F1R1_FB29 CAN_F1R1_FB29_Msk /*!< Filter bit 29 */
+#define CAN_F1R1_FB30_Pos (30U)
+#define CAN_F1R1_FB30_Msk (0x1U << CAN_F1R1_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F1R1_FB30 CAN_F1R1_FB30_Msk /*!< Filter bit 30 */
+#define CAN_F1R1_FB31_Pos (31U)
+#define CAN_F1R1_FB31_Msk (0x1U << CAN_F1R1_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F1R1_FB31 CAN_F1R1_FB31_Msk /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F2R1 register *******************/
+#define CAN_F2R1_FB0_Pos (0U)
+#define CAN_F2R1_FB0_Msk (0x1U << CAN_F2R1_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F2R1_FB0 CAN_F2R1_FB0_Msk /*!< Filter bit 0 */
+#define CAN_F2R1_FB1_Pos (1U)
+#define CAN_F2R1_FB1_Msk (0x1U << CAN_F2R1_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F2R1_FB1 CAN_F2R1_FB1_Msk /*!< Filter bit 1 */
+#define CAN_F2R1_FB2_Pos (2U)
+#define CAN_F2R1_FB2_Msk (0x1U << CAN_F2R1_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F2R1_FB2 CAN_F2R1_FB2_Msk /*!< Filter bit 2 */
+#define CAN_F2R1_FB3_Pos (3U)
+#define CAN_F2R1_FB3_Msk (0x1U << CAN_F2R1_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F2R1_FB3 CAN_F2R1_FB3_Msk /*!< Filter bit 3 */
+#define CAN_F2R1_FB4_Pos (4U)
+#define CAN_F2R1_FB4_Msk (0x1U << CAN_F2R1_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F2R1_FB4 CAN_F2R1_FB4_Msk /*!< Filter bit 4 */
+#define CAN_F2R1_FB5_Pos (5U)
+#define CAN_F2R1_FB5_Msk (0x1U << CAN_F2R1_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F2R1_FB5 CAN_F2R1_FB5_Msk /*!< Filter bit 5 */
+#define CAN_F2R1_FB6_Pos (6U)
+#define CAN_F2R1_FB6_Msk (0x1U << CAN_F2R1_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F2R1_FB6 CAN_F2R1_FB6_Msk /*!< Filter bit 6 */
+#define CAN_F2R1_FB7_Pos (7U)
+#define CAN_F2R1_FB7_Msk (0x1U << CAN_F2R1_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F2R1_FB7 CAN_F2R1_FB7_Msk /*!< Filter bit 7 */
+#define CAN_F2R1_FB8_Pos (8U)
+#define CAN_F2R1_FB8_Msk (0x1U << CAN_F2R1_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F2R1_FB8 CAN_F2R1_FB8_Msk /*!< Filter bit 8 */
+#define CAN_F2R1_FB9_Pos (9U)
+#define CAN_F2R1_FB9_Msk (0x1U << CAN_F2R1_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F2R1_FB9 CAN_F2R1_FB9_Msk /*!< Filter bit 9 */
+#define CAN_F2R1_FB10_Pos (10U)
+#define CAN_F2R1_FB10_Msk (0x1U << CAN_F2R1_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F2R1_FB10 CAN_F2R1_FB10_Msk /*!< Filter bit 10 */
+#define CAN_F2R1_FB11_Pos (11U)
+#define CAN_F2R1_FB11_Msk (0x1U << CAN_F2R1_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F2R1_FB11 CAN_F2R1_FB11_Msk /*!< Filter bit 11 */
+#define CAN_F2R1_FB12_Pos (12U)
+#define CAN_F2R1_FB12_Msk (0x1U << CAN_F2R1_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F2R1_FB12 CAN_F2R1_FB12_Msk /*!< Filter bit 12 */
+#define CAN_F2R1_FB13_Pos (13U)
+#define CAN_F2R1_FB13_Msk (0x1U << CAN_F2R1_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F2R1_FB13 CAN_F2R1_FB13_Msk /*!< Filter bit 13 */
+#define CAN_F2R1_FB14_Pos (14U)
+#define CAN_F2R1_FB14_Msk (0x1U << CAN_F2R1_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F2R1_FB14 CAN_F2R1_FB14_Msk /*!< Filter bit 14 */
+#define CAN_F2R1_FB15_Pos (15U)
+#define CAN_F2R1_FB15_Msk (0x1U << CAN_F2R1_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F2R1_FB15 CAN_F2R1_FB15_Msk /*!< Filter bit 15 */
+#define CAN_F2R1_FB16_Pos (16U)
+#define CAN_F2R1_FB16_Msk (0x1U << CAN_F2R1_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F2R1_FB16 CAN_F2R1_FB16_Msk /*!< Filter bit 16 */
+#define CAN_F2R1_FB17_Pos (17U)
+#define CAN_F2R1_FB17_Msk (0x1U << CAN_F2R1_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F2R1_FB17 CAN_F2R1_FB17_Msk /*!< Filter bit 17 */
+#define CAN_F2R1_FB18_Pos (18U)
+#define CAN_F2R1_FB18_Msk (0x1U << CAN_F2R1_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F2R1_FB18 CAN_F2R1_FB18_Msk /*!< Filter bit 18 */
+#define CAN_F2R1_FB19_Pos (19U)
+#define CAN_F2R1_FB19_Msk (0x1U << CAN_F2R1_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F2R1_FB19 CAN_F2R1_FB19_Msk /*!< Filter bit 19 */
+#define CAN_F2R1_FB20_Pos (20U)
+#define CAN_F2R1_FB20_Msk (0x1U << CAN_F2R1_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F2R1_FB20 CAN_F2R1_FB20_Msk /*!< Filter bit 20 */
+#define CAN_F2R1_FB21_Pos (21U)
+#define CAN_F2R1_FB21_Msk (0x1U << CAN_F2R1_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F2R1_FB21 CAN_F2R1_FB21_Msk /*!< Filter bit 21 */
+#define CAN_F2R1_FB22_Pos (22U)
+#define CAN_F2R1_FB22_Msk (0x1U << CAN_F2R1_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F2R1_FB22 CAN_F2R1_FB22_Msk /*!< Filter bit 22 */
+#define CAN_F2R1_FB23_Pos (23U)
+#define CAN_F2R1_FB23_Msk (0x1U << CAN_F2R1_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F2R1_FB23 CAN_F2R1_FB23_Msk /*!< Filter bit 23 */
+#define CAN_F2R1_FB24_Pos (24U)
+#define CAN_F2R1_FB24_Msk (0x1U << CAN_F2R1_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F2R1_FB24 CAN_F2R1_FB24_Msk /*!< Filter bit 24 */
+#define CAN_F2R1_FB25_Pos (25U)
+#define CAN_F2R1_FB25_Msk (0x1U << CAN_F2R1_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F2R1_FB25 CAN_F2R1_FB25_Msk /*!< Filter bit 25 */
+#define CAN_F2R1_FB26_Pos (26U)
+#define CAN_F2R1_FB26_Msk (0x1U << CAN_F2R1_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F2R1_FB26 CAN_F2R1_FB26_Msk /*!< Filter bit 26 */
+#define CAN_F2R1_FB27_Pos (27U)
+#define CAN_F2R1_FB27_Msk (0x1U << CAN_F2R1_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F2R1_FB27 CAN_F2R1_FB27_Msk /*!< Filter bit 27 */
+#define CAN_F2R1_FB28_Pos (28U)
+#define CAN_F2R1_FB28_Msk (0x1U << CAN_F2R1_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F2R1_FB28 CAN_F2R1_FB28_Msk /*!< Filter bit 28 */
+#define CAN_F2R1_FB29_Pos (29U)
+#define CAN_F2R1_FB29_Msk (0x1U << CAN_F2R1_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F2R1_FB29 CAN_F2R1_FB29_Msk /*!< Filter bit 29 */
+#define CAN_F2R1_FB30_Pos (30U)
+#define CAN_F2R1_FB30_Msk (0x1U << CAN_F2R1_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F2R1_FB30 CAN_F2R1_FB30_Msk /*!< Filter bit 30 */
+#define CAN_F2R1_FB31_Pos (31U)
+#define CAN_F2R1_FB31_Msk (0x1U << CAN_F2R1_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F2R1_FB31 CAN_F2R1_FB31_Msk /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F3R1 register *******************/
+#define CAN_F3R1_FB0_Pos (0U)
+#define CAN_F3R1_FB0_Msk (0x1U << CAN_F3R1_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F3R1_FB0 CAN_F3R1_FB0_Msk /*!< Filter bit 0 */
+#define CAN_F3R1_FB1_Pos (1U)
+#define CAN_F3R1_FB1_Msk (0x1U << CAN_F3R1_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F3R1_FB1 CAN_F3R1_FB1_Msk /*!< Filter bit 1 */
+#define CAN_F3R1_FB2_Pos (2U)
+#define CAN_F3R1_FB2_Msk (0x1U << CAN_F3R1_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F3R1_FB2 CAN_F3R1_FB2_Msk /*!< Filter bit 2 */
+#define CAN_F3R1_FB3_Pos (3U)
+#define CAN_F3R1_FB3_Msk (0x1U << CAN_F3R1_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F3R1_FB3 CAN_F3R1_FB3_Msk /*!< Filter bit 3 */
+#define CAN_F3R1_FB4_Pos (4U)
+#define CAN_F3R1_FB4_Msk (0x1U << CAN_F3R1_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F3R1_FB4 CAN_F3R1_FB4_Msk /*!< Filter bit 4 */
+#define CAN_F3R1_FB5_Pos (5U)
+#define CAN_F3R1_FB5_Msk (0x1U << CAN_F3R1_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F3R1_FB5 CAN_F3R1_FB5_Msk /*!< Filter bit 5 */
+#define CAN_F3R1_FB6_Pos (6U)
+#define CAN_F3R1_FB6_Msk (0x1U << CAN_F3R1_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F3R1_FB6 CAN_F3R1_FB6_Msk /*!< Filter bit 6 */
+#define CAN_F3R1_FB7_Pos (7U)
+#define CAN_F3R1_FB7_Msk (0x1U << CAN_F3R1_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F3R1_FB7 CAN_F3R1_FB7_Msk /*!< Filter bit 7 */
+#define CAN_F3R1_FB8_Pos (8U)
+#define CAN_F3R1_FB8_Msk (0x1U << CAN_F3R1_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F3R1_FB8 CAN_F3R1_FB8_Msk /*!< Filter bit 8 */
+#define CAN_F3R1_FB9_Pos (9U)
+#define CAN_F3R1_FB9_Msk (0x1U << CAN_F3R1_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F3R1_FB9 CAN_F3R1_FB9_Msk /*!< Filter bit 9 */
+#define CAN_F3R1_FB10_Pos (10U)
+#define CAN_F3R1_FB10_Msk (0x1U << CAN_F3R1_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F3R1_FB10 CAN_F3R1_FB10_Msk /*!< Filter bit 10 */
+#define CAN_F3R1_FB11_Pos (11U)
+#define CAN_F3R1_FB11_Msk (0x1U << CAN_F3R1_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F3R1_FB11 CAN_F3R1_FB11_Msk /*!< Filter bit 11 */
+#define CAN_F3R1_FB12_Pos (12U)
+#define CAN_F3R1_FB12_Msk (0x1U << CAN_F3R1_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F3R1_FB12 CAN_F3R1_FB12_Msk /*!< Filter bit 12 */
+#define CAN_F3R1_FB13_Pos (13U)
+#define CAN_F3R1_FB13_Msk (0x1U << CAN_F3R1_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F3R1_FB13 CAN_F3R1_FB13_Msk /*!< Filter bit 13 */
+#define CAN_F3R1_FB14_Pos (14U)
+#define CAN_F3R1_FB14_Msk (0x1U << CAN_F3R1_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F3R1_FB14 CAN_F3R1_FB14_Msk /*!< Filter bit 14 */
+#define CAN_F3R1_FB15_Pos (15U)
+#define CAN_F3R1_FB15_Msk (0x1U << CAN_F3R1_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F3R1_FB15 CAN_F3R1_FB15_Msk /*!< Filter bit 15 */
+#define CAN_F3R1_FB16_Pos (16U)
+#define CAN_F3R1_FB16_Msk (0x1U << CAN_F3R1_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F3R1_FB16 CAN_F3R1_FB16_Msk /*!< Filter bit 16 */
+#define CAN_F3R1_FB17_Pos (17U)
+#define CAN_F3R1_FB17_Msk (0x1U << CAN_F3R1_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F3R1_FB17 CAN_F3R1_FB17_Msk /*!< Filter bit 17 */
+#define CAN_F3R1_FB18_Pos (18U)
+#define CAN_F3R1_FB18_Msk (0x1U << CAN_F3R1_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F3R1_FB18 CAN_F3R1_FB18_Msk /*!< Filter bit 18 */
+#define CAN_F3R1_FB19_Pos (19U)
+#define CAN_F3R1_FB19_Msk (0x1U << CAN_F3R1_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F3R1_FB19 CAN_F3R1_FB19_Msk /*!< Filter bit 19 */
+#define CAN_F3R1_FB20_Pos (20U)
+#define CAN_F3R1_FB20_Msk (0x1U << CAN_F3R1_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F3R1_FB20 CAN_F3R1_FB20_Msk /*!< Filter bit 20 */
+#define CAN_F3R1_FB21_Pos (21U)
+#define CAN_F3R1_FB21_Msk (0x1U << CAN_F3R1_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F3R1_FB21 CAN_F3R1_FB21_Msk /*!< Filter bit 21 */
+#define CAN_F3R1_FB22_Pos (22U)
+#define CAN_F3R1_FB22_Msk (0x1U << CAN_F3R1_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F3R1_FB22 CAN_F3R1_FB22_Msk /*!< Filter bit 22 */
+#define CAN_F3R1_FB23_Pos (23U)
+#define CAN_F3R1_FB23_Msk (0x1U << CAN_F3R1_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F3R1_FB23 CAN_F3R1_FB23_Msk /*!< Filter bit 23 */
+#define CAN_F3R1_FB24_Pos (24U)
+#define CAN_F3R1_FB24_Msk (0x1U << CAN_F3R1_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F3R1_FB24 CAN_F3R1_FB24_Msk /*!< Filter bit 24 */
+#define CAN_F3R1_FB25_Pos (25U)
+#define CAN_F3R1_FB25_Msk (0x1U << CAN_F3R1_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F3R1_FB25 CAN_F3R1_FB25_Msk /*!< Filter bit 25 */
+#define CAN_F3R1_FB26_Pos (26U)
+#define CAN_F3R1_FB26_Msk (0x1U << CAN_F3R1_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F3R1_FB26 CAN_F3R1_FB26_Msk /*!< Filter bit 26 */
+#define CAN_F3R1_FB27_Pos (27U)
+#define CAN_F3R1_FB27_Msk (0x1U << CAN_F3R1_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F3R1_FB27 CAN_F3R1_FB27_Msk /*!< Filter bit 27 */
+#define CAN_F3R1_FB28_Pos (28U)
+#define CAN_F3R1_FB28_Msk (0x1U << CAN_F3R1_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F3R1_FB28 CAN_F3R1_FB28_Msk /*!< Filter bit 28 */
+#define CAN_F3R1_FB29_Pos (29U)
+#define CAN_F3R1_FB29_Msk (0x1U << CAN_F3R1_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F3R1_FB29 CAN_F3R1_FB29_Msk /*!< Filter bit 29 */
+#define CAN_F3R1_FB30_Pos (30U)
+#define CAN_F3R1_FB30_Msk (0x1U << CAN_F3R1_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F3R1_FB30 CAN_F3R1_FB30_Msk /*!< Filter bit 30 */
+#define CAN_F3R1_FB31_Pos (31U)
+#define CAN_F3R1_FB31_Msk (0x1U << CAN_F3R1_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F3R1_FB31 CAN_F3R1_FB31_Msk /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F4R1 register *******************/
+#define CAN_F4R1_FB0_Pos (0U)
+#define CAN_F4R1_FB0_Msk (0x1U << CAN_F4R1_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F4R1_FB0 CAN_F4R1_FB0_Msk /*!< Filter bit 0 */
+#define CAN_F4R1_FB1_Pos (1U)
+#define CAN_F4R1_FB1_Msk (0x1U << CAN_F4R1_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F4R1_FB1 CAN_F4R1_FB1_Msk /*!< Filter bit 1 */
+#define CAN_F4R1_FB2_Pos (2U)
+#define CAN_F4R1_FB2_Msk (0x1U << CAN_F4R1_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F4R1_FB2 CAN_F4R1_FB2_Msk /*!< Filter bit 2 */
+#define CAN_F4R1_FB3_Pos (3U)
+#define CAN_F4R1_FB3_Msk (0x1U << CAN_F4R1_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F4R1_FB3 CAN_F4R1_FB3_Msk /*!< Filter bit 3 */
+#define CAN_F4R1_FB4_Pos (4U)
+#define CAN_F4R1_FB4_Msk (0x1U << CAN_F4R1_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F4R1_FB4 CAN_F4R1_FB4_Msk /*!< Filter bit 4 */
+#define CAN_F4R1_FB5_Pos (5U)
+#define CAN_F4R1_FB5_Msk (0x1U << CAN_F4R1_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F4R1_FB5 CAN_F4R1_FB5_Msk /*!< Filter bit 5 */
+#define CAN_F4R1_FB6_Pos (6U)
+#define CAN_F4R1_FB6_Msk (0x1U << CAN_F4R1_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F4R1_FB6 CAN_F4R1_FB6_Msk /*!< Filter bit 6 */
+#define CAN_F4R1_FB7_Pos (7U)
+#define CAN_F4R1_FB7_Msk (0x1U << CAN_F4R1_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F4R1_FB7 CAN_F4R1_FB7_Msk /*!< Filter bit 7 */
+#define CAN_F4R1_FB8_Pos (8U)
+#define CAN_F4R1_FB8_Msk (0x1U << CAN_F4R1_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F4R1_FB8 CAN_F4R1_FB8_Msk /*!< Filter bit 8 */
+#define CAN_F4R1_FB9_Pos (9U)
+#define CAN_F4R1_FB9_Msk (0x1U << CAN_F4R1_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F4R1_FB9 CAN_F4R1_FB9_Msk /*!< Filter bit 9 */
+#define CAN_F4R1_FB10_Pos (10U)
+#define CAN_F4R1_FB10_Msk (0x1U << CAN_F4R1_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F4R1_FB10 CAN_F4R1_FB10_Msk /*!< Filter bit 10 */
+#define CAN_F4R1_FB11_Pos (11U)
+#define CAN_F4R1_FB11_Msk (0x1U << CAN_F4R1_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F4R1_FB11 CAN_F4R1_FB11_Msk /*!< Filter bit 11 */
+#define CAN_F4R1_FB12_Pos (12U)
+#define CAN_F4R1_FB12_Msk (0x1U << CAN_F4R1_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F4R1_FB12 CAN_F4R1_FB12_Msk /*!< Filter bit 12 */
+#define CAN_F4R1_FB13_Pos (13U)
+#define CAN_F4R1_FB13_Msk (0x1U << CAN_F4R1_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F4R1_FB13 CAN_F4R1_FB13_Msk /*!< Filter bit 13 */
+#define CAN_F4R1_FB14_Pos (14U)
+#define CAN_F4R1_FB14_Msk (0x1U << CAN_F4R1_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F4R1_FB14 CAN_F4R1_FB14_Msk /*!< Filter bit 14 */
+#define CAN_F4R1_FB15_Pos (15U)
+#define CAN_F4R1_FB15_Msk (0x1U << CAN_F4R1_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F4R1_FB15 CAN_F4R1_FB15_Msk /*!< Filter bit 15 */
+#define CAN_F4R1_FB16_Pos (16U)
+#define CAN_F4R1_FB16_Msk (0x1U << CAN_F4R1_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F4R1_FB16 CAN_F4R1_FB16_Msk /*!< Filter bit 16 */
+#define CAN_F4R1_FB17_Pos (17U)
+#define CAN_F4R1_FB17_Msk (0x1U << CAN_F4R1_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F4R1_FB17 CAN_F4R1_FB17_Msk /*!< Filter bit 17 */
+#define CAN_F4R1_FB18_Pos (18U)
+#define CAN_F4R1_FB18_Msk (0x1U << CAN_F4R1_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F4R1_FB18 CAN_F4R1_FB18_Msk /*!< Filter bit 18 */
+#define CAN_F4R1_FB19_Pos (19U)
+#define CAN_F4R1_FB19_Msk (0x1U << CAN_F4R1_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F4R1_FB19 CAN_F4R1_FB19_Msk /*!< Filter bit 19 */
+#define CAN_F4R1_FB20_Pos (20U)
+#define CAN_F4R1_FB20_Msk (0x1U << CAN_F4R1_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F4R1_FB20 CAN_F4R1_FB20_Msk /*!< Filter bit 20 */
+#define CAN_F4R1_FB21_Pos (21U)
+#define CAN_F4R1_FB21_Msk (0x1U << CAN_F4R1_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F4R1_FB21 CAN_F4R1_FB21_Msk /*!< Filter bit 21 */
+#define CAN_F4R1_FB22_Pos (22U)
+#define CAN_F4R1_FB22_Msk (0x1U << CAN_F4R1_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F4R1_FB22 CAN_F4R1_FB22_Msk /*!< Filter bit 22 */
+#define CAN_F4R1_FB23_Pos (23U)
+#define CAN_F4R1_FB23_Msk (0x1U << CAN_F4R1_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F4R1_FB23 CAN_F4R1_FB23_Msk /*!< Filter bit 23 */
+#define CAN_F4R1_FB24_Pos (24U)
+#define CAN_F4R1_FB24_Msk (0x1U << CAN_F4R1_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F4R1_FB24 CAN_F4R1_FB24_Msk /*!< Filter bit 24 */
+#define CAN_F4R1_FB25_Pos (25U)
+#define CAN_F4R1_FB25_Msk (0x1U << CAN_F4R1_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F4R1_FB25 CAN_F4R1_FB25_Msk /*!< Filter bit 25 */
+#define CAN_F4R1_FB26_Pos (26U)
+#define CAN_F4R1_FB26_Msk (0x1U << CAN_F4R1_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F4R1_FB26 CAN_F4R1_FB26_Msk /*!< Filter bit 26 */
+#define CAN_F4R1_FB27_Pos (27U)
+#define CAN_F4R1_FB27_Msk (0x1U << CAN_F4R1_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F4R1_FB27 CAN_F4R1_FB27_Msk /*!< Filter bit 27 */
+#define CAN_F4R1_FB28_Pos (28U)
+#define CAN_F4R1_FB28_Msk (0x1U << CAN_F4R1_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F4R1_FB28 CAN_F4R1_FB28_Msk /*!< Filter bit 28 */
+#define CAN_F4R1_FB29_Pos (29U)
+#define CAN_F4R1_FB29_Msk (0x1U << CAN_F4R1_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F4R1_FB29 CAN_F4R1_FB29_Msk /*!< Filter bit 29 */
+#define CAN_F4R1_FB30_Pos (30U)
+#define CAN_F4R1_FB30_Msk (0x1U << CAN_F4R1_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F4R1_FB30 CAN_F4R1_FB30_Msk /*!< Filter bit 30 */
+#define CAN_F4R1_FB31_Pos (31U)
+#define CAN_F4R1_FB31_Msk (0x1U << CAN_F4R1_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F4R1_FB31 CAN_F4R1_FB31_Msk /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F5R1 register *******************/
+#define CAN_F5R1_FB0_Pos (0U)
+#define CAN_F5R1_FB0_Msk (0x1U << CAN_F5R1_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F5R1_FB0 CAN_F5R1_FB0_Msk /*!< Filter bit 0 */
+#define CAN_F5R1_FB1_Pos (1U)
+#define CAN_F5R1_FB1_Msk (0x1U << CAN_F5R1_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F5R1_FB1 CAN_F5R1_FB1_Msk /*!< Filter bit 1 */
+#define CAN_F5R1_FB2_Pos (2U)
+#define CAN_F5R1_FB2_Msk (0x1U << CAN_F5R1_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F5R1_FB2 CAN_F5R1_FB2_Msk /*!< Filter bit 2 */
+#define CAN_F5R1_FB3_Pos (3U)
+#define CAN_F5R1_FB3_Msk (0x1U << CAN_F5R1_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F5R1_FB3 CAN_F5R1_FB3_Msk /*!< Filter bit 3 */
+#define CAN_F5R1_FB4_Pos (4U)
+#define CAN_F5R1_FB4_Msk (0x1U << CAN_F5R1_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F5R1_FB4 CAN_F5R1_FB4_Msk /*!< Filter bit 4 */
+#define CAN_F5R1_FB5_Pos (5U)
+#define CAN_F5R1_FB5_Msk (0x1U << CAN_F5R1_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F5R1_FB5 CAN_F5R1_FB5_Msk /*!< Filter bit 5 */
+#define CAN_F5R1_FB6_Pos (6U)
+#define CAN_F5R1_FB6_Msk (0x1U << CAN_F5R1_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F5R1_FB6 CAN_F5R1_FB6_Msk /*!< Filter bit 6 */
+#define CAN_F5R1_FB7_Pos (7U)
+#define CAN_F5R1_FB7_Msk (0x1U << CAN_F5R1_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F5R1_FB7 CAN_F5R1_FB7_Msk /*!< Filter bit 7 */
+#define CAN_F5R1_FB8_Pos (8U)
+#define CAN_F5R1_FB8_Msk (0x1U << CAN_F5R1_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F5R1_FB8 CAN_F5R1_FB8_Msk /*!< Filter bit 8 */
+#define CAN_F5R1_FB9_Pos (9U)
+#define CAN_F5R1_FB9_Msk (0x1U << CAN_F5R1_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F5R1_FB9 CAN_F5R1_FB9_Msk /*!< Filter bit 9 */
+#define CAN_F5R1_FB10_Pos (10U)
+#define CAN_F5R1_FB10_Msk (0x1U << CAN_F5R1_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F5R1_FB10 CAN_F5R1_FB10_Msk /*!< Filter bit 10 */
+#define CAN_F5R1_FB11_Pos (11U)
+#define CAN_F5R1_FB11_Msk (0x1U << CAN_F5R1_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F5R1_FB11 CAN_F5R1_FB11_Msk /*!< Filter bit 11 */
+#define CAN_F5R1_FB12_Pos (12U)
+#define CAN_F5R1_FB12_Msk (0x1U << CAN_F5R1_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F5R1_FB12 CAN_F5R1_FB12_Msk /*!< Filter bit 12 */
+#define CAN_F5R1_FB13_Pos (13U)
+#define CAN_F5R1_FB13_Msk (0x1U << CAN_F5R1_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F5R1_FB13 CAN_F5R1_FB13_Msk /*!< Filter bit 13 */
+#define CAN_F5R1_FB14_Pos (14U)
+#define CAN_F5R1_FB14_Msk (0x1U << CAN_F5R1_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F5R1_FB14 CAN_F5R1_FB14_Msk /*!< Filter bit 14 */
+#define CAN_F5R1_FB15_Pos (15U)
+#define CAN_F5R1_FB15_Msk (0x1U << CAN_F5R1_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F5R1_FB15 CAN_F5R1_FB15_Msk /*!< Filter bit 15 */
+#define CAN_F5R1_FB16_Pos (16U)
+#define CAN_F5R1_FB16_Msk (0x1U << CAN_F5R1_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F5R1_FB16 CAN_F5R1_FB16_Msk /*!< Filter bit 16 */
+#define CAN_F5R1_FB17_Pos (17U)
+#define CAN_F5R1_FB17_Msk (0x1U << CAN_F5R1_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F5R1_FB17 CAN_F5R1_FB17_Msk /*!< Filter bit 17 */
+#define CAN_F5R1_FB18_Pos (18U)
+#define CAN_F5R1_FB18_Msk (0x1U << CAN_F5R1_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F5R1_FB18 CAN_F5R1_FB18_Msk /*!< Filter bit 18 */
+#define CAN_F5R1_FB19_Pos (19U)
+#define CAN_F5R1_FB19_Msk (0x1U << CAN_F5R1_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F5R1_FB19 CAN_F5R1_FB19_Msk /*!< Filter bit 19 */
+#define CAN_F5R1_FB20_Pos (20U)
+#define CAN_F5R1_FB20_Msk (0x1U << CAN_F5R1_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F5R1_FB20 CAN_F5R1_FB20_Msk /*!< Filter bit 20 */
+#define CAN_F5R1_FB21_Pos (21U)
+#define CAN_F5R1_FB21_Msk (0x1U << CAN_F5R1_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F5R1_FB21 CAN_F5R1_FB21_Msk /*!< Filter bit 21 */
+#define CAN_F5R1_FB22_Pos (22U)
+#define CAN_F5R1_FB22_Msk (0x1U << CAN_F5R1_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F5R1_FB22 CAN_F5R1_FB22_Msk /*!< Filter bit 22 */
+#define CAN_F5R1_FB23_Pos (23U)
+#define CAN_F5R1_FB23_Msk (0x1U << CAN_F5R1_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F5R1_FB23 CAN_F5R1_FB23_Msk /*!< Filter bit 23 */
+#define CAN_F5R1_FB24_Pos (24U)
+#define CAN_F5R1_FB24_Msk (0x1U << CAN_F5R1_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F5R1_FB24 CAN_F5R1_FB24_Msk /*!< Filter bit 24 */
+#define CAN_F5R1_FB25_Pos (25U)
+#define CAN_F5R1_FB25_Msk (0x1U << CAN_F5R1_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F5R1_FB25 CAN_F5R1_FB25_Msk /*!< Filter bit 25 */
+#define CAN_F5R1_FB26_Pos (26U)
+#define CAN_F5R1_FB26_Msk (0x1U << CAN_F5R1_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F5R1_FB26 CAN_F5R1_FB26_Msk /*!< Filter bit 26 */
+#define CAN_F5R1_FB27_Pos (27U)
+#define CAN_F5R1_FB27_Msk (0x1U << CAN_F5R1_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F5R1_FB27 CAN_F5R1_FB27_Msk /*!< Filter bit 27 */
+#define CAN_F5R1_FB28_Pos (28U)
+#define CAN_F5R1_FB28_Msk (0x1U << CAN_F5R1_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F5R1_FB28 CAN_F5R1_FB28_Msk /*!< Filter bit 28 */
+#define CAN_F5R1_FB29_Pos (29U)
+#define CAN_F5R1_FB29_Msk (0x1U << CAN_F5R1_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F5R1_FB29 CAN_F5R1_FB29_Msk /*!< Filter bit 29 */
+#define CAN_F5R1_FB30_Pos (30U)
+#define CAN_F5R1_FB30_Msk (0x1U << CAN_F5R1_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F5R1_FB30 CAN_F5R1_FB30_Msk /*!< Filter bit 30 */
+#define CAN_F5R1_FB31_Pos (31U)
+#define CAN_F5R1_FB31_Msk (0x1U << CAN_F5R1_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F5R1_FB31 CAN_F5R1_FB31_Msk /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F6R1 register *******************/
+#define CAN_F6R1_FB0_Pos (0U)
+#define CAN_F6R1_FB0_Msk (0x1U << CAN_F6R1_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F6R1_FB0 CAN_F6R1_FB0_Msk /*!< Filter bit 0 */
+#define CAN_F6R1_FB1_Pos (1U)
+#define CAN_F6R1_FB1_Msk (0x1U << CAN_F6R1_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F6R1_FB1 CAN_F6R1_FB1_Msk /*!< Filter bit 1 */
+#define CAN_F6R1_FB2_Pos (2U)
+#define CAN_F6R1_FB2_Msk (0x1U << CAN_F6R1_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F6R1_FB2 CAN_F6R1_FB2_Msk /*!< Filter bit 2 */
+#define CAN_F6R1_FB3_Pos (3U)
+#define CAN_F6R1_FB3_Msk (0x1U << CAN_F6R1_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F6R1_FB3 CAN_F6R1_FB3_Msk /*!< Filter bit 3 */
+#define CAN_F6R1_FB4_Pos (4U)
+#define CAN_F6R1_FB4_Msk (0x1U << CAN_F6R1_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F6R1_FB4 CAN_F6R1_FB4_Msk /*!< Filter bit 4 */
+#define CAN_F6R1_FB5_Pos (5U)
+#define CAN_F6R1_FB5_Msk (0x1U << CAN_F6R1_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F6R1_FB5 CAN_F6R1_FB5_Msk /*!< Filter bit 5 */
+#define CAN_F6R1_FB6_Pos (6U)
+#define CAN_F6R1_FB6_Msk (0x1U << CAN_F6R1_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F6R1_FB6 CAN_F6R1_FB6_Msk /*!< Filter bit 6 */
+#define CAN_F6R1_FB7_Pos (7U)
+#define CAN_F6R1_FB7_Msk (0x1U << CAN_F6R1_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F6R1_FB7 CAN_F6R1_FB7_Msk /*!< Filter bit 7 */
+#define CAN_F6R1_FB8_Pos (8U)
+#define CAN_F6R1_FB8_Msk (0x1U << CAN_F6R1_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F6R1_FB8 CAN_F6R1_FB8_Msk /*!< Filter bit 8 */
+#define CAN_F6R1_FB9_Pos (9U)
+#define CAN_F6R1_FB9_Msk (0x1U << CAN_F6R1_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F6R1_FB9 CAN_F6R1_FB9_Msk /*!< Filter bit 9 */
+#define CAN_F6R1_FB10_Pos (10U)
+#define CAN_F6R1_FB10_Msk (0x1U << CAN_F6R1_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F6R1_FB10 CAN_F6R1_FB10_Msk /*!< Filter bit 10 */
+#define CAN_F6R1_FB11_Pos (11U)
+#define CAN_F6R1_FB11_Msk (0x1U << CAN_F6R1_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F6R1_FB11 CAN_F6R1_FB11_Msk /*!< Filter bit 11 */
+#define CAN_F6R1_FB12_Pos (12U)
+#define CAN_F6R1_FB12_Msk (0x1U << CAN_F6R1_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F6R1_FB12 CAN_F6R1_FB12_Msk /*!< Filter bit 12 */
+#define CAN_F6R1_FB13_Pos (13U)
+#define CAN_F6R1_FB13_Msk (0x1U << CAN_F6R1_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F6R1_FB13 CAN_F6R1_FB13_Msk /*!< Filter bit 13 */
+#define CAN_F6R1_FB14_Pos (14U)
+#define CAN_F6R1_FB14_Msk (0x1U << CAN_F6R1_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F6R1_FB14 CAN_F6R1_FB14_Msk /*!< Filter bit 14 */
+#define CAN_F6R1_FB15_Pos (15U)
+#define CAN_F6R1_FB15_Msk (0x1U << CAN_F6R1_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F6R1_FB15 CAN_F6R1_FB15_Msk /*!< Filter bit 15 */
+#define CAN_F6R1_FB16_Pos (16U)
+#define CAN_F6R1_FB16_Msk (0x1U << CAN_F6R1_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F6R1_FB16 CAN_F6R1_FB16_Msk /*!< Filter bit 16 */
+#define CAN_F6R1_FB17_Pos (17U)
+#define CAN_F6R1_FB17_Msk (0x1U << CAN_F6R1_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F6R1_FB17 CAN_F6R1_FB17_Msk /*!< Filter bit 17 */
+#define CAN_F6R1_FB18_Pos (18U)
+#define CAN_F6R1_FB18_Msk (0x1U << CAN_F6R1_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F6R1_FB18 CAN_F6R1_FB18_Msk /*!< Filter bit 18 */
+#define CAN_F6R1_FB19_Pos (19U)
+#define CAN_F6R1_FB19_Msk (0x1U << CAN_F6R1_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F6R1_FB19 CAN_F6R1_FB19_Msk /*!< Filter bit 19 */
+#define CAN_F6R1_FB20_Pos (20U)
+#define CAN_F6R1_FB20_Msk (0x1U << CAN_F6R1_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F6R1_FB20 CAN_F6R1_FB20_Msk /*!< Filter bit 20 */
+#define CAN_F6R1_FB21_Pos (21U)
+#define CAN_F6R1_FB21_Msk (0x1U << CAN_F6R1_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F6R1_FB21 CAN_F6R1_FB21_Msk /*!< Filter bit 21 */
+#define CAN_F6R1_FB22_Pos (22U)
+#define CAN_F6R1_FB22_Msk (0x1U << CAN_F6R1_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F6R1_FB22 CAN_F6R1_FB22_Msk /*!< Filter bit 22 */
+#define CAN_F6R1_FB23_Pos (23U)
+#define CAN_F6R1_FB23_Msk (0x1U << CAN_F6R1_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F6R1_FB23 CAN_F6R1_FB23_Msk /*!< Filter bit 23 */
+#define CAN_F6R1_FB24_Pos (24U)
+#define CAN_F6R1_FB24_Msk (0x1U << CAN_F6R1_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F6R1_FB24 CAN_F6R1_FB24_Msk /*!< Filter bit 24 */
+#define CAN_F6R1_FB25_Pos (25U)
+#define CAN_F6R1_FB25_Msk (0x1U << CAN_F6R1_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F6R1_FB25 CAN_F6R1_FB25_Msk /*!< Filter bit 25 */
+#define CAN_F6R1_FB26_Pos (26U)
+#define CAN_F6R1_FB26_Msk (0x1U << CAN_F6R1_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F6R1_FB26 CAN_F6R1_FB26_Msk /*!< Filter bit 26 */
+#define CAN_F6R1_FB27_Pos (27U)
+#define CAN_F6R1_FB27_Msk (0x1U << CAN_F6R1_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F6R1_FB27 CAN_F6R1_FB27_Msk /*!< Filter bit 27 */
+#define CAN_F6R1_FB28_Pos (28U)
+#define CAN_F6R1_FB28_Msk (0x1U << CAN_F6R1_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F6R1_FB28 CAN_F6R1_FB28_Msk /*!< Filter bit 28 */
+#define CAN_F6R1_FB29_Pos (29U)
+#define CAN_F6R1_FB29_Msk (0x1U << CAN_F6R1_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F6R1_FB29 CAN_F6R1_FB29_Msk /*!< Filter bit 29 */
+#define CAN_F6R1_FB30_Pos (30U)
+#define CAN_F6R1_FB30_Msk (0x1U << CAN_F6R1_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F6R1_FB30 CAN_F6R1_FB30_Msk /*!< Filter bit 30 */
+#define CAN_F6R1_FB31_Pos (31U)
+#define CAN_F6R1_FB31_Msk (0x1U << CAN_F6R1_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F6R1_FB31 CAN_F6R1_FB31_Msk /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F7R1 register *******************/
+#define CAN_F7R1_FB0_Pos (0U)
+#define CAN_F7R1_FB0_Msk (0x1U << CAN_F7R1_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F7R1_FB0 CAN_F7R1_FB0_Msk /*!< Filter bit 0 */
+#define CAN_F7R1_FB1_Pos (1U)
+#define CAN_F7R1_FB1_Msk (0x1U << CAN_F7R1_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F7R1_FB1 CAN_F7R1_FB1_Msk /*!< Filter bit 1 */
+#define CAN_F7R1_FB2_Pos (2U)
+#define CAN_F7R1_FB2_Msk (0x1U << CAN_F7R1_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F7R1_FB2 CAN_F7R1_FB2_Msk /*!< Filter bit 2 */
+#define CAN_F7R1_FB3_Pos (3U)
+#define CAN_F7R1_FB3_Msk (0x1U << CAN_F7R1_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F7R1_FB3 CAN_F7R1_FB3_Msk /*!< Filter bit 3 */
+#define CAN_F7R1_FB4_Pos (4U)
+#define CAN_F7R1_FB4_Msk (0x1U << CAN_F7R1_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F7R1_FB4 CAN_F7R1_FB4_Msk /*!< Filter bit 4 */
+#define CAN_F7R1_FB5_Pos (5U)
+#define CAN_F7R1_FB5_Msk (0x1U << CAN_F7R1_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F7R1_FB5 CAN_F7R1_FB5_Msk /*!< Filter bit 5 */
+#define CAN_F7R1_FB6_Pos (6U)
+#define CAN_F7R1_FB6_Msk (0x1U << CAN_F7R1_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F7R1_FB6 CAN_F7R1_FB6_Msk /*!< Filter bit 6 */
+#define CAN_F7R1_FB7_Pos (7U)
+#define CAN_F7R1_FB7_Msk (0x1U << CAN_F7R1_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F7R1_FB7 CAN_F7R1_FB7_Msk /*!< Filter bit 7 */
+#define CAN_F7R1_FB8_Pos (8U)
+#define CAN_F7R1_FB8_Msk (0x1U << CAN_F7R1_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F7R1_FB8 CAN_F7R1_FB8_Msk /*!< Filter bit 8 */
+#define CAN_F7R1_FB9_Pos (9U)
+#define CAN_F7R1_FB9_Msk (0x1U << CAN_F7R1_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F7R1_FB9 CAN_F7R1_FB9_Msk /*!< Filter bit 9 */
+#define CAN_F7R1_FB10_Pos (10U)
+#define CAN_F7R1_FB10_Msk (0x1U << CAN_F7R1_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F7R1_FB10 CAN_F7R1_FB10_Msk /*!< Filter bit 10 */
+#define CAN_F7R1_FB11_Pos (11U)
+#define CAN_F7R1_FB11_Msk (0x1U << CAN_F7R1_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F7R1_FB11 CAN_F7R1_FB11_Msk /*!< Filter bit 11 */
+#define CAN_F7R1_FB12_Pos (12U)
+#define CAN_F7R1_FB12_Msk (0x1U << CAN_F7R1_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F7R1_FB12 CAN_F7R1_FB12_Msk /*!< Filter bit 12 */
+#define CAN_F7R1_FB13_Pos (13U)
+#define CAN_F7R1_FB13_Msk (0x1U << CAN_F7R1_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F7R1_FB13 CAN_F7R1_FB13_Msk /*!< Filter bit 13 */
+#define CAN_F7R1_FB14_Pos (14U)
+#define CAN_F7R1_FB14_Msk (0x1U << CAN_F7R1_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F7R1_FB14 CAN_F7R1_FB14_Msk /*!< Filter bit 14 */
+#define CAN_F7R1_FB15_Pos (15U)
+#define CAN_F7R1_FB15_Msk (0x1U << CAN_F7R1_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F7R1_FB15 CAN_F7R1_FB15_Msk /*!< Filter bit 15 */
+#define CAN_F7R1_FB16_Pos (16U)
+#define CAN_F7R1_FB16_Msk (0x1U << CAN_F7R1_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F7R1_FB16 CAN_F7R1_FB16_Msk /*!< Filter bit 16 */
+#define CAN_F7R1_FB17_Pos (17U)
+#define CAN_F7R1_FB17_Msk (0x1U << CAN_F7R1_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F7R1_FB17 CAN_F7R1_FB17_Msk /*!< Filter bit 17 */
+#define CAN_F7R1_FB18_Pos (18U)
+#define CAN_F7R1_FB18_Msk (0x1U << CAN_F7R1_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F7R1_FB18 CAN_F7R1_FB18_Msk /*!< Filter bit 18 */
+#define CAN_F7R1_FB19_Pos (19U)
+#define CAN_F7R1_FB19_Msk (0x1U << CAN_F7R1_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F7R1_FB19 CAN_F7R1_FB19_Msk /*!< Filter bit 19 */
+#define CAN_F7R1_FB20_Pos (20U)
+#define CAN_F7R1_FB20_Msk (0x1U << CAN_F7R1_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F7R1_FB20 CAN_F7R1_FB20_Msk /*!< Filter bit 20 */
+#define CAN_F7R1_FB21_Pos (21U)
+#define CAN_F7R1_FB21_Msk (0x1U << CAN_F7R1_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F7R1_FB21 CAN_F7R1_FB21_Msk /*!< Filter bit 21 */
+#define CAN_F7R1_FB22_Pos (22U)
+#define CAN_F7R1_FB22_Msk (0x1U << CAN_F7R1_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F7R1_FB22 CAN_F7R1_FB22_Msk /*!< Filter bit 22 */
+#define CAN_F7R1_FB23_Pos (23U)
+#define CAN_F7R1_FB23_Msk (0x1U << CAN_F7R1_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F7R1_FB23 CAN_F7R1_FB23_Msk /*!< Filter bit 23 */
+#define CAN_F7R1_FB24_Pos (24U)
+#define CAN_F7R1_FB24_Msk (0x1U << CAN_F7R1_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F7R1_FB24 CAN_F7R1_FB24_Msk /*!< Filter bit 24 */
+#define CAN_F7R1_FB25_Pos (25U)
+#define CAN_F7R1_FB25_Msk (0x1U << CAN_F7R1_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F7R1_FB25 CAN_F7R1_FB25_Msk /*!< Filter bit 25 */
+#define CAN_F7R1_FB26_Pos (26U)
+#define CAN_F7R1_FB26_Msk (0x1U << CAN_F7R1_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F7R1_FB26 CAN_F7R1_FB26_Msk /*!< Filter bit 26 */
+#define CAN_F7R1_FB27_Pos (27U)
+#define CAN_F7R1_FB27_Msk (0x1U << CAN_F7R1_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F7R1_FB27 CAN_F7R1_FB27_Msk /*!< Filter bit 27 */
+#define CAN_F7R1_FB28_Pos (28U)
+#define CAN_F7R1_FB28_Msk (0x1U << CAN_F7R1_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F7R1_FB28 CAN_F7R1_FB28_Msk /*!< Filter bit 28 */
+#define CAN_F7R1_FB29_Pos (29U)
+#define CAN_F7R1_FB29_Msk (0x1U << CAN_F7R1_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F7R1_FB29 CAN_F7R1_FB29_Msk /*!< Filter bit 29 */
+#define CAN_F7R1_FB30_Pos (30U)
+#define CAN_F7R1_FB30_Msk (0x1U << CAN_F7R1_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F7R1_FB30 CAN_F7R1_FB30_Msk /*!< Filter bit 30 */
+#define CAN_F7R1_FB31_Pos (31U)
+#define CAN_F7R1_FB31_Msk (0x1U << CAN_F7R1_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F7R1_FB31 CAN_F7R1_FB31_Msk /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F8R1 register *******************/
+#define CAN_F8R1_FB0_Pos (0U)
+#define CAN_F8R1_FB0_Msk (0x1U << CAN_F8R1_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F8R1_FB0 CAN_F8R1_FB0_Msk /*!< Filter bit 0 */
+#define CAN_F8R1_FB1_Pos (1U)
+#define CAN_F8R1_FB1_Msk (0x1U << CAN_F8R1_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F8R1_FB1 CAN_F8R1_FB1_Msk /*!< Filter bit 1 */
+#define CAN_F8R1_FB2_Pos (2U)
+#define CAN_F8R1_FB2_Msk (0x1U << CAN_F8R1_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F8R1_FB2 CAN_F8R1_FB2_Msk /*!< Filter bit 2 */
+#define CAN_F8R1_FB3_Pos (3U)
+#define CAN_F8R1_FB3_Msk (0x1U << CAN_F8R1_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F8R1_FB3 CAN_F8R1_FB3_Msk /*!< Filter bit 3 */
+#define CAN_F8R1_FB4_Pos (4U)
+#define CAN_F8R1_FB4_Msk (0x1U << CAN_F8R1_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F8R1_FB4 CAN_F8R1_FB4_Msk /*!< Filter bit 4 */
+#define CAN_F8R1_FB5_Pos (5U)
+#define CAN_F8R1_FB5_Msk (0x1U << CAN_F8R1_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F8R1_FB5 CAN_F8R1_FB5_Msk /*!< Filter bit 5 */
+#define CAN_F8R1_FB6_Pos (6U)
+#define CAN_F8R1_FB6_Msk (0x1U << CAN_F8R1_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F8R1_FB6 CAN_F8R1_FB6_Msk /*!< Filter bit 6 */
+#define CAN_F8R1_FB7_Pos (7U)
+#define CAN_F8R1_FB7_Msk (0x1U << CAN_F8R1_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F8R1_FB7 CAN_F8R1_FB7_Msk /*!< Filter bit 7 */
+#define CAN_F8R1_FB8_Pos (8U)
+#define CAN_F8R1_FB8_Msk (0x1U << CAN_F8R1_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F8R1_FB8 CAN_F8R1_FB8_Msk /*!< Filter bit 8 */
+#define CAN_F8R1_FB9_Pos (9U)
+#define CAN_F8R1_FB9_Msk (0x1U << CAN_F8R1_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F8R1_FB9 CAN_F8R1_FB9_Msk /*!< Filter bit 9 */
+#define CAN_F8R1_FB10_Pos (10U)
+#define CAN_F8R1_FB10_Msk (0x1U << CAN_F8R1_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F8R1_FB10 CAN_F8R1_FB10_Msk /*!< Filter bit 10 */
+#define CAN_F8R1_FB11_Pos (11U)
+#define CAN_F8R1_FB11_Msk (0x1U << CAN_F8R1_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F8R1_FB11 CAN_F8R1_FB11_Msk /*!< Filter bit 11 */
+#define CAN_F8R1_FB12_Pos (12U)
+#define CAN_F8R1_FB12_Msk (0x1U << CAN_F8R1_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F8R1_FB12 CAN_F8R1_FB12_Msk /*!< Filter bit 12 */
+#define CAN_F8R1_FB13_Pos (13U)
+#define CAN_F8R1_FB13_Msk (0x1U << CAN_F8R1_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F8R1_FB13 CAN_F8R1_FB13_Msk /*!< Filter bit 13 */
+#define CAN_F8R1_FB14_Pos (14U)
+#define CAN_F8R1_FB14_Msk (0x1U << CAN_F8R1_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F8R1_FB14 CAN_F8R1_FB14_Msk /*!< Filter bit 14 */
+#define CAN_F8R1_FB15_Pos (15U)
+#define CAN_F8R1_FB15_Msk (0x1U << CAN_F8R1_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F8R1_FB15 CAN_F8R1_FB15_Msk /*!< Filter bit 15 */
+#define CAN_F8R1_FB16_Pos (16U)
+#define CAN_F8R1_FB16_Msk (0x1U << CAN_F8R1_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F8R1_FB16 CAN_F8R1_FB16_Msk /*!< Filter bit 16 */
+#define CAN_F8R1_FB17_Pos (17U)
+#define CAN_F8R1_FB17_Msk (0x1U << CAN_F8R1_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F8R1_FB17 CAN_F8R1_FB17_Msk /*!< Filter bit 17 */
+#define CAN_F8R1_FB18_Pos (18U)
+#define CAN_F8R1_FB18_Msk (0x1U << CAN_F8R1_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F8R1_FB18 CAN_F8R1_FB18_Msk /*!< Filter bit 18 */
+#define CAN_F8R1_FB19_Pos (19U)
+#define CAN_F8R1_FB19_Msk (0x1U << CAN_F8R1_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F8R1_FB19 CAN_F8R1_FB19_Msk /*!< Filter bit 19 */
+#define CAN_F8R1_FB20_Pos (20U)
+#define CAN_F8R1_FB20_Msk (0x1U << CAN_F8R1_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F8R1_FB20 CAN_F8R1_FB20_Msk /*!< Filter bit 20 */
+#define CAN_F8R1_FB21_Pos (21U)
+#define CAN_F8R1_FB21_Msk (0x1U << CAN_F8R1_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F8R1_FB21 CAN_F8R1_FB21_Msk /*!< Filter bit 21 */
+#define CAN_F8R1_FB22_Pos (22U)
+#define CAN_F8R1_FB22_Msk (0x1U << CAN_F8R1_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F8R1_FB22 CAN_F8R1_FB22_Msk /*!< Filter bit 22 */
+#define CAN_F8R1_FB23_Pos (23U)
+#define CAN_F8R1_FB23_Msk (0x1U << CAN_F8R1_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F8R1_FB23 CAN_F8R1_FB23_Msk /*!< Filter bit 23 */
+#define CAN_F8R1_FB24_Pos (24U)
+#define CAN_F8R1_FB24_Msk (0x1U << CAN_F8R1_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F8R1_FB24 CAN_F8R1_FB24_Msk /*!< Filter bit 24 */
+#define CAN_F8R1_FB25_Pos (25U)
+#define CAN_F8R1_FB25_Msk (0x1U << CAN_F8R1_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F8R1_FB25 CAN_F8R1_FB25_Msk /*!< Filter bit 25 */
+#define CAN_F8R1_FB26_Pos (26U)
+#define CAN_F8R1_FB26_Msk (0x1U << CAN_F8R1_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F8R1_FB26 CAN_F8R1_FB26_Msk /*!< Filter bit 26 */
+#define CAN_F8R1_FB27_Pos (27U)
+#define CAN_F8R1_FB27_Msk (0x1U << CAN_F8R1_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F8R1_FB27 CAN_F8R1_FB27_Msk /*!< Filter bit 27 */
+#define CAN_F8R1_FB28_Pos (28U)
+#define CAN_F8R1_FB28_Msk (0x1U << CAN_F8R1_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F8R1_FB28 CAN_F8R1_FB28_Msk /*!< Filter bit 28 */
+#define CAN_F8R1_FB29_Pos (29U)
+#define CAN_F8R1_FB29_Msk (0x1U << CAN_F8R1_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F8R1_FB29 CAN_F8R1_FB29_Msk /*!< Filter bit 29 */
+#define CAN_F8R1_FB30_Pos (30U)
+#define CAN_F8R1_FB30_Msk (0x1U << CAN_F8R1_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F8R1_FB30 CAN_F8R1_FB30_Msk /*!< Filter bit 30 */
+#define CAN_F8R1_FB31_Pos (31U)
+#define CAN_F8R1_FB31_Msk (0x1U << CAN_F8R1_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F8R1_FB31 CAN_F8R1_FB31_Msk /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F9R1 register *******************/
+#define CAN_F9R1_FB0_Pos (0U)
+#define CAN_F9R1_FB0_Msk (0x1U << CAN_F9R1_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F9R1_FB0 CAN_F9R1_FB0_Msk /*!< Filter bit 0 */
+#define CAN_F9R1_FB1_Pos (1U)
+#define CAN_F9R1_FB1_Msk (0x1U << CAN_F9R1_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F9R1_FB1 CAN_F9R1_FB1_Msk /*!< Filter bit 1 */
+#define CAN_F9R1_FB2_Pos (2U)
+#define CAN_F9R1_FB2_Msk (0x1U << CAN_F9R1_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F9R1_FB2 CAN_F9R1_FB2_Msk /*!< Filter bit 2 */
+#define CAN_F9R1_FB3_Pos (3U)
+#define CAN_F9R1_FB3_Msk (0x1U << CAN_F9R1_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F9R1_FB3 CAN_F9R1_FB3_Msk /*!< Filter bit 3 */
+#define CAN_F9R1_FB4_Pos (4U)
+#define CAN_F9R1_FB4_Msk (0x1U << CAN_F9R1_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F9R1_FB4 CAN_F9R1_FB4_Msk /*!< Filter bit 4 */
+#define CAN_F9R1_FB5_Pos (5U)
+#define CAN_F9R1_FB5_Msk (0x1U << CAN_F9R1_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F9R1_FB5 CAN_F9R1_FB5_Msk /*!< Filter bit 5 */
+#define CAN_F9R1_FB6_Pos (6U)
+#define CAN_F9R1_FB6_Msk (0x1U << CAN_F9R1_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F9R1_FB6 CAN_F9R1_FB6_Msk /*!< Filter bit 6 */
+#define CAN_F9R1_FB7_Pos (7U)
+#define CAN_F9R1_FB7_Msk (0x1U << CAN_F9R1_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F9R1_FB7 CAN_F9R1_FB7_Msk /*!< Filter bit 7 */
+#define CAN_F9R1_FB8_Pos (8U)
+#define CAN_F9R1_FB8_Msk (0x1U << CAN_F9R1_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F9R1_FB8 CAN_F9R1_FB8_Msk /*!< Filter bit 8 */
+#define CAN_F9R1_FB9_Pos (9U)
+#define CAN_F9R1_FB9_Msk (0x1U << CAN_F9R1_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F9R1_FB9 CAN_F9R1_FB9_Msk /*!< Filter bit 9 */
+#define CAN_F9R1_FB10_Pos (10U)
+#define CAN_F9R1_FB10_Msk (0x1U << CAN_F9R1_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F9R1_FB10 CAN_F9R1_FB10_Msk /*!< Filter bit 10 */
+#define CAN_F9R1_FB11_Pos (11U)
+#define CAN_F9R1_FB11_Msk (0x1U << CAN_F9R1_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F9R1_FB11 CAN_F9R1_FB11_Msk /*!< Filter bit 11 */
+#define CAN_F9R1_FB12_Pos (12U)
+#define CAN_F9R1_FB12_Msk (0x1U << CAN_F9R1_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F9R1_FB12 CAN_F9R1_FB12_Msk /*!< Filter bit 12 */
+#define CAN_F9R1_FB13_Pos (13U)
+#define CAN_F9R1_FB13_Msk (0x1U << CAN_F9R1_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F9R1_FB13 CAN_F9R1_FB13_Msk /*!< Filter bit 13 */
+#define CAN_F9R1_FB14_Pos (14U)
+#define CAN_F9R1_FB14_Msk (0x1U << CAN_F9R1_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F9R1_FB14 CAN_F9R1_FB14_Msk /*!< Filter bit 14 */
+#define CAN_F9R1_FB15_Pos (15U)
+#define CAN_F9R1_FB15_Msk (0x1U << CAN_F9R1_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F9R1_FB15 CAN_F9R1_FB15_Msk /*!< Filter bit 15 */
+#define CAN_F9R1_FB16_Pos (16U)
+#define CAN_F9R1_FB16_Msk (0x1U << CAN_F9R1_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F9R1_FB16 CAN_F9R1_FB16_Msk /*!< Filter bit 16 */
+#define CAN_F9R1_FB17_Pos (17U)
+#define CAN_F9R1_FB17_Msk (0x1U << CAN_F9R1_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F9R1_FB17 CAN_F9R1_FB17_Msk /*!< Filter bit 17 */
+#define CAN_F9R1_FB18_Pos (18U)
+#define CAN_F9R1_FB18_Msk (0x1U << CAN_F9R1_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F9R1_FB18 CAN_F9R1_FB18_Msk /*!< Filter bit 18 */
+#define CAN_F9R1_FB19_Pos (19U)
+#define CAN_F9R1_FB19_Msk (0x1U << CAN_F9R1_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F9R1_FB19 CAN_F9R1_FB19_Msk /*!< Filter bit 19 */
+#define CAN_F9R1_FB20_Pos (20U)
+#define CAN_F9R1_FB20_Msk (0x1U << CAN_F9R1_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F9R1_FB20 CAN_F9R1_FB20_Msk /*!< Filter bit 20 */
+#define CAN_F9R1_FB21_Pos (21U)
+#define CAN_F9R1_FB21_Msk (0x1U << CAN_F9R1_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F9R1_FB21 CAN_F9R1_FB21_Msk /*!< Filter bit 21 */
+#define CAN_F9R1_FB22_Pos (22U)
+#define CAN_F9R1_FB22_Msk (0x1U << CAN_F9R1_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F9R1_FB22 CAN_F9R1_FB22_Msk /*!< Filter bit 22 */
+#define CAN_F9R1_FB23_Pos (23U)
+#define CAN_F9R1_FB23_Msk (0x1U << CAN_F9R1_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F9R1_FB23 CAN_F9R1_FB23_Msk /*!< Filter bit 23 */
+#define CAN_F9R1_FB24_Pos (24U)
+#define CAN_F9R1_FB24_Msk (0x1U << CAN_F9R1_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F9R1_FB24 CAN_F9R1_FB24_Msk /*!< Filter bit 24 */
+#define CAN_F9R1_FB25_Pos (25U)
+#define CAN_F9R1_FB25_Msk (0x1U << CAN_F9R1_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F9R1_FB25 CAN_F9R1_FB25_Msk /*!< Filter bit 25 */
+#define CAN_F9R1_FB26_Pos (26U)
+#define CAN_F9R1_FB26_Msk (0x1U << CAN_F9R1_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F9R1_FB26 CAN_F9R1_FB26_Msk /*!< Filter bit 26 */
+#define CAN_F9R1_FB27_Pos (27U)
+#define CAN_F9R1_FB27_Msk (0x1U << CAN_F9R1_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F9R1_FB27 CAN_F9R1_FB27_Msk /*!< Filter bit 27 */
+#define CAN_F9R1_FB28_Pos (28U)
+#define CAN_F9R1_FB28_Msk (0x1U << CAN_F9R1_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F9R1_FB28 CAN_F9R1_FB28_Msk /*!< Filter bit 28 */
+#define CAN_F9R1_FB29_Pos (29U)
+#define CAN_F9R1_FB29_Msk (0x1U << CAN_F9R1_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F9R1_FB29 CAN_F9R1_FB29_Msk /*!< Filter bit 29 */
+#define CAN_F9R1_FB30_Pos (30U)
+#define CAN_F9R1_FB30_Msk (0x1U << CAN_F9R1_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F9R1_FB30 CAN_F9R1_FB30_Msk /*!< Filter bit 30 */
+#define CAN_F9R1_FB31_Pos (31U)
+#define CAN_F9R1_FB31_Msk (0x1U << CAN_F9R1_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F9R1_FB31 CAN_F9R1_FB31_Msk /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F10R1 register ******************/
+#define CAN_F10R1_FB0_Pos (0U)
+#define CAN_F10R1_FB0_Msk (0x1U << CAN_F10R1_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F10R1_FB0 CAN_F10R1_FB0_Msk /*!< Filter bit 0 */
+#define CAN_F10R1_FB1_Pos (1U)
+#define CAN_F10R1_FB1_Msk (0x1U << CAN_F10R1_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F10R1_FB1 CAN_F10R1_FB1_Msk /*!< Filter bit 1 */
+#define CAN_F10R1_FB2_Pos (2U)
+#define CAN_F10R1_FB2_Msk (0x1U << CAN_F10R1_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F10R1_FB2 CAN_F10R1_FB2_Msk /*!< Filter bit 2 */
+#define CAN_F10R1_FB3_Pos (3U)
+#define CAN_F10R1_FB3_Msk (0x1U << CAN_F10R1_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F10R1_FB3 CAN_F10R1_FB3_Msk /*!< Filter bit 3 */
+#define CAN_F10R1_FB4_Pos (4U)
+#define CAN_F10R1_FB4_Msk (0x1U << CAN_F10R1_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F10R1_FB4 CAN_F10R1_FB4_Msk /*!< Filter bit 4 */
+#define CAN_F10R1_FB5_Pos (5U)
+#define CAN_F10R1_FB5_Msk (0x1U << CAN_F10R1_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F10R1_FB5 CAN_F10R1_FB5_Msk /*!< Filter bit 5 */
+#define CAN_F10R1_FB6_Pos (6U)
+#define CAN_F10R1_FB6_Msk (0x1U << CAN_F10R1_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F10R1_FB6 CAN_F10R1_FB6_Msk /*!< Filter bit 6 */
+#define CAN_F10R1_FB7_Pos (7U)
+#define CAN_F10R1_FB7_Msk (0x1U << CAN_F10R1_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F10R1_FB7 CAN_F10R1_FB7_Msk /*!< Filter bit 7 */
+#define CAN_F10R1_FB8_Pos (8U)
+#define CAN_F10R1_FB8_Msk (0x1U << CAN_F10R1_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F10R1_FB8 CAN_F10R1_FB8_Msk /*!< Filter bit 8 */
+#define CAN_F10R1_FB9_Pos (9U)
+#define CAN_F10R1_FB9_Msk (0x1U << CAN_F10R1_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F10R1_FB9 CAN_F10R1_FB9_Msk /*!< Filter bit 9 */
+#define CAN_F10R1_FB10_Pos (10U)
+#define CAN_F10R1_FB10_Msk (0x1U << CAN_F10R1_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F10R1_FB10 CAN_F10R1_FB10_Msk /*!< Filter bit 10 */
+#define CAN_F10R1_FB11_Pos (11U)
+#define CAN_F10R1_FB11_Msk (0x1U << CAN_F10R1_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F10R1_FB11 CAN_F10R1_FB11_Msk /*!< Filter bit 11 */
+#define CAN_F10R1_FB12_Pos (12U)
+#define CAN_F10R1_FB12_Msk (0x1U << CAN_F10R1_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F10R1_FB12 CAN_F10R1_FB12_Msk /*!< Filter bit 12 */
+#define CAN_F10R1_FB13_Pos (13U)
+#define CAN_F10R1_FB13_Msk (0x1U << CAN_F10R1_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F10R1_FB13 CAN_F10R1_FB13_Msk /*!< Filter bit 13 */
+#define CAN_F10R1_FB14_Pos (14U)
+#define CAN_F10R1_FB14_Msk (0x1U << CAN_F10R1_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F10R1_FB14 CAN_F10R1_FB14_Msk /*!< Filter bit 14 */
+#define CAN_F10R1_FB15_Pos (15U)
+#define CAN_F10R1_FB15_Msk (0x1U << CAN_F10R1_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F10R1_FB15 CAN_F10R1_FB15_Msk /*!< Filter bit 15 */
+#define CAN_F10R1_FB16_Pos (16U)
+#define CAN_F10R1_FB16_Msk (0x1U << CAN_F10R1_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F10R1_FB16 CAN_F10R1_FB16_Msk /*!< Filter bit 16 */
+#define CAN_F10R1_FB17_Pos (17U)
+#define CAN_F10R1_FB17_Msk (0x1U << CAN_F10R1_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F10R1_FB17 CAN_F10R1_FB17_Msk /*!< Filter bit 17 */
+#define CAN_F10R1_FB18_Pos (18U)
+#define CAN_F10R1_FB18_Msk (0x1U << CAN_F10R1_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F10R1_FB18 CAN_F10R1_FB18_Msk /*!< Filter bit 18 */
+#define CAN_F10R1_FB19_Pos (19U)
+#define CAN_F10R1_FB19_Msk (0x1U << CAN_F10R1_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F10R1_FB19 CAN_F10R1_FB19_Msk /*!< Filter bit 19 */
+#define CAN_F10R1_FB20_Pos (20U)
+#define CAN_F10R1_FB20_Msk (0x1U << CAN_F10R1_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F10R1_FB20 CAN_F10R1_FB20_Msk /*!< Filter bit 20 */
+#define CAN_F10R1_FB21_Pos (21U)
+#define CAN_F10R1_FB21_Msk (0x1U << CAN_F10R1_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F10R1_FB21 CAN_F10R1_FB21_Msk /*!< Filter bit 21 */
+#define CAN_F10R1_FB22_Pos (22U)
+#define CAN_F10R1_FB22_Msk (0x1U << CAN_F10R1_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F10R1_FB22 CAN_F10R1_FB22_Msk /*!< Filter bit 22 */
+#define CAN_F10R1_FB23_Pos (23U)
+#define CAN_F10R1_FB23_Msk (0x1U << CAN_F10R1_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F10R1_FB23 CAN_F10R1_FB23_Msk /*!< Filter bit 23 */
+#define CAN_F10R1_FB24_Pos (24U)
+#define CAN_F10R1_FB24_Msk (0x1U << CAN_F10R1_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F10R1_FB24 CAN_F10R1_FB24_Msk /*!< Filter bit 24 */
+#define CAN_F10R1_FB25_Pos (25U)
+#define CAN_F10R1_FB25_Msk (0x1U << CAN_F10R1_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F10R1_FB25 CAN_F10R1_FB25_Msk /*!< Filter bit 25 */
+#define CAN_F10R1_FB26_Pos (26U)
+#define CAN_F10R1_FB26_Msk (0x1U << CAN_F10R1_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F10R1_FB26 CAN_F10R1_FB26_Msk /*!< Filter bit 26 */
+#define CAN_F10R1_FB27_Pos (27U)
+#define CAN_F10R1_FB27_Msk (0x1U << CAN_F10R1_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F10R1_FB27 CAN_F10R1_FB27_Msk /*!< Filter bit 27 */
+#define CAN_F10R1_FB28_Pos (28U)
+#define CAN_F10R1_FB28_Msk (0x1U << CAN_F10R1_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F10R1_FB28 CAN_F10R1_FB28_Msk /*!< Filter bit 28 */
+#define CAN_F10R1_FB29_Pos (29U)
+#define CAN_F10R1_FB29_Msk (0x1U << CAN_F10R1_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F10R1_FB29 CAN_F10R1_FB29_Msk /*!< Filter bit 29 */
+#define CAN_F10R1_FB30_Pos (30U)
+#define CAN_F10R1_FB30_Msk (0x1U << CAN_F10R1_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F10R1_FB30 CAN_F10R1_FB30_Msk /*!< Filter bit 30 */
+#define CAN_F10R1_FB31_Pos (31U)
+#define CAN_F10R1_FB31_Msk (0x1U << CAN_F10R1_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F10R1_FB31 CAN_F10R1_FB31_Msk /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F11R1 register ******************/
+#define CAN_F11R1_FB0_Pos (0U)
+#define CAN_F11R1_FB0_Msk (0x1U << CAN_F11R1_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F11R1_FB0 CAN_F11R1_FB0_Msk /*!< Filter bit 0 */
+#define CAN_F11R1_FB1_Pos (1U)
+#define CAN_F11R1_FB1_Msk (0x1U << CAN_F11R1_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F11R1_FB1 CAN_F11R1_FB1_Msk /*!< Filter bit 1 */
+#define CAN_F11R1_FB2_Pos (2U)
+#define CAN_F11R1_FB2_Msk (0x1U << CAN_F11R1_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F11R1_FB2 CAN_F11R1_FB2_Msk /*!< Filter bit 2 */
+#define CAN_F11R1_FB3_Pos (3U)
+#define CAN_F11R1_FB3_Msk (0x1U << CAN_F11R1_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F11R1_FB3 CAN_F11R1_FB3_Msk /*!< Filter bit 3 */
+#define CAN_F11R1_FB4_Pos (4U)
+#define CAN_F11R1_FB4_Msk (0x1U << CAN_F11R1_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F11R1_FB4 CAN_F11R1_FB4_Msk /*!< Filter bit 4 */
+#define CAN_F11R1_FB5_Pos (5U)
+#define CAN_F11R1_FB5_Msk (0x1U << CAN_F11R1_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F11R1_FB5 CAN_F11R1_FB5_Msk /*!< Filter bit 5 */
+#define CAN_F11R1_FB6_Pos (6U)
+#define CAN_F11R1_FB6_Msk (0x1U << CAN_F11R1_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F11R1_FB6 CAN_F11R1_FB6_Msk /*!< Filter bit 6 */
+#define CAN_F11R1_FB7_Pos (7U)
+#define CAN_F11R1_FB7_Msk (0x1U << CAN_F11R1_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F11R1_FB7 CAN_F11R1_FB7_Msk /*!< Filter bit 7 */
+#define CAN_F11R1_FB8_Pos (8U)
+#define CAN_F11R1_FB8_Msk (0x1U << CAN_F11R1_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F11R1_FB8 CAN_F11R1_FB8_Msk /*!< Filter bit 8 */
+#define CAN_F11R1_FB9_Pos (9U)
+#define CAN_F11R1_FB9_Msk (0x1U << CAN_F11R1_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F11R1_FB9 CAN_F11R1_FB9_Msk /*!< Filter bit 9 */
+#define CAN_F11R1_FB10_Pos (10U)
+#define CAN_F11R1_FB10_Msk (0x1U << CAN_F11R1_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F11R1_FB10 CAN_F11R1_FB10_Msk /*!< Filter bit 10 */
+#define CAN_F11R1_FB11_Pos (11U)
+#define CAN_F11R1_FB11_Msk (0x1U << CAN_F11R1_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F11R1_FB11 CAN_F11R1_FB11_Msk /*!< Filter bit 11 */
+#define CAN_F11R1_FB12_Pos (12U)
+#define CAN_F11R1_FB12_Msk (0x1U << CAN_F11R1_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F11R1_FB12 CAN_F11R1_FB12_Msk /*!< Filter bit 12 */
+#define CAN_F11R1_FB13_Pos (13U)
+#define CAN_F11R1_FB13_Msk (0x1U << CAN_F11R1_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F11R1_FB13 CAN_F11R1_FB13_Msk /*!< Filter bit 13 */
+#define CAN_F11R1_FB14_Pos (14U)
+#define CAN_F11R1_FB14_Msk (0x1U << CAN_F11R1_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F11R1_FB14 CAN_F11R1_FB14_Msk /*!< Filter bit 14 */
+#define CAN_F11R1_FB15_Pos (15U)
+#define CAN_F11R1_FB15_Msk (0x1U << CAN_F11R1_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F11R1_FB15 CAN_F11R1_FB15_Msk /*!< Filter bit 15 */
+#define CAN_F11R1_FB16_Pos (16U)
+#define CAN_F11R1_FB16_Msk (0x1U << CAN_F11R1_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F11R1_FB16 CAN_F11R1_FB16_Msk /*!< Filter bit 16 */
+#define CAN_F11R1_FB17_Pos (17U)
+#define CAN_F11R1_FB17_Msk (0x1U << CAN_F11R1_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F11R1_FB17 CAN_F11R1_FB17_Msk /*!< Filter bit 17 */
+#define CAN_F11R1_FB18_Pos (18U)
+#define CAN_F11R1_FB18_Msk (0x1U << CAN_F11R1_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F11R1_FB18 CAN_F11R1_FB18_Msk /*!< Filter bit 18 */
+#define CAN_F11R1_FB19_Pos (19U)
+#define CAN_F11R1_FB19_Msk (0x1U << CAN_F11R1_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F11R1_FB19 CAN_F11R1_FB19_Msk /*!< Filter bit 19 */
+#define CAN_F11R1_FB20_Pos (20U)
+#define CAN_F11R1_FB20_Msk (0x1U << CAN_F11R1_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F11R1_FB20 CAN_F11R1_FB20_Msk /*!< Filter bit 20 */
+#define CAN_F11R1_FB21_Pos (21U)
+#define CAN_F11R1_FB21_Msk (0x1U << CAN_F11R1_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F11R1_FB21 CAN_F11R1_FB21_Msk /*!< Filter bit 21 */
+#define CAN_F11R1_FB22_Pos (22U)
+#define CAN_F11R1_FB22_Msk (0x1U << CAN_F11R1_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F11R1_FB22 CAN_F11R1_FB22_Msk /*!< Filter bit 22 */
+#define CAN_F11R1_FB23_Pos (23U)
+#define CAN_F11R1_FB23_Msk (0x1U << CAN_F11R1_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F11R1_FB23 CAN_F11R1_FB23_Msk /*!< Filter bit 23 */
+#define CAN_F11R1_FB24_Pos (24U)
+#define CAN_F11R1_FB24_Msk (0x1U << CAN_F11R1_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F11R1_FB24 CAN_F11R1_FB24_Msk /*!< Filter bit 24 */
+#define CAN_F11R1_FB25_Pos (25U)
+#define CAN_F11R1_FB25_Msk (0x1U << CAN_F11R1_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F11R1_FB25 CAN_F11R1_FB25_Msk /*!< Filter bit 25 */
+#define CAN_F11R1_FB26_Pos (26U)
+#define CAN_F11R1_FB26_Msk (0x1U << CAN_F11R1_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F11R1_FB26 CAN_F11R1_FB26_Msk /*!< Filter bit 26 */
+#define CAN_F11R1_FB27_Pos (27U)
+#define CAN_F11R1_FB27_Msk (0x1U << CAN_F11R1_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F11R1_FB27 CAN_F11R1_FB27_Msk /*!< Filter bit 27 */
+#define CAN_F11R1_FB28_Pos (28U)
+#define CAN_F11R1_FB28_Msk (0x1U << CAN_F11R1_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F11R1_FB28 CAN_F11R1_FB28_Msk /*!< Filter bit 28 */
+#define CAN_F11R1_FB29_Pos (29U)
+#define CAN_F11R1_FB29_Msk (0x1U << CAN_F11R1_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F11R1_FB29 CAN_F11R1_FB29_Msk /*!< Filter bit 29 */
+#define CAN_F11R1_FB30_Pos (30U)
+#define CAN_F11R1_FB30_Msk (0x1U << CAN_F11R1_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F11R1_FB30 CAN_F11R1_FB30_Msk /*!< Filter bit 30 */
+#define CAN_F11R1_FB31_Pos (31U)
+#define CAN_F11R1_FB31_Msk (0x1U << CAN_F11R1_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F11R1_FB31 CAN_F11R1_FB31_Msk /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F12R1 register ******************/
+#define CAN_F12R1_FB0_Pos (0U)
+#define CAN_F12R1_FB0_Msk (0x1U << CAN_F12R1_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F12R1_FB0 CAN_F12R1_FB0_Msk /*!< Filter bit 0 */
+#define CAN_F12R1_FB1_Pos (1U)
+#define CAN_F12R1_FB1_Msk (0x1U << CAN_F12R1_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F12R1_FB1 CAN_F12R1_FB1_Msk /*!< Filter bit 1 */
+#define CAN_F12R1_FB2_Pos (2U)
+#define CAN_F12R1_FB2_Msk (0x1U << CAN_F12R1_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F12R1_FB2 CAN_F12R1_FB2_Msk /*!< Filter bit 2 */
+#define CAN_F12R1_FB3_Pos (3U)
+#define CAN_F12R1_FB3_Msk (0x1U << CAN_F12R1_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F12R1_FB3 CAN_F12R1_FB3_Msk /*!< Filter bit 3 */
+#define CAN_F12R1_FB4_Pos (4U)
+#define CAN_F12R1_FB4_Msk (0x1U << CAN_F12R1_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F12R1_FB4 CAN_F12R1_FB4_Msk /*!< Filter bit 4 */
+#define CAN_F12R1_FB5_Pos (5U)
+#define CAN_F12R1_FB5_Msk (0x1U << CAN_F12R1_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F12R1_FB5 CAN_F12R1_FB5_Msk /*!< Filter bit 5 */
+#define CAN_F12R1_FB6_Pos (6U)
+#define CAN_F12R1_FB6_Msk (0x1U << CAN_F12R1_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F12R1_FB6 CAN_F12R1_FB6_Msk /*!< Filter bit 6 */
+#define CAN_F12R1_FB7_Pos (7U)
+#define CAN_F12R1_FB7_Msk (0x1U << CAN_F12R1_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F12R1_FB7 CAN_F12R1_FB7_Msk /*!< Filter bit 7 */
+#define CAN_F12R1_FB8_Pos (8U)
+#define CAN_F12R1_FB8_Msk (0x1U << CAN_F12R1_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F12R1_FB8 CAN_F12R1_FB8_Msk /*!< Filter bit 8 */
+#define CAN_F12R1_FB9_Pos (9U)
+#define CAN_F12R1_FB9_Msk (0x1U << CAN_F12R1_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F12R1_FB9 CAN_F12R1_FB9_Msk /*!< Filter bit 9 */
+#define CAN_F12R1_FB10_Pos (10U)
+#define CAN_F12R1_FB10_Msk (0x1U << CAN_F12R1_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F12R1_FB10 CAN_F12R1_FB10_Msk /*!< Filter bit 10 */
+#define CAN_F12R1_FB11_Pos (11U)
+#define CAN_F12R1_FB11_Msk (0x1U << CAN_F12R1_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F12R1_FB11 CAN_F12R1_FB11_Msk /*!< Filter bit 11 */
+#define CAN_F12R1_FB12_Pos (12U)
+#define CAN_F12R1_FB12_Msk (0x1U << CAN_F12R1_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F12R1_FB12 CAN_F12R1_FB12_Msk /*!< Filter bit 12 */
+#define CAN_F12R1_FB13_Pos (13U)
+#define CAN_F12R1_FB13_Msk (0x1U << CAN_F12R1_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F12R1_FB13 CAN_F12R1_FB13_Msk /*!< Filter bit 13 */
+#define CAN_F12R1_FB14_Pos (14U)
+#define CAN_F12R1_FB14_Msk (0x1U << CAN_F12R1_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F12R1_FB14 CAN_F12R1_FB14_Msk /*!< Filter bit 14 */
+#define CAN_F12R1_FB15_Pos (15U)
+#define CAN_F12R1_FB15_Msk (0x1U << CAN_F12R1_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F12R1_FB15 CAN_F12R1_FB15_Msk /*!< Filter bit 15 */
+#define CAN_F12R1_FB16_Pos (16U)
+#define CAN_F12R1_FB16_Msk (0x1U << CAN_F12R1_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F12R1_FB16 CAN_F12R1_FB16_Msk /*!< Filter bit 16 */
+#define CAN_F12R1_FB17_Pos (17U)
+#define CAN_F12R1_FB17_Msk (0x1U << CAN_F12R1_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F12R1_FB17 CAN_F12R1_FB17_Msk /*!< Filter bit 17 */
+#define CAN_F12R1_FB18_Pos (18U)
+#define CAN_F12R1_FB18_Msk (0x1U << CAN_F12R1_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F12R1_FB18 CAN_F12R1_FB18_Msk /*!< Filter bit 18 */
+#define CAN_F12R1_FB19_Pos (19U)
+#define CAN_F12R1_FB19_Msk (0x1U << CAN_F12R1_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F12R1_FB19 CAN_F12R1_FB19_Msk /*!< Filter bit 19 */
+#define CAN_F12R1_FB20_Pos (20U)
+#define CAN_F12R1_FB20_Msk (0x1U << CAN_F12R1_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F12R1_FB20 CAN_F12R1_FB20_Msk /*!< Filter bit 20 */
+#define CAN_F12R1_FB21_Pos (21U)
+#define CAN_F12R1_FB21_Msk (0x1U << CAN_F12R1_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F12R1_FB21 CAN_F12R1_FB21_Msk /*!< Filter bit 21 */
+#define CAN_F12R1_FB22_Pos (22U)
+#define CAN_F12R1_FB22_Msk (0x1U << CAN_F12R1_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F12R1_FB22 CAN_F12R1_FB22_Msk /*!< Filter bit 22 */
+#define CAN_F12R1_FB23_Pos (23U)
+#define CAN_F12R1_FB23_Msk (0x1U << CAN_F12R1_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F12R1_FB23 CAN_F12R1_FB23_Msk /*!< Filter bit 23 */
+#define CAN_F12R1_FB24_Pos (24U)
+#define CAN_F12R1_FB24_Msk (0x1U << CAN_F12R1_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F12R1_FB24 CAN_F12R1_FB24_Msk /*!< Filter bit 24 */
+#define CAN_F12R1_FB25_Pos (25U)
+#define CAN_F12R1_FB25_Msk (0x1U << CAN_F12R1_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F12R1_FB25 CAN_F12R1_FB25_Msk /*!< Filter bit 25 */
+#define CAN_F12R1_FB26_Pos (26U)
+#define CAN_F12R1_FB26_Msk (0x1U << CAN_F12R1_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F12R1_FB26 CAN_F12R1_FB26_Msk /*!< Filter bit 26 */
+#define CAN_F12R1_FB27_Pos (27U)
+#define CAN_F12R1_FB27_Msk (0x1U << CAN_F12R1_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F12R1_FB27 CAN_F12R1_FB27_Msk /*!< Filter bit 27 */
+#define CAN_F12R1_FB28_Pos (28U)
+#define CAN_F12R1_FB28_Msk (0x1U << CAN_F12R1_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F12R1_FB28 CAN_F12R1_FB28_Msk /*!< Filter bit 28 */
+#define CAN_F12R1_FB29_Pos (29U)
+#define CAN_F12R1_FB29_Msk (0x1U << CAN_F12R1_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F12R1_FB29 CAN_F12R1_FB29_Msk /*!< Filter bit 29 */
+#define CAN_F12R1_FB30_Pos (30U)
+#define CAN_F12R1_FB30_Msk (0x1U << CAN_F12R1_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F12R1_FB30 CAN_F12R1_FB30_Msk /*!< Filter bit 30 */
+#define CAN_F12R1_FB31_Pos (31U)
+#define CAN_F12R1_FB31_Msk (0x1U << CAN_F12R1_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F12R1_FB31 CAN_F12R1_FB31_Msk /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F13R1 register ******************/
+#define CAN_F13R1_FB0_Pos (0U)
+#define CAN_F13R1_FB0_Msk (0x1U << CAN_F13R1_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F13R1_FB0 CAN_F13R1_FB0_Msk /*!< Filter bit 0 */
+#define CAN_F13R1_FB1_Pos (1U)
+#define CAN_F13R1_FB1_Msk (0x1U << CAN_F13R1_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F13R1_FB1 CAN_F13R1_FB1_Msk /*!< Filter bit 1 */
+#define CAN_F13R1_FB2_Pos (2U)
+#define CAN_F13R1_FB2_Msk (0x1U << CAN_F13R1_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F13R1_FB2 CAN_F13R1_FB2_Msk /*!< Filter bit 2 */
+#define CAN_F13R1_FB3_Pos (3U)
+#define CAN_F13R1_FB3_Msk (0x1U << CAN_F13R1_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F13R1_FB3 CAN_F13R1_FB3_Msk /*!< Filter bit 3 */
+#define CAN_F13R1_FB4_Pos (4U)
+#define CAN_F13R1_FB4_Msk (0x1U << CAN_F13R1_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F13R1_FB4 CAN_F13R1_FB4_Msk /*!< Filter bit 4 */
+#define CAN_F13R1_FB5_Pos (5U)
+#define CAN_F13R1_FB5_Msk (0x1U << CAN_F13R1_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F13R1_FB5 CAN_F13R1_FB5_Msk /*!< Filter bit 5 */
+#define CAN_F13R1_FB6_Pos (6U)
+#define CAN_F13R1_FB6_Msk (0x1U << CAN_F13R1_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F13R1_FB6 CAN_F13R1_FB6_Msk /*!< Filter bit 6 */
+#define CAN_F13R1_FB7_Pos (7U)
+#define CAN_F13R1_FB7_Msk (0x1U << CAN_F13R1_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F13R1_FB7 CAN_F13R1_FB7_Msk /*!< Filter bit 7 */
+#define CAN_F13R1_FB8_Pos (8U)
+#define CAN_F13R1_FB8_Msk (0x1U << CAN_F13R1_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F13R1_FB8 CAN_F13R1_FB8_Msk /*!< Filter bit 8 */
+#define CAN_F13R1_FB9_Pos (9U)
+#define CAN_F13R1_FB9_Msk (0x1U << CAN_F13R1_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F13R1_FB9 CAN_F13R1_FB9_Msk /*!< Filter bit 9 */
+#define CAN_F13R1_FB10_Pos (10U)
+#define CAN_F13R1_FB10_Msk (0x1U << CAN_F13R1_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F13R1_FB10 CAN_F13R1_FB10_Msk /*!< Filter bit 10 */
+#define CAN_F13R1_FB11_Pos (11U)
+#define CAN_F13R1_FB11_Msk (0x1U << CAN_F13R1_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F13R1_FB11 CAN_F13R1_FB11_Msk /*!< Filter bit 11 */
+#define CAN_F13R1_FB12_Pos (12U)
+#define CAN_F13R1_FB12_Msk (0x1U << CAN_F13R1_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F13R1_FB12 CAN_F13R1_FB12_Msk /*!< Filter bit 12 */
+#define CAN_F13R1_FB13_Pos (13U)
+#define CAN_F13R1_FB13_Msk (0x1U << CAN_F13R1_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F13R1_FB13 CAN_F13R1_FB13_Msk /*!< Filter bit 13 */
+#define CAN_F13R1_FB14_Pos (14U)
+#define CAN_F13R1_FB14_Msk (0x1U << CAN_F13R1_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F13R1_FB14 CAN_F13R1_FB14_Msk /*!< Filter bit 14 */
+#define CAN_F13R1_FB15_Pos (15U)
+#define CAN_F13R1_FB15_Msk (0x1U << CAN_F13R1_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F13R1_FB15 CAN_F13R1_FB15_Msk /*!< Filter bit 15 */
+#define CAN_F13R1_FB16_Pos (16U)
+#define CAN_F13R1_FB16_Msk (0x1U << CAN_F13R1_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F13R1_FB16 CAN_F13R1_FB16_Msk /*!< Filter bit 16 */
+#define CAN_F13R1_FB17_Pos (17U)
+#define CAN_F13R1_FB17_Msk (0x1U << CAN_F13R1_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F13R1_FB17 CAN_F13R1_FB17_Msk /*!< Filter bit 17 */
+#define CAN_F13R1_FB18_Pos (18U)
+#define CAN_F13R1_FB18_Msk (0x1U << CAN_F13R1_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F13R1_FB18 CAN_F13R1_FB18_Msk /*!< Filter bit 18 */
+#define CAN_F13R1_FB19_Pos (19U)
+#define CAN_F13R1_FB19_Msk (0x1U << CAN_F13R1_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F13R1_FB19 CAN_F13R1_FB19_Msk /*!< Filter bit 19 */
+#define CAN_F13R1_FB20_Pos (20U)
+#define CAN_F13R1_FB20_Msk (0x1U << CAN_F13R1_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F13R1_FB20 CAN_F13R1_FB20_Msk /*!< Filter bit 20 */
+#define CAN_F13R1_FB21_Pos (21U)
+#define CAN_F13R1_FB21_Msk (0x1U << CAN_F13R1_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F13R1_FB21 CAN_F13R1_FB21_Msk /*!< Filter bit 21 */
+#define CAN_F13R1_FB22_Pos (22U)
+#define CAN_F13R1_FB22_Msk (0x1U << CAN_F13R1_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F13R1_FB22 CAN_F13R1_FB22_Msk /*!< Filter bit 22 */
+#define CAN_F13R1_FB23_Pos (23U)
+#define CAN_F13R1_FB23_Msk (0x1U << CAN_F13R1_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F13R1_FB23 CAN_F13R1_FB23_Msk /*!< Filter bit 23 */
+#define CAN_F13R1_FB24_Pos (24U)
+#define CAN_F13R1_FB24_Msk (0x1U << CAN_F13R1_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F13R1_FB24 CAN_F13R1_FB24_Msk /*!< Filter bit 24 */
+#define CAN_F13R1_FB25_Pos (25U)
+#define CAN_F13R1_FB25_Msk (0x1U << CAN_F13R1_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F13R1_FB25 CAN_F13R1_FB25_Msk /*!< Filter bit 25 */
+#define CAN_F13R1_FB26_Pos (26U)
+#define CAN_F13R1_FB26_Msk (0x1U << CAN_F13R1_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F13R1_FB26 CAN_F13R1_FB26_Msk /*!< Filter bit 26 */
+#define CAN_F13R1_FB27_Pos (27U)
+#define CAN_F13R1_FB27_Msk (0x1U << CAN_F13R1_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F13R1_FB27 CAN_F13R1_FB27_Msk /*!< Filter bit 27 */
+#define CAN_F13R1_FB28_Pos (28U)
+#define CAN_F13R1_FB28_Msk (0x1U << CAN_F13R1_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F13R1_FB28 CAN_F13R1_FB28_Msk /*!< Filter bit 28 */
+#define CAN_F13R1_FB29_Pos (29U)
+#define CAN_F13R1_FB29_Msk (0x1U << CAN_F13R1_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F13R1_FB29 CAN_F13R1_FB29_Msk /*!< Filter bit 29 */
+#define CAN_F13R1_FB30_Pos (30U)
+#define CAN_F13R1_FB30_Msk (0x1U << CAN_F13R1_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F13R1_FB30 CAN_F13R1_FB30_Msk /*!< Filter bit 30 */
+#define CAN_F13R1_FB31_Pos (31U)
+#define CAN_F13R1_FB31_Msk (0x1U << CAN_F13R1_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F13R1_FB31 CAN_F13R1_FB31_Msk /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F0R2 register *******************/
+#define CAN_F0R2_FB0_Pos (0U)
+#define CAN_F0R2_FB0_Msk (0x1U << CAN_F0R2_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F0R2_FB0 CAN_F0R2_FB0_Msk /*!< Filter bit 0 */
+#define CAN_F0R2_FB1_Pos (1U)
+#define CAN_F0R2_FB1_Msk (0x1U << CAN_F0R2_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F0R2_FB1 CAN_F0R2_FB1_Msk /*!< Filter bit 1 */
+#define CAN_F0R2_FB2_Pos (2U)
+#define CAN_F0R2_FB2_Msk (0x1U << CAN_F0R2_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F0R2_FB2 CAN_F0R2_FB2_Msk /*!< Filter bit 2 */
+#define CAN_F0R2_FB3_Pos (3U)
+#define CAN_F0R2_FB3_Msk (0x1U << CAN_F0R2_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F0R2_FB3 CAN_F0R2_FB3_Msk /*!< Filter bit 3 */
+#define CAN_F0R2_FB4_Pos (4U)
+#define CAN_F0R2_FB4_Msk (0x1U << CAN_F0R2_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F0R2_FB4 CAN_F0R2_FB4_Msk /*!< Filter bit 4 */
+#define CAN_F0R2_FB5_Pos (5U)
+#define CAN_F0R2_FB5_Msk (0x1U << CAN_F0R2_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F0R2_FB5 CAN_F0R2_FB5_Msk /*!< Filter bit 5 */
+#define CAN_F0R2_FB6_Pos (6U)
+#define CAN_F0R2_FB6_Msk (0x1U << CAN_F0R2_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F0R2_FB6 CAN_F0R2_FB6_Msk /*!< Filter bit 6 */
+#define CAN_F0R2_FB7_Pos (7U)
+#define CAN_F0R2_FB7_Msk (0x1U << CAN_F0R2_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F0R2_FB7 CAN_F0R2_FB7_Msk /*!< Filter bit 7 */
+#define CAN_F0R2_FB8_Pos (8U)
+#define CAN_F0R2_FB8_Msk (0x1U << CAN_F0R2_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F0R2_FB8 CAN_F0R2_FB8_Msk /*!< Filter bit 8 */
+#define CAN_F0R2_FB9_Pos (9U)
+#define CAN_F0R2_FB9_Msk (0x1U << CAN_F0R2_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F0R2_FB9 CAN_F0R2_FB9_Msk /*!< Filter bit 9 */
+#define CAN_F0R2_FB10_Pos (10U)
+#define CAN_F0R2_FB10_Msk (0x1U << CAN_F0R2_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F0R2_FB10 CAN_F0R2_FB10_Msk /*!< Filter bit 10 */
+#define CAN_F0R2_FB11_Pos (11U)
+#define CAN_F0R2_FB11_Msk (0x1U << CAN_F0R2_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F0R2_FB11 CAN_F0R2_FB11_Msk /*!< Filter bit 11 */
+#define CAN_F0R2_FB12_Pos (12U)
+#define CAN_F0R2_FB12_Msk (0x1U << CAN_F0R2_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F0R2_FB12 CAN_F0R2_FB12_Msk /*!< Filter bit 12 */
+#define CAN_F0R2_FB13_Pos (13U)
+#define CAN_F0R2_FB13_Msk (0x1U << CAN_F0R2_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F0R2_FB13 CAN_F0R2_FB13_Msk /*!< Filter bit 13 */
+#define CAN_F0R2_FB14_Pos (14U)
+#define CAN_F0R2_FB14_Msk (0x1U << CAN_F0R2_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F0R2_FB14 CAN_F0R2_FB14_Msk /*!< Filter bit 14 */
+#define CAN_F0R2_FB15_Pos (15U)
+#define CAN_F0R2_FB15_Msk (0x1U << CAN_F0R2_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F0R2_FB15 CAN_F0R2_FB15_Msk /*!< Filter bit 15 */
+#define CAN_F0R2_FB16_Pos (16U)
+#define CAN_F0R2_FB16_Msk (0x1U << CAN_F0R2_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F0R2_FB16 CAN_F0R2_FB16_Msk /*!< Filter bit 16 */
+#define CAN_F0R2_FB17_Pos (17U)
+#define CAN_F0R2_FB17_Msk (0x1U << CAN_F0R2_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F0R2_FB17 CAN_F0R2_FB17_Msk /*!< Filter bit 17 */
+#define CAN_F0R2_FB18_Pos (18U)
+#define CAN_F0R2_FB18_Msk (0x1U << CAN_F0R2_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F0R2_FB18 CAN_F0R2_FB18_Msk /*!< Filter bit 18 */
+#define CAN_F0R2_FB19_Pos (19U)
+#define CAN_F0R2_FB19_Msk (0x1U << CAN_F0R2_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F0R2_FB19 CAN_F0R2_FB19_Msk /*!< Filter bit 19 */
+#define CAN_F0R2_FB20_Pos (20U)
+#define CAN_F0R2_FB20_Msk (0x1U << CAN_F0R2_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F0R2_FB20 CAN_F0R2_FB20_Msk /*!< Filter bit 20 */
+#define CAN_F0R2_FB21_Pos (21U)
+#define CAN_F0R2_FB21_Msk (0x1U << CAN_F0R2_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F0R2_FB21 CAN_F0R2_FB21_Msk /*!< Filter bit 21 */
+#define CAN_F0R2_FB22_Pos (22U)
+#define CAN_F0R2_FB22_Msk (0x1U << CAN_F0R2_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F0R2_FB22 CAN_F0R2_FB22_Msk /*!< Filter bit 22 */
+#define CAN_F0R2_FB23_Pos (23U)
+#define CAN_F0R2_FB23_Msk (0x1U << CAN_F0R2_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F0R2_FB23 CAN_F0R2_FB23_Msk /*!< Filter bit 23 */
+#define CAN_F0R2_FB24_Pos (24U)
+#define CAN_F0R2_FB24_Msk (0x1U << CAN_F0R2_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F0R2_FB24 CAN_F0R2_FB24_Msk /*!< Filter bit 24 */
+#define CAN_F0R2_FB25_Pos (25U)
+#define CAN_F0R2_FB25_Msk (0x1U << CAN_F0R2_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F0R2_FB25 CAN_F0R2_FB25_Msk /*!< Filter bit 25 */
+#define CAN_F0R2_FB26_Pos (26U)
+#define CAN_F0R2_FB26_Msk (0x1U << CAN_F0R2_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F0R2_FB26 CAN_F0R2_FB26_Msk /*!< Filter bit 26 */
+#define CAN_F0R2_FB27_Pos (27U)
+#define CAN_F0R2_FB27_Msk (0x1U << CAN_F0R2_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F0R2_FB27 CAN_F0R2_FB27_Msk /*!< Filter bit 27 */
+#define CAN_F0R2_FB28_Pos (28U)
+#define CAN_F0R2_FB28_Msk (0x1U << CAN_F0R2_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F0R2_FB28 CAN_F0R2_FB28_Msk /*!< Filter bit 28 */
+#define CAN_F0R2_FB29_Pos (29U)
+#define CAN_F0R2_FB29_Msk (0x1U << CAN_F0R2_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F0R2_FB29 CAN_F0R2_FB29_Msk /*!< Filter bit 29 */
+#define CAN_F0R2_FB30_Pos (30U)
+#define CAN_F0R2_FB30_Msk (0x1U << CAN_F0R2_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F0R2_FB30 CAN_F0R2_FB30_Msk /*!< Filter bit 30 */
+#define CAN_F0R2_FB31_Pos (31U)
+#define CAN_F0R2_FB31_Msk (0x1U << CAN_F0R2_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F0R2_FB31 CAN_F0R2_FB31_Msk /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F1R2 register *******************/
+#define CAN_F1R2_FB0_Pos (0U)
+#define CAN_F1R2_FB0_Msk (0x1U << CAN_F1R2_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F1R2_FB0 CAN_F1R2_FB0_Msk /*!< Filter bit 0 */
+#define CAN_F1R2_FB1_Pos (1U)
+#define CAN_F1R2_FB1_Msk (0x1U << CAN_F1R2_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F1R2_FB1 CAN_F1R2_FB1_Msk /*!< Filter bit 1 */
+#define CAN_F1R2_FB2_Pos (2U)
+#define CAN_F1R2_FB2_Msk (0x1U << CAN_F1R2_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F1R2_FB2 CAN_F1R2_FB2_Msk /*!< Filter bit 2 */
+#define CAN_F1R2_FB3_Pos (3U)
+#define CAN_F1R2_FB3_Msk (0x1U << CAN_F1R2_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F1R2_FB3 CAN_F1R2_FB3_Msk /*!< Filter bit 3 */
+#define CAN_F1R2_FB4_Pos (4U)
+#define CAN_F1R2_FB4_Msk (0x1U << CAN_F1R2_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F1R2_FB4 CAN_F1R2_FB4_Msk /*!< Filter bit 4 */
+#define CAN_F1R2_FB5_Pos (5U)
+#define CAN_F1R2_FB5_Msk (0x1U << CAN_F1R2_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F1R2_FB5 CAN_F1R2_FB5_Msk /*!< Filter bit 5 */
+#define CAN_F1R2_FB6_Pos (6U)
+#define CAN_F1R2_FB6_Msk (0x1U << CAN_F1R2_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F1R2_FB6 CAN_F1R2_FB6_Msk /*!< Filter bit 6 */
+#define CAN_F1R2_FB7_Pos (7U)
+#define CAN_F1R2_FB7_Msk (0x1U << CAN_F1R2_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F1R2_FB7 CAN_F1R2_FB7_Msk /*!< Filter bit 7 */
+#define CAN_F1R2_FB8_Pos (8U)
+#define CAN_F1R2_FB8_Msk (0x1U << CAN_F1R2_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F1R2_FB8 CAN_F1R2_FB8_Msk /*!< Filter bit 8 */
+#define CAN_F1R2_FB9_Pos (9U)
+#define CAN_F1R2_FB9_Msk (0x1U << CAN_F1R2_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F1R2_FB9 CAN_F1R2_FB9_Msk /*!< Filter bit 9 */
+#define CAN_F1R2_FB10_Pos (10U)
+#define CAN_F1R2_FB10_Msk (0x1U << CAN_F1R2_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F1R2_FB10 CAN_F1R2_FB10_Msk /*!< Filter bit 10 */
+#define CAN_F1R2_FB11_Pos (11U)
+#define CAN_F1R2_FB11_Msk (0x1U << CAN_F1R2_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F1R2_FB11 CAN_F1R2_FB11_Msk /*!< Filter bit 11 */
+#define CAN_F1R2_FB12_Pos (12U)
+#define CAN_F1R2_FB12_Msk (0x1U << CAN_F1R2_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F1R2_FB12 CAN_F1R2_FB12_Msk /*!< Filter bit 12 */
+#define CAN_F1R2_FB13_Pos (13U)
+#define CAN_F1R2_FB13_Msk (0x1U << CAN_F1R2_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F1R2_FB13 CAN_F1R2_FB13_Msk /*!< Filter bit 13 */
+#define CAN_F1R2_FB14_Pos (14U)
+#define CAN_F1R2_FB14_Msk (0x1U << CAN_F1R2_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F1R2_FB14 CAN_F1R2_FB14_Msk /*!< Filter bit 14 */
+#define CAN_F1R2_FB15_Pos (15U)
+#define CAN_F1R2_FB15_Msk (0x1U << CAN_F1R2_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F1R2_FB15 CAN_F1R2_FB15_Msk /*!< Filter bit 15 */
+#define CAN_F1R2_FB16_Pos (16U)
+#define CAN_F1R2_FB16_Msk (0x1U << CAN_F1R2_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F1R2_FB16 CAN_F1R2_FB16_Msk /*!< Filter bit 16 */
+#define CAN_F1R2_FB17_Pos (17U)
+#define CAN_F1R2_FB17_Msk (0x1U << CAN_F1R2_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F1R2_FB17 CAN_F1R2_FB17_Msk /*!< Filter bit 17 */
+#define CAN_F1R2_FB18_Pos (18U)
+#define CAN_F1R2_FB18_Msk (0x1U << CAN_F1R2_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F1R2_FB18 CAN_F1R2_FB18_Msk /*!< Filter bit 18 */
+#define CAN_F1R2_FB19_Pos (19U)
+#define CAN_F1R2_FB19_Msk (0x1U << CAN_F1R2_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F1R2_FB19 CAN_F1R2_FB19_Msk /*!< Filter bit 19 */
+#define CAN_F1R2_FB20_Pos (20U)
+#define CAN_F1R2_FB20_Msk (0x1U << CAN_F1R2_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F1R2_FB20 CAN_F1R2_FB20_Msk /*!< Filter bit 20 */
+#define CAN_F1R2_FB21_Pos (21U)
+#define CAN_F1R2_FB21_Msk (0x1U << CAN_F1R2_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F1R2_FB21 CAN_F1R2_FB21_Msk /*!< Filter bit 21 */
+#define CAN_F1R2_FB22_Pos (22U)
+#define CAN_F1R2_FB22_Msk (0x1U << CAN_F1R2_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F1R2_FB22 CAN_F1R2_FB22_Msk /*!< Filter bit 22 */
+#define CAN_F1R2_FB23_Pos (23U)
+#define CAN_F1R2_FB23_Msk (0x1U << CAN_F1R2_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F1R2_FB23 CAN_F1R2_FB23_Msk /*!< Filter bit 23 */
+#define CAN_F1R2_FB24_Pos (24U)
+#define CAN_F1R2_FB24_Msk (0x1U << CAN_F1R2_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F1R2_FB24 CAN_F1R2_FB24_Msk /*!< Filter bit 24 */
+#define CAN_F1R2_FB25_Pos (25U)
+#define CAN_F1R2_FB25_Msk (0x1U << CAN_F1R2_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F1R2_FB25 CAN_F1R2_FB25_Msk /*!< Filter bit 25 */
+#define CAN_F1R2_FB26_Pos (26U)
+#define CAN_F1R2_FB26_Msk (0x1U << CAN_F1R2_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F1R2_FB26 CAN_F1R2_FB26_Msk /*!< Filter bit 26 */
+#define CAN_F1R2_FB27_Pos (27U)
+#define CAN_F1R2_FB27_Msk (0x1U << CAN_F1R2_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F1R2_FB27 CAN_F1R2_FB27_Msk /*!< Filter bit 27 */
+#define CAN_F1R2_FB28_Pos (28U)
+#define CAN_F1R2_FB28_Msk (0x1U << CAN_F1R2_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F1R2_FB28 CAN_F1R2_FB28_Msk /*!< Filter bit 28 */
+#define CAN_F1R2_FB29_Pos (29U)
+#define CAN_F1R2_FB29_Msk (0x1U << CAN_F1R2_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F1R2_FB29 CAN_F1R2_FB29_Msk /*!< Filter bit 29 */
+#define CAN_F1R2_FB30_Pos (30U)
+#define CAN_F1R2_FB30_Msk (0x1U << CAN_F1R2_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F1R2_FB30 CAN_F1R2_FB30_Msk /*!< Filter bit 30 */
+#define CAN_F1R2_FB31_Pos (31U)
+#define CAN_F1R2_FB31_Msk (0x1U << CAN_F1R2_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F1R2_FB31 CAN_F1R2_FB31_Msk /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F2R2 register *******************/
+#define CAN_F2R2_FB0_Pos (0U)
+#define CAN_F2R2_FB0_Msk (0x1U << CAN_F2R2_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F2R2_FB0 CAN_F2R2_FB0_Msk /*!< Filter bit 0 */
+#define CAN_F2R2_FB1_Pos (1U)
+#define CAN_F2R2_FB1_Msk (0x1U << CAN_F2R2_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F2R2_FB1 CAN_F2R2_FB1_Msk /*!< Filter bit 1 */
+#define CAN_F2R2_FB2_Pos (2U)
+#define CAN_F2R2_FB2_Msk (0x1U << CAN_F2R2_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F2R2_FB2 CAN_F2R2_FB2_Msk /*!< Filter bit 2 */
+#define CAN_F2R2_FB3_Pos (3U)
+#define CAN_F2R2_FB3_Msk (0x1U << CAN_F2R2_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F2R2_FB3 CAN_F2R2_FB3_Msk /*!< Filter bit 3 */
+#define CAN_F2R2_FB4_Pos (4U)
+#define CAN_F2R2_FB4_Msk (0x1U << CAN_F2R2_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F2R2_FB4 CAN_F2R2_FB4_Msk /*!< Filter bit 4 */
+#define CAN_F2R2_FB5_Pos (5U)
+#define CAN_F2R2_FB5_Msk (0x1U << CAN_F2R2_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F2R2_FB5 CAN_F2R2_FB5_Msk /*!< Filter bit 5 */
+#define CAN_F2R2_FB6_Pos (6U)
+#define CAN_F2R2_FB6_Msk (0x1U << CAN_F2R2_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F2R2_FB6 CAN_F2R2_FB6_Msk /*!< Filter bit 6 */
+#define CAN_F2R2_FB7_Pos (7U)
+#define CAN_F2R2_FB7_Msk (0x1U << CAN_F2R2_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F2R2_FB7 CAN_F2R2_FB7_Msk /*!< Filter bit 7 */
+#define CAN_F2R2_FB8_Pos (8U)
+#define CAN_F2R2_FB8_Msk (0x1U << CAN_F2R2_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F2R2_FB8 CAN_F2R2_FB8_Msk /*!< Filter bit 8 */
+#define CAN_F2R2_FB9_Pos (9U)
+#define CAN_F2R2_FB9_Msk (0x1U << CAN_F2R2_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F2R2_FB9 CAN_F2R2_FB9_Msk /*!< Filter bit 9 */
+#define CAN_F2R2_FB10_Pos (10U)
+#define CAN_F2R2_FB10_Msk (0x1U << CAN_F2R2_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F2R2_FB10 CAN_F2R2_FB10_Msk /*!< Filter bit 10 */
+#define CAN_F2R2_FB11_Pos (11U)
+#define CAN_F2R2_FB11_Msk (0x1U << CAN_F2R2_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F2R2_FB11 CAN_F2R2_FB11_Msk /*!< Filter bit 11 */
+#define CAN_F2R2_FB12_Pos (12U)
+#define CAN_F2R2_FB12_Msk (0x1U << CAN_F2R2_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F2R2_FB12 CAN_F2R2_FB12_Msk /*!< Filter bit 12 */
+#define CAN_F2R2_FB13_Pos (13U)
+#define CAN_F2R2_FB13_Msk (0x1U << CAN_F2R2_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F2R2_FB13 CAN_F2R2_FB13_Msk /*!< Filter bit 13 */
+#define CAN_F2R2_FB14_Pos (14U)
+#define CAN_F2R2_FB14_Msk (0x1U << CAN_F2R2_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F2R2_FB14 CAN_F2R2_FB14_Msk /*!< Filter bit 14 */
+#define CAN_F2R2_FB15_Pos (15U)
+#define CAN_F2R2_FB15_Msk (0x1U << CAN_F2R2_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F2R2_FB15 CAN_F2R2_FB15_Msk /*!< Filter bit 15 */
+#define CAN_F2R2_FB16_Pos (16U)
+#define CAN_F2R2_FB16_Msk (0x1U << CAN_F2R2_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F2R2_FB16 CAN_F2R2_FB16_Msk /*!< Filter bit 16 */
+#define CAN_F2R2_FB17_Pos (17U)
+#define CAN_F2R2_FB17_Msk (0x1U << CAN_F2R2_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F2R2_FB17 CAN_F2R2_FB17_Msk /*!< Filter bit 17 */
+#define CAN_F2R2_FB18_Pos (18U)
+#define CAN_F2R2_FB18_Msk (0x1U << CAN_F2R2_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F2R2_FB18 CAN_F2R2_FB18_Msk /*!< Filter bit 18 */
+#define CAN_F2R2_FB19_Pos (19U)
+#define CAN_F2R2_FB19_Msk (0x1U << CAN_F2R2_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F2R2_FB19 CAN_F2R2_FB19_Msk /*!< Filter bit 19 */
+#define CAN_F2R2_FB20_Pos (20U)
+#define CAN_F2R2_FB20_Msk (0x1U << CAN_F2R2_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F2R2_FB20 CAN_F2R2_FB20_Msk /*!< Filter bit 20 */
+#define CAN_F2R2_FB21_Pos (21U)
+#define CAN_F2R2_FB21_Msk (0x1U << CAN_F2R2_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F2R2_FB21 CAN_F2R2_FB21_Msk /*!< Filter bit 21 */
+#define CAN_F2R2_FB22_Pos (22U)
+#define CAN_F2R2_FB22_Msk (0x1U << CAN_F2R2_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F2R2_FB22 CAN_F2R2_FB22_Msk /*!< Filter bit 22 */
+#define CAN_F2R2_FB23_Pos (23U)
+#define CAN_F2R2_FB23_Msk (0x1U << CAN_F2R2_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F2R2_FB23 CAN_F2R2_FB23_Msk /*!< Filter bit 23 */
+#define CAN_F2R2_FB24_Pos (24U)
+#define CAN_F2R2_FB24_Msk (0x1U << CAN_F2R2_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F2R2_FB24 CAN_F2R2_FB24_Msk /*!< Filter bit 24 */
+#define CAN_F2R2_FB25_Pos (25U)
+#define CAN_F2R2_FB25_Msk (0x1U << CAN_F2R2_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F2R2_FB25 CAN_F2R2_FB25_Msk /*!< Filter bit 25 */
+#define CAN_F2R2_FB26_Pos (26U)
+#define CAN_F2R2_FB26_Msk (0x1U << CAN_F2R2_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F2R2_FB26 CAN_F2R2_FB26_Msk /*!< Filter bit 26 */
+#define CAN_F2R2_FB27_Pos (27U)
+#define CAN_F2R2_FB27_Msk (0x1U << CAN_F2R2_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F2R2_FB27 CAN_F2R2_FB27_Msk /*!< Filter bit 27 */
+#define CAN_F2R2_FB28_Pos (28U)
+#define CAN_F2R2_FB28_Msk (0x1U << CAN_F2R2_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F2R2_FB28 CAN_F2R2_FB28_Msk /*!< Filter bit 28 */
+#define CAN_F2R2_FB29_Pos (29U)
+#define CAN_F2R2_FB29_Msk (0x1U << CAN_F2R2_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F2R2_FB29 CAN_F2R2_FB29_Msk /*!< Filter bit 29 */
+#define CAN_F2R2_FB30_Pos (30U)
+#define CAN_F2R2_FB30_Msk (0x1U << CAN_F2R2_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F2R2_FB30 CAN_F2R2_FB30_Msk /*!< Filter bit 30 */
+#define CAN_F2R2_FB31_Pos (31U)
+#define CAN_F2R2_FB31_Msk (0x1U << CAN_F2R2_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F2R2_FB31 CAN_F2R2_FB31_Msk /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F3R2 register *******************/
+#define CAN_F3R2_FB0_Pos (0U)
+#define CAN_F3R2_FB0_Msk (0x1U << CAN_F3R2_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F3R2_FB0 CAN_F3R2_FB0_Msk /*!< Filter bit 0 */
+#define CAN_F3R2_FB1_Pos (1U)
+#define CAN_F3R2_FB1_Msk (0x1U << CAN_F3R2_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F3R2_FB1 CAN_F3R2_FB1_Msk /*!< Filter bit 1 */
+#define CAN_F3R2_FB2_Pos (2U)
+#define CAN_F3R2_FB2_Msk (0x1U << CAN_F3R2_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F3R2_FB2 CAN_F3R2_FB2_Msk /*!< Filter bit 2 */
+#define CAN_F3R2_FB3_Pos (3U)
+#define CAN_F3R2_FB3_Msk (0x1U << CAN_F3R2_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F3R2_FB3 CAN_F3R2_FB3_Msk /*!< Filter bit 3 */
+#define CAN_F3R2_FB4_Pos (4U)
+#define CAN_F3R2_FB4_Msk (0x1U << CAN_F3R2_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F3R2_FB4 CAN_F3R2_FB4_Msk /*!< Filter bit 4 */
+#define CAN_F3R2_FB5_Pos (5U)
+#define CAN_F3R2_FB5_Msk (0x1U << CAN_F3R2_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F3R2_FB5 CAN_F3R2_FB5_Msk /*!< Filter bit 5 */
+#define CAN_F3R2_FB6_Pos (6U)
+#define CAN_F3R2_FB6_Msk (0x1U << CAN_F3R2_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F3R2_FB6 CAN_F3R2_FB6_Msk /*!< Filter bit 6 */
+#define CAN_F3R2_FB7_Pos (7U)
+#define CAN_F3R2_FB7_Msk (0x1U << CAN_F3R2_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F3R2_FB7 CAN_F3R2_FB7_Msk /*!< Filter bit 7 */
+#define CAN_F3R2_FB8_Pos (8U)
+#define CAN_F3R2_FB8_Msk (0x1U << CAN_F3R2_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F3R2_FB8 CAN_F3R2_FB8_Msk /*!< Filter bit 8 */
+#define CAN_F3R2_FB9_Pos (9U)
+#define CAN_F3R2_FB9_Msk (0x1U << CAN_F3R2_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F3R2_FB9 CAN_F3R2_FB9_Msk /*!< Filter bit 9 */
+#define CAN_F3R2_FB10_Pos (10U)
+#define CAN_F3R2_FB10_Msk (0x1U << CAN_F3R2_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F3R2_FB10 CAN_F3R2_FB10_Msk /*!< Filter bit 10 */
+#define CAN_F3R2_FB11_Pos (11U)
+#define CAN_F3R2_FB11_Msk (0x1U << CAN_F3R2_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F3R2_FB11 CAN_F3R2_FB11_Msk /*!< Filter bit 11 */
+#define CAN_F3R2_FB12_Pos (12U)
+#define CAN_F3R2_FB12_Msk (0x1U << CAN_F3R2_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F3R2_FB12 CAN_F3R2_FB12_Msk /*!< Filter bit 12 */
+#define CAN_F3R2_FB13_Pos (13U)
+#define CAN_F3R2_FB13_Msk (0x1U << CAN_F3R2_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F3R2_FB13 CAN_F3R2_FB13_Msk /*!< Filter bit 13 */
+#define CAN_F3R2_FB14_Pos (14U)
+#define CAN_F3R2_FB14_Msk (0x1U << CAN_F3R2_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F3R2_FB14 CAN_F3R2_FB14_Msk /*!< Filter bit 14 */
+#define CAN_F3R2_FB15_Pos (15U)
+#define CAN_F3R2_FB15_Msk (0x1U << CAN_F3R2_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F3R2_FB15 CAN_F3R2_FB15_Msk /*!< Filter bit 15 */
+#define CAN_F3R2_FB16_Pos (16U)
+#define CAN_F3R2_FB16_Msk (0x1U << CAN_F3R2_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F3R2_FB16 CAN_F3R2_FB16_Msk /*!< Filter bit 16 */
+#define CAN_F3R2_FB17_Pos (17U)
+#define CAN_F3R2_FB17_Msk (0x1U << CAN_F3R2_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F3R2_FB17 CAN_F3R2_FB17_Msk /*!< Filter bit 17 */
+#define CAN_F3R2_FB18_Pos (18U)
+#define CAN_F3R2_FB18_Msk (0x1U << CAN_F3R2_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F3R2_FB18 CAN_F3R2_FB18_Msk /*!< Filter bit 18 */
+#define CAN_F3R2_FB19_Pos (19U)
+#define CAN_F3R2_FB19_Msk (0x1U << CAN_F3R2_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F3R2_FB19 CAN_F3R2_FB19_Msk /*!< Filter bit 19 */
+#define CAN_F3R2_FB20_Pos (20U)
+#define CAN_F3R2_FB20_Msk (0x1U << CAN_F3R2_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F3R2_FB20 CAN_F3R2_FB20_Msk /*!< Filter bit 20 */
+#define CAN_F3R2_FB21_Pos (21U)
+#define CAN_F3R2_FB21_Msk (0x1U << CAN_F3R2_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F3R2_FB21 CAN_F3R2_FB21_Msk /*!< Filter bit 21 */
+#define CAN_F3R2_FB22_Pos (22U)
+#define CAN_F3R2_FB22_Msk (0x1U << CAN_F3R2_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F3R2_FB22 CAN_F3R2_FB22_Msk /*!< Filter bit 22 */
+#define CAN_F3R2_FB23_Pos (23U)
+#define CAN_F3R2_FB23_Msk (0x1U << CAN_F3R2_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F3R2_FB23 CAN_F3R2_FB23_Msk /*!< Filter bit 23 */
+#define CAN_F3R2_FB24_Pos (24U)
+#define CAN_F3R2_FB24_Msk (0x1U << CAN_F3R2_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F3R2_FB24 CAN_F3R2_FB24_Msk /*!< Filter bit 24 */
+#define CAN_F3R2_FB25_Pos (25U)
+#define CAN_F3R2_FB25_Msk (0x1U << CAN_F3R2_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F3R2_FB25 CAN_F3R2_FB25_Msk /*!< Filter bit 25 */
+#define CAN_F3R2_FB26_Pos (26U)
+#define CAN_F3R2_FB26_Msk (0x1U << CAN_F3R2_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F3R2_FB26 CAN_F3R2_FB26_Msk /*!< Filter bit 26 */
+#define CAN_F3R2_FB27_Pos (27U)
+#define CAN_F3R2_FB27_Msk (0x1U << CAN_F3R2_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F3R2_FB27 CAN_F3R2_FB27_Msk /*!< Filter bit 27 */
+#define CAN_F3R2_FB28_Pos (28U)
+#define CAN_F3R2_FB28_Msk (0x1U << CAN_F3R2_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F3R2_FB28 CAN_F3R2_FB28_Msk /*!< Filter bit 28 */
+#define CAN_F3R2_FB29_Pos (29U)
+#define CAN_F3R2_FB29_Msk (0x1U << CAN_F3R2_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F3R2_FB29 CAN_F3R2_FB29_Msk /*!< Filter bit 29 */
+#define CAN_F3R2_FB30_Pos (30U)
+#define CAN_F3R2_FB30_Msk (0x1U << CAN_F3R2_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F3R2_FB30 CAN_F3R2_FB30_Msk /*!< Filter bit 30 */
+#define CAN_F3R2_FB31_Pos (31U)
+#define CAN_F3R2_FB31_Msk (0x1U << CAN_F3R2_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F3R2_FB31 CAN_F3R2_FB31_Msk /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F4R2 register *******************/
+#define CAN_F4R2_FB0_Pos (0U)
+#define CAN_F4R2_FB0_Msk (0x1U << CAN_F4R2_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F4R2_FB0 CAN_F4R2_FB0_Msk /*!< Filter bit 0 */
+#define CAN_F4R2_FB1_Pos (1U)
+#define CAN_F4R2_FB1_Msk (0x1U << CAN_F4R2_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F4R2_FB1 CAN_F4R2_FB1_Msk /*!< Filter bit 1 */
+#define CAN_F4R2_FB2_Pos (2U)
+#define CAN_F4R2_FB2_Msk (0x1U << CAN_F4R2_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F4R2_FB2 CAN_F4R2_FB2_Msk /*!< Filter bit 2 */
+#define CAN_F4R2_FB3_Pos (3U)
+#define CAN_F4R2_FB3_Msk (0x1U << CAN_F4R2_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F4R2_FB3 CAN_F4R2_FB3_Msk /*!< Filter bit 3 */
+#define CAN_F4R2_FB4_Pos (4U)
+#define CAN_F4R2_FB4_Msk (0x1U << CAN_F4R2_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F4R2_FB4 CAN_F4R2_FB4_Msk /*!< Filter bit 4 */
+#define CAN_F4R2_FB5_Pos (5U)
+#define CAN_F4R2_FB5_Msk (0x1U << CAN_F4R2_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F4R2_FB5 CAN_F4R2_FB5_Msk /*!< Filter bit 5 */
+#define CAN_F4R2_FB6_Pos (6U)
+#define CAN_F4R2_FB6_Msk (0x1U << CAN_F4R2_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F4R2_FB6 CAN_F4R2_FB6_Msk /*!< Filter bit 6 */
+#define CAN_F4R2_FB7_Pos (7U)
+#define CAN_F4R2_FB7_Msk (0x1U << CAN_F4R2_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F4R2_FB7 CAN_F4R2_FB7_Msk /*!< Filter bit 7 */
+#define CAN_F4R2_FB8_Pos (8U)
+#define CAN_F4R2_FB8_Msk (0x1U << CAN_F4R2_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F4R2_FB8 CAN_F4R2_FB8_Msk /*!< Filter bit 8 */
+#define CAN_F4R2_FB9_Pos (9U)
+#define CAN_F4R2_FB9_Msk (0x1U << CAN_F4R2_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F4R2_FB9 CAN_F4R2_FB9_Msk /*!< Filter bit 9 */
+#define CAN_F4R2_FB10_Pos (10U)
+#define CAN_F4R2_FB10_Msk (0x1U << CAN_F4R2_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F4R2_FB10 CAN_F4R2_FB10_Msk /*!< Filter bit 10 */
+#define CAN_F4R2_FB11_Pos (11U)
+#define CAN_F4R2_FB11_Msk (0x1U << CAN_F4R2_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F4R2_FB11 CAN_F4R2_FB11_Msk /*!< Filter bit 11 */
+#define CAN_F4R2_FB12_Pos (12U)
+#define CAN_F4R2_FB12_Msk (0x1U << CAN_F4R2_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F4R2_FB12 CAN_F4R2_FB12_Msk /*!< Filter bit 12 */
+#define CAN_F4R2_FB13_Pos (13U)
+#define CAN_F4R2_FB13_Msk (0x1U << CAN_F4R2_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F4R2_FB13 CAN_F4R2_FB13_Msk /*!< Filter bit 13 */
+#define CAN_F4R2_FB14_Pos (14U)
+#define CAN_F4R2_FB14_Msk (0x1U << CAN_F4R2_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F4R2_FB14 CAN_F4R2_FB14_Msk /*!< Filter bit 14 */
+#define CAN_F4R2_FB15_Pos (15U)
+#define CAN_F4R2_FB15_Msk (0x1U << CAN_F4R2_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F4R2_FB15 CAN_F4R2_FB15_Msk /*!< Filter bit 15 */
+#define CAN_F4R2_FB16_Pos (16U)
+#define CAN_F4R2_FB16_Msk (0x1U << CAN_F4R2_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F4R2_FB16 CAN_F4R2_FB16_Msk /*!< Filter bit 16 */
+#define CAN_F4R2_FB17_Pos (17U)
+#define CAN_F4R2_FB17_Msk (0x1U << CAN_F4R2_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F4R2_FB17 CAN_F4R2_FB17_Msk /*!< Filter bit 17 */
+#define CAN_F4R2_FB18_Pos (18U)
+#define CAN_F4R2_FB18_Msk (0x1U << CAN_F4R2_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F4R2_FB18 CAN_F4R2_FB18_Msk /*!< Filter bit 18 */
+#define CAN_F4R2_FB19_Pos (19U)
+#define CAN_F4R2_FB19_Msk (0x1U << CAN_F4R2_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F4R2_FB19 CAN_F4R2_FB19_Msk /*!< Filter bit 19 */
+#define CAN_F4R2_FB20_Pos (20U)
+#define CAN_F4R2_FB20_Msk (0x1U << CAN_F4R2_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F4R2_FB20 CAN_F4R2_FB20_Msk /*!< Filter bit 20 */
+#define CAN_F4R2_FB21_Pos (21U)
+#define CAN_F4R2_FB21_Msk (0x1U << CAN_F4R2_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F4R2_FB21 CAN_F4R2_FB21_Msk /*!< Filter bit 21 */
+#define CAN_F4R2_FB22_Pos (22U)
+#define CAN_F4R2_FB22_Msk (0x1U << CAN_F4R2_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F4R2_FB22 CAN_F4R2_FB22_Msk /*!< Filter bit 22 */
+#define CAN_F4R2_FB23_Pos (23U)
+#define CAN_F4R2_FB23_Msk (0x1U << CAN_F4R2_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F4R2_FB23 CAN_F4R2_FB23_Msk /*!< Filter bit 23 */
+#define CAN_F4R2_FB24_Pos (24U)
+#define CAN_F4R2_FB24_Msk (0x1U << CAN_F4R2_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F4R2_FB24 CAN_F4R2_FB24_Msk /*!< Filter bit 24 */
+#define CAN_F4R2_FB25_Pos (25U)
+#define CAN_F4R2_FB25_Msk (0x1U << CAN_F4R2_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F4R2_FB25 CAN_F4R2_FB25_Msk /*!< Filter bit 25 */
+#define CAN_F4R2_FB26_Pos (26U)
+#define CAN_F4R2_FB26_Msk (0x1U << CAN_F4R2_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F4R2_FB26 CAN_F4R2_FB26_Msk /*!< Filter bit 26 */
+#define CAN_F4R2_FB27_Pos (27U)
+#define CAN_F4R2_FB27_Msk (0x1U << CAN_F4R2_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F4R2_FB27 CAN_F4R2_FB27_Msk /*!< Filter bit 27 */
+#define CAN_F4R2_FB28_Pos (28U)
+#define CAN_F4R2_FB28_Msk (0x1U << CAN_F4R2_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F4R2_FB28 CAN_F4R2_FB28_Msk /*!< Filter bit 28 */
+#define CAN_F4R2_FB29_Pos (29U)
+#define CAN_F4R2_FB29_Msk (0x1U << CAN_F4R2_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F4R2_FB29 CAN_F4R2_FB29_Msk /*!< Filter bit 29 */
+#define CAN_F4R2_FB30_Pos (30U)
+#define CAN_F4R2_FB30_Msk (0x1U << CAN_F4R2_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F4R2_FB30 CAN_F4R2_FB30_Msk /*!< Filter bit 30 */
+#define CAN_F4R2_FB31_Pos (31U)
+#define CAN_F4R2_FB31_Msk (0x1U << CAN_F4R2_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F4R2_FB31 CAN_F4R2_FB31_Msk /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F5R2 register *******************/
+#define CAN_F5R2_FB0_Pos (0U)
+#define CAN_F5R2_FB0_Msk (0x1U << CAN_F5R2_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F5R2_FB0 CAN_F5R2_FB0_Msk /*!< Filter bit 0 */
+#define CAN_F5R2_FB1_Pos (1U)
+#define CAN_F5R2_FB1_Msk (0x1U << CAN_F5R2_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F5R2_FB1 CAN_F5R2_FB1_Msk /*!< Filter bit 1 */
+#define CAN_F5R2_FB2_Pos (2U)
+#define CAN_F5R2_FB2_Msk (0x1U << CAN_F5R2_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F5R2_FB2 CAN_F5R2_FB2_Msk /*!< Filter bit 2 */
+#define CAN_F5R2_FB3_Pos (3U)
+#define CAN_F5R2_FB3_Msk (0x1U << CAN_F5R2_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F5R2_FB3 CAN_F5R2_FB3_Msk /*!< Filter bit 3 */
+#define CAN_F5R2_FB4_Pos (4U)
+#define CAN_F5R2_FB4_Msk (0x1U << CAN_F5R2_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F5R2_FB4 CAN_F5R2_FB4_Msk /*!< Filter bit 4 */
+#define CAN_F5R2_FB5_Pos (5U)
+#define CAN_F5R2_FB5_Msk (0x1U << CAN_F5R2_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F5R2_FB5 CAN_F5R2_FB5_Msk /*!< Filter bit 5 */
+#define CAN_F5R2_FB6_Pos (6U)
+#define CAN_F5R2_FB6_Msk (0x1U << CAN_F5R2_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F5R2_FB6 CAN_F5R2_FB6_Msk /*!< Filter bit 6 */
+#define CAN_F5R2_FB7_Pos (7U)
+#define CAN_F5R2_FB7_Msk (0x1U << CAN_F5R2_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F5R2_FB7 CAN_F5R2_FB7_Msk /*!< Filter bit 7 */
+#define CAN_F5R2_FB8_Pos (8U)
+#define CAN_F5R2_FB8_Msk (0x1U << CAN_F5R2_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F5R2_FB8 CAN_F5R2_FB8_Msk /*!< Filter bit 8 */
+#define CAN_F5R2_FB9_Pos (9U)
+#define CAN_F5R2_FB9_Msk (0x1U << CAN_F5R2_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F5R2_FB9 CAN_F5R2_FB9_Msk /*!< Filter bit 9 */
+#define CAN_F5R2_FB10_Pos (10U)
+#define CAN_F5R2_FB10_Msk (0x1U << CAN_F5R2_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F5R2_FB10 CAN_F5R2_FB10_Msk /*!< Filter bit 10 */
+#define CAN_F5R2_FB11_Pos (11U)
+#define CAN_F5R2_FB11_Msk (0x1U << CAN_F5R2_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F5R2_FB11 CAN_F5R2_FB11_Msk /*!< Filter bit 11 */
+#define CAN_F5R2_FB12_Pos (12U)
+#define CAN_F5R2_FB12_Msk (0x1U << CAN_F5R2_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F5R2_FB12 CAN_F5R2_FB12_Msk /*!< Filter bit 12 */
+#define CAN_F5R2_FB13_Pos (13U)
+#define CAN_F5R2_FB13_Msk (0x1U << CAN_F5R2_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F5R2_FB13 CAN_F5R2_FB13_Msk /*!< Filter bit 13 */
+#define CAN_F5R2_FB14_Pos (14U)
+#define CAN_F5R2_FB14_Msk (0x1U << CAN_F5R2_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F5R2_FB14 CAN_F5R2_FB14_Msk /*!< Filter bit 14 */
+#define CAN_F5R2_FB15_Pos (15U)
+#define CAN_F5R2_FB15_Msk (0x1U << CAN_F5R2_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F5R2_FB15 CAN_F5R2_FB15_Msk /*!< Filter bit 15 */
+#define CAN_F5R2_FB16_Pos (16U)
+#define CAN_F5R2_FB16_Msk (0x1U << CAN_F5R2_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F5R2_FB16 CAN_F5R2_FB16_Msk /*!< Filter bit 16 */
+#define CAN_F5R2_FB17_Pos (17U)
+#define CAN_F5R2_FB17_Msk (0x1U << CAN_F5R2_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F5R2_FB17 CAN_F5R2_FB17_Msk /*!< Filter bit 17 */
+#define CAN_F5R2_FB18_Pos (18U)
+#define CAN_F5R2_FB18_Msk (0x1U << CAN_F5R2_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F5R2_FB18 CAN_F5R2_FB18_Msk /*!< Filter bit 18 */
+#define CAN_F5R2_FB19_Pos (19U)
+#define CAN_F5R2_FB19_Msk (0x1U << CAN_F5R2_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F5R2_FB19 CAN_F5R2_FB19_Msk /*!< Filter bit 19 */
+#define CAN_F5R2_FB20_Pos (20U)
+#define CAN_F5R2_FB20_Msk (0x1U << CAN_F5R2_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F5R2_FB20 CAN_F5R2_FB20_Msk /*!< Filter bit 20 */
+#define CAN_F5R2_FB21_Pos (21U)
+#define CAN_F5R2_FB21_Msk (0x1U << CAN_F5R2_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F5R2_FB21 CAN_F5R2_FB21_Msk /*!< Filter bit 21 */
+#define CAN_F5R2_FB22_Pos (22U)
+#define CAN_F5R2_FB22_Msk (0x1U << CAN_F5R2_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F5R2_FB22 CAN_F5R2_FB22_Msk /*!< Filter bit 22 */
+#define CAN_F5R2_FB23_Pos (23U)
+#define CAN_F5R2_FB23_Msk (0x1U << CAN_F5R2_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F5R2_FB23 CAN_F5R2_FB23_Msk /*!< Filter bit 23 */
+#define CAN_F5R2_FB24_Pos (24U)
+#define CAN_F5R2_FB24_Msk (0x1U << CAN_F5R2_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F5R2_FB24 CAN_F5R2_FB24_Msk /*!< Filter bit 24 */
+#define CAN_F5R2_FB25_Pos (25U)
+#define CAN_F5R2_FB25_Msk (0x1U << CAN_F5R2_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F5R2_FB25 CAN_F5R2_FB25_Msk /*!< Filter bit 25 */
+#define CAN_F5R2_FB26_Pos (26U)
+#define CAN_F5R2_FB26_Msk (0x1U << CAN_F5R2_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F5R2_FB26 CAN_F5R2_FB26_Msk /*!< Filter bit 26 */
+#define CAN_F5R2_FB27_Pos (27U)
+#define CAN_F5R2_FB27_Msk (0x1U << CAN_F5R2_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F5R2_FB27 CAN_F5R2_FB27_Msk /*!< Filter bit 27 */
+#define CAN_F5R2_FB28_Pos (28U)
+#define CAN_F5R2_FB28_Msk (0x1U << CAN_F5R2_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F5R2_FB28 CAN_F5R2_FB28_Msk /*!< Filter bit 28 */
+#define CAN_F5R2_FB29_Pos (29U)
+#define CAN_F5R2_FB29_Msk (0x1U << CAN_F5R2_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F5R2_FB29 CAN_F5R2_FB29_Msk /*!< Filter bit 29 */
+#define CAN_F5R2_FB30_Pos (30U)
+#define CAN_F5R2_FB30_Msk (0x1U << CAN_F5R2_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F5R2_FB30 CAN_F5R2_FB30_Msk /*!< Filter bit 30 */
+#define CAN_F5R2_FB31_Pos (31U)
+#define CAN_F5R2_FB31_Msk (0x1U << CAN_F5R2_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F5R2_FB31 CAN_F5R2_FB31_Msk /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F6R2 register *******************/
+#define CAN_F6R2_FB0_Pos (0U)
+#define CAN_F6R2_FB0_Msk (0x1U << CAN_F6R2_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F6R2_FB0 CAN_F6R2_FB0_Msk /*!< Filter bit 0 */
+#define CAN_F6R2_FB1_Pos (1U)
+#define CAN_F6R2_FB1_Msk (0x1U << CAN_F6R2_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F6R2_FB1 CAN_F6R2_FB1_Msk /*!< Filter bit 1 */
+#define CAN_F6R2_FB2_Pos (2U)
+#define CAN_F6R2_FB2_Msk (0x1U << CAN_F6R2_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F6R2_FB2 CAN_F6R2_FB2_Msk /*!< Filter bit 2 */
+#define CAN_F6R2_FB3_Pos (3U)
+#define CAN_F6R2_FB3_Msk (0x1U << CAN_F6R2_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F6R2_FB3 CAN_F6R2_FB3_Msk /*!< Filter bit 3 */
+#define CAN_F6R2_FB4_Pos (4U)
+#define CAN_F6R2_FB4_Msk (0x1U << CAN_F6R2_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F6R2_FB4 CAN_F6R2_FB4_Msk /*!< Filter bit 4 */
+#define CAN_F6R2_FB5_Pos (5U)
+#define CAN_F6R2_FB5_Msk (0x1U << CAN_F6R2_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F6R2_FB5 CAN_F6R2_FB5_Msk /*!< Filter bit 5 */
+#define CAN_F6R2_FB6_Pos (6U)
+#define CAN_F6R2_FB6_Msk (0x1U << CAN_F6R2_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F6R2_FB6 CAN_F6R2_FB6_Msk /*!< Filter bit 6 */
+#define CAN_F6R2_FB7_Pos (7U)
+#define CAN_F6R2_FB7_Msk (0x1U << CAN_F6R2_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F6R2_FB7 CAN_F6R2_FB7_Msk /*!< Filter bit 7 */
+#define CAN_F6R2_FB8_Pos (8U)
+#define CAN_F6R2_FB8_Msk (0x1U << CAN_F6R2_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F6R2_FB8 CAN_F6R2_FB8_Msk /*!< Filter bit 8 */
+#define CAN_F6R2_FB9_Pos (9U)
+#define CAN_F6R2_FB9_Msk (0x1U << CAN_F6R2_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F6R2_FB9 CAN_F6R2_FB9_Msk /*!< Filter bit 9 */
+#define CAN_F6R2_FB10_Pos (10U)
+#define CAN_F6R2_FB10_Msk (0x1U << CAN_F6R2_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F6R2_FB10 CAN_F6R2_FB10_Msk /*!< Filter bit 10 */
+#define CAN_F6R2_FB11_Pos (11U)
+#define CAN_F6R2_FB11_Msk (0x1U << CAN_F6R2_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F6R2_FB11 CAN_F6R2_FB11_Msk /*!< Filter bit 11 */
+#define CAN_F6R2_FB12_Pos (12U)
+#define CAN_F6R2_FB12_Msk (0x1U << CAN_F6R2_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F6R2_FB12 CAN_F6R2_FB12_Msk /*!< Filter bit 12 */
+#define CAN_F6R2_FB13_Pos (13U)
+#define CAN_F6R2_FB13_Msk (0x1U << CAN_F6R2_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F6R2_FB13 CAN_F6R2_FB13_Msk /*!< Filter bit 13 */
+#define CAN_F6R2_FB14_Pos (14U)
+#define CAN_F6R2_FB14_Msk (0x1U << CAN_F6R2_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F6R2_FB14 CAN_F6R2_FB14_Msk /*!< Filter bit 14 */
+#define CAN_F6R2_FB15_Pos (15U)
+#define CAN_F6R2_FB15_Msk (0x1U << CAN_F6R2_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F6R2_FB15 CAN_F6R2_FB15_Msk /*!< Filter bit 15 */
+#define CAN_F6R2_FB16_Pos (16U)
+#define CAN_F6R2_FB16_Msk (0x1U << CAN_F6R2_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F6R2_FB16 CAN_F6R2_FB16_Msk /*!< Filter bit 16 */
+#define CAN_F6R2_FB17_Pos (17U)
+#define CAN_F6R2_FB17_Msk (0x1U << CAN_F6R2_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F6R2_FB17 CAN_F6R2_FB17_Msk /*!< Filter bit 17 */
+#define CAN_F6R2_FB18_Pos (18U)
+#define CAN_F6R2_FB18_Msk (0x1U << CAN_F6R2_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F6R2_FB18 CAN_F6R2_FB18_Msk /*!< Filter bit 18 */
+#define CAN_F6R2_FB19_Pos (19U)
+#define CAN_F6R2_FB19_Msk (0x1U << CAN_F6R2_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F6R2_FB19 CAN_F6R2_FB19_Msk /*!< Filter bit 19 */
+#define CAN_F6R2_FB20_Pos (20U)
+#define CAN_F6R2_FB20_Msk (0x1U << CAN_F6R2_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F6R2_FB20 CAN_F6R2_FB20_Msk /*!< Filter bit 20 */
+#define CAN_F6R2_FB21_Pos (21U)
+#define CAN_F6R2_FB21_Msk (0x1U << CAN_F6R2_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F6R2_FB21 CAN_F6R2_FB21_Msk /*!< Filter bit 21 */
+#define CAN_F6R2_FB22_Pos (22U)
+#define CAN_F6R2_FB22_Msk (0x1U << CAN_F6R2_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F6R2_FB22 CAN_F6R2_FB22_Msk /*!< Filter bit 22 */
+#define CAN_F6R2_FB23_Pos (23U)
+#define CAN_F6R2_FB23_Msk (0x1U << CAN_F6R2_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F6R2_FB23 CAN_F6R2_FB23_Msk /*!< Filter bit 23 */
+#define CAN_F6R2_FB24_Pos (24U)
+#define CAN_F6R2_FB24_Msk (0x1U << CAN_F6R2_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F6R2_FB24 CAN_F6R2_FB24_Msk /*!< Filter bit 24 */
+#define CAN_F6R2_FB25_Pos (25U)
+#define CAN_F6R2_FB25_Msk (0x1U << CAN_F6R2_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F6R2_FB25 CAN_F6R2_FB25_Msk /*!< Filter bit 25 */
+#define CAN_F6R2_FB26_Pos (26U)
+#define CAN_F6R2_FB26_Msk (0x1U << CAN_F6R2_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F6R2_FB26 CAN_F6R2_FB26_Msk /*!< Filter bit 26 */
+#define CAN_F6R2_FB27_Pos (27U)
+#define CAN_F6R2_FB27_Msk (0x1U << CAN_F6R2_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F6R2_FB27 CAN_F6R2_FB27_Msk /*!< Filter bit 27 */
+#define CAN_F6R2_FB28_Pos (28U)
+#define CAN_F6R2_FB28_Msk (0x1U << CAN_F6R2_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F6R2_FB28 CAN_F6R2_FB28_Msk /*!< Filter bit 28 */
+#define CAN_F6R2_FB29_Pos (29U)
+#define CAN_F6R2_FB29_Msk (0x1U << CAN_F6R2_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F6R2_FB29 CAN_F6R2_FB29_Msk /*!< Filter bit 29 */
+#define CAN_F6R2_FB30_Pos (30U)
+#define CAN_F6R2_FB30_Msk (0x1U << CAN_F6R2_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F6R2_FB30 CAN_F6R2_FB30_Msk /*!< Filter bit 30 */
+#define CAN_F6R2_FB31_Pos (31U)
+#define CAN_F6R2_FB31_Msk (0x1U << CAN_F6R2_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F6R2_FB31 CAN_F6R2_FB31_Msk /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F7R2 register *******************/
+#define CAN_F7R2_FB0_Pos (0U)
+#define CAN_F7R2_FB0_Msk (0x1U << CAN_F7R2_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F7R2_FB0 CAN_F7R2_FB0_Msk /*!< Filter bit 0 */
+#define CAN_F7R2_FB1_Pos (1U)
+#define CAN_F7R2_FB1_Msk (0x1U << CAN_F7R2_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F7R2_FB1 CAN_F7R2_FB1_Msk /*!< Filter bit 1 */
+#define CAN_F7R2_FB2_Pos (2U)
+#define CAN_F7R2_FB2_Msk (0x1U << CAN_F7R2_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F7R2_FB2 CAN_F7R2_FB2_Msk /*!< Filter bit 2 */
+#define CAN_F7R2_FB3_Pos (3U)
+#define CAN_F7R2_FB3_Msk (0x1U << CAN_F7R2_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F7R2_FB3 CAN_F7R2_FB3_Msk /*!< Filter bit 3 */
+#define CAN_F7R2_FB4_Pos (4U)
+#define CAN_F7R2_FB4_Msk (0x1U << CAN_F7R2_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F7R2_FB4 CAN_F7R2_FB4_Msk /*!< Filter bit 4 */
+#define CAN_F7R2_FB5_Pos (5U)
+#define CAN_F7R2_FB5_Msk (0x1U << CAN_F7R2_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F7R2_FB5 CAN_F7R2_FB5_Msk /*!< Filter bit 5 */
+#define CAN_F7R2_FB6_Pos (6U)
+#define CAN_F7R2_FB6_Msk (0x1U << CAN_F7R2_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F7R2_FB6 CAN_F7R2_FB6_Msk /*!< Filter bit 6 */
+#define CAN_F7R2_FB7_Pos (7U)
+#define CAN_F7R2_FB7_Msk (0x1U << CAN_F7R2_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F7R2_FB7 CAN_F7R2_FB7_Msk /*!< Filter bit 7 */
+#define CAN_F7R2_FB8_Pos (8U)
+#define CAN_F7R2_FB8_Msk (0x1U << CAN_F7R2_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F7R2_FB8 CAN_F7R2_FB8_Msk /*!< Filter bit 8 */
+#define CAN_F7R2_FB9_Pos (9U)
+#define CAN_F7R2_FB9_Msk (0x1U << CAN_F7R2_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F7R2_FB9 CAN_F7R2_FB9_Msk /*!< Filter bit 9 */
+#define CAN_F7R2_FB10_Pos (10U)
+#define CAN_F7R2_FB10_Msk (0x1U << CAN_F7R2_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F7R2_FB10 CAN_F7R2_FB10_Msk /*!< Filter bit 10 */
+#define CAN_F7R2_FB11_Pos (11U)
+#define CAN_F7R2_FB11_Msk (0x1U << CAN_F7R2_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F7R2_FB11 CAN_F7R2_FB11_Msk /*!< Filter bit 11 */
+#define CAN_F7R2_FB12_Pos (12U)
+#define CAN_F7R2_FB12_Msk (0x1U << CAN_F7R2_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F7R2_FB12 CAN_F7R2_FB12_Msk /*!< Filter bit 12 */
+#define CAN_F7R2_FB13_Pos (13U)
+#define CAN_F7R2_FB13_Msk (0x1U << CAN_F7R2_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F7R2_FB13 CAN_F7R2_FB13_Msk /*!< Filter bit 13 */
+#define CAN_F7R2_FB14_Pos (14U)
+#define CAN_F7R2_FB14_Msk (0x1U << CAN_F7R2_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F7R2_FB14 CAN_F7R2_FB14_Msk /*!< Filter bit 14 */
+#define CAN_F7R2_FB15_Pos (15U)
+#define CAN_F7R2_FB15_Msk (0x1U << CAN_F7R2_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F7R2_FB15 CAN_F7R2_FB15_Msk /*!< Filter bit 15 */
+#define CAN_F7R2_FB16_Pos (16U)
+#define CAN_F7R2_FB16_Msk (0x1U << CAN_F7R2_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F7R2_FB16 CAN_F7R2_FB16_Msk /*!< Filter bit 16 */
+#define CAN_F7R2_FB17_Pos (17U)
+#define CAN_F7R2_FB17_Msk (0x1U << CAN_F7R2_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F7R2_FB17 CAN_F7R2_FB17_Msk /*!< Filter bit 17 */
+#define CAN_F7R2_FB18_Pos (18U)
+#define CAN_F7R2_FB18_Msk (0x1U << CAN_F7R2_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F7R2_FB18 CAN_F7R2_FB18_Msk /*!< Filter bit 18 */
+#define CAN_F7R2_FB19_Pos (19U)
+#define CAN_F7R2_FB19_Msk (0x1U << CAN_F7R2_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F7R2_FB19 CAN_F7R2_FB19_Msk /*!< Filter bit 19 */
+#define CAN_F7R2_FB20_Pos (20U)
+#define CAN_F7R2_FB20_Msk (0x1U << CAN_F7R2_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F7R2_FB20 CAN_F7R2_FB20_Msk /*!< Filter bit 20 */
+#define CAN_F7R2_FB21_Pos (21U)
+#define CAN_F7R2_FB21_Msk (0x1U << CAN_F7R2_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F7R2_FB21 CAN_F7R2_FB21_Msk /*!< Filter bit 21 */
+#define CAN_F7R2_FB22_Pos (22U)
+#define CAN_F7R2_FB22_Msk (0x1U << CAN_F7R2_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F7R2_FB22 CAN_F7R2_FB22_Msk /*!< Filter bit 22 */
+#define CAN_F7R2_FB23_Pos (23U)
+#define CAN_F7R2_FB23_Msk (0x1U << CAN_F7R2_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F7R2_FB23 CAN_F7R2_FB23_Msk /*!< Filter bit 23 */
+#define CAN_F7R2_FB24_Pos (24U)
+#define CAN_F7R2_FB24_Msk (0x1U << CAN_F7R2_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F7R2_FB24 CAN_F7R2_FB24_Msk /*!< Filter bit 24 */
+#define CAN_F7R2_FB25_Pos (25U)
+#define CAN_F7R2_FB25_Msk (0x1U << CAN_F7R2_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F7R2_FB25 CAN_F7R2_FB25_Msk /*!< Filter bit 25 */
+#define CAN_F7R2_FB26_Pos (26U)
+#define CAN_F7R2_FB26_Msk (0x1U << CAN_F7R2_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F7R2_FB26 CAN_F7R2_FB26_Msk /*!< Filter bit 26 */
+#define CAN_F7R2_FB27_Pos (27U)
+#define CAN_F7R2_FB27_Msk (0x1U << CAN_F7R2_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F7R2_FB27 CAN_F7R2_FB27_Msk /*!< Filter bit 27 */
+#define CAN_F7R2_FB28_Pos (28U)
+#define CAN_F7R2_FB28_Msk (0x1U << CAN_F7R2_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F7R2_FB28 CAN_F7R2_FB28_Msk /*!< Filter bit 28 */
+#define CAN_F7R2_FB29_Pos (29U)
+#define CAN_F7R2_FB29_Msk (0x1U << CAN_F7R2_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F7R2_FB29 CAN_F7R2_FB29_Msk /*!< Filter bit 29 */
+#define CAN_F7R2_FB30_Pos (30U)
+#define CAN_F7R2_FB30_Msk (0x1U << CAN_F7R2_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F7R2_FB30 CAN_F7R2_FB30_Msk /*!< Filter bit 30 */
+#define CAN_F7R2_FB31_Pos (31U)
+#define CAN_F7R2_FB31_Msk (0x1U << CAN_F7R2_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F7R2_FB31 CAN_F7R2_FB31_Msk /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F8R2 register *******************/
+#define CAN_F8R2_FB0_Pos (0U)
+#define CAN_F8R2_FB0_Msk (0x1U << CAN_F8R2_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F8R2_FB0 CAN_F8R2_FB0_Msk /*!< Filter bit 0 */
+#define CAN_F8R2_FB1_Pos (1U)
+#define CAN_F8R2_FB1_Msk (0x1U << CAN_F8R2_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F8R2_FB1 CAN_F8R2_FB1_Msk /*!< Filter bit 1 */
+#define CAN_F8R2_FB2_Pos (2U)
+#define CAN_F8R2_FB2_Msk (0x1U << CAN_F8R2_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F8R2_FB2 CAN_F8R2_FB2_Msk /*!< Filter bit 2 */
+#define CAN_F8R2_FB3_Pos (3U)
+#define CAN_F8R2_FB3_Msk (0x1U << CAN_F8R2_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F8R2_FB3 CAN_F8R2_FB3_Msk /*!< Filter bit 3 */
+#define CAN_F8R2_FB4_Pos (4U)
+#define CAN_F8R2_FB4_Msk (0x1U << CAN_F8R2_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F8R2_FB4 CAN_F8R2_FB4_Msk /*!< Filter bit 4 */
+#define CAN_F8R2_FB5_Pos (5U)
+#define CAN_F8R2_FB5_Msk (0x1U << CAN_F8R2_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F8R2_FB5 CAN_F8R2_FB5_Msk /*!< Filter bit 5 */
+#define CAN_F8R2_FB6_Pos (6U)
+#define CAN_F8R2_FB6_Msk (0x1U << CAN_F8R2_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F8R2_FB6 CAN_F8R2_FB6_Msk /*!< Filter bit 6 */
+#define CAN_F8R2_FB7_Pos (7U)
+#define CAN_F8R2_FB7_Msk (0x1U << CAN_F8R2_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F8R2_FB7 CAN_F8R2_FB7_Msk /*!< Filter bit 7 */
+#define CAN_F8R2_FB8_Pos (8U)
+#define CAN_F8R2_FB8_Msk (0x1U << CAN_F8R2_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F8R2_FB8 CAN_F8R2_FB8_Msk /*!< Filter bit 8 */
+#define CAN_F8R2_FB9_Pos (9U)
+#define CAN_F8R2_FB9_Msk (0x1U << CAN_F8R2_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F8R2_FB9 CAN_F8R2_FB9_Msk /*!< Filter bit 9 */
+#define CAN_F8R2_FB10_Pos (10U)
+#define CAN_F8R2_FB10_Msk (0x1U << CAN_F8R2_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F8R2_FB10 CAN_F8R2_FB10_Msk /*!< Filter bit 10 */
+#define CAN_F8R2_FB11_Pos (11U)
+#define CAN_F8R2_FB11_Msk (0x1U << CAN_F8R2_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F8R2_FB11 CAN_F8R2_FB11_Msk /*!< Filter bit 11 */
+#define CAN_F8R2_FB12_Pos (12U)
+#define CAN_F8R2_FB12_Msk (0x1U << CAN_F8R2_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F8R2_FB12 CAN_F8R2_FB12_Msk /*!< Filter bit 12 */
+#define CAN_F8R2_FB13_Pos (13U)
+#define CAN_F8R2_FB13_Msk (0x1U << CAN_F8R2_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F8R2_FB13 CAN_F8R2_FB13_Msk /*!< Filter bit 13 */
+#define CAN_F8R2_FB14_Pos (14U)
+#define CAN_F8R2_FB14_Msk (0x1U << CAN_F8R2_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F8R2_FB14 CAN_F8R2_FB14_Msk /*!< Filter bit 14 */
+#define CAN_F8R2_FB15_Pos (15U)
+#define CAN_F8R2_FB15_Msk (0x1U << CAN_F8R2_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F8R2_FB15 CAN_F8R2_FB15_Msk /*!< Filter bit 15 */
+#define CAN_F8R2_FB16_Pos (16U)
+#define CAN_F8R2_FB16_Msk (0x1U << CAN_F8R2_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F8R2_FB16 CAN_F8R2_FB16_Msk /*!< Filter bit 16 */
+#define CAN_F8R2_FB17_Pos (17U)
+#define CAN_F8R2_FB17_Msk (0x1U << CAN_F8R2_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F8R2_FB17 CAN_F8R2_FB17_Msk /*!< Filter bit 17 */
+#define CAN_F8R2_FB18_Pos (18U)
+#define CAN_F8R2_FB18_Msk (0x1U << CAN_F8R2_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F8R2_FB18 CAN_F8R2_FB18_Msk /*!< Filter bit 18 */
+#define CAN_F8R2_FB19_Pos (19U)
+#define CAN_F8R2_FB19_Msk (0x1U << CAN_F8R2_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F8R2_FB19 CAN_F8R2_FB19_Msk /*!< Filter bit 19 */
+#define CAN_F8R2_FB20_Pos (20U)
+#define CAN_F8R2_FB20_Msk (0x1U << CAN_F8R2_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F8R2_FB20 CAN_F8R2_FB20_Msk /*!< Filter bit 20 */
+#define CAN_F8R2_FB21_Pos (21U)
+#define CAN_F8R2_FB21_Msk (0x1U << CAN_F8R2_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F8R2_FB21 CAN_F8R2_FB21_Msk /*!< Filter bit 21 */
+#define CAN_F8R2_FB22_Pos (22U)
+#define CAN_F8R2_FB22_Msk (0x1U << CAN_F8R2_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F8R2_FB22 CAN_F8R2_FB22_Msk /*!< Filter bit 22 */
+#define CAN_F8R2_FB23_Pos (23U)
+#define CAN_F8R2_FB23_Msk (0x1U << CAN_F8R2_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F8R2_FB23 CAN_F8R2_FB23_Msk /*!< Filter bit 23 */
+#define CAN_F8R2_FB24_Pos (24U)
+#define CAN_F8R2_FB24_Msk (0x1U << CAN_F8R2_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F8R2_FB24 CAN_F8R2_FB24_Msk /*!< Filter bit 24 */
+#define CAN_F8R2_FB25_Pos (25U)
+#define CAN_F8R2_FB25_Msk (0x1U << CAN_F8R2_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F8R2_FB25 CAN_F8R2_FB25_Msk /*!< Filter bit 25 */
+#define CAN_F8R2_FB26_Pos (26U)
+#define CAN_F8R2_FB26_Msk (0x1U << CAN_F8R2_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F8R2_FB26 CAN_F8R2_FB26_Msk /*!< Filter bit 26 */
+#define CAN_F8R2_FB27_Pos (27U)
+#define CAN_F8R2_FB27_Msk (0x1U << CAN_F8R2_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F8R2_FB27 CAN_F8R2_FB27_Msk /*!< Filter bit 27 */
+#define CAN_F8R2_FB28_Pos (28U)
+#define CAN_F8R2_FB28_Msk (0x1U << CAN_F8R2_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F8R2_FB28 CAN_F8R2_FB28_Msk /*!< Filter bit 28 */
+#define CAN_F8R2_FB29_Pos (29U)
+#define CAN_F8R2_FB29_Msk (0x1U << CAN_F8R2_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F8R2_FB29 CAN_F8R2_FB29_Msk /*!< Filter bit 29 */
+#define CAN_F8R2_FB30_Pos (30U)
+#define CAN_F8R2_FB30_Msk (0x1U << CAN_F8R2_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F8R2_FB30 CAN_F8R2_FB30_Msk /*!< Filter bit 30 */
+#define CAN_F8R2_FB31_Pos (31U)
+#define CAN_F8R2_FB31_Msk (0x1U << CAN_F8R2_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F8R2_FB31 CAN_F8R2_FB31_Msk /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F9R2 register *******************/
+#define CAN_F9R2_FB0_Pos (0U)
+#define CAN_F9R2_FB0_Msk (0x1U << CAN_F9R2_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F9R2_FB0 CAN_F9R2_FB0_Msk /*!< Filter bit 0 */
+#define CAN_F9R2_FB1_Pos (1U)
+#define CAN_F9R2_FB1_Msk (0x1U << CAN_F9R2_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F9R2_FB1 CAN_F9R2_FB1_Msk /*!< Filter bit 1 */
+#define CAN_F9R2_FB2_Pos (2U)
+#define CAN_F9R2_FB2_Msk (0x1U << CAN_F9R2_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F9R2_FB2 CAN_F9R2_FB2_Msk /*!< Filter bit 2 */
+#define CAN_F9R2_FB3_Pos (3U)
+#define CAN_F9R2_FB3_Msk (0x1U << CAN_F9R2_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F9R2_FB3 CAN_F9R2_FB3_Msk /*!< Filter bit 3 */
+#define CAN_F9R2_FB4_Pos (4U)
+#define CAN_F9R2_FB4_Msk (0x1U << CAN_F9R2_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F9R2_FB4 CAN_F9R2_FB4_Msk /*!< Filter bit 4 */
+#define CAN_F9R2_FB5_Pos (5U)
+#define CAN_F9R2_FB5_Msk (0x1U << CAN_F9R2_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F9R2_FB5 CAN_F9R2_FB5_Msk /*!< Filter bit 5 */
+#define CAN_F9R2_FB6_Pos (6U)
+#define CAN_F9R2_FB6_Msk (0x1U << CAN_F9R2_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F9R2_FB6 CAN_F9R2_FB6_Msk /*!< Filter bit 6 */
+#define CAN_F9R2_FB7_Pos (7U)
+#define CAN_F9R2_FB7_Msk (0x1U << CAN_F9R2_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F9R2_FB7 CAN_F9R2_FB7_Msk /*!< Filter bit 7 */
+#define CAN_F9R2_FB8_Pos (8U)
+#define CAN_F9R2_FB8_Msk (0x1U << CAN_F9R2_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F9R2_FB8 CAN_F9R2_FB8_Msk /*!< Filter bit 8 */
+#define CAN_F9R2_FB9_Pos (9U)
+#define CAN_F9R2_FB9_Msk (0x1U << CAN_F9R2_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F9R2_FB9 CAN_F9R2_FB9_Msk /*!< Filter bit 9 */
+#define CAN_F9R2_FB10_Pos (10U)
+#define CAN_F9R2_FB10_Msk (0x1U << CAN_F9R2_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F9R2_FB10 CAN_F9R2_FB10_Msk /*!< Filter bit 10 */
+#define CAN_F9R2_FB11_Pos (11U)
+#define CAN_F9R2_FB11_Msk (0x1U << CAN_F9R2_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F9R2_FB11 CAN_F9R2_FB11_Msk /*!< Filter bit 11 */
+#define CAN_F9R2_FB12_Pos (12U)
+#define CAN_F9R2_FB12_Msk (0x1U << CAN_F9R2_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F9R2_FB12 CAN_F9R2_FB12_Msk /*!< Filter bit 12 */
+#define CAN_F9R2_FB13_Pos (13U)
+#define CAN_F9R2_FB13_Msk (0x1U << CAN_F9R2_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F9R2_FB13 CAN_F9R2_FB13_Msk /*!< Filter bit 13 */
+#define CAN_F9R2_FB14_Pos (14U)
+#define CAN_F9R2_FB14_Msk (0x1U << CAN_F9R2_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F9R2_FB14 CAN_F9R2_FB14_Msk /*!< Filter bit 14 */
+#define CAN_F9R2_FB15_Pos (15U)
+#define CAN_F9R2_FB15_Msk (0x1U << CAN_F9R2_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F9R2_FB15 CAN_F9R2_FB15_Msk /*!< Filter bit 15 */
+#define CAN_F9R2_FB16_Pos (16U)
+#define CAN_F9R2_FB16_Msk (0x1U << CAN_F9R2_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F9R2_FB16 CAN_F9R2_FB16_Msk /*!< Filter bit 16 */
+#define CAN_F9R2_FB17_Pos (17U)
+#define CAN_F9R2_FB17_Msk (0x1U << CAN_F9R2_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F9R2_FB17 CAN_F9R2_FB17_Msk /*!< Filter bit 17 */
+#define CAN_F9R2_FB18_Pos (18U)
+#define CAN_F9R2_FB18_Msk (0x1U << CAN_F9R2_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F9R2_FB18 CAN_F9R2_FB18_Msk /*!< Filter bit 18 */
+#define CAN_F9R2_FB19_Pos (19U)
+#define CAN_F9R2_FB19_Msk (0x1U << CAN_F9R2_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F9R2_FB19 CAN_F9R2_FB19_Msk /*!< Filter bit 19 */
+#define CAN_F9R2_FB20_Pos (20U)
+#define CAN_F9R2_FB20_Msk (0x1U << CAN_F9R2_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F9R2_FB20 CAN_F9R2_FB20_Msk /*!< Filter bit 20 */
+#define CAN_F9R2_FB21_Pos (21U)
+#define CAN_F9R2_FB21_Msk (0x1U << CAN_F9R2_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F9R2_FB21 CAN_F9R2_FB21_Msk /*!< Filter bit 21 */
+#define CAN_F9R2_FB22_Pos (22U)
+#define CAN_F9R2_FB22_Msk (0x1U << CAN_F9R2_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F9R2_FB22 CAN_F9R2_FB22_Msk /*!< Filter bit 22 */
+#define CAN_F9R2_FB23_Pos (23U)
+#define CAN_F9R2_FB23_Msk (0x1U << CAN_F9R2_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F9R2_FB23 CAN_F9R2_FB23_Msk /*!< Filter bit 23 */
+#define CAN_F9R2_FB24_Pos (24U)
+#define CAN_F9R2_FB24_Msk (0x1U << CAN_F9R2_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F9R2_FB24 CAN_F9R2_FB24_Msk /*!< Filter bit 24 */
+#define CAN_F9R2_FB25_Pos (25U)
+#define CAN_F9R2_FB25_Msk (0x1U << CAN_F9R2_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F9R2_FB25 CAN_F9R2_FB25_Msk /*!< Filter bit 25 */
+#define CAN_F9R2_FB26_Pos (26U)
+#define CAN_F9R2_FB26_Msk (0x1U << CAN_F9R2_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F9R2_FB26 CAN_F9R2_FB26_Msk /*!< Filter bit 26 */
+#define CAN_F9R2_FB27_Pos (27U)
+#define CAN_F9R2_FB27_Msk (0x1U << CAN_F9R2_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F9R2_FB27 CAN_F9R2_FB27_Msk /*!< Filter bit 27 */
+#define CAN_F9R2_FB28_Pos (28U)
+#define CAN_F9R2_FB28_Msk (0x1U << CAN_F9R2_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F9R2_FB28 CAN_F9R2_FB28_Msk /*!< Filter bit 28 */
+#define CAN_F9R2_FB29_Pos (29U)
+#define CAN_F9R2_FB29_Msk (0x1U << CAN_F9R2_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F9R2_FB29 CAN_F9R2_FB29_Msk /*!< Filter bit 29 */
+#define CAN_F9R2_FB30_Pos (30U)
+#define CAN_F9R2_FB30_Msk (0x1U << CAN_F9R2_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F9R2_FB30 CAN_F9R2_FB30_Msk /*!< Filter bit 30 */
+#define CAN_F9R2_FB31_Pos (31U)
+#define CAN_F9R2_FB31_Msk (0x1U << CAN_F9R2_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F9R2_FB31 CAN_F9R2_FB31_Msk /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F10R2 register ******************/
+#define CAN_F10R2_FB0_Pos (0U)
+#define CAN_F10R2_FB0_Msk (0x1U << CAN_F10R2_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F10R2_FB0 CAN_F10R2_FB0_Msk /*!< Filter bit 0 */
+#define CAN_F10R2_FB1_Pos (1U)
+#define CAN_F10R2_FB1_Msk (0x1U << CAN_F10R2_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F10R2_FB1 CAN_F10R2_FB1_Msk /*!< Filter bit 1 */
+#define CAN_F10R2_FB2_Pos (2U)
+#define CAN_F10R2_FB2_Msk (0x1U << CAN_F10R2_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F10R2_FB2 CAN_F10R2_FB2_Msk /*!< Filter bit 2 */
+#define CAN_F10R2_FB3_Pos (3U)
+#define CAN_F10R2_FB3_Msk (0x1U << CAN_F10R2_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F10R2_FB3 CAN_F10R2_FB3_Msk /*!< Filter bit 3 */
+#define CAN_F10R2_FB4_Pos (4U)
+#define CAN_F10R2_FB4_Msk (0x1U << CAN_F10R2_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F10R2_FB4 CAN_F10R2_FB4_Msk /*!< Filter bit 4 */
+#define CAN_F10R2_FB5_Pos (5U)
+#define CAN_F10R2_FB5_Msk (0x1U << CAN_F10R2_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F10R2_FB5 CAN_F10R2_FB5_Msk /*!< Filter bit 5 */
+#define CAN_F10R2_FB6_Pos (6U)
+#define CAN_F10R2_FB6_Msk (0x1U << CAN_F10R2_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F10R2_FB6 CAN_F10R2_FB6_Msk /*!< Filter bit 6 */
+#define CAN_F10R2_FB7_Pos (7U)
+#define CAN_F10R2_FB7_Msk (0x1U << CAN_F10R2_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F10R2_FB7 CAN_F10R2_FB7_Msk /*!< Filter bit 7 */
+#define CAN_F10R2_FB8_Pos (8U)
+#define CAN_F10R2_FB8_Msk (0x1U << CAN_F10R2_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F10R2_FB8 CAN_F10R2_FB8_Msk /*!< Filter bit 8 */
+#define CAN_F10R2_FB9_Pos (9U)
+#define CAN_F10R2_FB9_Msk (0x1U << CAN_F10R2_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F10R2_FB9 CAN_F10R2_FB9_Msk /*!< Filter bit 9 */
+#define CAN_F10R2_FB10_Pos (10U)
+#define CAN_F10R2_FB10_Msk (0x1U << CAN_F10R2_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F10R2_FB10 CAN_F10R2_FB10_Msk /*!< Filter bit 10 */
+#define CAN_F10R2_FB11_Pos (11U)
+#define CAN_F10R2_FB11_Msk (0x1U << CAN_F10R2_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F10R2_FB11 CAN_F10R2_FB11_Msk /*!< Filter bit 11 */
+#define CAN_F10R2_FB12_Pos (12U)
+#define CAN_F10R2_FB12_Msk (0x1U << CAN_F10R2_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F10R2_FB12 CAN_F10R2_FB12_Msk /*!< Filter bit 12 */
+#define CAN_F10R2_FB13_Pos (13U)
+#define CAN_F10R2_FB13_Msk (0x1U << CAN_F10R2_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F10R2_FB13 CAN_F10R2_FB13_Msk /*!< Filter bit 13 */
+#define CAN_F10R2_FB14_Pos (14U)
+#define CAN_F10R2_FB14_Msk (0x1U << CAN_F10R2_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F10R2_FB14 CAN_F10R2_FB14_Msk /*!< Filter bit 14 */
+#define CAN_F10R2_FB15_Pos (15U)
+#define CAN_F10R2_FB15_Msk (0x1U << CAN_F10R2_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F10R2_FB15 CAN_F10R2_FB15_Msk /*!< Filter bit 15 */
+#define CAN_F10R2_FB16_Pos (16U)
+#define CAN_F10R2_FB16_Msk (0x1U << CAN_F10R2_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F10R2_FB16 CAN_F10R2_FB16_Msk /*!< Filter bit 16 */
+#define CAN_F10R2_FB17_Pos (17U)
+#define CAN_F10R2_FB17_Msk (0x1U << CAN_F10R2_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F10R2_FB17 CAN_F10R2_FB17_Msk /*!< Filter bit 17 */
+#define CAN_F10R2_FB18_Pos (18U)
+#define CAN_F10R2_FB18_Msk (0x1U << CAN_F10R2_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F10R2_FB18 CAN_F10R2_FB18_Msk /*!< Filter bit 18 */
+#define CAN_F10R2_FB19_Pos (19U)
+#define CAN_F10R2_FB19_Msk (0x1U << CAN_F10R2_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F10R2_FB19 CAN_F10R2_FB19_Msk /*!< Filter bit 19 */
+#define CAN_F10R2_FB20_Pos (20U)
+#define CAN_F10R2_FB20_Msk (0x1U << CAN_F10R2_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F10R2_FB20 CAN_F10R2_FB20_Msk /*!< Filter bit 20 */
+#define CAN_F10R2_FB21_Pos (21U)
+#define CAN_F10R2_FB21_Msk (0x1U << CAN_F10R2_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F10R2_FB21 CAN_F10R2_FB21_Msk /*!< Filter bit 21 */
+#define CAN_F10R2_FB22_Pos (22U)
+#define CAN_F10R2_FB22_Msk (0x1U << CAN_F10R2_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F10R2_FB22 CAN_F10R2_FB22_Msk /*!< Filter bit 22 */
+#define CAN_F10R2_FB23_Pos (23U)
+#define CAN_F10R2_FB23_Msk (0x1U << CAN_F10R2_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F10R2_FB23 CAN_F10R2_FB23_Msk /*!< Filter bit 23 */
+#define CAN_F10R2_FB24_Pos (24U)
+#define CAN_F10R2_FB24_Msk (0x1U << CAN_F10R2_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F10R2_FB24 CAN_F10R2_FB24_Msk /*!< Filter bit 24 */
+#define CAN_F10R2_FB25_Pos (25U)
+#define CAN_F10R2_FB25_Msk (0x1U << CAN_F10R2_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F10R2_FB25 CAN_F10R2_FB25_Msk /*!< Filter bit 25 */
+#define CAN_F10R2_FB26_Pos (26U)
+#define CAN_F10R2_FB26_Msk (0x1U << CAN_F10R2_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F10R2_FB26 CAN_F10R2_FB26_Msk /*!< Filter bit 26 */
+#define CAN_F10R2_FB27_Pos (27U)
+#define CAN_F10R2_FB27_Msk (0x1U << CAN_F10R2_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F10R2_FB27 CAN_F10R2_FB27_Msk /*!< Filter bit 27 */
+#define CAN_F10R2_FB28_Pos (28U)
+#define CAN_F10R2_FB28_Msk (0x1U << CAN_F10R2_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F10R2_FB28 CAN_F10R2_FB28_Msk /*!< Filter bit 28 */
+#define CAN_F10R2_FB29_Pos (29U)
+#define CAN_F10R2_FB29_Msk (0x1U << CAN_F10R2_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F10R2_FB29 CAN_F10R2_FB29_Msk /*!< Filter bit 29 */
+#define CAN_F10R2_FB30_Pos (30U)
+#define CAN_F10R2_FB30_Msk (0x1U << CAN_F10R2_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F10R2_FB30 CAN_F10R2_FB30_Msk /*!< Filter bit 30 */
+#define CAN_F10R2_FB31_Pos (31U)
+#define CAN_F10R2_FB31_Msk (0x1U << CAN_F10R2_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F10R2_FB31 CAN_F10R2_FB31_Msk /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F11R2 register ******************/
+#define CAN_F11R2_FB0_Pos (0U)
+#define CAN_F11R2_FB0_Msk (0x1U << CAN_F11R2_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F11R2_FB0 CAN_F11R2_FB0_Msk /*!< Filter bit 0 */
+#define CAN_F11R2_FB1_Pos (1U)
+#define CAN_F11R2_FB1_Msk (0x1U << CAN_F11R2_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F11R2_FB1 CAN_F11R2_FB1_Msk /*!< Filter bit 1 */
+#define CAN_F11R2_FB2_Pos (2U)
+#define CAN_F11R2_FB2_Msk (0x1U << CAN_F11R2_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F11R2_FB2 CAN_F11R2_FB2_Msk /*!< Filter bit 2 */
+#define CAN_F11R2_FB3_Pos (3U)
+#define CAN_F11R2_FB3_Msk (0x1U << CAN_F11R2_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F11R2_FB3 CAN_F11R2_FB3_Msk /*!< Filter bit 3 */
+#define CAN_F11R2_FB4_Pos (4U)
+#define CAN_F11R2_FB4_Msk (0x1U << CAN_F11R2_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F11R2_FB4 CAN_F11R2_FB4_Msk /*!< Filter bit 4 */
+#define CAN_F11R2_FB5_Pos (5U)
+#define CAN_F11R2_FB5_Msk (0x1U << CAN_F11R2_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F11R2_FB5 CAN_F11R2_FB5_Msk /*!< Filter bit 5 */
+#define CAN_F11R2_FB6_Pos (6U)
+#define CAN_F11R2_FB6_Msk (0x1U << CAN_F11R2_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F11R2_FB6 CAN_F11R2_FB6_Msk /*!< Filter bit 6 */
+#define CAN_F11R2_FB7_Pos (7U)
+#define CAN_F11R2_FB7_Msk (0x1U << CAN_F11R2_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F11R2_FB7 CAN_F11R2_FB7_Msk /*!< Filter bit 7 */
+#define CAN_F11R2_FB8_Pos (8U)
+#define CAN_F11R2_FB8_Msk (0x1U << CAN_F11R2_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F11R2_FB8 CAN_F11R2_FB8_Msk /*!< Filter bit 8 */
+#define CAN_F11R2_FB9_Pos (9U)
+#define CAN_F11R2_FB9_Msk (0x1U << CAN_F11R2_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F11R2_FB9 CAN_F11R2_FB9_Msk /*!< Filter bit 9 */
+#define CAN_F11R2_FB10_Pos (10U)
+#define CAN_F11R2_FB10_Msk (0x1U << CAN_F11R2_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F11R2_FB10 CAN_F11R2_FB10_Msk /*!< Filter bit 10 */
+#define CAN_F11R2_FB11_Pos (11U)
+#define CAN_F11R2_FB11_Msk (0x1U << CAN_F11R2_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F11R2_FB11 CAN_F11R2_FB11_Msk /*!< Filter bit 11 */
+#define CAN_F11R2_FB12_Pos (12U)
+#define CAN_F11R2_FB12_Msk (0x1U << CAN_F11R2_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F11R2_FB12 CAN_F11R2_FB12_Msk /*!< Filter bit 12 */
+#define CAN_F11R2_FB13_Pos (13U)
+#define CAN_F11R2_FB13_Msk (0x1U << CAN_F11R2_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F11R2_FB13 CAN_F11R2_FB13_Msk /*!< Filter bit 13 */
+#define CAN_F11R2_FB14_Pos (14U)
+#define CAN_F11R2_FB14_Msk (0x1U << CAN_F11R2_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F11R2_FB14 CAN_F11R2_FB14_Msk /*!< Filter bit 14 */
+#define CAN_F11R2_FB15_Pos (15U)
+#define CAN_F11R2_FB15_Msk (0x1U << CAN_F11R2_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F11R2_FB15 CAN_F11R2_FB15_Msk /*!< Filter bit 15 */
+#define CAN_F11R2_FB16_Pos (16U)
+#define CAN_F11R2_FB16_Msk (0x1U << CAN_F11R2_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F11R2_FB16 CAN_F11R2_FB16_Msk /*!< Filter bit 16 */
+#define CAN_F11R2_FB17_Pos (17U)
+#define CAN_F11R2_FB17_Msk (0x1U << CAN_F11R2_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F11R2_FB17 CAN_F11R2_FB17_Msk /*!< Filter bit 17 */
+#define CAN_F11R2_FB18_Pos (18U)
+#define CAN_F11R2_FB18_Msk (0x1U << CAN_F11R2_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F11R2_FB18 CAN_F11R2_FB18_Msk /*!< Filter bit 18 */
+#define CAN_F11R2_FB19_Pos (19U)
+#define CAN_F11R2_FB19_Msk (0x1U << CAN_F11R2_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F11R2_FB19 CAN_F11R2_FB19_Msk /*!< Filter bit 19 */
+#define CAN_F11R2_FB20_Pos (20U)
+#define CAN_F11R2_FB20_Msk (0x1U << CAN_F11R2_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F11R2_FB20 CAN_F11R2_FB20_Msk /*!< Filter bit 20 */
+#define CAN_F11R2_FB21_Pos (21U)
+#define CAN_F11R2_FB21_Msk (0x1U << CAN_F11R2_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F11R2_FB21 CAN_F11R2_FB21_Msk /*!< Filter bit 21 */
+#define CAN_F11R2_FB22_Pos (22U)
+#define CAN_F11R2_FB22_Msk (0x1U << CAN_F11R2_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F11R2_FB22 CAN_F11R2_FB22_Msk /*!< Filter bit 22 */
+#define CAN_F11R2_FB23_Pos (23U)
+#define CAN_F11R2_FB23_Msk (0x1U << CAN_F11R2_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F11R2_FB23 CAN_F11R2_FB23_Msk /*!< Filter bit 23 */
+#define CAN_F11R2_FB24_Pos (24U)
+#define CAN_F11R2_FB24_Msk (0x1U << CAN_F11R2_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F11R2_FB24 CAN_F11R2_FB24_Msk /*!< Filter bit 24 */
+#define CAN_F11R2_FB25_Pos (25U)
+#define CAN_F11R2_FB25_Msk (0x1U << CAN_F11R2_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F11R2_FB25 CAN_F11R2_FB25_Msk /*!< Filter bit 25 */
+#define CAN_F11R2_FB26_Pos (26U)
+#define CAN_F11R2_FB26_Msk (0x1U << CAN_F11R2_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F11R2_FB26 CAN_F11R2_FB26_Msk /*!< Filter bit 26 */
+#define CAN_F11R2_FB27_Pos (27U)
+#define CAN_F11R2_FB27_Msk (0x1U << CAN_F11R2_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F11R2_FB27 CAN_F11R2_FB27_Msk /*!< Filter bit 27 */
+#define CAN_F11R2_FB28_Pos (28U)
+#define CAN_F11R2_FB28_Msk (0x1U << CAN_F11R2_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F11R2_FB28 CAN_F11R2_FB28_Msk /*!< Filter bit 28 */
+#define CAN_F11R2_FB29_Pos (29U)
+#define CAN_F11R2_FB29_Msk (0x1U << CAN_F11R2_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F11R2_FB29 CAN_F11R2_FB29_Msk /*!< Filter bit 29 */
+#define CAN_F11R2_FB30_Pos (30U)
+#define CAN_F11R2_FB30_Msk (0x1U << CAN_F11R2_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F11R2_FB30 CAN_F11R2_FB30_Msk /*!< Filter bit 30 */
+#define CAN_F11R2_FB31_Pos (31U)
+#define CAN_F11R2_FB31_Msk (0x1U << CAN_F11R2_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F11R2_FB31 CAN_F11R2_FB31_Msk /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F12R2 register ******************/
+#define CAN_F12R2_FB0_Pos (0U)
+#define CAN_F12R2_FB0_Msk (0x1U << CAN_F12R2_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F12R2_FB0 CAN_F12R2_FB0_Msk /*!< Filter bit 0 */
+#define CAN_F12R2_FB1_Pos (1U)
+#define CAN_F12R2_FB1_Msk (0x1U << CAN_F12R2_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F12R2_FB1 CAN_F12R2_FB1_Msk /*!< Filter bit 1 */
+#define CAN_F12R2_FB2_Pos (2U)
+#define CAN_F12R2_FB2_Msk (0x1U << CAN_F12R2_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F12R2_FB2 CAN_F12R2_FB2_Msk /*!< Filter bit 2 */
+#define CAN_F12R2_FB3_Pos (3U)
+#define CAN_F12R2_FB3_Msk (0x1U << CAN_F12R2_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F12R2_FB3 CAN_F12R2_FB3_Msk /*!< Filter bit 3 */
+#define CAN_F12R2_FB4_Pos (4U)
+#define CAN_F12R2_FB4_Msk (0x1U << CAN_F12R2_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F12R2_FB4 CAN_F12R2_FB4_Msk /*!< Filter bit 4 */
+#define CAN_F12R2_FB5_Pos (5U)
+#define CAN_F12R2_FB5_Msk (0x1U << CAN_F12R2_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F12R2_FB5 CAN_F12R2_FB5_Msk /*!< Filter bit 5 */
+#define CAN_F12R2_FB6_Pos (6U)
+#define CAN_F12R2_FB6_Msk (0x1U << CAN_F12R2_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F12R2_FB6 CAN_F12R2_FB6_Msk /*!< Filter bit 6 */
+#define CAN_F12R2_FB7_Pos (7U)
+#define CAN_F12R2_FB7_Msk (0x1U << CAN_F12R2_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F12R2_FB7 CAN_F12R2_FB7_Msk /*!< Filter bit 7 */
+#define CAN_F12R2_FB8_Pos (8U)
+#define CAN_F12R2_FB8_Msk (0x1U << CAN_F12R2_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F12R2_FB8 CAN_F12R2_FB8_Msk /*!< Filter bit 8 */
+#define CAN_F12R2_FB9_Pos (9U)
+#define CAN_F12R2_FB9_Msk (0x1U << CAN_F12R2_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F12R2_FB9 CAN_F12R2_FB9_Msk /*!< Filter bit 9 */
+#define CAN_F12R2_FB10_Pos (10U)
+#define CAN_F12R2_FB10_Msk (0x1U << CAN_F12R2_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F12R2_FB10 CAN_F12R2_FB10_Msk /*!< Filter bit 10 */
+#define CAN_F12R2_FB11_Pos (11U)
+#define CAN_F12R2_FB11_Msk (0x1U << CAN_F12R2_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F12R2_FB11 CAN_F12R2_FB11_Msk /*!< Filter bit 11 */
+#define CAN_F12R2_FB12_Pos (12U)
+#define CAN_F12R2_FB12_Msk (0x1U << CAN_F12R2_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F12R2_FB12 CAN_F12R2_FB12_Msk /*!< Filter bit 12 */
+#define CAN_F12R2_FB13_Pos (13U)
+#define CAN_F12R2_FB13_Msk (0x1U << CAN_F12R2_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F12R2_FB13 CAN_F12R2_FB13_Msk /*!< Filter bit 13 */
+#define CAN_F12R2_FB14_Pos (14U)
+#define CAN_F12R2_FB14_Msk (0x1U << CAN_F12R2_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F12R2_FB14 CAN_F12R2_FB14_Msk /*!< Filter bit 14 */
+#define CAN_F12R2_FB15_Pos (15U)
+#define CAN_F12R2_FB15_Msk (0x1U << CAN_F12R2_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F12R2_FB15 CAN_F12R2_FB15_Msk /*!< Filter bit 15 */
+#define CAN_F12R2_FB16_Pos (16U)
+#define CAN_F12R2_FB16_Msk (0x1U << CAN_F12R2_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F12R2_FB16 CAN_F12R2_FB16_Msk /*!< Filter bit 16 */
+#define CAN_F12R2_FB17_Pos (17U)
+#define CAN_F12R2_FB17_Msk (0x1U << CAN_F12R2_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F12R2_FB17 CAN_F12R2_FB17_Msk /*!< Filter bit 17 */
+#define CAN_F12R2_FB18_Pos (18U)
+#define CAN_F12R2_FB18_Msk (0x1U << CAN_F12R2_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F12R2_FB18 CAN_F12R2_FB18_Msk /*!< Filter bit 18 */
+#define CAN_F12R2_FB19_Pos (19U)
+#define CAN_F12R2_FB19_Msk (0x1U << CAN_F12R2_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F12R2_FB19 CAN_F12R2_FB19_Msk /*!< Filter bit 19 */
+#define CAN_F12R2_FB20_Pos (20U)
+#define CAN_F12R2_FB20_Msk (0x1U << CAN_F12R2_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F12R2_FB20 CAN_F12R2_FB20_Msk /*!< Filter bit 20 */
+#define CAN_F12R2_FB21_Pos (21U)
+#define CAN_F12R2_FB21_Msk (0x1U << CAN_F12R2_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F12R2_FB21 CAN_F12R2_FB21_Msk /*!< Filter bit 21 */
+#define CAN_F12R2_FB22_Pos (22U)
+#define CAN_F12R2_FB22_Msk (0x1U << CAN_F12R2_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F12R2_FB22 CAN_F12R2_FB22_Msk /*!< Filter bit 22 */
+#define CAN_F12R2_FB23_Pos (23U)
+#define CAN_F12R2_FB23_Msk (0x1U << CAN_F12R2_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F12R2_FB23 CAN_F12R2_FB23_Msk /*!< Filter bit 23 */
+#define CAN_F12R2_FB24_Pos (24U)
+#define CAN_F12R2_FB24_Msk (0x1U << CAN_F12R2_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F12R2_FB24 CAN_F12R2_FB24_Msk /*!< Filter bit 24 */
+#define CAN_F12R2_FB25_Pos (25U)
+#define CAN_F12R2_FB25_Msk (0x1U << CAN_F12R2_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F12R2_FB25 CAN_F12R2_FB25_Msk /*!< Filter bit 25 */
+#define CAN_F12R2_FB26_Pos (26U)
+#define CAN_F12R2_FB26_Msk (0x1U << CAN_F12R2_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F12R2_FB26 CAN_F12R2_FB26_Msk /*!< Filter bit 26 */
+#define CAN_F12R2_FB27_Pos (27U)
+#define CAN_F12R2_FB27_Msk (0x1U << CAN_F12R2_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F12R2_FB27 CAN_F12R2_FB27_Msk /*!< Filter bit 27 */
+#define CAN_F12R2_FB28_Pos (28U)
+#define CAN_F12R2_FB28_Msk (0x1U << CAN_F12R2_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F12R2_FB28 CAN_F12R2_FB28_Msk /*!< Filter bit 28 */
+#define CAN_F12R2_FB29_Pos (29U)
+#define CAN_F12R2_FB29_Msk (0x1U << CAN_F12R2_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F12R2_FB29 CAN_F12R2_FB29_Msk /*!< Filter bit 29 */
+#define CAN_F12R2_FB30_Pos (30U)
+#define CAN_F12R2_FB30_Msk (0x1U << CAN_F12R2_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F12R2_FB30 CAN_F12R2_FB30_Msk /*!< Filter bit 30 */
+#define CAN_F12R2_FB31_Pos (31U)
+#define CAN_F12R2_FB31_Msk (0x1U << CAN_F12R2_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F12R2_FB31 CAN_F12R2_FB31_Msk /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F13R2 register ******************/
+#define CAN_F13R2_FB0_Pos (0U)
+#define CAN_F13R2_FB0_Msk (0x1U << CAN_F13R2_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F13R2_FB0 CAN_F13R2_FB0_Msk /*!< Filter bit 0 */
+#define CAN_F13R2_FB1_Pos (1U)
+#define CAN_F13R2_FB1_Msk (0x1U << CAN_F13R2_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F13R2_FB1 CAN_F13R2_FB1_Msk /*!< Filter bit 1 */
+#define CAN_F13R2_FB2_Pos (2U)
+#define CAN_F13R2_FB2_Msk (0x1U << CAN_F13R2_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F13R2_FB2 CAN_F13R2_FB2_Msk /*!< Filter bit 2 */
+#define CAN_F13R2_FB3_Pos (3U)
+#define CAN_F13R2_FB3_Msk (0x1U << CAN_F13R2_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F13R2_FB3 CAN_F13R2_FB3_Msk /*!< Filter bit 3 */
+#define CAN_F13R2_FB4_Pos (4U)
+#define CAN_F13R2_FB4_Msk (0x1U << CAN_F13R2_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F13R2_FB4 CAN_F13R2_FB4_Msk /*!< Filter bit 4 */
+#define CAN_F13R2_FB5_Pos (5U)
+#define CAN_F13R2_FB5_Msk (0x1U << CAN_F13R2_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F13R2_FB5 CAN_F13R2_FB5_Msk /*!< Filter bit 5 */
+#define CAN_F13R2_FB6_Pos (6U)
+#define CAN_F13R2_FB6_Msk (0x1U << CAN_F13R2_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F13R2_FB6 CAN_F13R2_FB6_Msk /*!< Filter bit 6 */
+#define CAN_F13R2_FB7_Pos (7U)
+#define CAN_F13R2_FB7_Msk (0x1U << CAN_F13R2_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F13R2_FB7 CAN_F13R2_FB7_Msk /*!< Filter bit 7 */
+#define CAN_F13R2_FB8_Pos (8U)
+#define CAN_F13R2_FB8_Msk (0x1U << CAN_F13R2_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F13R2_FB8 CAN_F13R2_FB8_Msk /*!< Filter bit 8 */
+#define CAN_F13R2_FB9_Pos (9U)
+#define CAN_F13R2_FB9_Msk (0x1U << CAN_F13R2_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F13R2_FB9 CAN_F13R2_FB9_Msk /*!< Filter bit 9 */
+#define CAN_F13R2_FB10_Pos (10U)
+#define CAN_F13R2_FB10_Msk (0x1U << CAN_F13R2_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F13R2_FB10 CAN_F13R2_FB10_Msk /*!< Filter bit 10 */
+#define CAN_F13R2_FB11_Pos (11U)
+#define CAN_F13R2_FB11_Msk (0x1U << CAN_F13R2_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F13R2_FB11 CAN_F13R2_FB11_Msk /*!< Filter bit 11 */
+#define CAN_F13R2_FB12_Pos (12U)
+#define CAN_F13R2_FB12_Msk (0x1U << CAN_F13R2_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F13R2_FB12 CAN_F13R2_FB12_Msk /*!< Filter bit 12 */
+#define CAN_F13R2_FB13_Pos (13U)
+#define CAN_F13R2_FB13_Msk (0x1U << CAN_F13R2_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F13R2_FB13 CAN_F13R2_FB13_Msk /*!< Filter bit 13 */
+#define CAN_F13R2_FB14_Pos (14U)
+#define CAN_F13R2_FB14_Msk (0x1U << CAN_F13R2_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F13R2_FB14 CAN_F13R2_FB14_Msk /*!< Filter bit 14 */
+#define CAN_F13R2_FB15_Pos (15U)
+#define CAN_F13R2_FB15_Msk (0x1U << CAN_F13R2_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F13R2_FB15 CAN_F13R2_FB15_Msk /*!< Filter bit 15 */
+#define CAN_F13R2_FB16_Pos (16U)
+#define CAN_F13R2_FB16_Msk (0x1U << CAN_F13R2_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F13R2_FB16 CAN_F13R2_FB16_Msk /*!< Filter bit 16 */
+#define CAN_F13R2_FB17_Pos (17U)
+#define CAN_F13R2_FB17_Msk (0x1U << CAN_F13R2_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F13R2_FB17 CAN_F13R2_FB17_Msk /*!< Filter bit 17 */
+#define CAN_F13R2_FB18_Pos (18U)
+#define CAN_F13R2_FB18_Msk (0x1U << CAN_F13R2_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F13R2_FB18 CAN_F13R2_FB18_Msk /*!< Filter bit 18 */
+#define CAN_F13R2_FB19_Pos (19U)
+#define CAN_F13R2_FB19_Msk (0x1U << CAN_F13R2_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F13R2_FB19 CAN_F13R2_FB19_Msk /*!< Filter bit 19 */
+#define CAN_F13R2_FB20_Pos (20U)
+#define CAN_F13R2_FB20_Msk (0x1U << CAN_F13R2_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F13R2_FB20 CAN_F13R2_FB20_Msk /*!< Filter bit 20 */
+#define CAN_F13R2_FB21_Pos (21U)
+#define CAN_F13R2_FB21_Msk (0x1U << CAN_F13R2_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F13R2_FB21 CAN_F13R2_FB21_Msk /*!< Filter bit 21 */
+#define CAN_F13R2_FB22_Pos (22U)
+#define CAN_F13R2_FB22_Msk (0x1U << CAN_F13R2_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F13R2_FB22 CAN_F13R2_FB22_Msk /*!< Filter bit 22 */
+#define CAN_F13R2_FB23_Pos (23U)
+#define CAN_F13R2_FB23_Msk (0x1U << CAN_F13R2_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F13R2_FB23 CAN_F13R2_FB23_Msk /*!< Filter bit 23 */
+#define CAN_F13R2_FB24_Pos (24U)
+#define CAN_F13R2_FB24_Msk (0x1U << CAN_F13R2_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F13R2_FB24 CAN_F13R2_FB24_Msk /*!< Filter bit 24 */
+#define CAN_F13R2_FB25_Pos (25U)
+#define CAN_F13R2_FB25_Msk (0x1U << CAN_F13R2_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F13R2_FB25 CAN_F13R2_FB25_Msk /*!< Filter bit 25 */
+#define CAN_F13R2_FB26_Pos (26U)
+#define CAN_F13R2_FB26_Msk (0x1U << CAN_F13R2_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F13R2_FB26 CAN_F13R2_FB26_Msk /*!< Filter bit 26 */
+#define CAN_F13R2_FB27_Pos (27U)
+#define CAN_F13R2_FB27_Msk (0x1U << CAN_F13R2_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F13R2_FB27 CAN_F13R2_FB27_Msk /*!< Filter bit 27 */
+#define CAN_F13R2_FB28_Pos (28U)
+#define CAN_F13R2_FB28_Msk (0x1U << CAN_F13R2_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F13R2_FB28 CAN_F13R2_FB28_Msk /*!< Filter bit 28 */
+#define CAN_F13R2_FB29_Pos (29U)
+#define CAN_F13R2_FB29_Msk (0x1U << CAN_F13R2_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F13R2_FB29 CAN_F13R2_FB29_Msk /*!< Filter bit 29 */
+#define CAN_F13R2_FB30_Pos (30U)
+#define CAN_F13R2_FB30_Msk (0x1U << CAN_F13R2_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F13R2_FB30 CAN_F13R2_FB30_Msk /*!< Filter bit 30 */
+#define CAN_F13R2_FB31_Pos (31U)
+#define CAN_F13R2_FB31_Msk (0x1U << CAN_F13R2_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F13R2_FB31 CAN_F13R2_FB31_Msk /*!< Filter bit 31 */
+
+/******************************************************************************/
+/* */
+/* Serial Peripheral Interface */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for SPI_CR1 register ********************/
+#define SPI_CR1_CPHA_Pos (0U)
+#define SPI_CR1_CPHA_Msk (0x1U << SPI_CR1_CPHA_Pos) /*!< 0x00000001 */
+#define SPI_CR1_CPHA SPI_CR1_CPHA_Msk /*!< Clock Phase */
+#define SPI_CR1_CPOL_Pos (1U)
+#define SPI_CR1_CPOL_Msk (0x1U << SPI_CR1_CPOL_Pos) /*!< 0x00000002 */
+#define SPI_CR1_CPOL SPI_CR1_CPOL_Msk /*!< Clock Polarity */
+#define SPI_CR1_MSTR_Pos (2U)
+#define SPI_CR1_MSTR_Msk (0x1U << SPI_CR1_MSTR_Pos) /*!< 0x00000004 */
+#define SPI_CR1_MSTR SPI_CR1_MSTR_Msk /*!< Master Selection */
+
+#define SPI_CR1_BR_Pos (3U)
+#define SPI_CR1_BR_Msk (0x7U << SPI_CR1_BR_Pos) /*!< 0x00000038 */
+#define SPI_CR1_BR SPI_CR1_BR_Msk /*!< BR[2:0] bits (Baud Rate Control) */
+#define SPI_CR1_BR_0 (0x1U << SPI_CR1_BR_Pos) /*!< 0x00000008 */
+#define SPI_CR1_BR_1 (0x2U << SPI_CR1_BR_Pos) /*!< 0x00000010 */
+#define SPI_CR1_BR_2 (0x4U << SPI_CR1_BR_Pos) /*!< 0x00000020 */
+
+#define SPI_CR1_SPE_Pos (6U)
+#define SPI_CR1_SPE_Msk (0x1U << SPI_CR1_SPE_Pos) /*!< 0x00000040 */
+#define SPI_CR1_SPE SPI_CR1_SPE_Msk /*!< SPI Enable */
+#define SPI_CR1_LSBFIRST_Pos (7U)
+#define SPI_CR1_LSBFIRST_Msk (0x1U << SPI_CR1_LSBFIRST_Pos) /*!< 0x00000080 */
+#define SPI_CR1_LSBFIRST SPI_CR1_LSBFIRST_Msk /*!< Frame Format */
+#define SPI_CR1_SSI_Pos (8U)
+#define SPI_CR1_SSI_Msk (0x1U << SPI_CR1_SSI_Pos) /*!< 0x00000100 */
+#define SPI_CR1_SSI SPI_CR1_SSI_Msk /*!< Internal slave select */
+#define SPI_CR1_SSM_Pos (9U)
+#define SPI_CR1_SSM_Msk (0x1U << SPI_CR1_SSM_Pos) /*!< 0x00000200 */
+#define SPI_CR1_SSM SPI_CR1_SSM_Msk /*!< Software slave management */
+#define SPI_CR1_RXONLY_Pos (10U)
+#define SPI_CR1_RXONLY_Msk (0x1U << SPI_CR1_RXONLY_Pos) /*!< 0x00000400 */
+#define SPI_CR1_RXONLY SPI_CR1_RXONLY_Msk /*!< Receive only */
+#define SPI_CR1_DFF_Pos (11U)
+#define SPI_CR1_DFF_Msk (0x1U << SPI_CR1_DFF_Pos) /*!< 0x00000800 */
+#define SPI_CR1_DFF SPI_CR1_DFF_Msk /*!< Data Frame Format */
+#define SPI_CR1_CRCNEXT_Pos (12U)
+#define SPI_CR1_CRCNEXT_Msk (0x1U << SPI_CR1_CRCNEXT_Pos) /*!< 0x00001000 */
+#define SPI_CR1_CRCNEXT SPI_CR1_CRCNEXT_Msk /*!< Transmit CRC next */
+#define SPI_CR1_CRCEN_Pos (13U)
+#define SPI_CR1_CRCEN_Msk (0x1U << SPI_CR1_CRCEN_Pos) /*!< 0x00002000 */
+#define SPI_CR1_CRCEN SPI_CR1_CRCEN_Msk /*!< Hardware CRC calculation enable */
+#define SPI_CR1_BIDIOE_Pos (14U)
+#define SPI_CR1_BIDIOE_Msk (0x1U << SPI_CR1_BIDIOE_Pos) /*!< 0x00004000 */
+#define SPI_CR1_BIDIOE SPI_CR1_BIDIOE_Msk /*!< Output enable in bidirectional mode */
+#define SPI_CR1_BIDIMODE_Pos (15U)
+#define SPI_CR1_BIDIMODE_Msk (0x1U << SPI_CR1_BIDIMODE_Pos) /*!< 0x00008000 */
+#define SPI_CR1_BIDIMODE SPI_CR1_BIDIMODE_Msk /*!< Bidirectional data mode enable */
+
+/******************* Bit definition for SPI_CR2 register ********************/
+#define SPI_CR2_RXDMAEN_Pos (0U)
+#define SPI_CR2_RXDMAEN_Msk (0x1U << SPI_CR2_RXDMAEN_Pos) /*!< 0x00000001 */
+#define SPI_CR2_RXDMAEN SPI_CR2_RXDMAEN_Msk /*!< Rx Buffer DMA Enable */
+#define SPI_CR2_TXDMAEN_Pos (1U)
+#define SPI_CR2_TXDMAEN_Msk (0x1U << SPI_CR2_TXDMAEN_Pos) /*!< 0x00000002 */
+#define SPI_CR2_TXDMAEN SPI_CR2_TXDMAEN_Msk /*!< Tx Buffer DMA Enable */
+#define SPI_CR2_SSOE_Pos (2U)
+#define SPI_CR2_SSOE_Msk (0x1U << SPI_CR2_SSOE_Pos) /*!< 0x00000004 */
+#define SPI_CR2_SSOE SPI_CR2_SSOE_Msk /*!< SS Output Enable */
+#define SPI_CR2_ERRIE_Pos (5U)
+#define SPI_CR2_ERRIE_Msk (0x1U << SPI_CR2_ERRIE_Pos) /*!< 0x00000020 */
+#define SPI_CR2_ERRIE SPI_CR2_ERRIE_Msk /*!< Error Interrupt Enable */
+#define SPI_CR2_RXNEIE_Pos (6U)
+#define SPI_CR2_RXNEIE_Msk (0x1U << SPI_CR2_RXNEIE_Pos) /*!< 0x00000040 */
+#define SPI_CR2_RXNEIE SPI_CR2_RXNEIE_Msk /*!< RX buffer Not Empty Interrupt Enable */
+#define SPI_CR2_TXEIE_Pos (7U)
+#define SPI_CR2_TXEIE_Msk (0x1U << SPI_CR2_TXEIE_Pos) /*!< 0x00000080 */
+#define SPI_CR2_TXEIE SPI_CR2_TXEIE_Msk /*!< Tx buffer Empty Interrupt Enable */
+
+/******************** Bit definition for SPI_SR register ********************/
+#define SPI_SR_RXNE_Pos (0U)
+#define SPI_SR_RXNE_Msk (0x1U << SPI_SR_RXNE_Pos) /*!< 0x00000001 */
+#define SPI_SR_RXNE SPI_SR_RXNE_Msk /*!< Receive buffer Not Empty */
+#define SPI_SR_TXE_Pos (1U)
+#define SPI_SR_TXE_Msk (0x1U << SPI_SR_TXE_Pos) /*!< 0x00000002 */
+#define SPI_SR_TXE SPI_SR_TXE_Msk /*!< Transmit buffer Empty */
+#define SPI_SR_CHSIDE_Pos (2U)
+#define SPI_SR_CHSIDE_Msk (0x1U << SPI_SR_CHSIDE_Pos) /*!< 0x00000004 */
+#define SPI_SR_CHSIDE SPI_SR_CHSIDE_Msk /*!< Channel side */
+#define SPI_SR_UDR_Pos (3U)
+#define SPI_SR_UDR_Msk (0x1U << SPI_SR_UDR_Pos) /*!< 0x00000008 */
+#define SPI_SR_UDR SPI_SR_UDR_Msk /*!< Underrun flag */
+#define SPI_SR_CRCERR_Pos (4U)
+#define SPI_SR_CRCERR_Msk (0x1U << SPI_SR_CRCERR_Pos) /*!< 0x00000010 */
+#define SPI_SR_CRCERR SPI_SR_CRCERR_Msk /*!< CRC Error flag */
+#define SPI_SR_MODF_Pos (5U)
+#define SPI_SR_MODF_Msk (0x1U << SPI_SR_MODF_Pos) /*!< 0x00000020 */
+#define SPI_SR_MODF SPI_SR_MODF_Msk /*!< Mode fault */
+#define SPI_SR_OVR_Pos (6U)
+#define SPI_SR_OVR_Msk (0x1U << SPI_SR_OVR_Pos) /*!< 0x00000040 */
+#define SPI_SR_OVR SPI_SR_OVR_Msk /*!< Overrun flag */
+#define SPI_SR_BSY_Pos (7U)
+#define SPI_SR_BSY_Msk (0x1U << SPI_SR_BSY_Pos) /*!< 0x00000080 */
+#define SPI_SR_BSY SPI_SR_BSY_Msk /*!< Busy flag */
+
+/******************** Bit definition for SPI_DR register ********************/
+#define SPI_DR_DR_Pos (0U)
+#define SPI_DR_DR_Msk (0xFFFFU << SPI_DR_DR_Pos) /*!< 0x0000FFFF */
+#define SPI_DR_DR SPI_DR_DR_Msk /*!< Data Register */
+
+/******************* Bit definition for SPI_CRCPR register ******************/
+#define SPI_CRCPR_CRCPOLY_Pos (0U)
+#define SPI_CRCPR_CRCPOLY_Msk (0xFFFFU << SPI_CRCPR_CRCPOLY_Pos) /*!< 0x0000FFFF */
+#define SPI_CRCPR_CRCPOLY SPI_CRCPR_CRCPOLY_Msk /*!< CRC polynomial register */
+
+/****************** Bit definition for SPI_RXCRCR register ******************/
+#define SPI_RXCRCR_RXCRC_Pos (0U)
+#define SPI_RXCRCR_RXCRC_Msk (0xFFFFU << SPI_RXCRCR_RXCRC_Pos) /*!< 0x0000FFFF */
+#define SPI_RXCRCR_RXCRC SPI_RXCRCR_RXCRC_Msk /*!< Rx CRC Register */
+
+/****************** Bit definition for SPI_TXCRCR register ******************/
+#define SPI_TXCRCR_TXCRC_Pos (0U)
+#define SPI_TXCRCR_TXCRC_Msk (0xFFFFU << SPI_TXCRCR_TXCRC_Pos) /*!< 0x0000FFFF */
+#define SPI_TXCRCR_TXCRC SPI_TXCRCR_TXCRC_Msk /*!< Tx CRC Register */
+
+/****************** Bit definition for SPI_I2SCFGR register *****************/
+#define SPI_I2SCFGR_CHLEN_Pos (0U)
+#define SPI_I2SCFGR_CHLEN_Msk (0x1U << SPI_I2SCFGR_CHLEN_Pos) /*!< 0x00000001 */
+#define SPI_I2SCFGR_CHLEN SPI_I2SCFGR_CHLEN_Msk /*!< Channel length (number of bits per audio channel) */
+
+#define SPI_I2SCFGR_DATLEN_Pos (1U)
+#define SPI_I2SCFGR_DATLEN_Msk (0x3U << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000006 */
+#define SPI_I2SCFGR_DATLEN SPI_I2SCFGR_DATLEN_Msk /*!< DATLEN[1:0] bits (Data length to be transferred) */
+#define SPI_I2SCFGR_DATLEN_0 (0x1U << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000002 */
+#define SPI_I2SCFGR_DATLEN_1 (0x2U << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000004 */
+
+#define SPI_I2SCFGR_CKPOL_Pos (3U)
+#define SPI_I2SCFGR_CKPOL_Msk (0x1U << SPI_I2SCFGR_CKPOL_Pos) /*!< 0x00000008 */
+#define SPI_I2SCFGR_CKPOL SPI_I2SCFGR_CKPOL_Msk /*!< steady state clock polarity */
+
+#define SPI_I2SCFGR_I2SSTD_Pos (4U)
+#define SPI_I2SCFGR_I2SSTD_Msk (0x3U << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000030 */
+#define SPI_I2SCFGR_I2SSTD SPI_I2SCFGR_I2SSTD_Msk /*!< I2SSTD[1:0] bits (I2S standard selection) */
+#define SPI_I2SCFGR_I2SSTD_0 (0x1U << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000010 */
+#define SPI_I2SCFGR_I2SSTD_1 (0x2U << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000020 */
+
+#define SPI_I2SCFGR_PCMSYNC_Pos (7U)
+#define SPI_I2SCFGR_PCMSYNC_Msk (0x1U << SPI_I2SCFGR_PCMSYNC_Pos) /*!< 0x00000080 */
+#define SPI_I2SCFGR_PCMSYNC SPI_I2SCFGR_PCMSYNC_Msk /*!< PCM frame synchronization */
+
+#define SPI_I2SCFGR_I2SCFG_Pos (8U)
+#define SPI_I2SCFGR_I2SCFG_Msk (0x3U << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000300 */
+#define SPI_I2SCFGR_I2SCFG SPI_I2SCFGR_I2SCFG_Msk /*!< I2SCFG[1:0] bits (I2S configuration mode) */
+#define SPI_I2SCFGR_I2SCFG_0 (0x1U << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000100 */
+#define SPI_I2SCFGR_I2SCFG_1 (0x2U << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000200 */
+
+#define SPI_I2SCFGR_I2SE_Pos (10U)
+#define SPI_I2SCFGR_I2SE_Msk (0x1U << SPI_I2SCFGR_I2SE_Pos) /*!< 0x00000400 */
+#define SPI_I2SCFGR_I2SE SPI_I2SCFGR_I2SE_Msk /*!< I2S Enable */
+#define SPI_I2SCFGR_I2SMOD_Pos (11U)
+#define SPI_I2SCFGR_I2SMOD_Msk (0x1U << SPI_I2SCFGR_I2SMOD_Pos) /*!< 0x00000800 */
+#define SPI_I2SCFGR_I2SMOD SPI_I2SCFGR_I2SMOD_Msk /*!< I2S mode selection */
+
+/****************** Bit definition for SPI_I2SPR register *******************/
+#define SPI_I2SPR_I2SDIV_Pos (0U)
+#define SPI_I2SPR_I2SDIV_Msk (0xFFU << SPI_I2SPR_I2SDIV_Pos) /*!< 0x000000FF */
+#define SPI_I2SPR_I2SDIV SPI_I2SPR_I2SDIV_Msk /*!< I2S Linear prescaler */
+#define SPI_I2SPR_ODD_Pos (8U)
+#define SPI_I2SPR_ODD_Msk (0x1U << SPI_I2SPR_ODD_Pos) /*!< 0x00000100 */
+#define SPI_I2SPR_ODD SPI_I2SPR_ODD_Msk /*!< Odd factor for the prescaler */
+#define SPI_I2SPR_MCKOE_Pos (9U)
+#define SPI_I2SPR_MCKOE_Msk (0x1U << SPI_I2SPR_MCKOE_Pos) /*!< 0x00000200 */
+#define SPI_I2SPR_MCKOE SPI_I2SPR_MCKOE_Msk /*!< Master Clock Output Enable */
+
+/******************************************************************************/
+/* */
+/* Inter-integrated Circuit Interface */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for I2C_CR1 register ********************/
+#define I2C_CR1_PE_Pos (0U)
+#define I2C_CR1_PE_Msk (0x1U << I2C_CR1_PE_Pos) /*!< 0x00000001 */
+#define I2C_CR1_PE I2C_CR1_PE_Msk /*!< Peripheral Enable */
+#define I2C_CR1_SMBUS_Pos (1U)
+#define I2C_CR1_SMBUS_Msk (0x1U << I2C_CR1_SMBUS_Pos) /*!< 0x00000002 */
+#define I2C_CR1_SMBUS I2C_CR1_SMBUS_Msk /*!< SMBus Mode */
+#define I2C_CR1_SMBTYPE_Pos (3U)
+#define I2C_CR1_SMBTYPE_Msk (0x1U << I2C_CR1_SMBTYPE_Pos) /*!< 0x00000008 */
+#define I2C_CR1_SMBTYPE I2C_CR1_SMBTYPE_Msk /*!< SMBus Type */
+#define I2C_CR1_ENARP_Pos (4U)
+#define I2C_CR1_ENARP_Msk (0x1U << I2C_CR1_ENARP_Pos) /*!< 0x00000010 */
+#define I2C_CR1_ENARP I2C_CR1_ENARP_Msk /*!< ARP Enable */
+#define I2C_CR1_ENPEC_Pos (5U)
+#define I2C_CR1_ENPEC_Msk (0x1U << I2C_CR1_ENPEC_Pos) /*!< 0x00000020 */
+#define I2C_CR1_ENPEC I2C_CR1_ENPEC_Msk /*!< PEC Enable */
+#define I2C_CR1_ENGC_Pos (6U)
+#define I2C_CR1_ENGC_Msk (0x1U << I2C_CR1_ENGC_Pos) /*!< 0x00000040 */
+#define I2C_CR1_ENGC I2C_CR1_ENGC_Msk /*!< General Call Enable */
+#define I2C_CR1_NOSTRETCH_Pos (7U)
+#define I2C_CR1_NOSTRETCH_Msk (0x1U << I2C_CR1_NOSTRETCH_Pos) /*!< 0x00000080 */
+#define I2C_CR1_NOSTRETCH I2C_CR1_NOSTRETCH_Msk /*!< Clock Stretching Disable (Slave mode) */
+#define I2C_CR1_START_Pos (8U)
+#define I2C_CR1_START_Msk (0x1U << I2C_CR1_START_Pos) /*!< 0x00000100 */
+#define I2C_CR1_START I2C_CR1_START_Msk /*!< Start Generation */
+#define I2C_CR1_STOP_Pos (9U)
+#define I2C_CR1_STOP_Msk (0x1U << I2C_CR1_STOP_Pos) /*!< 0x00000200 */
+#define I2C_CR1_STOP I2C_CR1_STOP_Msk /*!< Stop Generation */
+#define I2C_CR1_ACK_Pos (10U)
+#define I2C_CR1_ACK_Msk (0x1U << I2C_CR1_ACK_Pos) /*!< 0x00000400 */
+#define I2C_CR1_ACK I2C_CR1_ACK_Msk /*!< Acknowledge Enable */
+#define I2C_CR1_POS_Pos (11U)
+#define I2C_CR1_POS_Msk (0x1U << I2C_CR1_POS_Pos) /*!< 0x00000800 */
+#define I2C_CR1_POS I2C_CR1_POS_Msk /*!< Acknowledge/PEC Position (for data reception) */
+#define I2C_CR1_PEC_Pos (12U)
+#define I2C_CR1_PEC_Msk (0x1U << I2C_CR1_PEC_Pos) /*!< 0x00001000 */
+#define I2C_CR1_PEC I2C_CR1_PEC_Msk /*!< Packet Error Checking */
+#define I2C_CR1_ALERT_Pos (13U)
+#define I2C_CR1_ALERT_Msk (0x1U << I2C_CR1_ALERT_Pos) /*!< 0x00002000 */
+#define I2C_CR1_ALERT I2C_CR1_ALERT_Msk /*!< SMBus Alert */
+#define I2C_CR1_SWRST_Pos (15U)
+#define I2C_CR1_SWRST_Msk (0x1U << I2C_CR1_SWRST_Pos) /*!< 0x00008000 */
+#define I2C_CR1_SWRST I2C_CR1_SWRST_Msk /*!< Software Reset */
+
+/******************* Bit definition for I2C_CR2 register ********************/
+#define I2C_CR2_FREQ_Pos (0U)
+#define I2C_CR2_FREQ_Msk (0x3FU << I2C_CR2_FREQ_Pos) /*!< 0x0000003F */
+#define I2C_CR2_FREQ I2C_CR2_FREQ_Msk /*!< FREQ[5:0] bits (Peripheral Clock Frequency) */
+#define I2C_CR2_FREQ_0 (0x01U << I2C_CR2_FREQ_Pos) /*!< 0x00000001 */
+#define I2C_CR2_FREQ_1 (0x02U << I2C_CR2_FREQ_Pos) /*!< 0x00000002 */
+#define I2C_CR2_FREQ_2 (0x04U << I2C_CR2_FREQ_Pos) /*!< 0x00000004 */
+#define I2C_CR2_FREQ_3 (0x08U << I2C_CR2_FREQ_Pos) /*!< 0x00000008 */
+#define I2C_CR2_FREQ_4 (0x10U << I2C_CR2_FREQ_Pos) /*!< 0x00000010 */
+#define I2C_CR2_FREQ_5 (0x20U << I2C_CR2_FREQ_Pos) /*!< 0x00000020 */
+
+#define I2C_CR2_ITERREN_Pos (8U)
+#define I2C_CR2_ITERREN_Msk (0x1U << I2C_CR2_ITERREN_Pos) /*!< 0x00000100 */
+#define I2C_CR2_ITERREN I2C_CR2_ITERREN_Msk /*!< Error Interrupt Enable */
+#define I2C_CR2_ITEVTEN_Pos (9U)
+#define I2C_CR2_ITEVTEN_Msk (0x1U << I2C_CR2_ITEVTEN_Pos) /*!< 0x00000200 */
+#define I2C_CR2_ITEVTEN I2C_CR2_ITEVTEN_Msk /*!< Event Interrupt Enable */
+#define I2C_CR2_ITBUFEN_Pos (10U)
+#define I2C_CR2_ITBUFEN_Msk (0x1U << I2C_CR2_ITBUFEN_Pos) /*!< 0x00000400 */
+#define I2C_CR2_ITBUFEN I2C_CR2_ITBUFEN_Msk /*!< Buffer Interrupt Enable */
+#define I2C_CR2_DMAEN_Pos (11U)
+#define I2C_CR2_DMAEN_Msk (0x1U << I2C_CR2_DMAEN_Pos) /*!< 0x00000800 */
+#define I2C_CR2_DMAEN I2C_CR2_DMAEN_Msk /*!< DMA Requests Enable */
+#define I2C_CR2_LAST_Pos (12U)
+#define I2C_CR2_LAST_Msk (0x1U << I2C_CR2_LAST_Pos) /*!< 0x00001000 */
+#define I2C_CR2_LAST I2C_CR2_LAST_Msk /*!< DMA Last Transfer */
+
+/******************* Bit definition for I2C_OAR1 register *******************/
+#define I2C_OAR1_ADD1_7 ((uint32_t)0x000000FE) /*!< Interface Address */
+#define I2C_OAR1_ADD8_9 ((uint32_t)0x00000300) /*!< Interface Address */
+
+#define I2C_OAR1_ADD0_Pos (0U)
+#define I2C_OAR1_ADD0_Msk (0x1U << I2C_OAR1_ADD0_Pos) /*!< 0x00000001 */
+#define I2C_OAR1_ADD0 I2C_OAR1_ADD0_Msk /*!< Bit 0 */
+#define I2C_OAR1_ADD1_Pos (1U)
+#define I2C_OAR1_ADD1_Msk (0x1U << I2C_OAR1_ADD1_Pos) /*!< 0x00000002 */
+#define I2C_OAR1_ADD1 I2C_OAR1_ADD1_Msk /*!< Bit 1 */
+#define I2C_OAR1_ADD2_Pos (2U)
+#define I2C_OAR1_ADD2_Msk (0x1U << I2C_OAR1_ADD2_Pos) /*!< 0x00000004 */
+#define I2C_OAR1_ADD2 I2C_OAR1_ADD2_Msk /*!< Bit 2 */
+#define I2C_OAR1_ADD3_Pos (3U)
+#define I2C_OAR1_ADD3_Msk (0x1U << I2C_OAR1_ADD3_Pos) /*!< 0x00000008 */
+#define I2C_OAR1_ADD3 I2C_OAR1_ADD3_Msk /*!< Bit 3 */
+#define I2C_OAR1_ADD4_Pos (4U)
+#define I2C_OAR1_ADD4_Msk (0x1U << I2C_OAR1_ADD4_Pos) /*!< 0x00000010 */
+#define I2C_OAR1_ADD4 I2C_OAR1_ADD4_Msk /*!< Bit 4 */
+#define I2C_OAR1_ADD5_Pos (5U)
+#define I2C_OAR1_ADD5_Msk (0x1U << I2C_OAR1_ADD5_Pos) /*!< 0x00000020 */
+#define I2C_OAR1_ADD5 I2C_OAR1_ADD5_Msk /*!< Bit 5 */
+#define I2C_OAR1_ADD6_Pos (6U)
+#define I2C_OAR1_ADD6_Msk (0x1U << I2C_OAR1_ADD6_Pos) /*!< 0x00000040 */
+#define I2C_OAR1_ADD6 I2C_OAR1_ADD6_Msk /*!< Bit 6 */
+#define I2C_OAR1_ADD7_Pos (7U)
+#define I2C_OAR1_ADD7_Msk (0x1U << I2C_OAR1_ADD7_Pos) /*!< 0x00000080 */
+#define I2C_OAR1_ADD7 I2C_OAR1_ADD7_Msk /*!< Bit 7 */
+#define I2C_OAR1_ADD8_Pos (8U)
+#define I2C_OAR1_ADD8_Msk (0x1U << I2C_OAR1_ADD8_Pos) /*!< 0x00000100 */
+#define I2C_OAR1_ADD8 I2C_OAR1_ADD8_Msk /*!< Bit 8 */
+#define I2C_OAR1_ADD9_Pos (9U)
+#define I2C_OAR1_ADD9_Msk (0x1U << I2C_OAR1_ADD9_Pos) /*!< 0x00000200 */
+#define I2C_OAR1_ADD9 I2C_OAR1_ADD9_Msk /*!< Bit 9 */
+
+#define I2C_OAR1_ADDMODE_Pos (15U)
+#define I2C_OAR1_ADDMODE_Msk (0x1U << I2C_OAR1_ADDMODE_Pos) /*!< 0x00008000 */
+#define I2C_OAR1_ADDMODE I2C_OAR1_ADDMODE_Msk /*!< Addressing Mode (Slave mode) */
+
+/******************* Bit definition for I2C_OAR2 register *******************/
+#define I2C_OAR2_ENDUAL_Pos (0U)
+#define I2C_OAR2_ENDUAL_Msk (0x1U << I2C_OAR2_ENDUAL_Pos) /*!< 0x00000001 */
+#define I2C_OAR2_ENDUAL I2C_OAR2_ENDUAL_Msk /*!< Dual addressing mode enable */
+#define I2C_OAR2_ADD2_Pos (1U)
+#define I2C_OAR2_ADD2_Msk (0x7FU << I2C_OAR2_ADD2_Pos) /*!< 0x000000FE */
+#define I2C_OAR2_ADD2 I2C_OAR2_ADD2_Msk /*!< Interface address */
+
+/******************* Bit definition for I2C_SR1 register ********************/
+#define I2C_SR1_SB_Pos (0U)
+#define I2C_SR1_SB_Msk (0x1U << I2C_SR1_SB_Pos) /*!< 0x00000001 */
+#define I2C_SR1_SB I2C_SR1_SB_Msk /*!< Start Bit (Master mode) */
+#define I2C_SR1_ADDR_Pos (1U)
+#define I2C_SR1_ADDR_Msk (0x1U << I2C_SR1_ADDR_Pos) /*!< 0x00000002 */
+#define I2C_SR1_ADDR I2C_SR1_ADDR_Msk /*!< Address sent (master mode)/matched (slave mode) */
+#define I2C_SR1_BTF_Pos (2U)
+#define I2C_SR1_BTF_Msk (0x1U << I2C_SR1_BTF_Pos) /*!< 0x00000004 */
+#define I2C_SR1_BTF I2C_SR1_BTF_Msk /*!< Byte Transfer Finished */
+#define I2C_SR1_ADD10_Pos (3U)
+#define I2C_SR1_ADD10_Msk (0x1U << I2C_SR1_ADD10_Pos) /*!< 0x00000008 */
+#define I2C_SR1_ADD10 I2C_SR1_ADD10_Msk /*!< 10-bit header sent (Master mode) */
+#define I2C_SR1_STOPF_Pos (4U)
+#define I2C_SR1_STOPF_Msk (0x1U << I2C_SR1_STOPF_Pos) /*!< 0x00000010 */
+#define I2C_SR1_STOPF I2C_SR1_STOPF_Msk /*!< Stop detection (Slave mode) */
+#define I2C_SR1_RXNE_Pos (6U)
+#define I2C_SR1_RXNE_Msk (0x1U << I2C_SR1_RXNE_Pos) /*!< 0x00000040 */
+#define I2C_SR1_RXNE I2C_SR1_RXNE_Msk /*!< Data Register not Empty (receivers) */
+#define I2C_SR1_TXE_Pos (7U)
+#define I2C_SR1_TXE_Msk (0x1U << I2C_SR1_TXE_Pos) /*!< 0x00000080 */
+#define I2C_SR1_TXE I2C_SR1_TXE_Msk /*!< Data Register Empty (transmitters) */
+#define I2C_SR1_BERR_Pos (8U)
+#define I2C_SR1_BERR_Msk (0x1U << I2C_SR1_BERR_Pos) /*!< 0x00000100 */
+#define I2C_SR1_BERR I2C_SR1_BERR_Msk /*!< Bus Error */
+#define I2C_SR1_ARLO_Pos (9U)
+#define I2C_SR1_ARLO_Msk (0x1U << I2C_SR1_ARLO_Pos) /*!< 0x00000200 */
+#define I2C_SR1_ARLO I2C_SR1_ARLO_Msk /*!< Arbitration Lost (master mode) */
+#define I2C_SR1_AF_Pos (10U)
+#define I2C_SR1_AF_Msk (0x1U << I2C_SR1_AF_Pos) /*!< 0x00000400 */
+#define I2C_SR1_AF I2C_SR1_AF_Msk /*!< Acknowledge Failure */
+#define I2C_SR1_OVR_Pos (11U)
+#define I2C_SR1_OVR_Msk (0x1U << I2C_SR1_OVR_Pos) /*!< 0x00000800 */
+#define I2C_SR1_OVR I2C_SR1_OVR_Msk /*!< Overrun/Underrun */
+#define I2C_SR1_PECERR_Pos (12U)
+#define I2C_SR1_PECERR_Msk (0x1U << I2C_SR1_PECERR_Pos) /*!< 0x00001000 */
+#define I2C_SR1_PECERR I2C_SR1_PECERR_Msk /*!< PEC Error in reception */
+#define I2C_SR1_TIMEOUT_Pos (14U)
+#define I2C_SR1_TIMEOUT_Msk (0x1U << I2C_SR1_TIMEOUT_Pos) /*!< 0x00004000 */
+#define I2C_SR1_TIMEOUT I2C_SR1_TIMEOUT_Msk /*!< Timeout or Tlow Error */
+#define I2C_SR1_SMBALERT_Pos (15U)
+#define I2C_SR1_SMBALERT_Msk (0x1U << I2C_SR1_SMBALERT_Pos) /*!< 0x00008000 */
+#define I2C_SR1_SMBALERT I2C_SR1_SMBALERT_Msk /*!< SMBus Alert */
+
+/******************* Bit definition for I2C_SR2 register ********************/
+#define I2C_SR2_MSL_Pos (0U)
+#define I2C_SR2_MSL_Msk (0x1U << I2C_SR2_MSL_Pos) /*!< 0x00000001 */
+#define I2C_SR2_MSL I2C_SR2_MSL_Msk /*!< Master/Slave */
+#define I2C_SR2_BUSY_Pos (1U)
+#define I2C_SR2_BUSY_Msk (0x1U << I2C_SR2_BUSY_Pos) /*!< 0x00000002 */
+#define I2C_SR2_BUSY I2C_SR2_BUSY_Msk /*!< Bus Busy */
+#define I2C_SR2_TRA_Pos (2U)
+#define I2C_SR2_TRA_Msk (0x1U << I2C_SR2_TRA_Pos) /*!< 0x00000004 */
+#define I2C_SR2_TRA I2C_SR2_TRA_Msk /*!< Transmitter/Receiver */
+#define I2C_SR2_GENCALL_Pos (4U)
+#define I2C_SR2_GENCALL_Msk (0x1U << I2C_SR2_GENCALL_Pos) /*!< 0x00000010 */
+#define I2C_SR2_GENCALL I2C_SR2_GENCALL_Msk /*!< General Call Address (Slave mode) */
+#define I2C_SR2_SMBDEFAULT_Pos (5U)
+#define I2C_SR2_SMBDEFAULT_Msk (0x1U << I2C_SR2_SMBDEFAULT_Pos) /*!< 0x00000020 */
+#define I2C_SR2_SMBDEFAULT I2C_SR2_SMBDEFAULT_Msk /*!< SMBus Device Default Address (Slave mode) */
+#define I2C_SR2_SMBHOST_Pos (6U)
+#define I2C_SR2_SMBHOST_Msk (0x1U << I2C_SR2_SMBHOST_Pos) /*!< 0x00000040 */
+#define I2C_SR2_SMBHOST I2C_SR2_SMBHOST_Msk /*!< SMBus Host Header (Slave mode) */
+#define I2C_SR2_DUALF_Pos (7U)
+#define I2C_SR2_DUALF_Msk (0x1U << I2C_SR2_DUALF_Pos) /*!< 0x00000080 */
+#define I2C_SR2_DUALF I2C_SR2_DUALF_Msk /*!< Dual Flag (Slave mode) */
+#define I2C_SR2_PEC_Pos (8U)
+#define I2C_SR2_PEC_Msk (0xFFU << I2C_SR2_PEC_Pos) /*!< 0x0000FF00 */
+#define I2C_SR2_PEC I2C_SR2_PEC_Msk /*!< Packet Error Checking Register */
+
+/******************* Bit definition for I2C_CCR register ********************/
+#define I2C_CCR_CCR_Pos (0U)
+#define I2C_CCR_CCR_Msk (0xFFFU << I2C_CCR_CCR_Pos) /*!< 0x00000FFF */
+#define I2C_CCR_CCR I2C_CCR_CCR_Msk /*!< Clock Control Register in Fast/Standard mode (Master mode) */
+#define I2C_CCR_DUTY_Pos (14U)
+#define I2C_CCR_DUTY_Msk (0x1U << I2C_CCR_DUTY_Pos) /*!< 0x00004000 */
+#define I2C_CCR_DUTY I2C_CCR_DUTY_Msk /*!< Fast Mode Duty Cycle */
+#define I2C_CCR_FS_Pos (15U)
+#define I2C_CCR_FS_Msk (0x1U << I2C_CCR_FS_Pos) /*!< 0x00008000 */
+#define I2C_CCR_FS I2C_CCR_FS_Msk /*!< I2C Master Mode Selection */
+
+/****************** Bit definition for I2C_TRISE register *******************/
+#define I2C_TRISE_TRISE_Pos (0U)
+#define I2C_TRISE_TRISE_Msk (0x3FU << I2C_TRISE_TRISE_Pos) /*!< 0x0000003F */
+#define I2C_TRISE_TRISE I2C_TRISE_TRISE_Msk /*!< Maximum Rise Time in Fast/Standard mode (Master mode) */
+
+/******************************************************************************/
+/* */
+/* Universal Synchronous Asynchronous Receiver Transmitter */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for USART_SR register *******************/
+#define USART_SR_PE_Pos (0U)
+#define USART_SR_PE_Msk (0x1U << USART_SR_PE_Pos) /*!< 0x00000001 */
+#define USART_SR_PE USART_SR_PE_Msk /*!< Parity Error */
+#define USART_SR_FE_Pos (1U)
+#define USART_SR_FE_Msk (0x1U << USART_SR_FE_Pos) /*!< 0x00000002 */
+#define USART_SR_FE USART_SR_FE_Msk /*!< Framing Error */
+#define USART_SR_NE_Pos (2U)
+#define USART_SR_NE_Msk (0x1U << USART_SR_NE_Pos) /*!< 0x00000004 */
+#define USART_SR_NE USART_SR_NE_Msk /*!< Noise Error Flag */
+#define USART_SR_ORE_Pos (3U)
+#define USART_SR_ORE_Msk (0x1U << USART_SR_ORE_Pos) /*!< 0x00000008 */
+#define USART_SR_ORE USART_SR_ORE_Msk /*!< OverRun Error */
+#define USART_SR_IDLE_Pos (4U)
+#define USART_SR_IDLE_Msk (0x1U << USART_SR_IDLE_Pos) /*!< 0x00000010 */
+#define USART_SR_IDLE USART_SR_IDLE_Msk /*!< IDLE line detected */
+#define USART_SR_RXNE_Pos (5U)
+#define USART_SR_RXNE_Msk (0x1U << USART_SR_RXNE_Pos) /*!< 0x00000020 */
+#define USART_SR_RXNE USART_SR_RXNE_Msk /*!< Read Data Register Not Empty */
+#define USART_SR_TC_Pos (6U)
+#define USART_SR_TC_Msk (0x1U << USART_SR_TC_Pos) /*!< 0x00000040 */
+#define USART_SR_TC USART_SR_TC_Msk /*!< Transmission Complete */
+#define USART_SR_TXE_Pos (7U)
+#define USART_SR_TXE_Msk (0x1U << USART_SR_TXE_Pos) /*!< 0x00000080 */
+#define USART_SR_TXE USART_SR_TXE_Msk /*!< Transmit Data Register Empty */
+#define USART_SR_LBD_Pos (8U)
+#define USART_SR_LBD_Msk (0x1U << USART_SR_LBD_Pos) /*!< 0x00000100 */
+#define USART_SR_LBD USART_SR_LBD_Msk /*!< LIN Break Detection Flag */
+#define USART_SR_CTS_Pos (9U)
+#define USART_SR_CTS_Msk (0x1U << USART_SR_CTS_Pos) /*!< 0x00000200 */
+#define USART_SR_CTS USART_SR_CTS_Msk /*!< CTS Flag */
+
+/******************* Bit definition for USART_DR register *******************/
+#define USART_DR_DR_Pos (0U)
+#define USART_DR_DR_Msk (0x1FFU << USART_DR_DR_Pos) /*!< 0x000001FF */
+#define USART_DR_DR USART_DR_DR_Msk /*!< Data value */
+
+/****************** Bit definition for USART_BRR register *******************/
+#define USART_BRR_DIV_Fraction_Pos (0U)
+#define USART_BRR_DIV_Fraction_Msk (0xFU << USART_BRR_DIV_Fraction_Pos) /*!< 0x0000000F */
+#define USART_BRR_DIV_Fraction USART_BRR_DIV_Fraction_Msk /*!< Fraction of USARTDIV */
+#define USART_BRR_DIV_Mantissa_Pos (4U)
+#define USART_BRR_DIV_Mantissa_Msk (0xFFFU << USART_BRR_DIV_Mantissa_Pos) /*!< 0x0000FFF0 */
+#define USART_BRR_DIV_Mantissa USART_BRR_DIV_Mantissa_Msk /*!< Mantissa of USARTDIV */
+
+/****************** Bit definition for USART_CR1 register *******************/
+#define USART_CR1_SBK_Pos (0U)
+#define USART_CR1_SBK_Msk (0x1U << USART_CR1_SBK_Pos) /*!< 0x00000001 */
+#define USART_CR1_SBK USART_CR1_SBK_Msk /*!< Send Break */
+#define USART_CR1_RWU_Pos (1U)
+#define USART_CR1_RWU_Msk (0x1U << USART_CR1_RWU_Pos) /*!< 0x00000002 */
+#define USART_CR1_RWU USART_CR1_RWU_Msk /*!< Receiver wakeup */
+#define USART_CR1_RE_Pos (2U)
+#define USART_CR1_RE_Msk (0x1U << USART_CR1_RE_Pos) /*!< 0x00000004 */
+#define USART_CR1_RE USART_CR1_RE_Msk /*!< Receiver Enable */
+#define USART_CR1_TE_Pos (3U)
+#define USART_CR1_TE_Msk (0x1U << USART_CR1_TE_Pos) /*!< 0x00000008 */
+#define USART_CR1_TE USART_CR1_TE_Msk /*!< Transmitter Enable */
+#define USART_CR1_IDLEIE_Pos (4U)
+#define USART_CR1_IDLEIE_Msk (0x1U << USART_CR1_IDLEIE_Pos) /*!< 0x00000010 */
+#define USART_CR1_IDLEIE USART_CR1_IDLEIE_Msk /*!< IDLE Interrupt Enable */
+#define USART_CR1_RXNEIE_Pos (5U)
+#define USART_CR1_RXNEIE_Msk (0x1U << USART_CR1_RXNEIE_Pos) /*!< 0x00000020 */
+#define USART_CR1_RXNEIE USART_CR1_RXNEIE_Msk /*!< RXNE Interrupt Enable */
+#define USART_CR1_TCIE_Pos (6U)
+#define USART_CR1_TCIE_Msk (0x1U << USART_CR1_TCIE_Pos) /*!< 0x00000040 */
+#define USART_CR1_TCIE USART_CR1_TCIE_Msk /*!< Transmission Complete Interrupt Enable */
+#define USART_CR1_TXEIE_Pos (7U)
+#define USART_CR1_TXEIE_Msk (0x1U << USART_CR1_TXEIE_Pos) /*!< 0x00000080 */
+#define USART_CR1_TXEIE USART_CR1_TXEIE_Msk /*!< PE Interrupt Enable */
+#define USART_CR1_PEIE_Pos (8U)
+#define USART_CR1_PEIE_Msk (0x1U << USART_CR1_PEIE_Pos) /*!< 0x00000100 */
+#define USART_CR1_PEIE USART_CR1_PEIE_Msk /*!< PE Interrupt Enable */
+#define USART_CR1_PS_Pos (9U)
+#define USART_CR1_PS_Msk (0x1U << USART_CR1_PS_Pos) /*!< 0x00000200 */
+#define USART_CR1_PS USART_CR1_PS_Msk /*!< Parity Selection */
+#define USART_CR1_PCE_Pos (10U)
+#define USART_CR1_PCE_Msk (0x1U << USART_CR1_PCE_Pos) /*!< 0x00000400 */
+#define USART_CR1_PCE USART_CR1_PCE_Msk /*!< Parity Control Enable */
+#define USART_CR1_WAKE_Pos (11U)
+#define USART_CR1_WAKE_Msk (0x1U << USART_CR1_WAKE_Pos) /*!< 0x00000800 */
+#define USART_CR1_WAKE USART_CR1_WAKE_Msk /*!< Wakeup method */
+#define USART_CR1_M_Pos (12U)
+#define USART_CR1_M_Msk (0x1U << USART_CR1_M_Pos) /*!< 0x00001000 */
+#define USART_CR1_M USART_CR1_M_Msk /*!< Word length */
+#define USART_CR1_UE_Pos (13U)
+#define USART_CR1_UE_Msk (0x1U << USART_CR1_UE_Pos) /*!< 0x00002000 */
+#define USART_CR1_UE USART_CR1_UE_Msk /*!< USART Enable */
+
+/****************** Bit definition for USART_CR2 register *******************/
+#define USART_CR2_ADD_Pos (0U)
+#define USART_CR2_ADD_Msk (0xFU << USART_CR2_ADD_Pos) /*!< 0x0000000F */
+#define USART_CR2_ADD USART_CR2_ADD_Msk /*!< Address of the USART node */
+#define USART_CR2_LBDL_Pos (5U)
+#define USART_CR2_LBDL_Msk (0x1U << USART_CR2_LBDL_Pos) /*!< 0x00000020 */
+#define USART_CR2_LBDL USART_CR2_LBDL_Msk /*!< LIN Break Detection Length */
+#define USART_CR2_LBDIE_Pos (6U)
+#define USART_CR2_LBDIE_Msk (0x1U << USART_CR2_LBDIE_Pos) /*!< 0x00000040 */
+#define USART_CR2_LBDIE USART_CR2_LBDIE_Msk /*!< LIN Break Detection Interrupt Enable */
+#define USART_CR2_LBCL_Pos (8U)
+#define USART_CR2_LBCL_Msk (0x1U << USART_CR2_LBCL_Pos) /*!< 0x00000100 */
+#define USART_CR2_LBCL USART_CR2_LBCL_Msk /*!< Last Bit Clock pulse */
+#define USART_CR2_CPHA_Pos (9U)
+#define USART_CR2_CPHA_Msk (0x1U << USART_CR2_CPHA_Pos) /*!< 0x00000200 */
+#define USART_CR2_CPHA USART_CR2_CPHA_Msk /*!< Clock Phase */
+#define USART_CR2_CPOL_Pos (10U)
+#define USART_CR2_CPOL_Msk (0x1U << USART_CR2_CPOL_Pos) /*!< 0x00000400 */
+#define USART_CR2_CPOL USART_CR2_CPOL_Msk /*!< Clock Polarity */
+#define USART_CR2_CLKEN_Pos (11U)
+#define USART_CR2_CLKEN_Msk (0x1U << USART_CR2_CLKEN_Pos) /*!< 0x00000800 */
+#define USART_CR2_CLKEN USART_CR2_CLKEN_Msk /*!< Clock Enable */
+
+#define USART_CR2_STOP_Pos (12U)
+#define USART_CR2_STOP_Msk (0x3U << USART_CR2_STOP_Pos) /*!< 0x00003000 */
+#define USART_CR2_STOP USART_CR2_STOP_Msk /*!< STOP[1:0] bits (STOP bits) */
+#define USART_CR2_STOP_0 (0x1U << USART_CR2_STOP_Pos) /*!< 0x00001000 */
+#define USART_CR2_STOP_1 (0x2U << USART_CR2_STOP_Pos) /*!< 0x00002000 */
+
+#define USART_CR2_LINEN_Pos (14U)
+#define USART_CR2_LINEN_Msk (0x1U << USART_CR2_LINEN_Pos) /*!< 0x00004000 */
+#define USART_CR2_LINEN USART_CR2_LINEN_Msk /*!< LIN mode enable */
+
+/****************** Bit definition for USART_CR3 register *******************/
+#define USART_CR3_EIE_Pos (0U)
+#define USART_CR3_EIE_Msk (0x1U << USART_CR3_EIE_Pos) /*!< 0x00000001 */
+#define USART_CR3_EIE USART_CR3_EIE_Msk /*!< Error Interrupt Enable */
+#define USART_CR3_IREN_Pos (1U)
+#define USART_CR3_IREN_Msk (0x1U << USART_CR3_IREN_Pos) /*!< 0x00000002 */
+#define USART_CR3_IREN USART_CR3_IREN_Msk /*!< IrDA mode Enable */
+#define USART_CR3_IRLP_Pos (2U)
+#define USART_CR3_IRLP_Msk (0x1U << USART_CR3_IRLP_Pos) /*!< 0x00000004 */
+#define USART_CR3_IRLP USART_CR3_IRLP_Msk /*!< IrDA Low-Power */
+#define USART_CR3_HDSEL_Pos (3U)
+#define USART_CR3_HDSEL_Msk (0x1U << USART_CR3_HDSEL_Pos) /*!< 0x00000008 */
+#define USART_CR3_HDSEL USART_CR3_HDSEL_Msk /*!< Half-Duplex Selection */
+#define USART_CR3_NACK_Pos (4U)
+#define USART_CR3_NACK_Msk (0x1U << USART_CR3_NACK_Pos) /*!< 0x00000010 */
+#define USART_CR3_NACK USART_CR3_NACK_Msk /*!< Smartcard NACK enable */
+#define USART_CR3_SCEN_Pos (5U)
+#define USART_CR3_SCEN_Msk (0x1U << USART_CR3_SCEN_Pos) /*!< 0x00000020 */
+#define USART_CR3_SCEN USART_CR3_SCEN_Msk /*!< Smartcard mode enable */
+#define USART_CR3_DMAR_Pos (6U)
+#define USART_CR3_DMAR_Msk (0x1U << USART_CR3_DMAR_Pos) /*!< 0x00000040 */
+#define USART_CR3_DMAR USART_CR3_DMAR_Msk /*!< DMA Enable Receiver */
+#define USART_CR3_DMAT_Pos (7U)
+#define USART_CR3_DMAT_Msk (0x1U << USART_CR3_DMAT_Pos) /*!< 0x00000080 */
+#define USART_CR3_DMAT USART_CR3_DMAT_Msk /*!< DMA Enable Transmitter */
+#define USART_CR3_RTSE_Pos (8U)
+#define USART_CR3_RTSE_Msk (0x1U << USART_CR3_RTSE_Pos) /*!< 0x00000100 */
+#define USART_CR3_RTSE USART_CR3_RTSE_Msk /*!< RTS Enable */
+#define USART_CR3_CTSE_Pos (9U)
+#define USART_CR3_CTSE_Msk (0x1U << USART_CR3_CTSE_Pos) /*!< 0x00000200 */
+#define USART_CR3_CTSE USART_CR3_CTSE_Msk /*!< CTS Enable */
+#define USART_CR3_CTSIE_Pos (10U)
+#define USART_CR3_CTSIE_Msk (0x1U << USART_CR3_CTSIE_Pos) /*!< 0x00000400 */
+#define USART_CR3_CTSIE USART_CR3_CTSIE_Msk /*!< CTS Interrupt Enable */
+
+/****************** Bit definition for USART_GTPR register ******************/
+#define USART_GTPR_PSC_Pos (0U)
+#define USART_GTPR_PSC_Msk (0xFFU << USART_GTPR_PSC_Pos) /*!< 0x000000FF */
+#define USART_GTPR_PSC USART_GTPR_PSC_Msk /*!< PSC[7:0] bits (Prescaler value) */
+#define USART_GTPR_PSC_0 (0x01U << USART_GTPR_PSC_Pos) /*!< 0x00000001 */
+#define USART_GTPR_PSC_1 (0x02U << USART_GTPR_PSC_Pos) /*!< 0x00000002 */
+#define USART_GTPR_PSC_2 (0x04U << USART_GTPR_PSC_Pos) /*!< 0x00000004 */
+#define USART_GTPR_PSC_3 (0x08U << USART_GTPR_PSC_Pos) /*!< 0x00000008 */
+#define USART_GTPR_PSC_4 (0x10U << USART_GTPR_PSC_Pos) /*!< 0x00000010 */
+#define USART_GTPR_PSC_5 (0x20U << USART_GTPR_PSC_Pos) /*!< 0x00000020 */
+#define USART_GTPR_PSC_6 (0x40U << USART_GTPR_PSC_Pos) /*!< 0x00000040 */
+#define USART_GTPR_PSC_7 (0x80U << USART_GTPR_PSC_Pos) /*!< 0x00000080 */
+
+#define USART_GTPR_GT_Pos (8U)
+#define USART_GTPR_GT_Msk (0xFFU << USART_GTPR_GT_Pos) /*!< 0x0000FF00 */
+#define USART_GTPR_GT USART_GTPR_GT_Msk /*!< Guard time value */
+
+/******************************************************************************/
+/* */
+/* Debug MCU */
+/* */
+/******************************************************************************/
+
+/**************** Bit definition for DBGMCU_IDCODE register *****************/
+#define DBGMCU_IDCODE_DEV_ID_Pos (0U)
+#define DBGMCU_IDCODE_DEV_ID_Msk (0xFFFU << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */
+#define DBGMCU_IDCODE_DEV_ID DBGMCU_IDCODE_DEV_ID_Msk /*!< Device Identifier */
+
+#define DBGMCU_IDCODE_REV_ID_Pos (16U)
+#define DBGMCU_IDCODE_REV_ID_Msk (0xFFFFU << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */
+#define DBGMCU_IDCODE_REV_ID DBGMCU_IDCODE_REV_ID_Msk /*!< REV_ID[15:0] bits (Revision Identifier) */
+#define DBGMCU_IDCODE_REV_ID_0 (0x0001U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00010000 */
+#define DBGMCU_IDCODE_REV_ID_1 (0x0002U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00020000 */
+#define DBGMCU_IDCODE_REV_ID_2 (0x0004U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00040000 */
+#define DBGMCU_IDCODE_REV_ID_3 (0x0008U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00080000 */
+#define DBGMCU_IDCODE_REV_ID_4 (0x0010U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00100000 */
+#define DBGMCU_IDCODE_REV_ID_5 (0x0020U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00200000 */
+#define DBGMCU_IDCODE_REV_ID_6 (0x0040U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00400000 */
+#define DBGMCU_IDCODE_REV_ID_7 (0x0080U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00800000 */
+#define DBGMCU_IDCODE_REV_ID_8 (0x0100U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x01000000 */
+#define DBGMCU_IDCODE_REV_ID_9 (0x0200U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x02000000 */
+#define DBGMCU_IDCODE_REV_ID_10 (0x0400U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x04000000 */
+#define DBGMCU_IDCODE_REV_ID_11 (0x0800U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x08000000 */
+#define DBGMCU_IDCODE_REV_ID_12 (0x1000U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x10000000 */
+#define DBGMCU_IDCODE_REV_ID_13 (0x2000U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x20000000 */
+#define DBGMCU_IDCODE_REV_ID_14 (0x4000U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x40000000 */
+#define DBGMCU_IDCODE_REV_ID_15 (0x8000U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x80000000 */
+
+/****************** Bit definition for DBGMCU_CR register *******************/
+#define DBGMCU_CR_DBG_SLEEP_Pos (0U)
+#define DBGMCU_CR_DBG_SLEEP_Msk (0x1U << DBGMCU_CR_DBG_SLEEP_Pos) /*!< 0x00000001 */
+#define DBGMCU_CR_DBG_SLEEP DBGMCU_CR_DBG_SLEEP_Msk /*!< Debug Sleep Mode */
+#define DBGMCU_CR_DBG_STOP_Pos (1U)
+#define DBGMCU_CR_DBG_STOP_Msk (0x1U << DBGMCU_CR_DBG_STOP_Pos) /*!< 0x00000002 */
+#define DBGMCU_CR_DBG_STOP DBGMCU_CR_DBG_STOP_Msk /*!< Debug Stop Mode */
+#define DBGMCU_CR_DBG_STANDBY_Pos (2U)
+#define DBGMCU_CR_DBG_STANDBY_Msk (0x1U << DBGMCU_CR_DBG_STANDBY_Pos) /*!< 0x00000004 */
+#define DBGMCU_CR_DBG_STANDBY DBGMCU_CR_DBG_STANDBY_Msk /*!< Debug Standby mode */
+#define DBGMCU_CR_TRACE_IOEN_Pos (5U)
+#define DBGMCU_CR_TRACE_IOEN_Msk (0x1U << DBGMCU_CR_TRACE_IOEN_Pos) /*!< 0x00000020 */
+#define DBGMCU_CR_TRACE_IOEN DBGMCU_CR_TRACE_IOEN_Msk /*!< Trace Pin Assignment Control */
+
+#define DBGMCU_CR_TRACE_MODE_Pos (6U)
+#define DBGMCU_CR_TRACE_MODE_Msk (0x3U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x000000C0 */
+#define DBGMCU_CR_TRACE_MODE DBGMCU_CR_TRACE_MODE_Msk /*!< TRACE_MODE[1:0] bits (Trace Pin Assignment Control) */
+#define DBGMCU_CR_TRACE_MODE_0 (0x1U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000040 */
+#define DBGMCU_CR_TRACE_MODE_1 (0x2U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000080 */
+
+#define DBGMCU_CR_DBG_IWDG_STOP_Pos (8U)
+#define DBGMCU_CR_DBG_IWDG_STOP_Msk (0x1U << DBGMCU_CR_DBG_IWDG_STOP_Pos) /*!< 0x00000100 */
+#define DBGMCU_CR_DBG_IWDG_STOP DBGMCU_CR_DBG_IWDG_STOP_Msk /*!< Debug Independent Watchdog stopped when Core is halted */
+#define DBGMCU_CR_DBG_WWDG_STOP_Pos (9U)
+#define DBGMCU_CR_DBG_WWDG_STOP_Msk (0x1U << DBGMCU_CR_DBG_WWDG_STOP_Pos) /*!< 0x00000200 */
+#define DBGMCU_CR_DBG_WWDG_STOP DBGMCU_CR_DBG_WWDG_STOP_Msk /*!< Debug Window Watchdog stopped when Core is halted */
+#define DBGMCU_CR_DBG_TIM1_STOP_Pos (10U)
+#define DBGMCU_CR_DBG_TIM1_STOP_Msk (0x1U << DBGMCU_CR_DBG_TIM1_STOP_Pos) /*!< 0x00000400 */
+#define DBGMCU_CR_DBG_TIM1_STOP DBGMCU_CR_DBG_TIM1_STOP_Msk /*!< TIM1 counter stopped when core is halted */
+#define DBGMCU_CR_DBG_TIM2_STOP_Pos (11U)
+#define DBGMCU_CR_DBG_TIM2_STOP_Msk (0x1U << DBGMCU_CR_DBG_TIM2_STOP_Pos) /*!< 0x00000800 */
+#define DBGMCU_CR_DBG_TIM2_STOP DBGMCU_CR_DBG_TIM2_STOP_Msk /*!< TIM2 counter stopped when core is halted */
+#define DBGMCU_CR_DBG_TIM3_STOP_Pos (12U)
+#define DBGMCU_CR_DBG_TIM3_STOP_Msk (0x1U << DBGMCU_CR_DBG_TIM3_STOP_Pos) /*!< 0x00001000 */
+#define DBGMCU_CR_DBG_TIM3_STOP DBGMCU_CR_DBG_TIM3_STOP_Msk /*!< TIM3 counter stopped when core is halted */
+#define DBGMCU_CR_DBG_TIM4_STOP_Pos (13U)
+#define DBGMCU_CR_DBG_TIM4_STOP_Msk (0x1U << DBGMCU_CR_DBG_TIM4_STOP_Pos) /*!< 0x00002000 */
+#define DBGMCU_CR_DBG_TIM4_STOP DBGMCU_CR_DBG_TIM4_STOP_Msk /*!< TIM4 counter stopped when core is halted */
+#define DBGMCU_CR_DBG_CAN1_STOP_Pos (14U)
+#define DBGMCU_CR_DBG_CAN1_STOP_Msk (0x1U << DBGMCU_CR_DBG_CAN1_STOP_Pos) /*!< 0x00004000 */
+#define DBGMCU_CR_DBG_CAN1_STOP DBGMCU_CR_DBG_CAN1_STOP_Msk /*!< Debug CAN1 stopped when Core is halted */
+#define DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT_Pos (15U)
+#define DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT_Msk (0x1U << DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT_Pos) /*!< 0x00008000 */
+#define DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT_Msk /*!< SMBUS timeout mode stopped when Core is halted */
+#define DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT_Pos (16U)
+#define DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT_Msk (0x1U << DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT_Pos) /*!< 0x00010000 */
+#define DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT_Msk /*!< SMBUS timeout mode stopped when Core is halted */
+#define DBGMCU_CR_DBG_TIM8_STOP_Pos (17U)
+#define DBGMCU_CR_DBG_TIM8_STOP_Msk (0x1U << DBGMCU_CR_DBG_TIM8_STOP_Pos) /*!< 0x00020000 */
+#define DBGMCU_CR_DBG_TIM8_STOP DBGMCU_CR_DBG_TIM8_STOP_Msk /*!< TIM8 counter stopped when core is halted */
+#define DBGMCU_CR_DBG_TIM5_STOP_Pos (18U)
+#define DBGMCU_CR_DBG_TIM5_STOP_Msk (0x1U << DBGMCU_CR_DBG_TIM5_STOP_Pos) /*!< 0x00040000 */
+#define DBGMCU_CR_DBG_TIM5_STOP DBGMCU_CR_DBG_TIM5_STOP_Msk /*!< TIM5 counter stopped when core is halted */
+#define DBGMCU_CR_DBG_TIM6_STOP_Pos (19U)
+#define DBGMCU_CR_DBG_TIM6_STOP_Msk (0x1U << DBGMCU_CR_DBG_TIM6_STOP_Pos) /*!< 0x00080000 */
+#define DBGMCU_CR_DBG_TIM6_STOP DBGMCU_CR_DBG_TIM6_STOP_Msk /*!< TIM6 counter stopped when core is halted */
+#define DBGMCU_CR_DBG_TIM7_STOP_Pos (20U)
+#define DBGMCU_CR_DBG_TIM7_STOP_Msk (0x1U << DBGMCU_CR_DBG_TIM7_STOP_Pos) /*!< 0x00100000 */
+#define DBGMCU_CR_DBG_TIM7_STOP DBGMCU_CR_DBG_TIM7_STOP_Msk /*!< TIM7 counter stopped when core is halted */
+#define DBGMCU_CR_DBG_TIM12_STOP_Pos (25U)
+#define DBGMCU_CR_DBG_TIM12_STOP_Msk (0x1U << DBGMCU_CR_DBG_TIM12_STOP_Pos) /*!< 0x02000000 */
+#define DBGMCU_CR_DBG_TIM12_STOP DBGMCU_CR_DBG_TIM12_STOP_Msk /*!< Debug TIM12 stopped when Core is halted */
+#define DBGMCU_CR_DBG_TIM13_STOP_Pos (26U)
+#define DBGMCU_CR_DBG_TIM13_STOP_Msk (0x1U << DBGMCU_CR_DBG_TIM13_STOP_Pos) /*!< 0x04000000 */
+#define DBGMCU_CR_DBG_TIM13_STOP DBGMCU_CR_DBG_TIM13_STOP_Msk /*!< Debug TIM13 stopped when Core is halted */
+#define DBGMCU_CR_DBG_TIM14_STOP_Pos (27U)
+#define DBGMCU_CR_DBG_TIM14_STOP_Msk (0x1U << DBGMCU_CR_DBG_TIM14_STOP_Pos) /*!< 0x08000000 */
+#define DBGMCU_CR_DBG_TIM14_STOP DBGMCU_CR_DBG_TIM14_STOP_Msk /*!< Debug TIM14 stopped when Core is halted */
+#define DBGMCU_CR_DBG_TIM9_STOP_Pos (28U)
+#define DBGMCU_CR_DBG_TIM9_STOP_Msk (0x1U << DBGMCU_CR_DBG_TIM9_STOP_Pos) /*!< 0x10000000 */
+#define DBGMCU_CR_DBG_TIM9_STOP DBGMCU_CR_DBG_TIM9_STOP_Msk /*!< Debug TIM9 stopped when Core is halted */
+#define DBGMCU_CR_DBG_TIM10_STOP_Pos (29U)
+#define DBGMCU_CR_DBG_TIM10_STOP_Msk (0x1U << DBGMCU_CR_DBG_TIM10_STOP_Pos) /*!< 0x20000000 */
+#define DBGMCU_CR_DBG_TIM10_STOP DBGMCU_CR_DBG_TIM10_STOP_Msk /*!< Debug TIM10 stopped when Core is halted */
+#define DBGMCU_CR_DBG_TIM11_STOP_Pos (30U)
+#define DBGMCU_CR_DBG_TIM11_STOP_Msk (0x1U << DBGMCU_CR_DBG_TIM11_STOP_Pos) /*!< 0x40000000 */
+#define DBGMCU_CR_DBG_TIM11_STOP DBGMCU_CR_DBG_TIM11_STOP_Msk /*!< Debug TIM11 stopped when Core is halted */
+
+/******************************************************************************/
+/* */
+/* FLASH and Option Bytes Registers */
+/* */
+/******************************************************************************/
+/******************* Bit definition for FLASH_ACR register ******************/
+#define FLASH_ACR_LATENCY_Pos (0U)
+#define FLASH_ACR_LATENCY_Msk (0x7U << FLASH_ACR_LATENCY_Pos) /*!< 0x00000007 */
+#define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk /*!< LATENCY[2:0] bits (Latency) */
+#define FLASH_ACR_LATENCY_0 (0x1U << FLASH_ACR_LATENCY_Pos) /*!< 0x00000001 */
+#define FLASH_ACR_LATENCY_1 (0x2U << FLASH_ACR_LATENCY_Pos) /*!< 0x00000002 */
+#define FLASH_ACR_LATENCY_2 (0x4U << FLASH_ACR_LATENCY_Pos) /*!< 0x00000004 */
+
+#define FLASH_ACR_HLFCYA_Pos (3U)
+#define FLASH_ACR_HLFCYA_Msk (0x1U << FLASH_ACR_HLFCYA_Pos) /*!< 0x00000008 */
+#define FLASH_ACR_HLFCYA FLASH_ACR_HLFCYA_Msk /*!< Flash Half Cycle Access Enable */
+#define FLASH_ACR_PRFTBE_Pos (4U)
+#define FLASH_ACR_PRFTBE_Msk (0x1U << FLASH_ACR_PRFTBE_Pos) /*!< 0x00000010 */
+#define FLASH_ACR_PRFTBE FLASH_ACR_PRFTBE_Msk /*!< Prefetch Buffer Enable */
+#define FLASH_ACR_PRFTBS_Pos (5U)
+#define FLASH_ACR_PRFTBS_Msk (0x1U << FLASH_ACR_PRFTBS_Pos) /*!< 0x00000020 */
+#define FLASH_ACR_PRFTBS FLASH_ACR_PRFTBS_Msk /*!< Prefetch Buffer Status */
+
+/****************** Bit definition for FLASH_KEYR register ******************/
+#define FLASH_KEYR_FKEYR_Pos (0U)
+#define FLASH_KEYR_FKEYR_Msk (0xFFFFFFFFU << FLASH_KEYR_FKEYR_Pos) /*!< 0xFFFFFFFF */
+#define FLASH_KEYR_FKEYR FLASH_KEYR_FKEYR_Msk /*!< FPEC Key */
+
+#define RDP_KEY_Pos (0U)
+#define RDP_KEY_Msk (0xA5U << RDP_KEY_Pos) /*!< 0x000000A5 */
+#define RDP_KEY RDP_KEY_Msk /*!< RDP Key */
+#define FLASH_KEY1_Pos (0U)
+#define FLASH_KEY1_Msk (0x45670123U << FLASH_KEY1_Pos) /*!< 0x45670123 */
+#define FLASH_KEY1 FLASH_KEY1_Msk /*!< FPEC Key1 */
+#define FLASH_KEY2_Pos (0U)
+#define FLASH_KEY2_Msk (0xCDEF89ABU << FLASH_KEY2_Pos) /*!< 0xCDEF89AB */
+#define FLASH_KEY2 FLASH_KEY2_Msk /*!< FPEC Key2 */
+
+/***************** Bit definition for FLASH_OPTKEYR register ****************/
+#define FLASH_OPTKEYR_OPTKEYR_Pos (0U)
+#define FLASH_OPTKEYR_OPTKEYR_Msk (0xFFFFFFFFU << FLASH_OPTKEYR_OPTKEYR_Pos) /*!< 0xFFFFFFFF */
+#define FLASH_OPTKEYR_OPTKEYR FLASH_OPTKEYR_OPTKEYR_Msk /*!< Option Byte Key */
+
+#define FLASH_OPTKEY1 FLASH_KEY1 /*!< Option Byte Key1 */
+#define FLASH_OPTKEY2 FLASH_KEY2 /*!< Option Byte Key2 */
+
+/****************** Bit definition for FLASH_SR register ********************/
+#define FLASH_SR_BSY_Pos (0U)
+#define FLASH_SR_BSY_Msk (0x1U << FLASH_SR_BSY_Pos) /*!< 0x00000001 */
+#define FLASH_SR_BSY FLASH_SR_BSY_Msk /*!< Busy */
+#define FLASH_SR_PGERR_Pos (2U)
+#define FLASH_SR_PGERR_Msk (0x1U << FLASH_SR_PGERR_Pos) /*!< 0x00000004 */
+#define FLASH_SR_PGERR FLASH_SR_PGERR_Msk /*!< Programming Error */
+#define FLASH_SR_WRPRTERR_Pos (4U)
+#define FLASH_SR_WRPRTERR_Msk (0x1U << FLASH_SR_WRPRTERR_Pos) /*!< 0x00000010 */
+#define FLASH_SR_WRPRTERR FLASH_SR_WRPRTERR_Msk /*!< Write Protection Error */
+#define FLASH_SR_EOP_Pos (5U)
+#define FLASH_SR_EOP_Msk (0x1U << FLASH_SR_EOP_Pos) /*!< 0x00000020 */
+#define FLASH_SR_EOP FLASH_SR_EOP_Msk /*!< End of operation */
+
+/******************* Bit definition for FLASH_CR register *******************/
+#define FLASH_CR_PG_Pos (0U)
+#define FLASH_CR_PG_Msk (0x1U << FLASH_CR_PG_Pos) /*!< 0x00000001 */
+#define FLASH_CR_PG FLASH_CR_PG_Msk /*!< Programming */
+#define FLASH_CR_PER_Pos (1U)
+#define FLASH_CR_PER_Msk (0x1U << FLASH_CR_PER_Pos) /*!< 0x00000002 */
+#define FLASH_CR_PER FLASH_CR_PER_Msk /*!< Page Erase */
+#define FLASH_CR_MER_Pos (2U)
+#define FLASH_CR_MER_Msk (0x1U << FLASH_CR_MER_Pos) /*!< 0x00000004 */
+#define FLASH_CR_MER FLASH_CR_MER_Msk /*!< Mass Erase */
+#define FLASH_CR_OPTPG_Pos (4U)
+#define FLASH_CR_OPTPG_Msk (0x1U << FLASH_CR_OPTPG_Pos) /*!< 0x00000010 */
+#define FLASH_CR_OPTPG FLASH_CR_OPTPG_Msk /*!< Option Byte Programming */
+#define FLASH_CR_OPTER_Pos (5U)
+#define FLASH_CR_OPTER_Msk (0x1U << FLASH_CR_OPTER_Pos) /*!< 0x00000020 */
+#define FLASH_CR_OPTER FLASH_CR_OPTER_Msk /*!< Option Byte Erase */
+#define FLASH_CR_STRT_Pos (6U)
+#define FLASH_CR_STRT_Msk (0x1U << FLASH_CR_STRT_Pos) /*!< 0x00000040 */
+#define FLASH_CR_STRT FLASH_CR_STRT_Msk /*!< Start */
+#define FLASH_CR_LOCK_Pos (7U)
+#define FLASH_CR_LOCK_Msk (0x1U << FLASH_CR_LOCK_Pos) /*!< 0x00000080 */
+#define FLASH_CR_LOCK FLASH_CR_LOCK_Msk /*!< Lock */
+#define FLASH_CR_OPTWRE_Pos (9U)
+#define FLASH_CR_OPTWRE_Msk (0x1U << FLASH_CR_OPTWRE_Pos) /*!< 0x00000200 */
+#define FLASH_CR_OPTWRE FLASH_CR_OPTWRE_Msk /*!< Option Bytes Write Enable */
+#define FLASH_CR_ERRIE_Pos (10U)
+#define FLASH_CR_ERRIE_Msk (0x1U << FLASH_CR_ERRIE_Pos) /*!< 0x00000400 */
+#define FLASH_CR_ERRIE FLASH_CR_ERRIE_Msk /*!< Error Interrupt Enable */
+#define FLASH_CR_EOPIE_Pos (12U)
+#define FLASH_CR_EOPIE_Msk (0x1U << FLASH_CR_EOPIE_Pos) /*!< 0x00001000 */
+#define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk /*!< End of operation interrupt enable */
+
+/******************* Bit definition for FLASH_AR register *******************/
+#define FLASH_AR_FAR_Pos (0U)
+#define FLASH_AR_FAR_Msk (0xFFFFFFFFU << FLASH_AR_FAR_Pos) /*!< 0xFFFFFFFF */
+#define FLASH_AR_FAR FLASH_AR_FAR_Msk /*!< Flash Address */
+
+/****************** Bit definition for FLASH_OBR register *******************/
+#define FLASH_OBR_OPTERR_Pos (0U)
+#define FLASH_OBR_OPTERR_Msk (0x1U << FLASH_OBR_OPTERR_Pos) /*!< 0x00000001 */
+#define FLASH_OBR_OPTERR FLASH_OBR_OPTERR_Msk /*!< Option Byte Error */
+#define FLASH_OBR_RDPRT_Pos (1U)
+#define FLASH_OBR_RDPRT_Msk (0x1U << FLASH_OBR_RDPRT_Pos) /*!< 0x00000002 */
+#define FLASH_OBR_RDPRT FLASH_OBR_RDPRT_Msk /*!< Read protection */
+
+#define FLASH_OBR_IWDG_SW_Pos (2U)
+#define FLASH_OBR_IWDG_SW_Msk (0x1U << FLASH_OBR_IWDG_SW_Pos) /*!< 0x00000004 */
+#define FLASH_OBR_IWDG_SW FLASH_OBR_IWDG_SW_Msk /*!< IWDG SW */
+#define FLASH_OBR_nRST_STOP_Pos (3U)
+#define FLASH_OBR_nRST_STOP_Msk (0x1U << FLASH_OBR_nRST_STOP_Pos) /*!< 0x00000008 */
+#define FLASH_OBR_nRST_STOP FLASH_OBR_nRST_STOP_Msk /*!< nRST_STOP */
+#define FLASH_OBR_nRST_STDBY_Pos (4U)
+#define FLASH_OBR_nRST_STDBY_Msk (0x1U << FLASH_OBR_nRST_STDBY_Pos) /*!< 0x00000010 */
+#define FLASH_OBR_nRST_STDBY FLASH_OBR_nRST_STDBY_Msk /*!< nRST_STDBY */
+#define FLASH_OBR_BFB2_Pos (5U)
+#define FLASH_OBR_BFB2_Msk (0x1U << FLASH_OBR_BFB2_Pos) /*!< 0x00000020 */
+#define FLASH_OBR_BFB2 FLASH_OBR_BFB2_Msk /*!< BFB2 */
+#define FLASH_OBR_USER_Pos (2U)
+#define FLASH_OBR_USER_Msk (0xFU << FLASH_OBR_USER_Pos) /*!< 0x0000003C */
+#define FLASH_OBR_USER FLASH_OBR_USER_Msk /*!< User Option Bytes */
+#define FLASH_OBR_DATA0_Pos (10U)
+#define FLASH_OBR_DATA0_Msk (0xFFU << FLASH_OBR_DATA0_Pos) /*!< 0x0003FC00 */
+#define FLASH_OBR_DATA0 FLASH_OBR_DATA0_Msk /*!< Data0 */
+#define FLASH_OBR_DATA1_Pos (18U)
+#define FLASH_OBR_DATA1_Msk (0xFFU << FLASH_OBR_DATA1_Pos) /*!< 0x03FC0000 */
+#define FLASH_OBR_DATA1 FLASH_OBR_DATA1_Msk /*!< Data1 */
+
+/****************** Bit definition for FLASH_WRPR register ******************/
+#define FLASH_WRPR_WRP_Pos (0U)
+#define FLASH_WRPR_WRP_Msk (0xFFFFFFFFU << FLASH_WRPR_WRP_Pos) /*!< 0xFFFFFFFF */
+#define FLASH_WRPR_WRP FLASH_WRPR_WRP_Msk /*!< Write Protect */
+
+/***************** Bit definition for FLASH_OPTKEYR2 register ****************/
+#define FLASH_OPTKEYR_OPTKEYR2_Pos (0U)
+#define FLASH_OPTKEYR_OPTKEYR2_Msk (0xFFFFFFFFU << FLASH_OPTKEYR_OPTKEYR2_Pos) /*!< 0xFFFFFFFF */
+#define FLASH_OPTKEYR_OPTKEYR2 FLASH_OPTKEYR_OPTKEYR2_Msk /*!< Option Byte Key */
+
+/****************** Bit definition for FLASH_SR2 register ********************/
+#define FLASH_SR2_BSY_Pos (0U)
+#define FLASH_SR2_BSY_Msk (0x1U << FLASH_SR2_BSY_Pos) /*!< 0x00000001 */
+#define FLASH_SR2_BSY FLASH_SR2_BSY_Msk /*!< Busy */
+#define FLASH_SR2_PGERR_Pos (2U)
+#define FLASH_SR2_PGERR_Msk (0x1U << FLASH_SR2_PGERR_Pos) /*!< 0x00000004 */
+#define FLASH_SR2_PGERR FLASH_SR2_PGERR_Msk /*!< Programming Error */
+#define FLASH_SR2_WRPRTERR_Pos (4U)
+#define FLASH_SR2_WRPRTERR_Msk (0x1U << FLASH_SR2_WRPRTERR_Pos) /*!< 0x00000010 */
+#define FLASH_SR2_WRPRTERR FLASH_SR2_WRPRTERR_Msk /*!< Write Protection Error */
+#define FLASH_SR2_EOP_Pos (5U)
+#define FLASH_SR2_EOP_Msk (0x1U << FLASH_SR2_EOP_Pos) /*!< 0x00000020 */
+#define FLASH_SR2_EOP FLASH_SR2_EOP_Msk /*!< End of operation */
+
+/******************* Bit definition for FLASH_CR2 register *******************/
+#define FLASH_CR2_PG_Pos (0U)
+#define FLASH_CR2_PG_Msk (0x1U << FLASH_CR2_PG_Pos) /*!< 0x00000001 */
+#define FLASH_CR2_PG FLASH_CR2_PG_Msk /*!< Programming */
+#define FLASH_CR2_PER_Pos (1U)
+#define FLASH_CR2_PER_Msk (0x1U << FLASH_CR2_PER_Pos) /*!< 0x00000002 */
+#define FLASH_CR2_PER FLASH_CR2_PER_Msk /*!< Page Erase */
+#define FLASH_CR2_MER_Pos (2U)
+#define FLASH_CR2_MER_Msk (0x1U << FLASH_CR2_MER_Pos) /*!< 0x00000004 */
+#define FLASH_CR2_MER FLASH_CR2_MER_Msk /*!< Mass Erase */
+#define FLASH_CR2_STRT_Pos (6U)
+#define FLASH_CR2_STRT_Msk (0x1U << FLASH_CR2_STRT_Pos) /*!< 0x00000040 */
+#define FLASH_CR2_STRT FLASH_CR2_STRT_Msk /*!< Start */
+#define FLASH_CR2_LOCK_Pos (7U)
+#define FLASH_CR2_LOCK_Msk (0x1U << FLASH_CR2_LOCK_Pos) /*!< 0x00000080 */
+#define FLASH_CR2_LOCK FLASH_CR2_LOCK_Msk /*!< Lock */
+#define FLASH_CR2_ERRIE_Pos (10U)
+#define FLASH_CR2_ERRIE_Msk (0x1U << FLASH_CR2_ERRIE_Pos) /*!< 0x00000400 */
+#define FLASH_CR2_ERRIE FLASH_CR2_ERRIE_Msk /*!< Error Interrupt Enable */
+#define FLASH_CR2_EOPIE_Pos (12U)
+#define FLASH_CR2_EOPIE_Msk (0x1U << FLASH_CR2_EOPIE_Pos) /*!< 0x00001000 */
+#define FLASH_CR2_EOPIE FLASH_CR2_EOPIE_Msk /*!< End of operation interrupt enable */
+
+/******************* Bit definition for FLASH_AR2 register *******************/
+#define FLASH_AR_FAR2_Pos (0U)
+#define FLASH_AR_FAR2_Msk (0xFFFFFFFFU << FLASH_AR_FAR2_Pos) /*!< 0xFFFFFFFF */
+#define FLASH_AR_FAR2 FLASH_AR_FAR2_Msk /*!< Flash Address */
+
+/*----------------------------------------------------------------------------*/
+
+/****************** Bit definition for FLASH_RDP register *******************/
+#define FLASH_RDP_RDP_Pos (0U)
+#define FLASH_RDP_RDP_Msk (0xFFU << FLASH_RDP_RDP_Pos) /*!< 0x000000FF */
+#define FLASH_RDP_RDP FLASH_RDP_RDP_Msk /*!< Read protection option byte */
+#define FLASH_RDP_nRDP_Pos (8U)
+#define FLASH_RDP_nRDP_Msk (0xFFU << FLASH_RDP_nRDP_Pos) /*!< 0x0000FF00 */
+#define FLASH_RDP_nRDP FLASH_RDP_nRDP_Msk /*!< Read protection complemented option byte */
+
+/****************** Bit definition for FLASH_USER register ******************/
+#define FLASH_USER_USER_Pos (16U)
+#define FLASH_USER_USER_Msk (0xFFU << FLASH_USER_USER_Pos) /*!< 0x00FF0000 */
+#define FLASH_USER_USER FLASH_USER_USER_Msk /*!< User option byte */
+#define FLASH_USER_nUSER_Pos (24U)
+#define FLASH_USER_nUSER_Msk (0xFFU << FLASH_USER_nUSER_Pos) /*!< 0xFF000000 */
+#define FLASH_USER_nUSER FLASH_USER_nUSER_Msk /*!< User complemented option byte */
+
+/****************** Bit definition for FLASH_Data0 register *****************/
+#define FLASH_DATA0_DATA0_Pos (0U)
+#define FLASH_DATA0_DATA0_Msk (0xFFU << FLASH_DATA0_DATA0_Pos) /*!< 0x000000FF */
+#define FLASH_DATA0_DATA0 FLASH_DATA0_DATA0_Msk /*!< User data storage option byte */
+#define FLASH_DATA0_nDATA0_Pos (8U)
+#define FLASH_DATA0_nDATA0_Msk (0xFFU << FLASH_DATA0_nDATA0_Pos) /*!< 0x0000FF00 */
+#define FLASH_DATA0_nDATA0 FLASH_DATA0_nDATA0_Msk /*!< User data storage complemented option byte */
+
+/****************** Bit definition for FLASH_Data1 register *****************/
+#define FLASH_DATA1_DATA1_Pos (16U)
+#define FLASH_DATA1_DATA1_Msk (0xFFU << FLASH_DATA1_DATA1_Pos) /*!< 0x00FF0000 */
+#define FLASH_DATA1_DATA1 FLASH_DATA1_DATA1_Msk /*!< User data storage option byte */
+#define FLASH_DATA1_nDATA1_Pos (24U)
+#define FLASH_DATA1_nDATA1_Msk (0xFFU << FLASH_DATA1_nDATA1_Pos) /*!< 0xFF000000 */
+#define FLASH_DATA1_nDATA1 FLASH_DATA1_nDATA1_Msk /*!< User data storage complemented option byte */
+
+/****************** Bit definition for FLASH_WRP0 register ******************/
+#define FLASH_WRP0_WRP0_Pos (0U)
+#define FLASH_WRP0_WRP0_Msk (0xFFU << FLASH_WRP0_WRP0_Pos) /*!< 0x000000FF */
+#define FLASH_WRP0_WRP0 FLASH_WRP0_WRP0_Msk /*!< Flash memory write protection option bytes */
+#define FLASH_WRP0_nWRP0_Pos (8U)
+#define FLASH_WRP0_nWRP0_Msk (0xFFU << FLASH_WRP0_nWRP0_Pos) /*!< 0x0000FF00 */
+#define FLASH_WRP0_nWRP0 FLASH_WRP0_nWRP0_Msk /*!< Flash memory write protection complemented option bytes */
+
+/****************** Bit definition for FLASH_WRP1 register ******************/
+#define FLASH_WRP1_WRP1_Pos (16U)
+#define FLASH_WRP1_WRP1_Msk (0xFFU << FLASH_WRP1_WRP1_Pos) /*!< 0x00FF0000 */
+#define FLASH_WRP1_WRP1 FLASH_WRP1_WRP1_Msk /*!< Flash memory write protection option bytes */
+#define FLASH_WRP1_nWRP1_Pos (24U)
+#define FLASH_WRP1_nWRP1_Msk (0xFFU << FLASH_WRP1_nWRP1_Pos) /*!< 0xFF000000 */
+#define FLASH_WRP1_nWRP1 FLASH_WRP1_nWRP1_Msk /*!< Flash memory write protection complemented option bytes */
+
+/****************** Bit definition for FLASH_WRP2 register ******************/
+#define FLASH_WRP2_WRP2_Pos (0U)
+#define FLASH_WRP2_WRP2_Msk (0xFFU << FLASH_WRP2_WRP2_Pos) /*!< 0x000000FF */
+#define FLASH_WRP2_WRP2 FLASH_WRP2_WRP2_Msk /*!< Flash memory write protection option bytes */
+#define FLASH_WRP2_nWRP2_Pos (8U)
+#define FLASH_WRP2_nWRP2_Msk (0xFFU << FLASH_WRP2_nWRP2_Pos) /*!< 0x0000FF00 */
+#define FLASH_WRP2_nWRP2 FLASH_WRP2_nWRP2_Msk /*!< Flash memory write protection complemented option bytes */
+
+/****************** Bit definition for FLASH_WRP3 register ******************/
+#define FLASH_WRP3_WRP3_Pos (16U)
+#define FLASH_WRP3_WRP3_Msk (0xFFU << FLASH_WRP3_WRP3_Pos) /*!< 0x00FF0000 */
+#define FLASH_WRP3_WRP3 FLASH_WRP3_WRP3_Msk /*!< Flash memory write protection option bytes */
+#define FLASH_WRP3_nWRP3_Pos (24U)
+#define FLASH_WRP3_nWRP3_Msk (0xFFU << FLASH_WRP3_nWRP3_Pos) /*!< 0xFF000000 */
+#define FLASH_WRP3_nWRP3 FLASH_WRP3_nWRP3_Msk /*!< Flash memory write protection complemented option bytes */
+
+
+
+/**
+ * @}
+*/
+
+/**
+ * @}
+*/
+
+/** @addtogroup Exported_macro
+ * @{
+ */
+
+/****************************** ADC Instances *********************************/
+#define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) || \
+ ((INSTANCE) == ADC2) || \
+ ((INSTANCE) == ADC3))
+
+#define IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
+
+#define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC12_COMMON)
+
+#define IS_ADC_DMA_CAPABILITY_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) || \
+ ((INSTANCE) == ADC3))
+
+/****************************** CAN Instances *********************************/
+#define IS_CAN_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CAN1)
+
+/****************************** CRC Instances *********************************/
+#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
+
+/****************************** DAC Instances *********************************/
+#define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC)
+
+/****************************** DMA Instances *********************************/
+#define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \
+ ((INSTANCE) == DMA1_Channel2) || \
+ ((INSTANCE) == DMA1_Channel3) || \
+ ((INSTANCE) == DMA1_Channel4) || \
+ ((INSTANCE) == DMA1_Channel5) || \
+ ((INSTANCE) == DMA1_Channel6) || \
+ ((INSTANCE) == DMA1_Channel7) || \
+ ((INSTANCE) == DMA2_Channel1) || \
+ ((INSTANCE) == DMA2_Channel2) || \
+ ((INSTANCE) == DMA2_Channel3) || \
+ ((INSTANCE) == DMA2_Channel4) || \
+ ((INSTANCE) == DMA2_Channel5))
+
+/******************************* GPIO Instances *******************************/
+#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
+ ((INSTANCE) == GPIOB) || \
+ ((INSTANCE) == GPIOC) || \
+ ((INSTANCE) == GPIOD) || \
+ ((INSTANCE) == GPIOE) || \
+ ((INSTANCE) == GPIOF) || \
+ ((INSTANCE) == GPIOG))
+
+/**************************** GPIO Alternate Function Instances ***************/
+#define IS_GPIO_AF_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
+
+/**************************** GPIO Lock Instances *****************************/
+#define IS_GPIO_LOCK_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
+
+/******************************** I2C Instances *******************************/
+#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
+ ((INSTANCE) == I2C2))
+
+/******************************** I2S Instances *******************************/
+#define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI2) || \
+ ((INSTANCE) == SPI3))
+
+/****************************** IWDG Instances ********************************/
+#define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
+
+/****************************** SDIO Instances *********************************/
+#define IS_SDIO_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SDIO)
+
+/******************************** SPI Instances *******************************/
+#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
+ ((INSTANCE) == SPI2) || \
+ ((INSTANCE) == SPI3))
+
+/****************************** START TIM Instances ***************************/
+/****************************** TIM Instances *********************************/
+#define IS_TIM_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM6) || \
+ ((INSTANCE) == TIM7) || \
+ ((INSTANCE) == TIM9) || \
+ ((INSTANCE) == TIM10) || \
+ ((INSTANCE) == TIM11) || \
+ ((INSTANCE) == TIM12) || \
+ ((INSTANCE) == TIM13) || \
+ ((INSTANCE) == TIM14))
+
+#define IS_TIM_CC1_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM9) || \
+ ((INSTANCE) == TIM10) || \
+ ((INSTANCE) == TIM11) || \
+ ((INSTANCE) == TIM12) || \
+ ((INSTANCE) == TIM13) || \
+ ((INSTANCE) == TIM14))
+
+#define IS_TIM_CC2_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM9) || \
+ ((INSTANCE) == TIM12))
+
+#define IS_TIM_CC3_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5))
+
+#define IS_TIM_CC4_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5))
+
+#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5))
+
+#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5))
+
+#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM9) || \
+ ((INSTANCE) == TIM12))
+
+#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM9) || \
+ ((INSTANCE) == TIM12))
+
+#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5))
+
+#define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5))
+
+#define IS_TIM_XOR_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5))
+
+#define IS_TIM_MASTER_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM6) || \
+ ((INSTANCE) == TIM7) || \
+ ((INSTANCE) == TIM12))
+
+#define IS_TIM_SLAVE_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM12))
+
+#define IS_TIM_DMABURST_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5))
+
+#define IS_TIM_BREAK_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM8))
+
+#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
+ ((((INSTANCE) == TIM1) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM8) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM2) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM3) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM4) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM5) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM9) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2))) \
+ || \
+ (((INSTANCE) == TIM10) && \
+ (((CHANNEL) == TIM_CHANNEL_1))) \
+ || \
+ (((INSTANCE) == TIM11) && \
+ (((CHANNEL) == TIM_CHANNEL_1))) \
+ || \
+ (((INSTANCE) == TIM12) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2))) \
+ || \
+ (((INSTANCE) == TIM13) && \
+ (((CHANNEL) == TIM_CHANNEL_1))) \
+ || \
+ (((INSTANCE) == TIM14) && \
+ (((CHANNEL) == TIM_CHANNEL_1))))
+
+#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
+ ((((INSTANCE) == TIM1) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3))) \
+ || \
+ (((INSTANCE) == TIM8) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3))))
+
+#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5))
+
+#define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM8))
+
+#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM9) || \
+ ((INSTANCE) == TIM10) || \
+ ((INSTANCE) == TIM11) || \
+ ((INSTANCE) == TIM12) || \
+ ((INSTANCE) == TIM13) || \
+ ((INSTANCE) == TIM14))
+
+#define IS_TIM_DMA_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM6) || \
+ ((INSTANCE) == TIM7))
+
+#define IS_TIM_DMA_CC_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5))
+
+#define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM8))
+
+/****************************** END TIM Instances *****************************/
+
+
+/******************** USART Instances : Synchronous mode **********************/
+#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3))
+
+/******************** UART Instances : Asynchronous mode **********************/
+#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3) || \
+ ((INSTANCE) == UART4) || \
+ ((INSTANCE) == UART5))
+
+/******************** UART Instances : Half-Duplex mode **********************/
+#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3) || \
+ ((INSTANCE) == UART4) || \
+ ((INSTANCE) == UART5))
+
+/******************** UART Instances : LIN mode **********************/
+#define IS_UART_LIN_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3) || \
+ ((INSTANCE) == UART4) || \
+ ((INSTANCE) == UART5))
+
+/****************** UART Instances : Hardware Flow control ********************/
+#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3))
+
+/********************* UART Instances : Smard card mode ***********************/
+#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3))
+
+/*********************** UART Instances : IRDA mode ***************************/
+#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3) || \
+ ((INSTANCE) == UART4) || \
+ ((INSTANCE) == UART5))
+
+/***************** UART Instances : Multi-Processor mode **********************/
+#define IS_UART_MULTIPROCESSOR_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3) || \
+ ((INSTANCE) == UART4) || \
+ ((INSTANCE) == UART5))
+
+/***************** UART Instances : DMA mode available **********************/
+#define IS_UART_DMA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3) || \
+ ((INSTANCE) == UART4))
+
+/****************************** RTC Instances *********************************/
+#define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
+
+/**************************** WWDG Instances *****************************/
+#define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
+
+/****************************** USB Instances ********************************/
+#define IS_USB_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB)
+
+
+
+
+/**
+ * @}
+*/
+/******************************************************************************/
+/* For a painless codes migration between the STM32F1xx device product */
+/* lines, the aliases defined below are put in place to overcome the */
+/* differences in the interrupt handlers and IRQn definitions. */
+/* No need to update developed interrupt code when moving across */
+/* product lines within the same STM32F1 Family */
+/******************************************************************************/
+
+/* Aliases for __IRQn */
+#define ADC1_IRQn ADC1_2_IRQn
+#define DMA2_Channel4_IRQn DMA2_Channel4_5_IRQn
+#define TIM1_BRK_TIM15_IRQn TIM1_BRK_TIM9_IRQn
+#define TIM1_BRK_IRQn TIM1_BRK_TIM9_IRQn
+#define TIM9_IRQn TIM1_BRK_TIM9_IRQn
+#define TIM1_TRG_COM_TIM17_IRQn TIM1_TRG_COM_TIM11_IRQn
+#define TIM1_TRG_COM_IRQn TIM1_TRG_COM_TIM11_IRQn
+#define TIM11_IRQn TIM1_TRG_COM_TIM11_IRQn
+#define TIM10_IRQn TIM1_UP_TIM10_IRQn
+#define TIM1_UP_TIM16_IRQn TIM1_UP_TIM10_IRQn
+#define TIM1_UP_IRQn TIM1_UP_TIM10_IRQn
+#define TIM6_DAC_IRQn TIM6_IRQn
+#define TIM12_IRQn TIM8_BRK_TIM12_IRQn
+#define TIM8_BRK_IRQn TIM8_BRK_TIM12_IRQn
+#define TIM14_IRQn TIM8_TRG_COM_TIM14_IRQn
+#define TIM8_TRG_COM_IRQn TIM8_TRG_COM_TIM14_IRQn
+#define TIM8_UP_IRQn TIM8_UP_TIM13_IRQn
+#define TIM13_IRQn TIM8_UP_TIM13_IRQn
+#define CEC_IRQn USBWakeUp_IRQn
+#define OTG_FS_WKUP_IRQn USBWakeUp_IRQn
+#define CAN1_TX_IRQn USB_HP_CAN1_TX_IRQn
+#define USB_HP_IRQn USB_HP_CAN1_TX_IRQn
+#define USB_LP_IRQn USB_LP_CAN1_RX0_IRQn
+#define CAN1_RX0_IRQn USB_LP_CAN1_RX0_IRQn
+
+
+/* Aliases for __IRQHandler */
+#define ADC1_IRQHandler ADC1_2_IRQHandler
+#define DMA2_Channel4_IRQHandler DMA2_Channel4_5_IRQHandler
+#define TIM1_BRK_TIM15_IRQHandler TIM1_BRK_TIM9_IRQHandler
+#define TIM1_BRK_IRQHandler TIM1_BRK_TIM9_IRQHandler
+#define TIM9_IRQHandler TIM1_BRK_TIM9_IRQHandler
+#define TIM1_TRG_COM_TIM17_IRQHandler TIM1_TRG_COM_TIM11_IRQHandler
+#define TIM1_TRG_COM_IRQHandler TIM1_TRG_COM_TIM11_IRQHandler
+#define TIM11_IRQHandler TIM1_TRG_COM_TIM11_IRQHandler
+#define TIM10_IRQHandler TIM1_UP_TIM10_IRQHandler
+#define TIM1_UP_TIM16_IRQHandler TIM1_UP_TIM10_IRQHandler
+#define TIM1_UP_IRQHandler TIM1_UP_TIM10_IRQHandler
+#define TIM6_DAC_IRQHandler TIM6_IRQHandler
+#define TIM12_IRQHandler TIM8_BRK_TIM12_IRQHandler
+#define TIM8_BRK_IRQHandler TIM8_BRK_TIM12_IRQHandler
+#define TIM14_IRQHandler TIM8_TRG_COM_TIM14_IRQHandler
+#define TIM8_TRG_COM_IRQHandler TIM8_TRG_COM_TIM14_IRQHandler
+#define TIM8_UP_IRQHandler TIM8_UP_TIM13_IRQHandler
+#define TIM13_IRQHandler TIM8_UP_TIM13_IRQHandler
+#define CEC_IRQHandler USBWakeUp_IRQHandler
+#define OTG_FS_WKUP_IRQHandler USBWakeUp_IRQHandler
+#define CAN1_TX_IRQHandler USB_HP_CAN1_TX_IRQHandler
+#define USB_HP_IRQHandler USB_HP_CAN1_TX_IRQHandler
+#define USB_LP_IRQHandler USB_LP_CAN1_RX0_IRQHandler
+#define CAN1_RX0_IRQHandler USB_LP_CAN1_RX0_IRQHandler
+
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+
+#ifdef __cplusplus
+ }
+#endif /* __cplusplus */
+
+#endif /* __STM32F103xG_H */
+
+
+
+ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Device/ST/STM32F1xx/Include/stm32f105xc.h b/Device/ST/STM32F1xx/Include/stm32f105xc.h
new file mode 100644
index 0000000..137ebfa
--- /dev/null
+++ b/Device/ST/STM32F1xx/Include/stm32f105xc.h
@@ -0,0 +1,15138 @@
+/**
+ ******************************************************************************
+ * @file stm32f105xc.h
+ * @author MCD Application Team
+ * @version V4.1.0
+ * @date 29-April-2016
+ * @brief CMSIS Cortex-M3 Device Peripheral Access Layer Header File.
+ * This file contains all the peripheral register's definitions, bits
+ * definitions and memory mapping for STM32F1xx devices.
+ *
+ * This file contains:
+ * - Data structures and the address mapping for all peripherals
+ * - Peripheral's registers declarations and bits definition
+ * - Macros to access peripheral’s registers hardware
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+
+/** @addtogroup CMSIS
+ * @{
+ */
+
+/** @addtogroup stm32f105xc
+ * @{
+ */
+
+#ifndef __STM32F105xC_H
+#define __STM32F105xC_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/** @addtogroup Configuration_section_for_CMSIS
+ * @{
+ */
+/**
+ * @brief Configuration of the Cortex-M3 Processor and Core Peripherals
+ */
+ #define __MPU_PRESENT 0 /*!< Other STM32 devices does not provide an MPU */
+#define __CM3_REV 0x0200 /*!< Core Revision r2p0 */
+#define __NVIC_PRIO_BITS 4 /*!< STM32 uses 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
+
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_interrupt_number_definition
+ * @{
+ */
+
+/**
+ * @brief STM32F10x Interrupt Number Definition, according to the selected device
+ * in @ref Library_configuration_section
+ */
+
+ /*!< Interrupt Number Definition */
+typedef enum
+{
+/****** Cortex-M3 Processor Exceptions Numbers ***************************************************/
+ NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
+ HardFault_IRQn = -13, /*!< 3 Cortex-M3 Hard Fault Interrupt */
+ MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */
+ BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */
+ UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */
+ SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */
+ DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */
+ PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */
+ SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */
+
+/****** STM32 specific Interrupt Numbers *********************************************************/
+ WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
+ PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */
+ TAMPER_IRQn = 2, /*!< Tamper Interrupt */
+ RTC_IRQn = 3, /*!< RTC global Interrupt */
+ FLASH_IRQn = 4, /*!< FLASH global Interrupt */
+ RCC_IRQn = 5, /*!< RCC global Interrupt */
+ EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */
+ EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */
+ EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */
+ EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */
+ EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */
+ DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 global Interrupt */
+ DMA1_Channel2_IRQn = 12, /*!< DMA1 Channel 2 global Interrupt */
+ DMA1_Channel3_IRQn = 13, /*!< DMA1 Channel 3 global Interrupt */
+ DMA1_Channel4_IRQn = 14, /*!< DMA1 Channel 4 global Interrupt */
+ DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 global Interrupt */
+ DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 global Interrupt */
+ DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 global Interrupt */
+ ADC1_2_IRQn = 18, /*!< ADC1 and ADC2 global Interrupt */
+ CAN1_TX_IRQn = 19, /*!< CAN1 TX Interrupts */
+ CAN1_RX0_IRQn = 20, /*!< CAN1 RX0 Interrupts */
+ CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */
+ CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */
+ EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
+ TIM1_BRK_IRQn = 24, /*!< TIM1 Break Interrupt */
+ TIM1_UP_IRQn = 25, /*!< TIM1 Update Interrupt */
+ TIM1_TRG_COM_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt */
+ TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
+ TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
+ TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
+ TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
+ I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
+ I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
+ I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
+ I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
+ SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
+ SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
+ USART1_IRQn = 37, /*!< USART1 global Interrupt */
+ USART2_IRQn = 38, /*!< USART2 global Interrupt */
+ USART3_IRQn = 39, /*!< USART3 global Interrupt */
+ EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
+ RTC_Alarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */
+ OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS WakeUp from suspend through EXTI Line Interrupt */
+ TIM5_IRQn = 50, /*!< TIM5 global Interrupt */
+ SPI3_IRQn = 51, /*!< SPI3 global Interrupt */
+ UART4_IRQn = 52, /*!< UART4 global Interrupt */
+ UART5_IRQn = 53, /*!< UART5 global Interrupt */
+ TIM6_IRQn = 54, /*!< TIM6 global Interrupt */
+ TIM7_IRQn = 55, /*!< TIM7 global Interrupt */
+ DMA2_Channel1_IRQn = 56, /*!< DMA2 Channel 1 global Interrupt */
+ DMA2_Channel2_IRQn = 57, /*!< DMA2 Channel 2 global Interrupt */
+ DMA2_Channel3_IRQn = 58, /*!< DMA2 Channel 3 global Interrupt */
+ DMA2_Channel4_IRQn = 59, /*!< DMA2 Channel 4 global Interrupt */
+ DMA2_Channel5_IRQn = 60, /*!< DMA2 Channel 5 global Interrupt */
+ CAN2_TX_IRQn = 63, /*!< CAN2 TX Interrupt */
+ CAN2_RX0_IRQn = 64, /*!< CAN2 RX0 Interrupt */
+ CAN2_RX1_IRQn = 65, /*!< CAN2 RX1 Interrupt */
+ CAN2_SCE_IRQn = 66, /*!< CAN2 SCE Interrupt */
+ OTG_FS_IRQn = 67 /*!< USB OTG FS global Interrupt */
+} IRQn_Type;
+
+
+/**
+ * @}
+ */
+
+#include "core_cm3.h"
+#include "system_stm32f1xx.h"
+#include <stdint.h>
+
+/** @addtogroup Peripheral_registers_structures
+ * @{
+ */
+
+/**
+ * @brief Analog to Digital Converter
+ */
+
+typedef struct
+{
+ __IO uint32_t SR;
+ __IO uint32_t CR1;
+ __IO uint32_t CR2;
+ __IO uint32_t SMPR1;
+ __IO uint32_t SMPR2;
+ __IO uint32_t JOFR1;
+ __IO uint32_t JOFR2;
+ __IO uint32_t JOFR3;
+ __IO uint32_t JOFR4;
+ __IO uint32_t HTR;
+ __IO uint32_t LTR;
+ __IO uint32_t SQR1;
+ __IO uint32_t SQR2;
+ __IO uint32_t SQR3;
+ __IO uint32_t JSQR;
+ __IO uint32_t JDR1;
+ __IO uint32_t JDR2;
+ __IO uint32_t JDR3;
+ __IO uint32_t JDR4;
+ __IO uint32_t DR;
+} ADC_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t SR; /*!< ADC status register, used for ADC multimode (bits common to several ADC instances). Address offset: ADC1 base address */
+ __IO uint32_t CR1; /*!< ADC control register 1, used for ADC multimode (bits common to several ADC instances). Address offset: ADC1 base address + 0x04 */
+ __IO uint32_t CR2; /*!< ADC control register 2, used for ADC multimode (bits common to several ADC instances). Address offset: ADC1 base address + 0x08 */
+ uint32_t RESERVED[16];
+ __IO uint32_t DR; /*!< ADC data register, used for ADC multimode (bits common to several ADC instances). Address offset: ADC1 base address + 0x4C */
+} ADC_Common_TypeDef;
+
+/**
+ * @brief Backup Registers
+ */
+
+typedef struct
+{
+ uint32_t RESERVED0;
+ __IO uint32_t DR1;
+ __IO uint32_t DR2;
+ __IO uint32_t DR3;
+ __IO uint32_t DR4;
+ __IO uint32_t DR5;
+ __IO uint32_t DR6;
+ __IO uint32_t DR7;
+ __IO uint32_t DR8;
+ __IO uint32_t DR9;
+ __IO uint32_t DR10;
+ __IO uint32_t RTCCR;
+ __IO uint32_t CR;
+ __IO uint32_t CSR;
+ uint32_t RESERVED13[2];
+ __IO uint32_t DR11;
+ __IO uint32_t DR12;
+ __IO uint32_t DR13;
+ __IO uint32_t DR14;
+ __IO uint32_t DR15;
+ __IO uint32_t DR16;
+ __IO uint32_t DR17;
+ __IO uint32_t DR18;
+ __IO uint32_t DR19;
+ __IO uint32_t DR20;
+ __IO uint32_t DR21;
+ __IO uint32_t DR22;
+ __IO uint32_t DR23;
+ __IO uint32_t DR24;
+ __IO uint32_t DR25;
+ __IO uint32_t DR26;
+ __IO uint32_t DR27;
+ __IO uint32_t DR28;
+ __IO uint32_t DR29;
+ __IO uint32_t DR30;
+ __IO uint32_t DR31;
+ __IO uint32_t DR32;
+ __IO uint32_t DR33;
+ __IO uint32_t DR34;
+ __IO uint32_t DR35;
+ __IO uint32_t DR36;
+ __IO uint32_t DR37;
+ __IO uint32_t DR38;
+ __IO uint32_t DR39;
+ __IO uint32_t DR40;
+ __IO uint32_t DR41;
+ __IO uint32_t DR42;
+} BKP_TypeDef;
+
+/**
+ * @brief Controller Area Network TxMailBox
+ */
+
+typedef struct
+{
+ __IO uint32_t TIR;
+ __IO uint32_t TDTR;
+ __IO uint32_t TDLR;
+ __IO uint32_t TDHR;
+} CAN_TxMailBox_TypeDef;
+
+/**
+ * @brief Controller Area Network FIFOMailBox
+ */
+
+typedef struct
+{
+ __IO uint32_t RIR;
+ __IO uint32_t RDTR;
+ __IO uint32_t RDLR;
+ __IO uint32_t RDHR;
+} CAN_FIFOMailBox_TypeDef;
+
+/**
+ * @brief Controller Area Network FilterRegister
+ */
+
+typedef struct
+{
+ __IO uint32_t FR1;
+ __IO uint32_t FR2;
+} CAN_FilterRegister_TypeDef;
+
+/**
+ * @brief Controller Area Network
+ */
+
+typedef struct
+{
+ __IO uint32_t MCR;
+ __IO uint32_t MSR;
+ __IO uint32_t TSR;
+ __IO uint32_t RF0R;
+ __IO uint32_t RF1R;
+ __IO uint32_t IER;
+ __IO uint32_t ESR;
+ __IO uint32_t BTR;
+ uint32_t RESERVED0[88];
+ CAN_TxMailBox_TypeDef sTxMailBox[3];
+ CAN_FIFOMailBox_TypeDef sFIFOMailBox[2];
+ uint32_t RESERVED1[12];
+ __IO uint32_t FMR;
+ __IO uint32_t FM1R;
+ uint32_t RESERVED2;
+ __IO uint32_t FS1R;
+ uint32_t RESERVED3;
+ __IO uint32_t FFA1R;
+ uint32_t RESERVED4;
+ __IO uint32_t FA1R;
+ uint32_t RESERVED5[8];
+ CAN_FilterRegister_TypeDef sFilterRegister[28];
+} CAN_TypeDef;
+
+/**
+ * @brief CRC calculation unit
+ */
+
+typedef struct
+{
+ __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
+ __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
+ uint8_t RESERVED0; /*!< Reserved, Address offset: 0x05 */
+ uint16_t RESERVED1; /*!< Reserved, Address offset: 0x06 */
+ __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
+} CRC_TypeDef;
+
+/**
+ * @brief Digital to Analog Converter
+ */
+
+typedef struct
+{
+ __IO uint32_t CR;
+ __IO uint32_t SWTRIGR;
+ __IO uint32_t DHR12R1;
+ __IO uint32_t DHR12L1;
+ __IO uint32_t DHR8R1;
+ __IO uint32_t DHR12R2;
+ __IO uint32_t DHR12L2;
+ __IO uint32_t DHR8R2;
+ __IO uint32_t DHR12RD;
+ __IO uint32_t DHR12LD;
+ __IO uint32_t DHR8RD;
+ __IO uint32_t DOR1;
+ __IO uint32_t DOR2;
+} DAC_TypeDef;
+
+/**
+ * @brief Debug MCU
+ */
+
+typedef struct
+{
+ __IO uint32_t IDCODE;
+ __IO uint32_t CR;
+}DBGMCU_TypeDef;
+
+/**
+ * @brief DMA Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t CCR;
+ __IO uint32_t CNDTR;
+ __IO uint32_t CPAR;
+ __IO uint32_t CMAR;
+} DMA_Channel_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t ISR;
+ __IO uint32_t IFCR;
+} DMA_TypeDef;
+
+
+
+/**
+ * @brief External Interrupt/Event Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t IMR;
+ __IO uint32_t EMR;
+ __IO uint32_t RTSR;
+ __IO uint32_t FTSR;
+ __IO uint32_t SWIER;
+ __IO uint32_t PR;
+} EXTI_TypeDef;
+
+/**
+ * @brief FLASH Registers
+ */
+
+typedef struct
+{
+ __IO uint32_t ACR;
+ __IO uint32_t KEYR;
+ __IO uint32_t OPTKEYR;
+ __IO uint32_t SR;
+ __IO uint32_t CR;
+ __IO uint32_t AR;
+ __IO uint32_t RESERVED;
+ __IO uint32_t OBR;
+ __IO uint32_t WRPR;
+} FLASH_TypeDef;
+
+/**
+ * @brief Option Bytes Registers
+ */
+
+typedef struct
+{
+ __IO uint16_t RDP;
+ __IO uint16_t USER;
+ __IO uint16_t Data0;
+ __IO uint16_t Data1;
+ __IO uint16_t WRP0;
+ __IO uint16_t WRP1;
+ __IO uint16_t WRP2;
+ __IO uint16_t WRP3;
+} OB_TypeDef;
+
+/**
+ * @brief General Purpose I/O
+ */
+
+typedef struct
+{
+ __IO uint32_t CRL;
+ __IO uint32_t CRH;
+ __IO uint32_t IDR;
+ __IO uint32_t ODR;
+ __IO uint32_t BSRR;
+ __IO uint32_t BRR;
+ __IO uint32_t LCKR;
+} GPIO_TypeDef;
+
+/**
+ * @brief Alternate Function I/O
+ */
+
+typedef struct
+{
+ __IO uint32_t EVCR;
+ __IO uint32_t MAPR;
+ __IO uint32_t EXTICR[4];
+ uint32_t RESERVED0;
+ __IO uint32_t MAPR2;
+} AFIO_TypeDef;
+/**
+ * @brief Inter Integrated Circuit Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t CR1;
+ __IO uint32_t CR2;
+ __IO uint32_t OAR1;
+ __IO uint32_t OAR2;
+ __IO uint32_t DR;
+ __IO uint32_t SR1;
+ __IO uint32_t SR2;
+ __IO uint32_t CCR;
+ __IO uint32_t TRISE;
+} I2C_TypeDef;
+
+/**
+ * @brief Independent WATCHDOG
+ */
+
+typedef struct
+{
+ __IO uint32_t KR; /*!< Key register, Address offset: 0x00 */
+ __IO uint32_t PR; /*!< Prescaler register, Address offset: 0x04 */
+ __IO uint32_t RLR; /*!< Reload register, Address offset: 0x08 */
+ __IO uint32_t SR; /*!< Status register, Address offset: 0x0C */
+} IWDG_TypeDef;
+
+/**
+ * @brief Power Control
+ */
+
+typedef struct
+{
+ __IO uint32_t CR;
+ __IO uint32_t CSR;
+} PWR_TypeDef;
+
+/**
+ * @brief Reset and Clock Control
+ */
+
+typedef struct
+{
+ __IO uint32_t CR;
+ __IO uint32_t CFGR;
+ __IO uint32_t CIR;
+ __IO uint32_t APB2RSTR;
+ __IO uint32_t APB1RSTR;
+ __IO uint32_t AHBENR;
+ __IO uint32_t APB2ENR;
+ __IO uint32_t APB1ENR;
+ __IO uint32_t BDCR;
+ __IO uint32_t CSR;
+
+ __IO uint32_t AHBRSTR;
+ __IO uint32_t CFGR2;
+
+} RCC_TypeDef;
+
+/**
+ * @brief Real-Time Clock
+ */
+
+typedef struct
+{
+ __IO uint32_t CRH;
+ __IO uint32_t CRL;
+ __IO uint32_t PRLH;
+ __IO uint32_t PRLL;
+ __IO uint32_t DIVH;
+ __IO uint32_t DIVL;
+ __IO uint32_t CNTH;
+ __IO uint32_t CNTL;
+ __IO uint32_t ALRH;
+ __IO uint32_t ALRL;
+} RTC_TypeDef;
+
+/**
+ * @brief SD host Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t POWER;
+ __IO uint32_t CLKCR;
+ __IO uint32_t ARG;
+ __IO uint32_t CMD;
+ __I uint32_t RESPCMD;
+ __I uint32_t RESP1;
+ __I uint32_t RESP2;
+ __I uint32_t RESP3;
+ __I uint32_t RESP4;
+ __IO uint32_t DTIMER;
+ __IO uint32_t DLEN;
+ __IO uint32_t DCTRL;
+ __I uint32_t DCOUNT;
+ __I uint32_t STA;
+ __IO uint32_t ICR;
+ __IO uint32_t MASK;
+ uint32_t RESERVED0[2];
+ __I uint32_t FIFOCNT;
+ uint32_t RESERVED1[13];
+ __IO uint32_t FIFO;
+} SDIO_TypeDef;
+
+/**
+ * @brief Serial Peripheral Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t CR1;
+ __IO uint32_t CR2;
+ __IO uint32_t SR;
+ __IO uint32_t DR;
+ __IO uint32_t CRCPR;
+ __IO uint32_t RXCRCR;
+ __IO uint32_t TXCRCR;
+ __IO uint32_t I2SCFGR;
+ __IO uint32_t I2SPR;
+} SPI_TypeDef;
+
+/**
+ * @brief TIM Timers
+ */
+typedef struct
+{
+ __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
+ __IO uint32_t SMCR; /*!< TIM slave Mode Control register, Address offset: 0x08 */
+ __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
+ __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
+ __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
+ __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
+ __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
+ __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
+ __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
+ __IO uint32_t PSC; /*!< TIM prescaler register, Address offset: 0x28 */
+ __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
+ __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */
+ __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
+ __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
+ __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
+ __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
+ __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
+ __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
+ __IO uint32_t DMAR; /*!< TIM DMA address for full transfer register, Address offset: 0x4C */
+ __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */
+}TIM_TypeDef;
+
+
+/**
+ * @brief Universal Synchronous Asynchronous Receiver Transmitter
+ */
+
+typedef struct
+{
+ __IO uint32_t SR; /*!< USART Status register, Address offset: 0x00 */
+ __IO uint32_t DR; /*!< USART Data register, Address offset: 0x04 */
+ __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x08 */
+ __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x0C */
+ __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x10 */
+ __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x14 */
+ __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x18 */
+} USART_TypeDef;
+
+
+/**
+ * @brief __USB_OTG_Core_register
+ */
+
+typedef struct
+{
+ __IO uint32_t GOTGCTL; /*!< USB_OTG Control and Status Register Address offset: 000h */
+ __IO uint32_t GOTGINT; /*!< USB_OTG Interrupt Register Address offset: 004h */
+ __IO uint32_t GAHBCFG; /*!< Core AHB Configuration Register Address offset: 008h */
+ __IO uint32_t GUSBCFG; /*!< Core USB Configuration Register Address offset: 00Ch */
+ __IO uint32_t GRSTCTL; /*!< Core Reset Register Address offset: 010h */
+ __IO uint32_t GINTSTS; /*!< Core Interrupt Register Address offset: 014h */
+ __IO uint32_t GINTMSK; /*!< Core Interrupt Mask Register Address offset: 018h */
+ __IO uint32_t GRXSTSR; /*!< Receive Sts Q Read Register Address offset: 01Ch */
+ __IO uint32_t GRXSTSP; /*!< Receive Sts Q Read & POP Register Address offset: 020h */
+ __IO uint32_t GRXFSIZ; /*!< Receive FIFO Size Register Address offset: 024h */
+ __IO uint32_t DIEPTXF0_HNPTXFSIZ; /*!< EP0 / Non Periodic Tx FIFO Size Register Address offset: 028h */
+ __IO uint32_t HNPTXSTS; /*!< Non Periodic Tx FIFO/Queue Sts reg Address offset: 02Ch */
+ uint32_t Reserved30[2]; /*!< Reserved 030h*/
+ __IO uint32_t GCCFG; /*!< General Purpose IO Register Address offset: 038h */
+ __IO uint32_t CID; /*!< User ID Register Address offset: 03Ch */
+ uint32_t Reserved40[48]; /*!< Reserved 040h-0FFh */
+ __IO uint32_t HPTXFSIZ; /*!< Host Periodic Tx FIFO Size Reg Address offset: 100h */
+ __IO uint32_t DIEPTXF[0x0F]; /*!< dev Periodic Transmit FIFO Address offset: 0x104 */
+} USB_OTG_GlobalTypeDef;
+
+/**
+ * @brief __device_Registers
+ */
+
+typedef struct
+{
+ __IO uint32_t DCFG; /*!< dev Configuration Register Address offset: 800h*/
+ __IO uint32_t DCTL; /*!< dev Control Register Address offset: 804h*/
+ __IO uint32_t DSTS; /*!< dev Status Register (RO) Address offset: 808h*/
+ uint32_t Reserved0C; /*!< Reserved 80Ch*/
+ __IO uint32_t DIEPMSK; /*!< dev IN Endpoint Mask Address offset: 810h*/
+ __IO uint32_t DOEPMSK; /*!< dev OUT Endpoint Mask Address offset: 814h*/
+ __IO uint32_t DAINT; /*!< dev All Endpoints Itr Reg Address offset: 818h*/
+ __IO uint32_t DAINTMSK; /*!< dev All Endpoints Itr Mask Address offset: 81Ch*/
+ uint32_t Reserved20; /*!< Reserved 820h*/
+ uint32_t Reserved9; /*!< Reserved 824h*/
+ __IO uint32_t DVBUSDIS; /*!< dev VBUS discharge Register Address offset: 828h*/
+ __IO uint32_t DVBUSPULSE; /*!< dev VBUS Pulse Register Address offset: 82Ch*/
+ __IO uint32_t DTHRCTL; /*!< dev thr Address offset: 830h*/
+ __IO uint32_t DIEPEMPMSK; /*!< dev empty msk Address offset: 834h*/
+ __IO uint32_t DEACHINT; /*!< dedicated EP interrupt Address offset: 838h*/
+ __IO uint32_t DEACHMSK; /*!< dedicated EP msk Address offset: 83Ch*/
+ uint32_t Reserved40; /*!< dedicated EP mask Address offset: 840h*/
+ __IO uint32_t DINEP1MSK; /*!< dedicated EP mask Address offset: 844h*/
+ uint32_t Reserved44[15]; /*!< Reserved 844-87Ch*/
+ __IO uint32_t DOUTEP1MSK; /*!< dedicated EP msk Address offset: 884h*/
+} USB_OTG_DeviceTypeDef;
+
+/**
+ * @brief __IN_Endpoint-Specific_Register
+ */
+
+typedef struct
+{
+ __IO uint32_t DIEPCTL; /*!< dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h*/
+ uint32_t Reserved04; /*!< Reserved 900h + (ep_num * 20h) + 04h*/
+ __IO uint32_t DIEPINT; /*!< dev IN Endpoint Itr Reg 900h + (ep_num * 20h) + 08h*/
+ uint32_t Reserved0C; /*!< Reserved 900h + (ep_num * 20h) + 0Ch*/
+ __IO uint32_t DIEPTSIZ; /*!< IN Endpoint Txfer Size 900h + (ep_num * 20h) + 10h*/
+ __IO uint32_t DIEPDMA; /*!< IN Endpoint DMA Address Reg 900h + (ep_num * 20h) + 14h*/
+ __IO uint32_t DTXFSTS; /*!< IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h*/
+ uint32_t Reserved18; /*!< Reserved 900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch*/
+} USB_OTG_INEndpointTypeDef;
+
+/**
+ * @brief __OUT_Endpoint-Specific_Registers
+ */
+
+typedef struct
+{
+ __IO uint32_t DOEPCTL; /*!< dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h*/
+ uint32_t Reserved04; /*!< Reserved B00h + (ep_num * 20h) + 04h*/
+ __IO uint32_t DOEPINT; /*!< dev OUT Endpoint Itr Reg B00h + (ep_num * 20h) + 08h*/
+ uint32_t Reserved0C; /*!< Reserved B00h + (ep_num * 20h) + 0Ch*/
+ __IO uint32_t DOEPTSIZ; /*!< dev OUT Endpoint Txfer Size B00h + (ep_num * 20h) + 10h*/
+ __IO uint32_t DOEPDMA; /*!< dev OUT Endpoint DMA Address B00h + (ep_num * 20h) + 14h*/
+ uint32_t Reserved18[2]; /*!< Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch*/
+} USB_OTG_OUTEndpointTypeDef;
+
+/**
+ * @brief __Host_Mode_Register_Structures
+ */
+
+typedef struct
+{
+ __IO uint32_t HCFG; /*!< Host Configuration Register 400h*/
+ __IO uint32_t HFIR; /*!< Host Frame Interval Register 404h*/
+ __IO uint32_t HFNUM; /*!< Host Frame Nbr/Frame Remaining 408h*/
+ uint32_t Reserved40C; /*!< Reserved 40Ch*/
+ __IO uint32_t HPTXSTS; /*!< Host Periodic Tx FIFO/ Queue Status 410h*/
+ __IO uint32_t HAINT; /*!< Host All Channels Interrupt Register 414h*/
+ __IO uint32_t HAINTMSK; /*!< Host All Channels Interrupt Mask 418h*/
+} USB_OTG_HostTypeDef;
+
+/**
+ * @brief __Host_Channel_Specific_Registers
+ */
+
+typedef struct
+{
+ __IO uint32_t HCCHAR;
+ __IO uint32_t HCSPLT;
+ __IO uint32_t HCINT;
+ __IO uint32_t HCINTMSK;
+ __IO uint32_t HCTSIZ;
+ __IO uint32_t HCDMA;
+ uint32_t Reserved[2];
+} USB_OTG_HostChannelTypeDef;
+
+/**
+ * @brief Window WATCHDOG
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
+ __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
+ __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
+} WWDG_TypeDef;
+
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_memory_map
+ * @{
+ */
+
+
+#define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH base address in the alias region */
+#define FLASH_BANK1_END ((uint32_t)0x0803FFFF) /*!< FLASH END address of bank1 */
+#define SRAM_BASE ((uint32_t)0x20000000) /*!< SRAM base address in the alias region */
+#define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */
+
+#define SRAM_BB_BASE ((uint32_t)0x22000000) /*!< SRAM base address in the bit-band region */
+#define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */
+
+
+/*!< Peripheral memory map */
+#define APB1PERIPH_BASE PERIPH_BASE
+#define APB2PERIPH_BASE (PERIPH_BASE + 0x10000)
+#define AHBPERIPH_BASE (PERIPH_BASE + 0x20000)
+
+#define TIM2_BASE (APB1PERIPH_BASE + 0x0000)
+#define TIM3_BASE (APB1PERIPH_BASE + 0x0400)
+#define TIM4_BASE (APB1PERIPH_BASE + 0x0800)
+#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00)
+#define TIM6_BASE (APB1PERIPH_BASE + 0x1000)
+#define TIM7_BASE (APB1PERIPH_BASE + 0x1400)
+#define RTC_BASE (APB1PERIPH_BASE + 0x2800)
+#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00)
+#define IWDG_BASE (APB1PERIPH_BASE + 0x3000)
+#define SPI2_BASE (APB1PERIPH_BASE + 0x3800)
+#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00)
+#define USART2_BASE (APB1PERIPH_BASE + 0x4400)
+#define USART3_BASE (APB1PERIPH_BASE + 0x4800)
+#define UART4_BASE (APB1PERIPH_BASE + 0x4C00)
+#define UART5_BASE (APB1PERIPH_BASE + 0x5000)
+#define I2C1_BASE (APB1PERIPH_BASE + 0x5400)
+#define I2C2_BASE (APB1PERIPH_BASE + 0x5800)
+#define CAN1_BASE (APB1PERIPH_BASE + 0x6400)
+#define CAN2_BASE (APB1PERIPH_BASE + 0x6800)
+#define BKP_BASE (APB1PERIPH_BASE + 0x6C00)
+#define PWR_BASE (APB1PERIPH_BASE + 0x7000)
+#define DAC_BASE (APB1PERIPH_BASE + 0x7400)
+#define AFIO_BASE (APB2PERIPH_BASE + 0x0000)
+#define EXTI_BASE (APB2PERIPH_BASE + 0x0400)
+#define GPIOA_BASE (APB2PERIPH_BASE + 0x0800)
+#define GPIOB_BASE (APB2PERIPH_BASE + 0x0C00)
+#define GPIOC_BASE (APB2PERIPH_BASE + 0x1000)
+#define GPIOD_BASE (APB2PERIPH_BASE + 0x1400)
+#define GPIOE_BASE (APB2PERIPH_BASE + 0x1800)
+#define ADC1_BASE (APB2PERIPH_BASE + 0x2400)
+#define ADC2_BASE (APB2PERIPH_BASE + 0x2800)
+#define TIM1_BASE (APB2PERIPH_BASE + 0x2C00)
+#define SPI1_BASE (APB2PERIPH_BASE + 0x3000)
+#define USART1_BASE (APB2PERIPH_BASE + 0x3800)
+
+#define SDIO_BASE (PERIPH_BASE + 0x18000)
+
+#define DMA1_BASE (AHBPERIPH_BASE + 0x0000)
+#define DMA1_Channel1_BASE (AHBPERIPH_BASE + 0x0008)
+#define DMA1_Channel2_BASE (AHBPERIPH_BASE + 0x001C)
+#define DMA1_Channel3_BASE (AHBPERIPH_BASE + 0x0030)
+#define DMA1_Channel4_BASE (AHBPERIPH_BASE + 0x0044)
+#define DMA1_Channel5_BASE (AHBPERIPH_BASE + 0x0058)
+#define DMA1_Channel6_BASE (AHBPERIPH_BASE + 0x006C)
+#define DMA1_Channel7_BASE (AHBPERIPH_BASE + 0x0080)
+#define DMA2_BASE (AHBPERIPH_BASE + 0x0400)
+#define DMA2_Channel1_BASE (AHBPERIPH_BASE + 0x0408)
+#define DMA2_Channel2_BASE (AHBPERIPH_BASE + 0x041C)
+#define DMA2_Channel3_BASE (AHBPERIPH_BASE + 0x0430)
+#define DMA2_Channel4_BASE (AHBPERIPH_BASE + 0x0444)
+#define DMA2_Channel5_BASE (AHBPERIPH_BASE + 0x0458)
+#define RCC_BASE (AHBPERIPH_BASE + 0x1000)
+#define CRC_BASE (AHBPERIPH_BASE + 0x3000)
+
+#define FLASH_R_BASE (AHBPERIPH_BASE + 0x2000) /*!< Flash registers base address */
+#define FLASHSIZE_BASE ((uint32_t)0x1FFFF7E0) /*!< FLASH Size register base address */
+#define UID_BASE ((uint32_t)0x1FFFF7E8) /*!< Unique device ID register base address */
+#define OB_BASE ((uint32_t)0x1FFFF800) /*!< Flash Option Bytes base address */
+
+
+
+#define DBGMCU_BASE ((uint32_t)0xE0042000) /*!< Debug MCU registers base address */
+
+
+/*!< USB registers base address */
+#define USB_OTG_FS_PERIPH_BASE ((uint32_t )0x50000000)
+
+#define USB_OTG_GLOBAL_BASE ((uint32_t )0x00000000)
+#define USB_OTG_DEVICE_BASE ((uint32_t )0x00000800)
+#define USB_OTG_IN_ENDPOINT_BASE ((uint32_t )0x00000900)
+#define USB_OTG_OUT_ENDPOINT_BASE ((uint32_t )0x00000B00)
+#define USB_OTG_EP_REG_SIZE ((uint32_t )0x00000020)
+#define USB_OTG_HOST_BASE ((uint32_t )0x00000400)
+#define USB_OTG_HOST_PORT_BASE ((uint32_t )0x00000440)
+#define USB_OTG_HOST_CHANNEL_BASE ((uint32_t )0x00000500)
+#define USB_OTG_HOST_CHANNEL_SIZE ((uint32_t )0x00000020)
+#define USB_OTG_PCGCCTL_BASE ((uint32_t )0x00000E00)
+#define USB_OTG_FIFO_BASE ((uint32_t )0x00001000)
+#define USB_OTG_FIFO_SIZE ((uint32_t )0x00001000)
+
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_declaration
+ * @{
+ */
+
+#define TIM2 ((TIM_TypeDef *) TIM2_BASE)
+#define TIM3 ((TIM_TypeDef *) TIM3_BASE)
+#define TIM4 ((TIM_TypeDef *) TIM4_BASE)
+#define TIM5 ((TIM_TypeDef *) TIM5_BASE)
+#define TIM6 ((TIM_TypeDef *) TIM6_BASE)
+#define TIM7 ((TIM_TypeDef *) TIM7_BASE)
+#define RTC ((RTC_TypeDef *) RTC_BASE)
+#define WWDG ((WWDG_TypeDef *) WWDG_BASE)
+#define IWDG ((IWDG_TypeDef *) IWDG_BASE)
+#define SPI2 ((SPI_TypeDef *) SPI2_BASE)
+#define SPI3 ((SPI_TypeDef *) SPI3_BASE)
+#define USART2 ((USART_TypeDef *) USART2_BASE)
+#define USART3 ((USART_TypeDef *) USART3_BASE)
+#define UART4 ((USART_TypeDef *) UART4_BASE)
+#define UART5 ((USART_TypeDef *) UART5_BASE)
+#define I2C1 ((I2C_TypeDef *) I2C1_BASE)
+#define I2C2 ((I2C_TypeDef *) I2C2_BASE)
+#define CAN1 ((CAN_TypeDef *) CAN1_BASE)
+#define CAN2 ((CAN_TypeDef *) CAN2_BASE)
+#define BKP ((BKP_TypeDef *) BKP_BASE)
+#define PWR ((PWR_TypeDef *) PWR_BASE)
+#define DAC ((DAC_TypeDef *) DAC_BASE)
+#define AFIO ((AFIO_TypeDef *) AFIO_BASE)
+#define EXTI ((EXTI_TypeDef *) EXTI_BASE)
+#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
+#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
+#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
+#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
+#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
+#define ADC1 ((ADC_TypeDef *) ADC1_BASE)
+#define ADC2 ((ADC_TypeDef *) ADC2_BASE)
+#define ADC12_COMMON ((ADC_Common_TypeDef *) ADC1_BASE)
+#define TIM1 ((TIM_TypeDef *) TIM1_BASE)
+#define SPI1 ((SPI_TypeDef *) SPI1_BASE)
+#define USART1 ((USART_TypeDef *) USART1_BASE)
+#define SDIO ((SDIO_TypeDef *) SDIO_BASE)
+#define DMA1 ((DMA_TypeDef *) DMA1_BASE)
+#define DMA2 ((DMA_TypeDef *) DMA2_BASE)
+#define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
+#define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
+#define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
+#define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
+#define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
+#define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
+#define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
+#define DMA2_Channel1 ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE)
+#define DMA2_Channel2 ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE)
+#define DMA2_Channel3 ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE)
+#define DMA2_Channel4 ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE)
+#define DMA2_Channel5 ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE)
+#define RCC ((RCC_TypeDef *) RCC_BASE)
+#define CRC ((CRC_TypeDef *) CRC_BASE)
+#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
+#define OB ((OB_TypeDef *) OB_BASE)
+#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
+
+#define USB_OTG_FS ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE)
+
+/**
+ * @}
+ */
+
+/** @addtogroup Exported_constants
+ * @{
+ */
+
+ /** @addtogroup Peripheral_Registers_Bits_Definition
+ * @{
+ */
+
+/******************************************************************************/
+/* Peripheral Registers_Bits_Definition */
+/******************************************************************************/
+
+/******************************************************************************/
+/* */
+/* CRC calculation unit (CRC) */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for CRC_DR register *********************/
+#define CRC_DR_DR_Pos (0U)
+#define CRC_DR_DR_Msk (0xFFFFFFFFU << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */
+#define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */
+
+/******************* Bit definition for CRC_IDR register ********************/
+#define CRC_IDR_IDR_Pos (0U)
+#define CRC_IDR_IDR_Msk (0xFFU << CRC_IDR_IDR_Pos) /*!< 0x000000FF */
+#define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 8-bit data register bits */
+
+/******************** Bit definition for CRC_CR register ********************/
+#define CRC_CR_RESET_Pos (0U)
+#define CRC_CR_RESET_Msk (0x1U << CRC_CR_RESET_Pos) /*!< 0x00000001 */
+#define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET bit */
+
+/******************************************************************************/
+/* */
+/* Power Control */
+/* */
+/******************************************************************************/
+
+/******************** Bit definition for PWR_CR register ********************/
+#define PWR_CR_LPDS_Pos (0U)
+#define PWR_CR_LPDS_Msk (0x1U << PWR_CR_LPDS_Pos) /*!< 0x00000001 */
+#define PWR_CR_LPDS PWR_CR_LPDS_Msk /*!< Low-Power Deepsleep */
+#define PWR_CR_PDDS_Pos (1U)
+#define PWR_CR_PDDS_Msk (0x1U << PWR_CR_PDDS_Pos) /*!< 0x00000002 */
+#define PWR_CR_PDDS PWR_CR_PDDS_Msk /*!< Power Down Deepsleep */
+#define PWR_CR_CWUF_Pos (2U)
+#define PWR_CR_CWUF_Msk (0x1U << PWR_CR_CWUF_Pos) /*!< 0x00000004 */
+#define PWR_CR_CWUF PWR_CR_CWUF_Msk /*!< Clear Wakeup Flag */
+#define PWR_CR_CSBF_Pos (3U)
+#define PWR_CR_CSBF_Msk (0x1U << PWR_CR_CSBF_Pos) /*!< 0x00000008 */
+#define PWR_CR_CSBF PWR_CR_CSBF_Msk /*!< Clear Standby Flag */
+#define PWR_CR_PVDE_Pos (4U)
+#define PWR_CR_PVDE_Msk (0x1U << PWR_CR_PVDE_Pos) /*!< 0x00000010 */
+#define PWR_CR_PVDE PWR_CR_PVDE_Msk /*!< Power Voltage Detector Enable */
+
+#define PWR_CR_PLS_Pos (5U)
+#define PWR_CR_PLS_Msk (0x7U << PWR_CR_PLS_Pos) /*!< 0x000000E0 */
+#define PWR_CR_PLS PWR_CR_PLS_Msk /*!< PLS[2:0] bits (PVD Level Selection) */
+#define PWR_CR_PLS_0 (0x1U << PWR_CR_PLS_Pos) /*!< 0x00000020 */
+#define PWR_CR_PLS_1 (0x2U << PWR_CR_PLS_Pos) /*!< 0x00000040 */
+#define PWR_CR_PLS_2 (0x4U << PWR_CR_PLS_Pos) /*!< 0x00000080 */
+
+/*!< PVD level configuration */
+#define PWR_CR_PLS_2V2 ((uint32_t)0x00000000) /*!< PVD level 2.2V */
+#define PWR_CR_PLS_2V3 ((uint32_t)0x00000020) /*!< PVD level 2.3V */
+#define PWR_CR_PLS_2V4 ((uint32_t)0x00000040) /*!< PVD level 2.4V */
+#define PWR_CR_PLS_2V5 ((uint32_t)0x00000060) /*!< PVD level 2.5V */
+#define PWR_CR_PLS_2V6 ((uint32_t)0x00000080) /*!< PVD level 2.6V */
+#define PWR_CR_PLS_2V7 ((uint32_t)0x000000A0) /*!< PVD level 2.7V */
+#define PWR_CR_PLS_2V8 ((uint32_t)0x000000C0) /*!< PVD level 2.8V */
+#define PWR_CR_PLS_2V9 ((uint32_t)0x000000E0) /*!< PVD level 2.9V */
+
+#define PWR_CR_DBP_Pos (8U)
+#define PWR_CR_DBP_Msk (0x1U << PWR_CR_DBP_Pos) /*!< 0x00000100 */
+#define PWR_CR_DBP PWR_CR_DBP_Msk /*!< Disable Backup Domain write protection */
+
+
+/******************* Bit definition for PWR_CSR register ********************/
+#define PWR_CSR_WUF_Pos (0U)
+#define PWR_CSR_WUF_Msk (0x1U << PWR_CSR_WUF_Pos) /*!< 0x00000001 */
+#define PWR_CSR_WUF PWR_CSR_WUF_Msk /*!< Wakeup Flag */
+#define PWR_CSR_SBF_Pos (1U)
+#define PWR_CSR_SBF_Msk (0x1U << PWR_CSR_SBF_Pos) /*!< 0x00000002 */
+#define PWR_CSR_SBF PWR_CSR_SBF_Msk /*!< Standby Flag */
+#define PWR_CSR_PVDO_Pos (2U)
+#define PWR_CSR_PVDO_Msk (0x1U << PWR_CSR_PVDO_Pos) /*!< 0x00000004 */
+#define PWR_CSR_PVDO PWR_CSR_PVDO_Msk /*!< PVD Output */
+#define PWR_CSR_EWUP_Pos (8U)
+#define PWR_CSR_EWUP_Msk (0x1U << PWR_CSR_EWUP_Pos) /*!< 0x00000100 */
+#define PWR_CSR_EWUP PWR_CSR_EWUP_Msk /*!< Enable WKUP pin */
+
+/******************************************************************************/
+/* */
+/* Backup registers */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for BKP_DR1 register ********************/
+#define BKP_DR1_D_Pos (0U)
+#define BKP_DR1_D_Msk (0xFFFFU << BKP_DR1_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR1_D BKP_DR1_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR2 register ********************/
+#define BKP_DR2_D_Pos (0U)
+#define BKP_DR2_D_Msk (0xFFFFU << BKP_DR2_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR2_D BKP_DR2_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR3 register ********************/
+#define BKP_DR3_D_Pos (0U)
+#define BKP_DR3_D_Msk (0xFFFFU << BKP_DR3_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR3_D BKP_DR3_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR4 register ********************/
+#define BKP_DR4_D_Pos (0U)
+#define BKP_DR4_D_Msk (0xFFFFU << BKP_DR4_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR4_D BKP_DR4_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR5 register ********************/
+#define BKP_DR5_D_Pos (0U)
+#define BKP_DR5_D_Msk (0xFFFFU << BKP_DR5_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR5_D BKP_DR5_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR6 register ********************/
+#define BKP_DR6_D_Pos (0U)
+#define BKP_DR6_D_Msk (0xFFFFU << BKP_DR6_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR6_D BKP_DR6_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR7 register ********************/
+#define BKP_DR7_D_Pos (0U)
+#define BKP_DR7_D_Msk (0xFFFFU << BKP_DR7_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR7_D BKP_DR7_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR8 register ********************/
+#define BKP_DR8_D_Pos (0U)
+#define BKP_DR8_D_Msk (0xFFFFU << BKP_DR8_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR8_D BKP_DR8_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR9 register ********************/
+#define BKP_DR9_D_Pos (0U)
+#define BKP_DR9_D_Msk (0xFFFFU << BKP_DR9_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR9_D BKP_DR9_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR10 register *******************/
+#define BKP_DR10_D_Pos (0U)
+#define BKP_DR10_D_Msk (0xFFFFU << BKP_DR10_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR10_D BKP_DR10_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR11 register *******************/
+#define BKP_DR11_D_Pos (0U)
+#define BKP_DR11_D_Msk (0xFFFFU << BKP_DR11_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR11_D BKP_DR11_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR12 register *******************/
+#define BKP_DR12_D_Pos (0U)
+#define BKP_DR12_D_Msk (0xFFFFU << BKP_DR12_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR12_D BKP_DR12_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR13 register *******************/
+#define BKP_DR13_D_Pos (0U)
+#define BKP_DR13_D_Msk (0xFFFFU << BKP_DR13_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR13_D BKP_DR13_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR14 register *******************/
+#define BKP_DR14_D_Pos (0U)
+#define BKP_DR14_D_Msk (0xFFFFU << BKP_DR14_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR14_D BKP_DR14_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR15 register *******************/
+#define BKP_DR15_D_Pos (0U)
+#define BKP_DR15_D_Msk (0xFFFFU << BKP_DR15_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR15_D BKP_DR15_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR16 register *******************/
+#define BKP_DR16_D_Pos (0U)
+#define BKP_DR16_D_Msk (0xFFFFU << BKP_DR16_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR16_D BKP_DR16_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR17 register *******************/
+#define BKP_DR17_D_Pos (0U)
+#define BKP_DR17_D_Msk (0xFFFFU << BKP_DR17_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR17_D BKP_DR17_D_Msk /*!< Backup data */
+
+/****************** Bit definition for BKP_DR18 register ********************/
+#define BKP_DR18_D_Pos (0U)
+#define BKP_DR18_D_Msk (0xFFFFU << BKP_DR18_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR18_D BKP_DR18_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR19 register *******************/
+#define BKP_DR19_D_Pos (0U)
+#define BKP_DR19_D_Msk (0xFFFFU << BKP_DR19_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR19_D BKP_DR19_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR20 register *******************/
+#define BKP_DR20_D_Pos (0U)
+#define BKP_DR20_D_Msk (0xFFFFU << BKP_DR20_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR20_D BKP_DR20_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR21 register *******************/
+#define BKP_DR21_D_Pos (0U)
+#define BKP_DR21_D_Msk (0xFFFFU << BKP_DR21_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR21_D BKP_DR21_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR22 register *******************/
+#define BKP_DR22_D_Pos (0U)
+#define BKP_DR22_D_Msk (0xFFFFU << BKP_DR22_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR22_D BKP_DR22_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR23 register *******************/
+#define BKP_DR23_D_Pos (0U)
+#define BKP_DR23_D_Msk (0xFFFFU << BKP_DR23_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR23_D BKP_DR23_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR24 register *******************/
+#define BKP_DR24_D_Pos (0U)
+#define BKP_DR24_D_Msk (0xFFFFU << BKP_DR24_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR24_D BKP_DR24_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR25 register *******************/
+#define BKP_DR25_D_Pos (0U)
+#define BKP_DR25_D_Msk (0xFFFFU << BKP_DR25_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR25_D BKP_DR25_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR26 register *******************/
+#define BKP_DR26_D_Pos (0U)
+#define BKP_DR26_D_Msk (0xFFFFU << BKP_DR26_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR26_D BKP_DR26_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR27 register *******************/
+#define BKP_DR27_D_Pos (0U)
+#define BKP_DR27_D_Msk (0xFFFFU << BKP_DR27_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR27_D BKP_DR27_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR28 register *******************/
+#define BKP_DR28_D_Pos (0U)
+#define BKP_DR28_D_Msk (0xFFFFU << BKP_DR28_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR28_D BKP_DR28_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR29 register *******************/
+#define BKP_DR29_D_Pos (0U)
+#define BKP_DR29_D_Msk (0xFFFFU << BKP_DR29_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR29_D BKP_DR29_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR30 register *******************/
+#define BKP_DR30_D_Pos (0U)
+#define BKP_DR30_D_Msk (0xFFFFU << BKP_DR30_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR30_D BKP_DR30_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR31 register *******************/
+#define BKP_DR31_D_Pos (0U)
+#define BKP_DR31_D_Msk (0xFFFFU << BKP_DR31_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR31_D BKP_DR31_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR32 register *******************/
+#define BKP_DR32_D_Pos (0U)
+#define BKP_DR32_D_Msk (0xFFFFU << BKP_DR32_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR32_D BKP_DR32_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR33 register *******************/
+#define BKP_DR33_D_Pos (0U)
+#define BKP_DR33_D_Msk (0xFFFFU << BKP_DR33_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR33_D BKP_DR33_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR34 register *******************/
+#define BKP_DR34_D_Pos (0U)
+#define BKP_DR34_D_Msk (0xFFFFU << BKP_DR34_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR34_D BKP_DR34_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR35 register *******************/
+#define BKP_DR35_D_Pos (0U)
+#define BKP_DR35_D_Msk (0xFFFFU << BKP_DR35_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR35_D BKP_DR35_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR36 register *******************/
+#define BKP_DR36_D_Pos (0U)
+#define BKP_DR36_D_Msk (0xFFFFU << BKP_DR36_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR36_D BKP_DR36_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR37 register *******************/
+#define BKP_DR37_D_Pos (0U)
+#define BKP_DR37_D_Msk (0xFFFFU << BKP_DR37_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR37_D BKP_DR37_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR38 register *******************/
+#define BKP_DR38_D_Pos (0U)
+#define BKP_DR38_D_Msk (0xFFFFU << BKP_DR38_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR38_D BKP_DR38_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR39 register *******************/
+#define BKP_DR39_D_Pos (0U)
+#define BKP_DR39_D_Msk (0xFFFFU << BKP_DR39_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR39_D BKP_DR39_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR40 register *******************/
+#define BKP_DR40_D_Pos (0U)
+#define BKP_DR40_D_Msk (0xFFFFU << BKP_DR40_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR40_D BKP_DR40_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR41 register *******************/
+#define BKP_DR41_D_Pos (0U)
+#define BKP_DR41_D_Msk (0xFFFFU << BKP_DR41_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR41_D BKP_DR41_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR42 register *******************/
+#define BKP_DR42_D_Pos (0U)
+#define BKP_DR42_D_Msk (0xFFFFU << BKP_DR42_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR42_D BKP_DR42_D_Msk /*!< Backup data */
+
+#define RTC_BKP_NUMBER 42
+
+/****************** Bit definition for BKP_RTCCR register *******************/
+#define BKP_RTCCR_CAL_Pos (0U)
+#define BKP_RTCCR_CAL_Msk (0x7FU << BKP_RTCCR_CAL_Pos) /*!< 0x0000007F */
+#define BKP_RTCCR_CAL BKP_RTCCR_CAL_Msk /*!< Calibration value */
+#define BKP_RTCCR_CCO_Pos (7U)
+#define BKP_RTCCR_CCO_Msk (0x1U << BKP_RTCCR_CCO_Pos) /*!< 0x00000080 */
+#define BKP_RTCCR_CCO BKP_RTCCR_CCO_Msk /*!< Calibration Clock Output */
+#define BKP_RTCCR_ASOE_Pos (8U)
+#define BKP_RTCCR_ASOE_Msk (0x1U << BKP_RTCCR_ASOE_Pos) /*!< 0x00000100 */
+#define BKP_RTCCR_ASOE BKP_RTCCR_ASOE_Msk /*!< Alarm or Second Output Enable */
+#define BKP_RTCCR_ASOS_Pos (9U)
+#define BKP_RTCCR_ASOS_Msk (0x1U << BKP_RTCCR_ASOS_Pos) /*!< 0x00000200 */
+#define BKP_RTCCR_ASOS BKP_RTCCR_ASOS_Msk /*!< Alarm or Second Output Selection */
+
+/******************** Bit definition for BKP_CR register ********************/
+#define BKP_CR_TPE_Pos (0U)
+#define BKP_CR_TPE_Msk (0x1U << BKP_CR_TPE_Pos) /*!< 0x00000001 */
+#define BKP_CR_TPE BKP_CR_TPE_Msk /*!< TAMPER pin enable */
+#define BKP_CR_TPAL_Pos (1U)
+#define BKP_CR_TPAL_Msk (0x1U << BKP_CR_TPAL_Pos) /*!< 0x00000002 */
+#define BKP_CR_TPAL BKP_CR_TPAL_Msk /*!< TAMPER pin active level */
+
+/******************* Bit definition for BKP_CSR register ********************/
+#define BKP_CSR_CTE_Pos (0U)
+#define BKP_CSR_CTE_Msk (0x1U << BKP_CSR_CTE_Pos) /*!< 0x00000001 */
+#define BKP_CSR_CTE BKP_CSR_CTE_Msk /*!< Clear Tamper event */
+#define BKP_CSR_CTI_Pos (1U)
+#define BKP_CSR_CTI_Msk (0x1U << BKP_CSR_CTI_Pos) /*!< 0x00000002 */
+#define BKP_CSR_CTI BKP_CSR_CTI_Msk /*!< Clear Tamper Interrupt */
+#define BKP_CSR_TPIE_Pos (2U)
+#define BKP_CSR_TPIE_Msk (0x1U << BKP_CSR_TPIE_Pos) /*!< 0x00000004 */
+#define BKP_CSR_TPIE BKP_CSR_TPIE_Msk /*!< TAMPER Pin interrupt enable */
+#define BKP_CSR_TEF_Pos (8U)
+#define BKP_CSR_TEF_Msk (0x1U << BKP_CSR_TEF_Pos) /*!< 0x00000100 */
+#define BKP_CSR_TEF BKP_CSR_TEF_Msk /*!< Tamper Event Flag */
+#define BKP_CSR_TIF_Pos (9U)
+#define BKP_CSR_TIF_Msk (0x1U << BKP_CSR_TIF_Pos) /*!< 0x00000200 */
+#define BKP_CSR_TIF BKP_CSR_TIF_Msk /*!< Tamper Interrupt Flag */
+
+/******************************************************************************/
+/* */
+/* Reset and Clock Control */
+/* */
+/******************************************************************************/
+
+/******************** Bit definition for RCC_CR register ********************/
+#define RCC_CR_HSION_Pos (0U)
+#define RCC_CR_HSION_Msk (0x1U << RCC_CR_HSION_Pos) /*!< 0x00000001 */
+#define RCC_CR_HSION RCC_CR_HSION_Msk /*!< Internal High Speed clock enable */
+#define RCC_CR_HSIRDY_Pos (1U)
+#define RCC_CR_HSIRDY_Msk (0x1U << RCC_CR_HSIRDY_Pos) /*!< 0x00000002 */
+#define RCC_CR_HSIRDY RCC_CR_HSIRDY_Msk /*!< Internal High Speed clock ready flag */
+#define RCC_CR_HSITRIM_Pos (3U)
+#define RCC_CR_HSITRIM_Msk (0x1FU << RCC_CR_HSITRIM_Pos) /*!< 0x000000F8 */
+#define RCC_CR_HSITRIM RCC_CR_HSITRIM_Msk /*!< Internal High Speed clock trimming */
+#define RCC_CR_HSICAL_Pos (8U)
+#define RCC_CR_HSICAL_Msk (0xFFU << RCC_CR_HSICAL_Pos) /*!< 0x0000FF00 */
+#define RCC_CR_HSICAL RCC_CR_HSICAL_Msk /*!< Internal High Speed clock Calibration */
+#define RCC_CR_HSEON_Pos (16U)
+#define RCC_CR_HSEON_Msk (0x1U << RCC_CR_HSEON_Pos) /*!< 0x00010000 */
+#define RCC_CR_HSEON RCC_CR_HSEON_Msk /*!< External High Speed clock enable */
+#define RCC_CR_HSERDY_Pos (17U)
+#define RCC_CR_HSERDY_Msk (0x1U << RCC_CR_HSERDY_Pos) /*!< 0x00020000 */
+#define RCC_CR_HSERDY RCC_CR_HSERDY_Msk /*!< External High Speed clock ready flag */
+#define RCC_CR_HSEBYP_Pos (18U)
+#define RCC_CR_HSEBYP_Msk (0x1U << RCC_CR_HSEBYP_Pos) /*!< 0x00040000 */
+#define RCC_CR_HSEBYP RCC_CR_HSEBYP_Msk /*!< External High Speed clock Bypass */
+#define RCC_CR_CSSON_Pos (19U)
+#define RCC_CR_CSSON_Msk (0x1U << RCC_CR_CSSON_Pos) /*!< 0x00080000 */
+#define RCC_CR_CSSON RCC_CR_CSSON_Msk /*!< Clock Security System enable */
+#define RCC_CR_PLLON_Pos (24U)
+#define RCC_CR_PLLON_Msk (0x1U << RCC_CR_PLLON_Pos) /*!< 0x01000000 */
+#define RCC_CR_PLLON RCC_CR_PLLON_Msk /*!< PLL enable */
+#define RCC_CR_PLLRDY_Pos (25U)
+#define RCC_CR_PLLRDY_Msk (0x1U << RCC_CR_PLLRDY_Pos) /*!< 0x02000000 */
+#define RCC_CR_PLLRDY RCC_CR_PLLRDY_Msk /*!< PLL clock ready flag */
+
+#define RCC_CR_PLL2ON_Pos (26U)
+#define RCC_CR_PLL2ON_Msk (0x1U << RCC_CR_PLL2ON_Pos) /*!< 0x04000000 */
+#define RCC_CR_PLL2ON RCC_CR_PLL2ON_Msk /*!< PLL2 enable */
+#define RCC_CR_PLL2RDY_Pos (27U)
+#define RCC_CR_PLL2RDY_Msk (0x1U << RCC_CR_PLL2RDY_Pos) /*!< 0x08000000 */
+#define RCC_CR_PLL2RDY RCC_CR_PLL2RDY_Msk /*!< PLL2 clock ready flag */
+#define RCC_CR_PLL3ON_Pos (28U)
+#define RCC_CR_PLL3ON_Msk (0x1U << RCC_CR_PLL3ON_Pos) /*!< 0x10000000 */
+#define RCC_CR_PLL3ON RCC_CR_PLL3ON_Msk /*!< PLL3 enable */
+#define RCC_CR_PLL3RDY_Pos (29U)
+#define RCC_CR_PLL3RDY_Msk (0x1U << RCC_CR_PLL3RDY_Pos) /*!< 0x20000000 */
+#define RCC_CR_PLL3RDY RCC_CR_PLL3RDY_Msk /*!< PLL3 clock ready flag */
+
+/******************* Bit definition for RCC_CFGR register *******************/
+/*!< SW configuration */
+#define RCC_CFGR_SW_Pos (0U)
+#define RCC_CFGR_SW_Msk (0x3U << RCC_CFGR_SW_Pos) /*!< 0x00000003 */
+#define RCC_CFGR_SW RCC_CFGR_SW_Msk /*!< SW[1:0] bits (System clock Switch) */
+#define RCC_CFGR_SW_0 (0x1U << RCC_CFGR_SW_Pos) /*!< 0x00000001 */
+#define RCC_CFGR_SW_1 (0x2U << RCC_CFGR_SW_Pos) /*!< 0x00000002 */
+
+#define RCC_CFGR_SW_HSI ((uint32_t)0x00000000) /*!< HSI selected as system clock */
+#define RCC_CFGR_SW_HSE ((uint32_t)0x00000001) /*!< HSE selected as system clock */
+#define RCC_CFGR_SW_PLL ((uint32_t)0x00000002) /*!< PLL selected as system clock */
+
+/*!< SWS configuration */
+#define RCC_CFGR_SWS_Pos (2U)
+#define RCC_CFGR_SWS_Msk (0x3U << RCC_CFGR_SWS_Pos) /*!< 0x0000000C */
+#define RCC_CFGR_SWS RCC_CFGR_SWS_Msk /*!< SWS[1:0] bits (System Clock Switch Status) */
+#define RCC_CFGR_SWS_0 (0x1U << RCC_CFGR_SWS_Pos) /*!< 0x00000004 */
+#define RCC_CFGR_SWS_1 (0x2U << RCC_CFGR_SWS_Pos) /*!< 0x00000008 */
+
+#define RCC_CFGR_SWS_HSI ((uint32_t)0x00000000) /*!< HSI oscillator used as system clock */
+#define RCC_CFGR_SWS_HSE ((uint32_t)0x00000004) /*!< HSE oscillator used as system clock */
+#define RCC_CFGR_SWS_PLL ((uint32_t)0x00000008) /*!< PLL used as system clock */
+
+/*!< HPRE configuration */
+#define RCC_CFGR_HPRE_Pos (4U)
+#define RCC_CFGR_HPRE_Msk (0xFU << RCC_CFGR_HPRE_Pos) /*!< 0x000000F0 */
+#define RCC_CFGR_HPRE RCC_CFGR_HPRE_Msk /*!< HPRE[3:0] bits (AHB prescaler) */
+#define RCC_CFGR_HPRE_0 (0x1U << RCC_CFGR_HPRE_Pos) /*!< 0x00000010 */
+#define RCC_CFGR_HPRE_1 (0x2U << RCC_CFGR_HPRE_Pos) /*!< 0x00000020 */
+#define RCC_CFGR_HPRE_2 (0x4U << RCC_CFGR_HPRE_Pos) /*!< 0x00000040 */
+#define RCC_CFGR_HPRE_3 (0x8U << RCC_CFGR_HPRE_Pos) /*!< 0x00000080 */
+
+#define RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000) /*!< SYSCLK not divided */
+#define RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080) /*!< SYSCLK divided by 2 */
+#define RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090) /*!< SYSCLK divided by 4 */
+#define RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0) /*!< SYSCLK divided by 8 */
+#define RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0) /*!< SYSCLK divided by 16 */
+#define RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0) /*!< SYSCLK divided by 64 */
+#define RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0) /*!< SYSCLK divided by 128 */
+#define RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0) /*!< SYSCLK divided by 256 */
+#define RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0) /*!< SYSCLK divided by 512 */
+
+/*!< PPRE1 configuration */
+#define RCC_CFGR_PPRE1_Pos (8U)
+#define RCC_CFGR_PPRE1_Msk (0x7U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000700 */
+#define RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_Msk /*!< PRE1[2:0] bits (APB1 prescaler) */
+#define RCC_CFGR_PPRE1_0 (0x1U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000100 */
+#define RCC_CFGR_PPRE1_1 (0x2U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000200 */
+#define RCC_CFGR_PPRE1_2 (0x4U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000400 */
+
+#define RCC_CFGR_PPRE1_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */
+#define RCC_CFGR_PPRE1_DIV2 ((uint32_t)0x00000400) /*!< HCLK divided by 2 */
+#define RCC_CFGR_PPRE1_DIV4 ((uint32_t)0x00000500) /*!< HCLK divided by 4 */
+#define RCC_CFGR_PPRE1_DIV8 ((uint32_t)0x00000600) /*!< HCLK divided by 8 */
+#define RCC_CFGR_PPRE1_DIV16 ((uint32_t)0x00000700) /*!< HCLK divided by 16 */
+
+/*!< PPRE2 configuration */
+#define RCC_CFGR_PPRE2_Pos (11U)
+#define RCC_CFGR_PPRE2_Msk (0x7U << RCC_CFGR_PPRE2_Pos) /*!< 0x00003800 */
+#define RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_Msk /*!< PRE2[2:0] bits (APB2 prescaler) */
+#define RCC_CFGR_PPRE2_0 (0x1U << RCC_CFGR_PPRE2_Pos) /*!< 0x00000800 */
+#define RCC_CFGR_PPRE2_1 (0x2U << RCC_CFGR_PPRE2_Pos) /*!< 0x00001000 */
+#define RCC_CFGR_PPRE2_2 (0x4U << RCC_CFGR_PPRE2_Pos) /*!< 0x00002000 */
+
+#define RCC_CFGR_PPRE2_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */
+#define RCC_CFGR_PPRE2_DIV2 ((uint32_t)0x00002000) /*!< HCLK divided by 2 */
+#define RCC_CFGR_PPRE2_DIV4 ((uint32_t)0x00002800) /*!< HCLK divided by 4 */
+#define RCC_CFGR_PPRE2_DIV8 ((uint32_t)0x00003000) /*!< HCLK divided by 8 */
+#define RCC_CFGR_PPRE2_DIV16 ((uint32_t)0x00003800) /*!< HCLK divided by 16 */
+
+/*!< ADCPPRE configuration */
+#define RCC_CFGR_ADCPRE_Pos (14U)
+#define RCC_CFGR_ADCPRE_Msk (0x3U << RCC_CFGR_ADCPRE_Pos) /*!< 0x0000C000 */
+#define RCC_CFGR_ADCPRE RCC_CFGR_ADCPRE_Msk /*!< ADCPRE[1:0] bits (ADC prescaler) */
+#define RCC_CFGR_ADCPRE_0 (0x1U << RCC_CFGR_ADCPRE_Pos) /*!< 0x00004000 */
+#define RCC_CFGR_ADCPRE_1 (0x2U << RCC_CFGR_ADCPRE_Pos) /*!< 0x00008000 */
+
+#define RCC_CFGR_ADCPRE_DIV2 ((uint32_t)0x00000000) /*!< PCLK2 divided by 2 */
+#define RCC_CFGR_ADCPRE_DIV4 ((uint32_t)0x00004000) /*!< PCLK2 divided by 4 */
+#define RCC_CFGR_ADCPRE_DIV6 ((uint32_t)0x00008000) /*!< PCLK2 divided by 6 */
+#define RCC_CFGR_ADCPRE_DIV8 ((uint32_t)0x0000C000) /*!< PCLK2 divided by 8 */
+
+#define RCC_CFGR_PLLSRC_Pos (16U)
+#define RCC_CFGR_PLLSRC_Msk (0x1U << RCC_CFGR_PLLSRC_Pos) /*!< 0x00010000 */
+#define RCC_CFGR_PLLSRC RCC_CFGR_PLLSRC_Msk /*!< PLL entry clock source */
+
+#define RCC_CFGR_PLLXTPRE_Pos (17U)
+#define RCC_CFGR_PLLXTPRE_Msk (0x1U << RCC_CFGR_PLLXTPRE_Pos) /*!< 0x00020000 */
+#define RCC_CFGR_PLLXTPRE RCC_CFGR_PLLXTPRE_Msk /*!< HSE divider for PLL entry */
+
+/*!< PLLMUL configuration */
+#define RCC_CFGR_PLLMULL_Pos (18U)
+#define RCC_CFGR_PLLMULL_Msk (0xFU << RCC_CFGR_PLLMULL_Pos) /*!< 0x003C0000 */
+#define RCC_CFGR_PLLMULL RCC_CFGR_PLLMULL_Msk /*!< PLLMUL[3:0] bits (PLL multiplication factor) */
+#define RCC_CFGR_PLLMULL_0 (0x1U << RCC_CFGR_PLLMULL_Pos) /*!< 0x00040000 */
+#define RCC_CFGR_PLLMULL_1 (0x2U << RCC_CFGR_PLLMULL_Pos) /*!< 0x00080000 */
+#define RCC_CFGR_PLLMULL_2 (0x4U << RCC_CFGR_PLLMULL_Pos) /*!< 0x00100000 */
+#define RCC_CFGR_PLLMULL_3 (0x8U << RCC_CFGR_PLLMULL_Pos) /*!< 0x00200000 */
+
+#define RCC_CFGR_PLLXTPRE_PREDIV1 ((uint32_t)0x00000000) /*!< PREDIV1 clock not divided for PLL entry */
+#define RCC_CFGR_PLLXTPRE_PREDIV1_DIV2 ((uint32_t)0x00020000) /*!< PREDIV1 clock divided by 2 for PLL entry */
+
+#define RCC_CFGR_PLLMULL4_Pos (19U)
+#define RCC_CFGR_PLLMULL4_Msk (0x1U << RCC_CFGR_PLLMULL4_Pos) /*!< 0x00080000 */
+#define RCC_CFGR_PLLMULL4 RCC_CFGR_PLLMULL4_Msk /*!< PLL input clock * 4 */
+#define RCC_CFGR_PLLMULL5_Pos (18U)
+#define RCC_CFGR_PLLMULL5_Msk (0x3U << RCC_CFGR_PLLMULL5_Pos) /*!< 0x000C0000 */
+#define RCC_CFGR_PLLMULL5 RCC_CFGR_PLLMULL5_Msk /*!< PLL input clock * 5 */
+#define RCC_CFGR_PLLMULL6_Pos (20U)
+#define RCC_CFGR_PLLMULL6_Msk (0x1U << RCC_CFGR_PLLMULL6_Pos) /*!< 0x00100000 */
+#define RCC_CFGR_PLLMULL6 RCC_CFGR_PLLMULL6_Msk /*!< PLL input clock * 6 */
+#define RCC_CFGR_PLLMULL7_Pos (18U)
+#define RCC_CFGR_PLLMULL7_Msk (0x5U << RCC_CFGR_PLLMULL7_Pos) /*!< 0x00140000 */
+#define RCC_CFGR_PLLMULL7 RCC_CFGR_PLLMULL7_Msk /*!< PLL input clock * 7 */
+#define RCC_CFGR_PLLMULL8_Pos (19U)
+#define RCC_CFGR_PLLMULL8_Msk (0x3U << RCC_CFGR_PLLMULL8_Pos) /*!< 0x00180000 */
+#define RCC_CFGR_PLLMULL8 RCC_CFGR_PLLMULL8_Msk /*!< PLL input clock * 8 */
+#define RCC_CFGR_PLLMULL9_Pos (18U)
+#define RCC_CFGR_PLLMULL9_Msk (0x7U << RCC_CFGR_PLLMULL9_Pos) /*!< 0x001C0000 */
+#define RCC_CFGR_PLLMULL9 RCC_CFGR_PLLMULL9_Msk /*!< PLL input clock * 9 */
+#define RCC_CFGR_PLLMULL6_5 ((uint32_t)0x00340000) /*!< PLL input clock * 6.5 */
+
+#define RCC_CFGR_OTGFSPRE_Pos (22U)
+#define RCC_CFGR_OTGFSPRE_Msk (0x1U << RCC_CFGR_OTGFSPRE_Pos) /*!< 0x00400000 */
+#define RCC_CFGR_OTGFSPRE RCC_CFGR_OTGFSPRE_Msk /*!< USB OTG FS prescaler */
+
+/*!< MCO configuration */
+#define RCC_CFGR_MCO_Pos (24U)
+#define RCC_CFGR_MCO_Msk (0xFU << RCC_CFGR_MCO_Pos) /*!< 0x0F000000 */
+#define RCC_CFGR_MCO RCC_CFGR_MCO_Msk /*!< MCO[3:0] bits (Microcontroller Clock Output) */
+#define RCC_CFGR_MCO_0 (0x1U << RCC_CFGR_MCO_Pos) /*!< 0x01000000 */
+#define RCC_CFGR_MCO_1 (0x2U << RCC_CFGR_MCO_Pos) /*!< 0x02000000 */
+#define RCC_CFGR_MCO_2 (0x4U << RCC_CFGR_MCO_Pos) /*!< 0x04000000 */
+#define RCC_CFGR_MCO_3 (0x8U << RCC_CFGR_MCO_Pos) /*!< 0x08000000 */
+
+#define RCC_CFGR_MCO_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */
+#define RCC_CFGR_MCO_SYSCLK ((uint32_t)0x04000000) /*!< System clock selected as MCO source */
+#define RCC_CFGR_MCO_HSI ((uint32_t)0x05000000) /*!< HSI clock selected as MCO source */
+#define RCC_CFGR_MCO_HSE ((uint32_t)0x06000000) /*!< HSE clock selected as MCO source */
+#define RCC_CFGR_MCO_PLLCLK_DIV2 ((uint32_t)0x07000000) /*!< PLL clock divided by 2 selected as MCO source */
+#define RCC_CFGR_MCO_PLL2CLK ((uint32_t)0x08000000) /*!< PLL2 clock selected as MCO source*/
+#define RCC_CFGR_MCO_PLL3CLK_DIV2 ((uint32_t)0x09000000) /*!< PLL3 clock divided by 2 selected as MCO source*/
+#define RCC_CFGR_MCO_EXT_HSE ((uint32_t)0x0A000000) /*!< XT1 external 3-25 MHz oscillator clock selected as MCO source */
+#define RCC_CFGR_MCO_PLL3CLK ((uint32_t)0x0B000000) /*!< PLL3 clock selected as MCO source */
+
+ /* Reference defines */
+ #define RCC_CFGR_MCOSEL RCC_CFGR_MCO
+ #define RCC_CFGR_MCOSEL_0 RCC_CFGR_MCO_0
+ #define RCC_CFGR_MCOSEL_1 RCC_CFGR_MCO_1
+ #define RCC_CFGR_MCOSEL_2 RCC_CFGR_MCO_2
+ #define RCC_CFGR_MCOSEL_3 RCC_CFGR_MCO_3
+ #define RCC_CFGR_MCOSEL_NOCLOCK RCC_CFGR_MCO_NOCLOCK
+ #define RCC_CFGR_MCOSEL_SYSCLK RCC_CFGR_MCO_SYSCLK
+ #define RCC_CFGR_MCOSEL_HSI RCC_CFGR_MCO_HSI
+ #define RCC_CFGR_MCOSEL_HSE RCC_CFGR_MCO_HSE
+ #define RCC_CFGR_MCOSEL_PLL_DIV2 RCC_CFGR_MCO_PLLCLK_DIV2
+ #define RCC_CFGR_MCOSEL_PLL2 RCC_CFGR_MCO_PLL2CLK
+ #define RCC_CFGR_MCOSEL_PLL3_DIV2 RCC_CFGR_MCO_PLL3CLK_DIV2
+ #define RCC_CFGR_MCOSEL_EXT_HSE RCC_CFGR_MCO_EXT_HSE
+ #define RCC_CFGR_MCOSEL_PLL3CLK RCC_CFGR_MCO_PLL3CLK
+
+/*!<****************** Bit definition for RCC_CIR register ********************/
+#define RCC_CIR_LSIRDYF_Pos (0U)
+#define RCC_CIR_LSIRDYF_Msk (0x1U << RCC_CIR_LSIRDYF_Pos) /*!< 0x00000001 */
+#define RCC_CIR_LSIRDYF RCC_CIR_LSIRDYF_Msk /*!< LSI Ready Interrupt flag */
+#define RCC_CIR_LSERDYF_Pos (1U)
+#define RCC_CIR_LSERDYF_Msk (0x1U << RCC_CIR_LSERDYF_Pos) /*!< 0x00000002 */
+#define RCC_CIR_LSERDYF RCC_CIR_LSERDYF_Msk /*!< LSE Ready Interrupt flag */
+#define RCC_CIR_HSIRDYF_Pos (2U)
+#define RCC_CIR_HSIRDYF_Msk (0x1U << RCC_CIR_HSIRDYF_Pos) /*!< 0x00000004 */
+#define RCC_CIR_HSIRDYF RCC_CIR_HSIRDYF_Msk /*!< HSI Ready Interrupt flag */
+#define RCC_CIR_HSERDYF_Pos (3U)
+#define RCC_CIR_HSERDYF_Msk (0x1U << RCC_CIR_HSERDYF_Pos) /*!< 0x00000008 */
+#define RCC_CIR_HSERDYF RCC_CIR_HSERDYF_Msk /*!< HSE Ready Interrupt flag */
+#define RCC_CIR_PLLRDYF_Pos (4U)
+#define RCC_CIR_PLLRDYF_Msk (0x1U << RCC_CIR_PLLRDYF_Pos) /*!< 0x00000010 */
+#define RCC_CIR_PLLRDYF RCC_CIR_PLLRDYF_Msk /*!< PLL Ready Interrupt flag */
+#define RCC_CIR_CSSF_Pos (7U)
+#define RCC_CIR_CSSF_Msk (0x1U << RCC_CIR_CSSF_Pos) /*!< 0x00000080 */
+#define RCC_CIR_CSSF RCC_CIR_CSSF_Msk /*!< Clock Security System Interrupt flag */
+#define RCC_CIR_LSIRDYIE_Pos (8U)
+#define RCC_CIR_LSIRDYIE_Msk (0x1U << RCC_CIR_LSIRDYIE_Pos) /*!< 0x00000100 */
+#define RCC_CIR_LSIRDYIE RCC_CIR_LSIRDYIE_Msk /*!< LSI Ready Interrupt Enable */
+#define RCC_CIR_LSERDYIE_Pos (9U)
+#define RCC_CIR_LSERDYIE_Msk (0x1U << RCC_CIR_LSERDYIE_Pos) /*!< 0x00000200 */
+#define RCC_CIR_LSERDYIE RCC_CIR_LSERDYIE_Msk /*!< LSE Ready Interrupt Enable */
+#define RCC_CIR_HSIRDYIE_Pos (10U)
+#define RCC_CIR_HSIRDYIE_Msk (0x1U << RCC_CIR_HSIRDYIE_Pos) /*!< 0x00000400 */
+#define RCC_CIR_HSIRDYIE RCC_CIR_HSIRDYIE_Msk /*!< HSI Ready Interrupt Enable */
+#define RCC_CIR_HSERDYIE_Pos (11U)
+#define RCC_CIR_HSERDYIE_Msk (0x1U << RCC_CIR_HSERDYIE_Pos) /*!< 0x00000800 */
+#define RCC_CIR_HSERDYIE RCC_CIR_HSERDYIE_Msk /*!< HSE Ready Interrupt Enable */
+#define RCC_CIR_PLLRDYIE_Pos (12U)
+#define RCC_CIR_PLLRDYIE_Msk (0x1U << RCC_CIR_PLLRDYIE_Pos) /*!< 0x00001000 */
+#define RCC_CIR_PLLRDYIE RCC_CIR_PLLRDYIE_Msk /*!< PLL Ready Interrupt Enable */
+#define RCC_CIR_LSIRDYC_Pos (16U)
+#define RCC_CIR_LSIRDYC_Msk (0x1U << RCC_CIR_LSIRDYC_Pos) /*!< 0x00010000 */
+#define RCC_CIR_LSIRDYC RCC_CIR_LSIRDYC_Msk /*!< LSI Ready Interrupt Clear */
+#define RCC_CIR_LSERDYC_Pos (17U)
+#define RCC_CIR_LSERDYC_Msk (0x1U << RCC_CIR_LSERDYC_Pos) /*!< 0x00020000 */
+#define RCC_CIR_LSERDYC RCC_CIR_LSERDYC_Msk /*!< LSE Ready Interrupt Clear */
+#define RCC_CIR_HSIRDYC_Pos (18U)
+#define RCC_CIR_HSIRDYC_Msk (0x1U << RCC_CIR_HSIRDYC_Pos) /*!< 0x00040000 */
+#define RCC_CIR_HSIRDYC RCC_CIR_HSIRDYC_Msk /*!< HSI Ready Interrupt Clear */
+#define RCC_CIR_HSERDYC_Pos (19U)
+#define RCC_CIR_HSERDYC_Msk (0x1U << RCC_CIR_HSERDYC_Pos) /*!< 0x00080000 */
+#define RCC_CIR_HSERDYC RCC_CIR_HSERDYC_Msk /*!< HSE Ready Interrupt Clear */
+#define RCC_CIR_PLLRDYC_Pos (20U)
+#define RCC_CIR_PLLRDYC_Msk (0x1U << RCC_CIR_PLLRDYC_Pos) /*!< 0x00100000 */
+#define RCC_CIR_PLLRDYC RCC_CIR_PLLRDYC_Msk /*!< PLL Ready Interrupt Clear */
+#define RCC_CIR_CSSC_Pos (23U)
+#define RCC_CIR_CSSC_Msk (0x1U << RCC_CIR_CSSC_Pos) /*!< 0x00800000 */
+#define RCC_CIR_CSSC RCC_CIR_CSSC_Msk /*!< Clock Security System Interrupt Clear */
+
+#define RCC_CIR_PLL2RDYF_Pos (5U)
+#define RCC_CIR_PLL2RDYF_Msk (0x1U << RCC_CIR_PLL2RDYF_Pos) /*!< 0x00000020 */
+#define RCC_CIR_PLL2RDYF RCC_CIR_PLL2RDYF_Msk /*!< PLL2 Ready Interrupt flag */
+#define RCC_CIR_PLL3RDYF_Pos (6U)
+#define RCC_CIR_PLL3RDYF_Msk (0x1U << RCC_CIR_PLL3RDYF_Pos) /*!< 0x00000040 */
+#define RCC_CIR_PLL3RDYF RCC_CIR_PLL3RDYF_Msk /*!< PLL3 Ready Interrupt flag */
+#define RCC_CIR_PLL2RDYIE_Pos (13U)
+#define RCC_CIR_PLL2RDYIE_Msk (0x1U << RCC_CIR_PLL2RDYIE_Pos) /*!< 0x00002000 */
+#define RCC_CIR_PLL2RDYIE RCC_CIR_PLL2RDYIE_Msk /*!< PLL2 Ready Interrupt Enable */
+#define RCC_CIR_PLL3RDYIE_Pos (14U)
+#define RCC_CIR_PLL3RDYIE_Msk (0x1U << RCC_CIR_PLL3RDYIE_Pos) /*!< 0x00004000 */
+#define RCC_CIR_PLL3RDYIE RCC_CIR_PLL3RDYIE_Msk /*!< PLL3 Ready Interrupt Enable */
+#define RCC_CIR_PLL2RDYC_Pos (21U)
+#define RCC_CIR_PLL2RDYC_Msk (0x1U << RCC_CIR_PLL2RDYC_Pos) /*!< 0x00200000 */
+#define RCC_CIR_PLL2RDYC RCC_CIR_PLL2RDYC_Msk /*!< PLL2 Ready Interrupt Clear */
+#define RCC_CIR_PLL3RDYC_Pos (22U)
+#define RCC_CIR_PLL3RDYC_Msk (0x1U << RCC_CIR_PLL3RDYC_Pos) /*!< 0x00400000 */
+#define RCC_CIR_PLL3RDYC RCC_CIR_PLL3RDYC_Msk /*!< PLL3 Ready Interrupt Clear */
+
+/***************** Bit definition for RCC_APB2RSTR register *****************/
+#define RCC_APB2RSTR_AFIORST_Pos (0U)
+#define RCC_APB2RSTR_AFIORST_Msk (0x1U << RCC_APB2RSTR_AFIORST_Pos) /*!< 0x00000001 */
+#define RCC_APB2RSTR_AFIORST RCC_APB2RSTR_AFIORST_Msk /*!< Alternate Function I/O reset */
+#define RCC_APB2RSTR_IOPARST_Pos (2U)
+#define RCC_APB2RSTR_IOPARST_Msk (0x1U << RCC_APB2RSTR_IOPARST_Pos) /*!< 0x00000004 */
+#define RCC_APB2RSTR_IOPARST RCC_APB2RSTR_IOPARST_Msk /*!< I/O port A reset */
+#define RCC_APB2RSTR_IOPBRST_Pos (3U)
+#define RCC_APB2RSTR_IOPBRST_Msk (0x1U << RCC_APB2RSTR_IOPBRST_Pos) /*!< 0x00000008 */
+#define RCC_APB2RSTR_IOPBRST RCC_APB2RSTR_IOPBRST_Msk /*!< I/O port B reset */
+#define RCC_APB2RSTR_IOPCRST_Pos (4U)
+#define RCC_APB2RSTR_IOPCRST_Msk (0x1U << RCC_APB2RSTR_IOPCRST_Pos) /*!< 0x00000010 */
+#define RCC_APB2RSTR_IOPCRST RCC_APB2RSTR_IOPCRST_Msk /*!< I/O port C reset */
+#define RCC_APB2RSTR_IOPDRST_Pos (5U)
+#define RCC_APB2RSTR_IOPDRST_Msk (0x1U << RCC_APB2RSTR_IOPDRST_Pos) /*!< 0x00000020 */
+#define RCC_APB2RSTR_IOPDRST RCC_APB2RSTR_IOPDRST_Msk /*!< I/O port D reset */
+#define RCC_APB2RSTR_ADC1RST_Pos (9U)
+#define RCC_APB2RSTR_ADC1RST_Msk (0x1U << RCC_APB2RSTR_ADC1RST_Pos) /*!< 0x00000200 */
+#define RCC_APB2RSTR_ADC1RST RCC_APB2RSTR_ADC1RST_Msk /*!< ADC 1 interface reset */
+
+#define RCC_APB2RSTR_ADC2RST_Pos (10U)
+#define RCC_APB2RSTR_ADC2RST_Msk (0x1U << RCC_APB2RSTR_ADC2RST_Pos) /*!< 0x00000400 */
+#define RCC_APB2RSTR_ADC2RST RCC_APB2RSTR_ADC2RST_Msk /*!< ADC 2 interface reset */
+
+#define RCC_APB2RSTR_TIM1RST_Pos (11U)
+#define RCC_APB2RSTR_TIM1RST_Msk (0x1U << RCC_APB2RSTR_TIM1RST_Pos) /*!< 0x00000800 */
+#define RCC_APB2RSTR_TIM1RST RCC_APB2RSTR_TIM1RST_Msk /*!< TIM1 Timer reset */
+#define RCC_APB2RSTR_SPI1RST_Pos (12U)
+#define RCC_APB2RSTR_SPI1RST_Msk (0x1U << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */
+#define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk /*!< SPI 1 reset */
+#define RCC_APB2RSTR_USART1RST_Pos (14U)
+#define RCC_APB2RSTR_USART1RST_Msk (0x1U << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00004000 */
+#define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk /*!< USART1 reset */
+
+
+#define RCC_APB2RSTR_IOPERST_Pos (6U)
+#define RCC_APB2RSTR_IOPERST_Msk (0x1U << RCC_APB2RSTR_IOPERST_Pos) /*!< 0x00000040 */
+#define RCC_APB2RSTR_IOPERST RCC_APB2RSTR_IOPERST_Msk /*!< I/O port E reset */
+
+
+
+
+/***************** Bit definition for RCC_APB1RSTR register *****************/
+#define RCC_APB1RSTR_TIM2RST_Pos (0U)
+#define RCC_APB1RSTR_TIM2RST_Msk (0x1U << RCC_APB1RSTR_TIM2RST_Pos) /*!< 0x00000001 */
+#define RCC_APB1RSTR_TIM2RST RCC_APB1RSTR_TIM2RST_Msk /*!< Timer 2 reset */
+#define RCC_APB1RSTR_TIM3RST_Pos (1U)
+#define RCC_APB1RSTR_TIM3RST_Msk (0x1U << RCC_APB1RSTR_TIM3RST_Pos) /*!< 0x00000002 */
+#define RCC_APB1RSTR_TIM3RST RCC_APB1RSTR_TIM3RST_Msk /*!< Timer 3 reset */
+#define RCC_APB1RSTR_WWDGRST_Pos (11U)
+#define RCC_APB1RSTR_WWDGRST_Msk (0x1U << RCC_APB1RSTR_WWDGRST_Pos) /*!< 0x00000800 */
+#define RCC_APB1RSTR_WWDGRST RCC_APB1RSTR_WWDGRST_Msk /*!< Window Watchdog reset */
+#define RCC_APB1RSTR_USART2RST_Pos (17U)
+#define RCC_APB1RSTR_USART2RST_Msk (0x1U << RCC_APB1RSTR_USART2RST_Pos) /*!< 0x00020000 */
+#define RCC_APB1RSTR_USART2RST RCC_APB1RSTR_USART2RST_Msk /*!< USART 2 reset */
+#define RCC_APB1RSTR_I2C1RST_Pos (21U)
+#define RCC_APB1RSTR_I2C1RST_Msk (0x1U << RCC_APB1RSTR_I2C1RST_Pos) /*!< 0x00200000 */
+#define RCC_APB1RSTR_I2C1RST RCC_APB1RSTR_I2C1RST_Msk /*!< I2C 1 reset */
+
+#define RCC_APB1RSTR_CAN1RST_Pos (25U)
+#define RCC_APB1RSTR_CAN1RST_Msk (0x1U << RCC_APB1RSTR_CAN1RST_Pos) /*!< 0x02000000 */
+#define RCC_APB1RSTR_CAN1RST RCC_APB1RSTR_CAN1RST_Msk /*!< CAN1 reset */
+
+#define RCC_APB1RSTR_BKPRST_Pos (27U)
+#define RCC_APB1RSTR_BKPRST_Msk (0x1U << RCC_APB1RSTR_BKPRST_Pos) /*!< 0x08000000 */
+#define RCC_APB1RSTR_BKPRST RCC_APB1RSTR_BKPRST_Msk /*!< Backup interface reset */
+#define RCC_APB1RSTR_PWRRST_Pos (28U)
+#define RCC_APB1RSTR_PWRRST_Msk (0x1U << RCC_APB1RSTR_PWRRST_Pos) /*!< 0x10000000 */
+#define RCC_APB1RSTR_PWRRST RCC_APB1RSTR_PWRRST_Msk /*!< Power interface reset */
+
+#define RCC_APB1RSTR_TIM4RST_Pos (2U)
+#define RCC_APB1RSTR_TIM4RST_Msk (0x1U << RCC_APB1RSTR_TIM4RST_Pos) /*!< 0x00000004 */
+#define RCC_APB1RSTR_TIM4RST RCC_APB1RSTR_TIM4RST_Msk /*!< Timer 4 reset */
+#define RCC_APB1RSTR_SPI2RST_Pos (14U)
+#define RCC_APB1RSTR_SPI2RST_Msk (0x1U << RCC_APB1RSTR_SPI2RST_Pos) /*!< 0x00004000 */
+#define RCC_APB1RSTR_SPI2RST RCC_APB1RSTR_SPI2RST_Msk /*!< SPI 2 reset */
+#define RCC_APB1RSTR_USART3RST_Pos (18U)
+#define RCC_APB1RSTR_USART3RST_Msk (0x1U << RCC_APB1RSTR_USART3RST_Pos) /*!< 0x00040000 */
+#define RCC_APB1RSTR_USART3RST RCC_APB1RSTR_USART3RST_Msk /*!< USART 3 reset */
+#define RCC_APB1RSTR_I2C2RST_Pos (22U)
+#define RCC_APB1RSTR_I2C2RST_Msk (0x1U << RCC_APB1RSTR_I2C2RST_Pos) /*!< 0x00400000 */
+#define RCC_APB1RSTR_I2C2RST RCC_APB1RSTR_I2C2RST_Msk /*!< I2C 2 reset */
+
+
+#define RCC_APB1RSTR_TIM5RST_Pos (3U)
+#define RCC_APB1RSTR_TIM5RST_Msk (0x1U << RCC_APB1RSTR_TIM5RST_Pos) /*!< 0x00000008 */
+#define RCC_APB1RSTR_TIM5RST RCC_APB1RSTR_TIM5RST_Msk /*!< Timer 5 reset */
+#define RCC_APB1RSTR_TIM6RST_Pos (4U)
+#define RCC_APB1RSTR_TIM6RST_Msk (0x1U << RCC_APB1RSTR_TIM6RST_Pos) /*!< 0x00000010 */
+#define RCC_APB1RSTR_TIM6RST RCC_APB1RSTR_TIM6RST_Msk /*!< Timer 6 reset */
+#define RCC_APB1RSTR_TIM7RST_Pos (5U)
+#define RCC_APB1RSTR_TIM7RST_Msk (0x1U << RCC_APB1RSTR_TIM7RST_Pos) /*!< 0x00000020 */
+#define RCC_APB1RSTR_TIM7RST RCC_APB1RSTR_TIM7RST_Msk /*!< Timer 7 reset */
+#define RCC_APB1RSTR_SPI3RST_Pos (15U)
+#define RCC_APB1RSTR_SPI3RST_Msk (0x1U << RCC_APB1RSTR_SPI3RST_Pos) /*!< 0x00008000 */
+#define RCC_APB1RSTR_SPI3RST RCC_APB1RSTR_SPI3RST_Msk /*!< SPI 3 reset */
+#define RCC_APB1RSTR_UART4RST_Pos (19U)
+#define RCC_APB1RSTR_UART4RST_Msk (0x1U << RCC_APB1RSTR_UART4RST_Pos) /*!< 0x00080000 */
+#define RCC_APB1RSTR_UART4RST RCC_APB1RSTR_UART4RST_Msk /*!< UART 4 reset */
+#define RCC_APB1RSTR_UART5RST_Pos (20U)
+#define RCC_APB1RSTR_UART5RST_Msk (0x1U << RCC_APB1RSTR_UART5RST_Pos) /*!< 0x00100000 */
+#define RCC_APB1RSTR_UART5RST RCC_APB1RSTR_UART5RST_Msk /*!< UART 5 reset */
+
+
+
+#define RCC_APB1RSTR_CAN2RST_Pos (26U)
+#define RCC_APB1RSTR_CAN2RST_Msk (0x1U << RCC_APB1RSTR_CAN2RST_Pos) /*!< 0x04000000 */
+#define RCC_APB1RSTR_CAN2RST RCC_APB1RSTR_CAN2RST_Msk /*!< CAN2 reset */
+
+#define RCC_APB1RSTR_DACRST_Pos (29U)
+#define RCC_APB1RSTR_DACRST_Msk (0x1U << RCC_APB1RSTR_DACRST_Pos) /*!< 0x20000000 */
+#define RCC_APB1RSTR_DACRST RCC_APB1RSTR_DACRST_Msk /*!< DAC interface reset */
+
+/****************** Bit definition for RCC_AHBENR register ******************/
+#define RCC_AHBENR_DMA1EN_Pos (0U)
+#define RCC_AHBENR_DMA1EN_Msk (0x1U << RCC_AHBENR_DMA1EN_Pos) /*!< 0x00000001 */
+#define RCC_AHBENR_DMA1EN RCC_AHBENR_DMA1EN_Msk /*!< DMA1 clock enable */
+#define RCC_AHBENR_SRAMEN_Pos (2U)
+#define RCC_AHBENR_SRAMEN_Msk (0x1U << RCC_AHBENR_SRAMEN_Pos) /*!< 0x00000004 */
+#define RCC_AHBENR_SRAMEN RCC_AHBENR_SRAMEN_Msk /*!< SRAM interface clock enable */
+#define RCC_AHBENR_FLITFEN_Pos (4U)
+#define RCC_AHBENR_FLITFEN_Msk (0x1U << RCC_AHBENR_FLITFEN_Pos) /*!< 0x00000010 */
+#define RCC_AHBENR_FLITFEN RCC_AHBENR_FLITFEN_Msk /*!< FLITF clock enable */
+#define RCC_AHBENR_CRCEN_Pos (6U)
+#define RCC_AHBENR_CRCEN_Msk (0x1U << RCC_AHBENR_CRCEN_Pos) /*!< 0x00000040 */
+#define RCC_AHBENR_CRCEN RCC_AHBENR_CRCEN_Msk /*!< CRC clock enable */
+
+#define RCC_AHBENR_DMA2EN_Pos (1U)
+#define RCC_AHBENR_DMA2EN_Msk (0x1U << RCC_AHBENR_DMA2EN_Pos) /*!< 0x00000002 */
+#define RCC_AHBENR_DMA2EN RCC_AHBENR_DMA2EN_Msk /*!< DMA2 clock enable */
+
+
+#define RCC_AHBENR_OTGFSEN_Pos (12U)
+#define RCC_AHBENR_OTGFSEN_Msk (0x1U << RCC_AHBENR_OTGFSEN_Pos) /*!< 0x00001000 */
+#define RCC_AHBENR_OTGFSEN RCC_AHBENR_OTGFSEN_Msk /*!< USB OTG FS clock enable */
+
+/****************** Bit definition for RCC_APB2ENR register *****************/
+#define RCC_APB2ENR_AFIOEN_Pos (0U)
+#define RCC_APB2ENR_AFIOEN_Msk (0x1U << RCC_APB2ENR_AFIOEN_Pos) /*!< 0x00000001 */
+#define RCC_APB2ENR_AFIOEN RCC_APB2ENR_AFIOEN_Msk /*!< Alternate Function I/O clock enable */
+#define RCC_APB2ENR_IOPAEN_Pos (2U)
+#define RCC_APB2ENR_IOPAEN_Msk (0x1U << RCC_APB2ENR_IOPAEN_Pos) /*!< 0x00000004 */
+#define RCC_APB2ENR_IOPAEN RCC_APB2ENR_IOPAEN_Msk /*!< I/O port A clock enable */
+#define RCC_APB2ENR_IOPBEN_Pos (3U)
+#define RCC_APB2ENR_IOPBEN_Msk (0x1U << RCC_APB2ENR_IOPBEN_Pos) /*!< 0x00000008 */
+#define RCC_APB2ENR_IOPBEN RCC_APB2ENR_IOPBEN_Msk /*!< I/O port B clock enable */
+#define RCC_APB2ENR_IOPCEN_Pos (4U)
+#define RCC_APB2ENR_IOPCEN_Msk (0x1U << RCC_APB2ENR_IOPCEN_Pos) /*!< 0x00000010 */
+#define RCC_APB2ENR_IOPCEN RCC_APB2ENR_IOPCEN_Msk /*!< I/O port C clock enable */
+#define RCC_APB2ENR_IOPDEN_Pos (5U)
+#define RCC_APB2ENR_IOPDEN_Msk (0x1U << RCC_APB2ENR_IOPDEN_Pos) /*!< 0x00000020 */
+#define RCC_APB2ENR_IOPDEN RCC_APB2ENR_IOPDEN_Msk /*!< I/O port D clock enable */
+#define RCC_APB2ENR_ADC1EN_Pos (9U)
+#define RCC_APB2ENR_ADC1EN_Msk (0x1U << RCC_APB2ENR_ADC1EN_Pos) /*!< 0x00000200 */
+#define RCC_APB2ENR_ADC1EN RCC_APB2ENR_ADC1EN_Msk /*!< ADC 1 interface clock enable */
+
+#define RCC_APB2ENR_ADC2EN_Pos (10U)
+#define RCC_APB2ENR_ADC2EN_Msk (0x1U << RCC_APB2ENR_ADC2EN_Pos) /*!< 0x00000400 */
+#define RCC_APB2ENR_ADC2EN RCC_APB2ENR_ADC2EN_Msk /*!< ADC 2 interface clock enable */
+
+#define RCC_APB2ENR_TIM1EN_Pos (11U)
+#define RCC_APB2ENR_TIM1EN_Msk (0x1U << RCC_APB2ENR_TIM1EN_Pos) /*!< 0x00000800 */
+#define RCC_APB2ENR_TIM1EN RCC_APB2ENR_TIM1EN_Msk /*!< TIM1 Timer clock enable */
+#define RCC_APB2ENR_SPI1EN_Pos (12U)
+#define RCC_APB2ENR_SPI1EN_Msk (0x1U << RCC_APB2ENR_SPI1EN_Pos) /*!< 0x00001000 */
+#define RCC_APB2ENR_SPI1EN RCC_APB2ENR_SPI1EN_Msk /*!< SPI 1 clock enable */
+#define RCC_APB2ENR_USART1EN_Pos (14U)
+#define RCC_APB2ENR_USART1EN_Msk (0x1U << RCC_APB2ENR_USART1EN_Pos) /*!< 0x00004000 */
+#define RCC_APB2ENR_USART1EN RCC_APB2ENR_USART1EN_Msk /*!< USART1 clock enable */
+
+
+#define RCC_APB2ENR_IOPEEN_Pos (6U)
+#define RCC_APB2ENR_IOPEEN_Msk (0x1U << RCC_APB2ENR_IOPEEN_Pos) /*!< 0x00000040 */
+#define RCC_APB2ENR_IOPEEN RCC_APB2ENR_IOPEEN_Msk /*!< I/O port E clock enable */
+
+
+
+
+/***************** Bit definition for RCC_APB1ENR register ******************/
+#define RCC_APB1ENR_TIM2EN_Pos (0U)
+#define RCC_APB1ENR_TIM2EN_Msk (0x1U << RCC_APB1ENR_TIM2EN_Pos) /*!< 0x00000001 */
+#define RCC_APB1ENR_TIM2EN RCC_APB1ENR_TIM2EN_Msk /*!< Timer 2 clock enabled*/
+#define RCC_APB1ENR_TIM3EN_Pos (1U)
+#define RCC_APB1ENR_TIM3EN_Msk (0x1U << RCC_APB1ENR_TIM3EN_Pos) /*!< 0x00000002 */
+#define RCC_APB1ENR_TIM3EN RCC_APB1ENR_TIM3EN_Msk /*!< Timer 3 clock enable */
+#define RCC_APB1ENR_WWDGEN_Pos (11U)
+#define RCC_APB1ENR_WWDGEN_Msk (0x1U << RCC_APB1ENR_WWDGEN_Pos) /*!< 0x00000800 */
+#define RCC_APB1ENR_WWDGEN RCC_APB1ENR_WWDGEN_Msk /*!< Window Watchdog clock enable */
+#define RCC_APB1ENR_USART2EN_Pos (17U)
+#define RCC_APB1ENR_USART2EN_Msk (0x1U << RCC_APB1ENR_USART2EN_Pos) /*!< 0x00020000 */
+#define RCC_APB1ENR_USART2EN RCC_APB1ENR_USART2EN_Msk /*!< USART 2 clock enable */
+#define RCC_APB1ENR_I2C1EN_Pos (21U)
+#define RCC_APB1ENR_I2C1EN_Msk (0x1U << RCC_APB1ENR_I2C1EN_Pos) /*!< 0x00200000 */
+#define RCC_APB1ENR_I2C1EN RCC_APB1ENR_I2C1EN_Msk /*!< I2C 1 clock enable */
+
+#define RCC_APB1ENR_CAN1EN_Pos (25U)
+#define RCC_APB1ENR_CAN1EN_Msk (0x1U << RCC_APB1ENR_CAN1EN_Pos) /*!< 0x02000000 */
+#define RCC_APB1ENR_CAN1EN RCC_APB1ENR_CAN1EN_Msk /*!< CAN1 clock enable */
+
+#define RCC_APB1ENR_BKPEN_Pos (27U)
+#define RCC_APB1ENR_BKPEN_Msk (0x1U << RCC_APB1ENR_BKPEN_Pos) /*!< 0x08000000 */
+#define RCC_APB1ENR_BKPEN RCC_APB1ENR_BKPEN_Msk /*!< Backup interface clock enable */
+#define RCC_APB1ENR_PWREN_Pos (28U)
+#define RCC_APB1ENR_PWREN_Msk (0x1U << RCC_APB1ENR_PWREN_Pos) /*!< 0x10000000 */
+#define RCC_APB1ENR_PWREN RCC_APB1ENR_PWREN_Msk /*!< Power interface clock enable */
+
+#define RCC_APB1ENR_TIM4EN_Pos (2U)
+#define RCC_APB1ENR_TIM4EN_Msk (0x1U << RCC_APB1ENR_TIM4EN_Pos) /*!< 0x00000004 */
+#define RCC_APB1ENR_TIM4EN RCC_APB1ENR_TIM4EN_Msk /*!< Timer 4 clock enable */
+#define RCC_APB1ENR_SPI2EN_Pos (14U)
+#define RCC_APB1ENR_SPI2EN_Msk (0x1U << RCC_APB1ENR_SPI2EN_Pos) /*!< 0x00004000 */
+#define RCC_APB1ENR_SPI2EN RCC_APB1ENR_SPI2EN_Msk /*!< SPI 2 clock enable */
+#define RCC_APB1ENR_USART3EN_Pos (18U)
+#define RCC_APB1ENR_USART3EN_Msk (0x1U << RCC_APB1ENR_USART3EN_Pos) /*!< 0x00040000 */
+#define RCC_APB1ENR_USART3EN RCC_APB1ENR_USART3EN_Msk /*!< USART 3 clock enable */
+#define RCC_APB1ENR_I2C2EN_Pos (22U)
+#define RCC_APB1ENR_I2C2EN_Msk (0x1U << RCC_APB1ENR_I2C2EN_Pos) /*!< 0x00400000 */
+#define RCC_APB1ENR_I2C2EN RCC_APB1ENR_I2C2EN_Msk /*!< I2C 2 clock enable */
+
+
+#define RCC_APB1ENR_TIM5EN_Pos (3U)
+#define RCC_APB1ENR_TIM5EN_Msk (0x1U << RCC_APB1ENR_TIM5EN_Pos) /*!< 0x00000008 */
+#define RCC_APB1ENR_TIM5EN RCC_APB1ENR_TIM5EN_Msk /*!< Timer 5 clock enable */
+#define RCC_APB1ENR_TIM6EN_Pos (4U)
+#define RCC_APB1ENR_TIM6EN_Msk (0x1U << RCC_APB1ENR_TIM6EN_Pos) /*!< 0x00000010 */
+#define RCC_APB1ENR_TIM6EN RCC_APB1ENR_TIM6EN_Msk /*!< Timer 6 clock enable */
+#define RCC_APB1ENR_TIM7EN_Pos (5U)
+#define RCC_APB1ENR_TIM7EN_Msk (0x1U << RCC_APB1ENR_TIM7EN_Pos) /*!< 0x00000020 */
+#define RCC_APB1ENR_TIM7EN RCC_APB1ENR_TIM7EN_Msk /*!< Timer 7 clock enable */
+#define RCC_APB1ENR_SPI3EN_Pos (15U)
+#define RCC_APB1ENR_SPI3EN_Msk (0x1U << RCC_APB1ENR_SPI3EN_Pos) /*!< 0x00008000 */
+#define RCC_APB1ENR_SPI3EN RCC_APB1ENR_SPI3EN_Msk /*!< SPI 3 clock enable */
+#define RCC_APB1ENR_UART4EN_Pos (19U)
+#define RCC_APB1ENR_UART4EN_Msk (0x1U << RCC_APB1ENR_UART4EN_Pos) /*!< 0x00080000 */
+#define RCC_APB1ENR_UART4EN RCC_APB1ENR_UART4EN_Msk /*!< UART 4 clock enable */
+#define RCC_APB1ENR_UART5EN_Pos (20U)
+#define RCC_APB1ENR_UART5EN_Msk (0x1U << RCC_APB1ENR_UART5EN_Pos) /*!< 0x00100000 */
+#define RCC_APB1ENR_UART5EN RCC_APB1ENR_UART5EN_Msk /*!< UART 5 clock enable */
+
+
+
+#define RCC_APB1ENR_CAN2EN_Pos (26U)
+#define RCC_APB1ENR_CAN2EN_Msk (0x1U << RCC_APB1ENR_CAN2EN_Pos) /*!< 0x04000000 */
+#define RCC_APB1ENR_CAN2EN RCC_APB1ENR_CAN2EN_Msk /*!< CAN2 clock enable */
+
+#define RCC_APB1ENR_DACEN_Pos (29U)
+#define RCC_APB1ENR_DACEN_Msk (0x1U << RCC_APB1ENR_DACEN_Pos) /*!< 0x20000000 */
+#define RCC_APB1ENR_DACEN RCC_APB1ENR_DACEN_Msk /*!< DAC interface clock enable */
+
+/******************* Bit definition for RCC_BDCR register *******************/
+#define RCC_BDCR_LSEON_Pos (0U)
+#define RCC_BDCR_LSEON_Msk (0x1U << RCC_BDCR_LSEON_Pos) /*!< 0x00000001 */
+#define RCC_BDCR_LSEON RCC_BDCR_LSEON_Msk /*!< External Low Speed oscillator enable */
+#define RCC_BDCR_LSERDY_Pos (1U)
+#define RCC_BDCR_LSERDY_Msk (0x1U << RCC_BDCR_LSERDY_Pos) /*!< 0x00000002 */
+#define RCC_BDCR_LSERDY RCC_BDCR_LSERDY_Msk /*!< External Low Speed oscillator Ready */
+#define RCC_BDCR_LSEBYP_Pos (2U)
+#define RCC_BDCR_LSEBYP_Msk (0x1U << RCC_BDCR_LSEBYP_Pos) /*!< 0x00000004 */
+#define RCC_BDCR_LSEBYP RCC_BDCR_LSEBYP_Msk /*!< External Low Speed oscillator Bypass */
+
+#define RCC_BDCR_RTCSEL_Pos (8U)
+#define RCC_BDCR_RTCSEL_Msk (0x3U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000300 */
+#define RCC_BDCR_RTCSEL RCC_BDCR_RTCSEL_Msk /*!< RTCSEL[1:0] bits (RTC clock source selection) */
+#define RCC_BDCR_RTCSEL_0 (0x1U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000100 */
+#define RCC_BDCR_RTCSEL_1 (0x2U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000200 */
+
+/*!< RTC congiguration */
+#define RCC_BDCR_RTCSEL_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */
+#define RCC_BDCR_RTCSEL_LSE ((uint32_t)0x00000100) /*!< LSE oscillator clock used as RTC clock */
+#define RCC_BDCR_RTCSEL_LSI ((uint32_t)0x00000200) /*!< LSI oscillator clock used as RTC clock */
+#define RCC_BDCR_RTCSEL_HSE ((uint32_t)0x00000300) /*!< HSE oscillator clock divided by 128 used as RTC clock */
+
+#define RCC_BDCR_RTCEN_Pos (15U)
+#define RCC_BDCR_RTCEN_Msk (0x1U << RCC_BDCR_RTCEN_Pos) /*!< 0x00008000 */
+#define RCC_BDCR_RTCEN RCC_BDCR_RTCEN_Msk /*!< RTC clock enable */
+#define RCC_BDCR_BDRST_Pos (16U)
+#define RCC_BDCR_BDRST_Msk (0x1U << RCC_BDCR_BDRST_Pos) /*!< 0x00010000 */
+#define RCC_BDCR_BDRST RCC_BDCR_BDRST_Msk /*!< Backup domain software reset */
+
+/******************* Bit definition for RCC_CSR register ********************/
+#define RCC_CSR_LSION_Pos (0U)
+#define RCC_CSR_LSION_Msk (0x1U << RCC_CSR_LSION_Pos) /*!< 0x00000001 */
+#define RCC_CSR_LSION RCC_CSR_LSION_Msk /*!< Internal Low Speed oscillator enable */
+#define RCC_CSR_LSIRDY_Pos (1U)
+#define RCC_CSR_LSIRDY_Msk (0x1U << RCC_CSR_LSIRDY_Pos) /*!< 0x00000002 */
+#define RCC_CSR_LSIRDY RCC_CSR_LSIRDY_Msk /*!< Internal Low Speed oscillator Ready */
+#define RCC_CSR_RMVF_Pos (24U)
+#define RCC_CSR_RMVF_Msk (0x1U << RCC_CSR_RMVF_Pos) /*!< 0x01000000 */
+#define RCC_CSR_RMVF RCC_CSR_RMVF_Msk /*!< Remove reset flag */
+#define RCC_CSR_PINRSTF_Pos (26U)
+#define RCC_CSR_PINRSTF_Msk (0x1U << RCC_CSR_PINRSTF_Pos) /*!< 0x04000000 */
+#define RCC_CSR_PINRSTF RCC_CSR_PINRSTF_Msk /*!< PIN reset flag */
+#define RCC_CSR_PORRSTF_Pos (27U)
+#define RCC_CSR_PORRSTF_Msk (0x1U << RCC_CSR_PORRSTF_Pos) /*!< 0x08000000 */
+#define RCC_CSR_PORRSTF RCC_CSR_PORRSTF_Msk /*!< POR/PDR reset flag */
+#define RCC_CSR_SFTRSTF_Pos (28U)
+#define RCC_CSR_SFTRSTF_Msk (0x1U << RCC_CSR_SFTRSTF_Pos) /*!< 0x10000000 */
+#define RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF_Msk /*!< Software Reset flag */
+#define RCC_CSR_IWDGRSTF_Pos (29U)
+#define RCC_CSR_IWDGRSTF_Msk (0x1U << RCC_CSR_IWDGRSTF_Pos) /*!< 0x20000000 */
+#define RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF_Msk /*!< Independent Watchdog reset flag */
+#define RCC_CSR_WWDGRSTF_Pos (30U)
+#define RCC_CSR_WWDGRSTF_Msk (0x1U << RCC_CSR_WWDGRSTF_Pos) /*!< 0x40000000 */
+#define RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF_Msk /*!< Window watchdog reset flag */
+#define RCC_CSR_LPWRRSTF_Pos (31U)
+#define RCC_CSR_LPWRRSTF_Msk (0x1U << RCC_CSR_LPWRRSTF_Pos) /*!< 0x80000000 */
+#define RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF_Msk /*!< Low-Power reset flag */
+
+/******************* Bit definition for RCC_AHBRSTR register ****************/
+#define RCC_AHBRSTR_OTGFSRST_Pos (12U)
+#define RCC_AHBRSTR_OTGFSRST_Msk (0x1U << RCC_AHBRSTR_OTGFSRST_Pos) /*!< 0x00001000 */
+#define RCC_AHBRSTR_OTGFSRST RCC_AHBRSTR_OTGFSRST_Msk /*!< USB OTG FS reset */
+
+/******************* Bit definition for RCC_CFGR2 register ******************/
+/*!< PREDIV1 configuration */
+#define RCC_CFGR2_PREDIV1_Pos (0U)
+#define RCC_CFGR2_PREDIV1_Msk (0xFU << RCC_CFGR2_PREDIV1_Pos) /*!< 0x0000000F */
+#define RCC_CFGR2_PREDIV1 RCC_CFGR2_PREDIV1_Msk /*!< PREDIV1[3:0] bits */
+#define RCC_CFGR2_PREDIV1_0 (0x1U << RCC_CFGR2_PREDIV1_Pos) /*!< 0x00000001 */
+#define RCC_CFGR2_PREDIV1_1 (0x2U << RCC_CFGR2_PREDIV1_Pos) /*!< 0x00000002 */
+#define RCC_CFGR2_PREDIV1_2 (0x4U << RCC_CFGR2_PREDIV1_Pos) /*!< 0x00000004 */
+#define RCC_CFGR2_PREDIV1_3 (0x8U << RCC_CFGR2_PREDIV1_Pos) /*!< 0x00000008 */
+
+#define RCC_CFGR2_PREDIV1_DIV1 ((uint32_t)0x00000000) /*!< PREDIV1 input clock not divided */
+#define RCC_CFGR2_PREDIV1_DIV2_Pos (0U)
+#define RCC_CFGR2_PREDIV1_DIV2_Msk (0x1U << RCC_CFGR2_PREDIV1_DIV2_Pos) /*!< 0x00000001 */
+#define RCC_CFGR2_PREDIV1_DIV2 RCC_CFGR2_PREDIV1_DIV2_Msk /*!< PREDIV1 input clock divided by 2 */
+#define RCC_CFGR2_PREDIV1_DIV3_Pos (1U)
+#define RCC_CFGR2_PREDIV1_DIV3_Msk (0x1U << RCC_CFGR2_PREDIV1_DIV3_Pos) /*!< 0x00000002 */
+#define RCC_CFGR2_PREDIV1_DIV3 RCC_CFGR2_PREDIV1_DIV3_Msk /*!< PREDIV1 input clock divided by 3 */
+#define RCC_CFGR2_PREDIV1_DIV4_Pos (0U)
+#define RCC_CFGR2_PREDIV1_DIV4_Msk (0x3U << RCC_CFGR2_PREDIV1_DIV4_Pos) /*!< 0x00000003 */
+#define RCC_CFGR2_PREDIV1_DIV4 RCC_CFGR2_PREDIV1_DIV4_Msk /*!< PREDIV1 input clock divided by 4 */
+#define RCC_CFGR2_PREDIV1_DIV5_Pos (2U)
+#define RCC_CFGR2_PREDIV1_DIV5_Msk (0x1U << RCC_CFGR2_PREDIV1_DIV5_Pos) /*!< 0x00000004 */
+#define RCC_CFGR2_PREDIV1_DIV5 RCC_CFGR2_PREDIV1_DIV5_Msk /*!< PREDIV1 input clock divided by 5 */
+#define RCC_CFGR2_PREDIV1_DIV6_Pos (0U)
+#define RCC_CFGR2_PREDIV1_DIV6_Msk (0x5U << RCC_CFGR2_PREDIV1_DIV6_Pos) /*!< 0x00000005 */
+#define RCC_CFGR2_PREDIV1_DIV6 RCC_CFGR2_PREDIV1_DIV6_Msk /*!< PREDIV1 input clock divided by 6 */
+#define RCC_CFGR2_PREDIV1_DIV7_Pos (1U)
+#define RCC_CFGR2_PREDIV1_DIV7_Msk (0x3U << RCC_CFGR2_PREDIV1_DIV7_Pos) /*!< 0x00000006 */
+#define RCC_CFGR2_PREDIV1_DIV7 RCC_CFGR2_PREDIV1_DIV7_Msk /*!< PREDIV1 input clock divided by 7 */
+#define RCC_CFGR2_PREDIV1_DIV8_Pos (0U)
+#define RCC_CFGR2_PREDIV1_DIV8_Msk (0x7U << RCC_CFGR2_PREDIV1_DIV8_Pos) /*!< 0x00000007 */
+#define RCC_CFGR2_PREDIV1_DIV8 RCC_CFGR2_PREDIV1_DIV8_Msk /*!< PREDIV1 input clock divided by 8 */
+#define RCC_CFGR2_PREDIV1_DIV9_Pos (3U)
+#define RCC_CFGR2_PREDIV1_DIV9_Msk (0x1U << RCC_CFGR2_PREDIV1_DIV9_Pos) /*!< 0x00000008 */
+#define RCC_CFGR2_PREDIV1_DIV9 RCC_CFGR2_PREDIV1_DIV9_Msk /*!< PREDIV1 input clock divided by 9 */
+#define RCC_CFGR2_PREDIV1_DIV10_Pos (0U)
+#define RCC_CFGR2_PREDIV1_DIV10_Msk (0x9U << RCC_CFGR2_PREDIV1_DIV10_Pos) /*!< 0x00000009 */
+#define RCC_CFGR2_PREDIV1_DIV10 RCC_CFGR2_PREDIV1_DIV10_Msk /*!< PREDIV1 input clock divided by 10 */
+#define RCC_CFGR2_PREDIV1_DIV11_Pos (1U)
+#define RCC_CFGR2_PREDIV1_DIV11_Msk (0x5U << RCC_CFGR2_PREDIV1_DIV11_Pos) /*!< 0x0000000A */
+#define RCC_CFGR2_PREDIV1_DIV11 RCC_CFGR2_PREDIV1_DIV11_Msk /*!< PREDIV1 input clock divided by 11 */
+#define RCC_CFGR2_PREDIV1_DIV12_Pos (0U)
+#define RCC_CFGR2_PREDIV1_DIV12_Msk (0xBU << RCC_CFGR2_PREDIV1_DIV12_Pos) /*!< 0x0000000B */
+#define RCC_CFGR2_PREDIV1_DIV12 RCC_CFGR2_PREDIV1_DIV12_Msk /*!< PREDIV1 input clock divided by 12 */
+#define RCC_CFGR2_PREDIV1_DIV13_Pos (2U)
+#define RCC_CFGR2_PREDIV1_DIV13_Msk (0x3U << RCC_CFGR2_PREDIV1_DIV13_Pos) /*!< 0x0000000C */
+#define RCC_CFGR2_PREDIV1_DIV13 RCC_CFGR2_PREDIV1_DIV13_Msk /*!< PREDIV1 input clock divided by 13 */
+#define RCC_CFGR2_PREDIV1_DIV14_Pos (0U)
+#define RCC_CFGR2_PREDIV1_DIV14_Msk (0xDU << RCC_CFGR2_PREDIV1_DIV14_Pos) /*!< 0x0000000D */
+#define RCC_CFGR2_PREDIV1_DIV14 RCC_CFGR2_PREDIV1_DIV14_Msk /*!< PREDIV1 input clock divided by 14 */
+#define RCC_CFGR2_PREDIV1_DIV15_Pos (1U)
+#define RCC_CFGR2_PREDIV1_DIV15_Msk (0x7U << RCC_CFGR2_PREDIV1_DIV15_Pos) /*!< 0x0000000E */
+#define RCC_CFGR2_PREDIV1_DIV15 RCC_CFGR2_PREDIV1_DIV15_Msk /*!< PREDIV1 input clock divided by 15 */
+#define RCC_CFGR2_PREDIV1_DIV16_Pos (0U)
+#define RCC_CFGR2_PREDIV1_DIV16_Msk (0xFU << RCC_CFGR2_PREDIV1_DIV16_Pos) /*!< 0x0000000F */
+#define RCC_CFGR2_PREDIV1_DIV16 RCC_CFGR2_PREDIV1_DIV16_Msk /*!< PREDIV1 input clock divided by 16 */
+
+/*!< PREDIV2 configuration */
+#define RCC_CFGR2_PREDIV2_Pos (4U)
+#define RCC_CFGR2_PREDIV2_Msk (0xFU << RCC_CFGR2_PREDIV2_Pos) /*!< 0x000000F0 */
+#define RCC_CFGR2_PREDIV2 RCC_CFGR2_PREDIV2_Msk /*!< PREDIV2[3:0] bits */
+#define RCC_CFGR2_PREDIV2_0 (0x1U << RCC_CFGR2_PREDIV2_Pos) /*!< 0x00000010 */
+#define RCC_CFGR2_PREDIV2_1 (0x2U << RCC_CFGR2_PREDIV2_Pos) /*!< 0x00000020 */
+#define RCC_CFGR2_PREDIV2_2 (0x4U << RCC_CFGR2_PREDIV2_Pos) /*!< 0x00000040 */
+#define RCC_CFGR2_PREDIV2_3 (0x8U << RCC_CFGR2_PREDIV2_Pos) /*!< 0x00000080 */
+
+#define RCC_CFGR2_PREDIV2_DIV1 ((uint32_t)0x00000000) /*!< PREDIV2 input clock not divided */
+#define RCC_CFGR2_PREDIV2_DIV2_Pos (4U)
+#define RCC_CFGR2_PREDIV2_DIV2_Msk (0x1U << RCC_CFGR2_PREDIV2_DIV2_Pos) /*!< 0x00000010 */
+#define RCC_CFGR2_PREDIV2_DIV2 RCC_CFGR2_PREDIV2_DIV2_Msk /*!< PREDIV2 input clock divided by 2 */
+#define RCC_CFGR2_PREDIV2_DIV3_Pos (5U)
+#define RCC_CFGR2_PREDIV2_DIV3_Msk (0x1U << RCC_CFGR2_PREDIV2_DIV3_Pos) /*!< 0x00000020 */
+#define RCC_CFGR2_PREDIV2_DIV3 RCC_CFGR2_PREDIV2_DIV3_Msk /*!< PREDIV2 input clock divided by 3 */
+#define RCC_CFGR2_PREDIV2_DIV4_Pos (4U)
+#define RCC_CFGR2_PREDIV2_DIV4_Msk (0x3U << RCC_CFGR2_PREDIV2_DIV4_Pos) /*!< 0x00000030 */
+#define RCC_CFGR2_PREDIV2_DIV4 RCC_CFGR2_PREDIV2_DIV4_Msk /*!< PREDIV2 input clock divided by 4 */
+#define RCC_CFGR2_PREDIV2_DIV5_Pos (6U)
+#define RCC_CFGR2_PREDIV2_DIV5_Msk (0x1U << RCC_CFGR2_PREDIV2_DIV5_Pos) /*!< 0x00000040 */
+#define RCC_CFGR2_PREDIV2_DIV5 RCC_CFGR2_PREDIV2_DIV5_Msk /*!< PREDIV2 input clock divided by 5 */
+#define RCC_CFGR2_PREDIV2_DIV6_Pos (4U)
+#define RCC_CFGR2_PREDIV2_DIV6_Msk (0x5U << RCC_CFGR2_PREDIV2_DIV6_Pos) /*!< 0x00000050 */
+#define RCC_CFGR2_PREDIV2_DIV6 RCC_CFGR2_PREDIV2_DIV6_Msk /*!< PREDIV2 input clock divided by 6 */
+#define RCC_CFGR2_PREDIV2_DIV7_Pos (5U)
+#define RCC_CFGR2_PREDIV2_DIV7_Msk (0x3U << RCC_CFGR2_PREDIV2_DIV7_Pos) /*!< 0x00000060 */
+#define RCC_CFGR2_PREDIV2_DIV7 RCC_CFGR2_PREDIV2_DIV7_Msk /*!< PREDIV2 input clock divided by 7 */
+#define RCC_CFGR2_PREDIV2_DIV8_Pos (4U)
+#define RCC_CFGR2_PREDIV2_DIV8_Msk (0x7U << RCC_CFGR2_PREDIV2_DIV8_Pos) /*!< 0x00000070 */
+#define RCC_CFGR2_PREDIV2_DIV8 RCC_CFGR2_PREDIV2_DIV8_Msk /*!< PREDIV2 input clock divided by 8 */
+#define RCC_CFGR2_PREDIV2_DIV9_Pos (7U)
+#define RCC_CFGR2_PREDIV2_DIV9_Msk (0x1U << RCC_CFGR2_PREDIV2_DIV9_Pos) /*!< 0x00000080 */
+#define RCC_CFGR2_PREDIV2_DIV9 RCC_CFGR2_PREDIV2_DIV9_Msk /*!< PREDIV2 input clock divided by 9 */
+#define RCC_CFGR2_PREDIV2_DIV10_Pos (4U)
+#define RCC_CFGR2_PREDIV2_DIV10_Msk (0x9U << RCC_CFGR2_PREDIV2_DIV10_Pos) /*!< 0x00000090 */
+#define RCC_CFGR2_PREDIV2_DIV10 RCC_CFGR2_PREDIV2_DIV10_Msk /*!< PREDIV2 input clock divided by 10 */
+#define RCC_CFGR2_PREDIV2_DIV11_Pos (5U)
+#define RCC_CFGR2_PREDIV2_DIV11_Msk (0x5U << RCC_CFGR2_PREDIV2_DIV11_Pos) /*!< 0x000000A0 */
+#define RCC_CFGR2_PREDIV2_DIV11 RCC_CFGR2_PREDIV2_DIV11_Msk /*!< PREDIV2 input clock divided by 11 */
+#define RCC_CFGR2_PREDIV2_DIV12_Pos (4U)
+#define RCC_CFGR2_PREDIV2_DIV12_Msk (0xBU << RCC_CFGR2_PREDIV2_DIV12_Pos) /*!< 0x000000B0 */
+#define RCC_CFGR2_PREDIV2_DIV12 RCC_CFGR2_PREDIV2_DIV12_Msk /*!< PREDIV2 input clock divided by 12 */
+#define RCC_CFGR2_PREDIV2_DIV13_Pos (6U)
+#define RCC_CFGR2_PREDIV2_DIV13_Msk (0x3U << RCC_CFGR2_PREDIV2_DIV13_Pos) /*!< 0x000000C0 */
+#define RCC_CFGR2_PREDIV2_DIV13 RCC_CFGR2_PREDIV2_DIV13_Msk /*!< PREDIV2 input clock divided by 13 */
+#define RCC_CFGR2_PREDIV2_DIV14_Pos (4U)
+#define RCC_CFGR2_PREDIV2_DIV14_Msk (0xDU << RCC_CFGR2_PREDIV2_DIV14_Pos) /*!< 0x000000D0 */
+#define RCC_CFGR2_PREDIV2_DIV14 RCC_CFGR2_PREDIV2_DIV14_Msk /*!< PREDIV2 input clock divided by 14 */
+#define RCC_CFGR2_PREDIV2_DIV15_Pos (5U)
+#define RCC_CFGR2_PREDIV2_DIV15_Msk (0x7U << RCC_CFGR2_PREDIV2_DIV15_Pos) /*!< 0x000000E0 */
+#define RCC_CFGR2_PREDIV2_DIV15 RCC_CFGR2_PREDIV2_DIV15_Msk /*!< PREDIV2 input clock divided by 15 */
+#define RCC_CFGR2_PREDIV2_DIV16_Pos (4U)
+#define RCC_CFGR2_PREDIV2_DIV16_Msk (0xFU << RCC_CFGR2_PREDIV2_DIV16_Pos) /*!< 0x000000F0 */
+#define RCC_CFGR2_PREDIV2_DIV16 RCC_CFGR2_PREDIV2_DIV16_Msk /*!< PREDIV2 input clock divided by 16 */
+
+/*!< PLL2MUL configuration */
+#define RCC_CFGR2_PLL2MUL_Pos (8U)
+#define RCC_CFGR2_PLL2MUL_Msk (0xFU << RCC_CFGR2_PLL2MUL_Pos) /*!< 0x00000F00 */
+#define RCC_CFGR2_PLL2MUL RCC_CFGR2_PLL2MUL_Msk /*!< PLL2MUL[3:0] bits */
+#define RCC_CFGR2_PLL2MUL_0 (0x1U << RCC_CFGR2_PLL2MUL_Pos) /*!< 0x00000100 */
+#define RCC_CFGR2_PLL2MUL_1 (0x2U << RCC_CFGR2_PLL2MUL_Pos) /*!< 0x00000200 */
+#define RCC_CFGR2_PLL2MUL_2 (0x4U << RCC_CFGR2_PLL2MUL_Pos) /*!< 0x00000400 */
+#define RCC_CFGR2_PLL2MUL_3 (0x8U << RCC_CFGR2_PLL2MUL_Pos) /*!< 0x00000800 */
+
+#define RCC_CFGR2_PLL2MUL8_Pos (9U)
+#define RCC_CFGR2_PLL2MUL8_Msk (0x3U << RCC_CFGR2_PLL2MUL8_Pos) /*!< 0x00000600 */
+#define RCC_CFGR2_PLL2MUL8 RCC_CFGR2_PLL2MUL8_Msk /*!< PLL2 input clock * 8 */
+#define RCC_CFGR2_PLL2MUL9_Pos (8U)
+#define RCC_CFGR2_PLL2MUL9_Msk (0x7U << RCC_CFGR2_PLL2MUL9_Pos) /*!< 0x00000700 */
+#define RCC_CFGR2_PLL2MUL9 RCC_CFGR2_PLL2MUL9_Msk /*!< PLL2 input clock * 9 */
+#define RCC_CFGR2_PLL2MUL10_Pos (11U)
+#define RCC_CFGR2_PLL2MUL10_Msk (0x1U << RCC_CFGR2_PLL2MUL10_Pos) /*!< 0x00000800 */
+#define RCC_CFGR2_PLL2MUL10 RCC_CFGR2_PLL2MUL10_Msk /*!< PLL2 input clock * 10 */
+#define RCC_CFGR2_PLL2MUL11_Pos (8U)
+#define RCC_CFGR2_PLL2MUL11_Msk (0x9U << RCC_CFGR2_PLL2MUL11_Pos) /*!< 0x00000900 */
+#define RCC_CFGR2_PLL2MUL11 RCC_CFGR2_PLL2MUL11_Msk /*!< PLL2 input clock * 11 */
+#define RCC_CFGR2_PLL2MUL12_Pos (9U)
+#define RCC_CFGR2_PLL2MUL12_Msk (0x5U << RCC_CFGR2_PLL2MUL12_Pos) /*!< 0x00000A00 */
+#define RCC_CFGR2_PLL2MUL12 RCC_CFGR2_PLL2MUL12_Msk /*!< PLL2 input clock * 12 */
+#define RCC_CFGR2_PLL2MUL13_Pos (8U)
+#define RCC_CFGR2_PLL2MUL13_Msk (0xBU << RCC_CFGR2_PLL2MUL13_Pos) /*!< 0x00000B00 */
+#define RCC_CFGR2_PLL2MUL13 RCC_CFGR2_PLL2MUL13_Msk /*!< PLL2 input clock * 13 */
+#define RCC_CFGR2_PLL2MUL14_Pos (10U)
+#define RCC_CFGR2_PLL2MUL14_Msk (0x3U << RCC_CFGR2_PLL2MUL14_Pos) /*!< 0x00000C00 */
+#define RCC_CFGR2_PLL2MUL14 RCC_CFGR2_PLL2MUL14_Msk /*!< PLL2 input clock * 14 */
+#define RCC_CFGR2_PLL2MUL16_Pos (9U)
+#define RCC_CFGR2_PLL2MUL16_Msk (0x7U << RCC_CFGR2_PLL2MUL16_Pos) /*!< 0x00000E00 */
+#define RCC_CFGR2_PLL2MUL16 RCC_CFGR2_PLL2MUL16_Msk /*!< PLL2 input clock * 16 */
+#define RCC_CFGR2_PLL2MUL20_Pos (8U)
+#define RCC_CFGR2_PLL2MUL20_Msk (0xFU << RCC_CFGR2_PLL2MUL20_Pos) /*!< 0x00000F00 */
+#define RCC_CFGR2_PLL2MUL20 RCC_CFGR2_PLL2MUL20_Msk /*!< PLL2 input clock * 20 */
+
+/*!< PLL3MUL configuration */
+#define RCC_CFGR2_PLL3MUL_Pos (12U)
+#define RCC_CFGR2_PLL3MUL_Msk (0xFU << RCC_CFGR2_PLL3MUL_Pos) /*!< 0x0000F000 */
+#define RCC_CFGR2_PLL3MUL RCC_CFGR2_PLL3MUL_Msk /*!< PLL3MUL[3:0] bits */
+#define RCC_CFGR2_PLL3MUL_0 (0x1U << RCC_CFGR2_PLL3MUL_Pos) /*!< 0x00001000 */
+#define RCC_CFGR2_PLL3MUL_1 (0x2U << RCC_CFGR2_PLL3MUL_Pos) /*!< 0x00002000 */
+#define RCC_CFGR2_PLL3MUL_2 (0x4U << RCC_CFGR2_PLL3MUL_Pos) /*!< 0x00004000 */
+#define RCC_CFGR2_PLL3MUL_3 (0x8U << RCC_CFGR2_PLL3MUL_Pos) /*!< 0x00008000 */
+
+#define RCC_CFGR2_PLL3MUL8_Pos (13U)
+#define RCC_CFGR2_PLL3MUL8_Msk (0x3U << RCC_CFGR2_PLL3MUL8_Pos) /*!< 0x00006000 */
+#define RCC_CFGR2_PLL3MUL8 RCC_CFGR2_PLL3MUL8_Msk /*!< PLL3 input clock * 8 */
+#define RCC_CFGR2_PLL3MUL9_Pos (12U)
+#define RCC_CFGR2_PLL3MUL9_Msk (0x7U << RCC_CFGR2_PLL3MUL9_Pos) /*!< 0x00007000 */
+#define RCC_CFGR2_PLL3MUL9 RCC_CFGR2_PLL3MUL9_Msk /*!< PLL3 input clock * 9 */
+#define RCC_CFGR2_PLL3MUL10_Pos (15U)
+#define RCC_CFGR2_PLL3MUL10_Msk (0x1U << RCC_CFGR2_PLL3MUL10_Pos) /*!< 0x00008000 */
+#define RCC_CFGR2_PLL3MUL10 RCC_CFGR2_PLL3MUL10_Msk /*!< PLL3 input clock * 10 */
+#define RCC_CFGR2_PLL3MUL11_Pos (12U)
+#define RCC_CFGR2_PLL3MUL11_Msk (0x9U << RCC_CFGR2_PLL3MUL11_Pos) /*!< 0x00009000 */
+#define RCC_CFGR2_PLL3MUL11 RCC_CFGR2_PLL3MUL11_Msk /*!< PLL3 input clock * 11 */
+#define RCC_CFGR2_PLL3MUL12_Pos (13U)
+#define RCC_CFGR2_PLL3MUL12_Msk (0x5U << RCC_CFGR2_PLL3MUL12_Pos) /*!< 0x0000A000 */
+#define RCC_CFGR2_PLL3MUL12 RCC_CFGR2_PLL3MUL12_Msk /*!< PLL3 input clock * 12 */
+#define RCC_CFGR2_PLL3MUL13_Pos (12U)
+#define RCC_CFGR2_PLL3MUL13_Msk (0xBU << RCC_CFGR2_PLL3MUL13_Pos) /*!< 0x0000B000 */
+#define RCC_CFGR2_PLL3MUL13 RCC_CFGR2_PLL3MUL13_Msk /*!< PLL3 input clock * 13 */
+#define RCC_CFGR2_PLL3MUL14_Pos (14U)
+#define RCC_CFGR2_PLL3MUL14_Msk (0x3U << RCC_CFGR2_PLL3MUL14_Pos) /*!< 0x0000C000 */
+#define RCC_CFGR2_PLL3MUL14 RCC_CFGR2_PLL3MUL14_Msk /*!< PLL3 input clock * 14 */
+#define RCC_CFGR2_PLL3MUL16_Pos (13U)
+#define RCC_CFGR2_PLL3MUL16_Msk (0x7U << RCC_CFGR2_PLL3MUL16_Pos) /*!< 0x0000E000 */
+#define RCC_CFGR2_PLL3MUL16 RCC_CFGR2_PLL3MUL16_Msk /*!< PLL3 input clock * 16 */
+#define RCC_CFGR2_PLL3MUL20_Pos (12U)
+#define RCC_CFGR2_PLL3MUL20_Msk (0xFU << RCC_CFGR2_PLL3MUL20_Pos) /*!< 0x0000F000 */
+#define RCC_CFGR2_PLL3MUL20 RCC_CFGR2_PLL3MUL20_Msk /*!< PLL3 input clock * 20 */
+
+#define RCC_CFGR2_PREDIV1SRC_Pos (16U)
+#define RCC_CFGR2_PREDIV1SRC_Msk (0x1U << RCC_CFGR2_PREDIV1SRC_Pos) /*!< 0x00010000 */
+#define RCC_CFGR2_PREDIV1SRC RCC_CFGR2_PREDIV1SRC_Msk /*!< PREDIV1 entry clock source */
+#define RCC_CFGR2_PREDIV1SRC_PLL2_Pos (16U)
+#define RCC_CFGR2_PREDIV1SRC_PLL2_Msk (0x1U << RCC_CFGR2_PREDIV1SRC_PLL2_Pos) /*!< 0x00010000 */
+#define RCC_CFGR2_PREDIV1SRC_PLL2 RCC_CFGR2_PREDIV1SRC_PLL2_Msk /*!< PLL2 selected as PREDIV1 entry clock source */
+#define RCC_CFGR2_PREDIV1SRC_HSE ((uint32_t)0x00000000) /*!< HSE selected as PREDIV1 entry clock source */
+#define RCC_CFGR2_I2S2SRC_Pos (17U)
+#define RCC_CFGR2_I2S2SRC_Msk (0x1U << RCC_CFGR2_I2S2SRC_Pos) /*!< 0x00020000 */
+#define RCC_CFGR2_I2S2SRC RCC_CFGR2_I2S2SRC_Msk /*!< I2S2 entry clock source */
+#define RCC_CFGR2_I2S3SRC_Pos (18U)
+#define RCC_CFGR2_I2S3SRC_Msk (0x1U << RCC_CFGR2_I2S3SRC_Pos) /*!< 0x00040000 */
+#define RCC_CFGR2_I2S3SRC RCC_CFGR2_I2S3SRC_Msk /*!< I2S3 clock source */
+
+
+/******************************************************************************/
+/* */
+/* General Purpose and Alternate Function I/O */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for GPIO_CRL register *******************/
+#define GPIO_CRL_MODE_Pos (0U)
+#define GPIO_CRL_MODE_Msk (0x33333333U << GPIO_CRL_MODE_Pos) /*!< 0x33333333 */
+#define GPIO_CRL_MODE GPIO_CRL_MODE_Msk /*!< Port x mode bits */
+
+#define GPIO_CRL_MODE0_Pos (0U)
+#define GPIO_CRL_MODE0_Msk (0x3U << GPIO_CRL_MODE0_Pos) /*!< 0x00000003 */
+#define GPIO_CRL_MODE0 GPIO_CRL_MODE0_Msk /*!< MODE0[1:0] bits (Port x mode bits, pin 0) */
+#define GPIO_CRL_MODE0_0 (0x1U << GPIO_CRL_MODE0_Pos) /*!< 0x00000001 */
+#define GPIO_CRL_MODE0_1 (0x2U << GPIO_CRL_MODE0_Pos) /*!< 0x00000002 */
+
+#define GPIO_CRL_MODE1_Pos (4U)
+#define GPIO_CRL_MODE1_Msk (0x3U << GPIO_CRL_MODE1_Pos) /*!< 0x00000030 */
+#define GPIO_CRL_MODE1 GPIO_CRL_MODE1_Msk /*!< MODE1[1:0] bits (Port x mode bits, pin 1) */
+#define GPIO_CRL_MODE1_0 (0x1U << GPIO_CRL_MODE1_Pos) /*!< 0x00000010 */
+#define GPIO_CRL_MODE1_1 (0x2U << GPIO_CRL_MODE1_Pos) /*!< 0x00000020 */
+
+#define GPIO_CRL_MODE2_Pos (8U)
+#define GPIO_CRL_MODE2_Msk (0x3U << GPIO_CRL_MODE2_Pos) /*!< 0x00000300 */
+#define GPIO_CRL_MODE2 GPIO_CRL_MODE2_Msk /*!< MODE2[1:0] bits (Port x mode bits, pin 2) */
+#define GPIO_CRL_MODE2_0 (0x1U << GPIO_CRL_MODE2_Pos) /*!< 0x00000100 */
+#define GPIO_CRL_MODE2_1 (0x2U << GPIO_CRL_MODE2_Pos) /*!< 0x00000200 */
+
+#define GPIO_CRL_MODE3_Pos (12U)
+#define GPIO_CRL_MODE3_Msk (0x3U << GPIO_CRL_MODE3_Pos) /*!< 0x00003000 */
+#define GPIO_CRL_MODE3 GPIO_CRL_MODE3_Msk /*!< MODE3[1:0] bits (Port x mode bits, pin 3) */
+#define GPIO_CRL_MODE3_0 (0x1U << GPIO_CRL_MODE3_Pos) /*!< 0x00001000 */
+#define GPIO_CRL_MODE3_1 (0x2U << GPIO_CRL_MODE3_Pos) /*!< 0x00002000 */
+
+#define GPIO_CRL_MODE4_Pos (16U)
+#define GPIO_CRL_MODE4_Msk (0x3U << GPIO_CRL_MODE4_Pos) /*!< 0x00030000 */
+#define GPIO_CRL_MODE4 GPIO_CRL_MODE4_Msk /*!< MODE4[1:0] bits (Port x mode bits, pin 4) */
+#define GPIO_CRL_MODE4_0 (0x1U << GPIO_CRL_MODE4_Pos) /*!< 0x00010000 */
+#define GPIO_CRL_MODE4_1 (0x2U << GPIO_CRL_MODE4_Pos) /*!< 0x00020000 */
+
+#define GPIO_CRL_MODE5_Pos (20U)
+#define GPIO_CRL_MODE5_Msk (0x3U << GPIO_CRL_MODE5_Pos) /*!< 0x00300000 */
+#define GPIO_CRL_MODE5 GPIO_CRL_MODE5_Msk /*!< MODE5[1:0] bits (Port x mode bits, pin 5) */
+#define GPIO_CRL_MODE5_0 (0x1U << GPIO_CRL_MODE5_Pos) /*!< 0x00100000 */
+#define GPIO_CRL_MODE5_1 (0x2U << GPIO_CRL_MODE5_Pos) /*!< 0x00200000 */
+
+#define GPIO_CRL_MODE6_Pos (24U)
+#define GPIO_CRL_MODE6_Msk (0x3U << GPIO_CRL_MODE6_Pos) /*!< 0x03000000 */
+#define GPIO_CRL_MODE6 GPIO_CRL_MODE6_Msk /*!< MODE6[1:0] bits (Port x mode bits, pin 6) */
+#define GPIO_CRL_MODE6_0 (0x1U << GPIO_CRL_MODE6_Pos) /*!< 0x01000000 */
+#define GPIO_CRL_MODE6_1 (0x2U << GPIO_CRL_MODE6_Pos) /*!< 0x02000000 */
+
+#define GPIO_CRL_MODE7_Pos (28U)
+#define GPIO_CRL_MODE7_Msk (0x3U << GPIO_CRL_MODE7_Pos) /*!< 0x30000000 */
+#define GPIO_CRL_MODE7 GPIO_CRL_MODE7_Msk /*!< MODE7[1:0] bits (Port x mode bits, pin 7) */
+#define GPIO_CRL_MODE7_0 (0x1U << GPIO_CRL_MODE7_Pos) /*!< 0x10000000 */
+#define GPIO_CRL_MODE7_1 (0x2U << GPIO_CRL_MODE7_Pos) /*!< 0x20000000 */
+
+#define GPIO_CRL_CNF_Pos (2U)
+#define GPIO_CRL_CNF_Msk (0x33333333U << GPIO_CRL_CNF_Pos) /*!< 0xCCCCCCCC */
+#define GPIO_CRL_CNF GPIO_CRL_CNF_Msk /*!< Port x configuration bits */
+
+#define GPIO_CRL_CNF0_Pos (2U)
+#define GPIO_CRL_CNF0_Msk (0x3U << GPIO_CRL_CNF0_Pos) /*!< 0x0000000C */
+#define GPIO_CRL_CNF0 GPIO_CRL_CNF0_Msk /*!< CNF0[1:0] bits (Port x configuration bits, pin 0) */
+#define GPIO_CRL_CNF0_0 (0x1U << GPIO_CRL_CNF0_Pos) /*!< 0x00000004 */
+#define GPIO_CRL_CNF0_1 (0x2U << GPIO_CRL_CNF0_Pos) /*!< 0x00000008 */
+
+#define GPIO_CRL_CNF1_Pos (6U)
+#define GPIO_CRL_CNF1_Msk (0x3U << GPIO_CRL_CNF1_Pos) /*!< 0x000000C0 */
+#define GPIO_CRL_CNF1 GPIO_CRL_CNF1_Msk /*!< CNF1[1:0] bits (Port x configuration bits, pin 1) */
+#define GPIO_CRL_CNF1_0 (0x1U << GPIO_CRL_CNF1_Pos) /*!< 0x00000040 */
+#define GPIO_CRL_CNF1_1 (0x2U << GPIO_CRL_CNF1_Pos) /*!< 0x00000080 */
+
+#define GPIO_CRL_CNF2_Pos (10U)
+#define GPIO_CRL_CNF2_Msk (0x3U << GPIO_CRL_CNF2_Pos) /*!< 0x00000C00 */
+#define GPIO_CRL_CNF2 GPIO_CRL_CNF2_Msk /*!< CNF2[1:0] bits (Port x configuration bits, pin 2) */
+#define GPIO_CRL_CNF2_0 (0x1U << GPIO_CRL_CNF2_Pos) /*!< 0x00000400 */
+#define GPIO_CRL_CNF2_1 (0x2U << GPIO_CRL_CNF2_Pos) /*!< 0x00000800 */
+
+#define GPIO_CRL_CNF3_Pos (14U)
+#define GPIO_CRL_CNF3_Msk (0x3U << GPIO_CRL_CNF3_Pos) /*!< 0x0000C000 */
+#define GPIO_CRL_CNF3 GPIO_CRL_CNF3_Msk /*!< CNF3[1:0] bits (Port x configuration bits, pin 3) */
+#define GPIO_CRL_CNF3_0 (0x1U << GPIO_CRL_CNF3_Pos) /*!< 0x00004000 */
+#define GPIO_CRL_CNF3_1 (0x2U << GPIO_CRL_CNF3_Pos) /*!< 0x00008000 */
+
+#define GPIO_CRL_CNF4_Pos (18U)
+#define GPIO_CRL_CNF4_Msk (0x3U << GPIO_CRL_CNF4_Pos) /*!< 0x000C0000 */
+#define GPIO_CRL_CNF4 GPIO_CRL_CNF4_Msk /*!< CNF4[1:0] bits (Port x configuration bits, pin 4) */
+#define GPIO_CRL_CNF4_0 (0x1U << GPIO_CRL_CNF4_Pos) /*!< 0x00040000 */
+#define GPIO_CRL_CNF4_1 (0x2U << GPIO_CRL_CNF4_Pos) /*!< 0x00080000 */
+
+#define GPIO_CRL_CNF5_Pos (22U)
+#define GPIO_CRL_CNF5_Msk (0x3U << GPIO_CRL_CNF5_Pos) /*!< 0x00C00000 */
+#define GPIO_CRL_CNF5 GPIO_CRL_CNF5_Msk /*!< CNF5[1:0] bits (Port x configuration bits, pin 5) */
+#define GPIO_CRL_CNF5_0 (0x1U << GPIO_CRL_CNF5_Pos) /*!< 0x00400000 */
+#define GPIO_CRL_CNF5_1 (0x2U << GPIO_CRL_CNF5_Pos) /*!< 0x00800000 */
+
+#define GPIO_CRL_CNF6_Pos (26U)
+#define GPIO_CRL_CNF6_Msk (0x3U << GPIO_CRL_CNF6_Pos) /*!< 0x0C000000 */
+#define GPIO_CRL_CNF6 GPIO_CRL_CNF6_Msk /*!< CNF6[1:0] bits (Port x configuration bits, pin 6) */
+#define GPIO_CRL_CNF6_0 (0x1U << GPIO_CRL_CNF6_Pos) /*!< 0x04000000 */
+#define GPIO_CRL_CNF6_1 (0x2U << GPIO_CRL_CNF6_Pos) /*!< 0x08000000 */
+
+#define GPIO_CRL_CNF7_Pos (30U)
+#define GPIO_CRL_CNF7_Msk (0x3U << GPIO_CRL_CNF7_Pos) /*!< 0xC0000000 */
+#define GPIO_CRL_CNF7 GPIO_CRL_CNF7_Msk /*!< CNF7[1:0] bits (Port x configuration bits, pin 7) */
+#define GPIO_CRL_CNF7_0 (0x1U << GPIO_CRL_CNF7_Pos) /*!< 0x40000000 */
+#define GPIO_CRL_CNF7_1 (0x2U << GPIO_CRL_CNF7_Pos) /*!< 0x80000000 */
+
+/******************* Bit definition for GPIO_CRH register *******************/
+#define GPIO_CRH_MODE_Pos (0U)
+#define GPIO_CRH_MODE_Msk (0x33333333U << GPIO_CRH_MODE_Pos) /*!< 0x33333333 */
+#define GPIO_CRH_MODE GPIO_CRH_MODE_Msk /*!< Port x mode bits */
+
+#define GPIO_CRH_MODE8_Pos (0U)
+#define GPIO_CRH_MODE8_Msk (0x3U << GPIO_CRH_MODE8_Pos) /*!< 0x00000003 */
+#define GPIO_CRH_MODE8 GPIO_CRH_MODE8_Msk /*!< MODE8[1:0] bits (Port x mode bits, pin 8) */
+#define GPIO_CRH_MODE8_0 (0x1U << GPIO_CRH_MODE8_Pos) /*!< 0x00000001 */
+#define GPIO_CRH_MODE8_1 (0x2U << GPIO_CRH_MODE8_Pos) /*!< 0x00000002 */
+
+#define GPIO_CRH_MODE9_Pos (4U)
+#define GPIO_CRH_MODE9_Msk (0x3U << GPIO_CRH_MODE9_Pos) /*!< 0x00000030 */
+#define GPIO_CRH_MODE9 GPIO_CRH_MODE9_Msk /*!< MODE9[1:0] bits (Port x mode bits, pin 9) */
+#define GPIO_CRH_MODE9_0 (0x1U << GPIO_CRH_MODE9_Pos) /*!< 0x00000010 */
+#define GPIO_CRH_MODE9_1 (0x2U << GPIO_CRH_MODE9_Pos) /*!< 0x00000020 */
+
+#define GPIO_CRH_MODE10_Pos (8U)
+#define GPIO_CRH_MODE10_Msk (0x3U << GPIO_CRH_MODE10_Pos) /*!< 0x00000300 */
+#define GPIO_CRH_MODE10 GPIO_CRH_MODE10_Msk /*!< MODE10[1:0] bits (Port x mode bits, pin 10) */
+#define GPIO_CRH_MODE10_0 (0x1U << GPIO_CRH_MODE10_Pos) /*!< 0x00000100 */
+#define GPIO_CRH_MODE10_1 (0x2U << GPIO_CRH_MODE10_Pos) /*!< 0x00000200 */
+
+#define GPIO_CRH_MODE11_Pos (12U)
+#define GPIO_CRH_MODE11_Msk (0x3U << GPIO_CRH_MODE11_Pos) /*!< 0x00003000 */
+#define GPIO_CRH_MODE11 GPIO_CRH_MODE11_Msk /*!< MODE11[1:0] bits (Port x mode bits, pin 11) */
+#define GPIO_CRH_MODE11_0 (0x1U << GPIO_CRH_MODE11_Pos) /*!< 0x00001000 */
+#define GPIO_CRH_MODE11_1 (0x2U << GPIO_CRH_MODE11_Pos) /*!< 0x00002000 */
+
+#define GPIO_CRH_MODE12_Pos (16U)
+#define GPIO_CRH_MODE12_Msk (0x3U << GPIO_CRH_MODE12_Pos) /*!< 0x00030000 */
+#define GPIO_CRH_MODE12 GPIO_CRH_MODE12_Msk /*!< MODE12[1:0] bits (Port x mode bits, pin 12) */
+#define GPIO_CRH_MODE12_0 (0x1U << GPIO_CRH_MODE12_Pos) /*!< 0x00010000 */
+#define GPIO_CRH_MODE12_1 (0x2U << GPIO_CRH_MODE12_Pos) /*!< 0x00020000 */
+
+#define GPIO_CRH_MODE13_Pos (20U)
+#define GPIO_CRH_MODE13_Msk (0x3U << GPIO_CRH_MODE13_Pos) /*!< 0x00300000 */
+#define GPIO_CRH_MODE13 GPIO_CRH_MODE13_Msk /*!< MODE13[1:0] bits (Port x mode bits, pin 13) */
+#define GPIO_CRH_MODE13_0 (0x1U << GPIO_CRH_MODE13_Pos) /*!< 0x00100000 */
+#define GPIO_CRH_MODE13_1 (0x2U << GPIO_CRH_MODE13_Pos) /*!< 0x00200000 */
+
+#define GPIO_CRH_MODE14_Pos (24U)
+#define GPIO_CRH_MODE14_Msk (0x3U << GPIO_CRH_MODE14_Pos) /*!< 0x03000000 */
+#define GPIO_CRH_MODE14 GPIO_CRH_MODE14_Msk /*!< MODE14[1:0] bits (Port x mode bits, pin 14) */
+#define GPIO_CRH_MODE14_0 (0x1U << GPIO_CRH_MODE14_Pos) /*!< 0x01000000 */
+#define GPIO_CRH_MODE14_1 (0x2U << GPIO_CRH_MODE14_Pos) /*!< 0x02000000 */
+
+#define GPIO_CRH_MODE15_Pos (28U)
+#define GPIO_CRH_MODE15_Msk (0x3U << GPIO_CRH_MODE15_Pos) /*!< 0x30000000 */
+#define GPIO_CRH_MODE15 GPIO_CRH_MODE15_Msk /*!< MODE15[1:0] bits (Port x mode bits, pin 15) */
+#define GPIO_CRH_MODE15_0 (0x1U << GPIO_CRH_MODE15_Pos) /*!< 0x10000000 */
+#define GPIO_CRH_MODE15_1 (0x2U << GPIO_CRH_MODE15_Pos) /*!< 0x20000000 */
+
+#define GPIO_CRH_CNF_Pos (2U)
+#define GPIO_CRH_CNF_Msk (0x33333333U << GPIO_CRH_CNF_Pos) /*!< 0xCCCCCCCC */
+#define GPIO_CRH_CNF GPIO_CRH_CNF_Msk /*!< Port x configuration bits */
+
+#define GPIO_CRH_CNF8_Pos (2U)
+#define GPIO_CRH_CNF8_Msk (0x3U << GPIO_CRH_CNF8_Pos) /*!< 0x0000000C */
+#define GPIO_CRH_CNF8 GPIO_CRH_CNF8_Msk /*!< CNF8[1:0] bits (Port x configuration bits, pin 8) */
+#define GPIO_CRH_CNF8_0 (0x1U << GPIO_CRH_CNF8_Pos) /*!< 0x00000004 */
+#define GPIO_CRH_CNF8_1 (0x2U << GPIO_CRH_CNF8_Pos) /*!< 0x00000008 */
+
+#define GPIO_CRH_CNF9_Pos (6U)
+#define GPIO_CRH_CNF9_Msk (0x3U << GPIO_CRH_CNF9_Pos) /*!< 0x000000C0 */
+#define GPIO_CRH_CNF9 GPIO_CRH_CNF9_Msk /*!< CNF9[1:0] bits (Port x configuration bits, pin 9) */
+#define GPIO_CRH_CNF9_0 (0x1U << GPIO_CRH_CNF9_Pos) /*!< 0x00000040 */
+#define GPIO_CRH_CNF9_1 (0x2U << GPIO_CRH_CNF9_Pos) /*!< 0x00000080 */
+
+#define GPIO_CRH_CNF10_Pos (10U)
+#define GPIO_CRH_CNF10_Msk (0x3U << GPIO_CRH_CNF10_Pos) /*!< 0x00000C00 */
+#define GPIO_CRH_CNF10 GPIO_CRH_CNF10_Msk /*!< CNF10[1:0] bits (Port x configuration bits, pin 10) */
+#define GPIO_CRH_CNF10_0 (0x1U << GPIO_CRH_CNF10_Pos) /*!< 0x00000400 */
+#define GPIO_CRH_CNF10_1 (0x2U << GPIO_CRH_CNF10_Pos) /*!< 0x00000800 */
+
+#define GPIO_CRH_CNF11_Pos (14U)
+#define GPIO_CRH_CNF11_Msk (0x3U << GPIO_CRH_CNF11_Pos) /*!< 0x0000C000 */
+#define GPIO_CRH_CNF11 GPIO_CRH_CNF11_Msk /*!< CNF11[1:0] bits (Port x configuration bits, pin 11) */
+#define GPIO_CRH_CNF11_0 (0x1U << GPIO_CRH_CNF11_Pos) /*!< 0x00004000 */
+#define GPIO_CRH_CNF11_1 (0x2U << GPIO_CRH_CNF11_Pos) /*!< 0x00008000 */
+
+#define GPIO_CRH_CNF12_Pos (18U)
+#define GPIO_CRH_CNF12_Msk (0x3U << GPIO_CRH_CNF12_Pos) /*!< 0x000C0000 */
+#define GPIO_CRH_CNF12 GPIO_CRH_CNF12_Msk /*!< CNF12[1:0] bits (Port x configuration bits, pin 12) */
+#define GPIO_CRH_CNF12_0 (0x1U << GPIO_CRH_CNF12_Pos) /*!< 0x00040000 */
+#define GPIO_CRH_CNF12_1 (0x2U << GPIO_CRH_CNF12_Pos) /*!< 0x00080000 */
+
+#define GPIO_CRH_CNF13_Pos (22U)
+#define GPIO_CRH_CNF13_Msk (0x3U << GPIO_CRH_CNF13_Pos) /*!< 0x00C00000 */
+#define GPIO_CRH_CNF13 GPIO_CRH_CNF13_Msk /*!< CNF13[1:0] bits (Port x configuration bits, pin 13) */
+#define GPIO_CRH_CNF13_0 (0x1U << GPIO_CRH_CNF13_Pos) /*!< 0x00400000 */
+#define GPIO_CRH_CNF13_1 (0x2U << GPIO_CRH_CNF13_Pos) /*!< 0x00800000 */
+
+#define GPIO_CRH_CNF14_Pos (26U)
+#define GPIO_CRH_CNF14_Msk (0x3U << GPIO_CRH_CNF14_Pos) /*!< 0x0C000000 */
+#define GPIO_CRH_CNF14 GPIO_CRH_CNF14_Msk /*!< CNF14[1:0] bits (Port x configuration bits, pin 14) */
+#define GPIO_CRH_CNF14_0 (0x1U << GPIO_CRH_CNF14_Pos) /*!< 0x04000000 */
+#define GPIO_CRH_CNF14_1 (0x2U << GPIO_CRH_CNF14_Pos) /*!< 0x08000000 */
+
+#define GPIO_CRH_CNF15_Pos (30U)
+#define GPIO_CRH_CNF15_Msk (0x3U << GPIO_CRH_CNF15_Pos) /*!< 0xC0000000 */
+#define GPIO_CRH_CNF15 GPIO_CRH_CNF15_Msk /*!< CNF15[1:0] bits (Port x configuration bits, pin 15) */
+#define GPIO_CRH_CNF15_0 (0x1U << GPIO_CRH_CNF15_Pos) /*!< 0x40000000 */
+#define GPIO_CRH_CNF15_1 (0x2U << GPIO_CRH_CNF15_Pos) /*!< 0x80000000 */
+
+/*!<****************** Bit definition for GPIO_IDR register *******************/
+#define GPIO_IDR_IDR0_Pos (0U)
+#define GPIO_IDR_IDR0_Msk (0x1U << GPIO_IDR_IDR0_Pos) /*!< 0x00000001 */
+#define GPIO_IDR_IDR0 GPIO_IDR_IDR0_Msk /*!< Port input data, bit 0 */
+#define GPIO_IDR_IDR1_Pos (1U)
+#define GPIO_IDR_IDR1_Msk (0x1U << GPIO_IDR_IDR1_Pos) /*!< 0x00000002 */
+#define GPIO_IDR_IDR1 GPIO_IDR_IDR1_Msk /*!< Port input data, bit 1 */
+#define GPIO_IDR_IDR2_Pos (2U)
+#define GPIO_IDR_IDR2_Msk (0x1U << GPIO_IDR_IDR2_Pos) /*!< 0x00000004 */
+#define GPIO_IDR_IDR2 GPIO_IDR_IDR2_Msk /*!< Port input data, bit 2 */
+#define GPIO_IDR_IDR3_Pos (3U)
+#define GPIO_IDR_IDR3_Msk (0x1U << GPIO_IDR_IDR3_Pos) /*!< 0x00000008 */
+#define GPIO_IDR_IDR3 GPIO_IDR_IDR3_Msk /*!< Port input data, bit 3 */
+#define GPIO_IDR_IDR4_Pos (4U)
+#define GPIO_IDR_IDR4_Msk (0x1U << GPIO_IDR_IDR4_Pos) /*!< 0x00000010 */
+#define GPIO_IDR_IDR4 GPIO_IDR_IDR4_Msk /*!< Port input data, bit 4 */
+#define GPIO_IDR_IDR5_Pos (5U)
+#define GPIO_IDR_IDR5_Msk (0x1U << GPIO_IDR_IDR5_Pos) /*!< 0x00000020 */
+#define GPIO_IDR_IDR5 GPIO_IDR_IDR5_Msk /*!< Port input data, bit 5 */
+#define GPIO_IDR_IDR6_Pos (6U)
+#define GPIO_IDR_IDR6_Msk (0x1U << GPIO_IDR_IDR6_Pos) /*!< 0x00000040 */
+#define GPIO_IDR_IDR6 GPIO_IDR_IDR6_Msk /*!< Port input data, bit 6 */
+#define GPIO_IDR_IDR7_Pos (7U)
+#define GPIO_IDR_IDR7_Msk (0x1U << GPIO_IDR_IDR7_Pos) /*!< 0x00000080 */
+#define GPIO_IDR_IDR7 GPIO_IDR_IDR7_Msk /*!< Port input data, bit 7 */
+#define GPIO_IDR_IDR8_Pos (8U)
+#define GPIO_IDR_IDR8_Msk (0x1U << GPIO_IDR_IDR8_Pos) /*!< 0x00000100 */
+#define GPIO_IDR_IDR8 GPIO_IDR_IDR8_Msk /*!< Port input data, bit 8 */
+#define GPIO_IDR_IDR9_Pos (9U)
+#define GPIO_IDR_IDR9_Msk (0x1U << GPIO_IDR_IDR9_Pos) /*!< 0x00000200 */
+#define GPIO_IDR_IDR9 GPIO_IDR_IDR9_Msk /*!< Port input data, bit 9 */
+#define GPIO_IDR_IDR10_Pos (10U)
+#define GPIO_IDR_IDR10_Msk (0x1U << GPIO_IDR_IDR10_Pos) /*!< 0x00000400 */
+#define GPIO_IDR_IDR10 GPIO_IDR_IDR10_Msk /*!< Port input data, bit 10 */
+#define GPIO_IDR_IDR11_Pos (11U)
+#define GPIO_IDR_IDR11_Msk (0x1U << GPIO_IDR_IDR11_Pos) /*!< 0x00000800 */
+#define GPIO_IDR_IDR11 GPIO_IDR_IDR11_Msk /*!< Port input data, bit 11 */
+#define GPIO_IDR_IDR12_Pos (12U)
+#define GPIO_IDR_IDR12_Msk (0x1U << GPIO_IDR_IDR12_Pos) /*!< 0x00001000 */
+#define GPIO_IDR_IDR12 GPIO_IDR_IDR12_Msk /*!< Port input data, bit 12 */
+#define GPIO_IDR_IDR13_Pos (13U)
+#define GPIO_IDR_IDR13_Msk (0x1U << GPIO_IDR_IDR13_Pos) /*!< 0x00002000 */
+#define GPIO_IDR_IDR13 GPIO_IDR_IDR13_Msk /*!< Port input data, bit 13 */
+#define GPIO_IDR_IDR14_Pos (14U)
+#define GPIO_IDR_IDR14_Msk (0x1U << GPIO_IDR_IDR14_Pos) /*!< 0x00004000 */
+#define GPIO_IDR_IDR14 GPIO_IDR_IDR14_Msk /*!< Port input data, bit 14 */
+#define GPIO_IDR_IDR15_Pos (15U)
+#define GPIO_IDR_IDR15_Msk (0x1U << GPIO_IDR_IDR15_Pos) /*!< 0x00008000 */
+#define GPIO_IDR_IDR15 GPIO_IDR_IDR15_Msk /*!< Port input data, bit 15 */
+
+/******************* Bit definition for GPIO_ODR register *******************/
+#define GPIO_ODR_ODR0_Pos (0U)
+#define GPIO_ODR_ODR0_Msk (0x1U << GPIO_ODR_ODR0_Pos) /*!< 0x00000001 */
+#define GPIO_ODR_ODR0 GPIO_ODR_ODR0_Msk /*!< Port output data, bit 0 */
+#define GPIO_ODR_ODR1_Pos (1U)
+#define GPIO_ODR_ODR1_Msk (0x1U << GPIO_ODR_ODR1_Pos) /*!< 0x00000002 */
+#define GPIO_ODR_ODR1 GPIO_ODR_ODR1_Msk /*!< Port output data, bit 1 */
+#define GPIO_ODR_ODR2_Pos (2U)
+#define GPIO_ODR_ODR2_Msk (0x1U << GPIO_ODR_ODR2_Pos) /*!< 0x00000004 */
+#define GPIO_ODR_ODR2 GPIO_ODR_ODR2_Msk /*!< Port output data, bit 2 */
+#define GPIO_ODR_ODR3_Pos (3U)
+#define GPIO_ODR_ODR3_Msk (0x1U << GPIO_ODR_ODR3_Pos) /*!< 0x00000008 */
+#define GPIO_ODR_ODR3 GPIO_ODR_ODR3_Msk /*!< Port output data, bit 3 */
+#define GPIO_ODR_ODR4_Pos (4U)
+#define GPIO_ODR_ODR4_Msk (0x1U << GPIO_ODR_ODR4_Pos) /*!< 0x00000010 */
+#define GPIO_ODR_ODR4 GPIO_ODR_ODR4_Msk /*!< Port output data, bit 4 */
+#define GPIO_ODR_ODR5_Pos (5U)
+#define GPIO_ODR_ODR5_Msk (0x1U << GPIO_ODR_ODR5_Pos) /*!< 0x00000020 */
+#define GPIO_ODR_ODR5 GPIO_ODR_ODR5_Msk /*!< Port output data, bit 5 */
+#define GPIO_ODR_ODR6_Pos (6U)
+#define GPIO_ODR_ODR6_Msk (0x1U << GPIO_ODR_ODR6_Pos) /*!< 0x00000040 */
+#define GPIO_ODR_ODR6 GPIO_ODR_ODR6_Msk /*!< Port output data, bit 6 */
+#define GPIO_ODR_ODR7_Pos (7U)
+#define GPIO_ODR_ODR7_Msk (0x1U << GPIO_ODR_ODR7_Pos) /*!< 0x00000080 */
+#define GPIO_ODR_ODR7 GPIO_ODR_ODR7_Msk /*!< Port output data, bit 7 */
+#define GPIO_ODR_ODR8_Pos (8U)
+#define GPIO_ODR_ODR8_Msk (0x1U << GPIO_ODR_ODR8_Pos) /*!< 0x00000100 */
+#define GPIO_ODR_ODR8 GPIO_ODR_ODR8_Msk /*!< Port output data, bit 8 */
+#define GPIO_ODR_ODR9_Pos (9U)
+#define GPIO_ODR_ODR9_Msk (0x1U << GPIO_ODR_ODR9_Pos) /*!< 0x00000200 */
+#define GPIO_ODR_ODR9 GPIO_ODR_ODR9_Msk /*!< Port output data, bit 9 */
+#define GPIO_ODR_ODR10_Pos (10U)
+#define GPIO_ODR_ODR10_Msk (0x1U << GPIO_ODR_ODR10_Pos) /*!< 0x00000400 */
+#define GPIO_ODR_ODR10 GPIO_ODR_ODR10_Msk /*!< Port output data, bit 10 */
+#define GPIO_ODR_ODR11_Pos (11U)
+#define GPIO_ODR_ODR11_Msk (0x1U << GPIO_ODR_ODR11_Pos) /*!< 0x00000800 */
+#define GPIO_ODR_ODR11 GPIO_ODR_ODR11_Msk /*!< Port output data, bit 11 */
+#define GPIO_ODR_ODR12_Pos (12U)
+#define GPIO_ODR_ODR12_Msk (0x1U << GPIO_ODR_ODR12_Pos) /*!< 0x00001000 */
+#define GPIO_ODR_ODR12 GPIO_ODR_ODR12_Msk /*!< Port output data, bit 12 */
+#define GPIO_ODR_ODR13_Pos (13U)
+#define GPIO_ODR_ODR13_Msk (0x1U << GPIO_ODR_ODR13_Pos) /*!< 0x00002000 */
+#define GPIO_ODR_ODR13 GPIO_ODR_ODR13_Msk /*!< Port output data, bit 13 */
+#define GPIO_ODR_ODR14_Pos (14U)
+#define GPIO_ODR_ODR14_Msk (0x1U << GPIO_ODR_ODR14_Pos) /*!< 0x00004000 */
+#define GPIO_ODR_ODR14 GPIO_ODR_ODR14_Msk /*!< Port output data, bit 14 */
+#define GPIO_ODR_ODR15_Pos (15U)
+#define GPIO_ODR_ODR15_Msk (0x1U << GPIO_ODR_ODR15_Pos) /*!< 0x00008000 */
+#define GPIO_ODR_ODR15 GPIO_ODR_ODR15_Msk /*!< Port output data, bit 15 */
+
+/****************** Bit definition for GPIO_BSRR register *******************/
+#define GPIO_BSRR_BS0_Pos (0U)
+#define GPIO_BSRR_BS0_Msk (0x1U << GPIO_BSRR_BS0_Pos) /*!< 0x00000001 */
+#define GPIO_BSRR_BS0 GPIO_BSRR_BS0_Msk /*!< Port x Set bit 0 */
+#define GPIO_BSRR_BS1_Pos (1U)
+#define GPIO_BSRR_BS1_Msk (0x1U << GPIO_BSRR_BS1_Pos) /*!< 0x00000002 */
+#define GPIO_BSRR_BS1 GPIO_BSRR_BS1_Msk /*!< Port x Set bit 1 */
+#define GPIO_BSRR_BS2_Pos (2U)
+#define GPIO_BSRR_BS2_Msk (0x1U << GPIO_BSRR_BS2_Pos) /*!< 0x00000004 */
+#define GPIO_BSRR_BS2 GPIO_BSRR_BS2_Msk /*!< Port x Set bit 2 */
+#define GPIO_BSRR_BS3_Pos (3U)
+#define GPIO_BSRR_BS3_Msk (0x1U << GPIO_BSRR_BS3_Pos) /*!< 0x00000008 */
+#define GPIO_BSRR_BS3 GPIO_BSRR_BS3_Msk /*!< Port x Set bit 3 */
+#define GPIO_BSRR_BS4_Pos (4U)
+#define GPIO_BSRR_BS4_Msk (0x1U << GPIO_BSRR_BS4_Pos) /*!< 0x00000010 */
+#define GPIO_BSRR_BS4 GPIO_BSRR_BS4_Msk /*!< Port x Set bit 4 */
+#define GPIO_BSRR_BS5_Pos (5U)
+#define GPIO_BSRR_BS5_Msk (0x1U << GPIO_BSRR_BS5_Pos) /*!< 0x00000020 */
+#define GPIO_BSRR_BS5 GPIO_BSRR_BS5_Msk /*!< Port x Set bit 5 */
+#define GPIO_BSRR_BS6_Pos (6U)
+#define GPIO_BSRR_BS6_Msk (0x1U << GPIO_BSRR_BS6_Pos) /*!< 0x00000040 */
+#define GPIO_BSRR_BS6 GPIO_BSRR_BS6_Msk /*!< Port x Set bit 6 */
+#define GPIO_BSRR_BS7_Pos (7U)
+#define GPIO_BSRR_BS7_Msk (0x1U << GPIO_BSRR_BS7_Pos) /*!< 0x00000080 */
+#define GPIO_BSRR_BS7 GPIO_BSRR_BS7_Msk /*!< Port x Set bit 7 */
+#define GPIO_BSRR_BS8_Pos (8U)
+#define GPIO_BSRR_BS8_Msk (0x1U << GPIO_BSRR_BS8_Pos) /*!< 0x00000100 */
+#define GPIO_BSRR_BS8 GPIO_BSRR_BS8_Msk /*!< Port x Set bit 8 */
+#define GPIO_BSRR_BS9_Pos (9U)
+#define GPIO_BSRR_BS9_Msk (0x1U << GPIO_BSRR_BS9_Pos) /*!< 0x00000200 */
+#define GPIO_BSRR_BS9 GPIO_BSRR_BS9_Msk /*!< Port x Set bit 9 */
+#define GPIO_BSRR_BS10_Pos (10U)
+#define GPIO_BSRR_BS10_Msk (0x1U << GPIO_BSRR_BS10_Pos) /*!< 0x00000400 */
+#define GPIO_BSRR_BS10 GPIO_BSRR_BS10_Msk /*!< Port x Set bit 10 */
+#define GPIO_BSRR_BS11_Pos (11U)
+#define GPIO_BSRR_BS11_Msk (0x1U << GPIO_BSRR_BS11_Pos) /*!< 0x00000800 */
+#define GPIO_BSRR_BS11 GPIO_BSRR_BS11_Msk /*!< Port x Set bit 11 */
+#define GPIO_BSRR_BS12_Pos (12U)
+#define GPIO_BSRR_BS12_Msk (0x1U << GPIO_BSRR_BS12_Pos) /*!< 0x00001000 */
+#define GPIO_BSRR_BS12 GPIO_BSRR_BS12_Msk /*!< Port x Set bit 12 */
+#define GPIO_BSRR_BS13_Pos (13U)
+#define GPIO_BSRR_BS13_Msk (0x1U << GPIO_BSRR_BS13_Pos) /*!< 0x00002000 */
+#define GPIO_BSRR_BS13 GPIO_BSRR_BS13_Msk /*!< Port x Set bit 13 */
+#define GPIO_BSRR_BS14_Pos (14U)
+#define GPIO_BSRR_BS14_Msk (0x1U << GPIO_BSRR_BS14_Pos) /*!< 0x00004000 */
+#define GPIO_BSRR_BS14 GPIO_BSRR_BS14_Msk /*!< Port x Set bit 14 */
+#define GPIO_BSRR_BS15_Pos (15U)
+#define GPIO_BSRR_BS15_Msk (0x1U << GPIO_BSRR_BS15_Pos) /*!< 0x00008000 */
+#define GPIO_BSRR_BS15 GPIO_BSRR_BS15_Msk /*!< Port x Set bit 15 */
+
+#define GPIO_BSRR_BR0_Pos (16U)
+#define GPIO_BSRR_BR0_Msk (0x1U << GPIO_BSRR_BR0_Pos) /*!< 0x00010000 */
+#define GPIO_BSRR_BR0 GPIO_BSRR_BR0_Msk /*!< Port x Reset bit 0 */
+#define GPIO_BSRR_BR1_Pos (17U)
+#define GPIO_BSRR_BR1_Msk (0x1U << GPIO_BSRR_BR1_Pos) /*!< 0x00020000 */
+#define GPIO_BSRR_BR1 GPIO_BSRR_BR1_Msk /*!< Port x Reset bit 1 */
+#define GPIO_BSRR_BR2_Pos (18U)
+#define GPIO_BSRR_BR2_Msk (0x1U << GPIO_BSRR_BR2_Pos) /*!< 0x00040000 */
+#define GPIO_BSRR_BR2 GPIO_BSRR_BR2_Msk /*!< Port x Reset bit 2 */
+#define GPIO_BSRR_BR3_Pos (19U)
+#define GPIO_BSRR_BR3_Msk (0x1U << GPIO_BSRR_BR3_Pos) /*!< 0x00080000 */
+#define GPIO_BSRR_BR3 GPIO_BSRR_BR3_Msk /*!< Port x Reset bit 3 */
+#define GPIO_BSRR_BR4_Pos (20U)
+#define GPIO_BSRR_BR4_Msk (0x1U << GPIO_BSRR_BR4_Pos) /*!< 0x00100000 */
+#define GPIO_BSRR_BR4 GPIO_BSRR_BR4_Msk /*!< Port x Reset bit 4 */
+#define GPIO_BSRR_BR5_Pos (21U)
+#define GPIO_BSRR_BR5_Msk (0x1U << GPIO_BSRR_BR5_Pos) /*!< 0x00200000 */
+#define GPIO_BSRR_BR5 GPIO_BSRR_BR5_Msk /*!< Port x Reset bit 5 */
+#define GPIO_BSRR_BR6_Pos (22U)
+#define GPIO_BSRR_BR6_Msk (0x1U << GPIO_BSRR_BR6_Pos) /*!< 0x00400000 */
+#define GPIO_BSRR_BR6 GPIO_BSRR_BR6_Msk /*!< Port x Reset bit 6 */
+#define GPIO_BSRR_BR7_Pos (23U)
+#define GPIO_BSRR_BR7_Msk (0x1U << GPIO_BSRR_BR7_Pos) /*!< 0x00800000 */
+#define GPIO_BSRR_BR7 GPIO_BSRR_BR7_Msk /*!< Port x Reset bit 7 */
+#define GPIO_BSRR_BR8_Pos (24U)
+#define GPIO_BSRR_BR8_Msk (0x1U << GPIO_BSRR_BR8_Pos) /*!< 0x01000000 */
+#define GPIO_BSRR_BR8 GPIO_BSRR_BR8_Msk /*!< Port x Reset bit 8 */
+#define GPIO_BSRR_BR9_Pos (25U)
+#define GPIO_BSRR_BR9_Msk (0x1U << GPIO_BSRR_BR9_Pos) /*!< 0x02000000 */
+#define GPIO_BSRR_BR9 GPIO_BSRR_BR9_Msk /*!< Port x Reset bit 9 */
+#define GPIO_BSRR_BR10_Pos (26U)
+#define GPIO_BSRR_BR10_Msk (0x1U << GPIO_BSRR_BR10_Pos) /*!< 0x04000000 */
+#define GPIO_BSRR_BR10 GPIO_BSRR_BR10_Msk /*!< Port x Reset bit 10 */
+#define GPIO_BSRR_BR11_Pos (27U)
+#define GPIO_BSRR_BR11_Msk (0x1U << GPIO_BSRR_BR11_Pos) /*!< 0x08000000 */
+#define GPIO_BSRR_BR11 GPIO_BSRR_BR11_Msk /*!< Port x Reset bit 11 */
+#define GPIO_BSRR_BR12_Pos (28U)
+#define GPIO_BSRR_BR12_Msk (0x1U << GPIO_BSRR_BR12_Pos) /*!< 0x10000000 */
+#define GPIO_BSRR_BR12 GPIO_BSRR_BR12_Msk /*!< Port x Reset bit 12 */
+#define GPIO_BSRR_BR13_Pos (29U)
+#define GPIO_BSRR_BR13_Msk (0x1U << GPIO_BSRR_BR13_Pos) /*!< 0x20000000 */
+#define GPIO_BSRR_BR13 GPIO_BSRR_BR13_Msk /*!< Port x Reset bit 13 */
+#define GPIO_BSRR_BR14_Pos (30U)
+#define GPIO_BSRR_BR14_Msk (0x1U << GPIO_BSRR_BR14_Pos) /*!< 0x40000000 */
+#define GPIO_BSRR_BR14 GPIO_BSRR_BR14_Msk /*!< Port x Reset bit 14 */
+#define GPIO_BSRR_BR15_Pos (31U)
+#define GPIO_BSRR_BR15_Msk (0x1U << GPIO_BSRR_BR15_Pos) /*!< 0x80000000 */
+#define GPIO_BSRR_BR15 GPIO_BSRR_BR15_Msk /*!< Port x Reset bit 15 */
+
+/******************* Bit definition for GPIO_BRR register *******************/
+#define GPIO_BRR_BR0_Pos (0U)
+#define GPIO_BRR_BR0_Msk (0x1U << GPIO_BRR_BR0_Pos) /*!< 0x00000001 */
+#define GPIO_BRR_BR0 GPIO_BRR_BR0_Msk /*!< Port x Reset bit 0 */
+#define GPIO_BRR_BR1_Pos (1U)
+#define GPIO_BRR_BR1_Msk (0x1U << GPIO_BRR_BR1_Pos) /*!< 0x00000002 */
+#define GPIO_BRR_BR1 GPIO_BRR_BR1_Msk /*!< Port x Reset bit 1 */
+#define GPIO_BRR_BR2_Pos (2U)
+#define GPIO_BRR_BR2_Msk (0x1U << GPIO_BRR_BR2_Pos) /*!< 0x00000004 */
+#define GPIO_BRR_BR2 GPIO_BRR_BR2_Msk /*!< Port x Reset bit 2 */
+#define GPIO_BRR_BR3_Pos (3U)
+#define GPIO_BRR_BR3_Msk (0x1U << GPIO_BRR_BR3_Pos) /*!< 0x00000008 */
+#define GPIO_BRR_BR3 GPIO_BRR_BR3_Msk /*!< Port x Reset bit 3 */
+#define GPIO_BRR_BR4_Pos (4U)
+#define GPIO_BRR_BR4_Msk (0x1U << GPIO_BRR_BR4_Pos) /*!< 0x00000010 */
+#define GPIO_BRR_BR4 GPIO_BRR_BR4_Msk /*!< Port x Reset bit 4 */
+#define GPIO_BRR_BR5_Pos (5U)
+#define GPIO_BRR_BR5_Msk (0x1U << GPIO_BRR_BR5_Pos) /*!< 0x00000020 */
+#define GPIO_BRR_BR5 GPIO_BRR_BR5_Msk /*!< Port x Reset bit 5 */
+#define GPIO_BRR_BR6_Pos (6U)
+#define GPIO_BRR_BR6_Msk (0x1U << GPIO_BRR_BR6_Pos) /*!< 0x00000040 */
+#define GPIO_BRR_BR6 GPIO_BRR_BR6_Msk /*!< Port x Reset bit 6 */
+#define GPIO_BRR_BR7_Pos (7U)
+#define GPIO_BRR_BR7_Msk (0x1U << GPIO_BRR_BR7_Pos) /*!< 0x00000080 */
+#define GPIO_BRR_BR7 GPIO_BRR_BR7_Msk /*!< Port x Reset bit 7 */
+#define GPIO_BRR_BR8_Pos (8U)
+#define GPIO_BRR_BR8_Msk (0x1U << GPIO_BRR_BR8_Pos) /*!< 0x00000100 */
+#define GPIO_BRR_BR8 GPIO_BRR_BR8_Msk /*!< Port x Reset bit 8 */
+#define GPIO_BRR_BR9_Pos (9U)
+#define GPIO_BRR_BR9_Msk (0x1U << GPIO_BRR_BR9_Pos) /*!< 0x00000200 */
+#define GPIO_BRR_BR9 GPIO_BRR_BR9_Msk /*!< Port x Reset bit 9 */
+#define GPIO_BRR_BR10_Pos (10U)
+#define GPIO_BRR_BR10_Msk (0x1U << GPIO_BRR_BR10_Pos) /*!< 0x00000400 */
+#define GPIO_BRR_BR10 GPIO_BRR_BR10_Msk /*!< Port x Reset bit 10 */
+#define GPIO_BRR_BR11_Pos (11U)
+#define GPIO_BRR_BR11_Msk (0x1U << GPIO_BRR_BR11_Pos) /*!< 0x00000800 */
+#define GPIO_BRR_BR11 GPIO_BRR_BR11_Msk /*!< Port x Reset bit 11 */
+#define GPIO_BRR_BR12_Pos (12U)
+#define GPIO_BRR_BR12_Msk (0x1U << GPIO_BRR_BR12_Pos) /*!< 0x00001000 */
+#define GPIO_BRR_BR12 GPIO_BRR_BR12_Msk /*!< Port x Reset bit 12 */
+#define GPIO_BRR_BR13_Pos (13U)
+#define GPIO_BRR_BR13_Msk (0x1U << GPIO_BRR_BR13_Pos) /*!< 0x00002000 */
+#define GPIO_BRR_BR13 GPIO_BRR_BR13_Msk /*!< Port x Reset bit 13 */
+#define GPIO_BRR_BR14_Pos (14U)
+#define GPIO_BRR_BR14_Msk (0x1U << GPIO_BRR_BR14_Pos) /*!< 0x00004000 */
+#define GPIO_BRR_BR14 GPIO_BRR_BR14_Msk /*!< Port x Reset bit 14 */
+#define GPIO_BRR_BR15_Pos (15U)
+#define GPIO_BRR_BR15_Msk (0x1U << GPIO_BRR_BR15_Pos) /*!< 0x00008000 */
+#define GPIO_BRR_BR15 GPIO_BRR_BR15_Msk /*!< Port x Reset bit 15 */
+
+/****************** Bit definition for GPIO_LCKR register *******************/
+#define GPIO_LCKR_LCK0_Pos (0U)
+#define GPIO_LCKR_LCK0_Msk (0x1U << GPIO_LCKR_LCK0_Pos) /*!< 0x00000001 */
+#define GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk /*!< Port x Lock bit 0 */
+#define GPIO_LCKR_LCK1_Pos (1U)
+#define GPIO_LCKR_LCK1_Msk (0x1U << GPIO_LCKR_LCK1_Pos) /*!< 0x00000002 */
+#define GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk /*!< Port x Lock bit 1 */
+#define GPIO_LCKR_LCK2_Pos (2U)
+#define GPIO_LCKR_LCK2_Msk (0x1U << GPIO_LCKR_LCK2_Pos) /*!< 0x00000004 */
+#define GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk /*!< Port x Lock bit 2 */
+#define GPIO_LCKR_LCK3_Pos (3U)
+#define GPIO_LCKR_LCK3_Msk (0x1U << GPIO_LCKR_LCK3_Pos) /*!< 0x00000008 */
+#define GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk /*!< Port x Lock bit 3 */
+#define GPIO_LCKR_LCK4_Pos (4U)
+#define GPIO_LCKR_LCK4_Msk (0x1U << GPIO_LCKR_LCK4_Pos) /*!< 0x00000010 */
+#define GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk /*!< Port x Lock bit 4 */
+#define GPIO_LCKR_LCK5_Pos (5U)
+#define GPIO_LCKR_LCK5_Msk (0x1U << GPIO_LCKR_LCK5_Pos) /*!< 0x00000020 */
+#define GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk /*!< Port x Lock bit 5 */
+#define GPIO_LCKR_LCK6_Pos (6U)
+#define GPIO_LCKR_LCK6_Msk (0x1U << GPIO_LCKR_LCK6_Pos) /*!< 0x00000040 */
+#define GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk /*!< Port x Lock bit 6 */
+#define GPIO_LCKR_LCK7_Pos (7U)
+#define GPIO_LCKR_LCK7_Msk (0x1U << GPIO_LCKR_LCK7_Pos) /*!< 0x00000080 */
+#define GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk /*!< Port x Lock bit 7 */
+#define GPIO_LCKR_LCK8_Pos (8U)
+#define GPIO_LCKR_LCK8_Msk (0x1U << GPIO_LCKR_LCK8_Pos) /*!< 0x00000100 */
+#define GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk /*!< Port x Lock bit 8 */
+#define GPIO_LCKR_LCK9_Pos (9U)
+#define GPIO_LCKR_LCK9_Msk (0x1U << GPIO_LCKR_LCK9_Pos) /*!< 0x00000200 */
+#define GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk /*!< Port x Lock bit 9 */
+#define GPIO_LCKR_LCK10_Pos (10U)
+#define GPIO_LCKR_LCK10_Msk (0x1U << GPIO_LCKR_LCK10_Pos) /*!< 0x00000400 */
+#define GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk /*!< Port x Lock bit 10 */
+#define GPIO_LCKR_LCK11_Pos (11U)
+#define GPIO_LCKR_LCK11_Msk (0x1U << GPIO_LCKR_LCK11_Pos) /*!< 0x00000800 */
+#define GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk /*!< Port x Lock bit 11 */
+#define GPIO_LCKR_LCK12_Pos (12U)
+#define GPIO_LCKR_LCK12_Msk (0x1U << GPIO_LCKR_LCK12_Pos) /*!< 0x00001000 */
+#define GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk /*!< Port x Lock bit 12 */
+#define GPIO_LCKR_LCK13_Pos (13U)
+#define GPIO_LCKR_LCK13_Msk (0x1U << GPIO_LCKR_LCK13_Pos) /*!< 0x00002000 */
+#define GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk /*!< Port x Lock bit 13 */
+#define GPIO_LCKR_LCK14_Pos (14U)
+#define GPIO_LCKR_LCK14_Msk (0x1U << GPIO_LCKR_LCK14_Pos) /*!< 0x00004000 */
+#define GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk /*!< Port x Lock bit 14 */
+#define GPIO_LCKR_LCK15_Pos (15U)
+#define GPIO_LCKR_LCK15_Msk (0x1U << GPIO_LCKR_LCK15_Pos) /*!< 0x00008000 */
+#define GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk /*!< Port x Lock bit 15 */
+#define GPIO_LCKR_LCKK_Pos (16U)
+#define GPIO_LCKR_LCKK_Msk (0x1U << GPIO_LCKR_LCKK_Pos) /*!< 0x00010000 */
+#define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk /*!< Lock key */
+
+/*----------------------------------------------------------------------------*/
+
+/****************** Bit definition for AFIO_EVCR register *******************/
+#define AFIO_EVCR_PIN_Pos (0U)
+#define AFIO_EVCR_PIN_Msk (0xFU << AFIO_EVCR_PIN_Pos) /*!< 0x0000000F */
+#define AFIO_EVCR_PIN AFIO_EVCR_PIN_Msk /*!< PIN[3:0] bits (Pin selection) */
+#define AFIO_EVCR_PIN_0 (0x1U << AFIO_EVCR_PIN_Pos) /*!< 0x00000001 */
+#define AFIO_EVCR_PIN_1 (0x2U << AFIO_EVCR_PIN_Pos) /*!< 0x00000002 */
+#define AFIO_EVCR_PIN_2 (0x4U << AFIO_EVCR_PIN_Pos) /*!< 0x00000004 */
+#define AFIO_EVCR_PIN_3 (0x8U << AFIO_EVCR_PIN_Pos) /*!< 0x00000008 */
+
+/*!< PIN configuration */
+#define AFIO_EVCR_PIN_PX0 ((uint32_t)0x00000000) /*!< Pin 0 selected */
+#define AFIO_EVCR_PIN_PX1_Pos (0U)
+#define AFIO_EVCR_PIN_PX1_Msk (0x1U << AFIO_EVCR_PIN_PX1_Pos) /*!< 0x00000001 */
+#define AFIO_EVCR_PIN_PX1 AFIO_EVCR_PIN_PX1_Msk /*!< Pin 1 selected */
+#define AFIO_EVCR_PIN_PX2_Pos (1U)
+#define AFIO_EVCR_PIN_PX2_Msk (0x1U << AFIO_EVCR_PIN_PX2_Pos) /*!< 0x00000002 */
+#define AFIO_EVCR_PIN_PX2 AFIO_EVCR_PIN_PX2_Msk /*!< Pin 2 selected */
+#define AFIO_EVCR_PIN_PX3_Pos (0U)
+#define AFIO_EVCR_PIN_PX3_Msk (0x3U << AFIO_EVCR_PIN_PX3_Pos) /*!< 0x00000003 */
+#define AFIO_EVCR_PIN_PX3 AFIO_EVCR_PIN_PX3_Msk /*!< Pin 3 selected */
+#define AFIO_EVCR_PIN_PX4_Pos (2U)
+#define AFIO_EVCR_PIN_PX4_Msk (0x1U << AFIO_EVCR_PIN_PX4_Pos) /*!< 0x00000004 */
+#define AFIO_EVCR_PIN_PX4 AFIO_EVCR_PIN_PX4_Msk /*!< Pin 4 selected */
+#define AFIO_EVCR_PIN_PX5_Pos (0U)
+#define AFIO_EVCR_PIN_PX5_Msk (0x5U << AFIO_EVCR_PIN_PX5_Pos) /*!< 0x00000005 */
+#define AFIO_EVCR_PIN_PX5 AFIO_EVCR_PIN_PX5_Msk /*!< Pin 5 selected */
+#define AFIO_EVCR_PIN_PX6_Pos (1U)
+#define AFIO_EVCR_PIN_PX6_Msk (0x3U << AFIO_EVCR_PIN_PX6_Pos) /*!< 0x00000006 */
+#define AFIO_EVCR_PIN_PX6 AFIO_EVCR_PIN_PX6_Msk /*!< Pin 6 selected */
+#define AFIO_EVCR_PIN_PX7_Pos (0U)
+#define AFIO_EVCR_PIN_PX7_Msk (0x7U << AFIO_EVCR_PIN_PX7_Pos) /*!< 0x00000007 */
+#define AFIO_EVCR_PIN_PX7 AFIO_EVCR_PIN_PX7_Msk /*!< Pin 7 selected */
+#define AFIO_EVCR_PIN_PX8_Pos (3U)
+#define AFIO_EVCR_PIN_PX8_Msk (0x1U << AFIO_EVCR_PIN_PX8_Pos) /*!< 0x00000008 */
+#define AFIO_EVCR_PIN_PX8 AFIO_EVCR_PIN_PX8_Msk /*!< Pin 8 selected */
+#define AFIO_EVCR_PIN_PX9_Pos (0U)
+#define AFIO_EVCR_PIN_PX9_Msk (0x9U << AFIO_EVCR_PIN_PX9_Pos) /*!< 0x00000009 */
+#define AFIO_EVCR_PIN_PX9 AFIO_EVCR_PIN_PX9_Msk /*!< Pin 9 selected */
+#define AFIO_EVCR_PIN_PX10_Pos (1U)
+#define AFIO_EVCR_PIN_PX10_Msk (0x5U << AFIO_EVCR_PIN_PX10_Pos) /*!< 0x0000000A */
+#define AFIO_EVCR_PIN_PX10 AFIO_EVCR_PIN_PX10_Msk /*!< Pin 10 selected */
+#define AFIO_EVCR_PIN_PX11_Pos (0U)
+#define AFIO_EVCR_PIN_PX11_Msk (0xBU << AFIO_EVCR_PIN_PX11_Pos) /*!< 0x0000000B */
+#define AFIO_EVCR_PIN_PX11 AFIO_EVCR_PIN_PX11_Msk /*!< Pin 11 selected */
+#define AFIO_EVCR_PIN_PX12_Pos (2U)
+#define AFIO_EVCR_PIN_PX12_Msk (0x3U << AFIO_EVCR_PIN_PX12_Pos) /*!< 0x0000000C */
+#define AFIO_EVCR_PIN_PX12 AFIO_EVCR_PIN_PX12_Msk /*!< Pin 12 selected */
+#define AFIO_EVCR_PIN_PX13_Pos (0U)
+#define AFIO_EVCR_PIN_PX13_Msk (0xDU << AFIO_EVCR_PIN_PX13_Pos) /*!< 0x0000000D */
+#define AFIO_EVCR_PIN_PX13 AFIO_EVCR_PIN_PX13_Msk /*!< Pin 13 selected */
+#define AFIO_EVCR_PIN_PX14_Pos (1U)
+#define AFIO_EVCR_PIN_PX14_Msk (0x7U << AFIO_EVCR_PIN_PX14_Pos) /*!< 0x0000000E */
+#define AFIO_EVCR_PIN_PX14 AFIO_EVCR_PIN_PX14_Msk /*!< Pin 14 selected */
+#define AFIO_EVCR_PIN_PX15_Pos (0U)
+#define AFIO_EVCR_PIN_PX15_Msk (0xFU << AFIO_EVCR_PIN_PX15_Pos) /*!< 0x0000000F */
+#define AFIO_EVCR_PIN_PX15 AFIO_EVCR_PIN_PX15_Msk /*!< Pin 15 selected */
+
+#define AFIO_EVCR_PORT_Pos (4U)
+#define AFIO_EVCR_PORT_Msk (0x7U << AFIO_EVCR_PORT_Pos) /*!< 0x00000070 */
+#define AFIO_EVCR_PORT AFIO_EVCR_PORT_Msk /*!< PORT[2:0] bits (Port selection) */
+#define AFIO_EVCR_PORT_0 (0x1U << AFIO_EVCR_PORT_Pos) /*!< 0x00000010 */
+#define AFIO_EVCR_PORT_1 (0x2U << AFIO_EVCR_PORT_Pos) /*!< 0x00000020 */
+#define AFIO_EVCR_PORT_2 (0x4U << AFIO_EVCR_PORT_Pos) /*!< 0x00000040 */
+
+/*!< PORT configuration */
+#define AFIO_EVCR_PORT_PA ((uint32_t)0x00000000) /*!< Port A selected */
+#define AFIO_EVCR_PORT_PB_Pos (4U)
+#define AFIO_EVCR_PORT_PB_Msk (0x1U << AFIO_EVCR_PORT_PB_Pos) /*!< 0x00000010 */
+#define AFIO_EVCR_PORT_PB AFIO_EVCR_PORT_PB_Msk /*!< Port B selected */
+#define AFIO_EVCR_PORT_PC_Pos (5U)
+#define AFIO_EVCR_PORT_PC_Msk (0x1U << AFIO_EVCR_PORT_PC_Pos) /*!< 0x00000020 */
+#define AFIO_EVCR_PORT_PC AFIO_EVCR_PORT_PC_Msk /*!< Port C selected */
+#define AFIO_EVCR_PORT_PD_Pos (4U)
+#define AFIO_EVCR_PORT_PD_Msk (0x3U << AFIO_EVCR_PORT_PD_Pos) /*!< 0x00000030 */
+#define AFIO_EVCR_PORT_PD AFIO_EVCR_PORT_PD_Msk /*!< Port D selected */
+#define AFIO_EVCR_PORT_PE_Pos (6U)
+#define AFIO_EVCR_PORT_PE_Msk (0x1U << AFIO_EVCR_PORT_PE_Pos) /*!< 0x00000040 */
+#define AFIO_EVCR_PORT_PE AFIO_EVCR_PORT_PE_Msk /*!< Port E selected */
+
+#define AFIO_EVCR_EVOE_Pos (7U)
+#define AFIO_EVCR_EVOE_Msk (0x1U << AFIO_EVCR_EVOE_Pos) /*!< 0x00000080 */
+#define AFIO_EVCR_EVOE AFIO_EVCR_EVOE_Msk /*!< Event Output Enable */
+
+/****************** Bit definition for AFIO_MAPR register *******************/
+#define AFIO_MAPR_SPI1_REMAP_Pos (0U)
+#define AFIO_MAPR_SPI1_REMAP_Msk (0x1U << AFIO_MAPR_SPI1_REMAP_Pos) /*!< 0x00000001 */
+#define AFIO_MAPR_SPI1_REMAP AFIO_MAPR_SPI1_REMAP_Msk /*!< SPI1 remapping */
+#define AFIO_MAPR_I2C1_REMAP_Pos (1U)
+#define AFIO_MAPR_I2C1_REMAP_Msk (0x1U << AFIO_MAPR_I2C1_REMAP_Pos) /*!< 0x00000002 */
+#define AFIO_MAPR_I2C1_REMAP AFIO_MAPR_I2C1_REMAP_Msk /*!< I2C1 remapping */
+#define AFIO_MAPR_USART1_REMAP_Pos (2U)
+#define AFIO_MAPR_USART1_REMAP_Msk (0x1U << AFIO_MAPR_USART1_REMAP_Pos) /*!< 0x00000004 */
+#define AFIO_MAPR_USART1_REMAP AFIO_MAPR_USART1_REMAP_Msk /*!< USART1 remapping */
+#define AFIO_MAPR_USART2_REMAP_Pos (3U)
+#define AFIO_MAPR_USART2_REMAP_Msk (0x1U << AFIO_MAPR_USART2_REMAP_Pos) /*!< 0x00000008 */
+#define AFIO_MAPR_USART2_REMAP AFIO_MAPR_USART2_REMAP_Msk /*!< USART2 remapping */
+
+#define AFIO_MAPR_USART3_REMAP_Pos (4U)
+#define AFIO_MAPR_USART3_REMAP_Msk (0x3U << AFIO_MAPR_USART3_REMAP_Pos) /*!< 0x00000030 */
+#define AFIO_MAPR_USART3_REMAP AFIO_MAPR_USART3_REMAP_Msk /*!< USART3_REMAP[1:0] bits (USART3 remapping) */
+#define AFIO_MAPR_USART3_REMAP_0 (0x1U << AFIO_MAPR_USART3_REMAP_Pos) /*!< 0x00000010 */
+#define AFIO_MAPR_USART3_REMAP_1 (0x2U << AFIO_MAPR_USART3_REMAP_Pos) /*!< 0x00000020 */
+
+/* USART3_REMAP configuration */
+#define AFIO_MAPR_USART3_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14) */
+#define AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Pos (4U)
+#define AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Msk (0x1U << AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Pos) /*!< 0x00000010 */
+#define AFIO_MAPR_USART3_REMAP_PARTIALREMAP AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Msk /*!< Partial remap (TX/PC10, RX/PC11, CK/PC12, CTS/PB13, RTS/PB14) */
+#define AFIO_MAPR_USART3_REMAP_FULLREMAP_Pos (4U)
+#define AFIO_MAPR_USART3_REMAP_FULLREMAP_Msk (0x3U << AFIO_MAPR_USART3_REMAP_FULLREMAP_Pos) /*!< 0x00000030 */
+#define AFIO_MAPR_USART3_REMAP_FULLREMAP AFIO_MAPR_USART3_REMAP_FULLREMAP_Msk /*!< Full remap (TX/PD8, RX/PD9, CK/PD10, CTS/PD11, RTS/PD12) */
+
+#define AFIO_MAPR_TIM1_REMAP_Pos (6U)
+#define AFIO_MAPR_TIM1_REMAP_Msk (0x3U << AFIO_MAPR_TIM1_REMAP_Pos) /*!< 0x000000C0 */
+#define AFIO_MAPR_TIM1_REMAP AFIO_MAPR_TIM1_REMAP_Msk /*!< TIM1_REMAP[1:0] bits (TIM1 remapping) */
+#define AFIO_MAPR_TIM1_REMAP_0 (0x1U << AFIO_MAPR_TIM1_REMAP_Pos) /*!< 0x00000040 */
+#define AFIO_MAPR_TIM1_REMAP_1 (0x2U << AFIO_MAPR_TIM1_REMAP_Pos) /*!< 0x00000080 */
+
+/*!< TIM1_REMAP configuration */
+#define AFIO_MAPR_TIM1_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15) */
+#define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Pos (6U)
+#define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Msk (0x1U << AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Pos) /*!< 0x00000040 */
+#define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Msk /*!< Partial remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PA6, CH1N/PA7, CH2N/PB0, CH3N/PB1) */
+#define AFIO_MAPR_TIM1_REMAP_FULLREMAP_Pos (6U)
+#define AFIO_MAPR_TIM1_REMAP_FULLREMAP_Msk (0x3U << AFIO_MAPR_TIM1_REMAP_FULLREMAP_Pos) /*!< 0x000000C0 */
+#define AFIO_MAPR_TIM1_REMAP_FULLREMAP AFIO_MAPR_TIM1_REMAP_FULLREMAP_Msk /*!< Full remap (ETR/PE7, CH1/PE9, CH2/PE11, CH3/PE13, CH4/PE14, BKIN/PE15, CH1N/PE8, CH2N/PE10, CH3N/PE12) */
+
+#define AFIO_MAPR_TIM2_REMAP_Pos (8U)
+#define AFIO_MAPR_TIM2_REMAP_Msk (0x3U << AFIO_MAPR_TIM2_REMAP_Pos) /*!< 0x00000300 */
+#define AFIO_MAPR_TIM2_REMAP AFIO_MAPR_TIM2_REMAP_Msk /*!< TIM2_REMAP[1:0] bits (TIM2 remapping) */
+#define AFIO_MAPR_TIM2_REMAP_0 (0x1U << AFIO_MAPR_TIM2_REMAP_Pos) /*!< 0x00000100 */
+#define AFIO_MAPR_TIM2_REMAP_1 (0x2U << AFIO_MAPR_TIM2_REMAP_Pos) /*!< 0x00000200 */
+
+/*!< TIM2_REMAP configuration */
+#define AFIO_MAPR_TIM2_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3) */
+#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Pos (8U)
+#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Msk (0x1U << AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Pos) /*!< 0x00000100 */
+#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1 AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Msk /*!< Partial remap (CH1/ETR/PA15, CH2/PB3, CH3/PA2, CH4/PA3) */
+#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2_Pos (9U)
+#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2_Msk (0x1U << AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2_Pos) /*!< 0x00000200 */
+#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2 AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2_Msk /*!< Partial remap (CH1/ETR/PA0, CH2/PA1, CH3/PB10, CH4/PB11) */
+#define AFIO_MAPR_TIM2_REMAP_FULLREMAP_Pos (8U)
+#define AFIO_MAPR_TIM2_REMAP_FULLREMAP_Msk (0x3U << AFIO_MAPR_TIM2_REMAP_FULLREMAP_Pos) /*!< 0x00000300 */
+#define AFIO_MAPR_TIM2_REMAP_FULLREMAP AFIO_MAPR_TIM2_REMAP_FULLREMAP_Msk /*!< Full remap (CH1/ETR/PA15, CH2/PB3, CH3/PB10, CH4/PB11) */
+
+#define AFIO_MAPR_TIM3_REMAP_Pos (10U)
+#define AFIO_MAPR_TIM3_REMAP_Msk (0x3U << AFIO_MAPR_TIM3_REMAP_Pos) /*!< 0x00000C00 */
+#define AFIO_MAPR_TIM3_REMAP AFIO_MAPR_TIM3_REMAP_Msk /*!< TIM3_REMAP[1:0] bits (TIM3 remapping) */
+#define AFIO_MAPR_TIM3_REMAP_0 (0x1U << AFIO_MAPR_TIM3_REMAP_Pos) /*!< 0x00000400 */
+#define AFIO_MAPR_TIM3_REMAP_1 (0x2U << AFIO_MAPR_TIM3_REMAP_Pos) /*!< 0x00000800 */
+
+/*!< TIM3_REMAP configuration */
+#define AFIO_MAPR_TIM3_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1) */
+#define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Pos (11U)
+#define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Msk (0x1U << AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Pos) /*!< 0x00000800 */
+#define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Msk /*!< Partial remap (CH1/PB4, CH2/PB5, CH3/PB0, CH4/PB1) */
+#define AFIO_MAPR_TIM3_REMAP_FULLREMAP_Pos (10U)
+#define AFIO_MAPR_TIM3_REMAP_FULLREMAP_Msk (0x3U << AFIO_MAPR_TIM3_REMAP_FULLREMAP_Pos) /*!< 0x00000C00 */
+#define AFIO_MAPR_TIM3_REMAP_FULLREMAP AFIO_MAPR_TIM3_REMAP_FULLREMAP_Msk /*!< Full remap (CH1/PC6, CH2/PC7, CH3/PC8, CH4/PC9) */
+
+#define AFIO_MAPR_TIM4_REMAP_Pos (12U)
+#define AFIO_MAPR_TIM4_REMAP_Msk (0x1U << AFIO_MAPR_TIM4_REMAP_Pos) /*!< 0x00001000 */
+#define AFIO_MAPR_TIM4_REMAP AFIO_MAPR_TIM4_REMAP_Msk /*!< TIM4_REMAP bit (TIM4 remapping) */
+
+#define AFIO_MAPR_CAN_REMAP_Pos (13U)
+#define AFIO_MAPR_CAN_REMAP_Msk (0x3U << AFIO_MAPR_CAN_REMAP_Pos) /*!< 0x00006000 */
+#define AFIO_MAPR_CAN_REMAP AFIO_MAPR_CAN_REMAP_Msk /*!< CAN_REMAP[1:0] bits (CAN Alternate function remapping) */
+#define AFIO_MAPR_CAN_REMAP_0 (0x1U << AFIO_MAPR_CAN_REMAP_Pos) /*!< 0x00002000 */
+#define AFIO_MAPR_CAN_REMAP_1 (0x2U << AFIO_MAPR_CAN_REMAP_Pos) /*!< 0x00004000 */
+
+/*!< CAN_REMAP configuration */
+#define AFIO_MAPR_CAN_REMAP_REMAP1 ((uint32_t)0x00000000) /*!< CANRX mapped to PA11, CANTX mapped to PA12 */
+#define AFIO_MAPR_CAN_REMAP_REMAP2_Pos (14U)
+#define AFIO_MAPR_CAN_REMAP_REMAP2_Msk (0x1U << AFIO_MAPR_CAN_REMAP_REMAP2_Pos) /*!< 0x00004000 */
+#define AFIO_MAPR_CAN_REMAP_REMAP2 AFIO_MAPR_CAN_REMAP_REMAP2_Msk /*!< CANRX mapped to PB8, CANTX mapped to PB9 */
+#define AFIO_MAPR_CAN_REMAP_REMAP3_Pos (13U)
+#define AFIO_MAPR_CAN_REMAP_REMAP3_Msk (0x3U << AFIO_MAPR_CAN_REMAP_REMAP3_Pos) /*!< 0x00006000 */
+#define AFIO_MAPR_CAN_REMAP_REMAP3 AFIO_MAPR_CAN_REMAP_REMAP3_Msk /*!< CANRX mapped to PD0, CANTX mapped to PD1 */
+
+#define AFIO_MAPR_PD01_REMAP_Pos (15U)
+#define AFIO_MAPR_PD01_REMAP_Msk (0x1U << AFIO_MAPR_PD01_REMAP_Pos) /*!< 0x00008000 */
+#define AFIO_MAPR_PD01_REMAP AFIO_MAPR_PD01_REMAP_Msk /*!< Port D0/Port D1 mapping on OSC_IN/OSC_OUT */
+#define AFIO_MAPR_TIM5CH4_IREMAP_Pos (16U)
+#define AFIO_MAPR_TIM5CH4_IREMAP_Msk (0x1U << AFIO_MAPR_TIM5CH4_IREMAP_Pos) /*!< 0x00010000 */
+#define AFIO_MAPR_TIM5CH4_IREMAP AFIO_MAPR_TIM5CH4_IREMAP_Msk /*!< TIM5 Channel4 Internal Remap */
+
+/*!< SWJ_CFG configuration */
+#define AFIO_MAPR_SWJ_CFG_Pos (24U)
+#define AFIO_MAPR_SWJ_CFG_Msk (0x7U << AFIO_MAPR_SWJ_CFG_Pos) /*!< 0x07000000 */
+#define AFIO_MAPR_SWJ_CFG AFIO_MAPR_SWJ_CFG_Msk /*!< SWJ_CFG[2:0] bits (Serial Wire JTAG configuration) */
+#define AFIO_MAPR_SWJ_CFG_0 (0x1U << AFIO_MAPR_SWJ_CFG_Pos) /*!< 0x01000000 */
+#define AFIO_MAPR_SWJ_CFG_1 (0x2U << AFIO_MAPR_SWJ_CFG_Pos) /*!< 0x02000000 */
+#define AFIO_MAPR_SWJ_CFG_2 (0x4U << AFIO_MAPR_SWJ_CFG_Pos) /*!< 0x04000000 */
+
+#define AFIO_MAPR_SWJ_CFG_RESET ((uint32_t)0x00000000) /*!< Full SWJ (JTAG-DP + SW-DP) : Reset State */
+#define AFIO_MAPR_SWJ_CFG_NOJNTRST_Pos (24U)
+#define AFIO_MAPR_SWJ_CFG_NOJNTRST_Msk (0x1U << AFIO_MAPR_SWJ_CFG_NOJNTRST_Pos) /*!< 0x01000000 */
+#define AFIO_MAPR_SWJ_CFG_NOJNTRST AFIO_MAPR_SWJ_CFG_NOJNTRST_Msk /*!< Full SWJ (JTAG-DP + SW-DP) but without JNTRST */
+#define AFIO_MAPR_SWJ_CFG_JTAGDISABLE_Pos (25U)
+#define AFIO_MAPR_SWJ_CFG_JTAGDISABLE_Msk (0x1U << AFIO_MAPR_SWJ_CFG_JTAGDISABLE_Pos) /*!< 0x02000000 */
+#define AFIO_MAPR_SWJ_CFG_JTAGDISABLE AFIO_MAPR_SWJ_CFG_JTAGDISABLE_Msk /*!< JTAG-DP Disabled and SW-DP Enabled */
+#define AFIO_MAPR_SWJ_CFG_DISABLE_Pos (26U)
+#define AFIO_MAPR_SWJ_CFG_DISABLE_Msk (0x1U << AFIO_MAPR_SWJ_CFG_DISABLE_Pos) /*!< 0x04000000 */
+#define AFIO_MAPR_SWJ_CFG_DISABLE AFIO_MAPR_SWJ_CFG_DISABLE_Msk /*!< JTAG-DP Disabled and SW-DP Disabled */
+
+/*!< ETH_REMAP configuration */
+#define AFIO_MAPR_ETH_REMAP_Pos (21U)
+#define AFIO_MAPR_ETH_REMAP_Msk (0x1U << AFIO_MAPR_ETH_REMAP_Pos) /*!< 0x00200000 */
+#define AFIO_MAPR_ETH_REMAP AFIO_MAPR_ETH_REMAP_Msk /*!< SPI3_REMAP bit (Ethernet MAC I/O remapping) */
+
+/*!< CAN2_REMAP configuration */
+#define AFIO_MAPR_CAN2_REMAP_Pos (22U)
+#define AFIO_MAPR_CAN2_REMAP_Msk (0x1U << AFIO_MAPR_CAN2_REMAP_Pos) /*!< 0x00400000 */
+#define AFIO_MAPR_CAN2_REMAP AFIO_MAPR_CAN2_REMAP_Msk /*!< CAN2_REMAP bit (CAN2 I/O remapping) */
+
+/*!< MII_RMII_SEL configuration */
+#define AFIO_MAPR_MII_RMII_SEL_Pos (23U)
+#define AFIO_MAPR_MII_RMII_SEL_Msk (0x1U << AFIO_MAPR_MII_RMII_SEL_Pos) /*!< 0x00800000 */
+#define AFIO_MAPR_MII_RMII_SEL AFIO_MAPR_MII_RMII_SEL_Msk /*!< MII_RMII_SEL bit (Ethernet MII or RMII selection) */
+
+/*!< SPI3_REMAP configuration */
+#define AFIO_MAPR_SPI3_REMAP_Pos (28U)
+#define AFIO_MAPR_SPI3_REMAP_Msk (0x1U << AFIO_MAPR_SPI3_REMAP_Pos) /*!< 0x10000000 */
+#define AFIO_MAPR_SPI3_REMAP AFIO_MAPR_SPI3_REMAP_Msk /*!< SPI3_REMAP bit (SPI3 remapping) */
+
+/*!< TIM2ITR1_IREMAP configuration */
+#define AFIO_MAPR_TIM2ITR1_IREMAP_Pos (29U)
+#define AFIO_MAPR_TIM2ITR1_IREMAP_Msk (0x1U << AFIO_MAPR_TIM2ITR1_IREMAP_Pos) /*!< 0x20000000 */
+#define AFIO_MAPR_TIM2ITR1_IREMAP AFIO_MAPR_TIM2ITR1_IREMAP_Msk /*!< TIM2ITR1_IREMAP bit (TIM2 internal trigger 1 remapping) */
+
+/*!< PTP_PPS_REMAP configuration */
+#define AFIO_MAPR_PTP_PPS_REMAP_Pos (30U)
+#define AFIO_MAPR_PTP_PPS_REMAP_Msk (0x1U << AFIO_MAPR_PTP_PPS_REMAP_Pos) /*!< 0x40000000 */
+#define AFIO_MAPR_PTP_PPS_REMAP AFIO_MAPR_PTP_PPS_REMAP_Msk /*!< PTP_PPS_REMAP bit (Ethernet PTP PPS remapping) */
+
+/***************** Bit definition for AFIO_EXTICR1 register *****************/
+#define AFIO_EXTICR1_EXTI0_Pos (0U)
+#define AFIO_EXTICR1_EXTI0_Msk (0xFU << AFIO_EXTICR1_EXTI0_Pos) /*!< 0x0000000F */
+#define AFIO_EXTICR1_EXTI0 AFIO_EXTICR1_EXTI0_Msk /*!< EXTI 0 configuration */
+#define AFIO_EXTICR1_EXTI1_Pos (4U)
+#define AFIO_EXTICR1_EXTI1_Msk (0xFU << AFIO_EXTICR1_EXTI1_Pos) /*!< 0x000000F0 */
+#define AFIO_EXTICR1_EXTI1 AFIO_EXTICR1_EXTI1_Msk /*!< EXTI 1 configuration */
+#define AFIO_EXTICR1_EXTI2_Pos (8U)
+#define AFIO_EXTICR1_EXTI2_Msk (0xFU << AFIO_EXTICR1_EXTI2_Pos) /*!< 0x00000F00 */
+#define AFIO_EXTICR1_EXTI2 AFIO_EXTICR1_EXTI2_Msk /*!< EXTI 2 configuration */
+#define AFIO_EXTICR1_EXTI3_Pos (12U)
+#define AFIO_EXTICR1_EXTI3_Msk (0xFU << AFIO_EXTICR1_EXTI3_Pos) /*!< 0x0000F000 */
+#define AFIO_EXTICR1_EXTI3 AFIO_EXTICR1_EXTI3_Msk /*!< EXTI 3 configuration */
+
+/*!< EXTI0 configuration */
+#define AFIO_EXTICR1_EXTI0_PA ((uint32_t)0x00000000) /*!< PA[0] pin */
+#define AFIO_EXTICR1_EXTI0_PB_Pos (0U)
+#define AFIO_EXTICR1_EXTI0_PB_Msk (0x1U << AFIO_EXTICR1_EXTI0_PB_Pos) /*!< 0x00000001 */
+#define AFIO_EXTICR1_EXTI0_PB AFIO_EXTICR1_EXTI0_PB_Msk /*!< PB[0] pin */
+#define AFIO_EXTICR1_EXTI0_PC_Pos (1U)
+#define AFIO_EXTICR1_EXTI0_PC_Msk (0x1U << AFIO_EXTICR1_EXTI0_PC_Pos) /*!< 0x00000002 */
+#define AFIO_EXTICR1_EXTI0_PC AFIO_EXTICR1_EXTI0_PC_Msk /*!< PC[0] pin */
+#define AFIO_EXTICR1_EXTI0_PD_Pos (0U)
+#define AFIO_EXTICR1_EXTI0_PD_Msk (0x3U << AFIO_EXTICR1_EXTI0_PD_Pos) /*!< 0x00000003 */
+#define AFIO_EXTICR1_EXTI0_PD AFIO_EXTICR1_EXTI0_PD_Msk /*!< PD[0] pin */
+#define AFIO_EXTICR1_EXTI0_PE_Pos (2U)
+#define AFIO_EXTICR1_EXTI0_PE_Msk (0x1U << AFIO_EXTICR1_EXTI0_PE_Pos) /*!< 0x00000004 */
+#define AFIO_EXTICR1_EXTI0_PE AFIO_EXTICR1_EXTI0_PE_Msk /*!< PE[0] pin */
+#define AFIO_EXTICR1_EXTI0_PF_Pos (0U)
+#define AFIO_EXTICR1_EXTI0_PF_Msk (0x5U << AFIO_EXTICR1_EXTI0_PF_Pos) /*!< 0x00000005 */
+#define AFIO_EXTICR1_EXTI0_PF AFIO_EXTICR1_EXTI0_PF_Msk /*!< PF[0] pin */
+#define AFIO_EXTICR1_EXTI0_PG_Pos (1U)
+#define AFIO_EXTICR1_EXTI0_PG_Msk (0x3U << AFIO_EXTICR1_EXTI0_PG_Pos) /*!< 0x00000006 */
+#define AFIO_EXTICR1_EXTI0_PG AFIO_EXTICR1_EXTI0_PG_Msk /*!< PG[0] pin */
+
+/*!< EXTI1 configuration */
+#define AFIO_EXTICR1_EXTI1_PA ((uint32_t)0x00000000) /*!< PA[1] pin */
+#define AFIO_EXTICR1_EXTI1_PB_Pos (4U)
+#define AFIO_EXTICR1_EXTI1_PB_Msk (0x1U << AFIO_EXTICR1_EXTI1_PB_Pos) /*!< 0x00000010 */
+#define AFIO_EXTICR1_EXTI1_PB AFIO_EXTICR1_EXTI1_PB_Msk /*!< PB[1] pin */
+#define AFIO_EXTICR1_EXTI1_PC_Pos (5U)
+#define AFIO_EXTICR1_EXTI1_PC_Msk (0x1U << AFIO_EXTICR1_EXTI1_PC_Pos) /*!< 0x00000020 */
+#define AFIO_EXTICR1_EXTI1_PC AFIO_EXTICR1_EXTI1_PC_Msk /*!< PC[1] pin */
+#define AFIO_EXTICR1_EXTI1_PD_Pos (4U)
+#define AFIO_EXTICR1_EXTI1_PD_Msk (0x3U << AFIO_EXTICR1_EXTI1_PD_Pos) /*!< 0x00000030 */
+#define AFIO_EXTICR1_EXTI1_PD AFIO_EXTICR1_EXTI1_PD_Msk /*!< PD[1] pin */
+#define AFIO_EXTICR1_EXTI1_PE_Pos (6U)
+#define AFIO_EXTICR1_EXTI1_PE_Msk (0x1U << AFIO_EXTICR1_EXTI1_PE_Pos) /*!< 0x00000040 */
+#define AFIO_EXTICR1_EXTI1_PE AFIO_EXTICR1_EXTI1_PE_Msk /*!< PE[1] pin */
+#define AFIO_EXTICR1_EXTI1_PF_Pos (4U)
+#define AFIO_EXTICR1_EXTI1_PF_Msk (0x5U << AFIO_EXTICR1_EXTI1_PF_Pos) /*!< 0x00000050 */
+#define AFIO_EXTICR1_EXTI1_PF AFIO_EXTICR1_EXTI1_PF_Msk /*!< PF[1] pin */
+#define AFIO_EXTICR1_EXTI1_PG_Pos (5U)
+#define AFIO_EXTICR1_EXTI1_PG_Msk (0x3U << AFIO_EXTICR1_EXTI1_PG_Pos) /*!< 0x00000060 */
+#define AFIO_EXTICR1_EXTI1_PG AFIO_EXTICR1_EXTI1_PG_Msk /*!< PG[1] pin */
+
+/*!< EXTI2 configuration */
+#define AFIO_EXTICR1_EXTI2_PA ((uint32_t)0x00000000) /*!< PA[2] pin */
+#define AFIO_EXTICR1_EXTI2_PB_Pos (8U)
+#define AFIO_EXTICR1_EXTI2_PB_Msk (0x1U << AFIO_EXTICR1_EXTI2_PB_Pos) /*!< 0x00000100 */
+#define AFIO_EXTICR1_EXTI2_PB AFIO_EXTICR1_EXTI2_PB_Msk /*!< PB[2] pin */
+#define AFIO_EXTICR1_EXTI2_PC_Pos (9U)
+#define AFIO_EXTICR1_EXTI2_PC_Msk (0x1U << AFIO_EXTICR1_EXTI2_PC_Pos) /*!< 0x00000200 */
+#define AFIO_EXTICR1_EXTI2_PC AFIO_EXTICR1_EXTI2_PC_Msk /*!< PC[2] pin */
+#define AFIO_EXTICR1_EXTI2_PD_Pos (8U)
+#define AFIO_EXTICR1_EXTI2_PD_Msk (0x3U << AFIO_EXTICR1_EXTI2_PD_Pos) /*!< 0x00000300 */
+#define AFIO_EXTICR1_EXTI2_PD AFIO_EXTICR1_EXTI2_PD_Msk /*!< PD[2] pin */
+#define AFIO_EXTICR1_EXTI2_PE_Pos (10U)
+#define AFIO_EXTICR1_EXTI2_PE_Msk (0x1U << AFIO_EXTICR1_EXTI2_PE_Pos) /*!< 0x00000400 */
+#define AFIO_EXTICR1_EXTI2_PE AFIO_EXTICR1_EXTI2_PE_Msk /*!< PE[2] pin */
+#define AFIO_EXTICR1_EXTI2_PF_Pos (8U)
+#define AFIO_EXTICR1_EXTI2_PF_Msk (0x5U << AFIO_EXTICR1_EXTI2_PF_Pos) /*!< 0x00000500 */
+#define AFIO_EXTICR1_EXTI2_PF AFIO_EXTICR1_EXTI2_PF_Msk /*!< PF[2] pin */
+#define AFIO_EXTICR1_EXTI2_PG_Pos (9U)
+#define AFIO_EXTICR1_EXTI2_PG_Msk (0x3U << AFIO_EXTICR1_EXTI2_PG_Pos) /*!< 0x00000600 */
+#define AFIO_EXTICR1_EXTI2_PG AFIO_EXTICR1_EXTI2_PG_Msk /*!< PG[2] pin */
+
+/*!< EXTI3 configuration */
+#define AFIO_EXTICR1_EXTI3_PA ((uint32_t)0x00000000) /*!< PA[3] pin */
+#define AFIO_EXTICR1_EXTI3_PB_Pos (12U)
+#define AFIO_EXTICR1_EXTI3_PB_Msk (0x1U << AFIO_EXTICR1_EXTI3_PB_Pos) /*!< 0x00001000 */
+#define AFIO_EXTICR1_EXTI3_PB AFIO_EXTICR1_EXTI3_PB_Msk /*!< PB[3] pin */
+#define AFIO_EXTICR1_EXTI3_PC_Pos (13U)
+#define AFIO_EXTICR1_EXTI3_PC_Msk (0x1U << AFIO_EXTICR1_EXTI3_PC_Pos) /*!< 0x00002000 */
+#define AFIO_EXTICR1_EXTI3_PC AFIO_EXTICR1_EXTI3_PC_Msk /*!< PC[3] pin */
+#define AFIO_EXTICR1_EXTI3_PD_Pos (12U)
+#define AFIO_EXTICR1_EXTI3_PD_Msk (0x3U << AFIO_EXTICR1_EXTI3_PD_Pos) /*!< 0x00003000 */
+#define AFIO_EXTICR1_EXTI3_PD AFIO_EXTICR1_EXTI3_PD_Msk /*!< PD[3] pin */
+#define AFIO_EXTICR1_EXTI3_PE_Pos (14U)
+#define AFIO_EXTICR1_EXTI3_PE_Msk (0x1U << AFIO_EXTICR1_EXTI3_PE_Pos) /*!< 0x00004000 */
+#define AFIO_EXTICR1_EXTI3_PE AFIO_EXTICR1_EXTI3_PE_Msk /*!< PE[3] pin */
+#define AFIO_EXTICR1_EXTI3_PF_Pos (12U)
+#define AFIO_EXTICR1_EXTI3_PF_Msk (0x5U << AFIO_EXTICR1_EXTI3_PF_Pos) /*!< 0x00005000 */
+#define AFIO_EXTICR1_EXTI3_PF AFIO_EXTICR1_EXTI3_PF_Msk /*!< PF[3] pin */
+#define AFIO_EXTICR1_EXTI3_PG_Pos (13U)
+#define AFIO_EXTICR1_EXTI3_PG_Msk (0x3U << AFIO_EXTICR1_EXTI3_PG_Pos) /*!< 0x00006000 */
+#define AFIO_EXTICR1_EXTI3_PG AFIO_EXTICR1_EXTI3_PG_Msk /*!< PG[3] pin */
+
+/***************** Bit definition for AFIO_EXTICR2 register *****************/
+#define AFIO_EXTICR2_EXTI4_Pos (0U)
+#define AFIO_EXTICR2_EXTI4_Msk (0xFU << AFIO_EXTICR2_EXTI4_Pos) /*!< 0x0000000F */
+#define AFIO_EXTICR2_EXTI4 AFIO_EXTICR2_EXTI4_Msk /*!< EXTI 4 configuration */
+#define AFIO_EXTICR2_EXTI5_Pos (4U)
+#define AFIO_EXTICR2_EXTI5_Msk (0xFU << AFIO_EXTICR2_EXTI5_Pos) /*!< 0x000000F0 */
+#define AFIO_EXTICR2_EXTI5 AFIO_EXTICR2_EXTI5_Msk /*!< EXTI 5 configuration */
+#define AFIO_EXTICR2_EXTI6_Pos (8U)
+#define AFIO_EXTICR2_EXTI6_Msk (0xFU << AFIO_EXTICR2_EXTI6_Pos) /*!< 0x00000F00 */
+#define AFIO_EXTICR2_EXTI6 AFIO_EXTICR2_EXTI6_Msk /*!< EXTI 6 configuration */
+#define AFIO_EXTICR2_EXTI7_Pos (12U)
+#define AFIO_EXTICR2_EXTI7_Msk (0xFU << AFIO_EXTICR2_EXTI7_Pos) /*!< 0x0000F000 */
+#define AFIO_EXTICR2_EXTI7 AFIO_EXTICR2_EXTI7_Msk /*!< EXTI 7 configuration */
+
+/*!< EXTI4 configuration */
+#define AFIO_EXTICR2_EXTI4_PA ((uint32_t)0x00000000) /*!< PA[4] pin */
+#define AFIO_EXTICR2_EXTI4_PB_Pos (0U)
+#define AFIO_EXTICR2_EXTI4_PB_Msk (0x1U << AFIO_EXTICR2_EXTI4_PB_Pos) /*!< 0x00000001 */
+#define AFIO_EXTICR2_EXTI4_PB AFIO_EXTICR2_EXTI4_PB_Msk /*!< PB[4] pin */
+#define AFIO_EXTICR2_EXTI4_PC_Pos (1U)
+#define AFIO_EXTICR2_EXTI4_PC_Msk (0x1U << AFIO_EXTICR2_EXTI4_PC_Pos) /*!< 0x00000002 */
+#define AFIO_EXTICR2_EXTI4_PC AFIO_EXTICR2_EXTI4_PC_Msk /*!< PC[4] pin */
+#define AFIO_EXTICR2_EXTI4_PD_Pos (0U)
+#define AFIO_EXTICR2_EXTI4_PD_Msk (0x3U << AFIO_EXTICR2_EXTI4_PD_Pos) /*!< 0x00000003 */
+#define AFIO_EXTICR2_EXTI4_PD AFIO_EXTICR2_EXTI4_PD_Msk /*!< PD[4] pin */
+#define AFIO_EXTICR2_EXTI4_PE_Pos (2U)
+#define AFIO_EXTICR2_EXTI4_PE_Msk (0x1U << AFIO_EXTICR2_EXTI4_PE_Pos) /*!< 0x00000004 */
+#define AFIO_EXTICR2_EXTI4_PE AFIO_EXTICR2_EXTI4_PE_Msk /*!< PE[4] pin */
+#define AFIO_EXTICR2_EXTI4_PF_Pos (0U)
+#define AFIO_EXTICR2_EXTI4_PF_Msk (0x5U << AFIO_EXTICR2_EXTI4_PF_Pos) /*!< 0x00000005 */
+#define AFIO_EXTICR2_EXTI4_PF AFIO_EXTICR2_EXTI4_PF_Msk /*!< PF[4] pin */
+#define AFIO_EXTICR2_EXTI4_PG_Pos (1U)
+#define AFIO_EXTICR2_EXTI4_PG_Msk (0x3U << AFIO_EXTICR2_EXTI4_PG_Pos) /*!< 0x00000006 */
+#define AFIO_EXTICR2_EXTI4_PG AFIO_EXTICR2_EXTI4_PG_Msk /*!< PG[4] pin */
+
+/* EXTI5 configuration */
+#define AFIO_EXTICR2_EXTI5_PA ((uint32_t)0x00000000) /*!< PA[5] pin */
+#define AFIO_EXTICR2_EXTI5_PB_Pos (4U)
+#define AFIO_EXTICR2_EXTI5_PB_Msk (0x1U << AFIO_EXTICR2_EXTI5_PB_Pos) /*!< 0x00000010 */
+#define AFIO_EXTICR2_EXTI5_PB AFIO_EXTICR2_EXTI5_PB_Msk /*!< PB[5] pin */
+#define AFIO_EXTICR2_EXTI5_PC_Pos (5U)
+#define AFIO_EXTICR2_EXTI5_PC_Msk (0x1U << AFIO_EXTICR2_EXTI5_PC_Pos) /*!< 0x00000020 */
+#define AFIO_EXTICR2_EXTI5_PC AFIO_EXTICR2_EXTI5_PC_Msk /*!< PC[5] pin */
+#define AFIO_EXTICR2_EXTI5_PD_Pos (4U)
+#define AFIO_EXTICR2_EXTI5_PD_Msk (0x3U << AFIO_EXTICR2_EXTI5_PD_Pos) /*!< 0x00000030 */
+#define AFIO_EXTICR2_EXTI5_PD AFIO_EXTICR2_EXTI5_PD_Msk /*!< PD[5] pin */
+#define AFIO_EXTICR2_EXTI5_PE_Pos (6U)
+#define AFIO_EXTICR2_EXTI5_PE_Msk (0x1U << AFIO_EXTICR2_EXTI5_PE_Pos) /*!< 0x00000040 */
+#define AFIO_EXTICR2_EXTI5_PE AFIO_EXTICR2_EXTI5_PE_Msk /*!< PE[5] pin */
+#define AFIO_EXTICR2_EXTI5_PF_Pos (4U)
+#define AFIO_EXTICR2_EXTI5_PF_Msk (0x5U << AFIO_EXTICR2_EXTI5_PF_Pos) /*!< 0x00000050 */
+#define AFIO_EXTICR2_EXTI5_PF AFIO_EXTICR2_EXTI5_PF_Msk /*!< PF[5] pin */
+#define AFIO_EXTICR2_EXTI5_PG_Pos (5U)
+#define AFIO_EXTICR2_EXTI5_PG_Msk (0x3U << AFIO_EXTICR2_EXTI5_PG_Pos) /*!< 0x00000060 */
+#define AFIO_EXTICR2_EXTI5_PG AFIO_EXTICR2_EXTI5_PG_Msk /*!< PG[5] pin */
+
+/*!< EXTI6 configuration */
+#define AFIO_EXTICR2_EXTI6_PA ((uint32_t)0x00000000) /*!< PA[6] pin */
+#define AFIO_EXTICR2_EXTI6_PB_Pos (8U)
+#define AFIO_EXTICR2_EXTI6_PB_Msk (0x1U << AFIO_EXTICR2_EXTI6_PB_Pos) /*!< 0x00000100 */
+#define AFIO_EXTICR2_EXTI6_PB AFIO_EXTICR2_EXTI6_PB_Msk /*!< PB[6] pin */
+#define AFIO_EXTICR2_EXTI6_PC_Pos (9U)
+#define AFIO_EXTICR2_EXTI6_PC_Msk (0x1U << AFIO_EXTICR2_EXTI6_PC_Pos) /*!< 0x00000200 */
+#define AFIO_EXTICR2_EXTI6_PC AFIO_EXTICR2_EXTI6_PC_Msk /*!< PC[6] pin */
+#define AFIO_EXTICR2_EXTI6_PD_Pos (8U)
+#define AFIO_EXTICR2_EXTI6_PD_Msk (0x3U << AFIO_EXTICR2_EXTI6_PD_Pos) /*!< 0x00000300 */
+#define AFIO_EXTICR2_EXTI6_PD AFIO_EXTICR2_EXTI6_PD_Msk /*!< PD[6] pin */
+#define AFIO_EXTICR2_EXTI6_PE_Pos (10U)
+#define AFIO_EXTICR2_EXTI6_PE_Msk (0x1U << AFIO_EXTICR2_EXTI6_PE_Pos) /*!< 0x00000400 */
+#define AFIO_EXTICR2_EXTI6_PE AFIO_EXTICR2_EXTI6_PE_Msk /*!< PE[6] pin */
+#define AFIO_EXTICR2_EXTI6_PF_Pos (8U)
+#define AFIO_EXTICR2_EXTI6_PF_Msk (0x5U << AFIO_EXTICR2_EXTI6_PF_Pos) /*!< 0x00000500 */
+#define AFIO_EXTICR2_EXTI6_PF AFIO_EXTICR2_EXTI6_PF_Msk /*!< PF[6] pin */
+#define AFIO_EXTICR2_EXTI6_PG_Pos (9U)
+#define AFIO_EXTICR2_EXTI6_PG_Msk (0x3U << AFIO_EXTICR2_EXTI6_PG_Pos) /*!< 0x00000600 */
+#define AFIO_EXTICR2_EXTI6_PG AFIO_EXTICR2_EXTI6_PG_Msk /*!< PG[6] pin */
+
+/*!< EXTI7 configuration */
+#define AFIO_EXTICR2_EXTI7_PA ((uint32_t)0x00000000) /*!< PA[7] pin */
+#define AFIO_EXTICR2_EXTI7_PB_Pos (12U)
+#define AFIO_EXTICR2_EXTI7_PB_Msk (0x1U << AFIO_EXTICR2_EXTI7_PB_Pos) /*!< 0x00001000 */
+#define AFIO_EXTICR2_EXTI7_PB AFIO_EXTICR2_EXTI7_PB_Msk /*!< PB[7] pin */
+#define AFIO_EXTICR2_EXTI7_PC_Pos (13U)
+#define AFIO_EXTICR2_EXTI7_PC_Msk (0x1U << AFIO_EXTICR2_EXTI7_PC_Pos) /*!< 0x00002000 */
+#define AFIO_EXTICR2_EXTI7_PC AFIO_EXTICR2_EXTI7_PC_Msk /*!< PC[7] pin */
+#define AFIO_EXTICR2_EXTI7_PD_Pos (12U)
+#define AFIO_EXTICR2_EXTI7_PD_Msk (0x3U << AFIO_EXTICR2_EXTI7_PD_Pos) /*!< 0x00003000 */
+#define AFIO_EXTICR2_EXTI7_PD AFIO_EXTICR2_EXTI7_PD_Msk /*!< PD[7] pin */
+#define AFIO_EXTICR2_EXTI7_PE_Pos (14U)
+#define AFIO_EXTICR2_EXTI7_PE_Msk (0x1U << AFIO_EXTICR2_EXTI7_PE_Pos) /*!< 0x00004000 */
+#define AFIO_EXTICR2_EXTI7_PE AFIO_EXTICR2_EXTI7_PE_Msk /*!< PE[7] pin */
+#define AFIO_EXTICR2_EXTI7_PF_Pos (12U)
+#define AFIO_EXTICR2_EXTI7_PF_Msk (0x5U << AFIO_EXTICR2_EXTI7_PF_Pos) /*!< 0x00005000 */
+#define AFIO_EXTICR2_EXTI7_PF AFIO_EXTICR2_EXTI7_PF_Msk /*!< PF[7] pin */
+#define AFIO_EXTICR2_EXTI7_PG_Pos (13U)
+#define AFIO_EXTICR2_EXTI7_PG_Msk (0x3U << AFIO_EXTICR2_EXTI7_PG_Pos) /*!< 0x00006000 */
+#define AFIO_EXTICR2_EXTI7_PG AFIO_EXTICR2_EXTI7_PG_Msk /*!< PG[7] pin */
+
+/***************** Bit definition for AFIO_EXTICR3 register *****************/
+#define AFIO_EXTICR3_EXTI8_Pos (0U)
+#define AFIO_EXTICR3_EXTI8_Msk (0xFU << AFIO_EXTICR3_EXTI8_Pos) /*!< 0x0000000F */
+#define AFIO_EXTICR3_EXTI8 AFIO_EXTICR3_EXTI8_Msk /*!< EXTI 8 configuration */
+#define AFIO_EXTICR3_EXTI9_Pos (4U)
+#define AFIO_EXTICR3_EXTI9_Msk (0xFU << AFIO_EXTICR3_EXTI9_Pos) /*!< 0x000000F0 */
+#define AFIO_EXTICR3_EXTI9 AFIO_EXTICR3_EXTI9_Msk /*!< EXTI 9 configuration */
+#define AFIO_EXTICR3_EXTI10_Pos (8U)
+#define AFIO_EXTICR3_EXTI10_Msk (0xFU << AFIO_EXTICR3_EXTI10_Pos) /*!< 0x00000F00 */
+#define AFIO_EXTICR3_EXTI10 AFIO_EXTICR3_EXTI10_Msk /*!< EXTI 10 configuration */
+#define AFIO_EXTICR3_EXTI11_Pos (12U)
+#define AFIO_EXTICR3_EXTI11_Msk (0xFU << AFIO_EXTICR3_EXTI11_Pos) /*!< 0x0000F000 */
+#define AFIO_EXTICR3_EXTI11 AFIO_EXTICR3_EXTI11_Msk /*!< EXTI 11 configuration */
+
+/*!< EXTI8 configuration */
+#define AFIO_EXTICR3_EXTI8_PA ((uint32_t)0x00000000) /*!< PA[8] pin */
+#define AFIO_EXTICR3_EXTI8_PB_Pos (0U)
+#define AFIO_EXTICR3_EXTI8_PB_Msk (0x1U << AFIO_EXTICR3_EXTI8_PB_Pos) /*!< 0x00000001 */
+#define AFIO_EXTICR3_EXTI8_PB AFIO_EXTICR3_EXTI8_PB_Msk /*!< PB[8] pin */
+#define AFIO_EXTICR3_EXTI8_PC_Pos (1U)
+#define AFIO_EXTICR3_EXTI8_PC_Msk (0x1U << AFIO_EXTICR3_EXTI8_PC_Pos) /*!< 0x00000002 */
+#define AFIO_EXTICR3_EXTI8_PC AFIO_EXTICR3_EXTI8_PC_Msk /*!< PC[8] pin */
+#define AFIO_EXTICR3_EXTI8_PD_Pos (0U)
+#define AFIO_EXTICR3_EXTI8_PD_Msk (0x3U << AFIO_EXTICR3_EXTI8_PD_Pos) /*!< 0x00000003 */
+#define AFIO_EXTICR3_EXTI8_PD AFIO_EXTICR3_EXTI8_PD_Msk /*!< PD[8] pin */
+#define AFIO_EXTICR3_EXTI8_PE_Pos (2U)
+#define AFIO_EXTICR3_EXTI8_PE_Msk (0x1U << AFIO_EXTICR3_EXTI8_PE_Pos) /*!< 0x00000004 */
+#define AFIO_EXTICR3_EXTI8_PE AFIO_EXTICR3_EXTI8_PE_Msk /*!< PE[8] pin */
+#define AFIO_EXTICR3_EXTI8_PF_Pos (0U)
+#define AFIO_EXTICR3_EXTI8_PF_Msk (0x5U << AFIO_EXTICR3_EXTI8_PF_Pos) /*!< 0x00000005 */
+#define AFIO_EXTICR3_EXTI8_PF AFIO_EXTICR3_EXTI8_PF_Msk /*!< PF[8] pin */
+#define AFIO_EXTICR3_EXTI8_PG_Pos (1U)
+#define AFIO_EXTICR3_EXTI8_PG_Msk (0x3U << AFIO_EXTICR3_EXTI8_PG_Pos) /*!< 0x00000006 */
+#define AFIO_EXTICR3_EXTI8_PG AFIO_EXTICR3_EXTI8_PG_Msk /*!< PG[8] pin */
+
+/*!< EXTI9 configuration */
+#define AFIO_EXTICR3_EXTI9_PA ((uint32_t)0x00000000) /*!< PA[9] pin */
+#define AFIO_EXTICR3_EXTI9_PB_Pos (4U)
+#define AFIO_EXTICR3_EXTI9_PB_Msk (0x1U << AFIO_EXTICR3_EXTI9_PB_Pos) /*!< 0x00000010 */
+#define AFIO_EXTICR3_EXTI9_PB AFIO_EXTICR3_EXTI9_PB_Msk /*!< PB[9] pin */
+#define AFIO_EXTICR3_EXTI9_PC_Pos (5U)
+#define AFIO_EXTICR3_EXTI9_PC_Msk (0x1U << AFIO_EXTICR3_EXTI9_PC_Pos) /*!< 0x00000020 */
+#define AFIO_EXTICR3_EXTI9_PC AFIO_EXTICR3_EXTI9_PC_Msk /*!< PC[9] pin */
+#define AFIO_EXTICR3_EXTI9_PD_Pos (4U)
+#define AFIO_EXTICR3_EXTI9_PD_Msk (0x3U << AFIO_EXTICR3_EXTI9_PD_Pos) /*!< 0x00000030 */
+#define AFIO_EXTICR3_EXTI9_PD AFIO_EXTICR3_EXTI9_PD_Msk /*!< PD[9] pin */
+#define AFIO_EXTICR3_EXTI9_PE_Pos (6U)
+#define AFIO_EXTICR3_EXTI9_PE_Msk (0x1U << AFIO_EXTICR3_EXTI9_PE_Pos) /*!< 0x00000040 */
+#define AFIO_EXTICR3_EXTI9_PE AFIO_EXTICR3_EXTI9_PE_Msk /*!< PE[9] pin */
+#define AFIO_EXTICR3_EXTI9_PF_Pos (4U)
+#define AFIO_EXTICR3_EXTI9_PF_Msk (0x5U << AFIO_EXTICR3_EXTI9_PF_Pos) /*!< 0x00000050 */
+#define AFIO_EXTICR3_EXTI9_PF AFIO_EXTICR3_EXTI9_PF_Msk /*!< PF[9] pin */
+#define AFIO_EXTICR3_EXTI9_PG_Pos (5U)
+#define AFIO_EXTICR3_EXTI9_PG_Msk (0x3U << AFIO_EXTICR3_EXTI9_PG_Pos) /*!< 0x00000060 */
+#define AFIO_EXTICR3_EXTI9_PG AFIO_EXTICR3_EXTI9_PG_Msk /*!< PG[9] pin */
+
+/*!< EXTI10 configuration */
+#define AFIO_EXTICR3_EXTI10_PA ((uint32_t)0x00000000) /*!< PA[10] pin */
+#define AFIO_EXTICR3_EXTI10_PB_Pos (8U)
+#define AFIO_EXTICR3_EXTI10_PB_Msk (0x1U << AFIO_EXTICR3_EXTI10_PB_Pos) /*!< 0x00000100 */
+#define AFIO_EXTICR3_EXTI10_PB AFIO_EXTICR3_EXTI10_PB_Msk /*!< PB[10] pin */
+#define AFIO_EXTICR3_EXTI10_PC_Pos (9U)
+#define AFIO_EXTICR3_EXTI10_PC_Msk (0x1U << AFIO_EXTICR3_EXTI10_PC_Pos) /*!< 0x00000200 */
+#define AFIO_EXTICR3_EXTI10_PC AFIO_EXTICR3_EXTI10_PC_Msk /*!< PC[10] pin */
+#define AFIO_EXTICR3_EXTI10_PD_Pos (8U)
+#define AFIO_EXTICR3_EXTI10_PD_Msk (0x3U << AFIO_EXTICR3_EXTI10_PD_Pos) /*!< 0x00000300 */
+#define AFIO_EXTICR3_EXTI10_PD AFIO_EXTICR3_EXTI10_PD_Msk /*!< PD[10] pin */
+#define AFIO_EXTICR3_EXTI10_PE_Pos (10U)
+#define AFIO_EXTICR3_EXTI10_PE_Msk (0x1U << AFIO_EXTICR3_EXTI10_PE_Pos) /*!< 0x00000400 */
+#define AFIO_EXTICR3_EXTI10_PE AFIO_EXTICR3_EXTI10_PE_Msk /*!< PE[10] pin */
+#define AFIO_EXTICR3_EXTI10_PF_Pos (8U)
+#define AFIO_EXTICR3_EXTI10_PF_Msk (0x5U << AFIO_EXTICR3_EXTI10_PF_Pos) /*!< 0x00000500 */
+#define AFIO_EXTICR3_EXTI10_PF AFIO_EXTICR3_EXTI10_PF_Msk /*!< PF[10] pin */
+#define AFIO_EXTICR3_EXTI10_PG_Pos (9U)
+#define AFIO_EXTICR3_EXTI10_PG_Msk (0x3U << AFIO_EXTICR3_EXTI10_PG_Pos) /*!< 0x00000600 */
+#define AFIO_EXTICR3_EXTI10_PG AFIO_EXTICR3_EXTI10_PG_Msk /*!< PG[10] pin */
+
+/*!< EXTI11 configuration */
+#define AFIO_EXTICR3_EXTI11_PA ((uint32_t)0x00000000) /*!< PA[11] pin */
+#define AFIO_EXTICR3_EXTI11_PB_Pos (12U)
+#define AFIO_EXTICR3_EXTI11_PB_Msk (0x1U << AFIO_EXTICR3_EXTI11_PB_Pos) /*!< 0x00001000 */
+#define AFIO_EXTICR3_EXTI11_PB AFIO_EXTICR3_EXTI11_PB_Msk /*!< PB[11] pin */
+#define AFIO_EXTICR3_EXTI11_PC_Pos (13U)
+#define AFIO_EXTICR3_EXTI11_PC_Msk (0x1U << AFIO_EXTICR3_EXTI11_PC_Pos) /*!< 0x00002000 */
+#define AFIO_EXTICR3_EXTI11_PC AFIO_EXTICR3_EXTI11_PC_Msk /*!< PC[11] pin */
+#define AFIO_EXTICR3_EXTI11_PD_Pos (12U)
+#define AFIO_EXTICR3_EXTI11_PD_Msk (0x3U << AFIO_EXTICR3_EXTI11_PD_Pos) /*!< 0x00003000 */
+#define AFIO_EXTICR3_EXTI11_PD AFIO_EXTICR3_EXTI11_PD_Msk /*!< PD[11] pin */
+#define AFIO_EXTICR3_EXTI11_PE_Pos (14U)
+#define AFIO_EXTICR3_EXTI11_PE_Msk (0x1U << AFIO_EXTICR3_EXTI11_PE_Pos) /*!< 0x00004000 */
+#define AFIO_EXTICR3_EXTI11_PE AFIO_EXTICR3_EXTI11_PE_Msk /*!< PE[11] pin */
+#define AFIO_EXTICR3_EXTI11_PF_Pos (12U)
+#define AFIO_EXTICR3_EXTI11_PF_Msk (0x5U << AFIO_EXTICR3_EXTI11_PF_Pos) /*!< 0x00005000 */
+#define AFIO_EXTICR3_EXTI11_PF AFIO_EXTICR3_EXTI11_PF_Msk /*!< PF[11] pin */
+#define AFIO_EXTICR3_EXTI11_PG_Pos (13U)
+#define AFIO_EXTICR3_EXTI11_PG_Msk (0x3U << AFIO_EXTICR3_EXTI11_PG_Pos) /*!< 0x00006000 */
+#define AFIO_EXTICR3_EXTI11_PG AFIO_EXTICR3_EXTI11_PG_Msk /*!< PG[11] pin */
+
+/***************** Bit definition for AFIO_EXTICR4 register *****************/
+#define AFIO_EXTICR4_EXTI12_Pos (0U)
+#define AFIO_EXTICR4_EXTI12_Msk (0xFU << AFIO_EXTICR4_EXTI12_Pos) /*!< 0x0000000F */
+#define AFIO_EXTICR4_EXTI12 AFIO_EXTICR4_EXTI12_Msk /*!< EXTI 12 configuration */
+#define AFIO_EXTICR4_EXTI13_Pos (4U)
+#define AFIO_EXTICR4_EXTI13_Msk (0xFU << AFIO_EXTICR4_EXTI13_Pos) /*!< 0x000000F0 */
+#define AFIO_EXTICR4_EXTI13 AFIO_EXTICR4_EXTI13_Msk /*!< EXTI 13 configuration */
+#define AFIO_EXTICR4_EXTI14_Pos (8U)
+#define AFIO_EXTICR4_EXTI14_Msk (0xFU << AFIO_EXTICR4_EXTI14_Pos) /*!< 0x00000F00 */
+#define AFIO_EXTICR4_EXTI14 AFIO_EXTICR4_EXTI14_Msk /*!< EXTI 14 configuration */
+#define AFIO_EXTICR4_EXTI15_Pos (12U)
+#define AFIO_EXTICR4_EXTI15_Msk (0xFU << AFIO_EXTICR4_EXTI15_Pos) /*!< 0x0000F000 */
+#define AFIO_EXTICR4_EXTI15 AFIO_EXTICR4_EXTI15_Msk /*!< EXTI 15 configuration */
+
+/* EXTI12 configuration */
+#define AFIO_EXTICR4_EXTI12_PA ((uint32_t)0x00000000) /*!< PA[12] pin */
+#define AFIO_EXTICR4_EXTI12_PB_Pos (0U)
+#define AFIO_EXTICR4_EXTI12_PB_Msk (0x1U << AFIO_EXTICR4_EXTI12_PB_Pos) /*!< 0x00000001 */
+#define AFIO_EXTICR4_EXTI12_PB AFIO_EXTICR4_EXTI12_PB_Msk /*!< PB[12] pin */
+#define AFIO_EXTICR4_EXTI12_PC_Pos (1U)
+#define AFIO_EXTICR4_EXTI12_PC_Msk (0x1U << AFIO_EXTICR4_EXTI12_PC_Pos) /*!< 0x00000002 */
+#define AFIO_EXTICR4_EXTI12_PC AFIO_EXTICR4_EXTI12_PC_Msk /*!< PC[12] pin */
+#define AFIO_EXTICR4_EXTI12_PD_Pos (0U)
+#define AFIO_EXTICR4_EXTI12_PD_Msk (0x3U << AFIO_EXTICR4_EXTI12_PD_Pos) /*!< 0x00000003 */
+#define AFIO_EXTICR4_EXTI12_PD AFIO_EXTICR4_EXTI12_PD_Msk /*!< PD[12] pin */
+#define AFIO_EXTICR4_EXTI12_PE_Pos (2U)
+#define AFIO_EXTICR4_EXTI12_PE_Msk (0x1U << AFIO_EXTICR4_EXTI12_PE_Pos) /*!< 0x00000004 */
+#define AFIO_EXTICR4_EXTI12_PE AFIO_EXTICR4_EXTI12_PE_Msk /*!< PE[12] pin */
+#define AFIO_EXTICR4_EXTI12_PF_Pos (0U)
+#define AFIO_EXTICR4_EXTI12_PF_Msk (0x5U << AFIO_EXTICR4_EXTI12_PF_Pos) /*!< 0x00000005 */
+#define AFIO_EXTICR4_EXTI12_PF AFIO_EXTICR4_EXTI12_PF_Msk /*!< PF[12] pin */
+#define AFIO_EXTICR4_EXTI12_PG_Pos (1U)
+#define AFIO_EXTICR4_EXTI12_PG_Msk (0x3U << AFIO_EXTICR4_EXTI12_PG_Pos) /*!< 0x00000006 */
+#define AFIO_EXTICR4_EXTI12_PG AFIO_EXTICR4_EXTI12_PG_Msk /*!< PG[12] pin */
+
+/* EXTI13 configuration */
+#define AFIO_EXTICR4_EXTI13_PA ((uint32_t)0x00000000) /*!< PA[13] pin */
+#define AFIO_EXTICR4_EXTI13_PB_Pos (4U)
+#define AFIO_EXTICR4_EXTI13_PB_Msk (0x1U << AFIO_EXTICR4_EXTI13_PB_Pos) /*!< 0x00000010 */
+#define AFIO_EXTICR4_EXTI13_PB AFIO_EXTICR4_EXTI13_PB_Msk /*!< PB[13] pin */
+#define AFIO_EXTICR4_EXTI13_PC_Pos (5U)
+#define AFIO_EXTICR4_EXTI13_PC_Msk (0x1U << AFIO_EXTICR4_EXTI13_PC_Pos) /*!< 0x00000020 */
+#define AFIO_EXTICR4_EXTI13_PC AFIO_EXTICR4_EXTI13_PC_Msk /*!< PC[13] pin */
+#define AFIO_EXTICR4_EXTI13_PD_Pos (4U)
+#define AFIO_EXTICR4_EXTI13_PD_Msk (0x3U << AFIO_EXTICR4_EXTI13_PD_Pos) /*!< 0x00000030 */
+#define AFIO_EXTICR4_EXTI13_PD AFIO_EXTICR4_EXTI13_PD_Msk /*!< PD[13] pin */
+#define AFIO_EXTICR4_EXTI13_PE_Pos (6U)
+#define AFIO_EXTICR4_EXTI13_PE_Msk (0x1U << AFIO_EXTICR4_EXTI13_PE_Pos) /*!< 0x00000040 */
+#define AFIO_EXTICR4_EXTI13_PE AFIO_EXTICR4_EXTI13_PE_Msk /*!< PE[13] pin */
+#define AFIO_EXTICR4_EXTI13_PF_Pos (4U)
+#define AFIO_EXTICR4_EXTI13_PF_Msk (0x5U << AFIO_EXTICR4_EXTI13_PF_Pos) /*!< 0x00000050 */
+#define AFIO_EXTICR4_EXTI13_PF AFIO_EXTICR4_EXTI13_PF_Msk /*!< PF[13] pin */
+#define AFIO_EXTICR4_EXTI13_PG_Pos (5U)
+#define AFIO_EXTICR4_EXTI13_PG_Msk (0x3U << AFIO_EXTICR4_EXTI13_PG_Pos) /*!< 0x00000060 */
+#define AFIO_EXTICR4_EXTI13_PG AFIO_EXTICR4_EXTI13_PG_Msk /*!< PG[13] pin */
+
+/*!< EXTI14 configuration */
+#define AFIO_EXTICR4_EXTI14_PA ((uint32_t)0x00000000) /*!< PA[14] pin */
+#define AFIO_EXTICR4_EXTI14_PB_Pos (8U)
+#define AFIO_EXTICR4_EXTI14_PB_Msk (0x1U << AFIO_EXTICR4_EXTI14_PB_Pos) /*!< 0x00000100 */
+#define AFIO_EXTICR4_EXTI14_PB AFIO_EXTICR4_EXTI14_PB_Msk /*!< PB[14] pin */
+#define AFIO_EXTICR4_EXTI14_PC_Pos (9U)
+#define AFIO_EXTICR4_EXTI14_PC_Msk (0x1U << AFIO_EXTICR4_EXTI14_PC_Pos) /*!< 0x00000200 */
+#define AFIO_EXTICR4_EXTI14_PC AFIO_EXTICR4_EXTI14_PC_Msk /*!< PC[14] pin */
+#define AFIO_EXTICR4_EXTI14_PD_Pos (8U)
+#define AFIO_EXTICR4_EXTI14_PD_Msk (0x3U << AFIO_EXTICR4_EXTI14_PD_Pos) /*!< 0x00000300 */
+#define AFIO_EXTICR4_EXTI14_PD AFIO_EXTICR4_EXTI14_PD_Msk /*!< PD[14] pin */
+#define AFIO_EXTICR4_EXTI14_PE_Pos (10U)
+#define AFIO_EXTICR4_EXTI14_PE_Msk (0x1U << AFIO_EXTICR4_EXTI14_PE_Pos) /*!< 0x00000400 */
+#define AFIO_EXTICR4_EXTI14_PE AFIO_EXTICR4_EXTI14_PE_Msk /*!< PE[14] pin */
+#define AFIO_EXTICR4_EXTI14_PF_Pos (8U)
+#define AFIO_EXTICR4_EXTI14_PF_Msk (0x5U << AFIO_EXTICR4_EXTI14_PF_Pos) /*!< 0x00000500 */
+#define AFIO_EXTICR4_EXTI14_PF AFIO_EXTICR4_EXTI14_PF_Msk /*!< PF[14] pin */
+#define AFIO_EXTICR4_EXTI14_PG_Pos (9U)
+#define AFIO_EXTICR4_EXTI14_PG_Msk (0x3U << AFIO_EXTICR4_EXTI14_PG_Pos) /*!< 0x00000600 */
+#define AFIO_EXTICR4_EXTI14_PG AFIO_EXTICR4_EXTI14_PG_Msk /*!< PG[14] pin */
+
+/*!< EXTI15 configuration */
+#define AFIO_EXTICR4_EXTI15_PA ((uint32_t)0x00000000) /*!< PA[15] pin */
+#define AFIO_EXTICR4_EXTI15_PB_Pos (12U)
+#define AFIO_EXTICR4_EXTI15_PB_Msk (0x1U << AFIO_EXTICR4_EXTI15_PB_Pos) /*!< 0x00001000 */
+#define AFIO_EXTICR4_EXTI15_PB AFIO_EXTICR4_EXTI15_PB_Msk /*!< PB[15] pin */
+#define AFIO_EXTICR4_EXTI15_PC_Pos (13U)
+#define AFIO_EXTICR4_EXTI15_PC_Msk (0x1U << AFIO_EXTICR4_EXTI15_PC_Pos) /*!< 0x00002000 */
+#define AFIO_EXTICR4_EXTI15_PC AFIO_EXTICR4_EXTI15_PC_Msk /*!< PC[15] pin */
+#define AFIO_EXTICR4_EXTI15_PD_Pos (12U)
+#define AFIO_EXTICR4_EXTI15_PD_Msk (0x3U << AFIO_EXTICR4_EXTI15_PD_Pos) /*!< 0x00003000 */
+#define AFIO_EXTICR4_EXTI15_PD AFIO_EXTICR4_EXTI15_PD_Msk /*!< PD[15] pin */
+#define AFIO_EXTICR4_EXTI15_PE_Pos (14U)
+#define AFIO_EXTICR4_EXTI15_PE_Msk (0x1U << AFIO_EXTICR4_EXTI15_PE_Pos) /*!< 0x00004000 */
+#define AFIO_EXTICR4_EXTI15_PE AFIO_EXTICR4_EXTI15_PE_Msk /*!< PE[15] pin */
+#define AFIO_EXTICR4_EXTI15_PF_Pos (12U)
+#define AFIO_EXTICR4_EXTI15_PF_Msk (0x5U << AFIO_EXTICR4_EXTI15_PF_Pos) /*!< 0x00005000 */
+#define AFIO_EXTICR4_EXTI15_PF AFIO_EXTICR4_EXTI15_PF_Msk /*!< PF[15] pin */
+#define AFIO_EXTICR4_EXTI15_PG_Pos (13U)
+#define AFIO_EXTICR4_EXTI15_PG_Msk (0x3U << AFIO_EXTICR4_EXTI15_PG_Pos) /*!< 0x00006000 */
+#define AFIO_EXTICR4_EXTI15_PG AFIO_EXTICR4_EXTI15_PG_Msk /*!< PG[15] pin */
+
+/****************** Bit definition for AFIO_MAPR2 register ******************/
+
+
+
+/******************************************************************************/
+/* */
+/* SystemTick */
+/* */
+/******************************************************************************/
+
+/***************** Bit definition for SysTick_CTRL register *****************/
+#define SysTick_CTRL_ENABLE ((uint32_t)0x00000001) /*!< Counter enable */
+#define SysTick_CTRL_TICKINT ((uint32_t)0x00000002) /*!< Counting down to 0 pends the SysTick handler */
+#define SysTick_CTRL_CLKSOURCE ((uint32_t)0x00000004) /*!< Clock source */
+#define SysTick_CTRL_COUNTFLAG ((uint32_t)0x00010000) /*!< Count Flag */
+
+/***************** Bit definition for SysTick_LOAD register *****************/
+#define SysTick_LOAD_RELOAD ((uint32_t)0x00FFFFFF) /*!< Value to load into the SysTick Current Value Register when the counter reaches 0 */
+
+/***************** Bit definition for SysTick_VAL register ******************/
+#define SysTick_VAL_CURRENT ((uint32_t)0x00FFFFFF) /*!< Current value at the time the register is accessed */
+
+/***************** Bit definition for SysTick_CALIB register ****************/
+#define SysTick_CALIB_TENMS ((uint32_t)0x00FFFFFF) /*!< Reload value to use for 10ms timing */
+#define SysTick_CALIB_SKEW ((uint32_t)0x40000000) /*!< Calibration value is not exactly 10 ms */
+#define SysTick_CALIB_NOREF ((uint32_t)0x80000000) /*!< The reference clock is not provided */
+
+/******************************************************************************/
+/* */
+/* Nested Vectored Interrupt Controller */
+/* */
+/******************************************************************************/
+
+/****************** Bit definition for NVIC_ISER register *******************/
+#define NVIC_ISER_SETENA_Pos (0U)
+#define NVIC_ISER_SETENA_Msk (0xFFFFFFFFU << NVIC_ISER_SETENA_Pos) /*!< 0xFFFFFFFF */
+#define NVIC_ISER_SETENA NVIC_ISER_SETENA_Msk /*!< Interrupt set enable bits */
+#define NVIC_ISER_SETENA_0 (0x00000001U << NVIC_ISER_SETENA_Pos) /*!< 0x00000001 */
+#define NVIC_ISER_SETENA_1 (0x00000002U << NVIC_ISER_SETENA_Pos) /*!< 0x00000002 */
+#define NVIC_ISER_SETENA_2 (0x00000004U << NVIC_ISER_SETENA_Pos) /*!< 0x00000004 */
+#define NVIC_ISER_SETENA_3 (0x00000008U << NVIC_ISER_SETENA_Pos) /*!< 0x00000008 */
+#define NVIC_ISER_SETENA_4 (0x00000010U << NVIC_ISER_SETENA_Pos) /*!< 0x00000010 */
+#define NVIC_ISER_SETENA_5 (0x00000020U << NVIC_ISER_SETENA_Pos) /*!< 0x00000020 */
+#define NVIC_ISER_SETENA_6 (0x00000040U << NVIC_ISER_SETENA_Pos) /*!< 0x00000040 */
+#define NVIC_ISER_SETENA_7 (0x00000080U << NVIC_ISER_SETENA_Pos) /*!< 0x00000080 */
+#define NVIC_ISER_SETENA_8 (0x00000100U << NVIC_ISER_SETENA_Pos) /*!< 0x00000100 */
+#define NVIC_ISER_SETENA_9 (0x00000200U << NVIC_ISER_SETENA_Pos) /*!< 0x00000200 */
+#define NVIC_ISER_SETENA_10 (0x00000400U << NVIC_ISER_SETENA_Pos) /*!< 0x00000400 */
+#define NVIC_ISER_SETENA_11 (0x00000800U << NVIC_ISER_SETENA_Pos) /*!< 0x00000800 */
+#define NVIC_ISER_SETENA_12 (0x00001000U << NVIC_ISER_SETENA_Pos) /*!< 0x00001000 */
+#define NVIC_ISER_SETENA_13 (0x00002000U << NVIC_ISER_SETENA_Pos) /*!< 0x00002000 */
+#define NVIC_ISER_SETENA_14 (0x00004000U << NVIC_ISER_SETENA_Pos) /*!< 0x00004000 */
+#define NVIC_ISER_SETENA_15 (0x00008000U << NVIC_ISER_SETENA_Pos) /*!< 0x00008000 */
+#define NVIC_ISER_SETENA_16 (0x00010000U << NVIC_ISER_SETENA_Pos) /*!< 0x00010000 */
+#define NVIC_ISER_SETENA_17 (0x00020000U << NVIC_ISER_SETENA_Pos) /*!< 0x00020000 */
+#define NVIC_ISER_SETENA_18 (0x00040000U << NVIC_ISER_SETENA_Pos) /*!< 0x00040000 */
+#define NVIC_ISER_SETENA_19 (0x00080000U << NVIC_ISER_SETENA_Pos) /*!< 0x00080000 */
+#define NVIC_ISER_SETENA_20 (0x00100000U << NVIC_ISER_SETENA_Pos) /*!< 0x00100000 */
+#define NVIC_ISER_SETENA_21 (0x00200000U << NVIC_ISER_SETENA_Pos) /*!< 0x00200000 */
+#define NVIC_ISER_SETENA_22 (0x00400000U << NVIC_ISER_SETENA_Pos) /*!< 0x00400000 */
+#define NVIC_ISER_SETENA_23 (0x00800000U << NVIC_ISER_SETENA_Pos) /*!< 0x00800000 */
+#define NVIC_ISER_SETENA_24 (0x01000000U << NVIC_ISER_SETENA_Pos) /*!< 0x01000000 */
+#define NVIC_ISER_SETENA_25 (0x02000000U << NVIC_ISER_SETENA_Pos) /*!< 0x02000000 */
+#define NVIC_ISER_SETENA_26 (0x04000000U << NVIC_ISER_SETENA_Pos) /*!< 0x04000000 */
+#define NVIC_ISER_SETENA_27 (0x08000000U << NVIC_ISER_SETENA_Pos) /*!< 0x08000000 */
+#define NVIC_ISER_SETENA_28 (0x10000000U << NVIC_ISER_SETENA_Pos) /*!< 0x10000000 */
+#define NVIC_ISER_SETENA_29 (0x20000000U << NVIC_ISER_SETENA_Pos) /*!< 0x20000000 */
+#define NVIC_ISER_SETENA_30 (0x40000000U << NVIC_ISER_SETENA_Pos) /*!< 0x40000000 */
+#define NVIC_ISER_SETENA_31 (0x80000000U << NVIC_ISER_SETENA_Pos) /*!< 0x80000000 */
+
+/****************** Bit definition for NVIC_ICER register *******************/
+#define NVIC_ICER_CLRENA_Pos (0U)
+#define NVIC_ICER_CLRENA_Msk (0xFFFFFFFFU << NVIC_ICER_CLRENA_Pos) /*!< 0xFFFFFFFF */
+#define NVIC_ICER_CLRENA NVIC_ICER_CLRENA_Msk /*!< Interrupt clear-enable bits */
+#define NVIC_ICER_CLRENA_0 (0x00000001U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000001 */
+#define NVIC_ICER_CLRENA_1 (0x00000002U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000002 */
+#define NVIC_ICER_CLRENA_2 (0x00000004U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000004 */
+#define NVIC_ICER_CLRENA_3 (0x00000008U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000008 */
+#define NVIC_ICER_CLRENA_4 (0x00000010U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000010 */
+#define NVIC_ICER_CLRENA_5 (0x00000020U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000020 */
+#define NVIC_ICER_CLRENA_6 (0x00000040U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000040 */
+#define NVIC_ICER_CLRENA_7 (0x00000080U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000080 */
+#define NVIC_ICER_CLRENA_8 (0x00000100U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000100 */
+#define NVIC_ICER_CLRENA_9 (0x00000200U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000200 */
+#define NVIC_ICER_CLRENA_10 (0x00000400U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000400 */
+#define NVIC_ICER_CLRENA_11 (0x00000800U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000800 */
+#define NVIC_ICER_CLRENA_12 (0x00001000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00001000 */
+#define NVIC_ICER_CLRENA_13 (0x00002000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00002000 */
+#define NVIC_ICER_CLRENA_14 (0x00004000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00004000 */
+#define NVIC_ICER_CLRENA_15 (0x00008000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00008000 */
+#define NVIC_ICER_CLRENA_16 (0x00010000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00010000 */
+#define NVIC_ICER_CLRENA_17 (0x00020000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00020000 */
+#define NVIC_ICER_CLRENA_18 (0x00040000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00040000 */
+#define NVIC_ICER_CLRENA_19 (0x00080000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00080000 */
+#define NVIC_ICER_CLRENA_20 (0x00100000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00100000 */
+#define NVIC_ICER_CLRENA_21 (0x00200000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00200000 */
+#define NVIC_ICER_CLRENA_22 (0x00400000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00400000 */
+#define NVIC_ICER_CLRENA_23 (0x00800000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00800000 */
+#define NVIC_ICER_CLRENA_24 (0x01000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x01000000 */
+#define NVIC_ICER_CLRENA_25 (0x02000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x02000000 */
+#define NVIC_ICER_CLRENA_26 (0x04000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x04000000 */
+#define NVIC_ICER_CLRENA_27 (0x08000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x08000000 */
+#define NVIC_ICER_CLRENA_28 (0x10000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x10000000 */
+#define NVIC_ICER_CLRENA_29 (0x20000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x20000000 */
+#define NVIC_ICER_CLRENA_30 (0x40000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x40000000 */
+#define NVIC_ICER_CLRENA_31 (0x80000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x80000000 */
+
+/****************** Bit definition for NVIC_ISPR register *******************/
+#define NVIC_ISPR_SETPEND_Pos (0U)
+#define NVIC_ISPR_SETPEND_Msk (0xFFFFFFFFU << NVIC_ISPR_SETPEND_Pos) /*!< 0xFFFFFFFF */
+#define NVIC_ISPR_SETPEND NVIC_ISPR_SETPEND_Msk /*!< Interrupt set-pending bits */
+#define NVIC_ISPR_SETPEND_0 (0x00000001U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000001 */
+#define NVIC_ISPR_SETPEND_1 (0x00000002U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000002 */
+#define NVIC_ISPR_SETPEND_2 (0x00000004U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000004 */
+#define NVIC_ISPR_SETPEND_3 (0x00000008U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000008 */
+#define NVIC_ISPR_SETPEND_4 (0x00000010U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000010 */
+#define NVIC_ISPR_SETPEND_5 (0x00000020U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000020 */
+#define NVIC_ISPR_SETPEND_6 (0x00000040U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000040 */
+#define NVIC_ISPR_SETPEND_7 (0x00000080U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000080 */
+#define NVIC_ISPR_SETPEND_8 (0x00000100U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000100 */
+#define NVIC_ISPR_SETPEND_9 (0x00000200U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000200 */
+#define NVIC_ISPR_SETPEND_10 (0x00000400U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000400 */
+#define NVIC_ISPR_SETPEND_11 (0x00000800U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000800 */
+#define NVIC_ISPR_SETPEND_12 (0x00001000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00001000 */
+#define NVIC_ISPR_SETPEND_13 (0x00002000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00002000 */
+#define NVIC_ISPR_SETPEND_14 (0x00004000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00004000 */
+#define NVIC_ISPR_SETPEND_15 (0x00008000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00008000 */
+#define NVIC_ISPR_SETPEND_16 (0x00010000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00010000 */
+#define NVIC_ISPR_SETPEND_17 (0x00020000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00020000 */
+#define NVIC_ISPR_SETPEND_18 (0x00040000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00040000 */
+#define NVIC_ISPR_SETPEND_19 (0x00080000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00080000 */
+#define NVIC_ISPR_SETPEND_20 (0x00100000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00100000 */
+#define NVIC_ISPR_SETPEND_21 (0x00200000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00200000 */
+#define NVIC_ISPR_SETPEND_22 (0x00400000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00400000 */
+#define NVIC_ISPR_SETPEND_23 (0x00800000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00800000 */
+#define NVIC_ISPR_SETPEND_24 (0x01000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x01000000 */
+#define NVIC_ISPR_SETPEND_25 (0x02000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x02000000 */
+#define NVIC_ISPR_SETPEND_26 (0x04000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x04000000 */
+#define NVIC_ISPR_SETPEND_27 (0x08000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x08000000 */
+#define NVIC_ISPR_SETPEND_28 (0x10000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x10000000 */
+#define NVIC_ISPR_SETPEND_29 (0x20000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x20000000 */
+#define NVIC_ISPR_SETPEND_30 (0x40000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x40000000 */
+#define NVIC_ISPR_SETPEND_31 (0x80000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x80000000 */
+
+/****************** Bit definition for NVIC_ICPR register *******************/
+#define NVIC_ICPR_CLRPEND_Pos (0U)
+#define NVIC_ICPR_CLRPEND_Msk (0xFFFFFFFFU << NVIC_ICPR_CLRPEND_Pos) /*!< 0xFFFFFFFF */
+#define NVIC_ICPR_CLRPEND NVIC_ICPR_CLRPEND_Msk /*!< Interrupt clear-pending bits */
+#define NVIC_ICPR_CLRPEND_0 (0x00000001U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000001 */
+#define NVIC_ICPR_CLRPEND_1 (0x00000002U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000002 */
+#define NVIC_ICPR_CLRPEND_2 (0x00000004U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000004 */
+#define NVIC_ICPR_CLRPEND_3 (0x00000008U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000008 */
+#define NVIC_ICPR_CLRPEND_4 (0x00000010U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000010 */
+#define NVIC_ICPR_CLRPEND_5 (0x00000020U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000020 */
+#define NVIC_ICPR_CLRPEND_6 (0x00000040U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000040 */
+#define NVIC_ICPR_CLRPEND_7 (0x00000080U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000080 */
+#define NVIC_ICPR_CLRPEND_8 (0x00000100U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000100 */
+#define NVIC_ICPR_CLRPEND_9 (0x00000200U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000200 */
+#define NVIC_ICPR_CLRPEND_10 (0x00000400U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000400 */
+#define NVIC_ICPR_CLRPEND_11 (0x00000800U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000800 */
+#define NVIC_ICPR_CLRPEND_12 (0x00001000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00001000 */
+#define NVIC_ICPR_CLRPEND_13 (0x00002000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00002000 */
+#define NVIC_ICPR_CLRPEND_14 (0x00004000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00004000 */
+#define NVIC_ICPR_CLRPEND_15 (0x00008000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00008000 */
+#define NVIC_ICPR_CLRPEND_16 (0x00010000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00010000 */
+#define NVIC_ICPR_CLRPEND_17 (0x00020000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00020000 */
+#define NVIC_ICPR_CLRPEND_18 (0x00040000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00040000 */
+#define NVIC_ICPR_CLRPEND_19 (0x00080000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00080000 */
+#define NVIC_ICPR_CLRPEND_20 (0x00100000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00100000 */
+#define NVIC_ICPR_CLRPEND_21 (0x00200000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00200000 */
+#define NVIC_ICPR_CLRPEND_22 (0x00400000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00400000 */
+#define NVIC_ICPR_CLRPEND_23 (0x00800000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00800000 */
+#define NVIC_ICPR_CLRPEND_24 (0x01000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x01000000 */
+#define NVIC_ICPR_CLRPEND_25 (0x02000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x02000000 */
+#define NVIC_ICPR_CLRPEND_26 (0x04000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x04000000 */
+#define NVIC_ICPR_CLRPEND_27 (0x08000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x08000000 */
+#define NVIC_ICPR_CLRPEND_28 (0x10000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x10000000 */
+#define NVIC_ICPR_CLRPEND_29 (0x20000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x20000000 */
+#define NVIC_ICPR_CLRPEND_30 (0x40000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x40000000 */
+#define NVIC_ICPR_CLRPEND_31 (0x80000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x80000000 */
+
+/****************** Bit definition for NVIC_IABR register *******************/
+#define NVIC_IABR_ACTIVE_Pos (0U)
+#define NVIC_IABR_ACTIVE_Msk (0xFFFFFFFFU << NVIC_IABR_ACTIVE_Pos) /*!< 0xFFFFFFFF */
+#define NVIC_IABR_ACTIVE NVIC_IABR_ACTIVE_Msk /*!< Interrupt active flags */
+#define NVIC_IABR_ACTIVE_0 (0x00000001U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000001 */
+#define NVIC_IABR_ACTIVE_1 (0x00000002U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000002 */
+#define NVIC_IABR_ACTIVE_2 (0x00000004U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000004 */
+#define NVIC_IABR_ACTIVE_3 (0x00000008U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000008 */
+#define NVIC_IABR_ACTIVE_4 (0x00000010U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000010 */
+#define NVIC_IABR_ACTIVE_5 (0x00000020U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000020 */
+#define NVIC_IABR_ACTIVE_6 (0x00000040U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000040 */
+#define NVIC_IABR_ACTIVE_7 (0x00000080U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000080 */
+#define NVIC_IABR_ACTIVE_8 (0x00000100U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000100 */
+#define NVIC_IABR_ACTIVE_9 (0x00000200U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000200 */
+#define NVIC_IABR_ACTIVE_10 (0x00000400U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000400 */
+#define NVIC_IABR_ACTIVE_11 (0x00000800U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000800 */
+#define NVIC_IABR_ACTIVE_12 (0x00001000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00001000 */
+#define NVIC_IABR_ACTIVE_13 (0x00002000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00002000 */
+#define NVIC_IABR_ACTIVE_14 (0x00004000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00004000 */
+#define NVIC_IABR_ACTIVE_15 (0x00008000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00008000 */
+#define NVIC_IABR_ACTIVE_16 (0x00010000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00010000 */
+#define NVIC_IABR_ACTIVE_17 (0x00020000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00020000 */
+#define NVIC_IABR_ACTIVE_18 (0x00040000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00040000 */
+#define NVIC_IABR_ACTIVE_19 (0x00080000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00080000 */
+#define NVIC_IABR_ACTIVE_20 (0x00100000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00100000 */
+#define NVIC_IABR_ACTIVE_21 (0x00200000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00200000 */
+#define NVIC_IABR_ACTIVE_22 (0x00400000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00400000 */
+#define NVIC_IABR_ACTIVE_23 (0x00800000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00800000 */
+#define NVIC_IABR_ACTIVE_24 (0x01000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x01000000 */
+#define NVIC_IABR_ACTIVE_25 (0x02000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x02000000 */
+#define NVIC_IABR_ACTIVE_26 (0x04000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x04000000 */
+#define NVIC_IABR_ACTIVE_27 (0x08000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x08000000 */
+#define NVIC_IABR_ACTIVE_28 (0x10000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x10000000 */
+#define NVIC_IABR_ACTIVE_29 (0x20000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x20000000 */
+#define NVIC_IABR_ACTIVE_30 (0x40000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x40000000 */
+#define NVIC_IABR_ACTIVE_31 (0x80000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x80000000 */
+
+/****************** Bit definition for NVIC_PRI0 register *******************/
+#define NVIC_IPR0_PRI_0 ((uint32_t)0x000000FF) /*!< Priority of interrupt 0 */
+#define NVIC_IPR0_PRI_1 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 1 */
+#define NVIC_IPR0_PRI_2 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 2 */
+#define NVIC_IPR0_PRI_3 ((uint32_t)0xFF000000) /*!< Priority of interrupt 3 */
+
+/****************** Bit definition for NVIC_PRI1 register *******************/
+#define NVIC_IPR1_PRI_4 ((uint32_t)0x000000FF) /*!< Priority of interrupt 4 */
+#define NVIC_IPR1_PRI_5 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 5 */
+#define NVIC_IPR1_PRI_6 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 6 */
+#define NVIC_IPR1_PRI_7 ((uint32_t)0xFF000000) /*!< Priority of interrupt 7 */
+
+/****************** Bit definition for NVIC_PRI2 register *******************/
+#define NVIC_IPR2_PRI_8 ((uint32_t)0x000000FF) /*!< Priority of interrupt 8 */
+#define NVIC_IPR2_PRI_9 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 9 */
+#define NVIC_IPR2_PRI_10 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 10 */
+#define NVIC_IPR2_PRI_11 ((uint32_t)0xFF000000) /*!< Priority of interrupt 11 */
+
+/****************** Bit definition for NVIC_PRI3 register *******************/
+#define NVIC_IPR3_PRI_12 ((uint32_t)0x000000FF) /*!< Priority of interrupt 12 */
+#define NVIC_IPR3_PRI_13 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 13 */
+#define NVIC_IPR3_PRI_14 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 14 */
+#define NVIC_IPR3_PRI_15 ((uint32_t)0xFF000000) /*!< Priority of interrupt 15 */
+
+/****************** Bit definition for NVIC_PRI4 register *******************/
+#define NVIC_IPR4_PRI_16 ((uint32_t)0x000000FF) /*!< Priority of interrupt 16 */
+#define NVIC_IPR4_PRI_17 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 17 */
+#define NVIC_IPR4_PRI_18 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 18 */
+#define NVIC_IPR4_PRI_19 ((uint32_t)0xFF000000) /*!< Priority of interrupt 19 */
+
+/****************** Bit definition for NVIC_PRI5 register *******************/
+#define NVIC_IPR5_PRI_20 ((uint32_t)0x000000FF) /*!< Priority of interrupt 20 */
+#define NVIC_IPR5_PRI_21 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 21 */
+#define NVIC_IPR5_PRI_22 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 22 */
+#define NVIC_IPR5_PRI_23 ((uint32_t)0xFF000000) /*!< Priority of interrupt 23 */
+
+/****************** Bit definition for NVIC_PRI6 register *******************/
+#define NVIC_IPR6_PRI_24 ((uint32_t)0x000000FF) /*!< Priority of interrupt 24 */
+#define NVIC_IPR6_PRI_25 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 25 */
+#define NVIC_IPR6_PRI_26 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 26 */
+#define NVIC_IPR6_PRI_27 ((uint32_t)0xFF000000) /*!< Priority of interrupt 27 */
+
+/****************** Bit definition for NVIC_PRI7 register *******************/
+#define NVIC_IPR7_PRI_28 ((uint32_t)0x000000FF) /*!< Priority of interrupt 28 */
+#define NVIC_IPR7_PRI_29 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 29 */
+#define NVIC_IPR7_PRI_30 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 30 */
+#define NVIC_IPR7_PRI_31 ((uint32_t)0xFF000000) /*!< Priority of interrupt 31 */
+
+/****************** Bit definition for SCB_CPUID register *******************/
+#define SCB_CPUID_REVISION ((uint32_t)0x0000000F) /*!< Implementation defined revision number */
+#define SCB_CPUID_PARTNO ((uint32_t)0x0000FFF0) /*!< Number of processor within family */
+#define SCB_CPUID_Constant ((uint32_t)0x000F0000) /*!< Reads as 0x0F */
+#define SCB_CPUID_VARIANT ((uint32_t)0x00F00000) /*!< Implementation defined variant number */
+#define SCB_CPUID_IMPLEMENTER ((uint32_t)0xFF000000) /*!< Implementer code. ARM is 0x41 */
+
+/******************* Bit definition for SCB_ICSR register *******************/
+#define SCB_ICSR_VECTACTIVE ((uint32_t)0x000001FF) /*!< Active ISR number field */
+#define SCB_ICSR_RETTOBASE ((uint32_t)0x00000800) /*!< All active exceptions minus the IPSR_current_exception yields the empty set */
+#define SCB_ICSR_VECTPENDING ((uint32_t)0x003FF000) /*!< Pending ISR number field */
+#define SCB_ICSR_ISRPENDING ((uint32_t)0x00400000) /*!< Interrupt pending flag */
+#define SCB_ICSR_ISRPREEMPT ((uint32_t)0x00800000) /*!< It indicates that a pending interrupt becomes active in the next running cycle */
+#define SCB_ICSR_PENDSTCLR ((uint32_t)0x02000000) /*!< Clear pending SysTick bit */
+#define SCB_ICSR_PENDSTSET ((uint32_t)0x04000000) /*!< Set pending SysTick bit */
+#define SCB_ICSR_PENDSVCLR ((uint32_t)0x08000000) /*!< Clear pending pendSV bit */
+#define SCB_ICSR_PENDSVSET ((uint32_t)0x10000000) /*!< Set pending pendSV bit */
+#define SCB_ICSR_NMIPENDSET ((uint32_t)0x80000000) /*!< Set pending NMI bit */
+
+/******************* Bit definition for SCB_VTOR register *******************/
+#define SCB_VTOR_TBLOFF ((uint32_t)0x1FFFFF80) /*!< Vector table base offset field */
+#define SCB_VTOR_TBLBASE ((uint32_t)0x20000000) /*!< Table base in code(0) or RAM(1) */
+
+/*!<***************** Bit definition for SCB_AIRCR register *******************/
+#define SCB_AIRCR_VECTRESET ((uint32_t)0x00000001) /*!< System Reset bit */
+#define SCB_AIRCR_VECTCLRACTIVE ((uint32_t)0x00000002) /*!< Clear active vector bit */
+#define SCB_AIRCR_SYSRESETREQ ((uint32_t)0x00000004) /*!< Requests chip control logic to generate a reset */
+
+#define SCB_AIRCR_PRIGROUP ((uint32_t)0x00000700) /*!< PRIGROUP[2:0] bits (Priority group) */
+#define SCB_AIRCR_PRIGROUP_0 ((uint32_t)0x00000100) /*!< Bit 0 */
+#define SCB_AIRCR_PRIGROUP_1 ((uint32_t)0x00000200) /*!< Bit 1 */
+#define SCB_AIRCR_PRIGROUP_2 ((uint32_t)0x00000400) /*!< Bit 2 */
+
+/* prority group configuration */
+#define SCB_AIRCR_PRIGROUP0 ((uint32_t)0x00000000) /*!< Priority group=0 (7 bits of pre-emption priority, 1 bit of subpriority) */
+#define SCB_AIRCR_PRIGROUP1 ((uint32_t)0x00000100) /*!< Priority group=1 (6 bits of pre-emption priority, 2 bits of subpriority) */
+#define SCB_AIRCR_PRIGROUP2 ((uint32_t)0x00000200) /*!< Priority group=2 (5 bits of pre-emption priority, 3 bits of subpriority) */
+#define SCB_AIRCR_PRIGROUP3 ((uint32_t)0x00000300) /*!< Priority group=3 (4 bits of pre-emption priority, 4 bits of subpriority) */
+#define SCB_AIRCR_PRIGROUP4 ((uint32_t)0x00000400) /*!< Priority group=4 (3 bits of pre-emption priority, 5 bits of subpriority) */
+#define SCB_AIRCR_PRIGROUP5 ((uint32_t)0x00000500) /*!< Priority group=5 (2 bits of pre-emption priority, 6 bits of subpriority) */
+#define SCB_AIRCR_PRIGROUP6 ((uint32_t)0x00000600) /*!< Priority group=6 (1 bit of pre-emption priority, 7 bits of subpriority) */
+#define SCB_AIRCR_PRIGROUP7 ((uint32_t)0x00000700) /*!< Priority group=7 (no pre-emption priority, 8 bits of subpriority) */
+
+#define SCB_AIRCR_ENDIANESS ((uint32_t)0x00008000) /*!< Data endianness bit */
+#define SCB_AIRCR_VECTKEY ((uint32_t)0xFFFF0000) /*!< Register key (VECTKEY) - Reads as 0xFA05 (VECTKEYSTAT) */
+
+/******************* Bit definition for SCB_SCR register ********************/
+#define SCB_SCR_SLEEPONEXIT ((uint32_t)0x00000002) /*!< Sleep on exit bit */
+#define SCB_SCR_SLEEPDEEP ((uint32_t)0x00000004) /*!< Sleep deep bit */
+#define SCB_SCR_SEVONPEND ((uint32_t)0x00000010) /*!< Wake up from WFE */
+
+/******************** Bit definition for SCB_CCR register *******************/
+#define SCB_CCR_NONBASETHRDENA ((uint32_t)0x00000001) /*!< Thread mode can be entered from any level in Handler mode by controlled return value */
+#define SCB_CCR_USERSETMPEND ((uint32_t)0x00000002) /*!< Enables user code to write the Software Trigger Interrupt register to trigger (pend) a Main exception */
+#define SCB_CCR_UNALIGN_TRP ((uint32_t)0x00000008) /*!< Trap for unaligned access */
+#define SCB_CCR_DIV_0_TRP ((uint32_t)0x00000010) /*!< Trap on Divide by 0 */
+#define SCB_CCR_BFHFNMIGN ((uint32_t)0x00000100) /*!< Handlers running at priority -1 and -2 */
+#define SCB_CCR_STKALIGN ((uint32_t)0x00000200) /*!< On exception entry, the SP used prior to the exception is adjusted to be 8-byte aligned */
+
+/******************* Bit definition for SCB_SHPR register ********************/
+#define SCB_SHPR_PRI_N_Pos (0U)
+#define SCB_SHPR_PRI_N_Msk (0xFFU << SCB_SHPR_PRI_N_Pos) /*!< 0x000000FF */
+#define SCB_SHPR_PRI_N SCB_SHPR_PRI_N_Msk /*!< Priority of system handler 4,8, and 12. Mem Manage, reserved and Debug Monitor */
+#define SCB_SHPR_PRI_N1_Pos (8U)
+#define SCB_SHPR_PRI_N1_Msk (0xFFU << SCB_SHPR_PRI_N1_Pos) /*!< 0x0000FF00 */
+#define SCB_SHPR_PRI_N1 SCB_SHPR_PRI_N1_Msk /*!< Priority of system handler 5,9, and 13. Bus Fault, reserved and reserved */
+#define SCB_SHPR_PRI_N2_Pos (16U)
+#define SCB_SHPR_PRI_N2_Msk (0xFFU << SCB_SHPR_PRI_N2_Pos) /*!< 0x00FF0000 */
+#define SCB_SHPR_PRI_N2 SCB_SHPR_PRI_N2_Msk /*!< Priority of system handler 6,10, and 14. Usage Fault, reserved and PendSV */
+#define SCB_SHPR_PRI_N3_Pos (24U)
+#define SCB_SHPR_PRI_N3_Msk (0xFFU << SCB_SHPR_PRI_N3_Pos) /*!< 0xFF000000 */
+#define SCB_SHPR_PRI_N3 SCB_SHPR_PRI_N3_Msk /*!< Priority of system handler 7,11, and 15. Reserved, SVCall and SysTick */
+
+/****************** Bit definition for SCB_SHCSR register *******************/
+#define SCB_SHCSR_MEMFAULTACT ((uint32_t)0x00000001) /*!< MemManage is active */
+#define SCB_SHCSR_BUSFAULTACT ((uint32_t)0x00000002) /*!< BusFault is active */
+#define SCB_SHCSR_USGFAULTACT ((uint32_t)0x00000008) /*!< UsageFault is active */
+#define SCB_SHCSR_SVCALLACT ((uint32_t)0x00000080) /*!< SVCall is active */
+#define SCB_SHCSR_MONITORACT ((uint32_t)0x00000100) /*!< Monitor is active */
+#define SCB_SHCSR_PENDSVACT ((uint32_t)0x00000400) /*!< PendSV is active */
+#define SCB_SHCSR_SYSTICKACT ((uint32_t)0x00000800) /*!< SysTick is active */
+#define SCB_SHCSR_USGFAULTPENDED ((uint32_t)0x00001000) /*!< Usage Fault is pended */
+#define SCB_SHCSR_MEMFAULTPENDED ((uint32_t)0x00002000) /*!< MemManage is pended */
+#define SCB_SHCSR_BUSFAULTPENDED ((uint32_t)0x00004000) /*!< Bus Fault is pended */
+#define SCB_SHCSR_SVCALLPENDED ((uint32_t)0x00008000) /*!< SVCall is pended */
+#define SCB_SHCSR_MEMFAULTENA ((uint32_t)0x00010000) /*!< MemManage enable */
+#define SCB_SHCSR_BUSFAULTENA ((uint32_t)0x00020000) /*!< Bus Fault enable */
+#define SCB_SHCSR_USGFAULTENA ((uint32_t)0x00040000) /*!< UsageFault enable */
+
+/******************* Bit definition for SCB_CFSR register *******************/
+/*!< MFSR */
+#define SCB_CFSR_IACCVIOL_Pos (0U)
+#define SCB_CFSR_IACCVIOL_Msk (0x1U << SCB_CFSR_IACCVIOL_Pos) /*!< 0x00000001 */
+#define SCB_CFSR_IACCVIOL SCB_CFSR_IACCVIOL_Msk /*!< Instruction access violation */
+#define SCB_CFSR_DACCVIOL_Pos (1U)
+#define SCB_CFSR_DACCVIOL_Msk (0x1U << SCB_CFSR_DACCVIOL_Pos) /*!< 0x00000002 */
+#define SCB_CFSR_DACCVIOL SCB_CFSR_DACCVIOL_Msk /*!< Data access violation */
+#define SCB_CFSR_MUNSTKERR_Pos (3U)
+#define SCB_CFSR_MUNSTKERR_Msk (0x1U << SCB_CFSR_MUNSTKERR_Pos) /*!< 0x00000008 */
+#define SCB_CFSR_MUNSTKERR SCB_CFSR_MUNSTKERR_Msk /*!< Unstacking error */
+#define SCB_CFSR_MSTKERR_Pos (4U)
+#define SCB_CFSR_MSTKERR_Msk (0x1U << SCB_CFSR_MSTKERR_Pos) /*!< 0x00000010 */
+#define SCB_CFSR_MSTKERR SCB_CFSR_MSTKERR_Msk /*!< Stacking error */
+#define SCB_CFSR_MMARVALID_Pos (7U)
+#define SCB_CFSR_MMARVALID_Msk (0x1U << SCB_CFSR_MMARVALID_Pos) /*!< 0x00000080 */
+#define SCB_CFSR_MMARVALID SCB_CFSR_MMARVALID_Msk /*!< Memory Manage Address Register address valid flag */
+/*!< BFSR */
+#define SCB_CFSR_IBUSERR_Pos (8U)
+#define SCB_CFSR_IBUSERR_Msk (0x1U << SCB_CFSR_IBUSERR_Pos) /*!< 0x00000100 */
+#define SCB_CFSR_IBUSERR SCB_CFSR_IBUSERR_Msk /*!< Instruction bus error flag */
+#define SCB_CFSR_PRECISERR_Pos (9U)
+#define SCB_CFSR_PRECISERR_Msk (0x1U << SCB_CFSR_PRECISERR_Pos) /*!< 0x00000200 */
+#define SCB_CFSR_PRECISERR SCB_CFSR_PRECISERR_Msk /*!< Precise data bus error */
+#define SCB_CFSR_IMPRECISERR_Pos (10U)
+#define SCB_CFSR_IMPRECISERR_Msk (0x1U << SCB_CFSR_IMPRECISERR_Pos) /*!< 0x00000400 */
+#define SCB_CFSR_IMPRECISERR SCB_CFSR_IMPRECISERR_Msk /*!< Imprecise data bus error */
+#define SCB_CFSR_UNSTKERR_Pos (11U)
+#define SCB_CFSR_UNSTKERR_Msk (0x1U << SCB_CFSR_UNSTKERR_Pos) /*!< 0x00000800 */
+#define SCB_CFSR_UNSTKERR SCB_CFSR_UNSTKERR_Msk /*!< Unstacking error */
+#define SCB_CFSR_STKERR_Pos (12U)
+#define SCB_CFSR_STKERR_Msk (0x1U << SCB_CFSR_STKERR_Pos) /*!< 0x00001000 */
+#define SCB_CFSR_STKERR SCB_CFSR_STKERR_Msk /*!< Stacking error */
+#define SCB_CFSR_BFARVALID_Pos (15U)
+#define SCB_CFSR_BFARVALID_Msk (0x1U << SCB_CFSR_BFARVALID_Pos) /*!< 0x00008000 */
+#define SCB_CFSR_BFARVALID SCB_CFSR_BFARVALID_Msk /*!< Bus Fault Address Register address valid flag */
+/*!< UFSR */
+#define SCB_CFSR_UNDEFINSTR_Pos (16U)
+#define SCB_CFSR_UNDEFINSTR_Msk (0x1U << SCB_CFSR_UNDEFINSTR_Pos) /*!< 0x00010000 */
+#define SCB_CFSR_UNDEFINSTR SCB_CFSR_UNDEFINSTR_Msk /*!< The processor attempt to execute an undefined instruction */
+#define SCB_CFSR_INVSTATE_Pos (17U)
+#define SCB_CFSR_INVSTATE_Msk (0x1U << SCB_CFSR_INVSTATE_Pos) /*!< 0x00020000 */
+#define SCB_CFSR_INVSTATE SCB_CFSR_INVSTATE_Msk /*!< Invalid combination of EPSR and instruction */
+#define SCB_CFSR_INVPC_Pos (18U)
+#define SCB_CFSR_INVPC_Msk (0x1U << SCB_CFSR_INVPC_Pos) /*!< 0x00040000 */
+#define SCB_CFSR_INVPC SCB_CFSR_INVPC_Msk /*!< Attempt to load EXC_RETURN into pc illegally */
+#define SCB_CFSR_NOCP_Pos (19U)
+#define SCB_CFSR_NOCP_Msk (0x1U << SCB_CFSR_NOCP_Pos) /*!< 0x00080000 */
+#define SCB_CFSR_NOCP SCB_CFSR_NOCP_Msk /*!< Attempt to use a coprocessor instruction */
+#define SCB_CFSR_UNALIGNED_Pos (24U)
+#define SCB_CFSR_UNALIGNED_Msk (0x1U << SCB_CFSR_UNALIGNED_Pos) /*!< 0x01000000 */
+#define SCB_CFSR_UNALIGNED SCB_CFSR_UNALIGNED_Msk /*!< Fault occurs when there is an attempt to make an unaligned memory access */
+#define SCB_CFSR_DIVBYZERO_Pos (25U)
+#define SCB_CFSR_DIVBYZERO_Msk (0x1U << SCB_CFSR_DIVBYZERO_Pos) /*!< 0x02000000 */
+#define SCB_CFSR_DIVBYZERO SCB_CFSR_DIVBYZERO_Msk /*!< Fault occurs when SDIV or DIV instruction is used with a divisor of 0 */
+
+/******************* Bit definition for SCB_HFSR register *******************/
+#define SCB_HFSR_VECTTBL ((uint32_t)0x00000002) /*!< Fault occurs because of vector table read on exception processing */
+#define SCB_HFSR_FORCED ((uint32_t)0x40000000) /*!< Hard Fault activated when a configurable Fault was received and cannot activate */
+#define SCB_HFSR_DEBUGEVT ((uint32_t)0x80000000) /*!< Fault related to debug */
+
+/******************* Bit definition for SCB_DFSR register *******************/
+#define SCB_DFSR_HALTED ((uint32_t)0x00000001) /*!< Halt request flag */
+#define SCB_DFSR_BKPT ((uint32_t)0x00000002) /*!< BKPT flag */
+#define SCB_DFSR_DWTTRAP ((uint32_t)0x00000004) /*!< Data Watchpoint and Trace (DWT) flag */
+#define SCB_DFSR_VCATCH ((uint32_t)0x00000008) /*!< Vector catch flag */
+#define SCB_DFSR_EXTERNAL ((uint32_t)0x00000010) /*!< External debug request flag */
+
+/******************* Bit definition for SCB_MMFAR register ******************/
+#define SCB_MMFAR_ADDRESS_Pos (0U)
+#define SCB_MMFAR_ADDRESS_Msk (0xFFFFFFFFU << SCB_MMFAR_ADDRESS_Pos) /*!< 0xFFFFFFFF */
+#define SCB_MMFAR_ADDRESS SCB_MMFAR_ADDRESS_Msk /*!< Mem Manage fault address field */
+
+/******************* Bit definition for SCB_BFAR register *******************/
+#define SCB_BFAR_ADDRESS_Pos (0U)
+#define SCB_BFAR_ADDRESS_Msk (0xFFFFFFFFU << SCB_BFAR_ADDRESS_Pos) /*!< 0xFFFFFFFF */
+#define SCB_BFAR_ADDRESS SCB_BFAR_ADDRESS_Msk /*!< Bus fault address field */
+
+/******************* Bit definition for SCB_afsr register *******************/
+#define SCB_AFSR_IMPDEF_Pos (0U)
+#define SCB_AFSR_IMPDEF_Msk (0xFFFFFFFFU << SCB_AFSR_IMPDEF_Pos) /*!< 0xFFFFFFFF */
+#define SCB_AFSR_IMPDEF SCB_AFSR_IMPDEF_Msk /*!< Implementation defined */
+
+/******************************************************************************/
+/* */
+/* External Interrupt/Event Controller */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for EXTI_IMR register *******************/
+#define EXTI_IMR_MR0_Pos (0U)
+#define EXTI_IMR_MR0_Msk (0x1U << EXTI_IMR_MR0_Pos) /*!< 0x00000001 */
+#define EXTI_IMR_MR0 EXTI_IMR_MR0_Msk /*!< Interrupt Mask on line 0 */
+#define EXTI_IMR_MR1_Pos (1U)
+#define EXTI_IMR_MR1_Msk (0x1U << EXTI_IMR_MR1_Pos) /*!< 0x00000002 */
+#define EXTI_IMR_MR1 EXTI_IMR_MR1_Msk /*!< Interrupt Mask on line 1 */
+#define EXTI_IMR_MR2_Pos (2U)
+#define EXTI_IMR_MR2_Msk (0x1U << EXTI_IMR_MR2_Pos) /*!< 0x00000004 */
+#define EXTI_IMR_MR2 EXTI_IMR_MR2_Msk /*!< Interrupt Mask on line 2 */
+#define EXTI_IMR_MR3_Pos (3U)
+#define EXTI_IMR_MR3_Msk (0x1U << EXTI_IMR_MR3_Pos) /*!< 0x00000008 */
+#define EXTI_IMR_MR3 EXTI_IMR_MR3_Msk /*!< Interrupt Mask on line 3 */
+#define EXTI_IMR_MR4_Pos (4U)
+#define EXTI_IMR_MR4_Msk (0x1U << EXTI_IMR_MR4_Pos) /*!< 0x00000010 */
+#define EXTI_IMR_MR4 EXTI_IMR_MR4_Msk /*!< Interrupt Mask on line 4 */
+#define EXTI_IMR_MR5_Pos (5U)
+#define EXTI_IMR_MR5_Msk (0x1U << EXTI_IMR_MR5_Pos) /*!< 0x00000020 */
+#define EXTI_IMR_MR5 EXTI_IMR_MR5_Msk /*!< Interrupt Mask on line 5 */
+#define EXTI_IMR_MR6_Pos (6U)
+#define EXTI_IMR_MR6_Msk (0x1U << EXTI_IMR_MR6_Pos) /*!< 0x00000040 */
+#define EXTI_IMR_MR6 EXTI_IMR_MR6_Msk /*!< Interrupt Mask on line 6 */
+#define EXTI_IMR_MR7_Pos (7U)
+#define EXTI_IMR_MR7_Msk (0x1U << EXTI_IMR_MR7_Pos) /*!< 0x00000080 */
+#define EXTI_IMR_MR7 EXTI_IMR_MR7_Msk /*!< Interrupt Mask on line 7 */
+#define EXTI_IMR_MR8_Pos (8U)
+#define EXTI_IMR_MR8_Msk (0x1U << EXTI_IMR_MR8_Pos) /*!< 0x00000100 */
+#define EXTI_IMR_MR8 EXTI_IMR_MR8_Msk /*!< Interrupt Mask on line 8 */
+#define EXTI_IMR_MR9_Pos (9U)
+#define EXTI_IMR_MR9_Msk (0x1U << EXTI_IMR_MR9_Pos) /*!< 0x00000200 */
+#define EXTI_IMR_MR9 EXTI_IMR_MR9_Msk /*!< Interrupt Mask on line 9 */
+#define EXTI_IMR_MR10_Pos (10U)
+#define EXTI_IMR_MR10_Msk (0x1U << EXTI_IMR_MR10_Pos) /*!< 0x00000400 */
+#define EXTI_IMR_MR10 EXTI_IMR_MR10_Msk /*!< Interrupt Mask on line 10 */
+#define EXTI_IMR_MR11_Pos (11U)
+#define EXTI_IMR_MR11_Msk (0x1U << EXTI_IMR_MR11_Pos) /*!< 0x00000800 */
+#define EXTI_IMR_MR11 EXTI_IMR_MR11_Msk /*!< Interrupt Mask on line 11 */
+#define EXTI_IMR_MR12_Pos (12U)
+#define EXTI_IMR_MR12_Msk (0x1U << EXTI_IMR_MR12_Pos) /*!< 0x00001000 */
+#define EXTI_IMR_MR12 EXTI_IMR_MR12_Msk /*!< Interrupt Mask on line 12 */
+#define EXTI_IMR_MR13_Pos (13U)
+#define EXTI_IMR_MR13_Msk (0x1U << EXTI_IMR_MR13_Pos) /*!< 0x00002000 */
+#define EXTI_IMR_MR13 EXTI_IMR_MR13_Msk /*!< Interrupt Mask on line 13 */
+#define EXTI_IMR_MR14_Pos (14U)
+#define EXTI_IMR_MR14_Msk (0x1U << EXTI_IMR_MR14_Pos) /*!< 0x00004000 */
+#define EXTI_IMR_MR14 EXTI_IMR_MR14_Msk /*!< Interrupt Mask on line 14 */
+#define EXTI_IMR_MR15_Pos (15U)
+#define EXTI_IMR_MR15_Msk (0x1U << EXTI_IMR_MR15_Pos) /*!< 0x00008000 */
+#define EXTI_IMR_MR15 EXTI_IMR_MR15_Msk /*!< Interrupt Mask on line 15 */
+#define EXTI_IMR_MR16_Pos (16U)
+#define EXTI_IMR_MR16_Msk (0x1U << EXTI_IMR_MR16_Pos) /*!< 0x00010000 */
+#define EXTI_IMR_MR16 EXTI_IMR_MR16_Msk /*!< Interrupt Mask on line 16 */
+#define EXTI_IMR_MR17_Pos (17U)
+#define EXTI_IMR_MR17_Msk (0x1U << EXTI_IMR_MR17_Pos) /*!< 0x00020000 */
+#define EXTI_IMR_MR17 EXTI_IMR_MR17_Msk /*!< Interrupt Mask on line 17 */
+#define EXTI_IMR_MR18_Pos (18U)
+#define EXTI_IMR_MR18_Msk (0x1U << EXTI_IMR_MR18_Pos) /*!< 0x00040000 */
+#define EXTI_IMR_MR18 EXTI_IMR_MR18_Msk /*!< Interrupt Mask on line 18 */
+#define EXTI_IMR_MR19_Pos (19U)
+#define EXTI_IMR_MR19_Msk (0x1U << EXTI_IMR_MR19_Pos) /*!< 0x00080000 */
+#define EXTI_IMR_MR19 EXTI_IMR_MR19_Msk /*!< Interrupt Mask on line 19 */
+
+/* References Defines */
+#define EXTI_IMR_IM0 EXTI_IMR_MR0
+#define EXTI_IMR_IM1 EXTI_IMR_MR1
+#define EXTI_IMR_IM2 EXTI_IMR_MR2
+#define EXTI_IMR_IM3 EXTI_IMR_MR3
+#define EXTI_IMR_IM4 EXTI_IMR_MR4
+#define EXTI_IMR_IM5 EXTI_IMR_MR5
+#define EXTI_IMR_IM6 EXTI_IMR_MR6
+#define EXTI_IMR_IM7 EXTI_IMR_MR7
+#define EXTI_IMR_IM8 EXTI_IMR_MR8
+#define EXTI_IMR_IM9 EXTI_IMR_MR9
+#define EXTI_IMR_IM10 EXTI_IMR_MR10
+#define EXTI_IMR_IM11 EXTI_IMR_MR11
+#define EXTI_IMR_IM12 EXTI_IMR_MR12
+#define EXTI_IMR_IM13 EXTI_IMR_MR13
+#define EXTI_IMR_IM14 EXTI_IMR_MR14
+#define EXTI_IMR_IM15 EXTI_IMR_MR15
+#define EXTI_IMR_IM16 EXTI_IMR_MR16
+#define EXTI_IMR_IM17 EXTI_IMR_MR17
+#define EXTI_IMR_IM18 EXTI_IMR_MR18
+#define EXTI_IMR_IM19 EXTI_IMR_MR19
+
+/******************* Bit definition for EXTI_EMR register *******************/
+#define EXTI_EMR_MR0_Pos (0U)
+#define EXTI_EMR_MR0_Msk (0x1U << EXTI_EMR_MR0_Pos) /*!< 0x00000001 */
+#define EXTI_EMR_MR0 EXTI_EMR_MR0_Msk /*!< Event Mask on line 0 */
+#define EXTI_EMR_MR1_Pos (1U)
+#define EXTI_EMR_MR1_Msk (0x1U << EXTI_EMR_MR1_Pos) /*!< 0x00000002 */
+#define EXTI_EMR_MR1 EXTI_EMR_MR1_Msk /*!< Event Mask on line 1 */
+#define EXTI_EMR_MR2_Pos (2U)
+#define EXTI_EMR_MR2_Msk (0x1U << EXTI_EMR_MR2_Pos) /*!< 0x00000004 */
+#define EXTI_EMR_MR2 EXTI_EMR_MR2_Msk /*!< Event Mask on line 2 */
+#define EXTI_EMR_MR3_Pos (3U)
+#define EXTI_EMR_MR3_Msk (0x1U << EXTI_EMR_MR3_Pos) /*!< 0x00000008 */
+#define EXTI_EMR_MR3 EXTI_EMR_MR3_Msk /*!< Event Mask on line 3 */
+#define EXTI_EMR_MR4_Pos (4U)
+#define EXTI_EMR_MR4_Msk (0x1U << EXTI_EMR_MR4_Pos) /*!< 0x00000010 */
+#define EXTI_EMR_MR4 EXTI_EMR_MR4_Msk /*!< Event Mask on line 4 */
+#define EXTI_EMR_MR5_Pos (5U)
+#define EXTI_EMR_MR5_Msk (0x1U << EXTI_EMR_MR5_Pos) /*!< 0x00000020 */
+#define EXTI_EMR_MR5 EXTI_EMR_MR5_Msk /*!< Event Mask on line 5 */
+#define EXTI_EMR_MR6_Pos (6U)
+#define EXTI_EMR_MR6_Msk (0x1U << EXTI_EMR_MR6_Pos) /*!< 0x00000040 */
+#define EXTI_EMR_MR6 EXTI_EMR_MR6_Msk /*!< Event Mask on line 6 */
+#define EXTI_EMR_MR7_Pos (7U)
+#define EXTI_EMR_MR7_Msk (0x1U << EXTI_EMR_MR7_Pos) /*!< 0x00000080 */
+#define EXTI_EMR_MR7 EXTI_EMR_MR7_Msk /*!< Event Mask on line 7 */
+#define EXTI_EMR_MR8_Pos (8U)
+#define EXTI_EMR_MR8_Msk (0x1U << EXTI_EMR_MR8_Pos) /*!< 0x00000100 */
+#define EXTI_EMR_MR8 EXTI_EMR_MR8_Msk /*!< Event Mask on line 8 */
+#define EXTI_EMR_MR9_Pos (9U)
+#define EXTI_EMR_MR9_Msk (0x1U << EXTI_EMR_MR9_Pos) /*!< 0x00000200 */
+#define EXTI_EMR_MR9 EXTI_EMR_MR9_Msk /*!< Event Mask on line 9 */
+#define EXTI_EMR_MR10_Pos (10U)
+#define EXTI_EMR_MR10_Msk (0x1U << EXTI_EMR_MR10_Pos) /*!< 0x00000400 */
+#define EXTI_EMR_MR10 EXTI_EMR_MR10_Msk /*!< Event Mask on line 10 */
+#define EXTI_EMR_MR11_Pos (11U)
+#define EXTI_EMR_MR11_Msk (0x1U << EXTI_EMR_MR11_Pos) /*!< 0x00000800 */
+#define EXTI_EMR_MR11 EXTI_EMR_MR11_Msk /*!< Event Mask on line 11 */
+#define EXTI_EMR_MR12_Pos (12U)
+#define EXTI_EMR_MR12_Msk (0x1U << EXTI_EMR_MR12_Pos) /*!< 0x00001000 */
+#define EXTI_EMR_MR12 EXTI_EMR_MR12_Msk /*!< Event Mask on line 12 */
+#define EXTI_EMR_MR13_Pos (13U)
+#define EXTI_EMR_MR13_Msk (0x1U << EXTI_EMR_MR13_Pos) /*!< 0x00002000 */
+#define EXTI_EMR_MR13 EXTI_EMR_MR13_Msk /*!< Event Mask on line 13 */
+#define EXTI_EMR_MR14_Pos (14U)
+#define EXTI_EMR_MR14_Msk (0x1U << EXTI_EMR_MR14_Pos) /*!< 0x00004000 */
+#define EXTI_EMR_MR14 EXTI_EMR_MR14_Msk /*!< Event Mask on line 14 */
+#define EXTI_EMR_MR15_Pos (15U)
+#define EXTI_EMR_MR15_Msk (0x1U << EXTI_EMR_MR15_Pos) /*!< 0x00008000 */
+#define EXTI_EMR_MR15 EXTI_EMR_MR15_Msk /*!< Event Mask on line 15 */
+#define EXTI_EMR_MR16_Pos (16U)
+#define EXTI_EMR_MR16_Msk (0x1U << EXTI_EMR_MR16_Pos) /*!< 0x00010000 */
+#define EXTI_EMR_MR16 EXTI_EMR_MR16_Msk /*!< Event Mask on line 16 */
+#define EXTI_EMR_MR17_Pos (17U)
+#define EXTI_EMR_MR17_Msk (0x1U << EXTI_EMR_MR17_Pos) /*!< 0x00020000 */
+#define EXTI_EMR_MR17 EXTI_EMR_MR17_Msk /*!< Event Mask on line 17 */
+#define EXTI_EMR_MR18_Pos (18U)
+#define EXTI_EMR_MR18_Msk (0x1U << EXTI_EMR_MR18_Pos) /*!< 0x00040000 */
+#define EXTI_EMR_MR18 EXTI_EMR_MR18_Msk /*!< Event Mask on line 18 */
+#define EXTI_EMR_MR19_Pos (19U)
+#define EXTI_EMR_MR19_Msk (0x1U << EXTI_EMR_MR19_Pos) /*!< 0x00080000 */
+#define EXTI_EMR_MR19 EXTI_EMR_MR19_Msk /*!< Event Mask on line 19 */
+
+/* References Defines */
+#define EXTI_EMR_EM0 EXTI_EMR_MR0
+#define EXTI_EMR_EM1 EXTI_EMR_MR1
+#define EXTI_EMR_EM2 EXTI_EMR_MR2
+#define EXTI_EMR_EM3 EXTI_EMR_MR3
+#define EXTI_EMR_EM4 EXTI_EMR_MR4
+#define EXTI_EMR_EM5 EXTI_EMR_MR5
+#define EXTI_EMR_EM6 EXTI_EMR_MR6
+#define EXTI_EMR_EM7 EXTI_EMR_MR7
+#define EXTI_EMR_EM8 EXTI_EMR_MR8
+#define EXTI_EMR_EM9 EXTI_EMR_MR9
+#define EXTI_EMR_EM10 EXTI_EMR_MR10
+#define EXTI_EMR_EM11 EXTI_EMR_MR11
+#define EXTI_EMR_EM12 EXTI_EMR_MR12
+#define EXTI_EMR_EM13 EXTI_EMR_MR13
+#define EXTI_EMR_EM14 EXTI_EMR_MR14
+#define EXTI_EMR_EM15 EXTI_EMR_MR15
+#define EXTI_EMR_EM16 EXTI_EMR_MR16
+#define EXTI_EMR_EM17 EXTI_EMR_MR17
+#define EXTI_EMR_EM18 EXTI_EMR_MR18
+#define EXTI_EMR_EM19 EXTI_EMR_MR19
+
+/****************** Bit definition for EXTI_RTSR register *******************/
+#define EXTI_RTSR_TR0_Pos (0U)
+#define EXTI_RTSR_TR0_Msk (0x1U << EXTI_RTSR_TR0_Pos) /*!< 0x00000001 */
+#define EXTI_RTSR_TR0 EXTI_RTSR_TR0_Msk /*!< Rising trigger event configuration bit of line 0 */
+#define EXTI_RTSR_TR1_Pos (1U)
+#define EXTI_RTSR_TR1_Msk (0x1U << EXTI_RTSR_TR1_Pos) /*!< 0x00000002 */
+#define EXTI_RTSR_TR1 EXTI_RTSR_TR1_Msk /*!< Rising trigger event configuration bit of line 1 */
+#define EXTI_RTSR_TR2_Pos (2U)
+#define EXTI_RTSR_TR2_Msk (0x1U << EXTI_RTSR_TR2_Pos) /*!< 0x00000004 */
+#define EXTI_RTSR_TR2 EXTI_RTSR_TR2_Msk /*!< Rising trigger event configuration bit of line 2 */
+#define EXTI_RTSR_TR3_Pos (3U)
+#define EXTI_RTSR_TR3_Msk (0x1U << EXTI_RTSR_TR3_Pos) /*!< 0x00000008 */
+#define EXTI_RTSR_TR3 EXTI_RTSR_TR3_Msk /*!< Rising trigger event configuration bit of line 3 */
+#define EXTI_RTSR_TR4_Pos (4U)
+#define EXTI_RTSR_TR4_Msk (0x1U << EXTI_RTSR_TR4_Pos) /*!< 0x00000010 */
+#define EXTI_RTSR_TR4 EXTI_RTSR_TR4_Msk /*!< Rising trigger event configuration bit of line 4 */
+#define EXTI_RTSR_TR5_Pos (5U)
+#define EXTI_RTSR_TR5_Msk (0x1U << EXTI_RTSR_TR5_Pos) /*!< 0x00000020 */
+#define EXTI_RTSR_TR5 EXTI_RTSR_TR5_Msk /*!< Rising trigger event configuration bit of line 5 */
+#define EXTI_RTSR_TR6_Pos (6U)
+#define EXTI_RTSR_TR6_Msk (0x1U << EXTI_RTSR_TR6_Pos) /*!< 0x00000040 */
+#define EXTI_RTSR_TR6 EXTI_RTSR_TR6_Msk /*!< Rising trigger event configuration bit of line 6 */
+#define EXTI_RTSR_TR7_Pos (7U)
+#define EXTI_RTSR_TR7_Msk (0x1U << EXTI_RTSR_TR7_Pos) /*!< 0x00000080 */
+#define EXTI_RTSR_TR7 EXTI_RTSR_TR7_Msk /*!< Rising trigger event configuration bit of line 7 */
+#define EXTI_RTSR_TR8_Pos (8U)
+#define EXTI_RTSR_TR8_Msk (0x1U << EXTI_RTSR_TR8_Pos) /*!< 0x00000100 */
+#define EXTI_RTSR_TR8 EXTI_RTSR_TR8_Msk /*!< Rising trigger event configuration bit of line 8 */
+#define EXTI_RTSR_TR9_Pos (9U)
+#define EXTI_RTSR_TR9_Msk (0x1U << EXTI_RTSR_TR9_Pos) /*!< 0x00000200 */
+#define EXTI_RTSR_TR9 EXTI_RTSR_TR9_Msk /*!< Rising trigger event configuration bit of line 9 */
+#define EXTI_RTSR_TR10_Pos (10U)
+#define EXTI_RTSR_TR10_Msk (0x1U << EXTI_RTSR_TR10_Pos) /*!< 0x00000400 */
+#define EXTI_RTSR_TR10 EXTI_RTSR_TR10_Msk /*!< Rising trigger event configuration bit of line 10 */
+#define EXTI_RTSR_TR11_Pos (11U)
+#define EXTI_RTSR_TR11_Msk (0x1U << EXTI_RTSR_TR11_Pos) /*!< 0x00000800 */
+#define EXTI_RTSR_TR11 EXTI_RTSR_TR11_Msk /*!< Rising trigger event configuration bit of line 11 */
+#define EXTI_RTSR_TR12_Pos (12U)
+#define EXTI_RTSR_TR12_Msk (0x1U << EXTI_RTSR_TR12_Pos) /*!< 0x00001000 */
+#define EXTI_RTSR_TR12 EXTI_RTSR_TR12_Msk /*!< Rising trigger event configuration bit of line 12 */
+#define EXTI_RTSR_TR13_Pos (13U)
+#define EXTI_RTSR_TR13_Msk (0x1U << EXTI_RTSR_TR13_Pos) /*!< 0x00002000 */
+#define EXTI_RTSR_TR13 EXTI_RTSR_TR13_Msk /*!< Rising trigger event configuration bit of line 13 */
+#define EXTI_RTSR_TR14_Pos (14U)
+#define EXTI_RTSR_TR14_Msk (0x1U << EXTI_RTSR_TR14_Pos) /*!< 0x00004000 */
+#define EXTI_RTSR_TR14 EXTI_RTSR_TR14_Msk /*!< Rising trigger event configuration bit of line 14 */
+#define EXTI_RTSR_TR15_Pos (15U)
+#define EXTI_RTSR_TR15_Msk (0x1U << EXTI_RTSR_TR15_Pos) /*!< 0x00008000 */
+#define EXTI_RTSR_TR15 EXTI_RTSR_TR15_Msk /*!< Rising trigger event configuration bit of line 15 */
+#define EXTI_RTSR_TR16_Pos (16U)
+#define EXTI_RTSR_TR16_Msk (0x1U << EXTI_RTSR_TR16_Pos) /*!< 0x00010000 */
+#define EXTI_RTSR_TR16 EXTI_RTSR_TR16_Msk /*!< Rising trigger event configuration bit of line 16 */
+#define EXTI_RTSR_TR17_Pos (17U)
+#define EXTI_RTSR_TR17_Msk (0x1U << EXTI_RTSR_TR17_Pos) /*!< 0x00020000 */
+#define EXTI_RTSR_TR17 EXTI_RTSR_TR17_Msk /*!< Rising trigger event configuration bit of line 17 */
+#define EXTI_RTSR_TR18_Pos (18U)
+#define EXTI_RTSR_TR18_Msk (0x1U << EXTI_RTSR_TR18_Pos) /*!< 0x00040000 */
+#define EXTI_RTSR_TR18 EXTI_RTSR_TR18_Msk /*!< Rising trigger event configuration bit of line 18 */
+#define EXTI_RTSR_TR19_Pos (19U)
+#define EXTI_RTSR_TR19_Msk (0x1U << EXTI_RTSR_TR19_Pos) /*!< 0x00080000 */
+#define EXTI_RTSR_TR19 EXTI_RTSR_TR19_Msk /*!< Rising trigger event configuration bit of line 19 */
+
+/* References Defines */
+#define EXTI_RTSR_RT0 EXTI_RTSR_TR0
+#define EXTI_RTSR_RT1 EXTI_RTSR_TR1
+#define EXTI_RTSR_RT2 EXTI_RTSR_TR2
+#define EXTI_RTSR_RT3 EXTI_RTSR_TR3
+#define EXTI_RTSR_RT4 EXTI_RTSR_TR4
+#define EXTI_RTSR_RT5 EXTI_RTSR_TR5
+#define EXTI_RTSR_RT6 EXTI_RTSR_TR6
+#define EXTI_RTSR_RT7 EXTI_RTSR_TR7
+#define EXTI_RTSR_RT8 EXTI_RTSR_TR8
+#define EXTI_RTSR_RT9 EXTI_RTSR_TR9
+#define EXTI_RTSR_RT10 EXTI_RTSR_TR10
+#define EXTI_RTSR_RT11 EXTI_RTSR_TR11
+#define EXTI_RTSR_RT12 EXTI_RTSR_TR12
+#define EXTI_RTSR_RT13 EXTI_RTSR_TR13
+#define EXTI_RTSR_RT14 EXTI_RTSR_TR14
+#define EXTI_RTSR_RT15 EXTI_RTSR_TR15
+#define EXTI_RTSR_RT16 EXTI_RTSR_TR16
+#define EXTI_RTSR_RT17 EXTI_RTSR_TR17
+#define EXTI_RTSR_RT18 EXTI_RTSR_TR18
+#define EXTI_RTSR_RT19 EXTI_RTSR_TR19
+
+/****************** Bit definition for EXTI_FTSR register *******************/
+#define EXTI_FTSR_TR0_Pos (0U)
+#define EXTI_FTSR_TR0_Msk (0x1U << EXTI_FTSR_TR0_Pos) /*!< 0x00000001 */
+#define EXTI_FTSR_TR0 EXTI_FTSR_TR0_Msk /*!< Falling trigger event configuration bit of line 0 */
+#define EXTI_FTSR_TR1_Pos (1U)
+#define EXTI_FTSR_TR1_Msk (0x1U << EXTI_FTSR_TR1_Pos) /*!< 0x00000002 */
+#define EXTI_FTSR_TR1 EXTI_FTSR_TR1_Msk /*!< Falling trigger event configuration bit of line 1 */
+#define EXTI_FTSR_TR2_Pos (2U)
+#define EXTI_FTSR_TR2_Msk (0x1U << EXTI_FTSR_TR2_Pos) /*!< 0x00000004 */
+#define EXTI_FTSR_TR2 EXTI_FTSR_TR2_Msk /*!< Falling trigger event configuration bit of line 2 */
+#define EXTI_FTSR_TR3_Pos (3U)
+#define EXTI_FTSR_TR3_Msk (0x1U << EXTI_FTSR_TR3_Pos) /*!< 0x00000008 */
+#define EXTI_FTSR_TR3 EXTI_FTSR_TR3_Msk /*!< Falling trigger event configuration bit of line 3 */
+#define EXTI_FTSR_TR4_Pos (4U)
+#define EXTI_FTSR_TR4_Msk (0x1U << EXTI_FTSR_TR4_Pos) /*!< 0x00000010 */
+#define EXTI_FTSR_TR4 EXTI_FTSR_TR4_Msk /*!< Falling trigger event configuration bit of line 4 */
+#define EXTI_FTSR_TR5_Pos (5U)
+#define EXTI_FTSR_TR5_Msk (0x1U << EXTI_FTSR_TR5_Pos) /*!< 0x00000020 */
+#define EXTI_FTSR_TR5 EXTI_FTSR_TR5_Msk /*!< Falling trigger event configuration bit of line 5 */
+#define EXTI_FTSR_TR6_Pos (6U)
+#define EXTI_FTSR_TR6_Msk (0x1U << EXTI_FTSR_TR6_Pos) /*!< 0x00000040 */
+#define EXTI_FTSR_TR6 EXTI_FTSR_TR6_Msk /*!< Falling trigger event configuration bit of line 6 */
+#define EXTI_FTSR_TR7_Pos (7U)
+#define EXTI_FTSR_TR7_Msk (0x1U << EXTI_FTSR_TR7_Pos) /*!< 0x00000080 */
+#define EXTI_FTSR_TR7 EXTI_FTSR_TR7_Msk /*!< Falling trigger event configuration bit of line 7 */
+#define EXTI_FTSR_TR8_Pos (8U)
+#define EXTI_FTSR_TR8_Msk (0x1U << EXTI_FTSR_TR8_Pos) /*!< 0x00000100 */
+#define EXTI_FTSR_TR8 EXTI_FTSR_TR8_Msk /*!< Falling trigger event configuration bit of line 8 */
+#define EXTI_FTSR_TR9_Pos (9U)
+#define EXTI_FTSR_TR9_Msk (0x1U << EXTI_FTSR_TR9_Pos) /*!< 0x00000200 */
+#define EXTI_FTSR_TR9 EXTI_FTSR_TR9_Msk /*!< Falling trigger event configuration bit of line 9 */
+#define EXTI_FTSR_TR10_Pos (10U)
+#define EXTI_FTSR_TR10_Msk (0x1U << EXTI_FTSR_TR10_Pos) /*!< 0x00000400 */
+#define EXTI_FTSR_TR10 EXTI_FTSR_TR10_Msk /*!< Falling trigger event configuration bit of line 10 */
+#define EXTI_FTSR_TR11_Pos (11U)
+#define EXTI_FTSR_TR11_Msk (0x1U << EXTI_FTSR_TR11_Pos) /*!< 0x00000800 */
+#define EXTI_FTSR_TR11 EXTI_FTSR_TR11_Msk /*!< Falling trigger event configuration bit of line 11 */
+#define EXTI_FTSR_TR12_Pos (12U)
+#define EXTI_FTSR_TR12_Msk (0x1U << EXTI_FTSR_TR12_Pos) /*!< 0x00001000 */
+#define EXTI_FTSR_TR12 EXTI_FTSR_TR12_Msk /*!< Falling trigger event configuration bit of line 12 */
+#define EXTI_FTSR_TR13_Pos (13U)
+#define EXTI_FTSR_TR13_Msk (0x1U << EXTI_FTSR_TR13_Pos) /*!< 0x00002000 */
+#define EXTI_FTSR_TR13 EXTI_FTSR_TR13_Msk /*!< Falling trigger event configuration bit of line 13 */
+#define EXTI_FTSR_TR14_Pos (14U)
+#define EXTI_FTSR_TR14_Msk (0x1U << EXTI_FTSR_TR14_Pos) /*!< 0x00004000 */
+#define EXTI_FTSR_TR14 EXTI_FTSR_TR14_Msk /*!< Falling trigger event configuration bit of line 14 */
+#define EXTI_FTSR_TR15_Pos (15U)
+#define EXTI_FTSR_TR15_Msk (0x1U << EXTI_FTSR_TR15_Pos) /*!< 0x00008000 */
+#define EXTI_FTSR_TR15 EXTI_FTSR_TR15_Msk /*!< Falling trigger event configuration bit of line 15 */
+#define EXTI_FTSR_TR16_Pos (16U)
+#define EXTI_FTSR_TR16_Msk (0x1U << EXTI_FTSR_TR16_Pos) /*!< 0x00010000 */
+#define EXTI_FTSR_TR16 EXTI_FTSR_TR16_Msk /*!< Falling trigger event configuration bit of line 16 */
+#define EXTI_FTSR_TR17_Pos (17U)
+#define EXTI_FTSR_TR17_Msk (0x1U << EXTI_FTSR_TR17_Pos) /*!< 0x00020000 */
+#define EXTI_FTSR_TR17 EXTI_FTSR_TR17_Msk /*!< Falling trigger event configuration bit of line 17 */
+#define EXTI_FTSR_TR18_Pos (18U)
+#define EXTI_FTSR_TR18_Msk (0x1U << EXTI_FTSR_TR18_Pos) /*!< 0x00040000 */
+#define EXTI_FTSR_TR18 EXTI_FTSR_TR18_Msk /*!< Falling trigger event configuration bit of line 18 */
+#define EXTI_FTSR_TR19_Pos (19U)
+#define EXTI_FTSR_TR19_Msk (0x1U << EXTI_FTSR_TR19_Pos) /*!< 0x00080000 */
+#define EXTI_FTSR_TR19 EXTI_FTSR_TR19_Msk /*!< Falling trigger event configuration bit of line 19 */
+
+/* References Defines */
+#define EXTI_FTSR_FT0 EXTI_FTSR_TR0
+#define EXTI_FTSR_FT1 EXTI_FTSR_TR1
+#define EXTI_FTSR_FT2 EXTI_FTSR_TR2
+#define EXTI_FTSR_FT3 EXTI_FTSR_TR3
+#define EXTI_FTSR_FT4 EXTI_FTSR_TR4
+#define EXTI_FTSR_FT5 EXTI_FTSR_TR5
+#define EXTI_FTSR_FT6 EXTI_FTSR_TR6
+#define EXTI_FTSR_FT7 EXTI_FTSR_TR7
+#define EXTI_FTSR_FT8 EXTI_FTSR_TR8
+#define EXTI_FTSR_FT9 EXTI_FTSR_TR9
+#define EXTI_FTSR_FT10 EXTI_FTSR_TR10
+#define EXTI_FTSR_FT11 EXTI_FTSR_TR11
+#define EXTI_FTSR_FT12 EXTI_FTSR_TR12
+#define EXTI_FTSR_FT13 EXTI_FTSR_TR13
+#define EXTI_FTSR_FT14 EXTI_FTSR_TR14
+#define EXTI_FTSR_FT15 EXTI_FTSR_TR15
+#define EXTI_FTSR_FT16 EXTI_FTSR_TR16
+#define EXTI_FTSR_FT17 EXTI_FTSR_TR17
+#define EXTI_FTSR_FT18 EXTI_FTSR_TR18
+#define EXTI_FTSR_FT19 EXTI_FTSR_TR19
+
+/****************** Bit definition for EXTI_SWIER register ******************/
+#define EXTI_SWIER_SWIER0_Pos (0U)
+#define EXTI_SWIER_SWIER0_Msk (0x1U << EXTI_SWIER_SWIER0_Pos) /*!< 0x00000001 */
+#define EXTI_SWIER_SWIER0 EXTI_SWIER_SWIER0_Msk /*!< Software Interrupt on line 0 */
+#define EXTI_SWIER_SWIER1_Pos (1U)
+#define EXTI_SWIER_SWIER1_Msk (0x1U << EXTI_SWIER_SWIER1_Pos) /*!< 0x00000002 */
+#define EXTI_SWIER_SWIER1 EXTI_SWIER_SWIER1_Msk /*!< Software Interrupt on line 1 */
+#define EXTI_SWIER_SWIER2_Pos (2U)
+#define EXTI_SWIER_SWIER2_Msk (0x1U << EXTI_SWIER_SWIER2_Pos) /*!< 0x00000004 */
+#define EXTI_SWIER_SWIER2 EXTI_SWIER_SWIER2_Msk /*!< Software Interrupt on line 2 */
+#define EXTI_SWIER_SWIER3_Pos (3U)
+#define EXTI_SWIER_SWIER3_Msk (0x1U << EXTI_SWIER_SWIER3_Pos) /*!< 0x00000008 */
+#define EXTI_SWIER_SWIER3 EXTI_SWIER_SWIER3_Msk /*!< Software Interrupt on line 3 */
+#define EXTI_SWIER_SWIER4_Pos (4U)
+#define EXTI_SWIER_SWIER4_Msk (0x1U << EXTI_SWIER_SWIER4_Pos) /*!< 0x00000010 */
+#define EXTI_SWIER_SWIER4 EXTI_SWIER_SWIER4_Msk /*!< Software Interrupt on line 4 */
+#define EXTI_SWIER_SWIER5_Pos (5U)
+#define EXTI_SWIER_SWIER5_Msk (0x1U << EXTI_SWIER_SWIER5_Pos) /*!< 0x00000020 */
+#define EXTI_SWIER_SWIER5 EXTI_SWIER_SWIER5_Msk /*!< Software Interrupt on line 5 */
+#define EXTI_SWIER_SWIER6_Pos (6U)
+#define EXTI_SWIER_SWIER6_Msk (0x1U << EXTI_SWIER_SWIER6_Pos) /*!< 0x00000040 */
+#define EXTI_SWIER_SWIER6 EXTI_SWIER_SWIER6_Msk /*!< Software Interrupt on line 6 */
+#define EXTI_SWIER_SWIER7_Pos (7U)
+#define EXTI_SWIER_SWIER7_Msk (0x1U << EXTI_SWIER_SWIER7_Pos) /*!< 0x00000080 */
+#define EXTI_SWIER_SWIER7 EXTI_SWIER_SWIER7_Msk /*!< Software Interrupt on line 7 */
+#define EXTI_SWIER_SWIER8_Pos (8U)
+#define EXTI_SWIER_SWIER8_Msk (0x1U << EXTI_SWIER_SWIER8_Pos) /*!< 0x00000100 */
+#define EXTI_SWIER_SWIER8 EXTI_SWIER_SWIER8_Msk /*!< Software Interrupt on line 8 */
+#define EXTI_SWIER_SWIER9_Pos (9U)
+#define EXTI_SWIER_SWIER9_Msk (0x1U << EXTI_SWIER_SWIER9_Pos) /*!< 0x00000200 */
+#define EXTI_SWIER_SWIER9 EXTI_SWIER_SWIER9_Msk /*!< Software Interrupt on line 9 */
+#define EXTI_SWIER_SWIER10_Pos (10U)
+#define EXTI_SWIER_SWIER10_Msk (0x1U << EXTI_SWIER_SWIER10_Pos) /*!< 0x00000400 */
+#define EXTI_SWIER_SWIER10 EXTI_SWIER_SWIER10_Msk /*!< Software Interrupt on line 10 */
+#define EXTI_SWIER_SWIER11_Pos (11U)
+#define EXTI_SWIER_SWIER11_Msk (0x1U << EXTI_SWIER_SWIER11_Pos) /*!< 0x00000800 */
+#define EXTI_SWIER_SWIER11 EXTI_SWIER_SWIER11_Msk /*!< Software Interrupt on line 11 */
+#define EXTI_SWIER_SWIER12_Pos (12U)
+#define EXTI_SWIER_SWIER12_Msk (0x1U << EXTI_SWIER_SWIER12_Pos) /*!< 0x00001000 */
+#define EXTI_SWIER_SWIER12 EXTI_SWIER_SWIER12_Msk /*!< Software Interrupt on line 12 */
+#define EXTI_SWIER_SWIER13_Pos (13U)
+#define EXTI_SWIER_SWIER13_Msk (0x1U << EXTI_SWIER_SWIER13_Pos) /*!< 0x00002000 */
+#define EXTI_SWIER_SWIER13 EXTI_SWIER_SWIER13_Msk /*!< Software Interrupt on line 13 */
+#define EXTI_SWIER_SWIER14_Pos (14U)
+#define EXTI_SWIER_SWIER14_Msk (0x1U << EXTI_SWIER_SWIER14_Pos) /*!< 0x00004000 */
+#define EXTI_SWIER_SWIER14 EXTI_SWIER_SWIER14_Msk /*!< Software Interrupt on line 14 */
+#define EXTI_SWIER_SWIER15_Pos (15U)
+#define EXTI_SWIER_SWIER15_Msk (0x1U << EXTI_SWIER_SWIER15_Pos) /*!< 0x00008000 */
+#define EXTI_SWIER_SWIER15 EXTI_SWIER_SWIER15_Msk /*!< Software Interrupt on line 15 */
+#define EXTI_SWIER_SWIER16_Pos (16U)
+#define EXTI_SWIER_SWIER16_Msk (0x1U << EXTI_SWIER_SWIER16_Pos) /*!< 0x00010000 */
+#define EXTI_SWIER_SWIER16 EXTI_SWIER_SWIER16_Msk /*!< Software Interrupt on line 16 */
+#define EXTI_SWIER_SWIER17_Pos (17U)
+#define EXTI_SWIER_SWIER17_Msk (0x1U << EXTI_SWIER_SWIER17_Pos) /*!< 0x00020000 */
+#define EXTI_SWIER_SWIER17 EXTI_SWIER_SWIER17_Msk /*!< Software Interrupt on line 17 */
+#define EXTI_SWIER_SWIER18_Pos (18U)
+#define EXTI_SWIER_SWIER18_Msk (0x1U << EXTI_SWIER_SWIER18_Pos) /*!< 0x00040000 */
+#define EXTI_SWIER_SWIER18 EXTI_SWIER_SWIER18_Msk /*!< Software Interrupt on line 18 */
+#define EXTI_SWIER_SWIER19_Pos (19U)
+#define EXTI_SWIER_SWIER19_Msk (0x1U << EXTI_SWIER_SWIER19_Pos) /*!< 0x00080000 */
+#define EXTI_SWIER_SWIER19 EXTI_SWIER_SWIER19_Msk /*!< Software Interrupt on line 19 */
+
+/* References Defines */
+#define EXTI_SWIER_SWI0 EXTI_SWIER_SWIER0
+#define EXTI_SWIER_SWI1 EXTI_SWIER_SWIER1
+#define EXTI_SWIER_SWI2 EXTI_SWIER_SWIER2
+#define EXTI_SWIER_SWI3 EXTI_SWIER_SWIER3
+#define EXTI_SWIER_SWI4 EXTI_SWIER_SWIER4
+#define EXTI_SWIER_SWI5 EXTI_SWIER_SWIER5
+#define EXTI_SWIER_SWI6 EXTI_SWIER_SWIER6
+#define EXTI_SWIER_SWI7 EXTI_SWIER_SWIER7
+#define EXTI_SWIER_SWI8 EXTI_SWIER_SWIER8
+#define EXTI_SWIER_SWI9 EXTI_SWIER_SWIER9
+#define EXTI_SWIER_SWI10 EXTI_SWIER_SWIER10
+#define EXTI_SWIER_SWI11 EXTI_SWIER_SWIER11
+#define EXTI_SWIER_SWI12 EXTI_SWIER_SWIER12
+#define EXTI_SWIER_SWI13 EXTI_SWIER_SWIER13
+#define EXTI_SWIER_SWI14 EXTI_SWIER_SWIER14
+#define EXTI_SWIER_SWI15 EXTI_SWIER_SWIER15
+#define EXTI_SWIER_SWI16 EXTI_SWIER_SWIER16
+#define EXTI_SWIER_SWI17 EXTI_SWIER_SWIER17
+#define EXTI_SWIER_SWI18 EXTI_SWIER_SWIER18
+#define EXTI_SWIER_SWI19 EXTI_SWIER_SWIER19
+
+/******************* Bit definition for EXTI_PR register ********************/
+#define EXTI_PR_PR0_Pos (0U)
+#define EXTI_PR_PR0_Msk (0x1U << EXTI_PR_PR0_Pos) /*!< 0x00000001 */
+#define EXTI_PR_PR0 EXTI_PR_PR0_Msk /*!< Pending bit for line 0 */
+#define EXTI_PR_PR1_Pos (1U)
+#define EXTI_PR_PR1_Msk (0x1U << EXTI_PR_PR1_Pos) /*!< 0x00000002 */
+#define EXTI_PR_PR1 EXTI_PR_PR1_Msk /*!< Pending bit for line 1 */
+#define EXTI_PR_PR2_Pos (2U)
+#define EXTI_PR_PR2_Msk (0x1U << EXTI_PR_PR2_Pos) /*!< 0x00000004 */
+#define EXTI_PR_PR2 EXTI_PR_PR2_Msk /*!< Pending bit for line 2 */
+#define EXTI_PR_PR3_Pos (3U)
+#define EXTI_PR_PR3_Msk (0x1U << EXTI_PR_PR3_Pos) /*!< 0x00000008 */
+#define EXTI_PR_PR3 EXTI_PR_PR3_Msk /*!< Pending bit for line 3 */
+#define EXTI_PR_PR4_Pos (4U)
+#define EXTI_PR_PR4_Msk (0x1U << EXTI_PR_PR4_Pos) /*!< 0x00000010 */
+#define EXTI_PR_PR4 EXTI_PR_PR4_Msk /*!< Pending bit for line 4 */
+#define EXTI_PR_PR5_Pos (5U)
+#define EXTI_PR_PR5_Msk (0x1U << EXTI_PR_PR5_Pos) /*!< 0x00000020 */
+#define EXTI_PR_PR5 EXTI_PR_PR5_Msk /*!< Pending bit for line 5 */
+#define EXTI_PR_PR6_Pos (6U)
+#define EXTI_PR_PR6_Msk (0x1U << EXTI_PR_PR6_Pos) /*!< 0x00000040 */
+#define EXTI_PR_PR6 EXTI_PR_PR6_Msk /*!< Pending bit for line 6 */
+#define EXTI_PR_PR7_Pos (7U)
+#define EXTI_PR_PR7_Msk (0x1U << EXTI_PR_PR7_Pos) /*!< 0x00000080 */
+#define EXTI_PR_PR7 EXTI_PR_PR7_Msk /*!< Pending bit for line 7 */
+#define EXTI_PR_PR8_Pos (8U)
+#define EXTI_PR_PR8_Msk (0x1U << EXTI_PR_PR8_Pos) /*!< 0x00000100 */
+#define EXTI_PR_PR8 EXTI_PR_PR8_Msk /*!< Pending bit for line 8 */
+#define EXTI_PR_PR9_Pos (9U)
+#define EXTI_PR_PR9_Msk (0x1U << EXTI_PR_PR9_Pos) /*!< 0x00000200 */
+#define EXTI_PR_PR9 EXTI_PR_PR9_Msk /*!< Pending bit for line 9 */
+#define EXTI_PR_PR10_Pos (10U)
+#define EXTI_PR_PR10_Msk (0x1U << EXTI_PR_PR10_Pos) /*!< 0x00000400 */
+#define EXTI_PR_PR10 EXTI_PR_PR10_Msk /*!< Pending bit for line 10 */
+#define EXTI_PR_PR11_Pos (11U)
+#define EXTI_PR_PR11_Msk (0x1U << EXTI_PR_PR11_Pos) /*!< 0x00000800 */
+#define EXTI_PR_PR11 EXTI_PR_PR11_Msk /*!< Pending bit for line 11 */
+#define EXTI_PR_PR12_Pos (12U)
+#define EXTI_PR_PR12_Msk (0x1U << EXTI_PR_PR12_Pos) /*!< 0x00001000 */
+#define EXTI_PR_PR12 EXTI_PR_PR12_Msk /*!< Pending bit for line 12 */
+#define EXTI_PR_PR13_Pos (13U)
+#define EXTI_PR_PR13_Msk (0x1U << EXTI_PR_PR13_Pos) /*!< 0x00002000 */
+#define EXTI_PR_PR13 EXTI_PR_PR13_Msk /*!< Pending bit for line 13 */
+#define EXTI_PR_PR14_Pos (14U)
+#define EXTI_PR_PR14_Msk (0x1U << EXTI_PR_PR14_Pos) /*!< 0x00004000 */
+#define EXTI_PR_PR14 EXTI_PR_PR14_Msk /*!< Pending bit for line 14 */
+#define EXTI_PR_PR15_Pos (15U)
+#define EXTI_PR_PR15_Msk (0x1U << EXTI_PR_PR15_Pos) /*!< 0x00008000 */
+#define EXTI_PR_PR15 EXTI_PR_PR15_Msk /*!< Pending bit for line 15 */
+#define EXTI_PR_PR16_Pos (16U)
+#define EXTI_PR_PR16_Msk (0x1U << EXTI_PR_PR16_Pos) /*!< 0x00010000 */
+#define EXTI_PR_PR16 EXTI_PR_PR16_Msk /*!< Pending bit for line 16 */
+#define EXTI_PR_PR17_Pos (17U)
+#define EXTI_PR_PR17_Msk (0x1U << EXTI_PR_PR17_Pos) /*!< 0x00020000 */
+#define EXTI_PR_PR17 EXTI_PR_PR17_Msk /*!< Pending bit for line 17 */
+#define EXTI_PR_PR18_Pos (18U)
+#define EXTI_PR_PR18_Msk (0x1U << EXTI_PR_PR18_Pos) /*!< 0x00040000 */
+#define EXTI_PR_PR18 EXTI_PR_PR18_Msk /*!< Pending bit for line 18 */
+#define EXTI_PR_PR19_Pos (19U)
+#define EXTI_PR_PR19_Msk (0x1U << EXTI_PR_PR19_Pos) /*!< 0x00080000 */
+#define EXTI_PR_PR19 EXTI_PR_PR19_Msk /*!< Pending bit for line 19 */
+
+/* References Defines */
+#define EXTI_PR_PIF0 EXTI_PR_PR0
+#define EXTI_PR_PIF1 EXTI_PR_PR1
+#define EXTI_PR_PIF2 EXTI_PR_PR2
+#define EXTI_PR_PIF3 EXTI_PR_PR3
+#define EXTI_PR_PIF4 EXTI_PR_PR4
+#define EXTI_PR_PIF5 EXTI_PR_PR5
+#define EXTI_PR_PIF6 EXTI_PR_PR6
+#define EXTI_PR_PIF7 EXTI_PR_PR7
+#define EXTI_PR_PIF8 EXTI_PR_PR8
+#define EXTI_PR_PIF9 EXTI_PR_PR9
+#define EXTI_PR_PIF10 EXTI_PR_PR10
+#define EXTI_PR_PIF11 EXTI_PR_PR11
+#define EXTI_PR_PIF12 EXTI_PR_PR12
+#define EXTI_PR_PIF13 EXTI_PR_PR13
+#define EXTI_PR_PIF14 EXTI_PR_PR14
+#define EXTI_PR_PIF15 EXTI_PR_PR15
+#define EXTI_PR_PIF16 EXTI_PR_PR16
+#define EXTI_PR_PIF17 EXTI_PR_PR17
+#define EXTI_PR_PIF18 EXTI_PR_PR18
+#define EXTI_PR_PIF19 EXTI_PR_PR19
+
+/******************************************************************************/
+/* */
+/* DMA Controller */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for DMA_ISR register ********************/
+#define DMA_ISR_GIF1_Pos (0U)
+#define DMA_ISR_GIF1_Msk (0x1U << DMA_ISR_GIF1_Pos) /*!< 0x00000001 */
+#define DMA_ISR_GIF1 DMA_ISR_GIF1_Msk /*!< Channel 1 Global interrupt flag */
+#define DMA_ISR_TCIF1_Pos (1U)
+#define DMA_ISR_TCIF1_Msk (0x1U << DMA_ISR_TCIF1_Pos) /*!< 0x00000002 */
+#define DMA_ISR_TCIF1 DMA_ISR_TCIF1_Msk /*!< Channel 1 Transfer Complete flag */
+#define DMA_ISR_HTIF1_Pos (2U)
+#define DMA_ISR_HTIF1_Msk (0x1U << DMA_ISR_HTIF1_Pos) /*!< 0x00000004 */
+#define DMA_ISR_HTIF1 DMA_ISR_HTIF1_Msk /*!< Channel 1 Half Transfer flag */
+#define DMA_ISR_TEIF1_Pos (3U)
+#define DMA_ISR_TEIF1_Msk (0x1U << DMA_ISR_TEIF1_Pos) /*!< 0x00000008 */
+#define DMA_ISR_TEIF1 DMA_ISR_TEIF1_Msk /*!< Channel 1 Transfer Error flag */
+#define DMA_ISR_GIF2_Pos (4U)
+#define DMA_ISR_GIF2_Msk (0x1U << DMA_ISR_GIF2_Pos) /*!< 0x00000010 */
+#define DMA_ISR_GIF2 DMA_ISR_GIF2_Msk /*!< Channel 2 Global interrupt flag */
+#define DMA_ISR_TCIF2_Pos (5U)
+#define DMA_ISR_TCIF2_Msk (0x1U << DMA_ISR_TCIF2_Pos) /*!< 0x00000020 */
+#define DMA_ISR_TCIF2 DMA_ISR_TCIF2_Msk /*!< Channel 2 Transfer Complete flag */
+#define DMA_ISR_HTIF2_Pos (6U)
+#define DMA_ISR_HTIF2_Msk (0x1U << DMA_ISR_HTIF2_Pos) /*!< 0x00000040 */
+#define DMA_ISR_HTIF2 DMA_ISR_HTIF2_Msk /*!< Channel 2 Half Transfer flag */
+#define DMA_ISR_TEIF2_Pos (7U)
+#define DMA_ISR_TEIF2_Msk (0x1U << DMA_ISR_TEIF2_Pos) /*!< 0x00000080 */
+#define DMA_ISR_TEIF2 DMA_ISR_TEIF2_Msk /*!< Channel 2 Transfer Error flag */
+#define DMA_ISR_GIF3_Pos (8U)
+#define DMA_ISR_GIF3_Msk (0x1U << DMA_ISR_GIF3_Pos) /*!< 0x00000100 */
+#define DMA_ISR_GIF3 DMA_ISR_GIF3_Msk /*!< Channel 3 Global interrupt flag */
+#define DMA_ISR_TCIF3_Pos (9U)
+#define DMA_ISR_TCIF3_Msk (0x1U << DMA_ISR_TCIF3_Pos) /*!< 0x00000200 */
+#define DMA_ISR_TCIF3 DMA_ISR_TCIF3_Msk /*!< Channel 3 Transfer Complete flag */
+#define DMA_ISR_HTIF3_Pos (10U)
+#define DMA_ISR_HTIF3_Msk (0x1U << DMA_ISR_HTIF3_Pos) /*!< 0x00000400 */
+#define DMA_ISR_HTIF3 DMA_ISR_HTIF3_Msk /*!< Channel 3 Half Transfer flag */
+#define DMA_ISR_TEIF3_Pos (11U)
+#define DMA_ISR_TEIF3_Msk (0x1U << DMA_ISR_TEIF3_Pos) /*!< 0x00000800 */
+#define DMA_ISR_TEIF3 DMA_ISR_TEIF3_Msk /*!< Channel 3 Transfer Error flag */
+#define DMA_ISR_GIF4_Pos (12U)
+#define DMA_ISR_GIF4_Msk (0x1U << DMA_ISR_GIF4_Pos) /*!< 0x00001000 */
+#define DMA_ISR_GIF4 DMA_ISR_GIF4_Msk /*!< Channel 4 Global interrupt flag */
+#define DMA_ISR_TCIF4_Pos (13U)
+#define DMA_ISR_TCIF4_Msk (0x1U << DMA_ISR_TCIF4_Pos) /*!< 0x00002000 */
+#define DMA_ISR_TCIF4 DMA_ISR_TCIF4_Msk /*!< Channel 4 Transfer Complete flag */
+#define DMA_ISR_HTIF4_Pos (14U)
+#define DMA_ISR_HTIF4_Msk (0x1U << DMA_ISR_HTIF4_Pos) /*!< 0x00004000 */
+#define DMA_ISR_HTIF4 DMA_ISR_HTIF4_Msk /*!< Channel 4 Half Transfer flag */
+#define DMA_ISR_TEIF4_Pos (15U)
+#define DMA_ISR_TEIF4_Msk (0x1U << DMA_ISR_TEIF4_Pos) /*!< 0x00008000 */
+#define DMA_ISR_TEIF4 DMA_ISR_TEIF4_Msk /*!< Channel 4 Transfer Error flag */
+#define DMA_ISR_GIF5_Pos (16U)
+#define DMA_ISR_GIF5_Msk (0x1U << DMA_ISR_GIF5_Pos) /*!< 0x00010000 */
+#define DMA_ISR_GIF5 DMA_ISR_GIF5_Msk /*!< Channel 5 Global interrupt flag */
+#define DMA_ISR_TCIF5_Pos (17U)
+#define DMA_ISR_TCIF5_Msk (0x1U << DMA_ISR_TCIF5_Pos) /*!< 0x00020000 */
+#define DMA_ISR_TCIF5 DMA_ISR_TCIF5_Msk /*!< Channel 5 Transfer Complete flag */
+#define DMA_ISR_HTIF5_Pos (18U)
+#define DMA_ISR_HTIF5_Msk (0x1U << DMA_ISR_HTIF5_Pos) /*!< 0x00040000 */
+#define DMA_ISR_HTIF5 DMA_ISR_HTIF5_Msk /*!< Channel 5 Half Transfer flag */
+#define DMA_ISR_TEIF5_Pos (19U)
+#define DMA_ISR_TEIF5_Msk (0x1U << DMA_ISR_TEIF5_Pos) /*!< 0x00080000 */
+#define DMA_ISR_TEIF5 DMA_ISR_TEIF5_Msk /*!< Channel 5 Transfer Error flag */
+#define DMA_ISR_GIF6_Pos (20U)
+#define DMA_ISR_GIF6_Msk (0x1U << DMA_ISR_GIF6_Pos) /*!< 0x00100000 */
+#define DMA_ISR_GIF6 DMA_ISR_GIF6_Msk /*!< Channel 6 Global interrupt flag */
+#define DMA_ISR_TCIF6_Pos (21U)
+#define DMA_ISR_TCIF6_Msk (0x1U << DMA_ISR_TCIF6_Pos) /*!< 0x00200000 */
+#define DMA_ISR_TCIF6 DMA_ISR_TCIF6_Msk /*!< Channel 6 Transfer Complete flag */
+#define DMA_ISR_HTIF6_Pos (22U)
+#define DMA_ISR_HTIF6_Msk (0x1U << DMA_ISR_HTIF6_Pos) /*!< 0x00400000 */
+#define DMA_ISR_HTIF6 DMA_ISR_HTIF6_Msk /*!< Channel 6 Half Transfer flag */
+#define DMA_ISR_TEIF6_Pos (23U)
+#define DMA_ISR_TEIF6_Msk (0x1U << DMA_ISR_TEIF6_Pos) /*!< 0x00800000 */
+#define DMA_ISR_TEIF6 DMA_ISR_TEIF6_Msk /*!< Channel 6 Transfer Error flag */
+#define DMA_ISR_GIF7_Pos (24U)
+#define DMA_ISR_GIF7_Msk (0x1U << DMA_ISR_GIF7_Pos) /*!< 0x01000000 */
+#define DMA_ISR_GIF7 DMA_ISR_GIF7_Msk /*!< Channel 7 Global interrupt flag */
+#define DMA_ISR_TCIF7_Pos (25U)
+#define DMA_ISR_TCIF7_Msk (0x1U << DMA_ISR_TCIF7_Pos) /*!< 0x02000000 */
+#define DMA_ISR_TCIF7 DMA_ISR_TCIF7_Msk /*!< Channel 7 Transfer Complete flag */
+#define DMA_ISR_HTIF7_Pos (26U)
+#define DMA_ISR_HTIF7_Msk (0x1U << DMA_ISR_HTIF7_Pos) /*!< 0x04000000 */
+#define DMA_ISR_HTIF7 DMA_ISR_HTIF7_Msk /*!< Channel 7 Half Transfer flag */
+#define DMA_ISR_TEIF7_Pos (27U)
+#define DMA_ISR_TEIF7_Msk (0x1U << DMA_ISR_TEIF7_Pos) /*!< 0x08000000 */
+#define DMA_ISR_TEIF7 DMA_ISR_TEIF7_Msk /*!< Channel 7 Transfer Error flag */
+
+/******************* Bit definition for DMA_IFCR register *******************/
+#define DMA_IFCR_CGIF1_Pos (0U)
+#define DMA_IFCR_CGIF1_Msk (0x1U << DMA_IFCR_CGIF1_Pos) /*!< 0x00000001 */
+#define DMA_IFCR_CGIF1 DMA_IFCR_CGIF1_Msk /*!< Channel 1 Global interrupt clear */
+#define DMA_IFCR_CTCIF1_Pos (1U)
+#define DMA_IFCR_CTCIF1_Msk (0x1U << DMA_IFCR_CTCIF1_Pos) /*!< 0x00000002 */
+#define DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF1_Msk /*!< Channel 1 Transfer Complete clear */
+#define DMA_IFCR_CHTIF1_Pos (2U)
+#define DMA_IFCR_CHTIF1_Msk (0x1U << DMA_IFCR_CHTIF1_Pos) /*!< 0x00000004 */
+#define DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF1_Msk /*!< Channel 1 Half Transfer clear */
+#define DMA_IFCR_CTEIF1_Pos (3U)
+#define DMA_IFCR_CTEIF1_Msk (0x1U << DMA_IFCR_CTEIF1_Pos) /*!< 0x00000008 */
+#define DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF1_Msk /*!< Channel 1 Transfer Error clear */
+#define DMA_IFCR_CGIF2_Pos (4U)
+#define DMA_IFCR_CGIF2_Msk (0x1U << DMA_IFCR_CGIF2_Pos) /*!< 0x00000010 */
+#define DMA_IFCR_CGIF2 DMA_IFCR_CGIF2_Msk /*!< Channel 2 Global interrupt clear */
+#define DMA_IFCR_CTCIF2_Pos (5U)
+#define DMA_IFCR_CTCIF2_Msk (0x1U << DMA_IFCR_CTCIF2_Pos) /*!< 0x00000020 */
+#define DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF2_Msk /*!< Channel 2 Transfer Complete clear */
+#define DMA_IFCR_CHTIF2_Pos (6U)
+#define DMA_IFCR_CHTIF2_Msk (0x1U << DMA_IFCR_CHTIF2_Pos) /*!< 0x00000040 */
+#define DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF2_Msk /*!< Channel 2 Half Transfer clear */
+#define DMA_IFCR_CTEIF2_Pos (7U)
+#define DMA_IFCR_CTEIF2_Msk (0x1U << DMA_IFCR_CTEIF2_Pos) /*!< 0x00000080 */
+#define DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF2_Msk /*!< Channel 2 Transfer Error clear */
+#define DMA_IFCR_CGIF3_Pos (8U)
+#define DMA_IFCR_CGIF3_Msk (0x1U << DMA_IFCR_CGIF3_Pos) /*!< 0x00000100 */
+#define DMA_IFCR_CGIF3 DMA_IFCR_CGIF3_Msk /*!< Channel 3 Global interrupt clear */
+#define DMA_IFCR_CTCIF3_Pos (9U)
+#define DMA_IFCR_CTCIF3_Msk (0x1U << DMA_IFCR_CTCIF3_Pos) /*!< 0x00000200 */
+#define DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF3_Msk /*!< Channel 3 Transfer Complete clear */
+#define DMA_IFCR_CHTIF3_Pos (10U)
+#define DMA_IFCR_CHTIF3_Msk (0x1U << DMA_IFCR_CHTIF3_Pos) /*!< 0x00000400 */
+#define DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF3_Msk /*!< Channel 3 Half Transfer clear */
+#define DMA_IFCR_CTEIF3_Pos (11U)
+#define DMA_IFCR_CTEIF3_Msk (0x1U << DMA_IFCR_CTEIF3_Pos) /*!< 0x00000800 */
+#define DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF3_Msk /*!< Channel 3 Transfer Error clear */
+#define DMA_IFCR_CGIF4_Pos (12U)
+#define DMA_IFCR_CGIF4_Msk (0x1U << DMA_IFCR_CGIF4_Pos) /*!< 0x00001000 */
+#define DMA_IFCR_CGIF4 DMA_IFCR_CGIF4_Msk /*!< Channel 4 Global interrupt clear */
+#define DMA_IFCR_CTCIF4_Pos (13U)
+#define DMA_IFCR_CTCIF4_Msk (0x1U << DMA_IFCR_CTCIF4_Pos) /*!< 0x00002000 */
+#define DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF4_Msk /*!< Channel 4 Transfer Complete clear */
+#define DMA_IFCR_CHTIF4_Pos (14U)
+#define DMA_IFCR_CHTIF4_Msk (0x1U << DMA_IFCR_CHTIF4_Pos) /*!< 0x00004000 */
+#define DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF4_Msk /*!< Channel 4 Half Transfer clear */
+#define DMA_IFCR_CTEIF4_Pos (15U)
+#define DMA_IFCR_CTEIF4_Msk (0x1U << DMA_IFCR_CTEIF4_Pos) /*!< 0x00008000 */
+#define DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF4_Msk /*!< Channel 4 Transfer Error clear */
+#define DMA_IFCR_CGIF5_Pos (16U)
+#define DMA_IFCR_CGIF5_Msk (0x1U << DMA_IFCR_CGIF5_Pos) /*!< 0x00010000 */
+#define DMA_IFCR_CGIF5 DMA_IFCR_CGIF5_Msk /*!< Channel 5 Global interrupt clear */
+#define DMA_IFCR_CTCIF5_Pos (17U)
+#define DMA_IFCR_CTCIF5_Msk (0x1U << DMA_IFCR_CTCIF5_Pos) /*!< 0x00020000 */
+#define DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF5_Msk /*!< Channel 5 Transfer Complete clear */
+#define DMA_IFCR_CHTIF5_Pos (18U)
+#define DMA_IFCR_CHTIF5_Msk (0x1U << DMA_IFCR_CHTIF5_Pos) /*!< 0x00040000 */
+#define DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5_Msk /*!< Channel 5 Half Transfer clear */
+#define DMA_IFCR_CTEIF5_Pos (19U)
+#define DMA_IFCR_CTEIF5_Msk (0x1U << DMA_IFCR_CTEIF5_Pos) /*!< 0x00080000 */
+#define DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF5_Msk /*!< Channel 5 Transfer Error clear */
+#define DMA_IFCR_CGIF6_Pos (20U)
+#define DMA_IFCR_CGIF6_Msk (0x1U << DMA_IFCR_CGIF6_Pos) /*!< 0x00100000 */
+#define DMA_IFCR_CGIF6 DMA_IFCR_CGIF6_Msk /*!< Channel 6 Global interrupt clear */
+#define DMA_IFCR_CTCIF6_Pos (21U)
+#define DMA_IFCR_CTCIF6_Msk (0x1U << DMA_IFCR_CTCIF6_Pos) /*!< 0x00200000 */
+#define DMA_IFCR_CTCIF6 DMA_IFCR_CTCIF6_Msk /*!< Channel 6 Transfer Complete clear */
+#define DMA_IFCR_CHTIF6_Pos (22U)
+#define DMA_IFCR_CHTIF6_Msk (0x1U << DMA_IFCR_CHTIF6_Pos) /*!< 0x00400000 */
+#define DMA_IFCR_CHTIF6 DMA_IFCR_CHTIF6_Msk /*!< Channel 6 Half Transfer clear */
+#define DMA_IFCR_CTEIF6_Pos (23U)
+#define DMA_IFCR_CTEIF6_Msk (0x1U << DMA_IFCR_CTEIF6_Pos) /*!< 0x00800000 */
+#define DMA_IFCR_CTEIF6 DMA_IFCR_CTEIF6_Msk /*!< Channel 6 Transfer Error clear */
+#define DMA_IFCR_CGIF7_Pos (24U)
+#define DMA_IFCR_CGIF7_Msk (0x1U << DMA_IFCR_CGIF7_Pos) /*!< 0x01000000 */
+#define DMA_IFCR_CGIF7 DMA_IFCR_CGIF7_Msk /*!< Channel 7 Global interrupt clear */
+#define DMA_IFCR_CTCIF7_Pos (25U)
+#define DMA_IFCR_CTCIF7_Msk (0x1U << DMA_IFCR_CTCIF7_Pos) /*!< 0x02000000 */
+#define DMA_IFCR_CTCIF7 DMA_IFCR_CTCIF7_Msk /*!< Channel 7 Transfer Complete clear */
+#define DMA_IFCR_CHTIF7_Pos (26U)
+#define DMA_IFCR_CHTIF7_Msk (0x1U << DMA_IFCR_CHTIF7_Pos) /*!< 0x04000000 */
+#define DMA_IFCR_CHTIF7 DMA_IFCR_CHTIF7_Msk /*!< Channel 7 Half Transfer clear */
+#define DMA_IFCR_CTEIF7_Pos (27U)
+#define DMA_IFCR_CTEIF7_Msk (0x1U << DMA_IFCR_CTEIF7_Pos) /*!< 0x08000000 */
+#define DMA_IFCR_CTEIF7 DMA_IFCR_CTEIF7_Msk /*!< Channel 7 Transfer Error clear */
+
+/******************* Bit definition for DMA_CCR register *******************/
+#define DMA_CCR_EN_Pos (0U)
+#define DMA_CCR_EN_Msk (0x1U << DMA_CCR_EN_Pos) /*!< 0x00000001 */
+#define DMA_CCR_EN DMA_CCR_EN_Msk /*!< Channel enable */
+#define DMA_CCR_TCIE_Pos (1U)
+#define DMA_CCR_TCIE_Msk (0x1U << DMA_CCR_TCIE_Pos) /*!< 0x00000002 */
+#define DMA_CCR_TCIE DMA_CCR_TCIE_Msk /*!< Transfer complete interrupt enable */
+#define DMA_CCR_HTIE_Pos (2U)
+#define DMA_CCR_HTIE_Msk (0x1U << DMA_CCR_HTIE_Pos) /*!< 0x00000004 */
+#define DMA_CCR_HTIE DMA_CCR_HTIE_Msk /*!< Half Transfer interrupt enable */
+#define DMA_CCR_TEIE_Pos (3U)
+#define DMA_CCR_TEIE_Msk (0x1U << DMA_CCR_TEIE_Pos) /*!< 0x00000008 */
+#define DMA_CCR_TEIE DMA_CCR_TEIE_Msk /*!< Transfer error interrupt enable */
+#define DMA_CCR_DIR_Pos (4U)
+#define DMA_CCR_DIR_Msk (0x1U << DMA_CCR_DIR_Pos) /*!< 0x00000010 */
+#define DMA_CCR_DIR DMA_CCR_DIR_Msk /*!< Data transfer direction */
+#define DMA_CCR_CIRC_Pos (5U)
+#define DMA_CCR_CIRC_Msk (0x1U << DMA_CCR_CIRC_Pos) /*!< 0x00000020 */
+#define DMA_CCR_CIRC DMA_CCR_CIRC_Msk /*!< Circular mode */
+#define DMA_CCR_PINC_Pos (6U)
+#define DMA_CCR_PINC_Msk (0x1U << DMA_CCR_PINC_Pos) /*!< 0x00000040 */
+#define DMA_CCR_PINC DMA_CCR_PINC_Msk /*!< Peripheral increment mode */
+#define DMA_CCR_MINC_Pos (7U)
+#define DMA_CCR_MINC_Msk (0x1U << DMA_CCR_MINC_Pos) /*!< 0x00000080 */
+#define DMA_CCR_MINC DMA_CCR_MINC_Msk /*!< Memory increment mode */
+
+#define DMA_CCR_PSIZE_Pos (8U)
+#define DMA_CCR_PSIZE_Msk (0x3U << DMA_CCR_PSIZE_Pos) /*!< 0x00000300 */
+#define DMA_CCR_PSIZE DMA_CCR_PSIZE_Msk /*!< PSIZE[1:0] bits (Peripheral size) */
+#define DMA_CCR_PSIZE_0 (0x1U << DMA_CCR_PSIZE_Pos) /*!< 0x00000100 */
+#define DMA_CCR_PSIZE_1 (0x2U << DMA_CCR_PSIZE_Pos) /*!< 0x00000200 */
+
+#define DMA_CCR_MSIZE_Pos (10U)
+#define DMA_CCR_MSIZE_Msk (0x3U << DMA_CCR_MSIZE_Pos) /*!< 0x00000C00 */
+#define DMA_CCR_MSIZE DMA_CCR_MSIZE_Msk /*!< MSIZE[1:0] bits (Memory size) */
+#define DMA_CCR_MSIZE_0 (0x1U << DMA_CCR_MSIZE_Pos) /*!< 0x00000400 */
+#define DMA_CCR_MSIZE_1 (0x2U << DMA_CCR_MSIZE_Pos) /*!< 0x00000800 */
+
+#define DMA_CCR_PL_Pos (12U)
+#define DMA_CCR_PL_Msk (0x3U << DMA_CCR_PL_Pos) /*!< 0x00003000 */
+#define DMA_CCR_PL DMA_CCR_PL_Msk /*!< PL[1:0] bits(Channel Priority level) */
+#define DMA_CCR_PL_0 (0x1U << DMA_CCR_PL_Pos) /*!< 0x00001000 */
+#define DMA_CCR_PL_1 (0x2U << DMA_CCR_PL_Pos) /*!< 0x00002000 */
+
+#define DMA_CCR_MEM2MEM_Pos (14U)
+#define DMA_CCR_MEM2MEM_Msk (0x1U << DMA_CCR_MEM2MEM_Pos) /*!< 0x00004000 */
+#define DMA_CCR_MEM2MEM DMA_CCR_MEM2MEM_Msk /*!< Memory to memory mode */
+
+/****************** Bit definition for DMA_CNDTR register ******************/
+#define DMA_CNDTR_NDT_Pos (0U)
+#define DMA_CNDTR_NDT_Msk (0xFFFFU << DMA_CNDTR_NDT_Pos) /*!< 0x0000FFFF */
+#define DMA_CNDTR_NDT DMA_CNDTR_NDT_Msk /*!< Number of data to Transfer */
+
+/****************** Bit definition for DMA_CPAR register *******************/
+#define DMA_CPAR_PA_Pos (0U)
+#define DMA_CPAR_PA_Msk (0xFFFFFFFFU << DMA_CPAR_PA_Pos) /*!< 0xFFFFFFFF */
+#define DMA_CPAR_PA DMA_CPAR_PA_Msk /*!< Peripheral Address */
+
+/****************** Bit definition for DMA_CMAR register *******************/
+#define DMA_CMAR_MA_Pos (0U)
+#define DMA_CMAR_MA_Msk (0xFFFFFFFFU << DMA_CMAR_MA_Pos) /*!< 0xFFFFFFFF */
+#define DMA_CMAR_MA DMA_CMAR_MA_Msk /*!< Memory Address */
+
+/******************************************************************************/
+/* */
+/* Analog to Digital Converter (ADC) */
+/* */
+/******************************************************************************/
+
+/*
+ * @brief Specific device feature definitions (not present on all devices in the STM32F1 family)
+ */
+#define ADC_MULTIMODE_SUPPORT /*!< ADC feature available only on specific devices: multimode available on devices with several ADC instances */
+
+/******************** Bit definition for ADC_SR register ********************/
+#define ADC_SR_AWD_Pos (0U)
+#define ADC_SR_AWD_Msk (0x1U << ADC_SR_AWD_Pos) /*!< 0x00000001 */
+#define ADC_SR_AWD ADC_SR_AWD_Msk /*!< ADC analog watchdog 1 flag */
+#define ADC_SR_EOS_Pos (1U)
+#define ADC_SR_EOS_Msk (0x1U << ADC_SR_EOS_Pos) /*!< 0x00000002 */
+#define ADC_SR_EOS ADC_SR_EOS_Msk /*!< ADC group regular end of sequence conversions flag */
+#define ADC_SR_JEOS_Pos (2U)
+#define ADC_SR_JEOS_Msk (0x1U << ADC_SR_JEOS_Pos) /*!< 0x00000004 */
+#define ADC_SR_JEOS ADC_SR_JEOS_Msk /*!< ADC group injected end of sequence conversions flag */
+#define ADC_SR_JSTRT_Pos (3U)
+#define ADC_SR_JSTRT_Msk (0x1U << ADC_SR_JSTRT_Pos) /*!< 0x00000008 */
+#define ADC_SR_JSTRT ADC_SR_JSTRT_Msk /*!< ADC group injected conversion start flag */
+#define ADC_SR_STRT_Pos (4U)
+#define ADC_SR_STRT_Msk (0x1U << ADC_SR_STRT_Pos) /*!< 0x00000010 */
+#define ADC_SR_STRT ADC_SR_STRT_Msk /*!< ADC group regular conversion start flag */
+
+/* Legacy defines */
+#define ADC_SR_EOC (ADC_SR_EOS)
+#define ADC_SR_JEOC (ADC_SR_JEOS)
+
+/******************* Bit definition for ADC_CR1 register ********************/
+#define ADC_CR1_AWDCH_Pos (0U)
+#define ADC_CR1_AWDCH_Msk (0x1FU << ADC_CR1_AWDCH_Pos) /*!< 0x0000001F */
+#define ADC_CR1_AWDCH ADC_CR1_AWDCH_Msk /*!< ADC analog watchdog 1 monitored channel selection */
+#define ADC_CR1_AWDCH_0 (0x01U << ADC_CR1_AWDCH_Pos) /*!< 0x00000001 */
+#define ADC_CR1_AWDCH_1 (0x02U << ADC_CR1_AWDCH_Pos) /*!< 0x00000002 */
+#define ADC_CR1_AWDCH_2 (0x04U << ADC_CR1_AWDCH_Pos) /*!< 0x00000004 */
+#define ADC_CR1_AWDCH_3 (0x08U << ADC_CR1_AWDCH_Pos) /*!< 0x00000008 */
+#define ADC_CR1_AWDCH_4 (0x10U << ADC_CR1_AWDCH_Pos) /*!< 0x00000010 */
+
+#define ADC_CR1_EOSIE_Pos (5U)
+#define ADC_CR1_EOSIE_Msk (0x1U << ADC_CR1_EOSIE_Pos) /*!< 0x00000020 */
+#define ADC_CR1_EOSIE ADC_CR1_EOSIE_Msk /*!< ADC group regular end of sequence conversions interrupt */
+#define ADC_CR1_AWDIE_Pos (6U)
+#define ADC_CR1_AWDIE_Msk (0x1U << ADC_CR1_AWDIE_Pos) /*!< 0x00000040 */
+#define ADC_CR1_AWDIE ADC_CR1_AWDIE_Msk /*!< ADC analog watchdog 1 interrupt */
+#define ADC_CR1_JEOSIE_Pos (7U)
+#define ADC_CR1_JEOSIE_Msk (0x1U << ADC_CR1_JEOSIE_Pos) /*!< 0x00000080 */
+#define ADC_CR1_JEOSIE ADC_CR1_JEOSIE_Msk /*!< ADC group injected end of sequence conversions interrupt */
+#define ADC_CR1_SCAN_Pos (8U)
+#define ADC_CR1_SCAN_Msk (0x1U << ADC_CR1_SCAN_Pos) /*!< 0x00000100 */
+#define ADC_CR1_SCAN ADC_CR1_SCAN_Msk /*!< ADC scan mode */
+#define ADC_CR1_AWDSGL_Pos (9U)
+#define ADC_CR1_AWDSGL_Msk (0x1U << ADC_CR1_AWDSGL_Pos) /*!< 0x00000200 */
+#define ADC_CR1_AWDSGL ADC_CR1_AWDSGL_Msk /*!< ADC analog watchdog 1 monitoring a single channel or all channels */
+#define ADC_CR1_JAUTO_Pos (10U)
+#define ADC_CR1_JAUTO_Msk (0x1U << ADC_CR1_JAUTO_Pos) /*!< 0x00000400 */
+#define ADC_CR1_JAUTO ADC_CR1_JAUTO_Msk /*!< ADC group injected automatic trigger mode */
+#define ADC_CR1_DISCEN_Pos (11U)
+#define ADC_CR1_DISCEN_Msk (0x1U << ADC_CR1_DISCEN_Pos) /*!< 0x00000800 */
+#define ADC_CR1_DISCEN ADC_CR1_DISCEN_Msk /*!< ADC group regular sequencer discontinuous mode */
+#define ADC_CR1_JDISCEN_Pos (12U)
+#define ADC_CR1_JDISCEN_Msk (0x1U << ADC_CR1_JDISCEN_Pos) /*!< 0x00001000 */
+#define ADC_CR1_JDISCEN ADC_CR1_JDISCEN_Msk /*!< ADC group injected sequencer discontinuous mode */
+
+#define ADC_CR1_DISCNUM_Pos (13U)
+#define ADC_CR1_DISCNUM_Msk (0x7U << ADC_CR1_DISCNUM_Pos) /*!< 0x0000E000 */
+#define ADC_CR1_DISCNUM ADC_CR1_DISCNUM_Msk /*!< ADC group regular sequencer discontinuous number of ranks */
+#define ADC_CR1_DISCNUM_0 (0x1U << ADC_CR1_DISCNUM_Pos) /*!< 0x00002000 */
+#define ADC_CR1_DISCNUM_1 (0x2U << ADC_CR1_DISCNUM_Pos) /*!< 0x00004000 */
+#define ADC_CR1_DISCNUM_2 (0x4U << ADC_CR1_DISCNUM_Pos) /*!< 0x00008000 */
+
+#define ADC_CR1_DUALMOD_Pos (16U)
+#define ADC_CR1_DUALMOD_Msk (0xFU << ADC_CR1_DUALMOD_Pos) /*!< 0x000F0000 */
+#define ADC_CR1_DUALMOD ADC_CR1_DUALMOD_Msk /*!< ADC multimode mode selection */
+#define ADC_CR1_DUALMOD_0 (0x1U << ADC_CR1_DUALMOD_Pos) /*!< 0x00010000 */
+#define ADC_CR1_DUALMOD_1 (0x2U << ADC_CR1_DUALMOD_Pos) /*!< 0x00020000 */
+#define ADC_CR1_DUALMOD_2 (0x4U << ADC_CR1_DUALMOD_Pos) /*!< 0x00040000 */
+#define ADC_CR1_DUALMOD_3 (0x8U << ADC_CR1_DUALMOD_Pos) /*!< 0x00080000 */
+
+#define ADC_CR1_JAWDEN_Pos (22U)
+#define ADC_CR1_JAWDEN_Msk (0x1U << ADC_CR1_JAWDEN_Pos) /*!< 0x00400000 */
+#define ADC_CR1_JAWDEN ADC_CR1_JAWDEN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group injected */
+#define ADC_CR1_AWDEN_Pos (23U)
+#define ADC_CR1_AWDEN_Msk (0x1U << ADC_CR1_AWDEN_Pos) /*!< 0x00800000 */
+#define ADC_CR1_AWDEN ADC_CR1_AWDEN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group regular */
+
+/* Legacy defines */
+#define ADC_CR1_EOCIE (ADC_CR1_EOSIE)
+#define ADC_CR1_JEOCIE (ADC_CR1_JEOSIE)
+
+/******************* Bit definition for ADC_CR2 register ********************/
+#define ADC_CR2_ADON_Pos (0U)
+#define ADC_CR2_ADON_Msk (0x1U << ADC_CR2_ADON_Pos) /*!< 0x00000001 */
+#define ADC_CR2_ADON ADC_CR2_ADON_Msk /*!< ADC enable */
+#define ADC_CR2_CONT_Pos (1U)
+#define ADC_CR2_CONT_Msk (0x1U << ADC_CR2_CONT_Pos) /*!< 0x00000002 */
+#define ADC_CR2_CONT ADC_CR2_CONT_Msk /*!< ADC group regular continuous conversion mode */
+#define ADC_CR2_CAL_Pos (2U)
+#define ADC_CR2_CAL_Msk (0x1U << ADC_CR2_CAL_Pos) /*!< 0x00000004 */
+#define ADC_CR2_CAL ADC_CR2_CAL_Msk /*!< ADC calibration start */
+#define ADC_CR2_RSTCAL_Pos (3U)
+#define ADC_CR2_RSTCAL_Msk (0x1U << ADC_CR2_RSTCAL_Pos) /*!< 0x00000008 */
+#define ADC_CR2_RSTCAL ADC_CR2_RSTCAL_Msk /*!< ADC calibration reset */
+#define ADC_CR2_DMA_Pos (8U)
+#define ADC_CR2_DMA_Msk (0x1U << ADC_CR2_DMA_Pos) /*!< 0x00000100 */
+#define ADC_CR2_DMA ADC_CR2_DMA_Msk /*!< ADC DMA transfer enable */
+#define ADC_CR2_ALIGN_Pos (11U)
+#define ADC_CR2_ALIGN_Msk (0x1U << ADC_CR2_ALIGN_Pos) /*!< 0x00000800 */
+#define ADC_CR2_ALIGN ADC_CR2_ALIGN_Msk /*!< ADC data alignement */
+
+#define ADC_CR2_JEXTSEL_Pos (12U)
+#define ADC_CR2_JEXTSEL_Msk (0x7U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00007000 */
+#define ADC_CR2_JEXTSEL ADC_CR2_JEXTSEL_Msk /*!< ADC group injected external trigger source */
+#define ADC_CR2_JEXTSEL_0 (0x1U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00001000 */
+#define ADC_CR2_JEXTSEL_1 (0x2U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00002000 */
+#define ADC_CR2_JEXTSEL_2 (0x4U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00004000 */
+
+#define ADC_CR2_JEXTTRIG_Pos (15U)
+#define ADC_CR2_JEXTTRIG_Msk (0x1U << ADC_CR2_JEXTTRIG_Pos) /*!< 0x00008000 */
+#define ADC_CR2_JEXTTRIG ADC_CR2_JEXTTRIG_Msk /*!< ADC group injected external trigger enable */
+
+#define ADC_CR2_EXTSEL_Pos (17U)
+#define ADC_CR2_EXTSEL_Msk (0x7U << ADC_CR2_EXTSEL_Pos) /*!< 0x000E0000 */
+#define ADC_CR2_EXTSEL ADC_CR2_EXTSEL_Msk /*!< ADC group regular external trigger source */
+#define ADC_CR2_EXTSEL_0 (0x1U << ADC_CR2_EXTSEL_Pos) /*!< 0x00020000 */
+#define ADC_CR2_EXTSEL_1 (0x2U << ADC_CR2_EXTSEL_Pos) /*!< 0x00040000 */
+#define ADC_CR2_EXTSEL_2 (0x4U << ADC_CR2_EXTSEL_Pos) /*!< 0x00080000 */
+
+#define ADC_CR2_EXTTRIG_Pos (20U)
+#define ADC_CR2_EXTTRIG_Msk (0x1U << ADC_CR2_EXTTRIG_Pos) /*!< 0x00100000 */
+#define ADC_CR2_EXTTRIG ADC_CR2_EXTTRIG_Msk /*!< ADC group regular external trigger enable */
+#define ADC_CR2_JSWSTART_Pos (21U)
+#define ADC_CR2_JSWSTART_Msk (0x1U << ADC_CR2_JSWSTART_Pos) /*!< 0x00200000 */
+#define ADC_CR2_JSWSTART ADC_CR2_JSWSTART_Msk /*!< ADC group injected conversion start */
+#define ADC_CR2_SWSTART_Pos (22U)
+#define ADC_CR2_SWSTART_Msk (0x1U << ADC_CR2_SWSTART_Pos) /*!< 0x00400000 */
+#define ADC_CR2_SWSTART ADC_CR2_SWSTART_Msk /*!< ADC group regular conversion start */
+#define ADC_CR2_TSVREFE_Pos (23U)
+#define ADC_CR2_TSVREFE_Msk (0x1U << ADC_CR2_TSVREFE_Pos) /*!< 0x00800000 */
+#define ADC_CR2_TSVREFE ADC_CR2_TSVREFE_Msk /*!< ADC internal path to VrefInt and temperature sensor enable */
+
+/****************** Bit definition for ADC_SMPR1 register *******************/
+#define ADC_SMPR1_SMP10_Pos (0U)
+#define ADC_SMPR1_SMP10_Msk (0x7U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000007 */
+#define ADC_SMPR1_SMP10 ADC_SMPR1_SMP10_Msk /*!< ADC channel 10 sampling time selection */
+#define ADC_SMPR1_SMP10_0 (0x1U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000001 */
+#define ADC_SMPR1_SMP10_1 (0x2U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000002 */
+#define ADC_SMPR1_SMP10_2 (0x4U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000004 */
+
+#define ADC_SMPR1_SMP11_Pos (3U)
+#define ADC_SMPR1_SMP11_Msk (0x7U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000038 */
+#define ADC_SMPR1_SMP11 ADC_SMPR1_SMP11_Msk /*!< ADC channel 11 sampling time selection */
+#define ADC_SMPR1_SMP11_0 (0x1U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000008 */
+#define ADC_SMPR1_SMP11_1 (0x2U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000010 */
+#define ADC_SMPR1_SMP11_2 (0x4U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000020 */
+
+#define ADC_SMPR1_SMP12_Pos (6U)
+#define ADC_SMPR1_SMP12_Msk (0x7U << ADC_SMPR1_SMP12_Pos) /*!< 0x000001C0 */
+#define ADC_SMPR1_SMP12 ADC_SMPR1_SMP12_Msk /*!< ADC channel 12 sampling time selection */
+#define ADC_SMPR1_SMP12_0 (0x1U << ADC_SMPR1_SMP12_Pos) /*!< 0x00000040 */
+#define ADC_SMPR1_SMP12_1 (0x2U << ADC_SMPR1_SMP12_Pos) /*!< 0x00000080 */
+#define ADC_SMPR1_SMP12_2 (0x4U << ADC_SMPR1_SMP12_Pos) /*!< 0x00000100 */
+
+#define ADC_SMPR1_SMP13_Pos (9U)
+#define ADC_SMPR1_SMP13_Msk (0x7U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000E00 */
+#define ADC_SMPR1_SMP13 ADC_SMPR1_SMP13_Msk /*!< ADC channel 13 sampling time selection */
+#define ADC_SMPR1_SMP13_0 (0x1U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000200 */
+#define ADC_SMPR1_SMP13_1 (0x2U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000400 */
+#define ADC_SMPR1_SMP13_2 (0x4U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000800 */
+
+#define ADC_SMPR1_SMP14_Pos (12U)
+#define ADC_SMPR1_SMP14_Msk (0x7U << ADC_SMPR1_SMP14_Pos) /*!< 0x00007000 */
+#define ADC_SMPR1_SMP14 ADC_SMPR1_SMP14_Msk /*!< ADC channel 14 sampling time selection */
+#define ADC_SMPR1_SMP14_0 (0x1U << ADC_SMPR1_SMP14_Pos) /*!< 0x00001000 */
+#define ADC_SMPR1_SMP14_1 (0x2U << ADC_SMPR1_SMP14_Pos) /*!< 0x00002000 */
+#define ADC_SMPR1_SMP14_2 (0x4U << ADC_SMPR1_SMP14_Pos) /*!< 0x00004000 */
+
+#define ADC_SMPR1_SMP15_Pos (15U)
+#define ADC_SMPR1_SMP15_Msk (0x7U << ADC_SMPR1_SMP15_Pos) /*!< 0x00038000 */
+#define ADC_SMPR1_SMP15 ADC_SMPR1_SMP15_Msk /*!< ADC channel 15 sampling time selection */
+#define ADC_SMPR1_SMP15_0 (0x1U << ADC_SMPR1_SMP15_Pos) /*!< 0x00008000 */
+#define ADC_SMPR1_SMP15_1 (0x2U << ADC_SMPR1_SMP15_Pos) /*!< 0x00010000 */
+#define ADC_SMPR1_SMP15_2 (0x4U << ADC_SMPR1_SMP15_Pos) /*!< 0x00020000 */
+
+#define ADC_SMPR1_SMP16_Pos (18U)
+#define ADC_SMPR1_SMP16_Msk (0x7U << ADC_SMPR1_SMP16_Pos) /*!< 0x001C0000 */
+#define ADC_SMPR1_SMP16 ADC_SMPR1_SMP16_Msk /*!< ADC channel 16 sampling time selection */
+#define ADC_SMPR1_SMP16_0 (0x1U << ADC_SMPR1_SMP16_Pos) /*!< 0x00040000 */
+#define ADC_SMPR1_SMP16_1 (0x2U << ADC_SMPR1_SMP16_Pos) /*!< 0x00080000 */
+#define ADC_SMPR1_SMP16_2 (0x4U << ADC_SMPR1_SMP16_Pos) /*!< 0x00100000 */
+
+#define ADC_SMPR1_SMP17_Pos (21U)
+#define ADC_SMPR1_SMP17_Msk (0x7U << ADC_SMPR1_SMP17_Pos) /*!< 0x00E00000 */
+#define ADC_SMPR1_SMP17 ADC_SMPR1_SMP17_Msk /*!< ADC channel 17 sampling time selection */
+#define ADC_SMPR1_SMP17_0 (0x1U << ADC_SMPR1_SMP17_Pos) /*!< 0x00200000 */
+#define ADC_SMPR1_SMP17_1 (0x2U << ADC_SMPR1_SMP17_Pos) /*!< 0x00400000 */
+#define ADC_SMPR1_SMP17_2 (0x4U << ADC_SMPR1_SMP17_Pos) /*!< 0x00800000 */
+
+/****************** Bit definition for ADC_SMPR2 register *******************/
+#define ADC_SMPR2_SMP0_Pos (0U)
+#define ADC_SMPR2_SMP0_Msk (0x7U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000007 */
+#define ADC_SMPR2_SMP0 ADC_SMPR2_SMP0_Msk /*!< ADC channel 0 sampling time selection */
+#define ADC_SMPR2_SMP0_0 (0x1U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000001 */
+#define ADC_SMPR2_SMP0_1 (0x2U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000002 */
+#define ADC_SMPR2_SMP0_2 (0x4U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000004 */
+
+#define ADC_SMPR2_SMP1_Pos (3U)
+#define ADC_SMPR2_SMP1_Msk (0x7U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000038 */
+#define ADC_SMPR2_SMP1 ADC_SMPR2_SMP1_Msk /*!< ADC channel 1 sampling time selection */
+#define ADC_SMPR2_SMP1_0 (0x1U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000008 */
+#define ADC_SMPR2_SMP1_1 (0x2U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000010 */
+#define ADC_SMPR2_SMP1_2 (0x4U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000020 */
+
+#define ADC_SMPR2_SMP2_Pos (6U)
+#define ADC_SMPR2_SMP2_Msk (0x7U << ADC_SMPR2_SMP2_Pos) /*!< 0x000001C0 */
+#define ADC_SMPR2_SMP2 ADC_SMPR2_SMP2_Msk /*!< ADC channel 2 sampling time selection */
+#define ADC_SMPR2_SMP2_0 (0x1U << ADC_SMPR2_SMP2_Pos) /*!< 0x00000040 */
+#define ADC_SMPR2_SMP2_1 (0x2U << ADC_SMPR2_SMP2_Pos) /*!< 0x00000080 */
+#define ADC_SMPR2_SMP2_2 (0x4U << ADC_SMPR2_SMP2_Pos) /*!< 0x00000100 */
+
+#define ADC_SMPR2_SMP3_Pos (9U)
+#define ADC_SMPR2_SMP3_Msk (0x7U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000E00 */
+#define ADC_SMPR2_SMP3 ADC_SMPR2_SMP3_Msk /*!< ADC channel 3 sampling time selection */
+#define ADC_SMPR2_SMP3_0 (0x1U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000200 */
+#define ADC_SMPR2_SMP3_1 (0x2U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000400 */
+#define ADC_SMPR2_SMP3_2 (0x4U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000800 */
+
+#define ADC_SMPR2_SMP4_Pos (12U)
+#define ADC_SMPR2_SMP4_Msk (0x7U << ADC_SMPR2_SMP4_Pos) /*!< 0x00007000 */
+#define ADC_SMPR2_SMP4 ADC_SMPR2_SMP4_Msk /*!< ADC channel 4 sampling time selection */
+#define ADC_SMPR2_SMP4_0 (0x1U << ADC_SMPR2_SMP4_Pos) /*!< 0x00001000 */
+#define ADC_SMPR2_SMP4_1 (0x2U << ADC_SMPR2_SMP4_Pos) /*!< 0x00002000 */
+#define ADC_SMPR2_SMP4_2 (0x4U << ADC_SMPR2_SMP4_Pos) /*!< 0x00004000 */
+
+#define ADC_SMPR2_SMP5_Pos (15U)
+#define ADC_SMPR2_SMP5_Msk (0x7U << ADC_SMPR2_SMP5_Pos) /*!< 0x00038000 */
+#define ADC_SMPR2_SMP5 ADC_SMPR2_SMP5_Msk /*!< ADC channel 5 sampling time selection */
+#define ADC_SMPR2_SMP5_0 (0x1U << ADC_SMPR2_SMP5_Pos) /*!< 0x00008000 */
+#define ADC_SMPR2_SMP5_1 (0x2U << ADC_SMPR2_SMP5_Pos) /*!< 0x00010000 */
+#define ADC_SMPR2_SMP5_2 (0x4U << ADC_SMPR2_SMP5_Pos) /*!< 0x00020000 */
+
+#define ADC_SMPR2_SMP6_Pos (18U)
+#define ADC_SMPR2_SMP6_Msk (0x7U << ADC_SMPR2_SMP6_Pos) /*!< 0x001C0000 */
+#define ADC_SMPR2_SMP6 ADC_SMPR2_SMP6_Msk /*!< ADC channel 6 sampling time selection */
+#define ADC_SMPR2_SMP6_0 (0x1U << ADC_SMPR2_SMP6_Pos) /*!< 0x00040000 */
+#define ADC_SMPR2_SMP6_1 (0x2U << ADC_SMPR2_SMP6_Pos) /*!< 0x00080000 */
+#define ADC_SMPR2_SMP6_2 (0x4U << ADC_SMPR2_SMP6_Pos) /*!< 0x00100000 */
+
+#define ADC_SMPR2_SMP7_Pos (21U)
+#define ADC_SMPR2_SMP7_Msk (0x7U << ADC_SMPR2_SMP7_Pos) /*!< 0x00E00000 */
+#define ADC_SMPR2_SMP7 ADC_SMPR2_SMP7_Msk /*!< ADC channel 7 sampling time selection */
+#define ADC_SMPR2_SMP7_0 (0x1U << ADC_SMPR2_SMP7_Pos) /*!< 0x00200000 */
+#define ADC_SMPR2_SMP7_1 (0x2U << ADC_SMPR2_SMP7_Pos) /*!< 0x00400000 */
+#define ADC_SMPR2_SMP7_2 (0x4U << ADC_SMPR2_SMP7_Pos) /*!< 0x00800000 */
+
+#define ADC_SMPR2_SMP8_Pos (24U)
+#define ADC_SMPR2_SMP8_Msk (0x7U << ADC_SMPR2_SMP8_Pos) /*!< 0x07000000 */
+#define ADC_SMPR2_SMP8 ADC_SMPR2_SMP8_Msk /*!< ADC channel 8 sampling time selection */
+#define ADC_SMPR2_SMP8_0 (0x1U << ADC_SMPR2_SMP8_Pos) /*!< 0x01000000 */
+#define ADC_SMPR2_SMP8_1 (0x2U << ADC_SMPR2_SMP8_Pos) /*!< 0x02000000 */
+#define ADC_SMPR2_SMP8_2 (0x4U << ADC_SMPR2_SMP8_Pos) /*!< 0x04000000 */
+
+#define ADC_SMPR2_SMP9_Pos (27U)
+#define ADC_SMPR2_SMP9_Msk (0x7U << ADC_SMPR2_SMP9_Pos) /*!< 0x38000000 */
+#define ADC_SMPR2_SMP9 ADC_SMPR2_SMP9_Msk /*!< ADC channel 9 sampling time selection */
+#define ADC_SMPR2_SMP9_0 (0x1U << ADC_SMPR2_SMP9_Pos) /*!< 0x08000000 */
+#define ADC_SMPR2_SMP9_1 (0x2U << ADC_SMPR2_SMP9_Pos) /*!< 0x10000000 */
+#define ADC_SMPR2_SMP9_2 (0x4U << ADC_SMPR2_SMP9_Pos) /*!< 0x20000000 */
+
+/****************** Bit definition for ADC_JOFR1 register *******************/
+#define ADC_JOFR1_JOFFSET1_Pos (0U)
+#define ADC_JOFR1_JOFFSET1_Msk (0xFFFU << ADC_JOFR1_JOFFSET1_Pos) /*!< 0x00000FFF */
+#define ADC_JOFR1_JOFFSET1 ADC_JOFR1_JOFFSET1_Msk /*!< ADC group injected sequencer rank 1 offset value */
+
+/****************** Bit definition for ADC_JOFR2 register *******************/
+#define ADC_JOFR2_JOFFSET2_Pos (0U)
+#define ADC_JOFR2_JOFFSET2_Msk (0xFFFU << ADC_JOFR2_JOFFSET2_Pos) /*!< 0x00000FFF */
+#define ADC_JOFR2_JOFFSET2 ADC_JOFR2_JOFFSET2_Msk /*!< ADC group injected sequencer rank 2 offset value */
+
+/****************** Bit definition for ADC_JOFR3 register *******************/
+#define ADC_JOFR3_JOFFSET3_Pos (0U)
+#define ADC_JOFR3_JOFFSET3_Msk (0xFFFU << ADC_JOFR3_JOFFSET3_Pos) /*!< 0x00000FFF */
+#define ADC_JOFR3_JOFFSET3 ADC_JOFR3_JOFFSET3_Msk /*!< ADC group injected sequencer rank 3 offset value */
+
+/****************** Bit definition for ADC_JOFR4 register *******************/
+#define ADC_JOFR4_JOFFSET4_Pos (0U)
+#define ADC_JOFR4_JOFFSET4_Msk (0xFFFU << ADC_JOFR4_JOFFSET4_Pos) /*!< 0x00000FFF */
+#define ADC_JOFR4_JOFFSET4 ADC_JOFR4_JOFFSET4_Msk /*!< ADC group injected sequencer rank 4 offset value */
+
+/******************* Bit definition for ADC_HTR register ********************/
+#define ADC_HTR_HT_Pos (0U)
+#define ADC_HTR_HT_Msk (0xFFFU << ADC_HTR_HT_Pos) /*!< 0x00000FFF */
+#define ADC_HTR_HT ADC_HTR_HT_Msk /*!< ADC analog watchdog 1 threshold high */
+
+/******************* Bit definition for ADC_LTR register ********************/
+#define ADC_LTR_LT_Pos (0U)
+#define ADC_LTR_LT_Msk (0xFFFU << ADC_LTR_LT_Pos) /*!< 0x00000FFF */
+#define ADC_LTR_LT ADC_LTR_LT_Msk /*!< ADC analog watchdog 1 threshold low */
+
+/******************* Bit definition for ADC_SQR1 register *******************/
+#define ADC_SQR1_SQ13_Pos (0U)
+#define ADC_SQR1_SQ13_Msk (0x1FU << ADC_SQR1_SQ13_Pos) /*!< 0x0000001F */
+#define ADC_SQR1_SQ13 ADC_SQR1_SQ13_Msk /*!< ADC group regular sequencer rank 13 */
+#define ADC_SQR1_SQ13_0 (0x01U << ADC_SQR1_SQ13_Pos) /*!< 0x00000001 */
+#define ADC_SQR1_SQ13_1 (0x02U << ADC_SQR1_SQ13_Pos) /*!< 0x00000002 */
+#define ADC_SQR1_SQ13_2 (0x04U << ADC_SQR1_SQ13_Pos) /*!< 0x00000004 */
+#define ADC_SQR1_SQ13_3 (0x08U << ADC_SQR1_SQ13_Pos) /*!< 0x00000008 */
+#define ADC_SQR1_SQ13_4 (0x10U << ADC_SQR1_SQ13_Pos) /*!< 0x00000010 */
+
+#define ADC_SQR1_SQ14_Pos (5U)
+#define ADC_SQR1_SQ14_Msk (0x1FU << ADC_SQR1_SQ14_Pos) /*!< 0x000003E0 */
+#define ADC_SQR1_SQ14 ADC_SQR1_SQ14_Msk /*!< ADC group regular sequencer rank 14 */
+#define ADC_SQR1_SQ14_0 (0x01U << ADC_SQR1_SQ14_Pos) /*!< 0x00000020 */
+#define ADC_SQR1_SQ14_1 (0x02U << ADC_SQR1_SQ14_Pos) /*!< 0x00000040 */
+#define ADC_SQR1_SQ14_2 (0x04U << ADC_SQR1_SQ14_Pos) /*!< 0x00000080 */
+#define ADC_SQR1_SQ14_3 (0x08U << ADC_SQR1_SQ14_Pos) /*!< 0x00000100 */
+#define ADC_SQR1_SQ14_4 (0x10U << ADC_SQR1_SQ14_Pos) /*!< 0x00000200 */
+
+#define ADC_SQR1_SQ15_Pos (10U)
+#define ADC_SQR1_SQ15_Msk (0x1FU << ADC_SQR1_SQ15_Pos) /*!< 0x00007C00 */
+#define ADC_SQR1_SQ15 ADC_SQR1_SQ15_Msk /*!< ADC group regular sequencer rank 15 */
+#define ADC_SQR1_SQ15_0 (0x01U << ADC_SQR1_SQ15_Pos) /*!< 0x00000400 */
+#define ADC_SQR1_SQ15_1 (0x02U << ADC_SQR1_SQ15_Pos) /*!< 0x00000800 */
+#define ADC_SQR1_SQ15_2 (0x04U << ADC_SQR1_SQ15_Pos) /*!< 0x00001000 */
+#define ADC_SQR1_SQ15_3 (0x08U << ADC_SQR1_SQ15_Pos) /*!< 0x00002000 */
+#define ADC_SQR1_SQ15_4 (0x10U << ADC_SQR1_SQ15_Pos) /*!< 0x00004000 */
+
+#define ADC_SQR1_SQ16_Pos (15U)
+#define ADC_SQR1_SQ16_Msk (0x1FU << ADC_SQR1_SQ16_Pos) /*!< 0x000F8000 */
+#define ADC_SQR1_SQ16 ADC_SQR1_SQ16_Msk /*!< ADC group regular sequencer rank 16 */
+#define ADC_SQR1_SQ16_0 (0x01U << ADC_SQR1_SQ16_Pos) /*!< 0x00008000 */
+#define ADC_SQR1_SQ16_1 (0x02U << ADC_SQR1_SQ16_Pos) /*!< 0x00010000 */
+#define ADC_SQR1_SQ16_2 (0x04U << ADC_SQR1_SQ16_Pos) /*!< 0x00020000 */
+#define ADC_SQR1_SQ16_3 (0x08U << ADC_SQR1_SQ16_Pos) /*!< 0x00040000 */
+#define ADC_SQR1_SQ16_4 (0x10U << ADC_SQR1_SQ16_Pos) /*!< 0x00080000 */
+
+#define ADC_SQR1_L_Pos (20U)
+#define ADC_SQR1_L_Msk (0xFU << ADC_SQR1_L_Pos) /*!< 0x00F00000 */
+#define ADC_SQR1_L ADC_SQR1_L_Msk /*!< ADC group regular sequencer scan length */
+#define ADC_SQR1_L_0 (0x1U << ADC_SQR1_L_Pos) /*!< 0x00100000 */
+#define ADC_SQR1_L_1 (0x2U << ADC_SQR1_L_Pos) /*!< 0x00200000 */
+#define ADC_SQR1_L_2 (0x4U << ADC_SQR1_L_Pos) /*!< 0x00400000 */
+#define ADC_SQR1_L_3 (0x8U << ADC_SQR1_L_Pos) /*!< 0x00800000 */
+
+/******************* Bit definition for ADC_SQR2 register *******************/
+#define ADC_SQR2_SQ7_Pos (0U)
+#define ADC_SQR2_SQ7_Msk (0x1FU << ADC_SQR2_SQ7_Pos) /*!< 0x0000001F */
+#define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk /*!< ADC group regular sequencer rank 7 */
+#define ADC_SQR2_SQ7_0 (0x01U << ADC_SQR2_SQ7_Pos) /*!< 0x00000001 */
+#define ADC_SQR2_SQ7_1 (0x02U << ADC_SQR2_SQ7_Pos) /*!< 0x00000002 */
+#define ADC_SQR2_SQ7_2 (0x04U << ADC_SQR2_SQ7_Pos) /*!< 0x00000004 */
+#define ADC_SQR2_SQ7_3 (0x08U << ADC_SQR2_SQ7_Pos) /*!< 0x00000008 */
+#define ADC_SQR2_SQ7_4 (0x10U << ADC_SQR2_SQ7_Pos) /*!< 0x00000010 */
+
+#define ADC_SQR2_SQ8_Pos (5U)
+#define ADC_SQR2_SQ8_Msk (0x1FU << ADC_SQR2_SQ8_Pos) /*!< 0x000003E0 */
+#define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk /*!< ADC group regular sequencer rank 8 */
+#define ADC_SQR2_SQ8_0 (0x01U << ADC_SQR2_SQ8_Pos) /*!< 0x00000020 */
+#define ADC_SQR2_SQ8_1 (0x02U << ADC_SQR2_SQ8_Pos) /*!< 0x00000040 */
+#define ADC_SQR2_SQ8_2 (0x04U << ADC_SQR2_SQ8_Pos) /*!< 0x00000080 */
+#define ADC_SQR2_SQ8_3 (0x08U << ADC_SQR2_SQ8_Pos) /*!< 0x00000100 */
+#define ADC_SQR2_SQ8_4 (0x10U << ADC_SQR2_SQ8_Pos) /*!< 0x00000200 */
+
+#define ADC_SQR2_SQ9_Pos (10U)
+#define ADC_SQR2_SQ9_Msk (0x1FU << ADC_SQR2_SQ9_Pos) /*!< 0x00007C00 */
+#define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk /*!< ADC group regular sequencer rank 9 */
+#define ADC_SQR2_SQ9_0 (0x01U << ADC_SQR2_SQ9_Pos) /*!< 0x00000400 */
+#define ADC_SQR2_SQ9_1 (0x02U << ADC_SQR2_SQ9_Pos) /*!< 0x00000800 */
+#define ADC_SQR2_SQ9_2 (0x04U << ADC_SQR2_SQ9_Pos) /*!< 0x00001000 */
+#define ADC_SQR2_SQ9_3 (0x08U << ADC_SQR2_SQ9_Pos) /*!< 0x00002000 */
+#define ADC_SQR2_SQ9_4 (0x10U << ADC_SQR2_SQ9_Pos) /*!< 0x00004000 */
+
+#define ADC_SQR2_SQ10_Pos (15U)
+#define ADC_SQR2_SQ10_Msk (0x1FU << ADC_SQR2_SQ10_Pos) /*!< 0x000F8000 */
+#define ADC_SQR2_SQ10 ADC_SQR2_SQ10_Msk /*!< ADC group regular sequencer rank 10 */
+#define ADC_SQR2_SQ10_0 (0x01U << ADC_SQR2_SQ10_Pos) /*!< 0x00008000 */
+#define ADC_SQR2_SQ10_1 (0x02U << ADC_SQR2_SQ10_Pos) /*!< 0x00010000 */
+#define ADC_SQR2_SQ10_2 (0x04U << ADC_SQR2_SQ10_Pos) /*!< 0x00020000 */
+#define ADC_SQR2_SQ10_3 (0x08U << ADC_SQR2_SQ10_Pos) /*!< 0x00040000 */
+#define ADC_SQR2_SQ10_4 (0x10U << ADC_SQR2_SQ10_Pos) /*!< 0x00080000 */
+
+#define ADC_SQR2_SQ11_Pos (20U)
+#define ADC_SQR2_SQ11_Msk (0x1FU << ADC_SQR2_SQ11_Pos) /*!< 0x01F00000 */
+#define ADC_SQR2_SQ11 ADC_SQR2_SQ11_Msk /*!< ADC group regular sequencer rank 1 */
+#define ADC_SQR2_SQ11_0 (0x01U << ADC_SQR2_SQ11_Pos) /*!< 0x00100000 */
+#define ADC_SQR2_SQ11_1 (0x02U << ADC_SQR2_SQ11_Pos) /*!< 0x00200000 */
+#define ADC_SQR2_SQ11_2 (0x04U << ADC_SQR2_SQ11_Pos) /*!< 0x00400000 */
+#define ADC_SQR2_SQ11_3 (0x08U << ADC_SQR2_SQ11_Pos) /*!< 0x00800000 */
+#define ADC_SQR2_SQ11_4 (0x10U << ADC_SQR2_SQ11_Pos) /*!< 0x01000000 */
+
+#define ADC_SQR2_SQ12_Pos (25U)
+#define ADC_SQR2_SQ12_Msk (0x1FU << ADC_SQR2_SQ12_Pos) /*!< 0x3E000000 */
+#define ADC_SQR2_SQ12 ADC_SQR2_SQ12_Msk /*!< ADC group regular sequencer rank 12 */
+#define ADC_SQR2_SQ12_0 (0x01U << ADC_SQR2_SQ12_Pos) /*!< 0x02000000 */
+#define ADC_SQR2_SQ12_1 (0x02U << ADC_SQR2_SQ12_Pos) /*!< 0x04000000 */
+#define ADC_SQR2_SQ12_2 (0x04U << ADC_SQR2_SQ12_Pos) /*!< 0x08000000 */
+#define ADC_SQR2_SQ12_3 (0x08U << ADC_SQR2_SQ12_Pos) /*!< 0x10000000 */
+#define ADC_SQR2_SQ12_4 (0x10U << ADC_SQR2_SQ12_Pos) /*!< 0x20000000 */
+
+/******************* Bit definition for ADC_SQR3 register *******************/
+#define ADC_SQR3_SQ1_Pos (0U)
+#define ADC_SQR3_SQ1_Msk (0x1FU << ADC_SQR3_SQ1_Pos) /*!< 0x0000001F */
+#define ADC_SQR3_SQ1 ADC_SQR3_SQ1_Msk /*!< ADC group regular sequencer rank 1 */
+#define ADC_SQR3_SQ1_0 (0x01U << ADC_SQR3_SQ1_Pos) /*!< 0x00000001 */
+#define ADC_SQR3_SQ1_1 (0x02U << ADC_SQR3_SQ1_Pos) /*!< 0x00000002 */
+#define ADC_SQR3_SQ1_2 (0x04U << ADC_SQR3_SQ1_Pos) /*!< 0x00000004 */
+#define ADC_SQR3_SQ1_3 (0x08U << ADC_SQR3_SQ1_Pos) /*!< 0x00000008 */
+#define ADC_SQR3_SQ1_4 (0x10U << ADC_SQR3_SQ1_Pos) /*!< 0x00000010 */
+
+#define ADC_SQR3_SQ2_Pos (5U)
+#define ADC_SQR3_SQ2_Msk (0x1FU << ADC_SQR3_SQ2_Pos) /*!< 0x000003E0 */
+#define ADC_SQR3_SQ2 ADC_SQR3_SQ2_Msk /*!< ADC group regular sequencer rank 2 */
+#define ADC_SQR3_SQ2_0 (0x01U << ADC_SQR3_SQ2_Pos) /*!< 0x00000020 */
+#define ADC_SQR3_SQ2_1 (0x02U << ADC_SQR3_SQ2_Pos) /*!< 0x00000040 */
+#define ADC_SQR3_SQ2_2 (0x04U << ADC_SQR3_SQ2_Pos) /*!< 0x00000080 */
+#define ADC_SQR3_SQ2_3 (0x08U << ADC_SQR3_SQ2_Pos) /*!< 0x00000100 */
+#define ADC_SQR3_SQ2_4 (0x10U << ADC_SQR3_SQ2_Pos) /*!< 0x00000200 */
+
+#define ADC_SQR3_SQ3_Pos (10U)
+#define ADC_SQR3_SQ3_Msk (0x1FU << ADC_SQR3_SQ3_Pos) /*!< 0x00007C00 */
+#define ADC_SQR3_SQ3 ADC_SQR3_SQ3_Msk /*!< ADC group regular sequencer rank 3 */
+#define ADC_SQR3_SQ3_0 (0x01U << ADC_SQR3_SQ3_Pos) /*!< 0x00000400 */
+#define ADC_SQR3_SQ3_1 (0x02U << ADC_SQR3_SQ3_Pos) /*!< 0x00000800 */
+#define ADC_SQR3_SQ3_2 (0x04U << ADC_SQR3_SQ3_Pos) /*!< 0x00001000 */
+#define ADC_SQR3_SQ3_3 (0x08U << ADC_SQR3_SQ3_Pos) /*!< 0x00002000 */
+#define ADC_SQR3_SQ3_4 (0x10U << ADC_SQR3_SQ3_Pos) /*!< 0x00004000 */
+
+#define ADC_SQR3_SQ4_Pos (15U)
+#define ADC_SQR3_SQ4_Msk (0x1FU << ADC_SQR3_SQ4_Pos) /*!< 0x000F8000 */
+#define ADC_SQR3_SQ4 ADC_SQR3_SQ4_Msk /*!< ADC group regular sequencer rank 4 */
+#define ADC_SQR3_SQ4_0 (0x01U << ADC_SQR3_SQ4_Pos) /*!< 0x00008000 */
+#define ADC_SQR3_SQ4_1 (0x02U << ADC_SQR3_SQ4_Pos) /*!< 0x00010000 */
+#define ADC_SQR3_SQ4_2 (0x04U << ADC_SQR3_SQ4_Pos) /*!< 0x00020000 */
+#define ADC_SQR3_SQ4_3 (0x08U << ADC_SQR3_SQ4_Pos) /*!< 0x00040000 */
+#define ADC_SQR3_SQ4_4 (0x10U << ADC_SQR3_SQ4_Pos) /*!< 0x00080000 */
+
+#define ADC_SQR3_SQ5_Pos (20U)
+#define ADC_SQR3_SQ5_Msk (0x1FU << ADC_SQR3_SQ5_Pos) /*!< 0x01F00000 */
+#define ADC_SQR3_SQ5 ADC_SQR3_SQ5_Msk /*!< ADC group regular sequencer rank 5 */
+#define ADC_SQR3_SQ5_0 (0x01U << ADC_SQR3_SQ5_Pos) /*!< 0x00100000 */
+#define ADC_SQR3_SQ5_1 (0x02U << ADC_SQR3_SQ5_Pos) /*!< 0x00200000 */
+#define ADC_SQR3_SQ5_2 (0x04U << ADC_SQR3_SQ5_Pos) /*!< 0x00400000 */
+#define ADC_SQR3_SQ5_3 (0x08U << ADC_SQR3_SQ5_Pos) /*!< 0x00800000 */
+#define ADC_SQR3_SQ5_4 (0x10U << ADC_SQR3_SQ5_Pos) /*!< 0x01000000 */
+
+#define ADC_SQR3_SQ6_Pos (25U)
+#define ADC_SQR3_SQ6_Msk (0x1FU << ADC_SQR3_SQ6_Pos) /*!< 0x3E000000 */
+#define ADC_SQR3_SQ6 ADC_SQR3_SQ6_Msk /*!< ADC group regular sequencer rank 6 */
+#define ADC_SQR3_SQ6_0 (0x01U << ADC_SQR3_SQ6_Pos) /*!< 0x02000000 */
+#define ADC_SQR3_SQ6_1 (0x02U << ADC_SQR3_SQ6_Pos) /*!< 0x04000000 */
+#define ADC_SQR3_SQ6_2 (0x04U << ADC_SQR3_SQ6_Pos) /*!< 0x08000000 */
+#define ADC_SQR3_SQ6_3 (0x08U << ADC_SQR3_SQ6_Pos) /*!< 0x10000000 */
+#define ADC_SQR3_SQ6_4 (0x10U << ADC_SQR3_SQ6_Pos) /*!< 0x20000000 */
+
+/******************* Bit definition for ADC_JSQR register *******************/
+#define ADC_JSQR_JSQ1_Pos (0U)
+#define ADC_JSQR_JSQ1_Msk (0x1FU << ADC_JSQR_JSQ1_Pos) /*!< 0x0000001F */
+#define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!< ADC group injected sequencer rank 1 */
+#define ADC_JSQR_JSQ1_0 (0x01U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000001 */
+#define ADC_JSQR_JSQ1_1 (0x02U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000002 */
+#define ADC_JSQR_JSQ1_2 (0x04U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000004 */
+#define ADC_JSQR_JSQ1_3 (0x08U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000008 */
+#define ADC_JSQR_JSQ1_4 (0x10U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000010 */
+
+#define ADC_JSQR_JSQ2_Pos (5U)
+#define ADC_JSQR_JSQ2_Msk (0x1FU << ADC_JSQR_JSQ2_Pos) /*!< 0x000003E0 */
+#define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!< ADC group injected sequencer rank 2 */
+#define ADC_JSQR_JSQ2_0 (0x01U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000020 */
+#define ADC_JSQR_JSQ2_1 (0x02U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000040 */
+#define ADC_JSQR_JSQ2_2 (0x04U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000080 */
+#define ADC_JSQR_JSQ2_3 (0x08U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000100 */
+#define ADC_JSQR_JSQ2_4 (0x10U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000200 */
+
+#define ADC_JSQR_JSQ3_Pos (10U)
+#define ADC_JSQR_JSQ3_Msk (0x1FU << ADC_JSQR_JSQ3_Pos) /*!< 0x00007C00 */
+#define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!< ADC group injected sequencer rank 3 */
+#define ADC_JSQR_JSQ3_0 (0x01U << ADC_JSQR_JSQ3_Pos) /*!< 0x00000400 */
+#define ADC_JSQR_JSQ3_1 (0x02U << ADC_JSQR_JSQ3_Pos) /*!< 0x00000800 */
+#define ADC_JSQR_JSQ3_2 (0x04U << ADC_JSQR_JSQ3_Pos) /*!< 0x00001000 */
+#define ADC_JSQR_JSQ3_3 (0x08U << ADC_JSQR_JSQ3_Pos) /*!< 0x00002000 */
+#define ADC_JSQR_JSQ3_4 (0x10U << ADC_JSQR_JSQ3_Pos) /*!< 0x00004000 */
+
+#define ADC_JSQR_JSQ4_Pos (15U)
+#define ADC_JSQR_JSQ4_Msk (0x1FU << ADC_JSQR_JSQ4_Pos) /*!< 0x000F8000 */
+#define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!< ADC group injected sequencer rank 4 */
+#define ADC_JSQR_JSQ4_0 (0x01U << ADC_JSQR_JSQ4_Pos) /*!< 0x00008000 */
+#define ADC_JSQR_JSQ4_1 (0x02U << ADC_JSQR_JSQ4_Pos) /*!< 0x00010000 */
+#define ADC_JSQR_JSQ4_2 (0x04U << ADC_JSQR_JSQ4_Pos) /*!< 0x00020000 */
+#define ADC_JSQR_JSQ4_3 (0x08U << ADC_JSQR_JSQ4_Pos) /*!< 0x00040000 */
+#define ADC_JSQR_JSQ4_4 (0x10U << ADC_JSQR_JSQ4_Pos) /*!< 0x00080000 */
+
+#define ADC_JSQR_JL_Pos (20U)
+#define ADC_JSQR_JL_Msk (0x3U << ADC_JSQR_JL_Pos) /*!< 0x00300000 */
+#define ADC_JSQR_JL ADC_JSQR_JL_Msk /*!< ADC group injected sequencer scan length */
+#define ADC_JSQR_JL_0 (0x1U << ADC_JSQR_JL_Pos) /*!< 0x00100000 */
+#define ADC_JSQR_JL_1 (0x2U << ADC_JSQR_JL_Pos) /*!< 0x00200000 */
+
+/******************* Bit definition for ADC_JDR1 register *******************/
+#define ADC_JDR1_JDATA_Pos (0U)
+#define ADC_JDR1_JDATA_Msk (0xFFFFU << ADC_JDR1_JDATA_Pos) /*!< 0x0000FFFF */
+#define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!< ADC group injected sequencer rank 1 conversion data */
+
+/******************* Bit definition for ADC_JDR2 register *******************/
+#define ADC_JDR2_JDATA_Pos (0U)
+#define ADC_JDR2_JDATA_Msk (0xFFFFU << ADC_JDR2_JDATA_Pos) /*!< 0x0000FFFF */
+#define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!< ADC group injected sequencer rank 2 conversion data */
+
+/******************* Bit definition for ADC_JDR3 register *******************/
+#define ADC_JDR3_JDATA_Pos (0U)
+#define ADC_JDR3_JDATA_Msk (0xFFFFU << ADC_JDR3_JDATA_Pos) /*!< 0x0000FFFF */
+#define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!< ADC group injected sequencer rank 3 conversion data */
+
+/******************* Bit definition for ADC_JDR4 register *******************/
+#define ADC_JDR4_JDATA_Pos (0U)
+#define ADC_JDR4_JDATA_Msk (0xFFFFU << ADC_JDR4_JDATA_Pos) /*!< 0x0000FFFF */
+#define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!< ADC group injected sequencer rank 4 conversion data */
+
+/******************** Bit definition for ADC_DR register ********************/
+#define ADC_DR_DATA_Pos (0U)
+#define ADC_DR_DATA_Msk (0xFFFFU << ADC_DR_DATA_Pos) /*!< 0x0000FFFF */
+#define ADC_DR_DATA ADC_DR_DATA_Msk /*!< ADC group regular conversion data */
+#define ADC_DR_ADC2DATA_Pos (16U)
+#define ADC_DR_ADC2DATA_Msk (0xFFFFU << ADC_DR_ADC2DATA_Pos) /*!< 0xFFFF0000 */
+#define ADC_DR_ADC2DATA ADC_DR_ADC2DATA_Msk /*!< ADC group regular conversion data for ADC slave, in multimode */
+/******************************************************************************/
+/* */
+/* Digital to Analog Converter */
+/* */
+/******************************************************************************/
+
+/******************** Bit definition for DAC_CR register ********************/
+#define DAC_CR_EN1_Pos (0U)
+#define DAC_CR_EN1_Msk (0x1U << DAC_CR_EN1_Pos) /*!< 0x00000001 */
+#define DAC_CR_EN1 DAC_CR_EN1_Msk /*!< DAC channel1 enable */
+#define DAC_CR_BOFF1_Pos (1U)
+#define DAC_CR_BOFF1_Msk (0x1U << DAC_CR_BOFF1_Pos) /*!< 0x00000002 */
+#define DAC_CR_BOFF1 DAC_CR_BOFF1_Msk /*!< DAC channel1 output buffer disable */
+#define DAC_CR_TEN1_Pos (2U)
+#define DAC_CR_TEN1_Msk (0x1U << DAC_CR_TEN1_Pos) /*!< 0x00000004 */
+#define DAC_CR_TEN1 DAC_CR_TEN1_Msk /*!< DAC channel1 Trigger enable */
+
+#define DAC_CR_TSEL1_Pos (3U)
+#define DAC_CR_TSEL1_Msk (0x7U << DAC_CR_TSEL1_Pos) /*!< 0x00000038 */
+#define DAC_CR_TSEL1 DAC_CR_TSEL1_Msk /*!< TSEL1[2:0] (DAC channel1 Trigger selection) */
+#define DAC_CR_TSEL1_0 (0x1U << DAC_CR_TSEL1_Pos) /*!< 0x00000008 */
+#define DAC_CR_TSEL1_1 (0x2U << DAC_CR_TSEL1_Pos) /*!< 0x00000010 */
+#define DAC_CR_TSEL1_2 (0x4U << DAC_CR_TSEL1_Pos) /*!< 0x00000020 */
+
+#define DAC_CR_WAVE1_Pos (6U)
+#define DAC_CR_WAVE1_Msk (0x3U << DAC_CR_WAVE1_Pos) /*!< 0x000000C0 */
+#define DAC_CR_WAVE1 DAC_CR_WAVE1_Msk /*!< WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
+#define DAC_CR_WAVE1_0 (0x1U << DAC_CR_WAVE1_Pos) /*!< 0x00000040 */
+#define DAC_CR_WAVE1_1 (0x2U << DAC_CR_WAVE1_Pos) /*!< 0x00000080 */
+
+#define DAC_CR_MAMP1_Pos (8U)
+#define DAC_CR_MAMP1_Msk (0xFU << DAC_CR_MAMP1_Pos) /*!< 0x00000F00 */
+#define DAC_CR_MAMP1 DAC_CR_MAMP1_Msk /*!< MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
+#define DAC_CR_MAMP1_0 (0x1U << DAC_CR_MAMP1_Pos) /*!< 0x00000100 */
+#define DAC_CR_MAMP1_1 (0x2U << DAC_CR_MAMP1_Pos) /*!< 0x00000200 */
+#define DAC_CR_MAMP1_2 (0x4U << DAC_CR_MAMP1_Pos) /*!< 0x00000400 */
+#define DAC_CR_MAMP1_3 (0x8U << DAC_CR_MAMP1_Pos) /*!< 0x00000800 */
+
+#define DAC_CR_DMAEN1_Pos (12U)
+#define DAC_CR_DMAEN1_Msk (0x1U << DAC_CR_DMAEN1_Pos) /*!< 0x00001000 */
+#define DAC_CR_DMAEN1 DAC_CR_DMAEN1_Msk /*!< DAC channel1 DMA enable */
+#define DAC_CR_EN2_Pos (16U)
+#define DAC_CR_EN2_Msk (0x1U << DAC_CR_EN2_Pos) /*!< 0x00010000 */
+#define DAC_CR_EN2 DAC_CR_EN2_Msk /*!< DAC channel2 enable */
+#define DAC_CR_BOFF2_Pos (17U)
+#define DAC_CR_BOFF2_Msk (0x1U << DAC_CR_BOFF2_Pos) /*!< 0x00020000 */
+#define DAC_CR_BOFF2 DAC_CR_BOFF2_Msk /*!< DAC channel2 output buffer disable */
+#define DAC_CR_TEN2_Pos (18U)
+#define DAC_CR_TEN2_Msk (0x1U << DAC_CR_TEN2_Pos) /*!< 0x00040000 */
+#define DAC_CR_TEN2 DAC_CR_TEN2_Msk /*!< DAC channel2 Trigger enable */
+
+#define DAC_CR_TSEL2_Pos (19U)
+#define DAC_CR_TSEL2_Msk (0x7U << DAC_CR_TSEL2_Pos) /*!< 0x00380000 */
+#define DAC_CR_TSEL2 DAC_CR_TSEL2_Msk /*!< TSEL2[2:0] (DAC channel2 Trigger selection) */
+#define DAC_CR_TSEL2_0 (0x1U << DAC_CR_TSEL2_Pos) /*!< 0x00080000 */
+#define DAC_CR_TSEL2_1 (0x2U << DAC_CR_TSEL2_Pos) /*!< 0x00100000 */
+#define DAC_CR_TSEL2_2 (0x4U << DAC_CR_TSEL2_Pos) /*!< 0x00200000 */
+
+#define DAC_CR_WAVE2_Pos (22U)
+#define DAC_CR_WAVE2_Msk (0x3U << DAC_CR_WAVE2_Pos) /*!< 0x00C00000 */
+#define DAC_CR_WAVE2 DAC_CR_WAVE2_Msk /*!< WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
+#define DAC_CR_WAVE2_0 (0x1U << DAC_CR_WAVE2_Pos) /*!< 0x00400000 */
+#define DAC_CR_WAVE2_1 (0x2U << DAC_CR_WAVE2_Pos) /*!< 0x00800000 */
+
+#define DAC_CR_MAMP2_Pos (24U)
+#define DAC_CR_MAMP2_Msk (0xFU << DAC_CR_MAMP2_Pos) /*!< 0x0F000000 */
+#define DAC_CR_MAMP2 DAC_CR_MAMP2_Msk /*!< MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
+#define DAC_CR_MAMP2_0 (0x1U << DAC_CR_MAMP2_Pos) /*!< 0x01000000 */
+#define DAC_CR_MAMP2_1 (0x2U << DAC_CR_MAMP2_Pos) /*!< 0x02000000 */
+#define DAC_CR_MAMP2_2 (0x4U << DAC_CR_MAMP2_Pos) /*!< 0x04000000 */
+#define DAC_CR_MAMP2_3 (0x8U << DAC_CR_MAMP2_Pos) /*!< 0x08000000 */
+
+#define DAC_CR_DMAEN2_Pos (28U)
+#define DAC_CR_DMAEN2_Msk (0x1U << DAC_CR_DMAEN2_Pos) /*!< 0x10000000 */
+#define DAC_CR_DMAEN2 DAC_CR_DMAEN2_Msk /*!< DAC channel2 DMA enabled */
+
+
+/***************** Bit definition for DAC_SWTRIGR register ******************/
+#define DAC_SWTRIGR_SWTRIG1_Pos (0U)
+#define DAC_SWTRIGR_SWTRIG1_Msk (0x1U << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */
+#define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /*!< DAC channel1 software trigger */
+#define DAC_SWTRIGR_SWTRIG2_Pos (1U)
+#define DAC_SWTRIGR_SWTRIG2_Msk (0x1U << DAC_SWTRIGR_SWTRIG2_Pos) /*!< 0x00000002 */
+#define DAC_SWTRIGR_SWTRIG2 DAC_SWTRIGR_SWTRIG2_Msk /*!< DAC channel2 software trigger */
+
+/***************** Bit definition for DAC_DHR12R1 register ******************/
+#define DAC_DHR12R1_DACC1DHR_Pos (0U)
+#define DAC_DHR12R1_DACC1DHR_Msk (0xFFFU << DAC_DHR12R1_DACC1DHR_Pos) /*!< 0x00000FFF */
+#define DAC_DHR12R1_DACC1DHR DAC_DHR12R1_DACC1DHR_Msk /*!< DAC channel1 12-bit Right aligned data */
+
+/***************** Bit definition for DAC_DHR12L1 register ******************/
+#define DAC_DHR12L1_DACC1DHR_Pos (4U)
+#define DAC_DHR12L1_DACC1DHR_Msk (0xFFFU << DAC_DHR12L1_DACC1DHR_Pos) /*!< 0x0000FFF0 */
+#define DAC_DHR12L1_DACC1DHR DAC_DHR12L1_DACC1DHR_Msk /*!< DAC channel1 12-bit Left aligned data */
+
+/****************** Bit definition for DAC_DHR8R1 register ******************/
+#define DAC_DHR8R1_DACC1DHR_Pos (0U)
+#define DAC_DHR8R1_DACC1DHR_Msk (0xFFU << DAC_DHR8R1_DACC1DHR_Pos) /*!< 0x000000FF */
+#define DAC_DHR8R1_DACC1DHR DAC_DHR8R1_DACC1DHR_Msk /*!< DAC channel1 8-bit Right aligned data */
+
+/***************** Bit definition for DAC_DHR12R2 register ******************/
+#define DAC_DHR12R2_DACC2DHR_Pos (0U)
+#define DAC_DHR12R2_DACC2DHR_Msk (0xFFFU << DAC_DHR12R2_DACC2DHR_Pos) /*!< 0x00000FFF */
+#define DAC_DHR12R2_DACC2DHR DAC_DHR12R2_DACC2DHR_Msk /*!< DAC channel2 12-bit Right aligned data */
+
+/***************** Bit definition for DAC_DHR12L2 register ******************/
+#define DAC_DHR12L2_DACC2DHR_Pos (4U)
+#define DAC_DHR12L2_DACC2DHR_Msk (0xFFFU << DAC_DHR12L2_DACC2DHR_Pos) /*!< 0x0000FFF0 */
+#define DAC_DHR12L2_DACC2DHR DAC_DHR12L2_DACC2DHR_Msk /*!< DAC channel2 12-bit Left aligned data */
+
+/****************** Bit definition for DAC_DHR8R2 register ******************/
+#define DAC_DHR8R2_DACC2DHR_Pos (0U)
+#define DAC_DHR8R2_DACC2DHR_Msk (0xFFU << DAC_DHR8R2_DACC2DHR_Pos) /*!< 0x000000FF */
+#define DAC_DHR8R2_DACC2DHR DAC_DHR8R2_DACC2DHR_Msk /*!< DAC channel2 8-bit Right aligned data */
+
+/***************** Bit definition for DAC_DHR12RD register ******************/
+#define DAC_DHR12RD_DACC1DHR_Pos (0U)
+#define DAC_DHR12RD_DACC1DHR_Msk (0xFFFU << DAC_DHR12RD_DACC1DHR_Pos) /*!< 0x00000FFF */
+#define DAC_DHR12RD_DACC1DHR DAC_DHR12RD_DACC1DHR_Msk /*!< DAC channel1 12-bit Right aligned data */
+#define DAC_DHR12RD_DACC2DHR_Pos (16U)
+#define DAC_DHR12RD_DACC2DHR_Msk (0xFFFU << DAC_DHR12RD_DACC2DHR_Pos) /*!< 0x0FFF0000 */
+#define DAC_DHR12RD_DACC2DHR DAC_DHR12RD_DACC2DHR_Msk /*!< DAC channel2 12-bit Right aligned data */
+
+/***************** Bit definition for DAC_DHR12LD register ******************/
+#define DAC_DHR12LD_DACC1DHR_Pos (4U)
+#define DAC_DHR12LD_DACC1DHR_Msk (0xFFFU << DAC_DHR12LD_DACC1DHR_Pos) /*!< 0x0000FFF0 */
+#define DAC_DHR12LD_DACC1DHR DAC_DHR12LD_DACC1DHR_Msk /*!< DAC channel1 12-bit Left aligned data */
+#define DAC_DHR12LD_DACC2DHR_Pos (20U)
+#define DAC_DHR12LD_DACC2DHR_Msk (0xFFFU << DAC_DHR12LD_DACC2DHR_Pos) /*!< 0xFFF00000 */
+#define DAC_DHR12LD_DACC2DHR DAC_DHR12LD_DACC2DHR_Msk /*!< DAC channel2 12-bit Left aligned data */
+
+/****************** Bit definition for DAC_DHR8RD register ******************/
+#define DAC_DHR8RD_DACC1DHR_Pos (0U)
+#define DAC_DHR8RD_DACC1DHR_Msk (0xFFU << DAC_DHR8RD_DACC1DHR_Pos) /*!< 0x000000FF */
+#define DAC_DHR8RD_DACC1DHR DAC_DHR8RD_DACC1DHR_Msk /*!< DAC channel1 8-bit Right aligned data */
+#define DAC_DHR8RD_DACC2DHR_Pos (8U)
+#define DAC_DHR8RD_DACC2DHR_Msk (0xFFU << DAC_DHR8RD_DACC2DHR_Pos) /*!< 0x0000FF00 */
+#define DAC_DHR8RD_DACC2DHR DAC_DHR8RD_DACC2DHR_Msk /*!< DAC channel2 8-bit Right aligned data */
+
+/******************* Bit definition for DAC_DOR1 register *******************/
+#define DAC_DOR1_DACC1DOR_Pos (0U)
+#define DAC_DOR1_DACC1DOR_Msk (0xFFFU << DAC_DOR1_DACC1DOR_Pos) /*!< 0x00000FFF */
+#define DAC_DOR1_DACC1DOR DAC_DOR1_DACC1DOR_Msk /*!< DAC channel1 data output */
+
+/******************* Bit definition for DAC_DOR2 register *******************/
+#define DAC_DOR2_DACC2DOR_Pos (0U)
+#define DAC_DOR2_DACC2DOR_Msk (0xFFFU << DAC_DOR2_DACC2DOR_Pos) /*!< 0x00000FFF */
+#define DAC_DOR2_DACC2DOR DAC_DOR2_DACC2DOR_Msk /*!< DAC channel2 data output */
+
+
+
+/*****************************************************************************/
+/* */
+/* Timers (TIM) */
+/* */
+/*****************************************************************************/
+/******************* Bit definition for TIM_CR1 register *******************/
+#define TIM_CR1_CEN_Pos (0U)
+#define TIM_CR1_CEN_Msk (0x1U << TIM_CR1_CEN_Pos) /*!< 0x00000001 */
+#define TIM_CR1_CEN TIM_CR1_CEN_Msk /*!<Counter enable */
+#define TIM_CR1_UDIS_Pos (1U)
+#define TIM_CR1_UDIS_Msk (0x1U << TIM_CR1_UDIS_Pos) /*!< 0x00000002 */
+#define TIM_CR1_UDIS TIM_CR1_UDIS_Msk /*!<Update disable */
+#define TIM_CR1_URS_Pos (2U)
+#define TIM_CR1_URS_Msk (0x1U << TIM_CR1_URS_Pos) /*!< 0x00000004 */
+#define TIM_CR1_URS TIM_CR1_URS_Msk /*!<Update request source */
+#define TIM_CR1_OPM_Pos (3U)
+#define TIM_CR1_OPM_Msk (0x1U << TIM_CR1_OPM_Pos) /*!< 0x00000008 */
+#define TIM_CR1_OPM TIM_CR1_OPM_Msk /*!<One pulse mode */
+#define TIM_CR1_DIR_Pos (4U)
+#define TIM_CR1_DIR_Msk (0x1U << TIM_CR1_DIR_Pos) /*!< 0x00000010 */
+#define TIM_CR1_DIR TIM_CR1_DIR_Msk /*!<Direction */
+
+#define TIM_CR1_CMS_Pos (5U)
+#define TIM_CR1_CMS_Msk (0x3U << TIM_CR1_CMS_Pos) /*!< 0x00000060 */
+#define TIM_CR1_CMS TIM_CR1_CMS_Msk /*!<CMS[1:0] bits (Center-aligned mode selection) */
+#define TIM_CR1_CMS_0 (0x1U << TIM_CR1_CMS_Pos) /*!< 0x00000020 */
+#define TIM_CR1_CMS_1 (0x2U << TIM_CR1_CMS_Pos) /*!< 0x00000040 */
+
+#define TIM_CR1_ARPE_Pos (7U)
+#define TIM_CR1_ARPE_Msk (0x1U << TIM_CR1_ARPE_Pos) /*!< 0x00000080 */
+#define TIM_CR1_ARPE TIM_CR1_ARPE_Msk /*!<Auto-reload preload enable */
+
+#define TIM_CR1_CKD_Pos (8U)
+#define TIM_CR1_CKD_Msk (0x3U << TIM_CR1_CKD_Pos) /*!< 0x00000300 */
+#define TIM_CR1_CKD TIM_CR1_CKD_Msk /*!<CKD[1:0] bits (clock division) */
+#define TIM_CR1_CKD_0 (0x1U << TIM_CR1_CKD_Pos) /*!< 0x00000100 */
+#define TIM_CR1_CKD_1 (0x2U << TIM_CR1_CKD_Pos) /*!< 0x00000200 */
+
+/******************* Bit definition for TIM_CR2 register *******************/
+#define TIM_CR2_CCPC_Pos (0U)
+#define TIM_CR2_CCPC_Msk (0x1U << TIM_CR2_CCPC_Pos) /*!< 0x00000001 */
+#define TIM_CR2_CCPC TIM_CR2_CCPC_Msk /*!<Capture/Compare Preloaded Control */
+#define TIM_CR2_CCUS_Pos (2U)
+#define TIM_CR2_CCUS_Msk (0x1U << TIM_CR2_CCUS_Pos) /*!< 0x00000004 */
+#define TIM_CR2_CCUS TIM_CR2_CCUS_Msk /*!<Capture/Compare Control Update Selection */
+#define TIM_CR2_CCDS_Pos (3U)
+#define TIM_CR2_CCDS_Msk (0x1U << TIM_CR2_CCDS_Pos) /*!< 0x00000008 */
+#define TIM_CR2_CCDS TIM_CR2_CCDS_Msk /*!<Capture/Compare DMA Selection */
+
+#define TIM_CR2_MMS_Pos (4U)
+#define TIM_CR2_MMS_Msk (0x7U << TIM_CR2_MMS_Pos) /*!< 0x00000070 */
+#define TIM_CR2_MMS TIM_CR2_MMS_Msk /*!<MMS[2:0] bits (Master Mode Selection) */
+#define TIM_CR2_MMS_0 (0x1U << TIM_CR2_MMS_Pos) /*!< 0x00000010 */
+#define TIM_CR2_MMS_1 (0x2U << TIM_CR2_MMS_Pos) /*!< 0x00000020 */
+#define TIM_CR2_MMS_2 (0x4U << TIM_CR2_MMS_Pos) /*!< 0x00000040 */
+
+#define TIM_CR2_TI1S_Pos (7U)
+#define TIM_CR2_TI1S_Msk (0x1U << TIM_CR2_TI1S_Pos) /*!< 0x00000080 */
+#define TIM_CR2_TI1S TIM_CR2_TI1S_Msk /*!<TI1 Selection */
+#define TIM_CR2_OIS1_Pos (8U)
+#define TIM_CR2_OIS1_Msk (0x1U << TIM_CR2_OIS1_Pos) /*!< 0x00000100 */
+#define TIM_CR2_OIS1 TIM_CR2_OIS1_Msk /*!<Output Idle state 1 (OC1 output) */
+#define TIM_CR2_OIS1N_Pos (9U)
+#define TIM_CR2_OIS1N_Msk (0x1U << TIM_CR2_OIS1N_Pos) /*!< 0x00000200 */
+#define TIM_CR2_OIS1N TIM_CR2_OIS1N_Msk /*!<Output Idle state 1 (OC1N output) */
+#define TIM_CR2_OIS2_Pos (10U)
+#define TIM_CR2_OIS2_Msk (0x1U << TIM_CR2_OIS2_Pos) /*!< 0x00000400 */
+#define TIM_CR2_OIS2 TIM_CR2_OIS2_Msk /*!<Output Idle state 2 (OC2 output) */
+#define TIM_CR2_OIS2N_Pos (11U)
+#define TIM_CR2_OIS2N_Msk (0x1U << TIM_CR2_OIS2N_Pos) /*!< 0x00000800 */
+#define TIM_CR2_OIS2N TIM_CR2_OIS2N_Msk /*!<Output Idle state 2 (OC2N output) */
+#define TIM_CR2_OIS3_Pos (12U)
+#define TIM_CR2_OIS3_Msk (0x1U << TIM_CR2_OIS3_Pos) /*!< 0x00001000 */
+#define TIM_CR2_OIS3 TIM_CR2_OIS3_Msk /*!<Output Idle state 3 (OC3 output) */
+#define TIM_CR2_OIS3N_Pos (13U)
+#define TIM_CR2_OIS3N_Msk (0x1U << TIM_CR2_OIS3N_Pos) /*!< 0x00002000 */
+#define TIM_CR2_OIS3N TIM_CR2_OIS3N_Msk /*!<Output Idle state 3 (OC3N output) */
+#define TIM_CR2_OIS4_Pos (14U)
+#define TIM_CR2_OIS4_Msk (0x1U << TIM_CR2_OIS4_Pos) /*!< 0x00004000 */
+#define TIM_CR2_OIS4 TIM_CR2_OIS4_Msk /*!<Output Idle state 4 (OC4 output) */
+
+/******************* Bit definition for TIM_SMCR register ******************/
+#define TIM_SMCR_SMS_Pos (0U)
+#define TIM_SMCR_SMS_Msk (0x7U << TIM_SMCR_SMS_Pos) /*!< 0x00000007 */
+#define TIM_SMCR_SMS TIM_SMCR_SMS_Msk /*!<SMS[2:0] bits (Slave mode selection) */
+#define TIM_SMCR_SMS_0 (0x1U << TIM_SMCR_SMS_Pos) /*!< 0x00000001 */
+#define TIM_SMCR_SMS_1 (0x2U << TIM_SMCR_SMS_Pos) /*!< 0x00000002 */
+#define TIM_SMCR_SMS_2 (0x4U << TIM_SMCR_SMS_Pos) /*!< 0x00000004 */
+
+#define TIM_SMCR_OCCS_Pos (3U)
+#define TIM_SMCR_OCCS_Msk (0x1U << TIM_SMCR_OCCS_Pos) /*!< 0x00000008 */
+#define TIM_SMCR_OCCS TIM_SMCR_OCCS_Msk /*!< OCREF clear selection */
+
+#define TIM_SMCR_TS_Pos (4U)
+#define TIM_SMCR_TS_Msk (0x7U << TIM_SMCR_TS_Pos) /*!< 0x00000070 */
+#define TIM_SMCR_TS TIM_SMCR_TS_Msk /*!<TS[2:0] bits (Trigger selection) */
+#define TIM_SMCR_TS_0 (0x1U << TIM_SMCR_TS_Pos) /*!< 0x00000010 */
+#define TIM_SMCR_TS_1 (0x2U << TIM_SMCR_TS_Pos) /*!< 0x00000020 */
+#define TIM_SMCR_TS_2 (0x4U << TIM_SMCR_TS_Pos) /*!< 0x00000040 */
+
+#define TIM_SMCR_MSM_Pos (7U)
+#define TIM_SMCR_MSM_Msk (0x1U << TIM_SMCR_MSM_Pos) /*!< 0x00000080 */
+#define TIM_SMCR_MSM TIM_SMCR_MSM_Msk /*!<Master/slave mode */
+
+#define TIM_SMCR_ETF_Pos (8U)
+#define TIM_SMCR_ETF_Msk (0xFU << TIM_SMCR_ETF_Pos) /*!< 0x00000F00 */
+#define TIM_SMCR_ETF TIM_SMCR_ETF_Msk /*!<ETF[3:0] bits (External trigger filter) */
+#define TIM_SMCR_ETF_0 (0x1U << TIM_SMCR_ETF_Pos) /*!< 0x00000100 */
+#define TIM_SMCR_ETF_1 (0x2U << TIM_SMCR_ETF_Pos) /*!< 0x00000200 */
+#define TIM_SMCR_ETF_2 (0x4U << TIM_SMCR_ETF_Pos) /*!< 0x00000400 */
+#define TIM_SMCR_ETF_3 (0x8U << TIM_SMCR_ETF_Pos) /*!< 0x00000800 */
+
+#define TIM_SMCR_ETPS_Pos (12U)
+#define TIM_SMCR_ETPS_Msk (0x3U << TIM_SMCR_ETPS_Pos) /*!< 0x00003000 */
+#define TIM_SMCR_ETPS TIM_SMCR_ETPS_Msk /*!<ETPS[1:0] bits (External trigger prescaler) */
+#define TIM_SMCR_ETPS_0 (0x1U << TIM_SMCR_ETPS_Pos) /*!< 0x00001000 */
+#define TIM_SMCR_ETPS_1 (0x2U << TIM_SMCR_ETPS_Pos) /*!< 0x00002000 */
+
+#define TIM_SMCR_ECE_Pos (14U)
+#define TIM_SMCR_ECE_Msk (0x1U << TIM_SMCR_ECE_Pos) /*!< 0x00004000 */
+#define TIM_SMCR_ECE TIM_SMCR_ECE_Msk /*!<External clock enable */
+#define TIM_SMCR_ETP_Pos (15U)
+#define TIM_SMCR_ETP_Msk (0x1U << TIM_SMCR_ETP_Pos) /*!< 0x00008000 */
+#define TIM_SMCR_ETP TIM_SMCR_ETP_Msk /*!<External trigger polarity */
+
+/******************* Bit definition for TIM_DIER register ******************/
+#define TIM_DIER_UIE_Pos (0U)
+#define TIM_DIER_UIE_Msk (0x1U << TIM_DIER_UIE_Pos) /*!< 0x00000001 */
+#define TIM_DIER_UIE TIM_DIER_UIE_Msk /*!<Update interrupt enable */
+#define TIM_DIER_CC1IE_Pos (1U)
+#define TIM_DIER_CC1IE_Msk (0x1U << TIM_DIER_CC1IE_Pos) /*!< 0x00000002 */
+#define TIM_DIER_CC1IE TIM_DIER_CC1IE_Msk /*!<Capture/Compare 1 interrupt enable */
+#define TIM_DIER_CC2IE_Pos (2U)
+#define TIM_DIER_CC2IE_Msk (0x1U << TIM_DIER_CC2IE_Pos) /*!< 0x00000004 */
+#define TIM_DIER_CC2IE TIM_DIER_CC2IE_Msk /*!<Capture/Compare 2 interrupt enable */
+#define TIM_DIER_CC3IE_Pos (3U)
+#define TIM_DIER_CC3IE_Msk (0x1U << TIM_DIER_CC3IE_Pos) /*!< 0x00000008 */
+#define TIM_DIER_CC3IE TIM_DIER_CC3IE_Msk /*!<Capture/Compare 3 interrupt enable */
+#define TIM_DIER_CC4IE_Pos (4U)
+#define TIM_DIER_CC4IE_Msk (0x1U << TIM_DIER_CC4IE_Pos) /*!< 0x00000010 */
+#define TIM_DIER_CC4IE TIM_DIER_CC4IE_Msk /*!<Capture/Compare 4 interrupt enable */
+#define TIM_DIER_COMIE_Pos (5U)
+#define TIM_DIER_COMIE_Msk (0x1U << TIM_DIER_COMIE_Pos) /*!< 0x00000020 */
+#define TIM_DIER_COMIE TIM_DIER_COMIE_Msk /*!<COM interrupt enable */
+#define TIM_DIER_TIE_Pos (6U)
+#define TIM_DIER_TIE_Msk (0x1U << TIM_DIER_TIE_Pos) /*!< 0x00000040 */
+#define TIM_DIER_TIE TIM_DIER_TIE_Msk /*!<Trigger interrupt enable */
+#define TIM_DIER_BIE_Pos (7U)
+#define TIM_DIER_BIE_Msk (0x1U << TIM_DIER_BIE_Pos) /*!< 0x00000080 */
+#define TIM_DIER_BIE TIM_DIER_BIE_Msk /*!<Break interrupt enable */
+#define TIM_DIER_UDE_Pos (8U)
+#define TIM_DIER_UDE_Msk (0x1U << TIM_DIER_UDE_Pos) /*!< 0x00000100 */
+#define TIM_DIER_UDE TIM_DIER_UDE_Msk /*!<Update DMA request enable */
+#define TIM_DIER_CC1DE_Pos (9U)
+#define TIM_DIER_CC1DE_Msk (0x1U << TIM_DIER_CC1DE_Pos) /*!< 0x00000200 */
+#define TIM_DIER_CC1DE TIM_DIER_CC1DE_Msk /*!<Capture/Compare 1 DMA request enable */
+#define TIM_DIER_CC2DE_Pos (10U)
+#define TIM_DIER_CC2DE_Msk (0x1U << TIM_DIER_CC2DE_Pos) /*!< 0x00000400 */
+#define TIM_DIER_CC2DE TIM_DIER_CC2DE_Msk /*!<Capture/Compare 2 DMA request enable */
+#define TIM_DIER_CC3DE_Pos (11U)
+#define TIM_DIER_CC3DE_Msk (0x1U << TIM_DIER_CC3DE_Pos) /*!< 0x00000800 */
+#define TIM_DIER_CC3DE TIM_DIER_CC3DE_Msk /*!<Capture/Compare 3 DMA request enable */
+#define TIM_DIER_CC4DE_Pos (12U)
+#define TIM_DIER_CC4DE_Msk (0x1U << TIM_DIER_CC4DE_Pos) /*!< 0x00001000 */
+#define TIM_DIER_CC4DE TIM_DIER_CC4DE_Msk /*!<Capture/Compare 4 DMA request enable */
+#define TIM_DIER_COMDE_Pos (13U)
+#define TIM_DIER_COMDE_Msk (0x1U << TIM_DIER_COMDE_Pos) /*!< 0x00002000 */
+#define TIM_DIER_COMDE TIM_DIER_COMDE_Msk /*!<COM DMA request enable */
+#define TIM_DIER_TDE_Pos (14U)
+#define TIM_DIER_TDE_Msk (0x1U << TIM_DIER_TDE_Pos) /*!< 0x00004000 */
+#define TIM_DIER_TDE TIM_DIER_TDE_Msk /*!<Trigger DMA request enable */
+
+/******************** Bit definition for TIM_SR register *******************/
+#define TIM_SR_UIF_Pos (0U)
+#define TIM_SR_UIF_Msk (0x1U << TIM_SR_UIF_Pos) /*!< 0x00000001 */
+#define TIM_SR_UIF TIM_SR_UIF_Msk /*!<Update interrupt Flag */
+#define TIM_SR_CC1IF_Pos (1U)
+#define TIM_SR_CC1IF_Msk (0x1U << TIM_SR_CC1IF_Pos) /*!< 0x00000002 */
+#define TIM_SR_CC1IF TIM_SR_CC1IF_Msk /*!<Capture/Compare 1 interrupt Flag */
+#define TIM_SR_CC2IF_Pos (2U)
+#define TIM_SR_CC2IF_Msk (0x1U << TIM_SR_CC2IF_Pos) /*!< 0x00000004 */
+#define TIM_SR_CC2IF TIM_SR_CC2IF_Msk /*!<Capture/Compare 2 interrupt Flag */
+#define TIM_SR_CC3IF_Pos (3U)
+#define TIM_SR_CC3IF_Msk (0x1U << TIM_SR_CC3IF_Pos) /*!< 0x00000008 */
+#define TIM_SR_CC3IF TIM_SR_CC3IF_Msk /*!<Capture/Compare 3 interrupt Flag */
+#define TIM_SR_CC4IF_Pos (4U)
+#define TIM_SR_CC4IF_Msk (0x1U << TIM_SR_CC4IF_Pos) /*!< 0x00000010 */
+#define TIM_SR_CC4IF TIM_SR_CC4IF_Msk /*!<Capture/Compare 4 interrupt Flag */
+#define TIM_SR_COMIF_Pos (5U)
+#define TIM_SR_COMIF_Msk (0x1U << TIM_SR_COMIF_Pos) /*!< 0x00000020 */
+#define TIM_SR_COMIF TIM_SR_COMIF_Msk /*!<COM interrupt Flag */
+#define TIM_SR_TIF_Pos (6U)
+#define TIM_SR_TIF_Msk (0x1U << TIM_SR_TIF_Pos) /*!< 0x00000040 */
+#define TIM_SR_TIF TIM_SR_TIF_Msk /*!<Trigger interrupt Flag */
+#define TIM_SR_BIF_Pos (7U)
+#define TIM_SR_BIF_Msk (0x1U << TIM_SR_BIF_Pos) /*!< 0x00000080 */
+#define TIM_SR_BIF TIM_SR_BIF_Msk /*!<Break interrupt Flag */
+#define TIM_SR_CC1OF_Pos (9U)
+#define TIM_SR_CC1OF_Msk (0x1U << TIM_SR_CC1OF_Pos) /*!< 0x00000200 */
+#define TIM_SR_CC1OF TIM_SR_CC1OF_Msk /*!<Capture/Compare 1 Overcapture Flag */
+#define TIM_SR_CC2OF_Pos (10U)
+#define TIM_SR_CC2OF_Msk (0x1U << TIM_SR_CC2OF_Pos) /*!< 0x00000400 */
+#define TIM_SR_CC2OF TIM_SR_CC2OF_Msk /*!<Capture/Compare 2 Overcapture Flag */
+#define TIM_SR_CC3OF_Pos (11U)
+#define TIM_SR_CC3OF_Msk (0x1U << TIM_SR_CC3OF_Pos) /*!< 0x00000800 */
+#define TIM_SR_CC3OF TIM_SR_CC3OF_Msk /*!<Capture/Compare 3 Overcapture Flag */
+#define TIM_SR_CC4OF_Pos (12U)
+#define TIM_SR_CC4OF_Msk (0x1U << TIM_SR_CC4OF_Pos) /*!< 0x00001000 */
+#define TIM_SR_CC4OF TIM_SR_CC4OF_Msk /*!<Capture/Compare 4 Overcapture Flag */
+
+/******************* Bit definition for TIM_EGR register *******************/
+#define TIM_EGR_UG_Pos (0U)
+#define TIM_EGR_UG_Msk (0x1U << TIM_EGR_UG_Pos) /*!< 0x00000001 */
+#define TIM_EGR_UG TIM_EGR_UG_Msk /*!<Update Generation */
+#define TIM_EGR_CC1G_Pos (1U)
+#define TIM_EGR_CC1G_Msk (0x1U << TIM_EGR_CC1G_Pos) /*!< 0x00000002 */
+#define TIM_EGR_CC1G TIM_EGR_CC1G_Msk /*!<Capture/Compare 1 Generation */
+#define TIM_EGR_CC2G_Pos (2U)
+#define TIM_EGR_CC2G_Msk (0x1U << TIM_EGR_CC2G_Pos) /*!< 0x00000004 */
+#define TIM_EGR_CC2G TIM_EGR_CC2G_Msk /*!<Capture/Compare 2 Generation */
+#define TIM_EGR_CC3G_Pos (3U)
+#define TIM_EGR_CC3G_Msk (0x1U << TIM_EGR_CC3G_Pos) /*!< 0x00000008 */
+#define TIM_EGR_CC3G TIM_EGR_CC3G_Msk /*!<Capture/Compare 3 Generation */
+#define TIM_EGR_CC4G_Pos (4U)
+#define TIM_EGR_CC4G_Msk (0x1U << TIM_EGR_CC4G_Pos) /*!< 0x00000010 */
+#define TIM_EGR_CC4G TIM_EGR_CC4G_Msk /*!<Capture/Compare 4 Generation */
+#define TIM_EGR_COMG_Pos (5U)
+#define TIM_EGR_COMG_Msk (0x1U << TIM_EGR_COMG_Pos) /*!< 0x00000020 */
+#define TIM_EGR_COMG TIM_EGR_COMG_Msk /*!<Capture/Compare Control Update Generation */
+#define TIM_EGR_TG_Pos (6U)
+#define TIM_EGR_TG_Msk (0x1U << TIM_EGR_TG_Pos) /*!< 0x00000040 */
+#define TIM_EGR_TG TIM_EGR_TG_Msk /*!<Trigger Generation */
+#define TIM_EGR_BG_Pos (7U)
+#define TIM_EGR_BG_Msk (0x1U << TIM_EGR_BG_Pos) /*!< 0x00000080 */
+#define TIM_EGR_BG TIM_EGR_BG_Msk /*!<Break Generation */
+
+/****************** Bit definition for TIM_CCMR1 register ******************/
+#define TIM_CCMR1_CC1S_Pos (0U)
+#define TIM_CCMR1_CC1S_Msk (0x3U << TIM_CCMR1_CC1S_Pos) /*!< 0x00000003 */
+#define TIM_CCMR1_CC1S TIM_CCMR1_CC1S_Msk /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
+#define TIM_CCMR1_CC1S_0 (0x1U << TIM_CCMR1_CC1S_Pos) /*!< 0x00000001 */
+#define TIM_CCMR1_CC1S_1 (0x2U << TIM_CCMR1_CC1S_Pos) /*!< 0x00000002 */
+
+#define TIM_CCMR1_OC1FE_Pos (2U)
+#define TIM_CCMR1_OC1FE_Msk (0x1U << TIM_CCMR1_OC1FE_Pos) /*!< 0x00000004 */
+#define TIM_CCMR1_OC1FE TIM_CCMR1_OC1FE_Msk /*!<Output Compare 1 Fast enable */
+#define TIM_CCMR1_OC1PE_Pos (3U)
+#define TIM_CCMR1_OC1PE_Msk (0x1U << TIM_CCMR1_OC1PE_Pos) /*!< 0x00000008 */
+#define TIM_CCMR1_OC1PE TIM_CCMR1_OC1PE_Msk /*!<Output Compare 1 Preload enable */
+
+#define TIM_CCMR1_OC1M_Pos (4U)
+#define TIM_CCMR1_OC1M_Msk (0x7U << TIM_CCMR1_OC1M_Pos) /*!< 0x00000070 */
+#define TIM_CCMR1_OC1M TIM_CCMR1_OC1M_Msk /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
+#define TIM_CCMR1_OC1M_0 (0x1U << TIM_CCMR1_OC1M_Pos) /*!< 0x00000010 */
+#define TIM_CCMR1_OC1M_1 (0x2U << TIM_CCMR1_OC1M_Pos) /*!< 0x00000020 */
+#define TIM_CCMR1_OC1M_2 (0x4U << TIM_CCMR1_OC1M_Pos) /*!< 0x00000040 */
+
+#define TIM_CCMR1_OC1CE_Pos (7U)
+#define TIM_CCMR1_OC1CE_Msk (0x1U << TIM_CCMR1_OC1CE_Pos) /*!< 0x00000080 */
+#define TIM_CCMR1_OC1CE TIM_CCMR1_OC1CE_Msk /*!<Output Compare 1Clear Enable */
+
+#define TIM_CCMR1_CC2S_Pos (8U)
+#define TIM_CCMR1_CC2S_Msk (0x3U << TIM_CCMR1_CC2S_Pos) /*!< 0x00000300 */
+#define TIM_CCMR1_CC2S TIM_CCMR1_CC2S_Msk /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
+#define TIM_CCMR1_CC2S_0 (0x1U << TIM_CCMR1_CC2S_Pos) /*!< 0x00000100 */
+#define TIM_CCMR1_CC2S_1 (0x2U << TIM_CCMR1_CC2S_Pos) /*!< 0x00000200 */
+
+#define TIM_CCMR1_OC2FE_Pos (10U)
+#define TIM_CCMR1_OC2FE_Msk (0x1U << TIM_CCMR1_OC2FE_Pos) /*!< 0x00000400 */
+#define TIM_CCMR1_OC2FE TIM_CCMR1_OC2FE_Msk /*!<Output Compare 2 Fast enable */
+#define TIM_CCMR1_OC2PE_Pos (11U)
+#define TIM_CCMR1_OC2PE_Msk (0x1U << TIM_CCMR1_OC2PE_Pos) /*!< 0x00000800 */
+#define TIM_CCMR1_OC2PE TIM_CCMR1_OC2PE_Msk /*!<Output Compare 2 Preload enable */
+
+#define TIM_CCMR1_OC2M_Pos (12U)
+#define TIM_CCMR1_OC2M_Msk (0x7U << TIM_CCMR1_OC2M_Pos) /*!< 0x00007000 */
+#define TIM_CCMR1_OC2M TIM_CCMR1_OC2M_Msk /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
+#define TIM_CCMR1_OC2M_0 (0x1U << TIM_CCMR1_OC2M_Pos) /*!< 0x00001000 */
+#define TIM_CCMR1_OC2M_1 (0x2U << TIM_CCMR1_OC2M_Pos) /*!< 0x00002000 */
+#define TIM_CCMR1_OC2M_2 (0x4U << TIM_CCMR1_OC2M_Pos) /*!< 0x00004000 */
+
+#define TIM_CCMR1_OC2CE_Pos (15U)
+#define TIM_CCMR1_OC2CE_Msk (0x1U << TIM_CCMR1_OC2CE_Pos) /*!< 0x00008000 */
+#define TIM_CCMR1_OC2CE TIM_CCMR1_OC2CE_Msk /*!<Output Compare 2 Clear Enable */
+
+/*---------------------------------------------------------------------------*/
+
+#define TIM_CCMR1_IC1PSC_Pos (2U)
+#define TIM_CCMR1_IC1PSC_Msk (0x3U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x0000000C */
+#define TIM_CCMR1_IC1PSC TIM_CCMR1_IC1PSC_Msk /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
+#define TIM_CCMR1_IC1PSC_0 (0x1U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x00000004 */
+#define TIM_CCMR1_IC1PSC_1 (0x2U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x00000008 */
+
+#define TIM_CCMR1_IC1F_Pos (4U)
+#define TIM_CCMR1_IC1F_Msk (0xFU << TIM_CCMR1_IC1F_Pos) /*!< 0x000000F0 */
+#define TIM_CCMR1_IC1F TIM_CCMR1_IC1F_Msk /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
+#define TIM_CCMR1_IC1F_0 (0x1U << TIM_CCMR1_IC1F_Pos) /*!< 0x00000010 */
+#define TIM_CCMR1_IC1F_1 (0x2U << TIM_CCMR1_IC1F_Pos) /*!< 0x00000020 */
+#define TIM_CCMR1_IC1F_2 (0x4U << TIM_CCMR1_IC1F_Pos) /*!< 0x00000040 */
+#define TIM_CCMR1_IC1F_3 (0x8U << TIM_CCMR1_IC1F_Pos) /*!< 0x00000080 */
+
+#define TIM_CCMR1_IC2PSC_Pos (10U)
+#define TIM_CCMR1_IC2PSC_Msk (0x3U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000C00 */
+#define TIM_CCMR1_IC2PSC TIM_CCMR1_IC2PSC_Msk /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
+#define TIM_CCMR1_IC2PSC_0 (0x1U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000400 */
+#define TIM_CCMR1_IC2PSC_1 (0x2U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000800 */
+
+#define TIM_CCMR1_IC2F_Pos (12U)
+#define TIM_CCMR1_IC2F_Msk (0xFU << TIM_CCMR1_IC2F_Pos) /*!< 0x0000F000 */
+#define TIM_CCMR1_IC2F TIM_CCMR1_IC2F_Msk /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
+#define TIM_CCMR1_IC2F_0 (0x1U << TIM_CCMR1_IC2F_Pos) /*!< 0x00001000 */
+#define TIM_CCMR1_IC2F_1 (0x2U << TIM_CCMR1_IC2F_Pos) /*!< 0x00002000 */
+#define TIM_CCMR1_IC2F_2 (0x4U << TIM_CCMR1_IC2F_Pos) /*!< 0x00004000 */
+#define TIM_CCMR1_IC2F_3 (0x8U << TIM_CCMR1_IC2F_Pos) /*!< 0x00008000 */
+
+/****************** Bit definition for TIM_CCMR2 register ******************/
+#define TIM_CCMR2_CC3S_Pos (0U)
+#define TIM_CCMR2_CC3S_Msk (0x3U << TIM_CCMR2_CC3S_Pos) /*!< 0x00000003 */
+#define TIM_CCMR2_CC3S TIM_CCMR2_CC3S_Msk /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
+#define TIM_CCMR2_CC3S_0 (0x1U << TIM_CCMR2_CC3S_Pos) /*!< 0x00000001 */
+#define TIM_CCMR2_CC3S_1 (0x2U << TIM_CCMR2_CC3S_Pos) /*!< 0x00000002 */
+
+#define TIM_CCMR2_OC3FE_Pos (2U)
+#define TIM_CCMR2_OC3FE_Msk (0x1U << TIM_CCMR2_OC3FE_Pos) /*!< 0x00000004 */
+#define TIM_CCMR2_OC3FE TIM_CCMR2_OC3FE_Msk /*!<Output Compare 3 Fast enable */
+#define TIM_CCMR2_OC3PE_Pos (3U)
+#define TIM_CCMR2_OC3PE_Msk (0x1U << TIM_CCMR2_OC3PE_Pos) /*!< 0x00000008 */
+#define TIM_CCMR2_OC3PE TIM_CCMR2_OC3PE_Msk /*!<Output Compare 3 Preload enable */
+
+#define TIM_CCMR2_OC3M_Pos (4U)
+#define TIM_CCMR2_OC3M_Msk (0x7U << TIM_CCMR2_OC3M_Pos) /*!< 0x00000070 */
+#define TIM_CCMR2_OC3M TIM_CCMR2_OC3M_Msk /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
+#define TIM_CCMR2_OC3M_0 (0x1U << TIM_CCMR2_OC3M_Pos) /*!< 0x00000010 */
+#define TIM_CCMR2_OC3M_1 (0x2U << TIM_CCMR2_OC3M_Pos) /*!< 0x00000020 */
+#define TIM_CCMR2_OC3M_2 (0x4U << TIM_CCMR2_OC3M_Pos) /*!< 0x00000040 */
+
+#define TIM_CCMR2_OC3CE_Pos (7U)
+#define TIM_CCMR2_OC3CE_Msk (0x1U << TIM_CCMR2_OC3CE_Pos) /*!< 0x00000080 */
+#define TIM_CCMR2_OC3CE TIM_CCMR2_OC3CE_Msk /*!<Output Compare 3 Clear Enable */
+
+#define TIM_CCMR2_CC4S_Pos (8U)
+#define TIM_CCMR2_CC4S_Msk (0x3U << TIM_CCMR2_CC4S_Pos) /*!< 0x00000300 */
+#define TIM_CCMR2_CC4S TIM_CCMR2_CC4S_Msk /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
+#define TIM_CCMR2_CC4S_0 (0x1U << TIM_CCMR2_CC4S_Pos) /*!< 0x00000100 */
+#define TIM_CCMR2_CC4S_1 (0x2U << TIM_CCMR2_CC4S_Pos) /*!< 0x00000200 */
+
+#define TIM_CCMR2_OC4FE_Pos (10U)
+#define TIM_CCMR2_OC4FE_Msk (0x1U << TIM_CCMR2_OC4FE_Pos) /*!< 0x00000400 */
+#define TIM_CCMR2_OC4FE TIM_CCMR2_OC4FE_Msk /*!<Output Compare 4 Fast enable */
+#define TIM_CCMR2_OC4PE_Pos (11U)
+#define TIM_CCMR2_OC4PE_Msk (0x1U << TIM_CCMR2_OC4PE_Pos) /*!< 0x00000800 */
+#define TIM_CCMR2_OC4PE TIM_CCMR2_OC4PE_Msk /*!<Output Compare 4 Preload enable */
+
+#define TIM_CCMR2_OC4M_Pos (12U)
+#define TIM_CCMR2_OC4M_Msk (0x7U << TIM_CCMR2_OC4M_Pos) /*!< 0x00007000 */
+#define TIM_CCMR2_OC4M TIM_CCMR2_OC4M_Msk /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
+#define TIM_CCMR2_OC4M_0 (0x1U << TIM_CCMR2_OC4M_Pos) /*!< 0x00001000 */
+#define TIM_CCMR2_OC4M_1 (0x2U << TIM_CCMR2_OC4M_Pos) /*!< 0x00002000 */
+#define TIM_CCMR2_OC4M_2 (0x4U << TIM_CCMR2_OC4M_Pos) /*!< 0x00004000 */
+
+#define TIM_CCMR2_OC4CE_Pos (15U)
+#define TIM_CCMR2_OC4CE_Msk (0x1U << TIM_CCMR2_OC4CE_Pos) /*!< 0x00008000 */
+#define TIM_CCMR2_OC4CE TIM_CCMR2_OC4CE_Msk /*!<Output Compare 4 Clear Enable */
+
+/*---------------------------------------------------------------------------*/
+
+#define TIM_CCMR2_IC3PSC_Pos (2U)
+#define TIM_CCMR2_IC3PSC_Msk (0x3U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x0000000C */
+#define TIM_CCMR2_IC3PSC TIM_CCMR2_IC3PSC_Msk /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
+#define TIM_CCMR2_IC3PSC_0 (0x1U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x00000004 */
+#define TIM_CCMR2_IC3PSC_1 (0x2U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x00000008 */
+
+#define TIM_CCMR2_IC3F_Pos (4U)
+#define TIM_CCMR2_IC3F_Msk (0xFU << TIM_CCMR2_IC3F_Pos) /*!< 0x000000F0 */
+#define TIM_CCMR2_IC3F TIM_CCMR2_IC3F_Msk /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
+#define TIM_CCMR2_IC3F_0 (0x1U << TIM_CCMR2_IC3F_Pos) /*!< 0x00000010 */
+#define TIM_CCMR2_IC3F_1 (0x2U << TIM_CCMR2_IC3F_Pos) /*!< 0x00000020 */
+#define TIM_CCMR2_IC3F_2 (0x4U << TIM_CCMR2_IC3F_Pos) /*!< 0x00000040 */
+#define TIM_CCMR2_IC3F_3 (0x8U << TIM_CCMR2_IC3F_Pos) /*!< 0x00000080 */
+
+#define TIM_CCMR2_IC4PSC_Pos (10U)
+#define TIM_CCMR2_IC4PSC_Msk (0x3U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000C00 */
+#define TIM_CCMR2_IC4PSC TIM_CCMR2_IC4PSC_Msk /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
+#define TIM_CCMR2_IC4PSC_0 (0x1U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000400 */
+#define TIM_CCMR2_IC4PSC_1 (0x2U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000800 */
+
+#define TIM_CCMR2_IC4F_Pos (12U)
+#define TIM_CCMR2_IC4F_Msk (0xFU << TIM_CCMR2_IC4F_Pos) /*!< 0x0000F000 */
+#define TIM_CCMR2_IC4F TIM_CCMR2_IC4F_Msk /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
+#define TIM_CCMR2_IC4F_0 (0x1U << TIM_CCMR2_IC4F_Pos) /*!< 0x00001000 */
+#define TIM_CCMR2_IC4F_1 (0x2U << TIM_CCMR2_IC4F_Pos) /*!< 0x00002000 */
+#define TIM_CCMR2_IC4F_2 (0x4U << TIM_CCMR2_IC4F_Pos) /*!< 0x00004000 */
+#define TIM_CCMR2_IC4F_3 (0x8U << TIM_CCMR2_IC4F_Pos) /*!< 0x00008000 */
+
+/******************* Bit definition for TIM_CCER register ******************/
+#define TIM_CCER_CC1E_Pos (0U)
+#define TIM_CCER_CC1E_Msk (0x1U << TIM_CCER_CC1E_Pos) /*!< 0x00000001 */
+#define TIM_CCER_CC1E TIM_CCER_CC1E_Msk /*!<Capture/Compare 1 output enable */
+#define TIM_CCER_CC1P_Pos (1U)
+#define TIM_CCER_CC1P_Msk (0x1U << TIM_CCER_CC1P_Pos) /*!< 0x00000002 */
+#define TIM_CCER_CC1P TIM_CCER_CC1P_Msk /*!<Capture/Compare 1 output Polarity */
+#define TIM_CCER_CC1NE_Pos (2U)
+#define TIM_CCER_CC1NE_Msk (0x1U << TIM_CCER_CC1NE_Pos) /*!< 0x00000004 */
+#define TIM_CCER_CC1NE TIM_CCER_CC1NE_Msk /*!<Capture/Compare 1 Complementary output enable */
+#define TIM_CCER_CC1NP_Pos (3U)
+#define TIM_CCER_CC1NP_Msk (0x1U << TIM_CCER_CC1NP_Pos) /*!< 0x00000008 */
+#define TIM_CCER_CC1NP TIM_CCER_CC1NP_Msk /*!<Capture/Compare 1 Complementary output Polarity */
+#define TIM_CCER_CC2E_Pos (4U)
+#define TIM_CCER_CC2E_Msk (0x1U << TIM_CCER_CC2E_Pos) /*!< 0x00000010 */
+#define TIM_CCER_CC2E TIM_CCER_CC2E_Msk /*!<Capture/Compare 2 output enable */
+#define TIM_CCER_CC2P_Pos (5U)
+#define TIM_CCER_CC2P_Msk (0x1U << TIM_CCER_CC2P_Pos) /*!< 0x00000020 */
+#define TIM_CCER_CC2P TIM_CCER_CC2P_Msk /*!<Capture/Compare 2 output Polarity */
+#define TIM_CCER_CC2NE_Pos (6U)
+#define TIM_CCER_CC2NE_Msk (0x1U << TIM_CCER_CC2NE_Pos) /*!< 0x00000040 */
+#define TIM_CCER_CC2NE TIM_CCER_CC2NE_Msk /*!<Capture/Compare 2 Complementary output enable */
+#define TIM_CCER_CC2NP_Pos (7U)
+#define TIM_CCER_CC2NP_Msk (0x1U << TIM_CCER_CC2NP_Pos) /*!< 0x00000080 */
+#define TIM_CCER_CC2NP TIM_CCER_CC2NP_Msk /*!<Capture/Compare 2 Complementary output Polarity */
+#define TIM_CCER_CC3E_Pos (8U)
+#define TIM_CCER_CC3E_Msk (0x1U << TIM_CCER_CC3E_Pos) /*!< 0x00000100 */
+#define TIM_CCER_CC3E TIM_CCER_CC3E_Msk /*!<Capture/Compare 3 output enable */
+#define TIM_CCER_CC3P_Pos (9U)
+#define TIM_CCER_CC3P_Msk (0x1U << TIM_CCER_CC3P_Pos) /*!< 0x00000200 */
+#define TIM_CCER_CC3P TIM_CCER_CC3P_Msk /*!<Capture/Compare 3 output Polarity */
+#define TIM_CCER_CC3NE_Pos (10U)
+#define TIM_CCER_CC3NE_Msk (0x1U << TIM_CCER_CC3NE_Pos) /*!< 0x00000400 */
+#define TIM_CCER_CC3NE TIM_CCER_CC3NE_Msk /*!<Capture/Compare 3 Complementary output enable */
+#define TIM_CCER_CC3NP_Pos (11U)
+#define TIM_CCER_CC3NP_Msk (0x1U << TIM_CCER_CC3NP_Pos) /*!< 0x00000800 */
+#define TIM_CCER_CC3NP TIM_CCER_CC3NP_Msk /*!<Capture/Compare 3 Complementary output Polarity */
+#define TIM_CCER_CC4E_Pos (12U)
+#define TIM_CCER_CC4E_Msk (0x1U << TIM_CCER_CC4E_Pos) /*!< 0x00001000 */
+#define TIM_CCER_CC4E TIM_CCER_CC4E_Msk /*!<Capture/Compare 4 output enable */
+#define TIM_CCER_CC4P_Pos (13U)
+#define TIM_CCER_CC4P_Msk (0x1U << TIM_CCER_CC4P_Pos) /*!< 0x00002000 */
+#define TIM_CCER_CC4P TIM_CCER_CC4P_Msk /*!<Capture/Compare 4 output Polarity */
+#define TIM_CCER_CC4NP_Pos (15U)
+#define TIM_CCER_CC4NP_Msk (0x1U << TIM_CCER_CC4NP_Pos) /*!< 0x00008000 */
+#define TIM_CCER_CC4NP TIM_CCER_CC4NP_Msk /*!<Capture/Compare 4 Complementary output Polarity */
+
+/******************* Bit definition for TIM_CNT register *******************/
+#define TIM_CNT_CNT_Pos (0U)
+#define TIM_CNT_CNT_Msk (0xFFFFFFFFU << TIM_CNT_CNT_Pos) /*!< 0xFFFFFFFF */
+#define TIM_CNT_CNT TIM_CNT_CNT_Msk /*!<Counter Value */
+
+/******************* Bit definition for TIM_PSC register *******************/
+#define TIM_PSC_PSC_Pos (0U)
+#define TIM_PSC_PSC_Msk (0xFFFFU << TIM_PSC_PSC_Pos) /*!< 0x0000FFFF */
+#define TIM_PSC_PSC TIM_PSC_PSC_Msk /*!<Prescaler Value */
+
+/******************* Bit definition for TIM_ARR register *******************/
+#define TIM_ARR_ARR_Pos (0U)
+#define TIM_ARR_ARR_Msk (0xFFFFFFFFU << TIM_ARR_ARR_Pos) /*!< 0xFFFFFFFF */
+#define TIM_ARR_ARR TIM_ARR_ARR_Msk /*!<actual auto-reload Value */
+
+/******************* Bit definition for TIM_RCR register *******************/
+#define TIM_RCR_REP_Pos (0U)
+#define TIM_RCR_REP_Msk (0xFFU << TIM_RCR_REP_Pos) /*!< 0x000000FF */
+#define TIM_RCR_REP TIM_RCR_REP_Msk /*!<Repetition Counter Value */
+
+/******************* Bit definition for TIM_CCR1 register ******************/
+#define TIM_CCR1_CCR1_Pos (0U)
+#define TIM_CCR1_CCR1_Msk (0xFFFFU << TIM_CCR1_CCR1_Pos) /*!< 0x0000FFFF */
+#define TIM_CCR1_CCR1 TIM_CCR1_CCR1_Msk /*!<Capture/Compare 1 Value */
+
+/******************* Bit definition for TIM_CCR2 register ******************/
+#define TIM_CCR2_CCR2_Pos (0U)
+#define TIM_CCR2_CCR2_Msk (0xFFFFU << TIM_CCR2_CCR2_Pos) /*!< 0x0000FFFF */
+#define TIM_CCR2_CCR2 TIM_CCR2_CCR2_Msk /*!<Capture/Compare 2 Value */
+
+/******************* Bit definition for TIM_CCR3 register ******************/
+#define TIM_CCR3_CCR3_Pos (0U)
+#define TIM_CCR3_CCR3_Msk (0xFFFFU << TIM_CCR3_CCR3_Pos) /*!< 0x0000FFFF */
+#define TIM_CCR3_CCR3 TIM_CCR3_CCR3_Msk /*!<Capture/Compare 3 Value */
+
+/******************* Bit definition for TIM_CCR4 register ******************/
+#define TIM_CCR4_CCR4_Pos (0U)
+#define TIM_CCR4_CCR4_Msk (0xFFFFU << TIM_CCR4_CCR4_Pos) /*!< 0x0000FFFF */
+#define TIM_CCR4_CCR4 TIM_CCR4_CCR4_Msk /*!<Capture/Compare 4 Value */
+
+/******************* Bit definition for TIM_BDTR register ******************/
+#define TIM_BDTR_DTG_Pos (0U)
+#define TIM_BDTR_DTG_Msk (0xFFU << TIM_BDTR_DTG_Pos) /*!< 0x000000FF */
+#define TIM_BDTR_DTG TIM_BDTR_DTG_Msk /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
+#define TIM_BDTR_DTG_0 (0x01U << TIM_BDTR_DTG_Pos) /*!< 0x00000001 */
+#define TIM_BDTR_DTG_1 (0x02U << TIM_BDTR_DTG_Pos) /*!< 0x00000002 */
+#define TIM_BDTR_DTG_2 (0x04U << TIM_BDTR_DTG_Pos) /*!< 0x00000004 */
+#define TIM_BDTR_DTG_3 (0x08U << TIM_BDTR_DTG_Pos) /*!< 0x00000008 */
+#define TIM_BDTR_DTG_4 (0x10U << TIM_BDTR_DTG_Pos) /*!< 0x00000010 */
+#define TIM_BDTR_DTG_5 (0x20U << TIM_BDTR_DTG_Pos) /*!< 0x00000020 */
+#define TIM_BDTR_DTG_6 (0x40U << TIM_BDTR_DTG_Pos) /*!< 0x00000040 */
+#define TIM_BDTR_DTG_7 (0x80U << TIM_BDTR_DTG_Pos) /*!< 0x00000080 */
+
+#define TIM_BDTR_LOCK_Pos (8U)
+#define TIM_BDTR_LOCK_Msk (0x3U << TIM_BDTR_LOCK_Pos) /*!< 0x00000300 */
+#define TIM_BDTR_LOCK TIM_BDTR_LOCK_Msk /*!<LOCK[1:0] bits (Lock Configuration) */
+#define TIM_BDTR_LOCK_0 (0x1U << TIM_BDTR_LOCK_Pos) /*!< 0x00000100 */
+#define TIM_BDTR_LOCK_1 (0x2U << TIM_BDTR_LOCK_Pos) /*!< 0x00000200 */
+
+#define TIM_BDTR_OSSI_Pos (10U)
+#define TIM_BDTR_OSSI_Msk (0x1U << TIM_BDTR_OSSI_Pos) /*!< 0x00000400 */
+#define TIM_BDTR_OSSI TIM_BDTR_OSSI_Msk /*!<Off-State Selection for Idle mode */
+#define TIM_BDTR_OSSR_Pos (11U)
+#define TIM_BDTR_OSSR_Msk (0x1U << TIM_BDTR_OSSR_Pos) /*!< 0x00000800 */
+#define TIM_BDTR_OSSR TIM_BDTR_OSSR_Msk /*!<Off-State Selection for Run mode */
+#define TIM_BDTR_BKE_Pos (12U)
+#define TIM_BDTR_BKE_Msk (0x1U << TIM_BDTR_BKE_Pos) /*!< 0x00001000 */
+#define TIM_BDTR_BKE TIM_BDTR_BKE_Msk /*!<Break enable */
+#define TIM_BDTR_BKP_Pos (13U)
+#define TIM_BDTR_BKP_Msk (0x1U << TIM_BDTR_BKP_Pos) /*!< 0x00002000 */
+#define TIM_BDTR_BKP TIM_BDTR_BKP_Msk /*!<Break Polarity */
+#define TIM_BDTR_AOE_Pos (14U)
+#define TIM_BDTR_AOE_Msk (0x1U << TIM_BDTR_AOE_Pos) /*!< 0x00004000 */
+#define TIM_BDTR_AOE TIM_BDTR_AOE_Msk /*!<Automatic Output enable */
+#define TIM_BDTR_MOE_Pos (15U)
+#define TIM_BDTR_MOE_Msk (0x1U << TIM_BDTR_MOE_Pos) /*!< 0x00008000 */
+#define TIM_BDTR_MOE TIM_BDTR_MOE_Msk /*!<Main Output enable */
+
+/******************* Bit definition for TIM_DCR register *******************/
+#define TIM_DCR_DBA_Pos (0U)
+#define TIM_DCR_DBA_Msk (0x1FU << TIM_DCR_DBA_Pos) /*!< 0x0000001F */
+#define TIM_DCR_DBA TIM_DCR_DBA_Msk /*!<DBA[4:0] bits (DMA Base Address) */
+#define TIM_DCR_DBA_0 (0x01U << TIM_DCR_DBA_Pos) /*!< 0x00000001 */
+#define TIM_DCR_DBA_1 (0x02U << TIM_DCR_DBA_Pos) /*!< 0x00000002 */
+#define TIM_DCR_DBA_2 (0x04U << TIM_DCR_DBA_Pos) /*!< 0x00000004 */
+#define TIM_DCR_DBA_3 (0x08U << TIM_DCR_DBA_Pos) /*!< 0x00000008 */
+#define TIM_DCR_DBA_4 (0x10U << TIM_DCR_DBA_Pos) /*!< 0x00000010 */
+
+#define TIM_DCR_DBL_Pos (8U)
+#define TIM_DCR_DBL_Msk (0x1FU << TIM_DCR_DBL_Pos) /*!< 0x00001F00 */
+#define TIM_DCR_DBL TIM_DCR_DBL_Msk /*!<DBL[4:0] bits (DMA Burst Length) */
+#define TIM_DCR_DBL_0 (0x01U << TIM_DCR_DBL_Pos) /*!< 0x00000100 */
+#define TIM_DCR_DBL_1 (0x02U << TIM_DCR_DBL_Pos) /*!< 0x00000200 */
+#define TIM_DCR_DBL_2 (0x04U << TIM_DCR_DBL_Pos) /*!< 0x00000400 */
+#define TIM_DCR_DBL_3 (0x08U << TIM_DCR_DBL_Pos) /*!< 0x00000800 */
+#define TIM_DCR_DBL_4 (0x10U << TIM_DCR_DBL_Pos) /*!< 0x00001000 */
+
+/******************* Bit definition for TIM_DMAR register ******************/
+#define TIM_DMAR_DMAB_Pos (0U)
+#define TIM_DMAR_DMAB_Msk (0xFFFFU << TIM_DMAR_DMAB_Pos) /*!< 0x0000FFFF */
+#define TIM_DMAR_DMAB TIM_DMAR_DMAB_Msk /*!<DMA register for burst accesses */
+
+/******************* Bit definition for TIM_OR register ********************/
+
+/******************************************************************************/
+/* */
+/* Real-Time Clock */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for RTC_CRH register ********************/
+#define RTC_CRH_SECIE_Pos (0U)
+#define RTC_CRH_SECIE_Msk (0x1U << RTC_CRH_SECIE_Pos) /*!< 0x00000001 */
+#define RTC_CRH_SECIE RTC_CRH_SECIE_Msk /*!< Second Interrupt Enable */
+#define RTC_CRH_ALRIE_Pos (1U)
+#define RTC_CRH_ALRIE_Msk (0x1U << RTC_CRH_ALRIE_Pos) /*!< 0x00000002 */
+#define RTC_CRH_ALRIE RTC_CRH_ALRIE_Msk /*!< Alarm Interrupt Enable */
+#define RTC_CRH_OWIE_Pos (2U)
+#define RTC_CRH_OWIE_Msk (0x1U << RTC_CRH_OWIE_Pos) /*!< 0x00000004 */
+#define RTC_CRH_OWIE RTC_CRH_OWIE_Msk /*!< OverfloW Interrupt Enable */
+
+/******************* Bit definition for RTC_CRL register ********************/
+#define RTC_CRL_SECF_Pos (0U)
+#define RTC_CRL_SECF_Msk (0x1U << RTC_CRL_SECF_Pos) /*!< 0x00000001 */
+#define RTC_CRL_SECF RTC_CRL_SECF_Msk /*!< Second Flag */
+#define RTC_CRL_ALRF_Pos (1U)
+#define RTC_CRL_ALRF_Msk (0x1U << RTC_CRL_ALRF_Pos) /*!< 0x00000002 */
+#define RTC_CRL_ALRF RTC_CRL_ALRF_Msk /*!< Alarm Flag */
+#define RTC_CRL_OWF_Pos (2U)
+#define RTC_CRL_OWF_Msk (0x1U << RTC_CRL_OWF_Pos) /*!< 0x00000004 */
+#define RTC_CRL_OWF RTC_CRL_OWF_Msk /*!< OverfloW Flag */
+#define RTC_CRL_RSF_Pos (3U)
+#define RTC_CRL_RSF_Msk (0x1U << RTC_CRL_RSF_Pos) /*!< 0x00000008 */
+#define RTC_CRL_RSF RTC_CRL_RSF_Msk /*!< Registers Synchronized Flag */
+#define RTC_CRL_CNF_Pos (4U)
+#define RTC_CRL_CNF_Msk (0x1U << RTC_CRL_CNF_Pos) /*!< 0x00000010 */
+#define RTC_CRL_CNF RTC_CRL_CNF_Msk /*!< Configuration Flag */
+#define RTC_CRL_RTOFF_Pos (5U)
+#define RTC_CRL_RTOFF_Msk (0x1U << RTC_CRL_RTOFF_Pos) /*!< 0x00000020 */
+#define RTC_CRL_RTOFF RTC_CRL_RTOFF_Msk /*!< RTC operation OFF */
+
+/******************* Bit definition for RTC_PRLH register *******************/
+#define RTC_PRLH_PRL_Pos (0U)
+#define RTC_PRLH_PRL_Msk (0xFU << RTC_PRLH_PRL_Pos) /*!< 0x0000000F */
+#define RTC_PRLH_PRL RTC_PRLH_PRL_Msk /*!< RTC Prescaler Reload Value High */
+
+/******************* Bit definition for RTC_PRLL register *******************/
+#define RTC_PRLL_PRL_Pos (0U)
+#define RTC_PRLL_PRL_Msk (0xFFFFU << RTC_PRLL_PRL_Pos) /*!< 0x0000FFFF */
+#define RTC_PRLL_PRL RTC_PRLL_PRL_Msk /*!< RTC Prescaler Reload Value Low */
+
+/******************* Bit definition for RTC_DIVH register *******************/
+#define RTC_DIVH_RTC_DIV_Pos (0U)
+#define RTC_DIVH_RTC_DIV_Msk (0xFU << RTC_DIVH_RTC_DIV_Pos) /*!< 0x0000000F */
+#define RTC_DIVH_RTC_DIV RTC_DIVH_RTC_DIV_Msk /*!< RTC Clock Divider High */
+
+/******************* Bit definition for RTC_DIVL register *******************/
+#define RTC_DIVL_RTC_DIV_Pos (0U)
+#define RTC_DIVL_RTC_DIV_Msk (0xFFFFU << RTC_DIVL_RTC_DIV_Pos) /*!< 0x0000FFFF */
+#define RTC_DIVL_RTC_DIV RTC_DIVL_RTC_DIV_Msk /*!< RTC Clock Divider Low */
+
+/******************* Bit definition for RTC_CNTH register *******************/
+#define RTC_CNTH_RTC_CNT_Pos (0U)
+#define RTC_CNTH_RTC_CNT_Msk (0xFFFFU << RTC_CNTH_RTC_CNT_Pos) /*!< 0x0000FFFF */
+#define RTC_CNTH_RTC_CNT RTC_CNTH_RTC_CNT_Msk /*!< RTC Counter High */
+
+/******************* Bit definition for RTC_CNTL register *******************/
+#define RTC_CNTL_RTC_CNT_Pos (0U)
+#define RTC_CNTL_RTC_CNT_Msk (0xFFFFU << RTC_CNTL_RTC_CNT_Pos) /*!< 0x0000FFFF */
+#define RTC_CNTL_RTC_CNT RTC_CNTL_RTC_CNT_Msk /*!< RTC Counter Low */
+
+/******************* Bit definition for RTC_ALRH register *******************/
+#define RTC_ALRH_RTC_ALR_Pos (0U)
+#define RTC_ALRH_RTC_ALR_Msk (0xFFFFU << RTC_ALRH_RTC_ALR_Pos) /*!< 0x0000FFFF */
+#define RTC_ALRH_RTC_ALR RTC_ALRH_RTC_ALR_Msk /*!< RTC Alarm High */
+
+/******************* Bit definition for RTC_ALRL register *******************/
+#define RTC_ALRL_RTC_ALR_Pos (0U)
+#define RTC_ALRL_RTC_ALR_Msk (0xFFFFU << RTC_ALRL_RTC_ALR_Pos) /*!< 0x0000FFFF */
+#define RTC_ALRL_RTC_ALR RTC_ALRL_RTC_ALR_Msk /*!< RTC Alarm Low */
+
+/******************************************************************************/
+/* */
+/* Independent WATCHDOG (IWDG) */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for IWDG_KR register ********************/
+#define IWDG_KR_KEY_Pos (0U)
+#define IWDG_KR_KEY_Msk (0xFFFFU << IWDG_KR_KEY_Pos) /*!< 0x0000FFFF */
+#define IWDG_KR_KEY IWDG_KR_KEY_Msk /*!< Key value (write only, read 0000h) */
+
+/******************* Bit definition for IWDG_PR register ********************/
+#define IWDG_PR_PR_Pos (0U)
+#define IWDG_PR_PR_Msk (0x7U << IWDG_PR_PR_Pos) /*!< 0x00000007 */
+#define IWDG_PR_PR IWDG_PR_PR_Msk /*!< PR[2:0] (Prescaler divider) */
+#define IWDG_PR_PR_0 (0x1U << IWDG_PR_PR_Pos) /*!< 0x00000001 */
+#define IWDG_PR_PR_1 (0x2U << IWDG_PR_PR_Pos) /*!< 0x00000002 */
+#define IWDG_PR_PR_2 (0x4U << IWDG_PR_PR_Pos) /*!< 0x00000004 */
+
+/******************* Bit definition for IWDG_RLR register *******************/
+#define IWDG_RLR_RL_Pos (0U)
+#define IWDG_RLR_RL_Msk (0xFFFU << IWDG_RLR_RL_Pos) /*!< 0x00000FFF */
+#define IWDG_RLR_RL IWDG_RLR_RL_Msk /*!< Watchdog counter reload value */
+
+/******************* Bit definition for IWDG_SR register ********************/
+#define IWDG_SR_PVU_Pos (0U)
+#define IWDG_SR_PVU_Msk (0x1U << IWDG_SR_PVU_Pos) /*!< 0x00000001 */
+#define IWDG_SR_PVU IWDG_SR_PVU_Msk /*!< Watchdog prescaler value update */
+#define IWDG_SR_RVU_Pos (1U)
+#define IWDG_SR_RVU_Msk (0x1U << IWDG_SR_RVU_Pos) /*!< 0x00000002 */
+#define IWDG_SR_RVU IWDG_SR_RVU_Msk /*!< Watchdog counter reload value update */
+
+/******************************************************************************/
+/* */
+/* Window WATCHDOG (WWDG) */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for WWDG_CR register ********************/
+#define WWDG_CR_T_Pos (0U)
+#define WWDG_CR_T_Msk (0x7FU << WWDG_CR_T_Pos) /*!< 0x0000007F */
+#define WWDG_CR_T WWDG_CR_T_Msk /*!< T[6:0] bits (7-Bit counter (MSB to LSB)) */
+#define WWDG_CR_T_0 (0x01U << WWDG_CR_T_Pos) /*!< 0x00000001 */
+#define WWDG_CR_T_1 (0x02U << WWDG_CR_T_Pos) /*!< 0x00000002 */
+#define WWDG_CR_T_2 (0x04U << WWDG_CR_T_Pos) /*!< 0x00000004 */
+#define WWDG_CR_T_3 (0x08U << WWDG_CR_T_Pos) /*!< 0x00000008 */
+#define WWDG_CR_T_4 (0x10U << WWDG_CR_T_Pos) /*!< 0x00000010 */
+#define WWDG_CR_T_5 (0x20U << WWDG_CR_T_Pos) /*!< 0x00000020 */
+#define WWDG_CR_T_6 (0x40U << WWDG_CR_T_Pos) /*!< 0x00000040 */
+
+/* Legacy defines */
+#define WWDG_CR_T0 WWDG_CR_T_0
+#define WWDG_CR_T1 WWDG_CR_T_1
+#define WWDG_CR_T2 WWDG_CR_T_2
+#define WWDG_CR_T3 WWDG_CR_T_3
+#define WWDG_CR_T4 WWDG_CR_T_4
+#define WWDG_CR_T5 WWDG_CR_T_5
+#define WWDG_CR_T6 WWDG_CR_T_6
+
+#define WWDG_CR_WDGA_Pos (7U)
+#define WWDG_CR_WDGA_Msk (0x1U << WWDG_CR_WDGA_Pos) /*!< 0x00000080 */
+#define WWDG_CR_WDGA WWDG_CR_WDGA_Msk /*!< Activation bit */
+
+/******************* Bit definition for WWDG_CFR register *******************/
+#define WWDG_CFR_W_Pos (0U)
+#define WWDG_CFR_W_Msk (0x7FU << WWDG_CFR_W_Pos) /*!< 0x0000007F */
+#define WWDG_CFR_W WWDG_CFR_W_Msk /*!< W[6:0] bits (7-bit window value) */
+#define WWDG_CFR_W_0 (0x01U << WWDG_CFR_W_Pos) /*!< 0x00000001 */
+#define WWDG_CFR_W_1 (0x02U << WWDG_CFR_W_Pos) /*!< 0x00000002 */
+#define WWDG_CFR_W_2 (0x04U << WWDG_CFR_W_Pos) /*!< 0x00000004 */
+#define WWDG_CFR_W_3 (0x08U << WWDG_CFR_W_Pos) /*!< 0x00000008 */
+#define WWDG_CFR_W_4 (0x10U << WWDG_CFR_W_Pos) /*!< 0x00000010 */
+#define WWDG_CFR_W_5 (0x20U << WWDG_CFR_W_Pos) /*!< 0x00000020 */
+#define WWDG_CFR_W_6 (0x40U << WWDG_CFR_W_Pos) /*!< 0x00000040 */
+
+/* Legacy defines */
+#define WWDG_CFR_W0 WWDG_CFR_W_0
+#define WWDG_CFR_W1 WWDG_CFR_W_1
+#define WWDG_CFR_W2 WWDG_CFR_W_2
+#define WWDG_CFR_W3 WWDG_CFR_W_3
+#define WWDG_CFR_W4 WWDG_CFR_W_4
+#define WWDG_CFR_W5 WWDG_CFR_W_5
+#define WWDG_CFR_W6 WWDG_CFR_W_6
+
+#define WWDG_CFR_WDGTB_Pos (7U)
+#define WWDG_CFR_WDGTB_Msk (0x3U << WWDG_CFR_WDGTB_Pos) /*!< 0x00000180 */
+#define WWDG_CFR_WDGTB WWDG_CFR_WDGTB_Msk /*!< WDGTB[1:0] bits (Timer Base) */
+#define WWDG_CFR_WDGTB_0 (0x1U << WWDG_CFR_WDGTB_Pos) /*!< 0x00000080 */
+#define WWDG_CFR_WDGTB_1 (0x2U << WWDG_CFR_WDGTB_Pos) /*!< 0x00000100 */
+
+/* Legacy defines */
+#define WWDG_CFR_WDGTB0 WWDG_CFR_WDGTB_0
+#define WWDG_CFR_WDGTB1 WWDG_CFR_WDGTB_1
+
+#define WWDG_CFR_EWI_Pos (9U)
+#define WWDG_CFR_EWI_Msk (0x1U << WWDG_CFR_EWI_Pos) /*!< 0x00000200 */
+#define WWDG_CFR_EWI WWDG_CFR_EWI_Msk /*!< Early Wakeup Interrupt */
+
+/******************* Bit definition for WWDG_SR register ********************/
+#define WWDG_SR_EWIF_Pos (0U)
+#define WWDG_SR_EWIF_Msk (0x1U << WWDG_SR_EWIF_Pos) /*!< 0x00000001 */
+#define WWDG_SR_EWIF WWDG_SR_EWIF_Msk /*!< Early Wakeup Interrupt Flag */
+
+
+/******************************************************************************/
+/* */
+/* SD host Interface */
+/* */
+/******************************************************************************/
+
+/****************** Bit definition for SDIO_POWER register ******************/
+#define SDIO_POWER_PWRCTRL_Pos (0U)
+#define SDIO_POWER_PWRCTRL_Msk (0x3U << SDIO_POWER_PWRCTRL_Pos) /*!< 0x00000003 */
+#define SDIO_POWER_PWRCTRL SDIO_POWER_PWRCTRL_Msk /*!< PWRCTRL[1:0] bits (Power supply control bits) */
+#define SDIO_POWER_PWRCTRL_0 (0x1U << SDIO_POWER_PWRCTRL_Pos) /*!< 0x01 */
+#define SDIO_POWER_PWRCTRL_1 (0x2U << SDIO_POWER_PWRCTRL_Pos) /*!< 0x02 */
+
+/****************** Bit definition for SDIO_CLKCR register ******************/
+#define SDIO_CLKCR_CLKDIV_Pos (0U)
+#define SDIO_CLKCR_CLKDIV_Msk (0xFFU << SDIO_CLKCR_CLKDIV_Pos) /*!< 0x000000FF */
+#define SDIO_CLKCR_CLKDIV SDIO_CLKCR_CLKDIV_Msk /*!< Clock divide factor */
+#define SDIO_CLKCR_CLKEN_Pos (8U)
+#define SDIO_CLKCR_CLKEN_Msk (0x1U << SDIO_CLKCR_CLKEN_Pos) /*!< 0x00000100 */
+#define SDIO_CLKCR_CLKEN SDIO_CLKCR_CLKEN_Msk /*!< Clock enable bit */
+#define SDIO_CLKCR_PWRSAV_Pos (9U)
+#define SDIO_CLKCR_PWRSAV_Msk (0x1U << SDIO_CLKCR_PWRSAV_Pos) /*!< 0x00000200 */
+#define SDIO_CLKCR_PWRSAV SDIO_CLKCR_PWRSAV_Msk /*!< Power saving configuration bit */
+#define SDIO_CLKCR_BYPASS_Pos (10U)
+#define SDIO_CLKCR_BYPASS_Msk (0x1U << SDIO_CLKCR_BYPASS_Pos) /*!< 0x00000400 */
+#define SDIO_CLKCR_BYPASS SDIO_CLKCR_BYPASS_Msk /*!< Clock divider bypass enable bit */
+
+#define SDIO_CLKCR_WIDBUS_Pos (11U)
+#define SDIO_CLKCR_WIDBUS_Msk (0x3U << SDIO_CLKCR_WIDBUS_Pos) /*!< 0x00001800 */
+#define SDIO_CLKCR_WIDBUS SDIO_CLKCR_WIDBUS_Msk /*!< WIDBUS[1:0] bits (Wide bus mode enable bit) */
+#define SDIO_CLKCR_WIDBUS_0 (0x1U << SDIO_CLKCR_WIDBUS_Pos) /*!< 0x0800 */
+#define SDIO_CLKCR_WIDBUS_1 (0x2U << SDIO_CLKCR_WIDBUS_Pos) /*!< 0x1000 */
+
+#define SDIO_CLKCR_NEGEDGE_Pos (13U)
+#define SDIO_CLKCR_NEGEDGE_Msk (0x1U << SDIO_CLKCR_NEGEDGE_Pos) /*!< 0x00002000 */
+#define SDIO_CLKCR_NEGEDGE SDIO_CLKCR_NEGEDGE_Msk /*!< SDIO_CK dephasing selection bit */
+#define SDIO_CLKCR_HWFC_EN_Pos (14U)
+#define SDIO_CLKCR_HWFC_EN_Msk (0x1U << SDIO_CLKCR_HWFC_EN_Pos) /*!< 0x00004000 */
+#define SDIO_CLKCR_HWFC_EN SDIO_CLKCR_HWFC_EN_Msk /*!< HW Flow Control enable */
+
+/******************* Bit definition for SDIO_ARG register *******************/
+#define SDIO_ARG_CMDARG_Pos (0U)
+#define SDIO_ARG_CMDARG_Msk (0xFFFFFFFFU << SDIO_ARG_CMDARG_Pos) /*!< 0xFFFFFFFF */
+#define SDIO_ARG_CMDARG SDIO_ARG_CMDARG_Msk /*!< Command argument */
+
+/******************* Bit definition for SDIO_CMD register *******************/
+#define SDIO_CMD_CMDINDEX_Pos (0U)
+#define SDIO_CMD_CMDINDEX_Msk (0x3FU << SDIO_CMD_CMDINDEX_Pos) /*!< 0x0000003F */
+#define SDIO_CMD_CMDINDEX SDIO_CMD_CMDINDEX_Msk /*!< Command Index */
+
+#define SDIO_CMD_WAITRESP_Pos (6U)
+#define SDIO_CMD_WAITRESP_Msk (0x3U << SDIO_CMD_WAITRESP_Pos) /*!< 0x000000C0 */
+#define SDIO_CMD_WAITRESP SDIO_CMD_WAITRESP_Msk /*!< WAITRESP[1:0] bits (Wait for response bits) */
+#define SDIO_CMD_WAITRESP_0 (0x1U << SDIO_CMD_WAITRESP_Pos) /*!< 0x0040 */
+#define SDIO_CMD_WAITRESP_1 (0x2U << SDIO_CMD_WAITRESP_Pos) /*!< 0x0080 */
+
+#define SDIO_CMD_WAITINT_Pos (8U)
+#define SDIO_CMD_WAITINT_Msk (0x1U << SDIO_CMD_WAITINT_Pos) /*!< 0x00000100 */
+#define SDIO_CMD_WAITINT SDIO_CMD_WAITINT_Msk /*!< CPSM Waits for Interrupt Request */
+#define SDIO_CMD_WAITPEND_Pos (9U)
+#define SDIO_CMD_WAITPEND_Msk (0x1U << SDIO_CMD_WAITPEND_Pos) /*!< 0x00000200 */
+#define SDIO_CMD_WAITPEND SDIO_CMD_WAITPEND_Msk /*!< CPSM Waits for ends of data transfer (CmdPend internal signal) */
+#define SDIO_CMD_CPSMEN_Pos (10U)
+#define SDIO_CMD_CPSMEN_Msk (0x1U << SDIO_CMD_CPSMEN_Pos) /*!< 0x00000400 */
+#define SDIO_CMD_CPSMEN SDIO_CMD_CPSMEN_Msk /*!< Command path state machine (CPSM) Enable bit */
+#define SDIO_CMD_SDIOSUSPEND_Pos (11U)
+#define SDIO_CMD_SDIOSUSPEND_Msk (0x1U << SDIO_CMD_SDIOSUSPEND_Pos) /*!< 0x00000800 */
+#define SDIO_CMD_SDIOSUSPEND SDIO_CMD_SDIOSUSPEND_Msk /*!< SD I/O suspend command */
+#define SDIO_CMD_ENCMDCOMPL_Pos (12U)
+#define SDIO_CMD_ENCMDCOMPL_Msk (0x1U << SDIO_CMD_ENCMDCOMPL_Pos) /*!< 0x00001000 */
+#define SDIO_CMD_ENCMDCOMPL SDIO_CMD_ENCMDCOMPL_Msk /*!< Enable CMD completion */
+#define SDIO_CMD_NIEN_Pos (13U)
+#define SDIO_CMD_NIEN_Msk (0x1U << SDIO_CMD_NIEN_Pos) /*!< 0x00002000 */
+#define SDIO_CMD_NIEN SDIO_CMD_NIEN_Msk /*!< Not Interrupt Enable */
+#define SDIO_CMD_CEATACMD_Pos (14U)
+#define SDIO_CMD_CEATACMD_Msk (0x1U << SDIO_CMD_CEATACMD_Pos) /*!< 0x00004000 */
+#define SDIO_CMD_CEATACMD SDIO_CMD_CEATACMD_Msk /*!< CE-ATA command */
+
+/***************** Bit definition for SDIO_RESPCMD register *****************/
+#define SDIO_RESPCMD_RESPCMD_Pos (0U)
+#define SDIO_RESPCMD_RESPCMD_Msk (0x3FU << SDIO_RESPCMD_RESPCMD_Pos) /*!< 0x0000003F */
+#define SDIO_RESPCMD_RESPCMD SDIO_RESPCMD_RESPCMD_Msk /*!< Response command index */
+
+/****************** Bit definition for SDIO_RESP0 register ******************/
+#define SDIO_RESP0_CARDSTATUS0_Pos (0U)
+#define SDIO_RESP0_CARDSTATUS0_Msk (0xFFFFFFFFU << SDIO_RESP0_CARDSTATUS0_Pos) /*!< 0xFFFFFFFF */
+#define SDIO_RESP0_CARDSTATUS0 SDIO_RESP0_CARDSTATUS0_Msk /*!< Card Status */
+
+/****************** Bit definition for SDIO_RESP1 register ******************/
+#define SDIO_RESP1_CARDSTATUS1_Pos (0U)
+#define SDIO_RESP1_CARDSTATUS1_Msk (0xFFFFFFFFU << SDIO_RESP1_CARDSTATUS1_Pos) /*!< 0xFFFFFFFF */
+#define SDIO_RESP1_CARDSTATUS1 SDIO_RESP1_CARDSTATUS1_Msk /*!< Card Status */
+
+/****************** Bit definition for SDIO_RESP2 register ******************/
+#define SDIO_RESP2_CARDSTATUS2_Pos (0U)
+#define SDIO_RESP2_CARDSTATUS2_Msk (0xFFFFFFFFU << SDIO_RESP2_CARDSTATUS2_Pos) /*!< 0xFFFFFFFF */
+#define SDIO_RESP2_CARDSTATUS2 SDIO_RESP2_CARDSTATUS2_Msk /*!< Card Status */
+
+/****************** Bit definition for SDIO_RESP3 register ******************/
+#define SDIO_RESP3_CARDSTATUS3_Pos (0U)
+#define SDIO_RESP3_CARDSTATUS3_Msk (0xFFFFFFFFU << SDIO_RESP3_CARDSTATUS3_Pos) /*!< 0xFFFFFFFF */
+#define SDIO_RESP3_CARDSTATUS3 SDIO_RESP3_CARDSTATUS3_Msk /*!< Card Status */
+
+/****************** Bit definition for SDIO_RESP4 register ******************/
+#define SDIO_RESP4_CARDSTATUS4_Pos (0U)
+#define SDIO_RESP4_CARDSTATUS4_Msk (0xFFFFFFFFU << SDIO_RESP4_CARDSTATUS4_Pos) /*!< 0xFFFFFFFF */
+#define SDIO_RESP4_CARDSTATUS4 SDIO_RESP4_CARDSTATUS4_Msk /*!< Card Status */
+
+/****************** Bit definition for SDIO_DTIMER register *****************/
+#define SDIO_DTIMER_DATATIME_Pos (0U)
+#define SDIO_DTIMER_DATATIME_Msk (0xFFFFFFFFU << SDIO_DTIMER_DATATIME_Pos) /*!< 0xFFFFFFFF */
+#define SDIO_DTIMER_DATATIME SDIO_DTIMER_DATATIME_Msk /*!< Data timeout period. */
+
+/****************** Bit definition for SDIO_DLEN register *******************/
+#define SDIO_DLEN_DATALENGTH_Pos (0U)
+#define SDIO_DLEN_DATALENGTH_Msk (0x1FFFFFFU << SDIO_DLEN_DATALENGTH_Pos) /*!< 0x01FFFFFF */
+#define SDIO_DLEN_DATALENGTH SDIO_DLEN_DATALENGTH_Msk /*!< Data length value */
+
+/****************** Bit definition for SDIO_DCTRL register ******************/
+#define SDIO_DCTRL_DTEN_Pos (0U)
+#define SDIO_DCTRL_DTEN_Msk (0x1U << SDIO_DCTRL_DTEN_Pos) /*!< 0x00000001 */
+#define SDIO_DCTRL_DTEN SDIO_DCTRL_DTEN_Msk /*!< Data transfer enabled bit */
+#define SDIO_DCTRL_DTDIR_Pos (1U)
+#define SDIO_DCTRL_DTDIR_Msk (0x1U << SDIO_DCTRL_DTDIR_Pos) /*!< 0x00000002 */
+#define SDIO_DCTRL_DTDIR SDIO_DCTRL_DTDIR_Msk /*!< Data transfer direction selection */
+#define SDIO_DCTRL_DTMODE_Pos (2U)
+#define SDIO_DCTRL_DTMODE_Msk (0x1U << SDIO_DCTRL_DTMODE_Pos) /*!< 0x00000004 */
+#define SDIO_DCTRL_DTMODE SDIO_DCTRL_DTMODE_Msk /*!< Data transfer mode selection */
+#define SDIO_DCTRL_DMAEN_Pos (3U)
+#define SDIO_DCTRL_DMAEN_Msk (0x1U << SDIO_DCTRL_DMAEN_Pos) /*!< 0x00000008 */
+#define SDIO_DCTRL_DMAEN SDIO_DCTRL_DMAEN_Msk /*!< DMA enabled bit */
+
+#define SDIO_DCTRL_DBLOCKSIZE_Pos (4U)
+#define SDIO_DCTRL_DBLOCKSIZE_Msk (0xFU << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x000000F0 */
+#define SDIO_DCTRL_DBLOCKSIZE SDIO_DCTRL_DBLOCKSIZE_Msk /*!< DBLOCKSIZE[3:0] bits (Data block size) */
+#define SDIO_DCTRL_DBLOCKSIZE_0 (0x1U << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0010 */
+#define SDIO_DCTRL_DBLOCKSIZE_1 (0x2U << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0020 */
+#define SDIO_DCTRL_DBLOCKSIZE_2 (0x4U << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0040 */
+#define SDIO_DCTRL_DBLOCKSIZE_3 (0x8U << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0080 */
+
+#define SDIO_DCTRL_RWSTART_Pos (8U)
+#define SDIO_DCTRL_RWSTART_Msk (0x1U << SDIO_DCTRL_RWSTART_Pos) /*!< 0x00000100 */
+#define SDIO_DCTRL_RWSTART SDIO_DCTRL_RWSTART_Msk /*!< Read wait start */
+#define SDIO_DCTRL_RWSTOP_Pos (9U)
+#define SDIO_DCTRL_RWSTOP_Msk (0x1U << SDIO_DCTRL_RWSTOP_Pos) /*!< 0x00000200 */
+#define SDIO_DCTRL_RWSTOP SDIO_DCTRL_RWSTOP_Msk /*!< Read wait stop */
+#define SDIO_DCTRL_RWMOD_Pos (10U)
+#define SDIO_DCTRL_RWMOD_Msk (0x1U << SDIO_DCTRL_RWMOD_Pos) /*!< 0x00000400 */
+#define SDIO_DCTRL_RWMOD SDIO_DCTRL_RWMOD_Msk /*!< Read wait mode */
+#define SDIO_DCTRL_SDIOEN_Pos (11U)
+#define SDIO_DCTRL_SDIOEN_Msk (0x1U << SDIO_DCTRL_SDIOEN_Pos) /*!< 0x00000800 */
+#define SDIO_DCTRL_SDIOEN SDIO_DCTRL_SDIOEN_Msk /*!< SD I/O enable functions */
+
+/****************** Bit definition for SDIO_DCOUNT register *****************/
+#define SDIO_DCOUNT_DATACOUNT_Pos (0U)
+#define SDIO_DCOUNT_DATACOUNT_Msk (0x1FFFFFFU << SDIO_DCOUNT_DATACOUNT_Pos) /*!< 0x01FFFFFF */
+#define SDIO_DCOUNT_DATACOUNT SDIO_DCOUNT_DATACOUNT_Msk /*!< Data count value */
+
+/****************** Bit definition for SDIO_STA register ********************/
+#define SDIO_STA_CCRCFAIL_Pos (0U)
+#define SDIO_STA_CCRCFAIL_Msk (0x1U << SDIO_STA_CCRCFAIL_Pos) /*!< 0x00000001 */
+#define SDIO_STA_CCRCFAIL SDIO_STA_CCRCFAIL_Msk /*!< Command response received (CRC check failed) */
+#define SDIO_STA_DCRCFAIL_Pos (1U)
+#define SDIO_STA_DCRCFAIL_Msk (0x1U << SDIO_STA_DCRCFAIL_Pos) /*!< 0x00000002 */
+#define SDIO_STA_DCRCFAIL SDIO_STA_DCRCFAIL_Msk /*!< Data block sent/received (CRC check failed) */
+#define SDIO_STA_CTIMEOUT_Pos (2U)
+#define SDIO_STA_CTIMEOUT_Msk (0x1U << SDIO_STA_CTIMEOUT_Pos) /*!< 0x00000004 */
+#define SDIO_STA_CTIMEOUT SDIO_STA_CTIMEOUT_Msk /*!< Command response timeout */
+#define SDIO_STA_DTIMEOUT_Pos (3U)
+#define SDIO_STA_DTIMEOUT_Msk (0x1U << SDIO_STA_DTIMEOUT_Pos) /*!< 0x00000008 */
+#define SDIO_STA_DTIMEOUT SDIO_STA_DTIMEOUT_Msk /*!< Data timeout */
+#define SDIO_STA_TXUNDERR_Pos (4U)
+#define SDIO_STA_TXUNDERR_Msk (0x1U << SDIO_STA_TXUNDERR_Pos) /*!< 0x00000010 */
+#define SDIO_STA_TXUNDERR SDIO_STA_TXUNDERR_Msk /*!< Transmit FIFO underrun error */
+#define SDIO_STA_RXOVERR_Pos (5U)
+#define SDIO_STA_RXOVERR_Msk (0x1U << SDIO_STA_RXOVERR_Pos) /*!< 0x00000020 */
+#define SDIO_STA_RXOVERR SDIO_STA_RXOVERR_Msk /*!< Received FIFO overrun error */
+#define SDIO_STA_CMDREND_Pos (6U)
+#define SDIO_STA_CMDREND_Msk (0x1U << SDIO_STA_CMDREND_Pos) /*!< 0x00000040 */
+#define SDIO_STA_CMDREND SDIO_STA_CMDREND_Msk /*!< Command response received (CRC check passed) */
+#define SDIO_STA_CMDSENT_Pos (7U)
+#define SDIO_STA_CMDSENT_Msk (0x1U << SDIO_STA_CMDSENT_Pos) /*!< 0x00000080 */
+#define SDIO_STA_CMDSENT SDIO_STA_CMDSENT_Msk /*!< Command sent (no response required) */
+#define SDIO_STA_DATAEND_Pos (8U)
+#define SDIO_STA_DATAEND_Msk (0x1U << SDIO_STA_DATAEND_Pos) /*!< 0x00000100 */
+#define SDIO_STA_DATAEND SDIO_STA_DATAEND_Msk /*!< Data end (data counter, SDIDCOUNT, is zero) */
+#define SDIO_STA_STBITERR_Pos (9U)
+#define SDIO_STA_STBITERR_Msk (0x1U << SDIO_STA_STBITERR_Pos) /*!< 0x00000200 */
+#define SDIO_STA_STBITERR SDIO_STA_STBITERR_Msk /*!< Start bit not detected on all data signals in wide bus mode */
+#define SDIO_STA_DBCKEND_Pos (10U)
+#define SDIO_STA_DBCKEND_Msk (0x1U << SDIO_STA_DBCKEND_Pos) /*!< 0x00000400 */
+#define SDIO_STA_DBCKEND SDIO_STA_DBCKEND_Msk /*!< Data block sent/received (CRC check passed) */
+#define SDIO_STA_CMDACT_Pos (11U)
+#define SDIO_STA_CMDACT_Msk (0x1U << SDIO_STA_CMDACT_Pos) /*!< 0x00000800 */
+#define SDIO_STA_CMDACT SDIO_STA_CMDACT_Msk /*!< Command transfer in progress */
+#define SDIO_STA_TXACT_Pos (12U)
+#define SDIO_STA_TXACT_Msk (0x1U << SDIO_STA_TXACT_Pos) /*!< 0x00001000 */
+#define SDIO_STA_TXACT SDIO_STA_TXACT_Msk /*!< Data transmit in progress */
+#define SDIO_STA_RXACT_Pos (13U)
+#define SDIO_STA_RXACT_Msk (0x1U << SDIO_STA_RXACT_Pos) /*!< 0x00002000 */
+#define SDIO_STA_RXACT SDIO_STA_RXACT_Msk /*!< Data receive in progress */
+#define SDIO_STA_TXFIFOHE_Pos (14U)
+#define SDIO_STA_TXFIFOHE_Msk (0x1U << SDIO_STA_TXFIFOHE_Pos) /*!< 0x00004000 */
+#define SDIO_STA_TXFIFOHE SDIO_STA_TXFIFOHE_Msk /*!< Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
+#define SDIO_STA_RXFIFOHF_Pos (15U)
+#define SDIO_STA_RXFIFOHF_Msk (0x1U << SDIO_STA_RXFIFOHF_Pos) /*!< 0x00008000 */
+#define SDIO_STA_RXFIFOHF SDIO_STA_RXFIFOHF_Msk /*!< Receive FIFO Half Full: there are at least 8 words in the FIFO */
+#define SDIO_STA_TXFIFOF_Pos (16U)
+#define SDIO_STA_TXFIFOF_Msk (0x1U << SDIO_STA_TXFIFOF_Pos) /*!< 0x00010000 */
+#define SDIO_STA_TXFIFOF SDIO_STA_TXFIFOF_Msk /*!< Transmit FIFO full */
+#define SDIO_STA_RXFIFOF_Pos (17U)
+#define SDIO_STA_RXFIFOF_Msk (0x1U << SDIO_STA_RXFIFOF_Pos) /*!< 0x00020000 */
+#define SDIO_STA_RXFIFOF SDIO_STA_RXFIFOF_Msk /*!< Receive FIFO full */
+#define SDIO_STA_TXFIFOE_Pos (18U)
+#define SDIO_STA_TXFIFOE_Msk (0x1U << SDIO_STA_TXFIFOE_Pos) /*!< 0x00040000 */
+#define SDIO_STA_TXFIFOE SDIO_STA_TXFIFOE_Msk /*!< Transmit FIFO empty */
+#define SDIO_STA_RXFIFOE_Pos (19U)
+#define SDIO_STA_RXFIFOE_Msk (0x1U << SDIO_STA_RXFIFOE_Pos) /*!< 0x00080000 */
+#define SDIO_STA_RXFIFOE SDIO_STA_RXFIFOE_Msk /*!< Receive FIFO empty */
+#define SDIO_STA_TXDAVL_Pos (20U)
+#define SDIO_STA_TXDAVL_Msk (0x1U << SDIO_STA_TXDAVL_Pos) /*!< 0x00100000 */
+#define SDIO_STA_TXDAVL SDIO_STA_TXDAVL_Msk /*!< Data available in transmit FIFO */
+#define SDIO_STA_RXDAVL_Pos (21U)
+#define SDIO_STA_RXDAVL_Msk (0x1U << SDIO_STA_RXDAVL_Pos) /*!< 0x00200000 */
+#define SDIO_STA_RXDAVL SDIO_STA_RXDAVL_Msk /*!< Data available in receive FIFO */
+#define SDIO_STA_SDIOIT_Pos (22U)
+#define SDIO_STA_SDIOIT_Msk (0x1U << SDIO_STA_SDIOIT_Pos) /*!< 0x00400000 */
+#define SDIO_STA_SDIOIT SDIO_STA_SDIOIT_Msk /*!< SDIO interrupt received */
+#define SDIO_STA_CEATAEND_Pos (23U)
+#define SDIO_STA_CEATAEND_Msk (0x1U << SDIO_STA_CEATAEND_Pos) /*!< 0x00800000 */
+#define SDIO_STA_CEATAEND SDIO_STA_CEATAEND_Msk /*!< CE-ATA command completion signal received for CMD61 */
+
+/******************* Bit definition for SDIO_ICR register *******************/
+#define SDIO_ICR_CCRCFAILC_Pos (0U)
+#define SDIO_ICR_CCRCFAILC_Msk (0x1U << SDIO_ICR_CCRCFAILC_Pos) /*!< 0x00000001 */
+#define SDIO_ICR_CCRCFAILC SDIO_ICR_CCRCFAILC_Msk /*!< CCRCFAIL flag clear bit */
+#define SDIO_ICR_DCRCFAILC_Pos (1U)
+#define SDIO_ICR_DCRCFAILC_Msk (0x1U << SDIO_ICR_DCRCFAILC_Pos) /*!< 0x00000002 */
+#define SDIO_ICR_DCRCFAILC SDIO_ICR_DCRCFAILC_Msk /*!< DCRCFAIL flag clear bit */
+#define SDIO_ICR_CTIMEOUTC_Pos (2U)
+#define SDIO_ICR_CTIMEOUTC_Msk (0x1U << SDIO_ICR_CTIMEOUTC_Pos) /*!< 0x00000004 */
+#define SDIO_ICR_CTIMEOUTC SDIO_ICR_CTIMEOUTC_Msk /*!< CTIMEOUT flag clear bit */
+#define SDIO_ICR_DTIMEOUTC_Pos (3U)
+#define SDIO_ICR_DTIMEOUTC_Msk (0x1U << SDIO_ICR_DTIMEOUTC_Pos) /*!< 0x00000008 */
+#define SDIO_ICR_DTIMEOUTC SDIO_ICR_DTIMEOUTC_Msk /*!< DTIMEOUT flag clear bit */
+#define SDIO_ICR_TXUNDERRC_Pos (4U)
+#define SDIO_ICR_TXUNDERRC_Msk (0x1U << SDIO_ICR_TXUNDERRC_Pos) /*!< 0x00000010 */
+#define SDIO_ICR_TXUNDERRC SDIO_ICR_TXUNDERRC_Msk /*!< TXUNDERR flag clear bit */
+#define SDIO_ICR_RXOVERRC_Pos (5U)
+#define SDIO_ICR_RXOVERRC_Msk (0x1U << SDIO_ICR_RXOVERRC_Pos) /*!< 0x00000020 */
+#define SDIO_ICR_RXOVERRC SDIO_ICR_RXOVERRC_Msk /*!< RXOVERR flag clear bit */
+#define SDIO_ICR_CMDRENDC_Pos (6U)
+#define SDIO_ICR_CMDRENDC_Msk (0x1U << SDIO_ICR_CMDRENDC_Pos) /*!< 0x00000040 */
+#define SDIO_ICR_CMDRENDC SDIO_ICR_CMDRENDC_Msk /*!< CMDREND flag clear bit */
+#define SDIO_ICR_CMDSENTC_Pos (7U)
+#define SDIO_ICR_CMDSENTC_Msk (0x1U << SDIO_ICR_CMDSENTC_Pos) /*!< 0x00000080 */
+#define SDIO_ICR_CMDSENTC SDIO_ICR_CMDSENTC_Msk /*!< CMDSENT flag clear bit */
+#define SDIO_ICR_DATAENDC_Pos (8U)
+#define SDIO_ICR_DATAENDC_Msk (0x1U << SDIO_ICR_DATAENDC_Pos) /*!< 0x00000100 */
+#define SDIO_ICR_DATAENDC SDIO_ICR_DATAENDC_Msk /*!< DATAEND flag clear bit */
+#define SDIO_ICR_STBITERRC_Pos (9U)
+#define SDIO_ICR_STBITERRC_Msk (0x1U << SDIO_ICR_STBITERRC_Pos) /*!< 0x00000200 */
+#define SDIO_ICR_STBITERRC SDIO_ICR_STBITERRC_Msk /*!< STBITERR flag clear bit */
+#define SDIO_ICR_DBCKENDC_Pos (10U)
+#define SDIO_ICR_DBCKENDC_Msk (0x1U << SDIO_ICR_DBCKENDC_Pos) /*!< 0x00000400 */
+#define SDIO_ICR_DBCKENDC SDIO_ICR_DBCKENDC_Msk /*!< DBCKEND flag clear bit */
+#define SDIO_ICR_SDIOITC_Pos (22U)
+#define SDIO_ICR_SDIOITC_Msk (0x1U << SDIO_ICR_SDIOITC_Pos) /*!< 0x00400000 */
+#define SDIO_ICR_SDIOITC SDIO_ICR_SDIOITC_Msk /*!< SDIOIT flag clear bit */
+#define SDIO_ICR_CEATAENDC_Pos (23U)
+#define SDIO_ICR_CEATAENDC_Msk (0x1U << SDIO_ICR_CEATAENDC_Pos) /*!< 0x00800000 */
+#define SDIO_ICR_CEATAENDC SDIO_ICR_CEATAENDC_Msk /*!< CEATAEND flag clear bit */
+
+/****************** Bit definition for SDIO_MASK register *******************/
+#define SDIO_MASK_CCRCFAILIE_Pos (0U)
+#define SDIO_MASK_CCRCFAILIE_Msk (0x1U << SDIO_MASK_CCRCFAILIE_Pos) /*!< 0x00000001 */
+#define SDIO_MASK_CCRCFAILIE SDIO_MASK_CCRCFAILIE_Msk /*!< Command CRC Fail Interrupt Enable */
+#define SDIO_MASK_DCRCFAILIE_Pos (1U)
+#define SDIO_MASK_DCRCFAILIE_Msk (0x1U << SDIO_MASK_DCRCFAILIE_Pos) /*!< 0x00000002 */
+#define SDIO_MASK_DCRCFAILIE SDIO_MASK_DCRCFAILIE_Msk /*!< Data CRC Fail Interrupt Enable */
+#define SDIO_MASK_CTIMEOUTIE_Pos (2U)
+#define SDIO_MASK_CTIMEOUTIE_Msk (0x1U << SDIO_MASK_CTIMEOUTIE_Pos) /*!< 0x00000004 */
+#define SDIO_MASK_CTIMEOUTIE SDIO_MASK_CTIMEOUTIE_Msk /*!< Command TimeOut Interrupt Enable */
+#define SDIO_MASK_DTIMEOUTIE_Pos (3U)
+#define SDIO_MASK_DTIMEOUTIE_Msk (0x1U << SDIO_MASK_DTIMEOUTIE_Pos) /*!< 0x00000008 */
+#define SDIO_MASK_DTIMEOUTIE SDIO_MASK_DTIMEOUTIE_Msk /*!< Data TimeOut Interrupt Enable */
+#define SDIO_MASK_TXUNDERRIE_Pos (4U)
+#define SDIO_MASK_TXUNDERRIE_Msk (0x1U << SDIO_MASK_TXUNDERRIE_Pos) /*!< 0x00000010 */
+#define SDIO_MASK_TXUNDERRIE SDIO_MASK_TXUNDERRIE_Msk /*!< Tx FIFO UnderRun Error Interrupt Enable */
+#define SDIO_MASK_RXOVERRIE_Pos (5U)
+#define SDIO_MASK_RXOVERRIE_Msk (0x1U << SDIO_MASK_RXOVERRIE_Pos) /*!< 0x00000020 */
+#define SDIO_MASK_RXOVERRIE SDIO_MASK_RXOVERRIE_Msk /*!< Rx FIFO OverRun Error Interrupt Enable */
+#define SDIO_MASK_CMDRENDIE_Pos (6U)
+#define SDIO_MASK_CMDRENDIE_Msk (0x1U << SDIO_MASK_CMDRENDIE_Pos) /*!< 0x00000040 */
+#define SDIO_MASK_CMDRENDIE SDIO_MASK_CMDRENDIE_Msk /*!< Command Response Received Interrupt Enable */
+#define SDIO_MASK_CMDSENTIE_Pos (7U)
+#define SDIO_MASK_CMDSENTIE_Msk (0x1U << SDIO_MASK_CMDSENTIE_Pos) /*!< 0x00000080 */
+#define SDIO_MASK_CMDSENTIE SDIO_MASK_CMDSENTIE_Msk /*!< Command Sent Interrupt Enable */
+#define SDIO_MASK_DATAENDIE_Pos (8U)
+#define SDIO_MASK_DATAENDIE_Msk (0x1U << SDIO_MASK_DATAENDIE_Pos) /*!< 0x00000100 */
+#define SDIO_MASK_DATAENDIE SDIO_MASK_DATAENDIE_Msk /*!< Data End Interrupt Enable */
+#define SDIO_MASK_STBITERRIE_Pos (9U)
+#define SDIO_MASK_STBITERRIE_Msk (0x1U << SDIO_MASK_STBITERRIE_Pos) /*!< 0x00000200 */
+#define SDIO_MASK_STBITERRIE SDIO_MASK_STBITERRIE_Msk /*!< Start Bit Error Interrupt Enable */
+#define SDIO_MASK_DBCKENDIE_Pos (10U)
+#define SDIO_MASK_DBCKENDIE_Msk (0x1U << SDIO_MASK_DBCKENDIE_Pos) /*!< 0x00000400 */
+#define SDIO_MASK_DBCKENDIE SDIO_MASK_DBCKENDIE_Msk /*!< Data Block End Interrupt Enable */
+#define SDIO_MASK_CMDACTIE_Pos (11U)
+#define SDIO_MASK_CMDACTIE_Msk (0x1U << SDIO_MASK_CMDACTIE_Pos) /*!< 0x00000800 */
+#define SDIO_MASK_CMDACTIE SDIO_MASK_CMDACTIE_Msk /*!< Command Acting Interrupt Enable */
+#define SDIO_MASK_TXACTIE_Pos (12U)
+#define SDIO_MASK_TXACTIE_Msk (0x1U << SDIO_MASK_TXACTIE_Pos) /*!< 0x00001000 */
+#define SDIO_MASK_TXACTIE SDIO_MASK_TXACTIE_Msk /*!< Data Transmit Acting Interrupt Enable */
+#define SDIO_MASK_RXACTIE_Pos (13U)
+#define SDIO_MASK_RXACTIE_Msk (0x1U << SDIO_MASK_RXACTIE_Pos) /*!< 0x00002000 */
+#define SDIO_MASK_RXACTIE SDIO_MASK_RXACTIE_Msk /*!< Data receive acting interrupt enabled */
+#define SDIO_MASK_TXFIFOHEIE_Pos (14U)
+#define SDIO_MASK_TXFIFOHEIE_Msk (0x1U << SDIO_MASK_TXFIFOHEIE_Pos) /*!< 0x00004000 */
+#define SDIO_MASK_TXFIFOHEIE SDIO_MASK_TXFIFOHEIE_Msk /*!< Tx FIFO Half Empty interrupt Enable */
+#define SDIO_MASK_RXFIFOHFIE_Pos (15U)
+#define SDIO_MASK_RXFIFOHFIE_Msk (0x1U << SDIO_MASK_RXFIFOHFIE_Pos) /*!< 0x00008000 */
+#define SDIO_MASK_RXFIFOHFIE SDIO_MASK_RXFIFOHFIE_Msk /*!< Rx FIFO Half Full interrupt Enable */
+#define SDIO_MASK_TXFIFOFIE_Pos (16U)
+#define SDIO_MASK_TXFIFOFIE_Msk (0x1U << SDIO_MASK_TXFIFOFIE_Pos) /*!< 0x00010000 */
+#define SDIO_MASK_TXFIFOFIE SDIO_MASK_TXFIFOFIE_Msk /*!< Tx FIFO Full interrupt Enable */
+#define SDIO_MASK_RXFIFOFIE_Pos (17U)
+#define SDIO_MASK_RXFIFOFIE_Msk (0x1U << SDIO_MASK_RXFIFOFIE_Pos) /*!< 0x00020000 */
+#define SDIO_MASK_RXFIFOFIE SDIO_MASK_RXFIFOFIE_Msk /*!< Rx FIFO Full interrupt Enable */
+#define SDIO_MASK_TXFIFOEIE_Pos (18U)
+#define SDIO_MASK_TXFIFOEIE_Msk (0x1U << SDIO_MASK_TXFIFOEIE_Pos) /*!< 0x00040000 */
+#define SDIO_MASK_TXFIFOEIE SDIO_MASK_TXFIFOEIE_Msk /*!< Tx FIFO Empty interrupt Enable */
+#define SDIO_MASK_RXFIFOEIE_Pos (19U)
+#define SDIO_MASK_RXFIFOEIE_Msk (0x1U << SDIO_MASK_RXFIFOEIE_Pos) /*!< 0x00080000 */
+#define SDIO_MASK_RXFIFOEIE SDIO_MASK_RXFIFOEIE_Msk /*!< Rx FIFO Empty interrupt Enable */
+#define SDIO_MASK_TXDAVLIE_Pos (20U)
+#define SDIO_MASK_TXDAVLIE_Msk (0x1U << SDIO_MASK_TXDAVLIE_Pos) /*!< 0x00100000 */
+#define SDIO_MASK_TXDAVLIE SDIO_MASK_TXDAVLIE_Msk /*!< Data available in Tx FIFO interrupt Enable */
+#define SDIO_MASK_RXDAVLIE_Pos (21U)
+#define SDIO_MASK_RXDAVLIE_Msk (0x1U << SDIO_MASK_RXDAVLIE_Pos) /*!< 0x00200000 */
+#define SDIO_MASK_RXDAVLIE SDIO_MASK_RXDAVLIE_Msk /*!< Data available in Rx FIFO interrupt Enable */
+#define SDIO_MASK_SDIOITIE_Pos (22U)
+#define SDIO_MASK_SDIOITIE_Msk (0x1U << SDIO_MASK_SDIOITIE_Pos) /*!< 0x00400000 */
+#define SDIO_MASK_SDIOITIE SDIO_MASK_SDIOITIE_Msk /*!< SDIO Mode Interrupt Received interrupt Enable */
+#define SDIO_MASK_CEATAENDIE_Pos (23U)
+#define SDIO_MASK_CEATAENDIE_Msk (0x1U << SDIO_MASK_CEATAENDIE_Pos) /*!< 0x00800000 */
+#define SDIO_MASK_CEATAENDIE SDIO_MASK_CEATAENDIE_Msk /*!< CE-ATA command completion signal received Interrupt Enable */
+
+/***************** Bit definition for SDIO_FIFOCNT register *****************/
+#define SDIO_FIFOCNT_FIFOCOUNT_Pos (0U)
+#define SDIO_FIFOCNT_FIFOCOUNT_Msk (0xFFFFFFU << SDIO_FIFOCNT_FIFOCOUNT_Pos) /*!< 0x00FFFFFF */
+#define SDIO_FIFOCNT_FIFOCOUNT SDIO_FIFOCNT_FIFOCOUNT_Msk /*!< Remaining number of words to be written to or read from the FIFO */
+
+/****************** Bit definition for SDIO_FIFO register *******************/
+#define SDIO_FIFO_FIFODATA_Pos (0U)
+#define SDIO_FIFO_FIFODATA_Msk (0xFFFFFFFFU << SDIO_FIFO_FIFODATA_Pos) /*!< 0xFFFFFFFF */
+#define SDIO_FIFO_FIFODATA SDIO_FIFO_FIFODATA_Msk /*!< Receive and transmit FIFO data */
+
+
+/******************************************************************************/
+/* */
+/* Controller Area Network */
+/* */
+/******************************************************************************/
+
+/*!< CAN control and status registers */
+/******************* Bit definition for CAN_MCR register ********************/
+#define CAN_MCR_INRQ_Pos (0U)
+#define CAN_MCR_INRQ_Msk (0x1U << CAN_MCR_INRQ_Pos) /*!< 0x00000001 */
+#define CAN_MCR_INRQ CAN_MCR_INRQ_Msk /*!< Initialization Request */
+#define CAN_MCR_SLEEP_Pos (1U)
+#define CAN_MCR_SLEEP_Msk (0x1U << CAN_MCR_SLEEP_Pos) /*!< 0x00000002 */
+#define CAN_MCR_SLEEP CAN_MCR_SLEEP_Msk /*!< Sleep Mode Request */
+#define CAN_MCR_TXFP_Pos (2U)
+#define CAN_MCR_TXFP_Msk (0x1U << CAN_MCR_TXFP_Pos) /*!< 0x00000004 */
+#define CAN_MCR_TXFP CAN_MCR_TXFP_Msk /*!< Transmit FIFO Priority */
+#define CAN_MCR_RFLM_Pos (3U)
+#define CAN_MCR_RFLM_Msk (0x1U << CAN_MCR_RFLM_Pos) /*!< 0x00000008 */
+#define CAN_MCR_RFLM CAN_MCR_RFLM_Msk /*!< Receive FIFO Locked Mode */
+#define CAN_MCR_NART_Pos (4U)
+#define CAN_MCR_NART_Msk (0x1U << CAN_MCR_NART_Pos) /*!< 0x00000010 */
+#define CAN_MCR_NART CAN_MCR_NART_Msk /*!< No Automatic Retransmission */
+#define CAN_MCR_AWUM_Pos (5U)
+#define CAN_MCR_AWUM_Msk (0x1U << CAN_MCR_AWUM_Pos) /*!< 0x00000020 */
+#define CAN_MCR_AWUM CAN_MCR_AWUM_Msk /*!< Automatic Wakeup Mode */
+#define CAN_MCR_ABOM_Pos (6U)
+#define CAN_MCR_ABOM_Msk (0x1U << CAN_MCR_ABOM_Pos) /*!< 0x00000040 */
+#define CAN_MCR_ABOM CAN_MCR_ABOM_Msk /*!< Automatic Bus-Off Management */
+#define CAN_MCR_TTCM_Pos (7U)
+#define CAN_MCR_TTCM_Msk (0x1U << CAN_MCR_TTCM_Pos) /*!< 0x00000080 */
+#define CAN_MCR_TTCM CAN_MCR_TTCM_Msk /*!< Time Triggered Communication Mode */
+#define CAN_MCR_RESET_Pos (15U)
+#define CAN_MCR_RESET_Msk (0x1U << CAN_MCR_RESET_Pos) /*!< 0x00008000 */
+#define CAN_MCR_RESET CAN_MCR_RESET_Msk /*!< CAN software master reset */
+#define CAN_MCR_DBF_Pos (16U)
+#define CAN_MCR_DBF_Msk (0x1U << CAN_MCR_DBF_Pos) /*!< 0x00010000 */
+#define CAN_MCR_DBF CAN_MCR_DBF_Msk /*!< CAN Debug freeze */
+
+/******************* Bit definition for CAN_MSR register ********************/
+#define CAN_MSR_INAK_Pos (0U)
+#define CAN_MSR_INAK_Msk (0x1U << CAN_MSR_INAK_Pos) /*!< 0x00000001 */
+#define CAN_MSR_INAK CAN_MSR_INAK_Msk /*!< Initialization Acknowledge */
+#define CAN_MSR_SLAK_Pos (1U)
+#define CAN_MSR_SLAK_Msk (0x1U << CAN_MSR_SLAK_Pos) /*!< 0x00000002 */
+#define CAN_MSR_SLAK CAN_MSR_SLAK_Msk /*!< Sleep Acknowledge */
+#define CAN_MSR_ERRI_Pos (2U)
+#define CAN_MSR_ERRI_Msk (0x1U << CAN_MSR_ERRI_Pos) /*!< 0x00000004 */
+#define CAN_MSR_ERRI CAN_MSR_ERRI_Msk /*!< Error Interrupt */
+#define CAN_MSR_WKUI_Pos (3U)
+#define CAN_MSR_WKUI_Msk (0x1U << CAN_MSR_WKUI_Pos) /*!< 0x00000008 */
+#define CAN_MSR_WKUI CAN_MSR_WKUI_Msk /*!< Wakeup Interrupt */
+#define CAN_MSR_SLAKI_Pos (4U)
+#define CAN_MSR_SLAKI_Msk (0x1U << CAN_MSR_SLAKI_Pos) /*!< 0x00000010 */
+#define CAN_MSR_SLAKI CAN_MSR_SLAKI_Msk /*!< Sleep Acknowledge Interrupt */
+#define CAN_MSR_TXM_Pos (8U)
+#define CAN_MSR_TXM_Msk (0x1U << CAN_MSR_TXM_Pos) /*!< 0x00000100 */
+#define CAN_MSR_TXM CAN_MSR_TXM_Msk /*!< Transmit Mode */
+#define CAN_MSR_RXM_Pos (9U)
+#define CAN_MSR_RXM_Msk (0x1U << CAN_MSR_RXM_Pos) /*!< 0x00000200 */
+#define CAN_MSR_RXM CAN_MSR_RXM_Msk /*!< Receive Mode */
+#define CAN_MSR_SAMP_Pos (10U)
+#define CAN_MSR_SAMP_Msk (0x1U << CAN_MSR_SAMP_Pos) /*!< 0x00000400 */
+#define CAN_MSR_SAMP CAN_MSR_SAMP_Msk /*!< Last Sample Point */
+#define CAN_MSR_RX_Pos (11U)
+#define CAN_MSR_RX_Msk (0x1U << CAN_MSR_RX_Pos) /*!< 0x00000800 */
+#define CAN_MSR_RX CAN_MSR_RX_Msk /*!< CAN Rx Signal */
+
+/******************* Bit definition for CAN_TSR register ********************/
+#define CAN_TSR_RQCP0_Pos (0U)
+#define CAN_TSR_RQCP0_Msk (0x1U << CAN_TSR_RQCP0_Pos) /*!< 0x00000001 */
+#define CAN_TSR_RQCP0 CAN_TSR_RQCP0_Msk /*!< Request Completed Mailbox0 */
+#define CAN_TSR_TXOK0_Pos (1U)
+#define CAN_TSR_TXOK0_Msk (0x1U << CAN_TSR_TXOK0_Pos) /*!< 0x00000002 */
+#define CAN_TSR_TXOK0 CAN_TSR_TXOK0_Msk /*!< Transmission OK of Mailbox0 */
+#define CAN_TSR_ALST0_Pos (2U)
+#define CAN_TSR_ALST0_Msk (0x1U << CAN_TSR_ALST0_Pos) /*!< 0x00000004 */
+#define CAN_TSR_ALST0 CAN_TSR_ALST0_Msk /*!< Arbitration Lost for Mailbox0 */
+#define CAN_TSR_TERR0_Pos (3U)
+#define CAN_TSR_TERR0_Msk (0x1U << CAN_TSR_TERR0_Pos) /*!< 0x00000008 */
+#define CAN_TSR_TERR0 CAN_TSR_TERR0_Msk /*!< Transmission Error of Mailbox0 */
+#define CAN_TSR_ABRQ0_Pos (7U)
+#define CAN_TSR_ABRQ0_Msk (0x1U << CAN_TSR_ABRQ0_Pos) /*!< 0x00000080 */
+#define CAN_TSR_ABRQ0 CAN_TSR_ABRQ0_Msk /*!< Abort Request for Mailbox0 */
+#define CAN_TSR_RQCP1_Pos (8U)
+#define CAN_TSR_RQCP1_Msk (0x1U << CAN_TSR_RQCP1_Pos) /*!< 0x00000100 */
+#define CAN_TSR_RQCP1 CAN_TSR_RQCP1_Msk /*!< Request Completed Mailbox1 */
+#define CAN_TSR_TXOK1_Pos (9U)
+#define CAN_TSR_TXOK1_Msk (0x1U << CAN_TSR_TXOK1_Pos) /*!< 0x00000200 */
+#define CAN_TSR_TXOK1 CAN_TSR_TXOK1_Msk /*!< Transmission OK of Mailbox1 */
+#define CAN_TSR_ALST1_Pos (10U)
+#define CAN_TSR_ALST1_Msk (0x1U << CAN_TSR_ALST1_Pos) /*!< 0x00000400 */
+#define CAN_TSR_ALST1 CAN_TSR_ALST1_Msk /*!< Arbitration Lost for Mailbox1 */
+#define CAN_TSR_TERR1_Pos (11U)
+#define CAN_TSR_TERR1_Msk (0x1U << CAN_TSR_TERR1_Pos) /*!< 0x00000800 */
+#define CAN_TSR_TERR1 CAN_TSR_TERR1_Msk /*!< Transmission Error of Mailbox1 */
+#define CAN_TSR_ABRQ1_Pos (15U)
+#define CAN_TSR_ABRQ1_Msk (0x1U << CAN_TSR_ABRQ1_Pos) /*!< 0x00008000 */
+#define CAN_TSR_ABRQ1 CAN_TSR_ABRQ1_Msk /*!< Abort Request for Mailbox 1 */
+#define CAN_TSR_RQCP2_Pos (16U)
+#define CAN_TSR_RQCP2_Msk (0x1U << CAN_TSR_RQCP2_Pos) /*!< 0x00010000 */
+#define CAN_TSR_RQCP2 CAN_TSR_RQCP2_Msk /*!< Request Completed Mailbox2 */
+#define CAN_TSR_TXOK2_Pos (17U)
+#define CAN_TSR_TXOK2_Msk (0x1U << CAN_TSR_TXOK2_Pos) /*!< 0x00020000 */
+#define CAN_TSR_TXOK2 CAN_TSR_TXOK2_Msk /*!< Transmission OK of Mailbox 2 */
+#define CAN_TSR_ALST2_Pos (18U)
+#define CAN_TSR_ALST2_Msk (0x1U << CAN_TSR_ALST2_Pos) /*!< 0x00040000 */
+#define CAN_TSR_ALST2 CAN_TSR_ALST2_Msk /*!< Arbitration Lost for mailbox 2 */
+#define CAN_TSR_TERR2_Pos (19U)
+#define CAN_TSR_TERR2_Msk (0x1U << CAN_TSR_TERR2_Pos) /*!< 0x00080000 */
+#define CAN_TSR_TERR2 CAN_TSR_TERR2_Msk /*!< Transmission Error of Mailbox 2 */
+#define CAN_TSR_ABRQ2_Pos (23U)
+#define CAN_TSR_ABRQ2_Msk (0x1U << CAN_TSR_ABRQ2_Pos) /*!< 0x00800000 */
+#define CAN_TSR_ABRQ2 CAN_TSR_ABRQ2_Msk /*!< Abort Request for Mailbox 2 */
+#define CAN_TSR_CODE_Pos (24U)
+#define CAN_TSR_CODE_Msk (0x3U << CAN_TSR_CODE_Pos) /*!< 0x03000000 */
+#define CAN_TSR_CODE CAN_TSR_CODE_Msk /*!< Mailbox Code */
+
+#define CAN_TSR_TME_Pos (26U)
+#define CAN_TSR_TME_Msk (0x7U << CAN_TSR_TME_Pos) /*!< 0x1C000000 */
+#define CAN_TSR_TME CAN_TSR_TME_Msk /*!< TME[2:0] bits */
+#define CAN_TSR_TME0_Pos (26U)
+#define CAN_TSR_TME0_Msk (0x1U << CAN_TSR_TME0_Pos) /*!< 0x04000000 */
+#define CAN_TSR_TME0 CAN_TSR_TME0_Msk /*!< Transmit Mailbox 0 Empty */
+#define CAN_TSR_TME1_Pos (27U)
+#define CAN_TSR_TME1_Msk (0x1U << CAN_TSR_TME1_Pos) /*!< 0x08000000 */
+#define CAN_TSR_TME1 CAN_TSR_TME1_Msk /*!< Transmit Mailbox 1 Empty */
+#define CAN_TSR_TME2_Pos (28U)
+#define CAN_TSR_TME2_Msk (0x1U << CAN_TSR_TME2_Pos) /*!< 0x10000000 */
+#define CAN_TSR_TME2 CAN_TSR_TME2_Msk /*!< Transmit Mailbox 2 Empty */
+
+#define CAN_TSR_LOW_Pos (29U)
+#define CAN_TSR_LOW_Msk (0x7U << CAN_TSR_LOW_Pos) /*!< 0xE0000000 */
+#define CAN_TSR_LOW CAN_TSR_LOW_Msk /*!< LOW[2:0] bits */
+#define CAN_TSR_LOW0_Pos (29U)
+#define CAN_TSR_LOW0_Msk (0x1U << CAN_TSR_LOW0_Pos) /*!< 0x20000000 */
+#define CAN_TSR_LOW0 CAN_TSR_LOW0_Msk /*!< Lowest Priority Flag for Mailbox 0 */
+#define CAN_TSR_LOW1_Pos (30U)
+#define CAN_TSR_LOW1_Msk (0x1U << CAN_TSR_LOW1_Pos) /*!< 0x40000000 */
+#define CAN_TSR_LOW1 CAN_TSR_LOW1_Msk /*!< Lowest Priority Flag for Mailbox 1 */
+#define CAN_TSR_LOW2_Pos (31U)
+#define CAN_TSR_LOW2_Msk (0x1U << CAN_TSR_LOW2_Pos) /*!< 0x80000000 */
+#define CAN_TSR_LOW2 CAN_TSR_LOW2_Msk /*!< Lowest Priority Flag for Mailbox 2 */
+
+/******************* Bit definition for CAN_RF0R register *******************/
+#define CAN_RF0R_FMP0_Pos (0U)
+#define CAN_RF0R_FMP0_Msk (0x3U << CAN_RF0R_FMP0_Pos) /*!< 0x00000003 */
+#define CAN_RF0R_FMP0 CAN_RF0R_FMP0_Msk /*!< FIFO 0 Message Pending */
+#define CAN_RF0R_FULL0_Pos (3U)
+#define CAN_RF0R_FULL0_Msk (0x1U << CAN_RF0R_FULL0_Pos) /*!< 0x00000008 */
+#define CAN_RF0R_FULL0 CAN_RF0R_FULL0_Msk /*!< FIFO 0 Full */
+#define CAN_RF0R_FOVR0_Pos (4U)
+#define CAN_RF0R_FOVR0_Msk (0x1U << CAN_RF0R_FOVR0_Pos) /*!< 0x00000010 */
+#define CAN_RF0R_FOVR0 CAN_RF0R_FOVR0_Msk /*!< FIFO 0 Overrun */
+#define CAN_RF0R_RFOM0_Pos (5U)
+#define CAN_RF0R_RFOM0_Msk (0x1U << CAN_RF0R_RFOM0_Pos) /*!< 0x00000020 */
+#define CAN_RF0R_RFOM0 CAN_RF0R_RFOM0_Msk /*!< Release FIFO 0 Output Mailbox */
+
+/******************* Bit definition for CAN_RF1R register *******************/
+#define CAN_RF1R_FMP1_Pos (0U)
+#define CAN_RF1R_FMP1_Msk (0x3U << CAN_RF1R_FMP1_Pos) /*!< 0x00000003 */
+#define CAN_RF1R_FMP1 CAN_RF1R_FMP1_Msk /*!< FIFO 1 Message Pending */
+#define CAN_RF1R_FULL1_Pos (3U)
+#define CAN_RF1R_FULL1_Msk (0x1U << CAN_RF1R_FULL1_Pos) /*!< 0x00000008 */
+#define CAN_RF1R_FULL1 CAN_RF1R_FULL1_Msk /*!< FIFO 1 Full */
+#define CAN_RF1R_FOVR1_Pos (4U)
+#define CAN_RF1R_FOVR1_Msk (0x1U << CAN_RF1R_FOVR1_Pos) /*!< 0x00000010 */
+#define CAN_RF1R_FOVR1 CAN_RF1R_FOVR1_Msk /*!< FIFO 1 Overrun */
+#define CAN_RF1R_RFOM1_Pos (5U)
+#define CAN_RF1R_RFOM1_Msk (0x1U << CAN_RF1R_RFOM1_Pos) /*!< 0x00000020 */
+#define CAN_RF1R_RFOM1 CAN_RF1R_RFOM1_Msk /*!< Release FIFO 1 Output Mailbox */
+
+/******************** Bit definition for CAN_IER register *******************/
+#define CAN_IER_TMEIE_Pos (0U)
+#define CAN_IER_TMEIE_Msk (0x1U << CAN_IER_TMEIE_Pos) /*!< 0x00000001 */
+#define CAN_IER_TMEIE CAN_IER_TMEIE_Msk /*!< Transmit Mailbox Empty Interrupt Enable */
+#define CAN_IER_FMPIE0_Pos (1U)
+#define CAN_IER_FMPIE0_Msk (0x1U << CAN_IER_FMPIE0_Pos) /*!< 0x00000002 */
+#define CAN_IER_FMPIE0 CAN_IER_FMPIE0_Msk /*!< FIFO Message Pending Interrupt Enable */
+#define CAN_IER_FFIE0_Pos (2U)
+#define CAN_IER_FFIE0_Msk (0x1U << CAN_IER_FFIE0_Pos) /*!< 0x00000004 */
+#define CAN_IER_FFIE0 CAN_IER_FFIE0_Msk /*!< FIFO Full Interrupt Enable */
+#define CAN_IER_FOVIE0_Pos (3U)
+#define CAN_IER_FOVIE0_Msk (0x1U << CAN_IER_FOVIE0_Pos) /*!< 0x00000008 */
+#define CAN_IER_FOVIE0 CAN_IER_FOVIE0_Msk /*!< FIFO Overrun Interrupt Enable */
+#define CAN_IER_FMPIE1_Pos (4U)
+#define CAN_IER_FMPIE1_Msk (0x1U << CAN_IER_FMPIE1_Pos) /*!< 0x00000010 */
+#define CAN_IER_FMPIE1 CAN_IER_FMPIE1_Msk /*!< FIFO Message Pending Interrupt Enable */
+#define CAN_IER_FFIE1_Pos (5U)
+#define CAN_IER_FFIE1_Msk (0x1U << CAN_IER_FFIE1_Pos) /*!< 0x00000020 */
+#define CAN_IER_FFIE1 CAN_IER_FFIE1_Msk /*!< FIFO Full Interrupt Enable */
+#define CAN_IER_FOVIE1_Pos (6U)
+#define CAN_IER_FOVIE1_Msk (0x1U << CAN_IER_FOVIE1_Pos) /*!< 0x00000040 */
+#define CAN_IER_FOVIE1 CAN_IER_FOVIE1_Msk /*!< FIFO Overrun Interrupt Enable */
+#define CAN_IER_EWGIE_Pos (8U)
+#define CAN_IER_EWGIE_Msk (0x1U << CAN_IER_EWGIE_Pos) /*!< 0x00000100 */
+#define CAN_IER_EWGIE CAN_IER_EWGIE_Msk /*!< Error Warning Interrupt Enable */
+#define CAN_IER_EPVIE_Pos (9U)
+#define CAN_IER_EPVIE_Msk (0x1U << CAN_IER_EPVIE_Pos) /*!< 0x00000200 */
+#define CAN_IER_EPVIE CAN_IER_EPVIE_Msk /*!< Error Passive Interrupt Enable */
+#define CAN_IER_BOFIE_Pos (10U)
+#define CAN_IER_BOFIE_Msk (0x1U << CAN_IER_BOFIE_Pos) /*!< 0x00000400 */
+#define CAN_IER_BOFIE CAN_IER_BOFIE_Msk /*!< Bus-Off Interrupt Enable */
+#define CAN_IER_LECIE_Pos (11U)
+#define CAN_IER_LECIE_Msk (0x1U << CAN_IER_LECIE_Pos) /*!< 0x00000800 */
+#define CAN_IER_LECIE CAN_IER_LECIE_Msk /*!< Last Error Code Interrupt Enable */
+#define CAN_IER_ERRIE_Pos (15U)
+#define CAN_IER_ERRIE_Msk (0x1U << CAN_IER_ERRIE_Pos) /*!< 0x00008000 */
+#define CAN_IER_ERRIE CAN_IER_ERRIE_Msk /*!< Error Interrupt Enable */
+#define CAN_IER_WKUIE_Pos (16U)
+#define CAN_IER_WKUIE_Msk (0x1U << CAN_IER_WKUIE_Pos) /*!< 0x00010000 */
+#define CAN_IER_WKUIE CAN_IER_WKUIE_Msk /*!< Wakeup Interrupt Enable */
+#define CAN_IER_SLKIE_Pos (17U)
+#define CAN_IER_SLKIE_Msk (0x1U << CAN_IER_SLKIE_Pos) /*!< 0x00020000 */
+#define CAN_IER_SLKIE CAN_IER_SLKIE_Msk /*!< Sleep Interrupt Enable */
+
+/******************** Bit definition for CAN_ESR register *******************/
+#define CAN_ESR_EWGF_Pos (0U)
+#define CAN_ESR_EWGF_Msk (0x1U << CAN_ESR_EWGF_Pos) /*!< 0x00000001 */
+#define CAN_ESR_EWGF CAN_ESR_EWGF_Msk /*!< Error Warning Flag */
+#define CAN_ESR_EPVF_Pos (1U)
+#define CAN_ESR_EPVF_Msk (0x1U << CAN_ESR_EPVF_Pos) /*!< 0x00000002 */
+#define CAN_ESR_EPVF CAN_ESR_EPVF_Msk /*!< Error Passive Flag */
+#define CAN_ESR_BOFF_Pos (2U)
+#define CAN_ESR_BOFF_Msk (0x1U << CAN_ESR_BOFF_Pos) /*!< 0x00000004 */
+#define CAN_ESR_BOFF CAN_ESR_BOFF_Msk /*!< Bus-Off Flag */
+
+#define CAN_ESR_LEC_Pos (4U)
+#define CAN_ESR_LEC_Msk (0x7U << CAN_ESR_LEC_Pos) /*!< 0x00000070 */
+#define CAN_ESR_LEC CAN_ESR_LEC_Msk /*!< LEC[2:0] bits (Last Error Code) */
+#define CAN_ESR_LEC_0 (0x1U << CAN_ESR_LEC_Pos) /*!< 0x00000010 */
+#define CAN_ESR_LEC_1 (0x2U << CAN_ESR_LEC_Pos) /*!< 0x00000020 */
+#define CAN_ESR_LEC_2 (0x4U << CAN_ESR_LEC_Pos) /*!< 0x00000040 */
+
+#define CAN_ESR_TEC_Pos (16U)
+#define CAN_ESR_TEC_Msk (0xFFU << CAN_ESR_TEC_Pos) /*!< 0x00FF0000 */
+#define CAN_ESR_TEC CAN_ESR_TEC_Msk /*!< Least significant byte of the 9-bit Transmit Error Counter */
+#define CAN_ESR_REC_Pos (24U)
+#define CAN_ESR_REC_Msk (0xFFU << CAN_ESR_REC_Pos) /*!< 0xFF000000 */
+#define CAN_ESR_REC CAN_ESR_REC_Msk /*!< Receive Error Counter */
+
+/******************* Bit definition for CAN_BTR register ********************/
+#define CAN_BTR_BRP_Pos (0U)
+#define CAN_BTR_BRP_Msk (0x3FFU << CAN_BTR_BRP_Pos) /*!< 0x000003FF */
+#define CAN_BTR_BRP CAN_BTR_BRP_Msk /*!<Baud Rate Prescaler */
+#define CAN_BTR_TS1_Pos (16U)
+#define CAN_BTR_TS1_Msk (0xFU << CAN_BTR_TS1_Pos) /*!< 0x000F0000 */
+#define CAN_BTR_TS1 CAN_BTR_TS1_Msk /*!<Time Segment 1 */
+#define CAN_BTR_TS1_0 (0x1U << CAN_BTR_TS1_Pos) /*!< 0x00010000 */
+#define CAN_BTR_TS1_1 (0x2U << CAN_BTR_TS1_Pos) /*!< 0x00020000 */
+#define CAN_BTR_TS1_2 (0x4U << CAN_BTR_TS1_Pos) /*!< 0x00040000 */
+#define CAN_BTR_TS1_3 (0x8U << CAN_BTR_TS1_Pos) /*!< 0x00080000 */
+#define CAN_BTR_TS2_Pos (20U)
+#define CAN_BTR_TS2_Msk (0x7U << CAN_BTR_TS2_Pos) /*!< 0x00700000 */
+#define CAN_BTR_TS2 CAN_BTR_TS2_Msk /*!<Time Segment 2 */
+#define CAN_BTR_TS2_0 (0x1U << CAN_BTR_TS2_Pos) /*!< 0x00100000 */
+#define CAN_BTR_TS2_1 (0x2U << CAN_BTR_TS2_Pos) /*!< 0x00200000 */
+#define CAN_BTR_TS2_2 (0x4U << CAN_BTR_TS2_Pos) /*!< 0x00400000 */
+#define CAN_BTR_SJW_Pos (24U)
+#define CAN_BTR_SJW_Msk (0x3U << CAN_BTR_SJW_Pos) /*!< 0x03000000 */
+#define CAN_BTR_SJW CAN_BTR_SJW_Msk /*!<Resynchronization Jump Width */
+#define CAN_BTR_SJW_0 (0x1U << CAN_BTR_SJW_Pos) /*!< 0x01000000 */
+#define CAN_BTR_SJW_1 (0x2U << CAN_BTR_SJW_Pos) /*!< 0x02000000 */
+#define CAN_BTR_LBKM_Pos (30U)
+#define CAN_BTR_LBKM_Msk (0x1U << CAN_BTR_LBKM_Pos) /*!< 0x40000000 */
+#define CAN_BTR_LBKM CAN_BTR_LBKM_Msk /*!<Loop Back Mode (Debug) */
+#define CAN_BTR_SILM_Pos (31U)
+#define CAN_BTR_SILM_Msk (0x1U << CAN_BTR_SILM_Pos) /*!< 0x80000000 */
+#define CAN_BTR_SILM CAN_BTR_SILM_Msk /*!<Silent Mode */
+
+/*!< Mailbox registers */
+/****************** Bit definition for CAN_TI0R register ********************/
+#define CAN_TI0R_TXRQ_Pos (0U)
+#define CAN_TI0R_TXRQ_Msk (0x1U << CAN_TI0R_TXRQ_Pos) /*!< 0x00000001 */
+#define CAN_TI0R_TXRQ CAN_TI0R_TXRQ_Msk /*!< Transmit Mailbox Request */
+#define CAN_TI0R_RTR_Pos (1U)
+#define CAN_TI0R_RTR_Msk (0x1U << CAN_TI0R_RTR_Pos) /*!< 0x00000002 */
+#define CAN_TI0R_RTR CAN_TI0R_RTR_Msk /*!< Remote Transmission Request */
+#define CAN_TI0R_IDE_Pos (2U)
+#define CAN_TI0R_IDE_Msk (0x1U << CAN_TI0R_IDE_Pos) /*!< 0x00000004 */
+#define CAN_TI0R_IDE CAN_TI0R_IDE_Msk /*!< Identifier Extension */
+#define CAN_TI0R_EXID_Pos (3U)
+#define CAN_TI0R_EXID_Msk (0x3FFFFU << CAN_TI0R_EXID_Pos) /*!< 0x001FFFF8 */
+#define CAN_TI0R_EXID CAN_TI0R_EXID_Msk /*!< Extended Identifier */
+#define CAN_TI0R_STID_Pos (21U)
+#define CAN_TI0R_STID_Msk (0x7FFU << CAN_TI0R_STID_Pos) /*!< 0xFFE00000 */
+#define CAN_TI0R_STID CAN_TI0R_STID_Msk /*!< Standard Identifier or Extended Identifier */
+
+/****************** Bit definition for CAN_TDT0R register *******************/
+#define CAN_TDT0R_DLC_Pos (0U)
+#define CAN_TDT0R_DLC_Msk (0xFU << CAN_TDT0R_DLC_Pos) /*!< 0x0000000F */
+#define CAN_TDT0R_DLC CAN_TDT0R_DLC_Msk /*!< Data Length Code */
+#define CAN_TDT0R_TGT_Pos (8U)
+#define CAN_TDT0R_TGT_Msk (0x1U << CAN_TDT0R_TGT_Pos) /*!< 0x00000100 */
+#define CAN_TDT0R_TGT CAN_TDT0R_TGT_Msk /*!< Transmit Global Time */
+#define CAN_TDT0R_TIME_Pos (16U)
+#define CAN_TDT0R_TIME_Msk (0xFFFFU << CAN_TDT0R_TIME_Pos) /*!< 0xFFFF0000 */
+#define CAN_TDT0R_TIME CAN_TDT0R_TIME_Msk /*!< Message Time Stamp */
+
+/****************** Bit definition for CAN_TDL0R register *******************/
+#define CAN_TDL0R_DATA0_Pos (0U)
+#define CAN_TDL0R_DATA0_Msk (0xFFU << CAN_TDL0R_DATA0_Pos) /*!< 0x000000FF */
+#define CAN_TDL0R_DATA0 CAN_TDL0R_DATA0_Msk /*!< Data byte 0 */
+#define CAN_TDL0R_DATA1_Pos (8U)
+#define CAN_TDL0R_DATA1_Msk (0xFFU << CAN_TDL0R_DATA1_Pos) /*!< 0x0000FF00 */
+#define CAN_TDL0R_DATA1 CAN_TDL0R_DATA1_Msk /*!< Data byte 1 */
+#define CAN_TDL0R_DATA2_Pos (16U)
+#define CAN_TDL0R_DATA2_Msk (0xFFU << CAN_TDL0R_DATA2_Pos) /*!< 0x00FF0000 */
+#define CAN_TDL0R_DATA2 CAN_TDL0R_DATA2_Msk /*!< Data byte 2 */
+#define CAN_TDL0R_DATA3_Pos (24U)
+#define CAN_TDL0R_DATA3_Msk (0xFFU << CAN_TDL0R_DATA3_Pos) /*!< 0xFF000000 */
+#define CAN_TDL0R_DATA3 CAN_TDL0R_DATA3_Msk /*!< Data byte 3 */
+
+/****************** Bit definition for CAN_TDH0R register *******************/
+#define CAN_TDH0R_DATA4_Pos (0U)
+#define CAN_TDH0R_DATA4_Msk (0xFFU << CAN_TDH0R_DATA4_Pos) /*!< 0x000000FF */
+#define CAN_TDH0R_DATA4 CAN_TDH0R_DATA4_Msk /*!< Data byte 4 */
+#define CAN_TDH0R_DATA5_Pos (8U)
+#define CAN_TDH0R_DATA5_Msk (0xFFU << CAN_TDH0R_DATA5_Pos) /*!< 0x0000FF00 */
+#define CAN_TDH0R_DATA5 CAN_TDH0R_DATA5_Msk /*!< Data byte 5 */
+#define CAN_TDH0R_DATA6_Pos (16U)
+#define CAN_TDH0R_DATA6_Msk (0xFFU << CAN_TDH0R_DATA6_Pos) /*!< 0x00FF0000 */
+#define CAN_TDH0R_DATA6 CAN_TDH0R_DATA6_Msk /*!< Data byte 6 */
+#define CAN_TDH0R_DATA7_Pos (24U)
+#define CAN_TDH0R_DATA7_Msk (0xFFU << CAN_TDH0R_DATA7_Pos) /*!< 0xFF000000 */
+#define CAN_TDH0R_DATA7 CAN_TDH0R_DATA7_Msk /*!< Data byte 7 */
+
+/******************* Bit definition for CAN_TI1R register *******************/
+#define CAN_TI1R_TXRQ_Pos (0U)
+#define CAN_TI1R_TXRQ_Msk (0x1U << CAN_TI1R_TXRQ_Pos) /*!< 0x00000001 */
+#define CAN_TI1R_TXRQ CAN_TI1R_TXRQ_Msk /*!< Transmit Mailbox Request */
+#define CAN_TI1R_RTR_Pos (1U)
+#define CAN_TI1R_RTR_Msk (0x1U << CAN_TI1R_RTR_Pos) /*!< 0x00000002 */
+#define CAN_TI1R_RTR CAN_TI1R_RTR_Msk /*!< Remote Transmission Request */
+#define CAN_TI1R_IDE_Pos (2U)
+#define CAN_TI1R_IDE_Msk (0x1U << CAN_TI1R_IDE_Pos) /*!< 0x00000004 */
+#define CAN_TI1R_IDE CAN_TI1R_IDE_Msk /*!< Identifier Extension */
+#define CAN_TI1R_EXID_Pos (3U)
+#define CAN_TI1R_EXID_Msk (0x3FFFFU << CAN_TI1R_EXID_Pos) /*!< 0x001FFFF8 */
+#define CAN_TI1R_EXID CAN_TI1R_EXID_Msk /*!< Extended Identifier */
+#define CAN_TI1R_STID_Pos (21U)
+#define CAN_TI1R_STID_Msk (0x7FFU << CAN_TI1R_STID_Pos) /*!< 0xFFE00000 */
+#define CAN_TI1R_STID CAN_TI1R_STID_Msk /*!< Standard Identifier or Extended Identifier */
+
+/******************* Bit definition for CAN_TDT1R register ******************/
+#define CAN_TDT1R_DLC_Pos (0U)
+#define CAN_TDT1R_DLC_Msk (0xFU << CAN_TDT1R_DLC_Pos) /*!< 0x0000000F */
+#define CAN_TDT1R_DLC CAN_TDT1R_DLC_Msk /*!< Data Length Code */
+#define CAN_TDT1R_TGT_Pos (8U)
+#define CAN_TDT1R_TGT_Msk (0x1U << CAN_TDT1R_TGT_Pos) /*!< 0x00000100 */
+#define CAN_TDT1R_TGT CAN_TDT1R_TGT_Msk /*!< Transmit Global Time */
+#define CAN_TDT1R_TIME_Pos (16U)
+#define CAN_TDT1R_TIME_Msk (0xFFFFU << CAN_TDT1R_TIME_Pos) /*!< 0xFFFF0000 */
+#define CAN_TDT1R_TIME CAN_TDT1R_TIME_Msk /*!< Message Time Stamp */
+
+/******************* Bit definition for CAN_TDL1R register ******************/
+#define CAN_TDL1R_DATA0_Pos (0U)
+#define CAN_TDL1R_DATA0_Msk (0xFFU << CAN_TDL1R_DATA0_Pos) /*!< 0x000000FF */
+#define CAN_TDL1R_DATA0 CAN_TDL1R_DATA0_Msk /*!< Data byte 0 */
+#define CAN_TDL1R_DATA1_Pos (8U)
+#define CAN_TDL1R_DATA1_Msk (0xFFU << CAN_TDL1R_DATA1_Pos) /*!< 0x0000FF00 */
+#define CAN_TDL1R_DATA1 CAN_TDL1R_DATA1_Msk /*!< Data byte 1 */
+#define CAN_TDL1R_DATA2_Pos (16U)
+#define CAN_TDL1R_DATA2_Msk (0xFFU << CAN_TDL1R_DATA2_Pos) /*!< 0x00FF0000 */
+#define CAN_TDL1R_DATA2 CAN_TDL1R_DATA2_Msk /*!< Data byte 2 */
+#define CAN_TDL1R_DATA3_Pos (24U)
+#define CAN_TDL1R_DATA3_Msk (0xFFU << CAN_TDL1R_DATA3_Pos) /*!< 0xFF000000 */
+#define CAN_TDL1R_DATA3 CAN_TDL1R_DATA3_Msk /*!< Data byte 3 */
+
+/******************* Bit definition for CAN_TDH1R register ******************/
+#define CAN_TDH1R_DATA4_Pos (0U)
+#define CAN_TDH1R_DATA4_Msk (0xFFU << CAN_TDH1R_DATA4_Pos) /*!< 0x000000FF */
+#define CAN_TDH1R_DATA4 CAN_TDH1R_DATA4_Msk /*!< Data byte 4 */
+#define CAN_TDH1R_DATA5_Pos (8U)
+#define CAN_TDH1R_DATA5_Msk (0xFFU << CAN_TDH1R_DATA5_Pos) /*!< 0x0000FF00 */
+#define CAN_TDH1R_DATA5 CAN_TDH1R_DATA5_Msk /*!< Data byte 5 */
+#define CAN_TDH1R_DATA6_Pos (16U)
+#define CAN_TDH1R_DATA6_Msk (0xFFU << CAN_TDH1R_DATA6_Pos) /*!< 0x00FF0000 */
+#define CAN_TDH1R_DATA6 CAN_TDH1R_DATA6_Msk /*!< Data byte 6 */
+#define CAN_TDH1R_DATA7_Pos (24U)
+#define CAN_TDH1R_DATA7_Msk (0xFFU << CAN_TDH1R_DATA7_Pos) /*!< 0xFF000000 */
+#define CAN_TDH1R_DATA7 CAN_TDH1R_DATA7_Msk /*!< Data byte 7 */
+
+/******************* Bit definition for CAN_TI2R register *******************/
+#define CAN_TI2R_TXRQ_Pos (0U)
+#define CAN_TI2R_TXRQ_Msk (0x1U << CAN_TI2R_TXRQ_Pos) /*!< 0x00000001 */
+#define CAN_TI2R_TXRQ CAN_TI2R_TXRQ_Msk /*!< Transmit Mailbox Request */
+#define CAN_TI2R_RTR_Pos (1U)
+#define CAN_TI2R_RTR_Msk (0x1U << CAN_TI2R_RTR_Pos) /*!< 0x00000002 */
+#define CAN_TI2R_RTR CAN_TI2R_RTR_Msk /*!< Remote Transmission Request */
+#define CAN_TI2R_IDE_Pos (2U)
+#define CAN_TI2R_IDE_Msk (0x1U << CAN_TI2R_IDE_Pos) /*!< 0x00000004 */
+#define CAN_TI2R_IDE CAN_TI2R_IDE_Msk /*!< Identifier Extension */
+#define CAN_TI2R_EXID_Pos (3U)
+#define CAN_TI2R_EXID_Msk (0x3FFFFU << CAN_TI2R_EXID_Pos) /*!< 0x001FFFF8 */
+#define CAN_TI2R_EXID CAN_TI2R_EXID_Msk /*!< Extended identifier */
+#define CAN_TI2R_STID_Pos (21U)
+#define CAN_TI2R_STID_Msk (0x7FFU << CAN_TI2R_STID_Pos) /*!< 0xFFE00000 */
+#define CAN_TI2R_STID CAN_TI2R_STID_Msk /*!< Standard Identifier or Extended Identifier */
+
+/******************* Bit definition for CAN_TDT2R register ******************/
+#define CAN_TDT2R_DLC_Pos (0U)
+#define CAN_TDT2R_DLC_Msk (0xFU << CAN_TDT2R_DLC_Pos) /*!< 0x0000000F */
+#define CAN_TDT2R_DLC CAN_TDT2R_DLC_Msk /*!< Data Length Code */
+#define CAN_TDT2R_TGT_Pos (8U)
+#define CAN_TDT2R_TGT_Msk (0x1U << CAN_TDT2R_TGT_Pos) /*!< 0x00000100 */
+#define CAN_TDT2R_TGT CAN_TDT2R_TGT_Msk /*!< Transmit Global Time */
+#define CAN_TDT2R_TIME_Pos (16U)
+#define CAN_TDT2R_TIME_Msk (0xFFFFU << CAN_TDT2R_TIME_Pos) /*!< 0xFFFF0000 */
+#define CAN_TDT2R_TIME CAN_TDT2R_TIME_Msk /*!< Message Time Stamp */
+
+/******************* Bit definition for CAN_TDL2R register ******************/
+#define CAN_TDL2R_DATA0_Pos (0U)
+#define CAN_TDL2R_DATA0_Msk (0xFFU << CAN_TDL2R_DATA0_Pos) /*!< 0x000000FF */
+#define CAN_TDL2R_DATA0 CAN_TDL2R_DATA0_Msk /*!< Data byte 0 */
+#define CAN_TDL2R_DATA1_Pos (8U)
+#define CAN_TDL2R_DATA1_Msk (0xFFU << CAN_TDL2R_DATA1_Pos) /*!< 0x0000FF00 */
+#define CAN_TDL2R_DATA1 CAN_TDL2R_DATA1_Msk /*!< Data byte 1 */
+#define CAN_TDL2R_DATA2_Pos (16U)
+#define CAN_TDL2R_DATA2_Msk (0xFFU << CAN_TDL2R_DATA2_Pos) /*!< 0x00FF0000 */
+#define CAN_TDL2R_DATA2 CAN_TDL2R_DATA2_Msk /*!< Data byte 2 */
+#define CAN_TDL2R_DATA3_Pos (24U)
+#define CAN_TDL2R_DATA3_Msk (0xFFU << CAN_TDL2R_DATA3_Pos) /*!< 0xFF000000 */
+#define CAN_TDL2R_DATA3 CAN_TDL2R_DATA3_Msk /*!< Data byte 3 */
+
+/******************* Bit definition for CAN_TDH2R register ******************/
+#define CAN_TDH2R_DATA4_Pos (0U)
+#define CAN_TDH2R_DATA4_Msk (0xFFU << CAN_TDH2R_DATA4_Pos) /*!< 0x000000FF */
+#define CAN_TDH2R_DATA4 CAN_TDH2R_DATA4_Msk /*!< Data byte 4 */
+#define CAN_TDH2R_DATA5_Pos (8U)
+#define CAN_TDH2R_DATA5_Msk (0xFFU << CAN_TDH2R_DATA5_Pos) /*!< 0x0000FF00 */
+#define CAN_TDH2R_DATA5 CAN_TDH2R_DATA5_Msk /*!< Data byte 5 */
+#define CAN_TDH2R_DATA6_Pos (16U)
+#define CAN_TDH2R_DATA6_Msk (0xFFU << CAN_TDH2R_DATA6_Pos) /*!< 0x00FF0000 */
+#define CAN_TDH2R_DATA6 CAN_TDH2R_DATA6_Msk /*!< Data byte 6 */
+#define CAN_TDH2R_DATA7_Pos (24U)
+#define CAN_TDH2R_DATA7_Msk (0xFFU << CAN_TDH2R_DATA7_Pos) /*!< 0xFF000000 */
+#define CAN_TDH2R_DATA7 CAN_TDH2R_DATA7_Msk /*!< Data byte 7 */
+
+/******************* Bit definition for CAN_RI0R register *******************/
+#define CAN_RI0R_RTR_Pos (1U)
+#define CAN_RI0R_RTR_Msk (0x1U << CAN_RI0R_RTR_Pos) /*!< 0x00000002 */
+#define CAN_RI0R_RTR CAN_RI0R_RTR_Msk /*!< Remote Transmission Request */
+#define CAN_RI0R_IDE_Pos (2U)
+#define CAN_RI0R_IDE_Msk (0x1U << CAN_RI0R_IDE_Pos) /*!< 0x00000004 */
+#define CAN_RI0R_IDE CAN_RI0R_IDE_Msk /*!< Identifier Extension */
+#define CAN_RI0R_EXID_Pos (3U)
+#define CAN_RI0R_EXID_Msk (0x3FFFFU << CAN_RI0R_EXID_Pos) /*!< 0x001FFFF8 */
+#define CAN_RI0R_EXID CAN_RI0R_EXID_Msk /*!< Extended Identifier */
+#define CAN_RI0R_STID_Pos (21U)
+#define CAN_RI0R_STID_Msk (0x7FFU << CAN_RI0R_STID_Pos) /*!< 0xFFE00000 */
+#define CAN_RI0R_STID CAN_RI0R_STID_Msk /*!< Standard Identifier or Extended Identifier */
+
+/******************* Bit definition for CAN_RDT0R register ******************/
+#define CAN_RDT0R_DLC_Pos (0U)
+#define CAN_RDT0R_DLC_Msk (0xFU << CAN_RDT0R_DLC_Pos) /*!< 0x0000000F */
+#define CAN_RDT0R_DLC CAN_RDT0R_DLC_Msk /*!< Data Length Code */
+#define CAN_RDT0R_FMI_Pos (8U)
+#define CAN_RDT0R_FMI_Msk (0xFFU << CAN_RDT0R_FMI_Pos) /*!< 0x0000FF00 */
+#define CAN_RDT0R_FMI CAN_RDT0R_FMI_Msk /*!< Filter Match Index */
+#define CAN_RDT0R_TIME_Pos (16U)
+#define CAN_RDT0R_TIME_Msk (0xFFFFU << CAN_RDT0R_TIME_Pos) /*!< 0xFFFF0000 */
+#define CAN_RDT0R_TIME CAN_RDT0R_TIME_Msk /*!< Message Time Stamp */
+
+/******************* Bit definition for CAN_RDL0R register ******************/
+#define CAN_RDL0R_DATA0_Pos (0U)
+#define CAN_RDL0R_DATA0_Msk (0xFFU << CAN_RDL0R_DATA0_Pos) /*!< 0x000000FF */
+#define CAN_RDL0R_DATA0 CAN_RDL0R_DATA0_Msk /*!< Data byte 0 */
+#define CAN_RDL0R_DATA1_Pos (8U)
+#define CAN_RDL0R_DATA1_Msk (0xFFU << CAN_RDL0R_DATA1_Pos) /*!< 0x0000FF00 */
+#define CAN_RDL0R_DATA1 CAN_RDL0R_DATA1_Msk /*!< Data byte 1 */
+#define CAN_RDL0R_DATA2_Pos (16U)
+#define CAN_RDL0R_DATA2_Msk (0xFFU << CAN_RDL0R_DATA2_Pos) /*!< 0x00FF0000 */
+#define CAN_RDL0R_DATA2 CAN_RDL0R_DATA2_Msk /*!< Data byte 2 */
+#define CAN_RDL0R_DATA3_Pos (24U)
+#define CAN_RDL0R_DATA3_Msk (0xFFU << CAN_RDL0R_DATA3_Pos) /*!< 0xFF000000 */
+#define CAN_RDL0R_DATA3 CAN_RDL0R_DATA3_Msk /*!< Data byte 3 */
+
+/******************* Bit definition for CAN_RDH0R register ******************/
+#define CAN_RDH0R_DATA4_Pos (0U)
+#define CAN_RDH0R_DATA4_Msk (0xFFU << CAN_RDH0R_DATA4_Pos) /*!< 0x000000FF */
+#define CAN_RDH0R_DATA4 CAN_RDH0R_DATA4_Msk /*!< Data byte 4 */
+#define CAN_RDH0R_DATA5_Pos (8U)
+#define CAN_RDH0R_DATA5_Msk (0xFFU << CAN_RDH0R_DATA5_Pos) /*!< 0x0000FF00 */
+#define CAN_RDH0R_DATA5 CAN_RDH0R_DATA5_Msk /*!< Data byte 5 */
+#define CAN_RDH0R_DATA6_Pos (16U)
+#define CAN_RDH0R_DATA6_Msk (0xFFU << CAN_RDH0R_DATA6_Pos) /*!< 0x00FF0000 */
+#define CAN_RDH0R_DATA6 CAN_RDH0R_DATA6_Msk /*!< Data byte 6 */
+#define CAN_RDH0R_DATA7_Pos (24U)
+#define CAN_RDH0R_DATA7_Msk (0xFFU << CAN_RDH0R_DATA7_Pos) /*!< 0xFF000000 */
+#define CAN_RDH0R_DATA7 CAN_RDH0R_DATA7_Msk /*!< Data byte 7 */
+
+/******************* Bit definition for CAN_RI1R register *******************/
+#define CAN_RI1R_RTR_Pos (1U)
+#define CAN_RI1R_RTR_Msk (0x1U << CAN_RI1R_RTR_Pos) /*!< 0x00000002 */
+#define CAN_RI1R_RTR CAN_RI1R_RTR_Msk /*!< Remote Transmission Request */
+#define CAN_RI1R_IDE_Pos (2U)
+#define CAN_RI1R_IDE_Msk (0x1U << CAN_RI1R_IDE_Pos) /*!< 0x00000004 */
+#define CAN_RI1R_IDE CAN_RI1R_IDE_Msk /*!< Identifier Extension */
+#define CAN_RI1R_EXID_Pos (3U)
+#define CAN_RI1R_EXID_Msk (0x3FFFFU << CAN_RI1R_EXID_Pos) /*!< 0x001FFFF8 */
+#define CAN_RI1R_EXID CAN_RI1R_EXID_Msk /*!< Extended identifier */
+#define CAN_RI1R_STID_Pos (21U)
+#define CAN_RI1R_STID_Msk (0x7FFU << CAN_RI1R_STID_Pos) /*!< 0xFFE00000 */
+#define CAN_RI1R_STID CAN_RI1R_STID_Msk /*!< Standard Identifier or Extended Identifier */
+
+/******************* Bit definition for CAN_RDT1R register ******************/
+#define CAN_RDT1R_DLC_Pos (0U)
+#define CAN_RDT1R_DLC_Msk (0xFU << CAN_RDT1R_DLC_Pos) /*!< 0x0000000F */
+#define CAN_RDT1R_DLC CAN_RDT1R_DLC_Msk /*!< Data Length Code */
+#define CAN_RDT1R_FMI_Pos (8U)
+#define CAN_RDT1R_FMI_Msk (0xFFU << CAN_RDT1R_FMI_Pos) /*!< 0x0000FF00 */
+#define CAN_RDT1R_FMI CAN_RDT1R_FMI_Msk /*!< Filter Match Index */
+#define CAN_RDT1R_TIME_Pos (16U)
+#define CAN_RDT1R_TIME_Msk (0xFFFFU << CAN_RDT1R_TIME_Pos) /*!< 0xFFFF0000 */
+#define CAN_RDT1R_TIME CAN_RDT1R_TIME_Msk /*!< Message Time Stamp */
+
+/******************* Bit definition for CAN_RDL1R register ******************/
+#define CAN_RDL1R_DATA0_Pos (0U)
+#define CAN_RDL1R_DATA0_Msk (0xFFU << CAN_RDL1R_DATA0_Pos) /*!< 0x000000FF */
+#define CAN_RDL1R_DATA0 CAN_RDL1R_DATA0_Msk /*!< Data byte 0 */
+#define CAN_RDL1R_DATA1_Pos (8U)
+#define CAN_RDL1R_DATA1_Msk (0xFFU << CAN_RDL1R_DATA1_Pos) /*!< 0x0000FF00 */
+#define CAN_RDL1R_DATA1 CAN_RDL1R_DATA1_Msk /*!< Data byte 1 */
+#define CAN_RDL1R_DATA2_Pos (16U)
+#define CAN_RDL1R_DATA2_Msk (0xFFU << CAN_RDL1R_DATA2_Pos) /*!< 0x00FF0000 */
+#define CAN_RDL1R_DATA2 CAN_RDL1R_DATA2_Msk /*!< Data byte 2 */
+#define CAN_RDL1R_DATA3_Pos (24U)
+#define CAN_RDL1R_DATA3_Msk (0xFFU << CAN_RDL1R_DATA3_Pos) /*!< 0xFF000000 */
+#define CAN_RDL1R_DATA3 CAN_RDL1R_DATA3_Msk /*!< Data byte 3 */
+
+/******************* Bit definition for CAN_RDH1R register ******************/
+#define CAN_RDH1R_DATA4_Pos (0U)
+#define CAN_RDH1R_DATA4_Msk (0xFFU << CAN_RDH1R_DATA4_Pos) /*!< 0x000000FF */
+#define CAN_RDH1R_DATA4 CAN_RDH1R_DATA4_Msk /*!< Data byte 4 */
+#define CAN_RDH1R_DATA5_Pos (8U)
+#define CAN_RDH1R_DATA5_Msk (0xFFU << CAN_RDH1R_DATA5_Pos) /*!< 0x0000FF00 */
+#define CAN_RDH1R_DATA5 CAN_RDH1R_DATA5_Msk /*!< Data byte 5 */
+#define CAN_RDH1R_DATA6_Pos (16U)
+#define CAN_RDH1R_DATA6_Msk (0xFFU << CAN_RDH1R_DATA6_Pos) /*!< 0x00FF0000 */
+#define CAN_RDH1R_DATA6 CAN_RDH1R_DATA6_Msk /*!< Data byte 6 */
+#define CAN_RDH1R_DATA7_Pos (24U)
+#define CAN_RDH1R_DATA7_Msk (0xFFU << CAN_RDH1R_DATA7_Pos) /*!< 0xFF000000 */
+#define CAN_RDH1R_DATA7 CAN_RDH1R_DATA7_Msk /*!< Data byte 7 */
+
+/*!< CAN filter registers */
+/******************* Bit definition for CAN_FMR register ********************/
+#define CAN_FMR_FINIT_Pos (0U)
+#define CAN_FMR_FINIT_Msk (0x1U << CAN_FMR_FINIT_Pos) /*!< 0x00000001 */
+#define CAN_FMR_FINIT CAN_FMR_FINIT_Msk /*!< Filter Init Mode */
+#define CAN_FMR_CAN2SB_Pos (8U)
+#define CAN_FMR_CAN2SB_Msk (0x3FU << CAN_FMR_CAN2SB_Pos) /*!< 0x00003F00 */
+#define CAN_FMR_CAN2SB CAN_FMR_CAN2SB_Msk /*!< CAN2 start bank */
+
+/******************* Bit definition for CAN_FM1R register *******************/
+#define CAN_FM1R_FBM_Pos (0U)
+#define CAN_FM1R_FBM_Msk (0x3FFFU << CAN_FM1R_FBM_Pos) /*!< 0x00003FFF */
+#define CAN_FM1R_FBM CAN_FM1R_FBM_Msk /*!< Filter Mode */
+#define CAN_FM1R_FBM0_Pos (0U)
+#define CAN_FM1R_FBM0_Msk (0x1U << CAN_FM1R_FBM0_Pos) /*!< 0x00000001 */
+#define CAN_FM1R_FBM0 CAN_FM1R_FBM0_Msk /*!< Filter Init Mode for filter 0 */
+#define CAN_FM1R_FBM1_Pos (1U)
+#define CAN_FM1R_FBM1_Msk (0x1U << CAN_FM1R_FBM1_Pos) /*!< 0x00000002 */
+#define CAN_FM1R_FBM1 CAN_FM1R_FBM1_Msk /*!< Filter Init Mode for filter 1 */
+#define CAN_FM1R_FBM2_Pos (2U)
+#define CAN_FM1R_FBM2_Msk (0x1U << CAN_FM1R_FBM2_Pos) /*!< 0x00000004 */
+#define CAN_FM1R_FBM2 CAN_FM1R_FBM2_Msk /*!< Filter Init Mode for filter 2 */
+#define CAN_FM1R_FBM3_Pos (3U)
+#define CAN_FM1R_FBM3_Msk (0x1U << CAN_FM1R_FBM3_Pos) /*!< 0x00000008 */
+#define CAN_FM1R_FBM3 CAN_FM1R_FBM3_Msk /*!< Filter Init Mode for filter 3 */
+#define CAN_FM1R_FBM4_Pos (4U)
+#define CAN_FM1R_FBM4_Msk (0x1U << CAN_FM1R_FBM4_Pos) /*!< 0x00000010 */
+#define CAN_FM1R_FBM4 CAN_FM1R_FBM4_Msk /*!< Filter Init Mode for filter 4 */
+#define CAN_FM1R_FBM5_Pos (5U)
+#define CAN_FM1R_FBM5_Msk (0x1U << CAN_FM1R_FBM5_Pos) /*!< 0x00000020 */
+#define CAN_FM1R_FBM5 CAN_FM1R_FBM5_Msk /*!< Filter Init Mode for filter 5 */
+#define CAN_FM1R_FBM6_Pos (6U)
+#define CAN_FM1R_FBM6_Msk (0x1U << CAN_FM1R_FBM6_Pos) /*!< 0x00000040 */
+#define CAN_FM1R_FBM6 CAN_FM1R_FBM6_Msk /*!< Filter Init Mode for filter 6 */
+#define CAN_FM1R_FBM7_Pos (7U)
+#define CAN_FM1R_FBM7_Msk (0x1U << CAN_FM1R_FBM7_Pos) /*!< 0x00000080 */
+#define CAN_FM1R_FBM7 CAN_FM1R_FBM7_Msk /*!< Filter Init Mode for filter 7 */
+#define CAN_FM1R_FBM8_Pos (8U)
+#define CAN_FM1R_FBM8_Msk (0x1U << CAN_FM1R_FBM8_Pos) /*!< 0x00000100 */
+#define CAN_FM1R_FBM8 CAN_FM1R_FBM8_Msk /*!< Filter Init Mode for filter 8 */
+#define CAN_FM1R_FBM9_Pos (9U)
+#define CAN_FM1R_FBM9_Msk (0x1U << CAN_FM1R_FBM9_Pos) /*!< 0x00000200 */
+#define CAN_FM1R_FBM9 CAN_FM1R_FBM9_Msk /*!< Filter Init Mode for filter 9 */
+#define CAN_FM1R_FBM10_Pos (10U)
+#define CAN_FM1R_FBM10_Msk (0x1U << CAN_FM1R_FBM10_Pos) /*!< 0x00000400 */
+#define CAN_FM1R_FBM10 CAN_FM1R_FBM10_Msk /*!< Filter Init Mode for filter 10 */
+#define CAN_FM1R_FBM11_Pos (11U)
+#define CAN_FM1R_FBM11_Msk (0x1U << CAN_FM1R_FBM11_Pos) /*!< 0x00000800 */
+#define CAN_FM1R_FBM11 CAN_FM1R_FBM11_Msk /*!< Filter Init Mode for filter 11 */
+#define CAN_FM1R_FBM12_Pos (12U)
+#define CAN_FM1R_FBM12_Msk (0x1U << CAN_FM1R_FBM12_Pos) /*!< 0x00001000 */
+#define CAN_FM1R_FBM12 CAN_FM1R_FBM12_Msk /*!< Filter Init Mode for filter 12 */
+#define CAN_FM1R_FBM13_Pos (13U)
+#define CAN_FM1R_FBM13_Msk (0x1U << CAN_FM1R_FBM13_Pos) /*!< 0x00002000 */
+#define CAN_FM1R_FBM13 CAN_FM1R_FBM13_Msk /*!< Filter Init Mode for filter 13 */
+#define CAN_FM1R_FBM14_Pos (14U)
+#define CAN_FM1R_FBM14_Msk (0x1U << CAN_FM1R_FBM14_Pos) /*!< 0x00004000 */
+#define CAN_FM1R_FBM14 CAN_FM1R_FBM14_Msk /*!< Filter Init Mode for filter 14 */
+#define CAN_FM1R_FBM15_Pos (15U)
+#define CAN_FM1R_FBM15_Msk (0x1U << CAN_FM1R_FBM15_Pos) /*!< 0x00008000 */
+#define CAN_FM1R_FBM15 CAN_FM1R_FBM15_Msk /*!< Filter Init Mode for filter 15 */
+#define CAN_FM1R_FBM16_Pos (16U)
+#define CAN_FM1R_FBM16_Msk (0x1U << CAN_FM1R_FBM16_Pos) /*!< 0x00010000 */
+#define CAN_FM1R_FBM16 CAN_FM1R_FBM16_Msk /*!< Filter Init Mode for filter 16 */
+#define CAN_FM1R_FBM17_Pos (17U)
+#define CAN_FM1R_FBM17_Msk (0x1U << CAN_FM1R_FBM17_Pos) /*!< 0x00020000 */
+#define CAN_FM1R_FBM17 CAN_FM1R_FBM17_Msk /*!< Filter Init Mode for filter 17 */
+#define CAN_FM1R_FBM18_Pos (18U)
+#define CAN_FM1R_FBM18_Msk (0x1U << CAN_FM1R_FBM18_Pos) /*!< 0x00040000 */
+#define CAN_FM1R_FBM18 CAN_FM1R_FBM18_Msk /*!< Filter Init Mode for filter 18 */
+#define CAN_FM1R_FBM19_Pos (19U)
+#define CAN_FM1R_FBM19_Msk (0x1U << CAN_FM1R_FBM19_Pos) /*!< 0x00080000 */
+#define CAN_FM1R_FBM19 CAN_FM1R_FBM19_Msk /*!< Filter Init Mode for filter 19 */
+#define CAN_FM1R_FBM20_Pos (20U)
+#define CAN_FM1R_FBM20_Msk (0x1U << CAN_FM1R_FBM20_Pos) /*!< 0x00100000 */
+#define CAN_FM1R_FBM20 CAN_FM1R_FBM20_Msk /*!< Filter Init Mode for filter 20 */
+#define CAN_FM1R_FBM21_Pos (21U)
+#define CAN_FM1R_FBM21_Msk (0x1U << CAN_FM1R_FBM21_Pos) /*!< 0x00200000 */
+#define CAN_FM1R_FBM21 CAN_FM1R_FBM21_Msk /*!< Filter Init Mode for filter 21 */
+#define CAN_FM1R_FBM22_Pos (22U)
+#define CAN_FM1R_FBM22_Msk (0x1U << CAN_FM1R_FBM22_Pos) /*!< 0x00400000 */
+#define CAN_FM1R_FBM22 CAN_FM1R_FBM22_Msk /*!< Filter Init Mode for filter 22 */
+#define CAN_FM1R_FBM23_Pos (23U)
+#define CAN_FM1R_FBM23_Msk (0x1U << CAN_FM1R_FBM23_Pos) /*!< 0x00800000 */
+#define CAN_FM1R_FBM23 CAN_FM1R_FBM23_Msk /*!< Filter Init Mode for filter 23 */
+#define CAN_FM1R_FBM24_Pos (24U)
+#define CAN_FM1R_FBM24_Msk (0x1U << CAN_FM1R_FBM24_Pos) /*!< 0x01000000 */
+#define CAN_FM1R_FBM24 CAN_FM1R_FBM24_Msk /*!< Filter Init Mode for filter 24 */
+#define CAN_FM1R_FBM25_Pos (25U)
+#define CAN_FM1R_FBM25_Msk (0x1U << CAN_FM1R_FBM25_Pos) /*!< 0x02000000 */
+#define CAN_FM1R_FBM25 CAN_FM1R_FBM25_Msk /*!< Filter Init Mode for filter 25 */
+#define CAN_FM1R_FBM26_Pos (26U)
+#define CAN_FM1R_FBM26_Msk (0x1U << CAN_FM1R_FBM26_Pos) /*!< 0x04000000 */
+#define CAN_FM1R_FBM26 CAN_FM1R_FBM26_Msk /*!< Filter Init Mode for filter 26 */
+#define CAN_FM1R_FBM27_Pos (27U)
+#define CAN_FM1R_FBM27_Msk (0x1U << CAN_FM1R_FBM27_Pos) /*!< 0x08000000 */
+#define CAN_FM1R_FBM27 CAN_FM1R_FBM27_Msk /*!< Filter Init Mode for filter 27 */
+
+/******************* Bit definition for CAN_FS1R register *******************/
+#define CAN_FS1R_FSC_Pos (0U)
+#define CAN_FS1R_FSC_Msk (0x3FFFU << CAN_FS1R_FSC_Pos) /*!< 0x00003FFF */
+#define CAN_FS1R_FSC CAN_FS1R_FSC_Msk /*!< Filter Scale Configuration */
+#define CAN_FS1R_FSC0_Pos (0U)
+#define CAN_FS1R_FSC0_Msk (0x1U << CAN_FS1R_FSC0_Pos) /*!< 0x00000001 */
+#define CAN_FS1R_FSC0 CAN_FS1R_FSC0_Msk /*!< Filter Scale Configuration for filter 0 */
+#define CAN_FS1R_FSC1_Pos (1U)
+#define CAN_FS1R_FSC1_Msk (0x1U << CAN_FS1R_FSC1_Pos) /*!< 0x00000002 */
+#define CAN_FS1R_FSC1 CAN_FS1R_FSC1_Msk /*!< Filter Scale Configuration for filter 1 */
+#define CAN_FS1R_FSC2_Pos (2U)
+#define CAN_FS1R_FSC2_Msk (0x1U << CAN_FS1R_FSC2_Pos) /*!< 0x00000004 */
+#define CAN_FS1R_FSC2 CAN_FS1R_FSC2_Msk /*!< Filter Scale Configuration for filter 2 */
+#define CAN_FS1R_FSC3_Pos (3U)
+#define CAN_FS1R_FSC3_Msk (0x1U << CAN_FS1R_FSC3_Pos) /*!< 0x00000008 */
+#define CAN_FS1R_FSC3 CAN_FS1R_FSC3_Msk /*!< Filter Scale Configuration for filter 3 */
+#define CAN_FS1R_FSC4_Pos (4U)
+#define CAN_FS1R_FSC4_Msk (0x1U << CAN_FS1R_FSC4_Pos) /*!< 0x00000010 */
+#define CAN_FS1R_FSC4 CAN_FS1R_FSC4_Msk /*!< Filter Scale Configuration for filter 4 */
+#define CAN_FS1R_FSC5_Pos (5U)
+#define CAN_FS1R_FSC5_Msk (0x1U << CAN_FS1R_FSC5_Pos) /*!< 0x00000020 */
+#define CAN_FS1R_FSC5 CAN_FS1R_FSC5_Msk /*!< Filter Scale Configuration for filter 5 */
+#define CAN_FS1R_FSC6_Pos (6U)
+#define CAN_FS1R_FSC6_Msk (0x1U << CAN_FS1R_FSC6_Pos) /*!< 0x00000040 */
+#define CAN_FS1R_FSC6 CAN_FS1R_FSC6_Msk /*!< Filter Scale Configuration for filter 6 */
+#define CAN_FS1R_FSC7_Pos (7U)
+#define CAN_FS1R_FSC7_Msk (0x1U << CAN_FS1R_FSC7_Pos) /*!< 0x00000080 */
+#define CAN_FS1R_FSC7 CAN_FS1R_FSC7_Msk /*!< Filter Scale Configuration for filter 7 */
+#define CAN_FS1R_FSC8_Pos (8U)
+#define CAN_FS1R_FSC8_Msk (0x1U << CAN_FS1R_FSC8_Pos) /*!< 0x00000100 */
+#define CAN_FS1R_FSC8 CAN_FS1R_FSC8_Msk /*!< Filter Scale Configuration for filter 8 */
+#define CAN_FS1R_FSC9_Pos (9U)
+#define CAN_FS1R_FSC9_Msk (0x1U << CAN_FS1R_FSC9_Pos) /*!< 0x00000200 */
+#define CAN_FS1R_FSC9 CAN_FS1R_FSC9_Msk /*!< Filter Scale Configuration for filter 9 */
+#define CAN_FS1R_FSC10_Pos (10U)
+#define CAN_FS1R_FSC10_Msk (0x1U << CAN_FS1R_FSC10_Pos) /*!< 0x00000400 */
+#define CAN_FS1R_FSC10 CAN_FS1R_FSC10_Msk /*!< Filter Scale Configuration for filter 10 */
+#define CAN_FS1R_FSC11_Pos (11U)
+#define CAN_FS1R_FSC11_Msk (0x1U << CAN_FS1R_FSC11_Pos) /*!< 0x00000800 */
+#define CAN_FS1R_FSC11 CAN_FS1R_FSC11_Msk /*!< Filter Scale Configuration for filter 11 */
+#define CAN_FS1R_FSC12_Pos (12U)
+#define CAN_FS1R_FSC12_Msk (0x1U << CAN_FS1R_FSC12_Pos) /*!< 0x00001000 */
+#define CAN_FS1R_FSC12 CAN_FS1R_FSC12_Msk /*!< Filter Scale Configuration for filter 12 */
+#define CAN_FS1R_FSC13_Pos (13U)
+#define CAN_FS1R_FSC13_Msk (0x1U << CAN_FS1R_FSC13_Pos) /*!< 0x00002000 */
+#define CAN_FS1R_FSC13 CAN_FS1R_FSC13_Msk /*!< Filter Scale Configuration for filter 13 */
+#define CAN_FS1R_FSC14_Pos (14U)
+#define CAN_FS1R_FSC14_Msk (0x1U << CAN_FS1R_FSC14_Pos) /*!< 0x00004000 */
+#define CAN_FS1R_FSC14 CAN_FS1R_FSC14_Msk /*!< Filter Scale Configuration for filter 14 */
+#define CAN_FS1R_FSC15_Pos (15U)
+#define CAN_FS1R_FSC15_Msk (0x1U << CAN_FS1R_FSC15_Pos) /*!< 0x00008000 */
+#define CAN_FS1R_FSC15 CAN_FS1R_FSC15_Msk /*!< Filter Scale Configuration for filter 15 */
+#define CAN_FS1R_FSC16_Pos (16U)
+#define CAN_FS1R_FSC16_Msk (0x1U << CAN_FS1R_FSC16_Pos) /*!< 0x00010000 */
+#define CAN_FS1R_FSC16 CAN_FS1R_FSC16_Msk /*!< Filter Scale Configuration for filter 16 */
+#define CAN_FS1R_FSC17_Pos (17U)
+#define CAN_FS1R_FSC17_Msk (0x1U << CAN_FS1R_FSC17_Pos) /*!< 0x00020000 */
+#define CAN_FS1R_FSC17 CAN_FS1R_FSC17_Msk /*!< Filter Scale Configuration for filter 17 */
+#define CAN_FS1R_FSC18_Pos (18U)
+#define CAN_FS1R_FSC18_Msk (0x1U << CAN_FS1R_FSC18_Pos) /*!< 0x00040000 */
+#define CAN_FS1R_FSC18 CAN_FS1R_FSC18_Msk /*!< Filter Scale Configuration for filter 18 */
+#define CAN_FS1R_FSC19_Pos (19U)
+#define CAN_FS1R_FSC19_Msk (0x1U << CAN_FS1R_FSC19_Pos) /*!< 0x00080000 */
+#define CAN_FS1R_FSC19 CAN_FS1R_FSC19_Msk /*!< Filter Scale Configuration for filter 19 */
+#define CAN_FS1R_FSC20_Pos (20U)
+#define CAN_FS1R_FSC20_Msk (0x1U << CAN_FS1R_FSC20_Pos) /*!< 0x00100000 */
+#define CAN_FS1R_FSC20 CAN_FS1R_FSC20_Msk /*!< Filter Scale Configuration for filter 20 */
+#define CAN_FS1R_FSC21_Pos (21U)
+#define CAN_FS1R_FSC21_Msk (0x1U << CAN_FS1R_FSC21_Pos) /*!< 0x00200000 */
+#define CAN_FS1R_FSC21 CAN_FS1R_FSC21_Msk /*!< Filter Scale Configuration for filter 21 */
+#define CAN_FS1R_FSC22_Pos (22U)
+#define CAN_FS1R_FSC22_Msk (0x1U << CAN_FS1R_FSC22_Pos) /*!< 0x00400000 */
+#define CAN_FS1R_FSC22 CAN_FS1R_FSC22_Msk /*!< Filter Scale Configuration for filter 22 */
+#define CAN_FS1R_FSC23_Pos (23U)
+#define CAN_FS1R_FSC23_Msk (0x1U << CAN_FS1R_FSC23_Pos) /*!< 0x00800000 */
+#define CAN_FS1R_FSC23 CAN_FS1R_FSC23_Msk /*!< Filter Scale Configuration for filter 23 */
+#define CAN_FS1R_FSC24_Pos (24U)
+#define CAN_FS1R_FSC24_Msk (0x1U << CAN_FS1R_FSC24_Pos) /*!< 0x01000000 */
+#define CAN_FS1R_FSC24 CAN_FS1R_FSC24_Msk /*!< Filter Scale Configuration for filter 24 */
+#define CAN_FS1R_FSC25_Pos (25U)
+#define CAN_FS1R_FSC25_Msk (0x1U << CAN_FS1R_FSC25_Pos) /*!< 0x02000000 */
+#define CAN_FS1R_FSC25 CAN_FS1R_FSC25_Msk /*!< Filter Scale Configuration for filter 25 */
+#define CAN_FS1R_FSC26_Pos (26U)
+#define CAN_FS1R_FSC26_Msk (0x1U << CAN_FS1R_FSC26_Pos) /*!< 0x04000000 */
+#define CAN_FS1R_FSC26 CAN_FS1R_FSC26_Msk /*!< Filter Scale Configuration for filter 26 */
+#define CAN_FS1R_FSC27_Pos (27U)
+#define CAN_FS1R_FSC27_Msk (0x1U << CAN_FS1R_FSC27_Pos) /*!< 0x08000000 */
+#define CAN_FS1R_FSC27 CAN_FS1R_FSC27_Msk /*!< Filter Scale Configuration for filter 27 */
+
+/****************** Bit definition for CAN_FFA1R register *******************/
+#define CAN_FFA1R_FFA_Pos (0U)
+#define CAN_FFA1R_FFA_Msk (0x3FFFU << CAN_FFA1R_FFA_Pos) /*!< 0x00003FFF */
+#define CAN_FFA1R_FFA CAN_FFA1R_FFA_Msk /*!< Filter FIFO Assignment */
+#define CAN_FFA1R_FFA0_Pos (0U)
+#define CAN_FFA1R_FFA0_Msk (0x1U << CAN_FFA1R_FFA0_Pos) /*!< 0x00000001 */
+#define CAN_FFA1R_FFA0 CAN_FFA1R_FFA0_Msk /*!< Filter FIFO Assignment for filter 0 */
+#define CAN_FFA1R_FFA1_Pos (1U)
+#define CAN_FFA1R_FFA1_Msk (0x1U << CAN_FFA1R_FFA1_Pos) /*!< 0x00000002 */
+#define CAN_FFA1R_FFA1 CAN_FFA1R_FFA1_Msk /*!< Filter FIFO Assignment for filter 1 */
+#define CAN_FFA1R_FFA2_Pos (2U)
+#define CAN_FFA1R_FFA2_Msk (0x1U << CAN_FFA1R_FFA2_Pos) /*!< 0x00000004 */
+#define CAN_FFA1R_FFA2 CAN_FFA1R_FFA2_Msk /*!< Filter FIFO Assignment for filter 2 */
+#define CAN_FFA1R_FFA3_Pos (3U)
+#define CAN_FFA1R_FFA3_Msk (0x1U << CAN_FFA1R_FFA3_Pos) /*!< 0x00000008 */
+#define CAN_FFA1R_FFA3 CAN_FFA1R_FFA3_Msk /*!< Filter FIFO Assignment for filter 3 */
+#define CAN_FFA1R_FFA4_Pos (4U)
+#define CAN_FFA1R_FFA4_Msk (0x1U << CAN_FFA1R_FFA4_Pos) /*!< 0x00000010 */
+#define CAN_FFA1R_FFA4 CAN_FFA1R_FFA4_Msk /*!< Filter FIFO Assignment for filter 4 */
+#define CAN_FFA1R_FFA5_Pos (5U)
+#define CAN_FFA1R_FFA5_Msk (0x1U << CAN_FFA1R_FFA5_Pos) /*!< 0x00000020 */
+#define CAN_FFA1R_FFA5 CAN_FFA1R_FFA5_Msk /*!< Filter FIFO Assignment for filter 5 */
+#define CAN_FFA1R_FFA6_Pos (6U)
+#define CAN_FFA1R_FFA6_Msk (0x1U << CAN_FFA1R_FFA6_Pos) /*!< 0x00000040 */
+#define CAN_FFA1R_FFA6 CAN_FFA1R_FFA6_Msk /*!< Filter FIFO Assignment for filter 6 */
+#define CAN_FFA1R_FFA7_Pos (7U)
+#define CAN_FFA1R_FFA7_Msk (0x1U << CAN_FFA1R_FFA7_Pos) /*!< 0x00000080 */
+#define CAN_FFA1R_FFA7 CAN_FFA1R_FFA7_Msk /*!< Filter FIFO Assignment for filter 7 */
+#define CAN_FFA1R_FFA8_Pos (8U)
+#define CAN_FFA1R_FFA8_Msk (0x1U << CAN_FFA1R_FFA8_Pos) /*!< 0x00000100 */
+#define CAN_FFA1R_FFA8 CAN_FFA1R_FFA8_Msk /*!< Filter FIFO Assignment for filter 8 */
+#define CAN_FFA1R_FFA9_Pos (9U)
+#define CAN_FFA1R_FFA9_Msk (0x1U << CAN_FFA1R_FFA9_Pos) /*!< 0x00000200 */
+#define CAN_FFA1R_FFA9 CAN_FFA1R_FFA9_Msk /*!< Filter FIFO Assignment for filter 9 */
+#define CAN_FFA1R_FFA10_Pos (10U)
+#define CAN_FFA1R_FFA10_Msk (0x1U << CAN_FFA1R_FFA10_Pos) /*!< 0x00000400 */
+#define CAN_FFA1R_FFA10 CAN_FFA1R_FFA10_Msk /*!< Filter FIFO Assignment for filter 10 */
+#define CAN_FFA1R_FFA11_Pos (11U)
+#define CAN_FFA1R_FFA11_Msk (0x1U << CAN_FFA1R_FFA11_Pos) /*!< 0x00000800 */
+#define CAN_FFA1R_FFA11 CAN_FFA1R_FFA11_Msk /*!< Filter FIFO Assignment for filter 11 */
+#define CAN_FFA1R_FFA12_Pos (12U)
+#define CAN_FFA1R_FFA12_Msk (0x1U << CAN_FFA1R_FFA12_Pos) /*!< 0x00001000 */
+#define CAN_FFA1R_FFA12 CAN_FFA1R_FFA12_Msk /*!< Filter FIFO Assignment for filter 12 */
+#define CAN_FFA1R_FFA13_Pos (13U)
+#define CAN_FFA1R_FFA13_Msk (0x1U << CAN_FFA1R_FFA13_Pos) /*!< 0x00002000 */
+#define CAN_FFA1R_FFA13 CAN_FFA1R_FFA13_Msk /*!< Filter FIFO Assignment for filter 13 */
+#define CAN_FFA1_FFA14_Pos (14U)
+#define CAN_FFA1_FFA14_Msk (0x1U << CAN_FFA1_FFA14_Pos) /*!< 0x00004000 */
+#define CAN_FFA1_FFA14 CAN_FFA1_FFA14_Msk /*!< Filter FIFO Assignment for filter 14 */
+#define CAN_FFA1_FFA15_Pos (15U)
+#define CAN_FFA1_FFA15_Msk (0x1U << CAN_FFA1_FFA15_Pos) /*!< 0x00008000 */
+#define CAN_FFA1_FFA15 CAN_FFA1_FFA15_Msk /*!< Filter FIFO Assignment for filter 15 */
+#define CAN_FFA1_FFA16_Pos (16U)
+#define CAN_FFA1_FFA16_Msk (0x1U << CAN_FFA1_FFA16_Pos) /*!< 0x00010000 */
+#define CAN_FFA1_FFA16 CAN_FFA1_FFA16_Msk /*!< Filter FIFO Assignment for filter 16 */
+#define CAN_FFA1_FFA17_Pos (17U)
+#define CAN_FFA1_FFA17_Msk (0x1U << CAN_FFA1_FFA17_Pos) /*!< 0x00020000 */
+#define CAN_FFA1_FFA17 CAN_FFA1_FFA17_Msk /*!< Filter FIFO Assignment for filter 17 */
+#define CAN_FFA1_FFA18_Pos (18U)
+#define CAN_FFA1_FFA18_Msk (0x1U << CAN_FFA1_FFA18_Pos) /*!< 0x00040000 */
+#define CAN_FFA1_FFA18 CAN_FFA1_FFA18_Msk /*!< Filter FIFO Assignment for filter 18 */
+#define CAN_FFA1_FFA19_Pos (19U)
+#define CAN_FFA1_FFA19_Msk (0x1U << CAN_FFA1_FFA19_Pos) /*!< 0x00080000 */
+#define CAN_FFA1_FFA19 CAN_FFA1_FFA19_Msk /*!< Filter FIFO Assignment for filter 19 */
+#define CAN_FFA1_FFA20_Pos (20U)
+#define CAN_FFA1_FFA20_Msk (0x1U << CAN_FFA1_FFA20_Pos) /*!< 0x00100000 */
+#define CAN_FFA1_FFA20 CAN_FFA1_FFA20_Msk /*!< Filter FIFO Assignment for filter 20 */
+#define CAN_FFA1_FFA21_Pos (21U)
+#define CAN_FFA1_FFA21_Msk (0x1U << CAN_FFA1_FFA21_Pos) /*!< 0x00200000 */
+#define CAN_FFA1_FFA21 CAN_FFA1_FFA21_Msk /*!< Filter FIFO Assignment for filter 21 */
+#define CAN_FFA1_FFA22_Pos (22U)
+#define CAN_FFA1_FFA22_Msk (0x1U << CAN_FFA1_FFA22_Pos) /*!< 0x00400000 */
+#define CAN_FFA1_FFA22 CAN_FFA1_FFA22_Msk /*!< Filter FIFO Assignment for filter 22 */
+#define CAN_FFA1_FFA23_Pos (23U)
+#define CAN_FFA1_FFA23_Msk (0x1U << CAN_FFA1_FFA23_Pos) /*!< 0x00800000 */
+#define CAN_FFA1_FFA23 CAN_FFA1_FFA23_Msk /*!< Filter FIFO Assignment for filter 23 */
+#define CAN_FFA1_FFA24_Pos (24U)
+#define CAN_FFA1_FFA24_Msk (0x1U << CAN_FFA1_FFA24_Pos) /*!< 0x01000000 */
+#define CAN_FFA1_FFA24 CAN_FFA1_FFA24_Msk /*!< Filter FIFO Assignment for filter 24 */
+#define CAN_FFA1_FFA25_Pos (25U)
+#define CAN_FFA1_FFA25_Msk (0x1U << CAN_FFA1_FFA25_Pos) /*!< 0x02000000 */
+#define CAN_FFA1_FFA25 CAN_FFA1_FFA25_Msk /*!< Filter FIFO Assignment for filter 25 */
+#define CAN_FFA1_FFA26_Pos (26U)
+#define CAN_FFA1_FFA26_Msk (0x1U << CAN_FFA1_FFA26_Pos) /*!< 0x04000000 */
+#define CAN_FFA1_FFA26 CAN_FFA1_FFA26_Msk /*!< Filter FIFO Assignment for filter 26 */
+#define CAN_FFA1_FFA27_Pos (27U)
+#define CAN_FFA1_FFA27_Msk (0x1U << CAN_FFA1_FFA27_Pos) /*!< 0x08000000 */
+#define CAN_FFA1_FFA27 CAN_FFA1_FFA27_Msk /*!< Filter FIFO Assignment for filter 27 */
+
+/******************* Bit definition for CAN_FA1R register *******************/
+#define CAN_FA1R_FACT_Pos (0U)
+#define CAN_FA1R_FACT_Msk (0x3FFFU << CAN_FA1R_FACT_Pos) /*!< 0x00003FFF */
+#define CAN_FA1R_FACT CAN_FA1R_FACT_Msk /*!< Filter Active */
+#define CAN_FA1R_FACT0_Pos (0U)
+#define CAN_FA1R_FACT0_Msk (0x1U << CAN_FA1R_FACT0_Pos) /*!< 0x00000001 */
+#define CAN_FA1R_FACT0 CAN_FA1R_FACT0_Msk /*!< Filter 0 Active */
+#define CAN_FA1R_FACT1_Pos (1U)
+#define CAN_FA1R_FACT1_Msk (0x1U << CAN_FA1R_FACT1_Pos) /*!< 0x00000002 */
+#define CAN_FA1R_FACT1 CAN_FA1R_FACT1_Msk /*!< Filter 1 Active */
+#define CAN_FA1R_FACT2_Pos (2U)
+#define CAN_FA1R_FACT2_Msk (0x1U << CAN_FA1R_FACT2_Pos) /*!< 0x00000004 */
+#define CAN_FA1R_FACT2 CAN_FA1R_FACT2_Msk /*!< Filter 2 Active */
+#define CAN_FA1R_FACT3_Pos (3U)
+#define CAN_FA1R_FACT3_Msk (0x1U << CAN_FA1R_FACT3_Pos) /*!< 0x00000008 */
+#define CAN_FA1R_FACT3 CAN_FA1R_FACT3_Msk /*!< Filter 3 Active */
+#define CAN_FA1R_FACT4_Pos (4U)
+#define CAN_FA1R_FACT4_Msk (0x1U << CAN_FA1R_FACT4_Pos) /*!< 0x00000010 */
+#define CAN_FA1R_FACT4 CAN_FA1R_FACT4_Msk /*!< Filter 4 Active */
+#define CAN_FA1R_FACT5_Pos (5U)
+#define CAN_FA1R_FACT5_Msk (0x1U << CAN_FA1R_FACT5_Pos) /*!< 0x00000020 */
+#define CAN_FA1R_FACT5 CAN_FA1R_FACT5_Msk /*!< Filter 5 Active */
+#define CAN_FA1R_FACT6_Pos (6U)
+#define CAN_FA1R_FACT6_Msk (0x1U << CAN_FA1R_FACT6_Pos) /*!< 0x00000040 */
+#define CAN_FA1R_FACT6 CAN_FA1R_FACT6_Msk /*!< Filter 6 Active */
+#define CAN_FA1R_FACT7_Pos (7U)
+#define CAN_FA1R_FACT7_Msk (0x1U << CAN_FA1R_FACT7_Pos) /*!< 0x00000080 */
+#define CAN_FA1R_FACT7 CAN_FA1R_FACT7_Msk /*!< Filter 7 Active */
+#define CAN_FA1R_FACT8_Pos (8U)
+#define CAN_FA1R_FACT8_Msk (0x1U << CAN_FA1R_FACT8_Pos) /*!< 0x00000100 */
+#define CAN_FA1R_FACT8 CAN_FA1R_FACT8_Msk /*!< Filter 8 Active */
+#define CAN_FA1R_FACT9_Pos (9U)
+#define CAN_FA1R_FACT9_Msk (0x1U << CAN_FA1R_FACT9_Pos) /*!< 0x00000200 */
+#define CAN_FA1R_FACT9 CAN_FA1R_FACT9_Msk /*!< Filter 9 Active */
+#define CAN_FA1R_FACT10_Pos (10U)
+#define CAN_FA1R_FACT10_Msk (0x1U << CAN_FA1R_FACT10_Pos) /*!< 0x00000400 */
+#define CAN_FA1R_FACT10 CAN_FA1R_FACT10_Msk /*!< Filter 10 Active */
+#define CAN_FA1R_FACT11_Pos (11U)
+#define CAN_FA1R_FACT11_Msk (0x1U << CAN_FA1R_FACT11_Pos) /*!< 0x00000800 */
+#define CAN_FA1R_FACT11 CAN_FA1R_FACT11_Msk /*!< Filter 11 Active */
+#define CAN_FA1R_FACT12_Pos (12U)
+#define CAN_FA1R_FACT12_Msk (0x1U << CAN_FA1R_FACT12_Pos) /*!< 0x00001000 */
+#define CAN_FA1R_FACT12 CAN_FA1R_FACT12_Msk /*!< Filter 12 Active */
+#define CAN_FA1R_FACT13_Pos (13U)
+#define CAN_FA1R_FACT13_Msk (0x1U << CAN_FA1R_FACT13_Pos) /*!< 0x00002000 */
+#define CAN_FA1R_FACT13 CAN_FA1R_FACT13_Msk /*!< Filter 13 Active */
+#define CAN_FA1R_FACT14_Pos (14U)
+#define CAN_FA1R_FACT14_Msk (0x1U << CAN_FA1R_FACT14_Pos) /*!< 0x00004000 */
+#define CAN_FA1R_FACT14 CAN_FA1R_FACT14_Msk /*!< Filter 14 Active */
+#define CAN_FA1R_FACT15_Pos (15U)
+#define CAN_FA1R_FACT15_Msk (0x1U << CAN_FA1R_FACT15_Pos) /*!< 0x00008000 */
+#define CAN_FA1R_FACT15 CAN_FA1R_FACT15_Msk /*!< Filter 15 Active */
+#define CAN_FA1R_FACT16_Pos (16U)
+#define CAN_FA1R_FACT16_Msk (0x1U << CAN_FA1R_FACT16_Pos) /*!< 0x00010000 */
+#define CAN_FA1R_FACT16 CAN_FA1R_FACT16_Msk /*!< Filter 16 Active */
+#define CAN_FA1R_FACT17_Pos (17U)
+#define CAN_FA1R_FACT17_Msk (0x1U << CAN_FA1R_FACT17_Pos) /*!< 0x00020000 */
+#define CAN_FA1R_FACT17 CAN_FA1R_FACT17_Msk /*!< Filter 17 Active */
+#define CAN_FA1R_FACT18_Pos (18U)
+#define CAN_FA1R_FACT18_Msk (0x1U << CAN_FA1R_FACT18_Pos) /*!< 0x00040000 */
+#define CAN_FA1R_FACT18 CAN_FA1R_FACT18_Msk /*!< Filter 18 Active */
+#define CAN_FA1R_FACT19_Pos (19U)
+#define CAN_FA1R_FACT19_Msk (0x1U << CAN_FA1R_FACT19_Pos) /*!< 0x00080000 */
+#define CAN_FA1R_FACT19 CAN_FA1R_FACT19_Msk /*!< Filter 19 Active */
+#define CAN_FA1R_FACT20_Pos (20U)
+#define CAN_FA1R_FACT20_Msk (0x1U << CAN_FA1R_FACT20_Pos) /*!< 0x00100000 */
+#define CAN_FA1R_FACT20 CAN_FA1R_FACT20_Msk /*!< Filter 20 Active */
+#define CAN_FA1R_FACT21_Pos (21U)
+#define CAN_FA1R_FACT21_Msk (0x1U << CAN_FA1R_FACT21_Pos) /*!< 0x00200000 */
+#define CAN_FA1R_FACT21 CAN_FA1R_FACT21_Msk /*!< Filter 21 Active */
+#define CAN_FA1R_FACT22_Pos (22U)
+#define CAN_FA1R_FACT22_Msk (0x1U << CAN_FA1R_FACT22_Pos) /*!< 0x00400000 */
+#define CAN_FA1R_FACT22 CAN_FA1R_FACT22_Msk /*!< Filter 22 Active */
+#define CAN_FA1R_FACT23_Pos (23U)
+#define CAN_FA1R_FACT23_Msk (0x1U << CAN_FA1R_FACT23_Pos) /*!< 0x00800000 */
+#define CAN_FA1R_FACT23 CAN_FA1R_FACT23_Msk /*!< Filter 23 Active */
+#define CAN_FA1R_FACT24_Pos (24U)
+#define CAN_FA1R_FACT24_Msk (0x1U << CAN_FA1R_FACT24_Pos) /*!< 0x01000000 */
+#define CAN_FA1R_FACT24 CAN_FA1R_FACT24_Msk /*!< Filter 24 Active */
+#define CAN_FA1R_FACT25_Pos (25U)
+#define CAN_FA1R_FACT25_Msk (0x1U << CAN_FA1R_FACT25_Pos) /*!< 0x02000000 */
+#define CAN_FA1R_FACT25 CAN_FA1R_FACT25_Msk /*!< Filter 25 Active */
+#define CAN_FA1R_FACT26_Pos (26U)
+#define CAN_FA1R_FACT26_Msk (0x1U << CAN_FA1R_FACT26_Pos) /*!< 0x04000000 */
+#define CAN_FA1R_FACT26 CAN_FA1R_FACT26_Msk /*!< Filter 26 Active */
+#define CAN_FA1R_FACT27_Pos (27U)
+#define CAN_FA1R_FACT27_Msk (0x1U << CAN_FA1R_FACT27_Pos) /*!< 0x08000000 */
+#define CAN_FA1R_FACT27 CAN_FA1R_FACT27_Msk /*!< Filter 27 Active */
+
+/******************* Bit definition for CAN_F0R1 register *******************/
+#define CAN_F0R1_FB0_Pos (0U)
+#define CAN_F0R1_FB0_Msk (0x1U << CAN_F0R1_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F0R1_FB0 CAN_F0R1_FB0_Msk /*!< Filter bit 0 */
+#define CAN_F0R1_FB1_Pos (1U)
+#define CAN_F0R1_FB1_Msk (0x1U << CAN_F0R1_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F0R1_FB1 CAN_F0R1_FB1_Msk /*!< Filter bit 1 */
+#define CAN_F0R1_FB2_Pos (2U)
+#define CAN_F0R1_FB2_Msk (0x1U << CAN_F0R1_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F0R1_FB2 CAN_F0R1_FB2_Msk /*!< Filter bit 2 */
+#define CAN_F0R1_FB3_Pos (3U)
+#define CAN_F0R1_FB3_Msk (0x1U << CAN_F0R1_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F0R1_FB3 CAN_F0R1_FB3_Msk /*!< Filter bit 3 */
+#define CAN_F0R1_FB4_Pos (4U)
+#define CAN_F0R1_FB4_Msk (0x1U << CAN_F0R1_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F0R1_FB4 CAN_F0R1_FB4_Msk /*!< Filter bit 4 */
+#define CAN_F0R1_FB5_Pos (5U)
+#define CAN_F0R1_FB5_Msk (0x1U << CAN_F0R1_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F0R1_FB5 CAN_F0R1_FB5_Msk /*!< Filter bit 5 */
+#define CAN_F0R1_FB6_Pos (6U)
+#define CAN_F0R1_FB6_Msk (0x1U << CAN_F0R1_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F0R1_FB6 CAN_F0R1_FB6_Msk /*!< Filter bit 6 */
+#define CAN_F0R1_FB7_Pos (7U)
+#define CAN_F0R1_FB7_Msk (0x1U << CAN_F0R1_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F0R1_FB7 CAN_F0R1_FB7_Msk /*!< Filter bit 7 */
+#define CAN_F0R1_FB8_Pos (8U)
+#define CAN_F0R1_FB8_Msk (0x1U << CAN_F0R1_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F0R1_FB8 CAN_F0R1_FB8_Msk /*!< Filter bit 8 */
+#define CAN_F0R1_FB9_Pos (9U)
+#define CAN_F0R1_FB9_Msk (0x1U << CAN_F0R1_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F0R1_FB9 CAN_F0R1_FB9_Msk /*!< Filter bit 9 */
+#define CAN_F0R1_FB10_Pos (10U)
+#define CAN_F0R1_FB10_Msk (0x1U << CAN_F0R1_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F0R1_FB10 CAN_F0R1_FB10_Msk /*!< Filter bit 10 */
+#define CAN_F0R1_FB11_Pos (11U)
+#define CAN_F0R1_FB11_Msk (0x1U << CAN_F0R1_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F0R1_FB11 CAN_F0R1_FB11_Msk /*!< Filter bit 11 */
+#define CAN_F0R1_FB12_Pos (12U)
+#define CAN_F0R1_FB12_Msk (0x1U << CAN_F0R1_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F0R1_FB12 CAN_F0R1_FB12_Msk /*!< Filter bit 12 */
+#define CAN_F0R1_FB13_Pos (13U)
+#define CAN_F0R1_FB13_Msk (0x1U << CAN_F0R1_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F0R1_FB13 CAN_F0R1_FB13_Msk /*!< Filter bit 13 */
+#define CAN_F0R1_FB14_Pos (14U)
+#define CAN_F0R1_FB14_Msk (0x1U << CAN_F0R1_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F0R1_FB14 CAN_F0R1_FB14_Msk /*!< Filter bit 14 */
+#define CAN_F0R1_FB15_Pos (15U)
+#define CAN_F0R1_FB15_Msk (0x1U << CAN_F0R1_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F0R1_FB15 CAN_F0R1_FB15_Msk /*!< Filter bit 15 */
+#define CAN_F0R1_FB16_Pos (16U)
+#define CAN_F0R1_FB16_Msk (0x1U << CAN_F0R1_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F0R1_FB16 CAN_F0R1_FB16_Msk /*!< Filter bit 16 */
+#define CAN_F0R1_FB17_Pos (17U)
+#define CAN_F0R1_FB17_Msk (0x1U << CAN_F0R1_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F0R1_FB17 CAN_F0R1_FB17_Msk /*!< Filter bit 17 */
+#define CAN_F0R1_FB18_Pos (18U)
+#define CAN_F0R1_FB18_Msk (0x1U << CAN_F0R1_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F0R1_FB18 CAN_F0R1_FB18_Msk /*!< Filter bit 18 */
+#define CAN_F0R1_FB19_Pos (19U)
+#define CAN_F0R1_FB19_Msk (0x1U << CAN_F0R1_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F0R1_FB19 CAN_F0R1_FB19_Msk /*!< Filter bit 19 */
+#define CAN_F0R1_FB20_Pos (20U)
+#define CAN_F0R1_FB20_Msk (0x1U << CAN_F0R1_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F0R1_FB20 CAN_F0R1_FB20_Msk /*!< Filter bit 20 */
+#define CAN_F0R1_FB21_Pos (21U)
+#define CAN_F0R1_FB21_Msk (0x1U << CAN_F0R1_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F0R1_FB21 CAN_F0R1_FB21_Msk /*!< Filter bit 21 */
+#define CAN_F0R1_FB22_Pos (22U)
+#define CAN_F0R1_FB22_Msk (0x1U << CAN_F0R1_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F0R1_FB22 CAN_F0R1_FB22_Msk /*!< Filter bit 22 */
+#define CAN_F0R1_FB23_Pos (23U)
+#define CAN_F0R1_FB23_Msk (0x1U << CAN_F0R1_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F0R1_FB23 CAN_F0R1_FB23_Msk /*!< Filter bit 23 */
+#define CAN_F0R1_FB24_Pos (24U)
+#define CAN_F0R1_FB24_Msk (0x1U << CAN_F0R1_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F0R1_FB24 CAN_F0R1_FB24_Msk /*!< Filter bit 24 */
+#define CAN_F0R1_FB25_Pos (25U)
+#define CAN_F0R1_FB25_Msk (0x1U << CAN_F0R1_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F0R1_FB25 CAN_F0R1_FB25_Msk /*!< Filter bit 25 */
+#define CAN_F0R1_FB26_Pos (26U)
+#define CAN_F0R1_FB26_Msk (0x1U << CAN_F0R1_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F0R1_FB26 CAN_F0R1_FB26_Msk /*!< Filter bit 26 */
+#define CAN_F0R1_FB27_Pos (27U)
+#define CAN_F0R1_FB27_Msk (0x1U << CAN_F0R1_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F0R1_FB27 CAN_F0R1_FB27_Msk /*!< Filter bit 27 */
+#define CAN_F0R1_FB28_Pos (28U)
+#define CAN_F0R1_FB28_Msk (0x1U << CAN_F0R1_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F0R1_FB28 CAN_F0R1_FB28_Msk /*!< Filter bit 28 */
+#define CAN_F0R1_FB29_Pos (29U)
+#define CAN_F0R1_FB29_Msk (0x1U << CAN_F0R1_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F0R1_FB29 CAN_F0R1_FB29_Msk /*!< Filter bit 29 */
+#define CAN_F0R1_FB30_Pos (30U)
+#define CAN_F0R1_FB30_Msk (0x1U << CAN_F0R1_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F0R1_FB30 CAN_F0R1_FB30_Msk /*!< Filter bit 30 */
+#define CAN_F0R1_FB31_Pos (31U)
+#define CAN_F0R1_FB31_Msk (0x1U << CAN_F0R1_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F0R1_FB31 CAN_F0R1_FB31_Msk /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F1R1 register *******************/
+#define CAN_F1R1_FB0_Pos (0U)
+#define CAN_F1R1_FB0_Msk (0x1U << CAN_F1R1_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F1R1_FB0 CAN_F1R1_FB0_Msk /*!< Filter bit 0 */
+#define CAN_F1R1_FB1_Pos (1U)
+#define CAN_F1R1_FB1_Msk (0x1U << CAN_F1R1_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F1R1_FB1 CAN_F1R1_FB1_Msk /*!< Filter bit 1 */
+#define CAN_F1R1_FB2_Pos (2U)
+#define CAN_F1R1_FB2_Msk (0x1U << CAN_F1R1_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F1R1_FB2 CAN_F1R1_FB2_Msk /*!< Filter bit 2 */
+#define CAN_F1R1_FB3_Pos (3U)
+#define CAN_F1R1_FB3_Msk (0x1U << CAN_F1R1_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F1R1_FB3 CAN_F1R1_FB3_Msk /*!< Filter bit 3 */
+#define CAN_F1R1_FB4_Pos (4U)
+#define CAN_F1R1_FB4_Msk (0x1U << CAN_F1R1_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F1R1_FB4 CAN_F1R1_FB4_Msk /*!< Filter bit 4 */
+#define CAN_F1R1_FB5_Pos (5U)
+#define CAN_F1R1_FB5_Msk (0x1U << CAN_F1R1_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F1R1_FB5 CAN_F1R1_FB5_Msk /*!< Filter bit 5 */
+#define CAN_F1R1_FB6_Pos (6U)
+#define CAN_F1R1_FB6_Msk (0x1U << CAN_F1R1_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F1R1_FB6 CAN_F1R1_FB6_Msk /*!< Filter bit 6 */
+#define CAN_F1R1_FB7_Pos (7U)
+#define CAN_F1R1_FB7_Msk (0x1U << CAN_F1R1_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F1R1_FB7 CAN_F1R1_FB7_Msk /*!< Filter bit 7 */
+#define CAN_F1R1_FB8_Pos (8U)
+#define CAN_F1R1_FB8_Msk (0x1U << CAN_F1R1_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F1R1_FB8 CAN_F1R1_FB8_Msk /*!< Filter bit 8 */
+#define CAN_F1R1_FB9_Pos (9U)
+#define CAN_F1R1_FB9_Msk (0x1U << CAN_F1R1_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F1R1_FB9 CAN_F1R1_FB9_Msk /*!< Filter bit 9 */
+#define CAN_F1R1_FB10_Pos (10U)
+#define CAN_F1R1_FB10_Msk (0x1U << CAN_F1R1_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F1R1_FB10 CAN_F1R1_FB10_Msk /*!< Filter bit 10 */
+#define CAN_F1R1_FB11_Pos (11U)
+#define CAN_F1R1_FB11_Msk (0x1U << CAN_F1R1_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F1R1_FB11 CAN_F1R1_FB11_Msk /*!< Filter bit 11 */
+#define CAN_F1R1_FB12_Pos (12U)
+#define CAN_F1R1_FB12_Msk (0x1U << CAN_F1R1_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F1R1_FB12 CAN_F1R1_FB12_Msk /*!< Filter bit 12 */
+#define CAN_F1R1_FB13_Pos (13U)
+#define CAN_F1R1_FB13_Msk (0x1U << CAN_F1R1_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F1R1_FB13 CAN_F1R1_FB13_Msk /*!< Filter bit 13 */
+#define CAN_F1R1_FB14_Pos (14U)
+#define CAN_F1R1_FB14_Msk (0x1U << CAN_F1R1_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F1R1_FB14 CAN_F1R1_FB14_Msk /*!< Filter bit 14 */
+#define CAN_F1R1_FB15_Pos (15U)
+#define CAN_F1R1_FB15_Msk (0x1U << CAN_F1R1_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F1R1_FB15 CAN_F1R1_FB15_Msk /*!< Filter bit 15 */
+#define CAN_F1R1_FB16_Pos (16U)
+#define CAN_F1R1_FB16_Msk (0x1U << CAN_F1R1_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F1R1_FB16 CAN_F1R1_FB16_Msk /*!< Filter bit 16 */
+#define CAN_F1R1_FB17_Pos (17U)
+#define CAN_F1R1_FB17_Msk (0x1U << CAN_F1R1_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F1R1_FB17 CAN_F1R1_FB17_Msk /*!< Filter bit 17 */
+#define CAN_F1R1_FB18_Pos (18U)
+#define CAN_F1R1_FB18_Msk (0x1U << CAN_F1R1_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F1R1_FB18 CAN_F1R1_FB18_Msk /*!< Filter bit 18 */
+#define CAN_F1R1_FB19_Pos (19U)
+#define CAN_F1R1_FB19_Msk (0x1U << CAN_F1R1_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F1R1_FB19 CAN_F1R1_FB19_Msk /*!< Filter bit 19 */
+#define CAN_F1R1_FB20_Pos (20U)
+#define CAN_F1R1_FB20_Msk (0x1U << CAN_F1R1_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F1R1_FB20 CAN_F1R1_FB20_Msk /*!< Filter bit 20 */
+#define CAN_F1R1_FB21_Pos (21U)
+#define CAN_F1R1_FB21_Msk (0x1U << CAN_F1R1_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F1R1_FB21 CAN_F1R1_FB21_Msk /*!< Filter bit 21 */
+#define CAN_F1R1_FB22_Pos (22U)
+#define CAN_F1R1_FB22_Msk (0x1U << CAN_F1R1_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F1R1_FB22 CAN_F1R1_FB22_Msk /*!< Filter bit 22 */
+#define CAN_F1R1_FB23_Pos (23U)
+#define CAN_F1R1_FB23_Msk (0x1U << CAN_F1R1_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F1R1_FB23 CAN_F1R1_FB23_Msk /*!< Filter bit 23 */
+#define CAN_F1R1_FB24_Pos (24U)
+#define CAN_F1R1_FB24_Msk (0x1U << CAN_F1R1_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F1R1_FB24 CAN_F1R1_FB24_Msk /*!< Filter bit 24 */
+#define CAN_F1R1_FB25_Pos (25U)
+#define CAN_F1R1_FB25_Msk (0x1U << CAN_F1R1_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F1R1_FB25 CAN_F1R1_FB25_Msk /*!< Filter bit 25 */
+#define CAN_F1R1_FB26_Pos (26U)
+#define CAN_F1R1_FB26_Msk (0x1U << CAN_F1R1_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F1R1_FB26 CAN_F1R1_FB26_Msk /*!< Filter bit 26 */
+#define CAN_F1R1_FB27_Pos (27U)
+#define CAN_F1R1_FB27_Msk (0x1U << CAN_F1R1_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F1R1_FB27 CAN_F1R1_FB27_Msk /*!< Filter bit 27 */
+#define CAN_F1R1_FB28_Pos (28U)
+#define CAN_F1R1_FB28_Msk (0x1U << CAN_F1R1_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F1R1_FB28 CAN_F1R1_FB28_Msk /*!< Filter bit 28 */
+#define CAN_F1R1_FB29_Pos (29U)
+#define CAN_F1R1_FB29_Msk (0x1U << CAN_F1R1_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F1R1_FB29 CAN_F1R1_FB29_Msk /*!< Filter bit 29 */
+#define CAN_F1R1_FB30_Pos (30U)
+#define CAN_F1R1_FB30_Msk (0x1U << CAN_F1R1_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F1R1_FB30 CAN_F1R1_FB30_Msk /*!< Filter bit 30 */
+#define CAN_F1R1_FB31_Pos (31U)
+#define CAN_F1R1_FB31_Msk (0x1U << CAN_F1R1_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F1R1_FB31 CAN_F1R1_FB31_Msk /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F2R1 register *******************/
+#define CAN_F2R1_FB0_Pos (0U)
+#define CAN_F2R1_FB0_Msk (0x1U << CAN_F2R1_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F2R1_FB0 CAN_F2R1_FB0_Msk /*!< Filter bit 0 */
+#define CAN_F2R1_FB1_Pos (1U)
+#define CAN_F2R1_FB1_Msk (0x1U << CAN_F2R1_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F2R1_FB1 CAN_F2R1_FB1_Msk /*!< Filter bit 1 */
+#define CAN_F2R1_FB2_Pos (2U)
+#define CAN_F2R1_FB2_Msk (0x1U << CAN_F2R1_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F2R1_FB2 CAN_F2R1_FB2_Msk /*!< Filter bit 2 */
+#define CAN_F2R1_FB3_Pos (3U)
+#define CAN_F2R1_FB3_Msk (0x1U << CAN_F2R1_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F2R1_FB3 CAN_F2R1_FB3_Msk /*!< Filter bit 3 */
+#define CAN_F2R1_FB4_Pos (4U)
+#define CAN_F2R1_FB4_Msk (0x1U << CAN_F2R1_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F2R1_FB4 CAN_F2R1_FB4_Msk /*!< Filter bit 4 */
+#define CAN_F2R1_FB5_Pos (5U)
+#define CAN_F2R1_FB5_Msk (0x1U << CAN_F2R1_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F2R1_FB5 CAN_F2R1_FB5_Msk /*!< Filter bit 5 */
+#define CAN_F2R1_FB6_Pos (6U)
+#define CAN_F2R1_FB6_Msk (0x1U << CAN_F2R1_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F2R1_FB6 CAN_F2R1_FB6_Msk /*!< Filter bit 6 */
+#define CAN_F2R1_FB7_Pos (7U)
+#define CAN_F2R1_FB7_Msk (0x1U << CAN_F2R1_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F2R1_FB7 CAN_F2R1_FB7_Msk /*!< Filter bit 7 */
+#define CAN_F2R1_FB8_Pos (8U)
+#define CAN_F2R1_FB8_Msk (0x1U << CAN_F2R1_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F2R1_FB8 CAN_F2R1_FB8_Msk /*!< Filter bit 8 */
+#define CAN_F2R1_FB9_Pos (9U)
+#define CAN_F2R1_FB9_Msk (0x1U << CAN_F2R1_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F2R1_FB9 CAN_F2R1_FB9_Msk /*!< Filter bit 9 */
+#define CAN_F2R1_FB10_Pos (10U)
+#define CAN_F2R1_FB10_Msk (0x1U << CAN_F2R1_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F2R1_FB10 CAN_F2R1_FB10_Msk /*!< Filter bit 10 */
+#define CAN_F2R1_FB11_Pos (11U)
+#define CAN_F2R1_FB11_Msk (0x1U << CAN_F2R1_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F2R1_FB11 CAN_F2R1_FB11_Msk /*!< Filter bit 11 */
+#define CAN_F2R1_FB12_Pos (12U)
+#define CAN_F2R1_FB12_Msk (0x1U << CAN_F2R1_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F2R1_FB12 CAN_F2R1_FB12_Msk /*!< Filter bit 12 */
+#define CAN_F2R1_FB13_Pos (13U)
+#define CAN_F2R1_FB13_Msk (0x1U << CAN_F2R1_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F2R1_FB13 CAN_F2R1_FB13_Msk /*!< Filter bit 13 */
+#define CAN_F2R1_FB14_Pos (14U)
+#define CAN_F2R1_FB14_Msk (0x1U << CAN_F2R1_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F2R1_FB14 CAN_F2R1_FB14_Msk /*!< Filter bit 14 */
+#define CAN_F2R1_FB15_Pos (15U)
+#define CAN_F2R1_FB15_Msk (0x1U << CAN_F2R1_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F2R1_FB15 CAN_F2R1_FB15_Msk /*!< Filter bit 15 */
+#define CAN_F2R1_FB16_Pos (16U)
+#define CAN_F2R1_FB16_Msk (0x1U << CAN_F2R1_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F2R1_FB16 CAN_F2R1_FB16_Msk /*!< Filter bit 16 */
+#define CAN_F2R1_FB17_Pos (17U)
+#define CAN_F2R1_FB17_Msk (0x1U << CAN_F2R1_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F2R1_FB17 CAN_F2R1_FB17_Msk /*!< Filter bit 17 */
+#define CAN_F2R1_FB18_Pos (18U)
+#define CAN_F2R1_FB18_Msk (0x1U << CAN_F2R1_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F2R1_FB18 CAN_F2R1_FB18_Msk /*!< Filter bit 18 */
+#define CAN_F2R1_FB19_Pos (19U)
+#define CAN_F2R1_FB19_Msk (0x1U << CAN_F2R1_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F2R1_FB19 CAN_F2R1_FB19_Msk /*!< Filter bit 19 */
+#define CAN_F2R1_FB20_Pos (20U)
+#define CAN_F2R1_FB20_Msk (0x1U << CAN_F2R1_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F2R1_FB20 CAN_F2R1_FB20_Msk /*!< Filter bit 20 */
+#define CAN_F2R1_FB21_Pos (21U)
+#define CAN_F2R1_FB21_Msk (0x1U << CAN_F2R1_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F2R1_FB21 CAN_F2R1_FB21_Msk /*!< Filter bit 21 */
+#define CAN_F2R1_FB22_Pos (22U)
+#define CAN_F2R1_FB22_Msk (0x1U << CAN_F2R1_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F2R1_FB22 CAN_F2R1_FB22_Msk /*!< Filter bit 22 */
+#define CAN_F2R1_FB23_Pos (23U)
+#define CAN_F2R1_FB23_Msk (0x1U << CAN_F2R1_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F2R1_FB23 CAN_F2R1_FB23_Msk /*!< Filter bit 23 */
+#define CAN_F2R1_FB24_Pos (24U)
+#define CAN_F2R1_FB24_Msk (0x1U << CAN_F2R1_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F2R1_FB24 CAN_F2R1_FB24_Msk /*!< Filter bit 24 */
+#define CAN_F2R1_FB25_Pos (25U)
+#define CAN_F2R1_FB25_Msk (0x1U << CAN_F2R1_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F2R1_FB25 CAN_F2R1_FB25_Msk /*!< Filter bit 25 */
+#define CAN_F2R1_FB26_Pos (26U)
+#define CAN_F2R1_FB26_Msk (0x1U << CAN_F2R1_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F2R1_FB26 CAN_F2R1_FB26_Msk /*!< Filter bit 26 */
+#define CAN_F2R1_FB27_Pos (27U)
+#define CAN_F2R1_FB27_Msk (0x1U << CAN_F2R1_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F2R1_FB27 CAN_F2R1_FB27_Msk /*!< Filter bit 27 */
+#define CAN_F2R1_FB28_Pos (28U)
+#define CAN_F2R1_FB28_Msk (0x1U << CAN_F2R1_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F2R1_FB28 CAN_F2R1_FB28_Msk /*!< Filter bit 28 */
+#define CAN_F2R1_FB29_Pos (29U)
+#define CAN_F2R1_FB29_Msk (0x1U << CAN_F2R1_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F2R1_FB29 CAN_F2R1_FB29_Msk /*!< Filter bit 29 */
+#define CAN_F2R1_FB30_Pos (30U)
+#define CAN_F2R1_FB30_Msk (0x1U << CAN_F2R1_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F2R1_FB30 CAN_F2R1_FB30_Msk /*!< Filter bit 30 */
+#define CAN_F2R1_FB31_Pos (31U)
+#define CAN_F2R1_FB31_Msk (0x1U << CAN_F2R1_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F2R1_FB31 CAN_F2R1_FB31_Msk /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F3R1 register *******************/
+#define CAN_F3R1_FB0_Pos (0U)
+#define CAN_F3R1_FB0_Msk (0x1U << CAN_F3R1_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F3R1_FB0 CAN_F3R1_FB0_Msk /*!< Filter bit 0 */
+#define CAN_F3R1_FB1_Pos (1U)
+#define CAN_F3R1_FB1_Msk (0x1U << CAN_F3R1_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F3R1_FB1 CAN_F3R1_FB1_Msk /*!< Filter bit 1 */
+#define CAN_F3R1_FB2_Pos (2U)
+#define CAN_F3R1_FB2_Msk (0x1U << CAN_F3R1_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F3R1_FB2 CAN_F3R1_FB2_Msk /*!< Filter bit 2 */
+#define CAN_F3R1_FB3_Pos (3U)
+#define CAN_F3R1_FB3_Msk (0x1U << CAN_F3R1_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F3R1_FB3 CAN_F3R1_FB3_Msk /*!< Filter bit 3 */
+#define CAN_F3R1_FB4_Pos (4U)
+#define CAN_F3R1_FB4_Msk (0x1U << CAN_F3R1_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F3R1_FB4 CAN_F3R1_FB4_Msk /*!< Filter bit 4 */
+#define CAN_F3R1_FB5_Pos (5U)
+#define CAN_F3R1_FB5_Msk (0x1U << CAN_F3R1_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F3R1_FB5 CAN_F3R1_FB5_Msk /*!< Filter bit 5 */
+#define CAN_F3R1_FB6_Pos (6U)
+#define CAN_F3R1_FB6_Msk (0x1U << CAN_F3R1_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F3R1_FB6 CAN_F3R1_FB6_Msk /*!< Filter bit 6 */
+#define CAN_F3R1_FB7_Pos (7U)
+#define CAN_F3R1_FB7_Msk (0x1U << CAN_F3R1_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F3R1_FB7 CAN_F3R1_FB7_Msk /*!< Filter bit 7 */
+#define CAN_F3R1_FB8_Pos (8U)
+#define CAN_F3R1_FB8_Msk (0x1U << CAN_F3R1_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F3R1_FB8 CAN_F3R1_FB8_Msk /*!< Filter bit 8 */
+#define CAN_F3R1_FB9_Pos (9U)
+#define CAN_F3R1_FB9_Msk (0x1U << CAN_F3R1_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F3R1_FB9 CAN_F3R1_FB9_Msk /*!< Filter bit 9 */
+#define CAN_F3R1_FB10_Pos (10U)
+#define CAN_F3R1_FB10_Msk (0x1U << CAN_F3R1_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F3R1_FB10 CAN_F3R1_FB10_Msk /*!< Filter bit 10 */
+#define CAN_F3R1_FB11_Pos (11U)
+#define CAN_F3R1_FB11_Msk (0x1U << CAN_F3R1_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F3R1_FB11 CAN_F3R1_FB11_Msk /*!< Filter bit 11 */
+#define CAN_F3R1_FB12_Pos (12U)
+#define CAN_F3R1_FB12_Msk (0x1U << CAN_F3R1_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F3R1_FB12 CAN_F3R1_FB12_Msk /*!< Filter bit 12 */
+#define CAN_F3R1_FB13_Pos (13U)
+#define CAN_F3R1_FB13_Msk (0x1U << CAN_F3R1_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F3R1_FB13 CAN_F3R1_FB13_Msk /*!< Filter bit 13 */
+#define CAN_F3R1_FB14_Pos (14U)
+#define CAN_F3R1_FB14_Msk (0x1U << CAN_F3R1_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F3R1_FB14 CAN_F3R1_FB14_Msk /*!< Filter bit 14 */
+#define CAN_F3R1_FB15_Pos (15U)
+#define CAN_F3R1_FB15_Msk (0x1U << CAN_F3R1_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F3R1_FB15 CAN_F3R1_FB15_Msk /*!< Filter bit 15 */
+#define CAN_F3R1_FB16_Pos (16U)
+#define CAN_F3R1_FB16_Msk (0x1U << CAN_F3R1_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F3R1_FB16 CAN_F3R1_FB16_Msk /*!< Filter bit 16 */
+#define CAN_F3R1_FB17_Pos (17U)
+#define CAN_F3R1_FB17_Msk (0x1U << CAN_F3R1_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F3R1_FB17 CAN_F3R1_FB17_Msk /*!< Filter bit 17 */
+#define CAN_F3R1_FB18_Pos (18U)
+#define CAN_F3R1_FB18_Msk (0x1U << CAN_F3R1_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F3R1_FB18 CAN_F3R1_FB18_Msk /*!< Filter bit 18 */
+#define CAN_F3R1_FB19_Pos (19U)
+#define CAN_F3R1_FB19_Msk (0x1U << CAN_F3R1_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F3R1_FB19 CAN_F3R1_FB19_Msk /*!< Filter bit 19 */
+#define CAN_F3R1_FB20_Pos (20U)
+#define CAN_F3R1_FB20_Msk (0x1U << CAN_F3R1_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F3R1_FB20 CAN_F3R1_FB20_Msk /*!< Filter bit 20 */
+#define CAN_F3R1_FB21_Pos (21U)
+#define CAN_F3R1_FB21_Msk (0x1U << CAN_F3R1_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F3R1_FB21 CAN_F3R1_FB21_Msk /*!< Filter bit 21 */
+#define CAN_F3R1_FB22_Pos (22U)
+#define CAN_F3R1_FB22_Msk (0x1U << CAN_F3R1_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F3R1_FB22 CAN_F3R1_FB22_Msk /*!< Filter bit 22 */
+#define CAN_F3R1_FB23_Pos (23U)
+#define CAN_F3R1_FB23_Msk (0x1U << CAN_F3R1_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F3R1_FB23 CAN_F3R1_FB23_Msk /*!< Filter bit 23 */
+#define CAN_F3R1_FB24_Pos (24U)
+#define CAN_F3R1_FB24_Msk (0x1U << CAN_F3R1_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F3R1_FB24 CAN_F3R1_FB24_Msk /*!< Filter bit 24 */
+#define CAN_F3R1_FB25_Pos (25U)
+#define CAN_F3R1_FB25_Msk (0x1U << CAN_F3R1_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F3R1_FB25 CAN_F3R1_FB25_Msk /*!< Filter bit 25 */
+#define CAN_F3R1_FB26_Pos (26U)
+#define CAN_F3R1_FB26_Msk (0x1U << CAN_F3R1_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F3R1_FB26 CAN_F3R1_FB26_Msk /*!< Filter bit 26 */
+#define CAN_F3R1_FB27_Pos (27U)
+#define CAN_F3R1_FB27_Msk (0x1U << CAN_F3R1_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F3R1_FB27 CAN_F3R1_FB27_Msk /*!< Filter bit 27 */
+#define CAN_F3R1_FB28_Pos (28U)
+#define CAN_F3R1_FB28_Msk (0x1U << CAN_F3R1_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F3R1_FB28 CAN_F3R1_FB28_Msk /*!< Filter bit 28 */
+#define CAN_F3R1_FB29_Pos (29U)
+#define CAN_F3R1_FB29_Msk (0x1U << CAN_F3R1_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F3R1_FB29 CAN_F3R1_FB29_Msk /*!< Filter bit 29 */
+#define CAN_F3R1_FB30_Pos (30U)
+#define CAN_F3R1_FB30_Msk (0x1U << CAN_F3R1_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F3R1_FB30 CAN_F3R1_FB30_Msk /*!< Filter bit 30 */
+#define CAN_F3R1_FB31_Pos (31U)
+#define CAN_F3R1_FB31_Msk (0x1U << CAN_F3R1_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F3R1_FB31 CAN_F3R1_FB31_Msk /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F4R1 register *******************/
+#define CAN_F4R1_FB0_Pos (0U)
+#define CAN_F4R1_FB0_Msk (0x1U << CAN_F4R1_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F4R1_FB0 CAN_F4R1_FB0_Msk /*!< Filter bit 0 */
+#define CAN_F4R1_FB1_Pos (1U)
+#define CAN_F4R1_FB1_Msk (0x1U << CAN_F4R1_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F4R1_FB1 CAN_F4R1_FB1_Msk /*!< Filter bit 1 */
+#define CAN_F4R1_FB2_Pos (2U)
+#define CAN_F4R1_FB2_Msk (0x1U << CAN_F4R1_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F4R1_FB2 CAN_F4R1_FB2_Msk /*!< Filter bit 2 */
+#define CAN_F4R1_FB3_Pos (3U)
+#define CAN_F4R1_FB3_Msk (0x1U << CAN_F4R1_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F4R1_FB3 CAN_F4R1_FB3_Msk /*!< Filter bit 3 */
+#define CAN_F4R1_FB4_Pos (4U)
+#define CAN_F4R1_FB4_Msk (0x1U << CAN_F4R1_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F4R1_FB4 CAN_F4R1_FB4_Msk /*!< Filter bit 4 */
+#define CAN_F4R1_FB5_Pos (5U)
+#define CAN_F4R1_FB5_Msk (0x1U << CAN_F4R1_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F4R1_FB5 CAN_F4R1_FB5_Msk /*!< Filter bit 5 */
+#define CAN_F4R1_FB6_Pos (6U)
+#define CAN_F4R1_FB6_Msk (0x1U << CAN_F4R1_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F4R1_FB6 CAN_F4R1_FB6_Msk /*!< Filter bit 6 */
+#define CAN_F4R1_FB7_Pos (7U)
+#define CAN_F4R1_FB7_Msk (0x1U << CAN_F4R1_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F4R1_FB7 CAN_F4R1_FB7_Msk /*!< Filter bit 7 */
+#define CAN_F4R1_FB8_Pos (8U)
+#define CAN_F4R1_FB8_Msk (0x1U << CAN_F4R1_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F4R1_FB8 CAN_F4R1_FB8_Msk /*!< Filter bit 8 */
+#define CAN_F4R1_FB9_Pos (9U)
+#define CAN_F4R1_FB9_Msk (0x1U << CAN_F4R1_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F4R1_FB9 CAN_F4R1_FB9_Msk /*!< Filter bit 9 */
+#define CAN_F4R1_FB10_Pos (10U)
+#define CAN_F4R1_FB10_Msk (0x1U << CAN_F4R1_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F4R1_FB10 CAN_F4R1_FB10_Msk /*!< Filter bit 10 */
+#define CAN_F4R1_FB11_Pos (11U)
+#define CAN_F4R1_FB11_Msk (0x1U << CAN_F4R1_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F4R1_FB11 CAN_F4R1_FB11_Msk /*!< Filter bit 11 */
+#define CAN_F4R1_FB12_Pos (12U)
+#define CAN_F4R1_FB12_Msk (0x1U << CAN_F4R1_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F4R1_FB12 CAN_F4R1_FB12_Msk /*!< Filter bit 12 */
+#define CAN_F4R1_FB13_Pos (13U)
+#define CAN_F4R1_FB13_Msk (0x1U << CAN_F4R1_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F4R1_FB13 CAN_F4R1_FB13_Msk /*!< Filter bit 13 */
+#define CAN_F4R1_FB14_Pos (14U)
+#define CAN_F4R1_FB14_Msk (0x1U << CAN_F4R1_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F4R1_FB14 CAN_F4R1_FB14_Msk /*!< Filter bit 14 */
+#define CAN_F4R1_FB15_Pos (15U)
+#define CAN_F4R1_FB15_Msk (0x1U << CAN_F4R1_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F4R1_FB15 CAN_F4R1_FB15_Msk /*!< Filter bit 15 */
+#define CAN_F4R1_FB16_Pos (16U)
+#define CAN_F4R1_FB16_Msk (0x1U << CAN_F4R1_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F4R1_FB16 CAN_F4R1_FB16_Msk /*!< Filter bit 16 */
+#define CAN_F4R1_FB17_Pos (17U)
+#define CAN_F4R1_FB17_Msk (0x1U << CAN_F4R1_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F4R1_FB17 CAN_F4R1_FB17_Msk /*!< Filter bit 17 */
+#define CAN_F4R1_FB18_Pos (18U)
+#define CAN_F4R1_FB18_Msk (0x1U << CAN_F4R1_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F4R1_FB18 CAN_F4R1_FB18_Msk /*!< Filter bit 18 */
+#define CAN_F4R1_FB19_Pos (19U)
+#define CAN_F4R1_FB19_Msk (0x1U << CAN_F4R1_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F4R1_FB19 CAN_F4R1_FB19_Msk /*!< Filter bit 19 */
+#define CAN_F4R1_FB20_Pos (20U)
+#define CAN_F4R1_FB20_Msk (0x1U << CAN_F4R1_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F4R1_FB20 CAN_F4R1_FB20_Msk /*!< Filter bit 20 */
+#define CAN_F4R1_FB21_Pos (21U)
+#define CAN_F4R1_FB21_Msk (0x1U << CAN_F4R1_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F4R1_FB21 CAN_F4R1_FB21_Msk /*!< Filter bit 21 */
+#define CAN_F4R1_FB22_Pos (22U)
+#define CAN_F4R1_FB22_Msk (0x1U << CAN_F4R1_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F4R1_FB22 CAN_F4R1_FB22_Msk /*!< Filter bit 22 */
+#define CAN_F4R1_FB23_Pos (23U)
+#define CAN_F4R1_FB23_Msk (0x1U << CAN_F4R1_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F4R1_FB23 CAN_F4R1_FB23_Msk /*!< Filter bit 23 */
+#define CAN_F4R1_FB24_Pos (24U)
+#define CAN_F4R1_FB24_Msk (0x1U << CAN_F4R1_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F4R1_FB24 CAN_F4R1_FB24_Msk /*!< Filter bit 24 */
+#define CAN_F4R1_FB25_Pos (25U)
+#define CAN_F4R1_FB25_Msk (0x1U << CAN_F4R1_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F4R1_FB25 CAN_F4R1_FB25_Msk /*!< Filter bit 25 */
+#define CAN_F4R1_FB26_Pos (26U)
+#define CAN_F4R1_FB26_Msk (0x1U << CAN_F4R1_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F4R1_FB26 CAN_F4R1_FB26_Msk /*!< Filter bit 26 */
+#define CAN_F4R1_FB27_Pos (27U)
+#define CAN_F4R1_FB27_Msk (0x1U << CAN_F4R1_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F4R1_FB27 CAN_F4R1_FB27_Msk /*!< Filter bit 27 */
+#define CAN_F4R1_FB28_Pos (28U)
+#define CAN_F4R1_FB28_Msk (0x1U << CAN_F4R1_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F4R1_FB28 CAN_F4R1_FB28_Msk /*!< Filter bit 28 */
+#define CAN_F4R1_FB29_Pos (29U)
+#define CAN_F4R1_FB29_Msk (0x1U << CAN_F4R1_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F4R1_FB29 CAN_F4R1_FB29_Msk /*!< Filter bit 29 */
+#define CAN_F4R1_FB30_Pos (30U)
+#define CAN_F4R1_FB30_Msk (0x1U << CAN_F4R1_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F4R1_FB30 CAN_F4R1_FB30_Msk /*!< Filter bit 30 */
+#define CAN_F4R1_FB31_Pos (31U)
+#define CAN_F4R1_FB31_Msk (0x1U << CAN_F4R1_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F4R1_FB31 CAN_F4R1_FB31_Msk /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F5R1 register *******************/
+#define CAN_F5R1_FB0_Pos (0U)
+#define CAN_F5R1_FB0_Msk (0x1U << CAN_F5R1_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F5R1_FB0 CAN_F5R1_FB0_Msk /*!< Filter bit 0 */
+#define CAN_F5R1_FB1_Pos (1U)
+#define CAN_F5R1_FB1_Msk (0x1U << CAN_F5R1_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F5R1_FB1 CAN_F5R1_FB1_Msk /*!< Filter bit 1 */
+#define CAN_F5R1_FB2_Pos (2U)
+#define CAN_F5R1_FB2_Msk (0x1U << CAN_F5R1_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F5R1_FB2 CAN_F5R1_FB2_Msk /*!< Filter bit 2 */
+#define CAN_F5R1_FB3_Pos (3U)
+#define CAN_F5R1_FB3_Msk (0x1U << CAN_F5R1_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F5R1_FB3 CAN_F5R1_FB3_Msk /*!< Filter bit 3 */
+#define CAN_F5R1_FB4_Pos (4U)
+#define CAN_F5R1_FB4_Msk (0x1U << CAN_F5R1_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F5R1_FB4 CAN_F5R1_FB4_Msk /*!< Filter bit 4 */
+#define CAN_F5R1_FB5_Pos (5U)
+#define CAN_F5R1_FB5_Msk (0x1U << CAN_F5R1_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F5R1_FB5 CAN_F5R1_FB5_Msk /*!< Filter bit 5 */
+#define CAN_F5R1_FB6_Pos (6U)
+#define CAN_F5R1_FB6_Msk (0x1U << CAN_F5R1_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F5R1_FB6 CAN_F5R1_FB6_Msk /*!< Filter bit 6 */
+#define CAN_F5R1_FB7_Pos (7U)
+#define CAN_F5R1_FB7_Msk (0x1U << CAN_F5R1_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F5R1_FB7 CAN_F5R1_FB7_Msk /*!< Filter bit 7 */
+#define CAN_F5R1_FB8_Pos (8U)
+#define CAN_F5R1_FB8_Msk (0x1U << CAN_F5R1_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F5R1_FB8 CAN_F5R1_FB8_Msk /*!< Filter bit 8 */
+#define CAN_F5R1_FB9_Pos (9U)
+#define CAN_F5R1_FB9_Msk (0x1U << CAN_F5R1_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F5R1_FB9 CAN_F5R1_FB9_Msk /*!< Filter bit 9 */
+#define CAN_F5R1_FB10_Pos (10U)
+#define CAN_F5R1_FB10_Msk (0x1U << CAN_F5R1_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F5R1_FB10 CAN_F5R1_FB10_Msk /*!< Filter bit 10 */
+#define CAN_F5R1_FB11_Pos (11U)
+#define CAN_F5R1_FB11_Msk (0x1U << CAN_F5R1_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F5R1_FB11 CAN_F5R1_FB11_Msk /*!< Filter bit 11 */
+#define CAN_F5R1_FB12_Pos (12U)
+#define CAN_F5R1_FB12_Msk (0x1U << CAN_F5R1_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F5R1_FB12 CAN_F5R1_FB12_Msk /*!< Filter bit 12 */
+#define CAN_F5R1_FB13_Pos (13U)
+#define CAN_F5R1_FB13_Msk (0x1U << CAN_F5R1_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F5R1_FB13 CAN_F5R1_FB13_Msk /*!< Filter bit 13 */
+#define CAN_F5R1_FB14_Pos (14U)
+#define CAN_F5R1_FB14_Msk (0x1U << CAN_F5R1_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F5R1_FB14 CAN_F5R1_FB14_Msk /*!< Filter bit 14 */
+#define CAN_F5R1_FB15_Pos (15U)
+#define CAN_F5R1_FB15_Msk (0x1U << CAN_F5R1_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F5R1_FB15 CAN_F5R1_FB15_Msk /*!< Filter bit 15 */
+#define CAN_F5R1_FB16_Pos (16U)
+#define CAN_F5R1_FB16_Msk (0x1U << CAN_F5R1_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F5R1_FB16 CAN_F5R1_FB16_Msk /*!< Filter bit 16 */
+#define CAN_F5R1_FB17_Pos (17U)
+#define CAN_F5R1_FB17_Msk (0x1U << CAN_F5R1_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F5R1_FB17 CAN_F5R1_FB17_Msk /*!< Filter bit 17 */
+#define CAN_F5R1_FB18_Pos (18U)
+#define CAN_F5R1_FB18_Msk (0x1U << CAN_F5R1_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F5R1_FB18 CAN_F5R1_FB18_Msk /*!< Filter bit 18 */
+#define CAN_F5R1_FB19_Pos (19U)
+#define CAN_F5R1_FB19_Msk (0x1U << CAN_F5R1_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F5R1_FB19 CAN_F5R1_FB19_Msk /*!< Filter bit 19 */
+#define CAN_F5R1_FB20_Pos (20U)
+#define CAN_F5R1_FB20_Msk (0x1U << CAN_F5R1_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F5R1_FB20 CAN_F5R1_FB20_Msk /*!< Filter bit 20 */
+#define CAN_F5R1_FB21_Pos (21U)
+#define CAN_F5R1_FB21_Msk (0x1U << CAN_F5R1_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F5R1_FB21 CAN_F5R1_FB21_Msk /*!< Filter bit 21 */
+#define CAN_F5R1_FB22_Pos (22U)
+#define CAN_F5R1_FB22_Msk (0x1U << CAN_F5R1_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F5R1_FB22 CAN_F5R1_FB22_Msk /*!< Filter bit 22 */
+#define CAN_F5R1_FB23_Pos (23U)
+#define CAN_F5R1_FB23_Msk (0x1U << CAN_F5R1_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F5R1_FB23 CAN_F5R1_FB23_Msk /*!< Filter bit 23 */
+#define CAN_F5R1_FB24_Pos (24U)
+#define CAN_F5R1_FB24_Msk (0x1U << CAN_F5R1_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F5R1_FB24 CAN_F5R1_FB24_Msk /*!< Filter bit 24 */
+#define CAN_F5R1_FB25_Pos (25U)
+#define CAN_F5R1_FB25_Msk (0x1U << CAN_F5R1_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F5R1_FB25 CAN_F5R1_FB25_Msk /*!< Filter bit 25 */
+#define CAN_F5R1_FB26_Pos (26U)
+#define CAN_F5R1_FB26_Msk (0x1U << CAN_F5R1_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F5R1_FB26 CAN_F5R1_FB26_Msk /*!< Filter bit 26 */
+#define CAN_F5R1_FB27_Pos (27U)
+#define CAN_F5R1_FB27_Msk (0x1U << CAN_F5R1_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F5R1_FB27 CAN_F5R1_FB27_Msk /*!< Filter bit 27 */
+#define CAN_F5R1_FB28_Pos (28U)
+#define CAN_F5R1_FB28_Msk (0x1U << CAN_F5R1_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F5R1_FB28 CAN_F5R1_FB28_Msk /*!< Filter bit 28 */
+#define CAN_F5R1_FB29_Pos (29U)
+#define CAN_F5R1_FB29_Msk (0x1U << CAN_F5R1_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F5R1_FB29 CAN_F5R1_FB29_Msk /*!< Filter bit 29 */
+#define CAN_F5R1_FB30_Pos (30U)
+#define CAN_F5R1_FB30_Msk (0x1U << CAN_F5R1_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F5R1_FB30 CAN_F5R1_FB30_Msk /*!< Filter bit 30 */
+#define CAN_F5R1_FB31_Pos (31U)
+#define CAN_F5R1_FB31_Msk (0x1U << CAN_F5R1_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F5R1_FB31 CAN_F5R1_FB31_Msk /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F6R1 register *******************/
+#define CAN_F6R1_FB0_Pos (0U)
+#define CAN_F6R1_FB0_Msk (0x1U << CAN_F6R1_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F6R1_FB0 CAN_F6R1_FB0_Msk /*!< Filter bit 0 */
+#define CAN_F6R1_FB1_Pos (1U)
+#define CAN_F6R1_FB1_Msk (0x1U << CAN_F6R1_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F6R1_FB1 CAN_F6R1_FB1_Msk /*!< Filter bit 1 */
+#define CAN_F6R1_FB2_Pos (2U)
+#define CAN_F6R1_FB2_Msk (0x1U << CAN_F6R1_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F6R1_FB2 CAN_F6R1_FB2_Msk /*!< Filter bit 2 */
+#define CAN_F6R1_FB3_Pos (3U)
+#define CAN_F6R1_FB3_Msk (0x1U << CAN_F6R1_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F6R1_FB3 CAN_F6R1_FB3_Msk /*!< Filter bit 3 */
+#define CAN_F6R1_FB4_Pos (4U)
+#define CAN_F6R1_FB4_Msk (0x1U << CAN_F6R1_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F6R1_FB4 CAN_F6R1_FB4_Msk /*!< Filter bit 4 */
+#define CAN_F6R1_FB5_Pos (5U)
+#define CAN_F6R1_FB5_Msk (0x1U << CAN_F6R1_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F6R1_FB5 CAN_F6R1_FB5_Msk /*!< Filter bit 5 */
+#define CAN_F6R1_FB6_Pos (6U)
+#define CAN_F6R1_FB6_Msk (0x1U << CAN_F6R1_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F6R1_FB6 CAN_F6R1_FB6_Msk /*!< Filter bit 6 */
+#define CAN_F6R1_FB7_Pos (7U)
+#define CAN_F6R1_FB7_Msk (0x1U << CAN_F6R1_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F6R1_FB7 CAN_F6R1_FB7_Msk /*!< Filter bit 7 */
+#define CAN_F6R1_FB8_Pos (8U)
+#define CAN_F6R1_FB8_Msk (0x1U << CAN_F6R1_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F6R1_FB8 CAN_F6R1_FB8_Msk /*!< Filter bit 8 */
+#define CAN_F6R1_FB9_Pos (9U)
+#define CAN_F6R1_FB9_Msk (0x1U << CAN_F6R1_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F6R1_FB9 CAN_F6R1_FB9_Msk /*!< Filter bit 9 */
+#define CAN_F6R1_FB10_Pos (10U)
+#define CAN_F6R1_FB10_Msk (0x1U << CAN_F6R1_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F6R1_FB10 CAN_F6R1_FB10_Msk /*!< Filter bit 10 */
+#define CAN_F6R1_FB11_Pos (11U)
+#define CAN_F6R1_FB11_Msk (0x1U << CAN_F6R1_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F6R1_FB11 CAN_F6R1_FB11_Msk /*!< Filter bit 11 */
+#define CAN_F6R1_FB12_Pos (12U)
+#define CAN_F6R1_FB12_Msk (0x1U << CAN_F6R1_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F6R1_FB12 CAN_F6R1_FB12_Msk /*!< Filter bit 12 */
+#define CAN_F6R1_FB13_Pos (13U)
+#define CAN_F6R1_FB13_Msk (0x1U << CAN_F6R1_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F6R1_FB13 CAN_F6R1_FB13_Msk /*!< Filter bit 13 */
+#define CAN_F6R1_FB14_Pos (14U)
+#define CAN_F6R1_FB14_Msk (0x1U << CAN_F6R1_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F6R1_FB14 CAN_F6R1_FB14_Msk /*!< Filter bit 14 */
+#define CAN_F6R1_FB15_Pos (15U)
+#define CAN_F6R1_FB15_Msk (0x1U << CAN_F6R1_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F6R1_FB15 CAN_F6R1_FB15_Msk /*!< Filter bit 15 */
+#define CAN_F6R1_FB16_Pos (16U)
+#define CAN_F6R1_FB16_Msk (0x1U << CAN_F6R1_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F6R1_FB16 CAN_F6R1_FB16_Msk /*!< Filter bit 16 */
+#define CAN_F6R1_FB17_Pos (17U)
+#define CAN_F6R1_FB17_Msk (0x1U << CAN_F6R1_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F6R1_FB17 CAN_F6R1_FB17_Msk /*!< Filter bit 17 */
+#define CAN_F6R1_FB18_Pos (18U)
+#define CAN_F6R1_FB18_Msk (0x1U << CAN_F6R1_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F6R1_FB18 CAN_F6R1_FB18_Msk /*!< Filter bit 18 */
+#define CAN_F6R1_FB19_Pos (19U)
+#define CAN_F6R1_FB19_Msk (0x1U << CAN_F6R1_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F6R1_FB19 CAN_F6R1_FB19_Msk /*!< Filter bit 19 */
+#define CAN_F6R1_FB20_Pos (20U)
+#define CAN_F6R1_FB20_Msk (0x1U << CAN_F6R1_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F6R1_FB20 CAN_F6R1_FB20_Msk /*!< Filter bit 20 */
+#define CAN_F6R1_FB21_Pos (21U)
+#define CAN_F6R1_FB21_Msk (0x1U << CAN_F6R1_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F6R1_FB21 CAN_F6R1_FB21_Msk /*!< Filter bit 21 */
+#define CAN_F6R1_FB22_Pos (22U)
+#define CAN_F6R1_FB22_Msk (0x1U << CAN_F6R1_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F6R1_FB22 CAN_F6R1_FB22_Msk /*!< Filter bit 22 */
+#define CAN_F6R1_FB23_Pos (23U)
+#define CAN_F6R1_FB23_Msk (0x1U << CAN_F6R1_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F6R1_FB23 CAN_F6R1_FB23_Msk /*!< Filter bit 23 */
+#define CAN_F6R1_FB24_Pos (24U)
+#define CAN_F6R1_FB24_Msk (0x1U << CAN_F6R1_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F6R1_FB24 CAN_F6R1_FB24_Msk /*!< Filter bit 24 */
+#define CAN_F6R1_FB25_Pos (25U)
+#define CAN_F6R1_FB25_Msk (0x1U << CAN_F6R1_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F6R1_FB25 CAN_F6R1_FB25_Msk /*!< Filter bit 25 */
+#define CAN_F6R1_FB26_Pos (26U)
+#define CAN_F6R1_FB26_Msk (0x1U << CAN_F6R1_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F6R1_FB26 CAN_F6R1_FB26_Msk /*!< Filter bit 26 */
+#define CAN_F6R1_FB27_Pos (27U)
+#define CAN_F6R1_FB27_Msk (0x1U << CAN_F6R1_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F6R1_FB27 CAN_F6R1_FB27_Msk /*!< Filter bit 27 */
+#define CAN_F6R1_FB28_Pos (28U)
+#define CAN_F6R1_FB28_Msk (0x1U << CAN_F6R1_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F6R1_FB28 CAN_F6R1_FB28_Msk /*!< Filter bit 28 */
+#define CAN_F6R1_FB29_Pos (29U)
+#define CAN_F6R1_FB29_Msk (0x1U << CAN_F6R1_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F6R1_FB29 CAN_F6R1_FB29_Msk /*!< Filter bit 29 */
+#define CAN_F6R1_FB30_Pos (30U)
+#define CAN_F6R1_FB30_Msk (0x1U << CAN_F6R1_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F6R1_FB30 CAN_F6R1_FB30_Msk /*!< Filter bit 30 */
+#define CAN_F6R1_FB31_Pos (31U)
+#define CAN_F6R1_FB31_Msk (0x1U << CAN_F6R1_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F6R1_FB31 CAN_F6R1_FB31_Msk /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F7R1 register *******************/
+#define CAN_F7R1_FB0_Pos (0U)
+#define CAN_F7R1_FB0_Msk (0x1U << CAN_F7R1_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F7R1_FB0 CAN_F7R1_FB0_Msk /*!< Filter bit 0 */
+#define CAN_F7R1_FB1_Pos (1U)
+#define CAN_F7R1_FB1_Msk (0x1U << CAN_F7R1_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F7R1_FB1 CAN_F7R1_FB1_Msk /*!< Filter bit 1 */
+#define CAN_F7R1_FB2_Pos (2U)
+#define CAN_F7R1_FB2_Msk (0x1U << CAN_F7R1_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F7R1_FB2 CAN_F7R1_FB2_Msk /*!< Filter bit 2 */
+#define CAN_F7R1_FB3_Pos (3U)
+#define CAN_F7R1_FB3_Msk (0x1U << CAN_F7R1_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F7R1_FB3 CAN_F7R1_FB3_Msk /*!< Filter bit 3 */
+#define CAN_F7R1_FB4_Pos (4U)
+#define CAN_F7R1_FB4_Msk (0x1U << CAN_F7R1_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F7R1_FB4 CAN_F7R1_FB4_Msk /*!< Filter bit 4 */
+#define CAN_F7R1_FB5_Pos (5U)
+#define CAN_F7R1_FB5_Msk (0x1U << CAN_F7R1_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F7R1_FB5 CAN_F7R1_FB5_Msk /*!< Filter bit 5 */
+#define CAN_F7R1_FB6_Pos (6U)
+#define CAN_F7R1_FB6_Msk (0x1U << CAN_F7R1_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F7R1_FB6 CAN_F7R1_FB6_Msk /*!< Filter bit 6 */
+#define CAN_F7R1_FB7_Pos (7U)
+#define CAN_F7R1_FB7_Msk (0x1U << CAN_F7R1_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F7R1_FB7 CAN_F7R1_FB7_Msk /*!< Filter bit 7 */
+#define CAN_F7R1_FB8_Pos (8U)
+#define CAN_F7R1_FB8_Msk (0x1U << CAN_F7R1_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F7R1_FB8 CAN_F7R1_FB8_Msk /*!< Filter bit 8 */
+#define CAN_F7R1_FB9_Pos (9U)
+#define CAN_F7R1_FB9_Msk (0x1U << CAN_F7R1_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F7R1_FB9 CAN_F7R1_FB9_Msk /*!< Filter bit 9 */
+#define CAN_F7R1_FB10_Pos (10U)
+#define CAN_F7R1_FB10_Msk (0x1U << CAN_F7R1_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F7R1_FB10 CAN_F7R1_FB10_Msk /*!< Filter bit 10 */
+#define CAN_F7R1_FB11_Pos (11U)
+#define CAN_F7R1_FB11_Msk (0x1U << CAN_F7R1_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F7R1_FB11 CAN_F7R1_FB11_Msk /*!< Filter bit 11 */
+#define CAN_F7R1_FB12_Pos (12U)
+#define CAN_F7R1_FB12_Msk (0x1U << CAN_F7R1_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F7R1_FB12 CAN_F7R1_FB12_Msk /*!< Filter bit 12 */
+#define CAN_F7R1_FB13_Pos (13U)
+#define CAN_F7R1_FB13_Msk (0x1U << CAN_F7R1_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F7R1_FB13 CAN_F7R1_FB13_Msk /*!< Filter bit 13 */
+#define CAN_F7R1_FB14_Pos (14U)
+#define CAN_F7R1_FB14_Msk (0x1U << CAN_F7R1_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F7R1_FB14 CAN_F7R1_FB14_Msk /*!< Filter bit 14 */
+#define CAN_F7R1_FB15_Pos (15U)
+#define CAN_F7R1_FB15_Msk (0x1U << CAN_F7R1_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F7R1_FB15 CAN_F7R1_FB15_Msk /*!< Filter bit 15 */
+#define CAN_F7R1_FB16_Pos (16U)
+#define CAN_F7R1_FB16_Msk (0x1U << CAN_F7R1_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F7R1_FB16 CAN_F7R1_FB16_Msk /*!< Filter bit 16 */
+#define CAN_F7R1_FB17_Pos (17U)
+#define CAN_F7R1_FB17_Msk (0x1U << CAN_F7R1_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F7R1_FB17 CAN_F7R1_FB17_Msk /*!< Filter bit 17 */
+#define CAN_F7R1_FB18_Pos (18U)
+#define CAN_F7R1_FB18_Msk (0x1U << CAN_F7R1_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F7R1_FB18 CAN_F7R1_FB18_Msk /*!< Filter bit 18 */
+#define CAN_F7R1_FB19_Pos (19U)
+#define CAN_F7R1_FB19_Msk (0x1U << CAN_F7R1_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F7R1_FB19 CAN_F7R1_FB19_Msk /*!< Filter bit 19 */
+#define CAN_F7R1_FB20_Pos (20U)
+#define CAN_F7R1_FB20_Msk (0x1U << CAN_F7R1_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F7R1_FB20 CAN_F7R1_FB20_Msk /*!< Filter bit 20 */
+#define CAN_F7R1_FB21_Pos (21U)
+#define CAN_F7R1_FB21_Msk (0x1U << CAN_F7R1_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F7R1_FB21 CAN_F7R1_FB21_Msk /*!< Filter bit 21 */
+#define CAN_F7R1_FB22_Pos (22U)
+#define CAN_F7R1_FB22_Msk (0x1U << CAN_F7R1_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F7R1_FB22 CAN_F7R1_FB22_Msk /*!< Filter bit 22 */
+#define CAN_F7R1_FB23_Pos (23U)
+#define CAN_F7R1_FB23_Msk (0x1U << CAN_F7R1_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F7R1_FB23 CAN_F7R1_FB23_Msk /*!< Filter bit 23 */
+#define CAN_F7R1_FB24_Pos (24U)
+#define CAN_F7R1_FB24_Msk (0x1U << CAN_F7R1_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F7R1_FB24 CAN_F7R1_FB24_Msk /*!< Filter bit 24 */
+#define CAN_F7R1_FB25_Pos (25U)
+#define CAN_F7R1_FB25_Msk (0x1U << CAN_F7R1_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F7R1_FB25 CAN_F7R1_FB25_Msk /*!< Filter bit 25 */
+#define CAN_F7R1_FB26_Pos (26U)
+#define CAN_F7R1_FB26_Msk (0x1U << CAN_F7R1_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F7R1_FB26 CAN_F7R1_FB26_Msk /*!< Filter bit 26 */
+#define CAN_F7R1_FB27_Pos (27U)
+#define CAN_F7R1_FB27_Msk (0x1U << CAN_F7R1_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F7R1_FB27 CAN_F7R1_FB27_Msk /*!< Filter bit 27 */
+#define CAN_F7R1_FB28_Pos (28U)
+#define CAN_F7R1_FB28_Msk (0x1U << CAN_F7R1_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F7R1_FB28 CAN_F7R1_FB28_Msk /*!< Filter bit 28 */
+#define CAN_F7R1_FB29_Pos (29U)
+#define CAN_F7R1_FB29_Msk (0x1U << CAN_F7R1_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F7R1_FB29 CAN_F7R1_FB29_Msk /*!< Filter bit 29 */
+#define CAN_F7R1_FB30_Pos (30U)
+#define CAN_F7R1_FB30_Msk (0x1U << CAN_F7R1_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F7R1_FB30 CAN_F7R1_FB30_Msk /*!< Filter bit 30 */
+#define CAN_F7R1_FB31_Pos (31U)
+#define CAN_F7R1_FB31_Msk (0x1U << CAN_F7R1_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F7R1_FB31 CAN_F7R1_FB31_Msk /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F8R1 register *******************/
+#define CAN_F8R1_FB0_Pos (0U)
+#define CAN_F8R1_FB0_Msk (0x1U << CAN_F8R1_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F8R1_FB0 CAN_F8R1_FB0_Msk /*!< Filter bit 0 */
+#define CAN_F8R1_FB1_Pos (1U)
+#define CAN_F8R1_FB1_Msk (0x1U << CAN_F8R1_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F8R1_FB1 CAN_F8R1_FB1_Msk /*!< Filter bit 1 */
+#define CAN_F8R1_FB2_Pos (2U)
+#define CAN_F8R1_FB2_Msk (0x1U << CAN_F8R1_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F8R1_FB2 CAN_F8R1_FB2_Msk /*!< Filter bit 2 */
+#define CAN_F8R1_FB3_Pos (3U)
+#define CAN_F8R1_FB3_Msk (0x1U << CAN_F8R1_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F8R1_FB3 CAN_F8R1_FB3_Msk /*!< Filter bit 3 */
+#define CAN_F8R1_FB4_Pos (4U)
+#define CAN_F8R1_FB4_Msk (0x1U << CAN_F8R1_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F8R1_FB4 CAN_F8R1_FB4_Msk /*!< Filter bit 4 */
+#define CAN_F8R1_FB5_Pos (5U)
+#define CAN_F8R1_FB5_Msk (0x1U << CAN_F8R1_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F8R1_FB5 CAN_F8R1_FB5_Msk /*!< Filter bit 5 */
+#define CAN_F8R1_FB6_Pos (6U)
+#define CAN_F8R1_FB6_Msk (0x1U << CAN_F8R1_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F8R1_FB6 CAN_F8R1_FB6_Msk /*!< Filter bit 6 */
+#define CAN_F8R1_FB7_Pos (7U)
+#define CAN_F8R1_FB7_Msk (0x1U << CAN_F8R1_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F8R1_FB7 CAN_F8R1_FB7_Msk /*!< Filter bit 7 */
+#define CAN_F8R1_FB8_Pos (8U)
+#define CAN_F8R1_FB8_Msk (0x1U << CAN_F8R1_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F8R1_FB8 CAN_F8R1_FB8_Msk /*!< Filter bit 8 */
+#define CAN_F8R1_FB9_Pos (9U)
+#define CAN_F8R1_FB9_Msk (0x1U << CAN_F8R1_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F8R1_FB9 CAN_F8R1_FB9_Msk /*!< Filter bit 9 */
+#define CAN_F8R1_FB10_Pos (10U)
+#define CAN_F8R1_FB10_Msk (0x1U << CAN_F8R1_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F8R1_FB10 CAN_F8R1_FB10_Msk /*!< Filter bit 10 */
+#define CAN_F8R1_FB11_Pos (11U)
+#define CAN_F8R1_FB11_Msk (0x1U << CAN_F8R1_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F8R1_FB11 CAN_F8R1_FB11_Msk /*!< Filter bit 11 */
+#define CAN_F8R1_FB12_Pos (12U)
+#define CAN_F8R1_FB12_Msk (0x1U << CAN_F8R1_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F8R1_FB12 CAN_F8R1_FB12_Msk /*!< Filter bit 12 */
+#define CAN_F8R1_FB13_Pos (13U)
+#define CAN_F8R1_FB13_Msk (0x1U << CAN_F8R1_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F8R1_FB13 CAN_F8R1_FB13_Msk /*!< Filter bit 13 */
+#define CAN_F8R1_FB14_Pos (14U)
+#define CAN_F8R1_FB14_Msk (0x1U << CAN_F8R1_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F8R1_FB14 CAN_F8R1_FB14_Msk /*!< Filter bit 14 */
+#define CAN_F8R1_FB15_Pos (15U)
+#define CAN_F8R1_FB15_Msk (0x1U << CAN_F8R1_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F8R1_FB15 CAN_F8R1_FB15_Msk /*!< Filter bit 15 */
+#define CAN_F8R1_FB16_Pos (16U)
+#define CAN_F8R1_FB16_Msk (0x1U << CAN_F8R1_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F8R1_FB16 CAN_F8R1_FB16_Msk /*!< Filter bit 16 */
+#define CAN_F8R1_FB17_Pos (17U)
+#define CAN_F8R1_FB17_Msk (0x1U << CAN_F8R1_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F8R1_FB17 CAN_F8R1_FB17_Msk /*!< Filter bit 17 */
+#define CAN_F8R1_FB18_Pos (18U)
+#define CAN_F8R1_FB18_Msk (0x1U << CAN_F8R1_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F8R1_FB18 CAN_F8R1_FB18_Msk /*!< Filter bit 18 */
+#define CAN_F8R1_FB19_Pos (19U)
+#define CAN_F8R1_FB19_Msk (0x1U << CAN_F8R1_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F8R1_FB19 CAN_F8R1_FB19_Msk /*!< Filter bit 19 */
+#define CAN_F8R1_FB20_Pos (20U)
+#define CAN_F8R1_FB20_Msk (0x1U << CAN_F8R1_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F8R1_FB20 CAN_F8R1_FB20_Msk /*!< Filter bit 20 */
+#define CAN_F8R1_FB21_Pos (21U)
+#define CAN_F8R1_FB21_Msk (0x1U << CAN_F8R1_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F8R1_FB21 CAN_F8R1_FB21_Msk /*!< Filter bit 21 */
+#define CAN_F8R1_FB22_Pos (22U)
+#define CAN_F8R1_FB22_Msk (0x1U << CAN_F8R1_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F8R1_FB22 CAN_F8R1_FB22_Msk /*!< Filter bit 22 */
+#define CAN_F8R1_FB23_Pos (23U)
+#define CAN_F8R1_FB23_Msk (0x1U << CAN_F8R1_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F8R1_FB23 CAN_F8R1_FB23_Msk /*!< Filter bit 23 */
+#define CAN_F8R1_FB24_Pos (24U)
+#define CAN_F8R1_FB24_Msk (0x1U << CAN_F8R1_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F8R1_FB24 CAN_F8R1_FB24_Msk /*!< Filter bit 24 */
+#define CAN_F8R1_FB25_Pos (25U)
+#define CAN_F8R1_FB25_Msk (0x1U << CAN_F8R1_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F8R1_FB25 CAN_F8R1_FB25_Msk /*!< Filter bit 25 */
+#define CAN_F8R1_FB26_Pos (26U)
+#define CAN_F8R1_FB26_Msk (0x1U << CAN_F8R1_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F8R1_FB26 CAN_F8R1_FB26_Msk /*!< Filter bit 26 */
+#define CAN_F8R1_FB27_Pos (27U)
+#define CAN_F8R1_FB27_Msk (0x1U << CAN_F8R1_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F8R1_FB27 CAN_F8R1_FB27_Msk /*!< Filter bit 27 */
+#define CAN_F8R1_FB28_Pos (28U)
+#define CAN_F8R1_FB28_Msk (0x1U << CAN_F8R1_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F8R1_FB28 CAN_F8R1_FB28_Msk /*!< Filter bit 28 */
+#define CAN_F8R1_FB29_Pos (29U)
+#define CAN_F8R1_FB29_Msk (0x1U << CAN_F8R1_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F8R1_FB29 CAN_F8R1_FB29_Msk /*!< Filter bit 29 */
+#define CAN_F8R1_FB30_Pos (30U)
+#define CAN_F8R1_FB30_Msk (0x1U << CAN_F8R1_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F8R1_FB30 CAN_F8R1_FB30_Msk /*!< Filter bit 30 */
+#define CAN_F8R1_FB31_Pos (31U)
+#define CAN_F8R1_FB31_Msk (0x1U << CAN_F8R1_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F8R1_FB31 CAN_F8R1_FB31_Msk /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F9R1 register *******************/
+#define CAN_F9R1_FB0_Pos (0U)
+#define CAN_F9R1_FB0_Msk (0x1U << CAN_F9R1_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F9R1_FB0 CAN_F9R1_FB0_Msk /*!< Filter bit 0 */
+#define CAN_F9R1_FB1_Pos (1U)
+#define CAN_F9R1_FB1_Msk (0x1U << CAN_F9R1_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F9R1_FB1 CAN_F9R1_FB1_Msk /*!< Filter bit 1 */
+#define CAN_F9R1_FB2_Pos (2U)
+#define CAN_F9R1_FB2_Msk (0x1U << CAN_F9R1_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F9R1_FB2 CAN_F9R1_FB2_Msk /*!< Filter bit 2 */
+#define CAN_F9R1_FB3_Pos (3U)
+#define CAN_F9R1_FB3_Msk (0x1U << CAN_F9R1_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F9R1_FB3 CAN_F9R1_FB3_Msk /*!< Filter bit 3 */
+#define CAN_F9R1_FB4_Pos (4U)
+#define CAN_F9R1_FB4_Msk (0x1U << CAN_F9R1_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F9R1_FB4 CAN_F9R1_FB4_Msk /*!< Filter bit 4 */
+#define CAN_F9R1_FB5_Pos (5U)
+#define CAN_F9R1_FB5_Msk (0x1U << CAN_F9R1_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F9R1_FB5 CAN_F9R1_FB5_Msk /*!< Filter bit 5 */
+#define CAN_F9R1_FB6_Pos (6U)
+#define CAN_F9R1_FB6_Msk (0x1U << CAN_F9R1_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F9R1_FB6 CAN_F9R1_FB6_Msk /*!< Filter bit 6 */
+#define CAN_F9R1_FB7_Pos (7U)
+#define CAN_F9R1_FB7_Msk (0x1U << CAN_F9R1_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F9R1_FB7 CAN_F9R1_FB7_Msk /*!< Filter bit 7 */
+#define CAN_F9R1_FB8_Pos (8U)
+#define CAN_F9R1_FB8_Msk (0x1U << CAN_F9R1_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F9R1_FB8 CAN_F9R1_FB8_Msk /*!< Filter bit 8 */
+#define CAN_F9R1_FB9_Pos (9U)
+#define CAN_F9R1_FB9_Msk (0x1U << CAN_F9R1_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F9R1_FB9 CAN_F9R1_FB9_Msk /*!< Filter bit 9 */
+#define CAN_F9R1_FB10_Pos (10U)
+#define CAN_F9R1_FB10_Msk (0x1U << CAN_F9R1_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F9R1_FB10 CAN_F9R1_FB10_Msk /*!< Filter bit 10 */
+#define CAN_F9R1_FB11_Pos (11U)
+#define CAN_F9R1_FB11_Msk (0x1U << CAN_F9R1_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F9R1_FB11 CAN_F9R1_FB11_Msk /*!< Filter bit 11 */
+#define CAN_F9R1_FB12_Pos (12U)
+#define CAN_F9R1_FB12_Msk (0x1U << CAN_F9R1_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F9R1_FB12 CAN_F9R1_FB12_Msk /*!< Filter bit 12 */
+#define CAN_F9R1_FB13_Pos (13U)
+#define CAN_F9R1_FB13_Msk (0x1U << CAN_F9R1_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F9R1_FB13 CAN_F9R1_FB13_Msk /*!< Filter bit 13 */
+#define CAN_F9R1_FB14_Pos (14U)
+#define CAN_F9R1_FB14_Msk (0x1U << CAN_F9R1_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F9R1_FB14 CAN_F9R1_FB14_Msk /*!< Filter bit 14 */
+#define CAN_F9R1_FB15_Pos (15U)
+#define CAN_F9R1_FB15_Msk (0x1U << CAN_F9R1_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F9R1_FB15 CAN_F9R1_FB15_Msk /*!< Filter bit 15 */
+#define CAN_F9R1_FB16_Pos (16U)
+#define CAN_F9R1_FB16_Msk (0x1U << CAN_F9R1_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F9R1_FB16 CAN_F9R1_FB16_Msk /*!< Filter bit 16 */
+#define CAN_F9R1_FB17_Pos (17U)
+#define CAN_F9R1_FB17_Msk (0x1U << CAN_F9R1_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F9R1_FB17 CAN_F9R1_FB17_Msk /*!< Filter bit 17 */
+#define CAN_F9R1_FB18_Pos (18U)
+#define CAN_F9R1_FB18_Msk (0x1U << CAN_F9R1_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F9R1_FB18 CAN_F9R1_FB18_Msk /*!< Filter bit 18 */
+#define CAN_F9R1_FB19_Pos (19U)
+#define CAN_F9R1_FB19_Msk (0x1U << CAN_F9R1_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F9R1_FB19 CAN_F9R1_FB19_Msk /*!< Filter bit 19 */
+#define CAN_F9R1_FB20_Pos (20U)
+#define CAN_F9R1_FB20_Msk (0x1U << CAN_F9R1_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F9R1_FB20 CAN_F9R1_FB20_Msk /*!< Filter bit 20 */
+#define CAN_F9R1_FB21_Pos (21U)
+#define CAN_F9R1_FB21_Msk (0x1U << CAN_F9R1_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F9R1_FB21 CAN_F9R1_FB21_Msk /*!< Filter bit 21 */
+#define CAN_F9R1_FB22_Pos (22U)
+#define CAN_F9R1_FB22_Msk (0x1U << CAN_F9R1_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F9R1_FB22 CAN_F9R1_FB22_Msk /*!< Filter bit 22 */
+#define CAN_F9R1_FB23_Pos (23U)
+#define CAN_F9R1_FB23_Msk (0x1U << CAN_F9R1_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F9R1_FB23 CAN_F9R1_FB23_Msk /*!< Filter bit 23 */
+#define CAN_F9R1_FB24_Pos (24U)
+#define CAN_F9R1_FB24_Msk (0x1U << CAN_F9R1_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F9R1_FB24 CAN_F9R1_FB24_Msk /*!< Filter bit 24 */
+#define CAN_F9R1_FB25_Pos (25U)
+#define CAN_F9R1_FB25_Msk (0x1U << CAN_F9R1_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F9R1_FB25 CAN_F9R1_FB25_Msk /*!< Filter bit 25 */
+#define CAN_F9R1_FB26_Pos (26U)
+#define CAN_F9R1_FB26_Msk (0x1U << CAN_F9R1_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F9R1_FB26 CAN_F9R1_FB26_Msk /*!< Filter bit 26 */
+#define CAN_F9R1_FB27_Pos (27U)
+#define CAN_F9R1_FB27_Msk (0x1U << CAN_F9R1_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F9R1_FB27 CAN_F9R1_FB27_Msk /*!< Filter bit 27 */
+#define CAN_F9R1_FB28_Pos (28U)
+#define CAN_F9R1_FB28_Msk (0x1U << CAN_F9R1_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F9R1_FB28 CAN_F9R1_FB28_Msk /*!< Filter bit 28 */
+#define CAN_F9R1_FB29_Pos (29U)
+#define CAN_F9R1_FB29_Msk (0x1U << CAN_F9R1_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F9R1_FB29 CAN_F9R1_FB29_Msk /*!< Filter bit 29 */
+#define CAN_F9R1_FB30_Pos (30U)
+#define CAN_F9R1_FB30_Msk (0x1U << CAN_F9R1_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F9R1_FB30 CAN_F9R1_FB30_Msk /*!< Filter bit 30 */
+#define CAN_F9R1_FB31_Pos (31U)
+#define CAN_F9R1_FB31_Msk (0x1U << CAN_F9R1_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F9R1_FB31 CAN_F9R1_FB31_Msk /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F10R1 register ******************/
+#define CAN_F10R1_FB0_Pos (0U)
+#define CAN_F10R1_FB0_Msk (0x1U << CAN_F10R1_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F10R1_FB0 CAN_F10R1_FB0_Msk /*!< Filter bit 0 */
+#define CAN_F10R1_FB1_Pos (1U)
+#define CAN_F10R1_FB1_Msk (0x1U << CAN_F10R1_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F10R1_FB1 CAN_F10R1_FB1_Msk /*!< Filter bit 1 */
+#define CAN_F10R1_FB2_Pos (2U)
+#define CAN_F10R1_FB2_Msk (0x1U << CAN_F10R1_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F10R1_FB2 CAN_F10R1_FB2_Msk /*!< Filter bit 2 */
+#define CAN_F10R1_FB3_Pos (3U)
+#define CAN_F10R1_FB3_Msk (0x1U << CAN_F10R1_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F10R1_FB3 CAN_F10R1_FB3_Msk /*!< Filter bit 3 */
+#define CAN_F10R1_FB4_Pos (4U)
+#define CAN_F10R1_FB4_Msk (0x1U << CAN_F10R1_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F10R1_FB4 CAN_F10R1_FB4_Msk /*!< Filter bit 4 */
+#define CAN_F10R1_FB5_Pos (5U)
+#define CAN_F10R1_FB5_Msk (0x1U << CAN_F10R1_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F10R1_FB5 CAN_F10R1_FB5_Msk /*!< Filter bit 5 */
+#define CAN_F10R1_FB6_Pos (6U)
+#define CAN_F10R1_FB6_Msk (0x1U << CAN_F10R1_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F10R1_FB6 CAN_F10R1_FB6_Msk /*!< Filter bit 6 */
+#define CAN_F10R1_FB7_Pos (7U)
+#define CAN_F10R1_FB7_Msk (0x1U << CAN_F10R1_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F10R1_FB7 CAN_F10R1_FB7_Msk /*!< Filter bit 7 */
+#define CAN_F10R1_FB8_Pos (8U)
+#define CAN_F10R1_FB8_Msk (0x1U << CAN_F10R1_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F10R1_FB8 CAN_F10R1_FB8_Msk /*!< Filter bit 8 */
+#define CAN_F10R1_FB9_Pos (9U)
+#define CAN_F10R1_FB9_Msk (0x1U << CAN_F10R1_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F10R1_FB9 CAN_F10R1_FB9_Msk /*!< Filter bit 9 */
+#define CAN_F10R1_FB10_Pos (10U)
+#define CAN_F10R1_FB10_Msk (0x1U << CAN_F10R1_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F10R1_FB10 CAN_F10R1_FB10_Msk /*!< Filter bit 10 */
+#define CAN_F10R1_FB11_Pos (11U)
+#define CAN_F10R1_FB11_Msk (0x1U << CAN_F10R1_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F10R1_FB11 CAN_F10R1_FB11_Msk /*!< Filter bit 11 */
+#define CAN_F10R1_FB12_Pos (12U)
+#define CAN_F10R1_FB12_Msk (0x1U << CAN_F10R1_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F10R1_FB12 CAN_F10R1_FB12_Msk /*!< Filter bit 12 */
+#define CAN_F10R1_FB13_Pos (13U)
+#define CAN_F10R1_FB13_Msk (0x1U << CAN_F10R1_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F10R1_FB13 CAN_F10R1_FB13_Msk /*!< Filter bit 13 */
+#define CAN_F10R1_FB14_Pos (14U)
+#define CAN_F10R1_FB14_Msk (0x1U << CAN_F10R1_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F10R1_FB14 CAN_F10R1_FB14_Msk /*!< Filter bit 14 */
+#define CAN_F10R1_FB15_Pos (15U)
+#define CAN_F10R1_FB15_Msk (0x1U << CAN_F10R1_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F10R1_FB15 CAN_F10R1_FB15_Msk /*!< Filter bit 15 */
+#define CAN_F10R1_FB16_Pos (16U)
+#define CAN_F10R1_FB16_Msk (0x1U << CAN_F10R1_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F10R1_FB16 CAN_F10R1_FB16_Msk /*!< Filter bit 16 */
+#define CAN_F10R1_FB17_Pos (17U)
+#define CAN_F10R1_FB17_Msk (0x1U << CAN_F10R1_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F10R1_FB17 CAN_F10R1_FB17_Msk /*!< Filter bit 17 */
+#define CAN_F10R1_FB18_Pos (18U)
+#define CAN_F10R1_FB18_Msk (0x1U << CAN_F10R1_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F10R1_FB18 CAN_F10R1_FB18_Msk /*!< Filter bit 18 */
+#define CAN_F10R1_FB19_Pos (19U)
+#define CAN_F10R1_FB19_Msk (0x1U << CAN_F10R1_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F10R1_FB19 CAN_F10R1_FB19_Msk /*!< Filter bit 19 */
+#define CAN_F10R1_FB20_Pos (20U)
+#define CAN_F10R1_FB20_Msk (0x1U << CAN_F10R1_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F10R1_FB20 CAN_F10R1_FB20_Msk /*!< Filter bit 20 */
+#define CAN_F10R1_FB21_Pos (21U)
+#define CAN_F10R1_FB21_Msk (0x1U << CAN_F10R1_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F10R1_FB21 CAN_F10R1_FB21_Msk /*!< Filter bit 21 */
+#define CAN_F10R1_FB22_Pos (22U)
+#define CAN_F10R1_FB22_Msk (0x1U << CAN_F10R1_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F10R1_FB22 CAN_F10R1_FB22_Msk /*!< Filter bit 22 */
+#define CAN_F10R1_FB23_Pos (23U)
+#define CAN_F10R1_FB23_Msk (0x1U << CAN_F10R1_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F10R1_FB23 CAN_F10R1_FB23_Msk /*!< Filter bit 23 */
+#define CAN_F10R1_FB24_Pos (24U)
+#define CAN_F10R1_FB24_Msk (0x1U << CAN_F10R1_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F10R1_FB24 CAN_F10R1_FB24_Msk /*!< Filter bit 24 */
+#define CAN_F10R1_FB25_Pos (25U)
+#define CAN_F10R1_FB25_Msk (0x1U << CAN_F10R1_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F10R1_FB25 CAN_F10R1_FB25_Msk /*!< Filter bit 25 */
+#define CAN_F10R1_FB26_Pos (26U)
+#define CAN_F10R1_FB26_Msk (0x1U << CAN_F10R1_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F10R1_FB26 CAN_F10R1_FB26_Msk /*!< Filter bit 26 */
+#define CAN_F10R1_FB27_Pos (27U)
+#define CAN_F10R1_FB27_Msk (0x1U << CAN_F10R1_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F10R1_FB27 CAN_F10R1_FB27_Msk /*!< Filter bit 27 */
+#define CAN_F10R1_FB28_Pos (28U)
+#define CAN_F10R1_FB28_Msk (0x1U << CAN_F10R1_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F10R1_FB28 CAN_F10R1_FB28_Msk /*!< Filter bit 28 */
+#define CAN_F10R1_FB29_Pos (29U)
+#define CAN_F10R1_FB29_Msk (0x1U << CAN_F10R1_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F10R1_FB29 CAN_F10R1_FB29_Msk /*!< Filter bit 29 */
+#define CAN_F10R1_FB30_Pos (30U)
+#define CAN_F10R1_FB30_Msk (0x1U << CAN_F10R1_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F10R1_FB30 CAN_F10R1_FB30_Msk /*!< Filter bit 30 */
+#define CAN_F10R1_FB31_Pos (31U)
+#define CAN_F10R1_FB31_Msk (0x1U << CAN_F10R1_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F10R1_FB31 CAN_F10R1_FB31_Msk /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F11R1 register ******************/
+#define CAN_F11R1_FB0_Pos (0U)
+#define CAN_F11R1_FB0_Msk (0x1U << CAN_F11R1_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F11R1_FB0 CAN_F11R1_FB0_Msk /*!< Filter bit 0 */
+#define CAN_F11R1_FB1_Pos (1U)
+#define CAN_F11R1_FB1_Msk (0x1U << CAN_F11R1_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F11R1_FB1 CAN_F11R1_FB1_Msk /*!< Filter bit 1 */
+#define CAN_F11R1_FB2_Pos (2U)
+#define CAN_F11R1_FB2_Msk (0x1U << CAN_F11R1_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F11R1_FB2 CAN_F11R1_FB2_Msk /*!< Filter bit 2 */
+#define CAN_F11R1_FB3_Pos (3U)
+#define CAN_F11R1_FB3_Msk (0x1U << CAN_F11R1_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F11R1_FB3 CAN_F11R1_FB3_Msk /*!< Filter bit 3 */
+#define CAN_F11R1_FB4_Pos (4U)
+#define CAN_F11R1_FB4_Msk (0x1U << CAN_F11R1_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F11R1_FB4 CAN_F11R1_FB4_Msk /*!< Filter bit 4 */
+#define CAN_F11R1_FB5_Pos (5U)
+#define CAN_F11R1_FB5_Msk (0x1U << CAN_F11R1_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F11R1_FB5 CAN_F11R1_FB5_Msk /*!< Filter bit 5 */
+#define CAN_F11R1_FB6_Pos (6U)
+#define CAN_F11R1_FB6_Msk (0x1U << CAN_F11R1_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F11R1_FB6 CAN_F11R1_FB6_Msk /*!< Filter bit 6 */
+#define CAN_F11R1_FB7_Pos (7U)
+#define CAN_F11R1_FB7_Msk (0x1U << CAN_F11R1_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F11R1_FB7 CAN_F11R1_FB7_Msk /*!< Filter bit 7 */
+#define CAN_F11R1_FB8_Pos (8U)
+#define CAN_F11R1_FB8_Msk (0x1U << CAN_F11R1_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F11R1_FB8 CAN_F11R1_FB8_Msk /*!< Filter bit 8 */
+#define CAN_F11R1_FB9_Pos (9U)
+#define CAN_F11R1_FB9_Msk (0x1U << CAN_F11R1_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F11R1_FB9 CAN_F11R1_FB9_Msk /*!< Filter bit 9 */
+#define CAN_F11R1_FB10_Pos (10U)
+#define CAN_F11R1_FB10_Msk (0x1U << CAN_F11R1_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F11R1_FB10 CAN_F11R1_FB10_Msk /*!< Filter bit 10 */
+#define CAN_F11R1_FB11_Pos (11U)
+#define CAN_F11R1_FB11_Msk (0x1U << CAN_F11R1_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F11R1_FB11 CAN_F11R1_FB11_Msk /*!< Filter bit 11 */
+#define CAN_F11R1_FB12_Pos (12U)
+#define CAN_F11R1_FB12_Msk (0x1U << CAN_F11R1_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F11R1_FB12 CAN_F11R1_FB12_Msk /*!< Filter bit 12 */
+#define CAN_F11R1_FB13_Pos (13U)
+#define CAN_F11R1_FB13_Msk (0x1U << CAN_F11R1_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F11R1_FB13 CAN_F11R1_FB13_Msk /*!< Filter bit 13 */
+#define CAN_F11R1_FB14_Pos (14U)
+#define CAN_F11R1_FB14_Msk (0x1U << CAN_F11R1_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F11R1_FB14 CAN_F11R1_FB14_Msk /*!< Filter bit 14 */
+#define CAN_F11R1_FB15_Pos (15U)
+#define CAN_F11R1_FB15_Msk (0x1U << CAN_F11R1_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F11R1_FB15 CAN_F11R1_FB15_Msk /*!< Filter bit 15 */
+#define CAN_F11R1_FB16_Pos (16U)
+#define CAN_F11R1_FB16_Msk (0x1U << CAN_F11R1_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F11R1_FB16 CAN_F11R1_FB16_Msk /*!< Filter bit 16 */
+#define CAN_F11R1_FB17_Pos (17U)
+#define CAN_F11R1_FB17_Msk (0x1U << CAN_F11R1_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F11R1_FB17 CAN_F11R1_FB17_Msk /*!< Filter bit 17 */
+#define CAN_F11R1_FB18_Pos (18U)
+#define CAN_F11R1_FB18_Msk (0x1U << CAN_F11R1_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F11R1_FB18 CAN_F11R1_FB18_Msk /*!< Filter bit 18 */
+#define CAN_F11R1_FB19_Pos (19U)
+#define CAN_F11R1_FB19_Msk (0x1U << CAN_F11R1_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F11R1_FB19 CAN_F11R1_FB19_Msk /*!< Filter bit 19 */
+#define CAN_F11R1_FB20_Pos (20U)
+#define CAN_F11R1_FB20_Msk (0x1U << CAN_F11R1_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F11R1_FB20 CAN_F11R1_FB20_Msk /*!< Filter bit 20 */
+#define CAN_F11R1_FB21_Pos (21U)
+#define CAN_F11R1_FB21_Msk (0x1U << CAN_F11R1_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F11R1_FB21 CAN_F11R1_FB21_Msk /*!< Filter bit 21 */
+#define CAN_F11R1_FB22_Pos (22U)
+#define CAN_F11R1_FB22_Msk (0x1U << CAN_F11R1_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F11R1_FB22 CAN_F11R1_FB22_Msk /*!< Filter bit 22 */
+#define CAN_F11R1_FB23_Pos (23U)
+#define CAN_F11R1_FB23_Msk (0x1U << CAN_F11R1_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F11R1_FB23 CAN_F11R1_FB23_Msk /*!< Filter bit 23 */
+#define CAN_F11R1_FB24_Pos (24U)
+#define CAN_F11R1_FB24_Msk (0x1U << CAN_F11R1_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F11R1_FB24 CAN_F11R1_FB24_Msk /*!< Filter bit 24 */
+#define CAN_F11R1_FB25_Pos (25U)
+#define CAN_F11R1_FB25_Msk (0x1U << CAN_F11R1_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F11R1_FB25 CAN_F11R1_FB25_Msk /*!< Filter bit 25 */
+#define CAN_F11R1_FB26_Pos (26U)
+#define CAN_F11R1_FB26_Msk (0x1U << CAN_F11R1_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F11R1_FB26 CAN_F11R1_FB26_Msk /*!< Filter bit 26 */
+#define CAN_F11R1_FB27_Pos (27U)
+#define CAN_F11R1_FB27_Msk (0x1U << CAN_F11R1_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F11R1_FB27 CAN_F11R1_FB27_Msk /*!< Filter bit 27 */
+#define CAN_F11R1_FB28_Pos (28U)
+#define CAN_F11R1_FB28_Msk (0x1U << CAN_F11R1_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F11R1_FB28 CAN_F11R1_FB28_Msk /*!< Filter bit 28 */
+#define CAN_F11R1_FB29_Pos (29U)
+#define CAN_F11R1_FB29_Msk (0x1U << CAN_F11R1_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F11R1_FB29 CAN_F11R1_FB29_Msk /*!< Filter bit 29 */
+#define CAN_F11R1_FB30_Pos (30U)
+#define CAN_F11R1_FB30_Msk (0x1U << CAN_F11R1_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F11R1_FB30 CAN_F11R1_FB30_Msk /*!< Filter bit 30 */
+#define CAN_F11R1_FB31_Pos (31U)
+#define CAN_F11R1_FB31_Msk (0x1U << CAN_F11R1_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F11R1_FB31 CAN_F11R1_FB31_Msk /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F12R1 register ******************/
+#define CAN_F12R1_FB0_Pos (0U)
+#define CAN_F12R1_FB0_Msk (0x1U << CAN_F12R1_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F12R1_FB0 CAN_F12R1_FB0_Msk /*!< Filter bit 0 */
+#define CAN_F12R1_FB1_Pos (1U)
+#define CAN_F12R1_FB1_Msk (0x1U << CAN_F12R1_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F12R1_FB1 CAN_F12R1_FB1_Msk /*!< Filter bit 1 */
+#define CAN_F12R1_FB2_Pos (2U)
+#define CAN_F12R1_FB2_Msk (0x1U << CAN_F12R1_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F12R1_FB2 CAN_F12R1_FB2_Msk /*!< Filter bit 2 */
+#define CAN_F12R1_FB3_Pos (3U)
+#define CAN_F12R1_FB3_Msk (0x1U << CAN_F12R1_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F12R1_FB3 CAN_F12R1_FB3_Msk /*!< Filter bit 3 */
+#define CAN_F12R1_FB4_Pos (4U)
+#define CAN_F12R1_FB4_Msk (0x1U << CAN_F12R1_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F12R1_FB4 CAN_F12R1_FB4_Msk /*!< Filter bit 4 */
+#define CAN_F12R1_FB5_Pos (5U)
+#define CAN_F12R1_FB5_Msk (0x1U << CAN_F12R1_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F12R1_FB5 CAN_F12R1_FB5_Msk /*!< Filter bit 5 */
+#define CAN_F12R1_FB6_Pos (6U)
+#define CAN_F12R1_FB6_Msk (0x1U << CAN_F12R1_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F12R1_FB6 CAN_F12R1_FB6_Msk /*!< Filter bit 6 */
+#define CAN_F12R1_FB7_Pos (7U)
+#define CAN_F12R1_FB7_Msk (0x1U << CAN_F12R1_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F12R1_FB7 CAN_F12R1_FB7_Msk /*!< Filter bit 7 */
+#define CAN_F12R1_FB8_Pos (8U)
+#define CAN_F12R1_FB8_Msk (0x1U << CAN_F12R1_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F12R1_FB8 CAN_F12R1_FB8_Msk /*!< Filter bit 8 */
+#define CAN_F12R1_FB9_Pos (9U)
+#define CAN_F12R1_FB9_Msk (0x1U << CAN_F12R1_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F12R1_FB9 CAN_F12R1_FB9_Msk /*!< Filter bit 9 */
+#define CAN_F12R1_FB10_Pos (10U)
+#define CAN_F12R1_FB10_Msk (0x1U << CAN_F12R1_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F12R1_FB10 CAN_F12R1_FB10_Msk /*!< Filter bit 10 */
+#define CAN_F12R1_FB11_Pos (11U)
+#define CAN_F12R1_FB11_Msk (0x1U << CAN_F12R1_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F12R1_FB11 CAN_F12R1_FB11_Msk /*!< Filter bit 11 */
+#define CAN_F12R1_FB12_Pos (12U)
+#define CAN_F12R1_FB12_Msk (0x1U << CAN_F12R1_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F12R1_FB12 CAN_F12R1_FB12_Msk /*!< Filter bit 12 */
+#define CAN_F12R1_FB13_Pos (13U)
+#define CAN_F12R1_FB13_Msk (0x1U << CAN_F12R1_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F12R1_FB13 CAN_F12R1_FB13_Msk /*!< Filter bit 13 */
+#define CAN_F12R1_FB14_Pos (14U)
+#define CAN_F12R1_FB14_Msk (0x1U << CAN_F12R1_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F12R1_FB14 CAN_F12R1_FB14_Msk /*!< Filter bit 14 */
+#define CAN_F12R1_FB15_Pos (15U)
+#define CAN_F12R1_FB15_Msk (0x1U << CAN_F12R1_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F12R1_FB15 CAN_F12R1_FB15_Msk /*!< Filter bit 15 */
+#define CAN_F12R1_FB16_Pos (16U)
+#define CAN_F12R1_FB16_Msk (0x1U << CAN_F12R1_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F12R1_FB16 CAN_F12R1_FB16_Msk /*!< Filter bit 16 */
+#define CAN_F12R1_FB17_Pos (17U)
+#define CAN_F12R1_FB17_Msk (0x1U << CAN_F12R1_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F12R1_FB17 CAN_F12R1_FB17_Msk /*!< Filter bit 17 */
+#define CAN_F12R1_FB18_Pos (18U)
+#define CAN_F12R1_FB18_Msk (0x1U << CAN_F12R1_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F12R1_FB18 CAN_F12R1_FB18_Msk /*!< Filter bit 18 */
+#define CAN_F12R1_FB19_Pos (19U)
+#define CAN_F12R1_FB19_Msk (0x1U << CAN_F12R1_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F12R1_FB19 CAN_F12R1_FB19_Msk /*!< Filter bit 19 */
+#define CAN_F12R1_FB20_Pos (20U)
+#define CAN_F12R1_FB20_Msk (0x1U << CAN_F12R1_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F12R1_FB20 CAN_F12R1_FB20_Msk /*!< Filter bit 20 */
+#define CAN_F12R1_FB21_Pos (21U)
+#define CAN_F12R1_FB21_Msk (0x1U << CAN_F12R1_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F12R1_FB21 CAN_F12R1_FB21_Msk /*!< Filter bit 21 */
+#define CAN_F12R1_FB22_Pos (22U)
+#define CAN_F12R1_FB22_Msk (0x1U << CAN_F12R1_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F12R1_FB22 CAN_F12R1_FB22_Msk /*!< Filter bit 22 */
+#define CAN_F12R1_FB23_Pos (23U)
+#define CAN_F12R1_FB23_Msk (0x1U << CAN_F12R1_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F12R1_FB23 CAN_F12R1_FB23_Msk /*!< Filter bit 23 */
+#define CAN_F12R1_FB24_Pos (24U)
+#define CAN_F12R1_FB24_Msk (0x1U << CAN_F12R1_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F12R1_FB24 CAN_F12R1_FB24_Msk /*!< Filter bit 24 */
+#define CAN_F12R1_FB25_Pos (25U)
+#define CAN_F12R1_FB25_Msk (0x1U << CAN_F12R1_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F12R1_FB25 CAN_F12R1_FB25_Msk /*!< Filter bit 25 */
+#define CAN_F12R1_FB26_Pos (26U)
+#define CAN_F12R1_FB26_Msk (0x1U << CAN_F12R1_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F12R1_FB26 CAN_F12R1_FB26_Msk /*!< Filter bit 26 */
+#define CAN_F12R1_FB27_Pos (27U)
+#define CAN_F12R1_FB27_Msk (0x1U << CAN_F12R1_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F12R1_FB27 CAN_F12R1_FB27_Msk /*!< Filter bit 27 */
+#define CAN_F12R1_FB28_Pos (28U)
+#define CAN_F12R1_FB28_Msk (0x1U << CAN_F12R1_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F12R1_FB28 CAN_F12R1_FB28_Msk /*!< Filter bit 28 */
+#define CAN_F12R1_FB29_Pos (29U)
+#define CAN_F12R1_FB29_Msk (0x1U << CAN_F12R1_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F12R1_FB29 CAN_F12R1_FB29_Msk /*!< Filter bit 29 */
+#define CAN_F12R1_FB30_Pos (30U)
+#define CAN_F12R1_FB30_Msk (0x1U << CAN_F12R1_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F12R1_FB30 CAN_F12R1_FB30_Msk /*!< Filter bit 30 */
+#define CAN_F12R1_FB31_Pos (31U)
+#define CAN_F12R1_FB31_Msk (0x1U << CAN_F12R1_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F12R1_FB31 CAN_F12R1_FB31_Msk /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F13R1 register ******************/
+#define CAN_F13R1_FB0_Pos (0U)
+#define CAN_F13R1_FB0_Msk (0x1U << CAN_F13R1_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F13R1_FB0 CAN_F13R1_FB0_Msk /*!< Filter bit 0 */
+#define CAN_F13R1_FB1_Pos (1U)
+#define CAN_F13R1_FB1_Msk (0x1U << CAN_F13R1_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F13R1_FB1 CAN_F13R1_FB1_Msk /*!< Filter bit 1 */
+#define CAN_F13R1_FB2_Pos (2U)
+#define CAN_F13R1_FB2_Msk (0x1U << CAN_F13R1_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F13R1_FB2 CAN_F13R1_FB2_Msk /*!< Filter bit 2 */
+#define CAN_F13R1_FB3_Pos (3U)
+#define CAN_F13R1_FB3_Msk (0x1U << CAN_F13R1_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F13R1_FB3 CAN_F13R1_FB3_Msk /*!< Filter bit 3 */
+#define CAN_F13R1_FB4_Pos (4U)
+#define CAN_F13R1_FB4_Msk (0x1U << CAN_F13R1_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F13R1_FB4 CAN_F13R1_FB4_Msk /*!< Filter bit 4 */
+#define CAN_F13R1_FB5_Pos (5U)
+#define CAN_F13R1_FB5_Msk (0x1U << CAN_F13R1_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F13R1_FB5 CAN_F13R1_FB5_Msk /*!< Filter bit 5 */
+#define CAN_F13R1_FB6_Pos (6U)
+#define CAN_F13R1_FB6_Msk (0x1U << CAN_F13R1_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F13R1_FB6 CAN_F13R1_FB6_Msk /*!< Filter bit 6 */
+#define CAN_F13R1_FB7_Pos (7U)
+#define CAN_F13R1_FB7_Msk (0x1U << CAN_F13R1_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F13R1_FB7 CAN_F13R1_FB7_Msk /*!< Filter bit 7 */
+#define CAN_F13R1_FB8_Pos (8U)
+#define CAN_F13R1_FB8_Msk (0x1U << CAN_F13R1_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F13R1_FB8 CAN_F13R1_FB8_Msk /*!< Filter bit 8 */
+#define CAN_F13R1_FB9_Pos (9U)
+#define CAN_F13R1_FB9_Msk (0x1U << CAN_F13R1_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F13R1_FB9 CAN_F13R1_FB9_Msk /*!< Filter bit 9 */
+#define CAN_F13R1_FB10_Pos (10U)
+#define CAN_F13R1_FB10_Msk (0x1U << CAN_F13R1_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F13R1_FB10 CAN_F13R1_FB10_Msk /*!< Filter bit 10 */
+#define CAN_F13R1_FB11_Pos (11U)
+#define CAN_F13R1_FB11_Msk (0x1U << CAN_F13R1_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F13R1_FB11 CAN_F13R1_FB11_Msk /*!< Filter bit 11 */
+#define CAN_F13R1_FB12_Pos (12U)
+#define CAN_F13R1_FB12_Msk (0x1U << CAN_F13R1_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F13R1_FB12 CAN_F13R1_FB12_Msk /*!< Filter bit 12 */
+#define CAN_F13R1_FB13_Pos (13U)
+#define CAN_F13R1_FB13_Msk (0x1U << CAN_F13R1_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F13R1_FB13 CAN_F13R1_FB13_Msk /*!< Filter bit 13 */
+#define CAN_F13R1_FB14_Pos (14U)
+#define CAN_F13R1_FB14_Msk (0x1U << CAN_F13R1_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F13R1_FB14 CAN_F13R1_FB14_Msk /*!< Filter bit 14 */
+#define CAN_F13R1_FB15_Pos (15U)
+#define CAN_F13R1_FB15_Msk (0x1U << CAN_F13R1_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F13R1_FB15 CAN_F13R1_FB15_Msk /*!< Filter bit 15 */
+#define CAN_F13R1_FB16_Pos (16U)
+#define CAN_F13R1_FB16_Msk (0x1U << CAN_F13R1_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F13R1_FB16 CAN_F13R1_FB16_Msk /*!< Filter bit 16 */
+#define CAN_F13R1_FB17_Pos (17U)
+#define CAN_F13R1_FB17_Msk (0x1U << CAN_F13R1_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F13R1_FB17 CAN_F13R1_FB17_Msk /*!< Filter bit 17 */
+#define CAN_F13R1_FB18_Pos (18U)
+#define CAN_F13R1_FB18_Msk (0x1U << CAN_F13R1_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F13R1_FB18 CAN_F13R1_FB18_Msk /*!< Filter bit 18 */
+#define CAN_F13R1_FB19_Pos (19U)
+#define CAN_F13R1_FB19_Msk (0x1U << CAN_F13R1_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F13R1_FB19 CAN_F13R1_FB19_Msk /*!< Filter bit 19 */
+#define CAN_F13R1_FB20_Pos (20U)
+#define CAN_F13R1_FB20_Msk (0x1U << CAN_F13R1_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F13R1_FB20 CAN_F13R1_FB20_Msk /*!< Filter bit 20 */
+#define CAN_F13R1_FB21_Pos (21U)
+#define CAN_F13R1_FB21_Msk (0x1U << CAN_F13R1_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F13R1_FB21 CAN_F13R1_FB21_Msk /*!< Filter bit 21 */
+#define CAN_F13R1_FB22_Pos (22U)
+#define CAN_F13R1_FB22_Msk (0x1U << CAN_F13R1_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F13R1_FB22 CAN_F13R1_FB22_Msk /*!< Filter bit 22 */
+#define CAN_F13R1_FB23_Pos (23U)
+#define CAN_F13R1_FB23_Msk (0x1U << CAN_F13R1_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F13R1_FB23 CAN_F13R1_FB23_Msk /*!< Filter bit 23 */
+#define CAN_F13R1_FB24_Pos (24U)
+#define CAN_F13R1_FB24_Msk (0x1U << CAN_F13R1_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F13R1_FB24 CAN_F13R1_FB24_Msk /*!< Filter bit 24 */
+#define CAN_F13R1_FB25_Pos (25U)
+#define CAN_F13R1_FB25_Msk (0x1U << CAN_F13R1_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F13R1_FB25 CAN_F13R1_FB25_Msk /*!< Filter bit 25 */
+#define CAN_F13R1_FB26_Pos (26U)
+#define CAN_F13R1_FB26_Msk (0x1U << CAN_F13R1_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F13R1_FB26 CAN_F13R1_FB26_Msk /*!< Filter bit 26 */
+#define CAN_F13R1_FB27_Pos (27U)
+#define CAN_F13R1_FB27_Msk (0x1U << CAN_F13R1_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F13R1_FB27 CAN_F13R1_FB27_Msk /*!< Filter bit 27 */
+#define CAN_F13R1_FB28_Pos (28U)
+#define CAN_F13R1_FB28_Msk (0x1U << CAN_F13R1_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F13R1_FB28 CAN_F13R1_FB28_Msk /*!< Filter bit 28 */
+#define CAN_F13R1_FB29_Pos (29U)
+#define CAN_F13R1_FB29_Msk (0x1U << CAN_F13R1_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F13R1_FB29 CAN_F13R1_FB29_Msk /*!< Filter bit 29 */
+#define CAN_F13R1_FB30_Pos (30U)
+#define CAN_F13R1_FB30_Msk (0x1U << CAN_F13R1_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F13R1_FB30 CAN_F13R1_FB30_Msk /*!< Filter bit 30 */
+#define CAN_F13R1_FB31_Pos (31U)
+#define CAN_F13R1_FB31_Msk (0x1U << CAN_F13R1_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F13R1_FB31 CAN_F13R1_FB31_Msk /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F14R1 register ******************/
+#define CAN_F14R1_FB0_Pos (0U)
+#define CAN_F14R1_FB0_Msk (0x1U << CAN_F14R1_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F14R1_FB0 CAN_F14R1_FB0_Msk /*!< Filter bit 0 */
+#define CAN_F14R1_FB1_Pos (1U)
+#define CAN_F14R1_FB1_Msk (0x1U << CAN_F14R1_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F14R1_FB1 CAN_F14R1_FB1_Msk /*!< Filter bit 1 */
+#define CAN_F14R1_FB2_Pos (2U)
+#define CAN_F14R1_FB2_Msk (0x1U << CAN_F14R1_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F14R1_FB2 CAN_F14R1_FB2_Msk /*!< Filter bit 2 */
+#define CAN_F14R1_FB3_Pos (3U)
+#define CAN_F14R1_FB3_Msk (0x1U << CAN_F14R1_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F14R1_FB3 CAN_F14R1_FB3_Msk /*!< Filter bit 3 */
+#define CAN_F14R1_FB4_Pos (4U)
+#define CAN_F14R1_FB4_Msk (0x1U << CAN_F14R1_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F14R1_FB4 CAN_F14R1_FB4_Msk /*!< Filter bit 4 */
+#define CAN_F14R1_FB5_Pos (5U)
+#define CAN_F14R1_FB5_Msk (0x1U << CAN_F14R1_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F14R1_FB5 CAN_F14R1_FB5_Msk /*!< Filter bit 5 */
+#define CAN_F14R1_FB6_Pos (6U)
+#define CAN_F14R1_FB6_Msk (0x1U << CAN_F14R1_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F14R1_FB6 CAN_F14R1_FB6_Msk /*!< Filter bit 6 */
+#define CAN_F14R1_FB7_Pos (7U)
+#define CAN_F14R1_FB7_Msk (0x1U << CAN_F14R1_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F14R1_FB7 CAN_F14R1_FB7_Msk /*!< Filter bit 7 */
+#define CAN_F14R1_FB8_Pos (8U)
+#define CAN_F14R1_FB8_Msk (0x1U << CAN_F14R1_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F14R1_FB8 CAN_F14R1_FB8_Msk /*!< Filter bit 8 */
+#define CAN_F14R1_FB9_Pos (9U)
+#define CAN_F14R1_FB9_Msk (0x1U << CAN_F14R1_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F14R1_FB9 CAN_F14R1_FB9_Msk /*!< Filter bit 9 */
+#define CAN_F14R1_FB10_Pos (10U)
+#define CAN_F14R1_FB10_Msk (0x1U << CAN_F14R1_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F14R1_FB10 CAN_F14R1_FB10_Msk /*!< Filter bit 10 */
+#define CAN_F14R1_FB11_Pos (11U)
+#define CAN_F14R1_FB11_Msk (0x1U << CAN_F14R1_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F14R1_FB11 CAN_F14R1_FB11_Msk /*!< Filter bit 11 */
+#define CAN_F14R1_FB12_Pos (12U)
+#define CAN_F14R1_FB12_Msk (0x1U << CAN_F14R1_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F14R1_FB12 CAN_F14R1_FB12_Msk /*!< Filter bit 12 */
+#define CAN_F14R1_FB13_Pos (13U)
+#define CAN_F14R1_FB13_Msk (0x1U << CAN_F14R1_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F14R1_FB13 CAN_F14R1_FB13_Msk /*!< Filter bit 13 */
+#define CAN_F14R1_FB14_Pos (14U)
+#define CAN_F14R1_FB14_Msk (0x1U << CAN_F14R1_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F14R1_FB14 CAN_F14R1_FB14_Msk /*!< Filter bit 14 */
+#define CAN_F14R1_FB15_Pos (15U)
+#define CAN_F14R1_FB15_Msk (0x1U << CAN_F14R1_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F14R1_FB15 CAN_F14R1_FB15_Msk /*!< Filter bit 15 */
+#define CAN_F14R1_FB16_Pos (16U)
+#define CAN_F14R1_FB16_Msk (0x1U << CAN_F14R1_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F14R1_FB16 CAN_F14R1_FB16_Msk /*!< Filter bit 16 */
+#define CAN_F14R1_FB17_Pos (17U)
+#define CAN_F14R1_FB17_Msk (0x1U << CAN_F14R1_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F14R1_FB17 CAN_F14R1_FB17_Msk /*!< Filter bit 17 */
+#define CAN_F14R1_FB18_Pos (18U)
+#define CAN_F14R1_FB18_Msk (0x1U << CAN_F14R1_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F14R1_FB18 CAN_F14R1_FB18_Msk /*!< Filter bit 18 */
+#define CAN_F14R1_FB19_Pos (19U)
+#define CAN_F14R1_FB19_Msk (0x1U << CAN_F14R1_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F14R1_FB19 CAN_F14R1_FB19_Msk /*!< Filter bit 19 */
+#define CAN_F14R1_FB20_Pos (20U)
+#define CAN_F14R1_FB20_Msk (0x1U << CAN_F14R1_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F14R1_FB20 CAN_F14R1_FB20_Msk /*!< Filter bit 20 */
+#define CAN_F14R1_FB21_Pos (21U)
+#define CAN_F14R1_FB21_Msk (0x1U << CAN_F14R1_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F14R1_FB21 CAN_F14R1_FB21_Msk /*!< Filter bit 21 */
+#define CAN_F14R1_FB22_Pos (22U)
+#define CAN_F14R1_FB22_Msk (0x1U << CAN_F14R1_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F14R1_FB22 CAN_F14R1_FB22_Msk /*!< Filter bit 22 */
+#define CAN_F14R1_FB23_Pos (23U)
+#define CAN_F14R1_FB23_Msk (0x1U << CAN_F14R1_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F14R1_FB23 CAN_F14R1_FB23_Msk /*!< Filter bit 23 */
+#define CAN_F14R1_FB24_Pos (24U)
+#define CAN_F14R1_FB24_Msk (0x1U << CAN_F14R1_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F14R1_FB24 CAN_F14R1_FB24_Msk /*!< Filter bit 24 */
+#define CAN_F14R1_FB25_Pos (25U)
+#define CAN_F14R1_FB25_Msk (0x1U << CAN_F14R1_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F14R1_FB25 CAN_F14R1_FB25_Msk /*!< Filter bit 25 */
+#define CAN_F14R1_FB26_Pos (26U)
+#define CAN_F14R1_FB26_Msk (0x1U << CAN_F14R1_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F14R1_FB26 CAN_F14R1_FB26_Msk /*!< Filter bit 26 */
+#define CAN_F14R1_FB27_Pos (27U)
+#define CAN_F14R1_FB27_Msk (0x1U << CAN_F14R1_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F14R1_FB27 CAN_F14R1_FB27_Msk /*!< Filter bit 27 */
+#define CAN_F14R1_FB28_Pos (28U)
+#define CAN_F14R1_FB28_Msk (0x1U << CAN_F14R1_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F14R1_FB28 CAN_F14R1_FB28_Msk /*!< Filter bit 28 */
+#define CAN_F14R1_FB29_Pos (29U)
+#define CAN_F14R1_FB29_Msk (0x1U << CAN_F14R1_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F14R1_FB29 CAN_F14R1_FB29_Msk /*!< Filter bit 29 */
+#define CAN_F14R1_FB30_Pos (30U)
+#define CAN_F14R1_FB30_Msk (0x1U << CAN_F14R1_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F14R1_FB30 CAN_F14R1_FB30_Msk /*!< Filter bit 30 */
+#define CAN_F14R1_FB31_Pos (31U)
+#define CAN_F14R1_FB31_Msk (0x1U << CAN_F14R1_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F14R1_FB31 CAN_F14R1_FB31_Msk /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F15R1 register ******************/
+#define CAN_F15R1_FB0_Pos (0U)
+#define CAN_F15R1_FB0_Msk (0x1U << CAN_F15R1_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F15R1_FB0 CAN_F15R1_FB0_Msk /*!< Filter bit 0 */
+#define CAN_F15R1_FB1_Pos (1U)
+#define CAN_F15R1_FB1_Msk (0x1U << CAN_F15R1_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F15R1_FB1 CAN_F15R1_FB1_Msk /*!< Filter bit 1 */
+#define CAN_F15R1_FB2_Pos (2U)
+#define CAN_F15R1_FB2_Msk (0x1U << CAN_F15R1_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F15R1_FB2 CAN_F15R1_FB2_Msk /*!< Filter bit 2 */
+#define CAN_F15R1_FB3_Pos (3U)
+#define CAN_F15R1_FB3_Msk (0x1U << CAN_F15R1_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F15R1_FB3 CAN_F15R1_FB3_Msk /*!< Filter bit 3 */
+#define CAN_F15R1_FB4_Pos (4U)
+#define CAN_F15R1_FB4_Msk (0x1U << CAN_F15R1_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F15R1_FB4 CAN_F15R1_FB4_Msk /*!< Filter bit 4 */
+#define CAN_F15R1_FB5_Pos (5U)
+#define CAN_F15R1_FB5_Msk (0x1U << CAN_F15R1_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F15R1_FB5 CAN_F15R1_FB5_Msk /*!< Filter bit 5 */
+#define CAN_F15R1_FB6_Pos (6U)
+#define CAN_F15R1_FB6_Msk (0x1U << CAN_F15R1_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F15R1_FB6 CAN_F15R1_FB6_Msk /*!< Filter bit 6 */
+#define CAN_F15R1_FB7_Pos (7U)
+#define CAN_F15R1_FB7_Msk (0x1U << CAN_F15R1_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F15R1_FB7 CAN_F15R1_FB7_Msk /*!< Filter bit 7 */
+#define CAN_F15R1_FB8_Pos (8U)
+#define CAN_F15R1_FB8_Msk (0x1U << CAN_F15R1_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F15R1_FB8 CAN_F15R1_FB8_Msk /*!< Filter bit 8 */
+#define CAN_F15R1_FB9_Pos (9U)
+#define CAN_F15R1_FB9_Msk (0x1U << CAN_F15R1_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F15R1_FB9 CAN_F15R1_FB9_Msk /*!< Filter bit 9 */
+#define CAN_F15R1_FB10_Pos (10U)
+#define CAN_F15R1_FB10_Msk (0x1U << CAN_F15R1_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F15R1_FB10 CAN_F15R1_FB10_Msk /*!< Filter bit 10 */
+#define CAN_F15R1_FB11_Pos (11U)
+#define CAN_F15R1_FB11_Msk (0x1U << CAN_F15R1_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F15R1_FB11 CAN_F15R1_FB11_Msk /*!< Filter bit 11 */
+#define CAN_F15R1_FB12_Pos (12U)
+#define CAN_F15R1_FB12_Msk (0x1U << CAN_F15R1_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F15R1_FB12 CAN_F15R1_FB12_Msk /*!< Filter bit 12 */
+#define CAN_F15R1_FB13_Pos (13U)
+#define CAN_F15R1_FB13_Msk (0x1U << CAN_F15R1_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F15R1_FB13 CAN_F15R1_FB13_Msk /*!< Filter bit 13 */
+#define CAN_F15R1_FB14_Pos (14U)
+#define CAN_F15R1_FB14_Msk (0x1U << CAN_F15R1_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F15R1_FB14 CAN_F15R1_FB14_Msk /*!< Filter bit 14 */
+#define CAN_F15R1_FB15_Pos (15U)
+#define CAN_F15R1_FB15_Msk (0x1U << CAN_F15R1_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F15R1_FB15 CAN_F15R1_FB15_Msk /*!< Filter bit 15 */
+#define CAN_F15R1_FB16_Pos (16U)
+#define CAN_F15R1_FB16_Msk (0x1U << CAN_F15R1_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F15R1_FB16 CAN_F15R1_FB16_Msk /*!< Filter bit 16 */
+#define CAN_F15R1_FB17_Pos (17U)
+#define CAN_F15R1_FB17_Msk (0x1U << CAN_F15R1_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F15R1_FB17 CAN_F15R1_FB17_Msk /*!< Filter bit 17 */
+#define CAN_F15R1_FB18_Pos (18U)
+#define CAN_F15R1_FB18_Msk (0x1U << CAN_F15R1_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F15R1_FB18 CAN_F15R1_FB18_Msk /*!< Filter bit 18 */
+#define CAN_F15R1_FB19_Pos (19U)
+#define CAN_F15R1_FB19_Msk (0x1U << CAN_F15R1_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F15R1_FB19 CAN_F15R1_FB19_Msk /*!< Filter bit 19 */
+#define CAN_F15R1_FB20_Pos (20U)
+#define CAN_F15R1_FB20_Msk (0x1U << CAN_F15R1_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F15R1_FB20 CAN_F15R1_FB20_Msk /*!< Filter bit 20 */
+#define CAN_F15R1_FB21_Pos (21U)
+#define CAN_F15R1_FB21_Msk (0x1U << CAN_F15R1_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F15R1_FB21 CAN_F15R1_FB21_Msk /*!< Filter bit 21 */
+#define CAN_F15R1_FB22_Pos (22U)
+#define CAN_F15R1_FB22_Msk (0x1U << CAN_F15R1_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F15R1_FB22 CAN_F15R1_FB22_Msk /*!< Filter bit 22 */
+#define CAN_F15R1_FB23_Pos (23U)
+#define CAN_F15R1_FB23_Msk (0x1U << CAN_F15R1_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F15R1_FB23 CAN_F15R1_FB23_Msk /*!< Filter bit 23 */
+#define CAN_F15R1_FB24_Pos (24U)
+#define CAN_F15R1_FB24_Msk (0x1U << CAN_F15R1_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F15R1_FB24 CAN_F15R1_FB24_Msk /*!< Filter bit 24 */
+#define CAN_F15R1_FB25_Pos (25U)
+#define CAN_F15R1_FB25_Msk (0x1U << CAN_F15R1_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F15R1_FB25 CAN_F15R1_FB25_Msk /*!< Filter bit 25 */
+#define CAN_F15R1_FB26_Pos (26U)
+#define CAN_F15R1_FB26_Msk (0x1U << CAN_F15R1_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F15R1_FB26 CAN_F15R1_FB26_Msk /*!< Filter bit 26 */
+#define CAN_F15R1_FB27_Pos (27U)
+#define CAN_F15R1_FB27_Msk (0x1U << CAN_F15R1_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F15R1_FB27 CAN_F15R1_FB27_Msk /*!< Filter bit 27 */
+#define CAN_F15R1_FB28_Pos (28U)
+#define CAN_F15R1_FB28_Msk (0x1U << CAN_F15R1_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F15R1_FB28 CAN_F15R1_FB28_Msk /*!< Filter bit 28 */
+#define CAN_F15R1_FB29_Pos (29U)
+#define CAN_F15R1_FB29_Msk (0x1U << CAN_F15R1_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F15R1_FB29 CAN_F15R1_FB29_Msk /*!< Filter bit 29 */
+#define CAN_F15R1_FB30_Pos (30U)
+#define CAN_F15R1_FB30_Msk (0x1U << CAN_F15R1_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F15R1_FB30 CAN_F15R1_FB30_Msk /*!< Filter bit 30 */
+#define CAN_F15R1_FB31_Pos (31U)
+#define CAN_F15R1_FB31_Msk (0x1U << CAN_F15R1_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F15R1_FB31 CAN_F15R1_FB31_Msk /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F16R1 register ******************/
+#define CAN_F16R1_FB0_Pos (0U)
+#define CAN_F16R1_FB0_Msk (0x1U << CAN_F16R1_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F16R1_FB0 CAN_F16R1_FB0_Msk /*!< Filter bit 0 */
+#define CAN_F16R1_FB1_Pos (1U)
+#define CAN_F16R1_FB1_Msk (0x1U << CAN_F16R1_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F16R1_FB1 CAN_F16R1_FB1_Msk /*!< Filter bit 1 */
+#define CAN_F16R1_FB2_Pos (2U)
+#define CAN_F16R1_FB2_Msk (0x1U << CAN_F16R1_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F16R1_FB2 CAN_F16R1_FB2_Msk /*!< Filter bit 2 */
+#define CAN_F16R1_FB3_Pos (3U)
+#define CAN_F16R1_FB3_Msk (0x1U << CAN_F16R1_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F16R1_FB3 CAN_F16R1_FB3_Msk /*!< Filter bit 3 */
+#define CAN_F16R1_FB4_Pos (4U)
+#define CAN_F16R1_FB4_Msk (0x1U << CAN_F16R1_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F16R1_FB4 CAN_F16R1_FB4_Msk /*!< Filter bit 4 */
+#define CAN_F16R1_FB5_Pos (5U)
+#define CAN_F16R1_FB5_Msk (0x1U << CAN_F16R1_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F16R1_FB5 CAN_F16R1_FB5_Msk /*!< Filter bit 5 */
+#define CAN_F16R1_FB6_Pos (6U)
+#define CAN_F16R1_FB6_Msk (0x1U << CAN_F16R1_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F16R1_FB6 CAN_F16R1_FB6_Msk /*!< Filter bit 6 */
+#define CAN_F16R1_FB7_Pos (7U)
+#define CAN_F16R1_FB7_Msk (0x1U << CAN_F16R1_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F16R1_FB7 CAN_F16R1_FB7_Msk /*!< Filter bit 7 */
+#define CAN_F16R1_FB8_Pos (8U)
+#define CAN_F16R1_FB8_Msk (0x1U << CAN_F16R1_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F16R1_FB8 CAN_F16R1_FB8_Msk /*!< Filter bit 8 */
+#define CAN_F16R1_FB9_Pos (9U)
+#define CAN_F16R1_FB9_Msk (0x1U << CAN_F16R1_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F16R1_FB9 CAN_F16R1_FB9_Msk /*!< Filter bit 9 */
+#define CAN_F16R1_FB10_Pos (10U)
+#define CAN_F16R1_FB10_Msk (0x1U << CAN_F16R1_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F16R1_FB10 CAN_F16R1_FB10_Msk /*!< Filter bit 10 */
+#define CAN_F16R1_FB11_Pos (11U)
+#define CAN_F16R1_FB11_Msk (0x1U << CAN_F16R1_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F16R1_FB11 CAN_F16R1_FB11_Msk /*!< Filter bit 11 */
+#define CAN_F16R1_FB12_Pos (12U)
+#define CAN_F16R1_FB12_Msk (0x1U << CAN_F16R1_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F16R1_FB12 CAN_F16R1_FB12_Msk /*!< Filter bit 12 */
+#define CAN_F16R1_FB13_Pos (13U)
+#define CAN_F16R1_FB13_Msk (0x1U << CAN_F16R1_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F16R1_FB13 CAN_F16R1_FB13_Msk /*!< Filter bit 13 */
+#define CAN_F16R1_FB14_Pos (14U)
+#define CAN_F16R1_FB14_Msk (0x1U << CAN_F16R1_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F16R1_FB14 CAN_F16R1_FB14_Msk /*!< Filter bit 14 */
+#define CAN_F16R1_FB15_Pos (15U)
+#define CAN_F16R1_FB15_Msk (0x1U << CAN_F16R1_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F16R1_FB15 CAN_F16R1_FB15_Msk /*!< Filter bit 15 */
+#define CAN_F16R1_FB16_Pos (16U)
+#define CAN_F16R1_FB16_Msk (0x1U << CAN_F16R1_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F16R1_FB16 CAN_F16R1_FB16_Msk /*!< Filter bit 16 */
+#define CAN_F16R1_FB17_Pos (17U)
+#define CAN_F16R1_FB17_Msk (0x1U << CAN_F16R1_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F16R1_FB17 CAN_F16R1_FB17_Msk /*!< Filter bit 17 */
+#define CAN_F16R1_FB18_Pos (18U)
+#define CAN_F16R1_FB18_Msk (0x1U << CAN_F16R1_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F16R1_FB18 CAN_F16R1_FB18_Msk /*!< Filter bit 18 */
+#define CAN_F16R1_FB19_Pos (19U)
+#define CAN_F16R1_FB19_Msk (0x1U << CAN_F16R1_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F16R1_FB19 CAN_F16R1_FB19_Msk /*!< Filter bit 19 */
+#define CAN_F16R1_FB20_Pos (20U)
+#define CAN_F16R1_FB20_Msk (0x1U << CAN_F16R1_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F16R1_FB20 CAN_F16R1_FB20_Msk /*!< Filter bit 20 */
+#define CAN_F16R1_FB21_Pos (21U)
+#define CAN_F16R1_FB21_Msk (0x1U << CAN_F16R1_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F16R1_FB21 CAN_F16R1_FB21_Msk /*!< Filter bit 21 */
+#define CAN_F16R1_FB22_Pos (22U)
+#define CAN_F16R1_FB22_Msk (0x1U << CAN_F16R1_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F16R1_FB22 CAN_F16R1_FB22_Msk /*!< Filter bit 22 */
+#define CAN_F16R1_FB23_Pos (23U)
+#define CAN_F16R1_FB23_Msk (0x1U << CAN_F16R1_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F16R1_FB23 CAN_F16R1_FB23_Msk /*!< Filter bit 23 */
+#define CAN_F16R1_FB24_Pos (24U)
+#define CAN_F16R1_FB24_Msk (0x1U << CAN_F16R1_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F16R1_FB24 CAN_F16R1_FB24_Msk /*!< Filter bit 24 */
+#define CAN_F16R1_FB25_Pos (25U)
+#define CAN_F16R1_FB25_Msk (0x1U << CAN_F16R1_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F16R1_FB25 CAN_F16R1_FB25_Msk /*!< Filter bit 25 */
+#define CAN_F16R1_FB26_Pos (26U)
+#define CAN_F16R1_FB26_Msk (0x1U << CAN_F16R1_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F16R1_FB26 CAN_F16R1_FB26_Msk /*!< Filter bit 26 */
+#define CAN_F16R1_FB27_Pos (27U)
+#define CAN_F16R1_FB27_Msk (0x1U << CAN_F16R1_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F16R1_FB27 CAN_F16R1_FB27_Msk /*!< Filter bit 27 */
+#define CAN_F16R1_FB28_Pos (28U)
+#define CAN_F16R1_FB28_Msk (0x1U << CAN_F16R1_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F16R1_FB28 CAN_F16R1_FB28_Msk /*!< Filter bit 28 */
+#define CAN_F16R1_FB29_Pos (29U)
+#define CAN_F16R1_FB29_Msk (0x1U << CAN_F16R1_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F16R1_FB29 CAN_F16R1_FB29_Msk /*!< Filter bit 29 */
+#define CAN_F16R1_FB30_Pos (30U)
+#define CAN_F16R1_FB30_Msk (0x1U << CAN_F16R1_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F16R1_FB30 CAN_F16R1_FB30_Msk /*!< Filter bit 30 */
+#define CAN_F16R1_FB31_Pos (31U)
+#define CAN_F16R1_FB31_Msk (0x1U << CAN_F16R1_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F16R1_FB31 CAN_F16R1_FB31_Msk /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F17R1 register ******************/
+#define CAN_F17R1_FB0_Pos (0U)
+#define CAN_F17R1_FB0_Msk (0x1U << CAN_F17R1_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F17R1_FB0 CAN_F17R1_FB0_Msk /*!< Filter bit 0 */
+#define CAN_F17R1_FB1_Pos (1U)
+#define CAN_F17R1_FB1_Msk (0x1U << CAN_F17R1_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F17R1_FB1 CAN_F17R1_FB1_Msk /*!< Filter bit 1 */
+#define CAN_F17R1_FB2_Pos (2U)
+#define CAN_F17R1_FB2_Msk (0x1U << CAN_F17R1_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F17R1_FB2 CAN_F17R1_FB2_Msk /*!< Filter bit 2 */
+#define CAN_F17R1_FB3_Pos (3U)
+#define CAN_F17R1_FB3_Msk (0x1U << CAN_F17R1_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F17R1_FB3 CAN_F17R1_FB3_Msk /*!< Filter bit 3 */
+#define CAN_F17R1_FB4_Pos (4U)
+#define CAN_F17R1_FB4_Msk (0x1U << CAN_F17R1_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F17R1_FB4 CAN_F17R1_FB4_Msk /*!< Filter bit 4 */
+#define CAN_F17R1_FB5_Pos (5U)
+#define CAN_F17R1_FB5_Msk (0x1U << CAN_F17R1_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F17R1_FB5 CAN_F17R1_FB5_Msk /*!< Filter bit 5 */
+#define CAN_F17R1_FB6_Pos (6U)
+#define CAN_F17R1_FB6_Msk (0x1U << CAN_F17R1_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F17R1_FB6 CAN_F17R1_FB6_Msk /*!< Filter bit 6 */
+#define CAN_F17R1_FB7_Pos (7U)
+#define CAN_F17R1_FB7_Msk (0x1U << CAN_F17R1_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F17R1_FB7 CAN_F17R1_FB7_Msk /*!< Filter bit 7 */
+#define CAN_F17R1_FB8_Pos (8U)
+#define CAN_F17R1_FB8_Msk (0x1U << CAN_F17R1_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F17R1_FB8 CAN_F17R1_FB8_Msk /*!< Filter bit 8 */
+#define CAN_F17R1_FB9_Pos (9U)
+#define CAN_F17R1_FB9_Msk (0x1U << CAN_F17R1_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F17R1_FB9 CAN_F17R1_FB9_Msk /*!< Filter bit 9 */
+#define CAN_F17R1_FB10_Pos (10U)
+#define CAN_F17R1_FB10_Msk (0x1U << CAN_F17R1_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F17R1_FB10 CAN_F17R1_FB10_Msk /*!< Filter bit 10 */
+#define CAN_F17R1_FB11_Pos (11U)
+#define CAN_F17R1_FB11_Msk (0x1U << CAN_F17R1_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F17R1_FB11 CAN_F17R1_FB11_Msk /*!< Filter bit 11 */
+#define CAN_F17R1_FB12_Pos (12U)
+#define CAN_F17R1_FB12_Msk (0x1U << CAN_F17R1_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F17R1_FB12 CAN_F17R1_FB12_Msk /*!< Filter bit 12 */
+#define CAN_F17R1_FB13_Pos (13U)
+#define CAN_F17R1_FB13_Msk (0x1U << CAN_F17R1_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F17R1_FB13 CAN_F17R1_FB13_Msk /*!< Filter bit 13 */
+#define CAN_F17R1_FB14_Pos (14U)
+#define CAN_F17R1_FB14_Msk (0x1U << CAN_F17R1_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F17R1_FB14 CAN_F17R1_FB14_Msk /*!< Filter bit 14 */
+#define CAN_F17R1_FB15_Pos (15U)
+#define CAN_F17R1_FB15_Msk (0x1U << CAN_F17R1_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F17R1_FB15 CAN_F17R1_FB15_Msk /*!< Filter bit 15 */
+#define CAN_F17R1_FB16_Pos (16U)
+#define CAN_F17R1_FB16_Msk (0x1U << CAN_F17R1_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F17R1_FB16 CAN_F17R1_FB16_Msk /*!< Filter bit 16 */
+#define CAN_F17R1_FB17_Pos (17U)
+#define CAN_F17R1_FB17_Msk (0x1U << CAN_F17R1_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F17R1_FB17 CAN_F17R1_FB17_Msk /*!< Filter bit 17 */
+#define CAN_F17R1_FB18_Pos (18U)
+#define CAN_F17R1_FB18_Msk (0x1U << CAN_F17R1_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F17R1_FB18 CAN_F17R1_FB18_Msk /*!< Filter bit 18 */
+#define CAN_F17R1_FB19_Pos (19U)
+#define CAN_F17R1_FB19_Msk (0x1U << CAN_F17R1_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F17R1_FB19 CAN_F17R1_FB19_Msk /*!< Filter bit 19 */
+#define CAN_F17R1_FB20_Pos (20U)
+#define CAN_F17R1_FB20_Msk (0x1U << CAN_F17R1_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F17R1_FB20 CAN_F17R1_FB20_Msk /*!< Filter bit 20 */
+#define CAN_F17R1_FB21_Pos (21U)
+#define CAN_F17R1_FB21_Msk (0x1U << CAN_F17R1_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F17R1_FB21 CAN_F17R1_FB21_Msk /*!< Filter bit 21 */
+#define CAN_F17R1_FB22_Pos (22U)
+#define CAN_F17R1_FB22_Msk (0x1U << CAN_F17R1_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F17R1_FB22 CAN_F17R1_FB22_Msk /*!< Filter bit 22 */
+#define CAN_F17R1_FB23_Pos (23U)
+#define CAN_F17R1_FB23_Msk (0x1U << CAN_F17R1_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F17R1_FB23 CAN_F17R1_FB23_Msk /*!< Filter bit 23 */
+#define CAN_F17R1_FB24_Pos (24U)
+#define CAN_F17R1_FB24_Msk (0x1U << CAN_F17R1_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F17R1_FB24 CAN_F17R1_FB24_Msk /*!< Filter bit 24 */
+#define CAN_F17R1_FB25_Pos (25U)
+#define CAN_F17R1_FB25_Msk (0x1U << CAN_F17R1_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F17R1_FB25 CAN_F17R1_FB25_Msk /*!< Filter bit 25 */
+#define CAN_F17R1_FB26_Pos (26U)
+#define CAN_F17R1_FB26_Msk (0x1U << CAN_F17R1_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F17R1_FB26 CAN_F17R1_FB26_Msk /*!< Filter bit 26 */
+#define CAN_F17R1_FB27_Pos (27U)
+#define CAN_F17R1_FB27_Msk (0x1U << CAN_F17R1_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F17R1_FB27 CAN_F17R1_FB27_Msk /*!< Filter bit 27 */
+#define CAN_F17R1_FB28_Pos (28U)
+#define CAN_F17R1_FB28_Msk (0x1U << CAN_F17R1_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F17R1_FB28 CAN_F17R1_FB28_Msk /*!< Filter bit 28 */
+#define CAN_F17R1_FB29_Pos (29U)
+#define CAN_F17R1_FB29_Msk (0x1U << CAN_F17R1_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F17R1_FB29 CAN_F17R1_FB29_Msk /*!< Filter bit 29 */
+#define CAN_F17R1_FB30_Pos (30U)
+#define CAN_F17R1_FB30_Msk (0x1U << CAN_F17R1_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F17R1_FB30 CAN_F17R1_FB30_Msk /*!< Filter bit 30 */
+#define CAN_F17R1_FB31_Pos (31U)
+#define CAN_F17R1_FB31_Msk (0x1U << CAN_F17R1_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F17R1_FB31 CAN_F17R1_FB31_Msk /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F18R1 register ******************/
+#define CAN_F18R1_FB0_Pos (0U)
+#define CAN_F18R1_FB0_Msk (0x1U << CAN_F18R1_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F18R1_FB0 CAN_F18R1_FB0_Msk /*!< Filter bit 0 */
+#define CAN_F18R1_FB1_Pos (1U)
+#define CAN_F18R1_FB1_Msk (0x1U << CAN_F18R1_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F18R1_FB1 CAN_F18R1_FB1_Msk /*!< Filter bit 1 */
+#define CAN_F18R1_FB2_Pos (2U)
+#define CAN_F18R1_FB2_Msk (0x1U << CAN_F18R1_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F18R1_FB2 CAN_F18R1_FB2_Msk /*!< Filter bit 2 */
+#define CAN_F18R1_FB3_Pos (3U)
+#define CAN_F18R1_FB3_Msk (0x1U << CAN_F18R1_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F18R1_FB3 CAN_F18R1_FB3_Msk /*!< Filter bit 3 */
+#define CAN_F18R1_FB4_Pos (4U)
+#define CAN_F18R1_FB4_Msk (0x1U << CAN_F18R1_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F18R1_FB4 CAN_F18R1_FB4_Msk /*!< Filter bit 4 */
+#define CAN_F18R1_FB5_Pos (5U)
+#define CAN_F18R1_FB5_Msk (0x1U << CAN_F18R1_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F18R1_FB5 CAN_F18R1_FB5_Msk /*!< Filter bit 5 */
+#define CAN_F18R1_FB6_Pos (6U)
+#define CAN_F18R1_FB6_Msk (0x1U << CAN_F18R1_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F18R1_FB6 CAN_F18R1_FB6_Msk /*!< Filter bit 6 */
+#define CAN_F18R1_FB7_Pos (7U)
+#define CAN_F18R1_FB7_Msk (0x1U << CAN_F18R1_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F18R1_FB7 CAN_F18R1_FB7_Msk /*!< Filter bit 7 */
+#define CAN_F18R1_FB8_Pos (8U)
+#define CAN_F18R1_FB8_Msk (0x1U << CAN_F18R1_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F18R1_FB8 CAN_F18R1_FB8_Msk /*!< Filter bit 8 */
+#define CAN_F18R1_FB9_Pos (9U)
+#define CAN_F18R1_FB9_Msk (0x1U << CAN_F18R1_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F18R1_FB9 CAN_F18R1_FB9_Msk /*!< Filter bit 9 */
+#define CAN_F18R1_FB10_Pos (10U)
+#define CAN_F18R1_FB10_Msk (0x1U << CAN_F18R1_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F18R1_FB10 CAN_F18R1_FB10_Msk /*!< Filter bit 10 */
+#define CAN_F18R1_FB11_Pos (11U)
+#define CAN_F18R1_FB11_Msk (0x1U << CAN_F18R1_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F18R1_FB11 CAN_F18R1_FB11_Msk /*!< Filter bit 11 */
+#define CAN_F18R1_FB12_Pos (12U)
+#define CAN_F18R1_FB12_Msk (0x1U << CAN_F18R1_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F18R1_FB12 CAN_F18R1_FB12_Msk /*!< Filter bit 12 */
+#define CAN_F18R1_FB13_Pos (13U)
+#define CAN_F18R1_FB13_Msk (0x1U << CAN_F18R1_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F18R1_FB13 CAN_F18R1_FB13_Msk /*!< Filter bit 13 */
+#define CAN_F18R1_FB14_Pos (14U)
+#define CAN_F18R1_FB14_Msk (0x1U << CAN_F18R1_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F18R1_FB14 CAN_F18R1_FB14_Msk /*!< Filter bit 14 */
+#define CAN_F18R1_FB15_Pos (15U)
+#define CAN_F18R1_FB15_Msk (0x1U << CAN_F18R1_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F18R1_FB15 CAN_F18R1_FB15_Msk /*!< Filter bit 15 */
+#define CAN_F18R1_FB16_Pos (16U)
+#define CAN_F18R1_FB16_Msk (0x1U << CAN_F18R1_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F18R1_FB16 CAN_F18R1_FB16_Msk /*!< Filter bit 16 */
+#define CAN_F18R1_FB17_Pos (17U)
+#define CAN_F18R1_FB17_Msk (0x1U << CAN_F18R1_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F18R1_FB17 CAN_F18R1_FB17_Msk /*!< Filter bit 17 */
+#define CAN_F18R1_FB18_Pos (18U)
+#define CAN_F18R1_FB18_Msk (0x1U << CAN_F18R1_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F18R1_FB18 CAN_F18R1_FB18_Msk /*!< Filter bit 18 */
+#define CAN_F18R1_FB19_Pos (19U)
+#define CAN_F18R1_FB19_Msk (0x1U << CAN_F18R1_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F18R1_FB19 CAN_F18R1_FB19_Msk /*!< Filter bit 19 */
+#define CAN_F18R1_FB20_Pos (20U)
+#define CAN_F18R1_FB20_Msk (0x1U << CAN_F18R1_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F18R1_FB20 CAN_F18R1_FB20_Msk /*!< Filter bit 20 */
+#define CAN_F18R1_FB21_Pos (21U)
+#define CAN_F18R1_FB21_Msk (0x1U << CAN_F18R1_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F18R1_FB21 CAN_F18R1_FB21_Msk /*!< Filter bit 21 */
+#define CAN_F18R1_FB22_Pos (22U)
+#define CAN_F18R1_FB22_Msk (0x1U << CAN_F18R1_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F18R1_FB22 CAN_F18R1_FB22_Msk /*!< Filter bit 22 */
+#define CAN_F18R1_FB23_Pos (23U)
+#define CAN_F18R1_FB23_Msk (0x1U << CAN_F18R1_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F18R1_FB23 CAN_F18R1_FB23_Msk /*!< Filter bit 23 */
+#define CAN_F18R1_FB24_Pos (24U)
+#define CAN_F18R1_FB24_Msk (0x1U << CAN_F18R1_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F18R1_FB24 CAN_F18R1_FB24_Msk /*!< Filter bit 24 */
+#define CAN_F18R1_FB25_Pos (25U)
+#define CAN_F18R1_FB25_Msk (0x1U << CAN_F18R1_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F18R1_FB25 CAN_F18R1_FB25_Msk /*!< Filter bit 25 */
+#define CAN_F18R1_FB26_Pos (26U)
+#define CAN_F18R1_FB26_Msk (0x1U << CAN_F18R1_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F18R1_FB26 CAN_F18R1_FB26_Msk /*!< Filter bit 26 */
+#define CAN_F18R1_FB27_Pos (27U)
+#define CAN_F18R1_FB27_Msk (0x1U << CAN_F18R1_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F18R1_FB27 CAN_F18R1_FB27_Msk /*!< Filter bit 27 */
+#define CAN_F18R1_FB28_Pos (28U)
+#define CAN_F18R1_FB28_Msk (0x1U << CAN_F18R1_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F18R1_FB28 CAN_F18R1_FB28_Msk /*!< Filter bit 28 */
+#define CAN_F18R1_FB29_Pos (29U)
+#define CAN_F18R1_FB29_Msk (0x1U << CAN_F18R1_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F18R1_FB29 CAN_F18R1_FB29_Msk /*!< Filter bit 29 */
+#define CAN_F18R1_FB30_Pos (30U)
+#define CAN_F18R1_FB30_Msk (0x1U << CAN_F18R1_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F18R1_FB30 CAN_F18R1_FB30_Msk /*!< Filter bit 30 */
+#define CAN_F18R1_FB31_Pos (31U)
+#define CAN_F18R1_FB31_Msk (0x1U << CAN_F18R1_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F18R1_FB31 CAN_F18R1_FB31_Msk /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F19R1 register ******************/
+#define CAN_F19R1_FB0_Pos (0U)
+#define CAN_F19R1_FB0_Msk (0x1U << CAN_F19R1_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F19R1_FB0 CAN_F19R1_FB0_Msk /*!< Filter bit 0 */
+#define CAN_F19R1_FB1_Pos (1U)
+#define CAN_F19R1_FB1_Msk (0x1U << CAN_F19R1_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F19R1_FB1 CAN_F19R1_FB1_Msk /*!< Filter bit 1 */
+#define CAN_F19R1_FB2_Pos (2U)
+#define CAN_F19R1_FB2_Msk (0x1U << CAN_F19R1_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F19R1_FB2 CAN_F19R1_FB2_Msk /*!< Filter bit 2 */
+#define CAN_F19R1_FB3_Pos (3U)
+#define CAN_F19R1_FB3_Msk (0x1U << CAN_F19R1_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F19R1_FB3 CAN_F19R1_FB3_Msk /*!< Filter bit 3 */
+#define CAN_F19R1_FB4_Pos (4U)
+#define CAN_F19R1_FB4_Msk (0x1U << CAN_F19R1_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F19R1_FB4 CAN_F19R1_FB4_Msk /*!< Filter bit 4 */
+#define CAN_F19R1_FB5_Pos (5U)
+#define CAN_F19R1_FB5_Msk (0x1U << CAN_F19R1_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F19R1_FB5 CAN_F19R1_FB5_Msk /*!< Filter bit 5 */
+#define CAN_F19R1_FB6_Pos (6U)
+#define CAN_F19R1_FB6_Msk (0x1U << CAN_F19R1_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F19R1_FB6 CAN_F19R1_FB6_Msk /*!< Filter bit 6 */
+#define CAN_F19R1_FB7_Pos (7U)
+#define CAN_F19R1_FB7_Msk (0x1U << CAN_F19R1_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F19R1_FB7 CAN_F19R1_FB7_Msk /*!< Filter bit 7 */
+#define CAN_F19R1_FB8_Pos (8U)
+#define CAN_F19R1_FB8_Msk (0x1U << CAN_F19R1_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F19R1_FB8 CAN_F19R1_FB8_Msk /*!< Filter bit 8 */
+#define CAN_F19R1_FB9_Pos (9U)
+#define CAN_F19R1_FB9_Msk (0x1U << CAN_F19R1_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F19R1_FB9 CAN_F19R1_FB9_Msk /*!< Filter bit 9 */
+#define CAN_F19R1_FB10_Pos (10U)
+#define CAN_F19R1_FB10_Msk (0x1U << CAN_F19R1_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F19R1_FB10 CAN_F19R1_FB10_Msk /*!< Filter bit 10 */
+#define CAN_F19R1_FB11_Pos (11U)
+#define CAN_F19R1_FB11_Msk (0x1U << CAN_F19R1_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F19R1_FB11 CAN_F19R1_FB11_Msk /*!< Filter bit 11 */
+#define CAN_F19R1_FB12_Pos (12U)
+#define CAN_F19R1_FB12_Msk (0x1U << CAN_F19R1_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F19R1_FB12 CAN_F19R1_FB12_Msk /*!< Filter bit 12 */
+#define CAN_F19R1_FB13_Pos (13U)
+#define CAN_F19R1_FB13_Msk (0x1U << CAN_F19R1_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F19R1_FB13 CAN_F19R1_FB13_Msk /*!< Filter bit 13 */
+#define CAN_F19R1_FB14_Pos (14U)
+#define CAN_F19R1_FB14_Msk (0x1U << CAN_F19R1_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F19R1_FB14 CAN_F19R1_FB14_Msk /*!< Filter bit 14 */
+#define CAN_F19R1_FB15_Pos (15U)
+#define CAN_F19R1_FB15_Msk (0x1U << CAN_F19R1_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F19R1_FB15 CAN_F19R1_FB15_Msk /*!< Filter bit 15 */
+#define CAN_F19R1_FB16_Pos (16U)
+#define CAN_F19R1_FB16_Msk (0x1U << CAN_F19R1_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F19R1_FB16 CAN_F19R1_FB16_Msk /*!< Filter bit 16 */
+#define CAN_F19R1_FB17_Pos (17U)
+#define CAN_F19R1_FB17_Msk (0x1U << CAN_F19R1_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F19R1_FB17 CAN_F19R1_FB17_Msk /*!< Filter bit 17 */
+#define CAN_F19R1_FB18_Pos (18U)
+#define CAN_F19R1_FB18_Msk (0x1U << CAN_F19R1_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F19R1_FB18 CAN_F19R1_FB18_Msk /*!< Filter bit 18 */
+#define CAN_F19R1_FB19_Pos (19U)
+#define CAN_F19R1_FB19_Msk (0x1U << CAN_F19R1_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F19R1_FB19 CAN_F19R1_FB19_Msk /*!< Filter bit 19 */
+#define CAN_F19R1_FB20_Pos (20U)
+#define CAN_F19R1_FB20_Msk (0x1U << CAN_F19R1_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F19R1_FB20 CAN_F19R1_FB20_Msk /*!< Filter bit 20 */
+#define CAN_F19R1_FB21_Pos (21U)
+#define CAN_F19R1_FB21_Msk (0x1U << CAN_F19R1_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F19R1_FB21 CAN_F19R1_FB21_Msk /*!< Filter bit 21 */
+#define CAN_F19R1_FB22_Pos (22U)
+#define CAN_F19R1_FB22_Msk (0x1U << CAN_F19R1_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F19R1_FB22 CAN_F19R1_FB22_Msk /*!< Filter bit 22 */
+#define CAN_F19R1_FB23_Pos (23U)
+#define CAN_F19R1_FB23_Msk (0x1U << CAN_F19R1_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F19R1_FB23 CAN_F19R1_FB23_Msk /*!< Filter bit 23 */
+#define CAN_F19R1_FB24_Pos (24U)
+#define CAN_F19R1_FB24_Msk (0x1U << CAN_F19R1_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F19R1_FB24 CAN_F19R1_FB24_Msk /*!< Filter bit 24 */
+#define CAN_F19R1_FB25_Pos (25U)
+#define CAN_F19R1_FB25_Msk (0x1U << CAN_F19R1_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F19R1_FB25 CAN_F19R1_FB25_Msk /*!< Filter bit 25 */
+#define CAN_F19R1_FB26_Pos (26U)
+#define CAN_F19R1_FB26_Msk (0x1U << CAN_F19R1_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F19R1_FB26 CAN_F19R1_FB26_Msk /*!< Filter bit 26 */
+#define CAN_F19R1_FB27_Pos (27U)
+#define CAN_F19R1_FB27_Msk (0x1U << CAN_F19R1_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F19R1_FB27 CAN_F19R1_FB27_Msk /*!< Filter bit 27 */
+#define CAN_F19R1_FB28_Pos (28U)
+#define CAN_F19R1_FB28_Msk (0x1U << CAN_F19R1_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F19R1_FB28 CAN_F19R1_FB28_Msk /*!< Filter bit 28 */
+#define CAN_F19R1_FB29_Pos (29U)
+#define CAN_F19R1_FB29_Msk (0x1U << CAN_F19R1_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F19R1_FB29 CAN_F19R1_FB29_Msk /*!< Filter bit 29 */
+#define CAN_F19R1_FB30_Pos (30U)
+#define CAN_F19R1_FB30_Msk (0x1U << CAN_F19R1_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F19R1_FB30 CAN_F19R1_FB30_Msk /*!< Filter bit 30 */
+#define CAN_F19R1_FB31_Pos (31U)
+#define CAN_F19R1_FB31_Msk (0x1U << CAN_F19R1_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F19R1_FB31 CAN_F19R1_FB31_Msk /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F20R1 register ******************/
+#define CAN_F20R1_FB0_Pos (0U)
+#define CAN_F20R1_FB0_Msk (0x1U << CAN_F20R1_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F20R1_FB0 CAN_F20R1_FB0_Msk /*!< Filter bit 0 */
+#define CAN_F20R1_FB1_Pos (1U)
+#define CAN_F20R1_FB1_Msk (0x1U << CAN_F20R1_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F20R1_FB1 CAN_F20R1_FB1_Msk /*!< Filter bit 1 */
+#define CAN_F20R1_FB2_Pos (2U)
+#define CAN_F20R1_FB2_Msk (0x1U << CAN_F20R1_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F20R1_FB2 CAN_F20R1_FB2_Msk /*!< Filter bit 2 */
+#define CAN_F20R1_FB3_Pos (3U)
+#define CAN_F20R1_FB3_Msk (0x1U << CAN_F20R1_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F20R1_FB3 CAN_F20R1_FB3_Msk /*!< Filter bit 3 */
+#define CAN_F20R1_FB4_Pos (4U)
+#define CAN_F20R1_FB4_Msk (0x1U << CAN_F20R1_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F20R1_FB4 CAN_F20R1_FB4_Msk /*!< Filter bit 4 */
+#define CAN_F20R1_FB5_Pos (5U)
+#define CAN_F20R1_FB5_Msk (0x1U << CAN_F20R1_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F20R1_FB5 CAN_F20R1_FB5_Msk /*!< Filter bit 5 */
+#define CAN_F20R1_FB6_Pos (6U)
+#define CAN_F20R1_FB6_Msk (0x1U << CAN_F20R1_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F20R1_FB6 CAN_F20R1_FB6_Msk /*!< Filter bit 6 */
+#define CAN_F20R1_FB7_Pos (7U)
+#define CAN_F20R1_FB7_Msk (0x1U << CAN_F20R1_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F20R1_FB7 CAN_F20R1_FB7_Msk /*!< Filter bit 7 */
+#define CAN_F20R1_FB8_Pos (8U)
+#define CAN_F20R1_FB8_Msk (0x1U << CAN_F20R1_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F20R1_FB8 CAN_F20R1_FB8_Msk /*!< Filter bit 8 */
+#define CAN_F20R1_FB9_Pos (9U)
+#define CAN_F20R1_FB9_Msk (0x1U << CAN_F20R1_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F20R1_FB9 CAN_F20R1_FB9_Msk /*!< Filter bit 9 */
+#define CAN_F20R1_FB10_Pos (10U)
+#define CAN_F20R1_FB10_Msk (0x1U << CAN_F20R1_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F20R1_FB10 CAN_F20R1_FB10_Msk /*!< Filter bit 10 */
+#define CAN_F20R1_FB11_Pos (11U)
+#define CAN_F20R1_FB11_Msk (0x1U << CAN_F20R1_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F20R1_FB11 CAN_F20R1_FB11_Msk /*!< Filter bit 11 */
+#define CAN_F20R1_FB12_Pos (12U)
+#define CAN_F20R1_FB12_Msk (0x1U << CAN_F20R1_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F20R1_FB12 CAN_F20R1_FB12_Msk /*!< Filter bit 12 */
+#define CAN_F20R1_FB13_Pos (13U)
+#define CAN_F20R1_FB13_Msk (0x1U << CAN_F20R1_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F20R1_FB13 CAN_F20R1_FB13_Msk /*!< Filter bit 13 */
+#define CAN_F20R1_FB14_Pos (14U)
+#define CAN_F20R1_FB14_Msk (0x1U << CAN_F20R1_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F20R1_FB14 CAN_F20R1_FB14_Msk /*!< Filter bit 14 */
+#define CAN_F20R1_FB15_Pos (15U)
+#define CAN_F20R1_FB15_Msk (0x1U << CAN_F20R1_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F20R1_FB15 CAN_F20R1_FB15_Msk /*!< Filter bit 15 */
+#define CAN_F20R1_FB16_Pos (16U)
+#define CAN_F20R1_FB16_Msk (0x1U << CAN_F20R1_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F20R1_FB16 CAN_F20R1_FB16_Msk /*!< Filter bit 16 */
+#define CAN_F20R1_FB17_Pos (17U)
+#define CAN_F20R1_FB17_Msk (0x1U << CAN_F20R1_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F20R1_FB17 CAN_F20R1_FB17_Msk /*!< Filter bit 17 */
+#define CAN_F20R1_FB18_Pos (18U)
+#define CAN_F20R1_FB18_Msk (0x1U << CAN_F20R1_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F20R1_FB18 CAN_F20R1_FB18_Msk /*!< Filter bit 18 */
+#define CAN_F20R1_FB19_Pos (19U)
+#define CAN_F20R1_FB19_Msk (0x1U << CAN_F20R1_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F20R1_FB19 CAN_F20R1_FB19_Msk /*!< Filter bit 19 */
+#define CAN_F20R1_FB20_Pos (20U)
+#define CAN_F20R1_FB20_Msk (0x1U << CAN_F20R1_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F20R1_FB20 CAN_F20R1_FB20_Msk /*!< Filter bit 20 */
+#define CAN_F20R1_FB21_Pos (21U)
+#define CAN_F20R1_FB21_Msk (0x1U << CAN_F20R1_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F20R1_FB21 CAN_F20R1_FB21_Msk /*!< Filter bit 21 */
+#define CAN_F20R1_FB22_Pos (22U)
+#define CAN_F20R1_FB22_Msk (0x1U << CAN_F20R1_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F20R1_FB22 CAN_F20R1_FB22_Msk /*!< Filter bit 22 */
+#define CAN_F20R1_FB23_Pos (23U)
+#define CAN_F20R1_FB23_Msk (0x1U << CAN_F20R1_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F20R1_FB23 CAN_F20R1_FB23_Msk /*!< Filter bit 23 */
+#define CAN_F20R1_FB24_Pos (24U)
+#define CAN_F20R1_FB24_Msk (0x1U << CAN_F20R1_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F20R1_FB24 CAN_F20R1_FB24_Msk /*!< Filter bit 24 */
+#define CAN_F20R1_FB25_Pos (25U)
+#define CAN_F20R1_FB25_Msk (0x1U << CAN_F20R1_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F20R1_FB25 CAN_F20R1_FB25_Msk /*!< Filter bit 25 */
+#define CAN_F20R1_FB26_Pos (26U)
+#define CAN_F20R1_FB26_Msk (0x1U << CAN_F20R1_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F20R1_FB26 CAN_F20R1_FB26_Msk /*!< Filter bit 26 */
+#define CAN_F20R1_FB27_Pos (27U)
+#define CAN_F20R1_FB27_Msk (0x1U << CAN_F20R1_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F20R1_FB27 CAN_F20R1_FB27_Msk /*!< Filter bit 27 */
+#define CAN_F20R1_FB28_Pos (28U)
+#define CAN_F20R1_FB28_Msk (0x1U << CAN_F20R1_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F20R1_FB28 CAN_F20R1_FB28_Msk /*!< Filter bit 28 */
+#define CAN_F20R1_FB29_Pos (29U)
+#define CAN_F20R1_FB29_Msk (0x1U << CAN_F20R1_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F20R1_FB29 CAN_F20R1_FB29_Msk /*!< Filter bit 29 */
+#define CAN_F20R1_FB30_Pos (30U)
+#define CAN_F20R1_FB30_Msk (0x1U << CAN_F20R1_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F20R1_FB30 CAN_F20R1_FB30_Msk /*!< Filter bit 30 */
+#define CAN_F20R1_FB31_Pos (31U)
+#define CAN_F20R1_FB31_Msk (0x1U << CAN_F20R1_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F20R1_FB31 CAN_F20R1_FB31_Msk /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F21R1 register ******************/
+#define CAN_F21R1_FB0_Pos (0U)
+#define CAN_F21R1_FB0_Msk (0x1U << CAN_F21R1_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F21R1_FB0 CAN_F21R1_FB0_Msk /*!< Filter bit 0 */
+#define CAN_F21R1_FB1_Pos (1U)
+#define CAN_F21R1_FB1_Msk (0x1U << CAN_F21R1_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F21R1_FB1 CAN_F21R1_FB1_Msk /*!< Filter bit 1 */
+#define CAN_F21R1_FB2_Pos (2U)
+#define CAN_F21R1_FB2_Msk (0x1U << CAN_F21R1_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F21R1_FB2 CAN_F21R1_FB2_Msk /*!< Filter bit 2 */
+#define CAN_F21R1_FB3_Pos (3U)
+#define CAN_F21R1_FB3_Msk (0x1U << CAN_F21R1_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F21R1_FB3 CAN_F21R1_FB3_Msk /*!< Filter bit 3 */
+#define CAN_F21R1_FB4_Pos (4U)
+#define CAN_F21R1_FB4_Msk (0x1U << CAN_F21R1_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F21R1_FB4 CAN_F21R1_FB4_Msk /*!< Filter bit 4 */
+#define CAN_F21R1_FB5_Pos (5U)
+#define CAN_F21R1_FB5_Msk (0x1U << CAN_F21R1_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F21R1_FB5 CAN_F21R1_FB5_Msk /*!< Filter bit 5 */
+#define CAN_F21R1_FB6_Pos (6U)
+#define CAN_F21R1_FB6_Msk (0x1U << CAN_F21R1_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F21R1_FB6 CAN_F21R1_FB6_Msk /*!< Filter bit 6 */
+#define CAN_F21R1_FB7_Pos (7U)
+#define CAN_F21R1_FB7_Msk (0x1U << CAN_F21R1_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F21R1_FB7 CAN_F21R1_FB7_Msk /*!< Filter bit 7 */
+#define CAN_F21R1_FB8_Pos (8U)
+#define CAN_F21R1_FB8_Msk (0x1U << CAN_F21R1_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F21R1_FB8 CAN_F21R1_FB8_Msk /*!< Filter bit 8 */
+#define CAN_F21R1_FB9_Pos (9U)
+#define CAN_F21R1_FB9_Msk (0x1U << CAN_F21R1_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F21R1_FB9 CAN_F21R1_FB9_Msk /*!< Filter bit 9 */
+#define CAN_F21R1_FB10_Pos (10U)
+#define CAN_F21R1_FB10_Msk (0x1U << CAN_F21R1_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F21R1_FB10 CAN_F21R1_FB10_Msk /*!< Filter bit 10 */
+#define CAN_F21R1_FB11_Pos (11U)
+#define CAN_F21R1_FB11_Msk (0x1U << CAN_F21R1_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F21R1_FB11 CAN_F21R1_FB11_Msk /*!< Filter bit 11 */
+#define CAN_F21R1_FB12_Pos (12U)
+#define CAN_F21R1_FB12_Msk (0x1U << CAN_F21R1_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F21R1_FB12 CAN_F21R1_FB12_Msk /*!< Filter bit 12 */
+#define CAN_F21R1_FB13_Pos (13U)
+#define CAN_F21R1_FB13_Msk (0x1U << CAN_F21R1_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F21R1_FB13 CAN_F21R1_FB13_Msk /*!< Filter bit 13 */
+#define CAN_F21R1_FB14_Pos (14U)
+#define CAN_F21R1_FB14_Msk (0x1U << CAN_F21R1_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F21R1_FB14 CAN_F21R1_FB14_Msk /*!< Filter bit 14 */
+#define CAN_F21R1_FB15_Pos (15U)
+#define CAN_F21R1_FB15_Msk (0x1U << CAN_F21R1_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F21R1_FB15 CAN_F21R1_FB15_Msk /*!< Filter bit 15 */
+#define CAN_F21R1_FB16_Pos (16U)
+#define CAN_F21R1_FB16_Msk (0x1U << CAN_F21R1_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F21R1_FB16 CAN_F21R1_FB16_Msk /*!< Filter bit 16 */
+#define CAN_F21R1_FB17_Pos (17U)
+#define CAN_F21R1_FB17_Msk (0x1U << CAN_F21R1_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F21R1_FB17 CAN_F21R1_FB17_Msk /*!< Filter bit 17 */
+#define CAN_F21R1_FB18_Pos (18U)
+#define CAN_F21R1_FB18_Msk (0x1U << CAN_F21R1_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F21R1_FB18 CAN_F21R1_FB18_Msk /*!< Filter bit 18 */
+#define CAN_F21R1_FB19_Pos (19U)
+#define CAN_F21R1_FB19_Msk (0x1U << CAN_F21R1_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F21R1_FB19 CAN_F21R1_FB19_Msk /*!< Filter bit 19 */
+#define CAN_F21R1_FB20_Pos (20U)
+#define CAN_F21R1_FB20_Msk (0x1U << CAN_F21R1_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F21R1_FB20 CAN_F21R1_FB20_Msk /*!< Filter bit 20 */
+#define CAN_F21R1_FB21_Pos (21U)
+#define CAN_F21R1_FB21_Msk (0x1U << CAN_F21R1_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F21R1_FB21 CAN_F21R1_FB21_Msk /*!< Filter bit 21 */
+#define CAN_F21R1_FB22_Pos (22U)
+#define CAN_F21R1_FB22_Msk (0x1U << CAN_F21R1_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F21R1_FB22 CAN_F21R1_FB22_Msk /*!< Filter bit 22 */
+#define CAN_F21R1_FB23_Pos (23U)
+#define CAN_F21R1_FB23_Msk (0x1U << CAN_F21R1_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F21R1_FB23 CAN_F21R1_FB23_Msk /*!< Filter bit 23 */
+#define CAN_F21R1_FB24_Pos (24U)
+#define CAN_F21R1_FB24_Msk (0x1U << CAN_F21R1_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F21R1_FB24 CAN_F21R1_FB24_Msk /*!< Filter bit 24 */
+#define CAN_F21R1_FB25_Pos (25U)
+#define CAN_F21R1_FB25_Msk (0x1U << CAN_F21R1_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F21R1_FB25 CAN_F21R1_FB25_Msk /*!< Filter bit 25 */
+#define CAN_F21R1_FB26_Pos (26U)
+#define CAN_F21R1_FB26_Msk (0x1U << CAN_F21R1_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F21R1_FB26 CAN_F21R1_FB26_Msk /*!< Filter bit 26 */
+#define CAN_F21R1_FB27_Pos (27U)
+#define CAN_F21R1_FB27_Msk (0x1U << CAN_F21R1_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F21R1_FB27 CAN_F21R1_FB27_Msk /*!< Filter bit 27 */
+#define CAN_F21R1_FB28_Pos (28U)
+#define CAN_F21R1_FB28_Msk (0x1U << CAN_F21R1_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F21R1_FB28 CAN_F21R1_FB28_Msk /*!< Filter bit 28 */
+#define CAN_F21R1_FB29_Pos (29U)
+#define CAN_F21R1_FB29_Msk (0x1U << CAN_F21R1_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F21R1_FB29 CAN_F21R1_FB29_Msk /*!< Filter bit 29 */
+#define CAN_F21R1_FB30_Pos (30U)
+#define CAN_F21R1_FB30_Msk (0x1U << CAN_F21R1_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F21R1_FB30 CAN_F21R1_FB30_Msk /*!< Filter bit 30 */
+#define CAN_F21R1_FB31_Pos (31U)
+#define CAN_F21R1_FB31_Msk (0x1U << CAN_F21R1_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F21R1_FB31 CAN_F21R1_FB31_Msk /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F22R1 register ******************/
+#define CAN_F22R1_FB0_Pos (0U)
+#define CAN_F22R1_FB0_Msk (0x1U << CAN_F22R1_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F22R1_FB0 CAN_F22R1_FB0_Msk /*!< Filter bit 0 */
+#define CAN_F22R1_FB1_Pos (1U)
+#define CAN_F22R1_FB1_Msk (0x1U << CAN_F22R1_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F22R1_FB1 CAN_F22R1_FB1_Msk /*!< Filter bit 1 */
+#define CAN_F22R1_FB2_Pos (2U)
+#define CAN_F22R1_FB2_Msk (0x1U << CAN_F22R1_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F22R1_FB2 CAN_F22R1_FB2_Msk /*!< Filter bit 2 */
+#define CAN_F22R1_FB3_Pos (3U)
+#define CAN_F22R1_FB3_Msk (0x1U << CAN_F22R1_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F22R1_FB3 CAN_F22R1_FB3_Msk /*!< Filter bit 3 */
+#define CAN_F22R1_FB4_Pos (4U)
+#define CAN_F22R1_FB4_Msk (0x1U << CAN_F22R1_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F22R1_FB4 CAN_F22R1_FB4_Msk /*!< Filter bit 4 */
+#define CAN_F22R1_FB5_Pos (5U)
+#define CAN_F22R1_FB5_Msk (0x1U << CAN_F22R1_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F22R1_FB5 CAN_F22R1_FB5_Msk /*!< Filter bit 5 */
+#define CAN_F22R1_FB6_Pos (6U)
+#define CAN_F22R1_FB6_Msk (0x1U << CAN_F22R1_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F22R1_FB6 CAN_F22R1_FB6_Msk /*!< Filter bit 6 */
+#define CAN_F22R1_FB7_Pos (7U)
+#define CAN_F22R1_FB7_Msk (0x1U << CAN_F22R1_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F22R1_FB7 CAN_F22R1_FB7_Msk /*!< Filter bit 7 */
+#define CAN_F22R1_FB8_Pos (8U)
+#define CAN_F22R1_FB8_Msk (0x1U << CAN_F22R1_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F22R1_FB8 CAN_F22R1_FB8_Msk /*!< Filter bit 8 */
+#define CAN_F22R1_FB9_Pos (9U)
+#define CAN_F22R1_FB9_Msk (0x1U << CAN_F22R1_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F22R1_FB9 CAN_F22R1_FB9_Msk /*!< Filter bit 9 */
+#define CAN_F22R1_FB10_Pos (10U)
+#define CAN_F22R1_FB10_Msk (0x1U << CAN_F22R1_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F22R1_FB10 CAN_F22R1_FB10_Msk /*!< Filter bit 10 */
+#define CAN_F22R1_FB11_Pos (11U)
+#define CAN_F22R1_FB11_Msk (0x1U << CAN_F22R1_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F22R1_FB11 CAN_F22R1_FB11_Msk /*!< Filter bit 11 */
+#define CAN_F22R1_FB12_Pos (12U)
+#define CAN_F22R1_FB12_Msk (0x1U << CAN_F22R1_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F22R1_FB12 CAN_F22R1_FB12_Msk /*!< Filter bit 12 */
+#define CAN_F22R1_FB13_Pos (13U)
+#define CAN_F22R1_FB13_Msk (0x1U << CAN_F22R1_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F22R1_FB13 CAN_F22R1_FB13_Msk /*!< Filter bit 13 */
+#define CAN_F22R1_FB14_Pos (14U)
+#define CAN_F22R1_FB14_Msk (0x1U << CAN_F22R1_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F22R1_FB14 CAN_F22R1_FB14_Msk /*!< Filter bit 14 */
+#define CAN_F22R1_FB15_Pos (15U)
+#define CAN_F22R1_FB15_Msk (0x1U << CAN_F22R1_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F22R1_FB15 CAN_F22R1_FB15_Msk /*!< Filter bit 15 */
+#define CAN_F22R1_FB16_Pos (16U)
+#define CAN_F22R1_FB16_Msk (0x1U << CAN_F22R1_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F22R1_FB16 CAN_F22R1_FB16_Msk /*!< Filter bit 16 */
+#define CAN_F22R1_FB17_Pos (17U)
+#define CAN_F22R1_FB17_Msk (0x1U << CAN_F22R1_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F22R1_FB17 CAN_F22R1_FB17_Msk /*!< Filter bit 17 */
+#define CAN_F22R1_FB18_Pos (18U)
+#define CAN_F22R1_FB18_Msk (0x1U << CAN_F22R1_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F22R1_FB18 CAN_F22R1_FB18_Msk /*!< Filter bit 18 */
+#define CAN_F22R1_FB19_Pos (19U)
+#define CAN_F22R1_FB19_Msk (0x1U << CAN_F22R1_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F22R1_FB19 CAN_F22R1_FB19_Msk /*!< Filter bit 19 */
+#define CAN_F22R1_FB20_Pos (20U)
+#define CAN_F22R1_FB20_Msk (0x1U << CAN_F22R1_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F22R1_FB20 CAN_F22R1_FB20_Msk /*!< Filter bit 20 */
+#define CAN_F22R1_FB21_Pos (21U)
+#define CAN_F22R1_FB21_Msk (0x1U << CAN_F22R1_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F22R1_FB21 CAN_F22R1_FB21_Msk /*!< Filter bit 21 */
+#define CAN_F22R1_FB22_Pos (22U)
+#define CAN_F22R1_FB22_Msk (0x1U << CAN_F22R1_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F22R1_FB22 CAN_F22R1_FB22_Msk /*!< Filter bit 22 */
+#define CAN_F22R1_FB23_Pos (23U)
+#define CAN_F22R1_FB23_Msk (0x1U << CAN_F22R1_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F22R1_FB23 CAN_F22R1_FB23_Msk /*!< Filter bit 23 */
+#define CAN_F22R1_FB24_Pos (24U)
+#define CAN_F22R1_FB24_Msk (0x1U << CAN_F22R1_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F22R1_FB24 CAN_F22R1_FB24_Msk /*!< Filter bit 24 */
+#define CAN_F22R1_FB25_Pos (25U)
+#define CAN_F22R1_FB25_Msk (0x1U << CAN_F22R1_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F22R1_FB25 CAN_F22R1_FB25_Msk /*!< Filter bit 25 */
+#define CAN_F22R1_FB26_Pos (26U)
+#define CAN_F22R1_FB26_Msk (0x1U << CAN_F22R1_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F22R1_FB26 CAN_F22R1_FB26_Msk /*!< Filter bit 26 */
+#define CAN_F22R1_FB27_Pos (27U)
+#define CAN_F22R1_FB27_Msk (0x1U << CAN_F22R1_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F22R1_FB27 CAN_F22R1_FB27_Msk /*!< Filter bit 27 */
+#define CAN_F22R1_FB28_Pos (28U)
+#define CAN_F22R1_FB28_Msk (0x1U << CAN_F22R1_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F22R1_FB28 CAN_F22R1_FB28_Msk /*!< Filter bit 28 */
+#define CAN_F22R1_FB29_Pos (29U)
+#define CAN_F22R1_FB29_Msk (0x1U << CAN_F22R1_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F22R1_FB29 CAN_F22R1_FB29_Msk /*!< Filter bit 29 */
+#define CAN_F22R1_FB30_Pos (30U)
+#define CAN_F22R1_FB30_Msk (0x1U << CAN_F22R1_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F22R1_FB30 CAN_F22R1_FB30_Msk /*!< Filter bit 30 */
+#define CAN_F22R1_FB31_Pos (31U)
+#define CAN_F22R1_FB31_Msk (0x1U << CAN_F22R1_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F22R1_FB31 CAN_F22R1_FB31_Msk /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F23R1 register ******************/
+#define CAN_F23R1_FB0_Pos (0U)
+#define CAN_F23R1_FB0_Msk (0x1U << CAN_F23R1_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F23R1_FB0 CAN_F23R1_FB0_Msk /*!< Filter bit 0 */
+#define CAN_F23R1_FB1_Pos (1U)
+#define CAN_F23R1_FB1_Msk (0x1U << CAN_F23R1_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F23R1_FB1 CAN_F23R1_FB1_Msk /*!< Filter bit 1 */
+#define CAN_F23R1_FB2_Pos (2U)
+#define CAN_F23R1_FB2_Msk (0x1U << CAN_F23R1_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F23R1_FB2 CAN_F23R1_FB2_Msk /*!< Filter bit 2 */
+#define CAN_F23R1_FB3_Pos (3U)
+#define CAN_F23R1_FB3_Msk (0x1U << CAN_F23R1_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F23R1_FB3 CAN_F23R1_FB3_Msk /*!< Filter bit 3 */
+#define CAN_F23R1_FB4_Pos (4U)
+#define CAN_F23R1_FB4_Msk (0x1U << CAN_F23R1_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F23R1_FB4 CAN_F23R1_FB4_Msk /*!< Filter bit 4 */
+#define CAN_F23R1_FB5_Pos (5U)
+#define CAN_F23R1_FB5_Msk (0x1U << CAN_F23R1_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F23R1_FB5 CAN_F23R1_FB5_Msk /*!< Filter bit 5 */
+#define CAN_F23R1_FB6_Pos (6U)
+#define CAN_F23R1_FB6_Msk (0x1U << CAN_F23R1_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F23R1_FB6 CAN_F23R1_FB6_Msk /*!< Filter bit 6 */
+#define CAN_F23R1_FB7_Pos (7U)
+#define CAN_F23R1_FB7_Msk (0x1U << CAN_F23R1_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F23R1_FB7 CAN_F23R1_FB7_Msk /*!< Filter bit 7 */
+#define CAN_F23R1_FB8_Pos (8U)
+#define CAN_F23R1_FB8_Msk (0x1U << CAN_F23R1_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F23R1_FB8 CAN_F23R1_FB8_Msk /*!< Filter bit 8 */
+#define CAN_F23R1_FB9_Pos (9U)
+#define CAN_F23R1_FB9_Msk (0x1U << CAN_F23R1_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F23R1_FB9 CAN_F23R1_FB9_Msk /*!< Filter bit 9 */
+#define CAN_F23R1_FB10_Pos (10U)
+#define CAN_F23R1_FB10_Msk (0x1U << CAN_F23R1_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F23R1_FB10 CAN_F23R1_FB10_Msk /*!< Filter bit 10 */
+#define CAN_F23R1_FB11_Pos (11U)
+#define CAN_F23R1_FB11_Msk (0x1U << CAN_F23R1_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F23R1_FB11 CAN_F23R1_FB11_Msk /*!< Filter bit 11 */
+#define CAN_F23R1_FB12_Pos (12U)
+#define CAN_F23R1_FB12_Msk (0x1U << CAN_F23R1_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F23R1_FB12 CAN_F23R1_FB12_Msk /*!< Filter bit 12 */
+#define CAN_F23R1_FB13_Pos (13U)
+#define CAN_F23R1_FB13_Msk (0x1U << CAN_F23R1_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F23R1_FB13 CAN_F23R1_FB13_Msk /*!< Filter bit 13 */
+#define CAN_F23R1_FB14_Pos (14U)
+#define CAN_F23R1_FB14_Msk (0x1U << CAN_F23R1_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F23R1_FB14 CAN_F23R1_FB14_Msk /*!< Filter bit 14 */
+#define CAN_F23R1_FB15_Pos (15U)
+#define CAN_F23R1_FB15_Msk (0x1U << CAN_F23R1_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F23R1_FB15 CAN_F23R1_FB15_Msk /*!< Filter bit 15 */
+#define CAN_F23R1_FB16_Pos (16U)
+#define CAN_F23R1_FB16_Msk (0x1U << CAN_F23R1_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F23R1_FB16 CAN_F23R1_FB16_Msk /*!< Filter bit 16 */
+#define CAN_F23R1_FB17_Pos (17U)
+#define CAN_F23R1_FB17_Msk (0x1U << CAN_F23R1_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F23R1_FB17 CAN_F23R1_FB17_Msk /*!< Filter bit 17 */
+#define CAN_F23R1_FB18_Pos (18U)
+#define CAN_F23R1_FB18_Msk (0x1U << CAN_F23R1_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F23R1_FB18 CAN_F23R1_FB18_Msk /*!< Filter bit 18 */
+#define CAN_F23R1_FB19_Pos (19U)
+#define CAN_F23R1_FB19_Msk (0x1U << CAN_F23R1_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F23R1_FB19 CAN_F23R1_FB19_Msk /*!< Filter bit 19 */
+#define CAN_F23R1_FB20_Pos (20U)
+#define CAN_F23R1_FB20_Msk (0x1U << CAN_F23R1_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F23R1_FB20 CAN_F23R1_FB20_Msk /*!< Filter bit 20 */
+#define CAN_F23R1_FB21_Pos (21U)
+#define CAN_F23R1_FB21_Msk (0x1U << CAN_F23R1_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F23R1_FB21 CAN_F23R1_FB21_Msk /*!< Filter bit 21 */
+#define CAN_F23R1_FB22_Pos (22U)
+#define CAN_F23R1_FB22_Msk (0x1U << CAN_F23R1_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F23R1_FB22 CAN_F23R1_FB22_Msk /*!< Filter bit 22 */
+#define CAN_F23R1_FB23_Pos (23U)
+#define CAN_F23R1_FB23_Msk (0x1U << CAN_F23R1_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F23R1_FB23 CAN_F23R1_FB23_Msk /*!< Filter bit 23 */
+#define CAN_F23R1_FB24_Pos (24U)
+#define CAN_F23R1_FB24_Msk (0x1U << CAN_F23R1_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F23R1_FB24 CAN_F23R1_FB24_Msk /*!< Filter bit 24 */
+#define CAN_F23R1_FB25_Pos (25U)
+#define CAN_F23R1_FB25_Msk (0x1U << CAN_F23R1_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F23R1_FB25 CAN_F23R1_FB25_Msk /*!< Filter bit 25 */
+#define CAN_F23R1_FB26_Pos (26U)
+#define CAN_F23R1_FB26_Msk (0x1U << CAN_F23R1_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F23R1_FB26 CAN_F23R1_FB26_Msk /*!< Filter bit 26 */
+#define CAN_F23R1_FB27_Pos (27U)
+#define CAN_F23R1_FB27_Msk (0x1U << CAN_F23R1_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F23R1_FB27 CAN_F23R1_FB27_Msk /*!< Filter bit 27 */
+#define CAN_F23R1_FB28_Pos (28U)
+#define CAN_F23R1_FB28_Msk (0x1U << CAN_F23R1_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F23R1_FB28 CAN_F23R1_FB28_Msk /*!< Filter bit 28 */
+#define CAN_F23R1_FB29_Pos (29U)
+#define CAN_F23R1_FB29_Msk (0x1U << CAN_F23R1_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F23R1_FB29 CAN_F23R1_FB29_Msk /*!< Filter bit 29 */
+#define CAN_F23R1_FB30_Pos (30U)
+#define CAN_F23R1_FB30_Msk (0x1U << CAN_F23R1_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F23R1_FB30 CAN_F23R1_FB30_Msk /*!< Filter bit 30 */
+#define CAN_F23R1_FB31_Pos (31U)
+#define CAN_F23R1_FB31_Msk (0x1U << CAN_F23R1_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F23R1_FB31 CAN_F23R1_FB31_Msk /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F24R1 register ******************/
+#define CAN_F24R1_FB0_Pos (0U)
+#define CAN_F24R1_FB0_Msk (0x1U << CAN_F24R1_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F24R1_FB0 CAN_F24R1_FB0_Msk /*!< Filter bit 0 */
+#define CAN_F24R1_FB1_Pos (1U)
+#define CAN_F24R1_FB1_Msk (0x1U << CAN_F24R1_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F24R1_FB1 CAN_F24R1_FB1_Msk /*!< Filter bit 1 */
+#define CAN_F24R1_FB2_Pos (2U)
+#define CAN_F24R1_FB2_Msk (0x1U << CAN_F24R1_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F24R1_FB2 CAN_F24R1_FB2_Msk /*!< Filter bit 2 */
+#define CAN_F24R1_FB3_Pos (3U)
+#define CAN_F24R1_FB3_Msk (0x1U << CAN_F24R1_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F24R1_FB3 CAN_F24R1_FB3_Msk /*!< Filter bit 3 */
+#define CAN_F24R1_FB4_Pos (4U)
+#define CAN_F24R1_FB4_Msk (0x1U << CAN_F24R1_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F24R1_FB4 CAN_F24R1_FB4_Msk /*!< Filter bit 4 */
+#define CAN_F24R1_FB5_Pos (5U)
+#define CAN_F24R1_FB5_Msk (0x1U << CAN_F24R1_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F24R1_FB5 CAN_F24R1_FB5_Msk /*!< Filter bit 5 */
+#define CAN_F24R1_FB6_Pos (6U)
+#define CAN_F24R1_FB6_Msk (0x1U << CAN_F24R1_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F24R1_FB6 CAN_F24R1_FB6_Msk /*!< Filter bit 6 */
+#define CAN_F24R1_FB7_Pos (7U)
+#define CAN_F24R1_FB7_Msk (0x1U << CAN_F24R1_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F24R1_FB7 CAN_F24R1_FB7_Msk /*!< Filter bit 7 */
+#define CAN_F24R1_FB8_Pos (8U)
+#define CAN_F24R1_FB8_Msk (0x1U << CAN_F24R1_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F24R1_FB8 CAN_F24R1_FB8_Msk /*!< Filter bit 8 */
+#define CAN_F24R1_FB9_Pos (9U)
+#define CAN_F24R1_FB9_Msk (0x1U << CAN_F24R1_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F24R1_FB9 CAN_F24R1_FB9_Msk /*!< Filter bit 9 */
+#define CAN_F24R1_FB10_Pos (10U)
+#define CAN_F24R1_FB10_Msk (0x1U << CAN_F24R1_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F24R1_FB10 CAN_F24R1_FB10_Msk /*!< Filter bit 10 */
+#define CAN_F24R1_FB11_Pos (11U)
+#define CAN_F24R1_FB11_Msk (0x1U << CAN_F24R1_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F24R1_FB11 CAN_F24R1_FB11_Msk /*!< Filter bit 11 */
+#define CAN_F24R1_FB12_Pos (12U)
+#define CAN_F24R1_FB12_Msk (0x1U << CAN_F24R1_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F24R1_FB12 CAN_F24R1_FB12_Msk /*!< Filter bit 12 */
+#define CAN_F24R1_FB13_Pos (13U)
+#define CAN_F24R1_FB13_Msk (0x1U << CAN_F24R1_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F24R1_FB13 CAN_F24R1_FB13_Msk /*!< Filter bit 13 */
+#define CAN_F24R1_FB14_Pos (14U)
+#define CAN_F24R1_FB14_Msk (0x1U << CAN_F24R1_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F24R1_FB14 CAN_F24R1_FB14_Msk /*!< Filter bit 14 */
+#define CAN_F24R1_FB15_Pos (15U)
+#define CAN_F24R1_FB15_Msk (0x1U << CAN_F24R1_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F24R1_FB15 CAN_F24R1_FB15_Msk /*!< Filter bit 15 */
+#define CAN_F24R1_FB16_Pos (16U)
+#define CAN_F24R1_FB16_Msk (0x1U << CAN_F24R1_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F24R1_FB16 CAN_F24R1_FB16_Msk /*!< Filter bit 16 */
+#define CAN_F24R1_FB17_Pos (17U)
+#define CAN_F24R1_FB17_Msk (0x1U << CAN_F24R1_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F24R1_FB17 CAN_F24R1_FB17_Msk /*!< Filter bit 17 */
+#define CAN_F24R1_FB18_Pos (18U)
+#define CAN_F24R1_FB18_Msk (0x1U << CAN_F24R1_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F24R1_FB18 CAN_F24R1_FB18_Msk /*!< Filter bit 18 */
+#define CAN_F24R1_FB19_Pos (19U)
+#define CAN_F24R1_FB19_Msk (0x1U << CAN_F24R1_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F24R1_FB19 CAN_F24R1_FB19_Msk /*!< Filter bit 19 */
+#define CAN_F24R1_FB20_Pos (20U)
+#define CAN_F24R1_FB20_Msk (0x1U << CAN_F24R1_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F24R1_FB20 CAN_F24R1_FB20_Msk /*!< Filter bit 20 */
+#define CAN_F24R1_FB21_Pos (21U)
+#define CAN_F24R1_FB21_Msk (0x1U << CAN_F24R1_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F24R1_FB21 CAN_F24R1_FB21_Msk /*!< Filter bit 21 */
+#define CAN_F24R1_FB22_Pos (22U)
+#define CAN_F24R1_FB22_Msk (0x1U << CAN_F24R1_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F24R1_FB22 CAN_F24R1_FB22_Msk /*!< Filter bit 22 */
+#define CAN_F24R1_FB23_Pos (23U)
+#define CAN_F24R1_FB23_Msk (0x1U << CAN_F24R1_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F24R1_FB23 CAN_F24R1_FB23_Msk /*!< Filter bit 23 */
+#define CAN_F24R1_FB24_Pos (24U)
+#define CAN_F24R1_FB24_Msk (0x1U << CAN_F24R1_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F24R1_FB24 CAN_F24R1_FB24_Msk /*!< Filter bit 24 */
+#define CAN_F24R1_FB25_Pos (25U)
+#define CAN_F24R1_FB25_Msk (0x1U << CAN_F24R1_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F24R1_FB25 CAN_F24R1_FB25_Msk /*!< Filter bit 25 */
+#define CAN_F24R1_FB26_Pos (26U)
+#define CAN_F24R1_FB26_Msk (0x1U << CAN_F24R1_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F24R1_FB26 CAN_F24R1_FB26_Msk /*!< Filter bit 26 */
+#define CAN_F24R1_FB27_Pos (27U)
+#define CAN_F24R1_FB27_Msk (0x1U << CAN_F24R1_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F24R1_FB27 CAN_F24R1_FB27_Msk /*!< Filter bit 27 */
+#define CAN_F24R1_FB28_Pos (28U)
+#define CAN_F24R1_FB28_Msk (0x1U << CAN_F24R1_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F24R1_FB28 CAN_F24R1_FB28_Msk /*!< Filter bit 28 */
+#define CAN_F24R1_FB29_Pos (29U)
+#define CAN_F24R1_FB29_Msk (0x1U << CAN_F24R1_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F24R1_FB29 CAN_F24R1_FB29_Msk /*!< Filter bit 29 */
+#define CAN_F24R1_FB30_Pos (30U)
+#define CAN_F24R1_FB30_Msk (0x1U << CAN_F24R1_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F24R1_FB30 CAN_F24R1_FB30_Msk /*!< Filter bit 30 */
+#define CAN_F24R1_FB31_Pos (31U)
+#define CAN_F24R1_FB31_Msk (0x1U << CAN_F24R1_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F24R1_FB31 CAN_F24R1_FB31_Msk /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F25R1 register ******************/
+#define CAN_F25R1_FB0_Pos (0U)
+#define CAN_F25R1_FB0_Msk (0x1U << CAN_F25R1_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F25R1_FB0 CAN_F25R1_FB0_Msk /*!< Filter bit 0 */
+#define CAN_F25R1_FB1_Pos (1U)
+#define CAN_F25R1_FB1_Msk (0x1U << CAN_F25R1_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F25R1_FB1 CAN_F25R1_FB1_Msk /*!< Filter bit 1 */
+#define CAN_F25R1_FB2_Pos (2U)
+#define CAN_F25R1_FB2_Msk (0x1U << CAN_F25R1_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F25R1_FB2 CAN_F25R1_FB2_Msk /*!< Filter bit 2 */
+#define CAN_F25R1_FB3_Pos (3U)
+#define CAN_F25R1_FB3_Msk (0x1U << CAN_F25R1_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F25R1_FB3 CAN_F25R1_FB3_Msk /*!< Filter bit 3 */
+#define CAN_F25R1_FB4_Pos (4U)
+#define CAN_F25R1_FB4_Msk (0x1U << CAN_F25R1_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F25R1_FB4 CAN_F25R1_FB4_Msk /*!< Filter bit 4 */
+#define CAN_F25R1_FB5_Pos (5U)
+#define CAN_F25R1_FB5_Msk (0x1U << CAN_F25R1_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F25R1_FB5 CAN_F25R1_FB5_Msk /*!< Filter bit 5 */
+#define CAN_F25R1_FB6_Pos (6U)
+#define CAN_F25R1_FB6_Msk (0x1U << CAN_F25R1_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F25R1_FB6 CAN_F25R1_FB6_Msk /*!< Filter bit 6 */
+#define CAN_F25R1_FB7_Pos (7U)
+#define CAN_F25R1_FB7_Msk (0x1U << CAN_F25R1_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F25R1_FB7 CAN_F25R1_FB7_Msk /*!< Filter bit 7 */
+#define CAN_F25R1_FB8_Pos (8U)
+#define CAN_F25R1_FB8_Msk (0x1U << CAN_F25R1_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F25R1_FB8 CAN_F25R1_FB8_Msk /*!< Filter bit 8 */
+#define CAN_F25R1_FB9_Pos (9U)
+#define CAN_F25R1_FB9_Msk (0x1U << CAN_F25R1_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F25R1_FB9 CAN_F25R1_FB9_Msk /*!< Filter bit 9 */
+#define CAN_F25R1_FB10_Pos (10U)
+#define CAN_F25R1_FB10_Msk (0x1U << CAN_F25R1_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F25R1_FB10 CAN_F25R1_FB10_Msk /*!< Filter bit 10 */
+#define CAN_F25R1_FB11_Pos (11U)
+#define CAN_F25R1_FB11_Msk (0x1U << CAN_F25R1_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F25R1_FB11 CAN_F25R1_FB11_Msk /*!< Filter bit 11 */
+#define CAN_F25R1_FB12_Pos (12U)
+#define CAN_F25R1_FB12_Msk (0x1U << CAN_F25R1_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F25R1_FB12 CAN_F25R1_FB12_Msk /*!< Filter bit 12 */
+#define CAN_F25R1_FB13_Pos (13U)
+#define CAN_F25R1_FB13_Msk (0x1U << CAN_F25R1_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F25R1_FB13 CAN_F25R1_FB13_Msk /*!< Filter bit 13 */
+#define CAN_F25R1_FB14_Pos (14U)
+#define CAN_F25R1_FB14_Msk (0x1U << CAN_F25R1_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F25R1_FB14 CAN_F25R1_FB14_Msk /*!< Filter bit 14 */
+#define CAN_F25R1_FB15_Pos (15U)
+#define CAN_F25R1_FB15_Msk (0x1U << CAN_F25R1_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F25R1_FB15 CAN_F25R1_FB15_Msk /*!< Filter bit 15 */
+#define CAN_F25R1_FB16_Pos (16U)
+#define CAN_F25R1_FB16_Msk (0x1U << CAN_F25R1_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F25R1_FB16 CAN_F25R1_FB16_Msk /*!< Filter bit 16 */
+#define CAN_F25R1_FB17_Pos (17U)
+#define CAN_F25R1_FB17_Msk (0x1U << CAN_F25R1_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F25R1_FB17 CAN_F25R1_FB17_Msk /*!< Filter bit 17 */
+#define CAN_F25R1_FB18_Pos (18U)
+#define CAN_F25R1_FB18_Msk (0x1U << CAN_F25R1_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F25R1_FB18 CAN_F25R1_FB18_Msk /*!< Filter bit 18 */
+#define CAN_F25R1_FB19_Pos (19U)
+#define CAN_F25R1_FB19_Msk (0x1U << CAN_F25R1_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F25R1_FB19 CAN_F25R1_FB19_Msk /*!< Filter bit 19 */
+#define CAN_F25R1_FB20_Pos (20U)
+#define CAN_F25R1_FB20_Msk (0x1U << CAN_F25R1_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F25R1_FB20 CAN_F25R1_FB20_Msk /*!< Filter bit 20 */
+#define CAN_F25R1_FB21_Pos (21U)
+#define CAN_F25R1_FB21_Msk (0x1U << CAN_F25R1_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F25R1_FB21 CAN_F25R1_FB21_Msk /*!< Filter bit 21 */
+#define CAN_F25R1_FB22_Pos (22U)
+#define CAN_F25R1_FB22_Msk (0x1U << CAN_F25R1_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F25R1_FB22 CAN_F25R1_FB22_Msk /*!< Filter bit 22 */
+#define CAN_F25R1_FB23_Pos (23U)
+#define CAN_F25R1_FB23_Msk (0x1U << CAN_F25R1_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F25R1_FB23 CAN_F25R1_FB23_Msk /*!< Filter bit 23 */
+#define CAN_F25R1_FB24_Pos (24U)
+#define CAN_F25R1_FB24_Msk (0x1U << CAN_F25R1_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F25R1_FB24 CAN_F25R1_FB24_Msk /*!< Filter bit 24 */
+#define CAN_F25R1_FB25_Pos (25U)
+#define CAN_F25R1_FB25_Msk (0x1U << CAN_F25R1_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F25R1_FB25 CAN_F25R1_FB25_Msk /*!< Filter bit 25 */
+#define CAN_F25R1_FB26_Pos (26U)
+#define CAN_F25R1_FB26_Msk (0x1U << CAN_F25R1_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F25R1_FB26 CAN_F25R1_FB26_Msk /*!< Filter bit 26 */
+#define CAN_F25R1_FB27_Pos (27U)
+#define CAN_F25R1_FB27_Msk (0x1U << CAN_F25R1_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F25R1_FB27 CAN_F25R1_FB27_Msk /*!< Filter bit 27 */
+#define CAN_F25R1_FB28_Pos (28U)
+#define CAN_F25R1_FB28_Msk (0x1U << CAN_F25R1_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F25R1_FB28 CAN_F25R1_FB28_Msk /*!< Filter bit 28 */
+#define CAN_F25R1_FB29_Pos (29U)
+#define CAN_F25R1_FB29_Msk (0x1U << CAN_F25R1_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F25R1_FB29 CAN_F25R1_FB29_Msk /*!< Filter bit 29 */
+#define CAN_F25R1_FB30_Pos (30U)
+#define CAN_F25R1_FB30_Msk (0x1U << CAN_F25R1_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F25R1_FB30 CAN_F25R1_FB30_Msk /*!< Filter bit 30 */
+#define CAN_F25R1_FB31_Pos (31U)
+#define CAN_F25R1_FB31_Msk (0x1U << CAN_F25R1_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F25R1_FB31 CAN_F25R1_FB31_Msk /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F26R1 register ******************/
+#define CAN_F26R1_FB0_Pos (0U)
+#define CAN_F26R1_FB0_Msk (0x1U << CAN_F26R1_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F26R1_FB0 CAN_F26R1_FB0_Msk /*!< Filter bit 0 */
+#define CAN_F26R1_FB1_Pos (1U)
+#define CAN_F26R1_FB1_Msk (0x1U << CAN_F26R1_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F26R1_FB1 CAN_F26R1_FB1_Msk /*!< Filter bit 1 */
+#define CAN_F26R1_FB2_Pos (2U)
+#define CAN_F26R1_FB2_Msk (0x1U << CAN_F26R1_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F26R1_FB2 CAN_F26R1_FB2_Msk /*!< Filter bit 2 */
+#define CAN_F26R1_FB3_Pos (3U)
+#define CAN_F26R1_FB3_Msk (0x1U << CAN_F26R1_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F26R1_FB3 CAN_F26R1_FB3_Msk /*!< Filter bit 3 */
+#define CAN_F26R1_FB4_Pos (4U)
+#define CAN_F26R1_FB4_Msk (0x1U << CAN_F26R1_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F26R1_FB4 CAN_F26R1_FB4_Msk /*!< Filter bit 4 */
+#define CAN_F26R1_FB5_Pos (5U)
+#define CAN_F26R1_FB5_Msk (0x1U << CAN_F26R1_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F26R1_FB5 CAN_F26R1_FB5_Msk /*!< Filter bit 5 */
+#define CAN_F26R1_FB6_Pos (6U)
+#define CAN_F26R1_FB6_Msk (0x1U << CAN_F26R1_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F26R1_FB6 CAN_F26R1_FB6_Msk /*!< Filter bit 6 */
+#define CAN_F26R1_FB7_Pos (7U)
+#define CAN_F26R1_FB7_Msk (0x1U << CAN_F26R1_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F26R1_FB7 CAN_F26R1_FB7_Msk /*!< Filter bit 7 */
+#define CAN_F26R1_FB8_Pos (8U)
+#define CAN_F26R1_FB8_Msk (0x1U << CAN_F26R1_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F26R1_FB8 CAN_F26R1_FB8_Msk /*!< Filter bit 8 */
+#define CAN_F26R1_FB9_Pos (9U)
+#define CAN_F26R1_FB9_Msk (0x1U << CAN_F26R1_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F26R1_FB9 CAN_F26R1_FB9_Msk /*!< Filter bit 9 */
+#define CAN_F26R1_FB10_Pos (10U)
+#define CAN_F26R1_FB10_Msk (0x1U << CAN_F26R1_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F26R1_FB10 CAN_F26R1_FB10_Msk /*!< Filter bit 10 */
+#define CAN_F26R1_FB11_Pos (11U)
+#define CAN_F26R1_FB11_Msk (0x1U << CAN_F26R1_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F26R1_FB11 CAN_F26R1_FB11_Msk /*!< Filter bit 11 */
+#define CAN_F26R1_FB12_Pos (12U)
+#define CAN_F26R1_FB12_Msk (0x1U << CAN_F26R1_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F26R1_FB12 CAN_F26R1_FB12_Msk /*!< Filter bit 12 */
+#define CAN_F26R1_FB13_Pos (13U)
+#define CAN_F26R1_FB13_Msk (0x1U << CAN_F26R1_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F26R1_FB13 CAN_F26R1_FB13_Msk /*!< Filter bit 13 */
+#define CAN_F26R1_FB14_Pos (14U)
+#define CAN_F26R1_FB14_Msk (0x1U << CAN_F26R1_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F26R1_FB14 CAN_F26R1_FB14_Msk /*!< Filter bit 14 */
+#define CAN_F26R1_FB15_Pos (15U)
+#define CAN_F26R1_FB15_Msk (0x1U << CAN_F26R1_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F26R1_FB15 CAN_F26R1_FB15_Msk /*!< Filter bit 15 */
+#define CAN_F26R1_FB16_Pos (16U)
+#define CAN_F26R1_FB16_Msk (0x1U << CAN_F26R1_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F26R1_FB16 CAN_F26R1_FB16_Msk /*!< Filter bit 16 */
+#define CAN_F26R1_FB17_Pos (17U)
+#define CAN_F26R1_FB17_Msk (0x1U << CAN_F26R1_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F26R1_FB17 CAN_F26R1_FB17_Msk /*!< Filter bit 17 */
+#define CAN_F26R1_FB18_Pos (18U)
+#define CAN_F26R1_FB18_Msk (0x1U << CAN_F26R1_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F26R1_FB18 CAN_F26R1_FB18_Msk /*!< Filter bit 18 */
+#define CAN_F26R1_FB19_Pos (19U)
+#define CAN_F26R1_FB19_Msk (0x1U << CAN_F26R1_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F26R1_FB19 CAN_F26R1_FB19_Msk /*!< Filter bit 19 */
+#define CAN_F26R1_FB20_Pos (20U)
+#define CAN_F26R1_FB20_Msk (0x1U << CAN_F26R1_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F26R1_FB20 CAN_F26R1_FB20_Msk /*!< Filter bit 20 */
+#define CAN_F26R1_FB21_Pos (21U)
+#define CAN_F26R1_FB21_Msk (0x1U << CAN_F26R1_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F26R1_FB21 CAN_F26R1_FB21_Msk /*!< Filter bit 21 */
+#define CAN_F26R1_FB22_Pos (22U)
+#define CAN_F26R1_FB22_Msk (0x1U << CAN_F26R1_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F26R1_FB22 CAN_F26R1_FB22_Msk /*!< Filter bit 22 */
+#define CAN_F26R1_FB23_Pos (23U)
+#define CAN_F26R1_FB23_Msk (0x1U << CAN_F26R1_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F26R1_FB23 CAN_F26R1_FB23_Msk /*!< Filter bit 23 */
+#define CAN_F26R1_FB24_Pos (24U)
+#define CAN_F26R1_FB24_Msk (0x1U << CAN_F26R1_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F26R1_FB24 CAN_F26R1_FB24_Msk /*!< Filter bit 24 */
+#define CAN_F26R1_FB25_Pos (25U)
+#define CAN_F26R1_FB25_Msk (0x1U << CAN_F26R1_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F26R1_FB25 CAN_F26R1_FB25_Msk /*!< Filter bit 25 */
+#define CAN_F26R1_FB26_Pos (26U)
+#define CAN_F26R1_FB26_Msk (0x1U << CAN_F26R1_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F26R1_FB26 CAN_F26R1_FB26_Msk /*!< Filter bit 26 */
+#define CAN_F26R1_FB27_Pos (27U)
+#define CAN_F26R1_FB27_Msk (0x1U << CAN_F26R1_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F26R1_FB27 CAN_F26R1_FB27_Msk /*!< Filter bit 27 */
+#define CAN_F26R1_FB28_Pos (28U)
+#define CAN_F26R1_FB28_Msk (0x1U << CAN_F26R1_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F26R1_FB28 CAN_F26R1_FB28_Msk /*!< Filter bit 28 */
+#define CAN_F26R1_FB29_Pos (29U)
+#define CAN_F26R1_FB29_Msk (0x1U << CAN_F26R1_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F26R1_FB29 CAN_F26R1_FB29_Msk /*!< Filter bit 29 */
+#define CAN_F26R1_FB30_Pos (30U)
+#define CAN_F26R1_FB30_Msk (0x1U << CAN_F26R1_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F26R1_FB30 CAN_F26R1_FB30_Msk /*!< Filter bit 30 */
+#define CAN_F26R1_FB31_Pos (31U)
+#define CAN_F26R1_FB31_Msk (0x1U << CAN_F26R1_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F26R1_FB31 CAN_F26R1_FB31_Msk /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F27R1 register ******************/
+#define CAN_F27R1_FB0_Pos (0U)
+#define CAN_F27R1_FB0_Msk (0x1U << CAN_F27R1_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F27R1_FB0 CAN_F27R1_FB0_Msk /*!< Filter bit 0 */
+#define CAN_F27R1_FB1_Pos (1U)
+#define CAN_F27R1_FB1_Msk (0x1U << CAN_F27R1_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F27R1_FB1 CAN_F27R1_FB1_Msk /*!< Filter bit 1 */
+#define CAN_F27R1_FB2_Pos (2U)
+#define CAN_F27R1_FB2_Msk (0x1U << CAN_F27R1_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F27R1_FB2 CAN_F27R1_FB2_Msk /*!< Filter bit 2 */
+#define CAN_F27R1_FB3_Pos (3U)
+#define CAN_F27R1_FB3_Msk (0x1U << CAN_F27R1_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F27R1_FB3 CAN_F27R1_FB3_Msk /*!< Filter bit 3 */
+#define CAN_F27R1_FB4_Pos (4U)
+#define CAN_F27R1_FB4_Msk (0x1U << CAN_F27R1_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F27R1_FB4 CAN_F27R1_FB4_Msk /*!< Filter bit 4 */
+#define CAN_F27R1_FB5_Pos (5U)
+#define CAN_F27R1_FB5_Msk (0x1U << CAN_F27R1_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F27R1_FB5 CAN_F27R1_FB5_Msk /*!< Filter bit 5 */
+#define CAN_F27R1_FB6_Pos (6U)
+#define CAN_F27R1_FB6_Msk (0x1U << CAN_F27R1_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F27R1_FB6 CAN_F27R1_FB6_Msk /*!< Filter bit 6 */
+#define CAN_F27R1_FB7_Pos (7U)
+#define CAN_F27R1_FB7_Msk (0x1U << CAN_F27R1_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F27R1_FB7 CAN_F27R1_FB7_Msk /*!< Filter bit 7 */
+#define CAN_F27R1_FB8_Pos (8U)
+#define CAN_F27R1_FB8_Msk (0x1U << CAN_F27R1_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F27R1_FB8 CAN_F27R1_FB8_Msk /*!< Filter bit 8 */
+#define CAN_F27R1_FB9_Pos (9U)
+#define CAN_F27R1_FB9_Msk (0x1U << CAN_F27R1_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F27R1_FB9 CAN_F27R1_FB9_Msk /*!< Filter bit 9 */
+#define CAN_F27R1_FB10_Pos (10U)
+#define CAN_F27R1_FB10_Msk (0x1U << CAN_F27R1_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F27R1_FB10 CAN_F27R1_FB10_Msk /*!< Filter bit 10 */
+#define CAN_F27R1_FB11_Pos (11U)
+#define CAN_F27R1_FB11_Msk (0x1U << CAN_F27R1_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F27R1_FB11 CAN_F27R1_FB11_Msk /*!< Filter bit 11 */
+#define CAN_F27R1_FB12_Pos (12U)
+#define CAN_F27R1_FB12_Msk (0x1U << CAN_F27R1_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F27R1_FB12 CAN_F27R1_FB12_Msk /*!< Filter bit 12 */
+#define CAN_F27R1_FB13_Pos (13U)
+#define CAN_F27R1_FB13_Msk (0x1U << CAN_F27R1_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F27R1_FB13 CAN_F27R1_FB13_Msk /*!< Filter bit 13 */
+#define CAN_F27R1_FB14_Pos (14U)
+#define CAN_F27R1_FB14_Msk (0x1U << CAN_F27R1_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F27R1_FB14 CAN_F27R1_FB14_Msk /*!< Filter bit 14 */
+#define CAN_F27R1_FB15_Pos (15U)
+#define CAN_F27R1_FB15_Msk (0x1U << CAN_F27R1_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F27R1_FB15 CAN_F27R1_FB15_Msk /*!< Filter bit 15 */
+#define CAN_F27R1_FB16_Pos (16U)
+#define CAN_F27R1_FB16_Msk (0x1U << CAN_F27R1_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F27R1_FB16 CAN_F27R1_FB16_Msk /*!< Filter bit 16 */
+#define CAN_F27R1_FB17_Pos (17U)
+#define CAN_F27R1_FB17_Msk (0x1U << CAN_F27R1_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F27R1_FB17 CAN_F27R1_FB17_Msk /*!< Filter bit 17 */
+#define CAN_F27R1_FB18_Pos (18U)
+#define CAN_F27R1_FB18_Msk (0x1U << CAN_F27R1_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F27R1_FB18 CAN_F27R1_FB18_Msk /*!< Filter bit 18 */
+#define CAN_F27R1_FB19_Pos (19U)
+#define CAN_F27R1_FB19_Msk (0x1U << CAN_F27R1_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F27R1_FB19 CAN_F27R1_FB19_Msk /*!< Filter bit 19 */
+#define CAN_F27R1_FB20_Pos (20U)
+#define CAN_F27R1_FB20_Msk (0x1U << CAN_F27R1_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F27R1_FB20 CAN_F27R1_FB20_Msk /*!< Filter bit 20 */
+#define CAN_F27R1_FB21_Pos (21U)
+#define CAN_F27R1_FB21_Msk (0x1U << CAN_F27R1_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F27R1_FB21 CAN_F27R1_FB21_Msk /*!< Filter bit 21 */
+#define CAN_F27R1_FB22_Pos (22U)
+#define CAN_F27R1_FB22_Msk (0x1U << CAN_F27R1_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F27R1_FB22 CAN_F27R1_FB22_Msk /*!< Filter bit 22 */
+#define CAN_F27R1_FB23_Pos (23U)
+#define CAN_F27R1_FB23_Msk (0x1U << CAN_F27R1_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F27R1_FB23 CAN_F27R1_FB23_Msk /*!< Filter bit 23 */
+#define CAN_F27R1_FB24_Pos (24U)
+#define CAN_F27R1_FB24_Msk (0x1U << CAN_F27R1_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F27R1_FB24 CAN_F27R1_FB24_Msk /*!< Filter bit 24 */
+#define CAN_F27R1_FB25_Pos (25U)
+#define CAN_F27R1_FB25_Msk (0x1U << CAN_F27R1_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F27R1_FB25 CAN_F27R1_FB25_Msk /*!< Filter bit 25 */
+#define CAN_F27R1_FB26_Pos (26U)
+#define CAN_F27R1_FB26_Msk (0x1U << CAN_F27R1_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F27R1_FB26 CAN_F27R1_FB26_Msk /*!< Filter bit 26 */
+#define CAN_F27R1_FB27_Pos (27U)
+#define CAN_F27R1_FB27_Msk (0x1U << CAN_F27R1_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F27R1_FB27 CAN_F27R1_FB27_Msk /*!< Filter bit 27 */
+#define CAN_F27R1_FB28_Pos (28U)
+#define CAN_F27R1_FB28_Msk (0x1U << CAN_F27R1_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F27R1_FB28 CAN_F27R1_FB28_Msk /*!< Filter bit 28 */
+#define CAN_F27R1_FB29_Pos (29U)
+#define CAN_F27R1_FB29_Msk (0x1U << CAN_F27R1_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F27R1_FB29 CAN_F27R1_FB29_Msk /*!< Filter bit 29 */
+#define CAN_F27R1_FB30_Pos (30U)
+#define CAN_F27R1_FB30_Msk (0x1U << CAN_F27R1_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F27R1_FB30 CAN_F27R1_FB30_Msk /*!< Filter bit 30 */
+#define CAN_F27R1_FB31_Pos (31U)
+#define CAN_F27R1_FB31_Msk (0x1U << CAN_F27R1_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F27R1_FB31 CAN_F27R1_FB31_Msk /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F0R2 register *******************/
+#define CAN_F0R2_FB0_Pos (0U)
+#define CAN_F0R2_FB0_Msk (0x1U << CAN_F0R2_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F0R2_FB0 CAN_F0R2_FB0_Msk /*!< Filter bit 0 */
+#define CAN_F0R2_FB1_Pos (1U)
+#define CAN_F0R2_FB1_Msk (0x1U << CAN_F0R2_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F0R2_FB1 CAN_F0R2_FB1_Msk /*!< Filter bit 1 */
+#define CAN_F0R2_FB2_Pos (2U)
+#define CAN_F0R2_FB2_Msk (0x1U << CAN_F0R2_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F0R2_FB2 CAN_F0R2_FB2_Msk /*!< Filter bit 2 */
+#define CAN_F0R2_FB3_Pos (3U)
+#define CAN_F0R2_FB3_Msk (0x1U << CAN_F0R2_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F0R2_FB3 CAN_F0R2_FB3_Msk /*!< Filter bit 3 */
+#define CAN_F0R2_FB4_Pos (4U)
+#define CAN_F0R2_FB4_Msk (0x1U << CAN_F0R2_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F0R2_FB4 CAN_F0R2_FB4_Msk /*!< Filter bit 4 */
+#define CAN_F0R2_FB5_Pos (5U)
+#define CAN_F0R2_FB5_Msk (0x1U << CAN_F0R2_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F0R2_FB5 CAN_F0R2_FB5_Msk /*!< Filter bit 5 */
+#define CAN_F0R2_FB6_Pos (6U)
+#define CAN_F0R2_FB6_Msk (0x1U << CAN_F0R2_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F0R2_FB6 CAN_F0R2_FB6_Msk /*!< Filter bit 6 */
+#define CAN_F0R2_FB7_Pos (7U)
+#define CAN_F0R2_FB7_Msk (0x1U << CAN_F0R2_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F0R2_FB7 CAN_F0R2_FB7_Msk /*!< Filter bit 7 */
+#define CAN_F0R2_FB8_Pos (8U)
+#define CAN_F0R2_FB8_Msk (0x1U << CAN_F0R2_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F0R2_FB8 CAN_F0R2_FB8_Msk /*!< Filter bit 8 */
+#define CAN_F0R2_FB9_Pos (9U)
+#define CAN_F0R2_FB9_Msk (0x1U << CAN_F0R2_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F0R2_FB9 CAN_F0R2_FB9_Msk /*!< Filter bit 9 */
+#define CAN_F0R2_FB10_Pos (10U)
+#define CAN_F0R2_FB10_Msk (0x1U << CAN_F0R2_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F0R2_FB10 CAN_F0R2_FB10_Msk /*!< Filter bit 10 */
+#define CAN_F0R2_FB11_Pos (11U)
+#define CAN_F0R2_FB11_Msk (0x1U << CAN_F0R2_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F0R2_FB11 CAN_F0R2_FB11_Msk /*!< Filter bit 11 */
+#define CAN_F0R2_FB12_Pos (12U)
+#define CAN_F0R2_FB12_Msk (0x1U << CAN_F0R2_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F0R2_FB12 CAN_F0R2_FB12_Msk /*!< Filter bit 12 */
+#define CAN_F0R2_FB13_Pos (13U)
+#define CAN_F0R2_FB13_Msk (0x1U << CAN_F0R2_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F0R2_FB13 CAN_F0R2_FB13_Msk /*!< Filter bit 13 */
+#define CAN_F0R2_FB14_Pos (14U)
+#define CAN_F0R2_FB14_Msk (0x1U << CAN_F0R2_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F0R2_FB14 CAN_F0R2_FB14_Msk /*!< Filter bit 14 */
+#define CAN_F0R2_FB15_Pos (15U)
+#define CAN_F0R2_FB15_Msk (0x1U << CAN_F0R2_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F0R2_FB15 CAN_F0R2_FB15_Msk /*!< Filter bit 15 */
+#define CAN_F0R2_FB16_Pos (16U)
+#define CAN_F0R2_FB16_Msk (0x1U << CAN_F0R2_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F0R2_FB16 CAN_F0R2_FB16_Msk /*!< Filter bit 16 */
+#define CAN_F0R2_FB17_Pos (17U)
+#define CAN_F0R2_FB17_Msk (0x1U << CAN_F0R2_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F0R2_FB17 CAN_F0R2_FB17_Msk /*!< Filter bit 17 */
+#define CAN_F0R2_FB18_Pos (18U)
+#define CAN_F0R2_FB18_Msk (0x1U << CAN_F0R2_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F0R2_FB18 CAN_F0R2_FB18_Msk /*!< Filter bit 18 */
+#define CAN_F0R2_FB19_Pos (19U)
+#define CAN_F0R2_FB19_Msk (0x1U << CAN_F0R2_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F0R2_FB19 CAN_F0R2_FB19_Msk /*!< Filter bit 19 */
+#define CAN_F0R2_FB20_Pos (20U)
+#define CAN_F0R2_FB20_Msk (0x1U << CAN_F0R2_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F0R2_FB20 CAN_F0R2_FB20_Msk /*!< Filter bit 20 */
+#define CAN_F0R2_FB21_Pos (21U)
+#define CAN_F0R2_FB21_Msk (0x1U << CAN_F0R2_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F0R2_FB21 CAN_F0R2_FB21_Msk /*!< Filter bit 21 */
+#define CAN_F0R2_FB22_Pos (22U)
+#define CAN_F0R2_FB22_Msk (0x1U << CAN_F0R2_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F0R2_FB22 CAN_F0R2_FB22_Msk /*!< Filter bit 22 */
+#define CAN_F0R2_FB23_Pos (23U)
+#define CAN_F0R2_FB23_Msk (0x1U << CAN_F0R2_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F0R2_FB23 CAN_F0R2_FB23_Msk /*!< Filter bit 23 */
+#define CAN_F0R2_FB24_Pos (24U)
+#define CAN_F0R2_FB24_Msk (0x1U << CAN_F0R2_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F0R2_FB24 CAN_F0R2_FB24_Msk /*!< Filter bit 24 */
+#define CAN_F0R2_FB25_Pos (25U)
+#define CAN_F0R2_FB25_Msk (0x1U << CAN_F0R2_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F0R2_FB25 CAN_F0R2_FB25_Msk /*!< Filter bit 25 */
+#define CAN_F0R2_FB26_Pos (26U)
+#define CAN_F0R2_FB26_Msk (0x1U << CAN_F0R2_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F0R2_FB26 CAN_F0R2_FB26_Msk /*!< Filter bit 26 */
+#define CAN_F0R2_FB27_Pos (27U)
+#define CAN_F0R2_FB27_Msk (0x1U << CAN_F0R2_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F0R2_FB27 CAN_F0R2_FB27_Msk /*!< Filter bit 27 */
+#define CAN_F0R2_FB28_Pos (28U)
+#define CAN_F0R2_FB28_Msk (0x1U << CAN_F0R2_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F0R2_FB28 CAN_F0R2_FB28_Msk /*!< Filter bit 28 */
+#define CAN_F0R2_FB29_Pos (29U)
+#define CAN_F0R2_FB29_Msk (0x1U << CAN_F0R2_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F0R2_FB29 CAN_F0R2_FB29_Msk /*!< Filter bit 29 */
+#define CAN_F0R2_FB30_Pos (30U)
+#define CAN_F0R2_FB30_Msk (0x1U << CAN_F0R2_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F0R2_FB30 CAN_F0R2_FB30_Msk /*!< Filter bit 30 */
+#define CAN_F0R2_FB31_Pos (31U)
+#define CAN_F0R2_FB31_Msk (0x1U << CAN_F0R2_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F0R2_FB31 CAN_F0R2_FB31_Msk /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F1R2 register *******************/
+#define CAN_F1R2_FB0_Pos (0U)
+#define CAN_F1R2_FB0_Msk (0x1U << CAN_F1R2_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F1R2_FB0 CAN_F1R2_FB0_Msk /*!< Filter bit 0 */
+#define CAN_F1R2_FB1_Pos (1U)
+#define CAN_F1R2_FB1_Msk (0x1U << CAN_F1R2_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F1R2_FB1 CAN_F1R2_FB1_Msk /*!< Filter bit 1 */
+#define CAN_F1R2_FB2_Pos (2U)
+#define CAN_F1R2_FB2_Msk (0x1U << CAN_F1R2_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F1R2_FB2 CAN_F1R2_FB2_Msk /*!< Filter bit 2 */
+#define CAN_F1R2_FB3_Pos (3U)
+#define CAN_F1R2_FB3_Msk (0x1U << CAN_F1R2_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F1R2_FB3 CAN_F1R2_FB3_Msk /*!< Filter bit 3 */
+#define CAN_F1R2_FB4_Pos (4U)
+#define CAN_F1R2_FB4_Msk (0x1U << CAN_F1R2_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F1R2_FB4 CAN_F1R2_FB4_Msk /*!< Filter bit 4 */
+#define CAN_F1R2_FB5_Pos (5U)
+#define CAN_F1R2_FB5_Msk (0x1U << CAN_F1R2_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F1R2_FB5 CAN_F1R2_FB5_Msk /*!< Filter bit 5 */
+#define CAN_F1R2_FB6_Pos (6U)
+#define CAN_F1R2_FB6_Msk (0x1U << CAN_F1R2_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F1R2_FB6 CAN_F1R2_FB6_Msk /*!< Filter bit 6 */
+#define CAN_F1R2_FB7_Pos (7U)
+#define CAN_F1R2_FB7_Msk (0x1U << CAN_F1R2_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F1R2_FB7 CAN_F1R2_FB7_Msk /*!< Filter bit 7 */
+#define CAN_F1R2_FB8_Pos (8U)
+#define CAN_F1R2_FB8_Msk (0x1U << CAN_F1R2_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F1R2_FB8 CAN_F1R2_FB8_Msk /*!< Filter bit 8 */
+#define CAN_F1R2_FB9_Pos (9U)
+#define CAN_F1R2_FB9_Msk (0x1U << CAN_F1R2_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F1R2_FB9 CAN_F1R2_FB9_Msk /*!< Filter bit 9 */
+#define CAN_F1R2_FB10_Pos (10U)
+#define CAN_F1R2_FB10_Msk (0x1U << CAN_F1R2_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F1R2_FB10 CAN_F1R2_FB10_Msk /*!< Filter bit 10 */
+#define CAN_F1R2_FB11_Pos (11U)
+#define CAN_F1R2_FB11_Msk (0x1U << CAN_F1R2_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F1R2_FB11 CAN_F1R2_FB11_Msk /*!< Filter bit 11 */
+#define CAN_F1R2_FB12_Pos (12U)
+#define CAN_F1R2_FB12_Msk (0x1U << CAN_F1R2_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F1R2_FB12 CAN_F1R2_FB12_Msk /*!< Filter bit 12 */
+#define CAN_F1R2_FB13_Pos (13U)
+#define CAN_F1R2_FB13_Msk (0x1U << CAN_F1R2_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F1R2_FB13 CAN_F1R2_FB13_Msk /*!< Filter bit 13 */
+#define CAN_F1R2_FB14_Pos (14U)
+#define CAN_F1R2_FB14_Msk (0x1U << CAN_F1R2_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F1R2_FB14 CAN_F1R2_FB14_Msk /*!< Filter bit 14 */
+#define CAN_F1R2_FB15_Pos (15U)
+#define CAN_F1R2_FB15_Msk (0x1U << CAN_F1R2_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F1R2_FB15 CAN_F1R2_FB15_Msk /*!< Filter bit 15 */
+#define CAN_F1R2_FB16_Pos (16U)
+#define CAN_F1R2_FB16_Msk (0x1U << CAN_F1R2_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F1R2_FB16 CAN_F1R2_FB16_Msk /*!< Filter bit 16 */
+#define CAN_F1R2_FB17_Pos (17U)
+#define CAN_F1R2_FB17_Msk (0x1U << CAN_F1R2_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F1R2_FB17 CAN_F1R2_FB17_Msk /*!< Filter bit 17 */
+#define CAN_F1R2_FB18_Pos (18U)
+#define CAN_F1R2_FB18_Msk (0x1U << CAN_F1R2_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F1R2_FB18 CAN_F1R2_FB18_Msk /*!< Filter bit 18 */
+#define CAN_F1R2_FB19_Pos (19U)
+#define CAN_F1R2_FB19_Msk (0x1U << CAN_F1R2_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F1R2_FB19 CAN_F1R2_FB19_Msk /*!< Filter bit 19 */
+#define CAN_F1R2_FB20_Pos (20U)
+#define CAN_F1R2_FB20_Msk (0x1U << CAN_F1R2_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F1R2_FB20 CAN_F1R2_FB20_Msk /*!< Filter bit 20 */
+#define CAN_F1R2_FB21_Pos (21U)
+#define CAN_F1R2_FB21_Msk (0x1U << CAN_F1R2_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F1R2_FB21 CAN_F1R2_FB21_Msk /*!< Filter bit 21 */
+#define CAN_F1R2_FB22_Pos (22U)
+#define CAN_F1R2_FB22_Msk (0x1U << CAN_F1R2_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F1R2_FB22 CAN_F1R2_FB22_Msk /*!< Filter bit 22 */
+#define CAN_F1R2_FB23_Pos (23U)
+#define CAN_F1R2_FB23_Msk (0x1U << CAN_F1R2_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F1R2_FB23 CAN_F1R2_FB23_Msk /*!< Filter bit 23 */
+#define CAN_F1R2_FB24_Pos (24U)
+#define CAN_F1R2_FB24_Msk (0x1U << CAN_F1R2_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F1R2_FB24 CAN_F1R2_FB24_Msk /*!< Filter bit 24 */
+#define CAN_F1R2_FB25_Pos (25U)
+#define CAN_F1R2_FB25_Msk (0x1U << CAN_F1R2_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F1R2_FB25 CAN_F1R2_FB25_Msk /*!< Filter bit 25 */
+#define CAN_F1R2_FB26_Pos (26U)
+#define CAN_F1R2_FB26_Msk (0x1U << CAN_F1R2_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F1R2_FB26 CAN_F1R2_FB26_Msk /*!< Filter bit 26 */
+#define CAN_F1R2_FB27_Pos (27U)
+#define CAN_F1R2_FB27_Msk (0x1U << CAN_F1R2_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F1R2_FB27 CAN_F1R2_FB27_Msk /*!< Filter bit 27 */
+#define CAN_F1R2_FB28_Pos (28U)
+#define CAN_F1R2_FB28_Msk (0x1U << CAN_F1R2_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F1R2_FB28 CAN_F1R2_FB28_Msk /*!< Filter bit 28 */
+#define CAN_F1R2_FB29_Pos (29U)
+#define CAN_F1R2_FB29_Msk (0x1U << CAN_F1R2_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F1R2_FB29 CAN_F1R2_FB29_Msk /*!< Filter bit 29 */
+#define CAN_F1R2_FB30_Pos (30U)
+#define CAN_F1R2_FB30_Msk (0x1U << CAN_F1R2_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F1R2_FB30 CAN_F1R2_FB30_Msk /*!< Filter bit 30 */
+#define CAN_F1R2_FB31_Pos (31U)
+#define CAN_F1R2_FB31_Msk (0x1U << CAN_F1R2_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F1R2_FB31 CAN_F1R2_FB31_Msk /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F2R2 register *******************/
+#define CAN_F2R2_FB0_Pos (0U)
+#define CAN_F2R2_FB0_Msk (0x1U << CAN_F2R2_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F2R2_FB0 CAN_F2R2_FB0_Msk /*!< Filter bit 0 */
+#define CAN_F2R2_FB1_Pos (1U)
+#define CAN_F2R2_FB1_Msk (0x1U << CAN_F2R2_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F2R2_FB1 CAN_F2R2_FB1_Msk /*!< Filter bit 1 */
+#define CAN_F2R2_FB2_Pos (2U)
+#define CAN_F2R2_FB2_Msk (0x1U << CAN_F2R2_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F2R2_FB2 CAN_F2R2_FB2_Msk /*!< Filter bit 2 */
+#define CAN_F2R2_FB3_Pos (3U)
+#define CAN_F2R2_FB3_Msk (0x1U << CAN_F2R2_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F2R2_FB3 CAN_F2R2_FB3_Msk /*!< Filter bit 3 */
+#define CAN_F2R2_FB4_Pos (4U)
+#define CAN_F2R2_FB4_Msk (0x1U << CAN_F2R2_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F2R2_FB4 CAN_F2R2_FB4_Msk /*!< Filter bit 4 */
+#define CAN_F2R2_FB5_Pos (5U)
+#define CAN_F2R2_FB5_Msk (0x1U << CAN_F2R2_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F2R2_FB5 CAN_F2R2_FB5_Msk /*!< Filter bit 5 */
+#define CAN_F2R2_FB6_Pos (6U)
+#define CAN_F2R2_FB6_Msk (0x1U << CAN_F2R2_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F2R2_FB6 CAN_F2R2_FB6_Msk /*!< Filter bit 6 */
+#define CAN_F2R2_FB7_Pos (7U)
+#define CAN_F2R2_FB7_Msk (0x1U << CAN_F2R2_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F2R2_FB7 CAN_F2R2_FB7_Msk /*!< Filter bit 7 */
+#define CAN_F2R2_FB8_Pos (8U)
+#define CAN_F2R2_FB8_Msk (0x1U << CAN_F2R2_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F2R2_FB8 CAN_F2R2_FB8_Msk /*!< Filter bit 8 */
+#define CAN_F2R2_FB9_Pos (9U)
+#define CAN_F2R2_FB9_Msk (0x1U << CAN_F2R2_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F2R2_FB9 CAN_F2R2_FB9_Msk /*!< Filter bit 9 */
+#define CAN_F2R2_FB10_Pos (10U)
+#define CAN_F2R2_FB10_Msk (0x1U << CAN_F2R2_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F2R2_FB10 CAN_F2R2_FB10_Msk /*!< Filter bit 10 */
+#define CAN_F2R2_FB11_Pos (11U)
+#define CAN_F2R2_FB11_Msk (0x1U << CAN_F2R2_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F2R2_FB11 CAN_F2R2_FB11_Msk /*!< Filter bit 11 */
+#define CAN_F2R2_FB12_Pos (12U)
+#define CAN_F2R2_FB12_Msk (0x1U << CAN_F2R2_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F2R2_FB12 CAN_F2R2_FB12_Msk /*!< Filter bit 12 */
+#define CAN_F2R2_FB13_Pos (13U)
+#define CAN_F2R2_FB13_Msk (0x1U << CAN_F2R2_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F2R2_FB13 CAN_F2R2_FB13_Msk /*!< Filter bit 13 */
+#define CAN_F2R2_FB14_Pos (14U)
+#define CAN_F2R2_FB14_Msk (0x1U << CAN_F2R2_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F2R2_FB14 CAN_F2R2_FB14_Msk /*!< Filter bit 14 */
+#define CAN_F2R2_FB15_Pos (15U)
+#define CAN_F2R2_FB15_Msk (0x1U << CAN_F2R2_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F2R2_FB15 CAN_F2R2_FB15_Msk /*!< Filter bit 15 */
+#define CAN_F2R2_FB16_Pos (16U)
+#define CAN_F2R2_FB16_Msk (0x1U << CAN_F2R2_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F2R2_FB16 CAN_F2R2_FB16_Msk /*!< Filter bit 16 */
+#define CAN_F2R2_FB17_Pos (17U)
+#define CAN_F2R2_FB17_Msk (0x1U << CAN_F2R2_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F2R2_FB17 CAN_F2R2_FB17_Msk /*!< Filter bit 17 */
+#define CAN_F2R2_FB18_Pos (18U)
+#define CAN_F2R2_FB18_Msk (0x1U << CAN_F2R2_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F2R2_FB18 CAN_F2R2_FB18_Msk /*!< Filter bit 18 */
+#define CAN_F2R2_FB19_Pos (19U)
+#define CAN_F2R2_FB19_Msk (0x1U << CAN_F2R2_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F2R2_FB19 CAN_F2R2_FB19_Msk /*!< Filter bit 19 */
+#define CAN_F2R2_FB20_Pos (20U)
+#define CAN_F2R2_FB20_Msk (0x1U << CAN_F2R2_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F2R2_FB20 CAN_F2R2_FB20_Msk /*!< Filter bit 20 */
+#define CAN_F2R2_FB21_Pos (21U)
+#define CAN_F2R2_FB21_Msk (0x1U << CAN_F2R2_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F2R2_FB21 CAN_F2R2_FB21_Msk /*!< Filter bit 21 */
+#define CAN_F2R2_FB22_Pos (22U)
+#define CAN_F2R2_FB22_Msk (0x1U << CAN_F2R2_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F2R2_FB22 CAN_F2R2_FB22_Msk /*!< Filter bit 22 */
+#define CAN_F2R2_FB23_Pos (23U)
+#define CAN_F2R2_FB23_Msk (0x1U << CAN_F2R2_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F2R2_FB23 CAN_F2R2_FB23_Msk /*!< Filter bit 23 */
+#define CAN_F2R2_FB24_Pos (24U)
+#define CAN_F2R2_FB24_Msk (0x1U << CAN_F2R2_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F2R2_FB24 CAN_F2R2_FB24_Msk /*!< Filter bit 24 */
+#define CAN_F2R2_FB25_Pos (25U)
+#define CAN_F2R2_FB25_Msk (0x1U << CAN_F2R2_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F2R2_FB25 CAN_F2R2_FB25_Msk /*!< Filter bit 25 */
+#define CAN_F2R2_FB26_Pos (26U)
+#define CAN_F2R2_FB26_Msk (0x1U << CAN_F2R2_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F2R2_FB26 CAN_F2R2_FB26_Msk /*!< Filter bit 26 */
+#define CAN_F2R2_FB27_Pos (27U)
+#define CAN_F2R2_FB27_Msk (0x1U << CAN_F2R2_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F2R2_FB27 CAN_F2R2_FB27_Msk /*!< Filter bit 27 */
+#define CAN_F2R2_FB28_Pos (28U)
+#define CAN_F2R2_FB28_Msk (0x1U << CAN_F2R2_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F2R2_FB28 CAN_F2R2_FB28_Msk /*!< Filter bit 28 */
+#define CAN_F2R2_FB29_Pos (29U)
+#define CAN_F2R2_FB29_Msk (0x1U << CAN_F2R2_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F2R2_FB29 CAN_F2R2_FB29_Msk /*!< Filter bit 29 */
+#define CAN_F2R2_FB30_Pos (30U)
+#define CAN_F2R2_FB30_Msk (0x1U << CAN_F2R2_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F2R2_FB30 CAN_F2R2_FB30_Msk /*!< Filter bit 30 */
+#define CAN_F2R2_FB31_Pos (31U)
+#define CAN_F2R2_FB31_Msk (0x1U << CAN_F2R2_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F2R2_FB31 CAN_F2R2_FB31_Msk /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F3R2 register *******************/
+#define CAN_F3R2_FB0_Pos (0U)
+#define CAN_F3R2_FB0_Msk (0x1U << CAN_F3R2_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F3R2_FB0 CAN_F3R2_FB0_Msk /*!< Filter bit 0 */
+#define CAN_F3R2_FB1_Pos (1U)
+#define CAN_F3R2_FB1_Msk (0x1U << CAN_F3R2_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F3R2_FB1 CAN_F3R2_FB1_Msk /*!< Filter bit 1 */
+#define CAN_F3R2_FB2_Pos (2U)
+#define CAN_F3R2_FB2_Msk (0x1U << CAN_F3R2_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F3R2_FB2 CAN_F3R2_FB2_Msk /*!< Filter bit 2 */
+#define CAN_F3R2_FB3_Pos (3U)
+#define CAN_F3R2_FB3_Msk (0x1U << CAN_F3R2_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F3R2_FB3 CAN_F3R2_FB3_Msk /*!< Filter bit 3 */
+#define CAN_F3R2_FB4_Pos (4U)
+#define CAN_F3R2_FB4_Msk (0x1U << CAN_F3R2_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F3R2_FB4 CAN_F3R2_FB4_Msk /*!< Filter bit 4 */
+#define CAN_F3R2_FB5_Pos (5U)
+#define CAN_F3R2_FB5_Msk (0x1U << CAN_F3R2_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F3R2_FB5 CAN_F3R2_FB5_Msk /*!< Filter bit 5 */
+#define CAN_F3R2_FB6_Pos (6U)
+#define CAN_F3R2_FB6_Msk (0x1U << CAN_F3R2_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F3R2_FB6 CAN_F3R2_FB6_Msk /*!< Filter bit 6 */
+#define CAN_F3R2_FB7_Pos (7U)
+#define CAN_F3R2_FB7_Msk (0x1U << CAN_F3R2_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F3R2_FB7 CAN_F3R2_FB7_Msk /*!< Filter bit 7 */
+#define CAN_F3R2_FB8_Pos (8U)
+#define CAN_F3R2_FB8_Msk (0x1U << CAN_F3R2_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F3R2_FB8 CAN_F3R2_FB8_Msk /*!< Filter bit 8 */
+#define CAN_F3R2_FB9_Pos (9U)
+#define CAN_F3R2_FB9_Msk (0x1U << CAN_F3R2_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F3R2_FB9 CAN_F3R2_FB9_Msk /*!< Filter bit 9 */
+#define CAN_F3R2_FB10_Pos (10U)
+#define CAN_F3R2_FB10_Msk (0x1U << CAN_F3R2_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F3R2_FB10 CAN_F3R2_FB10_Msk /*!< Filter bit 10 */
+#define CAN_F3R2_FB11_Pos (11U)
+#define CAN_F3R2_FB11_Msk (0x1U << CAN_F3R2_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F3R2_FB11 CAN_F3R2_FB11_Msk /*!< Filter bit 11 */
+#define CAN_F3R2_FB12_Pos (12U)
+#define CAN_F3R2_FB12_Msk (0x1U << CAN_F3R2_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F3R2_FB12 CAN_F3R2_FB12_Msk /*!< Filter bit 12 */
+#define CAN_F3R2_FB13_Pos (13U)
+#define CAN_F3R2_FB13_Msk (0x1U << CAN_F3R2_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F3R2_FB13 CAN_F3R2_FB13_Msk /*!< Filter bit 13 */
+#define CAN_F3R2_FB14_Pos (14U)
+#define CAN_F3R2_FB14_Msk (0x1U << CAN_F3R2_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F3R2_FB14 CAN_F3R2_FB14_Msk /*!< Filter bit 14 */
+#define CAN_F3R2_FB15_Pos (15U)
+#define CAN_F3R2_FB15_Msk (0x1U << CAN_F3R2_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F3R2_FB15 CAN_F3R2_FB15_Msk /*!< Filter bit 15 */
+#define CAN_F3R2_FB16_Pos (16U)
+#define CAN_F3R2_FB16_Msk (0x1U << CAN_F3R2_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F3R2_FB16 CAN_F3R2_FB16_Msk /*!< Filter bit 16 */
+#define CAN_F3R2_FB17_Pos (17U)
+#define CAN_F3R2_FB17_Msk (0x1U << CAN_F3R2_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F3R2_FB17 CAN_F3R2_FB17_Msk /*!< Filter bit 17 */
+#define CAN_F3R2_FB18_Pos (18U)
+#define CAN_F3R2_FB18_Msk (0x1U << CAN_F3R2_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F3R2_FB18 CAN_F3R2_FB18_Msk /*!< Filter bit 18 */
+#define CAN_F3R2_FB19_Pos (19U)
+#define CAN_F3R2_FB19_Msk (0x1U << CAN_F3R2_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F3R2_FB19 CAN_F3R2_FB19_Msk /*!< Filter bit 19 */
+#define CAN_F3R2_FB20_Pos (20U)
+#define CAN_F3R2_FB20_Msk (0x1U << CAN_F3R2_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F3R2_FB20 CAN_F3R2_FB20_Msk /*!< Filter bit 20 */
+#define CAN_F3R2_FB21_Pos (21U)
+#define CAN_F3R2_FB21_Msk (0x1U << CAN_F3R2_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F3R2_FB21 CAN_F3R2_FB21_Msk /*!< Filter bit 21 */
+#define CAN_F3R2_FB22_Pos (22U)
+#define CAN_F3R2_FB22_Msk (0x1U << CAN_F3R2_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F3R2_FB22 CAN_F3R2_FB22_Msk /*!< Filter bit 22 */
+#define CAN_F3R2_FB23_Pos (23U)
+#define CAN_F3R2_FB23_Msk (0x1U << CAN_F3R2_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F3R2_FB23 CAN_F3R2_FB23_Msk /*!< Filter bit 23 */
+#define CAN_F3R2_FB24_Pos (24U)
+#define CAN_F3R2_FB24_Msk (0x1U << CAN_F3R2_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F3R2_FB24 CAN_F3R2_FB24_Msk /*!< Filter bit 24 */
+#define CAN_F3R2_FB25_Pos (25U)
+#define CAN_F3R2_FB25_Msk (0x1U << CAN_F3R2_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F3R2_FB25 CAN_F3R2_FB25_Msk /*!< Filter bit 25 */
+#define CAN_F3R2_FB26_Pos (26U)
+#define CAN_F3R2_FB26_Msk (0x1U << CAN_F3R2_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F3R2_FB26 CAN_F3R2_FB26_Msk /*!< Filter bit 26 */
+#define CAN_F3R2_FB27_Pos (27U)
+#define CAN_F3R2_FB27_Msk (0x1U << CAN_F3R2_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F3R2_FB27 CAN_F3R2_FB27_Msk /*!< Filter bit 27 */
+#define CAN_F3R2_FB28_Pos (28U)
+#define CAN_F3R2_FB28_Msk (0x1U << CAN_F3R2_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F3R2_FB28 CAN_F3R2_FB28_Msk /*!< Filter bit 28 */
+#define CAN_F3R2_FB29_Pos (29U)
+#define CAN_F3R2_FB29_Msk (0x1U << CAN_F3R2_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F3R2_FB29 CAN_F3R2_FB29_Msk /*!< Filter bit 29 */
+#define CAN_F3R2_FB30_Pos (30U)
+#define CAN_F3R2_FB30_Msk (0x1U << CAN_F3R2_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F3R2_FB30 CAN_F3R2_FB30_Msk /*!< Filter bit 30 */
+#define CAN_F3R2_FB31_Pos (31U)
+#define CAN_F3R2_FB31_Msk (0x1U << CAN_F3R2_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F3R2_FB31 CAN_F3R2_FB31_Msk /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F4R2 register *******************/
+#define CAN_F4R2_FB0_Pos (0U)
+#define CAN_F4R2_FB0_Msk (0x1U << CAN_F4R2_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F4R2_FB0 CAN_F4R2_FB0_Msk /*!< Filter bit 0 */
+#define CAN_F4R2_FB1_Pos (1U)
+#define CAN_F4R2_FB1_Msk (0x1U << CAN_F4R2_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F4R2_FB1 CAN_F4R2_FB1_Msk /*!< Filter bit 1 */
+#define CAN_F4R2_FB2_Pos (2U)
+#define CAN_F4R2_FB2_Msk (0x1U << CAN_F4R2_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F4R2_FB2 CAN_F4R2_FB2_Msk /*!< Filter bit 2 */
+#define CAN_F4R2_FB3_Pos (3U)
+#define CAN_F4R2_FB3_Msk (0x1U << CAN_F4R2_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F4R2_FB3 CAN_F4R2_FB3_Msk /*!< Filter bit 3 */
+#define CAN_F4R2_FB4_Pos (4U)
+#define CAN_F4R2_FB4_Msk (0x1U << CAN_F4R2_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F4R2_FB4 CAN_F4R2_FB4_Msk /*!< Filter bit 4 */
+#define CAN_F4R2_FB5_Pos (5U)
+#define CAN_F4R2_FB5_Msk (0x1U << CAN_F4R2_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F4R2_FB5 CAN_F4R2_FB5_Msk /*!< Filter bit 5 */
+#define CAN_F4R2_FB6_Pos (6U)
+#define CAN_F4R2_FB6_Msk (0x1U << CAN_F4R2_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F4R2_FB6 CAN_F4R2_FB6_Msk /*!< Filter bit 6 */
+#define CAN_F4R2_FB7_Pos (7U)
+#define CAN_F4R2_FB7_Msk (0x1U << CAN_F4R2_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F4R2_FB7 CAN_F4R2_FB7_Msk /*!< Filter bit 7 */
+#define CAN_F4R2_FB8_Pos (8U)
+#define CAN_F4R2_FB8_Msk (0x1U << CAN_F4R2_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F4R2_FB8 CAN_F4R2_FB8_Msk /*!< Filter bit 8 */
+#define CAN_F4R2_FB9_Pos (9U)
+#define CAN_F4R2_FB9_Msk (0x1U << CAN_F4R2_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F4R2_FB9 CAN_F4R2_FB9_Msk /*!< Filter bit 9 */
+#define CAN_F4R2_FB10_Pos (10U)
+#define CAN_F4R2_FB10_Msk (0x1U << CAN_F4R2_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F4R2_FB10 CAN_F4R2_FB10_Msk /*!< Filter bit 10 */
+#define CAN_F4R2_FB11_Pos (11U)
+#define CAN_F4R2_FB11_Msk (0x1U << CAN_F4R2_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F4R2_FB11 CAN_F4R2_FB11_Msk /*!< Filter bit 11 */
+#define CAN_F4R2_FB12_Pos (12U)
+#define CAN_F4R2_FB12_Msk (0x1U << CAN_F4R2_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F4R2_FB12 CAN_F4R2_FB12_Msk /*!< Filter bit 12 */
+#define CAN_F4R2_FB13_Pos (13U)
+#define CAN_F4R2_FB13_Msk (0x1U << CAN_F4R2_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F4R2_FB13 CAN_F4R2_FB13_Msk /*!< Filter bit 13 */
+#define CAN_F4R2_FB14_Pos (14U)
+#define CAN_F4R2_FB14_Msk (0x1U << CAN_F4R2_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F4R2_FB14 CAN_F4R2_FB14_Msk /*!< Filter bit 14 */
+#define CAN_F4R2_FB15_Pos (15U)
+#define CAN_F4R2_FB15_Msk (0x1U << CAN_F4R2_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F4R2_FB15 CAN_F4R2_FB15_Msk /*!< Filter bit 15 */
+#define CAN_F4R2_FB16_Pos (16U)
+#define CAN_F4R2_FB16_Msk (0x1U << CAN_F4R2_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F4R2_FB16 CAN_F4R2_FB16_Msk /*!< Filter bit 16 */
+#define CAN_F4R2_FB17_Pos (17U)
+#define CAN_F4R2_FB17_Msk (0x1U << CAN_F4R2_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F4R2_FB17 CAN_F4R2_FB17_Msk /*!< Filter bit 17 */
+#define CAN_F4R2_FB18_Pos (18U)
+#define CAN_F4R2_FB18_Msk (0x1U << CAN_F4R2_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F4R2_FB18 CAN_F4R2_FB18_Msk /*!< Filter bit 18 */
+#define CAN_F4R2_FB19_Pos (19U)
+#define CAN_F4R2_FB19_Msk (0x1U << CAN_F4R2_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F4R2_FB19 CAN_F4R2_FB19_Msk /*!< Filter bit 19 */
+#define CAN_F4R2_FB20_Pos (20U)
+#define CAN_F4R2_FB20_Msk (0x1U << CAN_F4R2_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F4R2_FB20 CAN_F4R2_FB20_Msk /*!< Filter bit 20 */
+#define CAN_F4R2_FB21_Pos (21U)
+#define CAN_F4R2_FB21_Msk (0x1U << CAN_F4R2_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F4R2_FB21 CAN_F4R2_FB21_Msk /*!< Filter bit 21 */
+#define CAN_F4R2_FB22_Pos (22U)
+#define CAN_F4R2_FB22_Msk (0x1U << CAN_F4R2_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F4R2_FB22 CAN_F4R2_FB22_Msk /*!< Filter bit 22 */
+#define CAN_F4R2_FB23_Pos (23U)
+#define CAN_F4R2_FB23_Msk (0x1U << CAN_F4R2_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F4R2_FB23 CAN_F4R2_FB23_Msk /*!< Filter bit 23 */
+#define CAN_F4R2_FB24_Pos (24U)
+#define CAN_F4R2_FB24_Msk (0x1U << CAN_F4R2_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F4R2_FB24 CAN_F4R2_FB24_Msk /*!< Filter bit 24 */
+#define CAN_F4R2_FB25_Pos (25U)
+#define CAN_F4R2_FB25_Msk (0x1U << CAN_F4R2_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F4R2_FB25 CAN_F4R2_FB25_Msk /*!< Filter bit 25 */
+#define CAN_F4R2_FB26_Pos (26U)
+#define CAN_F4R2_FB26_Msk (0x1U << CAN_F4R2_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F4R2_FB26 CAN_F4R2_FB26_Msk /*!< Filter bit 26 */
+#define CAN_F4R2_FB27_Pos (27U)
+#define CAN_F4R2_FB27_Msk (0x1U << CAN_F4R2_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F4R2_FB27 CAN_F4R2_FB27_Msk /*!< Filter bit 27 */
+#define CAN_F4R2_FB28_Pos (28U)
+#define CAN_F4R2_FB28_Msk (0x1U << CAN_F4R2_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F4R2_FB28 CAN_F4R2_FB28_Msk /*!< Filter bit 28 */
+#define CAN_F4R2_FB29_Pos (29U)
+#define CAN_F4R2_FB29_Msk (0x1U << CAN_F4R2_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F4R2_FB29 CAN_F4R2_FB29_Msk /*!< Filter bit 29 */
+#define CAN_F4R2_FB30_Pos (30U)
+#define CAN_F4R2_FB30_Msk (0x1U << CAN_F4R2_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F4R2_FB30 CAN_F4R2_FB30_Msk /*!< Filter bit 30 */
+#define CAN_F4R2_FB31_Pos (31U)
+#define CAN_F4R2_FB31_Msk (0x1U << CAN_F4R2_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F4R2_FB31 CAN_F4R2_FB31_Msk /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F5R2 register *******************/
+#define CAN_F5R2_FB0_Pos (0U)
+#define CAN_F5R2_FB0_Msk (0x1U << CAN_F5R2_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F5R2_FB0 CAN_F5R2_FB0_Msk /*!< Filter bit 0 */
+#define CAN_F5R2_FB1_Pos (1U)
+#define CAN_F5R2_FB1_Msk (0x1U << CAN_F5R2_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F5R2_FB1 CAN_F5R2_FB1_Msk /*!< Filter bit 1 */
+#define CAN_F5R2_FB2_Pos (2U)
+#define CAN_F5R2_FB2_Msk (0x1U << CAN_F5R2_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F5R2_FB2 CAN_F5R2_FB2_Msk /*!< Filter bit 2 */
+#define CAN_F5R2_FB3_Pos (3U)
+#define CAN_F5R2_FB3_Msk (0x1U << CAN_F5R2_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F5R2_FB3 CAN_F5R2_FB3_Msk /*!< Filter bit 3 */
+#define CAN_F5R2_FB4_Pos (4U)
+#define CAN_F5R2_FB4_Msk (0x1U << CAN_F5R2_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F5R2_FB4 CAN_F5R2_FB4_Msk /*!< Filter bit 4 */
+#define CAN_F5R2_FB5_Pos (5U)
+#define CAN_F5R2_FB5_Msk (0x1U << CAN_F5R2_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F5R2_FB5 CAN_F5R2_FB5_Msk /*!< Filter bit 5 */
+#define CAN_F5R2_FB6_Pos (6U)
+#define CAN_F5R2_FB6_Msk (0x1U << CAN_F5R2_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F5R2_FB6 CAN_F5R2_FB6_Msk /*!< Filter bit 6 */
+#define CAN_F5R2_FB7_Pos (7U)
+#define CAN_F5R2_FB7_Msk (0x1U << CAN_F5R2_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F5R2_FB7 CAN_F5R2_FB7_Msk /*!< Filter bit 7 */
+#define CAN_F5R2_FB8_Pos (8U)
+#define CAN_F5R2_FB8_Msk (0x1U << CAN_F5R2_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F5R2_FB8 CAN_F5R2_FB8_Msk /*!< Filter bit 8 */
+#define CAN_F5R2_FB9_Pos (9U)
+#define CAN_F5R2_FB9_Msk (0x1U << CAN_F5R2_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F5R2_FB9 CAN_F5R2_FB9_Msk /*!< Filter bit 9 */
+#define CAN_F5R2_FB10_Pos (10U)
+#define CAN_F5R2_FB10_Msk (0x1U << CAN_F5R2_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F5R2_FB10 CAN_F5R2_FB10_Msk /*!< Filter bit 10 */
+#define CAN_F5R2_FB11_Pos (11U)
+#define CAN_F5R2_FB11_Msk (0x1U << CAN_F5R2_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F5R2_FB11 CAN_F5R2_FB11_Msk /*!< Filter bit 11 */
+#define CAN_F5R2_FB12_Pos (12U)
+#define CAN_F5R2_FB12_Msk (0x1U << CAN_F5R2_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F5R2_FB12 CAN_F5R2_FB12_Msk /*!< Filter bit 12 */
+#define CAN_F5R2_FB13_Pos (13U)
+#define CAN_F5R2_FB13_Msk (0x1U << CAN_F5R2_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F5R2_FB13 CAN_F5R2_FB13_Msk /*!< Filter bit 13 */
+#define CAN_F5R2_FB14_Pos (14U)
+#define CAN_F5R2_FB14_Msk (0x1U << CAN_F5R2_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F5R2_FB14 CAN_F5R2_FB14_Msk /*!< Filter bit 14 */
+#define CAN_F5R2_FB15_Pos (15U)
+#define CAN_F5R2_FB15_Msk (0x1U << CAN_F5R2_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F5R2_FB15 CAN_F5R2_FB15_Msk /*!< Filter bit 15 */
+#define CAN_F5R2_FB16_Pos (16U)
+#define CAN_F5R2_FB16_Msk (0x1U << CAN_F5R2_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F5R2_FB16 CAN_F5R2_FB16_Msk /*!< Filter bit 16 */
+#define CAN_F5R2_FB17_Pos (17U)
+#define CAN_F5R2_FB17_Msk (0x1U << CAN_F5R2_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F5R2_FB17 CAN_F5R2_FB17_Msk /*!< Filter bit 17 */
+#define CAN_F5R2_FB18_Pos (18U)
+#define CAN_F5R2_FB18_Msk (0x1U << CAN_F5R2_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F5R2_FB18 CAN_F5R2_FB18_Msk /*!< Filter bit 18 */
+#define CAN_F5R2_FB19_Pos (19U)
+#define CAN_F5R2_FB19_Msk (0x1U << CAN_F5R2_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F5R2_FB19 CAN_F5R2_FB19_Msk /*!< Filter bit 19 */
+#define CAN_F5R2_FB20_Pos (20U)
+#define CAN_F5R2_FB20_Msk (0x1U << CAN_F5R2_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F5R2_FB20 CAN_F5R2_FB20_Msk /*!< Filter bit 20 */
+#define CAN_F5R2_FB21_Pos (21U)
+#define CAN_F5R2_FB21_Msk (0x1U << CAN_F5R2_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F5R2_FB21 CAN_F5R2_FB21_Msk /*!< Filter bit 21 */
+#define CAN_F5R2_FB22_Pos (22U)
+#define CAN_F5R2_FB22_Msk (0x1U << CAN_F5R2_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F5R2_FB22 CAN_F5R2_FB22_Msk /*!< Filter bit 22 */
+#define CAN_F5R2_FB23_Pos (23U)
+#define CAN_F5R2_FB23_Msk (0x1U << CAN_F5R2_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F5R2_FB23 CAN_F5R2_FB23_Msk /*!< Filter bit 23 */
+#define CAN_F5R2_FB24_Pos (24U)
+#define CAN_F5R2_FB24_Msk (0x1U << CAN_F5R2_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F5R2_FB24 CAN_F5R2_FB24_Msk /*!< Filter bit 24 */
+#define CAN_F5R2_FB25_Pos (25U)
+#define CAN_F5R2_FB25_Msk (0x1U << CAN_F5R2_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F5R2_FB25 CAN_F5R2_FB25_Msk /*!< Filter bit 25 */
+#define CAN_F5R2_FB26_Pos (26U)
+#define CAN_F5R2_FB26_Msk (0x1U << CAN_F5R2_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F5R2_FB26 CAN_F5R2_FB26_Msk /*!< Filter bit 26 */
+#define CAN_F5R2_FB27_Pos (27U)
+#define CAN_F5R2_FB27_Msk (0x1U << CAN_F5R2_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F5R2_FB27 CAN_F5R2_FB27_Msk /*!< Filter bit 27 */
+#define CAN_F5R2_FB28_Pos (28U)
+#define CAN_F5R2_FB28_Msk (0x1U << CAN_F5R2_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F5R2_FB28 CAN_F5R2_FB28_Msk /*!< Filter bit 28 */
+#define CAN_F5R2_FB29_Pos (29U)
+#define CAN_F5R2_FB29_Msk (0x1U << CAN_F5R2_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F5R2_FB29 CAN_F5R2_FB29_Msk /*!< Filter bit 29 */
+#define CAN_F5R2_FB30_Pos (30U)
+#define CAN_F5R2_FB30_Msk (0x1U << CAN_F5R2_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F5R2_FB30 CAN_F5R2_FB30_Msk /*!< Filter bit 30 */
+#define CAN_F5R2_FB31_Pos (31U)
+#define CAN_F5R2_FB31_Msk (0x1U << CAN_F5R2_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F5R2_FB31 CAN_F5R2_FB31_Msk /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F6R2 register *******************/
+#define CAN_F6R2_FB0_Pos (0U)
+#define CAN_F6R2_FB0_Msk (0x1U << CAN_F6R2_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F6R2_FB0 CAN_F6R2_FB0_Msk /*!< Filter bit 0 */
+#define CAN_F6R2_FB1_Pos (1U)
+#define CAN_F6R2_FB1_Msk (0x1U << CAN_F6R2_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F6R2_FB1 CAN_F6R2_FB1_Msk /*!< Filter bit 1 */
+#define CAN_F6R2_FB2_Pos (2U)
+#define CAN_F6R2_FB2_Msk (0x1U << CAN_F6R2_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F6R2_FB2 CAN_F6R2_FB2_Msk /*!< Filter bit 2 */
+#define CAN_F6R2_FB3_Pos (3U)
+#define CAN_F6R2_FB3_Msk (0x1U << CAN_F6R2_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F6R2_FB3 CAN_F6R2_FB3_Msk /*!< Filter bit 3 */
+#define CAN_F6R2_FB4_Pos (4U)
+#define CAN_F6R2_FB4_Msk (0x1U << CAN_F6R2_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F6R2_FB4 CAN_F6R2_FB4_Msk /*!< Filter bit 4 */
+#define CAN_F6R2_FB5_Pos (5U)
+#define CAN_F6R2_FB5_Msk (0x1U << CAN_F6R2_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F6R2_FB5 CAN_F6R2_FB5_Msk /*!< Filter bit 5 */
+#define CAN_F6R2_FB6_Pos (6U)
+#define CAN_F6R2_FB6_Msk (0x1U << CAN_F6R2_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F6R2_FB6 CAN_F6R2_FB6_Msk /*!< Filter bit 6 */
+#define CAN_F6R2_FB7_Pos (7U)
+#define CAN_F6R2_FB7_Msk (0x1U << CAN_F6R2_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F6R2_FB7 CAN_F6R2_FB7_Msk /*!< Filter bit 7 */
+#define CAN_F6R2_FB8_Pos (8U)
+#define CAN_F6R2_FB8_Msk (0x1U << CAN_F6R2_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F6R2_FB8 CAN_F6R2_FB8_Msk /*!< Filter bit 8 */
+#define CAN_F6R2_FB9_Pos (9U)
+#define CAN_F6R2_FB9_Msk (0x1U << CAN_F6R2_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F6R2_FB9 CAN_F6R2_FB9_Msk /*!< Filter bit 9 */
+#define CAN_F6R2_FB10_Pos (10U)
+#define CAN_F6R2_FB10_Msk (0x1U << CAN_F6R2_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F6R2_FB10 CAN_F6R2_FB10_Msk /*!< Filter bit 10 */
+#define CAN_F6R2_FB11_Pos (11U)
+#define CAN_F6R2_FB11_Msk (0x1U << CAN_F6R2_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F6R2_FB11 CAN_F6R2_FB11_Msk /*!< Filter bit 11 */
+#define CAN_F6R2_FB12_Pos (12U)
+#define CAN_F6R2_FB12_Msk (0x1U << CAN_F6R2_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F6R2_FB12 CAN_F6R2_FB12_Msk /*!< Filter bit 12 */
+#define CAN_F6R2_FB13_Pos (13U)
+#define CAN_F6R2_FB13_Msk (0x1U << CAN_F6R2_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F6R2_FB13 CAN_F6R2_FB13_Msk /*!< Filter bit 13 */
+#define CAN_F6R2_FB14_Pos (14U)
+#define CAN_F6R2_FB14_Msk (0x1U << CAN_F6R2_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F6R2_FB14 CAN_F6R2_FB14_Msk /*!< Filter bit 14 */
+#define CAN_F6R2_FB15_Pos (15U)
+#define CAN_F6R2_FB15_Msk (0x1U << CAN_F6R2_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F6R2_FB15 CAN_F6R2_FB15_Msk /*!< Filter bit 15 */
+#define CAN_F6R2_FB16_Pos (16U)
+#define CAN_F6R2_FB16_Msk (0x1U << CAN_F6R2_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F6R2_FB16 CAN_F6R2_FB16_Msk /*!< Filter bit 16 */
+#define CAN_F6R2_FB17_Pos (17U)
+#define CAN_F6R2_FB17_Msk (0x1U << CAN_F6R2_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F6R2_FB17 CAN_F6R2_FB17_Msk /*!< Filter bit 17 */
+#define CAN_F6R2_FB18_Pos (18U)
+#define CAN_F6R2_FB18_Msk (0x1U << CAN_F6R2_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F6R2_FB18 CAN_F6R2_FB18_Msk /*!< Filter bit 18 */
+#define CAN_F6R2_FB19_Pos (19U)
+#define CAN_F6R2_FB19_Msk (0x1U << CAN_F6R2_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F6R2_FB19 CAN_F6R2_FB19_Msk /*!< Filter bit 19 */
+#define CAN_F6R2_FB20_Pos (20U)
+#define CAN_F6R2_FB20_Msk (0x1U << CAN_F6R2_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F6R2_FB20 CAN_F6R2_FB20_Msk /*!< Filter bit 20 */
+#define CAN_F6R2_FB21_Pos (21U)
+#define CAN_F6R2_FB21_Msk (0x1U << CAN_F6R2_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F6R2_FB21 CAN_F6R2_FB21_Msk /*!< Filter bit 21 */
+#define CAN_F6R2_FB22_Pos (22U)
+#define CAN_F6R2_FB22_Msk (0x1U << CAN_F6R2_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F6R2_FB22 CAN_F6R2_FB22_Msk /*!< Filter bit 22 */
+#define CAN_F6R2_FB23_Pos (23U)
+#define CAN_F6R2_FB23_Msk (0x1U << CAN_F6R2_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F6R2_FB23 CAN_F6R2_FB23_Msk /*!< Filter bit 23 */
+#define CAN_F6R2_FB24_Pos (24U)
+#define CAN_F6R2_FB24_Msk (0x1U << CAN_F6R2_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F6R2_FB24 CAN_F6R2_FB24_Msk /*!< Filter bit 24 */
+#define CAN_F6R2_FB25_Pos (25U)
+#define CAN_F6R2_FB25_Msk (0x1U << CAN_F6R2_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F6R2_FB25 CAN_F6R2_FB25_Msk /*!< Filter bit 25 */
+#define CAN_F6R2_FB26_Pos (26U)
+#define CAN_F6R2_FB26_Msk (0x1U << CAN_F6R2_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F6R2_FB26 CAN_F6R2_FB26_Msk /*!< Filter bit 26 */
+#define CAN_F6R2_FB27_Pos (27U)
+#define CAN_F6R2_FB27_Msk (0x1U << CAN_F6R2_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F6R2_FB27 CAN_F6R2_FB27_Msk /*!< Filter bit 27 */
+#define CAN_F6R2_FB28_Pos (28U)
+#define CAN_F6R2_FB28_Msk (0x1U << CAN_F6R2_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F6R2_FB28 CAN_F6R2_FB28_Msk /*!< Filter bit 28 */
+#define CAN_F6R2_FB29_Pos (29U)
+#define CAN_F6R2_FB29_Msk (0x1U << CAN_F6R2_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F6R2_FB29 CAN_F6R2_FB29_Msk /*!< Filter bit 29 */
+#define CAN_F6R2_FB30_Pos (30U)
+#define CAN_F6R2_FB30_Msk (0x1U << CAN_F6R2_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F6R2_FB30 CAN_F6R2_FB30_Msk /*!< Filter bit 30 */
+#define CAN_F6R2_FB31_Pos (31U)
+#define CAN_F6R2_FB31_Msk (0x1U << CAN_F6R2_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F6R2_FB31 CAN_F6R2_FB31_Msk /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F7R2 register *******************/
+#define CAN_F7R2_FB0_Pos (0U)
+#define CAN_F7R2_FB0_Msk (0x1U << CAN_F7R2_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F7R2_FB0 CAN_F7R2_FB0_Msk /*!< Filter bit 0 */
+#define CAN_F7R2_FB1_Pos (1U)
+#define CAN_F7R2_FB1_Msk (0x1U << CAN_F7R2_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F7R2_FB1 CAN_F7R2_FB1_Msk /*!< Filter bit 1 */
+#define CAN_F7R2_FB2_Pos (2U)
+#define CAN_F7R2_FB2_Msk (0x1U << CAN_F7R2_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F7R2_FB2 CAN_F7R2_FB2_Msk /*!< Filter bit 2 */
+#define CAN_F7R2_FB3_Pos (3U)
+#define CAN_F7R2_FB3_Msk (0x1U << CAN_F7R2_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F7R2_FB3 CAN_F7R2_FB3_Msk /*!< Filter bit 3 */
+#define CAN_F7R2_FB4_Pos (4U)
+#define CAN_F7R2_FB4_Msk (0x1U << CAN_F7R2_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F7R2_FB4 CAN_F7R2_FB4_Msk /*!< Filter bit 4 */
+#define CAN_F7R2_FB5_Pos (5U)
+#define CAN_F7R2_FB5_Msk (0x1U << CAN_F7R2_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F7R2_FB5 CAN_F7R2_FB5_Msk /*!< Filter bit 5 */
+#define CAN_F7R2_FB6_Pos (6U)
+#define CAN_F7R2_FB6_Msk (0x1U << CAN_F7R2_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F7R2_FB6 CAN_F7R2_FB6_Msk /*!< Filter bit 6 */
+#define CAN_F7R2_FB7_Pos (7U)
+#define CAN_F7R2_FB7_Msk (0x1U << CAN_F7R2_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F7R2_FB7 CAN_F7R2_FB7_Msk /*!< Filter bit 7 */
+#define CAN_F7R2_FB8_Pos (8U)
+#define CAN_F7R2_FB8_Msk (0x1U << CAN_F7R2_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F7R2_FB8 CAN_F7R2_FB8_Msk /*!< Filter bit 8 */
+#define CAN_F7R2_FB9_Pos (9U)
+#define CAN_F7R2_FB9_Msk (0x1U << CAN_F7R2_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F7R2_FB9 CAN_F7R2_FB9_Msk /*!< Filter bit 9 */
+#define CAN_F7R2_FB10_Pos (10U)
+#define CAN_F7R2_FB10_Msk (0x1U << CAN_F7R2_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F7R2_FB10 CAN_F7R2_FB10_Msk /*!< Filter bit 10 */
+#define CAN_F7R2_FB11_Pos (11U)
+#define CAN_F7R2_FB11_Msk (0x1U << CAN_F7R2_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F7R2_FB11 CAN_F7R2_FB11_Msk /*!< Filter bit 11 */
+#define CAN_F7R2_FB12_Pos (12U)
+#define CAN_F7R2_FB12_Msk (0x1U << CAN_F7R2_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F7R2_FB12 CAN_F7R2_FB12_Msk /*!< Filter bit 12 */
+#define CAN_F7R2_FB13_Pos (13U)
+#define CAN_F7R2_FB13_Msk (0x1U << CAN_F7R2_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F7R2_FB13 CAN_F7R2_FB13_Msk /*!< Filter bit 13 */
+#define CAN_F7R2_FB14_Pos (14U)
+#define CAN_F7R2_FB14_Msk (0x1U << CAN_F7R2_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F7R2_FB14 CAN_F7R2_FB14_Msk /*!< Filter bit 14 */
+#define CAN_F7R2_FB15_Pos (15U)
+#define CAN_F7R2_FB15_Msk (0x1U << CAN_F7R2_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F7R2_FB15 CAN_F7R2_FB15_Msk /*!< Filter bit 15 */
+#define CAN_F7R2_FB16_Pos (16U)
+#define CAN_F7R2_FB16_Msk (0x1U << CAN_F7R2_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F7R2_FB16 CAN_F7R2_FB16_Msk /*!< Filter bit 16 */
+#define CAN_F7R2_FB17_Pos (17U)
+#define CAN_F7R2_FB17_Msk (0x1U << CAN_F7R2_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F7R2_FB17 CAN_F7R2_FB17_Msk /*!< Filter bit 17 */
+#define CAN_F7R2_FB18_Pos (18U)
+#define CAN_F7R2_FB18_Msk (0x1U << CAN_F7R2_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F7R2_FB18 CAN_F7R2_FB18_Msk /*!< Filter bit 18 */
+#define CAN_F7R2_FB19_Pos (19U)
+#define CAN_F7R2_FB19_Msk (0x1U << CAN_F7R2_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F7R2_FB19 CAN_F7R2_FB19_Msk /*!< Filter bit 19 */
+#define CAN_F7R2_FB20_Pos (20U)
+#define CAN_F7R2_FB20_Msk (0x1U << CAN_F7R2_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F7R2_FB20 CAN_F7R2_FB20_Msk /*!< Filter bit 20 */
+#define CAN_F7R2_FB21_Pos (21U)
+#define CAN_F7R2_FB21_Msk (0x1U << CAN_F7R2_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F7R2_FB21 CAN_F7R2_FB21_Msk /*!< Filter bit 21 */
+#define CAN_F7R2_FB22_Pos (22U)
+#define CAN_F7R2_FB22_Msk (0x1U << CAN_F7R2_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F7R2_FB22 CAN_F7R2_FB22_Msk /*!< Filter bit 22 */
+#define CAN_F7R2_FB23_Pos (23U)
+#define CAN_F7R2_FB23_Msk (0x1U << CAN_F7R2_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F7R2_FB23 CAN_F7R2_FB23_Msk /*!< Filter bit 23 */
+#define CAN_F7R2_FB24_Pos (24U)
+#define CAN_F7R2_FB24_Msk (0x1U << CAN_F7R2_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F7R2_FB24 CAN_F7R2_FB24_Msk /*!< Filter bit 24 */
+#define CAN_F7R2_FB25_Pos (25U)
+#define CAN_F7R2_FB25_Msk (0x1U << CAN_F7R2_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F7R2_FB25 CAN_F7R2_FB25_Msk /*!< Filter bit 25 */
+#define CAN_F7R2_FB26_Pos (26U)
+#define CAN_F7R2_FB26_Msk (0x1U << CAN_F7R2_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F7R2_FB26 CAN_F7R2_FB26_Msk /*!< Filter bit 26 */
+#define CAN_F7R2_FB27_Pos (27U)
+#define CAN_F7R2_FB27_Msk (0x1U << CAN_F7R2_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F7R2_FB27 CAN_F7R2_FB27_Msk /*!< Filter bit 27 */
+#define CAN_F7R2_FB28_Pos (28U)
+#define CAN_F7R2_FB28_Msk (0x1U << CAN_F7R2_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F7R2_FB28 CAN_F7R2_FB28_Msk /*!< Filter bit 28 */
+#define CAN_F7R2_FB29_Pos (29U)
+#define CAN_F7R2_FB29_Msk (0x1U << CAN_F7R2_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F7R2_FB29 CAN_F7R2_FB29_Msk /*!< Filter bit 29 */
+#define CAN_F7R2_FB30_Pos (30U)
+#define CAN_F7R2_FB30_Msk (0x1U << CAN_F7R2_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F7R2_FB30 CAN_F7R2_FB30_Msk /*!< Filter bit 30 */
+#define CAN_F7R2_FB31_Pos (31U)
+#define CAN_F7R2_FB31_Msk (0x1U << CAN_F7R2_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F7R2_FB31 CAN_F7R2_FB31_Msk /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F8R2 register *******************/
+#define CAN_F8R2_FB0_Pos (0U)
+#define CAN_F8R2_FB0_Msk (0x1U << CAN_F8R2_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F8R2_FB0 CAN_F8R2_FB0_Msk /*!< Filter bit 0 */
+#define CAN_F8R2_FB1_Pos (1U)
+#define CAN_F8R2_FB1_Msk (0x1U << CAN_F8R2_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F8R2_FB1 CAN_F8R2_FB1_Msk /*!< Filter bit 1 */
+#define CAN_F8R2_FB2_Pos (2U)
+#define CAN_F8R2_FB2_Msk (0x1U << CAN_F8R2_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F8R2_FB2 CAN_F8R2_FB2_Msk /*!< Filter bit 2 */
+#define CAN_F8R2_FB3_Pos (3U)
+#define CAN_F8R2_FB3_Msk (0x1U << CAN_F8R2_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F8R2_FB3 CAN_F8R2_FB3_Msk /*!< Filter bit 3 */
+#define CAN_F8R2_FB4_Pos (4U)
+#define CAN_F8R2_FB4_Msk (0x1U << CAN_F8R2_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F8R2_FB4 CAN_F8R2_FB4_Msk /*!< Filter bit 4 */
+#define CAN_F8R2_FB5_Pos (5U)
+#define CAN_F8R2_FB5_Msk (0x1U << CAN_F8R2_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F8R2_FB5 CAN_F8R2_FB5_Msk /*!< Filter bit 5 */
+#define CAN_F8R2_FB6_Pos (6U)
+#define CAN_F8R2_FB6_Msk (0x1U << CAN_F8R2_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F8R2_FB6 CAN_F8R2_FB6_Msk /*!< Filter bit 6 */
+#define CAN_F8R2_FB7_Pos (7U)
+#define CAN_F8R2_FB7_Msk (0x1U << CAN_F8R2_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F8R2_FB7 CAN_F8R2_FB7_Msk /*!< Filter bit 7 */
+#define CAN_F8R2_FB8_Pos (8U)
+#define CAN_F8R2_FB8_Msk (0x1U << CAN_F8R2_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F8R2_FB8 CAN_F8R2_FB8_Msk /*!< Filter bit 8 */
+#define CAN_F8R2_FB9_Pos (9U)
+#define CAN_F8R2_FB9_Msk (0x1U << CAN_F8R2_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F8R2_FB9 CAN_F8R2_FB9_Msk /*!< Filter bit 9 */
+#define CAN_F8R2_FB10_Pos (10U)
+#define CAN_F8R2_FB10_Msk (0x1U << CAN_F8R2_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F8R2_FB10 CAN_F8R2_FB10_Msk /*!< Filter bit 10 */
+#define CAN_F8R2_FB11_Pos (11U)
+#define CAN_F8R2_FB11_Msk (0x1U << CAN_F8R2_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F8R2_FB11 CAN_F8R2_FB11_Msk /*!< Filter bit 11 */
+#define CAN_F8R2_FB12_Pos (12U)
+#define CAN_F8R2_FB12_Msk (0x1U << CAN_F8R2_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F8R2_FB12 CAN_F8R2_FB12_Msk /*!< Filter bit 12 */
+#define CAN_F8R2_FB13_Pos (13U)
+#define CAN_F8R2_FB13_Msk (0x1U << CAN_F8R2_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F8R2_FB13 CAN_F8R2_FB13_Msk /*!< Filter bit 13 */
+#define CAN_F8R2_FB14_Pos (14U)
+#define CAN_F8R2_FB14_Msk (0x1U << CAN_F8R2_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F8R2_FB14 CAN_F8R2_FB14_Msk /*!< Filter bit 14 */
+#define CAN_F8R2_FB15_Pos (15U)
+#define CAN_F8R2_FB15_Msk (0x1U << CAN_F8R2_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F8R2_FB15 CAN_F8R2_FB15_Msk /*!< Filter bit 15 */
+#define CAN_F8R2_FB16_Pos (16U)
+#define CAN_F8R2_FB16_Msk (0x1U << CAN_F8R2_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F8R2_FB16 CAN_F8R2_FB16_Msk /*!< Filter bit 16 */
+#define CAN_F8R2_FB17_Pos (17U)
+#define CAN_F8R2_FB17_Msk (0x1U << CAN_F8R2_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F8R2_FB17 CAN_F8R2_FB17_Msk /*!< Filter bit 17 */
+#define CAN_F8R2_FB18_Pos (18U)
+#define CAN_F8R2_FB18_Msk (0x1U << CAN_F8R2_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F8R2_FB18 CAN_F8R2_FB18_Msk /*!< Filter bit 18 */
+#define CAN_F8R2_FB19_Pos (19U)
+#define CAN_F8R2_FB19_Msk (0x1U << CAN_F8R2_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F8R2_FB19 CAN_F8R2_FB19_Msk /*!< Filter bit 19 */
+#define CAN_F8R2_FB20_Pos (20U)
+#define CAN_F8R2_FB20_Msk (0x1U << CAN_F8R2_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F8R2_FB20 CAN_F8R2_FB20_Msk /*!< Filter bit 20 */
+#define CAN_F8R2_FB21_Pos (21U)
+#define CAN_F8R2_FB21_Msk (0x1U << CAN_F8R2_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F8R2_FB21 CAN_F8R2_FB21_Msk /*!< Filter bit 21 */
+#define CAN_F8R2_FB22_Pos (22U)
+#define CAN_F8R2_FB22_Msk (0x1U << CAN_F8R2_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F8R2_FB22 CAN_F8R2_FB22_Msk /*!< Filter bit 22 */
+#define CAN_F8R2_FB23_Pos (23U)
+#define CAN_F8R2_FB23_Msk (0x1U << CAN_F8R2_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F8R2_FB23 CAN_F8R2_FB23_Msk /*!< Filter bit 23 */
+#define CAN_F8R2_FB24_Pos (24U)
+#define CAN_F8R2_FB24_Msk (0x1U << CAN_F8R2_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F8R2_FB24 CAN_F8R2_FB24_Msk /*!< Filter bit 24 */
+#define CAN_F8R2_FB25_Pos (25U)
+#define CAN_F8R2_FB25_Msk (0x1U << CAN_F8R2_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F8R2_FB25 CAN_F8R2_FB25_Msk /*!< Filter bit 25 */
+#define CAN_F8R2_FB26_Pos (26U)
+#define CAN_F8R2_FB26_Msk (0x1U << CAN_F8R2_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F8R2_FB26 CAN_F8R2_FB26_Msk /*!< Filter bit 26 */
+#define CAN_F8R2_FB27_Pos (27U)
+#define CAN_F8R2_FB27_Msk (0x1U << CAN_F8R2_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F8R2_FB27 CAN_F8R2_FB27_Msk /*!< Filter bit 27 */
+#define CAN_F8R2_FB28_Pos (28U)
+#define CAN_F8R2_FB28_Msk (0x1U << CAN_F8R2_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F8R2_FB28 CAN_F8R2_FB28_Msk /*!< Filter bit 28 */
+#define CAN_F8R2_FB29_Pos (29U)
+#define CAN_F8R2_FB29_Msk (0x1U << CAN_F8R2_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F8R2_FB29 CAN_F8R2_FB29_Msk /*!< Filter bit 29 */
+#define CAN_F8R2_FB30_Pos (30U)
+#define CAN_F8R2_FB30_Msk (0x1U << CAN_F8R2_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F8R2_FB30 CAN_F8R2_FB30_Msk /*!< Filter bit 30 */
+#define CAN_F8R2_FB31_Pos (31U)
+#define CAN_F8R2_FB31_Msk (0x1U << CAN_F8R2_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F8R2_FB31 CAN_F8R2_FB31_Msk /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F9R2 register *******************/
+#define CAN_F9R2_FB0_Pos (0U)
+#define CAN_F9R2_FB0_Msk (0x1U << CAN_F9R2_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F9R2_FB0 CAN_F9R2_FB0_Msk /*!< Filter bit 0 */
+#define CAN_F9R2_FB1_Pos (1U)
+#define CAN_F9R2_FB1_Msk (0x1U << CAN_F9R2_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F9R2_FB1 CAN_F9R2_FB1_Msk /*!< Filter bit 1 */
+#define CAN_F9R2_FB2_Pos (2U)
+#define CAN_F9R2_FB2_Msk (0x1U << CAN_F9R2_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F9R2_FB2 CAN_F9R2_FB2_Msk /*!< Filter bit 2 */
+#define CAN_F9R2_FB3_Pos (3U)
+#define CAN_F9R2_FB3_Msk (0x1U << CAN_F9R2_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F9R2_FB3 CAN_F9R2_FB3_Msk /*!< Filter bit 3 */
+#define CAN_F9R2_FB4_Pos (4U)
+#define CAN_F9R2_FB4_Msk (0x1U << CAN_F9R2_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F9R2_FB4 CAN_F9R2_FB4_Msk /*!< Filter bit 4 */
+#define CAN_F9R2_FB5_Pos (5U)
+#define CAN_F9R2_FB5_Msk (0x1U << CAN_F9R2_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F9R2_FB5 CAN_F9R2_FB5_Msk /*!< Filter bit 5 */
+#define CAN_F9R2_FB6_Pos (6U)
+#define CAN_F9R2_FB6_Msk (0x1U << CAN_F9R2_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F9R2_FB6 CAN_F9R2_FB6_Msk /*!< Filter bit 6 */
+#define CAN_F9R2_FB7_Pos (7U)
+#define CAN_F9R2_FB7_Msk (0x1U << CAN_F9R2_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F9R2_FB7 CAN_F9R2_FB7_Msk /*!< Filter bit 7 */
+#define CAN_F9R2_FB8_Pos (8U)
+#define CAN_F9R2_FB8_Msk (0x1U << CAN_F9R2_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F9R2_FB8 CAN_F9R2_FB8_Msk /*!< Filter bit 8 */
+#define CAN_F9R2_FB9_Pos (9U)
+#define CAN_F9R2_FB9_Msk (0x1U << CAN_F9R2_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F9R2_FB9 CAN_F9R2_FB9_Msk /*!< Filter bit 9 */
+#define CAN_F9R2_FB10_Pos (10U)
+#define CAN_F9R2_FB10_Msk (0x1U << CAN_F9R2_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F9R2_FB10 CAN_F9R2_FB10_Msk /*!< Filter bit 10 */
+#define CAN_F9R2_FB11_Pos (11U)
+#define CAN_F9R2_FB11_Msk (0x1U << CAN_F9R2_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F9R2_FB11 CAN_F9R2_FB11_Msk /*!< Filter bit 11 */
+#define CAN_F9R2_FB12_Pos (12U)
+#define CAN_F9R2_FB12_Msk (0x1U << CAN_F9R2_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F9R2_FB12 CAN_F9R2_FB12_Msk /*!< Filter bit 12 */
+#define CAN_F9R2_FB13_Pos (13U)
+#define CAN_F9R2_FB13_Msk (0x1U << CAN_F9R2_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F9R2_FB13 CAN_F9R2_FB13_Msk /*!< Filter bit 13 */
+#define CAN_F9R2_FB14_Pos (14U)
+#define CAN_F9R2_FB14_Msk (0x1U << CAN_F9R2_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F9R2_FB14 CAN_F9R2_FB14_Msk /*!< Filter bit 14 */
+#define CAN_F9R2_FB15_Pos (15U)
+#define CAN_F9R2_FB15_Msk (0x1U << CAN_F9R2_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F9R2_FB15 CAN_F9R2_FB15_Msk /*!< Filter bit 15 */
+#define CAN_F9R2_FB16_Pos (16U)
+#define CAN_F9R2_FB16_Msk (0x1U << CAN_F9R2_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F9R2_FB16 CAN_F9R2_FB16_Msk /*!< Filter bit 16 */
+#define CAN_F9R2_FB17_Pos (17U)
+#define CAN_F9R2_FB17_Msk (0x1U << CAN_F9R2_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F9R2_FB17 CAN_F9R2_FB17_Msk /*!< Filter bit 17 */
+#define CAN_F9R2_FB18_Pos (18U)
+#define CAN_F9R2_FB18_Msk (0x1U << CAN_F9R2_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F9R2_FB18 CAN_F9R2_FB18_Msk /*!< Filter bit 18 */
+#define CAN_F9R2_FB19_Pos (19U)
+#define CAN_F9R2_FB19_Msk (0x1U << CAN_F9R2_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F9R2_FB19 CAN_F9R2_FB19_Msk /*!< Filter bit 19 */
+#define CAN_F9R2_FB20_Pos (20U)
+#define CAN_F9R2_FB20_Msk (0x1U << CAN_F9R2_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F9R2_FB20 CAN_F9R2_FB20_Msk /*!< Filter bit 20 */
+#define CAN_F9R2_FB21_Pos (21U)
+#define CAN_F9R2_FB21_Msk (0x1U << CAN_F9R2_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F9R2_FB21 CAN_F9R2_FB21_Msk /*!< Filter bit 21 */
+#define CAN_F9R2_FB22_Pos (22U)
+#define CAN_F9R2_FB22_Msk (0x1U << CAN_F9R2_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F9R2_FB22 CAN_F9R2_FB22_Msk /*!< Filter bit 22 */
+#define CAN_F9R2_FB23_Pos (23U)
+#define CAN_F9R2_FB23_Msk (0x1U << CAN_F9R2_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F9R2_FB23 CAN_F9R2_FB23_Msk /*!< Filter bit 23 */
+#define CAN_F9R2_FB24_Pos (24U)
+#define CAN_F9R2_FB24_Msk (0x1U << CAN_F9R2_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F9R2_FB24 CAN_F9R2_FB24_Msk /*!< Filter bit 24 */
+#define CAN_F9R2_FB25_Pos (25U)
+#define CAN_F9R2_FB25_Msk (0x1U << CAN_F9R2_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F9R2_FB25 CAN_F9R2_FB25_Msk /*!< Filter bit 25 */
+#define CAN_F9R2_FB26_Pos (26U)
+#define CAN_F9R2_FB26_Msk (0x1U << CAN_F9R2_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F9R2_FB26 CAN_F9R2_FB26_Msk /*!< Filter bit 26 */
+#define CAN_F9R2_FB27_Pos (27U)
+#define CAN_F9R2_FB27_Msk (0x1U << CAN_F9R2_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F9R2_FB27 CAN_F9R2_FB27_Msk /*!< Filter bit 27 */
+#define CAN_F9R2_FB28_Pos (28U)
+#define CAN_F9R2_FB28_Msk (0x1U << CAN_F9R2_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F9R2_FB28 CAN_F9R2_FB28_Msk /*!< Filter bit 28 */
+#define CAN_F9R2_FB29_Pos (29U)
+#define CAN_F9R2_FB29_Msk (0x1U << CAN_F9R2_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F9R2_FB29 CAN_F9R2_FB29_Msk /*!< Filter bit 29 */
+#define CAN_F9R2_FB30_Pos (30U)
+#define CAN_F9R2_FB30_Msk (0x1U << CAN_F9R2_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F9R2_FB30 CAN_F9R2_FB30_Msk /*!< Filter bit 30 */
+#define CAN_F9R2_FB31_Pos (31U)
+#define CAN_F9R2_FB31_Msk (0x1U << CAN_F9R2_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F9R2_FB31 CAN_F9R2_FB31_Msk /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F10R2 register ******************/
+#define CAN_F10R2_FB0_Pos (0U)
+#define CAN_F10R2_FB0_Msk (0x1U << CAN_F10R2_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F10R2_FB0 CAN_F10R2_FB0_Msk /*!< Filter bit 0 */
+#define CAN_F10R2_FB1_Pos (1U)
+#define CAN_F10R2_FB1_Msk (0x1U << CAN_F10R2_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F10R2_FB1 CAN_F10R2_FB1_Msk /*!< Filter bit 1 */
+#define CAN_F10R2_FB2_Pos (2U)
+#define CAN_F10R2_FB2_Msk (0x1U << CAN_F10R2_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F10R2_FB2 CAN_F10R2_FB2_Msk /*!< Filter bit 2 */
+#define CAN_F10R2_FB3_Pos (3U)
+#define CAN_F10R2_FB3_Msk (0x1U << CAN_F10R2_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F10R2_FB3 CAN_F10R2_FB3_Msk /*!< Filter bit 3 */
+#define CAN_F10R2_FB4_Pos (4U)
+#define CAN_F10R2_FB4_Msk (0x1U << CAN_F10R2_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F10R2_FB4 CAN_F10R2_FB4_Msk /*!< Filter bit 4 */
+#define CAN_F10R2_FB5_Pos (5U)
+#define CAN_F10R2_FB5_Msk (0x1U << CAN_F10R2_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F10R2_FB5 CAN_F10R2_FB5_Msk /*!< Filter bit 5 */
+#define CAN_F10R2_FB6_Pos (6U)
+#define CAN_F10R2_FB6_Msk (0x1U << CAN_F10R2_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F10R2_FB6 CAN_F10R2_FB6_Msk /*!< Filter bit 6 */
+#define CAN_F10R2_FB7_Pos (7U)
+#define CAN_F10R2_FB7_Msk (0x1U << CAN_F10R2_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F10R2_FB7 CAN_F10R2_FB7_Msk /*!< Filter bit 7 */
+#define CAN_F10R2_FB8_Pos (8U)
+#define CAN_F10R2_FB8_Msk (0x1U << CAN_F10R2_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F10R2_FB8 CAN_F10R2_FB8_Msk /*!< Filter bit 8 */
+#define CAN_F10R2_FB9_Pos (9U)
+#define CAN_F10R2_FB9_Msk (0x1U << CAN_F10R2_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F10R2_FB9 CAN_F10R2_FB9_Msk /*!< Filter bit 9 */
+#define CAN_F10R2_FB10_Pos (10U)
+#define CAN_F10R2_FB10_Msk (0x1U << CAN_F10R2_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F10R2_FB10 CAN_F10R2_FB10_Msk /*!< Filter bit 10 */
+#define CAN_F10R2_FB11_Pos (11U)
+#define CAN_F10R2_FB11_Msk (0x1U << CAN_F10R2_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F10R2_FB11 CAN_F10R2_FB11_Msk /*!< Filter bit 11 */
+#define CAN_F10R2_FB12_Pos (12U)
+#define CAN_F10R2_FB12_Msk (0x1U << CAN_F10R2_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F10R2_FB12 CAN_F10R2_FB12_Msk /*!< Filter bit 12 */
+#define CAN_F10R2_FB13_Pos (13U)
+#define CAN_F10R2_FB13_Msk (0x1U << CAN_F10R2_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F10R2_FB13 CAN_F10R2_FB13_Msk /*!< Filter bit 13 */
+#define CAN_F10R2_FB14_Pos (14U)
+#define CAN_F10R2_FB14_Msk (0x1U << CAN_F10R2_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F10R2_FB14 CAN_F10R2_FB14_Msk /*!< Filter bit 14 */
+#define CAN_F10R2_FB15_Pos (15U)
+#define CAN_F10R2_FB15_Msk (0x1U << CAN_F10R2_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F10R2_FB15 CAN_F10R2_FB15_Msk /*!< Filter bit 15 */
+#define CAN_F10R2_FB16_Pos (16U)
+#define CAN_F10R2_FB16_Msk (0x1U << CAN_F10R2_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F10R2_FB16 CAN_F10R2_FB16_Msk /*!< Filter bit 16 */
+#define CAN_F10R2_FB17_Pos (17U)
+#define CAN_F10R2_FB17_Msk (0x1U << CAN_F10R2_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F10R2_FB17 CAN_F10R2_FB17_Msk /*!< Filter bit 17 */
+#define CAN_F10R2_FB18_Pos (18U)
+#define CAN_F10R2_FB18_Msk (0x1U << CAN_F10R2_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F10R2_FB18 CAN_F10R2_FB18_Msk /*!< Filter bit 18 */
+#define CAN_F10R2_FB19_Pos (19U)
+#define CAN_F10R2_FB19_Msk (0x1U << CAN_F10R2_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F10R2_FB19 CAN_F10R2_FB19_Msk /*!< Filter bit 19 */
+#define CAN_F10R2_FB20_Pos (20U)
+#define CAN_F10R2_FB20_Msk (0x1U << CAN_F10R2_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F10R2_FB20 CAN_F10R2_FB20_Msk /*!< Filter bit 20 */
+#define CAN_F10R2_FB21_Pos (21U)
+#define CAN_F10R2_FB21_Msk (0x1U << CAN_F10R2_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F10R2_FB21 CAN_F10R2_FB21_Msk /*!< Filter bit 21 */
+#define CAN_F10R2_FB22_Pos (22U)
+#define CAN_F10R2_FB22_Msk (0x1U << CAN_F10R2_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F10R2_FB22 CAN_F10R2_FB22_Msk /*!< Filter bit 22 */
+#define CAN_F10R2_FB23_Pos (23U)
+#define CAN_F10R2_FB23_Msk (0x1U << CAN_F10R2_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F10R2_FB23 CAN_F10R2_FB23_Msk /*!< Filter bit 23 */
+#define CAN_F10R2_FB24_Pos (24U)
+#define CAN_F10R2_FB24_Msk (0x1U << CAN_F10R2_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F10R2_FB24 CAN_F10R2_FB24_Msk /*!< Filter bit 24 */
+#define CAN_F10R2_FB25_Pos (25U)
+#define CAN_F10R2_FB25_Msk (0x1U << CAN_F10R2_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F10R2_FB25 CAN_F10R2_FB25_Msk /*!< Filter bit 25 */
+#define CAN_F10R2_FB26_Pos (26U)
+#define CAN_F10R2_FB26_Msk (0x1U << CAN_F10R2_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F10R2_FB26 CAN_F10R2_FB26_Msk /*!< Filter bit 26 */
+#define CAN_F10R2_FB27_Pos (27U)
+#define CAN_F10R2_FB27_Msk (0x1U << CAN_F10R2_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F10R2_FB27 CAN_F10R2_FB27_Msk /*!< Filter bit 27 */
+#define CAN_F10R2_FB28_Pos (28U)
+#define CAN_F10R2_FB28_Msk (0x1U << CAN_F10R2_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F10R2_FB28 CAN_F10R2_FB28_Msk /*!< Filter bit 28 */
+#define CAN_F10R2_FB29_Pos (29U)
+#define CAN_F10R2_FB29_Msk (0x1U << CAN_F10R2_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F10R2_FB29 CAN_F10R2_FB29_Msk /*!< Filter bit 29 */
+#define CAN_F10R2_FB30_Pos (30U)
+#define CAN_F10R2_FB30_Msk (0x1U << CAN_F10R2_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F10R2_FB30 CAN_F10R2_FB30_Msk /*!< Filter bit 30 */
+#define CAN_F10R2_FB31_Pos (31U)
+#define CAN_F10R2_FB31_Msk (0x1U << CAN_F10R2_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F10R2_FB31 CAN_F10R2_FB31_Msk /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F11R2 register ******************/
+#define CAN_F11R2_FB0_Pos (0U)
+#define CAN_F11R2_FB0_Msk (0x1U << CAN_F11R2_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F11R2_FB0 CAN_F11R2_FB0_Msk /*!< Filter bit 0 */
+#define CAN_F11R2_FB1_Pos (1U)
+#define CAN_F11R2_FB1_Msk (0x1U << CAN_F11R2_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F11R2_FB1 CAN_F11R2_FB1_Msk /*!< Filter bit 1 */
+#define CAN_F11R2_FB2_Pos (2U)
+#define CAN_F11R2_FB2_Msk (0x1U << CAN_F11R2_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F11R2_FB2 CAN_F11R2_FB2_Msk /*!< Filter bit 2 */
+#define CAN_F11R2_FB3_Pos (3U)
+#define CAN_F11R2_FB3_Msk (0x1U << CAN_F11R2_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F11R2_FB3 CAN_F11R2_FB3_Msk /*!< Filter bit 3 */
+#define CAN_F11R2_FB4_Pos (4U)
+#define CAN_F11R2_FB4_Msk (0x1U << CAN_F11R2_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F11R2_FB4 CAN_F11R2_FB4_Msk /*!< Filter bit 4 */
+#define CAN_F11R2_FB5_Pos (5U)
+#define CAN_F11R2_FB5_Msk (0x1U << CAN_F11R2_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F11R2_FB5 CAN_F11R2_FB5_Msk /*!< Filter bit 5 */
+#define CAN_F11R2_FB6_Pos (6U)
+#define CAN_F11R2_FB6_Msk (0x1U << CAN_F11R2_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F11R2_FB6 CAN_F11R2_FB6_Msk /*!< Filter bit 6 */
+#define CAN_F11R2_FB7_Pos (7U)
+#define CAN_F11R2_FB7_Msk (0x1U << CAN_F11R2_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F11R2_FB7 CAN_F11R2_FB7_Msk /*!< Filter bit 7 */
+#define CAN_F11R2_FB8_Pos (8U)
+#define CAN_F11R2_FB8_Msk (0x1U << CAN_F11R2_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F11R2_FB8 CAN_F11R2_FB8_Msk /*!< Filter bit 8 */
+#define CAN_F11R2_FB9_Pos (9U)
+#define CAN_F11R2_FB9_Msk (0x1U << CAN_F11R2_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F11R2_FB9 CAN_F11R2_FB9_Msk /*!< Filter bit 9 */
+#define CAN_F11R2_FB10_Pos (10U)
+#define CAN_F11R2_FB10_Msk (0x1U << CAN_F11R2_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F11R2_FB10 CAN_F11R2_FB10_Msk /*!< Filter bit 10 */
+#define CAN_F11R2_FB11_Pos (11U)
+#define CAN_F11R2_FB11_Msk (0x1U << CAN_F11R2_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F11R2_FB11 CAN_F11R2_FB11_Msk /*!< Filter bit 11 */
+#define CAN_F11R2_FB12_Pos (12U)
+#define CAN_F11R2_FB12_Msk (0x1U << CAN_F11R2_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F11R2_FB12 CAN_F11R2_FB12_Msk /*!< Filter bit 12 */
+#define CAN_F11R2_FB13_Pos (13U)
+#define CAN_F11R2_FB13_Msk (0x1U << CAN_F11R2_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F11R2_FB13 CAN_F11R2_FB13_Msk /*!< Filter bit 13 */
+#define CAN_F11R2_FB14_Pos (14U)
+#define CAN_F11R2_FB14_Msk (0x1U << CAN_F11R2_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F11R2_FB14 CAN_F11R2_FB14_Msk /*!< Filter bit 14 */
+#define CAN_F11R2_FB15_Pos (15U)
+#define CAN_F11R2_FB15_Msk (0x1U << CAN_F11R2_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F11R2_FB15 CAN_F11R2_FB15_Msk /*!< Filter bit 15 */
+#define CAN_F11R2_FB16_Pos (16U)
+#define CAN_F11R2_FB16_Msk (0x1U << CAN_F11R2_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F11R2_FB16 CAN_F11R2_FB16_Msk /*!< Filter bit 16 */
+#define CAN_F11R2_FB17_Pos (17U)
+#define CAN_F11R2_FB17_Msk (0x1U << CAN_F11R2_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F11R2_FB17 CAN_F11R2_FB17_Msk /*!< Filter bit 17 */
+#define CAN_F11R2_FB18_Pos (18U)
+#define CAN_F11R2_FB18_Msk (0x1U << CAN_F11R2_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F11R2_FB18 CAN_F11R2_FB18_Msk /*!< Filter bit 18 */
+#define CAN_F11R2_FB19_Pos (19U)
+#define CAN_F11R2_FB19_Msk (0x1U << CAN_F11R2_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F11R2_FB19 CAN_F11R2_FB19_Msk /*!< Filter bit 19 */
+#define CAN_F11R2_FB20_Pos (20U)
+#define CAN_F11R2_FB20_Msk (0x1U << CAN_F11R2_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F11R2_FB20 CAN_F11R2_FB20_Msk /*!< Filter bit 20 */
+#define CAN_F11R2_FB21_Pos (21U)
+#define CAN_F11R2_FB21_Msk (0x1U << CAN_F11R2_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F11R2_FB21 CAN_F11R2_FB21_Msk /*!< Filter bit 21 */
+#define CAN_F11R2_FB22_Pos (22U)
+#define CAN_F11R2_FB22_Msk (0x1U << CAN_F11R2_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F11R2_FB22 CAN_F11R2_FB22_Msk /*!< Filter bit 22 */
+#define CAN_F11R2_FB23_Pos (23U)
+#define CAN_F11R2_FB23_Msk (0x1U << CAN_F11R2_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F11R2_FB23 CAN_F11R2_FB23_Msk /*!< Filter bit 23 */
+#define CAN_F11R2_FB24_Pos (24U)
+#define CAN_F11R2_FB24_Msk (0x1U << CAN_F11R2_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F11R2_FB24 CAN_F11R2_FB24_Msk /*!< Filter bit 24 */
+#define CAN_F11R2_FB25_Pos (25U)
+#define CAN_F11R2_FB25_Msk (0x1U << CAN_F11R2_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F11R2_FB25 CAN_F11R2_FB25_Msk /*!< Filter bit 25 */
+#define CAN_F11R2_FB26_Pos (26U)
+#define CAN_F11R2_FB26_Msk (0x1U << CAN_F11R2_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F11R2_FB26 CAN_F11R2_FB26_Msk /*!< Filter bit 26 */
+#define CAN_F11R2_FB27_Pos (27U)
+#define CAN_F11R2_FB27_Msk (0x1U << CAN_F11R2_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F11R2_FB27 CAN_F11R2_FB27_Msk /*!< Filter bit 27 */
+#define CAN_F11R2_FB28_Pos (28U)
+#define CAN_F11R2_FB28_Msk (0x1U << CAN_F11R2_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F11R2_FB28 CAN_F11R2_FB28_Msk /*!< Filter bit 28 */
+#define CAN_F11R2_FB29_Pos (29U)
+#define CAN_F11R2_FB29_Msk (0x1U << CAN_F11R2_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F11R2_FB29 CAN_F11R2_FB29_Msk /*!< Filter bit 29 */
+#define CAN_F11R2_FB30_Pos (30U)
+#define CAN_F11R2_FB30_Msk (0x1U << CAN_F11R2_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F11R2_FB30 CAN_F11R2_FB30_Msk /*!< Filter bit 30 */
+#define CAN_F11R2_FB31_Pos (31U)
+#define CAN_F11R2_FB31_Msk (0x1U << CAN_F11R2_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F11R2_FB31 CAN_F11R2_FB31_Msk /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F12R2 register ******************/
+#define CAN_F12R2_FB0_Pos (0U)
+#define CAN_F12R2_FB0_Msk (0x1U << CAN_F12R2_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F12R2_FB0 CAN_F12R2_FB0_Msk /*!< Filter bit 0 */
+#define CAN_F12R2_FB1_Pos (1U)
+#define CAN_F12R2_FB1_Msk (0x1U << CAN_F12R2_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F12R2_FB1 CAN_F12R2_FB1_Msk /*!< Filter bit 1 */
+#define CAN_F12R2_FB2_Pos (2U)
+#define CAN_F12R2_FB2_Msk (0x1U << CAN_F12R2_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F12R2_FB2 CAN_F12R2_FB2_Msk /*!< Filter bit 2 */
+#define CAN_F12R2_FB3_Pos (3U)
+#define CAN_F12R2_FB3_Msk (0x1U << CAN_F12R2_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F12R2_FB3 CAN_F12R2_FB3_Msk /*!< Filter bit 3 */
+#define CAN_F12R2_FB4_Pos (4U)
+#define CAN_F12R2_FB4_Msk (0x1U << CAN_F12R2_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F12R2_FB4 CAN_F12R2_FB4_Msk /*!< Filter bit 4 */
+#define CAN_F12R2_FB5_Pos (5U)
+#define CAN_F12R2_FB5_Msk (0x1U << CAN_F12R2_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F12R2_FB5 CAN_F12R2_FB5_Msk /*!< Filter bit 5 */
+#define CAN_F12R2_FB6_Pos (6U)
+#define CAN_F12R2_FB6_Msk (0x1U << CAN_F12R2_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F12R2_FB6 CAN_F12R2_FB6_Msk /*!< Filter bit 6 */
+#define CAN_F12R2_FB7_Pos (7U)
+#define CAN_F12R2_FB7_Msk (0x1U << CAN_F12R2_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F12R2_FB7 CAN_F12R2_FB7_Msk /*!< Filter bit 7 */
+#define CAN_F12R2_FB8_Pos (8U)
+#define CAN_F12R2_FB8_Msk (0x1U << CAN_F12R2_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F12R2_FB8 CAN_F12R2_FB8_Msk /*!< Filter bit 8 */
+#define CAN_F12R2_FB9_Pos (9U)
+#define CAN_F12R2_FB9_Msk (0x1U << CAN_F12R2_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F12R2_FB9 CAN_F12R2_FB9_Msk /*!< Filter bit 9 */
+#define CAN_F12R2_FB10_Pos (10U)
+#define CAN_F12R2_FB10_Msk (0x1U << CAN_F12R2_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F12R2_FB10 CAN_F12R2_FB10_Msk /*!< Filter bit 10 */
+#define CAN_F12R2_FB11_Pos (11U)
+#define CAN_F12R2_FB11_Msk (0x1U << CAN_F12R2_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F12R2_FB11 CAN_F12R2_FB11_Msk /*!< Filter bit 11 */
+#define CAN_F12R2_FB12_Pos (12U)
+#define CAN_F12R2_FB12_Msk (0x1U << CAN_F12R2_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F12R2_FB12 CAN_F12R2_FB12_Msk /*!< Filter bit 12 */
+#define CAN_F12R2_FB13_Pos (13U)
+#define CAN_F12R2_FB13_Msk (0x1U << CAN_F12R2_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F12R2_FB13 CAN_F12R2_FB13_Msk /*!< Filter bit 13 */
+#define CAN_F12R2_FB14_Pos (14U)
+#define CAN_F12R2_FB14_Msk (0x1U << CAN_F12R2_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F12R2_FB14 CAN_F12R2_FB14_Msk /*!< Filter bit 14 */
+#define CAN_F12R2_FB15_Pos (15U)
+#define CAN_F12R2_FB15_Msk (0x1U << CAN_F12R2_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F12R2_FB15 CAN_F12R2_FB15_Msk /*!< Filter bit 15 */
+#define CAN_F12R2_FB16_Pos (16U)
+#define CAN_F12R2_FB16_Msk (0x1U << CAN_F12R2_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F12R2_FB16 CAN_F12R2_FB16_Msk /*!< Filter bit 16 */
+#define CAN_F12R2_FB17_Pos (17U)
+#define CAN_F12R2_FB17_Msk (0x1U << CAN_F12R2_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F12R2_FB17 CAN_F12R2_FB17_Msk /*!< Filter bit 17 */
+#define CAN_F12R2_FB18_Pos (18U)
+#define CAN_F12R2_FB18_Msk (0x1U << CAN_F12R2_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F12R2_FB18 CAN_F12R2_FB18_Msk /*!< Filter bit 18 */
+#define CAN_F12R2_FB19_Pos (19U)
+#define CAN_F12R2_FB19_Msk (0x1U << CAN_F12R2_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F12R2_FB19 CAN_F12R2_FB19_Msk /*!< Filter bit 19 */
+#define CAN_F12R2_FB20_Pos (20U)
+#define CAN_F12R2_FB20_Msk (0x1U << CAN_F12R2_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F12R2_FB20 CAN_F12R2_FB20_Msk /*!< Filter bit 20 */
+#define CAN_F12R2_FB21_Pos (21U)
+#define CAN_F12R2_FB21_Msk (0x1U << CAN_F12R2_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F12R2_FB21 CAN_F12R2_FB21_Msk /*!< Filter bit 21 */
+#define CAN_F12R2_FB22_Pos (22U)
+#define CAN_F12R2_FB22_Msk (0x1U << CAN_F12R2_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F12R2_FB22 CAN_F12R2_FB22_Msk /*!< Filter bit 22 */
+#define CAN_F12R2_FB23_Pos (23U)
+#define CAN_F12R2_FB23_Msk (0x1U << CAN_F12R2_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F12R2_FB23 CAN_F12R2_FB23_Msk /*!< Filter bit 23 */
+#define CAN_F12R2_FB24_Pos (24U)
+#define CAN_F12R2_FB24_Msk (0x1U << CAN_F12R2_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F12R2_FB24 CAN_F12R2_FB24_Msk /*!< Filter bit 24 */
+#define CAN_F12R2_FB25_Pos (25U)
+#define CAN_F12R2_FB25_Msk (0x1U << CAN_F12R2_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F12R2_FB25 CAN_F12R2_FB25_Msk /*!< Filter bit 25 */
+#define CAN_F12R2_FB26_Pos (26U)
+#define CAN_F12R2_FB26_Msk (0x1U << CAN_F12R2_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F12R2_FB26 CAN_F12R2_FB26_Msk /*!< Filter bit 26 */
+#define CAN_F12R2_FB27_Pos (27U)
+#define CAN_F12R2_FB27_Msk (0x1U << CAN_F12R2_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F12R2_FB27 CAN_F12R2_FB27_Msk /*!< Filter bit 27 */
+#define CAN_F12R2_FB28_Pos (28U)
+#define CAN_F12R2_FB28_Msk (0x1U << CAN_F12R2_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F12R2_FB28 CAN_F12R2_FB28_Msk /*!< Filter bit 28 */
+#define CAN_F12R2_FB29_Pos (29U)
+#define CAN_F12R2_FB29_Msk (0x1U << CAN_F12R2_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F12R2_FB29 CAN_F12R2_FB29_Msk /*!< Filter bit 29 */
+#define CAN_F12R2_FB30_Pos (30U)
+#define CAN_F12R2_FB30_Msk (0x1U << CAN_F12R2_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F12R2_FB30 CAN_F12R2_FB30_Msk /*!< Filter bit 30 */
+#define CAN_F12R2_FB31_Pos (31U)
+#define CAN_F12R2_FB31_Msk (0x1U << CAN_F12R2_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F12R2_FB31 CAN_F12R2_FB31_Msk /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F13R2 register ******************/
+#define CAN_F13R2_FB0_Pos (0U)
+#define CAN_F13R2_FB0_Msk (0x1U << CAN_F13R2_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F13R2_FB0 CAN_F13R2_FB0_Msk /*!< Filter bit 0 */
+#define CAN_F13R2_FB1_Pos (1U)
+#define CAN_F13R2_FB1_Msk (0x1U << CAN_F13R2_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F13R2_FB1 CAN_F13R2_FB1_Msk /*!< Filter bit 1 */
+#define CAN_F13R2_FB2_Pos (2U)
+#define CAN_F13R2_FB2_Msk (0x1U << CAN_F13R2_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F13R2_FB2 CAN_F13R2_FB2_Msk /*!< Filter bit 2 */
+#define CAN_F13R2_FB3_Pos (3U)
+#define CAN_F13R2_FB3_Msk (0x1U << CAN_F13R2_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F13R2_FB3 CAN_F13R2_FB3_Msk /*!< Filter bit 3 */
+#define CAN_F13R2_FB4_Pos (4U)
+#define CAN_F13R2_FB4_Msk (0x1U << CAN_F13R2_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F13R2_FB4 CAN_F13R2_FB4_Msk /*!< Filter bit 4 */
+#define CAN_F13R2_FB5_Pos (5U)
+#define CAN_F13R2_FB5_Msk (0x1U << CAN_F13R2_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F13R2_FB5 CAN_F13R2_FB5_Msk /*!< Filter bit 5 */
+#define CAN_F13R2_FB6_Pos (6U)
+#define CAN_F13R2_FB6_Msk (0x1U << CAN_F13R2_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F13R2_FB6 CAN_F13R2_FB6_Msk /*!< Filter bit 6 */
+#define CAN_F13R2_FB7_Pos (7U)
+#define CAN_F13R2_FB7_Msk (0x1U << CAN_F13R2_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F13R2_FB7 CAN_F13R2_FB7_Msk /*!< Filter bit 7 */
+#define CAN_F13R2_FB8_Pos (8U)
+#define CAN_F13R2_FB8_Msk (0x1U << CAN_F13R2_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F13R2_FB8 CAN_F13R2_FB8_Msk /*!< Filter bit 8 */
+#define CAN_F13R2_FB9_Pos (9U)
+#define CAN_F13R2_FB9_Msk (0x1U << CAN_F13R2_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F13R2_FB9 CAN_F13R2_FB9_Msk /*!< Filter bit 9 */
+#define CAN_F13R2_FB10_Pos (10U)
+#define CAN_F13R2_FB10_Msk (0x1U << CAN_F13R2_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F13R2_FB10 CAN_F13R2_FB10_Msk /*!< Filter bit 10 */
+#define CAN_F13R2_FB11_Pos (11U)
+#define CAN_F13R2_FB11_Msk (0x1U << CAN_F13R2_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F13R2_FB11 CAN_F13R2_FB11_Msk /*!< Filter bit 11 */
+#define CAN_F13R2_FB12_Pos (12U)
+#define CAN_F13R2_FB12_Msk (0x1U << CAN_F13R2_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F13R2_FB12 CAN_F13R2_FB12_Msk /*!< Filter bit 12 */
+#define CAN_F13R2_FB13_Pos (13U)
+#define CAN_F13R2_FB13_Msk (0x1U << CAN_F13R2_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F13R2_FB13 CAN_F13R2_FB13_Msk /*!< Filter bit 13 */
+#define CAN_F13R2_FB14_Pos (14U)
+#define CAN_F13R2_FB14_Msk (0x1U << CAN_F13R2_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F13R2_FB14 CAN_F13R2_FB14_Msk /*!< Filter bit 14 */
+#define CAN_F13R2_FB15_Pos (15U)
+#define CAN_F13R2_FB15_Msk (0x1U << CAN_F13R2_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F13R2_FB15 CAN_F13R2_FB15_Msk /*!< Filter bit 15 */
+#define CAN_F13R2_FB16_Pos (16U)
+#define CAN_F13R2_FB16_Msk (0x1U << CAN_F13R2_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F13R2_FB16 CAN_F13R2_FB16_Msk /*!< Filter bit 16 */
+#define CAN_F13R2_FB17_Pos (17U)
+#define CAN_F13R2_FB17_Msk (0x1U << CAN_F13R2_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F13R2_FB17 CAN_F13R2_FB17_Msk /*!< Filter bit 17 */
+#define CAN_F13R2_FB18_Pos (18U)
+#define CAN_F13R2_FB18_Msk (0x1U << CAN_F13R2_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F13R2_FB18 CAN_F13R2_FB18_Msk /*!< Filter bit 18 */
+#define CAN_F13R2_FB19_Pos (19U)
+#define CAN_F13R2_FB19_Msk (0x1U << CAN_F13R2_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F13R2_FB19 CAN_F13R2_FB19_Msk /*!< Filter bit 19 */
+#define CAN_F13R2_FB20_Pos (20U)
+#define CAN_F13R2_FB20_Msk (0x1U << CAN_F13R2_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F13R2_FB20 CAN_F13R2_FB20_Msk /*!< Filter bit 20 */
+#define CAN_F13R2_FB21_Pos (21U)
+#define CAN_F13R2_FB21_Msk (0x1U << CAN_F13R2_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F13R2_FB21 CAN_F13R2_FB21_Msk /*!< Filter bit 21 */
+#define CAN_F13R2_FB22_Pos (22U)
+#define CAN_F13R2_FB22_Msk (0x1U << CAN_F13R2_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F13R2_FB22 CAN_F13R2_FB22_Msk /*!< Filter bit 22 */
+#define CAN_F13R2_FB23_Pos (23U)
+#define CAN_F13R2_FB23_Msk (0x1U << CAN_F13R2_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F13R2_FB23 CAN_F13R2_FB23_Msk /*!< Filter bit 23 */
+#define CAN_F13R2_FB24_Pos (24U)
+#define CAN_F13R2_FB24_Msk (0x1U << CAN_F13R2_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F13R2_FB24 CAN_F13R2_FB24_Msk /*!< Filter bit 24 */
+#define CAN_F13R2_FB25_Pos (25U)
+#define CAN_F13R2_FB25_Msk (0x1U << CAN_F13R2_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F13R2_FB25 CAN_F13R2_FB25_Msk /*!< Filter bit 25 */
+#define CAN_F13R2_FB26_Pos (26U)
+#define CAN_F13R2_FB26_Msk (0x1U << CAN_F13R2_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F13R2_FB26 CAN_F13R2_FB26_Msk /*!< Filter bit 26 */
+#define CAN_F13R2_FB27_Pos (27U)
+#define CAN_F13R2_FB27_Msk (0x1U << CAN_F13R2_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F13R2_FB27 CAN_F13R2_FB27_Msk /*!< Filter bit 27 */
+#define CAN_F13R2_FB28_Pos (28U)
+#define CAN_F13R2_FB28_Msk (0x1U << CAN_F13R2_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F13R2_FB28 CAN_F13R2_FB28_Msk /*!< Filter bit 28 */
+#define CAN_F13R2_FB29_Pos (29U)
+#define CAN_F13R2_FB29_Msk (0x1U << CAN_F13R2_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F13R2_FB29 CAN_F13R2_FB29_Msk /*!< Filter bit 29 */
+#define CAN_F13R2_FB30_Pos (30U)
+#define CAN_F13R2_FB30_Msk (0x1U << CAN_F13R2_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F13R2_FB30 CAN_F13R2_FB30_Msk /*!< Filter bit 30 */
+#define CAN_F13R2_FB31_Pos (31U)
+#define CAN_F13R2_FB31_Msk (0x1U << CAN_F13R2_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F13R2_FB31 CAN_F13R2_FB31_Msk /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F14R2 register ******************/
+#define CAN_F14R2_FB0_Pos (0U)
+#define CAN_F14R2_FB0_Msk (0x1U << CAN_F14R2_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F14R2_FB0 CAN_F14R2_FB0_Msk /*!< Filter bit 0 */
+#define CAN_F14R2_FB1_Pos (1U)
+#define CAN_F14R2_FB1_Msk (0x1U << CAN_F14R2_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F14R2_FB1 CAN_F14R2_FB1_Msk /*!< Filter bit 1 */
+#define CAN_F14R2_FB2_Pos (2U)
+#define CAN_F14R2_FB2_Msk (0x1U << CAN_F14R2_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F14R2_FB2 CAN_F14R2_FB2_Msk /*!< Filter bit 2 */
+#define CAN_F14R2_FB3_Pos (3U)
+#define CAN_F14R2_FB3_Msk (0x1U << CAN_F14R2_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F14R2_FB3 CAN_F14R2_FB3_Msk /*!< Filter bit 3 */
+#define CAN_F14R2_FB4_Pos (4U)
+#define CAN_F14R2_FB4_Msk (0x1U << CAN_F14R2_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F14R2_FB4 CAN_F14R2_FB4_Msk /*!< Filter bit 4 */
+#define CAN_F14R2_FB5_Pos (5U)
+#define CAN_F14R2_FB5_Msk (0x1U << CAN_F14R2_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F14R2_FB5 CAN_F14R2_FB5_Msk /*!< Filter bit 5 */
+#define CAN_F14R2_FB6_Pos (6U)
+#define CAN_F14R2_FB6_Msk (0x1U << CAN_F14R2_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F14R2_FB6 CAN_F14R2_FB6_Msk /*!< Filter bit 6 */
+#define CAN_F14R2_FB7_Pos (7U)
+#define CAN_F14R2_FB7_Msk (0x1U << CAN_F14R2_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F14R2_FB7 CAN_F14R2_FB7_Msk /*!< Filter bit 7 */
+#define CAN_F14R2_FB8_Pos (8U)
+#define CAN_F14R2_FB8_Msk (0x1U << CAN_F14R2_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F14R2_FB8 CAN_F14R2_FB8_Msk /*!< Filter bit 8 */
+#define CAN_F14R2_FB9_Pos (9U)
+#define CAN_F14R2_FB9_Msk (0x1U << CAN_F14R2_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F14R2_FB9 CAN_F14R2_FB9_Msk /*!< Filter bit 9 */
+#define CAN_F14R2_FB10_Pos (10U)
+#define CAN_F14R2_FB10_Msk (0x1U << CAN_F14R2_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F14R2_FB10 CAN_F14R2_FB10_Msk /*!< Filter bit 10 */
+#define CAN_F14R2_FB11_Pos (11U)
+#define CAN_F14R2_FB11_Msk (0x1U << CAN_F14R2_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F14R2_FB11 CAN_F14R2_FB11_Msk /*!< Filter bit 11 */
+#define CAN_F14R2_FB12_Pos (12U)
+#define CAN_F14R2_FB12_Msk (0x1U << CAN_F14R2_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F14R2_FB12 CAN_F14R2_FB12_Msk /*!< Filter bit 12 */
+#define CAN_F14R2_FB13_Pos (13U)
+#define CAN_F14R2_FB13_Msk (0x1U << CAN_F14R2_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F14R2_FB13 CAN_F14R2_FB13_Msk /*!< Filter bit 13 */
+#define CAN_F14R2_FB14_Pos (14U)
+#define CAN_F14R2_FB14_Msk (0x1U << CAN_F14R2_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F14R2_FB14 CAN_F14R2_FB14_Msk /*!< Filter bit 14 */
+#define CAN_F14R2_FB15_Pos (15U)
+#define CAN_F14R2_FB15_Msk (0x1U << CAN_F14R2_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F14R2_FB15 CAN_F14R2_FB15_Msk /*!< Filter bit 15 */
+#define CAN_F14R2_FB16_Pos (16U)
+#define CAN_F14R2_FB16_Msk (0x1U << CAN_F14R2_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F14R2_FB16 CAN_F14R2_FB16_Msk /*!< Filter bit 16 */
+#define CAN_F14R2_FB17_Pos (17U)
+#define CAN_F14R2_FB17_Msk (0x1U << CAN_F14R2_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F14R2_FB17 CAN_F14R2_FB17_Msk /*!< Filter bit 17 */
+#define CAN_F14R2_FB18_Pos (18U)
+#define CAN_F14R2_FB18_Msk (0x1U << CAN_F14R2_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F14R2_FB18 CAN_F14R2_FB18_Msk /*!< Filter bit 18 */
+#define CAN_F14R2_FB19_Pos (19U)
+#define CAN_F14R2_FB19_Msk (0x1U << CAN_F14R2_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F14R2_FB19 CAN_F14R2_FB19_Msk /*!< Filter bit 19 */
+#define CAN_F14R2_FB20_Pos (20U)
+#define CAN_F14R2_FB20_Msk (0x1U << CAN_F14R2_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F14R2_FB20 CAN_F14R2_FB20_Msk /*!< Filter bit 20 */
+#define CAN_F14R2_FB21_Pos (21U)
+#define CAN_F14R2_FB21_Msk (0x1U << CAN_F14R2_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F14R2_FB21 CAN_F14R2_FB21_Msk /*!< Filter bit 21 */
+#define CAN_F14R2_FB22_Pos (22U)
+#define CAN_F14R2_FB22_Msk (0x1U << CAN_F14R2_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F14R2_FB22 CAN_F14R2_FB22_Msk /*!< Filter bit 22 */
+#define CAN_F14R2_FB23_Pos (23U)
+#define CAN_F14R2_FB23_Msk (0x1U << CAN_F14R2_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F14R2_FB23 CAN_F14R2_FB23_Msk /*!< Filter bit 23 */
+#define CAN_F14R2_FB24_Pos (24U)
+#define CAN_F14R2_FB24_Msk (0x1U << CAN_F14R2_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F14R2_FB24 CAN_F14R2_FB24_Msk /*!< Filter bit 24 */
+#define CAN_F14R2_FB25_Pos (25U)
+#define CAN_F14R2_FB25_Msk (0x1U << CAN_F14R2_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F14R2_FB25 CAN_F14R2_FB25_Msk /*!< Filter bit 25 */
+#define CAN_F14R2_FB26_Pos (26U)
+#define CAN_F14R2_FB26_Msk (0x1U << CAN_F14R2_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F14R2_FB26 CAN_F14R2_FB26_Msk /*!< Filter bit 26 */
+#define CAN_F14R2_FB27_Pos (27U)
+#define CAN_F14R2_FB27_Msk (0x1U << CAN_F14R2_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F14R2_FB27 CAN_F14R2_FB27_Msk /*!< Filter bit 27 */
+#define CAN_F14R2_FB28_Pos (28U)
+#define CAN_F14R2_FB28_Msk (0x1U << CAN_F14R2_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F14R2_FB28 CAN_F14R2_FB28_Msk /*!< Filter bit 28 */
+#define CAN_F14R2_FB29_Pos (29U)
+#define CAN_F14R2_FB29_Msk (0x1U << CAN_F14R2_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F14R2_FB29 CAN_F14R2_FB29_Msk /*!< Filter bit 29 */
+#define CAN_F14R2_FB30_Pos (30U)
+#define CAN_F14R2_FB30_Msk (0x1U << CAN_F14R2_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F14R2_FB30 CAN_F14R2_FB30_Msk /*!< Filter bit 30 */
+#define CAN_F14R2_FB31_Pos (31U)
+#define CAN_F14R2_FB31_Msk (0x1U << CAN_F14R2_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F14R2_FB31 CAN_F14R2_FB31_Msk /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F15R2 register ******************/
+#define CAN_F15R2_FB0_Pos (0U)
+#define CAN_F15R2_FB0_Msk (0x1U << CAN_F15R2_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F15R2_FB0 CAN_F15R2_FB0_Msk /*!< Filter bit 0 */
+#define CAN_F15R2_FB1_Pos (1U)
+#define CAN_F15R2_FB1_Msk (0x1U << CAN_F15R2_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F15R2_FB1 CAN_F15R2_FB1_Msk /*!< Filter bit 1 */
+#define CAN_F15R2_FB2_Pos (2U)
+#define CAN_F15R2_FB2_Msk (0x1U << CAN_F15R2_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F15R2_FB2 CAN_F15R2_FB2_Msk /*!< Filter bit 2 */
+#define CAN_F15R2_FB3_Pos (3U)
+#define CAN_F15R2_FB3_Msk (0x1U << CAN_F15R2_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F15R2_FB3 CAN_F15R2_FB3_Msk /*!< Filter bit 3 */
+#define CAN_F15R2_FB4_Pos (4U)
+#define CAN_F15R2_FB4_Msk (0x1U << CAN_F15R2_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F15R2_FB4 CAN_F15R2_FB4_Msk /*!< Filter bit 4 */
+#define CAN_F15R2_FB5_Pos (5U)
+#define CAN_F15R2_FB5_Msk (0x1U << CAN_F15R2_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F15R2_FB5 CAN_F15R2_FB5_Msk /*!< Filter bit 5 */
+#define CAN_F15R2_FB6_Pos (6U)
+#define CAN_F15R2_FB6_Msk (0x1U << CAN_F15R2_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F15R2_FB6 CAN_F15R2_FB6_Msk /*!< Filter bit 6 */
+#define CAN_F15R2_FB7_Pos (7U)
+#define CAN_F15R2_FB7_Msk (0x1U << CAN_F15R2_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F15R2_FB7 CAN_F15R2_FB7_Msk /*!< Filter bit 7 */
+#define CAN_F15R2_FB8_Pos (8U)
+#define CAN_F15R2_FB8_Msk (0x1U << CAN_F15R2_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F15R2_FB8 CAN_F15R2_FB8_Msk /*!< Filter bit 8 */
+#define CAN_F15R2_FB9_Pos (9U)
+#define CAN_F15R2_FB9_Msk (0x1U << CAN_F15R2_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F15R2_FB9 CAN_F15R2_FB9_Msk /*!< Filter bit 9 */
+#define CAN_F15R2_FB10_Pos (10U)
+#define CAN_F15R2_FB10_Msk (0x1U << CAN_F15R2_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F15R2_FB10 CAN_F15R2_FB10_Msk /*!< Filter bit 10 */
+#define CAN_F15R2_FB11_Pos (11U)
+#define CAN_F15R2_FB11_Msk (0x1U << CAN_F15R2_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F15R2_FB11 CAN_F15R2_FB11_Msk /*!< Filter bit 11 */
+#define CAN_F15R2_FB12_Pos (12U)
+#define CAN_F15R2_FB12_Msk (0x1U << CAN_F15R2_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F15R2_FB12 CAN_F15R2_FB12_Msk /*!< Filter bit 12 */
+#define CAN_F15R2_FB13_Pos (13U)
+#define CAN_F15R2_FB13_Msk (0x1U << CAN_F15R2_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F15R2_FB13 CAN_F15R2_FB13_Msk /*!< Filter bit 13 */
+#define CAN_F15R2_FB14_Pos (14U)
+#define CAN_F15R2_FB14_Msk (0x1U << CAN_F15R2_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F15R2_FB14 CAN_F15R2_FB14_Msk /*!< Filter bit 14 */
+#define CAN_F15R2_FB15_Pos (15U)
+#define CAN_F15R2_FB15_Msk (0x1U << CAN_F15R2_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F15R2_FB15 CAN_F15R2_FB15_Msk /*!< Filter bit 15 */
+#define CAN_F15R2_FB16_Pos (16U)
+#define CAN_F15R2_FB16_Msk (0x1U << CAN_F15R2_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F15R2_FB16 CAN_F15R2_FB16_Msk /*!< Filter bit 16 */
+#define CAN_F15R2_FB17_Pos (17U)
+#define CAN_F15R2_FB17_Msk (0x1U << CAN_F15R2_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F15R2_FB17 CAN_F15R2_FB17_Msk /*!< Filter bit 17 */
+#define CAN_F15R2_FB18_Pos (18U)
+#define CAN_F15R2_FB18_Msk (0x1U << CAN_F15R2_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F15R2_FB18 CAN_F15R2_FB18_Msk /*!< Filter bit 18 */
+#define CAN_F15R2_FB19_Pos (19U)
+#define CAN_F15R2_FB19_Msk (0x1U << CAN_F15R2_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F15R2_FB19 CAN_F15R2_FB19_Msk /*!< Filter bit 19 */
+#define CAN_F15R2_FB20_Pos (20U)
+#define CAN_F15R2_FB20_Msk (0x1U << CAN_F15R2_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F15R2_FB20 CAN_F15R2_FB20_Msk /*!< Filter bit 20 */
+#define CAN_F15R2_FB21_Pos (21U)
+#define CAN_F15R2_FB21_Msk (0x1U << CAN_F15R2_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F15R2_FB21 CAN_F15R2_FB21_Msk /*!< Filter bit 21 */
+#define CAN_F15R2_FB22_Pos (22U)
+#define CAN_F15R2_FB22_Msk (0x1U << CAN_F15R2_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F15R2_FB22 CAN_F15R2_FB22_Msk /*!< Filter bit 22 */
+#define CAN_F15R2_FB23_Pos (23U)
+#define CAN_F15R2_FB23_Msk (0x1U << CAN_F15R2_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F15R2_FB23 CAN_F15R2_FB23_Msk /*!< Filter bit 23 */
+#define CAN_F15R2_FB24_Pos (24U)
+#define CAN_F15R2_FB24_Msk (0x1U << CAN_F15R2_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F15R2_FB24 CAN_F15R2_FB24_Msk /*!< Filter bit 24 */
+#define CAN_F15R2_FB25_Pos (25U)
+#define CAN_F15R2_FB25_Msk (0x1U << CAN_F15R2_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F15R2_FB25 CAN_F15R2_FB25_Msk /*!< Filter bit 25 */
+#define CAN_F15R2_FB26_Pos (26U)
+#define CAN_F15R2_FB26_Msk (0x1U << CAN_F15R2_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F15R2_FB26 CAN_F15R2_FB26_Msk /*!< Filter bit 26 */
+#define CAN_F15R2_FB27_Pos (27U)
+#define CAN_F15R2_FB27_Msk (0x1U << CAN_F15R2_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F15R2_FB27 CAN_F15R2_FB27_Msk /*!< Filter bit 27 */
+#define CAN_F15R2_FB28_Pos (28U)
+#define CAN_F15R2_FB28_Msk (0x1U << CAN_F15R2_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F15R2_FB28 CAN_F15R2_FB28_Msk /*!< Filter bit 28 */
+#define CAN_F15R2_FB29_Pos (29U)
+#define CAN_F15R2_FB29_Msk (0x1U << CAN_F15R2_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F15R2_FB29 CAN_F15R2_FB29_Msk /*!< Filter bit 29 */
+#define CAN_F15R2_FB30_Pos (30U)
+#define CAN_F15R2_FB30_Msk (0x1U << CAN_F15R2_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F15R2_FB30 CAN_F15R2_FB30_Msk /*!< Filter bit 30 */
+#define CAN_F15R2_FB31_Pos (31U)
+#define CAN_F15R2_FB31_Msk (0x1U << CAN_F15R2_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F15R2_FB31 CAN_F15R2_FB31_Msk /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F16R2 register ******************/
+#define CAN_F16R2_FB0_Pos (0U)
+#define CAN_F16R2_FB0_Msk (0x1U << CAN_F16R2_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F16R2_FB0 CAN_F16R2_FB0_Msk /*!< Filter bit 0 */
+#define CAN_F16R2_FB1_Pos (1U)
+#define CAN_F16R2_FB1_Msk (0x1U << CAN_F16R2_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F16R2_FB1 CAN_F16R2_FB1_Msk /*!< Filter bit 1 */
+#define CAN_F16R2_FB2_Pos (2U)
+#define CAN_F16R2_FB2_Msk (0x1U << CAN_F16R2_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F16R2_FB2 CAN_F16R2_FB2_Msk /*!< Filter bit 2 */
+#define CAN_F16R2_FB3_Pos (3U)
+#define CAN_F16R2_FB3_Msk (0x1U << CAN_F16R2_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F16R2_FB3 CAN_F16R2_FB3_Msk /*!< Filter bit 3 */
+#define CAN_F16R2_FB4_Pos (4U)
+#define CAN_F16R2_FB4_Msk (0x1U << CAN_F16R2_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F16R2_FB4 CAN_F16R2_FB4_Msk /*!< Filter bit 4 */
+#define CAN_F16R2_FB5_Pos (5U)
+#define CAN_F16R2_FB5_Msk (0x1U << CAN_F16R2_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F16R2_FB5 CAN_F16R2_FB5_Msk /*!< Filter bit 5 */
+#define CAN_F16R2_FB6_Pos (6U)
+#define CAN_F16R2_FB6_Msk (0x1U << CAN_F16R2_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F16R2_FB6 CAN_F16R2_FB6_Msk /*!< Filter bit 6 */
+#define CAN_F16R2_FB7_Pos (7U)
+#define CAN_F16R2_FB7_Msk (0x1U << CAN_F16R2_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F16R2_FB7 CAN_F16R2_FB7_Msk /*!< Filter bit 7 */
+#define CAN_F16R2_FB8_Pos (8U)
+#define CAN_F16R2_FB8_Msk (0x1U << CAN_F16R2_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F16R2_FB8 CAN_F16R2_FB8_Msk /*!< Filter bit 8 */
+#define CAN_F16R2_FB9_Pos (9U)
+#define CAN_F16R2_FB9_Msk (0x1U << CAN_F16R2_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F16R2_FB9 CAN_F16R2_FB9_Msk /*!< Filter bit 9 */
+#define CAN_F16R2_FB10_Pos (10U)
+#define CAN_F16R2_FB10_Msk (0x1U << CAN_F16R2_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F16R2_FB10 CAN_F16R2_FB10_Msk /*!< Filter bit 10 */
+#define CAN_F16R2_FB11_Pos (11U)
+#define CAN_F16R2_FB11_Msk (0x1U << CAN_F16R2_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F16R2_FB11 CAN_F16R2_FB11_Msk /*!< Filter bit 11 */
+#define CAN_F16R2_FB12_Pos (12U)
+#define CAN_F16R2_FB12_Msk (0x1U << CAN_F16R2_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F16R2_FB12 CAN_F16R2_FB12_Msk /*!< Filter bit 12 */
+#define CAN_F16R2_FB13_Pos (13U)
+#define CAN_F16R2_FB13_Msk (0x1U << CAN_F16R2_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F16R2_FB13 CAN_F16R2_FB13_Msk /*!< Filter bit 13 */
+#define CAN_F16R2_FB14_Pos (14U)
+#define CAN_F16R2_FB14_Msk (0x1U << CAN_F16R2_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F16R2_FB14 CAN_F16R2_FB14_Msk /*!< Filter bit 14 */
+#define CAN_F16R2_FB15_Pos (15U)
+#define CAN_F16R2_FB15_Msk (0x1U << CAN_F16R2_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F16R2_FB15 CAN_F16R2_FB15_Msk /*!< Filter bit 15 */
+#define CAN_F16R2_FB16_Pos (16U)
+#define CAN_F16R2_FB16_Msk (0x1U << CAN_F16R2_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F16R2_FB16 CAN_F16R2_FB16_Msk /*!< Filter bit 16 */
+#define CAN_F16R2_FB17_Pos (17U)
+#define CAN_F16R2_FB17_Msk (0x1U << CAN_F16R2_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F16R2_FB17 CAN_F16R2_FB17_Msk /*!< Filter bit 17 */
+#define CAN_F16R2_FB18_Pos (18U)
+#define CAN_F16R2_FB18_Msk (0x1U << CAN_F16R2_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F16R2_FB18 CAN_F16R2_FB18_Msk /*!< Filter bit 18 */
+#define CAN_F16R2_FB19_Pos (19U)
+#define CAN_F16R2_FB19_Msk (0x1U << CAN_F16R2_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F16R2_FB19 CAN_F16R2_FB19_Msk /*!< Filter bit 19 */
+#define CAN_F16R2_FB20_Pos (20U)
+#define CAN_F16R2_FB20_Msk (0x1U << CAN_F16R2_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F16R2_FB20 CAN_F16R2_FB20_Msk /*!< Filter bit 20 */
+#define CAN_F16R2_FB21_Pos (21U)
+#define CAN_F16R2_FB21_Msk (0x1U << CAN_F16R2_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F16R2_FB21 CAN_F16R2_FB21_Msk /*!< Filter bit 21 */
+#define CAN_F16R2_FB22_Pos (22U)
+#define CAN_F16R2_FB22_Msk (0x1U << CAN_F16R2_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F16R2_FB22 CAN_F16R2_FB22_Msk /*!< Filter bit 22 */
+#define CAN_F16R2_FB23_Pos (23U)
+#define CAN_F16R2_FB23_Msk (0x1U << CAN_F16R2_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F16R2_FB23 CAN_F16R2_FB23_Msk /*!< Filter bit 23 */
+#define CAN_F16R2_FB24_Pos (24U)
+#define CAN_F16R2_FB24_Msk (0x1U << CAN_F16R2_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F16R2_FB24 CAN_F16R2_FB24_Msk /*!< Filter bit 24 */
+#define CAN_F16R2_FB25_Pos (25U)
+#define CAN_F16R2_FB25_Msk (0x1U << CAN_F16R2_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F16R2_FB25 CAN_F16R2_FB25_Msk /*!< Filter bit 25 */
+#define CAN_F16R2_FB26_Pos (26U)
+#define CAN_F16R2_FB26_Msk (0x1U << CAN_F16R2_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F16R2_FB26 CAN_F16R2_FB26_Msk /*!< Filter bit 26 */
+#define CAN_F16R2_FB27_Pos (27U)
+#define CAN_F16R2_FB27_Msk (0x1U << CAN_F16R2_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F16R2_FB27 CAN_F16R2_FB27_Msk /*!< Filter bit 27 */
+#define CAN_F16R2_FB28_Pos (28U)
+#define CAN_F16R2_FB28_Msk (0x1U << CAN_F16R2_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F16R2_FB28 CAN_F16R2_FB28_Msk /*!< Filter bit 28 */
+#define CAN_F16R2_FB29_Pos (29U)
+#define CAN_F16R2_FB29_Msk (0x1U << CAN_F16R2_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F16R2_FB29 CAN_F16R2_FB29_Msk /*!< Filter bit 29 */
+#define CAN_F16R2_FB30_Pos (30U)
+#define CAN_F16R2_FB30_Msk (0x1U << CAN_F16R2_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F16R2_FB30 CAN_F16R2_FB30_Msk /*!< Filter bit 30 */
+#define CAN_F16R2_FB31_Pos (31U)
+#define CAN_F16R2_FB31_Msk (0x1U << CAN_F16R2_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F16R2_FB31 CAN_F16R2_FB31_Msk /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F17R2 register ******************/
+#define CAN_F17R2_FB0_Pos (0U)
+#define CAN_F17R2_FB0_Msk (0x1U << CAN_F17R2_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F17R2_FB0 CAN_F17R2_FB0_Msk /*!< Filter bit 0 */
+#define CAN_F17R2_FB1_Pos (1U)
+#define CAN_F17R2_FB1_Msk (0x1U << CAN_F17R2_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F17R2_FB1 CAN_F17R2_FB1_Msk /*!< Filter bit 1 */
+#define CAN_F17R2_FB2_Pos (2U)
+#define CAN_F17R2_FB2_Msk (0x1U << CAN_F17R2_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F17R2_FB2 CAN_F17R2_FB2_Msk /*!< Filter bit 2 */
+#define CAN_F17R2_FB3_Pos (3U)
+#define CAN_F17R2_FB3_Msk (0x1U << CAN_F17R2_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F17R2_FB3 CAN_F17R2_FB3_Msk /*!< Filter bit 3 */
+#define CAN_F17R2_FB4_Pos (4U)
+#define CAN_F17R2_FB4_Msk (0x1U << CAN_F17R2_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F17R2_FB4 CAN_F17R2_FB4_Msk /*!< Filter bit 4 */
+#define CAN_F17R2_FB5_Pos (5U)
+#define CAN_F17R2_FB5_Msk (0x1U << CAN_F17R2_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F17R2_FB5 CAN_F17R2_FB5_Msk /*!< Filter bit 5 */
+#define CAN_F17R2_FB6_Pos (6U)
+#define CAN_F17R2_FB6_Msk (0x1U << CAN_F17R2_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F17R2_FB6 CAN_F17R2_FB6_Msk /*!< Filter bit 6 */
+#define CAN_F17R2_FB7_Pos (7U)
+#define CAN_F17R2_FB7_Msk (0x1U << CAN_F17R2_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F17R2_FB7 CAN_F17R2_FB7_Msk /*!< Filter bit 7 */
+#define CAN_F17R2_FB8_Pos (8U)
+#define CAN_F17R2_FB8_Msk (0x1U << CAN_F17R2_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F17R2_FB8 CAN_F17R2_FB8_Msk /*!< Filter bit 8 */
+#define CAN_F17R2_FB9_Pos (9U)
+#define CAN_F17R2_FB9_Msk (0x1U << CAN_F17R2_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F17R2_FB9 CAN_F17R2_FB9_Msk /*!< Filter bit 9 */
+#define CAN_F17R2_FB10_Pos (10U)
+#define CAN_F17R2_FB10_Msk (0x1U << CAN_F17R2_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F17R2_FB10 CAN_F17R2_FB10_Msk /*!< Filter bit 10 */
+#define CAN_F17R2_FB11_Pos (11U)
+#define CAN_F17R2_FB11_Msk (0x1U << CAN_F17R2_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F17R2_FB11 CAN_F17R2_FB11_Msk /*!< Filter bit 11 */
+#define CAN_F17R2_FB12_Pos (12U)
+#define CAN_F17R2_FB12_Msk (0x1U << CAN_F17R2_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F17R2_FB12 CAN_F17R2_FB12_Msk /*!< Filter bit 12 */
+#define CAN_F17R2_FB13_Pos (13U)
+#define CAN_F17R2_FB13_Msk (0x1U << CAN_F17R2_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F17R2_FB13 CAN_F17R2_FB13_Msk /*!< Filter bit 13 */
+#define CAN_F17R2_FB14_Pos (14U)
+#define CAN_F17R2_FB14_Msk (0x1U << CAN_F17R2_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F17R2_FB14 CAN_F17R2_FB14_Msk /*!< Filter bit 14 */
+#define CAN_F17R2_FB15_Pos (15U)
+#define CAN_F17R2_FB15_Msk (0x1U << CAN_F17R2_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F17R2_FB15 CAN_F17R2_FB15_Msk /*!< Filter bit 15 */
+#define CAN_F17R2_FB16_Pos (16U)
+#define CAN_F17R2_FB16_Msk (0x1U << CAN_F17R2_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F17R2_FB16 CAN_F17R2_FB16_Msk /*!< Filter bit 16 */
+#define CAN_F17R2_FB17_Pos (17U)
+#define CAN_F17R2_FB17_Msk (0x1U << CAN_F17R2_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F17R2_FB17 CAN_F17R2_FB17_Msk /*!< Filter bit 17 */
+#define CAN_F17R2_FB18_Pos (18U)
+#define CAN_F17R2_FB18_Msk (0x1U << CAN_F17R2_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F17R2_FB18 CAN_F17R2_FB18_Msk /*!< Filter bit 18 */
+#define CAN_F17R2_FB19_Pos (19U)
+#define CAN_F17R2_FB19_Msk (0x1U << CAN_F17R2_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F17R2_FB19 CAN_F17R2_FB19_Msk /*!< Filter bit 19 */
+#define CAN_F17R2_FB20_Pos (20U)
+#define CAN_F17R2_FB20_Msk (0x1U << CAN_F17R2_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F17R2_FB20 CAN_F17R2_FB20_Msk /*!< Filter bit 20 */
+#define CAN_F17R2_FB21_Pos (21U)
+#define CAN_F17R2_FB21_Msk (0x1U << CAN_F17R2_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F17R2_FB21 CAN_F17R2_FB21_Msk /*!< Filter bit 21 */
+#define CAN_F17R2_FB22_Pos (22U)
+#define CAN_F17R2_FB22_Msk (0x1U << CAN_F17R2_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F17R2_FB22 CAN_F17R2_FB22_Msk /*!< Filter bit 22 */
+#define CAN_F17R2_FB23_Pos (23U)
+#define CAN_F17R2_FB23_Msk (0x1U << CAN_F17R2_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F17R2_FB23 CAN_F17R2_FB23_Msk /*!< Filter bit 23 */
+#define CAN_F17R2_FB24_Pos (24U)
+#define CAN_F17R2_FB24_Msk (0x1U << CAN_F17R2_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F17R2_FB24 CAN_F17R2_FB24_Msk /*!< Filter bit 24 */
+#define CAN_F17R2_FB25_Pos (25U)
+#define CAN_F17R2_FB25_Msk (0x1U << CAN_F17R2_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F17R2_FB25 CAN_F17R2_FB25_Msk /*!< Filter bit 25 */
+#define CAN_F17R2_FB26_Pos (26U)
+#define CAN_F17R2_FB26_Msk (0x1U << CAN_F17R2_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F17R2_FB26 CAN_F17R2_FB26_Msk /*!< Filter bit 26 */
+#define CAN_F17R2_FB27_Pos (27U)
+#define CAN_F17R2_FB27_Msk (0x1U << CAN_F17R2_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F17R2_FB27 CAN_F17R2_FB27_Msk /*!< Filter bit 27 */
+#define CAN_F17R2_FB28_Pos (28U)
+#define CAN_F17R2_FB28_Msk (0x1U << CAN_F17R2_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F17R2_FB28 CAN_F17R2_FB28_Msk /*!< Filter bit 28 */
+#define CAN_F17R2_FB29_Pos (29U)
+#define CAN_F17R2_FB29_Msk (0x1U << CAN_F17R2_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F17R2_FB29 CAN_F17R2_FB29_Msk /*!< Filter bit 29 */
+#define CAN_F17R2_FB30_Pos (30U)
+#define CAN_F17R2_FB30_Msk (0x1U << CAN_F17R2_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F17R2_FB30 CAN_F17R2_FB30_Msk /*!< Filter bit 30 */
+#define CAN_F17R2_FB31_Pos (31U)
+#define CAN_F17R2_FB31_Msk (0x1U << CAN_F17R2_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F17R2_FB31 CAN_F17R2_FB31_Msk /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F18R2 register ******************/
+#define CAN_F18R2_FB0_Pos (0U)
+#define CAN_F18R2_FB0_Msk (0x1U << CAN_F18R2_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F18R2_FB0 CAN_F18R2_FB0_Msk /*!< Filter bit 0 */
+#define CAN_F18R2_FB1_Pos (1U)
+#define CAN_F18R2_FB1_Msk (0x1U << CAN_F18R2_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F18R2_FB1 CAN_F18R2_FB1_Msk /*!< Filter bit 1 */
+#define CAN_F18R2_FB2_Pos (2U)
+#define CAN_F18R2_FB2_Msk (0x1U << CAN_F18R2_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F18R2_FB2 CAN_F18R2_FB2_Msk /*!< Filter bit 2 */
+#define CAN_F18R2_FB3_Pos (3U)
+#define CAN_F18R2_FB3_Msk (0x1U << CAN_F18R2_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F18R2_FB3 CAN_F18R2_FB3_Msk /*!< Filter bit 3 */
+#define CAN_F18R2_FB4_Pos (4U)
+#define CAN_F18R2_FB4_Msk (0x1U << CAN_F18R2_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F18R2_FB4 CAN_F18R2_FB4_Msk /*!< Filter bit 4 */
+#define CAN_F18R2_FB5_Pos (5U)
+#define CAN_F18R2_FB5_Msk (0x1U << CAN_F18R2_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F18R2_FB5 CAN_F18R2_FB5_Msk /*!< Filter bit 5 */
+#define CAN_F18R2_FB6_Pos (6U)
+#define CAN_F18R2_FB6_Msk (0x1U << CAN_F18R2_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F18R2_FB6 CAN_F18R2_FB6_Msk /*!< Filter bit 6 */
+#define CAN_F18R2_FB7_Pos (7U)
+#define CAN_F18R2_FB7_Msk (0x1U << CAN_F18R2_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F18R2_FB7 CAN_F18R2_FB7_Msk /*!< Filter bit 7 */
+#define CAN_F18R2_FB8_Pos (8U)
+#define CAN_F18R2_FB8_Msk (0x1U << CAN_F18R2_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F18R2_FB8 CAN_F18R2_FB8_Msk /*!< Filter bit 8 */
+#define CAN_F18R2_FB9_Pos (9U)
+#define CAN_F18R2_FB9_Msk (0x1U << CAN_F18R2_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F18R2_FB9 CAN_F18R2_FB9_Msk /*!< Filter bit 9 */
+#define CAN_F18R2_FB10_Pos (10U)
+#define CAN_F18R2_FB10_Msk (0x1U << CAN_F18R2_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F18R2_FB10 CAN_F18R2_FB10_Msk /*!< Filter bit 10 */
+#define CAN_F18R2_FB11_Pos (11U)
+#define CAN_F18R2_FB11_Msk (0x1U << CAN_F18R2_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F18R2_FB11 CAN_F18R2_FB11_Msk /*!< Filter bit 11 */
+#define CAN_F18R2_FB12_Pos (12U)
+#define CAN_F18R2_FB12_Msk (0x1U << CAN_F18R2_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F18R2_FB12 CAN_F18R2_FB12_Msk /*!< Filter bit 12 */
+#define CAN_F18R2_FB13_Pos (13U)
+#define CAN_F18R2_FB13_Msk (0x1U << CAN_F18R2_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F18R2_FB13 CAN_F18R2_FB13_Msk /*!< Filter bit 13 */
+#define CAN_F18R2_FB14_Pos (14U)
+#define CAN_F18R2_FB14_Msk (0x1U << CAN_F18R2_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F18R2_FB14 CAN_F18R2_FB14_Msk /*!< Filter bit 14 */
+#define CAN_F18R2_FB15_Pos (15U)
+#define CAN_F18R2_FB15_Msk (0x1U << CAN_F18R2_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F18R2_FB15 CAN_F18R2_FB15_Msk /*!< Filter bit 15 */
+#define CAN_F18R2_FB16_Pos (16U)
+#define CAN_F18R2_FB16_Msk (0x1U << CAN_F18R2_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F18R2_FB16 CAN_F18R2_FB16_Msk /*!< Filter bit 16 */
+#define CAN_F18R2_FB17_Pos (17U)
+#define CAN_F18R2_FB17_Msk (0x1U << CAN_F18R2_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F18R2_FB17 CAN_F18R2_FB17_Msk /*!< Filter bit 17 */
+#define CAN_F18R2_FB18_Pos (18U)
+#define CAN_F18R2_FB18_Msk (0x1U << CAN_F18R2_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F18R2_FB18 CAN_F18R2_FB18_Msk /*!< Filter bit 18 */
+#define CAN_F18R2_FB19_Pos (19U)
+#define CAN_F18R2_FB19_Msk (0x1U << CAN_F18R2_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F18R2_FB19 CAN_F18R2_FB19_Msk /*!< Filter bit 19 */
+#define CAN_F18R2_FB20_Pos (20U)
+#define CAN_F18R2_FB20_Msk (0x1U << CAN_F18R2_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F18R2_FB20 CAN_F18R2_FB20_Msk /*!< Filter bit 20 */
+#define CAN_F18R2_FB21_Pos (21U)
+#define CAN_F18R2_FB21_Msk (0x1U << CAN_F18R2_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F18R2_FB21 CAN_F18R2_FB21_Msk /*!< Filter bit 21 */
+#define CAN_F18R2_FB22_Pos (22U)
+#define CAN_F18R2_FB22_Msk (0x1U << CAN_F18R2_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F18R2_FB22 CAN_F18R2_FB22_Msk /*!< Filter bit 22 */
+#define CAN_F18R2_FB23_Pos (23U)
+#define CAN_F18R2_FB23_Msk (0x1U << CAN_F18R2_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F18R2_FB23 CAN_F18R2_FB23_Msk /*!< Filter bit 23 */
+#define CAN_F18R2_FB24_Pos (24U)
+#define CAN_F18R2_FB24_Msk (0x1U << CAN_F18R2_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F18R2_FB24 CAN_F18R2_FB24_Msk /*!< Filter bit 24 */
+#define CAN_F18R2_FB25_Pos (25U)
+#define CAN_F18R2_FB25_Msk (0x1U << CAN_F18R2_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F18R2_FB25 CAN_F18R2_FB25_Msk /*!< Filter bit 25 */
+#define CAN_F18R2_FB26_Pos (26U)
+#define CAN_F18R2_FB26_Msk (0x1U << CAN_F18R2_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F18R2_FB26 CAN_F18R2_FB26_Msk /*!< Filter bit 26 */
+#define CAN_F18R2_FB27_Pos (27U)
+#define CAN_F18R2_FB27_Msk (0x1U << CAN_F18R2_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F18R2_FB27 CAN_F18R2_FB27_Msk /*!< Filter bit 27 */
+#define CAN_F18R2_FB28_Pos (28U)
+#define CAN_F18R2_FB28_Msk (0x1U << CAN_F18R2_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F18R2_FB28 CAN_F18R2_FB28_Msk /*!< Filter bit 28 */
+#define CAN_F18R2_FB29_Pos (29U)
+#define CAN_F18R2_FB29_Msk (0x1U << CAN_F18R2_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F18R2_FB29 CAN_F18R2_FB29_Msk /*!< Filter bit 29 */
+#define CAN_F18R2_FB30_Pos (30U)
+#define CAN_F18R2_FB30_Msk (0x1U << CAN_F18R2_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F18R2_FB30 CAN_F18R2_FB30_Msk /*!< Filter bit 30 */
+#define CAN_F18R2_FB31_Pos (31U)
+#define CAN_F18R2_FB31_Msk (0x1U << CAN_F18R2_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F18R2_FB31 CAN_F18R2_FB31_Msk /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F19R2 register ******************/
+#define CAN_F19R2_FB0_Pos (0U)
+#define CAN_F19R2_FB0_Msk (0x1U << CAN_F19R2_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F19R2_FB0 CAN_F19R2_FB0_Msk /*!< Filter bit 0 */
+#define CAN_F19R2_FB1_Pos (1U)
+#define CAN_F19R2_FB1_Msk (0x1U << CAN_F19R2_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F19R2_FB1 CAN_F19R2_FB1_Msk /*!< Filter bit 1 */
+#define CAN_F19R2_FB2_Pos (2U)
+#define CAN_F19R2_FB2_Msk (0x1U << CAN_F19R2_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F19R2_FB2 CAN_F19R2_FB2_Msk /*!< Filter bit 2 */
+#define CAN_F19R2_FB3_Pos (3U)
+#define CAN_F19R2_FB3_Msk (0x1U << CAN_F19R2_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F19R2_FB3 CAN_F19R2_FB3_Msk /*!< Filter bit 3 */
+#define CAN_F19R2_FB4_Pos (4U)
+#define CAN_F19R2_FB4_Msk (0x1U << CAN_F19R2_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F19R2_FB4 CAN_F19R2_FB4_Msk /*!< Filter bit 4 */
+#define CAN_F19R2_FB5_Pos (5U)
+#define CAN_F19R2_FB5_Msk (0x1U << CAN_F19R2_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F19R2_FB5 CAN_F19R2_FB5_Msk /*!< Filter bit 5 */
+#define CAN_F19R2_FB6_Pos (6U)
+#define CAN_F19R2_FB6_Msk (0x1U << CAN_F19R2_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F19R2_FB6 CAN_F19R2_FB6_Msk /*!< Filter bit 6 */
+#define CAN_F19R2_FB7_Pos (7U)
+#define CAN_F19R2_FB7_Msk (0x1U << CAN_F19R2_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F19R2_FB7 CAN_F19R2_FB7_Msk /*!< Filter bit 7 */
+#define CAN_F19R2_FB8_Pos (8U)
+#define CAN_F19R2_FB8_Msk (0x1U << CAN_F19R2_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F19R2_FB8 CAN_F19R2_FB8_Msk /*!< Filter bit 8 */
+#define CAN_F19R2_FB9_Pos (9U)
+#define CAN_F19R2_FB9_Msk (0x1U << CAN_F19R2_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F19R2_FB9 CAN_F19R2_FB9_Msk /*!< Filter bit 9 */
+#define CAN_F19R2_FB10_Pos (10U)
+#define CAN_F19R2_FB10_Msk (0x1U << CAN_F19R2_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F19R2_FB10 CAN_F19R2_FB10_Msk /*!< Filter bit 10 */
+#define CAN_F19R2_FB11_Pos (11U)
+#define CAN_F19R2_FB11_Msk (0x1U << CAN_F19R2_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F19R2_FB11 CAN_F19R2_FB11_Msk /*!< Filter bit 11 */
+#define CAN_F19R2_FB12_Pos (12U)
+#define CAN_F19R2_FB12_Msk (0x1U << CAN_F19R2_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F19R2_FB12 CAN_F19R2_FB12_Msk /*!< Filter bit 12 */
+#define CAN_F19R2_FB13_Pos (13U)
+#define CAN_F19R2_FB13_Msk (0x1U << CAN_F19R2_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F19R2_FB13 CAN_F19R2_FB13_Msk /*!< Filter bit 13 */
+#define CAN_F19R2_FB14_Pos (14U)
+#define CAN_F19R2_FB14_Msk (0x1U << CAN_F19R2_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F19R2_FB14 CAN_F19R2_FB14_Msk /*!< Filter bit 14 */
+#define CAN_F19R2_FB15_Pos (15U)
+#define CAN_F19R2_FB15_Msk (0x1U << CAN_F19R2_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F19R2_FB15 CAN_F19R2_FB15_Msk /*!< Filter bit 15 */
+#define CAN_F19R2_FB16_Pos (16U)
+#define CAN_F19R2_FB16_Msk (0x1U << CAN_F19R2_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F19R2_FB16 CAN_F19R2_FB16_Msk /*!< Filter bit 16 */
+#define CAN_F19R2_FB17_Pos (17U)
+#define CAN_F19R2_FB17_Msk (0x1U << CAN_F19R2_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F19R2_FB17 CAN_F19R2_FB17_Msk /*!< Filter bit 17 */
+#define CAN_F19R2_FB18_Pos (18U)
+#define CAN_F19R2_FB18_Msk (0x1U << CAN_F19R2_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F19R2_FB18 CAN_F19R2_FB18_Msk /*!< Filter bit 18 */
+#define CAN_F19R2_FB19_Pos (19U)
+#define CAN_F19R2_FB19_Msk (0x1U << CAN_F19R2_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F19R2_FB19 CAN_F19R2_FB19_Msk /*!< Filter bit 19 */
+#define CAN_F19R2_FB20_Pos (20U)
+#define CAN_F19R2_FB20_Msk (0x1U << CAN_F19R2_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F19R2_FB20 CAN_F19R2_FB20_Msk /*!< Filter bit 20 */
+#define CAN_F19R2_FB21_Pos (21U)
+#define CAN_F19R2_FB21_Msk (0x1U << CAN_F19R2_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F19R2_FB21 CAN_F19R2_FB21_Msk /*!< Filter bit 21 */
+#define CAN_F19R2_FB22_Pos (22U)
+#define CAN_F19R2_FB22_Msk (0x1U << CAN_F19R2_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F19R2_FB22 CAN_F19R2_FB22_Msk /*!< Filter bit 22 */
+#define CAN_F19R2_FB23_Pos (23U)
+#define CAN_F19R2_FB23_Msk (0x1U << CAN_F19R2_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F19R2_FB23 CAN_F19R2_FB23_Msk /*!< Filter bit 23 */
+#define CAN_F19R2_FB24_Pos (24U)
+#define CAN_F19R2_FB24_Msk (0x1U << CAN_F19R2_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F19R2_FB24 CAN_F19R2_FB24_Msk /*!< Filter bit 24 */
+#define CAN_F19R2_FB25_Pos (25U)
+#define CAN_F19R2_FB25_Msk (0x1U << CAN_F19R2_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F19R2_FB25 CAN_F19R2_FB25_Msk /*!< Filter bit 25 */
+#define CAN_F19R2_FB26_Pos (26U)
+#define CAN_F19R2_FB26_Msk (0x1U << CAN_F19R2_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F19R2_FB26 CAN_F19R2_FB26_Msk /*!< Filter bit 26 */
+#define CAN_F19R2_FB27_Pos (27U)
+#define CAN_F19R2_FB27_Msk (0x1U << CAN_F19R2_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F19R2_FB27 CAN_F19R2_FB27_Msk /*!< Filter bit 27 */
+#define CAN_F19R2_FB28_Pos (28U)
+#define CAN_F19R2_FB28_Msk (0x1U << CAN_F19R2_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F19R2_FB28 CAN_F19R2_FB28_Msk /*!< Filter bit 28 */
+#define CAN_F19R2_FB29_Pos (29U)
+#define CAN_F19R2_FB29_Msk (0x1U << CAN_F19R2_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F19R2_FB29 CAN_F19R2_FB29_Msk /*!< Filter bit 29 */
+#define CAN_F19R2_FB30_Pos (30U)
+#define CAN_F19R2_FB30_Msk (0x1U << CAN_F19R2_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F19R2_FB30 CAN_F19R2_FB30_Msk /*!< Filter bit 30 */
+#define CAN_F19R2_FB31_Pos (31U)
+#define CAN_F19R2_FB31_Msk (0x1U << CAN_F19R2_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F19R2_FB31 CAN_F19R2_FB31_Msk /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F20R2 register ******************/
+#define CAN_F20R2_FB0_Pos (0U)
+#define CAN_F20R2_FB0_Msk (0x1U << CAN_F20R2_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F20R2_FB0 CAN_F20R2_FB0_Msk /*!< Filter bit 0 */
+#define CAN_F20R2_FB1_Pos (1U)
+#define CAN_F20R2_FB1_Msk (0x1U << CAN_F20R2_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F20R2_FB1 CAN_F20R2_FB1_Msk /*!< Filter bit 1 */
+#define CAN_F20R2_FB2_Pos (2U)
+#define CAN_F20R2_FB2_Msk (0x1U << CAN_F20R2_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F20R2_FB2 CAN_F20R2_FB2_Msk /*!< Filter bit 2 */
+#define CAN_F20R2_FB3_Pos (3U)
+#define CAN_F20R2_FB3_Msk (0x1U << CAN_F20R2_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F20R2_FB3 CAN_F20R2_FB3_Msk /*!< Filter bit 3 */
+#define CAN_F20R2_FB4_Pos (4U)
+#define CAN_F20R2_FB4_Msk (0x1U << CAN_F20R2_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F20R2_FB4 CAN_F20R2_FB4_Msk /*!< Filter bit 4 */
+#define CAN_F20R2_FB5_Pos (5U)
+#define CAN_F20R2_FB5_Msk (0x1U << CAN_F20R2_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F20R2_FB5 CAN_F20R2_FB5_Msk /*!< Filter bit 5 */
+#define CAN_F20R2_FB6_Pos (6U)
+#define CAN_F20R2_FB6_Msk (0x1U << CAN_F20R2_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F20R2_FB6 CAN_F20R2_FB6_Msk /*!< Filter bit 6 */
+#define CAN_F20R2_FB7_Pos (7U)
+#define CAN_F20R2_FB7_Msk (0x1U << CAN_F20R2_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F20R2_FB7 CAN_F20R2_FB7_Msk /*!< Filter bit 7 */
+#define CAN_F20R2_FB8_Pos (8U)
+#define CAN_F20R2_FB8_Msk (0x1U << CAN_F20R2_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F20R2_FB8 CAN_F20R2_FB8_Msk /*!< Filter bit 8 */
+#define CAN_F20R2_FB9_Pos (9U)
+#define CAN_F20R2_FB9_Msk (0x1U << CAN_F20R2_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F20R2_FB9 CAN_F20R2_FB9_Msk /*!< Filter bit 9 */
+#define CAN_F20R2_FB10_Pos (10U)
+#define CAN_F20R2_FB10_Msk (0x1U << CAN_F20R2_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F20R2_FB10 CAN_F20R2_FB10_Msk /*!< Filter bit 10 */
+#define CAN_F20R2_FB11_Pos (11U)
+#define CAN_F20R2_FB11_Msk (0x1U << CAN_F20R2_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F20R2_FB11 CAN_F20R2_FB11_Msk /*!< Filter bit 11 */
+#define CAN_F20R2_FB12_Pos (12U)
+#define CAN_F20R2_FB12_Msk (0x1U << CAN_F20R2_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F20R2_FB12 CAN_F20R2_FB12_Msk /*!< Filter bit 12 */
+#define CAN_F20R2_FB13_Pos (13U)
+#define CAN_F20R2_FB13_Msk (0x1U << CAN_F20R2_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F20R2_FB13 CAN_F20R2_FB13_Msk /*!< Filter bit 13 */
+#define CAN_F20R2_FB14_Pos (14U)
+#define CAN_F20R2_FB14_Msk (0x1U << CAN_F20R2_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F20R2_FB14 CAN_F20R2_FB14_Msk /*!< Filter bit 14 */
+#define CAN_F20R2_FB15_Pos (15U)
+#define CAN_F20R2_FB15_Msk (0x1U << CAN_F20R2_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F20R2_FB15 CAN_F20R2_FB15_Msk /*!< Filter bit 15 */
+#define CAN_F20R2_FB16_Pos (16U)
+#define CAN_F20R2_FB16_Msk (0x1U << CAN_F20R2_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F20R2_FB16 CAN_F20R2_FB16_Msk /*!< Filter bit 16 */
+#define CAN_F20R2_FB17_Pos (17U)
+#define CAN_F20R2_FB17_Msk (0x1U << CAN_F20R2_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F20R2_FB17 CAN_F20R2_FB17_Msk /*!< Filter bit 17 */
+#define CAN_F20R2_FB18_Pos (18U)
+#define CAN_F20R2_FB18_Msk (0x1U << CAN_F20R2_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F20R2_FB18 CAN_F20R2_FB18_Msk /*!< Filter bit 18 */
+#define CAN_F20R2_FB19_Pos (19U)
+#define CAN_F20R2_FB19_Msk (0x1U << CAN_F20R2_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F20R2_FB19 CAN_F20R2_FB19_Msk /*!< Filter bit 19 */
+#define CAN_F20R2_FB20_Pos (20U)
+#define CAN_F20R2_FB20_Msk (0x1U << CAN_F20R2_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F20R2_FB20 CAN_F20R2_FB20_Msk /*!< Filter bit 20 */
+#define CAN_F20R2_FB21_Pos (21U)
+#define CAN_F20R2_FB21_Msk (0x1U << CAN_F20R2_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F20R2_FB21 CAN_F20R2_FB21_Msk /*!< Filter bit 21 */
+#define CAN_F20R2_FB22_Pos (22U)
+#define CAN_F20R2_FB22_Msk (0x1U << CAN_F20R2_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F20R2_FB22 CAN_F20R2_FB22_Msk /*!< Filter bit 22 */
+#define CAN_F20R2_FB23_Pos (23U)
+#define CAN_F20R2_FB23_Msk (0x1U << CAN_F20R2_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F20R2_FB23 CAN_F20R2_FB23_Msk /*!< Filter bit 23 */
+#define CAN_F20R2_FB24_Pos (24U)
+#define CAN_F20R2_FB24_Msk (0x1U << CAN_F20R2_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F20R2_FB24 CAN_F20R2_FB24_Msk /*!< Filter bit 24 */
+#define CAN_F20R2_FB25_Pos (25U)
+#define CAN_F20R2_FB25_Msk (0x1U << CAN_F20R2_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F20R2_FB25 CAN_F20R2_FB25_Msk /*!< Filter bit 25 */
+#define CAN_F20R2_FB26_Pos (26U)
+#define CAN_F20R2_FB26_Msk (0x1U << CAN_F20R2_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F20R2_FB26 CAN_F20R2_FB26_Msk /*!< Filter bit 26 */
+#define CAN_F20R2_FB27_Pos (27U)
+#define CAN_F20R2_FB27_Msk (0x1U << CAN_F20R2_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F20R2_FB27 CAN_F20R2_FB27_Msk /*!< Filter bit 27 */
+#define CAN_F20R2_FB28_Pos (28U)
+#define CAN_F20R2_FB28_Msk (0x1U << CAN_F20R2_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F20R2_FB28 CAN_F20R2_FB28_Msk /*!< Filter bit 28 */
+#define CAN_F20R2_FB29_Pos (29U)
+#define CAN_F20R2_FB29_Msk (0x1U << CAN_F20R2_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F20R2_FB29 CAN_F20R2_FB29_Msk /*!< Filter bit 29 */
+#define CAN_F20R2_FB30_Pos (30U)
+#define CAN_F20R2_FB30_Msk (0x1U << CAN_F20R2_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F20R2_FB30 CAN_F20R2_FB30_Msk /*!< Filter bit 30 */
+#define CAN_F20R2_FB31_Pos (31U)
+#define CAN_F20R2_FB31_Msk (0x1U << CAN_F20R2_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F20R2_FB31 CAN_F20R2_FB31_Msk /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F21R2 register ******************/
+#define CAN_F21R2_FB0_Pos (0U)
+#define CAN_F21R2_FB0_Msk (0x1U << CAN_F21R2_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F21R2_FB0 CAN_F21R2_FB0_Msk /*!< Filter bit 0 */
+#define CAN_F21R2_FB1_Pos (1U)
+#define CAN_F21R2_FB1_Msk (0x1U << CAN_F21R2_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F21R2_FB1 CAN_F21R2_FB1_Msk /*!< Filter bit 1 */
+#define CAN_F21R2_FB2_Pos (2U)
+#define CAN_F21R2_FB2_Msk (0x1U << CAN_F21R2_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F21R2_FB2 CAN_F21R2_FB2_Msk /*!< Filter bit 2 */
+#define CAN_F21R2_FB3_Pos (3U)
+#define CAN_F21R2_FB3_Msk (0x1U << CAN_F21R2_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F21R2_FB3 CAN_F21R2_FB3_Msk /*!< Filter bit 3 */
+#define CAN_F21R2_FB4_Pos (4U)
+#define CAN_F21R2_FB4_Msk (0x1U << CAN_F21R2_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F21R2_FB4 CAN_F21R2_FB4_Msk /*!< Filter bit 4 */
+#define CAN_F21R2_FB5_Pos (5U)
+#define CAN_F21R2_FB5_Msk (0x1U << CAN_F21R2_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F21R2_FB5 CAN_F21R2_FB5_Msk /*!< Filter bit 5 */
+#define CAN_F21R2_FB6_Pos (6U)
+#define CAN_F21R2_FB6_Msk (0x1U << CAN_F21R2_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F21R2_FB6 CAN_F21R2_FB6_Msk /*!< Filter bit 6 */
+#define CAN_F21R2_FB7_Pos (7U)
+#define CAN_F21R2_FB7_Msk (0x1U << CAN_F21R2_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F21R2_FB7 CAN_F21R2_FB7_Msk /*!< Filter bit 7 */
+#define CAN_F21R2_FB8_Pos (8U)
+#define CAN_F21R2_FB8_Msk (0x1U << CAN_F21R2_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F21R2_FB8 CAN_F21R2_FB8_Msk /*!< Filter bit 8 */
+#define CAN_F21R2_FB9_Pos (9U)
+#define CAN_F21R2_FB9_Msk (0x1U << CAN_F21R2_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F21R2_FB9 CAN_F21R2_FB9_Msk /*!< Filter bit 9 */
+#define CAN_F21R2_FB10_Pos (10U)
+#define CAN_F21R2_FB10_Msk (0x1U << CAN_F21R2_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F21R2_FB10 CAN_F21R2_FB10_Msk /*!< Filter bit 10 */
+#define CAN_F21R2_FB11_Pos (11U)
+#define CAN_F21R2_FB11_Msk (0x1U << CAN_F21R2_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F21R2_FB11 CAN_F21R2_FB11_Msk /*!< Filter bit 11 */
+#define CAN_F21R2_FB12_Pos (12U)
+#define CAN_F21R2_FB12_Msk (0x1U << CAN_F21R2_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F21R2_FB12 CAN_F21R2_FB12_Msk /*!< Filter bit 12 */
+#define CAN_F21R2_FB13_Pos (13U)
+#define CAN_F21R2_FB13_Msk (0x1U << CAN_F21R2_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F21R2_FB13 CAN_F21R2_FB13_Msk /*!< Filter bit 13 */
+#define CAN_F21R2_FB14_Pos (14U)
+#define CAN_F21R2_FB14_Msk (0x1U << CAN_F21R2_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F21R2_FB14 CAN_F21R2_FB14_Msk /*!< Filter bit 14 */
+#define CAN_F21R2_FB15_Pos (15U)
+#define CAN_F21R2_FB15_Msk (0x1U << CAN_F21R2_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F21R2_FB15 CAN_F21R2_FB15_Msk /*!< Filter bit 15 */
+#define CAN_F21R2_FB16_Pos (16U)
+#define CAN_F21R2_FB16_Msk (0x1U << CAN_F21R2_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F21R2_FB16 CAN_F21R2_FB16_Msk /*!< Filter bit 16 */
+#define CAN_F21R2_FB17_Pos (17U)
+#define CAN_F21R2_FB17_Msk (0x1U << CAN_F21R2_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F21R2_FB17 CAN_F21R2_FB17_Msk /*!< Filter bit 17 */
+#define CAN_F21R2_FB18_Pos (18U)
+#define CAN_F21R2_FB18_Msk (0x1U << CAN_F21R2_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F21R2_FB18 CAN_F21R2_FB18_Msk /*!< Filter bit 18 */
+#define CAN_F21R2_FB19_Pos (19U)
+#define CAN_F21R2_FB19_Msk (0x1U << CAN_F21R2_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F21R2_FB19 CAN_F21R2_FB19_Msk /*!< Filter bit 19 */
+#define CAN_F21R2_FB20_Pos (20U)
+#define CAN_F21R2_FB20_Msk (0x1U << CAN_F21R2_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F21R2_FB20 CAN_F21R2_FB20_Msk /*!< Filter bit 20 */
+#define CAN_F21R2_FB21_Pos (21U)
+#define CAN_F21R2_FB21_Msk (0x1U << CAN_F21R2_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F21R2_FB21 CAN_F21R2_FB21_Msk /*!< Filter bit 21 */
+#define CAN_F21R2_FB22_Pos (22U)
+#define CAN_F21R2_FB22_Msk (0x1U << CAN_F21R2_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F21R2_FB22 CAN_F21R2_FB22_Msk /*!< Filter bit 22 */
+#define CAN_F21R2_FB23_Pos (23U)
+#define CAN_F21R2_FB23_Msk (0x1U << CAN_F21R2_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F21R2_FB23 CAN_F21R2_FB23_Msk /*!< Filter bit 23 */
+#define CAN_F21R2_FB24_Pos (24U)
+#define CAN_F21R2_FB24_Msk (0x1U << CAN_F21R2_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F21R2_FB24 CAN_F21R2_FB24_Msk /*!< Filter bit 24 */
+#define CAN_F21R2_FB25_Pos (25U)
+#define CAN_F21R2_FB25_Msk (0x1U << CAN_F21R2_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F21R2_FB25 CAN_F21R2_FB25_Msk /*!< Filter bit 25 */
+#define CAN_F21R2_FB26_Pos (26U)
+#define CAN_F21R2_FB26_Msk (0x1U << CAN_F21R2_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F21R2_FB26 CAN_F21R2_FB26_Msk /*!< Filter bit 26 */
+#define CAN_F21R2_FB27_Pos (27U)
+#define CAN_F21R2_FB27_Msk (0x1U << CAN_F21R2_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F21R2_FB27 CAN_F21R2_FB27_Msk /*!< Filter bit 27 */
+#define CAN_F21R2_FB28_Pos (28U)
+#define CAN_F21R2_FB28_Msk (0x1U << CAN_F21R2_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F21R2_FB28 CAN_F21R2_FB28_Msk /*!< Filter bit 28 */
+#define CAN_F21R2_FB29_Pos (29U)
+#define CAN_F21R2_FB29_Msk (0x1U << CAN_F21R2_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F21R2_FB29 CAN_F21R2_FB29_Msk /*!< Filter bit 29 */
+#define CAN_F21R2_FB30_Pos (30U)
+#define CAN_F21R2_FB30_Msk (0x1U << CAN_F21R2_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F21R2_FB30 CAN_F21R2_FB30_Msk /*!< Filter bit 30 */
+#define CAN_F21R2_FB31_Pos (31U)
+#define CAN_F21R2_FB31_Msk (0x1U << CAN_F21R2_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F21R2_FB31 CAN_F21R2_FB31_Msk /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F22R2 register ******************/
+#define CAN_F22R2_FB0_Pos (0U)
+#define CAN_F22R2_FB0_Msk (0x1U << CAN_F22R2_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F22R2_FB0 CAN_F22R2_FB0_Msk /*!< Filter bit 0 */
+#define CAN_F22R2_FB1_Pos (1U)
+#define CAN_F22R2_FB1_Msk (0x1U << CAN_F22R2_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F22R2_FB1 CAN_F22R2_FB1_Msk /*!< Filter bit 1 */
+#define CAN_F22R2_FB2_Pos (2U)
+#define CAN_F22R2_FB2_Msk (0x1U << CAN_F22R2_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F22R2_FB2 CAN_F22R2_FB2_Msk /*!< Filter bit 2 */
+#define CAN_F22R2_FB3_Pos (3U)
+#define CAN_F22R2_FB3_Msk (0x1U << CAN_F22R2_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F22R2_FB3 CAN_F22R2_FB3_Msk /*!< Filter bit 3 */
+#define CAN_F22R2_FB4_Pos (4U)
+#define CAN_F22R2_FB4_Msk (0x1U << CAN_F22R2_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F22R2_FB4 CAN_F22R2_FB4_Msk /*!< Filter bit 4 */
+#define CAN_F22R2_FB5_Pos (5U)
+#define CAN_F22R2_FB5_Msk (0x1U << CAN_F22R2_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F22R2_FB5 CAN_F22R2_FB5_Msk /*!< Filter bit 5 */
+#define CAN_F22R2_FB6_Pos (6U)
+#define CAN_F22R2_FB6_Msk (0x1U << CAN_F22R2_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F22R2_FB6 CAN_F22R2_FB6_Msk /*!< Filter bit 6 */
+#define CAN_F22R2_FB7_Pos (7U)
+#define CAN_F22R2_FB7_Msk (0x1U << CAN_F22R2_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F22R2_FB7 CAN_F22R2_FB7_Msk /*!< Filter bit 7 */
+#define CAN_F22R2_FB8_Pos (8U)
+#define CAN_F22R2_FB8_Msk (0x1U << CAN_F22R2_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F22R2_FB8 CAN_F22R2_FB8_Msk /*!< Filter bit 8 */
+#define CAN_F22R2_FB9_Pos (9U)
+#define CAN_F22R2_FB9_Msk (0x1U << CAN_F22R2_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F22R2_FB9 CAN_F22R2_FB9_Msk /*!< Filter bit 9 */
+#define CAN_F22R2_FB10_Pos (10U)
+#define CAN_F22R2_FB10_Msk (0x1U << CAN_F22R2_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F22R2_FB10 CAN_F22R2_FB10_Msk /*!< Filter bit 10 */
+#define CAN_F22R2_FB11_Pos (11U)
+#define CAN_F22R2_FB11_Msk (0x1U << CAN_F22R2_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F22R2_FB11 CAN_F22R2_FB11_Msk /*!< Filter bit 11 */
+#define CAN_F22R2_FB12_Pos (12U)
+#define CAN_F22R2_FB12_Msk (0x1U << CAN_F22R2_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F22R2_FB12 CAN_F22R2_FB12_Msk /*!< Filter bit 12 */
+#define CAN_F22R2_FB13_Pos (13U)
+#define CAN_F22R2_FB13_Msk (0x1U << CAN_F22R2_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F22R2_FB13 CAN_F22R2_FB13_Msk /*!< Filter bit 13 */
+#define CAN_F22R2_FB14_Pos (14U)
+#define CAN_F22R2_FB14_Msk (0x1U << CAN_F22R2_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F22R2_FB14 CAN_F22R2_FB14_Msk /*!< Filter bit 14 */
+#define CAN_F22R2_FB15_Pos (15U)
+#define CAN_F22R2_FB15_Msk (0x1U << CAN_F22R2_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F22R2_FB15 CAN_F22R2_FB15_Msk /*!< Filter bit 15 */
+#define CAN_F22R2_FB16_Pos (16U)
+#define CAN_F22R2_FB16_Msk (0x1U << CAN_F22R2_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F22R2_FB16 CAN_F22R2_FB16_Msk /*!< Filter bit 16 */
+#define CAN_F22R2_FB17_Pos (17U)
+#define CAN_F22R2_FB17_Msk (0x1U << CAN_F22R2_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F22R2_FB17 CAN_F22R2_FB17_Msk /*!< Filter bit 17 */
+#define CAN_F22R2_FB18_Pos (18U)
+#define CAN_F22R2_FB18_Msk (0x1U << CAN_F22R2_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F22R2_FB18 CAN_F22R2_FB18_Msk /*!< Filter bit 18 */
+#define CAN_F22R2_FB19_Pos (19U)
+#define CAN_F22R2_FB19_Msk (0x1U << CAN_F22R2_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F22R2_FB19 CAN_F22R2_FB19_Msk /*!< Filter bit 19 */
+#define CAN_F22R2_FB20_Pos (20U)
+#define CAN_F22R2_FB20_Msk (0x1U << CAN_F22R2_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F22R2_FB20 CAN_F22R2_FB20_Msk /*!< Filter bit 20 */
+#define CAN_F22R2_FB21_Pos (21U)
+#define CAN_F22R2_FB21_Msk (0x1U << CAN_F22R2_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F22R2_FB21 CAN_F22R2_FB21_Msk /*!< Filter bit 21 */
+#define CAN_F22R2_FB22_Pos (22U)
+#define CAN_F22R2_FB22_Msk (0x1U << CAN_F22R2_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F22R2_FB22 CAN_F22R2_FB22_Msk /*!< Filter bit 22 */
+#define CAN_F22R2_FB23_Pos (23U)
+#define CAN_F22R2_FB23_Msk (0x1U << CAN_F22R2_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F22R2_FB23 CAN_F22R2_FB23_Msk /*!< Filter bit 23 */
+#define CAN_F22R2_FB24_Pos (24U)
+#define CAN_F22R2_FB24_Msk (0x1U << CAN_F22R2_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F22R2_FB24 CAN_F22R2_FB24_Msk /*!< Filter bit 24 */
+#define CAN_F22R2_FB25_Pos (25U)
+#define CAN_F22R2_FB25_Msk (0x1U << CAN_F22R2_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F22R2_FB25 CAN_F22R2_FB25_Msk /*!< Filter bit 25 */
+#define CAN_F22R2_FB26_Pos (26U)
+#define CAN_F22R2_FB26_Msk (0x1U << CAN_F22R2_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F22R2_FB26 CAN_F22R2_FB26_Msk /*!< Filter bit 26 */
+#define CAN_F22R2_FB27_Pos (27U)
+#define CAN_F22R2_FB27_Msk (0x1U << CAN_F22R2_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F22R2_FB27 CAN_F22R2_FB27_Msk /*!< Filter bit 27 */
+#define CAN_F22R2_FB28_Pos (28U)
+#define CAN_F22R2_FB28_Msk (0x1U << CAN_F22R2_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F22R2_FB28 CAN_F22R2_FB28_Msk /*!< Filter bit 28 */
+#define CAN_F22R2_FB29_Pos (29U)
+#define CAN_F22R2_FB29_Msk (0x1U << CAN_F22R2_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F22R2_FB29 CAN_F22R2_FB29_Msk /*!< Filter bit 29 */
+#define CAN_F22R2_FB30_Pos (30U)
+#define CAN_F22R2_FB30_Msk (0x1U << CAN_F22R2_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F22R2_FB30 CAN_F22R2_FB30_Msk /*!< Filter bit 30 */
+#define CAN_F22R2_FB31_Pos (31U)
+#define CAN_F22R2_FB31_Msk (0x1U << CAN_F22R2_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F22R2_FB31 CAN_F22R2_FB31_Msk /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F23R2 register ******************/
+#define CAN_F23R2_FB0_Pos (0U)
+#define CAN_F23R2_FB0_Msk (0x1U << CAN_F23R2_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F23R2_FB0 CAN_F23R2_FB0_Msk /*!< Filter bit 0 */
+#define CAN_F23R2_FB1_Pos (1U)
+#define CAN_F23R2_FB1_Msk (0x1U << CAN_F23R2_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F23R2_FB1 CAN_F23R2_FB1_Msk /*!< Filter bit 1 */
+#define CAN_F23R2_FB2_Pos (2U)
+#define CAN_F23R2_FB2_Msk (0x1U << CAN_F23R2_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F23R2_FB2 CAN_F23R2_FB2_Msk /*!< Filter bit 2 */
+#define CAN_F23R2_FB3_Pos (3U)
+#define CAN_F23R2_FB3_Msk (0x1U << CAN_F23R2_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F23R2_FB3 CAN_F23R2_FB3_Msk /*!< Filter bit 3 */
+#define CAN_F23R2_FB4_Pos (4U)
+#define CAN_F23R2_FB4_Msk (0x1U << CAN_F23R2_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F23R2_FB4 CAN_F23R2_FB4_Msk /*!< Filter bit 4 */
+#define CAN_F23R2_FB5_Pos (5U)
+#define CAN_F23R2_FB5_Msk (0x1U << CAN_F23R2_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F23R2_FB5 CAN_F23R2_FB5_Msk /*!< Filter bit 5 */
+#define CAN_F23R2_FB6_Pos (6U)
+#define CAN_F23R2_FB6_Msk (0x1U << CAN_F23R2_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F23R2_FB6 CAN_F23R2_FB6_Msk /*!< Filter bit 6 */
+#define CAN_F23R2_FB7_Pos (7U)
+#define CAN_F23R2_FB7_Msk (0x1U << CAN_F23R2_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F23R2_FB7 CAN_F23R2_FB7_Msk /*!< Filter bit 7 */
+#define CAN_F23R2_FB8_Pos (8U)
+#define CAN_F23R2_FB8_Msk (0x1U << CAN_F23R2_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F23R2_FB8 CAN_F23R2_FB8_Msk /*!< Filter bit 8 */
+#define CAN_F23R2_FB9_Pos (9U)
+#define CAN_F23R2_FB9_Msk (0x1U << CAN_F23R2_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F23R2_FB9 CAN_F23R2_FB9_Msk /*!< Filter bit 9 */
+#define CAN_F23R2_FB10_Pos (10U)
+#define CAN_F23R2_FB10_Msk (0x1U << CAN_F23R2_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F23R2_FB10 CAN_F23R2_FB10_Msk /*!< Filter bit 10 */
+#define CAN_F23R2_FB11_Pos (11U)
+#define CAN_F23R2_FB11_Msk (0x1U << CAN_F23R2_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F23R2_FB11 CAN_F23R2_FB11_Msk /*!< Filter bit 11 */
+#define CAN_F23R2_FB12_Pos (12U)
+#define CAN_F23R2_FB12_Msk (0x1U << CAN_F23R2_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F23R2_FB12 CAN_F23R2_FB12_Msk /*!< Filter bit 12 */
+#define CAN_F23R2_FB13_Pos (13U)
+#define CAN_F23R2_FB13_Msk (0x1U << CAN_F23R2_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F23R2_FB13 CAN_F23R2_FB13_Msk /*!< Filter bit 13 */
+#define CAN_F23R2_FB14_Pos (14U)
+#define CAN_F23R2_FB14_Msk (0x1U << CAN_F23R2_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F23R2_FB14 CAN_F23R2_FB14_Msk /*!< Filter bit 14 */
+#define CAN_F23R2_FB15_Pos (15U)
+#define CAN_F23R2_FB15_Msk (0x1U << CAN_F23R2_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F23R2_FB15 CAN_F23R2_FB15_Msk /*!< Filter bit 15 */
+#define CAN_F23R2_FB16_Pos (16U)
+#define CAN_F23R2_FB16_Msk (0x1U << CAN_F23R2_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F23R2_FB16 CAN_F23R2_FB16_Msk /*!< Filter bit 16 */
+#define CAN_F23R2_FB17_Pos (17U)
+#define CAN_F23R2_FB17_Msk (0x1U << CAN_F23R2_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F23R2_FB17 CAN_F23R2_FB17_Msk /*!< Filter bit 17 */
+#define CAN_F23R2_FB18_Pos (18U)
+#define CAN_F23R2_FB18_Msk (0x1U << CAN_F23R2_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F23R2_FB18 CAN_F23R2_FB18_Msk /*!< Filter bit 18 */
+#define CAN_F23R2_FB19_Pos (19U)
+#define CAN_F23R2_FB19_Msk (0x1U << CAN_F23R2_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F23R2_FB19 CAN_F23R2_FB19_Msk /*!< Filter bit 19 */
+#define CAN_F23R2_FB20_Pos (20U)
+#define CAN_F23R2_FB20_Msk (0x1U << CAN_F23R2_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F23R2_FB20 CAN_F23R2_FB20_Msk /*!< Filter bit 20 */
+#define CAN_F23R2_FB21_Pos (21U)
+#define CAN_F23R2_FB21_Msk (0x1U << CAN_F23R2_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F23R2_FB21 CAN_F23R2_FB21_Msk /*!< Filter bit 21 */
+#define CAN_F23R2_FB22_Pos (22U)
+#define CAN_F23R2_FB22_Msk (0x1U << CAN_F23R2_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F23R2_FB22 CAN_F23R2_FB22_Msk /*!< Filter bit 22 */
+#define CAN_F23R2_FB23_Pos (23U)
+#define CAN_F23R2_FB23_Msk (0x1U << CAN_F23R2_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F23R2_FB23 CAN_F23R2_FB23_Msk /*!< Filter bit 23 */
+#define CAN_F23R2_FB24_Pos (24U)
+#define CAN_F23R2_FB24_Msk (0x1U << CAN_F23R2_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F23R2_FB24 CAN_F23R2_FB24_Msk /*!< Filter bit 24 */
+#define CAN_F23R2_FB25_Pos (25U)
+#define CAN_F23R2_FB25_Msk (0x1U << CAN_F23R2_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F23R2_FB25 CAN_F23R2_FB25_Msk /*!< Filter bit 25 */
+#define CAN_F23R2_FB26_Pos (26U)
+#define CAN_F23R2_FB26_Msk (0x1U << CAN_F23R2_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F23R2_FB26 CAN_F23R2_FB26_Msk /*!< Filter bit 26 */
+#define CAN_F23R2_FB27_Pos (27U)
+#define CAN_F23R2_FB27_Msk (0x1U << CAN_F23R2_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F23R2_FB27 CAN_F23R2_FB27_Msk /*!< Filter bit 27 */
+#define CAN_F23R2_FB28_Pos (28U)
+#define CAN_F23R2_FB28_Msk (0x1U << CAN_F23R2_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F23R2_FB28 CAN_F23R2_FB28_Msk /*!< Filter bit 28 */
+#define CAN_F23R2_FB29_Pos (29U)
+#define CAN_F23R2_FB29_Msk (0x1U << CAN_F23R2_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F23R2_FB29 CAN_F23R2_FB29_Msk /*!< Filter bit 29 */
+#define CAN_F23R2_FB30_Pos (30U)
+#define CAN_F23R2_FB30_Msk (0x1U << CAN_F23R2_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F23R2_FB30 CAN_F23R2_FB30_Msk /*!< Filter bit 30 */
+#define CAN_F23R2_FB31_Pos (31U)
+#define CAN_F23R2_FB31_Msk (0x1U << CAN_F23R2_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F23R2_FB31 CAN_F23R2_FB31_Msk /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F24R2 register ******************/
+#define CAN_F24R2_FB0_Pos (0U)
+#define CAN_F24R2_FB0_Msk (0x1U << CAN_F24R2_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F24R2_FB0 CAN_F24R2_FB0_Msk /*!< Filter bit 0 */
+#define CAN_F24R2_FB1_Pos (1U)
+#define CAN_F24R2_FB1_Msk (0x1U << CAN_F24R2_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F24R2_FB1 CAN_F24R2_FB1_Msk /*!< Filter bit 1 */
+#define CAN_F24R2_FB2_Pos (2U)
+#define CAN_F24R2_FB2_Msk (0x1U << CAN_F24R2_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F24R2_FB2 CAN_F24R2_FB2_Msk /*!< Filter bit 2 */
+#define CAN_F24R2_FB3_Pos (3U)
+#define CAN_F24R2_FB3_Msk (0x1U << CAN_F24R2_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F24R2_FB3 CAN_F24R2_FB3_Msk /*!< Filter bit 3 */
+#define CAN_F24R2_FB4_Pos (4U)
+#define CAN_F24R2_FB4_Msk (0x1U << CAN_F24R2_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F24R2_FB4 CAN_F24R2_FB4_Msk /*!< Filter bit 4 */
+#define CAN_F24R2_FB5_Pos (5U)
+#define CAN_F24R2_FB5_Msk (0x1U << CAN_F24R2_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F24R2_FB5 CAN_F24R2_FB5_Msk /*!< Filter bit 5 */
+#define CAN_F24R2_FB6_Pos (6U)
+#define CAN_F24R2_FB6_Msk (0x1U << CAN_F24R2_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F24R2_FB6 CAN_F24R2_FB6_Msk /*!< Filter bit 6 */
+#define CAN_F24R2_FB7_Pos (7U)
+#define CAN_F24R2_FB7_Msk (0x1U << CAN_F24R2_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F24R2_FB7 CAN_F24R2_FB7_Msk /*!< Filter bit 7 */
+#define CAN_F24R2_FB8_Pos (8U)
+#define CAN_F24R2_FB8_Msk (0x1U << CAN_F24R2_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F24R2_FB8 CAN_F24R2_FB8_Msk /*!< Filter bit 8 */
+#define CAN_F24R2_FB9_Pos (9U)
+#define CAN_F24R2_FB9_Msk (0x1U << CAN_F24R2_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F24R2_FB9 CAN_F24R2_FB9_Msk /*!< Filter bit 9 */
+#define CAN_F24R2_FB10_Pos (10U)
+#define CAN_F24R2_FB10_Msk (0x1U << CAN_F24R2_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F24R2_FB10 CAN_F24R2_FB10_Msk /*!< Filter bit 10 */
+#define CAN_F24R2_FB11_Pos (11U)
+#define CAN_F24R2_FB11_Msk (0x1U << CAN_F24R2_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F24R2_FB11 CAN_F24R2_FB11_Msk /*!< Filter bit 11 */
+#define CAN_F24R2_FB12_Pos (12U)
+#define CAN_F24R2_FB12_Msk (0x1U << CAN_F24R2_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F24R2_FB12 CAN_F24R2_FB12_Msk /*!< Filter bit 12 */
+#define CAN_F24R2_FB13_Pos (13U)
+#define CAN_F24R2_FB13_Msk (0x1U << CAN_F24R2_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F24R2_FB13 CAN_F24R2_FB13_Msk /*!< Filter bit 13 */
+#define CAN_F24R2_FB14_Pos (14U)
+#define CAN_F24R2_FB14_Msk (0x1U << CAN_F24R2_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F24R2_FB14 CAN_F24R2_FB14_Msk /*!< Filter bit 14 */
+#define CAN_F24R2_FB15_Pos (15U)
+#define CAN_F24R2_FB15_Msk (0x1U << CAN_F24R2_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F24R2_FB15 CAN_F24R2_FB15_Msk /*!< Filter bit 15 */
+#define CAN_F24R2_FB16_Pos (16U)
+#define CAN_F24R2_FB16_Msk (0x1U << CAN_F24R2_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F24R2_FB16 CAN_F24R2_FB16_Msk /*!< Filter bit 16 */
+#define CAN_F24R2_FB17_Pos (17U)
+#define CAN_F24R2_FB17_Msk (0x1U << CAN_F24R2_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F24R2_FB17 CAN_F24R2_FB17_Msk /*!< Filter bit 17 */
+#define CAN_F24R2_FB18_Pos (18U)
+#define CAN_F24R2_FB18_Msk (0x1U << CAN_F24R2_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F24R2_FB18 CAN_F24R2_FB18_Msk /*!< Filter bit 18 */
+#define CAN_F24R2_FB19_Pos (19U)
+#define CAN_F24R2_FB19_Msk (0x1U << CAN_F24R2_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F24R2_FB19 CAN_F24R2_FB19_Msk /*!< Filter bit 19 */
+#define CAN_F24R2_FB20_Pos (20U)
+#define CAN_F24R2_FB20_Msk (0x1U << CAN_F24R2_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F24R2_FB20 CAN_F24R2_FB20_Msk /*!< Filter bit 20 */
+#define CAN_F24R2_FB21_Pos (21U)
+#define CAN_F24R2_FB21_Msk (0x1U << CAN_F24R2_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F24R2_FB21 CAN_F24R2_FB21_Msk /*!< Filter bit 21 */
+#define CAN_F24R2_FB22_Pos (22U)
+#define CAN_F24R2_FB22_Msk (0x1U << CAN_F24R2_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F24R2_FB22 CAN_F24R2_FB22_Msk /*!< Filter bit 22 */
+#define CAN_F24R2_FB23_Pos (23U)
+#define CAN_F24R2_FB23_Msk (0x1U << CAN_F24R2_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F24R2_FB23 CAN_F24R2_FB23_Msk /*!< Filter bit 23 */
+#define CAN_F24R2_FB24_Pos (24U)
+#define CAN_F24R2_FB24_Msk (0x1U << CAN_F24R2_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F24R2_FB24 CAN_F24R2_FB24_Msk /*!< Filter bit 24 */
+#define CAN_F24R2_FB25_Pos (25U)
+#define CAN_F24R2_FB25_Msk (0x1U << CAN_F24R2_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F24R2_FB25 CAN_F24R2_FB25_Msk /*!< Filter bit 25 */
+#define CAN_F24R2_FB26_Pos (26U)
+#define CAN_F24R2_FB26_Msk (0x1U << CAN_F24R2_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F24R2_FB26 CAN_F24R2_FB26_Msk /*!< Filter bit 26 */
+#define CAN_F24R2_FB27_Pos (27U)
+#define CAN_F24R2_FB27_Msk (0x1U << CAN_F24R2_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F24R2_FB27 CAN_F24R2_FB27_Msk /*!< Filter bit 27 */
+#define CAN_F24R2_FB28_Pos (28U)
+#define CAN_F24R2_FB28_Msk (0x1U << CAN_F24R2_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F24R2_FB28 CAN_F24R2_FB28_Msk /*!< Filter bit 28 */
+#define CAN_F24R2_FB29_Pos (29U)
+#define CAN_F24R2_FB29_Msk (0x1U << CAN_F24R2_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F24R2_FB29 CAN_F24R2_FB29_Msk /*!< Filter bit 29 */
+#define CAN_F24R2_FB30_Pos (30U)
+#define CAN_F24R2_FB30_Msk (0x1U << CAN_F24R2_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F24R2_FB30 CAN_F24R2_FB30_Msk /*!< Filter bit 30 */
+#define CAN_F24R2_FB31_Pos (31U)
+#define CAN_F24R2_FB31_Msk (0x1U << CAN_F24R2_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F24R2_FB31 CAN_F24R2_FB31_Msk /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F25R2 register ******************/
+#define CAN_F25R2_FB0_Pos (0U)
+#define CAN_F25R2_FB0_Msk (0x1U << CAN_F25R2_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F25R2_FB0 CAN_F25R2_FB0_Msk /*!< Filter bit 0 */
+#define CAN_F25R2_FB1_Pos (1U)
+#define CAN_F25R2_FB1_Msk (0x1U << CAN_F25R2_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F25R2_FB1 CAN_F25R2_FB1_Msk /*!< Filter bit 1 */
+#define CAN_F25R2_FB2_Pos (2U)
+#define CAN_F25R2_FB2_Msk (0x1U << CAN_F25R2_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F25R2_FB2 CAN_F25R2_FB2_Msk /*!< Filter bit 2 */
+#define CAN_F25R2_FB3_Pos (3U)
+#define CAN_F25R2_FB3_Msk (0x1U << CAN_F25R2_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F25R2_FB3 CAN_F25R2_FB3_Msk /*!< Filter bit 3 */
+#define CAN_F25R2_FB4_Pos (4U)
+#define CAN_F25R2_FB4_Msk (0x1U << CAN_F25R2_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F25R2_FB4 CAN_F25R2_FB4_Msk /*!< Filter bit 4 */
+#define CAN_F25R2_FB5_Pos (5U)
+#define CAN_F25R2_FB5_Msk (0x1U << CAN_F25R2_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F25R2_FB5 CAN_F25R2_FB5_Msk /*!< Filter bit 5 */
+#define CAN_F25R2_FB6_Pos (6U)
+#define CAN_F25R2_FB6_Msk (0x1U << CAN_F25R2_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F25R2_FB6 CAN_F25R2_FB6_Msk /*!< Filter bit 6 */
+#define CAN_F25R2_FB7_Pos (7U)
+#define CAN_F25R2_FB7_Msk (0x1U << CAN_F25R2_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F25R2_FB7 CAN_F25R2_FB7_Msk /*!< Filter bit 7 */
+#define CAN_F25R2_FB8_Pos (8U)
+#define CAN_F25R2_FB8_Msk (0x1U << CAN_F25R2_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F25R2_FB8 CAN_F25R2_FB8_Msk /*!< Filter bit 8 */
+#define CAN_F25R2_FB9_Pos (9U)
+#define CAN_F25R2_FB9_Msk (0x1U << CAN_F25R2_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F25R2_FB9 CAN_F25R2_FB9_Msk /*!< Filter bit 9 */
+#define CAN_F25R2_FB10_Pos (10U)
+#define CAN_F25R2_FB10_Msk (0x1U << CAN_F25R2_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F25R2_FB10 CAN_F25R2_FB10_Msk /*!< Filter bit 10 */
+#define CAN_F25R2_FB11_Pos (11U)
+#define CAN_F25R2_FB11_Msk (0x1U << CAN_F25R2_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F25R2_FB11 CAN_F25R2_FB11_Msk /*!< Filter bit 11 */
+#define CAN_F25R2_FB12_Pos (12U)
+#define CAN_F25R2_FB12_Msk (0x1U << CAN_F25R2_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F25R2_FB12 CAN_F25R2_FB12_Msk /*!< Filter bit 12 */
+#define CAN_F25R2_FB13_Pos (13U)
+#define CAN_F25R2_FB13_Msk (0x1U << CAN_F25R2_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F25R2_FB13 CAN_F25R2_FB13_Msk /*!< Filter bit 13 */
+#define CAN_F25R2_FB14_Pos (14U)
+#define CAN_F25R2_FB14_Msk (0x1U << CAN_F25R2_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F25R2_FB14 CAN_F25R2_FB14_Msk /*!< Filter bit 14 */
+#define CAN_F25R2_FB15_Pos (15U)
+#define CAN_F25R2_FB15_Msk (0x1U << CAN_F25R2_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F25R2_FB15 CAN_F25R2_FB15_Msk /*!< Filter bit 15 */
+#define CAN_F25R2_FB16_Pos (16U)
+#define CAN_F25R2_FB16_Msk (0x1U << CAN_F25R2_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F25R2_FB16 CAN_F25R2_FB16_Msk /*!< Filter bit 16 */
+#define CAN_F25R2_FB17_Pos (17U)
+#define CAN_F25R2_FB17_Msk (0x1U << CAN_F25R2_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F25R2_FB17 CAN_F25R2_FB17_Msk /*!< Filter bit 17 */
+#define CAN_F25R2_FB18_Pos (18U)
+#define CAN_F25R2_FB18_Msk (0x1U << CAN_F25R2_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F25R2_FB18 CAN_F25R2_FB18_Msk /*!< Filter bit 18 */
+#define CAN_F25R2_FB19_Pos (19U)
+#define CAN_F25R2_FB19_Msk (0x1U << CAN_F25R2_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F25R2_FB19 CAN_F25R2_FB19_Msk /*!< Filter bit 19 */
+#define CAN_F25R2_FB20_Pos (20U)
+#define CAN_F25R2_FB20_Msk (0x1U << CAN_F25R2_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F25R2_FB20 CAN_F25R2_FB20_Msk /*!< Filter bit 20 */
+#define CAN_F25R2_FB21_Pos (21U)
+#define CAN_F25R2_FB21_Msk (0x1U << CAN_F25R2_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F25R2_FB21 CAN_F25R2_FB21_Msk /*!< Filter bit 21 */
+#define CAN_F25R2_FB22_Pos (22U)
+#define CAN_F25R2_FB22_Msk (0x1U << CAN_F25R2_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F25R2_FB22 CAN_F25R2_FB22_Msk /*!< Filter bit 22 */
+#define CAN_F25R2_FB23_Pos (23U)
+#define CAN_F25R2_FB23_Msk (0x1U << CAN_F25R2_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F25R2_FB23 CAN_F25R2_FB23_Msk /*!< Filter bit 23 */
+#define CAN_F25R2_FB24_Pos (24U)
+#define CAN_F25R2_FB24_Msk (0x1U << CAN_F25R2_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F25R2_FB24 CAN_F25R2_FB24_Msk /*!< Filter bit 24 */
+#define CAN_F25R2_FB25_Pos (25U)
+#define CAN_F25R2_FB25_Msk (0x1U << CAN_F25R2_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F25R2_FB25 CAN_F25R2_FB25_Msk /*!< Filter bit 25 */
+#define CAN_F25R2_FB26_Pos (26U)
+#define CAN_F25R2_FB26_Msk (0x1U << CAN_F25R2_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F25R2_FB26 CAN_F25R2_FB26_Msk /*!< Filter bit 26 */
+#define CAN_F25R2_FB27_Pos (27U)
+#define CAN_F25R2_FB27_Msk (0x1U << CAN_F25R2_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F25R2_FB27 CAN_F25R2_FB27_Msk /*!< Filter bit 27 */
+#define CAN_F25R2_FB28_Pos (28U)
+#define CAN_F25R2_FB28_Msk (0x1U << CAN_F25R2_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F25R2_FB28 CAN_F25R2_FB28_Msk /*!< Filter bit 28 */
+#define CAN_F25R2_FB29_Pos (29U)
+#define CAN_F25R2_FB29_Msk (0x1U << CAN_F25R2_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F25R2_FB29 CAN_F25R2_FB29_Msk /*!< Filter bit 29 */
+#define CAN_F25R2_FB30_Pos (30U)
+#define CAN_F25R2_FB30_Msk (0x1U << CAN_F25R2_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F25R2_FB30 CAN_F25R2_FB30_Msk /*!< Filter bit 30 */
+#define CAN_F25R2_FB31_Pos (31U)
+#define CAN_F25R2_FB31_Msk (0x1U << CAN_F25R2_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F25R2_FB31 CAN_F25R2_FB31_Msk /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F26R2 register ******************/
+#define CAN_F26R2_FB0_Pos (0U)
+#define CAN_F26R2_FB0_Msk (0x1U << CAN_F26R2_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F26R2_FB0 CAN_F26R2_FB0_Msk /*!< Filter bit 0 */
+#define CAN_F26R2_FB1_Pos (1U)
+#define CAN_F26R2_FB1_Msk (0x1U << CAN_F26R2_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F26R2_FB1 CAN_F26R2_FB1_Msk /*!< Filter bit 1 */
+#define CAN_F26R2_FB2_Pos (2U)
+#define CAN_F26R2_FB2_Msk (0x1U << CAN_F26R2_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F26R2_FB2 CAN_F26R2_FB2_Msk /*!< Filter bit 2 */
+#define CAN_F26R2_FB3_Pos (3U)
+#define CAN_F26R2_FB3_Msk (0x1U << CAN_F26R2_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F26R2_FB3 CAN_F26R2_FB3_Msk /*!< Filter bit 3 */
+#define CAN_F26R2_FB4_Pos (4U)
+#define CAN_F26R2_FB4_Msk (0x1U << CAN_F26R2_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F26R2_FB4 CAN_F26R2_FB4_Msk /*!< Filter bit 4 */
+#define CAN_F26R2_FB5_Pos (5U)
+#define CAN_F26R2_FB5_Msk (0x1U << CAN_F26R2_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F26R2_FB5 CAN_F26R2_FB5_Msk /*!< Filter bit 5 */
+#define CAN_F26R2_FB6_Pos (6U)
+#define CAN_F26R2_FB6_Msk (0x1U << CAN_F26R2_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F26R2_FB6 CAN_F26R2_FB6_Msk /*!< Filter bit 6 */
+#define CAN_F26R2_FB7_Pos (7U)
+#define CAN_F26R2_FB7_Msk (0x1U << CAN_F26R2_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F26R2_FB7 CAN_F26R2_FB7_Msk /*!< Filter bit 7 */
+#define CAN_F26R2_FB8_Pos (8U)
+#define CAN_F26R2_FB8_Msk (0x1U << CAN_F26R2_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F26R2_FB8 CAN_F26R2_FB8_Msk /*!< Filter bit 8 */
+#define CAN_F26R2_FB9_Pos (9U)
+#define CAN_F26R2_FB9_Msk (0x1U << CAN_F26R2_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F26R2_FB9 CAN_F26R2_FB9_Msk /*!< Filter bit 9 */
+#define CAN_F26R2_FB10_Pos (10U)
+#define CAN_F26R2_FB10_Msk (0x1U << CAN_F26R2_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F26R2_FB10 CAN_F26R2_FB10_Msk /*!< Filter bit 10 */
+#define CAN_F26R2_FB11_Pos (11U)
+#define CAN_F26R2_FB11_Msk (0x1U << CAN_F26R2_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F26R2_FB11 CAN_F26R2_FB11_Msk /*!< Filter bit 11 */
+#define CAN_F26R2_FB12_Pos (12U)
+#define CAN_F26R2_FB12_Msk (0x1U << CAN_F26R2_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F26R2_FB12 CAN_F26R2_FB12_Msk /*!< Filter bit 12 */
+#define CAN_F26R2_FB13_Pos (13U)
+#define CAN_F26R2_FB13_Msk (0x1U << CAN_F26R2_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F26R2_FB13 CAN_F26R2_FB13_Msk /*!< Filter bit 13 */
+#define CAN_F26R2_FB14_Pos (14U)
+#define CAN_F26R2_FB14_Msk (0x1U << CAN_F26R2_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F26R2_FB14 CAN_F26R2_FB14_Msk /*!< Filter bit 14 */
+#define CAN_F26R2_FB15_Pos (15U)
+#define CAN_F26R2_FB15_Msk (0x1U << CAN_F26R2_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F26R2_FB15 CAN_F26R2_FB15_Msk /*!< Filter bit 15 */
+#define CAN_F26R2_FB16_Pos (16U)
+#define CAN_F26R2_FB16_Msk (0x1U << CAN_F26R2_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F26R2_FB16 CAN_F26R2_FB16_Msk /*!< Filter bit 16 */
+#define CAN_F26R2_FB17_Pos (17U)
+#define CAN_F26R2_FB17_Msk (0x1U << CAN_F26R2_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F26R2_FB17 CAN_F26R2_FB17_Msk /*!< Filter bit 17 */
+#define CAN_F26R2_FB18_Pos (18U)
+#define CAN_F26R2_FB18_Msk (0x1U << CAN_F26R2_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F26R2_FB18 CAN_F26R2_FB18_Msk /*!< Filter bit 18 */
+#define CAN_F26R2_FB19_Pos (19U)
+#define CAN_F26R2_FB19_Msk (0x1U << CAN_F26R2_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F26R2_FB19 CAN_F26R2_FB19_Msk /*!< Filter bit 19 */
+#define CAN_F26R2_FB20_Pos (20U)
+#define CAN_F26R2_FB20_Msk (0x1U << CAN_F26R2_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F26R2_FB20 CAN_F26R2_FB20_Msk /*!< Filter bit 20 */
+#define CAN_F26R2_FB21_Pos (21U)
+#define CAN_F26R2_FB21_Msk (0x1U << CAN_F26R2_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F26R2_FB21 CAN_F26R2_FB21_Msk /*!< Filter bit 21 */
+#define CAN_F26R2_FB22_Pos (22U)
+#define CAN_F26R2_FB22_Msk (0x1U << CAN_F26R2_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F26R2_FB22 CAN_F26R2_FB22_Msk /*!< Filter bit 22 */
+#define CAN_F26R2_FB23_Pos (23U)
+#define CAN_F26R2_FB23_Msk (0x1U << CAN_F26R2_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F26R2_FB23 CAN_F26R2_FB23_Msk /*!< Filter bit 23 */
+#define CAN_F26R2_FB24_Pos (24U)
+#define CAN_F26R2_FB24_Msk (0x1U << CAN_F26R2_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F26R2_FB24 CAN_F26R2_FB24_Msk /*!< Filter bit 24 */
+#define CAN_F26R2_FB25_Pos (25U)
+#define CAN_F26R2_FB25_Msk (0x1U << CAN_F26R2_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F26R2_FB25 CAN_F26R2_FB25_Msk /*!< Filter bit 25 */
+#define CAN_F26R2_FB26_Pos (26U)
+#define CAN_F26R2_FB26_Msk (0x1U << CAN_F26R2_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F26R2_FB26 CAN_F26R2_FB26_Msk /*!< Filter bit 26 */
+#define CAN_F26R2_FB27_Pos (27U)
+#define CAN_F26R2_FB27_Msk (0x1U << CAN_F26R2_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F26R2_FB27 CAN_F26R2_FB27_Msk /*!< Filter bit 27 */
+#define CAN_F26R2_FB28_Pos (28U)
+#define CAN_F26R2_FB28_Msk (0x1U << CAN_F26R2_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F26R2_FB28 CAN_F26R2_FB28_Msk /*!< Filter bit 28 */
+#define CAN_F26R2_FB29_Pos (29U)
+#define CAN_F26R2_FB29_Msk (0x1U << CAN_F26R2_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F26R2_FB29 CAN_F26R2_FB29_Msk /*!< Filter bit 29 */
+#define CAN_F26R2_FB30_Pos (30U)
+#define CAN_F26R2_FB30_Msk (0x1U << CAN_F26R2_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F26R2_FB30 CAN_F26R2_FB30_Msk /*!< Filter bit 30 */
+#define CAN_F26R2_FB31_Pos (31U)
+#define CAN_F26R2_FB31_Msk (0x1U << CAN_F26R2_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F26R2_FB31 CAN_F26R2_FB31_Msk /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F27R2 register ******************/
+#define CAN_F27R2_FB0_Pos (0U)
+#define CAN_F27R2_FB0_Msk (0x1U << CAN_F27R2_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F27R2_FB0 CAN_F27R2_FB0_Msk /*!< Filter bit 0 */
+#define CAN_F27R2_FB1_Pos (1U)
+#define CAN_F27R2_FB1_Msk (0x1U << CAN_F27R2_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F27R2_FB1 CAN_F27R2_FB1_Msk /*!< Filter bit 1 */
+#define CAN_F27R2_FB2_Pos (2U)
+#define CAN_F27R2_FB2_Msk (0x1U << CAN_F27R2_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F27R2_FB2 CAN_F27R2_FB2_Msk /*!< Filter bit 2 */
+#define CAN_F27R2_FB3_Pos (3U)
+#define CAN_F27R2_FB3_Msk (0x1U << CAN_F27R2_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F27R2_FB3 CAN_F27R2_FB3_Msk /*!< Filter bit 3 */
+#define CAN_F27R2_FB4_Pos (4U)
+#define CAN_F27R2_FB4_Msk (0x1U << CAN_F27R2_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F27R2_FB4 CAN_F27R2_FB4_Msk /*!< Filter bit 4 */
+#define CAN_F27R2_FB5_Pos (5U)
+#define CAN_F27R2_FB5_Msk (0x1U << CAN_F27R2_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F27R2_FB5 CAN_F27R2_FB5_Msk /*!< Filter bit 5 */
+#define CAN_F27R2_FB6_Pos (6U)
+#define CAN_F27R2_FB6_Msk (0x1U << CAN_F27R2_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F27R2_FB6 CAN_F27R2_FB6_Msk /*!< Filter bit 6 */
+#define CAN_F27R2_FB7_Pos (7U)
+#define CAN_F27R2_FB7_Msk (0x1U << CAN_F27R2_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F27R2_FB7 CAN_F27R2_FB7_Msk /*!< Filter bit 7 */
+#define CAN_F27R2_FB8_Pos (8U)
+#define CAN_F27R2_FB8_Msk (0x1U << CAN_F27R2_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F27R2_FB8 CAN_F27R2_FB8_Msk /*!< Filter bit 8 */
+#define CAN_F27R2_FB9_Pos (9U)
+#define CAN_F27R2_FB9_Msk (0x1U << CAN_F27R2_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F27R2_FB9 CAN_F27R2_FB9_Msk /*!< Filter bit 9 */
+#define CAN_F27R2_FB10_Pos (10U)
+#define CAN_F27R2_FB10_Msk (0x1U << CAN_F27R2_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F27R2_FB10 CAN_F27R2_FB10_Msk /*!< Filter bit 10 */
+#define CAN_F27R2_FB11_Pos (11U)
+#define CAN_F27R2_FB11_Msk (0x1U << CAN_F27R2_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F27R2_FB11 CAN_F27R2_FB11_Msk /*!< Filter bit 11 */
+#define CAN_F27R2_FB12_Pos (12U)
+#define CAN_F27R2_FB12_Msk (0x1U << CAN_F27R2_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F27R2_FB12 CAN_F27R2_FB12_Msk /*!< Filter bit 12 */
+#define CAN_F27R2_FB13_Pos (13U)
+#define CAN_F27R2_FB13_Msk (0x1U << CAN_F27R2_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F27R2_FB13 CAN_F27R2_FB13_Msk /*!< Filter bit 13 */
+#define CAN_F27R2_FB14_Pos (14U)
+#define CAN_F27R2_FB14_Msk (0x1U << CAN_F27R2_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F27R2_FB14 CAN_F27R2_FB14_Msk /*!< Filter bit 14 */
+#define CAN_F27R2_FB15_Pos (15U)
+#define CAN_F27R2_FB15_Msk (0x1U << CAN_F27R2_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F27R2_FB15 CAN_F27R2_FB15_Msk /*!< Filter bit 15 */
+#define CAN_F27R2_FB16_Pos (16U)
+#define CAN_F27R2_FB16_Msk (0x1U << CAN_F27R2_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F27R2_FB16 CAN_F27R2_FB16_Msk /*!< Filter bit 16 */
+#define CAN_F27R2_FB17_Pos (17U)
+#define CAN_F27R2_FB17_Msk (0x1U << CAN_F27R2_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F27R2_FB17 CAN_F27R2_FB17_Msk /*!< Filter bit 17 */
+#define CAN_F27R2_FB18_Pos (18U)
+#define CAN_F27R2_FB18_Msk (0x1U << CAN_F27R2_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F27R2_FB18 CAN_F27R2_FB18_Msk /*!< Filter bit 18 */
+#define CAN_F27R2_FB19_Pos (19U)
+#define CAN_F27R2_FB19_Msk (0x1U << CAN_F27R2_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F27R2_FB19 CAN_F27R2_FB19_Msk /*!< Filter bit 19 */
+#define CAN_F27R2_FB20_Pos (20U)
+#define CAN_F27R2_FB20_Msk (0x1U << CAN_F27R2_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F27R2_FB20 CAN_F27R2_FB20_Msk /*!< Filter bit 20 */
+#define CAN_F27R2_FB21_Pos (21U)
+#define CAN_F27R2_FB21_Msk (0x1U << CAN_F27R2_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F27R2_FB21 CAN_F27R2_FB21_Msk /*!< Filter bit 21 */
+#define CAN_F27R2_FB22_Pos (22U)
+#define CAN_F27R2_FB22_Msk (0x1U << CAN_F27R2_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F27R2_FB22 CAN_F27R2_FB22_Msk /*!< Filter bit 22 */
+#define CAN_F27R2_FB23_Pos (23U)
+#define CAN_F27R2_FB23_Msk (0x1U << CAN_F27R2_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F27R2_FB23 CAN_F27R2_FB23_Msk /*!< Filter bit 23 */
+#define CAN_F27R2_FB24_Pos (24U)
+#define CAN_F27R2_FB24_Msk (0x1U << CAN_F27R2_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F27R2_FB24 CAN_F27R2_FB24_Msk /*!< Filter bit 24 */
+#define CAN_F27R2_FB25_Pos (25U)
+#define CAN_F27R2_FB25_Msk (0x1U << CAN_F27R2_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F27R2_FB25 CAN_F27R2_FB25_Msk /*!< Filter bit 25 */
+#define CAN_F27R2_FB26_Pos (26U)
+#define CAN_F27R2_FB26_Msk (0x1U << CAN_F27R2_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F27R2_FB26 CAN_F27R2_FB26_Msk /*!< Filter bit 26 */
+#define CAN_F27R2_FB27_Pos (27U)
+#define CAN_F27R2_FB27_Msk (0x1U << CAN_F27R2_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F27R2_FB27 CAN_F27R2_FB27_Msk /*!< Filter bit 27 */
+#define CAN_F27R2_FB28_Pos (28U)
+#define CAN_F27R2_FB28_Msk (0x1U << CAN_F27R2_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F27R2_FB28 CAN_F27R2_FB28_Msk /*!< Filter bit 28 */
+#define CAN_F27R2_FB29_Pos (29U)
+#define CAN_F27R2_FB29_Msk (0x1U << CAN_F27R2_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F27R2_FB29 CAN_F27R2_FB29_Msk /*!< Filter bit 29 */
+#define CAN_F27R2_FB30_Pos (30U)
+#define CAN_F27R2_FB30_Msk (0x1U << CAN_F27R2_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F27R2_FB30 CAN_F27R2_FB30_Msk /*!< Filter bit 30 */
+#define CAN_F27R2_FB31_Pos (31U)
+#define CAN_F27R2_FB31_Msk (0x1U << CAN_F27R2_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F27R2_FB31 CAN_F27R2_FB31_Msk /*!< Filter bit 31 */
+
+/******************************************************************************/
+/* */
+/* Serial Peripheral Interface */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for SPI_CR1 register ********************/
+#define SPI_CR1_CPHA_Pos (0U)
+#define SPI_CR1_CPHA_Msk (0x1U << SPI_CR1_CPHA_Pos) /*!< 0x00000001 */
+#define SPI_CR1_CPHA SPI_CR1_CPHA_Msk /*!< Clock Phase */
+#define SPI_CR1_CPOL_Pos (1U)
+#define SPI_CR1_CPOL_Msk (0x1U << SPI_CR1_CPOL_Pos) /*!< 0x00000002 */
+#define SPI_CR1_CPOL SPI_CR1_CPOL_Msk /*!< Clock Polarity */
+#define SPI_CR1_MSTR_Pos (2U)
+#define SPI_CR1_MSTR_Msk (0x1U << SPI_CR1_MSTR_Pos) /*!< 0x00000004 */
+#define SPI_CR1_MSTR SPI_CR1_MSTR_Msk /*!< Master Selection */
+
+#define SPI_CR1_BR_Pos (3U)
+#define SPI_CR1_BR_Msk (0x7U << SPI_CR1_BR_Pos) /*!< 0x00000038 */
+#define SPI_CR1_BR SPI_CR1_BR_Msk /*!< BR[2:0] bits (Baud Rate Control) */
+#define SPI_CR1_BR_0 (0x1U << SPI_CR1_BR_Pos) /*!< 0x00000008 */
+#define SPI_CR1_BR_1 (0x2U << SPI_CR1_BR_Pos) /*!< 0x00000010 */
+#define SPI_CR1_BR_2 (0x4U << SPI_CR1_BR_Pos) /*!< 0x00000020 */
+
+#define SPI_CR1_SPE_Pos (6U)
+#define SPI_CR1_SPE_Msk (0x1U << SPI_CR1_SPE_Pos) /*!< 0x00000040 */
+#define SPI_CR1_SPE SPI_CR1_SPE_Msk /*!< SPI Enable */
+#define SPI_CR1_LSBFIRST_Pos (7U)
+#define SPI_CR1_LSBFIRST_Msk (0x1U << SPI_CR1_LSBFIRST_Pos) /*!< 0x00000080 */
+#define SPI_CR1_LSBFIRST SPI_CR1_LSBFIRST_Msk /*!< Frame Format */
+#define SPI_CR1_SSI_Pos (8U)
+#define SPI_CR1_SSI_Msk (0x1U << SPI_CR1_SSI_Pos) /*!< 0x00000100 */
+#define SPI_CR1_SSI SPI_CR1_SSI_Msk /*!< Internal slave select */
+#define SPI_CR1_SSM_Pos (9U)
+#define SPI_CR1_SSM_Msk (0x1U << SPI_CR1_SSM_Pos) /*!< 0x00000200 */
+#define SPI_CR1_SSM SPI_CR1_SSM_Msk /*!< Software slave management */
+#define SPI_CR1_RXONLY_Pos (10U)
+#define SPI_CR1_RXONLY_Msk (0x1U << SPI_CR1_RXONLY_Pos) /*!< 0x00000400 */
+#define SPI_CR1_RXONLY SPI_CR1_RXONLY_Msk /*!< Receive only */
+#define SPI_CR1_DFF_Pos (11U)
+#define SPI_CR1_DFF_Msk (0x1U << SPI_CR1_DFF_Pos) /*!< 0x00000800 */
+#define SPI_CR1_DFF SPI_CR1_DFF_Msk /*!< Data Frame Format */
+#define SPI_CR1_CRCNEXT_Pos (12U)
+#define SPI_CR1_CRCNEXT_Msk (0x1U << SPI_CR1_CRCNEXT_Pos) /*!< 0x00001000 */
+#define SPI_CR1_CRCNEXT SPI_CR1_CRCNEXT_Msk /*!< Transmit CRC next */
+#define SPI_CR1_CRCEN_Pos (13U)
+#define SPI_CR1_CRCEN_Msk (0x1U << SPI_CR1_CRCEN_Pos) /*!< 0x00002000 */
+#define SPI_CR1_CRCEN SPI_CR1_CRCEN_Msk /*!< Hardware CRC calculation enable */
+#define SPI_CR1_BIDIOE_Pos (14U)
+#define SPI_CR1_BIDIOE_Msk (0x1U << SPI_CR1_BIDIOE_Pos) /*!< 0x00004000 */
+#define SPI_CR1_BIDIOE SPI_CR1_BIDIOE_Msk /*!< Output enable in bidirectional mode */
+#define SPI_CR1_BIDIMODE_Pos (15U)
+#define SPI_CR1_BIDIMODE_Msk (0x1U << SPI_CR1_BIDIMODE_Pos) /*!< 0x00008000 */
+#define SPI_CR1_BIDIMODE SPI_CR1_BIDIMODE_Msk /*!< Bidirectional data mode enable */
+
+/******************* Bit definition for SPI_CR2 register ********************/
+#define SPI_CR2_RXDMAEN_Pos (0U)
+#define SPI_CR2_RXDMAEN_Msk (0x1U << SPI_CR2_RXDMAEN_Pos) /*!< 0x00000001 */
+#define SPI_CR2_RXDMAEN SPI_CR2_RXDMAEN_Msk /*!< Rx Buffer DMA Enable */
+#define SPI_CR2_TXDMAEN_Pos (1U)
+#define SPI_CR2_TXDMAEN_Msk (0x1U << SPI_CR2_TXDMAEN_Pos) /*!< 0x00000002 */
+#define SPI_CR2_TXDMAEN SPI_CR2_TXDMAEN_Msk /*!< Tx Buffer DMA Enable */
+#define SPI_CR2_SSOE_Pos (2U)
+#define SPI_CR2_SSOE_Msk (0x1U << SPI_CR2_SSOE_Pos) /*!< 0x00000004 */
+#define SPI_CR2_SSOE SPI_CR2_SSOE_Msk /*!< SS Output Enable */
+#define SPI_CR2_ERRIE_Pos (5U)
+#define SPI_CR2_ERRIE_Msk (0x1U << SPI_CR2_ERRIE_Pos) /*!< 0x00000020 */
+#define SPI_CR2_ERRIE SPI_CR2_ERRIE_Msk /*!< Error Interrupt Enable */
+#define SPI_CR2_RXNEIE_Pos (6U)
+#define SPI_CR2_RXNEIE_Msk (0x1U << SPI_CR2_RXNEIE_Pos) /*!< 0x00000040 */
+#define SPI_CR2_RXNEIE SPI_CR2_RXNEIE_Msk /*!< RX buffer Not Empty Interrupt Enable */
+#define SPI_CR2_TXEIE_Pos (7U)
+#define SPI_CR2_TXEIE_Msk (0x1U << SPI_CR2_TXEIE_Pos) /*!< 0x00000080 */
+#define SPI_CR2_TXEIE SPI_CR2_TXEIE_Msk /*!< Tx buffer Empty Interrupt Enable */
+
+/******************** Bit definition for SPI_SR register ********************/
+#define SPI_SR_RXNE_Pos (0U)
+#define SPI_SR_RXNE_Msk (0x1U << SPI_SR_RXNE_Pos) /*!< 0x00000001 */
+#define SPI_SR_RXNE SPI_SR_RXNE_Msk /*!< Receive buffer Not Empty */
+#define SPI_SR_TXE_Pos (1U)
+#define SPI_SR_TXE_Msk (0x1U << SPI_SR_TXE_Pos) /*!< 0x00000002 */
+#define SPI_SR_TXE SPI_SR_TXE_Msk /*!< Transmit buffer Empty */
+#define SPI_SR_CHSIDE_Pos (2U)
+#define SPI_SR_CHSIDE_Msk (0x1U << SPI_SR_CHSIDE_Pos) /*!< 0x00000004 */
+#define SPI_SR_CHSIDE SPI_SR_CHSIDE_Msk /*!< Channel side */
+#define SPI_SR_UDR_Pos (3U)
+#define SPI_SR_UDR_Msk (0x1U << SPI_SR_UDR_Pos) /*!< 0x00000008 */
+#define SPI_SR_UDR SPI_SR_UDR_Msk /*!< Underrun flag */
+#define SPI_SR_CRCERR_Pos (4U)
+#define SPI_SR_CRCERR_Msk (0x1U << SPI_SR_CRCERR_Pos) /*!< 0x00000010 */
+#define SPI_SR_CRCERR SPI_SR_CRCERR_Msk /*!< CRC Error flag */
+#define SPI_SR_MODF_Pos (5U)
+#define SPI_SR_MODF_Msk (0x1U << SPI_SR_MODF_Pos) /*!< 0x00000020 */
+#define SPI_SR_MODF SPI_SR_MODF_Msk /*!< Mode fault */
+#define SPI_SR_OVR_Pos (6U)
+#define SPI_SR_OVR_Msk (0x1U << SPI_SR_OVR_Pos) /*!< 0x00000040 */
+#define SPI_SR_OVR SPI_SR_OVR_Msk /*!< Overrun flag */
+#define SPI_SR_BSY_Pos (7U)
+#define SPI_SR_BSY_Msk (0x1U << SPI_SR_BSY_Pos) /*!< 0x00000080 */
+#define SPI_SR_BSY SPI_SR_BSY_Msk /*!< Busy flag */
+
+/******************** Bit definition for SPI_DR register ********************/
+#define SPI_DR_DR_Pos (0U)
+#define SPI_DR_DR_Msk (0xFFFFU << SPI_DR_DR_Pos) /*!< 0x0000FFFF */
+#define SPI_DR_DR SPI_DR_DR_Msk /*!< Data Register */
+
+/******************* Bit definition for SPI_CRCPR register ******************/
+#define SPI_CRCPR_CRCPOLY_Pos (0U)
+#define SPI_CRCPR_CRCPOLY_Msk (0xFFFFU << SPI_CRCPR_CRCPOLY_Pos) /*!< 0x0000FFFF */
+#define SPI_CRCPR_CRCPOLY SPI_CRCPR_CRCPOLY_Msk /*!< CRC polynomial register */
+
+/****************** Bit definition for SPI_RXCRCR register ******************/
+#define SPI_RXCRCR_RXCRC_Pos (0U)
+#define SPI_RXCRCR_RXCRC_Msk (0xFFFFU << SPI_RXCRCR_RXCRC_Pos) /*!< 0x0000FFFF */
+#define SPI_RXCRCR_RXCRC SPI_RXCRCR_RXCRC_Msk /*!< Rx CRC Register */
+
+/****************** Bit definition for SPI_TXCRCR register ******************/
+#define SPI_TXCRCR_TXCRC_Pos (0U)
+#define SPI_TXCRCR_TXCRC_Msk (0xFFFFU << SPI_TXCRCR_TXCRC_Pos) /*!< 0x0000FFFF */
+#define SPI_TXCRCR_TXCRC SPI_TXCRCR_TXCRC_Msk /*!< Tx CRC Register */
+
+/****************** Bit definition for SPI_I2SCFGR register *****************/
+#define SPI_I2SCFGR_CHLEN_Pos (0U)
+#define SPI_I2SCFGR_CHLEN_Msk (0x1U << SPI_I2SCFGR_CHLEN_Pos) /*!< 0x00000001 */
+#define SPI_I2SCFGR_CHLEN SPI_I2SCFGR_CHLEN_Msk /*!< Channel length (number of bits per audio channel) */
+
+#define SPI_I2SCFGR_DATLEN_Pos (1U)
+#define SPI_I2SCFGR_DATLEN_Msk (0x3U << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000006 */
+#define SPI_I2SCFGR_DATLEN SPI_I2SCFGR_DATLEN_Msk /*!< DATLEN[1:0] bits (Data length to be transferred) */
+#define SPI_I2SCFGR_DATLEN_0 (0x1U << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000002 */
+#define SPI_I2SCFGR_DATLEN_1 (0x2U << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000004 */
+
+#define SPI_I2SCFGR_CKPOL_Pos (3U)
+#define SPI_I2SCFGR_CKPOL_Msk (0x1U << SPI_I2SCFGR_CKPOL_Pos) /*!< 0x00000008 */
+#define SPI_I2SCFGR_CKPOL SPI_I2SCFGR_CKPOL_Msk /*!< steady state clock polarity */
+
+#define SPI_I2SCFGR_I2SSTD_Pos (4U)
+#define SPI_I2SCFGR_I2SSTD_Msk (0x3U << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000030 */
+#define SPI_I2SCFGR_I2SSTD SPI_I2SCFGR_I2SSTD_Msk /*!< I2SSTD[1:0] bits (I2S standard selection) */
+#define SPI_I2SCFGR_I2SSTD_0 (0x1U << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000010 */
+#define SPI_I2SCFGR_I2SSTD_1 (0x2U << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000020 */
+
+#define SPI_I2SCFGR_PCMSYNC_Pos (7U)
+#define SPI_I2SCFGR_PCMSYNC_Msk (0x1U << SPI_I2SCFGR_PCMSYNC_Pos) /*!< 0x00000080 */
+#define SPI_I2SCFGR_PCMSYNC SPI_I2SCFGR_PCMSYNC_Msk /*!< PCM frame synchronization */
+
+#define SPI_I2SCFGR_I2SCFG_Pos (8U)
+#define SPI_I2SCFGR_I2SCFG_Msk (0x3U << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000300 */
+#define SPI_I2SCFGR_I2SCFG SPI_I2SCFGR_I2SCFG_Msk /*!< I2SCFG[1:0] bits (I2S configuration mode) */
+#define SPI_I2SCFGR_I2SCFG_0 (0x1U << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000100 */
+#define SPI_I2SCFGR_I2SCFG_1 (0x2U << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000200 */
+
+#define SPI_I2SCFGR_I2SE_Pos (10U)
+#define SPI_I2SCFGR_I2SE_Msk (0x1U << SPI_I2SCFGR_I2SE_Pos) /*!< 0x00000400 */
+#define SPI_I2SCFGR_I2SE SPI_I2SCFGR_I2SE_Msk /*!< I2S Enable */
+#define SPI_I2SCFGR_I2SMOD_Pos (11U)
+#define SPI_I2SCFGR_I2SMOD_Msk (0x1U << SPI_I2SCFGR_I2SMOD_Pos) /*!< 0x00000800 */
+#define SPI_I2SCFGR_I2SMOD SPI_I2SCFGR_I2SMOD_Msk /*!< I2S mode selection */
+
+/****************** Bit definition for SPI_I2SPR register *******************/
+#define SPI_I2SPR_I2SDIV_Pos (0U)
+#define SPI_I2SPR_I2SDIV_Msk (0xFFU << SPI_I2SPR_I2SDIV_Pos) /*!< 0x000000FF */
+#define SPI_I2SPR_I2SDIV SPI_I2SPR_I2SDIV_Msk /*!< I2S Linear prescaler */
+#define SPI_I2SPR_ODD_Pos (8U)
+#define SPI_I2SPR_ODD_Msk (0x1U << SPI_I2SPR_ODD_Pos) /*!< 0x00000100 */
+#define SPI_I2SPR_ODD SPI_I2SPR_ODD_Msk /*!< Odd factor for the prescaler */
+#define SPI_I2SPR_MCKOE_Pos (9U)
+#define SPI_I2SPR_MCKOE_Msk (0x1U << SPI_I2SPR_MCKOE_Pos) /*!< 0x00000200 */
+#define SPI_I2SPR_MCKOE SPI_I2SPR_MCKOE_Msk /*!< Master Clock Output Enable */
+
+/******************************************************************************/
+/* */
+/* Inter-integrated Circuit Interface */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for I2C_CR1 register ********************/
+#define I2C_CR1_PE_Pos (0U)
+#define I2C_CR1_PE_Msk (0x1U << I2C_CR1_PE_Pos) /*!< 0x00000001 */
+#define I2C_CR1_PE I2C_CR1_PE_Msk /*!< Peripheral Enable */
+#define I2C_CR1_SMBUS_Pos (1U)
+#define I2C_CR1_SMBUS_Msk (0x1U << I2C_CR1_SMBUS_Pos) /*!< 0x00000002 */
+#define I2C_CR1_SMBUS I2C_CR1_SMBUS_Msk /*!< SMBus Mode */
+#define I2C_CR1_SMBTYPE_Pos (3U)
+#define I2C_CR1_SMBTYPE_Msk (0x1U << I2C_CR1_SMBTYPE_Pos) /*!< 0x00000008 */
+#define I2C_CR1_SMBTYPE I2C_CR1_SMBTYPE_Msk /*!< SMBus Type */
+#define I2C_CR1_ENARP_Pos (4U)
+#define I2C_CR1_ENARP_Msk (0x1U << I2C_CR1_ENARP_Pos) /*!< 0x00000010 */
+#define I2C_CR1_ENARP I2C_CR1_ENARP_Msk /*!< ARP Enable */
+#define I2C_CR1_ENPEC_Pos (5U)
+#define I2C_CR1_ENPEC_Msk (0x1U << I2C_CR1_ENPEC_Pos) /*!< 0x00000020 */
+#define I2C_CR1_ENPEC I2C_CR1_ENPEC_Msk /*!< PEC Enable */
+#define I2C_CR1_ENGC_Pos (6U)
+#define I2C_CR1_ENGC_Msk (0x1U << I2C_CR1_ENGC_Pos) /*!< 0x00000040 */
+#define I2C_CR1_ENGC I2C_CR1_ENGC_Msk /*!< General Call Enable */
+#define I2C_CR1_NOSTRETCH_Pos (7U)
+#define I2C_CR1_NOSTRETCH_Msk (0x1U << I2C_CR1_NOSTRETCH_Pos) /*!< 0x00000080 */
+#define I2C_CR1_NOSTRETCH I2C_CR1_NOSTRETCH_Msk /*!< Clock Stretching Disable (Slave mode) */
+#define I2C_CR1_START_Pos (8U)
+#define I2C_CR1_START_Msk (0x1U << I2C_CR1_START_Pos) /*!< 0x00000100 */
+#define I2C_CR1_START I2C_CR1_START_Msk /*!< Start Generation */
+#define I2C_CR1_STOP_Pos (9U)
+#define I2C_CR1_STOP_Msk (0x1U << I2C_CR1_STOP_Pos) /*!< 0x00000200 */
+#define I2C_CR1_STOP I2C_CR1_STOP_Msk /*!< Stop Generation */
+#define I2C_CR1_ACK_Pos (10U)
+#define I2C_CR1_ACK_Msk (0x1U << I2C_CR1_ACK_Pos) /*!< 0x00000400 */
+#define I2C_CR1_ACK I2C_CR1_ACK_Msk /*!< Acknowledge Enable */
+#define I2C_CR1_POS_Pos (11U)
+#define I2C_CR1_POS_Msk (0x1U << I2C_CR1_POS_Pos) /*!< 0x00000800 */
+#define I2C_CR1_POS I2C_CR1_POS_Msk /*!< Acknowledge/PEC Position (for data reception) */
+#define I2C_CR1_PEC_Pos (12U)
+#define I2C_CR1_PEC_Msk (0x1U << I2C_CR1_PEC_Pos) /*!< 0x00001000 */
+#define I2C_CR1_PEC I2C_CR1_PEC_Msk /*!< Packet Error Checking */
+#define I2C_CR1_ALERT_Pos (13U)
+#define I2C_CR1_ALERT_Msk (0x1U << I2C_CR1_ALERT_Pos) /*!< 0x00002000 */
+#define I2C_CR1_ALERT I2C_CR1_ALERT_Msk /*!< SMBus Alert */
+#define I2C_CR1_SWRST_Pos (15U)
+#define I2C_CR1_SWRST_Msk (0x1U << I2C_CR1_SWRST_Pos) /*!< 0x00008000 */
+#define I2C_CR1_SWRST I2C_CR1_SWRST_Msk /*!< Software Reset */
+
+/******************* Bit definition for I2C_CR2 register ********************/
+#define I2C_CR2_FREQ_Pos (0U)
+#define I2C_CR2_FREQ_Msk (0x3FU << I2C_CR2_FREQ_Pos) /*!< 0x0000003F */
+#define I2C_CR2_FREQ I2C_CR2_FREQ_Msk /*!< FREQ[5:0] bits (Peripheral Clock Frequency) */
+#define I2C_CR2_FREQ_0 (0x01U << I2C_CR2_FREQ_Pos) /*!< 0x00000001 */
+#define I2C_CR2_FREQ_1 (0x02U << I2C_CR2_FREQ_Pos) /*!< 0x00000002 */
+#define I2C_CR2_FREQ_2 (0x04U << I2C_CR2_FREQ_Pos) /*!< 0x00000004 */
+#define I2C_CR2_FREQ_3 (0x08U << I2C_CR2_FREQ_Pos) /*!< 0x00000008 */
+#define I2C_CR2_FREQ_4 (0x10U << I2C_CR2_FREQ_Pos) /*!< 0x00000010 */
+#define I2C_CR2_FREQ_5 (0x20U << I2C_CR2_FREQ_Pos) /*!< 0x00000020 */
+
+#define I2C_CR2_ITERREN_Pos (8U)
+#define I2C_CR2_ITERREN_Msk (0x1U << I2C_CR2_ITERREN_Pos) /*!< 0x00000100 */
+#define I2C_CR2_ITERREN I2C_CR2_ITERREN_Msk /*!< Error Interrupt Enable */
+#define I2C_CR2_ITEVTEN_Pos (9U)
+#define I2C_CR2_ITEVTEN_Msk (0x1U << I2C_CR2_ITEVTEN_Pos) /*!< 0x00000200 */
+#define I2C_CR2_ITEVTEN I2C_CR2_ITEVTEN_Msk /*!< Event Interrupt Enable */
+#define I2C_CR2_ITBUFEN_Pos (10U)
+#define I2C_CR2_ITBUFEN_Msk (0x1U << I2C_CR2_ITBUFEN_Pos) /*!< 0x00000400 */
+#define I2C_CR2_ITBUFEN I2C_CR2_ITBUFEN_Msk /*!< Buffer Interrupt Enable */
+#define I2C_CR2_DMAEN_Pos (11U)
+#define I2C_CR2_DMAEN_Msk (0x1U << I2C_CR2_DMAEN_Pos) /*!< 0x00000800 */
+#define I2C_CR2_DMAEN I2C_CR2_DMAEN_Msk /*!< DMA Requests Enable */
+#define I2C_CR2_LAST_Pos (12U)
+#define I2C_CR2_LAST_Msk (0x1U << I2C_CR2_LAST_Pos) /*!< 0x00001000 */
+#define I2C_CR2_LAST I2C_CR2_LAST_Msk /*!< DMA Last Transfer */
+
+/******************* Bit definition for I2C_OAR1 register *******************/
+#define I2C_OAR1_ADD1_7 ((uint32_t)0x000000FE) /*!< Interface Address */
+#define I2C_OAR1_ADD8_9 ((uint32_t)0x00000300) /*!< Interface Address */
+
+#define I2C_OAR1_ADD0_Pos (0U)
+#define I2C_OAR1_ADD0_Msk (0x1U << I2C_OAR1_ADD0_Pos) /*!< 0x00000001 */
+#define I2C_OAR1_ADD0 I2C_OAR1_ADD0_Msk /*!< Bit 0 */
+#define I2C_OAR1_ADD1_Pos (1U)
+#define I2C_OAR1_ADD1_Msk (0x1U << I2C_OAR1_ADD1_Pos) /*!< 0x00000002 */
+#define I2C_OAR1_ADD1 I2C_OAR1_ADD1_Msk /*!< Bit 1 */
+#define I2C_OAR1_ADD2_Pos (2U)
+#define I2C_OAR1_ADD2_Msk (0x1U << I2C_OAR1_ADD2_Pos) /*!< 0x00000004 */
+#define I2C_OAR1_ADD2 I2C_OAR1_ADD2_Msk /*!< Bit 2 */
+#define I2C_OAR1_ADD3_Pos (3U)
+#define I2C_OAR1_ADD3_Msk (0x1U << I2C_OAR1_ADD3_Pos) /*!< 0x00000008 */
+#define I2C_OAR1_ADD3 I2C_OAR1_ADD3_Msk /*!< Bit 3 */
+#define I2C_OAR1_ADD4_Pos (4U)
+#define I2C_OAR1_ADD4_Msk (0x1U << I2C_OAR1_ADD4_Pos) /*!< 0x00000010 */
+#define I2C_OAR1_ADD4 I2C_OAR1_ADD4_Msk /*!< Bit 4 */
+#define I2C_OAR1_ADD5_Pos (5U)
+#define I2C_OAR1_ADD5_Msk (0x1U << I2C_OAR1_ADD5_Pos) /*!< 0x00000020 */
+#define I2C_OAR1_ADD5 I2C_OAR1_ADD5_Msk /*!< Bit 5 */
+#define I2C_OAR1_ADD6_Pos (6U)
+#define I2C_OAR1_ADD6_Msk (0x1U << I2C_OAR1_ADD6_Pos) /*!< 0x00000040 */
+#define I2C_OAR1_ADD6 I2C_OAR1_ADD6_Msk /*!< Bit 6 */
+#define I2C_OAR1_ADD7_Pos (7U)
+#define I2C_OAR1_ADD7_Msk (0x1U << I2C_OAR1_ADD7_Pos) /*!< 0x00000080 */
+#define I2C_OAR1_ADD7 I2C_OAR1_ADD7_Msk /*!< Bit 7 */
+#define I2C_OAR1_ADD8_Pos (8U)
+#define I2C_OAR1_ADD8_Msk (0x1U << I2C_OAR1_ADD8_Pos) /*!< 0x00000100 */
+#define I2C_OAR1_ADD8 I2C_OAR1_ADD8_Msk /*!< Bit 8 */
+#define I2C_OAR1_ADD9_Pos (9U)
+#define I2C_OAR1_ADD9_Msk (0x1U << I2C_OAR1_ADD9_Pos) /*!< 0x00000200 */
+#define I2C_OAR1_ADD9 I2C_OAR1_ADD9_Msk /*!< Bit 9 */
+
+#define I2C_OAR1_ADDMODE_Pos (15U)
+#define I2C_OAR1_ADDMODE_Msk (0x1U << I2C_OAR1_ADDMODE_Pos) /*!< 0x00008000 */
+#define I2C_OAR1_ADDMODE I2C_OAR1_ADDMODE_Msk /*!< Addressing Mode (Slave mode) */
+
+/******************* Bit definition for I2C_OAR2 register *******************/
+#define I2C_OAR2_ENDUAL_Pos (0U)
+#define I2C_OAR2_ENDUAL_Msk (0x1U << I2C_OAR2_ENDUAL_Pos) /*!< 0x00000001 */
+#define I2C_OAR2_ENDUAL I2C_OAR2_ENDUAL_Msk /*!< Dual addressing mode enable */
+#define I2C_OAR2_ADD2_Pos (1U)
+#define I2C_OAR2_ADD2_Msk (0x7FU << I2C_OAR2_ADD2_Pos) /*!< 0x000000FE */
+#define I2C_OAR2_ADD2 I2C_OAR2_ADD2_Msk /*!< Interface address */
+
+/******************* Bit definition for I2C_SR1 register ********************/
+#define I2C_SR1_SB_Pos (0U)
+#define I2C_SR1_SB_Msk (0x1U << I2C_SR1_SB_Pos) /*!< 0x00000001 */
+#define I2C_SR1_SB I2C_SR1_SB_Msk /*!< Start Bit (Master mode) */
+#define I2C_SR1_ADDR_Pos (1U)
+#define I2C_SR1_ADDR_Msk (0x1U << I2C_SR1_ADDR_Pos) /*!< 0x00000002 */
+#define I2C_SR1_ADDR I2C_SR1_ADDR_Msk /*!< Address sent (master mode)/matched (slave mode) */
+#define I2C_SR1_BTF_Pos (2U)
+#define I2C_SR1_BTF_Msk (0x1U << I2C_SR1_BTF_Pos) /*!< 0x00000004 */
+#define I2C_SR1_BTF I2C_SR1_BTF_Msk /*!< Byte Transfer Finished */
+#define I2C_SR1_ADD10_Pos (3U)
+#define I2C_SR1_ADD10_Msk (0x1U << I2C_SR1_ADD10_Pos) /*!< 0x00000008 */
+#define I2C_SR1_ADD10 I2C_SR1_ADD10_Msk /*!< 10-bit header sent (Master mode) */
+#define I2C_SR1_STOPF_Pos (4U)
+#define I2C_SR1_STOPF_Msk (0x1U << I2C_SR1_STOPF_Pos) /*!< 0x00000010 */
+#define I2C_SR1_STOPF I2C_SR1_STOPF_Msk /*!< Stop detection (Slave mode) */
+#define I2C_SR1_RXNE_Pos (6U)
+#define I2C_SR1_RXNE_Msk (0x1U << I2C_SR1_RXNE_Pos) /*!< 0x00000040 */
+#define I2C_SR1_RXNE I2C_SR1_RXNE_Msk /*!< Data Register not Empty (receivers) */
+#define I2C_SR1_TXE_Pos (7U)
+#define I2C_SR1_TXE_Msk (0x1U << I2C_SR1_TXE_Pos) /*!< 0x00000080 */
+#define I2C_SR1_TXE I2C_SR1_TXE_Msk /*!< Data Register Empty (transmitters) */
+#define I2C_SR1_BERR_Pos (8U)
+#define I2C_SR1_BERR_Msk (0x1U << I2C_SR1_BERR_Pos) /*!< 0x00000100 */
+#define I2C_SR1_BERR I2C_SR1_BERR_Msk /*!< Bus Error */
+#define I2C_SR1_ARLO_Pos (9U)
+#define I2C_SR1_ARLO_Msk (0x1U << I2C_SR1_ARLO_Pos) /*!< 0x00000200 */
+#define I2C_SR1_ARLO I2C_SR1_ARLO_Msk /*!< Arbitration Lost (master mode) */
+#define I2C_SR1_AF_Pos (10U)
+#define I2C_SR1_AF_Msk (0x1U << I2C_SR1_AF_Pos) /*!< 0x00000400 */
+#define I2C_SR1_AF I2C_SR1_AF_Msk /*!< Acknowledge Failure */
+#define I2C_SR1_OVR_Pos (11U)
+#define I2C_SR1_OVR_Msk (0x1U << I2C_SR1_OVR_Pos) /*!< 0x00000800 */
+#define I2C_SR1_OVR I2C_SR1_OVR_Msk /*!< Overrun/Underrun */
+#define I2C_SR1_PECERR_Pos (12U)
+#define I2C_SR1_PECERR_Msk (0x1U << I2C_SR1_PECERR_Pos) /*!< 0x00001000 */
+#define I2C_SR1_PECERR I2C_SR1_PECERR_Msk /*!< PEC Error in reception */
+#define I2C_SR1_TIMEOUT_Pos (14U)
+#define I2C_SR1_TIMEOUT_Msk (0x1U << I2C_SR1_TIMEOUT_Pos) /*!< 0x00004000 */
+#define I2C_SR1_TIMEOUT I2C_SR1_TIMEOUT_Msk /*!< Timeout or Tlow Error */
+#define I2C_SR1_SMBALERT_Pos (15U)
+#define I2C_SR1_SMBALERT_Msk (0x1U << I2C_SR1_SMBALERT_Pos) /*!< 0x00008000 */
+#define I2C_SR1_SMBALERT I2C_SR1_SMBALERT_Msk /*!< SMBus Alert */
+
+/******************* Bit definition for I2C_SR2 register ********************/
+#define I2C_SR2_MSL_Pos (0U)
+#define I2C_SR2_MSL_Msk (0x1U << I2C_SR2_MSL_Pos) /*!< 0x00000001 */
+#define I2C_SR2_MSL I2C_SR2_MSL_Msk /*!< Master/Slave */
+#define I2C_SR2_BUSY_Pos (1U)
+#define I2C_SR2_BUSY_Msk (0x1U << I2C_SR2_BUSY_Pos) /*!< 0x00000002 */
+#define I2C_SR2_BUSY I2C_SR2_BUSY_Msk /*!< Bus Busy */
+#define I2C_SR2_TRA_Pos (2U)
+#define I2C_SR2_TRA_Msk (0x1U << I2C_SR2_TRA_Pos) /*!< 0x00000004 */
+#define I2C_SR2_TRA I2C_SR2_TRA_Msk /*!< Transmitter/Receiver */
+#define I2C_SR2_GENCALL_Pos (4U)
+#define I2C_SR2_GENCALL_Msk (0x1U << I2C_SR2_GENCALL_Pos) /*!< 0x00000010 */
+#define I2C_SR2_GENCALL I2C_SR2_GENCALL_Msk /*!< General Call Address (Slave mode) */
+#define I2C_SR2_SMBDEFAULT_Pos (5U)
+#define I2C_SR2_SMBDEFAULT_Msk (0x1U << I2C_SR2_SMBDEFAULT_Pos) /*!< 0x00000020 */
+#define I2C_SR2_SMBDEFAULT I2C_SR2_SMBDEFAULT_Msk /*!< SMBus Device Default Address (Slave mode) */
+#define I2C_SR2_SMBHOST_Pos (6U)
+#define I2C_SR2_SMBHOST_Msk (0x1U << I2C_SR2_SMBHOST_Pos) /*!< 0x00000040 */
+#define I2C_SR2_SMBHOST I2C_SR2_SMBHOST_Msk /*!< SMBus Host Header (Slave mode) */
+#define I2C_SR2_DUALF_Pos (7U)
+#define I2C_SR2_DUALF_Msk (0x1U << I2C_SR2_DUALF_Pos) /*!< 0x00000080 */
+#define I2C_SR2_DUALF I2C_SR2_DUALF_Msk /*!< Dual Flag (Slave mode) */
+#define I2C_SR2_PEC_Pos (8U)
+#define I2C_SR2_PEC_Msk (0xFFU << I2C_SR2_PEC_Pos) /*!< 0x0000FF00 */
+#define I2C_SR2_PEC I2C_SR2_PEC_Msk /*!< Packet Error Checking Register */
+
+/******************* Bit definition for I2C_CCR register ********************/
+#define I2C_CCR_CCR_Pos (0U)
+#define I2C_CCR_CCR_Msk (0xFFFU << I2C_CCR_CCR_Pos) /*!< 0x00000FFF */
+#define I2C_CCR_CCR I2C_CCR_CCR_Msk /*!< Clock Control Register in Fast/Standard mode (Master mode) */
+#define I2C_CCR_DUTY_Pos (14U)
+#define I2C_CCR_DUTY_Msk (0x1U << I2C_CCR_DUTY_Pos) /*!< 0x00004000 */
+#define I2C_CCR_DUTY I2C_CCR_DUTY_Msk /*!< Fast Mode Duty Cycle */
+#define I2C_CCR_FS_Pos (15U)
+#define I2C_CCR_FS_Msk (0x1U << I2C_CCR_FS_Pos) /*!< 0x00008000 */
+#define I2C_CCR_FS I2C_CCR_FS_Msk /*!< I2C Master Mode Selection */
+
+/****************** Bit definition for I2C_TRISE register *******************/
+#define I2C_TRISE_TRISE_Pos (0U)
+#define I2C_TRISE_TRISE_Msk (0x3FU << I2C_TRISE_TRISE_Pos) /*!< 0x0000003F */
+#define I2C_TRISE_TRISE I2C_TRISE_TRISE_Msk /*!< Maximum Rise Time in Fast/Standard mode (Master mode) */
+
+/******************************************************************************/
+/* */
+/* Universal Synchronous Asynchronous Receiver Transmitter */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for USART_SR register *******************/
+#define USART_SR_PE_Pos (0U)
+#define USART_SR_PE_Msk (0x1U << USART_SR_PE_Pos) /*!< 0x00000001 */
+#define USART_SR_PE USART_SR_PE_Msk /*!< Parity Error */
+#define USART_SR_FE_Pos (1U)
+#define USART_SR_FE_Msk (0x1U << USART_SR_FE_Pos) /*!< 0x00000002 */
+#define USART_SR_FE USART_SR_FE_Msk /*!< Framing Error */
+#define USART_SR_NE_Pos (2U)
+#define USART_SR_NE_Msk (0x1U << USART_SR_NE_Pos) /*!< 0x00000004 */
+#define USART_SR_NE USART_SR_NE_Msk /*!< Noise Error Flag */
+#define USART_SR_ORE_Pos (3U)
+#define USART_SR_ORE_Msk (0x1U << USART_SR_ORE_Pos) /*!< 0x00000008 */
+#define USART_SR_ORE USART_SR_ORE_Msk /*!< OverRun Error */
+#define USART_SR_IDLE_Pos (4U)
+#define USART_SR_IDLE_Msk (0x1U << USART_SR_IDLE_Pos) /*!< 0x00000010 */
+#define USART_SR_IDLE USART_SR_IDLE_Msk /*!< IDLE line detected */
+#define USART_SR_RXNE_Pos (5U)
+#define USART_SR_RXNE_Msk (0x1U << USART_SR_RXNE_Pos) /*!< 0x00000020 */
+#define USART_SR_RXNE USART_SR_RXNE_Msk /*!< Read Data Register Not Empty */
+#define USART_SR_TC_Pos (6U)
+#define USART_SR_TC_Msk (0x1U << USART_SR_TC_Pos) /*!< 0x00000040 */
+#define USART_SR_TC USART_SR_TC_Msk /*!< Transmission Complete */
+#define USART_SR_TXE_Pos (7U)
+#define USART_SR_TXE_Msk (0x1U << USART_SR_TXE_Pos) /*!< 0x00000080 */
+#define USART_SR_TXE USART_SR_TXE_Msk /*!< Transmit Data Register Empty */
+#define USART_SR_LBD_Pos (8U)
+#define USART_SR_LBD_Msk (0x1U << USART_SR_LBD_Pos) /*!< 0x00000100 */
+#define USART_SR_LBD USART_SR_LBD_Msk /*!< LIN Break Detection Flag */
+#define USART_SR_CTS_Pos (9U)
+#define USART_SR_CTS_Msk (0x1U << USART_SR_CTS_Pos) /*!< 0x00000200 */
+#define USART_SR_CTS USART_SR_CTS_Msk /*!< CTS Flag */
+
+/******************* Bit definition for USART_DR register *******************/
+#define USART_DR_DR_Pos (0U)
+#define USART_DR_DR_Msk (0x1FFU << USART_DR_DR_Pos) /*!< 0x000001FF */
+#define USART_DR_DR USART_DR_DR_Msk /*!< Data value */
+
+/****************** Bit definition for USART_BRR register *******************/
+#define USART_BRR_DIV_Fraction_Pos (0U)
+#define USART_BRR_DIV_Fraction_Msk (0xFU << USART_BRR_DIV_Fraction_Pos) /*!< 0x0000000F */
+#define USART_BRR_DIV_Fraction USART_BRR_DIV_Fraction_Msk /*!< Fraction of USARTDIV */
+#define USART_BRR_DIV_Mantissa_Pos (4U)
+#define USART_BRR_DIV_Mantissa_Msk (0xFFFU << USART_BRR_DIV_Mantissa_Pos) /*!< 0x0000FFF0 */
+#define USART_BRR_DIV_Mantissa USART_BRR_DIV_Mantissa_Msk /*!< Mantissa of USARTDIV */
+
+/****************** Bit definition for USART_CR1 register *******************/
+#define USART_CR1_SBK_Pos (0U)
+#define USART_CR1_SBK_Msk (0x1U << USART_CR1_SBK_Pos) /*!< 0x00000001 */
+#define USART_CR1_SBK USART_CR1_SBK_Msk /*!< Send Break */
+#define USART_CR1_RWU_Pos (1U)
+#define USART_CR1_RWU_Msk (0x1U << USART_CR1_RWU_Pos) /*!< 0x00000002 */
+#define USART_CR1_RWU USART_CR1_RWU_Msk /*!< Receiver wakeup */
+#define USART_CR1_RE_Pos (2U)
+#define USART_CR1_RE_Msk (0x1U << USART_CR1_RE_Pos) /*!< 0x00000004 */
+#define USART_CR1_RE USART_CR1_RE_Msk /*!< Receiver Enable */
+#define USART_CR1_TE_Pos (3U)
+#define USART_CR1_TE_Msk (0x1U << USART_CR1_TE_Pos) /*!< 0x00000008 */
+#define USART_CR1_TE USART_CR1_TE_Msk /*!< Transmitter Enable */
+#define USART_CR1_IDLEIE_Pos (4U)
+#define USART_CR1_IDLEIE_Msk (0x1U << USART_CR1_IDLEIE_Pos) /*!< 0x00000010 */
+#define USART_CR1_IDLEIE USART_CR1_IDLEIE_Msk /*!< IDLE Interrupt Enable */
+#define USART_CR1_RXNEIE_Pos (5U)
+#define USART_CR1_RXNEIE_Msk (0x1U << USART_CR1_RXNEIE_Pos) /*!< 0x00000020 */
+#define USART_CR1_RXNEIE USART_CR1_RXNEIE_Msk /*!< RXNE Interrupt Enable */
+#define USART_CR1_TCIE_Pos (6U)
+#define USART_CR1_TCIE_Msk (0x1U << USART_CR1_TCIE_Pos) /*!< 0x00000040 */
+#define USART_CR1_TCIE USART_CR1_TCIE_Msk /*!< Transmission Complete Interrupt Enable */
+#define USART_CR1_TXEIE_Pos (7U)
+#define USART_CR1_TXEIE_Msk (0x1U << USART_CR1_TXEIE_Pos) /*!< 0x00000080 */
+#define USART_CR1_TXEIE USART_CR1_TXEIE_Msk /*!< PE Interrupt Enable */
+#define USART_CR1_PEIE_Pos (8U)
+#define USART_CR1_PEIE_Msk (0x1U << USART_CR1_PEIE_Pos) /*!< 0x00000100 */
+#define USART_CR1_PEIE USART_CR1_PEIE_Msk /*!< PE Interrupt Enable */
+#define USART_CR1_PS_Pos (9U)
+#define USART_CR1_PS_Msk (0x1U << USART_CR1_PS_Pos) /*!< 0x00000200 */
+#define USART_CR1_PS USART_CR1_PS_Msk /*!< Parity Selection */
+#define USART_CR1_PCE_Pos (10U)
+#define USART_CR1_PCE_Msk (0x1U << USART_CR1_PCE_Pos) /*!< 0x00000400 */
+#define USART_CR1_PCE USART_CR1_PCE_Msk /*!< Parity Control Enable */
+#define USART_CR1_WAKE_Pos (11U)
+#define USART_CR1_WAKE_Msk (0x1U << USART_CR1_WAKE_Pos) /*!< 0x00000800 */
+#define USART_CR1_WAKE USART_CR1_WAKE_Msk /*!< Wakeup method */
+#define USART_CR1_M_Pos (12U)
+#define USART_CR1_M_Msk (0x1U << USART_CR1_M_Pos) /*!< 0x00001000 */
+#define USART_CR1_M USART_CR1_M_Msk /*!< Word length */
+#define USART_CR1_UE_Pos (13U)
+#define USART_CR1_UE_Msk (0x1U << USART_CR1_UE_Pos) /*!< 0x00002000 */
+#define USART_CR1_UE USART_CR1_UE_Msk /*!< USART Enable */
+
+/****************** Bit definition for USART_CR2 register *******************/
+#define USART_CR2_ADD_Pos (0U)
+#define USART_CR2_ADD_Msk (0xFU << USART_CR2_ADD_Pos) /*!< 0x0000000F */
+#define USART_CR2_ADD USART_CR2_ADD_Msk /*!< Address of the USART node */
+#define USART_CR2_LBDL_Pos (5U)
+#define USART_CR2_LBDL_Msk (0x1U << USART_CR2_LBDL_Pos) /*!< 0x00000020 */
+#define USART_CR2_LBDL USART_CR2_LBDL_Msk /*!< LIN Break Detection Length */
+#define USART_CR2_LBDIE_Pos (6U)
+#define USART_CR2_LBDIE_Msk (0x1U << USART_CR2_LBDIE_Pos) /*!< 0x00000040 */
+#define USART_CR2_LBDIE USART_CR2_LBDIE_Msk /*!< LIN Break Detection Interrupt Enable */
+#define USART_CR2_LBCL_Pos (8U)
+#define USART_CR2_LBCL_Msk (0x1U << USART_CR2_LBCL_Pos) /*!< 0x00000100 */
+#define USART_CR2_LBCL USART_CR2_LBCL_Msk /*!< Last Bit Clock pulse */
+#define USART_CR2_CPHA_Pos (9U)
+#define USART_CR2_CPHA_Msk (0x1U << USART_CR2_CPHA_Pos) /*!< 0x00000200 */
+#define USART_CR2_CPHA USART_CR2_CPHA_Msk /*!< Clock Phase */
+#define USART_CR2_CPOL_Pos (10U)
+#define USART_CR2_CPOL_Msk (0x1U << USART_CR2_CPOL_Pos) /*!< 0x00000400 */
+#define USART_CR2_CPOL USART_CR2_CPOL_Msk /*!< Clock Polarity */
+#define USART_CR2_CLKEN_Pos (11U)
+#define USART_CR2_CLKEN_Msk (0x1U << USART_CR2_CLKEN_Pos) /*!< 0x00000800 */
+#define USART_CR2_CLKEN USART_CR2_CLKEN_Msk /*!< Clock Enable */
+
+#define USART_CR2_STOP_Pos (12U)
+#define USART_CR2_STOP_Msk (0x3U << USART_CR2_STOP_Pos) /*!< 0x00003000 */
+#define USART_CR2_STOP USART_CR2_STOP_Msk /*!< STOP[1:0] bits (STOP bits) */
+#define USART_CR2_STOP_0 (0x1U << USART_CR2_STOP_Pos) /*!< 0x00001000 */
+#define USART_CR2_STOP_1 (0x2U << USART_CR2_STOP_Pos) /*!< 0x00002000 */
+
+#define USART_CR2_LINEN_Pos (14U)
+#define USART_CR2_LINEN_Msk (0x1U << USART_CR2_LINEN_Pos) /*!< 0x00004000 */
+#define USART_CR2_LINEN USART_CR2_LINEN_Msk /*!< LIN mode enable */
+
+/****************** Bit definition for USART_CR3 register *******************/
+#define USART_CR3_EIE_Pos (0U)
+#define USART_CR3_EIE_Msk (0x1U << USART_CR3_EIE_Pos) /*!< 0x00000001 */
+#define USART_CR3_EIE USART_CR3_EIE_Msk /*!< Error Interrupt Enable */
+#define USART_CR3_IREN_Pos (1U)
+#define USART_CR3_IREN_Msk (0x1U << USART_CR3_IREN_Pos) /*!< 0x00000002 */
+#define USART_CR3_IREN USART_CR3_IREN_Msk /*!< IrDA mode Enable */
+#define USART_CR3_IRLP_Pos (2U)
+#define USART_CR3_IRLP_Msk (0x1U << USART_CR3_IRLP_Pos) /*!< 0x00000004 */
+#define USART_CR3_IRLP USART_CR3_IRLP_Msk /*!< IrDA Low-Power */
+#define USART_CR3_HDSEL_Pos (3U)
+#define USART_CR3_HDSEL_Msk (0x1U << USART_CR3_HDSEL_Pos) /*!< 0x00000008 */
+#define USART_CR3_HDSEL USART_CR3_HDSEL_Msk /*!< Half-Duplex Selection */
+#define USART_CR3_NACK_Pos (4U)
+#define USART_CR3_NACK_Msk (0x1U << USART_CR3_NACK_Pos) /*!< 0x00000010 */
+#define USART_CR3_NACK USART_CR3_NACK_Msk /*!< Smartcard NACK enable */
+#define USART_CR3_SCEN_Pos (5U)
+#define USART_CR3_SCEN_Msk (0x1U << USART_CR3_SCEN_Pos) /*!< 0x00000020 */
+#define USART_CR3_SCEN USART_CR3_SCEN_Msk /*!< Smartcard mode enable */
+#define USART_CR3_DMAR_Pos (6U)
+#define USART_CR3_DMAR_Msk (0x1U << USART_CR3_DMAR_Pos) /*!< 0x00000040 */
+#define USART_CR3_DMAR USART_CR3_DMAR_Msk /*!< DMA Enable Receiver */
+#define USART_CR3_DMAT_Pos (7U)
+#define USART_CR3_DMAT_Msk (0x1U << USART_CR3_DMAT_Pos) /*!< 0x00000080 */
+#define USART_CR3_DMAT USART_CR3_DMAT_Msk /*!< DMA Enable Transmitter */
+#define USART_CR3_RTSE_Pos (8U)
+#define USART_CR3_RTSE_Msk (0x1U << USART_CR3_RTSE_Pos) /*!< 0x00000100 */
+#define USART_CR3_RTSE USART_CR3_RTSE_Msk /*!< RTS Enable */
+#define USART_CR3_CTSE_Pos (9U)
+#define USART_CR3_CTSE_Msk (0x1U << USART_CR3_CTSE_Pos) /*!< 0x00000200 */
+#define USART_CR3_CTSE USART_CR3_CTSE_Msk /*!< CTS Enable */
+#define USART_CR3_CTSIE_Pos (10U)
+#define USART_CR3_CTSIE_Msk (0x1U << USART_CR3_CTSIE_Pos) /*!< 0x00000400 */
+#define USART_CR3_CTSIE USART_CR3_CTSIE_Msk /*!< CTS Interrupt Enable */
+
+/****************** Bit definition for USART_GTPR register ******************/
+#define USART_GTPR_PSC_Pos (0U)
+#define USART_GTPR_PSC_Msk (0xFFU << USART_GTPR_PSC_Pos) /*!< 0x000000FF */
+#define USART_GTPR_PSC USART_GTPR_PSC_Msk /*!< PSC[7:0] bits (Prescaler value) */
+#define USART_GTPR_PSC_0 (0x01U << USART_GTPR_PSC_Pos) /*!< 0x00000001 */
+#define USART_GTPR_PSC_1 (0x02U << USART_GTPR_PSC_Pos) /*!< 0x00000002 */
+#define USART_GTPR_PSC_2 (0x04U << USART_GTPR_PSC_Pos) /*!< 0x00000004 */
+#define USART_GTPR_PSC_3 (0x08U << USART_GTPR_PSC_Pos) /*!< 0x00000008 */
+#define USART_GTPR_PSC_4 (0x10U << USART_GTPR_PSC_Pos) /*!< 0x00000010 */
+#define USART_GTPR_PSC_5 (0x20U << USART_GTPR_PSC_Pos) /*!< 0x00000020 */
+#define USART_GTPR_PSC_6 (0x40U << USART_GTPR_PSC_Pos) /*!< 0x00000040 */
+#define USART_GTPR_PSC_7 (0x80U << USART_GTPR_PSC_Pos) /*!< 0x00000080 */
+
+#define USART_GTPR_GT_Pos (8U)
+#define USART_GTPR_GT_Msk (0xFFU << USART_GTPR_GT_Pos) /*!< 0x0000FF00 */
+#define USART_GTPR_GT USART_GTPR_GT_Msk /*!< Guard time value */
+
+/******************************************************************************/
+/* */
+/* Debug MCU */
+/* */
+/******************************************************************************/
+
+/**************** Bit definition for DBGMCU_IDCODE register *****************/
+#define DBGMCU_IDCODE_DEV_ID_Pos (0U)
+#define DBGMCU_IDCODE_DEV_ID_Msk (0xFFFU << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */
+#define DBGMCU_IDCODE_DEV_ID DBGMCU_IDCODE_DEV_ID_Msk /*!< Device Identifier */
+
+#define DBGMCU_IDCODE_REV_ID_Pos (16U)
+#define DBGMCU_IDCODE_REV_ID_Msk (0xFFFFU << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */
+#define DBGMCU_IDCODE_REV_ID DBGMCU_IDCODE_REV_ID_Msk /*!< REV_ID[15:0] bits (Revision Identifier) */
+#define DBGMCU_IDCODE_REV_ID_0 (0x0001U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00010000 */
+#define DBGMCU_IDCODE_REV_ID_1 (0x0002U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00020000 */
+#define DBGMCU_IDCODE_REV_ID_2 (0x0004U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00040000 */
+#define DBGMCU_IDCODE_REV_ID_3 (0x0008U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00080000 */
+#define DBGMCU_IDCODE_REV_ID_4 (0x0010U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00100000 */
+#define DBGMCU_IDCODE_REV_ID_5 (0x0020U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00200000 */
+#define DBGMCU_IDCODE_REV_ID_6 (0x0040U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00400000 */
+#define DBGMCU_IDCODE_REV_ID_7 (0x0080U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00800000 */
+#define DBGMCU_IDCODE_REV_ID_8 (0x0100U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x01000000 */
+#define DBGMCU_IDCODE_REV_ID_9 (0x0200U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x02000000 */
+#define DBGMCU_IDCODE_REV_ID_10 (0x0400U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x04000000 */
+#define DBGMCU_IDCODE_REV_ID_11 (0x0800U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x08000000 */
+#define DBGMCU_IDCODE_REV_ID_12 (0x1000U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x10000000 */
+#define DBGMCU_IDCODE_REV_ID_13 (0x2000U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x20000000 */
+#define DBGMCU_IDCODE_REV_ID_14 (0x4000U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x40000000 */
+#define DBGMCU_IDCODE_REV_ID_15 (0x8000U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x80000000 */
+
+/****************** Bit definition for DBGMCU_CR register *******************/
+#define DBGMCU_CR_DBG_SLEEP_Pos (0U)
+#define DBGMCU_CR_DBG_SLEEP_Msk (0x1U << DBGMCU_CR_DBG_SLEEP_Pos) /*!< 0x00000001 */
+#define DBGMCU_CR_DBG_SLEEP DBGMCU_CR_DBG_SLEEP_Msk /*!< Debug Sleep Mode */
+#define DBGMCU_CR_DBG_STOP_Pos (1U)
+#define DBGMCU_CR_DBG_STOP_Msk (0x1U << DBGMCU_CR_DBG_STOP_Pos) /*!< 0x00000002 */
+#define DBGMCU_CR_DBG_STOP DBGMCU_CR_DBG_STOP_Msk /*!< Debug Stop Mode */
+#define DBGMCU_CR_DBG_STANDBY_Pos (2U)
+#define DBGMCU_CR_DBG_STANDBY_Msk (0x1U << DBGMCU_CR_DBG_STANDBY_Pos) /*!< 0x00000004 */
+#define DBGMCU_CR_DBG_STANDBY DBGMCU_CR_DBG_STANDBY_Msk /*!< Debug Standby mode */
+#define DBGMCU_CR_TRACE_IOEN_Pos (5U)
+#define DBGMCU_CR_TRACE_IOEN_Msk (0x1U << DBGMCU_CR_TRACE_IOEN_Pos) /*!< 0x00000020 */
+#define DBGMCU_CR_TRACE_IOEN DBGMCU_CR_TRACE_IOEN_Msk /*!< Trace Pin Assignment Control */
+
+#define DBGMCU_CR_TRACE_MODE_Pos (6U)
+#define DBGMCU_CR_TRACE_MODE_Msk (0x3U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x000000C0 */
+#define DBGMCU_CR_TRACE_MODE DBGMCU_CR_TRACE_MODE_Msk /*!< TRACE_MODE[1:0] bits (Trace Pin Assignment Control) */
+#define DBGMCU_CR_TRACE_MODE_0 (0x1U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000040 */
+#define DBGMCU_CR_TRACE_MODE_1 (0x2U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000080 */
+
+#define DBGMCU_CR_DBG_IWDG_STOP_Pos (8U)
+#define DBGMCU_CR_DBG_IWDG_STOP_Msk (0x1U << DBGMCU_CR_DBG_IWDG_STOP_Pos) /*!< 0x00000100 */
+#define DBGMCU_CR_DBG_IWDG_STOP DBGMCU_CR_DBG_IWDG_STOP_Msk /*!< Debug Independent Watchdog stopped when Core is halted */
+#define DBGMCU_CR_DBG_WWDG_STOP_Pos (9U)
+#define DBGMCU_CR_DBG_WWDG_STOP_Msk (0x1U << DBGMCU_CR_DBG_WWDG_STOP_Pos) /*!< 0x00000200 */
+#define DBGMCU_CR_DBG_WWDG_STOP DBGMCU_CR_DBG_WWDG_STOP_Msk /*!< Debug Window Watchdog stopped when Core is halted */
+#define DBGMCU_CR_DBG_TIM1_STOP_Pos (10U)
+#define DBGMCU_CR_DBG_TIM1_STOP_Msk (0x1U << DBGMCU_CR_DBG_TIM1_STOP_Pos) /*!< 0x00000400 */
+#define DBGMCU_CR_DBG_TIM1_STOP DBGMCU_CR_DBG_TIM1_STOP_Msk /*!< TIM1 counter stopped when core is halted */
+#define DBGMCU_CR_DBG_TIM2_STOP_Pos (11U)
+#define DBGMCU_CR_DBG_TIM2_STOP_Msk (0x1U << DBGMCU_CR_DBG_TIM2_STOP_Pos) /*!< 0x00000800 */
+#define DBGMCU_CR_DBG_TIM2_STOP DBGMCU_CR_DBG_TIM2_STOP_Msk /*!< TIM2 counter stopped when core is halted */
+#define DBGMCU_CR_DBG_TIM3_STOP_Pos (12U)
+#define DBGMCU_CR_DBG_TIM3_STOP_Msk (0x1U << DBGMCU_CR_DBG_TIM3_STOP_Pos) /*!< 0x00001000 */
+#define DBGMCU_CR_DBG_TIM3_STOP DBGMCU_CR_DBG_TIM3_STOP_Msk /*!< TIM3 counter stopped when core is halted */
+#define DBGMCU_CR_DBG_TIM4_STOP_Pos (13U)
+#define DBGMCU_CR_DBG_TIM4_STOP_Msk (0x1U << DBGMCU_CR_DBG_TIM4_STOP_Pos) /*!< 0x00002000 */
+#define DBGMCU_CR_DBG_TIM4_STOP DBGMCU_CR_DBG_TIM4_STOP_Msk /*!< TIM4 counter stopped when core is halted */
+#define DBGMCU_CR_DBG_CAN1_STOP_Pos (14U)
+#define DBGMCU_CR_DBG_CAN1_STOP_Msk (0x1U << DBGMCU_CR_DBG_CAN1_STOP_Pos) /*!< 0x00004000 */
+#define DBGMCU_CR_DBG_CAN1_STOP DBGMCU_CR_DBG_CAN1_STOP_Msk /*!< Debug CAN1 stopped when Core is halted */
+#define DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT_Pos (15U)
+#define DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT_Msk (0x1U << DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT_Pos) /*!< 0x00008000 */
+#define DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT_Msk /*!< SMBUS timeout mode stopped when Core is halted */
+#define DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT_Pos (16U)
+#define DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT_Msk (0x1U << DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT_Pos) /*!< 0x00010000 */
+#define DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT_Msk /*!< SMBUS timeout mode stopped when Core is halted */
+#define DBGMCU_CR_DBG_TIM5_STOP_Pos (18U)
+#define DBGMCU_CR_DBG_TIM5_STOP_Msk (0x1U << DBGMCU_CR_DBG_TIM5_STOP_Pos) /*!< 0x00040000 */
+#define DBGMCU_CR_DBG_TIM5_STOP DBGMCU_CR_DBG_TIM5_STOP_Msk /*!< TIM5 counter stopped when core is halted */
+#define DBGMCU_CR_DBG_TIM6_STOP_Pos (19U)
+#define DBGMCU_CR_DBG_TIM6_STOP_Msk (0x1U << DBGMCU_CR_DBG_TIM6_STOP_Pos) /*!< 0x00080000 */
+#define DBGMCU_CR_DBG_TIM6_STOP DBGMCU_CR_DBG_TIM6_STOP_Msk /*!< TIM6 counter stopped when core is halted */
+#define DBGMCU_CR_DBG_TIM7_STOP_Pos (20U)
+#define DBGMCU_CR_DBG_TIM7_STOP_Msk (0x1U << DBGMCU_CR_DBG_TIM7_STOP_Pos) /*!< 0x00100000 */
+#define DBGMCU_CR_DBG_TIM7_STOP DBGMCU_CR_DBG_TIM7_STOP_Msk /*!< TIM7 counter stopped when core is halted */
+#define DBGMCU_CR_DBG_CAN2_STOP_Pos (21U)
+#define DBGMCU_CR_DBG_CAN2_STOP_Msk (0x1U << DBGMCU_CR_DBG_CAN2_STOP_Pos) /*!< 0x00200000 */
+#define DBGMCU_CR_DBG_CAN2_STOP DBGMCU_CR_DBG_CAN2_STOP_Msk /*!< Debug CAN2 stopped when Core is halted */
+#define DBGMCU_CR_DBG_TIM9_STOP_Pos (28U)
+#define DBGMCU_CR_DBG_TIM9_STOP_Msk (0x1U << DBGMCU_CR_DBG_TIM9_STOP_Pos) /*!< 0x10000000 */
+#define DBGMCU_CR_DBG_TIM9_STOP DBGMCU_CR_DBG_TIM9_STOP_Msk /*!< Debug TIM9 stopped when Core is halted */
+#define DBGMCU_CR_DBG_TIM10_STOP_Pos (29U)
+#define DBGMCU_CR_DBG_TIM10_STOP_Msk (0x1U << DBGMCU_CR_DBG_TIM10_STOP_Pos) /*!< 0x20000000 */
+#define DBGMCU_CR_DBG_TIM10_STOP DBGMCU_CR_DBG_TIM10_STOP_Msk /*!< Debug TIM10 stopped when Core is halted */
+#define DBGMCU_CR_DBG_TIM11_STOP_Pos (30U)
+#define DBGMCU_CR_DBG_TIM11_STOP_Msk (0x1U << DBGMCU_CR_DBG_TIM11_STOP_Pos) /*!< 0x40000000 */
+#define DBGMCU_CR_DBG_TIM11_STOP DBGMCU_CR_DBG_TIM11_STOP_Msk /*!< Debug TIM11 stopped when Core is halted */
+
+/******************************************************************************/
+/* */
+/* FLASH and Option Bytes Registers */
+/* */
+/******************************************************************************/
+/******************* Bit definition for FLASH_ACR register ******************/
+#define FLASH_ACR_LATENCY_Pos (0U)
+#define FLASH_ACR_LATENCY_Msk (0x7U << FLASH_ACR_LATENCY_Pos) /*!< 0x00000007 */
+#define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk /*!< LATENCY[2:0] bits (Latency) */
+#define FLASH_ACR_LATENCY_0 (0x1U << FLASH_ACR_LATENCY_Pos) /*!< 0x00000001 */
+#define FLASH_ACR_LATENCY_1 (0x2U << FLASH_ACR_LATENCY_Pos) /*!< 0x00000002 */
+#define FLASH_ACR_LATENCY_2 (0x4U << FLASH_ACR_LATENCY_Pos) /*!< 0x00000004 */
+
+#define FLASH_ACR_HLFCYA_Pos (3U)
+#define FLASH_ACR_HLFCYA_Msk (0x1U << FLASH_ACR_HLFCYA_Pos) /*!< 0x00000008 */
+#define FLASH_ACR_HLFCYA FLASH_ACR_HLFCYA_Msk /*!< Flash Half Cycle Access Enable */
+#define FLASH_ACR_PRFTBE_Pos (4U)
+#define FLASH_ACR_PRFTBE_Msk (0x1U << FLASH_ACR_PRFTBE_Pos) /*!< 0x00000010 */
+#define FLASH_ACR_PRFTBE FLASH_ACR_PRFTBE_Msk /*!< Prefetch Buffer Enable */
+#define FLASH_ACR_PRFTBS_Pos (5U)
+#define FLASH_ACR_PRFTBS_Msk (0x1U << FLASH_ACR_PRFTBS_Pos) /*!< 0x00000020 */
+#define FLASH_ACR_PRFTBS FLASH_ACR_PRFTBS_Msk /*!< Prefetch Buffer Status */
+
+/****************** Bit definition for FLASH_KEYR register ******************/
+#define FLASH_KEYR_FKEYR_Pos (0U)
+#define FLASH_KEYR_FKEYR_Msk (0xFFFFFFFFU << FLASH_KEYR_FKEYR_Pos) /*!< 0xFFFFFFFF */
+#define FLASH_KEYR_FKEYR FLASH_KEYR_FKEYR_Msk /*!< FPEC Key */
+
+#define RDP_KEY_Pos (0U)
+#define RDP_KEY_Msk (0xA5U << RDP_KEY_Pos) /*!< 0x000000A5 */
+#define RDP_KEY RDP_KEY_Msk /*!< RDP Key */
+#define FLASH_KEY1_Pos (0U)
+#define FLASH_KEY1_Msk (0x45670123U << FLASH_KEY1_Pos) /*!< 0x45670123 */
+#define FLASH_KEY1 FLASH_KEY1_Msk /*!< FPEC Key1 */
+#define FLASH_KEY2_Pos (0U)
+#define FLASH_KEY2_Msk (0xCDEF89ABU << FLASH_KEY2_Pos) /*!< 0xCDEF89AB */
+#define FLASH_KEY2 FLASH_KEY2_Msk /*!< FPEC Key2 */
+
+/***************** Bit definition for FLASH_OPTKEYR register ****************/
+#define FLASH_OPTKEYR_OPTKEYR_Pos (0U)
+#define FLASH_OPTKEYR_OPTKEYR_Msk (0xFFFFFFFFU << FLASH_OPTKEYR_OPTKEYR_Pos) /*!< 0xFFFFFFFF */
+#define FLASH_OPTKEYR_OPTKEYR FLASH_OPTKEYR_OPTKEYR_Msk /*!< Option Byte Key */
+
+#define FLASH_OPTKEY1 FLASH_KEY1 /*!< Option Byte Key1 */
+#define FLASH_OPTKEY2 FLASH_KEY2 /*!< Option Byte Key2 */
+
+/****************** Bit definition for FLASH_SR register ********************/
+#define FLASH_SR_BSY_Pos (0U)
+#define FLASH_SR_BSY_Msk (0x1U << FLASH_SR_BSY_Pos) /*!< 0x00000001 */
+#define FLASH_SR_BSY FLASH_SR_BSY_Msk /*!< Busy */
+#define FLASH_SR_PGERR_Pos (2U)
+#define FLASH_SR_PGERR_Msk (0x1U << FLASH_SR_PGERR_Pos) /*!< 0x00000004 */
+#define FLASH_SR_PGERR FLASH_SR_PGERR_Msk /*!< Programming Error */
+#define FLASH_SR_WRPRTERR_Pos (4U)
+#define FLASH_SR_WRPRTERR_Msk (0x1U << FLASH_SR_WRPRTERR_Pos) /*!< 0x00000010 */
+#define FLASH_SR_WRPRTERR FLASH_SR_WRPRTERR_Msk /*!< Write Protection Error */
+#define FLASH_SR_EOP_Pos (5U)
+#define FLASH_SR_EOP_Msk (0x1U << FLASH_SR_EOP_Pos) /*!< 0x00000020 */
+#define FLASH_SR_EOP FLASH_SR_EOP_Msk /*!< End of operation */
+
+/******************* Bit definition for FLASH_CR register *******************/
+#define FLASH_CR_PG_Pos (0U)
+#define FLASH_CR_PG_Msk (0x1U << FLASH_CR_PG_Pos) /*!< 0x00000001 */
+#define FLASH_CR_PG FLASH_CR_PG_Msk /*!< Programming */
+#define FLASH_CR_PER_Pos (1U)
+#define FLASH_CR_PER_Msk (0x1U << FLASH_CR_PER_Pos) /*!< 0x00000002 */
+#define FLASH_CR_PER FLASH_CR_PER_Msk /*!< Page Erase */
+#define FLASH_CR_MER_Pos (2U)
+#define FLASH_CR_MER_Msk (0x1U << FLASH_CR_MER_Pos) /*!< 0x00000004 */
+#define FLASH_CR_MER FLASH_CR_MER_Msk /*!< Mass Erase */
+#define FLASH_CR_OPTPG_Pos (4U)
+#define FLASH_CR_OPTPG_Msk (0x1U << FLASH_CR_OPTPG_Pos) /*!< 0x00000010 */
+#define FLASH_CR_OPTPG FLASH_CR_OPTPG_Msk /*!< Option Byte Programming */
+#define FLASH_CR_OPTER_Pos (5U)
+#define FLASH_CR_OPTER_Msk (0x1U << FLASH_CR_OPTER_Pos) /*!< 0x00000020 */
+#define FLASH_CR_OPTER FLASH_CR_OPTER_Msk /*!< Option Byte Erase */
+#define FLASH_CR_STRT_Pos (6U)
+#define FLASH_CR_STRT_Msk (0x1U << FLASH_CR_STRT_Pos) /*!< 0x00000040 */
+#define FLASH_CR_STRT FLASH_CR_STRT_Msk /*!< Start */
+#define FLASH_CR_LOCK_Pos (7U)
+#define FLASH_CR_LOCK_Msk (0x1U << FLASH_CR_LOCK_Pos) /*!< 0x00000080 */
+#define FLASH_CR_LOCK FLASH_CR_LOCK_Msk /*!< Lock */
+#define FLASH_CR_OPTWRE_Pos (9U)
+#define FLASH_CR_OPTWRE_Msk (0x1U << FLASH_CR_OPTWRE_Pos) /*!< 0x00000200 */
+#define FLASH_CR_OPTWRE FLASH_CR_OPTWRE_Msk /*!< Option Bytes Write Enable */
+#define FLASH_CR_ERRIE_Pos (10U)
+#define FLASH_CR_ERRIE_Msk (0x1U << FLASH_CR_ERRIE_Pos) /*!< 0x00000400 */
+#define FLASH_CR_ERRIE FLASH_CR_ERRIE_Msk /*!< Error Interrupt Enable */
+#define FLASH_CR_EOPIE_Pos (12U)
+#define FLASH_CR_EOPIE_Msk (0x1U << FLASH_CR_EOPIE_Pos) /*!< 0x00001000 */
+#define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk /*!< End of operation interrupt enable */
+
+/******************* Bit definition for FLASH_AR register *******************/
+#define FLASH_AR_FAR_Pos (0U)
+#define FLASH_AR_FAR_Msk (0xFFFFFFFFU << FLASH_AR_FAR_Pos) /*!< 0xFFFFFFFF */
+#define FLASH_AR_FAR FLASH_AR_FAR_Msk /*!< Flash Address */
+
+/****************** Bit definition for FLASH_OBR register *******************/
+#define FLASH_OBR_OPTERR_Pos (0U)
+#define FLASH_OBR_OPTERR_Msk (0x1U << FLASH_OBR_OPTERR_Pos) /*!< 0x00000001 */
+#define FLASH_OBR_OPTERR FLASH_OBR_OPTERR_Msk /*!< Option Byte Error */
+#define FLASH_OBR_RDPRT_Pos (1U)
+#define FLASH_OBR_RDPRT_Msk (0x1U << FLASH_OBR_RDPRT_Pos) /*!< 0x00000002 */
+#define FLASH_OBR_RDPRT FLASH_OBR_RDPRT_Msk /*!< Read protection */
+
+#define FLASH_OBR_IWDG_SW_Pos (2U)
+#define FLASH_OBR_IWDG_SW_Msk (0x1U << FLASH_OBR_IWDG_SW_Pos) /*!< 0x00000004 */
+#define FLASH_OBR_IWDG_SW FLASH_OBR_IWDG_SW_Msk /*!< IWDG SW */
+#define FLASH_OBR_nRST_STOP_Pos (3U)
+#define FLASH_OBR_nRST_STOP_Msk (0x1U << FLASH_OBR_nRST_STOP_Pos) /*!< 0x00000008 */
+#define FLASH_OBR_nRST_STOP FLASH_OBR_nRST_STOP_Msk /*!< nRST_STOP */
+#define FLASH_OBR_nRST_STDBY_Pos (4U)
+#define FLASH_OBR_nRST_STDBY_Msk (0x1U << FLASH_OBR_nRST_STDBY_Pos) /*!< 0x00000010 */
+#define FLASH_OBR_nRST_STDBY FLASH_OBR_nRST_STDBY_Msk /*!< nRST_STDBY */
+#define FLASH_OBR_USER_Pos (2U)
+#define FLASH_OBR_USER_Msk (0x7U << FLASH_OBR_USER_Pos) /*!< 0x0000001C */
+#define FLASH_OBR_USER FLASH_OBR_USER_Msk /*!< User Option Bytes */
+#define FLASH_OBR_DATA0_Pos (10U)
+#define FLASH_OBR_DATA0_Msk (0xFFU << FLASH_OBR_DATA0_Pos) /*!< 0x0003FC00 */
+#define FLASH_OBR_DATA0 FLASH_OBR_DATA0_Msk /*!< Data0 */
+#define FLASH_OBR_DATA1_Pos (18U)
+#define FLASH_OBR_DATA1_Msk (0xFFU << FLASH_OBR_DATA1_Pos) /*!< 0x03FC0000 */
+#define FLASH_OBR_DATA1 FLASH_OBR_DATA1_Msk /*!< Data1 */
+
+/****************** Bit definition for FLASH_WRPR register ******************/
+#define FLASH_WRPR_WRP_Pos (0U)
+#define FLASH_WRPR_WRP_Msk (0xFFFFFFFFU << FLASH_WRPR_WRP_Pos) /*!< 0xFFFFFFFF */
+#define FLASH_WRPR_WRP FLASH_WRPR_WRP_Msk /*!< Write Protect */
+
+/*----------------------------------------------------------------------------*/
+
+/****************** Bit definition for FLASH_RDP register *******************/
+#define FLASH_RDP_RDP_Pos (0U)
+#define FLASH_RDP_RDP_Msk (0xFFU << FLASH_RDP_RDP_Pos) /*!< 0x000000FF */
+#define FLASH_RDP_RDP FLASH_RDP_RDP_Msk /*!< Read protection option byte */
+#define FLASH_RDP_nRDP_Pos (8U)
+#define FLASH_RDP_nRDP_Msk (0xFFU << FLASH_RDP_nRDP_Pos) /*!< 0x0000FF00 */
+#define FLASH_RDP_nRDP FLASH_RDP_nRDP_Msk /*!< Read protection complemented option byte */
+
+/****************** Bit definition for FLASH_USER register ******************/
+#define FLASH_USER_USER_Pos (16U)
+#define FLASH_USER_USER_Msk (0xFFU << FLASH_USER_USER_Pos) /*!< 0x00FF0000 */
+#define FLASH_USER_USER FLASH_USER_USER_Msk /*!< User option byte */
+#define FLASH_USER_nUSER_Pos (24U)
+#define FLASH_USER_nUSER_Msk (0xFFU << FLASH_USER_nUSER_Pos) /*!< 0xFF000000 */
+#define FLASH_USER_nUSER FLASH_USER_nUSER_Msk /*!< User complemented option byte */
+
+/****************** Bit definition for FLASH_Data0 register *****************/
+#define FLASH_DATA0_DATA0_Pos (0U)
+#define FLASH_DATA0_DATA0_Msk (0xFFU << FLASH_DATA0_DATA0_Pos) /*!< 0x000000FF */
+#define FLASH_DATA0_DATA0 FLASH_DATA0_DATA0_Msk /*!< User data storage option byte */
+#define FLASH_DATA0_nDATA0_Pos (8U)
+#define FLASH_DATA0_nDATA0_Msk (0xFFU << FLASH_DATA0_nDATA0_Pos) /*!< 0x0000FF00 */
+#define FLASH_DATA0_nDATA0 FLASH_DATA0_nDATA0_Msk /*!< User data storage complemented option byte */
+
+/****************** Bit definition for FLASH_Data1 register *****************/
+#define FLASH_DATA1_DATA1_Pos (16U)
+#define FLASH_DATA1_DATA1_Msk (0xFFU << FLASH_DATA1_DATA1_Pos) /*!< 0x00FF0000 */
+#define FLASH_DATA1_DATA1 FLASH_DATA1_DATA1_Msk /*!< User data storage option byte */
+#define FLASH_DATA1_nDATA1_Pos (24U)
+#define FLASH_DATA1_nDATA1_Msk (0xFFU << FLASH_DATA1_nDATA1_Pos) /*!< 0xFF000000 */
+#define FLASH_DATA1_nDATA1 FLASH_DATA1_nDATA1_Msk /*!< User data storage complemented option byte */
+
+/****************** Bit definition for FLASH_WRP0 register ******************/
+#define FLASH_WRP0_WRP0_Pos (0U)
+#define FLASH_WRP0_WRP0_Msk (0xFFU << FLASH_WRP0_WRP0_Pos) /*!< 0x000000FF */
+#define FLASH_WRP0_WRP0 FLASH_WRP0_WRP0_Msk /*!< Flash memory write protection option bytes */
+#define FLASH_WRP0_nWRP0_Pos (8U)
+#define FLASH_WRP0_nWRP0_Msk (0xFFU << FLASH_WRP0_nWRP0_Pos) /*!< 0x0000FF00 */
+#define FLASH_WRP0_nWRP0 FLASH_WRP0_nWRP0_Msk /*!< Flash memory write protection complemented option bytes */
+
+/****************** Bit definition for FLASH_WRP1 register ******************/
+#define FLASH_WRP1_WRP1_Pos (16U)
+#define FLASH_WRP1_WRP1_Msk (0xFFU << FLASH_WRP1_WRP1_Pos) /*!< 0x00FF0000 */
+#define FLASH_WRP1_WRP1 FLASH_WRP1_WRP1_Msk /*!< Flash memory write protection option bytes */
+#define FLASH_WRP1_nWRP1_Pos (24U)
+#define FLASH_WRP1_nWRP1_Msk (0xFFU << FLASH_WRP1_nWRP1_Pos) /*!< 0xFF000000 */
+#define FLASH_WRP1_nWRP1 FLASH_WRP1_nWRP1_Msk /*!< Flash memory write protection complemented option bytes */
+
+/****************** Bit definition for FLASH_WRP2 register ******************/
+#define FLASH_WRP2_WRP2_Pos (0U)
+#define FLASH_WRP2_WRP2_Msk (0xFFU << FLASH_WRP2_WRP2_Pos) /*!< 0x000000FF */
+#define FLASH_WRP2_WRP2 FLASH_WRP2_WRP2_Msk /*!< Flash memory write protection option bytes */
+#define FLASH_WRP2_nWRP2_Pos (8U)
+#define FLASH_WRP2_nWRP2_Msk (0xFFU << FLASH_WRP2_nWRP2_Pos) /*!< 0x0000FF00 */
+#define FLASH_WRP2_nWRP2 FLASH_WRP2_nWRP2_Msk /*!< Flash memory write protection complemented option bytes */
+
+/****************** Bit definition for FLASH_WRP3 register ******************/
+#define FLASH_WRP3_WRP3_Pos (16U)
+#define FLASH_WRP3_WRP3_Msk (0xFFU << FLASH_WRP3_WRP3_Pos) /*!< 0x00FF0000 */
+#define FLASH_WRP3_WRP3 FLASH_WRP3_WRP3_Msk /*!< Flash memory write protection option bytes */
+#define FLASH_WRP3_nWRP3_Pos (24U)
+#define FLASH_WRP3_nWRP3_Msk (0xFFU << FLASH_WRP3_nWRP3_Pos) /*!< 0xFF000000 */
+#define FLASH_WRP3_nWRP3 FLASH_WRP3_nWRP3_Msk /*!< Flash memory write protection complemented option bytes */
+
+
+/******************************************************************************/
+/* */
+/* USB_OTG */
+/* */
+/******************************************************************************/
+
+/******************** Bit definition forUSB_OTG_GOTGCTL register ********************/
+#define USB_OTG_GOTGCTL_SRQSCS_Pos (0U)
+#define USB_OTG_GOTGCTL_SRQSCS_Msk (0x1U << USB_OTG_GOTGCTL_SRQSCS_Pos) /*!< 0x00000001 */
+#define USB_OTG_GOTGCTL_SRQSCS USB_OTG_GOTGCTL_SRQSCS_Msk /*!< Session request success */
+#define USB_OTG_GOTGCTL_SRQ_Pos (1U)
+#define USB_OTG_GOTGCTL_SRQ_Msk (0x1U << USB_OTG_GOTGCTL_SRQ_Pos) /*!< 0x00000002 */
+#define USB_OTG_GOTGCTL_SRQ USB_OTG_GOTGCTL_SRQ_Msk /*!< Session request */
+#define USB_OTG_GOTGCTL_HNGSCS_Pos (8U)
+#define USB_OTG_GOTGCTL_HNGSCS_Msk (0x1U << USB_OTG_GOTGCTL_HNGSCS_Pos) /*!< 0x00000100 */
+#define USB_OTG_GOTGCTL_HNGSCS USB_OTG_GOTGCTL_HNGSCS_Msk /*!< Host negotiation success */
+#define USB_OTG_GOTGCTL_HNPRQ_Pos (9U)
+#define USB_OTG_GOTGCTL_HNPRQ_Msk (0x1U << USB_OTG_GOTGCTL_HNPRQ_Pos) /*!< 0x00000200 */
+#define USB_OTG_GOTGCTL_HNPRQ USB_OTG_GOTGCTL_HNPRQ_Msk /*!< HNP request */
+#define USB_OTG_GOTGCTL_HSHNPEN_Pos (10U)
+#define USB_OTG_GOTGCTL_HSHNPEN_Msk (0x1U << USB_OTG_GOTGCTL_HSHNPEN_Pos) /*!< 0x00000400 */
+#define USB_OTG_GOTGCTL_HSHNPEN USB_OTG_GOTGCTL_HSHNPEN_Msk /*!< Host set HNP enable */
+#define USB_OTG_GOTGCTL_DHNPEN_Pos (11U)
+#define USB_OTG_GOTGCTL_DHNPEN_Msk (0x1U << USB_OTG_GOTGCTL_DHNPEN_Pos) /*!< 0x00000800 */
+#define USB_OTG_GOTGCTL_DHNPEN USB_OTG_GOTGCTL_DHNPEN_Msk /*!< Device HNP enabled */
+#define USB_OTG_GOTGCTL_CIDSTS_Pos (16U)
+#define USB_OTG_GOTGCTL_CIDSTS_Msk (0x1U << USB_OTG_GOTGCTL_CIDSTS_Pos) /*!< 0x00010000 */
+#define USB_OTG_GOTGCTL_CIDSTS USB_OTG_GOTGCTL_CIDSTS_Msk /*!< Connector ID status */
+#define USB_OTG_GOTGCTL_DBCT_Pos (17U)
+#define USB_OTG_GOTGCTL_DBCT_Msk (0x1U << USB_OTG_GOTGCTL_DBCT_Pos) /*!< 0x00020000 */
+#define USB_OTG_GOTGCTL_DBCT USB_OTG_GOTGCTL_DBCT_Msk /*!< Long/short debounce time */
+#define USB_OTG_GOTGCTL_ASVLD_Pos (18U)
+#define USB_OTG_GOTGCTL_ASVLD_Msk (0x1U << USB_OTG_GOTGCTL_ASVLD_Pos) /*!< 0x00040000 */
+#define USB_OTG_GOTGCTL_ASVLD USB_OTG_GOTGCTL_ASVLD_Msk /*!< A-session valid */
+#define USB_OTG_GOTGCTL_BSVLD_Pos (19U)
+#define USB_OTG_GOTGCTL_BSVLD_Msk (0x1U << USB_OTG_GOTGCTL_BSVLD_Pos) /*!< 0x00080000 */
+#define USB_OTG_GOTGCTL_BSVLD USB_OTG_GOTGCTL_BSVLD_Msk /*!< B-session valid */
+
+/******************** Bit definition forUSB_OTG_HCFG register ********************/
+
+#define USB_OTG_HCFG_FSLSPCS_Pos (0U)
+#define USB_OTG_HCFG_FSLSPCS_Msk (0x3U << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000003 */
+#define USB_OTG_HCFG_FSLSPCS USB_OTG_HCFG_FSLSPCS_Msk /*!< FS/LS PHY clock select */
+#define USB_OTG_HCFG_FSLSPCS_0 (0x1U << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000001 */
+#define USB_OTG_HCFG_FSLSPCS_1 (0x2U << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000002 */
+#define USB_OTG_HCFG_FSLSS_Pos (2U)
+#define USB_OTG_HCFG_FSLSS_Msk (0x1U << USB_OTG_HCFG_FSLSS_Pos) /*!< 0x00000004 */
+#define USB_OTG_HCFG_FSLSS USB_OTG_HCFG_FSLSS_Msk /*!< FS- and LS-only support */
+
+/******************** Bit definition forUSB_OTG_DCFG register ********************/
+
+#define USB_OTG_DCFG_DSPD_Pos (0U)
+#define USB_OTG_DCFG_DSPD_Msk (0x3U << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000003 */
+#define USB_OTG_DCFG_DSPD USB_OTG_DCFG_DSPD_Msk /*!< Device speed */
+#define USB_OTG_DCFG_DSPD_0 (0x1U << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000001 */
+#define USB_OTG_DCFG_DSPD_1 (0x2U << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000002 */
+#define USB_OTG_DCFG_NZLSOHSK_Pos (2U)
+#define USB_OTG_DCFG_NZLSOHSK_Msk (0x1U << USB_OTG_DCFG_NZLSOHSK_Pos) /*!< 0x00000004 */
+#define USB_OTG_DCFG_NZLSOHSK USB_OTG_DCFG_NZLSOHSK_Msk /*!< Nonzero-length status OUT handshake */
+
+#define USB_OTG_DCFG_DAD_Pos (4U)
+#define USB_OTG_DCFG_DAD_Msk (0x7FU << USB_OTG_DCFG_DAD_Pos) /*!< 0x000007F0 */
+#define USB_OTG_DCFG_DAD USB_OTG_DCFG_DAD_Msk /*!< Device address */
+#define USB_OTG_DCFG_DAD_0 (0x01U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000010 */
+#define USB_OTG_DCFG_DAD_1 (0x02U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000020 */
+#define USB_OTG_DCFG_DAD_2 (0x04U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000040 */
+#define USB_OTG_DCFG_DAD_3 (0x08U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000080 */
+#define USB_OTG_DCFG_DAD_4 (0x10U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000100 */
+#define USB_OTG_DCFG_DAD_5 (0x20U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000200 */
+#define USB_OTG_DCFG_DAD_6 (0x40U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000400 */
+
+#define USB_OTG_DCFG_PFIVL_Pos (11U)
+#define USB_OTG_DCFG_PFIVL_Msk (0x3U << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001800 */
+#define USB_OTG_DCFG_PFIVL USB_OTG_DCFG_PFIVL_Msk /*!< Periodic (micro)frame interval */
+#define USB_OTG_DCFG_PFIVL_0 (0x1U << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00000800 */
+#define USB_OTG_DCFG_PFIVL_1 (0x2U << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001000 */
+
+#define USB_OTG_DCFG_PERSCHIVL_Pos (24U)
+#define USB_OTG_DCFG_PERSCHIVL_Msk (0x3U << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x03000000 */
+#define USB_OTG_DCFG_PERSCHIVL USB_OTG_DCFG_PERSCHIVL_Msk /*!< Periodic scheduling interval */
+#define USB_OTG_DCFG_PERSCHIVL_0 (0x1U << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x01000000 */
+#define USB_OTG_DCFG_PERSCHIVL_1 (0x2U << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x02000000 */
+
+/******************** Bit definition forUSB_OTG_PCGCR register ********************/
+#define USB_OTG_PCGCR_STPPCLK_Pos (0U)
+#define USB_OTG_PCGCR_STPPCLK_Msk (0x1U << USB_OTG_PCGCR_STPPCLK_Pos) /*!< 0x00000001 */
+#define USB_OTG_PCGCR_STPPCLK USB_OTG_PCGCR_STPPCLK_Msk /*!< Stop PHY clock */
+#define USB_OTG_PCGCR_GATEHCLK_Pos (1U)
+#define USB_OTG_PCGCR_GATEHCLK_Msk (0x1U << USB_OTG_PCGCR_GATEHCLK_Pos) /*!< 0x00000002 */
+#define USB_OTG_PCGCR_GATEHCLK USB_OTG_PCGCR_GATEHCLK_Msk /*!< Gate HCLK */
+#define USB_OTG_PCGCR_PHYSUSP_Pos (4U)
+#define USB_OTG_PCGCR_PHYSUSP_Msk (0x1U << USB_OTG_PCGCR_PHYSUSP_Pos) /*!< 0x00000010 */
+#define USB_OTG_PCGCR_PHYSUSP USB_OTG_PCGCR_PHYSUSP_Msk /*!< PHY suspended */
+
+/******************** Bit definition forUSB_OTG_GOTGINT register ******************/
+#define USB_OTG_GOTGINT_SEDET_Pos (2U)
+#define USB_OTG_GOTGINT_SEDET_Msk (0x1U << USB_OTG_GOTGINT_SEDET_Pos) /*!< 0x00000004 */
+#define USB_OTG_GOTGINT_SEDET USB_OTG_GOTGINT_SEDET_Msk /*!< Session end detected */
+#define USB_OTG_GOTGINT_SRSSCHG_Pos (8U)
+#define USB_OTG_GOTGINT_SRSSCHG_Msk (0x1U << USB_OTG_GOTGINT_SRSSCHG_Pos) /*!< 0x00000100 */
+#define USB_OTG_GOTGINT_SRSSCHG USB_OTG_GOTGINT_SRSSCHG_Msk /*!< Session request success status change */
+#define USB_OTG_GOTGINT_HNSSCHG_Pos (9U)
+#define USB_OTG_GOTGINT_HNSSCHG_Msk (0x1U << USB_OTG_GOTGINT_HNSSCHG_Pos) /*!< 0x00000200 */
+#define USB_OTG_GOTGINT_HNSSCHG USB_OTG_GOTGINT_HNSSCHG_Msk /*!< Host negotiation success status change */
+#define USB_OTG_GOTGINT_HNGDET_Pos (17U)
+#define USB_OTG_GOTGINT_HNGDET_Msk (0x1U << USB_OTG_GOTGINT_HNGDET_Pos) /*!< 0x00020000 */
+#define USB_OTG_GOTGINT_HNGDET USB_OTG_GOTGINT_HNGDET_Msk /*!< Host negotiation detected */
+#define USB_OTG_GOTGINT_ADTOCHG_Pos (18U)
+#define USB_OTG_GOTGINT_ADTOCHG_Msk (0x1U << USB_OTG_GOTGINT_ADTOCHG_Pos) /*!< 0x00040000 */
+#define USB_OTG_GOTGINT_ADTOCHG USB_OTG_GOTGINT_ADTOCHG_Msk /*!< A-device timeout change */
+#define USB_OTG_GOTGINT_DBCDNE_Pos (19U)
+#define USB_OTG_GOTGINT_DBCDNE_Msk (0x1U << USB_OTG_GOTGINT_DBCDNE_Pos) /*!< 0x00080000 */
+#define USB_OTG_GOTGINT_DBCDNE USB_OTG_GOTGINT_DBCDNE_Msk /*!< Debounce done */
+
+/******************** Bit definition forUSB_OTG_DCTL register ********************/
+#define USB_OTG_DCTL_RWUSIG_Pos (0U)
+#define USB_OTG_DCTL_RWUSIG_Msk (0x1U << USB_OTG_DCTL_RWUSIG_Pos) /*!< 0x00000001 */
+#define USB_OTG_DCTL_RWUSIG USB_OTG_DCTL_RWUSIG_Msk /*!< Remote wakeup signaling */
+#define USB_OTG_DCTL_SDIS_Pos (1U)
+#define USB_OTG_DCTL_SDIS_Msk (0x1U << USB_OTG_DCTL_SDIS_Pos) /*!< 0x00000002 */
+#define USB_OTG_DCTL_SDIS USB_OTG_DCTL_SDIS_Msk /*!< Soft disconnect */
+#define USB_OTG_DCTL_GINSTS_Pos (2U)
+#define USB_OTG_DCTL_GINSTS_Msk (0x1U << USB_OTG_DCTL_GINSTS_Pos) /*!< 0x00000004 */
+#define USB_OTG_DCTL_GINSTS USB_OTG_DCTL_GINSTS_Msk /*!< Global IN NAK status */
+#define USB_OTG_DCTL_GONSTS_Pos (3U)
+#define USB_OTG_DCTL_GONSTS_Msk (0x1U << USB_OTG_DCTL_GONSTS_Pos) /*!< 0x00000008 */
+#define USB_OTG_DCTL_GONSTS USB_OTG_DCTL_GONSTS_Msk /*!< Global OUT NAK status */
+
+#define USB_OTG_DCTL_TCTL_Pos (4U)
+#define USB_OTG_DCTL_TCTL_Msk (0x7U << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000070 */
+#define USB_OTG_DCTL_TCTL USB_OTG_DCTL_TCTL_Msk /*!< Test control */
+#define USB_OTG_DCTL_TCTL_0 (0x1U << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000010 */
+#define USB_OTG_DCTL_TCTL_1 (0x2U << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000020 */
+#define USB_OTG_DCTL_TCTL_2 (0x4U << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000040 */
+#define USB_OTG_DCTL_SGINAK_Pos (7U)
+#define USB_OTG_DCTL_SGINAK_Msk (0x1U << USB_OTG_DCTL_SGINAK_Pos) /*!< 0x00000080 */
+#define USB_OTG_DCTL_SGINAK USB_OTG_DCTL_SGINAK_Msk /*!< Set global IN NAK */
+#define USB_OTG_DCTL_CGINAK_Pos (8U)
+#define USB_OTG_DCTL_CGINAK_Msk (0x1U << USB_OTG_DCTL_CGINAK_Pos) /*!< 0x00000100 */
+#define USB_OTG_DCTL_CGINAK USB_OTG_DCTL_CGINAK_Msk /*!< Clear global IN NAK */
+#define USB_OTG_DCTL_SGONAK_Pos (9U)
+#define USB_OTG_DCTL_SGONAK_Msk (0x1U << USB_OTG_DCTL_SGONAK_Pos) /*!< 0x00000200 */
+#define USB_OTG_DCTL_SGONAK USB_OTG_DCTL_SGONAK_Msk /*!< Set global OUT NAK */
+#define USB_OTG_DCTL_CGONAK_Pos (10U)
+#define USB_OTG_DCTL_CGONAK_Msk (0x1U << USB_OTG_DCTL_CGONAK_Pos) /*!< 0x00000400 */
+#define USB_OTG_DCTL_CGONAK USB_OTG_DCTL_CGONAK_Msk /*!< Clear global OUT NAK */
+#define USB_OTG_DCTL_POPRGDNE_Pos (11U)
+#define USB_OTG_DCTL_POPRGDNE_Msk (0x1U << USB_OTG_DCTL_POPRGDNE_Pos) /*!< 0x00000800 */
+#define USB_OTG_DCTL_POPRGDNE USB_OTG_DCTL_POPRGDNE_Msk /*!< Power-on programming done */
+
+/******************** Bit definition forUSB_OTG_HFIR register ********************/
+#define USB_OTG_HFIR_FRIVL_Pos (0U)
+#define USB_OTG_HFIR_FRIVL_Msk (0xFFFFU << USB_OTG_HFIR_FRIVL_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_HFIR_FRIVL USB_OTG_HFIR_FRIVL_Msk /*!< Frame interval */
+
+/******************** Bit definition forUSB_OTG_HFNUM register ********************/
+#define USB_OTG_HFNUM_FRNUM_Pos (0U)
+#define USB_OTG_HFNUM_FRNUM_Msk (0xFFFFU << USB_OTG_HFNUM_FRNUM_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_HFNUM_FRNUM USB_OTG_HFNUM_FRNUM_Msk /*!< Frame number */
+#define USB_OTG_HFNUM_FTREM_Pos (16U)
+#define USB_OTG_HFNUM_FTREM_Msk (0xFFFFU << USB_OTG_HFNUM_FTREM_Pos) /*!< 0xFFFF0000 */
+#define USB_OTG_HFNUM_FTREM USB_OTG_HFNUM_FTREM_Msk /*!< Frame time remaining */
+
+/******************** Bit definition forUSB_OTG_DSTS register ********************/
+#define USB_OTG_DSTS_SUSPSTS_Pos (0U)
+#define USB_OTG_DSTS_SUSPSTS_Msk (0x1U << USB_OTG_DSTS_SUSPSTS_Pos) /*!< 0x00000001 */
+#define USB_OTG_DSTS_SUSPSTS USB_OTG_DSTS_SUSPSTS_Msk /*!< Suspend status */
+
+#define USB_OTG_DSTS_ENUMSPD_Pos (1U)
+#define USB_OTG_DSTS_ENUMSPD_Msk (0x3U << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000006 */
+#define USB_OTG_DSTS_ENUMSPD USB_OTG_DSTS_ENUMSPD_Msk /*!< Enumerated speed */
+#define USB_OTG_DSTS_ENUMSPD_0 (0x1U << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000002 */
+#define USB_OTG_DSTS_ENUMSPD_1 (0x2U << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000004 */
+#define USB_OTG_DSTS_EERR_Pos (3U)
+#define USB_OTG_DSTS_EERR_Msk (0x1U << USB_OTG_DSTS_EERR_Pos) /*!< 0x00000008 */
+#define USB_OTG_DSTS_EERR USB_OTG_DSTS_EERR_Msk /*!< Erratic error */
+#define USB_OTG_DSTS_FNSOF_Pos (8U)
+#define USB_OTG_DSTS_FNSOF_Msk (0x3FFFU << USB_OTG_DSTS_FNSOF_Pos) /*!< 0x003FFF00 */
+#define USB_OTG_DSTS_FNSOF USB_OTG_DSTS_FNSOF_Msk /*!< Frame number of the received SOF */
+
+/******************** Bit definition forUSB_OTG_GAHBCFG register *****************/
+#define USB_OTG_GAHBCFG_GINT_Pos (0U)
+#define USB_OTG_GAHBCFG_GINT_Msk (0x1U << USB_OTG_GAHBCFG_GINT_Pos) /*!< 0x00000001 */
+#define USB_OTG_GAHBCFG_GINT USB_OTG_GAHBCFG_GINT_Msk /*!< Global interrupt mask */
+
+#define USB_OTG_GAHBCFG_HBSTLEN_Pos (1U)
+#define USB_OTG_GAHBCFG_HBSTLEN_Msk (0xFU << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x0000001E */
+#define USB_OTG_GAHBCFG_HBSTLEN USB_OTG_GAHBCFG_HBSTLEN_Msk /*!< Burst length/type */
+#define USB_OTG_GAHBCFG_HBSTLEN_0 (0x1U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x00000002 */
+#define USB_OTG_GAHBCFG_HBSTLEN_1 (0x2U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x00000004 */
+#define USB_OTG_GAHBCFG_HBSTLEN_2 (0x4U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x00000008 */
+#define USB_OTG_GAHBCFG_HBSTLEN_3 (0x8U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x00000010 */
+#define USB_OTG_GAHBCFG_DMAEN_Pos (5U)
+#define USB_OTG_GAHBCFG_DMAEN_Msk (0x1U << USB_OTG_GAHBCFG_DMAEN_Pos) /*!< 0x00000020 */
+#define USB_OTG_GAHBCFG_DMAEN USB_OTG_GAHBCFG_DMAEN_Msk /*!< DMA enable */
+#define USB_OTG_GAHBCFG_TXFELVL_Pos (7U)
+#define USB_OTG_GAHBCFG_TXFELVL_Msk (0x1U << USB_OTG_GAHBCFG_TXFELVL_Pos) /*!< 0x00000080 */
+#define USB_OTG_GAHBCFG_TXFELVL USB_OTG_GAHBCFG_TXFELVL_Msk /*!< TxFIFO empty level */
+#define USB_OTG_GAHBCFG_PTXFELVL_Pos (8U)
+#define USB_OTG_GAHBCFG_PTXFELVL_Msk (0x1U << USB_OTG_GAHBCFG_PTXFELVL_Pos) /*!< 0x00000100 */
+#define USB_OTG_GAHBCFG_PTXFELVL USB_OTG_GAHBCFG_PTXFELVL_Msk /*!< Periodic TxFIFO empty level */
+
+/******************** Bit definition forUSB_OTG_GUSBCFG register *****************/
+
+#define USB_OTG_GUSBCFG_TOCAL_Pos (0U)
+#define USB_OTG_GUSBCFG_TOCAL_Msk (0x7U << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000007 */
+#define USB_OTG_GUSBCFG_TOCAL USB_OTG_GUSBCFG_TOCAL_Msk /*!< FS timeout calibration */
+#define USB_OTG_GUSBCFG_TOCAL_0 (0x1U << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000001 */
+#define USB_OTG_GUSBCFG_TOCAL_1 (0x2U << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000002 */
+#define USB_OTG_GUSBCFG_TOCAL_2 (0x4U << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000004 */
+#define USB_OTG_GUSBCFG_PHYSEL_Pos (6U)
+#define USB_OTG_GUSBCFG_PHYSEL_Msk (0x1U << USB_OTG_GUSBCFG_PHYSEL_Pos) /*!< 0x00000040 */
+#define USB_OTG_GUSBCFG_PHYSEL USB_OTG_GUSBCFG_PHYSEL_Msk /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */
+#define USB_OTG_GUSBCFG_SRPCAP_Pos (8U)
+#define USB_OTG_GUSBCFG_SRPCAP_Msk (0x1U << USB_OTG_GUSBCFG_SRPCAP_Pos) /*!< 0x00000100 */
+#define USB_OTG_GUSBCFG_SRPCAP USB_OTG_GUSBCFG_SRPCAP_Msk /*!< SRP-capable */
+#define USB_OTG_GUSBCFG_HNPCAP_Pos (9U)
+#define USB_OTG_GUSBCFG_HNPCAP_Msk (0x1U << USB_OTG_GUSBCFG_HNPCAP_Pos) /*!< 0x00000200 */
+#define USB_OTG_GUSBCFG_HNPCAP USB_OTG_GUSBCFG_HNPCAP_Msk /*!< HNP-capable */
+
+#define USB_OTG_GUSBCFG_TRDT_Pos (10U)
+#define USB_OTG_GUSBCFG_TRDT_Msk (0xFU << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00003C00 */
+#define USB_OTG_GUSBCFG_TRDT USB_OTG_GUSBCFG_TRDT_Msk /*!< USB turnaround time */
+#define USB_OTG_GUSBCFG_TRDT_0 (0x1U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000400 */
+#define USB_OTG_GUSBCFG_TRDT_1 (0x2U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000800 */
+#define USB_OTG_GUSBCFG_TRDT_2 (0x4U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00001000 */
+#define USB_OTG_GUSBCFG_TRDT_3 (0x8U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00002000 */
+#define USB_OTG_GUSBCFG_PHYLPCS_Pos (15U)
+#define USB_OTG_GUSBCFG_PHYLPCS_Msk (0x1U << USB_OTG_GUSBCFG_PHYLPCS_Pos) /*!< 0x00008000 */
+#define USB_OTG_GUSBCFG_PHYLPCS USB_OTG_GUSBCFG_PHYLPCS_Msk /*!< PHY Low-power clock select */
+#define USB_OTG_GUSBCFG_ULPIFSLS_Pos (17U)
+#define USB_OTG_GUSBCFG_ULPIFSLS_Msk (0x1U << USB_OTG_GUSBCFG_ULPIFSLS_Pos) /*!< 0x00020000 */
+#define USB_OTG_GUSBCFG_ULPIFSLS USB_OTG_GUSBCFG_ULPIFSLS_Msk /*!< ULPI FS/LS select */
+#define USB_OTG_GUSBCFG_ULPIAR_Pos (18U)
+#define USB_OTG_GUSBCFG_ULPIAR_Msk (0x1U << USB_OTG_GUSBCFG_ULPIAR_Pos) /*!< 0x00040000 */
+#define USB_OTG_GUSBCFG_ULPIAR USB_OTG_GUSBCFG_ULPIAR_Msk /*!< ULPI Auto-resume */
+#define USB_OTG_GUSBCFG_ULPICSM_Pos (19U)
+#define USB_OTG_GUSBCFG_ULPICSM_Msk (0x1U << USB_OTG_GUSBCFG_ULPICSM_Pos) /*!< 0x00080000 */
+#define USB_OTG_GUSBCFG_ULPICSM USB_OTG_GUSBCFG_ULPICSM_Msk /*!< ULPI Clock SuspendM */
+#define USB_OTG_GUSBCFG_ULPIEVBUSD_Pos (20U)
+#define USB_OTG_GUSBCFG_ULPIEVBUSD_Msk (0x1U << USB_OTG_GUSBCFG_ULPIEVBUSD_Pos) /*!< 0x00100000 */
+#define USB_OTG_GUSBCFG_ULPIEVBUSD USB_OTG_GUSBCFG_ULPIEVBUSD_Msk /*!< ULPI External VBUS Drive */
+#define USB_OTG_GUSBCFG_ULPIEVBUSI_Pos (21U)
+#define USB_OTG_GUSBCFG_ULPIEVBUSI_Msk (0x1U << USB_OTG_GUSBCFG_ULPIEVBUSI_Pos) /*!< 0x00200000 */
+#define USB_OTG_GUSBCFG_ULPIEVBUSI USB_OTG_GUSBCFG_ULPIEVBUSI_Msk /*!< ULPI external VBUS indicator */
+#define USB_OTG_GUSBCFG_TSDPS_Pos (22U)
+#define USB_OTG_GUSBCFG_TSDPS_Msk (0x1U << USB_OTG_GUSBCFG_TSDPS_Pos) /*!< 0x00400000 */
+#define USB_OTG_GUSBCFG_TSDPS USB_OTG_GUSBCFG_TSDPS_Msk /*!< TermSel DLine pulsing selection */
+#define USB_OTG_GUSBCFG_PCCI_Pos (23U)
+#define USB_OTG_GUSBCFG_PCCI_Msk (0x1U << USB_OTG_GUSBCFG_PCCI_Pos) /*!< 0x00800000 */
+#define USB_OTG_GUSBCFG_PCCI USB_OTG_GUSBCFG_PCCI_Msk /*!< Indicator complement */
+#define USB_OTG_GUSBCFG_PTCI_Pos (24U)
+#define USB_OTG_GUSBCFG_PTCI_Msk (0x1U << USB_OTG_GUSBCFG_PTCI_Pos) /*!< 0x01000000 */
+#define USB_OTG_GUSBCFG_PTCI USB_OTG_GUSBCFG_PTCI_Msk /*!< Indicator pass through */
+#define USB_OTG_GUSBCFG_ULPIIPD_Pos (25U)
+#define USB_OTG_GUSBCFG_ULPIIPD_Msk (0x1U << USB_OTG_GUSBCFG_ULPIIPD_Pos) /*!< 0x02000000 */
+#define USB_OTG_GUSBCFG_ULPIIPD USB_OTG_GUSBCFG_ULPIIPD_Msk /*!< ULPI interface protect disable */
+#define USB_OTG_GUSBCFG_FHMOD_Pos (29U)
+#define USB_OTG_GUSBCFG_FHMOD_Msk (0x1U << USB_OTG_GUSBCFG_FHMOD_Pos) /*!< 0x20000000 */
+#define USB_OTG_GUSBCFG_FHMOD USB_OTG_GUSBCFG_FHMOD_Msk /*!< Forced host mode */
+#define USB_OTG_GUSBCFG_FDMOD_Pos (30U)
+#define USB_OTG_GUSBCFG_FDMOD_Msk (0x1U << USB_OTG_GUSBCFG_FDMOD_Pos) /*!< 0x40000000 */
+#define USB_OTG_GUSBCFG_FDMOD USB_OTG_GUSBCFG_FDMOD_Msk /*!< Forced peripheral mode */
+#define USB_OTG_GUSBCFG_CTXPKT_Pos (31U)
+#define USB_OTG_GUSBCFG_CTXPKT_Msk (0x1U << USB_OTG_GUSBCFG_CTXPKT_Pos) /*!< 0x80000000 */
+#define USB_OTG_GUSBCFG_CTXPKT USB_OTG_GUSBCFG_CTXPKT_Msk /*!< Corrupt Tx packet */
+
+/******************** Bit definition forUSB_OTG_GRSTCTL register *****************/
+#define USB_OTG_GRSTCTL_CSRST_Pos (0U)
+#define USB_OTG_GRSTCTL_CSRST_Msk (0x1U << USB_OTG_GRSTCTL_CSRST_Pos) /*!< 0x00000001 */
+#define USB_OTG_GRSTCTL_CSRST USB_OTG_GRSTCTL_CSRST_Msk /*!< Core soft reset */
+#define USB_OTG_GRSTCTL_HSRST_Pos (1U)
+#define USB_OTG_GRSTCTL_HSRST_Msk (0x1U << USB_OTG_GRSTCTL_HSRST_Pos) /*!< 0x00000002 */
+#define USB_OTG_GRSTCTL_HSRST USB_OTG_GRSTCTL_HSRST_Msk /*!< HCLK soft reset */
+#define USB_OTG_GRSTCTL_FCRST_Pos (2U)
+#define USB_OTG_GRSTCTL_FCRST_Msk (0x1U << USB_OTG_GRSTCTL_FCRST_Pos) /*!< 0x00000004 */
+#define USB_OTG_GRSTCTL_FCRST USB_OTG_GRSTCTL_FCRST_Msk /*!< Host frame counter reset */
+#define USB_OTG_GRSTCTL_RXFFLSH_Pos (4U)
+#define USB_OTG_GRSTCTL_RXFFLSH_Msk (0x1U << USB_OTG_GRSTCTL_RXFFLSH_Pos) /*!< 0x00000010 */
+#define USB_OTG_GRSTCTL_RXFFLSH USB_OTG_GRSTCTL_RXFFLSH_Msk /*!< RxFIFO flush */
+#define USB_OTG_GRSTCTL_TXFFLSH_Pos (5U)
+#define USB_OTG_GRSTCTL_TXFFLSH_Msk (0x1U << USB_OTG_GRSTCTL_TXFFLSH_Pos) /*!< 0x00000020 */
+#define USB_OTG_GRSTCTL_TXFFLSH USB_OTG_GRSTCTL_TXFFLSH_Msk /*!< TxFIFO flush */
+
+#define USB_OTG_GRSTCTL_TXFNUM_Pos (6U)
+#define USB_OTG_GRSTCTL_TXFNUM_Msk (0x1FU << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x000007C0 */
+#define USB_OTG_GRSTCTL_TXFNUM USB_OTG_GRSTCTL_TXFNUM_Msk /*!< TxFIFO number */
+#define USB_OTG_GRSTCTL_TXFNUM_0 (0x01U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000040 */
+#define USB_OTG_GRSTCTL_TXFNUM_1 (0x02U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000080 */
+#define USB_OTG_GRSTCTL_TXFNUM_2 (0x04U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000100 */
+#define USB_OTG_GRSTCTL_TXFNUM_3 (0x08U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000200 */
+#define USB_OTG_GRSTCTL_TXFNUM_4 (0x10U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000400 */
+#define USB_OTG_GRSTCTL_DMAREQ_Pos (30U)
+#define USB_OTG_GRSTCTL_DMAREQ_Msk (0x1U << USB_OTG_GRSTCTL_DMAREQ_Pos) /*!< 0x40000000 */
+#define USB_OTG_GRSTCTL_DMAREQ USB_OTG_GRSTCTL_DMAREQ_Msk /*!< DMA request signal */
+#define USB_OTG_GRSTCTL_AHBIDL_Pos (31U)
+#define USB_OTG_GRSTCTL_AHBIDL_Msk (0x1U << USB_OTG_GRSTCTL_AHBIDL_Pos) /*!< 0x80000000 */
+#define USB_OTG_GRSTCTL_AHBIDL USB_OTG_GRSTCTL_AHBIDL_Msk /*!< AHB master idle */
+
+/******************** Bit definition forUSB_OTG_DIEPMSK register *****************/
+#define USB_OTG_DIEPMSK_XFRCM_Pos (0U)
+#define USB_OTG_DIEPMSK_XFRCM_Msk (0x1U << USB_OTG_DIEPMSK_XFRCM_Pos) /*!< 0x00000001 */
+#define USB_OTG_DIEPMSK_XFRCM USB_OTG_DIEPMSK_XFRCM_Msk /*!< Transfer completed interrupt mask */
+#define USB_OTG_DIEPMSK_EPDM_Pos (1U)
+#define USB_OTG_DIEPMSK_EPDM_Msk (0x1U << USB_OTG_DIEPMSK_EPDM_Pos) /*!< 0x00000002 */
+#define USB_OTG_DIEPMSK_EPDM USB_OTG_DIEPMSK_EPDM_Msk /*!< Endpoint disabled interrupt mask */
+#define USB_OTG_DIEPMSK_TOM_Pos (3U)
+#define USB_OTG_DIEPMSK_TOM_Msk (0x1U << USB_OTG_DIEPMSK_TOM_Pos) /*!< 0x00000008 */
+#define USB_OTG_DIEPMSK_TOM USB_OTG_DIEPMSK_TOM_Msk /*!< Timeout condition mask (nonisochronous endpoints) */
+#define USB_OTG_DIEPMSK_ITTXFEMSK_Pos (4U)
+#define USB_OTG_DIEPMSK_ITTXFEMSK_Msk (0x1U << USB_OTG_DIEPMSK_ITTXFEMSK_Pos) /*!< 0x00000010 */
+#define USB_OTG_DIEPMSK_ITTXFEMSK USB_OTG_DIEPMSK_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */
+#define USB_OTG_DIEPMSK_INEPNMM_Pos (5U)
+#define USB_OTG_DIEPMSK_INEPNMM_Msk (0x1U << USB_OTG_DIEPMSK_INEPNMM_Pos) /*!< 0x00000020 */
+#define USB_OTG_DIEPMSK_INEPNMM USB_OTG_DIEPMSK_INEPNMM_Msk /*!< IN token received with EP mismatch mask */
+#define USB_OTG_DIEPMSK_INEPNEM_Pos (6U)
+#define USB_OTG_DIEPMSK_INEPNEM_Msk (0x1U << USB_OTG_DIEPMSK_INEPNEM_Pos) /*!< 0x00000040 */
+#define USB_OTG_DIEPMSK_INEPNEM USB_OTG_DIEPMSK_INEPNEM_Msk /*!< IN endpoint NAK effective mask */
+#define USB_OTG_DIEPMSK_TXFURM_Pos (8U)
+#define USB_OTG_DIEPMSK_TXFURM_Msk (0x1U << USB_OTG_DIEPMSK_TXFURM_Pos) /*!< 0x00000100 */
+#define USB_OTG_DIEPMSK_TXFURM USB_OTG_DIEPMSK_TXFURM_Msk /*!< FIFO underrun mask */
+#define USB_OTG_DIEPMSK_BIM_Pos (9U)
+#define USB_OTG_DIEPMSK_BIM_Msk (0x1U << USB_OTG_DIEPMSK_BIM_Pos) /*!< 0x00000200 */
+#define USB_OTG_DIEPMSK_BIM USB_OTG_DIEPMSK_BIM_Msk /*!< BNA interrupt mask */
+
+/******************** Bit definition forUSB_OTG_HPTXSTS register *****************/
+#define USB_OTG_HPTXSTS_PTXFSAVL_Pos (0U)
+#define USB_OTG_HPTXSTS_PTXFSAVL_Msk (0xFFFFU << USB_OTG_HPTXSTS_PTXFSAVL_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_HPTXSTS_PTXFSAVL USB_OTG_HPTXSTS_PTXFSAVL_Msk /*!< Periodic transmit data FIFO space available */
+
+#define USB_OTG_HPTXSTS_PTXQSAV_Pos (16U)
+#define USB_OTG_HPTXSTS_PTXQSAV_Msk (0xFFU << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00FF0000 */
+#define USB_OTG_HPTXSTS_PTXQSAV USB_OTG_HPTXSTS_PTXQSAV_Msk /*!< Periodic transmit request queue space available */
+#define USB_OTG_HPTXSTS_PTXQSAV_0 (0x01U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00010000 */
+#define USB_OTG_HPTXSTS_PTXQSAV_1 (0x02U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00020000 */
+#define USB_OTG_HPTXSTS_PTXQSAV_2 (0x04U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00040000 */
+#define USB_OTG_HPTXSTS_PTXQSAV_3 (0x08U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00080000 */
+#define USB_OTG_HPTXSTS_PTXQSAV_4 (0x10U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00100000 */
+#define USB_OTG_HPTXSTS_PTXQSAV_5 (0x20U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00200000 */
+#define USB_OTG_HPTXSTS_PTXQSAV_6 (0x40U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00400000 */
+#define USB_OTG_HPTXSTS_PTXQSAV_7 (0x80U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00800000 */
+
+#define USB_OTG_HPTXSTS_PTXQTOP_Pos (24U)
+#define USB_OTG_HPTXSTS_PTXQTOP_Msk (0xFFU << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0xFF000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP USB_OTG_HPTXSTS_PTXQTOP_Msk /*!< Top of the periodic transmit request queue */
+#define USB_OTG_HPTXSTS_PTXQTOP_0 (0x01U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x01000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP_1 (0x02U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x02000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP_2 (0x04U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x04000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP_3 (0x08U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x08000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP_4 (0x10U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x10000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP_5 (0x20U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x20000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP_6 (0x40U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x40000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP_7 (0x80U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x80000000 */
+
+/******************** Bit definition forUSB_OTG_HAINT register *******************/
+#define USB_OTG_HAINT_HAINT_Pos (0U)
+#define USB_OTG_HAINT_HAINT_Msk (0xFFFFU << USB_OTG_HAINT_HAINT_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_HAINT_HAINT USB_OTG_HAINT_HAINT_Msk /*!< Channel interrupts */
+
+/******************** Bit definition forUSB_OTG_DOEPMSK register *****************/
+#define USB_OTG_DOEPMSK_XFRCM_Pos (0U)
+#define USB_OTG_DOEPMSK_XFRCM_Msk (0x1U << USB_OTG_DOEPMSK_XFRCM_Pos) /*!< 0x00000001 */
+#define USB_OTG_DOEPMSK_XFRCM USB_OTG_DOEPMSK_XFRCM_Msk /*!< Transfer completed interrupt mask */
+#define USB_OTG_DOEPMSK_EPDM_Pos (1U)
+#define USB_OTG_DOEPMSK_EPDM_Msk (0x1U << USB_OTG_DOEPMSK_EPDM_Pos) /*!< 0x00000002 */
+#define USB_OTG_DOEPMSK_EPDM USB_OTG_DOEPMSK_EPDM_Msk /*!< Endpoint disabled interrupt mask */
+#define USB_OTG_DOEPMSK_STUPM_Pos (3U)
+#define USB_OTG_DOEPMSK_STUPM_Msk (0x1U << USB_OTG_DOEPMSK_STUPM_Pos) /*!< 0x00000008 */
+#define USB_OTG_DOEPMSK_STUPM USB_OTG_DOEPMSK_STUPM_Msk /*!< SETUP phase done mask */
+#define USB_OTG_DOEPMSK_OTEPDM_Pos (4U)
+#define USB_OTG_DOEPMSK_OTEPDM_Msk (0x1U << USB_OTG_DOEPMSK_OTEPDM_Pos) /*!< 0x00000010 */
+#define USB_OTG_DOEPMSK_OTEPDM USB_OTG_DOEPMSK_OTEPDM_Msk /*!< OUT token received when endpoint disabled mask */
+#define USB_OTG_DOEPMSK_B2BSTUP_Pos (6U)
+#define USB_OTG_DOEPMSK_B2BSTUP_Msk (0x1U << USB_OTG_DOEPMSK_B2BSTUP_Pos) /*!< 0x00000040 */
+#define USB_OTG_DOEPMSK_B2BSTUP USB_OTG_DOEPMSK_B2BSTUP_Msk /*!< Back-to-back SETUP packets received mask */
+#define USB_OTG_DOEPMSK_OPEM_Pos (8U)
+#define USB_OTG_DOEPMSK_OPEM_Msk (0x1U << USB_OTG_DOEPMSK_OPEM_Pos) /*!< 0x00000100 */
+#define USB_OTG_DOEPMSK_OPEM USB_OTG_DOEPMSK_OPEM_Msk /*!< OUT packet error mask */
+#define USB_OTG_DOEPMSK_BOIM_Pos (9U)
+#define USB_OTG_DOEPMSK_BOIM_Msk (0x1U << USB_OTG_DOEPMSK_BOIM_Pos) /*!< 0x00000200 */
+#define USB_OTG_DOEPMSK_BOIM USB_OTG_DOEPMSK_BOIM_Msk /*!< BNA interrupt mask */
+
+/******************** Bit definition forUSB_OTG_GINTSTS register *****************/
+#define USB_OTG_GINTSTS_CMOD_Pos (0U)
+#define USB_OTG_GINTSTS_CMOD_Msk (0x1U << USB_OTG_GINTSTS_CMOD_Pos) /*!< 0x00000001 */
+#define USB_OTG_GINTSTS_CMOD USB_OTG_GINTSTS_CMOD_Msk /*!< Current mode of operation */
+#define USB_OTG_GINTSTS_MMIS_Pos (1U)
+#define USB_OTG_GINTSTS_MMIS_Msk (0x1U << USB_OTG_GINTSTS_MMIS_Pos) /*!< 0x00000002 */
+#define USB_OTG_GINTSTS_MMIS USB_OTG_GINTSTS_MMIS_Msk /*!< Mode mismatch interrupt */
+#define USB_OTG_GINTSTS_OTGINT_Pos (2U)
+#define USB_OTG_GINTSTS_OTGINT_Msk (0x1U << USB_OTG_GINTSTS_OTGINT_Pos) /*!< 0x00000004 */
+#define USB_OTG_GINTSTS_OTGINT USB_OTG_GINTSTS_OTGINT_Msk /*!< OTG interrupt */
+#define USB_OTG_GINTSTS_SOF_Pos (3U)
+#define USB_OTG_GINTSTS_SOF_Msk (0x1U << USB_OTG_GINTSTS_SOF_Pos) /*!< 0x00000008 */
+#define USB_OTG_GINTSTS_SOF USB_OTG_GINTSTS_SOF_Msk /*!< Start of frame */
+#define USB_OTG_GINTSTS_RXFLVL_Pos (4U)
+#define USB_OTG_GINTSTS_RXFLVL_Msk (0x1U << USB_OTG_GINTSTS_RXFLVL_Pos) /*!< 0x00000010 */
+#define USB_OTG_GINTSTS_RXFLVL USB_OTG_GINTSTS_RXFLVL_Msk /*!< RxFIFO nonempty */
+#define USB_OTG_GINTSTS_NPTXFE_Pos (5U)
+#define USB_OTG_GINTSTS_NPTXFE_Msk (0x1U << USB_OTG_GINTSTS_NPTXFE_Pos) /*!< 0x00000020 */
+#define USB_OTG_GINTSTS_NPTXFE USB_OTG_GINTSTS_NPTXFE_Msk /*!< Nonperiodic TxFIFO empty */
+#define USB_OTG_GINTSTS_GINAKEFF_Pos (6U)
+#define USB_OTG_GINTSTS_GINAKEFF_Msk (0x1U << USB_OTG_GINTSTS_GINAKEFF_Pos) /*!< 0x00000040 */
+#define USB_OTG_GINTSTS_GINAKEFF USB_OTG_GINTSTS_GINAKEFF_Msk /*!< Global IN nonperiodic NAK effective */
+#define USB_OTG_GINTSTS_BOUTNAKEFF_Pos (7U)
+#define USB_OTG_GINTSTS_BOUTNAKEFF_Msk (0x1U << USB_OTG_GINTSTS_BOUTNAKEFF_Pos) /*!< 0x00000080 */
+#define USB_OTG_GINTSTS_BOUTNAKEFF USB_OTG_GINTSTS_BOUTNAKEFF_Msk /*!< Global OUT NAK effective */
+#define USB_OTG_GINTSTS_ESUSP_Pos (10U)
+#define USB_OTG_GINTSTS_ESUSP_Msk (0x1U << USB_OTG_GINTSTS_ESUSP_Pos) /*!< 0x00000400 */
+#define USB_OTG_GINTSTS_ESUSP USB_OTG_GINTSTS_ESUSP_Msk /*!< Early suspend */
+#define USB_OTG_GINTSTS_USBSUSP_Pos (11U)
+#define USB_OTG_GINTSTS_USBSUSP_Msk (0x1U << USB_OTG_GINTSTS_USBSUSP_Pos) /*!< 0x00000800 */
+#define USB_OTG_GINTSTS_USBSUSP USB_OTG_GINTSTS_USBSUSP_Msk /*!< USB suspend */
+#define USB_OTG_GINTSTS_USBRST_Pos (12U)
+#define USB_OTG_GINTSTS_USBRST_Msk (0x1U << USB_OTG_GINTSTS_USBRST_Pos) /*!< 0x00001000 */
+#define USB_OTG_GINTSTS_USBRST USB_OTG_GINTSTS_USBRST_Msk /*!< USB reset */
+#define USB_OTG_GINTSTS_ENUMDNE_Pos (13U)
+#define USB_OTG_GINTSTS_ENUMDNE_Msk (0x1U << USB_OTG_GINTSTS_ENUMDNE_Pos) /*!< 0x00002000 */
+#define USB_OTG_GINTSTS_ENUMDNE USB_OTG_GINTSTS_ENUMDNE_Msk /*!< Enumeration done */
+#define USB_OTG_GINTSTS_ISOODRP_Pos (14U)
+#define USB_OTG_GINTSTS_ISOODRP_Msk (0x1U << USB_OTG_GINTSTS_ISOODRP_Pos) /*!< 0x00004000 */
+#define USB_OTG_GINTSTS_ISOODRP USB_OTG_GINTSTS_ISOODRP_Msk /*!< Isochronous OUT packet dropped interrupt */
+#define USB_OTG_GINTSTS_EOPF_Pos (15U)
+#define USB_OTG_GINTSTS_EOPF_Msk (0x1U << USB_OTG_GINTSTS_EOPF_Pos) /*!< 0x00008000 */
+#define USB_OTG_GINTSTS_EOPF USB_OTG_GINTSTS_EOPF_Msk /*!< End of periodic frame interrupt */
+#define USB_OTG_GINTSTS_IEPINT_Pos (18U)
+#define USB_OTG_GINTSTS_IEPINT_Msk (0x1U << USB_OTG_GINTSTS_IEPINT_Pos) /*!< 0x00040000 */
+#define USB_OTG_GINTSTS_IEPINT USB_OTG_GINTSTS_IEPINT_Msk /*!< IN endpoint interrupt */
+#define USB_OTG_GINTSTS_OEPINT_Pos (19U)
+#define USB_OTG_GINTSTS_OEPINT_Msk (0x1U << USB_OTG_GINTSTS_OEPINT_Pos) /*!< 0x00080000 */
+#define USB_OTG_GINTSTS_OEPINT USB_OTG_GINTSTS_OEPINT_Msk /*!< OUT endpoint interrupt */
+#define USB_OTG_GINTSTS_IISOIXFR_Pos (20U)
+#define USB_OTG_GINTSTS_IISOIXFR_Msk (0x1U << USB_OTG_GINTSTS_IISOIXFR_Pos) /*!< 0x00100000 */
+#define USB_OTG_GINTSTS_IISOIXFR USB_OTG_GINTSTS_IISOIXFR_Msk /*!< Incomplete isochronous IN transfer */
+#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos (21U)
+#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk (0x1U << USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos) /*!< 0x00200000 */
+#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk /*!< Incomplete periodic transfer */
+#define USB_OTG_GINTSTS_DATAFSUSP_Pos (22U)
+#define USB_OTG_GINTSTS_DATAFSUSP_Msk (0x1U << USB_OTG_GINTSTS_DATAFSUSP_Pos) /*!< 0x00400000 */
+#define USB_OTG_GINTSTS_DATAFSUSP USB_OTG_GINTSTS_DATAFSUSP_Msk /*!< Data fetch suspended */
+#define USB_OTG_GINTSTS_HPRTINT_Pos (24U)
+#define USB_OTG_GINTSTS_HPRTINT_Msk (0x1U << USB_OTG_GINTSTS_HPRTINT_Pos) /*!< 0x01000000 */
+#define USB_OTG_GINTSTS_HPRTINT USB_OTG_GINTSTS_HPRTINT_Msk /*!< Host port interrupt */
+#define USB_OTG_GINTSTS_HCINT_Pos (25U)
+#define USB_OTG_GINTSTS_HCINT_Msk (0x1U << USB_OTG_GINTSTS_HCINT_Pos) /*!< 0x02000000 */
+#define USB_OTG_GINTSTS_HCINT USB_OTG_GINTSTS_HCINT_Msk /*!< Host channels interrupt */
+#define USB_OTG_GINTSTS_PTXFE_Pos (26U)
+#define USB_OTG_GINTSTS_PTXFE_Msk (0x1U << USB_OTG_GINTSTS_PTXFE_Pos) /*!< 0x04000000 */
+#define USB_OTG_GINTSTS_PTXFE USB_OTG_GINTSTS_PTXFE_Msk /*!< Periodic TxFIFO empty */
+#define USB_OTG_GINTSTS_CIDSCHG_Pos (28U)
+#define USB_OTG_GINTSTS_CIDSCHG_Msk (0x1U << USB_OTG_GINTSTS_CIDSCHG_Pos) /*!< 0x10000000 */
+#define USB_OTG_GINTSTS_CIDSCHG USB_OTG_GINTSTS_CIDSCHG_Msk /*!< Connector ID status change */
+#define USB_OTG_GINTSTS_DISCINT_Pos (29U)
+#define USB_OTG_GINTSTS_DISCINT_Msk (0x1U << USB_OTG_GINTSTS_DISCINT_Pos) /*!< 0x20000000 */
+#define USB_OTG_GINTSTS_DISCINT USB_OTG_GINTSTS_DISCINT_Msk /*!< Disconnect detected interrupt */
+#define USB_OTG_GINTSTS_SRQINT_Pos (30U)
+#define USB_OTG_GINTSTS_SRQINT_Msk (0x1U << USB_OTG_GINTSTS_SRQINT_Pos) /*!< 0x40000000 */
+#define USB_OTG_GINTSTS_SRQINT USB_OTG_GINTSTS_SRQINT_Msk /*!< Session request/new session detected interrupt */
+#define USB_OTG_GINTSTS_WKUINT_Pos (31U)
+#define USB_OTG_GINTSTS_WKUINT_Msk (0x1U << USB_OTG_GINTSTS_WKUINT_Pos) /*!< 0x80000000 */
+#define USB_OTG_GINTSTS_WKUINT USB_OTG_GINTSTS_WKUINT_Msk /*!< Resume/remote wakeup detected interrupt */
+
+/******************** Bit definition forUSB_OTG_GINTMSK register *****************/
+#define USB_OTG_GINTMSK_MMISM_Pos (1U)
+#define USB_OTG_GINTMSK_MMISM_Msk (0x1U << USB_OTG_GINTMSK_MMISM_Pos) /*!< 0x00000002 */
+#define USB_OTG_GINTMSK_MMISM USB_OTG_GINTMSK_MMISM_Msk /*!< Mode mismatch interrupt mask */
+#define USB_OTG_GINTMSK_OTGINT_Pos (2U)
+#define USB_OTG_GINTMSK_OTGINT_Msk (0x1U << USB_OTG_GINTMSK_OTGINT_Pos) /*!< 0x00000004 */
+#define USB_OTG_GINTMSK_OTGINT USB_OTG_GINTMSK_OTGINT_Msk /*!< OTG interrupt mask */
+#define USB_OTG_GINTMSK_SOFM_Pos (3U)
+#define USB_OTG_GINTMSK_SOFM_Msk (0x1U << USB_OTG_GINTMSK_SOFM_Pos) /*!< 0x00000008 */
+#define USB_OTG_GINTMSK_SOFM USB_OTG_GINTMSK_SOFM_Msk /*!< Start of frame mask */
+#define USB_OTG_GINTMSK_RXFLVLM_Pos (4U)
+#define USB_OTG_GINTMSK_RXFLVLM_Msk (0x1U << USB_OTG_GINTMSK_RXFLVLM_Pos) /*!< 0x00000010 */
+#define USB_OTG_GINTMSK_RXFLVLM USB_OTG_GINTMSK_RXFLVLM_Msk /*!< Receive FIFO nonempty mask */
+#define USB_OTG_GINTMSK_NPTXFEM_Pos (5U)
+#define USB_OTG_GINTMSK_NPTXFEM_Msk (0x1U << USB_OTG_GINTMSK_NPTXFEM_Pos) /*!< 0x00000020 */
+#define USB_OTG_GINTMSK_NPTXFEM USB_OTG_GINTMSK_NPTXFEM_Msk /*!< Nonperiodic TxFIFO empty mask */
+#define USB_OTG_GINTMSK_GINAKEFFM_Pos (6U)
+#define USB_OTG_GINTMSK_GINAKEFFM_Msk (0x1U << USB_OTG_GINTMSK_GINAKEFFM_Pos) /*!< 0x00000040 */
+#define USB_OTG_GINTMSK_GINAKEFFM USB_OTG_GINTMSK_GINAKEFFM_Msk /*!< Global nonperiodic IN NAK effective mask */
+#define USB_OTG_GINTMSK_GONAKEFFM_Pos (7U)
+#define USB_OTG_GINTMSK_GONAKEFFM_Msk (0x1U << USB_OTG_GINTMSK_GONAKEFFM_Pos) /*!< 0x00000080 */
+#define USB_OTG_GINTMSK_GONAKEFFM USB_OTG_GINTMSK_GONAKEFFM_Msk /*!< Global OUT NAK effective mask */
+#define USB_OTG_GINTMSK_ESUSPM_Pos (10U)
+#define USB_OTG_GINTMSK_ESUSPM_Msk (0x1U << USB_OTG_GINTMSK_ESUSPM_Pos) /*!< 0x00000400 */
+#define USB_OTG_GINTMSK_ESUSPM USB_OTG_GINTMSK_ESUSPM_Msk /*!< Early suspend mask */
+#define USB_OTG_GINTMSK_USBSUSPM_Pos (11U)
+#define USB_OTG_GINTMSK_USBSUSPM_Msk (0x1U << USB_OTG_GINTMSK_USBSUSPM_Pos) /*!< 0x00000800 */
+#define USB_OTG_GINTMSK_USBSUSPM USB_OTG_GINTMSK_USBSUSPM_Msk /*!< USB suspend mask */
+#define USB_OTG_GINTMSK_USBRST_Pos (12U)
+#define USB_OTG_GINTMSK_USBRST_Msk (0x1U << USB_OTG_GINTMSK_USBRST_Pos) /*!< 0x00001000 */
+#define USB_OTG_GINTMSK_USBRST USB_OTG_GINTMSK_USBRST_Msk /*!< USB reset mask */
+#define USB_OTG_GINTMSK_ENUMDNEM_Pos (13U)
+#define USB_OTG_GINTMSK_ENUMDNEM_Msk (0x1U << USB_OTG_GINTMSK_ENUMDNEM_Pos) /*!< 0x00002000 */
+#define USB_OTG_GINTMSK_ENUMDNEM USB_OTG_GINTMSK_ENUMDNEM_Msk /*!< Enumeration done mask */
+#define USB_OTG_GINTMSK_ISOODRPM_Pos (14U)
+#define USB_OTG_GINTMSK_ISOODRPM_Msk (0x1U << USB_OTG_GINTMSK_ISOODRPM_Pos) /*!< 0x00004000 */
+#define USB_OTG_GINTMSK_ISOODRPM USB_OTG_GINTMSK_ISOODRPM_Msk /*!< Isochronous OUT packet dropped interrupt mask */
+#define USB_OTG_GINTMSK_EOPFM_Pos (15U)
+#define USB_OTG_GINTMSK_EOPFM_Msk (0x1U << USB_OTG_GINTMSK_EOPFM_Pos) /*!< 0x00008000 */
+#define USB_OTG_GINTMSK_EOPFM USB_OTG_GINTMSK_EOPFM_Msk /*!< End of periodic frame interrupt mask */
+#define USB_OTG_GINTMSK_EPMISM_Pos (17U)
+#define USB_OTG_GINTMSK_EPMISM_Msk (0x1U << USB_OTG_GINTMSK_EPMISM_Pos) /*!< 0x00020000 */
+#define USB_OTG_GINTMSK_EPMISM USB_OTG_GINTMSK_EPMISM_Msk /*!< Endpoint mismatch interrupt mask */
+#define USB_OTG_GINTMSK_IEPINT_Pos (18U)
+#define USB_OTG_GINTMSK_IEPINT_Msk (0x1U << USB_OTG_GINTMSK_IEPINT_Pos) /*!< 0x00040000 */
+#define USB_OTG_GINTMSK_IEPINT USB_OTG_GINTMSK_IEPINT_Msk /*!< IN endpoints interrupt mask */
+#define USB_OTG_GINTMSK_OEPINT_Pos (19U)
+#define USB_OTG_GINTMSK_OEPINT_Msk (0x1U << USB_OTG_GINTMSK_OEPINT_Pos) /*!< 0x00080000 */
+#define USB_OTG_GINTMSK_OEPINT USB_OTG_GINTMSK_OEPINT_Msk /*!< OUT endpoints interrupt mask */
+#define USB_OTG_GINTMSK_IISOIXFRM_Pos (20U)
+#define USB_OTG_GINTMSK_IISOIXFRM_Msk (0x1U << USB_OTG_GINTMSK_IISOIXFRM_Pos) /*!< 0x00100000 */
+#define USB_OTG_GINTMSK_IISOIXFRM USB_OTG_GINTMSK_IISOIXFRM_Msk /*!< Incomplete isochronous IN transfer mask */
+#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos (21U)
+#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk (0x1U << USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos) /*!< 0x00200000 */
+#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk /*!< Incomplete periodic transfer mask */
+#define USB_OTG_GINTMSK_FSUSPM_Pos (22U)
+#define USB_OTG_GINTMSK_FSUSPM_Msk (0x1U << USB_OTG_GINTMSK_FSUSPM_Pos) /*!< 0x00400000 */
+#define USB_OTG_GINTMSK_FSUSPM USB_OTG_GINTMSK_FSUSPM_Msk /*!< Data fetch suspended mask */
+#define USB_OTG_GINTMSK_PRTIM_Pos (24U)
+#define USB_OTG_GINTMSK_PRTIM_Msk (0x1U << USB_OTG_GINTMSK_PRTIM_Pos) /*!< 0x01000000 */
+#define USB_OTG_GINTMSK_PRTIM USB_OTG_GINTMSK_PRTIM_Msk /*!< Host port interrupt mask */
+#define USB_OTG_GINTMSK_HCIM_Pos (25U)
+#define USB_OTG_GINTMSK_HCIM_Msk (0x1U << USB_OTG_GINTMSK_HCIM_Pos) /*!< 0x02000000 */
+#define USB_OTG_GINTMSK_HCIM USB_OTG_GINTMSK_HCIM_Msk /*!< Host channels interrupt mask */
+#define USB_OTG_GINTMSK_PTXFEM_Pos (26U)
+#define USB_OTG_GINTMSK_PTXFEM_Msk (0x1U << USB_OTG_GINTMSK_PTXFEM_Pos) /*!< 0x04000000 */
+#define USB_OTG_GINTMSK_PTXFEM USB_OTG_GINTMSK_PTXFEM_Msk /*!< Periodic TxFIFO empty mask */
+#define USB_OTG_GINTMSK_CIDSCHGM_Pos (28U)
+#define USB_OTG_GINTMSK_CIDSCHGM_Msk (0x1U << USB_OTG_GINTMSK_CIDSCHGM_Pos) /*!< 0x10000000 */
+#define USB_OTG_GINTMSK_CIDSCHGM USB_OTG_GINTMSK_CIDSCHGM_Msk /*!< Connector ID status change mask */
+#define USB_OTG_GINTMSK_DISCINT_Pos (29U)
+#define USB_OTG_GINTMSK_DISCINT_Msk (0x1U << USB_OTG_GINTMSK_DISCINT_Pos) /*!< 0x20000000 */
+#define USB_OTG_GINTMSK_DISCINT USB_OTG_GINTMSK_DISCINT_Msk /*!< Disconnect detected interrupt mask */
+#define USB_OTG_GINTMSK_SRQIM_Pos (30U)
+#define USB_OTG_GINTMSK_SRQIM_Msk (0x1U << USB_OTG_GINTMSK_SRQIM_Pos) /*!< 0x40000000 */
+#define USB_OTG_GINTMSK_SRQIM USB_OTG_GINTMSK_SRQIM_Msk /*!< Session request/new session detected interrupt mask */
+#define USB_OTG_GINTMSK_WUIM_Pos (31U)
+#define USB_OTG_GINTMSK_WUIM_Msk (0x1U << USB_OTG_GINTMSK_WUIM_Pos) /*!< 0x80000000 */
+#define USB_OTG_GINTMSK_WUIM USB_OTG_GINTMSK_WUIM_Msk /*!< Resume/remote wakeup detected interrupt mask */
+
+/******************** Bit definition forUSB_OTG_DAINT register *******************/
+#define USB_OTG_DAINT_IEPINT_Pos (0U)
+#define USB_OTG_DAINT_IEPINT_Msk (0xFFFFU << USB_OTG_DAINT_IEPINT_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_DAINT_IEPINT USB_OTG_DAINT_IEPINT_Msk /*!< IN endpoint interrupt bits */
+#define USB_OTG_DAINT_OEPINT_Pos (16U)
+#define USB_OTG_DAINT_OEPINT_Msk (0xFFFFU << USB_OTG_DAINT_OEPINT_Pos) /*!< 0xFFFF0000 */
+#define USB_OTG_DAINT_OEPINT USB_OTG_DAINT_OEPINT_Msk /*!< OUT endpoint interrupt bits */
+
+/******************** Bit definition forUSB_OTG_HAINTMSK register ****************/
+#define USB_OTG_HAINTMSK_HAINTM_Pos (0U)
+#define USB_OTG_HAINTMSK_HAINTM_Msk (0xFFFFU << USB_OTG_HAINTMSK_HAINTM_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_HAINTMSK_HAINTM USB_OTG_HAINTMSK_HAINTM_Msk /*!< Channel interrupt mask */
+
+/******************** Bit definition for USB_OTG_GRXSTSP register ****************/
+#define USB_OTG_GRXSTSP_EPNUM_Pos (0U)
+#define USB_OTG_GRXSTSP_EPNUM_Msk (0xFU << USB_OTG_GRXSTSP_EPNUM_Pos) /*!< 0x0000000F */
+#define USB_OTG_GRXSTSP_EPNUM USB_OTG_GRXSTSP_EPNUM_Msk /*!< IN EP interrupt mask bits */
+#define USB_OTG_GRXSTSP_BCNT_Pos (4U)
+#define USB_OTG_GRXSTSP_BCNT_Msk (0x7FFU << USB_OTG_GRXSTSP_BCNT_Pos) /*!< 0x00007FF0 */
+#define USB_OTG_GRXSTSP_BCNT USB_OTG_GRXSTSP_BCNT_Msk /*!< OUT EP interrupt mask bits */
+#define USB_OTG_GRXSTSP_DPID_Pos (15U)
+#define USB_OTG_GRXSTSP_DPID_Msk (0x3U << USB_OTG_GRXSTSP_DPID_Pos) /*!< 0x00018000 */
+#define USB_OTG_GRXSTSP_DPID USB_OTG_GRXSTSP_DPID_Msk /*!< OUT EP interrupt mask bits */
+#define USB_OTG_GRXSTSP_PKTSTS_Pos (17U)
+#define USB_OTG_GRXSTSP_PKTSTS_Msk (0xFU << USB_OTG_GRXSTSP_PKTSTS_Pos) /*!< 0x001E0000 */
+#define USB_OTG_GRXSTSP_PKTSTS USB_OTG_GRXSTSP_PKTSTS_Msk /*!< OUT EP interrupt mask bits */
+
+/******************** Bit definition forUSB_OTG_DAINTMSK register ****************/
+#define USB_OTG_DAINTMSK_IEPM_Pos (0U)
+#define USB_OTG_DAINTMSK_IEPM_Msk (0xFFFFU << USB_OTG_DAINTMSK_IEPM_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_DAINTMSK_IEPM USB_OTG_DAINTMSK_IEPM_Msk /*!< IN EP interrupt mask bits */
+#define USB_OTG_DAINTMSK_OEPM_Pos (16U)
+#define USB_OTG_DAINTMSK_OEPM_Msk (0xFFFFU << USB_OTG_DAINTMSK_OEPM_Pos) /*!< 0xFFFF0000 */
+#define USB_OTG_DAINTMSK_OEPM USB_OTG_DAINTMSK_OEPM_Msk /*!< OUT EP interrupt mask bits */
+
+/******************** Bit definition for OTG register ****************************/
+#define USB_OTG_CHNUM_Pos (0U)
+#define USB_OTG_CHNUM_Msk (0xFU << USB_OTG_CHNUM_Pos) /*!< 0x0000000F */
+#define USB_OTG_CHNUM USB_OTG_CHNUM_Msk /*!< Channel number */
+#define USB_OTG_CHNUM_0 (0x1U << USB_OTG_CHNUM_Pos) /*!< 0x00000001 */
+#define USB_OTG_CHNUM_1 (0x2U << USB_OTG_CHNUM_Pos) /*!< 0x00000002 */
+#define USB_OTG_CHNUM_2 (0x4U << USB_OTG_CHNUM_Pos) /*!< 0x00000004 */
+#define USB_OTG_CHNUM_3 (0x8U << USB_OTG_CHNUM_Pos) /*!< 0x00000008 */
+#define USB_OTG_BCNT_Pos (4U)
+#define USB_OTG_BCNT_Msk (0x7FFU << USB_OTG_BCNT_Pos) /*!< 0x00007FF0 */
+#define USB_OTG_BCNT USB_OTG_BCNT_Msk /*!< Byte count */
+
+#define USB_OTG_DPID_Pos (15U)
+#define USB_OTG_DPID_Msk (0x3U << USB_OTG_DPID_Pos) /*!< 0x00018000 */
+#define USB_OTG_DPID USB_OTG_DPID_Msk /*!< Data PID */
+#define USB_OTG_DPID_0 (0x1U << USB_OTG_DPID_Pos) /*!< 0x00008000 */
+#define USB_OTG_DPID_1 (0x2U << USB_OTG_DPID_Pos) /*!< 0x00010000 */
+
+#define USB_OTG_PKTSTS_Pos (17U)
+#define USB_OTG_PKTSTS_Msk (0xFU << USB_OTG_PKTSTS_Pos) /*!< 0x001E0000 */
+#define USB_OTG_PKTSTS USB_OTG_PKTSTS_Msk /*!< Packet status */
+#define USB_OTG_PKTSTS_0 (0x1U << USB_OTG_PKTSTS_Pos) /*!< 0x00020000 */
+#define USB_OTG_PKTSTS_1 (0x2U << USB_OTG_PKTSTS_Pos) /*!< 0x00040000 */
+#define USB_OTG_PKTSTS_2 (0x4U << USB_OTG_PKTSTS_Pos) /*!< 0x00080000 */
+#define USB_OTG_PKTSTS_3 (0x8U << USB_OTG_PKTSTS_Pos) /*!< 0x00100000 */
+
+#define USB_OTG_EPNUM_Pos (0U)
+#define USB_OTG_EPNUM_Msk (0xFU << USB_OTG_EPNUM_Pos) /*!< 0x0000000F */
+#define USB_OTG_EPNUM USB_OTG_EPNUM_Msk /*!< Endpoint number */
+#define USB_OTG_EPNUM_0 (0x1U << USB_OTG_EPNUM_Pos) /*!< 0x00000001 */
+#define USB_OTG_EPNUM_1 (0x2U << USB_OTG_EPNUM_Pos) /*!< 0x00000002 */
+#define USB_OTG_EPNUM_2 (0x4U << USB_OTG_EPNUM_Pos) /*!< 0x00000004 */
+#define USB_OTG_EPNUM_3 (0x8U << USB_OTG_EPNUM_Pos) /*!< 0x00000008 */
+
+#define USB_OTG_FRMNUM_Pos (21U)
+#define USB_OTG_FRMNUM_Msk (0xFU << USB_OTG_FRMNUM_Pos) /*!< 0x01E00000 */
+#define USB_OTG_FRMNUM USB_OTG_FRMNUM_Msk /*!< Frame number */
+#define USB_OTG_FRMNUM_0 (0x1U << USB_OTG_FRMNUM_Pos) /*!< 0x00200000 */
+#define USB_OTG_FRMNUM_1 (0x2U << USB_OTG_FRMNUM_Pos) /*!< 0x00400000 */
+#define USB_OTG_FRMNUM_2 (0x4U << USB_OTG_FRMNUM_Pos) /*!< 0x00800000 */
+#define USB_OTG_FRMNUM_3 (0x8U << USB_OTG_FRMNUM_Pos) /*!< 0x01000000 */
+
+/******************** Bit definition for OTG register ****************************/
+#define USB_OTG_CHNUM_Pos (0U)
+#define USB_OTG_CHNUM_Msk (0xFU << USB_OTG_CHNUM_Pos) /*!< 0x0000000F */
+#define USB_OTG_CHNUM USB_OTG_CHNUM_Msk /*!< Channel number */
+#define USB_OTG_CHNUM_0 (0x1U << USB_OTG_CHNUM_Pos) /*!< 0x00000001 */
+#define USB_OTG_CHNUM_1 (0x2U << USB_OTG_CHNUM_Pos) /*!< 0x00000002 */
+#define USB_OTG_CHNUM_2 (0x4U << USB_OTG_CHNUM_Pos) /*!< 0x00000004 */
+#define USB_OTG_CHNUM_3 (0x8U << USB_OTG_CHNUM_Pos) /*!< 0x00000008 */
+#define USB_OTG_BCNT_Pos (4U)
+#define USB_OTG_BCNT_Msk (0x7FFU << USB_OTG_BCNT_Pos) /*!< 0x00007FF0 */
+#define USB_OTG_BCNT USB_OTG_BCNT_Msk /*!< Byte count */
+
+#define USB_OTG_DPID_Pos (15U)
+#define USB_OTG_DPID_Msk (0x3U << USB_OTG_DPID_Pos) /*!< 0x00018000 */
+#define USB_OTG_DPID USB_OTG_DPID_Msk /*!< Data PID */
+#define USB_OTG_DPID_0 (0x1U << USB_OTG_DPID_Pos) /*!< 0x00008000 */
+#define USB_OTG_DPID_1 (0x2U << USB_OTG_DPID_Pos) /*!< 0x00010000 */
+
+#define USB_OTG_PKTSTS_Pos (17U)
+#define USB_OTG_PKTSTS_Msk (0xFU << USB_OTG_PKTSTS_Pos) /*!< 0x001E0000 */
+#define USB_OTG_PKTSTS USB_OTG_PKTSTS_Msk /*!< Packet status */
+#define USB_OTG_PKTSTS_0 (0x1U << USB_OTG_PKTSTS_Pos) /*!< 0x00020000 */
+#define USB_OTG_PKTSTS_1 (0x2U << USB_OTG_PKTSTS_Pos) /*!< 0x00040000 */
+#define USB_OTG_PKTSTS_2 (0x4U << USB_OTG_PKTSTS_Pos) /*!< 0x00080000 */
+#define USB_OTG_PKTSTS_3 (0x8U << USB_OTG_PKTSTS_Pos) /*!< 0x00100000 */
+
+#define USB_OTG_EPNUM_Pos (0U)
+#define USB_OTG_EPNUM_Msk (0xFU << USB_OTG_EPNUM_Pos) /*!< 0x0000000F */
+#define USB_OTG_EPNUM USB_OTG_EPNUM_Msk /*!< Endpoint number */
+#define USB_OTG_EPNUM_0 (0x1U << USB_OTG_EPNUM_Pos) /*!< 0x00000001 */
+#define USB_OTG_EPNUM_1 (0x2U << USB_OTG_EPNUM_Pos) /*!< 0x00000002 */
+#define USB_OTG_EPNUM_2 (0x4U << USB_OTG_EPNUM_Pos) /*!< 0x00000004 */
+#define USB_OTG_EPNUM_3 (0x8U << USB_OTG_EPNUM_Pos) /*!< 0x00000008 */
+
+#define USB_OTG_FRMNUM_Pos (21U)
+#define USB_OTG_FRMNUM_Msk (0xFU << USB_OTG_FRMNUM_Pos) /*!< 0x01E00000 */
+#define USB_OTG_FRMNUM USB_OTG_FRMNUM_Msk /*!< Frame number */
+#define USB_OTG_FRMNUM_0 (0x1U << USB_OTG_FRMNUM_Pos) /*!< 0x00200000 */
+#define USB_OTG_FRMNUM_1 (0x2U << USB_OTG_FRMNUM_Pos) /*!< 0x00400000 */
+#define USB_OTG_FRMNUM_2 (0x4U << USB_OTG_FRMNUM_Pos) /*!< 0x00800000 */
+#define USB_OTG_FRMNUM_3 (0x8U << USB_OTG_FRMNUM_Pos) /*!< 0x01000000 */
+
+/******************** Bit definition forUSB_OTG_GRXFSIZ register *****************/
+#define USB_OTG_GRXFSIZ_RXFD_Pos (0U)
+#define USB_OTG_GRXFSIZ_RXFD_Msk (0xFFFFU << USB_OTG_GRXFSIZ_RXFD_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_GRXFSIZ_RXFD USB_OTG_GRXFSIZ_RXFD_Msk /*!< RxFIFO depth */
+
+/******************** Bit definition forUSB_OTG_DVBUSDIS register ****************/
+#define USB_OTG_DVBUSDIS_VBUSDT_Pos (0U)
+#define USB_OTG_DVBUSDIS_VBUSDT_Msk (0xFFFFU << USB_OTG_DVBUSDIS_VBUSDT_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_DVBUSDIS_VBUSDT USB_OTG_DVBUSDIS_VBUSDT_Msk /*!< Device VBUS discharge time */
+
+/******************** Bit definition for OTG register ****************************/
+#define USB_OTG_NPTXFSA_Pos (0U)
+#define USB_OTG_NPTXFSA_Msk (0xFFFFU << USB_OTG_NPTXFSA_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_NPTXFSA USB_OTG_NPTXFSA_Msk /*!< Nonperiodic transmit RAM start address */
+#define USB_OTG_NPTXFD_Pos (16U)
+#define USB_OTG_NPTXFD_Msk (0xFFFFU << USB_OTG_NPTXFD_Pos) /*!< 0xFFFF0000 */
+#define USB_OTG_NPTXFD USB_OTG_NPTXFD_Msk /*!< Nonperiodic TxFIFO depth */
+#define USB_OTG_TX0FSA_Pos (0U)
+#define USB_OTG_TX0FSA_Msk (0xFFFFU << USB_OTG_TX0FSA_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_TX0FSA USB_OTG_TX0FSA_Msk /*!< Endpoint 0 transmit RAM start address */
+#define USB_OTG_TX0FD_Pos (16U)
+#define USB_OTG_TX0FD_Msk (0xFFFFU << USB_OTG_TX0FD_Pos) /*!< 0xFFFF0000 */
+#define USB_OTG_TX0FD USB_OTG_TX0FD_Msk /*!< Endpoint 0 TxFIFO depth */
+
+/******************** Bit definition forUSB_OTG_DVBUSPULSE register **************/
+#define USB_OTG_DVBUSPULSE_DVBUSP_Pos (0U)
+#define USB_OTG_DVBUSPULSE_DVBUSP_Msk (0xFFFU << USB_OTG_DVBUSPULSE_DVBUSP_Pos) /*!< 0x00000FFF */
+#define USB_OTG_DVBUSPULSE_DVBUSP USB_OTG_DVBUSPULSE_DVBUSP_Msk /*!< Device VBUS pulsing time */
+
+/******************** Bit definition forUSB_OTG_GNPTXSTS register ****************/
+#define USB_OTG_GNPTXSTS_NPTXFSAV_Pos (0U)
+#define USB_OTG_GNPTXSTS_NPTXFSAV_Msk (0xFFFFU << USB_OTG_GNPTXSTS_NPTXFSAV_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_GNPTXSTS_NPTXFSAV USB_OTG_GNPTXSTS_NPTXFSAV_Msk /*!< Nonperiodic TxFIFO space available */
+
+#define USB_OTG_GNPTXSTS_NPTQXSAV_Pos (16U)
+#define USB_OTG_GNPTXSTS_NPTQXSAV_Msk (0xFFU << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00FF0000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV USB_OTG_GNPTXSTS_NPTQXSAV_Msk /*!< Nonperiodic transmit request queue space available */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_0 (0x01U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00010000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_1 (0x02U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00020000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_2 (0x04U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00040000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_3 (0x08U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00080000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_4 (0x10U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00100000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_5 (0x20U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00200000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_6 (0x40U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00400000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_7 (0x80U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00800000 */
+
+#define USB_OTG_GNPTXSTS_NPTXQTOP_Pos (24U)
+#define USB_OTG_GNPTXSTS_NPTXQTOP_Msk (0x7FU << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x7F000000 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP USB_OTG_GNPTXSTS_NPTXQTOP_Msk /*!< Top of the nonperiodic transmit request queue */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_0 (0x01U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x01000000 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_1 (0x02U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x02000000 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_2 (0x04U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x04000000 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_3 (0x08U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x08000000 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_4 (0x10U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x10000000 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_5 (0x20U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x20000000 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_6 (0x40U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x40000000 */
+
+/******************** Bit definition forUSB_OTG_DTHRCTL register *****************/
+#define USB_OTG_DTHRCTL_NONISOTHREN_Pos (0U)
+#define USB_OTG_DTHRCTL_NONISOTHREN_Msk (0x1U << USB_OTG_DTHRCTL_NONISOTHREN_Pos) /*!< 0x00000001 */
+#define USB_OTG_DTHRCTL_NONISOTHREN USB_OTG_DTHRCTL_NONISOTHREN_Msk /*!< Nonisochronous IN endpoints threshold enable */
+#define USB_OTG_DTHRCTL_ISOTHREN_Pos (1U)
+#define USB_OTG_DTHRCTL_ISOTHREN_Msk (0x1U << USB_OTG_DTHRCTL_ISOTHREN_Pos) /*!< 0x00000002 */
+#define USB_OTG_DTHRCTL_ISOTHREN USB_OTG_DTHRCTL_ISOTHREN_Msk /*!< ISO IN endpoint threshold enable */
+
+#define USB_OTG_DTHRCTL_TXTHRLEN_Pos (2U)
+#define USB_OTG_DTHRCTL_TXTHRLEN_Msk (0x1FFU << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x000007FC */
+#define USB_OTG_DTHRCTL_TXTHRLEN USB_OTG_DTHRCTL_TXTHRLEN_Msk /*!< Transmit threshold length */
+#define USB_OTG_DTHRCTL_TXTHRLEN_0 (0x001U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000004 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_1 (0x002U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000008 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_2 (0x004U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000010 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_3 (0x008U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000020 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_4 (0x010U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000040 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_5 (0x020U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000080 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_6 (0x040U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000100 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_7 (0x080U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000200 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_8 (0x100U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000400 */
+#define USB_OTG_DTHRCTL_RXTHREN_Pos (16U)
+#define USB_OTG_DTHRCTL_RXTHREN_Msk (0x1U << USB_OTG_DTHRCTL_RXTHREN_Pos) /*!< 0x00010000 */
+#define USB_OTG_DTHRCTL_RXTHREN USB_OTG_DTHRCTL_RXTHREN_Msk /*!< Receive threshold enable */
+
+#define USB_OTG_DTHRCTL_RXTHRLEN_Pos (17U)
+#define USB_OTG_DTHRCTL_RXTHRLEN_Msk (0x1FFU << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x03FE0000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN USB_OTG_DTHRCTL_RXTHRLEN_Msk /*!< Receive threshold length */
+#define USB_OTG_DTHRCTL_RXTHRLEN_0 (0x001U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00020000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_1 (0x002U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00040000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_2 (0x004U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00080000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_3 (0x008U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00100000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_4 (0x010U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00200000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_5 (0x020U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00400000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_6 (0x040U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00800000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_7 (0x080U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x01000000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_8 (0x100U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x02000000 */
+#define USB_OTG_DTHRCTL_ARPEN_Pos (27U)
+#define USB_OTG_DTHRCTL_ARPEN_Msk (0x1U << USB_OTG_DTHRCTL_ARPEN_Pos) /*!< 0x08000000 */
+#define USB_OTG_DTHRCTL_ARPEN USB_OTG_DTHRCTL_ARPEN_Msk /*!< Arbiter parking enable */
+
+/******************** Bit definition forUSB_OTG_DIEPEMPMSK register **************/
+#define USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos (0U)
+#define USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk (0xFFFFU << USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_DIEPEMPMSK_INEPTXFEM USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk /*!< IN EP Tx FIFO empty interrupt mask bits */
+
+/******************** Bit definition forUSB_OTG_DEACHINT register ****************/
+#define USB_OTG_DEACHINT_IEP1INT_Pos (1U)
+#define USB_OTG_DEACHINT_IEP1INT_Msk (0x1U << USB_OTG_DEACHINT_IEP1INT_Pos) /*!< 0x00000002 */
+#define USB_OTG_DEACHINT_IEP1INT USB_OTG_DEACHINT_IEP1INT_Msk /*!< IN endpoint 1interrupt bit */
+#define USB_OTG_DEACHINT_OEP1INT_Pos (17U)
+#define USB_OTG_DEACHINT_OEP1INT_Msk (0x1U << USB_OTG_DEACHINT_OEP1INT_Pos) /*!< 0x00020000 */
+#define USB_OTG_DEACHINT_OEP1INT USB_OTG_DEACHINT_OEP1INT_Msk /*!< OUT endpoint 1 interrupt bit */
+
+/******************** Bit definition forUSB_OTG_GCCFG register *******************/
+#define USB_OTG_GCCFG_PWRDWN_Pos (16U)
+#define USB_OTG_GCCFG_PWRDWN_Msk (0x1U << USB_OTG_GCCFG_PWRDWN_Pos) /*!< 0x00010000 */
+#define USB_OTG_GCCFG_PWRDWN USB_OTG_GCCFG_PWRDWN_Msk /*!< Power down */
+#define USB_OTG_GCCFG_VBUSASEN_Pos (18U)
+#define USB_OTG_GCCFG_VBUSASEN_Msk (0x1U << USB_OTG_GCCFG_VBUSASEN_Pos) /*!< 0x00040000 */
+#define USB_OTG_GCCFG_VBUSASEN USB_OTG_GCCFG_VBUSASEN_Msk /*!< Enable the VBUS sensing device */
+#define USB_OTG_GCCFG_VBUSBSEN_Pos (19U)
+#define USB_OTG_GCCFG_VBUSBSEN_Msk (0x1U << USB_OTG_GCCFG_VBUSBSEN_Pos) /*!< 0x00080000 */
+#define USB_OTG_GCCFG_VBUSBSEN USB_OTG_GCCFG_VBUSBSEN_Msk /*!< Enable the VBUS sensing device */
+#define USB_OTG_GCCFG_SOFOUTEN_Pos (20U)
+#define USB_OTG_GCCFG_SOFOUTEN_Msk (0x1U << USB_OTG_GCCFG_SOFOUTEN_Pos) /*!< 0x00100000 */
+#define USB_OTG_GCCFG_SOFOUTEN USB_OTG_GCCFG_SOFOUTEN_Msk /*!< SOF output enable */
+
+/******************** Bit definition forUSB_OTG_DEACHINTMSK register *************/
+#define USB_OTG_DEACHINTMSK_IEP1INTM_Pos (1U)
+#define USB_OTG_DEACHINTMSK_IEP1INTM_Msk (0x1U << USB_OTG_DEACHINTMSK_IEP1INTM_Pos) /*!< 0x00000002 */
+#define USB_OTG_DEACHINTMSK_IEP1INTM USB_OTG_DEACHINTMSK_IEP1INTM_Msk /*!< IN Endpoint 1 interrupt mask bit */
+#define USB_OTG_DEACHINTMSK_OEP1INTM_Pos (17U)
+#define USB_OTG_DEACHINTMSK_OEP1INTM_Msk (0x1U << USB_OTG_DEACHINTMSK_OEP1INTM_Pos) /*!< 0x00020000 */
+#define USB_OTG_DEACHINTMSK_OEP1INTM USB_OTG_DEACHINTMSK_OEP1INTM_Msk /*!< OUT Endpoint 1 interrupt mask bit */
+
+/******************** Bit definition forUSB_OTG_CID register *********************/
+#define USB_OTG_CID_PRODUCT_ID_Pos (0U)
+#define USB_OTG_CID_PRODUCT_ID_Msk (0xFFFFFFFFU << USB_OTG_CID_PRODUCT_ID_Pos) /*!< 0xFFFFFFFF */
+#define USB_OTG_CID_PRODUCT_ID USB_OTG_CID_PRODUCT_ID_Msk /*!< Product ID field */
+
+/******************** Bit definition forUSB_OTG_DIEPEACHMSK1 register ************/
+#define USB_OTG_DIEPEACHMSK1_XFRCM_Pos (0U)
+#define USB_OTG_DIEPEACHMSK1_XFRCM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */
+#define USB_OTG_DIEPEACHMSK1_XFRCM USB_OTG_DIEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask */
+#define USB_OTG_DIEPEACHMSK1_EPDM_Pos (1U)
+#define USB_OTG_DIEPEACHMSK1_EPDM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */
+#define USB_OTG_DIEPEACHMSK1_EPDM USB_OTG_DIEPEACHMSK1_EPDM_Msk /*!< Endpoint disabled interrupt mask */
+#define USB_OTG_DIEPEACHMSK1_TOM_Pos (3U)
+#define USB_OTG_DIEPEACHMSK1_TOM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */
+#define USB_OTG_DIEPEACHMSK1_TOM USB_OTG_DIEPEACHMSK1_TOM_Msk /*!< Timeout condition mask (nonisochronous endpoints) */
+#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos (4U)
+#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk (0x1U << USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */
+#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */
+#define USB_OTG_DIEPEACHMSK1_INEPNMM_Pos (5U)
+#define USB_OTG_DIEPEACHMSK1_INEPNMM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */
+#define USB_OTG_DIEPEACHMSK1_INEPNMM USB_OTG_DIEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask */
+#define USB_OTG_DIEPEACHMSK1_INEPNEM_Pos (6U)
+#define USB_OTG_DIEPEACHMSK1_INEPNEM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */
+#define USB_OTG_DIEPEACHMSK1_INEPNEM USB_OTG_DIEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask */
+#define USB_OTG_DIEPEACHMSK1_TXFURM_Pos (8U)
+#define USB_OTG_DIEPEACHMSK1_TXFURM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */
+#define USB_OTG_DIEPEACHMSK1_TXFURM USB_OTG_DIEPEACHMSK1_TXFURM_Msk /*!< FIFO underrun mask */
+#define USB_OTG_DIEPEACHMSK1_BIM_Pos (9U)
+#define USB_OTG_DIEPEACHMSK1_BIM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */
+#define USB_OTG_DIEPEACHMSK1_BIM USB_OTG_DIEPEACHMSK1_BIM_Msk /*!< BNA interrupt mask */
+#define USB_OTG_DIEPEACHMSK1_NAKM_Pos (13U)
+#define USB_OTG_DIEPEACHMSK1_NAKM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */
+#define USB_OTG_DIEPEACHMSK1_NAKM USB_OTG_DIEPEACHMSK1_NAKM_Msk /*!< NAK interrupt mask */
+
+/******************** Bit definition forUSB_OTG_HPRT register ********************/
+#define USB_OTG_HPRT_PCSTS_Pos (0U)
+#define USB_OTG_HPRT_PCSTS_Msk (0x1U << USB_OTG_HPRT_PCSTS_Pos) /*!< 0x00000001 */
+#define USB_OTG_HPRT_PCSTS USB_OTG_HPRT_PCSTS_Msk /*!< Port connect status */
+#define USB_OTG_HPRT_PCDET_Pos (1U)
+#define USB_OTG_HPRT_PCDET_Msk (0x1U << USB_OTG_HPRT_PCDET_Pos) /*!< 0x00000002 */
+#define USB_OTG_HPRT_PCDET USB_OTG_HPRT_PCDET_Msk /*!< Port connect detected */
+#define USB_OTG_HPRT_PENA_Pos (2U)
+#define USB_OTG_HPRT_PENA_Msk (0x1U << USB_OTG_HPRT_PENA_Pos) /*!< 0x00000004 */
+#define USB_OTG_HPRT_PENA USB_OTG_HPRT_PENA_Msk /*!< Port enable */
+#define USB_OTG_HPRT_PENCHNG_Pos (3U)
+#define USB_OTG_HPRT_PENCHNG_Msk (0x1U << USB_OTG_HPRT_PENCHNG_Pos) /*!< 0x00000008 */
+#define USB_OTG_HPRT_PENCHNG USB_OTG_HPRT_PENCHNG_Msk /*!< Port enable/disable change */
+#define USB_OTG_HPRT_POCA_Pos (4U)
+#define USB_OTG_HPRT_POCA_Msk (0x1U << USB_OTG_HPRT_POCA_Pos) /*!< 0x00000010 */
+#define USB_OTG_HPRT_POCA USB_OTG_HPRT_POCA_Msk /*!< Port overcurrent active */
+#define USB_OTG_HPRT_POCCHNG_Pos (5U)
+#define USB_OTG_HPRT_POCCHNG_Msk (0x1U << USB_OTG_HPRT_POCCHNG_Pos) /*!< 0x00000020 */
+#define USB_OTG_HPRT_POCCHNG USB_OTG_HPRT_POCCHNG_Msk /*!< Port overcurrent change */
+#define USB_OTG_HPRT_PRES_Pos (6U)
+#define USB_OTG_HPRT_PRES_Msk (0x1U << USB_OTG_HPRT_PRES_Pos) /*!< 0x00000040 */
+#define USB_OTG_HPRT_PRES USB_OTG_HPRT_PRES_Msk /*!< Port resume */
+#define USB_OTG_HPRT_PSUSP_Pos (7U)
+#define USB_OTG_HPRT_PSUSP_Msk (0x1U << USB_OTG_HPRT_PSUSP_Pos) /*!< 0x00000080 */
+#define USB_OTG_HPRT_PSUSP USB_OTG_HPRT_PSUSP_Msk /*!< Port suspend */
+#define USB_OTG_HPRT_PRST_Pos (8U)
+#define USB_OTG_HPRT_PRST_Msk (0x1U << USB_OTG_HPRT_PRST_Pos) /*!< 0x00000100 */
+#define USB_OTG_HPRT_PRST USB_OTG_HPRT_PRST_Msk /*!< Port reset */
+
+#define USB_OTG_HPRT_PLSTS_Pos (10U)
+#define USB_OTG_HPRT_PLSTS_Msk (0x3U << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000C00 */
+#define USB_OTG_HPRT_PLSTS USB_OTG_HPRT_PLSTS_Msk /*!< Port line status */
+#define USB_OTG_HPRT_PLSTS_0 (0x1U << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000400 */
+#define USB_OTG_HPRT_PLSTS_1 (0x2U << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000800 */
+#define USB_OTG_HPRT_PPWR_Pos (12U)
+#define USB_OTG_HPRT_PPWR_Msk (0x1U << USB_OTG_HPRT_PPWR_Pos) /*!< 0x00001000 */
+#define USB_OTG_HPRT_PPWR USB_OTG_HPRT_PPWR_Msk /*!< Port power */
+
+#define USB_OTG_HPRT_PTCTL_Pos (13U)
+#define USB_OTG_HPRT_PTCTL_Msk (0xFU << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x0001E000 */
+#define USB_OTG_HPRT_PTCTL USB_OTG_HPRT_PTCTL_Msk /*!< Port test control */
+#define USB_OTG_HPRT_PTCTL_0 (0x1U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00002000 */
+#define USB_OTG_HPRT_PTCTL_1 (0x2U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00004000 */
+#define USB_OTG_HPRT_PTCTL_2 (0x4U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00008000 */
+#define USB_OTG_HPRT_PTCTL_3 (0x8U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00010000 */
+
+#define USB_OTG_HPRT_PSPD_Pos (17U)
+#define USB_OTG_HPRT_PSPD_Msk (0x3U << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00060000 */
+#define USB_OTG_HPRT_PSPD USB_OTG_HPRT_PSPD_Msk /*!< Port speed */
+#define USB_OTG_HPRT_PSPD_0 (0x1U << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00020000 */
+#define USB_OTG_HPRT_PSPD_1 (0x2U << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00040000 */
+
+/******************** Bit definition forUSB_OTG_DOEPEACHMSK1 register ************/
+#define USB_OTG_DOEPEACHMSK1_XFRCM_Pos (0U)
+#define USB_OTG_DOEPEACHMSK1_XFRCM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */
+#define USB_OTG_DOEPEACHMSK1_XFRCM USB_OTG_DOEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_EPDM_Pos (1U)
+#define USB_OTG_DOEPEACHMSK1_EPDM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */
+#define USB_OTG_DOEPEACHMSK1_EPDM USB_OTG_DOEPEACHMSK1_EPDM_Msk /*!< Endpoint disabled interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_TOM_Pos (3U)
+#define USB_OTG_DOEPEACHMSK1_TOM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */
+#define USB_OTG_DOEPEACHMSK1_TOM USB_OTG_DOEPEACHMSK1_TOM_Msk /*!< Timeout condition mask */
+#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos (4U)
+#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk (0x1U << USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */
+#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */
+#define USB_OTG_DOEPEACHMSK1_INEPNMM_Pos (5U)
+#define USB_OTG_DOEPEACHMSK1_INEPNMM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */
+#define USB_OTG_DOEPEACHMSK1_INEPNMM USB_OTG_DOEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask */
+#define USB_OTG_DOEPEACHMSK1_INEPNEM_Pos (6U)
+#define USB_OTG_DOEPEACHMSK1_INEPNEM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */
+#define USB_OTG_DOEPEACHMSK1_INEPNEM USB_OTG_DOEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask */
+#define USB_OTG_DOEPEACHMSK1_TXFURM_Pos (8U)
+#define USB_OTG_DOEPEACHMSK1_TXFURM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */
+#define USB_OTG_DOEPEACHMSK1_TXFURM USB_OTG_DOEPEACHMSK1_TXFURM_Msk /*!< OUT packet error mask */
+#define USB_OTG_DOEPEACHMSK1_BIM_Pos (9U)
+#define USB_OTG_DOEPEACHMSK1_BIM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */
+#define USB_OTG_DOEPEACHMSK1_BIM USB_OTG_DOEPEACHMSK1_BIM_Msk /*!< BNA interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_BERRM_Pos (12U)
+#define USB_OTG_DOEPEACHMSK1_BERRM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_BERRM_Pos) /*!< 0x00001000 */
+#define USB_OTG_DOEPEACHMSK1_BERRM USB_OTG_DOEPEACHMSK1_BERRM_Msk /*!< Bubble error interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_NAKM_Pos (13U)
+#define USB_OTG_DOEPEACHMSK1_NAKM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */
+#define USB_OTG_DOEPEACHMSK1_NAKM USB_OTG_DOEPEACHMSK1_NAKM_Msk /*!< NAK interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_NYETM_Pos (14U)
+#define USB_OTG_DOEPEACHMSK1_NYETM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_NYETM_Pos) /*!< 0x00004000 */
+#define USB_OTG_DOEPEACHMSK1_NYETM USB_OTG_DOEPEACHMSK1_NYETM_Msk /*!< NYET interrupt mask */
+
+/******************** Bit definition forUSB_OTG_HPTXFSIZ register ****************/
+#define USB_OTG_HPTXFSIZ_PTXSA_Pos (0U)
+#define USB_OTG_HPTXFSIZ_PTXSA_Msk (0xFFFFU << USB_OTG_HPTXFSIZ_PTXSA_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_HPTXFSIZ_PTXSA USB_OTG_HPTXFSIZ_PTXSA_Msk /*!< Host periodic TxFIFO start address */
+#define USB_OTG_HPTXFSIZ_PTXFD_Pos (16U)
+#define USB_OTG_HPTXFSIZ_PTXFD_Msk (0xFFFFU << USB_OTG_HPTXFSIZ_PTXFD_Pos) /*!< 0xFFFF0000 */
+#define USB_OTG_HPTXFSIZ_PTXFD USB_OTG_HPTXFSIZ_PTXFD_Msk /*!< Host periodic TxFIFO depth */
+
+/******************** Bit definition forUSB_OTG_DIEPCTL register *****************/
+#define USB_OTG_DIEPCTL_MPSIZ_Pos (0U)
+#define USB_OTG_DIEPCTL_MPSIZ_Msk (0x7FFU << USB_OTG_DIEPCTL_MPSIZ_Pos) /*!< 0x000007FF */
+#define USB_OTG_DIEPCTL_MPSIZ USB_OTG_DIEPCTL_MPSIZ_Msk /*!< Maximum packet size */
+#define USB_OTG_DIEPCTL_USBAEP_Pos (15U)
+#define USB_OTG_DIEPCTL_USBAEP_Msk (0x1U << USB_OTG_DIEPCTL_USBAEP_Pos) /*!< 0x00008000 */
+#define USB_OTG_DIEPCTL_USBAEP USB_OTG_DIEPCTL_USBAEP_Msk /*!< USB active endpoint */
+#define USB_OTG_DIEPCTL_EONUM_DPID_Pos (16U)
+#define USB_OTG_DIEPCTL_EONUM_DPID_Msk (0x1U << USB_OTG_DIEPCTL_EONUM_DPID_Pos) /*!< 0x00010000 */
+#define USB_OTG_DIEPCTL_EONUM_DPID USB_OTG_DIEPCTL_EONUM_DPID_Msk /*!< Even/odd frame */
+#define USB_OTG_DIEPCTL_NAKSTS_Pos (17U)
+#define USB_OTG_DIEPCTL_NAKSTS_Msk (0x1U << USB_OTG_DIEPCTL_NAKSTS_Pos) /*!< 0x00020000 */
+#define USB_OTG_DIEPCTL_NAKSTS USB_OTG_DIEPCTL_NAKSTS_Msk /*!< NAK status */
+
+#define USB_OTG_DIEPCTL_EPTYP_Pos (18U)
+#define USB_OTG_DIEPCTL_EPTYP_Msk (0x3U << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x000C0000 */
+#define USB_OTG_DIEPCTL_EPTYP USB_OTG_DIEPCTL_EPTYP_Msk /*!< Endpoint type */
+#define USB_OTG_DIEPCTL_EPTYP_0 (0x1U << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00040000 */
+#define USB_OTG_DIEPCTL_EPTYP_1 (0x2U << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00080000 */
+#define USB_OTG_DIEPCTL_STALL_Pos (21U)
+#define USB_OTG_DIEPCTL_STALL_Msk (0x1U << USB_OTG_DIEPCTL_STALL_Pos) /*!< 0x00200000 */
+#define USB_OTG_DIEPCTL_STALL USB_OTG_DIEPCTL_STALL_Msk /*!< STALL handshake */
+
+#define USB_OTG_DIEPCTL_TXFNUM_Pos (22U)
+#define USB_OTG_DIEPCTL_TXFNUM_Msk (0xFU << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x03C00000 */
+#define USB_OTG_DIEPCTL_TXFNUM USB_OTG_DIEPCTL_TXFNUM_Msk /*!< TxFIFO number */
+#define USB_OTG_DIEPCTL_TXFNUM_0 (0x1U << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00400000 */
+#define USB_OTG_DIEPCTL_TXFNUM_1 (0x2U << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00800000 */
+#define USB_OTG_DIEPCTL_TXFNUM_2 (0x4U << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x01000000 */
+#define USB_OTG_DIEPCTL_TXFNUM_3 (0x8U << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x02000000 */
+#define USB_OTG_DIEPCTL_CNAK_Pos (26U)
+#define USB_OTG_DIEPCTL_CNAK_Msk (0x1U << USB_OTG_DIEPCTL_CNAK_Pos) /*!< 0x04000000 */
+#define USB_OTG_DIEPCTL_CNAK USB_OTG_DIEPCTL_CNAK_Msk /*!< Clear NAK */
+#define USB_OTG_DIEPCTL_SNAK_Pos (27U)
+#define USB_OTG_DIEPCTL_SNAK_Msk (0x1U << USB_OTG_DIEPCTL_SNAK_Pos) /*!< 0x08000000 */
+#define USB_OTG_DIEPCTL_SNAK USB_OTG_DIEPCTL_SNAK_Msk /*!< Set NAK */
+#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos (28U)
+#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk (0x1U << USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */
+#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */
+#define USB_OTG_DIEPCTL_SODDFRM_Pos (29U)
+#define USB_OTG_DIEPCTL_SODDFRM_Msk (0x1U << USB_OTG_DIEPCTL_SODDFRM_Pos) /*!< 0x20000000 */
+#define USB_OTG_DIEPCTL_SODDFRM USB_OTG_DIEPCTL_SODDFRM_Msk /*!< Set odd frame */
+#define USB_OTG_DIEPCTL_EPDIS_Pos (30U)
+#define USB_OTG_DIEPCTL_EPDIS_Msk (0x1U << USB_OTG_DIEPCTL_EPDIS_Pos) /*!< 0x40000000 */
+#define USB_OTG_DIEPCTL_EPDIS USB_OTG_DIEPCTL_EPDIS_Msk /*!< Endpoint disable */
+#define USB_OTG_DIEPCTL_EPENA_Pos (31U)
+#define USB_OTG_DIEPCTL_EPENA_Msk (0x1U << USB_OTG_DIEPCTL_EPENA_Pos) /*!< 0x80000000 */
+#define USB_OTG_DIEPCTL_EPENA USB_OTG_DIEPCTL_EPENA_Msk /*!< Endpoint enable */
+
+/******************** Bit definition forUSB_OTG_HCCHAR register ******************/
+#define USB_OTG_HCCHAR_MPSIZ_Pos (0U)
+#define USB_OTG_HCCHAR_MPSIZ_Msk (0x7FFU << USB_OTG_HCCHAR_MPSIZ_Pos) /*!< 0x000007FF */
+#define USB_OTG_HCCHAR_MPSIZ USB_OTG_HCCHAR_MPSIZ_Msk /*!< Maximum packet size */
+
+#define USB_OTG_HCCHAR_EPNUM_Pos (11U)
+#define USB_OTG_HCCHAR_EPNUM_Msk (0xFU << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00007800 */
+#define USB_OTG_HCCHAR_EPNUM USB_OTG_HCCHAR_EPNUM_Msk /*!< Endpoint number */
+#define USB_OTG_HCCHAR_EPNUM_0 (0x1U << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00000800 */
+#define USB_OTG_HCCHAR_EPNUM_1 (0x2U << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00001000 */
+#define USB_OTG_HCCHAR_EPNUM_2 (0x4U << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00002000 */
+#define USB_OTG_HCCHAR_EPNUM_3 (0x8U << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00004000 */
+#define USB_OTG_HCCHAR_EPDIR_Pos (15U)
+#define USB_OTG_HCCHAR_EPDIR_Msk (0x1U << USB_OTG_HCCHAR_EPDIR_Pos) /*!< 0x00008000 */
+#define USB_OTG_HCCHAR_EPDIR USB_OTG_HCCHAR_EPDIR_Msk /*!< Endpoint direction */
+#define USB_OTG_HCCHAR_LSDEV_Pos (17U)
+#define USB_OTG_HCCHAR_LSDEV_Msk (0x1U << USB_OTG_HCCHAR_LSDEV_Pos) /*!< 0x00020000 */
+#define USB_OTG_HCCHAR_LSDEV USB_OTG_HCCHAR_LSDEV_Msk /*!< Low-speed device */
+
+#define USB_OTG_HCCHAR_EPTYP_Pos (18U)
+#define USB_OTG_HCCHAR_EPTYP_Msk (0x3U << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x000C0000 */
+#define USB_OTG_HCCHAR_EPTYP USB_OTG_HCCHAR_EPTYP_Msk /*!< Endpoint type */
+#define USB_OTG_HCCHAR_EPTYP_0 (0x1U << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00040000 */
+#define USB_OTG_HCCHAR_EPTYP_1 (0x2U << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00080000 */
+
+#define USB_OTG_HCCHAR_MC_Pos (20U)
+#define USB_OTG_HCCHAR_MC_Msk (0x3U << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00300000 */
+#define USB_OTG_HCCHAR_MC USB_OTG_HCCHAR_MC_Msk /*!< Multi Count (MC) / Error Count (EC) */
+#define USB_OTG_HCCHAR_MC_0 (0x1U << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00100000 */
+#define USB_OTG_HCCHAR_MC_1 (0x2U << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00200000 */
+
+#define USB_OTG_HCCHAR_DAD_Pos (22U)
+#define USB_OTG_HCCHAR_DAD_Msk (0x7FU << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x1FC00000 */
+#define USB_OTG_HCCHAR_DAD USB_OTG_HCCHAR_DAD_Msk /*!< Device address */
+#define USB_OTG_HCCHAR_DAD_0 (0x01U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00400000 */
+#define USB_OTG_HCCHAR_DAD_1 (0x02U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00800000 */
+#define USB_OTG_HCCHAR_DAD_2 (0x04U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x01000000 */
+#define USB_OTG_HCCHAR_DAD_3 (0x08U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x02000000 */
+#define USB_OTG_HCCHAR_DAD_4 (0x10U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x04000000 */
+#define USB_OTG_HCCHAR_DAD_5 (0x20U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x08000000 */
+#define USB_OTG_HCCHAR_DAD_6 (0x40U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x10000000 */
+#define USB_OTG_HCCHAR_ODDFRM_Pos (29U)
+#define USB_OTG_HCCHAR_ODDFRM_Msk (0x1U << USB_OTG_HCCHAR_ODDFRM_Pos) /*!< 0x20000000 */
+#define USB_OTG_HCCHAR_ODDFRM USB_OTG_HCCHAR_ODDFRM_Msk /*!< Odd frame */
+#define USB_OTG_HCCHAR_CHDIS_Pos (30U)
+#define USB_OTG_HCCHAR_CHDIS_Msk (0x1U << USB_OTG_HCCHAR_CHDIS_Pos) /*!< 0x40000000 */
+#define USB_OTG_HCCHAR_CHDIS USB_OTG_HCCHAR_CHDIS_Msk /*!< Channel disable */
+#define USB_OTG_HCCHAR_CHENA_Pos (31U)
+#define USB_OTG_HCCHAR_CHENA_Msk (0x1U << USB_OTG_HCCHAR_CHENA_Pos) /*!< 0x80000000 */
+#define USB_OTG_HCCHAR_CHENA USB_OTG_HCCHAR_CHENA_Msk /*!< Channel enable */
+
+/******************** Bit definition forUSB_OTG_HCSPLT register ******************/
+
+#define USB_OTG_HCSPLT_PRTADDR_Pos (0U)
+#define USB_OTG_HCSPLT_PRTADDR_Msk (0x7FU << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x0000007F */
+#define USB_OTG_HCSPLT_PRTADDR USB_OTG_HCSPLT_PRTADDR_Msk /*!< Port address */
+#define USB_OTG_HCSPLT_PRTADDR_0 (0x01U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000001 */
+#define USB_OTG_HCSPLT_PRTADDR_1 (0x02U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000002 */
+#define USB_OTG_HCSPLT_PRTADDR_2 (0x04U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000004 */
+#define USB_OTG_HCSPLT_PRTADDR_3 (0x08U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000008 */
+#define USB_OTG_HCSPLT_PRTADDR_4 (0x10U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000010 */
+#define USB_OTG_HCSPLT_PRTADDR_5 (0x20U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000020 */
+#define USB_OTG_HCSPLT_PRTADDR_6 (0x40U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000040 */
+
+#define USB_OTG_HCSPLT_HUBADDR_Pos (7U)
+#define USB_OTG_HCSPLT_HUBADDR_Msk (0x7FU << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00003F80 */
+#define USB_OTG_HCSPLT_HUBADDR USB_OTG_HCSPLT_HUBADDR_Msk /*!< Hub address */
+#define USB_OTG_HCSPLT_HUBADDR_0 (0x01U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000080 */
+#define USB_OTG_HCSPLT_HUBADDR_1 (0x02U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000100 */
+#define USB_OTG_HCSPLT_HUBADDR_2 (0x04U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000200 */
+#define USB_OTG_HCSPLT_HUBADDR_3 (0x08U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000400 */
+#define USB_OTG_HCSPLT_HUBADDR_4 (0x10U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000800 */
+#define USB_OTG_HCSPLT_HUBADDR_5 (0x20U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00001000 */
+#define USB_OTG_HCSPLT_HUBADDR_6 (0x40U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00002000 */
+
+#define USB_OTG_HCSPLT_XACTPOS_Pos (14U)
+#define USB_OTG_HCSPLT_XACTPOS_Msk (0x3U << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x0000C000 */
+#define USB_OTG_HCSPLT_XACTPOS USB_OTG_HCSPLT_XACTPOS_Msk /*!< XACTPOS */
+#define USB_OTG_HCSPLT_XACTPOS_0 (0x1U << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00004000 */
+#define USB_OTG_HCSPLT_XACTPOS_1 (0x2U << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00008000 */
+#define USB_OTG_HCSPLT_COMPLSPLT_Pos (16U)
+#define USB_OTG_HCSPLT_COMPLSPLT_Msk (0x1U << USB_OTG_HCSPLT_COMPLSPLT_Pos) /*!< 0x00010000 */
+#define USB_OTG_HCSPLT_COMPLSPLT USB_OTG_HCSPLT_COMPLSPLT_Msk /*!< Do complete split */
+#define USB_OTG_HCSPLT_SPLITEN_Pos (31U)
+#define USB_OTG_HCSPLT_SPLITEN_Msk (0x1U << USB_OTG_HCSPLT_SPLITEN_Pos) /*!< 0x80000000 */
+#define USB_OTG_HCSPLT_SPLITEN USB_OTG_HCSPLT_SPLITEN_Msk /*!< Split enable */
+
+/******************** Bit definition forUSB_OTG_HCINT register *******************/
+#define USB_OTG_HCINT_XFRC_Pos (0U)
+#define USB_OTG_HCINT_XFRC_Msk (0x1U << USB_OTG_HCINT_XFRC_Pos) /*!< 0x00000001 */
+#define USB_OTG_HCINT_XFRC USB_OTG_HCINT_XFRC_Msk /*!< Transfer completed */
+#define USB_OTG_HCINT_CHH_Pos (1U)
+#define USB_OTG_HCINT_CHH_Msk (0x1U << USB_OTG_HCINT_CHH_Pos) /*!< 0x00000002 */
+#define USB_OTG_HCINT_CHH USB_OTG_HCINT_CHH_Msk /*!< Channel halted */
+#define USB_OTG_HCINT_AHBERR_Pos (2U)
+#define USB_OTG_HCINT_AHBERR_Msk (0x1U << USB_OTG_HCINT_AHBERR_Pos) /*!< 0x00000004 */
+#define USB_OTG_HCINT_AHBERR USB_OTG_HCINT_AHBERR_Msk /*!< AHB error */
+#define USB_OTG_HCINT_STALL_Pos (3U)
+#define USB_OTG_HCINT_STALL_Msk (0x1U << USB_OTG_HCINT_STALL_Pos) /*!< 0x00000008 */
+#define USB_OTG_HCINT_STALL USB_OTG_HCINT_STALL_Msk /*!< STALL response received interrupt */
+#define USB_OTG_HCINT_NAK_Pos (4U)
+#define USB_OTG_HCINT_NAK_Msk (0x1U << USB_OTG_HCINT_NAK_Pos) /*!< 0x00000010 */
+#define USB_OTG_HCINT_NAK USB_OTG_HCINT_NAK_Msk /*!< NAK response received interrupt */
+#define USB_OTG_HCINT_ACK_Pos (5U)
+#define USB_OTG_HCINT_ACK_Msk (0x1U << USB_OTG_HCINT_ACK_Pos) /*!< 0x00000020 */
+#define USB_OTG_HCINT_ACK USB_OTG_HCINT_ACK_Msk /*!< ACK response received/transmitted interrupt */
+#define USB_OTG_HCINT_NYET_Pos (6U)
+#define USB_OTG_HCINT_NYET_Msk (0x1U << USB_OTG_HCINT_NYET_Pos) /*!< 0x00000040 */
+#define USB_OTG_HCINT_NYET USB_OTG_HCINT_NYET_Msk /*!< Response received interrupt */
+#define USB_OTG_HCINT_TXERR_Pos (7U)
+#define USB_OTG_HCINT_TXERR_Msk (0x1U << USB_OTG_HCINT_TXERR_Pos) /*!< 0x00000080 */
+#define USB_OTG_HCINT_TXERR USB_OTG_HCINT_TXERR_Msk /*!< Transaction error */
+#define USB_OTG_HCINT_BBERR_Pos (8U)
+#define USB_OTG_HCINT_BBERR_Msk (0x1U << USB_OTG_HCINT_BBERR_Pos) /*!< 0x00000100 */
+#define USB_OTG_HCINT_BBERR USB_OTG_HCINT_BBERR_Msk /*!< Babble error */
+#define USB_OTG_HCINT_FRMOR_Pos (9U)
+#define USB_OTG_HCINT_FRMOR_Msk (0x1U << USB_OTG_HCINT_FRMOR_Pos) /*!< 0x00000200 */
+#define USB_OTG_HCINT_FRMOR USB_OTG_HCINT_FRMOR_Msk /*!< Frame overrun */
+#define USB_OTG_HCINT_DTERR_Pos (10U)
+#define USB_OTG_HCINT_DTERR_Msk (0x1U << USB_OTG_HCINT_DTERR_Pos) /*!< 0x00000400 */
+#define USB_OTG_HCINT_DTERR USB_OTG_HCINT_DTERR_Msk /*!< Data toggle error */
+
+/******************** Bit definition forUSB_OTG_DIEPINT register *****************/
+#define USB_OTG_DIEPINT_XFRC_Pos (0U)
+#define USB_OTG_DIEPINT_XFRC_Msk (0x1U << USB_OTG_DIEPINT_XFRC_Pos) /*!< 0x00000001 */
+#define USB_OTG_DIEPINT_XFRC USB_OTG_DIEPINT_XFRC_Msk /*!< Transfer completed interrupt */
+#define USB_OTG_DIEPINT_EPDISD_Pos (1U)
+#define USB_OTG_DIEPINT_EPDISD_Msk (0x1U << USB_OTG_DIEPINT_EPDISD_Pos) /*!< 0x00000002 */
+#define USB_OTG_DIEPINT_EPDISD USB_OTG_DIEPINT_EPDISD_Msk /*!< Endpoint disabled interrupt */
+#define USB_OTG_DIEPINT_TOC_Pos (3U)
+#define USB_OTG_DIEPINT_TOC_Msk (0x1U << USB_OTG_DIEPINT_TOC_Pos) /*!< 0x00000008 */
+#define USB_OTG_DIEPINT_TOC USB_OTG_DIEPINT_TOC_Msk /*!< Timeout condition */
+#define USB_OTG_DIEPINT_ITTXFE_Pos (4U)
+#define USB_OTG_DIEPINT_ITTXFE_Msk (0x1U << USB_OTG_DIEPINT_ITTXFE_Pos) /*!< 0x00000010 */
+#define USB_OTG_DIEPINT_ITTXFE USB_OTG_DIEPINT_ITTXFE_Msk /*!< IN token received when TxFIFO is empty */
+#define USB_OTG_DIEPINT_INEPNE_Pos (6U)
+#define USB_OTG_DIEPINT_INEPNE_Msk (0x1U << USB_OTG_DIEPINT_INEPNE_Pos) /*!< 0x00000040 */
+#define USB_OTG_DIEPINT_INEPNE USB_OTG_DIEPINT_INEPNE_Msk /*!< IN endpoint NAK effective */
+#define USB_OTG_DIEPINT_TXFE_Pos (7U)
+#define USB_OTG_DIEPINT_TXFE_Msk (0x1U << USB_OTG_DIEPINT_TXFE_Pos) /*!< 0x00000080 */
+#define USB_OTG_DIEPINT_TXFE USB_OTG_DIEPINT_TXFE_Msk /*!< Transmit FIFO empty */
+#define USB_OTG_DIEPINT_TXFIFOUDRN_Pos (8U)
+#define USB_OTG_DIEPINT_TXFIFOUDRN_Msk (0x1U << USB_OTG_DIEPINT_TXFIFOUDRN_Pos) /*!< 0x00000100 */
+#define USB_OTG_DIEPINT_TXFIFOUDRN USB_OTG_DIEPINT_TXFIFOUDRN_Msk /*!< Transmit Fifo Underrun */
+#define USB_OTG_DIEPINT_BNA_Pos (9U)
+#define USB_OTG_DIEPINT_BNA_Msk (0x1U << USB_OTG_DIEPINT_BNA_Pos) /*!< 0x00000200 */
+#define USB_OTG_DIEPINT_BNA USB_OTG_DIEPINT_BNA_Msk /*!< Buffer not available interrupt */
+#define USB_OTG_DIEPINT_PKTDRPSTS_Pos (11U)
+#define USB_OTG_DIEPINT_PKTDRPSTS_Msk (0x1U << USB_OTG_DIEPINT_PKTDRPSTS_Pos) /*!< 0x00000800 */
+#define USB_OTG_DIEPINT_PKTDRPSTS USB_OTG_DIEPINT_PKTDRPSTS_Msk /*!< Packet dropped status */
+#define USB_OTG_DIEPINT_BERR_Pos (12U)
+#define USB_OTG_DIEPINT_BERR_Msk (0x1U << USB_OTG_DIEPINT_BERR_Pos) /*!< 0x00001000 */
+#define USB_OTG_DIEPINT_BERR USB_OTG_DIEPINT_BERR_Msk /*!< Babble error interrupt */
+#define USB_OTG_DIEPINT_NAK_Pos (13U)
+#define USB_OTG_DIEPINT_NAK_Msk (0x1U << USB_OTG_DIEPINT_NAK_Pos) /*!< 0x00002000 */
+#define USB_OTG_DIEPINT_NAK USB_OTG_DIEPINT_NAK_Msk /*!< NAK interrupt */
+
+/******************** Bit definition forUSB_OTG_HCINTMSK register ****************/
+#define USB_OTG_HCINTMSK_XFRCM_Pos (0U)
+#define USB_OTG_HCINTMSK_XFRCM_Msk (0x1U << USB_OTG_HCINTMSK_XFRCM_Pos) /*!< 0x00000001 */
+#define USB_OTG_HCINTMSK_XFRCM USB_OTG_HCINTMSK_XFRCM_Msk /*!< Transfer completed mask */
+#define USB_OTG_HCINTMSK_CHHM_Pos (1U)
+#define USB_OTG_HCINTMSK_CHHM_Msk (0x1U << USB_OTG_HCINTMSK_CHHM_Pos) /*!< 0x00000002 */
+#define USB_OTG_HCINTMSK_CHHM USB_OTG_HCINTMSK_CHHM_Msk /*!< Channel halted mask */
+#define USB_OTG_HCINTMSK_AHBERR_Pos (2U)
+#define USB_OTG_HCINTMSK_AHBERR_Msk (0x1U << USB_OTG_HCINTMSK_AHBERR_Pos) /*!< 0x00000004 */
+#define USB_OTG_HCINTMSK_AHBERR USB_OTG_HCINTMSK_AHBERR_Msk /*!< AHB error */
+#define USB_OTG_HCINTMSK_STALLM_Pos (3U)
+#define USB_OTG_HCINTMSK_STALLM_Msk (0x1U << USB_OTG_HCINTMSK_STALLM_Pos) /*!< 0x00000008 */
+#define USB_OTG_HCINTMSK_STALLM USB_OTG_HCINTMSK_STALLM_Msk /*!< STALL response received interrupt mask */
+#define USB_OTG_HCINTMSK_NAKM_Pos (4U)
+#define USB_OTG_HCINTMSK_NAKM_Msk (0x1U << USB_OTG_HCINTMSK_NAKM_Pos) /*!< 0x00000010 */
+#define USB_OTG_HCINTMSK_NAKM USB_OTG_HCINTMSK_NAKM_Msk /*!< NAK response received interrupt mask */
+#define USB_OTG_HCINTMSK_ACKM_Pos (5U)
+#define USB_OTG_HCINTMSK_ACKM_Msk (0x1U << USB_OTG_HCINTMSK_ACKM_Pos) /*!< 0x00000020 */
+#define USB_OTG_HCINTMSK_ACKM USB_OTG_HCINTMSK_ACKM_Msk /*!< ACK response received/transmitted interrupt mask */
+#define USB_OTG_HCINTMSK_NYET_Pos (6U)
+#define USB_OTG_HCINTMSK_NYET_Msk (0x1U << USB_OTG_HCINTMSK_NYET_Pos) /*!< 0x00000040 */
+#define USB_OTG_HCINTMSK_NYET USB_OTG_HCINTMSK_NYET_Msk /*!< response received interrupt mask */
+#define USB_OTG_HCINTMSK_TXERRM_Pos (7U)
+#define USB_OTG_HCINTMSK_TXERRM_Msk (0x1U << USB_OTG_HCINTMSK_TXERRM_Pos) /*!< 0x00000080 */
+#define USB_OTG_HCINTMSK_TXERRM USB_OTG_HCINTMSK_TXERRM_Msk /*!< Transaction error mask */
+#define USB_OTG_HCINTMSK_BBERRM_Pos (8U)
+#define USB_OTG_HCINTMSK_BBERRM_Msk (0x1U << USB_OTG_HCINTMSK_BBERRM_Pos) /*!< 0x00000100 */
+#define USB_OTG_HCINTMSK_BBERRM USB_OTG_HCINTMSK_BBERRM_Msk /*!< Babble error mask */
+#define USB_OTG_HCINTMSK_FRMORM_Pos (9U)
+#define USB_OTG_HCINTMSK_FRMORM_Msk (0x1U << USB_OTG_HCINTMSK_FRMORM_Pos) /*!< 0x00000200 */
+#define USB_OTG_HCINTMSK_FRMORM USB_OTG_HCINTMSK_FRMORM_Msk /*!< Frame overrun mask */
+#define USB_OTG_HCINTMSK_DTERRM_Pos (10U)
+#define USB_OTG_HCINTMSK_DTERRM_Msk (0x1U << USB_OTG_HCINTMSK_DTERRM_Pos) /*!< 0x00000400 */
+#define USB_OTG_HCINTMSK_DTERRM USB_OTG_HCINTMSK_DTERRM_Msk /*!< Data toggle error mask */
+
+/******************** Bit definition for USB_OTG_DIEPTSIZ register ***************/
+#define USB_OTG_DIEPTSIZ_XFRSIZ_Pos (0U)
+#define USB_OTG_DIEPTSIZ_XFRSIZ_Msk (0x7FFFFU << USB_OTG_DIEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
+#define USB_OTG_DIEPTSIZ_XFRSIZ USB_OTG_DIEPTSIZ_XFRSIZ_Msk /*!< Transfer size */
+#define USB_OTG_DIEPTSIZ_PKTCNT_Pos (19U)
+#define USB_OTG_DIEPTSIZ_PKTCNT_Msk (0x3FFU << USB_OTG_DIEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
+#define USB_OTG_DIEPTSIZ_PKTCNT USB_OTG_DIEPTSIZ_PKTCNT_Msk /*!< Packet count */
+#define USB_OTG_DIEPTSIZ_MULCNT_Pos (29U)
+#define USB_OTG_DIEPTSIZ_MULCNT_Msk (0x3U << USB_OTG_DIEPTSIZ_MULCNT_Pos) /*!< 0x60000000 */
+#define USB_OTG_DIEPTSIZ_MULCNT USB_OTG_DIEPTSIZ_MULCNT_Msk /*!< Packet count */
+
+/******************** Bit definition forUSB_OTG_HCTSIZ register ******************/
+#define USB_OTG_HCTSIZ_XFRSIZ_Pos (0U)
+#define USB_OTG_HCTSIZ_XFRSIZ_Msk (0x7FFFFU << USB_OTG_HCTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
+#define USB_OTG_HCTSIZ_XFRSIZ USB_OTG_HCTSIZ_XFRSIZ_Msk /*!< Transfer size */
+#define USB_OTG_HCTSIZ_PKTCNT_Pos (19U)
+#define USB_OTG_HCTSIZ_PKTCNT_Msk (0x3FFU << USB_OTG_HCTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
+#define USB_OTG_HCTSIZ_PKTCNT USB_OTG_HCTSIZ_PKTCNT_Msk /*!< Packet count */
+#define USB_OTG_HCTSIZ_DOPING_Pos (31U)
+#define USB_OTG_HCTSIZ_DOPING_Msk (0x1U << USB_OTG_HCTSIZ_DOPING_Pos) /*!< 0x80000000 */
+#define USB_OTG_HCTSIZ_DOPING USB_OTG_HCTSIZ_DOPING_Msk /*!< Do PING */
+#define USB_OTG_HCTSIZ_DPID_Pos (29U)
+#define USB_OTG_HCTSIZ_DPID_Msk (0x3U << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x60000000 */
+#define USB_OTG_HCTSIZ_DPID USB_OTG_HCTSIZ_DPID_Msk /*!< Data PID */
+#define USB_OTG_HCTSIZ_DPID_0 (0x1U << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x20000000 */
+#define USB_OTG_HCTSIZ_DPID_1 (0x2U << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x40000000 */
+
+/******************** Bit definition forUSB_OTG_DIEPDMA register *****************/
+#define USB_OTG_DIEPDMA_DMAADDR_Pos (0U)
+#define USB_OTG_DIEPDMA_DMAADDR_Msk (0xFFFFFFFFU << USB_OTG_DIEPDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */
+#define USB_OTG_DIEPDMA_DMAADDR USB_OTG_DIEPDMA_DMAADDR_Msk /*!< DMA address */
+
+/******************** Bit definition forUSB_OTG_HCDMA register *******************/
+#define USB_OTG_HCDMA_DMAADDR_Pos (0U)
+#define USB_OTG_HCDMA_DMAADDR_Msk (0xFFFFFFFFU << USB_OTG_HCDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */
+#define USB_OTG_HCDMA_DMAADDR USB_OTG_HCDMA_DMAADDR_Msk /*!< DMA address */
+
+/******************** Bit definition forUSB_OTG_DTXFSTS register *****************/
+#define USB_OTG_DTXFSTS_INEPTFSAV_Pos (0U)
+#define USB_OTG_DTXFSTS_INEPTFSAV_Msk (0xFFFFU << USB_OTG_DTXFSTS_INEPTFSAV_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_DTXFSTS_INEPTFSAV USB_OTG_DTXFSTS_INEPTFSAV_Msk /*!< IN endpoint TxFIFO space avail */
+
+/******************** Bit definition forUSB_OTG_DIEPTXF register *****************/
+#define USB_OTG_DIEPTXF_INEPTXSA_Pos (0U)
+#define USB_OTG_DIEPTXF_INEPTXSA_Msk (0xFFFFU << USB_OTG_DIEPTXF_INEPTXSA_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_DIEPTXF_INEPTXSA USB_OTG_DIEPTXF_INEPTXSA_Msk /*!< IN endpoint FIFOx transmit RAM start address */
+#define USB_OTG_DIEPTXF_INEPTXFD_Pos (16U)
+#define USB_OTG_DIEPTXF_INEPTXFD_Msk (0xFFFFU << USB_OTG_DIEPTXF_INEPTXFD_Pos) /*!< 0xFFFF0000 */
+#define USB_OTG_DIEPTXF_INEPTXFD USB_OTG_DIEPTXF_INEPTXFD_Msk /*!< IN endpoint TxFIFO depth */
+
+/******************** Bit definition forUSB_OTG_DOEPCTL register *****************/
+#define USB_OTG_DOEPCTL_MPSIZ_Pos (0U)
+#define USB_OTG_DOEPCTL_MPSIZ_Msk (0x7FFU << USB_OTG_DOEPCTL_MPSIZ_Pos) /*!< 0x000007FF */
+#define USB_OTG_DOEPCTL_MPSIZ USB_OTG_DOEPCTL_MPSIZ_Msk /*!< Maximum packet size */
+#define USB_OTG_DOEPCTL_USBAEP_Pos (15U)
+#define USB_OTG_DOEPCTL_USBAEP_Msk (0x1U << USB_OTG_DOEPCTL_USBAEP_Pos) /*!< 0x00008000 */
+#define USB_OTG_DOEPCTL_USBAEP USB_OTG_DOEPCTL_USBAEP_Msk /*!< USB active endpoint */
+#define USB_OTG_DOEPCTL_NAKSTS_Pos (17U)
+#define USB_OTG_DOEPCTL_NAKSTS_Msk (0x1U << USB_OTG_DOEPCTL_NAKSTS_Pos) /*!< 0x00020000 */
+#define USB_OTG_DOEPCTL_NAKSTS USB_OTG_DOEPCTL_NAKSTS_Msk /*!< NAK status */
+#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos (28U)
+#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk (0x1U << USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */
+#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */
+#define USB_OTG_DOEPCTL_SODDFRM_Pos (29U)
+#define USB_OTG_DOEPCTL_SODDFRM_Msk (0x1U << USB_OTG_DOEPCTL_SODDFRM_Pos) /*!< 0x20000000 */
+#define USB_OTG_DOEPCTL_SODDFRM USB_OTG_DOEPCTL_SODDFRM_Msk /*!< Set odd frame */
+#define USB_OTG_DOEPCTL_EPTYP_Pos (18U)
+#define USB_OTG_DOEPCTL_EPTYP_Msk (0x3U << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x000C0000 */
+#define USB_OTG_DOEPCTL_EPTYP USB_OTG_DOEPCTL_EPTYP_Msk /*!< Endpoint type */
+#define USB_OTG_DOEPCTL_EPTYP_0 (0x1U << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x00040000 */
+#define USB_OTG_DOEPCTL_EPTYP_1 (0x2U << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x00080000 */
+#define USB_OTG_DOEPCTL_SNPM_Pos (20U)
+#define USB_OTG_DOEPCTL_SNPM_Msk (0x1U << USB_OTG_DOEPCTL_SNPM_Pos) /*!< 0x00100000 */
+#define USB_OTG_DOEPCTL_SNPM USB_OTG_DOEPCTL_SNPM_Msk /*!< Snoop mode */
+#define USB_OTG_DOEPCTL_STALL_Pos (21U)
+#define USB_OTG_DOEPCTL_STALL_Msk (0x1U << USB_OTG_DOEPCTL_STALL_Pos) /*!< 0x00200000 */
+#define USB_OTG_DOEPCTL_STALL USB_OTG_DOEPCTL_STALL_Msk /*!< STALL handshake */
+#define USB_OTG_DOEPCTL_CNAK_Pos (26U)
+#define USB_OTG_DOEPCTL_CNAK_Msk (0x1U << USB_OTG_DOEPCTL_CNAK_Pos) /*!< 0x04000000 */
+#define USB_OTG_DOEPCTL_CNAK USB_OTG_DOEPCTL_CNAK_Msk /*!< Clear NAK */
+#define USB_OTG_DOEPCTL_SNAK_Pos (27U)
+#define USB_OTG_DOEPCTL_SNAK_Msk (0x1U << USB_OTG_DOEPCTL_SNAK_Pos) /*!< 0x08000000 */
+#define USB_OTG_DOEPCTL_SNAK USB_OTG_DOEPCTL_SNAK_Msk /*!< Set NAK */
+#define USB_OTG_DOEPCTL_EPDIS_Pos (30U)
+#define USB_OTG_DOEPCTL_EPDIS_Msk (0x1U << USB_OTG_DOEPCTL_EPDIS_Pos) /*!< 0x40000000 */
+#define USB_OTG_DOEPCTL_EPDIS USB_OTG_DOEPCTL_EPDIS_Msk /*!< Endpoint disable */
+#define USB_OTG_DOEPCTL_EPENA_Pos (31U)
+#define USB_OTG_DOEPCTL_EPENA_Msk (0x1U << USB_OTG_DOEPCTL_EPENA_Pos) /*!< 0x80000000 */
+#define USB_OTG_DOEPCTL_EPENA USB_OTG_DOEPCTL_EPENA_Msk /*!< Endpoint enable */
+
+/******************** Bit definition forUSB_OTG_DOEPINT register *****************/
+#define USB_OTG_DOEPINT_XFRC_Pos (0U)
+#define USB_OTG_DOEPINT_XFRC_Msk (0x1U << USB_OTG_DOEPINT_XFRC_Pos) /*!< 0x00000001 */
+#define USB_OTG_DOEPINT_XFRC USB_OTG_DOEPINT_XFRC_Msk /*!< Transfer completed interrupt */
+#define USB_OTG_DOEPINT_EPDISD_Pos (1U)
+#define USB_OTG_DOEPINT_EPDISD_Msk (0x1U << USB_OTG_DOEPINT_EPDISD_Pos) /*!< 0x00000002 */
+#define USB_OTG_DOEPINT_EPDISD USB_OTG_DOEPINT_EPDISD_Msk /*!< Endpoint disabled interrupt */
+#define USB_OTG_DOEPINT_STUP_Pos (3U)
+#define USB_OTG_DOEPINT_STUP_Msk (0x1U << USB_OTG_DOEPINT_STUP_Pos) /*!< 0x00000008 */
+#define USB_OTG_DOEPINT_STUP USB_OTG_DOEPINT_STUP_Msk /*!< SETUP phase done */
+#define USB_OTG_DOEPINT_OTEPDIS_Pos (4U)
+#define USB_OTG_DOEPINT_OTEPDIS_Msk (0x1U << USB_OTG_DOEPINT_OTEPDIS_Pos) /*!< 0x00000010 */
+#define USB_OTG_DOEPINT_OTEPDIS USB_OTG_DOEPINT_OTEPDIS_Msk /*!< OUT token received when endpoint disabled */
+#define USB_OTG_DOEPINT_B2BSTUP_Pos (6U)
+#define USB_OTG_DOEPINT_B2BSTUP_Msk (0x1U << USB_OTG_DOEPINT_B2BSTUP_Pos) /*!< 0x00000040 */
+#define USB_OTG_DOEPINT_B2BSTUP USB_OTG_DOEPINT_B2BSTUP_Msk /*!< Back-to-back SETUP packets received */
+#define USB_OTG_DOEPINT_NYET_Pos (14U)
+#define USB_OTG_DOEPINT_NYET_Msk (0x1U << USB_OTG_DOEPINT_NYET_Pos) /*!< 0x00004000 */
+#define USB_OTG_DOEPINT_NYET USB_OTG_DOEPINT_NYET_Msk /*!< NYET interrupt */
+
+/******************** Bit definition forUSB_OTG_DOEPTSIZ register ****************/
+#define USB_OTG_DOEPTSIZ_XFRSIZ_Pos (0U)
+#define USB_OTG_DOEPTSIZ_XFRSIZ_Msk (0x7FFFFU << USB_OTG_DOEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
+#define USB_OTG_DOEPTSIZ_XFRSIZ USB_OTG_DOEPTSIZ_XFRSIZ_Msk /*!< Transfer size */
+#define USB_OTG_DOEPTSIZ_PKTCNT_Pos (19U)
+#define USB_OTG_DOEPTSIZ_PKTCNT_Msk (0x3FFU << USB_OTG_DOEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
+#define USB_OTG_DOEPTSIZ_PKTCNT USB_OTG_DOEPTSIZ_PKTCNT_Msk /*!< Packet count */
+
+#define USB_OTG_DOEPTSIZ_STUPCNT_Pos (29U)
+#define USB_OTG_DOEPTSIZ_STUPCNT_Msk (0x3U << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x60000000 */
+#define USB_OTG_DOEPTSIZ_STUPCNT USB_OTG_DOEPTSIZ_STUPCNT_Msk /*!< SETUP packet count */
+#define USB_OTG_DOEPTSIZ_STUPCNT_0 (0x1U << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x20000000 */
+#define USB_OTG_DOEPTSIZ_STUPCNT_1 (0x2U << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x40000000 */
+
+/******************** Bit definition for PCGCCTL register ************************/
+#define USB_OTG_PCGCCTL_STOPCLK_Pos (0U)
+#define USB_OTG_PCGCCTL_STOPCLK_Msk (0x1U << USB_OTG_PCGCCTL_STOPCLK_Pos) /*!< 0x00000001 */
+#define USB_OTG_PCGCCTL_STOPCLK USB_OTG_PCGCCTL_STOPCLK_Msk /*!< SETUP packet count */
+#define USB_OTG_PCGCCTL_GATECLK_Pos (1U)
+#define USB_OTG_PCGCCTL_GATECLK_Msk (0x1U << USB_OTG_PCGCCTL_GATECLK_Pos) /*!< 0x00000002 */
+#define USB_OTG_PCGCCTL_GATECLK USB_OTG_PCGCCTL_GATECLK_Msk /*!<Bit 0 */
+#define USB_OTG_PCGCCTL_PHYSUSP_Pos (4U)
+#define USB_OTG_PCGCCTL_PHYSUSP_Msk (0x1U << USB_OTG_PCGCCTL_PHYSUSP_Pos) /*!< 0x00000010 */
+#define USB_OTG_PCGCCTL_PHYSUSP USB_OTG_PCGCCTL_PHYSUSP_Msk /*!<Bit 1 */
+
+/**
+ * @}
+*/
+
+/**
+ * @}
+*/
+
+/** @addtogroup Exported_macro
+ * @{
+ */
+
+/****************************** ADC Instances *********************************/
+#define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) || \
+ ((INSTANCE) == ADC2))
+
+#define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC12_COMMON)
+
+#define IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
+
+#define IS_ADC_DMA_CAPABILITY_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
+
+/****************************** CAN Instances *********************************/
+#define IS_CAN_ALL_INSTANCE(INSTANCE) (((INSTANCE) == CAN1) || \
+ ((INSTANCE) == CAN2))
+
+/****************************** CRC Instances *********************************/
+#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
+
+/****************************** DAC Instances *********************************/
+#define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC)
+
+/****************************** DMA Instances *********************************/
+#define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \
+ ((INSTANCE) == DMA1_Channel2) || \
+ ((INSTANCE) == DMA1_Channel3) || \
+ ((INSTANCE) == DMA1_Channel4) || \
+ ((INSTANCE) == DMA1_Channel5) || \
+ ((INSTANCE) == DMA1_Channel6) || \
+ ((INSTANCE) == DMA1_Channel7) || \
+ ((INSTANCE) == DMA2_Channel1) || \
+ ((INSTANCE) == DMA2_Channel2) || \
+ ((INSTANCE) == DMA2_Channel3) || \
+ ((INSTANCE) == DMA2_Channel4) || \
+ ((INSTANCE) == DMA2_Channel5))
+
+/******************************* GPIO Instances *******************************/
+#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
+ ((INSTANCE) == GPIOB) || \
+ ((INSTANCE) == GPIOC) || \
+ ((INSTANCE) == GPIOD) || \
+ ((INSTANCE) == GPIOE))
+
+/**************************** GPIO Alternate Function Instances ***************/
+#define IS_GPIO_AF_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
+
+/**************************** GPIO Lock Instances *****************************/
+#define IS_GPIO_LOCK_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
+
+/******************************** I2C Instances *******************************/
+#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
+ ((INSTANCE) == I2C2))
+
+/******************************** I2S Instances *******************************/
+#define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI2) || \
+ ((INSTANCE) == SPI3))
+
+/****************************** IWDG Instances ********************************/
+#define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
+
+/******************************** SPI Instances *******************************/
+#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
+ ((INSTANCE) == SPI2) || \
+ ((INSTANCE) == SPI3))
+
+/****************************** START TIM Instances ***************************/
+/****************************** TIM Instances *********************************/
+#define IS_TIM_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM6) || \
+ ((INSTANCE) == TIM7))
+
+#define IS_TIM_CC1_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5))
+
+#define IS_TIM_CC2_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5))
+
+#define IS_TIM_CC3_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5))
+
+#define IS_TIM_CC4_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5))
+
+#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5))
+
+#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5))
+
+#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5))
+
+#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5))
+
+#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5))
+
+#define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5))
+
+#define IS_TIM_XOR_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5))
+
+#define IS_TIM_MASTER_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM6) || \
+ ((INSTANCE) == TIM7))
+
+#define IS_TIM_SLAVE_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5))
+
+#define IS_TIM_DMABURST_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5))
+
+#define IS_TIM_BREAK_INSTANCE(INSTANCE)\
+ ((INSTANCE) == TIM1)
+
+#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
+ ((((INSTANCE) == TIM1) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM2) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM3) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM4) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM5) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))))
+
+#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
+ (((INSTANCE) == TIM1) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3)))
+
+#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5))
+
+#define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE)\
+ ((INSTANCE) == TIM1)
+
+#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5))
+
+#define IS_TIM_DMA_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM6) || \
+ ((INSTANCE) == TIM7))
+
+#define IS_TIM_DMA_CC_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5))
+
+#define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE)\
+ ((INSTANCE) == TIM1)
+
+/****************************** END TIM Instances *****************************/
+
+
+/******************** USART Instances : Synchronous mode **********************/
+#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3))
+
+/******************** UART Instances : Asynchronous mode **********************/
+#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3) || \
+ ((INSTANCE) == UART4) || \
+ ((INSTANCE) == UART5))
+
+/******************** UART Instances : Half-Duplex mode **********************/
+#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3) || \
+ ((INSTANCE) == UART4) || \
+ ((INSTANCE) == UART5))
+
+/******************** UART Instances : LIN mode **********************/
+#define IS_UART_LIN_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3) || \
+ ((INSTANCE) == UART4) || \
+ ((INSTANCE) == UART5))
+
+/****************** UART Instances : Hardware Flow control ********************/
+#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3))
+
+/********************* UART Instances : Smard card mode ***********************/
+#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3))
+
+/*********************** UART Instances : IRDA mode ***************************/
+#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3) || \
+ ((INSTANCE) == UART4) || \
+ ((INSTANCE) == UART5))
+
+/***************** UART Instances : Multi-Processor mode **********************/
+#define IS_UART_MULTIPROCESSOR_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3) || \
+ ((INSTANCE) == UART4) || \
+ ((INSTANCE) == UART5))
+
+/***************** UART Instances : DMA mode available **********************/
+#define IS_UART_DMA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3) || \
+ ((INSTANCE) == UART4))
+
+/****************************** RTC Instances *********************************/
+#define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
+
+/**************************** WWDG Instances *****************************/
+#define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
+
+
+/****************************** USB Instances ********************************/
+#define IS_USB_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB_OTG_FS)
+
+
+
+/**
+ * @}
+*/
+/******************************************************************************/
+/* For a painless codes migration between the STM32F1xx device product */
+/* lines, the aliases defined below are put in place to overcome the */
+/* differences in the interrupt handlers and IRQn definitions. */
+/* No need to update developed interrupt code when moving across */
+/* product lines within the same STM32F1 Family */
+/******************************************************************************/
+
+/* Aliases for __IRQn */
+#define ADC1_IRQn ADC1_2_IRQn
+#define USB_LP_IRQn CAN1_RX0_IRQn
+#define USB_LP_CAN1_RX0_IRQn CAN1_RX0_IRQn
+#define USB_HP_CAN1_TX_IRQn CAN1_TX_IRQn
+#define USB_HP_IRQn CAN1_TX_IRQn
+#define DMA2_Channel4_5_IRQn DMA2_Channel4_IRQn
+#define USBWakeUp_IRQn OTG_FS_WKUP_IRQn
+#define CEC_IRQn OTG_FS_WKUP_IRQn
+#define TIM1_BRK_TIM15_IRQn TIM1_BRK_IRQn
+#define TIM1_BRK_TIM9_IRQn TIM1_BRK_IRQn
+#define TIM9_IRQn TIM1_BRK_IRQn
+#define TIM1_TRG_COM_TIM11_IRQn TIM1_TRG_COM_IRQn
+#define TIM1_TRG_COM_TIM17_IRQn TIM1_TRG_COM_IRQn
+#define TIM11_IRQn TIM1_TRG_COM_IRQn
+#define TIM10_IRQn TIM1_UP_IRQn
+#define TIM1_UP_TIM16_IRQn TIM1_UP_IRQn
+#define TIM1_UP_TIM10_IRQn TIM1_UP_IRQn
+#define TIM6_DAC_IRQn TIM6_IRQn
+
+
+/* Aliases for __IRQHandler */
+#define ADC1_IRQHandler ADC1_2_IRQHandler
+#define USB_LP_IRQHandler CAN1_RX0_IRQHandler
+#define USB_LP_CAN1_RX0_IRQHandler CAN1_RX0_IRQHandler
+#define USB_HP_CAN1_TX_IRQHandler CAN1_TX_IRQHandler
+#define USB_HP_IRQHandler CAN1_TX_IRQHandler
+#define DMA2_Channel4_5_IRQHandler DMA2_Channel4_IRQHandler
+#define USBWakeUp_IRQHandler OTG_FS_WKUP_IRQHandler
+#define CEC_IRQHandler OTG_FS_WKUP_IRQHandler
+#define TIM1_BRK_TIM15_IRQHandler TIM1_BRK_IRQHandler
+#define TIM1_BRK_TIM9_IRQHandler TIM1_BRK_IRQHandler
+#define TIM9_IRQHandler TIM1_BRK_IRQHandler
+#define TIM1_TRG_COM_TIM11_IRQHandler TIM1_TRG_COM_IRQHandler
+#define TIM1_TRG_COM_TIM17_IRQHandler TIM1_TRG_COM_IRQHandler
+#define TIM11_IRQHandler TIM1_TRG_COM_IRQHandler
+#define TIM10_IRQHandler TIM1_UP_IRQHandler
+#define TIM1_UP_TIM16_IRQHandler TIM1_UP_IRQHandler
+#define TIM1_UP_TIM10_IRQHandler TIM1_UP_IRQHandler
+#define TIM6_DAC_IRQHandler TIM6_IRQHandler
+
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+
+#ifdef __cplusplus
+ }
+#endif /* __cplusplus */
+
+#endif /* __STM32F105xC_H */
+
+
+
+ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Device/ST/STM32F1xx/Include/stm32f107xc.h b/Device/ST/STM32F1xx/Include/stm32f107xc.h
new file mode 100644
index 0000000..542f5aa
--- /dev/null
+++ b/Device/ST/STM32F1xx/Include/stm32f107xc.h
@@ -0,0 +1,16051 @@
+/**
+ ******************************************************************************
+ * @file stm32f107xc.h
+ * @author MCD Application Team
+ * @version V4.1.0
+ * @date 29-April-2016
+ * @brief CMSIS Cortex-M3 Device Peripheral Access Layer Header File.
+ * This file contains all the peripheral register's definitions, bits
+ * definitions and memory mapping for STM32F1xx devices.
+ *
+ * This file contains:
+ * - Data structures and the address mapping for all peripherals
+ * - Peripheral's registers declarations and bits definition
+ * - Macros to access peripheral’s registers hardware
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+
+/** @addtogroup CMSIS
+ * @{
+ */
+
+/** @addtogroup stm32f107xc
+ * @{
+ */
+
+#ifndef __STM32F107xC_H
+#define __STM32F107xC_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/** @addtogroup Configuration_section_for_CMSIS
+ * @{
+ */
+/**
+ * @brief Configuration of the Cortex-M3 Processor and Core Peripherals
+ */
+ #define __MPU_PRESENT 0 /*!< Other STM32 devices does not provide an MPU */
+#define __CM3_REV 0x0200 /*!< Core Revision r2p0 */
+#define __NVIC_PRIO_BITS 4 /*!< STM32 uses 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
+
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_interrupt_number_definition
+ * @{
+ */
+
+/**
+ * @brief STM32F10x Interrupt Number Definition, according to the selected device
+ * in @ref Library_configuration_section
+ */
+
+ /*!< Interrupt Number Definition */
+typedef enum
+{
+/****** Cortex-M3 Processor Exceptions Numbers ***************************************************/
+ NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
+ HardFault_IRQn = -13, /*!< 3 Cortex-M3 Hard Fault Interrupt */
+ MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */
+ BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */
+ UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */
+ SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */
+ DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */
+ PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */
+ SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */
+
+/****** STM32 specific Interrupt Numbers *********************************************************/
+ WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
+ PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */
+ TAMPER_IRQn = 2, /*!< Tamper Interrupt */
+ RTC_IRQn = 3, /*!< RTC global Interrupt */
+ FLASH_IRQn = 4, /*!< FLASH global Interrupt */
+ RCC_IRQn = 5, /*!< RCC global Interrupt */
+ EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */
+ EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */
+ EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */
+ EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */
+ EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */
+ DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 global Interrupt */
+ DMA1_Channel2_IRQn = 12, /*!< DMA1 Channel 2 global Interrupt */
+ DMA1_Channel3_IRQn = 13, /*!< DMA1 Channel 3 global Interrupt */
+ DMA1_Channel4_IRQn = 14, /*!< DMA1 Channel 4 global Interrupt */
+ DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 global Interrupt */
+ DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 global Interrupt */
+ DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 global Interrupt */
+ ADC1_2_IRQn = 18, /*!< ADC1 and ADC2 global Interrupt */
+ CAN1_TX_IRQn = 19, /*!< CAN1 TX Interrupts */
+ CAN1_RX0_IRQn = 20, /*!< CAN1 RX0 Interrupts */
+ CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */
+ CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */
+ EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
+ TIM1_BRK_IRQn = 24, /*!< TIM1 Break Interrupt */
+ TIM1_UP_IRQn = 25, /*!< TIM1 Update Interrupt */
+ TIM1_TRG_COM_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt */
+ TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
+ TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
+ TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
+ TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
+ I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
+ I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
+ I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
+ I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
+ SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
+ SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
+ USART1_IRQn = 37, /*!< USART1 global Interrupt */
+ USART2_IRQn = 38, /*!< USART2 global Interrupt */
+ USART3_IRQn = 39, /*!< USART3 global Interrupt */
+ EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
+ RTC_Alarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */
+ OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS WakeUp from suspend through EXTI Line Interrupt */
+ TIM5_IRQn = 50, /*!< TIM5 global Interrupt */
+ SPI3_IRQn = 51, /*!< SPI3 global Interrupt */
+ UART4_IRQn = 52, /*!< UART4 global Interrupt */
+ UART5_IRQn = 53, /*!< UART5 global Interrupt */
+ TIM6_IRQn = 54, /*!< TIM6 global Interrupt */
+ TIM7_IRQn = 55, /*!< TIM7 global Interrupt */
+ DMA2_Channel1_IRQn = 56, /*!< DMA2 Channel 1 global Interrupt */
+ DMA2_Channel2_IRQn = 57, /*!< DMA2 Channel 2 global Interrupt */
+ DMA2_Channel3_IRQn = 58, /*!< DMA2 Channel 3 global Interrupt */
+ DMA2_Channel4_IRQn = 59, /*!< DMA2 Channel 4 global Interrupt */
+ DMA2_Channel5_IRQn = 60, /*!< DMA2 Channel 5 global Interrupt */
+ ETH_IRQn = 61, /*!< Ethernet global Interrupt */
+ ETH_WKUP_IRQn = 62, /*!< Ethernet Wakeup through EXTI line Interrupt */
+ CAN2_TX_IRQn = 63, /*!< CAN2 TX Interrupt */
+ CAN2_RX0_IRQn = 64, /*!< CAN2 RX0 Interrupt */
+ CAN2_RX1_IRQn = 65, /*!< CAN2 RX1 Interrupt */
+ CAN2_SCE_IRQn = 66, /*!< CAN2 SCE Interrupt */
+ OTG_FS_IRQn = 67 /*!< USB OTG FS global Interrupt */
+} IRQn_Type;
+
+
+/**
+ * @}
+ */
+
+#include "core_cm3.h"
+#include "system_stm32f1xx.h"
+#include <stdint.h>
+
+/** @addtogroup Peripheral_registers_structures
+ * @{
+ */
+
+/**
+ * @brief Analog to Digital Converter
+ */
+
+typedef struct
+{
+ __IO uint32_t SR;
+ __IO uint32_t CR1;
+ __IO uint32_t CR2;
+ __IO uint32_t SMPR1;
+ __IO uint32_t SMPR2;
+ __IO uint32_t JOFR1;
+ __IO uint32_t JOFR2;
+ __IO uint32_t JOFR3;
+ __IO uint32_t JOFR4;
+ __IO uint32_t HTR;
+ __IO uint32_t LTR;
+ __IO uint32_t SQR1;
+ __IO uint32_t SQR2;
+ __IO uint32_t SQR3;
+ __IO uint32_t JSQR;
+ __IO uint32_t JDR1;
+ __IO uint32_t JDR2;
+ __IO uint32_t JDR3;
+ __IO uint32_t JDR4;
+ __IO uint32_t DR;
+} ADC_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t SR; /*!< ADC status register, used for ADC multimode (bits common to several ADC instances). Address offset: ADC1 base address */
+ __IO uint32_t CR1; /*!< ADC control register 1, used for ADC multimode (bits common to several ADC instances). Address offset: ADC1 base address + 0x04 */
+ __IO uint32_t CR2; /*!< ADC control register 2, used for ADC multimode (bits common to several ADC instances). Address offset: ADC1 base address + 0x08 */
+ uint32_t RESERVED[16];
+ __IO uint32_t DR; /*!< ADC data register, used for ADC multimode (bits common to several ADC instances). Address offset: ADC1 base address + 0x4C */
+} ADC_Common_TypeDef;
+
+/**
+ * @brief Backup Registers
+ */
+
+typedef struct
+{
+ uint32_t RESERVED0;
+ __IO uint32_t DR1;
+ __IO uint32_t DR2;
+ __IO uint32_t DR3;
+ __IO uint32_t DR4;
+ __IO uint32_t DR5;
+ __IO uint32_t DR6;
+ __IO uint32_t DR7;
+ __IO uint32_t DR8;
+ __IO uint32_t DR9;
+ __IO uint32_t DR10;
+ __IO uint32_t RTCCR;
+ __IO uint32_t CR;
+ __IO uint32_t CSR;
+ uint32_t RESERVED13[2];
+ __IO uint32_t DR11;
+ __IO uint32_t DR12;
+ __IO uint32_t DR13;
+ __IO uint32_t DR14;
+ __IO uint32_t DR15;
+ __IO uint32_t DR16;
+ __IO uint32_t DR17;
+ __IO uint32_t DR18;
+ __IO uint32_t DR19;
+ __IO uint32_t DR20;
+ __IO uint32_t DR21;
+ __IO uint32_t DR22;
+ __IO uint32_t DR23;
+ __IO uint32_t DR24;
+ __IO uint32_t DR25;
+ __IO uint32_t DR26;
+ __IO uint32_t DR27;
+ __IO uint32_t DR28;
+ __IO uint32_t DR29;
+ __IO uint32_t DR30;
+ __IO uint32_t DR31;
+ __IO uint32_t DR32;
+ __IO uint32_t DR33;
+ __IO uint32_t DR34;
+ __IO uint32_t DR35;
+ __IO uint32_t DR36;
+ __IO uint32_t DR37;
+ __IO uint32_t DR38;
+ __IO uint32_t DR39;
+ __IO uint32_t DR40;
+ __IO uint32_t DR41;
+ __IO uint32_t DR42;
+} BKP_TypeDef;
+
+/**
+ * @brief Controller Area Network TxMailBox
+ */
+
+typedef struct
+{
+ __IO uint32_t TIR;
+ __IO uint32_t TDTR;
+ __IO uint32_t TDLR;
+ __IO uint32_t TDHR;
+} CAN_TxMailBox_TypeDef;
+
+/**
+ * @brief Controller Area Network FIFOMailBox
+ */
+
+typedef struct
+{
+ __IO uint32_t RIR;
+ __IO uint32_t RDTR;
+ __IO uint32_t RDLR;
+ __IO uint32_t RDHR;
+} CAN_FIFOMailBox_TypeDef;
+
+/**
+ * @brief Controller Area Network FilterRegister
+ */
+
+typedef struct
+{
+ __IO uint32_t FR1;
+ __IO uint32_t FR2;
+} CAN_FilterRegister_TypeDef;
+
+/**
+ * @brief Controller Area Network
+ */
+
+typedef struct
+{
+ __IO uint32_t MCR;
+ __IO uint32_t MSR;
+ __IO uint32_t TSR;
+ __IO uint32_t RF0R;
+ __IO uint32_t RF1R;
+ __IO uint32_t IER;
+ __IO uint32_t ESR;
+ __IO uint32_t BTR;
+ uint32_t RESERVED0[88];
+ CAN_TxMailBox_TypeDef sTxMailBox[3];
+ CAN_FIFOMailBox_TypeDef sFIFOMailBox[2];
+ uint32_t RESERVED1[12];
+ __IO uint32_t FMR;
+ __IO uint32_t FM1R;
+ uint32_t RESERVED2;
+ __IO uint32_t FS1R;
+ uint32_t RESERVED3;
+ __IO uint32_t FFA1R;
+ uint32_t RESERVED4;
+ __IO uint32_t FA1R;
+ uint32_t RESERVED5[8];
+ CAN_FilterRegister_TypeDef sFilterRegister[28];
+} CAN_TypeDef;
+
+/**
+ * @brief CRC calculation unit
+ */
+
+typedef struct
+{
+ __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
+ __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
+ uint8_t RESERVED0; /*!< Reserved, Address offset: 0x05 */
+ uint16_t RESERVED1; /*!< Reserved, Address offset: 0x06 */
+ __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
+} CRC_TypeDef;
+
+/**
+ * @brief Digital to Analog Converter
+ */
+
+typedef struct
+{
+ __IO uint32_t CR;
+ __IO uint32_t SWTRIGR;
+ __IO uint32_t DHR12R1;
+ __IO uint32_t DHR12L1;
+ __IO uint32_t DHR8R1;
+ __IO uint32_t DHR12R2;
+ __IO uint32_t DHR12L2;
+ __IO uint32_t DHR8R2;
+ __IO uint32_t DHR12RD;
+ __IO uint32_t DHR12LD;
+ __IO uint32_t DHR8RD;
+ __IO uint32_t DOR1;
+ __IO uint32_t DOR2;
+} DAC_TypeDef;
+
+/**
+ * @brief Debug MCU
+ */
+
+typedef struct
+{
+ __IO uint32_t IDCODE;
+ __IO uint32_t CR;
+}DBGMCU_TypeDef;
+
+/**
+ * @brief DMA Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t CCR;
+ __IO uint32_t CNDTR;
+ __IO uint32_t CPAR;
+ __IO uint32_t CMAR;
+} DMA_Channel_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t ISR;
+ __IO uint32_t IFCR;
+} DMA_TypeDef;
+
+
+
+/**
+ * @brief Ethernet MAC
+ */
+
+typedef struct
+{
+ __IO uint32_t MACCR;
+ __IO uint32_t MACFFR;
+ __IO uint32_t MACHTHR;
+ __IO uint32_t MACHTLR;
+ __IO uint32_t MACMIIAR;
+ __IO uint32_t MACMIIDR;
+ __IO uint32_t MACFCR;
+ __IO uint32_t MACVLANTR; /* 8 */
+ uint32_t RESERVED0[2];
+ __IO uint32_t MACRWUFFR; /* 11 */
+ __IO uint32_t MACPMTCSR;
+ uint32_t RESERVED1[2];
+ __IO uint32_t MACSR; /* 15 */
+ __IO uint32_t MACIMR;
+ __IO uint32_t MACA0HR;
+ __IO uint32_t MACA0LR;
+ __IO uint32_t MACA1HR;
+ __IO uint32_t MACA1LR;
+ __IO uint32_t MACA2HR;
+ __IO uint32_t MACA2LR;
+ __IO uint32_t MACA3HR;
+ __IO uint32_t MACA3LR; /* 24 */
+ uint32_t RESERVED2[40];
+ __IO uint32_t MMCCR; /* 65 */
+ __IO uint32_t MMCRIR;
+ __IO uint32_t MMCTIR;
+ __IO uint32_t MMCRIMR;
+ __IO uint32_t MMCTIMR; /* 69 */
+ uint32_t RESERVED3[14];
+ __IO uint32_t MMCTGFSCCR; /* 84 */
+ __IO uint32_t MMCTGFMSCCR;
+ uint32_t RESERVED4[5];
+ __IO uint32_t MMCTGFCR;
+ uint32_t RESERVED5[10];
+ __IO uint32_t MMCRFCECR;
+ __IO uint32_t MMCRFAECR;
+ uint32_t RESERVED6[10];
+ __IO uint32_t MMCRGUFCR;
+ uint32_t RESERVED7[334];
+ __IO uint32_t PTPTSCR;
+ __IO uint32_t PTPSSIR;
+ __IO uint32_t PTPTSHR;
+ __IO uint32_t PTPTSLR;
+ __IO uint32_t PTPTSHUR;
+ __IO uint32_t PTPTSLUR;
+ __IO uint32_t PTPTSAR;
+ __IO uint32_t PTPTTHR;
+ __IO uint32_t PTPTTLR;
+ uint32_t RESERVED8[567];
+ __IO uint32_t DMABMR;
+ __IO uint32_t DMATPDR;
+ __IO uint32_t DMARPDR;
+ __IO uint32_t DMARDLAR;
+ __IO uint32_t DMATDLAR;
+ __IO uint32_t DMASR;
+ __IO uint32_t DMAOMR;
+ __IO uint32_t DMAIER;
+ __IO uint32_t DMAMFBOCR;
+ uint32_t RESERVED9[9];
+ __IO uint32_t DMACHTDR;
+ __IO uint32_t DMACHRDR;
+ __IO uint32_t DMACHTBAR;
+ __IO uint32_t DMACHRBAR;
+} ETH_TypeDef;
+
+
+/**
+ * @brief External Interrupt/Event Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t IMR;
+ __IO uint32_t EMR;
+ __IO uint32_t RTSR;
+ __IO uint32_t FTSR;
+ __IO uint32_t SWIER;
+ __IO uint32_t PR;
+} EXTI_TypeDef;
+
+/**
+ * @brief FLASH Registers
+ */
+
+typedef struct
+{
+ __IO uint32_t ACR;
+ __IO uint32_t KEYR;
+ __IO uint32_t OPTKEYR;
+ __IO uint32_t SR;
+ __IO uint32_t CR;
+ __IO uint32_t AR;
+ __IO uint32_t RESERVED;
+ __IO uint32_t OBR;
+ __IO uint32_t WRPR;
+} FLASH_TypeDef;
+
+/**
+ * @brief Option Bytes Registers
+ */
+
+typedef struct
+{
+ __IO uint16_t RDP;
+ __IO uint16_t USER;
+ __IO uint16_t Data0;
+ __IO uint16_t Data1;
+ __IO uint16_t WRP0;
+ __IO uint16_t WRP1;
+ __IO uint16_t WRP2;
+ __IO uint16_t WRP3;
+} OB_TypeDef;
+
+/**
+ * @brief General Purpose I/O
+ */
+
+typedef struct
+{
+ __IO uint32_t CRL;
+ __IO uint32_t CRH;
+ __IO uint32_t IDR;
+ __IO uint32_t ODR;
+ __IO uint32_t BSRR;
+ __IO uint32_t BRR;
+ __IO uint32_t LCKR;
+} GPIO_TypeDef;
+
+/**
+ * @brief Alternate Function I/O
+ */
+
+typedef struct
+{
+ __IO uint32_t EVCR;
+ __IO uint32_t MAPR;
+ __IO uint32_t EXTICR[4];
+ uint32_t RESERVED0;
+ __IO uint32_t MAPR2;
+} AFIO_TypeDef;
+/**
+ * @brief Inter Integrated Circuit Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t CR1;
+ __IO uint32_t CR2;
+ __IO uint32_t OAR1;
+ __IO uint32_t OAR2;
+ __IO uint32_t DR;
+ __IO uint32_t SR1;
+ __IO uint32_t SR2;
+ __IO uint32_t CCR;
+ __IO uint32_t TRISE;
+} I2C_TypeDef;
+
+/**
+ * @brief Independent WATCHDOG
+ */
+
+typedef struct
+{
+ __IO uint32_t KR; /*!< Key register, Address offset: 0x00 */
+ __IO uint32_t PR; /*!< Prescaler register, Address offset: 0x04 */
+ __IO uint32_t RLR; /*!< Reload register, Address offset: 0x08 */
+ __IO uint32_t SR; /*!< Status register, Address offset: 0x0C */
+} IWDG_TypeDef;
+
+/**
+ * @brief Power Control
+ */
+
+typedef struct
+{
+ __IO uint32_t CR;
+ __IO uint32_t CSR;
+} PWR_TypeDef;
+
+/**
+ * @brief Reset and Clock Control
+ */
+
+typedef struct
+{
+ __IO uint32_t CR;
+ __IO uint32_t CFGR;
+ __IO uint32_t CIR;
+ __IO uint32_t APB2RSTR;
+ __IO uint32_t APB1RSTR;
+ __IO uint32_t AHBENR;
+ __IO uint32_t APB2ENR;
+ __IO uint32_t APB1ENR;
+ __IO uint32_t BDCR;
+ __IO uint32_t CSR;
+
+ __IO uint32_t AHBRSTR;
+ __IO uint32_t CFGR2;
+
+} RCC_TypeDef;
+
+/**
+ * @brief Real-Time Clock
+ */
+
+typedef struct
+{
+ __IO uint32_t CRH;
+ __IO uint32_t CRL;
+ __IO uint32_t PRLH;
+ __IO uint32_t PRLL;
+ __IO uint32_t DIVH;
+ __IO uint32_t DIVL;
+ __IO uint32_t CNTH;
+ __IO uint32_t CNTL;
+ __IO uint32_t ALRH;
+ __IO uint32_t ALRL;
+} RTC_TypeDef;
+
+/**
+ * @brief SD host Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t POWER;
+ __IO uint32_t CLKCR;
+ __IO uint32_t ARG;
+ __IO uint32_t CMD;
+ __I uint32_t RESPCMD;
+ __I uint32_t RESP1;
+ __I uint32_t RESP2;
+ __I uint32_t RESP3;
+ __I uint32_t RESP4;
+ __IO uint32_t DTIMER;
+ __IO uint32_t DLEN;
+ __IO uint32_t DCTRL;
+ __I uint32_t DCOUNT;
+ __I uint32_t STA;
+ __IO uint32_t ICR;
+ __IO uint32_t MASK;
+ uint32_t RESERVED0[2];
+ __I uint32_t FIFOCNT;
+ uint32_t RESERVED1[13];
+ __IO uint32_t FIFO;
+} SDIO_TypeDef;
+
+/**
+ * @brief Serial Peripheral Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t CR1;
+ __IO uint32_t CR2;
+ __IO uint32_t SR;
+ __IO uint32_t DR;
+ __IO uint32_t CRCPR;
+ __IO uint32_t RXCRCR;
+ __IO uint32_t TXCRCR;
+ __IO uint32_t I2SCFGR;
+ __IO uint32_t I2SPR;
+} SPI_TypeDef;
+
+/**
+ * @brief TIM Timers
+ */
+typedef struct
+{
+ __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
+ __IO uint32_t SMCR; /*!< TIM slave Mode Control register, Address offset: 0x08 */
+ __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
+ __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
+ __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
+ __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
+ __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
+ __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
+ __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
+ __IO uint32_t PSC; /*!< TIM prescaler register, Address offset: 0x28 */
+ __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
+ __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */
+ __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
+ __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
+ __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
+ __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
+ __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
+ __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
+ __IO uint32_t DMAR; /*!< TIM DMA address for full transfer register, Address offset: 0x4C */
+ __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */
+}TIM_TypeDef;
+
+
+/**
+ * @brief Universal Synchronous Asynchronous Receiver Transmitter
+ */
+
+typedef struct
+{
+ __IO uint32_t SR; /*!< USART Status register, Address offset: 0x00 */
+ __IO uint32_t DR; /*!< USART Data register, Address offset: 0x04 */
+ __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x08 */
+ __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x0C */
+ __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x10 */
+ __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x14 */
+ __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x18 */
+} USART_TypeDef;
+
+
+/**
+ * @brief __USB_OTG_Core_register
+ */
+
+typedef struct
+{
+ __IO uint32_t GOTGCTL; /*!< USB_OTG Control and Status Register Address offset: 000h */
+ __IO uint32_t GOTGINT; /*!< USB_OTG Interrupt Register Address offset: 004h */
+ __IO uint32_t GAHBCFG; /*!< Core AHB Configuration Register Address offset: 008h */
+ __IO uint32_t GUSBCFG; /*!< Core USB Configuration Register Address offset: 00Ch */
+ __IO uint32_t GRSTCTL; /*!< Core Reset Register Address offset: 010h */
+ __IO uint32_t GINTSTS; /*!< Core Interrupt Register Address offset: 014h */
+ __IO uint32_t GINTMSK; /*!< Core Interrupt Mask Register Address offset: 018h */
+ __IO uint32_t GRXSTSR; /*!< Receive Sts Q Read Register Address offset: 01Ch */
+ __IO uint32_t GRXSTSP; /*!< Receive Sts Q Read & POP Register Address offset: 020h */
+ __IO uint32_t GRXFSIZ; /*!< Receive FIFO Size Register Address offset: 024h */
+ __IO uint32_t DIEPTXF0_HNPTXFSIZ; /*!< EP0 / Non Periodic Tx FIFO Size Register Address offset: 028h */
+ __IO uint32_t HNPTXSTS; /*!< Non Periodic Tx FIFO/Queue Sts reg Address offset: 02Ch */
+ uint32_t Reserved30[2]; /*!< Reserved 030h*/
+ __IO uint32_t GCCFG; /*!< General Purpose IO Register Address offset: 038h */
+ __IO uint32_t CID; /*!< User ID Register Address offset: 03Ch */
+ uint32_t Reserved40[48]; /*!< Reserved 040h-0FFh */
+ __IO uint32_t HPTXFSIZ; /*!< Host Periodic Tx FIFO Size Reg Address offset: 100h */
+ __IO uint32_t DIEPTXF[0x0F]; /*!< dev Periodic Transmit FIFO Address offset: 0x104 */
+} USB_OTG_GlobalTypeDef;
+
+/**
+ * @brief __device_Registers
+ */
+
+typedef struct
+{
+ __IO uint32_t DCFG; /*!< dev Configuration Register Address offset: 800h*/
+ __IO uint32_t DCTL; /*!< dev Control Register Address offset: 804h*/
+ __IO uint32_t DSTS; /*!< dev Status Register (RO) Address offset: 808h*/
+ uint32_t Reserved0C; /*!< Reserved 80Ch*/
+ __IO uint32_t DIEPMSK; /*!< dev IN Endpoint Mask Address offset: 810h*/
+ __IO uint32_t DOEPMSK; /*!< dev OUT Endpoint Mask Address offset: 814h*/
+ __IO uint32_t DAINT; /*!< dev All Endpoints Itr Reg Address offset: 818h*/
+ __IO uint32_t DAINTMSK; /*!< dev All Endpoints Itr Mask Address offset: 81Ch*/
+ uint32_t Reserved20; /*!< Reserved 820h*/
+ uint32_t Reserved9; /*!< Reserved 824h*/
+ __IO uint32_t DVBUSDIS; /*!< dev VBUS discharge Register Address offset: 828h*/
+ __IO uint32_t DVBUSPULSE; /*!< dev VBUS Pulse Register Address offset: 82Ch*/
+ __IO uint32_t DTHRCTL; /*!< dev thr Address offset: 830h*/
+ __IO uint32_t DIEPEMPMSK; /*!< dev empty msk Address offset: 834h*/
+ __IO uint32_t DEACHINT; /*!< dedicated EP interrupt Address offset: 838h*/
+ __IO uint32_t DEACHMSK; /*!< dedicated EP msk Address offset: 83Ch*/
+ uint32_t Reserved40; /*!< dedicated EP mask Address offset: 840h*/
+ __IO uint32_t DINEP1MSK; /*!< dedicated EP mask Address offset: 844h*/
+ uint32_t Reserved44[15]; /*!< Reserved 844-87Ch*/
+ __IO uint32_t DOUTEP1MSK; /*!< dedicated EP msk Address offset: 884h*/
+} USB_OTG_DeviceTypeDef;
+
+/**
+ * @brief __IN_Endpoint-Specific_Register
+ */
+
+typedef struct
+{
+ __IO uint32_t DIEPCTL; /*!< dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h*/
+ uint32_t Reserved04; /*!< Reserved 900h + (ep_num * 20h) + 04h*/
+ __IO uint32_t DIEPINT; /*!< dev IN Endpoint Itr Reg 900h + (ep_num * 20h) + 08h*/
+ uint32_t Reserved0C; /*!< Reserved 900h + (ep_num * 20h) + 0Ch*/
+ __IO uint32_t DIEPTSIZ; /*!< IN Endpoint Txfer Size 900h + (ep_num * 20h) + 10h*/
+ __IO uint32_t DIEPDMA; /*!< IN Endpoint DMA Address Reg 900h + (ep_num * 20h) + 14h*/
+ __IO uint32_t DTXFSTS; /*!< IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h*/
+ uint32_t Reserved18; /*!< Reserved 900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch*/
+} USB_OTG_INEndpointTypeDef;
+
+/**
+ * @brief __OUT_Endpoint-Specific_Registers
+ */
+
+typedef struct
+{
+ __IO uint32_t DOEPCTL; /*!< dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h*/
+ uint32_t Reserved04; /*!< Reserved B00h + (ep_num * 20h) + 04h*/
+ __IO uint32_t DOEPINT; /*!< dev OUT Endpoint Itr Reg B00h + (ep_num * 20h) + 08h*/
+ uint32_t Reserved0C; /*!< Reserved B00h + (ep_num * 20h) + 0Ch*/
+ __IO uint32_t DOEPTSIZ; /*!< dev OUT Endpoint Txfer Size B00h + (ep_num * 20h) + 10h*/
+ __IO uint32_t DOEPDMA; /*!< dev OUT Endpoint DMA Address B00h + (ep_num * 20h) + 14h*/
+ uint32_t Reserved18[2]; /*!< Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch*/
+} USB_OTG_OUTEndpointTypeDef;
+
+/**
+ * @brief __Host_Mode_Register_Structures
+ */
+
+typedef struct
+{
+ __IO uint32_t HCFG; /*!< Host Configuration Register 400h*/
+ __IO uint32_t HFIR; /*!< Host Frame Interval Register 404h*/
+ __IO uint32_t HFNUM; /*!< Host Frame Nbr/Frame Remaining 408h*/
+ uint32_t Reserved40C; /*!< Reserved 40Ch*/
+ __IO uint32_t HPTXSTS; /*!< Host Periodic Tx FIFO/ Queue Status 410h*/
+ __IO uint32_t HAINT; /*!< Host All Channels Interrupt Register 414h*/
+ __IO uint32_t HAINTMSK; /*!< Host All Channels Interrupt Mask 418h*/
+} USB_OTG_HostTypeDef;
+
+/**
+ * @brief __Host_Channel_Specific_Registers
+ */
+
+typedef struct
+{
+ __IO uint32_t HCCHAR;
+ __IO uint32_t HCSPLT;
+ __IO uint32_t HCINT;
+ __IO uint32_t HCINTMSK;
+ __IO uint32_t HCTSIZ;
+ __IO uint32_t HCDMA;
+ uint32_t Reserved[2];
+} USB_OTG_HostChannelTypeDef;
+
+/**
+ * @brief Window WATCHDOG
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
+ __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
+ __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
+} WWDG_TypeDef;
+
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_memory_map
+ * @{
+ */
+
+
+#define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH base address in the alias region */
+#define FLASH_BANK1_END ((uint32_t)0x0803FFFF) /*!< FLASH END address of bank1 */
+#define SRAM_BASE ((uint32_t)0x20000000) /*!< SRAM base address in the alias region */
+#define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */
+
+#define SRAM_BB_BASE ((uint32_t)0x22000000) /*!< SRAM base address in the bit-band region */
+#define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */
+
+
+/*!< Peripheral memory map */
+#define APB1PERIPH_BASE PERIPH_BASE
+#define APB2PERIPH_BASE (PERIPH_BASE + 0x10000)
+#define AHBPERIPH_BASE (PERIPH_BASE + 0x20000)
+
+#define TIM2_BASE (APB1PERIPH_BASE + 0x0000)
+#define TIM3_BASE (APB1PERIPH_BASE + 0x0400)
+#define TIM4_BASE (APB1PERIPH_BASE + 0x0800)
+#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00)
+#define TIM6_BASE (APB1PERIPH_BASE + 0x1000)
+#define TIM7_BASE (APB1PERIPH_BASE + 0x1400)
+#define RTC_BASE (APB1PERIPH_BASE + 0x2800)
+#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00)
+#define IWDG_BASE (APB1PERIPH_BASE + 0x3000)
+#define SPI2_BASE (APB1PERIPH_BASE + 0x3800)
+#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00)
+#define USART2_BASE (APB1PERIPH_BASE + 0x4400)
+#define USART3_BASE (APB1PERIPH_BASE + 0x4800)
+#define UART4_BASE (APB1PERIPH_BASE + 0x4C00)
+#define UART5_BASE (APB1PERIPH_BASE + 0x5000)
+#define I2C1_BASE (APB1PERIPH_BASE + 0x5400)
+#define I2C2_BASE (APB1PERIPH_BASE + 0x5800)
+#define CAN1_BASE (APB1PERIPH_BASE + 0x6400)
+#define CAN2_BASE (APB1PERIPH_BASE + 0x6800)
+#define BKP_BASE (APB1PERIPH_BASE + 0x6C00)
+#define PWR_BASE (APB1PERIPH_BASE + 0x7000)
+#define DAC_BASE (APB1PERIPH_BASE + 0x7400)
+#define AFIO_BASE (APB2PERIPH_BASE + 0x0000)
+#define EXTI_BASE (APB2PERIPH_BASE + 0x0400)
+#define GPIOA_BASE (APB2PERIPH_BASE + 0x0800)
+#define GPIOB_BASE (APB2PERIPH_BASE + 0x0C00)
+#define GPIOC_BASE (APB2PERIPH_BASE + 0x1000)
+#define GPIOD_BASE (APB2PERIPH_BASE + 0x1400)
+#define GPIOE_BASE (APB2PERIPH_BASE + 0x1800)
+#define ADC1_BASE (APB2PERIPH_BASE + 0x2400)
+#define ADC2_BASE (APB2PERIPH_BASE + 0x2800)
+#define TIM1_BASE (APB2PERIPH_BASE + 0x2C00)
+#define SPI1_BASE (APB2PERIPH_BASE + 0x3000)
+#define USART1_BASE (APB2PERIPH_BASE + 0x3800)
+
+#define SDIO_BASE (PERIPH_BASE + 0x18000)
+
+#define DMA1_BASE (AHBPERIPH_BASE + 0x0000)
+#define DMA1_Channel1_BASE (AHBPERIPH_BASE + 0x0008)
+#define DMA1_Channel2_BASE (AHBPERIPH_BASE + 0x001C)
+#define DMA1_Channel3_BASE (AHBPERIPH_BASE + 0x0030)
+#define DMA1_Channel4_BASE (AHBPERIPH_BASE + 0x0044)
+#define DMA1_Channel5_BASE (AHBPERIPH_BASE + 0x0058)
+#define DMA1_Channel6_BASE (AHBPERIPH_BASE + 0x006C)
+#define DMA1_Channel7_BASE (AHBPERIPH_BASE + 0x0080)
+#define DMA2_BASE (AHBPERIPH_BASE + 0x0400)
+#define DMA2_Channel1_BASE (AHBPERIPH_BASE + 0x0408)
+#define DMA2_Channel2_BASE (AHBPERIPH_BASE + 0x041C)
+#define DMA2_Channel3_BASE (AHBPERIPH_BASE + 0x0430)
+#define DMA2_Channel4_BASE (AHBPERIPH_BASE + 0x0444)
+#define DMA2_Channel5_BASE (AHBPERIPH_BASE + 0x0458)
+#define RCC_BASE (AHBPERIPH_BASE + 0x1000)
+#define CRC_BASE (AHBPERIPH_BASE + 0x3000)
+
+#define FLASH_R_BASE (AHBPERIPH_BASE + 0x2000) /*!< Flash registers base address */
+#define FLASHSIZE_BASE ((uint32_t)0x1FFFF7E0) /*!< FLASH Size register base address */
+#define UID_BASE ((uint32_t)0x1FFFF7E8) /*!< Unique device ID register base address */
+#define OB_BASE ((uint32_t)0x1FFFF800) /*!< Flash Option Bytes base address */
+
+#define ETH_BASE (AHBPERIPH_BASE + 0x8000)
+#define ETH_MAC_BASE (ETH_BASE)
+#define ETH_MMC_BASE (ETH_BASE + 0x0100)
+#define ETH_PTP_BASE (ETH_BASE + 0x0700)
+#define ETH_DMA_BASE (ETH_BASE + 0x1000)
+
+
+#define DBGMCU_BASE ((uint32_t)0xE0042000) /*!< Debug MCU registers base address */
+
+
+/*!< USB registers base address */
+#define USB_OTG_FS_PERIPH_BASE ((uint32_t )0x50000000)
+
+#define USB_OTG_GLOBAL_BASE ((uint32_t )0x00000000)
+#define USB_OTG_DEVICE_BASE ((uint32_t )0x00000800)
+#define USB_OTG_IN_ENDPOINT_BASE ((uint32_t )0x00000900)
+#define USB_OTG_OUT_ENDPOINT_BASE ((uint32_t )0x00000B00)
+#define USB_OTG_EP_REG_SIZE ((uint32_t )0x00000020)
+#define USB_OTG_HOST_BASE ((uint32_t )0x00000400)
+#define USB_OTG_HOST_PORT_BASE ((uint32_t )0x00000440)
+#define USB_OTG_HOST_CHANNEL_BASE ((uint32_t )0x00000500)
+#define USB_OTG_HOST_CHANNEL_SIZE ((uint32_t )0x00000020)
+#define USB_OTG_PCGCCTL_BASE ((uint32_t )0x00000E00)
+#define USB_OTG_FIFO_BASE ((uint32_t )0x00001000)
+#define USB_OTG_FIFO_SIZE ((uint32_t )0x00001000)
+
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_declaration
+ * @{
+ */
+
+#define TIM2 ((TIM_TypeDef *) TIM2_BASE)
+#define TIM3 ((TIM_TypeDef *) TIM3_BASE)
+#define TIM4 ((TIM_TypeDef *) TIM4_BASE)
+#define TIM5 ((TIM_TypeDef *) TIM5_BASE)
+#define TIM6 ((TIM_TypeDef *) TIM6_BASE)
+#define TIM7 ((TIM_TypeDef *) TIM7_BASE)
+#define RTC ((RTC_TypeDef *) RTC_BASE)
+#define WWDG ((WWDG_TypeDef *) WWDG_BASE)
+#define IWDG ((IWDG_TypeDef *) IWDG_BASE)
+#define SPI2 ((SPI_TypeDef *) SPI2_BASE)
+#define SPI3 ((SPI_TypeDef *) SPI3_BASE)
+#define USART2 ((USART_TypeDef *) USART2_BASE)
+#define USART3 ((USART_TypeDef *) USART3_BASE)
+#define UART4 ((USART_TypeDef *) UART4_BASE)
+#define UART5 ((USART_TypeDef *) UART5_BASE)
+#define I2C1 ((I2C_TypeDef *) I2C1_BASE)
+#define I2C2 ((I2C_TypeDef *) I2C2_BASE)
+#define CAN1 ((CAN_TypeDef *) CAN1_BASE)
+#define CAN2 ((CAN_TypeDef *) CAN2_BASE)
+#define BKP ((BKP_TypeDef *) BKP_BASE)
+#define PWR ((PWR_TypeDef *) PWR_BASE)
+#define DAC ((DAC_TypeDef *) DAC_BASE)
+#define AFIO ((AFIO_TypeDef *) AFIO_BASE)
+#define EXTI ((EXTI_TypeDef *) EXTI_BASE)
+#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
+#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
+#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
+#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
+#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
+#define ADC1 ((ADC_TypeDef *) ADC1_BASE)
+#define ADC2 ((ADC_TypeDef *) ADC2_BASE)
+#define ADC12_COMMON ((ADC_Common_TypeDef *) ADC1_BASE)
+#define TIM1 ((TIM_TypeDef *) TIM1_BASE)
+#define SPI1 ((SPI_TypeDef *) SPI1_BASE)
+#define USART1 ((USART_TypeDef *) USART1_BASE)
+#define SDIO ((SDIO_TypeDef *) SDIO_BASE)
+#define DMA1 ((DMA_TypeDef *) DMA1_BASE)
+#define DMA2 ((DMA_TypeDef *) DMA2_BASE)
+#define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
+#define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
+#define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
+#define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
+#define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
+#define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
+#define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
+#define DMA2_Channel1 ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE)
+#define DMA2_Channel2 ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE)
+#define DMA2_Channel3 ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE)
+#define DMA2_Channel4 ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE)
+#define DMA2_Channel5 ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE)
+#define RCC ((RCC_TypeDef *) RCC_BASE)
+#define CRC ((CRC_TypeDef *) CRC_BASE)
+#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
+#define OB ((OB_TypeDef *) OB_BASE)
+#define ETH ((ETH_TypeDef *) ETH_BASE)
+#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
+
+#define USB_OTG_FS ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE)
+
+/**
+ * @}
+ */
+
+/** @addtogroup Exported_constants
+ * @{
+ */
+
+ /** @addtogroup Peripheral_Registers_Bits_Definition
+ * @{
+ */
+
+/******************************************************************************/
+/* Peripheral Registers_Bits_Definition */
+/******************************************************************************/
+
+/******************************************************************************/
+/* */
+/* CRC calculation unit (CRC) */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for CRC_DR register *********************/
+#define CRC_DR_DR_Pos (0U)
+#define CRC_DR_DR_Msk (0xFFFFFFFFU << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */
+#define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */
+
+/******************* Bit definition for CRC_IDR register ********************/
+#define CRC_IDR_IDR_Pos (0U)
+#define CRC_IDR_IDR_Msk (0xFFU << CRC_IDR_IDR_Pos) /*!< 0x000000FF */
+#define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 8-bit data register bits */
+
+/******************** Bit definition for CRC_CR register ********************/
+#define CRC_CR_RESET_Pos (0U)
+#define CRC_CR_RESET_Msk (0x1U << CRC_CR_RESET_Pos) /*!< 0x00000001 */
+#define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET bit */
+
+/******************************************************************************/
+/* */
+/* Power Control */
+/* */
+/******************************************************************************/
+
+/******************** Bit definition for PWR_CR register ********************/
+#define PWR_CR_LPDS_Pos (0U)
+#define PWR_CR_LPDS_Msk (0x1U << PWR_CR_LPDS_Pos) /*!< 0x00000001 */
+#define PWR_CR_LPDS PWR_CR_LPDS_Msk /*!< Low-Power Deepsleep */
+#define PWR_CR_PDDS_Pos (1U)
+#define PWR_CR_PDDS_Msk (0x1U << PWR_CR_PDDS_Pos) /*!< 0x00000002 */
+#define PWR_CR_PDDS PWR_CR_PDDS_Msk /*!< Power Down Deepsleep */
+#define PWR_CR_CWUF_Pos (2U)
+#define PWR_CR_CWUF_Msk (0x1U << PWR_CR_CWUF_Pos) /*!< 0x00000004 */
+#define PWR_CR_CWUF PWR_CR_CWUF_Msk /*!< Clear Wakeup Flag */
+#define PWR_CR_CSBF_Pos (3U)
+#define PWR_CR_CSBF_Msk (0x1U << PWR_CR_CSBF_Pos) /*!< 0x00000008 */
+#define PWR_CR_CSBF PWR_CR_CSBF_Msk /*!< Clear Standby Flag */
+#define PWR_CR_PVDE_Pos (4U)
+#define PWR_CR_PVDE_Msk (0x1U << PWR_CR_PVDE_Pos) /*!< 0x00000010 */
+#define PWR_CR_PVDE PWR_CR_PVDE_Msk /*!< Power Voltage Detector Enable */
+
+#define PWR_CR_PLS_Pos (5U)
+#define PWR_CR_PLS_Msk (0x7U << PWR_CR_PLS_Pos) /*!< 0x000000E0 */
+#define PWR_CR_PLS PWR_CR_PLS_Msk /*!< PLS[2:0] bits (PVD Level Selection) */
+#define PWR_CR_PLS_0 (0x1U << PWR_CR_PLS_Pos) /*!< 0x00000020 */
+#define PWR_CR_PLS_1 (0x2U << PWR_CR_PLS_Pos) /*!< 0x00000040 */
+#define PWR_CR_PLS_2 (0x4U << PWR_CR_PLS_Pos) /*!< 0x00000080 */
+
+/*!< PVD level configuration */
+#define PWR_CR_PLS_2V2 ((uint32_t)0x00000000) /*!< PVD level 2.2V */
+#define PWR_CR_PLS_2V3 ((uint32_t)0x00000020) /*!< PVD level 2.3V */
+#define PWR_CR_PLS_2V4 ((uint32_t)0x00000040) /*!< PVD level 2.4V */
+#define PWR_CR_PLS_2V5 ((uint32_t)0x00000060) /*!< PVD level 2.5V */
+#define PWR_CR_PLS_2V6 ((uint32_t)0x00000080) /*!< PVD level 2.6V */
+#define PWR_CR_PLS_2V7 ((uint32_t)0x000000A0) /*!< PVD level 2.7V */
+#define PWR_CR_PLS_2V8 ((uint32_t)0x000000C0) /*!< PVD level 2.8V */
+#define PWR_CR_PLS_2V9 ((uint32_t)0x000000E0) /*!< PVD level 2.9V */
+
+#define PWR_CR_DBP_Pos (8U)
+#define PWR_CR_DBP_Msk (0x1U << PWR_CR_DBP_Pos) /*!< 0x00000100 */
+#define PWR_CR_DBP PWR_CR_DBP_Msk /*!< Disable Backup Domain write protection */
+
+
+/******************* Bit definition for PWR_CSR register ********************/
+#define PWR_CSR_WUF_Pos (0U)
+#define PWR_CSR_WUF_Msk (0x1U << PWR_CSR_WUF_Pos) /*!< 0x00000001 */
+#define PWR_CSR_WUF PWR_CSR_WUF_Msk /*!< Wakeup Flag */
+#define PWR_CSR_SBF_Pos (1U)
+#define PWR_CSR_SBF_Msk (0x1U << PWR_CSR_SBF_Pos) /*!< 0x00000002 */
+#define PWR_CSR_SBF PWR_CSR_SBF_Msk /*!< Standby Flag */
+#define PWR_CSR_PVDO_Pos (2U)
+#define PWR_CSR_PVDO_Msk (0x1U << PWR_CSR_PVDO_Pos) /*!< 0x00000004 */
+#define PWR_CSR_PVDO PWR_CSR_PVDO_Msk /*!< PVD Output */
+#define PWR_CSR_EWUP_Pos (8U)
+#define PWR_CSR_EWUP_Msk (0x1U << PWR_CSR_EWUP_Pos) /*!< 0x00000100 */
+#define PWR_CSR_EWUP PWR_CSR_EWUP_Msk /*!< Enable WKUP pin */
+
+/******************************************************************************/
+/* */
+/* Backup registers */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for BKP_DR1 register ********************/
+#define BKP_DR1_D_Pos (0U)
+#define BKP_DR1_D_Msk (0xFFFFU << BKP_DR1_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR1_D BKP_DR1_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR2 register ********************/
+#define BKP_DR2_D_Pos (0U)
+#define BKP_DR2_D_Msk (0xFFFFU << BKP_DR2_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR2_D BKP_DR2_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR3 register ********************/
+#define BKP_DR3_D_Pos (0U)
+#define BKP_DR3_D_Msk (0xFFFFU << BKP_DR3_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR3_D BKP_DR3_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR4 register ********************/
+#define BKP_DR4_D_Pos (0U)
+#define BKP_DR4_D_Msk (0xFFFFU << BKP_DR4_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR4_D BKP_DR4_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR5 register ********************/
+#define BKP_DR5_D_Pos (0U)
+#define BKP_DR5_D_Msk (0xFFFFU << BKP_DR5_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR5_D BKP_DR5_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR6 register ********************/
+#define BKP_DR6_D_Pos (0U)
+#define BKP_DR6_D_Msk (0xFFFFU << BKP_DR6_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR6_D BKP_DR6_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR7 register ********************/
+#define BKP_DR7_D_Pos (0U)
+#define BKP_DR7_D_Msk (0xFFFFU << BKP_DR7_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR7_D BKP_DR7_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR8 register ********************/
+#define BKP_DR8_D_Pos (0U)
+#define BKP_DR8_D_Msk (0xFFFFU << BKP_DR8_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR8_D BKP_DR8_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR9 register ********************/
+#define BKP_DR9_D_Pos (0U)
+#define BKP_DR9_D_Msk (0xFFFFU << BKP_DR9_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR9_D BKP_DR9_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR10 register *******************/
+#define BKP_DR10_D_Pos (0U)
+#define BKP_DR10_D_Msk (0xFFFFU << BKP_DR10_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR10_D BKP_DR10_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR11 register *******************/
+#define BKP_DR11_D_Pos (0U)
+#define BKP_DR11_D_Msk (0xFFFFU << BKP_DR11_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR11_D BKP_DR11_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR12 register *******************/
+#define BKP_DR12_D_Pos (0U)
+#define BKP_DR12_D_Msk (0xFFFFU << BKP_DR12_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR12_D BKP_DR12_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR13 register *******************/
+#define BKP_DR13_D_Pos (0U)
+#define BKP_DR13_D_Msk (0xFFFFU << BKP_DR13_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR13_D BKP_DR13_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR14 register *******************/
+#define BKP_DR14_D_Pos (0U)
+#define BKP_DR14_D_Msk (0xFFFFU << BKP_DR14_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR14_D BKP_DR14_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR15 register *******************/
+#define BKP_DR15_D_Pos (0U)
+#define BKP_DR15_D_Msk (0xFFFFU << BKP_DR15_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR15_D BKP_DR15_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR16 register *******************/
+#define BKP_DR16_D_Pos (0U)
+#define BKP_DR16_D_Msk (0xFFFFU << BKP_DR16_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR16_D BKP_DR16_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR17 register *******************/
+#define BKP_DR17_D_Pos (0U)
+#define BKP_DR17_D_Msk (0xFFFFU << BKP_DR17_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR17_D BKP_DR17_D_Msk /*!< Backup data */
+
+/****************** Bit definition for BKP_DR18 register ********************/
+#define BKP_DR18_D_Pos (0U)
+#define BKP_DR18_D_Msk (0xFFFFU << BKP_DR18_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR18_D BKP_DR18_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR19 register *******************/
+#define BKP_DR19_D_Pos (0U)
+#define BKP_DR19_D_Msk (0xFFFFU << BKP_DR19_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR19_D BKP_DR19_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR20 register *******************/
+#define BKP_DR20_D_Pos (0U)
+#define BKP_DR20_D_Msk (0xFFFFU << BKP_DR20_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR20_D BKP_DR20_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR21 register *******************/
+#define BKP_DR21_D_Pos (0U)
+#define BKP_DR21_D_Msk (0xFFFFU << BKP_DR21_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR21_D BKP_DR21_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR22 register *******************/
+#define BKP_DR22_D_Pos (0U)
+#define BKP_DR22_D_Msk (0xFFFFU << BKP_DR22_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR22_D BKP_DR22_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR23 register *******************/
+#define BKP_DR23_D_Pos (0U)
+#define BKP_DR23_D_Msk (0xFFFFU << BKP_DR23_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR23_D BKP_DR23_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR24 register *******************/
+#define BKP_DR24_D_Pos (0U)
+#define BKP_DR24_D_Msk (0xFFFFU << BKP_DR24_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR24_D BKP_DR24_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR25 register *******************/
+#define BKP_DR25_D_Pos (0U)
+#define BKP_DR25_D_Msk (0xFFFFU << BKP_DR25_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR25_D BKP_DR25_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR26 register *******************/
+#define BKP_DR26_D_Pos (0U)
+#define BKP_DR26_D_Msk (0xFFFFU << BKP_DR26_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR26_D BKP_DR26_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR27 register *******************/
+#define BKP_DR27_D_Pos (0U)
+#define BKP_DR27_D_Msk (0xFFFFU << BKP_DR27_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR27_D BKP_DR27_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR28 register *******************/
+#define BKP_DR28_D_Pos (0U)
+#define BKP_DR28_D_Msk (0xFFFFU << BKP_DR28_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR28_D BKP_DR28_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR29 register *******************/
+#define BKP_DR29_D_Pos (0U)
+#define BKP_DR29_D_Msk (0xFFFFU << BKP_DR29_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR29_D BKP_DR29_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR30 register *******************/
+#define BKP_DR30_D_Pos (0U)
+#define BKP_DR30_D_Msk (0xFFFFU << BKP_DR30_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR30_D BKP_DR30_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR31 register *******************/
+#define BKP_DR31_D_Pos (0U)
+#define BKP_DR31_D_Msk (0xFFFFU << BKP_DR31_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR31_D BKP_DR31_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR32 register *******************/
+#define BKP_DR32_D_Pos (0U)
+#define BKP_DR32_D_Msk (0xFFFFU << BKP_DR32_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR32_D BKP_DR32_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR33 register *******************/
+#define BKP_DR33_D_Pos (0U)
+#define BKP_DR33_D_Msk (0xFFFFU << BKP_DR33_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR33_D BKP_DR33_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR34 register *******************/
+#define BKP_DR34_D_Pos (0U)
+#define BKP_DR34_D_Msk (0xFFFFU << BKP_DR34_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR34_D BKP_DR34_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR35 register *******************/
+#define BKP_DR35_D_Pos (0U)
+#define BKP_DR35_D_Msk (0xFFFFU << BKP_DR35_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR35_D BKP_DR35_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR36 register *******************/
+#define BKP_DR36_D_Pos (0U)
+#define BKP_DR36_D_Msk (0xFFFFU << BKP_DR36_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR36_D BKP_DR36_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR37 register *******************/
+#define BKP_DR37_D_Pos (0U)
+#define BKP_DR37_D_Msk (0xFFFFU << BKP_DR37_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR37_D BKP_DR37_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR38 register *******************/
+#define BKP_DR38_D_Pos (0U)
+#define BKP_DR38_D_Msk (0xFFFFU << BKP_DR38_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR38_D BKP_DR38_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR39 register *******************/
+#define BKP_DR39_D_Pos (0U)
+#define BKP_DR39_D_Msk (0xFFFFU << BKP_DR39_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR39_D BKP_DR39_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR40 register *******************/
+#define BKP_DR40_D_Pos (0U)
+#define BKP_DR40_D_Msk (0xFFFFU << BKP_DR40_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR40_D BKP_DR40_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR41 register *******************/
+#define BKP_DR41_D_Pos (0U)
+#define BKP_DR41_D_Msk (0xFFFFU << BKP_DR41_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR41_D BKP_DR41_D_Msk /*!< Backup data */
+
+/******************* Bit definition for BKP_DR42 register *******************/
+#define BKP_DR42_D_Pos (0U)
+#define BKP_DR42_D_Msk (0xFFFFU << BKP_DR42_D_Pos) /*!< 0x0000FFFF */
+#define BKP_DR42_D BKP_DR42_D_Msk /*!< Backup data */
+
+#define RTC_BKP_NUMBER 42
+
+/****************** Bit definition for BKP_RTCCR register *******************/
+#define BKP_RTCCR_CAL_Pos (0U)
+#define BKP_RTCCR_CAL_Msk (0x7FU << BKP_RTCCR_CAL_Pos) /*!< 0x0000007F */
+#define BKP_RTCCR_CAL BKP_RTCCR_CAL_Msk /*!< Calibration value */
+#define BKP_RTCCR_CCO_Pos (7U)
+#define BKP_RTCCR_CCO_Msk (0x1U << BKP_RTCCR_CCO_Pos) /*!< 0x00000080 */
+#define BKP_RTCCR_CCO BKP_RTCCR_CCO_Msk /*!< Calibration Clock Output */
+#define BKP_RTCCR_ASOE_Pos (8U)
+#define BKP_RTCCR_ASOE_Msk (0x1U << BKP_RTCCR_ASOE_Pos) /*!< 0x00000100 */
+#define BKP_RTCCR_ASOE BKP_RTCCR_ASOE_Msk /*!< Alarm or Second Output Enable */
+#define BKP_RTCCR_ASOS_Pos (9U)
+#define BKP_RTCCR_ASOS_Msk (0x1U << BKP_RTCCR_ASOS_Pos) /*!< 0x00000200 */
+#define BKP_RTCCR_ASOS BKP_RTCCR_ASOS_Msk /*!< Alarm or Second Output Selection */
+
+/******************** Bit definition for BKP_CR register ********************/
+#define BKP_CR_TPE_Pos (0U)
+#define BKP_CR_TPE_Msk (0x1U << BKP_CR_TPE_Pos) /*!< 0x00000001 */
+#define BKP_CR_TPE BKP_CR_TPE_Msk /*!< TAMPER pin enable */
+#define BKP_CR_TPAL_Pos (1U)
+#define BKP_CR_TPAL_Msk (0x1U << BKP_CR_TPAL_Pos) /*!< 0x00000002 */
+#define BKP_CR_TPAL BKP_CR_TPAL_Msk /*!< TAMPER pin active level */
+
+/******************* Bit definition for BKP_CSR register ********************/
+#define BKP_CSR_CTE_Pos (0U)
+#define BKP_CSR_CTE_Msk (0x1U << BKP_CSR_CTE_Pos) /*!< 0x00000001 */
+#define BKP_CSR_CTE BKP_CSR_CTE_Msk /*!< Clear Tamper event */
+#define BKP_CSR_CTI_Pos (1U)
+#define BKP_CSR_CTI_Msk (0x1U << BKP_CSR_CTI_Pos) /*!< 0x00000002 */
+#define BKP_CSR_CTI BKP_CSR_CTI_Msk /*!< Clear Tamper Interrupt */
+#define BKP_CSR_TPIE_Pos (2U)
+#define BKP_CSR_TPIE_Msk (0x1U << BKP_CSR_TPIE_Pos) /*!< 0x00000004 */
+#define BKP_CSR_TPIE BKP_CSR_TPIE_Msk /*!< TAMPER Pin interrupt enable */
+#define BKP_CSR_TEF_Pos (8U)
+#define BKP_CSR_TEF_Msk (0x1U << BKP_CSR_TEF_Pos) /*!< 0x00000100 */
+#define BKP_CSR_TEF BKP_CSR_TEF_Msk /*!< Tamper Event Flag */
+#define BKP_CSR_TIF_Pos (9U)
+#define BKP_CSR_TIF_Msk (0x1U << BKP_CSR_TIF_Pos) /*!< 0x00000200 */
+#define BKP_CSR_TIF BKP_CSR_TIF_Msk /*!< Tamper Interrupt Flag */
+
+/******************************************************************************/
+/* */
+/* Reset and Clock Control */
+/* */
+/******************************************************************************/
+
+/******************** Bit definition for RCC_CR register ********************/
+#define RCC_CR_HSION_Pos (0U)
+#define RCC_CR_HSION_Msk (0x1U << RCC_CR_HSION_Pos) /*!< 0x00000001 */
+#define RCC_CR_HSION RCC_CR_HSION_Msk /*!< Internal High Speed clock enable */
+#define RCC_CR_HSIRDY_Pos (1U)
+#define RCC_CR_HSIRDY_Msk (0x1U << RCC_CR_HSIRDY_Pos) /*!< 0x00000002 */
+#define RCC_CR_HSIRDY RCC_CR_HSIRDY_Msk /*!< Internal High Speed clock ready flag */
+#define RCC_CR_HSITRIM_Pos (3U)
+#define RCC_CR_HSITRIM_Msk (0x1FU << RCC_CR_HSITRIM_Pos) /*!< 0x000000F8 */
+#define RCC_CR_HSITRIM RCC_CR_HSITRIM_Msk /*!< Internal High Speed clock trimming */
+#define RCC_CR_HSICAL_Pos (8U)
+#define RCC_CR_HSICAL_Msk (0xFFU << RCC_CR_HSICAL_Pos) /*!< 0x0000FF00 */
+#define RCC_CR_HSICAL RCC_CR_HSICAL_Msk /*!< Internal High Speed clock Calibration */
+#define RCC_CR_HSEON_Pos (16U)
+#define RCC_CR_HSEON_Msk (0x1U << RCC_CR_HSEON_Pos) /*!< 0x00010000 */
+#define RCC_CR_HSEON RCC_CR_HSEON_Msk /*!< External High Speed clock enable */
+#define RCC_CR_HSERDY_Pos (17U)
+#define RCC_CR_HSERDY_Msk (0x1U << RCC_CR_HSERDY_Pos) /*!< 0x00020000 */
+#define RCC_CR_HSERDY RCC_CR_HSERDY_Msk /*!< External High Speed clock ready flag */
+#define RCC_CR_HSEBYP_Pos (18U)
+#define RCC_CR_HSEBYP_Msk (0x1U << RCC_CR_HSEBYP_Pos) /*!< 0x00040000 */
+#define RCC_CR_HSEBYP RCC_CR_HSEBYP_Msk /*!< External High Speed clock Bypass */
+#define RCC_CR_CSSON_Pos (19U)
+#define RCC_CR_CSSON_Msk (0x1U << RCC_CR_CSSON_Pos) /*!< 0x00080000 */
+#define RCC_CR_CSSON RCC_CR_CSSON_Msk /*!< Clock Security System enable */
+#define RCC_CR_PLLON_Pos (24U)
+#define RCC_CR_PLLON_Msk (0x1U << RCC_CR_PLLON_Pos) /*!< 0x01000000 */
+#define RCC_CR_PLLON RCC_CR_PLLON_Msk /*!< PLL enable */
+#define RCC_CR_PLLRDY_Pos (25U)
+#define RCC_CR_PLLRDY_Msk (0x1U << RCC_CR_PLLRDY_Pos) /*!< 0x02000000 */
+#define RCC_CR_PLLRDY RCC_CR_PLLRDY_Msk /*!< PLL clock ready flag */
+
+#define RCC_CR_PLL2ON_Pos (26U)
+#define RCC_CR_PLL2ON_Msk (0x1U << RCC_CR_PLL2ON_Pos) /*!< 0x04000000 */
+#define RCC_CR_PLL2ON RCC_CR_PLL2ON_Msk /*!< PLL2 enable */
+#define RCC_CR_PLL2RDY_Pos (27U)
+#define RCC_CR_PLL2RDY_Msk (0x1U << RCC_CR_PLL2RDY_Pos) /*!< 0x08000000 */
+#define RCC_CR_PLL2RDY RCC_CR_PLL2RDY_Msk /*!< PLL2 clock ready flag */
+#define RCC_CR_PLL3ON_Pos (28U)
+#define RCC_CR_PLL3ON_Msk (0x1U << RCC_CR_PLL3ON_Pos) /*!< 0x10000000 */
+#define RCC_CR_PLL3ON RCC_CR_PLL3ON_Msk /*!< PLL3 enable */
+#define RCC_CR_PLL3RDY_Pos (29U)
+#define RCC_CR_PLL3RDY_Msk (0x1U << RCC_CR_PLL3RDY_Pos) /*!< 0x20000000 */
+#define RCC_CR_PLL3RDY RCC_CR_PLL3RDY_Msk /*!< PLL3 clock ready flag */
+
+/******************* Bit definition for RCC_CFGR register *******************/
+/*!< SW configuration */
+#define RCC_CFGR_SW_Pos (0U)
+#define RCC_CFGR_SW_Msk (0x3U << RCC_CFGR_SW_Pos) /*!< 0x00000003 */
+#define RCC_CFGR_SW RCC_CFGR_SW_Msk /*!< SW[1:0] bits (System clock Switch) */
+#define RCC_CFGR_SW_0 (0x1U << RCC_CFGR_SW_Pos) /*!< 0x00000001 */
+#define RCC_CFGR_SW_1 (0x2U << RCC_CFGR_SW_Pos) /*!< 0x00000002 */
+
+#define RCC_CFGR_SW_HSI ((uint32_t)0x00000000) /*!< HSI selected as system clock */
+#define RCC_CFGR_SW_HSE ((uint32_t)0x00000001) /*!< HSE selected as system clock */
+#define RCC_CFGR_SW_PLL ((uint32_t)0x00000002) /*!< PLL selected as system clock */
+
+/*!< SWS configuration */
+#define RCC_CFGR_SWS_Pos (2U)
+#define RCC_CFGR_SWS_Msk (0x3U << RCC_CFGR_SWS_Pos) /*!< 0x0000000C */
+#define RCC_CFGR_SWS RCC_CFGR_SWS_Msk /*!< SWS[1:0] bits (System Clock Switch Status) */
+#define RCC_CFGR_SWS_0 (0x1U << RCC_CFGR_SWS_Pos) /*!< 0x00000004 */
+#define RCC_CFGR_SWS_1 (0x2U << RCC_CFGR_SWS_Pos) /*!< 0x00000008 */
+
+#define RCC_CFGR_SWS_HSI ((uint32_t)0x00000000) /*!< HSI oscillator used as system clock */
+#define RCC_CFGR_SWS_HSE ((uint32_t)0x00000004) /*!< HSE oscillator used as system clock */
+#define RCC_CFGR_SWS_PLL ((uint32_t)0x00000008) /*!< PLL used as system clock */
+
+/*!< HPRE configuration */
+#define RCC_CFGR_HPRE_Pos (4U)
+#define RCC_CFGR_HPRE_Msk (0xFU << RCC_CFGR_HPRE_Pos) /*!< 0x000000F0 */
+#define RCC_CFGR_HPRE RCC_CFGR_HPRE_Msk /*!< HPRE[3:0] bits (AHB prescaler) */
+#define RCC_CFGR_HPRE_0 (0x1U << RCC_CFGR_HPRE_Pos) /*!< 0x00000010 */
+#define RCC_CFGR_HPRE_1 (0x2U << RCC_CFGR_HPRE_Pos) /*!< 0x00000020 */
+#define RCC_CFGR_HPRE_2 (0x4U << RCC_CFGR_HPRE_Pos) /*!< 0x00000040 */
+#define RCC_CFGR_HPRE_3 (0x8U << RCC_CFGR_HPRE_Pos) /*!< 0x00000080 */
+
+#define RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000) /*!< SYSCLK not divided */
+#define RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080) /*!< SYSCLK divided by 2 */
+#define RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090) /*!< SYSCLK divided by 4 */
+#define RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0) /*!< SYSCLK divided by 8 */
+#define RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0) /*!< SYSCLK divided by 16 */
+#define RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0) /*!< SYSCLK divided by 64 */
+#define RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0) /*!< SYSCLK divided by 128 */
+#define RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0) /*!< SYSCLK divided by 256 */
+#define RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0) /*!< SYSCLK divided by 512 */
+
+/*!< PPRE1 configuration */
+#define RCC_CFGR_PPRE1_Pos (8U)
+#define RCC_CFGR_PPRE1_Msk (0x7U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000700 */
+#define RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_Msk /*!< PRE1[2:0] bits (APB1 prescaler) */
+#define RCC_CFGR_PPRE1_0 (0x1U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000100 */
+#define RCC_CFGR_PPRE1_1 (0x2U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000200 */
+#define RCC_CFGR_PPRE1_2 (0x4U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000400 */
+
+#define RCC_CFGR_PPRE1_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */
+#define RCC_CFGR_PPRE1_DIV2 ((uint32_t)0x00000400) /*!< HCLK divided by 2 */
+#define RCC_CFGR_PPRE1_DIV4 ((uint32_t)0x00000500) /*!< HCLK divided by 4 */
+#define RCC_CFGR_PPRE1_DIV8 ((uint32_t)0x00000600) /*!< HCLK divided by 8 */
+#define RCC_CFGR_PPRE1_DIV16 ((uint32_t)0x00000700) /*!< HCLK divided by 16 */
+
+/*!< PPRE2 configuration */
+#define RCC_CFGR_PPRE2_Pos (11U)
+#define RCC_CFGR_PPRE2_Msk (0x7U << RCC_CFGR_PPRE2_Pos) /*!< 0x00003800 */
+#define RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_Msk /*!< PRE2[2:0] bits (APB2 prescaler) */
+#define RCC_CFGR_PPRE2_0 (0x1U << RCC_CFGR_PPRE2_Pos) /*!< 0x00000800 */
+#define RCC_CFGR_PPRE2_1 (0x2U << RCC_CFGR_PPRE2_Pos) /*!< 0x00001000 */
+#define RCC_CFGR_PPRE2_2 (0x4U << RCC_CFGR_PPRE2_Pos) /*!< 0x00002000 */
+
+#define RCC_CFGR_PPRE2_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */
+#define RCC_CFGR_PPRE2_DIV2 ((uint32_t)0x00002000) /*!< HCLK divided by 2 */
+#define RCC_CFGR_PPRE2_DIV4 ((uint32_t)0x00002800) /*!< HCLK divided by 4 */
+#define RCC_CFGR_PPRE2_DIV8 ((uint32_t)0x00003000) /*!< HCLK divided by 8 */
+#define RCC_CFGR_PPRE2_DIV16 ((uint32_t)0x00003800) /*!< HCLK divided by 16 */
+
+/*!< ADCPPRE configuration */
+#define RCC_CFGR_ADCPRE_Pos (14U)
+#define RCC_CFGR_ADCPRE_Msk (0x3U << RCC_CFGR_ADCPRE_Pos) /*!< 0x0000C000 */
+#define RCC_CFGR_ADCPRE RCC_CFGR_ADCPRE_Msk /*!< ADCPRE[1:0] bits (ADC prescaler) */
+#define RCC_CFGR_ADCPRE_0 (0x1U << RCC_CFGR_ADCPRE_Pos) /*!< 0x00004000 */
+#define RCC_CFGR_ADCPRE_1 (0x2U << RCC_CFGR_ADCPRE_Pos) /*!< 0x00008000 */
+
+#define RCC_CFGR_ADCPRE_DIV2 ((uint32_t)0x00000000) /*!< PCLK2 divided by 2 */
+#define RCC_CFGR_ADCPRE_DIV4 ((uint32_t)0x00004000) /*!< PCLK2 divided by 4 */
+#define RCC_CFGR_ADCPRE_DIV6 ((uint32_t)0x00008000) /*!< PCLK2 divided by 6 */
+#define RCC_CFGR_ADCPRE_DIV8 ((uint32_t)0x0000C000) /*!< PCLK2 divided by 8 */
+
+#define RCC_CFGR_PLLSRC_Pos (16U)
+#define RCC_CFGR_PLLSRC_Msk (0x1U << RCC_CFGR_PLLSRC_Pos) /*!< 0x00010000 */
+#define RCC_CFGR_PLLSRC RCC_CFGR_PLLSRC_Msk /*!< PLL entry clock source */
+
+#define RCC_CFGR_PLLXTPRE_Pos (17U)
+#define RCC_CFGR_PLLXTPRE_Msk (0x1U << RCC_CFGR_PLLXTPRE_Pos) /*!< 0x00020000 */
+#define RCC_CFGR_PLLXTPRE RCC_CFGR_PLLXTPRE_Msk /*!< HSE divider for PLL entry */
+
+/*!< PLLMUL configuration */
+#define RCC_CFGR_PLLMULL_Pos (18U)
+#define RCC_CFGR_PLLMULL_Msk (0xFU << RCC_CFGR_PLLMULL_Pos) /*!< 0x003C0000 */
+#define RCC_CFGR_PLLMULL RCC_CFGR_PLLMULL_Msk /*!< PLLMUL[3:0] bits (PLL multiplication factor) */
+#define RCC_CFGR_PLLMULL_0 (0x1U << RCC_CFGR_PLLMULL_Pos) /*!< 0x00040000 */
+#define RCC_CFGR_PLLMULL_1 (0x2U << RCC_CFGR_PLLMULL_Pos) /*!< 0x00080000 */
+#define RCC_CFGR_PLLMULL_2 (0x4U << RCC_CFGR_PLLMULL_Pos) /*!< 0x00100000 */
+#define RCC_CFGR_PLLMULL_3 (0x8U << RCC_CFGR_PLLMULL_Pos) /*!< 0x00200000 */
+
+#define RCC_CFGR_PLLXTPRE_PREDIV1 ((uint32_t)0x00000000) /*!< PREDIV1 clock not divided for PLL entry */
+#define RCC_CFGR_PLLXTPRE_PREDIV1_DIV2 ((uint32_t)0x00020000) /*!< PREDIV1 clock divided by 2 for PLL entry */
+
+#define RCC_CFGR_PLLMULL4_Pos (19U)
+#define RCC_CFGR_PLLMULL4_Msk (0x1U << RCC_CFGR_PLLMULL4_Pos) /*!< 0x00080000 */
+#define RCC_CFGR_PLLMULL4 RCC_CFGR_PLLMULL4_Msk /*!< PLL input clock * 4 */
+#define RCC_CFGR_PLLMULL5_Pos (18U)
+#define RCC_CFGR_PLLMULL5_Msk (0x3U << RCC_CFGR_PLLMULL5_Pos) /*!< 0x000C0000 */
+#define RCC_CFGR_PLLMULL5 RCC_CFGR_PLLMULL5_Msk /*!< PLL input clock * 5 */
+#define RCC_CFGR_PLLMULL6_Pos (20U)
+#define RCC_CFGR_PLLMULL6_Msk (0x1U << RCC_CFGR_PLLMULL6_Pos) /*!< 0x00100000 */
+#define RCC_CFGR_PLLMULL6 RCC_CFGR_PLLMULL6_Msk /*!< PLL input clock * 6 */
+#define RCC_CFGR_PLLMULL7_Pos (18U)
+#define RCC_CFGR_PLLMULL7_Msk (0x5U << RCC_CFGR_PLLMULL7_Pos) /*!< 0x00140000 */
+#define RCC_CFGR_PLLMULL7 RCC_CFGR_PLLMULL7_Msk /*!< PLL input clock * 7 */
+#define RCC_CFGR_PLLMULL8_Pos (19U)
+#define RCC_CFGR_PLLMULL8_Msk (0x3U << RCC_CFGR_PLLMULL8_Pos) /*!< 0x00180000 */
+#define RCC_CFGR_PLLMULL8 RCC_CFGR_PLLMULL8_Msk /*!< PLL input clock * 8 */
+#define RCC_CFGR_PLLMULL9_Pos (18U)
+#define RCC_CFGR_PLLMULL9_Msk (0x7U << RCC_CFGR_PLLMULL9_Pos) /*!< 0x001C0000 */
+#define RCC_CFGR_PLLMULL9 RCC_CFGR_PLLMULL9_Msk /*!< PLL input clock * 9 */
+#define RCC_CFGR_PLLMULL6_5 ((uint32_t)0x00340000) /*!< PLL input clock * 6.5 */
+
+#define RCC_CFGR_OTGFSPRE_Pos (22U)
+#define RCC_CFGR_OTGFSPRE_Msk (0x1U << RCC_CFGR_OTGFSPRE_Pos) /*!< 0x00400000 */
+#define RCC_CFGR_OTGFSPRE RCC_CFGR_OTGFSPRE_Msk /*!< USB OTG FS prescaler */
+
+/*!< MCO configuration */
+#define RCC_CFGR_MCO_Pos (24U)
+#define RCC_CFGR_MCO_Msk (0xFU << RCC_CFGR_MCO_Pos) /*!< 0x0F000000 */
+#define RCC_CFGR_MCO RCC_CFGR_MCO_Msk /*!< MCO[3:0] bits (Microcontroller Clock Output) */
+#define RCC_CFGR_MCO_0 (0x1U << RCC_CFGR_MCO_Pos) /*!< 0x01000000 */
+#define RCC_CFGR_MCO_1 (0x2U << RCC_CFGR_MCO_Pos) /*!< 0x02000000 */
+#define RCC_CFGR_MCO_2 (0x4U << RCC_CFGR_MCO_Pos) /*!< 0x04000000 */
+#define RCC_CFGR_MCO_3 (0x8U << RCC_CFGR_MCO_Pos) /*!< 0x08000000 */
+
+#define RCC_CFGR_MCO_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */
+#define RCC_CFGR_MCO_SYSCLK ((uint32_t)0x04000000) /*!< System clock selected as MCO source */
+#define RCC_CFGR_MCO_HSI ((uint32_t)0x05000000) /*!< HSI clock selected as MCO source */
+#define RCC_CFGR_MCO_HSE ((uint32_t)0x06000000) /*!< HSE clock selected as MCO source */
+#define RCC_CFGR_MCO_PLLCLK_DIV2 ((uint32_t)0x07000000) /*!< PLL clock divided by 2 selected as MCO source */
+#define RCC_CFGR_MCO_PLL2CLK ((uint32_t)0x08000000) /*!< PLL2 clock selected as MCO source*/
+#define RCC_CFGR_MCO_PLL3CLK_DIV2 ((uint32_t)0x09000000) /*!< PLL3 clock divided by 2 selected as MCO source*/
+#define RCC_CFGR_MCO_EXT_HSE ((uint32_t)0x0A000000) /*!< XT1 external 3-25 MHz oscillator clock selected as MCO source */
+#define RCC_CFGR_MCO_PLL3CLK ((uint32_t)0x0B000000) /*!< PLL3 clock selected as MCO source */
+
+ /* Reference defines */
+ #define RCC_CFGR_MCOSEL RCC_CFGR_MCO
+ #define RCC_CFGR_MCOSEL_0 RCC_CFGR_MCO_0
+ #define RCC_CFGR_MCOSEL_1 RCC_CFGR_MCO_1
+ #define RCC_CFGR_MCOSEL_2 RCC_CFGR_MCO_2
+ #define RCC_CFGR_MCOSEL_3 RCC_CFGR_MCO_3
+ #define RCC_CFGR_MCOSEL_NOCLOCK RCC_CFGR_MCO_NOCLOCK
+ #define RCC_CFGR_MCOSEL_SYSCLK RCC_CFGR_MCO_SYSCLK
+ #define RCC_CFGR_MCOSEL_HSI RCC_CFGR_MCO_HSI
+ #define RCC_CFGR_MCOSEL_HSE RCC_CFGR_MCO_HSE
+ #define RCC_CFGR_MCOSEL_PLL_DIV2 RCC_CFGR_MCO_PLLCLK_DIV2
+ #define RCC_CFGR_MCOSEL_PLL2 RCC_CFGR_MCO_PLL2CLK
+ #define RCC_CFGR_MCOSEL_PLL3_DIV2 RCC_CFGR_MCO_PLL3CLK_DIV2
+ #define RCC_CFGR_MCOSEL_EXT_HSE RCC_CFGR_MCO_EXT_HSE
+ #define RCC_CFGR_MCOSEL_PLL3CLK RCC_CFGR_MCO_PLL3CLK
+
+/*!<****************** Bit definition for RCC_CIR register ********************/
+#define RCC_CIR_LSIRDYF_Pos (0U)
+#define RCC_CIR_LSIRDYF_Msk (0x1U << RCC_CIR_LSIRDYF_Pos) /*!< 0x00000001 */
+#define RCC_CIR_LSIRDYF RCC_CIR_LSIRDYF_Msk /*!< LSI Ready Interrupt flag */
+#define RCC_CIR_LSERDYF_Pos (1U)
+#define RCC_CIR_LSERDYF_Msk (0x1U << RCC_CIR_LSERDYF_Pos) /*!< 0x00000002 */
+#define RCC_CIR_LSERDYF RCC_CIR_LSERDYF_Msk /*!< LSE Ready Interrupt flag */
+#define RCC_CIR_HSIRDYF_Pos (2U)
+#define RCC_CIR_HSIRDYF_Msk (0x1U << RCC_CIR_HSIRDYF_Pos) /*!< 0x00000004 */
+#define RCC_CIR_HSIRDYF RCC_CIR_HSIRDYF_Msk /*!< HSI Ready Interrupt flag */
+#define RCC_CIR_HSERDYF_Pos (3U)
+#define RCC_CIR_HSERDYF_Msk (0x1U << RCC_CIR_HSERDYF_Pos) /*!< 0x00000008 */
+#define RCC_CIR_HSERDYF RCC_CIR_HSERDYF_Msk /*!< HSE Ready Interrupt flag */
+#define RCC_CIR_PLLRDYF_Pos (4U)
+#define RCC_CIR_PLLRDYF_Msk (0x1U << RCC_CIR_PLLRDYF_Pos) /*!< 0x00000010 */
+#define RCC_CIR_PLLRDYF RCC_CIR_PLLRDYF_Msk /*!< PLL Ready Interrupt flag */
+#define RCC_CIR_CSSF_Pos (7U)
+#define RCC_CIR_CSSF_Msk (0x1U << RCC_CIR_CSSF_Pos) /*!< 0x00000080 */
+#define RCC_CIR_CSSF RCC_CIR_CSSF_Msk /*!< Clock Security System Interrupt flag */
+#define RCC_CIR_LSIRDYIE_Pos (8U)
+#define RCC_CIR_LSIRDYIE_Msk (0x1U << RCC_CIR_LSIRDYIE_Pos) /*!< 0x00000100 */
+#define RCC_CIR_LSIRDYIE RCC_CIR_LSIRDYIE_Msk /*!< LSI Ready Interrupt Enable */
+#define RCC_CIR_LSERDYIE_Pos (9U)
+#define RCC_CIR_LSERDYIE_Msk (0x1U << RCC_CIR_LSERDYIE_Pos) /*!< 0x00000200 */
+#define RCC_CIR_LSERDYIE RCC_CIR_LSERDYIE_Msk /*!< LSE Ready Interrupt Enable */
+#define RCC_CIR_HSIRDYIE_Pos (10U)
+#define RCC_CIR_HSIRDYIE_Msk (0x1U << RCC_CIR_HSIRDYIE_Pos) /*!< 0x00000400 */
+#define RCC_CIR_HSIRDYIE RCC_CIR_HSIRDYIE_Msk /*!< HSI Ready Interrupt Enable */
+#define RCC_CIR_HSERDYIE_Pos (11U)
+#define RCC_CIR_HSERDYIE_Msk (0x1U << RCC_CIR_HSERDYIE_Pos) /*!< 0x00000800 */
+#define RCC_CIR_HSERDYIE RCC_CIR_HSERDYIE_Msk /*!< HSE Ready Interrupt Enable */
+#define RCC_CIR_PLLRDYIE_Pos (12U)
+#define RCC_CIR_PLLRDYIE_Msk (0x1U << RCC_CIR_PLLRDYIE_Pos) /*!< 0x00001000 */
+#define RCC_CIR_PLLRDYIE RCC_CIR_PLLRDYIE_Msk /*!< PLL Ready Interrupt Enable */
+#define RCC_CIR_LSIRDYC_Pos (16U)
+#define RCC_CIR_LSIRDYC_Msk (0x1U << RCC_CIR_LSIRDYC_Pos) /*!< 0x00010000 */
+#define RCC_CIR_LSIRDYC RCC_CIR_LSIRDYC_Msk /*!< LSI Ready Interrupt Clear */
+#define RCC_CIR_LSERDYC_Pos (17U)
+#define RCC_CIR_LSERDYC_Msk (0x1U << RCC_CIR_LSERDYC_Pos) /*!< 0x00020000 */
+#define RCC_CIR_LSERDYC RCC_CIR_LSERDYC_Msk /*!< LSE Ready Interrupt Clear */
+#define RCC_CIR_HSIRDYC_Pos (18U)
+#define RCC_CIR_HSIRDYC_Msk (0x1U << RCC_CIR_HSIRDYC_Pos) /*!< 0x00040000 */
+#define RCC_CIR_HSIRDYC RCC_CIR_HSIRDYC_Msk /*!< HSI Ready Interrupt Clear */
+#define RCC_CIR_HSERDYC_Pos (19U)
+#define RCC_CIR_HSERDYC_Msk (0x1U << RCC_CIR_HSERDYC_Pos) /*!< 0x00080000 */
+#define RCC_CIR_HSERDYC RCC_CIR_HSERDYC_Msk /*!< HSE Ready Interrupt Clear */
+#define RCC_CIR_PLLRDYC_Pos (20U)
+#define RCC_CIR_PLLRDYC_Msk (0x1U << RCC_CIR_PLLRDYC_Pos) /*!< 0x00100000 */
+#define RCC_CIR_PLLRDYC RCC_CIR_PLLRDYC_Msk /*!< PLL Ready Interrupt Clear */
+#define RCC_CIR_CSSC_Pos (23U)
+#define RCC_CIR_CSSC_Msk (0x1U << RCC_CIR_CSSC_Pos) /*!< 0x00800000 */
+#define RCC_CIR_CSSC RCC_CIR_CSSC_Msk /*!< Clock Security System Interrupt Clear */
+
+#define RCC_CIR_PLL2RDYF_Pos (5U)
+#define RCC_CIR_PLL2RDYF_Msk (0x1U << RCC_CIR_PLL2RDYF_Pos) /*!< 0x00000020 */
+#define RCC_CIR_PLL2RDYF RCC_CIR_PLL2RDYF_Msk /*!< PLL2 Ready Interrupt flag */
+#define RCC_CIR_PLL3RDYF_Pos (6U)
+#define RCC_CIR_PLL3RDYF_Msk (0x1U << RCC_CIR_PLL3RDYF_Pos) /*!< 0x00000040 */
+#define RCC_CIR_PLL3RDYF RCC_CIR_PLL3RDYF_Msk /*!< PLL3 Ready Interrupt flag */
+#define RCC_CIR_PLL2RDYIE_Pos (13U)
+#define RCC_CIR_PLL2RDYIE_Msk (0x1U << RCC_CIR_PLL2RDYIE_Pos) /*!< 0x00002000 */
+#define RCC_CIR_PLL2RDYIE RCC_CIR_PLL2RDYIE_Msk /*!< PLL2 Ready Interrupt Enable */
+#define RCC_CIR_PLL3RDYIE_Pos (14U)
+#define RCC_CIR_PLL3RDYIE_Msk (0x1U << RCC_CIR_PLL3RDYIE_Pos) /*!< 0x00004000 */
+#define RCC_CIR_PLL3RDYIE RCC_CIR_PLL3RDYIE_Msk /*!< PLL3 Ready Interrupt Enable */
+#define RCC_CIR_PLL2RDYC_Pos (21U)
+#define RCC_CIR_PLL2RDYC_Msk (0x1U << RCC_CIR_PLL2RDYC_Pos) /*!< 0x00200000 */
+#define RCC_CIR_PLL2RDYC RCC_CIR_PLL2RDYC_Msk /*!< PLL2 Ready Interrupt Clear */
+#define RCC_CIR_PLL3RDYC_Pos (22U)
+#define RCC_CIR_PLL3RDYC_Msk (0x1U << RCC_CIR_PLL3RDYC_Pos) /*!< 0x00400000 */
+#define RCC_CIR_PLL3RDYC RCC_CIR_PLL3RDYC_Msk /*!< PLL3 Ready Interrupt Clear */
+
+/***************** Bit definition for RCC_APB2RSTR register *****************/
+#define RCC_APB2RSTR_AFIORST_Pos (0U)
+#define RCC_APB2RSTR_AFIORST_Msk (0x1U << RCC_APB2RSTR_AFIORST_Pos) /*!< 0x00000001 */
+#define RCC_APB2RSTR_AFIORST RCC_APB2RSTR_AFIORST_Msk /*!< Alternate Function I/O reset */
+#define RCC_APB2RSTR_IOPARST_Pos (2U)
+#define RCC_APB2RSTR_IOPARST_Msk (0x1U << RCC_APB2RSTR_IOPARST_Pos) /*!< 0x00000004 */
+#define RCC_APB2RSTR_IOPARST RCC_APB2RSTR_IOPARST_Msk /*!< I/O port A reset */
+#define RCC_APB2RSTR_IOPBRST_Pos (3U)
+#define RCC_APB2RSTR_IOPBRST_Msk (0x1U << RCC_APB2RSTR_IOPBRST_Pos) /*!< 0x00000008 */
+#define RCC_APB2RSTR_IOPBRST RCC_APB2RSTR_IOPBRST_Msk /*!< I/O port B reset */
+#define RCC_APB2RSTR_IOPCRST_Pos (4U)
+#define RCC_APB2RSTR_IOPCRST_Msk (0x1U << RCC_APB2RSTR_IOPCRST_Pos) /*!< 0x00000010 */
+#define RCC_APB2RSTR_IOPCRST RCC_APB2RSTR_IOPCRST_Msk /*!< I/O port C reset */
+#define RCC_APB2RSTR_IOPDRST_Pos (5U)
+#define RCC_APB2RSTR_IOPDRST_Msk (0x1U << RCC_APB2RSTR_IOPDRST_Pos) /*!< 0x00000020 */
+#define RCC_APB2RSTR_IOPDRST RCC_APB2RSTR_IOPDRST_Msk /*!< I/O port D reset */
+#define RCC_APB2RSTR_ADC1RST_Pos (9U)
+#define RCC_APB2RSTR_ADC1RST_Msk (0x1U << RCC_APB2RSTR_ADC1RST_Pos) /*!< 0x00000200 */
+#define RCC_APB2RSTR_ADC1RST RCC_APB2RSTR_ADC1RST_Msk /*!< ADC 1 interface reset */
+
+#define RCC_APB2RSTR_ADC2RST_Pos (10U)
+#define RCC_APB2RSTR_ADC2RST_Msk (0x1U << RCC_APB2RSTR_ADC2RST_Pos) /*!< 0x00000400 */
+#define RCC_APB2RSTR_ADC2RST RCC_APB2RSTR_ADC2RST_Msk /*!< ADC 2 interface reset */
+
+#define RCC_APB2RSTR_TIM1RST_Pos (11U)
+#define RCC_APB2RSTR_TIM1RST_Msk (0x1U << RCC_APB2RSTR_TIM1RST_Pos) /*!< 0x00000800 */
+#define RCC_APB2RSTR_TIM1RST RCC_APB2RSTR_TIM1RST_Msk /*!< TIM1 Timer reset */
+#define RCC_APB2RSTR_SPI1RST_Pos (12U)
+#define RCC_APB2RSTR_SPI1RST_Msk (0x1U << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */
+#define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk /*!< SPI 1 reset */
+#define RCC_APB2RSTR_USART1RST_Pos (14U)
+#define RCC_APB2RSTR_USART1RST_Msk (0x1U << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00004000 */
+#define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk /*!< USART1 reset */
+
+
+#define RCC_APB2RSTR_IOPERST_Pos (6U)
+#define RCC_APB2RSTR_IOPERST_Msk (0x1U << RCC_APB2RSTR_IOPERST_Pos) /*!< 0x00000040 */
+#define RCC_APB2RSTR_IOPERST RCC_APB2RSTR_IOPERST_Msk /*!< I/O port E reset */
+
+
+
+
+/***************** Bit definition for RCC_APB1RSTR register *****************/
+#define RCC_APB1RSTR_TIM2RST_Pos (0U)
+#define RCC_APB1RSTR_TIM2RST_Msk (0x1U << RCC_APB1RSTR_TIM2RST_Pos) /*!< 0x00000001 */
+#define RCC_APB1RSTR_TIM2RST RCC_APB1RSTR_TIM2RST_Msk /*!< Timer 2 reset */
+#define RCC_APB1RSTR_TIM3RST_Pos (1U)
+#define RCC_APB1RSTR_TIM3RST_Msk (0x1U << RCC_APB1RSTR_TIM3RST_Pos) /*!< 0x00000002 */
+#define RCC_APB1RSTR_TIM3RST RCC_APB1RSTR_TIM3RST_Msk /*!< Timer 3 reset */
+#define RCC_APB1RSTR_WWDGRST_Pos (11U)
+#define RCC_APB1RSTR_WWDGRST_Msk (0x1U << RCC_APB1RSTR_WWDGRST_Pos) /*!< 0x00000800 */
+#define RCC_APB1RSTR_WWDGRST RCC_APB1RSTR_WWDGRST_Msk /*!< Window Watchdog reset */
+#define RCC_APB1RSTR_USART2RST_Pos (17U)
+#define RCC_APB1RSTR_USART2RST_Msk (0x1U << RCC_APB1RSTR_USART2RST_Pos) /*!< 0x00020000 */
+#define RCC_APB1RSTR_USART2RST RCC_APB1RSTR_USART2RST_Msk /*!< USART 2 reset */
+#define RCC_APB1RSTR_I2C1RST_Pos (21U)
+#define RCC_APB1RSTR_I2C1RST_Msk (0x1U << RCC_APB1RSTR_I2C1RST_Pos) /*!< 0x00200000 */
+#define RCC_APB1RSTR_I2C1RST RCC_APB1RSTR_I2C1RST_Msk /*!< I2C 1 reset */
+
+#define RCC_APB1RSTR_CAN1RST_Pos (25U)
+#define RCC_APB1RSTR_CAN1RST_Msk (0x1U << RCC_APB1RSTR_CAN1RST_Pos) /*!< 0x02000000 */
+#define RCC_APB1RSTR_CAN1RST RCC_APB1RSTR_CAN1RST_Msk /*!< CAN1 reset */
+
+#define RCC_APB1RSTR_BKPRST_Pos (27U)
+#define RCC_APB1RSTR_BKPRST_Msk (0x1U << RCC_APB1RSTR_BKPRST_Pos) /*!< 0x08000000 */
+#define RCC_APB1RSTR_BKPRST RCC_APB1RSTR_BKPRST_Msk /*!< Backup interface reset */
+#define RCC_APB1RSTR_PWRRST_Pos (28U)
+#define RCC_APB1RSTR_PWRRST_Msk (0x1U << RCC_APB1RSTR_PWRRST_Pos) /*!< 0x10000000 */
+#define RCC_APB1RSTR_PWRRST RCC_APB1RSTR_PWRRST_Msk /*!< Power interface reset */
+
+#define RCC_APB1RSTR_TIM4RST_Pos (2U)
+#define RCC_APB1RSTR_TIM4RST_Msk (0x1U << RCC_APB1RSTR_TIM4RST_Pos) /*!< 0x00000004 */
+#define RCC_APB1RSTR_TIM4RST RCC_APB1RSTR_TIM4RST_Msk /*!< Timer 4 reset */
+#define RCC_APB1RSTR_SPI2RST_Pos (14U)
+#define RCC_APB1RSTR_SPI2RST_Msk (0x1U << RCC_APB1RSTR_SPI2RST_Pos) /*!< 0x00004000 */
+#define RCC_APB1RSTR_SPI2RST RCC_APB1RSTR_SPI2RST_Msk /*!< SPI 2 reset */
+#define RCC_APB1RSTR_USART3RST_Pos (18U)
+#define RCC_APB1RSTR_USART3RST_Msk (0x1U << RCC_APB1RSTR_USART3RST_Pos) /*!< 0x00040000 */
+#define RCC_APB1RSTR_USART3RST RCC_APB1RSTR_USART3RST_Msk /*!< USART 3 reset */
+#define RCC_APB1RSTR_I2C2RST_Pos (22U)
+#define RCC_APB1RSTR_I2C2RST_Msk (0x1U << RCC_APB1RSTR_I2C2RST_Pos) /*!< 0x00400000 */
+#define RCC_APB1RSTR_I2C2RST RCC_APB1RSTR_I2C2RST_Msk /*!< I2C 2 reset */
+
+
+#define RCC_APB1RSTR_TIM5RST_Pos (3U)
+#define RCC_APB1RSTR_TIM5RST_Msk (0x1U << RCC_APB1RSTR_TIM5RST_Pos) /*!< 0x00000008 */
+#define RCC_APB1RSTR_TIM5RST RCC_APB1RSTR_TIM5RST_Msk /*!< Timer 5 reset */
+#define RCC_APB1RSTR_TIM6RST_Pos (4U)
+#define RCC_APB1RSTR_TIM6RST_Msk (0x1U << RCC_APB1RSTR_TIM6RST_Pos) /*!< 0x00000010 */
+#define RCC_APB1RSTR_TIM6RST RCC_APB1RSTR_TIM6RST_Msk /*!< Timer 6 reset */
+#define RCC_APB1RSTR_TIM7RST_Pos (5U)
+#define RCC_APB1RSTR_TIM7RST_Msk (0x1U << RCC_APB1RSTR_TIM7RST_Pos) /*!< 0x00000020 */
+#define RCC_APB1RSTR_TIM7RST RCC_APB1RSTR_TIM7RST_Msk /*!< Timer 7 reset */
+#define RCC_APB1RSTR_SPI3RST_Pos (15U)
+#define RCC_APB1RSTR_SPI3RST_Msk (0x1U << RCC_APB1RSTR_SPI3RST_Pos) /*!< 0x00008000 */
+#define RCC_APB1RSTR_SPI3RST RCC_APB1RSTR_SPI3RST_Msk /*!< SPI 3 reset */
+#define RCC_APB1RSTR_UART4RST_Pos (19U)
+#define RCC_APB1RSTR_UART4RST_Msk (0x1U << RCC_APB1RSTR_UART4RST_Pos) /*!< 0x00080000 */
+#define RCC_APB1RSTR_UART4RST RCC_APB1RSTR_UART4RST_Msk /*!< UART 4 reset */
+#define RCC_APB1RSTR_UART5RST_Pos (20U)
+#define RCC_APB1RSTR_UART5RST_Msk (0x1U << RCC_APB1RSTR_UART5RST_Pos) /*!< 0x00100000 */
+#define RCC_APB1RSTR_UART5RST RCC_APB1RSTR_UART5RST_Msk /*!< UART 5 reset */
+
+
+
+#define RCC_APB1RSTR_CAN2RST_Pos (26U)
+#define RCC_APB1RSTR_CAN2RST_Msk (0x1U << RCC_APB1RSTR_CAN2RST_Pos) /*!< 0x04000000 */
+#define RCC_APB1RSTR_CAN2RST RCC_APB1RSTR_CAN2RST_Msk /*!< CAN2 reset */
+
+#define RCC_APB1RSTR_DACRST_Pos (29U)
+#define RCC_APB1RSTR_DACRST_Msk (0x1U << RCC_APB1RSTR_DACRST_Pos) /*!< 0x20000000 */
+#define RCC_APB1RSTR_DACRST RCC_APB1RSTR_DACRST_Msk /*!< DAC interface reset */
+
+/****************** Bit definition for RCC_AHBENR register ******************/
+#define RCC_AHBENR_DMA1EN_Pos (0U)
+#define RCC_AHBENR_DMA1EN_Msk (0x1U << RCC_AHBENR_DMA1EN_Pos) /*!< 0x00000001 */
+#define RCC_AHBENR_DMA1EN RCC_AHBENR_DMA1EN_Msk /*!< DMA1 clock enable */
+#define RCC_AHBENR_SRAMEN_Pos (2U)
+#define RCC_AHBENR_SRAMEN_Msk (0x1U << RCC_AHBENR_SRAMEN_Pos) /*!< 0x00000004 */
+#define RCC_AHBENR_SRAMEN RCC_AHBENR_SRAMEN_Msk /*!< SRAM interface clock enable */
+#define RCC_AHBENR_FLITFEN_Pos (4U)
+#define RCC_AHBENR_FLITFEN_Msk (0x1U << RCC_AHBENR_FLITFEN_Pos) /*!< 0x00000010 */
+#define RCC_AHBENR_FLITFEN RCC_AHBENR_FLITFEN_Msk /*!< FLITF clock enable */
+#define RCC_AHBENR_CRCEN_Pos (6U)
+#define RCC_AHBENR_CRCEN_Msk (0x1U << RCC_AHBENR_CRCEN_Pos) /*!< 0x00000040 */
+#define RCC_AHBENR_CRCEN RCC_AHBENR_CRCEN_Msk /*!< CRC clock enable */
+
+#define RCC_AHBENR_DMA2EN_Pos (1U)
+#define RCC_AHBENR_DMA2EN_Msk (0x1U << RCC_AHBENR_DMA2EN_Pos) /*!< 0x00000002 */
+#define RCC_AHBENR_DMA2EN RCC_AHBENR_DMA2EN_Msk /*!< DMA2 clock enable */
+
+
+#define RCC_AHBENR_OTGFSEN_Pos (12U)
+#define RCC_AHBENR_OTGFSEN_Msk (0x1U << RCC_AHBENR_OTGFSEN_Pos) /*!< 0x00001000 */
+#define RCC_AHBENR_OTGFSEN RCC_AHBENR_OTGFSEN_Msk /*!< USB OTG FS clock enable */
+#define RCC_AHBENR_ETHMACEN_Pos (14U)
+#define RCC_AHBENR_ETHMACEN_Msk (0x1U << RCC_AHBENR_ETHMACEN_Pos) /*!< 0x00004000 */
+#define RCC_AHBENR_ETHMACEN RCC_AHBENR_ETHMACEN_Msk /*!< ETHERNET MAC clock enable */
+#define RCC_AHBENR_ETHMACTXEN_Pos (15U)
+#define RCC_AHBENR_ETHMACTXEN_Msk (0x1U << RCC_AHBENR_ETHMACTXEN_Pos) /*!< 0x00008000 */
+#define RCC_AHBENR_ETHMACTXEN RCC_AHBENR_ETHMACTXEN_Msk /*!< ETHERNET MAC Tx clock enable */
+#define RCC_AHBENR_ETHMACRXEN_Pos (16U)
+#define RCC_AHBENR_ETHMACRXEN_Msk (0x1U << RCC_AHBENR_ETHMACRXEN_Pos) /*!< 0x00010000 */
+#define RCC_AHBENR_ETHMACRXEN RCC_AHBENR_ETHMACRXEN_Msk /*!< ETHERNET MAC Rx clock enable */
+
+/****************** Bit definition for RCC_APB2ENR register *****************/
+#define RCC_APB2ENR_AFIOEN_Pos (0U)
+#define RCC_APB2ENR_AFIOEN_Msk (0x1U << RCC_APB2ENR_AFIOEN_Pos) /*!< 0x00000001 */
+#define RCC_APB2ENR_AFIOEN RCC_APB2ENR_AFIOEN_Msk /*!< Alternate Function I/O clock enable */
+#define RCC_APB2ENR_IOPAEN_Pos (2U)
+#define RCC_APB2ENR_IOPAEN_Msk (0x1U << RCC_APB2ENR_IOPAEN_Pos) /*!< 0x00000004 */
+#define RCC_APB2ENR_IOPAEN RCC_APB2ENR_IOPAEN_Msk /*!< I/O port A clock enable */
+#define RCC_APB2ENR_IOPBEN_Pos (3U)
+#define RCC_APB2ENR_IOPBEN_Msk (0x1U << RCC_APB2ENR_IOPBEN_Pos) /*!< 0x00000008 */
+#define RCC_APB2ENR_IOPBEN RCC_APB2ENR_IOPBEN_Msk /*!< I/O port B clock enable */
+#define RCC_APB2ENR_IOPCEN_Pos (4U)
+#define RCC_APB2ENR_IOPCEN_Msk (0x1U << RCC_APB2ENR_IOPCEN_Pos) /*!< 0x00000010 */
+#define RCC_APB2ENR_IOPCEN RCC_APB2ENR_IOPCEN_Msk /*!< I/O port C clock enable */
+#define RCC_APB2ENR_IOPDEN_Pos (5U)
+#define RCC_APB2ENR_IOPDEN_Msk (0x1U << RCC_APB2ENR_IOPDEN_Pos) /*!< 0x00000020 */
+#define RCC_APB2ENR_IOPDEN RCC_APB2ENR_IOPDEN_Msk /*!< I/O port D clock enable */
+#define RCC_APB2ENR_ADC1EN_Pos (9U)
+#define RCC_APB2ENR_ADC1EN_Msk (0x1U << RCC_APB2ENR_ADC1EN_Pos) /*!< 0x00000200 */
+#define RCC_APB2ENR_ADC1EN RCC_APB2ENR_ADC1EN_Msk /*!< ADC 1 interface clock enable */
+
+#define RCC_APB2ENR_ADC2EN_Pos (10U)
+#define RCC_APB2ENR_ADC2EN_Msk (0x1U << RCC_APB2ENR_ADC2EN_Pos) /*!< 0x00000400 */
+#define RCC_APB2ENR_ADC2EN RCC_APB2ENR_ADC2EN_Msk /*!< ADC 2 interface clock enable */
+
+#define RCC_APB2ENR_TIM1EN_Pos (11U)
+#define RCC_APB2ENR_TIM1EN_Msk (0x1U << RCC_APB2ENR_TIM1EN_Pos) /*!< 0x00000800 */
+#define RCC_APB2ENR_TIM1EN RCC_APB2ENR_TIM1EN_Msk /*!< TIM1 Timer clock enable */
+#define RCC_APB2ENR_SPI1EN_Pos (12U)
+#define RCC_APB2ENR_SPI1EN_Msk (0x1U << RCC_APB2ENR_SPI1EN_Pos) /*!< 0x00001000 */
+#define RCC_APB2ENR_SPI1EN RCC_APB2ENR_SPI1EN_Msk /*!< SPI 1 clock enable */
+#define RCC_APB2ENR_USART1EN_Pos (14U)
+#define RCC_APB2ENR_USART1EN_Msk (0x1U << RCC_APB2ENR_USART1EN_Pos) /*!< 0x00004000 */
+#define RCC_APB2ENR_USART1EN RCC_APB2ENR_USART1EN_Msk /*!< USART1 clock enable */
+
+
+#define RCC_APB2ENR_IOPEEN_Pos (6U)
+#define RCC_APB2ENR_IOPEEN_Msk (0x1U << RCC_APB2ENR_IOPEEN_Pos) /*!< 0x00000040 */
+#define RCC_APB2ENR_IOPEEN RCC_APB2ENR_IOPEEN_Msk /*!< I/O port E clock enable */
+
+
+
+
+/***************** Bit definition for RCC_APB1ENR register ******************/
+#define RCC_APB1ENR_TIM2EN_Pos (0U)
+#define RCC_APB1ENR_TIM2EN_Msk (0x1U << RCC_APB1ENR_TIM2EN_Pos) /*!< 0x00000001 */
+#define RCC_APB1ENR_TIM2EN RCC_APB1ENR_TIM2EN_Msk /*!< Timer 2 clock enabled*/
+#define RCC_APB1ENR_TIM3EN_Pos (1U)
+#define RCC_APB1ENR_TIM3EN_Msk (0x1U << RCC_APB1ENR_TIM3EN_Pos) /*!< 0x00000002 */
+#define RCC_APB1ENR_TIM3EN RCC_APB1ENR_TIM3EN_Msk /*!< Timer 3 clock enable */
+#define RCC_APB1ENR_WWDGEN_Pos (11U)
+#define RCC_APB1ENR_WWDGEN_Msk (0x1U << RCC_APB1ENR_WWDGEN_Pos) /*!< 0x00000800 */
+#define RCC_APB1ENR_WWDGEN RCC_APB1ENR_WWDGEN_Msk /*!< Window Watchdog clock enable */
+#define RCC_APB1ENR_USART2EN_Pos (17U)
+#define RCC_APB1ENR_USART2EN_Msk (0x1U << RCC_APB1ENR_USART2EN_Pos) /*!< 0x00020000 */
+#define RCC_APB1ENR_USART2EN RCC_APB1ENR_USART2EN_Msk /*!< USART 2 clock enable */
+#define RCC_APB1ENR_I2C1EN_Pos (21U)
+#define RCC_APB1ENR_I2C1EN_Msk (0x1U << RCC_APB1ENR_I2C1EN_Pos) /*!< 0x00200000 */
+#define RCC_APB1ENR_I2C1EN RCC_APB1ENR_I2C1EN_Msk /*!< I2C 1 clock enable */
+
+#define RCC_APB1ENR_CAN1EN_Pos (25U)
+#define RCC_APB1ENR_CAN1EN_Msk (0x1U << RCC_APB1ENR_CAN1EN_Pos) /*!< 0x02000000 */
+#define RCC_APB1ENR_CAN1EN RCC_APB1ENR_CAN1EN_Msk /*!< CAN1 clock enable */
+
+#define RCC_APB1ENR_BKPEN_Pos (27U)
+#define RCC_APB1ENR_BKPEN_Msk (0x1U << RCC_APB1ENR_BKPEN_Pos) /*!< 0x08000000 */
+#define RCC_APB1ENR_BKPEN RCC_APB1ENR_BKPEN_Msk /*!< Backup interface clock enable */
+#define RCC_APB1ENR_PWREN_Pos (28U)
+#define RCC_APB1ENR_PWREN_Msk (0x1U << RCC_APB1ENR_PWREN_Pos) /*!< 0x10000000 */
+#define RCC_APB1ENR_PWREN RCC_APB1ENR_PWREN_Msk /*!< Power interface clock enable */
+
+#define RCC_APB1ENR_TIM4EN_Pos (2U)
+#define RCC_APB1ENR_TIM4EN_Msk (0x1U << RCC_APB1ENR_TIM4EN_Pos) /*!< 0x00000004 */
+#define RCC_APB1ENR_TIM4EN RCC_APB1ENR_TIM4EN_Msk /*!< Timer 4 clock enable */
+#define RCC_APB1ENR_SPI2EN_Pos (14U)
+#define RCC_APB1ENR_SPI2EN_Msk (0x1U << RCC_APB1ENR_SPI2EN_Pos) /*!< 0x00004000 */
+#define RCC_APB1ENR_SPI2EN RCC_APB1ENR_SPI2EN_Msk /*!< SPI 2 clock enable */
+#define RCC_APB1ENR_USART3EN_Pos (18U)
+#define RCC_APB1ENR_USART3EN_Msk (0x1U << RCC_APB1ENR_USART3EN_Pos) /*!< 0x00040000 */
+#define RCC_APB1ENR_USART3EN RCC_APB1ENR_USART3EN_Msk /*!< USART 3 clock enable */
+#define RCC_APB1ENR_I2C2EN_Pos (22U)
+#define RCC_APB1ENR_I2C2EN_Msk (0x1U << RCC_APB1ENR_I2C2EN_Pos) /*!< 0x00400000 */
+#define RCC_APB1ENR_I2C2EN RCC_APB1ENR_I2C2EN_Msk /*!< I2C 2 clock enable */
+
+
+#define RCC_APB1ENR_TIM5EN_Pos (3U)
+#define RCC_APB1ENR_TIM5EN_Msk (0x1U << RCC_APB1ENR_TIM5EN_Pos) /*!< 0x00000008 */
+#define RCC_APB1ENR_TIM5EN RCC_APB1ENR_TIM5EN_Msk /*!< Timer 5 clock enable */
+#define RCC_APB1ENR_TIM6EN_Pos (4U)
+#define RCC_APB1ENR_TIM6EN_Msk (0x1U << RCC_APB1ENR_TIM6EN_Pos) /*!< 0x00000010 */
+#define RCC_APB1ENR_TIM6EN RCC_APB1ENR_TIM6EN_Msk /*!< Timer 6 clock enable */
+#define RCC_APB1ENR_TIM7EN_Pos (5U)
+#define RCC_APB1ENR_TIM7EN_Msk (0x1U << RCC_APB1ENR_TIM7EN_Pos) /*!< 0x00000020 */
+#define RCC_APB1ENR_TIM7EN RCC_APB1ENR_TIM7EN_Msk /*!< Timer 7 clock enable */
+#define RCC_APB1ENR_SPI3EN_Pos (15U)
+#define RCC_APB1ENR_SPI3EN_Msk (0x1U << RCC_APB1ENR_SPI3EN_Pos) /*!< 0x00008000 */
+#define RCC_APB1ENR_SPI3EN RCC_APB1ENR_SPI3EN_Msk /*!< SPI 3 clock enable */
+#define RCC_APB1ENR_UART4EN_Pos (19U)
+#define RCC_APB1ENR_UART4EN_Msk (0x1U << RCC_APB1ENR_UART4EN_Pos) /*!< 0x00080000 */
+#define RCC_APB1ENR_UART4EN RCC_APB1ENR_UART4EN_Msk /*!< UART 4 clock enable */
+#define RCC_APB1ENR_UART5EN_Pos (20U)
+#define RCC_APB1ENR_UART5EN_Msk (0x1U << RCC_APB1ENR_UART5EN_Pos) /*!< 0x00100000 */
+#define RCC_APB1ENR_UART5EN RCC_APB1ENR_UART5EN_Msk /*!< UART 5 clock enable */
+
+
+
+#define RCC_APB1ENR_CAN2EN_Pos (26U)
+#define RCC_APB1ENR_CAN2EN_Msk (0x1U << RCC_APB1ENR_CAN2EN_Pos) /*!< 0x04000000 */
+#define RCC_APB1ENR_CAN2EN RCC_APB1ENR_CAN2EN_Msk /*!< CAN2 clock enable */
+
+#define RCC_APB1ENR_DACEN_Pos (29U)
+#define RCC_APB1ENR_DACEN_Msk (0x1U << RCC_APB1ENR_DACEN_Pos) /*!< 0x20000000 */
+#define RCC_APB1ENR_DACEN RCC_APB1ENR_DACEN_Msk /*!< DAC interface clock enable */
+
+/******************* Bit definition for RCC_BDCR register *******************/
+#define RCC_BDCR_LSEON_Pos (0U)
+#define RCC_BDCR_LSEON_Msk (0x1U << RCC_BDCR_LSEON_Pos) /*!< 0x00000001 */
+#define RCC_BDCR_LSEON RCC_BDCR_LSEON_Msk /*!< External Low Speed oscillator enable */
+#define RCC_BDCR_LSERDY_Pos (1U)
+#define RCC_BDCR_LSERDY_Msk (0x1U << RCC_BDCR_LSERDY_Pos) /*!< 0x00000002 */
+#define RCC_BDCR_LSERDY RCC_BDCR_LSERDY_Msk /*!< External Low Speed oscillator Ready */
+#define RCC_BDCR_LSEBYP_Pos (2U)
+#define RCC_BDCR_LSEBYP_Msk (0x1U << RCC_BDCR_LSEBYP_Pos) /*!< 0x00000004 */
+#define RCC_BDCR_LSEBYP RCC_BDCR_LSEBYP_Msk /*!< External Low Speed oscillator Bypass */
+
+#define RCC_BDCR_RTCSEL_Pos (8U)
+#define RCC_BDCR_RTCSEL_Msk (0x3U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000300 */
+#define RCC_BDCR_RTCSEL RCC_BDCR_RTCSEL_Msk /*!< RTCSEL[1:0] bits (RTC clock source selection) */
+#define RCC_BDCR_RTCSEL_0 (0x1U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000100 */
+#define RCC_BDCR_RTCSEL_1 (0x2U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000200 */
+
+/*!< RTC congiguration */
+#define RCC_BDCR_RTCSEL_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */
+#define RCC_BDCR_RTCSEL_LSE ((uint32_t)0x00000100) /*!< LSE oscillator clock used as RTC clock */
+#define RCC_BDCR_RTCSEL_LSI ((uint32_t)0x00000200) /*!< LSI oscillator clock used as RTC clock */
+#define RCC_BDCR_RTCSEL_HSE ((uint32_t)0x00000300) /*!< HSE oscillator clock divided by 128 used as RTC clock */
+
+#define RCC_BDCR_RTCEN_Pos (15U)
+#define RCC_BDCR_RTCEN_Msk (0x1U << RCC_BDCR_RTCEN_Pos) /*!< 0x00008000 */
+#define RCC_BDCR_RTCEN RCC_BDCR_RTCEN_Msk /*!< RTC clock enable */
+#define RCC_BDCR_BDRST_Pos (16U)
+#define RCC_BDCR_BDRST_Msk (0x1U << RCC_BDCR_BDRST_Pos) /*!< 0x00010000 */
+#define RCC_BDCR_BDRST RCC_BDCR_BDRST_Msk /*!< Backup domain software reset */
+
+/******************* Bit definition for RCC_CSR register ********************/
+#define RCC_CSR_LSION_Pos (0U)
+#define RCC_CSR_LSION_Msk (0x1U << RCC_CSR_LSION_Pos) /*!< 0x00000001 */
+#define RCC_CSR_LSION RCC_CSR_LSION_Msk /*!< Internal Low Speed oscillator enable */
+#define RCC_CSR_LSIRDY_Pos (1U)
+#define RCC_CSR_LSIRDY_Msk (0x1U << RCC_CSR_LSIRDY_Pos) /*!< 0x00000002 */
+#define RCC_CSR_LSIRDY RCC_CSR_LSIRDY_Msk /*!< Internal Low Speed oscillator Ready */
+#define RCC_CSR_RMVF_Pos (24U)
+#define RCC_CSR_RMVF_Msk (0x1U << RCC_CSR_RMVF_Pos) /*!< 0x01000000 */
+#define RCC_CSR_RMVF RCC_CSR_RMVF_Msk /*!< Remove reset flag */
+#define RCC_CSR_PINRSTF_Pos (26U)
+#define RCC_CSR_PINRSTF_Msk (0x1U << RCC_CSR_PINRSTF_Pos) /*!< 0x04000000 */
+#define RCC_CSR_PINRSTF RCC_CSR_PINRSTF_Msk /*!< PIN reset flag */
+#define RCC_CSR_PORRSTF_Pos (27U)
+#define RCC_CSR_PORRSTF_Msk (0x1U << RCC_CSR_PORRSTF_Pos) /*!< 0x08000000 */
+#define RCC_CSR_PORRSTF RCC_CSR_PORRSTF_Msk /*!< POR/PDR reset flag */
+#define RCC_CSR_SFTRSTF_Pos (28U)
+#define RCC_CSR_SFTRSTF_Msk (0x1U << RCC_CSR_SFTRSTF_Pos) /*!< 0x10000000 */
+#define RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF_Msk /*!< Software Reset flag */
+#define RCC_CSR_IWDGRSTF_Pos (29U)
+#define RCC_CSR_IWDGRSTF_Msk (0x1U << RCC_CSR_IWDGRSTF_Pos) /*!< 0x20000000 */
+#define RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF_Msk /*!< Independent Watchdog reset flag */
+#define RCC_CSR_WWDGRSTF_Pos (30U)
+#define RCC_CSR_WWDGRSTF_Msk (0x1U << RCC_CSR_WWDGRSTF_Pos) /*!< 0x40000000 */
+#define RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF_Msk /*!< Window watchdog reset flag */
+#define RCC_CSR_LPWRRSTF_Pos (31U)
+#define RCC_CSR_LPWRRSTF_Msk (0x1U << RCC_CSR_LPWRRSTF_Pos) /*!< 0x80000000 */
+#define RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF_Msk /*!< Low-Power reset flag */
+
+/******************* Bit definition for RCC_AHBRSTR register ****************/
+#define RCC_AHBRSTR_OTGFSRST_Pos (12U)
+#define RCC_AHBRSTR_OTGFSRST_Msk (0x1U << RCC_AHBRSTR_OTGFSRST_Pos) /*!< 0x00001000 */
+#define RCC_AHBRSTR_OTGFSRST RCC_AHBRSTR_OTGFSRST_Msk /*!< USB OTG FS reset */
+#define RCC_AHBRSTR_ETHMACRST_Pos (14U)
+#define RCC_AHBRSTR_ETHMACRST_Msk (0x1U << RCC_AHBRSTR_ETHMACRST_Pos) /*!< 0x00004000 */
+#define RCC_AHBRSTR_ETHMACRST RCC_AHBRSTR_ETHMACRST_Msk /*!< ETHERNET MAC reset */
+
+/******************* Bit definition for RCC_CFGR2 register ******************/
+/*!< PREDIV1 configuration */
+#define RCC_CFGR2_PREDIV1_Pos (0U)
+#define RCC_CFGR2_PREDIV1_Msk (0xFU << RCC_CFGR2_PREDIV1_Pos) /*!< 0x0000000F */
+#define RCC_CFGR2_PREDIV1 RCC_CFGR2_PREDIV1_Msk /*!< PREDIV1[3:0] bits */
+#define RCC_CFGR2_PREDIV1_0 (0x1U << RCC_CFGR2_PREDIV1_Pos) /*!< 0x00000001 */
+#define RCC_CFGR2_PREDIV1_1 (0x2U << RCC_CFGR2_PREDIV1_Pos) /*!< 0x00000002 */
+#define RCC_CFGR2_PREDIV1_2 (0x4U << RCC_CFGR2_PREDIV1_Pos) /*!< 0x00000004 */
+#define RCC_CFGR2_PREDIV1_3 (0x8U << RCC_CFGR2_PREDIV1_Pos) /*!< 0x00000008 */
+
+#define RCC_CFGR2_PREDIV1_DIV1 ((uint32_t)0x00000000) /*!< PREDIV1 input clock not divided */
+#define RCC_CFGR2_PREDIV1_DIV2_Pos (0U)
+#define RCC_CFGR2_PREDIV1_DIV2_Msk (0x1U << RCC_CFGR2_PREDIV1_DIV2_Pos) /*!< 0x00000001 */
+#define RCC_CFGR2_PREDIV1_DIV2 RCC_CFGR2_PREDIV1_DIV2_Msk /*!< PREDIV1 input clock divided by 2 */
+#define RCC_CFGR2_PREDIV1_DIV3_Pos (1U)
+#define RCC_CFGR2_PREDIV1_DIV3_Msk (0x1U << RCC_CFGR2_PREDIV1_DIV3_Pos) /*!< 0x00000002 */
+#define RCC_CFGR2_PREDIV1_DIV3 RCC_CFGR2_PREDIV1_DIV3_Msk /*!< PREDIV1 input clock divided by 3 */
+#define RCC_CFGR2_PREDIV1_DIV4_Pos (0U)
+#define RCC_CFGR2_PREDIV1_DIV4_Msk (0x3U << RCC_CFGR2_PREDIV1_DIV4_Pos) /*!< 0x00000003 */
+#define RCC_CFGR2_PREDIV1_DIV4 RCC_CFGR2_PREDIV1_DIV4_Msk /*!< PREDIV1 input clock divided by 4 */
+#define RCC_CFGR2_PREDIV1_DIV5_Pos (2U)
+#define RCC_CFGR2_PREDIV1_DIV5_Msk (0x1U << RCC_CFGR2_PREDIV1_DIV5_Pos) /*!< 0x00000004 */
+#define RCC_CFGR2_PREDIV1_DIV5 RCC_CFGR2_PREDIV1_DIV5_Msk /*!< PREDIV1 input clock divided by 5 */
+#define RCC_CFGR2_PREDIV1_DIV6_Pos (0U)
+#define RCC_CFGR2_PREDIV1_DIV6_Msk (0x5U << RCC_CFGR2_PREDIV1_DIV6_Pos) /*!< 0x00000005 */
+#define RCC_CFGR2_PREDIV1_DIV6 RCC_CFGR2_PREDIV1_DIV6_Msk /*!< PREDIV1 input clock divided by 6 */
+#define RCC_CFGR2_PREDIV1_DIV7_Pos (1U)
+#define RCC_CFGR2_PREDIV1_DIV7_Msk (0x3U << RCC_CFGR2_PREDIV1_DIV7_Pos) /*!< 0x00000006 */
+#define RCC_CFGR2_PREDIV1_DIV7 RCC_CFGR2_PREDIV1_DIV7_Msk /*!< PREDIV1 input clock divided by 7 */
+#define RCC_CFGR2_PREDIV1_DIV8_Pos (0U)
+#define RCC_CFGR2_PREDIV1_DIV8_Msk (0x7U << RCC_CFGR2_PREDIV1_DIV8_Pos) /*!< 0x00000007 */
+#define RCC_CFGR2_PREDIV1_DIV8 RCC_CFGR2_PREDIV1_DIV8_Msk /*!< PREDIV1 input clock divided by 8 */
+#define RCC_CFGR2_PREDIV1_DIV9_Pos (3U)
+#define RCC_CFGR2_PREDIV1_DIV9_Msk (0x1U << RCC_CFGR2_PREDIV1_DIV9_Pos) /*!< 0x00000008 */
+#define RCC_CFGR2_PREDIV1_DIV9 RCC_CFGR2_PREDIV1_DIV9_Msk /*!< PREDIV1 input clock divided by 9 */
+#define RCC_CFGR2_PREDIV1_DIV10_Pos (0U)
+#define RCC_CFGR2_PREDIV1_DIV10_Msk (0x9U << RCC_CFGR2_PREDIV1_DIV10_Pos) /*!< 0x00000009 */
+#define RCC_CFGR2_PREDIV1_DIV10 RCC_CFGR2_PREDIV1_DIV10_Msk /*!< PREDIV1 input clock divided by 10 */
+#define RCC_CFGR2_PREDIV1_DIV11_Pos (1U)
+#define RCC_CFGR2_PREDIV1_DIV11_Msk (0x5U << RCC_CFGR2_PREDIV1_DIV11_Pos) /*!< 0x0000000A */
+#define RCC_CFGR2_PREDIV1_DIV11 RCC_CFGR2_PREDIV1_DIV11_Msk /*!< PREDIV1 input clock divided by 11 */
+#define RCC_CFGR2_PREDIV1_DIV12_Pos (0U)
+#define RCC_CFGR2_PREDIV1_DIV12_Msk (0xBU << RCC_CFGR2_PREDIV1_DIV12_Pos) /*!< 0x0000000B */
+#define RCC_CFGR2_PREDIV1_DIV12 RCC_CFGR2_PREDIV1_DIV12_Msk /*!< PREDIV1 input clock divided by 12 */
+#define RCC_CFGR2_PREDIV1_DIV13_Pos (2U)
+#define RCC_CFGR2_PREDIV1_DIV13_Msk (0x3U << RCC_CFGR2_PREDIV1_DIV13_Pos) /*!< 0x0000000C */
+#define RCC_CFGR2_PREDIV1_DIV13 RCC_CFGR2_PREDIV1_DIV13_Msk /*!< PREDIV1 input clock divided by 13 */
+#define RCC_CFGR2_PREDIV1_DIV14_Pos (0U)
+#define RCC_CFGR2_PREDIV1_DIV14_Msk (0xDU << RCC_CFGR2_PREDIV1_DIV14_Pos) /*!< 0x0000000D */
+#define RCC_CFGR2_PREDIV1_DIV14 RCC_CFGR2_PREDIV1_DIV14_Msk /*!< PREDIV1 input clock divided by 14 */
+#define RCC_CFGR2_PREDIV1_DIV15_Pos (1U)
+#define RCC_CFGR2_PREDIV1_DIV15_Msk (0x7U << RCC_CFGR2_PREDIV1_DIV15_Pos) /*!< 0x0000000E */
+#define RCC_CFGR2_PREDIV1_DIV15 RCC_CFGR2_PREDIV1_DIV15_Msk /*!< PREDIV1 input clock divided by 15 */
+#define RCC_CFGR2_PREDIV1_DIV16_Pos (0U)
+#define RCC_CFGR2_PREDIV1_DIV16_Msk (0xFU << RCC_CFGR2_PREDIV1_DIV16_Pos) /*!< 0x0000000F */
+#define RCC_CFGR2_PREDIV1_DIV16 RCC_CFGR2_PREDIV1_DIV16_Msk /*!< PREDIV1 input clock divided by 16 */
+
+/*!< PREDIV2 configuration */
+#define RCC_CFGR2_PREDIV2_Pos (4U)
+#define RCC_CFGR2_PREDIV2_Msk (0xFU << RCC_CFGR2_PREDIV2_Pos) /*!< 0x000000F0 */
+#define RCC_CFGR2_PREDIV2 RCC_CFGR2_PREDIV2_Msk /*!< PREDIV2[3:0] bits */
+#define RCC_CFGR2_PREDIV2_0 (0x1U << RCC_CFGR2_PREDIV2_Pos) /*!< 0x00000010 */
+#define RCC_CFGR2_PREDIV2_1 (0x2U << RCC_CFGR2_PREDIV2_Pos) /*!< 0x00000020 */
+#define RCC_CFGR2_PREDIV2_2 (0x4U << RCC_CFGR2_PREDIV2_Pos) /*!< 0x00000040 */
+#define RCC_CFGR2_PREDIV2_3 (0x8U << RCC_CFGR2_PREDIV2_Pos) /*!< 0x00000080 */
+
+#define RCC_CFGR2_PREDIV2_DIV1 ((uint32_t)0x00000000) /*!< PREDIV2 input clock not divided */
+#define RCC_CFGR2_PREDIV2_DIV2_Pos (4U)
+#define RCC_CFGR2_PREDIV2_DIV2_Msk (0x1U << RCC_CFGR2_PREDIV2_DIV2_Pos) /*!< 0x00000010 */
+#define RCC_CFGR2_PREDIV2_DIV2 RCC_CFGR2_PREDIV2_DIV2_Msk /*!< PREDIV2 input clock divided by 2 */
+#define RCC_CFGR2_PREDIV2_DIV3_Pos (5U)
+#define RCC_CFGR2_PREDIV2_DIV3_Msk (0x1U << RCC_CFGR2_PREDIV2_DIV3_Pos) /*!< 0x00000020 */
+#define RCC_CFGR2_PREDIV2_DIV3 RCC_CFGR2_PREDIV2_DIV3_Msk /*!< PREDIV2 input clock divided by 3 */
+#define RCC_CFGR2_PREDIV2_DIV4_Pos (4U)
+#define RCC_CFGR2_PREDIV2_DIV4_Msk (0x3U << RCC_CFGR2_PREDIV2_DIV4_Pos) /*!< 0x00000030 */
+#define RCC_CFGR2_PREDIV2_DIV4 RCC_CFGR2_PREDIV2_DIV4_Msk /*!< PREDIV2 input clock divided by 4 */
+#define RCC_CFGR2_PREDIV2_DIV5_Pos (6U)
+#define RCC_CFGR2_PREDIV2_DIV5_Msk (0x1U << RCC_CFGR2_PREDIV2_DIV5_Pos) /*!< 0x00000040 */
+#define RCC_CFGR2_PREDIV2_DIV5 RCC_CFGR2_PREDIV2_DIV5_Msk /*!< PREDIV2 input clock divided by 5 */
+#define RCC_CFGR2_PREDIV2_DIV6_Pos (4U)
+#define RCC_CFGR2_PREDIV2_DIV6_Msk (0x5U << RCC_CFGR2_PREDIV2_DIV6_Pos) /*!< 0x00000050 */
+#define RCC_CFGR2_PREDIV2_DIV6 RCC_CFGR2_PREDIV2_DIV6_Msk /*!< PREDIV2 input clock divided by 6 */
+#define RCC_CFGR2_PREDIV2_DIV7_Pos (5U)
+#define RCC_CFGR2_PREDIV2_DIV7_Msk (0x3U << RCC_CFGR2_PREDIV2_DIV7_Pos) /*!< 0x00000060 */
+#define RCC_CFGR2_PREDIV2_DIV7 RCC_CFGR2_PREDIV2_DIV7_Msk /*!< PREDIV2 input clock divided by 7 */
+#define RCC_CFGR2_PREDIV2_DIV8_Pos (4U)
+#define RCC_CFGR2_PREDIV2_DIV8_Msk (0x7U << RCC_CFGR2_PREDIV2_DIV8_Pos) /*!< 0x00000070 */
+#define RCC_CFGR2_PREDIV2_DIV8 RCC_CFGR2_PREDIV2_DIV8_Msk /*!< PREDIV2 input clock divided by 8 */
+#define RCC_CFGR2_PREDIV2_DIV9_Pos (7U)
+#define RCC_CFGR2_PREDIV2_DIV9_Msk (0x1U << RCC_CFGR2_PREDIV2_DIV9_Pos) /*!< 0x00000080 */
+#define RCC_CFGR2_PREDIV2_DIV9 RCC_CFGR2_PREDIV2_DIV9_Msk /*!< PREDIV2 input clock divided by 9 */
+#define RCC_CFGR2_PREDIV2_DIV10_Pos (4U)
+#define RCC_CFGR2_PREDIV2_DIV10_Msk (0x9U << RCC_CFGR2_PREDIV2_DIV10_Pos) /*!< 0x00000090 */
+#define RCC_CFGR2_PREDIV2_DIV10 RCC_CFGR2_PREDIV2_DIV10_Msk /*!< PREDIV2 input clock divided by 10 */
+#define RCC_CFGR2_PREDIV2_DIV11_Pos (5U)
+#define RCC_CFGR2_PREDIV2_DIV11_Msk (0x5U << RCC_CFGR2_PREDIV2_DIV11_Pos) /*!< 0x000000A0 */
+#define RCC_CFGR2_PREDIV2_DIV11 RCC_CFGR2_PREDIV2_DIV11_Msk /*!< PREDIV2 input clock divided by 11 */
+#define RCC_CFGR2_PREDIV2_DIV12_Pos (4U)
+#define RCC_CFGR2_PREDIV2_DIV12_Msk (0xBU << RCC_CFGR2_PREDIV2_DIV12_Pos) /*!< 0x000000B0 */
+#define RCC_CFGR2_PREDIV2_DIV12 RCC_CFGR2_PREDIV2_DIV12_Msk /*!< PREDIV2 input clock divided by 12 */
+#define RCC_CFGR2_PREDIV2_DIV13_Pos (6U)
+#define RCC_CFGR2_PREDIV2_DIV13_Msk (0x3U << RCC_CFGR2_PREDIV2_DIV13_Pos) /*!< 0x000000C0 */
+#define RCC_CFGR2_PREDIV2_DIV13 RCC_CFGR2_PREDIV2_DIV13_Msk /*!< PREDIV2 input clock divided by 13 */
+#define RCC_CFGR2_PREDIV2_DIV14_Pos (4U)
+#define RCC_CFGR2_PREDIV2_DIV14_Msk (0xDU << RCC_CFGR2_PREDIV2_DIV14_Pos) /*!< 0x000000D0 */
+#define RCC_CFGR2_PREDIV2_DIV14 RCC_CFGR2_PREDIV2_DIV14_Msk /*!< PREDIV2 input clock divided by 14 */
+#define RCC_CFGR2_PREDIV2_DIV15_Pos (5U)
+#define RCC_CFGR2_PREDIV2_DIV15_Msk (0x7U << RCC_CFGR2_PREDIV2_DIV15_Pos) /*!< 0x000000E0 */
+#define RCC_CFGR2_PREDIV2_DIV15 RCC_CFGR2_PREDIV2_DIV15_Msk /*!< PREDIV2 input clock divided by 15 */
+#define RCC_CFGR2_PREDIV2_DIV16_Pos (4U)
+#define RCC_CFGR2_PREDIV2_DIV16_Msk (0xFU << RCC_CFGR2_PREDIV2_DIV16_Pos) /*!< 0x000000F0 */
+#define RCC_CFGR2_PREDIV2_DIV16 RCC_CFGR2_PREDIV2_DIV16_Msk /*!< PREDIV2 input clock divided by 16 */
+
+/*!< PLL2MUL configuration */
+#define RCC_CFGR2_PLL2MUL_Pos (8U)
+#define RCC_CFGR2_PLL2MUL_Msk (0xFU << RCC_CFGR2_PLL2MUL_Pos) /*!< 0x00000F00 */
+#define RCC_CFGR2_PLL2MUL RCC_CFGR2_PLL2MUL_Msk /*!< PLL2MUL[3:0] bits */
+#define RCC_CFGR2_PLL2MUL_0 (0x1U << RCC_CFGR2_PLL2MUL_Pos) /*!< 0x00000100 */
+#define RCC_CFGR2_PLL2MUL_1 (0x2U << RCC_CFGR2_PLL2MUL_Pos) /*!< 0x00000200 */
+#define RCC_CFGR2_PLL2MUL_2 (0x4U << RCC_CFGR2_PLL2MUL_Pos) /*!< 0x00000400 */
+#define RCC_CFGR2_PLL2MUL_3 (0x8U << RCC_CFGR2_PLL2MUL_Pos) /*!< 0x00000800 */
+
+#define RCC_CFGR2_PLL2MUL8_Pos (9U)
+#define RCC_CFGR2_PLL2MUL8_Msk (0x3U << RCC_CFGR2_PLL2MUL8_Pos) /*!< 0x00000600 */
+#define RCC_CFGR2_PLL2MUL8 RCC_CFGR2_PLL2MUL8_Msk /*!< PLL2 input clock * 8 */
+#define RCC_CFGR2_PLL2MUL9_Pos (8U)
+#define RCC_CFGR2_PLL2MUL9_Msk (0x7U << RCC_CFGR2_PLL2MUL9_Pos) /*!< 0x00000700 */
+#define RCC_CFGR2_PLL2MUL9 RCC_CFGR2_PLL2MUL9_Msk /*!< PLL2 input clock * 9 */
+#define RCC_CFGR2_PLL2MUL10_Pos (11U)
+#define RCC_CFGR2_PLL2MUL10_Msk (0x1U << RCC_CFGR2_PLL2MUL10_Pos) /*!< 0x00000800 */
+#define RCC_CFGR2_PLL2MUL10 RCC_CFGR2_PLL2MUL10_Msk /*!< PLL2 input clock * 10 */
+#define RCC_CFGR2_PLL2MUL11_Pos (8U)
+#define RCC_CFGR2_PLL2MUL11_Msk (0x9U << RCC_CFGR2_PLL2MUL11_Pos) /*!< 0x00000900 */
+#define RCC_CFGR2_PLL2MUL11 RCC_CFGR2_PLL2MUL11_Msk /*!< PLL2 input clock * 11 */
+#define RCC_CFGR2_PLL2MUL12_Pos (9U)
+#define RCC_CFGR2_PLL2MUL12_Msk (0x5U << RCC_CFGR2_PLL2MUL12_Pos) /*!< 0x00000A00 */
+#define RCC_CFGR2_PLL2MUL12 RCC_CFGR2_PLL2MUL12_Msk /*!< PLL2 input clock * 12 */
+#define RCC_CFGR2_PLL2MUL13_Pos (8U)
+#define RCC_CFGR2_PLL2MUL13_Msk (0xBU << RCC_CFGR2_PLL2MUL13_Pos) /*!< 0x00000B00 */
+#define RCC_CFGR2_PLL2MUL13 RCC_CFGR2_PLL2MUL13_Msk /*!< PLL2 input clock * 13 */
+#define RCC_CFGR2_PLL2MUL14_Pos (10U)
+#define RCC_CFGR2_PLL2MUL14_Msk (0x3U << RCC_CFGR2_PLL2MUL14_Pos) /*!< 0x00000C00 */
+#define RCC_CFGR2_PLL2MUL14 RCC_CFGR2_PLL2MUL14_Msk /*!< PLL2 input clock * 14 */
+#define RCC_CFGR2_PLL2MUL16_Pos (9U)
+#define RCC_CFGR2_PLL2MUL16_Msk (0x7U << RCC_CFGR2_PLL2MUL16_Pos) /*!< 0x00000E00 */
+#define RCC_CFGR2_PLL2MUL16 RCC_CFGR2_PLL2MUL16_Msk /*!< PLL2 input clock * 16 */
+#define RCC_CFGR2_PLL2MUL20_Pos (8U)
+#define RCC_CFGR2_PLL2MUL20_Msk (0xFU << RCC_CFGR2_PLL2MUL20_Pos) /*!< 0x00000F00 */
+#define RCC_CFGR2_PLL2MUL20 RCC_CFGR2_PLL2MUL20_Msk /*!< PLL2 input clock * 20 */
+
+/*!< PLL3MUL configuration */
+#define RCC_CFGR2_PLL3MUL_Pos (12U)
+#define RCC_CFGR2_PLL3MUL_Msk (0xFU << RCC_CFGR2_PLL3MUL_Pos) /*!< 0x0000F000 */
+#define RCC_CFGR2_PLL3MUL RCC_CFGR2_PLL3MUL_Msk /*!< PLL3MUL[3:0] bits */
+#define RCC_CFGR2_PLL3MUL_0 (0x1U << RCC_CFGR2_PLL3MUL_Pos) /*!< 0x00001000 */
+#define RCC_CFGR2_PLL3MUL_1 (0x2U << RCC_CFGR2_PLL3MUL_Pos) /*!< 0x00002000 */
+#define RCC_CFGR2_PLL3MUL_2 (0x4U << RCC_CFGR2_PLL3MUL_Pos) /*!< 0x00004000 */
+#define RCC_CFGR2_PLL3MUL_3 (0x8U << RCC_CFGR2_PLL3MUL_Pos) /*!< 0x00008000 */
+
+#define RCC_CFGR2_PLL3MUL8_Pos (13U)
+#define RCC_CFGR2_PLL3MUL8_Msk (0x3U << RCC_CFGR2_PLL3MUL8_Pos) /*!< 0x00006000 */
+#define RCC_CFGR2_PLL3MUL8 RCC_CFGR2_PLL3MUL8_Msk /*!< PLL3 input clock * 8 */
+#define RCC_CFGR2_PLL3MUL9_Pos (12U)
+#define RCC_CFGR2_PLL3MUL9_Msk (0x7U << RCC_CFGR2_PLL3MUL9_Pos) /*!< 0x00007000 */
+#define RCC_CFGR2_PLL3MUL9 RCC_CFGR2_PLL3MUL9_Msk /*!< PLL3 input clock * 9 */
+#define RCC_CFGR2_PLL3MUL10_Pos (15U)
+#define RCC_CFGR2_PLL3MUL10_Msk (0x1U << RCC_CFGR2_PLL3MUL10_Pos) /*!< 0x00008000 */
+#define RCC_CFGR2_PLL3MUL10 RCC_CFGR2_PLL3MUL10_Msk /*!< PLL3 input clock * 10 */
+#define RCC_CFGR2_PLL3MUL11_Pos (12U)
+#define RCC_CFGR2_PLL3MUL11_Msk (0x9U << RCC_CFGR2_PLL3MUL11_Pos) /*!< 0x00009000 */
+#define RCC_CFGR2_PLL3MUL11 RCC_CFGR2_PLL3MUL11_Msk /*!< PLL3 input clock * 11 */
+#define RCC_CFGR2_PLL3MUL12_Pos (13U)
+#define RCC_CFGR2_PLL3MUL12_Msk (0x5U << RCC_CFGR2_PLL3MUL12_Pos) /*!< 0x0000A000 */
+#define RCC_CFGR2_PLL3MUL12 RCC_CFGR2_PLL3MUL12_Msk /*!< PLL3 input clock * 12 */
+#define RCC_CFGR2_PLL3MUL13_Pos (12U)
+#define RCC_CFGR2_PLL3MUL13_Msk (0xBU << RCC_CFGR2_PLL3MUL13_Pos) /*!< 0x0000B000 */
+#define RCC_CFGR2_PLL3MUL13 RCC_CFGR2_PLL3MUL13_Msk /*!< PLL3 input clock * 13 */
+#define RCC_CFGR2_PLL3MUL14_Pos (14U)
+#define RCC_CFGR2_PLL3MUL14_Msk (0x3U << RCC_CFGR2_PLL3MUL14_Pos) /*!< 0x0000C000 */
+#define RCC_CFGR2_PLL3MUL14 RCC_CFGR2_PLL3MUL14_Msk /*!< PLL3 input clock * 14 */
+#define RCC_CFGR2_PLL3MUL16_Pos (13U)
+#define RCC_CFGR2_PLL3MUL16_Msk (0x7U << RCC_CFGR2_PLL3MUL16_Pos) /*!< 0x0000E000 */
+#define RCC_CFGR2_PLL3MUL16 RCC_CFGR2_PLL3MUL16_Msk /*!< PLL3 input clock * 16 */
+#define RCC_CFGR2_PLL3MUL20_Pos (12U)
+#define RCC_CFGR2_PLL3MUL20_Msk (0xFU << RCC_CFGR2_PLL3MUL20_Pos) /*!< 0x0000F000 */
+#define RCC_CFGR2_PLL3MUL20 RCC_CFGR2_PLL3MUL20_Msk /*!< PLL3 input clock * 20 */
+
+#define RCC_CFGR2_PREDIV1SRC_Pos (16U)
+#define RCC_CFGR2_PREDIV1SRC_Msk (0x1U << RCC_CFGR2_PREDIV1SRC_Pos) /*!< 0x00010000 */
+#define RCC_CFGR2_PREDIV1SRC RCC_CFGR2_PREDIV1SRC_Msk /*!< PREDIV1 entry clock source */
+#define RCC_CFGR2_PREDIV1SRC_PLL2_Pos (16U)
+#define RCC_CFGR2_PREDIV1SRC_PLL2_Msk (0x1U << RCC_CFGR2_PREDIV1SRC_PLL2_Pos) /*!< 0x00010000 */
+#define RCC_CFGR2_PREDIV1SRC_PLL2 RCC_CFGR2_PREDIV1SRC_PLL2_Msk /*!< PLL2 selected as PREDIV1 entry clock source */
+#define RCC_CFGR2_PREDIV1SRC_HSE ((uint32_t)0x00000000) /*!< HSE selected as PREDIV1 entry clock source */
+#define RCC_CFGR2_I2S2SRC_Pos (17U)
+#define RCC_CFGR2_I2S2SRC_Msk (0x1U << RCC_CFGR2_I2S2SRC_Pos) /*!< 0x00020000 */
+#define RCC_CFGR2_I2S2SRC RCC_CFGR2_I2S2SRC_Msk /*!< I2S2 entry clock source */
+#define RCC_CFGR2_I2S3SRC_Pos (18U)
+#define RCC_CFGR2_I2S3SRC_Msk (0x1U << RCC_CFGR2_I2S3SRC_Pos) /*!< 0x00040000 */
+#define RCC_CFGR2_I2S3SRC RCC_CFGR2_I2S3SRC_Msk /*!< I2S3 clock source */
+
+
+/******************************************************************************/
+/* */
+/* General Purpose and Alternate Function I/O */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for GPIO_CRL register *******************/
+#define GPIO_CRL_MODE_Pos (0U)
+#define GPIO_CRL_MODE_Msk (0x33333333U << GPIO_CRL_MODE_Pos) /*!< 0x33333333 */
+#define GPIO_CRL_MODE GPIO_CRL_MODE_Msk /*!< Port x mode bits */
+
+#define GPIO_CRL_MODE0_Pos (0U)
+#define GPIO_CRL_MODE0_Msk (0x3U << GPIO_CRL_MODE0_Pos) /*!< 0x00000003 */
+#define GPIO_CRL_MODE0 GPIO_CRL_MODE0_Msk /*!< MODE0[1:0] bits (Port x mode bits, pin 0) */
+#define GPIO_CRL_MODE0_0 (0x1U << GPIO_CRL_MODE0_Pos) /*!< 0x00000001 */
+#define GPIO_CRL_MODE0_1 (0x2U << GPIO_CRL_MODE0_Pos) /*!< 0x00000002 */
+
+#define GPIO_CRL_MODE1_Pos (4U)
+#define GPIO_CRL_MODE1_Msk (0x3U << GPIO_CRL_MODE1_Pos) /*!< 0x00000030 */
+#define GPIO_CRL_MODE1 GPIO_CRL_MODE1_Msk /*!< MODE1[1:0] bits (Port x mode bits, pin 1) */
+#define GPIO_CRL_MODE1_0 (0x1U << GPIO_CRL_MODE1_Pos) /*!< 0x00000010 */
+#define GPIO_CRL_MODE1_1 (0x2U << GPIO_CRL_MODE1_Pos) /*!< 0x00000020 */
+
+#define GPIO_CRL_MODE2_Pos (8U)
+#define GPIO_CRL_MODE2_Msk (0x3U << GPIO_CRL_MODE2_Pos) /*!< 0x00000300 */
+#define GPIO_CRL_MODE2 GPIO_CRL_MODE2_Msk /*!< MODE2[1:0] bits (Port x mode bits, pin 2) */
+#define GPIO_CRL_MODE2_0 (0x1U << GPIO_CRL_MODE2_Pos) /*!< 0x00000100 */
+#define GPIO_CRL_MODE2_1 (0x2U << GPIO_CRL_MODE2_Pos) /*!< 0x00000200 */
+
+#define GPIO_CRL_MODE3_Pos (12U)
+#define GPIO_CRL_MODE3_Msk (0x3U << GPIO_CRL_MODE3_Pos) /*!< 0x00003000 */
+#define GPIO_CRL_MODE3 GPIO_CRL_MODE3_Msk /*!< MODE3[1:0] bits (Port x mode bits, pin 3) */
+#define GPIO_CRL_MODE3_0 (0x1U << GPIO_CRL_MODE3_Pos) /*!< 0x00001000 */
+#define GPIO_CRL_MODE3_1 (0x2U << GPIO_CRL_MODE3_Pos) /*!< 0x00002000 */
+
+#define GPIO_CRL_MODE4_Pos (16U)
+#define GPIO_CRL_MODE4_Msk (0x3U << GPIO_CRL_MODE4_Pos) /*!< 0x00030000 */
+#define GPIO_CRL_MODE4 GPIO_CRL_MODE4_Msk /*!< MODE4[1:0] bits (Port x mode bits, pin 4) */
+#define GPIO_CRL_MODE4_0 (0x1U << GPIO_CRL_MODE4_Pos) /*!< 0x00010000 */
+#define GPIO_CRL_MODE4_1 (0x2U << GPIO_CRL_MODE4_Pos) /*!< 0x00020000 */
+
+#define GPIO_CRL_MODE5_Pos (20U)
+#define GPIO_CRL_MODE5_Msk (0x3U << GPIO_CRL_MODE5_Pos) /*!< 0x00300000 */
+#define GPIO_CRL_MODE5 GPIO_CRL_MODE5_Msk /*!< MODE5[1:0] bits (Port x mode bits, pin 5) */
+#define GPIO_CRL_MODE5_0 (0x1U << GPIO_CRL_MODE5_Pos) /*!< 0x00100000 */
+#define GPIO_CRL_MODE5_1 (0x2U << GPIO_CRL_MODE5_Pos) /*!< 0x00200000 */
+
+#define GPIO_CRL_MODE6_Pos (24U)
+#define GPIO_CRL_MODE6_Msk (0x3U << GPIO_CRL_MODE6_Pos) /*!< 0x03000000 */
+#define GPIO_CRL_MODE6 GPIO_CRL_MODE6_Msk /*!< MODE6[1:0] bits (Port x mode bits, pin 6) */
+#define GPIO_CRL_MODE6_0 (0x1U << GPIO_CRL_MODE6_Pos) /*!< 0x01000000 */
+#define GPIO_CRL_MODE6_1 (0x2U << GPIO_CRL_MODE6_Pos) /*!< 0x02000000 */
+
+#define GPIO_CRL_MODE7_Pos (28U)
+#define GPIO_CRL_MODE7_Msk (0x3U << GPIO_CRL_MODE7_Pos) /*!< 0x30000000 */
+#define GPIO_CRL_MODE7 GPIO_CRL_MODE7_Msk /*!< MODE7[1:0] bits (Port x mode bits, pin 7) */
+#define GPIO_CRL_MODE7_0 (0x1U << GPIO_CRL_MODE7_Pos) /*!< 0x10000000 */
+#define GPIO_CRL_MODE7_1 (0x2U << GPIO_CRL_MODE7_Pos) /*!< 0x20000000 */
+
+#define GPIO_CRL_CNF_Pos (2U)
+#define GPIO_CRL_CNF_Msk (0x33333333U << GPIO_CRL_CNF_Pos) /*!< 0xCCCCCCCC */
+#define GPIO_CRL_CNF GPIO_CRL_CNF_Msk /*!< Port x configuration bits */
+
+#define GPIO_CRL_CNF0_Pos (2U)
+#define GPIO_CRL_CNF0_Msk (0x3U << GPIO_CRL_CNF0_Pos) /*!< 0x0000000C */
+#define GPIO_CRL_CNF0 GPIO_CRL_CNF0_Msk /*!< CNF0[1:0] bits (Port x configuration bits, pin 0) */
+#define GPIO_CRL_CNF0_0 (0x1U << GPIO_CRL_CNF0_Pos) /*!< 0x00000004 */
+#define GPIO_CRL_CNF0_1 (0x2U << GPIO_CRL_CNF0_Pos) /*!< 0x00000008 */
+
+#define GPIO_CRL_CNF1_Pos (6U)
+#define GPIO_CRL_CNF1_Msk (0x3U << GPIO_CRL_CNF1_Pos) /*!< 0x000000C0 */
+#define GPIO_CRL_CNF1 GPIO_CRL_CNF1_Msk /*!< CNF1[1:0] bits (Port x configuration bits, pin 1) */
+#define GPIO_CRL_CNF1_0 (0x1U << GPIO_CRL_CNF1_Pos) /*!< 0x00000040 */
+#define GPIO_CRL_CNF1_1 (0x2U << GPIO_CRL_CNF1_Pos) /*!< 0x00000080 */
+
+#define GPIO_CRL_CNF2_Pos (10U)
+#define GPIO_CRL_CNF2_Msk (0x3U << GPIO_CRL_CNF2_Pos) /*!< 0x00000C00 */
+#define GPIO_CRL_CNF2 GPIO_CRL_CNF2_Msk /*!< CNF2[1:0] bits (Port x configuration bits, pin 2) */
+#define GPIO_CRL_CNF2_0 (0x1U << GPIO_CRL_CNF2_Pos) /*!< 0x00000400 */
+#define GPIO_CRL_CNF2_1 (0x2U << GPIO_CRL_CNF2_Pos) /*!< 0x00000800 */
+
+#define GPIO_CRL_CNF3_Pos (14U)
+#define GPIO_CRL_CNF3_Msk (0x3U << GPIO_CRL_CNF3_Pos) /*!< 0x0000C000 */
+#define GPIO_CRL_CNF3 GPIO_CRL_CNF3_Msk /*!< CNF3[1:0] bits (Port x configuration bits, pin 3) */
+#define GPIO_CRL_CNF3_0 (0x1U << GPIO_CRL_CNF3_Pos) /*!< 0x00004000 */
+#define GPIO_CRL_CNF3_1 (0x2U << GPIO_CRL_CNF3_Pos) /*!< 0x00008000 */
+
+#define GPIO_CRL_CNF4_Pos (18U)
+#define GPIO_CRL_CNF4_Msk (0x3U << GPIO_CRL_CNF4_Pos) /*!< 0x000C0000 */
+#define GPIO_CRL_CNF4 GPIO_CRL_CNF4_Msk /*!< CNF4[1:0] bits (Port x configuration bits, pin 4) */
+#define GPIO_CRL_CNF4_0 (0x1U << GPIO_CRL_CNF4_Pos) /*!< 0x00040000 */
+#define GPIO_CRL_CNF4_1 (0x2U << GPIO_CRL_CNF4_Pos) /*!< 0x00080000 */
+
+#define GPIO_CRL_CNF5_Pos (22U)
+#define GPIO_CRL_CNF5_Msk (0x3U << GPIO_CRL_CNF5_Pos) /*!< 0x00C00000 */
+#define GPIO_CRL_CNF5 GPIO_CRL_CNF5_Msk /*!< CNF5[1:0] bits (Port x configuration bits, pin 5) */
+#define GPIO_CRL_CNF5_0 (0x1U << GPIO_CRL_CNF5_Pos) /*!< 0x00400000 */
+#define GPIO_CRL_CNF5_1 (0x2U << GPIO_CRL_CNF5_Pos) /*!< 0x00800000 */
+
+#define GPIO_CRL_CNF6_Pos (26U)
+#define GPIO_CRL_CNF6_Msk (0x3U << GPIO_CRL_CNF6_Pos) /*!< 0x0C000000 */
+#define GPIO_CRL_CNF6 GPIO_CRL_CNF6_Msk /*!< CNF6[1:0] bits (Port x configuration bits, pin 6) */
+#define GPIO_CRL_CNF6_0 (0x1U << GPIO_CRL_CNF6_Pos) /*!< 0x04000000 */
+#define GPIO_CRL_CNF6_1 (0x2U << GPIO_CRL_CNF6_Pos) /*!< 0x08000000 */
+
+#define GPIO_CRL_CNF7_Pos (30U)
+#define GPIO_CRL_CNF7_Msk (0x3U << GPIO_CRL_CNF7_Pos) /*!< 0xC0000000 */
+#define GPIO_CRL_CNF7 GPIO_CRL_CNF7_Msk /*!< CNF7[1:0] bits (Port x configuration bits, pin 7) */
+#define GPIO_CRL_CNF7_0 (0x1U << GPIO_CRL_CNF7_Pos) /*!< 0x40000000 */
+#define GPIO_CRL_CNF7_1 (0x2U << GPIO_CRL_CNF7_Pos) /*!< 0x80000000 */
+
+/******************* Bit definition for GPIO_CRH register *******************/
+#define GPIO_CRH_MODE_Pos (0U)
+#define GPIO_CRH_MODE_Msk (0x33333333U << GPIO_CRH_MODE_Pos) /*!< 0x33333333 */
+#define GPIO_CRH_MODE GPIO_CRH_MODE_Msk /*!< Port x mode bits */
+
+#define GPIO_CRH_MODE8_Pos (0U)
+#define GPIO_CRH_MODE8_Msk (0x3U << GPIO_CRH_MODE8_Pos) /*!< 0x00000003 */
+#define GPIO_CRH_MODE8 GPIO_CRH_MODE8_Msk /*!< MODE8[1:0] bits (Port x mode bits, pin 8) */
+#define GPIO_CRH_MODE8_0 (0x1U << GPIO_CRH_MODE8_Pos) /*!< 0x00000001 */
+#define GPIO_CRH_MODE8_1 (0x2U << GPIO_CRH_MODE8_Pos) /*!< 0x00000002 */
+
+#define GPIO_CRH_MODE9_Pos (4U)
+#define GPIO_CRH_MODE9_Msk (0x3U << GPIO_CRH_MODE9_Pos) /*!< 0x00000030 */
+#define GPIO_CRH_MODE9 GPIO_CRH_MODE9_Msk /*!< MODE9[1:0] bits (Port x mode bits, pin 9) */
+#define GPIO_CRH_MODE9_0 (0x1U << GPIO_CRH_MODE9_Pos) /*!< 0x00000010 */
+#define GPIO_CRH_MODE9_1 (0x2U << GPIO_CRH_MODE9_Pos) /*!< 0x00000020 */
+
+#define GPIO_CRH_MODE10_Pos (8U)
+#define GPIO_CRH_MODE10_Msk (0x3U << GPIO_CRH_MODE10_Pos) /*!< 0x00000300 */
+#define GPIO_CRH_MODE10 GPIO_CRH_MODE10_Msk /*!< MODE10[1:0] bits (Port x mode bits, pin 10) */
+#define GPIO_CRH_MODE10_0 (0x1U << GPIO_CRH_MODE10_Pos) /*!< 0x00000100 */
+#define GPIO_CRH_MODE10_1 (0x2U << GPIO_CRH_MODE10_Pos) /*!< 0x00000200 */
+
+#define GPIO_CRH_MODE11_Pos (12U)
+#define GPIO_CRH_MODE11_Msk (0x3U << GPIO_CRH_MODE11_Pos) /*!< 0x00003000 */
+#define GPIO_CRH_MODE11 GPIO_CRH_MODE11_Msk /*!< MODE11[1:0] bits (Port x mode bits, pin 11) */
+#define GPIO_CRH_MODE11_0 (0x1U << GPIO_CRH_MODE11_Pos) /*!< 0x00001000 */
+#define GPIO_CRH_MODE11_1 (0x2U << GPIO_CRH_MODE11_Pos) /*!< 0x00002000 */
+
+#define GPIO_CRH_MODE12_Pos (16U)
+#define GPIO_CRH_MODE12_Msk (0x3U << GPIO_CRH_MODE12_Pos) /*!< 0x00030000 */
+#define GPIO_CRH_MODE12 GPIO_CRH_MODE12_Msk /*!< MODE12[1:0] bits (Port x mode bits, pin 12) */
+#define GPIO_CRH_MODE12_0 (0x1U << GPIO_CRH_MODE12_Pos) /*!< 0x00010000 */
+#define GPIO_CRH_MODE12_1 (0x2U << GPIO_CRH_MODE12_Pos) /*!< 0x00020000 */
+
+#define GPIO_CRH_MODE13_Pos (20U)
+#define GPIO_CRH_MODE13_Msk (0x3U << GPIO_CRH_MODE13_Pos) /*!< 0x00300000 */
+#define GPIO_CRH_MODE13 GPIO_CRH_MODE13_Msk /*!< MODE13[1:0] bits (Port x mode bits, pin 13) */
+#define GPIO_CRH_MODE13_0 (0x1U << GPIO_CRH_MODE13_Pos) /*!< 0x00100000 */
+#define GPIO_CRH_MODE13_1 (0x2U << GPIO_CRH_MODE13_Pos) /*!< 0x00200000 */
+
+#define GPIO_CRH_MODE14_Pos (24U)
+#define GPIO_CRH_MODE14_Msk (0x3U << GPIO_CRH_MODE14_Pos) /*!< 0x03000000 */
+#define GPIO_CRH_MODE14 GPIO_CRH_MODE14_Msk /*!< MODE14[1:0] bits (Port x mode bits, pin 14) */
+#define GPIO_CRH_MODE14_0 (0x1U << GPIO_CRH_MODE14_Pos) /*!< 0x01000000 */
+#define GPIO_CRH_MODE14_1 (0x2U << GPIO_CRH_MODE14_Pos) /*!< 0x02000000 */
+
+#define GPIO_CRH_MODE15_Pos (28U)
+#define GPIO_CRH_MODE15_Msk (0x3U << GPIO_CRH_MODE15_Pos) /*!< 0x30000000 */
+#define GPIO_CRH_MODE15 GPIO_CRH_MODE15_Msk /*!< MODE15[1:0] bits (Port x mode bits, pin 15) */
+#define GPIO_CRH_MODE15_0 (0x1U << GPIO_CRH_MODE15_Pos) /*!< 0x10000000 */
+#define GPIO_CRH_MODE15_1 (0x2U << GPIO_CRH_MODE15_Pos) /*!< 0x20000000 */
+
+#define GPIO_CRH_CNF_Pos (2U)
+#define GPIO_CRH_CNF_Msk (0x33333333U << GPIO_CRH_CNF_Pos) /*!< 0xCCCCCCCC */
+#define GPIO_CRH_CNF GPIO_CRH_CNF_Msk /*!< Port x configuration bits */
+
+#define GPIO_CRH_CNF8_Pos (2U)
+#define GPIO_CRH_CNF8_Msk (0x3U << GPIO_CRH_CNF8_Pos) /*!< 0x0000000C */
+#define GPIO_CRH_CNF8 GPIO_CRH_CNF8_Msk /*!< CNF8[1:0] bits (Port x configuration bits, pin 8) */
+#define GPIO_CRH_CNF8_0 (0x1U << GPIO_CRH_CNF8_Pos) /*!< 0x00000004 */
+#define GPIO_CRH_CNF8_1 (0x2U << GPIO_CRH_CNF8_Pos) /*!< 0x00000008 */
+
+#define GPIO_CRH_CNF9_Pos (6U)
+#define GPIO_CRH_CNF9_Msk (0x3U << GPIO_CRH_CNF9_Pos) /*!< 0x000000C0 */
+#define GPIO_CRH_CNF9 GPIO_CRH_CNF9_Msk /*!< CNF9[1:0] bits (Port x configuration bits, pin 9) */
+#define GPIO_CRH_CNF9_0 (0x1U << GPIO_CRH_CNF9_Pos) /*!< 0x00000040 */
+#define GPIO_CRH_CNF9_1 (0x2U << GPIO_CRH_CNF9_Pos) /*!< 0x00000080 */
+
+#define GPIO_CRH_CNF10_Pos (10U)
+#define GPIO_CRH_CNF10_Msk (0x3U << GPIO_CRH_CNF10_Pos) /*!< 0x00000C00 */
+#define GPIO_CRH_CNF10 GPIO_CRH_CNF10_Msk /*!< CNF10[1:0] bits (Port x configuration bits, pin 10) */
+#define GPIO_CRH_CNF10_0 (0x1U << GPIO_CRH_CNF10_Pos) /*!< 0x00000400 */
+#define GPIO_CRH_CNF10_1 (0x2U << GPIO_CRH_CNF10_Pos) /*!< 0x00000800 */
+
+#define GPIO_CRH_CNF11_Pos (14U)
+#define GPIO_CRH_CNF11_Msk (0x3U << GPIO_CRH_CNF11_Pos) /*!< 0x0000C000 */
+#define GPIO_CRH_CNF11 GPIO_CRH_CNF11_Msk /*!< CNF11[1:0] bits (Port x configuration bits, pin 11) */
+#define GPIO_CRH_CNF11_0 (0x1U << GPIO_CRH_CNF11_Pos) /*!< 0x00004000 */
+#define GPIO_CRH_CNF11_1 (0x2U << GPIO_CRH_CNF11_Pos) /*!< 0x00008000 */
+
+#define GPIO_CRH_CNF12_Pos (18U)
+#define GPIO_CRH_CNF12_Msk (0x3U << GPIO_CRH_CNF12_Pos) /*!< 0x000C0000 */
+#define GPIO_CRH_CNF12 GPIO_CRH_CNF12_Msk /*!< CNF12[1:0] bits (Port x configuration bits, pin 12) */
+#define GPIO_CRH_CNF12_0 (0x1U << GPIO_CRH_CNF12_Pos) /*!< 0x00040000 */
+#define GPIO_CRH_CNF12_1 (0x2U << GPIO_CRH_CNF12_Pos) /*!< 0x00080000 */
+
+#define GPIO_CRH_CNF13_Pos (22U)
+#define GPIO_CRH_CNF13_Msk (0x3U << GPIO_CRH_CNF13_Pos) /*!< 0x00C00000 */
+#define GPIO_CRH_CNF13 GPIO_CRH_CNF13_Msk /*!< CNF13[1:0] bits (Port x configuration bits, pin 13) */
+#define GPIO_CRH_CNF13_0 (0x1U << GPIO_CRH_CNF13_Pos) /*!< 0x00400000 */
+#define GPIO_CRH_CNF13_1 (0x2U << GPIO_CRH_CNF13_Pos) /*!< 0x00800000 */
+
+#define GPIO_CRH_CNF14_Pos (26U)
+#define GPIO_CRH_CNF14_Msk (0x3U << GPIO_CRH_CNF14_Pos) /*!< 0x0C000000 */
+#define GPIO_CRH_CNF14 GPIO_CRH_CNF14_Msk /*!< CNF14[1:0] bits (Port x configuration bits, pin 14) */
+#define GPIO_CRH_CNF14_0 (0x1U << GPIO_CRH_CNF14_Pos) /*!< 0x04000000 */
+#define GPIO_CRH_CNF14_1 (0x2U << GPIO_CRH_CNF14_Pos) /*!< 0x08000000 */
+
+#define GPIO_CRH_CNF15_Pos (30U)
+#define GPIO_CRH_CNF15_Msk (0x3U << GPIO_CRH_CNF15_Pos) /*!< 0xC0000000 */
+#define GPIO_CRH_CNF15 GPIO_CRH_CNF15_Msk /*!< CNF15[1:0] bits (Port x configuration bits, pin 15) */
+#define GPIO_CRH_CNF15_0 (0x1U << GPIO_CRH_CNF15_Pos) /*!< 0x40000000 */
+#define GPIO_CRH_CNF15_1 (0x2U << GPIO_CRH_CNF15_Pos) /*!< 0x80000000 */
+
+/*!<****************** Bit definition for GPIO_IDR register *******************/
+#define GPIO_IDR_IDR0_Pos (0U)
+#define GPIO_IDR_IDR0_Msk (0x1U << GPIO_IDR_IDR0_Pos) /*!< 0x00000001 */
+#define GPIO_IDR_IDR0 GPIO_IDR_IDR0_Msk /*!< Port input data, bit 0 */
+#define GPIO_IDR_IDR1_Pos (1U)
+#define GPIO_IDR_IDR1_Msk (0x1U << GPIO_IDR_IDR1_Pos) /*!< 0x00000002 */
+#define GPIO_IDR_IDR1 GPIO_IDR_IDR1_Msk /*!< Port input data, bit 1 */
+#define GPIO_IDR_IDR2_Pos (2U)
+#define GPIO_IDR_IDR2_Msk (0x1U << GPIO_IDR_IDR2_Pos) /*!< 0x00000004 */
+#define GPIO_IDR_IDR2 GPIO_IDR_IDR2_Msk /*!< Port input data, bit 2 */
+#define GPIO_IDR_IDR3_Pos (3U)
+#define GPIO_IDR_IDR3_Msk (0x1U << GPIO_IDR_IDR3_Pos) /*!< 0x00000008 */
+#define GPIO_IDR_IDR3 GPIO_IDR_IDR3_Msk /*!< Port input data, bit 3 */
+#define GPIO_IDR_IDR4_Pos (4U)
+#define GPIO_IDR_IDR4_Msk (0x1U << GPIO_IDR_IDR4_Pos) /*!< 0x00000010 */
+#define GPIO_IDR_IDR4 GPIO_IDR_IDR4_Msk /*!< Port input data, bit 4 */
+#define GPIO_IDR_IDR5_Pos (5U)
+#define GPIO_IDR_IDR5_Msk (0x1U << GPIO_IDR_IDR5_Pos) /*!< 0x00000020 */
+#define GPIO_IDR_IDR5 GPIO_IDR_IDR5_Msk /*!< Port input data, bit 5 */
+#define GPIO_IDR_IDR6_Pos (6U)
+#define GPIO_IDR_IDR6_Msk (0x1U << GPIO_IDR_IDR6_Pos) /*!< 0x00000040 */
+#define GPIO_IDR_IDR6 GPIO_IDR_IDR6_Msk /*!< Port input data, bit 6 */
+#define GPIO_IDR_IDR7_Pos (7U)
+#define GPIO_IDR_IDR7_Msk (0x1U << GPIO_IDR_IDR7_Pos) /*!< 0x00000080 */
+#define GPIO_IDR_IDR7 GPIO_IDR_IDR7_Msk /*!< Port input data, bit 7 */
+#define GPIO_IDR_IDR8_Pos (8U)
+#define GPIO_IDR_IDR8_Msk (0x1U << GPIO_IDR_IDR8_Pos) /*!< 0x00000100 */
+#define GPIO_IDR_IDR8 GPIO_IDR_IDR8_Msk /*!< Port input data, bit 8 */
+#define GPIO_IDR_IDR9_Pos (9U)
+#define GPIO_IDR_IDR9_Msk (0x1U << GPIO_IDR_IDR9_Pos) /*!< 0x00000200 */
+#define GPIO_IDR_IDR9 GPIO_IDR_IDR9_Msk /*!< Port input data, bit 9 */
+#define GPIO_IDR_IDR10_Pos (10U)
+#define GPIO_IDR_IDR10_Msk (0x1U << GPIO_IDR_IDR10_Pos) /*!< 0x00000400 */
+#define GPIO_IDR_IDR10 GPIO_IDR_IDR10_Msk /*!< Port input data, bit 10 */
+#define GPIO_IDR_IDR11_Pos (11U)
+#define GPIO_IDR_IDR11_Msk (0x1U << GPIO_IDR_IDR11_Pos) /*!< 0x00000800 */
+#define GPIO_IDR_IDR11 GPIO_IDR_IDR11_Msk /*!< Port input data, bit 11 */
+#define GPIO_IDR_IDR12_Pos (12U)
+#define GPIO_IDR_IDR12_Msk (0x1U << GPIO_IDR_IDR12_Pos) /*!< 0x00001000 */
+#define GPIO_IDR_IDR12 GPIO_IDR_IDR12_Msk /*!< Port input data, bit 12 */
+#define GPIO_IDR_IDR13_Pos (13U)
+#define GPIO_IDR_IDR13_Msk (0x1U << GPIO_IDR_IDR13_Pos) /*!< 0x00002000 */
+#define GPIO_IDR_IDR13 GPIO_IDR_IDR13_Msk /*!< Port input data, bit 13 */
+#define GPIO_IDR_IDR14_Pos (14U)
+#define GPIO_IDR_IDR14_Msk (0x1U << GPIO_IDR_IDR14_Pos) /*!< 0x00004000 */
+#define GPIO_IDR_IDR14 GPIO_IDR_IDR14_Msk /*!< Port input data, bit 14 */
+#define GPIO_IDR_IDR15_Pos (15U)
+#define GPIO_IDR_IDR15_Msk (0x1U << GPIO_IDR_IDR15_Pos) /*!< 0x00008000 */
+#define GPIO_IDR_IDR15 GPIO_IDR_IDR15_Msk /*!< Port input data, bit 15 */
+
+/******************* Bit definition for GPIO_ODR register *******************/
+#define GPIO_ODR_ODR0_Pos (0U)
+#define GPIO_ODR_ODR0_Msk (0x1U << GPIO_ODR_ODR0_Pos) /*!< 0x00000001 */
+#define GPIO_ODR_ODR0 GPIO_ODR_ODR0_Msk /*!< Port output data, bit 0 */
+#define GPIO_ODR_ODR1_Pos (1U)
+#define GPIO_ODR_ODR1_Msk (0x1U << GPIO_ODR_ODR1_Pos) /*!< 0x00000002 */
+#define GPIO_ODR_ODR1 GPIO_ODR_ODR1_Msk /*!< Port output data, bit 1 */
+#define GPIO_ODR_ODR2_Pos (2U)
+#define GPIO_ODR_ODR2_Msk (0x1U << GPIO_ODR_ODR2_Pos) /*!< 0x00000004 */
+#define GPIO_ODR_ODR2 GPIO_ODR_ODR2_Msk /*!< Port output data, bit 2 */
+#define GPIO_ODR_ODR3_Pos (3U)
+#define GPIO_ODR_ODR3_Msk (0x1U << GPIO_ODR_ODR3_Pos) /*!< 0x00000008 */
+#define GPIO_ODR_ODR3 GPIO_ODR_ODR3_Msk /*!< Port output data, bit 3 */
+#define GPIO_ODR_ODR4_Pos (4U)
+#define GPIO_ODR_ODR4_Msk (0x1U << GPIO_ODR_ODR4_Pos) /*!< 0x00000010 */
+#define GPIO_ODR_ODR4 GPIO_ODR_ODR4_Msk /*!< Port output data, bit 4 */
+#define GPIO_ODR_ODR5_Pos (5U)
+#define GPIO_ODR_ODR5_Msk (0x1U << GPIO_ODR_ODR5_Pos) /*!< 0x00000020 */
+#define GPIO_ODR_ODR5 GPIO_ODR_ODR5_Msk /*!< Port output data, bit 5 */
+#define GPIO_ODR_ODR6_Pos (6U)
+#define GPIO_ODR_ODR6_Msk (0x1U << GPIO_ODR_ODR6_Pos) /*!< 0x00000040 */
+#define GPIO_ODR_ODR6 GPIO_ODR_ODR6_Msk /*!< Port output data, bit 6 */
+#define GPIO_ODR_ODR7_Pos (7U)
+#define GPIO_ODR_ODR7_Msk (0x1U << GPIO_ODR_ODR7_Pos) /*!< 0x00000080 */
+#define GPIO_ODR_ODR7 GPIO_ODR_ODR7_Msk /*!< Port output data, bit 7 */
+#define GPIO_ODR_ODR8_Pos (8U)
+#define GPIO_ODR_ODR8_Msk (0x1U << GPIO_ODR_ODR8_Pos) /*!< 0x00000100 */
+#define GPIO_ODR_ODR8 GPIO_ODR_ODR8_Msk /*!< Port output data, bit 8 */
+#define GPIO_ODR_ODR9_Pos (9U)
+#define GPIO_ODR_ODR9_Msk (0x1U << GPIO_ODR_ODR9_Pos) /*!< 0x00000200 */
+#define GPIO_ODR_ODR9 GPIO_ODR_ODR9_Msk /*!< Port output data, bit 9 */
+#define GPIO_ODR_ODR10_Pos (10U)
+#define GPIO_ODR_ODR10_Msk (0x1U << GPIO_ODR_ODR10_Pos) /*!< 0x00000400 */
+#define GPIO_ODR_ODR10 GPIO_ODR_ODR10_Msk /*!< Port output data, bit 10 */
+#define GPIO_ODR_ODR11_Pos (11U)
+#define GPIO_ODR_ODR11_Msk (0x1U << GPIO_ODR_ODR11_Pos) /*!< 0x00000800 */
+#define GPIO_ODR_ODR11 GPIO_ODR_ODR11_Msk /*!< Port output data, bit 11 */
+#define GPIO_ODR_ODR12_Pos (12U)
+#define GPIO_ODR_ODR12_Msk (0x1U << GPIO_ODR_ODR12_Pos) /*!< 0x00001000 */
+#define GPIO_ODR_ODR12 GPIO_ODR_ODR12_Msk /*!< Port output data, bit 12 */
+#define GPIO_ODR_ODR13_Pos (13U)
+#define GPIO_ODR_ODR13_Msk (0x1U << GPIO_ODR_ODR13_Pos) /*!< 0x00002000 */
+#define GPIO_ODR_ODR13 GPIO_ODR_ODR13_Msk /*!< Port output data, bit 13 */
+#define GPIO_ODR_ODR14_Pos (14U)
+#define GPIO_ODR_ODR14_Msk (0x1U << GPIO_ODR_ODR14_Pos) /*!< 0x00004000 */
+#define GPIO_ODR_ODR14 GPIO_ODR_ODR14_Msk /*!< Port output data, bit 14 */
+#define GPIO_ODR_ODR15_Pos (15U)
+#define GPIO_ODR_ODR15_Msk (0x1U << GPIO_ODR_ODR15_Pos) /*!< 0x00008000 */
+#define GPIO_ODR_ODR15 GPIO_ODR_ODR15_Msk /*!< Port output data, bit 15 */
+
+/****************** Bit definition for GPIO_BSRR register *******************/
+#define GPIO_BSRR_BS0_Pos (0U)
+#define GPIO_BSRR_BS0_Msk (0x1U << GPIO_BSRR_BS0_Pos) /*!< 0x00000001 */
+#define GPIO_BSRR_BS0 GPIO_BSRR_BS0_Msk /*!< Port x Set bit 0 */
+#define GPIO_BSRR_BS1_Pos (1U)
+#define GPIO_BSRR_BS1_Msk (0x1U << GPIO_BSRR_BS1_Pos) /*!< 0x00000002 */
+#define GPIO_BSRR_BS1 GPIO_BSRR_BS1_Msk /*!< Port x Set bit 1 */
+#define GPIO_BSRR_BS2_Pos (2U)
+#define GPIO_BSRR_BS2_Msk (0x1U << GPIO_BSRR_BS2_Pos) /*!< 0x00000004 */
+#define GPIO_BSRR_BS2 GPIO_BSRR_BS2_Msk /*!< Port x Set bit 2 */
+#define GPIO_BSRR_BS3_Pos (3U)
+#define GPIO_BSRR_BS3_Msk (0x1U << GPIO_BSRR_BS3_Pos) /*!< 0x00000008 */
+#define GPIO_BSRR_BS3 GPIO_BSRR_BS3_Msk /*!< Port x Set bit 3 */
+#define GPIO_BSRR_BS4_Pos (4U)
+#define GPIO_BSRR_BS4_Msk (0x1U << GPIO_BSRR_BS4_Pos) /*!< 0x00000010 */
+#define GPIO_BSRR_BS4 GPIO_BSRR_BS4_Msk /*!< Port x Set bit 4 */
+#define GPIO_BSRR_BS5_Pos (5U)
+#define GPIO_BSRR_BS5_Msk (0x1U << GPIO_BSRR_BS5_Pos) /*!< 0x00000020 */
+#define GPIO_BSRR_BS5 GPIO_BSRR_BS5_Msk /*!< Port x Set bit 5 */
+#define GPIO_BSRR_BS6_Pos (6U)
+#define GPIO_BSRR_BS6_Msk (0x1U << GPIO_BSRR_BS6_Pos) /*!< 0x00000040 */
+#define GPIO_BSRR_BS6 GPIO_BSRR_BS6_Msk /*!< Port x Set bit 6 */
+#define GPIO_BSRR_BS7_Pos (7U)
+#define GPIO_BSRR_BS7_Msk (0x1U << GPIO_BSRR_BS7_Pos) /*!< 0x00000080 */
+#define GPIO_BSRR_BS7 GPIO_BSRR_BS7_Msk /*!< Port x Set bit 7 */
+#define GPIO_BSRR_BS8_Pos (8U)
+#define GPIO_BSRR_BS8_Msk (0x1U << GPIO_BSRR_BS8_Pos) /*!< 0x00000100 */
+#define GPIO_BSRR_BS8 GPIO_BSRR_BS8_Msk /*!< Port x Set bit 8 */
+#define GPIO_BSRR_BS9_Pos (9U)
+#define GPIO_BSRR_BS9_Msk (0x1U << GPIO_BSRR_BS9_Pos) /*!< 0x00000200 */
+#define GPIO_BSRR_BS9 GPIO_BSRR_BS9_Msk /*!< Port x Set bit 9 */
+#define GPIO_BSRR_BS10_Pos (10U)
+#define GPIO_BSRR_BS10_Msk (0x1U << GPIO_BSRR_BS10_Pos) /*!< 0x00000400 */
+#define GPIO_BSRR_BS10 GPIO_BSRR_BS10_Msk /*!< Port x Set bit 10 */
+#define GPIO_BSRR_BS11_Pos (11U)
+#define GPIO_BSRR_BS11_Msk (0x1U << GPIO_BSRR_BS11_Pos) /*!< 0x00000800 */
+#define GPIO_BSRR_BS11 GPIO_BSRR_BS11_Msk /*!< Port x Set bit 11 */
+#define GPIO_BSRR_BS12_Pos (12U)
+#define GPIO_BSRR_BS12_Msk (0x1U << GPIO_BSRR_BS12_Pos) /*!< 0x00001000 */
+#define GPIO_BSRR_BS12 GPIO_BSRR_BS12_Msk /*!< Port x Set bit 12 */
+#define GPIO_BSRR_BS13_Pos (13U)
+#define GPIO_BSRR_BS13_Msk (0x1U << GPIO_BSRR_BS13_Pos) /*!< 0x00002000 */
+#define GPIO_BSRR_BS13 GPIO_BSRR_BS13_Msk /*!< Port x Set bit 13 */
+#define GPIO_BSRR_BS14_Pos (14U)
+#define GPIO_BSRR_BS14_Msk (0x1U << GPIO_BSRR_BS14_Pos) /*!< 0x00004000 */
+#define GPIO_BSRR_BS14 GPIO_BSRR_BS14_Msk /*!< Port x Set bit 14 */
+#define GPIO_BSRR_BS15_Pos (15U)
+#define GPIO_BSRR_BS15_Msk (0x1U << GPIO_BSRR_BS15_Pos) /*!< 0x00008000 */
+#define GPIO_BSRR_BS15 GPIO_BSRR_BS15_Msk /*!< Port x Set bit 15 */
+
+#define GPIO_BSRR_BR0_Pos (16U)
+#define GPIO_BSRR_BR0_Msk (0x1U << GPIO_BSRR_BR0_Pos) /*!< 0x00010000 */
+#define GPIO_BSRR_BR0 GPIO_BSRR_BR0_Msk /*!< Port x Reset bit 0 */
+#define GPIO_BSRR_BR1_Pos (17U)
+#define GPIO_BSRR_BR1_Msk (0x1U << GPIO_BSRR_BR1_Pos) /*!< 0x00020000 */
+#define GPIO_BSRR_BR1 GPIO_BSRR_BR1_Msk /*!< Port x Reset bit 1 */
+#define GPIO_BSRR_BR2_Pos (18U)
+#define GPIO_BSRR_BR2_Msk (0x1U << GPIO_BSRR_BR2_Pos) /*!< 0x00040000 */
+#define GPIO_BSRR_BR2 GPIO_BSRR_BR2_Msk /*!< Port x Reset bit 2 */
+#define GPIO_BSRR_BR3_Pos (19U)
+#define GPIO_BSRR_BR3_Msk (0x1U << GPIO_BSRR_BR3_Pos) /*!< 0x00080000 */
+#define GPIO_BSRR_BR3 GPIO_BSRR_BR3_Msk /*!< Port x Reset bit 3 */
+#define GPIO_BSRR_BR4_Pos (20U)
+#define GPIO_BSRR_BR4_Msk (0x1U << GPIO_BSRR_BR4_Pos) /*!< 0x00100000 */
+#define GPIO_BSRR_BR4 GPIO_BSRR_BR4_Msk /*!< Port x Reset bit 4 */
+#define GPIO_BSRR_BR5_Pos (21U)
+#define GPIO_BSRR_BR5_Msk (0x1U << GPIO_BSRR_BR5_Pos) /*!< 0x00200000 */
+#define GPIO_BSRR_BR5 GPIO_BSRR_BR5_Msk /*!< Port x Reset bit 5 */
+#define GPIO_BSRR_BR6_Pos (22U)
+#define GPIO_BSRR_BR6_Msk (0x1U << GPIO_BSRR_BR6_Pos) /*!< 0x00400000 */
+#define GPIO_BSRR_BR6 GPIO_BSRR_BR6_Msk /*!< Port x Reset bit 6 */
+#define GPIO_BSRR_BR7_Pos (23U)
+#define GPIO_BSRR_BR7_Msk (0x1U << GPIO_BSRR_BR7_Pos) /*!< 0x00800000 */
+#define GPIO_BSRR_BR7 GPIO_BSRR_BR7_Msk /*!< Port x Reset bit 7 */
+#define GPIO_BSRR_BR8_Pos (24U)
+#define GPIO_BSRR_BR8_Msk (0x1U << GPIO_BSRR_BR8_Pos) /*!< 0x01000000 */
+#define GPIO_BSRR_BR8 GPIO_BSRR_BR8_Msk /*!< Port x Reset bit 8 */
+#define GPIO_BSRR_BR9_Pos (25U)
+#define GPIO_BSRR_BR9_Msk (0x1U << GPIO_BSRR_BR9_Pos) /*!< 0x02000000 */
+#define GPIO_BSRR_BR9 GPIO_BSRR_BR9_Msk /*!< Port x Reset bit 9 */
+#define GPIO_BSRR_BR10_Pos (26U)
+#define GPIO_BSRR_BR10_Msk (0x1U << GPIO_BSRR_BR10_Pos) /*!< 0x04000000 */
+#define GPIO_BSRR_BR10 GPIO_BSRR_BR10_Msk /*!< Port x Reset bit 10 */
+#define GPIO_BSRR_BR11_Pos (27U)
+#define GPIO_BSRR_BR11_Msk (0x1U << GPIO_BSRR_BR11_Pos) /*!< 0x08000000 */
+#define GPIO_BSRR_BR11 GPIO_BSRR_BR11_Msk /*!< Port x Reset bit 11 */
+#define GPIO_BSRR_BR12_Pos (28U)
+#define GPIO_BSRR_BR12_Msk (0x1U << GPIO_BSRR_BR12_Pos) /*!< 0x10000000 */
+#define GPIO_BSRR_BR12 GPIO_BSRR_BR12_Msk /*!< Port x Reset bit 12 */
+#define GPIO_BSRR_BR13_Pos (29U)
+#define GPIO_BSRR_BR13_Msk (0x1U << GPIO_BSRR_BR13_Pos) /*!< 0x20000000 */
+#define GPIO_BSRR_BR13 GPIO_BSRR_BR13_Msk /*!< Port x Reset bit 13 */
+#define GPIO_BSRR_BR14_Pos (30U)
+#define GPIO_BSRR_BR14_Msk (0x1U << GPIO_BSRR_BR14_Pos) /*!< 0x40000000 */
+#define GPIO_BSRR_BR14 GPIO_BSRR_BR14_Msk /*!< Port x Reset bit 14 */
+#define GPIO_BSRR_BR15_Pos (31U)
+#define GPIO_BSRR_BR15_Msk (0x1U << GPIO_BSRR_BR15_Pos) /*!< 0x80000000 */
+#define GPIO_BSRR_BR15 GPIO_BSRR_BR15_Msk /*!< Port x Reset bit 15 */
+
+/******************* Bit definition for GPIO_BRR register *******************/
+#define GPIO_BRR_BR0_Pos (0U)
+#define GPIO_BRR_BR0_Msk (0x1U << GPIO_BRR_BR0_Pos) /*!< 0x00000001 */
+#define GPIO_BRR_BR0 GPIO_BRR_BR0_Msk /*!< Port x Reset bit 0 */
+#define GPIO_BRR_BR1_Pos (1U)
+#define GPIO_BRR_BR1_Msk (0x1U << GPIO_BRR_BR1_Pos) /*!< 0x00000002 */
+#define GPIO_BRR_BR1 GPIO_BRR_BR1_Msk /*!< Port x Reset bit 1 */
+#define GPIO_BRR_BR2_Pos (2U)
+#define GPIO_BRR_BR2_Msk (0x1U << GPIO_BRR_BR2_Pos) /*!< 0x00000004 */
+#define GPIO_BRR_BR2 GPIO_BRR_BR2_Msk /*!< Port x Reset bit 2 */
+#define GPIO_BRR_BR3_Pos (3U)
+#define GPIO_BRR_BR3_Msk (0x1U << GPIO_BRR_BR3_Pos) /*!< 0x00000008 */
+#define GPIO_BRR_BR3 GPIO_BRR_BR3_Msk /*!< Port x Reset bit 3 */
+#define GPIO_BRR_BR4_Pos (4U)
+#define GPIO_BRR_BR4_Msk (0x1U << GPIO_BRR_BR4_Pos) /*!< 0x00000010 */
+#define GPIO_BRR_BR4 GPIO_BRR_BR4_Msk /*!< Port x Reset bit 4 */
+#define GPIO_BRR_BR5_Pos (5U)
+#define GPIO_BRR_BR5_Msk (0x1U << GPIO_BRR_BR5_Pos) /*!< 0x00000020 */
+#define GPIO_BRR_BR5 GPIO_BRR_BR5_Msk /*!< Port x Reset bit 5 */
+#define GPIO_BRR_BR6_Pos (6U)
+#define GPIO_BRR_BR6_Msk (0x1U << GPIO_BRR_BR6_Pos) /*!< 0x00000040 */
+#define GPIO_BRR_BR6 GPIO_BRR_BR6_Msk /*!< Port x Reset bit 6 */
+#define GPIO_BRR_BR7_Pos (7U)
+#define GPIO_BRR_BR7_Msk (0x1U << GPIO_BRR_BR7_Pos) /*!< 0x00000080 */
+#define GPIO_BRR_BR7 GPIO_BRR_BR7_Msk /*!< Port x Reset bit 7 */
+#define GPIO_BRR_BR8_Pos (8U)
+#define GPIO_BRR_BR8_Msk (0x1U << GPIO_BRR_BR8_Pos) /*!< 0x00000100 */
+#define GPIO_BRR_BR8 GPIO_BRR_BR8_Msk /*!< Port x Reset bit 8 */
+#define GPIO_BRR_BR9_Pos (9U)
+#define GPIO_BRR_BR9_Msk (0x1U << GPIO_BRR_BR9_Pos) /*!< 0x00000200 */
+#define GPIO_BRR_BR9 GPIO_BRR_BR9_Msk /*!< Port x Reset bit 9 */
+#define GPIO_BRR_BR10_Pos (10U)
+#define GPIO_BRR_BR10_Msk (0x1U << GPIO_BRR_BR10_Pos) /*!< 0x00000400 */
+#define GPIO_BRR_BR10 GPIO_BRR_BR10_Msk /*!< Port x Reset bit 10 */
+#define GPIO_BRR_BR11_Pos (11U)
+#define GPIO_BRR_BR11_Msk (0x1U << GPIO_BRR_BR11_Pos) /*!< 0x00000800 */
+#define GPIO_BRR_BR11 GPIO_BRR_BR11_Msk /*!< Port x Reset bit 11 */
+#define GPIO_BRR_BR12_Pos (12U)
+#define GPIO_BRR_BR12_Msk (0x1U << GPIO_BRR_BR12_Pos) /*!< 0x00001000 */
+#define GPIO_BRR_BR12 GPIO_BRR_BR12_Msk /*!< Port x Reset bit 12 */
+#define GPIO_BRR_BR13_Pos (13U)
+#define GPIO_BRR_BR13_Msk (0x1U << GPIO_BRR_BR13_Pos) /*!< 0x00002000 */
+#define GPIO_BRR_BR13 GPIO_BRR_BR13_Msk /*!< Port x Reset bit 13 */
+#define GPIO_BRR_BR14_Pos (14U)
+#define GPIO_BRR_BR14_Msk (0x1U << GPIO_BRR_BR14_Pos) /*!< 0x00004000 */
+#define GPIO_BRR_BR14 GPIO_BRR_BR14_Msk /*!< Port x Reset bit 14 */
+#define GPIO_BRR_BR15_Pos (15U)
+#define GPIO_BRR_BR15_Msk (0x1U << GPIO_BRR_BR15_Pos) /*!< 0x00008000 */
+#define GPIO_BRR_BR15 GPIO_BRR_BR15_Msk /*!< Port x Reset bit 15 */
+
+/****************** Bit definition for GPIO_LCKR register *******************/
+#define GPIO_LCKR_LCK0_Pos (0U)
+#define GPIO_LCKR_LCK0_Msk (0x1U << GPIO_LCKR_LCK0_Pos) /*!< 0x00000001 */
+#define GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk /*!< Port x Lock bit 0 */
+#define GPIO_LCKR_LCK1_Pos (1U)
+#define GPIO_LCKR_LCK1_Msk (0x1U << GPIO_LCKR_LCK1_Pos) /*!< 0x00000002 */
+#define GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk /*!< Port x Lock bit 1 */
+#define GPIO_LCKR_LCK2_Pos (2U)
+#define GPIO_LCKR_LCK2_Msk (0x1U << GPIO_LCKR_LCK2_Pos) /*!< 0x00000004 */
+#define GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk /*!< Port x Lock bit 2 */
+#define GPIO_LCKR_LCK3_Pos (3U)
+#define GPIO_LCKR_LCK3_Msk (0x1U << GPIO_LCKR_LCK3_Pos) /*!< 0x00000008 */
+#define GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk /*!< Port x Lock bit 3 */
+#define GPIO_LCKR_LCK4_Pos (4U)
+#define GPIO_LCKR_LCK4_Msk (0x1U << GPIO_LCKR_LCK4_Pos) /*!< 0x00000010 */
+#define GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk /*!< Port x Lock bit 4 */
+#define GPIO_LCKR_LCK5_Pos (5U)
+#define GPIO_LCKR_LCK5_Msk (0x1U << GPIO_LCKR_LCK5_Pos) /*!< 0x00000020 */
+#define GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk /*!< Port x Lock bit 5 */
+#define GPIO_LCKR_LCK6_Pos (6U)
+#define GPIO_LCKR_LCK6_Msk (0x1U << GPIO_LCKR_LCK6_Pos) /*!< 0x00000040 */
+#define GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk /*!< Port x Lock bit 6 */
+#define GPIO_LCKR_LCK7_Pos (7U)
+#define GPIO_LCKR_LCK7_Msk (0x1U << GPIO_LCKR_LCK7_Pos) /*!< 0x00000080 */
+#define GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk /*!< Port x Lock bit 7 */
+#define GPIO_LCKR_LCK8_Pos (8U)
+#define GPIO_LCKR_LCK8_Msk (0x1U << GPIO_LCKR_LCK8_Pos) /*!< 0x00000100 */
+#define GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk /*!< Port x Lock bit 8 */
+#define GPIO_LCKR_LCK9_Pos (9U)
+#define GPIO_LCKR_LCK9_Msk (0x1U << GPIO_LCKR_LCK9_Pos) /*!< 0x00000200 */
+#define GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk /*!< Port x Lock bit 9 */
+#define GPIO_LCKR_LCK10_Pos (10U)
+#define GPIO_LCKR_LCK10_Msk (0x1U << GPIO_LCKR_LCK10_Pos) /*!< 0x00000400 */
+#define GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk /*!< Port x Lock bit 10 */
+#define GPIO_LCKR_LCK11_Pos (11U)
+#define GPIO_LCKR_LCK11_Msk (0x1U << GPIO_LCKR_LCK11_Pos) /*!< 0x00000800 */
+#define GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk /*!< Port x Lock bit 11 */
+#define GPIO_LCKR_LCK12_Pos (12U)
+#define GPIO_LCKR_LCK12_Msk (0x1U << GPIO_LCKR_LCK12_Pos) /*!< 0x00001000 */
+#define GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk /*!< Port x Lock bit 12 */
+#define GPIO_LCKR_LCK13_Pos (13U)
+#define GPIO_LCKR_LCK13_Msk (0x1U << GPIO_LCKR_LCK13_Pos) /*!< 0x00002000 */
+#define GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk /*!< Port x Lock bit 13 */
+#define GPIO_LCKR_LCK14_Pos (14U)
+#define GPIO_LCKR_LCK14_Msk (0x1U << GPIO_LCKR_LCK14_Pos) /*!< 0x00004000 */
+#define GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk /*!< Port x Lock bit 14 */
+#define GPIO_LCKR_LCK15_Pos (15U)
+#define GPIO_LCKR_LCK15_Msk (0x1U << GPIO_LCKR_LCK15_Pos) /*!< 0x00008000 */
+#define GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk /*!< Port x Lock bit 15 */
+#define GPIO_LCKR_LCKK_Pos (16U)
+#define GPIO_LCKR_LCKK_Msk (0x1U << GPIO_LCKR_LCKK_Pos) /*!< 0x00010000 */
+#define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk /*!< Lock key */
+
+/*----------------------------------------------------------------------------*/
+
+/****************** Bit definition for AFIO_EVCR register *******************/
+#define AFIO_EVCR_PIN_Pos (0U)
+#define AFIO_EVCR_PIN_Msk (0xFU << AFIO_EVCR_PIN_Pos) /*!< 0x0000000F */
+#define AFIO_EVCR_PIN AFIO_EVCR_PIN_Msk /*!< PIN[3:0] bits (Pin selection) */
+#define AFIO_EVCR_PIN_0 (0x1U << AFIO_EVCR_PIN_Pos) /*!< 0x00000001 */
+#define AFIO_EVCR_PIN_1 (0x2U << AFIO_EVCR_PIN_Pos) /*!< 0x00000002 */
+#define AFIO_EVCR_PIN_2 (0x4U << AFIO_EVCR_PIN_Pos) /*!< 0x00000004 */
+#define AFIO_EVCR_PIN_3 (0x8U << AFIO_EVCR_PIN_Pos) /*!< 0x00000008 */
+
+/*!< PIN configuration */
+#define AFIO_EVCR_PIN_PX0 ((uint32_t)0x00000000) /*!< Pin 0 selected */
+#define AFIO_EVCR_PIN_PX1_Pos (0U)
+#define AFIO_EVCR_PIN_PX1_Msk (0x1U << AFIO_EVCR_PIN_PX1_Pos) /*!< 0x00000001 */
+#define AFIO_EVCR_PIN_PX1 AFIO_EVCR_PIN_PX1_Msk /*!< Pin 1 selected */
+#define AFIO_EVCR_PIN_PX2_Pos (1U)
+#define AFIO_EVCR_PIN_PX2_Msk (0x1U << AFIO_EVCR_PIN_PX2_Pos) /*!< 0x00000002 */
+#define AFIO_EVCR_PIN_PX2 AFIO_EVCR_PIN_PX2_Msk /*!< Pin 2 selected */
+#define AFIO_EVCR_PIN_PX3_Pos (0U)
+#define AFIO_EVCR_PIN_PX3_Msk (0x3U << AFIO_EVCR_PIN_PX3_Pos) /*!< 0x00000003 */
+#define AFIO_EVCR_PIN_PX3 AFIO_EVCR_PIN_PX3_Msk /*!< Pin 3 selected */
+#define AFIO_EVCR_PIN_PX4_Pos (2U)
+#define AFIO_EVCR_PIN_PX4_Msk (0x1U << AFIO_EVCR_PIN_PX4_Pos) /*!< 0x00000004 */
+#define AFIO_EVCR_PIN_PX4 AFIO_EVCR_PIN_PX4_Msk /*!< Pin 4 selected */
+#define AFIO_EVCR_PIN_PX5_Pos (0U)
+#define AFIO_EVCR_PIN_PX5_Msk (0x5U << AFIO_EVCR_PIN_PX5_Pos) /*!< 0x00000005 */
+#define AFIO_EVCR_PIN_PX5 AFIO_EVCR_PIN_PX5_Msk /*!< Pin 5 selected */
+#define AFIO_EVCR_PIN_PX6_Pos (1U)
+#define AFIO_EVCR_PIN_PX6_Msk (0x3U << AFIO_EVCR_PIN_PX6_Pos) /*!< 0x00000006 */
+#define AFIO_EVCR_PIN_PX6 AFIO_EVCR_PIN_PX6_Msk /*!< Pin 6 selected */
+#define AFIO_EVCR_PIN_PX7_Pos (0U)
+#define AFIO_EVCR_PIN_PX7_Msk (0x7U << AFIO_EVCR_PIN_PX7_Pos) /*!< 0x00000007 */
+#define AFIO_EVCR_PIN_PX7 AFIO_EVCR_PIN_PX7_Msk /*!< Pin 7 selected */
+#define AFIO_EVCR_PIN_PX8_Pos (3U)
+#define AFIO_EVCR_PIN_PX8_Msk (0x1U << AFIO_EVCR_PIN_PX8_Pos) /*!< 0x00000008 */
+#define AFIO_EVCR_PIN_PX8 AFIO_EVCR_PIN_PX8_Msk /*!< Pin 8 selected */
+#define AFIO_EVCR_PIN_PX9_Pos (0U)
+#define AFIO_EVCR_PIN_PX9_Msk (0x9U << AFIO_EVCR_PIN_PX9_Pos) /*!< 0x00000009 */
+#define AFIO_EVCR_PIN_PX9 AFIO_EVCR_PIN_PX9_Msk /*!< Pin 9 selected */
+#define AFIO_EVCR_PIN_PX10_Pos (1U)
+#define AFIO_EVCR_PIN_PX10_Msk (0x5U << AFIO_EVCR_PIN_PX10_Pos) /*!< 0x0000000A */
+#define AFIO_EVCR_PIN_PX10 AFIO_EVCR_PIN_PX10_Msk /*!< Pin 10 selected */
+#define AFIO_EVCR_PIN_PX11_Pos (0U)
+#define AFIO_EVCR_PIN_PX11_Msk (0xBU << AFIO_EVCR_PIN_PX11_Pos) /*!< 0x0000000B */
+#define AFIO_EVCR_PIN_PX11 AFIO_EVCR_PIN_PX11_Msk /*!< Pin 11 selected */
+#define AFIO_EVCR_PIN_PX12_Pos (2U)
+#define AFIO_EVCR_PIN_PX12_Msk (0x3U << AFIO_EVCR_PIN_PX12_Pos) /*!< 0x0000000C */
+#define AFIO_EVCR_PIN_PX12 AFIO_EVCR_PIN_PX12_Msk /*!< Pin 12 selected */
+#define AFIO_EVCR_PIN_PX13_Pos (0U)
+#define AFIO_EVCR_PIN_PX13_Msk (0xDU << AFIO_EVCR_PIN_PX13_Pos) /*!< 0x0000000D */
+#define AFIO_EVCR_PIN_PX13 AFIO_EVCR_PIN_PX13_Msk /*!< Pin 13 selected */
+#define AFIO_EVCR_PIN_PX14_Pos (1U)
+#define AFIO_EVCR_PIN_PX14_Msk (0x7U << AFIO_EVCR_PIN_PX14_Pos) /*!< 0x0000000E */
+#define AFIO_EVCR_PIN_PX14 AFIO_EVCR_PIN_PX14_Msk /*!< Pin 14 selected */
+#define AFIO_EVCR_PIN_PX15_Pos (0U)
+#define AFIO_EVCR_PIN_PX15_Msk (0xFU << AFIO_EVCR_PIN_PX15_Pos) /*!< 0x0000000F */
+#define AFIO_EVCR_PIN_PX15 AFIO_EVCR_PIN_PX15_Msk /*!< Pin 15 selected */
+
+#define AFIO_EVCR_PORT_Pos (4U)
+#define AFIO_EVCR_PORT_Msk (0x7U << AFIO_EVCR_PORT_Pos) /*!< 0x00000070 */
+#define AFIO_EVCR_PORT AFIO_EVCR_PORT_Msk /*!< PORT[2:0] bits (Port selection) */
+#define AFIO_EVCR_PORT_0 (0x1U << AFIO_EVCR_PORT_Pos) /*!< 0x00000010 */
+#define AFIO_EVCR_PORT_1 (0x2U << AFIO_EVCR_PORT_Pos) /*!< 0x00000020 */
+#define AFIO_EVCR_PORT_2 (0x4U << AFIO_EVCR_PORT_Pos) /*!< 0x00000040 */
+
+/*!< PORT configuration */
+#define AFIO_EVCR_PORT_PA ((uint32_t)0x00000000) /*!< Port A selected */
+#define AFIO_EVCR_PORT_PB_Pos (4U)
+#define AFIO_EVCR_PORT_PB_Msk (0x1U << AFIO_EVCR_PORT_PB_Pos) /*!< 0x00000010 */
+#define AFIO_EVCR_PORT_PB AFIO_EVCR_PORT_PB_Msk /*!< Port B selected */
+#define AFIO_EVCR_PORT_PC_Pos (5U)
+#define AFIO_EVCR_PORT_PC_Msk (0x1U << AFIO_EVCR_PORT_PC_Pos) /*!< 0x00000020 */
+#define AFIO_EVCR_PORT_PC AFIO_EVCR_PORT_PC_Msk /*!< Port C selected */
+#define AFIO_EVCR_PORT_PD_Pos (4U)
+#define AFIO_EVCR_PORT_PD_Msk (0x3U << AFIO_EVCR_PORT_PD_Pos) /*!< 0x00000030 */
+#define AFIO_EVCR_PORT_PD AFIO_EVCR_PORT_PD_Msk /*!< Port D selected */
+#define AFIO_EVCR_PORT_PE_Pos (6U)
+#define AFIO_EVCR_PORT_PE_Msk (0x1U << AFIO_EVCR_PORT_PE_Pos) /*!< 0x00000040 */
+#define AFIO_EVCR_PORT_PE AFIO_EVCR_PORT_PE_Msk /*!< Port E selected */
+
+#define AFIO_EVCR_EVOE_Pos (7U)
+#define AFIO_EVCR_EVOE_Msk (0x1U << AFIO_EVCR_EVOE_Pos) /*!< 0x00000080 */
+#define AFIO_EVCR_EVOE AFIO_EVCR_EVOE_Msk /*!< Event Output Enable */
+
+/****************** Bit definition for AFIO_MAPR register *******************/
+#define AFIO_MAPR_SPI1_REMAP_Pos (0U)
+#define AFIO_MAPR_SPI1_REMAP_Msk (0x1U << AFIO_MAPR_SPI1_REMAP_Pos) /*!< 0x00000001 */
+#define AFIO_MAPR_SPI1_REMAP AFIO_MAPR_SPI1_REMAP_Msk /*!< SPI1 remapping */
+#define AFIO_MAPR_I2C1_REMAP_Pos (1U)
+#define AFIO_MAPR_I2C1_REMAP_Msk (0x1U << AFIO_MAPR_I2C1_REMAP_Pos) /*!< 0x00000002 */
+#define AFIO_MAPR_I2C1_REMAP AFIO_MAPR_I2C1_REMAP_Msk /*!< I2C1 remapping */
+#define AFIO_MAPR_USART1_REMAP_Pos (2U)
+#define AFIO_MAPR_USART1_REMAP_Msk (0x1U << AFIO_MAPR_USART1_REMAP_Pos) /*!< 0x00000004 */
+#define AFIO_MAPR_USART1_REMAP AFIO_MAPR_USART1_REMAP_Msk /*!< USART1 remapping */
+#define AFIO_MAPR_USART2_REMAP_Pos (3U)
+#define AFIO_MAPR_USART2_REMAP_Msk (0x1U << AFIO_MAPR_USART2_REMAP_Pos) /*!< 0x00000008 */
+#define AFIO_MAPR_USART2_REMAP AFIO_MAPR_USART2_REMAP_Msk /*!< USART2 remapping */
+
+#define AFIO_MAPR_USART3_REMAP_Pos (4U)
+#define AFIO_MAPR_USART3_REMAP_Msk (0x3U << AFIO_MAPR_USART3_REMAP_Pos) /*!< 0x00000030 */
+#define AFIO_MAPR_USART3_REMAP AFIO_MAPR_USART3_REMAP_Msk /*!< USART3_REMAP[1:0] bits (USART3 remapping) */
+#define AFIO_MAPR_USART3_REMAP_0 (0x1U << AFIO_MAPR_USART3_REMAP_Pos) /*!< 0x00000010 */
+#define AFIO_MAPR_USART3_REMAP_1 (0x2U << AFIO_MAPR_USART3_REMAP_Pos) /*!< 0x00000020 */
+
+/* USART3_REMAP configuration */
+#define AFIO_MAPR_USART3_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14) */
+#define AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Pos (4U)
+#define AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Msk (0x1U << AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Pos) /*!< 0x00000010 */
+#define AFIO_MAPR_USART3_REMAP_PARTIALREMAP AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Msk /*!< Partial remap (TX/PC10, RX/PC11, CK/PC12, CTS/PB13, RTS/PB14) */
+#define AFIO_MAPR_USART3_REMAP_FULLREMAP_Pos (4U)
+#define AFIO_MAPR_USART3_REMAP_FULLREMAP_Msk (0x3U << AFIO_MAPR_USART3_REMAP_FULLREMAP_Pos) /*!< 0x00000030 */
+#define AFIO_MAPR_USART3_REMAP_FULLREMAP AFIO_MAPR_USART3_REMAP_FULLREMAP_Msk /*!< Full remap (TX/PD8, RX/PD9, CK/PD10, CTS/PD11, RTS/PD12) */
+
+#define AFIO_MAPR_TIM1_REMAP_Pos (6U)
+#define AFIO_MAPR_TIM1_REMAP_Msk (0x3U << AFIO_MAPR_TIM1_REMAP_Pos) /*!< 0x000000C0 */
+#define AFIO_MAPR_TIM1_REMAP AFIO_MAPR_TIM1_REMAP_Msk /*!< TIM1_REMAP[1:0] bits (TIM1 remapping) */
+#define AFIO_MAPR_TIM1_REMAP_0 (0x1U << AFIO_MAPR_TIM1_REMAP_Pos) /*!< 0x00000040 */
+#define AFIO_MAPR_TIM1_REMAP_1 (0x2U << AFIO_MAPR_TIM1_REMAP_Pos) /*!< 0x00000080 */
+
+/*!< TIM1_REMAP configuration */
+#define AFIO_MAPR_TIM1_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15) */
+#define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Pos (6U)
+#define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Msk (0x1U << AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Pos) /*!< 0x00000040 */
+#define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Msk /*!< Partial remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PA6, CH1N/PA7, CH2N/PB0, CH3N/PB1) */
+#define AFIO_MAPR_TIM1_REMAP_FULLREMAP_Pos (6U)
+#define AFIO_MAPR_TIM1_REMAP_FULLREMAP_Msk (0x3U << AFIO_MAPR_TIM1_REMAP_FULLREMAP_Pos) /*!< 0x000000C0 */
+#define AFIO_MAPR_TIM1_REMAP_FULLREMAP AFIO_MAPR_TIM1_REMAP_FULLREMAP_Msk /*!< Full remap (ETR/PE7, CH1/PE9, CH2/PE11, CH3/PE13, CH4/PE14, BKIN/PE15, CH1N/PE8, CH2N/PE10, CH3N/PE12) */
+
+#define AFIO_MAPR_TIM2_REMAP_Pos (8U)
+#define AFIO_MAPR_TIM2_REMAP_Msk (0x3U << AFIO_MAPR_TIM2_REMAP_Pos) /*!< 0x00000300 */
+#define AFIO_MAPR_TIM2_REMAP AFIO_MAPR_TIM2_REMAP_Msk /*!< TIM2_REMAP[1:0] bits (TIM2 remapping) */
+#define AFIO_MAPR_TIM2_REMAP_0 (0x1U << AFIO_MAPR_TIM2_REMAP_Pos) /*!< 0x00000100 */
+#define AFIO_MAPR_TIM2_REMAP_1 (0x2U << AFIO_MAPR_TIM2_REMAP_Pos) /*!< 0x00000200 */
+
+/*!< TIM2_REMAP configuration */
+#define AFIO_MAPR_TIM2_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3) */
+#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Pos (8U)
+#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Msk (0x1U << AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Pos) /*!< 0x00000100 */
+#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1 AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Msk /*!< Partial remap (CH1/ETR/PA15, CH2/PB3, CH3/PA2, CH4/PA3) */
+#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2_Pos (9U)
+#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2_Msk (0x1U << AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2_Pos) /*!< 0x00000200 */
+#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2 AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2_Msk /*!< Partial remap (CH1/ETR/PA0, CH2/PA1, CH3/PB10, CH4/PB11) */
+#define AFIO_MAPR_TIM2_REMAP_FULLREMAP_Pos (8U)
+#define AFIO_MAPR_TIM2_REMAP_FULLREMAP_Msk (0x3U << AFIO_MAPR_TIM2_REMAP_FULLREMAP_Pos) /*!< 0x00000300 */
+#define AFIO_MAPR_TIM2_REMAP_FULLREMAP AFIO_MAPR_TIM2_REMAP_FULLREMAP_Msk /*!< Full remap (CH1/ETR/PA15, CH2/PB3, CH3/PB10, CH4/PB11) */
+
+#define AFIO_MAPR_TIM3_REMAP_Pos (10U)
+#define AFIO_MAPR_TIM3_REMAP_Msk (0x3U << AFIO_MAPR_TIM3_REMAP_Pos) /*!< 0x00000C00 */
+#define AFIO_MAPR_TIM3_REMAP AFIO_MAPR_TIM3_REMAP_Msk /*!< TIM3_REMAP[1:0] bits (TIM3 remapping) */
+#define AFIO_MAPR_TIM3_REMAP_0 (0x1U << AFIO_MAPR_TIM3_REMAP_Pos) /*!< 0x00000400 */
+#define AFIO_MAPR_TIM3_REMAP_1 (0x2U << AFIO_MAPR_TIM3_REMAP_Pos) /*!< 0x00000800 */
+
+/*!< TIM3_REMAP configuration */
+#define AFIO_MAPR_TIM3_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1) */
+#define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Pos (11U)
+#define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Msk (0x1U << AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Pos) /*!< 0x00000800 */
+#define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Msk /*!< Partial remap (CH1/PB4, CH2/PB5, CH3/PB0, CH4/PB1) */
+#define AFIO_MAPR_TIM3_REMAP_FULLREMAP_Pos (10U)
+#define AFIO_MAPR_TIM3_REMAP_FULLREMAP_Msk (0x3U << AFIO_MAPR_TIM3_REMAP_FULLREMAP_Pos) /*!< 0x00000C00 */
+#define AFIO_MAPR_TIM3_REMAP_FULLREMAP AFIO_MAPR_TIM3_REMAP_FULLREMAP_Msk /*!< Full remap (CH1/PC6, CH2/PC7, CH3/PC8, CH4/PC9) */
+
+#define AFIO_MAPR_TIM4_REMAP_Pos (12U)
+#define AFIO_MAPR_TIM4_REMAP_Msk (0x1U << AFIO_MAPR_TIM4_REMAP_Pos) /*!< 0x00001000 */
+#define AFIO_MAPR_TIM4_REMAP AFIO_MAPR_TIM4_REMAP_Msk /*!< TIM4_REMAP bit (TIM4 remapping) */
+
+#define AFIO_MAPR_CAN_REMAP_Pos (13U)
+#define AFIO_MAPR_CAN_REMAP_Msk (0x3U << AFIO_MAPR_CAN_REMAP_Pos) /*!< 0x00006000 */
+#define AFIO_MAPR_CAN_REMAP AFIO_MAPR_CAN_REMAP_Msk /*!< CAN_REMAP[1:0] bits (CAN Alternate function remapping) */
+#define AFIO_MAPR_CAN_REMAP_0 (0x1U << AFIO_MAPR_CAN_REMAP_Pos) /*!< 0x00002000 */
+#define AFIO_MAPR_CAN_REMAP_1 (0x2U << AFIO_MAPR_CAN_REMAP_Pos) /*!< 0x00004000 */
+
+/*!< CAN_REMAP configuration */
+#define AFIO_MAPR_CAN_REMAP_REMAP1 ((uint32_t)0x00000000) /*!< CANRX mapped to PA11, CANTX mapped to PA12 */
+#define AFIO_MAPR_CAN_REMAP_REMAP2_Pos (14U)
+#define AFIO_MAPR_CAN_REMAP_REMAP2_Msk (0x1U << AFIO_MAPR_CAN_REMAP_REMAP2_Pos) /*!< 0x00004000 */
+#define AFIO_MAPR_CAN_REMAP_REMAP2 AFIO_MAPR_CAN_REMAP_REMAP2_Msk /*!< CANRX mapped to PB8, CANTX mapped to PB9 */
+#define AFIO_MAPR_CAN_REMAP_REMAP3_Pos (13U)
+#define AFIO_MAPR_CAN_REMAP_REMAP3_Msk (0x3U << AFIO_MAPR_CAN_REMAP_REMAP3_Pos) /*!< 0x00006000 */
+#define AFIO_MAPR_CAN_REMAP_REMAP3 AFIO_MAPR_CAN_REMAP_REMAP3_Msk /*!< CANRX mapped to PD0, CANTX mapped to PD1 */
+
+#define AFIO_MAPR_PD01_REMAP_Pos (15U)
+#define AFIO_MAPR_PD01_REMAP_Msk (0x1U << AFIO_MAPR_PD01_REMAP_Pos) /*!< 0x00008000 */
+#define AFIO_MAPR_PD01_REMAP AFIO_MAPR_PD01_REMAP_Msk /*!< Port D0/Port D1 mapping on OSC_IN/OSC_OUT */
+#define AFIO_MAPR_TIM5CH4_IREMAP_Pos (16U)
+#define AFIO_MAPR_TIM5CH4_IREMAP_Msk (0x1U << AFIO_MAPR_TIM5CH4_IREMAP_Pos) /*!< 0x00010000 */
+#define AFIO_MAPR_TIM5CH4_IREMAP AFIO_MAPR_TIM5CH4_IREMAP_Msk /*!< TIM5 Channel4 Internal Remap */
+
+/*!< SWJ_CFG configuration */
+#define AFIO_MAPR_SWJ_CFG_Pos (24U)
+#define AFIO_MAPR_SWJ_CFG_Msk (0x7U << AFIO_MAPR_SWJ_CFG_Pos) /*!< 0x07000000 */
+#define AFIO_MAPR_SWJ_CFG AFIO_MAPR_SWJ_CFG_Msk /*!< SWJ_CFG[2:0] bits (Serial Wire JTAG configuration) */
+#define AFIO_MAPR_SWJ_CFG_0 (0x1U << AFIO_MAPR_SWJ_CFG_Pos) /*!< 0x01000000 */
+#define AFIO_MAPR_SWJ_CFG_1 (0x2U << AFIO_MAPR_SWJ_CFG_Pos) /*!< 0x02000000 */
+#define AFIO_MAPR_SWJ_CFG_2 (0x4U << AFIO_MAPR_SWJ_CFG_Pos) /*!< 0x04000000 */
+
+#define AFIO_MAPR_SWJ_CFG_RESET ((uint32_t)0x00000000) /*!< Full SWJ (JTAG-DP + SW-DP) : Reset State */
+#define AFIO_MAPR_SWJ_CFG_NOJNTRST_Pos (24U)
+#define AFIO_MAPR_SWJ_CFG_NOJNTRST_Msk (0x1U << AFIO_MAPR_SWJ_CFG_NOJNTRST_Pos) /*!< 0x01000000 */
+#define AFIO_MAPR_SWJ_CFG_NOJNTRST AFIO_MAPR_SWJ_CFG_NOJNTRST_Msk /*!< Full SWJ (JTAG-DP + SW-DP) but without JNTRST */
+#define AFIO_MAPR_SWJ_CFG_JTAGDISABLE_Pos (25U)
+#define AFIO_MAPR_SWJ_CFG_JTAGDISABLE_Msk (0x1U << AFIO_MAPR_SWJ_CFG_JTAGDISABLE_Pos) /*!< 0x02000000 */
+#define AFIO_MAPR_SWJ_CFG_JTAGDISABLE AFIO_MAPR_SWJ_CFG_JTAGDISABLE_Msk /*!< JTAG-DP Disabled and SW-DP Enabled */
+#define AFIO_MAPR_SWJ_CFG_DISABLE_Pos (26U)
+#define AFIO_MAPR_SWJ_CFG_DISABLE_Msk (0x1U << AFIO_MAPR_SWJ_CFG_DISABLE_Pos) /*!< 0x04000000 */
+#define AFIO_MAPR_SWJ_CFG_DISABLE AFIO_MAPR_SWJ_CFG_DISABLE_Msk /*!< JTAG-DP Disabled and SW-DP Disabled */
+
+/*!< ETH_REMAP configuration */
+#define AFIO_MAPR_ETH_REMAP_Pos (21U)
+#define AFIO_MAPR_ETH_REMAP_Msk (0x1U << AFIO_MAPR_ETH_REMAP_Pos) /*!< 0x00200000 */
+#define AFIO_MAPR_ETH_REMAP AFIO_MAPR_ETH_REMAP_Msk /*!< SPI3_REMAP bit (Ethernet MAC I/O remapping) */
+
+/*!< CAN2_REMAP configuration */
+#define AFIO_MAPR_CAN2_REMAP_Pos (22U)
+#define AFIO_MAPR_CAN2_REMAP_Msk (0x1U << AFIO_MAPR_CAN2_REMAP_Pos) /*!< 0x00400000 */
+#define AFIO_MAPR_CAN2_REMAP AFIO_MAPR_CAN2_REMAP_Msk /*!< CAN2_REMAP bit (CAN2 I/O remapping) */
+
+/*!< MII_RMII_SEL configuration */
+#define AFIO_MAPR_MII_RMII_SEL_Pos (23U)
+#define AFIO_MAPR_MII_RMII_SEL_Msk (0x1U << AFIO_MAPR_MII_RMII_SEL_Pos) /*!< 0x00800000 */
+#define AFIO_MAPR_MII_RMII_SEL AFIO_MAPR_MII_RMII_SEL_Msk /*!< MII_RMII_SEL bit (Ethernet MII or RMII selection) */
+
+/*!< SPI3_REMAP configuration */
+#define AFIO_MAPR_SPI3_REMAP_Pos (28U)
+#define AFIO_MAPR_SPI3_REMAP_Msk (0x1U << AFIO_MAPR_SPI3_REMAP_Pos) /*!< 0x10000000 */
+#define AFIO_MAPR_SPI3_REMAP AFIO_MAPR_SPI3_REMAP_Msk /*!< SPI3_REMAP bit (SPI3 remapping) */
+
+/*!< TIM2ITR1_IREMAP configuration */
+#define AFIO_MAPR_TIM2ITR1_IREMAP_Pos (29U)
+#define AFIO_MAPR_TIM2ITR1_IREMAP_Msk (0x1U << AFIO_MAPR_TIM2ITR1_IREMAP_Pos) /*!< 0x20000000 */
+#define AFIO_MAPR_TIM2ITR1_IREMAP AFIO_MAPR_TIM2ITR1_IREMAP_Msk /*!< TIM2ITR1_IREMAP bit (TIM2 internal trigger 1 remapping) */
+
+/*!< PTP_PPS_REMAP configuration */
+#define AFIO_MAPR_PTP_PPS_REMAP_Pos (30U)
+#define AFIO_MAPR_PTP_PPS_REMAP_Msk (0x1U << AFIO_MAPR_PTP_PPS_REMAP_Pos) /*!< 0x40000000 */
+#define AFIO_MAPR_PTP_PPS_REMAP AFIO_MAPR_PTP_PPS_REMAP_Msk /*!< PTP_PPS_REMAP bit (Ethernet PTP PPS remapping) */
+
+/***************** Bit definition for AFIO_EXTICR1 register *****************/
+#define AFIO_EXTICR1_EXTI0_Pos (0U)
+#define AFIO_EXTICR1_EXTI0_Msk (0xFU << AFIO_EXTICR1_EXTI0_Pos) /*!< 0x0000000F */
+#define AFIO_EXTICR1_EXTI0 AFIO_EXTICR1_EXTI0_Msk /*!< EXTI 0 configuration */
+#define AFIO_EXTICR1_EXTI1_Pos (4U)
+#define AFIO_EXTICR1_EXTI1_Msk (0xFU << AFIO_EXTICR1_EXTI1_Pos) /*!< 0x000000F0 */
+#define AFIO_EXTICR1_EXTI1 AFIO_EXTICR1_EXTI1_Msk /*!< EXTI 1 configuration */
+#define AFIO_EXTICR1_EXTI2_Pos (8U)
+#define AFIO_EXTICR1_EXTI2_Msk (0xFU << AFIO_EXTICR1_EXTI2_Pos) /*!< 0x00000F00 */
+#define AFIO_EXTICR1_EXTI2 AFIO_EXTICR1_EXTI2_Msk /*!< EXTI 2 configuration */
+#define AFIO_EXTICR1_EXTI3_Pos (12U)
+#define AFIO_EXTICR1_EXTI3_Msk (0xFU << AFIO_EXTICR1_EXTI3_Pos) /*!< 0x0000F000 */
+#define AFIO_EXTICR1_EXTI3 AFIO_EXTICR1_EXTI3_Msk /*!< EXTI 3 configuration */
+
+/*!< EXTI0 configuration */
+#define AFIO_EXTICR1_EXTI0_PA ((uint32_t)0x00000000) /*!< PA[0] pin */
+#define AFIO_EXTICR1_EXTI0_PB_Pos (0U)
+#define AFIO_EXTICR1_EXTI0_PB_Msk (0x1U << AFIO_EXTICR1_EXTI0_PB_Pos) /*!< 0x00000001 */
+#define AFIO_EXTICR1_EXTI0_PB AFIO_EXTICR1_EXTI0_PB_Msk /*!< PB[0] pin */
+#define AFIO_EXTICR1_EXTI0_PC_Pos (1U)
+#define AFIO_EXTICR1_EXTI0_PC_Msk (0x1U << AFIO_EXTICR1_EXTI0_PC_Pos) /*!< 0x00000002 */
+#define AFIO_EXTICR1_EXTI0_PC AFIO_EXTICR1_EXTI0_PC_Msk /*!< PC[0] pin */
+#define AFIO_EXTICR1_EXTI0_PD_Pos (0U)
+#define AFIO_EXTICR1_EXTI0_PD_Msk (0x3U << AFIO_EXTICR1_EXTI0_PD_Pos) /*!< 0x00000003 */
+#define AFIO_EXTICR1_EXTI0_PD AFIO_EXTICR1_EXTI0_PD_Msk /*!< PD[0] pin */
+#define AFIO_EXTICR1_EXTI0_PE_Pos (2U)
+#define AFIO_EXTICR1_EXTI0_PE_Msk (0x1U << AFIO_EXTICR1_EXTI0_PE_Pos) /*!< 0x00000004 */
+#define AFIO_EXTICR1_EXTI0_PE AFIO_EXTICR1_EXTI0_PE_Msk /*!< PE[0] pin */
+#define AFIO_EXTICR1_EXTI0_PF_Pos (0U)
+#define AFIO_EXTICR1_EXTI0_PF_Msk (0x5U << AFIO_EXTICR1_EXTI0_PF_Pos) /*!< 0x00000005 */
+#define AFIO_EXTICR1_EXTI0_PF AFIO_EXTICR1_EXTI0_PF_Msk /*!< PF[0] pin */
+#define AFIO_EXTICR1_EXTI0_PG_Pos (1U)
+#define AFIO_EXTICR1_EXTI0_PG_Msk (0x3U << AFIO_EXTICR1_EXTI0_PG_Pos) /*!< 0x00000006 */
+#define AFIO_EXTICR1_EXTI0_PG AFIO_EXTICR1_EXTI0_PG_Msk /*!< PG[0] pin */
+
+/*!< EXTI1 configuration */
+#define AFIO_EXTICR1_EXTI1_PA ((uint32_t)0x00000000) /*!< PA[1] pin */
+#define AFIO_EXTICR1_EXTI1_PB_Pos (4U)
+#define AFIO_EXTICR1_EXTI1_PB_Msk (0x1U << AFIO_EXTICR1_EXTI1_PB_Pos) /*!< 0x00000010 */
+#define AFIO_EXTICR1_EXTI1_PB AFIO_EXTICR1_EXTI1_PB_Msk /*!< PB[1] pin */
+#define AFIO_EXTICR1_EXTI1_PC_Pos (5U)
+#define AFIO_EXTICR1_EXTI1_PC_Msk (0x1U << AFIO_EXTICR1_EXTI1_PC_Pos) /*!< 0x00000020 */
+#define AFIO_EXTICR1_EXTI1_PC AFIO_EXTICR1_EXTI1_PC_Msk /*!< PC[1] pin */
+#define AFIO_EXTICR1_EXTI1_PD_Pos (4U)
+#define AFIO_EXTICR1_EXTI1_PD_Msk (0x3U << AFIO_EXTICR1_EXTI1_PD_Pos) /*!< 0x00000030 */
+#define AFIO_EXTICR1_EXTI1_PD AFIO_EXTICR1_EXTI1_PD_Msk /*!< PD[1] pin */
+#define AFIO_EXTICR1_EXTI1_PE_Pos (6U)
+#define AFIO_EXTICR1_EXTI1_PE_Msk (0x1U << AFIO_EXTICR1_EXTI1_PE_Pos) /*!< 0x00000040 */
+#define AFIO_EXTICR1_EXTI1_PE AFIO_EXTICR1_EXTI1_PE_Msk /*!< PE[1] pin */
+#define AFIO_EXTICR1_EXTI1_PF_Pos (4U)
+#define AFIO_EXTICR1_EXTI1_PF_Msk (0x5U << AFIO_EXTICR1_EXTI1_PF_Pos) /*!< 0x00000050 */
+#define AFIO_EXTICR1_EXTI1_PF AFIO_EXTICR1_EXTI1_PF_Msk /*!< PF[1] pin */
+#define AFIO_EXTICR1_EXTI1_PG_Pos (5U)
+#define AFIO_EXTICR1_EXTI1_PG_Msk (0x3U << AFIO_EXTICR1_EXTI1_PG_Pos) /*!< 0x00000060 */
+#define AFIO_EXTICR1_EXTI1_PG AFIO_EXTICR1_EXTI1_PG_Msk /*!< PG[1] pin */
+
+/*!< EXTI2 configuration */
+#define AFIO_EXTICR1_EXTI2_PA ((uint32_t)0x00000000) /*!< PA[2] pin */
+#define AFIO_EXTICR1_EXTI2_PB_Pos (8U)
+#define AFIO_EXTICR1_EXTI2_PB_Msk (0x1U << AFIO_EXTICR1_EXTI2_PB_Pos) /*!< 0x00000100 */
+#define AFIO_EXTICR1_EXTI2_PB AFIO_EXTICR1_EXTI2_PB_Msk /*!< PB[2] pin */
+#define AFIO_EXTICR1_EXTI2_PC_Pos (9U)
+#define AFIO_EXTICR1_EXTI2_PC_Msk (0x1U << AFIO_EXTICR1_EXTI2_PC_Pos) /*!< 0x00000200 */
+#define AFIO_EXTICR1_EXTI2_PC AFIO_EXTICR1_EXTI2_PC_Msk /*!< PC[2] pin */
+#define AFIO_EXTICR1_EXTI2_PD_Pos (8U)
+#define AFIO_EXTICR1_EXTI2_PD_Msk (0x3U << AFIO_EXTICR1_EXTI2_PD_Pos) /*!< 0x00000300 */
+#define AFIO_EXTICR1_EXTI2_PD AFIO_EXTICR1_EXTI2_PD_Msk /*!< PD[2] pin */
+#define AFIO_EXTICR1_EXTI2_PE_Pos (10U)
+#define AFIO_EXTICR1_EXTI2_PE_Msk (0x1U << AFIO_EXTICR1_EXTI2_PE_Pos) /*!< 0x00000400 */
+#define AFIO_EXTICR1_EXTI2_PE AFIO_EXTICR1_EXTI2_PE_Msk /*!< PE[2] pin */
+#define AFIO_EXTICR1_EXTI2_PF_Pos (8U)
+#define AFIO_EXTICR1_EXTI2_PF_Msk (0x5U << AFIO_EXTICR1_EXTI2_PF_Pos) /*!< 0x00000500 */
+#define AFIO_EXTICR1_EXTI2_PF AFIO_EXTICR1_EXTI2_PF_Msk /*!< PF[2] pin */
+#define AFIO_EXTICR1_EXTI2_PG_Pos (9U)
+#define AFIO_EXTICR1_EXTI2_PG_Msk (0x3U << AFIO_EXTICR1_EXTI2_PG_Pos) /*!< 0x00000600 */
+#define AFIO_EXTICR1_EXTI2_PG AFIO_EXTICR1_EXTI2_PG_Msk /*!< PG[2] pin */
+
+/*!< EXTI3 configuration */
+#define AFIO_EXTICR1_EXTI3_PA ((uint32_t)0x00000000) /*!< PA[3] pin */
+#define AFIO_EXTICR1_EXTI3_PB_Pos (12U)
+#define AFIO_EXTICR1_EXTI3_PB_Msk (0x1U << AFIO_EXTICR1_EXTI3_PB_Pos) /*!< 0x00001000 */
+#define AFIO_EXTICR1_EXTI3_PB AFIO_EXTICR1_EXTI3_PB_Msk /*!< PB[3] pin */
+#define AFIO_EXTICR1_EXTI3_PC_Pos (13U)
+#define AFIO_EXTICR1_EXTI3_PC_Msk (0x1U << AFIO_EXTICR1_EXTI3_PC_Pos) /*!< 0x00002000 */
+#define AFIO_EXTICR1_EXTI3_PC AFIO_EXTICR1_EXTI3_PC_Msk /*!< PC[3] pin */
+#define AFIO_EXTICR1_EXTI3_PD_Pos (12U)
+#define AFIO_EXTICR1_EXTI3_PD_Msk (0x3U << AFIO_EXTICR1_EXTI3_PD_Pos) /*!< 0x00003000 */
+#define AFIO_EXTICR1_EXTI3_PD AFIO_EXTICR1_EXTI3_PD_Msk /*!< PD[3] pin */
+#define AFIO_EXTICR1_EXTI3_PE_Pos (14U)
+#define AFIO_EXTICR1_EXTI3_PE_Msk (0x1U << AFIO_EXTICR1_EXTI3_PE_Pos) /*!< 0x00004000 */
+#define AFIO_EXTICR1_EXTI3_PE AFIO_EXTICR1_EXTI3_PE_Msk /*!< PE[3] pin */
+#define AFIO_EXTICR1_EXTI3_PF_Pos (12U)
+#define AFIO_EXTICR1_EXTI3_PF_Msk (0x5U << AFIO_EXTICR1_EXTI3_PF_Pos) /*!< 0x00005000 */
+#define AFIO_EXTICR1_EXTI3_PF AFIO_EXTICR1_EXTI3_PF_Msk /*!< PF[3] pin */
+#define AFIO_EXTICR1_EXTI3_PG_Pos (13U)
+#define AFIO_EXTICR1_EXTI3_PG_Msk (0x3U << AFIO_EXTICR1_EXTI3_PG_Pos) /*!< 0x00006000 */
+#define AFIO_EXTICR1_EXTI3_PG AFIO_EXTICR1_EXTI3_PG_Msk /*!< PG[3] pin */
+
+/***************** Bit definition for AFIO_EXTICR2 register *****************/
+#define AFIO_EXTICR2_EXTI4_Pos (0U)
+#define AFIO_EXTICR2_EXTI4_Msk (0xFU << AFIO_EXTICR2_EXTI4_Pos) /*!< 0x0000000F */
+#define AFIO_EXTICR2_EXTI4 AFIO_EXTICR2_EXTI4_Msk /*!< EXTI 4 configuration */
+#define AFIO_EXTICR2_EXTI5_Pos (4U)
+#define AFIO_EXTICR2_EXTI5_Msk (0xFU << AFIO_EXTICR2_EXTI5_Pos) /*!< 0x000000F0 */
+#define AFIO_EXTICR2_EXTI5 AFIO_EXTICR2_EXTI5_Msk /*!< EXTI 5 configuration */
+#define AFIO_EXTICR2_EXTI6_Pos (8U)
+#define AFIO_EXTICR2_EXTI6_Msk (0xFU << AFIO_EXTICR2_EXTI6_Pos) /*!< 0x00000F00 */
+#define AFIO_EXTICR2_EXTI6 AFIO_EXTICR2_EXTI6_Msk /*!< EXTI 6 configuration */
+#define AFIO_EXTICR2_EXTI7_Pos (12U)
+#define AFIO_EXTICR2_EXTI7_Msk (0xFU << AFIO_EXTICR2_EXTI7_Pos) /*!< 0x0000F000 */
+#define AFIO_EXTICR2_EXTI7 AFIO_EXTICR2_EXTI7_Msk /*!< EXTI 7 configuration */
+
+/*!< EXTI4 configuration */
+#define AFIO_EXTICR2_EXTI4_PA ((uint32_t)0x00000000) /*!< PA[4] pin */
+#define AFIO_EXTICR2_EXTI4_PB_Pos (0U)
+#define AFIO_EXTICR2_EXTI4_PB_Msk (0x1U << AFIO_EXTICR2_EXTI4_PB_Pos) /*!< 0x00000001 */
+#define AFIO_EXTICR2_EXTI4_PB AFIO_EXTICR2_EXTI4_PB_Msk /*!< PB[4] pin */
+#define AFIO_EXTICR2_EXTI4_PC_Pos (1U)
+#define AFIO_EXTICR2_EXTI4_PC_Msk (0x1U << AFIO_EXTICR2_EXTI4_PC_Pos) /*!< 0x00000002 */
+#define AFIO_EXTICR2_EXTI4_PC AFIO_EXTICR2_EXTI4_PC_Msk /*!< PC[4] pin */
+#define AFIO_EXTICR2_EXTI4_PD_Pos (0U)
+#define AFIO_EXTICR2_EXTI4_PD_Msk (0x3U << AFIO_EXTICR2_EXTI4_PD_Pos) /*!< 0x00000003 */
+#define AFIO_EXTICR2_EXTI4_PD AFIO_EXTICR2_EXTI4_PD_Msk /*!< PD[4] pin */
+#define AFIO_EXTICR2_EXTI4_PE_Pos (2U)
+#define AFIO_EXTICR2_EXTI4_PE_Msk (0x1U << AFIO_EXTICR2_EXTI4_PE_Pos) /*!< 0x00000004 */
+#define AFIO_EXTICR2_EXTI4_PE AFIO_EXTICR2_EXTI4_PE_Msk /*!< PE[4] pin */
+#define AFIO_EXTICR2_EXTI4_PF_Pos (0U)
+#define AFIO_EXTICR2_EXTI4_PF_Msk (0x5U << AFIO_EXTICR2_EXTI4_PF_Pos) /*!< 0x00000005 */
+#define AFIO_EXTICR2_EXTI4_PF AFIO_EXTICR2_EXTI4_PF_Msk /*!< PF[4] pin */
+#define AFIO_EXTICR2_EXTI4_PG_Pos (1U)
+#define AFIO_EXTICR2_EXTI4_PG_Msk (0x3U << AFIO_EXTICR2_EXTI4_PG_Pos) /*!< 0x00000006 */
+#define AFIO_EXTICR2_EXTI4_PG AFIO_EXTICR2_EXTI4_PG_Msk /*!< PG[4] pin */
+
+/* EXTI5 configuration */
+#define AFIO_EXTICR2_EXTI5_PA ((uint32_t)0x00000000) /*!< PA[5] pin */
+#define AFIO_EXTICR2_EXTI5_PB_Pos (4U)
+#define AFIO_EXTICR2_EXTI5_PB_Msk (0x1U << AFIO_EXTICR2_EXTI5_PB_Pos) /*!< 0x00000010 */
+#define AFIO_EXTICR2_EXTI5_PB AFIO_EXTICR2_EXTI5_PB_Msk /*!< PB[5] pin */
+#define AFIO_EXTICR2_EXTI5_PC_Pos (5U)
+#define AFIO_EXTICR2_EXTI5_PC_Msk (0x1U << AFIO_EXTICR2_EXTI5_PC_Pos) /*!< 0x00000020 */
+#define AFIO_EXTICR2_EXTI5_PC AFIO_EXTICR2_EXTI5_PC_Msk /*!< PC[5] pin */
+#define AFIO_EXTICR2_EXTI5_PD_Pos (4U)
+#define AFIO_EXTICR2_EXTI5_PD_Msk (0x3U << AFIO_EXTICR2_EXTI5_PD_Pos) /*!< 0x00000030 */
+#define AFIO_EXTICR2_EXTI5_PD AFIO_EXTICR2_EXTI5_PD_Msk /*!< PD[5] pin */
+#define AFIO_EXTICR2_EXTI5_PE_Pos (6U)
+#define AFIO_EXTICR2_EXTI5_PE_Msk (0x1U << AFIO_EXTICR2_EXTI5_PE_Pos) /*!< 0x00000040 */
+#define AFIO_EXTICR2_EXTI5_PE AFIO_EXTICR2_EXTI5_PE_Msk /*!< PE[5] pin */
+#define AFIO_EXTICR2_EXTI5_PF_Pos (4U)
+#define AFIO_EXTICR2_EXTI5_PF_Msk (0x5U << AFIO_EXTICR2_EXTI5_PF_Pos) /*!< 0x00000050 */
+#define AFIO_EXTICR2_EXTI5_PF AFIO_EXTICR2_EXTI5_PF_Msk /*!< PF[5] pin */
+#define AFIO_EXTICR2_EXTI5_PG_Pos (5U)
+#define AFIO_EXTICR2_EXTI5_PG_Msk (0x3U << AFIO_EXTICR2_EXTI5_PG_Pos) /*!< 0x00000060 */
+#define AFIO_EXTICR2_EXTI5_PG AFIO_EXTICR2_EXTI5_PG_Msk /*!< PG[5] pin */
+
+/*!< EXTI6 configuration */
+#define AFIO_EXTICR2_EXTI6_PA ((uint32_t)0x00000000) /*!< PA[6] pin */
+#define AFIO_EXTICR2_EXTI6_PB_Pos (8U)
+#define AFIO_EXTICR2_EXTI6_PB_Msk (0x1U << AFIO_EXTICR2_EXTI6_PB_Pos) /*!< 0x00000100 */
+#define AFIO_EXTICR2_EXTI6_PB AFIO_EXTICR2_EXTI6_PB_Msk /*!< PB[6] pin */
+#define AFIO_EXTICR2_EXTI6_PC_Pos (9U)
+#define AFIO_EXTICR2_EXTI6_PC_Msk (0x1U << AFIO_EXTICR2_EXTI6_PC_Pos) /*!< 0x00000200 */
+#define AFIO_EXTICR2_EXTI6_PC AFIO_EXTICR2_EXTI6_PC_Msk /*!< PC[6] pin */
+#define AFIO_EXTICR2_EXTI6_PD_Pos (8U)
+#define AFIO_EXTICR2_EXTI6_PD_Msk (0x3U << AFIO_EXTICR2_EXTI6_PD_Pos) /*!< 0x00000300 */
+#define AFIO_EXTICR2_EXTI6_PD AFIO_EXTICR2_EXTI6_PD_Msk /*!< PD[6] pin */
+#define AFIO_EXTICR2_EXTI6_PE_Pos (10U)
+#define AFIO_EXTICR2_EXTI6_PE_Msk (0x1U << AFIO_EXTICR2_EXTI6_PE_Pos) /*!< 0x00000400 */
+#define AFIO_EXTICR2_EXTI6_PE AFIO_EXTICR2_EXTI6_PE_Msk /*!< PE[6] pin */
+#define AFIO_EXTICR2_EXTI6_PF_Pos (8U)
+#define AFIO_EXTICR2_EXTI6_PF_Msk (0x5U << AFIO_EXTICR2_EXTI6_PF_Pos) /*!< 0x00000500 */
+#define AFIO_EXTICR2_EXTI6_PF AFIO_EXTICR2_EXTI6_PF_Msk /*!< PF[6] pin */
+#define AFIO_EXTICR2_EXTI6_PG_Pos (9U)
+#define AFIO_EXTICR2_EXTI6_PG_Msk (0x3U << AFIO_EXTICR2_EXTI6_PG_Pos) /*!< 0x00000600 */
+#define AFIO_EXTICR2_EXTI6_PG AFIO_EXTICR2_EXTI6_PG_Msk /*!< PG[6] pin */
+
+/*!< EXTI7 configuration */
+#define AFIO_EXTICR2_EXTI7_PA ((uint32_t)0x00000000) /*!< PA[7] pin */
+#define AFIO_EXTICR2_EXTI7_PB_Pos (12U)
+#define AFIO_EXTICR2_EXTI7_PB_Msk (0x1U << AFIO_EXTICR2_EXTI7_PB_Pos) /*!< 0x00001000 */
+#define AFIO_EXTICR2_EXTI7_PB AFIO_EXTICR2_EXTI7_PB_Msk /*!< PB[7] pin */
+#define AFIO_EXTICR2_EXTI7_PC_Pos (13U)
+#define AFIO_EXTICR2_EXTI7_PC_Msk (0x1U << AFIO_EXTICR2_EXTI7_PC_Pos) /*!< 0x00002000 */
+#define AFIO_EXTICR2_EXTI7_PC AFIO_EXTICR2_EXTI7_PC_Msk /*!< PC[7] pin */
+#define AFIO_EXTICR2_EXTI7_PD_Pos (12U)
+#define AFIO_EXTICR2_EXTI7_PD_Msk (0x3U << AFIO_EXTICR2_EXTI7_PD_Pos) /*!< 0x00003000 */
+#define AFIO_EXTICR2_EXTI7_PD AFIO_EXTICR2_EXTI7_PD_Msk /*!< PD[7] pin */
+#define AFIO_EXTICR2_EXTI7_PE_Pos (14U)
+#define AFIO_EXTICR2_EXTI7_PE_Msk (0x1U << AFIO_EXTICR2_EXTI7_PE_Pos) /*!< 0x00004000 */
+#define AFIO_EXTICR2_EXTI7_PE AFIO_EXTICR2_EXTI7_PE_Msk /*!< PE[7] pin */
+#define AFIO_EXTICR2_EXTI7_PF_Pos (12U)
+#define AFIO_EXTICR2_EXTI7_PF_Msk (0x5U << AFIO_EXTICR2_EXTI7_PF_Pos) /*!< 0x00005000 */
+#define AFIO_EXTICR2_EXTI7_PF AFIO_EXTICR2_EXTI7_PF_Msk /*!< PF[7] pin */
+#define AFIO_EXTICR2_EXTI7_PG_Pos (13U)
+#define AFIO_EXTICR2_EXTI7_PG_Msk (0x3U << AFIO_EXTICR2_EXTI7_PG_Pos) /*!< 0x00006000 */
+#define AFIO_EXTICR2_EXTI7_PG AFIO_EXTICR2_EXTI7_PG_Msk /*!< PG[7] pin */
+
+/***************** Bit definition for AFIO_EXTICR3 register *****************/
+#define AFIO_EXTICR3_EXTI8_Pos (0U)
+#define AFIO_EXTICR3_EXTI8_Msk (0xFU << AFIO_EXTICR3_EXTI8_Pos) /*!< 0x0000000F */
+#define AFIO_EXTICR3_EXTI8 AFIO_EXTICR3_EXTI8_Msk /*!< EXTI 8 configuration */
+#define AFIO_EXTICR3_EXTI9_Pos (4U)
+#define AFIO_EXTICR3_EXTI9_Msk (0xFU << AFIO_EXTICR3_EXTI9_Pos) /*!< 0x000000F0 */
+#define AFIO_EXTICR3_EXTI9 AFIO_EXTICR3_EXTI9_Msk /*!< EXTI 9 configuration */
+#define AFIO_EXTICR3_EXTI10_Pos (8U)
+#define AFIO_EXTICR3_EXTI10_Msk (0xFU << AFIO_EXTICR3_EXTI10_Pos) /*!< 0x00000F00 */
+#define AFIO_EXTICR3_EXTI10 AFIO_EXTICR3_EXTI10_Msk /*!< EXTI 10 configuration */
+#define AFIO_EXTICR3_EXTI11_Pos (12U)
+#define AFIO_EXTICR3_EXTI11_Msk (0xFU << AFIO_EXTICR3_EXTI11_Pos) /*!< 0x0000F000 */
+#define AFIO_EXTICR3_EXTI11 AFIO_EXTICR3_EXTI11_Msk /*!< EXTI 11 configuration */
+
+/*!< EXTI8 configuration */
+#define AFIO_EXTICR3_EXTI8_PA ((uint32_t)0x00000000) /*!< PA[8] pin */
+#define AFIO_EXTICR3_EXTI8_PB_Pos (0U)
+#define AFIO_EXTICR3_EXTI8_PB_Msk (0x1U << AFIO_EXTICR3_EXTI8_PB_Pos) /*!< 0x00000001 */
+#define AFIO_EXTICR3_EXTI8_PB AFIO_EXTICR3_EXTI8_PB_Msk /*!< PB[8] pin */
+#define AFIO_EXTICR3_EXTI8_PC_Pos (1U)
+#define AFIO_EXTICR3_EXTI8_PC_Msk (0x1U << AFIO_EXTICR3_EXTI8_PC_Pos) /*!< 0x00000002 */
+#define AFIO_EXTICR3_EXTI8_PC AFIO_EXTICR3_EXTI8_PC_Msk /*!< PC[8] pin */
+#define AFIO_EXTICR3_EXTI8_PD_Pos (0U)
+#define AFIO_EXTICR3_EXTI8_PD_Msk (0x3U << AFIO_EXTICR3_EXTI8_PD_Pos) /*!< 0x00000003 */
+#define AFIO_EXTICR3_EXTI8_PD AFIO_EXTICR3_EXTI8_PD_Msk /*!< PD[8] pin */
+#define AFIO_EXTICR3_EXTI8_PE_Pos (2U)
+#define AFIO_EXTICR3_EXTI8_PE_Msk (0x1U << AFIO_EXTICR3_EXTI8_PE_Pos) /*!< 0x00000004 */
+#define AFIO_EXTICR3_EXTI8_PE AFIO_EXTICR3_EXTI8_PE_Msk /*!< PE[8] pin */
+#define AFIO_EXTICR3_EXTI8_PF_Pos (0U)
+#define AFIO_EXTICR3_EXTI8_PF_Msk (0x5U << AFIO_EXTICR3_EXTI8_PF_Pos) /*!< 0x00000005 */
+#define AFIO_EXTICR3_EXTI8_PF AFIO_EXTICR3_EXTI8_PF_Msk /*!< PF[8] pin */
+#define AFIO_EXTICR3_EXTI8_PG_Pos (1U)
+#define AFIO_EXTICR3_EXTI8_PG_Msk (0x3U << AFIO_EXTICR3_EXTI8_PG_Pos) /*!< 0x00000006 */
+#define AFIO_EXTICR3_EXTI8_PG AFIO_EXTICR3_EXTI8_PG_Msk /*!< PG[8] pin */
+
+/*!< EXTI9 configuration */
+#define AFIO_EXTICR3_EXTI9_PA ((uint32_t)0x00000000) /*!< PA[9] pin */
+#define AFIO_EXTICR3_EXTI9_PB_Pos (4U)
+#define AFIO_EXTICR3_EXTI9_PB_Msk (0x1U << AFIO_EXTICR3_EXTI9_PB_Pos) /*!< 0x00000010 */
+#define AFIO_EXTICR3_EXTI9_PB AFIO_EXTICR3_EXTI9_PB_Msk /*!< PB[9] pin */
+#define AFIO_EXTICR3_EXTI9_PC_Pos (5U)
+#define AFIO_EXTICR3_EXTI9_PC_Msk (0x1U << AFIO_EXTICR3_EXTI9_PC_Pos) /*!< 0x00000020 */
+#define AFIO_EXTICR3_EXTI9_PC AFIO_EXTICR3_EXTI9_PC_Msk /*!< PC[9] pin */
+#define AFIO_EXTICR3_EXTI9_PD_Pos (4U)
+#define AFIO_EXTICR3_EXTI9_PD_Msk (0x3U << AFIO_EXTICR3_EXTI9_PD_Pos) /*!< 0x00000030 */
+#define AFIO_EXTICR3_EXTI9_PD AFIO_EXTICR3_EXTI9_PD_Msk /*!< PD[9] pin */
+#define AFIO_EXTICR3_EXTI9_PE_Pos (6U)
+#define AFIO_EXTICR3_EXTI9_PE_Msk (0x1U << AFIO_EXTICR3_EXTI9_PE_Pos) /*!< 0x00000040 */
+#define AFIO_EXTICR3_EXTI9_PE AFIO_EXTICR3_EXTI9_PE_Msk /*!< PE[9] pin */
+#define AFIO_EXTICR3_EXTI9_PF_Pos (4U)
+#define AFIO_EXTICR3_EXTI9_PF_Msk (0x5U << AFIO_EXTICR3_EXTI9_PF_Pos) /*!< 0x00000050 */
+#define AFIO_EXTICR3_EXTI9_PF AFIO_EXTICR3_EXTI9_PF_Msk /*!< PF[9] pin */
+#define AFIO_EXTICR3_EXTI9_PG_Pos (5U)
+#define AFIO_EXTICR3_EXTI9_PG_Msk (0x3U << AFIO_EXTICR3_EXTI9_PG_Pos) /*!< 0x00000060 */
+#define AFIO_EXTICR3_EXTI9_PG AFIO_EXTICR3_EXTI9_PG_Msk /*!< PG[9] pin */
+
+/*!< EXTI10 configuration */
+#define AFIO_EXTICR3_EXTI10_PA ((uint32_t)0x00000000) /*!< PA[10] pin */
+#define AFIO_EXTICR3_EXTI10_PB_Pos (8U)
+#define AFIO_EXTICR3_EXTI10_PB_Msk (0x1U << AFIO_EXTICR3_EXTI10_PB_Pos) /*!< 0x00000100 */
+#define AFIO_EXTICR3_EXTI10_PB AFIO_EXTICR3_EXTI10_PB_Msk /*!< PB[10] pin */
+#define AFIO_EXTICR3_EXTI10_PC_Pos (9U)
+#define AFIO_EXTICR3_EXTI10_PC_Msk (0x1U << AFIO_EXTICR3_EXTI10_PC_Pos) /*!< 0x00000200 */
+#define AFIO_EXTICR3_EXTI10_PC AFIO_EXTICR3_EXTI10_PC_Msk /*!< PC[10] pin */
+#define AFIO_EXTICR3_EXTI10_PD_Pos (8U)
+#define AFIO_EXTICR3_EXTI10_PD_Msk (0x3U << AFIO_EXTICR3_EXTI10_PD_Pos) /*!< 0x00000300 */
+#define AFIO_EXTICR3_EXTI10_PD AFIO_EXTICR3_EXTI10_PD_Msk /*!< PD[10] pin */
+#define AFIO_EXTICR3_EXTI10_PE_Pos (10U)
+#define AFIO_EXTICR3_EXTI10_PE_Msk (0x1U << AFIO_EXTICR3_EXTI10_PE_Pos) /*!< 0x00000400 */
+#define AFIO_EXTICR3_EXTI10_PE AFIO_EXTICR3_EXTI10_PE_Msk /*!< PE[10] pin */
+#define AFIO_EXTICR3_EXTI10_PF_Pos (8U)
+#define AFIO_EXTICR3_EXTI10_PF_Msk (0x5U << AFIO_EXTICR3_EXTI10_PF_Pos) /*!< 0x00000500 */
+#define AFIO_EXTICR3_EXTI10_PF AFIO_EXTICR3_EXTI10_PF_Msk /*!< PF[10] pin */
+#define AFIO_EXTICR3_EXTI10_PG_Pos (9U)
+#define AFIO_EXTICR3_EXTI10_PG_Msk (0x3U << AFIO_EXTICR3_EXTI10_PG_Pos) /*!< 0x00000600 */
+#define AFIO_EXTICR3_EXTI10_PG AFIO_EXTICR3_EXTI10_PG_Msk /*!< PG[10] pin */
+
+/*!< EXTI11 configuration */
+#define AFIO_EXTICR3_EXTI11_PA ((uint32_t)0x00000000) /*!< PA[11] pin */
+#define AFIO_EXTICR3_EXTI11_PB_Pos (12U)
+#define AFIO_EXTICR3_EXTI11_PB_Msk (0x1U << AFIO_EXTICR3_EXTI11_PB_Pos) /*!< 0x00001000 */
+#define AFIO_EXTICR3_EXTI11_PB AFIO_EXTICR3_EXTI11_PB_Msk /*!< PB[11] pin */
+#define AFIO_EXTICR3_EXTI11_PC_Pos (13U)
+#define AFIO_EXTICR3_EXTI11_PC_Msk (0x1U << AFIO_EXTICR3_EXTI11_PC_Pos) /*!< 0x00002000 */
+#define AFIO_EXTICR3_EXTI11_PC AFIO_EXTICR3_EXTI11_PC_Msk /*!< PC[11] pin */
+#define AFIO_EXTICR3_EXTI11_PD_Pos (12U)
+#define AFIO_EXTICR3_EXTI11_PD_Msk (0x3U << AFIO_EXTICR3_EXTI11_PD_Pos) /*!< 0x00003000 */
+#define AFIO_EXTICR3_EXTI11_PD AFIO_EXTICR3_EXTI11_PD_Msk /*!< PD[11] pin */
+#define AFIO_EXTICR3_EXTI11_PE_Pos (14U)
+#define AFIO_EXTICR3_EXTI11_PE_Msk (0x1U << AFIO_EXTICR3_EXTI11_PE_Pos) /*!< 0x00004000 */
+#define AFIO_EXTICR3_EXTI11_PE AFIO_EXTICR3_EXTI11_PE_Msk /*!< PE[11] pin */
+#define AFIO_EXTICR3_EXTI11_PF_Pos (12U)
+#define AFIO_EXTICR3_EXTI11_PF_Msk (0x5U << AFIO_EXTICR3_EXTI11_PF_Pos) /*!< 0x00005000 */
+#define AFIO_EXTICR3_EXTI11_PF AFIO_EXTICR3_EXTI11_PF_Msk /*!< PF[11] pin */
+#define AFIO_EXTICR3_EXTI11_PG_Pos (13U)
+#define AFIO_EXTICR3_EXTI11_PG_Msk (0x3U << AFIO_EXTICR3_EXTI11_PG_Pos) /*!< 0x00006000 */
+#define AFIO_EXTICR3_EXTI11_PG AFIO_EXTICR3_EXTI11_PG_Msk /*!< PG[11] pin */
+
+/***************** Bit definition for AFIO_EXTICR4 register *****************/
+#define AFIO_EXTICR4_EXTI12_Pos (0U)
+#define AFIO_EXTICR4_EXTI12_Msk (0xFU << AFIO_EXTICR4_EXTI12_Pos) /*!< 0x0000000F */
+#define AFIO_EXTICR4_EXTI12 AFIO_EXTICR4_EXTI12_Msk /*!< EXTI 12 configuration */
+#define AFIO_EXTICR4_EXTI13_Pos (4U)
+#define AFIO_EXTICR4_EXTI13_Msk (0xFU << AFIO_EXTICR4_EXTI13_Pos) /*!< 0x000000F0 */
+#define AFIO_EXTICR4_EXTI13 AFIO_EXTICR4_EXTI13_Msk /*!< EXTI 13 configuration */
+#define AFIO_EXTICR4_EXTI14_Pos (8U)
+#define AFIO_EXTICR4_EXTI14_Msk (0xFU << AFIO_EXTICR4_EXTI14_Pos) /*!< 0x00000F00 */
+#define AFIO_EXTICR4_EXTI14 AFIO_EXTICR4_EXTI14_Msk /*!< EXTI 14 configuration */
+#define AFIO_EXTICR4_EXTI15_Pos (12U)
+#define AFIO_EXTICR4_EXTI15_Msk (0xFU << AFIO_EXTICR4_EXTI15_Pos) /*!< 0x0000F000 */
+#define AFIO_EXTICR4_EXTI15 AFIO_EXTICR4_EXTI15_Msk /*!< EXTI 15 configuration */
+
+/* EXTI12 configuration */
+#define AFIO_EXTICR4_EXTI12_PA ((uint32_t)0x00000000) /*!< PA[12] pin */
+#define AFIO_EXTICR4_EXTI12_PB_Pos (0U)
+#define AFIO_EXTICR4_EXTI12_PB_Msk (0x1U << AFIO_EXTICR4_EXTI12_PB_Pos) /*!< 0x00000001 */
+#define AFIO_EXTICR4_EXTI12_PB AFIO_EXTICR4_EXTI12_PB_Msk /*!< PB[12] pin */
+#define AFIO_EXTICR4_EXTI12_PC_Pos (1U)
+#define AFIO_EXTICR4_EXTI12_PC_Msk (0x1U << AFIO_EXTICR4_EXTI12_PC_Pos) /*!< 0x00000002 */
+#define AFIO_EXTICR4_EXTI12_PC AFIO_EXTICR4_EXTI12_PC_Msk /*!< PC[12] pin */
+#define AFIO_EXTICR4_EXTI12_PD_Pos (0U)
+#define AFIO_EXTICR4_EXTI12_PD_Msk (0x3U << AFIO_EXTICR4_EXTI12_PD_Pos) /*!< 0x00000003 */
+#define AFIO_EXTICR4_EXTI12_PD AFIO_EXTICR4_EXTI12_PD_Msk /*!< PD[12] pin */
+#define AFIO_EXTICR4_EXTI12_PE_Pos (2U)
+#define AFIO_EXTICR4_EXTI12_PE_Msk (0x1U << AFIO_EXTICR4_EXTI12_PE_Pos) /*!< 0x00000004 */
+#define AFIO_EXTICR4_EXTI12_PE AFIO_EXTICR4_EXTI12_PE_Msk /*!< PE[12] pin */
+#define AFIO_EXTICR4_EXTI12_PF_Pos (0U)
+#define AFIO_EXTICR4_EXTI12_PF_Msk (0x5U << AFIO_EXTICR4_EXTI12_PF_Pos) /*!< 0x00000005 */
+#define AFIO_EXTICR4_EXTI12_PF AFIO_EXTICR4_EXTI12_PF_Msk /*!< PF[12] pin */
+#define AFIO_EXTICR4_EXTI12_PG_Pos (1U)
+#define AFIO_EXTICR4_EXTI12_PG_Msk (0x3U << AFIO_EXTICR4_EXTI12_PG_Pos) /*!< 0x00000006 */
+#define AFIO_EXTICR4_EXTI12_PG AFIO_EXTICR4_EXTI12_PG_Msk /*!< PG[12] pin */
+
+/* EXTI13 configuration */
+#define AFIO_EXTICR4_EXTI13_PA ((uint32_t)0x00000000) /*!< PA[13] pin */
+#define AFIO_EXTICR4_EXTI13_PB_Pos (4U)
+#define AFIO_EXTICR4_EXTI13_PB_Msk (0x1U << AFIO_EXTICR4_EXTI13_PB_Pos) /*!< 0x00000010 */
+#define AFIO_EXTICR4_EXTI13_PB AFIO_EXTICR4_EXTI13_PB_Msk /*!< PB[13] pin */
+#define AFIO_EXTICR4_EXTI13_PC_Pos (5U)
+#define AFIO_EXTICR4_EXTI13_PC_Msk (0x1U << AFIO_EXTICR4_EXTI13_PC_Pos) /*!< 0x00000020 */
+#define AFIO_EXTICR4_EXTI13_PC AFIO_EXTICR4_EXTI13_PC_Msk /*!< PC[13] pin */
+#define AFIO_EXTICR4_EXTI13_PD_Pos (4U)
+#define AFIO_EXTICR4_EXTI13_PD_Msk (0x3U << AFIO_EXTICR4_EXTI13_PD_Pos) /*!< 0x00000030 */
+#define AFIO_EXTICR4_EXTI13_PD AFIO_EXTICR4_EXTI13_PD_Msk /*!< PD[13] pin */
+#define AFIO_EXTICR4_EXTI13_PE_Pos (6U)
+#define AFIO_EXTICR4_EXTI13_PE_Msk (0x1U << AFIO_EXTICR4_EXTI13_PE_Pos) /*!< 0x00000040 */
+#define AFIO_EXTICR4_EXTI13_PE AFIO_EXTICR4_EXTI13_PE_Msk /*!< PE[13] pin */
+#define AFIO_EXTICR4_EXTI13_PF_Pos (4U)
+#define AFIO_EXTICR4_EXTI13_PF_Msk (0x5U << AFIO_EXTICR4_EXTI13_PF_Pos) /*!< 0x00000050 */
+#define AFIO_EXTICR4_EXTI13_PF AFIO_EXTICR4_EXTI13_PF_Msk /*!< PF[13] pin */
+#define AFIO_EXTICR4_EXTI13_PG_Pos (5U)
+#define AFIO_EXTICR4_EXTI13_PG_Msk (0x3U << AFIO_EXTICR4_EXTI13_PG_Pos) /*!< 0x00000060 */
+#define AFIO_EXTICR4_EXTI13_PG AFIO_EXTICR4_EXTI13_PG_Msk /*!< PG[13] pin */
+
+/*!< EXTI14 configuration */
+#define AFIO_EXTICR4_EXTI14_PA ((uint32_t)0x00000000) /*!< PA[14] pin */
+#define AFIO_EXTICR4_EXTI14_PB_Pos (8U)
+#define AFIO_EXTICR4_EXTI14_PB_Msk (0x1U << AFIO_EXTICR4_EXTI14_PB_Pos) /*!< 0x00000100 */
+#define AFIO_EXTICR4_EXTI14_PB AFIO_EXTICR4_EXTI14_PB_Msk /*!< PB[14] pin */
+#define AFIO_EXTICR4_EXTI14_PC_Pos (9U)
+#define AFIO_EXTICR4_EXTI14_PC_Msk (0x1U << AFIO_EXTICR4_EXTI14_PC_Pos) /*!< 0x00000200 */
+#define AFIO_EXTICR4_EXTI14_PC AFIO_EXTICR4_EXTI14_PC_Msk /*!< PC[14] pin */
+#define AFIO_EXTICR4_EXTI14_PD_Pos (8U)
+#define AFIO_EXTICR4_EXTI14_PD_Msk (0x3U << AFIO_EXTICR4_EXTI14_PD_Pos) /*!< 0x00000300 */
+#define AFIO_EXTICR4_EXTI14_PD AFIO_EXTICR4_EXTI14_PD_Msk /*!< PD[14] pin */
+#define AFIO_EXTICR4_EXTI14_PE_Pos (10U)
+#define AFIO_EXTICR4_EXTI14_PE_Msk (0x1U << AFIO_EXTICR4_EXTI14_PE_Pos) /*!< 0x00000400 */
+#define AFIO_EXTICR4_EXTI14_PE AFIO_EXTICR4_EXTI14_PE_Msk /*!< PE[14] pin */
+#define AFIO_EXTICR4_EXTI14_PF_Pos (8U)
+#define AFIO_EXTICR4_EXTI14_PF_Msk (0x5U << AFIO_EXTICR4_EXTI14_PF_Pos) /*!< 0x00000500 */
+#define AFIO_EXTICR4_EXTI14_PF AFIO_EXTICR4_EXTI14_PF_Msk /*!< PF[14] pin */
+#define AFIO_EXTICR4_EXTI14_PG_Pos (9U)
+#define AFIO_EXTICR4_EXTI14_PG_Msk (0x3U << AFIO_EXTICR4_EXTI14_PG_Pos) /*!< 0x00000600 */
+#define AFIO_EXTICR4_EXTI14_PG AFIO_EXTICR4_EXTI14_PG_Msk /*!< PG[14] pin */
+
+/*!< EXTI15 configuration */
+#define AFIO_EXTICR4_EXTI15_PA ((uint32_t)0x00000000) /*!< PA[15] pin */
+#define AFIO_EXTICR4_EXTI15_PB_Pos (12U)
+#define AFIO_EXTICR4_EXTI15_PB_Msk (0x1U << AFIO_EXTICR4_EXTI15_PB_Pos) /*!< 0x00001000 */
+#define AFIO_EXTICR4_EXTI15_PB AFIO_EXTICR4_EXTI15_PB_Msk /*!< PB[15] pin */
+#define AFIO_EXTICR4_EXTI15_PC_Pos (13U)
+#define AFIO_EXTICR4_EXTI15_PC_Msk (0x1U << AFIO_EXTICR4_EXTI15_PC_Pos) /*!< 0x00002000 */
+#define AFIO_EXTICR4_EXTI15_PC AFIO_EXTICR4_EXTI15_PC_Msk /*!< PC[15] pin */
+#define AFIO_EXTICR4_EXTI15_PD_Pos (12U)
+#define AFIO_EXTICR4_EXTI15_PD_Msk (0x3U << AFIO_EXTICR4_EXTI15_PD_Pos) /*!< 0x00003000 */
+#define AFIO_EXTICR4_EXTI15_PD AFIO_EXTICR4_EXTI15_PD_Msk /*!< PD[15] pin */
+#define AFIO_EXTICR4_EXTI15_PE_Pos (14U)
+#define AFIO_EXTICR4_EXTI15_PE_Msk (0x1U << AFIO_EXTICR4_EXTI15_PE_Pos) /*!< 0x00004000 */
+#define AFIO_EXTICR4_EXTI15_PE AFIO_EXTICR4_EXTI15_PE_Msk /*!< PE[15] pin */
+#define AFIO_EXTICR4_EXTI15_PF_Pos (12U)
+#define AFIO_EXTICR4_EXTI15_PF_Msk (0x5U << AFIO_EXTICR4_EXTI15_PF_Pos) /*!< 0x00005000 */
+#define AFIO_EXTICR4_EXTI15_PF AFIO_EXTICR4_EXTI15_PF_Msk /*!< PF[15] pin */
+#define AFIO_EXTICR4_EXTI15_PG_Pos (13U)
+#define AFIO_EXTICR4_EXTI15_PG_Msk (0x3U << AFIO_EXTICR4_EXTI15_PG_Pos) /*!< 0x00006000 */
+#define AFIO_EXTICR4_EXTI15_PG AFIO_EXTICR4_EXTI15_PG_Msk /*!< PG[15] pin */
+
+/****************** Bit definition for AFIO_MAPR2 register ******************/
+
+
+
+/******************************************************************************/
+/* */
+/* SystemTick */
+/* */
+/******************************************************************************/
+
+/***************** Bit definition for SysTick_CTRL register *****************/
+#define SysTick_CTRL_ENABLE ((uint32_t)0x00000001) /*!< Counter enable */
+#define SysTick_CTRL_TICKINT ((uint32_t)0x00000002) /*!< Counting down to 0 pends the SysTick handler */
+#define SysTick_CTRL_CLKSOURCE ((uint32_t)0x00000004) /*!< Clock source */
+#define SysTick_CTRL_COUNTFLAG ((uint32_t)0x00010000) /*!< Count Flag */
+
+/***************** Bit definition for SysTick_LOAD register *****************/
+#define SysTick_LOAD_RELOAD ((uint32_t)0x00FFFFFF) /*!< Value to load into the SysTick Current Value Register when the counter reaches 0 */
+
+/***************** Bit definition for SysTick_VAL register ******************/
+#define SysTick_VAL_CURRENT ((uint32_t)0x00FFFFFF) /*!< Current value at the time the register is accessed */
+
+/***************** Bit definition for SysTick_CALIB register ****************/
+#define SysTick_CALIB_TENMS ((uint32_t)0x00FFFFFF) /*!< Reload value to use for 10ms timing */
+#define SysTick_CALIB_SKEW ((uint32_t)0x40000000) /*!< Calibration value is not exactly 10 ms */
+#define SysTick_CALIB_NOREF ((uint32_t)0x80000000) /*!< The reference clock is not provided */
+
+/******************************************************************************/
+/* */
+/* Nested Vectored Interrupt Controller */
+/* */
+/******************************************************************************/
+
+/****************** Bit definition for NVIC_ISER register *******************/
+#define NVIC_ISER_SETENA_Pos (0U)
+#define NVIC_ISER_SETENA_Msk (0xFFFFFFFFU << NVIC_ISER_SETENA_Pos) /*!< 0xFFFFFFFF */
+#define NVIC_ISER_SETENA NVIC_ISER_SETENA_Msk /*!< Interrupt set enable bits */
+#define NVIC_ISER_SETENA_0 (0x00000001U << NVIC_ISER_SETENA_Pos) /*!< 0x00000001 */
+#define NVIC_ISER_SETENA_1 (0x00000002U << NVIC_ISER_SETENA_Pos) /*!< 0x00000002 */
+#define NVIC_ISER_SETENA_2 (0x00000004U << NVIC_ISER_SETENA_Pos) /*!< 0x00000004 */
+#define NVIC_ISER_SETENA_3 (0x00000008U << NVIC_ISER_SETENA_Pos) /*!< 0x00000008 */
+#define NVIC_ISER_SETENA_4 (0x00000010U << NVIC_ISER_SETENA_Pos) /*!< 0x00000010 */
+#define NVIC_ISER_SETENA_5 (0x00000020U << NVIC_ISER_SETENA_Pos) /*!< 0x00000020 */
+#define NVIC_ISER_SETENA_6 (0x00000040U << NVIC_ISER_SETENA_Pos) /*!< 0x00000040 */
+#define NVIC_ISER_SETENA_7 (0x00000080U << NVIC_ISER_SETENA_Pos) /*!< 0x00000080 */
+#define NVIC_ISER_SETENA_8 (0x00000100U << NVIC_ISER_SETENA_Pos) /*!< 0x00000100 */
+#define NVIC_ISER_SETENA_9 (0x00000200U << NVIC_ISER_SETENA_Pos) /*!< 0x00000200 */
+#define NVIC_ISER_SETENA_10 (0x00000400U << NVIC_ISER_SETENA_Pos) /*!< 0x00000400 */
+#define NVIC_ISER_SETENA_11 (0x00000800U << NVIC_ISER_SETENA_Pos) /*!< 0x00000800 */
+#define NVIC_ISER_SETENA_12 (0x00001000U << NVIC_ISER_SETENA_Pos) /*!< 0x00001000 */
+#define NVIC_ISER_SETENA_13 (0x00002000U << NVIC_ISER_SETENA_Pos) /*!< 0x00002000 */
+#define NVIC_ISER_SETENA_14 (0x00004000U << NVIC_ISER_SETENA_Pos) /*!< 0x00004000 */
+#define NVIC_ISER_SETENA_15 (0x00008000U << NVIC_ISER_SETENA_Pos) /*!< 0x00008000 */
+#define NVIC_ISER_SETENA_16 (0x00010000U << NVIC_ISER_SETENA_Pos) /*!< 0x00010000 */
+#define NVIC_ISER_SETENA_17 (0x00020000U << NVIC_ISER_SETENA_Pos) /*!< 0x00020000 */
+#define NVIC_ISER_SETENA_18 (0x00040000U << NVIC_ISER_SETENA_Pos) /*!< 0x00040000 */
+#define NVIC_ISER_SETENA_19 (0x00080000U << NVIC_ISER_SETENA_Pos) /*!< 0x00080000 */
+#define NVIC_ISER_SETENA_20 (0x00100000U << NVIC_ISER_SETENA_Pos) /*!< 0x00100000 */
+#define NVIC_ISER_SETENA_21 (0x00200000U << NVIC_ISER_SETENA_Pos) /*!< 0x00200000 */
+#define NVIC_ISER_SETENA_22 (0x00400000U << NVIC_ISER_SETENA_Pos) /*!< 0x00400000 */
+#define NVIC_ISER_SETENA_23 (0x00800000U << NVIC_ISER_SETENA_Pos) /*!< 0x00800000 */
+#define NVIC_ISER_SETENA_24 (0x01000000U << NVIC_ISER_SETENA_Pos) /*!< 0x01000000 */
+#define NVIC_ISER_SETENA_25 (0x02000000U << NVIC_ISER_SETENA_Pos) /*!< 0x02000000 */
+#define NVIC_ISER_SETENA_26 (0x04000000U << NVIC_ISER_SETENA_Pos) /*!< 0x04000000 */
+#define NVIC_ISER_SETENA_27 (0x08000000U << NVIC_ISER_SETENA_Pos) /*!< 0x08000000 */
+#define NVIC_ISER_SETENA_28 (0x10000000U << NVIC_ISER_SETENA_Pos) /*!< 0x10000000 */
+#define NVIC_ISER_SETENA_29 (0x20000000U << NVIC_ISER_SETENA_Pos) /*!< 0x20000000 */
+#define NVIC_ISER_SETENA_30 (0x40000000U << NVIC_ISER_SETENA_Pos) /*!< 0x40000000 */
+#define NVIC_ISER_SETENA_31 (0x80000000U << NVIC_ISER_SETENA_Pos) /*!< 0x80000000 */
+
+/****************** Bit definition for NVIC_ICER register *******************/
+#define NVIC_ICER_CLRENA_Pos (0U)
+#define NVIC_ICER_CLRENA_Msk (0xFFFFFFFFU << NVIC_ICER_CLRENA_Pos) /*!< 0xFFFFFFFF */
+#define NVIC_ICER_CLRENA NVIC_ICER_CLRENA_Msk /*!< Interrupt clear-enable bits */
+#define NVIC_ICER_CLRENA_0 (0x00000001U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000001 */
+#define NVIC_ICER_CLRENA_1 (0x00000002U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000002 */
+#define NVIC_ICER_CLRENA_2 (0x00000004U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000004 */
+#define NVIC_ICER_CLRENA_3 (0x00000008U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000008 */
+#define NVIC_ICER_CLRENA_4 (0x00000010U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000010 */
+#define NVIC_ICER_CLRENA_5 (0x00000020U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000020 */
+#define NVIC_ICER_CLRENA_6 (0x00000040U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000040 */
+#define NVIC_ICER_CLRENA_7 (0x00000080U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000080 */
+#define NVIC_ICER_CLRENA_8 (0x00000100U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000100 */
+#define NVIC_ICER_CLRENA_9 (0x00000200U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000200 */
+#define NVIC_ICER_CLRENA_10 (0x00000400U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000400 */
+#define NVIC_ICER_CLRENA_11 (0x00000800U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000800 */
+#define NVIC_ICER_CLRENA_12 (0x00001000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00001000 */
+#define NVIC_ICER_CLRENA_13 (0x00002000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00002000 */
+#define NVIC_ICER_CLRENA_14 (0x00004000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00004000 */
+#define NVIC_ICER_CLRENA_15 (0x00008000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00008000 */
+#define NVIC_ICER_CLRENA_16 (0x00010000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00010000 */
+#define NVIC_ICER_CLRENA_17 (0x00020000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00020000 */
+#define NVIC_ICER_CLRENA_18 (0x00040000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00040000 */
+#define NVIC_ICER_CLRENA_19 (0x00080000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00080000 */
+#define NVIC_ICER_CLRENA_20 (0x00100000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00100000 */
+#define NVIC_ICER_CLRENA_21 (0x00200000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00200000 */
+#define NVIC_ICER_CLRENA_22 (0x00400000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00400000 */
+#define NVIC_ICER_CLRENA_23 (0x00800000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00800000 */
+#define NVIC_ICER_CLRENA_24 (0x01000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x01000000 */
+#define NVIC_ICER_CLRENA_25 (0x02000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x02000000 */
+#define NVIC_ICER_CLRENA_26 (0x04000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x04000000 */
+#define NVIC_ICER_CLRENA_27 (0x08000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x08000000 */
+#define NVIC_ICER_CLRENA_28 (0x10000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x10000000 */
+#define NVIC_ICER_CLRENA_29 (0x20000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x20000000 */
+#define NVIC_ICER_CLRENA_30 (0x40000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x40000000 */
+#define NVIC_ICER_CLRENA_31 (0x80000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x80000000 */
+
+/****************** Bit definition for NVIC_ISPR register *******************/
+#define NVIC_ISPR_SETPEND_Pos (0U)
+#define NVIC_ISPR_SETPEND_Msk (0xFFFFFFFFU << NVIC_ISPR_SETPEND_Pos) /*!< 0xFFFFFFFF */
+#define NVIC_ISPR_SETPEND NVIC_ISPR_SETPEND_Msk /*!< Interrupt set-pending bits */
+#define NVIC_ISPR_SETPEND_0 (0x00000001U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000001 */
+#define NVIC_ISPR_SETPEND_1 (0x00000002U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000002 */
+#define NVIC_ISPR_SETPEND_2 (0x00000004U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000004 */
+#define NVIC_ISPR_SETPEND_3 (0x00000008U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000008 */
+#define NVIC_ISPR_SETPEND_4 (0x00000010U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000010 */
+#define NVIC_ISPR_SETPEND_5 (0x00000020U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000020 */
+#define NVIC_ISPR_SETPEND_6 (0x00000040U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000040 */
+#define NVIC_ISPR_SETPEND_7 (0x00000080U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000080 */
+#define NVIC_ISPR_SETPEND_8 (0x00000100U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000100 */
+#define NVIC_ISPR_SETPEND_9 (0x00000200U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000200 */
+#define NVIC_ISPR_SETPEND_10 (0x00000400U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000400 */
+#define NVIC_ISPR_SETPEND_11 (0x00000800U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000800 */
+#define NVIC_ISPR_SETPEND_12 (0x00001000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00001000 */
+#define NVIC_ISPR_SETPEND_13 (0x00002000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00002000 */
+#define NVIC_ISPR_SETPEND_14 (0x00004000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00004000 */
+#define NVIC_ISPR_SETPEND_15 (0x00008000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00008000 */
+#define NVIC_ISPR_SETPEND_16 (0x00010000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00010000 */
+#define NVIC_ISPR_SETPEND_17 (0x00020000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00020000 */
+#define NVIC_ISPR_SETPEND_18 (0x00040000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00040000 */
+#define NVIC_ISPR_SETPEND_19 (0x00080000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00080000 */
+#define NVIC_ISPR_SETPEND_20 (0x00100000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00100000 */
+#define NVIC_ISPR_SETPEND_21 (0x00200000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00200000 */
+#define NVIC_ISPR_SETPEND_22 (0x00400000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00400000 */
+#define NVIC_ISPR_SETPEND_23 (0x00800000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00800000 */
+#define NVIC_ISPR_SETPEND_24 (0x01000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x01000000 */
+#define NVIC_ISPR_SETPEND_25 (0x02000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x02000000 */
+#define NVIC_ISPR_SETPEND_26 (0x04000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x04000000 */
+#define NVIC_ISPR_SETPEND_27 (0x08000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x08000000 */
+#define NVIC_ISPR_SETPEND_28 (0x10000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x10000000 */
+#define NVIC_ISPR_SETPEND_29 (0x20000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x20000000 */
+#define NVIC_ISPR_SETPEND_30 (0x40000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x40000000 */
+#define NVIC_ISPR_SETPEND_31 (0x80000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x80000000 */
+
+/****************** Bit definition for NVIC_ICPR register *******************/
+#define NVIC_ICPR_CLRPEND_Pos (0U)
+#define NVIC_ICPR_CLRPEND_Msk (0xFFFFFFFFU << NVIC_ICPR_CLRPEND_Pos) /*!< 0xFFFFFFFF */
+#define NVIC_ICPR_CLRPEND NVIC_ICPR_CLRPEND_Msk /*!< Interrupt clear-pending bits */
+#define NVIC_ICPR_CLRPEND_0 (0x00000001U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000001 */
+#define NVIC_ICPR_CLRPEND_1 (0x00000002U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000002 */
+#define NVIC_ICPR_CLRPEND_2 (0x00000004U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000004 */
+#define NVIC_ICPR_CLRPEND_3 (0x00000008U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000008 */
+#define NVIC_ICPR_CLRPEND_4 (0x00000010U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000010 */
+#define NVIC_ICPR_CLRPEND_5 (0x00000020U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000020 */
+#define NVIC_ICPR_CLRPEND_6 (0x00000040U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000040 */
+#define NVIC_ICPR_CLRPEND_7 (0x00000080U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000080 */
+#define NVIC_ICPR_CLRPEND_8 (0x00000100U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000100 */
+#define NVIC_ICPR_CLRPEND_9 (0x00000200U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000200 */
+#define NVIC_ICPR_CLRPEND_10 (0x00000400U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000400 */
+#define NVIC_ICPR_CLRPEND_11 (0x00000800U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000800 */
+#define NVIC_ICPR_CLRPEND_12 (0x00001000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00001000 */
+#define NVIC_ICPR_CLRPEND_13 (0x00002000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00002000 */
+#define NVIC_ICPR_CLRPEND_14 (0x00004000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00004000 */
+#define NVIC_ICPR_CLRPEND_15 (0x00008000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00008000 */
+#define NVIC_ICPR_CLRPEND_16 (0x00010000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00010000 */
+#define NVIC_ICPR_CLRPEND_17 (0x00020000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00020000 */
+#define NVIC_ICPR_CLRPEND_18 (0x00040000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00040000 */
+#define NVIC_ICPR_CLRPEND_19 (0x00080000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00080000 */
+#define NVIC_ICPR_CLRPEND_20 (0x00100000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00100000 */
+#define NVIC_ICPR_CLRPEND_21 (0x00200000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00200000 */
+#define NVIC_ICPR_CLRPEND_22 (0x00400000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00400000 */
+#define NVIC_ICPR_CLRPEND_23 (0x00800000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00800000 */
+#define NVIC_ICPR_CLRPEND_24 (0x01000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x01000000 */
+#define NVIC_ICPR_CLRPEND_25 (0x02000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x02000000 */
+#define NVIC_ICPR_CLRPEND_26 (0x04000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x04000000 */
+#define NVIC_ICPR_CLRPEND_27 (0x08000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x08000000 */
+#define NVIC_ICPR_CLRPEND_28 (0x10000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x10000000 */
+#define NVIC_ICPR_CLRPEND_29 (0x20000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x20000000 */
+#define NVIC_ICPR_CLRPEND_30 (0x40000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x40000000 */
+#define NVIC_ICPR_CLRPEND_31 (0x80000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x80000000 */
+
+/****************** Bit definition for NVIC_IABR register *******************/
+#define NVIC_IABR_ACTIVE_Pos (0U)
+#define NVIC_IABR_ACTIVE_Msk (0xFFFFFFFFU << NVIC_IABR_ACTIVE_Pos) /*!< 0xFFFFFFFF */
+#define NVIC_IABR_ACTIVE NVIC_IABR_ACTIVE_Msk /*!< Interrupt active flags */
+#define NVIC_IABR_ACTIVE_0 (0x00000001U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000001 */
+#define NVIC_IABR_ACTIVE_1 (0x00000002U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000002 */
+#define NVIC_IABR_ACTIVE_2 (0x00000004U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000004 */
+#define NVIC_IABR_ACTIVE_3 (0x00000008U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000008 */
+#define NVIC_IABR_ACTIVE_4 (0x00000010U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000010 */
+#define NVIC_IABR_ACTIVE_5 (0x00000020U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000020 */
+#define NVIC_IABR_ACTIVE_6 (0x00000040U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000040 */
+#define NVIC_IABR_ACTIVE_7 (0x00000080U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000080 */
+#define NVIC_IABR_ACTIVE_8 (0x00000100U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000100 */
+#define NVIC_IABR_ACTIVE_9 (0x00000200U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000200 */
+#define NVIC_IABR_ACTIVE_10 (0x00000400U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000400 */
+#define NVIC_IABR_ACTIVE_11 (0x00000800U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000800 */
+#define NVIC_IABR_ACTIVE_12 (0x00001000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00001000 */
+#define NVIC_IABR_ACTIVE_13 (0x00002000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00002000 */
+#define NVIC_IABR_ACTIVE_14 (0x00004000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00004000 */
+#define NVIC_IABR_ACTIVE_15 (0x00008000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00008000 */
+#define NVIC_IABR_ACTIVE_16 (0x00010000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00010000 */
+#define NVIC_IABR_ACTIVE_17 (0x00020000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00020000 */
+#define NVIC_IABR_ACTIVE_18 (0x00040000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00040000 */
+#define NVIC_IABR_ACTIVE_19 (0x00080000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00080000 */
+#define NVIC_IABR_ACTIVE_20 (0x00100000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00100000 */
+#define NVIC_IABR_ACTIVE_21 (0x00200000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00200000 */
+#define NVIC_IABR_ACTIVE_22 (0x00400000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00400000 */
+#define NVIC_IABR_ACTIVE_23 (0x00800000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00800000 */
+#define NVIC_IABR_ACTIVE_24 (0x01000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x01000000 */
+#define NVIC_IABR_ACTIVE_25 (0x02000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x02000000 */
+#define NVIC_IABR_ACTIVE_26 (0x04000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x04000000 */
+#define NVIC_IABR_ACTIVE_27 (0x08000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x08000000 */
+#define NVIC_IABR_ACTIVE_28 (0x10000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x10000000 */
+#define NVIC_IABR_ACTIVE_29 (0x20000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x20000000 */
+#define NVIC_IABR_ACTIVE_30 (0x40000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x40000000 */
+#define NVIC_IABR_ACTIVE_31 (0x80000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x80000000 */
+
+/****************** Bit definition for NVIC_PRI0 register *******************/
+#define NVIC_IPR0_PRI_0 ((uint32_t)0x000000FF) /*!< Priority of interrupt 0 */
+#define NVIC_IPR0_PRI_1 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 1 */
+#define NVIC_IPR0_PRI_2 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 2 */
+#define NVIC_IPR0_PRI_3 ((uint32_t)0xFF000000) /*!< Priority of interrupt 3 */
+
+/****************** Bit definition for NVIC_PRI1 register *******************/
+#define NVIC_IPR1_PRI_4 ((uint32_t)0x000000FF) /*!< Priority of interrupt 4 */
+#define NVIC_IPR1_PRI_5 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 5 */
+#define NVIC_IPR1_PRI_6 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 6 */
+#define NVIC_IPR1_PRI_7 ((uint32_t)0xFF000000) /*!< Priority of interrupt 7 */
+
+/****************** Bit definition for NVIC_PRI2 register *******************/
+#define NVIC_IPR2_PRI_8 ((uint32_t)0x000000FF) /*!< Priority of interrupt 8 */
+#define NVIC_IPR2_PRI_9 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 9 */
+#define NVIC_IPR2_PRI_10 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 10 */
+#define NVIC_IPR2_PRI_11 ((uint32_t)0xFF000000) /*!< Priority of interrupt 11 */
+
+/****************** Bit definition for NVIC_PRI3 register *******************/
+#define NVIC_IPR3_PRI_12 ((uint32_t)0x000000FF) /*!< Priority of interrupt 12 */
+#define NVIC_IPR3_PRI_13 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 13 */
+#define NVIC_IPR3_PRI_14 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 14 */
+#define NVIC_IPR3_PRI_15 ((uint32_t)0xFF000000) /*!< Priority of interrupt 15 */
+
+/****************** Bit definition for NVIC_PRI4 register *******************/
+#define NVIC_IPR4_PRI_16 ((uint32_t)0x000000FF) /*!< Priority of interrupt 16 */
+#define NVIC_IPR4_PRI_17 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 17 */
+#define NVIC_IPR4_PRI_18 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 18 */
+#define NVIC_IPR4_PRI_19 ((uint32_t)0xFF000000) /*!< Priority of interrupt 19 */
+
+/****************** Bit definition for NVIC_PRI5 register *******************/
+#define NVIC_IPR5_PRI_20 ((uint32_t)0x000000FF) /*!< Priority of interrupt 20 */
+#define NVIC_IPR5_PRI_21 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 21 */
+#define NVIC_IPR5_PRI_22 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 22 */
+#define NVIC_IPR5_PRI_23 ((uint32_t)0xFF000000) /*!< Priority of interrupt 23 */
+
+/****************** Bit definition for NVIC_PRI6 register *******************/
+#define NVIC_IPR6_PRI_24 ((uint32_t)0x000000FF) /*!< Priority of interrupt 24 */
+#define NVIC_IPR6_PRI_25 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 25 */
+#define NVIC_IPR6_PRI_26 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 26 */
+#define NVIC_IPR6_PRI_27 ((uint32_t)0xFF000000) /*!< Priority of interrupt 27 */
+
+/****************** Bit definition for NVIC_PRI7 register *******************/
+#define NVIC_IPR7_PRI_28 ((uint32_t)0x000000FF) /*!< Priority of interrupt 28 */
+#define NVIC_IPR7_PRI_29 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 29 */
+#define NVIC_IPR7_PRI_30 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 30 */
+#define NVIC_IPR7_PRI_31 ((uint32_t)0xFF000000) /*!< Priority of interrupt 31 */
+
+/****************** Bit definition for SCB_CPUID register *******************/
+#define SCB_CPUID_REVISION ((uint32_t)0x0000000F) /*!< Implementation defined revision number */
+#define SCB_CPUID_PARTNO ((uint32_t)0x0000FFF0) /*!< Number of processor within family */
+#define SCB_CPUID_Constant ((uint32_t)0x000F0000) /*!< Reads as 0x0F */
+#define SCB_CPUID_VARIANT ((uint32_t)0x00F00000) /*!< Implementation defined variant number */
+#define SCB_CPUID_IMPLEMENTER ((uint32_t)0xFF000000) /*!< Implementer code. ARM is 0x41 */
+
+/******************* Bit definition for SCB_ICSR register *******************/
+#define SCB_ICSR_VECTACTIVE ((uint32_t)0x000001FF) /*!< Active ISR number field */
+#define SCB_ICSR_RETTOBASE ((uint32_t)0x00000800) /*!< All active exceptions minus the IPSR_current_exception yields the empty set */
+#define SCB_ICSR_VECTPENDING ((uint32_t)0x003FF000) /*!< Pending ISR number field */
+#define SCB_ICSR_ISRPENDING ((uint32_t)0x00400000) /*!< Interrupt pending flag */
+#define SCB_ICSR_ISRPREEMPT ((uint32_t)0x00800000) /*!< It indicates that a pending interrupt becomes active in the next running cycle */
+#define SCB_ICSR_PENDSTCLR ((uint32_t)0x02000000) /*!< Clear pending SysTick bit */
+#define SCB_ICSR_PENDSTSET ((uint32_t)0x04000000) /*!< Set pending SysTick bit */
+#define SCB_ICSR_PENDSVCLR ((uint32_t)0x08000000) /*!< Clear pending pendSV bit */
+#define SCB_ICSR_PENDSVSET ((uint32_t)0x10000000) /*!< Set pending pendSV bit */
+#define SCB_ICSR_NMIPENDSET ((uint32_t)0x80000000) /*!< Set pending NMI bit */
+
+/******************* Bit definition for SCB_VTOR register *******************/
+#define SCB_VTOR_TBLOFF ((uint32_t)0x1FFFFF80) /*!< Vector table base offset field */
+#define SCB_VTOR_TBLBASE ((uint32_t)0x20000000) /*!< Table base in code(0) or RAM(1) */
+
+/*!<***************** Bit definition for SCB_AIRCR register *******************/
+#define SCB_AIRCR_VECTRESET ((uint32_t)0x00000001) /*!< System Reset bit */
+#define SCB_AIRCR_VECTCLRACTIVE ((uint32_t)0x00000002) /*!< Clear active vector bit */
+#define SCB_AIRCR_SYSRESETREQ ((uint32_t)0x00000004) /*!< Requests chip control logic to generate a reset */
+
+#define SCB_AIRCR_PRIGROUP ((uint32_t)0x00000700) /*!< PRIGROUP[2:0] bits (Priority group) */
+#define SCB_AIRCR_PRIGROUP_0 ((uint32_t)0x00000100) /*!< Bit 0 */
+#define SCB_AIRCR_PRIGROUP_1 ((uint32_t)0x00000200) /*!< Bit 1 */
+#define SCB_AIRCR_PRIGROUP_2 ((uint32_t)0x00000400) /*!< Bit 2 */
+
+/* prority group configuration */
+#define SCB_AIRCR_PRIGROUP0 ((uint32_t)0x00000000) /*!< Priority group=0 (7 bits of pre-emption priority, 1 bit of subpriority) */
+#define SCB_AIRCR_PRIGROUP1 ((uint32_t)0x00000100) /*!< Priority group=1 (6 bits of pre-emption priority, 2 bits of subpriority) */
+#define SCB_AIRCR_PRIGROUP2 ((uint32_t)0x00000200) /*!< Priority group=2 (5 bits of pre-emption priority, 3 bits of subpriority) */
+#define SCB_AIRCR_PRIGROUP3 ((uint32_t)0x00000300) /*!< Priority group=3 (4 bits of pre-emption priority, 4 bits of subpriority) */
+#define SCB_AIRCR_PRIGROUP4 ((uint32_t)0x00000400) /*!< Priority group=4 (3 bits of pre-emption priority, 5 bits of subpriority) */
+#define SCB_AIRCR_PRIGROUP5 ((uint32_t)0x00000500) /*!< Priority group=5 (2 bits of pre-emption priority, 6 bits of subpriority) */
+#define SCB_AIRCR_PRIGROUP6 ((uint32_t)0x00000600) /*!< Priority group=6 (1 bit of pre-emption priority, 7 bits of subpriority) */
+#define SCB_AIRCR_PRIGROUP7 ((uint32_t)0x00000700) /*!< Priority group=7 (no pre-emption priority, 8 bits of subpriority) */
+
+#define SCB_AIRCR_ENDIANESS ((uint32_t)0x00008000) /*!< Data endianness bit */
+#define SCB_AIRCR_VECTKEY ((uint32_t)0xFFFF0000) /*!< Register key (VECTKEY) - Reads as 0xFA05 (VECTKEYSTAT) */
+
+/******************* Bit definition for SCB_SCR register ********************/
+#define SCB_SCR_SLEEPONEXIT ((uint32_t)0x00000002) /*!< Sleep on exit bit */
+#define SCB_SCR_SLEEPDEEP ((uint32_t)0x00000004) /*!< Sleep deep bit */
+#define SCB_SCR_SEVONPEND ((uint32_t)0x00000010) /*!< Wake up from WFE */
+
+/******************** Bit definition for SCB_CCR register *******************/
+#define SCB_CCR_NONBASETHRDENA ((uint32_t)0x00000001) /*!< Thread mode can be entered from any level in Handler mode by controlled return value */
+#define SCB_CCR_USERSETMPEND ((uint32_t)0x00000002) /*!< Enables user code to write the Software Trigger Interrupt register to trigger (pend) a Main exception */
+#define SCB_CCR_UNALIGN_TRP ((uint32_t)0x00000008) /*!< Trap for unaligned access */
+#define SCB_CCR_DIV_0_TRP ((uint32_t)0x00000010) /*!< Trap on Divide by 0 */
+#define SCB_CCR_BFHFNMIGN ((uint32_t)0x00000100) /*!< Handlers running at priority -1 and -2 */
+#define SCB_CCR_STKALIGN ((uint32_t)0x00000200) /*!< On exception entry, the SP used prior to the exception is adjusted to be 8-byte aligned */
+
+/******************* Bit definition for SCB_SHPR register ********************/
+#define SCB_SHPR_PRI_N_Pos (0U)
+#define SCB_SHPR_PRI_N_Msk (0xFFU << SCB_SHPR_PRI_N_Pos) /*!< 0x000000FF */
+#define SCB_SHPR_PRI_N SCB_SHPR_PRI_N_Msk /*!< Priority of system handler 4,8, and 12. Mem Manage, reserved and Debug Monitor */
+#define SCB_SHPR_PRI_N1_Pos (8U)
+#define SCB_SHPR_PRI_N1_Msk (0xFFU << SCB_SHPR_PRI_N1_Pos) /*!< 0x0000FF00 */
+#define SCB_SHPR_PRI_N1 SCB_SHPR_PRI_N1_Msk /*!< Priority of system handler 5,9, and 13. Bus Fault, reserved and reserved */
+#define SCB_SHPR_PRI_N2_Pos (16U)
+#define SCB_SHPR_PRI_N2_Msk (0xFFU << SCB_SHPR_PRI_N2_Pos) /*!< 0x00FF0000 */
+#define SCB_SHPR_PRI_N2 SCB_SHPR_PRI_N2_Msk /*!< Priority of system handler 6,10, and 14. Usage Fault, reserved and PendSV */
+#define SCB_SHPR_PRI_N3_Pos (24U)
+#define SCB_SHPR_PRI_N3_Msk (0xFFU << SCB_SHPR_PRI_N3_Pos) /*!< 0xFF000000 */
+#define SCB_SHPR_PRI_N3 SCB_SHPR_PRI_N3_Msk /*!< Priority of system handler 7,11, and 15. Reserved, SVCall and SysTick */
+
+/****************** Bit definition for SCB_SHCSR register *******************/
+#define SCB_SHCSR_MEMFAULTACT ((uint32_t)0x00000001) /*!< MemManage is active */
+#define SCB_SHCSR_BUSFAULTACT ((uint32_t)0x00000002) /*!< BusFault is active */
+#define SCB_SHCSR_USGFAULTACT ((uint32_t)0x00000008) /*!< UsageFault is active */
+#define SCB_SHCSR_SVCALLACT ((uint32_t)0x00000080) /*!< SVCall is active */
+#define SCB_SHCSR_MONITORACT ((uint32_t)0x00000100) /*!< Monitor is active */
+#define SCB_SHCSR_PENDSVACT ((uint32_t)0x00000400) /*!< PendSV is active */
+#define SCB_SHCSR_SYSTICKACT ((uint32_t)0x00000800) /*!< SysTick is active */
+#define SCB_SHCSR_USGFAULTPENDED ((uint32_t)0x00001000) /*!< Usage Fault is pended */
+#define SCB_SHCSR_MEMFAULTPENDED ((uint32_t)0x00002000) /*!< MemManage is pended */
+#define SCB_SHCSR_BUSFAULTPENDED ((uint32_t)0x00004000) /*!< Bus Fault is pended */
+#define SCB_SHCSR_SVCALLPENDED ((uint32_t)0x00008000) /*!< SVCall is pended */
+#define SCB_SHCSR_MEMFAULTENA ((uint32_t)0x00010000) /*!< MemManage enable */
+#define SCB_SHCSR_BUSFAULTENA ((uint32_t)0x00020000) /*!< Bus Fault enable */
+#define SCB_SHCSR_USGFAULTENA ((uint32_t)0x00040000) /*!< UsageFault enable */
+
+/******************* Bit definition for SCB_CFSR register *******************/
+/*!< MFSR */
+#define SCB_CFSR_IACCVIOL_Pos (0U)
+#define SCB_CFSR_IACCVIOL_Msk (0x1U << SCB_CFSR_IACCVIOL_Pos) /*!< 0x00000001 */
+#define SCB_CFSR_IACCVIOL SCB_CFSR_IACCVIOL_Msk /*!< Instruction access violation */
+#define SCB_CFSR_DACCVIOL_Pos (1U)
+#define SCB_CFSR_DACCVIOL_Msk (0x1U << SCB_CFSR_DACCVIOL_Pos) /*!< 0x00000002 */
+#define SCB_CFSR_DACCVIOL SCB_CFSR_DACCVIOL_Msk /*!< Data access violation */
+#define SCB_CFSR_MUNSTKERR_Pos (3U)
+#define SCB_CFSR_MUNSTKERR_Msk (0x1U << SCB_CFSR_MUNSTKERR_Pos) /*!< 0x00000008 */
+#define SCB_CFSR_MUNSTKERR SCB_CFSR_MUNSTKERR_Msk /*!< Unstacking error */
+#define SCB_CFSR_MSTKERR_Pos (4U)
+#define SCB_CFSR_MSTKERR_Msk (0x1U << SCB_CFSR_MSTKERR_Pos) /*!< 0x00000010 */
+#define SCB_CFSR_MSTKERR SCB_CFSR_MSTKERR_Msk /*!< Stacking error */
+#define SCB_CFSR_MMARVALID_Pos (7U)
+#define SCB_CFSR_MMARVALID_Msk (0x1U << SCB_CFSR_MMARVALID_Pos) /*!< 0x00000080 */
+#define SCB_CFSR_MMARVALID SCB_CFSR_MMARVALID_Msk /*!< Memory Manage Address Register address valid flag */
+/*!< BFSR */
+#define SCB_CFSR_IBUSERR_Pos (8U)
+#define SCB_CFSR_IBUSERR_Msk (0x1U << SCB_CFSR_IBUSERR_Pos) /*!< 0x00000100 */
+#define SCB_CFSR_IBUSERR SCB_CFSR_IBUSERR_Msk /*!< Instruction bus error flag */
+#define SCB_CFSR_PRECISERR_Pos (9U)
+#define SCB_CFSR_PRECISERR_Msk (0x1U << SCB_CFSR_PRECISERR_Pos) /*!< 0x00000200 */
+#define SCB_CFSR_PRECISERR SCB_CFSR_PRECISERR_Msk /*!< Precise data bus error */
+#define SCB_CFSR_IMPRECISERR_Pos (10U)
+#define SCB_CFSR_IMPRECISERR_Msk (0x1U << SCB_CFSR_IMPRECISERR_Pos) /*!< 0x00000400 */
+#define SCB_CFSR_IMPRECISERR SCB_CFSR_IMPRECISERR_Msk /*!< Imprecise data bus error */
+#define SCB_CFSR_UNSTKERR_Pos (11U)
+#define SCB_CFSR_UNSTKERR_Msk (0x1U << SCB_CFSR_UNSTKERR_Pos) /*!< 0x00000800 */
+#define SCB_CFSR_UNSTKERR SCB_CFSR_UNSTKERR_Msk /*!< Unstacking error */
+#define SCB_CFSR_STKERR_Pos (12U)
+#define SCB_CFSR_STKERR_Msk (0x1U << SCB_CFSR_STKERR_Pos) /*!< 0x00001000 */
+#define SCB_CFSR_STKERR SCB_CFSR_STKERR_Msk /*!< Stacking error */
+#define SCB_CFSR_BFARVALID_Pos (15U)
+#define SCB_CFSR_BFARVALID_Msk (0x1U << SCB_CFSR_BFARVALID_Pos) /*!< 0x00008000 */
+#define SCB_CFSR_BFARVALID SCB_CFSR_BFARVALID_Msk /*!< Bus Fault Address Register address valid flag */
+/*!< UFSR */
+#define SCB_CFSR_UNDEFINSTR_Pos (16U)
+#define SCB_CFSR_UNDEFINSTR_Msk (0x1U << SCB_CFSR_UNDEFINSTR_Pos) /*!< 0x00010000 */
+#define SCB_CFSR_UNDEFINSTR SCB_CFSR_UNDEFINSTR_Msk /*!< The processor attempt to execute an undefined instruction */
+#define SCB_CFSR_INVSTATE_Pos (17U)
+#define SCB_CFSR_INVSTATE_Msk (0x1U << SCB_CFSR_INVSTATE_Pos) /*!< 0x00020000 */
+#define SCB_CFSR_INVSTATE SCB_CFSR_INVSTATE_Msk /*!< Invalid combination of EPSR and instruction */
+#define SCB_CFSR_INVPC_Pos (18U)
+#define SCB_CFSR_INVPC_Msk (0x1U << SCB_CFSR_INVPC_Pos) /*!< 0x00040000 */
+#define SCB_CFSR_INVPC SCB_CFSR_INVPC_Msk /*!< Attempt to load EXC_RETURN into pc illegally */
+#define SCB_CFSR_NOCP_Pos (19U)
+#define SCB_CFSR_NOCP_Msk (0x1U << SCB_CFSR_NOCP_Pos) /*!< 0x00080000 */
+#define SCB_CFSR_NOCP SCB_CFSR_NOCP_Msk /*!< Attempt to use a coprocessor instruction */
+#define SCB_CFSR_UNALIGNED_Pos (24U)
+#define SCB_CFSR_UNALIGNED_Msk (0x1U << SCB_CFSR_UNALIGNED_Pos) /*!< 0x01000000 */
+#define SCB_CFSR_UNALIGNED SCB_CFSR_UNALIGNED_Msk /*!< Fault occurs when there is an attempt to make an unaligned memory access */
+#define SCB_CFSR_DIVBYZERO_Pos (25U)
+#define SCB_CFSR_DIVBYZERO_Msk (0x1U << SCB_CFSR_DIVBYZERO_Pos) /*!< 0x02000000 */
+#define SCB_CFSR_DIVBYZERO SCB_CFSR_DIVBYZERO_Msk /*!< Fault occurs when SDIV or DIV instruction is used with a divisor of 0 */
+
+/******************* Bit definition for SCB_HFSR register *******************/
+#define SCB_HFSR_VECTTBL ((uint32_t)0x00000002) /*!< Fault occurs because of vector table read on exception processing */
+#define SCB_HFSR_FORCED ((uint32_t)0x40000000) /*!< Hard Fault activated when a configurable Fault was received and cannot activate */
+#define SCB_HFSR_DEBUGEVT ((uint32_t)0x80000000) /*!< Fault related to debug */
+
+/******************* Bit definition for SCB_DFSR register *******************/
+#define SCB_DFSR_HALTED ((uint32_t)0x00000001) /*!< Halt request flag */
+#define SCB_DFSR_BKPT ((uint32_t)0x00000002) /*!< BKPT flag */
+#define SCB_DFSR_DWTTRAP ((uint32_t)0x00000004) /*!< Data Watchpoint and Trace (DWT) flag */
+#define SCB_DFSR_VCATCH ((uint32_t)0x00000008) /*!< Vector catch flag */
+#define SCB_DFSR_EXTERNAL ((uint32_t)0x00000010) /*!< External debug request flag */
+
+/******************* Bit definition for SCB_MMFAR register ******************/
+#define SCB_MMFAR_ADDRESS_Pos (0U)
+#define SCB_MMFAR_ADDRESS_Msk (0xFFFFFFFFU << SCB_MMFAR_ADDRESS_Pos) /*!< 0xFFFFFFFF */
+#define SCB_MMFAR_ADDRESS SCB_MMFAR_ADDRESS_Msk /*!< Mem Manage fault address field */
+
+/******************* Bit definition for SCB_BFAR register *******************/
+#define SCB_BFAR_ADDRESS_Pos (0U)
+#define SCB_BFAR_ADDRESS_Msk (0xFFFFFFFFU << SCB_BFAR_ADDRESS_Pos) /*!< 0xFFFFFFFF */
+#define SCB_BFAR_ADDRESS SCB_BFAR_ADDRESS_Msk /*!< Bus fault address field */
+
+/******************* Bit definition for SCB_afsr register *******************/
+#define SCB_AFSR_IMPDEF_Pos (0U)
+#define SCB_AFSR_IMPDEF_Msk (0xFFFFFFFFU << SCB_AFSR_IMPDEF_Pos) /*!< 0xFFFFFFFF */
+#define SCB_AFSR_IMPDEF SCB_AFSR_IMPDEF_Msk /*!< Implementation defined */
+
+/******************************************************************************/
+/* */
+/* External Interrupt/Event Controller */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for EXTI_IMR register *******************/
+#define EXTI_IMR_MR0_Pos (0U)
+#define EXTI_IMR_MR0_Msk (0x1U << EXTI_IMR_MR0_Pos) /*!< 0x00000001 */
+#define EXTI_IMR_MR0 EXTI_IMR_MR0_Msk /*!< Interrupt Mask on line 0 */
+#define EXTI_IMR_MR1_Pos (1U)
+#define EXTI_IMR_MR1_Msk (0x1U << EXTI_IMR_MR1_Pos) /*!< 0x00000002 */
+#define EXTI_IMR_MR1 EXTI_IMR_MR1_Msk /*!< Interrupt Mask on line 1 */
+#define EXTI_IMR_MR2_Pos (2U)
+#define EXTI_IMR_MR2_Msk (0x1U << EXTI_IMR_MR2_Pos) /*!< 0x00000004 */
+#define EXTI_IMR_MR2 EXTI_IMR_MR2_Msk /*!< Interrupt Mask on line 2 */
+#define EXTI_IMR_MR3_Pos (3U)
+#define EXTI_IMR_MR3_Msk (0x1U << EXTI_IMR_MR3_Pos) /*!< 0x00000008 */
+#define EXTI_IMR_MR3 EXTI_IMR_MR3_Msk /*!< Interrupt Mask on line 3 */
+#define EXTI_IMR_MR4_Pos (4U)
+#define EXTI_IMR_MR4_Msk (0x1U << EXTI_IMR_MR4_Pos) /*!< 0x00000010 */
+#define EXTI_IMR_MR4 EXTI_IMR_MR4_Msk /*!< Interrupt Mask on line 4 */
+#define EXTI_IMR_MR5_Pos (5U)
+#define EXTI_IMR_MR5_Msk (0x1U << EXTI_IMR_MR5_Pos) /*!< 0x00000020 */
+#define EXTI_IMR_MR5 EXTI_IMR_MR5_Msk /*!< Interrupt Mask on line 5 */
+#define EXTI_IMR_MR6_Pos (6U)
+#define EXTI_IMR_MR6_Msk (0x1U << EXTI_IMR_MR6_Pos) /*!< 0x00000040 */
+#define EXTI_IMR_MR6 EXTI_IMR_MR6_Msk /*!< Interrupt Mask on line 6 */
+#define EXTI_IMR_MR7_Pos (7U)
+#define EXTI_IMR_MR7_Msk (0x1U << EXTI_IMR_MR7_Pos) /*!< 0x00000080 */
+#define EXTI_IMR_MR7 EXTI_IMR_MR7_Msk /*!< Interrupt Mask on line 7 */
+#define EXTI_IMR_MR8_Pos (8U)
+#define EXTI_IMR_MR8_Msk (0x1U << EXTI_IMR_MR8_Pos) /*!< 0x00000100 */
+#define EXTI_IMR_MR8 EXTI_IMR_MR8_Msk /*!< Interrupt Mask on line 8 */
+#define EXTI_IMR_MR9_Pos (9U)
+#define EXTI_IMR_MR9_Msk (0x1U << EXTI_IMR_MR9_Pos) /*!< 0x00000200 */
+#define EXTI_IMR_MR9 EXTI_IMR_MR9_Msk /*!< Interrupt Mask on line 9 */
+#define EXTI_IMR_MR10_Pos (10U)
+#define EXTI_IMR_MR10_Msk (0x1U << EXTI_IMR_MR10_Pos) /*!< 0x00000400 */
+#define EXTI_IMR_MR10 EXTI_IMR_MR10_Msk /*!< Interrupt Mask on line 10 */
+#define EXTI_IMR_MR11_Pos (11U)
+#define EXTI_IMR_MR11_Msk (0x1U << EXTI_IMR_MR11_Pos) /*!< 0x00000800 */
+#define EXTI_IMR_MR11 EXTI_IMR_MR11_Msk /*!< Interrupt Mask on line 11 */
+#define EXTI_IMR_MR12_Pos (12U)
+#define EXTI_IMR_MR12_Msk (0x1U << EXTI_IMR_MR12_Pos) /*!< 0x00001000 */
+#define EXTI_IMR_MR12 EXTI_IMR_MR12_Msk /*!< Interrupt Mask on line 12 */
+#define EXTI_IMR_MR13_Pos (13U)
+#define EXTI_IMR_MR13_Msk (0x1U << EXTI_IMR_MR13_Pos) /*!< 0x00002000 */
+#define EXTI_IMR_MR13 EXTI_IMR_MR13_Msk /*!< Interrupt Mask on line 13 */
+#define EXTI_IMR_MR14_Pos (14U)
+#define EXTI_IMR_MR14_Msk (0x1U << EXTI_IMR_MR14_Pos) /*!< 0x00004000 */
+#define EXTI_IMR_MR14 EXTI_IMR_MR14_Msk /*!< Interrupt Mask on line 14 */
+#define EXTI_IMR_MR15_Pos (15U)
+#define EXTI_IMR_MR15_Msk (0x1U << EXTI_IMR_MR15_Pos) /*!< 0x00008000 */
+#define EXTI_IMR_MR15 EXTI_IMR_MR15_Msk /*!< Interrupt Mask on line 15 */
+#define EXTI_IMR_MR16_Pos (16U)
+#define EXTI_IMR_MR16_Msk (0x1U << EXTI_IMR_MR16_Pos) /*!< 0x00010000 */
+#define EXTI_IMR_MR16 EXTI_IMR_MR16_Msk /*!< Interrupt Mask on line 16 */
+#define EXTI_IMR_MR17_Pos (17U)
+#define EXTI_IMR_MR17_Msk (0x1U << EXTI_IMR_MR17_Pos) /*!< 0x00020000 */
+#define EXTI_IMR_MR17 EXTI_IMR_MR17_Msk /*!< Interrupt Mask on line 17 */
+#define EXTI_IMR_MR18_Pos (18U)
+#define EXTI_IMR_MR18_Msk (0x1U << EXTI_IMR_MR18_Pos) /*!< 0x00040000 */
+#define EXTI_IMR_MR18 EXTI_IMR_MR18_Msk /*!< Interrupt Mask on line 18 */
+#define EXTI_IMR_MR19_Pos (19U)
+#define EXTI_IMR_MR19_Msk (0x1U << EXTI_IMR_MR19_Pos) /*!< 0x00080000 */
+#define EXTI_IMR_MR19 EXTI_IMR_MR19_Msk /*!< Interrupt Mask on line 19 */
+
+/* References Defines */
+#define EXTI_IMR_IM0 EXTI_IMR_MR0
+#define EXTI_IMR_IM1 EXTI_IMR_MR1
+#define EXTI_IMR_IM2 EXTI_IMR_MR2
+#define EXTI_IMR_IM3 EXTI_IMR_MR3
+#define EXTI_IMR_IM4 EXTI_IMR_MR4
+#define EXTI_IMR_IM5 EXTI_IMR_MR5
+#define EXTI_IMR_IM6 EXTI_IMR_MR6
+#define EXTI_IMR_IM7 EXTI_IMR_MR7
+#define EXTI_IMR_IM8 EXTI_IMR_MR8
+#define EXTI_IMR_IM9 EXTI_IMR_MR9
+#define EXTI_IMR_IM10 EXTI_IMR_MR10
+#define EXTI_IMR_IM11 EXTI_IMR_MR11
+#define EXTI_IMR_IM12 EXTI_IMR_MR12
+#define EXTI_IMR_IM13 EXTI_IMR_MR13
+#define EXTI_IMR_IM14 EXTI_IMR_MR14
+#define EXTI_IMR_IM15 EXTI_IMR_MR15
+#define EXTI_IMR_IM16 EXTI_IMR_MR16
+#define EXTI_IMR_IM17 EXTI_IMR_MR17
+#define EXTI_IMR_IM18 EXTI_IMR_MR18
+#define EXTI_IMR_IM19 EXTI_IMR_MR19
+
+/******************* Bit definition for EXTI_EMR register *******************/
+#define EXTI_EMR_MR0_Pos (0U)
+#define EXTI_EMR_MR0_Msk (0x1U << EXTI_EMR_MR0_Pos) /*!< 0x00000001 */
+#define EXTI_EMR_MR0 EXTI_EMR_MR0_Msk /*!< Event Mask on line 0 */
+#define EXTI_EMR_MR1_Pos (1U)
+#define EXTI_EMR_MR1_Msk (0x1U << EXTI_EMR_MR1_Pos) /*!< 0x00000002 */
+#define EXTI_EMR_MR1 EXTI_EMR_MR1_Msk /*!< Event Mask on line 1 */
+#define EXTI_EMR_MR2_Pos (2U)
+#define EXTI_EMR_MR2_Msk (0x1U << EXTI_EMR_MR2_Pos) /*!< 0x00000004 */
+#define EXTI_EMR_MR2 EXTI_EMR_MR2_Msk /*!< Event Mask on line 2 */
+#define EXTI_EMR_MR3_Pos (3U)
+#define EXTI_EMR_MR3_Msk (0x1U << EXTI_EMR_MR3_Pos) /*!< 0x00000008 */
+#define EXTI_EMR_MR3 EXTI_EMR_MR3_Msk /*!< Event Mask on line 3 */
+#define EXTI_EMR_MR4_Pos (4U)
+#define EXTI_EMR_MR4_Msk (0x1U << EXTI_EMR_MR4_Pos) /*!< 0x00000010 */
+#define EXTI_EMR_MR4 EXTI_EMR_MR4_Msk /*!< Event Mask on line 4 */
+#define EXTI_EMR_MR5_Pos (5U)
+#define EXTI_EMR_MR5_Msk (0x1U << EXTI_EMR_MR5_Pos) /*!< 0x00000020 */
+#define EXTI_EMR_MR5 EXTI_EMR_MR5_Msk /*!< Event Mask on line 5 */
+#define EXTI_EMR_MR6_Pos (6U)
+#define EXTI_EMR_MR6_Msk (0x1U << EXTI_EMR_MR6_Pos) /*!< 0x00000040 */
+#define EXTI_EMR_MR6 EXTI_EMR_MR6_Msk /*!< Event Mask on line 6 */
+#define EXTI_EMR_MR7_Pos (7U)
+#define EXTI_EMR_MR7_Msk (0x1U << EXTI_EMR_MR7_Pos) /*!< 0x00000080 */
+#define EXTI_EMR_MR7 EXTI_EMR_MR7_Msk /*!< Event Mask on line 7 */
+#define EXTI_EMR_MR8_Pos (8U)
+#define EXTI_EMR_MR8_Msk (0x1U << EXTI_EMR_MR8_Pos) /*!< 0x00000100 */
+#define EXTI_EMR_MR8 EXTI_EMR_MR8_Msk /*!< Event Mask on line 8 */
+#define EXTI_EMR_MR9_Pos (9U)
+#define EXTI_EMR_MR9_Msk (0x1U << EXTI_EMR_MR9_Pos) /*!< 0x00000200 */
+#define EXTI_EMR_MR9 EXTI_EMR_MR9_Msk /*!< Event Mask on line 9 */
+#define EXTI_EMR_MR10_Pos (10U)
+#define EXTI_EMR_MR10_Msk (0x1U << EXTI_EMR_MR10_Pos) /*!< 0x00000400 */
+#define EXTI_EMR_MR10 EXTI_EMR_MR10_Msk /*!< Event Mask on line 10 */
+#define EXTI_EMR_MR11_Pos (11U)
+#define EXTI_EMR_MR11_Msk (0x1U << EXTI_EMR_MR11_Pos) /*!< 0x00000800 */
+#define EXTI_EMR_MR11 EXTI_EMR_MR11_Msk /*!< Event Mask on line 11 */
+#define EXTI_EMR_MR12_Pos (12U)
+#define EXTI_EMR_MR12_Msk (0x1U << EXTI_EMR_MR12_Pos) /*!< 0x00001000 */
+#define EXTI_EMR_MR12 EXTI_EMR_MR12_Msk /*!< Event Mask on line 12 */
+#define EXTI_EMR_MR13_Pos (13U)
+#define EXTI_EMR_MR13_Msk (0x1U << EXTI_EMR_MR13_Pos) /*!< 0x00002000 */
+#define EXTI_EMR_MR13 EXTI_EMR_MR13_Msk /*!< Event Mask on line 13 */
+#define EXTI_EMR_MR14_Pos (14U)
+#define EXTI_EMR_MR14_Msk (0x1U << EXTI_EMR_MR14_Pos) /*!< 0x00004000 */
+#define EXTI_EMR_MR14 EXTI_EMR_MR14_Msk /*!< Event Mask on line 14 */
+#define EXTI_EMR_MR15_Pos (15U)
+#define EXTI_EMR_MR15_Msk (0x1U << EXTI_EMR_MR15_Pos) /*!< 0x00008000 */
+#define EXTI_EMR_MR15 EXTI_EMR_MR15_Msk /*!< Event Mask on line 15 */
+#define EXTI_EMR_MR16_Pos (16U)
+#define EXTI_EMR_MR16_Msk (0x1U << EXTI_EMR_MR16_Pos) /*!< 0x00010000 */
+#define EXTI_EMR_MR16 EXTI_EMR_MR16_Msk /*!< Event Mask on line 16 */
+#define EXTI_EMR_MR17_Pos (17U)
+#define EXTI_EMR_MR17_Msk (0x1U << EXTI_EMR_MR17_Pos) /*!< 0x00020000 */
+#define EXTI_EMR_MR17 EXTI_EMR_MR17_Msk /*!< Event Mask on line 17 */
+#define EXTI_EMR_MR18_Pos (18U)
+#define EXTI_EMR_MR18_Msk (0x1U << EXTI_EMR_MR18_Pos) /*!< 0x00040000 */
+#define EXTI_EMR_MR18 EXTI_EMR_MR18_Msk /*!< Event Mask on line 18 */
+#define EXTI_EMR_MR19_Pos (19U)
+#define EXTI_EMR_MR19_Msk (0x1U << EXTI_EMR_MR19_Pos) /*!< 0x00080000 */
+#define EXTI_EMR_MR19 EXTI_EMR_MR19_Msk /*!< Event Mask on line 19 */
+
+/* References Defines */
+#define EXTI_EMR_EM0 EXTI_EMR_MR0
+#define EXTI_EMR_EM1 EXTI_EMR_MR1
+#define EXTI_EMR_EM2 EXTI_EMR_MR2
+#define EXTI_EMR_EM3 EXTI_EMR_MR3
+#define EXTI_EMR_EM4 EXTI_EMR_MR4
+#define EXTI_EMR_EM5 EXTI_EMR_MR5
+#define EXTI_EMR_EM6 EXTI_EMR_MR6
+#define EXTI_EMR_EM7 EXTI_EMR_MR7
+#define EXTI_EMR_EM8 EXTI_EMR_MR8
+#define EXTI_EMR_EM9 EXTI_EMR_MR9
+#define EXTI_EMR_EM10 EXTI_EMR_MR10
+#define EXTI_EMR_EM11 EXTI_EMR_MR11
+#define EXTI_EMR_EM12 EXTI_EMR_MR12
+#define EXTI_EMR_EM13 EXTI_EMR_MR13
+#define EXTI_EMR_EM14 EXTI_EMR_MR14
+#define EXTI_EMR_EM15 EXTI_EMR_MR15
+#define EXTI_EMR_EM16 EXTI_EMR_MR16
+#define EXTI_EMR_EM17 EXTI_EMR_MR17
+#define EXTI_EMR_EM18 EXTI_EMR_MR18
+#define EXTI_EMR_EM19 EXTI_EMR_MR19
+
+/****************** Bit definition for EXTI_RTSR register *******************/
+#define EXTI_RTSR_TR0_Pos (0U)
+#define EXTI_RTSR_TR0_Msk (0x1U << EXTI_RTSR_TR0_Pos) /*!< 0x00000001 */
+#define EXTI_RTSR_TR0 EXTI_RTSR_TR0_Msk /*!< Rising trigger event configuration bit of line 0 */
+#define EXTI_RTSR_TR1_Pos (1U)
+#define EXTI_RTSR_TR1_Msk (0x1U << EXTI_RTSR_TR1_Pos) /*!< 0x00000002 */
+#define EXTI_RTSR_TR1 EXTI_RTSR_TR1_Msk /*!< Rising trigger event configuration bit of line 1 */
+#define EXTI_RTSR_TR2_Pos (2U)
+#define EXTI_RTSR_TR2_Msk (0x1U << EXTI_RTSR_TR2_Pos) /*!< 0x00000004 */
+#define EXTI_RTSR_TR2 EXTI_RTSR_TR2_Msk /*!< Rising trigger event configuration bit of line 2 */
+#define EXTI_RTSR_TR3_Pos (3U)
+#define EXTI_RTSR_TR3_Msk (0x1U << EXTI_RTSR_TR3_Pos) /*!< 0x00000008 */
+#define EXTI_RTSR_TR3 EXTI_RTSR_TR3_Msk /*!< Rising trigger event configuration bit of line 3 */
+#define EXTI_RTSR_TR4_Pos (4U)
+#define EXTI_RTSR_TR4_Msk (0x1U << EXTI_RTSR_TR4_Pos) /*!< 0x00000010 */
+#define EXTI_RTSR_TR4 EXTI_RTSR_TR4_Msk /*!< Rising trigger event configuration bit of line 4 */
+#define EXTI_RTSR_TR5_Pos (5U)
+#define EXTI_RTSR_TR5_Msk (0x1U << EXTI_RTSR_TR5_Pos) /*!< 0x00000020 */
+#define EXTI_RTSR_TR5 EXTI_RTSR_TR5_Msk /*!< Rising trigger event configuration bit of line 5 */
+#define EXTI_RTSR_TR6_Pos (6U)
+#define EXTI_RTSR_TR6_Msk (0x1U << EXTI_RTSR_TR6_Pos) /*!< 0x00000040 */
+#define EXTI_RTSR_TR6 EXTI_RTSR_TR6_Msk /*!< Rising trigger event configuration bit of line 6 */
+#define EXTI_RTSR_TR7_Pos (7U)
+#define EXTI_RTSR_TR7_Msk (0x1U << EXTI_RTSR_TR7_Pos) /*!< 0x00000080 */
+#define EXTI_RTSR_TR7 EXTI_RTSR_TR7_Msk /*!< Rising trigger event configuration bit of line 7 */
+#define EXTI_RTSR_TR8_Pos (8U)
+#define EXTI_RTSR_TR8_Msk (0x1U << EXTI_RTSR_TR8_Pos) /*!< 0x00000100 */
+#define EXTI_RTSR_TR8 EXTI_RTSR_TR8_Msk /*!< Rising trigger event configuration bit of line 8 */
+#define EXTI_RTSR_TR9_Pos (9U)
+#define EXTI_RTSR_TR9_Msk (0x1U << EXTI_RTSR_TR9_Pos) /*!< 0x00000200 */
+#define EXTI_RTSR_TR9 EXTI_RTSR_TR9_Msk /*!< Rising trigger event configuration bit of line 9 */
+#define EXTI_RTSR_TR10_Pos (10U)
+#define EXTI_RTSR_TR10_Msk (0x1U << EXTI_RTSR_TR10_Pos) /*!< 0x00000400 */
+#define EXTI_RTSR_TR10 EXTI_RTSR_TR10_Msk /*!< Rising trigger event configuration bit of line 10 */
+#define EXTI_RTSR_TR11_Pos (11U)
+#define EXTI_RTSR_TR11_Msk (0x1U << EXTI_RTSR_TR11_Pos) /*!< 0x00000800 */
+#define EXTI_RTSR_TR11 EXTI_RTSR_TR11_Msk /*!< Rising trigger event configuration bit of line 11 */
+#define EXTI_RTSR_TR12_Pos (12U)
+#define EXTI_RTSR_TR12_Msk (0x1U << EXTI_RTSR_TR12_Pos) /*!< 0x00001000 */
+#define EXTI_RTSR_TR12 EXTI_RTSR_TR12_Msk /*!< Rising trigger event configuration bit of line 12 */
+#define EXTI_RTSR_TR13_Pos (13U)
+#define EXTI_RTSR_TR13_Msk (0x1U << EXTI_RTSR_TR13_Pos) /*!< 0x00002000 */
+#define EXTI_RTSR_TR13 EXTI_RTSR_TR13_Msk /*!< Rising trigger event configuration bit of line 13 */
+#define EXTI_RTSR_TR14_Pos (14U)
+#define EXTI_RTSR_TR14_Msk (0x1U << EXTI_RTSR_TR14_Pos) /*!< 0x00004000 */
+#define EXTI_RTSR_TR14 EXTI_RTSR_TR14_Msk /*!< Rising trigger event configuration bit of line 14 */
+#define EXTI_RTSR_TR15_Pos (15U)
+#define EXTI_RTSR_TR15_Msk (0x1U << EXTI_RTSR_TR15_Pos) /*!< 0x00008000 */
+#define EXTI_RTSR_TR15 EXTI_RTSR_TR15_Msk /*!< Rising trigger event configuration bit of line 15 */
+#define EXTI_RTSR_TR16_Pos (16U)
+#define EXTI_RTSR_TR16_Msk (0x1U << EXTI_RTSR_TR16_Pos) /*!< 0x00010000 */
+#define EXTI_RTSR_TR16 EXTI_RTSR_TR16_Msk /*!< Rising trigger event configuration bit of line 16 */
+#define EXTI_RTSR_TR17_Pos (17U)
+#define EXTI_RTSR_TR17_Msk (0x1U << EXTI_RTSR_TR17_Pos) /*!< 0x00020000 */
+#define EXTI_RTSR_TR17 EXTI_RTSR_TR17_Msk /*!< Rising trigger event configuration bit of line 17 */
+#define EXTI_RTSR_TR18_Pos (18U)
+#define EXTI_RTSR_TR18_Msk (0x1U << EXTI_RTSR_TR18_Pos) /*!< 0x00040000 */
+#define EXTI_RTSR_TR18 EXTI_RTSR_TR18_Msk /*!< Rising trigger event configuration bit of line 18 */
+#define EXTI_RTSR_TR19_Pos (19U)
+#define EXTI_RTSR_TR19_Msk (0x1U << EXTI_RTSR_TR19_Pos) /*!< 0x00080000 */
+#define EXTI_RTSR_TR19 EXTI_RTSR_TR19_Msk /*!< Rising trigger event configuration bit of line 19 */
+
+/* References Defines */
+#define EXTI_RTSR_RT0 EXTI_RTSR_TR0
+#define EXTI_RTSR_RT1 EXTI_RTSR_TR1
+#define EXTI_RTSR_RT2 EXTI_RTSR_TR2
+#define EXTI_RTSR_RT3 EXTI_RTSR_TR3
+#define EXTI_RTSR_RT4 EXTI_RTSR_TR4
+#define EXTI_RTSR_RT5 EXTI_RTSR_TR5
+#define EXTI_RTSR_RT6 EXTI_RTSR_TR6
+#define EXTI_RTSR_RT7 EXTI_RTSR_TR7
+#define EXTI_RTSR_RT8 EXTI_RTSR_TR8
+#define EXTI_RTSR_RT9 EXTI_RTSR_TR9
+#define EXTI_RTSR_RT10 EXTI_RTSR_TR10
+#define EXTI_RTSR_RT11 EXTI_RTSR_TR11
+#define EXTI_RTSR_RT12 EXTI_RTSR_TR12
+#define EXTI_RTSR_RT13 EXTI_RTSR_TR13
+#define EXTI_RTSR_RT14 EXTI_RTSR_TR14
+#define EXTI_RTSR_RT15 EXTI_RTSR_TR15
+#define EXTI_RTSR_RT16 EXTI_RTSR_TR16
+#define EXTI_RTSR_RT17 EXTI_RTSR_TR17
+#define EXTI_RTSR_RT18 EXTI_RTSR_TR18
+#define EXTI_RTSR_RT19 EXTI_RTSR_TR19
+
+/****************** Bit definition for EXTI_FTSR register *******************/
+#define EXTI_FTSR_TR0_Pos (0U)
+#define EXTI_FTSR_TR0_Msk (0x1U << EXTI_FTSR_TR0_Pos) /*!< 0x00000001 */
+#define EXTI_FTSR_TR0 EXTI_FTSR_TR0_Msk /*!< Falling trigger event configuration bit of line 0 */
+#define EXTI_FTSR_TR1_Pos (1U)
+#define EXTI_FTSR_TR1_Msk (0x1U << EXTI_FTSR_TR1_Pos) /*!< 0x00000002 */
+#define EXTI_FTSR_TR1 EXTI_FTSR_TR1_Msk /*!< Falling trigger event configuration bit of line 1 */
+#define EXTI_FTSR_TR2_Pos (2U)
+#define EXTI_FTSR_TR2_Msk (0x1U << EXTI_FTSR_TR2_Pos) /*!< 0x00000004 */
+#define EXTI_FTSR_TR2 EXTI_FTSR_TR2_Msk /*!< Falling trigger event configuration bit of line 2 */
+#define EXTI_FTSR_TR3_Pos (3U)
+#define EXTI_FTSR_TR3_Msk (0x1U << EXTI_FTSR_TR3_Pos) /*!< 0x00000008 */
+#define EXTI_FTSR_TR3 EXTI_FTSR_TR3_Msk /*!< Falling trigger event configuration bit of line 3 */
+#define EXTI_FTSR_TR4_Pos (4U)
+#define EXTI_FTSR_TR4_Msk (0x1U << EXTI_FTSR_TR4_Pos) /*!< 0x00000010 */
+#define EXTI_FTSR_TR4 EXTI_FTSR_TR4_Msk /*!< Falling trigger event configuration bit of line 4 */
+#define EXTI_FTSR_TR5_Pos (5U)
+#define EXTI_FTSR_TR5_Msk (0x1U << EXTI_FTSR_TR5_Pos) /*!< 0x00000020 */
+#define EXTI_FTSR_TR5 EXTI_FTSR_TR5_Msk /*!< Falling trigger event configuration bit of line 5 */
+#define EXTI_FTSR_TR6_Pos (6U)
+#define EXTI_FTSR_TR6_Msk (0x1U << EXTI_FTSR_TR6_Pos) /*!< 0x00000040 */
+#define EXTI_FTSR_TR6 EXTI_FTSR_TR6_Msk /*!< Falling trigger event configuration bit of line 6 */
+#define EXTI_FTSR_TR7_Pos (7U)
+#define EXTI_FTSR_TR7_Msk (0x1U << EXTI_FTSR_TR7_Pos) /*!< 0x00000080 */
+#define EXTI_FTSR_TR7 EXTI_FTSR_TR7_Msk /*!< Falling trigger event configuration bit of line 7 */
+#define EXTI_FTSR_TR8_Pos (8U)
+#define EXTI_FTSR_TR8_Msk (0x1U << EXTI_FTSR_TR8_Pos) /*!< 0x00000100 */
+#define EXTI_FTSR_TR8 EXTI_FTSR_TR8_Msk /*!< Falling trigger event configuration bit of line 8 */
+#define EXTI_FTSR_TR9_Pos (9U)
+#define EXTI_FTSR_TR9_Msk (0x1U << EXTI_FTSR_TR9_Pos) /*!< 0x00000200 */
+#define EXTI_FTSR_TR9 EXTI_FTSR_TR9_Msk /*!< Falling trigger event configuration bit of line 9 */
+#define EXTI_FTSR_TR10_Pos (10U)
+#define EXTI_FTSR_TR10_Msk (0x1U << EXTI_FTSR_TR10_Pos) /*!< 0x00000400 */
+#define EXTI_FTSR_TR10 EXTI_FTSR_TR10_Msk /*!< Falling trigger event configuration bit of line 10 */
+#define EXTI_FTSR_TR11_Pos (11U)
+#define EXTI_FTSR_TR11_Msk (0x1U << EXTI_FTSR_TR11_Pos) /*!< 0x00000800 */
+#define EXTI_FTSR_TR11 EXTI_FTSR_TR11_Msk /*!< Falling trigger event configuration bit of line 11 */
+#define EXTI_FTSR_TR12_Pos (12U)
+#define EXTI_FTSR_TR12_Msk (0x1U << EXTI_FTSR_TR12_Pos) /*!< 0x00001000 */
+#define EXTI_FTSR_TR12 EXTI_FTSR_TR12_Msk /*!< Falling trigger event configuration bit of line 12 */
+#define EXTI_FTSR_TR13_Pos (13U)
+#define EXTI_FTSR_TR13_Msk (0x1U << EXTI_FTSR_TR13_Pos) /*!< 0x00002000 */
+#define EXTI_FTSR_TR13 EXTI_FTSR_TR13_Msk /*!< Falling trigger event configuration bit of line 13 */
+#define EXTI_FTSR_TR14_Pos (14U)
+#define EXTI_FTSR_TR14_Msk (0x1U << EXTI_FTSR_TR14_Pos) /*!< 0x00004000 */
+#define EXTI_FTSR_TR14 EXTI_FTSR_TR14_Msk /*!< Falling trigger event configuration bit of line 14 */
+#define EXTI_FTSR_TR15_Pos (15U)
+#define EXTI_FTSR_TR15_Msk (0x1U << EXTI_FTSR_TR15_Pos) /*!< 0x00008000 */
+#define EXTI_FTSR_TR15 EXTI_FTSR_TR15_Msk /*!< Falling trigger event configuration bit of line 15 */
+#define EXTI_FTSR_TR16_Pos (16U)
+#define EXTI_FTSR_TR16_Msk (0x1U << EXTI_FTSR_TR16_Pos) /*!< 0x00010000 */
+#define EXTI_FTSR_TR16 EXTI_FTSR_TR16_Msk /*!< Falling trigger event configuration bit of line 16 */
+#define EXTI_FTSR_TR17_Pos (17U)
+#define EXTI_FTSR_TR17_Msk (0x1U << EXTI_FTSR_TR17_Pos) /*!< 0x00020000 */
+#define EXTI_FTSR_TR17 EXTI_FTSR_TR17_Msk /*!< Falling trigger event configuration bit of line 17 */
+#define EXTI_FTSR_TR18_Pos (18U)
+#define EXTI_FTSR_TR18_Msk (0x1U << EXTI_FTSR_TR18_Pos) /*!< 0x00040000 */
+#define EXTI_FTSR_TR18 EXTI_FTSR_TR18_Msk /*!< Falling trigger event configuration bit of line 18 */
+#define EXTI_FTSR_TR19_Pos (19U)
+#define EXTI_FTSR_TR19_Msk (0x1U << EXTI_FTSR_TR19_Pos) /*!< 0x00080000 */
+#define EXTI_FTSR_TR19 EXTI_FTSR_TR19_Msk /*!< Falling trigger event configuration bit of line 19 */
+
+/* References Defines */
+#define EXTI_FTSR_FT0 EXTI_FTSR_TR0
+#define EXTI_FTSR_FT1 EXTI_FTSR_TR1
+#define EXTI_FTSR_FT2 EXTI_FTSR_TR2
+#define EXTI_FTSR_FT3 EXTI_FTSR_TR3
+#define EXTI_FTSR_FT4 EXTI_FTSR_TR4
+#define EXTI_FTSR_FT5 EXTI_FTSR_TR5
+#define EXTI_FTSR_FT6 EXTI_FTSR_TR6
+#define EXTI_FTSR_FT7 EXTI_FTSR_TR7
+#define EXTI_FTSR_FT8 EXTI_FTSR_TR8
+#define EXTI_FTSR_FT9 EXTI_FTSR_TR9
+#define EXTI_FTSR_FT10 EXTI_FTSR_TR10
+#define EXTI_FTSR_FT11 EXTI_FTSR_TR11
+#define EXTI_FTSR_FT12 EXTI_FTSR_TR12
+#define EXTI_FTSR_FT13 EXTI_FTSR_TR13
+#define EXTI_FTSR_FT14 EXTI_FTSR_TR14
+#define EXTI_FTSR_FT15 EXTI_FTSR_TR15
+#define EXTI_FTSR_FT16 EXTI_FTSR_TR16
+#define EXTI_FTSR_FT17 EXTI_FTSR_TR17
+#define EXTI_FTSR_FT18 EXTI_FTSR_TR18
+#define EXTI_FTSR_FT19 EXTI_FTSR_TR19
+
+/****************** Bit definition for EXTI_SWIER register ******************/
+#define EXTI_SWIER_SWIER0_Pos (0U)
+#define EXTI_SWIER_SWIER0_Msk (0x1U << EXTI_SWIER_SWIER0_Pos) /*!< 0x00000001 */
+#define EXTI_SWIER_SWIER0 EXTI_SWIER_SWIER0_Msk /*!< Software Interrupt on line 0 */
+#define EXTI_SWIER_SWIER1_Pos (1U)
+#define EXTI_SWIER_SWIER1_Msk (0x1U << EXTI_SWIER_SWIER1_Pos) /*!< 0x00000002 */
+#define EXTI_SWIER_SWIER1 EXTI_SWIER_SWIER1_Msk /*!< Software Interrupt on line 1 */
+#define EXTI_SWIER_SWIER2_Pos (2U)
+#define EXTI_SWIER_SWIER2_Msk (0x1U << EXTI_SWIER_SWIER2_Pos) /*!< 0x00000004 */
+#define EXTI_SWIER_SWIER2 EXTI_SWIER_SWIER2_Msk /*!< Software Interrupt on line 2 */
+#define EXTI_SWIER_SWIER3_Pos (3U)
+#define EXTI_SWIER_SWIER3_Msk (0x1U << EXTI_SWIER_SWIER3_Pos) /*!< 0x00000008 */
+#define EXTI_SWIER_SWIER3 EXTI_SWIER_SWIER3_Msk /*!< Software Interrupt on line 3 */
+#define EXTI_SWIER_SWIER4_Pos (4U)
+#define EXTI_SWIER_SWIER4_Msk (0x1U << EXTI_SWIER_SWIER4_Pos) /*!< 0x00000010 */
+#define EXTI_SWIER_SWIER4 EXTI_SWIER_SWIER4_Msk /*!< Software Interrupt on line 4 */
+#define EXTI_SWIER_SWIER5_Pos (5U)
+#define EXTI_SWIER_SWIER5_Msk (0x1U << EXTI_SWIER_SWIER5_Pos) /*!< 0x00000020 */
+#define EXTI_SWIER_SWIER5 EXTI_SWIER_SWIER5_Msk /*!< Software Interrupt on line 5 */
+#define EXTI_SWIER_SWIER6_Pos (6U)
+#define EXTI_SWIER_SWIER6_Msk (0x1U << EXTI_SWIER_SWIER6_Pos) /*!< 0x00000040 */
+#define EXTI_SWIER_SWIER6 EXTI_SWIER_SWIER6_Msk /*!< Software Interrupt on line 6 */
+#define EXTI_SWIER_SWIER7_Pos (7U)
+#define EXTI_SWIER_SWIER7_Msk (0x1U << EXTI_SWIER_SWIER7_Pos) /*!< 0x00000080 */
+#define EXTI_SWIER_SWIER7 EXTI_SWIER_SWIER7_Msk /*!< Software Interrupt on line 7 */
+#define EXTI_SWIER_SWIER8_Pos (8U)
+#define EXTI_SWIER_SWIER8_Msk (0x1U << EXTI_SWIER_SWIER8_Pos) /*!< 0x00000100 */
+#define EXTI_SWIER_SWIER8 EXTI_SWIER_SWIER8_Msk /*!< Software Interrupt on line 8 */
+#define EXTI_SWIER_SWIER9_Pos (9U)
+#define EXTI_SWIER_SWIER9_Msk (0x1U << EXTI_SWIER_SWIER9_Pos) /*!< 0x00000200 */
+#define EXTI_SWIER_SWIER9 EXTI_SWIER_SWIER9_Msk /*!< Software Interrupt on line 9 */
+#define EXTI_SWIER_SWIER10_Pos (10U)
+#define EXTI_SWIER_SWIER10_Msk (0x1U << EXTI_SWIER_SWIER10_Pos) /*!< 0x00000400 */
+#define EXTI_SWIER_SWIER10 EXTI_SWIER_SWIER10_Msk /*!< Software Interrupt on line 10 */
+#define EXTI_SWIER_SWIER11_Pos (11U)
+#define EXTI_SWIER_SWIER11_Msk (0x1U << EXTI_SWIER_SWIER11_Pos) /*!< 0x00000800 */
+#define EXTI_SWIER_SWIER11 EXTI_SWIER_SWIER11_Msk /*!< Software Interrupt on line 11 */
+#define EXTI_SWIER_SWIER12_Pos (12U)
+#define EXTI_SWIER_SWIER12_Msk (0x1U << EXTI_SWIER_SWIER12_Pos) /*!< 0x00001000 */
+#define EXTI_SWIER_SWIER12 EXTI_SWIER_SWIER12_Msk /*!< Software Interrupt on line 12 */
+#define EXTI_SWIER_SWIER13_Pos (13U)
+#define EXTI_SWIER_SWIER13_Msk (0x1U << EXTI_SWIER_SWIER13_Pos) /*!< 0x00002000 */
+#define EXTI_SWIER_SWIER13 EXTI_SWIER_SWIER13_Msk /*!< Software Interrupt on line 13 */
+#define EXTI_SWIER_SWIER14_Pos (14U)
+#define EXTI_SWIER_SWIER14_Msk (0x1U << EXTI_SWIER_SWIER14_Pos) /*!< 0x00004000 */
+#define EXTI_SWIER_SWIER14 EXTI_SWIER_SWIER14_Msk /*!< Software Interrupt on line 14 */
+#define EXTI_SWIER_SWIER15_Pos (15U)
+#define EXTI_SWIER_SWIER15_Msk (0x1U << EXTI_SWIER_SWIER15_Pos) /*!< 0x00008000 */
+#define EXTI_SWIER_SWIER15 EXTI_SWIER_SWIER15_Msk /*!< Software Interrupt on line 15 */
+#define EXTI_SWIER_SWIER16_Pos (16U)
+#define EXTI_SWIER_SWIER16_Msk (0x1U << EXTI_SWIER_SWIER16_Pos) /*!< 0x00010000 */
+#define EXTI_SWIER_SWIER16 EXTI_SWIER_SWIER16_Msk /*!< Software Interrupt on line 16 */
+#define EXTI_SWIER_SWIER17_Pos (17U)
+#define EXTI_SWIER_SWIER17_Msk (0x1U << EXTI_SWIER_SWIER17_Pos) /*!< 0x00020000 */
+#define EXTI_SWIER_SWIER17 EXTI_SWIER_SWIER17_Msk /*!< Software Interrupt on line 17 */
+#define EXTI_SWIER_SWIER18_Pos (18U)
+#define EXTI_SWIER_SWIER18_Msk (0x1U << EXTI_SWIER_SWIER18_Pos) /*!< 0x00040000 */
+#define EXTI_SWIER_SWIER18 EXTI_SWIER_SWIER18_Msk /*!< Software Interrupt on line 18 */
+#define EXTI_SWIER_SWIER19_Pos (19U)
+#define EXTI_SWIER_SWIER19_Msk (0x1U << EXTI_SWIER_SWIER19_Pos) /*!< 0x00080000 */
+#define EXTI_SWIER_SWIER19 EXTI_SWIER_SWIER19_Msk /*!< Software Interrupt on line 19 */
+
+/* References Defines */
+#define EXTI_SWIER_SWI0 EXTI_SWIER_SWIER0
+#define EXTI_SWIER_SWI1 EXTI_SWIER_SWIER1
+#define EXTI_SWIER_SWI2 EXTI_SWIER_SWIER2
+#define EXTI_SWIER_SWI3 EXTI_SWIER_SWIER3
+#define EXTI_SWIER_SWI4 EXTI_SWIER_SWIER4
+#define EXTI_SWIER_SWI5 EXTI_SWIER_SWIER5
+#define EXTI_SWIER_SWI6 EXTI_SWIER_SWIER6
+#define EXTI_SWIER_SWI7 EXTI_SWIER_SWIER7
+#define EXTI_SWIER_SWI8 EXTI_SWIER_SWIER8
+#define EXTI_SWIER_SWI9 EXTI_SWIER_SWIER9
+#define EXTI_SWIER_SWI10 EXTI_SWIER_SWIER10
+#define EXTI_SWIER_SWI11 EXTI_SWIER_SWIER11
+#define EXTI_SWIER_SWI12 EXTI_SWIER_SWIER12
+#define EXTI_SWIER_SWI13 EXTI_SWIER_SWIER13
+#define EXTI_SWIER_SWI14 EXTI_SWIER_SWIER14
+#define EXTI_SWIER_SWI15 EXTI_SWIER_SWIER15
+#define EXTI_SWIER_SWI16 EXTI_SWIER_SWIER16
+#define EXTI_SWIER_SWI17 EXTI_SWIER_SWIER17
+#define EXTI_SWIER_SWI18 EXTI_SWIER_SWIER18
+#define EXTI_SWIER_SWI19 EXTI_SWIER_SWIER19
+
+/******************* Bit definition for EXTI_PR register ********************/
+#define EXTI_PR_PR0_Pos (0U)
+#define EXTI_PR_PR0_Msk (0x1U << EXTI_PR_PR0_Pos) /*!< 0x00000001 */
+#define EXTI_PR_PR0 EXTI_PR_PR0_Msk /*!< Pending bit for line 0 */
+#define EXTI_PR_PR1_Pos (1U)
+#define EXTI_PR_PR1_Msk (0x1U << EXTI_PR_PR1_Pos) /*!< 0x00000002 */
+#define EXTI_PR_PR1 EXTI_PR_PR1_Msk /*!< Pending bit for line 1 */
+#define EXTI_PR_PR2_Pos (2U)
+#define EXTI_PR_PR2_Msk (0x1U << EXTI_PR_PR2_Pos) /*!< 0x00000004 */
+#define EXTI_PR_PR2 EXTI_PR_PR2_Msk /*!< Pending bit for line 2 */
+#define EXTI_PR_PR3_Pos (3U)
+#define EXTI_PR_PR3_Msk (0x1U << EXTI_PR_PR3_Pos) /*!< 0x00000008 */
+#define EXTI_PR_PR3 EXTI_PR_PR3_Msk /*!< Pending bit for line 3 */
+#define EXTI_PR_PR4_Pos (4U)
+#define EXTI_PR_PR4_Msk (0x1U << EXTI_PR_PR4_Pos) /*!< 0x00000010 */
+#define EXTI_PR_PR4 EXTI_PR_PR4_Msk /*!< Pending bit for line 4 */
+#define EXTI_PR_PR5_Pos (5U)
+#define EXTI_PR_PR5_Msk (0x1U << EXTI_PR_PR5_Pos) /*!< 0x00000020 */
+#define EXTI_PR_PR5 EXTI_PR_PR5_Msk /*!< Pending bit for line 5 */
+#define EXTI_PR_PR6_Pos (6U)
+#define EXTI_PR_PR6_Msk (0x1U << EXTI_PR_PR6_Pos) /*!< 0x00000040 */
+#define EXTI_PR_PR6 EXTI_PR_PR6_Msk /*!< Pending bit for line 6 */
+#define EXTI_PR_PR7_Pos (7U)
+#define EXTI_PR_PR7_Msk (0x1U << EXTI_PR_PR7_Pos) /*!< 0x00000080 */
+#define EXTI_PR_PR7 EXTI_PR_PR7_Msk /*!< Pending bit for line 7 */
+#define EXTI_PR_PR8_Pos (8U)
+#define EXTI_PR_PR8_Msk (0x1U << EXTI_PR_PR8_Pos) /*!< 0x00000100 */
+#define EXTI_PR_PR8 EXTI_PR_PR8_Msk /*!< Pending bit for line 8 */
+#define EXTI_PR_PR9_Pos (9U)
+#define EXTI_PR_PR9_Msk (0x1U << EXTI_PR_PR9_Pos) /*!< 0x00000200 */
+#define EXTI_PR_PR9 EXTI_PR_PR9_Msk /*!< Pending bit for line 9 */
+#define EXTI_PR_PR10_Pos (10U)
+#define EXTI_PR_PR10_Msk (0x1U << EXTI_PR_PR10_Pos) /*!< 0x00000400 */
+#define EXTI_PR_PR10 EXTI_PR_PR10_Msk /*!< Pending bit for line 10 */
+#define EXTI_PR_PR11_Pos (11U)
+#define EXTI_PR_PR11_Msk (0x1U << EXTI_PR_PR11_Pos) /*!< 0x00000800 */
+#define EXTI_PR_PR11 EXTI_PR_PR11_Msk /*!< Pending bit for line 11 */
+#define EXTI_PR_PR12_Pos (12U)
+#define EXTI_PR_PR12_Msk (0x1U << EXTI_PR_PR12_Pos) /*!< 0x00001000 */
+#define EXTI_PR_PR12 EXTI_PR_PR12_Msk /*!< Pending bit for line 12 */
+#define EXTI_PR_PR13_Pos (13U)
+#define EXTI_PR_PR13_Msk (0x1U << EXTI_PR_PR13_Pos) /*!< 0x00002000 */
+#define EXTI_PR_PR13 EXTI_PR_PR13_Msk /*!< Pending bit for line 13 */
+#define EXTI_PR_PR14_Pos (14U)
+#define EXTI_PR_PR14_Msk (0x1U << EXTI_PR_PR14_Pos) /*!< 0x00004000 */
+#define EXTI_PR_PR14 EXTI_PR_PR14_Msk /*!< Pending bit for line 14 */
+#define EXTI_PR_PR15_Pos (15U)
+#define EXTI_PR_PR15_Msk (0x1U << EXTI_PR_PR15_Pos) /*!< 0x00008000 */
+#define EXTI_PR_PR15 EXTI_PR_PR15_Msk /*!< Pending bit for line 15 */
+#define EXTI_PR_PR16_Pos (16U)
+#define EXTI_PR_PR16_Msk (0x1U << EXTI_PR_PR16_Pos) /*!< 0x00010000 */
+#define EXTI_PR_PR16 EXTI_PR_PR16_Msk /*!< Pending bit for line 16 */
+#define EXTI_PR_PR17_Pos (17U)
+#define EXTI_PR_PR17_Msk (0x1U << EXTI_PR_PR17_Pos) /*!< 0x00020000 */
+#define EXTI_PR_PR17 EXTI_PR_PR17_Msk /*!< Pending bit for line 17 */
+#define EXTI_PR_PR18_Pos (18U)
+#define EXTI_PR_PR18_Msk (0x1U << EXTI_PR_PR18_Pos) /*!< 0x00040000 */
+#define EXTI_PR_PR18 EXTI_PR_PR18_Msk /*!< Pending bit for line 18 */
+#define EXTI_PR_PR19_Pos (19U)
+#define EXTI_PR_PR19_Msk (0x1U << EXTI_PR_PR19_Pos) /*!< 0x00080000 */
+#define EXTI_PR_PR19 EXTI_PR_PR19_Msk /*!< Pending bit for line 19 */
+
+/* References Defines */
+#define EXTI_PR_PIF0 EXTI_PR_PR0
+#define EXTI_PR_PIF1 EXTI_PR_PR1
+#define EXTI_PR_PIF2 EXTI_PR_PR2
+#define EXTI_PR_PIF3 EXTI_PR_PR3
+#define EXTI_PR_PIF4 EXTI_PR_PR4
+#define EXTI_PR_PIF5 EXTI_PR_PR5
+#define EXTI_PR_PIF6 EXTI_PR_PR6
+#define EXTI_PR_PIF7 EXTI_PR_PR7
+#define EXTI_PR_PIF8 EXTI_PR_PR8
+#define EXTI_PR_PIF9 EXTI_PR_PR9
+#define EXTI_PR_PIF10 EXTI_PR_PR10
+#define EXTI_PR_PIF11 EXTI_PR_PR11
+#define EXTI_PR_PIF12 EXTI_PR_PR12
+#define EXTI_PR_PIF13 EXTI_PR_PR13
+#define EXTI_PR_PIF14 EXTI_PR_PR14
+#define EXTI_PR_PIF15 EXTI_PR_PR15
+#define EXTI_PR_PIF16 EXTI_PR_PR16
+#define EXTI_PR_PIF17 EXTI_PR_PR17
+#define EXTI_PR_PIF18 EXTI_PR_PR18
+#define EXTI_PR_PIF19 EXTI_PR_PR19
+
+/******************************************************************************/
+/* */
+/* DMA Controller */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for DMA_ISR register ********************/
+#define DMA_ISR_GIF1_Pos (0U)
+#define DMA_ISR_GIF1_Msk (0x1U << DMA_ISR_GIF1_Pos) /*!< 0x00000001 */
+#define DMA_ISR_GIF1 DMA_ISR_GIF1_Msk /*!< Channel 1 Global interrupt flag */
+#define DMA_ISR_TCIF1_Pos (1U)
+#define DMA_ISR_TCIF1_Msk (0x1U << DMA_ISR_TCIF1_Pos) /*!< 0x00000002 */
+#define DMA_ISR_TCIF1 DMA_ISR_TCIF1_Msk /*!< Channel 1 Transfer Complete flag */
+#define DMA_ISR_HTIF1_Pos (2U)
+#define DMA_ISR_HTIF1_Msk (0x1U << DMA_ISR_HTIF1_Pos) /*!< 0x00000004 */
+#define DMA_ISR_HTIF1 DMA_ISR_HTIF1_Msk /*!< Channel 1 Half Transfer flag */
+#define DMA_ISR_TEIF1_Pos (3U)
+#define DMA_ISR_TEIF1_Msk (0x1U << DMA_ISR_TEIF1_Pos) /*!< 0x00000008 */
+#define DMA_ISR_TEIF1 DMA_ISR_TEIF1_Msk /*!< Channel 1 Transfer Error flag */
+#define DMA_ISR_GIF2_Pos (4U)
+#define DMA_ISR_GIF2_Msk (0x1U << DMA_ISR_GIF2_Pos) /*!< 0x00000010 */
+#define DMA_ISR_GIF2 DMA_ISR_GIF2_Msk /*!< Channel 2 Global interrupt flag */
+#define DMA_ISR_TCIF2_Pos (5U)
+#define DMA_ISR_TCIF2_Msk (0x1U << DMA_ISR_TCIF2_Pos) /*!< 0x00000020 */
+#define DMA_ISR_TCIF2 DMA_ISR_TCIF2_Msk /*!< Channel 2 Transfer Complete flag */
+#define DMA_ISR_HTIF2_Pos (6U)
+#define DMA_ISR_HTIF2_Msk (0x1U << DMA_ISR_HTIF2_Pos) /*!< 0x00000040 */
+#define DMA_ISR_HTIF2 DMA_ISR_HTIF2_Msk /*!< Channel 2 Half Transfer flag */
+#define DMA_ISR_TEIF2_Pos (7U)
+#define DMA_ISR_TEIF2_Msk (0x1U << DMA_ISR_TEIF2_Pos) /*!< 0x00000080 */
+#define DMA_ISR_TEIF2 DMA_ISR_TEIF2_Msk /*!< Channel 2 Transfer Error flag */
+#define DMA_ISR_GIF3_Pos (8U)
+#define DMA_ISR_GIF3_Msk (0x1U << DMA_ISR_GIF3_Pos) /*!< 0x00000100 */
+#define DMA_ISR_GIF3 DMA_ISR_GIF3_Msk /*!< Channel 3 Global interrupt flag */
+#define DMA_ISR_TCIF3_Pos (9U)
+#define DMA_ISR_TCIF3_Msk (0x1U << DMA_ISR_TCIF3_Pos) /*!< 0x00000200 */
+#define DMA_ISR_TCIF3 DMA_ISR_TCIF3_Msk /*!< Channel 3 Transfer Complete flag */
+#define DMA_ISR_HTIF3_Pos (10U)
+#define DMA_ISR_HTIF3_Msk (0x1U << DMA_ISR_HTIF3_Pos) /*!< 0x00000400 */
+#define DMA_ISR_HTIF3 DMA_ISR_HTIF3_Msk /*!< Channel 3 Half Transfer flag */
+#define DMA_ISR_TEIF3_Pos (11U)
+#define DMA_ISR_TEIF3_Msk (0x1U << DMA_ISR_TEIF3_Pos) /*!< 0x00000800 */
+#define DMA_ISR_TEIF3 DMA_ISR_TEIF3_Msk /*!< Channel 3 Transfer Error flag */
+#define DMA_ISR_GIF4_Pos (12U)
+#define DMA_ISR_GIF4_Msk (0x1U << DMA_ISR_GIF4_Pos) /*!< 0x00001000 */
+#define DMA_ISR_GIF4 DMA_ISR_GIF4_Msk /*!< Channel 4 Global interrupt flag */
+#define DMA_ISR_TCIF4_Pos (13U)
+#define DMA_ISR_TCIF4_Msk (0x1U << DMA_ISR_TCIF4_Pos) /*!< 0x00002000 */
+#define DMA_ISR_TCIF4 DMA_ISR_TCIF4_Msk /*!< Channel 4 Transfer Complete flag */
+#define DMA_ISR_HTIF4_Pos (14U)
+#define DMA_ISR_HTIF4_Msk (0x1U << DMA_ISR_HTIF4_Pos) /*!< 0x00004000 */
+#define DMA_ISR_HTIF4 DMA_ISR_HTIF4_Msk /*!< Channel 4 Half Transfer flag */
+#define DMA_ISR_TEIF4_Pos (15U)
+#define DMA_ISR_TEIF4_Msk (0x1U << DMA_ISR_TEIF4_Pos) /*!< 0x00008000 */
+#define DMA_ISR_TEIF4 DMA_ISR_TEIF4_Msk /*!< Channel 4 Transfer Error flag */
+#define DMA_ISR_GIF5_Pos (16U)
+#define DMA_ISR_GIF5_Msk (0x1U << DMA_ISR_GIF5_Pos) /*!< 0x00010000 */
+#define DMA_ISR_GIF5 DMA_ISR_GIF5_Msk /*!< Channel 5 Global interrupt flag */
+#define DMA_ISR_TCIF5_Pos (17U)
+#define DMA_ISR_TCIF5_Msk (0x1U << DMA_ISR_TCIF5_Pos) /*!< 0x00020000 */
+#define DMA_ISR_TCIF5 DMA_ISR_TCIF5_Msk /*!< Channel 5 Transfer Complete flag */
+#define DMA_ISR_HTIF5_Pos (18U)
+#define DMA_ISR_HTIF5_Msk (0x1U << DMA_ISR_HTIF5_Pos) /*!< 0x00040000 */
+#define DMA_ISR_HTIF5 DMA_ISR_HTIF5_Msk /*!< Channel 5 Half Transfer flag */
+#define DMA_ISR_TEIF5_Pos (19U)
+#define DMA_ISR_TEIF5_Msk (0x1U << DMA_ISR_TEIF5_Pos) /*!< 0x00080000 */
+#define DMA_ISR_TEIF5 DMA_ISR_TEIF5_Msk /*!< Channel 5 Transfer Error flag */
+#define DMA_ISR_GIF6_Pos (20U)
+#define DMA_ISR_GIF6_Msk (0x1U << DMA_ISR_GIF6_Pos) /*!< 0x00100000 */
+#define DMA_ISR_GIF6 DMA_ISR_GIF6_Msk /*!< Channel 6 Global interrupt flag */
+#define DMA_ISR_TCIF6_Pos (21U)
+#define DMA_ISR_TCIF6_Msk (0x1U << DMA_ISR_TCIF6_Pos) /*!< 0x00200000 */
+#define DMA_ISR_TCIF6 DMA_ISR_TCIF6_Msk /*!< Channel 6 Transfer Complete flag */
+#define DMA_ISR_HTIF6_Pos (22U)
+#define DMA_ISR_HTIF6_Msk (0x1U << DMA_ISR_HTIF6_Pos) /*!< 0x00400000 */
+#define DMA_ISR_HTIF6 DMA_ISR_HTIF6_Msk /*!< Channel 6 Half Transfer flag */
+#define DMA_ISR_TEIF6_Pos (23U)
+#define DMA_ISR_TEIF6_Msk (0x1U << DMA_ISR_TEIF6_Pos) /*!< 0x00800000 */
+#define DMA_ISR_TEIF6 DMA_ISR_TEIF6_Msk /*!< Channel 6 Transfer Error flag */
+#define DMA_ISR_GIF7_Pos (24U)
+#define DMA_ISR_GIF7_Msk (0x1U << DMA_ISR_GIF7_Pos) /*!< 0x01000000 */
+#define DMA_ISR_GIF7 DMA_ISR_GIF7_Msk /*!< Channel 7 Global interrupt flag */
+#define DMA_ISR_TCIF7_Pos (25U)
+#define DMA_ISR_TCIF7_Msk (0x1U << DMA_ISR_TCIF7_Pos) /*!< 0x02000000 */
+#define DMA_ISR_TCIF7 DMA_ISR_TCIF7_Msk /*!< Channel 7 Transfer Complete flag */
+#define DMA_ISR_HTIF7_Pos (26U)
+#define DMA_ISR_HTIF7_Msk (0x1U << DMA_ISR_HTIF7_Pos) /*!< 0x04000000 */
+#define DMA_ISR_HTIF7 DMA_ISR_HTIF7_Msk /*!< Channel 7 Half Transfer flag */
+#define DMA_ISR_TEIF7_Pos (27U)
+#define DMA_ISR_TEIF7_Msk (0x1U << DMA_ISR_TEIF7_Pos) /*!< 0x08000000 */
+#define DMA_ISR_TEIF7 DMA_ISR_TEIF7_Msk /*!< Channel 7 Transfer Error flag */
+
+/******************* Bit definition for DMA_IFCR register *******************/
+#define DMA_IFCR_CGIF1_Pos (0U)
+#define DMA_IFCR_CGIF1_Msk (0x1U << DMA_IFCR_CGIF1_Pos) /*!< 0x00000001 */
+#define DMA_IFCR_CGIF1 DMA_IFCR_CGIF1_Msk /*!< Channel 1 Global interrupt clear */
+#define DMA_IFCR_CTCIF1_Pos (1U)
+#define DMA_IFCR_CTCIF1_Msk (0x1U << DMA_IFCR_CTCIF1_Pos) /*!< 0x00000002 */
+#define DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF1_Msk /*!< Channel 1 Transfer Complete clear */
+#define DMA_IFCR_CHTIF1_Pos (2U)
+#define DMA_IFCR_CHTIF1_Msk (0x1U << DMA_IFCR_CHTIF1_Pos) /*!< 0x00000004 */
+#define DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF1_Msk /*!< Channel 1 Half Transfer clear */
+#define DMA_IFCR_CTEIF1_Pos (3U)
+#define DMA_IFCR_CTEIF1_Msk (0x1U << DMA_IFCR_CTEIF1_Pos) /*!< 0x00000008 */
+#define DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF1_Msk /*!< Channel 1 Transfer Error clear */
+#define DMA_IFCR_CGIF2_Pos (4U)
+#define DMA_IFCR_CGIF2_Msk (0x1U << DMA_IFCR_CGIF2_Pos) /*!< 0x00000010 */
+#define DMA_IFCR_CGIF2 DMA_IFCR_CGIF2_Msk /*!< Channel 2 Global interrupt clear */
+#define DMA_IFCR_CTCIF2_Pos (5U)
+#define DMA_IFCR_CTCIF2_Msk (0x1U << DMA_IFCR_CTCIF2_Pos) /*!< 0x00000020 */
+#define DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF2_Msk /*!< Channel 2 Transfer Complete clear */
+#define DMA_IFCR_CHTIF2_Pos (6U)
+#define DMA_IFCR_CHTIF2_Msk (0x1U << DMA_IFCR_CHTIF2_Pos) /*!< 0x00000040 */
+#define DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF2_Msk /*!< Channel 2 Half Transfer clear */
+#define DMA_IFCR_CTEIF2_Pos (7U)
+#define DMA_IFCR_CTEIF2_Msk (0x1U << DMA_IFCR_CTEIF2_Pos) /*!< 0x00000080 */
+#define DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF2_Msk /*!< Channel 2 Transfer Error clear */
+#define DMA_IFCR_CGIF3_Pos (8U)
+#define DMA_IFCR_CGIF3_Msk (0x1U << DMA_IFCR_CGIF3_Pos) /*!< 0x00000100 */
+#define DMA_IFCR_CGIF3 DMA_IFCR_CGIF3_Msk /*!< Channel 3 Global interrupt clear */
+#define DMA_IFCR_CTCIF3_Pos (9U)
+#define DMA_IFCR_CTCIF3_Msk (0x1U << DMA_IFCR_CTCIF3_Pos) /*!< 0x00000200 */
+#define DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF3_Msk /*!< Channel 3 Transfer Complete clear */
+#define DMA_IFCR_CHTIF3_Pos (10U)
+#define DMA_IFCR_CHTIF3_Msk (0x1U << DMA_IFCR_CHTIF3_Pos) /*!< 0x00000400 */
+#define DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF3_Msk /*!< Channel 3 Half Transfer clear */
+#define DMA_IFCR_CTEIF3_Pos (11U)
+#define DMA_IFCR_CTEIF3_Msk (0x1U << DMA_IFCR_CTEIF3_Pos) /*!< 0x00000800 */
+#define DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF3_Msk /*!< Channel 3 Transfer Error clear */
+#define DMA_IFCR_CGIF4_Pos (12U)
+#define DMA_IFCR_CGIF4_Msk (0x1U << DMA_IFCR_CGIF4_Pos) /*!< 0x00001000 */
+#define DMA_IFCR_CGIF4 DMA_IFCR_CGIF4_Msk /*!< Channel 4 Global interrupt clear */
+#define DMA_IFCR_CTCIF4_Pos (13U)
+#define DMA_IFCR_CTCIF4_Msk (0x1U << DMA_IFCR_CTCIF4_Pos) /*!< 0x00002000 */
+#define DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF4_Msk /*!< Channel 4 Transfer Complete clear */
+#define DMA_IFCR_CHTIF4_Pos (14U)
+#define DMA_IFCR_CHTIF4_Msk (0x1U << DMA_IFCR_CHTIF4_Pos) /*!< 0x00004000 */
+#define DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF4_Msk /*!< Channel 4 Half Transfer clear */
+#define DMA_IFCR_CTEIF4_Pos (15U)
+#define DMA_IFCR_CTEIF4_Msk (0x1U << DMA_IFCR_CTEIF4_Pos) /*!< 0x00008000 */
+#define DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF4_Msk /*!< Channel 4 Transfer Error clear */
+#define DMA_IFCR_CGIF5_Pos (16U)
+#define DMA_IFCR_CGIF5_Msk (0x1U << DMA_IFCR_CGIF5_Pos) /*!< 0x00010000 */
+#define DMA_IFCR_CGIF5 DMA_IFCR_CGIF5_Msk /*!< Channel 5 Global interrupt clear */
+#define DMA_IFCR_CTCIF5_Pos (17U)
+#define DMA_IFCR_CTCIF5_Msk (0x1U << DMA_IFCR_CTCIF5_Pos) /*!< 0x00020000 */
+#define DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF5_Msk /*!< Channel 5 Transfer Complete clear */
+#define DMA_IFCR_CHTIF5_Pos (18U)
+#define DMA_IFCR_CHTIF5_Msk (0x1U << DMA_IFCR_CHTIF5_Pos) /*!< 0x00040000 */
+#define DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5_Msk /*!< Channel 5 Half Transfer clear */
+#define DMA_IFCR_CTEIF5_Pos (19U)
+#define DMA_IFCR_CTEIF5_Msk (0x1U << DMA_IFCR_CTEIF5_Pos) /*!< 0x00080000 */
+#define DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF5_Msk /*!< Channel 5 Transfer Error clear */
+#define DMA_IFCR_CGIF6_Pos (20U)
+#define DMA_IFCR_CGIF6_Msk (0x1U << DMA_IFCR_CGIF6_Pos) /*!< 0x00100000 */
+#define DMA_IFCR_CGIF6 DMA_IFCR_CGIF6_Msk /*!< Channel 6 Global interrupt clear */
+#define DMA_IFCR_CTCIF6_Pos (21U)
+#define DMA_IFCR_CTCIF6_Msk (0x1U << DMA_IFCR_CTCIF6_Pos) /*!< 0x00200000 */
+#define DMA_IFCR_CTCIF6 DMA_IFCR_CTCIF6_Msk /*!< Channel 6 Transfer Complete clear */
+#define DMA_IFCR_CHTIF6_Pos (22U)
+#define DMA_IFCR_CHTIF6_Msk (0x1U << DMA_IFCR_CHTIF6_Pos) /*!< 0x00400000 */
+#define DMA_IFCR_CHTIF6 DMA_IFCR_CHTIF6_Msk /*!< Channel 6 Half Transfer clear */
+#define DMA_IFCR_CTEIF6_Pos (23U)
+#define DMA_IFCR_CTEIF6_Msk (0x1U << DMA_IFCR_CTEIF6_Pos) /*!< 0x00800000 */
+#define DMA_IFCR_CTEIF6 DMA_IFCR_CTEIF6_Msk /*!< Channel 6 Transfer Error clear */
+#define DMA_IFCR_CGIF7_Pos (24U)
+#define DMA_IFCR_CGIF7_Msk (0x1U << DMA_IFCR_CGIF7_Pos) /*!< 0x01000000 */
+#define DMA_IFCR_CGIF7 DMA_IFCR_CGIF7_Msk /*!< Channel 7 Global interrupt clear */
+#define DMA_IFCR_CTCIF7_Pos (25U)
+#define DMA_IFCR_CTCIF7_Msk (0x1U << DMA_IFCR_CTCIF7_Pos) /*!< 0x02000000 */
+#define DMA_IFCR_CTCIF7 DMA_IFCR_CTCIF7_Msk /*!< Channel 7 Transfer Complete clear */
+#define DMA_IFCR_CHTIF7_Pos (26U)
+#define DMA_IFCR_CHTIF7_Msk (0x1U << DMA_IFCR_CHTIF7_Pos) /*!< 0x04000000 */
+#define DMA_IFCR_CHTIF7 DMA_IFCR_CHTIF7_Msk /*!< Channel 7 Half Transfer clear */
+#define DMA_IFCR_CTEIF7_Pos (27U)
+#define DMA_IFCR_CTEIF7_Msk (0x1U << DMA_IFCR_CTEIF7_Pos) /*!< 0x08000000 */
+#define DMA_IFCR_CTEIF7 DMA_IFCR_CTEIF7_Msk /*!< Channel 7 Transfer Error clear */
+
+/******************* Bit definition for DMA_CCR register *******************/
+#define DMA_CCR_EN_Pos (0U)
+#define DMA_CCR_EN_Msk (0x1U << DMA_CCR_EN_Pos) /*!< 0x00000001 */
+#define DMA_CCR_EN DMA_CCR_EN_Msk /*!< Channel enable */
+#define DMA_CCR_TCIE_Pos (1U)
+#define DMA_CCR_TCIE_Msk (0x1U << DMA_CCR_TCIE_Pos) /*!< 0x00000002 */
+#define DMA_CCR_TCIE DMA_CCR_TCIE_Msk /*!< Transfer complete interrupt enable */
+#define DMA_CCR_HTIE_Pos (2U)
+#define DMA_CCR_HTIE_Msk (0x1U << DMA_CCR_HTIE_Pos) /*!< 0x00000004 */
+#define DMA_CCR_HTIE DMA_CCR_HTIE_Msk /*!< Half Transfer interrupt enable */
+#define DMA_CCR_TEIE_Pos (3U)
+#define DMA_CCR_TEIE_Msk (0x1U << DMA_CCR_TEIE_Pos) /*!< 0x00000008 */
+#define DMA_CCR_TEIE DMA_CCR_TEIE_Msk /*!< Transfer error interrupt enable */
+#define DMA_CCR_DIR_Pos (4U)
+#define DMA_CCR_DIR_Msk (0x1U << DMA_CCR_DIR_Pos) /*!< 0x00000010 */
+#define DMA_CCR_DIR DMA_CCR_DIR_Msk /*!< Data transfer direction */
+#define DMA_CCR_CIRC_Pos (5U)
+#define DMA_CCR_CIRC_Msk (0x1U << DMA_CCR_CIRC_Pos) /*!< 0x00000020 */
+#define DMA_CCR_CIRC DMA_CCR_CIRC_Msk /*!< Circular mode */
+#define DMA_CCR_PINC_Pos (6U)
+#define DMA_CCR_PINC_Msk (0x1U << DMA_CCR_PINC_Pos) /*!< 0x00000040 */
+#define DMA_CCR_PINC DMA_CCR_PINC_Msk /*!< Peripheral increment mode */
+#define DMA_CCR_MINC_Pos (7U)
+#define DMA_CCR_MINC_Msk (0x1U << DMA_CCR_MINC_Pos) /*!< 0x00000080 */
+#define DMA_CCR_MINC DMA_CCR_MINC_Msk /*!< Memory increment mode */
+
+#define DMA_CCR_PSIZE_Pos (8U)
+#define DMA_CCR_PSIZE_Msk (0x3U << DMA_CCR_PSIZE_Pos) /*!< 0x00000300 */
+#define DMA_CCR_PSIZE DMA_CCR_PSIZE_Msk /*!< PSIZE[1:0] bits (Peripheral size) */
+#define DMA_CCR_PSIZE_0 (0x1U << DMA_CCR_PSIZE_Pos) /*!< 0x00000100 */
+#define DMA_CCR_PSIZE_1 (0x2U << DMA_CCR_PSIZE_Pos) /*!< 0x00000200 */
+
+#define DMA_CCR_MSIZE_Pos (10U)
+#define DMA_CCR_MSIZE_Msk (0x3U << DMA_CCR_MSIZE_Pos) /*!< 0x00000C00 */
+#define DMA_CCR_MSIZE DMA_CCR_MSIZE_Msk /*!< MSIZE[1:0] bits (Memory size) */
+#define DMA_CCR_MSIZE_0 (0x1U << DMA_CCR_MSIZE_Pos) /*!< 0x00000400 */
+#define DMA_CCR_MSIZE_1 (0x2U << DMA_CCR_MSIZE_Pos) /*!< 0x00000800 */
+
+#define DMA_CCR_PL_Pos (12U)
+#define DMA_CCR_PL_Msk (0x3U << DMA_CCR_PL_Pos) /*!< 0x00003000 */
+#define DMA_CCR_PL DMA_CCR_PL_Msk /*!< PL[1:0] bits(Channel Priority level) */
+#define DMA_CCR_PL_0 (0x1U << DMA_CCR_PL_Pos) /*!< 0x00001000 */
+#define DMA_CCR_PL_1 (0x2U << DMA_CCR_PL_Pos) /*!< 0x00002000 */
+
+#define DMA_CCR_MEM2MEM_Pos (14U)
+#define DMA_CCR_MEM2MEM_Msk (0x1U << DMA_CCR_MEM2MEM_Pos) /*!< 0x00004000 */
+#define DMA_CCR_MEM2MEM DMA_CCR_MEM2MEM_Msk /*!< Memory to memory mode */
+
+/****************** Bit definition for DMA_CNDTR register ******************/
+#define DMA_CNDTR_NDT_Pos (0U)
+#define DMA_CNDTR_NDT_Msk (0xFFFFU << DMA_CNDTR_NDT_Pos) /*!< 0x0000FFFF */
+#define DMA_CNDTR_NDT DMA_CNDTR_NDT_Msk /*!< Number of data to Transfer */
+
+/****************** Bit definition for DMA_CPAR register *******************/
+#define DMA_CPAR_PA_Pos (0U)
+#define DMA_CPAR_PA_Msk (0xFFFFFFFFU << DMA_CPAR_PA_Pos) /*!< 0xFFFFFFFF */
+#define DMA_CPAR_PA DMA_CPAR_PA_Msk /*!< Peripheral Address */
+
+/****************** Bit definition for DMA_CMAR register *******************/
+#define DMA_CMAR_MA_Pos (0U)
+#define DMA_CMAR_MA_Msk (0xFFFFFFFFU << DMA_CMAR_MA_Pos) /*!< 0xFFFFFFFF */
+#define DMA_CMAR_MA DMA_CMAR_MA_Msk /*!< Memory Address */
+
+/******************************************************************************/
+/* */
+/* Analog to Digital Converter (ADC) */
+/* */
+/******************************************************************************/
+
+/*
+ * @brief Specific device feature definitions (not present on all devices in the STM32F1 family)
+ */
+#define ADC_MULTIMODE_SUPPORT /*!< ADC feature available only on specific devices: multimode available on devices with several ADC instances */
+
+/******************** Bit definition for ADC_SR register ********************/
+#define ADC_SR_AWD_Pos (0U)
+#define ADC_SR_AWD_Msk (0x1U << ADC_SR_AWD_Pos) /*!< 0x00000001 */
+#define ADC_SR_AWD ADC_SR_AWD_Msk /*!< ADC analog watchdog 1 flag */
+#define ADC_SR_EOS_Pos (1U)
+#define ADC_SR_EOS_Msk (0x1U << ADC_SR_EOS_Pos) /*!< 0x00000002 */
+#define ADC_SR_EOS ADC_SR_EOS_Msk /*!< ADC group regular end of sequence conversions flag */
+#define ADC_SR_JEOS_Pos (2U)
+#define ADC_SR_JEOS_Msk (0x1U << ADC_SR_JEOS_Pos) /*!< 0x00000004 */
+#define ADC_SR_JEOS ADC_SR_JEOS_Msk /*!< ADC group injected end of sequence conversions flag */
+#define ADC_SR_JSTRT_Pos (3U)
+#define ADC_SR_JSTRT_Msk (0x1U << ADC_SR_JSTRT_Pos) /*!< 0x00000008 */
+#define ADC_SR_JSTRT ADC_SR_JSTRT_Msk /*!< ADC group injected conversion start flag */
+#define ADC_SR_STRT_Pos (4U)
+#define ADC_SR_STRT_Msk (0x1U << ADC_SR_STRT_Pos) /*!< 0x00000010 */
+#define ADC_SR_STRT ADC_SR_STRT_Msk /*!< ADC group regular conversion start flag */
+
+/* Legacy defines */
+#define ADC_SR_EOC (ADC_SR_EOS)
+#define ADC_SR_JEOC (ADC_SR_JEOS)
+
+/******************* Bit definition for ADC_CR1 register ********************/
+#define ADC_CR1_AWDCH_Pos (0U)
+#define ADC_CR1_AWDCH_Msk (0x1FU << ADC_CR1_AWDCH_Pos) /*!< 0x0000001F */
+#define ADC_CR1_AWDCH ADC_CR1_AWDCH_Msk /*!< ADC analog watchdog 1 monitored channel selection */
+#define ADC_CR1_AWDCH_0 (0x01U << ADC_CR1_AWDCH_Pos) /*!< 0x00000001 */
+#define ADC_CR1_AWDCH_1 (0x02U << ADC_CR1_AWDCH_Pos) /*!< 0x00000002 */
+#define ADC_CR1_AWDCH_2 (0x04U << ADC_CR1_AWDCH_Pos) /*!< 0x00000004 */
+#define ADC_CR1_AWDCH_3 (0x08U << ADC_CR1_AWDCH_Pos) /*!< 0x00000008 */
+#define ADC_CR1_AWDCH_4 (0x10U << ADC_CR1_AWDCH_Pos) /*!< 0x00000010 */
+
+#define ADC_CR1_EOSIE_Pos (5U)
+#define ADC_CR1_EOSIE_Msk (0x1U << ADC_CR1_EOSIE_Pos) /*!< 0x00000020 */
+#define ADC_CR1_EOSIE ADC_CR1_EOSIE_Msk /*!< ADC group regular end of sequence conversions interrupt */
+#define ADC_CR1_AWDIE_Pos (6U)
+#define ADC_CR1_AWDIE_Msk (0x1U << ADC_CR1_AWDIE_Pos) /*!< 0x00000040 */
+#define ADC_CR1_AWDIE ADC_CR1_AWDIE_Msk /*!< ADC analog watchdog 1 interrupt */
+#define ADC_CR1_JEOSIE_Pos (7U)
+#define ADC_CR1_JEOSIE_Msk (0x1U << ADC_CR1_JEOSIE_Pos) /*!< 0x00000080 */
+#define ADC_CR1_JEOSIE ADC_CR1_JEOSIE_Msk /*!< ADC group injected end of sequence conversions interrupt */
+#define ADC_CR1_SCAN_Pos (8U)
+#define ADC_CR1_SCAN_Msk (0x1U << ADC_CR1_SCAN_Pos) /*!< 0x00000100 */
+#define ADC_CR1_SCAN ADC_CR1_SCAN_Msk /*!< ADC scan mode */
+#define ADC_CR1_AWDSGL_Pos (9U)
+#define ADC_CR1_AWDSGL_Msk (0x1U << ADC_CR1_AWDSGL_Pos) /*!< 0x00000200 */
+#define ADC_CR1_AWDSGL ADC_CR1_AWDSGL_Msk /*!< ADC analog watchdog 1 monitoring a single channel or all channels */
+#define ADC_CR1_JAUTO_Pos (10U)
+#define ADC_CR1_JAUTO_Msk (0x1U << ADC_CR1_JAUTO_Pos) /*!< 0x00000400 */
+#define ADC_CR1_JAUTO ADC_CR1_JAUTO_Msk /*!< ADC group injected automatic trigger mode */
+#define ADC_CR1_DISCEN_Pos (11U)
+#define ADC_CR1_DISCEN_Msk (0x1U << ADC_CR1_DISCEN_Pos) /*!< 0x00000800 */
+#define ADC_CR1_DISCEN ADC_CR1_DISCEN_Msk /*!< ADC group regular sequencer discontinuous mode */
+#define ADC_CR1_JDISCEN_Pos (12U)
+#define ADC_CR1_JDISCEN_Msk (0x1U << ADC_CR1_JDISCEN_Pos) /*!< 0x00001000 */
+#define ADC_CR1_JDISCEN ADC_CR1_JDISCEN_Msk /*!< ADC group injected sequencer discontinuous mode */
+
+#define ADC_CR1_DISCNUM_Pos (13U)
+#define ADC_CR1_DISCNUM_Msk (0x7U << ADC_CR1_DISCNUM_Pos) /*!< 0x0000E000 */
+#define ADC_CR1_DISCNUM ADC_CR1_DISCNUM_Msk /*!< ADC group regular sequencer discontinuous number of ranks */
+#define ADC_CR1_DISCNUM_0 (0x1U << ADC_CR1_DISCNUM_Pos) /*!< 0x00002000 */
+#define ADC_CR1_DISCNUM_1 (0x2U << ADC_CR1_DISCNUM_Pos) /*!< 0x00004000 */
+#define ADC_CR1_DISCNUM_2 (0x4U << ADC_CR1_DISCNUM_Pos) /*!< 0x00008000 */
+
+#define ADC_CR1_DUALMOD_Pos (16U)
+#define ADC_CR1_DUALMOD_Msk (0xFU << ADC_CR1_DUALMOD_Pos) /*!< 0x000F0000 */
+#define ADC_CR1_DUALMOD ADC_CR1_DUALMOD_Msk /*!< ADC multimode mode selection */
+#define ADC_CR1_DUALMOD_0 (0x1U << ADC_CR1_DUALMOD_Pos) /*!< 0x00010000 */
+#define ADC_CR1_DUALMOD_1 (0x2U << ADC_CR1_DUALMOD_Pos) /*!< 0x00020000 */
+#define ADC_CR1_DUALMOD_2 (0x4U << ADC_CR1_DUALMOD_Pos) /*!< 0x00040000 */
+#define ADC_CR1_DUALMOD_3 (0x8U << ADC_CR1_DUALMOD_Pos) /*!< 0x00080000 */
+
+#define ADC_CR1_JAWDEN_Pos (22U)
+#define ADC_CR1_JAWDEN_Msk (0x1U << ADC_CR1_JAWDEN_Pos) /*!< 0x00400000 */
+#define ADC_CR1_JAWDEN ADC_CR1_JAWDEN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group injected */
+#define ADC_CR1_AWDEN_Pos (23U)
+#define ADC_CR1_AWDEN_Msk (0x1U << ADC_CR1_AWDEN_Pos) /*!< 0x00800000 */
+#define ADC_CR1_AWDEN ADC_CR1_AWDEN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group regular */
+
+/* Legacy defines */
+#define ADC_CR1_EOCIE (ADC_CR1_EOSIE)
+#define ADC_CR1_JEOCIE (ADC_CR1_JEOSIE)
+
+/******************* Bit definition for ADC_CR2 register ********************/
+#define ADC_CR2_ADON_Pos (0U)
+#define ADC_CR2_ADON_Msk (0x1U << ADC_CR2_ADON_Pos) /*!< 0x00000001 */
+#define ADC_CR2_ADON ADC_CR2_ADON_Msk /*!< ADC enable */
+#define ADC_CR2_CONT_Pos (1U)
+#define ADC_CR2_CONT_Msk (0x1U << ADC_CR2_CONT_Pos) /*!< 0x00000002 */
+#define ADC_CR2_CONT ADC_CR2_CONT_Msk /*!< ADC group regular continuous conversion mode */
+#define ADC_CR2_CAL_Pos (2U)
+#define ADC_CR2_CAL_Msk (0x1U << ADC_CR2_CAL_Pos) /*!< 0x00000004 */
+#define ADC_CR2_CAL ADC_CR2_CAL_Msk /*!< ADC calibration start */
+#define ADC_CR2_RSTCAL_Pos (3U)
+#define ADC_CR2_RSTCAL_Msk (0x1U << ADC_CR2_RSTCAL_Pos) /*!< 0x00000008 */
+#define ADC_CR2_RSTCAL ADC_CR2_RSTCAL_Msk /*!< ADC calibration reset */
+#define ADC_CR2_DMA_Pos (8U)
+#define ADC_CR2_DMA_Msk (0x1U << ADC_CR2_DMA_Pos) /*!< 0x00000100 */
+#define ADC_CR2_DMA ADC_CR2_DMA_Msk /*!< ADC DMA transfer enable */
+#define ADC_CR2_ALIGN_Pos (11U)
+#define ADC_CR2_ALIGN_Msk (0x1U << ADC_CR2_ALIGN_Pos) /*!< 0x00000800 */
+#define ADC_CR2_ALIGN ADC_CR2_ALIGN_Msk /*!< ADC data alignement */
+
+#define ADC_CR2_JEXTSEL_Pos (12U)
+#define ADC_CR2_JEXTSEL_Msk (0x7U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00007000 */
+#define ADC_CR2_JEXTSEL ADC_CR2_JEXTSEL_Msk /*!< ADC group injected external trigger source */
+#define ADC_CR2_JEXTSEL_0 (0x1U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00001000 */
+#define ADC_CR2_JEXTSEL_1 (0x2U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00002000 */
+#define ADC_CR2_JEXTSEL_2 (0x4U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00004000 */
+
+#define ADC_CR2_JEXTTRIG_Pos (15U)
+#define ADC_CR2_JEXTTRIG_Msk (0x1U << ADC_CR2_JEXTTRIG_Pos) /*!< 0x00008000 */
+#define ADC_CR2_JEXTTRIG ADC_CR2_JEXTTRIG_Msk /*!< ADC group injected external trigger enable */
+
+#define ADC_CR2_EXTSEL_Pos (17U)
+#define ADC_CR2_EXTSEL_Msk (0x7U << ADC_CR2_EXTSEL_Pos) /*!< 0x000E0000 */
+#define ADC_CR2_EXTSEL ADC_CR2_EXTSEL_Msk /*!< ADC group regular external trigger source */
+#define ADC_CR2_EXTSEL_0 (0x1U << ADC_CR2_EXTSEL_Pos) /*!< 0x00020000 */
+#define ADC_CR2_EXTSEL_1 (0x2U << ADC_CR2_EXTSEL_Pos) /*!< 0x00040000 */
+#define ADC_CR2_EXTSEL_2 (0x4U << ADC_CR2_EXTSEL_Pos) /*!< 0x00080000 */
+
+#define ADC_CR2_EXTTRIG_Pos (20U)
+#define ADC_CR2_EXTTRIG_Msk (0x1U << ADC_CR2_EXTTRIG_Pos) /*!< 0x00100000 */
+#define ADC_CR2_EXTTRIG ADC_CR2_EXTTRIG_Msk /*!< ADC group regular external trigger enable */
+#define ADC_CR2_JSWSTART_Pos (21U)
+#define ADC_CR2_JSWSTART_Msk (0x1U << ADC_CR2_JSWSTART_Pos) /*!< 0x00200000 */
+#define ADC_CR2_JSWSTART ADC_CR2_JSWSTART_Msk /*!< ADC group injected conversion start */
+#define ADC_CR2_SWSTART_Pos (22U)
+#define ADC_CR2_SWSTART_Msk (0x1U << ADC_CR2_SWSTART_Pos) /*!< 0x00400000 */
+#define ADC_CR2_SWSTART ADC_CR2_SWSTART_Msk /*!< ADC group regular conversion start */
+#define ADC_CR2_TSVREFE_Pos (23U)
+#define ADC_CR2_TSVREFE_Msk (0x1U << ADC_CR2_TSVREFE_Pos) /*!< 0x00800000 */
+#define ADC_CR2_TSVREFE ADC_CR2_TSVREFE_Msk /*!< ADC internal path to VrefInt and temperature sensor enable */
+
+/****************** Bit definition for ADC_SMPR1 register *******************/
+#define ADC_SMPR1_SMP10_Pos (0U)
+#define ADC_SMPR1_SMP10_Msk (0x7U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000007 */
+#define ADC_SMPR1_SMP10 ADC_SMPR1_SMP10_Msk /*!< ADC channel 10 sampling time selection */
+#define ADC_SMPR1_SMP10_0 (0x1U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000001 */
+#define ADC_SMPR1_SMP10_1 (0x2U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000002 */
+#define ADC_SMPR1_SMP10_2 (0x4U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000004 */
+
+#define ADC_SMPR1_SMP11_Pos (3U)
+#define ADC_SMPR1_SMP11_Msk (0x7U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000038 */
+#define ADC_SMPR1_SMP11 ADC_SMPR1_SMP11_Msk /*!< ADC channel 11 sampling time selection */
+#define ADC_SMPR1_SMP11_0 (0x1U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000008 */
+#define ADC_SMPR1_SMP11_1 (0x2U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000010 */
+#define ADC_SMPR1_SMP11_2 (0x4U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000020 */
+
+#define ADC_SMPR1_SMP12_Pos (6U)
+#define ADC_SMPR1_SMP12_Msk (0x7U << ADC_SMPR1_SMP12_Pos) /*!< 0x000001C0 */
+#define ADC_SMPR1_SMP12 ADC_SMPR1_SMP12_Msk /*!< ADC channel 12 sampling time selection */
+#define ADC_SMPR1_SMP12_0 (0x1U << ADC_SMPR1_SMP12_Pos) /*!< 0x00000040 */
+#define ADC_SMPR1_SMP12_1 (0x2U << ADC_SMPR1_SMP12_Pos) /*!< 0x00000080 */
+#define ADC_SMPR1_SMP12_2 (0x4U << ADC_SMPR1_SMP12_Pos) /*!< 0x00000100 */
+
+#define ADC_SMPR1_SMP13_Pos (9U)
+#define ADC_SMPR1_SMP13_Msk (0x7U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000E00 */
+#define ADC_SMPR1_SMP13 ADC_SMPR1_SMP13_Msk /*!< ADC channel 13 sampling time selection */
+#define ADC_SMPR1_SMP13_0 (0x1U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000200 */
+#define ADC_SMPR1_SMP13_1 (0x2U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000400 */
+#define ADC_SMPR1_SMP13_2 (0x4U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000800 */
+
+#define ADC_SMPR1_SMP14_Pos (12U)
+#define ADC_SMPR1_SMP14_Msk (0x7U << ADC_SMPR1_SMP14_Pos) /*!< 0x00007000 */
+#define ADC_SMPR1_SMP14 ADC_SMPR1_SMP14_Msk /*!< ADC channel 14 sampling time selection */
+#define ADC_SMPR1_SMP14_0 (0x1U << ADC_SMPR1_SMP14_Pos) /*!< 0x00001000 */
+#define ADC_SMPR1_SMP14_1 (0x2U << ADC_SMPR1_SMP14_Pos) /*!< 0x00002000 */
+#define ADC_SMPR1_SMP14_2 (0x4U << ADC_SMPR1_SMP14_Pos) /*!< 0x00004000 */
+
+#define ADC_SMPR1_SMP15_Pos (15U)
+#define ADC_SMPR1_SMP15_Msk (0x7U << ADC_SMPR1_SMP15_Pos) /*!< 0x00038000 */
+#define ADC_SMPR1_SMP15 ADC_SMPR1_SMP15_Msk /*!< ADC channel 15 sampling time selection */
+#define ADC_SMPR1_SMP15_0 (0x1U << ADC_SMPR1_SMP15_Pos) /*!< 0x00008000 */
+#define ADC_SMPR1_SMP15_1 (0x2U << ADC_SMPR1_SMP15_Pos) /*!< 0x00010000 */
+#define ADC_SMPR1_SMP15_2 (0x4U << ADC_SMPR1_SMP15_Pos) /*!< 0x00020000 */
+
+#define ADC_SMPR1_SMP16_Pos (18U)
+#define ADC_SMPR1_SMP16_Msk (0x7U << ADC_SMPR1_SMP16_Pos) /*!< 0x001C0000 */
+#define ADC_SMPR1_SMP16 ADC_SMPR1_SMP16_Msk /*!< ADC channel 16 sampling time selection */
+#define ADC_SMPR1_SMP16_0 (0x1U << ADC_SMPR1_SMP16_Pos) /*!< 0x00040000 */
+#define ADC_SMPR1_SMP16_1 (0x2U << ADC_SMPR1_SMP16_Pos) /*!< 0x00080000 */
+#define ADC_SMPR1_SMP16_2 (0x4U << ADC_SMPR1_SMP16_Pos) /*!< 0x00100000 */
+
+#define ADC_SMPR1_SMP17_Pos (21U)
+#define ADC_SMPR1_SMP17_Msk (0x7U << ADC_SMPR1_SMP17_Pos) /*!< 0x00E00000 */
+#define ADC_SMPR1_SMP17 ADC_SMPR1_SMP17_Msk /*!< ADC channel 17 sampling time selection */
+#define ADC_SMPR1_SMP17_0 (0x1U << ADC_SMPR1_SMP17_Pos) /*!< 0x00200000 */
+#define ADC_SMPR1_SMP17_1 (0x2U << ADC_SMPR1_SMP17_Pos) /*!< 0x00400000 */
+#define ADC_SMPR1_SMP17_2 (0x4U << ADC_SMPR1_SMP17_Pos) /*!< 0x00800000 */
+
+/****************** Bit definition for ADC_SMPR2 register *******************/
+#define ADC_SMPR2_SMP0_Pos (0U)
+#define ADC_SMPR2_SMP0_Msk (0x7U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000007 */
+#define ADC_SMPR2_SMP0 ADC_SMPR2_SMP0_Msk /*!< ADC channel 0 sampling time selection */
+#define ADC_SMPR2_SMP0_0 (0x1U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000001 */
+#define ADC_SMPR2_SMP0_1 (0x2U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000002 */
+#define ADC_SMPR2_SMP0_2 (0x4U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000004 */
+
+#define ADC_SMPR2_SMP1_Pos (3U)
+#define ADC_SMPR2_SMP1_Msk (0x7U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000038 */
+#define ADC_SMPR2_SMP1 ADC_SMPR2_SMP1_Msk /*!< ADC channel 1 sampling time selection */
+#define ADC_SMPR2_SMP1_0 (0x1U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000008 */
+#define ADC_SMPR2_SMP1_1 (0x2U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000010 */
+#define ADC_SMPR2_SMP1_2 (0x4U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000020 */
+
+#define ADC_SMPR2_SMP2_Pos (6U)
+#define ADC_SMPR2_SMP2_Msk (0x7U << ADC_SMPR2_SMP2_Pos) /*!< 0x000001C0 */
+#define ADC_SMPR2_SMP2 ADC_SMPR2_SMP2_Msk /*!< ADC channel 2 sampling time selection */
+#define ADC_SMPR2_SMP2_0 (0x1U << ADC_SMPR2_SMP2_Pos) /*!< 0x00000040 */
+#define ADC_SMPR2_SMP2_1 (0x2U << ADC_SMPR2_SMP2_Pos) /*!< 0x00000080 */
+#define ADC_SMPR2_SMP2_2 (0x4U << ADC_SMPR2_SMP2_Pos) /*!< 0x00000100 */
+
+#define ADC_SMPR2_SMP3_Pos (9U)
+#define ADC_SMPR2_SMP3_Msk (0x7U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000E00 */
+#define ADC_SMPR2_SMP3 ADC_SMPR2_SMP3_Msk /*!< ADC channel 3 sampling time selection */
+#define ADC_SMPR2_SMP3_0 (0x1U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000200 */
+#define ADC_SMPR2_SMP3_1 (0x2U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000400 */
+#define ADC_SMPR2_SMP3_2 (0x4U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000800 */
+
+#define ADC_SMPR2_SMP4_Pos (12U)
+#define ADC_SMPR2_SMP4_Msk (0x7U << ADC_SMPR2_SMP4_Pos) /*!< 0x00007000 */
+#define ADC_SMPR2_SMP4 ADC_SMPR2_SMP4_Msk /*!< ADC channel 4 sampling time selection */
+#define ADC_SMPR2_SMP4_0 (0x1U << ADC_SMPR2_SMP4_Pos) /*!< 0x00001000 */
+#define ADC_SMPR2_SMP4_1 (0x2U << ADC_SMPR2_SMP4_Pos) /*!< 0x00002000 */
+#define ADC_SMPR2_SMP4_2 (0x4U << ADC_SMPR2_SMP4_Pos) /*!< 0x00004000 */
+
+#define ADC_SMPR2_SMP5_Pos (15U)
+#define ADC_SMPR2_SMP5_Msk (0x7U << ADC_SMPR2_SMP5_Pos) /*!< 0x00038000 */
+#define ADC_SMPR2_SMP5 ADC_SMPR2_SMP5_Msk /*!< ADC channel 5 sampling time selection */
+#define ADC_SMPR2_SMP5_0 (0x1U << ADC_SMPR2_SMP5_Pos) /*!< 0x00008000 */
+#define ADC_SMPR2_SMP5_1 (0x2U << ADC_SMPR2_SMP5_Pos) /*!< 0x00010000 */
+#define ADC_SMPR2_SMP5_2 (0x4U << ADC_SMPR2_SMP5_Pos) /*!< 0x00020000 */
+
+#define ADC_SMPR2_SMP6_Pos (18U)
+#define ADC_SMPR2_SMP6_Msk (0x7U << ADC_SMPR2_SMP6_Pos) /*!< 0x001C0000 */
+#define ADC_SMPR2_SMP6 ADC_SMPR2_SMP6_Msk /*!< ADC channel 6 sampling time selection */
+#define ADC_SMPR2_SMP6_0 (0x1U << ADC_SMPR2_SMP6_Pos) /*!< 0x00040000 */
+#define ADC_SMPR2_SMP6_1 (0x2U << ADC_SMPR2_SMP6_Pos) /*!< 0x00080000 */
+#define ADC_SMPR2_SMP6_2 (0x4U << ADC_SMPR2_SMP6_Pos) /*!< 0x00100000 */
+
+#define ADC_SMPR2_SMP7_Pos (21U)
+#define ADC_SMPR2_SMP7_Msk (0x7U << ADC_SMPR2_SMP7_Pos) /*!< 0x00E00000 */
+#define ADC_SMPR2_SMP7 ADC_SMPR2_SMP7_Msk /*!< ADC channel 7 sampling time selection */
+#define ADC_SMPR2_SMP7_0 (0x1U << ADC_SMPR2_SMP7_Pos) /*!< 0x00200000 */
+#define ADC_SMPR2_SMP7_1 (0x2U << ADC_SMPR2_SMP7_Pos) /*!< 0x00400000 */
+#define ADC_SMPR2_SMP7_2 (0x4U << ADC_SMPR2_SMP7_Pos) /*!< 0x00800000 */
+
+#define ADC_SMPR2_SMP8_Pos (24U)
+#define ADC_SMPR2_SMP8_Msk (0x7U << ADC_SMPR2_SMP8_Pos) /*!< 0x07000000 */
+#define ADC_SMPR2_SMP8 ADC_SMPR2_SMP8_Msk /*!< ADC channel 8 sampling time selection */
+#define ADC_SMPR2_SMP8_0 (0x1U << ADC_SMPR2_SMP8_Pos) /*!< 0x01000000 */
+#define ADC_SMPR2_SMP8_1 (0x2U << ADC_SMPR2_SMP8_Pos) /*!< 0x02000000 */
+#define ADC_SMPR2_SMP8_2 (0x4U << ADC_SMPR2_SMP8_Pos) /*!< 0x04000000 */
+
+#define ADC_SMPR2_SMP9_Pos (27U)
+#define ADC_SMPR2_SMP9_Msk (0x7U << ADC_SMPR2_SMP9_Pos) /*!< 0x38000000 */
+#define ADC_SMPR2_SMP9 ADC_SMPR2_SMP9_Msk /*!< ADC channel 9 sampling time selection */
+#define ADC_SMPR2_SMP9_0 (0x1U << ADC_SMPR2_SMP9_Pos) /*!< 0x08000000 */
+#define ADC_SMPR2_SMP9_1 (0x2U << ADC_SMPR2_SMP9_Pos) /*!< 0x10000000 */
+#define ADC_SMPR2_SMP9_2 (0x4U << ADC_SMPR2_SMP9_Pos) /*!< 0x20000000 */
+
+/****************** Bit definition for ADC_JOFR1 register *******************/
+#define ADC_JOFR1_JOFFSET1_Pos (0U)
+#define ADC_JOFR1_JOFFSET1_Msk (0xFFFU << ADC_JOFR1_JOFFSET1_Pos) /*!< 0x00000FFF */
+#define ADC_JOFR1_JOFFSET1 ADC_JOFR1_JOFFSET1_Msk /*!< ADC group injected sequencer rank 1 offset value */
+
+/****************** Bit definition for ADC_JOFR2 register *******************/
+#define ADC_JOFR2_JOFFSET2_Pos (0U)
+#define ADC_JOFR2_JOFFSET2_Msk (0xFFFU << ADC_JOFR2_JOFFSET2_Pos) /*!< 0x00000FFF */
+#define ADC_JOFR2_JOFFSET2 ADC_JOFR2_JOFFSET2_Msk /*!< ADC group injected sequencer rank 2 offset value */
+
+/****************** Bit definition for ADC_JOFR3 register *******************/
+#define ADC_JOFR3_JOFFSET3_Pos (0U)
+#define ADC_JOFR3_JOFFSET3_Msk (0xFFFU << ADC_JOFR3_JOFFSET3_Pos) /*!< 0x00000FFF */
+#define ADC_JOFR3_JOFFSET3 ADC_JOFR3_JOFFSET3_Msk /*!< ADC group injected sequencer rank 3 offset value */
+
+/****************** Bit definition for ADC_JOFR4 register *******************/
+#define ADC_JOFR4_JOFFSET4_Pos (0U)
+#define ADC_JOFR4_JOFFSET4_Msk (0xFFFU << ADC_JOFR4_JOFFSET4_Pos) /*!< 0x00000FFF */
+#define ADC_JOFR4_JOFFSET4 ADC_JOFR4_JOFFSET4_Msk /*!< ADC group injected sequencer rank 4 offset value */
+
+/******************* Bit definition for ADC_HTR register ********************/
+#define ADC_HTR_HT_Pos (0U)
+#define ADC_HTR_HT_Msk (0xFFFU << ADC_HTR_HT_Pos) /*!< 0x00000FFF */
+#define ADC_HTR_HT ADC_HTR_HT_Msk /*!< ADC analog watchdog 1 threshold high */
+
+/******************* Bit definition for ADC_LTR register ********************/
+#define ADC_LTR_LT_Pos (0U)
+#define ADC_LTR_LT_Msk (0xFFFU << ADC_LTR_LT_Pos) /*!< 0x00000FFF */
+#define ADC_LTR_LT ADC_LTR_LT_Msk /*!< ADC analog watchdog 1 threshold low */
+
+/******************* Bit definition for ADC_SQR1 register *******************/
+#define ADC_SQR1_SQ13_Pos (0U)
+#define ADC_SQR1_SQ13_Msk (0x1FU << ADC_SQR1_SQ13_Pos) /*!< 0x0000001F */
+#define ADC_SQR1_SQ13 ADC_SQR1_SQ13_Msk /*!< ADC group regular sequencer rank 13 */
+#define ADC_SQR1_SQ13_0 (0x01U << ADC_SQR1_SQ13_Pos) /*!< 0x00000001 */
+#define ADC_SQR1_SQ13_1 (0x02U << ADC_SQR1_SQ13_Pos) /*!< 0x00000002 */
+#define ADC_SQR1_SQ13_2 (0x04U << ADC_SQR1_SQ13_Pos) /*!< 0x00000004 */
+#define ADC_SQR1_SQ13_3 (0x08U << ADC_SQR1_SQ13_Pos) /*!< 0x00000008 */
+#define ADC_SQR1_SQ13_4 (0x10U << ADC_SQR1_SQ13_Pos) /*!< 0x00000010 */
+
+#define ADC_SQR1_SQ14_Pos (5U)
+#define ADC_SQR1_SQ14_Msk (0x1FU << ADC_SQR1_SQ14_Pos) /*!< 0x000003E0 */
+#define ADC_SQR1_SQ14 ADC_SQR1_SQ14_Msk /*!< ADC group regular sequencer rank 14 */
+#define ADC_SQR1_SQ14_0 (0x01U << ADC_SQR1_SQ14_Pos) /*!< 0x00000020 */
+#define ADC_SQR1_SQ14_1 (0x02U << ADC_SQR1_SQ14_Pos) /*!< 0x00000040 */
+#define ADC_SQR1_SQ14_2 (0x04U << ADC_SQR1_SQ14_Pos) /*!< 0x00000080 */
+#define ADC_SQR1_SQ14_3 (0x08U << ADC_SQR1_SQ14_Pos) /*!< 0x00000100 */
+#define ADC_SQR1_SQ14_4 (0x10U << ADC_SQR1_SQ14_Pos) /*!< 0x00000200 */
+
+#define ADC_SQR1_SQ15_Pos (10U)
+#define ADC_SQR1_SQ15_Msk (0x1FU << ADC_SQR1_SQ15_Pos) /*!< 0x00007C00 */
+#define ADC_SQR1_SQ15 ADC_SQR1_SQ15_Msk /*!< ADC group regular sequencer rank 15 */
+#define ADC_SQR1_SQ15_0 (0x01U << ADC_SQR1_SQ15_Pos) /*!< 0x00000400 */
+#define ADC_SQR1_SQ15_1 (0x02U << ADC_SQR1_SQ15_Pos) /*!< 0x00000800 */
+#define ADC_SQR1_SQ15_2 (0x04U << ADC_SQR1_SQ15_Pos) /*!< 0x00001000 */
+#define ADC_SQR1_SQ15_3 (0x08U << ADC_SQR1_SQ15_Pos) /*!< 0x00002000 */
+#define ADC_SQR1_SQ15_4 (0x10U << ADC_SQR1_SQ15_Pos) /*!< 0x00004000 */
+
+#define ADC_SQR1_SQ16_Pos (15U)
+#define ADC_SQR1_SQ16_Msk (0x1FU << ADC_SQR1_SQ16_Pos) /*!< 0x000F8000 */
+#define ADC_SQR1_SQ16 ADC_SQR1_SQ16_Msk /*!< ADC group regular sequencer rank 16 */
+#define ADC_SQR1_SQ16_0 (0x01U << ADC_SQR1_SQ16_Pos) /*!< 0x00008000 */
+#define ADC_SQR1_SQ16_1 (0x02U << ADC_SQR1_SQ16_Pos) /*!< 0x00010000 */
+#define ADC_SQR1_SQ16_2 (0x04U << ADC_SQR1_SQ16_Pos) /*!< 0x00020000 */
+#define ADC_SQR1_SQ16_3 (0x08U << ADC_SQR1_SQ16_Pos) /*!< 0x00040000 */
+#define ADC_SQR1_SQ16_4 (0x10U << ADC_SQR1_SQ16_Pos) /*!< 0x00080000 */
+
+#define ADC_SQR1_L_Pos (20U)
+#define ADC_SQR1_L_Msk (0xFU << ADC_SQR1_L_Pos) /*!< 0x00F00000 */
+#define ADC_SQR1_L ADC_SQR1_L_Msk /*!< ADC group regular sequencer scan length */
+#define ADC_SQR1_L_0 (0x1U << ADC_SQR1_L_Pos) /*!< 0x00100000 */
+#define ADC_SQR1_L_1 (0x2U << ADC_SQR1_L_Pos) /*!< 0x00200000 */
+#define ADC_SQR1_L_2 (0x4U << ADC_SQR1_L_Pos) /*!< 0x00400000 */
+#define ADC_SQR1_L_3 (0x8U << ADC_SQR1_L_Pos) /*!< 0x00800000 */
+
+/******************* Bit definition for ADC_SQR2 register *******************/
+#define ADC_SQR2_SQ7_Pos (0U)
+#define ADC_SQR2_SQ7_Msk (0x1FU << ADC_SQR2_SQ7_Pos) /*!< 0x0000001F */
+#define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk /*!< ADC group regular sequencer rank 7 */
+#define ADC_SQR2_SQ7_0 (0x01U << ADC_SQR2_SQ7_Pos) /*!< 0x00000001 */
+#define ADC_SQR2_SQ7_1 (0x02U << ADC_SQR2_SQ7_Pos) /*!< 0x00000002 */
+#define ADC_SQR2_SQ7_2 (0x04U << ADC_SQR2_SQ7_Pos) /*!< 0x00000004 */
+#define ADC_SQR2_SQ7_3 (0x08U << ADC_SQR2_SQ7_Pos) /*!< 0x00000008 */
+#define ADC_SQR2_SQ7_4 (0x10U << ADC_SQR2_SQ7_Pos) /*!< 0x00000010 */
+
+#define ADC_SQR2_SQ8_Pos (5U)
+#define ADC_SQR2_SQ8_Msk (0x1FU << ADC_SQR2_SQ8_Pos) /*!< 0x000003E0 */
+#define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk /*!< ADC group regular sequencer rank 8 */
+#define ADC_SQR2_SQ8_0 (0x01U << ADC_SQR2_SQ8_Pos) /*!< 0x00000020 */
+#define ADC_SQR2_SQ8_1 (0x02U << ADC_SQR2_SQ8_Pos) /*!< 0x00000040 */
+#define ADC_SQR2_SQ8_2 (0x04U << ADC_SQR2_SQ8_Pos) /*!< 0x00000080 */
+#define ADC_SQR2_SQ8_3 (0x08U << ADC_SQR2_SQ8_Pos) /*!< 0x00000100 */
+#define ADC_SQR2_SQ8_4 (0x10U << ADC_SQR2_SQ8_Pos) /*!< 0x00000200 */
+
+#define ADC_SQR2_SQ9_Pos (10U)
+#define ADC_SQR2_SQ9_Msk (0x1FU << ADC_SQR2_SQ9_Pos) /*!< 0x00007C00 */
+#define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk /*!< ADC group regular sequencer rank 9 */
+#define ADC_SQR2_SQ9_0 (0x01U << ADC_SQR2_SQ9_Pos) /*!< 0x00000400 */
+#define ADC_SQR2_SQ9_1 (0x02U << ADC_SQR2_SQ9_Pos) /*!< 0x00000800 */
+#define ADC_SQR2_SQ9_2 (0x04U << ADC_SQR2_SQ9_Pos) /*!< 0x00001000 */
+#define ADC_SQR2_SQ9_3 (0x08U << ADC_SQR2_SQ9_Pos) /*!< 0x00002000 */
+#define ADC_SQR2_SQ9_4 (0x10U << ADC_SQR2_SQ9_Pos) /*!< 0x00004000 */
+
+#define ADC_SQR2_SQ10_Pos (15U)
+#define ADC_SQR2_SQ10_Msk (0x1FU << ADC_SQR2_SQ10_Pos) /*!< 0x000F8000 */
+#define ADC_SQR2_SQ10 ADC_SQR2_SQ10_Msk /*!< ADC group regular sequencer rank 10 */
+#define ADC_SQR2_SQ10_0 (0x01U << ADC_SQR2_SQ10_Pos) /*!< 0x00008000 */
+#define ADC_SQR2_SQ10_1 (0x02U << ADC_SQR2_SQ10_Pos) /*!< 0x00010000 */
+#define ADC_SQR2_SQ10_2 (0x04U << ADC_SQR2_SQ10_Pos) /*!< 0x00020000 */
+#define ADC_SQR2_SQ10_3 (0x08U << ADC_SQR2_SQ10_Pos) /*!< 0x00040000 */
+#define ADC_SQR2_SQ10_4 (0x10U << ADC_SQR2_SQ10_Pos) /*!< 0x00080000 */
+
+#define ADC_SQR2_SQ11_Pos (20U)
+#define ADC_SQR2_SQ11_Msk (0x1FU << ADC_SQR2_SQ11_Pos) /*!< 0x01F00000 */
+#define ADC_SQR2_SQ11 ADC_SQR2_SQ11_Msk /*!< ADC group regular sequencer rank 1 */
+#define ADC_SQR2_SQ11_0 (0x01U << ADC_SQR2_SQ11_Pos) /*!< 0x00100000 */
+#define ADC_SQR2_SQ11_1 (0x02U << ADC_SQR2_SQ11_Pos) /*!< 0x00200000 */
+#define ADC_SQR2_SQ11_2 (0x04U << ADC_SQR2_SQ11_Pos) /*!< 0x00400000 */
+#define ADC_SQR2_SQ11_3 (0x08U << ADC_SQR2_SQ11_Pos) /*!< 0x00800000 */
+#define ADC_SQR2_SQ11_4 (0x10U << ADC_SQR2_SQ11_Pos) /*!< 0x01000000 */
+
+#define ADC_SQR2_SQ12_Pos (25U)
+#define ADC_SQR2_SQ12_Msk (0x1FU << ADC_SQR2_SQ12_Pos) /*!< 0x3E000000 */
+#define ADC_SQR2_SQ12 ADC_SQR2_SQ12_Msk /*!< ADC group regular sequencer rank 12 */
+#define ADC_SQR2_SQ12_0 (0x01U << ADC_SQR2_SQ12_Pos) /*!< 0x02000000 */
+#define ADC_SQR2_SQ12_1 (0x02U << ADC_SQR2_SQ12_Pos) /*!< 0x04000000 */
+#define ADC_SQR2_SQ12_2 (0x04U << ADC_SQR2_SQ12_Pos) /*!< 0x08000000 */
+#define ADC_SQR2_SQ12_3 (0x08U << ADC_SQR2_SQ12_Pos) /*!< 0x10000000 */
+#define ADC_SQR2_SQ12_4 (0x10U << ADC_SQR2_SQ12_Pos) /*!< 0x20000000 */
+
+/******************* Bit definition for ADC_SQR3 register *******************/
+#define ADC_SQR3_SQ1_Pos (0U)
+#define ADC_SQR3_SQ1_Msk (0x1FU << ADC_SQR3_SQ1_Pos) /*!< 0x0000001F */
+#define ADC_SQR3_SQ1 ADC_SQR3_SQ1_Msk /*!< ADC group regular sequencer rank 1 */
+#define ADC_SQR3_SQ1_0 (0x01U << ADC_SQR3_SQ1_Pos) /*!< 0x00000001 */
+#define ADC_SQR3_SQ1_1 (0x02U << ADC_SQR3_SQ1_Pos) /*!< 0x00000002 */
+#define ADC_SQR3_SQ1_2 (0x04U << ADC_SQR3_SQ1_Pos) /*!< 0x00000004 */
+#define ADC_SQR3_SQ1_3 (0x08U << ADC_SQR3_SQ1_Pos) /*!< 0x00000008 */
+#define ADC_SQR3_SQ1_4 (0x10U << ADC_SQR3_SQ1_Pos) /*!< 0x00000010 */
+
+#define ADC_SQR3_SQ2_Pos (5U)
+#define ADC_SQR3_SQ2_Msk (0x1FU << ADC_SQR3_SQ2_Pos) /*!< 0x000003E0 */
+#define ADC_SQR3_SQ2 ADC_SQR3_SQ2_Msk /*!< ADC group regular sequencer rank 2 */
+#define ADC_SQR3_SQ2_0 (0x01U << ADC_SQR3_SQ2_Pos) /*!< 0x00000020 */
+#define ADC_SQR3_SQ2_1 (0x02U << ADC_SQR3_SQ2_Pos) /*!< 0x00000040 */
+#define ADC_SQR3_SQ2_2 (0x04U << ADC_SQR3_SQ2_Pos) /*!< 0x00000080 */
+#define ADC_SQR3_SQ2_3 (0x08U << ADC_SQR3_SQ2_Pos) /*!< 0x00000100 */
+#define ADC_SQR3_SQ2_4 (0x10U << ADC_SQR3_SQ2_Pos) /*!< 0x00000200 */
+
+#define ADC_SQR3_SQ3_Pos (10U)
+#define ADC_SQR3_SQ3_Msk (0x1FU << ADC_SQR3_SQ3_Pos) /*!< 0x00007C00 */
+#define ADC_SQR3_SQ3 ADC_SQR3_SQ3_Msk /*!< ADC group regular sequencer rank 3 */
+#define ADC_SQR3_SQ3_0 (0x01U << ADC_SQR3_SQ3_Pos) /*!< 0x00000400 */
+#define ADC_SQR3_SQ3_1 (0x02U << ADC_SQR3_SQ3_Pos) /*!< 0x00000800 */
+#define ADC_SQR3_SQ3_2 (0x04U << ADC_SQR3_SQ3_Pos) /*!< 0x00001000 */
+#define ADC_SQR3_SQ3_3 (0x08U << ADC_SQR3_SQ3_Pos) /*!< 0x00002000 */
+#define ADC_SQR3_SQ3_4 (0x10U << ADC_SQR3_SQ3_Pos) /*!< 0x00004000 */
+
+#define ADC_SQR3_SQ4_Pos (15U)
+#define ADC_SQR3_SQ4_Msk (0x1FU << ADC_SQR3_SQ4_Pos) /*!< 0x000F8000 */
+#define ADC_SQR3_SQ4 ADC_SQR3_SQ4_Msk /*!< ADC group regular sequencer rank 4 */
+#define ADC_SQR3_SQ4_0 (0x01U << ADC_SQR3_SQ4_Pos) /*!< 0x00008000 */
+#define ADC_SQR3_SQ4_1 (0x02U << ADC_SQR3_SQ4_Pos) /*!< 0x00010000 */
+#define ADC_SQR3_SQ4_2 (0x04U << ADC_SQR3_SQ4_Pos) /*!< 0x00020000 */
+#define ADC_SQR3_SQ4_3 (0x08U << ADC_SQR3_SQ4_Pos) /*!< 0x00040000 */
+#define ADC_SQR3_SQ4_4 (0x10U << ADC_SQR3_SQ4_Pos) /*!< 0x00080000 */
+
+#define ADC_SQR3_SQ5_Pos (20U)
+#define ADC_SQR3_SQ5_Msk (0x1FU << ADC_SQR3_SQ5_Pos) /*!< 0x01F00000 */
+#define ADC_SQR3_SQ5 ADC_SQR3_SQ5_Msk /*!< ADC group regular sequencer rank 5 */
+#define ADC_SQR3_SQ5_0 (0x01U << ADC_SQR3_SQ5_Pos) /*!< 0x00100000 */
+#define ADC_SQR3_SQ5_1 (0x02U << ADC_SQR3_SQ5_Pos) /*!< 0x00200000 */
+#define ADC_SQR3_SQ5_2 (0x04U << ADC_SQR3_SQ5_Pos) /*!< 0x00400000 */
+#define ADC_SQR3_SQ5_3 (0x08U << ADC_SQR3_SQ5_Pos) /*!< 0x00800000 */
+#define ADC_SQR3_SQ5_4 (0x10U << ADC_SQR3_SQ5_Pos) /*!< 0x01000000 */
+
+#define ADC_SQR3_SQ6_Pos (25U)
+#define ADC_SQR3_SQ6_Msk (0x1FU << ADC_SQR3_SQ6_Pos) /*!< 0x3E000000 */
+#define ADC_SQR3_SQ6 ADC_SQR3_SQ6_Msk /*!< ADC group regular sequencer rank 6 */
+#define ADC_SQR3_SQ6_0 (0x01U << ADC_SQR3_SQ6_Pos) /*!< 0x02000000 */
+#define ADC_SQR3_SQ6_1 (0x02U << ADC_SQR3_SQ6_Pos) /*!< 0x04000000 */
+#define ADC_SQR3_SQ6_2 (0x04U << ADC_SQR3_SQ6_Pos) /*!< 0x08000000 */
+#define ADC_SQR3_SQ6_3 (0x08U << ADC_SQR3_SQ6_Pos) /*!< 0x10000000 */
+#define ADC_SQR3_SQ6_4 (0x10U << ADC_SQR3_SQ6_Pos) /*!< 0x20000000 */
+
+/******************* Bit definition for ADC_JSQR register *******************/
+#define ADC_JSQR_JSQ1_Pos (0U)
+#define ADC_JSQR_JSQ1_Msk (0x1FU << ADC_JSQR_JSQ1_Pos) /*!< 0x0000001F */
+#define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!< ADC group injected sequencer rank 1 */
+#define ADC_JSQR_JSQ1_0 (0x01U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000001 */
+#define ADC_JSQR_JSQ1_1 (0x02U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000002 */
+#define ADC_JSQR_JSQ1_2 (0x04U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000004 */
+#define ADC_JSQR_JSQ1_3 (0x08U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000008 */
+#define ADC_JSQR_JSQ1_4 (0x10U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000010 */
+
+#define ADC_JSQR_JSQ2_Pos (5U)
+#define ADC_JSQR_JSQ2_Msk (0x1FU << ADC_JSQR_JSQ2_Pos) /*!< 0x000003E0 */
+#define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!< ADC group injected sequencer rank 2 */
+#define ADC_JSQR_JSQ2_0 (0x01U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000020 */
+#define ADC_JSQR_JSQ2_1 (0x02U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000040 */
+#define ADC_JSQR_JSQ2_2 (0x04U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000080 */
+#define ADC_JSQR_JSQ2_3 (0x08U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000100 */
+#define ADC_JSQR_JSQ2_4 (0x10U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000200 */
+
+#define ADC_JSQR_JSQ3_Pos (10U)
+#define ADC_JSQR_JSQ3_Msk (0x1FU << ADC_JSQR_JSQ3_Pos) /*!< 0x00007C00 */
+#define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!< ADC group injected sequencer rank 3 */
+#define ADC_JSQR_JSQ3_0 (0x01U << ADC_JSQR_JSQ3_Pos) /*!< 0x00000400 */
+#define ADC_JSQR_JSQ3_1 (0x02U << ADC_JSQR_JSQ3_Pos) /*!< 0x00000800 */
+#define ADC_JSQR_JSQ3_2 (0x04U << ADC_JSQR_JSQ3_Pos) /*!< 0x00001000 */
+#define ADC_JSQR_JSQ3_3 (0x08U << ADC_JSQR_JSQ3_Pos) /*!< 0x00002000 */
+#define ADC_JSQR_JSQ3_4 (0x10U << ADC_JSQR_JSQ3_Pos) /*!< 0x00004000 */
+
+#define ADC_JSQR_JSQ4_Pos (15U)
+#define ADC_JSQR_JSQ4_Msk (0x1FU << ADC_JSQR_JSQ4_Pos) /*!< 0x000F8000 */
+#define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!< ADC group injected sequencer rank 4 */
+#define ADC_JSQR_JSQ4_0 (0x01U << ADC_JSQR_JSQ4_Pos) /*!< 0x00008000 */
+#define ADC_JSQR_JSQ4_1 (0x02U << ADC_JSQR_JSQ4_Pos) /*!< 0x00010000 */
+#define ADC_JSQR_JSQ4_2 (0x04U << ADC_JSQR_JSQ4_Pos) /*!< 0x00020000 */
+#define ADC_JSQR_JSQ4_3 (0x08U << ADC_JSQR_JSQ4_Pos) /*!< 0x00040000 */
+#define ADC_JSQR_JSQ4_4 (0x10U << ADC_JSQR_JSQ4_Pos) /*!< 0x00080000 */
+
+#define ADC_JSQR_JL_Pos (20U)
+#define ADC_JSQR_JL_Msk (0x3U << ADC_JSQR_JL_Pos) /*!< 0x00300000 */
+#define ADC_JSQR_JL ADC_JSQR_JL_Msk /*!< ADC group injected sequencer scan length */
+#define ADC_JSQR_JL_0 (0x1U << ADC_JSQR_JL_Pos) /*!< 0x00100000 */
+#define ADC_JSQR_JL_1 (0x2U << ADC_JSQR_JL_Pos) /*!< 0x00200000 */
+
+/******************* Bit definition for ADC_JDR1 register *******************/
+#define ADC_JDR1_JDATA_Pos (0U)
+#define ADC_JDR1_JDATA_Msk (0xFFFFU << ADC_JDR1_JDATA_Pos) /*!< 0x0000FFFF */
+#define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!< ADC group injected sequencer rank 1 conversion data */
+
+/******************* Bit definition for ADC_JDR2 register *******************/
+#define ADC_JDR2_JDATA_Pos (0U)
+#define ADC_JDR2_JDATA_Msk (0xFFFFU << ADC_JDR2_JDATA_Pos) /*!< 0x0000FFFF */
+#define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!< ADC group injected sequencer rank 2 conversion data */
+
+/******************* Bit definition for ADC_JDR3 register *******************/
+#define ADC_JDR3_JDATA_Pos (0U)
+#define ADC_JDR3_JDATA_Msk (0xFFFFU << ADC_JDR3_JDATA_Pos) /*!< 0x0000FFFF */
+#define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!< ADC group injected sequencer rank 3 conversion data */
+
+/******************* Bit definition for ADC_JDR4 register *******************/
+#define ADC_JDR4_JDATA_Pos (0U)
+#define ADC_JDR4_JDATA_Msk (0xFFFFU << ADC_JDR4_JDATA_Pos) /*!< 0x0000FFFF */
+#define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!< ADC group injected sequencer rank 4 conversion data */
+
+/******************** Bit definition for ADC_DR register ********************/
+#define ADC_DR_DATA_Pos (0U)
+#define ADC_DR_DATA_Msk (0xFFFFU << ADC_DR_DATA_Pos) /*!< 0x0000FFFF */
+#define ADC_DR_DATA ADC_DR_DATA_Msk /*!< ADC group regular conversion data */
+#define ADC_DR_ADC2DATA_Pos (16U)
+#define ADC_DR_ADC2DATA_Msk (0xFFFFU << ADC_DR_ADC2DATA_Pos) /*!< 0xFFFF0000 */
+#define ADC_DR_ADC2DATA ADC_DR_ADC2DATA_Msk /*!< ADC group regular conversion data for ADC slave, in multimode */
+/******************************************************************************/
+/* */
+/* Digital to Analog Converter */
+/* */
+/******************************************************************************/
+
+/******************** Bit definition for DAC_CR register ********************/
+#define DAC_CR_EN1_Pos (0U)
+#define DAC_CR_EN1_Msk (0x1U << DAC_CR_EN1_Pos) /*!< 0x00000001 */
+#define DAC_CR_EN1 DAC_CR_EN1_Msk /*!< DAC channel1 enable */
+#define DAC_CR_BOFF1_Pos (1U)
+#define DAC_CR_BOFF1_Msk (0x1U << DAC_CR_BOFF1_Pos) /*!< 0x00000002 */
+#define DAC_CR_BOFF1 DAC_CR_BOFF1_Msk /*!< DAC channel1 output buffer disable */
+#define DAC_CR_TEN1_Pos (2U)
+#define DAC_CR_TEN1_Msk (0x1U << DAC_CR_TEN1_Pos) /*!< 0x00000004 */
+#define DAC_CR_TEN1 DAC_CR_TEN1_Msk /*!< DAC channel1 Trigger enable */
+
+#define DAC_CR_TSEL1_Pos (3U)
+#define DAC_CR_TSEL1_Msk (0x7U << DAC_CR_TSEL1_Pos) /*!< 0x00000038 */
+#define DAC_CR_TSEL1 DAC_CR_TSEL1_Msk /*!< TSEL1[2:0] (DAC channel1 Trigger selection) */
+#define DAC_CR_TSEL1_0 (0x1U << DAC_CR_TSEL1_Pos) /*!< 0x00000008 */
+#define DAC_CR_TSEL1_1 (0x2U << DAC_CR_TSEL1_Pos) /*!< 0x00000010 */
+#define DAC_CR_TSEL1_2 (0x4U << DAC_CR_TSEL1_Pos) /*!< 0x00000020 */
+
+#define DAC_CR_WAVE1_Pos (6U)
+#define DAC_CR_WAVE1_Msk (0x3U << DAC_CR_WAVE1_Pos) /*!< 0x000000C0 */
+#define DAC_CR_WAVE1 DAC_CR_WAVE1_Msk /*!< WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
+#define DAC_CR_WAVE1_0 (0x1U << DAC_CR_WAVE1_Pos) /*!< 0x00000040 */
+#define DAC_CR_WAVE1_1 (0x2U << DAC_CR_WAVE1_Pos) /*!< 0x00000080 */
+
+#define DAC_CR_MAMP1_Pos (8U)
+#define DAC_CR_MAMP1_Msk (0xFU << DAC_CR_MAMP1_Pos) /*!< 0x00000F00 */
+#define DAC_CR_MAMP1 DAC_CR_MAMP1_Msk /*!< MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
+#define DAC_CR_MAMP1_0 (0x1U << DAC_CR_MAMP1_Pos) /*!< 0x00000100 */
+#define DAC_CR_MAMP1_1 (0x2U << DAC_CR_MAMP1_Pos) /*!< 0x00000200 */
+#define DAC_CR_MAMP1_2 (0x4U << DAC_CR_MAMP1_Pos) /*!< 0x00000400 */
+#define DAC_CR_MAMP1_3 (0x8U << DAC_CR_MAMP1_Pos) /*!< 0x00000800 */
+
+#define DAC_CR_DMAEN1_Pos (12U)
+#define DAC_CR_DMAEN1_Msk (0x1U << DAC_CR_DMAEN1_Pos) /*!< 0x00001000 */
+#define DAC_CR_DMAEN1 DAC_CR_DMAEN1_Msk /*!< DAC channel1 DMA enable */
+#define DAC_CR_EN2_Pos (16U)
+#define DAC_CR_EN2_Msk (0x1U << DAC_CR_EN2_Pos) /*!< 0x00010000 */
+#define DAC_CR_EN2 DAC_CR_EN2_Msk /*!< DAC channel2 enable */
+#define DAC_CR_BOFF2_Pos (17U)
+#define DAC_CR_BOFF2_Msk (0x1U << DAC_CR_BOFF2_Pos) /*!< 0x00020000 */
+#define DAC_CR_BOFF2 DAC_CR_BOFF2_Msk /*!< DAC channel2 output buffer disable */
+#define DAC_CR_TEN2_Pos (18U)
+#define DAC_CR_TEN2_Msk (0x1U << DAC_CR_TEN2_Pos) /*!< 0x00040000 */
+#define DAC_CR_TEN2 DAC_CR_TEN2_Msk /*!< DAC channel2 Trigger enable */
+
+#define DAC_CR_TSEL2_Pos (19U)
+#define DAC_CR_TSEL2_Msk (0x7U << DAC_CR_TSEL2_Pos) /*!< 0x00380000 */
+#define DAC_CR_TSEL2 DAC_CR_TSEL2_Msk /*!< TSEL2[2:0] (DAC channel2 Trigger selection) */
+#define DAC_CR_TSEL2_0 (0x1U << DAC_CR_TSEL2_Pos) /*!< 0x00080000 */
+#define DAC_CR_TSEL2_1 (0x2U << DAC_CR_TSEL2_Pos) /*!< 0x00100000 */
+#define DAC_CR_TSEL2_2 (0x4U << DAC_CR_TSEL2_Pos) /*!< 0x00200000 */
+
+#define DAC_CR_WAVE2_Pos (22U)
+#define DAC_CR_WAVE2_Msk (0x3U << DAC_CR_WAVE2_Pos) /*!< 0x00C00000 */
+#define DAC_CR_WAVE2 DAC_CR_WAVE2_Msk /*!< WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
+#define DAC_CR_WAVE2_0 (0x1U << DAC_CR_WAVE2_Pos) /*!< 0x00400000 */
+#define DAC_CR_WAVE2_1 (0x2U << DAC_CR_WAVE2_Pos) /*!< 0x00800000 */
+
+#define DAC_CR_MAMP2_Pos (24U)
+#define DAC_CR_MAMP2_Msk (0xFU << DAC_CR_MAMP2_Pos) /*!< 0x0F000000 */
+#define DAC_CR_MAMP2 DAC_CR_MAMP2_Msk /*!< MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
+#define DAC_CR_MAMP2_0 (0x1U << DAC_CR_MAMP2_Pos) /*!< 0x01000000 */
+#define DAC_CR_MAMP2_1 (0x2U << DAC_CR_MAMP2_Pos) /*!< 0x02000000 */
+#define DAC_CR_MAMP2_2 (0x4U << DAC_CR_MAMP2_Pos) /*!< 0x04000000 */
+#define DAC_CR_MAMP2_3 (0x8U << DAC_CR_MAMP2_Pos) /*!< 0x08000000 */
+
+#define DAC_CR_DMAEN2_Pos (28U)
+#define DAC_CR_DMAEN2_Msk (0x1U << DAC_CR_DMAEN2_Pos) /*!< 0x10000000 */
+#define DAC_CR_DMAEN2 DAC_CR_DMAEN2_Msk /*!< DAC channel2 DMA enabled */
+
+
+/***************** Bit definition for DAC_SWTRIGR register ******************/
+#define DAC_SWTRIGR_SWTRIG1_Pos (0U)
+#define DAC_SWTRIGR_SWTRIG1_Msk (0x1U << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */
+#define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /*!< DAC channel1 software trigger */
+#define DAC_SWTRIGR_SWTRIG2_Pos (1U)
+#define DAC_SWTRIGR_SWTRIG2_Msk (0x1U << DAC_SWTRIGR_SWTRIG2_Pos) /*!< 0x00000002 */
+#define DAC_SWTRIGR_SWTRIG2 DAC_SWTRIGR_SWTRIG2_Msk /*!< DAC channel2 software trigger */
+
+/***************** Bit definition for DAC_DHR12R1 register ******************/
+#define DAC_DHR12R1_DACC1DHR_Pos (0U)
+#define DAC_DHR12R1_DACC1DHR_Msk (0xFFFU << DAC_DHR12R1_DACC1DHR_Pos) /*!< 0x00000FFF */
+#define DAC_DHR12R1_DACC1DHR DAC_DHR12R1_DACC1DHR_Msk /*!< DAC channel1 12-bit Right aligned data */
+
+/***************** Bit definition for DAC_DHR12L1 register ******************/
+#define DAC_DHR12L1_DACC1DHR_Pos (4U)
+#define DAC_DHR12L1_DACC1DHR_Msk (0xFFFU << DAC_DHR12L1_DACC1DHR_Pos) /*!< 0x0000FFF0 */
+#define DAC_DHR12L1_DACC1DHR DAC_DHR12L1_DACC1DHR_Msk /*!< DAC channel1 12-bit Left aligned data */
+
+/****************** Bit definition for DAC_DHR8R1 register ******************/
+#define DAC_DHR8R1_DACC1DHR_Pos (0U)
+#define DAC_DHR8R1_DACC1DHR_Msk (0xFFU << DAC_DHR8R1_DACC1DHR_Pos) /*!< 0x000000FF */
+#define DAC_DHR8R1_DACC1DHR DAC_DHR8R1_DACC1DHR_Msk /*!< DAC channel1 8-bit Right aligned data */
+
+/***************** Bit definition for DAC_DHR12R2 register ******************/
+#define DAC_DHR12R2_DACC2DHR_Pos (0U)
+#define DAC_DHR12R2_DACC2DHR_Msk (0xFFFU << DAC_DHR12R2_DACC2DHR_Pos) /*!< 0x00000FFF */
+#define DAC_DHR12R2_DACC2DHR DAC_DHR12R2_DACC2DHR_Msk /*!< DAC channel2 12-bit Right aligned data */
+
+/***************** Bit definition for DAC_DHR12L2 register ******************/
+#define DAC_DHR12L2_DACC2DHR_Pos (4U)
+#define DAC_DHR12L2_DACC2DHR_Msk (0xFFFU << DAC_DHR12L2_DACC2DHR_Pos) /*!< 0x0000FFF0 */
+#define DAC_DHR12L2_DACC2DHR DAC_DHR12L2_DACC2DHR_Msk /*!< DAC channel2 12-bit Left aligned data */
+
+/****************** Bit definition for DAC_DHR8R2 register ******************/
+#define DAC_DHR8R2_DACC2DHR_Pos (0U)
+#define DAC_DHR8R2_DACC2DHR_Msk (0xFFU << DAC_DHR8R2_DACC2DHR_Pos) /*!< 0x000000FF */
+#define DAC_DHR8R2_DACC2DHR DAC_DHR8R2_DACC2DHR_Msk /*!< DAC channel2 8-bit Right aligned data */
+
+/***************** Bit definition for DAC_DHR12RD register ******************/
+#define DAC_DHR12RD_DACC1DHR_Pos (0U)
+#define DAC_DHR12RD_DACC1DHR_Msk (0xFFFU << DAC_DHR12RD_DACC1DHR_Pos) /*!< 0x00000FFF */
+#define DAC_DHR12RD_DACC1DHR DAC_DHR12RD_DACC1DHR_Msk /*!< DAC channel1 12-bit Right aligned data */
+#define DAC_DHR12RD_DACC2DHR_Pos (16U)
+#define DAC_DHR12RD_DACC2DHR_Msk (0xFFFU << DAC_DHR12RD_DACC2DHR_Pos) /*!< 0x0FFF0000 */
+#define DAC_DHR12RD_DACC2DHR DAC_DHR12RD_DACC2DHR_Msk /*!< DAC channel2 12-bit Right aligned data */
+
+/***************** Bit definition for DAC_DHR12LD register ******************/
+#define DAC_DHR12LD_DACC1DHR_Pos (4U)
+#define DAC_DHR12LD_DACC1DHR_Msk (0xFFFU << DAC_DHR12LD_DACC1DHR_Pos) /*!< 0x0000FFF0 */
+#define DAC_DHR12LD_DACC1DHR DAC_DHR12LD_DACC1DHR_Msk /*!< DAC channel1 12-bit Left aligned data */
+#define DAC_DHR12LD_DACC2DHR_Pos (20U)
+#define DAC_DHR12LD_DACC2DHR_Msk (0xFFFU << DAC_DHR12LD_DACC2DHR_Pos) /*!< 0xFFF00000 */
+#define DAC_DHR12LD_DACC2DHR DAC_DHR12LD_DACC2DHR_Msk /*!< DAC channel2 12-bit Left aligned data */
+
+/****************** Bit definition for DAC_DHR8RD register ******************/
+#define DAC_DHR8RD_DACC1DHR_Pos (0U)
+#define DAC_DHR8RD_DACC1DHR_Msk (0xFFU << DAC_DHR8RD_DACC1DHR_Pos) /*!< 0x000000FF */
+#define DAC_DHR8RD_DACC1DHR DAC_DHR8RD_DACC1DHR_Msk /*!< DAC channel1 8-bit Right aligned data */
+#define DAC_DHR8RD_DACC2DHR_Pos (8U)
+#define DAC_DHR8RD_DACC2DHR_Msk (0xFFU << DAC_DHR8RD_DACC2DHR_Pos) /*!< 0x0000FF00 */
+#define DAC_DHR8RD_DACC2DHR DAC_DHR8RD_DACC2DHR_Msk /*!< DAC channel2 8-bit Right aligned data */
+
+/******************* Bit definition for DAC_DOR1 register *******************/
+#define DAC_DOR1_DACC1DOR_Pos (0U)
+#define DAC_DOR1_DACC1DOR_Msk (0xFFFU << DAC_DOR1_DACC1DOR_Pos) /*!< 0x00000FFF */
+#define DAC_DOR1_DACC1DOR DAC_DOR1_DACC1DOR_Msk /*!< DAC channel1 data output */
+
+/******************* Bit definition for DAC_DOR2 register *******************/
+#define DAC_DOR2_DACC2DOR_Pos (0U)
+#define DAC_DOR2_DACC2DOR_Msk (0xFFFU << DAC_DOR2_DACC2DOR_Pos) /*!< 0x00000FFF */
+#define DAC_DOR2_DACC2DOR DAC_DOR2_DACC2DOR_Msk /*!< DAC channel2 data output */
+
+
+
+/*****************************************************************************/
+/* */
+/* Timers (TIM) */
+/* */
+/*****************************************************************************/
+/******************* Bit definition for TIM_CR1 register *******************/
+#define TIM_CR1_CEN_Pos (0U)
+#define TIM_CR1_CEN_Msk (0x1U << TIM_CR1_CEN_Pos) /*!< 0x00000001 */
+#define TIM_CR1_CEN TIM_CR1_CEN_Msk /*!<Counter enable */
+#define TIM_CR1_UDIS_Pos (1U)
+#define TIM_CR1_UDIS_Msk (0x1U << TIM_CR1_UDIS_Pos) /*!< 0x00000002 */
+#define TIM_CR1_UDIS TIM_CR1_UDIS_Msk /*!<Update disable */
+#define TIM_CR1_URS_Pos (2U)
+#define TIM_CR1_URS_Msk (0x1U << TIM_CR1_URS_Pos) /*!< 0x00000004 */
+#define TIM_CR1_URS TIM_CR1_URS_Msk /*!<Update request source */
+#define TIM_CR1_OPM_Pos (3U)
+#define TIM_CR1_OPM_Msk (0x1U << TIM_CR1_OPM_Pos) /*!< 0x00000008 */
+#define TIM_CR1_OPM TIM_CR1_OPM_Msk /*!<One pulse mode */
+#define TIM_CR1_DIR_Pos (4U)
+#define TIM_CR1_DIR_Msk (0x1U << TIM_CR1_DIR_Pos) /*!< 0x00000010 */
+#define TIM_CR1_DIR TIM_CR1_DIR_Msk /*!<Direction */
+
+#define TIM_CR1_CMS_Pos (5U)
+#define TIM_CR1_CMS_Msk (0x3U << TIM_CR1_CMS_Pos) /*!< 0x00000060 */
+#define TIM_CR1_CMS TIM_CR1_CMS_Msk /*!<CMS[1:0] bits (Center-aligned mode selection) */
+#define TIM_CR1_CMS_0 (0x1U << TIM_CR1_CMS_Pos) /*!< 0x00000020 */
+#define TIM_CR1_CMS_1 (0x2U << TIM_CR1_CMS_Pos) /*!< 0x00000040 */
+
+#define TIM_CR1_ARPE_Pos (7U)
+#define TIM_CR1_ARPE_Msk (0x1U << TIM_CR1_ARPE_Pos) /*!< 0x00000080 */
+#define TIM_CR1_ARPE TIM_CR1_ARPE_Msk /*!<Auto-reload preload enable */
+
+#define TIM_CR1_CKD_Pos (8U)
+#define TIM_CR1_CKD_Msk (0x3U << TIM_CR1_CKD_Pos) /*!< 0x00000300 */
+#define TIM_CR1_CKD TIM_CR1_CKD_Msk /*!<CKD[1:0] bits (clock division) */
+#define TIM_CR1_CKD_0 (0x1U << TIM_CR1_CKD_Pos) /*!< 0x00000100 */
+#define TIM_CR1_CKD_1 (0x2U << TIM_CR1_CKD_Pos) /*!< 0x00000200 */
+
+/******************* Bit definition for TIM_CR2 register *******************/
+#define TIM_CR2_CCPC_Pos (0U)
+#define TIM_CR2_CCPC_Msk (0x1U << TIM_CR2_CCPC_Pos) /*!< 0x00000001 */
+#define TIM_CR2_CCPC TIM_CR2_CCPC_Msk /*!<Capture/Compare Preloaded Control */
+#define TIM_CR2_CCUS_Pos (2U)
+#define TIM_CR2_CCUS_Msk (0x1U << TIM_CR2_CCUS_Pos) /*!< 0x00000004 */
+#define TIM_CR2_CCUS TIM_CR2_CCUS_Msk /*!<Capture/Compare Control Update Selection */
+#define TIM_CR2_CCDS_Pos (3U)
+#define TIM_CR2_CCDS_Msk (0x1U << TIM_CR2_CCDS_Pos) /*!< 0x00000008 */
+#define TIM_CR2_CCDS TIM_CR2_CCDS_Msk /*!<Capture/Compare DMA Selection */
+
+#define TIM_CR2_MMS_Pos (4U)
+#define TIM_CR2_MMS_Msk (0x7U << TIM_CR2_MMS_Pos) /*!< 0x00000070 */
+#define TIM_CR2_MMS TIM_CR2_MMS_Msk /*!<MMS[2:0] bits (Master Mode Selection) */
+#define TIM_CR2_MMS_0 (0x1U << TIM_CR2_MMS_Pos) /*!< 0x00000010 */
+#define TIM_CR2_MMS_1 (0x2U << TIM_CR2_MMS_Pos) /*!< 0x00000020 */
+#define TIM_CR2_MMS_2 (0x4U << TIM_CR2_MMS_Pos) /*!< 0x00000040 */
+
+#define TIM_CR2_TI1S_Pos (7U)
+#define TIM_CR2_TI1S_Msk (0x1U << TIM_CR2_TI1S_Pos) /*!< 0x00000080 */
+#define TIM_CR2_TI1S TIM_CR2_TI1S_Msk /*!<TI1 Selection */
+#define TIM_CR2_OIS1_Pos (8U)
+#define TIM_CR2_OIS1_Msk (0x1U << TIM_CR2_OIS1_Pos) /*!< 0x00000100 */
+#define TIM_CR2_OIS1 TIM_CR2_OIS1_Msk /*!<Output Idle state 1 (OC1 output) */
+#define TIM_CR2_OIS1N_Pos (9U)
+#define TIM_CR2_OIS1N_Msk (0x1U << TIM_CR2_OIS1N_Pos) /*!< 0x00000200 */
+#define TIM_CR2_OIS1N TIM_CR2_OIS1N_Msk /*!<Output Idle state 1 (OC1N output) */
+#define TIM_CR2_OIS2_Pos (10U)
+#define TIM_CR2_OIS2_Msk (0x1U << TIM_CR2_OIS2_Pos) /*!< 0x00000400 */
+#define TIM_CR2_OIS2 TIM_CR2_OIS2_Msk /*!<Output Idle state 2 (OC2 output) */
+#define TIM_CR2_OIS2N_Pos (11U)
+#define TIM_CR2_OIS2N_Msk (0x1U << TIM_CR2_OIS2N_Pos) /*!< 0x00000800 */
+#define TIM_CR2_OIS2N TIM_CR2_OIS2N_Msk /*!<Output Idle state 2 (OC2N output) */
+#define TIM_CR2_OIS3_Pos (12U)
+#define TIM_CR2_OIS3_Msk (0x1U << TIM_CR2_OIS3_Pos) /*!< 0x00001000 */
+#define TIM_CR2_OIS3 TIM_CR2_OIS3_Msk /*!<Output Idle state 3 (OC3 output) */
+#define TIM_CR2_OIS3N_Pos (13U)
+#define TIM_CR2_OIS3N_Msk (0x1U << TIM_CR2_OIS3N_Pos) /*!< 0x00002000 */
+#define TIM_CR2_OIS3N TIM_CR2_OIS3N_Msk /*!<Output Idle state 3 (OC3N output) */
+#define TIM_CR2_OIS4_Pos (14U)
+#define TIM_CR2_OIS4_Msk (0x1U << TIM_CR2_OIS4_Pos) /*!< 0x00004000 */
+#define TIM_CR2_OIS4 TIM_CR2_OIS4_Msk /*!<Output Idle state 4 (OC4 output) */
+
+/******************* Bit definition for TIM_SMCR register ******************/
+#define TIM_SMCR_SMS_Pos (0U)
+#define TIM_SMCR_SMS_Msk (0x7U << TIM_SMCR_SMS_Pos) /*!< 0x00000007 */
+#define TIM_SMCR_SMS TIM_SMCR_SMS_Msk /*!<SMS[2:0] bits (Slave mode selection) */
+#define TIM_SMCR_SMS_0 (0x1U << TIM_SMCR_SMS_Pos) /*!< 0x00000001 */
+#define TIM_SMCR_SMS_1 (0x2U << TIM_SMCR_SMS_Pos) /*!< 0x00000002 */
+#define TIM_SMCR_SMS_2 (0x4U << TIM_SMCR_SMS_Pos) /*!< 0x00000004 */
+
+#define TIM_SMCR_OCCS_Pos (3U)
+#define TIM_SMCR_OCCS_Msk (0x1U << TIM_SMCR_OCCS_Pos) /*!< 0x00000008 */
+#define TIM_SMCR_OCCS TIM_SMCR_OCCS_Msk /*!< OCREF clear selection */
+
+#define TIM_SMCR_TS_Pos (4U)
+#define TIM_SMCR_TS_Msk (0x7U << TIM_SMCR_TS_Pos) /*!< 0x00000070 */
+#define TIM_SMCR_TS TIM_SMCR_TS_Msk /*!<TS[2:0] bits (Trigger selection) */
+#define TIM_SMCR_TS_0 (0x1U << TIM_SMCR_TS_Pos) /*!< 0x00000010 */
+#define TIM_SMCR_TS_1 (0x2U << TIM_SMCR_TS_Pos) /*!< 0x00000020 */
+#define TIM_SMCR_TS_2 (0x4U << TIM_SMCR_TS_Pos) /*!< 0x00000040 */
+
+#define TIM_SMCR_MSM_Pos (7U)
+#define TIM_SMCR_MSM_Msk (0x1U << TIM_SMCR_MSM_Pos) /*!< 0x00000080 */
+#define TIM_SMCR_MSM TIM_SMCR_MSM_Msk /*!<Master/slave mode */
+
+#define TIM_SMCR_ETF_Pos (8U)
+#define TIM_SMCR_ETF_Msk (0xFU << TIM_SMCR_ETF_Pos) /*!< 0x00000F00 */
+#define TIM_SMCR_ETF TIM_SMCR_ETF_Msk /*!<ETF[3:0] bits (External trigger filter) */
+#define TIM_SMCR_ETF_0 (0x1U << TIM_SMCR_ETF_Pos) /*!< 0x00000100 */
+#define TIM_SMCR_ETF_1 (0x2U << TIM_SMCR_ETF_Pos) /*!< 0x00000200 */
+#define TIM_SMCR_ETF_2 (0x4U << TIM_SMCR_ETF_Pos) /*!< 0x00000400 */
+#define TIM_SMCR_ETF_3 (0x8U << TIM_SMCR_ETF_Pos) /*!< 0x00000800 */
+
+#define TIM_SMCR_ETPS_Pos (12U)
+#define TIM_SMCR_ETPS_Msk (0x3U << TIM_SMCR_ETPS_Pos) /*!< 0x00003000 */
+#define TIM_SMCR_ETPS TIM_SMCR_ETPS_Msk /*!<ETPS[1:0] bits (External trigger prescaler) */
+#define TIM_SMCR_ETPS_0 (0x1U << TIM_SMCR_ETPS_Pos) /*!< 0x00001000 */
+#define TIM_SMCR_ETPS_1 (0x2U << TIM_SMCR_ETPS_Pos) /*!< 0x00002000 */
+
+#define TIM_SMCR_ECE_Pos (14U)
+#define TIM_SMCR_ECE_Msk (0x1U << TIM_SMCR_ECE_Pos) /*!< 0x00004000 */
+#define TIM_SMCR_ECE TIM_SMCR_ECE_Msk /*!<External clock enable */
+#define TIM_SMCR_ETP_Pos (15U)
+#define TIM_SMCR_ETP_Msk (0x1U << TIM_SMCR_ETP_Pos) /*!< 0x00008000 */
+#define TIM_SMCR_ETP TIM_SMCR_ETP_Msk /*!<External trigger polarity */
+
+/******************* Bit definition for TIM_DIER register ******************/
+#define TIM_DIER_UIE_Pos (0U)
+#define TIM_DIER_UIE_Msk (0x1U << TIM_DIER_UIE_Pos) /*!< 0x00000001 */
+#define TIM_DIER_UIE TIM_DIER_UIE_Msk /*!<Update interrupt enable */
+#define TIM_DIER_CC1IE_Pos (1U)
+#define TIM_DIER_CC1IE_Msk (0x1U << TIM_DIER_CC1IE_Pos) /*!< 0x00000002 */
+#define TIM_DIER_CC1IE TIM_DIER_CC1IE_Msk /*!<Capture/Compare 1 interrupt enable */
+#define TIM_DIER_CC2IE_Pos (2U)
+#define TIM_DIER_CC2IE_Msk (0x1U << TIM_DIER_CC2IE_Pos) /*!< 0x00000004 */
+#define TIM_DIER_CC2IE TIM_DIER_CC2IE_Msk /*!<Capture/Compare 2 interrupt enable */
+#define TIM_DIER_CC3IE_Pos (3U)
+#define TIM_DIER_CC3IE_Msk (0x1U << TIM_DIER_CC3IE_Pos) /*!< 0x00000008 */
+#define TIM_DIER_CC3IE TIM_DIER_CC3IE_Msk /*!<Capture/Compare 3 interrupt enable */
+#define TIM_DIER_CC4IE_Pos (4U)
+#define TIM_DIER_CC4IE_Msk (0x1U << TIM_DIER_CC4IE_Pos) /*!< 0x00000010 */
+#define TIM_DIER_CC4IE TIM_DIER_CC4IE_Msk /*!<Capture/Compare 4 interrupt enable */
+#define TIM_DIER_COMIE_Pos (5U)
+#define TIM_DIER_COMIE_Msk (0x1U << TIM_DIER_COMIE_Pos) /*!< 0x00000020 */
+#define TIM_DIER_COMIE TIM_DIER_COMIE_Msk /*!<COM interrupt enable */
+#define TIM_DIER_TIE_Pos (6U)
+#define TIM_DIER_TIE_Msk (0x1U << TIM_DIER_TIE_Pos) /*!< 0x00000040 */
+#define TIM_DIER_TIE TIM_DIER_TIE_Msk /*!<Trigger interrupt enable */
+#define TIM_DIER_BIE_Pos (7U)
+#define TIM_DIER_BIE_Msk (0x1U << TIM_DIER_BIE_Pos) /*!< 0x00000080 */
+#define TIM_DIER_BIE TIM_DIER_BIE_Msk /*!<Break interrupt enable */
+#define TIM_DIER_UDE_Pos (8U)
+#define TIM_DIER_UDE_Msk (0x1U << TIM_DIER_UDE_Pos) /*!< 0x00000100 */
+#define TIM_DIER_UDE TIM_DIER_UDE_Msk /*!<Update DMA request enable */
+#define TIM_DIER_CC1DE_Pos (9U)
+#define TIM_DIER_CC1DE_Msk (0x1U << TIM_DIER_CC1DE_Pos) /*!< 0x00000200 */
+#define TIM_DIER_CC1DE TIM_DIER_CC1DE_Msk /*!<Capture/Compare 1 DMA request enable */
+#define TIM_DIER_CC2DE_Pos (10U)
+#define TIM_DIER_CC2DE_Msk (0x1U << TIM_DIER_CC2DE_Pos) /*!< 0x00000400 */
+#define TIM_DIER_CC2DE TIM_DIER_CC2DE_Msk /*!<Capture/Compare 2 DMA request enable */
+#define TIM_DIER_CC3DE_Pos (11U)
+#define TIM_DIER_CC3DE_Msk (0x1U << TIM_DIER_CC3DE_Pos) /*!< 0x00000800 */
+#define TIM_DIER_CC3DE TIM_DIER_CC3DE_Msk /*!<Capture/Compare 3 DMA request enable */
+#define TIM_DIER_CC4DE_Pos (12U)
+#define TIM_DIER_CC4DE_Msk (0x1U << TIM_DIER_CC4DE_Pos) /*!< 0x00001000 */
+#define TIM_DIER_CC4DE TIM_DIER_CC4DE_Msk /*!<Capture/Compare 4 DMA request enable */
+#define TIM_DIER_COMDE_Pos (13U)
+#define TIM_DIER_COMDE_Msk (0x1U << TIM_DIER_COMDE_Pos) /*!< 0x00002000 */
+#define TIM_DIER_COMDE TIM_DIER_COMDE_Msk /*!<COM DMA request enable */
+#define TIM_DIER_TDE_Pos (14U)
+#define TIM_DIER_TDE_Msk (0x1U << TIM_DIER_TDE_Pos) /*!< 0x00004000 */
+#define TIM_DIER_TDE TIM_DIER_TDE_Msk /*!<Trigger DMA request enable */
+
+/******************** Bit definition for TIM_SR register *******************/
+#define TIM_SR_UIF_Pos (0U)
+#define TIM_SR_UIF_Msk (0x1U << TIM_SR_UIF_Pos) /*!< 0x00000001 */
+#define TIM_SR_UIF TIM_SR_UIF_Msk /*!<Update interrupt Flag */
+#define TIM_SR_CC1IF_Pos (1U)
+#define TIM_SR_CC1IF_Msk (0x1U << TIM_SR_CC1IF_Pos) /*!< 0x00000002 */
+#define TIM_SR_CC1IF TIM_SR_CC1IF_Msk /*!<Capture/Compare 1 interrupt Flag */
+#define TIM_SR_CC2IF_Pos (2U)
+#define TIM_SR_CC2IF_Msk (0x1U << TIM_SR_CC2IF_Pos) /*!< 0x00000004 */
+#define TIM_SR_CC2IF TIM_SR_CC2IF_Msk /*!<Capture/Compare 2 interrupt Flag */
+#define TIM_SR_CC3IF_Pos (3U)
+#define TIM_SR_CC3IF_Msk (0x1U << TIM_SR_CC3IF_Pos) /*!< 0x00000008 */
+#define TIM_SR_CC3IF TIM_SR_CC3IF_Msk /*!<Capture/Compare 3 interrupt Flag */
+#define TIM_SR_CC4IF_Pos (4U)
+#define TIM_SR_CC4IF_Msk (0x1U << TIM_SR_CC4IF_Pos) /*!< 0x00000010 */
+#define TIM_SR_CC4IF TIM_SR_CC4IF_Msk /*!<Capture/Compare 4 interrupt Flag */
+#define TIM_SR_COMIF_Pos (5U)
+#define TIM_SR_COMIF_Msk (0x1U << TIM_SR_COMIF_Pos) /*!< 0x00000020 */
+#define TIM_SR_COMIF TIM_SR_COMIF_Msk /*!<COM interrupt Flag */
+#define TIM_SR_TIF_Pos (6U)
+#define TIM_SR_TIF_Msk (0x1U << TIM_SR_TIF_Pos) /*!< 0x00000040 */
+#define TIM_SR_TIF TIM_SR_TIF_Msk /*!<Trigger interrupt Flag */
+#define TIM_SR_BIF_Pos (7U)
+#define TIM_SR_BIF_Msk (0x1U << TIM_SR_BIF_Pos) /*!< 0x00000080 */
+#define TIM_SR_BIF TIM_SR_BIF_Msk /*!<Break interrupt Flag */
+#define TIM_SR_CC1OF_Pos (9U)
+#define TIM_SR_CC1OF_Msk (0x1U << TIM_SR_CC1OF_Pos) /*!< 0x00000200 */
+#define TIM_SR_CC1OF TIM_SR_CC1OF_Msk /*!<Capture/Compare 1 Overcapture Flag */
+#define TIM_SR_CC2OF_Pos (10U)
+#define TIM_SR_CC2OF_Msk (0x1U << TIM_SR_CC2OF_Pos) /*!< 0x00000400 */
+#define TIM_SR_CC2OF TIM_SR_CC2OF_Msk /*!<Capture/Compare 2 Overcapture Flag */
+#define TIM_SR_CC3OF_Pos (11U)
+#define TIM_SR_CC3OF_Msk (0x1U << TIM_SR_CC3OF_Pos) /*!< 0x00000800 */
+#define TIM_SR_CC3OF TIM_SR_CC3OF_Msk /*!<Capture/Compare 3 Overcapture Flag */
+#define TIM_SR_CC4OF_Pos (12U)
+#define TIM_SR_CC4OF_Msk (0x1U << TIM_SR_CC4OF_Pos) /*!< 0x00001000 */
+#define TIM_SR_CC4OF TIM_SR_CC4OF_Msk /*!<Capture/Compare 4 Overcapture Flag */
+
+/******************* Bit definition for TIM_EGR register *******************/
+#define TIM_EGR_UG_Pos (0U)
+#define TIM_EGR_UG_Msk (0x1U << TIM_EGR_UG_Pos) /*!< 0x00000001 */
+#define TIM_EGR_UG TIM_EGR_UG_Msk /*!<Update Generation */
+#define TIM_EGR_CC1G_Pos (1U)
+#define TIM_EGR_CC1G_Msk (0x1U << TIM_EGR_CC1G_Pos) /*!< 0x00000002 */
+#define TIM_EGR_CC1G TIM_EGR_CC1G_Msk /*!<Capture/Compare 1 Generation */
+#define TIM_EGR_CC2G_Pos (2U)
+#define TIM_EGR_CC2G_Msk (0x1U << TIM_EGR_CC2G_Pos) /*!< 0x00000004 */
+#define TIM_EGR_CC2G TIM_EGR_CC2G_Msk /*!<Capture/Compare 2 Generation */
+#define TIM_EGR_CC3G_Pos (3U)
+#define TIM_EGR_CC3G_Msk (0x1U << TIM_EGR_CC3G_Pos) /*!< 0x00000008 */
+#define TIM_EGR_CC3G TIM_EGR_CC3G_Msk /*!<Capture/Compare 3 Generation */
+#define TIM_EGR_CC4G_Pos (4U)
+#define TIM_EGR_CC4G_Msk (0x1U << TIM_EGR_CC4G_Pos) /*!< 0x00000010 */
+#define TIM_EGR_CC4G TIM_EGR_CC4G_Msk /*!<Capture/Compare 4 Generation */
+#define TIM_EGR_COMG_Pos (5U)
+#define TIM_EGR_COMG_Msk (0x1U << TIM_EGR_COMG_Pos) /*!< 0x00000020 */
+#define TIM_EGR_COMG TIM_EGR_COMG_Msk /*!<Capture/Compare Control Update Generation */
+#define TIM_EGR_TG_Pos (6U)
+#define TIM_EGR_TG_Msk (0x1U << TIM_EGR_TG_Pos) /*!< 0x00000040 */
+#define TIM_EGR_TG TIM_EGR_TG_Msk /*!<Trigger Generation */
+#define TIM_EGR_BG_Pos (7U)
+#define TIM_EGR_BG_Msk (0x1U << TIM_EGR_BG_Pos) /*!< 0x00000080 */
+#define TIM_EGR_BG TIM_EGR_BG_Msk /*!<Break Generation */
+
+/****************** Bit definition for TIM_CCMR1 register ******************/
+#define TIM_CCMR1_CC1S_Pos (0U)
+#define TIM_CCMR1_CC1S_Msk (0x3U << TIM_CCMR1_CC1S_Pos) /*!< 0x00000003 */
+#define TIM_CCMR1_CC1S TIM_CCMR1_CC1S_Msk /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
+#define TIM_CCMR1_CC1S_0 (0x1U << TIM_CCMR1_CC1S_Pos) /*!< 0x00000001 */
+#define TIM_CCMR1_CC1S_1 (0x2U << TIM_CCMR1_CC1S_Pos) /*!< 0x00000002 */
+
+#define TIM_CCMR1_OC1FE_Pos (2U)
+#define TIM_CCMR1_OC1FE_Msk (0x1U << TIM_CCMR1_OC1FE_Pos) /*!< 0x00000004 */
+#define TIM_CCMR1_OC1FE TIM_CCMR1_OC1FE_Msk /*!<Output Compare 1 Fast enable */
+#define TIM_CCMR1_OC1PE_Pos (3U)
+#define TIM_CCMR1_OC1PE_Msk (0x1U << TIM_CCMR1_OC1PE_Pos) /*!< 0x00000008 */
+#define TIM_CCMR1_OC1PE TIM_CCMR1_OC1PE_Msk /*!<Output Compare 1 Preload enable */
+
+#define TIM_CCMR1_OC1M_Pos (4U)
+#define TIM_CCMR1_OC1M_Msk (0x7U << TIM_CCMR1_OC1M_Pos) /*!< 0x00000070 */
+#define TIM_CCMR1_OC1M TIM_CCMR1_OC1M_Msk /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
+#define TIM_CCMR1_OC1M_0 (0x1U << TIM_CCMR1_OC1M_Pos) /*!< 0x00000010 */
+#define TIM_CCMR1_OC1M_1 (0x2U << TIM_CCMR1_OC1M_Pos) /*!< 0x00000020 */
+#define TIM_CCMR1_OC1M_2 (0x4U << TIM_CCMR1_OC1M_Pos) /*!< 0x00000040 */
+
+#define TIM_CCMR1_OC1CE_Pos (7U)
+#define TIM_CCMR1_OC1CE_Msk (0x1U << TIM_CCMR1_OC1CE_Pos) /*!< 0x00000080 */
+#define TIM_CCMR1_OC1CE TIM_CCMR1_OC1CE_Msk /*!<Output Compare 1Clear Enable */
+
+#define TIM_CCMR1_CC2S_Pos (8U)
+#define TIM_CCMR1_CC2S_Msk (0x3U << TIM_CCMR1_CC2S_Pos) /*!< 0x00000300 */
+#define TIM_CCMR1_CC2S TIM_CCMR1_CC2S_Msk /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
+#define TIM_CCMR1_CC2S_0 (0x1U << TIM_CCMR1_CC2S_Pos) /*!< 0x00000100 */
+#define TIM_CCMR1_CC2S_1 (0x2U << TIM_CCMR1_CC2S_Pos) /*!< 0x00000200 */
+
+#define TIM_CCMR1_OC2FE_Pos (10U)
+#define TIM_CCMR1_OC2FE_Msk (0x1U << TIM_CCMR1_OC2FE_Pos) /*!< 0x00000400 */
+#define TIM_CCMR1_OC2FE TIM_CCMR1_OC2FE_Msk /*!<Output Compare 2 Fast enable */
+#define TIM_CCMR1_OC2PE_Pos (11U)
+#define TIM_CCMR1_OC2PE_Msk (0x1U << TIM_CCMR1_OC2PE_Pos) /*!< 0x00000800 */
+#define TIM_CCMR1_OC2PE TIM_CCMR1_OC2PE_Msk /*!<Output Compare 2 Preload enable */
+
+#define TIM_CCMR1_OC2M_Pos (12U)
+#define TIM_CCMR1_OC2M_Msk (0x7U << TIM_CCMR1_OC2M_Pos) /*!< 0x00007000 */
+#define TIM_CCMR1_OC2M TIM_CCMR1_OC2M_Msk /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
+#define TIM_CCMR1_OC2M_0 (0x1U << TIM_CCMR1_OC2M_Pos) /*!< 0x00001000 */
+#define TIM_CCMR1_OC2M_1 (0x2U << TIM_CCMR1_OC2M_Pos) /*!< 0x00002000 */
+#define TIM_CCMR1_OC2M_2 (0x4U << TIM_CCMR1_OC2M_Pos) /*!< 0x00004000 */
+
+#define TIM_CCMR1_OC2CE_Pos (15U)
+#define TIM_CCMR1_OC2CE_Msk (0x1U << TIM_CCMR1_OC2CE_Pos) /*!< 0x00008000 */
+#define TIM_CCMR1_OC2CE TIM_CCMR1_OC2CE_Msk /*!<Output Compare 2 Clear Enable */
+
+/*---------------------------------------------------------------------------*/
+
+#define TIM_CCMR1_IC1PSC_Pos (2U)
+#define TIM_CCMR1_IC1PSC_Msk (0x3U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x0000000C */
+#define TIM_CCMR1_IC1PSC TIM_CCMR1_IC1PSC_Msk /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
+#define TIM_CCMR1_IC1PSC_0 (0x1U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x00000004 */
+#define TIM_CCMR1_IC1PSC_1 (0x2U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x00000008 */
+
+#define TIM_CCMR1_IC1F_Pos (4U)
+#define TIM_CCMR1_IC1F_Msk (0xFU << TIM_CCMR1_IC1F_Pos) /*!< 0x000000F0 */
+#define TIM_CCMR1_IC1F TIM_CCMR1_IC1F_Msk /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
+#define TIM_CCMR1_IC1F_0 (0x1U << TIM_CCMR1_IC1F_Pos) /*!< 0x00000010 */
+#define TIM_CCMR1_IC1F_1 (0x2U << TIM_CCMR1_IC1F_Pos) /*!< 0x00000020 */
+#define TIM_CCMR1_IC1F_2 (0x4U << TIM_CCMR1_IC1F_Pos) /*!< 0x00000040 */
+#define TIM_CCMR1_IC1F_3 (0x8U << TIM_CCMR1_IC1F_Pos) /*!< 0x00000080 */
+
+#define TIM_CCMR1_IC2PSC_Pos (10U)
+#define TIM_CCMR1_IC2PSC_Msk (0x3U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000C00 */
+#define TIM_CCMR1_IC2PSC TIM_CCMR1_IC2PSC_Msk /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
+#define TIM_CCMR1_IC2PSC_0 (0x1U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000400 */
+#define TIM_CCMR1_IC2PSC_1 (0x2U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000800 */
+
+#define TIM_CCMR1_IC2F_Pos (12U)
+#define TIM_CCMR1_IC2F_Msk (0xFU << TIM_CCMR1_IC2F_Pos) /*!< 0x0000F000 */
+#define TIM_CCMR1_IC2F TIM_CCMR1_IC2F_Msk /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
+#define TIM_CCMR1_IC2F_0 (0x1U << TIM_CCMR1_IC2F_Pos) /*!< 0x00001000 */
+#define TIM_CCMR1_IC2F_1 (0x2U << TIM_CCMR1_IC2F_Pos) /*!< 0x00002000 */
+#define TIM_CCMR1_IC2F_2 (0x4U << TIM_CCMR1_IC2F_Pos) /*!< 0x00004000 */
+#define TIM_CCMR1_IC2F_3 (0x8U << TIM_CCMR1_IC2F_Pos) /*!< 0x00008000 */
+
+/****************** Bit definition for TIM_CCMR2 register ******************/
+#define TIM_CCMR2_CC3S_Pos (0U)
+#define TIM_CCMR2_CC3S_Msk (0x3U << TIM_CCMR2_CC3S_Pos) /*!< 0x00000003 */
+#define TIM_CCMR2_CC3S TIM_CCMR2_CC3S_Msk /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
+#define TIM_CCMR2_CC3S_0 (0x1U << TIM_CCMR2_CC3S_Pos) /*!< 0x00000001 */
+#define TIM_CCMR2_CC3S_1 (0x2U << TIM_CCMR2_CC3S_Pos) /*!< 0x00000002 */
+
+#define TIM_CCMR2_OC3FE_Pos (2U)
+#define TIM_CCMR2_OC3FE_Msk (0x1U << TIM_CCMR2_OC3FE_Pos) /*!< 0x00000004 */
+#define TIM_CCMR2_OC3FE TIM_CCMR2_OC3FE_Msk /*!<Output Compare 3 Fast enable */
+#define TIM_CCMR2_OC3PE_Pos (3U)
+#define TIM_CCMR2_OC3PE_Msk (0x1U << TIM_CCMR2_OC3PE_Pos) /*!< 0x00000008 */
+#define TIM_CCMR2_OC3PE TIM_CCMR2_OC3PE_Msk /*!<Output Compare 3 Preload enable */
+
+#define TIM_CCMR2_OC3M_Pos (4U)
+#define TIM_CCMR2_OC3M_Msk (0x7U << TIM_CCMR2_OC3M_Pos) /*!< 0x00000070 */
+#define TIM_CCMR2_OC3M TIM_CCMR2_OC3M_Msk /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
+#define TIM_CCMR2_OC3M_0 (0x1U << TIM_CCMR2_OC3M_Pos) /*!< 0x00000010 */
+#define TIM_CCMR2_OC3M_1 (0x2U << TIM_CCMR2_OC3M_Pos) /*!< 0x00000020 */
+#define TIM_CCMR2_OC3M_2 (0x4U << TIM_CCMR2_OC3M_Pos) /*!< 0x00000040 */
+
+#define TIM_CCMR2_OC3CE_Pos (7U)
+#define TIM_CCMR2_OC3CE_Msk (0x1U << TIM_CCMR2_OC3CE_Pos) /*!< 0x00000080 */
+#define TIM_CCMR2_OC3CE TIM_CCMR2_OC3CE_Msk /*!<Output Compare 3 Clear Enable */
+
+#define TIM_CCMR2_CC4S_Pos (8U)
+#define TIM_CCMR2_CC4S_Msk (0x3U << TIM_CCMR2_CC4S_Pos) /*!< 0x00000300 */
+#define TIM_CCMR2_CC4S TIM_CCMR2_CC4S_Msk /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
+#define TIM_CCMR2_CC4S_0 (0x1U << TIM_CCMR2_CC4S_Pos) /*!< 0x00000100 */
+#define TIM_CCMR2_CC4S_1 (0x2U << TIM_CCMR2_CC4S_Pos) /*!< 0x00000200 */
+
+#define TIM_CCMR2_OC4FE_Pos (10U)
+#define TIM_CCMR2_OC4FE_Msk (0x1U << TIM_CCMR2_OC4FE_Pos) /*!< 0x00000400 */
+#define TIM_CCMR2_OC4FE TIM_CCMR2_OC4FE_Msk /*!<Output Compare 4 Fast enable */
+#define TIM_CCMR2_OC4PE_Pos (11U)
+#define TIM_CCMR2_OC4PE_Msk (0x1U << TIM_CCMR2_OC4PE_Pos) /*!< 0x00000800 */
+#define TIM_CCMR2_OC4PE TIM_CCMR2_OC4PE_Msk /*!<Output Compare 4 Preload enable */
+
+#define TIM_CCMR2_OC4M_Pos (12U)
+#define TIM_CCMR2_OC4M_Msk (0x7U << TIM_CCMR2_OC4M_Pos) /*!< 0x00007000 */
+#define TIM_CCMR2_OC4M TIM_CCMR2_OC4M_Msk /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
+#define TIM_CCMR2_OC4M_0 (0x1U << TIM_CCMR2_OC4M_Pos) /*!< 0x00001000 */
+#define TIM_CCMR2_OC4M_1 (0x2U << TIM_CCMR2_OC4M_Pos) /*!< 0x00002000 */
+#define TIM_CCMR2_OC4M_2 (0x4U << TIM_CCMR2_OC4M_Pos) /*!< 0x00004000 */
+
+#define TIM_CCMR2_OC4CE_Pos (15U)
+#define TIM_CCMR2_OC4CE_Msk (0x1U << TIM_CCMR2_OC4CE_Pos) /*!< 0x00008000 */
+#define TIM_CCMR2_OC4CE TIM_CCMR2_OC4CE_Msk /*!<Output Compare 4 Clear Enable */
+
+/*---------------------------------------------------------------------------*/
+
+#define TIM_CCMR2_IC3PSC_Pos (2U)
+#define TIM_CCMR2_IC3PSC_Msk (0x3U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x0000000C */
+#define TIM_CCMR2_IC3PSC TIM_CCMR2_IC3PSC_Msk /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
+#define TIM_CCMR2_IC3PSC_0 (0x1U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x00000004 */
+#define TIM_CCMR2_IC3PSC_1 (0x2U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x00000008 */
+
+#define TIM_CCMR2_IC3F_Pos (4U)
+#define TIM_CCMR2_IC3F_Msk (0xFU << TIM_CCMR2_IC3F_Pos) /*!< 0x000000F0 */
+#define TIM_CCMR2_IC3F TIM_CCMR2_IC3F_Msk /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
+#define TIM_CCMR2_IC3F_0 (0x1U << TIM_CCMR2_IC3F_Pos) /*!< 0x00000010 */
+#define TIM_CCMR2_IC3F_1 (0x2U << TIM_CCMR2_IC3F_Pos) /*!< 0x00000020 */
+#define TIM_CCMR2_IC3F_2 (0x4U << TIM_CCMR2_IC3F_Pos) /*!< 0x00000040 */
+#define TIM_CCMR2_IC3F_3 (0x8U << TIM_CCMR2_IC3F_Pos) /*!< 0x00000080 */
+
+#define TIM_CCMR2_IC4PSC_Pos (10U)
+#define TIM_CCMR2_IC4PSC_Msk (0x3U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000C00 */
+#define TIM_CCMR2_IC4PSC TIM_CCMR2_IC4PSC_Msk /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
+#define TIM_CCMR2_IC4PSC_0 (0x1U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000400 */
+#define TIM_CCMR2_IC4PSC_1 (0x2U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000800 */
+
+#define TIM_CCMR2_IC4F_Pos (12U)
+#define TIM_CCMR2_IC4F_Msk (0xFU << TIM_CCMR2_IC4F_Pos) /*!< 0x0000F000 */
+#define TIM_CCMR2_IC4F TIM_CCMR2_IC4F_Msk /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
+#define TIM_CCMR2_IC4F_0 (0x1U << TIM_CCMR2_IC4F_Pos) /*!< 0x00001000 */
+#define TIM_CCMR2_IC4F_1 (0x2U << TIM_CCMR2_IC4F_Pos) /*!< 0x00002000 */
+#define TIM_CCMR2_IC4F_2 (0x4U << TIM_CCMR2_IC4F_Pos) /*!< 0x00004000 */
+#define TIM_CCMR2_IC4F_3 (0x8U << TIM_CCMR2_IC4F_Pos) /*!< 0x00008000 */
+
+/******************* Bit definition for TIM_CCER register ******************/
+#define TIM_CCER_CC1E_Pos (0U)
+#define TIM_CCER_CC1E_Msk (0x1U << TIM_CCER_CC1E_Pos) /*!< 0x00000001 */
+#define TIM_CCER_CC1E TIM_CCER_CC1E_Msk /*!<Capture/Compare 1 output enable */
+#define TIM_CCER_CC1P_Pos (1U)
+#define TIM_CCER_CC1P_Msk (0x1U << TIM_CCER_CC1P_Pos) /*!< 0x00000002 */
+#define TIM_CCER_CC1P TIM_CCER_CC1P_Msk /*!<Capture/Compare 1 output Polarity */
+#define TIM_CCER_CC1NE_Pos (2U)
+#define TIM_CCER_CC1NE_Msk (0x1U << TIM_CCER_CC1NE_Pos) /*!< 0x00000004 */
+#define TIM_CCER_CC1NE TIM_CCER_CC1NE_Msk /*!<Capture/Compare 1 Complementary output enable */
+#define TIM_CCER_CC1NP_Pos (3U)
+#define TIM_CCER_CC1NP_Msk (0x1U << TIM_CCER_CC1NP_Pos) /*!< 0x00000008 */
+#define TIM_CCER_CC1NP TIM_CCER_CC1NP_Msk /*!<Capture/Compare 1 Complementary output Polarity */
+#define TIM_CCER_CC2E_Pos (4U)
+#define TIM_CCER_CC2E_Msk (0x1U << TIM_CCER_CC2E_Pos) /*!< 0x00000010 */
+#define TIM_CCER_CC2E TIM_CCER_CC2E_Msk /*!<Capture/Compare 2 output enable */
+#define TIM_CCER_CC2P_Pos (5U)
+#define TIM_CCER_CC2P_Msk (0x1U << TIM_CCER_CC2P_Pos) /*!< 0x00000020 */
+#define TIM_CCER_CC2P TIM_CCER_CC2P_Msk /*!<Capture/Compare 2 output Polarity */
+#define TIM_CCER_CC2NE_Pos (6U)
+#define TIM_CCER_CC2NE_Msk (0x1U << TIM_CCER_CC2NE_Pos) /*!< 0x00000040 */
+#define TIM_CCER_CC2NE TIM_CCER_CC2NE_Msk /*!<Capture/Compare 2 Complementary output enable */
+#define TIM_CCER_CC2NP_Pos (7U)
+#define TIM_CCER_CC2NP_Msk (0x1U << TIM_CCER_CC2NP_Pos) /*!< 0x00000080 */
+#define TIM_CCER_CC2NP TIM_CCER_CC2NP_Msk /*!<Capture/Compare 2 Complementary output Polarity */
+#define TIM_CCER_CC3E_Pos (8U)
+#define TIM_CCER_CC3E_Msk (0x1U << TIM_CCER_CC3E_Pos) /*!< 0x00000100 */
+#define TIM_CCER_CC3E TIM_CCER_CC3E_Msk /*!<Capture/Compare 3 output enable */
+#define TIM_CCER_CC3P_Pos (9U)
+#define TIM_CCER_CC3P_Msk (0x1U << TIM_CCER_CC3P_Pos) /*!< 0x00000200 */
+#define TIM_CCER_CC3P TIM_CCER_CC3P_Msk /*!<Capture/Compare 3 output Polarity */
+#define TIM_CCER_CC3NE_Pos (10U)
+#define TIM_CCER_CC3NE_Msk (0x1U << TIM_CCER_CC3NE_Pos) /*!< 0x00000400 */
+#define TIM_CCER_CC3NE TIM_CCER_CC3NE_Msk /*!<Capture/Compare 3 Complementary output enable */
+#define TIM_CCER_CC3NP_Pos (11U)
+#define TIM_CCER_CC3NP_Msk (0x1U << TIM_CCER_CC3NP_Pos) /*!< 0x00000800 */
+#define TIM_CCER_CC3NP TIM_CCER_CC3NP_Msk /*!<Capture/Compare 3 Complementary output Polarity */
+#define TIM_CCER_CC4E_Pos (12U)
+#define TIM_CCER_CC4E_Msk (0x1U << TIM_CCER_CC4E_Pos) /*!< 0x00001000 */
+#define TIM_CCER_CC4E TIM_CCER_CC4E_Msk /*!<Capture/Compare 4 output enable */
+#define TIM_CCER_CC4P_Pos (13U)
+#define TIM_CCER_CC4P_Msk (0x1U << TIM_CCER_CC4P_Pos) /*!< 0x00002000 */
+#define TIM_CCER_CC4P TIM_CCER_CC4P_Msk /*!<Capture/Compare 4 output Polarity */
+#define TIM_CCER_CC4NP_Pos (15U)
+#define TIM_CCER_CC4NP_Msk (0x1U << TIM_CCER_CC4NP_Pos) /*!< 0x00008000 */
+#define TIM_CCER_CC4NP TIM_CCER_CC4NP_Msk /*!<Capture/Compare 4 Complementary output Polarity */
+
+/******************* Bit definition for TIM_CNT register *******************/
+#define TIM_CNT_CNT_Pos (0U)
+#define TIM_CNT_CNT_Msk (0xFFFFFFFFU << TIM_CNT_CNT_Pos) /*!< 0xFFFFFFFF */
+#define TIM_CNT_CNT TIM_CNT_CNT_Msk /*!<Counter Value */
+
+/******************* Bit definition for TIM_PSC register *******************/
+#define TIM_PSC_PSC_Pos (0U)
+#define TIM_PSC_PSC_Msk (0xFFFFU << TIM_PSC_PSC_Pos) /*!< 0x0000FFFF */
+#define TIM_PSC_PSC TIM_PSC_PSC_Msk /*!<Prescaler Value */
+
+/******************* Bit definition for TIM_ARR register *******************/
+#define TIM_ARR_ARR_Pos (0U)
+#define TIM_ARR_ARR_Msk (0xFFFFFFFFU << TIM_ARR_ARR_Pos) /*!< 0xFFFFFFFF */
+#define TIM_ARR_ARR TIM_ARR_ARR_Msk /*!<actual auto-reload Value */
+
+/******************* Bit definition for TIM_RCR register *******************/
+#define TIM_RCR_REP_Pos (0U)
+#define TIM_RCR_REP_Msk (0xFFU << TIM_RCR_REP_Pos) /*!< 0x000000FF */
+#define TIM_RCR_REP TIM_RCR_REP_Msk /*!<Repetition Counter Value */
+
+/******************* Bit definition for TIM_CCR1 register ******************/
+#define TIM_CCR1_CCR1_Pos (0U)
+#define TIM_CCR1_CCR1_Msk (0xFFFFU << TIM_CCR1_CCR1_Pos) /*!< 0x0000FFFF */
+#define TIM_CCR1_CCR1 TIM_CCR1_CCR1_Msk /*!<Capture/Compare 1 Value */
+
+/******************* Bit definition for TIM_CCR2 register ******************/
+#define TIM_CCR2_CCR2_Pos (0U)
+#define TIM_CCR2_CCR2_Msk (0xFFFFU << TIM_CCR2_CCR2_Pos) /*!< 0x0000FFFF */
+#define TIM_CCR2_CCR2 TIM_CCR2_CCR2_Msk /*!<Capture/Compare 2 Value */
+
+/******************* Bit definition for TIM_CCR3 register ******************/
+#define TIM_CCR3_CCR3_Pos (0U)
+#define TIM_CCR3_CCR3_Msk (0xFFFFU << TIM_CCR3_CCR3_Pos) /*!< 0x0000FFFF */
+#define TIM_CCR3_CCR3 TIM_CCR3_CCR3_Msk /*!<Capture/Compare 3 Value */
+
+/******************* Bit definition for TIM_CCR4 register ******************/
+#define TIM_CCR4_CCR4_Pos (0U)
+#define TIM_CCR4_CCR4_Msk (0xFFFFU << TIM_CCR4_CCR4_Pos) /*!< 0x0000FFFF */
+#define TIM_CCR4_CCR4 TIM_CCR4_CCR4_Msk /*!<Capture/Compare 4 Value */
+
+/******************* Bit definition for TIM_BDTR register ******************/
+#define TIM_BDTR_DTG_Pos (0U)
+#define TIM_BDTR_DTG_Msk (0xFFU << TIM_BDTR_DTG_Pos) /*!< 0x000000FF */
+#define TIM_BDTR_DTG TIM_BDTR_DTG_Msk /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
+#define TIM_BDTR_DTG_0 (0x01U << TIM_BDTR_DTG_Pos) /*!< 0x00000001 */
+#define TIM_BDTR_DTG_1 (0x02U << TIM_BDTR_DTG_Pos) /*!< 0x00000002 */
+#define TIM_BDTR_DTG_2 (0x04U << TIM_BDTR_DTG_Pos) /*!< 0x00000004 */
+#define TIM_BDTR_DTG_3 (0x08U << TIM_BDTR_DTG_Pos) /*!< 0x00000008 */
+#define TIM_BDTR_DTG_4 (0x10U << TIM_BDTR_DTG_Pos) /*!< 0x00000010 */
+#define TIM_BDTR_DTG_5 (0x20U << TIM_BDTR_DTG_Pos) /*!< 0x00000020 */
+#define TIM_BDTR_DTG_6 (0x40U << TIM_BDTR_DTG_Pos) /*!< 0x00000040 */
+#define TIM_BDTR_DTG_7 (0x80U << TIM_BDTR_DTG_Pos) /*!< 0x00000080 */
+
+#define TIM_BDTR_LOCK_Pos (8U)
+#define TIM_BDTR_LOCK_Msk (0x3U << TIM_BDTR_LOCK_Pos) /*!< 0x00000300 */
+#define TIM_BDTR_LOCK TIM_BDTR_LOCK_Msk /*!<LOCK[1:0] bits (Lock Configuration) */
+#define TIM_BDTR_LOCK_0 (0x1U << TIM_BDTR_LOCK_Pos) /*!< 0x00000100 */
+#define TIM_BDTR_LOCK_1 (0x2U << TIM_BDTR_LOCK_Pos) /*!< 0x00000200 */
+
+#define TIM_BDTR_OSSI_Pos (10U)
+#define TIM_BDTR_OSSI_Msk (0x1U << TIM_BDTR_OSSI_Pos) /*!< 0x00000400 */
+#define TIM_BDTR_OSSI TIM_BDTR_OSSI_Msk /*!<Off-State Selection for Idle mode */
+#define TIM_BDTR_OSSR_Pos (11U)
+#define TIM_BDTR_OSSR_Msk (0x1U << TIM_BDTR_OSSR_Pos) /*!< 0x00000800 */
+#define TIM_BDTR_OSSR TIM_BDTR_OSSR_Msk /*!<Off-State Selection for Run mode */
+#define TIM_BDTR_BKE_Pos (12U)
+#define TIM_BDTR_BKE_Msk (0x1U << TIM_BDTR_BKE_Pos) /*!< 0x00001000 */
+#define TIM_BDTR_BKE TIM_BDTR_BKE_Msk /*!<Break enable */
+#define TIM_BDTR_BKP_Pos (13U)
+#define TIM_BDTR_BKP_Msk (0x1U << TIM_BDTR_BKP_Pos) /*!< 0x00002000 */
+#define TIM_BDTR_BKP TIM_BDTR_BKP_Msk /*!<Break Polarity */
+#define TIM_BDTR_AOE_Pos (14U)
+#define TIM_BDTR_AOE_Msk (0x1U << TIM_BDTR_AOE_Pos) /*!< 0x00004000 */
+#define TIM_BDTR_AOE TIM_BDTR_AOE_Msk /*!<Automatic Output enable */
+#define TIM_BDTR_MOE_Pos (15U)
+#define TIM_BDTR_MOE_Msk (0x1U << TIM_BDTR_MOE_Pos) /*!< 0x00008000 */
+#define TIM_BDTR_MOE TIM_BDTR_MOE_Msk /*!<Main Output enable */
+
+/******************* Bit definition for TIM_DCR register *******************/
+#define TIM_DCR_DBA_Pos (0U)
+#define TIM_DCR_DBA_Msk (0x1FU << TIM_DCR_DBA_Pos) /*!< 0x0000001F */
+#define TIM_DCR_DBA TIM_DCR_DBA_Msk /*!<DBA[4:0] bits (DMA Base Address) */
+#define TIM_DCR_DBA_0 (0x01U << TIM_DCR_DBA_Pos) /*!< 0x00000001 */
+#define TIM_DCR_DBA_1 (0x02U << TIM_DCR_DBA_Pos) /*!< 0x00000002 */
+#define TIM_DCR_DBA_2 (0x04U << TIM_DCR_DBA_Pos) /*!< 0x00000004 */
+#define TIM_DCR_DBA_3 (0x08U << TIM_DCR_DBA_Pos) /*!< 0x00000008 */
+#define TIM_DCR_DBA_4 (0x10U << TIM_DCR_DBA_Pos) /*!< 0x00000010 */
+
+#define TIM_DCR_DBL_Pos (8U)
+#define TIM_DCR_DBL_Msk (0x1FU << TIM_DCR_DBL_Pos) /*!< 0x00001F00 */
+#define TIM_DCR_DBL TIM_DCR_DBL_Msk /*!<DBL[4:0] bits (DMA Burst Length) */
+#define TIM_DCR_DBL_0 (0x01U << TIM_DCR_DBL_Pos) /*!< 0x00000100 */
+#define TIM_DCR_DBL_1 (0x02U << TIM_DCR_DBL_Pos) /*!< 0x00000200 */
+#define TIM_DCR_DBL_2 (0x04U << TIM_DCR_DBL_Pos) /*!< 0x00000400 */
+#define TIM_DCR_DBL_3 (0x08U << TIM_DCR_DBL_Pos) /*!< 0x00000800 */
+#define TIM_DCR_DBL_4 (0x10U << TIM_DCR_DBL_Pos) /*!< 0x00001000 */
+
+/******************* Bit definition for TIM_DMAR register ******************/
+#define TIM_DMAR_DMAB_Pos (0U)
+#define TIM_DMAR_DMAB_Msk (0xFFFFU << TIM_DMAR_DMAB_Pos) /*!< 0x0000FFFF */
+#define TIM_DMAR_DMAB TIM_DMAR_DMAB_Msk /*!<DMA register for burst accesses */
+
+/******************* Bit definition for TIM_OR register ********************/
+
+/******************************************************************************/
+/* */
+/* Real-Time Clock */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for RTC_CRH register ********************/
+#define RTC_CRH_SECIE_Pos (0U)
+#define RTC_CRH_SECIE_Msk (0x1U << RTC_CRH_SECIE_Pos) /*!< 0x00000001 */
+#define RTC_CRH_SECIE RTC_CRH_SECIE_Msk /*!< Second Interrupt Enable */
+#define RTC_CRH_ALRIE_Pos (1U)
+#define RTC_CRH_ALRIE_Msk (0x1U << RTC_CRH_ALRIE_Pos) /*!< 0x00000002 */
+#define RTC_CRH_ALRIE RTC_CRH_ALRIE_Msk /*!< Alarm Interrupt Enable */
+#define RTC_CRH_OWIE_Pos (2U)
+#define RTC_CRH_OWIE_Msk (0x1U << RTC_CRH_OWIE_Pos) /*!< 0x00000004 */
+#define RTC_CRH_OWIE RTC_CRH_OWIE_Msk /*!< OverfloW Interrupt Enable */
+
+/******************* Bit definition for RTC_CRL register ********************/
+#define RTC_CRL_SECF_Pos (0U)
+#define RTC_CRL_SECF_Msk (0x1U << RTC_CRL_SECF_Pos) /*!< 0x00000001 */
+#define RTC_CRL_SECF RTC_CRL_SECF_Msk /*!< Second Flag */
+#define RTC_CRL_ALRF_Pos (1U)
+#define RTC_CRL_ALRF_Msk (0x1U << RTC_CRL_ALRF_Pos) /*!< 0x00000002 */
+#define RTC_CRL_ALRF RTC_CRL_ALRF_Msk /*!< Alarm Flag */
+#define RTC_CRL_OWF_Pos (2U)
+#define RTC_CRL_OWF_Msk (0x1U << RTC_CRL_OWF_Pos) /*!< 0x00000004 */
+#define RTC_CRL_OWF RTC_CRL_OWF_Msk /*!< OverfloW Flag */
+#define RTC_CRL_RSF_Pos (3U)
+#define RTC_CRL_RSF_Msk (0x1U << RTC_CRL_RSF_Pos) /*!< 0x00000008 */
+#define RTC_CRL_RSF RTC_CRL_RSF_Msk /*!< Registers Synchronized Flag */
+#define RTC_CRL_CNF_Pos (4U)
+#define RTC_CRL_CNF_Msk (0x1U << RTC_CRL_CNF_Pos) /*!< 0x00000010 */
+#define RTC_CRL_CNF RTC_CRL_CNF_Msk /*!< Configuration Flag */
+#define RTC_CRL_RTOFF_Pos (5U)
+#define RTC_CRL_RTOFF_Msk (0x1U << RTC_CRL_RTOFF_Pos) /*!< 0x00000020 */
+#define RTC_CRL_RTOFF RTC_CRL_RTOFF_Msk /*!< RTC operation OFF */
+
+/******************* Bit definition for RTC_PRLH register *******************/
+#define RTC_PRLH_PRL_Pos (0U)
+#define RTC_PRLH_PRL_Msk (0xFU << RTC_PRLH_PRL_Pos) /*!< 0x0000000F */
+#define RTC_PRLH_PRL RTC_PRLH_PRL_Msk /*!< RTC Prescaler Reload Value High */
+
+/******************* Bit definition for RTC_PRLL register *******************/
+#define RTC_PRLL_PRL_Pos (0U)
+#define RTC_PRLL_PRL_Msk (0xFFFFU << RTC_PRLL_PRL_Pos) /*!< 0x0000FFFF */
+#define RTC_PRLL_PRL RTC_PRLL_PRL_Msk /*!< RTC Prescaler Reload Value Low */
+
+/******************* Bit definition for RTC_DIVH register *******************/
+#define RTC_DIVH_RTC_DIV_Pos (0U)
+#define RTC_DIVH_RTC_DIV_Msk (0xFU << RTC_DIVH_RTC_DIV_Pos) /*!< 0x0000000F */
+#define RTC_DIVH_RTC_DIV RTC_DIVH_RTC_DIV_Msk /*!< RTC Clock Divider High */
+
+/******************* Bit definition for RTC_DIVL register *******************/
+#define RTC_DIVL_RTC_DIV_Pos (0U)
+#define RTC_DIVL_RTC_DIV_Msk (0xFFFFU << RTC_DIVL_RTC_DIV_Pos) /*!< 0x0000FFFF */
+#define RTC_DIVL_RTC_DIV RTC_DIVL_RTC_DIV_Msk /*!< RTC Clock Divider Low */
+
+/******************* Bit definition for RTC_CNTH register *******************/
+#define RTC_CNTH_RTC_CNT_Pos (0U)
+#define RTC_CNTH_RTC_CNT_Msk (0xFFFFU << RTC_CNTH_RTC_CNT_Pos) /*!< 0x0000FFFF */
+#define RTC_CNTH_RTC_CNT RTC_CNTH_RTC_CNT_Msk /*!< RTC Counter High */
+
+/******************* Bit definition for RTC_CNTL register *******************/
+#define RTC_CNTL_RTC_CNT_Pos (0U)
+#define RTC_CNTL_RTC_CNT_Msk (0xFFFFU << RTC_CNTL_RTC_CNT_Pos) /*!< 0x0000FFFF */
+#define RTC_CNTL_RTC_CNT RTC_CNTL_RTC_CNT_Msk /*!< RTC Counter Low */
+
+/******************* Bit definition for RTC_ALRH register *******************/
+#define RTC_ALRH_RTC_ALR_Pos (0U)
+#define RTC_ALRH_RTC_ALR_Msk (0xFFFFU << RTC_ALRH_RTC_ALR_Pos) /*!< 0x0000FFFF */
+#define RTC_ALRH_RTC_ALR RTC_ALRH_RTC_ALR_Msk /*!< RTC Alarm High */
+
+/******************* Bit definition for RTC_ALRL register *******************/
+#define RTC_ALRL_RTC_ALR_Pos (0U)
+#define RTC_ALRL_RTC_ALR_Msk (0xFFFFU << RTC_ALRL_RTC_ALR_Pos) /*!< 0x0000FFFF */
+#define RTC_ALRL_RTC_ALR RTC_ALRL_RTC_ALR_Msk /*!< RTC Alarm Low */
+
+/******************************************************************************/
+/* */
+/* Independent WATCHDOG (IWDG) */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for IWDG_KR register ********************/
+#define IWDG_KR_KEY_Pos (0U)
+#define IWDG_KR_KEY_Msk (0xFFFFU << IWDG_KR_KEY_Pos) /*!< 0x0000FFFF */
+#define IWDG_KR_KEY IWDG_KR_KEY_Msk /*!< Key value (write only, read 0000h) */
+
+/******************* Bit definition for IWDG_PR register ********************/
+#define IWDG_PR_PR_Pos (0U)
+#define IWDG_PR_PR_Msk (0x7U << IWDG_PR_PR_Pos) /*!< 0x00000007 */
+#define IWDG_PR_PR IWDG_PR_PR_Msk /*!< PR[2:0] (Prescaler divider) */
+#define IWDG_PR_PR_0 (0x1U << IWDG_PR_PR_Pos) /*!< 0x00000001 */
+#define IWDG_PR_PR_1 (0x2U << IWDG_PR_PR_Pos) /*!< 0x00000002 */
+#define IWDG_PR_PR_2 (0x4U << IWDG_PR_PR_Pos) /*!< 0x00000004 */
+
+/******************* Bit definition for IWDG_RLR register *******************/
+#define IWDG_RLR_RL_Pos (0U)
+#define IWDG_RLR_RL_Msk (0xFFFU << IWDG_RLR_RL_Pos) /*!< 0x00000FFF */
+#define IWDG_RLR_RL IWDG_RLR_RL_Msk /*!< Watchdog counter reload value */
+
+/******************* Bit definition for IWDG_SR register ********************/
+#define IWDG_SR_PVU_Pos (0U)
+#define IWDG_SR_PVU_Msk (0x1U << IWDG_SR_PVU_Pos) /*!< 0x00000001 */
+#define IWDG_SR_PVU IWDG_SR_PVU_Msk /*!< Watchdog prescaler value update */
+#define IWDG_SR_RVU_Pos (1U)
+#define IWDG_SR_RVU_Msk (0x1U << IWDG_SR_RVU_Pos) /*!< 0x00000002 */
+#define IWDG_SR_RVU IWDG_SR_RVU_Msk /*!< Watchdog counter reload value update */
+
+/******************************************************************************/
+/* */
+/* Window WATCHDOG (WWDG) */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for WWDG_CR register ********************/
+#define WWDG_CR_T_Pos (0U)
+#define WWDG_CR_T_Msk (0x7FU << WWDG_CR_T_Pos) /*!< 0x0000007F */
+#define WWDG_CR_T WWDG_CR_T_Msk /*!< T[6:0] bits (7-Bit counter (MSB to LSB)) */
+#define WWDG_CR_T_0 (0x01U << WWDG_CR_T_Pos) /*!< 0x00000001 */
+#define WWDG_CR_T_1 (0x02U << WWDG_CR_T_Pos) /*!< 0x00000002 */
+#define WWDG_CR_T_2 (0x04U << WWDG_CR_T_Pos) /*!< 0x00000004 */
+#define WWDG_CR_T_3 (0x08U << WWDG_CR_T_Pos) /*!< 0x00000008 */
+#define WWDG_CR_T_4 (0x10U << WWDG_CR_T_Pos) /*!< 0x00000010 */
+#define WWDG_CR_T_5 (0x20U << WWDG_CR_T_Pos) /*!< 0x00000020 */
+#define WWDG_CR_T_6 (0x40U << WWDG_CR_T_Pos) /*!< 0x00000040 */
+
+/* Legacy defines */
+#define WWDG_CR_T0 WWDG_CR_T_0
+#define WWDG_CR_T1 WWDG_CR_T_1
+#define WWDG_CR_T2 WWDG_CR_T_2
+#define WWDG_CR_T3 WWDG_CR_T_3
+#define WWDG_CR_T4 WWDG_CR_T_4
+#define WWDG_CR_T5 WWDG_CR_T_5
+#define WWDG_CR_T6 WWDG_CR_T_6
+
+#define WWDG_CR_WDGA_Pos (7U)
+#define WWDG_CR_WDGA_Msk (0x1U << WWDG_CR_WDGA_Pos) /*!< 0x00000080 */
+#define WWDG_CR_WDGA WWDG_CR_WDGA_Msk /*!< Activation bit */
+
+/******************* Bit definition for WWDG_CFR register *******************/
+#define WWDG_CFR_W_Pos (0U)
+#define WWDG_CFR_W_Msk (0x7FU << WWDG_CFR_W_Pos) /*!< 0x0000007F */
+#define WWDG_CFR_W WWDG_CFR_W_Msk /*!< W[6:0] bits (7-bit window value) */
+#define WWDG_CFR_W_0 (0x01U << WWDG_CFR_W_Pos) /*!< 0x00000001 */
+#define WWDG_CFR_W_1 (0x02U << WWDG_CFR_W_Pos) /*!< 0x00000002 */
+#define WWDG_CFR_W_2 (0x04U << WWDG_CFR_W_Pos) /*!< 0x00000004 */
+#define WWDG_CFR_W_3 (0x08U << WWDG_CFR_W_Pos) /*!< 0x00000008 */
+#define WWDG_CFR_W_4 (0x10U << WWDG_CFR_W_Pos) /*!< 0x00000010 */
+#define WWDG_CFR_W_5 (0x20U << WWDG_CFR_W_Pos) /*!< 0x00000020 */
+#define WWDG_CFR_W_6 (0x40U << WWDG_CFR_W_Pos) /*!< 0x00000040 */
+
+/* Legacy defines */
+#define WWDG_CFR_W0 WWDG_CFR_W_0
+#define WWDG_CFR_W1 WWDG_CFR_W_1
+#define WWDG_CFR_W2 WWDG_CFR_W_2
+#define WWDG_CFR_W3 WWDG_CFR_W_3
+#define WWDG_CFR_W4 WWDG_CFR_W_4
+#define WWDG_CFR_W5 WWDG_CFR_W_5
+#define WWDG_CFR_W6 WWDG_CFR_W_6
+
+#define WWDG_CFR_WDGTB_Pos (7U)
+#define WWDG_CFR_WDGTB_Msk (0x3U << WWDG_CFR_WDGTB_Pos) /*!< 0x00000180 */
+#define WWDG_CFR_WDGTB WWDG_CFR_WDGTB_Msk /*!< WDGTB[1:0] bits (Timer Base) */
+#define WWDG_CFR_WDGTB_0 (0x1U << WWDG_CFR_WDGTB_Pos) /*!< 0x00000080 */
+#define WWDG_CFR_WDGTB_1 (0x2U << WWDG_CFR_WDGTB_Pos) /*!< 0x00000100 */
+
+/* Legacy defines */
+#define WWDG_CFR_WDGTB0 WWDG_CFR_WDGTB_0
+#define WWDG_CFR_WDGTB1 WWDG_CFR_WDGTB_1
+
+#define WWDG_CFR_EWI_Pos (9U)
+#define WWDG_CFR_EWI_Msk (0x1U << WWDG_CFR_EWI_Pos) /*!< 0x00000200 */
+#define WWDG_CFR_EWI WWDG_CFR_EWI_Msk /*!< Early Wakeup Interrupt */
+
+/******************* Bit definition for WWDG_SR register ********************/
+#define WWDG_SR_EWIF_Pos (0U)
+#define WWDG_SR_EWIF_Msk (0x1U << WWDG_SR_EWIF_Pos) /*!< 0x00000001 */
+#define WWDG_SR_EWIF WWDG_SR_EWIF_Msk /*!< Early Wakeup Interrupt Flag */
+
+
+/******************************************************************************/
+/* */
+/* SD host Interface */
+/* */
+/******************************************************************************/
+
+/****************** Bit definition for SDIO_POWER register ******************/
+#define SDIO_POWER_PWRCTRL_Pos (0U)
+#define SDIO_POWER_PWRCTRL_Msk (0x3U << SDIO_POWER_PWRCTRL_Pos) /*!< 0x00000003 */
+#define SDIO_POWER_PWRCTRL SDIO_POWER_PWRCTRL_Msk /*!< PWRCTRL[1:0] bits (Power supply control bits) */
+#define SDIO_POWER_PWRCTRL_0 (0x1U << SDIO_POWER_PWRCTRL_Pos) /*!< 0x01 */
+#define SDIO_POWER_PWRCTRL_1 (0x2U << SDIO_POWER_PWRCTRL_Pos) /*!< 0x02 */
+
+/****************** Bit definition for SDIO_CLKCR register ******************/
+#define SDIO_CLKCR_CLKDIV_Pos (0U)
+#define SDIO_CLKCR_CLKDIV_Msk (0xFFU << SDIO_CLKCR_CLKDIV_Pos) /*!< 0x000000FF */
+#define SDIO_CLKCR_CLKDIV SDIO_CLKCR_CLKDIV_Msk /*!< Clock divide factor */
+#define SDIO_CLKCR_CLKEN_Pos (8U)
+#define SDIO_CLKCR_CLKEN_Msk (0x1U << SDIO_CLKCR_CLKEN_Pos) /*!< 0x00000100 */
+#define SDIO_CLKCR_CLKEN SDIO_CLKCR_CLKEN_Msk /*!< Clock enable bit */
+#define SDIO_CLKCR_PWRSAV_Pos (9U)
+#define SDIO_CLKCR_PWRSAV_Msk (0x1U << SDIO_CLKCR_PWRSAV_Pos) /*!< 0x00000200 */
+#define SDIO_CLKCR_PWRSAV SDIO_CLKCR_PWRSAV_Msk /*!< Power saving configuration bit */
+#define SDIO_CLKCR_BYPASS_Pos (10U)
+#define SDIO_CLKCR_BYPASS_Msk (0x1U << SDIO_CLKCR_BYPASS_Pos) /*!< 0x00000400 */
+#define SDIO_CLKCR_BYPASS SDIO_CLKCR_BYPASS_Msk /*!< Clock divider bypass enable bit */
+
+#define SDIO_CLKCR_WIDBUS_Pos (11U)
+#define SDIO_CLKCR_WIDBUS_Msk (0x3U << SDIO_CLKCR_WIDBUS_Pos) /*!< 0x00001800 */
+#define SDIO_CLKCR_WIDBUS SDIO_CLKCR_WIDBUS_Msk /*!< WIDBUS[1:0] bits (Wide bus mode enable bit) */
+#define SDIO_CLKCR_WIDBUS_0 (0x1U << SDIO_CLKCR_WIDBUS_Pos) /*!< 0x0800 */
+#define SDIO_CLKCR_WIDBUS_1 (0x2U << SDIO_CLKCR_WIDBUS_Pos) /*!< 0x1000 */
+
+#define SDIO_CLKCR_NEGEDGE_Pos (13U)
+#define SDIO_CLKCR_NEGEDGE_Msk (0x1U << SDIO_CLKCR_NEGEDGE_Pos) /*!< 0x00002000 */
+#define SDIO_CLKCR_NEGEDGE SDIO_CLKCR_NEGEDGE_Msk /*!< SDIO_CK dephasing selection bit */
+#define SDIO_CLKCR_HWFC_EN_Pos (14U)
+#define SDIO_CLKCR_HWFC_EN_Msk (0x1U << SDIO_CLKCR_HWFC_EN_Pos) /*!< 0x00004000 */
+#define SDIO_CLKCR_HWFC_EN SDIO_CLKCR_HWFC_EN_Msk /*!< HW Flow Control enable */
+
+/******************* Bit definition for SDIO_ARG register *******************/
+#define SDIO_ARG_CMDARG_Pos (0U)
+#define SDIO_ARG_CMDARG_Msk (0xFFFFFFFFU << SDIO_ARG_CMDARG_Pos) /*!< 0xFFFFFFFF */
+#define SDIO_ARG_CMDARG SDIO_ARG_CMDARG_Msk /*!< Command argument */
+
+/******************* Bit definition for SDIO_CMD register *******************/
+#define SDIO_CMD_CMDINDEX_Pos (0U)
+#define SDIO_CMD_CMDINDEX_Msk (0x3FU << SDIO_CMD_CMDINDEX_Pos) /*!< 0x0000003F */
+#define SDIO_CMD_CMDINDEX SDIO_CMD_CMDINDEX_Msk /*!< Command Index */
+
+#define SDIO_CMD_WAITRESP_Pos (6U)
+#define SDIO_CMD_WAITRESP_Msk (0x3U << SDIO_CMD_WAITRESP_Pos) /*!< 0x000000C0 */
+#define SDIO_CMD_WAITRESP SDIO_CMD_WAITRESP_Msk /*!< WAITRESP[1:0] bits (Wait for response bits) */
+#define SDIO_CMD_WAITRESP_0 (0x1U << SDIO_CMD_WAITRESP_Pos) /*!< 0x0040 */
+#define SDIO_CMD_WAITRESP_1 (0x2U << SDIO_CMD_WAITRESP_Pos) /*!< 0x0080 */
+
+#define SDIO_CMD_WAITINT_Pos (8U)
+#define SDIO_CMD_WAITINT_Msk (0x1U << SDIO_CMD_WAITINT_Pos) /*!< 0x00000100 */
+#define SDIO_CMD_WAITINT SDIO_CMD_WAITINT_Msk /*!< CPSM Waits for Interrupt Request */
+#define SDIO_CMD_WAITPEND_Pos (9U)
+#define SDIO_CMD_WAITPEND_Msk (0x1U << SDIO_CMD_WAITPEND_Pos) /*!< 0x00000200 */
+#define SDIO_CMD_WAITPEND SDIO_CMD_WAITPEND_Msk /*!< CPSM Waits for ends of data transfer (CmdPend internal signal) */
+#define SDIO_CMD_CPSMEN_Pos (10U)
+#define SDIO_CMD_CPSMEN_Msk (0x1U << SDIO_CMD_CPSMEN_Pos) /*!< 0x00000400 */
+#define SDIO_CMD_CPSMEN SDIO_CMD_CPSMEN_Msk /*!< Command path state machine (CPSM) Enable bit */
+#define SDIO_CMD_SDIOSUSPEND_Pos (11U)
+#define SDIO_CMD_SDIOSUSPEND_Msk (0x1U << SDIO_CMD_SDIOSUSPEND_Pos) /*!< 0x00000800 */
+#define SDIO_CMD_SDIOSUSPEND SDIO_CMD_SDIOSUSPEND_Msk /*!< SD I/O suspend command */
+#define SDIO_CMD_ENCMDCOMPL_Pos (12U)
+#define SDIO_CMD_ENCMDCOMPL_Msk (0x1U << SDIO_CMD_ENCMDCOMPL_Pos) /*!< 0x00001000 */
+#define SDIO_CMD_ENCMDCOMPL SDIO_CMD_ENCMDCOMPL_Msk /*!< Enable CMD completion */
+#define SDIO_CMD_NIEN_Pos (13U)
+#define SDIO_CMD_NIEN_Msk (0x1U << SDIO_CMD_NIEN_Pos) /*!< 0x00002000 */
+#define SDIO_CMD_NIEN SDIO_CMD_NIEN_Msk /*!< Not Interrupt Enable */
+#define SDIO_CMD_CEATACMD_Pos (14U)
+#define SDIO_CMD_CEATACMD_Msk (0x1U << SDIO_CMD_CEATACMD_Pos) /*!< 0x00004000 */
+#define SDIO_CMD_CEATACMD SDIO_CMD_CEATACMD_Msk /*!< CE-ATA command */
+
+/***************** Bit definition for SDIO_RESPCMD register *****************/
+#define SDIO_RESPCMD_RESPCMD_Pos (0U)
+#define SDIO_RESPCMD_RESPCMD_Msk (0x3FU << SDIO_RESPCMD_RESPCMD_Pos) /*!< 0x0000003F */
+#define SDIO_RESPCMD_RESPCMD SDIO_RESPCMD_RESPCMD_Msk /*!< Response command index */
+
+/****************** Bit definition for SDIO_RESP0 register ******************/
+#define SDIO_RESP0_CARDSTATUS0_Pos (0U)
+#define SDIO_RESP0_CARDSTATUS0_Msk (0xFFFFFFFFU << SDIO_RESP0_CARDSTATUS0_Pos) /*!< 0xFFFFFFFF */
+#define SDIO_RESP0_CARDSTATUS0 SDIO_RESP0_CARDSTATUS0_Msk /*!< Card Status */
+
+/****************** Bit definition for SDIO_RESP1 register ******************/
+#define SDIO_RESP1_CARDSTATUS1_Pos (0U)
+#define SDIO_RESP1_CARDSTATUS1_Msk (0xFFFFFFFFU << SDIO_RESP1_CARDSTATUS1_Pos) /*!< 0xFFFFFFFF */
+#define SDIO_RESP1_CARDSTATUS1 SDIO_RESP1_CARDSTATUS1_Msk /*!< Card Status */
+
+/****************** Bit definition for SDIO_RESP2 register ******************/
+#define SDIO_RESP2_CARDSTATUS2_Pos (0U)
+#define SDIO_RESP2_CARDSTATUS2_Msk (0xFFFFFFFFU << SDIO_RESP2_CARDSTATUS2_Pos) /*!< 0xFFFFFFFF */
+#define SDIO_RESP2_CARDSTATUS2 SDIO_RESP2_CARDSTATUS2_Msk /*!< Card Status */
+
+/****************** Bit definition for SDIO_RESP3 register ******************/
+#define SDIO_RESP3_CARDSTATUS3_Pos (0U)
+#define SDIO_RESP3_CARDSTATUS3_Msk (0xFFFFFFFFU << SDIO_RESP3_CARDSTATUS3_Pos) /*!< 0xFFFFFFFF */
+#define SDIO_RESP3_CARDSTATUS3 SDIO_RESP3_CARDSTATUS3_Msk /*!< Card Status */
+
+/****************** Bit definition for SDIO_RESP4 register ******************/
+#define SDIO_RESP4_CARDSTATUS4_Pos (0U)
+#define SDIO_RESP4_CARDSTATUS4_Msk (0xFFFFFFFFU << SDIO_RESP4_CARDSTATUS4_Pos) /*!< 0xFFFFFFFF */
+#define SDIO_RESP4_CARDSTATUS4 SDIO_RESP4_CARDSTATUS4_Msk /*!< Card Status */
+
+/****************** Bit definition for SDIO_DTIMER register *****************/
+#define SDIO_DTIMER_DATATIME_Pos (0U)
+#define SDIO_DTIMER_DATATIME_Msk (0xFFFFFFFFU << SDIO_DTIMER_DATATIME_Pos) /*!< 0xFFFFFFFF */
+#define SDIO_DTIMER_DATATIME SDIO_DTIMER_DATATIME_Msk /*!< Data timeout period. */
+
+/****************** Bit definition for SDIO_DLEN register *******************/
+#define SDIO_DLEN_DATALENGTH_Pos (0U)
+#define SDIO_DLEN_DATALENGTH_Msk (0x1FFFFFFU << SDIO_DLEN_DATALENGTH_Pos) /*!< 0x01FFFFFF */
+#define SDIO_DLEN_DATALENGTH SDIO_DLEN_DATALENGTH_Msk /*!< Data length value */
+
+/****************** Bit definition for SDIO_DCTRL register ******************/
+#define SDIO_DCTRL_DTEN_Pos (0U)
+#define SDIO_DCTRL_DTEN_Msk (0x1U << SDIO_DCTRL_DTEN_Pos) /*!< 0x00000001 */
+#define SDIO_DCTRL_DTEN SDIO_DCTRL_DTEN_Msk /*!< Data transfer enabled bit */
+#define SDIO_DCTRL_DTDIR_Pos (1U)
+#define SDIO_DCTRL_DTDIR_Msk (0x1U << SDIO_DCTRL_DTDIR_Pos) /*!< 0x00000002 */
+#define SDIO_DCTRL_DTDIR SDIO_DCTRL_DTDIR_Msk /*!< Data transfer direction selection */
+#define SDIO_DCTRL_DTMODE_Pos (2U)
+#define SDIO_DCTRL_DTMODE_Msk (0x1U << SDIO_DCTRL_DTMODE_Pos) /*!< 0x00000004 */
+#define SDIO_DCTRL_DTMODE SDIO_DCTRL_DTMODE_Msk /*!< Data transfer mode selection */
+#define SDIO_DCTRL_DMAEN_Pos (3U)
+#define SDIO_DCTRL_DMAEN_Msk (0x1U << SDIO_DCTRL_DMAEN_Pos) /*!< 0x00000008 */
+#define SDIO_DCTRL_DMAEN SDIO_DCTRL_DMAEN_Msk /*!< DMA enabled bit */
+
+#define SDIO_DCTRL_DBLOCKSIZE_Pos (4U)
+#define SDIO_DCTRL_DBLOCKSIZE_Msk (0xFU << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x000000F0 */
+#define SDIO_DCTRL_DBLOCKSIZE SDIO_DCTRL_DBLOCKSIZE_Msk /*!< DBLOCKSIZE[3:0] bits (Data block size) */
+#define SDIO_DCTRL_DBLOCKSIZE_0 (0x1U << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0010 */
+#define SDIO_DCTRL_DBLOCKSIZE_1 (0x2U << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0020 */
+#define SDIO_DCTRL_DBLOCKSIZE_2 (0x4U << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0040 */
+#define SDIO_DCTRL_DBLOCKSIZE_3 (0x8U << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0080 */
+
+#define SDIO_DCTRL_RWSTART_Pos (8U)
+#define SDIO_DCTRL_RWSTART_Msk (0x1U << SDIO_DCTRL_RWSTART_Pos) /*!< 0x00000100 */
+#define SDIO_DCTRL_RWSTART SDIO_DCTRL_RWSTART_Msk /*!< Read wait start */
+#define SDIO_DCTRL_RWSTOP_Pos (9U)
+#define SDIO_DCTRL_RWSTOP_Msk (0x1U << SDIO_DCTRL_RWSTOP_Pos) /*!< 0x00000200 */
+#define SDIO_DCTRL_RWSTOP SDIO_DCTRL_RWSTOP_Msk /*!< Read wait stop */
+#define SDIO_DCTRL_RWMOD_Pos (10U)
+#define SDIO_DCTRL_RWMOD_Msk (0x1U << SDIO_DCTRL_RWMOD_Pos) /*!< 0x00000400 */
+#define SDIO_DCTRL_RWMOD SDIO_DCTRL_RWMOD_Msk /*!< Read wait mode */
+#define SDIO_DCTRL_SDIOEN_Pos (11U)
+#define SDIO_DCTRL_SDIOEN_Msk (0x1U << SDIO_DCTRL_SDIOEN_Pos) /*!< 0x00000800 */
+#define SDIO_DCTRL_SDIOEN SDIO_DCTRL_SDIOEN_Msk /*!< SD I/O enable functions */
+
+/****************** Bit definition for SDIO_DCOUNT register *****************/
+#define SDIO_DCOUNT_DATACOUNT_Pos (0U)
+#define SDIO_DCOUNT_DATACOUNT_Msk (0x1FFFFFFU << SDIO_DCOUNT_DATACOUNT_Pos) /*!< 0x01FFFFFF */
+#define SDIO_DCOUNT_DATACOUNT SDIO_DCOUNT_DATACOUNT_Msk /*!< Data count value */
+
+/****************** Bit definition for SDIO_STA register ********************/
+#define SDIO_STA_CCRCFAIL_Pos (0U)
+#define SDIO_STA_CCRCFAIL_Msk (0x1U << SDIO_STA_CCRCFAIL_Pos) /*!< 0x00000001 */
+#define SDIO_STA_CCRCFAIL SDIO_STA_CCRCFAIL_Msk /*!< Command response received (CRC check failed) */
+#define SDIO_STA_DCRCFAIL_Pos (1U)
+#define SDIO_STA_DCRCFAIL_Msk (0x1U << SDIO_STA_DCRCFAIL_Pos) /*!< 0x00000002 */
+#define SDIO_STA_DCRCFAIL SDIO_STA_DCRCFAIL_Msk /*!< Data block sent/received (CRC check failed) */
+#define SDIO_STA_CTIMEOUT_Pos (2U)
+#define SDIO_STA_CTIMEOUT_Msk (0x1U << SDIO_STA_CTIMEOUT_Pos) /*!< 0x00000004 */
+#define SDIO_STA_CTIMEOUT SDIO_STA_CTIMEOUT_Msk /*!< Command response timeout */
+#define SDIO_STA_DTIMEOUT_Pos (3U)
+#define SDIO_STA_DTIMEOUT_Msk (0x1U << SDIO_STA_DTIMEOUT_Pos) /*!< 0x00000008 */
+#define SDIO_STA_DTIMEOUT SDIO_STA_DTIMEOUT_Msk /*!< Data timeout */
+#define SDIO_STA_TXUNDERR_Pos (4U)
+#define SDIO_STA_TXUNDERR_Msk (0x1U << SDIO_STA_TXUNDERR_Pos) /*!< 0x00000010 */
+#define SDIO_STA_TXUNDERR SDIO_STA_TXUNDERR_Msk /*!< Transmit FIFO underrun error */
+#define SDIO_STA_RXOVERR_Pos (5U)
+#define SDIO_STA_RXOVERR_Msk (0x1U << SDIO_STA_RXOVERR_Pos) /*!< 0x00000020 */
+#define SDIO_STA_RXOVERR SDIO_STA_RXOVERR_Msk /*!< Received FIFO overrun error */
+#define SDIO_STA_CMDREND_Pos (6U)
+#define SDIO_STA_CMDREND_Msk (0x1U << SDIO_STA_CMDREND_Pos) /*!< 0x00000040 */
+#define SDIO_STA_CMDREND SDIO_STA_CMDREND_Msk /*!< Command response received (CRC check passed) */
+#define SDIO_STA_CMDSENT_Pos (7U)
+#define SDIO_STA_CMDSENT_Msk (0x1U << SDIO_STA_CMDSENT_Pos) /*!< 0x00000080 */
+#define SDIO_STA_CMDSENT SDIO_STA_CMDSENT_Msk /*!< Command sent (no response required) */
+#define SDIO_STA_DATAEND_Pos (8U)
+#define SDIO_STA_DATAEND_Msk (0x1U << SDIO_STA_DATAEND_Pos) /*!< 0x00000100 */
+#define SDIO_STA_DATAEND SDIO_STA_DATAEND_Msk /*!< Data end (data counter, SDIDCOUNT, is zero) */
+#define SDIO_STA_STBITERR_Pos (9U)
+#define SDIO_STA_STBITERR_Msk (0x1U << SDIO_STA_STBITERR_Pos) /*!< 0x00000200 */
+#define SDIO_STA_STBITERR SDIO_STA_STBITERR_Msk /*!< Start bit not detected on all data signals in wide bus mode */
+#define SDIO_STA_DBCKEND_Pos (10U)
+#define SDIO_STA_DBCKEND_Msk (0x1U << SDIO_STA_DBCKEND_Pos) /*!< 0x00000400 */
+#define SDIO_STA_DBCKEND SDIO_STA_DBCKEND_Msk /*!< Data block sent/received (CRC check passed) */
+#define SDIO_STA_CMDACT_Pos (11U)
+#define SDIO_STA_CMDACT_Msk (0x1U << SDIO_STA_CMDACT_Pos) /*!< 0x00000800 */
+#define SDIO_STA_CMDACT SDIO_STA_CMDACT_Msk /*!< Command transfer in progress */
+#define SDIO_STA_TXACT_Pos (12U)
+#define SDIO_STA_TXACT_Msk (0x1U << SDIO_STA_TXACT_Pos) /*!< 0x00001000 */
+#define SDIO_STA_TXACT SDIO_STA_TXACT_Msk /*!< Data transmit in progress */
+#define SDIO_STA_RXACT_Pos (13U)
+#define SDIO_STA_RXACT_Msk (0x1U << SDIO_STA_RXACT_Pos) /*!< 0x00002000 */
+#define SDIO_STA_RXACT SDIO_STA_RXACT_Msk /*!< Data receive in progress */
+#define SDIO_STA_TXFIFOHE_Pos (14U)
+#define SDIO_STA_TXFIFOHE_Msk (0x1U << SDIO_STA_TXFIFOHE_Pos) /*!< 0x00004000 */
+#define SDIO_STA_TXFIFOHE SDIO_STA_TXFIFOHE_Msk /*!< Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
+#define SDIO_STA_RXFIFOHF_Pos (15U)
+#define SDIO_STA_RXFIFOHF_Msk (0x1U << SDIO_STA_RXFIFOHF_Pos) /*!< 0x00008000 */
+#define SDIO_STA_RXFIFOHF SDIO_STA_RXFIFOHF_Msk /*!< Receive FIFO Half Full: there are at least 8 words in the FIFO */
+#define SDIO_STA_TXFIFOF_Pos (16U)
+#define SDIO_STA_TXFIFOF_Msk (0x1U << SDIO_STA_TXFIFOF_Pos) /*!< 0x00010000 */
+#define SDIO_STA_TXFIFOF SDIO_STA_TXFIFOF_Msk /*!< Transmit FIFO full */
+#define SDIO_STA_RXFIFOF_Pos (17U)
+#define SDIO_STA_RXFIFOF_Msk (0x1U << SDIO_STA_RXFIFOF_Pos) /*!< 0x00020000 */
+#define SDIO_STA_RXFIFOF SDIO_STA_RXFIFOF_Msk /*!< Receive FIFO full */
+#define SDIO_STA_TXFIFOE_Pos (18U)
+#define SDIO_STA_TXFIFOE_Msk (0x1U << SDIO_STA_TXFIFOE_Pos) /*!< 0x00040000 */
+#define SDIO_STA_TXFIFOE SDIO_STA_TXFIFOE_Msk /*!< Transmit FIFO empty */
+#define SDIO_STA_RXFIFOE_Pos (19U)
+#define SDIO_STA_RXFIFOE_Msk (0x1U << SDIO_STA_RXFIFOE_Pos) /*!< 0x00080000 */
+#define SDIO_STA_RXFIFOE SDIO_STA_RXFIFOE_Msk /*!< Receive FIFO empty */
+#define SDIO_STA_TXDAVL_Pos (20U)
+#define SDIO_STA_TXDAVL_Msk (0x1U << SDIO_STA_TXDAVL_Pos) /*!< 0x00100000 */
+#define SDIO_STA_TXDAVL SDIO_STA_TXDAVL_Msk /*!< Data available in transmit FIFO */
+#define SDIO_STA_RXDAVL_Pos (21U)
+#define SDIO_STA_RXDAVL_Msk (0x1U << SDIO_STA_RXDAVL_Pos) /*!< 0x00200000 */
+#define SDIO_STA_RXDAVL SDIO_STA_RXDAVL_Msk /*!< Data available in receive FIFO */
+#define SDIO_STA_SDIOIT_Pos (22U)
+#define SDIO_STA_SDIOIT_Msk (0x1U << SDIO_STA_SDIOIT_Pos) /*!< 0x00400000 */
+#define SDIO_STA_SDIOIT SDIO_STA_SDIOIT_Msk /*!< SDIO interrupt received */
+#define SDIO_STA_CEATAEND_Pos (23U)
+#define SDIO_STA_CEATAEND_Msk (0x1U << SDIO_STA_CEATAEND_Pos) /*!< 0x00800000 */
+#define SDIO_STA_CEATAEND SDIO_STA_CEATAEND_Msk /*!< CE-ATA command completion signal received for CMD61 */
+
+/******************* Bit definition for SDIO_ICR register *******************/
+#define SDIO_ICR_CCRCFAILC_Pos (0U)
+#define SDIO_ICR_CCRCFAILC_Msk (0x1U << SDIO_ICR_CCRCFAILC_Pos) /*!< 0x00000001 */
+#define SDIO_ICR_CCRCFAILC SDIO_ICR_CCRCFAILC_Msk /*!< CCRCFAIL flag clear bit */
+#define SDIO_ICR_DCRCFAILC_Pos (1U)
+#define SDIO_ICR_DCRCFAILC_Msk (0x1U << SDIO_ICR_DCRCFAILC_Pos) /*!< 0x00000002 */
+#define SDIO_ICR_DCRCFAILC SDIO_ICR_DCRCFAILC_Msk /*!< DCRCFAIL flag clear bit */
+#define SDIO_ICR_CTIMEOUTC_Pos (2U)
+#define SDIO_ICR_CTIMEOUTC_Msk (0x1U << SDIO_ICR_CTIMEOUTC_Pos) /*!< 0x00000004 */
+#define SDIO_ICR_CTIMEOUTC SDIO_ICR_CTIMEOUTC_Msk /*!< CTIMEOUT flag clear bit */
+#define SDIO_ICR_DTIMEOUTC_Pos (3U)
+#define SDIO_ICR_DTIMEOUTC_Msk (0x1U << SDIO_ICR_DTIMEOUTC_Pos) /*!< 0x00000008 */
+#define SDIO_ICR_DTIMEOUTC SDIO_ICR_DTIMEOUTC_Msk /*!< DTIMEOUT flag clear bit */
+#define SDIO_ICR_TXUNDERRC_Pos (4U)
+#define SDIO_ICR_TXUNDERRC_Msk (0x1U << SDIO_ICR_TXUNDERRC_Pos) /*!< 0x00000010 */
+#define SDIO_ICR_TXUNDERRC SDIO_ICR_TXUNDERRC_Msk /*!< TXUNDERR flag clear bit */
+#define SDIO_ICR_RXOVERRC_Pos (5U)
+#define SDIO_ICR_RXOVERRC_Msk (0x1U << SDIO_ICR_RXOVERRC_Pos) /*!< 0x00000020 */
+#define SDIO_ICR_RXOVERRC SDIO_ICR_RXOVERRC_Msk /*!< RXOVERR flag clear bit */
+#define SDIO_ICR_CMDRENDC_Pos (6U)
+#define SDIO_ICR_CMDRENDC_Msk (0x1U << SDIO_ICR_CMDRENDC_Pos) /*!< 0x00000040 */
+#define SDIO_ICR_CMDRENDC SDIO_ICR_CMDRENDC_Msk /*!< CMDREND flag clear bit */
+#define SDIO_ICR_CMDSENTC_Pos (7U)
+#define SDIO_ICR_CMDSENTC_Msk (0x1U << SDIO_ICR_CMDSENTC_Pos) /*!< 0x00000080 */
+#define SDIO_ICR_CMDSENTC SDIO_ICR_CMDSENTC_Msk /*!< CMDSENT flag clear bit */
+#define SDIO_ICR_DATAENDC_Pos (8U)
+#define SDIO_ICR_DATAENDC_Msk (0x1U << SDIO_ICR_DATAENDC_Pos) /*!< 0x00000100 */
+#define SDIO_ICR_DATAENDC SDIO_ICR_DATAENDC_Msk /*!< DATAEND flag clear bit */
+#define SDIO_ICR_STBITERRC_Pos (9U)
+#define SDIO_ICR_STBITERRC_Msk (0x1U << SDIO_ICR_STBITERRC_Pos) /*!< 0x00000200 */
+#define SDIO_ICR_STBITERRC SDIO_ICR_STBITERRC_Msk /*!< STBITERR flag clear bit */
+#define SDIO_ICR_DBCKENDC_Pos (10U)
+#define SDIO_ICR_DBCKENDC_Msk (0x1U << SDIO_ICR_DBCKENDC_Pos) /*!< 0x00000400 */
+#define SDIO_ICR_DBCKENDC SDIO_ICR_DBCKENDC_Msk /*!< DBCKEND flag clear bit */
+#define SDIO_ICR_SDIOITC_Pos (22U)
+#define SDIO_ICR_SDIOITC_Msk (0x1U << SDIO_ICR_SDIOITC_Pos) /*!< 0x00400000 */
+#define SDIO_ICR_SDIOITC SDIO_ICR_SDIOITC_Msk /*!< SDIOIT flag clear bit */
+#define SDIO_ICR_CEATAENDC_Pos (23U)
+#define SDIO_ICR_CEATAENDC_Msk (0x1U << SDIO_ICR_CEATAENDC_Pos) /*!< 0x00800000 */
+#define SDIO_ICR_CEATAENDC SDIO_ICR_CEATAENDC_Msk /*!< CEATAEND flag clear bit */
+
+/****************** Bit definition for SDIO_MASK register *******************/
+#define SDIO_MASK_CCRCFAILIE_Pos (0U)
+#define SDIO_MASK_CCRCFAILIE_Msk (0x1U << SDIO_MASK_CCRCFAILIE_Pos) /*!< 0x00000001 */
+#define SDIO_MASK_CCRCFAILIE SDIO_MASK_CCRCFAILIE_Msk /*!< Command CRC Fail Interrupt Enable */
+#define SDIO_MASK_DCRCFAILIE_Pos (1U)
+#define SDIO_MASK_DCRCFAILIE_Msk (0x1U << SDIO_MASK_DCRCFAILIE_Pos) /*!< 0x00000002 */
+#define SDIO_MASK_DCRCFAILIE SDIO_MASK_DCRCFAILIE_Msk /*!< Data CRC Fail Interrupt Enable */
+#define SDIO_MASK_CTIMEOUTIE_Pos (2U)
+#define SDIO_MASK_CTIMEOUTIE_Msk (0x1U << SDIO_MASK_CTIMEOUTIE_Pos) /*!< 0x00000004 */
+#define SDIO_MASK_CTIMEOUTIE SDIO_MASK_CTIMEOUTIE_Msk /*!< Command TimeOut Interrupt Enable */
+#define SDIO_MASK_DTIMEOUTIE_Pos (3U)
+#define SDIO_MASK_DTIMEOUTIE_Msk (0x1U << SDIO_MASK_DTIMEOUTIE_Pos) /*!< 0x00000008 */
+#define SDIO_MASK_DTIMEOUTIE SDIO_MASK_DTIMEOUTIE_Msk /*!< Data TimeOut Interrupt Enable */
+#define SDIO_MASK_TXUNDERRIE_Pos (4U)
+#define SDIO_MASK_TXUNDERRIE_Msk (0x1U << SDIO_MASK_TXUNDERRIE_Pos) /*!< 0x00000010 */
+#define SDIO_MASK_TXUNDERRIE SDIO_MASK_TXUNDERRIE_Msk /*!< Tx FIFO UnderRun Error Interrupt Enable */
+#define SDIO_MASK_RXOVERRIE_Pos (5U)
+#define SDIO_MASK_RXOVERRIE_Msk (0x1U << SDIO_MASK_RXOVERRIE_Pos) /*!< 0x00000020 */
+#define SDIO_MASK_RXOVERRIE SDIO_MASK_RXOVERRIE_Msk /*!< Rx FIFO OverRun Error Interrupt Enable */
+#define SDIO_MASK_CMDRENDIE_Pos (6U)
+#define SDIO_MASK_CMDRENDIE_Msk (0x1U << SDIO_MASK_CMDRENDIE_Pos) /*!< 0x00000040 */
+#define SDIO_MASK_CMDRENDIE SDIO_MASK_CMDRENDIE_Msk /*!< Command Response Received Interrupt Enable */
+#define SDIO_MASK_CMDSENTIE_Pos (7U)
+#define SDIO_MASK_CMDSENTIE_Msk (0x1U << SDIO_MASK_CMDSENTIE_Pos) /*!< 0x00000080 */
+#define SDIO_MASK_CMDSENTIE SDIO_MASK_CMDSENTIE_Msk /*!< Command Sent Interrupt Enable */
+#define SDIO_MASK_DATAENDIE_Pos (8U)
+#define SDIO_MASK_DATAENDIE_Msk (0x1U << SDIO_MASK_DATAENDIE_Pos) /*!< 0x00000100 */
+#define SDIO_MASK_DATAENDIE SDIO_MASK_DATAENDIE_Msk /*!< Data End Interrupt Enable */
+#define SDIO_MASK_STBITERRIE_Pos (9U)
+#define SDIO_MASK_STBITERRIE_Msk (0x1U << SDIO_MASK_STBITERRIE_Pos) /*!< 0x00000200 */
+#define SDIO_MASK_STBITERRIE SDIO_MASK_STBITERRIE_Msk /*!< Start Bit Error Interrupt Enable */
+#define SDIO_MASK_DBCKENDIE_Pos (10U)
+#define SDIO_MASK_DBCKENDIE_Msk (0x1U << SDIO_MASK_DBCKENDIE_Pos) /*!< 0x00000400 */
+#define SDIO_MASK_DBCKENDIE SDIO_MASK_DBCKENDIE_Msk /*!< Data Block End Interrupt Enable */
+#define SDIO_MASK_CMDACTIE_Pos (11U)
+#define SDIO_MASK_CMDACTIE_Msk (0x1U << SDIO_MASK_CMDACTIE_Pos) /*!< 0x00000800 */
+#define SDIO_MASK_CMDACTIE SDIO_MASK_CMDACTIE_Msk /*!< Command Acting Interrupt Enable */
+#define SDIO_MASK_TXACTIE_Pos (12U)
+#define SDIO_MASK_TXACTIE_Msk (0x1U << SDIO_MASK_TXACTIE_Pos) /*!< 0x00001000 */
+#define SDIO_MASK_TXACTIE SDIO_MASK_TXACTIE_Msk /*!< Data Transmit Acting Interrupt Enable */
+#define SDIO_MASK_RXACTIE_Pos (13U)
+#define SDIO_MASK_RXACTIE_Msk (0x1U << SDIO_MASK_RXACTIE_Pos) /*!< 0x00002000 */
+#define SDIO_MASK_RXACTIE SDIO_MASK_RXACTIE_Msk /*!< Data receive acting interrupt enabled */
+#define SDIO_MASK_TXFIFOHEIE_Pos (14U)
+#define SDIO_MASK_TXFIFOHEIE_Msk (0x1U << SDIO_MASK_TXFIFOHEIE_Pos) /*!< 0x00004000 */
+#define SDIO_MASK_TXFIFOHEIE SDIO_MASK_TXFIFOHEIE_Msk /*!< Tx FIFO Half Empty interrupt Enable */
+#define SDIO_MASK_RXFIFOHFIE_Pos (15U)
+#define SDIO_MASK_RXFIFOHFIE_Msk (0x1U << SDIO_MASK_RXFIFOHFIE_Pos) /*!< 0x00008000 */
+#define SDIO_MASK_RXFIFOHFIE SDIO_MASK_RXFIFOHFIE_Msk /*!< Rx FIFO Half Full interrupt Enable */
+#define SDIO_MASK_TXFIFOFIE_Pos (16U)
+#define SDIO_MASK_TXFIFOFIE_Msk (0x1U << SDIO_MASK_TXFIFOFIE_Pos) /*!< 0x00010000 */
+#define SDIO_MASK_TXFIFOFIE SDIO_MASK_TXFIFOFIE_Msk /*!< Tx FIFO Full interrupt Enable */
+#define SDIO_MASK_RXFIFOFIE_Pos (17U)
+#define SDIO_MASK_RXFIFOFIE_Msk (0x1U << SDIO_MASK_RXFIFOFIE_Pos) /*!< 0x00020000 */
+#define SDIO_MASK_RXFIFOFIE SDIO_MASK_RXFIFOFIE_Msk /*!< Rx FIFO Full interrupt Enable */
+#define SDIO_MASK_TXFIFOEIE_Pos (18U)
+#define SDIO_MASK_TXFIFOEIE_Msk (0x1U << SDIO_MASK_TXFIFOEIE_Pos) /*!< 0x00040000 */
+#define SDIO_MASK_TXFIFOEIE SDIO_MASK_TXFIFOEIE_Msk /*!< Tx FIFO Empty interrupt Enable */
+#define SDIO_MASK_RXFIFOEIE_Pos (19U)
+#define SDIO_MASK_RXFIFOEIE_Msk (0x1U << SDIO_MASK_RXFIFOEIE_Pos) /*!< 0x00080000 */
+#define SDIO_MASK_RXFIFOEIE SDIO_MASK_RXFIFOEIE_Msk /*!< Rx FIFO Empty interrupt Enable */
+#define SDIO_MASK_TXDAVLIE_Pos (20U)
+#define SDIO_MASK_TXDAVLIE_Msk (0x1U << SDIO_MASK_TXDAVLIE_Pos) /*!< 0x00100000 */
+#define SDIO_MASK_TXDAVLIE SDIO_MASK_TXDAVLIE_Msk /*!< Data available in Tx FIFO interrupt Enable */
+#define SDIO_MASK_RXDAVLIE_Pos (21U)
+#define SDIO_MASK_RXDAVLIE_Msk (0x1U << SDIO_MASK_RXDAVLIE_Pos) /*!< 0x00200000 */
+#define SDIO_MASK_RXDAVLIE SDIO_MASK_RXDAVLIE_Msk /*!< Data available in Rx FIFO interrupt Enable */
+#define SDIO_MASK_SDIOITIE_Pos (22U)
+#define SDIO_MASK_SDIOITIE_Msk (0x1U << SDIO_MASK_SDIOITIE_Pos) /*!< 0x00400000 */
+#define SDIO_MASK_SDIOITIE SDIO_MASK_SDIOITIE_Msk /*!< SDIO Mode Interrupt Received interrupt Enable */
+#define SDIO_MASK_CEATAENDIE_Pos (23U)
+#define SDIO_MASK_CEATAENDIE_Msk (0x1U << SDIO_MASK_CEATAENDIE_Pos) /*!< 0x00800000 */
+#define SDIO_MASK_CEATAENDIE SDIO_MASK_CEATAENDIE_Msk /*!< CE-ATA command completion signal received Interrupt Enable */
+
+/***************** Bit definition for SDIO_FIFOCNT register *****************/
+#define SDIO_FIFOCNT_FIFOCOUNT_Pos (0U)
+#define SDIO_FIFOCNT_FIFOCOUNT_Msk (0xFFFFFFU << SDIO_FIFOCNT_FIFOCOUNT_Pos) /*!< 0x00FFFFFF */
+#define SDIO_FIFOCNT_FIFOCOUNT SDIO_FIFOCNT_FIFOCOUNT_Msk /*!< Remaining number of words to be written to or read from the FIFO */
+
+/****************** Bit definition for SDIO_FIFO register *******************/
+#define SDIO_FIFO_FIFODATA_Pos (0U)
+#define SDIO_FIFO_FIFODATA_Msk (0xFFFFFFFFU << SDIO_FIFO_FIFODATA_Pos) /*!< 0xFFFFFFFF */
+#define SDIO_FIFO_FIFODATA SDIO_FIFO_FIFODATA_Msk /*!< Receive and transmit FIFO data */
+
+
+/******************************************************************************/
+/* */
+/* Controller Area Network */
+/* */
+/******************************************************************************/
+
+/*!< CAN control and status registers */
+/******************* Bit definition for CAN_MCR register ********************/
+#define CAN_MCR_INRQ_Pos (0U)
+#define CAN_MCR_INRQ_Msk (0x1U << CAN_MCR_INRQ_Pos) /*!< 0x00000001 */
+#define CAN_MCR_INRQ CAN_MCR_INRQ_Msk /*!< Initialization Request */
+#define CAN_MCR_SLEEP_Pos (1U)
+#define CAN_MCR_SLEEP_Msk (0x1U << CAN_MCR_SLEEP_Pos) /*!< 0x00000002 */
+#define CAN_MCR_SLEEP CAN_MCR_SLEEP_Msk /*!< Sleep Mode Request */
+#define CAN_MCR_TXFP_Pos (2U)
+#define CAN_MCR_TXFP_Msk (0x1U << CAN_MCR_TXFP_Pos) /*!< 0x00000004 */
+#define CAN_MCR_TXFP CAN_MCR_TXFP_Msk /*!< Transmit FIFO Priority */
+#define CAN_MCR_RFLM_Pos (3U)
+#define CAN_MCR_RFLM_Msk (0x1U << CAN_MCR_RFLM_Pos) /*!< 0x00000008 */
+#define CAN_MCR_RFLM CAN_MCR_RFLM_Msk /*!< Receive FIFO Locked Mode */
+#define CAN_MCR_NART_Pos (4U)
+#define CAN_MCR_NART_Msk (0x1U << CAN_MCR_NART_Pos) /*!< 0x00000010 */
+#define CAN_MCR_NART CAN_MCR_NART_Msk /*!< No Automatic Retransmission */
+#define CAN_MCR_AWUM_Pos (5U)
+#define CAN_MCR_AWUM_Msk (0x1U << CAN_MCR_AWUM_Pos) /*!< 0x00000020 */
+#define CAN_MCR_AWUM CAN_MCR_AWUM_Msk /*!< Automatic Wakeup Mode */
+#define CAN_MCR_ABOM_Pos (6U)
+#define CAN_MCR_ABOM_Msk (0x1U << CAN_MCR_ABOM_Pos) /*!< 0x00000040 */
+#define CAN_MCR_ABOM CAN_MCR_ABOM_Msk /*!< Automatic Bus-Off Management */
+#define CAN_MCR_TTCM_Pos (7U)
+#define CAN_MCR_TTCM_Msk (0x1U << CAN_MCR_TTCM_Pos) /*!< 0x00000080 */
+#define CAN_MCR_TTCM CAN_MCR_TTCM_Msk /*!< Time Triggered Communication Mode */
+#define CAN_MCR_RESET_Pos (15U)
+#define CAN_MCR_RESET_Msk (0x1U << CAN_MCR_RESET_Pos) /*!< 0x00008000 */
+#define CAN_MCR_RESET CAN_MCR_RESET_Msk /*!< CAN software master reset */
+#define CAN_MCR_DBF_Pos (16U)
+#define CAN_MCR_DBF_Msk (0x1U << CAN_MCR_DBF_Pos) /*!< 0x00010000 */
+#define CAN_MCR_DBF CAN_MCR_DBF_Msk /*!< CAN Debug freeze */
+
+/******************* Bit definition for CAN_MSR register ********************/
+#define CAN_MSR_INAK_Pos (0U)
+#define CAN_MSR_INAK_Msk (0x1U << CAN_MSR_INAK_Pos) /*!< 0x00000001 */
+#define CAN_MSR_INAK CAN_MSR_INAK_Msk /*!< Initialization Acknowledge */
+#define CAN_MSR_SLAK_Pos (1U)
+#define CAN_MSR_SLAK_Msk (0x1U << CAN_MSR_SLAK_Pos) /*!< 0x00000002 */
+#define CAN_MSR_SLAK CAN_MSR_SLAK_Msk /*!< Sleep Acknowledge */
+#define CAN_MSR_ERRI_Pos (2U)
+#define CAN_MSR_ERRI_Msk (0x1U << CAN_MSR_ERRI_Pos) /*!< 0x00000004 */
+#define CAN_MSR_ERRI CAN_MSR_ERRI_Msk /*!< Error Interrupt */
+#define CAN_MSR_WKUI_Pos (3U)
+#define CAN_MSR_WKUI_Msk (0x1U << CAN_MSR_WKUI_Pos) /*!< 0x00000008 */
+#define CAN_MSR_WKUI CAN_MSR_WKUI_Msk /*!< Wakeup Interrupt */
+#define CAN_MSR_SLAKI_Pos (4U)
+#define CAN_MSR_SLAKI_Msk (0x1U << CAN_MSR_SLAKI_Pos) /*!< 0x00000010 */
+#define CAN_MSR_SLAKI CAN_MSR_SLAKI_Msk /*!< Sleep Acknowledge Interrupt */
+#define CAN_MSR_TXM_Pos (8U)
+#define CAN_MSR_TXM_Msk (0x1U << CAN_MSR_TXM_Pos) /*!< 0x00000100 */
+#define CAN_MSR_TXM CAN_MSR_TXM_Msk /*!< Transmit Mode */
+#define CAN_MSR_RXM_Pos (9U)
+#define CAN_MSR_RXM_Msk (0x1U << CAN_MSR_RXM_Pos) /*!< 0x00000200 */
+#define CAN_MSR_RXM CAN_MSR_RXM_Msk /*!< Receive Mode */
+#define CAN_MSR_SAMP_Pos (10U)
+#define CAN_MSR_SAMP_Msk (0x1U << CAN_MSR_SAMP_Pos) /*!< 0x00000400 */
+#define CAN_MSR_SAMP CAN_MSR_SAMP_Msk /*!< Last Sample Point */
+#define CAN_MSR_RX_Pos (11U)
+#define CAN_MSR_RX_Msk (0x1U << CAN_MSR_RX_Pos) /*!< 0x00000800 */
+#define CAN_MSR_RX CAN_MSR_RX_Msk /*!< CAN Rx Signal */
+
+/******************* Bit definition for CAN_TSR register ********************/
+#define CAN_TSR_RQCP0_Pos (0U)
+#define CAN_TSR_RQCP0_Msk (0x1U << CAN_TSR_RQCP0_Pos) /*!< 0x00000001 */
+#define CAN_TSR_RQCP0 CAN_TSR_RQCP0_Msk /*!< Request Completed Mailbox0 */
+#define CAN_TSR_TXOK0_Pos (1U)
+#define CAN_TSR_TXOK0_Msk (0x1U << CAN_TSR_TXOK0_Pos) /*!< 0x00000002 */
+#define CAN_TSR_TXOK0 CAN_TSR_TXOK0_Msk /*!< Transmission OK of Mailbox0 */
+#define CAN_TSR_ALST0_Pos (2U)
+#define CAN_TSR_ALST0_Msk (0x1U << CAN_TSR_ALST0_Pos) /*!< 0x00000004 */
+#define CAN_TSR_ALST0 CAN_TSR_ALST0_Msk /*!< Arbitration Lost for Mailbox0 */
+#define CAN_TSR_TERR0_Pos (3U)
+#define CAN_TSR_TERR0_Msk (0x1U << CAN_TSR_TERR0_Pos) /*!< 0x00000008 */
+#define CAN_TSR_TERR0 CAN_TSR_TERR0_Msk /*!< Transmission Error of Mailbox0 */
+#define CAN_TSR_ABRQ0_Pos (7U)
+#define CAN_TSR_ABRQ0_Msk (0x1U << CAN_TSR_ABRQ0_Pos) /*!< 0x00000080 */
+#define CAN_TSR_ABRQ0 CAN_TSR_ABRQ0_Msk /*!< Abort Request for Mailbox0 */
+#define CAN_TSR_RQCP1_Pos (8U)
+#define CAN_TSR_RQCP1_Msk (0x1U << CAN_TSR_RQCP1_Pos) /*!< 0x00000100 */
+#define CAN_TSR_RQCP1 CAN_TSR_RQCP1_Msk /*!< Request Completed Mailbox1 */
+#define CAN_TSR_TXOK1_Pos (9U)
+#define CAN_TSR_TXOK1_Msk (0x1U << CAN_TSR_TXOK1_Pos) /*!< 0x00000200 */
+#define CAN_TSR_TXOK1 CAN_TSR_TXOK1_Msk /*!< Transmission OK of Mailbox1 */
+#define CAN_TSR_ALST1_Pos (10U)
+#define CAN_TSR_ALST1_Msk (0x1U << CAN_TSR_ALST1_Pos) /*!< 0x00000400 */
+#define CAN_TSR_ALST1 CAN_TSR_ALST1_Msk /*!< Arbitration Lost for Mailbox1 */
+#define CAN_TSR_TERR1_Pos (11U)
+#define CAN_TSR_TERR1_Msk (0x1U << CAN_TSR_TERR1_Pos) /*!< 0x00000800 */
+#define CAN_TSR_TERR1 CAN_TSR_TERR1_Msk /*!< Transmission Error of Mailbox1 */
+#define CAN_TSR_ABRQ1_Pos (15U)
+#define CAN_TSR_ABRQ1_Msk (0x1U << CAN_TSR_ABRQ1_Pos) /*!< 0x00008000 */
+#define CAN_TSR_ABRQ1 CAN_TSR_ABRQ1_Msk /*!< Abort Request for Mailbox 1 */
+#define CAN_TSR_RQCP2_Pos (16U)
+#define CAN_TSR_RQCP2_Msk (0x1U << CAN_TSR_RQCP2_Pos) /*!< 0x00010000 */
+#define CAN_TSR_RQCP2 CAN_TSR_RQCP2_Msk /*!< Request Completed Mailbox2 */
+#define CAN_TSR_TXOK2_Pos (17U)
+#define CAN_TSR_TXOK2_Msk (0x1U << CAN_TSR_TXOK2_Pos) /*!< 0x00020000 */
+#define CAN_TSR_TXOK2 CAN_TSR_TXOK2_Msk /*!< Transmission OK of Mailbox 2 */
+#define CAN_TSR_ALST2_Pos (18U)
+#define CAN_TSR_ALST2_Msk (0x1U << CAN_TSR_ALST2_Pos) /*!< 0x00040000 */
+#define CAN_TSR_ALST2 CAN_TSR_ALST2_Msk /*!< Arbitration Lost for mailbox 2 */
+#define CAN_TSR_TERR2_Pos (19U)
+#define CAN_TSR_TERR2_Msk (0x1U << CAN_TSR_TERR2_Pos) /*!< 0x00080000 */
+#define CAN_TSR_TERR2 CAN_TSR_TERR2_Msk /*!< Transmission Error of Mailbox 2 */
+#define CAN_TSR_ABRQ2_Pos (23U)
+#define CAN_TSR_ABRQ2_Msk (0x1U << CAN_TSR_ABRQ2_Pos) /*!< 0x00800000 */
+#define CAN_TSR_ABRQ2 CAN_TSR_ABRQ2_Msk /*!< Abort Request for Mailbox 2 */
+#define CAN_TSR_CODE_Pos (24U)
+#define CAN_TSR_CODE_Msk (0x3U << CAN_TSR_CODE_Pos) /*!< 0x03000000 */
+#define CAN_TSR_CODE CAN_TSR_CODE_Msk /*!< Mailbox Code */
+
+#define CAN_TSR_TME_Pos (26U)
+#define CAN_TSR_TME_Msk (0x7U << CAN_TSR_TME_Pos) /*!< 0x1C000000 */
+#define CAN_TSR_TME CAN_TSR_TME_Msk /*!< TME[2:0] bits */
+#define CAN_TSR_TME0_Pos (26U)
+#define CAN_TSR_TME0_Msk (0x1U << CAN_TSR_TME0_Pos) /*!< 0x04000000 */
+#define CAN_TSR_TME0 CAN_TSR_TME0_Msk /*!< Transmit Mailbox 0 Empty */
+#define CAN_TSR_TME1_Pos (27U)
+#define CAN_TSR_TME1_Msk (0x1U << CAN_TSR_TME1_Pos) /*!< 0x08000000 */
+#define CAN_TSR_TME1 CAN_TSR_TME1_Msk /*!< Transmit Mailbox 1 Empty */
+#define CAN_TSR_TME2_Pos (28U)
+#define CAN_TSR_TME2_Msk (0x1U << CAN_TSR_TME2_Pos) /*!< 0x10000000 */
+#define CAN_TSR_TME2 CAN_TSR_TME2_Msk /*!< Transmit Mailbox 2 Empty */
+
+#define CAN_TSR_LOW_Pos (29U)
+#define CAN_TSR_LOW_Msk (0x7U << CAN_TSR_LOW_Pos) /*!< 0xE0000000 */
+#define CAN_TSR_LOW CAN_TSR_LOW_Msk /*!< LOW[2:0] bits */
+#define CAN_TSR_LOW0_Pos (29U)
+#define CAN_TSR_LOW0_Msk (0x1U << CAN_TSR_LOW0_Pos) /*!< 0x20000000 */
+#define CAN_TSR_LOW0 CAN_TSR_LOW0_Msk /*!< Lowest Priority Flag for Mailbox 0 */
+#define CAN_TSR_LOW1_Pos (30U)
+#define CAN_TSR_LOW1_Msk (0x1U << CAN_TSR_LOW1_Pos) /*!< 0x40000000 */
+#define CAN_TSR_LOW1 CAN_TSR_LOW1_Msk /*!< Lowest Priority Flag for Mailbox 1 */
+#define CAN_TSR_LOW2_Pos (31U)
+#define CAN_TSR_LOW2_Msk (0x1U << CAN_TSR_LOW2_Pos) /*!< 0x80000000 */
+#define CAN_TSR_LOW2 CAN_TSR_LOW2_Msk /*!< Lowest Priority Flag for Mailbox 2 */
+
+/******************* Bit definition for CAN_RF0R register *******************/
+#define CAN_RF0R_FMP0_Pos (0U)
+#define CAN_RF0R_FMP0_Msk (0x3U << CAN_RF0R_FMP0_Pos) /*!< 0x00000003 */
+#define CAN_RF0R_FMP0 CAN_RF0R_FMP0_Msk /*!< FIFO 0 Message Pending */
+#define CAN_RF0R_FULL0_Pos (3U)
+#define CAN_RF0R_FULL0_Msk (0x1U << CAN_RF0R_FULL0_Pos) /*!< 0x00000008 */
+#define CAN_RF0R_FULL0 CAN_RF0R_FULL0_Msk /*!< FIFO 0 Full */
+#define CAN_RF0R_FOVR0_Pos (4U)
+#define CAN_RF0R_FOVR0_Msk (0x1U << CAN_RF0R_FOVR0_Pos) /*!< 0x00000010 */
+#define CAN_RF0R_FOVR0 CAN_RF0R_FOVR0_Msk /*!< FIFO 0 Overrun */
+#define CAN_RF0R_RFOM0_Pos (5U)
+#define CAN_RF0R_RFOM0_Msk (0x1U << CAN_RF0R_RFOM0_Pos) /*!< 0x00000020 */
+#define CAN_RF0R_RFOM0 CAN_RF0R_RFOM0_Msk /*!< Release FIFO 0 Output Mailbox */
+
+/******************* Bit definition for CAN_RF1R register *******************/
+#define CAN_RF1R_FMP1_Pos (0U)
+#define CAN_RF1R_FMP1_Msk (0x3U << CAN_RF1R_FMP1_Pos) /*!< 0x00000003 */
+#define CAN_RF1R_FMP1 CAN_RF1R_FMP1_Msk /*!< FIFO 1 Message Pending */
+#define CAN_RF1R_FULL1_Pos (3U)
+#define CAN_RF1R_FULL1_Msk (0x1U << CAN_RF1R_FULL1_Pos) /*!< 0x00000008 */
+#define CAN_RF1R_FULL1 CAN_RF1R_FULL1_Msk /*!< FIFO 1 Full */
+#define CAN_RF1R_FOVR1_Pos (4U)
+#define CAN_RF1R_FOVR1_Msk (0x1U << CAN_RF1R_FOVR1_Pos) /*!< 0x00000010 */
+#define CAN_RF1R_FOVR1 CAN_RF1R_FOVR1_Msk /*!< FIFO 1 Overrun */
+#define CAN_RF1R_RFOM1_Pos (5U)
+#define CAN_RF1R_RFOM1_Msk (0x1U << CAN_RF1R_RFOM1_Pos) /*!< 0x00000020 */
+#define CAN_RF1R_RFOM1 CAN_RF1R_RFOM1_Msk /*!< Release FIFO 1 Output Mailbox */
+
+/******************** Bit definition for CAN_IER register *******************/
+#define CAN_IER_TMEIE_Pos (0U)
+#define CAN_IER_TMEIE_Msk (0x1U << CAN_IER_TMEIE_Pos) /*!< 0x00000001 */
+#define CAN_IER_TMEIE CAN_IER_TMEIE_Msk /*!< Transmit Mailbox Empty Interrupt Enable */
+#define CAN_IER_FMPIE0_Pos (1U)
+#define CAN_IER_FMPIE0_Msk (0x1U << CAN_IER_FMPIE0_Pos) /*!< 0x00000002 */
+#define CAN_IER_FMPIE0 CAN_IER_FMPIE0_Msk /*!< FIFO Message Pending Interrupt Enable */
+#define CAN_IER_FFIE0_Pos (2U)
+#define CAN_IER_FFIE0_Msk (0x1U << CAN_IER_FFIE0_Pos) /*!< 0x00000004 */
+#define CAN_IER_FFIE0 CAN_IER_FFIE0_Msk /*!< FIFO Full Interrupt Enable */
+#define CAN_IER_FOVIE0_Pos (3U)
+#define CAN_IER_FOVIE0_Msk (0x1U << CAN_IER_FOVIE0_Pos) /*!< 0x00000008 */
+#define CAN_IER_FOVIE0 CAN_IER_FOVIE0_Msk /*!< FIFO Overrun Interrupt Enable */
+#define CAN_IER_FMPIE1_Pos (4U)
+#define CAN_IER_FMPIE1_Msk (0x1U << CAN_IER_FMPIE1_Pos) /*!< 0x00000010 */
+#define CAN_IER_FMPIE1 CAN_IER_FMPIE1_Msk /*!< FIFO Message Pending Interrupt Enable */
+#define CAN_IER_FFIE1_Pos (5U)
+#define CAN_IER_FFIE1_Msk (0x1U << CAN_IER_FFIE1_Pos) /*!< 0x00000020 */
+#define CAN_IER_FFIE1 CAN_IER_FFIE1_Msk /*!< FIFO Full Interrupt Enable */
+#define CAN_IER_FOVIE1_Pos (6U)
+#define CAN_IER_FOVIE1_Msk (0x1U << CAN_IER_FOVIE1_Pos) /*!< 0x00000040 */
+#define CAN_IER_FOVIE1 CAN_IER_FOVIE1_Msk /*!< FIFO Overrun Interrupt Enable */
+#define CAN_IER_EWGIE_Pos (8U)
+#define CAN_IER_EWGIE_Msk (0x1U << CAN_IER_EWGIE_Pos) /*!< 0x00000100 */
+#define CAN_IER_EWGIE CAN_IER_EWGIE_Msk /*!< Error Warning Interrupt Enable */
+#define CAN_IER_EPVIE_Pos (9U)
+#define CAN_IER_EPVIE_Msk (0x1U << CAN_IER_EPVIE_Pos) /*!< 0x00000200 */
+#define CAN_IER_EPVIE CAN_IER_EPVIE_Msk /*!< Error Passive Interrupt Enable */
+#define CAN_IER_BOFIE_Pos (10U)
+#define CAN_IER_BOFIE_Msk (0x1U << CAN_IER_BOFIE_Pos) /*!< 0x00000400 */
+#define CAN_IER_BOFIE CAN_IER_BOFIE_Msk /*!< Bus-Off Interrupt Enable */
+#define CAN_IER_LECIE_Pos (11U)
+#define CAN_IER_LECIE_Msk (0x1U << CAN_IER_LECIE_Pos) /*!< 0x00000800 */
+#define CAN_IER_LECIE CAN_IER_LECIE_Msk /*!< Last Error Code Interrupt Enable */
+#define CAN_IER_ERRIE_Pos (15U)
+#define CAN_IER_ERRIE_Msk (0x1U << CAN_IER_ERRIE_Pos) /*!< 0x00008000 */
+#define CAN_IER_ERRIE CAN_IER_ERRIE_Msk /*!< Error Interrupt Enable */
+#define CAN_IER_WKUIE_Pos (16U)
+#define CAN_IER_WKUIE_Msk (0x1U << CAN_IER_WKUIE_Pos) /*!< 0x00010000 */
+#define CAN_IER_WKUIE CAN_IER_WKUIE_Msk /*!< Wakeup Interrupt Enable */
+#define CAN_IER_SLKIE_Pos (17U)
+#define CAN_IER_SLKIE_Msk (0x1U << CAN_IER_SLKIE_Pos) /*!< 0x00020000 */
+#define CAN_IER_SLKIE CAN_IER_SLKIE_Msk /*!< Sleep Interrupt Enable */
+
+/******************** Bit definition for CAN_ESR register *******************/
+#define CAN_ESR_EWGF_Pos (0U)
+#define CAN_ESR_EWGF_Msk (0x1U << CAN_ESR_EWGF_Pos) /*!< 0x00000001 */
+#define CAN_ESR_EWGF CAN_ESR_EWGF_Msk /*!< Error Warning Flag */
+#define CAN_ESR_EPVF_Pos (1U)
+#define CAN_ESR_EPVF_Msk (0x1U << CAN_ESR_EPVF_Pos) /*!< 0x00000002 */
+#define CAN_ESR_EPVF CAN_ESR_EPVF_Msk /*!< Error Passive Flag */
+#define CAN_ESR_BOFF_Pos (2U)
+#define CAN_ESR_BOFF_Msk (0x1U << CAN_ESR_BOFF_Pos) /*!< 0x00000004 */
+#define CAN_ESR_BOFF CAN_ESR_BOFF_Msk /*!< Bus-Off Flag */
+
+#define CAN_ESR_LEC_Pos (4U)
+#define CAN_ESR_LEC_Msk (0x7U << CAN_ESR_LEC_Pos) /*!< 0x00000070 */
+#define CAN_ESR_LEC CAN_ESR_LEC_Msk /*!< LEC[2:0] bits (Last Error Code) */
+#define CAN_ESR_LEC_0 (0x1U << CAN_ESR_LEC_Pos) /*!< 0x00000010 */
+#define CAN_ESR_LEC_1 (0x2U << CAN_ESR_LEC_Pos) /*!< 0x00000020 */
+#define CAN_ESR_LEC_2 (0x4U << CAN_ESR_LEC_Pos) /*!< 0x00000040 */
+
+#define CAN_ESR_TEC_Pos (16U)
+#define CAN_ESR_TEC_Msk (0xFFU << CAN_ESR_TEC_Pos) /*!< 0x00FF0000 */
+#define CAN_ESR_TEC CAN_ESR_TEC_Msk /*!< Least significant byte of the 9-bit Transmit Error Counter */
+#define CAN_ESR_REC_Pos (24U)
+#define CAN_ESR_REC_Msk (0xFFU << CAN_ESR_REC_Pos) /*!< 0xFF000000 */
+#define CAN_ESR_REC CAN_ESR_REC_Msk /*!< Receive Error Counter */
+
+/******************* Bit definition for CAN_BTR register ********************/
+#define CAN_BTR_BRP_Pos (0U)
+#define CAN_BTR_BRP_Msk (0x3FFU << CAN_BTR_BRP_Pos) /*!< 0x000003FF */
+#define CAN_BTR_BRP CAN_BTR_BRP_Msk /*!<Baud Rate Prescaler */
+#define CAN_BTR_TS1_Pos (16U)
+#define CAN_BTR_TS1_Msk (0xFU << CAN_BTR_TS1_Pos) /*!< 0x000F0000 */
+#define CAN_BTR_TS1 CAN_BTR_TS1_Msk /*!<Time Segment 1 */
+#define CAN_BTR_TS1_0 (0x1U << CAN_BTR_TS1_Pos) /*!< 0x00010000 */
+#define CAN_BTR_TS1_1 (0x2U << CAN_BTR_TS1_Pos) /*!< 0x00020000 */
+#define CAN_BTR_TS1_2 (0x4U << CAN_BTR_TS1_Pos) /*!< 0x00040000 */
+#define CAN_BTR_TS1_3 (0x8U << CAN_BTR_TS1_Pos) /*!< 0x00080000 */
+#define CAN_BTR_TS2_Pos (20U)
+#define CAN_BTR_TS2_Msk (0x7U << CAN_BTR_TS2_Pos) /*!< 0x00700000 */
+#define CAN_BTR_TS2 CAN_BTR_TS2_Msk /*!<Time Segment 2 */
+#define CAN_BTR_TS2_0 (0x1U << CAN_BTR_TS2_Pos) /*!< 0x00100000 */
+#define CAN_BTR_TS2_1 (0x2U << CAN_BTR_TS2_Pos) /*!< 0x00200000 */
+#define CAN_BTR_TS2_2 (0x4U << CAN_BTR_TS2_Pos) /*!< 0x00400000 */
+#define CAN_BTR_SJW_Pos (24U)
+#define CAN_BTR_SJW_Msk (0x3U << CAN_BTR_SJW_Pos) /*!< 0x03000000 */
+#define CAN_BTR_SJW CAN_BTR_SJW_Msk /*!<Resynchronization Jump Width */
+#define CAN_BTR_SJW_0 (0x1U << CAN_BTR_SJW_Pos) /*!< 0x01000000 */
+#define CAN_BTR_SJW_1 (0x2U << CAN_BTR_SJW_Pos) /*!< 0x02000000 */
+#define CAN_BTR_LBKM_Pos (30U)
+#define CAN_BTR_LBKM_Msk (0x1U << CAN_BTR_LBKM_Pos) /*!< 0x40000000 */
+#define CAN_BTR_LBKM CAN_BTR_LBKM_Msk /*!<Loop Back Mode (Debug) */
+#define CAN_BTR_SILM_Pos (31U)
+#define CAN_BTR_SILM_Msk (0x1U << CAN_BTR_SILM_Pos) /*!< 0x80000000 */
+#define CAN_BTR_SILM CAN_BTR_SILM_Msk /*!<Silent Mode */
+
+/*!< Mailbox registers */
+/****************** Bit definition for CAN_TI0R register ********************/
+#define CAN_TI0R_TXRQ_Pos (0U)
+#define CAN_TI0R_TXRQ_Msk (0x1U << CAN_TI0R_TXRQ_Pos) /*!< 0x00000001 */
+#define CAN_TI0R_TXRQ CAN_TI0R_TXRQ_Msk /*!< Transmit Mailbox Request */
+#define CAN_TI0R_RTR_Pos (1U)
+#define CAN_TI0R_RTR_Msk (0x1U << CAN_TI0R_RTR_Pos) /*!< 0x00000002 */
+#define CAN_TI0R_RTR CAN_TI0R_RTR_Msk /*!< Remote Transmission Request */
+#define CAN_TI0R_IDE_Pos (2U)
+#define CAN_TI0R_IDE_Msk (0x1U << CAN_TI0R_IDE_Pos) /*!< 0x00000004 */
+#define CAN_TI0R_IDE CAN_TI0R_IDE_Msk /*!< Identifier Extension */
+#define CAN_TI0R_EXID_Pos (3U)
+#define CAN_TI0R_EXID_Msk (0x3FFFFU << CAN_TI0R_EXID_Pos) /*!< 0x001FFFF8 */
+#define CAN_TI0R_EXID CAN_TI0R_EXID_Msk /*!< Extended Identifier */
+#define CAN_TI0R_STID_Pos (21U)
+#define CAN_TI0R_STID_Msk (0x7FFU << CAN_TI0R_STID_Pos) /*!< 0xFFE00000 */
+#define CAN_TI0R_STID CAN_TI0R_STID_Msk /*!< Standard Identifier or Extended Identifier */
+
+/****************** Bit definition for CAN_TDT0R register *******************/
+#define CAN_TDT0R_DLC_Pos (0U)
+#define CAN_TDT0R_DLC_Msk (0xFU << CAN_TDT0R_DLC_Pos) /*!< 0x0000000F */
+#define CAN_TDT0R_DLC CAN_TDT0R_DLC_Msk /*!< Data Length Code */
+#define CAN_TDT0R_TGT_Pos (8U)
+#define CAN_TDT0R_TGT_Msk (0x1U << CAN_TDT0R_TGT_Pos) /*!< 0x00000100 */
+#define CAN_TDT0R_TGT CAN_TDT0R_TGT_Msk /*!< Transmit Global Time */
+#define CAN_TDT0R_TIME_Pos (16U)
+#define CAN_TDT0R_TIME_Msk (0xFFFFU << CAN_TDT0R_TIME_Pos) /*!< 0xFFFF0000 */
+#define CAN_TDT0R_TIME CAN_TDT0R_TIME_Msk /*!< Message Time Stamp */
+
+/****************** Bit definition for CAN_TDL0R register *******************/
+#define CAN_TDL0R_DATA0_Pos (0U)
+#define CAN_TDL0R_DATA0_Msk (0xFFU << CAN_TDL0R_DATA0_Pos) /*!< 0x000000FF */
+#define CAN_TDL0R_DATA0 CAN_TDL0R_DATA0_Msk /*!< Data byte 0 */
+#define CAN_TDL0R_DATA1_Pos (8U)
+#define CAN_TDL0R_DATA1_Msk (0xFFU << CAN_TDL0R_DATA1_Pos) /*!< 0x0000FF00 */
+#define CAN_TDL0R_DATA1 CAN_TDL0R_DATA1_Msk /*!< Data byte 1 */
+#define CAN_TDL0R_DATA2_Pos (16U)
+#define CAN_TDL0R_DATA2_Msk (0xFFU << CAN_TDL0R_DATA2_Pos) /*!< 0x00FF0000 */
+#define CAN_TDL0R_DATA2 CAN_TDL0R_DATA2_Msk /*!< Data byte 2 */
+#define CAN_TDL0R_DATA3_Pos (24U)
+#define CAN_TDL0R_DATA3_Msk (0xFFU << CAN_TDL0R_DATA3_Pos) /*!< 0xFF000000 */
+#define CAN_TDL0R_DATA3 CAN_TDL0R_DATA3_Msk /*!< Data byte 3 */
+
+/****************** Bit definition for CAN_TDH0R register *******************/
+#define CAN_TDH0R_DATA4_Pos (0U)
+#define CAN_TDH0R_DATA4_Msk (0xFFU << CAN_TDH0R_DATA4_Pos) /*!< 0x000000FF */
+#define CAN_TDH0R_DATA4 CAN_TDH0R_DATA4_Msk /*!< Data byte 4 */
+#define CAN_TDH0R_DATA5_Pos (8U)
+#define CAN_TDH0R_DATA5_Msk (0xFFU << CAN_TDH0R_DATA5_Pos) /*!< 0x0000FF00 */
+#define CAN_TDH0R_DATA5 CAN_TDH0R_DATA5_Msk /*!< Data byte 5 */
+#define CAN_TDH0R_DATA6_Pos (16U)
+#define CAN_TDH0R_DATA6_Msk (0xFFU << CAN_TDH0R_DATA6_Pos) /*!< 0x00FF0000 */
+#define CAN_TDH0R_DATA6 CAN_TDH0R_DATA6_Msk /*!< Data byte 6 */
+#define CAN_TDH0R_DATA7_Pos (24U)
+#define CAN_TDH0R_DATA7_Msk (0xFFU << CAN_TDH0R_DATA7_Pos) /*!< 0xFF000000 */
+#define CAN_TDH0R_DATA7 CAN_TDH0R_DATA7_Msk /*!< Data byte 7 */
+
+/******************* Bit definition for CAN_TI1R register *******************/
+#define CAN_TI1R_TXRQ_Pos (0U)
+#define CAN_TI1R_TXRQ_Msk (0x1U << CAN_TI1R_TXRQ_Pos) /*!< 0x00000001 */
+#define CAN_TI1R_TXRQ CAN_TI1R_TXRQ_Msk /*!< Transmit Mailbox Request */
+#define CAN_TI1R_RTR_Pos (1U)
+#define CAN_TI1R_RTR_Msk (0x1U << CAN_TI1R_RTR_Pos) /*!< 0x00000002 */
+#define CAN_TI1R_RTR CAN_TI1R_RTR_Msk /*!< Remote Transmission Request */
+#define CAN_TI1R_IDE_Pos (2U)
+#define CAN_TI1R_IDE_Msk (0x1U << CAN_TI1R_IDE_Pos) /*!< 0x00000004 */
+#define CAN_TI1R_IDE CAN_TI1R_IDE_Msk /*!< Identifier Extension */
+#define CAN_TI1R_EXID_Pos (3U)
+#define CAN_TI1R_EXID_Msk (0x3FFFFU << CAN_TI1R_EXID_Pos) /*!< 0x001FFFF8 */
+#define CAN_TI1R_EXID CAN_TI1R_EXID_Msk /*!< Extended Identifier */
+#define CAN_TI1R_STID_Pos (21U)
+#define CAN_TI1R_STID_Msk (0x7FFU << CAN_TI1R_STID_Pos) /*!< 0xFFE00000 */
+#define CAN_TI1R_STID CAN_TI1R_STID_Msk /*!< Standard Identifier or Extended Identifier */
+
+/******************* Bit definition for CAN_TDT1R register ******************/
+#define CAN_TDT1R_DLC_Pos (0U)
+#define CAN_TDT1R_DLC_Msk (0xFU << CAN_TDT1R_DLC_Pos) /*!< 0x0000000F */
+#define CAN_TDT1R_DLC CAN_TDT1R_DLC_Msk /*!< Data Length Code */
+#define CAN_TDT1R_TGT_Pos (8U)
+#define CAN_TDT1R_TGT_Msk (0x1U << CAN_TDT1R_TGT_Pos) /*!< 0x00000100 */
+#define CAN_TDT1R_TGT CAN_TDT1R_TGT_Msk /*!< Transmit Global Time */
+#define CAN_TDT1R_TIME_Pos (16U)
+#define CAN_TDT1R_TIME_Msk (0xFFFFU << CAN_TDT1R_TIME_Pos) /*!< 0xFFFF0000 */
+#define CAN_TDT1R_TIME CAN_TDT1R_TIME_Msk /*!< Message Time Stamp */
+
+/******************* Bit definition for CAN_TDL1R register ******************/
+#define CAN_TDL1R_DATA0_Pos (0U)
+#define CAN_TDL1R_DATA0_Msk (0xFFU << CAN_TDL1R_DATA0_Pos) /*!< 0x000000FF */
+#define CAN_TDL1R_DATA0 CAN_TDL1R_DATA0_Msk /*!< Data byte 0 */
+#define CAN_TDL1R_DATA1_Pos (8U)
+#define CAN_TDL1R_DATA1_Msk (0xFFU << CAN_TDL1R_DATA1_Pos) /*!< 0x0000FF00 */
+#define CAN_TDL1R_DATA1 CAN_TDL1R_DATA1_Msk /*!< Data byte 1 */
+#define CAN_TDL1R_DATA2_Pos (16U)
+#define CAN_TDL1R_DATA2_Msk (0xFFU << CAN_TDL1R_DATA2_Pos) /*!< 0x00FF0000 */
+#define CAN_TDL1R_DATA2 CAN_TDL1R_DATA2_Msk /*!< Data byte 2 */
+#define CAN_TDL1R_DATA3_Pos (24U)
+#define CAN_TDL1R_DATA3_Msk (0xFFU << CAN_TDL1R_DATA3_Pos) /*!< 0xFF000000 */
+#define CAN_TDL1R_DATA3 CAN_TDL1R_DATA3_Msk /*!< Data byte 3 */
+
+/******************* Bit definition for CAN_TDH1R register ******************/
+#define CAN_TDH1R_DATA4_Pos (0U)
+#define CAN_TDH1R_DATA4_Msk (0xFFU << CAN_TDH1R_DATA4_Pos) /*!< 0x000000FF */
+#define CAN_TDH1R_DATA4 CAN_TDH1R_DATA4_Msk /*!< Data byte 4 */
+#define CAN_TDH1R_DATA5_Pos (8U)
+#define CAN_TDH1R_DATA5_Msk (0xFFU << CAN_TDH1R_DATA5_Pos) /*!< 0x0000FF00 */
+#define CAN_TDH1R_DATA5 CAN_TDH1R_DATA5_Msk /*!< Data byte 5 */
+#define CAN_TDH1R_DATA6_Pos (16U)
+#define CAN_TDH1R_DATA6_Msk (0xFFU << CAN_TDH1R_DATA6_Pos) /*!< 0x00FF0000 */
+#define CAN_TDH1R_DATA6 CAN_TDH1R_DATA6_Msk /*!< Data byte 6 */
+#define CAN_TDH1R_DATA7_Pos (24U)
+#define CAN_TDH1R_DATA7_Msk (0xFFU << CAN_TDH1R_DATA7_Pos) /*!< 0xFF000000 */
+#define CAN_TDH1R_DATA7 CAN_TDH1R_DATA7_Msk /*!< Data byte 7 */
+
+/******************* Bit definition for CAN_TI2R register *******************/
+#define CAN_TI2R_TXRQ_Pos (0U)
+#define CAN_TI2R_TXRQ_Msk (0x1U << CAN_TI2R_TXRQ_Pos) /*!< 0x00000001 */
+#define CAN_TI2R_TXRQ CAN_TI2R_TXRQ_Msk /*!< Transmit Mailbox Request */
+#define CAN_TI2R_RTR_Pos (1U)
+#define CAN_TI2R_RTR_Msk (0x1U << CAN_TI2R_RTR_Pos) /*!< 0x00000002 */
+#define CAN_TI2R_RTR CAN_TI2R_RTR_Msk /*!< Remote Transmission Request */
+#define CAN_TI2R_IDE_Pos (2U)
+#define CAN_TI2R_IDE_Msk (0x1U << CAN_TI2R_IDE_Pos) /*!< 0x00000004 */
+#define CAN_TI2R_IDE CAN_TI2R_IDE_Msk /*!< Identifier Extension */
+#define CAN_TI2R_EXID_Pos (3U)
+#define CAN_TI2R_EXID_Msk (0x3FFFFU << CAN_TI2R_EXID_Pos) /*!< 0x001FFFF8 */
+#define CAN_TI2R_EXID CAN_TI2R_EXID_Msk /*!< Extended identifier */
+#define CAN_TI2R_STID_Pos (21U)
+#define CAN_TI2R_STID_Msk (0x7FFU << CAN_TI2R_STID_Pos) /*!< 0xFFE00000 */
+#define CAN_TI2R_STID CAN_TI2R_STID_Msk /*!< Standard Identifier or Extended Identifier */
+
+/******************* Bit definition for CAN_TDT2R register ******************/
+#define CAN_TDT2R_DLC_Pos (0U)
+#define CAN_TDT2R_DLC_Msk (0xFU << CAN_TDT2R_DLC_Pos) /*!< 0x0000000F */
+#define CAN_TDT2R_DLC CAN_TDT2R_DLC_Msk /*!< Data Length Code */
+#define CAN_TDT2R_TGT_Pos (8U)
+#define CAN_TDT2R_TGT_Msk (0x1U << CAN_TDT2R_TGT_Pos) /*!< 0x00000100 */
+#define CAN_TDT2R_TGT CAN_TDT2R_TGT_Msk /*!< Transmit Global Time */
+#define CAN_TDT2R_TIME_Pos (16U)
+#define CAN_TDT2R_TIME_Msk (0xFFFFU << CAN_TDT2R_TIME_Pos) /*!< 0xFFFF0000 */
+#define CAN_TDT2R_TIME CAN_TDT2R_TIME_Msk /*!< Message Time Stamp */
+
+/******************* Bit definition for CAN_TDL2R register ******************/
+#define CAN_TDL2R_DATA0_Pos (0U)
+#define CAN_TDL2R_DATA0_Msk (0xFFU << CAN_TDL2R_DATA0_Pos) /*!< 0x000000FF */
+#define CAN_TDL2R_DATA0 CAN_TDL2R_DATA0_Msk /*!< Data byte 0 */
+#define CAN_TDL2R_DATA1_Pos (8U)
+#define CAN_TDL2R_DATA1_Msk (0xFFU << CAN_TDL2R_DATA1_Pos) /*!< 0x0000FF00 */
+#define CAN_TDL2R_DATA1 CAN_TDL2R_DATA1_Msk /*!< Data byte 1 */
+#define CAN_TDL2R_DATA2_Pos (16U)
+#define CAN_TDL2R_DATA2_Msk (0xFFU << CAN_TDL2R_DATA2_Pos) /*!< 0x00FF0000 */
+#define CAN_TDL2R_DATA2 CAN_TDL2R_DATA2_Msk /*!< Data byte 2 */
+#define CAN_TDL2R_DATA3_Pos (24U)
+#define CAN_TDL2R_DATA3_Msk (0xFFU << CAN_TDL2R_DATA3_Pos) /*!< 0xFF000000 */
+#define CAN_TDL2R_DATA3 CAN_TDL2R_DATA3_Msk /*!< Data byte 3 */
+
+/******************* Bit definition for CAN_TDH2R register ******************/
+#define CAN_TDH2R_DATA4_Pos (0U)
+#define CAN_TDH2R_DATA4_Msk (0xFFU << CAN_TDH2R_DATA4_Pos) /*!< 0x000000FF */
+#define CAN_TDH2R_DATA4 CAN_TDH2R_DATA4_Msk /*!< Data byte 4 */
+#define CAN_TDH2R_DATA5_Pos (8U)
+#define CAN_TDH2R_DATA5_Msk (0xFFU << CAN_TDH2R_DATA5_Pos) /*!< 0x0000FF00 */
+#define CAN_TDH2R_DATA5 CAN_TDH2R_DATA5_Msk /*!< Data byte 5 */
+#define CAN_TDH2R_DATA6_Pos (16U)
+#define CAN_TDH2R_DATA6_Msk (0xFFU << CAN_TDH2R_DATA6_Pos) /*!< 0x00FF0000 */
+#define CAN_TDH2R_DATA6 CAN_TDH2R_DATA6_Msk /*!< Data byte 6 */
+#define CAN_TDH2R_DATA7_Pos (24U)
+#define CAN_TDH2R_DATA7_Msk (0xFFU << CAN_TDH2R_DATA7_Pos) /*!< 0xFF000000 */
+#define CAN_TDH2R_DATA7 CAN_TDH2R_DATA7_Msk /*!< Data byte 7 */
+
+/******************* Bit definition for CAN_RI0R register *******************/
+#define CAN_RI0R_RTR_Pos (1U)
+#define CAN_RI0R_RTR_Msk (0x1U << CAN_RI0R_RTR_Pos) /*!< 0x00000002 */
+#define CAN_RI0R_RTR CAN_RI0R_RTR_Msk /*!< Remote Transmission Request */
+#define CAN_RI0R_IDE_Pos (2U)
+#define CAN_RI0R_IDE_Msk (0x1U << CAN_RI0R_IDE_Pos) /*!< 0x00000004 */
+#define CAN_RI0R_IDE CAN_RI0R_IDE_Msk /*!< Identifier Extension */
+#define CAN_RI0R_EXID_Pos (3U)
+#define CAN_RI0R_EXID_Msk (0x3FFFFU << CAN_RI0R_EXID_Pos) /*!< 0x001FFFF8 */
+#define CAN_RI0R_EXID CAN_RI0R_EXID_Msk /*!< Extended Identifier */
+#define CAN_RI0R_STID_Pos (21U)
+#define CAN_RI0R_STID_Msk (0x7FFU << CAN_RI0R_STID_Pos) /*!< 0xFFE00000 */
+#define CAN_RI0R_STID CAN_RI0R_STID_Msk /*!< Standard Identifier or Extended Identifier */
+
+/******************* Bit definition for CAN_RDT0R register ******************/
+#define CAN_RDT0R_DLC_Pos (0U)
+#define CAN_RDT0R_DLC_Msk (0xFU << CAN_RDT0R_DLC_Pos) /*!< 0x0000000F */
+#define CAN_RDT0R_DLC CAN_RDT0R_DLC_Msk /*!< Data Length Code */
+#define CAN_RDT0R_FMI_Pos (8U)
+#define CAN_RDT0R_FMI_Msk (0xFFU << CAN_RDT0R_FMI_Pos) /*!< 0x0000FF00 */
+#define CAN_RDT0R_FMI CAN_RDT0R_FMI_Msk /*!< Filter Match Index */
+#define CAN_RDT0R_TIME_Pos (16U)
+#define CAN_RDT0R_TIME_Msk (0xFFFFU << CAN_RDT0R_TIME_Pos) /*!< 0xFFFF0000 */
+#define CAN_RDT0R_TIME CAN_RDT0R_TIME_Msk /*!< Message Time Stamp */
+
+/******************* Bit definition for CAN_RDL0R register ******************/
+#define CAN_RDL0R_DATA0_Pos (0U)
+#define CAN_RDL0R_DATA0_Msk (0xFFU << CAN_RDL0R_DATA0_Pos) /*!< 0x000000FF */
+#define CAN_RDL0R_DATA0 CAN_RDL0R_DATA0_Msk /*!< Data byte 0 */
+#define CAN_RDL0R_DATA1_Pos (8U)
+#define CAN_RDL0R_DATA1_Msk (0xFFU << CAN_RDL0R_DATA1_Pos) /*!< 0x0000FF00 */
+#define CAN_RDL0R_DATA1 CAN_RDL0R_DATA1_Msk /*!< Data byte 1 */
+#define CAN_RDL0R_DATA2_Pos (16U)
+#define CAN_RDL0R_DATA2_Msk (0xFFU << CAN_RDL0R_DATA2_Pos) /*!< 0x00FF0000 */
+#define CAN_RDL0R_DATA2 CAN_RDL0R_DATA2_Msk /*!< Data byte 2 */
+#define CAN_RDL0R_DATA3_Pos (24U)
+#define CAN_RDL0R_DATA3_Msk (0xFFU << CAN_RDL0R_DATA3_Pos) /*!< 0xFF000000 */
+#define CAN_RDL0R_DATA3 CAN_RDL0R_DATA3_Msk /*!< Data byte 3 */
+
+/******************* Bit definition for CAN_RDH0R register ******************/
+#define CAN_RDH0R_DATA4_Pos (0U)
+#define CAN_RDH0R_DATA4_Msk (0xFFU << CAN_RDH0R_DATA4_Pos) /*!< 0x000000FF */
+#define CAN_RDH0R_DATA4 CAN_RDH0R_DATA4_Msk /*!< Data byte 4 */
+#define CAN_RDH0R_DATA5_Pos (8U)
+#define CAN_RDH0R_DATA5_Msk (0xFFU << CAN_RDH0R_DATA5_Pos) /*!< 0x0000FF00 */
+#define CAN_RDH0R_DATA5 CAN_RDH0R_DATA5_Msk /*!< Data byte 5 */
+#define CAN_RDH0R_DATA6_Pos (16U)
+#define CAN_RDH0R_DATA6_Msk (0xFFU << CAN_RDH0R_DATA6_Pos) /*!< 0x00FF0000 */
+#define CAN_RDH0R_DATA6 CAN_RDH0R_DATA6_Msk /*!< Data byte 6 */
+#define CAN_RDH0R_DATA7_Pos (24U)
+#define CAN_RDH0R_DATA7_Msk (0xFFU << CAN_RDH0R_DATA7_Pos) /*!< 0xFF000000 */
+#define CAN_RDH0R_DATA7 CAN_RDH0R_DATA7_Msk /*!< Data byte 7 */
+
+/******************* Bit definition for CAN_RI1R register *******************/
+#define CAN_RI1R_RTR_Pos (1U)
+#define CAN_RI1R_RTR_Msk (0x1U << CAN_RI1R_RTR_Pos) /*!< 0x00000002 */
+#define CAN_RI1R_RTR CAN_RI1R_RTR_Msk /*!< Remote Transmission Request */
+#define CAN_RI1R_IDE_Pos (2U)
+#define CAN_RI1R_IDE_Msk (0x1U << CAN_RI1R_IDE_Pos) /*!< 0x00000004 */
+#define CAN_RI1R_IDE CAN_RI1R_IDE_Msk /*!< Identifier Extension */
+#define CAN_RI1R_EXID_Pos (3U)
+#define CAN_RI1R_EXID_Msk (0x3FFFFU << CAN_RI1R_EXID_Pos) /*!< 0x001FFFF8 */
+#define CAN_RI1R_EXID CAN_RI1R_EXID_Msk /*!< Extended identifier */
+#define CAN_RI1R_STID_Pos (21U)
+#define CAN_RI1R_STID_Msk (0x7FFU << CAN_RI1R_STID_Pos) /*!< 0xFFE00000 */
+#define CAN_RI1R_STID CAN_RI1R_STID_Msk /*!< Standard Identifier or Extended Identifier */
+
+/******************* Bit definition for CAN_RDT1R register ******************/
+#define CAN_RDT1R_DLC_Pos (0U)
+#define CAN_RDT1R_DLC_Msk (0xFU << CAN_RDT1R_DLC_Pos) /*!< 0x0000000F */
+#define CAN_RDT1R_DLC CAN_RDT1R_DLC_Msk /*!< Data Length Code */
+#define CAN_RDT1R_FMI_Pos (8U)
+#define CAN_RDT1R_FMI_Msk (0xFFU << CAN_RDT1R_FMI_Pos) /*!< 0x0000FF00 */
+#define CAN_RDT1R_FMI CAN_RDT1R_FMI_Msk /*!< Filter Match Index */
+#define CAN_RDT1R_TIME_Pos (16U)
+#define CAN_RDT1R_TIME_Msk (0xFFFFU << CAN_RDT1R_TIME_Pos) /*!< 0xFFFF0000 */
+#define CAN_RDT1R_TIME CAN_RDT1R_TIME_Msk /*!< Message Time Stamp */
+
+/******************* Bit definition for CAN_RDL1R register ******************/
+#define CAN_RDL1R_DATA0_Pos (0U)
+#define CAN_RDL1R_DATA0_Msk (0xFFU << CAN_RDL1R_DATA0_Pos) /*!< 0x000000FF */
+#define CAN_RDL1R_DATA0 CAN_RDL1R_DATA0_Msk /*!< Data byte 0 */
+#define CAN_RDL1R_DATA1_Pos (8U)
+#define CAN_RDL1R_DATA1_Msk (0xFFU << CAN_RDL1R_DATA1_Pos) /*!< 0x0000FF00 */
+#define CAN_RDL1R_DATA1 CAN_RDL1R_DATA1_Msk /*!< Data byte 1 */
+#define CAN_RDL1R_DATA2_Pos (16U)
+#define CAN_RDL1R_DATA2_Msk (0xFFU << CAN_RDL1R_DATA2_Pos) /*!< 0x00FF0000 */
+#define CAN_RDL1R_DATA2 CAN_RDL1R_DATA2_Msk /*!< Data byte 2 */
+#define CAN_RDL1R_DATA3_Pos (24U)
+#define CAN_RDL1R_DATA3_Msk (0xFFU << CAN_RDL1R_DATA3_Pos) /*!< 0xFF000000 */
+#define CAN_RDL1R_DATA3 CAN_RDL1R_DATA3_Msk /*!< Data byte 3 */
+
+/******************* Bit definition for CAN_RDH1R register ******************/
+#define CAN_RDH1R_DATA4_Pos (0U)
+#define CAN_RDH1R_DATA4_Msk (0xFFU << CAN_RDH1R_DATA4_Pos) /*!< 0x000000FF */
+#define CAN_RDH1R_DATA4 CAN_RDH1R_DATA4_Msk /*!< Data byte 4 */
+#define CAN_RDH1R_DATA5_Pos (8U)
+#define CAN_RDH1R_DATA5_Msk (0xFFU << CAN_RDH1R_DATA5_Pos) /*!< 0x0000FF00 */
+#define CAN_RDH1R_DATA5 CAN_RDH1R_DATA5_Msk /*!< Data byte 5 */
+#define CAN_RDH1R_DATA6_Pos (16U)
+#define CAN_RDH1R_DATA6_Msk (0xFFU << CAN_RDH1R_DATA6_Pos) /*!< 0x00FF0000 */
+#define CAN_RDH1R_DATA6 CAN_RDH1R_DATA6_Msk /*!< Data byte 6 */
+#define CAN_RDH1R_DATA7_Pos (24U)
+#define CAN_RDH1R_DATA7_Msk (0xFFU << CAN_RDH1R_DATA7_Pos) /*!< 0xFF000000 */
+#define CAN_RDH1R_DATA7 CAN_RDH1R_DATA7_Msk /*!< Data byte 7 */
+
+/*!< CAN filter registers */
+/******************* Bit definition for CAN_FMR register ********************/
+#define CAN_FMR_FINIT_Pos (0U)
+#define CAN_FMR_FINIT_Msk (0x1U << CAN_FMR_FINIT_Pos) /*!< 0x00000001 */
+#define CAN_FMR_FINIT CAN_FMR_FINIT_Msk /*!< Filter Init Mode */
+#define CAN_FMR_CAN2SB_Pos (8U)
+#define CAN_FMR_CAN2SB_Msk (0x3FU << CAN_FMR_CAN2SB_Pos) /*!< 0x00003F00 */
+#define CAN_FMR_CAN2SB CAN_FMR_CAN2SB_Msk /*!< CAN2 start bank */
+
+/******************* Bit definition for CAN_FM1R register *******************/
+#define CAN_FM1R_FBM_Pos (0U)
+#define CAN_FM1R_FBM_Msk (0x3FFFU << CAN_FM1R_FBM_Pos) /*!< 0x00003FFF */
+#define CAN_FM1R_FBM CAN_FM1R_FBM_Msk /*!< Filter Mode */
+#define CAN_FM1R_FBM0_Pos (0U)
+#define CAN_FM1R_FBM0_Msk (0x1U << CAN_FM1R_FBM0_Pos) /*!< 0x00000001 */
+#define CAN_FM1R_FBM0 CAN_FM1R_FBM0_Msk /*!< Filter Init Mode for filter 0 */
+#define CAN_FM1R_FBM1_Pos (1U)
+#define CAN_FM1R_FBM1_Msk (0x1U << CAN_FM1R_FBM1_Pos) /*!< 0x00000002 */
+#define CAN_FM1R_FBM1 CAN_FM1R_FBM1_Msk /*!< Filter Init Mode for filter 1 */
+#define CAN_FM1R_FBM2_Pos (2U)
+#define CAN_FM1R_FBM2_Msk (0x1U << CAN_FM1R_FBM2_Pos) /*!< 0x00000004 */
+#define CAN_FM1R_FBM2 CAN_FM1R_FBM2_Msk /*!< Filter Init Mode for filter 2 */
+#define CAN_FM1R_FBM3_Pos (3U)
+#define CAN_FM1R_FBM3_Msk (0x1U << CAN_FM1R_FBM3_Pos) /*!< 0x00000008 */
+#define CAN_FM1R_FBM3 CAN_FM1R_FBM3_Msk /*!< Filter Init Mode for filter 3 */
+#define CAN_FM1R_FBM4_Pos (4U)
+#define CAN_FM1R_FBM4_Msk (0x1U << CAN_FM1R_FBM4_Pos) /*!< 0x00000010 */
+#define CAN_FM1R_FBM4 CAN_FM1R_FBM4_Msk /*!< Filter Init Mode for filter 4 */
+#define CAN_FM1R_FBM5_Pos (5U)
+#define CAN_FM1R_FBM5_Msk (0x1U << CAN_FM1R_FBM5_Pos) /*!< 0x00000020 */
+#define CAN_FM1R_FBM5 CAN_FM1R_FBM5_Msk /*!< Filter Init Mode for filter 5 */
+#define CAN_FM1R_FBM6_Pos (6U)
+#define CAN_FM1R_FBM6_Msk (0x1U << CAN_FM1R_FBM6_Pos) /*!< 0x00000040 */
+#define CAN_FM1R_FBM6 CAN_FM1R_FBM6_Msk /*!< Filter Init Mode for filter 6 */
+#define CAN_FM1R_FBM7_Pos (7U)
+#define CAN_FM1R_FBM7_Msk (0x1U << CAN_FM1R_FBM7_Pos) /*!< 0x00000080 */
+#define CAN_FM1R_FBM7 CAN_FM1R_FBM7_Msk /*!< Filter Init Mode for filter 7 */
+#define CAN_FM1R_FBM8_Pos (8U)
+#define CAN_FM1R_FBM8_Msk (0x1U << CAN_FM1R_FBM8_Pos) /*!< 0x00000100 */
+#define CAN_FM1R_FBM8 CAN_FM1R_FBM8_Msk /*!< Filter Init Mode for filter 8 */
+#define CAN_FM1R_FBM9_Pos (9U)
+#define CAN_FM1R_FBM9_Msk (0x1U << CAN_FM1R_FBM9_Pos) /*!< 0x00000200 */
+#define CAN_FM1R_FBM9 CAN_FM1R_FBM9_Msk /*!< Filter Init Mode for filter 9 */
+#define CAN_FM1R_FBM10_Pos (10U)
+#define CAN_FM1R_FBM10_Msk (0x1U << CAN_FM1R_FBM10_Pos) /*!< 0x00000400 */
+#define CAN_FM1R_FBM10 CAN_FM1R_FBM10_Msk /*!< Filter Init Mode for filter 10 */
+#define CAN_FM1R_FBM11_Pos (11U)
+#define CAN_FM1R_FBM11_Msk (0x1U << CAN_FM1R_FBM11_Pos) /*!< 0x00000800 */
+#define CAN_FM1R_FBM11 CAN_FM1R_FBM11_Msk /*!< Filter Init Mode for filter 11 */
+#define CAN_FM1R_FBM12_Pos (12U)
+#define CAN_FM1R_FBM12_Msk (0x1U << CAN_FM1R_FBM12_Pos) /*!< 0x00001000 */
+#define CAN_FM1R_FBM12 CAN_FM1R_FBM12_Msk /*!< Filter Init Mode for filter 12 */
+#define CAN_FM1R_FBM13_Pos (13U)
+#define CAN_FM1R_FBM13_Msk (0x1U << CAN_FM1R_FBM13_Pos) /*!< 0x00002000 */
+#define CAN_FM1R_FBM13 CAN_FM1R_FBM13_Msk /*!< Filter Init Mode for filter 13 */
+#define CAN_FM1R_FBM14_Pos (14U)
+#define CAN_FM1R_FBM14_Msk (0x1U << CAN_FM1R_FBM14_Pos) /*!< 0x00004000 */
+#define CAN_FM1R_FBM14 CAN_FM1R_FBM14_Msk /*!< Filter Init Mode for filter 14 */
+#define CAN_FM1R_FBM15_Pos (15U)
+#define CAN_FM1R_FBM15_Msk (0x1U << CAN_FM1R_FBM15_Pos) /*!< 0x00008000 */
+#define CAN_FM1R_FBM15 CAN_FM1R_FBM15_Msk /*!< Filter Init Mode for filter 15 */
+#define CAN_FM1R_FBM16_Pos (16U)
+#define CAN_FM1R_FBM16_Msk (0x1U << CAN_FM1R_FBM16_Pos) /*!< 0x00010000 */
+#define CAN_FM1R_FBM16 CAN_FM1R_FBM16_Msk /*!< Filter Init Mode for filter 16 */
+#define CAN_FM1R_FBM17_Pos (17U)
+#define CAN_FM1R_FBM17_Msk (0x1U << CAN_FM1R_FBM17_Pos) /*!< 0x00020000 */
+#define CAN_FM1R_FBM17 CAN_FM1R_FBM17_Msk /*!< Filter Init Mode for filter 17 */
+#define CAN_FM1R_FBM18_Pos (18U)
+#define CAN_FM1R_FBM18_Msk (0x1U << CAN_FM1R_FBM18_Pos) /*!< 0x00040000 */
+#define CAN_FM1R_FBM18 CAN_FM1R_FBM18_Msk /*!< Filter Init Mode for filter 18 */
+#define CAN_FM1R_FBM19_Pos (19U)
+#define CAN_FM1R_FBM19_Msk (0x1U << CAN_FM1R_FBM19_Pos) /*!< 0x00080000 */
+#define CAN_FM1R_FBM19 CAN_FM1R_FBM19_Msk /*!< Filter Init Mode for filter 19 */
+#define CAN_FM1R_FBM20_Pos (20U)
+#define CAN_FM1R_FBM20_Msk (0x1U << CAN_FM1R_FBM20_Pos) /*!< 0x00100000 */
+#define CAN_FM1R_FBM20 CAN_FM1R_FBM20_Msk /*!< Filter Init Mode for filter 20 */
+#define CAN_FM1R_FBM21_Pos (21U)
+#define CAN_FM1R_FBM21_Msk (0x1U << CAN_FM1R_FBM21_Pos) /*!< 0x00200000 */
+#define CAN_FM1R_FBM21 CAN_FM1R_FBM21_Msk /*!< Filter Init Mode for filter 21 */
+#define CAN_FM1R_FBM22_Pos (22U)
+#define CAN_FM1R_FBM22_Msk (0x1U << CAN_FM1R_FBM22_Pos) /*!< 0x00400000 */
+#define CAN_FM1R_FBM22 CAN_FM1R_FBM22_Msk /*!< Filter Init Mode for filter 22 */
+#define CAN_FM1R_FBM23_Pos (23U)
+#define CAN_FM1R_FBM23_Msk (0x1U << CAN_FM1R_FBM23_Pos) /*!< 0x00800000 */
+#define CAN_FM1R_FBM23 CAN_FM1R_FBM23_Msk /*!< Filter Init Mode for filter 23 */
+#define CAN_FM1R_FBM24_Pos (24U)
+#define CAN_FM1R_FBM24_Msk (0x1U << CAN_FM1R_FBM24_Pos) /*!< 0x01000000 */
+#define CAN_FM1R_FBM24 CAN_FM1R_FBM24_Msk /*!< Filter Init Mode for filter 24 */
+#define CAN_FM1R_FBM25_Pos (25U)
+#define CAN_FM1R_FBM25_Msk (0x1U << CAN_FM1R_FBM25_Pos) /*!< 0x02000000 */
+#define CAN_FM1R_FBM25 CAN_FM1R_FBM25_Msk /*!< Filter Init Mode for filter 25 */
+#define CAN_FM1R_FBM26_Pos (26U)
+#define CAN_FM1R_FBM26_Msk (0x1U << CAN_FM1R_FBM26_Pos) /*!< 0x04000000 */
+#define CAN_FM1R_FBM26 CAN_FM1R_FBM26_Msk /*!< Filter Init Mode for filter 26 */
+#define CAN_FM1R_FBM27_Pos (27U)
+#define CAN_FM1R_FBM27_Msk (0x1U << CAN_FM1R_FBM27_Pos) /*!< 0x08000000 */
+#define CAN_FM1R_FBM27 CAN_FM1R_FBM27_Msk /*!< Filter Init Mode for filter 27 */
+
+/******************* Bit definition for CAN_FS1R register *******************/
+#define CAN_FS1R_FSC_Pos (0U)
+#define CAN_FS1R_FSC_Msk (0x3FFFU << CAN_FS1R_FSC_Pos) /*!< 0x00003FFF */
+#define CAN_FS1R_FSC CAN_FS1R_FSC_Msk /*!< Filter Scale Configuration */
+#define CAN_FS1R_FSC0_Pos (0U)
+#define CAN_FS1R_FSC0_Msk (0x1U << CAN_FS1R_FSC0_Pos) /*!< 0x00000001 */
+#define CAN_FS1R_FSC0 CAN_FS1R_FSC0_Msk /*!< Filter Scale Configuration for filter 0 */
+#define CAN_FS1R_FSC1_Pos (1U)
+#define CAN_FS1R_FSC1_Msk (0x1U << CAN_FS1R_FSC1_Pos) /*!< 0x00000002 */
+#define CAN_FS1R_FSC1 CAN_FS1R_FSC1_Msk /*!< Filter Scale Configuration for filter 1 */
+#define CAN_FS1R_FSC2_Pos (2U)
+#define CAN_FS1R_FSC2_Msk (0x1U << CAN_FS1R_FSC2_Pos) /*!< 0x00000004 */
+#define CAN_FS1R_FSC2 CAN_FS1R_FSC2_Msk /*!< Filter Scale Configuration for filter 2 */
+#define CAN_FS1R_FSC3_Pos (3U)
+#define CAN_FS1R_FSC3_Msk (0x1U << CAN_FS1R_FSC3_Pos) /*!< 0x00000008 */
+#define CAN_FS1R_FSC3 CAN_FS1R_FSC3_Msk /*!< Filter Scale Configuration for filter 3 */
+#define CAN_FS1R_FSC4_Pos (4U)
+#define CAN_FS1R_FSC4_Msk (0x1U << CAN_FS1R_FSC4_Pos) /*!< 0x00000010 */
+#define CAN_FS1R_FSC4 CAN_FS1R_FSC4_Msk /*!< Filter Scale Configuration for filter 4 */
+#define CAN_FS1R_FSC5_Pos (5U)
+#define CAN_FS1R_FSC5_Msk (0x1U << CAN_FS1R_FSC5_Pos) /*!< 0x00000020 */
+#define CAN_FS1R_FSC5 CAN_FS1R_FSC5_Msk /*!< Filter Scale Configuration for filter 5 */
+#define CAN_FS1R_FSC6_Pos (6U)
+#define CAN_FS1R_FSC6_Msk (0x1U << CAN_FS1R_FSC6_Pos) /*!< 0x00000040 */
+#define CAN_FS1R_FSC6 CAN_FS1R_FSC6_Msk /*!< Filter Scale Configuration for filter 6 */
+#define CAN_FS1R_FSC7_Pos (7U)
+#define CAN_FS1R_FSC7_Msk (0x1U << CAN_FS1R_FSC7_Pos) /*!< 0x00000080 */
+#define CAN_FS1R_FSC7 CAN_FS1R_FSC7_Msk /*!< Filter Scale Configuration for filter 7 */
+#define CAN_FS1R_FSC8_Pos (8U)
+#define CAN_FS1R_FSC8_Msk (0x1U << CAN_FS1R_FSC8_Pos) /*!< 0x00000100 */
+#define CAN_FS1R_FSC8 CAN_FS1R_FSC8_Msk /*!< Filter Scale Configuration for filter 8 */
+#define CAN_FS1R_FSC9_Pos (9U)
+#define CAN_FS1R_FSC9_Msk (0x1U << CAN_FS1R_FSC9_Pos) /*!< 0x00000200 */
+#define CAN_FS1R_FSC9 CAN_FS1R_FSC9_Msk /*!< Filter Scale Configuration for filter 9 */
+#define CAN_FS1R_FSC10_Pos (10U)
+#define CAN_FS1R_FSC10_Msk (0x1U << CAN_FS1R_FSC10_Pos) /*!< 0x00000400 */
+#define CAN_FS1R_FSC10 CAN_FS1R_FSC10_Msk /*!< Filter Scale Configuration for filter 10 */
+#define CAN_FS1R_FSC11_Pos (11U)
+#define CAN_FS1R_FSC11_Msk (0x1U << CAN_FS1R_FSC11_Pos) /*!< 0x00000800 */
+#define CAN_FS1R_FSC11 CAN_FS1R_FSC11_Msk /*!< Filter Scale Configuration for filter 11 */
+#define CAN_FS1R_FSC12_Pos (12U)
+#define CAN_FS1R_FSC12_Msk (0x1U << CAN_FS1R_FSC12_Pos) /*!< 0x00001000 */
+#define CAN_FS1R_FSC12 CAN_FS1R_FSC12_Msk /*!< Filter Scale Configuration for filter 12 */
+#define CAN_FS1R_FSC13_Pos (13U)
+#define CAN_FS1R_FSC13_Msk (0x1U << CAN_FS1R_FSC13_Pos) /*!< 0x00002000 */
+#define CAN_FS1R_FSC13 CAN_FS1R_FSC13_Msk /*!< Filter Scale Configuration for filter 13 */
+#define CAN_FS1R_FSC14_Pos (14U)
+#define CAN_FS1R_FSC14_Msk (0x1U << CAN_FS1R_FSC14_Pos) /*!< 0x00004000 */
+#define CAN_FS1R_FSC14 CAN_FS1R_FSC14_Msk /*!< Filter Scale Configuration for filter 14 */
+#define CAN_FS1R_FSC15_Pos (15U)
+#define CAN_FS1R_FSC15_Msk (0x1U << CAN_FS1R_FSC15_Pos) /*!< 0x00008000 */
+#define CAN_FS1R_FSC15 CAN_FS1R_FSC15_Msk /*!< Filter Scale Configuration for filter 15 */
+#define CAN_FS1R_FSC16_Pos (16U)
+#define CAN_FS1R_FSC16_Msk (0x1U << CAN_FS1R_FSC16_Pos) /*!< 0x00010000 */
+#define CAN_FS1R_FSC16 CAN_FS1R_FSC16_Msk /*!< Filter Scale Configuration for filter 16 */
+#define CAN_FS1R_FSC17_Pos (17U)
+#define CAN_FS1R_FSC17_Msk (0x1U << CAN_FS1R_FSC17_Pos) /*!< 0x00020000 */
+#define CAN_FS1R_FSC17 CAN_FS1R_FSC17_Msk /*!< Filter Scale Configuration for filter 17 */
+#define CAN_FS1R_FSC18_Pos (18U)
+#define CAN_FS1R_FSC18_Msk (0x1U << CAN_FS1R_FSC18_Pos) /*!< 0x00040000 */
+#define CAN_FS1R_FSC18 CAN_FS1R_FSC18_Msk /*!< Filter Scale Configuration for filter 18 */
+#define CAN_FS1R_FSC19_Pos (19U)
+#define CAN_FS1R_FSC19_Msk (0x1U << CAN_FS1R_FSC19_Pos) /*!< 0x00080000 */
+#define CAN_FS1R_FSC19 CAN_FS1R_FSC19_Msk /*!< Filter Scale Configuration for filter 19 */
+#define CAN_FS1R_FSC20_Pos (20U)
+#define CAN_FS1R_FSC20_Msk (0x1U << CAN_FS1R_FSC20_Pos) /*!< 0x00100000 */
+#define CAN_FS1R_FSC20 CAN_FS1R_FSC20_Msk /*!< Filter Scale Configuration for filter 20 */
+#define CAN_FS1R_FSC21_Pos (21U)
+#define CAN_FS1R_FSC21_Msk (0x1U << CAN_FS1R_FSC21_Pos) /*!< 0x00200000 */
+#define CAN_FS1R_FSC21 CAN_FS1R_FSC21_Msk /*!< Filter Scale Configuration for filter 21 */
+#define CAN_FS1R_FSC22_Pos (22U)
+#define CAN_FS1R_FSC22_Msk (0x1U << CAN_FS1R_FSC22_Pos) /*!< 0x00400000 */
+#define CAN_FS1R_FSC22 CAN_FS1R_FSC22_Msk /*!< Filter Scale Configuration for filter 22 */
+#define CAN_FS1R_FSC23_Pos (23U)
+#define CAN_FS1R_FSC23_Msk (0x1U << CAN_FS1R_FSC23_Pos) /*!< 0x00800000 */
+#define CAN_FS1R_FSC23 CAN_FS1R_FSC23_Msk /*!< Filter Scale Configuration for filter 23 */
+#define CAN_FS1R_FSC24_Pos (24U)
+#define CAN_FS1R_FSC24_Msk (0x1U << CAN_FS1R_FSC24_Pos) /*!< 0x01000000 */
+#define CAN_FS1R_FSC24 CAN_FS1R_FSC24_Msk /*!< Filter Scale Configuration for filter 24 */
+#define CAN_FS1R_FSC25_Pos (25U)
+#define CAN_FS1R_FSC25_Msk (0x1U << CAN_FS1R_FSC25_Pos) /*!< 0x02000000 */
+#define CAN_FS1R_FSC25 CAN_FS1R_FSC25_Msk /*!< Filter Scale Configuration for filter 25 */
+#define CAN_FS1R_FSC26_Pos (26U)
+#define CAN_FS1R_FSC26_Msk (0x1U << CAN_FS1R_FSC26_Pos) /*!< 0x04000000 */
+#define CAN_FS1R_FSC26 CAN_FS1R_FSC26_Msk /*!< Filter Scale Configuration for filter 26 */
+#define CAN_FS1R_FSC27_Pos (27U)
+#define CAN_FS1R_FSC27_Msk (0x1U << CAN_FS1R_FSC27_Pos) /*!< 0x08000000 */
+#define CAN_FS1R_FSC27 CAN_FS1R_FSC27_Msk /*!< Filter Scale Configuration for filter 27 */
+
+/****************** Bit definition for CAN_FFA1R register *******************/
+#define CAN_FFA1R_FFA_Pos (0U)
+#define CAN_FFA1R_FFA_Msk (0x3FFFU << CAN_FFA1R_FFA_Pos) /*!< 0x00003FFF */
+#define CAN_FFA1R_FFA CAN_FFA1R_FFA_Msk /*!< Filter FIFO Assignment */
+#define CAN_FFA1R_FFA0_Pos (0U)
+#define CAN_FFA1R_FFA0_Msk (0x1U << CAN_FFA1R_FFA0_Pos) /*!< 0x00000001 */
+#define CAN_FFA1R_FFA0 CAN_FFA1R_FFA0_Msk /*!< Filter FIFO Assignment for filter 0 */
+#define CAN_FFA1R_FFA1_Pos (1U)
+#define CAN_FFA1R_FFA1_Msk (0x1U << CAN_FFA1R_FFA1_Pos) /*!< 0x00000002 */
+#define CAN_FFA1R_FFA1 CAN_FFA1R_FFA1_Msk /*!< Filter FIFO Assignment for filter 1 */
+#define CAN_FFA1R_FFA2_Pos (2U)
+#define CAN_FFA1R_FFA2_Msk (0x1U << CAN_FFA1R_FFA2_Pos) /*!< 0x00000004 */
+#define CAN_FFA1R_FFA2 CAN_FFA1R_FFA2_Msk /*!< Filter FIFO Assignment for filter 2 */
+#define CAN_FFA1R_FFA3_Pos (3U)
+#define CAN_FFA1R_FFA3_Msk (0x1U << CAN_FFA1R_FFA3_Pos) /*!< 0x00000008 */
+#define CAN_FFA1R_FFA3 CAN_FFA1R_FFA3_Msk /*!< Filter FIFO Assignment for filter 3 */
+#define CAN_FFA1R_FFA4_Pos (4U)
+#define CAN_FFA1R_FFA4_Msk (0x1U << CAN_FFA1R_FFA4_Pos) /*!< 0x00000010 */
+#define CAN_FFA1R_FFA4 CAN_FFA1R_FFA4_Msk /*!< Filter FIFO Assignment for filter 4 */
+#define CAN_FFA1R_FFA5_Pos (5U)
+#define CAN_FFA1R_FFA5_Msk (0x1U << CAN_FFA1R_FFA5_Pos) /*!< 0x00000020 */
+#define CAN_FFA1R_FFA5 CAN_FFA1R_FFA5_Msk /*!< Filter FIFO Assignment for filter 5 */
+#define CAN_FFA1R_FFA6_Pos (6U)
+#define CAN_FFA1R_FFA6_Msk (0x1U << CAN_FFA1R_FFA6_Pos) /*!< 0x00000040 */
+#define CAN_FFA1R_FFA6 CAN_FFA1R_FFA6_Msk /*!< Filter FIFO Assignment for filter 6 */
+#define CAN_FFA1R_FFA7_Pos (7U)
+#define CAN_FFA1R_FFA7_Msk (0x1U << CAN_FFA1R_FFA7_Pos) /*!< 0x00000080 */
+#define CAN_FFA1R_FFA7 CAN_FFA1R_FFA7_Msk /*!< Filter FIFO Assignment for filter 7 */
+#define CAN_FFA1R_FFA8_Pos (8U)
+#define CAN_FFA1R_FFA8_Msk (0x1U << CAN_FFA1R_FFA8_Pos) /*!< 0x00000100 */
+#define CAN_FFA1R_FFA8 CAN_FFA1R_FFA8_Msk /*!< Filter FIFO Assignment for filter 8 */
+#define CAN_FFA1R_FFA9_Pos (9U)
+#define CAN_FFA1R_FFA9_Msk (0x1U << CAN_FFA1R_FFA9_Pos) /*!< 0x00000200 */
+#define CAN_FFA1R_FFA9 CAN_FFA1R_FFA9_Msk /*!< Filter FIFO Assignment for filter 9 */
+#define CAN_FFA1R_FFA10_Pos (10U)
+#define CAN_FFA1R_FFA10_Msk (0x1U << CAN_FFA1R_FFA10_Pos) /*!< 0x00000400 */
+#define CAN_FFA1R_FFA10 CAN_FFA1R_FFA10_Msk /*!< Filter FIFO Assignment for filter 10 */
+#define CAN_FFA1R_FFA11_Pos (11U)
+#define CAN_FFA1R_FFA11_Msk (0x1U << CAN_FFA1R_FFA11_Pos) /*!< 0x00000800 */
+#define CAN_FFA1R_FFA11 CAN_FFA1R_FFA11_Msk /*!< Filter FIFO Assignment for filter 11 */
+#define CAN_FFA1R_FFA12_Pos (12U)
+#define CAN_FFA1R_FFA12_Msk (0x1U << CAN_FFA1R_FFA12_Pos) /*!< 0x00001000 */
+#define CAN_FFA1R_FFA12 CAN_FFA1R_FFA12_Msk /*!< Filter FIFO Assignment for filter 12 */
+#define CAN_FFA1R_FFA13_Pos (13U)
+#define CAN_FFA1R_FFA13_Msk (0x1U << CAN_FFA1R_FFA13_Pos) /*!< 0x00002000 */
+#define CAN_FFA1R_FFA13 CAN_FFA1R_FFA13_Msk /*!< Filter FIFO Assignment for filter 13 */
+#define CAN_FFA1_FFA14_Pos (14U)
+#define CAN_FFA1_FFA14_Msk (0x1U << CAN_FFA1_FFA14_Pos) /*!< 0x00004000 */
+#define CAN_FFA1_FFA14 CAN_FFA1_FFA14_Msk /*!< Filter FIFO Assignment for filter 14 */
+#define CAN_FFA1_FFA15_Pos (15U)
+#define CAN_FFA1_FFA15_Msk (0x1U << CAN_FFA1_FFA15_Pos) /*!< 0x00008000 */
+#define CAN_FFA1_FFA15 CAN_FFA1_FFA15_Msk /*!< Filter FIFO Assignment for filter 15 */
+#define CAN_FFA1_FFA16_Pos (16U)
+#define CAN_FFA1_FFA16_Msk (0x1U << CAN_FFA1_FFA16_Pos) /*!< 0x00010000 */
+#define CAN_FFA1_FFA16 CAN_FFA1_FFA16_Msk /*!< Filter FIFO Assignment for filter 16 */
+#define CAN_FFA1_FFA17_Pos (17U)
+#define CAN_FFA1_FFA17_Msk (0x1U << CAN_FFA1_FFA17_Pos) /*!< 0x00020000 */
+#define CAN_FFA1_FFA17 CAN_FFA1_FFA17_Msk /*!< Filter FIFO Assignment for filter 17 */
+#define CAN_FFA1_FFA18_Pos (18U)
+#define CAN_FFA1_FFA18_Msk (0x1U << CAN_FFA1_FFA18_Pos) /*!< 0x00040000 */
+#define CAN_FFA1_FFA18 CAN_FFA1_FFA18_Msk /*!< Filter FIFO Assignment for filter 18 */
+#define CAN_FFA1_FFA19_Pos (19U)
+#define CAN_FFA1_FFA19_Msk (0x1U << CAN_FFA1_FFA19_Pos) /*!< 0x00080000 */
+#define CAN_FFA1_FFA19 CAN_FFA1_FFA19_Msk /*!< Filter FIFO Assignment for filter 19 */
+#define CAN_FFA1_FFA20_Pos (20U)
+#define CAN_FFA1_FFA20_Msk (0x1U << CAN_FFA1_FFA20_Pos) /*!< 0x00100000 */
+#define CAN_FFA1_FFA20 CAN_FFA1_FFA20_Msk /*!< Filter FIFO Assignment for filter 20 */
+#define CAN_FFA1_FFA21_Pos (21U)
+#define CAN_FFA1_FFA21_Msk (0x1U << CAN_FFA1_FFA21_Pos) /*!< 0x00200000 */
+#define CAN_FFA1_FFA21 CAN_FFA1_FFA21_Msk /*!< Filter FIFO Assignment for filter 21 */
+#define CAN_FFA1_FFA22_Pos (22U)
+#define CAN_FFA1_FFA22_Msk (0x1U << CAN_FFA1_FFA22_Pos) /*!< 0x00400000 */
+#define CAN_FFA1_FFA22 CAN_FFA1_FFA22_Msk /*!< Filter FIFO Assignment for filter 22 */
+#define CAN_FFA1_FFA23_Pos (23U)
+#define CAN_FFA1_FFA23_Msk (0x1U << CAN_FFA1_FFA23_Pos) /*!< 0x00800000 */
+#define CAN_FFA1_FFA23 CAN_FFA1_FFA23_Msk /*!< Filter FIFO Assignment for filter 23 */
+#define CAN_FFA1_FFA24_Pos (24U)
+#define CAN_FFA1_FFA24_Msk (0x1U << CAN_FFA1_FFA24_Pos) /*!< 0x01000000 */
+#define CAN_FFA1_FFA24 CAN_FFA1_FFA24_Msk /*!< Filter FIFO Assignment for filter 24 */
+#define CAN_FFA1_FFA25_Pos (25U)
+#define CAN_FFA1_FFA25_Msk (0x1U << CAN_FFA1_FFA25_Pos) /*!< 0x02000000 */
+#define CAN_FFA1_FFA25 CAN_FFA1_FFA25_Msk /*!< Filter FIFO Assignment for filter 25 */
+#define CAN_FFA1_FFA26_Pos (26U)
+#define CAN_FFA1_FFA26_Msk (0x1U << CAN_FFA1_FFA26_Pos) /*!< 0x04000000 */
+#define CAN_FFA1_FFA26 CAN_FFA1_FFA26_Msk /*!< Filter FIFO Assignment for filter 26 */
+#define CAN_FFA1_FFA27_Pos (27U)
+#define CAN_FFA1_FFA27_Msk (0x1U << CAN_FFA1_FFA27_Pos) /*!< 0x08000000 */
+#define CAN_FFA1_FFA27 CAN_FFA1_FFA27_Msk /*!< Filter FIFO Assignment for filter 27 */
+
+/******************* Bit definition for CAN_FA1R register *******************/
+#define CAN_FA1R_FACT_Pos (0U)
+#define CAN_FA1R_FACT_Msk (0x3FFFU << CAN_FA1R_FACT_Pos) /*!< 0x00003FFF */
+#define CAN_FA1R_FACT CAN_FA1R_FACT_Msk /*!< Filter Active */
+#define CAN_FA1R_FACT0_Pos (0U)
+#define CAN_FA1R_FACT0_Msk (0x1U << CAN_FA1R_FACT0_Pos) /*!< 0x00000001 */
+#define CAN_FA1R_FACT0 CAN_FA1R_FACT0_Msk /*!< Filter 0 Active */
+#define CAN_FA1R_FACT1_Pos (1U)
+#define CAN_FA1R_FACT1_Msk (0x1U << CAN_FA1R_FACT1_Pos) /*!< 0x00000002 */
+#define CAN_FA1R_FACT1 CAN_FA1R_FACT1_Msk /*!< Filter 1 Active */
+#define CAN_FA1R_FACT2_Pos (2U)
+#define CAN_FA1R_FACT2_Msk (0x1U << CAN_FA1R_FACT2_Pos) /*!< 0x00000004 */
+#define CAN_FA1R_FACT2 CAN_FA1R_FACT2_Msk /*!< Filter 2 Active */
+#define CAN_FA1R_FACT3_Pos (3U)
+#define CAN_FA1R_FACT3_Msk (0x1U << CAN_FA1R_FACT3_Pos) /*!< 0x00000008 */
+#define CAN_FA1R_FACT3 CAN_FA1R_FACT3_Msk /*!< Filter 3 Active */
+#define CAN_FA1R_FACT4_Pos (4U)
+#define CAN_FA1R_FACT4_Msk (0x1U << CAN_FA1R_FACT4_Pos) /*!< 0x00000010 */
+#define CAN_FA1R_FACT4 CAN_FA1R_FACT4_Msk /*!< Filter 4 Active */
+#define CAN_FA1R_FACT5_Pos (5U)
+#define CAN_FA1R_FACT5_Msk (0x1U << CAN_FA1R_FACT5_Pos) /*!< 0x00000020 */
+#define CAN_FA1R_FACT5 CAN_FA1R_FACT5_Msk /*!< Filter 5 Active */
+#define CAN_FA1R_FACT6_Pos (6U)
+#define CAN_FA1R_FACT6_Msk (0x1U << CAN_FA1R_FACT6_Pos) /*!< 0x00000040 */
+#define CAN_FA1R_FACT6 CAN_FA1R_FACT6_Msk /*!< Filter 6 Active */
+#define CAN_FA1R_FACT7_Pos (7U)
+#define CAN_FA1R_FACT7_Msk (0x1U << CAN_FA1R_FACT7_Pos) /*!< 0x00000080 */
+#define CAN_FA1R_FACT7 CAN_FA1R_FACT7_Msk /*!< Filter 7 Active */
+#define CAN_FA1R_FACT8_Pos (8U)
+#define CAN_FA1R_FACT8_Msk (0x1U << CAN_FA1R_FACT8_Pos) /*!< 0x00000100 */
+#define CAN_FA1R_FACT8 CAN_FA1R_FACT8_Msk /*!< Filter 8 Active */
+#define CAN_FA1R_FACT9_Pos (9U)
+#define CAN_FA1R_FACT9_Msk (0x1U << CAN_FA1R_FACT9_Pos) /*!< 0x00000200 */
+#define CAN_FA1R_FACT9 CAN_FA1R_FACT9_Msk /*!< Filter 9 Active */
+#define CAN_FA1R_FACT10_Pos (10U)
+#define CAN_FA1R_FACT10_Msk (0x1U << CAN_FA1R_FACT10_Pos) /*!< 0x00000400 */
+#define CAN_FA1R_FACT10 CAN_FA1R_FACT10_Msk /*!< Filter 10 Active */
+#define CAN_FA1R_FACT11_Pos (11U)
+#define CAN_FA1R_FACT11_Msk (0x1U << CAN_FA1R_FACT11_Pos) /*!< 0x00000800 */
+#define CAN_FA1R_FACT11 CAN_FA1R_FACT11_Msk /*!< Filter 11 Active */
+#define CAN_FA1R_FACT12_Pos (12U)
+#define CAN_FA1R_FACT12_Msk (0x1U << CAN_FA1R_FACT12_Pos) /*!< 0x00001000 */
+#define CAN_FA1R_FACT12 CAN_FA1R_FACT12_Msk /*!< Filter 12 Active */
+#define CAN_FA1R_FACT13_Pos (13U)
+#define CAN_FA1R_FACT13_Msk (0x1U << CAN_FA1R_FACT13_Pos) /*!< 0x00002000 */
+#define CAN_FA1R_FACT13 CAN_FA1R_FACT13_Msk /*!< Filter 13 Active */
+#define CAN_FA1R_FACT14_Pos (14U)
+#define CAN_FA1R_FACT14_Msk (0x1U << CAN_FA1R_FACT14_Pos) /*!< 0x00004000 */
+#define CAN_FA1R_FACT14 CAN_FA1R_FACT14_Msk /*!< Filter 14 Active */
+#define CAN_FA1R_FACT15_Pos (15U)
+#define CAN_FA1R_FACT15_Msk (0x1U << CAN_FA1R_FACT15_Pos) /*!< 0x00008000 */
+#define CAN_FA1R_FACT15 CAN_FA1R_FACT15_Msk /*!< Filter 15 Active */
+#define CAN_FA1R_FACT16_Pos (16U)
+#define CAN_FA1R_FACT16_Msk (0x1U << CAN_FA1R_FACT16_Pos) /*!< 0x00010000 */
+#define CAN_FA1R_FACT16 CAN_FA1R_FACT16_Msk /*!< Filter 16 Active */
+#define CAN_FA1R_FACT17_Pos (17U)
+#define CAN_FA1R_FACT17_Msk (0x1U << CAN_FA1R_FACT17_Pos) /*!< 0x00020000 */
+#define CAN_FA1R_FACT17 CAN_FA1R_FACT17_Msk /*!< Filter 17 Active */
+#define CAN_FA1R_FACT18_Pos (18U)
+#define CAN_FA1R_FACT18_Msk (0x1U << CAN_FA1R_FACT18_Pos) /*!< 0x00040000 */
+#define CAN_FA1R_FACT18 CAN_FA1R_FACT18_Msk /*!< Filter 18 Active */
+#define CAN_FA1R_FACT19_Pos (19U)
+#define CAN_FA1R_FACT19_Msk (0x1U << CAN_FA1R_FACT19_Pos) /*!< 0x00080000 */
+#define CAN_FA1R_FACT19 CAN_FA1R_FACT19_Msk /*!< Filter 19 Active */
+#define CAN_FA1R_FACT20_Pos (20U)
+#define CAN_FA1R_FACT20_Msk (0x1U << CAN_FA1R_FACT20_Pos) /*!< 0x00100000 */
+#define CAN_FA1R_FACT20 CAN_FA1R_FACT20_Msk /*!< Filter 20 Active */
+#define CAN_FA1R_FACT21_Pos (21U)
+#define CAN_FA1R_FACT21_Msk (0x1U << CAN_FA1R_FACT21_Pos) /*!< 0x00200000 */
+#define CAN_FA1R_FACT21 CAN_FA1R_FACT21_Msk /*!< Filter 21 Active */
+#define CAN_FA1R_FACT22_Pos (22U)
+#define CAN_FA1R_FACT22_Msk (0x1U << CAN_FA1R_FACT22_Pos) /*!< 0x00400000 */
+#define CAN_FA1R_FACT22 CAN_FA1R_FACT22_Msk /*!< Filter 22 Active */
+#define CAN_FA1R_FACT23_Pos (23U)
+#define CAN_FA1R_FACT23_Msk (0x1U << CAN_FA1R_FACT23_Pos) /*!< 0x00800000 */
+#define CAN_FA1R_FACT23 CAN_FA1R_FACT23_Msk /*!< Filter 23 Active */
+#define CAN_FA1R_FACT24_Pos (24U)
+#define CAN_FA1R_FACT24_Msk (0x1U << CAN_FA1R_FACT24_Pos) /*!< 0x01000000 */
+#define CAN_FA1R_FACT24 CAN_FA1R_FACT24_Msk /*!< Filter 24 Active */
+#define CAN_FA1R_FACT25_Pos (25U)
+#define CAN_FA1R_FACT25_Msk (0x1U << CAN_FA1R_FACT25_Pos) /*!< 0x02000000 */
+#define CAN_FA1R_FACT25 CAN_FA1R_FACT25_Msk /*!< Filter 25 Active */
+#define CAN_FA1R_FACT26_Pos (26U)
+#define CAN_FA1R_FACT26_Msk (0x1U << CAN_FA1R_FACT26_Pos) /*!< 0x04000000 */
+#define CAN_FA1R_FACT26 CAN_FA1R_FACT26_Msk /*!< Filter 26 Active */
+#define CAN_FA1R_FACT27_Pos (27U)
+#define CAN_FA1R_FACT27_Msk (0x1U << CAN_FA1R_FACT27_Pos) /*!< 0x08000000 */
+#define CAN_FA1R_FACT27 CAN_FA1R_FACT27_Msk /*!< Filter 27 Active */
+
+/******************* Bit definition for CAN_F0R1 register *******************/
+#define CAN_F0R1_FB0_Pos (0U)
+#define CAN_F0R1_FB0_Msk (0x1U << CAN_F0R1_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F0R1_FB0 CAN_F0R1_FB0_Msk /*!< Filter bit 0 */
+#define CAN_F0R1_FB1_Pos (1U)
+#define CAN_F0R1_FB1_Msk (0x1U << CAN_F0R1_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F0R1_FB1 CAN_F0R1_FB1_Msk /*!< Filter bit 1 */
+#define CAN_F0R1_FB2_Pos (2U)
+#define CAN_F0R1_FB2_Msk (0x1U << CAN_F0R1_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F0R1_FB2 CAN_F0R1_FB2_Msk /*!< Filter bit 2 */
+#define CAN_F0R1_FB3_Pos (3U)
+#define CAN_F0R1_FB3_Msk (0x1U << CAN_F0R1_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F0R1_FB3 CAN_F0R1_FB3_Msk /*!< Filter bit 3 */
+#define CAN_F0R1_FB4_Pos (4U)
+#define CAN_F0R1_FB4_Msk (0x1U << CAN_F0R1_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F0R1_FB4 CAN_F0R1_FB4_Msk /*!< Filter bit 4 */
+#define CAN_F0R1_FB5_Pos (5U)
+#define CAN_F0R1_FB5_Msk (0x1U << CAN_F0R1_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F0R1_FB5 CAN_F0R1_FB5_Msk /*!< Filter bit 5 */
+#define CAN_F0R1_FB6_Pos (6U)
+#define CAN_F0R1_FB6_Msk (0x1U << CAN_F0R1_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F0R1_FB6 CAN_F0R1_FB6_Msk /*!< Filter bit 6 */
+#define CAN_F0R1_FB7_Pos (7U)
+#define CAN_F0R1_FB7_Msk (0x1U << CAN_F0R1_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F0R1_FB7 CAN_F0R1_FB7_Msk /*!< Filter bit 7 */
+#define CAN_F0R1_FB8_Pos (8U)
+#define CAN_F0R1_FB8_Msk (0x1U << CAN_F0R1_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F0R1_FB8 CAN_F0R1_FB8_Msk /*!< Filter bit 8 */
+#define CAN_F0R1_FB9_Pos (9U)
+#define CAN_F0R1_FB9_Msk (0x1U << CAN_F0R1_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F0R1_FB9 CAN_F0R1_FB9_Msk /*!< Filter bit 9 */
+#define CAN_F0R1_FB10_Pos (10U)
+#define CAN_F0R1_FB10_Msk (0x1U << CAN_F0R1_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F0R1_FB10 CAN_F0R1_FB10_Msk /*!< Filter bit 10 */
+#define CAN_F0R1_FB11_Pos (11U)
+#define CAN_F0R1_FB11_Msk (0x1U << CAN_F0R1_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F0R1_FB11 CAN_F0R1_FB11_Msk /*!< Filter bit 11 */
+#define CAN_F0R1_FB12_Pos (12U)
+#define CAN_F0R1_FB12_Msk (0x1U << CAN_F0R1_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F0R1_FB12 CAN_F0R1_FB12_Msk /*!< Filter bit 12 */
+#define CAN_F0R1_FB13_Pos (13U)
+#define CAN_F0R1_FB13_Msk (0x1U << CAN_F0R1_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F0R1_FB13 CAN_F0R1_FB13_Msk /*!< Filter bit 13 */
+#define CAN_F0R1_FB14_Pos (14U)
+#define CAN_F0R1_FB14_Msk (0x1U << CAN_F0R1_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F0R1_FB14 CAN_F0R1_FB14_Msk /*!< Filter bit 14 */
+#define CAN_F0R1_FB15_Pos (15U)
+#define CAN_F0R1_FB15_Msk (0x1U << CAN_F0R1_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F0R1_FB15 CAN_F0R1_FB15_Msk /*!< Filter bit 15 */
+#define CAN_F0R1_FB16_Pos (16U)
+#define CAN_F0R1_FB16_Msk (0x1U << CAN_F0R1_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F0R1_FB16 CAN_F0R1_FB16_Msk /*!< Filter bit 16 */
+#define CAN_F0R1_FB17_Pos (17U)
+#define CAN_F0R1_FB17_Msk (0x1U << CAN_F0R1_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F0R1_FB17 CAN_F0R1_FB17_Msk /*!< Filter bit 17 */
+#define CAN_F0R1_FB18_Pos (18U)
+#define CAN_F0R1_FB18_Msk (0x1U << CAN_F0R1_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F0R1_FB18 CAN_F0R1_FB18_Msk /*!< Filter bit 18 */
+#define CAN_F0R1_FB19_Pos (19U)
+#define CAN_F0R1_FB19_Msk (0x1U << CAN_F0R1_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F0R1_FB19 CAN_F0R1_FB19_Msk /*!< Filter bit 19 */
+#define CAN_F0R1_FB20_Pos (20U)
+#define CAN_F0R1_FB20_Msk (0x1U << CAN_F0R1_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F0R1_FB20 CAN_F0R1_FB20_Msk /*!< Filter bit 20 */
+#define CAN_F0R1_FB21_Pos (21U)
+#define CAN_F0R1_FB21_Msk (0x1U << CAN_F0R1_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F0R1_FB21 CAN_F0R1_FB21_Msk /*!< Filter bit 21 */
+#define CAN_F0R1_FB22_Pos (22U)
+#define CAN_F0R1_FB22_Msk (0x1U << CAN_F0R1_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F0R1_FB22 CAN_F0R1_FB22_Msk /*!< Filter bit 22 */
+#define CAN_F0R1_FB23_Pos (23U)
+#define CAN_F0R1_FB23_Msk (0x1U << CAN_F0R1_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F0R1_FB23 CAN_F0R1_FB23_Msk /*!< Filter bit 23 */
+#define CAN_F0R1_FB24_Pos (24U)
+#define CAN_F0R1_FB24_Msk (0x1U << CAN_F0R1_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F0R1_FB24 CAN_F0R1_FB24_Msk /*!< Filter bit 24 */
+#define CAN_F0R1_FB25_Pos (25U)
+#define CAN_F0R1_FB25_Msk (0x1U << CAN_F0R1_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F0R1_FB25 CAN_F0R1_FB25_Msk /*!< Filter bit 25 */
+#define CAN_F0R1_FB26_Pos (26U)
+#define CAN_F0R1_FB26_Msk (0x1U << CAN_F0R1_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F0R1_FB26 CAN_F0R1_FB26_Msk /*!< Filter bit 26 */
+#define CAN_F0R1_FB27_Pos (27U)
+#define CAN_F0R1_FB27_Msk (0x1U << CAN_F0R1_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F0R1_FB27 CAN_F0R1_FB27_Msk /*!< Filter bit 27 */
+#define CAN_F0R1_FB28_Pos (28U)
+#define CAN_F0R1_FB28_Msk (0x1U << CAN_F0R1_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F0R1_FB28 CAN_F0R1_FB28_Msk /*!< Filter bit 28 */
+#define CAN_F0R1_FB29_Pos (29U)
+#define CAN_F0R1_FB29_Msk (0x1U << CAN_F0R1_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F0R1_FB29 CAN_F0R1_FB29_Msk /*!< Filter bit 29 */
+#define CAN_F0R1_FB30_Pos (30U)
+#define CAN_F0R1_FB30_Msk (0x1U << CAN_F0R1_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F0R1_FB30 CAN_F0R1_FB30_Msk /*!< Filter bit 30 */
+#define CAN_F0R1_FB31_Pos (31U)
+#define CAN_F0R1_FB31_Msk (0x1U << CAN_F0R1_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F0R1_FB31 CAN_F0R1_FB31_Msk /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F1R1 register *******************/
+#define CAN_F1R1_FB0_Pos (0U)
+#define CAN_F1R1_FB0_Msk (0x1U << CAN_F1R1_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F1R1_FB0 CAN_F1R1_FB0_Msk /*!< Filter bit 0 */
+#define CAN_F1R1_FB1_Pos (1U)
+#define CAN_F1R1_FB1_Msk (0x1U << CAN_F1R1_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F1R1_FB1 CAN_F1R1_FB1_Msk /*!< Filter bit 1 */
+#define CAN_F1R1_FB2_Pos (2U)
+#define CAN_F1R1_FB2_Msk (0x1U << CAN_F1R1_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F1R1_FB2 CAN_F1R1_FB2_Msk /*!< Filter bit 2 */
+#define CAN_F1R1_FB3_Pos (3U)
+#define CAN_F1R1_FB3_Msk (0x1U << CAN_F1R1_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F1R1_FB3 CAN_F1R1_FB3_Msk /*!< Filter bit 3 */
+#define CAN_F1R1_FB4_Pos (4U)
+#define CAN_F1R1_FB4_Msk (0x1U << CAN_F1R1_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F1R1_FB4 CAN_F1R1_FB4_Msk /*!< Filter bit 4 */
+#define CAN_F1R1_FB5_Pos (5U)
+#define CAN_F1R1_FB5_Msk (0x1U << CAN_F1R1_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F1R1_FB5 CAN_F1R1_FB5_Msk /*!< Filter bit 5 */
+#define CAN_F1R1_FB6_Pos (6U)
+#define CAN_F1R1_FB6_Msk (0x1U << CAN_F1R1_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F1R1_FB6 CAN_F1R1_FB6_Msk /*!< Filter bit 6 */
+#define CAN_F1R1_FB7_Pos (7U)
+#define CAN_F1R1_FB7_Msk (0x1U << CAN_F1R1_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F1R1_FB7 CAN_F1R1_FB7_Msk /*!< Filter bit 7 */
+#define CAN_F1R1_FB8_Pos (8U)
+#define CAN_F1R1_FB8_Msk (0x1U << CAN_F1R1_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F1R1_FB8 CAN_F1R1_FB8_Msk /*!< Filter bit 8 */
+#define CAN_F1R1_FB9_Pos (9U)
+#define CAN_F1R1_FB9_Msk (0x1U << CAN_F1R1_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F1R1_FB9 CAN_F1R1_FB9_Msk /*!< Filter bit 9 */
+#define CAN_F1R1_FB10_Pos (10U)
+#define CAN_F1R1_FB10_Msk (0x1U << CAN_F1R1_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F1R1_FB10 CAN_F1R1_FB10_Msk /*!< Filter bit 10 */
+#define CAN_F1R1_FB11_Pos (11U)
+#define CAN_F1R1_FB11_Msk (0x1U << CAN_F1R1_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F1R1_FB11 CAN_F1R1_FB11_Msk /*!< Filter bit 11 */
+#define CAN_F1R1_FB12_Pos (12U)
+#define CAN_F1R1_FB12_Msk (0x1U << CAN_F1R1_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F1R1_FB12 CAN_F1R1_FB12_Msk /*!< Filter bit 12 */
+#define CAN_F1R1_FB13_Pos (13U)
+#define CAN_F1R1_FB13_Msk (0x1U << CAN_F1R1_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F1R1_FB13 CAN_F1R1_FB13_Msk /*!< Filter bit 13 */
+#define CAN_F1R1_FB14_Pos (14U)
+#define CAN_F1R1_FB14_Msk (0x1U << CAN_F1R1_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F1R1_FB14 CAN_F1R1_FB14_Msk /*!< Filter bit 14 */
+#define CAN_F1R1_FB15_Pos (15U)
+#define CAN_F1R1_FB15_Msk (0x1U << CAN_F1R1_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F1R1_FB15 CAN_F1R1_FB15_Msk /*!< Filter bit 15 */
+#define CAN_F1R1_FB16_Pos (16U)
+#define CAN_F1R1_FB16_Msk (0x1U << CAN_F1R1_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F1R1_FB16 CAN_F1R1_FB16_Msk /*!< Filter bit 16 */
+#define CAN_F1R1_FB17_Pos (17U)
+#define CAN_F1R1_FB17_Msk (0x1U << CAN_F1R1_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F1R1_FB17 CAN_F1R1_FB17_Msk /*!< Filter bit 17 */
+#define CAN_F1R1_FB18_Pos (18U)
+#define CAN_F1R1_FB18_Msk (0x1U << CAN_F1R1_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F1R1_FB18 CAN_F1R1_FB18_Msk /*!< Filter bit 18 */
+#define CAN_F1R1_FB19_Pos (19U)
+#define CAN_F1R1_FB19_Msk (0x1U << CAN_F1R1_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F1R1_FB19 CAN_F1R1_FB19_Msk /*!< Filter bit 19 */
+#define CAN_F1R1_FB20_Pos (20U)
+#define CAN_F1R1_FB20_Msk (0x1U << CAN_F1R1_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F1R1_FB20 CAN_F1R1_FB20_Msk /*!< Filter bit 20 */
+#define CAN_F1R1_FB21_Pos (21U)
+#define CAN_F1R1_FB21_Msk (0x1U << CAN_F1R1_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F1R1_FB21 CAN_F1R1_FB21_Msk /*!< Filter bit 21 */
+#define CAN_F1R1_FB22_Pos (22U)
+#define CAN_F1R1_FB22_Msk (0x1U << CAN_F1R1_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F1R1_FB22 CAN_F1R1_FB22_Msk /*!< Filter bit 22 */
+#define CAN_F1R1_FB23_Pos (23U)
+#define CAN_F1R1_FB23_Msk (0x1U << CAN_F1R1_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F1R1_FB23 CAN_F1R1_FB23_Msk /*!< Filter bit 23 */
+#define CAN_F1R1_FB24_Pos (24U)
+#define CAN_F1R1_FB24_Msk (0x1U << CAN_F1R1_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F1R1_FB24 CAN_F1R1_FB24_Msk /*!< Filter bit 24 */
+#define CAN_F1R1_FB25_Pos (25U)
+#define CAN_F1R1_FB25_Msk (0x1U << CAN_F1R1_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F1R1_FB25 CAN_F1R1_FB25_Msk /*!< Filter bit 25 */
+#define CAN_F1R1_FB26_Pos (26U)
+#define CAN_F1R1_FB26_Msk (0x1U << CAN_F1R1_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F1R1_FB26 CAN_F1R1_FB26_Msk /*!< Filter bit 26 */
+#define CAN_F1R1_FB27_Pos (27U)
+#define CAN_F1R1_FB27_Msk (0x1U << CAN_F1R1_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F1R1_FB27 CAN_F1R1_FB27_Msk /*!< Filter bit 27 */
+#define CAN_F1R1_FB28_Pos (28U)
+#define CAN_F1R1_FB28_Msk (0x1U << CAN_F1R1_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F1R1_FB28 CAN_F1R1_FB28_Msk /*!< Filter bit 28 */
+#define CAN_F1R1_FB29_Pos (29U)
+#define CAN_F1R1_FB29_Msk (0x1U << CAN_F1R1_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F1R1_FB29 CAN_F1R1_FB29_Msk /*!< Filter bit 29 */
+#define CAN_F1R1_FB30_Pos (30U)
+#define CAN_F1R1_FB30_Msk (0x1U << CAN_F1R1_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F1R1_FB30 CAN_F1R1_FB30_Msk /*!< Filter bit 30 */
+#define CAN_F1R1_FB31_Pos (31U)
+#define CAN_F1R1_FB31_Msk (0x1U << CAN_F1R1_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F1R1_FB31 CAN_F1R1_FB31_Msk /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F2R1 register *******************/
+#define CAN_F2R1_FB0_Pos (0U)
+#define CAN_F2R1_FB0_Msk (0x1U << CAN_F2R1_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F2R1_FB0 CAN_F2R1_FB0_Msk /*!< Filter bit 0 */
+#define CAN_F2R1_FB1_Pos (1U)
+#define CAN_F2R1_FB1_Msk (0x1U << CAN_F2R1_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F2R1_FB1 CAN_F2R1_FB1_Msk /*!< Filter bit 1 */
+#define CAN_F2R1_FB2_Pos (2U)
+#define CAN_F2R1_FB2_Msk (0x1U << CAN_F2R1_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F2R1_FB2 CAN_F2R1_FB2_Msk /*!< Filter bit 2 */
+#define CAN_F2R1_FB3_Pos (3U)
+#define CAN_F2R1_FB3_Msk (0x1U << CAN_F2R1_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F2R1_FB3 CAN_F2R1_FB3_Msk /*!< Filter bit 3 */
+#define CAN_F2R1_FB4_Pos (4U)
+#define CAN_F2R1_FB4_Msk (0x1U << CAN_F2R1_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F2R1_FB4 CAN_F2R1_FB4_Msk /*!< Filter bit 4 */
+#define CAN_F2R1_FB5_Pos (5U)
+#define CAN_F2R1_FB5_Msk (0x1U << CAN_F2R1_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F2R1_FB5 CAN_F2R1_FB5_Msk /*!< Filter bit 5 */
+#define CAN_F2R1_FB6_Pos (6U)
+#define CAN_F2R1_FB6_Msk (0x1U << CAN_F2R1_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F2R1_FB6 CAN_F2R1_FB6_Msk /*!< Filter bit 6 */
+#define CAN_F2R1_FB7_Pos (7U)
+#define CAN_F2R1_FB7_Msk (0x1U << CAN_F2R1_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F2R1_FB7 CAN_F2R1_FB7_Msk /*!< Filter bit 7 */
+#define CAN_F2R1_FB8_Pos (8U)
+#define CAN_F2R1_FB8_Msk (0x1U << CAN_F2R1_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F2R1_FB8 CAN_F2R1_FB8_Msk /*!< Filter bit 8 */
+#define CAN_F2R1_FB9_Pos (9U)
+#define CAN_F2R1_FB9_Msk (0x1U << CAN_F2R1_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F2R1_FB9 CAN_F2R1_FB9_Msk /*!< Filter bit 9 */
+#define CAN_F2R1_FB10_Pos (10U)
+#define CAN_F2R1_FB10_Msk (0x1U << CAN_F2R1_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F2R1_FB10 CAN_F2R1_FB10_Msk /*!< Filter bit 10 */
+#define CAN_F2R1_FB11_Pos (11U)
+#define CAN_F2R1_FB11_Msk (0x1U << CAN_F2R1_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F2R1_FB11 CAN_F2R1_FB11_Msk /*!< Filter bit 11 */
+#define CAN_F2R1_FB12_Pos (12U)
+#define CAN_F2R1_FB12_Msk (0x1U << CAN_F2R1_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F2R1_FB12 CAN_F2R1_FB12_Msk /*!< Filter bit 12 */
+#define CAN_F2R1_FB13_Pos (13U)
+#define CAN_F2R1_FB13_Msk (0x1U << CAN_F2R1_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F2R1_FB13 CAN_F2R1_FB13_Msk /*!< Filter bit 13 */
+#define CAN_F2R1_FB14_Pos (14U)
+#define CAN_F2R1_FB14_Msk (0x1U << CAN_F2R1_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F2R1_FB14 CAN_F2R1_FB14_Msk /*!< Filter bit 14 */
+#define CAN_F2R1_FB15_Pos (15U)
+#define CAN_F2R1_FB15_Msk (0x1U << CAN_F2R1_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F2R1_FB15 CAN_F2R1_FB15_Msk /*!< Filter bit 15 */
+#define CAN_F2R1_FB16_Pos (16U)
+#define CAN_F2R1_FB16_Msk (0x1U << CAN_F2R1_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F2R1_FB16 CAN_F2R1_FB16_Msk /*!< Filter bit 16 */
+#define CAN_F2R1_FB17_Pos (17U)
+#define CAN_F2R1_FB17_Msk (0x1U << CAN_F2R1_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F2R1_FB17 CAN_F2R1_FB17_Msk /*!< Filter bit 17 */
+#define CAN_F2R1_FB18_Pos (18U)
+#define CAN_F2R1_FB18_Msk (0x1U << CAN_F2R1_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F2R1_FB18 CAN_F2R1_FB18_Msk /*!< Filter bit 18 */
+#define CAN_F2R1_FB19_Pos (19U)
+#define CAN_F2R1_FB19_Msk (0x1U << CAN_F2R1_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F2R1_FB19 CAN_F2R1_FB19_Msk /*!< Filter bit 19 */
+#define CAN_F2R1_FB20_Pos (20U)
+#define CAN_F2R1_FB20_Msk (0x1U << CAN_F2R1_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F2R1_FB20 CAN_F2R1_FB20_Msk /*!< Filter bit 20 */
+#define CAN_F2R1_FB21_Pos (21U)
+#define CAN_F2R1_FB21_Msk (0x1U << CAN_F2R1_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F2R1_FB21 CAN_F2R1_FB21_Msk /*!< Filter bit 21 */
+#define CAN_F2R1_FB22_Pos (22U)
+#define CAN_F2R1_FB22_Msk (0x1U << CAN_F2R1_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F2R1_FB22 CAN_F2R1_FB22_Msk /*!< Filter bit 22 */
+#define CAN_F2R1_FB23_Pos (23U)
+#define CAN_F2R1_FB23_Msk (0x1U << CAN_F2R1_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F2R1_FB23 CAN_F2R1_FB23_Msk /*!< Filter bit 23 */
+#define CAN_F2R1_FB24_Pos (24U)
+#define CAN_F2R1_FB24_Msk (0x1U << CAN_F2R1_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F2R1_FB24 CAN_F2R1_FB24_Msk /*!< Filter bit 24 */
+#define CAN_F2R1_FB25_Pos (25U)
+#define CAN_F2R1_FB25_Msk (0x1U << CAN_F2R1_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F2R1_FB25 CAN_F2R1_FB25_Msk /*!< Filter bit 25 */
+#define CAN_F2R1_FB26_Pos (26U)
+#define CAN_F2R1_FB26_Msk (0x1U << CAN_F2R1_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F2R1_FB26 CAN_F2R1_FB26_Msk /*!< Filter bit 26 */
+#define CAN_F2R1_FB27_Pos (27U)
+#define CAN_F2R1_FB27_Msk (0x1U << CAN_F2R1_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F2R1_FB27 CAN_F2R1_FB27_Msk /*!< Filter bit 27 */
+#define CAN_F2R1_FB28_Pos (28U)
+#define CAN_F2R1_FB28_Msk (0x1U << CAN_F2R1_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F2R1_FB28 CAN_F2R1_FB28_Msk /*!< Filter bit 28 */
+#define CAN_F2R1_FB29_Pos (29U)
+#define CAN_F2R1_FB29_Msk (0x1U << CAN_F2R1_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F2R1_FB29 CAN_F2R1_FB29_Msk /*!< Filter bit 29 */
+#define CAN_F2R1_FB30_Pos (30U)
+#define CAN_F2R1_FB30_Msk (0x1U << CAN_F2R1_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F2R1_FB30 CAN_F2R1_FB30_Msk /*!< Filter bit 30 */
+#define CAN_F2R1_FB31_Pos (31U)
+#define CAN_F2R1_FB31_Msk (0x1U << CAN_F2R1_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F2R1_FB31 CAN_F2R1_FB31_Msk /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F3R1 register *******************/
+#define CAN_F3R1_FB0_Pos (0U)
+#define CAN_F3R1_FB0_Msk (0x1U << CAN_F3R1_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F3R1_FB0 CAN_F3R1_FB0_Msk /*!< Filter bit 0 */
+#define CAN_F3R1_FB1_Pos (1U)
+#define CAN_F3R1_FB1_Msk (0x1U << CAN_F3R1_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F3R1_FB1 CAN_F3R1_FB1_Msk /*!< Filter bit 1 */
+#define CAN_F3R1_FB2_Pos (2U)
+#define CAN_F3R1_FB2_Msk (0x1U << CAN_F3R1_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F3R1_FB2 CAN_F3R1_FB2_Msk /*!< Filter bit 2 */
+#define CAN_F3R1_FB3_Pos (3U)
+#define CAN_F3R1_FB3_Msk (0x1U << CAN_F3R1_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F3R1_FB3 CAN_F3R1_FB3_Msk /*!< Filter bit 3 */
+#define CAN_F3R1_FB4_Pos (4U)
+#define CAN_F3R1_FB4_Msk (0x1U << CAN_F3R1_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F3R1_FB4 CAN_F3R1_FB4_Msk /*!< Filter bit 4 */
+#define CAN_F3R1_FB5_Pos (5U)
+#define CAN_F3R1_FB5_Msk (0x1U << CAN_F3R1_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F3R1_FB5 CAN_F3R1_FB5_Msk /*!< Filter bit 5 */
+#define CAN_F3R1_FB6_Pos (6U)
+#define CAN_F3R1_FB6_Msk (0x1U << CAN_F3R1_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F3R1_FB6 CAN_F3R1_FB6_Msk /*!< Filter bit 6 */
+#define CAN_F3R1_FB7_Pos (7U)
+#define CAN_F3R1_FB7_Msk (0x1U << CAN_F3R1_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F3R1_FB7 CAN_F3R1_FB7_Msk /*!< Filter bit 7 */
+#define CAN_F3R1_FB8_Pos (8U)
+#define CAN_F3R1_FB8_Msk (0x1U << CAN_F3R1_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F3R1_FB8 CAN_F3R1_FB8_Msk /*!< Filter bit 8 */
+#define CAN_F3R1_FB9_Pos (9U)
+#define CAN_F3R1_FB9_Msk (0x1U << CAN_F3R1_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F3R1_FB9 CAN_F3R1_FB9_Msk /*!< Filter bit 9 */
+#define CAN_F3R1_FB10_Pos (10U)
+#define CAN_F3R1_FB10_Msk (0x1U << CAN_F3R1_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F3R1_FB10 CAN_F3R1_FB10_Msk /*!< Filter bit 10 */
+#define CAN_F3R1_FB11_Pos (11U)
+#define CAN_F3R1_FB11_Msk (0x1U << CAN_F3R1_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F3R1_FB11 CAN_F3R1_FB11_Msk /*!< Filter bit 11 */
+#define CAN_F3R1_FB12_Pos (12U)
+#define CAN_F3R1_FB12_Msk (0x1U << CAN_F3R1_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F3R1_FB12 CAN_F3R1_FB12_Msk /*!< Filter bit 12 */
+#define CAN_F3R1_FB13_Pos (13U)
+#define CAN_F3R1_FB13_Msk (0x1U << CAN_F3R1_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F3R1_FB13 CAN_F3R1_FB13_Msk /*!< Filter bit 13 */
+#define CAN_F3R1_FB14_Pos (14U)
+#define CAN_F3R1_FB14_Msk (0x1U << CAN_F3R1_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F3R1_FB14 CAN_F3R1_FB14_Msk /*!< Filter bit 14 */
+#define CAN_F3R1_FB15_Pos (15U)
+#define CAN_F3R1_FB15_Msk (0x1U << CAN_F3R1_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F3R1_FB15 CAN_F3R1_FB15_Msk /*!< Filter bit 15 */
+#define CAN_F3R1_FB16_Pos (16U)
+#define CAN_F3R1_FB16_Msk (0x1U << CAN_F3R1_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F3R1_FB16 CAN_F3R1_FB16_Msk /*!< Filter bit 16 */
+#define CAN_F3R1_FB17_Pos (17U)
+#define CAN_F3R1_FB17_Msk (0x1U << CAN_F3R1_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F3R1_FB17 CAN_F3R1_FB17_Msk /*!< Filter bit 17 */
+#define CAN_F3R1_FB18_Pos (18U)
+#define CAN_F3R1_FB18_Msk (0x1U << CAN_F3R1_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F3R1_FB18 CAN_F3R1_FB18_Msk /*!< Filter bit 18 */
+#define CAN_F3R1_FB19_Pos (19U)
+#define CAN_F3R1_FB19_Msk (0x1U << CAN_F3R1_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F3R1_FB19 CAN_F3R1_FB19_Msk /*!< Filter bit 19 */
+#define CAN_F3R1_FB20_Pos (20U)
+#define CAN_F3R1_FB20_Msk (0x1U << CAN_F3R1_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F3R1_FB20 CAN_F3R1_FB20_Msk /*!< Filter bit 20 */
+#define CAN_F3R1_FB21_Pos (21U)
+#define CAN_F3R1_FB21_Msk (0x1U << CAN_F3R1_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F3R1_FB21 CAN_F3R1_FB21_Msk /*!< Filter bit 21 */
+#define CAN_F3R1_FB22_Pos (22U)
+#define CAN_F3R1_FB22_Msk (0x1U << CAN_F3R1_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F3R1_FB22 CAN_F3R1_FB22_Msk /*!< Filter bit 22 */
+#define CAN_F3R1_FB23_Pos (23U)
+#define CAN_F3R1_FB23_Msk (0x1U << CAN_F3R1_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F3R1_FB23 CAN_F3R1_FB23_Msk /*!< Filter bit 23 */
+#define CAN_F3R1_FB24_Pos (24U)
+#define CAN_F3R1_FB24_Msk (0x1U << CAN_F3R1_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F3R1_FB24 CAN_F3R1_FB24_Msk /*!< Filter bit 24 */
+#define CAN_F3R1_FB25_Pos (25U)
+#define CAN_F3R1_FB25_Msk (0x1U << CAN_F3R1_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F3R1_FB25 CAN_F3R1_FB25_Msk /*!< Filter bit 25 */
+#define CAN_F3R1_FB26_Pos (26U)
+#define CAN_F3R1_FB26_Msk (0x1U << CAN_F3R1_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F3R1_FB26 CAN_F3R1_FB26_Msk /*!< Filter bit 26 */
+#define CAN_F3R1_FB27_Pos (27U)
+#define CAN_F3R1_FB27_Msk (0x1U << CAN_F3R1_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F3R1_FB27 CAN_F3R1_FB27_Msk /*!< Filter bit 27 */
+#define CAN_F3R1_FB28_Pos (28U)
+#define CAN_F3R1_FB28_Msk (0x1U << CAN_F3R1_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F3R1_FB28 CAN_F3R1_FB28_Msk /*!< Filter bit 28 */
+#define CAN_F3R1_FB29_Pos (29U)
+#define CAN_F3R1_FB29_Msk (0x1U << CAN_F3R1_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F3R1_FB29 CAN_F3R1_FB29_Msk /*!< Filter bit 29 */
+#define CAN_F3R1_FB30_Pos (30U)
+#define CAN_F3R1_FB30_Msk (0x1U << CAN_F3R1_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F3R1_FB30 CAN_F3R1_FB30_Msk /*!< Filter bit 30 */
+#define CAN_F3R1_FB31_Pos (31U)
+#define CAN_F3R1_FB31_Msk (0x1U << CAN_F3R1_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F3R1_FB31 CAN_F3R1_FB31_Msk /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F4R1 register *******************/
+#define CAN_F4R1_FB0_Pos (0U)
+#define CAN_F4R1_FB0_Msk (0x1U << CAN_F4R1_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F4R1_FB0 CAN_F4R1_FB0_Msk /*!< Filter bit 0 */
+#define CAN_F4R1_FB1_Pos (1U)
+#define CAN_F4R1_FB1_Msk (0x1U << CAN_F4R1_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F4R1_FB1 CAN_F4R1_FB1_Msk /*!< Filter bit 1 */
+#define CAN_F4R1_FB2_Pos (2U)
+#define CAN_F4R1_FB2_Msk (0x1U << CAN_F4R1_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F4R1_FB2 CAN_F4R1_FB2_Msk /*!< Filter bit 2 */
+#define CAN_F4R1_FB3_Pos (3U)
+#define CAN_F4R1_FB3_Msk (0x1U << CAN_F4R1_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F4R1_FB3 CAN_F4R1_FB3_Msk /*!< Filter bit 3 */
+#define CAN_F4R1_FB4_Pos (4U)
+#define CAN_F4R1_FB4_Msk (0x1U << CAN_F4R1_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F4R1_FB4 CAN_F4R1_FB4_Msk /*!< Filter bit 4 */
+#define CAN_F4R1_FB5_Pos (5U)
+#define CAN_F4R1_FB5_Msk (0x1U << CAN_F4R1_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F4R1_FB5 CAN_F4R1_FB5_Msk /*!< Filter bit 5 */
+#define CAN_F4R1_FB6_Pos (6U)
+#define CAN_F4R1_FB6_Msk (0x1U << CAN_F4R1_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F4R1_FB6 CAN_F4R1_FB6_Msk /*!< Filter bit 6 */
+#define CAN_F4R1_FB7_Pos (7U)
+#define CAN_F4R1_FB7_Msk (0x1U << CAN_F4R1_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F4R1_FB7 CAN_F4R1_FB7_Msk /*!< Filter bit 7 */
+#define CAN_F4R1_FB8_Pos (8U)
+#define CAN_F4R1_FB8_Msk (0x1U << CAN_F4R1_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F4R1_FB8 CAN_F4R1_FB8_Msk /*!< Filter bit 8 */
+#define CAN_F4R1_FB9_Pos (9U)
+#define CAN_F4R1_FB9_Msk (0x1U << CAN_F4R1_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F4R1_FB9 CAN_F4R1_FB9_Msk /*!< Filter bit 9 */
+#define CAN_F4R1_FB10_Pos (10U)
+#define CAN_F4R1_FB10_Msk (0x1U << CAN_F4R1_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F4R1_FB10 CAN_F4R1_FB10_Msk /*!< Filter bit 10 */
+#define CAN_F4R1_FB11_Pos (11U)
+#define CAN_F4R1_FB11_Msk (0x1U << CAN_F4R1_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F4R1_FB11 CAN_F4R1_FB11_Msk /*!< Filter bit 11 */
+#define CAN_F4R1_FB12_Pos (12U)
+#define CAN_F4R1_FB12_Msk (0x1U << CAN_F4R1_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F4R1_FB12 CAN_F4R1_FB12_Msk /*!< Filter bit 12 */
+#define CAN_F4R1_FB13_Pos (13U)
+#define CAN_F4R1_FB13_Msk (0x1U << CAN_F4R1_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F4R1_FB13 CAN_F4R1_FB13_Msk /*!< Filter bit 13 */
+#define CAN_F4R1_FB14_Pos (14U)
+#define CAN_F4R1_FB14_Msk (0x1U << CAN_F4R1_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F4R1_FB14 CAN_F4R1_FB14_Msk /*!< Filter bit 14 */
+#define CAN_F4R1_FB15_Pos (15U)
+#define CAN_F4R1_FB15_Msk (0x1U << CAN_F4R1_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F4R1_FB15 CAN_F4R1_FB15_Msk /*!< Filter bit 15 */
+#define CAN_F4R1_FB16_Pos (16U)
+#define CAN_F4R1_FB16_Msk (0x1U << CAN_F4R1_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F4R1_FB16 CAN_F4R1_FB16_Msk /*!< Filter bit 16 */
+#define CAN_F4R1_FB17_Pos (17U)
+#define CAN_F4R1_FB17_Msk (0x1U << CAN_F4R1_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F4R1_FB17 CAN_F4R1_FB17_Msk /*!< Filter bit 17 */
+#define CAN_F4R1_FB18_Pos (18U)
+#define CAN_F4R1_FB18_Msk (0x1U << CAN_F4R1_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F4R1_FB18 CAN_F4R1_FB18_Msk /*!< Filter bit 18 */
+#define CAN_F4R1_FB19_Pos (19U)
+#define CAN_F4R1_FB19_Msk (0x1U << CAN_F4R1_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F4R1_FB19 CAN_F4R1_FB19_Msk /*!< Filter bit 19 */
+#define CAN_F4R1_FB20_Pos (20U)
+#define CAN_F4R1_FB20_Msk (0x1U << CAN_F4R1_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F4R1_FB20 CAN_F4R1_FB20_Msk /*!< Filter bit 20 */
+#define CAN_F4R1_FB21_Pos (21U)
+#define CAN_F4R1_FB21_Msk (0x1U << CAN_F4R1_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F4R1_FB21 CAN_F4R1_FB21_Msk /*!< Filter bit 21 */
+#define CAN_F4R1_FB22_Pos (22U)
+#define CAN_F4R1_FB22_Msk (0x1U << CAN_F4R1_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F4R1_FB22 CAN_F4R1_FB22_Msk /*!< Filter bit 22 */
+#define CAN_F4R1_FB23_Pos (23U)
+#define CAN_F4R1_FB23_Msk (0x1U << CAN_F4R1_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F4R1_FB23 CAN_F4R1_FB23_Msk /*!< Filter bit 23 */
+#define CAN_F4R1_FB24_Pos (24U)
+#define CAN_F4R1_FB24_Msk (0x1U << CAN_F4R1_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F4R1_FB24 CAN_F4R1_FB24_Msk /*!< Filter bit 24 */
+#define CAN_F4R1_FB25_Pos (25U)
+#define CAN_F4R1_FB25_Msk (0x1U << CAN_F4R1_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F4R1_FB25 CAN_F4R1_FB25_Msk /*!< Filter bit 25 */
+#define CAN_F4R1_FB26_Pos (26U)
+#define CAN_F4R1_FB26_Msk (0x1U << CAN_F4R1_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F4R1_FB26 CAN_F4R1_FB26_Msk /*!< Filter bit 26 */
+#define CAN_F4R1_FB27_Pos (27U)
+#define CAN_F4R1_FB27_Msk (0x1U << CAN_F4R1_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F4R1_FB27 CAN_F4R1_FB27_Msk /*!< Filter bit 27 */
+#define CAN_F4R1_FB28_Pos (28U)
+#define CAN_F4R1_FB28_Msk (0x1U << CAN_F4R1_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F4R1_FB28 CAN_F4R1_FB28_Msk /*!< Filter bit 28 */
+#define CAN_F4R1_FB29_Pos (29U)
+#define CAN_F4R1_FB29_Msk (0x1U << CAN_F4R1_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F4R1_FB29 CAN_F4R1_FB29_Msk /*!< Filter bit 29 */
+#define CAN_F4R1_FB30_Pos (30U)
+#define CAN_F4R1_FB30_Msk (0x1U << CAN_F4R1_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F4R1_FB30 CAN_F4R1_FB30_Msk /*!< Filter bit 30 */
+#define CAN_F4R1_FB31_Pos (31U)
+#define CAN_F4R1_FB31_Msk (0x1U << CAN_F4R1_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F4R1_FB31 CAN_F4R1_FB31_Msk /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F5R1 register *******************/
+#define CAN_F5R1_FB0_Pos (0U)
+#define CAN_F5R1_FB0_Msk (0x1U << CAN_F5R1_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F5R1_FB0 CAN_F5R1_FB0_Msk /*!< Filter bit 0 */
+#define CAN_F5R1_FB1_Pos (1U)
+#define CAN_F5R1_FB1_Msk (0x1U << CAN_F5R1_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F5R1_FB1 CAN_F5R1_FB1_Msk /*!< Filter bit 1 */
+#define CAN_F5R1_FB2_Pos (2U)
+#define CAN_F5R1_FB2_Msk (0x1U << CAN_F5R1_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F5R1_FB2 CAN_F5R1_FB2_Msk /*!< Filter bit 2 */
+#define CAN_F5R1_FB3_Pos (3U)
+#define CAN_F5R1_FB3_Msk (0x1U << CAN_F5R1_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F5R1_FB3 CAN_F5R1_FB3_Msk /*!< Filter bit 3 */
+#define CAN_F5R1_FB4_Pos (4U)
+#define CAN_F5R1_FB4_Msk (0x1U << CAN_F5R1_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F5R1_FB4 CAN_F5R1_FB4_Msk /*!< Filter bit 4 */
+#define CAN_F5R1_FB5_Pos (5U)
+#define CAN_F5R1_FB5_Msk (0x1U << CAN_F5R1_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F5R1_FB5 CAN_F5R1_FB5_Msk /*!< Filter bit 5 */
+#define CAN_F5R1_FB6_Pos (6U)
+#define CAN_F5R1_FB6_Msk (0x1U << CAN_F5R1_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F5R1_FB6 CAN_F5R1_FB6_Msk /*!< Filter bit 6 */
+#define CAN_F5R1_FB7_Pos (7U)
+#define CAN_F5R1_FB7_Msk (0x1U << CAN_F5R1_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F5R1_FB7 CAN_F5R1_FB7_Msk /*!< Filter bit 7 */
+#define CAN_F5R1_FB8_Pos (8U)
+#define CAN_F5R1_FB8_Msk (0x1U << CAN_F5R1_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F5R1_FB8 CAN_F5R1_FB8_Msk /*!< Filter bit 8 */
+#define CAN_F5R1_FB9_Pos (9U)
+#define CAN_F5R1_FB9_Msk (0x1U << CAN_F5R1_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F5R1_FB9 CAN_F5R1_FB9_Msk /*!< Filter bit 9 */
+#define CAN_F5R1_FB10_Pos (10U)
+#define CAN_F5R1_FB10_Msk (0x1U << CAN_F5R1_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F5R1_FB10 CAN_F5R1_FB10_Msk /*!< Filter bit 10 */
+#define CAN_F5R1_FB11_Pos (11U)
+#define CAN_F5R1_FB11_Msk (0x1U << CAN_F5R1_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F5R1_FB11 CAN_F5R1_FB11_Msk /*!< Filter bit 11 */
+#define CAN_F5R1_FB12_Pos (12U)
+#define CAN_F5R1_FB12_Msk (0x1U << CAN_F5R1_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F5R1_FB12 CAN_F5R1_FB12_Msk /*!< Filter bit 12 */
+#define CAN_F5R1_FB13_Pos (13U)
+#define CAN_F5R1_FB13_Msk (0x1U << CAN_F5R1_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F5R1_FB13 CAN_F5R1_FB13_Msk /*!< Filter bit 13 */
+#define CAN_F5R1_FB14_Pos (14U)
+#define CAN_F5R1_FB14_Msk (0x1U << CAN_F5R1_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F5R1_FB14 CAN_F5R1_FB14_Msk /*!< Filter bit 14 */
+#define CAN_F5R1_FB15_Pos (15U)
+#define CAN_F5R1_FB15_Msk (0x1U << CAN_F5R1_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F5R1_FB15 CAN_F5R1_FB15_Msk /*!< Filter bit 15 */
+#define CAN_F5R1_FB16_Pos (16U)
+#define CAN_F5R1_FB16_Msk (0x1U << CAN_F5R1_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F5R1_FB16 CAN_F5R1_FB16_Msk /*!< Filter bit 16 */
+#define CAN_F5R1_FB17_Pos (17U)
+#define CAN_F5R1_FB17_Msk (0x1U << CAN_F5R1_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F5R1_FB17 CAN_F5R1_FB17_Msk /*!< Filter bit 17 */
+#define CAN_F5R1_FB18_Pos (18U)
+#define CAN_F5R1_FB18_Msk (0x1U << CAN_F5R1_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F5R1_FB18 CAN_F5R1_FB18_Msk /*!< Filter bit 18 */
+#define CAN_F5R1_FB19_Pos (19U)
+#define CAN_F5R1_FB19_Msk (0x1U << CAN_F5R1_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F5R1_FB19 CAN_F5R1_FB19_Msk /*!< Filter bit 19 */
+#define CAN_F5R1_FB20_Pos (20U)
+#define CAN_F5R1_FB20_Msk (0x1U << CAN_F5R1_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F5R1_FB20 CAN_F5R1_FB20_Msk /*!< Filter bit 20 */
+#define CAN_F5R1_FB21_Pos (21U)
+#define CAN_F5R1_FB21_Msk (0x1U << CAN_F5R1_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F5R1_FB21 CAN_F5R1_FB21_Msk /*!< Filter bit 21 */
+#define CAN_F5R1_FB22_Pos (22U)
+#define CAN_F5R1_FB22_Msk (0x1U << CAN_F5R1_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F5R1_FB22 CAN_F5R1_FB22_Msk /*!< Filter bit 22 */
+#define CAN_F5R1_FB23_Pos (23U)
+#define CAN_F5R1_FB23_Msk (0x1U << CAN_F5R1_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F5R1_FB23 CAN_F5R1_FB23_Msk /*!< Filter bit 23 */
+#define CAN_F5R1_FB24_Pos (24U)
+#define CAN_F5R1_FB24_Msk (0x1U << CAN_F5R1_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F5R1_FB24 CAN_F5R1_FB24_Msk /*!< Filter bit 24 */
+#define CAN_F5R1_FB25_Pos (25U)
+#define CAN_F5R1_FB25_Msk (0x1U << CAN_F5R1_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F5R1_FB25 CAN_F5R1_FB25_Msk /*!< Filter bit 25 */
+#define CAN_F5R1_FB26_Pos (26U)
+#define CAN_F5R1_FB26_Msk (0x1U << CAN_F5R1_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F5R1_FB26 CAN_F5R1_FB26_Msk /*!< Filter bit 26 */
+#define CAN_F5R1_FB27_Pos (27U)
+#define CAN_F5R1_FB27_Msk (0x1U << CAN_F5R1_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F5R1_FB27 CAN_F5R1_FB27_Msk /*!< Filter bit 27 */
+#define CAN_F5R1_FB28_Pos (28U)
+#define CAN_F5R1_FB28_Msk (0x1U << CAN_F5R1_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F5R1_FB28 CAN_F5R1_FB28_Msk /*!< Filter bit 28 */
+#define CAN_F5R1_FB29_Pos (29U)
+#define CAN_F5R1_FB29_Msk (0x1U << CAN_F5R1_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F5R1_FB29 CAN_F5R1_FB29_Msk /*!< Filter bit 29 */
+#define CAN_F5R1_FB30_Pos (30U)
+#define CAN_F5R1_FB30_Msk (0x1U << CAN_F5R1_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F5R1_FB30 CAN_F5R1_FB30_Msk /*!< Filter bit 30 */
+#define CAN_F5R1_FB31_Pos (31U)
+#define CAN_F5R1_FB31_Msk (0x1U << CAN_F5R1_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F5R1_FB31 CAN_F5R1_FB31_Msk /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F6R1 register *******************/
+#define CAN_F6R1_FB0_Pos (0U)
+#define CAN_F6R1_FB0_Msk (0x1U << CAN_F6R1_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F6R1_FB0 CAN_F6R1_FB0_Msk /*!< Filter bit 0 */
+#define CAN_F6R1_FB1_Pos (1U)
+#define CAN_F6R1_FB1_Msk (0x1U << CAN_F6R1_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F6R1_FB1 CAN_F6R1_FB1_Msk /*!< Filter bit 1 */
+#define CAN_F6R1_FB2_Pos (2U)
+#define CAN_F6R1_FB2_Msk (0x1U << CAN_F6R1_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F6R1_FB2 CAN_F6R1_FB2_Msk /*!< Filter bit 2 */
+#define CAN_F6R1_FB3_Pos (3U)
+#define CAN_F6R1_FB3_Msk (0x1U << CAN_F6R1_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F6R1_FB3 CAN_F6R1_FB3_Msk /*!< Filter bit 3 */
+#define CAN_F6R1_FB4_Pos (4U)
+#define CAN_F6R1_FB4_Msk (0x1U << CAN_F6R1_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F6R1_FB4 CAN_F6R1_FB4_Msk /*!< Filter bit 4 */
+#define CAN_F6R1_FB5_Pos (5U)
+#define CAN_F6R1_FB5_Msk (0x1U << CAN_F6R1_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F6R1_FB5 CAN_F6R1_FB5_Msk /*!< Filter bit 5 */
+#define CAN_F6R1_FB6_Pos (6U)
+#define CAN_F6R1_FB6_Msk (0x1U << CAN_F6R1_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F6R1_FB6 CAN_F6R1_FB6_Msk /*!< Filter bit 6 */
+#define CAN_F6R1_FB7_Pos (7U)
+#define CAN_F6R1_FB7_Msk (0x1U << CAN_F6R1_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F6R1_FB7 CAN_F6R1_FB7_Msk /*!< Filter bit 7 */
+#define CAN_F6R1_FB8_Pos (8U)
+#define CAN_F6R1_FB8_Msk (0x1U << CAN_F6R1_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F6R1_FB8 CAN_F6R1_FB8_Msk /*!< Filter bit 8 */
+#define CAN_F6R1_FB9_Pos (9U)
+#define CAN_F6R1_FB9_Msk (0x1U << CAN_F6R1_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F6R1_FB9 CAN_F6R1_FB9_Msk /*!< Filter bit 9 */
+#define CAN_F6R1_FB10_Pos (10U)
+#define CAN_F6R1_FB10_Msk (0x1U << CAN_F6R1_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F6R1_FB10 CAN_F6R1_FB10_Msk /*!< Filter bit 10 */
+#define CAN_F6R1_FB11_Pos (11U)
+#define CAN_F6R1_FB11_Msk (0x1U << CAN_F6R1_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F6R1_FB11 CAN_F6R1_FB11_Msk /*!< Filter bit 11 */
+#define CAN_F6R1_FB12_Pos (12U)
+#define CAN_F6R1_FB12_Msk (0x1U << CAN_F6R1_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F6R1_FB12 CAN_F6R1_FB12_Msk /*!< Filter bit 12 */
+#define CAN_F6R1_FB13_Pos (13U)
+#define CAN_F6R1_FB13_Msk (0x1U << CAN_F6R1_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F6R1_FB13 CAN_F6R1_FB13_Msk /*!< Filter bit 13 */
+#define CAN_F6R1_FB14_Pos (14U)
+#define CAN_F6R1_FB14_Msk (0x1U << CAN_F6R1_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F6R1_FB14 CAN_F6R1_FB14_Msk /*!< Filter bit 14 */
+#define CAN_F6R1_FB15_Pos (15U)
+#define CAN_F6R1_FB15_Msk (0x1U << CAN_F6R1_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F6R1_FB15 CAN_F6R1_FB15_Msk /*!< Filter bit 15 */
+#define CAN_F6R1_FB16_Pos (16U)
+#define CAN_F6R1_FB16_Msk (0x1U << CAN_F6R1_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F6R1_FB16 CAN_F6R1_FB16_Msk /*!< Filter bit 16 */
+#define CAN_F6R1_FB17_Pos (17U)
+#define CAN_F6R1_FB17_Msk (0x1U << CAN_F6R1_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F6R1_FB17 CAN_F6R1_FB17_Msk /*!< Filter bit 17 */
+#define CAN_F6R1_FB18_Pos (18U)
+#define CAN_F6R1_FB18_Msk (0x1U << CAN_F6R1_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F6R1_FB18 CAN_F6R1_FB18_Msk /*!< Filter bit 18 */
+#define CAN_F6R1_FB19_Pos (19U)
+#define CAN_F6R1_FB19_Msk (0x1U << CAN_F6R1_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F6R1_FB19 CAN_F6R1_FB19_Msk /*!< Filter bit 19 */
+#define CAN_F6R1_FB20_Pos (20U)
+#define CAN_F6R1_FB20_Msk (0x1U << CAN_F6R1_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F6R1_FB20 CAN_F6R1_FB20_Msk /*!< Filter bit 20 */
+#define CAN_F6R1_FB21_Pos (21U)
+#define CAN_F6R1_FB21_Msk (0x1U << CAN_F6R1_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F6R1_FB21 CAN_F6R1_FB21_Msk /*!< Filter bit 21 */
+#define CAN_F6R1_FB22_Pos (22U)
+#define CAN_F6R1_FB22_Msk (0x1U << CAN_F6R1_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F6R1_FB22 CAN_F6R1_FB22_Msk /*!< Filter bit 22 */
+#define CAN_F6R1_FB23_Pos (23U)
+#define CAN_F6R1_FB23_Msk (0x1U << CAN_F6R1_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F6R1_FB23 CAN_F6R1_FB23_Msk /*!< Filter bit 23 */
+#define CAN_F6R1_FB24_Pos (24U)
+#define CAN_F6R1_FB24_Msk (0x1U << CAN_F6R1_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F6R1_FB24 CAN_F6R1_FB24_Msk /*!< Filter bit 24 */
+#define CAN_F6R1_FB25_Pos (25U)
+#define CAN_F6R1_FB25_Msk (0x1U << CAN_F6R1_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F6R1_FB25 CAN_F6R1_FB25_Msk /*!< Filter bit 25 */
+#define CAN_F6R1_FB26_Pos (26U)
+#define CAN_F6R1_FB26_Msk (0x1U << CAN_F6R1_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F6R1_FB26 CAN_F6R1_FB26_Msk /*!< Filter bit 26 */
+#define CAN_F6R1_FB27_Pos (27U)
+#define CAN_F6R1_FB27_Msk (0x1U << CAN_F6R1_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F6R1_FB27 CAN_F6R1_FB27_Msk /*!< Filter bit 27 */
+#define CAN_F6R1_FB28_Pos (28U)
+#define CAN_F6R1_FB28_Msk (0x1U << CAN_F6R1_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F6R1_FB28 CAN_F6R1_FB28_Msk /*!< Filter bit 28 */
+#define CAN_F6R1_FB29_Pos (29U)
+#define CAN_F6R1_FB29_Msk (0x1U << CAN_F6R1_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F6R1_FB29 CAN_F6R1_FB29_Msk /*!< Filter bit 29 */
+#define CAN_F6R1_FB30_Pos (30U)
+#define CAN_F6R1_FB30_Msk (0x1U << CAN_F6R1_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F6R1_FB30 CAN_F6R1_FB30_Msk /*!< Filter bit 30 */
+#define CAN_F6R1_FB31_Pos (31U)
+#define CAN_F6R1_FB31_Msk (0x1U << CAN_F6R1_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F6R1_FB31 CAN_F6R1_FB31_Msk /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F7R1 register *******************/
+#define CAN_F7R1_FB0_Pos (0U)
+#define CAN_F7R1_FB0_Msk (0x1U << CAN_F7R1_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F7R1_FB0 CAN_F7R1_FB0_Msk /*!< Filter bit 0 */
+#define CAN_F7R1_FB1_Pos (1U)
+#define CAN_F7R1_FB1_Msk (0x1U << CAN_F7R1_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F7R1_FB1 CAN_F7R1_FB1_Msk /*!< Filter bit 1 */
+#define CAN_F7R1_FB2_Pos (2U)
+#define CAN_F7R1_FB2_Msk (0x1U << CAN_F7R1_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F7R1_FB2 CAN_F7R1_FB2_Msk /*!< Filter bit 2 */
+#define CAN_F7R1_FB3_Pos (3U)
+#define CAN_F7R1_FB3_Msk (0x1U << CAN_F7R1_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F7R1_FB3 CAN_F7R1_FB3_Msk /*!< Filter bit 3 */
+#define CAN_F7R1_FB4_Pos (4U)
+#define CAN_F7R1_FB4_Msk (0x1U << CAN_F7R1_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F7R1_FB4 CAN_F7R1_FB4_Msk /*!< Filter bit 4 */
+#define CAN_F7R1_FB5_Pos (5U)
+#define CAN_F7R1_FB5_Msk (0x1U << CAN_F7R1_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F7R1_FB5 CAN_F7R1_FB5_Msk /*!< Filter bit 5 */
+#define CAN_F7R1_FB6_Pos (6U)
+#define CAN_F7R1_FB6_Msk (0x1U << CAN_F7R1_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F7R1_FB6 CAN_F7R1_FB6_Msk /*!< Filter bit 6 */
+#define CAN_F7R1_FB7_Pos (7U)
+#define CAN_F7R1_FB7_Msk (0x1U << CAN_F7R1_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F7R1_FB7 CAN_F7R1_FB7_Msk /*!< Filter bit 7 */
+#define CAN_F7R1_FB8_Pos (8U)
+#define CAN_F7R1_FB8_Msk (0x1U << CAN_F7R1_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F7R1_FB8 CAN_F7R1_FB8_Msk /*!< Filter bit 8 */
+#define CAN_F7R1_FB9_Pos (9U)
+#define CAN_F7R1_FB9_Msk (0x1U << CAN_F7R1_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F7R1_FB9 CAN_F7R1_FB9_Msk /*!< Filter bit 9 */
+#define CAN_F7R1_FB10_Pos (10U)
+#define CAN_F7R1_FB10_Msk (0x1U << CAN_F7R1_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F7R1_FB10 CAN_F7R1_FB10_Msk /*!< Filter bit 10 */
+#define CAN_F7R1_FB11_Pos (11U)
+#define CAN_F7R1_FB11_Msk (0x1U << CAN_F7R1_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F7R1_FB11 CAN_F7R1_FB11_Msk /*!< Filter bit 11 */
+#define CAN_F7R1_FB12_Pos (12U)
+#define CAN_F7R1_FB12_Msk (0x1U << CAN_F7R1_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F7R1_FB12 CAN_F7R1_FB12_Msk /*!< Filter bit 12 */
+#define CAN_F7R1_FB13_Pos (13U)
+#define CAN_F7R1_FB13_Msk (0x1U << CAN_F7R1_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F7R1_FB13 CAN_F7R1_FB13_Msk /*!< Filter bit 13 */
+#define CAN_F7R1_FB14_Pos (14U)
+#define CAN_F7R1_FB14_Msk (0x1U << CAN_F7R1_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F7R1_FB14 CAN_F7R1_FB14_Msk /*!< Filter bit 14 */
+#define CAN_F7R1_FB15_Pos (15U)
+#define CAN_F7R1_FB15_Msk (0x1U << CAN_F7R1_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F7R1_FB15 CAN_F7R1_FB15_Msk /*!< Filter bit 15 */
+#define CAN_F7R1_FB16_Pos (16U)
+#define CAN_F7R1_FB16_Msk (0x1U << CAN_F7R1_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F7R1_FB16 CAN_F7R1_FB16_Msk /*!< Filter bit 16 */
+#define CAN_F7R1_FB17_Pos (17U)
+#define CAN_F7R1_FB17_Msk (0x1U << CAN_F7R1_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F7R1_FB17 CAN_F7R1_FB17_Msk /*!< Filter bit 17 */
+#define CAN_F7R1_FB18_Pos (18U)
+#define CAN_F7R1_FB18_Msk (0x1U << CAN_F7R1_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F7R1_FB18 CAN_F7R1_FB18_Msk /*!< Filter bit 18 */
+#define CAN_F7R1_FB19_Pos (19U)
+#define CAN_F7R1_FB19_Msk (0x1U << CAN_F7R1_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F7R1_FB19 CAN_F7R1_FB19_Msk /*!< Filter bit 19 */
+#define CAN_F7R1_FB20_Pos (20U)
+#define CAN_F7R1_FB20_Msk (0x1U << CAN_F7R1_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F7R1_FB20 CAN_F7R1_FB20_Msk /*!< Filter bit 20 */
+#define CAN_F7R1_FB21_Pos (21U)
+#define CAN_F7R1_FB21_Msk (0x1U << CAN_F7R1_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F7R1_FB21 CAN_F7R1_FB21_Msk /*!< Filter bit 21 */
+#define CAN_F7R1_FB22_Pos (22U)
+#define CAN_F7R1_FB22_Msk (0x1U << CAN_F7R1_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F7R1_FB22 CAN_F7R1_FB22_Msk /*!< Filter bit 22 */
+#define CAN_F7R1_FB23_Pos (23U)
+#define CAN_F7R1_FB23_Msk (0x1U << CAN_F7R1_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F7R1_FB23 CAN_F7R1_FB23_Msk /*!< Filter bit 23 */
+#define CAN_F7R1_FB24_Pos (24U)
+#define CAN_F7R1_FB24_Msk (0x1U << CAN_F7R1_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F7R1_FB24 CAN_F7R1_FB24_Msk /*!< Filter bit 24 */
+#define CAN_F7R1_FB25_Pos (25U)
+#define CAN_F7R1_FB25_Msk (0x1U << CAN_F7R1_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F7R1_FB25 CAN_F7R1_FB25_Msk /*!< Filter bit 25 */
+#define CAN_F7R1_FB26_Pos (26U)
+#define CAN_F7R1_FB26_Msk (0x1U << CAN_F7R1_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F7R1_FB26 CAN_F7R1_FB26_Msk /*!< Filter bit 26 */
+#define CAN_F7R1_FB27_Pos (27U)
+#define CAN_F7R1_FB27_Msk (0x1U << CAN_F7R1_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F7R1_FB27 CAN_F7R1_FB27_Msk /*!< Filter bit 27 */
+#define CAN_F7R1_FB28_Pos (28U)
+#define CAN_F7R1_FB28_Msk (0x1U << CAN_F7R1_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F7R1_FB28 CAN_F7R1_FB28_Msk /*!< Filter bit 28 */
+#define CAN_F7R1_FB29_Pos (29U)
+#define CAN_F7R1_FB29_Msk (0x1U << CAN_F7R1_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F7R1_FB29 CAN_F7R1_FB29_Msk /*!< Filter bit 29 */
+#define CAN_F7R1_FB30_Pos (30U)
+#define CAN_F7R1_FB30_Msk (0x1U << CAN_F7R1_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F7R1_FB30 CAN_F7R1_FB30_Msk /*!< Filter bit 30 */
+#define CAN_F7R1_FB31_Pos (31U)
+#define CAN_F7R1_FB31_Msk (0x1U << CAN_F7R1_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F7R1_FB31 CAN_F7R1_FB31_Msk /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F8R1 register *******************/
+#define CAN_F8R1_FB0_Pos (0U)
+#define CAN_F8R1_FB0_Msk (0x1U << CAN_F8R1_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F8R1_FB0 CAN_F8R1_FB0_Msk /*!< Filter bit 0 */
+#define CAN_F8R1_FB1_Pos (1U)
+#define CAN_F8R1_FB1_Msk (0x1U << CAN_F8R1_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F8R1_FB1 CAN_F8R1_FB1_Msk /*!< Filter bit 1 */
+#define CAN_F8R1_FB2_Pos (2U)
+#define CAN_F8R1_FB2_Msk (0x1U << CAN_F8R1_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F8R1_FB2 CAN_F8R1_FB2_Msk /*!< Filter bit 2 */
+#define CAN_F8R1_FB3_Pos (3U)
+#define CAN_F8R1_FB3_Msk (0x1U << CAN_F8R1_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F8R1_FB3 CAN_F8R1_FB3_Msk /*!< Filter bit 3 */
+#define CAN_F8R1_FB4_Pos (4U)
+#define CAN_F8R1_FB4_Msk (0x1U << CAN_F8R1_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F8R1_FB4 CAN_F8R1_FB4_Msk /*!< Filter bit 4 */
+#define CAN_F8R1_FB5_Pos (5U)
+#define CAN_F8R1_FB5_Msk (0x1U << CAN_F8R1_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F8R1_FB5 CAN_F8R1_FB5_Msk /*!< Filter bit 5 */
+#define CAN_F8R1_FB6_Pos (6U)
+#define CAN_F8R1_FB6_Msk (0x1U << CAN_F8R1_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F8R1_FB6 CAN_F8R1_FB6_Msk /*!< Filter bit 6 */
+#define CAN_F8R1_FB7_Pos (7U)
+#define CAN_F8R1_FB7_Msk (0x1U << CAN_F8R1_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F8R1_FB7 CAN_F8R1_FB7_Msk /*!< Filter bit 7 */
+#define CAN_F8R1_FB8_Pos (8U)
+#define CAN_F8R1_FB8_Msk (0x1U << CAN_F8R1_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F8R1_FB8 CAN_F8R1_FB8_Msk /*!< Filter bit 8 */
+#define CAN_F8R1_FB9_Pos (9U)
+#define CAN_F8R1_FB9_Msk (0x1U << CAN_F8R1_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F8R1_FB9 CAN_F8R1_FB9_Msk /*!< Filter bit 9 */
+#define CAN_F8R1_FB10_Pos (10U)
+#define CAN_F8R1_FB10_Msk (0x1U << CAN_F8R1_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F8R1_FB10 CAN_F8R1_FB10_Msk /*!< Filter bit 10 */
+#define CAN_F8R1_FB11_Pos (11U)
+#define CAN_F8R1_FB11_Msk (0x1U << CAN_F8R1_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F8R1_FB11 CAN_F8R1_FB11_Msk /*!< Filter bit 11 */
+#define CAN_F8R1_FB12_Pos (12U)
+#define CAN_F8R1_FB12_Msk (0x1U << CAN_F8R1_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F8R1_FB12 CAN_F8R1_FB12_Msk /*!< Filter bit 12 */
+#define CAN_F8R1_FB13_Pos (13U)
+#define CAN_F8R1_FB13_Msk (0x1U << CAN_F8R1_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F8R1_FB13 CAN_F8R1_FB13_Msk /*!< Filter bit 13 */
+#define CAN_F8R1_FB14_Pos (14U)
+#define CAN_F8R1_FB14_Msk (0x1U << CAN_F8R1_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F8R1_FB14 CAN_F8R1_FB14_Msk /*!< Filter bit 14 */
+#define CAN_F8R1_FB15_Pos (15U)
+#define CAN_F8R1_FB15_Msk (0x1U << CAN_F8R1_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F8R1_FB15 CAN_F8R1_FB15_Msk /*!< Filter bit 15 */
+#define CAN_F8R1_FB16_Pos (16U)
+#define CAN_F8R1_FB16_Msk (0x1U << CAN_F8R1_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F8R1_FB16 CAN_F8R1_FB16_Msk /*!< Filter bit 16 */
+#define CAN_F8R1_FB17_Pos (17U)
+#define CAN_F8R1_FB17_Msk (0x1U << CAN_F8R1_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F8R1_FB17 CAN_F8R1_FB17_Msk /*!< Filter bit 17 */
+#define CAN_F8R1_FB18_Pos (18U)
+#define CAN_F8R1_FB18_Msk (0x1U << CAN_F8R1_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F8R1_FB18 CAN_F8R1_FB18_Msk /*!< Filter bit 18 */
+#define CAN_F8R1_FB19_Pos (19U)
+#define CAN_F8R1_FB19_Msk (0x1U << CAN_F8R1_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F8R1_FB19 CAN_F8R1_FB19_Msk /*!< Filter bit 19 */
+#define CAN_F8R1_FB20_Pos (20U)
+#define CAN_F8R1_FB20_Msk (0x1U << CAN_F8R1_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F8R1_FB20 CAN_F8R1_FB20_Msk /*!< Filter bit 20 */
+#define CAN_F8R1_FB21_Pos (21U)
+#define CAN_F8R1_FB21_Msk (0x1U << CAN_F8R1_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F8R1_FB21 CAN_F8R1_FB21_Msk /*!< Filter bit 21 */
+#define CAN_F8R1_FB22_Pos (22U)
+#define CAN_F8R1_FB22_Msk (0x1U << CAN_F8R1_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F8R1_FB22 CAN_F8R1_FB22_Msk /*!< Filter bit 22 */
+#define CAN_F8R1_FB23_Pos (23U)
+#define CAN_F8R1_FB23_Msk (0x1U << CAN_F8R1_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F8R1_FB23 CAN_F8R1_FB23_Msk /*!< Filter bit 23 */
+#define CAN_F8R1_FB24_Pos (24U)
+#define CAN_F8R1_FB24_Msk (0x1U << CAN_F8R1_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F8R1_FB24 CAN_F8R1_FB24_Msk /*!< Filter bit 24 */
+#define CAN_F8R1_FB25_Pos (25U)
+#define CAN_F8R1_FB25_Msk (0x1U << CAN_F8R1_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F8R1_FB25 CAN_F8R1_FB25_Msk /*!< Filter bit 25 */
+#define CAN_F8R1_FB26_Pos (26U)
+#define CAN_F8R1_FB26_Msk (0x1U << CAN_F8R1_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F8R1_FB26 CAN_F8R1_FB26_Msk /*!< Filter bit 26 */
+#define CAN_F8R1_FB27_Pos (27U)
+#define CAN_F8R1_FB27_Msk (0x1U << CAN_F8R1_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F8R1_FB27 CAN_F8R1_FB27_Msk /*!< Filter bit 27 */
+#define CAN_F8R1_FB28_Pos (28U)
+#define CAN_F8R1_FB28_Msk (0x1U << CAN_F8R1_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F8R1_FB28 CAN_F8R1_FB28_Msk /*!< Filter bit 28 */
+#define CAN_F8R1_FB29_Pos (29U)
+#define CAN_F8R1_FB29_Msk (0x1U << CAN_F8R1_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F8R1_FB29 CAN_F8R1_FB29_Msk /*!< Filter bit 29 */
+#define CAN_F8R1_FB30_Pos (30U)
+#define CAN_F8R1_FB30_Msk (0x1U << CAN_F8R1_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F8R1_FB30 CAN_F8R1_FB30_Msk /*!< Filter bit 30 */
+#define CAN_F8R1_FB31_Pos (31U)
+#define CAN_F8R1_FB31_Msk (0x1U << CAN_F8R1_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F8R1_FB31 CAN_F8R1_FB31_Msk /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F9R1 register *******************/
+#define CAN_F9R1_FB0_Pos (0U)
+#define CAN_F9R1_FB0_Msk (0x1U << CAN_F9R1_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F9R1_FB0 CAN_F9R1_FB0_Msk /*!< Filter bit 0 */
+#define CAN_F9R1_FB1_Pos (1U)
+#define CAN_F9R1_FB1_Msk (0x1U << CAN_F9R1_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F9R1_FB1 CAN_F9R1_FB1_Msk /*!< Filter bit 1 */
+#define CAN_F9R1_FB2_Pos (2U)
+#define CAN_F9R1_FB2_Msk (0x1U << CAN_F9R1_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F9R1_FB2 CAN_F9R1_FB2_Msk /*!< Filter bit 2 */
+#define CAN_F9R1_FB3_Pos (3U)
+#define CAN_F9R1_FB3_Msk (0x1U << CAN_F9R1_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F9R1_FB3 CAN_F9R1_FB3_Msk /*!< Filter bit 3 */
+#define CAN_F9R1_FB4_Pos (4U)
+#define CAN_F9R1_FB4_Msk (0x1U << CAN_F9R1_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F9R1_FB4 CAN_F9R1_FB4_Msk /*!< Filter bit 4 */
+#define CAN_F9R1_FB5_Pos (5U)
+#define CAN_F9R1_FB5_Msk (0x1U << CAN_F9R1_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F9R1_FB5 CAN_F9R1_FB5_Msk /*!< Filter bit 5 */
+#define CAN_F9R1_FB6_Pos (6U)
+#define CAN_F9R1_FB6_Msk (0x1U << CAN_F9R1_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F9R1_FB6 CAN_F9R1_FB6_Msk /*!< Filter bit 6 */
+#define CAN_F9R1_FB7_Pos (7U)
+#define CAN_F9R1_FB7_Msk (0x1U << CAN_F9R1_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F9R1_FB7 CAN_F9R1_FB7_Msk /*!< Filter bit 7 */
+#define CAN_F9R1_FB8_Pos (8U)
+#define CAN_F9R1_FB8_Msk (0x1U << CAN_F9R1_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F9R1_FB8 CAN_F9R1_FB8_Msk /*!< Filter bit 8 */
+#define CAN_F9R1_FB9_Pos (9U)
+#define CAN_F9R1_FB9_Msk (0x1U << CAN_F9R1_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F9R1_FB9 CAN_F9R1_FB9_Msk /*!< Filter bit 9 */
+#define CAN_F9R1_FB10_Pos (10U)
+#define CAN_F9R1_FB10_Msk (0x1U << CAN_F9R1_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F9R1_FB10 CAN_F9R1_FB10_Msk /*!< Filter bit 10 */
+#define CAN_F9R1_FB11_Pos (11U)
+#define CAN_F9R1_FB11_Msk (0x1U << CAN_F9R1_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F9R1_FB11 CAN_F9R1_FB11_Msk /*!< Filter bit 11 */
+#define CAN_F9R1_FB12_Pos (12U)
+#define CAN_F9R1_FB12_Msk (0x1U << CAN_F9R1_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F9R1_FB12 CAN_F9R1_FB12_Msk /*!< Filter bit 12 */
+#define CAN_F9R1_FB13_Pos (13U)
+#define CAN_F9R1_FB13_Msk (0x1U << CAN_F9R1_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F9R1_FB13 CAN_F9R1_FB13_Msk /*!< Filter bit 13 */
+#define CAN_F9R1_FB14_Pos (14U)
+#define CAN_F9R1_FB14_Msk (0x1U << CAN_F9R1_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F9R1_FB14 CAN_F9R1_FB14_Msk /*!< Filter bit 14 */
+#define CAN_F9R1_FB15_Pos (15U)
+#define CAN_F9R1_FB15_Msk (0x1U << CAN_F9R1_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F9R1_FB15 CAN_F9R1_FB15_Msk /*!< Filter bit 15 */
+#define CAN_F9R1_FB16_Pos (16U)
+#define CAN_F9R1_FB16_Msk (0x1U << CAN_F9R1_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F9R1_FB16 CAN_F9R1_FB16_Msk /*!< Filter bit 16 */
+#define CAN_F9R1_FB17_Pos (17U)
+#define CAN_F9R1_FB17_Msk (0x1U << CAN_F9R1_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F9R1_FB17 CAN_F9R1_FB17_Msk /*!< Filter bit 17 */
+#define CAN_F9R1_FB18_Pos (18U)
+#define CAN_F9R1_FB18_Msk (0x1U << CAN_F9R1_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F9R1_FB18 CAN_F9R1_FB18_Msk /*!< Filter bit 18 */
+#define CAN_F9R1_FB19_Pos (19U)
+#define CAN_F9R1_FB19_Msk (0x1U << CAN_F9R1_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F9R1_FB19 CAN_F9R1_FB19_Msk /*!< Filter bit 19 */
+#define CAN_F9R1_FB20_Pos (20U)
+#define CAN_F9R1_FB20_Msk (0x1U << CAN_F9R1_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F9R1_FB20 CAN_F9R1_FB20_Msk /*!< Filter bit 20 */
+#define CAN_F9R1_FB21_Pos (21U)
+#define CAN_F9R1_FB21_Msk (0x1U << CAN_F9R1_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F9R1_FB21 CAN_F9R1_FB21_Msk /*!< Filter bit 21 */
+#define CAN_F9R1_FB22_Pos (22U)
+#define CAN_F9R1_FB22_Msk (0x1U << CAN_F9R1_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F9R1_FB22 CAN_F9R1_FB22_Msk /*!< Filter bit 22 */
+#define CAN_F9R1_FB23_Pos (23U)
+#define CAN_F9R1_FB23_Msk (0x1U << CAN_F9R1_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F9R1_FB23 CAN_F9R1_FB23_Msk /*!< Filter bit 23 */
+#define CAN_F9R1_FB24_Pos (24U)
+#define CAN_F9R1_FB24_Msk (0x1U << CAN_F9R1_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F9R1_FB24 CAN_F9R1_FB24_Msk /*!< Filter bit 24 */
+#define CAN_F9R1_FB25_Pos (25U)
+#define CAN_F9R1_FB25_Msk (0x1U << CAN_F9R1_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F9R1_FB25 CAN_F9R1_FB25_Msk /*!< Filter bit 25 */
+#define CAN_F9R1_FB26_Pos (26U)
+#define CAN_F9R1_FB26_Msk (0x1U << CAN_F9R1_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F9R1_FB26 CAN_F9R1_FB26_Msk /*!< Filter bit 26 */
+#define CAN_F9R1_FB27_Pos (27U)
+#define CAN_F9R1_FB27_Msk (0x1U << CAN_F9R1_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F9R1_FB27 CAN_F9R1_FB27_Msk /*!< Filter bit 27 */
+#define CAN_F9R1_FB28_Pos (28U)
+#define CAN_F9R1_FB28_Msk (0x1U << CAN_F9R1_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F9R1_FB28 CAN_F9R1_FB28_Msk /*!< Filter bit 28 */
+#define CAN_F9R1_FB29_Pos (29U)
+#define CAN_F9R1_FB29_Msk (0x1U << CAN_F9R1_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F9R1_FB29 CAN_F9R1_FB29_Msk /*!< Filter bit 29 */
+#define CAN_F9R1_FB30_Pos (30U)
+#define CAN_F9R1_FB30_Msk (0x1U << CAN_F9R1_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F9R1_FB30 CAN_F9R1_FB30_Msk /*!< Filter bit 30 */
+#define CAN_F9R1_FB31_Pos (31U)
+#define CAN_F9R1_FB31_Msk (0x1U << CAN_F9R1_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F9R1_FB31 CAN_F9R1_FB31_Msk /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F10R1 register ******************/
+#define CAN_F10R1_FB0_Pos (0U)
+#define CAN_F10R1_FB0_Msk (0x1U << CAN_F10R1_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F10R1_FB0 CAN_F10R1_FB0_Msk /*!< Filter bit 0 */
+#define CAN_F10R1_FB1_Pos (1U)
+#define CAN_F10R1_FB1_Msk (0x1U << CAN_F10R1_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F10R1_FB1 CAN_F10R1_FB1_Msk /*!< Filter bit 1 */
+#define CAN_F10R1_FB2_Pos (2U)
+#define CAN_F10R1_FB2_Msk (0x1U << CAN_F10R1_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F10R1_FB2 CAN_F10R1_FB2_Msk /*!< Filter bit 2 */
+#define CAN_F10R1_FB3_Pos (3U)
+#define CAN_F10R1_FB3_Msk (0x1U << CAN_F10R1_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F10R1_FB3 CAN_F10R1_FB3_Msk /*!< Filter bit 3 */
+#define CAN_F10R1_FB4_Pos (4U)
+#define CAN_F10R1_FB4_Msk (0x1U << CAN_F10R1_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F10R1_FB4 CAN_F10R1_FB4_Msk /*!< Filter bit 4 */
+#define CAN_F10R1_FB5_Pos (5U)
+#define CAN_F10R1_FB5_Msk (0x1U << CAN_F10R1_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F10R1_FB5 CAN_F10R1_FB5_Msk /*!< Filter bit 5 */
+#define CAN_F10R1_FB6_Pos (6U)
+#define CAN_F10R1_FB6_Msk (0x1U << CAN_F10R1_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F10R1_FB6 CAN_F10R1_FB6_Msk /*!< Filter bit 6 */
+#define CAN_F10R1_FB7_Pos (7U)
+#define CAN_F10R1_FB7_Msk (0x1U << CAN_F10R1_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F10R1_FB7 CAN_F10R1_FB7_Msk /*!< Filter bit 7 */
+#define CAN_F10R1_FB8_Pos (8U)
+#define CAN_F10R1_FB8_Msk (0x1U << CAN_F10R1_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F10R1_FB8 CAN_F10R1_FB8_Msk /*!< Filter bit 8 */
+#define CAN_F10R1_FB9_Pos (9U)
+#define CAN_F10R1_FB9_Msk (0x1U << CAN_F10R1_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F10R1_FB9 CAN_F10R1_FB9_Msk /*!< Filter bit 9 */
+#define CAN_F10R1_FB10_Pos (10U)
+#define CAN_F10R1_FB10_Msk (0x1U << CAN_F10R1_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F10R1_FB10 CAN_F10R1_FB10_Msk /*!< Filter bit 10 */
+#define CAN_F10R1_FB11_Pos (11U)
+#define CAN_F10R1_FB11_Msk (0x1U << CAN_F10R1_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F10R1_FB11 CAN_F10R1_FB11_Msk /*!< Filter bit 11 */
+#define CAN_F10R1_FB12_Pos (12U)
+#define CAN_F10R1_FB12_Msk (0x1U << CAN_F10R1_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F10R1_FB12 CAN_F10R1_FB12_Msk /*!< Filter bit 12 */
+#define CAN_F10R1_FB13_Pos (13U)
+#define CAN_F10R1_FB13_Msk (0x1U << CAN_F10R1_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F10R1_FB13 CAN_F10R1_FB13_Msk /*!< Filter bit 13 */
+#define CAN_F10R1_FB14_Pos (14U)
+#define CAN_F10R1_FB14_Msk (0x1U << CAN_F10R1_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F10R1_FB14 CAN_F10R1_FB14_Msk /*!< Filter bit 14 */
+#define CAN_F10R1_FB15_Pos (15U)
+#define CAN_F10R1_FB15_Msk (0x1U << CAN_F10R1_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F10R1_FB15 CAN_F10R1_FB15_Msk /*!< Filter bit 15 */
+#define CAN_F10R1_FB16_Pos (16U)
+#define CAN_F10R1_FB16_Msk (0x1U << CAN_F10R1_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F10R1_FB16 CAN_F10R1_FB16_Msk /*!< Filter bit 16 */
+#define CAN_F10R1_FB17_Pos (17U)
+#define CAN_F10R1_FB17_Msk (0x1U << CAN_F10R1_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F10R1_FB17 CAN_F10R1_FB17_Msk /*!< Filter bit 17 */
+#define CAN_F10R1_FB18_Pos (18U)
+#define CAN_F10R1_FB18_Msk (0x1U << CAN_F10R1_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F10R1_FB18 CAN_F10R1_FB18_Msk /*!< Filter bit 18 */
+#define CAN_F10R1_FB19_Pos (19U)
+#define CAN_F10R1_FB19_Msk (0x1U << CAN_F10R1_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F10R1_FB19 CAN_F10R1_FB19_Msk /*!< Filter bit 19 */
+#define CAN_F10R1_FB20_Pos (20U)
+#define CAN_F10R1_FB20_Msk (0x1U << CAN_F10R1_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F10R1_FB20 CAN_F10R1_FB20_Msk /*!< Filter bit 20 */
+#define CAN_F10R1_FB21_Pos (21U)
+#define CAN_F10R1_FB21_Msk (0x1U << CAN_F10R1_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F10R1_FB21 CAN_F10R1_FB21_Msk /*!< Filter bit 21 */
+#define CAN_F10R1_FB22_Pos (22U)
+#define CAN_F10R1_FB22_Msk (0x1U << CAN_F10R1_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F10R1_FB22 CAN_F10R1_FB22_Msk /*!< Filter bit 22 */
+#define CAN_F10R1_FB23_Pos (23U)
+#define CAN_F10R1_FB23_Msk (0x1U << CAN_F10R1_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F10R1_FB23 CAN_F10R1_FB23_Msk /*!< Filter bit 23 */
+#define CAN_F10R1_FB24_Pos (24U)
+#define CAN_F10R1_FB24_Msk (0x1U << CAN_F10R1_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F10R1_FB24 CAN_F10R1_FB24_Msk /*!< Filter bit 24 */
+#define CAN_F10R1_FB25_Pos (25U)
+#define CAN_F10R1_FB25_Msk (0x1U << CAN_F10R1_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F10R1_FB25 CAN_F10R1_FB25_Msk /*!< Filter bit 25 */
+#define CAN_F10R1_FB26_Pos (26U)
+#define CAN_F10R1_FB26_Msk (0x1U << CAN_F10R1_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F10R1_FB26 CAN_F10R1_FB26_Msk /*!< Filter bit 26 */
+#define CAN_F10R1_FB27_Pos (27U)
+#define CAN_F10R1_FB27_Msk (0x1U << CAN_F10R1_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F10R1_FB27 CAN_F10R1_FB27_Msk /*!< Filter bit 27 */
+#define CAN_F10R1_FB28_Pos (28U)
+#define CAN_F10R1_FB28_Msk (0x1U << CAN_F10R1_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F10R1_FB28 CAN_F10R1_FB28_Msk /*!< Filter bit 28 */
+#define CAN_F10R1_FB29_Pos (29U)
+#define CAN_F10R1_FB29_Msk (0x1U << CAN_F10R1_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F10R1_FB29 CAN_F10R1_FB29_Msk /*!< Filter bit 29 */
+#define CAN_F10R1_FB30_Pos (30U)
+#define CAN_F10R1_FB30_Msk (0x1U << CAN_F10R1_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F10R1_FB30 CAN_F10R1_FB30_Msk /*!< Filter bit 30 */
+#define CAN_F10R1_FB31_Pos (31U)
+#define CAN_F10R1_FB31_Msk (0x1U << CAN_F10R1_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F10R1_FB31 CAN_F10R1_FB31_Msk /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F11R1 register ******************/
+#define CAN_F11R1_FB0_Pos (0U)
+#define CAN_F11R1_FB0_Msk (0x1U << CAN_F11R1_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F11R1_FB0 CAN_F11R1_FB0_Msk /*!< Filter bit 0 */
+#define CAN_F11R1_FB1_Pos (1U)
+#define CAN_F11R1_FB1_Msk (0x1U << CAN_F11R1_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F11R1_FB1 CAN_F11R1_FB1_Msk /*!< Filter bit 1 */
+#define CAN_F11R1_FB2_Pos (2U)
+#define CAN_F11R1_FB2_Msk (0x1U << CAN_F11R1_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F11R1_FB2 CAN_F11R1_FB2_Msk /*!< Filter bit 2 */
+#define CAN_F11R1_FB3_Pos (3U)
+#define CAN_F11R1_FB3_Msk (0x1U << CAN_F11R1_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F11R1_FB3 CAN_F11R1_FB3_Msk /*!< Filter bit 3 */
+#define CAN_F11R1_FB4_Pos (4U)
+#define CAN_F11R1_FB4_Msk (0x1U << CAN_F11R1_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F11R1_FB4 CAN_F11R1_FB4_Msk /*!< Filter bit 4 */
+#define CAN_F11R1_FB5_Pos (5U)
+#define CAN_F11R1_FB5_Msk (0x1U << CAN_F11R1_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F11R1_FB5 CAN_F11R1_FB5_Msk /*!< Filter bit 5 */
+#define CAN_F11R1_FB6_Pos (6U)
+#define CAN_F11R1_FB6_Msk (0x1U << CAN_F11R1_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F11R1_FB6 CAN_F11R1_FB6_Msk /*!< Filter bit 6 */
+#define CAN_F11R1_FB7_Pos (7U)
+#define CAN_F11R1_FB7_Msk (0x1U << CAN_F11R1_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F11R1_FB7 CAN_F11R1_FB7_Msk /*!< Filter bit 7 */
+#define CAN_F11R1_FB8_Pos (8U)
+#define CAN_F11R1_FB8_Msk (0x1U << CAN_F11R1_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F11R1_FB8 CAN_F11R1_FB8_Msk /*!< Filter bit 8 */
+#define CAN_F11R1_FB9_Pos (9U)
+#define CAN_F11R1_FB9_Msk (0x1U << CAN_F11R1_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F11R1_FB9 CAN_F11R1_FB9_Msk /*!< Filter bit 9 */
+#define CAN_F11R1_FB10_Pos (10U)
+#define CAN_F11R1_FB10_Msk (0x1U << CAN_F11R1_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F11R1_FB10 CAN_F11R1_FB10_Msk /*!< Filter bit 10 */
+#define CAN_F11R1_FB11_Pos (11U)
+#define CAN_F11R1_FB11_Msk (0x1U << CAN_F11R1_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F11R1_FB11 CAN_F11R1_FB11_Msk /*!< Filter bit 11 */
+#define CAN_F11R1_FB12_Pos (12U)
+#define CAN_F11R1_FB12_Msk (0x1U << CAN_F11R1_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F11R1_FB12 CAN_F11R1_FB12_Msk /*!< Filter bit 12 */
+#define CAN_F11R1_FB13_Pos (13U)
+#define CAN_F11R1_FB13_Msk (0x1U << CAN_F11R1_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F11R1_FB13 CAN_F11R1_FB13_Msk /*!< Filter bit 13 */
+#define CAN_F11R1_FB14_Pos (14U)
+#define CAN_F11R1_FB14_Msk (0x1U << CAN_F11R1_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F11R1_FB14 CAN_F11R1_FB14_Msk /*!< Filter bit 14 */
+#define CAN_F11R1_FB15_Pos (15U)
+#define CAN_F11R1_FB15_Msk (0x1U << CAN_F11R1_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F11R1_FB15 CAN_F11R1_FB15_Msk /*!< Filter bit 15 */
+#define CAN_F11R1_FB16_Pos (16U)
+#define CAN_F11R1_FB16_Msk (0x1U << CAN_F11R1_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F11R1_FB16 CAN_F11R1_FB16_Msk /*!< Filter bit 16 */
+#define CAN_F11R1_FB17_Pos (17U)
+#define CAN_F11R1_FB17_Msk (0x1U << CAN_F11R1_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F11R1_FB17 CAN_F11R1_FB17_Msk /*!< Filter bit 17 */
+#define CAN_F11R1_FB18_Pos (18U)
+#define CAN_F11R1_FB18_Msk (0x1U << CAN_F11R1_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F11R1_FB18 CAN_F11R1_FB18_Msk /*!< Filter bit 18 */
+#define CAN_F11R1_FB19_Pos (19U)
+#define CAN_F11R1_FB19_Msk (0x1U << CAN_F11R1_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F11R1_FB19 CAN_F11R1_FB19_Msk /*!< Filter bit 19 */
+#define CAN_F11R1_FB20_Pos (20U)
+#define CAN_F11R1_FB20_Msk (0x1U << CAN_F11R1_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F11R1_FB20 CAN_F11R1_FB20_Msk /*!< Filter bit 20 */
+#define CAN_F11R1_FB21_Pos (21U)
+#define CAN_F11R1_FB21_Msk (0x1U << CAN_F11R1_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F11R1_FB21 CAN_F11R1_FB21_Msk /*!< Filter bit 21 */
+#define CAN_F11R1_FB22_Pos (22U)
+#define CAN_F11R1_FB22_Msk (0x1U << CAN_F11R1_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F11R1_FB22 CAN_F11R1_FB22_Msk /*!< Filter bit 22 */
+#define CAN_F11R1_FB23_Pos (23U)
+#define CAN_F11R1_FB23_Msk (0x1U << CAN_F11R1_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F11R1_FB23 CAN_F11R1_FB23_Msk /*!< Filter bit 23 */
+#define CAN_F11R1_FB24_Pos (24U)
+#define CAN_F11R1_FB24_Msk (0x1U << CAN_F11R1_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F11R1_FB24 CAN_F11R1_FB24_Msk /*!< Filter bit 24 */
+#define CAN_F11R1_FB25_Pos (25U)
+#define CAN_F11R1_FB25_Msk (0x1U << CAN_F11R1_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F11R1_FB25 CAN_F11R1_FB25_Msk /*!< Filter bit 25 */
+#define CAN_F11R1_FB26_Pos (26U)
+#define CAN_F11R1_FB26_Msk (0x1U << CAN_F11R1_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F11R1_FB26 CAN_F11R1_FB26_Msk /*!< Filter bit 26 */
+#define CAN_F11R1_FB27_Pos (27U)
+#define CAN_F11R1_FB27_Msk (0x1U << CAN_F11R1_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F11R1_FB27 CAN_F11R1_FB27_Msk /*!< Filter bit 27 */
+#define CAN_F11R1_FB28_Pos (28U)
+#define CAN_F11R1_FB28_Msk (0x1U << CAN_F11R1_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F11R1_FB28 CAN_F11R1_FB28_Msk /*!< Filter bit 28 */
+#define CAN_F11R1_FB29_Pos (29U)
+#define CAN_F11R1_FB29_Msk (0x1U << CAN_F11R1_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F11R1_FB29 CAN_F11R1_FB29_Msk /*!< Filter bit 29 */
+#define CAN_F11R1_FB30_Pos (30U)
+#define CAN_F11R1_FB30_Msk (0x1U << CAN_F11R1_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F11R1_FB30 CAN_F11R1_FB30_Msk /*!< Filter bit 30 */
+#define CAN_F11R1_FB31_Pos (31U)
+#define CAN_F11R1_FB31_Msk (0x1U << CAN_F11R1_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F11R1_FB31 CAN_F11R1_FB31_Msk /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F12R1 register ******************/
+#define CAN_F12R1_FB0_Pos (0U)
+#define CAN_F12R1_FB0_Msk (0x1U << CAN_F12R1_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F12R1_FB0 CAN_F12R1_FB0_Msk /*!< Filter bit 0 */
+#define CAN_F12R1_FB1_Pos (1U)
+#define CAN_F12R1_FB1_Msk (0x1U << CAN_F12R1_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F12R1_FB1 CAN_F12R1_FB1_Msk /*!< Filter bit 1 */
+#define CAN_F12R1_FB2_Pos (2U)
+#define CAN_F12R1_FB2_Msk (0x1U << CAN_F12R1_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F12R1_FB2 CAN_F12R1_FB2_Msk /*!< Filter bit 2 */
+#define CAN_F12R1_FB3_Pos (3U)
+#define CAN_F12R1_FB3_Msk (0x1U << CAN_F12R1_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F12R1_FB3 CAN_F12R1_FB3_Msk /*!< Filter bit 3 */
+#define CAN_F12R1_FB4_Pos (4U)
+#define CAN_F12R1_FB4_Msk (0x1U << CAN_F12R1_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F12R1_FB4 CAN_F12R1_FB4_Msk /*!< Filter bit 4 */
+#define CAN_F12R1_FB5_Pos (5U)
+#define CAN_F12R1_FB5_Msk (0x1U << CAN_F12R1_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F12R1_FB5 CAN_F12R1_FB5_Msk /*!< Filter bit 5 */
+#define CAN_F12R1_FB6_Pos (6U)
+#define CAN_F12R1_FB6_Msk (0x1U << CAN_F12R1_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F12R1_FB6 CAN_F12R1_FB6_Msk /*!< Filter bit 6 */
+#define CAN_F12R1_FB7_Pos (7U)
+#define CAN_F12R1_FB7_Msk (0x1U << CAN_F12R1_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F12R1_FB7 CAN_F12R1_FB7_Msk /*!< Filter bit 7 */
+#define CAN_F12R1_FB8_Pos (8U)
+#define CAN_F12R1_FB8_Msk (0x1U << CAN_F12R1_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F12R1_FB8 CAN_F12R1_FB8_Msk /*!< Filter bit 8 */
+#define CAN_F12R1_FB9_Pos (9U)
+#define CAN_F12R1_FB9_Msk (0x1U << CAN_F12R1_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F12R1_FB9 CAN_F12R1_FB9_Msk /*!< Filter bit 9 */
+#define CAN_F12R1_FB10_Pos (10U)
+#define CAN_F12R1_FB10_Msk (0x1U << CAN_F12R1_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F12R1_FB10 CAN_F12R1_FB10_Msk /*!< Filter bit 10 */
+#define CAN_F12R1_FB11_Pos (11U)
+#define CAN_F12R1_FB11_Msk (0x1U << CAN_F12R1_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F12R1_FB11 CAN_F12R1_FB11_Msk /*!< Filter bit 11 */
+#define CAN_F12R1_FB12_Pos (12U)
+#define CAN_F12R1_FB12_Msk (0x1U << CAN_F12R1_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F12R1_FB12 CAN_F12R1_FB12_Msk /*!< Filter bit 12 */
+#define CAN_F12R1_FB13_Pos (13U)
+#define CAN_F12R1_FB13_Msk (0x1U << CAN_F12R1_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F12R1_FB13 CAN_F12R1_FB13_Msk /*!< Filter bit 13 */
+#define CAN_F12R1_FB14_Pos (14U)
+#define CAN_F12R1_FB14_Msk (0x1U << CAN_F12R1_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F12R1_FB14 CAN_F12R1_FB14_Msk /*!< Filter bit 14 */
+#define CAN_F12R1_FB15_Pos (15U)
+#define CAN_F12R1_FB15_Msk (0x1U << CAN_F12R1_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F12R1_FB15 CAN_F12R1_FB15_Msk /*!< Filter bit 15 */
+#define CAN_F12R1_FB16_Pos (16U)
+#define CAN_F12R1_FB16_Msk (0x1U << CAN_F12R1_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F12R1_FB16 CAN_F12R1_FB16_Msk /*!< Filter bit 16 */
+#define CAN_F12R1_FB17_Pos (17U)
+#define CAN_F12R1_FB17_Msk (0x1U << CAN_F12R1_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F12R1_FB17 CAN_F12R1_FB17_Msk /*!< Filter bit 17 */
+#define CAN_F12R1_FB18_Pos (18U)
+#define CAN_F12R1_FB18_Msk (0x1U << CAN_F12R1_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F12R1_FB18 CAN_F12R1_FB18_Msk /*!< Filter bit 18 */
+#define CAN_F12R1_FB19_Pos (19U)
+#define CAN_F12R1_FB19_Msk (0x1U << CAN_F12R1_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F12R1_FB19 CAN_F12R1_FB19_Msk /*!< Filter bit 19 */
+#define CAN_F12R1_FB20_Pos (20U)
+#define CAN_F12R1_FB20_Msk (0x1U << CAN_F12R1_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F12R1_FB20 CAN_F12R1_FB20_Msk /*!< Filter bit 20 */
+#define CAN_F12R1_FB21_Pos (21U)
+#define CAN_F12R1_FB21_Msk (0x1U << CAN_F12R1_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F12R1_FB21 CAN_F12R1_FB21_Msk /*!< Filter bit 21 */
+#define CAN_F12R1_FB22_Pos (22U)
+#define CAN_F12R1_FB22_Msk (0x1U << CAN_F12R1_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F12R1_FB22 CAN_F12R1_FB22_Msk /*!< Filter bit 22 */
+#define CAN_F12R1_FB23_Pos (23U)
+#define CAN_F12R1_FB23_Msk (0x1U << CAN_F12R1_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F12R1_FB23 CAN_F12R1_FB23_Msk /*!< Filter bit 23 */
+#define CAN_F12R1_FB24_Pos (24U)
+#define CAN_F12R1_FB24_Msk (0x1U << CAN_F12R1_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F12R1_FB24 CAN_F12R1_FB24_Msk /*!< Filter bit 24 */
+#define CAN_F12R1_FB25_Pos (25U)
+#define CAN_F12R1_FB25_Msk (0x1U << CAN_F12R1_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F12R1_FB25 CAN_F12R1_FB25_Msk /*!< Filter bit 25 */
+#define CAN_F12R1_FB26_Pos (26U)
+#define CAN_F12R1_FB26_Msk (0x1U << CAN_F12R1_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F12R1_FB26 CAN_F12R1_FB26_Msk /*!< Filter bit 26 */
+#define CAN_F12R1_FB27_Pos (27U)
+#define CAN_F12R1_FB27_Msk (0x1U << CAN_F12R1_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F12R1_FB27 CAN_F12R1_FB27_Msk /*!< Filter bit 27 */
+#define CAN_F12R1_FB28_Pos (28U)
+#define CAN_F12R1_FB28_Msk (0x1U << CAN_F12R1_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F12R1_FB28 CAN_F12R1_FB28_Msk /*!< Filter bit 28 */
+#define CAN_F12R1_FB29_Pos (29U)
+#define CAN_F12R1_FB29_Msk (0x1U << CAN_F12R1_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F12R1_FB29 CAN_F12R1_FB29_Msk /*!< Filter bit 29 */
+#define CAN_F12R1_FB30_Pos (30U)
+#define CAN_F12R1_FB30_Msk (0x1U << CAN_F12R1_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F12R1_FB30 CAN_F12R1_FB30_Msk /*!< Filter bit 30 */
+#define CAN_F12R1_FB31_Pos (31U)
+#define CAN_F12R1_FB31_Msk (0x1U << CAN_F12R1_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F12R1_FB31 CAN_F12R1_FB31_Msk /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F13R1 register ******************/
+#define CAN_F13R1_FB0_Pos (0U)
+#define CAN_F13R1_FB0_Msk (0x1U << CAN_F13R1_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F13R1_FB0 CAN_F13R1_FB0_Msk /*!< Filter bit 0 */
+#define CAN_F13R1_FB1_Pos (1U)
+#define CAN_F13R1_FB1_Msk (0x1U << CAN_F13R1_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F13R1_FB1 CAN_F13R1_FB1_Msk /*!< Filter bit 1 */
+#define CAN_F13R1_FB2_Pos (2U)
+#define CAN_F13R1_FB2_Msk (0x1U << CAN_F13R1_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F13R1_FB2 CAN_F13R1_FB2_Msk /*!< Filter bit 2 */
+#define CAN_F13R1_FB3_Pos (3U)
+#define CAN_F13R1_FB3_Msk (0x1U << CAN_F13R1_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F13R1_FB3 CAN_F13R1_FB3_Msk /*!< Filter bit 3 */
+#define CAN_F13R1_FB4_Pos (4U)
+#define CAN_F13R1_FB4_Msk (0x1U << CAN_F13R1_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F13R1_FB4 CAN_F13R1_FB4_Msk /*!< Filter bit 4 */
+#define CAN_F13R1_FB5_Pos (5U)
+#define CAN_F13R1_FB5_Msk (0x1U << CAN_F13R1_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F13R1_FB5 CAN_F13R1_FB5_Msk /*!< Filter bit 5 */
+#define CAN_F13R1_FB6_Pos (6U)
+#define CAN_F13R1_FB6_Msk (0x1U << CAN_F13R1_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F13R1_FB6 CAN_F13R1_FB6_Msk /*!< Filter bit 6 */
+#define CAN_F13R1_FB7_Pos (7U)
+#define CAN_F13R1_FB7_Msk (0x1U << CAN_F13R1_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F13R1_FB7 CAN_F13R1_FB7_Msk /*!< Filter bit 7 */
+#define CAN_F13R1_FB8_Pos (8U)
+#define CAN_F13R1_FB8_Msk (0x1U << CAN_F13R1_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F13R1_FB8 CAN_F13R1_FB8_Msk /*!< Filter bit 8 */
+#define CAN_F13R1_FB9_Pos (9U)
+#define CAN_F13R1_FB9_Msk (0x1U << CAN_F13R1_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F13R1_FB9 CAN_F13R1_FB9_Msk /*!< Filter bit 9 */
+#define CAN_F13R1_FB10_Pos (10U)
+#define CAN_F13R1_FB10_Msk (0x1U << CAN_F13R1_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F13R1_FB10 CAN_F13R1_FB10_Msk /*!< Filter bit 10 */
+#define CAN_F13R1_FB11_Pos (11U)
+#define CAN_F13R1_FB11_Msk (0x1U << CAN_F13R1_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F13R1_FB11 CAN_F13R1_FB11_Msk /*!< Filter bit 11 */
+#define CAN_F13R1_FB12_Pos (12U)
+#define CAN_F13R1_FB12_Msk (0x1U << CAN_F13R1_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F13R1_FB12 CAN_F13R1_FB12_Msk /*!< Filter bit 12 */
+#define CAN_F13R1_FB13_Pos (13U)
+#define CAN_F13R1_FB13_Msk (0x1U << CAN_F13R1_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F13R1_FB13 CAN_F13R1_FB13_Msk /*!< Filter bit 13 */
+#define CAN_F13R1_FB14_Pos (14U)
+#define CAN_F13R1_FB14_Msk (0x1U << CAN_F13R1_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F13R1_FB14 CAN_F13R1_FB14_Msk /*!< Filter bit 14 */
+#define CAN_F13R1_FB15_Pos (15U)
+#define CAN_F13R1_FB15_Msk (0x1U << CAN_F13R1_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F13R1_FB15 CAN_F13R1_FB15_Msk /*!< Filter bit 15 */
+#define CAN_F13R1_FB16_Pos (16U)
+#define CAN_F13R1_FB16_Msk (0x1U << CAN_F13R1_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F13R1_FB16 CAN_F13R1_FB16_Msk /*!< Filter bit 16 */
+#define CAN_F13R1_FB17_Pos (17U)
+#define CAN_F13R1_FB17_Msk (0x1U << CAN_F13R1_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F13R1_FB17 CAN_F13R1_FB17_Msk /*!< Filter bit 17 */
+#define CAN_F13R1_FB18_Pos (18U)
+#define CAN_F13R1_FB18_Msk (0x1U << CAN_F13R1_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F13R1_FB18 CAN_F13R1_FB18_Msk /*!< Filter bit 18 */
+#define CAN_F13R1_FB19_Pos (19U)
+#define CAN_F13R1_FB19_Msk (0x1U << CAN_F13R1_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F13R1_FB19 CAN_F13R1_FB19_Msk /*!< Filter bit 19 */
+#define CAN_F13R1_FB20_Pos (20U)
+#define CAN_F13R1_FB20_Msk (0x1U << CAN_F13R1_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F13R1_FB20 CAN_F13R1_FB20_Msk /*!< Filter bit 20 */
+#define CAN_F13R1_FB21_Pos (21U)
+#define CAN_F13R1_FB21_Msk (0x1U << CAN_F13R1_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F13R1_FB21 CAN_F13R1_FB21_Msk /*!< Filter bit 21 */
+#define CAN_F13R1_FB22_Pos (22U)
+#define CAN_F13R1_FB22_Msk (0x1U << CAN_F13R1_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F13R1_FB22 CAN_F13R1_FB22_Msk /*!< Filter bit 22 */
+#define CAN_F13R1_FB23_Pos (23U)
+#define CAN_F13R1_FB23_Msk (0x1U << CAN_F13R1_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F13R1_FB23 CAN_F13R1_FB23_Msk /*!< Filter bit 23 */
+#define CAN_F13R1_FB24_Pos (24U)
+#define CAN_F13R1_FB24_Msk (0x1U << CAN_F13R1_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F13R1_FB24 CAN_F13R1_FB24_Msk /*!< Filter bit 24 */
+#define CAN_F13R1_FB25_Pos (25U)
+#define CAN_F13R1_FB25_Msk (0x1U << CAN_F13R1_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F13R1_FB25 CAN_F13R1_FB25_Msk /*!< Filter bit 25 */
+#define CAN_F13R1_FB26_Pos (26U)
+#define CAN_F13R1_FB26_Msk (0x1U << CAN_F13R1_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F13R1_FB26 CAN_F13R1_FB26_Msk /*!< Filter bit 26 */
+#define CAN_F13R1_FB27_Pos (27U)
+#define CAN_F13R1_FB27_Msk (0x1U << CAN_F13R1_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F13R1_FB27 CAN_F13R1_FB27_Msk /*!< Filter bit 27 */
+#define CAN_F13R1_FB28_Pos (28U)
+#define CAN_F13R1_FB28_Msk (0x1U << CAN_F13R1_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F13R1_FB28 CAN_F13R1_FB28_Msk /*!< Filter bit 28 */
+#define CAN_F13R1_FB29_Pos (29U)
+#define CAN_F13R1_FB29_Msk (0x1U << CAN_F13R1_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F13R1_FB29 CAN_F13R1_FB29_Msk /*!< Filter bit 29 */
+#define CAN_F13R1_FB30_Pos (30U)
+#define CAN_F13R1_FB30_Msk (0x1U << CAN_F13R1_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F13R1_FB30 CAN_F13R1_FB30_Msk /*!< Filter bit 30 */
+#define CAN_F13R1_FB31_Pos (31U)
+#define CAN_F13R1_FB31_Msk (0x1U << CAN_F13R1_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F13R1_FB31 CAN_F13R1_FB31_Msk /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F14R1 register ******************/
+#define CAN_F14R1_FB0_Pos (0U)
+#define CAN_F14R1_FB0_Msk (0x1U << CAN_F14R1_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F14R1_FB0 CAN_F14R1_FB0_Msk /*!< Filter bit 0 */
+#define CAN_F14R1_FB1_Pos (1U)
+#define CAN_F14R1_FB1_Msk (0x1U << CAN_F14R1_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F14R1_FB1 CAN_F14R1_FB1_Msk /*!< Filter bit 1 */
+#define CAN_F14R1_FB2_Pos (2U)
+#define CAN_F14R1_FB2_Msk (0x1U << CAN_F14R1_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F14R1_FB2 CAN_F14R1_FB2_Msk /*!< Filter bit 2 */
+#define CAN_F14R1_FB3_Pos (3U)
+#define CAN_F14R1_FB3_Msk (0x1U << CAN_F14R1_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F14R1_FB3 CAN_F14R1_FB3_Msk /*!< Filter bit 3 */
+#define CAN_F14R1_FB4_Pos (4U)
+#define CAN_F14R1_FB4_Msk (0x1U << CAN_F14R1_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F14R1_FB4 CAN_F14R1_FB4_Msk /*!< Filter bit 4 */
+#define CAN_F14R1_FB5_Pos (5U)
+#define CAN_F14R1_FB5_Msk (0x1U << CAN_F14R1_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F14R1_FB5 CAN_F14R1_FB5_Msk /*!< Filter bit 5 */
+#define CAN_F14R1_FB6_Pos (6U)
+#define CAN_F14R1_FB6_Msk (0x1U << CAN_F14R1_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F14R1_FB6 CAN_F14R1_FB6_Msk /*!< Filter bit 6 */
+#define CAN_F14R1_FB7_Pos (7U)
+#define CAN_F14R1_FB7_Msk (0x1U << CAN_F14R1_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F14R1_FB7 CAN_F14R1_FB7_Msk /*!< Filter bit 7 */
+#define CAN_F14R1_FB8_Pos (8U)
+#define CAN_F14R1_FB8_Msk (0x1U << CAN_F14R1_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F14R1_FB8 CAN_F14R1_FB8_Msk /*!< Filter bit 8 */
+#define CAN_F14R1_FB9_Pos (9U)
+#define CAN_F14R1_FB9_Msk (0x1U << CAN_F14R1_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F14R1_FB9 CAN_F14R1_FB9_Msk /*!< Filter bit 9 */
+#define CAN_F14R1_FB10_Pos (10U)
+#define CAN_F14R1_FB10_Msk (0x1U << CAN_F14R1_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F14R1_FB10 CAN_F14R1_FB10_Msk /*!< Filter bit 10 */
+#define CAN_F14R1_FB11_Pos (11U)
+#define CAN_F14R1_FB11_Msk (0x1U << CAN_F14R1_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F14R1_FB11 CAN_F14R1_FB11_Msk /*!< Filter bit 11 */
+#define CAN_F14R1_FB12_Pos (12U)
+#define CAN_F14R1_FB12_Msk (0x1U << CAN_F14R1_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F14R1_FB12 CAN_F14R1_FB12_Msk /*!< Filter bit 12 */
+#define CAN_F14R1_FB13_Pos (13U)
+#define CAN_F14R1_FB13_Msk (0x1U << CAN_F14R1_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F14R1_FB13 CAN_F14R1_FB13_Msk /*!< Filter bit 13 */
+#define CAN_F14R1_FB14_Pos (14U)
+#define CAN_F14R1_FB14_Msk (0x1U << CAN_F14R1_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F14R1_FB14 CAN_F14R1_FB14_Msk /*!< Filter bit 14 */
+#define CAN_F14R1_FB15_Pos (15U)
+#define CAN_F14R1_FB15_Msk (0x1U << CAN_F14R1_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F14R1_FB15 CAN_F14R1_FB15_Msk /*!< Filter bit 15 */
+#define CAN_F14R1_FB16_Pos (16U)
+#define CAN_F14R1_FB16_Msk (0x1U << CAN_F14R1_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F14R1_FB16 CAN_F14R1_FB16_Msk /*!< Filter bit 16 */
+#define CAN_F14R1_FB17_Pos (17U)
+#define CAN_F14R1_FB17_Msk (0x1U << CAN_F14R1_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F14R1_FB17 CAN_F14R1_FB17_Msk /*!< Filter bit 17 */
+#define CAN_F14R1_FB18_Pos (18U)
+#define CAN_F14R1_FB18_Msk (0x1U << CAN_F14R1_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F14R1_FB18 CAN_F14R1_FB18_Msk /*!< Filter bit 18 */
+#define CAN_F14R1_FB19_Pos (19U)
+#define CAN_F14R1_FB19_Msk (0x1U << CAN_F14R1_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F14R1_FB19 CAN_F14R1_FB19_Msk /*!< Filter bit 19 */
+#define CAN_F14R1_FB20_Pos (20U)
+#define CAN_F14R1_FB20_Msk (0x1U << CAN_F14R1_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F14R1_FB20 CAN_F14R1_FB20_Msk /*!< Filter bit 20 */
+#define CAN_F14R1_FB21_Pos (21U)
+#define CAN_F14R1_FB21_Msk (0x1U << CAN_F14R1_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F14R1_FB21 CAN_F14R1_FB21_Msk /*!< Filter bit 21 */
+#define CAN_F14R1_FB22_Pos (22U)
+#define CAN_F14R1_FB22_Msk (0x1U << CAN_F14R1_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F14R1_FB22 CAN_F14R1_FB22_Msk /*!< Filter bit 22 */
+#define CAN_F14R1_FB23_Pos (23U)
+#define CAN_F14R1_FB23_Msk (0x1U << CAN_F14R1_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F14R1_FB23 CAN_F14R1_FB23_Msk /*!< Filter bit 23 */
+#define CAN_F14R1_FB24_Pos (24U)
+#define CAN_F14R1_FB24_Msk (0x1U << CAN_F14R1_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F14R1_FB24 CAN_F14R1_FB24_Msk /*!< Filter bit 24 */
+#define CAN_F14R1_FB25_Pos (25U)
+#define CAN_F14R1_FB25_Msk (0x1U << CAN_F14R1_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F14R1_FB25 CAN_F14R1_FB25_Msk /*!< Filter bit 25 */
+#define CAN_F14R1_FB26_Pos (26U)
+#define CAN_F14R1_FB26_Msk (0x1U << CAN_F14R1_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F14R1_FB26 CAN_F14R1_FB26_Msk /*!< Filter bit 26 */
+#define CAN_F14R1_FB27_Pos (27U)
+#define CAN_F14R1_FB27_Msk (0x1U << CAN_F14R1_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F14R1_FB27 CAN_F14R1_FB27_Msk /*!< Filter bit 27 */
+#define CAN_F14R1_FB28_Pos (28U)
+#define CAN_F14R1_FB28_Msk (0x1U << CAN_F14R1_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F14R1_FB28 CAN_F14R1_FB28_Msk /*!< Filter bit 28 */
+#define CAN_F14R1_FB29_Pos (29U)
+#define CAN_F14R1_FB29_Msk (0x1U << CAN_F14R1_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F14R1_FB29 CAN_F14R1_FB29_Msk /*!< Filter bit 29 */
+#define CAN_F14R1_FB30_Pos (30U)
+#define CAN_F14R1_FB30_Msk (0x1U << CAN_F14R1_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F14R1_FB30 CAN_F14R1_FB30_Msk /*!< Filter bit 30 */
+#define CAN_F14R1_FB31_Pos (31U)
+#define CAN_F14R1_FB31_Msk (0x1U << CAN_F14R1_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F14R1_FB31 CAN_F14R1_FB31_Msk /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F15R1 register ******************/
+#define CAN_F15R1_FB0_Pos (0U)
+#define CAN_F15R1_FB0_Msk (0x1U << CAN_F15R1_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F15R1_FB0 CAN_F15R1_FB0_Msk /*!< Filter bit 0 */
+#define CAN_F15R1_FB1_Pos (1U)
+#define CAN_F15R1_FB1_Msk (0x1U << CAN_F15R1_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F15R1_FB1 CAN_F15R1_FB1_Msk /*!< Filter bit 1 */
+#define CAN_F15R1_FB2_Pos (2U)
+#define CAN_F15R1_FB2_Msk (0x1U << CAN_F15R1_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F15R1_FB2 CAN_F15R1_FB2_Msk /*!< Filter bit 2 */
+#define CAN_F15R1_FB3_Pos (3U)
+#define CAN_F15R1_FB3_Msk (0x1U << CAN_F15R1_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F15R1_FB3 CAN_F15R1_FB3_Msk /*!< Filter bit 3 */
+#define CAN_F15R1_FB4_Pos (4U)
+#define CAN_F15R1_FB4_Msk (0x1U << CAN_F15R1_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F15R1_FB4 CAN_F15R1_FB4_Msk /*!< Filter bit 4 */
+#define CAN_F15R1_FB5_Pos (5U)
+#define CAN_F15R1_FB5_Msk (0x1U << CAN_F15R1_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F15R1_FB5 CAN_F15R1_FB5_Msk /*!< Filter bit 5 */
+#define CAN_F15R1_FB6_Pos (6U)
+#define CAN_F15R1_FB6_Msk (0x1U << CAN_F15R1_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F15R1_FB6 CAN_F15R1_FB6_Msk /*!< Filter bit 6 */
+#define CAN_F15R1_FB7_Pos (7U)
+#define CAN_F15R1_FB7_Msk (0x1U << CAN_F15R1_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F15R1_FB7 CAN_F15R1_FB7_Msk /*!< Filter bit 7 */
+#define CAN_F15R1_FB8_Pos (8U)
+#define CAN_F15R1_FB8_Msk (0x1U << CAN_F15R1_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F15R1_FB8 CAN_F15R1_FB8_Msk /*!< Filter bit 8 */
+#define CAN_F15R1_FB9_Pos (9U)
+#define CAN_F15R1_FB9_Msk (0x1U << CAN_F15R1_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F15R1_FB9 CAN_F15R1_FB9_Msk /*!< Filter bit 9 */
+#define CAN_F15R1_FB10_Pos (10U)
+#define CAN_F15R1_FB10_Msk (0x1U << CAN_F15R1_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F15R1_FB10 CAN_F15R1_FB10_Msk /*!< Filter bit 10 */
+#define CAN_F15R1_FB11_Pos (11U)
+#define CAN_F15R1_FB11_Msk (0x1U << CAN_F15R1_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F15R1_FB11 CAN_F15R1_FB11_Msk /*!< Filter bit 11 */
+#define CAN_F15R1_FB12_Pos (12U)
+#define CAN_F15R1_FB12_Msk (0x1U << CAN_F15R1_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F15R1_FB12 CAN_F15R1_FB12_Msk /*!< Filter bit 12 */
+#define CAN_F15R1_FB13_Pos (13U)
+#define CAN_F15R1_FB13_Msk (0x1U << CAN_F15R1_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F15R1_FB13 CAN_F15R1_FB13_Msk /*!< Filter bit 13 */
+#define CAN_F15R1_FB14_Pos (14U)
+#define CAN_F15R1_FB14_Msk (0x1U << CAN_F15R1_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F15R1_FB14 CAN_F15R1_FB14_Msk /*!< Filter bit 14 */
+#define CAN_F15R1_FB15_Pos (15U)
+#define CAN_F15R1_FB15_Msk (0x1U << CAN_F15R1_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F15R1_FB15 CAN_F15R1_FB15_Msk /*!< Filter bit 15 */
+#define CAN_F15R1_FB16_Pos (16U)
+#define CAN_F15R1_FB16_Msk (0x1U << CAN_F15R1_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F15R1_FB16 CAN_F15R1_FB16_Msk /*!< Filter bit 16 */
+#define CAN_F15R1_FB17_Pos (17U)
+#define CAN_F15R1_FB17_Msk (0x1U << CAN_F15R1_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F15R1_FB17 CAN_F15R1_FB17_Msk /*!< Filter bit 17 */
+#define CAN_F15R1_FB18_Pos (18U)
+#define CAN_F15R1_FB18_Msk (0x1U << CAN_F15R1_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F15R1_FB18 CAN_F15R1_FB18_Msk /*!< Filter bit 18 */
+#define CAN_F15R1_FB19_Pos (19U)
+#define CAN_F15R1_FB19_Msk (0x1U << CAN_F15R1_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F15R1_FB19 CAN_F15R1_FB19_Msk /*!< Filter bit 19 */
+#define CAN_F15R1_FB20_Pos (20U)
+#define CAN_F15R1_FB20_Msk (0x1U << CAN_F15R1_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F15R1_FB20 CAN_F15R1_FB20_Msk /*!< Filter bit 20 */
+#define CAN_F15R1_FB21_Pos (21U)
+#define CAN_F15R1_FB21_Msk (0x1U << CAN_F15R1_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F15R1_FB21 CAN_F15R1_FB21_Msk /*!< Filter bit 21 */
+#define CAN_F15R1_FB22_Pos (22U)
+#define CAN_F15R1_FB22_Msk (0x1U << CAN_F15R1_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F15R1_FB22 CAN_F15R1_FB22_Msk /*!< Filter bit 22 */
+#define CAN_F15R1_FB23_Pos (23U)
+#define CAN_F15R1_FB23_Msk (0x1U << CAN_F15R1_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F15R1_FB23 CAN_F15R1_FB23_Msk /*!< Filter bit 23 */
+#define CAN_F15R1_FB24_Pos (24U)
+#define CAN_F15R1_FB24_Msk (0x1U << CAN_F15R1_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F15R1_FB24 CAN_F15R1_FB24_Msk /*!< Filter bit 24 */
+#define CAN_F15R1_FB25_Pos (25U)
+#define CAN_F15R1_FB25_Msk (0x1U << CAN_F15R1_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F15R1_FB25 CAN_F15R1_FB25_Msk /*!< Filter bit 25 */
+#define CAN_F15R1_FB26_Pos (26U)
+#define CAN_F15R1_FB26_Msk (0x1U << CAN_F15R1_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F15R1_FB26 CAN_F15R1_FB26_Msk /*!< Filter bit 26 */
+#define CAN_F15R1_FB27_Pos (27U)
+#define CAN_F15R1_FB27_Msk (0x1U << CAN_F15R1_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F15R1_FB27 CAN_F15R1_FB27_Msk /*!< Filter bit 27 */
+#define CAN_F15R1_FB28_Pos (28U)
+#define CAN_F15R1_FB28_Msk (0x1U << CAN_F15R1_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F15R1_FB28 CAN_F15R1_FB28_Msk /*!< Filter bit 28 */
+#define CAN_F15R1_FB29_Pos (29U)
+#define CAN_F15R1_FB29_Msk (0x1U << CAN_F15R1_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F15R1_FB29 CAN_F15R1_FB29_Msk /*!< Filter bit 29 */
+#define CAN_F15R1_FB30_Pos (30U)
+#define CAN_F15R1_FB30_Msk (0x1U << CAN_F15R1_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F15R1_FB30 CAN_F15R1_FB30_Msk /*!< Filter bit 30 */
+#define CAN_F15R1_FB31_Pos (31U)
+#define CAN_F15R1_FB31_Msk (0x1U << CAN_F15R1_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F15R1_FB31 CAN_F15R1_FB31_Msk /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F16R1 register ******************/
+#define CAN_F16R1_FB0_Pos (0U)
+#define CAN_F16R1_FB0_Msk (0x1U << CAN_F16R1_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F16R1_FB0 CAN_F16R1_FB0_Msk /*!< Filter bit 0 */
+#define CAN_F16R1_FB1_Pos (1U)
+#define CAN_F16R1_FB1_Msk (0x1U << CAN_F16R1_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F16R1_FB1 CAN_F16R1_FB1_Msk /*!< Filter bit 1 */
+#define CAN_F16R1_FB2_Pos (2U)
+#define CAN_F16R1_FB2_Msk (0x1U << CAN_F16R1_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F16R1_FB2 CAN_F16R1_FB2_Msk /*!< Filter bit 2 */
+#define CAN_F16R1_FB3_Pos (3U)
+#define CAN_F16R1_FB3_Msk (0x1U << CAN_F16R1_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F16R1_FB3 CAN_F16R1_FB3_Msk /*!< Filter bit 3 */
+#define CAN_F16R1_FB4_Pos (4U)
+#define CAN_F16R1_FB4_Msk (0x1U << CAN_F16R1_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F16R1_FB4 CAN_F16R1_FB4_Msk /*!< Filter bit 4 */
+#define CAN_F16R1_FB5_Pos (5U)
+#define CAN_F16R1_FB5_Msk (0x1U << CAN_F16R1_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F16R1_FB5 CAN_F16R1_FB5_Msk /*!< Filter bit 5 */
+#define CAN_F16R1_FB6_Pos (6U)
+#define CAN_F16R1_FB6_Msk (0x1U << CAN_F16R1_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F16R1_FB6 CAN_F16R1_FB6_Msk /*!< Filter bit 6 */
+#define CAN_F16R1_FB7_Pos (7U)
+#define CAN_F16R1_FB7_Msk (0x1U << CAN_F16R1_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F16R1_FB7 CAN_F16R1_FB7_Msk /*!< Filter bit 7 */
+#define CAN_F16R1_FB8_Pos (8U)
+#define CAN_F16R1_FB8_Msk (0x1U << CAN_F16R1_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F16R1_FB8 CAN_F16R1_FB8_Msk /*!< Filter bit 8 */
+#define CAN_F16R1_FB9_Pos (9U)
+#define CAN_F16R1_FB9_Msk (0x1U << CAN_F16R1_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F16R1_FB9 CAN_F16R1_FB9_Msk /*!< Filter bit 9 */
+#define CAN_F16R1_FB10_Pos (10U)
+#define CAN_F16R1_FB10_Msk (0x1U << CAN_F16R1_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F16R1_FB10 CAN_F16R1_FB10_Msk /*!< Filter bit 10 */
+#define CAN_F16R1_FB11_Pos (11U)
+#define CAN_F16R1_FB11_Msk (0x1U << CAN_F16R1_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F16R1_FB11 CAN_F16R1_FB11_Msk /*!< Filter bit 11 */
+#define CAN_F16R1_FB12_Pos (12U)
+#define CAN_F16R1_FB12_Msk (0x1U << CAN_F16R1_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F16R1_FB12 CAN_F16R1_FB12_Msk /*!< Filter bit 12 */
+#define CAN_F16R1_FB13_Pos (13U)
+#define CAN_F16R1_FB13_Msk (0x1U << CAN_F16R1_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F16R1_FB13 CAN_F16R1_FB13_Msk /*!< Filter bit 13 */
+#define CAN_F16R1_FB14_Pos (14U)
+#define CAN_F16R1_FB14_Msk (0x1U << CAN_F16R1_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F16R1_FB14 CAN_F16R1_FB14_Msk /*!< Filter bit 14 */
+#define CAN_F16R1_FB15_Pos (15U)
+#define CAN_F16R1_FB15_Msk (0x1U << CAN_F16R1_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F16R1_FB15 CAN_F16R1_FB15_Msk /*!< Filter bit 15 */
+#define CAN_F16R1_FB16_Pos (16U)
+#define CAN_F16R1_FB16_Msk (0x1U << CAN_F16R1_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F16R1_FB16 CAN_F16R1_FB16_Msk /*!< Filter bit 16 */
+#define CAN_F16R1_FB17_Pos (17U)
+#define CAN_F16R1_FB17_Msk (0x1U << CAN_F16R1_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F16R1_FB17 CAN_F16R1_FB17_Msk /*!< Filter bit 17 */
+#define CAN_F16R1_FB18_Pos (18U)
+#define CAN_F16R1_FB18_Msk (0x1U << CAN_F16R1_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F16R1_FB18 CAN_F16R1_FB18_Msk /*!< Filter bit 18 */
+#define CAN_F16R1_FB19_Pos (19U)
+#define CAN_F16R1_FB19_Msk (0x1U << CAN_F16R1_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F16R1_FB19 CAN_F16R1_FB19_Msk /*!< Filter bit 19 */
+#define CAN_F16R1_FB20_Pos (20U)
+#define CAN_F16R1_FB20_Msk (0x1U << CAN_F16R1_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F16R1_FB20 CAN_F16R1_FB20_Msk /*!< Filter bit 20 */
+#define CAN_F16R1_FB21_Pos (21U)
+#define CAN_F16R1_FB21_Msk (0x1U << CAN_F16R1_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F16R1_FB21 CAN_F16R1_FB21_Msk /*!< Filter bit 21 */
+#define CAN_F16R1_FB22_Pos (22U)
+#define CAN_F16R1_FB22_Msk (0x1U << CAN_F16R1_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F16R1_FB22 CAN_F16R1_FB22_Msk /*!< Filter bit 22 */
+#define CAN_F16R1_FB23_Pos (23U)
+#define CAN_F16R1_FB23_Msk (0x1U << CAN_F16R1_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F16R1_FB23 CAN_F16R1_FB23_Msk /*!< Filter bit 23 */
+#define CAN_F16R1_FB24_Pos (24U)
+#define CAN_F16R1_FB24_Msk (0x1U << CAN_F16R1_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F16R1_FB24 CAN_F16R1_FB24_Msk /*!< Filter bit 24 */
+#define CAN_F16R1_FB25_Pos (25U)
+#define CAN_F16R1_FB25_Msk (0x1U << CAN_F16R1_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F16R1_FB25 CAN_F16R1_FB25_Msk /*!< Filter bit 25 */
+#define CAN_F16R1_FB26_Pos (26U)
+#define CAN_F16R1_FB26_Msk (0x1U << CAN_F16R1_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F16R1_FB26 CAN_F16R1_FB26_Msk /*!< Filter bit 26 */
+#define CAN_F16R1_FB27_Pos (27U)
+#define CAN_F16R1_FB27_Msk (0x1U << CAN_F16R1_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F16R1_FB27 CAN_F16R1_FB27_Msk /*!< Filter bit 27 */
+#define CAN_F16R1_FB28_Pos (28U)
+#define CAN_F16R1_FB28_Msk (0x1U << CAN_F16R1_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F16R1_FB28 CAN_F16R1_FB28_Msk /*!< Filter bit 28 */
+#define CAN_F16R1_FB29_Pos (29U)
+#define CAN_F16R1_FB29_Msk (0x1U << CAN_F16R1_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F16R1_FB29 CAN_F16R1_FB29_Msk /*!< Filter bit 29 */
+#define CAN_F16R1_FB30_Pos (30U)
+#define CAN_F16R1_FB30_Msk (0x1U << CAN_F16R1_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F16R1_FB30 CAN_F16R1_FB30_Msk /*!< Filter bit 30 */
+#define CAN_F16R1_FB31_Pos (31U)
+#define CAN_F16R1_FB31_Msk (0x1U << CAN_F16R1_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F16R1_FB31 CAN_F16R1_FB31_Msk /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F17R1 register ******************/
+#define CAN_F17R1_FB0_Pos (0U)
+#define CAN_F17R1_FB0_Msk (0x1U << CAN_F17R1_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F17R1_FB0 CAN_F17R1_FB0_Msk /*!< Filter bit 0 */
+#define CAN_F17R1_FB1_Pos (1U)
+#define CAN_F17R1_FB1_Msk (0x1U << CAN_F17R1_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F17R1_FB1 CAN_F17R1_FB1_Msk /*!< Filter bit 1 */
+#define CAN_F17R1_FB2_Pos (2U)
+#define CAN_F17R1_FB2_Msk (0x1U << CAN_F17R1_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F17R1_FB2 CAN_F17R1_FB2_Msk /*!< Filter bit 2 */
+#define CAN_F17R1_FB3_Pos (3U)
+#define CAN_F17R1_FB3_Msk (0x1U << CAN_F17R1_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F17R1_FB3 CAN_F17R1_FB3_Msk /*!< Filter bit 3 */
+#define CAN_F17R1_FB4_Pos (4U)
+#define CAN_F17R1_FB4_Msk (0x1U << CAN_F17R1_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F17R1_FB4 CAN_F17R1_FB4_Msk /*!< Filter bit 4 */
+#define CAN_F17R1_FB5_Pos (5U)
+#define CAN_F17R1_FB5_Msk (0x1U << CAN_F17R1_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F17R1_FB5 CAN_F17R1_FB5_Msk /*!< Filter bit 5 */
+#define CAN_F17R1_FB6_Pos (6U)
+#define CAN_F17R1_FB6_Msk (0x1U << CAN_F17R1_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F17R1_FB6 CAN_F17R1_FB6_Msk /*!< Filter bit 6 */
+#define CAN_F17R1_FB7_Pos (7U)
+#define CAN_F17R1_FB7_Msk (0x1U << CAN_F17R1_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F17R1_FB7 CAN_F17R1_FB7_Msk /*!< Filter bit 7 */
+#define CAN_F17R1_FB8_Pos (8U)
+#define CAN_F17R1_FB8_Msk (0x1U << CAN_F17R1_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F17R1_FB8 CAN_F17R1_FB8_Msk /*!< Filter bit 8 */
+#define CAN_F17R1_FB9_Pos (9U)
+#define CAN_F17R1_FB9_Msk (0x1U << CAN_F17R1_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F17R1_FB9 CAN_F17R1_FB9_Msk /*!< Filter bit 9 */
+#define CAN_F17R1_FB10_Pos (10U)
+#define CAN_F17R1_FB10_Msk (0x1U << CAN_F17R1_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F17R1_FB10 CAN_F17R1_FB10_Msk /*!< Filter bit 10 */
+#define CAN_F17R1_FB11_Pos (11U)
+#define CAN_F17R1_FB11_Msk (0x1U << CAN_F17R1_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F17R1_FB11 CAN_F17R1_FB11_Msk /*!< Filter bit 11 */
+#define CAN_F17R1_FB12_Pos (12U)
+#define CAN_F17R1_FB12_Msk (0x1U << CAN_F17R1_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F17R1_FB12 CAN_F17R1_FB12_Msk /*!< Filter bit 12 */
+#define CAN_F17R1_FB13_Pos (13U)
+#define CAN_F17R1_FB13_Msk (0x1U << CAN_F17R1_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F17R1_FB13 CAN_F17R1_FB13_Msk /*!< Filter bit 13 */
+#define CAN_F17R1_FB14_Pos (14U)
+#define CAN_F17R1_FB14_Msk (0x1U << CAN_F17R1_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F17R1_FB14 CAN_F17R1_FB14_Msk /*!< Filter bit 14 */
+#define CAN_F17R1_FB15_Pos (15U)
+#define CAN_F17R1_FB15_Msk (0x1U << CAN_F17R1_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F17R1_FB15 CAN_F17R1_FB15_Msk /*!< Filter bit 15 */
+#define CAN_F17R1_FB16_Pos (16U)
+#define CAN_F17R1_FB16_Msk (0x1U << CAN_F17R1_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F17R1_FB16 CAN_F17R1_FB16_Msk /*!< Filter bit 16 */
+#define CAN_F17R1_FB17_Pos (17U)
+#define CAN_F17R1_FB17_Msk (0x1U << CAN_F17R1_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F17R1_FB17 CAN_F17R1_FB17_Msk /*!< Filter bit 17 */
+#define CAN_F17R1_FB18_Pos (18U)
+#define CAN_F17R1_FB18_Msk (0x1U << CAN_F17R1_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F17R1_FB18 CAN_F17R1_FB18_Msk /*!< Filter bit 18 */
+#define CAN_F17R1_FB19_Pos (19U)
+#define CAN_F17R1_FB19_Msk (0x1U << CAN_F17R1_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F17R1_FB19 CAN_F17R1_FB19_Msk /*!< Filter bit 19 */
+#define CAN_F17R1_FB20_Pos (20U)
+#define CAN_F17R1_FB20_Msk (0x1U << CAN_F17R1_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F17R1_FB20 CAN_F17R1_FB20_Msk /*!< Filter bit 20 */
+#define CAN_F17R1_FB21_Pos (21U)
+#define CAN_F17R1_FB21_Msk (0x1U << CAN_F17R1_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F17R1_FB21 CAN_F17R1_FB21_Msk /*!< Filter bit 21 */
+#define CAN_F17R1_FB22_Pos (22U)
+#define CAN_F17R1_FB22_Msk (0x1U << CAN_F17R1_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F17R1_FB22 CAN_F17R1_FB22_Msk /*!< Filter bit 22 */
+#define CAN_F17R1_FB23_Pos (23U)
+#define CAN_F17R1_FB23_Msk (0x1U << CAN_F17R1_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F17R1_FB23 CAN_F17R1_FB23_Msk /*!< Filter bit 23 */
+#define CAN_F17R1_FB24_Pos (24U)
+#define CAN_F17R1_FB24_Msk (0x1U << CAN_F17R1_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F17R1_FB24 CAN_F17R1_FB24_Msk /*!< Filter bit 24 */
+#define CAN_F17R1_FB25_Pos (25U)
+#define CAN_F17R1_FB25_Msk (0x1U << CAN_F17R1_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F17R1_FB25 CAN_F17R1_FB25_Msk /*!< Filter bit 25 */
+#define CAN_F17R1_FB26_Pos (26U)
+#define CAN_F17R1_FB26_Msk (0x1U << CAN_F17R1_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F17R1_FB26 CAN_F17R1_FB26_Msk /*!< Filter bit 26 */
+#define CAN_F17R1_FB27_Pos (27U)
+#define CAN_F17R1_FB27_Msk (0x1U << CAN_F17R1_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F17R1_FB27 CAN_F17R1_FB27_Msk /*!< Filter bit 27 */
+#define CAN_F17R1_FB28_Pos (28U)
+#define CAN_F17R1_FB28_Msk (0x1U << CAN_F17R1_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F17R1_FB28 CAN_F17R1_FB28_Msk /*!< Filter bit 28 */
+#define CAN_F17R1_FB29_Pos (29U)
+#define CAN_F17R1_FB29_Msk (0x1U << CAN_F17R1_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F17R1_FB29 CAN_F17R1_FB29_Msk /*!< Filter bit 29 */
+#define CAN_F17R1_FB30_Pos (30U)
+#define CAN_F17R1_FB30_Msk (0x1U << CAN_F17R1_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F17R1_FB30 CAN_F17R1_FB30_Msk /*!< Filter bit 30 */
+#define CAN_F17R1_FB31_Pos (31U)
+#define CAN_F17R1_FB31_Msk (0x1U << CAN_F17R1_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F17R1_FB31 CAN_F17R1_FB31_Msk /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F18R1 register ******************/
+#define CAN_F18R1_FB0_Pos (0U)
+#define CAN_F18R1_FB0_Msk (0x1U << CAN_F18R1_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F18R1_FB0 CAN_F18R1_FB0_Msk /*!< Filter bit 0 */
+#define CAN_F18R1_FB1_Pos (1U)
+#define CAN_F18R1_FB1_Msk (0x1U << CAN_F18R1_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F18R1_FB1 CAN_F18R1_FB1_Msk /*!< Filter bit 1 */
+#define CAN_F18R1_FB2_Pos (2U)
+#define CAN_F18R1_FB2_Msk (0x1U << CAN_F18R1_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F18R1_FB2 CAN_F18R1_FB2_Msk /*!< Filter bit 2 */
+#define CAN_F18R1_FB3_Pos (3U)
+#define CAN_F18R1_FB3_Msk (0x1U << CAN_F18R1_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F18R1_FB3 CAN_F18R1_FB3_Msk /*!< Filter bit 3 */
+#define CAN_F18R1_FB4_Pos (4U)
+#define CAN_F18R1_FB4_Msk (0x1U << CAN_F18R1_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F18R1_FB4 CAN_F18R1_FB4_Msk /*!< Filter bit 4 */
+#define CAN_F18R1_FB5_Pos (5U)
+#define CAN_F18R1_FB5_Msk (0x1U << CAN_F18R1_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F18R1_FB5 CAN_F18R1_FB5_Msk /*!< Filter bit 5 */
+#define CAN_F18R1_FB6_Pos (6U)
+#define CAN_F18R1_FB6_Msk (0x1U << CAN_F18R1_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F18R1_FB6 CAN_F18R1_FB6_Msk /*!< Filter bit 6 */
+#define CAN_F18R1_FB7_Pos (7U)
+#define CAN_F18R1_FB7_Msk (0x1U << CAN_F18R1_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F18R1_FB7 CAN_F18R1_FB7_Msk /*!< Filter bit 7 */
+#define CAN_F18R1_FB8_Pos (8U)
+#define CAN_F18R1_FB8_Msk (0x1U << CAN_F18R1_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F18R1_FB8 CAN_F18R1_FB8_Msk /*!< Filter bit 8 */
+#define CAN_F18R1_FB9_Pos (9U)
+#define CAN_F18R1_FB9_Msk (0x1U << CAN_F18R1_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F18R1_FB9 CAN_F18R1_FB9_Msk /*!< Filter bit 9 */
+#define CAN_F18R1_FB10_Pos (10U)
+#define CAN_F18R1_FB10_Msk (0x1U << CAN_F18R1_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F18R1_FB10 CAN_F18R1_FB10_Msk /*!< Filter bit 10 */
+#define CAN_F18R1_FB11_Pos (11U)
+#define CAN_F18R1_FB11_Msk (0x1U << CAN_F18R1_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F18R1_FB11 CAN_F18R1_FB11_Msk /*!< Filter bit 11 */
+#define CAN_F18R1_FB12_Pos (12U)
+#define CAN_F18R1_FB12_Msk (0x1U << CAN_F18R1_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F18R1_FB12 CAN_F18R1_FB12_Msk /*!< Filter bit 12 */
+#define CAN_F18R1_FB13_Pos (13U)
+#define CAN_F18R1_FB13_Msk (0x1U << CAN_F18R1_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F18R1_FB13 CAN_F18R1_FB13_Msk /*!< Filter bit 13 */
+#define CAN_F18R1_FB14_Pos (14U)
+#define CAN_F18R1_FB14_Msk (0x1U << CAN_F18R1_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F18R1_FB14 CAN_F18R1_FB14_Msk /*!< Filter bit 14 */
+#define CAN_F18R1_FB15_Pos (15U)
+#define CAN_F18R1_FB15_Msk (0x1U << CAN_F18R1_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F18R1_FB15 CAN_F18R1_FB15_Msk /*!< Filter bit 15 */
+#define CAN_F18R1_FB16_Pos (16U)
+#define CAN_F18R1_FB16_Msk (0x1U << CAN_F18R1_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F18R1_FB16 CAN_F18R1_FB16_Msk /*!< Filter bit 16 */
+#define CAN_F18R1_FB17_Pos (17U)
+#define CAN_F18R1_FB17_Msk (0x1U << CAN_F18R1_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F18R1_FB17 CAN_F18R1_FB17_Msk /*!< Filter bit 17 */
+#define CAN_F18R1_FB18_Pos (18U)
+#define CAN_F18R1_FB18_Msk (0x1U << CAN_F18R1_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F18R1_FB18 CAN_F18R1_FB18_Msk /*!< Filter bit 18 */
+#define CAN_F18R1_FB19_Pos (19U)
+#define CAN_F18R1_FB19_Msk (0x1U << CAN_F18R1_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F18R1_FB19 CAN_F18R1_FB19_Msk /*!< Filter bit 19 */
+#define CAN_F18R1_FB20_Pos (20U)
+#define CAN_F18R1_FB20_Msk (0x1U << CAN_F18R1_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F18R1_FB20 CAN_F18R1_FB20_Msk /*!< Filter bit 20 */
+#define CAN_F18R1_FB21_Pos (21U)
+#define CAN_F18R1_FB21_Msk (0x1U << CAN_F18R1_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F18R1_FB21 CAN_F18R1_FB21_Msk /*!< Filter bit 21 */
+#define CAN_F18R1_FB22_Pos (22U)
+#define CAN_F18R1_FB22_Msk (0x1U << CAN_F18R1_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F18R1_FB22 CAN_F18R1_FB22_Msk /*!< Filter bit 22 */
+#define CAN_F18R1_FB23_Pos (23U)
+#define CAN_F18R1_FB23_Msk (0x1U << CAN_F18R1_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F18R1_FB23 CAN_F18R1_FB23_Msk /*!< Filter bit 23 */
+#define CAN_F18R1_FB24_Pos (24U)
+#define CAN_F18R1_FB24_Msk (0x1U << CAN_F18R1_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F18R1_FB24 CAN_F18R1_FB24_Msk /*!< Filter bit 24 */
+#define CAN_F18R1_FB25_Pos (25U)
+#define CAN_F18R1_FB25_Msk (0x1U << CAN_F18R1_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F18R1_FB25 CAN_F18R1_FB25_Msk /*!< Filter bit 25 */
+#define CAN_F18R1_FB26_Pos (26U)
+#define CAN_F18R1_FB26_Msk (0x1U << CAN_F18R1_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F18R1_FB26 CAN_F18R1_FB26_Msk /*!< Filter bit 26 */
+#define CAN_F18R1_FB27_Pos (27U)
+#define CAN_F18R1_FB27_Msk (0x1U << CAN_F18R1_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F18R1_FB27 CAN_F18R1_FB27_Msk /*!< Filter bit 27 */
+#define CAN_F18R1_FB28_Pos (28U)
+#define CAN_F18R1_FB28_Msk (0x1U << CAN_F18R1_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F18R1_FB28 CAN_F18R1_FB28_Msk /*!< Filter bit 28 */
+#define CAN_F18R1_FB29_Pos (29U)
+#define CAN_F18R1_FB29_Msk (0x1U << CAN_F18R1_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F18R1_FB29 CAN_F18R1_FB29_Msk /*!< Filter bit 29 */
+#define CAN_F18R1_FB30_Pos (30U)
+#define CAN_F18R1_FB30_Msk (0x1U << CAN_F18R1_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F18R1_FB30 CAN_F18R1_FB30_Msk /*!< Filter bit 30 */
+#define CAN_F18R1_FB31_Pos (31U)
+#define CAN_F18R1_FB31_Msk (0x1U << CAN_F18R1_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F18R1_FB31 CAN_F18R1_FB31_Msk /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F19R1 register ******************/
+#define CAN_F19R1_FB0_Pos (0U)
+#define CAN_F19R1_FB0_Msk (0x1U << CAN_F19R1_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F19R1_FB0 CAN_F19R1_FB0_Msk /*!< Filter bit 0 */
+#define CAN_F19R1_FB1_Pos (1U)
+#define CAN_F19R1_FB1_Msk (0x1U << CAN_F19R1_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F19R1_FB1 CAN_F19R1_FB1_Msk /*!< Filter bit 1 */
+#define CAN_F19R1_FB2_Pos (2U)
+#define CAN_F19R1_FB2_Msk (0x1U << CAN_F19R1_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F19R1_FB2 CAN_F19R1_FB2_Msk /*!< Filter bit 2 */
+#define CAN_F19R1_FB3_Pos (3U)
+#define CAN_F19R1_FB3_Msk (0x1U << CAN_F19R1_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F19R1_FB3 CAN_F19R1_FB3_Msk /*!< Filter bit 3 */
+#define CAN_F19R1_FB4_Pos (4U)
+#define CAN_F19R1_FB4_Msk (0x1U << CAN_F19R1_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F19R1_FB4 CAN_F19R1_FB4_Msk /*!< Filter bit 4 */
+#define CAN_F19R1_FB5_Pos (5U)
+#define CAN_F19R1_FB5_Msk (0x1U << CAN_F19R1_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F19R1_FB5 CAN_F19R1_FB5_Msk /*!< Filter bit 5 */
+#define CAN_F19R1_FB6_Pos (6U)
+#define CAN_F19R1_FB6_Msk (0x1U << CAN_F19R1_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F19R1_FB6 CAN_F19R1_FB6_Msk /*!< Filter bit 6 */
+#define CAN_F19R1_FB7_Pos (7U)
+#define CAN_F19R1_FB7_Msk (0x1U << CAN_F19R1_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F19R1_FB7 CAN_F19R1_FB7_Msk /*!< Filter bit 7 */
+#define CAN_F19R1_FB8_Pos (8U)
+#define CAN_F19R1_FB8_Msk (0x1U << CAN_F19R1_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F19R1_FB8 CAN_F19R1_FB8_Msk /*!< Filter bit 8 */
+#define CAN_F19R1_FB9_Pos (9U)
+#define CAN_F19R1_FB9_Msk (0x1U << CAN_F19R1_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F19R1_FB9 CAN_F19R1_FB9_Msk /*!< Filter bit 9 */
+#define CAN_F19R1_FB10_Pos (10U)
+#define CAN_F19R1_FB10_Msk (0x1U << CAN_F19R1_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F19R1_FB10 CAN_F19R1_FB10_Msk /*!< Filter bit 10 */
+#define CAN_F19R1_FB11_Pos (11U)
+#define CAN_F19R1_FB11_Msk (0x1U << CAN_F19R1_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F19R1_FB11 CAN_F19R1_FB11_Msk /*!< Filter bit 11 */
+#define CAN_F19R1_FB12_Pos (12U)
+#define CAN_F19R1_FB12_Msk (0x1U << CAN_F19R1_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F19R1_FB12 CAN_F19R1_FB12_Msk /*!< Filter bit 12 */
+#define CAN_F19R1_FB13_Pos (13U)
+#define CAN_F19R1_FB13_Msk (0x1U << CAN_F19R1_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F19R1_FB13 CAN_F19R1_FB13_Msk /*!< Filter bit 13 */
+#define CAN_F19R1_FB14_Pos (14U)
+#define CAN_F19R1_FB14_Msk (0x1U << CAN_F19R1_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F19R1_FB14 CAN_F19R1_FB14_Msk /*!< Filter bit 14 */
+#define CAN_F19R1_FB15_Pos (15U)
+#define CAN_F19R1_FB15_Msk (0x1U << CAN_F19R1_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F19R1_FB15 CAN_F19R1_FB15_Msk /*!< Filter bit 15 */
+#define CAN_F19R1_FB16_Pos (16U)
+#define CAN_F19R1_FB16_Msk (0x1U << CAN_F19R1_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F19R1_FB16 CAN_F19R1_FB16_Msk /*!< Filter bit 16 */
+#define CAN_F19R1_FB17_Pos (17U)
+#define CAN_F19R1_FB17_Msk (0x1U << CAN_F19R1_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F19R1_FB17 CAN_F19R1_FB17_Msk /*!< Filter bit 17 */
+#define CAN_F19R1_FB18_Pos (18U)
+#define CAN_F19R1_FB18_Msk (0x1U << CAN_F19R1_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F19R1_FB18 CAN_F19R1_FB18_Msk /*!< Filter bit 18 */
+#define CAN_F19R1_FB19_Pos (19U)
+#define CAN_F19R1_FB19_Msk (0x1U << CAN_F19R1_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F19R1_FB19 CAN_F19R1_FB19_Msk /*!< Filter bit 19 */
+#define CAN_F19R1_FB20_Pos (20U)
+#define CAN_F19R1_FB20_Msk (0x1U << CAN_F19R1_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F19R1_FB20 CAN_F19R1_FB20_Msk /*!< Filter bit 20 */
+#define CAN_F19R1_FB21_Pos (21U)
+#define CAN_F19R1_FB21_Msk (0x1U << CAN_F19R1_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F19R1_FB21 CAN_F19R1_FB21_Msk /*!< Filter bit 21 */
+#define CAN_F19R1_FB22_Pos (22U)
+#define CAN_F19R1_FB22_Msk (0x1U << CAN_F19R1_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F19R1_FB22 CAN_F19R1_FB22_Msk /*!< Filter bit 22 */
+#define CAN_F19R1_FB23_Pos (23U)
+#define CAN_F19R1_FB23_Msk (0x1U << CAN_F19R1_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F19R1_FB23 CAN_F19R1_FB23_Msk /*!< Filter bit 23 */
+#define CAN_F19R1_FB24_Pos (24U)
+#define CAN_F19R1_FB24_Msk (0x1U << CAN_F19R1_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F19R1_FB24 CAN_F19R1_FB24_Msk /*!< Filter bit 24 */
+#define CAN_F19R1_FB25_Pos (25U)
+#define CAN_F19R1_FB25_Msk (0x1U << CAN_F19R1_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F19R1_FB25 CAN_F19R1_FB25_Msk /*!< Filter bit 25 */
+#define CAN_F19R1_FB26_Pos (26U)
+#define CAN_F19R1_FB26_Msk (0x1U << CAN_F19R1_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F19R1_FB26 CAN_F19R1_FB26_Msk /*!< Filter bit 26 */
+#define CAN_F19R1_FB27_Pos (27U)
+#define CAN_F19R1_FB27_Msk (0x1U << CAN_F19R1_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F19R1_FB27 CAN_F19R1_FB27_Msk /*!< Filter bit 27 */
+#define CAN_F19R1_FB28_Pos (28U)
+#define CAN_F19R1_FB28_Msk (0x1U << CAN_F19R1_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F19R1_FB28 CAN_F19R1_FB28_Msk /*!< Filter bit 28 */
+#define CAN_F19R1_FB29_Pos (29U)
+#define CAN_F19R1_FB29_Msk (0x1U << CAN_F19R1_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F19R1_FB29 CAN_F19R1_FB29_Msk /*!< Filter bit 29 */
+#define CAN_F19R1_FB30_Pos (30U)
+#define CAN_F19R1_FB30_Msk (0x1U << CAN_F19R1_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F19R1_FB30 CAN_F19R1_FB30_Msk /*!< Filter bit 30 */
+#define CAN_F19R1_FB31_Pos (31U)
+#define CAN_F19R1_FB31_Msk (0x1U << CAN_F19R1_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F19R1_FB31 CAN_F19R1_FB31_Msk /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F20R1 register ******************/
+#define CAN_F20R1_FB0_Pos (0U)
+#define CAN_F20R1_FB0_Msk (0x1U << CAN_F20R1_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F20R1_FB0 CAN_F20R1_FB0_Msk /*!< Filter bit 0 */
+#define CAN_F20R1_FB1_Pos (1U)
+#define CAN_F20R1_FB1_Msk (0x1U << CAN_F20R1_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F20R1_FB1 CAN_F20R1_FB1_Msk /*!< Filter bit 1 */
+#define CAN_F20R1_FB2_Pos (2U)
+#define CAN_F20R1_FB2_Msk (0x1U << CAN_F20R1_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F20R1_FB2 CAN_F20R1_FB2_Msk /*!< Filter bit 2 */
+#define CAN_F20R1_FB3_Pos (3U)
+#define CAN_F20R1_FB3_Msk (0x1U << CAN_F20R1_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F20R1_FB3 CAN_F20R1_FB3_Msk /*!< Filter bit 3 */
+#define CAN_F20R1_FB4_Pos (4U)
+#define CAN_F20R1_FB4_Msk (0x1U << CAN_F20R1_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F20R1_FB4 CAN_F20R1_FB4_Msk /*!< Filter bit 4 */
+#define CAN_F20R1_FB5_Pos (5U)
+#define CAN_F20R1_FB5_Msk (0x1U << CAN_F20R1_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F20R1_FB5 CAN_F20R1_FB5_Msk /*!< Filter bit 5 */
+#define CAN_F20R1_FB6_Pos (6U)
+#define CAN_F20R1_FB6_Msk (0x1U << CAN_F20R1_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F20R1_FB6 CAN_F20R1_FB6_Msk /*!< Filter bit 6 */
+#define CAN_F20R1_FB7_Pos (7U)
+#define CAN_F20R1_FB7_Msk (0x1U << CAN_F20R1_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F20R1_FB7 CAN_F20R1_FB7_Msk /*!< Filter bit 7 */
+#define CAN_F20R1_FB8_Pos (8U)
+#define CAN_F20R1_FB8_Msk (0x1U << CAN_F20R1_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F20R1_FB8 CAN_F20R1_FB8_Msk /*!< Filter bit 8 */
+#define CAN_F20R1_FB9_Pos (9U)
+#define CAN_F20R1_FB9_Msk (0x1U << CAN_F20R1_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F20R1_FB9 CAN_F20R1_FB9_Msk /*!< Filter bit 9 */
+#define CAN_F20R1_FB10_Pos (10U)
+#define CAN_F20R1_FB10_Msk (0x1U << CAN_F20R1_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F20R1_FB10 CAN_F20R1_FB10_Msk /*!< Filter bit 10 */
+#define CAN_F20R1_FB11_Pos (11U)
+#define CAN_F20R1_FB11_Msk (0x1U << CAN_F20R1_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F20R1_FB11 CAN_F20R1_FB11_Msk /*!< Filter bit 11 */
+#define CAN_F20R1_FB12_Pos (12U)
+#define CAN_F20R1_FB12_Msk (0x1U << CAN_F20R1_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F20R1_FB12 CAN_F20R1_FB12_Msk /*!< Filter bit 12 */
+#define CAN_F20R1_FB13_Pos (13U)
+#define CAN_F20R1_FB13_Msk (0x1U << CAN_F20R1_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F20R1_FB13 CAN_F20R1_FB13_Msk /*!< Filter bit 13 */
+#define CAN_F20R1_FB14_Pos (14U)
+#define CAN_F20R1_FB14_Msk (0x1U << CAN_F20R1_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F20R1_FB14 CAN_F20R1_FB14_Msk /*!< Filter bit 14 */
+#define CAN_F20R1_FB15_Pos (15U)
+#define CAN_F20R1_FB15_Msk (0x1U << CAN_F20R1_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F20R1_FB15 CAN_F20R1_FB15_Msk /*!< Filter bit 15 */
+#define CAN_F20R1_FB16_Pos (16U)
+#define CAN_F20R1_FB16_Msk (0x1U << CAN_F20R1_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F20R1_FB16 CAN_F20R1_FB16_Msk /*!< Filter bit 16 */
+#define CAN_F20R1_FB17_Pos (17U)
+#define CAN_F20R1_FB17_Msk (0x1U << CAN_F20R1_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F20R1_FB17 CAN_F20R1_FB17_Msk /*!< Filter bit 17 */
+#define CAN_F20R1_FB18_Pos (18U)
+#define CAN_F20R1_FB18_Msk (0x1U << CAN_F20R1_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F20R1_FB18 CAN_F20R1_FB18_Msk /*!< Filter bit 18 */
+#define CAN_F20R1_FB19_Pos (19U)
+#define CAN_F20R1_FB19_Msk (0x1U << CAN_F20R1_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F20R1_FB19 CAN_F20R1_FB19_Msk /*!< Filter bit 19 */
+#define CAN_F20R1_FB20_Pos (20U)
+#define CAN_F20R1_FB20_Msk (0x1U << CAN_F20R1_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F20R1_FB20 CAN_F20R1_FB20_Msk /*!< Filter bit 20 */
+#define CAN_F20R1_FB21_Pos (21U)
+#define CAN_F20R1_FB21_Msk (0x1U << CAN_F20R1_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F20R1_FB21 CAN_F20R1_FB21_Msk /*!< Filter bit 21 */
+#define CAN_F20R1_FB22_Pos (22U)
+#define CAN_F20R1_FB22_Msk (0x1U << CAN_F20R1_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F20R1_FB22 CAN_F20R1_FB22_Msk /*!< Filter bit 22 */
+#define CAN_F20R1_FB23_Pos (23U)
+#define CAN_F20R1_FB23_Msk (0x1U << CAN_F20R1_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F20R1_FB23 CAN_F20R1_FB23_Msk /*!< Filter bit 23 */
+#define CAN_F20R1_FB24_Pos (24U)
+#define CAN_F20R1_FB24_Msk (0x1U << CAN_F20R1_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F20R1_FB24 CAN_F20R1_FB24_Msk /*!< Filter bit 24 */
+#define CAN_F20R1_FB25_Pos (25U)
+#define CAN_F20R1_FB25_Msk (0x1U << CAN_F20R1_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F20R1_FB25 CAN_F20R1_FB25_Msk /*!< Filter bit 25 */
+#define CAN_F20R1_FB26_Pos (26U)
+#define CAN_F20R1_FB26_Msk (0x1U << CAN_F20R1_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F20R1_FB26 CAN_F20R1_FB26_Msk /*!< Filter bit 26 */
+#define CAN_F20R1_FB27_Pos (27U)
+#define CAN_F20R1_FB27_Msk (0x1U << CAN_F20R1_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F20R1_FB27 CAN_F20R1_FB27_Msk /*!< Filter bit 27 */
+#define CAN_F20R1_FB28_Pos (28U)
+#define CAN_F20R1_FB28_Msk (0x1U << CAN_F20R1_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F20R1_FB28 CAN_F20R1_FB28_Msk /*!< Filter bit 28 */
+#define CAN_F20R1_FB29_Pos (29U)
+#define CAN_F20R1_FB29_Msk (0x1U << CAN_F20R1_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F20R1_FB29 CAN_F20R1_FB29_Msk /*!< Filter bit 29 */
+#define CAN_F20R1_FB30_Pos (30U)
+#define CAN_F20R1_FB30_Msk (0x1U << CAN_F20R1_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F20R1_FB30 CAN_F20R1_FB30_Msk /*!< Filter bit 30 */
+#define CAN_F20R1_FB31_Pos (31U)
+#define CAN_F20R1_FB31_Msk (0x1U << CAN_F20R1_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F20R1_FB31 CAN_F20R1_FB31_Msk /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F21R1 register ******************/
+#define CAN_F21R1_FB0_Pos (0U)
+#define CAN_F21R1_FB0_Msk (0x1U << CAN_F21R1_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F21R1_FB0 CAN_F21R1_FB0_Msk /*!< Filter bit 0 */
+#define CAN_F21R1_FB1_Pos (1U)
+#define CAN_F21R1_FB1_Msk (0x1U << CAN_F21R1_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F21R1_FB1 CAN_F21R1_FB1_Msk /*!< Filter bit 1 */
+#define CAN_F21R1_FB2_Pos (2U)
+#define CAN_F21R1_FB2_Msk (0x1U << CAN_F21R1_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F21R1_FB2 CAN_F21R1_FB2_Msk /*!< Filter bit 2 */
+#define CAN_F21R1_FB3_Pos (3U)
+#define CAN_F21R1_FB3_Msk (0x1U << CAN_F21R1_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F21R1_FB3 CAN_F21R1_FB3_Msk /*!< Filter bit 3 */
+#define CAN_F21R1_FB4_Pos (4U)
+#define CAN_F21R1_FB4_Msk (0x1U << CAN_F21R1_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F21R1_FB4 CAN_F21R1_FB4_Msk /*!< Filter bit 4 */
+#define CAN_F21R1_FB5_Pos (5U)
+#define CAN_F21R1_FB5_Msk (0x1U << CAN_F21R1_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F21R1_FB5 CAN_F21R1_FB5_Msk /*!< Filter bit 5 */
+#define CAN_F21R1_FB6_Pos (6U)
+#define CAN_F21R1_FB6_Msk (0x1U << CAN_F21R1_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F21R1_FB6 CAN_F21R1_FB6_Msk /*!< Filter bit 6 */
+#define CAN_F21R1_FB7_Pos (7U)
+#define CAN_F21R1_FB7_Msk (0x1U << CAN_F21R1_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F21R1_FB7 CAN_F21R1_FB7_Msk /*!< Filter bit 7 */
+#define CAN_F21R1_FB8_Pos (8U)
+#define CAN_F21R1_FB8_Msk (0x1U << CAN_F21R1_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F21R1_FB8 CAN_F21R1_FB8_Msk /*!< Filter bit 8 */
+#define CAN_F21R1_FB9_Pos (9U)
+#define CAN_F21R1_FB9_Msk (0x1U << CAN_F21R1_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F21R1_FB9 CAN_F21R1_FB9_Msk /*!< Filter bit 9 */
+#define CAN_F21R1_FB10_Pos (10U)
+#define CAN_F21R1_FB10_Msk (0x1U << CAN_F21R1_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F21R1_FB10 CAN_F21R1_FB10_Msk /*!< Filter bit 10 */
+#define CAN_F21R1_FB11_Pos (11U)
+#define CAN_F21R1_FB11_Msk (0x1U << CAN_F21R1_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F21R1_FB11 CAN_F21R1_FB11_Msk /*!< Filter bit 11 */
+#define CAN_F21R1_FB12_Pos (12U)
+#define CAN_F21R1_FB12_Msk (0x1U << CAN_F21R1_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F21R1_FB12 CAN_F21R1_FB12_Msk /*!< Filter bit 12 */
+#define CAN_F21R1_FB13_Pos (13U)
+#define CAN_F21R1_FB13_Msk (0x1U << CAN_F21R1_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F21R1_FB13 CAN_F21R1_FB13_Msk /*!< Filter bit 13 */
+#define CAN_F21R1_FB14_Pos (14U)
+#define CAN_F21R1_FB14_Msk (0x1U << CAN_F21R1_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F21R1_FB14 CAN_F21R1_FB14_Msk /*!< Filter bit 14 */
+#define CAN_F21R1_FB15_Pos (15U)
+#define CAN_F21R1_FB15_Msk (0x1U << CAN_F21R1_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F21R1_FB15 CAN_F21R1_FB15_Msk /*!< Filter bit 15 */
+#define CAN_F21R1_FB16_Pos (16U)
+#define CAN_F21R1_FB16_Msk (0x1U << CAN_F21R1_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F21R1_FB16 CAN_F21R1_FB16_Msk /*!< Filter bit 16 */
+#define CAN_F21R1_FB17_Pos (17U)
+#define CAN_F21R1_FB17_Msk (0x1U << CAN_F21R1_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F21R1_FB17 CAN_F21R1_FB17_Msk /*!< Filter bit 17 */
+#define CAN_F21R1_FB18_Pos (18U)
+#define CAN_F21R1_FB18_Msk (0x1U << CAN_F21R1_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F21R1_FB18 CAN_F21R1_FB18_Msk /*!< Filter bit 18 */
+#define CAN_F21R1_FB19_Pos (19U)
+#define CAN_F21R1_FB19_Msk (0x1U << CAN_F21R1_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F21R1_FB19 CAN_F21R1_FB19_Msk /*!< Filter bit 19 */
+#define CAN_F21R1_FB20_Pos (20U)
+#define CAN_F21R1_FB20_Msk (0x1U << CAN_F21R1_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F21R1_FB20 CAN_F21R1_FB20_Msk /*!< Filter bit 20 */
+#define CAN_F21R1_FB21_Pos (21U)
+#define CAN_F21R1_FB21_Msk (0x1U << CAN_F21R1_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F21R1_FB21 CAN_F21R1_FB21_Msk /*!< Filter bit 21 */
+#define CAN_F21R1_FB22_Pos (22U)
+#define CAN_F21R1_FB22_Msk (0x1U << CAN_F21R1_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F21R1_FB22 CAN_F21R1_FB22_Msk /*!< Filter bit 22 */
+#define CAN_F21R1_FB23_Pos (23U)
+#define CAN_F21R1_FB23_Msk (0x1U << CAN_F21R1_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F21R1_FB23 CAN_F21R1_FB23_Msk /*!< Filter bit 23 */
+#define CAN_F21R1_FB24_Pos (24U)
+#define CAN_F21R1_FB24_Msk (0x1U << CAN_F21R1_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F21R1_FB24 CAN_F21R1_FB24_Msk /*!< Filter bit 24 */
+#define CAN_F21R1_FB25_Pos (25U)
+#define CAN_F21R1_FB25_Msk (0x1U << CAN_F21R1_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F21R1_FB25 CAN_F21R1_FB25_Msk /*!< Filter bit 25 */
+#define CAN_F21R1_FB26_Pos (26U)
+#define CAN_F21R1_FB26_Msk (0x1U << CAN_F21R1_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F21R1_FB26 CAN_F21R1_FB26_Msk /*!< Filter bit 26 */
+#define CAN_F21R1_FB27_Pos (27U)
+#define CAN_F21R1_FB27_Msk (0x1U << CAN_F21R1_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F21R1_FB27 CAN_F21R1_FB27_Msk /*!< Filter bit 27 */
+#define CAN_F21R1_FB28_Pos (28U)
+#define CAN_F21R1_FB28_Msk (0x1U << CAN_F21R1_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F21R1_FB28 CAN_F21R1_FB28_Msk /*!< Filter bit 28 */
+#define CAN_F21R1_FB29_Pos (29U)
+#define CAN_F21R1_FB29_Msk (0x1U << CAN_F21R1_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F21R1_FB29 CAN_F21R1_FB29_Msk /*!< Filter bit 29 */
+#define CAN_F21R1_FB30_Pos (30U)
+#define CAN_F21R1_FB30_Msk (0x1U << CAN_F21R1_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F21R1_FB30 CAN_F21R1_FB30_Msk /*!< Filter bit 30 */
+#define CAN_F21R1_FB31_Pos (31U)
+#define CAN_F21R1_FB31_Msk (0x1U << CAN_F21R1_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F21R1_FB31 CAN_F21R1_FB31_Msk /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F22R1 register ******************/
+#define CAN_F22R1_FB0_Pos (0U)
+#define CAN_F22R1_FB0_Msk (0x1U << CAN_F22R1_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F22R1_FB0 CAN_F22R1_FB0_Msk /*!< Filter bit 0 */
+#define CAN_F22R1_FB1_Pos (1U)
+#define CAN_F22R1_FB1_Msk (0x1U << CAN_F22R1_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F22R1_FB1 CAN_F22R1_FB1_Msk /*!< Filter bit 1 */
+#define CAN_F22R1_FB2_Pos (2U)
+#define CAN_F22R1_FB2_Msk (0x1U << CAN_F22R1_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F22R1_FB2 CAN_F22R1_FB2_Msk /*!< Filter bit 2 */
+#define CAN_F22R1_FB3_Pos (3U)
+#define CAN_F22R1_FB3_Msk (0x1U << CAN_F22R1_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F22R1_FB3 CAN_F22R1_FB3_Msk /*!< Filter bit 3 */
+#define CAN_F22R1_FB4_Pos (4U)
+#define CAN_F22R1_FB4_Msk (0x1U << CAN_F22R1_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F22R1_FB4 CAN_F22R1_FB4_Msk /*!< Filter bit 4 */
+#define CAN_F22R1_FB5_Pos (5U)
+#define CAN_F22R1_FB5_Msk (0x1U << CAN_F22R1_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F22R1_FB5 CAN_F22R1_FB5_Msk /*!< Filter bit 5 */
+#define CAN_F22R1_FB6_Pos (6U)
+#define CAN_F22R1_FB6_Msk (0x1U << CAN_F22R1_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F22R1_FB6 CAN_F22R1_FB6_Msk /*!< Filter bit 6 */
+#define CAN_F22R1_FB7_Pos (7U)
+#define CAN_F22R1_FB7_Msk (0x1U << CAN_F22R1_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F22R1_FB7 CAN_F22R1_FB7_Msk /*!< Filter bit 7 */
+#define CAN_F22R1_FB8_Pos (8U)
+#define CAN_F22R1_FB8_Msk (0x1U << CAN_F22R1_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F22R1_FB8 CAN_F22R1_FB8_Msk /*!< Filter bit 8 */
+#define CAN_F22R1_FB9_Pos (9U)
+#define CAN_F22R1_FB9_Msk (0x1U << CAN_F22R1_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F22R1_FB9 CAN_F22R1_FB9_Msk /*!< Filter bit 9 */
+#define CAN_F22R1_FB10_Pos (10U)
+#define CAN_F22R1_FB10_Msk (0x1U << CAN_F22R1_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F22R1_FB10 CAN_F22R1_FB10_Msk /*!< Filter bit 10 */
+#define CAN_F22R1_FB11_Pos (11U)
+#define CAN_F22R1_FB11_Msk (0x1U << CAN_F22R1_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F22R1_FB11 CAN_F22R1_FB11_Msk /*!< Filter bit 11 */
+#define CAN_F22R1_FB12_Pos (12U)
+#define CAN_F22R1_FB12_Msk (0x1U << CAN_F22R1_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F22R1_FB12 CAN_F22R1_FB12_Msk /*!< Filter bit 12 */
+#define CAN_F22R1_FB13_Pos (13U)
+#define CAN_F22R1_FB13_Msk (0x1U << CAN_F22R1_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F22R1_FB13 CAN_F22R1_FB13_Msk /*!< Filter bit 13 */
+#define CAN_F22R1_FB14_Pos (14U)
+#define CAN_F22R1_FB14_Msk (0x1U << CAN_F22R1_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F22R1_FB14 CAN_F22R1_FB14_Msk /*!< Filter bit 14 */
+#define CAN_F22R1_FB15_Pos (15U)
+#define CAN_F22R1_FB15_Msk (0x1U << CAN_F22R1_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F22R1_FB15 CAN_F22R1_FB15_Msk /*!< Filter bit 15 */
+#define CAN_F22R1_FB16_Pos (16U)
+#define CAN_F22R1_FB16_Msk (0x1U << CAN_F22R1_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F22R1_FB16 CAN_F22R1_FB16_Msk /*!< Filter bit 16 */
+#define CAN_F22R1_FB17_Pos (17U)
+#define CAN_F22R1_FB17_Msk (0x1U << CAN_F22R1_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F22R1_FB17 CAN_F22R1_FB17_Msk /*!< Filter bit 17 */
+#define CAN_F22R1_FB18_Pos (18U)
+#define CAN_F22R1_FB18_Msk (0x1U << CAN_F22R1_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F22R1_FB18 CAN_F22R1_FB18_Msk /*!< Filter bit 18 */
+#define CAN_F22R1_FB19_Pos (19U)
+#define CAN_F22R1_FB19_Msk (0x1U << CAN_F22R1_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F22R1_FB19 CAN_F22R1_FB19_Msk /*!< Filter bit 19 */
+#define CAN_F22R1_FB20_Pos (20U)
+#define CAN_F22R1_FB20_Msk (0x1U << CAN_F22R1_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F22R1_FB20 CAN_F22R1_FB20_Msk /*!< Filter bit 20 */
+#define CAN_F22R1_FB21_Pos (21U)
+#define CAN_F22R1_FB21_Msk (0x1U << CAN_F22R1_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F22R1_FB21 CAN_F22R1_FB21_Msk /*!< Filter bit 21 */
+#define CAN_F22R1_FB22_Pos (22U)
+#define CAN_F22R1_FB22_Msk (0x1U << CAN_F22R1_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F22R1_FB22 CAN_F22R1_FB22_Msk /*!< Filter bit 22 */
+#define CAN_F22R1_FB23_Pos (23U)
+#define CAN_F22R1_FB23_Msk (0x1U << CAN_F22R1_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F22R1_FB23 CAN_F22R1_FB23_Msk /*!< Filter bit 23 */
+#define CAN_F22R1_FB24_Pos (24U)
+#define CAN_F22R1_FB24_Msk (0x1U << CAN_F22R1_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F22R1_FB24 CAN_F22R1_FB24_Msk /*!< Filter bit 24 */
+#define CAN_F22R1_FB25_Pos (25U)
+#define CAN_F22R1_FB25_Msk (0x1U << CAN_F22R1_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F22R1_FB25 CAN_F22R1_FB25_Msk /*!< Filter bit 25 */
+#define CAN_F22R1_FB26_Pos (26U)
+#define CAN_F22R1_FB26_Msk (0x1U << CAN_F22R1_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F22R1_FB26 CAN_F22R1_FB26_Msk /*!< Filter bit 26 */
+#define CAN_F22R1_FB27_Pos (27U)
+#define CAN_F22R1_FB27_Msk (0x1U << CAN_F22R1_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F22R1_FB27 CAN_F22R1_FB27_Msk /*!< Filter bit 27 */
+#define CAN_F22R1_FB28_Pos (28U)
+#define CAN_F22R1_FB28_Msk (0x1U << CAN_F22R1_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F22R1_FB28 CAN_F22R1_FB28_Msk /*!< Filter bit 28 */
+#define CAN_F22R1_FB29_Pos (29U)
+#define CAN_F22R1_FB29_Msk (0x1U << CAN_F22R1_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F22R1_FB29 CAN_F22R1_FB29_Msk /*!< Filter bit 29 */
+#define CAN_F22R1_FB30_Pos (30U)
+#define CAN_F22R1_FB30_Msk (0x1U << CAN_F22R1_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F22R1_FB30 CAN_F22R1_FB30_Msk /*!< Filter bit 30 */
+#define CAN_F22R1_FB31_Pos (31U)
+#define CAN_F22R1_FB31_Msk (0x1U << CAN_F22R1_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F22R1_FB31 CAN_F22R1_FB31_Msk /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F23R1 register ******************/
+#define CAN_F23R1_FB0_Pos (0U)
+#define CAN_F23R1_FB0_Msk (0x1U << CAN_F23R1_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F23R1_FB0 CAN_F23R1_FB0_Msk /*!< Filter bit 0 */
+#define CAN_F23R1_FB1_Pos (1U)
+#define CAN_F23R1_FB1_Msk (0x1U << CAN_F23R1_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F23R1_FB1 CAN_F23R1_FB1_Msk /*!< Filter bit 1 */
+#define CAN_F23R1_FB2_Pos (2U)
+#define CAN_F23R1_FB2_Msk (0x1U << CAN_F23R1_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F23R1_FB2 CAN_F23R1_FB2_Msk /*!< Filter bit 2 */
+#define CAN_F23R1_FB3_Pos (3U)
+#define CAN_F23R1_FB3_Msk (0x1U << CAN_F23R1_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F23R1_FB3 CAN_F23R1_FB3_Msk /*!< Filter bit 3 */
+#define CAN_F23R1_FB4_Pos (4U)
+#define CAN_F23R1_FB4_Msk (0x1U << CAN_F23R1_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F23R1_FB4 CAN_F23R1_FB4_Msk /*!< Filter bit 4 */
+#define CAN_F23R1_FB5_Pos (5U)
+#define CAN_F23R1_FB5_Msk (0x1U << CAN_F23R1_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F23R1_FB5 CAN_F23R1_FB5_Msk /*!< Filter bit 5 */
+#define CAN_F23R1_FB6_Pos (6U)
+#define CAN_F23R1_FB6_Msk (0x1U << CAN_F23R1_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F23R1_FB6 CAN_F23R1_FB6_Msk /*!< Filter bit 6 */
+#define CAN_F23R1_FB7_Pos (7U)
+#define CAN_F23R1_FB7_Msk (0x1U << CAN_F23R1_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F23R1_FB7 CAN_F23R1_FB7_Msk /*!< Filter bit 7 */
+#define CAN_F23R1_FB8_Pos (8U)
+#define CAN_F23R1_FB8_Msk (0x1U << CAN_F23R1_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F23R1_FB8 CAN_F23R1_FB8_Msk /*!< Filter bit 8 */
+#define CAN_F23R1_FB9_Pos (9U)
+#define CAN_F23R1_FB9_Msk (0x1U << CAN_F23R1_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F23R1_FB9 CAN_F23R1_FB9_Msk /*!< Filter bit 9 */
+#define CAN_F23R1_FB10_Pos (10U)
+#define CAN_F23R1_FB10_Msk (0x1U << CAN_F23R1_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F23R1_FB10 CAN_F23R1_FB10_Msk /*!< Filter bit 10 */
+#define CAN_F23R1_FB11_Pos (11U)
+#define CAN_F23R1_FB11_Msk (0x1U << CAN_F23R1_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F23R1_FB11 CAN_F23R1_FB11_Msk /*!< Filter bit 11 */
+#define CAN_F23R1_FB12_Pos (12U)
+#define CAN_F23R1_FB12_Msk (0x1U << CAN_F23R1_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F23R1_FB12 CAN_F23R1_FB12_Msk /*!< Filter bit 12 */
+#define CAN_F23R1_FB13_Pos (13U)
+#define CAN_F23R1_FB13_Msk (0x1U << CAN_F23R1_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F23R1_FB13 CAN_F23R1_FB13_Msk /*!< Filter bit 13 */
+#define CAN_F23R1_FB14_Pos (14U)
+#define CAN_F23R1_FB14_Msk (0x1U << CAN_F23R1_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F23R1_FB14 CAN_F23R1_FB14_Msk /*!< Filter bit 14 */
+#define CAN_F23R1_FB15_Pos (15U)
+#define CAN_F23R1_FB15_Msk (0x1U << CAN_F23R1_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F23R1_FB15 CAN_F23R1_FB15_Msk /*!< Filter bit 15 */
+#define CAN_F23R1_FB16_Pos (16U)
+#define CAN_F23R1_FB16_Msk (0x1U << CAN_F23R1_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F23R1_FB16 CAN_F23R1_FB16_Msk /*!< Filter bit 16 */
+#define CAN_F23R1_FB17_Pos (17U)
+#define CAN_F23R1_FB17_Msk (0x1U << CAN_F23R1_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F23R1_FB17 CAN_F23R1_FB17_Msk /*!< Filter bit 17 */
+#define CAN_F23R1_FB18_Pos (18U)
+#define CAN_F23R1_FB18_Msk (0x1U << CAN_F23R1_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F23R1_FB18 CAN_F23R1_FB18_Msk /*!< Filter bit 18 */
+#define CAN_F23R1_FB19_Pos (19U)
+#define CAN_F23R1_FB19_Msk (0x1U << CAN_F23R1_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F23R1_FB19 CAN_F23R1_FB19_Msk /*!< Filter bit 19 */
+#define CAN_F23R1_FB20_Pos (20U)
+#define CAN_F23R1_FB20_Msk (0x1U << CAN_F23R1_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F23R1_FB20 CAN_F23R1_FB20_Msk /*!< Filter bit 20 */
+#define CAN_F23R1_FB21_Pos (21U)
+#define CAN_F23R1_FB21_Msk (0x1U << CAN_F23R1_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F23R1_FB21 CAN_F23R1_FB21_Msk /*!< Filter bit 21 */
+#define CAN_F23R1_FB22_Pos (22U)
+#define CAN_F23R1_FB22_Msk (0x1U << CAN_F23R1_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F23R1_FB22 CAN_F23R1_FB22_Msk /*!< Filter bit 22 */
+#define CAN_F23R1_FB23_Pos (23U)
+#define CAN_F23R1_FB23_Msk (0x1U << CAN_F23R1_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F23R1_FB23 CAN_F23R1_FB23_Msk /*!< Filter bit 23 */
+#define CAN_F23R1_FB24_Pos (24U)
+#define CAN_F23R1_FB24_Msk (0x1U << CAN_F23R1_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F23R1_FB24 CAN_F23R1_FB24_Msk /*!< Filter bit 24 */
+#define CAN_F23R1_FB25_Pos (25U)
+#define CAN_F23R1_FB25_Msk (0x1U << CAN_F23R1_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F23R1_FB25 CAN_F23R1_FB25_Msk /*!< Filter bit 25 */
+#define CAN_F23R1_FB26_Pos (26U)
+#define CAN_F23R1_FB26_Msk (0x1U << CAN_F23R1_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F23R1_FB26 CAN_F23R1_FB26_Msk /*!< Filter bit 26 */
+#define CAN_F23R1_FB27_Pos (27U)
+#define CAN_F23R1_FB27_Msk (0x1U << CAN_F23R1_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F23R1_FB27 CAN_F23R1_FB27_Msk /*!< Filter bit 27 */
+#define CAN_F23R1_FB28_Pos (28U)
+#define CAN_F23R1_FB28_Msk (0x1U << CAN_F23R1_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F23R1_FB28 CAN_F23R1_FB28_Msk /*!< Filter bit 28 */
+#define CAN_F23R1_FB29_Pos (29U)
+#define CAN_F23R1_FB29_Msk (0x1U << CAN_F23R1_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F23R1_FB29 CAN_F23R1_FB29_Msk /*!< Filter bit 29 */
+#define CAN_F23R1_FB30_Pos (30U)
+#define CAN_F23R1_FB30_Msk (0x1U << CAN_F23R1_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F23R1_FB30 CAN_F23R1_FB30_Msk /*!< Filter bit 30 */
+#define CAN_F23R1_FB31_Pos (31U)
+#define CAN_F23R1_FB31_Msk (0x1U << CAN_F23R1_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F23R1_FB31 CAN_F23R1_FB31_Msk /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F24R1 register ******************/
+#define CAN_F24R1_FB0_Pos (0U)
+#define CAN_F24R1_FB0_Msk (0x1U << CAN_F24R1_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F24R1_FB0 CAN_F24R1_FB0_Msk /*!< Filter bit 0 */
+#define CAN_F24R1_FB1_Pos (1U)
+#define CAN_F24R1_FB1_Msk (0x1U << CAN_F24R1_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F24R1_FB1 CAN_F24R1_FB1_Msk /*!< Filter bit 1 */
+#define CAN_F24R1_FB2_Pos (2U)
+#define CAN_F24R1_FB2_Msk (0x1U << CAN_F24R1_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F24R1_FB2 CAN_F24R1_FB2_Msk /*!< Filter bit 2 */
+#define CAN_F24R1_FB3_Pos (3U)
+#define CAN_F24R1_FB3_Msk (0x1U << CAN_F24R1_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F24R1_FB3 CAN_F24R1_FB3_Msk /*!< Filter bit 3 */
+#define CAN_F24R1_FB4_Pos (4U)
+#define CAN_F24R1_FB4_Msk (0x1U << CAN_F24R1_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F24R1_FB4 CAN_F24R1_FB4_Msk /*!< Filter bit 4 */
+#define CAN_F24R1_FB5_Pos (5U)
+#define CAN_F24R1_FB5_Msk (0x1U << CAN_F24R1_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F24R1_FB5 CAN_F24R1_FB5_Msk /*!< Filter bit 5 */
+#define CAN_F24R1_FB6_Pos (6U)
+#define CAN_F24R1_FB6_Msk (0x1U << CAN_F24R1_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F24R1_FB6 CAN_F24R1_FB6_Msk /*!< Filter bit 6 */
+#define CAN_F24R1_FB7_Pos (7U)
+#define CAN_F24R1_FB7_Msk (0x1U << CAN_F24R1_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F24R1_FB7 CAN_F24R1_FB7_Msk /*!< Filter bit 7 */
+#define CAN_F24R1_FB8_Pos (8U)
+#define CAN_F24R1_FB8_Msk (0x1U << CAN_F24R1_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F24R1_FB8 CAN_F24R1_FB8_Msk /*!< Filter bit 8 */
+#define CAN_F24R1_FB9_Pos (9U)
+#define CAN_F24R1_FB9_Msk (0x1U << CAN_F24R1_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F24R1_FB9 CAN_F24R1_FB9_Msk /*!< Filter bit 9 */
+#define CAN_F24R1_FB10_Pos (10U)
+#define CAN_F24R1_FB10_Msk (0x1U << CAN_F24R1_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F24R1_FB10 CAN_F24R1_FB10_Msk /*!< Filter bit 10 */
+#define CAN_F24R1_FB11_Pos (11U)
+#define CAN_F24R1_FB11_Msk (0x1U << CAN_F24R1_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F24R1_FB11 CAN_F24R1_FB11_Msk /*!< Filter bit 11 */
+#define CAN_F24R1_FB12_Pos (12U)
+#define CAN_F24R1_FB12_Msk (0x1U << CAN_F24R1_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F24R1_FB12 CAN_F24R1_FB12_Msk /*!< Filter bit 12 */
+#define CAN_F24R1_FB13_Pos (13U)
+#define CAN_F24R1_FB13_Msk (0x1U << CAN_F24R1_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F24R1_FB13 CAN_F24R1_FB13_Msk /*!< Filter bit 13 */
+#define CAN_F24R1_FB14_Pos (14U)
+#define CAN_F24R1_FB14_Msk (0x1U << CAN_F24R1_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F24R1_FB14 CAN_F24R1_FB14_Msk /*!< Filter bit 14 */
+#define CAN_F24R1_FB15_Pos (15U)
+#define CAN_F24R1_FB15_Msk (0x1U << CAN_F24R1_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F24R1_FB15 CAN_F24R1_FB15_Msk /*!< Filter bit 15 */
+#define CAN_F24R1_FB16_Pos (16U)
+#define CAN_F24R1_FB16_Msk (0x1U << CAN_F24R1_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F24R1_FB16 CAN_F24R1_FB16_Msk /*!< Filter bit 16 */
+#define CAN_F24R1_FB17_Pos (17U)
+#define CAN_F24R1_FB17_Msk (0x1U << CAN_F24R1_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F24R1_FB17 CAN_F24R1_FB17_Msk /*!< Filter bit 17 */
+#define CAN_F24R1_FB18_Pos (18U)
+#define CAN_F24R1_FB18_Msk (0x1U << CAN_F24R1_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F24R1_FB18 CAN_F24R1_FB18_Msk /*!< Filter bit 18 */
+#define CAN_F24R1_FB19_Pos (19U)
+#define CAN_F24R1_FB19_Msk (0x1U << CAN_F24R1_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F24R1_FB19 CAN_F24R1_FB19_Msk /*!< Filter bit 19 */
+#define CAN_F24R1_FB20_Pos (20U)
+#define CAN_F24R1_FB20_Msk (0x1U << CAN_F24R1_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F24R1_FB20 CAN_F24R1_FB20_Msk /*!< Filter bit 20 */
+#define CAN_F24R1_FB21_Pos (21U)
+#define CAN_F24R1_FB21_Msk (0x1U << CAN_F24R1_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F24R1_FB21 CAN_F24R1_FB21_Msk /*!< Filter bit 21 */
+#define CAN_F24R1_FB22_Pos (22U)
+#define CAN_F24R1_FB22_Msk (0x1U << CAN_F24R1_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F24R1_FB22 CAN_F24R1_FB22_Msk /*!< Filter bit 22 */
+#define CAN_F24R1_FB23_Pos (23U)
+#define CAN_F24R1_FB23_Msk (0x1U << CAN_F24R1_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F24R1_FB23 CAN_F24R1_FB23_Msk /*!< Filter bit 23 */
+#define CAN_F24R1_FB24_Pos (24U)
+#define CAN_F24R1_FB24_Msk (0x1U << CAN_F24R1_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F24R1_FB24 CAN_F24R1_FB24_Msk /*!< Filter bit 24 */
+#define CAN_F24R1_FB25_Pos (25U)
+#define CAN_F24R1_FB25_Msk (0x1U << CAN_F24R1_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F24R1_FB25 CAN_F24R1_FB25_Msk /*!< Filter bit 25 */
+#define CAN_F24R1_FB26_Pos (26U)
+#define CAN_F24R1_FB26_Msk (0x1U << CAN_F24R1_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F24R1_FB26 CAN_F24R1_FB26_Msk /*!< Filter bit 26 */
+#define CAN_F24R1_FB27_Pos (27U)
+#define CAN_F24R1_FB27_Msk (0x1U << CAN_F24R1_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F24R1_FB27 CAN_F24R1_FB27_Msk /*!< Filter bit 27 */
+#define CAN_F24R1_FB28_Pos (28U)
+#define CAN_F24R1_FB28_Msk (0x1U << CAN_F24R1_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F24R1_FB28 CAN_F24R1_FB28_Msk /*!< Filter bit 28 */
+#define CAN_F24R1_FB29_Pos (29U)
+#define CAN_F24R1_FB29_Msk (0x1U << CAN_F24R1_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F24R1_FB29 CAN_F24R1_FB29_Msk /*!< Filter bit 29 */
+#define CAN_F24R1_FB30_Pos (30U)
+#define CAN_F24R1_FB30_Msk (0x1U << CAN_F24R1_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F24R1_FB30 CAN_F24R1_FB30_Msk /*!< Filter bit 30 */
+#define CAN_F24R1_FB31_Pos (31U)
+#define CAN_F24R1_FB31_Msk (0x1U << CAN_F24R1_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F24R1_FB31 CAN_F24R1_FB31_Msk /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F25R1 register ******************/
+#define CAN_F25R1_FB0_Pos (0U)
+#define CAN_F25R1_FB0_Msk (0x1U << CAN_F25R1_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F25R1_FB0 CAN_F25R1_FB0_Msk /*!< Filter bit 0 */
+#define CAN_F25R1_FB1_Pos (1U)
+#define CAN_F25R1_FB1_Msk (0x1U << CAN_F25R1_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F25R1_FB1 CAN_F25R1_FB1_Msk /*!< Filter bit 1 */
+#define CAN_F25R1_FB2_Pos (2U)
+#define CAN_F25R1_FB2_Msk (0x1U << CAN_F25R1_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F25R1_FB2 CAN_F25R1_FB2_Msk /*!< Filter bit 2 */
+#define CAN_F25R1_FB3_Pos (3U)
+#define CAN_F25R1_FB3_Msk (0x1U << CAN_F25R1_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F25R1_FB3 CAN_F25R1_FB3_Msk /*!< Filter bit 3 */
+#define CAN_F25R1_FB4_Pos (4U)
+#define CAN_F25R1_FB4_Msk (0x1U << CAN_F25R1_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F25R1_FB4 CAN_F25R1_FB4_Msk /*!< Filter bit 4 */
+#define CAN_F25R1_FB5_Pos (5U)
+#define CAN_F25R1_FB5_Msk (0x1U << CAN_F25R1_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F25R1_FB5 CAN_F25R1_FB5_Msk /*!< Filter bit 5 */
+#define CAN_F25R1_FB6_Pos (6U)
+#define CAN_F25R1_FB6_Msk (0x1U << CAN_F25R1_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F25R1_FB6 CAN_F25R1_FB6_Msk /*!< Filter bit 6 */
+#define CAN_F25R1_FB7_Pos (7U)
+#define CAN_F25R1_FB7_Msk (0x1U << CAN_F25R1_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F25R1_FB7 CAN_F25R1_FB7_Msk /*!< Filter bit 7 */
+#define CAN_F25R1_FB8_Pos (8U)
+#define CAN_F25R1_FB8_Msk (0x1U << CAN_F25R1_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F25R1_FB8 CAN_F25R1_FB8_Msk /*!< Filter bit 8 */
+#define CAN_F25R1_FB9_Pos (9U)
+#define CAN_F25R1_FB9_Msk (0x1U << CAN_F25R1_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F25R1_FB9 CAN_F25R1_FB9_Msk /*!< Filter bit 9 */
+#define CAN_F25R1_FB10_Pos (10U)
+#define CAN_F25R1_FB10_Msk (0x1U << CAN_F25R1_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F25R1_FB10 CAN_F25R1_FB10_Msk /*!< Filter bit 10 */
+#define CAN_F25R1_FB11_Pos (11U)
+#define CAN_F25R1_FB11_Msk (0x1U << CAN_F25R1_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F25R1_FB11 CAN_F25R1_FB11_Msk /*!< Filter bit 11 */
+#define CAN_F25R1_FB12_Pos (12U)
+#define CAN_F25R1_FB12_Msk (0x1U << CAN_F25R1_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F25R1_FB12 CAN_F25R1_FB12_Msk /*!< Filter bit 12 */
+#define CAN_F25R1_FB13_Pos (13U)
+#define CAN_F25R1_FB13_Msk (0x1U << CAN_F25R1_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F25R1_FB13 CAN_F25R1_FB13_Msk /*!< Filter bit 13 */
+#define CAN_F25R1_FB14_Pos (14U)
+#define CAN_F25R1_FB14_Msk (0x1U << CAN_F25R1_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F25R1_FB14 CAN_F25R1_FB14_Msk /*!< Filter bit 14 */
+#define CAN_F25R1_FB15_Pos (15U)
+#define CAN_F25R1_FB15_Msk (0x1U << CAN_F25R1_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F25R1_FB15 CAN_F25R1_FB15_Msk /*!< Filter bit 15 */
+#define CAN_F25R1_FB16_Pos (16U)
+#define CAN_F25R1_FB16_Msk (0x1U << CAN_F25R1_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F25R1_FB16 CAN_F25R1_FB16_Msk /*!< Filter bit 16 */
+#define CAN_F25R1_FB17_Pos (17U)
+#define CAN_F25R1_FB17_Msk (0x1U << CAN_F25R1_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F25R1_FB17 CAN_F25R1_FB17_Msk /*!< Filter bit 17 */
+#define CAN_F25R1_FB18_Pos (18U)
+#define CAN_F25R1_FB18_Msk (0x1U << CAN_F25R1_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F25R1_FB18 CAN_F25R1_FB18_Msk /*!< Filter bit 18 */
+#define CAN_F25R1_FB19_Pos (19U)
+#define CAN_F25R1_FB19_Msk (0x1U << CAN_F25R1_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F25R1_FB19 CAN_F25R1_FB19_Msk /*!< Filter bit 19 */
+#define CAN_F25R1_FB20_Pos (20U)
+#define CAN_F25R1_FB20_Msk (0x1U << CAN_F25R1_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F25R1_FB20 CAN_F25R1_FB20_Msk /*!< Filter bit 20 */
+#define CAN_F25R1_FB21_Pos (21U)
+#define CAN_F25R1_FB21_Msk (0x1U << CAN_F25R1_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F25R1_FB21 CAN_F25R1_FB21_Msk /*!< Filter bit 21 */
+#define CAN_F25R1_FB22_Pos (22U)
+#define CAN_F25R1_FB22_Msk (0x1U << CAN_F25R1_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F25R1_FB22 CAN_F25R1_FB22_Msk /*!< Filter bit 22 */
+#define CAN_F25R1_FB23_Pos (23U)
+#define CAN_F25R1_FB23_Msk (0x1U << CAN_F25R1_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F25R1_FB23 CAN_F25R1_FB23_Msk /*!< Filter bit 23 */
+#define CAN_F25R1_FB24_Pos (24U)
+#define CAN_F25R1_FB24_Msk (0x1U << CAN_F25R1_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F25R1_FB24 CAN_F25R1_FB24_Msk /*!< Filter bit 24 */
+#define CAN_F25R1_FB25_Pos (25U)
+#define CAN_F25R1_FB25_Msk (0x1U << CAN_F25R1_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F25R1_FB25 CAN_F25R1_FB25_Msk /*!< Filter bit 25 */
+#define CAN_F25R1_FB26_Pos (26U)
+#define CAN_F25R1_FB26_Msk (0x1U << CAN_F25R1_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F25R1_FB26 CAN_F25R1_FB26_Msk /*!< Filter bit 26 */
+#define CAN_F25R1_FB27_Pos (27U)
+#define CAN_F25R1_FB27_Msk (0x1U << CAN_F25R1_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F25R1_FB27 CAN_F25R1_FB27_Msk /*!< Filter bit 27 */
+#define CAN_F25R1_FB28_Pos (28U)
+#define CAN_F25R1_FB28_Msk (0x1U << CAN_F25R1_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F25R1_FB28 CAN_F25R1_FB28_Msk /*!< Filter bit 28 */
+#define CAN_F25R1_FB29_Pos (29U)
+#define CAN_F25R1_FB29_Msk (0x1U << CAN_F25R1_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F25R1_FB29 CAN_F25R1_FB29_Msk /*!< Filter bit 29 */
+#define CAN_F25R1_FB30_Pos (30U)
+#define CAN_F25R1_FB30_Msk (0x1U << CAN_F25R1_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F25R1_FB30 CAN_F25R1_FB30_Msk /*!< Filter bit 30 */
+#define CAN_F25R1_FB31_Pos (31U)
+#define CAN_F25R1_FB31_Msk (0x1U << CAN_F25R1_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F25R1_FB31 CAN_F25R1_FB31_Msk /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F26R1 register ******************/
+#define CAN_F26R1_FB0_Pos (0U)
+#define CAN_F26R1_FB0_Msk (0x1U << CAN_F26R1_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F26R1_FB0 CAN_F26R1_FB0_Msk /*!< Filter bit 0 */
+#define CAN_F26R1_FB1_Pos (1U)
+#define CAN_F26R1_FB1_Msk (0x1U << CAN_F26R1_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F26R1_FB1 CAN_F26R1_FB1_Msk /*!< Filter bit 1 */
+#define CAN_F26R1_FB2_Pos (2U)
+#define CAN_F26R1_FB2_Msk (0x1U << CAN_F26R1_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F26R1_FB2 CAN_F26R1_FB2_Msk /*!< Filter bit 2 */
+#define CAN_F26R1_FB3_Pos (3U)
+#define CAN_F26R1_FB3_Msk (0x1U << CAN_F26R1_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F26R1_FB3 CAN_F26R1_FB3_Msk /*!< Filter bit 3 */
+#define CAN_F26R1_FB4_Pos (4U)
+#define CAN_F26R1_FB4_Msk (0x1U << CAN_F26R1_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F26R1_FB4 CAN_F26R1_FB4_Msk /*!< Filter bit 4 */
+#define CAN_F26R1_FB5_Pos (5U)
+#define CAN_F26R1_FB5_Msk (0x1U << CAN_F26R1_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F26R1_FB5 CAN_F26R1_FB5_Msk /*!< Filter bit 5 */
+#define CAN_F26R1_FB6_Pos (6U)
+#define CAN_F26R1_FB6_Msk (0x1U << CAN_F26R1_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F26R1_FB6 CAN_F26R1_FB6_Msk /*!< Filter bit 6 */
+#define CAN_F26R1_FB7_Pos (7U)
+#define CAN_F26R1_FB7_Msk (0x1U << CAN_F26R1_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F26R1_FB7 CAN_F26R1_FB7_Msk /*!< Filter bit 7 */
+#define CAN_F26R1_FB8_Pos (8U)
+#define CAN_F26R1_FB8_Msk (0x1U << CAN_F26R1_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F26R1_FB8 CAN_F26R1_FB8_Msk /*!< Filter bit 8 */
+#define CAN_F26R1_FB9_Pos (9U)
+#define CAN_F26R1_FB9_Msk (0x1U << CAN_F26R1_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F26R1_FB9 CAN_F26R1_FB9_Msk /*!< Filter bit 9 */
+#define CAN_F26R1_FB10_Pos (10U)
+#define CAN_F26R1_FB10_Msk (0x1U << CAN_F26R1_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F26R1_FB10 CAN_F26R1_FB10_Msk /*!< Filter bit 10 */
+#define CAN_F26R1_FB11_Pos (11U)
+#define CAN_F26R1_FB11_Msk (0x1U << CAN_F26R1_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F26R1_FB11 CAN_F26R1_FB11_Msk /*!< Filter bit 11 */
+#define CAN_F26R1_FB12_Pos (12U)
+#define CAN_F26R1_FB12_Msk (0x1U << CAN_F26R1_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F26R1_FB12 CAN_F26R1_FB12_Msk /*!< Filter bit 12 */
+#define CAN_F26R1_FB13_Pos (13U)
+#define CAN_F26R1_FB13_Msk (0x1U << CAN_F26R1_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F26R1_FB13 CAN_F26R1_FB13_Msk /*!< Filter bit 13 */
+#define CAN_F26R1_FB14_Pos (14U)
+#define CAN_F26R1_FB14_Msk (0x1U << CAN_F26R1_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F26R1_FB14 CAN_F26R1_FB14_Msk /*!< Filter bit 14 */
+#define CAN_F26R1_FB15_Pos (15U)
+#define CAN_F26R1_FB15_Msk (0x1U << CAN_F26R1_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F26R1_FB15 CAN_F26R1_FB15_Msk /*!< Filter bit 15 */
+#define CAN_F26R1_FB16_Pos (16U)
+#define CAN_F26R1_FB16_Msk (0x1U << CAN_F26R1_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F26R1_FB16 CAN_F26R1_FB16_Msk /*!< Filter bit 16 */
+#define CAN_F26R1_FB17_Pos (17U)
+#define CAN_F26R1_FB17_Msk (0x1U << CAN_F26R1_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F26R1_FB17 CAN_F26R1_FB17_Msk /*!< Filter bit 17 */
+#define CAN_F26R1_FB18_Pos (18U)
+#define CAN_F26R1_FB18_Msk (0x1U << CAN_F26R1_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F26R1_FB18 CAN_F26R1_FB18_Msk /*!< Filter bit 18 */
+#define CAN_F26R1_FB19_Pos (19U)
+#define CAN_F26R1_FB19_Msk (0x1U << CAN_F26R1_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F26R1_FB19 CAN_F26R1_FB19_Msk /*!< Filter bit 19 */
+#define CAN_F26R1_FB20_Pos (20U)
+#define CAN_F26R1_FB20_Msk (0x1U << CAN_F26R1_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F26R1_FB20 CAN_F26R1_FB20_Msk /*!< Filter bit 20 */
+#define CAN_F26R1_FB21_Pos (21U)
+#define CAN_F26R1_FB21_Msk (0x1U << CAN_F26R1_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F26R1_FB21 CAN_F26R1_FB21_Msk /*!< Filter bit 21 */
+#define CAN_F26R1_FB22_Pos (22U)
+#define CAN_F26R1_FB22_Msk (0x1U << CAN_F26R1_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F26R1_FB22 CAN_F26R1_FB22_Msk /*!< Filter bit 22 */
+#define CAN_F26R1_FB23_Pos (23U)
+#define CAN_F26R1_FB23_Msk (0x1U << CAN_F26R1_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F26R1_FB23 CAN_F26R1_FB23_Msk /*!< Filter bit 23 */
+#define CAN_F26R1_FB24_Pos (24U)
+#define CAN_F26R1_FB24_Msk (0x1U << CAN_F26R1_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F26R1_FB24 CAN_F26R1_FB24_Msk /*!< Filter bit 24 */
+#define CAN_F26R1_FB25_Pos (25U)
+#define CAN_F26R1_FB25_Msk (0x1U << CAN_F26R1_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F26R1_FB25 CAN_F26R1_FB25_Msk /*!< Filter bit 25 */
+#define CAN_F26R1_FB26_Pos (26U)
+#define CAN_F26R1_FB26_Msk (0x1U << CAN_F26R1_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F26R1_FB26 CAN_F26R1_FB26_Msk /*!< Filter bit 26 */
+#define CAN_F26R1_FB27_Pos (27U)
+#define CAN_F26R1_FB27_Msk (0x1U << CAN_F26R1_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F26R1_FB27 CAN_F26R1_FB27_Msk /*!< Filter bit 27 */
+#define CAN_F26R1_FB28_Pos (28U)
+#define CAN_F26R1_FB28_Msk (0x1U << CAN_F26R1_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F26R1_FB28 CAN_F26R1_FB28_Msk /*!< Filter bit 28 */
+#define CAN_F26R1_FB29_Pos (29U)
+#define CAN_F26R1_FB29_Msk (0x1U << CAN_F26R1_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F26R1_FB29 CAN_F26R1_FB29_Msk /*!< Filter bit 29 */
+#define CAN_F26R1_FB30_Pos (30U)
+#define CAN_F26R1_FB30_Msk (0x1U << CAN_F26R1_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F26R1_FB30 CAN_F26R1_FB30_Msk /*!< Filter bit 30 */
+#define CAN_F26R1_FB31_Pos (31U)
+#define CAN_F26R1_FB31_Msk (0x1U << CAN_F26R1_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F26R1_FB31 CAN_F26R1_FB31_Msk /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F27R1 register ******************/
+#define CAN_F27R1_FB0_Pos (0U)
+#define CAN_F27R1_FB0_Msk (0x1U << CAN_F27R1_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F27R1_FB0 CAN_F27R1_FB0_Msk /*!< Filter bit 0 */
+#define CAN_F27R1_FB1_Pos (1U)
+#define CAN_F27R1_FB1_Msk (0x1U << CAN_F27R1_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F27R1_FB1 CAN_F27R1_FB1_Msk /*!< Filter bit 1 */
+#define CAN_F27R1_FB2_Pos (2U)
+#define CAN_F27R1_FB2_Msk (0x1U << CAN_F27R1_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F27R1_FB2 CAN_F27R1_FB2_Msk /*!< Filter bit 2 */
+#define CAN_F27R1_FB3_Pos (3U)
+#define CAN_F27R1_FB3_Msk (0x1U << CAN_F27R1_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F27R1_FB3 CAN_F27R1_FB3_Msk /*!< Filter bit 3 */
+#define CAN_F27R1_FB4_Pos (4U)
+#define CAN_F27R1_FB4_Msk (0x1U << CAN_F27R1_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F27R1_FB4 CAN_F27R1_FB4_Msk /*!< Filter bit 4 */
+#define CAN_F27R1_FB5_Pos (5U)
+#define CAN_F27R1_FB5_Msk (0x1U << CAN_F27R1_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F27R1_FB5 CAN_F27R1_FB5_Msk /*!< Filter bit 5 */
+#define CAN_F27R1_FB6_Pos (6U)
+#define CAN_F27R1_FB6_Msk (0x1U << CAN_F27R1_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F27R1_FB6 CAN_F27R1_FB6_Msk /*!< Filter bit 6 */
+#define CAN_F27R1_FB7_Pos (7U)
+#define CAN_F27R1_FB7_Msk (0x1U << CAN_F27R1_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F27R1_FB7 CAN_F27R1_FB7_Msk /*!< Filter bit 7 */
+#define CAN_F27R1_FB8_Pos (8U)
+#define CAN_F27R1_FB8_Msk (0x1U << CAN_F27R1_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F27R1_FB8 CAN_F27R1_FB8_Msk /*!< Filter bit 8 */
+#define CAN_F27R1_FB9_Pos (9U)
+#define CAN_F27R1_FB9_Msk (0x1U << CAN_F27R1_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F27R1_FB9 CAN_F27R1_FB9_Msk /*!< Filter bit 9 */
+#define CAN_F27R1_FB10_Pos (10U)
+#define CAN_F27R1_FB10_Msk (0x1U << CAN_F27R1_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F27R1_FB10 CAN_F27R1_FB10_Msk /*!< Filter bit 10 */
+#define CAN_F27R1_FB11_Pos (11U)
+#define CAN_F27R1_FB11_Msk (0x1U << CAN_F27R1_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F27R1_FB11 CAN_F27R1_FB11_Msk /*!< Filter bit 11 */
+#define CAN_F27R1_FB12_Pos (12U)
+#define CAN_F27R1_FB12_Msk (0x1U << CAN_F27R1_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F27R1_FB12 CAN_F27R1_FB12_Msk /*!< Filter bit 12 */
+#define CAN_F27R1_FB13_Pos (13U)
+#define CAN_F27R1_FB13_Msk (0x1U << CAN_F27R1_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F27R1_FB13 CAN_F27R1_FB13_Msk /*!< Filter bit 13 */
+#define CAN_F27R1_FB14_Pos (14U)
+#define CAN_F27R1_FB14_Msk (0x1U << CAN_F27R1_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F27R1_FB14 CAN_F27R1_FB14_Msk /*!< Filter bit 14 */
+#define CAN_F27R1_FB15_Pos (15U)
+#define CAN_F27R1_FB15_Msk (0x1U << CAN_F27R1_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F27R1_FB15 CAN_F27R1_FB15_Msk /*!< Filter bit 15 */
+#define CAN_F27R1_FB16_Pos (16U)
+#define CAN_F27R1_FB16_Msk (0x1U << CAN_F27R1_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F27R1_FB16 CAN_F27R1_FB16_Msk /*!< Filter bit 16 */
+#define CAN_F27R1_FB17_Pos (17U)
+#define CAN_F27R1_FB17_Msk (0x1U << CAN_F27R1_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F27R1_FB17 CAN_F27R1_FB17_Msk /*!< Filter bit 17 */
+#define CAN_F27R1_FB18_Pos (18U)
+#define CAN_F27R1_FB18_Msk (0x1U << CAN_F27R1_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F27R1_FB18 CAN_F27R1_FB18_Msk /*!< Filter bit 18 */
+#define CAN_F27R1_FB19_Pos (19U)
+#define CAN_F27R1_FB19_Msk (0x1U << CAN_F27R1_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F27R1_FB19 CAN_F27R1_FB19_Msk /*!< Filter bit 19 */
+#define CAN_F27R1_FB20_Pos (20U)
+#define CAN_F27R1_FB20_Msk (0x1U << CAN_F27R1_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F27R1_FB20 CAN_F27R1_FB20_Msk /*!< Filter bit 20 */
+#define CAN_F27R1_FB21_Pos (21U)
+#define CAN_F27R1_FB21_Msk (0x1U << CAN_F27R1_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F27R1_FB21 CAN_F27R1_FB21_Msk /*!< Filter bit 21 */
+#define CAN_F27R1_FB22_Pos (22U)
+#define CAN_F27R1_FB22_Msk (0x1U << CAN_F27R1_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F27R1_FB22 CAN_F27R1_FB22_Msk /*!< Filter bit 22 */
+#define CAN_F27R1_FB23_Pos (23U)
+#define CAN_F27R1_FB23_Msk (0x1U << CAN_F27R1_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F27R1_FB23 CAN_F27R1_FB23_Msk /*!< Filter bit 23 */
+#define CAN_F27R1_FB24_Pos (24U)
+#define CAN_F27R1_FB24_Msk (0x1U << CAN_F27R1_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F27R1_FB24 CAN_F27R1_FB24_Msk /*!< Filter bit 24 */
+#define CAN_F27R1_FB25_Pos (25U)
+#define CAN_F27R1_FB25_Msk (0x1U << CAN_F27R1_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F27R1_FB25 CAN_F27R1_FB25_Msk /*!< Filter bit 25 */
+#define CAN_F27R1_FB26_Pos (26U)
+#define CAN_F27R1_FB26_Msk (0x1U << CAN_F27R1_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F27R1_FB26 CAN_F27R1_FB26_Msk /*!< Filter bit 26 */
+#define CAN_F27R1_FB27_Pos (27U)
+#define CAN_F27R1_FB27_Msk (0x1U << CAN_F27R1_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F27R1_FB27 CAN_F27R1_FB27_Msk /*!< Filter bit 27 */
+#define CAN_F27R1_FB28_Pos (28U)
+#define CAN_F27R1_FB28_Msk (0x1U << CAN_F27R1_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F27R1_FB28 CAN_F27R1_FB28_Msk /*!< Filter bit 28 */
+#define CAN_F27R1_FB29_Pos (29U)
+#define CAN_F27R1_FB29_Msk (0x1U << CAN_F27R1_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F27R1_FB29 CAN_F27R1_FB29_Msk /*!< Filter bit 29 */
+#define CAN_F27R1_FB30_Pos (30U)
+#define CAN_F27R1_FB30_Msk (0x1U << CAN_F27R1_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F27R1_FB30 CAN_F27R1_FB30_Msk /*!< Filter bit 30 */
+#define CAN_F27R1_FB31_Pos (31U)
+#define CAN_F27R1_FB31_Msk (0x1U << CAN_F27R1_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F27R1_FB31 CAN_F27R1_FB31_Msk /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F0R2 register *******************/
+#define CAN_F0R2_FB0_Pos (0U)
+#define CAN_F0R2_FB0_Msk (0x1U << CAN_F0R2_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F0R2_FB0 CAN_F0R2_FB0_Msk /*!< Filter bit 0 */
+#define CAN_F0R2_FB1_Pos (1U)
+#define CAN_F0R2_FB1_Msk (0x1U << CAN_F0R2_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F0R2_FB1 CAN_F0R2_FB1_Msk /*!< Filter bit 1 */
+#define CAN_F0R2_FB2_Pos (2U)
+#define CAN_F0R2_FB2_Msk (0x1U << CAN_F0R2_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F0R2_FB2 CAN_F0R2_FB2_Msk /*!< Filter bit 2 */
+#define CAN_F0R2_FB3_Pos (3U)
+#define CAN_F0R2_FB3_Msk (0x1U << CAN_F0R2_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F0R2_FB3 CAN_F0R2_FB3_Msk /*!< Filter bit 3 */
+#define CAN_F0R2_FB4_Pos (4U)
+#define CAN_F0R2_FB4_Msk (0x1U << CAN_F0R2_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F0R2_FB4 CAN_F0R2_FB4_Msk /*!< Filter bit 4 */
+#define CAN_F0R2_FB5_Pos (5U)
+#define CAN_F0R2_FB5_Msk (0x1U << CAN_F0R2_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F0R2_FB5 CAN_F0R2_FB5_Msk /*!< Filter bit 5 */
+#define CAN_F0R2_FB6_Pos (6U)
+#define CAN_F0R2_FB6_Msk (0x1U << CAN_F0R2_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F0R2_FB6 CAN_F0R2_FB6_Msk /*!< Filter bit 6 */
+#define CAN_F0R2_FB7_Pos (7U)
+#define CAN_F0R2_FB7_Msk (0x1U << CAN_F0R2_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F0R2_FB7 CAN_F0R2_FB7_Msk /*!< Filter bit 7 */
+#define CAN_F0R2_FB8_Pos (8U)
+#define CAN_F0R2_FB8_Msk (0x1U << CAN_F0R2_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F0R2_FB8 CAN_F0R2_FB8_Msk /*!< Filter bit 8 */
+#define CAN_F0R2_FB9_Pos (9U)
+#define CAN_F0R2_FB9_Msk (0x1U << CAN_F0R2_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F0R2_FB9 CAN_F0R2_FB9_Msk /*!< Filter bit 9 */
+#define CAN_F0R2_FB10_Pos (10U)
+#define CAN_F0R2_FB10_Msk (0x1U << CAN_F0R2_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F0R2_FB10 CAN_F0R2_FB10_Msk /*!< Filter bit 10 */
+#define CAN_F0R2_FB11_Pos (11U)
+#define CAN_F0R2_FB11_Msk (0x1U << CAN_F0R2_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F0R2_FB11 CAN_F0R2_FB11_Msk /*!< Filter bit 11 */
+#define CAN_F0R2_FB12_Pos (12U)
+#define CAN_F0R2_FB12_Msk (0x1U << CAN_F0R2_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F0R2_FB12 CAN_F0R2_FB12_Msk /*!< Filter bit 12 */
+#define CAN_F0R2_FB13_Pos (13U)
+#define CAN_F0R2_FB13_Msk (0x1U << CAN_F0R2_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F0R2_FB13 CAN_F0R2_FB13_Msk /*!< Filter bit 13 */
+#define CAN_F0R2_FB14_Pos (14U)
+#define CAN_F0R2_FB14_Msk (0x1U << CAN_F0R2_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F0R2_FB14 CAN_F0R2_FB14_Msk /*!< Filter bit 14 */
+#define CAN_F0R2_FB15_Pos (15U)
+#define CAN_F0R2_FB15_Msk (0x1U << CAN_F0R2_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F0R2_FB15 CAN_F0R2_FB15_Msk /*!< Filter bit 15 */
+#define CAN_F0R2_FB16_Pos (16U)
+#define CAN_F0R2_FB16_Msk (0x1U << CAN_F0R2_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F0R2_FB16 CAN_F0R2_FB16_Msk /*!< Filter bit 16 */
+#define CAN_F0R2_FB17_Pos (17U)
+#define CAN_F0R2_FB17_Msk (0x1U << CAN_F0R2_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F0R2_FB17 CAN_F0R2_FB17_Msk /*!< Filter bit 17 */
+#define CAN_F0R2_FB18_Pos (18U)
+#define CAN_F0R2_FB18_Msk (0x1U << CAN_F0R2_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F0R2_FB18 CAN_F0R2_FB18_Msk /*!< Filter bit 18 */
+#define CAN_F0R2_FB19_Pos (19U)
+#define CAN_F0R2_FB19_Msk (0x1U << CAN_F0R2_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F0R2_FB19 CAN_F0R2_FB19_Msk /*!< Filter bit 19 */
+#define CAN_F0R2_FB20_Pos (20U)
+#define CAN_F0R2_FB20_Msk (0x1U << CAN_F0R2_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F0R2_FB20 CAN_F0R2_FB20_Msk /*!< Filter bit 20 */
+#define CAN_F0R2_FB21_Pos (21U)
+#define CAN_F0R2_FB21_Msk (0x1U << CAN_F0R2_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F0R2_FB21 CAN_F0R2_FB21_Msk /*!< Filter bit 21 */
+#define CAN_F0R2_FB22_Pos (22U)
+#define CAN_F0R2_FB22_Msk (0x1U << CAN_F0R2_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F0R2_FB22 CAN_F0R2_FB22_Msk /*!< Filter bit 22 */
+#define CAN_F0R2_FB23_Pos (23U)
+#define CAN_F0R2_FB23_Msk (0x1U << CAN_F0R2_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F0R2_FB23 CAN_F0R2_FB23_Msk /*!< Filter bit 23 */
+#define CAN_F0R2_FB24_Pos (24U)
+#define CAN_F0R2_FB24_Msk (0x1U << CAN_F0R2_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F0R2_FB24 CAN_F0R2_FB24_Msk /*!< Filter bit 24 */
+#define CAN_F0R2_FB25_Pos (25U)
+#define CAN_F0R2_FB25_Msk (0x1U << CAN_F0R2_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F0R2_FB25 CAN_F0R2_FB25_Msk /*!< Filter bit 25 */
+#define CAN_F0R2_FB26_Pos (26U)
+#define CAN_F0R2_FB26_Msk (0x1U << CAN_F0R2_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F0R2_FB26 CAN_F0R2_FB26_Msk /*!< Filter bit 26 */
+#define CAN_F0R2_FB27_Pos (27U)
+#define CAN_F0R2_FB27_Msk (0x1U << CAN_F0R2_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F0R2_FB27 CAN_F0R2_FB27_Msk /*!< Filter bit 27 */
+#define CAN_F0R2_FB28_Pos (28U)
+#define CAN_F0R2_FB28_Msk (0x1U << CAN_F0R2_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F0R2_FB28 CAN_F0R2_FB28_Msk /*!< Filter bit 28 */
+#define CAN_F0R2_FB29_Pos (29U)
+#define CAN_F0R2_FB29_Msk (0x1U << CAN_F0R2_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F0R2_FB29 CAN_F0R2_FB29_Msk /*!< Filter bit 29 */
+#define CAN_F0R2_FB30_Pos (30U)
+#define CAN_F0R2_FB30_Msk (0x1U << CAN_F0R2_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F0R2_FB30 CAN_F0R2_FB30_Msk /*!< Filter bit 30 */
+#define CAN_F0R2_FB31_Pos (31U)
+#define CAN_F0R2_FB31_Msk (0x1U << CAN_F0R2_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F0R2_FB31 CAN_F0R2_FB31_Msk /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F1R2 register *******************/
+#define CAN_F1R2_FB0_Pos (0U)
+#define CAN_F1R2_FB0_Msk (0x1U << CAN_F1R2_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F1R2_FB0 CAN_F1R2_FB0_Msk /*!< Filter bit 0 */
+#define CAN_F1R2_FB1_Pos (1U)
+#define CAN_F1R2_FB1_Msk (0x1U << CAN_F1R2_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F1R2_FB1 CAN_F1R2_FB1_Msk /*!< Filter bit 1 */
+#define CAN_F1R2_FB2_Pos (2U)
+#define CAN_F1R2_FB2_Msk (0x1U << CAN_F1R2_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F1R2_FB2 CAN_F1R2_FB2_Msk /*!< Filter bit 2 */
+#define CAN_F1R2_FB3_Pos (3U)
+#define CAN_F1R2_FB3_Msk (0x1U << CAN_F1R2_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F1R2_FB3 CAN_F1R2_FB3_Msk /*!< Filter bit 3 */
+#define CAN_F1R2_FB4_Pos (4U)
+#define CAN_F1R2_FB4_Msk (0x1U << CAN_F1R2_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F1R2_FB4 CAN_F1R2_FB4_Msk /*!< Filter bit 4 */
+#define CAN_F1R2_FB5_Pos (5U)
+#define CAN_F1R2_FB5_Msk (0x1U << CAN_F1R2_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F1R2_FB5 CAN_F1R2_FB5_Msk /*!< Filter bit 5 */
+#define CAN_F1R2_FB6_Pos (6U)
+#define CAN_F1R2_FB6_Msk (0x1U << CAN_F1R2_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F1R2_FB6 CAN_F1R2_FB6_Msk /*!< Filter bit 6 */
+#define CAN_F1R2_FB7_Pos (7U)
+#define CAN_F1R2_FB7_Msk (0x1U << CAN_F1R2_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F1R2_FB7 CAN_F1R2_FB7_Msk /*!< Filter bit 7 */
+#define CAN_F1R2_FB8_Pos (8U)
+#define CAN_F1R2_FB8_Msk (0x1U << CAN_F1R2_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F1R2_FB8 CAN_F1R2_FB8_Msk /*!< Filter bit 8 */
+#define CAN_F1R2_FB9_Pos (9U)
+#define CAN_F1R2_FB9_Msk (0x1U << CAN_F1R2_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F1R2_FB9 CAN_F1R2_FB9_Msk /*!< Filter bit 9 */
+#define CAN_F1R2_FB10_Pos (10U)
+#define CAN_F1R2_FB10_Msk (0x1U << CAN_F1R2_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F1R2_FB10 CAN_F1R2_FB10_Msk /*!< Filter bit 10 */
+#define CAN_F1R2_FB11_Pos (11U)
+#define CAN_F1R2_FB11_Msk (0x1U << CAN_F1R2_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F1R2_FB11 CAN_F1R2_FB11_Msk /*!< Filter bit 11 */
+#define CAN_F1R2_FB12_Pos (12U)
+#define CAN_F1R2_FB12_Msk (0x1U << CAN_F1R2_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F1R2_FB12 CAN_F1R2_FB12_Msk /*!< Filter bit 12 */
+#define CAN_F1R2_FB13_Pos (13U)
+#define CAN_F1R2_FB13_Msk (0x1U << CAN_F1R2_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F1R2_FB13 CAN_F1R2_FB13_Msk /*!< Filter bit 13 */
+#define CAN_F1R2_FB14_Pos (14U)
+#define CAN_F1R2_FB14_Msk (0x1U << CAN_F1R2_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F1R2_FB14 CAN_F1R2_FB14_Msk /*!< Filter bit 14 */
+#define CAN_F1R2_FB15_Pos (15U)
+#define CAN_F1R2_FB15_Msk (0x1U << CAN_F1R2_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F1R2_FB15 CAN_F1R2_FB15_Msk /*!< Filter bit 15 */
+#define CAN_F1R2_FB16_Pos (16U)
+#define CAN_F1R2_FB16_Msk (0x1U << CAN_F1R2_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F1R2_FB16 CAN_F1R2_FB16_Msk /*!< Filter bit 16 */
+#define CAN_F1R2_FB17_Pos (17U)
+#define CAN_F1R2_FB17_Msk (0x1U << CAN_F1R2_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F1R2_FB17 CAN_F1R2_FB17_Msk /*!< Filter bit 17 */
+#define CAN_F1R2_FB18_Pos (18U)
+#define CAN_F1R2_FB18_Msk (0x1U << CAN_F1R2_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F1R2_FB18 CAN_F1R2_FB18_Msk /*!< Filter bit 18 */
+#define CAN_F1R2_FB19_Pos (19U)
+#define CAN_F1R2_FB19_Msk (0x1U << CAN_F1R2_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F1R2_FB19 CAN_F1R2_FB19_Msk /*!< Filter bit 19 */
+#define CAN_F1R2_FB20_Pos (20U)
+#define CAN_F1R2_FB20_Msk (0x1U << CAN_F1R2_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F1R2_FB20 CAN_F1R2_FB20_Msk /*!< Filter bit 20 */
+#define CAN_F1R2_FB21_Pos (21U)
+#define CAN_F1R2_FB21_Msk (0x1U << CAN_F1R2_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F1R2_FB21 CAN_F1R2_FB21_Msk /*!< Filter bit 21 */
+#define CAN_F1R2_FB22_Pos (22U)
+#define CAN_F1R2_FB22_Msk (0x1U << CAN_F1R2_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F1R2_FB22 CAN_F1R2_FB22_Msk /*!< Filter bit 22 */
+#define CAN_F1R2_FB23_Pos (23U)
+#define CAN_F1R2_FB23_Msk (0x1U << CAN_F1R2_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F1R2_FB23 CAN_F1R2_FB23_Msk /*!< Filter bit 23 */
+#define CAN_F1R2_FB24_Pos (24U)
+#define CAN_F1R2_FB24_Msk (0x1U << CAN_F1R2_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F1R2_FB24 CAN_F1R2_FB24_Msk /*!< Filter bit 24 */
+#define CAN_F1R2_FB25_Pos (25U)
+#define CAN_F1R2_FB25_Msk (0x1U << CAN_F1R2_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F1R2_FB25 CAN_F1R2_FB25_Msk /*!< Filter bit 25 */
+#define CAN_F1R2_FB26_Pos (26U)
+#define CAN_F1R2_FB26_Msk (0x1U << CAN_F1R2_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F1R2_FB26 CAN_F1R2_FB26_Msk /*!< Filter bit 26 */
+#define CAN_F1R2_FB27_Pos (27U)
+#define CAN_F1R2_FB27_Msk (0x1U << CAN_F1R2_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F1R2_FB27 CAN_F1R2_FB27_Msk /*!< Filter bit 27 */
+#define CAN_F1R2_FB28_Pos (28U)
+#define CAN_F1R2_FB28_Msk (0x1U << CAN_F1R2_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F1R2_FB28 CAN_F1R2_FB28_Msk /*!< Filter bit 28 */
+#define CAN_F1R2_FB29_Pos (29U)
+#define CAN_F1R2_FB29_Msk (0x1U << CAN_F1R2_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F1R2_FB29 CAN_F1R2_FB29_Msk /*!< Filter bit 29 */
+#define CAN_F1R2_FB30_Pos (30U)
+#define CAN_F1R2_FB30_Msk (0x1U << CAN_F1R2_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F1R2_FB30 CAN_F1R2_FB30_Msk /*!< Filter bit 30 */
+#define CAN_F1R2_FB31_Pos (31U)
+#define CAN_F1R2_FB31_Msk (0x1U << CAN_F1R2_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F1R2_FB31 CAN_F1R2_FB31_Msk /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F2R2 register *******************/
+#define CAN_F2R2_FB0_Pos (0U)
+#define CAN_F2R2_FB0_Msk (0x1U << CAN_F2R2_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F2R2_FB0 CAN_F2R2_FB0_Msk /*!< Filter bit 0 */
+#define CAN_F2R2_FB1_Pos (1U)
+#define CAN_F2R2_FB1_Msk (0x1U << CAN_F2R2_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F2R2_FB1 CAN_F2R2_FB1_Msk /*!< Filter bit 1 */
+#define CAN_F2R2_FB2_Pos (2U)
+#define CAN_F2R2_FB2_Msk (0x1U << CAN_F2R2_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F2R2_FB2 CAN_F2R2_FB2_Msk /*!< Filter bit 2 */
+#define CAN_F2R2_FB3_Pos (3U)
+#define CAN_F2R2_FB3_Msk (0x1U << CAN_F2R2_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F2R2_FB3 CAN_F2R2_FB3_Msk /*!< Filter bit 3 */
+#define CAN_F2R2_FB4_Pos (4U)
+#define CAN_F2R2_FB4_Msk (0x1U << CAN_F2R2_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F2R2_FB4 CAN_F2R2_FB4_Msk /*!< Filter bit 4 */
+#define CAN_F2R2_FB5_Pos (5U)
+#define CAN_F2R2_FB5_Msk (0x1U << CAN_F2R2_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F2R2_FB5 CAN_F2R2_FB5_Msk /*!< Filter bit 5 */
+#define CAN_F2R2_FB6_Pos (6U)
+#define CAN_F2R2_FB6_Msk (0x1U << CAN_F2R2_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F2R2_FB6 CAN_F2R2_FB6_Msk /*!< Filter bit 6 */
+#define CAN_F2R2_FB7_Pos (7U)
+#define CAN_F2R2_FB7_Msk (0x1U << CAN_F2R2_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F2R2_FB7 CAN_F2R2_FB7_Msk /*!< Filter bit 7 */
+#define CAN_F2R2_FB8_Pos (8U)
+#define CAN_F2R2_FB8_Msk (0x1U << CAN_F2R2_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F2R2_FB8 CAN_F2R2_FB8_Msk /*!< Filter bit 8 */
+#define CAN_F2R2_FB9_Pos (9U)
+#define CAN_F2R2_FB9_Msk (0x1U << CAN_F2R2_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F2R2_FB9 CAN_F2R2_FB9_Msk /*!< Filter bit 9 */
+#define CAN_F2R2_FB10_Pos (10U)
+#define CAN_F2R2_FB10_Msk (0x1U << CAN_F2R2_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F2R2_FB10 CAN_F2R2_FB10_Msk /*!< Filter bit 10 */
+#define CAN_F2R2_FB11_Pos (11U)
+#define CAN_F2R2_FB11_Msk (0x1U << CAN_F2R2_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F2R2_FB11 CAN_F2R2_FB11_Msk /*!< Filter bit 11 */
+#define CAN_F2R2_FB12_Pos (12U)
+#define CAN_F2R2_FB12_Msk (0x1U << CAN_F2R2_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F2R2_FB12 CAN_F2R2_FB12_Msk /*!< Filter bit 12 */
+#define CAN_F2R2_FB13_Pos (13U)
+#define CAN_F2R2_FB13_Msk (0x1U << CAN_F2R2_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F2R2_FB13 CAN_F2R2_FB13_Msk /*!< Filter bit 13 */
+#define CAN_F2R2_FB14_Pos (14U)
+#define CAN_F2R2_FB14_Msk (0x1U << CAN_F2R2_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F2R2_FB14 CAN_F2R2_FB14_Msk /*!< Filter bit 14 */
+#define CAN_F2R2_FB15_Pos (15U)
+#define CAN_F2R2_FB15_Msk (0x1U << CAN_F2R2_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F2R2_FB15 CAN_F2R2_FB15_Msk /*!< Filter bit 15 */
+#define CAN_F2R2_FB16_Pos (16U)
+#define CAN_F2R2_FB16_Msk (0x1U << CAN_F2R2_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F2R2_FB16 CAN_F2R2_FB16_Msk /*!< Filter bit 16 */
+#define CAN_F2R2_FB17_Pos (17U)
+#define CAN_F2R2_FB17_Msk (0x1U << CAN_F2R2_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F2R2_FB17 CAN_F2R2_FB17_Msk /*!< Filter bit 17 */
+#define CAN_F2R2_FB18_Pos (18U)
+#define CAN_F2R2_FB18_Msk (0x1U << CAN_F2R2_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F2R2_FB18 CAN_F2R2_FB18_Msk /*!< Filter bit 18 */
+#define CAN_F2R2_FB19_Pos (19U)
+#define CAN_F2R2_FB19_Msk (0x1U << CAN_F2R2_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F2R2_FB19 CAN_F2R2_FB19_Msk /*!< Filter bit 19 */
+#define CAN_F2R2_FB20_Pos (20U)
+#define CAN_F2R2_FB20_Msk (0x1U << CAN_F2R2_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F2R2_FB20 CAN_F2R2_FB20_Msk /*!< Filter bit 20 */
+#define CAN_F2R2_FB21_Pos (21U)
+#define CAN_F2R2_FB21_Msk (0x1U << CAN_F2R2_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F2R2_FB21 CAN_F2R2_FB21_Msk /*!< Filter bit 21 */
+#define CAN_F2R2_FB22_Pos (22U)
+#define CAN_F2R2_FB22_Msk (0x1U << CAN_F2R2_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F2R2_FB22 CAN_F2R2_FB22_Msk /*!< Filter bit 22 */
+#define CAN_F2R2_FB23_Pos (23U)
+#define CAN_F2R2_FB23_Msk (0x1U << CAN_F2R2_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F2R2_FB23 CAN_F2R2_FB23_Msk /*!< Filter bit 23 */
+#define CAN_F2R2_FB24_Pos (24U)
+#define CAN_F2R2_FB24_Msk (0x1U << CAN_F2R2_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F2R2_FB24 CAN_F2R2_FB24_Msk /*!< Filter bit 24 */
+#define CAN_F2R2_FB25_Pos (25U)
+#define CAN_F2R2_FB25_Msk (0x1U << CAN_F2R2_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F2R2_FB25 CAN_F2R2_FB25_Msk /*!< Filter bit 25 */
+#define CAN_F2R2_FB26_Pos (26U)
+#define CAN_F2R2_FB26_Msk (0x1U << CAN_F2R2_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F2R2_FB26 CAN_F2R2_FB26_Msk /*!< Filter bit 26 */
+#define CAN_F2R2_FB27_Pos (27U)
+#define CAN_F2R2_FB27_Msk (0x1U << CAN_F2R2_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F2R2_FB27 CAN_F2R2_FB27_Msk /*!< Filter bit 27 */
+#define CAN_F2R2_FB28_Pos (28U)
+#define CAN_F2R2_FB28_Msk (0x1U << CAN_F2R2_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F2R2_FB28 CAN_F2R2_FB28_Msk /*!< Filter bit 28 */
+#define CAN_F2R2_FB29_Pos (29U)
+#define CAN_F2R2_FB29_Msk (0x1U << CAN_F2R2_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F2R2_FB29 CAN_F2R2_FB29_Msk /*!< Filter bit 29 */
+#define CAN_F2R2_FB30_Pos (30U)
+#define CAN_F2R2_FB30_Msk (0x1U << CAN_F2R2_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F2R2_FB30 CAN_F2R2_FB30_Msk /*!< Filter bit 30 */
+#define CAN_F2R2_FB31_Pos (31U)
+#define CAN_F2R2_FB31_Msk (0x1U << CAN_F2R2_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F2R2_FB31 CAN_F2R2_FB31_Msk /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F3R2 register *******************/
+#define CAN_F3R2_FB0_Pos (0U)
+#define CAN_F3R2_FB0_Msk (0x1U << CAN_F3R2_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F3R2_FB0 CAN_F3R2_FB0_Msk /*!< Filter bit 0 */
+#define CAN_F3R2_FB1_Pos (1U)
+#define CAN_F3R2_FB1_Msk (0x1U << CAN_F3R2_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F3R2_FB1 CAN_F3R2_FB1_Msk /*!< Filter bit 1 */
+#define CAN_F3R2_FB2_Pos (2U)
+#define CAN_F3R2_FB2_Msk (0x1U << CAN_F3R2_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F3R2_FB2 CAN_F3R2_FB2_Msk /*!< Filter bit 2 */
+#define CAN_F3R2_FB3_Pos (3U)
+#define CAN_F3R2_FB3_Msk (0x1U << CAN_F3R2_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F3R2_FB3 CAN_F3R2_FB3_Msk /*!< Filter bit 3 */
+#define CAN_F3R2_FB4_Pos (4U)
+#define CAN_F3R2_FB4_Msk (0x1U << CAN_F3R2_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F3R2_FB4 CAN_F3R2_FB4_Msk /*!< Filter bit 4 */
+#define CAN_F3R2_FB5_Pos (5U)
+#define CAN_F3R2_FB5_Msk (0x1U << CAN_F3R2_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F3R2_FB5 CAN_F3R2_FB5_Msk /*!< Filter bit 5 */
+#define CAN_F3R2_FB6_Pos (6U)
+#define CAN_F3R2_FB6_Msk (0x1U << CAN_F3R2_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F3R2_FB6 CAN_F3R2_FB6_Msk /*!< Filter bit 6 */
+#define CAN_F3R2_FB7_Pos (7U)
+#define CAN_F3R2_FB7_Msk (0x1U << CAN_F3R2_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F3R2_FB7 CAN_F3R2_FB7_Msk /*!< Filter bit 7 */
+#define CAN_F3R2_FB8_Pos (8U)
+#define CAN_F3R2_FB8_Msk (0x1U << CAN_F3R2_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F3R2_FB8 CAN_F3R2_FB8_Msk /*!< Filter bit 8 */
+#define CAN_F3R2_FB9_Pos (9U)
+#define CAN_F3R2_FB9_Msk (0x1U << CAN_F3R2_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F3R2_FB9 CAN_F3R2_FB9_Msk /*!< Filter bit 9 */
+#define CAN_F3R2_FB10_Pos (10U)
+#define CAN_F3R2_FB10_Msk (0x1U << CAN_F3R2_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F3R2_FB10 CAN_F3R2_FB10_Msk /*!< Filter bit 10 */
+#define CAN_F3R2_FB11_Pos (11U)
+#define CAN_F3R2_FB11_Msk (0x1U << CAN_F3R2_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F3R2_FB11 CAN_F3R2_FB11_Msk /*!< Filter bit 11 */
+#define CAN_F3R2_FB12_Pos (12U)
+#define CAN_F3R2_FB12_Msk (0x1U << CAN_F3R2_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F3R2_FB12 CAN_F3R2_FB12_Msk /*!< Filter bit 12 */
+#define CAN_F3R2_FB13_Pos (13U)
+#define CAN_F3R2_FB13_Msk (0x1U << CAN_F3R2_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F3R2_FB13 CAN_F3R2_FB13_Msk /*!< Filter bit 13 */
+#define CAN_F3R2_FB14_Pos (14U)
+#define CAN_F3R2_FB14_Msk (0x1U << CAN_F3R2_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F3R2_FB14 CAN_F3R2_FB14_Msk /*!< Filter bit 14 */
+#define CAN_F3R2_FB15_Pos (15U)
+#define CAN_F3R2_FB15_Msk (0x1U << CAN_F3R2_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F3R2_FB15 CAN_F3R2_FB15_Msk /*!< Filter bit 15 */
+#define CAN_F3R2_FB16_Pos (16U)
+#define CAN_F3R2_FB16_Msk (0x1U << CAN_F3R2_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F3R2_FB16 CAN_F3R2_FB16_Msk /*!< Filter bit 16 */
+#define CAN_F3R2_FB17_Pos (17U)
+#define CAN_F3R2_FB17_Msk (0x1U << CAN_F3R2_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F3R2_FB17 CAN_F3R2_FB17_Msk /*!< Filter bit 17 */
+#define CAN_F3R2_FB18_Pos (18U)
+#define CAN_F3R2_FB18_Msk (0x1U << CAN_F3R2_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F3R2_FB18 CAN_F3R2_FB18_Msk /*!< Filter bit 18 */
+#define CAN_F3R2_FB19_Pos (19U)
+#define CAN_F3R2_FB19_Msk (0x1U << CAN_F3R2_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F3R2_FB19 CAN_F3R2_FB19_Msk /*!< Filter bit 19 */
+#define CAN_F3R2_FB20_Pos (20U)
+#define CAN_F3R2_FB20_Msk (0x1U << CAN_F3R2_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F3R2_FB20 CAN_F3R2_FB20_Msk /*!< Filter bit 20 */
+#define CAN_F3R2_FB21_Pos (21U)
+#define CAN_F3R2_FB21_Msk (0x1U << CAN_F3R2_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F3R2_FB21 CAN_F3R2_FB21_Msk /*!< Filter bit 21 */
+#define CAN_F3R2_FB22_Pos (22U)
+#define CAN_F3R2_FB22_Msk (0x1U << CAN_F3R2_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F3R2_FB22 CAN_F3R2_FB22_Msk /*!< Filter bit 22 */
+#define CAN_F3R2_FB23_Pos (23U)
+#define CAN_F3R2_FB23_Msk (0x1U << CAN_F3R2_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F3R2_FB23 CAN_F3R2_FB23_Msk /*!< Filter bit 23 */
+#define CAN_F3R2_FB24_Pos (24U)
+#define CAN_F3R2_FB24_Msk (0x1U << CAN_F3R2_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F3R2_FB24 CAN_F3R2_FB24_Msk /*!< Filter bit 24 */
+#define CAN_F3R2_FB25_Pos (25U)
+#define CAN_F3R2_FB25_Msk (0x1U << CAN_F3R2_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F3R2_FB25 CAN_F3R2_FB25_Msk /*!< Filter bit 25 */
+#define CAN_F3R2_FB26_Pos (26U)
+#define CAN_F3R2_FB26_Msk (0x1U << CAN_F3R2_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F3R2_FB26 CAN_F3R2_FB26_Msk /*!< Filter bit 26 */
+#define CAN_F3R2_FB27_Pos (27U)
+#define CAN_F3R2_FB27_Msk (0x1U << CAN_F3R2_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F3R2_FB27 CAN_F3R2_FB27_Msk /*!< Filter bit 27 */
+#define CAN_F3R2_FB28_Pos (28U)
+#define CAN_F3R2_FB28_Msk (0x1U << CAN_F3R2_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F3R2_FB28 CAN_F3R2_FB28_Msk /*!< Filter bit 28 */
+#define CAN_F3R2_FB29_Pos (29U)
+#define CAN_F3R2_FB29_Msk (0x1U << CAN_F3R2_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F3R2_FB29 CAN_F3R2_FB29_Msk /*!< Filter bit 29 */
+#define CAN_F3R2_FB30_Pos (30U)
+#define CAN_F3R2_FB30_Msk (0x1U << CAN_F3R2_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F3R2_FB30 CAN_F3R2_FB30_Msk /*!< Filter bit 30 */
+#define CAN_F3R2_FB31_Pos (31U)
+#define CAN_F3R2_FB31_Msk (0x1U << CAN_F3R2_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F3R2_FB31 CAN_F3R2_FB31_Msk /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F4R2 register *******************/
+#define CAN_F4R2_FB0_Pos (0U)
+#define CAN_F4R2_FB0_Msk (0x1U << CAN_F4R2_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F4R2_FB0 CAN_F4R2_FB0_Msk /*!< Filter bit 0 */
+#define CAN_F4R2_FB1_Pos (1U)
+#define CAN_F4R2_FB1_Msk (0x1U << CAN_F4R2_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F4R2_FB1 CAN_F4R2_FB1_Msk /*!< Filter bit 1 */
+#define CAN_F4R2_FB2_Pos (2U)
+#define CAN_F4R2_FB2_Msk (0x1U << CAN_F4R2_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F4R2_FB2 CAN_F4R2_FB2_Msk /*!< Filter bit 2 */
+#define CAN_F4R2_FB3_Pos (3U)
+#define CAN_F4R2_FB3_Msk (0x1U << CAN_F4R2_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F4R2_FB3 CAN_F4R2_FB3_Msk /*!< Filter bit 3 */
+#define CAN_F4R2_FB4_Pos (4U)
+#define CAN_F4R2_FB4_Msk (0x1U << CAN_F4R2_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F4R2_FB4 CAN_F4R2_FB4_Msk /*!< Filter bit 4 */
+#define CAN_F4R2_FB5_Pos (5U)
+#define CAN_F4R2_FB5_Msk (0x1U << CAN_F4R2_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F4R2_FB5 CAN_F4R2_FB5_Msk /*!< Filter bit 5 */
+#define CAN_F4R2_FB6_Pos (6U)
+#define CAN_F4R2_FB6_Msk (0x1U << CAN_F4R2_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F4R2_FB6 CAN_F4R2_FB6_Msk /*!< Filter bit 6 */
+#define CAN_F4R2_FB7_Pos (7U)
+#define CAN_F4R2_FB7_Msk (0x1U << CAN_F4R2_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F4R2_FB7 CAN_F4R2_FB7_Msk /*!< Filter bit 7 */
+#define CAN_F4R2_FB8_Pos (8U)
+#define CAN_F4R2_FB8_Msk (0x1U << CAN_F4R2_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F4R2_FB8 CAN_F4R2_FB8_Msk /*!< Filter bit 8 */
+#define CAN_F4R2_FB9_Pos (9U)
+#define CAN_F4R2_FB9_Msk (0x1U << CAN_F4R2_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F4R2_FB9 CAN_F4R2_FB9_Msk /*!< Filter bit 9 */
+#define CAN_F4R2_FB10_Pos (10U)
+#define CAN_F4R2_FB10_Msk (0x1U << CAN_F4R2_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F4R2_FB10 CAN_F4R2_FB10_Msk /*!< Filter bit 10 */
+#define CAN_F4R2_FB11_Pos (11U)
+#define CAN_F4R2_FB11_Msk (0x1U << CAN_F4R2_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F4R2_FB11 CAN_F4R2_FB11_Msk /*!< Filter bit 11 */
+#define CAN_F4R2_FB12_Pos (12U)
+#define CAN_F4R2_FB12_Msk (0x1U << CAN_F4R2_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F4R2_FB12 CAN_F4R2_FB12_Msk /*!< Filter bit 12 */
+#define CAN_F4R2_FB13_Pos (13U)
+#define CAN_F4R2_FB13_Msk (0x1U << CAN_F4R2_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F4R2_FB13 CAN_F4R2_FB13_Msk /*!< Filter bit 13 */
+#define CAN_F4R2_FB14_Pos (14U)
+#define CAN_F4R2_FB14_Msk (0x1U << CAN_F4R2_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F4R2_FB14 CAN_F4R2_FB14_Msk /*!< Filter bit 14 */
+#define CAN_F4R2_FB15_Pos (15U)
+#define CAN_F4R2_FB15_Msk (0x1U << CAN_F4R2_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F4R2_FB15 CAN_F4R2_FB15_Msk /*!< Filter bit 15 */
+#define CAN_F4R2_FB16_Pos (16U)
+#define CAN_F4R2_FB16_Msk (0x1U << CAN_F4R2_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F4R2_FB16 CAN_F4R2_FB16_Msk /*!< Filter bit 16 */
+#define CAN_F4R2_FB17_Pos (17U)
+#define CAN_F4R2_FB17_Msk (0x1U << CAN_F4R2_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F4R2_FB17 CAN_F4R2_FB17_Msk /*!< Filter bit 17 */
+#define CAN_F4R2_FB18_Pos (18U)
+#define CAN_F4R2_FB18_Msk (0x1U << CAN_F4R2_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F4R2_FB18 CAN_F4R2_FB18_Msk /*!< Filter bit 18 */
+#define CAN_F4R2_FB19_Pos (19U)
+#define CAN_F4R2_FB19_Msk (0x1U << CAN_F4R2_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F4R2_FB19 CAN_F4R2_FB19_Msk /*!< Filter bit 19 */
+#define CAN_F4R2_FB20_Pos (20U)
+#define CAN_F4R2_FB20_Msk (0x1U << CAN_F4R2_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F4R2_FB20 CAN_F4R2_FB20_Msk /*!< Filter bit 20 */
+#define CAN_F4R2_FB21_Pos (21U)
+#define CAN_F4R2_FB21_Msk (0x1U << CAN_F4R2_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F4R2_FB21 CAN_F4R2_FB21_Msk /*!< Filter bit 21 */
+#define CAN_F4R2_FB22_Pos (22U)
+#define CAN_F4R2_FB22_Msk (0x1U << CAN_F4R2_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F4R2_FB22 CAN_F4R2_FB22_Msk /*!< Filter bit 22 */
+#define CAN_F4R2_FB23_Pos (23U)
+#define CAN_F4R2_FB23_Msk (0x1U << CAN_F4R2_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F4R2_FB23 CAN_F4R2_FB23_Msk /*!< Filter bit 23 */
+#define CAN_F4R2_FB24_Pos (24U)
+#define CAN_F4R2_FB24_Msk (0x1U << CAN_F4R2_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F4R2_FB24 CAN_F4R2_FB24_Msk /*!< Filter bit 24 */
+#define CAN_F4R2_FB25_Pos (25U)
+#define CAN_F4R2_FB25_Msk (0x1U << CAN_F4R2_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F4R2_FB25 CAN_F4R2_FB25_Msk /*!< Filter bit 25 */
+#define CAN_F4R2_FB26_Pos (26U)
+#define CAN_F4R2_FB26_Msk (0x1U << CAN_F4R2_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F4R2_FB26 CAN_F4R2_FB26_Msk /*!< Filter bit 26 */
+#define CAN_F4R2_FB27_Pos (27U)
+#define CAN_F4R2_FB27_Msk (0x1U << CAN_F4R2_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F4R2_FB27 CAN_F4R2_FB27_Msk /*!< Filter bit 27 */
+#define CAN_F4R2_FB28_Pos (28U)
+#define CAN_F4R2_FB28_Msk (0x1U << CAN_F4R2_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F4R2_FB28 CAN_F4R2_FB28_Msk /*!< Filter bit 28 */
+#define CAN_F4R2_FB29_Pos (29U)
+#define CAN_F4R2_FB29_Msk (0x1U << CAN_F4R2_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F4R2_FB29 CAN_F4R2_FB29_Msk /*!< Filter bit 29 */
+#define CAN_F4R2_FB30_Pos (30U)
+#define CAN_F4R2_FB30_Msk (0x1U << CAN_F4R2_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F4R2_FB30 CAN_F4R2_FB30_Msk /*!< Filter bit 30 */
+#define CAN_F4R2_FB31_Pos (31U)
+#define CAN_F4R2_FB31_Msk (0x1U << CAN_F4R2_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F4R2_FB31 CAN_F4R2_FB31_Msk /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F5R2 register *******************/
+#define CAN_F5R2_FB0_Pos (0U)
+#define CAN_F5R2_FB0_Msk (0x1U << CAN_F5R2_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F5R2_FB0 CAN_F5R2_FB0_Msk /*!< Filter bit 0 */
+#define CAN_F5R2_FB1_Pos (1U)
+#define CAN_F5R2_FB1_Msk (0x1U << CAN_F5R2_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F5R2_FB1 CAN_F5R2_FB1_Msk /*!< Filter bit 1 */
+#define CAN_F5R2_FB2_Pos (2U)
+#define CAN_F5R2_FB2_Msk (0x1U << CAN_F5R2_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F5R2_FB2 CAN_F5R2_FB2_Msk /*!< Filter bit 2 */
+#define CAN_F5R2_FB3_Pos (3U)
+#define CAN_F5R2_FB3_Msk (0x1U << CAN_F5R2_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F5R2_FB3 CAN_F5R2_FB3_Msk /*!< Filter bit 3 */
+#define CAN_F5R2_FB4_Pos (4U)
+#define CAN_F5R2_FB4_Msk (0x1U << CAN_F5R2_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F5R2_FB4 CAN_F5R2_FB4_Msk /*!< Filter bit 4 */
+#define CAN_F5R2_FB5_Pos (5U)
+#define CAN_F5R2_FB5_Msk (0x1U << CAN_F5R2_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F5R2_FB5 CAN_F5R2_FB5_Msk /*!< Filter bit 5 */
+#define CAN_F5R2_FB6_Pos (6U)
+#define CAN_F5R2_FB6_Msk (0x1U << CAN_F5R2_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F5R2_FB6 CAN_F5R2_FB6_Msk /*!< Filter bit 6 */
+#define CAN_F5R2_FB7_Pos (7U)
+#define CAN_F5R2_FB7_Msk (0x1U << CAN_F5R2_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F5R2_FB7 CAN_F5R2_FB7_Msk /*!< Filter bit 7 */
+#define CAN_F5R2_FB8_Pos (8U)
+#define CAN_F5R2_FB8_Msk (0x1U << CAN_F5R2_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F5R2_FB8 CAN_F5R2_FB8_Msk /*!< Filter bit 8 */
+#define CAN_F5R2_FB9_Pos (9U)
+#define CAN_F5R2_FB9_Msk (0x1U << CAN_F5R2_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F5R2_FB9 CAN_F5R2_FB9_Msk /*!< Filter bit 9 */
+#define CAN_F5R2_FB10_Pos (10U)
+#define CAN_F5R2_FB10_Msk (0x1U << CAN_F5R2_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F5R2_FB10 CAN_F5R2_FB10_Msk /*!< Filter bit 10 */
+#define CAN_F5R2_FB11_Pos (11U)
+#define CAN_F5R2_FB11_Msk (0x1U << CAN_F5R2_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F5R2_FB11 CAN_F5R2_FB11_Msk /*!< Filter bit 11 */
+#define CAN_F5R2_FB12_Pos (12U)
+#define CAN_F5R2_FB12_Msk (0x1U << CAN_F5R2_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F5R2_FB12 CAN_F5R2_FB12_Msk /*!< Filter bit 12 */
+#define CAN_F5R2_FB13_Pos (13U)
+#define CAN_F5R2_FB13_Msk (0x1U << CAN_F5R2_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F5R2_FB13 CAN_F5R2_FB13_Msk /*!< Filter bit 13 */
+#define CAN_F5R2_FB14_Pos (14U)
+#define CAN_F5R2_FB14_Msk (0x1U << CAN_F5R2_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F5R2_FB14 CAN_F5R2_FB14_Msk /*!< Filter bit 14 */
+#define CAN_F5R2_FB15_Pos (15U)
+#define CAN_F5R2_FB15_Msk (0x1U << CAN_F5R2_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F5R2_FB15 CAN_F5R2_FB15_Msk /*!< Filter bit 15 */
+#define CAN_F5R2_FB16_Pos (16U)
+#define CAN_F5R2_FB16_Msk (0x1U << CAN_F5R2_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F5R2_FB16 CAN_F5R2_FB16_Msk /*!< Filter bit 16 */
+#define CAN_F5R2_FB17_Pos (17U)
+#define CAN_F5R2_FB17_Msk (0x1U << CAN_F5R2_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F5R2_FB17 CAN_F5R2_FB17_Msk /*!< Filter bit 17 */
+#define CAN_F5R2_FB18_Pos (18U)
+#define CAN_F5R2_FB18_Msk (0x1U << CAN_F5R2_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F5R2_FB18 CAN_F5R2_FB18_Msk /*!< Filter bit 18 */
+#define CAN_F5R2_FB19_Pos (19U)
+#define CAN_F5R2_FB19_Msk (0x1U << CAN_F5R2_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F5R2_FB19 CAN_F5R2_FB19_Msk /*!< Filter bit 19 */
+#define CAN_F5R2_FB20_Pos (20U)
+#define CAN_F5R2_FB20_Msk (0x1U << CAN_F5R2_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F5R2_FB20 CAN_F5R2_FB20_Msk /*!< Filter bit 20 */
+#define CAN_F5R2_FB21_Pos (21U)
+#define CAN_F5R2_FB21_Msk (0x1U << CAN_F5R2_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F5R2_FB21 CAN_F5R2_FB21_Msk /*!< Filter bit 21 */
+#define CAN_F5R2_FB22_Pos (22U)
+#define CAN_F5R2_FB22_Msk (0x1U << CAN_F5R2_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F5R2_FB22 CAN_F5R2_FB22_Msk /*!< Filter bit 22 */
+#define CAN_F5R2_FB23_Pos (23U)
+#define CAN_F5R2_FB23_Msk (0x1U << CAN_F5R2_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F5R2_FB23 CAN_F5R2_FB23_Msk /*!< Filter bit 23 */
+#define CAN_F5R2_FB24_Pos (24U)
+#define CAN_F5R2_FB24_Msk (0x1U << CAN_F5R2_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F5R2_FB24 CAN_F5R2_FB24_Msk /*!< Filter bit 24 */
+#define CAN_F5R2_FB25_Pos (25U)
+#define CAN_F5R2_FB25_Msk (0x1U << CAN_F5R2_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F5R2_FB25 CAN_F5R2_FB25_Msk /*!< Filter bit 25 */
+#define CAN_F5R2_FB26_Pos (26U)
+#define CAN_F5R2_FB26_Msk (0x1U << CAN_F5R2_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F5R2_FB26 CAN_F5R2_FB26_Msk /*!< Filter bit 26 */
+#define CAN_F5R2_FB27_Pos (27U)
+#define CAN_F5R2_FB27_Msk (0x1U << CAN_F5R2_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F5R2_FB27 CAN_F5R2_FB27_Msk /*!< Filter bit 27 */
+#define CAN_F5R2_FB28_Pos (28U)
+#define CAN_F5R2_FB28_Msk (0x1U << CAN_F5R2_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F5R2_FB28 CAN_F5R2_FB28_Msk /*!< Filter bit 28 */
+#define CAN_F5R2_FB29_Pos (29U)
+#define CAN_F5R2_FB29_Msk (0x1U << CAN_F5R2_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F5R2_FB29 CAN_F5R2_FB29_Msk /*!< Filter bit 29 */
+#define CAN_F5R2_FB30_Pos (30U)
+#define CAN_F5R2_FB30_Msk (0x1U << CAN_F5R2_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F5R2_FB30 CAN_F5R2_FB30_Msk /*!< Filter bit 30 */
+#define CAN_F5R2_FB31_Pos (31U)
+#define CAN_F5R2_FB31_Msk (0x1U << CAN_F5R2_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F5R2_FB31 CAN_F5R2_FB31_Msk /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F6R2 register *******************/
+#define CAN_F6R2_FB0_Pos (0U)
+#define CAN_F6R2_FB0_Msk (0x1U << CAN_F6R2_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F6R2_FB0 CAN_F6R2_FB0_Msk /*!< Filter bit 0 */
+#define CAN_F6R2_FB1_Pos (1U)
+#define CAN_F6R2_FB1_Msk (0x1U << CAN_F6R2_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F6R2_FB1 CAN_F6R2_FB1_Msk /*!< Filter bit 1 */
+#define CAN_F6R2_FB2_Pos (2U)
+#define CAN_F6R2_FB2_Msk (0x1U << CAN_F6R2_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F6R2_FB2 CAN_F6R2_FB2_Msk /*!< Filter bit 2 */
+#define CAN_F6R2_FB3_Pos (3U)
+#define CAN_F6R2_FB3_Msk (0x1U << CAN_F6R2_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F6R2_FB3 CAN_F6R2_FB3_Msk /*!< Filter bit 3 */
+#define CAN_F6R2_FB4_Pos (4U)
+#define CAN_F6R2_FB4_Msk (0x1U << CAN_F6R2_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F6R2_FB4 CAN_F6R2_FB4_Msk /*!< Filter bit 4 */
+#define CAN_F6R2_FB5_Pos (5U)
+#define CAN_F6R2_FB5_Msk (0x1U << CAN_F6R2_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F6R2_FB5 CAN_F6R2_FB5_Msk /*!< Filter bit 5 */
+#define CAN_F6R2_FB6_Pos (6U)
+#define CAN_F6R2_FB6_Msk (0x1U << CAN_F6R2_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F6R2_FB6 CAN_F6R2_FB6_Msk /*!< Filter bit 6 */
+#define CAN_F6R2_FB7_Pos (7U)
+#define CAN_F6R2_FB7_Msk (0x1U << CAN_F6R2_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F6R2_FB7 CAN_F6R2_FB7_Msk /*!< Filter bit 7 */
+#define CAN_F6R2_FB8_Pos (8U)
+#define CAN_F6R2_FB8_Msk (0x1U << CAN_F6R2_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F6R2_FB8 CAN_F6R2_FB8_Msk /*!< Filter bit 8 */
+#define CAN_F6R2_FB9_Pos (9U)
+#define CAN_F6R2_FB9_Msk (0x1U << CAN_F6R2_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F6R2_FB9 CAN_F6R2_FB9_Msk /*!< Filter bit 9 */
+#define CAN_F6R2_FB10_Pos (10U)
+#define CAN_F6R2_FB10_Msk (0x1U << CAN_F6R2_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F6R2_FB10 CAN_F6R2_FB10_Msk /*!< Filter bit 10 */
+#define CAN_F6R2_FB11_Pos (11U)
+#define CAN_F6R2_FB11_Msk (0x1U << CAN_F6R2_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F6R2_FB11 CAN_F6R2_FB11_Msk /*!< Filter bit 11 */
+#define CAN_F6R2_FB12_Pos (12U)
+#define CAN_F6R2_FB12_Msk (0x1U << CAN_F6R2_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F6R2_FB12 CAN_F6R2_FB12_Msk /*!< Filter bit 12 */
+#define CAN_F6R2_FB13_Pos (13U)
+#define CAN_F6R2_FB13_Msk (0x1U << CAN_F6R2_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F6R2_FB13 CAN_F6R2_FB13_Msk /*!< Filter bit 13 */
+#define CAN_F6R2_FB14_Pos (14U)
+#define CAN_F6R2_FB14_Msk (0x1U << CAN_F6R2_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F6R2_FB14 CAN_F6R2_FB14_Msk /*!< Filter bit 14 */
+#define CAN_F6R2_FB15_Pos (15U)
+#define CAN_F6R2_FB15_Msk (0x1U << CAN_F6R2_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F6R2_FB15 CAN_F6R2_FB15_Msk /*!< Filter bit 15 */
+#define CAN_F6R2_FB16_Pos (16U)
+#define CAN_F6R2_FB16_Msk (0x1U << CAN_F6R2_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F6R2_FB16 CAN_F6R2_FB16_Msk /*!< Filter bit 16 */
+#define CAN_F6R2_FB17_Pos (17U)
+#define CAN_F6R2_FB17_Msk (0x1U << CAN_F6R2_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F6R2_FB17 CAN_F6R2_FB17_Msk /*!< Filter bit 17 */
+#define CAN_F6R2_FB18_Pos (18U)
+#define CAN_F6R2_FB18_Msk (0x1U << CAN_F6R2_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F6R2_FB18 CAN_F6R2_FB18_Msk /*!< Filter bit 18 */
+#define CAN_F6R2_FB19_Pos (19U)
+#define CAN_F6R2_FB19_Msk (0x1U << CAN_F6R2_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F6R2_FB19 CAN_F6R2_FB19_Msk /*!< Filter bit 19 */
+#define CAN_F6R2_FB20_Pos (20U)
+#define CAN_F6R2_FB20_Msk (0x1U << CAN_F6R2_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F6R2_FB20 CAN_F6R2_FB20_Msk /*!< Filter bit 20 */
+#define CAN_F6R2_FB21_Pos (21U)
+#define CAN_F6R2_FB21_Msk (0x1U << CAN_F6R2_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F6R2_FB21 CAN_F6R2_FB21_Msk /*!< Filter bit 21 */
+#define CAN_F6R2_FB22_Pos (22U)
+#define CAN_F6R2_FB22_Msk (0x1U << CAN_F6R2_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F6R2_FB22 CAN_F6R2_FB22_Msk /*!< Filter bit 22 */
+#define CAN_F6R2_FB23_Pos (23U)
+#define CAN_F6R2_FB23_Msk (0x1U << CAN_F6R2_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F6R2_FB23 CAN_F6R2_FB23_Msk /*!< Filter bit 23 */
+#define CAN_F6R2_FB24_Pos (24U)
+#define CAN_F6R2_FB24_Msk (0x1U << CAN_F6R2_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F6R2_FB24 CAN_F6R2_FB24_Msk /*!< Filter bit 24 */
+#define CAN_F6R2_FB25_Pos (25U)
+#define CAN_F6R2_FB25_Msk (0x1U << CAN_F6R2_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F6R2_FB25 CAN_F6R2_FB25_Msk /*!< Filter bit 25 */
+#define CAN_F6R2_FB26_Pos (26U)
+#define CAN_F6R2_FB26_Msk (0x1U << CAN_F6R2_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F6R2_FB26 CAN_F6R2_FB26_Msk /*!< Filter bit 26 */
+#define CAN_F6R2_FB27_Pos (27U)
+#define CAN_F6R2_FB27_Msk (0x1U << CAN_F6R2_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F6R2_FB27 CAN_F6R2_FB27_Msk /*!< Filter bit 27 */
+#define CAN_F6R2_FB28_Pos (28U)
+#define CAN_F6R2_FB28_Msk (0x1U << CAN_F6R2_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F6R2_FB28 CAN_F6R2_FB28_Msk /*!< Filter bit 28 */
+#define CAN_F6R2_FB29_Pos (29U)
+#define CAN_F6R2_FB29_Msk (0x1U << CAN_F6R2_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F6R2_FB29 CAN_F6R2_FB29_Msk /*!< Filter bit 29 */
+#define CAN_F6R2_FB30_Pos (30U)
+#define CAN_F6R2_FB30_Msk (0x1U << CAN_F6R2_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F6R2_FB30 CAN_F6R2_FB30_Msk /*!< Filter bit 30 */
+#define CAN_F6R2_FB31_Pos (31U)
+#define CAN_F6R2_FB31_Msk (0x1U << CAN_F6R2_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F6R2_FB31 CAN_F6R2_FB31_Msk /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F7R2 register *******************/
+#define CAN_F7R2_FB0_Pos (0U)
+#define CAN_F7R2_FB0_Msk (0x1U << CAN_F7R2_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F7R2_FB0 CAN_F7R2_FB0_Msk /*!< Filter bit 0 */
+#define CAN_F7R2_FB1_Pos (1U)
+#define CAN_F7R2_FB1_Msk (0x1U << CAN_F7R2_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F7R2_FB1 CAN_F7R2_FB1_Msk /*!< Filter bit 1 */
+#define CAN_F7R2_FB2_Pos (2U)
+#define CAN_F7R2_FB2_Msk (0x1U << CAN_F7R2_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F7R2_FB2 CAN_F7R2_FB2_Msk /*!< Filter bit 2 */
+#define CAN_F7R2_FB3_Pos (3U)
+#define CAN_F7R2_FB3_Msk (0x1U << CAN_F7R2_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F7R2_FB3 CAN_F7R2_FB3_Msk /*!< Filter bit 3 */
+#define CAN_F7R2_FB4_Pos (4U)
+#define CAN_F7R2_FB4_Msk (0x1U << CAN_F7R2_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F7R2_FB4 CAN_F7R2_FB4_Msk /*!< Filter bit 4 */
+#define CAN_F7R2_FB5_Pos (5U)
+#define CAN_F7R2_FB5_Msk (0x1U << CAN_F7R2_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F7R2_FB5 CAN_F7R2_FB5_Msk /*!< Filter bit 5 */
+#define CAN_F7R2_FB6_Pos (6U)
+#define CAN_F7R2_FB6_Msk (0x1U << CAN_F7R2_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F7R2_FB6 CAN_F7R2_FB6_Msk /*!< Filter bit 6 */
+#define CAN_F7R2_FB7_Pos (7U)
+#define CAN_F7R2_FB7_Msk (0x1U << CAN_F7R2_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F7R2_FB7 CAN_F7R2_FB7_Msk /*!< Filter bit 7 */
+#define CAN_F7R2_FB8_Pos (8U)
+#define CAN_F7R2_FB8_Msk (0x1U << CAN_F7R2_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F7R2_FB8 CAN_F7R2_FB8_Msk /*!< Filter bit 8 */
+#define CAN_F7R2_FB9_Pos (9U)
+#define CAN_F7R2_FB9_Msk (0x1U << CAN_F7R2_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F7R2_FB9 CAN_F7R2_FB9_Msk /*!< Filter bit 9 */
+#define CAN_F7R2_FB10_Pos (10U)
+#define CAN_F7R2_FB10_Msk (0x1U << CAN_F7R2_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F7R2_FB10 CAN_F7R2_FB10_Msk /*!< Filter bit 10 */
+#define CAN_F7R2_FB11_Pos (11U)
+#define CAN_F7R2_FB11_Msk (0x1U << CAN_F7R2_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F7R2_FB11 CAN_F7R2_FB11_Msk /*!< Filter bit 11 */
+#define CAN_F7R2_FB12_Pos (12U)
+#define CAN_F7R2_FB12_Msk (0x1U << CAN_F7R2_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F7R2_FB12 CAN_F7R2_FB12_Msk /*!< Filter bit 12 */
+#define CAN_F7R2_FB13_Pos (13U)
+#define CAN_F7R2_FB13_Msk (0x1U << CAN_F7R2_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F7R2_FB13 CAN_F7R2_FB13_Msk /*!< Filter bit 13 */
+#define CAN_F7R2_FB14_Pos (14U)
+#define CAN_F7R2_FB14_Msk (0x1U << CAN_F7R2_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F7R2_FB14 CAN_F7R2_FB14_Msk /*!< Filter bit 14 */
+#define CAN_F7R2_FB15_Pos (15U)
+#define CAN_F7R2_FB15_Msk (0x1U << CAN_F7R2_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F7R2_FB15 CAN_F7R2_FB15_Msk /*!< Filter bit 15 */
+#define CAN_F7R2_FB16_Pos (16U)
+#define CAN_F7R2_FB16_Msk (0x1U << CAN_F7R2_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F7R2_FB16 CAN_F7R2_FB16_Msk /*!< Filter bit 16 */
+#define CAN_F7R2_FB17_Pos (17U)
+#define CAN_F7R2_FB17_Msk (0x1U << CAN_F7R2_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F7R2_FB17 CAN_F7R2_FB17_Msk /*!< Filter bit 17 */
+#define CAN_F7R2_FB18_Pos (18U)
+#define CAN_F7R2_FB18_Msk (0x1U << CAN_F7R2_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F7R2_FB18 CAN_F7R2_FB18_Msk /*!< Filter bit 18 */
+#define CAN_F7R2_FB19_Pos (19U)
+#define CAN_F7R2_FB19_Msk (0x1U << CAN_F7R2_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F7R2_FB19 CAN_F7R2_FB19_Msk /*!< Filter bit 19 */
+#define CAN_F7R2_FB20_Pos (20U)
+#define CAN_F7R2_FB20_Msk (0x1U << CAN_F7R2_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F7R2_FB20 CAN_F7R2_FB20_Msk /*!< Filter bit 20 */
+#define CAN_F7R2_FB21_Pos (21U)
+#define CAN_F7R2_FB21_Msk (0x1U << CAN_F7R2_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F7R2_FB21 CAN_F7R2_FB21_Msk /*!< Filter bit 21 */
+#define CAN_F7R2_FB22_Pos (22U)
+#define CAN_F7R2_FB22_Msk (0x1U << CAN_F7R2_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F7R2_FB22 CAN_F7R2_FB22_Msk /*!< Filter bit 22 */
+#define CAN_F7R2_FB23_Pos (23U)
+#define CAN_F7R2_FB23_Msk (0x1U << CAN_F7R2_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F7R2_FB23 CAN_F7R2_FB23_Msk /*!< Filter bit 23 */
+#define CAN_F7R2_FB24_Pos (24U)
+#define CAN_F7R2_FB24_Msk (0x1U << CAN_F7R2_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F7R2_FB24 CAN_F7R2_FB24_Msk /*!< Filter bit 24 */
+#define CAN_F7R2_FB25_Pos (25U)
+#define CAN_F7R2_FB25_Msk (0x1U << CAN_F7R2_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F7R2_FB25 CAN_F7R2_FB25_Msk /*!< Filter bit 25 */
+#define CAN_F7R2_FB26_Pos (26U)
+#define CAN_F7R2_FB26_Msk (0x1U << CAN_F7R2_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F7R2_FB26 CAN_F7R2_FB26_Msk /*!< Filter bit 26 */
+#define CAN_F7R2_FB27_Pos (27U)
+#define CAN_F7R2_FB27_Msk (0x1U << CAN_F7R2_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F7R2_FB27 CAN_F7R2_FB27_Msk /*!< Filter bit 27 */
+#define CAN_F7R2_FB28_Pos (28U)
+#define CAN_F7R2_FB28_Msk (0x1U << CAN_F7R2_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F7R2_FB28 CAN_F7R2_FB28_Msk /*!< Filter bit 28 */
+#define CAN_F7R2_FB29_Pos (29U)
+#define CAN_F7R2_FB29_Msk (0x1U << CAN_F7R2_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F7R2_FB29 CAN_F7R2_FB29_Msk /*!< Filter bit 29 */
+#define CAN_F7R2_FB30_Pos (30U)
+#define CAN_F7R2_FB30_Msk (0x1U << CAN_F7R2_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F7R2_FB30 CAN_F7R2_FB30_Msk /*!< Filter bit 30 */
+#define CAN_F7R2_FB31_Pos (31U)
+#define CAN_F7R2_FB31_Msk (0x1U << CAN_F7R2_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F7R2_FB31 CAN_F7R2_FB31_Msk /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F8R2 register *******************/
+#define CAN_F8R2_FB0_Pos (0U)
+#define CAN_F8R2_FB0_Msk (0x1U << CAN_F8R2_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F8R2_FB0 CAN_F8R2_FB0_Msk /*!< Filter bit 0 */
+#define CAN_F8R2_FB1_Pos (1U)
+#define CAN_F8R2_FB1_Msk (0x1U << CAN_F8R2_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F8R2_FB1 CAN_F8R2_FB1_Msk /*!< Filter bit 1 */
+#define CAN_F8R2_FB2_Pos (2U)
+#define CAN_F8R2_FB2_Msk (0x1U << CAN_F8R2_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F8R2_FB2 CAN_F8R2_FB2_Msk /*!< Filter bit 2 */
+#define CAN_F8R2_FB3_Pos (3U)
+#define CAN_F8R2_FB3_Msk (0x1U << CAN_F8R2_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F8R2_FB3 CAN_F8R2_FB3_Msk /*!< Filter bit 3 */
+#define CAN_F8R2_FB4_Pos (4U)
+#define CAN_F8R2_FB4_Msk (0x1U << CAN_F8R2_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F8R2_FB4 CAN_F8R2_FB4_Msk /*!< Filter bit 4 */
+#define CAN_F8R2_FB5_Pos (5U)
+#define CAN_F8R2_FB5_Msk (0x1U << CAN_F8R2_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F8R2_FB5 CAN_F8R2_FB5_Msk /*!< Filter bit 5 */
+#define CAN_F8R2_FB6_Pos (6U)
+#define CAN_F8R2_FB6_Msk (0x1U << CAN_F8R2_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F8R2_FB6 CAN_F8R2_FB6_Msk /*!< Filter bit 6 */
+#define CAN_F8R2_FB7_Pos (7U)
+#define CAN_F8R2_FB7_Msk (0x1U << CAN_F8R2_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F8R2_FB7 CAN_F8R2_FB7_Msk /*!< Filter bit 7 */
+#define CAN_F8R2_FB8_Pos (8U)
+#define CAN_F8R2_FB8_Msk (0x1U << CAN_F8R2_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F8R2_FB8 CAN_F8R2_FB8_Msk /*!< Filter bit 8 */
+#define CAN_F8R2_FB9_Pos (9U)
+#define CAN_F8R2_FB9_Msk (0x1U << CAN_F8R2_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F8R2_FB9 CAN_F8R2_FB9_Msk /*!< Filter bit 9 */
+#define CAN_F8R2_FB10_Pos (10U)
+#define CAN_F8R2_FB10_Msk (0x1U << CAN_F8R2_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F8R2_FB10 CAN_F8R2_FB10_Msk /*!< Filter bit 10 */
+#define CAN_F8R2_FB11_Pos (11U)
+#define CAN_F8R2_FB11_Msk (0x1U << CAN_F8R2_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F8R2_FB11 CAN_F8R2_FB11_Msk /*!< Filter bit 11 */
+#define CAN_F8R2_FB12_Pos (12U)
+#define CAN_F8R2_FB12_Msk (0x1U << CAN_F8R2_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F8R2_FB12 CAN_F8R2_FB12_Msk /*!< Filter bit 12 */
+#define CAN_F8R2_FB13_Pos (13U)
+#define CAN_F8R2_FB13_Msk (0x1U << CAN_F8R2_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F8R2_FB13 CAN_F8R2_FB13_Msk /*!< Filter bit 13 */
+#define CAN_F8R2_FB14_Pos (14U)
+#define CAN_F8R2_FB14_Msk (0x1U << CAN_F8R2_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F8R2_FB14 CAN_F8R2_FB14_Msk /*!< Filter bit 14 */
+#define CAN_F8R2_FB15_Pos (15U)
+#define CAN_F8R2_FB15_Msk (0x1U << CAN_F8R2_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F8R2_FB15 CAN_F8R2_FB15_Msk /*!< Filter bit 15 */
+#define CAN_F8R2_FB16_Pos (16U)
+#define CAN_F8R2_FB16_Msk (0x1U << CAN_F8R2_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F8R2_FB16 CAN_F8R2_FB16_Msk /*!< Filter bit 16 */
+#define CAN_F8R2_FB17_Pos (17U)
+#define CAN_F8R2_FB17_Msk (0x1U << CAN_F8R2_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F8R2_FB17 CAN_F8R2_FB17_Msk /*!< Filter bit 17 */
+#define CAN_F8R2_FB18_Pos (18U)
+#define CAN_F8R2_FB18_Msk (0x1U << CAN_F8R2_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F8R2_FB18 CAN_F8R2_FB18_Msk /*!< Filter bit 18 */
+#define CAN_F8R2_FB19_Pos (19U)
+#define CAN_F8R2_FB19_Msk (0x1U << CAN_F8R2_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F8R2_FB19 CAN_F8R2_FB19_Msk /*!< Filter bit 19 */
+#define CAN_F8R2_FB20_Pos (20U)
+#define CAN_F8R2_FB20_Msk (0x1U << CAN_F8R2_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F8R2_FB20 CAN_F8R2_FB20_Msk /*!< Filter bit 20 */
+#define CAN_F8R2_FB21_Pos (21U)
+#define CAN_F8R2_FB21_Msk (0x1U << CAN_F8R2_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F8R2_FB21 CAN_F8R2_FB21_Msk /*!< Filter bit 21 */
+#define CAN_F8R2_FB22_Pos (22U)
+#define CAN_F8R2_FB22_Msk (0x1U << CAN_F8R2_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F8R2_FB22 CAN_F8R2_FB22_Msk /*!< Filter bit 22 */
+#define CAN_F8R2_FB23_Pos (23U)
+#define CAN_F8R2_FB23_Msk (0x1U << CAN_F8R2_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F8R2_FB23 CAN_F8R2_FB23_Msk /*!< Filter bit 23 */
+#define CAN_F8R2_FB24_Pos (24U)
+#define CAN_F8R2_FB24_Msk (0x1U << CAN_F8R2_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F8R2_FB24 CAN_F8R2_FB24_Msk /*!< Filter bit 24 */
+#define CAN_F8R2_FB25_Pos (25U)
+#define CAN_F8R2_FB25_Msk (0x1U << CAN_F8R2_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F8R2_FB25 CAN_F8R2_FB25_Msk /*!< Filter bit 25 */
+#define CAN_F8R2_FB26_Pos (26U)
+#define CAN_F8R2_FB26_Msk (0x1U << CAN_F8R2_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F8R2_FB26 CAN_F8R2_FB26_Msk /*!< Filter bit 26 */
+#define CAN_F8R2_FB27_Pos (27U)
+#define CAN_F8R2_FB27_Msk (0x1U << CAN_F8R2_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F8R2_FB27 CAN_F8R2_FB27_Msk /*!< Filter bit 27 */
+#define CAN_F8R2_FB28_Pos (28U)
+#define CAN_F8R2_FB28_Msk (0x1U << CAN_F8R2_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F8R2_FB28 CAN_F8R2_FB28_Msk /*!< Filter bit 28 */
+#define CAN_F8R2_FB29_Pos (29U)
+#define CAN_F8R2_FB29_Msk (0x1U << CAN_F8R2_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F8R2_FB29 CAN_F8R2_FB29_Msk /*!< Filter bit 29 */
+#define CAN_F8R2_FB30_Pos (30U)
+#define CAN_F8R2_FB30_Msk (0x1U << CAN_F8R2_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F8R2_FB30 CAN_F8R2_FB30_Msk /*!< Filter bit 30 */
+#define CAN_F8R2_FB31_Pos (31U)
+#define CAN_F8R2_FB31_Msk (0x1U << CAN_F8R2_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F8R2_FB31 CAN_F8R2_FB31_Msk /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F9R2 register *******************/
+#define CAN_F9R2_FB0_Pos (0U)
+#define CAN_F9R2_FB0_Msk (0x1U << CAN_F9R2_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F9R2_FB0 CAN_F9R2_FB0_Msk /*!< Filter bit 0 */
+#define CAN_F9R2_FB1_Pos (1U)
+#define CAN_F9R2_FB1_Msk (0x1U << CAN_F9R2_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F9R2_FB1 CAN_F9R2_FB1_Msk /*!< Filter bit 1 */
+#define CAN_F9R2_FB2_Pos (2U)
+#define CAN_F9R2_FB2_Msk (0x1U << CAN_F9R2_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F9R2_FB2 CAN_F9R2_FB2_Msk /*!< Filter bit 2 */
+#define CAN_F9R2_FB3_Pos (3U)
+#define CAN_F9R2_FB3_Msk (0x1U << CAN_F9R2_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F9R2_FB3 CAN_F9R2_FB3_Msk /*!< Filter bit 3 */
+#define CAN_F9R2_FB4_Pos (4U)
+#define CAN_F9R2_FB4_Msk (0x1U << CAN_F9R2_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F9R2_FB4 CAN_F9R2_FB4_Msk /*!< Filter bit 4 */
+#define CAN_F9R2_FB5_Pos (5U)
+#define CAN_F9R2_FB5_Msk (0x1U << CAN_F9R2_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F9R2_FB5 CAN_F9R2_FB5_Msk /*!< Filter bit 5 */
+#define CAN_F9R2_FB6_Pos (6U)
+#define CAN_F9R2_FB6_Msk (0x1U << CAN_F9R2_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F9R2_FB6 CAN_F9R2_FB6_Msk /*!< Filter bit 6 */
+#define CAN_F9R2_FB7_Pos (7U)
+#define CAN_F9R2_FB7_Msk (0x1U << CAN_F9R2_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F9R2_FB7 CAN_F9R2_FB7_Msk /*!< Filter bit 7 */
+#define CAN_F9R2_FB8_Pos (8U)
+#define CAN_F9R2_FB8_Msk (0x1U << CAN_F9R2_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F9R2_FB8 CAN_F9R2_FB8_Msk /*!< Filter bit 8 */
+#define CAN_F9R2_FB9_Pos (9U)
+#define CAN_F9R2_FB9_Msk (0x1U << CAN_F9R2_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F9R2_FB9 CAN_F9R2_FB9_Msk /*!< Filter bit 9 */
+#define CAN_F9R2_FB10_Pos (10U)
+#define CAN_F9R2_FB10_Msk (0x1U << CAN_F9R2_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F9R2_FB10 CAN_F9R2_FB10_Msk /*!< Filter bit 10 */
+#define CAN_F9R2_FB11_Pos (11U)
+#define CAN_F9R2_FB11_Msk (0x1U << CAN_F9R2_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F9R2_FB11 CAN_F9R2_FB11_Msk /*!< Filter bit 11 */
+#define CAN_F9R2_FB12_Pos (12U)
+#define CAN_F9R2_FB12_Msk (0x1U << CAN_F9R2_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F9R2_FB12 CAN_F9R2_FB12_Msk /*!< Filter bit 12 */
+#define CAN_F9R2_FB13_Pos (13U)
+#define CAN_F9R2_FB13_Msk (0x1U << CAN_F9R2_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F9R2_FB13 CAN_F9R2_FB13_Msk /*!< Filter bit 13 */
+#define CAN_F9R2_FB14_Pos (14U)
+#define CAN_F9R2_FB14_Msk (0x1U << CAN_F9R2_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F9R2_FB14 CAN_F9R2_FB14_Msk /*!< Filter bit 14 */
+#define CAN_F9R2_FB15_Pos (15U)
+#define CAN_F9R2_FB15_Msk (0x1U << CAN_F9R2_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F9R2_FB15 CAN_F9R2_FB15_Msk /*!< Filter bit 15 */
+#define CAN_F9R2_FB16_Pos (16U)
+#define CAN_F9R2_FB16_Msk (0x1U << CAN_F9R2_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F9R2_FB16 CAN_F9R2_FB16_Msk /*!< Filter bit 16 */
+#define CAN_F9R2_FB17_Pos (17U)
+#define CAN_F9R2_FB17_Msk (0x1U << CAN_F9R2_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F9R2_FB17 CAN_F9R2_FB17_Msk /*!< Filter bit 17 */
+#define CAN_F9R2_FB18_Pos (18U)
+#define CAN_F9R2_FB18_Msk (0x1U << CAN_F9R2_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F9R2_FB18 CAN_F9R2_FB18_Msk /*!< Filter bit 18 */
+#define CAN_F9R2_FB19_Pos (19U)
+#define CAN_F9R2_FB19_Msk (0x1U << CAN_F9R2_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F9R2_FB19 CAN_F9R2_FB19_Msk /*!< Filter bit 19 */
+#define CAN_F9R2_FB20_Pos (20U)
+#define CAN_F9R2_FB20_Msk (0x1U << CAN_F9R2_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F9R2_FB20 CAN_F9R2_FB20_Msk /*!< Filter bit 20 */
+#define CAN_F9R2_FB21_Pos (21U)
+#define CAN_F9R2_FB21_Msk (0x1U << CAN_F9R2_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F9R2_FB21 CAN_F9R2_FB21_Msk /*!< Filter bit 21 */
+#define CAN_F9R2_FB22_Pos (22U)
+#define CAN_F9R2_FB22_Msk (0x1U << CAN_F9R2_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F9R2_FB22 CAN_F9R2_FB22_Msk /*!< Filter bit 22 */
+#define CAN_F9R2_FB23_Pos (23U)
+#define CAN_F9R2_FB23_Msk (0x1U << CAN_F9R2_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F9R2_FB23 CAN_F9R2_FB23_Msk /*!< Filter bit 23 */
+#define CAN_F9R2_FB24_Pos (24U)
+#define CAN_F9R2_FB24_Msk (0x1U << CAN_F9R2_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F9R2_FB24 CAN_F9R2_FB24_Msk /*!< Filter bit 24 */
+#define CAN_F9R2_FB25_Pos (25U)
+#define CAN_F9R2_FB25_Msk (0x1U << CAN_F9R2_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F9R2_FB25 CAN_F9R2_FB25_Msk /*!< Filter bit 25 */
+#define CAN_F9R2_FB26_Pos (26U)
+#define CAN_F9R2_FB26_Msk (0x1U << CAN_F9R2_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F9R2_FB26 CAN_F9R2_FB26_Msk /*!< Filter bit 26 */
+#define CAN_F9R2_FB27_Pos (27U)
+#define CAN_F9R2_FB27_Msk (0x1U << CAN_F9R2_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F9R2_FB27 CAN_F9R2_FB27_Msk /*!< Filter bit 27 */
+#define CAN_F9R2_FB28_Pos (28U)
+#define CAN_F9R2_FB28_Msk (0x1U << CAN_F9R2_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F9R2_FB28 CAN_F9R2_FB28_Msk /*!< Filter bit 28 */
+#define CAN_F9R2_FB29_Pos (29U)
+#define CAN_F9R2_FB29_Msk (0x1U << CAN_F9R2_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F9R2_FB29 CAN_F9R2_FB29_Msk /*!< Filter bit 29 */
+#define CAN_F9R2_FB30_Pos (30U)
+#define CAN_F9R2_FB30_Msk (0x1U << CAN_F9R2_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F9R2_FB30 CAN_F9R2_FB30_Msk /*!< Filter bit 30 */
+#define CAN_F9R2_FB31_Pos (31U)
+#define CAN_F9R2_FB31_Msk (0x1U << CAN_F9R2_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F9R2_FB31 CAN_F9R2_FB31_Msk /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F10R2 register ******************/
+#define CAN_F10R2_FB0_Pos (0U)
+#define CAN_F10R2_FB0_Msk (0x1U << CAN_F10R2_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F10R2_FB0 CAN_F10R2_FB0_Msk /*!< Filter bit 0 */
+#define CAN_F10R2_FB1_Pos (1U)
+#define CAN_F10R2_FB1_Msk (0x1U << CAN_F10R2_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F10R2_FB1 CAN_F10R2_FB1_Msk /*!< Filter bit 1 */
+#define CAN_F10R2_FB2_Pos (2U)
+#define CAN_F10R2_FB2_Msk (0x1U << CAN_F10R2_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F10R2_FB2 CAN_F10R2_FB2_Msk /*!< Filter bit 2 */
+#define CAN_F10R2_FB3_Pos (3U)
+#define CAN_F10R2_FB3_Msk (0x1U << CAN_F10R2_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F10R2_FB3 CAN_F10R2_FB3_Msk /*!< Filter bit 3 */
+#define CAN_F10R2_FB4_Pos (4U)
+#define CAN_F10R2_FB4_Msk (0x1U << CAN_F10R2_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F10R2_FB4 CAN_F10R2_FB4_Msk /*!< Filter bit 4 */
+#define CAN_F10R2_FB5_Pos (5U)
+#define CAN_F10R2_FB5_Msk (0x1U << CAN_F10R2_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F10R2_FB5 CAN_F10R2_FB5_Msk /*!< Filter bit 5 */
+#define CAN_F10R2_FB6_Pos (6U)
+#define CAN_F10R2_FB6_Msk (0x1U << CAN_F10R2_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F10R2_FB6 CAN_F10R2_FB6_Msk /*!< Filter bit 6 */
+#define CAN_F10R2_FB7_Pos (7U)
+#define CAN_F10R2_FB7_Msk (0x1U << CAN_F10R2_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F10R2_FB7 CAN_F10R2_FB7_Msk /*!< Filter bit 7 */
+#define CAN_F10R2_FB8_Pos (8U)
+#define CAN_F10R2_FB8_Msk (0x1U << CAN_F10R2_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F10R2_FB8 CAN_F10R2_FB8_Msk /*!< Filter bit 8 */
+#define CAN_F10R2_FB9_Pos (9U)
+#define CAN_F10R2_FB9_Msk (0x1U << CAN_F10R2_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F10R2_FB9 CAN_F10R2_FB9_Msk /*!< Filter bit 9 */
+#define CAN_F10R2_FB10_Pos (10U)
+#define CAN_F10R2_FB10_Msk (0x1U << CAN_F10R2_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F10R2_FB10 CAN_F10R2_FB10_Msk /*!< Filter bit 10 */
+#define CAN_F10R2_FB11_Pos (11U)
+#define CAN_F10R2_FB11_Msk (0x1U << CAN_F10R2_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F10R2_FB11 CAN_F10R2_FB11_Msk /*!< Filter bit 11 */
+#define CAN_F10R2_FB12_Pos (12U)
+#define CAN_F10R2_FB12_Msk (0x1U << CAN_F10R2_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F10R2_FB12 CAN_F10R2_FB12_Msk /*!< Filter bit 12 */
+#define CAN_F10R2_FB13_Pos (13U)
+#define CAN_F10R2_FB13_Msk (0x1U << CAN_F10R2_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F10R2_FB13 CAN_F10R2_FB13_Msk /*!< Filter bit 13 */
+#define CAN_F10R2_FB14_Pos (14U)
+#define CAN_F10R2_FB14_Msk (0x1U << CAN_F10R2_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F10R2_FB14 CAN_F10R2_FB14_Msk /*!< Filter bit 14 */
+#define CAN_F10R2_FB15_Pos (15U)
+#define CAN_F10R2_FB15_Msk (0x1U << CAN_F10R2_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F10R2_FB15 CAN_F10R2_FB15_Msk /*!< Filter bit 15 */
+#define CAN_F10R2_FB16_Pos (16U)
+#define CAN_F10R2_FB16_Msk (0x1U << CAN_F10R2_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F10R2_FB16 CAN_F10R2_FB16_Msk /*!< Filter bit 16 */
+#define CAN_F10R2_FB17_Pos (17U)
+#define CAN_F10R2_FB17_Msk (0x1U << CAN_F10R2_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F10R2_FB17 CAN_F10R2_FB17_Msk /*!< Filter bit 17 */
+#define CAN_F10R2_FB18_Pos (18U)
+#define CAN_F10R2_FB18_Msk (0x1U << CAN_F10R2_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F10R2_FB18 CAN_F10R2_FB18_Msk /*!< Filter bit 18 */
+#define CAN_F10R2_FB19_Pos (19U)
+#define CAN_F10R2_FB19_Msk (0x1U << CAN_F10R2_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F10R2_FB19 CAN_F10R2_FB19_Msk /*!< Filter bit 19 */
+#define CAN_F10R2_FB20_Pos (20U)
+#define CAN_F10R2_FB20_Msk (0x1U << CAN_F10R2_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F10R2_FB20 CAN_F10R2_FB20_Msk /*!< Filter bit 20 */
+#define CAN_F10R2_FB21_Pos (21U)
+#define CAN_F10R2_FB21_Msk (0x1U << CAN_F10R2_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F10R2_FB21 CAN_F10R2_FB21_Msk /*!< Filter bit 21 */
+#define CAN_F10R2_FB22_Pos (22U)
+#define CAN_F10R2_FB22_Msk (0x1U << CAN_F10R2_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F10R2_FB22 CAN_F10R2_FB22_Msk /*!< Filter bit 22 */
+#define CAN_F10R2_FB23_Pos (23U)
+#define CAN_F10R2_FB23_Msk (0x1U << CAN_F10R2_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F10R2_FB23 CAN_F10R2_FB23_Msk /*!< Filter bit 23 */
+#define CAN_F10R2_FB24_Pos (24U)
+#define CAN_F10R2_FB24_Msk (0x1U << CAN_F10R2_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F10R2_FB24 CAN_F10R2_FB24_Msk /*!< Filter bit 24 */
+#define CAN_F10R2_FB25_Pos (25U)
+#define CAN_F10R2_FB25_Msk (0x1U << CAN_F10R2_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F10R2_FB25 CAN_F10R2_FB25_Msk /*!< Filter bit 25 */
+#define CAN_F10R2_FB26_Pos (26U)
+#define CAN_F10R2_FB26_Msk (0x1U << CAN_F10R2_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F10R2_FB26 CAN_F10R2_FB26_Msk /*!< Filter bit 26 */
+#define CAN_F10R2_FB27_Pos (27U)
+#define CAN_F10R2_FB27_Msk (0x1U << CAN_F10R2_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F10R2_FB27 CAN_F10R2_FB27_Msk /*!< Filter bit 27 */
+#define CAN_F10R2_FB28_Pos (28U)
+#define CAN_F10R2_FB28_Msk (0x1U << CAN_F10R2_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F10R2_FB28 CAN_F10R2_FB28_Msk /*!< Filter bit 28 */
+#define CAN_F10R2_FB29_Pos (29U)
+#define CAN_F10R2_FB29_Msk (0x1U << CAN_F10R2_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F10R2_FB29 CAN_F10R2_FB29_Msk /*!< Filter bit 29 */
+#define CAN_F10R2_FB30_Pos (30U)
+#define CAN_F10R2_FB30_Msk (0x1U << CAN_F10R2_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F10R2_FB30 CAN_F10R2_FB30_Msk /*!< Filter bit 30 */
+#define CAN_F10R2_FB31_Pos (31U)
+#define CAN_F10R2_FB31_Msk (0x1U << CAN_F10R2_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F10R2_FB31 CAN_F10R2_FB31_Msk /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F11R2 register ******************/
+#define CAN_F11R2_FB0_Pos (0U)
+#define CAN_F11R2_FB0_Msk (0x1U << CAN_F11R2_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F11R2_FB0 CAN_F11R2_FB0_Msk /*!< Filter bit 0 */
+#define CAN_F11R2_FB1_Pos (1U)
+#define CAN_F11R2_FB1_Msk (0x1U << CAN_F11R2_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F11R2_FB1 CAN_F11R2_FB1_Msk /*!< Filter bit 1 */
+#define CAN_F11R2_FB2_Pos (2U)
+#define CAN_F11R2_FB2_Msk (0x1U << CAN_F11R2_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F11R2_FB2 CAN_F11R2_FB2_Msk /*!< Filter bit 2 */
+#define CAN_F11R2_FB3_Pos (3U)
+#define CAN_F11R2_FB3_Msk (0x1U << CAN_F11R2_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F11R2_FB3 CAN_F11R2_FB3_Msk /*!< Filter bit 3 */
+#define CAN_F11R2_FB4_Pos (4U)
+#define CAN_F11R2_FB4_Msk (0x1U << CAN_F11R2_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F11R2_FB4 CAN_F11R2_FB4_Msk /*!< Filter bit 4 */
+#define CAN_F11R2_FB5_Pos (5U)
+#define CAN_F11R2_FB5_Msk (0x1U << CAN_F11R2_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F11R2_FB5 CAN_F11R2_FB5_Msk /*!< Filter bit 5 */
+#define CAN_F11R2_FB6_Pos (6U)
+#define CAN_F11R2_FB6_Msk (0x1U << CAN_F11R2_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F11R2_FB6 CAN_F11R2_FB6_Msk /*!< Filter bit 6 */
+#define CAN_F11R2_FB7_Pos (7U)
+#define CAN_F11R2_FB7_Msk (0x1U << CAN_F11R2_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F11R2_FB7 CAN_F11R2_FB7_Msk /*!< Filter bit 7 */
+#define CAN_F11R2_FB8_Pos (8U)
+#define CAN_F11R2_FB8_Msk (0x1U << CAN_F11R2_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F11R2_FB8 CAN_F11R2_FB8_Msk /*!< Filter bit 8 */
+#define CAN_F11R2_FB9_Pos (9U)
+#define CAN_F11R2_FB9_Msk (0x1U << CAN_F11R2_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F11R2_FB9 CAN_F11R2_FB9_Msk /*!< Filter bit 9 */
+#define CAN_F11R2_FB10_Pos (10U)
+#define CAN_F11R2_FB10_Msk (0x1U << CAN_F11R2_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F11R2_FB10 CAN_F11R2_FB10_Msk /*!< Filter bit 10 */
+#define CAN_F11R2_FB11_Pos (11U)
+#define CAN_F11R2_FB11_Msk (0x1U << CAN_F11R2_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F11R2_FB11 CAN_F11R2_FB11_Msk /*!< Filter bit 11 */
+#define CAN_F11R2_FB12_Pos (12U)
+#define CAN_F11R2_FB12_Msk (0x1U << CAN_F11R2_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F11R2_FB12 CAN_F11R2_FB12_Msk /*!< Filter bit 12 */
+#define CAN_F11R2_FB13_Pos (13U)
+#define CAN_F11R2_FB13_Msk (0x1U << CAN_F11R2_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F11R2_FB13 CAN_F11R2_FB13_Msk /*!< Filter bit 13 */
+#define CAN_F11R2_FB14_Pos (14U)
+#define CAN_F11R2_FB14_Msk (0x1U << CAN_F11R2_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F11R2_FB14 CAN_F11R2_FB14_Msk /*!< Filter bit 14 */
+#define CAN_F11R2_FB15_Pos (15U)
+#define CAN_F11R2_FB15_Msk (0x1U << CAN_F11R2_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F11R2_FB15 CAN_F11R2_FB15_Msk /*!< Filter bit 15 */
+#define CAN_F11R2_FB16_Pos (16U)
+#define CAN_F11R2_FB16_Msk (0x1U << CAN_F11R2_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F11R2_FB16 CAN_F11R2_FB16_Msk /*!< Filter bit 16 */
+#define CAN_F11R2_FB17_Pos (17U)
+#define CAN_F11R2_FB17_Msk (0x1U << CAN_F11R2_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F11R2_FB17 CAN_F11R2_FB17_Msk /*!< Filter bit 17 */
+#define CAN_F11R2_FB18_Pos (18U)
+#define CAN_F11R2_FB18_Msk (0x1U << CAN_F11R2_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F11R2_FB18 CAN_F11R2_FB18_Msk /*!< Filter bit 18 */
+#define CAN_F11R2_FB19_Pos (19U)
+#define CAN_F11R2_FB19_Msk (0x1U << CAN_F11R2_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F11R2_FB19 CAN_F11R2_FB19_Msk /*!< Filter bit 19 */
+#define CAN_F11R2_FB20_Pos (20U)
+#define CAN_F11R2_FB20_Msk (0x1U << CAN_F11R2_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F11R2_FB20 CAN_F11R2_FB20_Msk /*!< Filter bit 20 */
+#define CAN_F11R2_FB21_Pos (21U)
+#define CAN_F11R2_FB21_Msk (0x1U << CAN_F11R2_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F11R2_FB21 CAN_F11R2_FB21_Msk /*!< Filter bit 21 */
+#define CAN_F11R2_FB22_Pos (22U)
+#define CAN_F11R2_FB22_Msk (0x1U << CAN_F11R2_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F11R2_FB22 CAN_F11R2_FB22_Msk /*!< Filter bit 22 */
+#define CAN_F11R2_FB23_Pos (23U)
+#define CAN_F11R2_FB23_Msk (0x1U << CAN_F11R2_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F11R2_FB23 CAN_F11R2_FB23_Msk /*!< Filter bit 23 */
+#define CAN_F11R2_FB24_Pos (24U)
+#define CAN_F11R2_FB24_Msk (0x1U << CAN_F11R2_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F11R2_FB24 CAN_F11R2_FB24_Msk /*!< Filter bit 24 */
+#define CAN_F11R2_FB25_Pos (25U)
+#define CAN_F11R2_FB25_Msk (0x1U << CAN_F11R2_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F11R2_FB25 CAN_F11R2_FB25_Msk /*!< Filter bit 25 */
+#define CAN_F11R2_FB26_Pos (26U)
+#define CAN_F11R2_FB26_Msk (0x1U << CAN_F11R2_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F11R2_FB26 CAN_F11R2_FB26_Msk /*!< Filter bit 26 */
+#define CAN_F11R2_FB27_Pos (27U)
+#define CAN_F11R2_FB27_Msk (0x1U << CAN_F11R2_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F11R2_FB27 CAN_F11R2_FB27_Msk /*!< Filter bit 27 */
+#define CAN_F11R2_FB28_Pos (28U)
+#define CAN_F11R2_FB28_Msk (0x1U << CAN_F11R2_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F11R2_FB28 CAN_F11R2_FB28_Msk /*!< Filter bit 28 */
+#define CAN_F11R2_FB29_Pos (29U)
+#define CAN_F11R2_FB29_Msk (0x1U << CAN_F11R2_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F11R2_FB29 CAN_F11R2_FB29_Msk /*!< Filter bit 29 */
+#define CAN_F11R2_FB30_Pos (30U)
+#define CAN_F11R2_FB30_Msk (0x1U << CAN_F11R2_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F11R2_FB30 CAN_F11R2_FB30_Msk /*!< Filter bit 30 */
+#define CAN_F11R2_FB31_Pos (31U)
+#define CAN_F11R2_FB31_Msk (0x1U << CAN_F11R2_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F11R2_FB31 CAN_F11R2_FB31_Msk /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F12R2 register ******************/
+#define CAN_F12R2_FB0_Pos (0U)
+#define CAN_F12R2_FB0_Msk (0x1U << CAN_F12R2_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F12R2_FB0 CAN_F12R2_FB0_Msk /*!< Filter bit 0 */
+#define CAN_F12R2_FB1_Pos (1U)
+#define CAN_F12R2_FB1_Msk (0x1U << CAN_F12R2_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F12R2_FB1 CAN_F12R2_FB1_Msk /*!< Filter bit 1 */
+#define CAN_F12R2_FB2_Pos (2U)
+#define CAN_F12R2_FB2_Msk (0x1U << CAN_F12R2_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F12R2_FB2 CAN_F12R2_FB2_Msk /*!< Filter bit 2 */
+#define CAN_F12R2_FB3_Pos (3U)
+#define CAN_F12R2_FB3_Msk (0x1U << CAN_F12R2_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F12R2_FB3 CAN_F12R2_FB3_Msk /*!< Filter bit 3 */
+#define CAN_F12R2_FB4_Pos (4U)
+#define CAN_F12R2_FB4_Msk (0x1U << CAN_F12R2_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F12R2_FB4 CAN_F12R2_FB4_Msk /*!< Filter bit 4 */
+#define CAN_F12R2_FB5_Pos (5U)
+#define CAN_F12R2_FB5_Msk (0x1U << CAN_F12R2_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F12R2_FB5 CAN_F12R2_FB5_Msk /*!< Filter bit 5 */
+#define CAN_F12R2_FB6_Pos (6U)
+#define CAN_F12R2_FB6_Msk (0x1U << CAN_F12R2_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F12R2_FB6 CAN_F12R2_FB6_Msk /*!< Filter bit 6 */
+#define CAN_F12R2_FB7_Pos (7U)
+#define CAN_F12R2_FB7_Msk (0x1U << CAN_F12R2_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F12R2_FB7 CAN_F12R2_FB7_Msk /*!< Filter bit 7 */
+#define CAN_F12R2_FB8_Pos (8U)
+#define CAN_F12R2_FB8_Msk (0x1U << CAN_F12R2_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F12R2_FB8 CAN_F12R2_FB8_Msk /*!< Filter bit 8 */
+#define CAN_F12R2_FB9_Pos (9U)
+#define CAN_F12R2_FB9_Msk (0x1U << CAN_F12R2_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F12R2_FB9 CAN_F12R2_FB9_Msk /*!< Filter bit 9 */
+#define CAN_F12R2_FB10_Pos (10U)
+#define CAN_F12R2_FB10_Msk (0x1U << CAN_F12R2_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F12R2_FB10 CAN_F12R2_FB10_Msk /*!< Filter bit 10 */
+#define CAN_F12R2_FB11_Pos (11U)
+#define CAN_F12R2_FB11_Msk (0x1U << CAN_F12R2_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F12R2_FB11 CAN_F12R2_FB11_Msk /*!< Filter bit 11 */
+#define CAN_F12R2_FB12_Pos (12U)
+#define CAN_F12R2_FB12_Msk (0x1U << CAN_F12R2_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F12R2_FB12 CAN_F12R2_FB12_Msk /*!< Filter bit 12 */
+#define CAN_F12R2_FB13_Pos (13U)
+#define CAN_F12R2_FB13_Msk (0x1U << CAN_F12R2_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F12R2_FB13 CAN_F12R2_FB13_Msk /*!< Filter bit 13 */
+#define CAN_F12R2_FB14_Pos (14U)
+#define CAN_F12R2_FB14_Msk (0x1U << CAN_F12R2_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F12R2_FB14 CAN_F12R2_FB14_Msk /*!< Filter bit 14 */
+#define CAN_F12R2_FB15_Pos (15U)
+#define CAN_F12R2_FB15_Msk (0x1U << CAN_F12R2_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F12R2_FB15 CAN_F12R2_FB15_Msk /*!< Filter bit 15 */
+#define CAN_F12R2_FB16_Pos (16U)
+#define CAN_F12R2_FB16_Msk (0x1U << CAN_F12R2_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F12R2_FB16 CAN_F12R2_FB16_Msk /*!< Filter bit 16 */
+#define CAN_F12R2_FB17_Pos (17U)
+#define CAN_F12R2_FB17_Msk (0x1U << CAN_F12R2_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F12R2_FB17 CAN_F12R2_FB17_Msk /*!< Filter bit 17 */
+#define CAN_F12R2_FB18_Pos (18U)
+#define CAN_F12R2_FB18_Msk (0x1U << CAN_F12R2_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F12R2_FB18 CAN_F12R2_FB18_Msk /*!< Filter bit 18 */
+#define CAN_F12R2_FB19_Pos (19U)
+#define CAN_F12R2_FB19_Msk (0x1U << CAN_F12R2_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F12R2_FB19 CAN_F12R2_FB19_Msk /*!< Filter bit 19 */
+#define CAN_F12R2_FB20_Pos (20U)
+#define CAN_F12R2_FB20_Msk (0x1U << CAN_F12R2_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F12R2_FB20 CAN_F12R2_FB20_Msk /*!< Filter bit 20 */
+#define CAN_F12R2_FB21_Pos (21U)
+#define CAN_F12R2_FB21_Msk (0x1U << CAN_F12R2_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F12R2_FB21 CAN_F12R2_FB21_Msk /*!< Filter bit 21 */
+#define CAN_F12R2_FB22_Pos (22U)
+#define CAN_F12R2_FB22_Msk (0x1U << CAN_F12R2_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F12R2_FB22 CAN_F12R2_FB22_Msk /*!< Filter bit 22 */
+#define CAN_F12R2_FB23_Pos (23U)
+#define CAN_F12R2_FB23_Msk (0x1U << CAN_F12R2_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F12R2_FB23 CAN_F12R2_FB23_Msk /*!< Filter bit 23 */
+#define CAN_F12R2_FB24_Pos (24U)
+#define CAN_F12R2_FB24_Msk (0x1U << CAN_F12R2_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F12R2_FB24 CAN_F12R2_FB24_Msk /*!< Filter bit 24 */
+#define CAN_F12R2_FB25_Pos (25U)
+#define CAN_F12R2_FB25_Msk (0x1U << CAN_F12R2_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F12R2_FB25 CAN_F12R2_FB25_Msk /*!< Filter bit 25 */
+#define CAN_F12R2_FB26_Pos (26U)
+#define CAN_F12R2_FB26_Msk (0x1U << CAN_F12R2_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F12R2_FB26 CAN_F12R2_FB26_Msk /*!< Filter bit 26 */
+#define CAN_F12R2_FB27_Pos (27U)
+#define CAN_F12R2_FB27_Msk (0x1U << CAN_F12R2_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F12R2_FB27 CAN_F12R2_FB27_Msk /*!< Filter bit 27 */
+#define CAN_F12R2_FB28_Pos (28U)
+#define CAN_F12R2_FB28_Msk (0x1U << CAN_F12R2_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F12R2_FB28 CAN_F12R2_FB28_Msk /*!< Filter bit 28 */
+#define CAN_F12R2_FB29_Pos (29U)
+#define CAN_F12R2_FB29_Msk (0x1U << CAN_F12R2_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F12R2_FB29 CAN_F12R2_FB29_Msk /*!< Filter bit 29 */
+#define CAN_F12R2_FB30_Pos (30U)
+#define CAN_F12R2_FB30_Msk (0x1U << CAN_F12R2_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F12R2_FB30 CAN_F12R2_FB30_Msk /*!< Filter bit 30 */
+#define CAN_F12R2_FB31_Pos (31U)
+#define CAN_F12R2_FB31_Msk (0x1U << CAN_F12R2_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F12R2_FB31 CAN_F12R2_FB31_Msk /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F13R2 register ******************/
+#define CAN_F13R2_FB0_Pos (0U)
+#define CAN_F13R2_FB0_Msk (0x1U << CAN_F13R2_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F13R2_FB0 CAN_F13R2_FB0_Msk /*!< Filter bit 0 */
+#define CAN_F13R2_FB1_Pos (1U)
+#define CAN_F13R2_FB1_Msk (0x1U << CAN_F13R2_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F13R2_FB1 CAN_F13R2_FB1_Msk /*!< Filter bit 1 */
+#define CAN_F13R2_FB2_Pos (2U)
+#define CAN_F13R2_FB2_Msk (0x1U << CAN_F13R2_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F13R2_FB2 CAN_F13R2_FB2_Msk /*!< Filter bit 2 */
+#define CAN_F13R2_FB3_Pos (3U)
+#define CAN_F13R2_FB3_Msk (0x1U << CAN_F13R2_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F13R2_FB3 CAN_F13R2_FB3_Msk /*!< Filter bit 3 */
+#define CAN_F13R2_FB4_Pos (4U)
+#define CAN_F13R2_FB4_Msk (0x1U << CAN_F13R2_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F13R2_FB4 CAN_F13R2_FB4_Msk /*!< Filter bit 4 */
+#define CAN_F13R2_FB5_Pos (5U)
+#define CAN_F13R2_FB5_Msk (0x1U << CAN_F13R2_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F13R2_FB5 CAN_F13R2_FB5_Msk /*!< Filter bit 5 */
+#define CAN_F13R2_FB6_Pos (6U)
+#define CAN_F13R2_FB6_Msk (0x1U << CAN_F13R2_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F13R2_FB6 CAN_F13R2_FB6_Msk /*!< Filter bit 6 */
+#define CAN_F13R2_FB7_Pos (7U)
+#define CAN_F13R2_FB7_Msk (0x1U << CAN_F13R2_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F13R2_FB7 CAN_F13R2_FB7_Msk /*!< Filter bit 7 */
+#define CAN_F13R2_FB8_Pos (8U)
+#define CAN_F13R2_FB8_Msk (0x1U << CAN_F13R2_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F13R2_FB8 CAN_F13R2_FB8_Msk /*!< Filter bit 8 */
+#define CAN_F13R2_FB9_Pos (9U)
+#define CAN_F13R2_FB9_Msk (0x1U << CAN_F13R2_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F13R2_FB9 CAN_F13R2_FB9_Msk /*!< Filter bit 9 */
+#define CAN_F13R2_FB10_Pos (10U)
+#define CAN_F13R2_FB10_Msk (0x1U << CAN_F13R2_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F13R2_FB10 CAN_F13R2_FB10_Msk /*!< Filter bit 10 */
+#define CAN_F13R2_FB11_Pos (11U)
+#define CAN_F13R2_FB11_Msk (0x1U << CAN_F13R2_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F13R2_FB11 CAN_F13R2_FB11_Msk /*!< Filter bit 11 */
+#define CAN_F13R2_FB12_Pos (12U)
+#define CAN_F13R2_FB12_Msk (0x1U << CAN_F13R2_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F13R2_FB12 CAN_F13R2_FB12_Msk /*!< Filter bit 12 */
+#define CAN_F13R2_FB13_Pos (13U)
+#define CAN_F13R2_FB13_Msk (0x1U << CAN_F13R2_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F13R2_FB13 CAN_F13R2_FB13_Msk /*!< Filter bit 13 */
+#define CAN_F13R2_FB14_Pos (14U)
+#define CAN_F13R2_FB14_Msk (0x1U << CAN_F13R2_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F13R2_FB14 CAN_F13R2_FB14_Msk /*!< Filter bit 14 */
+#define CAN_F13R2_FB15_Pos (15U)
+#define CAN_F13R2_FB15_Msk (0x1U << CAN_F13R2_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F13R2_FB15 CAN_F13R2_FB15_Msk /*!< Filter bit 15 */
+#define CAN_F13R2_FB16_Pos (16U)
+#define CAN_F13R2_FB16_Msk (0x1U << CAN_F13R2_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F13R2_FB16 CAN_F13R2_FB16_Msk /*!< Filter bit 16 */
+#define CAN_F13R2_FB17_Pos (17U)
+#define CAN_F13R2_FB17_Msk (0x1U << CAN_F13R2_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F13R2_FB17 CAN_F13R2_FB17_Msk /*!< Filter bit 17 */
+#define CAN_F13R2_FB18_Pos (18U)
+#define CAN_F13R2_FB18_Msk (0x1U << CAN_F13R2_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F13R2_FB18 CAN_F13R2_FB18_Msk /*!< Filter bit 18 */
+#define CAN_F13R2_FB19_Pos (19U)
+#define CAN_F13R2_FB19_Msk (0x1U << CAN_F13R2_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F13R2_FB19 CAN_F13R2_FB19_Msk /*!< Filter bit 19 */
+#define CAN_F13R2_FB20_Pos (20U)
+#define CAN_F13R2_FB20_Msk (0x1U << CAN_F13R2_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F13R2_FB20 CAN_F13R2_FB20_Msk /*!< Filter bit 20 */
+#define CAN_F13R2_FB21_Pos (21U)
+#define CAN_F13R2_FB21_Msk (0x1U << CAN_F13R2_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F13R2_FB21 CAN_F13R2_FB21_Msk /*!< Filter bit 21 */
+#define CAN_F13R2_FB22_Pos (22U)
+#define CAN_F13R2_FB22_Msk (0x1U << CAN_F13R2_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F13R2_FB22 CAN_F13R2_FB22_Msk /*!< Filter bit 22 */
+#define CAN_F13R2_FB23_Pos (23U)
+#define CAN_F13R2_FB23_Msk (0x1U << CAN_F13R2_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F13R2_FB23 CAN_F13R2_FB23_Msk /*!< Filter bit 23 */
+#define CAN_F13R2_FB24_Pos (24U)
+#define CAN_F13R2_FB24_Msk (0x1U << CAN_F13R2_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F13R2_FB24 CAN_F13R2_FB24_Msk /*!< Filter bit 24 */
+#define CAN_F13R2_FB25_Pos (25U)
+#define CAN_F13R2_FB25_Msk (0x1U << CAN_F13R2_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F13R2_FB25 CAN_F13R2_FB25_Msk /*!< Filter bit 25 */
+#define CAN_F13R2_FB26_Pos (26U)
+#define CAN_F13R2_FB26_Msk (0x1U << CAN_F13R2_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F13R2_FB26 CAN_F13R2_FB26_Msk /*!< Filter bit 26 */
+#define CAN_F13R2_FB27_Pos (27U)
+#define CAN_F13R2_FB27_Msk (0x1U << CAN_F13R2_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F13R2_FB27 CAN_F13R2_FB27_Msk /*!< Filter bit 27 */
+#define CAN_F13R2_FB28_Pos (28U)
+#define CAN_F13R2_FB28_Msk (0x1U << CAN_F13R2_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F13R2_FB28 CAN_F13R2_FB28_Msk /*!< Filter bit 28 */
+#define CAN_F13R2_FB29_Pos (29U)
+#define CAN_F13R2_FB29_Msk (0x1U << CAN_F13R2_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F13R2_FB29 CAN_F13R2_FB29_Msk /*!< Filter bit 29 */
+#define CAN_F13R2_FB30_Pos (30U)
+#define CAN_F13R2_FB30_Msk (0x1U << CAN_F13R2_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F13R2_FB30 CAN_F13R2_FB30_Msk /*!< Filter bit 30 */
+#define CAN_F13R2_FB31_Pos (31U)
+#define CAN_F13R2_FB31_Msk (0x1U << CAN_F13R2_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F13R2_FB31 CAN_F13R2_FB31_Msk /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F14R2 register ******************/
+#define CAN_F14R2_FB0_Pos (0U)
+#define CAN_F14R2_FB0_Msk (0x1U << CAN_F14R2_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F14R2_FB0 CAN_F14R2_FB0_Msk /*!< Filter bit 0 */
+#define CAN_F14R2_FB1_Pos (1U)
+#define CAN_F14R2_FB1_Msk (0x1U << CAN_F14R2_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F14R2_FB1 CAN_F14R2_FB1_Msk /*!< Filter bit 1 */
+#define CAN_F14R2_FB2_Pos (2U)
+#define CAN_F14R2_FB2_Msk (0x1U << CAN_F14R2_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F14R2_FB2 CAN_F14R2_FB2_Msk /*!< Filter bit 2 */
+#define CAN_F14R2_FB3_Pos (3U)
+#define CAN_F14R2_FB3_Msk (0x1U << CAN_F14R2_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F14R2_FB3 CAN_F14R2_FB3_Msk /*!< Filter bit 3 */
+#define CAN_F14R2_FB4_Pos (4U)
+#define CAN_F14R2_FB4_Msk (0x1U << CAN_F14R2_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F14R2_FB4 CAN_F14R2_FB4_Msk /*!< Filter bit 4 */
+#define CAN_F14R2_FB5_Pos (5U)
+#define CAN_F14R2_FB5_Msk (0x1U << CAN_F14R2_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F14R2_FB5 CAN_F14R2_FB5_Msk /*!< Filter bit 5 */
+#define CAN_F14R2_FB6_Pos (6U)
+#define CAN_F14R2_FB6_Msk (0x1U << CAN_F14R2_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F14R2_FB6 CAN_F14R2_FB6_Msk /*!< Filter bit 6 */
+#define CAN_F14R2_FB7_Pos (7U)
+#define CAN_F14R2_FB7_Msk (0x1U << CAN_F14R2_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F14R2_FB7 CAN_F14R2_FB7_Msk /*!< Filter bit 7 */
+#define CAN_F14R2_FB8_Pos (8U)
+#define CAN_F14R2_FB8_Msk (0x1U << CAN_F14R2_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F14R2_FB8 CAN_F14R2_FB8_Msk /*!< Filter bit 8 */
+#define CAN_F14R2_FB9_Pos (9U)
+#define CAN_F14R2_FB9_Msk (0x1U << CAN_F14R2_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F14R2_FB9 CAN_F14R2_FB9_Msk /*!< Filter bit 9 */
+#define CAN_F14R2_FB10_Pos (10U)
+#define CAN_F14R2_FB10_Msk (0x1U << CAN_F14R2_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F14R2_FB10 CAN_F14R2_FB10_Msk /*!< Filter bit 10 */
+#define CAN_F14R2_FB11_Pos (11U)
+#define CAN_F14R2_FB11_Msk (0x1U << CAN_F14R2_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F14R2_FB11 CAN_F14R2_FB11_Msk /*!< Filter bit 11 */
+#define CAN_F14R2_FB12_Pos (12U)
+#define CAN_F14R2_FB12_Msk (0x1U << CAN_F14R2_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F14R2_FB12 CAN_F14R2_FB12_Msk /*!< Filter bit 12 */
+#define CAN_F14R2_FB13_Pos (13U)
+#define CAN_F14R2_FB13_Msk (0x1U << CAN_F14R2_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F14R2_FB13 CAN_F14R2_FB13_Msk /*!< Filter bit 13 */
+#define CAN_F14R2_FB14_Pos (14U)
+#define CAN_F14R2_FB14_Msk (0x1U << CAN_F14R2_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F14R2_FB14 CAN_F14R2_FB14_Msk /*!< Filter bit 14 */
+#define CAN_F14R2_FB15_Pos (15U)
+#define CAN_F14R2_FB15_Msk (0x1U << CAN_F14R2_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F14R2_FB15 CAN_F14R2_FB15_Msk /*!< Filter bit 15 */
+#define CAN_F14R2_FB16_Pos (16U)
+#define CAN_F14R2_FB16_Msk (0x1U << CAN_F14R2_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F14R2_FB16 CAN_F14R2_FB16_Msk /*!< Filter bit 16 */
+#define CAN_F14R2_FB17_Pos (17U)
+#define CAN_F14R2_FB17_Msk (0x1U << CAN_F14R2_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F14R2_FB17 CAN_F14R2_FB17_Msk /*!< Filter bit 17 */
+#define CAN_F14R2_FB18_Pos (18U)
+#define CAN_F14R2_FB18_Msk (0x1U << CAN_F14R2_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F14R2_FB18 CAN_F14R2_FB18_Msk /*!< Filter bit 18 */
+#define CAN_F14R2_FB19_Pos (19U)
+#define CAN_F14R2_FB19_Msk (0x1U << CAN_F14R2_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F14R2_FB19 CAN_F14R2_FB19_Msk /*!< Filter bit 19 */
+#define CAN_F14R2_FB20_Pos (20U)
+#define CAN_F14R2_FB20_Msk (0x1U << CAN_F14R2_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F14R2_FB20 CAN_F14R2_FB20_Msk /*!< Filter bit 20 */
+#define CAN_F14R2_FB21_Pos (21U)
+#define CAN_F14R2_FB21_Msk (0x1U << CAN_F14R2_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F14R2_FB21 CAN_F14R2_FB21_Msk /*!< Filter bit 21 */
+#define CAN_F14R2_FB22_Pos (22U)
+#define CAN_F14R2_FB22_Msk (0x1U << CAN_F14R2_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F14R2_FB22 CAN_F14R2_FB22_Msk /*!< Filter bit 22 */
+#define CAN_F14R2_FB23_Pos (23U)
+#define CAN_F14R2_FB23_Msk (0x1U << CAN_F14R2_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F14R2_FB23 CAN_F14R2_FB23_Msk /*!< Filter bit 23 */
+#define CAN_F14R2_FB24_Pos (24U)
+#define CAN_F14R2_FB24_Msk (0x1U << CAN_F14R2_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F14R2_FB24 CAN_F14R2_FB24_Msk /*!< Filter bit 24 */
+#define CAN_F14R2_FB25_Pos (25U)
+#define CAN_F14R2_FB25_Msk (0x1U << CAN_F14R2_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F14R2_FB25 CAN_F14R2_FB25_Msk /*!< Filter bit 25 */
+#define CAN_F14R2_FB26_Pos (26U)
+#define CAN_F14R2_FB26_Msk (0x1U << CAN_F14R2_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F14R2_FB26 CAN_F14R2_FB26_Msk /*!< Filter bit 26 */
+#define CAN_F14R2_FB27_Pos (27U)
+#define CAN_F14R2_FB27_Msk (0x1U << CAN_F14R2_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F14R2_FB27 CAN_F14R2_FB27_Msk /*!< Filter bit 27 */
+#define CAN_F14R2_FB28_Pos (28U)
+#define CAN_F14R2_FB28_Msk (0x1U << CAN_F14R2_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F14R2_FB28 CAN_F14R2_FB28_Msk /*!< Filter bit 28 */
+#define CAN_F14R2_FB29_Pos (29U)
+#define CAN_F14R2_FB29_Msk (0x1U << CAN_F14R2_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F14R2_FB29 CAN_F14R2_FB29_Msk /*!< Filter bit 29 */
+#define CAN_F14R2_FB30_Pos (30U)
+#define CAN_F14R2_FB30_Msk (0x1U << CAN_F14R2_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F14R2_FB30 CAN_F14R2_FB30_Msk /*!< Filter bit 30 */
+#define CAN_F14R2_FB31_Pos (31U)
+#define CAN_F14R2_FB31_Msk (0x1U << CAN_F14R2_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F14R2_FB31 CAN_F14R2_FB31_Msk /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F15R2 register ******************/
+#define CAN_F15R2_FB0_Pos (0U)
+#define CAN_F15R2_FB0_Msk (0x1U << CAN_F15R2_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F15R2_FB0 CAN_F15R2_FB0_Msk /*!< Filter bit 0 */
+#define CAN_F15R2_FB1_Pos (1U)
+#define CAN_F15R2_FB1_Msk (0x1U << CAN_F15R2_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F15R2_FB1 CAN_F15R2_FB1_Msk /*!< Filter bit 1 */
+#define CAN_F15R2_FB2_Pos (2U)
+#define CAN_F15R2_FB2_Msk (0x1U << CAN_F15R2_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F15R2_FB2 CAN_F15R2_FB2_Msk /*!< Filter bit 2 */
+#define CAN_F15R2_FB3_Pos (3U)
+#define CAN_F15R2_FB3_Msk (0x1U << CAN_F15R2_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F15R2_FB3 CAN_F15R2_FB3_Msk /*!< Filter bit 3 */
+#define CAN_F15R2_FB4_Pos (4U)
+#define CAN_F15R2_FB4_Msk (0x1U << CAN_F15R2_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F15R2_FB4 CAN_F15R2_FB4_Msk /*!< Filter bit 4 */
+#define CAN_F15R2_FB5_Pos (5U)
+#define CAN_F15R2_FB5_Msk (0x1U << CAN_F15R2_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F15R2_FB5 CAN_F15R2_FB5_Msk /*!< Filter bit 5 */
+#define CAN_F15R2_FB6_Pos (6U)
+#define CAN_F15R2_FB6_Msk (0x1U << CAN_F15R2_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F15R2_FB6 CAN_F15R2_FB6_Msk /*!< Filter bit 6 */
+#define CAN_F15R2_FB7_Pos (7U)
+#define CAN_F15R2_FB7_Msk (0x1U << CAN_F15R2_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F15R2_FB7 CAN_F15R2_FB7_Msk /*!< Filter bit 7 */
+#define CAN_F15R2_FB8_Pos (8U)
+#define CAN_F15R2_FB8_Msk (0x1U << CAN_F15R2_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F15R2_FB8 CAN_F15R2_FB8_Msk /*!< Filter bit 8 */
+#define CAN_F15R2_FB9_Pos (9U)
+#define CAN_F15R2_FB9_Msk (0x1U << CAN_F15R2_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F15R2_FB9 CAN_F15R2_FB9_Msk /*!< Filter bit 9 */
+#define CAN_F15R2_FB10_Pos (10U)
+#define CAN_F15R2_FB10_Msk (0x1U << CAN_F15R2_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F15R2_FB10 CAN_F15R2_FB10_Msk /*!< Filter bit 10 */
+#define CAN_F15R2_FB11_Pos (11U)
+#define CAN_F15R2_FB11_Msk (0x1U << CAN_F15R2_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F15R2_FB11 CAN_F15R2_FB11_Msk /*!< Filter bit 11 */
+#define CAN_F15R2_FB12_Pos (12U)
+#define CAN_F15R2_FB12_Msk (0x1U << CAN_F15R2_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F15R2_FB12 CAN_F15R2_FB12_Msk /*!< Filter bit 12 */
+#define CAN_F15R2_FB13_Pos (13U)
+#define CAN_F15R2_FB13_Msk (0x1U << CAN_F15R2_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F15R2_FB13 CAN_F15R2_FB13_Msk /*!< Filter bit 13 */
+#define CAN_F15R2_FB14_Pos (14U)
+#define CAN_F15R2_FB14_Msk (0x1U << CAN_F15R2_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F15R2_FB14 CAN_F15R2_FB14_Msk /*!< Filter bit 14 */
+#define CAN_F15R2_FB15_Pos (15U)
+#define CAN_F15R2_FB15_Msk (0x1U << CAN_F15R2_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F15R2_FB15 CAN_F15R2_FB15_Msk /*!< Filter bit 15 */
+#define CAN_F15R2_FB16_Pos (16U)
+#define CAN_F15R2_FB16_Msk (0x1U << CAN_F15R2_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F15R2_FB16 CAN_F15R2_FB16_Msk /*!< Filter bit 16 */
+#define CAN_F15R2_FB17_Pos (17U)
+#define CAN_F15R2_FB17_Msk (0x1U << CAN_F15R2_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F15R2_FB17 CAN_F15R2_FB17_Msk /*!< Filter bit 17 */
+#define CAN_F15R2_FB18_Pos (18U)
+#define CAN_F15R2_FB18_Msk (0x1U << CAN_F15R2_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F15R2_FB18 CAN_F15R2_FB18_Msk /*!< Filter bit 18 */
+#define CAN_F15R2_FB19_Pos (19U)
+#define CAN_F15R2_FB19_Msk (0x1U << CAN_F15R2_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F15R2_FB19 CAN_F15R2_FB19_Msk /*!< Filter bit 19 */
+#define CAN_F15R2_FB20_Pos (20U)
+#define CAN_F15R2_FB20_Msk (0x1U << CAN_F15R2_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F15R2_FB20 CAN_F15R2_FB20_Msk /*!< Filter bit 20 */
+#define CAN_F15R2_FB21_Pos (21U)
+#define CAN_F15R2_FB21_Msk (0x1U << CAN_F15R2_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F15R2_FB21 CAN_F15R2_FB21_Msk /*!< Filter bit 21 */
+#define CAN_F15R2_FB22_Pos (22U)
+#define CAN_F15R2_FB22_Msk (0x1U << CAN_F15R2_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F15R2_FB22 CAN_F15R2_FB22_Msk /*!< Filter bit 22 */
+#define CAN_F15R2_FB23_Pos (23U)
+#define CAN_F15R2_FB23_Msk (0x1U << CAN_F15R2_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F15R2_FB23 CAN_F15R2_FB23_Msk /*!< Filter bit 23 */
+#define CAN_F15R2_FB24_Pos (24U)
+#define CAN_F15R2_FB24_Msk (0x1U << CAN_F15R2_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F15R2_FB24 CAN_F15R2_FB24_Msk /*!< Filter bit 24 */
+#define CAN_F15R2_FB25_Pos (25U)
+#define CAN_F15R2_FB25_Msk (0x1U << CAN_F15R2_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F15R2_FB25 CAN_F15R2_FB25_Msk /*!< Filter bit 25 */
+#define CAN_F15R2_FB26_Pos (26U)
+#define CAN_F15R2_FB26_Msk (0x1U << CAN_F15R2_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F15R2_FB26 CAN_F15R2_FB26_Msk /*!< Filter bit 26 */
+#define CAN_F15R2_FB27_Pos (27U)
+#define CAN_F15R2_FB27_Msk (0x1U << CAN_F15R2_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F15R2_FB27 CAN_F15R2_FB27_Msk /*!< Filter bit 27 */
+#define CAN_F15R2_FB28_Pos (28U)
+#define CAN_F15R2_FB28_Msk (0x1U << CAN_F15R2_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F15R2_FB28 CAN_F15R2_FB28_Msk /*!< Filter bit 28 */
+#define CAN_F15R2_FB29_Pos (29U)
+#define CAN_F15R2_FB29_Msk (0x1U << CAN_F15R2_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F15R2_FB29 CAN_F15R2_FB29_Msk /*!< Filter bit 29 */
+#define CAN_F15R2_FB30_Pos (30U)
+#define CAN_F15R2_FB30_Msk (0x1U << CAN_F15R2_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F15R2_FB30 CAN_F15R2_FB30_Msk /*!< Filter bit 30 */
+#define CAN_F15R2_FB31_Pos (31U)
+#define CAN_F15R2_FB31_Msk (0x1U << CAN_F15R2_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F15R2_FB31 CAN_F15R2_FB31_Msk /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F16R2 register ******************/
+#define CAN_F16R2_FB0_Pos (0U)
+#define CAN_F16R2_FB0_Msk (0x1U << CAN_F16R2_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F16R2_FB0 CAN_F16R2_FB0_Msk /*!< Filter bit 0 */
+#define CAN_F16R2_FB1_Pos (1U)
+#define CAN_F16R2_FB1_Msk (0x1U << CAN_F16R2_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F16R2_FB1 CAN_F16R2_FB1_Msk /*!< Filter bit 1 */
+#define CAN_F16R2_FB2_Pos (2U)
+#define CAN_F16R2_FB2_Msk (0x1U << CAN_F16R2_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F16R2_FB2 CAN_F16R2_FB2_Msk /*!< Filter bit 2 */
+#define CAN_F16R2_FB3_Pos (3U)
+#define CAN_F16R2_FB3_Msk (0x1U << CAN_F16R2_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F16R2_FB3 CAN_F16R2_FB3_Msk /*!< Filter bit 3 */
+#define CAN_F16R2_FB4_Pos (4U)
+#define CAN_F16R2_FB4_Msk (0x1U << CAN_F16R2_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F16R2_FB4 CAN_F16R2_FB4_Msk /*!< Filter bit 4 */
+#define CAN_F16R2_FB5_Pos (5U)
+#define CAN_F16R2_FB5_Msk (0x1U << CAN_F16R2_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F16R2_FB5 CAN_F16R2_FB5_Msk /*!< Filter bit 5 */
+#define CAN_F16R2_FB6_Pos (6U)
+#define CAN_F16R2_FB6_Msk (0x1U << CAN_F16R2_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F16R2_FB6 CAN_F16R2_FB6_Msk /*!< Filter bit 6 */
+#define CAN_F16R2_FB7_Pos (7U)
+#define CAN_F16R2_FB7_Msk (0x1U << CAN_F16R2_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F16R2_FB7 CAN_F16R2_FB7_Msk /*!< Filter bit 7 */
+#define CAN_F16R2_FB8_Pos (8U)
+#define CAN_F16R2_FB8_Msk (0x1U << CAN_F16R2_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F16R2_FB8 CAN_F16R2_FB8_Msk /*!< Filter bit 8 */
+#define CAN_F16R2_FB9_Pos (9U)
+#define CAN_F16R2_FB9_Msk (0x1U << CAN_F16R2_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F16R2_FB9 CAN_F16R2_FB9_Msk /*!< Filter bit 9 */
+#define CAN_F16R2_FB10_Pos (10U)
+#define CAN_F16R2_FB10_Msk (0x1U << CAN_F16R2_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F16R2_FB10 CAN_F16R2_FB10_Msk /*!< Filter bit 10 */
+#define CAN_F16R2_FB11_Pos (11U)
+#define CAN_F16R2_FB11_Msk (0x1U << CAN_F16R2_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F16R2_FB11 CAN_F16R2_FB11_Msk /*!< Filter bit 11 */
+#define CAN_F16R2_FB12_Pos (12U)
+#define CAN_F16R2_FB12_Msk (0x1U << CAN_F16R2_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F16R2_FB12 CAN_F16R2_FB12_Msk /*!< Filter bit 12 */
+#define CAN_F16R2_FB13_Pos (13U)
+#define CAN_F16R2_FB13_Msk (0x1U << CAN_F16R2_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F16R2_FB13 CAN_F16R2_FB13_Msk /*!< Filter bit 13 */
+#define CAN_F16R2_FB14_Pos (14U)
+#define CAN_F16R2_FB14_Msk (0x1U << CAN_F16R2_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F16R2_FB14 CAN_F16R2_FB14_Msk /*!< Filter bit 14 */
+#define CAN_F16R2_FB15_Pos (15U)
+#define CAN_F16R2_FB15_Msk (0x1U << CAN_F16R2_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F16R2_FB15 CAN_F16R2_FB15_Msk /*!< Filter bit 15 */
+#define CAN_F16R2_FB16_Pos (16U)
+#define CAN_F16R2_FB16_Msk (0x1U << CAN_F16R2_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F16R2_FB16 CAN_F16R2_FB16_Msk /*!< Filter bit 16 */
+#define CAN_F16R2_FB17_Pos (17U)
+#define CAN_F16R2_FB17_Msk (0x1U << CAN_F16R2_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F16R2_FB17 CAN_F16R2_FB17_Msk /*!< Filter bit 17 */
+#define CAN_F16R2_FB18_Pos (18U)
+#define CAN_F16R2_FB18_Msk (0x1U << CAN_F16R2_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F16R2_FB18 CAN_F16R2_FB18_Msk /*!< Filter bit 18 */
+#define CAN_F16R2_FB19_Pos (19U)
+#define CAN_F16R2_FB19_Msk (0x1U << CAN_F16R2_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F16R2_FB19 CAN_F16R2_FB19_Msk /*!< Filter bit 19 */
+#define CAN_F16R2_FB20_Pos (20U)
+#define CAN_F16R2_FB20_Msk (0x1U << CAN_F16R2_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F16R2_FB20 CAN_F16R2_FB20_Msk /*!< Filter bit 20 */
+#define CAN_F16R2_FB21_Pos (21U)
+#define CAN_F16R2_FB21_Msk (0x1U << CAN_F16R2_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F16R2_FB21 CAN_F16R2_FB21_Msk /*!< Filter bit 21 */
+#define CAN_F16R2_FB22_Pos (22U)
+#define CAN_F16R2_FB22_Msk (0x1U << CAN_F16R2_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F16R2_FB22 CAN_F16R2_FB22_Msk /*!< Filter bit 22 */
+#define CAN_F16R2_FB23_Pos (23U)
+#define CAN_F16R2_FB23_Msk (0x1U << CAN_F16R2_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F16R2_FB23 CAN_F16R2_FB23_Msk /*!< Filter bit 23 */
+#define CAN_F16R2_FB24_Pos (24U)
+#define CAN_F16R2_FB24_Msk (0x1U << CAN_F16R2_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F16R2_FB24 CAN_F16R2_FB24_Msk /*!< Filter bit 24 */
+#define CAN_F16R2_FB25_Pos (25U)
+#define CAN_F16R2_FB25_Msk (0x1U << CAN_F16R2_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F16R2_FB25 CAN_F16R2_FB25_Msk /*!< Filter bit 25 */
+#define CAN_F16R2_FB26_Pos (26U)
+#define CAN_F16R2_FB26_Msk (0x1U << CAN_F16R2_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F16R2_FB26 CAN_F16R2_FB26_Msk /*!< Filter bit 26 */
+#define CAN_F16R2_FB27_Pos (27U)
+#define CAN_F16R2_FB27_Msk (0x1U << CAN_F16R2_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F16R2_FB27 CAN_F16R2_FB27_Msk /*!< Filter bit 27 */
+#define CAN_F16R2_FB28_Pos (28U)
+#define CAN_F16R2_FB28_Msk (0x1U << CAN_F16R2_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F16R2_FB28 CAN_F16R2_FB28_Msk /*!< Filter bit 28 */
+#define CAN_F16R2_FB29_Pos (29U)
+#define CAN_F16R2_FB29_Msk (0x1U << CAN_F16R2_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F16R2_FB29 CAN_F16R2_FB29_Msk /*!< Filter bit 29 */
+#define CAN_F16R2_FB30_Pos (30U)
+#define CAN_F16R2_FB30_Msk (0x1U << CAN_F16R2_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F16R2_FB30 CAN_F16R2_FB30_Msk /*!< Filter bit 30 */
+#define CAN_F16R2_FB31_Pos (31U)
+#define CAN_F16R2_FB31_Msk (0x1U << CAN_F16R2_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F16R2_FB31 CAN_F16R2_FB31_Msk /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F17R2 register ******************/
+#define CAN_F17R2_FB0_Pos (0U)
+#define CAN_F17R2_FB0_Msk (0x1U << CAN_F17R2_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F17R2_FB0 CAN_F17R2_FB0_Msk /*!< Filter bit 0 */
+#define CAN_F17R2_FB1_Pos (1U)
+#define CAN_F17R2_FB1_Msk (0x1U << CAN_F17R2_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F17R2_FB1 CAN_F17R2_FB1_Msk /*!< Filter bit 1 */
+#define CAN_F17R2_FB2_Pos (2U)
+#define CAN_F17R2_FB2_Msk (0x1U << CAN_F17R2_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F17R2_FB2 CAN_F17R2_FB2_Msk /*!< Filter bit 2 */
+#define CAN_F17R2_FB3_Pos (3U)
+#define CAN_F17R2_FB3_Msk (0x1U << CAN_F17R2_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F17R2_FB3 CAN_F17R2_FB3_Msk /*!< Filter bit 3 */
+#define CAN_F17R2_FB4_Pos (4U)
+#define CAN_F17R2_FB4_Msk (0x1U << CAN_F17R2_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F17R2_FB4 CAN_F17R2_FB4_Msk /*!< Filter bit 4 */
+#define CAN_F17R2_FB5_Pos (5U)
+#define CAN_F17R2_FB5_Msk (0x1U << CAN_F17R2_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F17R2_FB5 CAN_F17R2_FB5_Msk /*!< Filter bit 5 */
+#define CAN_F17R2_FB6_Pos (6U)
+#define CAN_F17R2_FB6_Msk (0x1U << CAN_F17R2_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F17R2_FB6 CAN_F17R2_FB6_Msk /*!< Filter bit 6 */
+#define CAN_F17R2_FB7_Pos (7U)
+#define CAN_F17R2_FB7_Msk (0x1U << CAN_F17R2_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F17R2_FB7 CAN_F17R2_FB7_Msk /*!< Filter bit 7 */
+#define CAN_F17R2_FB8_Pos (8U)
+#define CAN_F17R2_FB8_Msk (0x1U << CAN_F17R2_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F17R2_FB8 CAN_F17R2_FB8_Msk /*!< Filter bit 8 */
+#define CAN_F17R2_FB9_Pos (9U)
+#define CAN_F17R2_FB9_Msk (0x1U << CAN_F17R2_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F17R2_FB9 CAN_F17R2_FB9_Msk /*!< Filter bit 9 */
+#define CAN_F17R2_FB10_Pos (10U)
+#define CAN_F17R2_FB10_Msk (0x1U << CAN_F17R2_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F17R2_FB10 CAN_F17R2_FB10_Msk /*!< Filter bit 10 */
+#define CAN_F17R2_FB11_Pos (11U)
+#define CAN_F17R2_FB11_Msk (0x1U << CAN_F17R2_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F17R2_FB11 CAN_F17R2_FB11_Msk /*!< Filter bit 11 */
+#define CAN_F17R2_FB12_Pos (12U)
+#define CAN_F17R2_FB12_Msk (0x1U << CAN_F17R2_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F17R2_FB12 CAN_F17R2_FB12_Msk /*!< Filter bit 12 */
+#define CAN_F17R2_FB13_Pos (13U)
+#define CAN_F17R2_FB13_Msk (0x1U << CAN_F17R2_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F17R2_FB13 CAN_F17R2_FB13_Msk /*!< Filter bit 13 */
+#define CAN_F17R2_FB14_Pos (14U)
+#define CAN_F17R2_FB14_Msk (0x1U << CAN_F17R2_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F17R2_FB14 CAN_F17R2_FB14_Msk /*!< Filter bit 14 */
+#define CAN_F17R2_FB15_Pos (15U)
+#define CAN_F17R2_FB15_Msk (0x1U << CAN_F17R2_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F17R2_FB15 CAN_F17R2_FB15_Msk /*!< Filter bit 15 */
+#define CAN_F17R2_FB16_Pos (16U)
+#define CAN_F17R2_FB16_Msk (0x1U << CAN_F17R2_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F17R2_FB16 CAN_F17R2_FB16_Msk /*!< Filter bit 16 */
+#define CAN_F17R2_FB17_Pos (17U)
+#define CAN_F17R2_FB17_Msk (0x1U << CAN_F17R2_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F17R2_FB17 CAN_F17R2_FB17_Msk /*!< Filter bit 17 */
+#define CAN_F17R2_FB18_Pos (18U)
+#define CAN_F17R2_FB18_Msk (0x1U << CAN_F17R2_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F17R2_FB18 CAN_F17R2_FB18_Msk /*!< Filter bit 18 */
+#define CAN_F17R2_FB19_Pos (19U)
+#define CAN_F17R2_FB19_Msk (0x1U << CAN_F17R2_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F17R2_FB19 CAN_F17R2_FB19_Msk /*!< Filter bit 19 */
+#define CAN_F17R2_FB20_Pos (20U)
+#define CAN_F17R2_FB20_Msk (0x1U << CAN_F17R2_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F17R2_FB20 CAN_F17R2_FB20_Msk /*!< Filter bit 20 */
+#define CAN_F17R2_FB21_Pos (21U)
+#define CAN_F17R2_FB21_Msk (0x1U << CAN_F17R2_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F17R2_FB21 CAN_F17R2_FB21_Msk /*!< Filter bit 21 */
+#define CAN_F17R2_FB22_Pos (22U)
+#define CAN_F17R2_FB22_Msk (0x1U << CAN_F17R2_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F17R2_FB22 CAN_F17R2_FB22_Msk /*!< Filter bit 22 */
+#define CAN_F17R2_FB23_Pos (23U)
+#define CAN_F17R2_FB23_Msk (0x1U << CAN_F17R2_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F17R2_FB23 CAN_F17R2_FB23_Msk /*!< Filter bit 23 */
+#define CAN_F17R2_FB24_Pos (24U)
+#define CAN_F17R2_FB24_Msk (0x1U << CAN_F17R2_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F17R2_FB24 CAN_F17R2_FB24_Msk /*!< Filter bit 24 */
+#define CAN_F17R2_FB25_Pos (25U)
+#define CAN_F17R2_FB25_Msk (0x1U << CAN_F17R2_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F17R2_FB25 CAN_F17R2_FB25_Msk /*!< Filter bit 25 */
+#define CAN_F17R2_FB26_Pos (26U)
+#define CAN_F17R2_FB26_Msk (0x1U << CAN_F17R2_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F17R2_FB26 CAN_F17R2_FB26_Msk /*!< Filter bit 26 */
+#define CAN_F17R2_FB27_Pos (27U)
+#define CAN_F17R2_FB27_Msk (0x1U << CAN_F17R2_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F17R2_FB27 CAN_F17R2_FB27_Msk /*!< Filter bit 27 */
+#define CAN_F17R2_FB28_Pos (28U)
+#define CAN_F17R2_FB28_Msk (0x1U << CAN_F17R2_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F17R2_FB28 CAN_F17R2_FB28_Msk /*!< Filter bit 28 */
+#define CAN_F17R2_FB29_Pos (29U)
+#define CAN_F17R2_FB29_Msk (0x1U << CAN_F17R2_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F17R2_FB29 CAN_F17R2_FB29_Msk /*!< Filter bit 29 */
+#define CAN_F17R2_FB30_Pos (30U)
+#define CAN_F17R2_FB30_Msk (0x1U << CAN_F17R2_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F17R2_FB30 CAN_F17R2_FB30_Msk /*!< Filter bit 30 */
+#define CAN_F17R2_FB31_Pos (31U)
+#define CAN_F17R2_FB31_Msk (0x1U << CAN_F17R2_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F17R2_FB31 CAN_F17R2_FB31_Msk /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F18R2 register ******************/
+#define CAN_F18R2_FB0_Pos (0U)
+#define CAN_F18R2_FB0_Msk (0x1U << CAN_F18R2_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F18R2_FB0 CAN_F18R2_FB0_Msk /*!< Filter bit 0 */
+#define CAN_F18R2_FB1_Pos (1U)
+#define CAN_F18R2_FB1_Msk (0x1U << CAN_F18R2_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F18R2_FB1 CAN_F18R2_FB1_Msk /*!< Filter bit 1 */
+#define CAN_F18R2_FB2_Pos (2U)
+#define CAN_F18R2_FB2_Msk (0x1U << CAN_F18R2_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F18R2_FB2 CAN_F18R2_FB2_Msk /*!< Filter bit 2 */
+#define CAN_F18R2_FB3_Pos (3U)
+#define CAN_F18R2_FB3_Msk (0x1U << CAN_F18R2_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F18R2_FB3 CAN_F18R2_FB3_Msk /*!< Filter bit 3 */
+#define CAN_F18R2_FB4_Pos (4U)
+#define CAN_F18R2_FB4_Msk (0x1U << CAN_F18R2_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F18R2_FB4 CAN_F18R2_FB4_Msk /*!< Filter bit 4 */
+#define CAN_F18R2_FB5_Pos (5U)
+#define CAN_F18R2_FB5_Msk (0x1U << CAN_F18R2_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F18R2_FB5 CAN_F18R2_FB5_Msk /*!< Filter bit 5 */
+#define CAN_F18R2_FB6_Pos (6U)
+#define CAN_F18R2_FB6_Msk (0x1U << CAN_F18R2_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F18R2_FB6 CAN_F18R2_FB6_Msk /*!< Filter bit 6 */
+#define CAN_F18R2_FB7_Pos (7U)
+#define CAN_F18R2_FB7_Msk (0x1U << CAN_F18R2_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F18R2_FB7 CAN_F18R2_FB7_Msk /*!< Filter bit 7 */
+#define CAN_F18R2_FB8_Pos (8U)
+#define CAN_F18R2_FB8_Msk (0x1U << CAN_F18R2_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F18R2_FB8 CAN_F18R2_FB8_Msk /*!< Filter bit 8 */
+#define CAN_F18R2_FB9_Pos (9U)
+#define CAN_F18R2_FB9_Msk (0x1U << CAN_F18R2_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F18R2_FB9 CAN_F18R2_FB9_Msk /*!< Filter bit 9 */
+#define CAN_F18R2_FB10_Pos (10U)
+#define CAN_F18R2_FB10_Msk (0x1U << CAN_F18R2_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F18R2_FB10 CAN_F18R2_FB10_Msk /*!< Filter bit 10 */
+#define CAN_F18R2_FB11_Pos (11U)
+#define CAN_F18R2_FB11_Msk (0x1U << CAN_F18R2_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F18R2_FB11 CAN_F18R2_FB11_Msk /*!< Filter bit 11 */
+#define CAN_F18R2_FB12_Pos (12U)
+#define CAN_F18R2_FB12_Msk (0x1U << CAN_F18R2_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F18R2_FB12 CAN_F18R2_FB12_Msk /*!< Filter bit 12 */
+#define CAN_F18R2_FB13_Pos (13U)
+#define CAN_F18R2_FB13_Msk (0x1U << CAN_F18R2_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F18R2_FB13 CAN_F18R2_FB13_Msk /*!< Filter bit 13 */
+#define CAN_F18R2_FB14_Pos (14U)
+#define CAN_F18R2_FB14_Msk (0x1U << CAN_F18R2_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F18R2_FB14 CAN_F18R2_FB14_Msk /*!< Filter bit 14 */
+#define CAN_F18R2_FB15_Pos (15U)
+#define CAN_F18R2_FB15_Msk (0x1U << CAN_F18R2_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F18R2_FB15 CAN_F18R2_FB15_Msk /*!< Filter bit 15 */
+#define CAN_F18R2_FB16_Pos (16U)
+#define CAN_F18R2_FB16_Msk (0x1U << CAN_F18R2_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F18R2_FB16 CAN_F18R2_FB16_Msk /*!< Filter bit 16 */
+#define CAN_F18R2_FB17_Pos (17U)
+#define CAN_F18R2_FB17_Msk (0x1U << CAN_F18R2_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F18R2_FB17 CAN_F18R2_FB17_Msk /*!< Filter bit 17 */
+#define CAN_F18R2_FB18_Pos (18U)
+#define CAN_F18R2_FB18_Msk (0x1U << CAN_F18R2_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F18R2_FB18 CAN_F18R2_FB18_Msk /*!< Filter bit 18 */
+#define CAN_F18R2_FB19_Pos (19U)
+#define CAN_F18R2_FB19_Msk (0x1U << CAN_F18R2_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F18R2_FB19 CAN_F18R2_FB19_Msk /*!< Filter bit 19 */
+#define CAN_F18R2_FB20_Pos (20U)
+#define CAN_F18R2_FB20_Msk (0x1U << CAN_F18R2_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F18R2_FB20 CAN_F18R2_FB20_Msk /*!< Filter bit 20 */
+#define CAN_F18R2_FB21_Pos (21U)
+#define CAN_F18R2_FB21_Msk (0x1U << CAN_F18R2_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F18R2_FB21 CAN_F18R2_FB21_Msk /*!< Filter bit 21 */
+#define CAN_F18R2_FB22_Pos (22U)
+#define CAN_F18R2_FB22_Msk (0x1U << CAN_F18R2_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F18R2_FB22 CAN_F18R2_FB22_Msk /*!< Filter bit 22 */
+#define CAN_F18R2_FB23_Pos (23U)
+#define CAN_F18R2_FB23_Msk (0x1U << CAN_F18R2_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F18R2_FB23 CAN_F18R2_FB23_Msk /*!< Filter bit 23 */
+#define CAN_F18R2_FB24_Pos (24U)
+#define CAN_F18R2_FB24_Msk (0x1U << CAN_F18R2_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F18R2_FB24 CAN_F18R2_FB24_Msk /*!< Filter bit 24 */
+#define CAN_F18R2_FB25_Pos (25U)
+#define CAN_F18R2_FB25_Msk (0x1U << CAN_F18R2_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F18R2_FB25 CAN_F18R2_FB25_Msk /*!< Filter bit 25 */
+#define CAN_F18R2_FB26_Pos (26U)
+#define CAN_F18R2_FB26_Msk (0x1U << CAN_F18R2_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F18R2_FB26 CAN_F18R2_FB26_Msk /*!< Filter bit 26 */
+#define CAN_F18R2_FB27_Pos (27U)
+#define CAN_F18R2_FB27_Msk (0x1U << CAN_F18R2_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F18R2_FB27 CAN_F18R2_FB27_Msk /*!< Filter bit 27 */
+#define CAN_F18R2_FB28_Pos (28U)
+#define CAN_F18R2_FB28_Msk (0x1U << CAN_F18R2_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F18R2_FB28 CAN_F18R2_FB28_Msk /*!< Filter bit 28 */
+#define CAN_F18R2_FB29_Pos (29U)
+#define CAN_F18R2_FB29_Msk (0x1U << CAN_F18R2_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F18R2_FB29 CAN_F18R2_FB29_Msk /*!< Filter bit 29 */
+#define CAN_F18R2_FB30_Pos (30U)
+#define CAN_F18R2_FB30_Msk (0x1U << CAN_F18R2_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F18R2_FB30 CAN_F18R2_FB30_Msk /*!< Filter bit 30 */
+#define CAN_F18R2_FB31_Pos (31U)
+#define CAN_F18R2_FB31_Msk (0x1U << CAN_F18R2_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F18R2_FB31 CAN_F18R2_FB31_Msk /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F19R2 register ******************/
+#define CAN_F19R2_FB0_Pos (0U)
+#define CAN_F19R2_FB0_Msk (0x1U << CAN_F19R2_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F19R2_FB0 CAN_F19R2_FB0_Msk /*!< Filter bit 0 */
+#define CAN_F19R2_FB1_Pos (1U)
+#define CAN_F19R2_FB1_Msk (0x1U << CAN_F19R2_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F19R2_FB1 CAN_F19R2_FB1_Msk /*!< Filter bit 1 */
+#define CAN_F19R2_FB2_Pos (2U)
+#define CAN_F19R2_FB2_Msk (0x1U << CAN_F19R2_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F19R2_FB2 CAN_F19R2_FB2_Msk /*!< Filter bit 2 */
+#define CAN_F19R2_FB3_Pos (3U)
+#define CAN_F19R2_FB3_Msk (0x1U << CAN_F19R2_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F19R2_FB3 CAN_F19R2_FB3_Msk /*!< Filter bit 3 */
+#define CAN_F19R2_FB4_Pos (4U)
+#define CAN_F19R2_FB4_Msk (0x1U << CAN_F19R2_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F19R2_FB4 CAN_F19R2_FB4_Msk /*!< Filter bit 4 */
+#define CAN_F19R2_FB5_Pos (5U)
+#define CAN_F19R2_FB5_Msk (0x1U << CAN_F19R2_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F19R2_FB5 CAN_F19R2_FB5_Msk /*!< Filter bit 5 */
+#define CAN_F19R2_FB6_Pos (6U)
+#define CAN_F19R2_FB6_Msk (0x1U << CAN_F19R2_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F19R2_FB6 CAN_F19R2_FB6_Msk /*!< Filter bit 6 */
+#define CAN_F19R2_FB7_Pos (7U)
+#define CAN_F19R2_FB7_Msk (0x1U << CAN_F19R2_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F19R2_FB7 CAN_F19R2_FB7_Msk /*!< Filter bit 7 */
+#define CAN_F19R2_FB8_Pos (8U)
+#define CAN_F19R2_FB8_Msk (0x1U << CAN_F19R2_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F19R2_FB8 CAN_F19R2_FB8_Msk /*!< Filter bit 8 */
+#define CAN_F19R2_FB9_Pos (9U)
+#define CAN_F19R2_FB9_Msk (0x1U << CAN_F19R2_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F19R2_FB9 CAN_F19R2_FB9_Msk /*!< Filter bit 9 */
+#define CAN_F19R2_FB10_Pos (10U)
+#define CAN_F19R2_FB10_Msk (0x1U << CAN_F19R2_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F19R2_FB10 CAN_F19R2_FB10_Msk /*!< Filter bit 10 */
+#define CAN_F19R2_FB11_Pos (11U)
+#define CAN_F19R2_FB11_Msk (0x1U << CAN_F19R2_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F19R2_FB11 CAN_F19R2_FB11_Msk /*!< Filter bit 11 */
+#define CAN_F19R2_FB12_Pos (12U)
+#define CAN_F19R2_FB12_Msk (0x1U << CAN_F19R2_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F19R2_FB12 CAN_F19R2_FB12_Msk /*!< Filter bit 12 */
+#define CAN_F19R2_FB13_Pos (13U)
+#define CAN_F19R2_FB13_Msk (0x1U << CAN_F19R2_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F19R2_FB13 CAN_F19R2_FB13_Msk /*!< Filter bit 13 */
+#define CAN_F19R2_FB14_Pos (14U)
+#define CAN_F19R2_FB14_Msk (0x1U << CAN_F19R2_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F19R2_FB14 CAN_F19R2_FB14_Msk /*!< Filter bit 14 */
+#define CAN_F19R2_FB15_Pos (15U)
+#define CAN_F19R2_FB15_Msk (0x1U << CAN_F19R2_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F19R2_FB15 CAN_F19R2_FB15_Msk /*!< Filter bit 15 */
+#define CAN_F19R2_FB16_Pos (16U)
+#define CAN_F19R2_FB16_Msk (0x1U << CAN_F19R2_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F19R2_FB16 CAN_F19R2_FB16_Msk /*!< Filter bit 16 */
+#define CAN_F19R2_FB17_Pos (17U)
+#define CAN_F19R2_FB17_Msk (0x1U << CAN_F19R2_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F19R2_FB17 CAN_F19R2_FB17_Msk /*!< Filter bit 17 */
+#define CAN_F19R2_FB18_Pos (18U)
+#define CAN_F19R2_FB18_Msk (0x1U << CAN_F19R2_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F19R2_FB18 CAN_F19R2_FB18_Msk /*!< Filter bit 18 */
+#define CAN_F19R2_FB19_Pos (19U)
+#define CAN_F19R2_FB19_Msk (0x1U << CAN_F19R2_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F19R2_FB19 CAN_F19R2_FB19_Msk /*!< Filter bit 19 */
+#define CAN_F19R2_FB20_Pos (20U)
+#define CAN_F19R2_FB20_Msk (0x1U << CAN_F19R2_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F19R2_FB20 CAN_F19R2_FB20_Msk /*!< Filter bit 20 */
+#define CAN_F19R2_FB21_Pos (21U)
+#define CAN_F19R2_FB21_Msk (0x1U << CAN_F19R2_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F19R2_FB21 CAN_F19R2_FB21_Msk /*!< Filter bit 21 */
+#define CAN_F19R2_FB22_Pos (22U)
+#define CAN_F19R2_FB22_Msk (0x1U << CAN_F19R2_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F19R2_FB22 CAN_F19R2_FB22_Msk /*!< Filter bit 22 */
+#define CAN_F19R2_FB23_Pos (23U)
+#define CAN_F19R2_FB23_Msk (0x1U << CAN_F19R2_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F19R2_FB23 CAN_F19R2_FB23_Msk /*!< Filter bit 23 */
+#define CAN_F19R2_FB24_Pos (24U)
+#define CAN_F19R2_FB24_Msk (0x1U << CAN_F19R2_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F19R2_FB24 CAN_F19R2_FB24_Msk /*!< Filter bit 24 */
+#define CAN_F19R2_FB25_Pos (25U)
+#define CAN_F19R2_FB25_Msk (0x1U << CAN_F19R2_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F19R2_FB25 CAN_F19R2_FB25_Msk /*!< Filter bit 25 */
+#define CAN_F19R2_FB26_Pos (26U)
+#define CAN_F19R2_FB26_Msk (0x1U << CAN_F19R2_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F19R2_FB26 CAN_F19R2_FB26_Msk /*!< Filter bit 26 */
+#define CAN_F19R2_FB27_Pos (27U)
+#define CAN_F19R2_FB27_Msk (0x1U << CAN_F19R2_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F19R2_FB27 CAN_F19R2_FB27_Msk /*!< Filter bit 27 */
+#define CAN_F19R2_FB28_Pos (28U)
+#define CAN_F19R2_FB28_Msk (0x1U << CAN_F19R2_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F19R2_FB28 CAN_F19R2_FB28_Msk /*!< Filter bit 28 */
+#define CAN_F19R2_FB29_Pos (29U)
+#define CAN_F19R2_FB29_Msk (0x1U << CAN_F19R2_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F19R2_FB29 CAN_F19R2_FB29_Msk /*!< Filter bit 29 */
+#define CAN_F19R2_FB30_Pos (30U)
+#define CAN_F19R2_FB30_Msk (0x1U << CAN_F19R2_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F19R2_FB30 CAN_F19R2_FB30_Msk /*!< Filter bit 30 */
+#define CAN_F19R2_FB31_Pos (31U)
+#define CAN_F19R2_FB31_Msk (0x1U << CAN_F19R2_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F19R2_FB31 CAN_F19R2_FB31_Msk /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F20R2 register ******************/
+#define CAN_F20R2_FB0_Pos (0U)
+#define CAN_F20R2_FB0_Msk (0x1U << CAN_F20R2_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F20R2_FB0 CAN_F20R2_FB0_Msk /*!< Filter bit 0 */
+#define CAN_F20R2_FB1_Pos (1U)
+#define CAN_F20R2_FB1_Msk (0x1U << CAN_F20R2_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F20R2_FB1 CAN_F20R2_FB1_Msk /*!< Filter bit 1 */
+#define CAN_F20R2_FB2_Pos (2U)
+#define CAN_F20R2_FB2_Msk (0x1U << CAN_F20R2_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F20R2_FB2 CAN_F20R2_FB2_Msk /*!< Filter bit 2 */
+#define CAN_F20R2_FB3_Pos (3U)
+#define CAN_F20R2_FB3_Msk (0x1U << CAN_F20R2_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F20R2_FB3 CAN_F20R2_FB3_Msk /*!< Filter bit 3 */
+#define CAN_F20R2_FB4_Pos (4U)
+#define CAN_F20R2_FB4_Msk (0x1U << CAN_F20R2_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F20R2_FB4 CAN_F20R2_FB4_Msk /*!< Filter bit 4 */
+#define CAN_F20R2_FB5_Pos (5U)
+#define CAN_F20R2_FB5_Msk (0x1U << CAN_F20R2_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F20R2_FB5 CAN_F20R2_FB5_Msk /*!< Filter bit 5 */
+#define CAN_F20R2_FB6_Pos (6U)
+#define CAN_F20R2_FB6_Msk (0x1U << CAN_F20R2_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F20R2_FB6 CAN_F20R2_FB6_Msk /*!< Filter bit 6 */
+#define CAN_F20R2_FB7_Pos (7U)
+#define CAN_F20R2_FB7_Msk (0x1U << CAN_F20R2_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F20R2_FB7 CAN_F20R2_FB7_Msk /*!< Filter bit 7 */
+#define CAN_F20R2_FB8_Pos (8U)
+#define CAN_F20R2_FB8_Msk (0x1U << CAN_F20R2_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F20R2_FB8 CAN_F20R2_FB8_Msk /*!< Filter bit 8 */
+#define CAN_F20R2_FB9_Pos (9U)
+#define CAN_F20R2_FB9_Msk (0x1U << CAN_F20R2_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F20R2_FB9 CAN_F20R2_FB9_Msk /*!< Filter bit 9 */
+#define CAN_F20R2_FB10_Pos (10U)
+#define CAN_F20R2_FB10_Msk (0x1U << CAN_F20R2_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F20R2_FB10 CAN_F20R2_FB10_Msk /*!< Filter bit 10 */
+#define CAN_F20R2_FB11_Pos (11U)
+#define CAN_F20R2_FB11_Msk (0x1U << CAN_F20R2_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F20R2_FB11 CAN_F20R2_FB11_Msk /*!< Filter bit 11 */
+#define CAN_F20R2_FB12_Pos (12U)
+#define CAN_F20R2_FB12_Msk (0x1U << CAN_F20R2_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F20R2_FB12 CAN_F20R2_FB12_Msk /*!< Filter bit 12 */
+#define CAN_F20R2_FB13_Pos (13U)
+#define CAN_F20R2_FB13_Msk (0x1U << CAN_F20R2_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F20R2_FB13 CAN_F20R2_FB13_Msk /*!< Filter bit 13 */
+#define CAN_F20R2_FB14_Pos (14U)
+#define CAN_F20R2_FB14_Msk (0x1U << CAN_F20R2_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F20R2_FB14 CAN_F20R2_FB14_Msk /*!< Filter bit 14 */
+#define CAN_F20R2_FB15_Pos (15U)
+#define CAN_F20R2_FB15_Msk (0x1U << CAN_F20R2_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F20R2_FB15 CAN_F20R2_FB15_Msk /*!< Filter bit 15 */
+#define CAN_F20R2_FB16_Pos (16U)
+#define CAN_F20R2_FB16_Msk (0x1U << CAN_F20R2_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F20R2_FB16 CAN_F20R2_FB16_Msk /*!< Filter bit 16 */
+#define CAN_F20R2_FB17_Pos (17U)
+#define CAN_F20R2_FB17_Msk (0x1U << CAN_F20R2_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F20R2_FB17 CAN_F20R2_FB17_Msk /*!< Filter bit 17 */
+#define CAN_F20R2_FB18_Pos (18U)
+#define CAN_F20R2_FB18_Msk (0x1U << CAN_F20R2_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F20R2_FB18 CAN_F20R2_FB18_Msk /*!< Filter bit 18 */
+#define CAN_F20R2_FB19_Pos (19U)
+#define CAN_F20R2_FB19_Msk (0x1U << CAN_F20R2_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F20R2_FB19 CAN_F20R2_FB19_Msk /*!< Filter bit 19 */
+#define CAN_F20R2_FB20_Pos (20U)
+#define CAN_F20R2_FB20_Msk (0x1U << CAN_F20R2_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F20R2_FB20 CAN_F20R2_FB20_Msk /*!< Filter bit 20 */
+#define CAN_F20R2_FB21_Pos (21U)
+#define CAN_F20R2_FB21_Msk (0x1U << CAN_F20R2_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F20R2_FB21 CAN_F20R2_FB21_Msk /*!< Filter bit 21 */
+#define CAN_F20R2_FB22_Pos (22U)
+#define CAN_F20R2_FB22_Msk (0x1U << CAN_F20R2_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F20R2_FB22 CAN_F20R2_FB22_Msk /*!< Filter bit 22 */
+#define CAN_F20R2_FB23_Pos (23U)
+#define CAN_F20R2_FB23_Msk (0x1U << CAN_F20R2_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F20R2_FB23 CAN_F20R2_FB23_Msk /*!< Filter bit 23 */
+#define CAN_F20R2_FB24_Pos (24U)
+#define CAN_F20R2_FB24_Msk (0x1U << CAN_F20R2_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F20R2_FB24 CAN_F20R2_FB24_Msk /*!< Filter bit 24 */
+#define CAN_F20R2_FB25_Pos (25U)
+#define CAN_F20R2_FB25_Msk (0x1U << CAN_F20R2_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F20R2_FB25 CAN_F20R2_FB25_Msk /*!< Filter bit 25 */
+#define CAN_F20R2_FB26_Pos (26U)
+#define CAN_F20R2_FB26_Msk (0x1U << CAN_F20R2_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F20R2_FB26 CAN_F20R2_FB26_Msk /*!< Filter bit 26 */
+#define CAN_F20R2_FB27_Pos (27U)
+#define CAN_F20R2_FB27_Msk (0x1U << CAN_F20R2_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F20R2_FB27 CAN_F20R2_FB27_Msk /*!< Filter bit 27 */
+#define CAN_F20R2_FB28_Pos (28U)
+#define CAN_F20R2_FB28_Msk (0x1U << CAN_F20R2_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F20R2_FB28 CAN_F20R2_FB28_Msk /*!< Filter bit 28 */
+#define CAN_F20R2_FB29_Pos (29U)
+#define CAN_F20R2_FB29_Msk (0x1U << CAN_F20R2_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F20R2_FB29 CAN_F20R2_FB29_Msk /*!< Filter bit 29 */
+#define CAN_F20R2_FB30_Pos (30U)
+#define CAN_F20R2_FB30_Msk (0x1U << CAN_F20R2_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F20R2_FB30 CAN_F20R2_FB30_Msk /*!< Filter bit 30 */
+#define CAN_F20R2_FB31_Pos (31U)
+#define CAN_F20R2_FB31_Msk (0x1U << CAN_F20R2_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F20R2_FB31 CAN_F20R2_FB31_Msk /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F21R2 register ******************/
+#define CAN_F21R2_FB0_Pos (0U)
+#define CAN_F21R2_FB0_Msk (0x1U << CAN_F21R2_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F21R2_FB0 CAN_F21R2_FB0_Msk /*!< Filter bit 0 */
+#define CAN_F21R2_FB1_Pos (1U)
+#define CAN_F21R2_FB1_Msk (0x1U << CAN_F21R2_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F21R2_FB1 CAN_F21R2_FB1_Msk /*!< Filter bit 1 */
+#define CAN_F21R2_FB2_Pos (2U)
+#define CAN_F21R2_FB2_Msk (0x1U << CAN_F21R2_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F21R2_FB2 CAN_F21R2_FB2_Msk /*!< Filter bit 2 */
+#define CAN_F21R2_FB3_Pos (3U)
+#define CAN_F21R2_FB3_Msk (0x1U << CAN_F21R2_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F21R2_FB3 CAN_F21R2_FB3_Msk /*!< Filter bit 3 */
+#define CAN_F21R2_FB4_Pos (4U)
+#define CAN_F21R2_FB4_Msk (0x1U << CAN_F21R2_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F21R2_FB4 CAN_F21R2_FB4_Msk /*!< Filter bit 4 */
+#define CAN_F21R2_FB5_Pos (5U)
+#define CAN_F21R2_FB5_Msk (0x1U << CAN_F21R2_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F21R2_FB5 CAN_F21R2_FB5_Msk /*!< Filter bit 5 */
+#define CAN_F21R2_FB6_Pos (6U)
+#define CAN_F21R2_FB6_Msk (0x1U << CAN_F21R2_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F21R2_FB6 CAN_F21R2_FB6_Msk /*!< Filter bit 6 */
+#define CAN_F21R2_FB7_Pos (7U)
+#define CAN_F21R2_FB7_Msk (0x1U << CAN_F21R2_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F21R2_FB7 CAN_F21R2_FB7_Msk /*!< Filter bit 7 */
+#define CAN_F21R2_FB8_Pos (8U)
+#define CAN_F21R2_FB8_Msk (0x1U << CAN_F21R2_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F21R2_FB8 CAN_F21R2_FB8_Msk /*!< Filter bit 8 */
+#define CAN_F21R2_FB9_Pos (9U)
+#define CAN_F21R2_FB9_Msk (0x1U << CAN_F21R2_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F21R2_FB9 CAN_F21R2_FB9_Msk /*!< Filter bit 9 */
+#define CAN_F21R2_FB10_Pos (10U)
+#define CAN_F21R2_FB10_Msk (0x1U << CAN_F21R2_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F21R2_FB10 CAN_F21R2_FB10_Msk /*!< Filter bit 10 */
+#define CAN_F21R2_FB11_Pos (11U)
+#define CAN_F21R2_FB11_Msk (0x1U << CAN_F21R2_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F21R2_FB11 CAN_F21R2_FB11_Msk /*!< Filter bit 11 */
+#define CAN_F21R2_FB12_Pos (12U)
+#define CAN_F21R2_FB12_Msk (0x1U << CAN_F21R2_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F21R2_FB12 CAN_F21R2_FB12_Msk /*!< Filter bit 12 */
+#define CAN_F21R2_FB13_Pos (13U)
+#define CAN_F21R2_FB13_Msk (0x1U << CAN_F21R2_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F21R2_FB13 CAN_F21R2_FB13_Msk /*!< Filter bit 13 */
+#define CAN_F21R2_FB14_Pos (14U)
+#define CAN_F21R2_FB14_Msk (0x1U << CAN_F21R2_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F21R2_FB14 CAN_F21R2_FB14_Msk /*!< Filter bit 14 */
+#define CAN_F21R2_FB15_Pos (15U)
+#define CAN_F21R2_FB15_Msk (0x1U << CAN_F21R2_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F21R2_FB15 CAN_F21R2_FB15_Msk /*!< Filter bit 15 */
+#define CAN_F21R2_FB16_Pos (16U)
+#define CAN_F21R2_FB16_Msk (0x1U << CAN_F21R2_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F21R2_FB16 CAN_F21R2_FB16_Msk /*!< Filter bit 16 */
+#define CAN_F21R2_FB17_Pos (17U)
+#define CAN_F21R2_FB17_Msk (0x1U << CAN_F21R2_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F21R2_FB17 CAN_F21R2_FB17_Msk /*!< Filter bit 17 */
+#define CAN_F21R2_FB18_Pos (18U)
+#define CAN_F21R2_FB18_Msk (0x1U << CAN_F21R2_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F21R2_FB18 CAN_F21R2_FB18_Msk /*!< Filter bit 18 */
+#define CAN_F21R2_FB19_Pos (19U)
+#define CAN_F21R2_FB19_Msk (0x1U << CAN_F21R2_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F21R2_FB19 CAN_F21R2_FB19_Msk /*!< Filter bit 19 */
+#define CAN_F21R2_FB20_Pos (20U)
+#define CAN_F21R2_FB20_Msk (0x1U << CAN_F21R2_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F21R2_FB20 CAN_F21R2_FB20_Msk /*!< Filter bit 20 */
+#define CAN_F21R2_FB21_Pos (21U)
+#define CAN_F21R2_FB21_Msk (0x1U << CAN_F21R2_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F21R2_FB21 CAN_F21R2_FB21_Msk /*!< Filter bit 21 */
+#define CAN_F21R2_FB22_Pos (22U)
+#define CAN_F21R2_FB22_Msk (0x1U << CAN_F21R2_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F21R2_FB22 CAN_F21R2_FB22_Msk /*!< Filter bit 22 */
+#define CAN_F21R2_FB23_Pos (23U)
+#define CAN_F21R2_FB23_Msk (0x1U << CAN_F21R2_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F21R2_FB23 CAN_F21R2_FB23_Msk /*!< Filter bit 23 */
+#define CAN_F21R2_FB24_Pos (24U)
+#define CAN_F21R2_FB24_Msk (0x1U << CAN_F21R2_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F21R2_FB24 CAN_F21R2_FB24_Msk /*!< Filter bit 24 */
+#define CAN_F21R2_FB25_Pos (25U)
+#define CAN_F21R2_FB25_Msk (0x1U << CAN_F21R2_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F21R2_FB25 CAN_F21R2_FB25_Msk /*!< Filter bit 25 */
+#define CAN_F21R2_FB26_Pos (26U)
+#define CAN_F21R2_FB26_Msk (0x1U << CAN_F21R2_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F21R2_FB26 CAN_F21R2_FB26_Msk /*!< Filter bit 26 */
+#define CAN_F21R2_FB27_Pos (27U)
+#define CAN_F21R2_FB27_Msk (0x1U << CAN_F21R2_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F21R2_FB27 CAN_F21R2_FB27_Msk /*!< Filter bit 27 */
+#define CAN_F21R2_FB28_Pos (28U)
+#define CAN_F21R2_FB28_Msk (0x1U << CAN_F21R2_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F21R2_FB28 CAN_F21R2_FB28_Msk /*!< Filter bit 28 */
+#define CAN_F21R2_FB29_Pos (29U)
+#define CAN_F21R2_FB29_Msk (0x1U << CAN_F21R2_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F21R2_FB29 CAN_F21R2_FB29_Msk /*!< Filter bit 29 */
+#define CAN_F21R2_FB30_Pos (30U)
+#define CAN_F21R2_FB30_Msk (0x1U << CAN_F21R2_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F21R2_FB30 CAN_F21R2_FB30_Msk /*!< Filter bit 30 */
+#define CAN_F21R2_FB31_Pos (31U)
+#define CAN_F21R2_FB31_Msk (0x1U << CAN_F21R2_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F21R2_FB31 CAN_F21R2_FB31_Msk /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F22R2 register ******************/
+#define CAN_F22R2_FB0_Pos (0U)
+#define CAN_F22R2_FB0_Msk (0x1U << CAN_F22R2_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F22R2_FB0 CAN_F22R2_FB0_Msk /*!< Filter bit 0 */
+#define CAN_F22R2_FB1_Pos (1U)
+#define CAN_F22R2_FB1_Msk (0x1U << CAN_F22R2_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F22R2_FB1 CAN_F22R2_FB1_Msk /*!< Filter bit 1 */
+#define CAN_F22R2_FB2_Pos (2U)
+#define CAN_F22R2_FB2_Msk (0x1U << CAN_F22R2_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F22R2_FB2 CAN_F22R2_FB2_Msk /*!< Filter bit 2 */
+#define CAN_F22R2_FB3_Pos (3U)
+#define CAN_F22R2_FB3_Msk (0x1U << CAN_F22R2_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F22R2_FB3 CAN_F22R2_FB3_Msk /*!< Filter bit 3 */
+#define CAN_F22R2_FB4_Pos (4U)
+#define CAN_F22R2_FB4_Msk (0x1U << CAN_F22R2_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F22R2_FB4 CAN_F22R2_FB4_Msk /*!< Filter bit 4 */
+#define CAN_F22R2_FB5_Pos (5U)
+#define CAN_F22R2_FB5_Msk (0x1U << CAN_F22R2_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F22R2_FB5 CAN_F22R2_FB5_Msk /*!< Filter bit 5 */
+#define CAN_F22R2_FB6_Pos (6U)
+#define CAN_F22R2_FB6_Msk (0x1U << CAN_F22R2_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F22R2_FB6 CAN_F22R2_FB6_Msk /*!< Filter bit 6 */
+#define CAN_F22R2_FB7_Pos (7U)
+#define CAN_F22R2_FB7_Msk (0x1U << CAN_F22R2_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F22R2_FB7 CAN_F22R2_FB7_Msk /*!< Filter bit 7 */
+#define CAN_F22R2_FB8_Pos (8U)
+#define CAN_F22R2_FB8_Msk (0x1U << CAN_F22R2_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F22R2_FB8 CAN_F22R2_FB8_Msk /*!< Filter bit 8 */
+#define CAN_F22R2_FB9_Pos (9U)
+#define CAN_F22R2_FB9_Msk (0x1U << CAN_F22R2_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F22R2_FB9 CAN_F22R2_FB9_Msk /*!< Filter bit 9 */
+#define CAN_F22R2_FB10_Pos (10U)
+#define CAN_F22R2_FB10_Msk (0x1U << CAN_F22R2_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F22R2_FB10 CAN_F22R2_FB10_Msk /*!< Filter bit 10 */
+#define CAN_F22R2_FB11_Pos (11U)
+#define CAN_F22R2_FB11_Msk (0x1U << CAN_F22R2_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F22R2_FB11 CAN_F22R2_FB11_Msk /*!< Filter bit 11 */
+#define CAN_F22R2_FB12_Pos (12U)
+#define CAN_F22R2_FB12_Msk (0x1U << CAN_F22R2_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F22R2_FB12 CAN_F22R2_FB12_Msk /*!< Filter bit 12 */
+#define CAN_F22R2_FB13_Pos (13U)
+#define CAN_F22R2_FB13_Msk (0x1U << CAN_F22R2_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F22R2_FB13 CAN_F22R2_FB13_Msk /*!< Filter bit 13 */
+#define CAN_F22R2_FB14_Pos (14U)
+#define CAN_F22R2_FB14_Msk (0x1U << CAN_F22R2_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F22R2_FB14 CAN_F22R2_FB14_Msk /*!< Filter bit 14 */
+#define CAN_F22R2_FB15_Pos (15U)
+#define CAN_F22R2_FB15_Msk (0x1U << CAN_F22R2_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F22R2_FB15 CAN_F22R2_FB15_Msk /*!< Filter bit 15 */
+#define CAN_F22R2_FB16_Pos (16U)
+#define CAN_F22R2_FB16_Msk (0x1U << CAN_F22R2_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F22R2_FB16 CAN_F22R2_FB16_Msk /*!< Filter bit 16 */
+#define CAN_F22R2_FB17_Pos (17U)
+#define CAN_F22R2_FB17_Msk (0x1U << CAN_F22R2_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F22R2_FB17 CAN_F22R2_FB17_Msk /*!< Filter bit 17 */
+#define CAN_F22R2_FB18_Pos (18U)
+#define CAN_F22R2_FB18_Msk (0x1U << CAN_F22R2_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F22R2_FB18 CAN_F22R2_FB18_Msk /*!< Filter bit 18 */
+#define CAN_F22R2_FB19_Pos (19U)
+#define CAN_F22R2_FB19_Msk (0x1U << CAN_F22R2_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F22R2_FB19 CAN_F22R2_FB19_Msk /*!< Filter bit 19 */
+#define CAN_F22R2_FB20_Pos (20U)
+#define CAN_F22R2_FB20_Msk (0x1U << CAN_F22R2_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F22R2_FB20 CAN_F22R2_FB20_Msk /*!< Filter bit 20 */
+#define CAN_F22R2_FB21_Pos (21U)
+#define CAN_F22R2_FB21_Msk (0x1U << CAN_F22R2_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F22R2_FB21 CAN_F22R2_FB21_Msk /*!< Filter bit 21 */
+#define CAN_F22R2_FB22_Pos (22U)
+#define CAN_F22R2_FB22_Msk (0x1U << CAN_F22R2_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F22R2_FB22 CAN_F22R2_FB22_Msk /*!< Filter bit 22 */
+#define CAN_F22R2_FB23_Pos (23U)
+#define CAN_F22R2_FB23_Msk (0x1U << CAN_F22R2_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F22R2_FB23 CAN_F22R2_FB23_Msk /*!< Filter bit 23 */
+#define CAN_F22R2_FB24_Pos (24U)
+#define CAN_F22R2_FB24_Msk (0x1U << CAN_F22R2_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F22R2_FB24 CAN_F22R2_FB24_Msk /*!< Filter bit 24 */
+#define CAN_F22R2_FB25_Pos (25U)
+#define CAN_F22R2_FB25_Msk (0x1U << CAN_F22R2_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F22R2_FB25 CAN_F22R2_FB25_Msk /*!< Filter bit 25 */
+#define CAN_F22R2_FB26_Pos (26U)
+#define CAN_F22R2_FB26_Msk (0x1U << CAN_F22R2_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F22R2_FB26 CAN_F22R2_FB26_Msk /*!< Filter bit 26 */
+#define CAN_F22R2_FB27_Pos (27U)
+#define CAN_F22R2_FB27_Msk (0x1U << CAN_F22R2_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F22R2_FB27 CAN_F22R2_FB27_Msk /*!< Filter bit 27 */
+#define CAN_F22R2_FB28_Pos (28U)
+#define CAN_F22R2_FB28_Msk (0x1U << CAN_F22R2_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F22R2_FB28 CAN_F22R2_FB28_Msk /*!< Filter bit 28 */
+#define CAN_F22R2_FB29_Pos (29U)
+#define CAN_F22R2_FB29_Msk (0x1U << CAN_F22R2_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F22R2_FB29 CAN_F22R2_FB29_Msk /*!< Filter bit 29 */
+#define CAN_F22R2_FB30_Pos (30U)
+#define CAN_F22R2_FB30_Msk (0x1U << CAN_F22R2_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F22R2_FB30 CAN_F22R2_FB30_Msk /*!< Filter bit 30 */
+#define CAN_F22R2_FB31_Pos (31U)
+#define CAN_F22R2_FB31_Msk (0x1U << CAN_F22R2_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F22R2_FB31 CAN_F22R2_FB31_Msk /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F23R2 register ******************/
+#define CAN_F23R2_FB0_Pos (0U)
+#define CAN_F23R2_FB0_Msk (0x1U << CAN_F23R2_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F23R2_FB0 CAN_F23R2_FB0_Msk /*!< Filter bit 0 */
+#define CAN_F23R2_FB1_Pos (1U)
+#define CAN_F23R2_FB1_Msk (0x1U << CAN_F23R2_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F23R2_FB1 CAN_F23R2_FB1_Msk /*!< Filter bit 1 */
+#define CAN_F23R2_FB2_Pos (2U)
+#define CAN_F23R2_FB2_Msk (0x1U << CAN_F23R2_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F23R2_FB2 CAN_F23R2_FB2_Msk /*!< Filter bit 2 */
+#define CAN_F23R2_FB3_Pos (3U)
+#define CAN_F23R2_FB3_Msk (0x1U << CAN_F23R2_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F23R2_FB3 CAN_F23R2_FB3_Msk /*!< Filter bit 3 */
+#define CAN_F23R2_FB4_Pos (4U)
+#define CAN_F23R2_FB4_Msk (0x1U << CAN_F23R2_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F23R2_FB4 CAN_F23R2_FB4_Msk /*!< Filter bit 4 */
+#define CAN_F23R2_FB5_Pos (5U)
+#define CAN_F23R2_FB5_Msk (0x1U << CAN_F23R2_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F23R2_FB5 CAN_F23R2_FB5_Msk /*!< Filter bit 5 */
+#define CAN_F23R2_FB6_Pos (6U)
+#define CAN_F23R2_FB6_Msk (0x1U << CAN_F23R2_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F23R2_FB6 CAN_F23R2_FB6_Msk /*!< Filter bit 6 */
+#define CAN_F23R2_FB7_Pos (7U)
+#define CAN_F23R2_FB7_Msk (0x1U << CAN_F23R2_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F23R2_FB7 CAN_F23R2_FB7_Msk /*!< Filter bit 7 */
+#define CAN_F23R2_FB8_Pos (8U)
+#define CAN_F23R2_FB8_Msk (0x1U << CAN_F23R2_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F23R2_FB8 CAN_F23R2_FB8_Msk /*!< Filter bit 8 */
+#define CAN_F23R2_FB9_Pos (9U)
+#define CAN_F23R2_FB9_Msk (0x1U << CAN_F23R2_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F23R2_FB9 CAN_F23R2_FB9_Msk /*!< Filter bit 9 */
+#define CAN_F23R2_FB10_Pos (10U)
+#define CAN_F23R2_FB10_Msk (0x1U << CAN_F23R2_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F23R2_FB10 CAN_F23R2_FB10_Msk /*!< Filter bit 10 */
+#define CAN_F23R2_FB11_Pos (11U)
+#define CAN_F23R2_FB11_Msk (0x1U << CAN_F23R2_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F23R2_FB11 CAN_F23R2_FB11_Msk /*!< Filter bit 11 */
+#define CAN_F23R2_FB12_Pos (12U)
+#define CAN_F23R2_FB12_Msk (0x1U << CAN_F23R2_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F23R2_FB12 CAN_F23R2_FB12_Msk /*!< Filter bit 12 */
+#define CAN_F23R2_FB13_Pos (13U)
+#define CAN_F23R2_FB13_Msk (0x1U << CAN_F23R2_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F23R2_FB13 CAN_F23R2_FB13_Msk /*!< Filter bit 13 */
+#define CAN_F23R2_FB14_Pos (14U)
+#define CAN_F23R2_FB14_Msk (0x1U << CAN_F23R2_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F23R2_FB14 CAN_F23R2_FB14_Msk /*!< Filter bit 14 */
+#define CAN_F23R2_FB15_Pos (15U)
+#define CAN_F23R2_FB15_Msk (0x1U << CAN_F23R2_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F23R2_FB15 CAN_F23R2_FB15_Msk /*!< Filter bit 15 */
+#define CAN_F23R2_FB16_Pos (16U)
+#define CAN_F23R2_FB16_Msk (0x1U << CAN_F23R2_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F23R2_FB16 CAN_F23R2_FB16_Msk /*!< Filter bit 16 */
+#define CAN_F23R2_FB17_Pos (17U)
+#define CAN_F23R2_FB17_Msk (0x1U << CAN_F23R2_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F23R2_FB17 CAN_F23R2_FB17_Msk /*!< Filter bit 17 */
+#define CAN_F23R2_FB18_Pos (18U)
+#define CAN_F23R2_FB18_Msk (0x1U << CAN_F23R2_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F23R2_FB18 CAN_F23R2_FB18_Msk /*!< Filter bit 18 */
+#define CAN_F23R2_FB19_Pos (19U)
+#define CAN_F23R2_FB19_Msk (0x1U << CAN_F23R2_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F23R2_FB19 CAN_F23R2_FB19_Msk /*!< Filter bit 19 */
+#define CAN_F23R2_FB20_Pos (20U)
+#define CAN_F23R2_FB20_Msk (0x1U << CAN_F23R2_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F23R2_FB20 CAN_F23R2_FB20_Msk /*!< Filter bit 20 */
+#define CAN_F23R2_FB21_Pos (21U)
+#define CAN_F23R2_FB21_Msk (0x1U << CAN_F23R2_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F23R2_FB21 CAN_F23R2_FB21_Msk /*!< Filter bit 21 */
+#define CAN_F23R2_FB22_Pos (22U)
+#define CAN_F23R2_FB22_Msk (0x1U << CAN_F23R2_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F23R2_FB22 CAN_F23R2_FB22_Msk /*!< Filter bit 22 */
+#define CAN_F23R2_FB23_Pos (23U)
+#define CAN_F23R2_FB23_Msk (0x1U << CAN_F23R2_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F23R2_FB23 CAN_F23R2_FB23_Msk /*!< Filter bit 23 */
+#define CAN_F23R2_FB24_Pos (24U)
+#define CAN_F23R2_FB24_Msk (0x1U << CAN_F23R2_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F23R2_FB24 CAN_F23R2_FB24_Msk /*!< Filter bit 24 */
+#define CAN_F23R2_FB25_Pos (25U)
+#define CAN_F23R2_FB25_Msk (0x1U << CAN_F23R2_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F23R2_FB25 CAN_F23R2_FB25_Msk /*!< Filter bit 25 */
+#define CAN_F23R2_FB26_Pos (26U)
+#define CAN_F23R2_FB26_Msk (0x1U << CAN_F23R2_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F23R2_FB26 CAN_F23R2_FB26_Msk /*!< Filter bit 26 */
+#define CAN_F23R2_FB27_Pos (27U)
+#define CAN_F23R2_FB27_Msk (0x1U << CAN_F23R2_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F23R2_FB27 CAN_F23R2_FB27_Msk /*!< Filter bit 27 */
+#define CAN_F23R2_FB28_Pos (28U)
+#define CAN_F23R2_FB28_Msk (0x1U << CAN_F23R2_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F23R2_FB28 CAN_F23R2_FB28_Msk /*!< Filter bit 28 */
+#define CAN_F23R2_FB29_Pos (29U)
+#define CAN_F23R2_FB29_Msk (0x1U << CAN_F23R2_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F23R2_FB29 CAN_F23R2_FB29_Msk /*!< Filter bit 29 */
+#define CAN_F23R2_FB30_Pos (30U)
+#define CAN_F23R2_FB30_Msk (0x1U << CAN_F23R2_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F23R2_FB30 CAN_F23R2_FB30_Msk /*!< Filter bit 30 */
+#define CAN_F23R2_FB31_Pos (31U)
+#define CAN_F23R2_FB31_Msk (0x1U << CAN_F23R2_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F23R2_FB31 CAN_F23R2_FB31_Msk /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F24R2 register ******************/
+#define CAN_F24R2_FB0_Pos (0U)
+#define CAN_F24R2_FB0_Msk (0x1U << CAN_F24R2_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F24R2_FB0 CAN_F24R2_FB0_Msk /*!< Filter bit 0 */
+#define CAN_F24R2_FB1_Pos (1U)
+#define CAN_F24R2_FB1_Msk (0x1U << CAN_F24R2_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F24R2_FB1 CAN_F24R2_FB1_Msk /*!< Filter bit 1 */
+#define CAN_F24R2_FB2_Pos (2U)
+#define CAN_F24R2_FB2_Msk (0x1U << CAN_F24R2_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F24R2_FB2 CAN_F24R2_FB2_Msk /*!< Filter bit 2 */
+#define CAN_F24R2_FB3_Pos (3U)
+#define CAN_F24R2_FB3_Msk (0x1U << CAN_F24R2_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F24R2_FB3 CAN_F24R2_FB3_Msk /*!< Filter bit 3 */
+#define CAN_F24R2_FB4_Pos (4U)
+#define CAN_F24R2_FB4_Msk (0x1U << CAN_F24R2_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F24R2_FB4 CAN_F24R2_FB4_Msk /*!< Filter bit 4 */
+#define CAN_F24R2_FB5_Pos (5U)
+#define CAN_F24R2_FB5_Msk (0x1U << CAN_F24R2_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F24R2_FB5 CAN_F24R2_FB5_Msk /*!< Filter bit 5 */
+#define CAN_F24R2_FB6_Pos (6U)
+#define CAN_F24R2_FB6_Msk (0x1U << CAN_F24R2_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F24R2_FB6 CAN_F24R2_FB6_Msk /*!< Filter bit 6 */
+#define CAN_F24R2_FB7_Pos (7U)
+#define CAN_F24R2_FB7_Msk (0x1U << CAN_F24R2_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F24R2_FB7 CAN_F24R2_FB7_Msk /*!< Filter bit 7 */
+#define CAN_F24R2_FB8_Pos (8U)
+#define CAN_F24R2_FB8_Msk (0x1U << CAN_F24R2_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F24R2_FB8 CAN_F24R2_FB8_Msk /*!< Filter bit 8 */
+#define CAN_F24R2_FB9_Pos (9U)
+#define CAN_F24R2_FB9_Msk (0x1U << CAN_F24R2_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F24R2_FB9 CAN_F24R2_FB9_Msk /*!< Filter bit 9 */
+#define CAN_F24R2_FB10_Pos (10U)
+#define CAN_F24R2_FB10_Msk (0x1U << CAN_F24R2_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F24R2_FB10 CAN_F24R2_FB10_Msk /*!< Filter bit 10 */
+#define CAN_F24R2_FB11_Pos (11U)
+#define CAN_F24R2_FB11_Msk (0x1U << CAN_F24R2_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F24R2_FB11 CAN_F24R2_FB11_Msk /*!< Filter bit 11 */
+#define CAN_F24R2_FB12_Pos (12U)
+#define CAN_F24R2_FB12_Msk (0x1U << CAN_F24R2_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F24R2_FB12 CAN_F24R2_FB12_Msk /*!< Filter bit 12 */
+#define CAN_F24R2_FB13_Pos (13U)
+#define CAN_F24R2_FB13_Msk (0x1U << CAN_F24R2_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F24R2_FB13 CAN_F24R2_FB13_Msk /*!< Filter bit 13 */
+#define CAN_F24R2_FB14_Pos (14U)
+#define CAN_F24R2_FB14_Msk (0x1U << CAN_F24R2_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F24R2_FB14 CAN_F24R2_FB14_Msk /*!< Filter bit 14 */
+#define CAN_F24R2_FB15_Pos (15U)
+#define CAN_F24R2_FB15_Msk (0x1U << CAN_F24R2_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F24R2_FB15 CAN_F24R2_FB15_Msk /*!< Filter bit 15 */
+#define CAN_F24R2_FB16_Pos (16U)
+#define CAN_F24R2_FB16_Msk (0x1U << CAN_F24R2_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F24R2_FB16 CAN_F24R2_FB16_Msk /*!< Filter bit 16 */
+#define CAN_F24R2_FB17_Pos (17U)
+#define CAN_F24R2_FB17_Msk (0x1U << CAN_F24R2_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F24R2_FB17 CAN_F24R2_FB17_Msk /*!< Filter bit 17 */
+#define CAN_F24R2_FB18_Pos (18U)
+#define CAN_F24R2_FB18_Msk (0x1U << CAN_F24R2_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F24R2_FB18 CAN_F24R2_FB18_Msk /*!< Filter bit 18 */
+#define CAN_F24R2_FB19_Pos (19U)
+#define CAN_F24R2_FB19_Msk (0x1U << CAN_F24R2_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F24R2_FB19 CAN_F24R2_FB19_Msk /*!< Filter bit 19 */
+#define CAN_F24R2_FB20_Pos (20U)
+#define CAN_F24R2_FB20_Msk (0x1U << CAN_F24R2_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F24R2_FB20 CAN_F24R2_FB20_Msk /*!< Filter bit 20 */
+#define CAN_F24R2_FB21_Pos (21U)
+#define CAN_F24R2_FB21_Msk (0x1U << CAN_F24R2_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F24R2_FB21 CAN_F24R2_FB21_Msk /*!< Filter bit 21 */
+#define CAN_F24R2_FB22_Pos (22U)
+#define CAN_F24R2_FB22_Msk (0x1U << CAN_F24R2_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F24R2_FB22 CAN_F24R2_FB22_Msk /*!< Filter bit 22 */
+#define CAN_F24R2_FB23_Pos (23U)
+#define CAN_F24R2_FB23_Msk (0x1U << CAN_F24R2_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F24R2_FB23 CAN_F24R2_FB23_Msk /*!< Filter bit 23 */
+#define CAN_F24R2_FB24_Pos (24U)
+#define CAN_F24R2_FB24_Msk (0x1U << CAN_F24R2_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F24R2_FB24 CAN_F24R2_FB24_Msk /*!< Filter bit 24 */
+#define CAN_F24R2_FB25_Pos (25U)
+#define CAN_F24R2_FB25_Msk (0x1U << CAN_F24R2_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F24R2_FB25 CAN_F24R2_FB25_Msk /*!< Filter bit 25 */
+#define CAN_F24R2_FB26_Pos (26U)
+#define CAN_F24R2_FB26_Msk (0x1U << CAN_F24R2_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F24R2_FB26 CAN_F24R2_FB26_Msk /*!< Filter bit 26 */
+#define CAN_F24R2_FB27_Pos (27U)
+#define CAN_F24R2_FB27_Msk (0x1U << CAN_F24R2_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F24R2_FB27 CAN_F24R2_FB27_Msk /*!< Filter bit 27 */
+#define CAN_F24R2_FB28_Pos (28U)
+#define CAN_F24R2_FB28_Msk (0x1U << CAN_F24R2_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F24R2_FB28 CAN_F24R2_FB28_Msk /*!< Filter bit 28 */
+#define CAN_F24R2_FB29_Pos (29U)
+#define CAN_F24R2_FB29_Msk (0x1U << CAN_F24R2_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F24R2_FB29 CAN_F24R2_FB29_Msk /*!< Filter bit 29 */
+#define CAN_F24R2_FB30_Pos (30U)
+#define CAN_F24R2_FB30_Msk (0x1U << CAN_F24R2_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F24R2_FB30 CAN_F24R2_FB30_Msk /*!< Filter bit 30 */
+#define CAN_F24R2_FB31_Pos (31U)
+#define CAN_F24R2_FB31_Msk (0x1U << CAN_F24R2_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F24R2_FB31 CAN_F24R2_FB31_Msk /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F25R2 register ******************/
+#define CAN_F25R2_FB0_Pos (0U)
+#define CAN_F25R2_FB0_Msk (0x1U << CAN_F25R2_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F25R2_FB0 CAN_F25R2_FB0_Msk /*!< Filter bit 0 */
+#define CAN_F25R2_FB1_Pos (1U)
+#define CAN_F25R2_FB1_Msk (0x1U << CAN_F25R2_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F25R2_FB1 CAN_F25R2_FB1_Msk /*!< Filter bit 1 */
+#define CAN_F25R2_FB2_Pos (2U)
+#define CAN_F25R2_FB2_Msk (0x1U << CAN_F25R2_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F25R2_FB2 CAN_F25R2_FB2_Msk /*!< Filter bit 2 */
+#define CAN_F25R2_FB3_Pos (3U)
+#define CAN_F25R2_FB3_Msk (0x1U << CAN_F25R2_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F25R2_FB3 CAN_F25R2_FB3_Msk /*!< Filter bit 3 */
+#define CAN_F25R2_FB4_Pos (4U)
+#define CAN_F25R2_FB4_Msk (0x1U << CAN_F25R2_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F25R2_FB4 CAN_F25R2_FB4_Msk /*!< Filter bit 4 */
+#define CAN_F25R2_FB5_Pos (5U)
+#define CAN_F25R2_FB5_Msk (0x1U << CAN_F25R2_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F25R2_FB5 CAN_F25R2_FB5_Msk /*!< Filter bit 5 */
+#define CAN_F25R2_FB6_Pos (6U)
+#define CAN_F25R2_FB6_Msk (0x1U << CAN_F25R2_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F25R2_FB6 CAN_F25R2_FB6_Msk /*!< Filter bit 6 */
+#define CAN_F25R2_FB7_Pos (7U)
+#define CAN_F25R2_FB7_Msk (0x1U << CAN_F25R2_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F25R2_FB7 CAN_F25R2_FB7_Msk /*!< Filter bit 7 */
+#define CAN_F25R2_FB8_Pos (8U)
+#define CAN_F25R2_FB8_Msk (0x1U << CAN_F25R2_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F25R2_FB8 CAN_F25R2_FB8_Msk /*!< Filter bit 8 */
+#define CAN_F25R2_FB9_Pos (9U)
+#define CAN_F25R2_FB9_Msk (0x1U << CAN_F25R2_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F25R2_FB9 CAN_F25R2_FB9_Msk /*!< Filter bit 9 */
+#define CAN_F25R2_FB10_Pos (10U)
+#define CAN_F25R2_FB10_Msk (0x1U << CAN_F25R2_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F25R2_FB10 CAN_F25R2_FB10_Msk /*!< Filter bit 10 */
+#define CAN_F25R2_FB11_Pos (11U)
+#define CAN_F25R2_FB11_Msk (0x1U << CAN_F25R2_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F25R2_FB11 CAN_F25R2_FB11_Msk /*!< Filter bit 11 */
+#define CAN_F25R2_FB12_Pos (12U)
+#define CAN_F25R2_FB12_Msk (0x1U << CAN_F25R2_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F25R2_FB12 CAN_F25R2_FB12_Msk /*!< Filter bit 12 */
+#define CAN_F25R2_FB13_Pos (13U)
+#define CAN_F25R2_FB13_Msk (0x1U << CAN_F25R2_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F25R2_FB13 CAN_F25R2_FB13_Msk /*!< Filter bit 13 */
+#define CAN_F25R2_FB14_Pos (14U)
+#define CAN_F25R2_FB14_Msk (0x1U << CAN_F25R2_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F25R2_FB14 CAN_F25R2_FB14_Msk /*!< Filter bit 14 */
+#define CAN_F25R2_FB15_Pos (15U)
+#define CAN_F25R2_FB15_Msk (0x1U << CAN_F25R2_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F25R2_FB15 CAN_F25R2_FB15_Msk /*!< Filter bit 15 */
+#define CAN_F25R2_FB16_Pos (16U)
+#define CAN_F25R2_FB16_Msk (0x1U << CAN_F25R2_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F25R2_FB16 CAN_F25R2_FB16_Msk /*!< Filter bit 16 */
+#define CAN_F25R2_FB17_Pos (17U)
+#define CAN_F25R2_FB17_Msk (0x1U << CAN_F25R2_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F25R2_FB17 CAN_F25R2_FB17_Msk /*!< Filter bit 17 */
+#define CAN_F25R2_FB18_Pos (18U)
+#define CAN_F25R2_FB18_Msk (0x1U << CAN_F25R2_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F25R2_FB18 CAN_F25R2_FB18_Msk /*!< Filter bit 18 */
+#define CAN_F25R2_FB19_Pos (19U)
+#define CAN_F25R2_FB19_Msk (0x1U << CAN_F25R2_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F25R2_FB19 CAN_F25R2_FB19_Msk /*!< Filter bit 19 */
+#define CAN_F25R2_FB20_Pos (20U)
+#define CAN_F25R2_FB20_Msk (0x1U << CAN_F25R2_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F25R2_FB20 CAN_F25R2_FB20_Msk /*!< Filter bit 20 */
+#define CAN_F25R2_FB21_Pos (21U)
+#define CAN_F25R2_FB21_Msk (0x1U << CAN_F25R2_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F25R2_FB21 CAN_F25R2_FB21_Msk /*!< Filter bit 21 */
+#define CAN_F25R2_FB22_Pos (22U)
+#define CAN_F25R2_FB22_Msk (0x1U << CAN_F25R2_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F25R2_FB22 CAN_F25R2_FB22_Msk /*!< Filter bit 22 */
+#define CAN_F25R2_FB23_Pos (23U)
+#define CAN_F25R2_FB23_Msk (0x1U << CAN_F25R2_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F25R2_FB23 CAN_F25R2_FB23_Msk /*!< Filter bit 23 */
+#define CAN_F25R2_FB24_Pos (24U)
+#define CAN_F25R2_FB24_Msk (0x1U << CAN_F25R2_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F25R2_FB24 CAN_F25R2_FB24_Msk /*!< Filter bit 24 */
+#define CAN_F25R2_FB25_Pos (25U)
+#define CAN_F25R2_FB25_Msk (0x1U << CAN_F25R2_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F25R2_FB25 CAN_F25R2_FB25_Msk /*!< Filter bit 25 */
+#define CAN_F25R2_FB26_Pos (26U)
+#define CAN_F25R2_FB26_Msk (0x1U << CAN_F25R2_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F25R2_FB26 CAN_F25R2_FB26_Msk /*!< Filter bit 26 */
+#define CAN_F25R2_FB27_Pos (27U)
+#define CAN_F25R2_FB27_Msk (0x1U << CAN_F25R2_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F25R2_FB27 CAN_F25R2_FB27_Msk /*!< Filter bit 27 */
+#define CAN_F25R2_FB28_Pos (28U)
+#define CAN_F25R2_FB28_Msk (0x1U << CAN_F25R2_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F25R2_FB28 CAN_F25R2_FB28_Msk /*!< Filter bit 28 */
+#define CAN_F25R2_FB29_Pos (29U)
+#define CAN_F25R2_FB29_Msk (0x1U << CAN_F25R2_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F25R2_FB29 CAN_F25R2_FB29_Msk /*!< Filter bit 29 */
+#define CAN_F25R2_FB30_Pos (30U)
+#define CAN_F25R2_FB30_Msk (0x1U << CAN_F25R2_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F25R2_FB30 CAN_F25R2_FB30_Msk /*!< Filter bit 30 */
+#define CAN_F25R2_FB31_Pos (31U)
+#define CAN_F25R2_FB31_Msk (0x1U << CAN_F25R2_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F25R2_FB31 CAN_F25R2_FB31_Msk /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F26R2 register ******************/
+#define CAN_F26R2_FB0_Pos (0U)
+#define CAN_F26R2_FB0_Msk (0x1U << CAN_F26R2_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F26R2_FB0 CAN_F26R2_FB0_Msk /*!< Filter bit 0 */
+#define CAN_F26R2_FB1_Pos (1U)
+#define CAN_F26R2_FB1_Msk (0x1U << CAN_F26R2_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F26R2_FB1 CAN_F26R2_FB1_Msk /*!< Filter bit 1 */
+#define CAN_F26R2_FB2_Pos (2U)
+#define CAN_F26R2_FB2_Msk (0x1U << CAN_F26R2_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F26R2_FB2 CAN_F26R2_FB2_Msk /*!< Filter bit 2 */
+#define CAN_F26R2_FB3_Pos (3U)
+#define CAN_F26R2_FB3_Msk (0x1U << CAN_F26R2_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F26R2_FB3 CAN_F26R2_FB3_Msk /*!< Filter bit 3 */
+#define CAN_F26R2_FB4_Pos (4U)
+#define CAN_F26R2_FB4_Msk (0x1U << CAN_F26R2_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F26R2_FB4 CAN_F26R2_FB4_Msk /*!< Filter bit 4 */
+#define CAN_F26R2_FB5_Pos (5U)
+#define CAN_F26R2_FB5_Msk (0x1U << CAN_F26R2_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F26R2_FB5 CAN_F26R2_FB5_Msk /*!< Filter bit 5 */
+#define CAN_F26R2_FB6_Pos (6U)
+#define CAN_F26R2_FB6_Msk (0x1U << CAN_F26R2_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F26R2_FB6 CAN_F26R2_FB6_Msk /*!< Filter bit 6 */
+#define CAN_F26R2_FB7_Pos (7U)
+#define CAN_F26R2_FB7_Msk (0x1U << CAN_F26R2_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F26R2_FB7 CAN_F26R2_FB7_Msk /*!< Filter bit 7 */
+#define CAN_F26R2_FB8_Pos (8U)
+#define CAN_F26R2_FB8_Msk (0x1U << CAN_F26R2_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F26R2_FB8 CAN_F26R2_FB8_Msk /*!< Filter bit 8 */
+#define CAN_F26R2_FB9_Pos (9U)
+#define CAN_F26R2_FB9_Msk (0x1U << CAN_F26R2_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F26R2_FB9 CAN_F26R2_FB9_Msk /*!< Filter bit 9 */
+#define CAN_F26R2_FB10_Pos (10U)
+#define CAN_F26R2_FB10_Msk (0x1U << CAN_F26R2_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F26R2_FB10 CAN_F26R2_FB10_Msk /*!< Filter bit 10 */
+#define CAN_F26R2_FB11_Pos (11U)
+#define CAN_F26R2_FB11_Msk (0x1U << CAN_F26R2_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F26R2_FB11 CAN_F26R2_FB11_Msk /*!< Filter bit 11 */
+#define CAN_F26R2_FB12_Pos (12U)
+#define CAN_F26R2_FB12_Msk (0x1U << CAN_F26R2_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F26R2_FB12 CAN_F26R2_FB12_Msk /*!< Filter bit 12 */
+#define CAN_F26R2_FB13_Pos (13U)
+#define CAN_F26R2_FB13_Msk (0x1U << CAN_F26R2_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F26R2_FB13 CAN_F26R2_FB13_Msk /*!< Filter bit 13 */
+#define CAN_F26R2_FB14_Pos (14U)
+#define CAN_F26R2_FB14_Msk (0x1U << CAN_F26R2_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F26R2_FB14 CAN_F26R2_FB14_Msk /*!< Filter bit 14 */
+#define CAN_F26R2_FB15_Pos (15U)
+#define CAN_F26R2_FB15_Msk (0x1U << CAN_F26R2_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F26R2_FB15 CAN_F26R2_FB15_Msk /*!< Filter bit 15 */
+#define CAN_F26R2_FB16_Pos (16U)
+#define CAN_F26R2_FB16_Msk (0x1U << CAN_F26R2_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F26R2_FB16 CAN_F26R2_FB16_Msk /*!< Filter bit 16 */
+#define CAN_F26R2_FB17_Pos (17U)
+#define CAN_F26R2_FB17_Msk (0x1U << CAN_F26R2_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F26R2_FB17 CAN_F26R2_FB17_Msk /*!< Filter bit 17 */
+#define CAN_F26R2_FB18_Pos (18U)
+#define CAN_F26R2_FB18_Msk (0x1U << CAN_F26R2_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F26R2_FB18 CAN_F26R2_FB18_Msk /*!< Filter bit 18 */
+#define CAN_F26R2_FB19_Pos (19U)
+#define CAN_F26R2_FB19_Msk (0x1U << CAN_F26R2_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F26R2_FB19 CAN_F26R2_FB19_Msk /*!< Filter bit 19 */
+#define CAN_F26R2_FB20_Pos (20U)
+#define CAN_F26R2_FB20_Msk (0x1U << CAN_F26R2_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F26R2_FB20 CAN_F26R2_FB20_Msk /*!< Filter bit 20 */
+#define CAN_F26R2_FB21_Pos (21U)
+#define CAN_F26R2_FB21_Msk (0x1U << CAN_F26R2_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F26R2_FB21 CAN_F26R2_FB21_Msk /*!< Filter bit 21 */
+#define CAN_F26R2_FB22_Pos (22U)
+#define CAN_F26R2_FB22_Msk (0x1U << CAN_F26R2_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F26R2_FB22 CAN_F26R2_FB22_Msk /*!< Filter bit 22 */
+#define CAN_F26R2_FB23_Pos (23U)
+#define CAN_F26R2_FB23_Msk (0x1U << CAN_F26R2_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F26R2_FB23 CAN_F26R2_FB23_Msk /*!< Filter bit 23 */
+#define CAN_F26R2_FB24_Pos (24U)
+#define CAN_F26R2_FB24_Msk (0x1U << CAN_F26R2_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F26R2_FB24 CAN_F26R2_FB24_Msk /*!< Filter bit 24 */
+#define CAN_F26R2_FB25_Pos (25U)
+#define CAN_F26R2_FB25_Msk (0x1U << CAN_F26R2_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F26R2_FB25 CAN_F26R2_FB25_Msk /*!< Filter bit 25 */
+#define CAN_F26R2_FB26_Pos (26U)
+#define CAN_F26R2_FB26_Msk (0x1U << CAN_F26R2_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F26R2_FB26 CAN_F26R2_FB26_Msk /*!< Filter bit 26 */
+#define CAN_F26R2_FB27_Pos (27U)
+#define CAN_F26R2_FB27_Msk (0x1U << CAN_F26R2_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F26R2_FB27 CAN_F26R2_FB27_Msk /*!< Filter bit 27 */
+#define CAN_F26R2_FB28_Pos (28U)
+#define CAN_F26R2_FB28_Msk (0x1U << CAN_F26R2_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F26R2_FB28 CAN_F26R2_FB28_Msk /*!< Filter bit 28 */
+#define CAN_F26R2_FB29_Pos (29U)
+#define CAN_F26R2_FB29_Msk (0x1U << CAN_F26R2_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F26R2_FB29 CAN_F26R2_FB29_Msk /*!< Filter bit 29 */
+#define CAN_F26R2_FB30_Pos (30U)
+#define CAN_F26R2_FB30_Msk (0x1U << CAN_F26R2_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F26R2_FB30 CAN_F26R2_FB30_Msk /*!< Filter bit 30 */
+#define CAN_F26R2_FB31_Pos (31U)
+#define CAN_F26R2_FB31_Msk (0x1U << CAN_F26R2_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F26R2_FB31 CAN_F26R2_FB31_Msk /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F27R2 register ******************/
+#define CAN_F27R2_FB0_Pos (0U)
+#define CAN_F27R2_FB0_Msk (0x1U << CAN_F27R2_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F27R2_FB0 CAN_F27R2_FB0_Msk /*!< Filter bit 0 */
+#define CAN_F27R2_FB1_Pos (1U)
+#define CAN_F27R2_FB1_Msk (0x1U << CAN_F27R2_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F27R2_FB1 CAN_F27R2_FB1_Msk /*!< Filter bit 1 */
+#define CAN_F27R2_FB2_Pos (2U)
+#define CAN_F27R2_FB2_Msk (0x1U << CAN_F27R2_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F27R2_FB2 CAN_F27R2_FB2_Msk /*!< Filter bit 2 */
+#define CAN_F27R2_FB3_Pos (3U)
+#define CAN_F27R2_FB3_Msk (0x1U << CAN_F27R2_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F27R2_FB3 CAN_F27R2_FB3_Msk /*!< Filter bit 3 */
+#define CAN_F27R2_FB4_Pos (4U)
+#define CAN_F27R2_FB4_Msk (0x1U << CAN_F27R2_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F27R2_FB4 CAN_F27R2_FB4_Msk /*!< Filter bit 4 */
+#define CAN_F27R2_FB5_Pos (5U)
+#define CAN_F27R2_FB5_Msk (0x1U << CAN_F27R2_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F27R2_FB5 CAN_F27R2_FB5_Msk /*!< Filter bit 5 */
+#define CAN_F27R2_FB6_Pos (6U)
+#define CAN_F27R2_FB6_Msk (0x1U << CAN_F27R2_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F27R2_FB6 CAN_F27R2_FB6_Msk /*!< Filter bit 6 */
+#define CAN_F27R2_FB7_Pos (7U)
+#define CAN_F27R2_FB7_Msk (0x1U << CAN_F27R2_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F27R2_FB7 CAN_F27R2_FB7_Msk /*!< Filter bit 7 */
+#define CAN_F27R2_FB8_Pos (8U)
+#define CAN_F27R2_FB8_Msk (0x1U << CAN_F27R2_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F27R2_FB8 CAN_F27R2_FB8_Msk /*!< Filter bit 8 */
+#define CAN_F27R2_FB9_Pos (9U)
+#define CAN_F27R2_FB9_Msk (0x1U << CAN_F27R2_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F27R2_FB9 CAN_F27R2_FB9_Msk /*!< Filter bit 9 */
+#define CAN_F27R2_FB10_Pos (10U)
+#define CAN_F27R2_FB10_Msk (0x1U << CAN_F27R2_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F27R2_FB10 CAN_F27R2_FB10_Msk /*!< Filter bit 10 */
+#define CAN_F27R2_FB11_Pos (11U)
+#define CAN_F27R2_FB11_Msk (0x1U << CAN_F27R2_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F27R2_FB11 CAN_F27R2_FB11_Msk /*!< Filter bit 11 */
+#define CAN_F27R2_FB12_Pos (12U)
+#define CAN_F27R2_FB12_Msk (0x1U << CAN_F27R2_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F27R2_FB12 CAN_F27R2_FB12_Msk /*!< Filter bit 12 */
+#define CAN_F27R2_FB13_Pos (13U)
+#define CAN_F27R2_FB13_Msk (0x1U << CAN_F27R2_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F27R2_FB13 CAN_F27R2_FB13_Msk /*!< Filter bit 13 */
+#define CAN_F27R2_FB14_Pos (14U)
+#define CAN_F27R2_FB14_Msk (0x1U << CAN_F27R2_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F27R2_FB14 CAN_F27R2_FB14_Msk /*!< Filter bit 14 */
+#define CAN_F27R2_FB15_Pos (15U)
+#define CAN_F27R2_FB15_Msk (0x1U << CAN_F27R2_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F27R2_FB15 CAN_F27R2_FB15_Msk /*!< Filter bit 15 */
+#define CAN_F27R2_FB16_Pos (16U)
+#define CAN_F27R2_FB16_Msk (0x1U << CAN_F27R2_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F27R2_FB16 CAN_F27R2_FB16_Msk /*!< Filter bit 16 */
+#define CAN_F27R2_FB17_Pos (17U)
+#define CAN_F27R2_FB17_Msk (0x1U << CAN_F27R2_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F27R2_FB17 CAN_F27R2_FB17_Msk /*!< Filter bit 17 */
+#define CAN_F27R2_FB18_Pos (18U)
+#define CAN_F27R2_FB18_Msk (0x1U << CAN_F27R2_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F27R2_FB18 CAN_F27R2_FB18_Msk /*!< Filter bit 18 */
+#define CAN_F27R2_FB19_Pos (19U)
+#define CAN_F27R2_FB19_Msk (0x1U << CAN_F27R2_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F27R2_FB19 CAN_F27R2_FB19_Msk /*!< Filter bit 19 */
+#define CAN_F27R2_FB20_Pos (20U)
+#define CAN_F27R2_FB20_Msk (0x1U << CAN_F27R2_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F27R2_FB20 CAN_F27R2_FB20_Msk /*!< Filter bit 20 */
+#define CAN_F27R2_FB21_Pos (21U)
+#define CAN_F27R2_FB21_Msk (0x1U << CAN_F27R2_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F27R2_FB21 CAN_F27R2_FB21_Msk /*!< Filter bit 21 */
+#define CAN_F27R2_FB22_Pos (22U)
+#define CAN_F27R2_FB22_Msk (0x1U << CAN_F27R2_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F27R2_FB22 CAN_F27R2_FB22_Msk /*!< Filter bit 22 */
+#define CAN_F27R2_FB23_Pos (23U)
+#define CAN_F27R2_FB23_Msk (0x1U << CAN_F27R2_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F27R2_FB23 CAN_F27R2_FB23_Msk /*!< Filter bit 23 */
+#define CAN_F27R2_FB24_Pos (24U)
+#define CAN_F27R2_FB24_Msk (0x1U << CAN_F27R2_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F27R2_FB24 CAN_F27R2_FB24_Msk /*!< Filter bit 24 */
+#define CAN_F27R2_FB25_Pos (25U)
+#define CAN_F27R2_FB25_Msk (0x1U << CAN_F27R2_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F27R2_FB25 CAN_F27R2_FB25_Msk /*!< Filter bit 25 */
+#define CAN_F27R2_FB26_Pos (26U)
+#define CAN_F27R2_FB26_Msk (0x1U << CAN_F27R2_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F27R2_FB26 CAN_F27R2_FB26_Msk /*!< Filter bit 26 */
+#define CAN_F27R2_FB27_Pos (27U)
+#define CAN_F27R2_FB27_Msk (0x1U << CAN_F27R2_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F27R2_FB27 CAN_F27R2_FB27_Msk /*!< Filter bit 27 */
+#define CAN_F27R2_FB28_Pos (28U)
+#define CAN_F27R2_FB28_Msk (0x1U << CAN_F27R2_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F27R2_FB28 CAN_F27R2_FB28_Msk /*!< Filter bit 28 */
+#define CAN_F27R2_FB29_Pos (29U)
+#define CAN_F27R2_FB29_Msk (0x1U << CAN_F27R2_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F27R2_FB29 CAN_F27R2_FB29_Msk /*!< Filter bit 29 */
+#define CAN_F27R2_FB30_Pos (30U)
+#define CAN_F27R2_FB30_Msk (0x1U << CAN_F27R2_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F27R2_FB30 CAN_F27R2_FB30_Msk /*!< Filter bit 30 */
+#define CAN_F27R2_FB31_Pos (31U)
+#define CAN_F27R2_FB31_Msk (0x1U << CAN_F27R2_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F27R2_FB31 CAN_F27R2_FB31_Msk /*!< Filter bit 31 */
+
+/******************************************************************************/
+/* */
+/* Serial Peripheral Interface */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for SPI_CR1 register ********************/
+#define SPI_CR1_CPHA_Pos (0U)
+#define SPI_CR1_CPHA_Msk (0x1U << SPI_CR1_CPHA_Pos) /*!< 0x00000001 */
+#define SPI_CR1_CPHA SPI_CR1_CPHA_Msk /*!< Clock Phase */
+#define SPI_CR1_CPOL_Pos (1U)
+#define SPI_CR1_CPOL_Msk (0x1U << SPI_CR1_CPOL_Pos) /*!< 0x00000002 */
+#define SPI_CR1_CPOL SPI_CR1_CPOL_Msk /*!< Clock Polarity */
+#define SPI_CR1_MSTR_Pos (2U)
+#define SPI_CR1_MSTR_Msk (0x1U << SPI_CR1_MSTR_Pos) /*!< 0x00000004 */
+#define SPI_CR1_MSTR SPI_CR1_MSTR_Msk /*!< Master Selection */
+
+#define SPI_CR1_BR_Pos (3U)
+#define SPI_CR1_BR_Msk (0x7U << SPI_CR1_BR_Pos) /*!< 0x00000038 */
+#define SPI_CR1_BR SPI_CR1_BR_Msk /*!< BR[2:0] bits (Baud Rate Control) */
+#define SPI_CR1_BR_0 (0x1U << SPI_CR1_BR_Pos) /*!< 0x00000008 */
+#define SPI_CR1_BR_1 (0x2U << SPI_CR1_BR_Pos) /*!< 0x00000010 */
+#define SPI_CR1_BR_2 (0x4U << SPI_CR1_BR_Pos) /*!< 0x00000020 */
+
+#define SPI_CR1_SPE_Pos (6U)
+#define SPI_CR1_SPE_Msk (0x1U << SPI_CR1_SPE_Pos) /*!< 0x00000040 */
+#define SPI_CR1_SPE SPI_CR1_SPE_Msk /*!< SPI Enable */
+#define SPI_CR1_LSBFIRST_Pos (7U)
+#define SPI_CR1_LSBFIRST_Msk (0x1U << SPI_CR1_LSBFIRST_Pos) /*!< 0x00000080 */
+#define SPI_CR1_LSBFIRST SPI_CR1_LSBFIRST_Msk /*!< Frame Format */
+#define SPI_CR1_SSI_Pos (8U)
+#define SPI_CR1_SSI_Msk (0x1U << SPI_CR1_SSI_Pos) /*!< 0x00000100 */
+#define SPI_CR1_SSI SPI_CR1_SSI_Msk /*!< Internal slave select */
+#define SPI_CR1_SSM_Pos (9U)
+#define SPI_CR1_SSM_Msk (0x1U << SPI_CR1_SSM_Pos) /*!< 0x00000200 */
+#define SPI_CR1_SSM SPI_CR1_SSM_Msk /*!< Software slave management */
+#define SPI_CR1_RXONLY_Pos (10U)
+#define SPI_CR1_RXONLY_Msk (0x1U << SPI_CR1_RXONLY_Pos) /*!< 0x00000400 */
+#define SPI_CR1_RXONLY SPI_CR1_RXONLY_Msk /*!< Receive only */
+#define SPI_CR1_DFF_Pos (11U)
+#define SPI_CR1_DFF_Msk (0x1U << SPI_CR1_DFF_Pos) /*!< 0x00000800 */
+#define SPI_CR1_DFF SPI_CR1_DFF_Msk /*!< Data Frame Format */
+#define SPI_CR1_CRCNEXT_Pos (12U)
+#define SPI_CR1_CRCNEXT_Msk (0x1U << SPI_CR1_CRCNEXT_Pos) /*!< 0x00001000 */
+#define SPI_CR1_CRCNEXT SPI_CR1_CRCNEXT_Msk /*!< Transmit CRC next */
+#define SPI_CR1_CRCEN_Pos (13U)
+#define SPI_CR1_CRCEN_Msk (0x1U << SPI_CR1_CRCEN_Pos) /*!< 0x00002000 */
+#define SPI_CR1_CRCEN SPI_CR1_CRCEN_Msk /*!< Hardware CRC calculation enable */
+#define SPI_CR1_BIDIOE_Pos (14U)
+#define SPI_CR1_BIDIOE_Msk (0x1U << SPI_CR1_BIDIOE_Pos) /*!< 0x00004000 */
+#define SPI_CR1_BIDIOE SPI_CR1_BIDIOE_Msk /*!< Output enable in bidirectional mode */
+#define SPI_CR1_BIDIMODE_Pos (15U)
+#define SPI_CR1_BIDIMODE_Msk (0x1U << SPI_CR1_BIDIMODE_Pos) /*!< 0x00008000 */
+#define SPI_CR1_BIDIMODE SPI_CR1_BIDIMODE_Msk /*!< Bidirectional data mode enable */
+
+/******************* Bit definition for SPI_CR2 register ********************/
+#define SPI_CR2_RXDMAEN_Pos (0U)
+#define SPI_CR2_RXDMAEN_Msk (0x1U << SPI_CR2_RXDMAEN_Pos) /*!< 0x00000001 */
+#define SPI_CR2_RXDMAEN SPI_CR2_RXDMAEN_Msk /*!< Rx Buffer DMA Enable */
+#define SPI_CR2_TXDMAEN_Pos (1U)
+#define SPI_CR2_TXDMAEN_Msk (0x1U << SPI_CR2_TXDMAEN_Pos) /*!< 0x00000002 */
+#define SPI_CR2_TXDMAEN SPI_CR2_TXDMAEN_Msk /*!< Tx Buffer DMA Enable */
+#define SPI_CR2_SSOE_Pos (2U)
+#define SPI_CR2_SSOE_Msk (0x1U << SPI_CR2_SSOE_Pos) /*!< 0x00000004 */
+#define SPI_CR2_SSOE SPI_CR2_SSOE_Msk /*!< SS Output Enable */
+#define SPI_CR2_ERRIE_Pos (5U)
+#define SPI_CR2_ERRIE_Msk (0x1U << SPI_CR2_ERRIE_Pos) /*!< 0x00000020 */
+#define SPI_CR2_ERRIE SPI_CR2_ERRIE_Msk /*!< Error Interrupt Enable */
+#define SPI_CR2_RXNEIE_Pos (6U)
+#define SPI_CR2_RXNEIE_Msk (0x1U << SPI_CR2_RXNEIE_Pos) /*!< 0x00000040 */
+#define SPI_CR2_RXNEIE SPI_CR2_RXNEIE_Msk /*!< RX buffer Not Empty Interrupt Enable */
+#define SPI_CR2_TXEIE_Pos (7U)
+#define SPI_CR2_TXEIE_Msk (0x1U << SPI_CR2_TXEIE_Pos) /*!< 0x00000080 */
+#define SPI_CR2_TXEIE SPI_CR2_TXEIE_Msk /*!< Tx buffer Empty Interrupt Enable */
+
+/******************** Bit definition for SPI_SR register ********************/
+#define SPI_SR_RXNE_Pos (0U)
+#define SPI_SR_RXNE_Msk (0x1U << SPI_SR_RXNE_Pos) /*!< 0x00000001 */
+#define SPI_SR_RXNE SPI_SR_RXNE_Msk /*!< Receive buffer Not Empty */
+#define SPI_SR_TXE_Pos (1U)
+#define SPI_SR_TXE_Msk (0x1U << SPI_SR_TXE_Pos) /*!< 0x00000002 */
+#define SPI_SR_TXE SPI_SR_TXE_Msk /*!< Transmit buffer Empty */
+#define SPI_SR_CHSIDE_Pos (2U)
+#define SPI_SR_CHSIDE_Msk (0x1U << SPI_SR_CHSIDE_Pos) /*!< 0x00000004 */
+#define SPI_SR_CHSIDE SPI_SR_CHSIDE_Msk /*!< Channel side */
+#define SPI_SR_UDR_Pos (3U)
+#define SPI_SR_UDR_Msk (0x1U << SPI_SR_UDR_Pos) /*!< 0x00000008 */
+#define SPI_SR_UDR SPI_SR_UDR_Msk /*!< Underrun flag */
+#define SPI_SR_CRCERR_Pos (4U)
+#define SPI_SR_CRCERR_Msk (0x1U << SPI_SR_CRCERR_Pos) /*!< 0x00000010 */
+#define SPI_SR_CRCERR SPI_SR_CRCERR_Msk /*!< CRC Error flag */
+#define SPI_SR_MODF_Pos (5U)
+#define SPI_SR_MODF_Msk (0x1U << SPI_SR_MODF_Pos) /*!< 0x00000020 */
+#define SPI_SR_MODF SPI_SR_MODF_Msk /*!< Mode fault */
+#define SPI_SR_OVR_Pos (6U)
+#define SPI_SR_OVR_Msk (0x1U << SPI_SR_OVR_Pos) /*!< 0x00000040 */
+#define SPI_SR_OVR SPI_SR_OVR_Msk /*!< Overrun flag */
+#define SPI_SR_BSY_Pos (7U)
+#define SPI_SR_BSY_Msk (0x1U << SPI_SR_BSY_Pos) /*!< 0x00000080 */
+#define SPI_SR_BSY SPI_SR_BSY_Msk /*!< Busy flag */
+
+/******************** Bit definition for SPI_DR register ********************/
+#define SPI_DR_DR_Pos (0U)
+#define SPI_DR_DR_Msk (0xFFFFU << SPI_DR_DR_Pos) /*!< 0x0000FFFF */
+#define SPI_DR_DR SPI_DR_DR_Msk /*!< Data Register */
+
+/******************* Bit definition for SPI_CRCPR register ******************/
+#define SPI_CRCPR_CRCPOLY_Pos (0U)
+#define SPI_CRCPR_CRCPOLY_Msk (0xFFFFU << SPI_CRCPR_CRCPOLY_Pos) /*!< 0x0000FFFF */
+#define SPI_CRCPR_CRCPOLY SPI_CRCPR_CRCPOLY_Msk /*!< CRC polynomial register */
+
+/****************** Bit definition for SPI_RXCRCR register ******************/
+#define SPI_RXCRCR_RXCRC_Pos (0U)
+#define SPI_RXCRCR_RXCRC_Msk (0xFFFFU << SPI_RXCRCR_RXCRC_Pos) /*!< 0x0000FFFF */
+#define SPI_RXCRCR_RXCRC SPI_RXCRCR_RXCRC_Msk /*!< Rx CRC Register */
+
+/****************** Bit definition for SPI_TXCRCR register ******************/
+#define SPI_TXCRCR_TXCRC_Pos (0U)
+#define SPI_TXCRCR_TXCRC_Msk (0xFFFFU << SPI_TXCRCR_TXCRC_Pos) /*!< 0x0000FFFF */
+#define SPI_TXCRCR_TXCRC SPI_TXCRCR_TXCRC_Msk /*!< Tx CRC Register */
+
+/****************** Bit definition for SPI_I2SCFGR register *****************/
+#define SPI_I2SCFGR_CHLEN_Pos (0U)
+#define SPI_I2SCFGR_CHLEN_Msk (0x1U << SPI_I2SCFGR_CHLEN_Pos) /*!< 0x00000001 */
+#define SPI_I2SCFGR_CHLEN SPI_I2SCFGR_CHLEN_Msk /*!< Channel length (number of bits per audio channel) */
+
+#define SPI_I2SCFGR_DATLEN_Pos (1U)
+#define SPI_I2SCFGR_DATLEN_Msk (0x3U << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000006 */
+#define SPI_I2SCFGR_DATLEN SPI_I2SCFGR_DATLEN_Msk /*!< DATLEN[1:0] bits (Data length to be transferred) */
+#define SPI_I2SCFGR_DATLEN_0 (0x1U << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000002 */
+#define SPI_I2SCFGR_DATLEN_1 (0x2U << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000004 */
+
+#define SPI_I2SCFGR_CKPOL_Pos (3U)
+#define SPI_I2SCFGR_CKPOL_Msk (0x1U << SPI_I2SCFGR_CKPOL_Pos) /*!< 0x00000008 */
+#define SPI_I2SCFGR_CKPOL SPI_I2SCFGR_CKPOL_Msk /*!< steady state clock polarity */
+
+#define SPI_I2SCFGR_I2SSTD_Pos (4U)
+#define SPI_I2SCFGR_I2SSTD_Msk (0x3U << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000030 */
+#define SPI_I2SCFGR_I2SSTD SPI_I2SCFGR_I2SSTD_Msk /*!< I2SSTD[1:0] bits (I2S standard selection) */
+#define SPI_I2SCFGR_I2SSTD_0 (0x1U << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000010 */
+#define SPI_I2SCFGR_I2SSTD_1 (0x2U << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000020 */
+
+#define SPI_I2SCFGR_PCMSYNC_Pos (7U)
+#define SPI_I2SCFGR_PCMSYNC_Msk (0x1U << SPI_I2SCFGR_PCMSYNC_Pos) /*!< 0x00000080 */
+#define SPI_I2SCFGR_PCMSYNC SPI_I2SCFGR_PCMSYNC_Msk /*!< PCM frame synchronization */
+
+#define SPI_I2SCFGR_I2SCFG_Pos (8U)
+#define SPI_I2SCFGR_I2SCFG_Msk (0x3U << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000300 */
+#define SPI_I2SCFGR_I2SCFG SPI_I2SCFGR_I2SCFG_Msk /*!< I2SCFG[1:0] bits (I2S configuration mode) */
+#define SPI_I2SCFGR_I2SCFG_0 (0x1U << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000100 */
+#define SPI_I2SCFGR_I2SCFG_1 (0x2U << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000200 */
+
+#define SPI_I2SCFGR_I2SE_Pos (10U)
+#define SPI_I2SCFGR_I2SE_Msk (0x1U << SPI_I2SCFGR_I2SE_Pos) /*!< 0x00000400 */
+#define SPI_I2SCFGR_I2SE SPI_I2SCFGR_I2SE_Msk /*!< I2S Enable */
+#define SPI_I2SCFGR_I2SMOD_Pos (11U)
+#define SPI_I2SCFGR_I2SMOD_Msk (0x1U << SPI_I2SCFGR_I2SMOD_Pos) /*!< 0x00000800 */
+#define SPI_I2SCFGR_I2SMOD SPI_I2SCFGR_I2SMOD_Msk /*!< I2S mode selection */
+
+/****************** Bit definition for SPI_I2SPR register *******************/
+#define SPI_I2SPR_I2SDIV_Pos (0U)
+#define SPI_I2SPR_I2SDIV_Msk (0xFFU << SPI_I2SPR_I2SDIV_Pos) /*!< 0x000000FF */
+#define SPI_I2SPR_I2SDIV SPI_I2SPR_I2SDIV_Msk /*!< I2S Linear prescaler */
+#define SPI_I2SPR_ODD_Pos (8U)
+#define SPI_I2SPR_ODD_Msk (0x1U << SPI_I2SPR_ODD_Pos) /*!< 0x00000100 */
+#define SPI_I2SPR_ODD SPI_I2SPR_ODD_Msk /*!< Odd factor for the prescaler */
+#define SPI_I2SPR_MCKOE_Pos (9U)
+#define SPI_I2SPR_MCKOE_Msk (0x1U << SPI_I2SPR_MCKOE_Pos) /*!< 0x00000200 */
+#define SPI_I2SPR_MCKOE SPI_I2SPR_MCKOE_Msk /*!< Master Clock Output Enable */
+
+/******************************************************************************/
+/* */
+/* Inter-integrated Circuit Interface */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for I2C_CR1 register ********************/
+#define I2C_CR1_PE_Pos (0U)
+#define I2C_CR1_PE_Msk (0x1U << I2C_CR1_PE_Pos) /*!< 0x00000001 */
+#define I2C_CR1_PE I2C_CR1_PE_Msk /*!< Peripheral Enable */
+#define I2C_CR1_SMBUS_Pos (1U)
+#define I2C_CR1_SMBUS_Msk (0x1U << I2C_CR1_SMBUS_Pos) /*!< 0x00000002 */
+#define I2C_CR1_SMBUS I2C_CR1_SMBUS_Msk /*!< SMBus Mode */
+#define I2C_CR1_SMBTYPE_Pos (3U)
+#define I2C_CR1_SMBTYPE_Msk (0x1U << I2C_CR1_SMBTYPE_Pos) /*!< 0x00000008 */
+#define I2C_CR1_SMBTYPE I2C_CR1_SMBTYPE_Msk /*!< SMBus Type */
+#define I2C_CR1_ENARP_Pos (4U)
+#define I2C_CR1_ENARP_Msk (0x1U << I2C_CR1_ENARP_Pos) /*!< 0x00000010 */
+#define I2C_CR1_ENARP I2C_CR1_ENARP_Msk /*!< ARP Enable */
+#define I2C_CR1_ENPEC_Pos (5U)
+#define I2C_CR1_ENPEC_Msk (0x1U << I2C_CR1_ENPEC_Pos) /*!< 0x00000020 */
+#define I2C_CR1_ENPEC I2C_CR1_ENPEC_Msk /*!< PEC Enable */
+#define I2C_CR1_ENGC_Pos (6U)
+#define I2C_CR1_ENGC_Msk (0x1U << I2C_CR1_ENGC_Pos) /*!< 0x00000040 */
+#define I2C_CR1_ENGC I2C_CR1_ENGC_Msk /*!< General Call Enable */
+#define I2C_CR1_NOSTRETCH_Pos (7U)
+#define I2C_CR1_NOSTRETCH_Msk (0x1U << I2C_CR1_NOSTRETCH_Pos) /*!< 0x00000080 */
+#define I2C_CR1_NOSTRETCH I2C_CR1_NOSTRETCH_Msk /*!< Clock Stretching Disable (Slave mode) */
+#define I2C_CR1_START_Pos (8U)
+#define I2C_CR1_START_Msk (0x1U << I2C_CR1_START_Pos) /*!< 0x00000100 */
+#define I2C_CR1_START I2C_CR1_START_Msk /*!< Start Generation */
+#define I2C_CR1_STOP_Pos (9U)
+#define I2C_CR1_STOP_Msk (0x1U << I2C_CR1_STOP_Pos) /*!< 0x00000200 */
+#define I2C_CR1_STOP I2C_CR1_STOP_Msk /*!< Stop Generation */
+#define I2C_CR1_ACK_Pos (10U)
+#define I2C_CR1_ACK_Msk (0x1U << I2C_CR1_ACK_Pos) /*!< 0x00000400 */
+#define I2C_CR1_ACK I2C_CR1_ACK_Msk /*!< Acknowledge Enable */
+#define I2C_CR1_POS_Pos (11U)
+#define I2C_CR1_POS_Msk (0x1U << I2C_CR1_POS_Pos) /*!< 0x00000800 */
+#define I2C_CR1_POS I2C_CR1_POS_Msk /*!< Acknowledge/PEC Position (for data reception) */
+#define I2C_CR1_PEC_Pos (12U)
+#define I2C_CR1_PEC_Msk (0x1U << I2C_CR1_PEC_Pos) /*!< 0x00001000 */
+#define I2C_CR1_PEC I2C_CR1_PEC_Msk /*!< Packet Error Checking */
+#define I2C_CR1_ALERT_Pos (13U)
+#define I2C_CR1_ALERT_Msk (0x1U << I2C_CR1_ALERT_Pos) /*!< 0x00002000 */
+#define I2C_CR1_ALERT I2C_CR1_ALERT_Msk /*!< SMBus Alert */
+#define I2C_CR1_SWRST_Pos (15U)
+#define I2C_CR1_SWRST_Msk (0x1U << I2C_CR1_SWRST_Pos) /*!< 0x00008000 */
+#define I2C_CR1_SWRST I2C_CR1_SWRST_Msk /*!< Software Reset */
+
+/******************* Bit definition for I2C_CR2 register ********************/
+#define I2C_CR2_FREQ_Pos (0U)
+#define I2C_CR2_FREQ_Msk (0x3FU << I2C_CR2_FREQ_Pos) /*!< 0x0000003F */
+#define I2C_CR2_FREQ I2C_CR2_FREQ_Msk /*!< FREQ[5:0] bits (Peripheral Clock Frequency) */
+#define I2C_CR2_FREQ_0 (0x01U << I2C_CR2_FREQ_Pos) /*!< 0x00000001 */
+#define I2C_CR2_FREQ_1 (0x02U << I2C_CR2_FREQ_Pos) /*!< 0x00000002 */
+#define I2C_CR2_FREQ_2 (0x04U << I2C_CR2_FREQ_Pos) /*!< 0x00000004 */
+#define I2C_CR2_FREQ_3 (0x08U << I2C_CR2_FREQ_Pos) /*!< 0x00000008 */
+#define I2C_CR2_FREQ_4 (0x10U << I2C_CR2_FREQ_Pos) /*!< 0x00000010 */
+#define I2C_CR2_FREQ_5 (0x20U << I2C_CR2_FREQ_Pos) /*!< 0x00000020 */
+
+#define I2C_CR2_ITERREN_Pos (8U)
+#define I2C_CR2_ITERREN_Msk (0x1U << I2C_CR2_ITERREN_Pos) /*!< 0x00000100 */
+#define I2C_CR2_ITERREN I2C_CR2_ITERREN_Msk /*!< Error Interrupt Enable */
+#define I2C_CR2_ITEVTEN_Pos (9U)
+#define I2C_CR2_ITEVTEN_Msk (0x1U << I2C_CR2_ITEVTEN_Pos) /*!< 0x00000200 */
+#define I2C_CR2_ITEVTEN I2C_CR2_ITEVTEN_Msk /*!< Event Interrupt Enable */
+#define I2C_CR2_ITBUFEN_Pos (10U)
+#define I2C_CR2_ITBUFEN_Msk (0x1U << I2C_CR2_ITBUFEN_Pos) /*!< 0x00000400 */
+#define I2C_CR2_ITBUFEN I2C_CR2_ITBUFEN_Msk /*!< Buffer Interrupt Enable */
+#define I2C_CR2_DMAEN_Pos (11U)
+#define I2C_CR2_DMAEN_Msk (0x1U << I2C_CR2_DMAEN_Pos) /*!< 0x00000800 */
+#define I2C_CR2_DMAEN I2C_CR2_DMAEN_Msk /*!< DMA Requests Enable */
+#define I2C_CR2_LAST_Pos (12U)
+#define I2C_CR2_LAST_Msk (0x1U << I2C_CR2_LAST_Pos) /*!< 0x00001000 */
+#define I2C_CR2_LAST I2C_CR2_LAST_Msk /*!< DMA Last Transfer */
+
+/******************* Bit definition for I2C_OAR1 register *******************/
+#define I2C_OAR1_ADD1_7 ((uint32_t)0x000000FE) /*!< Interface Address */
+#define I2C_OAR1_ADD8_9 ((uint32_t)0x00000300) /*!< Interface Address */
+
+#define I2C_OAR1_ADD0_Pos (0U)
+#define I2C_OAR1_ADD0_Msk (0x1U << I2C_OAR1_ADD0_Pos) /*!< 0x00000001 */
+#define I2C_OAR1_ADD0 I2C_OAR1_ADD0_Msk /*!< Bit 0 */
+#define I2C_OAR1_ADD1_Pos (1U)
+#define I2C_OAR1_ADD1_Msk (0x1U << I2C_OAR1_ADD1_Pos) /*!< 0x00000002 */
+#define I2C_OAR1_ADD1 I2C_OAR1_ADD1_Msk /*!< Bit 1 */
+#define I2C_OAR1_ADD2_Pos (2U)
+#define I2C_OAR1_ADD2_Msk (0x1U << I2C_OAR1_ADD2_Pos) /*!< 0x00000004 */
+#define I2C_OAR1_ADD2 I2C_OAR1_ADD2_Msk /*!< Bit 2 */
+#define I2C_OAR1_ADD3_Pos (3U)
+#define I2C_OAR1_ADD3_Msk (0x1U << I2C_OAR1_ADD3_Pos) /*!< 0x00000008 */
+#define I2C_OAR1_ADD3 I2C_OAR1_ADD3_Msk /*!< Bit 3 */
+#define I2C_OAR1_ADD4_Pos (4U)
+#define I2C_OAR1_ADD4_Msk (0x1U << I2C_OAR1_ADD4_Pos) /*!< 0x00000010 */
+#define I2C_OAR1_ADD4 I2C_OAR1_ADD4_Msk /*!< Bit 4 */
+#define I2C_OAR1_ADD5_Pos (5U)
+#define I2C_OAR1_ADD5_Msk (0x1U << I2C_OAR1_ADD5_Pos) /*!< 0x00000020 */
+#define I2C_OAR1_ADD5 I2C_OAR1_ADD5_Msk /*!< Bit 5 */
+#define I2C_OAR1_ADD6_Pos (6U)
+#define I2C_OAR1_ADD6_Msk (0x1U << I2C_OAR1_ADD6_Pos) /*!< 0x00000040 */
+#define I2C_OAR1_ADD6 I2C_OAR1_ADD6_Msk /*!< Bit 6 */
+#define I2C_OAR1_ADD7_Pos (7U)
+#define I2C_OAR1_ADD7_Msk (0x1U << I2C_OAR1_ADD7_Pos) /*!< 0x00000080 */
+#define I2C_OAR1_ADD7 I2C_OAR1_ADD7_Msk /*!< Bit 7 */
+#define I2C_OAR1_ADD8_Pos (8U)
+#define I2C_OAR1_ADD8_Msk (0x1U << I2C_OAR1_ADD8_Pos) /*!< 0x00000100 */
+#define I2C_OAR1_ADD8 I2C_OAR1_ADD8_Msk /*!< Bit 8 */
+#define I2C_OAR1_ADD9_Pos (9U)
+#define I2C_OAR1_ADD9_Msk (0x1U << I2C_OAR1_ADD9_Pos) /*!< 0x00000200 */
+#define I2C_OAR1_ADD9 I2C_OAR1_ADD9_Msk /*!< Bit 9 */
+
+#define I2C_OAR1_ADDMODE_Pos (15U)
+#define I2C_OAR1_ADDMODE_Msk (0x1U << I2C_OAR1_ADDMODE_Pos) /*!< 0x00008000 */
+#define I2C_OAR1_ADDMODE I2C_OAR1_ADDMODE_Msk /*!< Addressing Mode (Slave mode) */
+
+/******************* Bit definition for I2C_OAR2 register *******************/
+#define I2C_OAR2_ENDUAL_Pos (0U)
+#define I2C_OAR2_ENDUAL_Msk (0x1U << I2C_OAR2_ENDUAL_Pos) /*!< 0x00000001 */
+#define I2C_OAR2_ENDUAL I2C_OAR2_ENDUAL_Msk /*!< Dual addressing mode enable */
+#define I2C_OAR2_ADD2_Pos (1U)
+#define I2C_OAR2_ADD2_Msk (0x7FU << I2C_OAR2_ADD2_Pos) /*!< 0x000000FE */
+#define I2C_OAR2_ADD2 I2C_OAR2_ADD2_Msk /*!< Interface address */
+
+/******************* Bit definition for I2C_SR1 register ********************/
+#define I2C_SR1_SB_Pos (0U)
+#define I2C_SR1_SB_Msk (0x1U << I2C_SR1_SB_Pos) /*!< 0x00000001 */
+#define I2C_SR1_SB I2C_SR1_SB_Msk /*!< Start Bit (Master mode) */
+#define I2C_SR1_ADDR_Pos (1U)
+#define I2C_SR1_ADDR_Msk (0x1U << I2C_SR1_ADDR_Pos) /*!< 0x00000002 */
+#define I2C_SR1_ADDR I2C_SR1_ADDR_Msk /*!< Address sent (master mode)/matched (slave mode) */
+#define I2C_SR1_BTF_Pos (2U)
+#define I2C_SR1_BTF_Msk (0x1U << I2C_SR1_BTF_Pos) /*!< 0x00000004 */
+#define I2C_SR1_BTF I2C_SR1_BTF_Msk /*!< Byte Transfer Finished */
+#define I2C_SR1_ADD10_Pos (3U)
+#define I2C_SR1_ADD10_Msk (0x1U << I2C_SR1_ADD10_Pos) /*!< 0x00000008 */
+#define I2C_SR1_ADD10 I2C_SR1_ADD10_Msk /*!< 10-bit header sent (Master mode) */
+#define I2C_SR1_STOPF_Pos (4U)
+#define I2C_SR1_STOPF_Msk (0x1U << I2C_SR1_STOPF_Pos) /*!< 0x00000010 */
+#define I2C_SR1_STOPF I2C_SR1_STOPF_Msk /*!< Stop detection (Slave mode) */
+#define I2C_SR1_RXNE_Pos (6U)
+#define I2C_SR1_RXNE_Msk (0x1U << I2C_SR1_RXNE_Pos) /*!< 0x00000040 */
+#define I2C_SR1_RXNE I2C_SR1_RXNE_Msk /*!< Data Register not Empty (receivers) */
+#define I2C_SR1_TXE_Pos (7U)
+#define I2C_SR1_TXE_Msk (0x1U << I2C_SR1_TXE_Pos) /*!< 0x00000080 */
+#define I2C_SR1_TXE I2C_SR1_TXE_Msk /*!< Data Register Empty (transmitters) */
+#define I2C_SR1_BERR_Pos (8U)
+#define I2C_SR1_BERR_Msk (0x1U << I2C_SR1_BERR_Pos) /*!< 0x00000100 */
+#define I2C_SR1_BERR I2C_SR1_BERR_Msk /*!< Bus Error */
+#define I2C_SR1_ARLO_Pos (9U)
+#define I2C_SR1_ARLO_Msk (0x1U << I2C_SR1_ARLO_Pos) /*!< 0x00000200 */
+#define I2C_SR1_ARLO I2C_SR1_ARLO_Msk /*!< Arbitration Lost (master mode) */
+#define I2C_SR1_AF_Pos (10U)
+#define I2C_SR1_AF_Msk (0x1U << I2C_SR1_AF_Pos) /*!< 0x00000400 */
+#define I2C_SR1_AF I2C_SR1_AF_Msk /*!< Acknowledge Failure */
+#define I2C_SR1_OVR_Pos (11U)
+#define I2C_SR1_OVR_Msk (0x1U << I2C_SR1_OVR_Pos) /*!< 0x00000800 */
+#define I2C_SR1_OVR I2C_SR1_OVR_Msk /*!< Overrun/Underrun */
+#define I2C_SR1_PECERR_Pos (12U)
+#define I2C_SR1_PECERR_Msk (0x1U << I2C_SR1_PECERR_Pos) /*!< 0x00001000 */
+#define I2C_SR1_PECERR I2C_SR1_PECERR_Msk /*!< PEC Error in reception */
+#define I2C_SR1_TIMEOUT_Pos (14U)
+#define I2C_SR1_TIMEOUT_Msk (0x1U << I2C_SR1_TIMEOUT_Pos) /*!< 0x00004000 */
+#define I2C_SR1_TIMEOUT I2C_SR1_TIMEOUT_Msk /*!< Timeout or Tlow Error */
+#define I2C_SR1_SMBALERT_Pos (15U)
+#define I2C_SR1_SMBALERT_Msk (0x1U << I2C_SR1_SMBALERT_Pos) /*!< 0x00008000 */
+#define I2C_SR1_SMBALERT I2C_SR1_SMBALERT_Msk /*!< SMBus Alert */
+
+/******************* Bit definition for I2C_SR2 register ********************/
+#define I2C_SR2_MSL_Pos (0U)
+#define I2C_SR2_MSL_Msk (0x1U << I2C_SR2_MSL_Pos) /*!< 0x00000001 */
+#define I2C_SR2_MSL I2C_SR2_MSL_Msk /*!< Master/Slave */
+#define I2C_SR2_BUSY_Pos (1U)
+#define I2C_SR2_BUSY_Msk (0x1U << I2C_SR2_BUSY_Pos) /*!< 0x00000002 */
+#define I2C_SR2_BUSY I2C_SR2_BUSY_Msk /*!< Bus Busy */
+#define I2C_SR2_TRA_Pos (2U)
+#define I2C_SR2_TRA_Msk (0x1U << I2C_SR2_TRA_Pos) /*!< 0x00000004 */
+#define I2C_SR2_TRA I2C_SR2_TRA_Msk /*!< Transmitter/Receiver */
+#define I2C_SR2_GENCALL_Pos (4U)
+#define I2C_SR2_GENCALL_Msk (0x1U << I2C_SR2_GENCALL_Pos) /*!< 0x00000010 */
+#define I2C_SR2_GENCALL I2C_SR2_GENCALL_Msk /*!< General Call Address (Slave mode) */
+#define I2C_SR2_SMBDEFAULT_Pos (5U)
+#define I2C_SR2_SMBDEFAULT_Msk (0x1U << I2C_SR2_SMBDEFAULT_Pos) /*!< 0x00000020 */
+#define I2C_SR2_SMBDEFAULT I2C_SR2_SMBDEFAULT_Msk /*!< SMBus Device Default Address (Slave mode) */
+#define I2C_SR2_SMBHOST_Pos (6U)
+#define I2C_SR2_SMBHOST_Msk (0x1U << I2C_SR2_SMBHOST_Pos) /*!< 0x00000040 */
+#define I2C_SR2_SMBHOST I2C_SR2_SMBHOST_Msk /*!< SMBus Host Header (Slave mode) */
+#define I2C_SR2_DUALF_Pos (7U)
+#define I2C_SR2_DUALF_Msk (0x1U << I2C_SR2_DUALF_Pos) /*!< 0x00000080 */
+#define I2C_SR2_DUALF I2C_SR2_DUALF_Msk /*!< Dual Flag (Slave mode) */
+#define I2C_SR2_PEC_Pos (8U)
+#define I2C_SR2_PEC_Msk (0xFFU << I2C_SR2_PEC_Pos) /*!< 0x0000FF00 */
+#define I2C_SR2_PEC I2C_SR2_PEC_Msk /*!< Packet Error Checking Register */
+
+/******************* Bit definition for I2C_CCR register ********************/
+#define I2C_CCR_CCR_Pos (0U)
+#define I2C_CCR_CCR_Msk (0xFFFU << I2C_CCR_CCR_Pos) /*!< 0x00000FFF */
+#define I2C_CCR_CCR I2C_CCR_CCR_Msk /*!< Clock Control Register in Fast/Standard mode (Master mode) */
+#define I2C_CCR_DUTY_Pos (14U)
+#define I2C_CCR_DUTY_Msk (0x1U << I2C_CCR_DUTY_Pos) /*!< 0x00004000 */
+#define I2C_CCR_DUTY I2C_CCR_DUTY_Msk /*!< Fast Mode Duty Cycle */
+#define I2C_CCR_FS_Pos (15U)
+#define I2C_CCR_FS_Msk (0x1U << I2C_CCR_FS_Pos) /*!< 0x00008000 */
+#define I2C_CCR_FS I2C_CCR_FS_Msk /*!< I2C Master Mode Selection */
+
+/****************** Bit definition for I2C_TRISE register *******************/
+#define I2C_TRISE_TRISE_Pos (0U)
+#define I2C_TRISE_TRISE_Msk (0x3FU << I2C_TRISE_TRISE_Pos) /*!< 0x0000003F */
+#define I2C_TRISE_TRISE I2C_TRISE_TRISE_Msk /*!< Maximum Rise Time in Fast/Standard mode (Master mode) */
+
+/******************************************************************************/
+/* */
+/* Universal Synchronous Asynchronous Receiver Transmitter */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for USART_SR register *******************/
+#define USART_SR_PE_Pos (0U)
+#define USART_SR_PE_Msk (0x1U << USART_SR_PE_Pos) /*!< 0x00000001 */
+#define USART_SR_PE USART_SR_PE_Msk /*!< Parity Error */
+#define USART_SR_FE_Pos (1U)
+#define USART_SR_FE_Msk (0x1U << USART_SR_FE_Pos) /*!< 0x00000002 */
+#define USART_SR_FE USART_SR_FE_Msk /*!< Framing Error */
+#define USART_SR_NE_Pos (2U)
+#define USART_SR_NE_Msk (0x1U << USART_SR_NE_Pos) /*!< 0x00000004 */
+#define USART_SR_NE USART_SR_NE_Msk /*!< Noise Error Flag */
+#define USART_SR_ORE_Pos (3U)
+#define USART_SR_ORE_Msk (0x1U << USART_SR_ORE_Pos) /*!< 0x00000008 */
+#define USART_SR_ORE USART_SR_ORE_Msk /*!< OverRun Error */
+#define USART_SR_IDLE_Pos (4U)
+#define USART_SR_IDLE_Msk (0x1U << USART_SR_IDLE_Pos) /*!< 0x00000010 */
+#define USART_SR_IDLE USART_SR_IDLE_Msk /*!< IDLE line detected */
+#define USART_SR_RXNE_Pos (5U)
+#define USART_SR_RXNE_Msk (0x1U << USART_SR_RXNE_Pos) /*!< 0x00000020 */
+#define USART_SR_RXNE USART_SR_RXNE_Msk /*!< Read Data Register Not Empty */
+#define USART_SR_TC_Pos (6U)
+#define USART_SR_TC_Msk (0x1U << USART_SR_TC_Pos) /*!< 0x00000040 */
+#define USART_SR_TC USART_SR_TC_Msk /*!< Transmission Complete */
+#define USART_SR_TXE_Pos (7U)
+#define USART_SR_TXE_Msk (0x1U << USART_SR_TXE_Pos) /*!< 0x00000080 */
+#define USART_SR_TXE USART_SR_TXE_Msk /*!< Transmit Data Register Empty */
+#define USART_SR_LBD_Pos (8U)
+#define USART_SR_LBD_Msk (0x1U << USART_SR_LBD_Pos) /*!< 0x00000100 */
+#define USART_SR_LBD USART_SR_LBD_Msk /*!< LIN Break Detection Flag */
+#define USART_SR_CTS_Pos (9U)
+#define USART_SR_CTS_Msk (0x1U << USART_SR_CTS_Pos) /*!< 0x00000200 */
+#define USART_SR_CTS USART_SR_CTS_Msk /*!< CTS Flag */
+
+/******************* Bit definition for USART_DR register *******************/
+#define USART_DR_DR_Pos (0U)
+#define USART_DR_DR_Msk (0x1FFU << USART_DR_DR_Pos) /*!< 0x000001FF */
+#define USART_DR_DR USART_DR_DR_Msk /*!< Data value */
+
+/****************** Bit definition for USART_BRR register *******************/
+#define USART_BRR_DIV_Fraction_Pos (0U)
+#define USART_BRR_DIV_Fraction_Msk (0xFU << USART_BRR_DIV_Fraction_Pos) /*!< 0x0000000F */
+#define USART_BRR_DIV_Fraction USART_BRR_DIV_Fraction_Msk /*!< Fraction of USARTDIV */
+#define USART_BRR_DIV_Mantissa_Pos (4U)
+#define USART_BRR_DIV_Mantissa_Msk (0xFFFU << USART_BRR_DIV_Mantissa_Pos) /*!< 0x0000FFF0 */
+#define USART_BRR_DIV_Mantissa USART_BRR_DIV_Mantissa_Msk /*!< Mantissa of USARTDIV */
+
+/****************** Bit definition for USART_CR1 register *******************/
+#define USART_CR1_SBK_Pos (0U)
+#define USART_CR1_SBK_Msk (0x1U << USART_CR1_SBK_Pos) /*!< 0x00000001 */
+#define USART_CR1_SBK USART_CR1_SBK_Msk /*!< Send Break */
+#define USART_CR1_RWU_Pos (1U)
+#define USART_CR1_RWU_Msk (0x1U << USART_CR1_RWU_Pos) /*!< 0x00000002 */
+#define USART_CR1_RWU USART_CR1_RWU_Msk /*!< Receiver wakeup */
+#define USART_CR1_RE_Pos (2U)
+#define USART_CR1_RE_Msk (0x1U << USART_CR1_RE_Pos) /*!< 0x00000004 */
+#define USART_CR1_RE USART_CR1_RE_Msk /*!< Receiver Enable */
+#define USART_CR1_TE_Pos (3U)
+#define USART_CR1_TE_Msk (0x1U << USART_CR1_TE_Pos) /*!< 0x00000008 */
+#define USART_CR1_TE USART_CR1_TE_Msk /*!< Transmitter Enable */
+#define USART_CR1_IDLEIE_Pos (4U)
+#define USART_CR1_IDLEIE_Msk (0x1U << USART_CR1_IDLEIE_Pos) /*!< 0x00000010 */
+#define USART_CR1_IDLEIE USART_CR1_IDLEIE_Msk /*!< IDLE Interrupt Enable */
+#define USART_CR1_RXNEIE_Pos (5U)
+#define USART_CR1_RXNEIE_Msk (0x1U << USART_CR1_RXNEIE_Pos) /*!< 0x00000020 */
+#define USART_CR1_RXNEIE USART_CR1_RXNEIE_Msk /*!< RXNE Interrupt Enable */
+#define USART_CR1_TCIE_Pos (6U)
+#define USART_CR1_TCIE_Msk (0x1U << USART_CR1_TCIE_Pos) /*!< 0x00000040 */
+#define USART_CR1_TCIE USART_CR1_TCIE_Msk /*!< Transmission Complete Interrupt Enable */
+#define USART_CR1_TXEIE_Pos (7U)
+#define USART_CR1_TXEIE_Msk (0x1U << USART_CR1_TXEIE_Pos) /*!< 0x00000080 */
+#define USART_CR1_TXEIE USART_CR1_TXEIE_Msk /*!< PE Interrupt Enable */
+#define USART_CR1_PEIE_Pos (8U)
+#define USART_CR1_PEIE_Msk (0x1U << USART_CR1_PEIE_Pos) /*!< 0x00000100 */
+#define USART_CR1_PEIE USART_CR1_PEIE_Msk /*!< PE Interrupt Enable */
+#define USART_CR1_PS_Pos (9U)
+#define USART_CR1_PS_Msk (0x1U << USART_CR1_PS_Pos) /*!< 0x00000200 */
+#define USART_CR1_PS USART_CR1_PS_Msk /*!< Parity Selection */
+#define USART_CR1_PCE_Pos (10U)
+#define USART_CR1_PCE_Msk (0x1U << USART_CR1_PCE_Pos) /*!< 0x00000400 */
+#define USART_CR1_PCE USART_CR1_PCE_Msk /*!< Parity Control Enable */
+#define USART_CR1_WAKE_Pos (11U)
+#define USART_CR1_WAKE_Msk (0x1U << USART_CR1_WAKE_Pos) /*!< 0x00000800 */
+#define USART_CR1_WAKE USART_CR1_WAKE_Msk /*!< Wakeup method */
+#define USART_CR1_M_Pos (12U)
+#define USART_CR1_M_Msk (0x1U << USART_CR1_M_Pos) /*!< 0x00001000 */
+#define USART_CR1_M USART_CR1_M_Msk /*!< Word length */
+#define USART_CR1_UE_Pos (13U)
+#define USART_CR1_UE_Msk (0x1U << USART_CR1_UE_Pos) /*!< 0x00002000 */
+#define USART_CR1_UE USART_CR1_UE_Msk /*!< USART Enable */
+
+/****************** Bit definition for USART_CR2 register *******************/
+#define USART_CR2_ADD_Pos (0U)
+#define USART_CR2_ADD_Msk (0xFU << USART_CR2_ADD_Pos) /*!< 0x0000000F */
+#define USART_CR2_ADD USART_CR2_ADD_Msk /*!< Address of the USART node */
+#define USART_CR2_LBDL_Pos (5U)
+#define USART_CR2_LBDL_Msk (0x1U << USART_CR2_LBDL_Pos) /*!< 0x00000020 */
+#define USART_CR2_LBDL USART_CR2_LBDL_Msk /*!< LIN Break Detection Length */
+#define USART_CR2_LBDIE_Pos (6U)
+#define USART_CR2_LBDIE_Msk (0x1U << USART_CR2_LBDIE_Pos) /*!< 0x00000040 */
+#define USART_CR2_LBDIE USART_CR2_LBDIE_Msk /*!< LIN Break Detection Interrupt Enable */
+#define USART_CR2_LBCL_Pos (8U)
+#define USART_CR2_LBCL_Msk (0x1U << USART_CR2_LBCL_Pos) /*!< 0x00000100 */
+#define USART_CR2_LBCL USART_CR2_LBCL_Msk /*!< Last Bit Clock pulse */
+#define USART_CR2_CPHA_Pos (9U)
+#define USART_CR2_CPHA_Msk (0x1U << USART_CR2_CPHA_Pos) /*!< 0x00000200 */
+#define USART_CR2_CPHA USART_CR2_CPHA_Msk /*!< Clock Phase */
+#define USART_CR2_CPOL_Pos (10U)
+#define USART_CR2_CPOL_Msk (0x1U << USART_CR2_CPOL_Pos) /*!< 0x00000400 */
+#define USART_CR2_CPOL USART_CR2_CPOL_Msk /*!< Clock Polarity */
+#define USART_CR2_CLKEN_Pos (11U)
+#define USART_CR2_CLKEN_Msk (0x1U << USART_CR2_CLKEN_Pos) /*!< 0x00000800 */
+#define USART_CR2_CLKEN USART_CR2_CLKEN_Msk /*!< Clock Enable */
+
+#define USART_CR2_STOP_Pos (12U)
+#define USART_CR2_STOP_Msk (0x3U << USART_CR2_STOP_Pos) /*!< 0x00003000 */
+#define USART_CR2_STOP USART_CR2_STOP_Msk /*!< STOP[1:0] bits (STOP bits) */
+#define USART_CR2_STOP_0 (0x1U << USART_CR2_STOP_Pos) /*!< 0x00001000 */
+#define USART_CR2_STOP_1 (0x2U << USART_CR2_STOP_Pos) /*!< 0x00002000 */
+
+#define USART_CR2_LINEN_Pos (14U)
+#define USART_CR2_LINEN_Msk (0x1U << USART_CR2_LINEN_Pos) /*!< 0x00004000 */
+#define USART_CR2_LINEN USART_CR2_LINEN_Msk /*!< LIN mode enable */
+
+/****************** Bit definition for USART_CR3 register *******************/
+#define USART_CR3_EIE_Pos (0U)
+#define USART_CR3_EIE_Msk (0x1U << USART_CR3_EIE_Pos) /*!< 0x00000001 */
+#define USART_CR3_EIE USART_CR3_EIE_Msk /*!< Error Interrupt Enable */
+#define USART_CR3_IREN_Pos (1U)
+#define USART_CR3_IREN_Msk (0x1U << USART_CR3_IREN_Pos) /*!< 0x00000002 */
+#define USART_CR3_IREN USART_CR3_IREN_Msk /*!< IrDA mode Enable */
+#define USART_CR3_IRLP_Pos (2U)
+#define USART_CR3_IRLP_Msk (0x1U << USART_CR3_IRLP_Pos) /*!< 0x00000004 */
+#define USART_CR3_IRLP USART_CR3_IRLP_Msk /*!< IrDA Low-Power */
+#define USART_CR3_HDSEL_Pos (3U)
+#define USART_CR3_HDSEL_Msk (0x1U << USART_CR3_HDSEL_Pos) /*!< 0x00000008 */
+#define USART_CR3_HDSEL USART_CR3_HDSEL_Msk /*!< Half-Duplex Selection */
+#define USART_CR3_NACK_Pos (4U)
+#define USART_CR3_NACK_Msk (0x1U << USART_CR3_NACK_Pos) /*!< 0x00000010 */
+#define USART_CR3_NACK USART_CR3_NACK_Msk /*!< Smartcard NACK enable */
+#define USART_CR3_SCEN_Pos (5U)
+#define USART_CR3_SCEN_Msk (0x1U << USART_CR3_SCEN_Pos) /*!< 0x00000020 */
+#define USART_CR3_SCEN USART_CR3_SCEN_Msk /*!< Smartcard mode enable */
+#define USART_CR3_DMAR_Pos (6U)
+#define USART_CR3_DMAR_Msk (0x1U << USART_CR3_DMAR_Pos) /*!< 0x00000040 */
+#define USART_CR3_DMAR USART_CR3_DMAR_Msk /*!< DMA Enable Receiver */
+#define USART_CR3_DMAT_Pos (7U)
+#define USART_CR3_DMAT_Msk (0x1U << USART_CR3_DMAT_Pos) /*!< 0x00000080 */
+#define USART_CR3_DMAT USART_CR3_DMAT_Msk /*!< DMA Enable Transmitter */
+#define USART_CR3_RTSE_Pos (8U)
+#define USART_CR3_RTSE_Msk (0x1U << USART_CR3_RTSE_Pos) /*!< 0x00000100 */
+#define USART_CR3_RTSE USART_CR3_RTSE_Msk /*!< RTS Enable */
+#define USART_CR3_CTSE_Pos (9U)
+#define USART_CR3_CTSE_Msk (0x1U << USART_CR3_CTSE_Pos) /*!< 0x00000200 */
+#define USART_CR3_CTSE USART_CR3_CTSE_Msk /*!< CTS Enable */
+#define USART_CR3_CTSIE_Pos (10U)
+#define USART_CR3_CTSIE_Msk (0x1U << USART_CR3_CTSIE_Pos) /*!< 0x00000400 */
+#define USART_CR3_CTSIE USART_CR3_CTSIE_Msk /*!< CTS Interrupt Enable */
+
+/****************** Bit definition for USART_GTPR register ******************/
+#define USART_GTPR_PSC_Pos (0U)
+#define USART_GTPR_PSC_Msk (0xFFU << USART_GTPR_PSC_Pos) /*!< 0x000000FF */
+#define USART_GTPR_PSC USART_GTPR_PSC_Msk /*!< PSC[7:0] bits (Prescaler value) */
+#define USART_GTPR_PSC_0 (0x01U << USART_GTPR_PSC_Pos) /*!< 0x00000001 */
+#define USART_GTPR_PSC_1 (0x02U << USART_GTPR_PSC_Pos) /*!< 0x00000002 */
+#define USART_GTPR_PSC_2 (0x04U << USART_GTPR_PSC_Pos) /*!< 0x00000004 */
+#define USART_GTPR_PSC_3 (0x08U << USART_GTPR_PSC_Pos) /*!< 0x00000008 */
+#define USART_GTPR_PSC_4 (0x10U << USART_GTPR_PSC_Pos) /*!< 0x00000010 */
+#define USART_GTPR_PSC_5 (0x20U << USART_GTPR_PSC_Pos) /*!< 0x00000020 */
+#define USART_GTPR_PSC_6 (0x40U << USART_GTPR_PSC_Pos) /*!< 0x00000040 */
+#define USART_GTPR_PSC_7 (0x80U << USART_GTPR_PSC_Pos) /*!< 0x00000080 */
+
+#define USART_GTPR_GT_Pos (8U)
+#define USART_GTPR_GT_Msk (0xFFU << USART_GTPR_GT_Pos) /*!< 0x0000FF00 */
+#define USART_GTPR_GT USART_GTPR_GT_Msk /*!< Guard time value */
+
+/******************************************************************************/
+/* */
+/* Debug MCU */
+/* */
+/******************************************************************************/
+
+/**************** Bit definition for DBGMCU_IDCODE register *****************/
+#define DBGMCU_IDCODE_DEV_ID_Pos (0U)
+#define DBGMCU_IDCODE_DEV_ID_Msk (0xFFFU << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */
+#define DBGMCU_IDCODE_DEV_ID DBGMCU_IDCODE_DEV_ID_Msk /*!< Device Identifier */
+
+#define DBGMCU_IDCODE_REV_ID_Pos (16U)
+#define DBGMCU_IDCODE_REV_ID_Msk (0xFFFFU << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */
+#define DBGMCU_IDCODE_REV_ID DBGMCU_IDCODE_REV_ID_Msk /*!< REV_ID[15:0] bits (Revision Identifier) */
+#define DBGMCU_IDCODE_REV_ID_0 (0x0001U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00010000 */
+#define DBGMCU_IDCODE_REV_ID_1 (0x0002U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00020000 */
+#define DBGMCU_IDCODE_REV_ID_2 (0x0004U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00040000 */
+#define DBGMCU_IDCODE_REV_ID_3 (0x0008U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00080000 */
+#define DBGMCU_IDCODE_REV_ID_4 (0x0010U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00100000 */
+#define DBGMCU_IDCODE_REV_ID_5 (0x0020U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00200000 */
+#define DBGMCU_IDCODE_REV_ID_6 (0x0040U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00400000 */
+#define DBGMCU_IDCODE_REV_ID_7 (0x0080U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00800000 */
+#define DBGMCU_IDCODE_REV_ID_8 (0x0100U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x01000000 */
+#define DBGMCU_IDCODE_REV_ID_9 (0x0200U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x02000000 */
+#define DBGMCU_IDCODE_REV_ID_10 (0x0400U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x04000000 */
+#define DBGMCU_IDCODE_REV_ID_11 (0x0800U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x08000000 */
+#define DBGMCU_IDCODE_REV_ID_12 (0x1000U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x10000000 */
+#define DBGMCU_IDCODE_REV_ID_13 (0x2000U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x20000000 */
+#define DBGMCU_IDCODE_REV_ID_14 (0x4000U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x40000000 */
+#define DBGMCU_IDCODE_REV_ID_15 (0x8000U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x80000000 */
+
+/****************** Bit definition for DBGMCU_CR register *******************/
+#define DBGMCU_CR_DBG_SLEEP_Pos (0U)
+#define DBGMCU_CR_DBG_SLEEP_Msk (0x1U << DBGMCU_CR_DBG_SLEEP_Pos) /*!< 0x00000001 */
+#define DBGMCU_CR_DBG_SLEEP DBGMCU_CR_DBG_SLEEP_Msk /*!< Debug Sleep Mode */
+#define DBGMCU_CR_DBG_STOP_Pos (1U)
+#define DBGMCU_CR_DBG_STOP_Msk (0x1U << DBGMCU_CR_DBG_STOP_Pos) /*!< 0x00000002 */
+#define DBGMCU_CR_DBG_STOP DBGMCU_CR_DBG_STOP_Msk /*!< Debug Stop Mode */
+#define DBGMCU_CR_DBG_STANDBY_Pos (2U)
+#define DBGMCU_CR_DBG_STANDBY_Msk (0x1U << DBGMCU_CR_DBG_STANDBY_Pos) /*!< 0x00000004 */
+#define DBGMCU_CR_DBG_STANDBY DBGMCU_CR_DBG_STANDBY_Msk /*!< Debug Standby mode */
+#define DBGMCU_CR_TRACE_IOEN_Pos (5U)
+#define DBGMCU_CR_TRACE_IOEN_Msk (0x1U << DBGMCU_CR_TRACE_IOEN_Pos) /*!< 0x00000020 */
+#define DBGMCU_CR_TRACE_IOEN DBGMCU_CR_TRACE_IOEN_Msk /*!< Trace Pin Assignment Control */
+
+#define DBGMCU_CR_TRACE_MODE_Pos (6U)
+#define DBGMCU_CR_TRACE_MODE_Msk (0x3U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x000000C0 */
+#define DBGMCU_CR_TRACE_MODE DBGMCU_CR_TRACE_MODE_Msk /*!< TRACE_MODE[1:0] bits (Trace Pin Assignment Control) */
+#define DBGMCU_CR_TRACE_MODE_0 (0x1U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000040 */
+#define DBGMCU_CR_TRACE_MODE_1 (0x2U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000080 */
+
+#define DBGMCU_CR_DBG_IWDG_STOP_Pos (8U)
+#define DBGMCU_CR_DBG_IWDG_STOP_Msk (0x1U << DBGMCU_CR_DBG_IWDG_STOP_Pos) /*!< 0x00000100 */
+#define DBGMCU_CR_DBG_IWDG_STOP DBGMCU_CR_DBG_IWDG_STOP_Msk /*!< Debug Independent Watchdog stopped when Core is halted */
+#define DBGMCU_CR_DBG_WWDG_STOP_Pos (9U)
+#define DBGMCU_CR_DBG_WWDG_STOP_Msk (0x1U << DBGMCU_CR_DBG_WWDG_STOP_Pos) /*!< 0x00000200 */
+#define DBGMCU_CR_DBG_WWDG_STOP DBGMCU_CR_DBG_WWDG_STOP_Msk /*!< Debug Window Watchdog stopped when Core is halted */
+#define DBGMCU_CR_DBG_TIM1_STOP_Pos (10U)
+#define DBGMCU_CR_DBG_TIM1_STOP_Msk (0x1U << DBGMCU_CR_DBG_TIM1_STOP_Pos) /*!< 0x00000400 */
+#define DBGMCU_CR_DBG_TIM1_STOP DBGMCU_CR_DBG_TIM1_STOP_Msk /*!< TIM1 counter stopped when core is halted */
+#define DBGMCU_CR_DBG_TIM2_STOP_Pos (11U)
+#define DBGMCU_CR_DBG_TIM2_STOP_Msk (0x1U << DBGMCU_CR_DBG_TIM2_STOP_Pos) /*!< 0x00000800 */
+#define DBGMCU_CR_DBG_TIM2_STOP DBGMCU_CR_DBG_TIM2_STOP_Msk /*!< TIM2 counter stopped when core is halted */
+#define DBGMCU_CR_DBG_TIM3_STOP_Pos (12U)
+#define DBGMCU_CR_DBG_TIM3_STOP_Msk (0x1U << DBGMCU_CR_DBG_TIM3_STOP_Pos) /*!< 0x00001000 */
+#define DBGMCU_CR_DBG_TIM3_STOP DBGMCU_CR_DBG_TIM3_STOP_Msk /*!< TIM3 counter stopped when core is halted */
+#define DBGMCU_CR_DBG_TIM4_STOP_Pos (13U)
+#define DBGMCU_CR_DBG_TIM4_STOP_Msk (0x1U << DBGMCU_CR_DBG_TIM4_STOP_Pos) /*!< 0x00002000 */
+#define DBGMCU_CR_DBG_TIM4_STOP DBGMCU_CR_DBG_TIM4_STOP_Msk /*!< TIM4 counter stopped when core is halted */
+#define DBGMCU_CR_DBG_CAN1_STOP_Pos (14U)
+#define DBGMCU_CR_DBG_CAN1_STOP_Msk (0x1U << DBGMCU_CR_DBG_CAN1_STOP_Pos) /*!< 0x00004000 */
+#define DBGMCU_CR_DBG_CAN1_STOP DBGMCU_CR_DBG_CAN1_STOP_Msk /*!< Debug CAN1 stopped when Core is halted */
+#define DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT_Pos (15U)
+#define DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT_Msk (0x1U << DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT_Pos) /*!< 0x00008000 */
+#define DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT_Msk /*!< SMBUS timeout mode stopped when Core is halted */
+#define DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT_Pos (16U)
+#define DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT_Msk (0x1U << DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT_Pos) /*!< 0x00010000 */
+#define DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT_Msk /*!< SMBUS timeout mode stopped when Core is halted */
+#define DBGMCU_CR_DBG_TIM5_STOP_Pos (18U)
+#define DBGMCU_CR_DBG_TIM5_STOP_Msk (0x1U << DBGMCU_CR_DBG_TIM5_STOP_Pos) /*!< 0x00040000 */
+#define DBGMCU_CR_DBG_TIM5_STOP DBGMCU_CR_DBG_TIM5_STOP_Msk /*!< TIM5 counter stopped when core is halted */
+#define DBGMCU_CR_DBG_TIM6_STOP_Pos (19U)
+#define DBGMCU_CR_DBG_TIM6_STOP_Msk (0x1U << DBGMCU_CR_DBG_TIM6_STOP_Pos) /*!< 0x00080000 */
+#define DBGMCU_CR_DBG_TIM6_STOP DBGMCU_CR_DBG_TIM6_STOP_Msk /*!< TIM6 counter stopped when core is halted */
+#define DBGMCU_CR_DBG_TIM7_STOP_Pos (20U)
+#define DBGMCU_CR_DBG_TIM7_STOP_Msk (0x1U << DBGMCU_CR_DBG_TIM7_STOP_Pos) /*!< 0x00100000 */
+#define DBGMCU_CR_DBG_TIM7_STOP DBGMCU_CR_DBG_TIM7_STOP_Msk /*!< TIM7 counter stopped when core is halted */
+#define DBGMCU_CR_DBG_CAN2_STOP_Pos (21U)
+#define DBGMCU_CR_DBG_CAN2_STOP_Msk (0x1U << DBGMCU_CR_DBG_CAN2_STOP_Pos) /*!< 0x00200000 */
+#define DBGMCU_CR_DBG_CAN2_STOP DBGMCU_CR_DBG_CAN2_STOP_Msk /*!< Debug CAN2 stopped when Core is halted */
+#define DBGMCU_CR_DBG_TIM9_STOP_Pos (28U)
+#define DBGMCU_CR_DBG_TIM9_STOP_Msk (0x1U << DBGMCU_CR_DBG_TIM9_STOP_Pos) /*!< 0x10000000 */
+#define DBGMCU_CR_DBG_TIM9_STOP DBGMCU_CR_DBG_TIM9_STOP_Msk /*!< Debug TIM9 stopped when Core is halted */
+#define DBGMCU_CR_DBG_TIM10_STOP_Pos (29U)
+#define DBGMCU_CR_DBG_TIM10_STOP_Msk (0x1U << DBGMCU_CR_DBG_TIM10_STOP_Pos) /*!< 0x20000000 */
+#define DBGMCU_CR_DBG_TIM10_STOP DBGMCU_CR_DBG_TIM10_STOP_Msk /*!< Debug TIM10 stopped when Core is halted */
+#define DBGMCU_CR_DBG_TIM11_STOP_Pos (30U)
+#define DBGMCU_CR_DBG_TIM11_STOP_Msk (0x1U << DBGMCU_CR_DBG_TIM11_STOP_Pos) /*!< 0x40000000 */
+#define DBGMCU_CR_DBG_TIM11_STOP DBGMCU_CR_DBG_TIM11_STOP_Msk /*!< Debug TIM11 stopped when Core is halted */
+
+/******************************************************************************/
+/* */
+/* FLASH and Option Bytes Registers */
+/* */
+/******************************************************************************/
+/******************* Bit definition for FLASH_ACR register ******************/
+#define FLASH_ACR_LATENCY_Pos (0U)
+#define FLASH_ACR_LATENCY_Msk (0x7U << FLASH_ACR_LATENCY_Pos) /*!< 0x00000007 */
+#define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk /*!< LATENCY[2:0] bits (Latency) */
+#define FLASH_ACR_LATENCY_0 (0x1U << FLASH_ACR_LATENCY_Pos) /*!< 0x00000001 */
+#define FLASH_ACR_LATENCY_1 (0x2U << FLASH_ACR_LATENCY_Pos) /*!< 0x00000002 */
+#define FLASH_ACR_LATENCY_2 (0x4U << FLASH_ACR_LATENCY_Pos) /*!< 0x00000004 */
+
+#define FLASH_ACR_HLFCYA_Pos (3U)
+#define FLASH_ACR_HLFCYA_Msk (0x1U << FLASH_ACR_HLFCYA_Pos) /*!< 0x00000008 */
+#define FLASH_ACR_HLFCYA FLASH_ACR_HLFCYA_Msk /*!< Flash Half Cycle Access Enable */
+#define FLASH_ACR_PRFTBE_Pos (4U)
+#define FLASH_ACR_PRFTBE_Msk (0x1U << FLASH_ACR_PRFTBE_Pos) /*!< 0x00000010 */
+#define FLASH_ACR_PRFTBE FLASH_ACR_PRFTBE_Msk /*!< Prefetch Buffer Enable */
+#define FLASH_ACR_PRFTBS_Pos (5U)
+#define FLASH_ACR_PRFTBS_Msk (0x1U << FLASH_ACR_PRFTBS_Pos) /*!< 0x00000020 */
+#define FLASH_ACR_PRFTBS FLASH_ACR_PRFTBS_Msk /*!< Prefetch Buffer Status */
+
+/****************** Bit definition for FLASH_KEYR register ******************/
+#define FLASH_KEYR_FKEYR_Pos (0U)
+#define FLASH_KEYR_FKEYR_Msk (0xFFFFFFFFU << FLASH_KEYR_FKEYR_Pos) /*!< 0xFFFFFFFF */
+#define FLASH_KEYR_FKEYR FLASH_KEYR_FKEYR_Msk /*!< FPEC Key */
+
+#define RDP_KEY_Pos (0U)
+#define RDP_KEY_Msk (0xA5U << RDP_KEY_Pos) /*!< 0x000000A5 */
+#define RDP_KEY RDP_KEY_Msk /*!< RDP Key */
+#define FLASH_KEY1_Pos (0U)
+#define FLASH_KEY1_Msk (0x45670123U << FLASH_KEY1_Pos) /*!< 0x45670123 */
+#define FLASH_KEY1 FLASH_KEY1_Msk /*!< FPEC Key1 */
+#define FLASH_KEY2_Pos (0U)
+#define FLASH_KEY2_Msk (0xCDEF89ABU << FLASH_KEY2_Pos) /*!< 0xCDEF89AB */
+#define FLASH_KEY2 FLASH_KEY2_Msk /*!< FPEC Key2 */
+
+/***************** Bit definition for FLASH_OPTKEYR register ****************/
+#define FLASH_OPTKEYR_OPTKEYR_Pos (0U)
+#define FLASH_OPTKEYR_OPTKEYR_Msk (0xFFFFFFFFU << FLASH_OPTKEYR_OPTKEYR_Pos) /*!< 0xFFFFFFFF */
+#define FLASH_OPTKEYR_OPTKEYR FLASH_OPTKEYR_OPTKEYR_Msk /*!< Option Byte Key */
+
+#define FLASH_OPTKEY1 FLASH_KEY1 /*!< Option Byte Key1 */
+#define FLASH_OPTKEY2 FLASH_KEY2 /*!< Option Byte Key2 */
+
+/****************** Bit definition for FLASH_SR register ********************/
+#define FLASH_SR_BSY_Pos (0U)
+#define FLASH_SR_BSY_Msk (0x1U << FLASH_SR_BSY_Pos) /*!< 0x00000001 */
+#define FLASH_SR_BSY FLASH_SR_BSY_Msk /*!< Busy */
+#define FLASH_SR_PGERR_Pos (2U)
+#define FLASH_SR_PGERR_Msk (0x1U << FLASH_SR_PGERR_Pos) /*!< 0x00000004 */
+#define FLASH_SR_PGERR FLASH_SR_PGERR_Msk /*!< Programming Error */
+#define FLASH_SR_WRPRTERR_Pos (4U)
+#define FLASH_SR_WRPRTERR_Msk (0x1U << FLASH_SR_WRPRTERR_Pos) /*!< 0x00000010 */
+#define FLASH_SR_WRPRTERR FLASH_SR_WRPRTERR_Msk /*!< Write Protection Error */
+#define FLASH_SR_EOP_Pos (5U)
+#define FLASH_SR_EOP_Msk (0x1U << FLASH_SR_EOP_Pos) /*!< 0x00000020 */
+#define FLASH_SR_EOP FLASH_SR_EOP_Msk /*!< End of operation */
+
+/******************* Bit definition for FLASH_CR register *******************/
+#define FLASH_CR_PG_Pos (0U)
+#define FLASH_CR_PG_Msk (0x1U << FLASH_CR_PG_Pos) /*!< 0x00000001 */
+#define FLASH_CR_PG FLASH_CR_PG_Msk /*!< Programming */
+#define FLASH_CR_PER_Pos (1U)
+#define FLASH_CR_PER_Msk (0x1U << FLASH_CR_PER_Pos) /*!< 0x00000002 */
+#define FLASH_CR_PER FLASH_CR_PER_Msk /*!< Page Erase */
+#define FLASH_CR_MER_Pos (2U)
+#define FLASH_CR_MER_Msk (0x1U << FLASH_CR_MER_Pos) /*!< 0x00000004 */
+#define FLASH_CR_MER FLASH_CR_MER_Msk /*!< Mass Erase */
+#define FLASH_CR_OPTPG_Pos (4U)
+#define FLASH_CR_OPTPG_Msk (0x1U << FLASH_CR_OPTPG_Pos) /*!< 0x00000010 */
+#define FLASH_CR_OPTPG FLASH_CR_OPTPG_Msk /*!< Option Byte Programming */
+#define FLASH_CR_OPTER_Pos (5U)
+#define FLASH_CR_OPTER_Msk (0x1U << FLASH_CR_OPTER_Pos) /*!< 0x00000020 */
+#define FLASH_CR_OPTER FLASH_CR_OPTER_Msk /*!< Option Byte Erase */
+#define FLASH_CR_STRT_Pos (6U)
+#define FLASH_CR_STRT_Msk (0x1U << FLASH_CR_STRT_Pos) /*!< 0x00000040 */
+#define FLASH_CR_STRT FLASH_CR_STRT_Msk /*!< Start */
+#define FLASH_CR_LOCK_Pos (7U)
+#define FLASH_CR_LOCK_Msk (0x1U << FLASH_CR_LOCK_Pos) /*!< 0x00000080 */
+#define FLASH_CR_LOCK FLASH_CR_LOCK_Msk /*!< Lock */
+#define FLASH_CR_OPTWRE_Pos (9U)
+#define FLASH_CR_OPTWRE_Msk (0x1U << FLASH_CR_OPTWRE_Pos) /*!< 0x00000200 */
+#define FLASH_CR_OPTWRE FLASH_CR_OPTWRE_Msk /*!< Option Bytes Write Enable */
+#define FLASH_CR_ERRIE_Pos (10U)
+#define FLASH_CR_ERRIE_Msk (0x1U << FLASH_CR_ERRIE_Pos) /*!< 0x00000400 */
+#define FLASH_CR_ERRIE FLASH_CR_ERRIE_Msk /*!< Error Interrupt Enable */
+#define FLASH_CR_EOPIE_Pos (12U)
+#define FLASH_CR_EOPIE_Msk (0x1U << FLASH_CR_EOPIE_Pos) /*!< 0x00001000 */
+#define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk /*!< End of operation interrupt enable */
+
+/******************* Bit definition for FLASH_AR register *******************/
+#define FLASH_AR_FAR_Pos (0U)
+#define FLASH_AR_FAR_Msk (0xFFFFFFFFU << FLASH_AR_FAR_Pos) /*!< 0xFFFFFFFF */
+#define FLASH_AR_FAR FLASH_AR_FAR_Msk /*!< Flash Address */
+
+/****************** Bit definition for FLASH_OBR register *******************/
+#define FLASH_OBR_OPTERR_Pos (0U)
+#define FLASH_OBR_OPTERR_Msk (0x1U << FLASH_OBR_OPTERR_Pos) /*!< 0x00000001 */
+#define FLASH_OBR_OPTERR FLASH_OBR_OPTERR_Msk /*!< Option Byte Error */
+#define FLASH_OBR_RDPRT_Pos (1U)
+#define FLASH_OBR_RDPRT_Msk (0x1U << FLASH_OBR_RDPRT_Pos) /*!< 0x00000002 */
+#define FLASH_OBR_RDPRT FLASH_OBR_RDPRT_Msk /*!< Read protection */
+
+#define FLASH_OBR_IWDG_SW_Pos (2U)
+#define FLASH_OBR_IWDG_SW_Msk (0x1U << FLASH_OBR_IWDG_SW_Pos) /*!< 0x00000004 */
+#define FLASH_OBR_IWDG_SW FLASH_OBR_IWDG_SW_Msk /*!< IWDG SW */
+#define FLASH_OBR_nRST_STOP_Pos (3U)
+#define FLASH_OBR_nRST_STOP_Msk (0x1U << FLASH_OBR_nRST_STOP_Pos) /*!< 0x00000008 */
+#define FLASH_OBR_nRST_STOP FLASH_OBR_nRST_STOP_Msk /*!< nRST_STOP */
+#define FLASH_OBR_nRST_STDBY_Pos (4U)
+#define FLASH_OBR_nRST_STDBY_Msk (0x1U << FLASH_OBR_nRST_STDBY_Pos) /*!< 0x00000010 */
+#define FLASH_OBR_nRST_STDBY FLASH_OBR_nRST_STDBY_Msk /*!< nRST_STDBY */
+#define FLASH_OBR_USER_Pos (2U)
+#define FLASH_OBR_USER_Msk (0x7U << FLASH_OBR_USER_Pos) /*!< 0x0000001C */
+#define FLASH_OBR_USER FLASH_OBR_USER_Msk /*!< User Option Bytes */
+#define FLASH_OBR_DATA0_Pos (10U)
+#define FLASH_OBR_DATA0_Msk (0xFFU << FLASH_OBR_DATA0_Pos) /*!< 0x0003FC00 */
+#define FLASH_OBR_DATA0 FLASH_OBR_DATA0_Msk /*!< Data0 */
+#define FLASH_OBR_DATA1_Pos (18U)
+#define FLASH_OBR_DATA1_Msk (0xFFU << FLASH_OBR_DATA1_Pos) /*!< 0x03FC0000 */
+#define FLASH_OBR_DATA1 FLASH_OBR_DATA1_Msk /*!< Data1 */
+
+/****************** Bit definition for FLASH_WRPR register ******************/
+#define FLASH_WRPR_WRP_Pos (0U)
+#define FLASH_WRPR_WRP_Msk (0xFFFFFFFFU << FLASH_WRPR_WRP_Pos) /*!< 0xFFFFFFFF */
+#define FLASH_WRPR_WRP FLASH_WRPR_WRP_Msk /*!< Write Protect */
+
+/*----------------------------------------------------------------------------*/
+
+/****************** Bit definition for FLASH_RDP register *******************/
+#define FLASH_RDP_RDP_Pos (0U)
+#define FLASH_RDP_RDP_Msk (0xFFU << FLASH_RDP_RDP_Pos) /*!< 0x000000FF */
+#define FLASH_RDP_RDP FLASH_RDP_RDP_Msk /*!< Read protection option byte */
+#define FLASH_RDP_nRDP_Pos (8U)
+#define FLASH_RDP_nRDP_Msk (0xFFU << FLASH_RDP_nRDP_Pos) /*!< 0x0000FF00 */
+#define FLASH_RDP_nRDP FLASH_RDP_nRDP_Msk /*!< Read protection complemented option byte */
+
+/****************** Bit definition for FLASH_USER register ******************/
+#define FLASH_USER_USER_Pos (16U)
+#define FLASH_USER_USER_Msk (0xFFU << FLASH_USER_USER_Pos) /*!< 0x00FF0000 */
+#define FLASH_USER_USER FLASH_USER_USER_Msk /*!< User option byte */
+#define FLASH_USER_nUSER_Pos (24U)
+#define FLASH_USER_nUSER_Msk (0xFFU << FLASH_USER_nUSER_Pos) /*!< 0xFF000000 */
+#define FLASH_USER_nUSER FLASH_USER_nUSER_Msk /*!< User complemented option byte */
+
+/****************** Bit definition for FLASH_Data0 register *****************/
+#define FLASH_DATA0_DATA0_Pos (0U)
+#define FLASH_DATA0_DATA0_Msk (0xFFU << FLASH_DATA0_DATA0_Pos) /*!< 0x000000FF */
+#define FLASH_DATA0_DATA0 FLASH_DATA0_DATA0_Msk /*!< User data storage option byte */
+#define FLASH_DATA0_nDATA0_Pos (8U)
+#define FLASH_DATA0_nDATA0_Msk (0xFFU << FLASH_DATA0_nDATA0_Pos) /*!< 0x0000FF00 */
+#define FLASH_DATA0_nDATA0 FLASH_DATA0_nDATA0_Msk /*!< User data storage complemented option byte */
+
+/****************** Bit definition for FLASH_Data1 register *****************/
+#define FLASH_DATA1_DATA1_Pos (16U)
+#define FLASH_DATA1_DATA1_Msk (0xFFU << FLASH_DATA1_DATA1_Pos) /*!< 0x00FF0000 */
+#define FLASH_DATA1_DATA1 FLASH_DATA1_DATA1_Msk /*!< User data storage option byte */
+#define FLASH_DATA1_nDATA1_Pos (24U)
+#define FLASH_DATA1_nDATA1_Msk (0xFFU << FLASH_DATA1_nDATA1_Pos) /*!< 0xFF000000 */
+#define FLASH_DATA1_nDATA1 FLASH_DATA1_nDATA1_Msk /*!< User data storage complemented option byte */
+
+/****************** Bit definition for FLASH_WRP0 register ******************/
+#define FLASH_WRP0_WRP0_Pos (0U)
+#define FLASH_WRP0_WRP0_Msk (0xFFU << FLASH_WRP0_WRP0_Pos) /*!< 0x000000FF */
+#define FLASH_WRP0_WRP0 FLASH_WRP0_WRP0_Msk /*!< Flash memory write protection option bytes */
+#define FLASH_WRP0_nWRP0_Pos (8U)
+#define FLASH_WRP0_nWRP0_Msk (0xFFU << FLASH_WRP0_nWRP0_Pos) /*!< 0x0000FF00 */
+#define FLASH_WRP0_nWRP0 FLASH_WRP0_nWRP0_Msk /*!< Flash memory write protection complemented option bytes */
+
+/****************** Bit definition for FLASH_WRP1 register ******************/
+#define FLASH_WRP1_WRP1_Pos (16U)
+#define FLASH_WRP1_WRP1_Msk (0xFFU << FLASH_WRP1_WRP1_Pos) /*!< 0x00FF0000 */
+#define FLASH_WRP1_WRP1 FLASH_WRP1_WRP1_Msk /*!< Flash memory write protection option bytes */
+#define FLASH_WRP1_nWRP1_Pos (24U)
+#define FLASH_WRP1_nWRP1_Msk (0xFFU << FLASH_WRP1_nWRP1_Pos) /*!< 0xFF000000 */
+#define FLASH_WRP1_nWRP1 FLASH_WRP1_nWRP1_Msk /*!< Flash memory write protection complemented option bytes */
+
+/****************** Bit definition for FLASH_WRP2 register ******************/
+#define FLASH_WRP2_WRP2_Pos (0U)
+#define FLASH_WRP2_WRP2_Msk (0xFFU << FLASH_WRP2_WRP2_Pos) /*!< 0x000000FF */
+#define FLASH_WRP2_WRP2 FLASH_WRP2_WRP2_Msk /*!< Flash memory write protection option bytes */
+#define FLASH_WRP2_nWRP2_Pos (8U)
+#define FLASH_WRP2_nWRP2_Msk (0xFFU << FLASH_WRP2_nWRP2_Pos) /*!< 0x0000FF00 */
+#define FLASH_WRP2_nWRP2 FLASH_WRP2_nWRP2_Msk /*!< Flash memory write protection complemented option bytes */
+
+/****************** Bit definition for FLASH_WRP3 register ******************/
+#define FLASH_WRP3_WRP3_Pos (16U)
+#define FLASH_WRP3_WRP3_Msk (0xFFU << FLASH_WRP3_WRP3_Pos) /*!< 0x00FF0000 */
+#define FLASH_WRP3_WRP3 FLASH_WRP3_WRP3_Msk /*!< Flash memory write protection option bytes */
+#define FLASH_WRP3_nWRP3_Pos (24U)
+#define FLASH_WRP3_nWRP3_Msk (0xFFU << FLASH_WRP3_nWRP3_Pos) /*!< 0xFF000000 */
+#define FLASH_WRP3_nWRP3 FLASH_WRP3_nWRP3_Msk /*!< Flash memory write protection complemented option bytes */
+
+/******************************************************************************/
+/* Ethernet MAC Registers bits definitions */
+/******************************************************************************/
+/* Bit definition for Ethernet MAC Control Register register */
+#define ETH_MACCR_WD_Pos (23U)
+#define ETH_MACCR_WD_Msk (0x1U << ETH_MACCR_WD_Pos) /*!< 0x00800000 */
+#define ETH_MACCR_WD ETH_MACCR_WD_Msk /* Watchdog disable */
+#define ETH_MACCR_JD_Pos (22U)
+#define ETH_MACCR_JD_Msk (0x1U << ETH_MACCR_JD_Pos) /*!< 0x00400000 */
+#define ETH_MACCR_JD ETH_MACCR_JD_Msk /* Jabber disable */
+#define ETH_MACCR_IFG_Pos (17U)
+#define ETH_MACCR_IFG_Msk (0x7U << ETH_MACCR_IFG_Pos) /*!< 0x000E0000 */
+#define ETH_MACCR_IFG ETH_MACCR_IFG_Msk /* Inter-frame gap */
+#define ETH_MACCR_IFG_96Bit ((uint32_t)0x00000000) /* Minimum IFG between frames during transmission is 96Bit */
+#define ETH_MACCR_IFG_88Bit ((uint32_t)0x00020000) /* Minimum IFG between frames during transmission is 88Bit */
+#define ETH_MACCR_IFG_80Bit ((uint32_t)0x00040000) /* Minimum IFG between frames during transmission is 80Bit */
+#define ETH_MACCR_IFG_72Bit ((uint32_t)0x00060000) /* Minimum IFG between frames during transmission is 72Bit */
+#define ETH_MACCR_IFG_64Bit ((uint32_t)0x00080000) /* Minimum IFG between frames during transmission is 64Bit */
+#define ETH_MACCR_IFG_56Bit ((uint32_t)0x000A0000) /* Minimum IFG between frames during transmission is 56Bit */
+#define ETH_MACCR_IFG_48Bit ((uint32_t)0x000C0000) /* Minimum IFG between frames during transmission is 48Bit */
+#define ETH_MACCR_IFG_40Bit ((uint32_t)0x000E0000) /* Minimum IFG between frames during transmission is 40Bit */
+#define ETH_MACCR_CSD_Pos (16U)
+#define ETH_MACCR_CSD_Msk (0x1U << ETH_MACCR_CSD_Pos) /*!< 0x00010000 */
+#define ETH_MACCR_CSD ETH_MACCR_CSD_Msk /* Carrier sense disable (during transmission) */
+#define ETH_MACCR_FES_Pos (14U)
+#define ETH_MACCR_FES_Msk (0x1U << ETH_MACCR_FES_Pos) /*!< 0x00004000 */
+#define ETH_MACCR_FES ETH_MACCR_FES_Msk /* Fast ethernet speed */
+#define ETH_MACCR_ROD_Pos (13U)
+#define ETH_MACCR_ROD_Msk (0x1U << ETH_MACCR_ROD_Pos) /*!< 0x00002000 */
+#define ETH_MACCR_ROD ETH_MACCR_ROD_Msk /* Receive own disable */
+#define ETH_MACCR_LM_Pos (12U)
+#define ETH_MACCR_LM_Msk (0x1U << ETH_MACCR_LM_Pos) /*!< 0x00001000 */
+#define ETH_MACCR_LM ETH_MACCR_LM_Msk /* loopback mode */
+#define ETH_MACCR_DM_Pos (11U)
+#define ETH_MACCR_DM_Msk (0x1U << ETH_MACCR_DM_Pos) /*!< 0x00000800 */
+#define ETH_MACCR_DM ETH_MACCR_DM_Msk /* Duplex mode */
+#define ETH_MACCR_IPCO_Pos (10U)
+#define ETH_MACCR_IPCO_Msk (0x1U << ETH_MACCR_IPCO_Pos) /*!< 0x00000400 */
+#define ETH_MACCR_IPCO ETH_MACCR_IPCO_Msk /* IP Checksum offload */
+#define ETH_MACCR_RD_Pos (9U)
+#define ETH_MACCR_RD_Msk (0x1U << ETH_MACCR_RD_Pos) /*!< 0x00000200 */
+#define ETH_MACCR_RD ETH_MACCR_RD_Msk /* Retry disable */
+#define ETH_MACCR_APCS_Pos (7U)
+#define ETH_MACCR_APCS_Msk (0x1U << ETH_MACCR_APCS_Pos) /*!< 0x00000080 */
+#define ETH_MACCR_APCS ETH_MACCR_APCS_Msk /* Automatic Pad/CRC stripping */
+#define ETH_MACCR_BL_Pos (5U)
+#define ETH_MACCR_BL_Msk (0x3U << ETH_MACCR_BL_Pos) /*!< 0x00000060 */
+#define ETH_MACCR_BL ETH_MACCR_BL_Msk /* Back-off limit: random integer number (r) of slot time delays before rescheduling
+ a transmission attempt during retries after a collision: 0 =< r <2^k */
+#define ETH_MACCR_BL_10 ((uint32_t)0x00000000) /* k = min (n, 10) */
+#define ETH_MACCR_BL_8 ((uint32_t)0x00000020) /* k = min (n, 8) */
+#define ETH_MACCR_BL_4 ((uint32_t)0x00000040) /* k = min (n, 4) */
+#define ETH_MACCR_BL_1 ((uint32_t)0x00000060) /* k = min (n, 1) */
+#define ETH_MACCR_DC_Pos (4U)
+#define ETH_MACCR_DC_Msk (0x1U << ETH_MACCR_DC_Pos) /*!< 0x00000010 */
+#define ETH_MACCR_DC ETH_MACCR_DC_Msk /* Defferal check */
+#define ETH_MACCR_TE_Pos (3U)
+#define ETH_MACCR_TE_Msk (0x1U << ETH_MACCR_TE_Pos) /*!< 0x00000008 */
+#define ETH_MACCR_TE ETH_MACCR_TE_Msk /* Transmitter enable */
+#define ETH_MACCR_RE_Pos (2U)
+#define ETH_MACCR_RE_Msk (0x1U << ETH_MACCR_RE_Pos) /*!< 0x00000004 */
+#define ETH_MACCR_RE ETH_MACCR_RE_Msk /* Receiver enable */
+
+/* Bit definition for Ethernet MAC Frame Filter Register */
+#define ETH_MACFFR_RA_Pos (31U)
+#define ETH_MACFFR_RA_Msk (0x1U << ETH_MACFFR_RA_Pos) /*!< 0x80000000 */
+#define ETH_MACFFR_RA ETH_MACFFR_RA_Msk /* Receive all */
+#define ETH_MACFFR_HPF_Pos (10U)
+#define ETH_MACFFR_HPF_Msk (0x1U << ETH_MACFFR_HPF_Pos) /*!< 0x00000400 */
+#define ETH_MACFFR_HPF ETH_MACFFR_HPF_Msk /* Hash or perfect filter */
+#define ETH_MACFFR_SAF_Pos (9U)
+#define ETH_MACFFR_SAF_Msk (0x1U << ETH_MACFFR_SAF_Pos) /*!< 0x00000200 */
+#define ETH_MACFFR_SAF ETH_MACFFR_SAF_Msk /* Source address filter enable */
+#define ETH_MACFFR_SAIF_Pos (8U)
+#define ETH_MACFFR_SAIF_Msk (0x1U << ETH_MACFFR_SAIF_Pos) /*!< 0x00000100 */
+#define ETH_MACFFR_SAIF ETH_MACFFR_SAIF_Msk /* SA inverse filtering */
+#define ETH_MACFFR_PCF_Pos (6U)
+#define ETH_MACFFR_PCF_Msk (0x3U << ETH_MACFFR_PCF_Pos) /*!< 0x000000C0 */
+#define ETH_MACFFR_PCF ETH_MACFFR_PCF_Msk /* Pass control frames: 3 cases */
+#define ETH_MACFFR_PCF_BlockAll_Pos (6U)
+#define ETH_MACFFR_PCF_BlockAll_Msk (0x1U << ETH_MACFFR_PCF_BlockAll_Pos) /*!< 0x00000040 */
+#define ETH_MACFFR_PCF_BlockAll ETH_MACFFR_PCF_BlockAll_Msk /* MAC filters all control frames from reaching the application */
+#define ETH_MACFFR_PCF_ForwardAll_Pos (7U)
+#define ETH_MACFFR_PCF_ForwardAll_Msk (0x1U << ETH_MACFFR_PCF_ForwardAll_Pos) /*!< 0x00000080 */
+#define ETH_MACFFR_PCF_ForwardAll ETH_MACFFR_PCF_ForwardAll_Msk /* MAC forwards all control frames to application even if they fail the Address Filter */
+#define ETH_MACFFR_PCF_ForwardPassedAddrFilter_Pos (6U)
+#define ETH_MACFFR_PCF_ForwardPassedAddrFilter_Msk (0x3U << ETH_MACFFR_PCF_ForwardPassedAddrFilter_Pos) /*!< 0x000000C0 */
+#define ETH_MACFFR_PCF_ForwardPassedAddrFilter ETH_MACFFR_PCF_ForwardPassedAddrFilter_Msk /* MAC forwards control frames that pass the Address Filter. */
+#define ETH_MACFFR_BFD_Pos (5U)
+#define ETH_MACFFR_BFD_Msk (0x1U << ETH_MACFFR_BFD_Pos) /*!< 0x00000020 */
+#define ETH_MACFFR_BFD ETH_MACFFR_BFD_Msk /* Broadcast frame disable */
+#define ETH_MACFFR_PAM_Pos (4U)
+#define ETH_MACFFR_PAM_Msk (0x1U << ETH_MACFFR_PAM_Pos) /*!< 0x00000010 */
+#define ETH_MACFFR_PAM ETH_MACFFR_PAM_Msk /* Pass all mutlicast */
+#define ETH_MACFFR_DAIF_Pos (3U)
+#define ETH_MACFFR_DAIF_Msk (0x1U << ETH_MACFFR_DAIF_Pos) /*!< 0x00000008 */
+#define ETH_MACFFR_DAIF ETH_MACFFR_DAIF_Msk /* DA Inverse filtering */
+#define ETH_MACFFR_HM_Pos (2U)
+#define ETH_MACFFR_HM_Msk (0x1U << ETH_MACFFR_HM_Pos) /*!< 0x00000004 */
+#define ETH_MACFFR_HM ETH_MACFFR_HM_Msk /* Hash multicast */
+#define ETH_MACFFR_HU_Pos (1U)
+#define ETH_MACFFR_HU_Msk (0x1U << ETH_MACFFR_HU_Pos) /*!< 0x00000002 */
+#define ETH_MACFFR_HU ETH_MACFFR_HU_Msk /* Hash unicast */
+#define ETH_MACFFR_PM_Pos (0U)
+#define ETH_MACFFR_PM_Msk (0x1U << ETH_MACFFR_PM_Pos) /*!< 0x00000001 */
+#define ETH_MACFFR_PM ETH_MACFFR_PM_Msk /* Promiscuous mode */
+
+/* Bit definition for Ethernet MAC Hash Table High Register */
+#define ETH_MACHTHR_HTH_Pos (0U)
+#define ETH_MACHTHR_HTH_Msk (0xFFFFFFFFU << ETH_MACHTHR_HTH_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACHTHR_HTH ETH_MACHTHR_HTH_Msk /* Hash table high */
+
+/* Bit definition for Ethernet MAC Hash Table Low Register */
+#define ETH_MACHTLR_HTL_Pos (0U)
+#define ETH_MACHTLR_HTL_Msk (0xFFFFFFFFU << ETH_MACHTLR_HTL_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACHTLR_HTL ETH_MACHTLR_HTL_Msk /* Hash table low */
+
+/* Bit definition for Ethernet MAC MII Address Register */
+#define ETH_MACMIIAR_PA_Pos (11U)
+#define ETH_MACMIIAR_PA_Msk (0x1FU << ETH_MACMIIAR_PA_Pos) /*!< 0x0000F800 */
+#define ETH_MACMIIAR_PA ETH_MACMIIAR_PA_Msk /* Physical layer address */
+#define ETH_MACMIIAR_MR_Pos (6U)
+#define ETH_MACMIIAR_MR_Msk (0x1FU << ETH_MACMIIAR_MR_Pos) /*!< 0x000007C0 */
+#define ETH_MACMIIAR_MR ETH_MACMIIAR_MR_Msk /* MII register in the selected PHY */
+#define ETH_MACMIIAR_CR_Pos (2U)
+#define ETH_MACMIIAR_CR_Msk (0x7U << ETH_MACMIIAR_CR_Pos) /*!< 0x0000001C */
+#define ETH_MACMIIAR_CR ETH_MACMIIAR_CR_Msk /* CR clock range: 6 cases */
+#define ETH_MACMIIAR_CR_DIV42 ((uint32_t)0x00000000) /* HCLK:60-72 MHz; MDC clock= HCLK/42 */
+#define ETH_MACMIIAR_CR_DIV16_Pos (3U)
+#define ETH_MACMIIAR_CR_DIV16_Msk (0x1U << ETH_MACMIIAR_CR_DIV16_Pos) /*!< 0x00000008 */
+#define ETH_MACMIIAR_CR_DIV16 ETH_MACMIIAR_CR_DIV16_Msk /* HCLK:20-35 MHz; MDC clock= HCLK/16 */
+#define ETH_MACMIIAR_CR_DIV26_Pos (2U)
+#define ETH_MACMIIAR_CR_DIV26_Msk (0x3U << ETH_MACMIIAR_CR_DIV26_Pos) /*!< 0x0000000C */
+#define ETH_MACMIIAR_CR_DIV26 ETH_MACMIIAR_CR_DIV26_Msk /* HCLK:35-60 MHz; MDC clock= HCLK/26 */
+#define ETH_MACMIIAR_MW_Pos (1U)
+#define ETH_MACMIIAR_MW_Msk (0x1U << ETH_MACMIIAR_MW_Pos) /*!< 0x00000002 */
+#define ETH_MACMIIAR_MW ETH_MACMIIAR_MW_Msk /* MII write */
+#define ETH_MACMIIAR_MB_Pos (0U)
+#define ETH_MACMIIAR_MB_Msk (0x1U << ETH_MACMIIAR_MB_Pos) /*!< 0x00000001 */
+#define ETH_MACMIIAR_MB ETH_MACMIIAR_MB_Msk /* MII busy */
+
+/* Bit definition for Ethernet MAC MII Data Register */
+#define ETH_MACMIIDR_MD_Pos (0U)
+#define ETH_MACMIIDR_MD_Msk (0xFFFFU << ETH_MACMIIDR_MD_Pos) /*!< 0x0000FFFF */
+#define ETH_MACMIIDR_MD ETH_MACMIIDR_MD_Msk /* MII data: read/write data from/to PHY */
+
+/* Bit definition for Ethernet MAC Flow Control Register */
+#define ETH_MACFCR_PT_Pos (16U)
+#define ETH_MACFCR_PT_Msk (0xFFFFU << ETH_MACFCR_PT_Pos) /*!< 0xFFFF0000 */
+#define ETH_MACFCR_PT ETH_MACFCR_PT_Msk /* Pause time */
+#define ETH_MACFCR_ZQPD_Pos (7U)
+#define ETH_MACFCR_ZQPD_Msk (0x1U << ETH_MACFCR_ZQPD_Pos) /*!< 0x00000080 */
+#define ETH_MACFCR_ZQPD ETH_MACFCR_ZQPD_Msk /* Zero-quanta pause disable */
+#define ETH_MACFCR_PLT_Pos (4U)
+#define ETH_MACFCR_PLT_Msk (0x3U << ETH_MACFCR_PLT_Pos) /*!< 0x00000030 */
+#define ETH_MACFCR_PLT ETH_MACFCR_PLT_Msk /* Pause low threshold: 4 cases */
+#define ETH_MACFCR_PLT_Minus4 ((uint32_t)0x00000000) /* Pause time minus 4 slot times */
+#define ETH_MACFCR_PLT_Minus28_Pos (4U)
+#define ETH_MACFCR_PLT_Minus28_Msk (0x1U << ETH_MACFCR_PLT_Minus28_Pos) /*!< 0x00000010 */
+#define ETH_MACFCR_PLT_Minus28 ETH_MACFCR_PLT_Minus28_Msk /* Pause time minus 28 slot times */
+#define ETH_MACFCR_PLT_Minus144_Pos (5U)
+#define ETH_MACFCR_PLT_Minus144_Msk (0x1U << ETH_MACFCR_PLT_Minus144_Pos) /*!< 0x00000020 */
+#define ETH_MACFCR_PLT_Minus144 ETH_MACFCR_PLT_Minus144_Msk /* Pause time minus 144 slot times */
+#define ETH_MACFCR_PLT_Minus256_Pos (4U)
+#define ETH_MACFCR_PLT_Minus256_Msk (0x3U << ETH_MACFCR_PLT_Minus256_Pos) /*!< 0x00000030 */
+#define ETH_MACFCR_PLT_Minus256 ETH_MACFCR_PLT_Minus256_Msk /* Pause time minus 256 slot times */
+#define ETH_MACFCR_UPFD_Pos (3U)
+#define ETH_MACFCR_UPFD_Msk (0x1U << ETH_MACFCR_UPFD_Pos) /*!< 0x00000008 */
+#define ETH_MACFCR_UPFD ETH_MACFCR_UPFD_Msk /* Unicast pause frame detect */
+#define ETH_MACFCR_RFCE_Pos (2U)
+#define ETH_MACFCR_RFCE_Msk (0x1U << ETH_MACFCR_RFCE_Pos) /*!< 0x00000004 */
+#define ETH_MACFCR_RFCE ETH_MACFCR_RFCE_Msk /* Receive flow control enable */
+#define ETH_MACFCR_TFCE_Pos (1U)
+#define ETH_MACFCR_TFCE_Msk (0x1U << ETH_MACFCR_TFCE_Pos) /*!< 0x00000002 */
+#define ETH_MACFCR_TFCE ETH_MACFCR_TFCE_Msk /* Transmit flow control enable */
+#define ETH_MACFCR_FCBBPA_Pos (0U)
+#define ETH_MACFCR_FCBBPA_Msk (0x1U << ETH_MACFCR_FCBBPA_Pos) /*!< 0x00000001 */
+#define ETH_MACFCR_FCBBPA ETH_MACFCR_FCBBPA_Msk /* Flow control busy/backpressure activate */
+
+/* Bit definition for Ethernet MAC VLAN Tag Register */
+#define ETH_MACVLANTR_VLANTC_Pos (16U)
+#define ETH_MACVLANTR_VLANTC_Msk (0x1U << ETH_MACVLANTR_VLANTC_Pos) /*!< 0x00010000 */
+#define ETH_MACVLANTR_VLANTC ETH_MACVLANTR_VLANTC_Msk /* 12-bit VLAN tag comparison */
+#define ETH_MACVLANTR_VLANTI_Pos (0U)
+#define ETH_MACVLANTR_VLANTI_Msk (0xFFFFU << ETH_MACVLANTR_VLANTI_Pos) /*!< 0x0000FFFF */
+#define ETH_MACVLANTR_VLANTI ETH_MACVLANTR_VLANTI_Msk /* VLAN tag identifier (for receive frames) */
+
+/* Bit definition for Ethernet MAC Remote Wake-UpFrame Filter Register */
+#define ETH_MACRWUFFR_D_Pos (0U)
+#define ETH_MACRWUFFR_D_Msk (0xFFFFFFFFU << ETH_MACRWUFFR_D_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACRWUFFR_D ETH_MACRWUFFR_D_Msk /* Wake-up frame filter register data */
+/* Eight sequential Writes to this address (offset 0x28) will write all Wake-UpFrame Filter Registers.
+ Eight sequential Reads from this address (offset 0x28) will read all Wake-UpFrame Filter Registers. */
+/* Wake-UpFrame Filter Reg0 : Filter 0 Byte Mask
+ Wake-UpFrame Filter Reg1 : Filter 1 Byte Mask
+ Wake-UpFrame Filter Reg2 : Filter 2 Byte Mask
+ Wake-UpFrame Filter Reg3 : Filter 3 Byte Mask
+ Wake-UpFrame Filter Reg4 : RSVD - Filter3 Command - RSVD - Filter2 Command -
+ RSVD - Filter1 Command - RSVD - Filter0 Command
+ Wake-UpFrame Filter Re5 : Filter3 Offset - Filter2 Offset - Filter1 Offset - Filter0 Offset
+ Wake-UpFrame Filter Re6 : Filter1 CRC16 - Filter0 CRC16
+ Wake-UpFrame Filter Re7 : Filter3 CRC16 - Filter2 CRC16 */
+
+/* Bit definition for Ethernet MAC PMT Control and Status Register */
+#define ETH_MACPMTCSR_WFFRPR_Pos (31U)
+#define ETH_MACPMTCSR_WFFRPR_Msk (0x1U << ETH_MACPMTCSR_WFFRPR_Pos) /*!< 0x80000000 */
+#define ETH_MACPMTCSR_WFFRPR ETH_MACPMTCSR_WFFRPR_Msk /* Wake-Up Frame Filter Register Pointer Reset */
+#define ETH_MACPMTCSR_GU_Pos (9U)
+#define ETH_MACPMTCSR_GU_Msk (0x1U << ETH_MACPMTCSR_GU_Pos) /*!< 0x00000200 */
+#define ETH_MACPMTCSR_GU ETH_MACPMTCSR_GU_Msk /* Global Unicast */
+#define ETH_MACPMTCSR_WFR_Pos (6U)
+#define ETH_MACPMTCSR_WFR_Msk (0x1U << ETH_MACPMTCSR_WFR_Pos) /*!< 0x00000040 */
+#define ETH_MACPMTCSR_WFR ETH_MACPMTCSR_WFR_Msk /* Wake-Up Frame Received */
+#define ETH_MACPMTCSR_MPR_Pos (5U)
+#define ETH_MACPMTCSR_MPR_Msk (0x1U << ETH_MACPMTCSR_MPR_Pos) /*!< 0x00000020 */
+#define ETH_MACPMTCSR_MPR ETH_MACPMTCSR_MPR_Msk /* Magic Packet Received */
+#define ETH_MACPMTCSR_WFE_Pos (2U)
+#define ETH_MACPMTCSR_WFE_Msk (0x1U << ETH_MACPMTCSR_WFE_Pos) /*!< 0x00000004 */
+#define ETH_MACPMTCSR_WFE ETH_MACPMTCSR_WFE_Msk /* Wake-Up Frame Enable */
+#define ETH_MACPMTCSR_MPE_Pos (1U)
+#define ETH_MACPMTCSR_MPE_Msk (0x1U << ETH_MACPMTCSR_MPE_Pos) /*!< 0x00000002 */
+#define ETH_MACPMTCSR_MPE ETH_MACPMTCSR_MPE_Msk /* Magic Packet Enable */
+#define ETH_MACPMTCSR_PD_Pos (0U)
+#define ETH_MACPMTCSR_PD_Msk (0x1U << ETH_MACPMTCSR_PD_Pos) /*!< 0x00000001 */
+#define ETH_MACPMTCSR_PD ETH_MACPMTCSR_PD_Msk /* Power Down */
+
+/* Bit definition for Ethernet MAC Status Register */
+#define ETH_MACSR_TSTS_Pos (9U)
+#define ETH_MACSR_TSTS_Msk (0x1U << ETH_MACSR_TSTS_Pos) /*!< 0x00000200 */
+#define ETH_MACSR_TSTS ETH_MACSR_TSTS_Msk /* Time stamp trigger status */
+#define ETH_MACSR_MMCTS_Pos (6U)
+#define ETH_MACSR_MMCTS_Msk (0x1U << ETH_MACSR_MMCTS_Pos) /*!< 0x00000040 */
+#define ETH_MACSR_MMCTS ETH_MACSR_MMCTS_Msk /* MMC transmit status */
+#define ETH_MACSR_MMMCRS_Pos (5U)
+#define ETH_MACSR_MMMCRS_Msk (0x1U << ETH_MACSR_MMMCRS_Pos) /*!< 0x00000020 */
+#define ETH_MACSR_MMMCRS ETH_MACSR_MMMCRS_Msk /* MMC receive status */
+#define ETH_MACSR_MMCS_Pos (4U)
+#define ETH_MACSR_MMCS_Msk (0x1U << ETH_MACSR_MMCS_Pos) /*!< 0x00000010 */
+#define ETH_MACSR_MMCS ETH_MACSR_MMCS_Msk /* MMC status */
+#define ETH_MACSR_PMTS_Pos (3U)
+#define ETH_MACSR_PMTS_Msk (0x1U << ETH_MACSR_PMTS_Pos) /*!< 0x00000008 */
+#define ETH_MACSR_PMTS ETH_MACSR_PMTS_Msk /* PMT status */
+
+/* Bit definition for Ethernet MAC Interrupt Mask Register */
+#define ETH_MACIMR_TSTIM_Pos (9U)
+#define ETH_MACIMR_TSTIM_Msk (0x1U << ETH_MACIMR_TSTIM_Pos) /*!< 0x00000200 */
+#define ETH_MACIMR_TSTIM ETH_MACIMR_TSTIM_Msk /* Time stamp trigger interrupt mask */
+#define ETH_MACIMR_PMTIM_Pos (3U)
+#define ETH_MACIMR_PMTIM_Msk (0x1U << ETH_MACIMR_PMTIM_Pos) /*!< 0x00000008 */
+#define ETH_MACIMR_PMTIM ETH_MACIMR_PMTIM_Msk /* PMT interrupt mask */
+
+/* Bit definition for Ethernet MAC Address0 High Register */
+#define ETH_MACA0HR_MACA0H_Pos (0U)
+#define ETH_MACA0HR_MACA0H_Msk (0xFFFFU << ETH_MACA0HR_MACA0H_Pos) /*!< 0x0000FFFF */
+#define ETH_MACA0HR_MACA0H ETH_MACA0HR_MACA0H_Msk /* MAC address0 high */
+
+/* Bit definition for Ethernet MAC Address0 Low Register */
+#define ETH_MACA0LR_MACA0L_Pos (0U)
+#define ETH_MACA0LR_MACA0L_Msk (0xFFFFFFFFU << ETH_MACA0LR_MACA0L_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACA0LR_MACA0L ETH_MACA0LR_MACA0L_Msk /* MAC address0 low */
+
+/* Bit definition for Ethernet MAC Address1 High Register */
+#define ETH_MACA1HR_AE_Pos (31U)
+#define ETH_MACA1HR_AE_Msk (0x1U << ETH_MACA1HR_AE_Pos) /*!< 0x80000000 */
+#define ETH_MACA1HR_AE ETH_MACA1HR_AE_Msk /* Address enable */
+#define ETH_MACA1HR_SA_Pos (30U)
+#define ETH_MACA1HR_SA_Msk (0x1U << ETH_MACA1HR_SA_Pos) /*!< 0x40000000 */
+#define ETH_MACA1HR_SA ETH_MACA1HR_SA_Msk /* Source address */
+#define ETH_MACA1HR_MBC_Pos (24U)
+#define ETH_MACA1HR_MBC_Msk (0x3FU << ETH_MACA1HR_MBC_Pos) /*!< 0x3F000000 */
+#define ETH_MACA1HR_MBC ETH_MACA1HR_MBC_Msk /* Mask byte control: bits to mask for comparison of the MAC Address bytes */
+#define ETH_MACA1HR_MBC_HBits15_8 ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */
+#define ETH_MACA1HR_MBC_HBits7_0 ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */
+#define ETH_MACA1HR_MBC_LBits31_24 ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */
+#define ETH_MACA1HR_MBC_LBits23_16 ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */
+#define ETH_MACA1HR_MBC_LBits15_8 ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */
+#define ETH_MACA1HR_MBC_LBits7_0 ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [7:0] */
+#define ETH_MACA1HR_MACA1H_Pos (0U)
+#define ETH_MACA1HR_MACA1H_Msk (0xFFFFU << ETH_MACA1HR_MACA1H_Pos) /*!< 0x0000FFFF */
+#define ETH_MACA1HR_MACA1H ETH_MACA1HR_MACA1H_Msk /* MAC address1 high */
+
+/* Bit definition for Ethernet MAC Address1 Low Register */
+#define ETH_MACA1LR_MACA1L_Pos (0U)
+#define ETH_MACA1LR_MACA1L_Msk (0xFFFFFFFFU << ETH_MACA1LR_MACA1L_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACA1LR_MACA1L ETH_MACA1LR_MACA1L_Msk /* MAC address1 low */
+
+/* Bit definition for Ethernet MAC Address2 High Register */
+#define ETH_MACA2HR_AE_Pos (31U)
+#define ETH_MACA2HR_AE_Msk (0x1U << ETH_MACA2HR_AE_Pos) /*!< 0x80000000 */
+#define ETH_MACA2HR_AE ETH_MACA2HR_AE_Msk /* Address enable */
+#define ETH_MACA2HR_SA_Pos (30U)
+#define ETH_MACA2HR_SA_Msk (0x1U << ETH_MACA2HR_SA_Pos) /*!< 0x40000000 */
+#define ETH_MACA2HR_SA ETH_MACA2HR_SA_Msk /* Source address */
+#define ETH_MACA2HR_MBC_Pos (24U)
+#define ETH_MACA2HR_MBC_Msk (0x3FU << ETH_MACA2HR_MBC_Pos) /*!< 0x3F000000 */
+#define ETH_MACA2HR_MBC ETH_MACA2HR_MBC_Msk /* Mask byte control */
+#define ETH_MACA2HR_MBC_HBits15_8 ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */
+#define ETH_MACA2HR_MBC_HBits7_0 ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */
+#define ETH_MACA2HR_MBC_LBits31_24 ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */
+#define ETH_MACA2HR_MBC_LBits23_16 ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */
+#define ETH_MACA2HR_MBC_LBits15_8 ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */
+#define ETH_MACA2HR_MBC_LBits7_0 ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [70] */
+#define ETH_MACA2HR_MACA2H_Pos (0U)
+#define ETH_MACA2HR_MACA2H_Msk (0xFFFFU << ETH_MACA2HR_MACA2H_Pos) /*!< 0x0000FFFF */
+#define ETH_MACA2HR_MACA2H ETH_MACA2HR_MACA2H_Msk /* MAC address1 high */
+
+/* Bit definition for Ethernet MAC Address2 Low Register */
+#define ETH_MACA2LR_MACA2L_Pos (0U)
+#define ETH_MACA2LR_MACA2L_Msk (0xFFFFFFFFU << ETH_MACA2LR_MACA2L_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACA2LR_MACA2L ETH_MACA2LR_MACA2L_Msk /* MAC address2 low */
+
+/* Bit definition for Ethernet MAC Address3 High Register */
+#define ETH_MACA3HR_AE_Pos (31U)
+#define ETH_MACA3HR_AE_Msk (0x1U << ETH_MACA3HR_AE_Pos) /*!< 0x80000000 */
+#define ETH_MACA3HR_AE ETH_MACA3HR_AE_Msk /* Address enable */
+#define ETH_MACA3HR_SA_Pos (30U)
+#define ETH_MACA3HR_SA_Msk (0x1U << ETH_MACA3HR_SA_Pos) /*!< 0x40000000 */
+#define ETH_MACA3HR_SA ETH_MACA3HR_SA_Msk /* Source address */
+#define ETH_MACA3HR_MBC_Pos (24U)
+#define ETH_MACA3HR_MBC_Msk (0x3FU << ETH_MACA3HR_MBC_Pos) /*!< 0x3F000000 */
+#define ETH_MACA3HR_MBC ETH_MACA3HR_MBC_Msk /* Mask byte control */
+#define ETH_MACA3HR_MBC_HBits15_8 ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */
+#define ETH_MACA3HR_MBC_HBits7_0 ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */
+#define ETH_MACA3HR_MBC_LBits31_24 ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */
+#define ETH_MACA3HR_MBC_LBits23_16 ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */
+#define ETH_MACA3HR_MBC_LBits15_8 ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */
+#define ETH_MACA3HR_MBC_LBits7_0 ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [70] */
+#define ETH_MACA3HR_MACA3H_Pos (0U)
+#define ETH_MACA3HR_MACA3H_Msk (0xFFFFU << ETH_MACA3HR_MACA3H_Pos) /*!< 0x0000FFFF */
+#define ETH_MACA3HR_MACA3H ETH_MACA3HR_MACA3H_Msk /* MAC address3 high */
+
+/* Bit definition for Ethernet MAC Address3 Low Register */
+#define ETH_MACA3LR_MACA3L_Pos (0U)
+#define ETH_MACA3LR_MACA3L_Msk (0xFFFFFFFFU << ETH_MACA3LR_MACA3L_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACA3LR_MACA3L ETH_MACA3LR_MACA3L_Msk /* MAC address3 low */
+
+/******************************************************************************/
+/* Ethernet MMC Registers bits definition */
+/******************************************************************************/
+
+/* Bit definition for Ethernet MMC Contol Register */
+#define ETH_MMCCR_MCF_Pos (3U)
+#define ETH_MMCCR_MCF_Msk (0x1U << ETH_MMCCR_MCF_Pos) /*!< 0x00000008 */
+#define ETH_MMCCR_MCF ETH_MMCCR_MCF_Msk /* MMC Counter Freeze */
+#define ETH_MMCCR_ROR_Pos (2U)
+#define ETH_MMCCR_ROR_Msk (0x1U << ETH_MMCCR_ROR_Pos) /*!< 0x00000004 */
+#define ETH_MMCCR_ROR ETH_MMCCR_ROR_Msk /* Reset on Read */
+#define ETH_MMCCR_CSR_Pos (1U)
+#define ETH_MMCCR_CSR_Msk (0x1U << ETH_MMCCR_CSR_Pos) /*!< 0x00000002 */
+#define ETH_MMCCR_CSR ETH_MMCCR_CSR_Msk /* Counter Stop Rollover */
+#define ETH_MMCCR_CR_Pos (0U)
+#define ETH_MMCCR_CR_Msk (0x1U << ETH_MMCCR_CR_Pos) /*!< 0x00000001 */
+#define ETH_MMCCR_CR ETH_MMCCR_CR_Msk /* Counters Reset */
+
+/* Bit definition for Ethernet MMC Receive Interrupt Register */
+#define ETH_MMCRIR_RGUFS_Pos (17U)
+#define ETH_MMCRIR_RGUFS_Msk (0x1U << ETH_MMCRIR_RGUFS_Pos) /*!< 0x00020000 */
+#define ETH_MMCRIR_RGUFS ETH_MMCRIR_RGUFS_Msk /* Set when Rx good unicast frames counter reaches half the maximum value */
+#define ETH_MMCRIR_RFAES_Pos (6U)
+#define ETH_MMCRIR_RFAES_Msk (0x1U << ETH_MMCRIR_RFAES_Pos) /*!< 0x00000040 */
+#define ETH_MMCRIR_RFAES ETH_MMCRIR_RFAES_Msk /* Set when Rx alignment error counter reaches half the maximum value */
+#define ETH_MMCRIR_RFCES_Pos (5U)
+#define ETH_MMCRIR_RFCES_Msk (0x1U << ETH_MMCRIR_RFCES_Pos) /*!< 0x00000020 */
+#define ETH_MMCRIR_RFCES ETH_MMCRIR_RFCES_Msk /* Set when Rx crc error counter reaches half the maximum value */
+
+/* Bit definition for Ethernet MMC Transmit Interrupt Register */
+#define ETH_MMCTIR_TGFS_Pos (21U)
+#define ETH_MMCTIR_TGFS_Msk (0x1U << ETH_MMCTIR_TGFS_Pos) /*!< 0x00200000 */
+#define ETH_MMCTIR_TGFS ETH_MMCTIR_TGFS_Msk /* Set when Tx good frame count counter reaches half the maximum value */
+#define ETH_MMCTIR_TGFMSCS_Pos (15U)
+#define ETH_MMCTIR_TGFMSCS_Msk (0x1U << ETH_MMCTIR_TGFMSCS_Pos) /*!< 0x00008000 */
+#define ETH_MMCTIR_TGFMSCS ETH_MMCTIR_TGFMSCS_Msk /* Set when Tx good multi col counter reaches half the maximum value */
+#define ETH_MMCTIR_TGFSCS_Pos (14U)
+#define ETH_MMCTIR_TGFSCS_Msk (0x1U << ETH_MMCTIR_TGFSCS_Pos) /*!< 0x00004000 */
+#define ETH_MMCTIR_TGFSCS ETH_MMCTIR_TGFSCS_Msk /* Set when Tx good single col counter reaches half the maximum value */
+
+/* Bit definition for Ethernet MMC Receive Interrupt Mask Register */
+#define ETH_MMCRIMR_RGUFM_Pos (17U)
+#define ETH_MMCRIMR_RGUFM_Msk (0x1U << ETH_MMCRIMR_RGUFM_Pos) /*!< 0x00020000 */
+#define ETH_MMCRIMR_RGUFM ETH_MMCRIMR_RGUFM_Msk /* Mask the interrupt when Rx good unicast frames counter reaches half the maximum value */
+#define ETH_MMCRIMR_RFAEM_Pos (6U)
+#define ETH_MMCRIMR_RFAEM_Msk (0x1U << ETH_MMCRIMR_RFAEM_Pos) /*!< 0x00000040 */
+#define ETH_MMCRIMR_RFAEM ETH_MMCRIMR_RFAEM_Msk /* Mask the interrupt when when Rx alignment error counter reaches half the maximum value */
+#define ETH_MMCRIMR_RFCEM_Pos (5U)
+#define ETH_MMCRIMR_RFCEM_Msk (0x1U << ETH_MMCRIMR_RFCEM_Pos) /*!< 0x00000020 */
+#define ETH_MMCRIMR_RFCEM ETH_MMCRIMR_RFCEM_Msk /* Mask the interrupt when Rx crc error counter reaches half the maximum value */
+
+/* Bit definition for Ethernet MMC Transmit Interrupt Mask Register */
+#define ETH_MMCTIMR_TGFM_Pos (21U)
+#define ETH_MMCTIMR_TGFM_Msk (0x1U << ETH_MMCTIMR_TGFM_Pos) /*!< 0x00200000 */
+#define ETH_MMCTIMR_TGFM ETH_MMCTIMR_TGFM_Msk /* Mask the interrupt when Tx good frame count counter reaches half the maximum value */
+#define ETH_MMCTIMR_TGFMSCM_Pos (15U)
+#define ETH_MMCTIMR_TGFMSCM_Msk (0x1U << ETH_MMCTIMR_TGFMSCM_Pos) /*!< 0x00008000 */
+#define ETH_MMCTIMR_TGFMSCM ETH_MMCTIMR_TGFMSCM_Msk /* Mask the interrupt when Tx good multi col counter reaches half the maximum value */
+#define ETH_MMCTIMR_TGFSCM_Pos (14U)
+#define ETH_MMCTIMR_TGFSCM_Msk (0x1U << ETH_MMCTIMR_TGFSCM_Pos) /*!< 0x00004000 */
+#define ETH_MMCTIMR_TGFSCM ETH_MMCTIMR_TGFSCM_Msk /* Mask the interrupt when Tx good single col counter reaches half the maximum value */
+
+/* Bit definition for Ethernet MMC Transmitted Good Frames after Single Collision Counter Register */
+#define ETH_MMCTGFSCCR_TGFSCC_Pos (0U)
+#define ETH_MMCTGFSCCR_TGFSCC_Msk (0xFFFFFFFFU << ETH_MMCTGFSCCR_TGFSCC_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MMCTGFSCCR_TGFSCC ETH_MMCTGFSCCR_TGFSCC_Msk /* Number of successfully transmitted frames after a single collision in Half-duplex mode. */
+
+/* Bit definition for Ethernet MMC Transmitted Good Frames after More than a Single Collision Counter Register */
+#define ETH_MMCTGFMSCCR_TGFMSCC_Pos (0U)
+#define ETH_MMCTGFMSCCR_TGFMSCC_Msk (0xFFFFFFFFU << ETH_MMCTGFMSCCR_TGFMSCC_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MMCTGFMSCCR_TGFMSCC ETH_MMCTGFMSCCR_TGFMSCC_Msk /* Number of successfully transmitted frames after more than a single collision in Half-duplex mode. */
+
+/* Bit definition for Ethernet MMC Transmitted Good Frames Counter Register */
+#define ETH_MMCTGFCR_TGFC_Pos (0U)
+#define ETH_MMCTGFCR_TGFC_Msk (0xFFFFFFFFU << ETH_MMCTGFCR_TGFC_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MMCTGFCR_TGFC ETH_MMCTGFCR_TGFC_Msk /* Number of good frames transmitted. */
+
+/* Bit definition for Ethernet MMC Received Frames with CRC Error Counter Register */
+#define ETH_MMCRFCECR_RFCEC_Pos (0U)
+#define ETH_MMCRFCECR_RFCEC_Msk (0xFFFFFFFFU << ETH_MMCRFCECR_RFCEC_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MMCRFCECR_RFCEC ETH_MMCRFCECR_RFCEC_Msk /* Number of frames received with CRC error. */
+
+/* Bit definition for Ethernet MMC Received Frames with Alignement Error Counter Register */
+#define ETH_MMCRFAECR_RFAEC_Pos (0U)
+#define ETH_MMCRFAECR_RFAEC_Msk (0xFFFFFFFFU << ETH_MMCRFAECR_RFAEC_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MMCRFAECR_RFAEC ETH_MMCRFAECR_RFAEC_Msk /* Number of frames received with alignment (dribble) error */
+
+/* Bit definition for Ethernet MMC Received Good Unicast Frames Counter Register */
+#define ETH_MMCRGUFCR_RGUFC_Pos (0U)
+#define ETH_MMCRGUFCR_RGUFC_Msk (0xFFFFFFFFU << ETH_MMCRGUFCR_RGUFC_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MMCRGUFCR_RGUFC ETH_MMCRGUFCR_RGUFC_Msk /* Number of good unicast frames received. */
+
+/******************************************************************************/
+/* Ethernet PTP Registers bits definition */
+/******************************************************************************/
+
+/* Bit definition for Ethernet PTP Time Stamp Contol Register */
+#define ETH_PTPTSCR_TSARU_Pos (5U)
+#define ETH_PTPTSCR_TSARU_Msk (0x1U << ETH_PTPTSCR_TSARU_Pos) /*!< 0x00000020 */
+#define ETH_PTPTSCR_TSARU ETH_PTPTSCR_TSARU_Msk /* Addend register update */
+#define ETH_PTPTSCR_TSITE_Pos (4U)
+#define ETH_PTPTSCR_TSITE_Msk (0x1U << ETH_PTPTSCR_TSITE_Pos) /*!< 0x00000010 */
+#define ETH_PTPTSCR_TSITE ETH_PTPTSCR_TSITE_Msk /* Time stamp interrupt trigger enable */
+#define ETH_PTPTSCR_TSSTU_Pos (3U)
+#define ETH_PTPTSCR_TSSTU_Msk (0x1U << ETH_PTPTSCR_TSSTU_Pos) /*!< 0x00000008 */
+#define ETH_PTPTSCR_TSSTU ETH_PTPTSCR_TSSTU_Msk /* Time stamp update */
+#define ETH_PTPTSCR_TSSTI_Pos (2U)
+#define ETH_PTPTSCR_TSSTI_Msk (0x1U << ETH_PTPTSCR_TSSTI_Pos) /*!< 0x00000004 */
+#define ETH_PTPTSCR_TSSTI ETH_PTPTSCR_TSSTI_Msk /* Time stamp initialize */
+#define ETH_PTPTSCR_TSFCU_Pos (1U)
+#define ETH_PTPTSCR_TSFCU_Msk (0x1U << ETH_PTPTSCR_TSFCU_Pos) /*!< 0x00000002 */
+#define ETH_PTPTSCR_TSFCU ETH_PTPTSCR_TSFCU_Msk /* Time stamp fine or coarse update */
+#define ETH_PTPTSCR_TSE_Pos (0U)
+#define ETH_PTPTSCR_TSE_Msk (0x1U << ETH_PTPTSCR_TSE_Pos) /*!< 0x00000001 */
+#define ETH_PTPTSCR_TSE ETH_PTPTSCR_TSE_Msk /* Time stamp enable */
+
+/* Bit definition for Ethernet PTP Sub-Second Increment Register */
+#define ETH_PTPSSIR_STSSI_Pos (0U)
+#define ETH_PTPSSIR_STSSI_Msk (0xFFU << ETH_PTPSSIR_STSSI_Pos) /*!< 0x000000FF */
+#define ETH_PTPSSIR_STSSI ETH_PTPSSIR_STSSI_Msk /* System time Sub-second increment value */
+
+/* Bit definition for Ethernet PTP Time Stamp High Register */
+#define ETH_PTPTSHR_STS_Pos (0U)
+#define ETH_PTPTSHR_STS_Msk (0xFFFFFFFFU << ETH_PTPTSHR_STS_Pos) /*!< 0xFFFFFFFF */
+#define ETH_PTPTSHR_STS ETH_PTPTSHR_STS_Msk /* System Time second */
+
+/* Bit definition for Ethernet PTP Time Stamp Low Register */
+#define ETH_PTPTSLR_STPNS_Pos (31U)
+#define ETH_PTPTSLR_STPNS_Msk (0x1U << ETH_PTPTSLR_STPNS_Pos) /*!< 0x80000000 */
+#define ETH_PTPTSLR_STPNS ETH_PTPTSLR_STPNS_Msk /* System Time Positive or negative time */
+#define ETH_PTPTSLR_STSS_Pos (0U)
+#define ETH_PTPTSLR_STSS_Msk (0x7FFFFFFFU << ETH_PTPTSLR_STSS_Pos) /*!< 0x7FFFFFFF */
+#define ETH_PTPTSLR_STSS ETH_PTPTSLR_STSS_Msk /* System Time sub-seconds */
+
+/* Bit definition for Ethernet PTP Time Stamp High Update Register */
+#define ETH_PTPTSHUR_TSUS_Pos (0U)
+#define ETH_PTPTSHUR_TSUS_Msk (0xFFFFFFFFU << ETH_PTPTSHUR_TSUS_Pos) /*!< 0xFFFFFFFF */
+#define ETH_PTPTSHUR_TSUS ETH_PTPTSHUR_TSUS_Msk /* Time stamp update seconds */
+
+/* Bit definition for Ethernet PTP Time Stamp Low Update Register */
+#define ETH_PTPTSLUR_TSUPNS_Pos (31U)
+#define ETH_PTPTSLUR_TSUPNS_Msk (0x1U << ETH_PTPTSLUR_TSUPNS_Pos) /*!< 0x80000000 */
+#define ETH_PTPTSLUR_TSUPNS ETH_PTPTSLUR_TSUPNS_Msk /* Time stamp update Positive or negative time */
+#define ETH_PTPTSLUR_TSUSS_Pos (0U)
+#define ETH_PTPTSLUR_TSUSS_Msk (0x7FFFFFFFU << ETH_PTPTSLUR_TSUSS_Pos) /*!< 0x7FFFFFFF */
+#define ETH_PTPTSLUR_TSUSS ETH_PTPTSLUR_TSUSS_Msk /* Time stamp update sub-seconds */
+
+/* Bit definition for Ethernet PTP Time Stamp Addend Register */
+#define ETH_PTPTSAR_TSA_Pos (0U)
+#define ETH_PTPTSAR_TSA_Msk (0xFFFFFFFFU << ETH_PTPTSAR_TSA_Pos) /*!< 0xFFFFFFFF */
+#define ETH_PTPTSAR_TSA ETH_PTPTSAR_TSA_Msk /* Time stamp addend */
+
+/* Bit definition for Ethernet PTP Target Time High Register */
+#define ETH_PTPTTHR_TTSH_Pos (0U)
+#define ETH_PTPTTHR_TTSH_Msk (0xFFFFFFFFU << ETH_PTPTTHR_TTSH_Pos) /*!< 0xFFFFFFFF */
+#define ETH_PTPTTHR_TTSH ETH_PTPTTHR_TTSH_Msk /* Target time stamp high */
+
+/* Bit definition for Ethernet PTP Target Time Low Register */
+#define ETH_PTPTTLR_TTSL_Pos (0U)
+#define ETH_PTPTTLR_TTSL_Msk (0xFFFFFFFFU << ETH_PTPTTLR_TTSL_Pos) /*!< 0xFFFFFFFF */
+#define ETH_PTPTTLR_TTSL ETH_PTPTTLR_TTSL_Msk /* Target time stamp low */
+
+/******************************************************************************/
+/* Ethernet DMA Registers bits definition */
+/******************************************************************************/
+
+/* Bit definition for Ethernet DMA Bus Mode Register */
+#define ETH_DMABMR_AAB_Pos (25U)
+#define ETH_DMABMR_AAB_Msk (0x1U << ETH_DMABMR_AAB_Pos) /*!< 0x02000000 */
+#define ETH_DMABMR_AAB ETH_DMABMR_AAB_Msk /* Address-Aligned beats */
+#define ETH_DMABMR_FPM_Pos (24U)
+#define ETH_DMABMR_FPM_Msk (0x1U << ETH_DMABMR_FPM_Pos) /*!< 0x01000000 */
+#define ETH_DMABMR_FPM ETH_DMABMR_FPM_Msk /* 4xPBL mode */
+#define ETH_DMABMR_USP_Pos (23U)
+#define ETH_DMABMR_USP_Msk (0x1U << ETH_DMABMR_USP_Pos) /*!< 0x00800000 */
+#define ETH_DMABMR_USP ETH_DMABMR_USP_Msk /* Use separate PBL */
+#define ETH_DMABMR_RDP_Pos (17U)
+#define ETH_DMABMR_RDP_Msk (0x3FU << ETH_DMABMR_RDP_Pos) /*!< 0x007E0000 */
+#define ETH_DMABMR_RDP ETH_DMABMR_RDP_Msk /* RxDMA PBL */
+#define ETH_DMABMR_RDP_1Beat ((uint32_t)0x00020000) /* maximum number of beats to be transferred in one RxDMA transaction is 1 */
+#define ETH_DMABMR_RDP_2Beat ((uint32_t)0x00040000) /* maximum number of beats to be transferred in one RxDMA transaction is 2 */
+#define ETH_DMABMR_RDP_4Beat ((uint32_t)0x00080000) /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
+#define ETH_DMABMR_RDP_8Beat ((uint32_t)0x00100000) /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
+#define ETH_DMABMR_RDP_16Beat ((uint32_t)0x00200000) /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
+#define ETH_DMABMR_RDP_32Beat ((uint32_t)0x00400000) /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
+#define ETH_DMABMR_RDP_4xPBL_4Beat ((uint32_t)0x01020000) /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
+#define ETH_DMABMR_RDP_4xPBL_8Beat ((uint32_t)0x01040000) /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
+#define ETH_DMABMR_RDP_4xPBL_16Beat ((uint32_t)0x01080000) /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
+#define ETH_DMABMR_RDP_4xPBL_32Beat ((uint32_t)0x01100000) /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
+#define ETH_DMABMR_RDP_4xPBL_64Beat ((uint32_t)0x01200000) /* maximum number of beats to be transferred in one RxDMA transaction is 64 */
+#define ETH_DMABMR_RDP_4xPBL_128Beat ((uint32_t)0x01400000) /* maximum number of beats to be transferred in one RxDMA transaction is 128 */
+#define ETH_DMABMR_FB_Pos (16U)
+#define ETH_DMABMR_FB_Msk (0x1U << ETH_DMABMR_FB_Pos) /*!< 0x00010000 */
+#define ETH_DMABMR_FB ETH_DMABMR_FB_Msk /* Fixed Burst */
+#define ETH_DMABMR_RTPR_Pos (14U)
+#define ETH_DMABMR_RTPR_Msk (0x3U << ETH_DMABMR_RTPR_Pos) /*!< 0x0000C000 */
+#define ETH_DMABMR_RTPR ETH_DMABMR_RTPR_Msk /* Rx Tx priority ratio */
+#define ETH_DMABMR_RTPR_1_1 ((uint32_t)0x00000000) /* Rx Tx priority ratio */
+#define ETH_DMABMR_RTPR_2_1 ((uint32_t)0x00004000) /* Rx Tx priority ratio */
+#define ETH_DMABMR_RTPR_3_1 ((uint32_t)0x00008000) /* Rx Tx priority ratio */
+#define ETH_DMABMR_RTPR_4_1 ((uint32_t)0x0000C000) /* Rx Tx priority ratio */
+#define ETH_DMABMR_PBL_Pos (8U)
+#define ETH_DMABMR_PBL_Msk (0x3FU << ETH_DMABMR_PBL_Pos) /*!< 0x00003F00 */
+#define ETH_DMABMR_PBL ETH_DMABMR_PBL_Msk /* Programmable burst length */
+#define ETH_DMABMR_PBL_1Beat ((uint32_t)0x00000100) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */
+#define ETH_DMABMR_PBL_2Beat ((uint32_t)0x00000200) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */
+#define ETH_DMABMR_PBL_4Beat ((uint32_t)0x00000400) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
+#define ETH_DMABMR_PBL_8Beat ((uint32_t)0x00000800) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
+#define ETH_DMABMR_PBL_16Beat ((uint32_t)0x00001000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
+#define ETH_DMABMR_PBL_32Beat ((uint32_t)0x00002000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
+#define ETH_DMABMR_PBL_4xPBL_4Beat ((uint32_t)0x01000100) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
+#define ETH_DMABMR_PBL_4xPBL_8Beat ((uint32_t)0x01000200) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
+#define ETH_DMABMR_PBL_4xPBL_16Beat ((uint32_t)0x01000400) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
+#define ETH_DMABMR_PBL_4xPBL_32Beat ((uint32_t)0x01000800) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
+#define ETH_DMABMR_PBL_4xPBL_64Beat ((uint32_t)0x01001000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */
+#define ETH_DMABMR_PBL_4xPBL_128Beat ((uint32_t)0x01002000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */
+#define ETH_DMABMR_DSL_Pos (2U)
+#define ETH_DMABMR_DSL_Msk (0x1FU << ETH_DMABMR_DSL_Pos) /*!< 0x0000007C */
+#define ETH_DMABMR_DSL ETH_DMABMR_DSL_Msk /* Descriptor Skip Length */
+#define ETH_DMABMR_DA_Pos (1U)
+#define ETH_DMABMR_DA_Msk (0x1U << ETH_DMABMR_DA_Pos) /*!< 0x00000002 */
+#define ETH_DMABMR_DA ETH_DMABMR_DA_Msk /* DMA arbitration scheme */
+#define ETH_DMABMR_SR_Pos (0U)
+#define ETH_DMABMR_SR_Msk (0x1U << ETH_DMABMR_SR_Pos) /*!< 0x00000001 */
+#define ETH_DMABMR_SR ETH_DMABMR_SR_Msk /* Software reset */
+
+/* Bit definition for Ethernet DMA Transmit Poll Demand Register */
+#define ETH_DMATPDR_TPD_Pos (0U)
+#define ETH_DMATPDR_TPD_Msk (0xFFFFFFFFU << ETH_DMATPDR_TPD_Pos) /*!< 0xFFFFFFFF */
+#define ETH_DMATPDR_TPD ETH_DMATPDR_TPD_Msk /* Transmit poll demand */
+
+/* Bit definition for Ethernet DMA Receive Poll Demand Register */
+#define ETH_DMARPDR_RPD_Pos (0U)
+#define ETH_DMARPDR_RPD_Msk (0xFFFFFFFFU << ETH_DMARPDR_RPD_Pos) /*!< 0xFFFFFFFF */
+#define ETH_DMARPDR_RPD ETH_DMARPDR_RPD_Msk /* Receive poll demand */
+
+/* Bit definition for Ethernet DMA Receive Descriptor List Address Register */
+#define ETH_DMARDLAR_SRL_Pos (0U)
+#define ETH_DMARDLAR_SRL_Msk (0xFFFFFFFFU << ETH_DMARDLAR_SRL_Pos) /*!< 0xFFFFFFFF */
+#define ETH_DMARDLAR_SRL ETH_DMARDLAR_SRL_Msk /* Start of receive list */
+
+/* Bit definition for Ethernet DMA Transmit Descriptor List Address Register */
+#define ETH_DMATDLAR_STL_Pos (0U)
+#define ETH_DMATDLAR_STL_Msk (0xFFFFFFFFU << ETH_DMATDLAR_STL_Pos) /*!< 0xFFFFFFFF */
+#define ETH_DMATDLAR_STL ETH_DMATDLAR_STL_Msk /* Start of transmit list */
+
+/* Bit definition for Ethernet DMA Status Register */
+#define ETH_DMASR_TSTS_Pos (29U)
+#define ETH_DMASR_TSTS_Msk (0x1U << ETH_DMASR_TSTS_Pos) /*!< 0x20000000 */
+#define ETH_DMASR_TSTS ETH_DMASR_TSTS_Msk /* Time-stamp trigger status */
+#define ETH_DMASR_PMTS_Pos (28U)
+#define ETH_DMASR_PMTS_Msk (0x1U << ETH_DMASR_PMTS_Pos) /*!< 0x10000000 */
+#define ETH_DMASR_PMTS ETH_DMASR_PMTS_Msk /* PMT status */
+#define ETH_DMASR_MMCS_Pos (27U)
+#define ETH_DMASR_MMCS_Msk (0x1U << ETH_DMASR_MMCS_Pos) /*!< 0x08000000 */
+#define ETH_DMASR_MMCS ETH_DMASR_MMCS_Msk /* MMC status */
+#define ETH_DMASR_EBS_Pos (23U)
+#define ETH_DMASR_EBS_Msk (0x7U << ETH_DMASR_EBS_Pos) /*!< 0x03800000 */
+#define ETH_DMASR_EBS ETH_DMASR_EBS_Msk /* Error bits status */
+ /* combination with EBS[2:0] for GetFlagStatus function */
+#define ETH_DMASR_EBS_DescAccess_Pos (25U)
+#define ETH_DMASR_EBS_DescAccess_Msk (0x1U << ETH_DMASR_EBS_DescAccess_Pos) /*!< 0x02000000 */
+#define ETH_DMASR_EBS_DescAccess ETH_DMASR_EBS_DescAccess_Msk /* Error bits 0-data buffer, 1-desc. access */
+#define ETH_DMASR_EBS_ReadTransf_Pos (24U)
+#define ETH_DMASR_EBS_ReadTransf_Msk (0x1U << ETH_DMASR_EBS_ReadTransf_Pos) /*!< 0x01000000 */
+#define ETH_DMASR_EBS_ReadTransf ETH_DMASR_EBS_ReadTransf_Msk /* Error bits 0-write trnsf, 1-read transfr */
+#define ETH_DMASR_EBS_DataTransfTx_Pos (23U)
+#define ETH_DMASR_EBS_DataTransfTx_Msk (0x1U << ETH_DMASR_EBS_DataTransfTx_Pos) /*!< 0x00800000 */
+#define ETH_DMASR_EBS_DataTransfTx ETH_DMASR_EBS_DataTransfTx_Msk /* Error bits 0-Rx DMA, 1-Tx DMA */
+#define ETH_DMASR_TPS_Pos (20U)
+#define ETH_DMASR_TPS_Msk (0x7U << ETH_DMASR_TPS_Pos) /*!< 0x00700000 */
+#define ETH_DMASR_TPS ETH_DMASR_TPS_Msk /* Transmit process state */
+#define ETH_DMASR_TPS_Stopped ((uint32_t)0x00000000) /* Stopped - Reset or Stop Tx Command issued */
+#define ETH_DMASR_TPS_Fetching_Pos (20U)
+#define ETH_DMASR_TPS_Fetching_Msk (0x1U << ETH_DMASR_TPS_Fetching_Pos) /*!< 0x00100000 */
+#define ETH_DMASR_TPS_Fetching ETH_DMASR_TPS_Fetching_Msk /* Running - fetching the Tx descriptor */
+#define ETH_DMASR_TPS_Waiting_Pos (21U)
+#define ETH_DMASR_TPS_Waiting_Msk (0x1U << ETH_DMASR_TPS_Waiting_Pos) /*!< 0x00200000 */
+#define ETH_DMASR_TPS_Waiting ETH_DMASR_TPS_Waiting_Msk /* Running - waiting for status */
+#define ETH_DMASR_TPS_Reading_Pos (20U)
+#define ETH_DMASR_TPS_Reading_Msk (0x3U << ETH_DMASR_TPS_Reading_Pos) /*!< 0x00300000 */
+#define ETH_DMASR_TPS_Reading ETH_DMASR_TPS_Reading_Msk /* Running - reading the data from host memory */
+#define ETH_DMASR_TPS_Suspended_Pos (21U)
+#define ETH_DMASR_TPS_Suspended_Msk (0x3U << ETH_DMASR_TPS_Suspended_Pos) /*!< 0x00600000 */
+#define ETH_DMASR_TPS_Suspended ETH_DMASR_TPS_Suspended_Msk /* Suspended - Tx Descriptor unavailabe */
+#define ETH_DMASR_TPS_Closing_Pos (20U)
+#define ETH_DMASR_TPS_Closing_Msk (0x7U << ETH_DMASR_TPS_Closing_Pos) /*!< 0x00700000 */
+#define ETH_DMASR_TPS_Closing ETH_DMASR_TPS_Closing_Msk /* Running - closing Rx descriptor */
+#define ETH_DMASR_RPS_Pos (17U)
+#define ETH_DMASR_RPS_Msk (0x7U << ETH_DMASR_RPS_Pos) /*!< 0x000E0000 */
+#define ETH_DMASR_RPS ETH_DMASR_RPS_Msk /* Receive process state */
+#define ETH_DMASR_RPS_Stopped ((uint32_t)0x00000000) /* Stopped - Reset or Stop Rx Command issued */
+#define ETH_DMASR_RPS_Fetching_Pos (17U)
+#define ETH_DMASR_RPS_Fetching_Msk (0x1U << ETH_DMASR_RPS_Fetching_Pos) /*!< 0x00020000 */
+#define ETH_DMASR_RPS_Fetching ETH_DMASR_RPS_Fetching_Msk /* Running - fetching the Rx descriptor */
+#define ETH_DMASR_RPS_Waiting_Pos (17U)
+#define ETH_DMASR_RPS_Waiting_Msk (0x3U << ETH_DMASR_RPS_Waiting_Pos) /*!< 0x00060000 */
+#define ETH_DMASR_RPS_Waiting ETH_DMASR_RPS_Waiting_Msk /* Running - waiting for packet */
+#define ETH_DMASR_RPS_Suspended_Pos (19U)
+#define ETH_DMASR_RPS_Suspended_Msk (0x1U << ETH_DMASR_RPS_Suspended_Pos) /*!< 0x00080000 */
+#define ETH_DMASR_RPS_Suspended ETH_DMASR_RPS_Suspended_Msk /* Suspended - Rx Descriptor unavailable */
+#define ETH_DMASR_RPS_Closing_Pos (17U)
+#define ETH_DMASR_RPS_Closing_Msk (0x5U << ETH_DMASR_RPS_Closing_Pos) /*!< 0x000A0000 */
+#define ETH_DMASR_RPS_Closing ETH_DMASR_RPS_Closing_Msk /* Running - closing descriptor */
+#define ETH_DMASR_RPS_Queuing_Pos (17U)
+#define ETH_DMASR_RPS_Queuing_Msk (0x7U << ETH_DMASR_RPS_Queuing_Pos) /*!< 0x000E0000 */
+#define ETH_DMASR_RPS_Queuing ETH_DMASR_RPS_Queuing_Msk /* Running - queuing the recieve frame into host memory */
+#define ETH_DMASR_NIS_Pos (16U)
+#define ETH_DMASR_NIS_Msk (0x1U << ETH_DMASR_NIS_Pos) /*!< 0x00010000 */
+#define ETH_DMASR_NIS ETH_DMASR_NIS_Msk /* Normal interrupt summary */
+#define ETH_DMASR_AIS_Pos (15U)
+#define ETH_DMASR_AIS_Msk (0x1U << ETH_DMASR_AIS_Pos) /*!< 0x00008000 */
+#define ETH_DMASR_AIS ETH_DMASR_AIS_Msk /* Abnormal interrupt summary */
+#define ETH_DMASR_ERS_Pos (14U)
+#define ETH_DMASR_ERS_Msk (0x1U << ETH_DMASR_ERS_Pos) /*!< 0x00004000 */
+#define ETH_DMASR_ERS ETH_DMASR_ERS_Msk /* Early receive status */
+#define ETH_DMASR_FBES_Pos (13U)
+#define ETH_DMASR_FBES_Msk (0x1U << ETH_DMASR_FBES_Pos) /*!< 0x00002000 */
+#define ETH_DMASR_FBES ETH_DMASR_FBES_Msk /* Fatal bus error status */
+#define ETH_DMASR_ETS_Pos (10U)
+#define ETH_DMASR_ETS_Msk (0x1U << ETH_DMASR_ETS_Pos) /*!< 0x00000400 */
+#define ETH_DMASR_ETS ETH_DMASR_ETS_Msk /* Early transmit status */
+#define ETH_DMASR_RWTS_Pos (9U)
+#define ETH_DMASR_RWTS_Msk (0x1U << ETH_DMASR_RWTS_Pos) /*!< 0x00000200 */
+#define ETH_DMASR_RWTS ETH_DMASR_RWTS_Msk /* Receive watchdog timeout status */
+#define ETH_DMASR_RPSS_Pos (8U)
+#define ETH_DMASR_RPSS_Msk (0x1U << ETH_DMASR_RPSS_Pos) /*!< 0x00000100 */
+#define ETH_DMASR_RPSS ETH_DMASR_RPSS_Msk /* Receive process stopped status */
+#define ETH_DMASR_RBUS_Pos (7U)
+#define ETH_DMASR_RBUS_Msk (0x1U << ETH_DMASR_RBUS_Pos) /*!< 0x00000080 */
+#define ETH_DMASR_RBUS ETH_DMASR_RBUS_Msk /* Receive buffer unavailable status */
+#define ETH_DMASR_RS_Pos (6U)
+#define ETH_DMASR_RS_Msk (0x1U << ETH_DMASR_RS_Pos) /*!< 0x00000040 */
+#define ETH_DMASR_RS ETH_DMASR_RS_Msk /* Receive status */
+#define ETH_DMASR_TUS_Pos (5U)
+#define ETH_DMASR_TUS_Msk (0x1U << ETH_DMASR_TUS_Pos) /*!< 0x00000020 */
+#define ETH_DMASR_TUS ETH_DMASR_TUS_Msk /* Transmit underflow status */
+#define ETH_DMASR_ROS_Pos (4U)
+#define ETH_DMASR_ROS_Msk (0x1U << ETH_DMASR_ROS_Pos) /*!< 0x00000010 */
+#define ETH_DMASR_ROS ETH_DMASR_ROS_Msk /* Receive overflow status */
+#define ETH_DMASR_TJTS_Pos (3U)
+#define ETH_DMASR_TJTS_Msk (0x1U << ETH_DMASR_TJTS_Pos) /*!< 0x00000008 */
+#define ETH_DMASR_TJTS ETH_DMASR_TJTS_Msk /* Transmit jabber timeout status */
+#define ETH_DMASR_TBUS_Pos (2U)
+#define ETH_DMASR_TBUS_Msk (0x1U << ETH_DMASR_TBUS_Pos) /*!< 0x00000004 */
+#define ETH_DMASR_TBUS ETH_DMASR_TBUS_Msk /* Transmit buffer unavailable status */
+#define ETH_DMASR_TPSS_Pos (1U)
+#define ETH_DMASR_TPSS_Msk (0x1U << ETH_DMASR_TPSS_Pos) /*!< 0x00000002 */
+#define ETH_DMASR_TPSS ETH_DMASR_TPSS_Msk /* Transmit process stopped status */
+#define ETH_DMASR_TS_Pos (0U)
+#define ETH_DMASR_TS_Msk (0x1U << ETH_DMASR_TS_Pos) /*!< 0x00000001 */
+#define ETH_DMASR_TS ETH_DMASR_TS_Msk /* Transmit status */
+
+/* Bit definition for Ethernet DMA Operation Mode Register */
+#define ETH_DMAOMR_DTCEFD_Pos (26U)
+#define ETH_DMAOMR_DTCEFD_Msk (0x1U << ETH_DMAOMR_DTCEFD_Pos) /*!< 0x04000000 */
+#define ETH_DMAOMR_DTCEFD ETH_DMAOMR_DTCEFD_Msk /* Disable Dropping of TCP/IP checksum error frames */
+#define ETH_DMAOMR_RSF_Pos (25U)
+#define ETH_DMAOMR_RSF_Msk (0x1U << ETH_DMAOMR_RSF_Pos) /*!< 0x02000000 */
+#define ETH_DMAOMR_RSF ETH_DMAOMR_RSF_Msk /* Receive store and forward */
+#define ETH_DMAOMR_DFRF_Pos (24U)
+#define ETH_DMAOMR_DFRF_Msk (0x1U << ETH_DMAOMR_DFRF_Pos) /*!< 0x01000000 */
+#define ETH_DMAOMR_DFRF ETH_DMAOMR_DFRF_Msk /* Disable flushing of received frames */
+#define ETH_DMAOMR_TSF_Pos (21U)
+#define ETH_DMAOMR_TSF_Msk (0x1U << ETH_DMAOMR_TSF_Pos) /*!< 0x00200000 */
+#define ETH_DMAOMR_TSF ETH_DMAOMR_TSF_Msk /* Transmit store and forward */
+#define ETH_DMAOMR_FTF_Pos (20U)
+#define ETH_DMAOMR_FTF_Msk (0x1U << ETH_DMAOMR_FTF_Pos) /*!< 0x00100000 */
+#define ETH_DMAOMR_FTF ETH_DMAOMR_FTF_Msk /* Flush transmit FIFO */
+#define ETH_DMAOMR_TTC_Pos (14U)
+#define ETH_DMAOMR_TTC_Msk (0x7U << ETH_DMAOMR_TTC_Pos) /*!< 0x0001C000 */
+#define ETH_DMAOMR_TTC ETH_DMAOMR_TTC_Msk /* Transmit threshold control */
+#define ETH_DMAOMR_TTC_64Bytes ((uint32_t)0x00000000) /* threshold level of the MTL Transmit FIFO is 64 Bytes */
+#define ETH_DMAOMR_TTC_128Bytes ((uint32_t)0x00004000) /* threshold level of the MTL Transmit FIFO is 128 Bytes */
+#define ETH_DMAOMR_TTC_192Bytes ((uint32_t)0x00008000) /* threshold level of the MTL Transmit FIFO is 192 Bytes */
+#define ETH_DMAOMR_TTC_256Bytes ((uint32_t)0x0000C000) /* threshold level of the MTL Transmit FIFO is 256 Bytes */
+#define ETH_DMAOMR_TTC_40Bytes ((uint32_t)0x00010000) /* threshold level of the MTL Transmit FIFO is 40 Bytes */
+#define ETH_DMAOMR_TTC_32Bytes ((uint32_t)0x00014000) /* threshold level of the MTL Transmit FIFO is 32 Bytes */
+#define ETH_DMAOMR_TTC_24Bytes ((uint32_t)0x00018000) /* threshold level of the MTL Transmit FIFO is 24 Bytes */
+#define ETH_DMAOMR_TTC_16Bytes ((uint32_t)0x0001C000) /* threshold level of the MTL Transmit FIFO is 16 Bytes */
+#define ETH_DMAOMR_ST_Pos (13U)
+#define ETH_DMAOMR_ST_Msk (0x1U << ETH_DMAOMR_ST_Pos) /*!< 0x00002000 */
+#define ETH_DMAOMR_ST ETH_DMAOMR_ST_Msk /* Start/stop transmission command */
+#define ETH_DMAOMR_FEF_Pos (7U)
+#define ETH_DMAOMR_FEF_Msk (0x1U << ETH_DMAOMR_FEF_Pos) /*!< 0x00000080 */
+#define ETH_DMAOMR_FEF ETH_DMAOMR_FEF_Msk /* Forward error frames */
+#define ETH_DMAOMR_FUGF_Pos (6U)
+#define ETH_DMAOMR_FUGF_Msk (0x1U << ETH_DMAOMR_FUGF_Pos) /*!< 0x00000040 */
+#define ETH_DMAOMR_FUGF ETH_DMAOMR_FUGF_Msk /* Forward undersized good frames */
+#define ETH_DMAOMR_RTC_Pos (3U)
+#define ETH_DMAOMR_RTC_Msk (0x3U << ETH_DMAOMR_RTC_Pos) /*!< 0x00000018 */
+#define ETH_DMAOMR_RTC ETH_DMAOMR_RTC_Msk /* receive threshold control */
+#define ETH_DMAOMR_RTC_64Bytes ((uint32_t)0x00000000) /* threshold level of the MTL Receive FIFO is 64 Bytes */
+#define ETH_DMAOMR_RTC_32Bytes ((uint32_t)0x00000008) /* threshold level of the MTL Receive FIFO is 32 Bytes */
+#define ETH_DMAOMR_RTC_96Bytes ((uint32_t)0x00000010) /* threshold level of the MTL Receive FIFO is 96 Bytes */
+#define ETH_DMAOMR_RTC_128Bytes ((uint32_t)0x00000018) /* threshold level of the MTL Receive FIFO is 128 Bytes */
+#define ETH_DMAOMR_OSF_Pos (2U)
+#define ETH_DMAOMR_OSF_Msk (0x1U << ETH_DMAOMR_OSF_Pos) /*!< 0x00000004 */
+#define ETH_DMAOMR_OSF ETH_DMAOMR_OSF_Msk /* operate on second frame */
+#define ETH_DMAOMR_SR_Pos (1U)
+#define ETH_DMAOMR_SR_Msk (0x1U << ETH_DMAOMR_SR_Pos) /*!< 0x00000002 */
+#define ETH_DMAOMR_SR ETH_DMAOMR_SR_Msk /* Start/stop receive */
+
+/* Bit definition for Ethernet DMA Interrupt Enable Register */
+#define ETH_DMAIER_NISE_Pos (16U)
+#define ETH_DMAIER_NISE_Msk (0x1U << ETH_DMAIER_NISE_Pos) /*!< 0x00010000 */
+#define ETH_DMAIER_NISE ETH_DMAIER_NISE_Msk /* Normal interrupt summary enable */
+#define ETH_DMAIER_AISE_Pos (15U)
+#define ETH_DMAIER_AISE_Msk (0x1U << ETH_DMAIER_AISE_Pos) /*!< 0x00008000 */
+#define ETH_DMAIER_AISE ETH_DMAIER_AISE_Msk /* Abnormal interrupt summary enable */
+#define ETH_DMAIER_ERIE_Pos (14U)
+#define ETH_DMAIER_ERIE_Msk (0x1U << ETH_DMAIER_ERIE_Pos) /*!< 0x00004000 */
+#define ETH_DMAIER_ERIE ETH_DMAIER_ERIE_Msk /* Early receive interrupt enable */
+#define ETH_DMAIER_FBEIE_Pos (13U)
+#define ETH_DMAIER_FBEIE_Msk (0x1U << ETH_DMAIER_FBEIE_Pos) /*!< 0x00002000 */
+#define ETH_DMAIER_FBEIE ETH_DMAIER_FBEIE_Msk /* Fatal bus error interrupt enable */
+#define ETH_DMAIER_ETIE_Pos (10U)
+#define ETH_DMAIER_ETIE_Msk (0x1U << ETH_DMAIER_ETIE_Pos) /*!< 0x00000400 */
+#define ETH_DMAIER_ETIE ETH_DMAIER_ETIE_Msk /* Early transmit interrupt enable */
+#define ETH_DMAIER_RWTIE_Pos (9U)
+#define ETH_DMAIER_RWTIE_Msk (0x1U << ETH_DMAIER_RWTIE_Pos) /*!< 0x00000200 */
+#define ETH_DMAIER_RWTIE ETH_DMAIER_RWTIE_Msk /* Receive watchdog timeout interrupt enable */
+#define ETH_DMAIER_RPSIE_Pos (8U)
+#define ETH_DMAIER_RPSIE_Msk (0x1U << ETH_DMAIER_RPSIE_Pos) /*!< 0x00000100 */
+#define ETH_DMAIER_RPSIE ETH_DMAIER_RPSIE_Msk /* Receive process stopped interrupt enable */
+#define ETH_DMAIER_RBUIE_Pos (7U)
+#define ETH_DMAIER_RBUIE_Msk (0x1U << ETH_DMAIER_RBUIE_Pos) /*!< 0x00000080 */
+#define ETH_DMAIER_RBUIE ETH_DMAIER_RBUIE_Msk /* Receive buffer unavailable interrupt enable */
+#define ETH_DMAIER_RIE_Pos (6U)
+#define ETH_DMAIER_RIE_Msk (0x1U << ETH_DMAIER_RIE_Pos) /*!< 0x00000040 */
+#define ETH_DMAIER_RIE ETH_DMAIER_RIE_Msk /* Receive interrupt enable */
+#define ETH_DMAIER_TUIE_Pos (5U)
+#define ETH_DMAIER_TUIE_Msk (0x1U << ETH_DMAIER_TUIE_Pos) /*!< 0x00000020 */
+#define ETH_DMAIER_TUIE ETH_DMAIER_TUIE_Msk /* Transmit Underflow interrupt enable */
+#define ETH_DMAIER_ROIE_Pos (4U)
+#define ETH_DMAIER_ROIE_Msk (0x1U << ETH_DMAIER_ROIE_Pos) /*!< 0x00000010 */
+#define ETH_DMAIER_ROIE ETH_DMAIER_ROIE_Msk /* Receive Overflow interrupt enable */
+#define ETH_DMAIER_TJTIE_Pos (3U)
+#define ETH_DMAIER_TJTIE_Msk (0x1U << ETH_DMAIER_TJTIE_Pos) /*!< 0x00000008 */
+#define ETH_DMAIER_TJTIE ETH_DMAIER_TJTIE_Msk /* Transmit jabber timeout interrupt enable */
+#define ETH_DMAIER_TBUIE_Pos (2U)
+#define ETH_DMAIER_TBUIE_Msk (0x1U << ETH_DMAIER_TBUIE_Pos) /*!< 0x00000004 */
+#define ETH_DMAIER_TBUIE ETH_DMAIER_TBUIE_Msk /* Transmit buffer unavailable interrupt enable */
+#define ETH_DMAIER_TPSIE_Pos (1U)
+#define ETH_DMAIER_TPSIE_Msk (0x1U << ETH_DMAIER_TPSIE_Pos) /*!< 0x00000002 */
+#define ETH_DMAIER_TPSIE ETH_DMAIER_TPSIE_Msk /* Transmit process stopped interrupt enable */
+#define ETH_DMAIER_TIE_Pos (0U)
+#define ETH_DMAIER_TIE_Msk (0x1U << ETH_DMAIER_TIE_Pos) /*!< 0x00000001 */
+#define ETH_DMAIER_TIE ETH_DMAIER_TIE_Msk /* Transmit interrupt enable */
+
+/* Bit definition for Ethernet DMA Missed Frame and Buffer Overflow Counter Register */
+#define ETH_DMAMFBOCR_OFOC_Pos (28U)
+#define ETH_DMAMFBOCR_OFOC_Msk (0x1U << ETH_DMAMFBOCR_OFOC_Pos) /*!< 0x10000000 */
+#define ETH_DMAMFBOCR_OFOC ETH_DMAMFBOCR_OFOC_Msk /* Overflow bit for FIFO overflow counter */
+#define ETH_DMAMFBOCR_MFA_Pos (17U)
+#define ETH_DMAMFBOCR_MFA_Msk (0x7FFU << ETH_DMAMFBOCR_MFA_Pos) /*!< 0x0FFE0000 */
+#define ETH_DMAMFBOCR_MFA ETH_DMAMFBOCR_MFA_Msk /* Number of frames missed by the application */
+#define ETH_DMAMFBOCR_OMFC_Pos (16U)
+#define ETH_DMAMFBOCR_OMFC_Msk (0x1U << ETH_DMAMFBOCR_OMFC_Pos) /*!< 0x00010000 */
+#define ETH_DMAMFBOCR_OMFC ETH_DMAMFBOCR_OMFC_Msk /* Overflow bit for missed frame counter */
+#define ETH_DMAMFBOCR_MFC_Pos (0U)
+#define ETH_DMAMFBOCR_MFC_Msk (0xFFFFU << ETH_DMAMFBOCR_MFC_Pos) /*!< 0x0000FFFF */
+#define ETH_DMAMFBOCR_MFC ETH_DMAMFBOCR_MFC_Msk /* Number of frames missed by the controller */
+
+/* Bit definition for Ethernet DMA Current Host Transmit Descriptor Register */
+#define ETH_DMACHTDR_HTDAP_Pos (0U)
+#define ETH_DMACHTDR_HTDAP_Msk (0xFFFFFFFFU << ETH_DMACHTDR_HTDAP_Pos) /*!< 0xFFFFFFFF */
+#define ETH_DMACHTDR_HTDAP ETH_DMACHTDR_HTDAP_Msk /* Host transmit descriptor address pointer */
+
+/* Bit definition for Ethernet DMA Current Host Receive Descriptor Register */
+#define ETH_DMACHRDR_HRDAP_Pos (0U)
+#define ETH_DMACHRDR_HRDAP_Msk (0xFFFFFFFFU << ETH_DMACHRDR_HRDAP_Pos) /*!< 0xFFFFFFFF */
+#define ETH_DMACHRDR_HRDAP ETH_DMACHRDR_HRDAP_Msk /* Host receive descriptor address pointer */
+
+/* Bit definition for Ethernet DMA Current Host Transmit Buffer Address Register */
+#define ETH_DMACHTBAR_HTBAP_Pos (0U)
+#define ETH_DMACHTBAR_HTBAP_Msk (0xFFFFFFFFU << ETH_DMACHTBAR_HTBAP_Pos) /*!< 0xFFFFFFFF */
+#define ETH_DMACHTBAR_HTBAP ETH_DMACHTBAR_HTBAP_Msk /* Host transmit buffer address pointer */
+
+/* Bit definition for Ethernet DMA Current Host Receive Buffer Address Register */
+#define ETH_DMACHRBAR_HRBAP_Pos (0U)
+#define ETH_DMACHRBAR_HRBAP_Msk (0xFFFFFFFFU << ETH_DMACHRBAR_HRBAP_Pos) /*!< 0xFFFFFFFF */
+#define ETH_DMACHRBAR_HRBAP ETH_DMACHRBAR_HRBAP_Msk /* Host receive buffer address pointer */
+
+/******************************************************************************/
+/* */
+/* USB_OTG */
+/* */
+/******************************************************************************/
+
+/******************** Bit definition forUSB_OTG_GOTGCTL register ********************/
+#define USB_OTG_GOTGCTL_SRQSCS_Pos (0U)
+#define USB_OTG_GOTGCTL_SRQSCS_Msk (0x1U << USB_OTG_GOTGCTL_SRQSCS_Pos) /*!< 0x00000001 */
+#define USB_OTG_GOTGCTL_SRQSCS USB_OTG_GOTGCTL_SRQSCS_Msk /*!< Session request success */
+#define USB_OTG_GOTGCTL_SRQ_Pos (1U)
+#define USB_OTG_GOTGCTL_SRQ_Msk (0x1U << USB_OTG_GOTGCTL_SRQ_Pos) /*!< 0x00000002 */
+#define USB_OTG_GOTGCTL_SRQ USB_OTG_GOTGCTL_SRQ_Msk /*!< Session request */
+#define USB_OTG_GOTGCTL_HNGSCS_Pos (8U)
+#define USB_OTG_GOTGCTL_HNGSCS_Msk (0x1U << USB_OTG_GOTGCTL_HNGSCS_Pos) /*!< 0x00000100 */
+#define USB_OTG_GOTGCTL_HNGSCS USB_OTG_GOTGCTL_HNGSCS_Msk /*!< Host negotiation success */
+#define USB_OTG_GOTGCTL_HNPRQ_Pos (9U)
+#define USB_OTG_GOTGCTL_HNPRQ_Msk (0x1U << USB_OTG_GOTGCTL_HNPRQ_Pos) /*!< 0x00000200 */
+#define USB_OTG_GOTGCTL_HNPRQ USB_OTG_GOTGCTL_HNPRQ_Msk /*!< HNP request */
+#define USB_OTG_GOTGCTL_HSHNPEN_Pos (10U)
+#define USB_OTG_GOTGCTL_HSHNPEN_Msk (0x1U << USB_OTG_GOTGCTL_HSHNPEN_Pos) /*!< 0x00000400 */
+#define USB_OTG_GOTGCTL_HSHNPEN USB_OTG_GOTGCTL_HSHNPEN_Msk /*!< Host set HNP enable */
+#define USB_OTG_GOTGCTL_DHNPEN_Pos (11U)
+#define USB_OTG_GOTGCTL_DHNPEN_Msk (0x1U << USB_OTG_GOTGCTL_DHNPEN_Pos) /*!< 0x00000800 */
+#define USB_OTG_GOTGCTL_DHNPEN USB_OTG_GOTGCTL_DHNPEN_Msk /*!< Device HNP enabled */
+#define USB_OTG_GOTGCTL_CIDSTS_Pos (16U)
+#define USB_OTG_GOTGCTL_CIDSTS_Msk (0x1U << USB_OTG_GOTGCTL_CIDSTS_Pos) /*!< 0x00010000 */
+#define USB_OTG_GOTGCTL_CIDSTS USB_OTG_GOTGCTL_CIDSTS_Msk /*!< Connector ID status */
+#define USB_OTG_GOTGCTL_DBCT_Pos (17U)
+#define USB_OTG_GOTGCTL_DBCT_Msk (0x1U << USB_OTG_GOTGCTL_DBCT_Pos) /*!< 0x00020000 */
+#define USB_OTG_GOTGCTL_DBCT USB_OTG_GOTGCTL_DBCT_Msk /*!< Long/short debounce time */
+#define USB_OTG_GOTGCTL_ASVLD_Pos (18U)
+#define USB_OTG_GOTGCTL_ASVLD_Msk (0x1U << USB_OTG_GOTGCTL_ASVLD_Pos) /*!< 0x00040000 */
+#define USB_OTG_GOTGCTL_ASVLD USB_OTG_GOTGCTL_ASVLD_Msk /*!< A-session valid */
+#define USB_OTG_GOTGCTL_BSVLD_Pos (19U)
+#define USB_OTG_GOTGCTL_BSVLD_Msk (0x1U << USB_OTG_GOTGCTL_BSVLD_Pos) /*!< 0x00080000 */
+#define USB_OTG_GOTGCTL_BSVLD USB_OTG_GOTGCTL_BSVLD_Msk /*!< B-session valid */
+
+/******************** Bit definition forUSB_OTG_HCFG register ********************/
+
+#define USB_OTG_HCFG_FSLSPCS_Pos (0U)
+#define USB_OTG_HCFG_FSLSPCS_Msk (0x3U << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000003 */
+#define USB_OTG_HCFG_FSLSPCS USB_OTG_HCFG_FSLSPCS_Msk /*!< FS/LS PHY clock select */
+#define USB_OTG_HCFG_FSLSPCS_0 (0x1U << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000001 */
+#define USB_OTG_HCFG_FSLSPCS_1 (0x2U << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000002 */
+#define USB_OTG_HCFG_FSLSS_Pos (2U)
+#define USB_OTG_HCFG_FSLSS_Msk (0x1U << USB_OTG_HCFG_FSLSS_Pos) /*!< 0x00000004 */
+#define USB_OTG_HCFG_FSLSS USB_OTG_HCFG_FSLSS_Msk /*!< FS- and LS-only support */
+
+/******************** Bit definition forUSB_OTG_DCFG register ********************/
+
+#define USB_OTG_DCFG_DSPD_Pos (0U)
+#define USB_OTG_DCFG_DSPD_Msk (0x3U << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000003 */
+#define USB_OTG_DCFG_DSPD USB_OTG_DCFG_DSPD_Msk /*!< Device speed */
+#define USB_OTG_DCFG_DSPD_0 (0x1U << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000001 */
+#define USB_OTG_DCFG_DSPD_1 (0x2U << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000002 */
+#define USB_OTG_DCFG_NZLSOHSK_Pos (2U)
+#define USB_OTG_DCFG_NZLSOHSK_Msk (0x1U << USB_OTG_DCFG_NZLSOHSK_Pos) /*!< 0x00000004 */
+#define USB_OTG_DCFG_NZLSOHSK USB_OTG_DCFG_NZLSOHSK_Msk /*!< Nonzero-length status OUT handshake */
+
+#define USB_OTG_DCFG_DAD_Pos (4U)
+#define USB_OTG_DCFG_DAD_Msk (0x7FU << USB_OTG_DCFG_DAD_Pos) /*!< 0x000007F0 */
+#define USB_OTG_DCFG_DAD USB_OTG_DCFG_DAD_Msk /*!< Device address */
+#define USB_OTG_DCFG_DAD_0 (0x01U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000010 */
+#define USB_OTG_DCFG_DAD_1 (0x02U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000020 */
+#define USB_OTG_DCFG_DAD_2 (0x04U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000040 */
+#define USB_OTG_DCFG_DAD_3 (0x08U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000080 */
+#define USB_OTG_DCFG_DAD_4 (0x10U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000100 */
+#define USB_OTG_DCFG_DAD_5 (0x20U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000200 */
+#define USB_OTG_DCFG_DAD_6 (0x40U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000400 */
+
+#define USB_OTG_DCFG_PFIVL_Pos (11U)
+#define USB_OTG_DCFG_PFIVL_Msk (0x3U << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001800 */
+#define USB_OTG_DCFG_PFIVL USB_OTG_DCFG_PFIVL_Msk /*!< Periodic (micro)frame interval */
+#define USB_OTG_DCFG_PFIVL_0 (0x1U << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00000800 */
+#define USB_OTG_DCFG_PFIVL_1 (0x2U << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001000 */
+
+#define USB_OTG_DCFG_PERSCHIVL_Pos (24U)
+#define USB_OTG_DCFG_PERSCHIVL_Msk (0x3U << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x03000000 */
+#define USB_OTG_DCFG_PERSCHIVL USB_OTG_DCFG_PERSCHIVL_Msk /*!< Periodic scheduling interval */
+#define USB_OTG_DCFG_PERSCHIVL_0 (0x1U << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x01000000 */
+#define USB_OTG_DCFG_PERSCHIVL_1 (0x2U << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x02000000 */
+
+/******************** Bit definition forUSB_OTG_PCGCR register ********************/
+#define USB_OTG_PCGCR_STPPCLK_Pos (0U)
+#define USB_OTG_PCGCR_STPPCLK_Msk (0x1U << USB_OTG_PCGCR_STPPCLK_Pos) /*!< 0x00000001 */
+#define USB_OTG_PCGCR_STPPCLK USB_OTG_PCGCR_STPPCLK_Msk /*!< Stop PHY clock */
+#define USB_OTG_PCGCR_GATEHCLK_Pos (1U)
+#define USB_OTG_PCGCR_GATEHCLK_Msk (0x1U << USB_OTG_PCGCR_GATEHCLK_Pos) /*!< 0x00000002 */
+#define USB_OTG_PCGCR_GATEHCLK USB_OTG_PCGCR_GATEHCLK_Msk /*!< Gate HCLK */
+#define USB_OTG_PCGCR_PHYSUSP_Pos (4U)
+#define USB_OTG_PCGCR_PHYSUSP_Msk (0x1U << USB_OTG_PCGCR_PHYSUSP_Pos) /*!< 0x00000010 */
+#define USB_OTG_PCGCR_PHYSUSP USB_OTG_PCGCR_PHYSUSP_Msk /*!< PHY suspended */
+
+/******************** Bit definition forUSB_OTG_GOTGINT register ******************/
+#define USB_OTG_GOTGINT_SEDET_Pos (2U)
+#define USB_OTG_GOTGINT_SEDET_Msk (0x1U << USB_OTG_GOTGINT_SEDET_Pos) /*!< 0x00000004 */
+#define USB_OTG_GOTGINT_SEDET USB_OTG_GOTGINT_SEDET_Msk /*!< Session end detected */
+#define USB_OTG_GOTGINT_SRSSCHG_Pos (8U)
+#define USB_OTG_GOTGINT_SRSSCHG_Msk (0x1U << USB_OTG_GOTGINT_SRSSCHG_Pos) /*!< 0x00000100 */
+#define USB_OTG_GOTGINT_SRSSCHG USB_OTG_GOTGINT_SRSSCHG_Msk /*!< Session request success status change */
+#define USB_OTG_GOTGINT_HNSSCHG_Pos (9U)
+#define USB_OTG_GOTGINT_HNSSCHG_Msk (0x1U << USB_OTG_GOTGINT_HNSSCHG_Pos) /*!< 0x00000200 */
+#define USB_OTG_GOTGINT_HNSSCHG USB_OTG_GOTGINT_HNSSCHG_Msk /*!< Host negotiation success status change */
+#define USB_OTG_GOTGINT_HNGDET_Pos (17U)
+#define USB_OTG_GOTGINT_HNGDET_Msk (0x1U << USB_OTG_GOTGINT_HNGDET_Pos) /*!< 0x00020000 */
+#define USB_OTG_GOTGINT_HNGDET USB_OTG_GOTGINT_HNGDET_Msk /*!< Host negotiation detected */
+#define USB_OTG_GOTGINT_ADTOCHG_Pos (18U)
+#define USB_OTG_GOTGINT_ADTOCHG_Msk (0x1U << USB_OTG_GOTGINT_ADTOCHG_Pos) /*!< 0x00040000 */
+#define USB_OTG_GOTGINT_ADTOCHG USB_OTG_GOTGINT_ADTOCHG_Msk /*!< A-device timeout change */
+#define USB_OTG_GOTGINT_DBCDNE_Pos (19U)
+#define USB_OTG_GOTGINT_DBCDNE_Msk (0x1U << USB_OTG_GOTGINT_DBCDNE_Pos) /*!< 0x00080000 */
+#define USB_OTG_GOTGINT_DBCDNE USB_OTG_GOTGINT_DBCDNE_Msk /*!< Debounce done */
+
+/******************** Bit definition forUSB_OTG_DCTL register ********************/
+#define USB_OTG_DCTL_RWUSIG_Pos (0U)
+#define USB_OTG_DCTL_RWUSIG_Msk (0x1U << USB_OTG_DCTL_RWUSIG_Pos) /*!< 0x00000001 */
+#define USB_OTG_DCTL_RWUSIG USB_OTG_DCTL_RWUSIG_Msk /*!< Remote wakeup signaling */
+#define USB_OTG_DCTL_SDIS_Pos (1U)
+#define USB_OTG_DCTL_SDIS_Msk (0x1U << USB_OTG_DCTL_SDIS_Pos) /*!< 0x00000002 */
+#define USB_OTG_DCTL_SDIS USB_OTG_DCTL_SDIS_Msk /*!< Soft disconnect */
+#define USB_OTG_DCTL_GINSTS_Pos (2U)
+#define USB_OTG_DCTL_GINSTS_Msk (0x1U << USB_OTG_DCTL_GINSTS_Pos) /*!< 0x00000004 */
+#define USB_OTG_DCTL_GINSTS USB_OTG_DCTL_GINSTS_Msk /*!< Global IN NAK status */
+#define USB_OTG_DCTL_GONSTS_Pos (3U)
+#define USB_OTG_DCTL_GONSTS_Msk (0x1U << USB_OTG_DCTL_GONSTS_Pos) /*!< 0x00000008 */
+#define USB_OTG_DCTL_GONSTS USB_OTG_DCTL_GONSTS_Msk /*!< Global OUT NAK status */
+
+#define USB_OTG_DCTL_TCTL_Pos (4U)
+#define USB_OTG_DCTL_TCTL_Msk (0x7U << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000070 */
+#define USB_OTG_DCTL_TCTL USB_OTG_DCTL_TCTL_Msk /*!< Test control */
+#define USB_OTG_DCTL_TCTL_0 (0x1U << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000010 */
+#define USB_OTG_DCTL_TCTL_1 (0x2U << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000020 */
+#define USB_OTG_DCTL_TCTL_2 (0x4U << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000040 */
+#define USB_OTG_DCTL_SGINAK_Pos (7U)
+#define USB_OTG_DCTL_SGINAK_Msk (0x1U << USB_OTG_DCTL_SGINAK_Pos) /*!< 0x00000080 */
+#define USB_OTG_DCTL_SGINAK USB_OTG_DCTL_SGINAK_Msk /*!< Set global IN NAK */
+#define USB_OTG_DCTL_CGINAK_Pos (8U)
+#define USB_OTG_DCTL_CGINAK_Msk (0x1U << USB_OTG_DCTL_CGINAK_Pos) /*!< 0x00000100 */
+#define USB_OTG_DCTL_CGINAK USB_OTG_DCTL_CGINAK_Msk /*!< Clear global IN NAK */
+#define USB_OTG_DCTL_SGONAK_Pos (9U)
+#define USB_OTG_DCTL_SGONAK_Msk (0x1U << USB_OTG_DCTL_SGONAK_Pos) /*!< 0x00000200 */
+#define USB_OTG_DCTL_SGONAK USB_OTG_DCTL_SGONAK_Msk /*!< Set global OUT NAK */
+#define USB_OTG_DCTL_CGONAK_Pos (10U)
+#define USB_OTG_DCTL_CGONAK_Msk (0x1U << USB_OTG_DCTL_CGONAK_Pos) /*!< 0x00000400 */
+#define USB_OTG_DCTL_CGONAK USB_OTG_DCTL_CGONAK_Msk /*!< Clear global OUT NAK */
+#define USB_OTG_DCTL_POPRGDNE_Pos (11U)
+#define USB_OTG_DCTL_POPRGDNE_Msk (0x1U << USB_OTG_DCTL_POPRGDNE_Pos) /*!< 0x00000800 */
+#define USB_OTG_DCTL_POPRGDNE USB_OTG_DCTL_POPRGDNE_Msk /*!< Power-on programming done */
+
+/******************** Bit definition forUSB_OTG_HFIR register ********************/
+#define USB_OTG_HFIR_FRIVL_Pos (0U)
+#define USB_OTG_HFIR_FRIVL_Msk (0xFFFFU << USB_OTG_HFIR_FRIVL_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_HFIR_FRIVL USB_OTG_HFIR_FRIVL_Msk /*!< Frame interval */
+
+/******************** Bit definition forUSB_OTG_HFNUM register ********************/
+#define USB_OTG_HFNUM_FRNUM_Pos (0U)
+#define USB_OTG_HFNUM_FRNUM_Msk (0xFFFFU << USB_OTG_HFNUM_FRNUM_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_HFNUM_FRNUM USB_OTG_HFNUM_FRNUM_Msk /*!< Frame number */
+#define USB_OTG_HFNUM_FTREM_Pos (16U)
+#define USB_OTG_HFNUM_FTREM_Msk (0xFFFFU << USB_OTG_HFNUM_FTREM_Pos) /*!< 0xFFFF0000 */
+#define USB_OTG_HFNUM_FTREM USB_OTG_HFNUM_FTREM_Msk /*!< Frame time remaining */
+
+/******************** Bit definition forUSB_OTG_DSTS register ********************/
+#define USB_OTG_DSTS_SUSPSTS_Pos (0U)
+#define USB_OTG_DSTS_SUSPSTS_Msk (0x1U << USB_OTG_DSTS_SUSPSTS_Pos) /*!< 0x00000001 */
+#define USB_OTG_DSTS_SUSPSTS USB_OTG_DSTS_SUSPSTS_Msk /*!< Suspend status */
+
+#define USB_OTG_DSTS_ENUMSPD_Pos (1U)
+#define USB_OTG_DSTS_ENUMSPD_Msk (0x3U << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000006 */
+#define USB_OTG_DSTS_ENUMSPD USB_OTG_DSTS_ENUMSPD_Msk /*!< Enumerated speed */
+#define USB_OTG_DSTS_ENUMSPD_0 (0x1U << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000002 */
+#define USB_OTG_DSTS_ENUMSPD_1 (0x2U << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000004 */
+#define USB_OTG_DSTS_EERR_Pos (3U)
+#define USB_OTG_DSTS_EERR_Msk (0x1U << USB_OTG_DSTS_EERR_Pos) /*!< 0x00000008 */
+#define USB_OTG_DSTS_EERR USB_OTG_DSTS_EERR_Msk /*!< Erratic error */
+#define USB_OTG_DSTS_FNSOF_Pos (8U)
+#define USB_OTG_DSTS_FNSOF_Msk (0x3FFFU << USB_OTG_DSTS_FNSOF_Pos) /*!< 0x003FFF00 */
+#define USB_OTG_DSTS_FNSOF USB_OTG_DSTS_FNSOF_Msk /*!< Frame number of the received SOF */
+
+/******************** Bit definition forUSB_OTG_GAHBCFG register *****************/
+#define USB_OTG_GAHBCFG_GINT_Pos (0U)
+#define USB_OTG_GAHBCFG_GINT_Msk (0x1U << USB_OTG_GAHBCFG_GINT_Pos) /*!< 0x00000001 */
+#define USB_OTG_GAHBCFG_GINT USB_OTG_GAHBCFG_GINT_Msk /*!< Global interrupt mask */
+
+#define USB_OTG_GAHBCFG_HBSTLEN_Pos (1U)
+#define USB_OTG_GAHBCFG_HBSTLEN_Msk (0xFU << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x0000001E */
+#define USB_OTG_GAHBCFG_HBSTLEN USB_OTG_GAHBCFG_HBSTLEN_Msk /*!< Burst length/type */
+#define USB_OTG_GAHBCFG_HBSTLEN_0 (0x1U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x00000002 */
+#define USB_OTG_GAHBCFG_HBSTLEN_1 (0x2U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x00000004 */
+#define USB_OTG_GAHBCFG_HBSTLEN_2 (0x4U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x00000008 */
+#define USB_OTG_GAHBCFG_HBSTLEN_3 (0x8U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x00000010 */
+#define USB_OTG_GAHBCFG_DMAEN_Pos (5U)
+#define USB_OTG_GAHBCFG_DMAEN_Msk (0x1U << USB_OTG_GAHBCFG_DMAEN_Pos) /*!< 0x00000020 */
+#define USB_OTG_GAHBCFG_DMAEN USB_OTG_GAHBCFG_DMAEN_Msk /*!< DMA enable */
+#define USB_OTG_GAHBCFG_TXFELVL_Pos (7U)
+#define USB_OTG_GAHBCFG_TXFELVL_Msk (0x1U << USB_OTG_GAHBCFG_TXFELVL_Pos) /*!< 0x00000080 */
+#define USB_OTG_GAHBCFG_TXFELVL USB_OTG_GAHBCFG_TXFELVL_Msk /*!< TxFIFO empty level */
+#define USB_OTG_GAHBCFG_PTXFELVL_Pos (8U)
+#define USB_OTG_GAHBCFG_PTXFELVL_Msk (0x1U << USB_OTG_GAHBCFG_PTXFELVL_Pos) /*!< 0x00000100 */
+#define USB_OTG_GAHBCFG_PTXFELVL USB_OTG_GAHBCFG_PTXFELVL_Msk /*!< Periodic TxFIFO empty level */
+
+/******************** Bit definition forUSB_OTG_GUSBCFG register *****************/
+
+#define USB_OTG_GUSBCFG_TOCAL_Pos (0U)
+#define USB_OTG_GUSBCFG_TOCAL_Msk (0x7U << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000007 */
+#define USB_OTG_GUSBCFG_TOCAL USB_OTG_GUSBCFG_TOCAL_Msk /*!< FS timeout calibration */
+#define USB_OTG_GUSBCFG_TOCAL_0 (0x1U << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000001 */
+#define USB_OTG_GUSBCFG_TOCAL_1 (0x2U << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000002 */
+#define USB_OTG_GUSBCFG_TOCAL_2 (0x4U << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000004 */
+#define USB_OTG_GUSBCFG_PHYSEL_Pos (6U)
+#define USB_OTG_GUSBCFG_PHYSEL_Msk (0x1U << USB_OTG_GUSBCFG_PHYSEL_Pos) /*!< 0x00000040 */
+#define USB_OTG_GUSBCFG_PHYSEL USB_OTG_GUSBCFG_PHYSEL_Msk /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */
+#define USB_OTG_GUSBCFG_SRPCAP_Pos (8U)
+#define USB_OTG_GUSBCFG_SRPCAP_Msk (0x1U << USB_OTG_GUSBCFG_SRPCAP_Pos) /*!< 0x00000100 */
+#define USB_OTG_GUSBCFG_SRPCAP USB_OTG_GUSBCFG_SRPCAP_Msk /*!< SRP-capable */
+#define USB_OTG_GUSBCFG_HNPCAP_Pos (9U)
+#define USB_OTG_GUSBCFG_HNPCAP_Msk (0x1U << USB_OTG_GUSBCFG_HNPCAP_Pos) /*!< 0x00000200 */
+#define USB_OTG_GUSBCFG_HNPCAP USB_OTG_GUSBCFG_HNPCAP_Msk /*!< HNP-capable */
+
+#define USB_OTG_GUSBCFG_TRDT_Pos (10U)
+#define USB_OTG_GUSBCFG_TRDT_Msk (0xFU << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00003C00 */
+#define USB_OTG_GUSBCFG_TRDT USB_OTG_GUSBCFG_TRDT_Msk /*!< USB turnaround time */
+#define USB_OTG_GUSBCFG_TRDT_0 (0x1U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000400 */
+#define USB_OTG_GUSBCFG_TRDT_1 (0x2U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000800 */
+#define USB_OTG_GUSBCFG_TRDT_2 (0x4U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00001000 */
+#define USB_OTG_GUSBCFG_TRDT_3 (0x8U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00002000 */
+#define USB_OTG_GUSBCFG_PHYLPCS_Pos (15U)
+#define USB_OTG_GUSBCFG_PHYLPCS_Msk (0x1U << USB_OTG_GUSBCFG_PHYLPCS_Pos) /*!< 0x00008000 */
+#define USB_OTG_GUSBCFG_PHYLPCS USB_OTG_GUSBCFG_PHYLPCS_Msk /*!< PHY Low-power clock select */
+#define USB_OTG_GUSBCFG_ULPIFSLS_Pos (17U)
+#define USB_OTG_GUSBCFG_ULPIFSLS_Msk (0x1U << USB_OTG_GUSBCFG_ULPIFSLS_Pos) /*!< 0x00020000 */
+#define USB_OTG_GUSBCFG_ULPIFSLS USB_OTG_GUSBCFG_ULPIFSLS_Msk /*!< ULPI FS/LS select */
+#define USB_OTG_GUSBCFG_ULPIAR_Pos (18U)
+#define USB_OTG_GUSBCFG_ULPIAR_Msk (0x1U << USB_OTG_GUSBCFG_ULPIAR_Pos) /*!< 0x00040000 */
+#define USB_OTG_GUSBCFG_ULPIAR USB_OTG_GUSBCFG_ULPIAR_Msk /*!< ULPI Auto-resume */
+#define USB_OTG_GUSBCFG_ULPICSM_Pos (19U)
+#define USB_OTG_GUSBCFG_ULPICSM_Msk (0x1U << USB_OTG_GUSBCFG_ULPICSM_Pos) /*!< 0x00080000 */
+#define USB_OTG_GUSBCFG_ULPICSM USB_OTG_GUSBCFG_ULPICSM_Msk /*!< ULPI Clock SuspendM */
+#define USB_OTG_GUSBCFG_ULPIEVBUSD_Pos (20U)
+#define USB_OTG_GUSBCFG_ULPIEVBUSD_Msk (0x1U << USB_OTG_GUSBCFG_ULPIEVBUSD_Pos) /*!< 0x00100000 */
+#define USB_OTG_GUSBCFG_ULPIEVBUSD USB_OTG_GUSBCFG_ULPIEVBUSD_Msk /*!< ULPI External VBUS Drive */
+#define USB_OTG_GUSBCFG_ULPIEVBUSI_Pos (21U)
+#define USB_OTG_GUSBCFG_ULPIEVBUSI_Msk (0x1U << USB_OTG_GUSBCFG_ULPIEVBUSI_Pos) /*!< 0x00200000 */
+#define USB_OTG_GUSBCFG_ULPIEVBUSI USB_OTG_GUSBCFG_ULPIEVBUSI_Msk /*!< ULPI external VBUS indicator */
+#define USB_OTG_GUSBCFG_TSDPS_Pos (22U)
+#define USB_OTG_GUSBCFG_TSDPS_Msk (0x1U << USB_OTG_GUSBCFG_TSDPS_Pos) /*!< 0x00400000 */
+#define USB_OTG_GUSBCFG_TSDPS USB_OTG_GUSBCFG_TSDPS_Msk /*!< TermSel DLine pulsing selection */
+#define USB_OTG_GUSBCFG_PCCI_Pos (23U)
+#define USB_OTG_GUSBCFG_PCCI_Msk (0x1U << USB_OTG_GUSBCFG_PCCI_Pos) /*!< 0x00800000 */
+#define USB_OTG_GUSBCFG_PCCI USB_OTG_GUSBCFG_PCCI_Msk /*!< Indicator complement */
+#define USB_OTG_GUSBCFG_PTCI_Pos (24U)
+#define USB_OTG_GUSBCFG_PTCI_Msk (0x1U << USB_OTG_GUSBCFG_PTCI_Pos) /*!< 0x01000000 */
+#define USB_OTG_GUSBCFG_PTCI USB_OTG_GUSBCFG_PTCI_Msk /*!< Indicator pass through */
+#define USB_OTG_GUSBCFG_ULPIIPD_Pos (25U)
+#define USB_OTG_GUSBCFG_ULPIIPD_Msk (0x1U << USB_OTG_GUSBCFG_ULPIIPD_Pos) /*!< 0x02000000 */
+#define USB_OTG_GUSBCFG_ULPIIPD USB_OTG_GUSBCFG_ULPIIPD_Msk /*!< ULPI interface protect disable */
+#define USB_OTG_GUSBCFG_FHMOD_Pos (29U)
+#define USB_OTG_GUSBCFG_FHMOD_Msk (0x1U << USB_OTG_GUSBCFG_FHMOD_Pos) /*!< 0x20000000 */
+#define USB_OTG_GUSBCFG_FHMOD USB_OTG_GUSBCFG_FHMOD_Msk /*!< Forced host mode */
+#define USB_OTG_GUSBCFG_FDMOD_Pos (30U)
+#define USB_OTG_GUSBCFG_FDMOD_Msk (0x1U << USB_OTG_GUSBCFG_FDMOD_Pos) /*!< 0x40000000 */
+#define USB_OTG_GUSBCFG_FDMOD USB_OTG_GUSBCFG_FDMOD_Msk /*!< Forced peripheral mode */
+#define USB_OTG_GUSBCFG_CTXPKT_Pos (31U)
+#define USB_OTG_GUSBCFG_CTXPKT_Msk (0x1U << USB_OTG_GUSBCFG_CTXPKT_Pos) /*!< 0x80000000 */
+#define USB_OTG_GUSBCFG_CTXPKT USB_OTG_GUSBCFG_CTXPKT_Msk /*!< Corrupt Tx packet */
+
+/******************** Bit definition forUSB_OTG_GRSTCTL register *****************/
+#define USB_OTG_GRSTCTL_CSRST_Pos (0U)
+#define USB_OTG_GRSTCTL_CSRST_Msk (0x1U << USB_OTG_GRSTCTL_CSRST_Pos) /*!< 0x00000001 */
+#define USB_OTG_GRSTCTL_CSRST USB_OTG_GRSTCTL_CSRST_Msk /*!< Core soft reset */
+#define USB_OTG_GRSTCTL_HSRST_Pos (1U)
+#define USB_OTG_GRSTCTL_HSRST_Msk (0x1U << USB_OTG_GRSTCTL_HSRST_Pos) /*!< 0x00000002 */
+#define USB_OTG_GRSTCTL_HSRST USB_OTG_GRSTCTL_HSRST_Msk /*!< HCLK soft reset */
+#define USB_OTG_GRSTCTL_FCRST_Pos (2U)
+#define USB_OTG_GRSTCTL_FCRST_Msk (0x1U << USB_OTG_GRSTCTL_FCRST_Pos) /*!< 0x00000004 */
+#define USB_OTG_GRSTCTL_FCRST USB_OTG_GRSTCTL_FCRST_Msk /*!< Host frame counter reset */
+#define USB_OTG_GRSTCTL_RXFFLSH_Pos (4U)
+#define USB_OTG_GRSTCTL_RXFFLSH_Msk (0x1U << USB_OTG_GRSTCTL_RXFFLSH_Pos) /*!< 0x00000010 */
+#define USB_OTG_GRSTCTL_RXFFLSH USB_OTG_GRSTCTL_RXFFLSH_Msk /*!< RxFIFO flush */
+#define USB_OTG_GRSTCTL_TXFFLSH_Pos (5U)
+#define USB_OTG_GRSTCTL_TXFFLSH_Msk (0x1U << USB_OTG_GRSTCTL_TXFFLSH_Pos) /*!< 0x00000020 */
+#define USB_OTG_GRSTCTL_TXFFLSH USB_OTG_GRSTCTL_TXFFLSH_Msk /*!< TxFIFO flush */
+
+#define USB_OTG_GRSTCTL_TXFNUM_Pos (6U)
+#define USB_OTG_GRSTCTL_TXFNUM_Msk (0x1FU << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x000007C0 */
+#define USB_OTG_GRSTCTL_TXFNUM USB_OTG_GRSTCTL_TXFNUM_Msk /*!< TxFIFO number */
+#define USB_OTG_GRSTCTL_TXFNUM_0 (0x01U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000040 */
+#define USB_OTG_GRSTCTL_TXFNUM_1 (0x02U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000080 */
+#define USB_OTG_GRSTCTL_TXFNUM_2 (0x04U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000100 */
+#define USB_OTG_GRSTCTL_TXFNUM_3 (0x08U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000200 */
+#define USB_OTG_GRSTCTL_TXFNUM_4 (0x10U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000400 */
+#define USB_OTG_GRSTCTL_DMAREQ_Pos (30U)
+#define USB_OTG_GRSTCTL_DMAREQ_Msk (0x1U << USB_OTG_GRSTCTL_DMAREQ_Pos) /*!< 0x40000000 */
+#define USB_OTG_GRSTCTL_DMAREQ USB_OTG_GRSTCTL_DMAREQ_Msk /*!< DMA request signal */
+#define USB_OTG_GRSTCTL_AHBIDL_Pos (31U)
+#define USB_OTG_GRSTCTL_AHBIDL_Msk (0x1U << USB_OTG_GRSTCTL_AHBIDL_Pos) /*!< 0x80000000 */
+#define USB_OTG_GRSTCTL_AHBIDL USB_OTG_GRSTCTL_AHBIDL_Msk /*!< AHB master idle */
+
+/******************** Bit definition forUSB_OTG_DIEPMSK register *****************/
+#define USB_OTG_DIEPMSK_XFRCM_Pos (0U)
+#define USB_OTG_DIEPMSK_XFRCM_Msk (0x1U << USB_OTG_DIEPMSK_XFRCM_Pos) /*!< 0x00000001 */
+#define USB_OTG_DIEPMSK_XFRCM USB_OTG_DIEPMSK_XFRCM_Msk /*!< Transfer completed interrupt mask */
+#define USB_OTG_DIEPMSK_EPDM_Pos (1U)
+#define USB_OTG_DIEPMSK_EPDM_Msk (0x1U << USB_OTG_DIEPMSK_EPDM_Pos) /*!< 0x00000002 */
+#define USB_OTG_DIEPMSK_EPDM USB_OTG_DIEPMSK_EPDM_Msk /*!< Endpoint disabled interrupt mask */
+#define USB_OTG_DIEPMSK_TOM_Pos (3U)
+#define USB_OTG_DIEPMSK_TOM_Msk (0x1U << USB_OTG_DIEPMSK_TOM_Pos) /*!< 0x00000008 */
+#define USB_OTG_DIEPMSK_TOM USB_OTG_DIEPMSK_TOM_Msk /*!< Timeout condition mask (nonisochronous endpoints) */
+#define USB_OTG_DIEPMSK_ITTXFEMSK_Pos (4U)
+#define USB_OTG_DIEPMSK_ITTXFEMSK_Msk (0x1U << USB_OTG_DIEPMSK_ITTXFEMSK_Pos) /*!< 0x00000010 */
+#define USB_OTG_DIEPMSK_ITTXFEMSK USB_OTG_DIEPMSK_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */
+#define USB_OTG_DIEPMSK_INEPNMM_Pos (5U)
+#define USB_OTG_DIEPMSK_INEPNMM_Msk (0x1U << USB_OTG_DIEPMSK_INEPNMM_Pos) /*!< 0x00000020 */
+#define USB_OTG_DIEPMSK_INEPNMM USB_OTG_DIEPMSK_INEPNMM_Msk /*!< IN token received with EP mismatch mask */
+#define USB_OTG_DIEPMSK_INEPNEM_Pos (6U)
+#define USB_OTG_DIEPMSK_INEPNEM_Msk (0x1U << USB_OTG_DIEPMSK_INEPNEM_Pos) /*!< 0x00000040 */
+#define USB_OTG_DIEPMSK_INEPNEM USB_OTG_DIEPMSK_INEPNEM_Msk /*!< IN endpoint NAK effective mask */
+#define USB_OTG_DIEPMSK_TXFURM_Pos (8U)
+#define USB_OTG_DIEPMSK_TXFURM_Msk (0x1U << USB_OTG_DIEPMSK_TXFURM_Pos) /*!< 0x00000100 */
+#define USB_OTG_DIEPMSK_TXFURM USB_OTG_DIEPMSK_TXFURM_Msk /*!< FIFO underrun mask */
+#define USB_OTG_DIEPMSK_BIM_Pos (9U)
+#define USB_OTG_DIEPMSK_BIM_Msk (0x1U << USB_OTG_DIEPMSK_BIM_Pos) /*!< 0x00000200 */
+#define USB_OTG_DIEPMSK_BIM USB_OTG_DIEPMSK_BIM_Msk /*!< BNA interrupt mask */
+
+/******************** Bit definition forUSB_OTG_HPTXSTS register *****************/
+#define USB_OTG_HPTXSTS_PTXFSAVL_Pos (0U)
+#define USB_OTG_HPTXSTS_PTXFSAVL_Msk (0xFFFFU << USB_OTG_HPTXSTS_PTXFSAVL_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_HPTXSTS_PTXFSAVL USB_OTG_HPTXSTS_PTXFSAVL_Msk /*!< Periodic transmit data FIFO space available */
+
+#define USB_OTG_HPTXSTS_PTXQSAV_Pos (16U)
+#define USB_OTG_HPTXSTS_PTXQSAV_Msk (0xFFU << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00FF0000 */
+#define USB_OTG_HPTXSTS_PTXQSAV USB_OTG_HPTXSTS_PTXQSAV_Msk /*!< Periodic transmit request queue space available */
+#define USB_OTG_HPTXSTS_PTXQSAV_0 (0x01U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00010000 */
+#define USB_OTG_HPTXSTS_PTXQSAV_1 (0x02U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00020000 */
+#define USB_OTG_HPTXSTS_PTXQSAV_2 (0x04U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00040000 */
+#define USB_OTG_HPTXSTS_PTXQSAV_3 (0x08U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00080000 */
+#define USB_OTG_HPTXSTS_PTXQSAV_4 (0x10U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00100000 */
+#define USB_OTG_HPTXSTS_PTXQSAV_5 (0x20U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00200000 */
+#define USB_OTG_HPTXSTS_PTXQSAV_6 (0x40U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00400000 */
+#define USB_OTG_HPTXSTS_PTXQSAV_7 (0x80U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00800000 */
+
+#define USB_OTG_HPTXSTS_PTXQTOP_Pos (24U)
+#define USB_OTG_HPTXSTS_PTXQTOP_Msk (0xFFU << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0xFF000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP USB_OTG_HPTXSTS_PTXQTOP_Msk /*!< Top of the periodic transmit request queue */
+#define USB_OTG_HPTXSTS_PTXQTOP_0 (0x01U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x01000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP_1 (0x02U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x02000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP_2 (0x04U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x04000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP_3 (0x08U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x08000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP_4 (0x10U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x10000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP_5 (0x20U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x20000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP_6 (0x40U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x40000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP_7 (0x80U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x80000000 */
+
+/******************** Bit definition forUSB_OTG_HAINT register *******************/
+#define USB_OTG_HAINT_HAINT_Pos (0U)
+#define USB_OTG_HAINT_HAINT_Msk (0xFFFFU << USB_OTG_HAINT_HAINT_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_HAINT_HAINT USB_OTG_HAINT_HAINT_Msk /*!< Channel interrupts */
+
+/******************** Bit definition forUSB_OTG_DOEPMSK register *****************/
+#define USB_OTG_DOEPMSK_XFRCM_Pos (0U)
+#define USB_OTG_DOEPMSK_XFRCM_Msk (0x1U << USB_OTG_DOEPMSK_XFRCM_Pos) /*!< 0x00000001 */
+#define USB_OTG_DOEPMSK_XFRCM USB_OTG_DOEPMSK_XFRCM_Msk /*!< Transfer completed interrupt mask */
+#define USB_OTG_DOEPMSK_EPDM_Pos (1U)
+#define USB_OTG_DOEPMSK_EPDM_Msk (0x1U << USB_OTG_DOEPMSK_EPDM_Pos) /*!< 0x00000002 */
+#define USB_OTG_DOEPMSK_EPDM USB_OTG_DOEPMSK_EPDM_Msk /*!< Endpoint disabled interrupt mask */
+#define USB_OTG_DOEPMSK_STUPM_Pos (3U)
+#define USB_OTG_DOEPMSK_STUPM_Msk (0x1U << USB_OTG_DOEPMSK_STUPM_Pos) /*!< 0x00000008 */
+#define USB_OTG_DOEPMSK_STUPM USB_OTG_DOEPMSK_STUPM_Msk /*!< SETUP phase done mask */
+#define USB_OTG_DOEPMSK_OTEPDM_Pos (4U)
+#define USB_OTG_DOEPMSK_OTEPDM_Msk (0x1U << USB_OTG_DOEPMSK_OTEPDM_Pos) /*!< 0x00000010 */
+#define USB_OTG_DOEPMSK_OTEPDM USB_OTG_DOEPMSK_OTEPDM_Msk /*!< OUT token received when endpoint disabled mask */
+#define USB_OTG_DOEPMSK_B2BSTUP_Pos (6U)
+#define USB_OTG_DOEPMSK_B2BSTUP_Msk (0x1U << USB_OTG_DOEPMSK_B2BSTUP_Pos) /*!< 0x00000040 */
+#define USB_OTG_DOEPMSK_B2BSTUP USB_OTG_DOEPMSK_B2BSTUP_Msk /*!< Back-to-back SETUP packets received mask */
+#define USB_OTG_DOEPMSK_OPEM_Pos (8U)
+#define USB_OTG_DOEPMSK_OPEM_Msk (0x1U << USB_OTG_DOEPMSK_OPEM_Pos) /*!< 0x00000100 */
+#define USB_OTG_DOEPMSK_OPEM USB_OTG_DOEPMSK_OPEM_Msk /*!< OUT packet error mask */
+#define USB_OTG_DOEPMSK_BOIM_Pos (9U)
+#define USB_OTG_DOEPMSK_BOIM_Msk (0x1U << USB_OTG_DOEPMSK_BOIM_Pos) /*!< 0x00000200 */
+#define USB_OTG_DOEPMSK_BOIM USB_OTG_DOEPMSK_BOIM_Msk /*!< BNA interrupt mask */
+
+/******************** Bit definition forUSB_OTG_GINTSTS register *****************/
+#define USB_OTG_GINTSTS_CMOD_Pos (0U)
+#define USB_OTG_GINTSTS_CMOD_Msk (0x1U << USB_OTG_GINTSTS_CMOD_Pos) /*!< 0x00000001 */
+#define USB_OTG_GINTSTS_CMOD USB_OTG_GINTSTS_CMOD_Msk /*!< Current mode of operation */
+#define USB_OTG_GINTSTS_MMIS_Pos (1U)
+#define USB_OTG_GINTSTS_MMIS_Msk (0x1U << USB_OTG_GINTSTS_MMIS_Pos) /*!< 0x00000002 */
+#define USB_OTG_GINTSTS_MMIS USB_OTG_GINTSTS_MMIS_Msk /*!< Mode mismatch interrupt */
+#define USB_OTG_GINTSTS_OTGINT_Pos (2U)
+#define USB_OTG_GINTSTS_OTGINT_Msk (0x1U << USB_OTG_GINTSTS_OTGINT_Pos) /*!< 0x00000004 */
+#define USB_OTG_GINTSTS_OTGINT USB_OTG_GINTSTS_OTGINT_Msk /*!< OTG interrupt */
+#define USB_OTG_GINTSTS_SOF_Pos (3U)
+#define USB_OTG_GINTSTS_SOF_Msk (0x1U << USB_OTG_GINTSTS_SOF_Pos) /*!< 0x00000008 */
+#define USB_OTG_GINTSTS_SOF USB_OTG_GINTSTS_SOF_Msk /*!< Start of frame */
+#define USB_OTG_GINTSTS_RXFLVL_Pos (4U)
+#define USB_OTG_GINTSTS_RXFLVL_Msk (0x1U << USB_OTG_GINTSTS_RXFLVL_Pos) /*!< 0x00000010 */
+#define USB_OTG_GINTSTS_RXFLVL USB_OTG_GINTSTS_RXFLVL_Msk /*!< RxFIFO nonempty */
+#define USB_OTG_GINTSTS_NPTXFE_Pos (5U)
+#define USB_OTG_GINTSTS_NPTXFE_Msk (0x1U << USB_OTG_GINTSTS_NPTXFE_Pos) /*!< 0x00000020 */
+#define USB_OTG_GINTSTS_NPTXFE USB_OTG_GINTSTS_NPTXFE_Msk /*!< Nonperiodic TxFIFO empty */
+#define USB_OTG_GINTSTS_GINAKEFF_Pos (6U)
+#define USB_OTG_GINTSTS_GINAKEFF_Msk (0x1U << USB_OTG_GINTSTS_GINAKEFF_Pos) /*!< 0x00000040 */
+#define USB_OTG_GINTSTS_GINAKEFF USB_OTG_GINTSTS_GINAKEFF_Msk /*!< Global IN nonperiodic NAK effective */
+#define USB_OTG_GINTSTS_BOUTNAKEFF_Pos (7U)
+#define USB_OTG_GINTSTS_BOUTNAKEFF_Msk (0x1U << USB_OTG_GINTSTS_BOUTNAKEFF_Pos) /*!< 0x00000080 */
+#define USB_OTG_GINTSTS_BOUTNAKEFF USB_OTG_GINTSTS_BOUTNAKEFF_Msk /*!< Global OUT NAK effective */
+#define USB_OTG_GINTSTS_ESUSP_Pos (10U)
+#define USB_OTG_GINTSTS_ESUSP_Msk (0x1U << USB_OTG_GINTSTS_ESUSP_Pos) /*!< 0x00000400 */
+#define USB_OTG_GINTSTS_ESUSP USB_OTG_GINTSTS_ESUSP_Msk /*!< Early suspend */
+#define USB_OTG_GINTSTS_USBSUSP_Pos (11U)
+#define USB_OTG_GINTSTS_USBSUSP_Msk (0x1U << USB_OTG_GINTSTS_USBSUSP_Pos) /*!< 0x00000800 */
+#define USB_OTG_GINTSTS_USBSUSP USB_OTG_GINTSTS_USBSUSP_Msk /*!< USB suspend */
+#define USB_OTG_GINTSTS_USBRST_Pos (12U)
+#define USB_OTG_GINTSTS_USBRST_Msk (0x1U << USB_OTG_GINTSTS_USBRST_Pos) /*!< 0x00001000 */
+#define USB_OTG_GINTSTS_USBRST USB_OTG_GINTSTS_USBRST_Msk /*!< USB reset */
+#define USB_OTG_GINTSTS_ENUMDNE_Pos (13U)
+#define USB_OTG_GINTSTS_ENUMDNE_Msk (0x1U << USB_OTG_GINTSTS_ENUMDNE_Pos) /*!< 0x00002000 */
+#define USB_OTG_GINTSTS_ENUMDNE USB_OTG_GINTSTS_ENUMDNE_Msk /*!< Enumeration done */
+#define USB_OTG_GINTSTS_ISOODRP_Pos (14U)
+#define USB_OTG_GINTSTS_ISOODRP_Msk (0x1U << USB_OTG_GINTSTS_ISOODRP_Pos) /*!< 0x00004000 */
+#define USB_OTG_GINTSTS_ISOODRP USB_OTG_GINTSTS_ISOODRP_Msk /*!< Isochronous OUT packet dropped interrupt */
+#define USB_OTG_GINTSTS_EOPF_Pos (15U)
+#define USB_OTG_GINTSTS_EOPF_Msk (0x1U << USB_OTG_GINTSTS_EOPF_Pos) /*!< 0x00008000 */
+#define USB_OTG_GINTSTS_EOPF USB_OTG_GINTSTS_EOPF_Msk /*!< End of periodic frame interrupt */
+#define USB_OTG_GINTSTS_IEPINT_Pos (18U)
+#define USB_OTG_GINTSTS_IEPINT_Msk (0x1U << USB_OTG_GINTSTS_IEPINT_Pos) /*!< 0x00040000 */
+#define USB_OTG_GINTSTS_IEPINT USB_OTG_GINTSTS_IEPINT_Msk /*!< IN endpoint interrupt */
+#define USB_OTG_GINTSTS_OEPINT_Pos (19U)
+#define USB_OTG_GINTSTS_OEPINT_Msk (0x1U << USB_OTG_GINTSTS_OEPINT_Pos) /*!< 0x00080000 */
+#define USB_OTG_GINTSTS_OEPINT USB_OTG_GINTSTS_OEPINT_Msk /*!< OUT endpoint interrupt */
+#define USB_OTG_GINTSTS_IISOIXFR_Pos (20U)
+#define USB_OTG_GINTSTS_IISOIXFR_Msk (0x1U << USB_OTG_GINTSTS_IISOIXFR_Pos) /*!< 0x00100000 */
+#define USB_OTG_GINTSTS_IISOIXFR USB_OTG_GINTSTS_IISOIXFR_Msk /*!< Incomplete isochronous IN transfer */
+#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos (21U)
+#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk (0x1U << USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos) /*!< 0x00200000 */
+#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk /*!< Incomplete periodic transfer */
+#define USB_OTG_GINTSTS_DATAFSUSP_Pos (22U)
+#define USB_OTG_GINTSTS_DATAFSUSP_Msk (0x1U << USB_OTG_GINTSTS_DATAFSUSP_Pos) /*!< 0x00400000 */
+#define USB_OTG_GINTSTS_DATAFSUSP USB_OTG_GINTSTS_DATAFSUSP_Msk /*!< Data fetch suspended */
+#define USB_OTG_GINTSTS_HPRTINT_Pos (24U)
+#define USB_OTG_GINTSTS_HPRTINT_Msk (0x1U << USB_OTG_GINTSTS_HPRTINT_Pos) /*!< 0x01000000 */
+#define USB_OTG_GINTSTS_HPRTINT USB_OTG_GINTSTS_HPRTINT_Msk /*!< Host port interrupt */
+#define USB_OTG_GINTSTS_HCINT_Pos (25U)
+#define USB_OTG_GINTSTS_HCINT_Msk (0x1U << USB_OTG_GINTSTS_HCINT_Pos) /*!< 0x02000000 */
+#define USB_OTG_GINTSTS_HCINT USB_OTG_GINTSTS_HCINT_Msk /*!< Host channels interrupt */
+#define USB_OTG_GINTSTS_PTXFE_Pos (26U)
+#define USB_OTG_GINTSTS_PTXFE_Msk (0x1U << USB_OTG_GINTSTS_PTXFE_Pos) /*!< 0x04000000 */
+#define USB_OTG_GINTSTS_PTXFE USB_OTG_GINTSTS_PTXFE_Msk /*!< Periodic TxFIFO empty */
+#define USB_OTG_GINTSTS_CIDSCHG_Pos (28U)
+#define USB_OTG_GINTSTS_CIDSCHG_Msk (0x1U << USB_OTG_GINTSTS_CIDSCHG_Pos) /*!< 0x10000000 */
+#define USB_OTG_GINTSTS_CIDSCHG USB_OTG_GINTSTS_CIDSCHG_Msk /*!< Connector ID status change */
+#define USB_OTG_GINTSTS_DISCINT_Pos (29U)
+#define USB_OTG_GINTSTS_DISCINT_Msk (0x1U << USB_OTG_GINTSTS_DISCINT_Pos) /*!< 0x20000000 */
+#define USB_OTG_GINTSTS_DISCINT USB_OTG_GINTSTS_DISCINT_Msk /*!< Disconnect detected interrupt */
+#define USB_OTG_GINTSTS_SRQINT_Pos (30U)
+#define USB_OTG_GINTSTS_SRQINT_Msk (0x1U << USB_OTG_GINTSTS_SRQINT_Pos) /*!< 0x40000000 */
+#define USB_OTG_GINTSTS_SRQINT USB_OTG_GINTSTS_SRQINT_Msk /*!< Session request/new session detected interrupt */
+#define USB_OTG_GINTSTS_WKUINT_Pos (31U)
+#define USB_OTG_GINTSTS_WKUINT_Msk (0x1U << USB_OTG_GINTSTS_WKUINT_Pos) /*!< 0x80000000 */
+#define USB_OTG_GINTSTS_WKUINT USB_OTG_GINTSTS_WKUINT_Msk /*!< Resume/remote wakeup detected interrupt */
+
+/******************** Bit definition forUSB_OTG_GINTMSK register *****************/
+#define USB_OTG_GINTMSK_MMISM_Pos (1U)
+#define USB_OTG_GINTMSK_MMISM_Msk (0x1U << USB_OTG_GINTMSK_MMISM_Pos) /*!< 0x00000002 */
+#define USB_OTG_GINTMSK_MMISM USB_OTG_GINTMSK_MMISM_Msk /*!< Mode mismatch interrupt mask */
+#define USB_OTG_GINTMSK_OTGINT_Pos (2U)
+#define USB_OTG_GINTMSK_OTGINT_Msk (0x1U << USB_OTG_GINTMSK_OTGINT_Pos) /*!< 0x00000004 */
+#define USB_OTG_GINTMSK_OTGINT USB_OTG_GINTMSK_OTGINT_Msk /*!< OTG interrupt mask */
+#define USB_OTG_GINTMSK_SOFM_Pos (3U)
+#define USB_OTG_GINTMSK_SOFM_Msk (0x1U << USB_OTG_GINTMSK_SOFM_Pos) /*!< 0x00000008 */
+#define USB_OTG_GINTMSK_SOFM USB_OTG_GINTMSK_SOFM_Msk /*!< Start of frame mask */
+#define USB_OTG_GINTMSK_RXFLVLM_Pos (4U)
+#define USB_OTG_GINTMSK_RXFLVLM_Msk (0x1U << USB_OTG_GINTMSK_RXFLVLM_Pos) /*!< 0x00000010 */
+#define USB_OTG_GINTMSK_RXFLVLM USB_OTG_GINTMSK_RXFLVLM_Msk /*!< Receive FIFO nonempty mask */
+#define USB_OTG_GINTMSK_NPTXFEM_Pos (5U)
+#define USB_OTG_GINTMSK_NPTXFEM_Msk (0x1U << USB_OTG_GINTMSK_NPTXFEM_Pos) /*!< 0x00000020 */
+#define USB_OTG_GINTMSK_NPTXFEM USB_OTG_GINTMSK_NPTXFEM_Msk /*!< Nonperiodic TxFIFO empty mask */
+#define USB_OTG_GINTMSK_GINAKEFFM_Pos (6U)
+#define USB_OTG_GINTMSK_GINAKEFFM_Msk (0x1U << USB_OTG_GINTMSK_GINAKEFFM_Pos) /*!< 0x00000040 */
+#define USB_OTG_GINTMSK_GINAKEFFM USB_OTG_GINTMSK_GINAKEFFM_Msk /*!< Global nonperiodic IN NAK effective mask */
+#define USB_OTG_GINTMSK_GONAKEFFM_Pos (7U)
+#define USB_OTG_GINTMSK_GONAKEFFM_Msk (0x1U << USB_OTG_GINTMSK_GONAKEFFM_Pos) /*!< 0x00000080 */
+#define USB_OTG_GINTMSK_GONAKEFFM USB_OTG_GINTMSK_GONAKEFFM_Msk /*!< Global OUT NAK effective mask */
+#define USB_OTG_GINTMSK_ESUSPM_Pos (10U)
+#define USB_OTG_GINTMSK_ESUSPM_Msk (0x1U << USB_OTG_GINTMSK_ESUSPM_Pos) /*!< 0x00000400 */
+#define USB_OTG_GINTMSK_ESUSPM USB_OTG_GINTMSK_ESUSPM_Msk /*!< Early suspend mask */
+#define USB_OTG_GINTMSK_USBSUSPM_Pos (11U)
+#define USB_OTG_GINTMSK_USBSUSPM_Msk (0x1U << USB_OTG_GINTMSK_USBSUSPM_Pos) /*!< 0x00000800 */
+#define USB_OTG_GINTMSK_USBSUSPM USB_OTG_GINTMSK_USBSUSPM_Msk /*!< USB suspend mask */
+#define USB_OTG_GINTMSK_USBRST_Pos (12U)
+#define USB_OTG_GINTMSK_USBRST_Msk (0x1U << USB_OTG_GINTMSK_USBRST_Pos) /*!< 0x00001000 */
+#define USB_OTG_GINTMSK_USBRST USB_OTG_GINTMSK_USBRST_Msk /*!< USB reset mask */
+#define USB_OTG_GINTMSK_ENUMDNEM_Pos (13U)
+#define USB_OTG_GINTMSK_ENUMDNEM_Msk (0x1U << USB_OTG_GINTMSK_ENUMDNEM_Pos) /*!< 0x00002000 */
+#define USB_OTG_GINTMSK_ENUMDNEM USB_OTG_GINTMSK_ENUMDNEM_Msk /*!< Enumeration done mask */
+#define USB_OTG_GINTMSK_ISOODRPM_Pos (14U)
+#define USB_OTG_GINTMSK_ISOODRPM_Msk (0x1U << USB_OTG_GINTMSK_ISOODRPM_Pos) /*!< 0x00004000 */
+#define USB_OTG_GINTMSK_ISOODRPM USB_OTG_GINTMSK_ISOODRPM_Msk /*!< Isochronous OUT packet dropped interrupt mask */
+#define USB_OTG_GINTMSK_EOPFM_Pos (15U)
+#define USB_OTG_GINTMSK_EOPFM_Msk (0x1U << USB_OTG_GINTMSK_EOPFM_Pos) /*!< 0x00008000 */
+#define USB_OTG_GINTMSK_EOPFM USB_OTG_GINTMSK_EOPFM_Msk /*!< End of periodic frame interrupt mask */
+#define USB_OTG_GINTMSK_EPMISM_Pos (17U)
+#define USB_OTG_GINTMSK_EPMISM_Msk (0x1U << USB_OTG_GINTMSK_EPMISM_Pos) /*!< 0x00020000 */
+#define USB_OTG_GINTMSK_EPMISM USB_OTG_GINTMSK_EPMISM_Msk /*!< Endpoint mismatch interrupt mask */
+#define USB_OTG_GINTMSK_IEPINT_Pos (18U)
+#define USB_OTG_GINTMSK_IEPINT_Msk (0x1U << USB_OTG_GINTMSK_IEPINT_Pos) /*!< 0x00040000 */
+#define USB_OTG_GINTMSK_IEPINT USB_OTG_GINTMSK_IEPINT_Msk /*!< IN endpoints interrupt mask */
+#define USB_OTG_GINTMSK_OEPINT_Pos (19U)
+#define USB_OTG_GINTMSK_OEPINT_Msk (0x1U << USB_OTG_GINTMSK_OEPINT_Pos) /*!< 0x00080000 */
+#define USB_OTG_GINTMSK_OEPINT USB_OTG_GINTMSK_OEPINT_Msk /*!< OUT endpoints interrupt mask */
+#define USB_OTG_GINTMSK_IISOIXFRM_Pos (20U)
+#define USB_OTG_GINTMSK_IISOIXFRM_Msk (0x1U << USB_OTG_GINTMSK_IISOIXFRM_Pos) /*!< 0x00100000 */
+#define USB_OTG_GINTMSK_IISOIXFRM USB_OTG_GINTMSK_IISOIXFRM_Msk /*!< Incomplete isochronous IN transfer mask */
+#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos (21U)
+#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk (0x1U << USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos) /*!< 0x00200000 */
+#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk /*!< Incomplete periodic transfer mask */
+#define USB_OTG_GINTMSK_FSUSPM_Pos (22U)
+#define USB_OTG_GINTMSK_FSUSPM_Msk (0x1U << USB_OTG_GINTMSK_FSUSPM_Pos) /*!< 0x00400000 */
+#define USB_OTG_GINTMSK_FSUSPM USB_OTG_GINTMSK_FSUSPM_Msk /*!< Data fetch suspended mask */
+#define USB_OTG_GINTMSK_PRTIM_Pos (24U)
+#define USB_OTG_GINTMSK_PRTIM_Msk (0x1U << USB_OTG_GINTMSK_PRTIM_Pos) /*!< 0x01000000 */
+#define USB_OTG_GINTMSK_PRTIM USB_OTG_GINTMSK_PRTIM_Msk /*!< Host port interrupt mask */
+#define USB_OTG_GINTMSK_HCIM_Pos (25U)
+#define USB_OTG_GINTMSK_HCIM_Msk (0x1U << USB_OTG_GINTMSK_HCIM_Pos) /*!< 0x02000000 */
+#define USB_OTG_GINTMSK_HCIM USB_OTG_GINTMSK_HCIM_Msk /*!< Host channels interrupt mask */
+#define USB_OTG_GINTMSK_PTXFEM_Pos (26U)
+#define USB_OTG_GINTMSK_PTXFEM_Msk (0x1U << USB_OTG_GINTMSK_PTXFEM_Pos) /*!< 0x04000000 */
+#define USB_OTG_GINTMSK_PTXFEM USB_OTG_GINTMSK_PTXFEM_Msk /*!< Periodic TxFIFO empty mask */
+#define USB_OTG_GINTMSK_CIDSCHGM_Pos (28U)
+#define USB_OTG_GINTMSK_CIDSCHGM_Msk (0x1U << USB_OTG_GINTMSK_CIDSCHGM_Pos) /*!< 0x10000000 */
+#define USB_OTG_GINTMSK_CIDSCHGM USB_OTG_GINTMSK_CIDSCHGM_Msk /*!< Connector ID status change mask */
+#define USB_OTG_GINTMSK_DISCINT_Pos (29U)
+#define USB_OTG_GINTMSK_DISCINT_Msk (0x1U << USB_OTG_GINTMSK_DISCINT_Pos) /*!< 0x20000000 */
+#define USB_OTG_GINTMSK_DISCINT USB_OTG_GINTMSK_DISCINT_Msk /*!< Disconnect detected interrupt mask */
+#define USB_OTG_GINTMSK_SRQIM_Pos (30U)
+#define USB_OTG_GINTMSK_SRQIM_Msk (0x1U << USB_OTG_GINTMSK_SRQIM_Pos) /*!< 0x40000000 */
+#define USB_OTG_GINTMSK_SRQIM USB_OTG_GINTMSK_SRQIM_Msk /*!< Session request/new session detected interrupt mask */
+#define USB_OTG_GINTMSK_WUIM_Pos (31U)
+#define USB_OTG_GINTMSK_WUIM_Msk (0x1U << USB_OTG_GINTMSK_WUIM_Pos) /*!< 0x80000000 */
+#define USB_OTG_GINTMSK_WUIM USB_OTG_GINTMSK_WUIM_Msk /*!< Resume/remote wakeup detected interrupt mask */
+
+/******************** Bit definition forUSB_OTG_DAINT register *******************/
+#define USB_OTG_DAINT_IEPINT_Pos (0U)
+#define USB_OTG_DAINT_IEPINT_Msk (0xFFFFU << USB_OTG_DAINT_IEPINT_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_DAINT_IEPINT USB_OTG_DAINT_IEPINT_Msk /*!< IN endpoint interrupt bits */
+#define USB_OTG_DAINT_OEPINT_Pos (16U)
+#define USB_OTG_DAINT_OEPINT_Msk (0xFFFFU << USB_OTG_DAINT_OEPINT_Pos) /*!< 0xFFFF0000 */
+#define USB_OTG_DAINT_OEPINT USB_OTG_DAINT_OEPINT_Msk /*!< OUT endpoint interrupt bits */
+
+/******************** Bit definition forUSB_OTG_HAINTMSK register ****************/
+#define USB_OTG_HAINTMSK_HAINTM_Pos (0U)
+#define USB_OTG_HAINTMSK_HAINTM_Msk (0xFFFFU << USB_OTG_HAINTMSK_HAINTM_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_HAINTMSK_HAINTM USB_OTG_HAINTMSK_HAINTM_Msk /*!< Channel interrupt mask */
+
+/******************** Bit definition for USB_OTG_GRXSTSP register ****************/
+#define USB_OTG_GRXSTSP_EPNUM_Pos (0U)
+#define USB_OTG_GRXSTSP_EPNUM_Msk (0xFU << USB_OTG_GRXSTSP_EPNUM_Pos) /*!< 0x0000000F */
+#define USB_OTG_GRXSTSP_EPNUM USB_OTG_GRXSTSP_EPNUM_Msk /*!< IN EP interrupt mask bits */
+#define USB_OTG_GRXSTSP_BCNT_Pos (4U)
+#define USB_OTG_GRXSTSP_BCNT_Msk (0x7FFU << USB_OTG_GRXSTSP_BCNT_Pos) /*!< 0x00007FF0 */
+#define USB_OTG_GRXSTSP_BCNT USB_OTG_GRXSTSP_BCNT_Msk /*!< OUT EP interrupt mask bits */
+#define USB_OTG_GRXSTSP_DPID_Pos (15U)
+#define USB_OTG_GRXSTSP_DPID_Msk (0x3U << USB_OTG_GRXSTSP_DPID_Pos) /*!< 0x00018000 */
+#define USB_OTG_GRXSTSP_DPID USB_OTG_GRXSTSP_DPID_Msk /*!< OUT EP interrupt mask bits */
+#define USB_OTG_GRXSTSP_PKTSTS_Pos (17U)
+#define USB_OTG_GRXSTSP_PKTSTS_Msk (0xFU << USB_OTG_GRXSTSP_PKTSTS_Pos) /*!< 0x001E0000 */
+#define USB_OTG_GRXSTSP_PKTSTS USB_OTG_GRXSTSP_PKTSTS_Msk /*!< OUT EP interrupt mask bits */
+
+/******************** Bit definition forUSB_OTG_DAINTMSK register ****************/
+#define USB_OTG_DAINTMSK_IEPM_Pos (0U)
+#define USB_OTG_DAINTMSK_IEPM_Msk (0xFFFFU << USB_OTG_DAINTMSK_IEPM_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_DAINTMSK_IEPM USB_OTG_DAINTMSK_IEPM_Msk /*!< IN EP interrupt mask bits */
+#define USB_OTG_DAINTMSK_OEPM_Pos (16U)
+#define USB_OTG_DAINTMSK_OEPM_Msk (0xFFFFU << USB_OTG_DAINTMSK_OEPM_Pos) /*!< 0xFFFF0000 */
+#define USB_OTG_DAINTMSK_OEPM USB_OTG_DAINTMSK_OEPM_Msk /*!< OUT EP interrupt mask bits */
+
+/******************** Bit definition for OTG register ****************************/
+#define USB_OTG_CHNUM_Pos (0U)
+#define USB_OTG_CHNUM_Msk (0xFU << USB_OTG_CHNUM_Pos) /*!< 0x0000000F */
+#define USB_OTG_CHNUM USB_OTG_CHNUM_Msk /*!< Channel number */
+#define USB_OTG_CHNUM_0 (0x1U << USB_OTG_CHNUM_Pos) /*!< 0x00000001 */
+#define USB_OTG_CHNUM_1 (0x2U << USB_OTG_CHNUM_Pos) /*!< 0x00000002 */
+#define USB_OTG_CHNUM_2 (0x4U << USB_OTG_CHNUM_Pos) /*!< 0x00000004 */
+#define USB_OTG_CHNUM_3 (0x8U << USB_OTG_CHNUM_Pos) /*!< 0x00000008 */
+#define USB_OTG_BCNT_Pos (4U)
+#define USB_OTG_BCNT_Msk (0x7FFU << USB_OTG_BCNT_Pos) /*!< 0x00007FF0 */
+#define USB_OTG_BCNT USB_OTG_BCNT_Msk /*!< Byte count */
+
+#define USB_OTG_DPID_Pos (15U)
+#define USB_OTG_DPID_Msk (0x3U << USB_OTG_DPID_Pos) /*!< 0x00018000 */
+#define USB_OTG_DPID USB_OTG_DPID_Msk /*!< Data PID */
+#define USB_OTG_DPID_0 (0x1U << USB_OTG_DPID_Pos) /*!< 0x00008000 */
+#define USB_OTG_DPID_1 (0x2U << USB_OTG_DPID_Pos) /*!< 0x00010000 */
+
+#define USB_OTG_PKTSTS_Pos (17U)
+#define USB_OTG_PKTSTS_Msk (0xFU << USB_OTG_PKTSTS_Pos) /*!< 0x001E0000 */
+#define USB_OTG_PKTSTS USB_OTG_PKTSTS_Msk /*!< Packet status */
+#define USB_OTG_PKTSTS_0 (0x1U << USB_OTG_PKTSTS_Pos) /*!< 0x00020000 */
+#define USB_OTG_PKTSTS_1 (0x2U << USB_OTG_PKTSTS_Pos) /*!< 0x00040000 */
+#define USB_OTG_PKTSTS_2 (0x4U << USB_OTG_PKTSTS_Pos) /*!< 0x00080000 */
+#define USB_OTG_PKTSTS_3 (0x8U << USB_OTG_PKTSTS_Pos) /*!< 0x00100000 */
+
+#define USB_OTG_EPNUM_Pos (0U)
+#define USB_OTG_EPNUM_Msk (0xFU << USB_OTG_EPNUM_Pos) /*!< 0x0000000F */
+#define USB_OTG_EPNUM USB_OTG_EPNUM_Msk /*!< Endpoint number */
+#define USB_OTG_EPNUM_0 (0x1U << USB_OTG_EPNUM_Pos) /*!< 0x00000001 */
+#define USB_OTG_EPNUM_1 (0x2U << USB_OTG_EPNUM_Pos) /*!< 0x00000002 */
+#define USB_OTG_EPNUM_2 (0x4U << USB_OTG_EPNUM_Pos) /*!< 0x00000004 */
+#define USB_OTG_EPNUM_3 (0x8U << USB_OTG_EPNUM_Pos) /*!< 0x00000008 */
+
+#define USB_OTG_FRMNUM_Pos (21U)
+#define USB_OTG_FRMNUM_Msk (0xFU << USB_OTG_FRMNUM_Pos) /*!< 0x01E00000 */
+#define USB_OTG_FRMNUM USB_OTG_FRMNUM_Msk /*!< Frame number */
+#define USB_OTG_FRMNUM_0 (0x1U << USB_OTG_FRMNUM_Pos) /*!< 0x00200000 */
+#define USB_OTG_FRMNUM_1 (0x2U << USB_OTG_FRMNUM_Pos) /*!< 0x00400000 */
+#define USB_OTG_FRMNUM_2 (0x4U << USB_OTG_FRMNUM_Pos) /*!< 0x00800000 */
+#define USB_OTG_FRMNUM_3 (0x8U << USB_OTG_FRMNUM_Pos) /*!< 0x01000000 */
+
+/******************** Bit definition for OTG register ****************************/
+#define USB_OTG_CHNUM_Pos (0U)
+#define USB_OTG_CHNUM_Msk (0xFU << USB_OTG_CHNUM_Pos) /*!< 0x0000000F */
+#define USB_OTG_CHNUM USB_OTG_CHNUM_Msk /*!< Channel number */
+#define USB_OTG_CHNUM_0 (0x1U << USB_OTG_CHNUM_Pos) /*!< 0x00000001 */
+#define USB_OTG_CHNUM_1 (0x2U << USB_OTG_CHNUM_Pos) /*!< 0x00000002 */
+#define USB_OTG_CHNUM_2 (0x4U << USB_OTG_CHNUM_Pos) /*!< 0x00000004 */
+#define USB_OTG_CHNUM_3 (0x8U << USB_OTG_CHNUM_Pos) /*!< 0x00000008 */
+#define USB_OTG_BCNT_Pos (4U)
+#define USB_OTG_BCNT_Msk (0x7FFU << USB_OTG_BCNT_Pos) /*!< 0x00007FF0 */
+#define USB_OTG_BCNT USB_OTG_BCNT_Msk /*!< Byte count */
+
+#define USB_OTG_DPID_Pos (15U)
+#define USB_OTG_DPID_Msk (0x3U << USB_OTG_DPID_Pos) /*!< 0x00018000 */
+#define USB_OTG_DPID USB_OTG_DPID_Msk /*!< Data PID */
+#define USB_OTG_DPID_0 (0x1U << USB_OTG_DPID_Pos) /*!< 0x00008000 */
+#define USB_OTG_DPID_1 (0x2U << USB_OTG_DPID_Pos) /*!< 0x00010000 */
+
+#define USB_OTG_PKTSTS_Pos (17U)
+#define USB_OTG_PKTSTS_Msk (0xFU << USB_OTG_PKTSTS_Pos) /*!< 0x001E0000 */
+#define USB_OTG_PKTSTS USB_OTG_PKTSTS_Msk /*!< Packet status */
+#define USB_OTG_PKTSTS_0 (0x1U << USB_OTG_PKTSTS_Pos) /*!< 0x00020000 */
+#define USB_OTG_PKTSTS_1 (0x2U << USB_OTG_PKTSTS_Pos) /*!< 0x00040000 */
+#define USB_OTG_PKTSTS_2 (0x4U << USB_OTG_PKTSTS_Pos) /*!< 0x00080000 */
+#define USB_OTG_PKTSTS_3 (0x8U << USB_OTG_PKTSTS_Pos) /*!< 0x00100000 */
+
+#define USB_OTG_EPNUM_Pos (0U)
+#define USB_OTG_EPNUM_Msk (0xFU << USB_OTG_EPNUM_Pos) /*!< 0x0000000F */
+#define USB_OTG_EPNUM USB_OTG_EPNUM_Msk /*!< Endpoint number */
+#define USB_OTG_EPNUM_0 (0x1U << USB_OTG_EPNUM_Pos) /*!< 0x00000001 */
+#define USB_OTG_EPNUM_1 (0x2U << USB_OTG_EPNUM_Pos) /*!< 0x00000002 */
+#define USB_OTG_EPNUM_2 (0x4U << USB_OTG_EPNUM_Pos) /*!< 0x00000004 */
+#define USB_OTG_EPNUM_3 (0x8U << USB_OTG_EPNUM_Pos) /*!< 0x00000008 */
+
+#define USB_OTG_FRMNUM_Pos (21U)
+#define USB_OTG_FRMNUM_Msk (0xFU << USB_OTG_FRMNUM_Pos) /*!< 0x01E00000 */
+#define USB_OTG_FRMNUM USB_OTG_FRMNUM_Msk /*!< Frame number */
+#define USB_OTG_FRMNUM_0 (0x1U << USB_OTG_FRMNUM_Pos) /*!< 0x00200000 */
+#define USB_OTG_FRMNUM_1 (0x2U << USB_OTG_FRMNUM_Pos) /*!< 0x00400000 */
+#define USB_OTG_FRMNUM_2 (0x4U << USB_OTG_FRMNUM_Pos) /*!< 0x00800000 */
+#define USB_OTG_FRMNUM_3 (0x8U << USB_OTG_FRMNUM_Pos) /*!< 0x01000000 */
+
+/******************** Bit definition forUSB_OTG_GRXFSIZ register *****************/
+#define USB_OTG_GRXFSIZ_RXFD_Pos (0U)
+#define USB_OTG_GRXFSIZ_RXFD_Msk (0xFFFFU << USB_OTG_GRXFSIZ_RXFD_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_GRXFSIZ_RXFD USB_OTG_GRXFSIZ_RXFD_Msk /*!< RxFIFO depth */
+
+/******************** Bit definition forUSB_OTG_DVBUSDIS register ****************/
+#define USB_OTG_DVBUSDIS_VBUSDT_Pos (0U)
+#define USB_OTG_DVBUSDIS_VBUSDT_Msk (0xFFFFU << USB_OTG_DVBUSDIS_VBUSDT_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_DVBUSDIS_VBUSDT USB_OTG_DVBUSDIS_VBUSDT_Msk /*!< Device VBUS discharge time */
+
+/******************** Bit definition for OTG register ****************************/
+#define USB_OTG_NPTXFSA_Pos (0U)
+#define USB_OTG_NPTXFSA_Msk (0xFFFFU << USB_OTG_NPTXFSA_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_NPTXFSA USB_OTG_NPTXFSA_Msk /*!< Nonperiodic transmit RAM start address */
+#define USB_OTG_NPTXFD_Pos (16U)
+#define USB_OTG_NPTXFD_Msk (0xFFFFU << USB_OTG_NPTXFD_Pos) /*!< 0xFFFF0000 */
+#define USB_OTG_NPTXFD USB_OTG_NPTXFD_Msk /*!< Nonperiodic TxFIFO depth */
+#define USB_OTG_TX0FSA_Pos (0U)
+#define USB_OTG_TX0FSA_Msk (0xFFFFU << USB_OTG_TX0FSA_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_TX0FSA USB_OTG_TX0FSA_Msk /*!< Endpoint 0 transmit RAM start address */
+#define USB_OTG_TX0FD_Pos (16U)
+#define USB_OTG_TX0FD_Msk (0xFFFFU << USB_OTG_TX0FD_Pos) /*!< 0xFFFF0000 */
+#define USB_OTG_TX0FD USB_OTG_TX0FD_Msk /*!< Endpoint 0 TxFIFO depth */
+
+/******************** Bit definition forUSB_OTG_DVBUSPULSE register **************/
+#define USB_OTG_DVBUSPULSE_DVBUSP_Pos (0U)
+#define USB_OTG_DVBUSPULSE_DVBUSP_Msk (0xFFFU << USB_OTG_DVBUSPULSE_DVBUSP_Pos) /*!< 0x00000FFF */
+#define USB_OTG_DVBUSPULSE_DVBUSP USB_OTG_DVBUSPULSE_DVBUSP_Msk /*!< Device VBUS pulsing time */
+
+/******************** Bit definition forUSB_OTG_GNPTXSTS register ****************/
+#define USB_OTG_GNPTXSTS_NPTXFSAV_Pos (0U)
+#define USB_OTG_GNPTXSTS_NPTXFSAV_Msk (0xFFFFU << USB_OTG_GNPTXSTS_NPTXFSAV_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_GNPTXSTS_NPTXFSAV USB_OTG_GNPTXSTS_NPTXFSAV_Msk /*!< Nonperiodic TxFIFO space available */
+
+#define USB_OTG_GNPTXSTS_NPTQXSAV_Pos (16U)
+#define USB_OTG_GNPTXSTS_NPTQXSAV_Msk (0xFFU << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00FF0000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV USB_OTG_GNPTXSTS_NPTQXSAV_Msk /*!< Nonperiodic transmit request queue space available */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_0 (0x01U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00010000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_1 (0x02U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00020000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_2 (0x04U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00040000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_3 (0x08U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00080000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_4 (0x10U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00100000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_5 (0x20U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00200000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_6 (0x40U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00400000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_7 (0x80U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00800000 */
+
+#define USB_OTG_GNPTXSTS_NPTXQTOP_Pos (24U)
+#define USB_OTG_GNPTXSTS_NPTXQTOP_Msk (0x7FU << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x7F000000 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP USB_OTG_GNPTXSTS_NPTXQTOP_Msk /*!< Top of the nonperiodic transmit request queue */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_0 (0x01U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x01000000 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_1 (0x02U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x02000000 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_2 (0x04U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x04000000 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_3 (0x08U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x08000000 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_4 (0x10U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x10000000 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_5 (0x20U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x20000000 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_6 (0x40U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x40000000 */
+
+/******************** Bit definition forUSB_OTG_DTHRCTL register *****************/
+#define USB_OTG_DTHRCTL_NONISOTHREN_Pos (0U)
+#define USB_OTG_DTHRCTL_NONISOTHREN_Msk (0x1U << USB_OTG_DTHRCTL_NONISOTHREN_Pos) /*!< 0x00000001 */
+#define USB_OTG_DTHRCTL_NONISOTHREN USB_OTG_DTHRCTL_NONISOTHREN_Msk /*!< Nonisochronous IN endpoints threshold enable */
+#define USB_OTG_DTHRCTL_ISOTHREN_Pos (1U)
+#define USB_OTG_DTHRCTL_ISOTHREN_Msk (0x1U << USB_OTG_DTHRCTL_ISOTHREN_Pos) /*!< 0x00000002 */
+#define USB_OTG_DTHRCTL_ISOTHREN USB_OTG_DTHRCTL_ISOTHREN_Msk /*!< ISO IN endpoint threshold enable */
+
+#define USB_OTG_DTHRCTL_TXTHRLEN_Pos (2U)
+#define USB_OTG_DTHRCTL_TXTHRLEN_Msk (0x1FFU << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x000007FC */
+#define USB_OTG_DTHRCTL_TXTHRLEN USB_OTG_DTHRCTL_TXTHRLEN_Msk /*!< Transmit threshold length */
+#define USB_OTG_DTHRCTL_TXTHRLEN_0 (0x001U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000004 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_1 (0x002U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000008 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_2 (0x004U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000010 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_3 (0x008U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000020 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_4 (0x010U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000040 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_5 (0x020U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000080 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_6 (0x040U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000100 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_7 (0x080U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000200 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_8 (0x100U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000400 */
+#define USB_OTG_DTHRCTL_RXTHREN_Pos (16U)
+#define USB_OTG_DTHRCTL_RXTHREN_Msk (0x1U << USB_OTG_DTHRCTL_RXTHREN_Pos) /*!< 0x00010000 */
+#define USB_OTG_DTHRCTL_RXTHREN USB_OTG_DTHRCTL_RXTHREN_Msk /*!< Receive threshold enable */
+
+#define USB_OTG_DTHRCTL_RXTHRLEN_Pos (17U)
+#define USB_OTG_DTHRCTL_RXTHRLEN_Msk (0x1FFU << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x03FE0000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN USB_OTG_DTHRCTL_RXTHRLEN_Msk /*!< Receive threshold length */
+#define USB_OTG_DTHRCTL_RXTHRLEN_0 (0x001U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00020000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_1 (0x002U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00040000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_2 (0x004U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00080000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_3 (0x008U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00100000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_4 (0x010U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00200000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_5 (0x020U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00400000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_6 (0x040U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00800000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_7 (0x080U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x01000000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_8 (0x100U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x02000000 */
+#define USB_OTG_DTHRCTL_ARPEN_Pos (27U)
+#define USB_OTG_DTHRCTL_ARPEN_Msk (0x1U << USB_OTG_DTHRCTL_ARPEN_Pos) /*!< 0x08000000 */
+#define USB_OTG_DTHRCTL_ARPEN USB_OTG_DTHRCTL_ARPEN_Msk /*!< Arbiter parking enable */
+
+/******************** Bit definition forUSB_OTG_DIEPEMPMSK register **************/
+#define USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos (0U)
+#define USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk (0xFFFFU << USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_DIEPEMPMSK_INEPTXFEM USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk /*!< IN EP Tx FIFO empty interrupt mask bits */
+
+/******************** Bit definition forUSB_OTG_DEACHINT register ****************/
+#define USB_OTG_DEACHINT_IEP1INT_Pos (1U)
+#define USB_OTG_DEACHINT_IEP1INT_Msk (0x1U << USB_OTG_DEACHINT_IEP1INT_Pos) /*!< 0x00000002 */
+#define USB_OTG_DEACHINT_IEP1INT USB_OTG_DEACHINT_IEP1INT_Msk /*!< IN endpoint 1interrupt bit */
+#define USB_OTG_DEACHINT_OEP1INT_Pos (17U)
+#define USB_OTG_DEACHINT_OEP1INT_Msk (0x1U << USB_OTG_DEACHINT_OEP1INT_Pos) /*!< 0x00020000 */
+#define USB_OTG_DEACHINT_OEP1INT USB_OTG_DEACHINT_OEP1INT_Msk /*!< OUT endpoint 1 interrupt bit */
+
+/******************** Bit definition forUSB_OTG_GCCFG register *******************/
+#define USB_OTG_GCCFG_PWRDWN_Pos (16U)
+#define USB_OTG_GCCFG_PWRDWN_Msk (0x1U << USB_OTG_GCCFG_PWRDWN_Pos) /*!< 0x00010000 */
+#define USB_OTG_GCCFG_PWRDWN USB_OTG_GCCFG_PWRDWN_Msk /*!< Power down */
+#define USB_OTG_GCCFG_VBUSASEN_Pos (18U)
+#define USB_OTG_GCCFG_VBUSASEN_Msk (0x1U << USB_OTG_GCCFG_VBUSASEN_Pos) /*!< 0x00040000 */
+#define USB_OTG_GCCFG_VBUSASEN USB_OTG_GCCFG_VBUSASEN_Msk /*!< Enable the VBUS sensing device */
+#define USB_OTG_GCCFG_VBUSBSEN_Pos (19U)
+#define USB_OTG_GCCFG_VBUSBSEN_Msk (0x1U << USB_OTG_GCCFG_VBUSBSEN_Pos) /*!< 0x00080000 */
+#define USB_OTG_GCCFG_VBUSBSEN USB_OTG_GCCFG_VBUSBSEN_Msk /*!< Enable the VBUS sensing device */
+#define USB_OTG_GCCFG_SOFOUTEN_Pos (20U)
+#define USB_OTG_GCCFG_SOFOUTEN_Msk (0x1U << USB_OTG_GCCFG_SOFOUTEN_Pos) /*!< 0x00100000 */
+#define USB_OTG_GCCFG_SOFOUTEN USB_OTG_GCCFG_SOFOUTEN_Msk /*!< SOF output enable */
+
+/******************** Bit definition forUSB_OTG_DEACHINTMSK register *************/
+#define USB_OTG_DEACHINTMSK_IEP1INTM_Pos (1U)
+#define USB_OTG_DEACHINTMSK_IEP1INTM_Msk (0x1U << USB_OTG_DEACHINTMSK_IEP1INTM_Pos) /*!< 0x00000002 */
+#define USB_OTG_DEACHINTMSK_IEP1INTM USB_OTG_DEACHINTMSK_IEP1INTM_Msk /*!< IN Endpoint 1 interrupt mask bit */
+#define USB_OTG_DEACHINTMSK_OEP1INTM_Pos (17U)
+#define USB_OTG_DEACHINTMSK_OEP1INTM_Msk (0x1U << USB_OTG_DEACHINTMSK_OEP1INTM_Pos) /*!< 0x00020000 */
+#define USB_OTG_DEACHINTMSK_OEP1INTM USB_OTG_DEACHINTMSK_OEP1INTM_Msk /*!< OUT Endpoint 1 interrupt mask bit */
+
+/******************** Bit definition forUSB_OTG_CID register *********************/
+#define USB_OTG_CID_PRODUCT_ID_Pos (0U)
+#define USB_OTG_CID_PRODUCT_ID_Msk (0xFFFFFFFFU << USB_OTG_CID_PRODUCT_ID_Pos) /*!< 0xFFFFFFFF */
+#define USB_OTG_CID_PRODUCT_ID USB_OTG_CID_PRODUCT_ID_Msk /*!< Product ID field */
+
+/******************** Bit definition forUSB_OTG_DIEPEACHMSK1 register ************/
+#define USB_OTG_DIEPEACHMSK1_XFRCM_Pos (0U)
+#define USB_OTG_DIEPEACHMSK1_XFRCM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */
+#define USB_OTG_DIEPEACHMSK1_XFRCM USB_OTG_DIEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask */
+#define USB_OTG_DIEPEACHMSK1_EPDM_Pos (1U)
+#define USB_OTG_DIEPEACHMSK1_EPDM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */
+#define USB_OTG_DIEPEACHMSK1_EPDM USB_OTG_DIEPEACHMSK1_EPDM_Msk /*!< Endpoint disabled interrupt mask */
+#define USB_OTG_DIEPEACHMSK1_TOM_Pos (3U)
+#define USB_OTG_DIEPEACHMSK1_TOM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */
+#define USB_OTG_DIEPEACHMSK1_TOM USB_OTG_DIEPEACHMSK1_TOM_Msk /*!< Timeout condition mask (nonisochronous endpoints) */
+#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos (4U)
+#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk (0x1U << USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */
+#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */
+#define USB_OTG_DIEPEACHMSK1_INEPNMM_Pos (5U)
+#define USB_OTG_DIEPEACHMSK1_INEPNMM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */
+#define USB_OTG_DIEPEACHMSK1_INEPNMM USB_OTG_DIEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask */
+#define USB_OTG_DIEPEACHMSK1_INEPNEM_Pos (6U)
+#define USB_OTG_DIEPEACHMSK1_INEPNEM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */
+#define USB_OTG_DIEPEACHMSK1_INEPNEM USB_OTG_DIEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask */
+#define USB_OTG_DIEPEACHMSK1_TXFURM_Pos (8U)
+#define USB_OTG_DIEPEACHMSK1_TXFURM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */
+#define USB_OTG_DIEPEACHMSK1_TXFURM USB_OTG_DIEPEACHMSK1_TXFURM_Msk /*!< FIFO underrun mask */
+#define USB_OTG_DIEPEACHMSK1_BIM_Pos (9U)
+#define USB_OTG_DIEPEACHMSK1_BIM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */
+#define USB_OTG_DIEPEACHMSK1_BIM USB_OTG_DIEPEACHMSK1_BIM_Msk /*!< BNA interrupt mask */
+#define USB_OTG_DIEPEACHMSK1_NAKM_Pos (13U)
+#define USB_OTG_DIEPEACHMSK1_NAKM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */
+#define USB_OTG_DIEPEACHMSK1_NAKM USB_OTG_DIEPEACHMSK1_NAKM_Msk /*!< NAK interrupt mask */
+
+/******************** Bit definition forUSB_OTG_HPRT register ********************/
+#define USB_OTG_HPRT_PCSTS_Pos (0U)
+#define USB_OTG_HPRT_PCSTS_Msk (0x1U << USB_OTG_HPRT_PCSTS_Pos) /*!< 0x00000001 */
+#define USB_OTG_HPRT_PCSTS USB_OTG_HPRT_PCSTS_Msk /*!< Port connect status */
+#define USB_OTG_HPRT_PCDET_Pos (1U)
+#define USB_OTG_HPRT_PCDET_Msk (0x1U << USB_OTG_HPRT_PCDET_Pos) /*!< 0x00000002 */
+#define USB_OTG_HPRT_PCDET USB_OTG_HPRT_PCDET_Msk /*!< Port connect detected */
+#define USB_OTG_HPRT_PENA_Pos (2U)
+#define USB_OTG_HPRT_PENA_Msk (0x1U << USB_OTG_HPRT_PENA_Pos) /*!< 0x00000004 */
+#define USB_OTG_HPRT_PENA USB_OTG_HPRT_PENA_Msk /*!< Port enable */
+#define USB_OTG_HPRT_PENCHNG_Pos (3U)
+#define USB_OTG_HPRT_PENCHNG_Msk (0x1U << USB_OTG_HPRT_PENCHNG_Pos) /*!< 0x00000008 */
+#define USB_OTG_HPRT_PENCHNG USB_OTG_HPRT_PENCHNG_Msk /*!< Port enable/disable change */
+#define USB_OTG_HPRT_POCA_Pos (4U)
+#define USB_OTG_HPRT_POCA_Msk (0x1U << USB_OTG_HPRT_POCA_Pos) /*!< 0x00000010 */
+#define USB_OTG_HPRT_POCA USB_OTG_HPRT_POCA_Msk /*!< Port overcurrent active */
+#define USB_OTG_HPRT_POCCHNG_Pos (5U)
+#define USB_OTG_HPRT_POCCHNG_Msk (0x1U << USB_OTG_HPRT_POCCHNG_Pos) /*!< 0x00000020 */
+#define USB_OTG_HPRT_POCCHNG USB_OTG_HPRT_POCCHNG_Msk /*!< Port overcurrent change */
+#define USB_OTG_HPRT_PRES_Pos (6U)
+#define USB_OTG_HPRT_PRES_Msk (0x1U << USB_OTG_HPRT_PRES_Pos) /*!< 0x00000040 */
+#define USB_OTG_HPRT_PRES USB_OTG_HPRT_PRES_Msk /*!< Port resume */
+#define USB_OTG_HPRT_PSUSP_Pos (7U)
+#define USB_OTG_HPRT_PSUSP_Msk (0x1U << USB_OTG_HPRT_PSUSP_Pos) /*!< 0x00000080 */
+#define USB_OTG_HPRT_PSUSP USB_OTG_HPRT_PSUSP_Msk /*!< Port suspend */
+#define USB_OTG_HPRT_PRST_Pos (8U)
+#define USB_OTG_HPRT_PRST_Msk (0x1U << USB_OTG_HPRT_PRST_Pos) /*!< 0x00000100 */
+#define USB_OTG_HPRT_PRST USB_OTG_HPRT_PRST_Msk /*!< Port reset */
+
+#define USB_OTG_HPRT_PLSTS_Pos (10U)
+#define USB_OTG_HPRT_PLSTS_Msk (0x3U << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000C00 */
+#define USB_OTG_HPRT_PLSTS USB_OTG_HPRT_PLSTS_Msk /*!< Port line status */
+#define USB_OTG_HPRT_PLSTS_0 (0x1U << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000400 */
+#define USB_OTG_HPRT_PLSTS_1 (0x2U << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000800 */
+#define USB_OTG_HPRT_PPWR_Pos (12U)
+#define USB_OTG_HPRT_PPWR_Msk (0x1U << USB_OTG_HPRT_PPWR_Pos) /*!< 0x00001000 */
+#define USB_OTG_HPRT_PPWR USB_OTG_HPRT_PPWR_Msk /*!< Port power */
+
+#define USB_OTG_HPRT_PTCTL_Pos (13U)
+#define USB_OTG_HPRT_PTCTL_Msk (0xFU << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x0001E000 */
+#define USB_OTG_HPRT_PTCTL USB_OTG_HPRT_PTCTL_Msk /*!< Port test control */
+#define USB_OTG_HPRT_PTCTL_0 (0x1U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00002000 */
+#define USB_OTG_HPRT_PTCTL_1 (0x2U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00004000 */
+#define USB_OTG_HPRT_PTCTL_2 (0x4U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00008000 */
+#define USB_OTG_HPRT_PTCTL_3 (0x8U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00010000 */
+
+#define USB_OTG_HPRT_PSPD_Pos (17U)
+#define USB_OTG_HPRT_PSPD_Msk (0x3U << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00060000 */
+#define USB_OTG_HPRT_PSPD USB_OTG_HPRT_PSPD_Msk /*!< Port speed */
+#define USB_OTG_HPRT_PSPD_0 (0x1U << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00020000 */
+#define USB_OTG_HPRT_PSPD_1 (0x2U << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00040000 */
+
+/******************** Bit definition forUSB_OTG_DOEPEACHMSK1 register ************/
+#define USB_OTG_DOEPEACHMSK1_XFRCM_Pos (0U)
+#define USB_OTG_DOEPEACHMSK1_XFRCM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */
+#define USB_OTG_DOEPEACHMSK1_XFRCM USB_OTG_DOEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_EPDM_Pos (1U)
+#define USB_OTG_DOEPEACHMSK1_EPDM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */
+#define USB_OTG_DOEPEACHMSK1_EPDM USB_OTG_DOEPEACHMSK1_EPDM_Msk /*!< Endpoint disabled interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_TOM_Pos (3U)
+#define USB_OTG_DOEPEACHMSK1_TOM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */
+#define USB_OTG_DOEPEACHMSK1_TOM USB_OTG_DOEPEACHMSK1_TOM_Msk /*!< Timeout condition mask */
+#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos (4U)
+#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk (0x1U << USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */
+#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */
+#define USB_OTG_DOEPEACHMSK1_INEPNMM_Pos (5U)
+#define USB_OTG_DOEPEACHMSK1_INEPNMM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */
+#define USB_OTG_DOEPEACHMSK1_INEPNMM USB_OTG_DOEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask */
+#define USB_OTG_DOEPEACHMSK1_INEPNEM_Pos (6U)
+#define USB_OTG_DOEPEACHMSK1_INEPNEM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */
+#define USB_OTG_DOEPEACHMSK1_INEPNEM USB_OTG_DOEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask */
+#define USB_OTG_DOEPEACHMSK1_TXFURM_Pos (8U)
+#define USB_OTG_DOEPEACHMSK1_TXFURM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */
+#define USB_OTG_DOEPEACHMSK1_TXFURM USB_OTG_DOEPEACHMSK1_TXFURM_Msk /*!< OUT packet error mask */
+#define USB_OTG_DOEPEACHMSK1_BIM_Pos (9U)
+#define USB_OTG_DOEPEACHMSK1_BIM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */
+#define USB_OTG_DOEPEACHMSK1_BIM USB_OTG_DOEPEACHMSK1_BIM_Msk /*!< BNA interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_BERRM_Pos (12U)
+#define USB_OTG_DOEPEACHMSK1_BERRM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_BERRM_Pos) /*!< 0x00001000 */
+#define USB_OTG_DOEPEACHMSK1_BERRM USB_OTG_DOEPEACHMSK1_BERRM_Msk /*!< Bubble error interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_NAKM_Pos (13U)
+#define USB_OTG_DOEPEACHMSK1_NAKM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */
+#define USB_OTG_DOEPEACHMSK1_NAKM USB_OTG_DOEPEACHMSK1_NAKM_Msk /*!< NAK interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_NYETM_Pos (14U)
+#define USB_OTG_DOEPEACHMSK1_NYETM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_NYETM_Pos) /*!< 0x00004000 */
+#define USB_OTG_DOEPEACHMSK1_NYETM USB_OTG_DOEPEACHMSK1_NYETM_Msk /*!< NYET interrupt mask */
+
+/******************** Bit definition forUSB_OTG_HPTXFSIZ register ****************/
+#define USB_OTG_HPTXFSIZ_PTXSA_Pos (0U)
+#define USB_OTG_HPTXFSIZ_PTXSA_Msk (0xFFFFU << USB_OTG_HPTXFSIZ_PTXSA_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_HPTXFSIZ_PTXSA USB_OTG_HPTXFSIZ_PTXSA_Msk /*!< Host periodic TxFIFO start address */
+#define USB_OTG_HPTXFSIZ_PTXFD_Pos (16U)
+#define USB_OTG_HPTXFSIZ_PTXFD_Msk (0xFFFFU << USB_OTG_HPTXFSIZ_PTXFD_Pos) /*!< 0xFFFF0000 */
+#define USB_OTG_HPTXFSIZ_PTXFD USB_OTG_HPTXFSIZ_PTXFD_Msk /*!< Host periodic TxFIFO depth */
+
+/******************** Bit definition forUSB_OTG_DIEPCTL register *****************/
+#define USB_OTG_DIEPCTL_MPSIZ_Pos (0U)
+#define USB_OTG_DIEPCTL_MPSIZ_Msk (0x7FFU << USB_OTG_DIEPCTL_MPSIZ_Pos) /*!< 0x000007FF */
+#define USB_OTG_DIEPCTL_MPSIZ USB_OTG_DIEPCTL_MPSIZ_Msk /*!< Maximum packet size */
+#define USB_OTG_DIEPCTL_USBAEP_Pos (15U)
+#define USB_OTG_DIEPCTL_USBAEP_Msk (0x1U << USB_OTG_DIEPCTL_USBAEP_Pos) /*!< 0x00008000 */
+#define USB_OTG_DIEPCTL_USBAEP USB_OTG_DIEPCTL_USBAEP_Msk /*!< USB active endpoint */
+#define USB_OTG_DIEPCTL_EONUM_DPID_Pos (16U)
+#define USB_OTG_DIEPCTL_EONUM_DPID_Msk (0x1U << USB_OTG_DIEPCTL_EONUM_DPID_Pos) /*!< 0x00010000 */
+#define USB_OTG_DIEPCTL_EONUM_DPID USB_OTG_DIEPCTL_EONUM_DPID_Msk /*!< Even/odd frame */
+#define USB_OTG_DIEPCTL_NAKSTS_Pos (17U)
+#define USB_OTG_DIEPCTL_NAKSTS_Msk (0x1U << USB_OTG_DIEPCTL_NAKSTS_Pos) /*!< 0x00020000 */
+#define USB_OTG_DIEPCTL_NAKSTS USB_OTG_DIEPCTL_NAKSTS_Msk /*!< NAK status */
+
+#define USB_OTG_DIEPCTL_EPTYP_Pos (18U)
+#define USB_OTG_DIEPCTL_EPTYP_Msk (0x3U << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x000C0000 */
+#define USB_OTG_DIEPCTL_EPTYP USB_OTG_DIEPCTL_EPTYP_Msk /*!< Endpoint type */
+#define USB_OTG_DIEPCTL_EPTYP_0 (0x1U << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00040000 */
+#define USB_OTG_DIEPCTL_EPTYP_1 (0x2U << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00080000 */
+#define USB_OTG_DIEPCTL_STALL_Pos (21U)
+#define USB_OTG_DIEPCTL_STALL_Msk (0x1U << USB_OTG_DIEPCTL_STALL_Pos) /*!< 0x00200000 */
+#define USB_OTG_DIEPCTL_STALL USB_OTG_DIEPCTL_STALL_Msk /*!< STALL handshake */
+
+#define USB_OTG_DIEPCTL_TXFNUM_Pos (22U)
+#define USB_OTG_DIEPCTL_TXFNUM_Msk (0xFU << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x03C00000 */
+#define USB_OTG_DIEPCTL_TXFNUM USB_OTG_DIEPCTL_TXFNUM_Msk /*!< TxFIFO number */
+#define USB_OTG_DIEPCTL_TXFNUM_0 (0x1U << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00400000 */
+#define USB_OTG_DIEPCTL_TXFNUM_1 (0x2U << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00800000 */
+#define USB_OTG_DIEPCTL_TXFNUM_2 (0x4U << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x01000000 */
+#define USB_OTG_DIEPCTL_TXFNUM_3 (0x8U << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x02000000 */
+#define USB_OTG_DIEPCTL_CNAK_Pos (26U)
+#define USB_OTG_DIEPCTL_CNAK_Msk (0x1U << USB_OTG_DIEPCTL_CNAK_Pos) /*!< 0x04000000 */
+#define USB_OTG_DIEPCTL_CNAK USB_OTG_DIEPCTL_CNAK_Msk /*!< Clear NAK */
+#define USB_OTG_DIEPCTL_SNAK_Pos (27U)
+#define USB_OTG_DIEPCTL_SNAK_Msk (0x1U << USB_OTG_DIEPCTL_SNAK_Pos) /*!< 0x08000000 */
+#define USB_OTG_DIEPCTL_SNAK USB_OTG_DIEPCTL_SNAK_Msk /*!< Set NAK */
+#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos (28U)
+#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk (0x1U << USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */
+#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */
+#define USB_OTG_DIEPCTL_SODDFRM_Pos (29U)
+#define USB_OTG_DIEPCTL_SODDFRM_Msk (0x1U << USB_OTG_DIEPCTL_SODDFRM_Pos) /*!< 0x20000000 */
+#define USB_OTG_DIEPCTL_SODDFRM USB_OTG_DIEPCTL_SODDFRM_Msk /*!< Set odd frame */
+#define USB_OTG_DIEPCTL_EPDIS_Pos (30U)
+#define USB_OTG_DIEPCTL_EPDIS_Msk (0x1U << USB_OTG_DIEPCTL_EPDIS_Pos) /*!< 0x40000000 */
+#define USB_OTG_DIEPCTL_EPDIS USB_OTG_DIEPCTL_EPDIS_Msk /*!< Endpoint disable */
+#define USB_OTG_DIEPCTL_EPENA_Pos (31U)
+#define USB_OTG_DIEPCTL_EPENA_Msk (0x1U << USB_OTG_DIEPCTL_EPENA_Pos) /*!< 0x80000000 */
+#define USB_OTG_DIEPCTL_EPENA USB_OTG_DIEPCTL_EPENA_Msk /*!< Endpoint enable */
+
+/******************** Bit definition forUSB_OTG_HCCHAR register ******************/
+#define USB_OTG_HCCHAR_MPSIZ_Pos (0U)
+#define USB_OTG_HCCHAR_MPSIZ_Msk (0x7FFU << USB_OTG_HCCHAR_MPSIZ_Pos) /*!< 0x000007FF */
+#define USB_OTG_HCCHAR_MPSIZ USB_OTG_HCCHAR_MPSIZ_Msk /*!< Maximum packet size */
+
+#define USB_OTG_HCCHAR_EPNUM_Pos (11U)
+#define USB_OTG_HCCHAR_EPNUM_Msk (0xFU << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00007800 */
+#define USB_OTG_HCCHAR_EPNUM USB_OTG_HCCHAR_EPNUM_Msk /*!< Endpoint number */
+#define USB_OTG_HCCHAR_EPNUM_0 (0x1U << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00000800 */
+#define USB_OTG_HCCHAR_EPNUM_1 (0x2U << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00001000 */
+#define USB_OTG_HCCHAR_EPNUM_2 (0x4U << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00002000 */
+#define USB_OTG_HCCHAR_EPNUM_3 (0x8U << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00004000 */
+#define USB_OTG_HCCHAR_EPDIR_Pos (15U)
+#define USB_OTG_HCCHAR_EPDIR_Msk (0x1U << USB_OTG_HCCHAR_EPDIR_Pos) /*!< 0x00008000 */
+#define USB_OTG_HCCHAR_EPDIR USB_OTG_HCCHAR_EPDIR_Msk /*!< Endpoint direction */
+#define USB_OTG_HCCHAR_LSDEV_Pos (17U)
+#define USB_OTG_HCCHAR_LSDEV_Msk (0x1U << USB_OTG_HCCHAR_LSDEV_Pos) /*!< 0x00020000 */
+#define USB_OTG_HCCHAR_LSDEV USB_OTG_HCCHAR_LSDEV_Msk /*!< Low-speed device */
+
+#define USB_OTG_HCCHAR_EPTYP_Pos (18U)
+#define USB_OTG_HCCHAR_EPTYP_Msk (0x3U << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x000C0000 */
+#define USB_OTG_HCCHAR_EPTYP USB_OTG_HCCHAR_EPTYP_Msk /*!< Endpoint type */
+#define USB_OTG_HCCHAR_EPTYP_0 (0x1U << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00040000 */
+#define USB_OTG_HCCHAR_EPTYP_1 (0x2U << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00080000 */
+
+#define USB_OTG_HCCHAR_MC_Pos (20U)
+#define USB_OTG_HCCHAR_MC_Msk (0x3U << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00300000 */
+#define USB_OTG_HCCHAR_MC USB_OTG_HCCHAR_MC_Msk /*!< Multi Count (MC) / Error Count (EC) */
+#define USB_OTG_HCCHAR_MC_0 (0x1U << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00100000 */
+#define USB_OTG_HCCHAR_MC_1 (0x2U << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00200000 */
+
+#define USB_OTG_HCCHAR_DAD_Pos (22U)
+#define USB_OTG_HCCHAR_DAD_Msk (0x7FU << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x1FC00000 */
+#define USB_OTG_HCCHAR_DAD USB_OTG_HCCHAR_DAD_Msk /*!< Device address */
+#define USB_OTG_HCCHAR_DAD_0 (0x01U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00400000 */
+#define USB_OTG_HCCHAR_DAD_1 (0x02U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00800000 */
+#define USB_OTG_HCCHAR_DAD_2 (0x04U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x01000000 */
+#define USB_OTG_HCCHAR_DAD_3 (0x08U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x02000000 */
+#define USB_OTG_HCCHAR_DAD_4 (0x10U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x04000000 */
+#define USB_OTG_HCCHAR_DAD_5 (0x20U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x08000000 */
+#define USB_OTG_HCCHAR_DAD_6 (0x40U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x10000000 */
+#define USB_OTG_HCCHAR_ODDFRM_Pos (29U)
+#define USB_OTG_HCCHAR_ODDFRM_Msk (0x1U << USB_OTG_HCCHAR_ODDFRM_Pos) /*!< 0x20000000 */
+#define USB_OTG_HCCHAR_ODDFRM USB_OTG_HCCHAR_ODDFRM_Msk /*!< Odd frame */
+#define USB_OTG_HCCHAR_CHDIS_Pos (30U)
+#define USB_OTG_HCCHAR_CHDIS_Msk (0x1U << USB_OTG_HCCHAR_CHDIS_Pos) /*!< 0x40000000 */
+#define USB_OTG_HCCHAR_CHDIS USB_OTG_HCCHAR_CHDIS_Msk /*!< Channel disable */
+#define USB_OTG_HCCHAR_CHENA_Pos (31U)
+#define USB_OTG_HCCHAR_CHENA_Msk (0x1U << USB_OTG_HCCHAR_CHENA_Pos) /*!< 0x80000000 */
+#define USB_OTG_HCCHAR_CHENA USB_OTG_HCCHAR_CHENA_Msk /*!< Channel enable */
+
+/******************** Bit definition forUSB_OTG_HCSPLT register ******************/
+
+#define USB_OTG_HCSPLT_PRTADDR_Pos (0U)
+#define USB_OTG_HCSPLT_PRTADDR_Msk (0x7FU << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x0000007F */
+#define USB_OTG_HCSPLT_PRTADDR USB_OTG_HCSPLT_PRTADDR_Msk /*!< Port address */
+#define USB_OTG_HCSPLT_PRTADDR_0 (0x01U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000001 */
+#define USB_OTG_HCSPLT_PRTADDR_1 (0x02U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000002 */
+#define USB_OTG_HCSPLT_PRTADDR_2 (0x04U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000004 */
+#define USB_OTG_HCSPLT_PRTADDR_3 (0x08U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000008 */
+#define USB_OTG_HCSPLT_PRTADDR_4 (0x10U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000010 */
+#define USB_OTG_HCSPLT_PRTADDR_5 (0x20U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000020 */
+#define USB_OTG_HCSPLT_PRTADDR_6 (0x40U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000040 */
+
+#define USB_OTG_HCSPLT_HUBADDR_Pos (7U)
+#define USB_OTG_HCSPLT_HUBADDR_Msk (0x7FU << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00003F80 */
+#define USB_OTG_HCSPLT_HUBADDR USB_OTG_HCSPLT_HUBADDR_Msk /*!< Hub address */
+#define USB_OTG_HCSPLT_HUBADDR_0 (0x01U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000080 */
+#define USB_OTG_HCSPLT_HUBADDR_1 (0x02U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000100 */
+#define USB_OTG_HCSPLT_HUBADDR_2 (0x04U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000200 */
+#define USB_OTG_HCSPLT_HUBADDR_3 (0x08U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000400 */
+#define USB_OTG_HCSPLT_HUBADDR_4 (0x10U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000800 */
+#define USB_OTG_HCSPLT_HUBADDR_5 (0x20U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00001000 */
+#define USB_OTG_HCSPLT_HUBADDR_6 (0x40U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00002000 */
+
+#define USB_OTG_HCSPLT_XACTPOS_Pos (14U)
+#define USB_OTG_HCSPLT_XACTPOS_Msk (0x3U << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x0000C000 */
+#define USB_OTG_HCSPLT_XACTPOS USB_OTG_HCSPLT_XACTPOS_Msk /*!< XACTPOS */
+#define USB_OTG_HCSPLT_XACTPOS_0 (0x1U << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00004000 */
+#define USB_OTG_HCSPLT_XACTPOS_1 (0x2U << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00008000 */
+#define USB_OTG_HCSPLT_COMPLSPLT_Pos (16U)
+#define USB_OTG_HCSPLT_COMPLSPLT_Msk (0x1U << USB_OTG_HCSPLT_COMPLSPLT_Pos) /*!< 0x00010000 */
+#define USB_OTG_HCSPLT_COMPLSPLT USB_OTG_HCSPLT_COMPLSPLT_Msk /*!< Do complete split */
+#define USB_OTG_HCSPLT_SPLITEN_Pos (31U)
+#define USB_OTG_HCSPLT_SPLITEN_Msk (0x1U << USB_OTG_HCSPLT_SPLITEN_Pos) /*!< 0x80000000 */
+#define USB_OTG_HCSPLT_SPLITEN USB_OTG_HCSPLT_SPLITEN_Msk /*!< Split enable */
+
+/******************** Bit definition forUSB_OTG_HCINT register *******************/
+#define USB_OTG_HCINT_XFRC_Pos (0U)
+#define USB_OTG_HCINT_XFRC_Msk (0x1U << USB_OTG_HCINT_XFRC_Pos) /*!< 0x00000001 */
+#define USB_OTG_HCINT_XFRC USB_OTG_HCINT_XFRC_Msk /*!< Transfer completed */
+#define USB_OTG_HCINT_CHH_Pos (1U)
+#define USB_OTG_HCINT_CHH_Msk (0x1U << USB_OTG_HCINT_CHH_Pos) /*!< 0x00000002 */
+#define USB_OTG_HCINT_CHH USB_OTG_HCINT_CHH_Msk /*!< Channel halted */
+#define USB_OTG_HCINT_AHBERR_Pos (2U)
+#define USB_OTG_HCINT_AHBERR_Msk (0x1U << USB_OTG_HCINT_AHBERR_Pos) /*!< 0x00000004 */
+#define USB_OTG_HCINT_AHBERR USB_OTG_HCINT_AHBERR_Msk /*!< AHB error */
+#define USB_OTG_HCINT_STALL_Pos (3U)
+#define USB_OTG_HCINT_STALL_Msk (0x1U << USB_OTG_HCINT_STALL_Pos) /*!< 0x00000008 */
+#define USB_OTG_HCINT_STALL USB_OTG_HCINT_STALL_Msk /*!< STALL response received interrupt */
+#define USB_OTG_HCINT_NAK_Pos (4U)
+#define USB_OTG_HCINT_NAK_Msk (0x1U << USB_OTG_HCINT_NAK_Pos) /*!< 0x00000010 */
+#define USB_OTG_HCINT_NAK USB_OTG_HCINT_NAK_Msk /*!< NAK response received interrupt */
+#define USB_OTG_HCINT_ACK_Pos (5U)
+#define USB_OTG_HCINT_ACK_Msk (0x1U << USB_OTG_HCINT_ACK_Pos) /*!< 0x00000020 */
+#define USB_OTG_HCINT_ACK USB_OTG_HCINT_ACK_Msk /*!< ACK response received/transmitted interrupt */
+#define USB_OTG_HCINT_NYET_Pos (6U)
+#define USB_OTG_HCINT_NYET_Msk (0x1U << USB_OTG_HCINT_NYET_Pos) /*!< 0x00000040 */
+#define USB_OTG_HCINT_NYET USB_OTG_HCINT_NYET_Msk /*!< Response received interrupt */
+#define USB_OTG_HCINT_TXERR_Pos (7U)
+#define USB_OTG_HCINT_TXERR_Msk (0x1U << USB_OTG_HCINT_TXERR_Pos) /*!< 0x00000080 */
+#define USB_OTG_HCINT_TXERR USB_OTG_HCINT_TXERR_Msk /*!< Transaction error */
+#define USB_OTG_HCINT_BBERR_Pos (8U)
+#define USB_OTG_HCINT_BBERR_Msk (0x1U << USB_OTG_HCINT_BBERR_Pos) /*!< 0x00000100 */
+#define USB_OTG_HCINT_BBERR USB_OTG_HCINT_BBERR_Msk /*!< Babble error */
+#define USB_OTG_HCINT_FRMOR_Pos (9U)
+#define USB_OTG_HCINT_FRMOR_Msk (0x1U << USB_OTG_HCINT_FRMOR_Pos) /*!< 0x00000200 */
+#define USB_OTG_HCINT_FRMOR USB_OTG_HCINT_FRMOR_Msk /*!< Frame overrun */
+#define USB_OTG_HCINT_DTERR_Pos (10U)
+#define USB_OTG_HCINT_DTERR_Msk (0x1U << USB_OTG_HCINT_DTERR_Pos) /*!< 0x00000400 */
+#define USB_OTG_HCINT_DTERR USB_OTG_HCINT_DTERR_Msk /*!< Data toggle error */
+
+/******************** Bit definition forUSB_OTG_DIEPINT register *****************/
+#define USB_OTG_DIEPINT_XFRC_Pos (0U)
+#define USB_OTG_DIEPINT_XFRC_Msk (0x1U << USB_OTG_DIEPINT_XFRC_Pos) /*!< 0x00000001 */
+#define USB_OTG_DIEPINT_XFRC USB_OTG_DIEPINT_XFRC_Msk /*!< Transfer completed interrupt */
+#define USB_OTG_DIEPINT_EPDISD_Pos (1U)
+#define USB_OTG_DIEPINT_EPDISD_Msk (0x1U << USB_OTG_DIEPINT_EPDISD_Pos) /*!< 0x00000002 */
+#define USB_OTG_DIEPINT_EPDISD USB_OTG_DIEPINT_EPDISD_Msk /*!< Endpoint disabled interrupt */
+#define USB_OTG_DIEPINT_TOC_Pos (3U)
+#define USB_OTG_DIEPINT_TOC_Msk (0x1U << USB_OTG_DIEPINT_TOC_Pos) /*!< 0x00000008 */
+#define USB_OTG_DIEPINT_TOC USB_OTG_DIEPINT_TOC_Msk /*!< Timeout condition */
+#define USB_OTG_DIEPINT_ITTXFE_Pos (4U)
+#define USB_OTG_DIEPINT_ITTXFE_Msk (0x1U << USB_OTG_DIEPINT_ITTXFE_Pos) /*!< 0x00000010 */
+#define USB_OTG_DIEPINT_ITTXFE USB_OTG_DIEPINT_ITTXFE_Msk /*!< IN token received when TxFIFO is empty */
+#define USB_OTG_DIEPINT_INEPNE_Pos (6U)
+#define USB_OTG_DIEPINT_INEPNE_Msk (0x1U << USB_OTG_DIEPINT_INEPNE_Pos) /*!< 0x00000040 */
+#define USB_OTG_DIEPINT_INEPNE USB_OTG_DIEPINT_INEPNE_Msk /*!< IN endpoint NAK effective */
+#define USB_OTG_DIEPINT_TXFE_Pos (7U)
+#define USB_OTG_DIEPINT_TXFE_Msk (0x1U << USB_OTG_DIEPINT_TXFE_Pos) /*!< 0x00000080 */
+#define USB_OTG_DIEPINT_TXFE USB_OTG_DIEPINT_TXFE_Msk /*!< Transmit FIFO empty */
+#define USB_OTG_DIEPINT_TXFIFOUDRN_Pos (8U)
+#define USB_OTG_DIEPINT_TXFIFOUDRN_Msk (0x1U << USB_OTG_DIEPINT_TXFIFOUDRN_Pos) /*!< 0x00000100 */
+#define USB_OTG_DIEPINT_TXFIFOUDRN USB_OTG_DIEPINT_TXFIFOUDRN_Msk /*!< Transmit Fifo Underrun */
+#define USB_OTG_DIEPINT_BNA_Pos (9U)
+#define USB_OTG_DIEPINT_BNA_Msk (0x1U << USB_OTG_DIEPINT_BNA_Pos) /*!< 0x00000200 */
+#define USB_OTG_DIEPINT_BNA USB_OTG_DIEPINT_BNA_Msk /*!< Buffer not available interrupt */
+#define USB_OTG_DIEPINT_PKTDRPSTS_Pos (11U)
+#define USB_OTG_DIEPINT_PKTDRPSTS_Msk (0x1U << USB_OTG_DIEPINT_PKTDRPSTS_Pos) /*!< 0x00000800 */
+#define USB_OTG_DIEPINT_PKTDRPSTS USB_OTG_DIEPINT_PKTDRPSTS_Msk /*!< Packet dropped status */
+#define USB_OTG_DIEPINT_BERR_Pos (12U)
+#define USB_OTG_DIEPINT_BERR_Msk (0x1U << USB_OTG_DIEPINT_BERR_Pos) /*!< 0x00001000 */
+#define USB_OTG_DIEPINT_BERR USB_OTG_DIEPINT_BERR_Msk /*!< Babble error interrupt */
+#define USB_OTG_DIEPINT_NAK_Pos (13U)
+#define USB_OTG_DIEPINT_NAK_Msk (0x1U << USB_OTG_DIEPINT_NAK_Pos) /*!< 0x00002000 */
+#define USB_OTG_DIEPINT_NAK USB_OTG_DIEPINT_NAK_Msk /*!< NAK interrupt */
+
+/******************** Bit definition forUSB_OTG_HCINTMSK register ****************/
+#define USB_OTG_HCINTMSK_XFRCM_Pos (0U)
+#define USB_OTG_HCINTMSK_XFRCM_Msk (0x1U << USB_OTG_HCINTMSK_XFRCM_Pos) /*!< 0x00000001 */
+#define USB_OTG_HCINTMSK_XFRCM USB_OTG_HCINTMSK_XFRCM_Msk /*!< Transfer completed mask */
+#define USB_OTG_HCINTMSK_CHHM_Pos (1U)
+#define USB_OTG_HCINTMSK_CHHM_Msk (0x1U << USB_OTG_HCINTMSK_CHHM_Pos) /*!< 0x00000002 */
+#define USB_OTG_HCINTMSK_CHHM USB_OTG_HCINTMSK_CHHM_Msk /*!< Channel halted mask */
+#define USB_OTG_HCINTMSK_AHBERR_Pos (2U)
+#define USB_OTG_HCINTMSK_AHBERR_Msk (0x1U << USB_OTG_HCINTMSK_AHBERR_Pos) /*!< 0x00000004 */
+#define USB_OTG_HCINTMSK_AHBERR USB_OTG_HCINTMSK_AHBERR_Msk /*!< AHB error */
+#define USB_OTG_HCINTMSK_STALLM_Pos (3U)
+#define USB_OTG_HCINTMSK_STALLM_Msk (0x1U << USB_OTG_HCINTMSK_STALLM_Pos) /*!< 0x00000008 */
+#define USB_OTG_HCINTMSK_STALLM USB_OTG_HCINTMSK_STALLM_Msk /*!< STALL response received interrupt mask */
+#define USB_OTG_HCINTMSK_NAKM_Pos (4U)
+#define USB_OTG_HCINTMSK_NAKM_Msk (0x1U << USB_OTG_HCINTMSK_NAKM_Pos) /*!< 0x00000010 */
+#define USB_OTG_HCINTMSK_NAKM USB_OTG_HCINTMSK_NAKM_Msk /*!< NAK response received interrupt mask */
+#define USB_OTG_HCINTMSK_ACKM_Pos (5U)
+#define USB_OTG_HCINTMSK_ACKM_Msk (0x1U << USB_OTG_HCINTMSK_ACKM_Pos) /*!< 0x00000020 */
+#define USB_OTG_HCINTMSK_ACKM USB_OTG_HCINTMSK_ACKM_Msk /*!< ACK response received/transmitted interrupt mask */
+#define USB_OTG_HCINTMSK_NYET_Pos (6U)
+#define USB_OTG_HCINTMSK_NYET_Msk (0x1U << USB_OTG_HCINTMSK_NYET_Pos) /*!< 0x00000040 */
+#define USB_OTG_HCINTMSK_NYET USB_OTG_HCINTMSK_NYET_Msk /*!< response received interrupt mask */
+#define USB_OTG_HCINTMSK_TXERRM_Pos (7U)
+#define USB_OTG_HCINTMSK_TXERRM_Msk (0x1U << USB_OTG_HCINTMSK_TXERRM_Pos) /*!< 0x00000080 */
+#define USB_OTG_HCINTMSK_TXERRM USB_OTG_HCINTMSK_TXERRM_Msk /*!< Transaction error mask */
+#define USB_OTG_HCINTMSK_BBERRM_Pos (8U)
+#define USB_OTG_HCINTMSK_BBERRM_Msk (0x1U << USB_OTG_HCINTMSK_BBERRM_Pos) /*!< 0x00000100 */
+#define USB_OTG_HCINTMSK_BBERRM USB_OTG_HCINTMSK_BBERRM_Msk /*!< Babble error mask */
+#define USB_OTG_HCINTMSK_FRMORM_Pos (9U)
+#define USB_OTG_HCINTMSK_FRMORM_Msk (0x1U << USB_OTG_HCINTMSK_FRMORM_Pos) /*!< 0x00000200 */
+#define USB_OTG_HCINTMSK_FRMORM USB_OTG_HCINTMSK_FRMORM_Msk /*!< Frame overrun mask */
+#define USB_OTG_HCINTMSK_DTERRM_Pos (10U)
+#define USB_OTG_HCINTMSK_DTERRM_Msk (0x1U << USB_OTG_HCINTMSK_DTERRM_Pos) /*!< 0x00000400 */
+#define USB_OTG_HCINTMSK_DTERRM USB_OTG_HCINTMSK_DTERRM_Msk /*!< Data toggle error mask */
+
+/******************** Bit definition for USB_OTG_DIEPTSIZ register ***************/
+#define USB_OTG_DIEPTSIZ_XFRSIZ_Pos (0U)
+#define USB_OTG_DIEPTSIZ_XFRSIZ_Msk (0x7FFFFU << USB_OTG_DIEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
+#define USB_OTG_DIEPTSIZ_XFRSIZ USB_OTG_DIEPTSIZ_XFRSIZ_Msk /*!< Transfer size */
+#define USB_OTG_DIEPTSIZ_PKTCNT_Pos (19U)
+#define USB_OTG_DIEPTSIZ_PKTCNT_Msk (0x3FFU << USB_OTG_DIEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
+#define USB_OTG_DIEPTSIZ_PKTCNT USB_OTG_DIEPTSIZ_PKTCNT_Msk /*!< Packet count */
+#define USB_OTG_DIEPTSIZ_MULCNT_Pos (29U)
+#define USB_OTG_DIEPTSIZ_MULCNT_Msk (0x3U << USB_OTG_DIEPTSIZ_MULCNT_Pos) /*!< 0x60000000 */
+#define USB_OTG_DIEPTSIZ_MULCNT USB_OTG_DIEPTSIZ_MULCNT_Msk /*!< Packet count */
+
+/******************** Bit definition forUSB_OTG_HCTSIZ register ******************/
+#define USB_OTG_HCTSIZ_XFRSIZ_Pos (0U)
+#define USB_OTG_HCTSIZ_XFRSIZ_Msk (0x7FFFFU << USB_OTG_HCTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
+#define USB_OTG_HCTSIZ_XFRSIZ USB_OTG_HCTSIZ_XFRSIZ_Msk /*!< Transfer size */
+#define USB_OTG_HCTSIZ_PKTCNT_Pos (19U)
+#define USB_OTG_HCTSIZ_PKTCNT_Msk (0x3FFU << USB_OTG_HCTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
+#define USB_OTG_HCTSIZ_PKTCNT USB_OTG_HCTSIZ_PKTCNT_Msk /*!< Packet count */
+#define USB_OTG_HCTSIZ_DOPING_Pos (31U)
+#define USB_OTG_HCTSIZ_DOPING_Msk (0x1U << USB_OTG_HCTSIZ_DOPING_Pos) /*!< 0x80000000 */
+#define USB_OTG_HCTSIZ_DOPING USB_OTG_HCTSIZ_DOPING_Msk /*!< Do PING */
+#define USB_OTG_HCTSIZ_DPID_Pos (29U)
+#define USB_OTG_HCTSIZ_DPID_Msk (0x3U << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x60000000 */
+#define USB_OTG_HCTSIZ_DPID USB_OTG_HCTSIZ_DPID_Msk /*!< Data PID */
+#define USB_OTG_HCTSIZ_DPID_0 (0x1U << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x20000000 */
+#define USB_OTG_HCTSIZ_DPID_1 (0x2U << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x40000000 */
+
+/******************** Bit definition forUSB_OTG_DIEPDMA register *****************/
+#define USB_OTG_DIEPDMA_DMAADDR_Pos (0U)
+#define USB_OTG_DIEPDMA_DMAADDR_Msk (0xFFFFFFFFU << USB_OTG_DIEPDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */
+#define USB_OTG_DIEPDMA_DMAADDR USB_OTG_DIEPDMA_DMAADDR_Msk /*!< DMA address */
+
+/******************** Bit definition forUSB_OTG_HCDMA register *******************/
+#define USB_OTG_HCDMA_DMAADDR_Pos (0U)
+#define USB_OTG_HCDMA_DMAADDR_Msk (0xFFFFFFFFU << USB_OTG_HCDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */
+#define USB_OTG_HCDMA_DMAADDR USB_OTG_HCDMA_DMAADDR_Msk /*!< DMA address */
+
+/******************** Bit definition forUSB_OTG_DTXFSTS register *****************/
+#define USB_OTG_DTXFSTS_INEPTFSAV_Pos (0U)
+#define USB_OTG_DTXFSTS_INEPTFSAV_Msk (0xFFFFU << USB_OTG_DTXFSTS_INEPTFSAV_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_DTXFSTS_INEPTFSAV USB_OTG_DTXFSTS_INEPTFSAV_Msk /*!< IN endpoint TxFIFO space avail */
+
+/******************** Bit definition forUSB_OTG_DIEPTXF register *****************/
+#define USB_OTG_DIEPTXF_INEPTXSA_Pos (0U)
+#define USB_OTG_DIEPTXF_INEPTXSA_Msk (0xFFFFU << USB_OTG_DIEPTXF_INEPTXSA_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_DIEPTXF_INEPTXSA USB_OTG_DIEPTXF_INEPTXSA_Msk /*!< IN endpoint FIFOx transmit RAM start address */
+#define USB_OTG_DIEPTXF_INEPTXFD_Pos (16U)
+#define USB_OTG_DIEPTXF_INEPTXFD_Msk (0xFFFFU << USB_OTG_DIEPTXF_INEPTXFD_Pos) /*!< 0xFFFF0000 */
+#define USB_OTG_DIEPTXF_INEPTXFD USB_OTG_DIEPTXF_INEPTXFD_Msk /*!< IN endpoint TxFIFO depth */
+
+/******************** Bit definition forUSB_OTG_DOEPCTL register *****************/
+#define USB_OTG_DOEPCTL_MPSIZ_Pos (0U)
+#define USB_OTG_DOEPCTL_MPSIZ_Msk (0x7FFU << USB_OTG_DOEPCTL_MPSIZ_Pos) /*!< 0x000007FF */
+#define USB_OTG_DOEPCTL_MPSIZ USB_OTG_DOEPCTL_MPSIZ_Msk /*!< Maximum packet size */
+#define USB_OTG_DOEPCTL_USBAEP_Pos (15U)
+#define USB_OTG_DOEPCTL_USBAEP_Msk (0x1U << USB_OTG_DOEPCTL_USBAEP_Pos) /*!< 0x00008000 */
+#define USB_OTG_DOEPCTL_USBAEP USB_OTG_DOEPCTL_USBAEP_Msk /*!< USB active endpoint */
+#define USB_OTG_DOEPCTL_NAKSTS_Pos (17U)
+#define USB_OTG_DOEPCTL_NAKSTS_Msk (0x1U << USB_OTG_DOEPCTL_NAKSTS_Pos) /*!< 0x00020000 */
+#define USB_OTG_DOEPCTL_NAKSTS USB_OTG_DOEPCTL_NAKSTS_Msk /*!< NAK status */
+#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos (28U)
+#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk (0x1U << USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */
+#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */
+#define USB_OTG_DOEPCTL_SODDFRM_Pos (29U)
+#define USB_OTG_DOEPCTL_SODDFRM_Msk (0x1U << USB_OTG_DOEPCTL_SODDFRM_Pos) /*!< 0x20000000 */
+#define USB_OTG_DOEPCTL_SODDFRM USB_OTG_DOEPCTL_SODDFRM_Msk /*!< Set odd frame */
+#define USB_OTG_DOEPCTL_EPTYP_Pos (18U)
+#define USB_OTG_DOEPCTL_EPTYP_Msk (0x3U << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x000C0000 */
+#define USB_OTG_DOEPCTL_EPTYP USB_OTG_DOEPCTL_EPTYP_Msk /*!< Endpoint type */
+#define USB_OTG_DOEPCTL_EPTYP_0 (0x1U << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x00040000 */
+#define USB_OTG_DOEPCTL_EPTYP_1 (0x2U << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x00080000 */
+#define USB_OTG_DOEPCTL_SNPM_Pos (20U)
+#define USB_OTG_DOEPCTL_SNPM_Msk (0x1U << USB_OTG_DOEPCTL_SNPM_Pos) /*!< 0x00100000 */
+#define USB_OTG_DOEPCTL_SNPM USB_OTG_DOEPCTL_SNPM_Msk /*!< Snoop mode */
+#define USB_OTG_DOEPCTL_STALL_Pos (21U)
+#define USB_OTG_DOEPCTL_STALL_Msk (0x1U << USB_OTG_DOEPCTL_STALL_Pos) /*!< 0x00200000 */
+#define USB_OTG_DOEPCTL_STALL USB_OTG_DOEPCTL_STALL_Msk /*!< STALL handshake */
+#define USB_OTG_DOEPCTL_CNAK_Pos (26U)
+#define USB_OTG_DOEPCTL_CNAK_Msk (0x1U << USB_OTG_DOEPCTL_CNAK_Pos) /*!< 0x04000000 */
+#define USB_OTG_DOEPCTL_CNAK USB_OTG_DOEPCTL_CNAK_Msk /*!< Clear NAK */
+#define USB_OTG_DOEPCTL_SNAK_Pos (27U)
+#define USB_OTG_DOEPCTL_SNAK_Msk (0x1U << USB_OTG_DOEPCTL_SNAK_Pos) /*!< 0x08000000 */
+#define USB_OTG_DOEPCTL_SNAK USB_OTG_DOEPCTL_SNAK_Msk /*!< Set NAK */
+#define USB_OTG_DOEPCTL_EPDIS_Pos (30U)
+#define USB_OTG_DOEPCTL_EPDIS_Msk (0x1U << USB_OTG_DOEPCTL_EPDIS_Pos) /*!< 0x40000000 */
+#define USB_OTG_DOEPCTL_EPDIS USB_OTG_DOEPCTL_EPDIS_Msk /*!< Endpoint disable */
+#define USB_OTG_DOEPCTL_EPENA_Pos (31U)
+#define USB_OTG_DOEPCTL_EPENA_Msk (0x1U << USB_OTG_DOEPCTL_EPENA_Pos) /*!< 0x80000000 */
+#define USB_OTG_DOEPCTL_EPENA USB_OTG_DOEPCTL_EPENA_Msk /*!< Endpoint enable */
+
+/******************** Bit definition forUSB_OTG_DOEPINT register *****************/
+#define USB_OTG_DOEPINT_XFRC_Pos (0U)
+#define USB_OTG_DOEPINT_XFRC_Msk (0x1U << USB_OTG_DOEPINT_XFRC_Pos) /*!< 0x00000001 */
+#define USB_OTG_DOEPINT_XFRC USB_OTG_DOEPINT_XFRC_Msk /*!< Transfer completed interrupt */
+#define USB_OTG_DOEPINT_EPDISD_Pos (1U)
+#define USB_OTG_DOEPINT_EPDISD_Msk (0x1U << USB_OTG_DOEPINT_EPDISD_Pos) /*!< 0x00000002 */
+#define USB_OTG_DOEPINT_EPDISD USB_OTG_DOEPINT_EPDISD_Msk /*!< Endpoint disabled interrupt */
+#define USB_OTG_DOEPINT_STUP_Pos (3U)
+#define USB_OTG_DOEPINT_STUP_Msk (0x1U << USB_OTG_DOEPINT_STUP_Pos) /*!< 0x00000008 */
+#define USB_OTG_DOEPINT_STUP USB_OTG_DOEPINT_STUP_Msk /*!< SETUP phase done */
+#define USB_OTG_DOEPINT_OTEPDIS_Pos (4U)
+#define USB_OTG_DOEPINT_OTEPDIS_Msk (0x1U << USB_OTG_DOEPINT_OTEPDIS_Pos) /*!< 0x00000010 */
+#define USB_OTG_DOEPINT_OTEPDIS USB_OTG_DOEPINT_OTEPDIS_Msk /*!< OUT token received when endpoint disabled */
+#define USB_OTG_DOEPINT_B2BSTUP_Pos (6U)
+#define USB_OTG_DOEPINT_B2BSTUP_Msk (0x1U << USB_OTG_DOEPINT_B2BSTUP_Pos) /*!< 0x00000040 */
+#define USB_OTG_DOEPINT_B2BSTUP USB_OTG_DOEPINT_B2BSTUP_Msk /*!< Back-to-back SETUP packets received */
+#define USB_OTG_DOEPINT_NYET_Pos (14U)
+#define USB_OTG_DOEPINT_NYET_Msk (0x1U << USB_OTG_DOEPINT_NYET_Pos) /*!< 0x00004000 */
+#define USB_OTG_DOEPINT_NYET USB_OTG_DOEPINT_NYET_Msk /*!< NYET interrupt */
+
+/******************** Bit definition forUSB_OTG_DOEPTSIZ register ****************/
+#define USB_OTG_DOEPTSIZ_XFRSIZ_Pos (0U)
+#define USB_OTG_DOEPTSIZ_XFRSIZ_Msk (0x7FFFFU << USB_OTG_DOEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
+#define USB_OTG_DOEPTSIZ_XFRSIZ USB_OTG_DOEPTSIZ_XFRSIZ_Msk /*!< Transfer size */
+#define USB_OTG_DOEPTSIZ_PKTCNT_Pos (19U)
+#define USB_OTG_DOEPTSIZ_PKTCNT_Msk (0x3FFU << USB_OTG_DOEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
+#define USB_OTG_DOEPTSIZ_PKTCNT USB_OTG_DOEPTSIZ_PKTCNT_Msk /*!< Packet count */
+
+#define USB_OTG_DOEPTSIZ_STUPCNT_Pos (29U)
+#define USB_OTG_DOEPTSIZ_STUPCNT_Msk (0x3U << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x60000000 */
+#define USB_OTG_DOEPTSIZ_STUPCNT USB_OTG_DOEPTSIZ_STUPCNT_Msk /*!< SETUP packet count */
+#define USB_OTG_DOEPTSIZ_STUPCNT_0 (0x1U << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x20000000 */
+#define USB_OTG_DOEPTSIZ_STUPCNT_1 (0x2U << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x40000000 */
+
+/******************** Bit definition for PCGCCTL register ************************/
+#define USB_OTG_PCGCCTL_STOPCLK_Pos (0U)
+#define USB_OTG_PCGCCTL_STOPCLK_Msk (0x1U << USB_OTG_PCGCCTL_STOPCLK_Pos) /*!< 0x00000001 */
+#define USB_OTG_PCGCCTL_STOPCLK USB_OTG_PCGCCTL_STOPCLK_Msk /*!< SETUP packet count */
+#define USB_OTG_PCGCCTL_GATECLK_Pos (1U)
+#define USB_OTG_PCGCCTL_GATECLK_Msk (0x1U << USB_OTG_PCGCCTL_GATECLK_Pos) /*!< 0x00000002 */
+#define USB_OTG_PCGCCTL_GATECLK USB_OTG_PCGCCTL_GATECLK_Msk /*!<Bit 0 */
+#define USB_OTG_PCGCCTL_PHYSUSP_Pos (4U)
+#define USB_OTG_PCGCCTL_PHYSUSP_Msk (0x1U << USB_OTG_PCGCCTL_PHYSUSP_Pos) /*!< 0x00000010 */
+#define USB_OTG_PCGCCTL_PHYSUSP USB_OTG_PCGCCTL_PHYSUSP_Msk /*!<Bit 1 */
+
+/**
+ * @}
+*/
+
+/**
+ * @}
+*/
+
+/** @addtogroup Exported_macro
+ * @{
+ */
+
+/****************************** ADC Instances *********************************/
+#define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) || \
+ ((INSTANCE) == ADC2))
+
+#define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC12_COMMON)
+
+#define IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
+
+#define IS_ADC_DMA_CAPABILITY_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
+
+/****************************** CAN Instances *********************************/
+#define IS_CAN_ALL_INSTANCE(INSTANCE) (((INSTANCE) == CAN1) || \
+ ((INSTANCE) == CAN2))
+
+/****************************** CRC Instances *********************************/
+#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
+
+/****************************** DAC Instances *********************************/
+#define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC)
+
+/****************************** DMA Instances *********************************/
+#define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \
+ ((INSTANCE) == DMA1_Channel2) || \
+ ((INSTANCE) == DMA1_Channel3) || \
+ ((INSTANCE) == DMA1_Channel4) || \
+ ((INSTANCE) == DMA1_Channel5) || \
+ ((INSTANCE) == DMA1_Channel6) || \
+ ((INSTANCE) == DMA1_Channel7) || \
+ ((INSTANCE) == DMA2_Channel1) || \
+ ((INSTANCE) == DMA2_Channel2) || \
+ ((INSTANCE) == DMA2_Channel3) || \
+ ((INSTANCE) == DMA2_Channel4) || \
+ ((INSTANCE) == DMA2_Channel5))
+
+/******************************* GPIO Instances *******************************/
+#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
+ ((INSTANCE) == GPIOB) || \
+ ((INSTANCE) == GPIOC) || \
+ ((INSTANCE) == GPIOD) || \
+ ((INSTANCE) == GPIOE))
+
+/**************************** GPIO Alternate Function Instances ***************/
+#define IS_GPIO_AF_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
+
+/**************************** GPIO Lock Instances *****************************/
+#define IS_GPIO_LOCK_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
+
+/******************************** I2C Instances *******************************/
+#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
+ ((INSTANCE) == I2C2))
+
+/******************************** I2S Instances *******************************/
+#define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI2) || \
+ ((INSTANCE) == SPI3))
+
+/****************************** IWDG Instances ********************************/
+#define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
+
+/******************************** SPI Instances *******************************/
+#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
+ ((INSTANCE) == SPI2) || \
+ ((INSTANCE) == SPI3))
+
+/****************************** START TIM Instances ***************************/
+/****************************** TIM Instances *********************************/
+#define IS_TIM_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM6) || \
+ ((INSTANCE) == TIM7))
+
+#define IS_TIM_CC1_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5))
+
+#define IS_TIM_CC2_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5))
+
+#define IS_TIM_CC3_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5))
+
+#define IS_TIM_CC4_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5))
+
+#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5))
+
+#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5))
+
+#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5))
+
+#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5))
+
+#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5))
+
+#define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5))
+
+#define IS_TIM_XOR_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5))
+
+#define IS_TIM_MASTER_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM6) || \
+ ((INSTANCE) == TIM7))
+
+#define IS_TIM_SLAVE_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5))
+
+#define IS_TIM_DMABURST_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5))
+
+#define IS_TIM_BREAK_INSTANCE(INSTANCE)\
+ ((INSTANCE) == TIM1)
+
+#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
+ ((((INSTANCE) == TIM1) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM2) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM3) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM4) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM5) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))))
+
+#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
+ (((INSTANCE) == TIM1) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3)))
+
+#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5))
+
+#define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE)\
+ ((INSTANCE) == TIM1)
+
+#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5))
+
+#define IS_TIM_DMA_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM6) || \
+ ((INSTANCE) == TIM7))
+
+#define IS_TIM_DMA_CC_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5))
+
+#define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE)\
+ ((INSTANCE) == TIM1)
+
+/****************************** END TIM Instances *****************************/
+
+
+/******************** USART Instances : Synchronous mode **********************/
+#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3))
+
+/******************** UART Instances : Asynchronous mode **********************/
+#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3) || \
+ ((INSTANCE) == UART4) || \
+ ((INSTANCE) == UART5))
+
+/******************** UART Instances : Half-Duplex mode **********************/
+#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3) || \
+ ((INSTANCE) == UART4) || \
+ ((INSTANCE) == UART5))
+
+/******************** UART Instances : LIN mode **********************/
+#define IS_UART_LIN_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3) || \
+ ((INSTANCE) == UART4) || \
+ ((INSTANCE) == UART5))
+
+/****************** UART Instances : Hardware Flow control ********************/
+#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3))
+
+/********************* UART Instances : Smard card mode ***********************/
+#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3))
+
+/*********************** UART Instances : IRDA mode ***************************/
+#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3) || \
+ ((INSTANCE) == UART4) || \
+ ((INSTANCE) == UART5))
+
+/***************** UART Instances : Multi-Processor mode **********************/
+#define IS_UART_MULTIPROCESSOR_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3) || \
+ ((INSTANCE) == UART4) || \
+ ((INSTANCE) == UART5))
+
+/***************** UART Instances : DMA mode available **********************/
+#define IS_UART_DMA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3) || \
+ ((INSTANCE) == UART4))
+
+/****************************** RTC Instances *********************************/
+#define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
+
+/**************************** WWDG Instances *****************************/
+#define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
+
+
+/****************************** USB Instances ********************************/
+#define IS_USB_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB_OTG_FS)
+
+/****************************** USB Instances ********************************/
+#define IS_ETH_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ETH)
+
+
+/**
+ * @}
+*/
+/******************************************************************************/
+/* For a painless codes migration between the STM32F1xx device product */
+/* lines, the aliases defined below are put in place to overcome the */
+/* differences in the interrupt handlers and IRQn definitions. */
+/* No need to update developed interrupt code when moving across */
+/* product lines within the same STM32F1 Family */
+/******************************************************************************/
+
+/* Aliases for __IRQn */
+#define ADC1_IRQn ADC1_2_IRQn
+#define USB_LP_IRQn CAN1_RX0_IRQn
+#define USB_LP_CAN1_RX0_IRQn CAN1_RX0_IRQn
+#define USB_HP_CAN1_TX_IRQn CAN1_TX_IRQn
+#define USB_HP_IRQn CAN1_TX_IRQn
+#define DMA2_Channel4_5_IRQn DMA2_Channel4_IRQn
+#define USBWakeUp_IRQn OTG_FS_WKUP_IRQn
+#define CEC_IRQn OTG_FS_WKUP_IRQn
+#define TIM1_BRK_TIM15_IRQn TIM1_BRK_IRQn
+#define TIM1_BRK_TIM9_IRQn TIM1_BRK_IRQn
+#define TIM9_IRQn TIM1_BRK_IRQn
+#define TIM1_TRG_COM_TIM11_IRQn TIM1_TRG_COM_IRQn
+#define TIM1_TRG_COM_TIM17_IRQn TIM1_TRG_COM_IRQn
+#define TIM11_IRQn TIM1_TRG_COM_IRQn
+#define TIM10_IRQn TIM1_UP_IRQn
+#define TIM1_UP_TIM16_IRQn TIM1_UP_IRQn
+#define TIM1_UP_TIM10_IRQn TIM1_UP_IRQn
+#define TIM6_DAC_IRQn TIM6_IRQn
+
+
+/* Aliases for __IRQHandler */
+#define ADC1_IRQHandler ADC1_2_IRQHandler
+#define USB_LP_IRQHandler CAN1_RX0_IRQHandler
+#define USB_LP_CAN1_RX0_IRQHandler CAN1_RX0_IRQHandler
+#define USB_HP_CAN1_TX_IRQHandler CAN1_TX_IRQHandler
+#define USB_HP_IRQHandler CAN1_TX_IRQHandler
+#define DMA2_Channel4_5_IRQHandler DMA2_Channel4_IRQHandler
+#define USBWakeUp_IRQHandler OTG_FS_WKUP_IRQHandler
+#define CEC_IRQHandler OTG_FS_WKUP_IRQHandler
+#define TIM1_BRK_TIM15_IRQHandler TIM1_BRK_IRQHandler
+#define TIM1_BRK_TIM9_IRQHandler TIM1_BRK_IRQHandler
+#define TIM9_IRQHandler TIM1_BRK_IRQHandler
+#define TIM1_TRG_COM_TIM11_IRQHandler TIM1_TRG_COM_IRQHandler
+#define TIM1_TRG_COM_TIM17_IRQHandler TIM1_TRG_COM_IRQHandler
+#define TIM11_IRQHandler TIM1_TRG_COM_IRQHandler
+#define TIM10_IRQHandler TIM1_UP_IRQHandler
+#define TIM1_UP_TIM16_IRQHandler TIM1_UP_IRQHandler
+#define TIM1_UP_TIM10_IRQHandler TIM1_UP_IRQHandler
+#define TIM6_DAC_IRQHandler TIM6_IRQHandler
+
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+
+#ifdef __cplusplus
+ }
+#endif /* __cplusplus */
+
+#endif /* __STM32F107xC_H */
+
+
+
+ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Device/ST/STM32F1xx/Include/stm32f1xx.h b/Device/ST/STM32F1xx/Include/stm32f1xx.h
new file mode 100644
index 0000000..233d1b3
--- /dev/null
+++ b/Device/ST/STM32F1xx/Include/stm32f1xx.h
@@ -0,0 +1,238 @@
+/**
+ ******************************************************************************
+ * @file stm32f1xx.h
+ * @author MCD Application Team
+ * @version V4.1.0
+ * @date 29-April-2016
+ * @brief CMSIS STM32F1xx Device Peripheral Access Layer Header File.
+ *
+ * The file is the unique include file that the application programmer
+ * is using in the C source code, usually in main.c. This file contains:
+ * - Configuration section that allows to select:
+ * - The STM32F1xx device used in the target application
+ * - To use or not the peripheral’s drivers in application code(i.e.
+ * code will be based on direct access to peripheral’s registers
+ * rather than drivers API), this option is controlled by
+ * "#define USE_HAL_DRIVER"
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/** @addtogroup CMSIS
+ * @{
+ */
+
+/** @addtogroup stm32f1xx
+ * @{
+ */
+
+#ifndef __STM32F1XX_H
+#define __STM32F1XX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif /* __cplusplus */
+
+/** @addtogroup Library_configuration_section
+ * @{
+ */
+
+/**
+ * @brief STM32 Family
+ */
+#if !defined (STM32F1)
+#define STM32F1
+#endif /* STM32F1 */
+
+/* Uncomment the line below according to the target STM32L device used in your
+ application
+ */
+
+#if !defined (STM32F100xB) && !defined (STM32F100xE) && !defined (STM32F101x6) && \
+ !defined (STM32F101xB) && !defined (STM32F101xE) && !defined (STM32F101xG) && !defined (STM32F102x6) && !defined (STM32F102xB) && !defined (STM32F103x6) && \
+ !defined (STM32F103xB) && !defined (STM32F103xE) && !defined (STM32F103xG) && !defined (STM32F105xC) && !defined (STM32F107xC)
+ /* #define STM32F100xB */ /*!< STM32F100C4, STM32F100R4, STM32F100C6, STM32F100R6, STM32F100C8, STM32F100R8, STM32F100V8, STM32F100CB, STM32F100RB and STM32F100VB */
+ /* #define STM32F100xE */ /*!< STM32F100RC, STM32F100VC, STM32F100ZC, STM32F100RD, STM32F100VD, STM32F100ZD, STM32F100RE, STM32F100VE and STM32F100ZE */
+ /* #define STM32F101x6 */ /*!< STM32F101C4, STM32F101R4, STM32F101T4, STM32F101C6, STM32F101R6 and STM32F101T6 Devices */
+ /* #define STM32F101xB */ /*!< STM32F101C8, STM32F101R8, STM32F101T8, STM32F101V8, STM32F101CB, STM32F101RB, STM32F101TB and STM32F101VB */
+ /* #define STM32F101xE */ /*!< STM32F101RC, STM32F101VC, STM32F101ZC, STM32F101RD, STM32F101VD, STM32F101ZD, STM32F101RE, STM32F101VE and STM32F101ZE */
+ /* #define STM32F101xG */ /*!< STM32F101RF, STM32F101VF, STM32F101ZF, STM32F101RG, STM32F101VG and STM32F101ZG */
+ /* #define STM32F102x6 */ /*!< STM32F102C4, STM32F102R4, STM32F102C6 and STM32F102R6 */
+ /* #define STM32F102xB */ /*!< STM32F102C8, STM32F102R8, STM32F102CB and STM32F102RB */
+ /* #define STM32F103x6 */ /*!< STM32F103C4, STM32F103R4, STM32F103T4, STM32F103C6, STM32F103R6 and STM32F103T6 */
+ /* #define STM32F103xB */ /*!< STM32F103C8, STM32F103R8, STM32F103T8, STM32F103V8, STM32F103CB, STM32F103RB, STM32F103TB and STM32F103VB */
+ /* #define STM32F103xE */ /*!< STM32F103RC, STM32F103VC, STM32F103ZC, STM32F103RD, STM32F103VD, STM32F103ZD, STM32F103RE, STM32F103VE and STM32F103ZE */
+ /* #define STM32F103xG */ /*!< STM32F103RF, STM32F103VF, STM32F103ZF, STM32F103RG, STM32F103VG and STM32F103ZG */
+ /* #define STM32F105xC */ /*!< STM32F105R8, STM32F105V8, STM32F105RB, STM32F105VB, STM32F105RC and STM32F105VC */
+ /* #define STM32F107xC */ /*!< STM32F107RB, STM32F107VB, STM32F107RC and STM32F107VC */
+#endif
+
+/* Tip: To avoid modifying this file each time you need to switch between these
+ devices, you can define the device in your toolchain compiler preprocessor.
+ */
+
+#if !defined (USE_HAL_DRIVER)
+/**
+ * @brief Comment the line below if you will not use the peripherals drivers.
+ In this case, these drivers will not be included and the application code will
+ be based on direct access to peripherals registers
+ */
+ /*#define USE_HAL_DRIVER */
+#endif /* USE_HAL_DRIVER */
+
+/**
+ * @brief CMSIS Device version number
+ */
+#define __STM32F1_CMSIS_VERSION_MAIN (0x04) /*!< [31:24] main version */
+#define __STM32F1_CMSIS_VERSION_SUB1 (0x01) /*!< [23:16] sub1 version */
+#define __STM32F1_CMSIS_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
+#define __STM32F1_CMSIS_VERSION_RC (0x00) /*!< [7:0] release candidate */
+#define __STM32F1_CMSIS_VERSION ((__STM32F1_CMSIS_VERSION_MAIN << 24)\
+ |(__STM32F1_CMSIS_VERSION_SUB1 << 16)\
+ |(__STM32F1_CMSIS_VERSION_SUB2 << 8 )\
+ |(__STM32F1_CMSIS_VERSION_RC))
+
+/**
+ * @}
+ */
+
+/** @addtogroup Device_Included
+ * @{
+ */
+
+#if defined(STM32F100xB)
+ #include "stm32f100xb.h"
+#elif defined(STM32F100xE)
+ #include "stm32f100xe.h"
+#elif defined(STM32F101x6)
+ #include "stm32f101x6.h"
+#elif defined(STM32F101xB)
+ #include "stm32f101xb.h"
+#elif defined(STM32F101xE)
+ #include "stm32f101xe.h"
+#elif defined(STM32F101xG)
+ #include "stm32f101xg.h"
+#elif defined(STM32F102x6)
+ #include "stm32f102x6.h"
+#elif defined(STM32F102xB)
+ #include "stm32f102xb.h"
+#elif defined(STM32F103x6)
+ #include "stm32f103x6.h"
+#elif defined(STM32F103xB)
+ #include "stm32f103xb.h"
+#elif defined(STM32F103xE)
+ #include "stm32f103xe.h"
+#elif defined(STM32F103xG)
+ #include "stm32f103xg.h"
+#elif defined(STM32F105xC)
+ #include "stm32f105xc.h"
+#elif defined(STM32F107xC)
+ #include "stm32f107xc.h"
+#else
+ #error "Please select first the target STM32F1xx device used in your application (in stm32f1xx.h file)"
+#endif
+
+/**
+ * @}
+ */
+
+/** @addtogroup Exported_types
+ * @{
+ */
+typedef enum
+{
+ RESET = 0,
+ SET = !RESET
+} FlagStatus, ITStatus;
+
+typedef enum
+{
+ DISABLE = 0,
+ ENABLE = !DISABLE
+} FunctionalState;
+#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
+
+typedef enum
+{
+ ERROR = 0,
+ SUCCESS = !ERROR
+} ErrorStatus;
+
+/**
+ * @}
+ */
+
+
+/** @addtogroup Exported_macros
+ * @{
+ */
+#define SET_BIT(REG, BIT) ((REG) |= (BIT))
+
+#define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT))
+
+#define READ_BIT(REG, BIT) ((REG) & (BIT))
+
+#define CLEAR_REG(REG) ((REG) = (0x0))
+
+#define WRITE_REG(REG, VAL) ((REG) = (VAL))
+
+#define READ_REG(REG) ((REG))
+
+#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))
+
+#define POSITION_VAL(VAL) (__CLZ(__RBIT(VAL)))
+
+
+/**
+ * @}
+ */
+
+#if defined (USE_HAL_DRIVER)
+ #include "stm32f1xx_hal.h"
+#endif /* USE_HAL_DRIVER */
+
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* __STM32F1xx_H */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+
+
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Device/ST/STM32F1xx/Include/system_stm32f1xx.h b/Device/ST/STM32F1xx/Include/system_stm32f1xx.h
new file mode 100644
index 0000000..3587015
--- /dev/null
+++ b/Device/ST/STM32F1xx/Include/system_stm32f1xx.h
@@ -0,0 +1,116 @@
+/**
+ ******************************************************************************
+ * @file system_stm32f10x.h
+ * @author MCD Application Team
+ * @version V4.1.0
+ * @date 29-April-2016
+ * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Header File.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/** @addtogroup CMSIS
+ * @{
+ */
+
+/** @addtogroup stm32f10x_system
+ * @{
+ */
+
+/**
+ * @brief Define to prevent recursive inclusion
+ */
+#ifndef __SYSTEM_STM32F10X_H
+#define __SYSTEM_STM32F10X_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/** @addtogroup STM32F10x_System_Includes
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+
+/** @addtogroup STM32F10x_System_Exported_types
+ * @{
+ */
+
+extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
+extern const uint8_t AHBPrescTable[16]; /*!< AHB prescalers table values */
+extern const uint8_t APBPrescTable[8]; /*!< APB prescalers table values */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F10x_System_Exported_Constants
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F10x_System_Exported_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F10x_System_Exported_Functions
+ * @{
+ */
+
+extern void SystemInit(void);
+extern void SystemCoreClockUpdate(void);
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__SYSTEM_STM32F10X_H */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Device/ST/STM32F4xx/Include/stm32f401xc.h b/Device/ST/STM32F4xx/Include/stm32f401xc.h
new file mode 100644
index 0000000..4970ef2
--- /dev/null
+++ b/Device/ST/STM32F4xx/Include/stm32f401xc.h
@@ -0,0 +1,4805 @@
+/**
+ ******************************************************************************
+ * @file stm32f401xc.h
+ * @author MCD Application Team
+ * @version V2.5.0
+ * @date 22-April-2016
+ * @brief CMSIS STM32F401xCxx Device Peripheral Access Layer Header File.
+ *
+ * This file contains:
+ * - Data structures and the address mapping for all peripherals
+ * - peripherals registers declarations and bits definition
+ * - Macros to access peripheral’s registers hardware
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/** @addtogroup CMSIS
+ * @{
+ */
+
+/** @addtogroup stm32f401xc
+ * @{
+ */
+
+#ifndef __STM32F401xC_H
+#define __STM32F401xC_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif /* __cplusplus */
+
+
+/** @addtogroup Configuration_section_for_CMSIS
+ * @{
+ */
+
+/**
+ * @brief Configuration of the Cortex-M4 Processor and Core Peripherals
+ */
+#define __CM4_REV 0x0001U /*!< Core revision r0p1 */
+#define __MPU_PRESENT 1U /*!< STM32F4XX provides an MPU */
+#define __NVIC_PRIO_BITS 4U /*!< STM32F4XX uses 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */
+#define __FPU_PRESENT 1U /*!< FPU present */
+
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_interrupt_number_definition
+ * @{
+ */
+
+/**
+ * @brief STM32F4XX Interrupt Number Definition, according to the selected device
+ * in @ref Library_configuration_section
+ */
+typedef enum
+{
+/****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/
+ NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
+ MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */
+ BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */
+ UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */
+ SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */
+ DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */
+ PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */
+ SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */
+/****** STM32 specific Interrupt Numbers **********************************************************************/
+ WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
+ PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */
+ TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */
+ RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */
+ FLASH_IRQn = 4, /*!< FLASH global Interrupt */
+ RCC_IRQn = 5, /*!< RCC global Interrupt */
+ EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */
+ EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */
+ EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */
+ EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */
+ EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */
+ DMA1_Stream0_IRQn = 11, /*!< DMA1 Stream 0 global Interrupt */
+ DMA1_Stream1_IRQn = 12, /*!< DMA1 Stream 1 global Interrupt */
+ DMA1_Stream2_IRQn = 13, /*!< DMA1 Stream 2 global Interrupt */
+ DMA1_Stream3_IRQn = 14, /*!< DMA1 Stream 3 global Interrupt */
+ DMA1_Stream4_IRQn = 15, /*!< DMA1 Stream 4 global Interrupt */
+ DMA1_Stream5_IRQn = 16, /*!< DMA1 Stream 5 global Interrupt */
+ DMA1_Stream6_IRQn = 17, /*!< DMA1 Stream 6 global Interrupt */
+ ADC_IRQn = 18, /*!< ADC1, ADC2 and ADC3 global Interrupts */
+ EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
+ TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break interrupt and TIM9 global interrupt */
+ TIM1_UP_TIM10_IRQn = 25, /*!< TIM1 Update Interrupt and TIM10 global interrupt */
+ TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */
+ TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
+ TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
+ TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
+ TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
+ I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
+ I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
+ I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
+ I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
+ SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
+ SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
+ USART1_IRQn = 37, /*!< USART1 global Interrupt */
+ USART2_IRQn = 38, /*!< USART2 global Interrupt */
+ EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
+ RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */
+ OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS Wakeup through EXTI line interrupt */
+ DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */
+ SDIO_IRQn = 49, /*!< SDIO global Interrupt */
+ TIM5_IRQn = 50, /*!< TIM5 global Interrupt */
+ SPI3_IRQn = 51, /*!< SPI3 global Interrupt */
+ DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */
+ DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */
+ DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */
+ DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */
+ DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */
+ OTG_FS_IRQn = 67, /*!< USB OTG FS global Interrupt */
+ DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */
+ DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */
+ DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */
+ USART6_IRQn = 71, /*!< USART6 global interrupt */
+ I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */
+ I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */
+ FPU_IRQn = 81, /*!< FPU global interrupt */
+ SPI4_IRQn = 84 /*!< SPI4 global Interrupt */
+} IRQn_Type;
+
+/**
+ * @}
+ */
+
+#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
+#include "system_stm32f4xx.h"
+#include <stdint.h>
+
+/** @addtogroup Peripheral_registers_structures
+ * @{
+ */
+
+/**
+ * @brief Analog to Digital Converter
+ */
+
+typedef struct
+{
+ __IO uint32_t SR; /*!< ADC status register, Address offset: 0x00 */
+ __IO uint32_t CR1; /*!< ADC control register 1, Address offset: 0x04 */
+ __IO uint32_t CR2; /*!< ADC control register 2, Address offset: 0x08 */
+ __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x0C */
+ __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x10 */
+ __IO uint32_t JOFR1; /*!< ADC injected channel data offset register 1, Address offset: 0x14 */
+ __IO uint32_t JOFR2; /*!< ADC injected channel data offset register 2, Address offset: 0x18 */
+ __IO uint32_t JOFR3; /*!< ADC injected channel data offset register 3, Address offset: 0x1C */
+ __IO uint32_t JOFR4; /*!< ADC injected channel data offset register 4, Address offset: 0x20 */
+ __IO uint32_t HTR; /*!< ADC watchdog higher threshold register, Address offset: 0x24 */
+ __IO uint32_t LTR; /*!< ADC watchdog lower threshold register, Address offset: 0x28 */
+ __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x2C */
+ __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x30 */
+ __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x34 */
+ __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x38*/
+ __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x3C */
+ __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x40 */
+ __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x44 */
+ __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x48 */
+ __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x4C */
+} ADC_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1 base address + 0x300 */
+ __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1 base address + 0x304 */
+ __IO uint32_t CDR; /*!< ADC common regular data register for dual
+ AND triple modes, Address offset: ADC1 base address + 0x308 */
+} ADC_Common_TypeDef;
+
+/**
+ * @brief CRC calculation unit
+ */
+
+typedef struct
+{
+ __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
+ __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
+ uint8_t RESERVED0; /*!< Reserved, 0x05 */
+ uint16_t RESERVED1; /*!< Reserved, 0x06 */
+ __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
+} CRC_TypeDef;
+
+/**
+ * @brief Debug MCU
+ */
+
+typedef struct
+{
+ __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
+ __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
+ __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */
+ __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */
+}DBGMCU_TypeDef;
+
+
+/**
+ * @brief DMA Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< DMA stream x configuration register */
+ __IO uint32_t NDTR; /*!< DMA stream x number of data register */
+ __IO uint32_t PAR; /*!< DMA stream x peripheral address register */
+ __IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */
+ __IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */
+ __IO uint32_t FCR; /*!< DMA stream x FIFO control register */
+} DMA_Stream_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t LISR; /*!< DMA low interrupt status register, Address offset: 0x00 */
+ __IO uint32_t HISR; /*!< DMA high interrupt status register, Address offset: 0x04 */
+ __IO uint32_t LIFCR; /*!< DMA low interrupt flag clear register, Address offset: 0x08 */
+ __IO uint32_t HIFCR; /*!< DMA high interrupt flag clear register, Address offset: 0x0C */
+} DMA_TypeDef;
+
+
+/**
+ * @brief External Interrupt/Event Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t IMR; /*!< EXTI Interrupt mask register, Address offset: 0x00 */
+ __IO uint32_t EMR; /*!< EXTI Event mask register, Address offset: 0x04 */
+ __IO uint32_t RTSR; /*!< EXTI Rising trigger selection register, Address offset: 0x08 */
+ __IO uint32_t FTSR; /*!< EXTI Falling trigger selection register, Address offset: 0x0C */
+ __IO uint32_t SWIER; /*!< EXTI Software interrupt event register, Address offset: 0x10 */
+ __IO uint32_t PR; /*!< EXTI Pending register, Address offset: 0x14 */
+} EXTI_TypeDef;
+
+/**
+ * @brief FLASH Registers
+ */
+
+typedef struct
+{
+ __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */
+ __IO uint32_t KEYR; /*!< FLASH key register, Address offset: 0x04 */
+ __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x08 */
+ __IO uint32_t SR; /*!< FLASH status register, Address offset: 0x0C */
+ __IO uint32_t CR; /*!< FLASH control register, Address offset: 0x10 */
+ __IO uint32_t OPTCR; /*!< FLASH option control register , Address offset: 0x14 */
+ __IO uint32_t OPTCR1; /*!< FLASH option control register 1, Address offset: 0x18 */
+} FLASH_TypeDef;
+
+/**
+ * @brief General Purpose I/O
+ */
+
+typedef struct
+{
+ __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
+ __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */
+ __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */
+ __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
+ __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
+ __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
+ __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */
+ __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
+ __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */
+} GPIO_TypeDef;
+
+/**
+ * @brief System configuration controller
+ */
+
+typedef struct
+{
+ __IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */
+ __IO uint32_t PMC; /*!< SYSCFG peripheral mode configuration register, Address offset: 0x04 */
+ __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
+ uint32_t RESERVED[2]; /*!< Reserved, 0x18-0x1C */
+ __IO uint32_t CMPCR; /*!< SYSCFG Compensation cell control register, Address offset: 0x20 */
+} SYSCFG_TypeDef;
+
+/**
+ * @brief Inter-integrated Circuit Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */
+ __IO uint32_t OAR1; /*!< I2C Own address register 1, Address offset: 0x08 */
+ __IO uint32_t OAR2; /*!< I2C Own address register 2, Address offset: 0x0C */
+ __IO uint32_t DR; /*!< I2C Data register, Address offset: 0x10 */
+ __IO uint32_t SR1; /*!< I2C Status register 1, Address offset: 0x14 */
+ __IO uint32_t SR2; /*!< I2C Status register 2, Address offset: 0x18 */
+ __IO uint32_t CCR; /*!< I2C Clock control register, Address offset: 0x1C */
+ __IO uint32_t TRISE; /*!< I2C TRISE register, Address offset: 0x20 */
+ __IO uint32_t FLTR; /*!< I2C FLTR register, Address offset: 0x24 */
+} I2C_TypeDef;
+
+/**
+ * @brief Independent WATCHDOG
+ */
+
+typedef struct
+{
+ __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */
+ __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */
+ __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */
+ __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */
+} IWDG_TypeDef;
+
+/**
+ * @brief Power Control
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */
+ __IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */
+} PWR_TypeDef;
+
+/**
+ * @brief Reset and Clock Control
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */
+ __IO uint32_t PLLCFGR; /*!< RCC PLL configuration register, Address offset: 0x04 */
+ __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x08 */
+ __IO uint32_t CIR; /*!< RCC clock interrupt register, Address offset: 0x0C */
+ __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x10 */
+ __IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x14 */
+ __IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0x18 */
+ uint32_t RESERVED0; /*!< Reserved, 0x1C */
+ __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x20 */
+ __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x24 */
+ uint32_t RESERVED1[2]; /*!< Reserved, 0x28-0x2C */
+ __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clock register, Address offset: 0x30 */
+ __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clock register, Address offset: 0x34 */
+ __IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clock register, Address offset: 0x38 */
+ uint32_t RESERVED2; /*!< Reserved, 0x3C */
+ __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x40 */
+ __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x44 */
+ uint32_t RESERVED3[2]; /*!< Reserved, 0x48-0x4C */
+ __IO uint32_t AHB1LPENR; /*!< RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 */
+ __IO uint32_t AHB2LPENR; /*!< RCC AHB2 peripheral clock enable in low power mode register, Address offset: 0x54 */
+ __IO uint32_t AHB3LPENR; /*!< RCC AHB3 peripheral clock enable in low power mode register, Address offset: 0x58 */
+ uint32_t RESERVED4; /*!< Reserved, 0x5C */
+ __IO uint32_t APB1LPENR; /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 */
+ __IO uint32_t APB2LPENR; /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 */
+ uint32_t RESERVED5[2]; /*!< Reserved, 0x68-0x6C */
+ __IO uint32_t BDCR; /*!< RCC Backup domain control register, Address offset: 0x70 */
+ __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x74 */
+ uint32_t RESERVED6[2]; /*!< Reserved, 0x78-0x7C */
+ __IO uint32_t SSCGR; /*!< RCC spread spectrum clock generation register, Address offset: 0x80 */
+ __IO uint32_t PLLI2SCFGR; /*!< RCC PLLI2S configuration register, Address offset: 0x84 */
+ uint32_t RESERVED7[1]; /*!< Reserved, 0x88 */
+ __IO uint32_t DCKCFGR; /*!< RCC DCKCFGR configuration register, Address offset: 0x8C */
+} RCC_TypeDef;
+
+/**
+ * @brief Real-Time Clock
+ */
+
+typedef struct
+{
+ __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
+ __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */
+ __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */
+ __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */
+ __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */
+ __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */
+ __IO uint32_t CALIBR; /*!< RTC calibration register, Address offset: 0x18 */
+ __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */
+ __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */
+ __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */
+ __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */
+ __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */
+ __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */
+ __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */
+ __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */
+ __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */
+ __IO uint32_t TAFCR; /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */
+ __IO uint32_t ALRMASSR;/*!< RTC alarm A sub second register, Address offset: 0x44 */
+ __IO uint32_t ALRMBSSR;/*!< RTC alarm B sub second register, Address offset: 0x48 */
+ uint32_t RESERVED7; /*!< Reserved, 0x4C */
+ __IO uint32_t BKP0R; /*!< RTC backup register 1, Address offset: 0x50 */
+ __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */
+ __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */
+ __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */
+ __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */
+ __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */
+ __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */
+ __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */
+ __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */
+ __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */
+ __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */
+ __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */
+ __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */
+ __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */
+ __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */
+ __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */
+ __IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */
+ __IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */
+ __IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */
+ __IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */
+} RTC_TypeDef;
+
+
+/**
+ * @brief SD host Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t POWER; /*!< SDIO power control register, Address offset: 0x00 */
+ __IO uint32_t CLKCR; /*!< SDI clock control register, Address offset: 0x04 */
+ __IO uint32_t ARG; /*!< SDIO argument register, Address offset: 0x08 */
+ __IO uint32_t CMD; /*!< SDIO command register, Address offset: 0x0C */
+ __I uint32_t RESPCMD; /*!< SDIO command response register, Address offset: 0x10 */
+ __I uint32_t RESP1; /*!< SDIO response 1 register, Address offset: 0x14 */
+ __I uint32_t RESP2; /*!< SDIO response 2 register, Address offset: 0x18 */
+ __I uint32_t RESP3; /*!< SDIO response 3 register, Address offset: 0x1C */
+ __I uint32_t RESP4; /*!< SDIO response 4 register, Address offset: 0x20 */
+ __IO uint32_t DTIMER; /*!< SDIO data timer register, Address offset: 0x24 */
+ __IO uint32_t DLEN; /*!< SDIO data length register, Address offset: 0x28 */
+ __IO uint32_t DCTRL; /*!< SDIO data control register, Address offset: 0x2C */
+ __I uint32_t DCOUNT; /*!< SDIO data counter register, Address offset: 0x30 */
+ __I uint32_t STA; /*!< SDIO status register, Address offset: 0x34 */
+ __IO uint32_t ICR; /*!< SDIO interrupt clear register, Address offset: 0x38 */
+ __IO uint32_t MASK; /*!< SDIO mask register, Address offset: 0x3C */
+ uint32_t RESERVED0[2]; /*!< Reserved, 0x40-0x44 */
+ __I uint32_t FIFOCNT; /*!< SDIO FIFO counter register, Address offset: 0x48 */
+ uint32_t RESERVED1[13]; /*!< Reserved, 0x4C-0x7C */
+ __IO uint32_t FIFO; /*!< SDIO data FIFO register, Address offset: 0x80 */
+} SDIO_TypeDef;
+
+/**
+ * @brief Serial Peripheral Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t CR1; /*!< SPI control register 1 (not used in I2S mode), Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< SPI control register 2, Address offset: 0x04 */
+ __IO uint32_t SR; /*!< SPI status register, Address offset: 0x08 */
+ __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */
+ __IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
+ __IO uint32_t RXCRCR; /*!< SPI RX CRC register (not used in I2S mode), Address offset: 0x14 */
+ __IO uint32_t TXCRCR; /*!< SPI TX CRC register (not used in I2S mode), Address offset: 0x18 */
+ __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */
+ __IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */
+} SPI_TypeDef;
+
+/**
+ * @brief TIM
+ */
+
+typedef struct
+{
+ __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
+ __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */
+ __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
+ __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
+ __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
+ __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
+ __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
+ __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
+ __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
+ __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */
+ __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
+ __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */
+ __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
+ __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
+ __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
+ __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
+ __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
+ __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
+ __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */
+ __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */
+} TIM_TypeDef;
+
+/**
+ * @brief Universal Synchronous Asynchronous Receiver Transmitter
+ */
+
+typedef struct
+{
+ __IO uint32_t SR; /*!< USART Status register, Address offset: 0x00 */
+ __IO uint32_t DR; /*!< USART Data register, Address offset: 0x04 */
+ __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x08 */
+ __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x0C */
+ __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x10 */
+ __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x14 */
+ __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x18 */
+} USART_TypeDef;
+
+/**
+ * @brief Window WATCHDOG
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
+ __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
+ __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
+} WWDG_TypeDef;
+
+/**
+ * @brief __USB_OTG_Core_register
+ */
+typedef struct
+{
+ __IO uint32_t GOTGCTL; /*!< USB_OTG Control and Status Register Address offset : 0x00 */
+ __IO uint32_t GOTGINT; /*!< USB_OTG Interrupt Register Address offset : 0x04 */
+ __IO uint32_t GAHBCFG; /*!< Core AHB Configuration Register Address offset : 0x08 */
+ __IO uint32_t GUSBCFG; /*!< Core USB Configuration Register Address offset : 0x0C */
+ __IO uint32_t GRSTCTL; /*!< Core Reset Register Address offset : 0x10 */
+ __IO uint32_t GINTSTS; /*!< Core Interrupt Register Address offset : 0x14 */
+ __IO uint32_t GINTMSK; /*!< Core Interrupt Mask Register Address offset : 0x18 */
+ __IO uint32_t GRXSTSR; /*!< Receive Sts Q Read Register Address offset : 0x1C */
+ __IO uint32_t GRXSTSP; /*!< Receive Sts Q Read & POP Register Address offset : 0x20 */
+ __IO uint32_t GRXFSIZ; /* Receive FIFO Size Register Address offset : 0x24 */
+ __IO uint32_t DIEPTXF0_HNPTXFSIZ; /*!< EP0 / Non Periodic Tx FIFO Size Register Address offset : 0x28 */
+ __IO uint32_t HNPTXSTS; /*!< Non Periodic Tx FIFO/Queue Sts reg Address offset : 0x2C */
+ uint32_t Reserved30[2]; /* Reserved Address offset : 0x30 */
+ __IO uint32_t GCCFG; /*!< General Purpose IO Register Address offset : 0x38 */
+ __IO uint32_t CID; /*!< User ID Register Address offset : 0x3C */
+ uint32_t Reserved40[48]; /*!< Reserved Address offset : 0x40-0xFF */
+ __IO uint32_t HPTXFSIZ; /*!< Host Periodic Tx FIFO Size Reg Address offset : 0x100 */
+ __IO uint32_t DIEPTXF[0x0F]; /*!< dev Periodic Transmit FIFO */
+}
+USB_OTG_GlobalTypeDef;
+
+
+
+/**
+ * @brief __device_Registers
+ */
+typedef struct
+{
+ __IO uint32_t DCFG; /*!< dev Configuration Register Address offset : 0x800 */
+ __IO uint32_t DCTL; /*!< dev Control Register Address offset : 0x804 */
+ __IO uint32_t DSTS; /*!< dev Status Register (RO) Address offset : 0x808 */
+ uint32_t Reserved0C; /*!< Reserved Address offset : 0x80C */
+ __IO uint32_t DIEPMSK; /* !< dev IN Endpoint Mask Address offset : 0x810 */
+ __IO uint32_t DOEPMSK; /*!< dev OUT Endpoint Mask Address offset : 0x814 */
+ __IO uint32_t DAINT; /*!< dev All Endpoints Itr Reg Address offset : 0x818 */
+ __IO uint32_t DAINTMSK; /*!< dev All Endpoints Itr Mask Address offset : 0x81C */
+ uint32_t Reserved20; /*!< Reserved Address offset : 0x820 */
+ uint32_t Reserved9; /*!< Reserved Address offset : 0x824 */
+ __IO uint32_t DVBUSDIS; /*!< dev VBUS discharge Register Address offset : 0x828 */
+ __IO uint32_t DVBUSPULSE; /*!< dev VBUS Pulse Register Address offset : 0x82C */
+ __IO uint32_t DTHRCTL; /*!< dev thr Address offset : 0x830 */
+ __IO uint32_t DIEPEMPMSK; /*!< dev empty msk Address offset : 0x834 */
+ __IO uint32_t DEACHINT; /*!< dedicated EP interrupt Address offset : 0x838 */
+ __IO uint32_t DEACHMSK; /*!< dedicated EP msk Address offset : 0x83C */
+ uint32_t Reserved40; /*!< dedicated EP mask Address offset : 0x840 */
+ __IO uint32_t DINEP1MSK; /*!< dedicated EP mask Address offset : 0x844 */
+ uint32_t Reserved44[15]; /*!< Reserved Address offset : 0x844-0x87C */
+ __IO uint32_t DOUTEP1MSK; /*!< dedicated EP msk Address offset : 0x884 */
+}
+USB_OTG_DeviceTypeDef;
+
+
+/**
+ * @brief __IN_Endpoint-Specific_Register
+ */
+typedef struct
+{
+ __IO uint32_t DIEPCTL; /* dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h */
+ uint32_t Reserved04; /* Reserved 900h + (ep_num * 20h) + 04h */
+ __IO uint32_t DIEPINT; /* dev IN Endpoint Itr Reg 900h + (ep_num * 20h) + 08h */
+ uint32_t Reserved0C; /* Reserved 900h + (ep_num * 20h) + 0Ch */
+ __IO uint32_t DIEPTSIZ; /* IN Endpoint Txfer Size 900h + (ep_num * 20h) + 10h */
+ __IO uint32_t DIEPDMA; /* IN Endpoint DMA Address Reg 900h + (ep_num * 20h) + 14h */
+ __IO uint32_t DTXFSTS; /*IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h */
+ uint32_t Reserved18; /* Reserved 900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch */
+}
+USB_OTG_INEndpointTypeDef;
+
+
+/**
+ * @brief __OUT_Endpoint-Specific_Registers
+ */
+typedef struct
+{
+ __IO uint32_t DOEPCTL; /* dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h*/
+ uint32_t Reserved04; /* Reserved B00h + (ep_num * 20h) + 04h*/
+ __IO uint32_t DOEPINT; /* dev OUT Endpoint Itr Reg B00h + (ep_num * 20h) + 08h*/
+ uint32_t Reserved0C; /* Reserved B00h + (ep_num * 20h) + 0Ch*/
+ __IO uint32_t DOEPTSIZ; /* dev OUT Endpoint Txfer Size B00h + (ep_num * 20h) + 10h*/
+ __IO uint32_t DOEPDMA; /* dev OUT Endpoint DMA Address B00h + (ep_num * 20h) + 14h*/
+ uint32_t Reserved18[2]; /* Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch*/
+}
+USB_OTG_OUTEndpointTypeDef;
+
+
+/**
+ * @brief __Host_Mode_Register_Structures
+ */
+typedef struct
+{
+ __IO uint32_t HCFG; /* Host Configuration Register 400h*/
+ __IO uint32_t HFIR; /* Host Frame Interval Register 404h*/
+ __IO uint32_t HFNUM; /* Host Frame Nbr/Frame Remaining 408h*/
+ uint32_t Reserved40C; /* Reserved 40Ch*/
+ __IO uint32_t HPTXSTS; /* Host Periodic Tx FIFO/ Queue Status 410h*/
+ __IO uint32_t HAINT; /* Host All Channels Interrupt Register 414h*/
+ __IO uint32_t HAINTMSK; /* Host All Channels Interrupt Mask 418h*/
+}
+USB_OTG_HostTypeDef;
+
+
+/**
+ * @brief __Host_Channel_Specific_Registers
+ */
+typedef struct
+{
+ __IO uint32_t HCCHAR;
+ __IO uint32_t HCSPLT;
+ __IO uint32_t HCINT;
+ __IO uint32_t HCINTMSK;
+ __IO uint32_t HCTSIZ;
+ __IO uint32_t HCDMA;
+ uint32_t Reserved[2];
+}
+USB_OTG_HostChannelTypeDef;
+
+
+/**
+ * @brief Peripheral_memory_map
+ */
+#define FLASH_BASE 0x08000000U /*!< FLASH(up to 1 MB) base address in the alias region */
+#define SRAM1_BASE 0x20000000U /*!< SRAM1(64 KB) base address in the alias region */
+#define PERIPH_BASE 0x40000000U /*!< Peripheral base address in the alias region */
+#define BKPSRAM_BASE 0x40024000U /*!< Backup SRAM(4 KB) base address in the alias region */
+#define SRAM1_BB_BASE 0x22000000U /*!< SRAM1(64 KB) base address in the bit-band region */
+#define PERIPH_BB_BASE 0x42000000U /*!< Peripheral base address in the bit-band region */
+#define BKPSRAM_BB_BASE 0x42480000U /*!< Backup SRAM(4 KB) base address in the bit-band region */
+#define FLASH_END 0x0803FFFFU /*!< FLASH end address */
+
+/* Legacy defines */
+#define SRAM_BASE SRAM1_BASE
+#define SRAM_BB_BASE SRAM1_BB_BASE
+
+
+/*!< Peripheral memory map */
+#define APB1PERIPH_BASE PERIPH_BASE
+#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000U)
+#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000U)
+#define AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000U)
+
+/*!< APB1 peripherals */
+#define TIM2_BASE (APB1PERIPH_BASE + 0x0000U)
+#define TIM3_BASE (APB1PERIPH_BASE + 0x0400U)
+#define TIM4_BASE (APB1PERIPH_BASE + 0x0800U)
+#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00U)
+#define RTC_BASE (APB1PERIPH_BASE + 0x2800U)
+#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00U)
+#define IWDG_BASE (APB1PERIPH_BASE + 0x3000U)
+#define I2S2ext_BASE (APB1PERIPH_BASE + 0x3400U)
+#define SPI2_BASE (APB1PERIPH_BASE + 0x3800U)
+#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00U)
+#define I2S3ext_BASE (APB1PERIPH_BASE + 0x4000U)
+#define USART2_BASE (APB1PERIPH_BASE + 0x4400U)
+#define I2C1_BASE (APB1PERIPH_BASE + 0x5400U)
+#define I2C2_BASE (APB1PERIPH_BASE + 0x5800U)
+#define I2C3_BASE (APB1PERIPH_BASE + 0x5C00U)
+#define PWR_BASE (APB1PERIPH_BASE + 0x7000U)
+
+/*!< APB2 peripherals */
+#define TIM1_BASE (APB2PERIPH_BASE + 0x0000U)
+#define USART1_BASE (APB2PERIPH_BASE + 0x1000U)
+#define USART6_BASE (APB2PERIPH_BASE + 0x1400U)
+#define ADC1_BASE (APB2PERIPH_BASE + 0x2000U)
+#define ADC_BASE (APB2PERIPH_BASE + 0x2300U)
+#define SDIO_BASE (APB2PERIPH_BASE + 0x2C00U)
+#define SPI1_BASE (APB2PERIPH_BASE + 0x3000U)
+#define SPI4_BASE (APB2PERIPH_BASE + 0x3400U)
+#define SYSCFG_BASE (APB2PERIPH_BASE + 0x3800U)
+#define EXTI_BASE (APB2PERIPH_BASE + 0x3C00U)
+#define TIM9_BASE (APB2PERIPH_BASE + 0x4000U)
+#define TIM10_BASE (APB2PERIPH_BASE + 0x4400U)
+#define TIM11_BASE (APB2PERIPH_BASE + 0x4800U)
+
+/*!< AHB1 peripherals */
+#define GPIOA_BASE (AHB1PERIPH_BASE + 0x0000U)
+#define GPIOB_BASE (AHB1PERIPH_BASE + 0x0400U)
+#define GPIOC_BASE (AHB1PERIPH_BASE + 0x0800U)
+#define GPIOD_BASE (AHB1PERIPH_BASE + 0x0C00U)
+#define GPIOE_BASE (AHB1PERIPH_BASE + 0x1000U)
+#define GPIOH_BASE (AHB1PERIPH_BASE + 0x1C00U)
+#define CRC_BASE (AHB1PERIPH_BASE + 0x3000U)
+#define RCC_BASE (AHB1PERIPH_BASE + 0x3800U)
+#define FLASH_R_BASE (AHB1PERIPH_BASE + 0x3C00U)
+#define DMA1_BASE (AHB1PERIPH_BASE + 0x6000U)
+#define DMA1_Stream0_BASE (DMA1_BASE + 0x010U)
+#define DMA1_Stream1_BASE (DMA1_BASE + 0x028U)
+#define DMA1_Stream2_BASE (DMA1_BASE + 0x040U)
+#define DMA1_Stream3_BASE (DMA1_BASE + 0x058U)
+#define DMA1_Stream4_BASE (DMA1_BASE + 0x070U)
+#define DMA1_Stream5_BASE (DMA1_BASE + 0x088U)
+#define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0U)
+#define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8U)
+#define DMA2_BASE (AHB1PERIPH_BASE + 0x6400U)
+#define DMA2_Stream0_BASE (DMA2_BASE + 0x010U)
+#define DMA2_Stream1_BASE (DMA2_BASE + 0x028U)
+#define DMA2_Stream2_BASE (DMA2_BASE + 0x040U)
+#define DMA2_Stream3_BASE (DMA2_BASE + 0x058U)
+#define DMA2_Stream4_BASE (DMA2_BASE + 0x070U)
+#define DMA2_Stream5_BASE (DMA2_BASE + 0x088U)
+#define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0U)
+#define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8U)
+
+/* Debug MCU registers base address */
+#define DBGMCU_BASE 0xE0042000U
+
+/*!< USB registers base address */
+#define USB_OTG_FS_PERIPH_BASE 0x50000000U
+
+#define USB_OTG_GLOBAL_BASE 0x000U
+#define USB_OTG_DEVICE_BASE 0x800U
+#define USB_OTG_IN_ENDPOINT_BASE 0x900U
+#define USB_OTG_OUT_ENDPOINT_BASE 0xB00U
+#define USB_OTG_EP_REG_SIZE 0x20U
+#define USB_OTG_HOST_BASE 0x400U
+#define USB_OTG_HOST_PORT_BASE 0x440U
+#define USB_OTG_HOST_CHANNEL_BASE 0x500U
+#define USB_OTG_HOST_CHANNEL_SIZE 0x20U
+#define USB_OTG_PCGCCTL_BASE 0xE00U
+#define USB_OTG_FIFO_BASE 0x1000U
+#define USB_OTG_FIFO_SIZE 0x1000U
+
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_declaration
+ * @{
+ */
+#define TIM2 ((TIM_TypeDef *) TIM2_BASE)
+#define TIM3 ((TIM_TypeDef *) TIM3_BASE)
+#define TIM4 ((TIM_TypeDef *) TIM4_BASE)
+#define TIM5 ((TIM_TypeDef *) TIM5_BASE)
+#define RTC ((RTC_TypeDef *) RTC_BASE)
+#define WWDG ((WWDG_TypeDef *) WWDG_BASE)
+#define IWDG ((IWDG_TypeDef *) IWDG_BASE)
+#define I2S2ext ((SPI_TypeDef *) I2S2ext_BASE)
+#define SPI2 ((SPI_TypeDef *) SPI2_BASE)
+#define SPI3 ((SPI_TypeDef *) SPI3_BASE)
+#define I2S3ext ((SPI_TypeDef *) I2S3ext_BASE)
+#define USART2 ((USART_TypeDef *) USART2_BASE)
+#define I2C1 ((I2C_TypeDef *) I2C1_BASE)
+#define I2C2 ((I2C_TypeDef *) I2C2_BASE)
+#define I2C3 ((I2C_TypeDef *) I2C3_BASE)
+#define PWR ((PWR_TypeDef *) PWR_BASE)
+#define TIM1 ((TIM_TypeDef *) TIM1_BASE)
+#define USART1 ((USART_TypeDef *) USART1_BASE)
+#define USART6 ((USART_TypeDef *) USART6_BASE)
+#define ADC ((ADC_Common_TypeDef *) ADC_BASE)
+#define ADC1 ((ADC_TypeDef *) ADC1_BASE)
+#define SDIO ((SDIO_TypeDef *) SDIO_BASE)
+#define SPI1 ((SPI_TypeDef *) SPI1_BASE)
+#define SPI4 ((SPI_TypeDef *) SPI4_BASE)
+#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
+#define EXTI ((EXTI_TypeDef *) EXTI_BASE)
+#define TIM9 ((TIM_TypeDef *) TIM9_BASE)
+#define TIM10 ((TIM_TypeDef *) TIM10_BASE)
+#define TIM11 ((TIM_TypeDef *) TIM11_BASE)
+#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
+#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
+#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
+#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
+#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
+#define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
+#define CRC ((CRC_TypeDef *) CRC_BASE)
+#define RCC ((RCC_TypeDef *) RCC_BASE)
+#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
+#define DMA1 ((DMA_TypeDef *) DMA1_BASE)
+#define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)
+#define DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)
+#define DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)
+#define DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)
+#define DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)
+#define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)
+#define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)
+#define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)
+#define DMA2 ((DMA_TypeDef *) DMA2_BASE)
+#define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)
+#define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
+#define DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)
+#define DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)
+#define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)
+#define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)
+#define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)
+#define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)
+
+#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
+
+#define USB_OTG_FS ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE)
+
+/**
+ * @}
+ */
+
+/** @addtogroup Exported_constants
+ * @{
+ */
+
+ /** @addtogroup Peripheral_Registers_Bits_Definition
+ * @{
+ */
+
+/******************************************************************************/
+/* Peripheral Registers_Bits_Definition */
+/******************************************************************************/
+
+/******************************************************************************/
+/* */
+/* Analog to Digital Converter */
+/* */
+/******************************************************************************/
+/******************** Bit definition for ADC_SR register ********************/
+#define ADC_SR_AWD 0x00000001U /*!<Analog watchdog flag */
+#define ADC_SR_EOC 0x00000002U /*!<End of conversion */
+#define ADC_SR_JEOC 0x00000004U /*!<Injected channel end of conversion */
+#define ADC_SR_JSTRT 0x00000008U /*!<Injected channel Start flag */
+#define ADC_SR_STRT 0x00000010U /*!<Regular channel Start flag */
+#define ADC_SR_OVR 0x00000020U /*!<Overrun flag */
+
+/******************* Bit definition for ADC_CR1 register ********************/
+#define ADC_CR1_AWDCH 0x0000001FU /*!<AWDCH[4:0] bits (Analog watchdog channel select bits) */
+#define ADC_CR1_AWDCH_0 0x00000001U /*!<Bit 0 */
+#define ADC_CR1_AWDCH_1 0x00000002U /*!<Bit 1 */
+#define ADC_CR1_AWDCH_2 0x00000004U /*!<Bit 2 */
+#define ADC_CR1_AWDCH_3 0x00000008U /*!<Bit 3 */
+#define ADC_CR1_AWDCH_4 0x00000010U /*!<Bit 4 */
+#define ADC_CR1_EOCIE 0x00000020U /*!<Interrupt enable for EOC */
+#define ADC_CR1_AWDIE 0x00000040U /*!<AAnalog Watchdog interrupt enable */
+#define ADC_CR1_JEOCIE 0x00000080U /*!<Interrupt enable for injected channels */
+#define ADC_CR1_SCAN 0x00000100U /*!<Scan mode */
+#define ADC_CR1_AWDSGL 0x00000200U /*!<Enable the watchdog on a single channel in scan mode */
+#define ADC_CR1_JAUTO 0x00000400U /*!<Automatic injected group conversion */
+#define ADC_CR1_DISCEN 0x00000800U /*!<Discontinuous mode on regular channels */
+#define ADC_CR1_JDISCEN 0x00001000U /*!<Discontinuous mode on injected channels */
+#define ADC_CR1_DISCNUM 0x0000E000U /*!<DISCNUM[2:0] bits (Discontinuous mode channel count) */
+#define ADC_CR1_DISCNUM_0 0x00002000U /*!<Bit 0 */
+#define ADC_CR1_DISCNUM_1 0x00004000U /*!<Bit 1 */
+#define ADC_CR1_DISCNUM_2 0x00008000U /*!<Bit 2 */
+#define ADC_CR1_JAWDEN 0x00400000U /*!<Analog watchdog enable on injected channels */
+#define ADC_CR1_AWDEN 0x00800000U /*!<Analog watchdog enable on regular channels */
+#define ADC_CR1_RES 0x03000000U /*!<RES[2:0] bits (Resolution) */
+#define ADC_CR1_RES_0 0x01000000U /*!<Bit 0 */
+#define ADC_CR1_RES_1 0x02000000U /*!<Bit 1 */
+#define ADC_CR1_OVRIE 0x04000000U /*!<overrun interrupt enable */
+
+/******************* Bit definition for ADC_CR2 register ********************/
+#define ADC_CR2_ADON 0x00000001U /*!<A/D Converter ON / OFF */
+#define ADC_CR2_CONT 0x00000002U /*!<Continuous Conversion */
+#define ADC_CR2_DMA 0x00000100U /*!<Direct Memory access mode */
+#define ADC_CR2_DDS 0x00000200U /*!<DMA disable selection (Single ADC) */
+#define ADC_CR2_EOCS 0x00000400U /*!<End of conversion selection */
+#define ADC_CR2_ALIGN 0x00000800U /*!<Data Alignment */
+#define ADC_CR2_JEXTSEL 0x000F0000U /*!<JEXTSEL[3:0] bits (External event select for injected group) */
+#define ADC_CR2_JEXTSEL_0 0x00010000U /*!<Bit 0 */
+#define ADC_CR2_JEXTSEL_1 0x00020000U /*!<Bit 1 */
+#define ADC_CR2_JEXTSEL_2 0x00040000U /*!<Bit 2 */
+#define ADC_CR2_JEXTSEL_3 0x00080000U /*!<Bit 3 */
+#define ADC_CR2_JEXTEN 0x00300000U /*!<JEXTEN[1:0] bits (External Trigger Conversion mode for injected channelsp) */
+#define ADC_CR2_JEXTEN_0 0x00100000U /*!<Bit 0 */
+#define ADC_CR2_JEXTEN_1 0x00200000U /*!<Bit 1 */
+#define ADC_CR2_JSWSTART 0x00400000U /*!<Start Conversion of injected channels */
+#define ADC_CR2_EXTSEL 0x0F000000U /*!<EXTSEL[3:0] bits (External Event Select for regular group) */
+#define ADC_CR2_EXTSEL_0 0x01000000U /*!<Bit 0 */
+#define ADC_CR2_EXTSEL_1 0x02000000U /*!<Bit 1 */
+#define ADC_CR2_EXTSEL_2 0x04000000U /*!<Bit 2 */
+#define ADC_CR2_EXTSEL_3 0x08000000U /*!<Bit 3 */
+#define ADC_CR2_EXTEN 0x30000000U /*!<EXTEN[1:0] bits (External Trigger Conversion mode for regular channelsp) */
+#define ADC_CR2_EXTEN_0 0x10000000U /*!<Bit 0 */
+#define ADC_CR2_EXTEN_1 0x20000000U /*!<Bit 1 */
+#define ADC_CR2_SWSTART 0x40000000U /*!<Start Conversion of regular channels */
+
+/****************** Bit definition for ADC_SMPR1 register *******************/
+#define ADC_SMPR1_SMP10 0x00000007U /*!<SMP10[2:0] bits (Channel 10 Sample time selection) */
+#define ADC_SMPR1_SMP10_0 0x00000001U /*!<Bit 0 */
+#define ADC_SMPR1_SMP10_1 0x00000002U /*!<Bit 1 */
+#define ADC_SMPR1_SMP10_2 0x00000004U /*!<Bit 2 */
+#define ADC_SMPR1_SMP11 0x00000038U /*!<SMP11[2:0] bits (Channel 11 Sample time selection) */
+#define ADC_SMPR1_SMP11_0 0x00000008U /*!<Bit 0 */
+#define ADC_SMPR1_SMP11_1 0x00000010U /*!<Bit 1 */
+#define ADC_SMPR1_SMP11_2 0x00000020U /*!<Bit 2 */
+#define ADC_SMPR1_SMP12 0x000001C0U /*!<SMP12[2:0] bits (Channel 12 Sample time selection) */
+#define ADC_SMPR1_SMP12_0 0x00000040U /*!<Bit 0 */
+#define ADC_SMPR1_SMP12_1 0x00000080U /*!<Bit 1 */
+#define ADC_SMPR1_SMP12_2 0x00000100U /*!<Bit 2 */
+#define ADC_SMPR1_SMP13 0x00000E00U /*!<SMP13[2:0] bits (Channel 13 Sample time selection) */
+#define ADC_SMPR1_SMP13_0 0x00000200U /*!<Bit 0 */
+#define ADC_SMPR1_SMP13_1 0x00000400U /*!<Bit 1 */
+#define ADC_SMPR1_SMP13_2 0x00000800U /*!<Bit 2 */
+#define ADC_SMPR1_SMP14 0x00007000U /*!<SMP14[2:0] bits (Channel 14 Sample time selection) */
+#define ADC_SMPR1_SMP14_0 0x00001000U /*!<Bit 0 */
+#define ADC_SMPR1_SMP14_1 0x00002000U /*!<Bit 1 */
+#define ADC_SMPR1_SMP14_2 0x00004000U /*!<Bit 2 */
+#define ADC_SMPR1_SMP15 0x00038000U /*!<SMP15[2:0] bits (Channel 15 Sample time selection) */
+#define ADC_SMPR1_SMP15_0 0x00008000U /*!<Bit 0 */
+#define ADC_SMPR1_SMP15_1 0x00010000U /*!<Bit 1 */
+#define ADC_SMPR1_SMP15_2 0x00020000U /*!<Bit 2 */
+#define ADC_SMPR1_SMP16 0x001C0000U /*!<SMP16[2:0] bits (Channel 16 Sample time selection) */
+#define ADC_SMPR1_SMP16_0 0x00040000U /*!<Bit 0 */
+#define ADC_SMPR1_SMP16_1 0x00080000U /*!<Bit 1 */
+#define ADC_SMPR1_SMP16_2 0x00100000U /*!<Bit 2 */
+#define ADC_SMPR1_SMP17 0x00E00000U /*!<SMP17[2:0] bits (Channel 17 Sample time selection) */
+#define ADC_SMPR1_SMP17_0 0x00200000U /*!<Bit 0 */
+#define ADC_SMPR1_SMP17_1 0x00400000U /*!<Bit 1 */
+#define ADC_SMPR1_SMP17_2 0x00800000U /*!<Bit 2 */
+#define ADC_SMPR1_SMP18 0x07000000U /*!<SMP18[2:0] bits (Channel 18 Sample time selection) */
+#define ADC_SMPR1_SMP18_0 0x01000000U /*!<Bit 0 */
+#define ADC_SMPR1_SMP18_1 0x02000000U /*!<Bit 1 */
+#define ADC_SMPR1_SMP18_2 0x04000000U /*!<Bit 2 */
+
+/****************** Bit definition for ADC_SMPR2 register *******************/
+#define ADC_SMPR2_SMP0 0x00000007U /*!<SMP0[2:0] bits (Channel 0 Sample time selection) */
+#define ADC_SMPR2_SMP0_0 0x00000001U /*!<Bit 0 */
+#define ADC_SMPR2_SMP0_1 0x00000002U /*!<Bit 1 */
+#define ADC_SMPR2_SMP0_2 0x00000004U /*!<Bit 2 */
+#define ADC_SMPR2_SMP1 0x00000038U /*!<SMP1[2:0] bits (Channel 1 Sample time selection) */
+#define ADC_SMPR2_SMP1_0 0x00000008U /*!<Bit 0 */
+#define ADC_SMPR2_SMP1_1 0x00000010U /*!<Bit 1 */
+#define ADC_SMPR2_SMP1_2 0x00000020U /*!<Bit 2 */
+#define ADC_SMPR2_SMP2 0x000001C0U /*!<SMP2[2:0] bits (Channel 2 Sample time selection) */
+#define ADC_SMPR2_SMP2_0 0x00000040U /*!<Bit 0 */
+#define ADC_SMPR2_SMP2_1 0x00000080U /*!<Bit 1 */
+#define ADC_SMPR2_SMP2_2 0x00000100U /*!<Bit 2 */
+#define ADC_SMPR2_SMP3 0x00000E00U /*!<SMP3[2:0] bits (Channel 3 Sample time selection) */
+#define ADC_SMPR2_SMP3_0 0x00000200U /*!<Bit 0 */
+#define ADC_SMPR2_SMP3_1 0x00000400U /*!<Bit 1 */
+#define ADC_SMPR2_SMP3_2 0x00000800U /*!<Bit 2 */
+#define ADC_SMPR2_SMP4 0x00007000U /*!<SMP4[2:0] bits (Channel 4 Sample time selection) */
+#define ADC_SMPR2_SMP4_0 0x00001000U /*!<Bit 0 */
+#define ADC_SMPR2_SMP4_1 0x00002000U /*!<Bit 1 */
+#define ADC_SMPR2_SMP4_2 0x00004000U /*!<Bit 2 */
+#define ADC_SMPR2_SMP5 0x00038000U /*!<SMP5[2:0] bits (Channel 5 Sample time selection) */
+#define ADC_SMPR2_SMP5_0 0x00008000U /*!<Bit 0 */
+#define ADC_SMPR2_SMP5_1 0x00010000U /*!<Bit 1 */
+#define ADC_SMPR2_SMP5_2 0x00020000U /*!<Bit 2 */
+#define ADC_SMPR2_SMP6 0x001C0000U /*!<SMP6[2:0] bits (Channel 6 Sample time selection) */
+#define ADC_SMPR2_SMP6_0 0x00040000U /*!<Bit 0 */
+#define ADC_SMPR2_SMP6_1 0x00080000U /*!<Bit 1 */
+#define ADC_SMPR2_SMP6_2 0x00100000U /*!<Bit 2 */
+#define ADC_SMPR2_SMP7 0x00E00000U /*!<SMP7[2:0] bits (Channel 7 Sample time selection) */
+#define ADC_SMPR2_SMP7_0 0x00200000U /*!<Bit 0 */
+#define ADC_SMPR2_SMP7_1 0x00400000U /*!<Bit 1 */
+#define ADC_SMPR2_SMP7_2 0x00800000U /*!<Bit 2 */
+#define ADC_SMPR2_SMP8 0x07000000U /*!<SMP8[2:0] bits (Channel 8 Sample time selection) */
+#define ADC_SMPR2_SMP8_0 0x01000000U /*!<Bit 0 */
+#define ADC_SMPR2_SMP8_1 0x02000000U /*!<Bit 1 */
+#define ADC_SMPR2_SMP8_2 0x04000000U /*!<Bit 2 */
+#define ADC_SMPR2_SMP9 0x38000000U /*!<SMP9[2:0] bits (Channel 9 Sample time selection) */
+#define ADC_SMPR2_SMP9_0 0x08000000U /*!<Bit 0 */
+#define ADC_SMPR2_SMP9_1 0x10000000U /*!<Bit 1 */
+#define ADC_SMPR2_SMP9_2 0x20000000U /*!<Bit 2 */
+
+/****************** Bit definition for ADC_JOFR1 register *******************/
+#define ADC_JOFR1_JOFFSET1 0x0FFFU /*!<Data offset for injected channel 1 */
+
+/****************** Bit definition for ADC_JOFR2 register *******************/
+#define ADC_JOFR2_JOFFSET2 0x0FFFU /*!<Data offset for injected channel 2 */
+
+/****************** Bit definition for ADC_JOFR3 register *******************/
+#define ADC_JOFR3_JOFFSET3 0x0FFFU /*!<Data offset for injected channel 3 */
+
+/****************** Bit definition for ADC_JOFR4 register *******************/
+#define ADC_JOFR4_JOFFSET4 0x0FFFU /*!<Data offset for injected channel 4 */
+
+/******************* Bit definition for ADC_HTR register ********************/
+#define ADC_HTR_HT 0x0FFFU /*!<Analog watchdog high threshold */
+
+/******************* Bit definition for ADC_LTR register ********************/
+#define ADC_LTR_LT 0x0FFFU /*!<Analog watchdog low threshold */
+
+/******************* Bit definition for ADC_SQR1 register *******************/
+#define ADC_SQR1_SQ13 0x0000001FU /*!<SQ13[4:0] bits (13th conversion in regular sequence) */
+#define ADC_SQR1_SQ13_0 0x00000001U /*!<Bit 0 */
+#define ADC_SQR1_SQ13_1 0x00000002U /*!<Bit 1 */
+#define ADC_SQR1_SQ13_2 0x00000004U /*!<Bit 2 */
+#define ADC_SQR1_SQ13_3 0x00000008U /*!<Bit 3 */
+#define ADC_SQR1_SQ13_4 0x00000010U /*!<Bit 4 */
+#define ADC_SQR1_SQ14 0x000003E0U /*!<SQ14[4:0] bits (14th conversion in regular sequence) */
+#define ADC_SQR1_SQ14_0 0x00000020U /*!<Bit 0 */
+#define ADC_SQR1_SQ14_1 0x00000040U /*!<Bit 1 */
+#define ADC_SQR1_SQ14_2 0x00000080U /*!<Bit 2 */
+#define ADC_SQR1_SQ14_3 0x00000100U /*!<Bit 3 */
+#define ADC_SQR1_SQ14_4 0x00000200U /*!<Bit 4 */
+#define ADC_SQR1_SQ15 0x00007C00U /*!<SQ15[4:0] bits (15th conversion in regular sequence) */
+#define ADC_SQR1_SQ15_0 0x00000400U /*!<Bit 0 */
+#define ADC_SQR1_SQ15_1 0x00000800U /*!<Bit 1 */
+#define ADC_SQR1_SQ15_2 0x00001000U /*!<Bit 2 */
+#define ADC_SQR1_SQ15_3 0x00002000U /*!<Bit 3 */
+#define ADC_SQR1_SQ15_4 0x00004000U /*!<Bit 4 */
+#define ADC_SQR1_SQ16 0x000F8000U /*!<SQ16[4:0] bits (16th conversion in regular sequence) */
+#define ADC_SQR1_SQ16_0 0x00008000U /*!<Bit 0 */
+#define ADC_SQR1_SQ16_1 0x00010000U /*!<Bit 1 */
+#define ADC_SQR1_SQ16_2 0x00020000U /*!<Bit 2 */
+#define ADC_SQR1_SQ16_3 0x00040000U /*!<Bit 3 */
+#define ADC_SQR1_SQ16_4 0x00080000U /*!<Bit 4 */
+#define ADC_SQR1_L 0x00F00000U /*!<L[3:0] bits (Regular channel sequence length) */
+#define ADC_SQR1_L_0 0x00100000U /*!<Bit 0 */
+#define ADC_SQR1_L_1 0x00200000U /*!<Bit 1 */
+#define ADC_SQR1_L_2 0x00400000U /*!<Bit 2 */
+#define ADC_SQR1_L_3 0x00800000U /*!<Bit 3 */
+
+/******************* Bit definition for ADC_SQR2 register *******************/
+#define ADC_SQR2_SQ7 0x0000001FU /*!<SQ7[4:0] bits (7th conversion in regular sequence) */
+#define ADC_SQR2_SQ7_0 0x00000001U /*!<Bit 0 */
+#define ADC_SQR2_SQ7_1 0x00000002U /*!<Bit 1 */
+#define ADC_SQR2_SQ7_2 0x00000004U /*!<Bit 2 */
+#define ADC_SQR2_SQ7_3 0x00000008U /*!<Bit 3 */
+#define ADC_SQR2_SQ7_4 0x00000010U /*!<Bit 4 */
+#define ADC_SQR2_SQ8 0x000003E0U /*!<SQ8[4:0] bits (8th conversion in regular sequence) */
+#define ADC_SQR2_SQ8_0 0x00000020U /*!<Bit 0 */
+#define ADC_SQR2_SQ8_1 0x00000040U /*!<Bit 1 */
+#define ADC_SQR2_SQ8_2 0x00000080U /*!<Bit 2 */
+#define ADC_SQR2_SQ8_3 0x00000100U /*!<Bit 3 */
+#define ADC_SQR2_SQ8_4 0x00000200U /*!<Bit 4 */
+#define ADC_SQR2_SQ9 0x00007C00U /*!<SQ9[4:0] bits (9th conversion in regular sequence) */
+#define ADC_SQR2_SQ9_0 0x00000400U /*!<Bit 0 */
+#define ADC_SQR2_SQ9_1 0x00000800U /*!<Bit 1 */
+#define ADC_SQR2_SQ9_2 0x00001000U /*!<Bit 2 */
+#define ADC_SQR2_SQ9_3 0x00002000U /*!<Bit 3 */
+#define ADC_SQR2_SQ9_4 0x00004000U /*!<Bit 4 */
+#define ADC_SQR2_SQ10 0x000F8000U /*!<SQ10[4:0] bits (10th conversion in regular sequence) */
+#define ADC_SQR2_SQ10_0 0x00008000U /*!<Bit 0 */
+#define ADC_SQR2_SQ10_1 0x00010000U /*!<Bit 1 */
+#define ADC_SQR2_SQ10_2 0x00020000U /*!<Bit 2 */
+#define ADC_SQR2_SQ10_3 0x00040000U /*!<Bit 3 */
+#define ADC_SQR2_SQ10_4 0x00080000U /*!<Bit 4 */
+#define ADC_SQR2_SQ11 0x01F00000U /*!<SQ11[4:0] bits (11th conversion in regular sequence) */
+#define ADC_SQR2_SQ11_0 0x00100000U /*!<Bit 0 */
+#define ADC_SQR2_SQ11_1 0x00200000U /*!<Bit 1 */
+#define ADC_SQR2_SQ11_2 0x00400000U /*!<Bit 2 */
+#define ADC_SQR2_SQ11_3 0x00800000U /*!<Bit 3 */
+#define ADC_SQR2_SQ11_4 0x01000000U /*!<Bit 4 */
+#define ADC_SQR2_SQ12 0x3E000000U /*!<SQ12[4:0] bits (12th conversion in regular sequence) */
+#define ADC_SQR2_SQ12_0 0x02000000U /*!<Bit 0 */
+#define ADC_SQR2_SQ12_1 0x04000000U /*!<Bit 1 */
+#define ADC_SQR2_SQ12_2 0x08000000U /*!<Bit 2 */
+#define ADC_SQR2_SQ12_3 0x10000000U /*!<Bit 3 */
+#define ADC_SQR2_SQ12_4 0x20000000U /*!<Bit 4 */
+
+/******************* Bit definition for ADC_SQR3 register *******************/
+#define ADC_SQR3_SQ1 0x0000001FU /*!<SQ1[4:0] bits (1st conversion in regular sequence) */
+#define ADC_SQR3_SQ1_0 0x00000001U /*!<Bit 0 */
+#define ADC_SQR3_SQ1_1 0x00000002U /*!<Bit 1 */
+#define ADC_SQR3_SQ1_2 0x00000004U /*!<Bit 2 */
+#define ADC_SQR3_SQ1_3 0x00000008U /*!<Bit 3 */
+#define ADC_SQR3_SQ1_4 0x00000010U /*!<Bit 4 */
+#define ADC_SQR3_SQ2 0x000003E0U /*!<SQ2[4:0] bits (2nd conversion in regular sequence) */
+#define ADC_SQR3_SQ2_0 0x00000020U /*!<Bit 0 */
+#define ADC_SQR3_SQ2_1 0x00000040U /*!<Bit 1 */
+#define ADC_SQR3_SQ2_2 0x00000080U /*!<Bit 2 */
+#define ADC_SQR3_SQ2_3 0x00000100U /*!<Bit 3 */
+#define ADC_SQR3_SQ2_4 0x00000200U /*!<Bit 4 */
+#define ADC_SQR3_SQ3 0x00007C00U /*!<SQ3[4:0] bits (3rd conversion in regular sequence) */
+#define ADC_SQR3_SQ3_0 0x00000400U /*!<Bit 0 */
+#define ADC_SQR3_SQ3_1 0x00000800U /*!<Bit 1 */
+#define ADC_SQR3_SQ3_2 0x00001000U /*!<Bit 2 */
+#define ADC_SQR3_SQ3_3 0x00002000U /*!<Bit 3 */
+#define ADC_SQR3_SQ3_4 0x00004000U /*!<Bit 4 */
+#define ADC_SQR3_SQ4 0x000F8000U /*!<SQ4[4:0] bits (4th conversion in regular sequence) */
+#define ADC_SQR3_SQ4_0 0x00008000U /*!<Bit 0 */
+#define ADC_SQR3_SQ4_1 0x00010000U /*!<Bit 1 */
+#define ADC_SQR3_SQ4_2 0x00020000U /*!<Bit 2 */
+#define ADC_SQR3_SQ4_3 0x00040000U /*!<Bit 3 */
+#define ADC_SQR3_SQ4_4 0x00080000U /*!<Bit 4 */
+#define ADC_SQR3_SQ5 0x01F00000U /*!<SQ5[4:0] bits (5th conversion in regular sequence) */
+#define ADC_SQR3_SQ5_0 0x00100000U /*!<Bit 0 */
+#define ADC_SQR3_SQ5_1 0x00200000U /*!<Bit 1 */
+#define ADC_SQR3_SQ5_2 0x00400000U /*!<Bit 2 */
+#define ADC_SQR3_SQ5_3 0x00800000U /*!<Bit 3 */
+#define ADC_SQR3_SQ5_4 0x01000000U /*!<Bit 4 */
+#define ADC_SQR3_SQ6 0x3E000000U /*!<SQ6[4:0] bits (6th conversion in regular sequence) */
+#define ADC_SQR3_SQ6_0 0x02000000U /*!<Bit 0 */
+#define ADC_SQR3_SQ6_1 0x04000000U /*!<Bit 1 */
+#define ADC_SQR3_SQ6_2 0x08000000U /*!<Bit 2 */
+#define ADC_SQR3_SQ6_3 0x10000000U /*!<Bit 3 */
+#define ADC_SQR3_SQ6_4 0x20000000U /*!<Bit 4 */
+
+/******************* Bit definition for ADC_JSQR register *******************/
+#define ADC_JSQR_JSQ1 0x0000001FU /*!<JSQ1[4:0] bits (1st conversion in injected sequence) */
+#define ADC_JSQR_JSQ1_0 0x00000001U /*!<Bit 0 */
+#define ADC_JSQR_JSQ1_1 0x00000002U /*!<Bit 1 */
+#define ADC_JSQR_JSQ1_2 0x00000004U /*!<Bit 2 */
+#define ADC_JSQR_JSQ1_3 0x00000008U /*!<Bit 3 */
+#define ADC_JSQR_JSQ1_4 0x00000010U /*!<Bit 4 */
+#define ADC_JSQR_JSQ2 0x000003E0U /*!<JSQ2[4:0] bits (2nd conversion in injected sequence) */
+#define ADC_JSQR_JSQ2_0 0x00000020U /*!<Bit 0 */
+#define ADC_JSQR_JSQ2_1 0x00000040U /*!<Bit 1 */
+#define ADC_JSQR_JSQ2_2 0x00000080U /*!<Bit 2 */
+#define ADC_JSQR_JSQ2_3 0x00000100U /*!<Bit 3 */
+#define ADC_JSQR_JSQ2_4 0x00000200U /*!<Bit 4 */
+#define ADC_JSQR_JSQ3 0x00007C00U /*!<JSQ3[4:0] bits (3rd conversion in injected sequence) */
+#define ADC_JSQR_JSQ3_0 0x00000400U /*!<Bit 0 */
+#define ADC_JSQR_JSQ3_1 0x00000800U /*!<Bit 1 */
+#define ADC_JSQR_JSQ3_2 0x00001000U /*!<Bit 2 */
+#define ADC_JSQR_JSQ3_3 0x00002000U /*!<Bit 3 */
+#define ADC_JSQR_JSQ3_4 0x00004000U /*!<Bit 4 */
+#define ADC_JSQR_JSQ4 0x000F8000U /*!<JSQ4[4:0] bits (4th conversion in injected sequence) */
+#define ADC_JSQR_JSQ4_0 0x00008000U /*!<Bit 0 */
+#define ADC_JSQR_JSQ4_1 0x00010000U /*!<Bit 1 */
+#define ADC_JSQR_JSQ4_2 0x00020000U /*!<Bit 2 */
+#define ADC_JSQR_JSQ4_3 0x00040000U /*!<Bit 3 */
+#define ADC_JSQR_JSQ4_4 0x00080000U /*!<Bit 4 */
+#define ADC_JSQR_JL 0x00300000U /*!<JL[1:0] bits (Injected Sequence length) */
+#define ADC_JSQR_JL_0 0x00100000U /*!<Bit 0 */
+#define ADC_JSQR_JL_1 0x00200000U /*!<Bit 1 */
+
+/******************* Bit definition for ADC_JDR1 register *******************/
+#define ADC_JDR1_JDATA 0xFFFFU /*!<Injected data */
+
+/******************* Bit definition for ADC_JDR2 register *******************/
+#define ADC_JDR2_JDATA 0xFFFFU /*!<Injected data */
+
+/******************* Bit definition for ADC_JDR3 register *******************/
+#define ADC_JDR3_JDATA 0xFFFFU /*!<Injected data */
+
+/******************* Bit definition for ADC_JDR4 register *******************/
+#define ADC_JDR4_JDATA 0xFFFFU /*!<Injected data */
+
+/******************** Bit definition for ADC_DR register ********************/
+#define ADC_DR_DATA 0x0000FFFFU /*!<Regular data */
+#define ADC_DR_ADC2DATA 0xFFFF0000U /*!<ADC2 data */
+
+/******************* Bit definition for ADC_CSR register ********************/
+#define ADC_CSR_AWD1 0x00000001U /*!<ADC1 Analog watchdog flag */
+#define ADC_CSR_EOC1 0x00000002U /*!<ADC1 End of conversion */
+#define ADC_CSR_JEOC1 0x00000004U /*!<ADC1 Injected channel end of conversion */
+#define ADC_CSR_JSTRT1 0x00000008U /*!<ADC1 Injected channel Start flag */
+#define ADC_CSR_STRT1 0x00000010U /*!<ADC1 Regular channel Start flag */
+#define ADC_CSR_OVR1 0x00000020U /*!<ADC1 DMA overrun flag */
+#define ADC_CSR_AWD2 0x00000100U /*!<ADC2 Analog watchdog flag */
+#define ADC_CSR_EOC2 0x00000200U /*!<ADC2 End of conversion */
+#define ADC_CSR_JEOC2 0x00000400U /*!<ADC2 Injected channel end of conversion */
+#define ADC_CSR_JSTRT2 0x00000800U /*!<ADC2 Injected channel Start flag */
+#define ADC_CSR_STRT2 0x00001000U /*!<ADC2 Regular channel Start flag */
+#define ADC_CSR_OVR2 0x00002000U /*!<ADC2 DMA overrun flag */
+#define ADC_CSR_AWD3 0x00010000U /*!<ADC3 Analog watchdog flag */
+#define ADC_CSR_EOC3 0x00020000U /*!<ADC3 End of conversion */
+#define ADC_CSR_JEOC3 0x00040000U /*!<ADC3 Injected channel end of conversion */
+#define ADC_CSR_JSTRT3 0x00080000U /*!<ADC3 Injected channel Start flag */
+#define ADC_CSR_STRT3 0x00100000U /*!<ADC3 Regular channel Start flag */
+#define ADC_CSR_OVR3 0x00200000U /*!<ADC3 DMA overrun flag */
+
+/* Legacy defines */
+#define ADC_CSR_DOVR1 ADC_CSR_OVR1
+#define ADC_CSR_DOVR2 ADC_CSR_OVR2
+#define ADC_CSR_DOVR3 ADC_CSR_OVR3
+
+/******************* Bit definition for ADC_CCR register ********************/
+#define ADC_CCR_MULTI 0x0000001FU /*!<MULTI[4:0] bits (Multi-ADC mode selection) */
+#define ADC_CCR_MULTI_0 0x00000001U /*!<Bit 0 */
+#define ADC_CCR_MULTI_1 0x00000002U /*!<Bit 1 */
+#define ADC_CCR_MULTI_2 0x00000004U /*!<Bit 2 */
+#define ADC_CCR_MULTI_3 0x00000008U /*!<Bit 3 */
+#define ADC_CCR_MULTI_4 0x00000010U /*!<Bit 4 */
+#define ADC_CCR_DELAY 0x00000F00U /*!<DELAY[3:0] bits (Delay between 2 sampling phases) */
+#define ADC_CCR_DELAY_0 0x00000100U /*!<Bit 0 */
+#define ADC_CCR_DELAY_1 0x00000200U /*!<Bit 1 */
+#define ADC_CCR_DELAY_2 0x00000400U /*!<Bit 2 */
+#define ADC_CCR_DELAY_3 0x00000800U /*!<Bit 3 */
+#define ADC_CCR_DDS 0x00002000U /*!<DMA disable selection (Multi-ADC mode) */
+#define ADC_CCR_DMA 0x0000C000U /*!<DMA[1:0] bits (Direct Memory Access mode for multimode) */
+#define ADC_CCR_DMA_0 0x00004000U /*!<Bit 0 */
+#define ADC_CCR_DMA_1 0x00008000U /*!<Bit 1 */
+#define ADC_CCR_ADCPRE 0x00030000U /*!<ADCPRE[1:0] bits (ADC prescaler) */
+#define ADC_CCR_ADCPRE_0 0x00010000U /*!<Bit 0 */
+#define ADC_CCR_ADCPRE_1 0x00020000U /*!<Bit 1 */
+#define ADC_CCR_VBATE 0x00400000U /*!<VBAT Enable */
+#define ADC_CCR_TSVREFE 0x00800000U /*!<Temperature Sensor and VREFINT Enable */
+
+/******************* Bit definition for ADC_CDR register ********************/
+#define ADC_CDR_DATA1 0x0000FFFFU /*!<1st data of a pair of regular conversions */
+#define ADC_CDR_DATA2 0xFFFF0000U /*!<2nd data of a pair of regular conversions */
+
+/******************************************************************************/
+/* */
+/* CRC calculation unit */
+/* */
+/******************************************************************************/
+/******************* Bit definition for CRC_DR register *********************/
+#define CRC_DR_DR 0xFFFFFFFFU /*!< Data register bits */
+
+
+/******************* Bit definition for CRC_IDR register ********************/
+#define CRC_IDR_IDR 0xFFU /*!< General-purpose 8-bit data register bits */
+
+
+/******************** Bit definition for CRC_CR register ********************/
+#define CRC_CR_RESET 0x01U /*!< RESET bit */
+
+/******************************************************************************/
+/* */
+/* Debug MCU */
+/* */
+/******************************************************************************/
+
+/******************************************************************************/
+/* */
+/* DMA Controller */
+/* */
+/******************************************************************************/
+/******************** Bits definition for DMA_SxCR register *****************/
+#define DMA_SxCR_CHSEL 0x0E000000U
+#define DMA_SxCR_CHSEL_0 0x02000000U
+#define DMA_SxCR_CHSEL_1 0x04000000U
+#define DMA_SxCR_CHSEL_2 0x08000000U
+#define DMA_SxCR_MBURST 0x01800000U
+#define DMA_SxCR_MBURST_0 0x00800000U
+#define DMA_SxCR_MBURST_1 0x01000000U
+#define DMA_SxCR_PBURST 0x00600000U
+#define DMA_SxCR_PBURST_0 0x00200000U
+#define DMA_SxCR_PBURST_1 0x00400000U
+#define DMA_SxCR_CT 0x00080000U
+#define DMA_SxCR_DBM 0x00040000U
+#define DMA_SxCR_PL 0x00030000U
+#define DMA_SxCR_PL_0 0x00010000U
+#define DMA_SxCR_PL_1 0x00020000U
+#define DMA_SxCR_PINCOS 0x00008000U
+#define DMA_SxCR_MSIZE 0x00006000U
+#define DMA_SxCR_MSIZE_0 0x00002000U
+#define DMA_SxCR_MSIZE_1 0x00004000U
+#define DMA_SxCR_PSIZE 0x00001800U
+#define DMA_SxCR_PSIZE_0 0x00000800U
+#define DMA_SxCR_PSIZE_1 0x00001000U
+#define DMA_SxCR_MINC 0x00000400U
+#define DMA_SxCR_PINC 0x00000200U
+#define DMA_SxCR_CIRC 0x00000100U
+#define DMA_SxCR_DIR 0x000000C0U
+#define DMA_SxCR_DIR_0 0x00000040U
+#define DMA_SxCR_DIR_1 0x00000080U
+#define DMA_SxCR_PFCTRL 0x00000020U
+#define DMA_SxCR_TCIE 0x00000010U
+#define DMA_SxCR_HTIE 0x00000008U
+#define DMA_SxCR_TEIE 0x00000004U
+#define DMA_SxCR_DMEIE 0x00000002U
+#define DMA_SxCR_EN 0x00000001U
+
+/* Legacy defines */
+#define DMA_SxCR_ACK 0x00100000U
+
+/******************** Bits definition for DMA_SxCNDTR register **************/
+#define DMA_SxNDT 0x0000FFFFU
+#define DMA_SxNDT_0 0x00000001U
+#define DMA_SxNDT_1 0x00000002U
+#define DMA_SxNDT_2 0x00000004U
+#define DMA_SxNDT_3 0x00000008U
+#define DMA_SxNDT_4 0x00000010U
+#define DMA_SxNDT_5 0x00000020U
+#define DMA_SxNDT_6 0x00000040U
+#define DMA_SxNDT_7 0x00000080U
+#define DMA_SxNDT_8 0x00000100U
+#define DMA_SxNDT_9 0x00000200U
+#define DMA_SxNDT_10 0x00000400U
+#define DMA_SxNDT_11 0x00000800U
+#define DMA_SxNDT_12 0x00001000U
+#define DMA_SxNDT_13 0x00002000U
+#define DMA_SxNDT_14 0x00004000U
+#define DMA_SxNDT_15 0x00008000U
+
+/******************** Bits definition for DMA_SxFCR register ****************/
+#define DMA_SxFCR_FEIE 0x00000080U
+#define DMA_SxFCR_FS 0x00000038U
+#define DMA_SxFCR_FS_0 0x00000008U
+#define DMA_SxFCR_FS_1 0x00000010U
+#define DMA_SxFCR_FS_2 0x00000020U
+#define DMA_SxFCR_DMDIS 0x00000004U
+#define DMA_SxFCR_FTH 0x00000003U
+#define DMA_SxFCR_FTH_0 0x00000001U
+#define DMA_SxFCR_FTH_1 0x00000002U
+
+/******************** Bits definition for DMA_LISR register *****************/
+#define DMA_LISR_TCIF3 0x08000000U
+#define DMA_LISR_HTIF3 0x04000000U
+#define DMA_LISR_TEIF3 0x02000000U
+#define DMA_LISR_DMEIF3 0x01000000U
+#define DMA_LISR_FEIF3 0x00400000U
+#define DMA_LISR_TCIF2 0x00200000U
+#define DMA_LISR_HTIF2 0x00100000U
+#define DMA_LISR_TEIF2 0x00080000U
+#define DMA_LISR_DMEIF2 0x00040000U
+#define DMA_LISR_FEIF2 0x00010000U
+#define DMA_LISR_TCIF1 0x00000800U
+#define DMA_LISR_HTIF1 0x00000400U
+#define DMA_LISR_TEIF1 0x00000200U
+#define DMA_LISR_DMEIF1 0x00000100U
+#define DMA_LISR_FEIF1 0x00000040U
+#define DMA_LISR_TCIF0 0x00000020U
+#define DMA_LISR_HTIF0 0x00000010U
+#define DMA_LISR_TEIF0 0x00000008U
+#define DMA_LISR_DMEIF0 0x00000004U
+#define DMA_LISR_FEIF0 0x00000001U
+
+/******************** Bits definition for DMA_HISR register *****************/
+#define DMA_HISR_TCIF7 0x08000000U
+#define DMA_HISR_HTIF7 0x04000000U
+#define DMA_HISR_TEIF7 0x02000000U
+#define DMA_HISR_DMEIF7 0x01000000U
+#define DMA_HISR_FEIF7 0x00400000U
+#define DMA_HISR_TCIF6 0x00200000U
+#define DMA_HISR_HTIF6 0x00100000U
+#define DMA_HISR_TEIF6 0x00080000U
+#define DMA_HISR_DMEIF6 0x00040000U
+#define DMA_HISR_FEIF6 0x00010000U
+#define DMA_HISR_TCIF5 0x00000800U
+#define DMA_HISR_HTIF5 0x00000400U
+#define DMA_HISR_TEIF5 0x00000200U
+#define DMA_HISR_DMEIF5 0x00000100U
+#define DMA_HISR_FEIF5 0x00000040U
+#define DMA_HISR_TCIF4 0x00000020U
+#define DMA_HISR_HTIF4 0x00000010U
+#define DMA_HISR_TEIF4 0x00000008U
+#define DMA_HISR_DMEIF4 0x00000004U
+#define DMA_HISR_FEIF4 0x00000001U
+
+/******************** Bits definition for DMA_LIFCR register ****************/
+#define DMA_LIFCR_CTCIF3 0x08000000U
+#define DMA_LIFCR_CHTIF3 0x04000000U
+#define DMA_LIFCR_CTEIF3 0x02000000U
+#define DMA_LIFCR_CDMEIF3 0x01000000U
+#define DMA_LIFCR_CFEIF3 0x00400000U
+#define DMA_LIFCR_CTCIF2 0x00200000U
+#define DMA_LIFCR_CHTIF2 0x00100000U
+#define DMA_LIFCR_CTEIF2 0x00080000U
+#define DMA_LIFCR_CDMEIF2 0x00040000U
+#define DMA_LIFCR_CFEIF2 0x00010000U
+#define DMA_LIFCR_CTCIF1 0x00000800U
+#define DMA_LIFCR_CHTIF1 0x00000400U
+#define DMA_LIFCR_CTEIF1 0x00000200U
+#define DMA_LIFCR_CDMEIF1 0x00000100U
+#define DMA_LIFCR_CFEIF1 0x00000040U
+#define DMA_LIFCR_CTCIF0 0x00000020U
+#define DMA_LIFCR_CHTIF0 0x00000010U
+#define DMA_LIFCR_CTEIF0 0x00000008U
+#define DMA_LIFCR_CDMEIF0 0x00000004U
+#define DMA_LIFCR_CFEIF0 0x00000001U
+
+/******************** Bits definition for DMA_HIFCR register ****************/
+#define DMA_HIFCR_CTCIF7 0x08000000U
+#define DMA_HIFCR_CHTIF7 0x04000000U
+#define DMA_HIFCR_CTEIF7 0x02000000U
+#define DMA_HIFCR_CDMEIF7 0x01000000U
+#define DMA_HIFCR_CFEIF7 0x00400000U
+#define DMA_HIFCR_CTCIF6 0x00200000U
+#define DMA_HIFCR_CHTIF6 0x00100000U
+#define DMA_HIFCR_CTEIF6 0x00080000U
+#define DMA_HIFCR_CDMEIF6 0x00040000U
+#define DMA_HIFCR_CFEIF6 0x00010000U
+#define DMA_HIFCR_CTCIF5 0x00000800U
+#define DMA_HIFCR_CHTIF5 0x00000400U
+#define DMA_HIFCR_CTEIF5 0x00000200U
+#define DMA_HIFCR_CDMEIF5 0x00000100U
+#define DMA_HIFCR_CFEIF5 0x00000040U
+#define DMA_HIFCR_CTCIF4 0x00000020U
+#define DMA_HIFCR_CHTIF4 0x00000010U
+#define DMA_HIFCR_CTEIF4 0x00000008U
+#define DMA_HIFCR_CDMEIF4 0x00000004U
+#define DMA_HIFCR_CFEIF4 0x00000001U
+
+
+/******************************************************************************/
+/* */
+/* External Interrupt/Event Controller */
+/* */
+/******************************************************************************/
+/******************* Bit definition for EXTI_IMR register *******************/
+#define EXTI_IMR_MR0 0x00000001U /*!< Interrupt Mask on line 0 */
+#define EXTI_IMR_MR1 0x00000002U /*!< Interrupt Mask on line 1 */
+#define EXTI_IMR_MR2 0x00000004U /*!< Interrupt Mask on line 2 */
+#define EXTI_IMR_MR3 0x00000008U /*!< Interrupt Mask on line 3 */
+#define EXTI_IMR_MR4 0x00000010U /*!< Interrupt Mask on line 4 */
+#define EXTI_IMR_MR5 0x00000020U /*!< Interrupt Mask on line 5 */
+#define EXTI_IMR_MR6 0x00000040U /*!< Interrupt Mask on line 6 */
+#define EXTI_IMR_MR7 0x00000080U /*!< Interrupt Mask on line 7 */
+#define EXTI_IMR_MR8 0x00000100U /*!< Interrupt Mask on line 8 */
+#define EXTI_IMR_MR9 0x00000200U /*!< Interrupt Mask on line 9 */
+#define EXTI_IMR_MR10 0x00000400U /*!< Interrupt Mask on line 10 */
+#define EXTI_IMR_MR11 0x00000800U /*!< Interrupt Mask on line 11 */
+#define EXTI_IMR_MR12 0x00001000U /*!< Interrupt Mask on line 12 */
+#define EXTI_IMR_MR13 0x00002000U /*!< Interrupt Mask on line 13 */
+#define EXTI_IMR_MR14 0x00004000U /*!< Interrupt Mask on line 14 */
+#define EXTI_IMR_MR15 0x00008000U /*!< Interrupt Mask on line 15 */
+#define EXTI_IMR_MR16 0x00010000U /*!< Interrupt Mask on line 16 */
+#define EXTI_IMR_MR17 0x00020000U /*!< Interrupt Mask on line 17 */
+#define EXTI_IMR_MR18 0x00040000U /*!< Interrupt Mask on line 18 */
+#define EXTI_IMR_MR19 0x00080000U /*!< Interrupt Mask on line 19 */
+#define EXTI_IMR_MR20 0x00100000U /*!< Interrupt Mask on line 20 */
+#define EXTI_IMR_MR21 0x00200000U /*!< Interrupt Mask on line 21 */
+#define EXTI_IMR_MR22 0x00400000U /*!< Interrupt Mask on line 22 */
+
+/******************* Bit definition for EXTI_EMR register *******************/
+#define EXTI_EMR_MR0 0x00000001U /*!< Event Mask on line 0 */
+#define EXTI_EMR_MR1 0x00000002U /*!< Event Mask on line 1 */
+#define EXTI_EMR_MR2 0x00000004U /*!< Event Mask on line 2 */
+#define EXTI_EMR_MR3 0x00000008U /*!< Event Mask on line 3 */
+#define EXTI_EMR_MR4 0x00000010U /*!< Event Mask on line 4 */
+#define EXTI_EMR_MR5 0x00000020U /*!< Event Mask on line 5 */
+#define EXTI_EMR_MR6 0x00000040U /*!< Event Mask on line 6 */
+#define EXTI_EMR_MR7 0x00000080U /*!< Event Mask on line 7 */
+#define EXTI_EMR_MR8 0x00000100U /*!< Event Mask on line 8 */
+#define EXTI_EMR_MR9 0x00000200U /*!< Event Mask on line 9 */
+#define EXTI_EMR_MR10 0x00000400U /*!< Event Mask on line 10 */
+#define EXTI_EMR_MR11 0x00000800U /*!< Event Mask on line 11 */
+#define EXTI_EMR_MR12 0x00001000U /*!< Event Mask on line 12 */
+#define EXTI_EMR_MR13 0x00002000U /*!< Event Mask on line 13 */
+#define EXTI_EMR_MR14 0x00004000U /*!< Event Mask on line 14 */
+#define EXTI_EMR_MR15 0x00008000U /*!< Event Mask on line 15 */
+#define EXTI_EMR_MR16 0x00010000U /*!< Event Mask on line 16 */
+#define EXTI_EMR_MR17 0x00020000U /*!< Event Mask on line 17 */
+#define EXTI_EMR_MR18 0x00040000U /*!< Event Mask on line 18 */
+#define EXTI_EMR_MR19 0x00080000U /*!< Event Mask on line 19 */
+#define EXTI_EMR_MR20 0x00100000U /*!< Event Mask on line 20 */
+#define EXTI_EMR_MR21 0x00200000U /*!< Event Mask on line 21 */
+#define EXTI_EMR_MR22 0x00400000U /*!< Event Mask on line 22 */
+
+/****************** Bit definition for EXTI_RTSR register *******************/
+#define EXTI_RTSR_TR0 0x00000001U /*!< Rising trigger event configuration bit of line 0 */
+#define EXTI_RTSR_TR1 0x00000002U /*!< Rising trigger event configuration bit of line 1 */
+#define EXTI_RTSR_TR2 0x00000004U /*!< Rising trigger event configuration bit of line 2 */
+#define EXTI_RTSR_TR3 0x00000008U /*!< Rising trigger event configuration bit of line 3 */
+#define EXTI_RTSR_TR4 0x00000010U /*!< Rising trigger event configuration bit of line 4 */
+#define EXTI_RTSR_TR5 0x00000020U /*!< Rising trigger event configuration bit of line 5 */
+#define EXTI_RTSR_TR6 0x00000040U /*!< Rising trigger event configuration bit of line 6 */
+#define EXTI_RTSR_TR7 0x00000080U /*!< Rising trigger event configuration bit of line 7 */
+#define EXTI_RTSR_TR8 0x00000100U /*!< Rising trigger event configuration bit of line 8 */
+#define EXTI_RTSR_TR9 0x00000200U /*!< Rising trigger event configuration bit of line 9 */
+#define EXTI_RTSR_TR10 0x00000400U /*!< Rising trigger event configuration bit of line 10 */
+#define EXTI_RTSR_TR11 0x00000800U /*!< Rising trigger event configuration bit of line 11 */
+#define EXTI_RTSR_TR12 0x00001000U /*!< Rising trigger event configuration bit of line 12 */
+#define EXTI_RTSR_TR13 0x00002000U /*!< Rising trigger event configuration bit of line 13 */
+#define EXTI_RTSR_TR14 0x00004000U /*!< Rising trigger event configuration bit of line 14 */
+#define EXTI_RTSR_TR15 0x00008000U /*!< Rising trigger event configuration bit of line 15 */
+#define EXTI_RTSR_TR16 0x00010000U /*!< Rising trigger event configuration bit of line 16 */
+#define EXTI_RTSR_TR17 0x00020000U /*!< Rising trigger event configuration bit of line 17 */
+#define EXTI_RTSR_TR18 0x00040000U /*!< Rising trigger event configuration bit of line 18 */
+#define EXTI_RTSR_TR19 0x00080000U /*!< Rising trigger event configuration bit of line 19 */
+#define EXTI_RTSR_TR20 0x00100000U /*!< Rising trigger event configuration bit of line 20 */
+#define EXTI_RTSR_TR21 0x00200000U /*!< Rising trigger event configuration bit of line 21 */
+#define EXTI_RTSR_TR22 0x00400000U /*!< Rising trigger event configuration bit of line 22 */
+
+/****************** Bit definition for EXTI_FTSR register *******************/
+#define EXTI_FTSR_TR0 0x00000001U /*!< Falling trigger event configuration bit of line 0 */
+#define EXTI_FTSR_TR1 0x00000002U /*!< Falling trigger event configuration bit of line 1 */
+#define EXTI_FTSR_TR2 0x00000004U /*!< Falling trigger event configuration bit of line 2 */
+#define EXTI_FTSR_TR3 0x00000008U /*!< Falling trigger event configuration bit of line 3 */
+#define EXTI_FTSR_TR4 0x00000010U /*!< Falling trigger event configuration bit of line 4 */
+#define EXTI_FTSR_TR5 0x00000020U /*!< Falling trigger event configuration bit of line 5 */
+#define EXTI_FTSR_TR6 0x00000040U /*!< Falling trigger event configuration bit of line 6 */
+#define EXTI_FTSR_TR7 0x00000080U /*!< Falling trigger event configuration bit of line 7 */
+#define EXTI_FTSR_TR8 0x00000100U /*!< Falling trigger event configuration bit of line 8 */
+#define EXTI_FTSR_TR9 0x00000200U /*!< Falling trigger event configuration bit of line 9 */
+#define EXTI_FTSR_TR10 0x00000400U /*!< Falling trigger event configuration bit of line 10 */
+#define EXTI_FTSR_TR11 0x00000800U /*!< Falling trigger event configuration bit of line 11 */
+#define EXTI_FTSR_TR12 0x00001000U /*!< Falling trigger event configuration bit of line 12 */
+#define EXTI_FTSR_TR13 0x00002000U /*!< Falling trigger event configuration bit of line 13 */
+#define EXTI_FTSR_TR14 0x00004000U /*!< Falling trigger event configuration bit of line 14 */
+#define EXTI_FTSR_TR15 0x00008000U /*!< Falling trigger event configuration bit of line 15 */
+#define EXTI_FTSR_TR16 0x00010000U /*!< Falling trigger event configuration bit of line 16 */
+#define EXTI_FTSR_TR17 0x00020000U /*!< Falling trigger event configuration bit of line 17 */
+#define EXTI_FTSR_TR18 0x00040000U /*!< Falling trigger event configuration bit of line 18 */
+#define EXTI_FTSR_TR19 0x00080000U /*!< Falling trigger event configuration bit of line 19 */
+#define EXTI_FTSR_TR20 0x00100000U /*!< Falling trigger event configuration bit of line 20 */
+#define EXTI_FTSR_TR21 0x00200000U /*!< Falling trigger event configuration bit of line 21 */
+#define EXTI_FTSR_TR22 0x00400000U /*!< Falling trigger event configuration bit of line 22 */
+
+/****************** Bit definition for EXTI_SWIER register ******************/
+#define EXTI_SWIER_SWIER0 0x00000001U /*!< Software Interrupt on line 0 */
+#define EXTI_SWIER_SWIER1 0x00000002U /*!< Software Interrupt on line 1 */
+#define EXTI_SWIER_SWIER2 0x00000004U /*!< Software Interrupt on line 2 */
+#define EXTI_SWIER_SWIER3 0x00000008U /*!< Software Interrupt on line 3 */
+#define EXTI_SWIER_SWIER4 0x00000010U /*!< Software Interrupt on line 4 */
+#define EXTI_SWIER_SWIER5 0x00000020U /*!< Software Interrupt on line 5 */
+#define EXTI_SWIER_SWIER6 0x00000040U /*!< Software Interrupt on line 6 */
+#define EXTI_SWIER_SWIER7 0x00000080U /*!< Software Interrupt on line 7 */
+#define EXTI_SWIER_SWIER8 0x00000100U /*!< Software Interrupt on line 8 */
+#define EXTI_SWIER_SWIER9 0x00000200U /*!< Software Interrupt on line 9 */
+#define EXTI_SWIER_SWIER10 0x00000400U /*!< Software Interrupt on line 10 */
+#define EXTI_SWIER_SWIER11 0x00000800U /*!< Software Interrupt on line 11 */
+#define EXTI_SWIER_SWIER12 0x00001000U /*!< Software Interrupt on line 12 */
+#define EXTI_SWIER_SWIER13 0x00002000U /*!< Software Interrupt on line 13 */
+#define EXTI_SWIER_SWIER14 0x00004000U /*!< Software Interrupt on line 14 */
+#define EXTI_SWIER_SWIER15 0x00008000U /*!< Software Interrupt on line 15 */
+#define EXTI_SWIER_SWIER16 0x00010000U /*!< Software Interrupt on line 16 */
+#define EXTI_SWIER_SWIER17 0x00020000U /*!< Software Interrupt on line 17 */
+#define EXTI_SWIER_SWIER18 0x00040000U /*!< Software Interrupt on line 18 */
+#define EXTI_SWIER_SWIER19 0x00080000U /*!< Software Interrupt on line 19 */
+#define EXTI_SWIER_SWIER20 0x00100000U /*!< Software Interrupt on line 20 */
+#define EXTI_SWIER_SWIER21 0x00200000U /*!< Software Interrupt on line 21 */
+#define EXTI_SWIER_SWIER22 0x00400000U /*!< Software Interrupt on line 22 */
+
+/******************* Bit definition for EXTI_PR register ********************/
+#define EXTI_PR_PR0 0x00000001U /*!< Pending bit for line 0 */
+#define EXTI_PR_PR1 0x00000002U /*!< Pending bit for line 1 */
+#define EXTI_PR_PR2 0x00000004U /*!< Pending bit for line 2 */
+#define EXTI_PR_PR3 0x00000008U /*!< Pending bit for line 3 */
+#define EXTI_PR_PR4 0x00000010U /*!< Pending bit for line 4 */
+#define EXTI_PR_PR5 0x00000020U /*!< Pending bit for line 5 */
+#define EXTI_PR_PR6 0x00000040U /*!< Pending bit for line 6 */
+#define EXTI_PR_PR7 0x00000080U /*!< Pending bit for line 7 */
+#define EXTI_PR_PR8 0x00000100U /*!< Pending bit for line 8 */
+#define EXTI_PR_PR9 0x00000200U /*!< Pending bit for line 9 */
+#define EXTI_PR_PR10 0x00000400U /*!< Pending bit for line 10 */
+#define EXTI_PR_PR11 0x00000800U /*!< Pending bit for line 11 */
+#define EXTI_PR_PR12 0x00001000U /*!< Pending bit for line 12 */
+#define EXTI_PR_PR13 0x00002000U /*!< Pending bit for line 13 */
+#define EXTI_PR_PR14 0x00004000U /*!< Pending bit for line 14 */
+#define EXTI_PR_PR15 0x00008000U /*!< Pending bit for line 15 */
+#define EXTI_PR_PR16 0x00010000U /*!< Pending bit for line 16 */
+#define EXTI_PR_PR17 0x00020000U /*!< Pending bit for line 17 */
+#define EXTI_PR_PR18 0x00040000U /*!< Pending bit for line 18 */
+#define EXTI_PR_PR19 0x00080000U /*!< Pending bit for line 19 */
+#define EXTI_PR_PR20 0x00100000U /*!< Pending bit for line 20 */
+#define EXTI_PR_PR21 0x00200000U /*!< Pending bit for line 21 */
+#define EXTI_PR_PR22 0x00400000U /*!< Pending bit for line 22 */
+
+/******************************************************************************/
+/* */
+/* FLASH */
+/* */
+/******************************************************************************/
+/******************* Bits definition for FLASH_ACR register *****************/
+#define FLASH_ACR_LATENCY 0x0000000FU
+#define FLASH_ACR_LATENCY_0WS 0x00000000U
+#define FLASH_ACR_LATENCY_1WS 0x00000001U
+#define FLASH_ACR_LATENCY_2WS 0x00000002U
+#define FLASH_ACR_LATENCY_3WS 0x00000003U
+#define FLASH_ACR_LATENCY_4WS 0x00000004U
+#define FLASH_ACR_LATENCY_5WS 0x00000005U
+#define FLASH_ACR_LATENCY_6WS 0x00000006U
+#define FLASH_ACR_LATENCY_7WS 0x00000007U
+
+#define FLASH_ACR_PRFTEN 0x00000100U
+#define FLASH_ACR_ICEN 0x00000200U
+#define FLASH_ACR_DCEN 0x00000400U
+#define FLASH_ACR_ICRST 0x00000800U
+#define FLASH_ACR_DCRST 0x00001000U
+#define FLASH_ACR_BYTE0_ADDRESS 0x40023C00U
+#define FLASH_ACR_BYTE2_ADDRESS 0x40023C03U
+
+/******************* Bits definition for FLASH_SR register ******************/
+#define FLASH_SR_EOP 0x00000001U
+#define FLASH_SR_SOP 0x00000002U
+#define FLASH_SR_WRPERR 0x00000010U
+#define FLASH_SR_PGAERR 0x00000020U
+#define FLASH_SR_PGPERR 0x00000040U
+#define FLASH_SR_PGSERR 0x00000080U
+#define FLASH_SR_BSY 0x00010000U
+
+/******************* Bits definition for FLASH_CR register ******************/
+#define FLASH_CR_PG 0x00000001U
+#define FLASH_CR_SER 0x00000002U
+#define FLASH_CR_MER 0x00000004U
+#define FLASH_CR_SNB 0x000000F8U
+#define FLASH_CR_SNB_0 0x00000008U
+#define FLASH_CR_SNB_1 0x00000010U
+#define FLASH_CR_SNB_2 0x00000020U
+#define FLASH_CR_SNB_3 0x00000040U
+#define FLASH_CR_SNB_4 0x00000080U
+#define FLASH_CR_PSIZE 0x00000300U
+#define FLASH_CR_PSIZE_0 0x00000100U
+#define FLASH_CR_PSIZE_1 0x00000200U
+#define FLASH_CR_STRT 0x00010000U
+#define FLASH_CR_EOPIE 0x01000000U
+#define FLASH_CR_LOCK 0x80000000U
+
+/******************* Bits definition for FLASH_OPTCR register ***************/
+#define FLASH_OPTCR_OPTLOCK 0x00000001U
+#define FLASH_OPTCR_OPTSTRT 0x00000002U
+#define FLASH_OPTCR_BOR_LEV_0 0x00000004U
+#define FLASH_OPTCR_BOR_LEV_1 0x00000008U
+#define FLASH_OPTCR_BOR_LEV 0x0000000CU
+
+#define FLASH_OPTCR_WDG_SW 0x00000020U
+#define FLASH_OPTCR_nRST_STOP 0x00000040U
+#define FLASH_OPTCR_nRST_STDBY 0x00000080U
+#define FLASH_OPTCR_RDP 0x0000FF00U
+#define FLASH_OPTCR_RDP_0 0x00000100U
+#define FLASH_OPTCR_RDP_1 0x00000200U
+#define FLASH_OPTCR_RDP_2 0x00000400U
+#define FLASH_OPTCR_RDP_3 0x00000800U
+#define FLASH_OPTCR_RDP_4 0x00001000U
+#define FLASH_OPTCR_RDP_5 0x00002000U
+#define FLASH_OPTCR_RDP_6 0x00004000U
+#define FLASH_OPTCR_RDP_7 0x00008000U
+#define FLASH_OPTCR_nWRP 0x0FFF0000U
+#define FLASH_OPTCR_nWRP_0 0x00010000U
+#define FLASH_OPTCR_nWRP_1 0x00020000U
+#define FLASH_OPTCR_nWRP_2 0x00040000U
+#define FLASH_OPTCR_nWRP_3 0x00080000U
+#define FLASH_OPTCR_nWRP_4 0x00100000U
+#define FLASH_OPTCR_nWRP_5 0x00200000U
+#define FLASH_OPTCR_nWRP_6 0x00400000U
+#define FLASH_OPTCR_nWRP_7 0x00800000U
+#define FLASH_OPTCR_nWRP_8 0x01000000U
+#define FLASH_OPTCR_nWRP_9 0x02000000U
+#define FLASH_OPTCR_nWRP_10 0x04000000U
+#define FLASH_OPTCR_nWRP_11 0x08000000U
+
+/****************** Bits definition for FLASH_OPTCR1 register ***************/
+#define FLASH_OPTCR1_nWRP 0x0FFF0000U
+#define FLASH_OPTCR1_nWRP_0 0x00010000U
+#define FLASH_OPTCR1_nWRP_1 0x00020000U
+#define FLASH_OPTCR1_nWRP_2 0x00040000U
+#define FLASH_OPTCR1_nWRP_3 0x00080000U
+#define FLASH_OPTCR1_nWRP_4 0x00100000U
+#define FLASH_OPTCR1_nWRP_5 0x00200000U
+#define FLASH_OPTCR1_nWRP_6 0x00400000U
+#define FLASH_OPTCR1_nWRP_7 0x00800000U
+#define FLASH_OPTCR1_nWRP_8 0x01000000U
+#define FLASH_OPTCR1_nWRP_9 0x02000000U
+#define FLASH_OPTCR1_nWRP_10 0x04000000U
+#define FLASH_OPTCR1_nWRP_11 0x08000000U
+
+/******************************************************************************/
+/* */
+/* General Purpose I/O */
+/* */
+/******************************************************************************/
+/****************** Bits definition for GPIO_MODER register *****************/
+#define GPIO_MODER_MODER0 0x00000003U
+#define GPIO_MODER_MODER0_0 0x00000001U
+#define GPIO_MODER_MODER0_1 0x00000002U
+
+#define GPIO_MODER_MODER1 0x0000000CU
+#define GPIO_MODER_MODER1_0 0x00000004U
+#define GPIO_MODER_MODER1_1 0x00000008U
+
+#define GPIO_MODER_MODER2 0x00000030U
+#define GPIO_MODER_MODER2_0 0x00000010U
+#define GPIO_MODER_MODER2_1 0x00000020U
+
+#define GPIO_MODER_MODER3 0x000000C0U
+#define GPIO_MODER_MODER3_0 0x00000040U
+#define GPIO_MODER_MODER3_1 0x00000080U
+
+#define GPIO_MODER_MODER4 0x00000300U
+#define GPIO_MODER_MODER4_0 0x00000100U
+#define GPIO_MODER_MODER4_1 0x00000200U
+
+#define GPIO_MODER_MODER5 0x00000C00U
+#define GPIO_MODER_MODER5_0 0x00000400U
+#define GPIO_MODER_MODER5_1 0x00000800U
+
+#define GPIO_MODER_MODER6 0x00003000U
+#define GPIO_MODER_MODER6_0 0x00001000U
+#define GPIO_MODER_MODER6_1 0x00002000U
+
+#define GPIO_MODER_MODER7 0x0000C000U
+#define GPIO_MODER_MODER7_0 0x00004000U
+#define GPIO_MODER_MODER7_1 0x00008000U
+
+#define GPIO_MODER_MODER8 0x00030000U
+#define GPIO_MODER_MODER8_0 0x00010000U
+#define GPIO_MODER_MODER8_1 0x00020000U
+
+#define GPIO_MODER_MODER9 0x000C0000U
+#define GPIO_MODER_MODER9_0 0x00040000U
+#define GPIO_MODER_MODER9_1 0x00080000U
+
+#define GPIO_MODER_MODER10 0x00300000U
+#define GPIO_MODER_MODER10_0 0x00100000U
+#define GPIO_MODER_MODER10_1 0x00200000U
+
+#define GPIO_MODER_MODER11 0x00C00000U
+#define GPIO_MODER_MODER11_0 0x00400000U
+#define GPIO_MODER_MODER11_1 0x00800000U
+
+#define GPIO_MODER_MODER12 0x03000000U
+#define GPIO_MODER_MODER12_0 0x01000000U
+#define GPIO_MODER_MODER12_1 0x02000000U
+
+#define GPIO_MODER_MODER13 0x0C000000U
+#define GPIO_MODER_MODER13_0 0x04000000U
+#define GPIO_MODER_MODER13_1 0x08000000U
+
+#define GPIO_MODER_MODER14 0x30000000U
+#define GPIO_MODER_MODER14_0 0x10000000U
+#define GPIO_MODER_MODER14_1 0x20000000U
+
+#define GPIO_MODER_MODER15 0xC0000000U
+#define GPIO_MODER_MODER15_0 0x40000000U
+#define GPIO_MODER_MODER15_1 0x80000000U
+
+/****************** Bits definition for GPIO_OTYPER register ****************/
+#define GPIO_OTYPER_OT_0 0x00000001U
+#define GPIO_OTYPER_OT_1 0x00000002U
+#define GPIO_OTYPER_OT_2 0x00000004U
+#define GPIO_OTYPER_OT_3 0x00000008U
+#define GPIO_OTYPER_OT_4 0x00000010U
+#define GPIO_OTYPER_OT_5 0x00000020U
+#define GPIO_OTYPER_OT_6 0x00000040U
+#define GPIO_OTYPER_OT_7 0x00000080U
+#define GPIO_OTYPER_OT_8 0x00000100U
+#define GPIO_OTYPER_OT_9 0x00000200U
+#define GPIO_OTYPER_OT_10 0x00000400U
+#define GPIO_OTYPER_OT_11 0x00000800U
+#define GPIO_OTYPER_OT_12 0x00001000U
+#define GPIO_OTYPER_OT_13 0x00002000U
+#define GPIO_OTYPER_OT_14 0x00004000U
+#define GPIO_OTYPER_OT_15 0x00008000U
+
+/****************** Bits definition for GPIO_OSPEEDR register ***************/
+#define GPIO_OSPEEDER_OSPEEDR0 0x00000003U
+#define GPIO_OSPEEDER_OSPEEDR0_0 0x00000001U
+#define GPIO_OSPEEDER_OSPEEDR0_1 0x00000002U
+
+#define GPIO_OSPEEDER_OSPEEDR1 0x0000000CU
+#define GPIO_OSPEEDER_OSPEEDR1_0 0x00000004U
+#define GPIO_OSPEEDER_OSPEEDR1_1 0x00000008U
+
+#define GPIO_OSPEEDER_OSPEEDR2 0x00000030U
+#define GPIO_OSPEEDER_OSPEEDR2_0 0x00000010U
+#define GPIO_OSPEEDER_OSPEEDR2_1 0x00000020U
+
+#define GPIO_OSPEEDER_OSPEEDR3 0x000000C0U
+#define GPIO_OSPEEDER_OSPEEDR3_0 0x00000040U
+#define GPIO_OSPEEDER_OSPEEDR3_1 0x00000080U
+
+#define GPIO_OSPEEDER_OSPEEDR4 0x00000300U
+#define GPIO_OSPEEDER_OSPEEDR4_0 0x00000100U
+#define GPIO_OSPEEDER_OSPEEDR4_1 0x00000200U
+
+#define GPIO_OSPEEDER_OSPEEDR5 0x00000C00U
+#define GPIO_OSPEEDER_OSPEEDR5_0 0x00000400U
+#define GPIO_OSPEEDER_OSPEEDR5_1 0x00000800U
+
+#define GPIO_OSPEEDER_OSPEEDR6 0x00003000U
+#define GPIO_OSPEEDER_OSPEEDR6_0 0x00001000U
+#define GPIO_OSPEEDER_OSPEEDR6_1 0x00002000U
+
+#define GPIO_OSPEEDER_OSPEEDR7 0x0000C000U
+#define GPIO_OSPEEDER_OSPEEDR7_0 0x00004000U
+#define GPIO_OSPEEDER_OSPEEDR7_1 0x00008000U
+
+#define GPIO_OSPEEDER_OSPEEDR8 0x00030000U
+#define GPIO_OSPEEDER_OSPEEDR8_0 0x00010000U
+#define GPIO_OSPEEDER_OSPEEDR8_1 0x00020000U
+
+#define GPIO_OSPEEDER_OSPEEDR9 0x000C0000U
+#define GPIO_OSPEEDER_OSPEEDR9_0 0x00040000U
+#define GPIO_OSPEEDER_OSPEEDR9_1 0x00080000U
+
+#define GPIO_OSPEEDER_OSPEEDR10 0x00300000U
+#define GPIO_OSPEEDER_OSPEEDR10_0 0x00100000U
+#define GPIO_OSPEEDER_OSPEEDR10_1 0x00200000U
+
+#define GPIO_OSPEEDER_OSPEEDR11 0x00C00000U
+#define GPIO_OSPEEDER_OSPEEDR11_0 0x00400000U
+#define GPIO_OSPEEDER_OSPEEDR11_1 0x00800000U
+
+#define GPIO_OSPEEDER_OSPEEDR12 0x03000000U
+#define GPIO_OSPEEDER_OSPEEDR12_0 0x01000000U
+#define GPIO_OSPEEDER_OSPEEDR12_1 0x02000000U
+
+#define GPIO_OSPEEDER_OSPEEDR13 0x0C000000U
+#define GPIO_OSPEEDER_OSPEEDR13_0 0x04000000U
+#define GPIO_OSPEEDER_OSPEEDR13_1 0x08000000U
+
+#define GPIO_OSPEEDER_OSPEEDR14 0x30000000U
+#define GPIO_OSPEEDER_OSPEEDR14_0 0x10000000U
+#define GPIO_OSPEEDER_OSPEEDR14_1 0x20000000U
+
+#define GPIO_OSPEEDER_OSPEEDR15 0xC0000000U
+#define GPIO_OSPEEDER_OSPEEDR15_0 0x40000000U
+#define GPIO_OSPEEDER_OSPEEDR15_1 0x80000000U
+
+/****************** Bits definition for GPIO_PUPDR register *****************/
+#define GPIO_PUPDR_PUPDR0 0x00000003U
+#define GPIO_PUPDR_PUPDR0_0 0x00000001U
+#define GPIO_PUPDR_PUPDR0_1 0x00000002U
+
+#define GPIO_PUPDR_PUPDR1 0x0000000CU
+#define GPIO_PUPDR_PUPDR1_0 0x00000004U
+#define GPIO_PUPDR_PUPDR1_1 0x00000008U
+
+#define GPIO_PUPDR_PUPDR2 0x00000030U
+#define GPIO_PUPDR_PUPDR2_0 0x00000010U
+#define GPIO_PUPDR_PUPDR2_1 0x00000020U
+
+#define GPIO_PUPDR_PUPDR3 0x000000C0U
+#define GPIO_PUPDR_PUPDR3_0 0x00000040U
+#define GPIO_PUPDR_PUPDR3_1 0x00000080U
+
+#define GPIO_PUPDR_PUPDR4 0x00000300U
+#define GPIO_PUPDR_PUPDR4_0 0x00000100U
+#define GPIO_PUPDR_PUPDR4_1 0x00000200U
+
+#define GPIO_PUPDR_PUPDR5 0x00000C00U
+#define GPIO_PUPDR_PUPDR5_0 0x00000400U
+#define GPIO_PUPDR_PUPDR5_1 0x00000800U
+
+#define GPIO_PUPDR_PUPDR6 0x00003000U
+#define GPIO_PUPDR_PUPDR6_0 0x00001000U
+#define GPIO_PUPDR_PUPDR6_1 0x00002000U
+
+#define GPIO_PUPDR_PUPDR7 0x0000C000U
+#define GPIO_PUPDR_PUPDR7_0 0x00004000U
+#define GPIO_PUPDR_PUPDR7_1 0x00008000U
+
+#define GPIO_PUPDR_PUPDR8 0x00030000U
+#define GPIO_PUPDR_PUPDR8_0 0x00010000U
+#define GPIO_PUPDR_PUPDR8_1 0x00020000U
+
+#define GPIO_PUPDR_PUPDR9 0x000C0000U
+#define GPIO_PUPDR_PUPDR9_0 0x00040000U
+#define GPIO_PUPDR_PUPDR9_1 0x00080000U
+
+#define GPIO_PUPDR_PUPDR10 0x00300000U
+#define GPIO_PUPDR_PUPDR10_0 0x00100000U
+#define GPIO_PUPDR_PUPDR10_1 0x00200000U
+
+#define GPIO_PUPDR_PUPDR11 0x00C00000U
+#define GPIO_PUPDR_PUPDR11_0 0x00400000U
+#define GPIO_PUPDR_PUPDR11_1 0x00800000U
+
+#define GPIO_PUPDR_PUPDR12 0x03000000U
+#define GPIO_PUPDR_PUPDR12_0 0x01000000U
+#define GPIO_PUPDR_PUPDR12_1 0x02000000U
+
+#define GPIO_PUPDR_PUPDR13 0x0C000000U
+#define GPIO_PUPDR_PUPDR13_0 0x04000000U
+#define GPIO_PUPDR_PUPDR13_1 0x08000000U
+
+#define GPIO_PUPDR_PUPDR14 0x30000000U
+#define GPIO_PUPDR_PUPDR14_0 0x10000000U
+#define GPIO_PUPDR_PUPDR14_1 0x20000000U
+
+#define GPIO_PUPDR_PUPDR15 0xC0000000U
+#define GPIO_PUPDR_PUPDR15_0 0x40000000U
+#define GPIO_PUPDR_PUPDR15_1 0x80000000U
+
+/****************** Bits definition for GPIO_IDR register *******************/
+#define GPIO_IDR_IDR_0 0x00000001U
+#define GPIO_IDR_IDR_1 0x00000002U
+#define GPIO_IDR_IDR_2 0x00000004U
+#define GPIO_IDR_IDR_3 0x00000008U
+#define GPIO_IDR_IDR_4 0x00000010U
+#define GPIO_IDR_IDR_5 0x00000020U
+#define GPIO_IDR_IDR_6 0x00000040U
+#define GPIO_IDR_IDR_7 0x00000080U
+#define GPIO_IDR_IDR_8 0x00000100U
+#define GPIO_IDR_IDR_9 0x00000200U
+#define GPIO_IDR_IDR_10 0x00000400U
+#define GPIO_IDR_IDR_11 0x00000800U
+#define GPIO_IDR_IDR_12 0x00001000U
+#define GPIO_IDR_IDR_13 0x00002000U
+#define GPIO_IDR_IDR_14 0x00004000U
+#define GPIO_IDR_IDR_15 0x00008000U
+/* Old GPIO_IDR register bits definition, maintained for legacy purpose */
+#define GPIO_OTYPER_IDR_0 GPIO_IDR_IDR_0
+#define GPIO_OTYPER_IDR_1 GPIO_IDR_IDR_1
+#define GPIO_OTYPER_IDR_2 GPIO_IDR_IDR_2
+#define GPIO_OTYPER_IDR_3 GPIO_IDR_IDR_3
+#define GPIO_OTYPER_IDR_4 GPIO_IDR_IDR_4
+#define GPIO_OTYPER_IDR_5 GPIO_IDR_IDR_5
+#define GPIO_OTYPER_IDR_6 GPIO_IDR_IDR_6
+#define GPIO_OTYPER_IDR_7 GPIO_IDR_IDR_7
+#define GPIO_OTYPER_IDR_8 GPIO_IDR_IDR_8
+#define GPIO_OTYPER_IDR_9 GPIO_IDR_IDR_9
+#define GPIO_OTYPER_IDR_10 GPIO_IDR_IDR_10
+#define GPIO_OTYPER_IDR_11 GPIO_IDR_IDR_11
+#define GPIO_OTYPER_IDR_12 GPIO_IDR_IDR_12
+#define GPIO_OTYPER_IDR_13 GPIO_IDR_IDR_13
+#define GPIO_OTYPER_IDR_14 GPIO_IDR_IDR_14
+#define GPIO_OTYPER_IDR_15 GPIO_IDR_IDR_15
+
+/****************** Bits definition for GPIO_ODR register *******************/
+#define GPIO_ODR_ODR_0 0x00000001U
+#define GPIO_ODR_ODR_1 0x00000002U
+#define GPIO_ODR_ODR_2 0x00000004U
+#define GPIO_ODR_ODR_3 0x00000008U
+#define GPIO_ODR_ODR_4 0x00000010U
+#define GPIO_ODR_ODR_5 0x00000020U
+#define GPIO_ODR_ODR_6 0x00000040U
+#define GPIO_ODR_ODR_7 0x00000080U
+#define GPIO_ODR_ODR_8 0x00000100U
+#define GPIO_ODR_ODR_9 0x00000200U
+#define GPIO_ODR_ODR_10 0x00000400U
+#define GPIO_ODR_ODR_11 0x00000800U
+#define GPIO_ODR_ODR_12 0x00001000U
+#define GPIO_ODR_ODR_13 0x00002000U
+#define GPIO_ODR_ODR_14 0x00004000U
+#define GPIO_ODR_ODR_15 0x00008000U
+/* Old GPIO_ODR register bits definition, maintained for legacy purpose */
+#define GPIO_OTYPER_ODR_0 GPIO_ODR_ODR_0
+#define GPIO_OTYPER_ODR_1 GPIO_ODR_ODR_1
+#define GPIO_OTYPER_ODR_2 GPIO_ODR_ODR_2
+#define GPIO_OTYPER_ODR_3 GPIO_ODR_ODR_3
+#define GPIO_OTYPER_ODR_4 GPIO_ODR_ODR_4
+#define GPIO_OTYPER_ODR_5 GPIO_ODR_ODR_5
+#define GPIO_OTYPER_ODR_6 GPIO_ODR_ODR_6
+#define GPIO_OTYPER_ODR_7 GPIO_ODR_ODR_7
+#define GPIO_OTYPER_ODR_8 GPIO_ODR_ODR_8
+#define GPIO_OTYPER_ODR_9 GPIO_ODR_ODR_9
+#define GPIO_OTYPER_ODR_10 GPIO_ODR_ODR_10
+#define GPIO_OTYPER_ODR_11 GPIO_ODR_ODR_11
+#define GPIO_OTYPER_ODR_12 GPIO_ODR_ODR_12
+#define GPIO_OTYPER_ODR_13 GPIO_ODR_ODR_13
+#define GPIO_OTYPER_ODR_14 GPIO_ODR_ODR_14
+#define GPIO_OTYPER_ODR_15 GPIO_ODR_ODR_15
+
+/****************** Bits definition for GPIO_BSRR register ******************/
+#define GPIO_BSRR_BS_0 0x00000001U
+#define GPIO_BSRR_BS_1 0x00000002U
+#define GPIO_BSRR_BS_2 0x00000004U
+#define GPIO_BSRR_BS_3 0x00000008U
+#define GPIO_BSRR_BS_4 0x00000010U
+#define GPIO_BSRR_BS_5 0x00000020U
+#define GPIO_BSRR_BS_6 0x00000040U
+#define GPIO_BSRR_BS_7 0x00000080U
+#define GPIO_BSRR_BS_8 0x00000100U
+#define GPIO_BSRR_BS_9 0x00000200U
+#define GPIO_BSRR_BS_10 0x00000400U
+#define GPIO_BSRR_BS_11 0x00000800U
+#define GPIO_BSRR_BS_12 0x00001000U
+#define GPIO_BSRR_BS_13 0x00002000U
+#define GPIO_BSRR_BS_14 0x00004000U
+#define GPIO_BSRR_BS_15 0x00008000U
+#define GPIO_BSRR_BR_0 0x00010000U
+#define GPIO_BSRR_BR_1 0x00020000U
+#define GPIO_BSRR_BR_2 0x00040000U
+#define GPIO_BSRR_BR_3 0x00080000U
+#define GPIO_BSRR_BR_4 0x00100000U
+#define GPIO_BSRR_BR_5 0x00200000U
+#define GPIO_BSRR_BR_6 0x00400000U
+#define GPIO_BSRR_BR_7 0x00800000U
+#define GPIO_BSRR_BR_8 0x01000000U
+#define GPIO_BSRR_BR_9 0x02000000U
+#define GPIO_BSRR_BR_10 0x04000000U
+#define GPIO_BSRR_BR_11 0x08000000U
+#define GPIO_BSRR_BR_12 0x10000000U
+#define GPIO_BSRR_BR_13 0x20000000U
+#define GPIO_BSRR_BR_14 0x40000000U
+#define GPIO_BSRR_BR_15 0x80000000U
+
+/****************** Bit definition for GPIO_LCKR register *********************/
+#define GPIO_LCKR_LCK0 0x00000001U
+#define GPIO_LCKR_LCK1 0x00000002U
+#define GPIO_LCKR_LCK2 0x00000004U
+#define GPIO_LCKR_LCK3 0x00000008U
+#define GPIO_LCKR_LCK4 0x00000010U
+#define GPIO_LCKR_LCK5 0x00000020U
+#define GPIO_LCKR_LCK6 0x00000040U
+#define GPIO_LCKR_LCK7 0x00000080U
+#define GPIO_LCKR_LCK8 0x00000100U
+#define GPIO_LCKR_LCK9 0x00000200U
+#define GPIO_LCKR_LCK10 0x00000400U
+#define GPIO_LCKR_LCK11 0x00000800U
+#define GPIO_LCKR_LCK12 0x00001000U
+#define GPIO_LCKR_LCK13 0x00002000U
+#define GPIO_LCKR_LCK14 0x00004000U
+#define GPIO_LCKR_LCK15 0x00008000U
+#define GPIO_LCKR_LCKK 0x00010000U
+
+/******************************************************************************/
+/* */
+/* Inter-integrated Circuit Interface */
+/* */
+/******************************************************************************/
+/******************* Bit definition for I2C_CR1 register ********************/
+#define I2C_CR1_PE 0x00000001U /*!<Peripheral Enable */
+#define I2C_CR1_SMBUS 0x00000002U /*!<SMBus Mode */
+#define I2C_CR1_SMBTYPE 0x00000008U /*!<SMBus Type */
+#define I2C_CR1_ENARP 0x00000010U /*!<ARP Enable */
+#define I2C_CR1_ENPEC 0x00000020U /*!<PEC Enable */
+#define I2C_CR1_ENGC 0x00000040U /*!<General Call Enable */
+#define I2C_CR1_NOSTRETCH 0x00000080U /*!<Clock Stretching Disable (Slave mode) */
+#define I2C_CR1_START 0x00000100U /*!<Start Generation */
+#define I2C_CR1_STOP 0x00000200U /*!<Stop Generation */
+#define I2C_CR1_ACK 0x00000400U /*!<Acknowledge Enable */
+#define I2C_CR1_POS 0x00000800U /*!<Acknowledge/PEC Position (for data reception) */
+#define I2C_CR1_PEC 0x00001000U /*!<Packet Error Checking */
+#define I2C_CR1_ALERT 0x00002000U /*!<SMBus Alert */
+#define I2C_CR1_SWRST 0x00008000U /*!<Software Reset */
+
+/******************* Bit definition for I2C_CR2 register ********************/
+#define I2C_CR2_FREQ 0x0000003FU /*!<FREQ[5:0] bits (Peripheral Clock Frequency) */
+#define I2C_CR2_FREQ_0 0x00000001U /*!<Bit 0 */
+#define I2C_CR2_FREQ_1 0x00000002U /*!<Bit 1 */
+#define I2C_CR2_FREQ_2 0x00000004U /*!<Bit 2 */
+#define I2C_CR2_FREQ_3 0x00000008U /*!<Bit 3 */
+#define I2C_CR2_FREQ_4 0x00000010U /*!<Bit 4 */
+#define I2C_CR2_FREQ_5 0x00000020U /*!<Bit 5 */
+
+#define I2C_CR2_ITERREN 0x00000100U /*!<Error Interrupt Enable */
+#define I2C_CR2_ITEVTEN 0x00000200U /*!<Event Interrupt Enable */
+#define I2C_CR2_ITBUFEN 0x00000400U /*!<Buffer Interrupt Enable */
+#define I2C_CR2_DMAEN 0x00000800U /*!<DMA Requests Enable */
+#define I2C_CR2_LAST 0x00001000U /*!<DMA Last Transfer */
+
+/******************* Bit definition for I2C_OAR1 register *******************/
+#define I2C_OAR1_ADD1_7 0x000000FEU /*!<Interface Address */
+#define I2C_OAR1_ADD8_9 0x00000300U /*!<Interface Address */
+
+#define I2C_OAR1_ADD0 0x00000001U /*!<Bit 0 */
+#define I2C_OAR1_ADD1 0x00000002U /*!<Bit 1 */
+#define I2C_OAR1_ADD2 0x00000004U /*!<Bit 2 */
+#define I2C_OAR1_ADD3 0x00000008U /*!<Bit 3 */
+#define I2C_OAR1_ADD4 0x00000010U /*!<Bit 4 */
+#define I2C_OAR1_ADD5 0x00000020U /*!<Bit 5 */
+#define I2C_OAR1_ADD6 0x00000040U /*!<Bit 6 */
+#define I2C_OAR1_ADD7 0x00000080U /*!<Bit 7 */
+#define I2C_OAR1_ADD8 0x00000100U /*!<Bit 8 */
+#define I2C_OAR1_ADD9 0x00000200U /*!<Bit 9 */
+
+#define I2C_OAR1_ADDMODE 0x00008000U /*!<Addressing Mode (Slave mode) */
+
+/******************* Bit definition for I2C_OAR2 register *******************/
+#define I2C_OAR2_ENDUAL 0x00000001U /*!<Dual addressing mode enable */
+#define I2C_OAR2_ADD2 0x000000FEU /*!<Interface address */
+
+/******************** Bit definition for I2C_DR register ********************/
+#define I2C_DR_DR 0x000000FFU /*!<8-bit Data Register */
+
+/******************* Bit definition for I2C_SR1 register ********************/
+#define I2C_SR1_SB 0x00000001U /*!<Start Bit (Master mode) */
+#define I2C_SR1_ADDR 0x00000002U /*!<Address sent (master mode)/matched (slave mode) */
+#define I2C_SR1_BTF 0x00000004U /*!<Byte Transfer Finished */
+#define I2C_SR1_ADD10 0x00000008U /*!<10-bit header sent (Master mode) */
+#define I2C_SR1_STOPF 0x00000010U /*!<Stop detection (Slave mode) */
+#define I2C_SR1_RXNE 0x00000040U /*!<Data Register not Empty (receivers) */
+#define I2C_SR1_TXE 0x00000080U /*!<Data Register Empty (transmitters) */
+#define I2C_SR1_BERR 0x00000100U /*!<Bus Error */
+#define I2C_SR1_ARLO 0x00000200U /*!<Arbitration Lost (master mode) */
+#define I2C_SR1_AF 0x00000400U /*!<Acknowledge Failure */
+#define I2C_SR1_OVR 0x00000800U /*!<Overrun/Underrun */
+#define I2C_SR1_PECERR 0x00001000U /*!<PEC Error in reception */
+#define I2C_SR1_TIMEOUT 0x00004000U /*!<Timeout or Tlow Error */
+#define I2C_SR1_SMBALERT 0x00008000U /*!<SMBus Alert */
+
+/******************* Bit definition for I2C_SR2 register ********************/
+#define I2C_SR2_MSL 0x00000001U /*!<Master/Slave */
+#define I2C_SR2_BUSY 0x00000002U /*!<Bus Busy */
+#define I2C_SR2_TRA 0x00000004U /*!<Transmitter/Receiver */
+#define I2C_SR2_GENCALL 0x00000010U /*!<General Call Address (Slave mode) */
+#define I2C_SR2_SMBDEFAULT 0x00000020U /*!<SMBus Device Default Address (Slave mode) */
+#define I2C_SR2_SMBHOST 0x00000040U /*!<SMBus Host Header (Slave mode) */
+#define I2C_SR2_DUALF 0x00000080U /*!<Dual Flag (Slave mode) */
+#define I2C_SR2_PEC 0x0000FF00U /*!<Packet Error Checking Register */
+
+/******************* Bit definition for I2C_CCR register ********************/
+#define I2C_CCR_CCR 0x00000FFFU /*!<Clock Control Register in Fast/Standard mode (Master mode) */
+#define I2C_CCR_DUTY 0x00004000U /*!<Fast Mode Duty Cycle */
+#define I2C_CCR_FS 0x00008000U /*!<I2C Master Mode Selection */
+
+/****************** Bit definition for I2C_TRISE register *******************/
+#define I2C_TRISE_TRISE 0x0000003FU /*!<Maximum Rise Time in Fast/Standard mode (Master mode) */
+
+/****************** Bit definition for I2C_FLTR register *******************/
+#define I2C_FLTR_DNF 0x0000000FU /*!<Digital Noise Filter */
+#define I2C_FLTR_ANOFF 0x00000010U /*!<Analog Noise Filter OFF */
+
+/******************************************************************************/
+/* */
+/* Independent WATCHDOG */
+/* */
+/******************************************************************************/
+/******************* Bit definition for IWDG_KR register ********************/
+#define IWDG_KR_KEY 0xFFFFU /*!<Key value (write only, read 0000h) */
+
+/******************* Bit definition for IWDG_PR register ********************/
+#define IWDG_PR_PR 0x07U /*!<PR[2:0] (Prescaler divider) */
+#define IWDG_PR_PR_0 0x01U /*!<Bit 0 */
+#define IWDG_PR_PR_1 0x02U /*!<Bit 1 */
+#define IWDG_PR_PR_2 0x04U /*!<Bit 2 */
+
+/******************* Bit definition for IWDG_RLR register *******************/
+#define IWDG_RLR_RL 0x0FFFU /*!<Watchdog counter reload value */
+
+/******************* Bit definition for IWDG_SR register ********************/
+#define IWDG_SR_PVU 0x01U /*!<Watchdog prescaler value update */
+#define IWDG_SR_RVU 0x02U /*!<Watchdog counter reload value update */
+
+
+/******************************************************************************/
+/* */
+/* Power Control */
+/* */
+/******************************************************************************/
+/******************** Bit definition for PWR_CR register ********************/
+#define PWR_CR_LPDS 0x00000001U /*!< Low-Power Deepsleep */
+#define PWR_CR_PDDS 0x00000002U /*!< Power Down Deepsleep */
+#define PWR_CR_CWUF 0x00000004U /*!< Clear Wakeup Flag */
+#define PWR_CR_CSBF 0x00000008U /*!< Clear Standby Flag */
+#define PWR_CR_PVDE 0x00000010U /*!< Power Voltage Detector Enable */
+
+#define PWR_CR_PLS 0x000000E0U /*!< PLS[2:0] bits (PVD Level Selection) */
+#define PWR_CR_PLS_0 0x00000020U /*!< Bit 0 */
+#define PWR_CR_PLS_1 0x00000040U /*!< Bit 1 */
+#define PWR_CR_PLS_2 0x00000080U /*!< Bit 2 */
+
+/*!< PVD level configuration */
+#define PWR_CR_PLS_LEV0 0x00000000U /*!< PVD level 0 */
+#define PWR_CR_PLS_LEV1 0x00000020U /*!< PVD level 1 */
+#define PWR_CR_PLS_LEV2 0x00000040U /*!< PVD level 2 */
+#define PWR_CR_PLS_LEV3 0x00000060U /*!< PVD level 3 */
+#define PWR_CR_PLS_LEV4 0x00000080U /*!< PVD level 4 */
+#define PWR_CR_PLS_LEV5 0x000000A0U /*!< PVD level 5 */
+#define PWR_CR_PLS_LEV6 0x000000C0U /*!< PVD level 6 */
+#define PWR_CR_PLS_LEV7 0x000000E0U /*!< PVD level 7 */
+
+#define PWR_CR_DBP 0x00000100U /*!< Disable Backup Domain write protection */
+#define PWR_CR_FPDS 0x00000200U /*!< Flash power down in Stop mode */
+#define PWR_CR_LPLVDS 0x00000400U /*!< Low Power Regulator Low Voltage in Deep Sleep mode */
+#define PWR_CR_MRLVDS 0x00000800U /*!< Main Regulator Low Voltage in Deep Sleep mode */
+#define PWR_CR_ADCDC1 0x00002000U /*!< Refer to AN4073 on how to use this bit */
+#define PWR_CR_VOS 0x0000C000U /*!< VOS[1:0] bits (Regulator voltage scaling output selection) */
+#define PWR_CR_VOS_0 0x00004000U /*!< Bit 0 */
+#define PWR_CR_VOS_1 0x00008000U /*!< Bit 1 */
+
+/* Legacy define */
+#define PWR_CR_PMODE PWR_CR_VOS
+
+/******************* Bit definition for PWR_CSR register ********************/
+#define PWR_CSR_WUF 0x00000001U /*!< Wakeup Flag */
+#define PWR_CSR_SBF 0x00000002U /*!< Standby Flag */
+#define PWR_CSR_PVDO 0x00000004U /*!< PVD Output */
+#define PWR_CSR_BRR 0x00000008U /*!< Backup regulator ready */
+#define PWR_CSR_EWUP 0x00000100U /*!< Enable WKUP pin */
+#define PWR_CSR_BRE 0x00000200U /*!< Backup regulator enable */
+#define PWR_CSR_VOSRDY 0x00004000U /*!< Regulator voltage scaling output selection ready */
+
+/* Legacy define */
+#define PWR_CSR_REGRDY PWR_CSR_VOSRDY
+
+/******************************************************************************/
+/* */
+/* Reset and Clock Control */
+/* */
+/******************************************************************************/
+/******************** Bit definition for RCC_CR register ********************/
+#define RCC_CR_HSION 0x00000001U
+#define RCC_CR_HSIRDY 0x00000002U
+
+#define RCC_CR_HSITRIM 0x000000F8U
+#define RCC_CR_HSITRIM_0 0x00000008U/*!<Bit 0 */
+#define RCC_CR_HSITRIM_1 0x00000010U/*!<Bit 1 */
+#define RCC_CR_HSITRIM_2 0x00000020U/*!<Bit 2 */
+#define RCC_CR_HSITRIM_3 0x00000040U/*!<Bit 3 */
+#define RCC_CR_HSITRIM_4 0x00000080U/*!<Bit 4 */
+
+#define RCC_CR_HSICAL 0x0000FF00U
+#define RCC_CR_HSICAL_0 0x00000100U/*!<Bit 0 */
+#define RCC_CR_HSICAL_1 0x00000200U/*!<Bit 1 */
+#define RCC_CR_HSICAL_2 0x00000400U/*!<Bit 2 */
+#define RCC_CR_HSICAL_3 0x00000800U/*!<Bit 3 */
+#define RCC_CR_HSICAL_4 0x00001000U/*!<Bit 4 */
+#define RCC_CR_HSICAL_5 0x00002000U/*!<Bit 5 */
+#define RCC_CR_HSICAL_6 0x00004000U/*!<Bit 6 */
+#define RCC_CR_HSICAL_7 0x00008000U/*!<Bit 7 */
+
+#define RCC_CR_HSEON 0x00010000U
+#define RCC_CR_HSERDY 0x00020000U
+#define RCC_CR_HSEBYP 0x00040000U
+#define RCC_CR_CSSON 0x00080000U
+#define RCC_CR_PLLON 0x01000000U
+#define RCC_CR_PLLRDY 0x02000000U
+#define RCC_CR_PLLI2SON 0x04000000U
+#define RCC_CR_PLLI2SRDY 0x08000000U
+
+/******************** Bit definition for RCC_PLLCFGR register ***************/
+#define RCC_PLLCFGR_PLLM 0x0000003FU
+#define RCC_PLLCFGR_PLLM_0 0x00000001U
+#define RCC_PLLCFGR_PLLM_1 0x00000002U
+#define RCC_PLLCFGR_PLLM_2 0x00000004U
+#define RCC_PLLCFGR_PLLM_3 0x00000008U
+#define RCC_PLLCFGR_PLLM_4 0x00000010U
+#define RCC_PLLCFGR_PLLM_5 0x00000020U
+
+#define RCC_PLLCFGR_PLLN 0x00007FC0U
+#define RCC_PLLCFGR_PLLN_0 0x00000040U
+#define RCC_PLLCFGR_PLLN_1 0x00000080U
+#define RCC_PLLCFGR_PLLN_2 0x00000100U
+#define RCC_PLLCFGR_PLLN_3 0x00000200U
+#define RCC_PLLCFGR_PLLN_4 0x00000400U
+#define RCC_PLLCFGR_PLLN_5 0x00000800U
+#define RCC_PLLCFGR_PLLN_6 0x00001000U
+#define RCC_PLLCFGR_PLLN_7 0x00002000U
+#define RCC_PLLCFGR_PLLN_8 0x00004000U
+
+#define RCC_PLLCFGR_PLLP 0x00030000U
+#define RCC_PLLCFGR_PLLP_0 0x00010000U
+#define RCC_PLLCFGR_PLLP_1 0x00020000U
+
+#define RCC_PLLCFGR_PLLSRC 0x00400000U
+#define RCC_PLLCFGR_PLLSRC_HSE 0x00400000U
+#define RCC_PLLCFGR_PLLSRC_HSI 0x00000000U
+
+#define RCC_PLLCFGR_PLLQ 0x0F000000U
+#define RCC_PLLCFGR_PLLQ_0 0x01000000U
+#define RCC_PLLCFGR_PLLQ_1 0x02000000U
+#define RCC_PLLCFGR_PLLQ_2 0x04000000U
+#define RCC_PLLCFGR_PLLQ_3 0x08000000U
+
+/******************** Bit definition for RCC_CFGR register ******************/
+/*!< SW configuration */
+#define RCC_CFGR_SW 0x00000003U /*!< SW[1:0] bits (System clock Switch) */
+#define RCC_CFGR_SW_0 0x00000001U /*!< Bit 0 */
+#define RCC_CFGR_SW_1 0x00000002U /*!< Bit 1 */
+
+#define RCC_CFGR_SW_HSI 0x00000000U /*!< HSI selected as system clock */
+#define RCC_CFGR_SW_HSE 0x00000001U /*!< HSE selected as system clock */
+#define RCC_CFGR_SW_PLL 0x00000002U /*!< PLL selected as system clock */
+
+/*!< SWS configuration */
+#define RCC_CFGR_SWS 0x0000000CU /*!< SWS[1:0] bits (System Clock Switch Status) */
+#define RCC_CFGR_SWS_0 0x00000004U /*!< Bit 0 */
+#define RCC_CFGR_SWS_1 0x00000008U /*!< Bit 1 */
+
+#define RCC_CFGR_SWS_HSI 0x00000000U /*!< HSI oscillator used as system clock */
+#define RCC_CFGR_SWS_HSE 0x00000004U /*!< HSE oscillator used as system clock */
+#define RCC_CFGR_SWS_PLL 0x00000008U /*!< PLL used as system clock */
+
+/*!< HPRE configuration */
+#define RCC_CFGR_HPRE 0x000000F0U /*!< HPRE[3:0] bits (AHB prescaler) */
+#define RCC_CFGR_HPRE_0 0x00000010U /*!< Bit 0 */
+#define RCC_CFGR_HPRE_1 0x00000020U /*!< Bit 1 */
+#define RCC_CFGR_HPRE_2 0x00000040U /*!< Bit 2 */
+#define RCC_CFGR_HPRE_3 0x00000080U /*!< Bit 3 */
+
+#define RCC_CFGR_HPRE_DIV1 0x00000000U /*!< SYSCLK not divided */
+#define RCC_CFGR_HPRE_DIV2 0x00000080U /*!< SYSCLK divided by 2 */
+#define RCC_CFGR_HPRE_DIV4 0x00000090U /*!< SYSCLK divided by 4 */
+#define RCC_CFGR_HPRE_DIV8 0x000000A0U /*!< SYSCLK divided by 8 */
+#define RCC_CFGR_HPRE_DIV16 0x000000B0U /*!< SYSCLK divided by 16 */
+#define RCC_CFGR_HPRE_DIV64 0x000000C0U /*!< SYSCLK divided by 64 */
+#define RCC_CFGR_HPRE_DIV128 0x000000D0U /*!< SYSCLK divided by 128 */
+#define RCC_CFGR_HPRE_DIV256 0x000000E0U /*!< SYSCLK divided by 256 */
+#define RCC_CFGR_HPRE_DIV512 0x000000F0U /*!< SYSCLK divided by 512 */
+
+/*!< PPRE1 configuration */
+#define RCC_CFGR_PPRE1 0x00001C00U /*!< PRE1[2:0] bits (APB1 prescaler) */
+#define RCC_CFGR_PPRE1_0 0x00000400U /*!< Bit 0 */
+#define RCC_CFGR_PPRE1_1 0x00000800U /*!< Bit 1 */
+#define RCC_CFGR_PPRE1_2 0x00001000U /*!< Bit 2 */
+
+#define RCC_CFGR_PPRE1_DIV1 0x00000000U /*!< HCLK not divided */
+#define RCC_CFGR_PPRE1_DIV2 0x00001000U /*!< HCLK divided by 2 */
+#define RCC_CFGR_PPRE1_DIV4 0x00001400U /*!< HCLK divided by 4 */
+#define RCC_CFGR_PPRE1_DIV8 0x00001800U /*!< HCLK divided by 8 */
+#define RCC_CFGR_PPRE1_DIV16 0x00001C00U /*!< HCLK divided by 16 */
+
+/*!< PPRE2 configuration */
+#define RCC_CFGR_PPRE2 0x0000E000U /*!< PRE2[2:0] bits (APB2 prescaler) */
+#define RCC_CFGR_PPRE2_0 0x00002000U /*!< Bit 0 */
+#define RCC_CFGR_PPRE2_1 0x00004000U /*!< Bit 1 */
+#define RCC_CFGR_PPRE2_2 0x00008000U /*!< Bit 2 */
+
+#define RCC_CFGR_PPRE2_DIV1 0x00000000U /*!< HCLK not divided */
+#define RCC_CFGR_PPRE2_DIV2 0x00008000U /*!< HCLK divided by 2 */
+#define RCC_CFGR_PPRE2_DIV4 0x0000A000U /*!< HCLK divided by 4 */
+#define RCC_CFGR_PPRE2_DIV8 0x0000C000U /*!< HCLK divided by 8 */
+#define RCC_CFGR_PPRE2_DIV16 0x0000E000U /*!< HCLK divided by 16 */
+
+/*!< RTCPRE configuration */
+#define RCC_CFGR_RTCPRE 0x001F0000U
+#define RCC_CFGR_RTCPRE_0 0x00010000U
+#define RCC_CFGR_RTCPRE_1 0x00020000U
+#define RCC_CFGR_RTCPRE_2 0x00040000U
+#define RCC_CFGR_RTCPRE_3 0x00080000U
+#define RCC_CFGR_RTCPRE_4 0x00100000U
+
+/*!< MCO1 configuration */
+#define RCC_CFGR_MCO1 0x00600000U
+#define RCC_CFGR_MCO1_0 0x00200000U
+#define RCC_CFGR_MCO1_1 0x00400000U
+
+#define RCC_CFGR_I2SSRC 0x00800000U
+
+#define RCC_CFGR_MCO1PRE 0x07000000U
+#define RCC_CFGR_MCO1PRE_0 0x01000000U
+#define RCC_CFGR_MCO1PRE_1 0x02000000U
+#define RCC_CFGR_MCO1PRE_2 0x04000000U
+
+#define RCC_CFGR_MCO2PRE 0x38000000U
+#define RCC_CFGR_MCO2PRE_0 0x08000000U
+#define RCC_CFGR_MCO2PRE_1 0x10000000U
+#define RCC_CFGR_MCO2PRE_2 0x20000000U
+
+#define RCC_CFGR_MCO2 0xC0000000U
+#define RCC_CFGR_MCO2_0 0x40000000U
+#define RCC_CFGR_MCO2_1 0x80000000U
+
+/******************** Bit definition for RCC_CIR register *******************/
+#define RCC_CIR_LSIRDYF 0x00000001U
+#define RCC_CIR_LSERDYF 0x00000002U
+#define RCC_CIR_HSIRDYF 0x00000004U
+#define RCC_CIR_HSERDYF 0x00000008U
+#define RCC_CIR_PLLRDYF 0x00000010U
+#define RCC_CIR_PLLI2SRDYF 0x00000020U
+
+#define RCC_CIR_CSSF 0x00000080U
+#define RCC_CIR_LSIRDYIE 0x00000100U
+#define RCC_CIR_LSERDYIE 0x00000200U
+#define RCC_CIR_HSIRDYIE 0x00000400U
+#define RCC_CIR_HSERDYIE 0x00000800U
+#define RCC_CIR_PLLRDYIE 0x00001000U
+#define RCC_CIR_PLLI2SRDYIE 0x00002000U
+
+#define RCC_CIR_LSIRDYC 0x00010000U
+#define RCC_CIR_LSERDYC 0x00020000U
+#define RCC_CIR_HSIRDYC 0x00040000U
+#define RCC_CIR_HSERDYC 0x00080000U
+#define RCC_CIR_PLLRDYC 0x00100000U
+#define RCC_CIR_PLLI2SRDYC 0x00200000U
+
+#define RCC_CIR_CSSC 0x00800000U
+
+/******************** Bit definition for RCC_AHB1RSTR register **************/
+#define RCC_AHB1RSTR_GPIOARST 0x00000001U
+#define RCC_AHB1RSTR_GPIOBRST 0x00000002U
+#define RCC_AHB1RSTR_GPIOCRST 0x00000004U
+#define RCC_AHB1RSTR_GPIODRST 0x00000008U
+#define RCC_AHB1RSTR_GPIOERST 0x00000010U
+#define RCC_AHB1RSTR_GPIOHRST 0x00000080U
+#define RCC_AHB1RSTR_CRCRST 0x00001000U
+#define RCC_AHB1RSTR_DMA1RST 0x00200000U
+#define RCC_AHB1RSTR_DMA2RST 0x00400000U
+
+/******************** Bit definition for RCC_AHB2RSTR register **************/
+#define RCC_AHB2RSTR_OTGFSRST 0x00000080U
+
+/******************** Bit definition for RCC_AHB3RSTR register **************/
+
+/******************** Bit definition for RCC_APB1RSTR register **************/
+#define RCC_APB1RSTR_TIM2RST 0x00000001U
+#define RCC_APB1RSTR_TIM3RST 0x00000002U
+#define RCC_APB1RSTR_TIM4RST 0x00000004U
+#define RCC_APB1RSTR_TIM5RST 0x00000008U
+#define RCC_APB1RSTR_WWDGRST 0x00000800U
+#define RCC_APB1RSTR_SPI2RST 0x00004000U
+#define RCC_APB1RSTR_SPI3RST 0x00008000U
+#define RCC_APB1RSTR_USART2RST 0x00020000U
+#define RCC_APB1RSTR_I2C1RST 0x00200000U
+#define RCC_APB1RSTR_I2C2RST 0x00400000U
+#define RCC_APB1RSTR_I2C3RST 0x00800000U
+#define RCC_APB1RSTR_PWRRST 0x10000000U
+
+/******************** Bit definition for RCC_APB2RSTR register **************/
+#define RCC_APB2RSTR_TIM1RST 0x00000001U
+#define RCC_APB2RSTR_USART1RST 0x00000010U
+#define RCC_APB2RSTR_USART6RST 0x00000020U
+#define RCC_APB2RSTR_ADCRST 0x00000100U
+#define RCC_APB2RSTR_SDIORST 0x00000800U
+#define RCC_APB2RSTR_SPI1RST 0x00001000U
+#define RCC_APB2RSTR_SPI4RST 0x00002000U
+#define RCC_APB2RSTR_SYSCFGRST 0x00004000U
+#define RCC_APB2RSTR_TIM9RST 0x00010000U
+#define RCC_APB2RSTR_TIM10RST 0x00020000U
+#define RCC_APB2RSTR_TIM11RST 0x00040000U
+
+/* Old SPI1RST bit definition, maintained for legacy purpose */
+#define RCC_APB2RSTR_SPI1 RCC_APB2RSTR_SPI1RST
+
+/******************** Bit definition for RCC_AHB1ENR register ***************/
+#define RCC_AHB1ENR_GPIOAEN 0x00000001U
+#define RCC_AHB1ENR_GPIOBEN 0x00000002U
+#define RCC_AHB1ENR_GPIOCEN 0x00000004U
+#define RCC_AHB1ENR_GPIODEN 0x00000008U
+#define RCC_AHB1ENR_GPIOEEN 0x00000010U
+#define RCC_AHB1ENR_GPIOHEN 0x00000080U
+#define RCC_AHB1ENR_CRCEN 0x00001000U
+#define RCC_AHB1ENR_BKPSRAMEN 0x00040000U
+#define RCC_AHB1ENR_DMA1EN 0x00200000U
+#define RCC_AHB1ENR_DMA2EN 0x00400000U
+
+/******************** Bit definition for RCC_AHB2ENR register ***************/
+#define RCC_AHB2ENR_OTGFSEN 0x00000080U
+
+/******************** Bit definition for RCC_AHB3ENR register ***************/
+
+/******************** Bit definition for RCC_APB1ENR register ***************/
+#define RCC_APB1ENR_TIM2EN 0x00000001U
+#define RCC_APB1ENR_TIM3EN 0x00000002U
+#define RCC_APB1ENR_TIM4EN 0x00000004U
+#define RCC_APB1ENR_TIM5EN 0x00000008U
+#define RCC_APB1ENR_WWDGEN 0x00000800U
+#define RCC_APB1ENR_SPI2EN 0x00004000U
+#define RCC_APB1ENR_SPI3EN 0x00008000U
+#define RCC_APB1ENR_USART2EN 0x00020000U
+#define RCC_APB1ENR_I2C1EN 0x00200000U
+#define RCC_APB1ENR_I2C2EN 0x00400000U
+#define RCC_APB1ENR_I2C3EN 0x00800000U
+#define RCC_APB1ENR_PWREN 0x10000000U
+
+/******************** Bit definition for RCC_APB2ENR register ***************/
+#define RCC_APB2ENR_TIM1EN 0x00000001U
+#define RCC_APB2ENR_USART1EN 0x00000010U
+#define RCC_APB2ENR_USART6EN 0x00000020U
+#define RCC_APB2ENR_ADC1EN 0x00000100U
+#define RCC_APB2ENR_SDIOEN 0x00000800U
+#define RCC_APB2ENR_SPI1EN 0x00001000U
+#define RCC_APB2ENR_SPI4EN 0x00002000U
+#define RCC_APB2ENR_SYSCFGEN 0x00004000U
+#define RCC_APB2ENR_TIM9EN 0x00010000U
+#define RCC_APB2ENR_TIM10EN 0x00020000U
+#define RCC_APB2ENR_TIM11EN 0x00040000U
+
+/******************** Bit definition for RCC_AHB1LPENR register *************/
+#define RCC_AHB1LPENR_GPIOALPEN 0x00000001U
+#define RCC_AHB1LPENR_GPIOBLPEN 0x00000002U
+#define RCC_AHB1LPENR_GPIOCLPEN 0x00000004U
+#define RCC_AHB1LPENR_GPIODLPEN 0x00000008U
+#define RCC_AHB1LPENR_GPIOELPEN 0x00000010U
+#define RCC_AHB1LPENR_GPIOHLPEN 0x00000080U
+#define RCC_AHB1LPENR_CRCLPEN 0x00001000U
+#define RCC_AHB1LPENR_FLITFLPEN 0x00008000U
+#define RCC_AHB1LPENR_SRAM1LPEN 0x00010000U
+#define RCC_AHB1LPENR_SRAM2LPEN 0x00020000U
+#define RCC_AHB1LPENR_BKPSRAMLPEN 0x00040000U
+#define RCC_AHB1LPENR_DMA1LPEN 0x00200000U
+#define RCC_AHB1LPENR_DMA2LPEN 0x00400000U
+
+/******************** Bit definition for RCC_AHB2LPENR register *************/
+#define RCC_AHB2LPENR_OTGFSLPEN 0x00000080U
+
+/******************** Bit definition for RCC_AHB3LPENR register *************/
+
+/******************** Bit definition for RCC_APB1LPENR register *************/
+#define RCC_APB1LPENR_TIM2LPEN 0x00000001U
+#define RCC_APB1LPENR_TIM3LPEN 0x00000002U
+#define RCC_APB1LPENR_TIM4LPEN 0x00000004U
+#define RCC_APB1LPENR_TIM5LPEN 0x00000008U
+#define RCC_APB1LPENR_WWDGLPEN 0x00000800U
+#define RCC_APB1LPENR_SPI2LPEN 0x00004000U
+#define RCC_APB1LPENR_SPI3LPEN 0x00008000U
+#define RCC_APB1LPENR_USART2LPEN 0x00020000U
+#define RCC_APB1LPENR_I2C1LPEN 0x00200000U
+#define RCC_APB1LPENR_I2C2LPEN 0x00400000U
+#define RCC_APB1LPENR_I2C3LPEN 0x00800000U
+#define RCC_APB1LPENR_PWRLPEN 0x10000000U
+#define RCC_APB1LPENR_DACLPEN 0x20000000U
+
+/******************** Bit definition for RCC_APB2LPENR register *************/
+#define RCC_APB2LPENR_TIM1LPEN 0x00000001U
+#define RCC_APB2LPENR_USART1LPEN 0x00000010U
+#define RCC_APB2LPENR_USART6LPEN 0x00000020U
+#define RCC_APB2LPENR_ADC1LPEN 0x00000100U
+#define RCC_APB2LPENR_SDIOLPEN 0x00000800U
+#define RCC_APB2LPENR_SPI1LPEN 0x00001000U
+#define RCC_APB2LPENR_SPI4LPEN 0x00002000U
+#define RCC_APB2LPENR_SYSCFGLPEN 0x00004000U
+#define RCC_APB2LPENR_TIM9LPEN 0x00010000U
+#define RCC_APB2LPENR_TIM10LPEN 0x00020000U
+#define RCC_APB2LPENR_TIM11LPEN 0x00040000U
+
+/******************** Bit definition for RCC_BDCR register ******************/
+#define RCC_BDCR_LSEON 0x00000001U
+#define RCC_BDCR_LSERDY 0x00000002U
+#define RCC_BDCR_LSEBYP 0x00000004U
+
+#define RCC_BDCR_RTCSEL 0x00000300U
+#define RCC_BDCR_RTCSEL_0 0x00000100U
+#define RCC_BDCR_RTCSEL_1 0x00000200U
+
+#define RCC_BDCR_RTCEN 0x00008000U
+#define RCC_BDCR_BDRST 0x00010000U
+
+/******************** Bit definition for RCC_CSR register *******************/
+#define RCC_CSR_LSION 0x00000001U
+#define RCC_CSR_LSIRDY 0x00000002U
+#define RCC_CSR_RMVF 0x01000000U
+#define RCC_CSR_BORRSTF 0x02000000U
+#define RCC_CSR_PADRSTF 0x04000000U
+#define RCC_CSR_PORRSTF 0x08000000U
+#define RCC_CSR_SFTRSTF 0x10000000U
+#define RCC_CSR_WDGRSTF 0x20000000U
+#define RCC_CSR_WWDGRSTF 0x40000000U
+#define RCC_CSR_LPWRRSTF 0x80000000U
+
+/******************** Bit definition for RCC_SSCGR register *****************/
+#define RCC_SSCGR_MODPER 0x00001FFFU
+#define RCC_SSCGR_INCSTEP 0x0FFFE000U
+#define RCC_SSCGR_SPREADSEL 0x40000000U
+#define RCC_SSCGR_SSCGEN 0x80000000U
+
+/******************** Bit definition for RCC_PLLI2SCFGR register ************/
+#define RCC_PLLI2SCFGR_PLLI2SN 0x00007FC0U
+#define RCC_PLLI2SCFGR_PLLI2SN_0 0x00000040U
+#define RCC_PLLI2SCFGR_PLLI2SN_1 0x00000080U
+#define RCC_PLLI2SCFGR_PLLI2SN_2 0x00000100U
+#define RCC_PLLI2SCFGR_PLLI2SN_3 0x00000200U
+#define RCC_PLLI2SCFGR_PLLI2SN_4 0x00000400U
+#define RCC_PLLI2SCFGR_PLLI2SN_5 0x00000800U
+#define RCC_PLLI2SCFGR_PLLI2SN_6 0x00001000U
+#define RCC_PLLI2SCFGR_PLLI2SN_7 0x00002000U
+#define RCC_PLLI2SCFGR_PLLI2SN_8 0x00004000U
+
+#define RCC_PLLI2SCFGR_PLLI2SR 0x70000000U
+#define RCC_PLLI2SCFGR_PLLI2SR_0 0x10000000U
+#define RCC_PLLI2SCFGR_PLLI2SR_1 0x20000000U
+#define RCC_PLLI2SCFGR_PLLI2SR_2 0x40000000U
+
+/******************** Bit definition for RCC_DCKCFGR register ***************/
+#define RCC_DCKCFGR_TIMPRE 0x01000000U
+
+/******************************************************************************/
+/* */
+/* Real-Time Clock (RTC) */
+/* */
+/******************************************************************************/
+/******************** Bits definition for RTC_TR register *******************/
+#define RTC_TR_PM 0x00400000U
+#define RTC_TR_HT 0x00300000U
+#define RTC_TR_HT_0 0x00100000U
+#define RTC_TR_HT_1 0x00200000U
+#define RTC_TR_HU 0x000F0000U
+#define RTC_TR_HU_0 0x00010000U
+#define RTC_TR_HU_1 0x00020000U
+#define RTC_TR_HU_2 0x00040000U
+#define RTC_TR_HU_3 0x00080000U
+#define RTC_TR_MNT 0x00007000U
+#define RTC_TR_MNT_0 0x00001000U
+#define RTC_TR_MNT_1 0x00002000U
+#define RTC_TR_MNT_2 0x00004000U
+#define RTC_TR_MNU 0x00000F00U
+#define RTC_TR_MNU_0 0x00000100U
+#define RTC_TR_MNU_1 0x00000200U
+#define RTC_TR_MNU_2 0x00000400U
+#define RTC_TR_MNU_3 0x00000800U
+#define RTC_TR_ST 0x00000070U
+#define RTC_TR_ST_0 0x00000010U
+#define RTC_TR_ST_1 0x00000020U
+#define RTC_TR_ST_2 0x00000040U
+#define RTC_TR_SU 0x0000000FU
+#define RTC_TR_SU_0 0x00000001U
+#define RTC_TR_SU_1 0x00000002U
+#define RTC_TR_SU_2 0x00000004U
+#define RTC_TR_SU_3 0x00000008U
+
+/******************** Bits definition for RTC_DR register *******************/
+#define RTC_DR_YT 0x00F00000U
+#define RTC_DR_YT_0 0x00100000U
+#define RTC_DR_YT_1 0x00200000U
+#define RTC_DR_YT_2 0x00400000U
+#define RTC_DR_YT_3 0x00800000U
+#define RTC_DR_YU 0x000F0000U
+#define RTC_DR_YU_0 0x00010000U
+#define RTC_DR_YU_1 0x00020000U
+#define RTC_DR_YU_2 0x00040000U
+#define RTC_DR_YU_3 0x00080000U
+#define RTC_DR_WDU 0x0000E000U
+#define RTC_DR_WDU_0 0x00002000U
+#define RTC_DR_WDU_1 0x00004000U
+#define RTC_DR_WDU_2 0x00008000U
+#define RTC_DR_MT 0x00001000U
+#define RTC_DR_MU 0x00000F00U
+#define RTC_DR_MU_0 0x00000100U
+#define RTC_DR_MU_1 0x00000200U
+#define RTC_DR_MU_2 0x00000400U
+#define RTC_DR_MU_3 0x00000800U
+#define RTC_DR_DT 0x00000030U
+#define RTC_DR_DT_0 0x00000010U
+#define RTC_DR_DT_1 0x00000020U
+#define RTC_DR_DU 0x0000000FU
+#define RTC_DR_DU_0 0x00000001U
+#define RTC_DR_DU_1 0x00000002U
+#define RTC_DR_DU_2 0x00000004U
+#define RTC_DR_DU_3 0x00000008U
+
+/******************** Bits definition for RTC_CR register *******************/
+#define RTC_CR_COE 0x00800000U
+#define RTC_CR_OSEL 0x00600000U
+#define RTC_CR_OSEL_0 0x00200000U
+#define RTC_CR_OSEL_1 0x00400000U
+#define RTC_CR_POL 0x00100000U
+#define RTC_CR_COSEL 0x00080000U
+#define RTC_CR_BCK 0x00040000U
+#define RTC_CR_SUB1H 0x00020000U
+#define RTC_CR_ADD1H 0x00010000U
+#define RTC_CR_TSIE 0x00008000U
+#define RTC_CR_WUTIE 0x00004000U
+#define RTC_CR_ALRBIE 0x00002000U
+#define RTC_CR_ALRAIE 0x00001000U
+#define RTC_CR_TSE 0x00000800U
+#define RTC_CR_WUTE 0x00000400U
+#define RTC_CR_ALRBE 0x00000200U
+#define RTC_CR_ALRAE 0x00000100U
+#define RTC_CR_DCE 0x00000080U
+#define RTC_CR_FMT 0x00000040U
+#define RTC_CR_BYPSHAD 0x00000020U
+#define RTC_CR_REFCKON 0x00000010U
+#define RTC_CR_TSEDGE 0x00000008U
+#define RTC_CR_WUCKSEL 0x00000007U
+#define RTC_CR_WUCKSEL_0 0x00000001U
+#define RTC_CR_WUCKSEL_1 0x00000002U
+#define RTC_CR_WUCKSEL_2 0x00000004U
+
+/******************** Bits definition for RTC_ISR register ******************/
+#define RTC_ISR_RECALPF 0x00010000U
+#define RTC_ISR_TAMP1F 0x00002000U
+#define RTC_ISR_TAMP2F 0x00004000U
+#define RTC_ISR_TSOVF 0x00001000U
+#define RTC_ISR_TSF 0x00000800U
+#define RTC_ISR_WUTF 0x00000400U
+#define RTC_ISR_ALRBF 0x00000200U
+#define RTC_ISR_ALRAF 0x00000100U
+#define RTC_ISR_INIT 0x00000080U
+#define RTC_ISR_INITF 0x00000040U
+#define RTC_ISR_RSF 0x00000020U
+#define RTC_ISR_INITS 0x00000010U
+#define RTC_ISR_SHPF 0x00000008U
+#define RTC_ISR_WUTWF 0x00000004U
+#define RTC_ISR_ALRBWF 0x00000002U
+#define RTC_ISR_ALRAWF 0x00000001U
+
+/******************** Bits definition for RTC_PRER register *****************/
+#define RTC_PRER_PREDIV_A 0x007F0000U
+#define RTC_PRER_PREDIV_S 0x00007FFFU
+
+/******************** Bits definition for RTC_WUTR register *****************/
+#define RTC_WUTR_WUT 0x0000FFFFU
+
+/******************** Bits definition for RTC_CALIBR register ***************/
+#define RTC_CALIBR_DCS 0x00000080U
+#define RTC_CALIBR_DC 0x0000001FU
+
+/******************** Bits definition for RTC_ALRMAR register ***************/
+#define RTC_ALRMAR_MSK4 0x80000000U
+#define RTC_ALRMAR_WDSEL 0x40000000U
+#define RTC_ALRMAR_DT 0x30000000U
+#define RTC_ALRMAR_DT_0 0x10000000U
+#define RTC_ALRMAR_DT_1 0x20000000U
+#define RTC_ALRMAR_DU 0x0F000000U
+#define RTC_ALRMAR_DU_0 0x01000000U
+#define RTC_ALRMAR_DU_1 0x02000000U
+#define RTC_ALRMAR_DU_2 0x04000000U
+#define RTC_ALRMAR_DU_3 0x08000000U
+#define RTC_ALRMAR_MSK3 0x00800000U
+#define RTC_ALRMAR_PM 0x00400000U
+#define RTC_ALRMAR_HT 0x00300000U
+#define RTC_ALRMAR_HT_0 0x00100000U
+#define RTC_ALRMAR_HT_1 0x00200000U
+#define RTC_ALRMAR_HU 0x000F0000U
+#define RTC_ALRMAR_HU_0 0x00010000U
+#define RTC_ALRMAR_HU_1 0x00020000U
+#define RTC_ALRMAR_HU_2 0x00040000U
+#define RTC_ALRMAR_HU_3 0x00080000U
+#define RTC_ALRMAR_MSK2 0x00008000U
+#define RTC_ALRMAR_MNT 0x00007000U
+#define RTC_ALRMAR_MNT_0 0x00001000U
+#define RTC_ALRMAR_MNT_1 0x00002000U
+#define RTC_ALRMAR_MNT_2 0x00004000U
+#define RTC_ALRMAR_MNU 0x00000F00U
+#define RTC_ALRMAR_MNU_0 0x00000100U
+#define RTC_ALRMAR_MNU_1 0x00000200U
+#define RTC_ALRMAR_MNU_2 0x00000400U
+#define RTC_ALRMAR_MNU_3 0x00000800U
+#define RTC_ALRMAR_MSK1 0x00000080U
+#define RTC_ALRMAR_ST 0x00000070U
+#define RTC_ALRMAR_ST_0 0x00000010U
+#define RTC_ALRMAR_ST_1 0x00000020U
+#define RTC_ALRMAR_ST_2 0x00000040U
+#define RTC_ALRMAR_SU 0x0000000FU
+#define RTC_ALRMAR_SU_0 0x00000001U
+#define RTC_ALRMAR_SU_1 0x00000002U
+#define RTC_ALRMAR_SU_2 0x00000004U
+#define RTC_ALRMAR_SU_3 0x00000008U
+
+/******************** Bits definition for RTC_ALRMBR register ***************/
+#define RTC_ALRMBR_MSK4 0x80000000U
+#define RTC_ALRMBR_WDSEL 0x40000000U
+#define RTC_ALRMBR_DT 0x30000000U
+#define RTC_ALRMBR_DT_0 0x10000000U
+#define RTC_ALRMBR_DT_1 0x20000000U
+#define RTC_ALRMBR_DU 0x0F000000U
+#define RTC_ALRMBR_DU_0 0x01000000U
+#define RTC_ALRMBR_DU_1 0x02000000U
+#define RTC_ALRMBR_DU_2 0x04000000U
+#define RTC_ALRMBR_DU_3 0x08000000U
+#define RTC_ALRMBR_MSK3 0x00800000U
+#define RTC_ALRMBR_PM 0x00400000U
+#define RTC_ALRMBR_HT 0x00300000U
+#define RTC_ALRMBR_HT_0 0x00100000U
+#define RTC_ALRMBR_HT_1 0x00200000U
+#define RTC_ALRMBR_HU 0x000F0000U
+#define RTC_ALRMBR_HU_0 0x00010000U
+#define RTC_ALRMBR_HU_1 0x00020000U
+#define RTC_ALRMBR_HU_2 0x00040000U
+#define RTC_ALRMBR_HU_3 0x00080000U
+#define RTC_ALRMBR_MSK2 0x00008000U
+#define RTC_ALRMBR_MNT 0x00007000U
+#define RTC_ALRMBR_MNT_0 0x00001000U
+#define RTC_ALRMBR_MNT_1 0x00002000U
+#define RTC_ALRMBR_MNT_2 0x00004000U
+#define RTC_ALRMBR_MNU 0x00000F00U
+#define RTC_ALRMBR_MNU_0 0x00000100U
+#define RTC_ALRMBR_MNU_1 0x00000200U
+#define RTC_ALRMBR_MNU_2 0x00000400U
+#define RTC_ALRMBR_MNU_3 0x00000800U
+#define RTC_ALRMBR_MSK1 0x00000080U
+#define RTC_ALRMBR_ST 0x00000070U
+#define RTC_ALRMBR_ST_0 0x00000010U
+#define RTC_ALRMBR_ST_1 0x00000020U
+#define RTC_ALRMBR_ST_2 0x00000040U
+#define RTC_ALRMBR_SU 0x0000000FU
+#define RTC_ALRMBR_SU_0 0x00000001U
+#define RTC_ALRMBR_SU_1 0x00000002U
+#define RTC_ALRMBR_SU_2 0x00000004U
+#define RTC_ALRMBR_SU_3 0x00000008U
+
+/******************** Bits definition for RTC_WPR register ******************/
+#define RTC_WPR_KEY 0x000000FFU
+
+/******************** Bits definition for RTC_SSR register ******************/
+#define RTC_SSR_SS 0x0000FFFFU
+
+/******************** Bits definition for RTC_SHIFTR register ***************/
+#define RTC_SHIFTR_SUBFS 0x00007FFFU
+#define RTC_SHIFTR_ADD1S 0x80000000U
+
+/******************** Bits definition for RTC_TSTR register *****************/
+#define RTC_TSTR_PM 0x00400000U
+#define RTC_TSTR_HT 0x00300000U
+#define RTC_TSTR_HT_0 0x00100000U
+#define RTC_TSTR_HT_1 0x00200000U
+#define RTC_TSTR_HU 0x000F0000U
+#define RTC_TSTR_HU_0 0x00010000U
+#define RTC_TSTR_HU_1 0x00020000U
+#define RTC_TSTR_HU_2 0x00040000U
+#define RTC_TSTR_HU_3 0x00080000U
+#define RTC_TSTR_MNT 0x00007000U
+#define RTC_TSTR_MNT_0 0x00001000U
+#define RTC_TSTR_MNT_1 0x00002000U
+#define RTC_TSTR_MNT_2 0x00004000U
+#define RTC_TSTR_MNU 0x00000F00U
+#define RTC_TSTR_MNU_0 0x00000100U
+#define RTC_TSTR_MNU_1 0x00000200U
+#define RTC_TSTR_MNU_2 0x00000400U
+#define RTC_TSTR_MNU_3 0x00000800U
+#define RTC_TSTR_ST 0x00000070U
+#define RTC_TSTR_ST_0 0x00000010U
+#define RTC_TSTR_ST_1 0x00000020U
+#define RTC_TSTR_ST_2 0x00000040U
+#define RTC_TSTR_SU 0x0000000FU
+#define RTC_TSTR_SU_0 0x00000001U
+#define RTC_TSTR_SU_1 0x00000002U
+#define RTC_TSTR_SU_2 0x00000004U
+#define RTC_TSTR_SU_3 0x00000008U
+
+/******************** Bits definition for RTC_TSDR register *****************/
+#define RTC_TSDR_WDU 0x0000E000U
+#define RTC_TSDR_WDU_0 0x00002000U
+#define RTC_TSDR_WDU_1 0x00004000U
+#define RTC_TSDR_WDU_2 0x00008000U
+#define RTC_TSDR_MT 0x00001000U
+#define RTC_TSDR_MU 0x00000F00U
+#define RTC_TSDR_MU_0 0x00000100U
+#define RTC_TSDR_MU_1 0x00000200U
+#define RTC_TSDR_MU_2 0x00000400U
+#define RTC_TSDR_MU_3 0x00000800U
+#define RTC_TSDR_DT 0x00000030U
+#define RTC_TSDR_DT_0 0x00000010U
+#define RTC_TSDR_DT_1 0x00000020U
+#define RTC_TSDR_DU 0x0000000FU
+#define RTC_TSDR_DU_0 0x00000001U
+#define RTC_TSDR_DU_1 0x00000002U
+#define RTC_TSDR_DU_2 0x00000004U
+#define RTC_TSDR_DU_3 0x00000008U
+
+/******************** Bits definition for RTC_TSSSR register ****************/
+#define RTC_TSSSR_SS 0x0000FFFFU
+
+/******************** Bits definition for RTC_CAL register *****************/
+#define RTC_CALR_CALP 0x00008000U
+#define RTC_CALR_CALW8 0x00004000U
+#define RTC_CALR_CALW16 0x00002000U
+#define RTC_CALR_CALM 0x000001FFU
+#define RTC_CALR_CALM_0 0x00000001U
+#define RTC_CALR_CALM_1 0x00000002U
+#define RTC_CALR_CALM_2 0x00000004U
+#define RTC_CALR_CALM_3 0x00000008U
+#define RTC_CALR_CALM_4 0x00000010U
+#define RTC_CALR_CALM_5 0x00000020U
+#define RTC_CALR_CALM_6 0x00000040U
+#define RTC_CALR_CALM_7 0x00000080U
+#define RTC_CALR_CALM_8 0x00000100U
+
+/******************** Bits definition for RTC_TAFCR register ****************/
+#define RTC_TAFCR_ALARMOUTTYPE 0x00040000U
+#define RTC_TAFCR_TSINSEL 0x00020000U
+#define RTC_TAFCR_TAMPINSEL 0x00010000U
+#define RTC_TAFCR_TAMPPUDIS 0x00008000U
+#define RTC_TAFCR_TAMPPRCH 0x00006000U
+#define RTC_TAFCR_TAMPPRCH_0 0x00002000U
+#define RTC_TAFCR_TAMPPRCH_1 0x00004000U
+#define RTC_TAFCR_TAMPFLT 0x00001800U
+#define RTC_TAFCR_TAMPFLT_0 0x00000800U
+#define RTC_TAFCR_TAMPFLT_1 0x00001000U
+#define RTC_TAFCR_TAMPFREQ 0x00000700U
+#define RTC_TAFCR_TAMPFREQ_0 0x00000100U
+#define RTC_TAFCR_TAMPFREQ_1 0x00000200U
+#define RTC_TAFCR_TAMPFREQ_2 0x00000400U
+#define RTC_TAFCR_TAMPTS 0x00000080U
+#define RTC_TAFCR_TAMP2TRG 0x00000010U
+#define RTC_TAFCR_TAMP2E 0x00000008U
+#define RTC_TAFCR_TAMPIE 0x00000004U
+#define RTC_TAFCR_TAMP1TRG 0x00000002U
+#define RTC_TAFCR_TAMP1E 0x00000001U
+
+/******************** Bits definition for RTC_ALRMASSR register *************/
+#define RTC_ALRMASSR_MASKSS 0x0F000000U
+#define RTC_ALRMASSR_MASKSS_0 0x01000000U
+#define RTC_ALRMASSR_MASKSS_1 0x02000000U
+#define RTC_ALRMASSR_MASKSS_2 0x04000000U
+#define RTC_ALRMASSR_MASKSS_3 0x08000000U
+#define RTC_ALRMASSR_SS 0x00007FFFU
+
+/******************** Bits definition for RTC_ALRMBSSR register *************/
+#define RTC_ALRMBSSR_MASKSS 0x0F000000U
+#define RTC_ALRMBSSR_MASKSS_0 0x01000000U
+#define RTC_ALRMBSSR_MASKSS_1 0x02000000U
+#define RTC_ALRMBSSR_MASKSS_2 0x04000000U
+#define RTC_ALRMBSSR_MASKSS_3 0x08000000U
+#define RTC_ALRMBSSR_SS 0x00007FFFU
+
+/******************** Bits definition for RTC_BKP0R register ****************/
+#define RTC_BKP0R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP1R register ****************/
+#define RTC_BKP1R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP2R register ****************/
+#define RTC_BKP2R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP3R register ****************/
+#define RTC_BKP3R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP4R register ****************/
+#define RTC_BKP4R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP5R register ****************/
+#define RTC_BKP5R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP6R register ****************/
+#define RTC_BKP6R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP7R register ****************/
+#define RTC_BKP7R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP8R register ****************/
+#define RTC_BKP8R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP9R register ****************/
+#define RTC_BKP9R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP10R register ***************/
+#define RTC_BKP10R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP11R register ***************/
+#define RTC_BKP11R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP12R register ***************/
+#define RTC_BKP12R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP13R register ***************/
+#define RTC_BKP13R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP14R register ***************/
+#define RTC_BKP14R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP15R register ***************/
+#define RTC_BKP15R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP16R register ***************/
+#define RTC_BKP16R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP17R register ***************/
+#define RTC_BKP17R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP18R register ***************/
+#define RTC_BKP18R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP19R register ***************/
+#define RTC_BKP19R 0xFFFFFFFFU
+
+
+
+/******************************************************************************/
+/* */
+/* SD host Interface */
+/* */
+/******************************************************************************/
+/****************** Bit definition for SDIO_POWER register ******************/
+#define SDIO_POWER_PWRCTRL 0x03U /*!<PWRCTRL[1:0] bits (Power supply control bits) */
+#define SDIO_POWER_PWRCTRL_0 0x01U /*!<Bit 0 */
+#define SDIO_POWER_PWRCTRL_1 0x02U /*!<Bit 1 */
+
+/****************** Bit definition for SDIO_CLKCR register ******************/
+#define SDIO_CLKCR_CLKDIV 0x00FFU /*!<Clock divide factor */
+#define SDIO_CLKCR_CLKEN 0x0100U /*!<Clock enable bit */
+#define SDIO_CLKCR_PWRSAV 0x0200U /*!<Power saving configuration bit */
+#define SDIO_CLKCR_BYPASS 0x0400U /*!<Clock divider bypass enable bit */
+
+#define SDIO_CLKCR_WIDBUS 0x1800U /*!<WIDBUS[1:0] bits (Wide bus mode enable bit) */
+#define SDIO_CLKCR_WIDBUS_0 0x0800U /*!<Bit 0 */
+#define SDIO_CLKCR_WIDBUS_1 0x1000U /*!<Bit 1 */
+
+#define SDIO_CLKCR_NEGEDGE 0x2000U /*!<SDIO_CK dephasing selection bit */
+#define SDIO_CLKCR_HWFC_EN 0x4000U /*!<HW Flow Control enable */
+
+/******************* Bit definition for SDIO_ARG register *******************/
+#define SDIO_ARG_CMDARG 0xFFFFFFFFU /*!<Command argument */
+
+/******************* Bit definition for SDIO_CMD register *******************/
+#define SDIO_CMD_CMDINDEX 0x003FU /*!<Command Index */
+
+#define SDIO_CMD_WAITRESP 0x00C0U /*!<WAITRESP[1:0] bits (Wait for response bits) */
+#define SDIO_CMD_WAITRESP_0 0x0040U /*!< Bit 0 */
+#define SDIO_CMD_WAITRESP_1 0x0080U /*!< Bit 1 */
+
+#define SDIO_CMD_WAITINT 0x0100U /*!<CPSM Waits for Interrupt Request */
+#define SDIO_CMD_WAITPEND 0x0200U /*!<CPSM Waits for ends of data transfer (CmdPend internal signal) */
+#define SDIO_CMD_CPSMEN 0x0400U /*!<Command path state machine (CPSM) Enable bit */
+#define SDIO_CMD_SDIOSUSPEND 0x0800U /*!<SD I/O suspend command */
+#define SDIO_CMD_ENCMDCOMPL 0x1000U /*!<Enable CMD completion */
+#define SDIO_CMD_NIEN 0x2000U /*!<Not Interrupt Enable */
+#define SDIO_CMD_CEATACMD 0x4000U /*!<CE-ATA command */
+
+/***************** Bit definition for SDIO_RESPCMD register *****************/
+#define SDIO_RESPCMD_RESPCMD 0x3FU /*!<Response command index */
+
+/****************** Bit definition for SDIO_RESP0 register ******************/
+#define SDIO_RESP0_CARDSTATUS0 0xFFFFFFFFU /*!<Card Status */
+
+/****************** Bit definition for SDIO_RESP1 register ******************/
+#define SDIO_RESP1_CARDSTATUS1 0xFFFFFFFFU /*!<Card Status */
+
+/****************** Bit definition for SDIO_RESP2 register ******************/
+#define SDIO_RESP2_CARDSTATUS2 0xFFFFFFFFU /*!<Card Status */
+
+/****************** Bit definition for SDIO_RESP3 register ******************/
+#define SDIO_RESP3_CARDSTATUS3 0xFFFFFFFFU /*!<Card Status */
+
+/****************** Bit definition for SDIO_RESP4 register ******************/
+#define SDIO_RESP4_CARDSTATUS4 0xFFFFFFFFU /*!<Card Status */
+
+/****************** Bit definition for SDIO_DTIMER register *****************/
+#define SDIO_DTIMER_DATATIME 0xFFFFFFFFU /*!<Data timeout period. */
+
+/****************** Bit definition for SDIO_DLEN register *******************/
+#define SDIO_DLEN_DATALENGTH 0x01FFFFFFU /*!<Data length value */
+
+/****************** Bit definition for SDIO_DCTRL register ******************/
+#define SDIO_DCTRL_DTEN 0x0001U /*!<Data transfer enabled bit */
+#define SDIO_DCTRL_DTDIR 0x0002U /*!<Data transfer direction selection */
+#define SDIO_DCTRL_DTMODE 0x0004U /*!<Data transfer mode selection */
+#define SDIO_DCTRL_DMAEN 0x0008U /*!<DMA enabled bit */
+
+#define SDIO_DCTRL_DBLOCKSIZE 0x00F0U /*!<DBLOCKSIZE[3:0] bits (Data block size) */
+#define SDIO_DCTRL_DBLOCKSIZE_0 0x0010U /*!<Bit 0 */
+#define SDIO_DCTRL_DBLOCKSIZE_1 0x0020U /*!<Bit 1 */
+#define SDIO_DCTRL_DBLOCKSIZE_2 0x0040U /*!<Bit 2 */
+#define SDIO_DCTRL_DBLOCKSIZE_3 0x0080U /*!<Bit 3 */
+
+#define SDIO_DCTRL_RWSTART 0x0100U /*!<Read wait start */
+#define SDIO_DCTRL_RWSTOP 0x0200U /*!<Read wait stop */
+#define SDIO_DCTRL_RWMOD 0x0400U /*!<Read wait mode */
+#define SDIO_DCTRL_SDIOEN 0x0800U /*!<SD I/O enable functions */
+
+/****************** Bit definition for SDIO_DCOUNT register *****************/
+#define SDIO_DCOUNT_DATACOUNT 0x01FFFFFFU /*!<Data count value */
+
+/****************** Bit definition for SDIO_STA register ********************/
+#define SDIO_STA_CCRCFAIL 0x00000001U /*!<Command response received (CRC check failed) */
+#define SDIO_STA_DCRCFAIL 0x00000002U /*!<Data block sent/received (CRC check failed) */
+#define SDIO_STA_CTIMEOUT 0x00000004U /*!<Command response timeout */
+#define SDIO_STA_DTIMEOUT 0x00000008U /*!<Data timeout */
+#define SDIO_STA_TXUNDERR 0x00000010U /*!<Transmit FIFO underrun error */
+#define SDIO_STA_RXOVERR 0x00000020U /*!<Received FIFO overrun error */
+#define SDIO_STA_CMDREND 0x00000040U /*!<Command response received (CRC check passed) */
+#define SDIO_STA_CMDSENT 0x00000080U /*!<Command sent (no response required) */
+#define SDIO_STA_DATAEND 0x00000100U /*!<Data end (data counter, SDIDCOUNT, is zero) */
+#define SDIO_STA_STBITERR 0x00000200U /*!<Start bit not detected on all data signals in wide bus mode */
+#define SDIO_STA_DBCKEND 0x00000400U /*!<Data block sent/received (CRC check passed) */
+#define SDIO_STA_CMDACT 0x00000800U /*!<Command transfer in progress */
+#define SDIO_STA_TXACT 0x00001000U /*!<Data transmit in progress */
+#define SDIO_STA_RXACT 0x00002000U /*!<Data receive in progress */
+#define SDIO_STA_TXFIFOHE 0x00004000U /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
+#define SDIO_STA_RXFIFOHF 0x00008000U /*!<Receive FIFO Half Full: there are at least 8 words in the FIFO */
+#define SDIO_STA_TXFIFOF 0x00010000U /*!<Transmit FIFO full */
+#define SDIO_STA_RXFIFOF 0x00020000U /*!<Receive FIFO full */
+#define SDIO_STA_TXFIFOE 0x00040000U /*!<Transmit FIFO empty */
+#define SDIO_STA_RXFIFOE 0x00080000U /*!<Receive FIFO empty */
+#define SDIO_STA_TXDAVL 0x00100000U /*!<Data available in transmit FIFO */
+#define SDIO_STA_RXDAVL 0x00200000U /*!<Data available in receive FIFO */
+#define SDIO_STA_SDIOIT 0x00400000U /*!<SDIO interrupt received */
+#define SDIO_STA_CEATAEND 0x00800000U /*!<CE-ATA command completion signal received for CMD61 */
+
+/******************* Bit definition for SDIO_ICR register *******************/
+#define SDIO_ICR_CCRCFAILC 0x00000001U /*!<CCRCFAIL flag clear bit */
+#define SDIO_ICR_DCRCFAILC 0x00000002U /*!<DCRCFAIL flag clear bit */
+#define SDIO_ICR_CTIMEOUTC 0x00000004U /*!<CTIMEOUT flag clear bit */
+#define SDIO_ICR_DTIMEOUTC 0x00000008U /*!<DTIMEOUT flag clear bit */
+#define SDIO_ICR_TXUNDERRC 0x00000010U /*!<TXUNDERR flag clear bit */
+#define SDIO_ICR_RXOVERRC 0x00000020U /*!<RXOVERR flag clear bit */
+#define SDIO_ICR_CMDRENDC 0x00000040U /*!<CMDREND flag clear bit */
+#define SDIO_ICR_CMDSENTC 0x00000080U /*!<CMDSENT flag clear bit */
+#define SDIO_ICR_DATAENDC 0x00000100U /*!<DATAEND flag clear bit */
+#define SDIO_ICR_STBITERRC 0x00000200U /*!<STBITERR flag clear bit */
+#define SDIO_ICR_DBCKENDC 0x00000400U /*!<DBCKEND flag clear bit */
+#define SDIO_ICR_SDIOITC 0x00400000U /*!<SDIOIT flag clear bit */
+#define SDIO_ICR_CEATAENDC 0x00800000U /*!<CEATAEND flag clear bit */
+
+/****************** Bit definition for SDIO_MASK register *******************/
+#define SDIO_MASK_CCRCFAILIE 0x00000001U /*!<Command CRC Fail Interrupt Enable */
+#define SDIO_MASK_DCRCFAILIE 0x00000002U /*!<Data CRC Fail Interrupt Enable */
+#define SDIO_MASK_CTIMEOUTIE 0x00000004U /*!<Command TimeOut Interrupt Enable */
+#define SDIO_MASK_DTIMEOUTIE 0x00000008U /*!<Data TimeOut Interrupt Enable */
+#define SDIO_MASK_TXUNDERRIE 0x00000010U /*!<Tx FIFO UnderRun Error Interrupt Enable */
+#define SDIO_MASK_RXOVERRIE 0x00000020U /*!<Rx FIFO OverRun Error Interrupt Enable */
+#define SDIO_MASK_CMDRENDIE 0x00000040U /*!<Command Response Received Interrupt Enable */
+#define SDIO_MASK_CMDSENTIE 0x00000080U /*!<Command Sent Interrupt Enable */
+#define SDIO_MASK_DATAENDIE 0x00000100U /*!<Data End Interrupt Enable */
+#define SDIO_MASK_STBITERRIE 0x00000200U /*!<Start Bit Error Interrupt Enable */
+#define SDIO_MASK_DBCKENDIE 0x00000400U /*!<Data Block End Interrupt Enable */
+#define SDIO_MASK_CMDACTIE 0x00000800U /*!<CCommand Acting Interrupt Enable */
+#define SDIO_MASK_TXACTIE 0x00001000U /*!<Data Transmit Acting Interrupt Enable */
+#define SDIO_MASK_RXACTIE 0x00002000U /*!<Data receive acting interrupt enabled */
+#define SDIO_MASK_TXFIFOHEIE 0x00004000U /*!<Tx FIFO Half Empty interrupt Enable */
+#define SDIO_MASK_RXFIFOHFIE 0x00008000U /*!<Rx FIFO Half Full interrupt Enable */
+#define SDIO_MASK_TXFIFOFIE 0x00010000U /*!<Tx FIFO Full interrupt Enable */
+#define SDIO_MASK_RXFIFOFIE 0x00020000U /*!<Rx FIFO Full interrupt Enable */
+#define SDIO_MASK_TXFIFOEIE 0x00040000U /*!<Tx FIFO Empty interrupt Enable */
+#define SDIO_MASK_RXFIFOEIE 0x00080000U /*!<Rx FIFO Empty interrupt Enable */
+#define SDIO_MASK_TXDAVLIE 0x00100000U /*!<Data available in Tx FIFO interrupt Enable */
+#define SDIO_MASK_RXDAVLIE 0x00200000U /*!<Data available in Rx FIFO interrupt Enable */
+#define SDIO_MASK_SDIOITIE 0x00400000U /*!<SDIO Mode Interrupt Received interrupt Enable */
+#define SDIO_MASK_CEATAENDIE 0x00800000U /*!<CE-ATA command completion signal received Interrupt Enable */
+
+/***************** Bit definition for SDIO_FIFOCNT register *****************/
+#define SDIO_FIFOCNT_FIFOCOUNT 0x00FFFFFFU /*!<Remaining number of words to be written to or read from the FIFO */
+
+/****************** Bit definition for SDIO_FIFO register *******************/
+#define SDIO_FIFO_FIFODATA 0xFFFFFFFFU /*!<Receive and transmit FIFO data */
+
+/******************************************************************************/
+/* */
+/* Serial Peripheral Interface */
+/* */
+/******************************************************************************/
+/******************* Bit definition for SPI_CR1 register ********************/
+#define SPI_CR1_CPHA 0x00000001U /*!<Clock Phase */
+#define SPI_CR1_CPOL 0x00000002U /*!<Clock Polarity */
+#define SPI_CR1_MSTR 0x00000004U /*!<Master Selection */
+
+#define SPI_CR1_BR 0x00000038U /*!<BR[2:0] bits (Baud Rate Control) */
+#define SPI_CR1_BR_0 0x00000008U /*!<Bit 0 */
+#define SPI_CR1_BR_1 0x00000010U /*!<Bit 1 */
+#define SPI_CR1_BR_2 0x00000020U /*!<Bit 2 */
+
+#define SPI_CR1_SPE 0x00000040U /*!<SPI Enable */
+#define SPI_CR1_LSBFIRST 0x00000080U /*!<Frame Format */
+#define SPI_CR1_SSI 0x00000100U /*!<Internal slave select */
+#define SPI_CR1_SSM 0x00000200U /*!<Software slave management */
+#define SPI_CR1_RXONLY 0x00000400U /*!<Receive only */
+#define SPI_CR1_DFF 0x00000800U /*!<Data Frame Format */
+#define SPI_CR1_CRCNEXT 0x00001000U /*!<Transmit CRC next */
+#define SPI_CR1_CRCEN 0x00002000U /*!<Hardware CRC calculation enable */
+#define SPI_CR1_BIDIOE 0x00004000U /*!<Output enable in bidirectional mode */
+#define SPI_CR1_BIDIMODE 0x00008000U /*!<Bidirectional data mode enable */
+
+/******************* Bit definition for SPI_CR2 register ********************/
+#define SPI_CR2_RXDMAEN 0x00000001U /*!<Rx Buffer DMA Enable */
+#define SPI_CR2_TXDMAEN 0x00000002U /*!<Tx Buffer DMA Enable */
+#define SPI_CR2_SSOE 0x00000004U /*!<SS Output Enable */
+#define SPI_CR2_FRF 0x00000010U /*!<Frame Format */
+#define SPI_CR2_ERRIE 0x00000020U /*!<Error Interrupt Enable */
+#define SPI_CR2_RXNEIE 0x00000040U /*!<RX buffer Not Empty Interrupt Enable */
+#define SPI_CR2_TXEIE 0x00000080U /*!<Tx buffer Empty Interrupt Enable */
+
+/******************** Bit definition for SPI_SR register ********************/
+#define SPI_SR_RXNE 0x00000001U /*!<Receive buffer Not Empty */
+#define SPI_SR_TXE 0x00000002U /*!<Transmit buffer Empty */
+#define SPI_SR_CHSIDE 0x00000004U /*!<Channel side */
+#define SPI_SR_UDR 0x00000008U /*!<Underrun flag */
+#define SPI_SR_CRCERR 0x00000010U /*!<CRC Error flag */
+#define SPI_SR_MODF 0x00000020U /*!<Mode fault */
+#define SPI_SR_OVR 0x00000040U /*!<Overrun flag */
+#define SPI_SR_BSY 0x00000080U /*!<Busy flag */
+#define SPI_SR_FRE 0x00000100U /*!<Frame format error flag */
+
+/******************** Bit definition for SPI_DR register ********************/
+#define SPI_DR_DR 0x0000FFFFU /*!<Data Register */
+
+/******************* Bit definition for SPI_CRCPR register ******************/
+#define SPI_CRCPR_CRCPOLY 0x0000FFFFU /*!<CRC polynomial register */
+
+/****************** Bit definition for SPI_RXCRCR register ******************/
+#define SPI_RXCRCR_RXCRC 0x0000FFFFU /*!<Rx CRC Register */
+
+/****************** Bit definition for SPI_TXCRCR register ******************/
+#define SPI_TXCRCR_TXCRC 0x0000FFFFU /*!<Tx CRC Register */
+
+/****************** Bit definition for SPI_I2SCFGR register *****************/
+#define SPI_I2SCFGR_CHLEN 0x00000001U /*!<Channel length (number of bits per audio channel) */
+
+#define SPI_I2SCFGR_DATLEN 0x00000006U /*!<DATLEN[1:0] bits (Data length to be transferred) */
+#define SPI_I2SCFGR_DATLEN_0 0x00000002U /*!<Bit 0 */
+#define SPI_I2SCFGR_DATLEN_1 0x00000004U /*!<Bit 1 */
+
+#define SPI_I2SCFGR_CKPOL 0x00000008U /*!<steady state clock polarity */
+
+#define SPI_I2SCFGR_I2SSTD 0x00000030U /*!<I2SSTD[1:0] bits (I2S standard selection) */
+#define SPI_I2SCFGR_I2SSTD_0 0x00000010U /*!<Bit 0 */
+#define SPI_I2SCFGR_I2SSTD_1 0x00000020U /*!<Bit 1 */
+
+#define SPI_I2SCFGR_PCMSYNC 0x00000080U /*!<PCM frame synchronization */
+
+#define SPI_I2SCFGR_I2SCFG 0x00000300U /*!<I2SCFG[1:0] bits (I2S configuration mode) */
+#define SPI_I2SCFGR_I2SCFG_0 0x00000100U /*!<Bit 0 */
+#define SPI_I2SCFGR_I2SCFG_1 0x00000200U /*!<Bit 1 */
+
+#define SPI_I2SCFGR_I2SE 0x00000400U /*!<I2S Enable */
+#define SPI_I2SCFGR_I2SMOD 0x00000800U /*!<I2S mode selection */
+
+/****************** Bit definition for SPI_I2SPR register *******************/
+#define SPI_I2SPR_I2SDIV 0x000000FFU /*!<I2S Linear prescaler */
+#define SPI_I2SPR_ODD 0x00000100U /*!<Odd factor for the prescaler */
+#define SPI_I2SPR_MCKOE 0x00000200U /*!<Master Clock Output Enable */
+
+/******************************************************************************/
+/* */
+/* SYSCFG */
+/* */
+/******************************************************************************/
+/****************** Bit definition for SYSCFG_MEMRMP register ***************/
+#define SYSCFG_MEMRMP_MEM_MODE 0x00000007U /*!< SYSCFG_Memory Remap Config */
+#define SYSCFG_MEMRMP_MEM_MODE_0 0x00000001U
+#define SYSCFG_MEMRMP_MEM_MODE_1 0x00000002U
+#define SYSCFG_MEMRMP_MEM_MODE_2 0x00000004U
+
+/****************** Bit definition for SYSCFG_PMC register ******************/
+#define SYSCFG_PMC_ADC1DC2 0x00010000U /*!< Refer to AN4073 on how to use this bit */
+
+/***************** Bit definition for SYSCFG_EXTICR1 register ***************/
+#define SYSCFG_EXTICR1_EXTI0 0x000FU /*!<EXTI 0 configuration */
+#define SYSCFG_EXTICR1_EXTI1 0x00F0U /*!<EXTI 1 configuration */
+#define SYSCFG_EXTICR1_EXTI2 0x0F00U /*!<EXTI 2 configuration */
+#define SYSCFG_EXTICR1_EXTI3 0xF000U /*!<EXTI 3 configuration */
+/**
+ * @brief EXTI0 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI0_PA 0x0000U /*!<PA[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PB 0x0001U /*!<PB[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PC 0x0002U /*!<PC[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PD 0x0003U /*!<PD[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PE 0x0004U /*!<PE[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PH 0x0007U /*!<PH[0] pin */
+
+/**
+ * @brief EXTI1 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI1_PA 0x0000U /*!<PA[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PB 0x0010U /*!<PB[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PC 0x0020U /*!<PC[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PD 0x0030U /*!<PD[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PE 0x0040U /*!<PE[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PH 0x0070U /*!<PH[1] pin */
+
+/**
+ * @brief EXTI2 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI2_PA 0x0000U /*!<PA[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PB 0x0100U /*!<PB[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PC 0x0200U /*!<PC[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PD 0x0300U /*!<PD[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PE 0x0400U /*!<PE[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PH 0x0700U /*!<PH[2] pin */
+
+/**
+ * @brief EXTI3 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI3_PA 0x0000U /*!<PA[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PB 0x1000U /*!<PB[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PC 0x2000U /*!<PC[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PD 0x3000U /*!<PD[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PE 0x4000U /*!<PE[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PH 0x7000U /*!<PH[3] pin */
+
+/***************** Bit definition for SYSCFG_EXTICR2 register ***************/
+#define SYSCFG_EXTICR2_EXTI4 0x000FU /*!<EXTI 4 configuration */
+#define SYSCFG_EXTICR2_EXTI5 0x00F0U /*!<EXTI 5 configuration */
+#define SYSCFG_EXTICR2_EXTI6 0x0F00U /*!<EXTI 6 configuration */
+#define SYSCFG_EXTICR2_EXTI7 0xF000U /*!<EXTI 7 configuration */
+/**
+ * @brief EXTI4 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI4_PA 0x0000U /*!<PA[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PB 0x0001U /*!<PB[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PC 0x0002U /*!<PC[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PD 0x0003U /*!<PD[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PE 0x0004U /*!<PE[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PH 0x0007U /*!<PH[4] pin */
+
+/**
+ * @brief EXTI5 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI5_PA 0x0000U /*!<PA[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PB 0x0010U /*!<PB[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PC 0x0020U /*!<PC[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PD 0x0030U /*!<PD[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PE 0x0040U /*!<PE[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PH 0x0070U /*!<PH[5] pin */
+
+/**
+ * @brief EXTI6 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI6_PA 0x0000U /*!<PA[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PB 0x0100U /*!<PB[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PC 0x0200U /*!<PC[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PD 0x0300U /*!<PD[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PE 0x0400U /*!<PE[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PH 0x0700U /*!<PH[6] pin */
+
+/**
+ * @brief EXTI7 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI7_PA 0x0000U /*!<PA[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PB 0x1000U /*!<PB[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PC 0x2000U /*!<PC[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PD 0x3000U /*!<PD[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PE 0x4000U /*!<PE[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PH 0x7000U /*!<PH[7] pin */
+
+
+/***************** Bit definition for SYSCFG_EXTICR3 register ***************/
+#define SYSCFG_EXTICR3_EXTI8 0x000FU /*!<EXTI 8 configuration */
+#define SYSCFG_EXTICR3_EXTI9 0x00F0U /*!<EXTI 9 configuration */
+#define SYSCFG_EXTICR3_EXTI10 0x0F00U /*!<EXTI 10 configuration */
+#define SYSCFG_EXTICR3_EXTI11 0xF000U /*!<EXTI 11 configuration */
+
+/**
+ * @brief EXTI8 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI8_PA 0x0000U /*!<PA[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PB 0x0001U /*!<PB[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PC 0x0002U /*!<PC[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PD 0x0003U /*!<PD[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PE 0x0004U /*!<PE[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PH 0x0007U /*!<PH[8] pin */
+
+/**
+ * @brief EXTI9 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI9_PA 0x0000U /*!<PA[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PB 0x0010U /*!<PB[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PC 0x0020U /*!<PC[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PD 0x0030U /*!<PD[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PE 0x0040U /*!<PE[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PH 0x0070U /*!<PH[9] pin */
+
+/**
+ * @brief EXTI10 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI10_PA 0x0000U /*!<PA[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PB 0x0100U /*!<PB[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PC 0x0200U /*!<PC[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PD 0x0300U /*!<PD[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PE 0x0400U /*!<PE[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PH 0x0700U /*!<PH[10] pin */
+
+/**
+ * @brief EXTI11 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI11_PA 0x0000U /*!<PA[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PB 0x1000U /*!<PB[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PC 0x2000U /*!<PC[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PD 0x3000U /*!<PD[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PE 0x4000U /*!<PE[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PH 0x7000U /*!<PH[11] pin */
+
+/***************** Bit definition for SYSCFG_EXTICR4 register ***************/
+#define SYSCFG_EXTICR4_EXTI12 0x000FU /*!<EXTI 12 configuration */
+#define SYSCFG_EXTICR4_EXTI13 0x00F0U /*!<EXTI 13 configuration */
+#define SYSCFG_EXTICR4_EXTI14 0x0F00U /*!<EXTI 14 configuration */
+#define SYSCFG_EXTICR4_EXTI15 0xF000U /*!<EXTI 15 configuration */
+/**
+ * @brief EXTI12 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI12_PA 0x0000U /*!<PA[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PB 0x0001U /*!<PB[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PC 0x0002U /*!<PC[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PD 0x0003U /*!<PD[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PE 0x0004U /*!<PE[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PH 0x0007U /*!<PH[12] pin */
+
+/**
+ * @brief EXTI13 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI13_PA 0x0000U /*!<PA[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PB 0x0010U /*!<PB[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PC 0x0020U /*!<PC[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PD 0x0030U /*!<PD[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PE 0x0040U /*!<PE[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PH 0x0070U /*!<PH[13] pin */
+
+/**
+ * @brief EXTI14 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI14_PA 0x0000U /*!<PA[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PB 0x0100U /*!<PB[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PC 0x0200U /*!<PC[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PD 0x0300U /*!<PD[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PE 0x0400U /*!<PE[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PH 0x0700U /*!<PH[14] pin */
+
+/**
+ * @brief EXTI15 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI15_PA 0x0000U /*!<PA[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PB 0x1000U /*!<PB[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PC 0x2000U /*!<PC[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PD 0x3000U /*!<PD[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PE 0x4000U /*!<PE[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PH 0x7000U /*!<PH[15] pin */
+
+/****************** Bit definition for SYSCFG_CMPCR register ****************/
+#define SYSCFG_CMPCR_CMP_PD 0x00000001U /*!<Compensation cell ready flag */
+#define SYSCFG_CMPCR_READY 0x00000100U /*!<Compensation cell power-down */
+
+/******************************************************************************/
+/* */
+/* TIM */
+/* */
+/******************************************************************************/
+/******************* Bit definition for TIM_CR1 register ********************/
+#define TIM_CR1_CEN 0x0001U /*!<Counter enable */
+#define TIM_CR1_UDIS 0x0002U /*!<Update disable */
+#define TIM_CR1_URS 0x0004U /*!<Update request source */
+#define TIM_CR1_OPM 0x0008U /*!<One pulse mode */
+#define TIM_CR1_DIR 0x0010U /*!<Direction */
+
+#define TIM_CR1_CMS 0x0060U /*!<CMS[1:0] bits (Center-aligned mode selection) */
+#define TIM_CR1_CMS_0 0x0020U /*!<Bit 0 */
+#define TIM_CR1_CMS_1 0x0040U /*!<Bit 1 */
+
+#define TIM_CR1_ARPE 0x0080U /*!<Auto-reload preload enable */
+
+#define TIM_CR1_CKD 0x0300U /*!<CKD[1:0] bits (clock division) */
+#define TIM_CR1_CKD_0 0x0100U /*!<Bit 0 */
+#define TIM_CR1_CKD_1 0x0200U /*!<Bit 1 */
+
+/******************* Bit definition for TIM_CR2 register ********************/
+#define TIM_CR2_CCPC 0x0001U /*!<Capture/Compare Preloaded Control */
+#define TIM_CR2_CCUS 0x0004U /*!<Capture/Compare Control Update Selection */
+#define TIM_CR2_CCDS 0x0008U /*!<Capture/Compare DMA Selection */
+
+#define TIM_CR2_MMS 0x0070U /*!<MMS[2:0] bits (Master Mode Selection) */
+#define TIM_CR2_MMS_0 0x0010U /*!<Bit 0 */
+#define TIM_CR2_MMS_1 0x0020U /*!<Bit 1 */
+#define TIM_CR2_MMS_2 0x0040U /*!<Bit 2 */
+
+#define TIM_CR2_TI1S 0x0080U /*!<TI1 Selection */
+#define TIM_CR2_OIS1 0x0100U /*!<Output Idle state 1 (OC1 output) */
+#define TIM_CR2_OIS1N 0x0200U /*!<Output Idle state 1 (OC1N output) */
+#define TIM_CR2_OIS2 0x0400U /*!<Output Idle state 2 (OC2 output) */
+#define TIM_CR2_OIS2N 0x0800U /*!<Output Idle state 2 (OC2N output) */
+#define TIM_CR2_OIS3 0x1000U /*!<Output Idle state 3 (OC3 output) */
+#define TIM_CR2_OIS3N 0x2000U /*!<Output Idle state 3 (OC3N output) */
+#define TIM_CR2_OIS4 0x4000U /*!<Output Idle state 4 (OC4 output) */
+
+/******************* Bit definition for TIM_SMCR register *******************/
+#define TIM_SMCR_SMS 0x0007U /*!<SMS[2:0] bits (Slave mode selection) */
+#define TIM_SMCR_SMS_0 0x0001U /*!<Bit 0 */
+#define TIM_SMCR_SMS_1 0x0002U /*!<Bit 1 */
+#define TIM_SMCR_SMS_2 0x0004U /*!<Bit 2 */
+
+#define TIM_SMCR_TS 0x0070U /*!<TS[2:0] bits (Trigger selection) */
+#define TIM_SMCR_TS_0 0x0010U /*!<Bit 0 */
+#define TIM_SMCR_TS_1 0x0020U /*!<Bit 1 */
+#define TIM_SMCR_TS_2 0x0040U /*!<Bit 2 */
+
+#define TIM_SMCR_MSM 0x0080U /*!<Master/slave mode */
+
+#define TIM_SMCR_ETF 0x0F00U /*!<ETF[3:0] bits (External trigger filter) */
+#define TIM_SMCR_ETF_0 0x0100U /*!<Bit 0 */
+#define TIM_SMCR_ETF_1 0x0200U /*!<Bit 1 */
+#define TIM_SMCR_ETF_2 0x0400U /*!<Bit 2 */
+#define TIM_SMCR_ETF_3 0x0800U /*!<Bit 3 */
+
+#define TIM_SMCR_ETPS 0x3000U /*!<ETPS[1:0] bits (External trigger prescaler) */
+#define TIM_SMCR_ETPS_0 0x1000U /*!<Bit 0 */
+#define TIM_SMCR_ETPS_1 0x2000U /*!<Bit 1 */
+
+#define TIM_SMCR_ECE 0x4000U /*!<External clock enable */
+#define TIM_SMCR_ETP 0x8000U /*!<External trigger polarity */
+
+/******************* Bit definition for TIM_DIER register *******************/
+#define TIM_DIER_UIE 0x0001U /*!<Update interrupt enable */
+#define TIM_DIER_CC1IE 0x0002U /*!<Capture/Compare 1 interrupt enable */
+#define TIM_DIER_CC2IE 0x0004U /*!<Capture/Compare 2 interrupt enable */
+#define TIM_DIER_CC3IE 0x0008U /*!<Capture/Compare 3 interrupt enable */
+#define TIM_DIER_CC4IE 0x0010U /*!<Capture/Compare 4 interrupt enable */
+#define TIM_DIER_COMIE 0x0020U /*!<COM interrupt enable */
+#define TIM_DIER_TIE 0x0040U /*!<Trigger interrupt enable */
+#define TIM_DIER_BIE 0x0080U /*!<Break interrupt enable */
+#define TIM_DIER_UDE 0x0100U /*!<Update DMA request enable */
+#define TIM_DIER_CC1DE 0x0200U /*!<Capture/Compare 1 DMA request enable */
+#define TIM_DIER_CC2DE 0x0400U /*!<Capture/Compare 2 DMA request enable */
+#define TIM_DIER_CC3DE 0x0800U /*!<Capture/Compare 3 DMA request enable */
+#define TIM_DIER_CC4DE 0x1000U /*!<Capture/Compare 4 DMA request enable */
+#define TIM_DIER_COMDE 0x2000U /*!<COM DMA request enable */
+#define TIM_DIER_TDE 0x4000U /*!<Trigger DMA request enable */
+
+/******************** Bit definition for TIM_SR register ********************/
+#define TIM_SR_UIF 0x0001U /*!<Update interrupt Flag */
+#define TIM_SR_CC1IF 0x0002U /*!<Capture/Compare 1 interrupt Flag */
+#define TIM_SR_CC2IF 0x0004U /*!<Capture/Compare 2 interrupt Flag */
+#define TIM_SR_CC3IF 0x0008U /*!<Capture/Compare 3 interrupt Flag */
+#define TIM_SR_CC4IF 0x0010U /*!<Capture/Compare 4 interrupt Flag */
+#define TIM_SR_COMIF 0x0020U /*!<COM interrupt Flag */
+#define TIM_SR_TIF 0x0040U /*!<Trigger interrupt Flag */
+#define TIM_SR_BIF 0x0080U /*!<Break interrupt Flag */
+#define TIM_SR_CC1OF 0x0200U /*!<Capture/Compare 1 Overcapture Flag */
+#define TIM_SR_CC2OF 0x0400U /*!<Capture/Compare 2 Overcapture Flag */
+#define TIM_SR_CC3OF 0x0800U /*!<Capture/Compare 3 Overcapture Flag */
+#define TIM_SR_CC4OF 0x1000U /*!<Capture/Compare 4 Overcapture Flag */
+
+/******************* Bit definition for TIM_EGR register ********************/
+#define TIM_EGR_UG 0x01U /*!<Update Generation */
+#define TIM_EGR_CC1G 0x02U /*!<Capture/Compare 1 Generation */
+#define TIM_EGR_CC2G 0x04U /*!<Capture/Compare 2 Generation */
+#define TIM_EGR_CC3G 0x08U /*!<Capture/Compare 3 Generation */
+#define TIM_EGR_CC4G 0x10U /*!<Capture/Compare 4 Generation */
+#define TIM_EGR_COMG 0x20U /*!<Capture/Compare Control Update Generation */
+#define TIM_EGR_TG 0x40U /*!<Trigger Generation */
+#define TIM_EGR_BG 0x80U /*!<Break Generation */
+
+/****************** Bit definition for TIM_CCMR1 register *******************/
+#define TIM_CCMR1_CC1S 0x0003U /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
+#define TIM_CCMR1_CC1S_0 0x0001U /*!<Bit 0 */
+#define TIM_CCMR1_CC1S_1 0x0002U /*!<Bit 1 */
+
+#define TIM_CCMR1_OC1FE 0x0004U /*!<Output Compare 1 Fast enable */
+#define TIM_CCMR1_OC1PE 0x0008U /*!<Output Compare 1 Preload enable */
+
+#define TIM_CCMR1_OC1M 0x0070U /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
+#define TIM_CCMR1_OC1M_0 0x0010U /*!<Bit 0 */
+#define TIM_CCMR1_OC1M_1 0x0020U /*!<Bit 1 */
+#define TIM_CCMR1_OC1M_2 0x0040U /*!<Bit 2 */
+
+#define TIM_CCMR1_OC1CE 0x0080U /*!<Output Compare 1Clear Enable */
+
+#define TIM_CCMR1_CC2S 0x0300U /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
+#define TIM_CCMR1_CC2S_0 0x0100U /*!<Bit 0 */
+#define TIM_CCMR1_CC2S_1 0x0200U /*!<Bit 1 */
+
+#define TIM_CCMR1_OC2FE 0x0400U /*!<Output Compare 2 Fast enable */
+#define TIM_CCMR1_OC2PE 0x0800U /*!<Output Compare 2 Preload enable */
+
+#define TIM_CCMR1_OC2M 0x7000U /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
+#define TIM_CCMR1_OC2M_0 0x1000U /*!<Bit 0 */
+#define TIM_CCMR1_OC2M_1 0x2000U /*!<Bit 1 */
+#define TIM_CCMR1_OC2M_2 0x4000U /*!<Bit 2 */
+
+#define TIM_CCMR1_OC2CE 0x8000U /*!<Output Compare 2 Clear Enable */
+
+/*----------------------------------------------------------------------------*/
+
+#define TIM_CCMR1_IC1PSC 0x000CU /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
+#define TIM_CCMR1_IC1PSC_0 0x0004U /*!<Bit 0 */
+#define TIM_CCMR1_IC1PSC_1 0x0008U /*!<Bit 1 */
+
+#define TIM_CCMR1_IC1F 0x00F0U /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
+#define TIM_CCMR1_IC1F_0 0x0010U /*!<Bit 0 */
+#define TIM_CCMR1_IC1F_1 0x0020U /*!<Bit 1 */
+#define TIM_CCMR1_IC1F_2 0x0040U /*!<Bit 2 */
+#define TIM_CCMR1_IC1F_3 0x0080U /*!<Bit 3 */
+
+#define TIM_CCMR1_IC2PSC 0x0C00U /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
+#define TIM_CCMR1_IC2PSC_0 0x0400U /*!<Bit 0 */
+#define TIM_CCMR1_IC2PSC_1 0x0800U /*!<Bit 1 */
+
+#define TIM_CCMR1_IC2F 0xF000U /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
+#define TIM_CCMR1_IC2F_0 0x1000U /*!<Bit 0 */
+#define TIM_CCMR1_IC2F_1 0x2000U /*!<Bit 1 */
+#define TIM_CCMR1_IC2F_2 0x4000U /*!<Bit 2 */
+#define TIM_CCMR1_IC2F_3 0x8000U /*!<Bit 3 */
+
+/****************** Bit definition for TIM_CCMR2 register *******************/
+#define TIM_CCMR2_CC3S 0x0003U /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
+#define TIM_CCMR2_CC3S_0 0x0001U /*!<Bit 0 */
+#define TIM_CCMR2_CC3S_1 0x0002U /*!<Bit 1 */
+
+#define TIM_CCMR2_OC3FE 0x0004U /*!<Output Compare 3 Fast enable */
+#define TIM_CCMR2_OC3PE 0x0008U /*!<Output Compare 3 Preload enable */
+
+#define TIM_CCMR2_OC3M 0x0070U /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
+#define TIM_CCMR2_OC3M_0 0x0010U /*!<Bit 0 */
+#define TIM_CCMR2_OC3M_1 0x0020U /*!<Bit 1 */
+#define TIM_CCMR2_OC3M_2 0x0040U /*!<Bit 2 */
+
+#define TIM_CCMR2_OC3CE 0x0080U /*!<Output Compare 3 Clear Enable */
+
+#define TIM_CCMR2_CC4S 0x0300U /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
+#define TIM_CCMR2_CC4S_0 0x0100U /*!<Bit 0 */
+#define TIM_CCMR2_CC4S_1 0x0200U /*!<Bit 1 */
+
+#define TIM_CCMR2_OC4FE 0x0400U /*!<Output Compare 4 Fast enable */
+#define TIM_CCMR2_OC4PE 0x0800U /*!<Output Compare 4 Preload enable */
+
+#define TIM_CCMR2_OC4M 0x7000U /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
+#define TIM_CCMR2_OC4M_0 0x1000U /*!<Bit 0 */
+#define TIM_CCMR2_OC4M_1 0x2000U /*!<Bit 1 */
+#define TIM_CCMR2_OC4M_2 0x4000U /*!<Bit 2 */
+
+#define TIM_CCMR2_OC4CE 0x8000U /*!<Output Compare 4 Clear Enable */
+
+/*----------------------------------------------------------------------------*/
+
+#define TIM_CCMR2_IC3PSC 0x000CU /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
+#define TIM_CCMR2_IC3PSC_0 0x0004U /*!<Bit 0 */
+#define TIM_CCMR2_IC3PSC_1 0x0008U /*!<Bit 1 */
+
+#define TIM_CCMR2_IC3F 0x00F0U /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
+#define TIM_CCMR2_IC3F_0 0x0010U /*!<Bit 0 */
+#define TIM_CCMR2_IC3F_1 0x0020U /*!<Bit 1 */
+#define TIM_CCMR2_IC3F_2 0x0040U /*!<Bit 2 */
+#define TIM_CCMR2_IC3F_3 0x0080U /*!<Bit 3 */
+
+#define TIM_CCMR2_IC4PSC 0x0C00U /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
+#define TIM_CCMR2_IC4PSC_0 0x0400U /*!<Bit 0 */
+#define TIM_CCMR2_IC4PSC_1 0x0800U /*!<Bit 1 */
+
+#define TIM_CCMR2_IC4F 0xF000U /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
+#define TIM_CCMR2_IC4F_0 0x1000U /*!<Bit 0 */
+#define TIM_CCMR2_IC4F_1 0x2000U /*!<Bit 1 */
+#define TIM_CCMR2_IC4F_2 0x4000U /*!<Bit 2 */
+#define TIM_CCMR2_IC4F_3 0x8000U /*!<Bit 3 */
+
+/******************* Bit definition for TIM_CCER register *******************/
+#define TIM_CCER_CC1E 0x0001U /*!<Capture/Compare 1 output enable */
+#define TIM_CCER_CC1P 0x0002U /*!<Capture/Compare 1 output Polarity */
+#define TIM_CCER_CC1NE 0x0004U /*!<Capture/Compare 1 Complementary output enable */
+#define TIM_CCER_CC1NP 0x0008U /*!<Capture/Compare 1 Complementary output Polarity */
+#define TIM_CCER_CC2E 0x0010U /*!<Capture/Compare 2 output enable */
+#define TIM_CCER_CC2P 0x0020U /*!<Capture/Compare 2 output Polarity */
+#define TIM_CCER_CC2NE 0x0040U /*!<Capture/Compare 2 Complementary output enable */
+#define TIM_CCER_CC2NP 0x0080U /*!<Capture/Compare 2 Complementary output Polarity */
+#define TIM_CCER_CC3E 0x0100U /*!<Capture/Compare 3 output enable */
+#define TIM_CCER_CC3P 0x0200U /*!<Capture/Compare 3 output Polarity */
+#define TIM_CCER_CC3NE 0x0400U /*!<Capture/Compare 3 Complementary output enable */
+#define TIM_CCER_CC3NP 0x0800U /*!<Capture/Compare 3 Complementary output Polarity */
+#define TIM_CCER_CC4E 0x1000U /*!<Capture/Compare 4 output enable */
+#define TIM_CCER_CC4P 0x2000U /*!<Capture/Compare 4 output Polarity */
+#define TIM_CCER_CC4NP 0x8000U /*!<Capture/Compare 4 Complementary output Polarity */
+
+/******************* Bit definition for TIM_CNT register ********************/
+#define TIM_CNT_CNT 0xFFFFU /*!<Counter Value */
+
+/******************* Bit definition for TIM_PSC register ********************/
+#define TIM_PSC_PSC 0xFFFFU /*!<Prescaler Value */
+
+/******************* Bit definition for TIM_ARR register ********************/
+#define TIM_ARR_ARR 0xFFFFU /*!<actual auto-reload Value */
+
+/******************* Bit definition for TIM_RCR register ********************/
+#define TIM_RCR_REP 0xFFU /*!<Repetition Counter Value */
+
+/******************* Bit definition for TIM_CCR1 register *******************/
+#define TIM_CCR1_CCR1 0xFFFFU /*!<Capture/Compare 1 Value */
+
+/******************* Bit definition for TIM_CCR2 register *******************/
+#define TIM_CCR2_CCR2 0xFFFFU /*!<Capture/Compare 2 Value */
+
+/******************* Bit definition for TIM_CCR3 register *******************/
+#define TIM_CCR3_CCR3 0xFFFFU /*!<Capture/Compare 3 Value */
+
+/******************* Bit definition for TIM_CCR4 register *******************/
+#define TIM_CCR4_CCR4 0xFFFFU /*!<Capture/Compare 4 Value */
+
+/******************* Bit definition for TIM_BDTR register *******************/
+#define TIM_BDTR_DTG 0x00FFU /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
+#define TIM_BDTR_DTG_0 0x0001U /*!<Bit 0 */
+#define TIM_BDTR_DTG_1 0x0002U /*!<Bit 1 */
+#define TIM_BDTR_DTG_2 0x0004U /*!<Bit 2 */
+#define TIM_BDTR_DTG_3 0x0008U /*!<Bit 3 */
+#define TIM_BDTR_DTG_4 0x0010U /*!<Bit 4 */
+#define TIM_BDTR_DTG_5 0x0020U /*!<Bit 5 */
+#define TIM_BDTR_DTG_6 0x0040U /*!<Bit 6 */
+#define TIM_BDTR_DTG_7 0x0080U /*!<Bit 7 */
+
+#define TIM_BDTR_LOCK 0x0300U /*!<LOCK[1:0] bits (Lock Configuration) */
+#define TIM_BDTR_LOCK_0 0x0100U /*!<Bit 0 */
+#define TIM_BDTR_LOCK_1 0x0200U /*!<Bit 1 */
+
+#define TIM_BDTR_OSSI 0x0400U /*!<Off-State Selection for Idle mode */
+#define TIM_BDTR_OSSR 0x0800U /*!<Off-State Selection for Run mode */
+#define TIM_BDTR_BKE 0x1000U /*!<Break enable */
+#define TIM_BDTR_BKP 0x2000U /*!<Break Polarity */
+#define TIM_BDTR_AOE 0x4000U /*!<Automatic Output enable */
+#define TIM_BDTR_MOE 0x8000U /*!<Main Output enable */
+
+/******************* Bit definition for TIM_DCR register ********************/
+#define TIM_DCR_DBA 0x001FU /*!<DBA[4:0] bits (DMA Base Address) */
+#define TIM_DCR_DBA_0 0x0001U /*!<Bit 0 */
+#define TIM_DCR_DBA_1 0x0002U /*!<Bit 1 */
+#define TIM_DCR_DBA_2 0x0004U /*!<Bit 2 */
+#define TIM_DCR_DBA_3 0x0008U /*!<Bit 3 */
+#define TIM_DCR_DBA_4 0x0010U /*!<Bit 4 */
+
+#define TIM_DCR_DBL 0x1F00U /*!<DBL[4:0] bits (DMA Burst Length) */
+#define TIM_DCR_DBL_0 0x0100U /*!<Bit 0 */
+#define TIM_DCR_DBL_1 0x0200U /*!<Bit 1 */
+#define TIM_DCR_DBL_2 0x0400U /*!<Bit 2 */
+#define TIM_DCR_DBL_3 0x0800U /*!<Bit 3 */
+#define TIM_DCR_DBL_4 0x1000U /*!<Bit 4 */
+
+/******************* Bit definition for TIM_DMAR register *******************/
+#define TIM_DMAR_DMAB 0xFFFFU /*!<DMA register for burst accesses */
+
+/******************* Bit definition for TIM_OR register *********************/
+#define TIM_OR_TI4_RMP 0x00C0U /*!<TI4_RMP[1:0] bits (TIM5 Input 4 remap) */
+#define TIM_OR_TI4_RMP_0 0x0040U /*!<Bit 0 */
+#define TIM_OR_TI4_RMP_1 0x0080U /*!<Bit 1 */
+#define TIM_OR_ITR1_RMP 0x0C00U /*!<ITR1_RMP[1:0] bits (TIM2 Internal trigger 1 remap) */
+#define TIM_OR_ITR1_RMP_0 0x0400U /*!<Bit 0 */
+#define TIM_OR_ITR1_RMP_1 0x0800U /*!<Bit 1 */
+
+
+/******************************************************************************/
+/* */
+/* Universal Synchronous Asynchronous Receiver Transmitter */
+/* */
+/******************************************************************************/
+/******************* Bit definition for USART_SR register *******************/
+#define USART_SR_PE 0x0001U /*!<Parity Error */
+#define USART_SR_FE 0x0002U /*!<Framing Error */
+#define USART_SR_NE 0x0004U /*!<Noise Error Flag */
+#define USART_SR_ORE 0x0008U /*!<OverRun Error */
+#define USART_SR_IDLE 0x0010U /*!<IDLE line detected */
+#define USART_SR_RXNE 0x0020U /*!<Read Data Register Not Empty */
+#define USART_SR_TC 0x0040U /*!<Transmission Complete */
+#define USART_SR_TXE 0x0080U /*!<Transmit Data Register Empty */
+#define USART_SR_LBD 0x0100U /*!<LIN Break Detection Flag */
+#define USART_SR_CTS 0x0200U /*!<CTS Flag */
+
+/******************* Bit definition for USART_DR register *******************/
+#define USART_DR_DR 0x01FFU /*!<Data value */
+
+/****************** Bit definition for USART_BRR register *******************/
+#define USART_BRR_DIV_Fraction 0x000FU /*!<Fraction of USARTDIV */
+#define USART_BRR_DIV_Mantissa 0xFFF0U /*!<Mantissa of USARTDIV */
+
+/****************** Bit definition for USART_CR1 register *******************/
+#define USART_CR1_SBK 0x0001U /*!<Send Break */
+#define USART_CR1_RWU 0x0002U /*!<Receiver wakeup */
+#define USART_CR1_RE 0x0004U /*!<Receiver Enable */
+#define USART_CR1_TE 0x0008U /*!<Transmitter Enable */
+#define USART_CR1_IDLEIE 0x0010U /*!<IDLE Interrupt Enable */
+#define USART_CR1_RXNEIE 0x0020U /*!<RXNE Interrupt Enable */
+#define USART_CR1_TCIE 0x0040U /*!<Transmission Complete Interrupt Enable */
+#define USART_CR1_TXEIE 0x0080U /*!<PE Interrupt Enable */
+#define USART_CR1_PEIE 0x0100U /*!<PE Interrupt Enable */
+#define USART_CR1_PS 0x0200U /*!<Parity Selection */
+#define USART_CR1_PCE 0x0400U /*!<Parity Control Enable */
+#define USART_CR1_WAKE 0x0800U /*!<Wakeup method */
+#define USART_CR1_M 0x1000U /*!<Word length */
+#define USART_CR1_UE 0x2000U /*!<USART Enable */
+#define USART_CR1_OVER8 0x8000U /*!<USART Oversampling by 8 enable */
+
+/****************** Bit definition for USART_CR2 register *******************/
+#define USART_CR2_ADD 0x000FU /*!<Address of the USART node */
+#define USART_CR2_LBDL 0x0020U /*!<LIN Break Detection Length */
+#define USART_CR2_LBDIE 0x0040U /*!<LIN Break Detection Interrupt Enable */
+#define USART_CR2_LBCL 0x0100U /*!<Last Bit Clock pulse */
+#define USART_CR2_CPHA 0x0200U /*!<Clock Phase */
+#define USART_CR2_CPOL 0x0400U /*!<Clock Polarity */
+#define USART_CR2_CLKEN 0x0800U /*!<Clock Enable */
+
+#define USART_CR2_STOP 0x3000U /*!<STOP[1:0] bits (STOP bits) */
+#define USART_CR2_STOP_0 0x1000U /*!<Bit 0 */
+#define USART_CR2_STOP_1 0x2000U /*!<Bit 1 */
+
+#define USART_CR2_LINEN 0x4000U /*!<LIN mode enable */
+
+/****************** Bit definition for USART_CR3 register *******************/
+#define USART_CR3_EIE 0x0001U /*!<Error Interrupt Enable */
+#define USART_CR3_IREN 0x0002U /*!<IrDA mode Enable */
+#define USART_CR3_IRLP 0x0004U /*!<IrDA Low-Power */
+#define USART_CR3_HDSEL 0x0008U /*!<Half-Duplex Selection */
+#define USART_CR3_NACK 0x0010U /*!<Smartcard NACK enable */
+#define USART_CR3_SCEN 0x0020U /*!<Smartcard mode enable */
+#define USART_CR3_DMAR 0x0040U /*!<DMA Enable Receiver */
+#define USART_CR3_DMAT 0x0080U /*!<DMA Enable Transmitter */
+#define USART_CR3_RTSE 0x0100U /*!<RTS Enable */
+#define USART_CR3_CTSE 0x0200U /*!<CTS Enable */
+#define USART_CR3_CTSIE 0x0400U /*!<CTS Interrupt Enable */
+#define USART_CR3_ONEBIT 0x0800U /*!<USART One bit method enable */
+
+/****************** Bit definition for USART_GTPR register ******************/
+#define USART_GTPR_PSC 0x00FFU /*!<PSC[7:0] bits (Prescaler value) */
+#define USART_GTPR_PSC_0 0x0001U /*!<Bit 0 */
+#define USART_GTPR_PSC_1 0x0002U /*!<Bit 1 */
+#define USART_GTPR_PSC_2 0x0004U /*!<Bit 2 */
+#define USART_GTPR_PSC_3 0x0008U /*!<Bit 3 */
+#define USART_GTPR_PSC_4 0x0010U /*!<Bit 4 */
+#define USART_GTPR_PSC_5 0x0020U /*!<Bit 5 */
+#define USART_GTPR_PSC_6 0x0040U /*!<Bit 6 */
+#define USART_GTPR_PSC_7 0x0080U /*!<Bit 7 */
+
+#define USART_GTPR_GT 0xFF00U /*!<Guard time value */
+
+/******************************************************************************/
+/* */
+/* Window WATCHDOG */
+/* */
+/******************************************************************************/
+/******************* Bit definition for WWDG_CR register ********************/
+#define WWDG_CR_T 0x7FU /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
+#define WWDG_CR_T_0 0x01U /*!<Bit 0 */
+#define WWDG_CR_T_1 0x02U /*!<Bit 1 */
+#define WWDG_CR_T_2 0x04U /*!<Bit 2 */
+#define WWDG_CR_T_3 0x08U /*!<Bit 3 */
+#define WWDG_CR_T_4 0x10U /*!<Bit 4 */
+#define WWDG_CR_T_5 0x20U /*!<Bit 5 */
+#define WWDG_CR_T_6 0x40U /*!<Bit 6 */
+/* Legacy defines */
+#define WWDG_CR_T0 WWDG_CR_T_0
+#define WWDG_CR_T1 WWDG_CR_T_1
+#define WWDG_CR_T2 WWDG_CR_T_2
+#define WWDG_CR_T3 WWDG_CR_T_3
+#define WWDG_CR_T4 WWDG_CR_T_4
+#define WWDG_CR_T5 WWDG_CR_T_5
+#define WWDG_CR_T6 WWDG_CR_T_6
+
+#define WWDG_CR_WDGA 0x80U /*!<Activation bit */
+
+/******************* Bit definition for WWDG_CFR register *******************/
+#define WWDG_CFR_W 0x007FU /*!<W[6:0] bits (7-bit window value) */
+#define WWDG_CFR_W_0 0x0001U /*!<Bit 0 */
+#define WWDG_CFR_W_1 0x0002U /*!<Bit 1 */
+#define WWDG_CFR_W_2 0x0004U /*!<Bit 2 */
+#define WWDG_CFR_W_3 0x0008U /*!<Bit 3 */
+#define WWDG_CFR_W_4 0x0010U /*!<Bit 4 */
+#define WWDG_CFR_W_5 0x0020U /*!<Bit 5 */
+#define WWDG_CFR_W_6 0x0040U /*!<Bit 6 */
+/* Legacy defines */
+#define WWDG_CFR_W0 WWDG_CFR_W_0
+#define WWDG_CFR_W1 WWDG_CFR_W_1
+#define WWDG_CFR_W2 WWDG_CFR_W_2
+#define WWDG_CFR_W3 WWDG_CFR_W_3
+#define WWDG_CFR_W4 WWDG_CFR_W_4
+#define WWDG_CFR_W5 WWDG_CFR_W_5
+#define WWDG_CFR_W6 WWDG_CFR_W_6
+
+#define WWDG_CFR_WDGTB 0x0180U /*!<WDGTB[1:0] bits (Timer Base) */
+#define WWDG_CFR_WDGTB_0 0x0080U /*!<Bit 0 */
+#define WWDG_CFR_WDGTB_1 0x0100U /*!<Bit 1 */
+/* Legacy defines */
+#define WWDG_CFR_WDGTB0 WWDG_CFR_WDGTB_0
+#define WWDG_CFR_WDGTB1 WWDG_CFR_WDGTB_1
+
+#define WWDG_CFR_EWI 0x0200U /*!<Early Wakeup Interrupt */
+
+/******************* Bit definition for WWDG_SR register ********************/
+#define WWDG_SR_EWIF 0x01U /*!<Early Wakeup Interrupt Flag */
+
+
+/******************************************************************************/
+/* */
+/* DBG */
+/* */
+/******************************************************************************/
+/******************** Bit definition for DBGMCU_IDCODE register *************/
+#define DBGMCU_IDCODE_DEV_ID 0x00000FFFU
+#define DBGMCU_IDCODE_REV_ID 0xFFFF0000U
+
+/******************** Bit definition for DBGMCU_CR register *****************/
+#define DBGMCU_CR_DBG_SLEEP 0x00000001U
+#define DBGMCU_CR_DBG_STOP 0x00000002U
+#define DBGMCU_CR_DBG_STANDBY 0x00000004U
+#define DBGMCU_CR_TRACE_IOEN 0x00000020U
+
+#define DBGMCU_CR_TRACE_MODE 0x000000C0U
+#define DBGMCU_CR_TRACE_MODE_0 0x00000040U/*!<Bit 0 */
+#define DBGMCU_CR_TRACE_MODE_1 0x00000080U/*!<Bit 1 */
+
+/******************** Bit definition for DBGMCU_APB1_FZ register ************/
+#define DBGMCU_APB1_FZ_DBG_TIM2_STOP 0x00000001U
+#define DBGMCU_APB1_FZ_DBG_TIM3_STOP 0x00000002U
+#define DBGMCU_APB1_FZ_DBG_TIM4_STOP 0x00000004U
+#define DBGMCU_APB1_FZ_DBG_TIM5_STOP 0x00000008U
+#define DBGMCU_APB1_FZ_DBG_TIM6_STOP 0x00000010U
+#define DBGMCU_APB1_FZ_DBG_TIM7_STOP 0x00000020U
+#define DBGMCU_APB1_FZ_DBG_TIM12_STOP 0x00000040U
+#define DBGMCU_APB1_FZ_DBG_TIM13_STOP 0x00000080U
+#define DBGMCU_APB1_FZ_DBG_TIM14_STOP 0x00000100U
+#define DBGMCU_APB1_FZ_DBG_RTC_STOP 0x00000400U
+#define DBGMCU_APB1_FZ_DBG_WWDG_STOP 0x00000800U
+#define DBGMCU_APB1_FZ_DBG_IWDG_STOP 0x00001000U
+#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT 0x00200000U
+#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT 0x00400000U
+#define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT 0x00800000U
+#define DBGMCU_APB1_FZ_DBG_CAN1_STOP 0x02000000U
+#define DBGMCU_APB1_FZ_DBG_CAN2_STOP 0x04000000U
+/* Old IWDGSTOP bit definition, maintained for legacy purpose */
+#define DBGMCU_APB1_FZ_DBG_IWDEG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP
+
+/******************** Bit definition for DBGMCU_APB2_FZ register ************/
+#define DBGMCU_APB2_FZ_DBG_TIM1_STOP 0x00000001U
+#define DBGMCU_APB2_FZ_DBG_TIM8_STOP 0x00000002U
+#define DBGMCU_APB2_FZ_DBG_TIM9_STOP 0x00010000U
+#define DBGMCU_APB2_FZ_DBG_TIM10_STOP 0x00020000U
+#define DBGMCU_APB2_FZ_DBG_TIM11_STOP 0x00040000U
+
+/******************************************************************************/
+/* */
+/* USB_OTG */
+/* */
+/******************************************************************************/
+/******************** Bit definition forUSB_OTG_GOTGCTL register ********************/
+#define USB_OTG_GOTGCTL_SRQSCS 0x00000001U /*!< Session request success */
+#define USB_OTG_GOTGCTL_SRQ 0x00000002U /*!< Session request */
+#define USB_OTG_GOTGCTL_HNGSCS 0x00000100U /*!< Host negotiation success */
+#define USB_OTG_GOTGCTL_HNPRQ 0x00000200U /*!< HNP request */
+#define USB_OTG_GOTGCTL_HSHNPEN 0x00000400U /*!< Host set HNP enable */
+#define USB_OTG_GOTGCTL_DHNPEN 0x00000800U /*!< Device HNP enabled */
+#define USB_OTG_GOTGCTL_CIDSTS 0x00010000U /*!< Connector ID status */
+#define USB_OTG_GOTGCTL_DBCT 0x00020000U /*!< Long/short debounce time */
+#define USB_OTG_GOTGCTL_ASVLD 0x00040000U /*!< A-session valid */
+#define USB_OTG_GOTGCTL_BSVLD 0x00080000U /*!< B-session valid */
+
+/******************** Bit definition forUSB_OTG_HCFG register ********************/
+
+#define USB_OTG_HCFG_FSLSPCS 0x00000003U /*!< FS/LS PHY clock select */
+#define USB_OTG_HCFG_FSLSPCS_0 0x00000001U /*!<Bit 0 */
+#define USB_OTG_HCFG_FSLSPCS_1 0x00000002U /*!<Bit 1 */
+#define USB_OTG_HCFG_FSLSS 0x00000004U /*!< FS- and LS-only support */
+
+/******************** Bit definition forUSB_OTG_DCFG register ********************/
+
+#define USB_OTG_DCFG_DSPD 0x00000003U /*!< Device speed */
+#define USB_OTG_DCFG_DSPD_0 0x00000001U /*!<Bit 0 */
+#define USB_OTG_DCFG_DSPD_1 0x00000002U /*!<Bit 1 */
+#define USB_OTG_DCFG_NZLSOHSK 0x00000004U /*!< Nonzero-length status OUT handshake */
+
+#define USB_OTG_DCFG_DAD 0x000007F0U /*!< Device address */
+#define USB_OTG_DCFG_DAD_0 0x00000010U /*!<Bit 0 */
+#define USB_OTG_DCFG_DAD_1 0x00000020U /*!<Bit 1 */
+#define USB_OTG_DCFG_DAD_2 0x00000040U /*!<Bit 2 */
+#define USB_OTG_DCFG_DAD_3 0x00000080U /*!<Bit 3 */
+#define USB_OTG_DCFG_DAD_4 0x00000100U /*!<Bit 4 */
+#define USB_OTG_DCFG_DAD_5 0x00000200U /*!<Bit 5 */
+#define USB_OTG_DCFG_DAD_6 0x00000400U /*!<Bit 6 */
+
+#define USB_OTG_DCFG_PFIVL 0x00001800U /*!< Periodic (micro)frame interval */
+#define USB_OTG_DCFG_PFIVL_0 0x00000800U /*!<Bit 0 */
+#define USB_OTG_DCFG_PFIVL_1 0x00001000U /*!<Bit 1 */
+
+#define USB_OTG_DCFG_PERSCHIVL 0x03000000U /*!< Periodic scheduling interval */
+#define USB_OTG_DCFG_PERSCHIVL_0 0x01000000U /*!<Bit 0 */
+#define USB_OTG_DCFG_PERSCHIVL_1 0x02000000U /*!<Bit 1 */
+
+/******************** Bit definition forUSB_OTG_PCGCR register ********************/
+#define USB_OTG_PCGCR_STPPCLK 0x00000001U /*!< Stop PHY clock */
+#define USB_OTG_PCGCR_GATEHCLK 0x00000002U /*!< Gate HCLK */
+#define USB_OTG_PCGCR_PHYSUSP 0x00000010U /*!< PHY suspended */
+
+/******************** Bit definition forUSB_OTG_GOTGINT register ********************/
+#define USB_OTG_GOTGINT_SEDET 0x00000004U /*!< Session end detected */
+#define USB_OTG_GOTGINT_SRSSCHG 0x00000100U /*!< Session request success status change */
+#define USB_OTG_GOTGINT_HNSSCHG 0x00000200U /*!< Host negotiation success status change */
+#define USB_OTG_GOTGINT_HNGDET 0x00020000U /*!< Host negotiation detected */
+#define USB_OTG_GOTGINT_ADTOCHG 0x00040000U /*!< A-device timeout change */
+#define USB_OTG_GOTGINT_DBCDNE 0x00080000U /*!< Debounce done */
+
+/******************** Bit definition forUSB_OTG_DCTL register ********************/
+#define USB_OTG_DCTL_RWUSIG 0x00000001U /*!< Remote wakeup signaling */
+#define USB_OTG_DCTL_SDIS 0x00000002U /*!< Soft disconnect */
+#define USB_OTG_DCTL_GINSTS 0x00000004U /*!< Global IN NAK status */
+#define USB_OTG_DCTL_GONSTS 0x00000008U /*!< Global OUT NAK status */
+
+#define USB_OTG_DCTL_TCTL 0x00000070U /*!< Test control */
+#define USB_OTG_DCTL_TCTL_0 0x00000010U /*!<Bit 0 */
+#define USB_OTG_DCTL_TCTL_1 0x00000020U /*!<Bit 1 */
+#define USB_OTG_DCTL_TCTL_2 0x00000040U /*!<Bit 2 */
+#define USB_OTG_DCTL_SGINAK 0x00000080U /*!< Set global IN NAK */
+#define USB_OTG_DCTL_CGINAK 0x00000100U /*!< Clear global IN NAK */
+#define USB_OTG_DCTL_SGONAK 0x00000200U /*!< Set global OUT NAK */
+#define USB_OTG_DCTL_CGONAK 0x00000400U /*!< Clear global OUT NAK */
+#define USB_OTG_DCTL_POPRGDNE 0x00000800U /*!< Power-on programming done */
+
+/******************** Bit definition forUSB_OTG_HFIR register ********************/
+#define USB_OTG_HFIR_FRIVL 0x0000FFFFU /*!< Frame interval */
+
+/******************** Bit definition forUSB_OTG_HFNUM register ********************/
+#define USB_OTG_HFNUM_FRNUM 0x0000FFFFU /*!< Frame number */
+#define USB_OTG_HFNUM_FTREM 0xFFFF0000U /*!< Frame time remaining */
+
+/******************** Bit definition forUSB_OTG_DSTS register ********************/
+#define USB_OTG_DSTS_SUSPSTS 0x00000001U /*!< Suspend status */
+
+#define USB_OTG_DSTS_ENUMSPD 0x00000006U /*!< Enumerated speed */
+#define USB_OTG_DSTS_ENUMSPD_0 0x00000002U /*!<Bit 0 */
+#define USB_OTG_DSTS_ENUMSPD_1 0x00000004U /*!<Bit 1 */
+#define USB_OTG_DSTS_EERR 0x00000008U /*!< Erratic error */
+#define USB_OTG_DSTS_FNSOF 0x003FFF00U /*!< Frame number of the received SOF */
+
+/******************** Bit definition forUSB_OTG_GAHBCFG register ********************/
+#define USB_OTG_GAHBCFG_GINT 0x00000001U /*!< Global interrupt mask */
+
+#define USB_OTG_GAHBCFG_HBSTLEN 0x0000001EU /*!< Burst length/type */
+#define USB_OTG_GAHBCFG_HBSTLEN_0 0x00000002U /*!<Bit 0 */
+#define USB_OTG_GAHBCFG_HBSTLEN_1 0x00000004U /*!<Bit 1 */
+#define USB_OTG_GAHBCFG_HBSTLEN_2 0x00000008U /*!<Bit 2 */
+#define USB_OTG_GAHBCFG_HBSTLEN_3 0x00000010U /*!<Bit 3 */
+#define USB_OTG_GAHBCFG_DMAEN 0x00000020U /*!< DMA enable */
+#define USB_OTG_GAHBCFG_TXFELVL 0x00000080U /*!< TxFIFO empty level */
+#define USB_OTG_GAHBCFG_PTXFELVL 0x00000100U /*!< Periodic TxFIFO empty level */
+
+/******************** Bit definition forUSB_OTG_GUSBCFG register ********************/
+
+#define USB_OTG_GUSBCFG_TOCAL 0x00000007U /*!< FS timeout calibration */
+#define USB_OTG_GUSBCFG_TOCAL_0 0x00000001U /*!<Bit 0 */
+#define USB_OTG_GUSBCFG_TOCAL_1 0x00000002U /*!<Bit 1 */
+#define USB_OTG_GUSBCFG_TOCAL_2 0x00000004U /*!<Bit 2 */
+#define USB_OTG_GUSBCFG_PHYSEL 0x00000040U /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */
+#define USB_OTG_GUSBCFG_SRPCAP 0x00000100U /*!< SRP-capable */
+#define USB_OTG_GUSBCFG_HNPCAP 0x00000200U /*!< HNP-capable */
+
+#define USB_OTG_GUSBCFG_TRDT 0x00003C00U /*!< USB turnaround time */
+#define USB_OTG_GUSBCFG_TRDT_0 0x00000400U /*!<Bit 0 */
+#define USB_OTG_GUSBCFG_TRDT_1 0x00000800U /*!<Bit 1 */
+#define USB_OTG_GUSBCFG_TRDT_2 0x00001000U /*!<Bit 2 */
+#define USB_OTG_GUSBCFG_TRDT_3 0x00002000U /*!<Bit 3 */
+#define USB_OTG_GUSBCFG_PHYLPCS 0x00008000U /*!< PHY Low-power clock select */
+#define USB_OTG_GUSBCFG_ULPIFSLS 0x00020000U /*!< ULPI FS/LS select */
+#define USB_OTG_GUSBCFG_ULPIAR 0x00040000U /*!< ULPI Auto-resume */
+#define USB_OTG_GUSBCFG_ULPICSM 0x00080000U /*!< ULPI Clock SuspendM */
+#define USB_OTG_GUSBCFG_ULPIEVBUSD 0x00100000U /*!< ULPI External VBUS Drive */
+#define USB_OTG_GUSBCFG_ULPIEVBUSI 0x00200000U /*!< ULPI external VBUS indicator */
+#define USB_OTG_GUSBCFG_TSDPS 0x00400000U /*!< TermSel DLine pulsing selection */
+#define USB_OTG_GUSBCFG_PCCI 0x00800000U /*!< Indicator complement */
+#define USB_OTG_GUSBCFG_PTCI 0x01000000U /*!< Indicator pass through */
+#define USB_OTG_GUSBCFG_ULPIIPD 0x02000000U /*!< ULPI interface protect disable */
+#define USB_OTG_GUSBCFG_FHMOD 0x20000000U /*!< Forced host mode */
+#define USB_OTG_GUSBCFG_FDMOD 0x40000000U /*!< Forced peripheral mode */
+#define USB_OTG_GUSBCFG_CTXPKT 0x80000000U /*!< Corrupt Tx packet */
+
+/******************** Bit definition forUSB_OTG_GRSTCTL register ********************/
+#define USB_OTG_GRSTCTL_CSRST 0x00000001U /*!< Core soft reset */
+#define USB_OTG_GRSTCTL_HSRST 0x00000002U /*!< HCLK soft reset */
+#define USB_OTG_GRSTCTL_FCRST 0x00000004U /*!< Host frame counter reset */
+#define USB_OTG_GRSTCTL_RXFFLSH 0x00000010U /*!< RxFIFO flush */
+#define USB_OTG_GRSTCTL_TXFFLSH 0x00000020U /*!< TxFIFO flush */
+
+#define USB_OTG_GRSTCTL_TXFNUM 0x000007C0U /*!< TxFIFO number */
+#define USB_OTG_GRSTCTL_TXFNUM_0 0x00000040U /*!<Bit 0 */
+#define USB_OTG_GRSTCTL_TXFNUM_1 0x00000080U /*!<Bit 1 */
+#define USB_OTG_GRSTCTL_TXFNUM_2 0x00000100U /*!<Bit 2 */
+#define USB_OTG_GRSTCTL_TXFNUM_3 0x00000200U /*!<Bit 3 */
+#define USB_OTG_GRSTCTL_TXFNUM_4 0x00000400U /*!<Bit 4 */
+#define USB_OTG_GRSTCTL_DMAREQ 0x40000000U /*!< DMA request signal */
+#define USB_OTG_GRSTCTL_AHBIDL 0x80000000U /*!< AHB master idle */
+
+/******************** Bit definition forUSB_OTG_DIEPMSK register ********************/
+#define USB_OTG_DIEPMSK_XFRCM 0x00000001U /*!< Transfer completed interrupt mask */
+#define USB_OTG_DIEPMSK_EPDM 0x00000002U /*!< Endpoint disabled interrupt mask */
+#define USB_OTG_DIEPMSK_TOM 0x00000008U /*!< Timeout condition mask (nonisochronous endpoints) */
+#define USB_OTG_DIEPMSK_ITTXFEMSK 0x00000010U /*!< IN token received when TxFIFO empty mask */
+#define USB_OTG_DIEPMSK_INEPNMM 0x00000020U /*!< IN token received with EP mismatch mask */
+#define USB_OTG_DIEPMSK_INEPNEM 0x00000040U /*!< IN endpoint NAK effective mask */
+#define USB_OTG_DIEPMSK_TXFURM 0x00000100U /*!< FIFO underrun mask */
+#define USB_OTG_DIEPMSK_BIM 0x00000200U /*!< BNA interrupt mask */
+
+/******************** Bit definition forUSB_OTG_HPTXSTS register ********************/
+#define USB_OTG_HPTXSTS_PTXFSAVL 0x0000FFFFU /*!< Periodic transmit data FIFO space available */
+
+#define USB_OTG_HPTXSTS_PTXQSAV 0x00FF0000U /*!< Periodic transmit request queue space available */
+#define USB_OTG_HPTXSTS_PTXQSAV_0 0x00010000U /*!<Bit 0 */
+#define USB_OTG_HPTXSTS_PTXQSAV_1 0x00020000U /*!<Bit 1 */
+#define USB_OTG_HPTXSTS_PTXQSAV_2 0x00040000U /*!<Bit 2 */
+#define USB_OTG_HPTXSTS_PTXQSAV_3 0x00080000U /*!<Bit 3 */
+#define USB_OTG_HPTXSTS_PTXQSAV_4 0x00100000U /*!<Bit 4 */
+#define USB_OTG_HPTXSTS_PTXQSAV_5 0x00200000U /*!<Bit 5 */
+#define USB_OTG_HPTXSTS_PTXQSAV_6 0x00400000U /*!<Bit 6 */
+#define USB_OTG_HPTXSTS_PTXQSAV_7 0x00800000U /*!<Bit 7 */
+
+#define USB_OTG_HPTXSTS_PTXQTOP 0xFF000000U /*!< Top of the periodic transmit request queue */
+#define USB_OTG_HPTXSTS_PTXQTOP_0 0x01000000U /*!<Bit 0 */
+#define USB_OTG_HPTXSTS_PTXQTOP_1 0x02000000U /*!<Bit 1 */
+#define USB_OTG_HPTXSTS_PTXQTOP_2 0x04000000U /*!<Bit 2 */
+#define USB_OTG_HPTXSTS_PTXQTOP_3 0x08000000U /*!<Bit 3 */
+#define USB_OTG_HPTXSTS_PTXQTOP_4 0x10000000U /*!<Bit 4 */
+#define USB_OTG_HPTXSTS_PTXQTOP_5 0x20000000U /*!<Bit 5 */
+#define USB_OTG_HPTXSTS_PTXQTOP_6 0x40000000U /*!<Bit 6 */
+#define USB_OTG_HPTXSTS_PTXQTOP_7 0x80000000U /*!<Bit 7 */
+
+/******************** Bit definition forUSB_OTG_HAINT register ********************/
+#define USB_OTG_HAINT_HAINT 0x0000FFFFU /*!< Channel interrupts */
+
+/******************** Bit definition forUSB_OTG_DOEPMSK register ********************/
+#define USB_OTG_DOEPMSK_XFRCM 0x00000001U /*!< Transfer completed interrupt mask */
+#define USB_OTG_DOEPMSK_EPDM 0x00000002U /*!< Endpoint disabled interrupt mask */
+#define USB_OTG_DOEPMSK_STUPM 0x00000008U /*!< SETUP phase done mask */
+#define USB_OTG_DOEPMSK_OTEPDM 0x00000010U /*!< OUT token received when endpoint disabled mask */
+#define USB_OTG_DOEPMSK_B2BSTUP 0x00000040U /*!< Back-to-back SETUP packets received mask */
+#define USB_OTG_DOEPMSK_OPEM 0x00000100U /*!< OUT packet error mask */
+#define USB_OTG_DOEPMSK_BOIM 0x00000200U /*!< BNA interrupt mask */
+
+/******************** Bit definition forUSB_OTG_GINTSTS register ********************/
+#define USB_OTG_GINTSTS_CMOD 0x00000001U /*!< Current mode of operation */
+#define USB_OTG_GINTSTS_MMIS 0x00000002U /*!< Mode mismatch interrupt */
+#define USB_OTG_GINTSTS_OTGINT 0x00000004U /*!< OTG interrupt */
+#define USB_OTG_GINTSTS_SOF 0x00000008U /*!< Start of frame */
+#define USB_OTG_GINTSTS_RXFLVL 0x00000010U /*!< RxFIFO nonempty */
+#define USB_OTG_GINTSTS_NPTXFE 0x00000020U /*!< Nonperiodic TxFIFO empty */
+#define USB_OTG_GINTSTS_GINAKEFF 0x00000040U /*!< Global IN nonperiodic NAK effective */
+#define USB_OTG_GINTSTS_BOUTNAKEFF 0x00000080U /*!< Global OUT NAK effective */
+#define USB_OTG_GINTSTS_ESUSP 0x00000400U /*!< Early suspend */
+#define USB_OTG_GINTSTS_USBSUSP 0x00000800U /*!< USB suspend */
+#define USB_OTG_GINTSTS_USBRST 0x00001000U /*!< USB reset */
+#define USB_OTG_GINTSTS_ENUMDNE 0x00002000U /*!< Enumeration done */
+#define USB_OTG_GINTSTS_ISOODRP 0x00004000U /*!< Isochronous OUT packet dropped interrupt */
+#define USB_OTG_GINTSTS_EOPF 0x00008000U /*!< End of periodic frame interrupt */
+#define USB_OTG_GINTSTS_IEPINT 0x00040000U /*!< IN endpoint interrupt */
+#define USB_OTG_GINTSTS_OEPINT 0x00080000U /*!< OUT endpoint interrupt */
+#define USB_OTG_GINTSTS_IISOIXFR 0x00100000U /*!< Incomplete isochronous IN transfer */
+#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT 0x00200000U /*!< Incomplete periodic transfer */
+#define USB_OTG_GINTSTS_DATAFSUSP 0x00400000U /*!< Data fetch suspended */
+#define USB_OTG_GINTSTS_HPRTINT 0x01000000U /*!< Host port interrupt */
+#define USB_OTG_GINTSTS_HCINT 0x02000000U /*!< Host channels interrupt */
+#define USB_OTG_GINTSTS_PTXFE 0x04000000U /*!< Periodic TxFIFO empty */
+#define USB_OTG_GINTSTS_CIDSCHG 0x10000000U /*!< Connector ID status change */
+#define USB_OTG_GINTSTS_DISCINT 0x20000000U /*!< Disconnect detected interrupt */
+#define USB_OTG_GINTSTS_SRQINT 0x40000000U /*!< Session request/new session detected interrupt */
+#define USB_OTG_GINTSTS_WKUINT 0x80000000U /*!< Resume/remote wakeup detected interrupt */
+
+/******************** Bit definition forUSB_OTG_GINTMSK register ********************/
+#define USB_OTG_GINTMSK_MMISM 0x00000002U /*!< Mode mismatch interrupt mask */
+#define USB_OTG_GINTMSK_OTGINT 0x00000004U /*!< OTG interrupt mask */
+#define USB_OTG_GINTMSK_SOFM 0x00000008U /*!< Start of frame mask */
+#define USB_OTG_GINTMSK_RXFLVLM 0x00000010U /*!< Receive FIFO nonempty mask */
+#define USB_OTG_GINTMSK_NPTXFEM 0x00000020U /*!< Nonperiodic TxFIFO empty mask */
+#define USB_OTG_GINTMSK_GINAKEFFM 0x00000040U /*!< Global nonperiodic IN NAK effective mask */
+#define USB_OTG_GINTMSK_GONAKEFFM 0x00000080U /*!< Global OUT NAK effective mask */
+#define USB_OTG_GINTMSK_ESUSPM 0x00000400U /*!< Early suspend mask */
+#define USB_OTG_GINTMSK_USBSUSPM 0x00000800U /*!< USB suspend mask */
+#define USB_OTG_GINTMSK_USBRST 0x00001000U /*!< USB reset mask */
+#define USB_OTG_GINTMSK_ENUMDNEM 0x00002000U /*!< Enumeration done mask */
+#define USB_OTG_GINTMSK_ISOODRPM 0x00004000U /*!< Isochronous OUT packet dropped interrupt mask */
+#define USB_OTG_GINTMSK_EOPFM 0x00008000U /*!< End of periodic frame interrupt mask */
+#define USB_OTG_GINTMSK_EPMISM 0x00020000U /*!< Endpoint mismatch interrupt mask */
+#define USB_OTG_GINTMSK_IEPINT 0x00040000U /*!< IN endpoints interrupt mask */
+#define USB_OTG_GINTMSK_OEPINT 0x00080000U /*!< OUT endpoints interrupt mask */
+#define USB_OTG_GINTMSK_IISOIXFRM 0x00100000U /*!< Incomplete isochronous IN transfer mask */
+#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM 0x00200000U /*!< Incomplete periodic transfer mask */
+#define USB_OTG_GINTMSK_FSUSPM 0x00400000U /*!< Data fetch suspended mask */
+#define USB_OTG_GINTMSK_PRTIM 0x01000000U /*!< Host port interrupt mask */
+#define USB_OTG_GINTMSK_HCIM 0x02000000U /*!< Host channels interrupt mask */
+#define USB_OTG_GINTMSK_PTXFEM 0x04000000U /*!< Periodic TxFIFO empty mask */
+#define USB_OTG_GINTMSK_CIDSCHGM 0x10000000U /*!< Connector ID status change mask */
+#define USB_OTG_GINTMSK_DISCINT 0x20000000U /*!< Disconnect detected interrupt mask */
+#define USB_OTG_GINTMSK_SRQIM 0x40000000U /*!< Session request/new session detected interrupt mask */
+#define USB_OTG_GINTMSK_WUIM 0x80000000U /*!< Resume/remote wakeup detected interrupt mask */
+
+/******************** Bit definition forUSB_OTG_DAINT register ********************/
+#define USB_OTG_DAINT_IEPINT 0x0000FFFFU /*!< IN endpoint interrupt bits */
+#define USB_OTG_DAINT_OEPINT 0xFFFF0000U /*!< OUT endpoint interrupt bits */
+
+/******************** Bit definition forUSB_OTG_HAINTMSK register ********************/
+#define USB_OTG_HAINTMSK_HAINTM 0x0000FFFFU /*!< Channel interrupt mask */
+
+/******************** Bit definition for USB_OTG_GRXSTSP register ********************/
+#define USB_OTG_GRXSTSP_EPNUM 0x0000000FU /*!< IN EP interrupt mask bits */
+#define USB_OTG_GRXSTSP_BCNT 0x00007FF0U /*!< OUT EP interrupt mask bits */
+#define USB_OTG_GRXSTSP_DPID 0x00018000U /*!< OUT EP interrupt mask bits */
+#define USB_OTG_GRXSTSP_PKTSTS 0x001E0000U /*!< OUT EP interrupt mask bits */
+
+/******************** Bit definition forUSB_OTG_DAINTMSK register ********************/
+#define USB_OTG_DAINTMSK_IEPM 0x0000FFFFU /*!< IN EP interrupt mask bits */
+#define USB_OTG_DAINTMSK_OEPM 0xFFFF0000U /*!< OUT EP interrupt mask bits */
+
+/******************** Bit definition for OTG register ********************/
+
+#define USB_OTG_CHNUM 0x0000000FU /*!< Channel number */
+#define USB_OTG_CHNUM_0 0x00000001U /*!<Bit 0 */
+#define USB_OTG_CHNUM_1 0x00000002U /*!<Bit 1 */
+#define USB_OTG_CHNUM_2 0x00000004U /*!<Bit 2 */
+#define USB_OTG_CHNUM_3 0x00000008U /*!<Bit 3 */
+#define USB_OTG_BCNT 0x00007FF0U /*!< Byte count */
+
+#define USB_OTG_DPID 0x00018000U /*!< Data PID */
+#define USB_OTG_DPID_0 0x00008000U /*!<Bit 0 */
+#define USB_OTG_DPID_1 0x00010000U /*!<Bit 1 */
+
+#define USB_OTG_PKTSTS 0x001E0000U /*!< Packet status */
+#define USB_OTG_PKTSTS_0 0x00020000U /*!<Bit 0 */
+#define USB_OTG_PKTSTS_1 0x00040000U /*!<Bit 1 */
+#define USB_OTG_PKTSTS_2 0x00080000U /*!<Bit 2 */
+#define USB_OTG_PKTSTS_3 0x00100000U /*!<Bit 3 */
+
+#define USB_OTG_EPNUM 0x0000000FU /*!< Endpoint number */
+#define USB_OTG_EPNUM_0 0x00000001U /*!<Bit 0 */
+#define USB_OTG_EPNUM_1 0x00000002U /*!<Bit 1 */
+#define USB_OTG_EPNUM_2 0x00000004U /*!<Bit 2 */
+#define USB_OTG_EPNUM_3 0x00000008U /*!<Bit 3 */
+
+#define USB_OTG_FRMNUM 0x01E00000U /*!< Frame number */
+#define USB_OTG_FRMNUM_0 0x00200000U /*!<Bit 0 */
+#define USB_OTG_FRMNUM_1 0x00400000U /*!<Bit 1 */
+#define USB_OTG_FRMNUM_2 0x00800000U /*!<Bit 2 */
+#define USB_OTG_FRMNUM_3 0x01000000U /*!<Bit 3 */
+
+/******************** Bit definition for OTG register ********************/
+
+#define USB_OTG_CHNUM 0x0000000FU /*!< Channel number */
+#define USB_OTG_CHNUM_0 0x00000001U /*!<Bit 0 */
+#define USB_OTG_CHNUM_1 0x00000002U /*!<Bit 1 */
+#define USB_OTG_CHNUM_2 0x00000004U /*!<Bit 2 */
+#define USB_OTG_CHNUM_3 0x00000008U /*!<Bit 3 */
+#define USB_OTG_BCNT 0x00007FF0U /*!< Byte count */
+
+#define USB_OTG_DPID 0x00018000U /*!< Data PID */
+#define USB_OTG_DPID_0 0x00008000U /*!<Bit 0 */
+#define USB_OTG_DPID_1 0x00010000U /*!<Bit 1 */
+
+#define USB_OTG_PKTSTS 0x001E0000U /*!< Packet status */
+#define USB_OTG_PKTSTS_0 0x00020000U /*!<Bit 0 */
+#define USB_OTG_PKTSTS_1 0x00040000U /*!<Bit 1 */
+#define USB_OTG_PKTSTS_2 0x00080000U /*!<Bit 2 */
+#define USB_OTG_PKTSTS_3 0x00100000U /*!<Bit 3 */
+
+#define USB_OTG_EPNUM 0x0000000FU /*!< Endpoint number */
+#define USB_OTG_EPNUM_0 0x00000001U /*!<Bit 0 */
+#define USB_OTG_EPNUM_1 0x00000002U /*!<Bit 1 */
+#define USB_OTG_EPNUM_2 0x00000004U /*!<Bit 2 */
+#define USB_OTG_EPNUM_3 0x00000008U /*!<Bit 3 */
+
+#define USB_OTG_FRMNUM 0x01E00000U /*!< Frame number */
+#define USB_OTG_FRMNUM_0 0x00200000U /*!<Bit 0 */
+#define USB_OTG_FRMNUM_1 0x00400000U /*!<Bit 1 */
+#define USB_OTG_FRMNUM_2 0x00800000U /*!<Bit 2 */
+#define USB_OTG_FRMNUM_3 0x01000000U /*!<Bit 3 */
+
+/******************** Bit definition forUSB_OTG_GRXFSIZ register ********************/
+#define USB_OTG_GRXFSIZ_RXFD 0x0000FFFFU /*!< RxFIFO depth */
+
+/******************** Bit definition forUSB_OTG_DVBUSDIS register ********************/
+#define USB_OTG_DVBUSDIS_VBUSDT 0x0000FFFFU /*!< Device VBUS discharge time */
+
+/******************** Bit definition for OTG register ********************/
+#define USB_OTG_NPTXFSA 0x0000FFFFU /*!< Nonperiodic transmit RAM start address */
+#define USB_OTG_NPTXFD 0xFFFF0000U /*!< Nonperiodic TxFIFO depth */
+#define USB_OTG_TX0FSA 0x0000FFFFU /*!< Endpoint 0 transmit RAM start address */
+#define USB_OTG_TX0FD 0xFFFF0000U /*!< Endpoint 0 TxFIFO depth */
+
+/******************** Bit definition forUSB_OTG_DVBUSPULSE register ********************/
+#define USB_OTG_DVBUSPULSE_DVBUSP 0x00000FFFU /*!< Device VBUS pulsing time */
+
+/******************** Bit definition forUSB_OTG_GNPTXSTS register ********************/
+#define USB_OTG_GNPTXSTS_NPTXFSAV 0x0000FFFFU /*!< Nonperiodic TxFIFO space available */
+
+#define USB_OTG_GNPTXSTS_NPTQXSAV 0x00FF0000U /*!< Nonperiodic transmit request queue space available */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_0 0x00010000U /*!<Bit 0 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_1 0x00020000U /*!<Bit 1 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_2 0x00040000U /*!<Bit 2 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_3 0x00080000U /*!<Bit 3 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_4 0x00100000U /*!<Bit 4 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_5 0x00200000U /*!<Bit 5 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_6 0x00400000U /*!<Bit 6 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_7 0x00800000U /*!<Bit 7 */
+
+#define USB_OTG_GNPTXSTS_NPTXQTOP 0x7F000000U /*!< Top of the nonperiodic transmit request queue */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_0 0x01000000U /*!<Bit 0 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_1 0x02000000U /*!<Bit 1 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_2 0x04000000U /*!<Bit 2 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_3 0x08000000U /*!<Bit 3 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_4 0x10000000U /*!<Bit 4 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_5 0x20000000U /*!<Bit 5 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_6 0x40000000U /*!<Bit 6 */
+
+/******************** Bit definition forUSB_OTG_DTHRCTL register ********************/
+#define USB_OTG_DTHRCTL_NONISOTHREN 0x00000001U /*!< Nonisochronous IN endpoints threshold enable */
+#define USB_OTG_DTHRCTL_ISOTHREN 0x00000002U /*!< ISO IN endpoint threshold enable */
+
+#define USB_OTG_DTHRCTL_TXTHRLEN 0x000007FCU /*!< Transmit threshold length */
+#define USB_OTG_DTHRCTL_TXTHRLEN_0 0x00000004U /*!<Bit 0 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_1 0x00000008U /*!<Bit 1 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_2 0x00000010U /*!<Bit 2 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_3 0x00000020U /*!<Bit 3 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_4 0x00000040U /*!<Bit 4 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_5 0x00000080U /*!<Bit 5 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_6 0x00000100U /*!<Bit 6 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_7 0x00000200U /*!<Bit 7 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_8 0x00000400U /*!<Bit 8 */
+#define USB_OTG_DTHRCTL_RXTHREN 0x00010000U /*!< Receive threshold enable */
+
+#define USB_OTG_DTHRCTL_RXTHRLEN 0x03FE0000U /*!< Receive threshold length */
+#define USB_OTG_DTHRCTL_RXTHRLEN_0 0x00020000U /*!<Bit 0 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_1 0x00040000U /*!<Bit 1 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_2 0x00080000U /*!<Bit 2 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_3 0x00100000U /*!<Bit 3 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_4 0x00200000U /*!<Bit 4 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_5 0x00400000U /*!<Bit 5 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_6 0x00800000U /*!<Bit 6 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_7 0x01000000U /*!<Bit 7 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_8 0x02000000U /*!<Bit 8 */
+#define USB_OTG_DTHRCTL_ARPEN 0x08000000U /*!< Arbiter parking enable */
+
+/******************** Bit definition forUSB_OTG_DIEPEMPMSK register ********************/
+#define USB_OTG_DIEPEMPMSK_INEPTXFEM 0x0000FFFFU /*!< IN EP Tx FIFO empty interrupt mask bits */
+
+/******************** Bit definition forUSB_OTG_DEACHINT register ********************/
+#define USB_OTG_DEACHINT_IEP1INT 0x00000002U /*!< IN endpoint 1interrupt bit */
+#define USB_OTG_DEACHINT_OEP1INT 0x00020000U /*!< OUT endpoint 1 interrupt bit */
+
+/******************** Bit definition forUSB_OTG_GCCFG register ********************/
+#define USB_OTG_GCCFG_PWRDWN 0x00010000U /*!< Power down */
+#define USB_OTG_GCCFG_I2CPADEN 0x00020000U /*!< Enable I2C bus connection for the external I2C PHY interface */
+#define USB_OTG_GCCFG_VBUSASEN 0x00040000U /*!< Enable the VBUS sensing device */
+#define USB_OTG_GCCFG_VBUSBSEN 0x00080000U /*!< Enable the VBUS sensing device */
+#define USB_OTG_GCCFG_SOFOUTEN 0x00100000U /*!< SOF output enable */
+#define USB_OTG_GCCFG_NOVBUSSENS 0x00200000U /*!< VBUS sensing disable option */
+
+/******************** Bit definition forUSB_OTG_DEACHINTMSK register ********************/
+#define USB_OTG_DEACHINTMSK_IEP1INTM 0x00000002U /*!< IN Endpoint 1 interrupt mask bit */
+#define USB_OTG_DEACHINTMSK_OEP1INTM 0x00020000U /*!< OUT Endpoint 1 interrupt mask bit */
+
+/******************** Bit definition forUSB_OTG_CID register ********************/
+#define USB_OTG_CID_PRODUCT_ID 0xFFFFFFFFU /*!< Product ID field */
+
+/******************** Bit definition forUSB_OTG_DIEPEACHMSK1 register ********************/
+#define USB_OTG_DIEPEACHMSK1_XFRCM 0x00000001U /*!< Transfer completed interrupt mask */
+#define USB_OTG_DIEPEACHMSK1_EPDM 0x00000002U /*!< Endpoint disabled interrupt mask */
+#define USB_OTG_DIEPEACHMSK1_TOM 0x00000008U /*!< Timeout condition mask (nonisochronous endpoints) */
+#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK 0x00000010U /*!< IN token received when TxFIFO empty mask */
+#define USB_OTG_DIEPEACHMSK1_INEPNMM 0x00000020U /*!< IN token received with EP mismatch mask */
+#define USB_OTG_DIEPEACHMSK1_INEPNEM 0x00000040U /*!< IN endpoint NAK effective mask */
+#define USB_OTG_DIEPEACHMSK1_TXFURM 0x00000100U /*!< FIFO underrun mask */
+#define USB_OTG_DIEPEACHMSK1_BIM 0x00000200U /*!< BNA interrupt mask */
+#define USB_OTG_DIEPEACHMSK1_NAKM 0x00002000U /*!< NAK interrupt mask */
+
+/******************** Bit definition forUSB_OTG_HPRT register ********************/
+#define USB_OTG_HPRT_PCSTS 0x00000001U /*!< Port connect status */
+#define USB_OTG_HPRT_PCDET 0x00000002U /*!< Port connect detected */
+#define USB_OTG_HPRT_PENA 0x00000004U /*!< Port enable */
+#define USB_OTG_HPRT_PENCHNG 0x00000008U /*!< Port enable/disable change */
+#define USB_OTG_HPRT_POCA 0x00000010U /*!< Port overcurrent active */
+#define USB_OTG_HPRT_POCCHNG 0x00000020U /*!< Port overcurrent change */
+#define USB_OTG_HPRT_PRES 0x00000040U /*!< Port resume */
+#define USB_OTG_HPRT_PSUSP 0x00000080U /*!< Port suspend */
+#define USB_OTG_HPRT_PRST 0x00000100U /*!< Port reset */
+
+#define USB_OTG_HPRT_PLSTS 0x00000C00U /*!< Port line status */
+#define USB_OTG_HPRT_PLSTS_0 0x00000400U /*!<Bit 0 */
+#define USB_OTG_HPRT_PLSTS_1 0x00000800U /*!<Bit 1 */
+#define USB_OTG_HPRT_PPWR 0x00001000U /*!< Port power */
+
+#define USB_OTG_HPRT_PTCTL 0x0001E000U /*!< Port test control */
+#define USB_OTG_HPRT_PTCTL_0 0x00002000U /*!<Bit 0 */
+#define USB_OTG_HPRT_PTCTL_1 0x00004000U /*!<Bit 1 */
+#define USB_OTG_HPRT_PTCTL_2 0x00008000U /*!<Bit 2 */
+#define USB_OTG_HPRT_PTCTL_3 0x00010000U /*!<Bit 3 */
+
+#define USB_OTG_HPRT_PSPD 0x00060000U /*!< Port speed */
+#define USB_OTG_HPRT_PSPD_0 0x00020000U /*!<Bit 0 */
+#define USB_OTG_HPRT_PSPD_1 0x00040000U /*!<Bit 1 */
+
+/******************** Bit definition forUSB_OTG_DOEPEACHMSK1 register ********************/
+#define USB_OTG_DOEPEACHMSK1_XFRCM 0x00000001U /*!< Transfer completed interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_EPDM 0x00000002U /*!< Endpoint disabled interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_TOM 0x00000008U /*!< Timeout condition mask */
+#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK 0x00000010U /*!< IN token received when TxFIFO empty mask */
+#define USB_OTG_DOEPEACHMSK1_INEPNMM 0x00000020U /*!< IN token received with EP mismatch mask */
+#define USB_OTG_DOEPEACHMSK1_INEPNEM 0x00000040U /*!< IN endpoint NAK effective mask */
+#define USB_OTG_DOEPEACHMSK1_TXFURM 0x00000100U /*!< OUT packet error mask */
+#define USB_OTG_DOEPEACHMSK1_BIM 0x00000200U /*!< BNA interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_BERRM 0x00001000U /*!< Bubble error interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_NAKM 0x00002000U /*!< NAK interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_NYETM 0x00004000U /*!< NYET interrupt mask */
+
+/******************** Bit definition forUSB_OTG_HPTXFSIZ register ********************/
+#define USB_OTG_HPTXFSIZ_PTXSA 0x0000FFFFU /*!< Host periodic TxFIFO start address */
+#define USB_OTG_HPTXFSIZ_PTXFD 0xFFFF0000U /*!< Host periodic TxFIFO depth */
+
+/******************** Bit definition forUSB_OTG_DIEPCTL register ********************/
+#define USB_OTG_DIEPCTL_MPSIZ 0x000007FFU /*!< Maximum packet size */
+#define USB_OTG_DIEPCTL_USBAEP 0x00008000U /*!< USB active endpoint */
+#define USB_OTG_DIEPCTL_EONUM_DPID 0x00010000U /*!< Even/odd frame */
+#define USB_OTG_DIEPCTL_NAKSTS 0x00020000U /*!< NAK status */
+
+#define USB_OTG_DIEPCTL_EPTYP 0x000C0000U /*!< Endpoint type */
+#define USB_OTG_DIEPCTL_EPTYP_0 0x00040000U /*!<Bit 0 */
+#define USB_OTG_DIEPCTL_EPTYP_1 0x00080000U /*!<Bit 1 */
+#define USB_OTG_DIEPCTL_STALL 0x00200000U /*!< STALL handshake */
+
+#define USB_OTG_DIEPCTL_TXFNUM 0x03C00000U /*!< TxFIFO number */
+#define USB_OTG_DIEPCTL_TXFNUM_0 0x00400000U /*!<Bit 0 */
+#define USB_OTG_DIEPCTL_TXFNUM_1 0x00800000U /*!<Bit 1 */
+#define USB_OTG_DIEPCTL_TXFNUM_2 0x01000000U /*!<Bit 2 */
+#define USB_OTG_DIEPCTL_TXFNUM_3 0x02000000U /*!<Bit 3 */
+#define USB_OTG_DIEPCTL_CNAK 0x04000000U /*!< Clear NAK */
+#define USB_OTG_DIEPCTL_SNAK 0x08000000U /*!< Set NAK */
+#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM 0x10000000U /*!< Set DATA0 PID */
+#define USB_OTG_DIEPCTL_SODDFRM 0x20000000U /*!< Set odd frame */
+#define USB_OTG_DIEPCTL_EPDIS 0x40000000U /*!< Endpoint disable */
+#define USB_OTG_DIEPCTL_EPENA 0x80000000U /*!< Endpoint enable */
+
+/******************** Bit definition forUSB_OTG_HCCHAR register ********************/
+#define USB_OTG_HCCHAR_MPSIZ 0x000007FFU /*!< Maximum packet size */
+
+#define USB_OTG_HCCHAR_EPNUM 0x00007800U /*!< Endpoint number */
+#define USB_OTG_HCCHAR_EPNUM_0 0x00000800U /*!<Bit 0 */
+#define USB_OTG_HCCHAR_EPNUM_1 0x00001000U /*!<Bit 1 */
+#define USB_OTG_HCCHAR_EPNUM_2 0x00002000U /*!<Bit 2 */
+#define USB_OTG_HCCHAR_EPNUM_3 0x00004000U /*!<Bit 3 */
+#define USB_OTG_HCCHAR_EPDIR 0x00008000U /*!< Endpoint direction */
+#define USB_OTG_HCCHAR_LSDEV 0x00020000U /*!< Low-speed device */
+
+#define USB_OTG_HCCHAR_EPTYP 0x000C0000U /*!< Endpoint type */
+#define USB_OTG_HCCHAR_EPTYP_0 0x00040000U /*!<Bit 0 */
+#define USB_OTG_HCCHAR_EPTYP_1 0x00080000U /*!<Bit 1 */
+
+#define USB_OTG_HCCHAR_MC 0x00300000U /*!< Multi Count (MC) / Error Count (EC) */
+#define USB_OTG_HCCHAR_MC_0 0x00100000U /*!<Bit 0 */
+#define USB_OTG_HCCHAR_MC_1 0x00200000U /*!<Bit 1 */
+
+#define USB_OTG_HCCHAR_DAD 0x1FC00000U /*!< Device address */
+#define USB_OTG_HCCHAR_DAD_0 0x00400000U /*!<Bit 0 */
+#define USB_OTG_HCCHAR_DAD_1 0x00800000U /*!<Bit 1 */
+#define USB_OTG_HCCHAR_DAD_2 0x01000000U /*!<Bit 2 */
+#define USB_OTG_HCCHAR_DAD_3 0x02000000U /*!<Bit 3 */
+#define USB_OTG_HCCHAR_DAD_4 0x04000000U /*!<Bit 4 */
+#define USB_OTG_HCCHAR_DAD_5 0x08000000U /*!<Bit 5 */
+#define USB_OTG_HCCHAR_DAD_6 0x10000000U /*!<Bit 6 */
+#define USB_OTG_HCCHAR_ODDFRM 0x20000000U /*!< Odd frame */
+#define USB_OTG_HCCHAR_CHDIS 0x40000000U /*!< Channel disable */
+#define USB_OTG_HCCHAR_CHENA 0x80000000U /*!< Channel enable */
+
+/******************** Bit definition forUSB_OTG_HCSPLT register ********************/
+
+#define USB_OTG_HCSPLT_PRTADDR 0x0000007FU /*!< Port address */
+#define USB_OTG_HCSPLT_PRTADDR_0 0x00000001U /*!<Bit 0 */
+#define USB_OTG_HCSPLT_PRTADDR_1 0x00000002U /*!<Bit 1 */
+#define USB_OTG_HCSPLT_PRTADDR_2 0x00000004U /*!<Bit 2 */
+#define USB_OTG_HCSPLT_PRTADDR_3 0x00000008U /*!<Bit 3 */
+#define USB_OTG_HCSPLT_PRTADDR_4 0x00000010U /*!<Bit 4 */
+#define USB_OTG_HCSPLT_PRTADDR_5 0x00000020U /*!<Bit 5 */
+#define USB_OTG_HCSPLT_PRTADDR_6 0x00000040U /*!<Bit 6 */
+
+#define USB_OTG_HCSPLT_HUBADDR 0x00003F80U /*!< Hub address */
+#define USB_OTG_HCSPLT_HUBADDR_0 0x00000080U /*!<Bit 0 */
+#define USB_OTG_HCSPLT_HUBADDR_1 0x00000100U /*!<Bit 1 */
+#define USB_OTG_HCSPLT_HUBADDR_2 0x00000200U /*!<Bit 2 */
+#define USB_OTG_HCSPLT_HUBADDR_3 0x00000400U /*!<Bit 3 */
+#define USB_OTG_HCSPLT_HUBADDR_4 0x00000800U /*!<Bit 4 */
+#define USB_OTG_HCSPLT_HUBADDR_5 0x00001000U /*!<Bit 5 */
+#define USB_OTG_HCSPLT_HUBADDR_6 0x00002000U /*!<Bit 6 */
+
+#define USB_OTG_HCSPLT_XACTPOS 0x0000C000U /*!< XACTPOS */
+#define USB_OTG_HCSPLT_XACTPOS_0 0x00004000U /*!<Bit 0 */
+#define USB_OTG_HCSPLT_XACTPOS_1 0x00008000U /*!<Bit 1 */
+#define USB_OTG_HCSPLT_COMPLSPLT 0x00010000U /*!< Do complete split */
+#define USB_OTG_HCSPLT_SPLITEN 0x80000000U /*!< Split enable */
+
+/******************** Bit definition forUSB_OTG_HCINT register ********************/
+#define USB_OTG_HCINT_XFRC 0x00000001U /*!< Transfer completed */
+#define USB_OTG_HCINT_CHH 0x00000002U /*!< Channel halted */
+#define USB_OTG_HCINT_AHBERR 0x00000004U /*!< AHB error */
+#define USB_OTG_HCINT_STALL 0x00000008U /*!< STALL response received interrupt */
+#define USB_OTG_HCINT_NAK 0x00000010U /*!< NAK response received interrupt */
+#define USB_OTG_HCINT_ACK 0x00000020U /*!< ACK response received/transmitted interrupt */
+#define USB_OTG_HCINT_NYET 0x00000040U /*!< Response received interrupt */
+#define USB_OTG_HCINT_TXERR 0x00000080U /*!< Transaction error */
+#define USB_OTG_HCINT_BBERR 0x00000100U /*!< Babble error */
+#define USB_OTG_HCINT_FRMOR 0x00000200U /*!< Frame overrun */
+#define USB_OTG_HCINT_DTERR 0x00000400U /*!< Data toggle error */
+
+/******************** Bit definition forUSB_OTG_DIEPINT register ********************/
+#define USB_OTG_DIEPINT_XFRC 0x00000001U /*!< Transfer completed interrupt */
+#define USB_OTG_DIEPINT_EPDISD 0x00000002U /*!< Endpoint disabled interrupt */
+#define USB_OTG_DIEPINT_TOC 0x00000008U /*!< Timeout condition */
+#define USB_OTG_DIEPINT_ITTXFE 0x00000010U /*!< IN token received when TxFIFO is empty */
+#define USB_OTG_DIEPINT_INEPNE 0x00000040U /*!< IN endpoint NAK effective */
+#define USB_OTG_DIEPINT_TXFE 0x00000080U /*!< Transmit FIFO empty */
+#define USB_OTG_DIEPINT_TXFIFOUDRN 0x00000100U /*!< Transmit Fifo Underrun */
+#define USB_OTG_DIEPINT_BNA 0x00000200U /*!< Buffer not available interrupt */
+#define USB_OTG_DIEPINT_PKTDRPSTS 0x00000800U /*!< Packet dropped status */
+#define USB_OTG_DIEPINT_BERR 0x00001000U /*!< Babble error interrupt */
+#define USB_OTG_DIEPINT_NAK 0x00002000U /*!< NAK interrupt */
+
+/******************** Bit definition forUSB_OTG_HCINTMSK register ********************/
+#define USB_OTG_HCINTMSK_XFRCM 0x00000001U /*!< Transfer completed mask */
+#define USB_OTG_HCINTMSK_CHHM 0x00000002U /*!< Channel halted mask */
+#define USB_OTG_HCINTMSK_AHBERR 0x00000004U /*!< AHB error */
+#define USB_OTG_HCINTMSK_STALLM 0x00000008U /*!< STALL response received interrupt mask */
+#define USB_OTG_HCINTMSK_NAKM 0x00000010U /*!< NAK response received interrupt mask */
+#define USB_OTG_HCINTMSK_ACKM 0x00000020U /*!< ACK response received/transmitted interrupt mask */
+#define USB_OTG_HCINTMSK_NYET 0x00000040U /*!< response received interrupt mask */
+#define USB_OTG_HCINTMSK_TXERRM 0x00000080U /*!< Transaction error mask */
+#define USB_OTG_HCINTMSK_BBERRM 0x00000100U /*!< Babble error mask */
+#define USB_OTG_HCINTMSK_FRMORM 0x00000200U /*!< Frame overrun mask */
+#define USB_OTG_HCINTMSK_DTERRM 0x00000400U /*!< Data toggle error mask */
+
+/******************** Bit definition for USB_OTG_DIEPTSIZ register ********************/
+
+#define USB_OTG_DIEPTSIZ_XFRSIZ 0x0007FFFFU /*!< Transfer size */
+#define USB_OTG_DIEPTSIZ_PKTCNT 0x1FF80000U /*!< Packet count */
+#define USB_OTG_DIEPTSIZ_MULCNT 0x60000000U /*!< Packet count */
+/******************** Bit definition forUSB_OTG_HCTSIZ register ********************/
+#define USB_OTG_HCTSIZ_XFRSIZ 0x0007FFFFU /*!< Transfer size */
+#define USB_OTG_HCTSIZ_PKTCNT 0x1FF80000U /*!< Packet count */
+#define USB_OTG_HCTSIZ_DOPING 0x80000000U /*!< Do PING */
+#define USB_OTG_HCTSIZ_DPID 0x60000000U /*!< Data PID */
+#define USB_OTG_HCTSIZ_DPID_0 0x20000000U /*!<Bit 0 */
+#define USB_OTG_HCTSIZ_DPID_1 0x40000000U /*!<Bit 1 */
+
+/******************** Bit definition forUSB_OTG_DIEPDMA register ********************/
+#define USB_OTG_DIEPDMA_DMAADDR 0xFFFFFFFFU /*!< DMA address */
+
+/******************** Bit definition forUSB_OTG_HCDMA register ********************/
+#define USB_OTG_HCDMA_DMAADDR 0xFFFFFFFFU /*!< DMA address */
+
+/******************** Bit definition forUSB_OTG_DTXFSTS register ********************/
+#define USB_OTG_DTXFSTS_INEPTFSAV 0x0000FFFFU /*!< IN endpoint TxFIFO space avail */
+
+/******************** Bit definition forUSB_OTG_DIEPTXF register ********************/
+#define USB_OTG_DIEPTXF_INEPTXSA 0x0000FFFFU /*!< IN endpoint FIFOx transmit RAM start address */
+#define USB_OTG_DIEPTXF_INEPTXFD 0xFFFF0000U /*!< IN endpoint TxFIFO depth */
+
+/******************** Bit definition forUSB_OTG_DOEPCTL register ********************/
+
+#define USB_OTG_DOEPCTL_MPSIZ 0x000007FFU /*!< Maximum packet size */ /*!<Bit 1 */
+#define USB_OTG_DOEPCTL_USBAEP 0x00008000U /*!< USB active endpoint */
+#define USB_OTG_DOEPCTL_NAKSTS 0x00020000U /*!< NAK status */
+#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM 0x10000000U /*!< Set DATA0 PID */
+#define USB_OTG_DOEPCTL_SODDFRM 0x20000000U /*!< Set odd frame */
+#define USB_OTG_DOEPCTL_EPTYP 0x000C0000U /*!< Endpoint type */
+#define USB_OTG_DOEPCTL_EPTYP_0 0x00040000U /*!<Bit 0 */
+#define USB_OTG_DOEPCTL_EPTYP_1 0x00080000U /*!<Bit 1 */
+#define USB_OTG_DOEPCTL_SNPM 0x00100000U /*!< Snoop mode */
+#define USB_OTG_DOEPCTL_STALL 0x00200000U /*!< STALL handshake */
+#define USB_OTG_DOEPCTL_CNAK 0x04000000U /*!< Clear NAK */
+#define USB_OTG_DOEPCTL_SNAK 0x08000000U /*!< Set NAK */
+#define USB_OTG_DOEPCTL_EPDIS 0x40000000U /*!< Endpoint disable */
+#define USB_OTG_DOEPCTL_EPENA 0x80000000U /*!< Endpoint enable */
+
+/******************** Bit definition forUSB_OTG_DOEPINT register ********************/
+#define USB_OTG_DOEPINT_XFRC 0x00000001U /*!< Transfer completed interrupt */
+#define USB_OTG_DOEPINT_EPDISD 0x00000002U /*!< Endpoint disabled interrupt */
+#define USB_OTG_DOEPINT_STUP 0x00000008U /*!< SETUP phase done */
+#define USB_OTG_DOEPINT_OTEPDIS 0x00000010U /*!< OUT token received when endpoint disabled */
+#define USB_OTG_DOEPINT_B2BSTUP 0x00000040U /*!< Back-to-back SETUP packets received */
+#define USB_OTG_DOEPINT_NYET 0x00004000U /*!< NYET interrupt */
+
+/******************** Bit definition forUSB_OTG_DOEPTSIZ register ********************/
+
+#define USB_OTG_DOEPTSIZ_XFRSIZ 0x0007FFFFU /*!< Transfer size */
+#define USB_OTG_DOEPTSIZ_PKTCNT 0x1FF80000U /*!< Packet count */
+
+#define USB_OTG_DOEPTSIZ_STUPCNT 0x60000000U /*!< SETUP packet count */
+#define USB_OTG_DOEPTSIZ_STUPCNT_0 0x20000000U /*!<Bit 0 */
+#define USB_OTG_DOEPTSIZ_STUPCNT_1 0x40000000U /*!<Bit 1 */
+
+/******************** Bit definition for PCGCCTL register ********************/
+#define USB_OTG_PCGCCTL_STOPCLK 0x00000001U /*!< SETUP packet count */
+#define USB_OTG_PCGCCTL_GATECLK 0x00000002U /*!<Bit 0 */
+#define USB_OTG_PCGCCTL_PHYSUSP 0x00000010U /*!<Bit 1 */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup Exported_macros
+ * @{
+ */
+
+/******************************* ADC Instances ********************************/
+#define IS_ADC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
+
+/******************************* CRC Instances ********************************/
+#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
+
+/******************************** DMA Instances *******************************/
+#define IS_DMA_STREAM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0) || \
+ ((INSTANCE) == DMA1_Stream1) || \
+ ((INSTANCE) == DMA1_Stream2) || \
+ ((INSTANCE) == DMA1_Stream3) || \
+ ((INSTANCE) == DMA1_Stream4) || \
+ ((INSTANCE) == DMA1_Stream5) || \
+ ((INSTANCE) == DMA1_Stream6) || \
+ ((INSTANCE) == DMA1_Stream7) || \
+ ((INSTANCE) == DMA2_Stream0) || \
+ ((INSTANCE) == DMA2_Stream1) || \
+ ((INSTANCE) == DMA2_Stream2) || \
+ ((INSTANCE) == DMA2_Stream3) || \
+ ((INSTANCE) == DMA2_Stream4) || \
+ ((INSTANCE) == DMA2_Stream5) || \
+ ((INSTANCE) == DMA2_Stream6) || \
+ ((INSTANCE) == DMA2_Stream7))
+
+/******************************* GPIO Instances *******************************/
+#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
+ ((INSTANCE) == GPIOB) || \
+ ((INSTANCE) == GPIOC) || \
+ ((INSTANCE) == GPIOD) || \
+ ((INSTANCE) == GPIOE) || \
+ ((INSTANCE) == GPIOH))
+
+/******************************** I2C Instances *******************************/
+#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
+ ((INSTANCE) == I2C2) || \
+ ((INSTANCE) == I2C3))
+
+/******************************** I2S Instances *******************************/
+#define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI2) || \
+ ((INSTANCE) == SPI3))
+
+/*************************** I2S Extended Instances ***************************/
+#define IS_I2S_ALL_INSTANCE_EXT(PERIPH) (((INSTANCE) == SPI2) || \
+ ((INSTANCE) == SPI3) || \
+ ((INSTANCE) == I2S2ext) || \
+ ((INSTANCE) == I2S3ext))
+
+/****************************** RTC Instances *********************************/
+#define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
+
+/******************************** SPI Instances *******************************/
+#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
+ ((INSTANCE) == SPI2) || \
+ ((INSTANCE) == SPI3) || \
+ ((INSTANCE) == SPI4))
+
+/*************************** SPI Extended Instances ***************************/
+#define IS_SPI_ALL_INSTANCE_EXT(INSTANCE) (((INSTANCE) == SPI1) || \
+ ((INSTANCE) == SPI2) || \
+ ((INSTANCE) == SPI3) || \
+ ((INSTANCE) == I2S2ext) || \
+ ((INSTANCE) == I2S3ext))
+
+/****************** TIM Instances : All supported instances *******************/
+#define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM9) || \
+ ((INSTANCE) == TIM10) || \
+ ((INSTANCE) == TIM11))
+
+/************* TIM Instances : at least 1 capture/compare channel *************/
+#define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM9) || \
+ ((INSTANCE) == TIM10) || \
+ ((INSTANCE) == TIM11))
+
+/************ TIM Instances : at least 2 capture/compare channels *************/
+#define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM9))
+
+/************ TIM Instances : at least 3 capture/compare channels *************/
+#define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5))
+
+/************ TIM Instances : at least 4 capture/compare channels *************/
+#define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5))
+
+/******************** TIM Instances : Advanced-control timers *****************/
+#define IS_TIM_ADVANCED_INSTANCE(INSTANCE) ((INSTANCE) == TIM1)
+
+/******************* TIM Instances : Timer input XOR function *****************/
+#define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5))
+
+/****************** TIM Instances : DMA requests generation (UDE) *************/
+#define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5))
+
+/************ TIM Instances : DMA requests generation (CCxDE) *****************/
+#define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5))
+
+/************ TIM Instances : DMA requests generation (COMDE) *****************/
+#define IS_TIM_CCDMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5))
+
+/******************** TIM Instances : DMA burst feature ***********************/
+#define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5))
+
+/****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/
+#define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM9))
+
+/*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
+#define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM9))
+
+/********************** TIM Instances : 32 bit Counter ************************/
+#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)(((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM5))
+
+/***************** TIM Instances : external trigger input availabe ************/
+#define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5))
+
+/****************** TIM Instances : remapping capability **********************/
+#define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM11))
+
+/******************* TIM Instances : output(s) available **********************/
+#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
+ ((((INSTANCE) == TIM1) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM2) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM3) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM4) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM5) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM9) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2))) \
+ || \
+ (((INSTANCE) == TIM10) && \
+ (((CHANNEL) == TIM_CHANNEL_1))) \
+ || \
+ (((INSTANCE) == TIM11) && \
+ (((CHANNEL) == TIM_CHANNEL_1))))
+
+/************ TIM Instances : complementary output(s) available ***************/
+#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
+ ((((INSTANCE) == TIM1) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3))))
+
+/******************** USART Instances : Synchronous mode **********************/
+#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART6))
+
+/******************** UART Instances : Asynchronous mode **********************/
+#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART6))
+
+/****************** UART Instances : Hardware Flow control ********************/
+#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART6))
+
+/********************* UART Instances : Smard card mode ***********************/
+#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART6))
+
+/*********************** UART Instances : IRDA mode ***************************/
+#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART6))
+
+/*********************** PCD Instances ****************************************/
+#define IS_PCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS))
+
+/*********************** HCD Instances ****************************************/
+#define IS_HCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS))
+
+/****************************** IWDG Instances ********************************/
+#define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
+
+/****************************** WWDG Instances ********************************/
+#define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
+
+/****************************** SDIO Instances ********************************/
+#define IS_SDIO_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SDIO)
+
+/****************************** USB Exported Constants ************************/
+#define USB_OTG_FS_HOST_MAX_CHANNEL_NBR 8U
+#define USB_OTG_FS_MAX_IN_ENDPOINTS 4U /* Including EP0 */
+#define USB_OTG_FS_MAX_OUT_ENDPOINTS 4U /* Including EP0 */
+#define USB_OTG_FS_TOTAL_FIFO_SIZE 1280U /* in Bytes */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* __STM32F401xC_H */
+
+
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Device/ST/STM32F4xx/Include/stm32f401xe.h b/Device/ST/STM32F4xx/Include/stm32f401xe.h
new file mode 100644
index 0000000..a57b388
--- /dev/null
+++ b/Device/ST/STM32F4xx/Include/stm32f401xe.h
@@ -0,0 +1,4805 @@
+/**
+ ******************************************************************************
+ * @file stm32f401xe.h
+ * @author MCD Application Team
+ * @version V2.5.0
+ * @date 22-April-2016
+ * @brief CMSIS STM32F401xExx Device Peripheral Access Layer Header File.
+ *
+ * This file contains:
+ * - Data structures and the address mapping for all peripherals
+ * - peripherals registers declarations and bits definition
+ * - Macros to access peripheral’s registers hardware
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/** @addtogroup CMSIS
+ * @{
+ */
+
+/** @addtogroup stm32f401xe
+ * @{
+ */
+
+#ifndef __STM32F401xE_H
+#define __STM32F401xE_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif /* __cplusplus */
+
+
+/** @addtogroup Configuration_section_for_CMSIS
+ * @{
+ */
+
+/**
+ * @brief Configuration of the Cortex-M4 Processor and Core Peripherals
+ */
+#define __CM4_REV 0x0001U /*!< Core revision r0p1 */
+#define __MPU_PRESENT 1U /*!< STM32F4XX provides an MPU */
+#define __NVIC_PRIO_BITS 4U /*!< STM32F4XX uses 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */
+#define __FPU_PRESENT 1U /*!< FPU present */
+
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_interrupt_number_definition
+ * @{
+ */
+
+/**
+ * @brief STM32F4XX Interrupt Number Definition, according to the selected device
+ * in @ref Library_configuration_section
+ */
+typedef enum
+{
+/****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/
+ NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
+ MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */
+ BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */
+ UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */
+ SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */
+ DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */
+ PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */
+ SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */
+/****** STM32 specific Interrupt Numbers **********************************************************************/
+ WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
+ PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */
+ TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */
+ RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */
+ FLASH_IRQn = 4, /*!< FLASH global Interrupt */
+ RCC_IRQn = 5, /*!< RCC global Interrupt */
+ EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */
+ EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */
+ EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */
+ EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */
+ EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */
+ DMA1_Stream0_IRQn = 11, /*!< DMA1 Stream 0 global Interrupt */
+ DMA1_Stream1_IRQn = 12, /*!< DMA1 Stream 1 global Interrupt */
+ DMA1_Stream2_IRQn = 13, /*!< DMA1 Stream 2 global Interrupt */
+ DMA1_Stream3_IRQn = 14, /*!< DMA1 Stream 3 global Interrupt */
+ DMA1_Stream4_IRQn = 15, /*!< DMA1 Stream 4 global Interrupt */
+ DMA1_Stream5_IRQn = 16, /*!< DMA1 Stream 5 global Interrupt */
+ DMA1_Stream6_IRQn = 17, /*!< DMA1 Stream 6 global Interrupt */
+ ADC_IRQn = 18, /*!< ADC1, ADC2 and ADC3 global Interrupts */
+ EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
+ TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break interrupt and TIM9 global interrupt */
+ TIM1_UP_TIM10_IRQn = 25, /*!< TIM1 Update Interrupt and TIM10 global interrupt */
+ TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */
+ TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
+ TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
+ TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
+ TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
+ I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
+ I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
+ I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
+ I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
+ SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
+ SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
+ USART1_IRQn = 37, /*!< USART1 global Interrupt */
+ USART2_IRQn = 38, /*!< USART2 global Interrupt */
+ EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
+ RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */
+ OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS Wakeup through EXTI line interrupt */
+ DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */
+ SDIO_IRQn = 49, /*!< SDIO global Interrupt */
+ TIM5_IRQn = 50, /*!< TIM5 global Interrupt */
+ SPI3_IRQn = 51, /*!< SPI3 global Interrupt */
+ DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */
+ DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */
+ DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */
+ DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */
+ DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */
+ OTG_FS_IRQn = 67, /*!< USB OTG FS global Interrupt */
+ DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */
+ DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */
+ DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */
+ USART6_IRQn = 71, /*!< USART6 global interrupt */
+ I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */
+ I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */
+ FPU_IRQn = 81, /*!< FPU global interrupt */
+ SPI4_IRQn = 84 /*!< SPI4 global Interrupt */
+} IRQn_Type;
+
+/**
+ * @}
+ */
+
+#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
+#include "system_stm32f4xx.h"
+#include <stdint.h>
+
+/** @addtogroup Peripheral_registers_structures
+ * @{
+ */
+
+/**
+ * @brief Analog to Digital Converter
+ */
+
+typedef struct
+{
+ __IO uint32_t SR; /*!< ADC status register, Address offset: 0x00 */
+ __IO uint32_t CR1; /*!< ADC control register 1, Address offset: 0x04 */
+ __IO uint32_t CR2; /*!< ADC control register 2, Address offset: 0x08 */
+ __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x0C */
+ __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x10 */
+ __IO uint32_t JOFR1; /*!< ADC injected channel data offset register 1, Address offset: 0x14 */
+ __IO uint32_t JOFR2; /*!< ADC injected channel data offset register 2, Address offset: 0x18 */
+ __IO uint32_t JOFR3; /*!< ADC injected channel data offset register 3, Address offset: 0x1C */
+ __IO uint32_t JOFR4; /*!< ADC injected channel data offset register 4, Address offset: 0x20 */
+ __IO uint32_t HTR; /*!< ADC watchdog higher threshold register, Address offset: 0x24 */
+ __IO uint32_t LTR; /*!< ADC watchdog lower threshold register, Address offset: 0x28 */
+ __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x2C */
+ __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x30 */
+ __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x34 */
+ __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x38*/
+ __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x3C */
+ __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x40 */
+ __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x44 */
+ __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x48 */
+ __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x4C */
+} ADC_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1 base address + 0x300 */
+ __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1 base address + 0x304 */
+ __IO uint32_t CDR; /*!< ADC common regular data register for dual
+ AND triple modes, Address offset: ADC1 base address + 0x308 */
+} ADC_Common_TypeDef;
+
+/**
+ * @brief CRC calculation unit
+ */
+
+typedef struct
+{
+ __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
+ __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
+ uint8_t RESERVED0; /*!< Reserved, 0x05 */
+ uint16_t RESERVED1; /*!< Reserved, 0x06 */
+ __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
+} CRC_TypeDef;
+
+/**
+ * @brief Debug MCU
+ */
+
+typedef struct
+{
+ __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
+ __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
+ __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */
+ __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */
+}DBGMCU_TypeDef;
+
+
+/**
+ * @brief DMA Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< DMA stream x configuration register */
+ __IO uint32_t NDTR; /*!< DMA stream x number of data register */
+ __IO uint32_t PAR; /*!< DMA stream x peripheral address register */
+ __IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */
+ __IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */
+ __IO uint32_t FCR; /*!< DMA stream x FIFO control register */
+} DMA_Stream_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t LISR; /*!< DMA low interrupt status register, Address offset: 0x00 */
+ __IO uint32_t HISR; /*!< DMA high interrupt status register, Address offset: 0x04 */
+ __IO uint32_t LIFCR; /*!< DMA low interrupt flag clear register, Address offset: 0x08 */
+ __IO uint32_t HIFCR; /*!< DMA high interrupt flag clear register, Address offset: 0x0C */
+} DMA_TypeDef;
+
+
+/**
+ * @brief External Interrupt/Event Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t IMR; /*!< EXTI Interrupt mask register, Address offset: 0x00 */
+ __IO uint32_t EMR; /*!< EXTI Event mask register, Address offset: 0x04 */
+ __IO uint32_t RTSR; /*!< EXTI Rising trigger selection register, Address offset: 0x08 */
+ __IO uint32_t FTSR; /*!< EXTI Falling trigger selection register, Address offset: 0x0C */
+ __IO uint32_t SWIER; /*!< EXTI Software interrupt event register, Address offset: 0x10 */
+ __IO uint32_t PR; /*!< EXTI Pending register, Address offset: 0x14 */
+} EXTI_TypeDef;
+
+/**
+ * @brief FLASH Registers
+ */
+
+typedef struct
+{
+ __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */
+ __IO uint32_t KEYR; /*!< FLASH key register, Address offset: 0x04 */
+ __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x08 */
+ __IO uint32_t SR; /*!< FLASH status register, Address offset: 0x0C */
+ __IO uint32_t CR; /*!< FLASH control register, Address offset: 0x10 */
+ __IO uint32_t OPTCR; /*!< FLASH option control register , Address offset: 0x14 */
+ __IO uint32_t OPTCR1; /*!< FLASH option control register 1, Address offset: 0x18 */
+} FLASH_TypeDef;
+
+/**
+ * @brief General Purpose I/O
+ */
+
+typedef struct
+{
+ __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
+ __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */
+ __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */
+ __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
+ __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
+ __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
+ __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */
+ __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
+ __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */
+} GPIO_TypeDef;
+
+/**
+ * @brief System configuration controller
+ */
+
+typedef struct
+{
+ __IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */
+ __IO uint32_t PMC; /*!< SYSCFG peripheral mode configuration register, Address offset: 0x04 */
+ __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
+ uint32_t RESERVED[2]; /*!< Reserved, 0x18-0x1C */
+ __IO uint32_t CMPCR; /*!< SYSCFG Compensation cell control register, Address offset: 0x20 */
+} SYSCFG_TypeDef;
+
+/**
+ * @brief Inter-integrated Circuit Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */
+ __IO uint32_t OAR1; /*!< I2C Own address register 1, Address offset: 0x08 */
+ __IO uint32_t OAR2; /*!< I2C Own address register 2, Address offset: 0x0C */
+ __IO uint32_t DR; /*!< I2C Data register, Address offset: 0x10 */
+ __IO uint32_t SR1; /*!< I2C Status register 1, Address offset: 0x14 */
+ __IO uint32_t SR2; /*!< I2C Status register 2, Address offset: 0x18 */
+ __IO uint32_t CCR; /*!< I2C Clock control register, Address offset: 0x1C */
+ __IO uint32_t TRISE; /*!< I2C TRISE register, Address offset: 0x20 */
+ __IO uint32_t FLTR; /*!< I2C FLTR register, Address offset: 0x24 */
+} I2C_TypeDef;
+
+/**
+ * @brief Independent WATCHDOG
+ */
+
+typedef struct
+{
+ __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */
+ __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */
+ __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */
+ __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */
+} IWDG_TypeDef;
+
+/**
+ * @brief Power Control
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */
+ __IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */
+} PWR_TypeDef;
+
+/**
+ * @brief Reset and Clock Control
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */
+ __IO uint32_t PLLCFGR; /*!< RCC PLL configuration register, Address offset: 0x04 */
+ __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x08 */
+ __IO uint32_t CIR; /*!< RCC clock interrupt register, Address offset: 0x0C */
+ __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x10 */
+ __IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x14 */
+ __IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0x18 */
+ uint32_t RESERVED0; /*!< Reserved, 0x1C */
+ __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x20 */
+ __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x24 */
+ uint32_t RESERVED1[2]; /*!< Reserved, 0x28-0x2C */
+ __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clock register, Address offset: 0x30 */
+ __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clock register, Address offset: 0x34 */
+ __IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clock register, Address offset: 0x38 */
+ uint32_t RESERVED2; /*!< Reserved, 0x3C */
+ __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x40 */
+ __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x44 */
+ uint32_t RESERVED3[2]; /*!< Reserved, 0x48-0x4C */
+ __IO uint32_t AHB1LPENR; /*!< RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 */
+ __IO uint32_t AHB2LPENR; /*!< RCC AHB2 peripheral clock enable in low power mode register, Address offset: 0x54 */
+ __IO uint32_t AHB3LPENR; /*!< RCC AHB3 peripheral clock enable in low power mode register, Address offset: 0x58 */
+ uint32_t RESERVED4; /*!< Reserved, 0x5C */
+ __IO uint32_t APB1LPENR; /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 */
+ __IO uint32_t APB2LPENR; /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 */
+ uint32_t RESERVED5[2]; /*!< Reserved, 0x68-0x6C */
+ __IO uint32_t BDCR; /*!< RCC Backup domain control register, Address offset: 0x70 */
+ __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x74 */
+ uint32_t RESERVED6[2]; /*!< Reserved, 0x78-0x7C */
+ __IO uint32_t SSCGR; /*!< RCC spread spectrum clock generation register, Address offset: 0x80 */
+ __IO uint32_t PLLI2SCFGR; /*!< RCC PLLI2S configuration register, Address offset: 0x84 */
+ uint32_t RESERVED7[1]; /*!< Reserved, 0x88 */
+ __IO uint32_t DCKCFGR; /*!< RCC DCKCFGR configuration register, Address offset: 0x8C */
+} RCC_TypeDef;
+
+/**
+ * @brief Real-Time Clock
+ */
+
+typedef struct
+{
+ __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
+ __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */
+ __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */
+ __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */
+ __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */
+ __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */
+ __IO uint32_t CALIBR; /*!< RTC calibration register, Address offset: 0x18 */
+ __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */
+ __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */
+ __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */
+ __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */
+ __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */
+ __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */
+ __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */
+ __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */
+ __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */
+ __IO uint32_t TAFCR; /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */
+ __IO uint32_t ALRMASSR;/*!< RTC alarm A sub second register, Address offset: 0x44 */
+ __IO uint32_t ALRMBSSR;/*!< RTC alarm B sub second register, Address offset: 0x48 */
+ uint32_t RESERVED7; /*!< Reserved, 0x4C */
+ __IO uint32_t BKP0R; /*!< RTC backup register 1, Address offset: 0x50 */
+ __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */
+ __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */
+ __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */
+ __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */
+ __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */
+ __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */
+ __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */
+ __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */
+ __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */
+ __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */
+ __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */
+ __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */
+ __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */
+ __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */
+ __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */
+ __IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */
+ __IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */
+ __IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */
+ __IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */
+} RTC_TypeDef;
+
+
+/**
+ * @brief SD host Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t POWER; /*!< SDIO power control register, Address offset: 0x00 */
+ __IO uint32_t CLKCR; /*!< SDI clock control register, Address offset: 0x04 */
+ __IO uint32_t ARG; /*!< SDIO argument register, Address offset: 0x08 */
+ __IO uint32_t CMD; /*!< SDIO command register, Address offset: 0x0C */
+ __I uint32_t RESPCMD; /*!< SDIO command response register, Address offset: 0x10 */
+ __I uint32_t RESP1; /*!< SDIO response 1 register, Address offset: 0x14 */
+ __I uint32_t RESP2; /*!< SDIO response 2 register, Address offset: 0x18 */
+ __I uint32_t RESP3; /*!< SDIO response 3 register, Address offset: 0x1C */
+ __I uint32_t RESP4; /*!< SDIO response 4 register, Address offset: 0x20 */
+ __IO uint32_t DTIMER; /*!< SDIO data timer register, Address offset: 0x24 */
+ __IO uint32_t DLEN; /*!< SDIO data length register, Address offset: 0x28 */
+ __IO uint32_t DCTRL; /*!< SDIO data control register, Address offset: 0x2C */
+ __I uint32_t DCOUNT; /*!< SDIO data counter register, Address offset: 0x30 */
+ __I uint32_t STA; /*!< SDIO status register, Address offset: 0x34 */
+ __IO uint32_t ICR; /*!< SDIO interrupt clear register, Address offset: 0x38 */
+ __IO uint32_t MASK; /*!< SDIO mask register, Address offset: 0x3C */
+ uint32_t RESERVED0[2]; /*!< Reserved, 0x40-0x44 */
+ __I uint32_t FIFOCNT; /*!< SDIO FIFO counter register, Address offset: 0x48 */
+ uint32_t RESERVED1[13]; /*!< Reserved, 0x4C-0x7C */
+ __IO uint32_t FIFO; /*!< SDIO data FIFO register, Address offset: 0x80 */
+} SDIO_TypeDef;
+
+/**
+ * @brief Serial Peripheral Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t CR1; /*!< SPI control register 1 (not used in I2S mode), Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< SPI control register 2, Address offset: 0x04 */
+ __IO uint32_t SR; /*!< SPI status register, Address offset: 0x08 */
+ __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */
+ __IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
+ __IO uint32_t RXCRCR; /*!< SPI RX CRC register (not used in I2S mode), Address offset: 0x14 */
+ __IO uint32_t TXCRCR; /*!< SPI TX CRC register (not used in I2S mode), Address offset: 0x18 */
+ __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */
+ __IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */
+} SPI_TypeDef;
+
+/**
+ * @brief TIM
+ */
+
+typedef struct
+{
+ __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
+ __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */
+ __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
+ __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
+ __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
+ __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
+ __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
+ __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
+ __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
+ __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */
+ __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
+ __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */
+ __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
+ __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
+ __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
+ __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
+ __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
+ __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
+ __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */
+ __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */
+} TIM_TypeDef;
+
+/**
+ * @brief Universal Synchronous Asynchronous Receiver Transmitter
+ */
+
+typedef struct
+{
+ __IO uint32_t SR; /*!< USART Status register, Address offset: 0x00 */
+ __IO uint32_t DR; /*!< USART Data register, Address offset: 0x04 */
+ __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x08 */
+ __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x0C */
+ __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x10 */
+ __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x14 */
+ __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x18 */
+} USART_TypeDef;
+
+/**
+ * @brief Window WATCHDOG
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
+ __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
+ __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
+} WWDG_TypeDef;
+
+/**
+ * @brief __USB_OTG_Core_register
+ */
+typedef struct
+{
+ __IO uint32_t GOTGCTL; /*!< USB_OTG Control and Status Register Address offset : 0x00 */
+ __IO uint32_t GOTGINT; /*!< USB_OTG Interrupt Register Address offset : 0x04 */
+ __IO uint32_t GAHBCFG; /*!< Core AHB Configuration Register Address offset : 0x08 */
+ __IO uint32_t GUSBCFG; /*!< Core USB Configuration Register Address offset : 0x0C */
+ __IO uint32_t GRSTCTL; /*!< Core Reset Register Address offset : 0x10 */
+ __IO uint32_t GINTSTS; /*!< Core Interrupt Register Address offset : 0x14 */
+ __IO uint32_t GINTMSK; /*!< Core Interrupt Mask Register Address offset : 0x18 */
+ __IO uint32_t GRXSTSR; /*!< Receive Sts Q Read Register Address offset : 0x1C */
+ __IO uint32_t GRXSTSP; /*!< Receive Sts Q Read & POP Register Address offset : 0x20 */
+ __IO uint32_t GRXFSIZ; /* Receive FIFO Size Register Address offset : 0x24 */
+ __IO uint32_t DIEPTXF0_HNPTXFSIZ; /*!< EP0 / Non Periodic Tx FIFO Size Register Address offset : 0x28 */
+ __IO uint32_t HNPTXSTS; /*!< Non Periodic Tx FIFO/Queue Sts reg Address offset : 0x2C */
+ uint32_t Reserved30[2]; /* Reserved Address offset : 0x30 */
+ __IO uint32_t GCCFG; /*!< General Purpose IO Register Address offset : 0x38 */
+ __IO uint32_t CID; /*!< User ID Register Address offset : 0x3C */
+ uint32_t Reserved40[48]; /*!< Reserved Address offset : 0x40-0xFF */
+ __IO uint32_t HPTXFSIZ; /*!< Host Periodic Tx FIFO Size Reg Address offset : 0x100 */
+ __IO uint32_t DIEPTXF[0x0F]; /*!< dev Periodic Transmit FIFO */
+}
+USB_OTG_GlobalTypeDef;
+
+
+
+/**
+ * @brief __device_Registers
+ */
+typedef struct
+{
+ __IO uint32_t DCFG; /*!< dev Configuration Register Address offset : 0x800 */
+ __IO uint32_t DCTL; /*!< dev Control Register Address offset : 0x804 */
+ __IO uint32_t DSTS; /*!< dev Status Register (RO) Address offset : 0x808 */
+ uint32_t Reserved0C; /*!< Reserved Address offset : 0x80C */
+ __IO uint32_t DIEPMSK; /* !< dev IN Endpoint Mask Address offset : 0x810 */
+ __IO uint32_t DOEPMSK; /*!< dev OUT Endpoint Mask Address offset : 0x814 */
+ __IO uint32_t DAINT; /*!< dev All Endpoints Itr Reg Address offset : 0x818 */
+ __IO uint32_t DAINTMSK; /*!< dev All Endpoints Itr Mask Address offset : 0x81C */
+ uint32_t Reserved20; /*!< Reserved Address offset : 0x820 */
+ uint32_t Reserved9; /*!< Reserved Address offset : 0x824 */
+ __IO uint32_t DVBUSDIS; /*!< dev VBUS discharge Register Address offset : 0x828 */
+ __IO uint32_t DVBUSPULSE; /*!< dev VBUS Pulse Register Address offset : 0x82C */
+ __IO uint32_t DTHRCTL; /*!< dev thr Address offset : 0x830 */
+ __IO uint32_t DIEPEMPMSK; /*!< dev empty msk Address offset : 0x834 */
+ __IO uint32_t DEACHINT; /*!< dedicated EP interrupt Address offset : 0x838 */
+ __IO uint32_t DEACHMSK; /*!< dedicated EP msk Address offset : 0x83C */
+ uint32_t Reserved40; /*!< dedicated EP mask Address offset : 0x840 */
+ __IO uint32_t DINEP1MSK; /*!< dedicated EP mask Address offset : 0x844 */
+ uint32_t Reserved44[15]; /*!< Reserved Address offset : 0x844-0x87C */
+ __IO uint32_t DOUTEP1MSK; /*!< dedicated EP msk Address offset : 0x884 */
+}
+USB_OTG_DeviceTypeDef;
+
+
+/**
+ * @brief __IN_Endpoint-Specific_Register
+ */
+typedef struct
+{
+ __IO uint32_t DIEPCTL; /* dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h */
+ uint32_t Reserved04; /* Reserved 900h + (ep_num * 20h) + 04h */
+ __IO uint32_t DIEPINT; /* dev IN Endpoint Itr Reg 900h + (ep_num * 20h) + 08h */
+ uint32_t Reserved0C; /* Reserved 900h + (ep_num * 20h) + 0Ch */
+ __IO uint32_t DIEPTSIZ; /* IN Endpoint Txfer Size 900h + (ep_num * 20h) + 10h */
+ __IO uint32_t DIEPDMA; /* IN Endpoint DMA Address Reg 900h + (ep_num * 20h) + 14h */
+ __IO uint32_t DTXFSTS; /*IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h */
+ uint32_t Reserved18; /* Reserved 900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch */
+}
+USB_OTG_INEndpointTypeDef;
+
+
+/**
+ * @brief __OUT_Endpoint-Specific_Registers
+ */
+typedef struct
+{
+ __IO uint32_t DOEPCTL; /* dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h*/
+ uint32_t Reserved04; /* Reserved B00h + (ep_num * 20h) + 04h*/
+ __IO uint32_t DOEPINT; /* dev OUT Endpoint Itr Reg B00h + (ep_num * 20h) + 08h*/
+ uint32_t Reserved0C; /* Reserved B00h + (ep_num * 20h) + 0Ch*/
+ __IO uint32_t DOEPTSIZ; /* dev OUT Endpoint Txfer Size B00h + (ep_num * 20h) + 10h*/
+ __IO uint32_t DOEPDMA; /* dev OUT Endpoint DMA Address B00h + (ep_num * 20h) + 14h*/
+ uint32_t Reserved18[2]; /* Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch*/
+}
+USB_OTG_OUTEndpointTypeDef;
+
+
+/**
+ * @brief __Host_Mode_Register_Structures
+ */
+typedef struct
+{
+ __IO uint32_t HCFG; /* Host Configuration Register 400h*/
+ __IO uint32_t HFIR; /* Host Frame Interval Register 404h*/
+ __IO uint32_t HFNUM; /* Host Frame Nbr/Frame Remaining 408h*/
+ uint32_t Reserved40C; /* Reserved 40Ch*/
+ __IO uint32_t HPTXSTS; /* Host Periodic Tx FIFO/ Queue Status 410h*/
+ __IO uint32_t HAINT; /* Host All Channels Interrupt Register 414h*/
+ __IO uint32_t HAINTMSK; /* Host All Channels Interrupt Mask 418h*/
+}
+USB_OTG_HostTypeDef;
+
+
+/**
+ * @brief __Host_Channel_Specific_Registers
+ */
+typedef struct
+{
+ __IO uint32_t HCCHAR;
+ __IO uint32_t HCSPLT;
+ __IO uint32_t HCINT;
+ __IO uint32_t HCINTMSK;
+ __IO uint32_t HCTSIZ;
+ __IO uint32_t HCDMA;
+ uint32_t Reserved[2];
+}
+USB_OTG_HostChannelTypeDef;
+
+/**
+ * @brief Peripheral_memory_map
+ */
+#define FLASH_BASE 0x08000000U /*!< FLASH(up to 1 MB) base address in the alias region */
+#define SRAM1_BASE 0x20000000U /*!< SRAM1(96 KB) base address in the alias region */
+#define PERIPH_BASE 0x40000000U /*!< Peripheral base address in the alias region */
+#define BKPSRAM_BASE 0x40024000U /*!< Backup SRAM(4 KB) base address in the alias region */
+#define SRAM1_BB_BASE 0x22000000U /*!< SRAM1(96 KB) base address in the bit-band region */
+#define PERIPH_BB_BASE 0x42000000U /*!< Peripheral base address in the bit-band region */
+#define BKPSRAM_BB_BASE 0x42480000U /*!< Backup SRAM(4 KB) base address in the bit-band region */
+#define FLASH_END 0x0807FFFFU /*!< FLASH end address */
+
+/* Legacy defines */
+#define SRAM_BASE SRAM1_BASE
+#define SRAM_BB_BASE SRAM1_BB_BASE
+
+
+/*!< Peripheral memory map */
+#define APB1PERIPH_BASE PERIPH_BASE
+#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000U)
+#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000U)
+#define AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000U)
+
+/*!< APB1 peripherals */
+#define TIM2_BASE (APB1PERIPH_BASE + 0x0000U)
+#define TIM3_BASE (APB1PERIPH_BASE + 0x0400U)
+#define TIM4_BASE (APB1PERIPH_BASE + 0x0800U)
+#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00U)
+#define RTC_BASE (APB1PERIPH_BASE + 0x2800U)
+#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00U)
+#define IWDG_BASE (APB1PERIPH_BASE + 0x3000U)
+#define I2S2ext_BASE (APB1PERIPH_BASE + 0x3400U)
+#define SPI2_BASE (APB1PERIPH_BASE + 0x3800U)
+#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00U)
+#define I2S3ext_BASE (APB1PERIPH_BASE + 0x4000U)
+#define USART2_BASE (APB1PERIPH_BASE + 0x4400U)
+#define I2C1_BASE (APB1PERIPH_BASE + 0x5400U)
+#define I2C2_BASE (APB1PERIPH_BASE + 0x5800U)
+#define I2C3_BASE (APB1PERIPH_BASE + 0x5C00U)
+#define PWR_BASE (APB1PERIPH_BASE + 0x7000U)
+
+/*!< APB2 peripherals */
+#define TIM1_BASE (APB2PERIPH_BASE + 0x0000U)
+#define USART1_BASE (APB2PERIPH_BASE + 0x1000U)
+#define USART6_BASE (APB2PERIPH_BASE + 0x1400U)
+#define ADC1_BASE (APB2PERIPH_BASE + 0x2000U)
+#define ADC_BASE (APB2PERIPH_BASE + 0x2300U)
+#define SDIO_BASE (APB2PERIPH_BASE + 0x2C00U)
+#define SPI1_BASE (APB2PERIPH_BASE + 0x3000U)
+#define SPI4_BASE (APB2PERIPH_BASE + 0x3400U)
+#define SYSCFG_BASE (APB2PERIPH_BASE + 0x3800U)
+#define EXTI_BASE (APB2PERIPH_BASE + 0x3C00U)
+#define TIM9_BASE (APB2PERIPH_BASE + 0x4000U)
+#define TIM10_BASE (APB2PERIPH_BASE + 0x4400U)
+#define TIM11_BASE (APB2PERIPH_BASE + 0x4800U)
+
+/*!< AHB1 peripherals */
+#define GPIOA_BASE (AHB1PERIPH_BASE + 0x0000U)
+#define GPIOB_BASE (AHB1PERIPH_BASE + 0x0400U)
+#define GPIOC_BASE (AHB1PERIPH_BASE + 0x0800U)
+#define GPIOD_BASE (AHB1PERIPH_BASE + 0x0C00U)
+#define GPIOE_BASE (AHB1PERIPH_BASE + 0x1000U)
+#define GPIOH_BASE (AHB1PERIPH_BASE + 0x1C00U)
+#define CRC_BASE (AHB1PERIPH_BASE + 0x3000U)
+#define RCC_BASE (AHB1PERIPH_BASE + 0x3800U)
+#define FLASH_R_BASE (AHB1PERIPH_BASE + 0x3C00U)
+#define DMA1_BASE (AHB1PERIPH_BASE + 0x6000U)
+#define DMA1_Stream0_BASE (DMA1_BASE + 0x010U)
+#define DMA1_Stream1_BASE (DMA1_BASE + 0x028U)
+#define DMA1_Stream2_BASE (DMA1_BASE + 0x040U)
+#define DMA1_Stream3_BASE (DMA1_BASE + 0x058U)
+#define DMA1_Stream4_BASE (DMA1_BASE + 0x070U)
+#define DMA1_Stream5_BASE (DMA1_BASE + 0x088U)
+#define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0U)
+#define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8U)
+#define DMA2_BASE (AHB1PERIPH_BASE + 0x6400U)
+#define DMA2_Stream0_BASE (DMA2_BASE + 0x010U)
+#define DMA2_Stream1_BASE (DMA2_BASE + 0x028U)
+#define DMA2_Stream2_BASE (DMA2_BASE + 0x040U)
+#define DMA2_Stream3_BASE (DMA2_BASE + 0x058U)
+#define DMA2_Stream4_BASE (DMA2_BASE + 0x070U)
+#define DMA2_Stream5_BASE (DMA2_BASE + 0x088U)
+#define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0U)
+#define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8U)
+
+/* Debug MCU registers base address */
+#define DBGMCU_BASE 0xE0042000U
+
+/*!< USB registers base address */
+#define USB_OTG_FS_PERIPH_BASE 0x50000000U
+
+#define USB_OTG_GLOBAL_BASE 0x000U
+#define USB_OTG_DEVICE_BASE 0x800U
+#define USB_OTG_IN_ENDPOINT_BASE 0x900U
+#define USB_OTG_OUT_ENDPOINT_BASE 0xB00U
+#define USB_OTG_EP_REG_SIZE 0x20U
+#define USB_OTG_HOST_BASE 0x400U
+#define USB_OTG_HOST_PORT_BASE 0x440U
+#define USB_OTG_HOST_CHANNEL_BASE 0x500U
+#define USB_OTG_HOST_CHANNEL_SIZE 0x20U
+#define USB_OTG_PCGCCTL_BASE 0xE00U
+#define USB_OTG_FIFO_BASE 0x1000U
+#define USB_OTG_FIFO_SIZE 0x1000U
+
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_declaration
+ * @{
+ */
+#define TIM2 ((TIM_TypeDef *) TIM2_BASE)
+#define TIM3 ((TIM_TypeDef *) TIM3_BASE)
+#define TIM4 ((TIM_TypeDef *) TIM4_BASE)
+#define TIM5 ((TIM_TypeDef *) TIM5_BASE)
+#define RTC ((RTC_TypeDef *) RTC_BASE)
+#define WWDG ((WWDG_TypeDef *) WWDG_BASE)
+#define IWDG ((IWDG_TypeDef *) IWDG_BASE)
+#define I2S2ext ((SPI_TypeDef *) I2S2ext_BASE)
+#define SPI2 ((SPI_TypeDef *) SPI2_BASE)
+#define SPI3 ((SPI_TypeDef *) SPI3_BASE)
+#define I2S3ext ((SPI_TypeDef *) I2S3ext_BASE)
+#define USART2 ((USART_TypeDef *) USART2_BASE)
+#define I2C1 ((I2C_TypeDef *) I2C1_BASE)
+#define I2C2 ((I2C_TypeDef *) I2C2_BASE)
+#define I2C3 ((I2C_TypeDef *) I2C3_BASE)
+#define PWR ((PWR_TypeDef *) PWR_BASE)
+#define TIM1 ((TIM_TypeDef *) TIM1_BASE)
+#define USART1 ((USART_TypeDef *) USART1_BASE)
+#define USART6 ((USART_TypeDef *) USART6_BASE)
+#define ADC ((ADC_Common_TypeDef *) ADC_BASE)
+#define ADC1 ((ADC_TypeDef *) ADC1_BASE)
+#define SDIO ((SDIO_TypeDef *) SDIO_BASE)
+#define SPI1 ((SPI_TypeDef *) SPI1_BASE)
+#define SPI4 ((SPI_TypeDef *) SPI4_BASE)
+#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
+#define EXTI ((EXTI_TypeDef *) EXTI_BASE)
+#define TIM9 ((TIM_TypeDef *) TIM9_BASE)
+#define TIM10 ((TIM_TypeDef *) TIM10_BASE)
+#define TIM11 ((TIM_TypeDef *) TIM11_BASE)
+#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
+#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
+#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
+#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
+#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
+#define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
+#define CRC ((CRC_TypeDef *) CRC_BASE)
+#define RCC ((RCC_TypeDef *) RCC_BASE)
+#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
+#define DMA1 ((DMA_TypeDef *) DMA1_BASE)
+#define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)
+#define DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)
+#define DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)
+#define DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)
+#define DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)
+#define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)
+#define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)
+#define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)
+#define DMA2 ((DMA_TypeDef *) DMA2_BASE)
+#define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)
+#define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
+#define DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)
+#define DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)
+#define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)
+#define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)
+#define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)
+#define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)
+
+#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
+
+#define USB_OTG_FS ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE)
+
+/**
+ * @}
+ */
+
+/** @addtogroup Exported_constants
+ * @{
+ */
+
+ /** @addtogroup Peripheral_Registers_Bits_Definition
+ * @{
+ */
+
+/******************************************************************************/
+/* Peripheral Registers_Bits_Definition */
+/******************************************************************************/
+
+/******************************************************************************/
+/* */
+/* Analog to Digital Converter */
+/* */
+/******************************************************************************/
+/******************** Bit definition for ADC_SR register ********************/
+#define ADC_SR_AWD 0x00000001U /*!<Analog watchdog flag */
+#define ADC_SR_EOC 0x00000002U /*!<End of conversion */
+#define ADC_SR_JEOC 0x00000004U /*!<Injected channel end of conversion */
+#define ADC_SR_JSTRT 0x00000008U /*!<Injected channel Start flag */
+#define ADC_SR_STRT 0x00000010U /*!<Regular channel Start flag */
+#define ADC_SR_OVR 0x00000020U /*!<Overrun flag */
+
+/******************* Bit definition for ADC_CR1 register ********************/
+#define ADC_CR1_AWDCH 0x0000001FU /*!<AWDCH[4:0] bits (Analog watchdog channel select bits) */
+#define ADC_CR1_AWDCH_0 0x00000001U /*!<Bit 0 */
+#define ADC_CR1_AWDCH_1 0x00000002U /*!<Bit 1 */
+#define ADC_CR1_AWDCH_2 0x00000004U /*!<Bit 2 */
+#define ADC_CR1_AWDCH_3 0x00000008U /*!<Bit 3 */
+#define ADC_CR1_AWDCH_4 0x00000010U /*!<Bit 4 */
+#define ADC_CR1_EOCIE 0x00000020U /*!<Interrupt enable for EOC */
+#define ADC_CR1_AWDIE 0x00000040U /*!<AAnalog Watchdog interrupt enable */
+#define ADC_CR1_JEOCIE 0x00000080U /*!<Interrupt enable for injected channels */
+#define ADC_CR1_SCAN 0x00000100U /*!<Scan mode */
+#define ADC_CR1_AWDSGL 0x00000200U /*!<Enable the watchdog on a single channel in scan mode */
+#define ADC_CR1_JAUTO 0x00000400U /*!<Automatic injected group conversion */
+#define ADC_CR1_DISCEN 0x00000800U /*!<Discontinuous mode on regular channels */
+#define ADC_CR1_JDISCEN 0x00001000U /*!<Discontinuous mode on injected channels */
+#define ADC_CR1_DISCNUM 0x0000E000U /*!<DISCNUM[2:0] bits (Discontinuous mode channel count) */
+#define ADC_CR1_DISCNUM_0 0x00002000U /*!<Bit 0 */
+#define ADC_CR1_DISCNUM_1 0x00004000U /*!<Bit 1 */
+#define ADC_CR1_DISCNUM_2 0x00008000U /*!<Bit 2 */
+#define ADC_CR1_JAWDEN 0x00400000U /*!<Analog watchdog enable on injected channels */
+#define ADC_CR1_AWDEN 0x00800000U /*!<Analog watchdog enable on regular channels */
+#define ADC_CR1_RES 0x03000000U /*!<RES[2:0] bits (Resolution) */
+#define ADC_CR1_RES_0 0x01000000U /*!<Bit 0 */
+#define ADC_CR1_RES_1 0x02000000U /*!<Bit 1 */
+#define ADC_CR1_OVRIE 0x04000000U /*!<overrun interrupt enable */
+
+/******************* Bit definition for ADC_CR2 register ********************/
+#define ADC_CR2_ADON 0x00000001U /*!<A/D Converter ON / OFF */
+#define ADC_CR2_CONT 0x00000002U /*!<Continuous Conversion */
+#define ADC_CR2_DMA 0x00000100U /*!<Direct Memory access mode */
+#define ADC_CR2_DDS 0x00000200U /*!<DMA disable selection (Single ADC) */
+#define ADC_CR2_EOCS 0x00000400U /*!<End of conversion selection */
+#define ADC_CR2_ALIGN 0x00000800U /*!<Data Alignment */
+#define ADC_CR2_JEXTSEL 0x000F0000U /*!<JEXTSEL[3:0] bits (External event select for injected group) */
+#define ADC_CR2_JEXTSEL_0 0x00010000U /*!<Bit 0 */
+#define ADC_CR2_JEXTSEL_1 0x00020000U /*!<Bit 1 */
+#define ADC_CR2_JEXTSEL_2 0x00040000U /*!<Bit 2 */
+#define ADC_CR2_JEXTSEL_3 0x00080000U /*!<Bit 3 */
+#define ADC_CR2_JEXTEN 0x00300000U /*!<JEXTEN[1:0] bits (External Trigger Conversion mode for injected channelsp) */
+#define ADC_CR2_JEXTEN_0 0x00100000U /*!<Bit 0 */
+#define ADC_CR2_JEXTEN_1 0x00200000U /*!<Bit 1 */
+#define ADC_CR2_JSWSTART 0x00400000U /*!<Start Conversion of injected channels */
+#define ADC_CR2_EXTSEL 0x0F000000U /*!<EXTSEL[3:0] bits (External Event Select for regular group) */
+#define ADC_CR2_EXTSEL_0 0x01000000U /*!<Bit 0 */
+#define ADC_CR2_EXTSEL_1 0x02000000U /*!<Bit 1 */
+#define ADC_CR2_EXTSEL_2 0x04000000U /*!<Bit 2 */
+#define ADC_CR2_EXTSEL_3 0x08000000U /*!<Bit 3 */
+#define ADC_CR2_EXTEN 0x30000000U /*!<EXTEN[1:0] bits (External Trigger Conversion mode for regular channelsp) */
+#define ADC_CR2_EXTEN_0 0x10000000U /*!<Bit 0 */
+#define ADC_CR2_EXTEN_1 0x20000000U /*!<Bit 1 */
+#define ADC_CR2_SWSTART 0x40000000U /*!<Start Conversion of regular channels */
+
+/****************** Bit definition for ADC_SMPR1 register *******************/
+#define ADC_SMPR1_SMP10 0x00000007U /*!<SMP10[2:0] bits (Channel 10 Sample time selection) */
+#define ADC_SMPR1_SMP10_0 0x00000001U /*!<Bit 0 */
+#define ADC_SMPR1_SMP10_1 0x00000002U /*!<Bit 1 */
+#define ADC_SMPR1_SMP10_2 0x00000004U /*!<Bit 2 */
+#define ADC_SMPR1_SMP11 0x00000038U /*!<SMP11[2:0] bits (Channel 11 Sample time selection) */
+#define ADC_SMPR1_SMP11_0 0x00000008U /*!<Bit 0 */
+#define ADC_SMPR1_SMP11_1 0x00000010U /*!<Bit 1 */
+#define ADC_SMPR1_SMP11_2 0x00000020U /*!<Bit 2 */
+#define ADC_SMPR1_SMP12 0x000001C0U /*!<SMP12[2:0] bits (Channel 12 Sample time selection) */
+#define ADC_SMPR1_SMP12_0 0x00000040U /*!<Bit 0 */
+#define ADC_SMPR1_SMP12_1 0x00000080U /*!<Bit 1 */
+#define ADC_SMPR1_SMP12_2 0x00000100U /*!<Bit 2 */
+#define ADC_SMPR1_SMP13 0x00000E00U /*!<SMP13[2:0] bits (Channel 13 Sample time selection) */
+#define ADC_SMPR1_SMP13_0 0x00000200U /*!<Bit 0 */
+#define ADC_SMPR1_SMP13_1 0x00000400U /*!<Bit 1 */
+#define ADC_SMPR1_SMP13_2 0x00000800U /*!<Bit 2 */
+#define ADC_SMPR1_SMP14 0x00007000U /*!<SMP14[2:0] bits (Channel 14 Sample time selection) */
+#define ADC_SMPR1_SMP14_0 0x00001000U /*!<Bit 0 */
+#define ADC_SMPR1_SMP14_1 0x00002000U /*!<Bit 1 */
+#define ADC_SMPR1_SMP14_2 0x00004000U /*!<Bit 2 */
+#define ADC_SMPR1_SMP15 0x00038000U /*!<SMP15[2:0] bits (Channel 15 Sample time selection) */
+#define ADC_SMPR1_SMP15_0 0x00008000U /*!<Bit 0 */
+#define ADC_SMPR1_SMP15_1 0x00010000U /*!<Bit 1 */
+#define ADC_SMPR1_SMP15_2 0x00020000U /*!<Bit 2 */
+#define ADC_SMPR1_SMP16 0x001C0000U /*!<SMP16[2:0] bits (Channel 16 Sample time selection) */
+#define ADC_SMPR1_SMP16_0 0x00040000U /*!<Bit 0 */
+#define ADC_SMPR1_SMP16_1 0x00080000U /*!<Bit 1 */
+#define ADC_SMPR1_SMP16_2 0x00100000U /*!<Bit 2 */
+#define ADC_SMPR1_SMP17 0x00E00000U /*!<SMP17[2:0] bits (Channel 17 Sample time selection) */
+#define ADC_SMPR1_SMP17_0 0x00200000U /*!<Bit 0 */
+#define ADC_SMPR1_SMP17_1 0x00400000U /*!<Bit 1 */
+#define ADC_SMPR1_SMP17_2 0x00800000U /*!<Bit 2 */
+#define ADC_SMPR1_SMP18 0x07000000U /*!<SMP18[2:0] bits (Channel 18 Sample time selection) */
+#define ADC_SMPR1_SMP18_0 0x01000000U /*!<Bit 0 */
+#define ADC_SMPR1_SMP18_1 0x02000000U /*!<Bit 1 */
+#define ADC_SMPR1_SMP18_2 0x04000000U /*!<Bit 2 */
+
+/****************** Bit definition for ADC_SMPR2 register *******************/
+#define ADC_SMPR2_SMP0 0x00000007U /*!<SMP0[2:0] bits (Channel 0 Sample time selection) */
+#define ADC_SMPR2_SMP0_0 0x00000001U /*!<Bit 0 */
+#define ADC_SMPR2_SMP0_1 0x00000002U /*!<Bit 1 */
+#define ADC_SMPR2_SMP0_2 0x00000004U /*!<Bit 2 */
+#define ADC_SMPR2_SMP1 0x00000038U /*!<SMP1[2:0] bits (Channel 1 Sample time selection) */
+#define ADC_SMPR2_SMP1_0 0x00000008U /*!<Bit 0 */
+#define ADC_SMPR2_SMP1_1 0x00000010U /*!<Bit 1 */
+#define ADC_SMPR2_SMP1_2 0x00000020U /*!<Bit 2 */
+#define ADC_SMPR2_SMP2 0x000001C0U /*!<SMP2[2:0] bits (Channel 2 Sample time selection) */
+#define ADC_SMPR2_SMP2_0 0x00000040U /*!<Bit 0 */
+#define ADC_SMPR2_SMP2_1 0x00000080U /*!<Bit 1 */
+#define ADC_SMPR2_SMP2_2 0x00000100U /*!<Bit 2 */
+#define ADC_SMPR2_SMP3 0x00000E00U /*!<SMP3[2:0] bits (Channel 3 Sample time selection) */
+#define ADC_SMPR2_SMP3_0 0x00000200U /*!<Bit 0 */
+#define ADC_SMPR2_SMP3_1 0x00000400U /*!<Bit 1 */
+#define ADC_SMPR2_SMP3_2 0x00000800U /*!<Bit 2 */
+#define ADC_SMPR2_SMP4 0x00007000U /*!<SMP4[2:0] bits (Channel 4 Sample time selection) */
+#define ADC_SMPR2_SMP4_0 0x00001000U /*!<Bit 0 */
+#define ADC_SMPR2_SMP4_1 0x00002000U /*!<Bit 1 */
+#define ADC_SMPR2_SMP4_2 0x00004000U /*!<Bit 2 */
+#define ADC_SMPR2_SMP5 0x00038000U /*!<SMP5[2:0] bits (Channel 5 Sample time selection) */
+#define ADC_SMPR2_SMP5_0 0x00008000U /*!<Bit 0 */
+#define ADC_SMPR2_SMP5_1 0x00010000U /*!<Bit 1 */
+#define ADC_SMPR2_SMP5_2 0x00020000U /*!<Bit 2 */
+#define ADC_SMPR2_SMP6 0x001C0000U /*!<SMP6[2:0] bits (Channel 6 Sample time selection) */
+#define ADC_SMPR2_SMP6_0 0x00040000U /*!<Bit 0 */
+#define ADC_SMPR2_SMP6_1 0x00080000U /*!<Bit 1 */
+#define ADC_SMPR2_SMP6_2 0x00100000U /*!<Bit 2 */
+#define ADC_SMPR2_SMP7 0x00E00000U /*!<SMP7[2:0] bits (Channel 7 Sample time selection) */
+#define ADC_SMPR2_SMP7_0 0x00200000U /*!<Bit 0 */
+#define ADC_SMPR2_SMP7_1 0x00400000U /*!<Bit 1 */
+#define ADC_SMPR2_SMP7_2 0x00800000U /*!<Bit 2 */
+#define ADC_SMPR2_SMP8 0x07000000U /*!<SMP8[2:0] bits (Channel 8 Sample time selection) */
+#define ADC_SMPR2_SMP8_0 0x01000000U /*!<Bit 0 */
+#define ADC_SMPR2_SMP8_1 0x02000000U /*!<Bit 1 */
+#define ADC_SMPR2_SMP8_2 0x04000000U /*!<Bit 2 */
+#define ADC_SMPR2_SMP9 0x38000000U /*!<SMP9[2:0] bits (Channel 9 Sample time selection) */
+#define ADC_SMPR2_SMP9_0 0x08000000U /*!<Bit 0 */
+#define ADC_SMPR2_SMP9_1 0x10000000U /*!<Bit 1 */
+#define ADC_SMPR2_SMP9_2 0x20000000U /*!<Bit 2 */
+
+/****************** Bit definition for ADC_JOFR1 register *******************/
+#define ADC_JOFR1_JOFFSET1 0x0FFFU /*!<Data offset for injected channel 1 */
+
+/****************** Bit definition for ADC_JOFR2 register *******************/
+#define ADC_JOFR2_JOFFSET2 0x0FFFU /*!<Data offset for injected channel 2 */
+
+/****************** Bit definition for ADC_JOFR3 register *******************/
+#define ADC_JOFR3_JOFFSET3 0x0FFFU /*!<Data offset for injected channel 3 */
+
+/****************** Bit definition for ADC_JOFR4 register *******************/
+#define ADC_JOFR4_JOFFSET4 0x0FFFU /*!<Data offset for injected channel 4 */
+
+/******************* Bit definition for ADC_HTR register ********************/
+#define ADC_HTR_HT 0x0FFFU /*!<Analog watchdog high threshold */
+
+/******************* Bit definition for ADC_LTR register ********************/
+#define ADC_LTR_LT 0x0FFFU /*!<Analog watchdog low threshold */
+
+/******************* Bit definition for ADC_SQR1 register *******************/
+#define ADC_SQR1_SQ13 0x0000001FU /*!<SQ13[4:0] bits (13th conversion in regular sequence) */
+#define ADC_SQR1_SQ13_0 0x00000001U /*!<Bit 0 */
+#define ADC_SQR1_SQ13_1 0x00000002U /*!<Bit 1 */
+#define ADC_SQR1_SQ13_2 0x00000004U /*!<Bit 2 */
+#define ADC_SQR1_SQ13_3 0x00000008U /*!<Bit 3 */
+#define ADC_SQR1_SQ13_4 0x00000010U /*!<Bit 4 */
+#define ADC_SQR1_SQ14 0x000003E0U /*!<SQ14[4:0] bits (14th conversion in regular sequence) */
+#define ADC_SQR1_SQ14_0 0x00000020U /*!<Bit 0 */
+#define ADC_SQR1_SQ14_1 0x00000040U /*!<Bit 1 */
+#define ADC_SQR1_SQ14_2 0x00000080U /*!<Bit 2 */
+#define ADC_SQR1_SQ14_3 0x00000100U /*!<Bit 3 */
+#define ADC_SQR1_SQ14_4 0x00000200U /*!<Bit 4 */
+#define ADC_SQR1_SQ15 0x00007C00U /*!<SQ15[4:0] bits (15th conversion in regular sequence) */
+#define ADC_SQR1_SQ15_0 0x00000400U /*!<Bit 0 */
+#define ADC_SQR1_SQ15_1 0x00000800U /*!<Bit 1 */
+#define ADC_SQR1_SQ15_2 0x00001000U /*!<Bit 2 */
+#define ADC_SQR1_SQ15_3 0x00002000U /*!<Bit 3 */
+#define ADC_SQR1_SQ15_4 0x00004000U /*!<Bit 4 */
+#define ADC_SQR1_SQ16 0x000F8000U /*!<SQ16[4:0] bits (16th conversion in regular sequence) */
+#define ADC_SQR1_SQ16_0 0x00008000U /*!<Bit 0 */
+#define ADC_SQR1_SQ16_1 0x00010000U /*!<Bit 1 */
+#define ADC_SQR1_SQ16_2 0x00020000U /*!<Bit 2 */
+#define ADC_SQR1_SQ16_3 0x00040000U /*!<Bit 3 */
+#define ADC_SQR1_SQ16_4 0x00080000U /*!<Bit 4 */
+#define ADC_SQR1_L 0x00F00000U /*!<L[3:0] bits (Regular channel sequence length) */
+#define ADC_SQR1_L_0 0x00100000U /*!<Bit 0 */
+#define ADC_SQR1_L_1 0x00200000U /*!<Bit 1 */
+#define ADC_SQR1_L_2 0x00400000U /*!<Bit 2 */
+#define ADC_SQR1_L_3 0x00800000U /*!<Bit 3 */
+
+/******************* Bit definition for ADC_SQR2 register *******************/
+#define ADC_SQR2_SQ7 0x0000001FU /*!<SQ7[4:0] bits (7th conversion in regular sequence) */
+#define ADC_SQR2_SQ7_0 0x00000001U /*!<Bit 0 */
+#define ADC_SQR2_SQ7_1 0x00000002U /*!<Bit 1 */
+#define ADC_SQR2_SQ7_2 0x00000004U /*!<Bit 2 */
+#define ADC_SQR2_SQ7_3 0x00000008U /*!<Bit 3 */
+#define ADC_SQR2_SQ7_4 0x00000010U /*!<Bit 4 */
+#define ADC_SQR2_SQ8 0x000003E0U /*!<SQ8[4:0] bits (8th conversion in regular sequence) */
+#define ADC_SQR2_SQ8_0 0x00000020U /*!<Bit 0 */
+#define ADC_SQR2_SQ8_1 0x00000040U /*!<Bit 1 */
+#define ADC_SQR2_SQ8_2 0x00000080U /*!<Bit 2 */
+#define ADC_SQR2_SQ8_3 0x00000100U /*!<Bit 3 */
+#define ADC_SQR2_SQ8_4 0x00000200U /*!<Bit 4 */
+#define ADC_SQR2_SQ9 0x00007C00U /*!<SQ9[4:0] bits (9th conversion in regular sequence) */
+#define ADC_SQR2_SQ9_0 0x00000400U /*!<Bit 0 */
+#define ADC_SQR2_SQ9_1 0x00000800U /*!<Bit 1 */
+#define ADC_SQR2_SQ9_2 0x00001000U /*!<Bit 2 */
+#define ADC_SQR2_SQ9_3 0x00002000U /*!<Bit 3 */
+#define ADC_SQR2_SQ9_4 0x00004000U /*!<Bit 4 */
+#define ADC_SQR2_SQ10 0x000F8000U /*!<SQ10[4:0] bits (10th conversion in regular sequence) */
+#define ADC_SQR2_SQ10_0 0x00008000U /*!<Bit 0 */
+#define ADC_SQR2_SQ10_1 0x00010000U /*!<Bit 1 */
+#define ADC_SQR2_SQ10_2 0x00020000U /*!<Bit 2 */
+#define ADC_SQR2_SQ10_3 0x00040000U /*!<Bit 3 */
+#define ADC_SQR2_SQ10_4 0x00080000U /*!<Bit 4 */
+#define ADC_SQR2_SQ11 0x01F00000U /*!<SQ11[4:0] bits (11th conversion in regular sequence) */
+#define ADC_SQR2_SQ11_0 0x00100000U /*!<Bit 0 */
+#define ADC_SQR2_SQ11_1 0x00200000U /*!<Bit 1 */
+#define ADC_SQR2_SQ11_2 0x00400000U /*!<Bit 2 */
+#define ADC_SQR2_SQ11_3 0x00800000U /*!<Bit 3 */
+#define ADC_SQR2_SQ11_4 0x01000000U /*!<Bit 4 */
+#define ADC_SQR2_SQ12 0x3E000000U /*!<SQ12[4:0] bits (12th conversion in regular sequence) */
+#define ADC_SQR2_SQ12_0 0x02000000U /*!<Bit 0 */
+#define ADC_SQR2_SQ12_1 0x04000000U /*!<Bit 1 */
+#define ADC_SQR2_SQ12_2 0x08000000U /*!<Bit 2 */
+#define ADC_SQR2_SQ12_3 0x10000000U /*!<Bit 3 */
+#define ADC_SQR2_SQ12_4 0x20000000U /*!<Bit 4 */
+
+/******************* Bit definition for ADC_SQR3 register *******************/
+#define ADC_SQR3_SQ1 0x0000001FU /*!<SQ1[4:0] bits (1st conversion in regular sequence) */
+#define ADC_SQR3_SQ1_0 0x00000001U /*!<Bit 0 */
+#define ADC_SQR3_SQ1_1 0x00000002U /*!<Bit 1 */
+#define ADC_SQR3_SQ1_2 0x00000004U /*!<Bit 2 */
+#define ADC_SQR3_SQ1_3 0x00000008U /*!<Bit 3 */
+#define ADC_SQR3_SQ1_4 0x00000010U /*!<Bit 4 */
+#define ADC_SQR3_SQ2 0x000003E0U /*!<SQ2[4:0] bits (2nd conversion in regular sequence) */
+#define ADC_SQR3_SQ2_0 0x00000020U /*!<Bit 0 */
+#define ADC_SQR3_SQ2_1 0x00000040U /*!<Bit 1 */
+#define ADC_SQR3_SQ2_2 0x00000080U /*!<Bit 2 */
+#define ADC_SQR3_SQ2_3 0x00000100U /*!<Bit 3 */
+#define ADC_SQR3_SQ2_4 0x00000200U /*!<Bit 4 */
+#define ADC_SQR3_SQ3 0x00007C00U /*!<SQ3[4:0] bits (3rd conversion in regular sequence) */
+#define ADC_SQR3_SQ3_0 0x00000400U /*!<Bit 0 */
+#define ADC_SQR3_SQ3_1 0x00000800U /*!<Bit 1 */
+#define ADC_SQR3_SQ3_2 0x00001000U /*!<Bit 2 */
+#define ADC_SQR3_SQ3_3 0x00002000U /*!<Bit 3 */
+#define ADC_SQR3_SQ3_4 0x00004000U /*!<Bit 4 */
+#define ADC_SQR3_SQ4 0x000F8000U /*!<SQ4[4:0] bits (4th conversion in regular sequence) */
+#define ADC_SQR3_SQ4_0 0x00008000U /*!<Bit 0 */
+#define ADC_SQR3_SQ4_1 0x00010000U /*!<Bit 1 */
+#define ADC_SQR3_SQ4_2 0x00020000U /*!<Bit 2 */
+#define ADC_SQR3_SQ4_3 0x00040000U /*!<Bit 3 */
+#define ADC_SQR3_SQ4_4 0x00080000U /*!<Bit 4 */
+#define ADC_SQR3_SQ5 0x01F00000U /*!<SQ5[4:0] bits (5th conversion in regular sequence) */
+#define ADC_SQR3_SQ5_0 0x00100000U /*!<Bit 0 */
+#define ADC_SQR3_SQ5_1 0x00200000U /*!<Bit 1 */
+#define ADC_SQR3_SQ5_2 0x00400000U /*!<Bit 2 */
+#define ADC_SQR3_SQ5_3 0x00800000U /*!<Bit 3 */
+#define ADC_SQR3_SQ5_4 0x01000000U /*!<Bit 4 */
+#define ADC_SQR3_SQ6 0x3E000000U /*!<SQ6[4:0] bits (6th conversion in regular sequence) */
+#define ADC_SQR3_SQ6_0 0x02000000U /*!<Bit 0 */
+#define ADC_SQR3_SQ6_1 0x04000000U /*!<Bit 1 */
+#define ADC_SQR3_SQ6_2 0x08000000U /*!<Bit 2 */
+#define ADC_SQR3_SQ6_3 0x10000000U /*!<Bit 3 */
+#define ADC_SQR3_SQ6_4 0x20000000U /*!<Bit 4 */
+
+/******************* Bit definition for ADC_JSQR register *******************/
+#define ADC_JSQR_JSQ1 0x0000001FU /*!<JSQ1[4:0] bits (1st conversion in injected sequence) */
+#define ADC_JSQR_JSQ1_0 0x00000001U /*!<Bit 0 */
+#define ADC_JSQR_JSQ1_1 0x00000002U /*!<Bit 1 */
+#define ADC_JSQR_JSQ1_2 0x00000004U /*!<Bit 2 */
+#define ADC_JSQR_JSQ1_3 0x00000008U /*!<Bit 3 */
+#define ADC_JSQR_JSQ1_4 0x00000010U /*!<Bit 4 */
+#define ADC_JSQR_JSQ2 0x000003E0U /*!<JSQ2[4:0] bits (2nd conversion in injected sequence) */
+#define ADC_JSQR_JSQ2_0 0x00000020U /*!<Bit 0 */
+#define ADC_JSQR_JSQ2_1 0x00000040U /*!<Bit 1 */
+#define ADC_JSQR_JSQ2_2 0x00000080U /*!<Bit 2 */
+#define ADC_JSQR_JSQ2_3 0x00000100U /*!<Bit 3 */
+#define ADC_JSQR_JSQ2_4 0x00000200U /*!<Bit 4 */
+#define ADC_JSQR_JSQ3 0x00007C00U /*!<JSQ3[4:0] bits (3rd conversion in injected sequence) */
+#define ADC_JSQR_JSQ3_0 0x00000400U /*!<Bit 0 */
+#define ADC_JSQR_JSQ3_1 0x00000800U /*!<Bit 1 */
+#define ADC_JSQR_JSQ3_2 0x00001000U /*!<Bit 2 */
+#define ADC_JSQR_JSQ3_3 0x00002000U /*!<Bit 3 */
+#define ADC_JSQR_JSQ3_4 0x00004000U /*!<Bit 4 */
+#define ADC_JSQR_JSQ4 0x000F8000U /*!<JSQ4[4:0] bits (4th conversion in injected sequence) */
+#define ADC_JSQR_JSQ4_0 0x00008000U /*!<Bit 0 */
+#define ADC_JSQR_JSQ4_1 0x00010000U /*!<Bit 1 */
+#define ADC_JSQR_JSQ4_2 0x00020000U /*!<Bit 2 */
+#define ADC_JSQR_JSQ4_3 0x00040000U /*!<Bit 3 */
+#define ADC_JSQR_JSQ4_4 0x00080000U /*!<Bit 4 */
+#define ADC_JSQR_JL 0x00300000U /*!<JL[1:0] bits (Injected Sequence length) */
+#define ADC_JSQR_JL_0 0x00100000U /*!<Bit 0 */
+#define ADC_JSQR_JL_1 0x00200000U /*!<Bit 1 */
+
+/******************* Bit definition for ADC_JDR1 register *******************/
+#define ADC_JDR1_JDATA 0xFFFFU /*!<Injected data */
+
+/******************* Bit definition for ADC_JDR2 register *******************/
+#define ADC_JDR2_JDATA 0xFFFFU /*!<Injected data */
+
+/******************* Bit definition for ADC_JDR3 register *******************/
+#define ADC_JDR3_JDATA 0xFFFFU /*!<Injected data */
+
+/******************* Bit definition for ADC_JDR4 register *******************/
+#define ADC_JDR4_JDATA 0xFFFFU /*!<Injected data */
+
+/******************** Bit definition for ADC_DR register ********************/
+#define ADC_DR_DATA 0x0000FFFFU /*!<Regular data */
+#define ADC_DR_ADC2DATA 0xFFFF0000U /*!<ADC2 data */
+
+/******************* Bit definition for ADC_CSR register ********************/
+#define ADC_CSR_AWD1 0x00000001U /*!<ADC1 Analog watchdog flag */
+#define ADC_CSR_EOC1 0x00000002U /*!<ADC1 End of conversion */
+#define ADC_CSR_JEOC1 0x00000004U /*!<ADC1 Injected channel end of conversion */
+#define ADC_CSR_JSTRT1 0x00000008U /*!<ADC1 Injected channel Start flag */
+#define ADC_CSR_STRT1 0x00000010U /*!<ADC1 Regular channel Start flag */
+#define ADC_CSR_OVR1 0x00000020U /*!<ADC1 DMA overrun flag */
+#define ADC_CSR_AWD2 0x00000100U /*!<ADC2 Analog watchdog flag */
+#define ADC_CSR_EOC2 0x00000200U /*!<ADC2 End of conversion */
+#define ADC_CSR_JEOC2 0x00000400U /*!<ADC2 Injected channel end of conversion */
+#define ADC_CSR_JSTRT2 0x00000800U /*!<ADC2 Injected channel Start flag */
+#define ADC_CSR_STRT2 0x00001000U /*!<ADC2 Regular channel Start flag */
+#define ADC_CSR_OVR2 0x00002000U /*!<ADC2 DMA overrun flag */
+#define ADC_CSR_AWD3 0x00010000U /*!<ADC3 Analog watchdog flag */
+#define ADC_CSR_EOC3 0x00020000U /*!<ADC3 End of conversion */
+#define ADC_CSR_JEOC3 0x00040000U /*!<ADC3 Injected channel end of conversion */
+#define ADC_CSR_JSTRT3 0x00080000U /*!<ADC3 Injected channel Start flag */
+#define ADC_CSR_STRT3 0x00100000U /*!<ADC3 Regular channel Start flag */
+#define ADC_CSR_OVR3 0x00200000U /*!<ADC3 DMA overrun flag */
+
+/* Legacy defines */
+#define ADC_CSR_DOVR1 ADC_CSR_OVR1
+#define ADC_CSR_DOVR2 ADC_CSR_OVR2
+#define ADC_CSR_DOVR3 ADC_CSR_OVR3
+
+/******************* Bit definition for ADC_CCR register ********************/
+#define ADC_CCR_MULTI 0x0000001FU /*!<MULTI[4:0] bits (Multi-ADC mode selection) */
+#define ADC_CCR_MULTI_0 0x00000001U /*!<Bit 0 */
+#define ADC_CCR_MULTI_1 0x00000002U /*!<Bit 1 */
+#define ADC_CCR_MULTI_2 0x00000004U /*!<Bit 2 */
+#define ADC_CCR_MULTI_3 0x00000008U /*!<Bit 3 */
+#define ADC_CCR_MULTI_4 0x00000010U /*!<Bit 4 */
+#define ADC_CCR_DELAY 0x00000F00U /*!<DELAY[3:0] bits (Delay between 2 sampling phases) */
+#define ADC_CCR_DELAY_0 0x00000100U /*!<Bit 0 */
+#define ADC_CCR_DELAY_1 0x00000200U /*!<Bit 1 */
+#define ADC_CCR_DELAY_2 0x00000400U /*!<Bit 2 */
+#define ADC_CCR_DELAY_3 0x00000800U /*!<Bit 3 */
+#define ADC_CCR_DDS 0x00002000U /*!<DMA disable selection (Multi-ADC mode) */
+#define ADC_CCR_DMA 0x0000C000U /*!<DMA[1:0] bits (Direct Memory Access mode for multimode) */
+#define ADC_CCR_DMA_0 0x00004000U /*!<Bit 0 */
+#define ADC_CCR_DMA_1 0x00008000U /*!<Bit 1 */
+#define ADC_CCR_ADCPRE 0x00030000U /*!<ADCPRE[1:0] bits (ADC prescaler) */
+#define ADC_CCR_ADCPRE_0 0x00010000U /*!<Bit 0 */
+#define ADC_CCR_ADCPRE_1 0x00020000U /*!<Bit 1 */
+#define ADC_CCR_VBATE 0x00400000U /*!<VBAT Enable */
+#define ADC_CCR_TSVREFE 0x00800000U /*!<Temperature Sensor and VREFINT Enable */
+
+/******************* Bit definition for ADC_CDR register ********************/
+#define ADC_CDR_DATA1 0x0000FFFFU /*!<1st data of a pair of regular conversions */
+#define ADC_CDR_DATA2 0xFFFF0000U /*!<2nd data of a pair of regular conversions */
+
+/******************************************************************************/
+/* */
+/* CRC calculation unit */
+/* */
+/******************************************************************************/
+/******************* Bit definition for CRC_DR register *********************/
+#define CRC_DR_DR 0xFFFFFFFFU /*!< Data register bits */
+
+
+/******************* Bit definition for CRC_IDR register ********************/
+#define CRC_IDR_IDR 0xFFU /*!< General-purpose 8-bit data register bits */
+
+
+/******************** Bit definition for CRC_CR register ********************/
+#define CRC_CR_RESET 0x01U /*!< RESET bit */
+
+/******************************************************************************/
+/* */
+/* Debug MCU */
+/* */
+/******************************************************************************/
+
+/******************************************************************************/
+/* */
+/* DMA Controller */
+/* */
+/******************************************************************************/
+/******************** Bits definition for DMA_SxCR register *****************/
+#define DMA_SxCR_CHSEL 0x0E000000U
+#define DMA_SxCR_CHSEL_0 0x02000000U
+#define DMA_SxCR_CHSEL_1 0x04000000U
+#define DMA_SxCR_CHSEL_2 0x08000000U
+#define DMA_SxCR_MBURST 0x01800000U
+#define DMA_SxCR_MBURST_0 0x00800000U
+#define DMA_SxCR_MBURST_1 0x01000000U
+#define DMA_SxCR_PBURST 0x00600000U
+#define DMA_SxCR_PBURST_0 0x00200000U
+#define DMA_SxCR_PBURST_1 0x00400000U
+#define DMA_SxCR_CT 0x00080000U
+#define DMA_SxCR_DBM 0x00040000U
+#define DMA_SxCR_PL 0x00030000U
+#define DMA_SxCR_PL_0 0x00010000U
+#define DMA_SxCR_PL_1 0x00020000U
+#define DMA_SxCR_PINCOS 0x00008000U
+#define DMA_SxCR_MSIZE 0x00006000U
+#define DMA_SxCR_MSIZE_0 0x00002000U
+#define DMA_SxCR_MSIZE_1 0x00004000U
+#define DMA_SxCR_PSIZE 0x00001800U
+#define DMA_SxCR_PSIZE_0 0x00000800U
+#define DMA_SxCR_PSIZE_1 0x00001000U
+#define DMA_SxCR_MINC 0x00000400U
+#define DMA_SxCR_PINC 0x00000200U
+#define DMA_SxCR_CIRC 0x00000100U
+#define DMA_SxCR_DIR 0x000000C0U
+#define DMA_SxCR_DIR_0 0x00000040U
+#define DMA_SxCR_DIR_1 0x00000080U
+#define DMA_SxCR_PFCTRL 0x00000020U
+#define DMA_SxCR_TCIE 0x00000010U
+#define DMA_SxCR_HTIE 0x00000008U
+#define DMA_SxCR_TEIE 0x00000004U
+#define DMA_SxCR_DMEIE 0x00000002U
+#define DMA_SxCR_EN 0x00000001U
+
+/* Legacy defines */
+#define DMA_SxCR_ACK 0x00100000U
+
+/******************** Bits definition for DMA_SxCNDTR register **************/
+#define DMA_SxNDT 0x0000FFFFU
+#define DMA_SxNDT_0 0x00000001U
+#define DMA_SxNDT_1 0x00000002U
+#define DMA_SxNDT_2 0x00000004U
+#define DMA_SxNDT_3 0x00000008U
+#define DMA_SxNDT_4 0x00000010U
+#define DMA_SxNDT_5 0x00000020U
+#define DMA_SxNDT_6 0x00000040U
+#define DMA_SxNDT_7 0x00000080U
+#define DMA_SxNDT_8 0x00000100U
+#define DMA_SxNDT_9 0x00000200U
+#define DMA_SxNDT_10 0x00000400U
+#define DMA_SxNDT_11 0x00000800U
+#define DMA_SxNDT_12 0x00001000U
+#define DMA_SxNDT_13 0x00002000U
+#define DMA_SxNDT_14 0x00004000U
+#define DMA_SxNDT_15 0x00008000U
+
+/******************** Bits definition for DMA_SxFCR register ****************/
+#define DMA_SxFCR_FEIE 0x00000080U
+#define DMA_SxFCR_FS 0x00000038U
+#define DMA_SxFCR_FS_0 0x00000008U
+#define DMA_SxFCR_FS_1 0x00000010U
+#define DMA_SxFCR_FS_2 0x00000020U
+#define DMA_SxFCR_DMDIS 0x00000004U
+#define DMA_SxFCR_FTH 0x00000003U
+#define DMA_SxFCR_FTH_0 0x00000001U
+#define DMA_SxFCR_FTH_1 0x00000002U
+
+/******************** Bits definition for DMA_LISR register *****************/
+#define DMA_LISR_TCIF3 0x08000000U
+#define DMA_LISR_HTIF3 0x04000000U
+#define DMA_LISR_TEIF3 0x02000000U
+#define DMA_LISR_DMEIF3 0x01000000U
+#define DMA_LISR_FEIF3 0x00400000U
+#define DMA_LISR_TCIF2 0x00200000U
+#define DMA_LISR_HTIF2 0x00100000U
+#define DMA_LISR_TEIF2 0x00080000U
+#define DMA_LISR_DMEIF2 0x00040000U
+#define DMA_LISR_FEIF2 0x00010000U
+#define DMA_LISR_TCIF1 0x00000800U
+#define DMA_LISR_HTIF1 0x00000400U
+#define DMA_LISR_TEIF1 0x00000200U
+#define DMA_LISR_DMEIF1 0x00000100U
+#define DMA_LISR_FEIF1 0x00000040U
+#define DMA_LISR_TCIF0 0x00000020U
+#define DMA_LISR_HTIF0 0x00000010U
+#define DMA_LISR_TEIF0 0x00000008U
+#define DMA_LISR_DMEIF0 0x00000004U
+#define DMA_LISR_FEIF0 0x00000001U
+
+/******************** Bits definition for DMA_HISR register *****************/
+#define DMA_HISR_TCIF7 0x08000000U
+#define DMA_HISR_HTIF7 0x04000000U
+#define DMA_HISR_TEIF7 0x02000000U
+#define DMA_HISR_DMEIF7 0x01000000U
+#define DMA_HISR_FEIF7 0x00400000U
+#define DMA_HISR_TCIF6 0x00200000U
+#define DMA_HISR_HTIF6 0x00100000U
+#define DMA_HISR_TEIF6 0x00080000U
+#define DMA_HISR_DMEIF6 0x00040000U
+#define DMA_HISR_FEIF6 0x00010000U
+#define DMA_HISR_TCIF5 0x00000800U
+#define DMA_HISR_HTIF5 0x00000400U
+#define DMA_HISR_TEIF5 0x00000200U
+#define DMA_HISR_DMEIF5 0x00000100U
+#define DMA_HISR_FEIF5 0x00000040U
+#define DMA_HISR_TCIF4 0x00000020U
+#define DMA_HISR_HTIF4 0x00000010U
+#define DMA_HISR_TEIF4 0x00000008U
+#define DMA_HISR_DMEIF4 0x00000004U
+#define DMA_HISR_FEIF4 0x00000001U
+
+/******************** Bits definition for DMA_LIFCR register ****************/
+#define DMA_LIFCR_CTCIF3 0x08000000U
+#define DMA_LIFCR_CHTIF3 0x04000000U
+#define DMA_LIFCR_CTEIF3 0x02000000U
+#define DMA_LIFCR_CDMEIF3 0x01000000U
+#define DMA_LIFCR_CFEIF3 0x00400000U
+#define DMA_LIFCR_CTCIF2 0x00200000U
+#define DMA_LIFCR_CHTIF2 0x00100000U
+#define DMA_LIFCR_CTEIF2 0x00080000U
+#define DMA_LIFCR_CDMEIF2 0x00040000U
+#define DMA_LIFCR_CFEIF2 0x00010000U
+#define DMA_LIFCR_CTCIF1 0x00000800U
+#define DMA_LIFCR_CHTIF1 0x00000400U
+#define DMA_LIFCR_CTEIF1 0x00000200U
+#define DMA_LIFCR_CDMEIF1 0x00000100U
+#define DMA_LIFCR_CFEIF1 0x00000040U
+#define DMA_LIFCR_CTCIF0 0x00000020U
+#define DMA_LIFCR_CHTIF0 0x00000010U
+#define DMA_LIFCR_CTEIF0 0x00000008U
+#define DMA_LIFCR_CDMEIF0 0x00000004U
+#define DMA_LIFCR_CFEIF0 0x00000001U
+
+/******************** Bits definition for DMA_HIFCR register ****************/
+#define DMA_HIFCR_CTCIF7 0x08000000U
+#define DMA_HIFCR_CHTIF7 0x04000000U
+#define DMA_HIFCR_CTEIF7 0x02000000U
+#define DMA_HIFCR_CDMEIF7 0x01000000U
+#define DMA_HIFCR_CFEIF7 0x00400000U
+#define DMA_HIFCR_CTCIF6 0x00200000U
+#define DMA_HIFCR_CHTIF6 0x00100000U
+#define DMA_HIFCR_CTEIF6 0x00080000U
+#define DMA_HIFCR_CDMEIF6 0x00040000U
+#define DMA_HIFCR_CFEIF6 0x00010000U
+#define DMA_HIFCR_CTCIF5 0x00000800U
+#define DMA_HIFCR_CHTIF5 0x00000400U
+#define DMA_HIFCR_CTEIF5 0x00000200U
+#define DMA_HIFCR_CDMEIF5 0x00000100U
+#define DMA_HIFCR_CFEIF5 0x00000040U
+#define DMA_HIFCR_CTCIF4 0x00000020U
+#define DMA_HIFCR_CHTIF4 0x00000010U
+#define DMA_HIFCR_CTEIF4 0x00000008U
+#define DMA_HIFCR_CDMEIF4 0x00000004U
+#define DMA_HIFCR_CFEIF4 0x00000001U
+
+
+/******************************************************************************/
+/* */
+/* External Interrupt/Event Controller */
+/* */
+/******************************************************************************/
+/******************* Bit definition for EXTI_IMR register *******************/
+#define EXTI_IMR_MR0 0x00000001U /*!< Interrupt Mask on line 0 */
+#define EXTI_IMR_MR1 0x00000002U /*!< Interrupt Mask on line 1 */
+#define EXTI_IMR_MR2 0x00000004U /*!< Interrupt Mask on line 2 */
+#define EXTI_IMR_MR3 0x00000008U /*!< Interrupt Mask on line 3 */
+#define EXTI_IMR_MR4 0x00000010U /*!< Interrupt Mask on line 4 */
+#define EXTI_IMR_MR5 0x00000020U /*!< Interrupt Mask on line 5 */
+#define EXTI_IMR_MR6 0x00000040U /*!< Interrupt Mask on line 6 */
+#define EXTI_IMR_MR7 0x00000080U /*!< Interrupt Mask on line 7 */
+#define EXTI_IMR_MR8 0x00000100U /*!< Interrupt Mask on line 8 */
+#define EXTI_IMR_MR9 0x00000200U /*!< Interrupt Mask on line 9 */
+#define EXTI_IMR_MR10 0x00000400U /*!< Interrupt Mask on line 10 */
+#define EXTI_IMR_MR11 0x00000800U /*!< Interrupt Mask on line 11 */
+#define EXTI_IMR_MR12 0x00001000U /*!< Interrupt Mask on line 12 */
+#define EXTI_IMR_MR13 0x00002000U /*!< Interrupt Mask on line 13 */
+#define EXTI_IMR_MR14 0x00004000U /*!< Interrupt Mask on line 14 */
+#define EXTI_IMR_MR15 0x00008000U /*!< Interrupt Mask on line 15 */
+#define EXTI_IMR_MR16 0x00010000U /*!< Interrupt Mask on line 16 */
+#define EXTI_IMR_MR17 0x00020000U /*!< Interrupt Mask on line 17 */
+#define EXTI_IMR_MR18 0x00040000U /*!< Interrupt Mask on line 18 */
+#define EXTI_IMR_MR19 0x00080000U /*!< Interrupt Mask on line 19 */
+#define EXTI_IMR_MR20 0x00100000U /*!< Interrupt Mask on line 20 */
+#define EXTI_IMR_MR21 0x00200000U /*!< Interrupt Mask on line 21 */
+#define EXTI_IMR_MR22 0x00400000U /*!< Interrupt Mask on line 22 */
+
+/******************* Bit definition for EXTI_EMR register *******************/
+#define EXTI_EMR_MR0 0x00000001U /*!< Event Mask on line 0 */
+#define EXTI_EMR_MR1 0x00000002U /*!< Event Mask on line 1 */
+#define EXTI_EMR_MR2 0x00000004U /*!< Event Mask on line 2 */
+#define EXTI_EMR_MR3 0x00000008U /*!< Event Mask on line 3 */
+#define EXTI_EMR_MR4 0x00000010U /*!< Event Mask on line 4 */
+#define EXTI_EMR_MR5 0x00000020U /*!< Event Mask on line 5 */
+#define EXTI_EMR_MR6 0x00000040U /*!< Event Mask on line 6 */
+#define EXTI_EMR_MR7 0x00000080U /*!< Event Mask on line 7 */
+#define EXTI_EMR_MR8 0x00000100U /*!< Event Mask on line 8 */
+#define EXTI_EMR_MR9 0x00000200U /*!< Event Mask on line 9 */
+#define EXTI_EMR_MR10 0x00000400U /*!< Event Mask on line 10 */
+#define EXTI_EMR_MR11 0x00000800U /*!< Event Mask on line 11 */
+#define EXTI_EMR_MR12 0x00001000U /*!< Event Mask on line 12 */
+#define EXTI_EMR_MR13 0x00002000U /*!< Event Mask on line 13 */
+#define EXTI_EMR_MR14 0x00004000U /*!< Event Mask on line 14 */
+#define EXTI_EMR_MR15 0x00008000U /*!< Event Mask on line 15 */
+#define EXTI_EMR_MR16 0x00010000U /*!< Event Mask on line 16 */
+#define EXTI_EMR_MR17 0x00020000U /*!< Event Mask on line 17 */
+#define EXTI_EMR_MR18 0x00040000U /*!< Event Mask on line 18 */
+#define EXTI_EMR_MR19 0x00080000U /*!< Event Mask on line 19 */
+#define EXTI_EMR_MR20 0x00100000U /*!< Event Mask on line 20 */
+#define EXTI_EMR_MR21 0x00200000U /*!< Event Mask on line 21 */
+#define EXTI_EMR_MR22 0x00400000U /*!< Event Mask on line 22 */
+
+/****************** Bit definition for EXTI_RTSR register *******************/
+#define EXTI_RTSR_TR0 0x00000001U /*!< Rising trigger event configuration bit of line 0 */
+#define EXTI_RTSR_TR1 0x00000002U /*!< Rising trigger event configuration bit of line 1 */
+#define EXTI_RTSR_TR2 0x00000004U /*!< Rising trigger event configuration bit of line 2 */
+#define EXTI_RTSR_TR3 0x00000008U /*!< Rising trigger event configuration bit of line 3 */
+#define EXTI_RTSR_TR4 0x00000010U /*!< Rising trigger event configuration bit of line 4 */
+#define EXTI_RTSR_TR5 0x00000020U /*!< Rising trigger event configuration bit of line 5 */
+#define EXTI_RTSR_TR6 0x00000040U /*!< Rising trigger event configuration bit of line 6 */
+#define EXTI_RTSR_TR7 0x00000080U /*!< Rising trigger event configuration bit of line 7 */
+#define EXTI_RTSR_TR8 0x00000100U /*!< Rising trigger event configuration bit of line 8 */
+#define EXTI_RTSR_TR9 0x00000200U /*!< Rising trigger event configuration bit of line 9 */
+#define EXTI_RTSR_TR10 0x00000400U /*!< Rising trigger event configuration bit of line 10 */
+#define EXTI_RTSR_TR11 0x00000800U /*!< Rising trigger event configuration bit of line 11 */
+#define EXTI_RTSR_TR12 0x00001000U /*!< Rising trigger event configuration bit of line 12 */
+#define EXTI_RTSR_TR13 0x00002000U /*!< Rising trigger event configuration bit of line 13 */
+#define EXTI_RTSR_TR14 0x00004000U /*!< Rising trigger event configuration bit of line 14 */
+#define EXTI_RTSR_TR15 0x00008000U /*!< Rising trigger event configuration bit of line 15 */
+#define EXTI_RTSR_TR16 0x00010000U /*!< Rising trigger event configuration bit of line 16 */
+#define EXTI_RTSR_TR17 0x00020000U /*!< Rising trigger event configuration bit of line 17 */
+#define EXTI_RTSR_TR18 0x00040000U /*!< Rising trigger event configuration bit of line 18 */
+#define EXTI_RTSR_TR19 0x00080000U /*!< Rising trigger event configuration bit of line 19 */
+#define EXTI_RTSR_TR20 0x00100000U /*!< Rising trigger event configuration bit of line 20 */
+#define EXTI_RTSR_TR21 0x00200000U /*!< Rising trigger event configuration bit of line 21 */
+#define EXTI_RTSR_TR22 0x00400000U /*!< Rising trigger event configuration bit of line 22 */
+
+/****************** Bit definition for EXTI_FTSR register *******************/
+#define EXTI_FTSR_TR0 0x00000001U /*!< Falling trigger event configuration bit of line 0 */
+#define EXTI_FTSR_TR1 0x00000002U /*!< Falling trigger event configuration bit of line 1 */
+#define EXTI_FTSR_TR2 0x00000004U /*!< Falling trigger event configuration bit of line 2 */
+#define EXTI_FTSR_TR3 0x00000008U /*!< Falling trigger event configuration bit of line 3 */
+#define EXTI_FTSR_TR4 0x00000010U /*!< Falling trigger event configuration bit of line 4 */
+#define EXTI_FTSR_TR5 0x00000020U /*!< Falling trigger event configuration bit of line 5 */
+#define EXTI_FTSR_TR6 0x00000040U /*!< Falling trigger event configuration bit of line 6 */
+#define EXTI_FTSR_TR7 0x00000080U /*!< Falling trigger event configuration bit of line 7 */
+#define EXTI_FTSR_TR8 0x00000100U /*!< Falling trigger event configuration bit of line 8 */
+#define EXTI_FTSR_TR9 0x00000200U /*!< Falling trigger event configuration bit of line 9 */
+#define EXTI_FTSR_TR10 0x00000400U /*!< Falling trigger event configuration bit of line 10 */
+#define EXTI_FTSR_TR11 0x00000800U /*!< Falling trigger event configuration bit of line 11 */
+#define EXTI_FTSR_TR12 0x00001000U /*!< Falling trigger event configuration bit of line 12 */
+#define EXTI_FTSR_TR13 0x00002000U /*!< Falling trigger event configuration bit of line 13 */
+#define EXTI_FTSR_TR14 0x00004000U /*!< Falling trigger event configuration bit of line 14 */
+#define EXTI_FTSR_TR15 0x00008000U /*!< Falling trigger event configuration bit of line 15 */
+#define EXTI_FTSR_TR16 0x00010000U /*!< Falling trigger event configuration bit of line 16 */
+#define EXTI_FTSR_TR17 0x00020000U /*!< Falling trigger event configuration bit of line 17 */
+#define EXTI_FTSR_TR18 0x00040000U /*!< Falling trigger event configuration bit of line 18 */
+#define EXTI_FTSR_TR19 0x00080000U /*!< Falling trigger event configuration bit of line 19 */
+#define EXTI_FTSR_TR20 0x00100000U /*!< Falling trigger event configuration bit of line 20 */
+#define EXTI_FTSR_TR21 0x00200000U /*!< Falling trigger event configuration bit of line 21 */
+#define EXTI_FTSR_TR22 0x00400000U /*!< Falling trigger event configuration bit of line 22 */
+
+/****************** Bit definition for EXTI_SWIER register ******************/
+#define EXTI_SWIER_SWIER0 0x00000001U /*!< Software Interrupt on line 0 */
+#define EXTI_SWIER_SWIER1 0x00000002U /*!< Software Interrupt on line 1 */
+#define EXTI_SWIER_SWIER2 0x00000004U /*!< Software Interrupt on line 2 */
+#define EXTI_SWIER_SWIER3 0x00000008U /*!< Software Interrupt on line 3 */
+#define EXTI_SWIER_SWIER4 0x00000010U /*!< Software Interrupt on line 4 */
+#define EXTI_SWIER_SWIER5 0x00000020U /*!< Software Interrupt on line 5 */
+#define EXTI_SWIER_SWIER6 0x00000040U /*!< Software Interrupt on line 6 */
+#define EXTI_SWIER_SWIER7 0x00000080U /*!< Software Interrupt on line 7 */
+#define EXTI_SWIER_SWIER8 0x00000100U /*!< Software Interrupt on line 8 */
+#define EXTI_SWIER_SWIER9 0x00000200U /*!< Software Interrupt on line 9 */
+#define EXTI_SWIER_SWIER10 0x00000400U /*!< Software Interrupt on line 10 */
+#define EXTI_SWIER_SWIER11 0x00000800U /*!< Software Interrupt on line 11 */
+#define EXTI_SWIER_SWIER12 0x00001000U /*!< Software Interrupt on line 12 */
+#define EXTI_SWIER_SWIER13 0x00002000U /*!< Software Interrupt on line 13 */
+#define EXTI_SWIER_SWIER14 0x00004000U /*!< Software Interrupt on line 14 */
+#define EXTI_SWIER_SWIER15 0x00008000U /*!< Software Interrupt on line 15 */
+#define EXTI_SWIER_SWIER16 0x00010000U /*!< Software Interrupt on line 16 */
+#define EXTI_SWIER_SWIER17 0x00020000U /*!< Software Interrupt on line 17 */
+#define EXTI_SWIER_SWIER18 0x00040000U /*!< Software Interrupt on line 18 */
+#define EXTI_SWIER_SWIER19 0x00080000U /*!< Software Interrupt on line 19 */
+#define EXTI_SWIER_SWIER20 0x00100000U /*!< Software Interrupt on line 20 */
+#define EXTI_SWIER_SWIER21 0x00200000U /*!< Software Interrupt on line 21 */
+#define EXTI_SWIER_SWIER22 0x00400000U /*!< Software Interrupt on line 22 */
+
+/******************* Bit definition for EXTI_PR register ********************/
+#define EXTI_PR_PR0 0x00000001U /*!< Pending bit for line 0 */
+#define EXTI_PR_PR1 0x00000002U /*!< Pending bit for line 1 */
+#define EXTI_PR_PR2 0x00000004U /*!< Pending bit for line 2 */
+#define EXTI_PR_PR3 0x00000008U /*!< Pending bit for line 3 */
+#define EXTI_PR_PR4 0x00000010U /*!< Pending bit for line 4 */
+#define EXTI_PR_PR5 0x00000020U /*!< Pending bit for line 5 */
+#define EXTI_PR_PR6 0x00000040U /*!< Pending bit for line 6 */
+#define EXTI_PR_PR7 0x00000080U /*!< Pending bit for line 7 */
+#define EXTI_PR_PR8 0x00000100U /*!< Pending bit for line 8 */
+#define EXTI_PR_PR9 0x00000200U /*!< Pending bit for line 9 */
+#define EXTI_PR_PR10 0x00000400U /*!< Pending bit for line 10 */
+#define EXTI_PR_PR11 0x00000800U /*!< Pending bit for line 11 */
+#define EXTI_PR_PR12 0x00001000U /*!< Pending bit for line 12 */
+#define EXTI_PR_PR13 0x00002000U /*!< Pending bit for line 13 */
+#define EXTI_PR_PR14 0x00004000U /*!< Pending bit for line 14 */
+#define EXTI_PR_PR15 0x00008000U /*!< Pending bit for line 15 */
+#define EXTI_PR_PR16 0x00010000U /*!< Pending bit for line 16 */
+#define EXTI_PR_PR17 0x00020000U /*!< Pending bit for line 17 */
+#define EXTI_PR_PR18 0x00040000U /*!< Pending bit for line 18 */
+#define EXTI_PR_PR19 0x00080000U /*!< Pending bit for line 19 */
+#define EXTI_PR_PR20 0x00100000U /*!< Pending bit for line 20 */
+#define EXTI_PR_PR21 0x00200000U /*!< Pending bit for line 21 */
+#define EXTI_PR_PR22 0x00400000U /*!< Pending bit for line 22 */
+
+/******************************************************************************/
+/* */
+/* FLASH */
+/* */
+/******************************************************************************/
+/******************* Bits definition for FLASH_ACR register *****************/
+#define FLASH_ACR_LATENCY 0x0000000FU
+#define FLASH_ACR_LATENCY_0WS 0x00000000U
+#define FLASH_ACR_LATENCY_1WS 0x00000001U
+#define FLASH_ACR_LATENCY_2WS 0x00000002U
+#define FLASH_ACR_LATENCY_3WS 0x00000003U
+#define FLASH_ACR_LATENCY_4WS 0x00000004U
+#define FLASH_ACR_LATENCY_5WS 0x00000005U
+#define FLASH_ACR_LATENCY_6WS 0x00000006U
+#define FLASH_ACR_LATENCY_7WS 0x00000007U
+
+#define FLASH_ACR_PRFTEN 0x00000100U
+#define FLASH_ACR_ICEN 0x00000200U
+#define FLASH_ACR_DCEN 0x00000400U
+#define FLASH_ACR_ICRST 0x00000800U
+#define FLASH_ACR_DCRST 0x00001000U
+#define FLASH_ACR_BYTE0_ADDRESS 0x40023C00U
+#define FLASH_ACR_BYTE2_ADDRESS 0x40023C03U
+
+/******************* Bits definition for FLASH_SR register ******************/
+#define FLASH_SR_EOP 0x00000001U
+#define FLASH_SR_SOP 0x00000002U
+#define FLASH_SR_WRPERR 0x00000010U
+#define FLASH_SR_PGAERR 0x00000020U
+#define FLASH_SR_PGPERR 0x00000040U
+#define FLASH_SR_PGSERR 0x00000080U
+#define FLASH_SR_BSY 0x00010000U
+
+/******************* Bits definition for FLASH_CR register ******************/
+#define FLASH_CR_PG 0x00000001U
+#define FLASH_CR_SER 0x00000002U
+#define FLASH_CR_MER 0x00000004U
+#define FLASH_CR_SNB 0x000000F8U
+#define FLASH_CR_SNB_0 0x00000008U
+#define FLASH_CR_SNB_1 0x00000010U
+#define FLASH_CR_SNB_2 0x00000020U
+#define FLASH_CR_SNB_3 0x00000040U
+#define FLASH_CR_SNB_4 0x00000080U
+#define FLASH_CR_PSIZE 0x00000300U
+#define FLASH_CR_PSIZE_0 0x00000100U
+#define FLASH_CR_PSIZE_1 0x00000200U
+#define FLASH_CR_STRT 0x00010000U
+#define FLASH_CR_EOPIE 0x01000000U
+#define FLASH_CR_LOCK 0x80000000U
+
+/******************* Bits definition for FLASH_OPTCR register ***************/
+#define FLASH_OPTCR_OPTLOCK 0x00000001U
+#define FLASH_OPTCR_OPTSTRT 0x00000002U
+#define FLASH_OPTCR_BOR_LEV_0 0x00000004U
+#define FLASH_OPTCR_BOR_LEV_1 0x00000008U
+#define FLASH_OPTCR_BOR_LEV 0x0000000CU
+
+#define FLASH_OPTCR_WDG_SW 0x00000020U
+#define FLASH_OPTCR_nRST_STOP 0x00000040U
+#define FLASH_OPTCR_nRST_STDBY 0x00000080U
+#define FLASH_OPTCR_RDP 0x0000FF00U
+#define FLASH_OPTCR_RDP_0 0x00000100U
+#define FLASH_OPTCR_RDP_1 0x00000200U
+#define FLASH_OPTCR_RDP_2 0x00000400U
+#define FLASH_OPTCR_RDP_3 0x00000800U
+#define FLASH_OPTCR_RDP_4 0x00001000U
+#define FLASH_OPTCR_RDP_5 0x00002000U
+#define FLASH_OPTCR_RDP_6 0x00004000U
+#define FLASH_OPTCR_RDP_7 0x00008000U
+#define FLASH_OPTCR_nWRP 0x0FFF0000U
+#define FLASH_OPTCR_nWRP_0 0x00010000U
+#define FLASH_OPTCR_nWRP_1 0x00020000U
+#define FLASH_OPTCR_nWRP_2 0x00040000U
+#define FLASH_OPTCR_nWRP_3 0x00080000U
+#define FLASH_OPTCR_nWRP_4 0x00100000U
+#define FLASH_OPTCR_nWRP_5 0x00200000U
+#define FLASH_OPTCR_nWRP_6 0x00400000U
+#define FLASH_OPTCR_nWRP_7 0x00800000U
+#define FLASH_OPTCR_nWRP_8 0x01000000U
+#define FLASH_OPTCR_nWRP_9 0x02000000U
+#define FLASH_OPTCR_nWRP_10 0x04000000U
+#define FLASH_OPTCR_nWRP_11 0x08000000U
+
+/****************** Bits definition for FLASH_OPTCR1 register ***************/
+#define FLASH_OPTCR1_nWRP 0x0FFF0000U
+#define FLASH_OPTCR1_nWRP_0 0x00010000U
+#define FLASH_OPTCR1_nWRP_1 0x00020000U
+#define FLASH_OPTCR1_nWRP_2 0x00040000U
+#define FLASH_OPTCR1_nWRP_3 0x00080000U
+#define FLASH_OPTCR1_nWRP_4 0x00100000U
+#define FLASH_OPTCR1_nWRP_5 0x00200000U
+#define FLASH_OPTCR1_nWRP_6 0x00400000U
+#define FLASH_OPTCR1_nWRP_7 0x00800000U
+#define FLASH_OPTCR1_nWRP_8 0x01000000U
+#define FLASH_OPTCR1_nWRP_9 0x02000000U
+#define FLASH_OPTCR1_nWRP_10 0x04000000U
+#define FLASH_OPTCR1_nWRP_11 0x08000000U
+
+/******************************************************************************/
+/* */
+/* General Purpose I/O */
+/* */
+/******************************************************************************/
+/****************** Bits definition for GPIO_MODER register *****************/
+#define GPIO_MODER_MODER0 0x00000003U
+#define GPIO_MODER_MODER0_0 0x00000001U
+#define GPIO_MODER_MODER0_1 0x00000002U
+
+#define GPIO_MODER_MODER1 0x0000000CU
+#define GPIO_MODER_MODER1_0 0x00000004U
+#define GPIO_MODER_MODER1_1 0x00000008U
+
+#define GPIO_MODER_MODER2 0x00000030U
+#define GPIO_MODER_MODER2_0 0x00000010U
+#define GPIO_MODER_MODER2_1 0x00000020U
+
+#define GPIO_MODER_MODER3 0x000000C0U
+#define GPIO_MODER_MODER3_0 0x00000040U
+#define GPIO_MODER_MODER3_1 0x00000080U
+
+#define GPIO_MODER_MODER4 0x00000300U
+#define GPIO_MODER_MODER4_0 0x00000100U
+#define GPIO_MODER_MODER4_1 0x00000200U
+
+#define GPIO_MODER_MODER5 0x00000C00U
+#define GPIO_MODER_MODER5_0 0x00000400U
+#define GPIO_MODER_MODER5_1 0x00000800U
+
+#define GPIO_MODER_MODER6 0x00003000U
+#define GPIO_MODER_MODER6_0 0x00001000U
+#define GPIO_MODER_MODER6_1 0x00002000U
+
+#define GPIO_MODER_MODER7 0x0000C000U
+#define GPIO_MODER_MODER7_0 0x00004000U
+#define GPIO_MODER_MODER7_1 0x00008000U
+
+#define GPIO_MODER_MODER8 0x00030000U
+#define GPIO_MODER_MODER8_0 0x00010000U
+#define GPIO_MODER_MODER8_1 0x00020000U
+
+#define GPIO_MODER_MODER9 0x000C0000U
+#define GPIO_MODER_MODER9_0 0x00040000U
+#define GPIO_MODER_MODER9_1 0x00080000U
+
+#define GPIO_MODER_MODER10 0x00300000U
+#define GPIO_MODER_MODER10_0 0x00100000U
+#define GPIO_MODER_MODER10_1 0x00200000U
+
+#define GPIO_MODER_MODER11 0x00C00000U
+#define GPIO_MODER_MODER11_0 0x00400000U
+#define GPIO_MODER_MODER11_1 0x00800000U
+
+#define GPIO_MODER_MODER12 0x03000000U
+#define GPIO_MODER_MODER12_0 0x01000000U
+#define GPIO_MODER_MODER12_1 0x02000000U
+
+#define GPIO_MODER_MODER13 0x0C000000U
+#define GPIO_MODER_MODER13_0 0x04000000U
+#define GPIO_MODER_MODER13_1 0x08000000U
+
+#define GPIO_MODER_MODER14 0x30000000U
+#define GPIO_MODER_MODER14_0 0x10000000U
+#define GPIO_MODER_MODER14_1 0x20000000U
+
+#define GPIO_MODER_MODER15 0xC0000000U
+#define GPIO_MODER_MODER15_0 0x40000000U
+#define GPIO_MODER_MODER15_1 0x80000000U
+
+/****************** Bits definition for GPIO_OTYPER register ****************/
+#define GPIO_OTYPER_OT_0 0x00000001U
+#define GPIO_OTYPER_OT_1 0x00000002U
+#define GPIO_OTYPER_OT_2 0x00000004U
+#define GPIO_OTYPER_OT_3 0x00000008U
+#define GPIO_OTYPER_OT_4 0x00000010U
+#define GPIO_OTYPER_OT_5 0x00000020U
+#define GPIO_OTYPER_OT_6 0x00000040U
+#define GPIO_OTYPER_OT_7 0x00000080U
+#define GPIO_OTYPER_OT_8 0x00000100U
+#define GPIO_OTYPER_OT_9 0x00000200U
+#define GPIO_OTYPER_OT_10 0x00000400U
+#define GPIO_OTYPER_OT_11 0x00000800U
+#define GPIO_OTYPER_OT_12 0x00001000U
+#define GPIO_OTYPER_OT_13 0x00002000U
+#define GPIO_OTYPER_OT_14 0x00004000U
+#define GPIO_OTYPER_OT_15 0x00008000U
+
+/****************** Bits definition for GPIO_OSPEEDR register ***************/
+#define GPIO_OSPEEDER_OSPEEDR0 0x00000003U
+#define GPIO_OSPEEDER_OSPEEDR0_0 0x00000001U
+#define GPIO_OSPEEDER_OSPEEDR0_1 0x00000002U
+
+#define GPIO_OSPEEDER_OSPEEDR1 0x0000000CU
+#define GPIO_OSPEEDER_OSPEEDR1_0 0x00000004U
+#define GPIO_OSPEEDER_OSPEEDR1_1 0x00000008U
+
+#define GPIO_OSPEEDER_OSPEEDR2 0x00000030U
+#define GPIO_OSPEEDER_OSPEEDR2_0 0x00000010U
+#define GPIO_OSPEEDER_OSPEEDR2_1 0x00000020U
+
+#define GPIO_OSPEEDER_OSPEEDR3 0x000000C0U
+#define GPIO_OSPEEDER_OSPEEDR3_0 0x00000040U
+#define GPIO_OSPEEDER_OSPEEDR3_1 0x00000080U
+
+#define GPIO_OSPEEDER_OSPEEDR4 0x00000300U
+#define GPIO_OSPEEDER_OSPEEDR4_0 0x00000100U
+#define GPIO_OSPEEDER_OSPEEDR4_1 0x00000200U
+
+#define GPIO_OSPEEDER_OSPEEDR5 0x00000C00U
+#define GPIO_OSPEEDER_OSPEEDR5_0 0x00000400U
+#define GPIO_OSPEEDER_OSPEEDR5_1 0x00000800U
+
+#define GPIO_OSPEEDER_OSPEEDR6 0x00003000U
+#define GPIO_OSPEEDER_OSPEEDR6_0 0x00001000U
+#define GPIO_OSPEEDER_OSPEEDR6_1 0x00002000U
+
+#define GPIO_OSPEEDER_OSPEEDR7 0x0000C000U
+#define GPIO_OSPEEDER_OSPEEDR7_0 0x00004000U
+#define GPIO_OSPEEDER_OSPEEDR7_1 0x00008000U
+
+#define GPIO_OSPEEDER_OSPEEDR8 0x00030000U
+#define GPIO_OSPEEDER_OSPEEDR8_0 0x00010000U
+#define GPIO_OSPEEDER_OSPEEDR8_1 0x00020000U
+
+#define GPIO_OSPEEDER_OSPEEDR9 0x000C0000U
+#define GPIO_OSPEEDER_OSPEEDR9_0 0x00040000U
+#define GPIO_OSPEEDER_OSPEEDR9_1 0x00080000U
+
+#define GPIO_OSPEEDER_OSPEEDR10 0x00300000U
+#define GPIO_OSPEEDER_OSPEEDR10_0 0x00100000U
+#define GPIO_OSPEEDER_OSPEEDR10_1 0x00200000U
+
+#define GPIO_OSPEEDER_OSPEEDR11 0x00C00000U
+#define GPIO_OSPEEDER_OSPEEDR11_0 0x00400000U
+#define GPIO_OSPEEDER_OSPEEDR11_1 0x00800000U
+
+#define GPIO_OSPEEDER_OSPEEDR12 0x03000000U
+#define GPIO_OSPEEDER_OSPEEDR12_0 0x01000000U
+#define GPIO_OSPEEDER_OSPEEDR12_1 0x02000000U
+
+#define GPIO_OSPEEDER_OSPEEDR13 0x0C000000U
+#define GPIO_OSPEEDER_OSPEEDR13_0 0x04000000U
+#define GPIO_OSPEEDER_OSPEEDR13_1 0x08000000U
+
+#define GPIO_OSPEEDER_OSPEEDR14 0x30000000U
+#define GPIO_OSPEEDER_OSPEEDR14_0 0x10000000U
+#define GPIO_OSPEEDER_OSPEEDR14_1 0x20000000U
+
+#define GPIO_OSPEEDER_OSPEEDR15 0xC0000000U
+#define GPIO_OSPEEDER_OSPEEDR15_0 0x40000000U
+#define GPIO_OSPEEDER_OSPEEDR15_1 0x80000000U
+
+/****************** Bits definition for GPIO_PUPDR register *****************/
+#define GPIO_PUPDR_PUPDR0 0x00000003U
+#define GPIO_PUPDR_PUPDR0_0 0x00000001U
+#define GPIO_PUPDR_PUPDR0_1 0x00000002U
+
+#define GPIO_PUPDR_PUPDR1 0x0000000CU
+#define GPIO_PUPDR_PUPDR1_0 0x00000004U
+#define GPIO_PUPDR_PUPDR1_1 0x00000008U
+
+#define GPIO_PUPDR_PUPDR2 0x00000030U
+#define GPIO_PUPDR_PUPDR2_0 0x00000010U
+#define GPIO_PUPDR_PUPDR2_1 0x00000020U
+
+#define GPIO_PUPDR_PUPDR3 0x000000C0U
+#define GPIO_PUPDR_PUPDR3_0 0x00000040U
+#define GPIO_PUPDR_PUPDR3_1 0x00000080U
+
+#define GPIO_PUPDR_PUPDR4 0x00000300U
+#define GPIO_PUPDR_PUPDR4_0 0x00000100U
+#define GPIO_PUPDR_PUPDR4_1 0x00000200U
+
+#define GPIO_PUPDR_PUPDR5 0x00000C00U
+#define GPIO_PUPDR_PUPDR5_0 0x00000400U
+#define GPIO_PUPDR_PUPDR5_1 0x00000800U
+
+#define GPIO_PUPDR_PUPDR6 0x00003000U
+#define GPIO_PUPDR_PUPDR6_0 0x00001000U
+#define GPIO_PUPDR_PUPDR6_1 0x00002000U
+
+#define GPIO_PUPDR_PUPDR7 0x0000C000U
+#define GPIO_PUPDR_PUPDR7_0 0x00004000U
+#define GPIO_PUPDR_PUPDR7_1 0x00008000U
+
+#define GPIO_PUPDR_PUPDR8 0x00030000U
+#define GPIO_PUPDR_PUPDR8_0 0x00010000U
+#define GPIO_PUPDR_PUPDR8_1 0x00020000U
+
+#define GPIO_PUPDR_PUPDR9 0x000C0000U
+#define GPIO_PUPDR_PUPDR9_0 0x00040000U
+#define GPIO_PUPDR_PUPDR9_1 0x00080000U
+
+#define GPIO_PUPDR_PUPDR10 0x00300000U
+#define GPIO_PUPDR_PUPDR10_0 0x00100000U
+#define GPIO_PUPDR_PUPDR10_1 0x00200000U
+
+#define GPIO_PUPDR_PUPDR11 0x00C00000U
+#define GPIO_PUPDR_PUPDR11_0 0x00400000U
+#define GPIO_PUPDR_PUPDR11_1 0x00800000U
+
+#define GPIO_PUPDR_PUPDR12 0x03000000U
+#define GPIO_PUPDR_PUPDR12_0 0x01000000U
+#define GPIO_PUPDR_PUPDR12_1 0x02000000U
+
+#define GPIO_PUPDR_PUPDR13 0x0C000000U
+#define GPIO_PUPDR_PUPDR13_0 0x04000000U
+#define GPIO_PUPDR_PUPDR13_1 0x08000000U
+
+#define GPIO_PUPDR_PUPDR14 0x30000000U
+#define GPIO_PUPDR_PUPDR14_0 0x10000000U
+#define GPIO_PUPDR_PUPDR14_1 0x20000000U
+
+#define GPIO_PUPDR_PUPDR15 0xC0000000U
+#define GPIO_PUPDR_PUPDR15_0 0x40000000U
+#define GPIO_PUPDR_PUPDR15_1 0x80000000U
+
+/****************** Bits definition for GPIO_IDR register *******************/
+#define GPIO_IDR_IDR_0 0x00000001U
+#define GPIO_IDR_IDR_1 0x00000002U
+#define GPIO_IDR_IDR_2 0x00000004U
+#define GPIO_IDR_IDR_3 0x00000008U
+#define GPIO_IDR_IDR_4 0x00000010U
+#define GPIO_IDR_IDR_5 0x00000020U
+#define GPIO_IDR_IDR_6 0x00000040U
+#define GPIO_IDR_IDR_7 0x00000080U
+#define GPIO_IDR_IDR_8 0x00000100U
+#define GPIO_IDR_IDR_9 0x00000200U
+#define GPIO_IDR_IDR_10 0x00000400U
+#define GPIO_IDR_IDR_11 0x00000800U
+#define GPIO_IDR_IDR_12 0x00001000U
+#define GPIO_IDR_IDR_13 0x00002000U
+#define GPIO_IDR_IDR_14 0x00004000U
+#define GPIO_IDR_IDR_15 0x00008000U
+/* Old GPIO_IDR register bits definition, maintained for legacy purpose */
+#define GPIO_OTYPER_IDR_0 GPIO_IDR_IDR_0
+#define GPIO_OTYPER_IDR_1 GPIO_IDR_IDR_1
+#define GPIO_OTYPER_IDR_2 GPIO_IDR_IDR_2
+#define GPIO_OTYPER_IDR_3 GPIO_IDR_IDR_3
+#define GPIO_OTYPER_IDR_4 GPIO_IDR_IDR_4
+#define GPIO_OTYPER_IDR_5 GPIO_IDR_IDR_5
+#define GPIO_OTYPER_IDR_6 GPIO_IDR_IDR_6
+#define GPIO_OTYPER_IDR_7 GPIO_IDR_IDR_7
+#define GPIO_OTYPER_IDR_8 GPIO_IDR_IDR_8
+#define GPIO_OTYPER_IDR_9 GPIO_IDR_IDR_9
+#define GPIO_OTYPER_IDR_10 GPIO_IDR_IDR_10
+#define GPIO_OTYPER_IDR_11 GPIO_IDR_IDR_11
+#define GPIO_OTYPER_IDR_12 GPIO_IDR_IDR_12
+#define GPIO_OTYPER_IDR_13 GPIO_IDR_IDR_13
+#define GPIO_OTYPER_IDR_14 GPIO_IDR_IDR_14
+#define GPIO_OTYPER_IDR_15 GPIO_IDR_IDR_15
+
+/****************** Bits definition for GPIO_ODR register *******************/
+#define GPIO_ODR_ODR_0 0x00000001U
+#define GPIO_ODR_ODR_1 0x00000002U
+#define GPIO_ODR_ODR_2 0x00000004U
+#define GPIO_ODR_ODR_3 0x00000008U
+#define GPIO_ODR_ODR_4 0x00000010U
+#define GPIO_ODR_ODR_5 0x00000020U
+#define GPIO_ODR_ODR_6 0x00000040U
+#define GPIO_ODR_ODR_7 0x00000080U
+#define GPIO_ODR_ODR_8 0x00000100U
+#define GPIO_ODR_ODR_9 0x00000200U
+#define GPIO_ODR_ODR_10 0x00000400U
+#define GPIO_ODR_ODR_11 0x00000800U
+#define GPIO_ODR_ODR_12 0x00001000U
+#define GPIO_ODR_ODR_13 0x00002000U
+#define GPIO_ODR_ODR_14 0x00004000U
+#define GPIO_ODR_ODR_15 0x00008000U
+/* Old GPIO_ODR register bits definition, maintained for legacy purpose */
+#define GPIO_OTYPER_ODR_0 GPIO_ODR_ODR_0
+#define GPIO_OTYPER_ODR_1 GPIO_ODR_ODR_1
+#define GPIO_OTYPER_ODR_2 GPIO_ODR_ODR_2
+#define GPIO_OTYPER_ODR_3 GPIO_ODR_ODR_3
+#define GPIO_OTYPER_ODR_4 GPIO_ODR_ODR_4
+#define GPIO_OTYPER_ODR_5 GPIO_ODR_ODR_5
+#define GPIO_OTYPER_ODR_6 GPIO_ODR_ODR_6
+#define GPIO_OTYPER_ODR_7 GPIO_ODR_ODR_7
+#define GPIO_OTYPER_ODR_8 GPIO_ODR_ODR_8
+#define GPIO_OTYPER_ODR_9 GPIO_ODR_ODR_9
+#define GPIO_OTYPER_ODR_10 GPIO_ODR_ODR_10
+#define GPIO_OTYPER_ODR_11 GPIO_ODR_ODR_11
+#define GPIO_OTYPER_ODR_12 GPIO_ODR_ODR_12
+#define GPIO_OTYPER_ODR_13 GPIO_ODR_ODR_13
+#define GPIO_OTYPER_ODR_14 GPIO_ODR_ODR_14
+#define GPIO_OTYPER_ODR_15 GPIO_ODR_ODR_15
+
+/****************** Bits definition for GPIO_BSRR register ******************/
+#define GPIO_BSRR_BS_0 0x00000001U
+#define GPIO_BSRR_BS_1 0x00000002U
+#define GPIO_BSRR_BS_2 0x00000004U
+#define GPIO_BSRR_BS_3 0x00000008U
+#define GPIO_BSRR_BS_4 0x00000010U
+#define GPIO_BSRR_BS_5 0x00000020U
+#define GPIO_BSRR_BS_6 0x00000040U
+#define GPIO_BSRR_BS_7 0x00000080U
+#define GPIO_BSRR_BS_8 0x00000100U
+#define GPIO_BSRR_BS_9 0x00000200U
+#define GPIO_BSRR_BS_10 0x00000400U
+#define GPIO_BSRR_BS_11 0x00000800U
+#define GPIO_BSRR_BS_12 0x00001000U
+#define GPIO_BSRR_BS_13 0x00002000U
+#define GPIO_BSRR_BS_14 0x00004000U
+#define GPIO_BSRR_BS_15 0x00008000U
+#define GPIO_BSRR_BR_0 0x00010000U
+#define GPIO_BSRR_BR_1 0x00020000U
+#define GPIO_BSRR_BR_2 0x00040000U
+#define GPIO_BSRR_BR_3 0x00080000U
+#define GPIO_BSRR_BR_4 0x00100000U
+#define GPIO_BSRR_BR_5 0x00200000U
+#define GPIO_BSRR_BR_6 0x00400000U
+#define GPIO_BSRR_BR_7 0x00800000U
+#define GPIO_BSRR_BR_8 0x01000000U
+#define GPIO_BSRR_BR_9 0x02000000U
+#define GPIO_BSRR_BR_10 0x04000000U
+#define GPIO_BSRR_BR_11 0x08000000U
+#define GPIO_BSRR_BR_12 0x10000000U
+#define GPIO_BSRR_BR_13 0x20000000U
+#define GPIO_BSRR_BR_14 0x40000000U
+#define GPIO_BSRR_BR_15 0x80000000U
+
+/****************** Bit definition for GPIO_LCKR register ********************/
+#define GPIO_LCKR_LCK0 0x00000001U
+#define GPIO_LCKR_LCK1 0x00000002U
+#define GPIO_LCKR_LCK2 0x00000004U
+#define GPIO_LCKR_LCK3 0x00000008U
+#define GPIO_LCKR_LCK4 0x00000010U
+#define GPIO_LCKR_LCK5 0x00000020U
+#define GPIO_LCKR_LCK6 0x00000040U
+#define GPIO_LCKR_LCK7 0x00000080U
+#define GPIO_LCKR_LCK8 0x00000100U
+#define GPIO_LCKR_LCK9 0x00000200U
+#define GPIO_LCKR_LCK10 0x00000400U
+#define GPIO_LCKR_LCK11 0x00000800U
+#define GPIO_LCKR_LCK12 0x00001000U
+#define GPIO_LCKR_LCK13 0x00002000U
+#define GPIO_LCKR_LCK14 0x00004000U
+#define GPIO_LCKR_LCK15 0x00008000U
+#define GPIO_LCKR_LCKK 0x00010000U
+
+/******************************************************************************/
+/* */
+/* Inter-integrated Circuit Interface */
+/* */
+/******************************************************************************/
+/******************* Bit definition for I2C_CR1 register ********************/
+#define I2C_CR1_PE 0x00000001U /*!<Peripheral Enable */
+#define I2C_CR1_SMBUS 0x00000002U /*!<SMBus Mode */
+#define I2C_CR1_SMBTYPE 0x00000008U /*!<SMBus Type */
+#define I2C_CR1_ENARP 0x00000010U /*!<ARP Enable */
+#define I2C_CR1_ENPEC 0x00000020U /*!<PEC Enable */
+#define I2C_CR1_ENGC 0x00000040U /*!<General Call Enable */
+#define I2C_CR1_NOSTRETCH 0x00000080U /*!<Clock Stretching Disable (Slave mode) */
+#define I2C_CR1_START 0x00000100U /*!<Start Generation */
+#define I2C_CR1_STOP 0x00000200U /*!<Stop Generation */
+#define I2C_CR1_ACK 0x00000400U /*!<Acknowledge Enable */
+#define I2C_CR1_POS 0x00000800U /*!<Acknowledge/PEC Position (for data reception) */
+#define I2C_CR1_PEC 0x00001000U /*!<Packet Error Checking */
+#define I2C_CR1_ALERT 0x00002000U /*!<SMBus Alert */
+#define I2C_CR1_SWRST 0x00008000U /*!<Software Reset */
+
+/******************* Bit definition for I2C_CR2 register ********************/
+#define I2C_CR2_FREQ 0x0000003FU /*!<FREQ[5:0] bits (Peripheral Clock Frequency) */
+#define I2C_CR2_FREQ_0 0x00000001U /*!<Bit 0 */
+#define I2C_CR2_FREQ_1 0x00000002U /*!<Bit 1 */
+#define I2C_CR2_FREQ_2 0x00000004U /*!<Bit 2 */
+#define I2C_CR2_FREQ_3 0x00000008U /*!<Bit 3 */
+#define I2C_CR2_FREQ_4 0x00000010U /*!<Bit 4 */
+#define I2C_CR2_FREQ_5 0x00000020U /*!<Bit 5 */
+
+#define I2C_CR2_ITERREN 0x00000100U /*!<Error Interrupt Enable */
+#define I2C_CR2_ITEVTEN 0x00000200U /*!<Event Interrupt Enable */
+#define I2C_CR2_ITBUFEN 0x00000400U /*!<Buffer Interrupt Enable */
+#define I2C_CR2_DMAEN 0x00000800U /*!<DMA Requests Enable */
+#define I2C_CR2_LAST 0x00001000U /*!<DMA Last Transfer */
+
+/******************* Bit definition for I2C_OAR1 register *******************/
+#define I2C_OAR1_ADD1_7 0x000000FEU /*!<Interface Address */
+#define I2C_OAR1_ADD8_9 0x00000300U /*!<Interface Address */
+
+#define I2C_OAR1_ADD0 0x00000001U /*!<Bit 0 */
+#define I2C_OAR1_ADD1 0x00000002U /*!<Bit 1 */
+#define I2C_OAR1_ADD2 0x00000004U /*!<Bit 2 */
+#define I2C_OAR1_ADD3 0x00000008U /*!<Bit 3 */
+#define I2C_OAR1_ADD4 0x00000010U /*!<Bit 4 */
+#define I2C_OAR1_ADD5 0x00000020U /*!<Bit 5 */
+#define I2C_OAR1_ADD6 0x00000040U /*!<Bit 6 */
+#define I2C_OAR1_ADD7 0x00000080U /*!<Bit 7 */
+#define I2C_OAR1_ADD8 0x00000100U /*!<Bit 8 */
+#define I2C_OAR1_ADD9 0x00000200U /*!<Bit 9 */
+
+#define I2C_OAR1_ADDMODE 0x00008000U /*!<Addressing Mode (Slave mode) */
+
+/******************* Bit definition for I2C_OAR2 register *******************/
+#define I2C_OAR2_ENDUAL 0x00000001U /*!<Dual addressing mode enable */
+#define I2C_OAR2_ADD2 0x000000FEU /*!<Interface address */
+
+/******************** Bit definition for I2C_DR register ********************/
+#define I2C_DR_DR 0x000000FFU /*!<8-bit Data Register */
+
+/******************* Bit definition for I2C_SR1 register ********************/
+#define I2C_SR1_SB 0x00000001U /*!<Start Bit (Master mode) */
+#define I2C_SR1_ADDR 0x00000002U /*!<Address sent (master mode)/matched (slave mode) */
+#define I2C_SR1_BTF 0x00000004U /*!<Byte Transfer Finished */
+#define I2C_SR1_ADD10 0x00000008U /*!<10-bit header sent (Master mode) */
+#define I2C_SR1_STOPF 0x00000010U /*!<Stop detection (Slave mode) */
+#define I2C_SR1_RXNE 0x00000040U /*!<Data Register not Empty (receivers) */
+#define I2C_SR1_TXE 0x00000080U /*!<Data Register Empty (transmitters) */
+#define I2C_SR1_BERR 0x00000100U /*!<Bus Error */
+#define I2C_SR1_ARLO 0x00000200U /*!<Arbitration Lost (master mode) */
+#define I2C_SR1_AF 0x00000400U /*!<Acknowledge Failure */
+#define I2C_SR1_OVR 0x00000800U /*!<Overrun/Underrun */
+#define I2C_SR1_PECERR 0x00001000U /*!<PEC Error in reception */
+#define I2C_SR1_TIMEOUT 0x00004000U /*!<Timeout or Tlow Error */
+#define I2C_SR1_SMBALERT 0x00008000U /*!<SMBus Alert */
+
+/******************* Bit definition for I2C_SR2 register ********************/
+#define I2C_SR2_MSL 0x00000001U /*!<Master/Slave */
+#define I2C_SR2_BUSY 0x00000002U /*!<Bus Busy */
+#define I2C_SR2_TRA 0x00000004U /*!<Transmitter/Receiver */
+#define I2C_SR2_GENCALL 0x00000010U /*!<General Call Address (Slave mode) */
+#define I2C_SR2_SMBDEFAULT 0x00000020U /*!<SMBus Device Default Address (Slave mode) */
+#define I2C_SR2_SMBHOST 0x00000040U /*!<SMBus Host Header (Slave mode) */
+#define I2C_SR2_DUALF 0x00000080U /*!<Dual Flag (Slave mode) */
+#define I2C_SR2_PEC 0x0000FF00U /*!<Packet Error Checking Register */
+
+/******************* Bit definition for I2C_CCR register ********************/
+#define I2C_CCR_CCR 0x00000FFFU /*!<Clock Control Register in Fast/Standard mode (Master mode) */
+#define I2C_CCR_DUTY 0x00004000U /*!<Fast Mode Duty Cycle */
+#define I2C_CCR_FS 0x00008000U /*!<I2C Master Mode Selection */
+
+/****************** Bit definition for I2C_TRISE register *******************/
+#define I2C_TRISE_TRISE 0x0000003FU /*!<Maximum Rise Time in Fast/Standard mode (Master mode) */
+
+/****************** Bit definition for I2C_FLTR register *******************/
+#define I2C_FLTR_DNF 0x0000000FU /*!<Digital Noise Filter */
+#define I2C_FLTR_ANOFF 0x00000010U /*!<Analog Noise Filter OFF */
+
+/******************************************************************************/
+/* */
+/* Independent WATCHDOG */
+/* */
+/******************************************************************************/
+/******************* Bit definition for IWDG_KR register ********************/
+#define IWDG_KR_KEY 0xFFFFU /*!<Key value (write only, read 0000h) */
+
+/******************* Bit definition for IWDG_PR register ********************/
+#define IWDG_PR_PR 0x07U /*!<PR[2:0] (Prescaler divider) */
+#define IWDG_PR_PR_0 0x01U /*!<Bit 0 */
+#define IWDG_PR_PR_1 0x02U /*!<Bit 1 */
+#define IWDG_PR_PR_2 0x04U /*!<Bit 2 */
+
+/******************* Bit definition for IWDG_RLR register *******************/
+#define IWDG_RLR_RL 0x0FFFU /*!<Watchdog counter reload value */
+
+/******************* Bit definition for IWDG_SR register ********************/
+#define IWDG_SR_PVU 0x01U /*!<Watchdog prescaler value update */
+#define IWDG_SR_RVU 0x02U /*!<Watchdog counter reload value update */
+
+
+/******************************************************************************/
+/* */
+/* Power Control */
+/* */
+/******************************************************************************/
+/******************** Bit definition for PWR_CR register ********************/
+#define PWR_CR_LPDS 0x00000001U /*!< Low-Power Deepsleep */
+#define PWR_CR_PDDS 0x00000002U /*!< Power Down Deepsleep */
+#define PWR_CR_CWUF 0x00000004U /*!< Clear Wakeup Flag */
+#define PWR_CR_CSBF 0x00000008U /*!< Clear Standby Flag */
+#define PWR_CR_PVDE 0x00000010U /*!< Power Voltage Detector Enable */
+
+#define PWR_CR_PLS 0x000000E0U /*!< PLS[2:0] bits (PVD Level Selection) */
+#define PWR_CR_PLS_0 0x00000020U /*!< Bit 0 */
+#define PWR_CR_PLS_1 0x00000040U /*!< Bit 1 */
+#define PWR_CR_PLS_2 0x00000080U /*!< Bit 2 */
+
+/*!< PVD level configuration */
+#define PWR_CR_PLS_LEV0 0x00000000U /*!< PVD level 0 */
+#define PWR_CR_PLS_LEV1 0x00000020U /*!< PVD level 1 */
+#define PWR_CR_PLS_LEV2 0x00000040U /*!< PVD level 2 */
+#define PWR_CR_PLS_LEV3 0x00000060U /*!< PVD level 3 */
+#define PWR_CR_PLS_LEV4 0x00000080U /*!< PVD level 4 */
+#define PWR_CR_PLS_LEV5 0x000000A0U /*!< PVD level 5 */
+#define PWR_CR_PLS_LEV6 0x000000C0U /*!< PVD level 6 */
+#define PWR_CR_PLS_LEV7 0x000000E0U /*!< PVD level 7 */
+
+#define PWR_CR_DBP 0x00000100U /*!< Disable Backup Domain write protection */
+#define PWR_CR_FPDS 0x00000200U /*!< Flash power down in Stop mode */
+#define PWR_CR_LPLVDS 0x00000400U /*!< Low Power Regulator Low Voltage in Deep Sleep mode */
+#define PWR_CR_MRLVDS 0x00000800U /*!< Main Regulator Low Voltage in Deep Sleep mode */
+#define PWR_CR_ADCDC1 0x00002000U /*!< Refer to AN4073 on how to use this bit */
+#define PWR_CR_VOS 0x0000C000U /*!< VOS[1:0] bits (Regulator voltage scaling output selection) */
+#define PWR_CR_VOS_0 0x00004000U /*!< Bit 0 */
+#define PWR_CR_VOS_1 0x00008000U /*!< Bit 1 */
+
+/* Legacy define */
+#define PWR_CR_PMODE PWR_CR_VOS
+
+/******************* Bit definition for PWR_CSR register ********************/
+#define PWR_CSR_WUF 0x00000001U /*!< Wakeup Flag */
+#define PWR_CSR_SBF 0x00000002U /*!< Standby Flag */
+#define PWR_CSR_PVDO 0x00000004U /*!< PVD Output */
+#define PWR_CSR_BRR 0x00000008U /*!< Backup regulator ready */
+#define PWR_CSR_EWUP 0x00000100U /*!< Enable WKUP pin */
+#define PWR_CSR_BRE 0x00000200U /*!< Backup regulator enable */
+#define PWR_CSR_VOSRDY 0x00004000U /*!< Regulator voltage scaling output selection ready */
+
+/* Legacy define */
+#define PWR_CSR_REGRDY PWR_CSR_VOSRDY
+
+/******************************************************************************/
+/* */
+/* Reset and Clock Control */
+/* */
+/******************************************************************************/
+/******************** Bit definition for RCC_CR register ********************/
+#define RCC_CR_HSION 0x00000001U
+#define RCC_CR_HSIRDY 0x00000002U
+
+#define RCC_CR_HSITRIM 0x000000F8U
+#define RCC_CR_HSITRIM_0 0x00000008U/*!<Bit 0 */
+#define RCC_CR_HSITRIM_1 0x00000010U/*!<Bit 1 */
+#define RCC_CR_HSITRIM_2 0x00000020U/*!<Bit 2 */
+#define RCC_CR_HSITRIM_3 0x00000040U/*!<Bit 3 */
+#define RCC_CR_HSITRIM_4 0x00000080U/*!<Bit 4 */
+
+#define RCC_CR_HSICAL 0x0000FF00U
+#define RCC_CR_HSICAL_0 0x00000100U/*!<Bit 0 */
+#define RCC_CR_HSICAL_1 0x00000200U/*!<Bit 1 */
+#define RCC_CR_HSICAL_2 0x00000400U/*!<Bit 2 */
+#define RCC_CR_HSICAL_3 0x00000800U/*!<Bit 3 */
+#define RCC_CR_HSICAL_4 0x00001000U/*!<Bit 4 */
+#define RCC_CR_HSICAL_5 0x00002000U/*!<Bit 5 */
+#define RCC_CR_HSICAL_6 0x00004000U/*!<Bit 6 */
+#define RCC_CR_HSICAL_7 0x00008000U/*!<Bit 7 */
+
+#define RCC_CR_HSEON 0x00010000U
+#define RCC_CR_HSERDY 0x00020000U
+#define RCC_CR_HSEBYP 0x00040000U
+#define RCC_CR_CSSON 0x00080000U
+#define RCC_CR_PLLON 0x01000000U
+#define RCC_CR_PLLRDY 0x02000000U
+#define RCC_CR_PLLI2SON 0x04000000U
+#define RCC_CR_PLLI2SRDY 0x08000000U
+
+/******************** Bit definition for RCC_PLLCFGR register ***************/
+#define RCC_PLLCFGR_PLLM 0x0000003FU
+#define RCC_PLLCFGR_PLLM_0 0x00000001U
+#define RCC_PLLCFGR_PLLM_1 0x00000002U
+#define RCC_PLLCFGR_PLLM_2 0x00000004U
+#define RCC_PLLCFGR_PLLM_3 0x00000008U
+#define RCC_PLLCFGR_PLLM_4 0x00000010U
+#define RCC_PLLCFGR_PLLM_5 0x00000020U
+
+#define RCC_PLLCFGR_PLLN 0x00007FC0U
+#define RCC_PLLCFGR_PLLN_0 0x00000040U
+#define RCC_PLLCFGR_PLLN_1 0x00000080U
+#define RCC_PLLCFGR_PLLN_2 0x00000100U
+#define RCC_PLLCFGR_PLLN_3 0x00000200U
+#define RCC_PLLCFGR_PLLN_4 0x00000400U
+#define RCC_PLLCFGR_PLLN_5 0x00000800U
+#define RCC_PLLCFGR_PLLN_6 0x00001000U
+#define RCC_PLLCFGR_PLLN_7 0x00002000U
+#define RCC_PLLCFGR_PLLN_8 0x00004000U
+
+#define RCC_PLLCFGR_PLLP 0x00030000U
+#define RCC_PLLCFGR_PLLP_0 0x00010000U
+#define RCC_PLLCFGR_PLLP_1 0x00020000U
+
+#define RCC_PLLCFGR_PLLSRC 0x00400000U
+#define RCC_PLLCFGR_PLLSRC_HSE 0x00400000U
+#define RCC_PLLCFGR_PLLSRC_HSI 0x00000000U
+
+#define RCC_PLLCFGR_PLLQ 0x0F000000U
+#define RCC_PLLCFGR_PLLQ_0 0x01000000U
+#define RCC_PLLCFGR_PLLQ_1 0x02000000U
+#define RCC_PLLCFGR_PLLQ_2 0x04000000U
+#define RCC_PLLCFGR_PLLQ_3 0x08000000U
+
+/******************** Bit definition for RCC_CFGR register ******************/
+/*!< SW configuration */
+#define RCC_CFGR_SW 0x00000003U /*!< SW[1:0] bits (System clock Switch) */
+#define RCC_CFGR_SW_0 0x00000001U /*!< Bit 0 */
+#define RCC_CFGR_SW_1 0x00000002U /*!< Bit 1 */
+
+#define RCC_CFGR_SW_HSI 0x00000000U /*!< HSI selected as system clock */
+#define RCC_CFGR_SW_HSE 0x00000001U /*!< HSE selected as system clock */
+#define RCC_CFGR_SW_PLL 0x00000002U /*!< PLL selected as system clock */
+
+/*!< SWS configuration */
+#define RCC_CFGR_SWS 0x0000000CU /*!< SWS[1:0] bits (System Clock Switch Status) */
+#define RCC_CFGR_SWS_0 0x00000004U /*!< Bit 0 */
+#define RCC_CFGR_SWS_1 0x00000008U /*!< Bit 1 */
+
+#define RCC_CFGR_SWS_HSI 0x00000000U /*!< HSI oscillator used as system clock */
+#define RCC_CFGR_SWS_HSE 0x00000004U /*!< HSE oscillator used as system clock */
+#define RCC_CFGR_SWS_PLL 0x00000008U /*!< PLL used as system clock */
+
+/*!< HPRE configuration */
+#define RCC_CFGR_HPRE 0x000000F0U /*!< HPRE[3:0] bits (AHB prescaler) */
+#define RCC_CFGR_HPRE_0 0x00000010U /*!< Bit 0 */
+#define RCC_CFGR_HPRE_1 0x00000020U /*!< Bit 1 */
+#define RCC_CFGR_HPRE_2 0x00000040U /*!< Bit 2 */
+#define RCC_CFGR_HPRE_3 0x00000080U /*!< Bit 3 */
+
+#define RCC_CFGR_HPRE_DIV1 0x00000000U /*!< SYSCLK not divided */
+#define RCC_CFGR_HPRE_DIV2 0x00000080U /*!< SYSCLK divided by 2 */
+#define RCC_CFGR_HPRE_DIV4 0x00000090U /*!< SYSCLK divided by 4 */
+#define RCC_CFGR_HPRE_DIV8 0x000000A0U /*!< SYSCLK divided by 8 */
+#define RCC_CFGR_HPRE_DIV16 0x000000B0U /*!< SYSCLK divided by 16 */
+#define RCC_CFGR_HPRE_DIV64 0x000000C0U /*!< SYSCLK divided by 64 */
+#define RCC_CFGR_HPRE_DIV128 0x000000D0U /*!< SYSCLK divided by 128 */
+#define RCC_CFGR_HPRE_DIV256 0x000000E0U /*!< SYSCLK divided by 256 */
+#define RCC_CFGR_HPRE_DIV512 0x000000F0U /*!< SYSCLK divided by 512 */
+
+/*!< PPRE1 configuration */
+#define RCC_CFGR_PPRE1 0x00001C00U /*!< PRE1[2:0] bits (APB1 prescaler) */
+#define RCC_CFGR_PPRE1_0 0x00000400U /*!< Bit 0 */
+#define RCC_CFGR_PPRE1_1 0x00000800U /*!< Bit 1 */
+#define RCC_CFGR_PPRE1_2 0x00001000U /*!< Bit 2 */
+
+#define RCC_CFGR_PPRE1_DIV1 0x00000000U /*!< HCLK not divided */
+#define RCC_CFGR_PPRE1_DIV2 0x00001000U /*!< HCLK divided by 2 */
+#define RCC_CFGR_PPRE1_DIV4 0x00001400U /*!< HCLK divided by 4 */
+#define RCC_CFGR_PPRE1_DIV8 0x00001800U /*!< HCLK divided by 8 */
+#define RCC_CFGR_PPRE1_DIV16 0x00001C00U /*!< HCLK divided by 16 */
+
+/*!< PPRE2 configuration */
+#define RCC_CFGR_PPRE2 0x0000E000U /*!< PRE2[2:0] bits (APB2 prescaler) */
+#define RCC_CFGR_PPRE2_0 0x00002000U /*!< Bit 0 */
+#define RCC_CFGR_PPRE2_1 0x00004000U /*!< Bit 1 */
+#define RCC_CFGR_PPRE2_2 0x00008000U /*!< Bit 2 */
+
+#define RCC_CFGR_PPRE2_DIV1 0x00000000U /*!< HCLK not divided */
+#define RCC_CFGR_PPRE2_DIV2 0x00008000U /*!< HCLK divided by 2 */
+#define RCC_CFGR_PPRE2_DIV4 0x0000A000U /*!< HCLK divided by 4 */
+#define RCC_CFGR_PPRE2_DIV8 0x0000C000U /*!< HCLK divided by 8 */
+#define RCC_CFGR_PPRE2_DIV16 0x0000E000U /*!< HCLK divided by 16 */
+
+/*!< RTCPRE configuration */
+#define RCC_CFGR_RTCPRE 0x001F0000U
+#define RCC_CFGR_RTCPRE_0 0x00010000U
+#define RCC_CFGR_RTCPRE_1 0x00020000U
+#define RCC_CFGR_RTCPRE_2 0x00040000U
+#define RCC_CFGR_RTCPRE_3 0x00080000U
+#define RCC_CFGR_RTCPRE_4 0x00100000U
+
+/*!< MCO1 configuration */
+#define RCC_CFGR_MCO1 0x00600000U
+#define RCC_CFGR_MCO1_0 0x00200000U
+#define RCC_CFGR_MCO1_1 0x00400000U
+
+#define RCC_CFGR_I2SSRC 0x00800000U
+
+#define RCC_CFGR_MCO1PRE 0x07000000U
+#define RCC_CFGR_MCO1PRE_0 0x01000000U
+#define RCC_CFGR_MCO1PRE_1 0x02000000U
+#define RCC_CFGR_MCO1PRE_2 0x04000000U
+
+#define RCC_CFGR_MCO2PRE 0x38000000U
+#define RCC_CFGR_MCO2PRE_0 0x08000000U
+#define RCC_CFGR_MCO2PRE_1 0x10000000U
+#define RCC_CFGR_MCO2PRE_2 0x20000000U
+
+#define RCC_CFGR_MCO2 0xC0000000U
+#define RCC_CFGR_MCO2_0 0x40000000U
+#define RCC_CFGR_MCO2_1 0x80000000U
+
+/******************** Bit definition for RCC_CIR register *******************/
+#define RCC_CIR_LSIRDYF 0x00000001U
+#define RCC_CIR_LSERDYF 0x00000002U
+#define RCC_CIR_HSIRDYF 0x00000004U
+#define RCC_CIR_HSERDYF 0x00000008U
+#define RCC_CIR_PLLRDYF 0x00000010U
+#define RCC_CIR_PLLI2SRDYF 0x00000020U
+
+#define RCC_CIR_CSSF 0x00000080U
+#define RCC_CIR_LSIRDYIE 0x00000100U
+#define RCC_CIR_LSERDYIE 0x00000200U
+#define RCC_CIR_HSIRDYIE 0x00000400U
+#define RCC_CIR_HSERDYIE 0x00000800U
+#define RCC_CIR_PLLRDYIE 0x00001000U
+#define RCC_CIR_PLLI2SRDYIE 0x00002000U
+
+#define RCC_CIR_LSIRDYC 0x00010000U
+#define RCC_CIR_LSERDYC 0x00020000U
+#define RCC_CIR_HSIRDYC 0x00040000U
+#define RCC_CIR_HSERDYC 0x00080000U
+#define RCC_CIR_PLLRDYC 0x00100000U
+#define RCC_CIR_PLLI2SRDYC 0x00200000U
+
+#define RCC_CIR_CSSC 0x00800000U
+
+/******************** Bit definition for RCC_AHB1RSTR register **************/
+#define RCC_AHB1RSTR_GPIOARST 0x00000001U
+#define RCC_AHB1RSTR_GPIOBRST 0x00000002U
+#define RCC_AHB1RSTR_GPIOCRST 0x00000004U
+#define RCC_AHB1RSTR_GPIODRST 0x00000008U
+#define RCC_AHB1RSTR_GPIOERST 0x00000010U
+#define RCC_AHB1RSTR_GPIOHRST 0x00000080U
+#define RCC_AHB1RSTR_CRCRST 0x00001000U
+#define RCC_AHB1RSTR_DMA1RST 0x00200000U
+#define RCC_AHB1RSTR_DMA2RST 0x00400000U
+
+/******************** Bit definition for RCC_AHB2RSTR register **************/
+#define RCC_AHB2RSTR_OTGFSRST 0x00000080U
+
+/******************** Bit definition for RCC_AHB3RSTR register **************/
+
+/******************** Bit definition for RCC_APB1RSTR register **************/
+#define RCC_APB1RSTR_TIM2RST 0x00000001U
+#define RCC_APB1RSTR_TIM3RST 0x00000002U
+#define RCC_APB1RSTR_TIM4RST 0x00000004U
+#define RCC_APB1RSTR_TIM5RST 0x00000008U
+#define RCC_APB1RSTR_WWDGRST 0x00000800U
+#define RCC_APB1RSTR_SPI2RST 0x00004000U
+#define RCC_APB1RSTR_SPI3RST 0x00008000U
+#define RCC_APB1RSTR_USART2RST 0x00020000U
+#define RCC_APB1RSTR_I2C1RST 0x00200000U
+#define RCC_APB1RSTR_I2C2RST 0x00400000U
+#define RCC_APB1RSTR_I2C3RST 0x00800000U
+#define RCC_APB1RSTR_PWRRST 0x10000000U
+
+/******************** Bit definition for RCC_APB2RSTR register **************/
+#define RCC_APB2RSTR_TIM1RST 0x00000001U
+#define RCC_APB2RSTR_USART1RST 0x00000010U
+#define RCC_APB2RSTR_USART6RST 0x00000020U
+#define RCC_APB2RSTR_ADCRST 0x00000100U
+#define RCC_APB2RSTR_SDIORST 0x00000800U
+#define RCC_APB2RSTR_SPI1RST 0x00001000U
+#define RCC_APB2RSTR_SPI4RST 0x00002000U
+#define RCC_APB2RSTR_SYSCFGRST 0x00004000U
+#define RCC_APB2RSTR_TIM9RST 0x00010000U
+#define RCC_APB2RSTR_TIM10RST 0x00020000U
+#define RCC_APB2RSTR_TIM11RST 0x00040000U
+
+/* Old SPI1RST bit definition, maintained for legacy purpose */
+#define RCC_APB2RSTR_SPI1 RCC_APB2RSTR_SPI1RST
+
+/******************** Bit definition for RCC_AHB1ENR register ***************/
+#define RCC_AHB1ENR_GPIOAEN 0x00000001U
+#define RCC_AHB1ENR_GPIOBEN 0x00000002U
+#define RCC_AHB1ENR_GPIOCEN 0x00000004U
+#define RCC_AHB1ENR_GPIODEN 0x00000008U
+#define RCC_AHB1ENR_GPIOEEN 0x00000010U
+#define RCC_AHB1ENR_GPIOHEN 0x00000080U
+#define RCC_AHB1ENR_CRCEN 0x00001000U
+#define RCC_AHB1ENR_BKPSRAMEN 0x00040000U
+#define RCC_AHB1ENR_DMA1EN 0x00200000U
+#define RCC_AHB1ENR_DMA2EN 0x00400000U
+
+/******************** Bit definition for RCC_AHB2ENR register ***************/
+#define RCC_AHB2ENR_OTGFSEN 0x00000080U
+
+/******************** Bit definition for RCC_AHB3ENR register ***************/
+
+/******************** Bit definition for RCC_APB1ENR register ***************/
+#define RCC_APB1ENR_TIM2EN 0x00000001U
+#define RCC_APB1ENR_TIM3EN 0x00000002U
+#define RCC_APB1ENR_TIM4EN 0x00000004U
+#define RCC_APB1ENR_TIM5EN 0x00000008U
+#define RCC_APB1ENR_WWDGEN 0x00000800U
+#define RCC_APB1ENR_SPI2EN 0x00004000U
+#define RCC_APB1ENR_SPI3EN 0x00008000U
+#define RCC_APB1ENR_USART2EN 0x00020000U
+#define RCC_APB1ENR_I2C1EN 0x00200000U
+#define RCC_APB1ENR_I2C2EN 0x00400000U
+#define RCC_APB1ENR_I2C3EN 0x00800000U
+#define RCC_APB1ENR_PWREN 0x10000000U
+
+/******************** Bit definition for RCC_APB2ENR register ***************/
+#define RCC_APB2ENR_TIM1EN 0x00000001U
+#define RCC_APB2ENR_USART1EN 0x00000010U
+#define RCC_APB2ENR_USART6EN 0x00000020U
+#define RCC_APB2ENR_ADC1EN 0x00000100U
+#define RCC_APB2ENR_SDIOEN 0x00000800U
+#define RCC_APB2ENR_SPI1EN 0x00001000U
+#define RCC_APB2ENR_SPI4EN 0x00002000U
+#define RCC_APB2ENR_SYSCFGEN 0x00004000U
+#define RCC_APB2ENR_TIM9EN 0x00010000U
+#define RCC_APB2ENR_TIM10EN 0x00020000U
+#define RCC_APB2ENR_TIM11EN 0x00040000U
+
+/******************** Bit definition for RCC_AHB1LPENR register *************/
+#define RCC_AHB1LPENR_GPIOALPEN 0x00000001U
+#define RCC_AHB1LPENR_GPIOBLPEN 0x00000002U
+#define RCC_AHB1LPENR_GPIOCLPEN 0x00000004U
+#define RCC_AHB1LPENR_GPIODLPEN 0x00000008U
+#define RCC_AHB1LPENR_GPIOELPEN 0x00000010U
+#define RCC_AHB1LPENR_GPIOHLPEN 0x00000080U
+#define RCC_AHB1LPENR_CRCLPEN 0x00001000U
+#define RCC_AHB1LPENR_FLITFLPEN 0x00008000U
+#define RCC_AHB1LPENR_SRAM1LPEN 0x00010000U
+#define RCC_AHB1LPENR_SRAM2LPEN 0x00020000U
+#define RCC_AHB1LPENR_BKPSRAMLPEN 0x00040000U
+#define RCC_AHB1LPENR_DMA1LPEN 0x00200000U
+#define RCC_AHB1LPENR_DMA2LPEN 0x00400000U
+
+/******************** Bit definition for RCC_AHB2LPENR register *************/
+#define RCC_AHB2LPENR_OTGFSLPEN 0x00000080U
+
+/******************** Bit definition for RCC_AHB3LPENR register *************/
+
+/******************** Bit definition for RCC_APB1LPENR register *************/
+#define RCC_APB1LPENR_TIM2LPEN 0x00000001U
+#define RCC_APB1LPENR_TIM3LPEN 0x00000002U
+#define RCC_APB1LPENR_TIM4LPEN 0x00000004U
+#define RCC_APB1LPENR_TIM5LPEN 0x00000008U
+#define RCC_APB1LPENR_WWDGLPEN 0x00000800U
+#define RCC_APB1LPENR_SPI2LPEN 0x00004000U
+#define RCC_APB1LPENR_SPI3LPEN 0x00008000U
+#define RCC_APB1LPENR_USART2LPEN 0x00020000U
+#define RCC_APB1LPENR_I2C1LPEN 0x00200000U
+#define RCC_APB1LPENR_I2C2LPEN 0x00400000U
+#define RCC_APB1LPENR_I2C3LPEN 0x00800000U
+#define RCC_APB1LPENR_PWRLPEN 0x10000000U
+#define RCC_APB1LPENR_DACLPEN 0x20000000U
+
+/******************** Bit definition for RCC_APB2LPENR register *************/
+#define RCC_APB2LPENR_TIM1LPEN 0x00000001U
+#define RCC_APB2LPENR_USART1LPEN 0x00000010U
+#define RCC_APB2LPENR_USART6LPEN 0x00000020U
+#define RCC_APB2LPENR_ADC1LPEN 0x00000100U
+#define RCC_APB2LPENR_SDIOLPEN 0x00000800U
+#define RCC_APB2LPENR_SPI1LPEN 0x00001000U
+#define RCC_APB2LPENR_SPI4LPEN 0x00002000U
+#define RCC_APB2LPENR_SYSCFGLPEN 0x00004000U
+#define RCC_APB2LPENR_TIM9LPEN 0x00010000U
+#define RCC_APB2LPENR_TIM10LPEN 0x00020000U
+#define RCC_APB2LPENR_TIM11LPEN 0x00040000U
+
+/******************** Bit definition for RCC_BDCR register ******************/
+#define RCC_BDCR_LSEON 0x00000001U
+#define RCC_BDCR_LSERDY 0x00000002U
+#define RCC_BDCR_LSEBYP 0x00000004U
+
+#define RCC_BDCR_RTCSEL 0x00000300U
+#define RCC_BDCR_RTCSEL_0 0x00000100U
+#define RCC_BDCR_RTCSEL_1 0x00000200U
+
+#define RCC_BDCR_RTCEN 0x00008000U
+#define RCC_BDCR_BDRST 0x00010000U
+
+/******************** Bit definition for RCC_CSR register *******************/
+#define RCC_CSR_LSION 0x00000001U
+#define RCC_CSR_LSIRDY 0x00000002U
+#define RCC_CSR_RMVF 0x01000000U
+#define RCC_CSR_BORRSTF 0x02000000U
+#define RCC_CSR_PADRSTF 0x04000000U
+#define RCC_CSR_PORRSTF 0x08000000U
+#define RCC_CSR_SFTRSTF 0x10000000U
+#define RCC_CSR_WDGRSTF 0x20000000U
+#define RCC_CSR_WWDGRSTF 0x40000000U
+#define RCC_CSR_LPWRRSTF 0x80000000U
+
+/******************** Bit definition for RCC_SSCGR register *****************/
+#define RCC_SSCGR_MODPER 0x00001FFFU
+#define RCC_SSCGR_INCSTEP 0x0FFFE000U
+#define RCC_SSCGR_SPREADSEL 0x40000000U
+#define RCC_SSCGR_SSCGEN 0x80000000U
+
+/******************** Bit definition for RCC_PLLI2SCFGR register ************/
+#define RCC_PLLI2SCFGR_PLLI2SN 0x00007FC0U
+#define RCC_PLLI2SCFGR_PLLI2SN_0 0x00000040U
+#define RCC_PLLI2SCFGR_PLLI2SN_1 0x00000080U
+#define RCC_PLLI2SCFGR_PLLI2SN_2 0x00000100U
+#define RCC_PLLI2SCFGR_PLLI2SN_3 0x00000200U
+#define RCC_PLLI2SCFGR_PLLI2SN_4 0x00000400U
+#define RCC_PLLI2SCFGR_PLLI2SN_5 0x00000800U
+#define RCC_PLLI2SCFGR_PLLI2SN_6 0x00001000U
+#define RCC_PLLI2SCFGR_PLLI2SN_7 0x00002000U
+#define RCC_PLLI2SCFGR_PLLI2SN_8 0x00004000U
+
+#define RCC_PLLI2SCFGR_PLLI2SR 0x70000000U
+#define RCC_PLLI2SCFGR_PLLI2SR_0 0x10000000U
+#define RCC_PLLI2SCFGR_PLLI2SR_1 0x20000000U
+#define RCC_PLLI2SCFGR_PLLI2SR_2 0x40000000U
+
+/******************** Bit definition for RCC_DCKCFGR register ***************/
+#define RCC_DCKCFGR_TIMPRE 0x01000000U
+
+/******************************************************************************/
+/* */
+/* Real-Time Clock (RTC) */
+/* */
+/******************************************************************************/
+/******************** Bits definition for RTC_TR register *******************/
+#define RTC_TR_PM 0x00400000U
+#define RTC_TR_HT 0x00300000U
+#define RTC_TR_HT_0 0x00100000U
+#define RTC_TR_HT_1 0x00200000U
+#define RTC_TR_HU 0x000F0000U
+#define RTC_TR_HU_0 0x00010000U
+#define RTC_TR_HU_1 0x00020000U
+#define RTC_TR_HU_2 0x00040000U
+#define RTC_TR_HU_3 0x00080000U
+#define RTC_TR_MNT 0x00007000U
+#define RTC_TR_MNT_0 0x00001000U
+#define RTC_TR_MNT_1 0x00002000U
+#define RTC_TR_MNT_2 0x00004000U
+#define RTC_TR_MNU 0x00000F00U
+#define RTC_TR_MNU_0 0x00000100U
+#define RTC_TR_MNU_1 0x00000200U
+#define RTC_TR_MNU_2 0x00000400U
+#define RTC_TR_MNU_3 0x00000800U
+#define RTC_TR_ST 0x00000070U
+#define RTC_TR_ST_0 0x00000010U
+#define RTC_TR_ST_1 0x00000020U
+#define RTC_TR_ST_2 0x00000040U
+#define RTC_TR_SU 0x0000000FU
+#define RTC_TR_SU_0 0x00000001U
+#define RTC_TR_SU_1 0x00000002U
+#define RTC_TR_SU_2 0x00000004U
+#define RTC_TR_SU_3 0x00000008U
+
+/******************** Bits definition for RTC_DR register *******************/
+#define RTC_DR_YT 0x00F00000U
+#define RTC_DR_YT_0 0x00100000U
+#define RTC_DR_YT_1 0x00200000U
+#define RTC_DR_YT_2 0x00400000U
+#define RTC_DR_YT_3 0x00800000U
+#define RTC_DR_YU 0x000F0000U
+#define RTC_DR_YU_0 0x00010000U
+#define RTC_DR_YU_1 0x00020000U
+#define RTC_DR_YU_2 0x00040000U
+#define RTC_DR_YU_3 0x00080000U
+#define RTC_DR_WDU 0x0000E000U
+#define RTC_DR_WDU_0 0x00002000U
+#define RTC_DR_WDU_1 0x00004000U
+#define RTC_DR_WDU_2 0x00008000U
+#define RTC_DR_MT 0x00001000U
+#define RTC_DR_MU 0x00000F00U
+#define RTC_DR_MU_0 0x00000100U
+#define RTC_DR_MU_1 0x00000200U
+#define RTC_DR_MU_2 0x00000400U
+#define RTC_DR_MU_3 0x00000800U
+#define RTC_DR_DT 0x00000030U
+#define RTC_DR_DT_0 0x00000010U
+#define RTC_DR_DT_1 0x00000020U
+#define RTC_DR_DU 0x0000000FU
+#define RTC_DR_DU_0 0x00000001U
+#define RTC_DR_DU_1 0x00000002U
+#define RTC_DR_DU_2 0x00000004U
+#define RTC_DR_DU_3 0x00000008U
+
+/******************** Bits definition for RTC_CR register *******************/
+#define RTC_CR_COE 0x00800000U
+#define RTC_CR_OSEL 0x00600000U
+#define RTC_CR_OSEL_0 0x00200000U
+#define RTC_CR_OSEL_1 0x00400000U
+#define RTC_CR_POL 0x00100000U
+#define RTC_CR_COSEL 0x00080000U
+#define RTC_CR_BCK 0x00040000U
+#define RTC_CR_SUB1H 0x00020000U
+#define RTC_CR_ADD1H 0x00010000U
+#define RTC_CR_TSIE 0x00008000U
+#define RTC_CR_WUTIE 0x00004000U
+#define RTC_CR_ALRBIE 0x00002000U
+#define RTC_CR_ALRAIE 0x00001000U
+#define RTC_CR_TSE 0x00000800U
+#define RTC_CR_WUTE 0x00000400U
+#define RTC_CR_ALRBE 0x00000200U
+#define RTC_CR_ALRAE 0x00000100U
+#define RTC_CR_DCE 0x00000080U
+#define RTC_CR_FMT 0x00000040U
+#define RTC_CR_BYPSHAD 0x00000020U
+#define RTC_CR_REFCKON 0x00000010U
+#define RTC_CR_TSEDGE 0x00000008U
+#define RTC_CR_WUCKSEL 0x00000007U
+#define RTC_CR_WUCKSEL_0 0x00000001U
+#define RTC_CR_WUCKSEL_1 0x00000002U
+#define RTC_CR_WUCKSEL_2 0x00000004U
+
+/******************** Bits definition for RTC_ISR register ******************/
+#define RTC_ISR_RECALPF 0x00010000U
+#define RTC_ISR_TAMP1F 0x00002000U
+#define RTC_ISR_TAMP2F 0x00004000U
+#define RTC_ISR_TSOVF 0x00001000U
+#define RTC_ISR_TSF 0x00000800U
+#define RTC_ISR_WUTF 0x00000400U
+#define RTC_ISR_ALRBF 0x00000200U
+#define RTC_ISR_ALRAF 0x00000100U
+#define RTC_ISR_INIT 0x00000080U
+#define RTC_ISR_INITF 0x00000040U
+#define RTC_ISR_RSF 0x00000020U
+#define RTC_ISR_INITS 0x00000010U
+#define RTC_ISR_SHPF 0x00000008U
+#define RTC_ISR_WUTWF 0x00000004U
+#define RTC_ISR_ALRBWF 0x00000002U
+#define RTC_ISR_ALRAWF 0x00000001U
+
+/******************** Bits definition for RTC_PRER register *****************/
+#define RTC_PRER_PREDIV_A 0x007F0000U
+#define RTC_PRER_PREDIV_S 0x00007FFFU
+
+/******************** Bits definition for RTC_WUTR register *****************/
+#define RTC_WUTR_WUT 0x0000FFFFU
+
+/******************** Bits definition for RTC_CALIBR register ***************/
+#define RTC_CALIBR_DCS 0x00000080U
+#define RTC_CALIBR_DC 0x0000001FU
+
+/******************** Bits definition for RTC_ALRMAR register ***************/
+#define RTC_ALRMAR_MSK4 0x80000000U
+#define RTC_ALRMAR_WDSEL 0x40000000U
+#define RTC_ALRMAR_DT 0x30000000U
+#define RTC_ALRMAR_DT_0 0x10000000U
+#define RTC_ALRMAR_DT_1 0x20000000U
+#define RTC_ALRMAR_DU 0x0F000000U
+#define RTC_ALRMAR_DU_0 0x01000000U
+#define RTC_ALRMAR_DU_1 0x02000000U
+#define RTC_ALRMAR_DU_2 0x04000000U
+#define RTC_ALRMAR_DU_3 0x08000000U
+#define RTC_ALRMAR_MSK3 0x00800000U
+#define RTC_ALRMAR_PM 0x00400000U
+#define RTC_ALRMAR_HT 0x00300000U
+#define RTC_ALRMAR_HT_0 0x00100000U
+#define RTC_ALRMAR_HT_1 0x00200000U
+#define RTC_ALRMAR_HU 0x000F0000U
+#define RTC_ALRMAR_HU_0 0x00010000U
+#define RTC_ALRMAR_HU_1 0x00020000U
+#define RTC_ALRMAR_HU_2 0x00040000U
+#define RTC_ALRMAR_HU_3 0x00080000U
+#define RTC_ALRMAR_MSK2 0x00008000U
+#define RTC_ALRMAR_MNT 0x00007000U
+#define RTC_ALRMAR_MNT_0 0x00001000U
+#define RTC_ALRMAR_MNT_1 0x00002000U
+#define RTC_ALRMAR_MNT_2 0x00004000U
+#define RTC_ALRMAR_MNU 0x00000F00U
+#define RTC_ALRMAR_MNU_0 0x00000100U
+#define RTC_ALRMAR_MNU_1 0x00000200U
+#define RTC_ALRMAR_MNU_2 0x00000400U
+#define RTC_ALRMAR_MNU_3 0x00000800U
+#define RTC_ALRMAR_MSK1 0x00000080U
+#define RTC_ALRMAR_ST 0x00000070U
+#define RTC_ALRMAR_ST_0 0x00000010U
+#define RTC_ALRMAR_ST_1 0x00000020U
+#define RTC_ALRMAR_ST_2 0x00000040U
+#define RTC_ALRMAR_SU 0x0000000FU
+#define RTC_ALRMAR_SU_0 0x00000001U
+#define RTC_ALRMAR_SU_1 0x00000002U
+#define RTC_ALRMAR_SU_2 0x00000004U
+#define RTC_ALRMAR_SU_3 0x00000008U
+
+/******************** Bits definition for RTC_ALRMBR register ***************/
+#define RTC_ALRMBR_MSK4 0x80000000U
+#define RTC_ALRMBR_WDSEL 0x40000000U
+#define RTC_ALRMBR_DT 0x30000000U
+#define RTC_ALRMBR_DT_0 0x10000000U
+#define RTC_ALRMBR_DT_1 0x20000000U
+#define RTC_ALRMBR_DU 0x0F000000U
+#define RTC_ALRMBR_DU_0 0x01000000U
+#define RTC_ALRMBR_DU_1 0x02000000U
+#define RTC_ALRMBR_DU_2 0x04000000U
+#define RTC_ALRMBR_DU_3 0x08000000U
+#define RTC_ALRMBR_MSK3 0x00800000U
+#define RTC_ALRMBR_PM 0x00400000U
+#define RTC_ALRMBR_HT 0x00300000U
+#define RTC_ALRMBR_HT_0 0x00100000U
+#define RTC_ALRMBR_HT_1 0x00200000U
+#define RTC_ALRMBR_HU 0x000F0000U
+#define RTC_ALRMBR_HU_0 0x00010000U
+#define RTC_ALRMBR_HU_1 0x00020000U
+#define RTC_ALRMBR_HU_2 0x00040000U
+#define RTC_ALRMBR_HU_3 0x00080000U
+#define RTC_ALRMBR_MSK2 0x00008000U
+#define RTC_ALRMBR_MNT 0x00007000U
+#define RTC_ALRMBR_MNT_0 0x00001000U
+#define RTC_ALRMBR_MNT_1 0x00002000U
+#define RTC_ALRMBR_MNT_2 0x00004000U
+#define RTC_ALRMBR_MNU 0x00000F00U
+#define RTC_ALRMBR_MNU_0 0x00000100U
+#define RTC_ALRMBR_MNU_1 0x00000200U
+#define RTC_ALRMBR_MNU_2 0x00000400U
+#define RTC_ALRMBR_MNU_3 0x00000800U
+#define RTC_ALRMBR_MSK1 0x00000080U
+#define RTC_ALRMBR_ST 0x00000070U
+#define RTC_ALRMBR_ST_0 0x00000010U
+#define RTC_ALRMBR_ST_1 0x00000020U
+#define RTC_ALRMBR_ST_2 0x00000040U
+#define RTC_ALRMBR_SU 0x0000000FU
+#define RTC_ALRMBR_SU_0 0x00000001U
+#define RTC_ALRMBR_SU_1 0x00000002U
+#define RTC_ALRMBR_SU_2 0x00000004U
+#define RTC_ALRMBR_SU_3 0x00000008U
+
+/******************** Bits definition for RTC_WPR register ******************/
+#define RTC_WPR_KEY 0x000000FFU
+
+/******************** Bits definition for RTC_SSR register ******************/
+#define RTC_SSR_SS 0x0000FFFFU
+
+/******************** Bits definition for RTC_SHIFTR register ***************/
+#define RTC_SHIFTR_SUBFS 0x00007FFFU
+#define RTC_SHIFTR_ADD1S 0x80000000U
+
+/******************** Bits definition for RTC_TSTR register *****************/
+#define RTC_TSTR_PM 0x00400000U
+#define RTC_TSTR_HT 0x00300000U
+#define RTC_TSTR_HT_0 0x00100000U
+#define RTC_TSTR_HT_1 0x00200000U
+#define RTC_TSTR_HU 0x000F0000U
+#define RTC_TSTR_HU_0 0x00010000U
+#define RTC_TSTR_HU_1 0x00020000U
+#define RTC_TSTR_HU_2 0x00040000U
+#define RTC_TSTR_HU_3 0x00080000U
+#define RTC_TSTR_MNT 0x00007000U
+#define RTC_TSTR_MNT_0 0x00001000U
+#define RTC_TSTR_MNT_1 0x00002000U
+#define RTC_TSTR_MNT_2 0x00004000U
+#define RTC_TSTR_MNU 0x00000F00U
+#define RTC_TSTR_MNU_0 0x00000100U
+#define RTC_TSTR_MNU_1 0x00000200U
+#define RTC_TSTR_MNU_2 0x00000400U
+#define RTC_TSTR_MNU_3 0x00000800U
+#define RTC_TSTR_ST 0x00000070U
+#define RTC_TSTR_ST_0 0x00000010U
+#define RTC_TSTR_ST_1 0x00000020U
+#define RTC_TSTR_ST_2 0x00000040U
+#define RTC_TSTR_SU 0x0000000FU
+#define RTC_TSTR_SU_0 0x00000001U
+#define RTC_TSTR_SU_1 0x00000002U
+#define RTC_TSTR_SU_2 0x00000004U
+#define RTC_TSTR_SU_3 0x00000008U
+
+/******************** Bits definition for RTC_TSDR register *****************/
+#define RTC_TSDR_WDU 0x0000E000U
+#define RTC_TSDR_WDU_0 0x00002000U
+#define RTC_TSDR_WDU_1 0x00004000U
+#define RTC_TSDR_WDU_2 0x00008000U
+#define RTC_TSDR_MT 0x00001000U
+#define RTC_TSDR_MU 0x00000F00U
+#define RTC_TSDR_MU_0 0x00000100U
+#define RTC_TSDR_MU_1 0x00000200U
+#define RTC_TSDR_MU_2 0x00000400U
+#define RTC_TSDR_MU_3 0x00000800U
+#define RTC_TSDR_DT 0x00000030U
+#define RTC_TSDR_DT_0 0x00000010U
+#define RTC_TSDR_DT_1 0x00000020U
+#define RTC_TSDR_DU 0x0000000FU
+#define RTC_TSDR_DU_0 0x00000001U
+#define RTC_TSDR_DU_1 0x00000002U
+#define RTC_TSDR_DU_2 0x00000004U
+#define RTC_TSDR_DU_3 0x00000008U
+
+/******************** Bits definition for RTC_TSSSR register ****************/
+#define RTC_TSSSR_SS 0x0000FFFFU
+
+/******************** Bits definition for RTC_CAL register *****************/
+#define RTC_CALR_CALP 0x00008000U
+#define RTC_CALR_CALW8 0x00004000U
+#define RTC_CALR_CALW16 0x00002000U
+#define RTC_CALR_CALM 0x000001FFU
+#define RTC_CALR_CALM_0 0x00000001U
+#define RTC_CALR_CALM_1 0x00000002U
+#define RTC_CALR_CALM_2 0x00000004U
+#define RTC_CALR_CALM_3 0x00000008U
+#define RTC_CALR_CALM_4 0x00000010U
+#define RTC_CALR_CALM_5 0x00000020U
+#define RTC_CALR_CALM_6 0x00000040U
+#define RTC_CALR_CALM_7 0x00000080U
+#define RTC_CALR_CALM_8 0x00000100U
+
+/******************** Bits definition for RTC_TAFCR register ****************/
+#define RTC_TAFCR_ALARMOUTTYPE 0x00040000U
+#define RTC_TAFCR_TSINSEL 0x00020000U
+#define RTC_TAFCR_TAMPINSEL 0x00010000U
+#define RTC_TAFCR_TAMPPUDIS 0x00008000U
+#define RTC_TAFCR_TAMPPRCH 0x00006000U
+#define RTC_TAFCR_TAMPPRCH_0 0x00002000U
+#define RTC_TAFCR_TAMPPRCH_1 0x00004000U
+#define RTC_TAFCR_TAMPFLT 0x00001800U
+#define RTC_TAFCR_TAMPFLT_0 0x00000800U
+#define RTC_TAFCR_TAMPFLT_1 0x00001000U
+#define RTC_TAFCR_TAMPFREQ 0x00000700U
+#define RTC_TAFCR_TAMPFREQ_0 0x00000100U
+#define RTC_TAFCR_TAMPFREQ_1 0x00000200U
+#define RTC_TAFCR_TAMPFREQ_2 0x00000400U
+#define RTC_TAFCR_TAMPTS 0x00000080U
+#define RTC_TAFCR_TAMP2TRG 0x00000010U
+#define RTC_TAFCR_TAMP2E 0x00000008U
+#define RTC_TAFCR_TAMPIE 0x00000004U
+#define RTC_TAFCR_TAMP1TRG 0x00000002U
+#define RTC_TAFCR_TAMP1E 0x00000001U
+
+/******************** Bits definition for RTC_ALRMASSR register *************/
+#define RTC_ALRMASSR_MASKSS 0x0F000000U
+#define RTC_ALRMASSR_MASKSS_0 0x01000000U
+#define RTC_ALRMASSR_MASKSS_1 0x02000000U
+#define RTC_ALRMASSR_MASKSS_2 0x04000000U
+#define RTC_ALRMASSR_MASKSS_3 0x08000000U
+#define RTC_ALRMASSR_SS 0x00007FFFU
+
+/******************** Bits definition for RTC_ALRMBSSR register *************/
+#define RTC_ALRMBSSR_MASKSS 0x0F000000U
+#define RTC_ALRMBSSR_MASKSS_0 0x01000000U
+#define RTC_ALRMBSSR_MASKSS_1 0x02000000U
+#define RTC_ALRMBSSR_MASKSS_2 0x04000000U
+#define RTC_ALRMBSSR_MASKSS_3 0x08000000U
+#define RTC_ALRMBSSR_SS 0x00007FFFU
+
+/******************** Bits definition for RTC_BKP0R register ****************/
+#define RTC_BKP0R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP1R register ****************/
+#define RTC_BKP1R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP2R register ****************/
+#define RTC_BKP2R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP3R register ****************/
+#define RTC_BKP3R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP4R register ****************/
+#define RTC_BKP4R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP5R register ****************/
+#define RTC_BKP5R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP6R register ****************/
+#define RTC_BKP6R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP7R register ****************/
+#define RTC_BKP7R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP8R register ****************/
+#define RTC_BKP8R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP9R register ****************/
+#define RTC_BKP9R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP10R register ***************/
+#define RTC_BKP10R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP11R register ***************/
+#define RTC_BKP11R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP12R register ***************/
+#define RTC_BKP12R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP13R register ***************/
+#define RTC_BKP13R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP14R register ***************/
+#define RTC_BKP14R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP15R register ***************/
+#define RTC_BKP15R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP16R register ***************/
+#define RTC_BKP16R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP17R register ***************/
+#define RTC_BKP17R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP18R register ***************/
+#define RTC_BKP18R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP19R register ***************/
+#define RTC_BKP19R 0xFFFFFFFFU
+
+
+
+/******************************************************************************/
+/* */
+/* SD host Interface */
+/* */
+/******************************************************************************/
+/****************** Bit definition for SDIO_POWER register ******************/
+#define SDIO_POWER_PWRCTRL 0x03U /*!<PWRCTRL[1:0] bits (Power supply control bits) */
+#define SDIO_POWER_PWRCTRL_0 0x01U /*!<Bit 0 */
+#define SDIO_POWER_PWRCTRL_1 0x02U /*!<Bit 1 */
+
+/****************** Bit definition for SDIO_CLKCR register ******************/
+#define SDIO_CLKCR_CLKDIV 0x00FFU /*!<Clock divide factor */
+#define SDIO_CLKCR_CLKEN 0x0100U /*!<Clock enable bit */
+#define SDIO_CLKCR_PWRSAV 0x0200U /*!<Power saving configuration bit */
+#define SDIO_CLKCR_BYPASS 0x0400U /*!<Clock divider bypass enable bit */
+
+#define SDIO_CLKCR_WIDBUS 0x1800U /*!<WIDBUS[1:0] bits (Wide bus mode enable bit) */
+#define SDIO_CLKCR_WIDBUS_0 0x0800U /*!<Bit 0 */
+#define SDIO_CLKCR_WIDBUS_1 0x1000U /*!<Bit 1 */
+
+#define SDIO_CLKCR_NEGEDGE 0x2000U /*!<SDIO_CK dephasing selection bit */
+#define SDIO_CLKCR_HWFC_EN 0x4000U /*!<HW Flow Control enable */
+
+/******************* Bit definition for SDIO_ARG register *******************/
+#define SDIO_ARG_CMDARG 0xFFFFFFFFU /*!<Command argument */
+
+/******************* Bit definition for SDIO_CMD register *******************/
+#define SDIO_CMD_CMDINDEX 0x003FU /*!<Command Index */
+
+#define SDIO_CMD_WAITRESP 0x00C0U /*!<WAITRESP[1:0] bits (Wait for response bits) */
+#define SDIO_CMD_WAITRESP_0 0x0040U /*!< Bit 0 */
+#define SDIO_CMD_WAITRESP_1 0x0080U /*!< Bit 1 */
+
+#define SDIO_CMD_WAITINT 0x0100U /*!<CPSM Waits for Interrupt Request */
+#define SDIO_CMD_WAITPEND 0x0200U /*!<CPSM Waits for ends of data transfer (CmdPend internal signal) */
+#define SDIO_CMD_CPSMEN 0x0400U /*!<Command path state machine (CPSM) Enable bit */
+#define SDIO_CMD_SDIOSUSPEND 0x0800U /*!<SD I/O suspend command */
+#define SDIO_CMD_ENCMDCOMPL 0x1000U /*!<Enable CMD completion */
+#define SDIO_CMD_NIEN 0x2000U /*!<Not Interrupt Enable */
+#define SDIO_CMD_CEATACMD 0x4000U /*!<CE-ATA command */
+
+/***************** Bit definition for SDIO_RESPCMD register *****************/
+#define SDIO_RESPCMD_RESPCMD 0x3FU /*!<Response command index */
+
+/****************** Bit definition for SDIO_RESP0 register ******************/
+#define SDIO_RESP0_CARDSTATUS0 0xFFFFFFFFU /*!<Card Status */
+
+/****************** Bit definition for SDIO_RESP1 register ******************/
+#define SDIO_RESP1_CARDSTATUS1 0xFFFFFFFFU /*!<Card Status */
+
+/****************** Bit definition for SDIO_RESP2 register ******************/
+#define SDIO_RESP2_CARDSTATUS2 0xFFFFFFFFU /*!<Card Status */
+
+/****************** Bit definition for SDIO_RESP3 register ******************/
+#define SDIO_RESP3_CARDSTATUS3 0xFFFFFFFFU /*!<Card Status */
+
+/****************** Bit definition for SDIO_RESP4 register ******************/
+#define SDIO_RESP4_CARDSTATUS4 0xFFFFFFFFU /*!<Card Status */
+
+/****************** Bit definition for SDIO_DTIMER register *****************/
+#define SDIO_DTIMER_DATATIME 0xFFFFFFFFU /*!<Data timeout period. */
+
+/****************** Bit definition for SDIO_DLEN register *******************/
+#define SDIO_DLEN_DATALENGTH 0x01FFFFFFU /*!<Data length value */
+
+/****************** Bit definition for SDIO_DCTRL register ******************/
+#define SDIO_DCTRL_DTEN 0x0001U /*!<Data transfer enabled bit */
+#define SDIO_DCTRL_DTDIR 0x0002U /*!<Data transfer direction selection */
+#define SDIO_DCTRL_DTMODE 0x0004U /*!<Data transfer mode selection */
+#define SDIO_DCTRL_DMAEN 0x0008U /*!<DMA enabled bit */
+
+#define SDIO_DCTRL_DBLOCKSIZE 0x00F0U /*!<DBLOCKSIZE[3:0] bits (Data block size) */
+#define SDIO_DCTRL_DBLOCKSIZE_0 0x0010U /*!<Bit 0 */
+#define SDIO_DCTRL_DBLOCKSIZE_1 0x0020U /*!<Bit 1 */
+#define SDIO_DCTRL_DBLOCKSIZE_2 0x0040U /*!<Bit 2 */
+#define SDIO_DCTRL_DBLOCKSIZE_3 0x0080U /*!<Bit 3 */
+
+#define SDIO_DCTRL_RWSTART 0x0100U /*!<Read wait start */
+#define SDIO_DCTRL_RWSTOP 0x0200U /*!<Read wait stop */
+#define SDIO_DCTRL_RWMOD 0x0400U /*!<Read wait mode */
+#define SDIO_DCTRL_SDIOEN 0x0800U /*!<SD I/O enable functions */
+
+/****************** Bit definition for SDIO_DCOUNT register *****************/
+#define SDIO_DCOUNT_DATACOUNT 0x01FFFFFFU /*!<Data count value */
+
+/****************** Bit definition for SDIO_STA register ********************/
+#define SDIO_STA_CCRCFAIL 0x00000001U /*!<Command response received (CRC check failed) */
+#define SDIO_STA_DCRCFAIL 0x00000002U /*!<Data block sent/received (CRC check failed) */
+#define SDIO_STA_CTIMEOUT 0x00000004U /*!<Command response timeout */
+#define SDIO_STA_DTIMEOUT 0x00000008U /*!<Data timeout */
+#define SDIO_STA_TXUNDERR 0x00000010U /*!<Transmit FIFO underrun error */
+#define SDIO_STA_RXOVERR 0x00000020U /*!<Received FIFO overrun error */
+#define SDIO_STA_CMDREND 0x00000040U /*!<Command response received (CRC check passed) */
+#define SDIO_STA_CMDSENT 0x00000080U /*!<Command sent (no response required) */
+#define SDIO_STA_DATAEND 0x00000100U /*!<Data end (data counter, SDIDCOUNT, is zero) */
+#define SDIO_STA_STBITERR 0x00000200U /*!<Start bit not detected on all data signals in wide bus mode */
+#define SDIO_STA_DBCKEND 0x00000400U /*!<Data block sent/received (CRC check passed) */
+#define SDIO_STA_CMDACT 0x00000800U /*!<Command transfer in progress */
+#define SDIO_STA_TXACT 0x00001000U /*!<Data transmit in progress */
+#define SDIO_STA_RXACT 0x00002000U /*!<Data receive in progress */
+#define SDIO_STA_TXFIFOHE 0x00004000U /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
+#define SDIO_STA_RXFIFOHF 0x00008000U /*!<Receive FIFO Half Full: there are at least 8 words in the FIFO */
+#define SDIO_STA_TXFIFOF 0x00010000U /*!<Transmit FIFO full */
+#define SDIO_STA_RXFIFOF 0x00020000U /*!<Receive FIFO full */
+#define SDIO_STA_TXFIFOE 0x00040000U /*!<Transmit FIFO empty */
+#define SDIO_STA_RXFIFOE 0x00080000U /*!<Receive FIFO empty */
+#define SDIO_STA_TXDAVL 0x00100000U /*!<Data available in transmit FIFO */
+#define SDIO_STA_RXDAVL 0x00200000U /*!<Data available in receive FIFO */
+#define SDIO_STA_SDIOIT 0x00400000U /*!<SDIO interrupt received */
+#define SDIO_STA_CEATAEND 0x00800000U /*!<CE-ATA command completion signal received for CMD61 */
+
+/******************* Bit definition for SDIO_ICR register *******************/
+#define SDIO_ICR_CCRCFAILC 0x00000001U /*!<CCRCFAIL flag clear bit */
+#define SDIO_ICR_DCRCFAILC 0x00000002U /*!<DCRCFAIL flag clear bit */
+#define SDIO_ICR_CTIMEOUTC 0x00000004U /*!<CTIMEOUT flag clear bit */
+#define SDIO_ICR_DTIMEOUTC 0x00000008U /*!<DTIMEOUT flag clear bit */
+#define SDIO_ICR_TXUNDERRC 0x00000010U /*!<TXUNDERR flag clear bit */
+#define SDIO_ICR_RXOVERRC 0x00000020U /*!<RXOVERR flag clear bit */
+#define SDIO_ICR_CMDRENDC 0x00000040U /*!<CMDREND flag clear bit */
+#define SDIO_ICR_CMDSENTC 0x00000080U /*!<CMDSENT flag clear bit */
+#define SDIO_ICR_DATAENDC 0x00000100U /*!<DATAEND flag clear bit */
+#define SDIO_ICR_STBITERRC 0x00000200U /*!<STBITERR flag clear bit */
+#define SDIO_ICR_DBCKENDC 0x00000400U /*!<DBCKEND flag clear bit */
+#define SDIO_ICR_SDIOITC 0x00400000U /*!<SDIOIT flag clear bit */
+#define SDIO_ICR_CEATAENDC 0x00800000U /*!<CEATAEND flag clear bit */
+
+/****************** Bit definition for SDIO_MASK register *******************/
+#define SDIO_MASK_CCRCFAILIE 0x00000001U /*!<Command CRC Fail Interrupt Enable */
+#define SDIO_MASK_DCRCFAILIE 0x00000002U /*!<Data CRC Fail Interrupt Enable */
+#define SDIO_MASK_CTIMEOUTIE 0x00000004U /*!<Command TimeOut Interrupt Enable */
+#define SDIO_MASK_DTIMEOUTIE 0x00000008U /*!<Data TimeOut Interrupt Enable */
+#define SDIO_MASK_TXUNDERRIE 0x00000010U /*!<Tx FIFO UnderRun Error Interrupt Enable */
+#define SDIO_MASK_RXOVERRIE 0x00000020U /*!<Rx FIFO OverRun Error Interrupt Enable */
+#define SDIO_MASK_CMDRENDIE 0x00000040U /*!<Command Response Received Interrupt Enable */
+#define SDIO_MASK_CMDSENTIE 0x00000080U /*!<Command Sent Interrupt Enable */
+#define SDIO_MASK_DATAENDIE 0x00000100U /*!<Data End Interrupt Enable */
+#define SDIO_MASK_STBITERRIE 0x00000200U /*!<Start Bit Error Interrupt Enable */
+#define SDIO_MASK_DBCKENDIE 0x00000400U /*!<Data Block End Interrupt Enable */
+#define SDIO_MASK_CMDACTIE 0x00000800U /*!<CCommand Acting Interrupt Enable */
+#define SDIO_MASK_TXACTIE 0x00001000U /*!<Data Transmit Acting Interrupt Enable */
+#define SDIO_MASK_RXACTIE 0x00002000U /*!<Data receive acting interrupt enabled */
+#define SDIO_MASK_TXFIFOHEIE 0x00004000U /*!<Tx FIFO Half Empty interrupt Enable */
+#define SDIO_MASK_RXFIFOHFIE 0x00008000U /*!<Rx FIFO Half Full interrupt Enable */
+#define SDIO_MASK_TXFIFOFIE 0x00010000U /*!<Tx FIFO Full interrupt Enable */
+#define SDIO_MASK_RXFIFOFIE 0x00020000U /*!<Rx FIFO Full interrupt Enable */
+#define SDIO_MASK_TXFIFOEIE 0x00040000U /*!<Tx FIFO Empty interrupt Enable */
+#define SDIO_MASK_RXFIFOEIE 0x00080000U /*!<Rx FIFO Empty interrupt Enable */
+#define SDIO_MASK_TXDAVLIE 0x00100000U /*!<Data available in Tx FIFO interrupt Enable */
+#define SDIO_MASK_RXDAVLIE 0x00200000U /*!<Data available in Rx FIFO interrupt Enable */
+#define SDIO_MASK_SDIOITIE 0x00400000U /*!<SDIO Mode Interrupt Received interrupt Enable */
+#define SDIO_MASK_CEATAENDIE 0x00800000U /*!<CE-ATA command completion signal received Interrupt Enable */
+
+/***************** Bit definition for SDIO_FIFOCNT register *****************/
+#define SDIO_FIFOCNT_FIFOCOUNT 0x00FFFFFFU /*!<Remaining number of words to be written to or read from the FIFO */
+
+/****************** Bit definition for SDIO_FIFO register *******************/
+#define SDIO_FIFO_FIFODATA 0xFFFFFFFFU /*!<Receive and transmit FIFO data */
+
+/******************************************************************************/
+/* */
+/* Serial Peripheral Interface */
+/* */
+/******************************************************************************/
+/******************* Bit definition for SPI_CR1 register ********************/
+#define SPI_CR1_CPHA 0x00000001U /*!<Clock Phase */
+#define SPI_CR1_CPOL 0x00000002U /*!<Clock Polarity */
+#define SPI_CR1_MSTR 0x00000004U /*!<Master Selection */
+
+#define SPI_CR1_BR 0x00000038U /*!<BR[2:0] bits (Baud Rate Control) */
+#define SPI_CR1_BR_0 0x00000008U /*!<Bit 0 */
+#define SPI_CR1_BR_1 0x00000010U /*!<Bit 1 */
+#define SPI_CR1_BR_2 0x00000020U /*!<Bit 2 */
+
+#define SPI_CR1_SPE 0x00000040U /*!<SPI Enable */
+#define SPI_CR1_LSBFIRST 0x00000080U /*!<Frame Format */
+#define SPI_CR1_SSI 0x00000100U /*!<Internal slave select */
+#define SPI_CR1_SSM 0x00000200U /*!<Software slave management */
+#define SPI_CR1_RXONLY 0x00000400U /*!<Receive only */
+#define SPI_CR1_DFF 0x00000800U /*!<Data Frame Format */
+#define SPI_CR1_CRCNEXT 0x00001000U /*!<Transmit CRC next */
+#define SPI_CR1_CRCEN 0x00002000U /*!<Hardware CRC calculation enable */
+#define SPI_CR1_BIDIOE 0x00004000U /*!<Output enable in bidirectional mode */
+#define SPI_CR1_BIDIMODE 0x00008000U /*!<Bidirectional data mode enable */
+
+/******************* Bit definition for SPI_CR2 register ********************/
+#define SPI_CR2_RXDMAEN 0x00000001U /*!<Rx Buffer DMA Enable */
+#define SPI_CR2_TXDMAEN 0x00000002U /*!<Tx Buffer DMA Enable */
+#define SPI_CR2_SSOE 0x00000004U /*!<SS Output Enable */
+#define SPI_CR2_FRF 0x00000010U /*!<Frame Format */
+#define SPI_CR2_ERRIE 0x00000020U /*!<Error Interrupt Enable */
+#define SPI_CR2_RXNEIE 0x00000040U /*!<RX buffer Not Empty Interrupt Enable */
+#define SPI_CR2_TXEIE 0x00000080U /*!<Tx buffer Empty Interrupt Enable */
+
+/******************** Bit definition for SPI_SR register ********************/
+#define SPI_SR_RXNE 0x00000001U /*!<Receive buffer Not Empty */
+#define SPI_SR_TXE 0x00000002U /*!<Transmit buffer Empty */
+#define SPI_SR_CHSIDE 0x00000004U /*!<Channel side */
+#define SPI_SR_UDR 0x00000008U /*!<Underrun flag */
+#define SPI_SR_CRCERR 0x00000010U /*!<CRC Error flag */
+#define SPI_SR_MODF 0x00000020U /*!<Mode fault */
+#define SPI_SR_OVR 0x00000040U /*!<Overrun flag */
+#define SPI_SR_BSY 0x00000080U /*!<Busy flag */
+#define SPI_SR_FRE 0x00000100U /*!<Frame format error flag */
+
+/******************** Bit definition for SPI_DR register ********************/
+#define SPI_DR_DR 0x0000FFFFU /*!<Data Register */
+
+/******************* Bit definition for SPI_CRCPR register ******************/
+#define SPI_CRCPR_CRCPOLY 0x0000FFFFU /*!<CRC polynomial register */
+
+/****************** Bit definition for SPI_RXCRCR register ******************/
+#define SPI_RXCRCR_RXCRC 0x0000FFFFU /*!<Rx CRC Register */
+
+/****************** Bit definition for SPI_TXCRCR register ******************/
+#define SPI_TXCRCR_TXCRC 0x0000FFFFU /*!<Tx CRC Register */
+
+/****************** Bit definition for SPI_I2SCFGR register *****************/
+#define SPI_I2SCFGR_CHLEN 0x00000001U /*!<Channel length (number of bits per audio channel) */
+
+#define SPI_I2SCFGR_DATLEN 0x00000006U /*!<DATLEN[1:0] bits (Data length to be transferred) */
+#define SPI_I2SCFGR_DATLEN_0 0x00000002U /*!<Bit 0 */
+#define SPI_I2SCFGR_DATLEN_1 0x00000004U /*!<Bit 1 */
+
+#define SPI_I2SCFGR_CKPOL 0x00000008U /*!<steady state clock polarity */
+
+#define SPI_I2SCFGR_I2SSTD 0x00000030U /*!<I2SSTD[1:0] bits (I2S standard selection) */
+#define SPI_I2SCFGR_I2SSTD_0 0x00000010U /*!<Bit 0 */
+#define SPI_I2SCFGR_I2SSTD_1 0x00000020U /*!<Bit 1 */
+
+#define SPI_I2SCFGR_PCMSYNC 0x00000080U /*!<PCM frame synchronization */
+
+#define SPI_I2SCFGR_I2SCFG 0x00000300U /*!<I2SCFG[1:0] bits (I2S configuration mode) */
+#define SPI_I2SCFGR_I2SCFG_0 0x00000100U /*!<Bit 0 */
+#define SPI_I2SCFGR_I2SCFG_1 0x00000200U /*!<Bit 1 */
+
+#define SPI_I2SCFGR_I2SE 0x00000400U /*!<I2S Enable */
+#define SPI_I2SCFGR_I2SMOD 0x00000800U /*!<I2S mode selection */
+
+/****************** Bit definition for SPI_I2SPR register *******************/
+#define SPI_I2SPR_I2SDIV 0x000000FFU /*!<I2S Linear prescaler */
+#define SPI_I2SPR_ODD 0x00000100U /*!<Odd factor for the prescaler */
+#define SPI_I2SPR_MCKOE 0x00000200U /*!<Master Clock Output Enable */
+
+/******************************************************************************/
+/* */
+/* SYSCFG */
+/* */
+/******************************************************************************/
+/****************** Bit definition for SYSCFG_MEMRMP register ***************/
+#define SYSCFG_MEMRMP_MEM_MODE 0x00000007U /*!< SYSCFG_Memory Remap Config */
+#define SYSCFG_MEMRMP_MEM_MODE_0 0x00000001U
+#define SYSCFG_MEMRMP_MEM_MODE_1 0x00000002U
+#define SYSCFG_MEMRMP_MEM_MODE_2 0x00000004U
+
+/****************** Bit definition for SYSCFG_PMC register ******************/
+#define SYSCFG_PMC_ADC1DC2 0x00010000U /*!< Refer to AN4073 on how to use this bit */
+
+/***************** Bit definition for SYSCFG_EXTICR1 register ***************/
+#define SYSCFG_EXTICR1_EXTI0 0x000FU /*!<EXTI 0 configuration */
+#define SYSCFG_EXTICR1_EXTI1 0x00F0U /*!<EXTI 1 configuration */
+#define SYSCFG_EXTICR1_EXTI2 0x0F00U /*!<EXTI 2 configuration */
+#define SYSCFG_EXTICR1_EXTI3 0xF000U /*!<EXTI 3 configuration */
+/**
+ * @brief EXTI0 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI0_PA 0x0000U /*!<PA[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PB 0x0001U /*!<PB[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PC 0x0002U /*!<PC[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PD 0x0003U /*!<PD[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PE 0x0004U /*!<PE[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PH 0x0007U /*!<PH[0] pin */
+
+/**
+ * @brief EXTI1 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI1_PA 0x0000U /*!<PA[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PB 0x0010U /*!<PB[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PC 0x0020U /*!<PC[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PD 0x0030U /*!<PD[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PE 0x0040U /*!<PE[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PH 0x0070U /*!<PH[1] pin */
+
+/**
+ * @brief EXTI2 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI2_PA 0x0000U /*!<PA[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PB 0x0100U /*!<PB[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PC 0x0200U /*!<PC[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PD 0x0300U /*!<PD[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PE 0x0400U /*!<PE[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PH 0x0700U /*!<PH[2] pin */
+
+/**
+ * @brief EXTI3 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI3_PA 0x0000U /*!<PA[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PB 0x1000U /*!<PB[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PC 0x2000U /*!<PC[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PD 0x3000U /*!<PD[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PE 0x4000U /*!<PE[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PH 0x7000U /*!<PH[3] pin */
+
+/***************** Bit definition for SYSCFG_EXTICR2 register ***************/
+#define SYSCFG_EXTICR2_EXTI4 0x000FU /*!<EXTI 4 configuration */
+#define SYSCFG_EXTICR2_EXTI5 0x00F0U /*!<EXTI 5 configuration */
+#define SYSCFG_EXTICR2_EXTI6 0x0F00U /*!<EXTI 6 configuration */
+#define SYSCFG_EXTICR2_EXTI7 0xF000U /*!<EXTI 7 configuration */
+/**
+ * @brief EXTI4 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI4_PA 0x0000U /*!<PA[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PB 0x0001U /*!<PB[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PC 0x0002U /*!<PC[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PD 0x0003U /*!<PD[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PE 0x0004U /*!<PE[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PH 0x0007U /*!<PH[4] pin */
+
+/**
+ * @brief EXTI5 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI5_PA 0x0000U /*!<PA[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PB 0x0010U /*!<PB[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PC 0x0020U /*!<PC[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PD 0x0030U /*!<PD[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PE 0x0040U /*!<PE[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PH 0x0070U /*!<PH[5] pin */
+
+/**
+ * @brief EXTI6 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI6_PA 0x0000U /*!<PA[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PB 0x0100U /*!<PB[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PC 0x0200U /*!<PC[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PD 0x0300U /*!<PD[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PE 0x0400U /*!<PE[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PH 0x0700U /*!<PH[6] pin */
+
+/**
+ * @brief EXTI7 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI7_PA 0x0000U /*!<PA[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PB 0x1000U /*!<PB[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PC 0x2000U /*!<PC[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PD 0x3000U /*!<PD[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PE 0x4000U /*!<PE[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PH 0x7000U /*!<PH[7] pin */
+
+
+/***************** Bit definition for SYSCFG_EXTICR3 register ***************/
+#define SYSCFG_EXTICR3_EXTI8 0x000FU /*!<EXTI 8 configuration */
+#define SYSCFG_EXTICR3_EXTI9 0x00F0U /*!<EXTI 9 configuration */
+#define SYSCFG_EXTICR3_EXTI10 0x0F00U /*!<EXTI 10 configuration */
+#define SYSCFG_EXTICR3_EXTI11 0xF000U /*!<EXTI 11 configuration */
+
+/**
+ * @brief EXTI8 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI8_PA 0x0000U /*!<PA[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PB 0x0001U /*!<PB[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PC 0x0002U /*!<PC[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PD 0x0003U /*!<PD[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PE 0x0004U /*!<PE[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PH 0x0007U /*!<PH[8] pin */
+
+/**
+ * @brief EXTI9 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI9_PA 0x0000U /*!<PA[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PB 0x0010U /*!<PB[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PC 0x0020U /*!<PC[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PD 0x0030U /*!<PD[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PE 0x0040U /*!<PE[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PH 0x0070U /*!<PH[9] pin */
+
+/**
+ * @brief EXTI10 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI10_PA 0x0000U /*!<PA[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PB 0x0100U /*!<PB[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PC 0x0200U /*!<PC[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PD 0x0300U /*!<PD[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PE 0x0400U /*!<PE[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PH 0x0700U /*!<PH[10] pin */
+
+/**
+ * @brief EXTI11 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI11_PA 0x0000U /*!<PA[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PB 0x1000U /*!<PB[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PC 0x2000U /*!<PC[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PD 0x3000U /*!<PD[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PE 0x4000U /*!<PE[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PH 0x7000U /*!<PH[11] pin */
+
+/***************** Bit definition for SYSCFG_EXTICR4 register ***************/
+#define SYSCFG_EXTICR4_EXTI12 0x000FU /*!<EXTI 12 configuration */
+#define SYSCFG_EXTICR4_EXTI13 0x00F0U /*!<EXTI 13 configuration */
+#define SYSCFG_EXTICR4_EXTI14 0x0F00U /*!<EXTI 14 configuration */
+#define SYSCFG_EXTICR4_EXTI15 0xF000U /*!<EXTI 15 configuration */
+/**
+ * @brief EXTI12 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI12_PA 0x0000U /*!<PA[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PB 0x0001U /*!<PB[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PC 0x0002U /*!<PC[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PD 0x0003U /*!<PD[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PE 0x0004U /*!<PE[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PH 0x0007U /*!<PH[12] pin */
+
+/**
+ * @brief EXTI13 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI13_PA 0x0000U /*!<PA[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PB 0x0010U /*!<PB[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PC 0x0020U /*!<PC[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PD 0x0030U /*!<PD[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PE 0x0040U /*!<PE[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PH 0x0070U /*!<PH[13] pin */
+
+/**
+ * @brief EXTI14 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI14_PA 0x0000U /*!<PA[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PB 0x0100U /*!<PB[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PC 0x0200U /*!<PC[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PD 0x0300U /*!<PD[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PE 0x0400U /*!<PE[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PH 0x0700U /*!<PH[14] pin */
+
+/**
+ * @brief EXTI15 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI15_PA 0x0000U /*!<PA[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PB 0x1000U /*!<PB[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PC 0x2000U /*!<PC[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PD 0x3000U /*!<PD[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PE 0x4000U /*!<PE[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PH 0x7000U /*!<PH[15] pin */
+
+/****************** Bit definition for SYSCFG_CMPCR register ****************/
+#define SYSCFG_CMPCR_CMP_PD 0x00000001U /*!<Compensation cell ready flag */
+#define SYSCFG_CMPCR_READY 0x00000100U /*!<Compensation cell power-down */
+
+/******************************************************************************/
+/* */
+/* TIM */
+/* */
+/******************************************************************************/
+/******************* Bit definition for TIM_CR1 register ********************/
+#define TIM_CR1_CEN 0x0001U /*!<Counter enable */
+#define TIM_CR1_UDIS 0x0002U /*!<Update disable */
+#define TIM_CR1_URS 0x0004U /*!<Update request source */
+#define TIM_CR1_OPM 0x0008U /*!<One pulse mode */
+#define TIM_CR1_DIR 0x0010U /*!<Direction */
+
+#define TIM_CR1_CMS 0x0060U /*!<CMS[1:0] bits (Center-aligned mode selection) */
+#define TIM_CR1_CMS_0 0x0020U /*!<Bit 0 */
+#define TIM_CR1_CMS_1 0x0040U /*!<Bit 1 */
+
+#define TIM_CR1_ARPE 0x0080U /*!<Auto-reload preload enable */
+
+#define TIM_CR1_CKD 0x0300U /*!<CKD[1:0] bits (clock division) */
+#define TIM_CR1_CKD_0 0x0100U /*!<Bit 0 */
+#define TIM_CR1_CKD_1 0x0200U /*!<Bit 1 */
+
+/******************* Bit definition for TIM_CR2 register ********************/
+#define TIM_CR2_CCPC 0x0001U /*!<Capture/Compare Preloaded Control */
+#define TIM_CR2_CCUS 0x0004U /*!<Capture/Compare Control Update Selection */
+#define TIM_CR2_CCDS 0x0008U /*!<Capture/Compare DMA Selection */
+
+#define TIM_CR2_MMS 0x0070U /*!<MMS[2:0] bits (Master Mode Selection) */
+#define TIM_CR2_MMS_0 0x0010U /*!<Bit 0 */
+#define TIM_CR2_MMS_1 0x0020U /*!<Bit 1 */
+#define TIM_CR2_MMS_2 0x0040U /*!<Bit 2 */
+
+#define TIM_CR2_TI1S 0x0080U /*!<TI1 Selection */
+#define TIM_CR2_OIS1 0x0100U /*!<Output Idle state 1 (OC1 output) */
+#define TIM_CR2_OIS1N 0x0200U /*!<Output Idle state 1 (OC1N output) */
+#define TIM_CR2_OIS2 0x0400U /*!<Output Idle state 2 (OC2 output) */
+#define TIM_CR2_OIS2N 0x0800U /*!<Output Idle state 2 (OC2N output) */
+#define TIM_CR2_OIS3 0x1000U /*!<Output Idle state 3 (OC3 output) */
+#define TIM_CR2_OIS3N 0x2000U /*!<Output Idle state 3 (OC3N output) */
+#define TIM_CR2_OIS4 0x4000U /*!<Output Idle state 4 (OC4 output) */
+
+/******************* Bit definition for TIM_SMCR register *******************/
+#define TIM_SMCR_SMS 0x0007U /*!<SMS[2:0] bits (Slave mode selection) */
+#define TIM_SMCR_SMS_0 0x0001U /*!<Bit 0 */
+#define TIM_SMCR_SMS_1 0x0002U /*!<Bit 1 */
+#define TIM_SMCR_SMS_2 0x0004U /*!<Bit 2 */
+
+#define TIM_SMCR_TS 0x0070U /*!<TS[2:0] bits (Trigger selection) */
+#define TIM_SMCR_TS_0 0x0010U /*!<Bit 0 */
+#define TIM_SMCR_TS_1 0x0020U /*!<Bit 1 */
+#define TIM_SMCR_TS_2 0x0040U /*!<Bit 2 */
+
+#define TIM_SMCR_MSM 0x0080U /*!<Master/slave mode */
+
+#define TIM_SMCR_ETF 0x0F00U /*!<ETF[3:0] bits (External trigger filter) */
+#define TIM_SMCR_ETF_0 0x0100U /*!<Bit 0 */
+#define TIM_SMCR_ETF_1 0x0200U /*!<Bit 1 */
+#define TIM_SMCR_ETF_2 0x0400U /*!<Bit 2 */
+#define TIM_SMCR_ETF_3 0x0800U /*!<Bit 3 */
+
+#define TIM_SMCR_ETPS 0x3000U /*!<ETPS[1:0] bits (External trigger prescaler) */
+#define TIM_SMCR_ETPS_0 0x1000U /*!<Bit 0 */
+#define TIM_SMCR_ETPS_1 0x2000U /*!<Bit 1 */
+
+#define TIM_SMCR_ECE 0x4000U /*!<External clock enable */
+#define TIM_SMCR_ETP 0x8000U /*!<External trigger polarity */
+
+/******************* Bit definition for TIM_DIER register *******************/
+#define TIM_DIER_UIE 0x0001U /*!<Update interrupt enable */
+#define TIM_DIER_CC1IE 0x0002U /*!<Capture/Compare 1 interrupt enable */
+#define TIM_DIER_CC2IE 0x0004U /*!<Capture/Compare 2 interrupt enable */
+#define TIM_DIER_CC3IE 0x0008U /*!<Capture/Compare 3 interrupt enable */
+#define TIM_DIER_CC4IE 0x0010U /*!<Capture/Compare 4 interrupt enable */
+#define TIM_DIER_COMIE 0x0020U /*!<COM interrupt enable */
+#define TIM_DIER_TIE 0x0040U /*!<Trigger interrupt enable */
+#define TIM_DIER_BIE 0x0080U /*!<Break interrupt enable */
+#define TIM_DIER_UDE 0x0100U /*!<Update DMA request enable */
+#define TIM_DIER_CC1DE 0x0200U /*!<Capture/Compare 1 DMA request enable */
+#define TIM_DIER_CC2DE 0x0400U /*!<Capture/Compare 2 DMA request enable */
+#define TIM_DIER_CC3DE 0x0800U /*!<Capture/Compare 3 DMA request enable */
+#define TIM_DIER_CC4DE 0x1000U /*!<Capture/Compare 4 DMA request enable */
+#define TIM_DIER_COMDE 0x2000U /*!<COM DMA request enable */
+#define TIM_DIER_TDE 0x4000U /*!<Trigger DMA request enable */
+
+/******************** Bit definition for TIM_SR register ********************/
+#define TIM_SR_UIF 0x0001U /*!<Update interrupt Flag */
+#define TIM_SR_CC1IF 0x0002U /*!<Capture/Compare 1 interrupt Flag */
+#define TIM_SR_CC2IF 0x0004U /*!<Capture/Compare 2 interrupt Flag */
+#define TIM_SR_CC3IF 0x0008U /*!<Capture/Compare 3 interrupt Flag */
+#define TIM_SR_CC4IF 0x0010U /*!<Capture/Compare 4 interrupt Flag */
+#define TIM_SR_COMIF 0x0020U /*!<COM interrupt Flag */
+#define TIM_SR_TIF 0x0040U /*!<Trigger interrupt Flag */
+#define TIM_SR_BIF 0x0080U /*!<Break interrupt Flag */
+#define TIM_SR_CC1OF 0x0200U /*!<Capture/Compare 1 Overcapture Flag */
+#define TIM_SR_CC2OF 0x0400U /*!<Capture/Compare 2 Overcapture Flag */
+#define TIM_SR_CC3OF 0x0800U /*!<Capture/Compare 3 Overcapture Flag */
+#define TIM_SR_CC4OF 0x1000U /*!<Capture/Compare 4 Overcapture Flag */
+
+/******************* Bit definition for TIM_EGR register ********************/
+#define TIM_EGR_UG 0x01U /*!<Update Generation */
+#define TIM_EGR_CC1G 0x02U /*!<Capture/Compare 1 Generation */
+#define TIM_EGR_CC2G 0x04U /*!<Capture/Compare 2 Generation */
+#define TIM_EGR_CC3G 0x08U /*!<Capture/Compare 3 Generation */
+#define TIM_EGR_CC4G 0x10U /*!<Capture/Compare 4 Generation */
+#define TIM_EGR_COMG 0x20U /*!<Capture/Compare Control Update Generation */
+#define TIM_EGR_TG 0x40U /*!<Trigger Generation */
+#define TIM_EGR_BG 0x80U /*!<Break Generation */
+
+/****************** Bit definition for TIM_CCMR1 register *******************/
+#define TIM_CCMR1_CC1S 0x0003U /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
+#define TIM_CCMR1_CC1S_0 0x0001U /*!<Bit 0 */
+#define TIM_CCMR1_CC1S_1 0x0002U /*!<Bit 1 */
+
+#define TIM_CCMR1_OC1FE 0x0004U /*!<Output Compare 1 Fast enable */
+#define TIM_CCMR1_OC1PE 0x0008U /*!<Output Compare 1 Preload enable */
+
+#define TIM_CCMR1_OC1M 0x0070U /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
+#define TIM_CCMR1_OC1M_0 0x0010U /*!<Bit 0 */
+#define TIM_CCMR1_OC1M_1 0x0020U /*!<Bit 1 */
+#define TIM_CCMR1_OC1M_2 0x0040U /*!<Bit 2 */
+
+#define TIM_CCMR1_OC1CE 0x0080U /*!<Output Compare 1Clear Enable */
+
+#define TIM_CCMR1_CC2S 0x0300U /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
+#define TIM_CCMR1_CC2S_0 0x0100U /*!<Bit 0 */
+#define TIM_CCMR1_CC2S_1 0x0200U /*!<Bit 1 */
+
+#define TIM_CCMR1_OC2FE 0x0400U /*!<Output Compare 2 Fast enable */
+#define TIM_CCMR1_OC2PE 0x0800U /*!<Output Compare 2 Preload enable */
+
+#define TIM_CCMR1_OC2M 0x7000U /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
+#define TIM_CCMR1_OC2M_0 0x1000U /*!<Bit 0 */
+#define TIM_CCMR1_OC2M_1 0x2000U /*!<Bit 1 */
+#define TIM_CCMR1_OC2M_2 0x4000U /*!<Bit 2 */
+
+#define TIM_CCMR1_OC2CE 0x8000U /*!<Output Compare 2 Clear Enable */
+
+/*----------------------------------------------------------------------------*/
+
+#define TIM_CCMR1_IC1PSC 0x000CU /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
+#define TIM_CCMR1_IC1PSC_0 0x0004U /*!<Bit 0 */
+#define TIM_CCMR1_IC1PSC_1 0x0008U /*!<Bit 1 */
+
+#define TIM_CCMR1_IC1F 0x00F0U /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
+#define TIM_CCMR1_IC1F_0 0x0010U /*!<Bit 0 */
+#define TIM_CCMR1_IC1F_1 0x0020U /*!<Bit 1 */
+#define TIM_CCMR1_IC1F_2 0x0040U /*!<Bit 2 */
+#define TIM_CCMR1_IC1F_3 0x0080U /*!<Bit 3 */
+
+#define TIM_CCMR1_IC2PSC 0x0C00U /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
+#define TIM_CCMR1_IC2PSC_0 0x0400U /*!<Bit 0 */
+#define TIM_CCMR1_IC2PSC_1 0x0800U /*!<Bit 1 */
+
+#define TIM_CCMR1_IC2F 0xF000U /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
+#define TIM_CCMR1_IC2F_0 0x1000U /*!<Bit 0 */
+#define TIM_CCMR1_IC2F_1 0x2000U /*!<Bit 1 */
+#define TIM_CCMR1_IC2F_2 0x4000U /*!<Bit 2 */
+#define TIM_CCMR1_IC2F_3 0x8000U /*!<Bit 3 */
+
+/****************** Bit definition for TIM_CCMR2 register *******************/
+#define TIM_CCMR2_CC3S 0x0003U /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
+#define TIM_CCMR2_CC3S_0 0x0001U /*!<Bit 0 */
+#define TIM_CCMR2_CC3S_1 0x0002U /*!<Bit 1 */
+
+#define TIM_CCMR2_OC3FE 0x0004U /*!<Output Compare 3 Fast enable */
+#define TIM_CCMR2_OC3PE 0x0008U /*!<Output Compare 3 Preload enable */
+
+#define TIM_CCMR2_OC3M 0x0070U /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
+#define TIM_CCMR2_OC3M_0 0x0010U /*!<Bit 0 */
+#define TIM_CCMR2_OC3M_1 0x0020U /*!<Bit 1 */
+#define TIM_CCMR2_OC3M_2 0x0040U /*!<Bit 2 */
+
+#define TIM_CCMR2_OC3CE 0x0080U /*!<Output Compare 3 Clear Enable */
+
+#define TIM_CCMR2_CC4S 0x0300U /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
+#define TIM_CCMR2_CC4S_0 0x0100U /*!<Bit 0 */
+#define TIM_CCMR2_CC4S_1 0x0200U /*!<Bit 1 */
+
+#define TIM_CCMR2_OC4FE 0x0400U /*!<Output Compare 4 Fast enable */
+#define TIM_CCMR2_OC4PE 0x0800U /*!<Output Compare 4 Preload enable */
+
+#define TIM_CCMR2_OC4M 0x7000U /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
+#define TIM_CCMR2_OC4M_0 0x1000U /*!<Bit 0 */
+#define TIM_CCMR2_OC4M_1 0x2000U /*!<Bit 1 */
+#define TIM_CCMR2_OC4M_2 0x4000U /*!<Bit 2 */
+
+#define TIM_CCMR2_OC4CE 0x8000U /*!<Output Compare 4 Clear Enable */
+
+/*----------------------------------------------------------------------------*/
+
+#define TIM_CCMR2_IC3PSC 0x000CU /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
+#define TIM_CCMR2_IC3PSC_0 0x0004U /*!<Bit 0 */
+#define TIM_CCMR2_IC3PSC_1 0x0008U /*!<Bit 1 */
+
+#define TIM_CCMR2_IC3F 0x00F0U /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
+#define TIM_CCMR2_IC3F_0 0x0010U /*!<Bit 0 */
+#define TIM_CCMR2_IC3F_1 0x0020U /*!<Bit 1 */
+#define TIM_CCMR2_IC3F_2 0x0040U /*!<Bit 2 */
+#define TIM_CCMR2_IC3F_3 0x0080U /*!<Bit 3 */
+
+#define TIM_CCMR2_IC4PSC 0x0C00U /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
+#define TIM_CCMR2_IC4PSC_0 0x0400U /*!<Bit 0 */
+#define TIM_CCMR2_IC4PSC_1 0x0800U /*!<Bit 1 */
+
+#define TIM_CCMR2_IC4F 0xF000U /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
+#define TIM_CCMR2_IC4F_0 0x1000U /*!<Bit 0 */
+#define TIM_CCMR2_IC4F_1 0x2000U /*!<Bit 1 */
+#define TIM_CCMR2_IC4F_2 0x4000U /*!<Bit 2 */
+#define TIM_CCMR2_IC4F_3 0x8000U /*!<Bit 3 */
+
+/******************* Bit definition for TIM_CCER register *******************/
+#define TIM_CCER_CC1E 0x0001U /*!<Capture/Compare 1 output enable */
+#define TIM_CCER_CC1P 0x0002U /*!<Capture/Compare 1 output Polarity */
+#define TIM_CCER_CC1NE 0x0004U /*!<Capture/Compare 1 Complementary output enable */
+#define TIM_CCER_CC1NP 0x0008U /*!<Capture/Compare 1 Complementary output Polarity */
+#define TIM_CCER_CC2E 0x0010U /*!<Capture/Compare 2 output enable */
+#define TIM_CCER_CC2P 0x0020U /*!<Capture/Compare 2 output Polarity */
+#define TIM_CCER_CC2NE 0x0040U /*!<Capture/Compare 2 Complementary output enable */
+#define TIM_CCER_CC2NP 0x0080U /*!<Capture/Compare 2 Complementary output Polarity */
+#define TIM_CCER_CC3E 0x0100U /*!<Capture/Compare 3 output enable */
+#define TIM_CCER_CC3P 0x0200U /*!<Capture/Compare 3 output Polarity */
+#define TIM_CCER_CC3NE 0x0400U /*!<Capture/Compare 3 Complementary output enable */
+#define TIM_CCER_CC3NP 0x0800U /*!<Capture/Compare 3 Complementary output Polarity */
+#define TIM_CCER_CC4E 0x1000U /*!<Capture/Compare 4 output enable */
+#define TIM_CCER_CC4P 0x2000U /*!<Capture/Compare 4 output Polarity */
+#define TIM_CCER_CC4NP 0x8000U /*!<Capture/Compare 4 Complementary output Polarity */
+
+/******************* Bit definition for TIM_CNT register ********************/
+#define TIM_CNT_CNT 0xFFFFU /*!<Counter Value */
+
+/******************* Bit definition for TIM_PSC register ********************/
+#define TIM_PSC_PSC 0xFFFFU /*!<Prescaler Value */
+
+/******************* Bit definition for TIM_ARR register ********************/
+#define TIM_ARR_ARR 0xFFFFU /*!<actual auto-reload Value */
+
+/******************* Bit definition for TIM_RCR register ********************/
+#define TIM_RCR_REP 0xFFU /*!<Repetition Counter Value */
+
+/******************* Bit definition for TIM_CCR1 register *******************/
+#define TIM_CCR1_CCR1 0xFFFFU /*!<Capture/Compare 1 Value */
+
+/******************* Bit definition for TIM_CCR2 register *******************/
+#define TIM_CCR2_CCR2 0xFFFFU /*!<Capture/Compare 2 Value */
+
+/******************* Bit definition for TIM_CCR3 register *******************/
+#define TIM_CCR3_CCR3 0xFFFFU /*!<Capture/Compare 3 Value */
+
+/******************* Bit definition for TIM_CCR4 register *******************/
+#define TIM_CCR4_CCR4 0xFFFFU /*!<Capture/Compare 4 Value */
+
+/******************* Bit definition for TIM_BDTR register *******************/
+#define TIM_BDTR_DTG 0x00FFU /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
+#define TIM_BDTR_DTG_0 0x0001U /*!<Bit 0 */
+#define TIM_BDTR_DTG_1 0x0002U /*!<Bit 1 */
+#define TIM_BDTR_DTG_2 0x0004U /*!<Bit 2 */
+#define TIM_BDTR_DTG_3 0x0008U /*!<Bit 3 */
+#define TIM_BDTR_DTG_4 0x0010U /*!<Bit 4 */
+#define TIM_BDTR_DTG_5 0x0020U /*!<Bit 5 */
+#define TIM_BDTR_DTG_6 0x0040U /*!<Bit 6 */
+#define TIM_BDTR_DTG_7 0x0080U /*!<Bit 7 */
+
+#define TIM_BDTR_LOCK 0x0300U /*!<LOCK[1:0] bits (Lock Configuration) */
+#define TIM_BDTR_LOCK_0 0x0100U /*!<Bit 0 */
+#define TIM_BDTR_LOCK_1 0x0200U /*!<Bit 1 */
+
+#define TIM_BDTR_OSSI 0x0400U /*!<Off-State Selection for Idle mode */
+#define TIM_BDTR_OSSR 0x0800U /*!<Off-State Selection for Run mode */
+#define TIM_BDTR_BKE 0x1000U /*!<Break enable */
+#define TIM_BDTR_BKP 0x2000U /*!<Break Polarity */
+#define TIM_BDTR_AOE 0x4000U /*!<Automatic Output enable */
+#define TIM_BDTR_MOE 0x8000U /*!<Main Output enable */
+
+/******************* Bit definition for TIM_DCR register ********************/
+#define TIM_DCR_DBA 0x001FU /*!<DBA[4:0] bits (DMA Base Address) */
+#define TIM_DCR_DBA_0 0x0001U /*!<Bit 0 */
+#define TIM_DCR_DBA_1 0x0002U /*!<Bit 1 */
+#define TIM_DCR_DBA_2 0x0004U /*!<Bit 2 */
+#define TIM_DCR_DBA_3 0x0008U /*!<Bit 3 */
+#define TIM_DCR_DBA_4 0x0010U /*!<Bit 4 */
+
+#define TIM_DCR_DBL 0x1F00U /*!<DBL[4:0] bits (DMA Burst Length) */
+#define TIM_DCR_DBL_0 0x0100U /*!<Bit 0 */
+#define TIM_DCR_DBL_1 0x0200U /*!<Bit 1 */
+#define TIM_DCR_DBL_2 0x0400U /*!<Bit 2 */
+#define TIM_DCR_DBL_3 0x0800U /*!<Bit 3 */
+#define TIM_DCR_DBL_4 0x1000U /*!<Bit 4 */
+
+/******************* Bit definition for TIM_DMAR register *******************/
+#define TIM_DMAR_DMAB 0xFFFFU /*!<DMA register for burst accesses */
+
+/******************* Bit definition for TIM_OR register *********************/
+#define TIM_OR_TI4_RMP 0x00C0U /*!<TI4_RMP[1:0] bits (TIM5 Input 4 remap) */
+#define TIM_OR_TI4_RMP_0 0x0040U /*!<Bit 0 */
+#define TIM_OR_TI4_RMP_1 0x0080U /*!<Bit 1 */
+#define TIM_OR_ITR1_RMP 0x0C00U /*!<ITR1_RMP[1:0] bits (TIM2 Internal trigger 1 remap) */
+#define TIM_OR_ITR1_RMP_0 0x0400U /*!<Bit 0 */
+#define TIM_OR_ITR1_RMP_1 0x0800U /*!<Bit 1 */
+
+
+/******************************************************************************/
+/* */
+/* Universal Synchronous Asynchronous Receiver Transmitter */
+/* */
+/******************************************************************************/
+/******************* Bit definition for USART_SR register *******************/
+#define USART_SR_PE 0x0001U /*!<Parity Error */
+#define USART_SR_FE 0x0002U /*!<Framing Error */
+#define USART_SR_NE 0x0004U /*!<Noise Error Flag */
+#define USART_SR_ORE 0x0008U /*!<OverRun Error */
+#define USART_SR_IDLE 0x0010U /*!<IDLE line detected */
+#define USART_SR_RXNE 0x0020U /*!<Read Data Register Not Empty */
+#define USART_SR_TC 0x0040U /*!<Transmission Complete */
+#define USART_SR_TXE 0x0080U /*!<Transmit Data Register Empty */
+#define USART_SR_LBD 0x0100U /*!<LIN Break Detection Flag */
+#define USART_SR_CTS 0x0200U /*!<CTS Flag */
+
+/******************* Bit definition for USART_DR register *******************/
+#define USART_DR_DR 0x01FFU /*!<Data value */
+
+/****************** Bit definition for USART_BRR register *******************/
+#define USART_BRR_DIV_Fraction 0x000FU /*!<Fraction of USARTDIV */
+#define USART_BRR_DIV_Mantissa 0xFFF0U /*!<Mantissa of USARTDIV */
+
+/****************** Bit definition for USART_CR1 register *******************/
+#define USART_CR1_SBK 0x0001U /*!<Send Break */
+#define USART_CR1_RWU 0x0002U /*!<Receiver wakeup */
+#define USART_CR1_RE 0x0004U /*!<Receiver Enable */
+#define USART_CR1_TE 0x0008U /*!<Transmitter Enable */
+#define USART_CR1_IDLEIE 0x0010U /*!<IDLE Interrupt Enable */
+#define USART_CR1_RXNEIE 0x0020U /*!<RXNE Interrupt Enable */
+#define USART_CR1_TCIE 0x0040U /*!<Transmission Complete Interrupt Enable */
+#define USART_CR1_TXEIE 0x0080U /*!<PE Interrupt Enable */
+#define USART_CR1_PEIE 0x0100U /*!<PE Interrupt Enable */
+#define USART_CR1_PS 0x0200U /*!<Parity Selection */
+#define USART_CR1_PCE 0x0400U /*!<Parity Control Enable */
+#define USART_CR1_WAKE 0x0800U /*!<Wakeup method */
+#define USART_CR1_M 0x1000U /*!<Word length */
+#define USART_CR1_UE 0x2000U /*!<USART Enable */
+#define USART_CR1_OVER8 0x8000U /*!<USART Oversampling by 8 enable */
+
+/****************** Bit definition for USART_CR2 register *******************/
+#define USART_CR2_ADD 0x000FU /*!<Address of the USART node */
+#define USART_CR2_LBDL 0x0020U /*!<LIN Break Detection Length */
+#define USART_CR2_LBDIE 0x0040U /*!<LIN Break Detection Interrupt Enable */
+#define USART_CR2_LBCL 0x0100U /*!<Last Bit Clock pulse */
+#define USART_CR2_CPHA 0x0200U /*!<Clock Phase */
+#define USART_CR2_CPOL 0x0400U /*!<Clock Polarity */
+#define USART_CR2_CLKEN 0x0800U /*!<Clock Enable */
+
+#define USART_CR2_STOP 0x3000U /*!<STOP[1:0] bits (STOP bits) */
+#define USART_CR2_STOP_0 0x1000U /*!<Bit 0 */
+#define USART_CR2_STOP_1 0x2000U /*!<Bit 1 */
+
+#define USART_CR2_LINEN 0x4000U /*!<LIN mode enable */
+
+/****************** Bit definition for USART_CR3 register *******************/
+#define USART_CR3_EIE 0x0001U /*!<Error Interrupt Enable */
+#define USART_CR3_IREN 0x0002U /*!<IrDA mode Enable */
+#define USART_CR3_IRLP 0x0004U /*!<IrDA Low-Power */
+#define USART_CR3_HDSEL 0x0008U /*!<Half-Duplex Selection */
+#define USART_CR3_NACK 0x0010U /*!<Smartcard NACK enable */
+#define USART_CR3_SCEN 0x0020U /*!<Smartcard mode enable */
+#define USART_CR3_DMAR 0x0040U /*!<DMA Enable Receiver */
+#define USART_CR3_DMAT 0x0080U /*!<DMA Enable Transmitter */
+#define USART_CR3_RTSE 0x0100U /*!<RTS Enable */
+#define USART_CR3_CTSE 0x0200U /*!<CTS Enable */
+#define USART_CR3_CTSIE 0x0400U /*!<CTS Interrupt Enable */
+#define USART_CR3_ONEBIT 0x0800U /*!<USART One bit method enable */
+
+/****************** Bit definition for USART_GTPR register ******************/
+#define USART_GTPR_PSC 0x00FFU /*!<PSC[7:0] bits (Prescaler value) */
+#define USART_GTPR_PSC_0 0x0001U /*!<Bit 0 */
+#define USART_GTPR_PSC_1 0x0002U /*!<Bit 1 */
+#define USART_GTPR_PSC_2 0x0004U /*!<Bit 2 */
+#define USART_GTPR_PSC_3 0x0008U /*!<Bit 3 */
+#define USART_GTPR_PSC_4 0x0010U /*!<Bit 4 */
+#define USART_GTPR_PSC_5 0x0020U /*!<Bit 5 */
+#define USART_GTPR_PSC_6 0x0040U /*!<Bit 6 */
+#define USART_GTPR_PSC_7 0x0080U /*!<Bit 7 */
+
+#define USART_GTPR_GT 0xFF00U /*!<Guard time value */
+
+/******************************************************************************/
+/* */
+/* Window WATCHDOG */
+/* */
+/******************************************************************************/
+/******************* Bit definition for WWDG_CR register ********************/
+#define WWDG_CR_T 0x7FU /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
+#define WWDG_CR_T_0 0x01U /*!<Bit 0 */
+#define WWDG_CR_T_1 0x02U /*!<Bit 1 */
+#define WWDG_CR_T_2 0x04U /*!<Bit 2 */
+#define WWDG_CR_T_3 0x08U /*!<Bit 3 */
+#define WWDG_CR_T_4 0x10U /*!<Bit 4 */
+#define WWDG_CR_T_5 0x20U /*!<Bit 5 */
+#define WWDG_CR_T_6 0x40U /*!<Bit 6 */
+/* Legacy defines */
+#define WWDG_CR_T0 WWDG_CR_T_0
+#define WWDG_CR_T1 WWDG_CR_T_1
+#define WWDG_CR_T2 WWDG_CR_T_2
+#define WWDG_CR_T3 WWDG_CR_T_3
+#define WWDG_CR_T4 WWDG_CR_T_4
+#define WWDG_CR_T5 WWDG_CR_T_5
+#define WWDG_CR_T6 WWDG_CR_T_6
+
+#define WWDG_CR_WDGA 0x80U /*!<Activation bit */
+
+/******************* Bit definition for WWDG_CFR register *******************/
+#define WWDG_CFR_W 0x007FU /*!<W[6:0] bits (7-bit window value) */
+#define WWDG_CFR_W_0 0x0001U /*!<Bit 0 */
+#define WWDG_CFR_W_1 0x0002U /*!<Bit 1 */
+#define WWDG_CFR_W_2 0x0004U /*!<Bit 2 */
+#define WWDG_CFR_W_3 0x0008U /*!<Bit 3 */
+#define WWDG_CFR_W_4 0x0010U /*!<Bit 4 */
+#define WWDG_CFR_W_5 0x0020U /*!<Bit 5 */
+#define WWDG_CFR_W_6 0x0040U /*!<Bit 6 */
+/* Legacy defines */
+#define WWDG_CFR_W0 WWDG_CFR_W_0
+#define WWDG_CFR_W1 WWDG_CFR_W_1
+#define WWDG_CFR_W2 WWDG_CFR_W_2
+#define WWDG_CFR_W3 WWDG_CFR_W_3
+#define WWDG_CFR_W4 WWDG_CFR_W_4
+#define WWDG_CFR_W5 WWDG_CFR_W_5
+#define WWDG_CFR_W6 WWDG_CFR_W_6
+
+#define WWDG_CFR_WDGTB 0x0180U /*!<WDGTB[1:0] bits (Timer Base) */
+#define WWDG_CFR_WDGTB_0 0x0080U /*!<Bit 0 */
+#define WWDG_CFR_WDGTB_1 0x0100U /*!<Bit 1 */
+/* Legacy defines */
+#define WWDG_CFR_WDGTB0 WWDG_CFR_WDGTB_0
+#define WWDG_CFR_WDGTB1 WWDG_CFR_WDGTB_1
+
+#define WWDG_CFR_EWI 0x0200U /*!<Early Wakeup Interrupt */
+
+/******************* Bit definition for WWDG_SR register ********************/
+#define WWDG_SR_EWIF 0x01U /*!<Early Wakeup Interrupt Flag */
+
+
+/******************************************************************************/
+/* */
+/* DBG */
+/* */
+/******************************************************************************/
+/******************** Bit definition for DBGMCU_IDCODE register *************/
+#define DBGMCU_IDCODE_DEV_ID 0x00000FFFU
+#define DBGMCU_IDCODE_REV_ID 0xFFFF0000U
+
+/******************** Bit definition for DBGMCU_CR register *****************/
+#define DBGMCU_CR_DBG_SLEEP 0x00000001U
+#define DBGMCU_CR_DBG_STOP 0x00000002U
+#define DBGMCU_CR_DBG_STANDBY 0x00000004U
+#define DBGMCU_CR_TRACE_IOEN 0x00000020U
+
+#define DBGMCU_CR_TRACE_MODE 0x000000C0U
+#define DBGMCU_CR_TRACE_MODE_0 0x00000040U/*!<Bit 0 */
+#define DBGMCU_CR_TRACE_MODE_1 0x00000080U/*!<Bit 1 */
+
+/******************** Bit definition for DBGMCU_APB1_FZ register ************/
+#define DBGMCU_APB1_FZ_DBG_TIM2_STOP 0x00000001U
+#define DBGMCU_APB1_FZ_DBG_TIM3_STOP 0x00000002U
+#define DBGMCU_APB1_FZ_DBG_TIM4_STOP 0x00000004U
+#define DBGMCU_APB1_FZ_DBG_TIM5_STOP 0x00000008U
+#define DBGMCU_APB1_FZ_DBG_TIM6_STOP 0x00000010U
+#define DBGMCU_APB1_FZ_DBG_TIM7_STOP 0x00000020U
+#define DBGMCU_APB1_FZ_DBG_TIM12_STOP 0x00000040U
+#define DBGMCU_APB1_FZ_DBG_TIM13_STOP 0x00000080U
+#define DBGMCU_APB1_FZ_DBG_TIM14_STOP 0x00000100U
+#define DBGMCU_APB1_FZ_DBG_RTC_STOP 0x00000400U
+#define DBGMCU_APB1_FZ_DBG_WWDG_STOP 0x00000800U
+#define DBGMCU_APB1_FZ_DBG_IWDG_STOP 0x00001000U
+#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT 0x00200000U
+#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT 0x00400000U
+#define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT 0x00800000U
+#define DBGMCU_APB1_FZ_DBG_CAN1_STOP 0x02000000U
+#define DBGMCU_APB1_FZ_DBG_CAN2_STOP 0x04000000U
+/* Old IWDGSTOP bit definition, maintained for legacy purpose */
+#define DBGMCU_APB1_FZ_DBG_IWDEG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP
+
+/******************** Bit definition for DBGMCU_APB2_FZ register ************/
+#define DBGMCU_APB2_FZ_DBG_TIM1_STOP 0x00000001U
+#define DBGMCU_APB2_FZ_DBG_TIM8_STOP 0x00000002U
+#define DBGMCU_APB2_FZ_DBG_TIM9_STOP 0x00010000U
+#define DBGMCU_APB2_FZ_DBG_TIM10_STOP 0x00020000U
+#define DBGMCU_APB2_FZ_DBG_TIM11_STOP 0x00040000U
+
+/******************************************************************************/
+/* */
+/* USB_OTG */
+/* */
+/******************************************************************************/
+/******************** Bit definition forUSB_OTG_GOTGCTL register ********************/
+#define USB_OTG_GOTGCTL_SRQSCS 0x00000001U /*!< Session request success */
+#define USB_OTG_GOTGCTL_SRQ 0x00000002U /*!< Session request */
+#define USB_OTG_GOTGCTL_HNGSCS 0x00000100U /*!< Host negotiation success */
+#define USB_OTG_GOTGCTL_HNPRQ 0x00000200U /*!< HNP request */
+#define USB_OTG_GOTGCTL_HSHNPEN 0x00000400U /*!< Host set HNP enable */
+#define USB_OTG_GOTGCTL_DHNPEN 0x00000800U /*!< Device HNP enabled */
+#define USB_OTG_GOTGCTL_CIDSTS 0x00010000U /*!< Connector ID status */
+#define USB_OTG_GOTGCTL_DBCT 0x00020000U /*!< Long/short debounce time */
+#define USB_OTG_GOTGCTL_ASVLD 0x00040000U /*!< A-session valid */
+#define USB_OTG_GOTGCTL_BSVLD 0x00080000U /*!< B-session valid */
+
+/******************** Bit definition forUSB_OTG_HCFG register ********************/
+
+#define USB_OTG_HCFG_FSLSPCS 0x00000003U /*!< FS/LS PHY clock select */
+#define USB_OTG_HCFG_FSLSPCS_0 0x00000001U /*!<Bit 0 */
+#define USB_OTG_HCFG_FSLSPCS_1 0x00000002U /*!<Bit 1 */
+#define USB_OTG_HCFG_FSLSS 0x00000004U /*!< FS- and LS-only support */
+
+/******************** Bit definition forUSB_OTG_DCFG register ********************/
+
+#define USB_OTG_DCFG_DSPD 0x00000003U /*!< Device speed */
+#define USB_OTG_DCFG_DSPD_0 0x00000001U /*!<Bit 0 */
+#define USB_OTG_DCFG_DSPD_1 0x00000002U /*!<Bit 1 */
+#define USB_OTG_DCFG_NZLSOHSK 0x00000004U /*!< Nonzero-length status OUT handshake */
+
+#define USB_OTG_DCFG_DAD 0x000007F0U /*!< Device address */
+#define USB_OTG_DCFG_DAD_0 0x00000010U /*!<Bit 0 */
+#define USB_OTG_DCFG_DAD_1 0x00000020U /*!<Bit 1 */
+#define USB_OTG_DCFG_DAD_2 0x00000040U /*!<Bit 2 */
+#define USB_OTG_DCFG_DAD_3 0x00000080U /*!<Bit 3 */
+#define USB_OTG_DCFG_DAD_4 0x00000100U /*!<Bit 4 */
+#define USB_OTG_DCFG_DAD_5 0x00000200U /*!<Bit 5 */
+#define USB_OTG_DCFG_DAD_6 0x00000400U /*!<Bit 6 */
+
+#define USB_OTG_DCFG_PFIVL 0x00001800U /*!< Periodic (micro)frame interval */
+#define USB_OTG_DCFG_PFIVL_0 0x00000800U /*!<Bit 0 */
+#define USB_OTG_DCFG_PFIVL_1 0x00001000U /*!<Bit 1 */
+
+#define USB_OTG_DCFG_PERSCHIVL 0x03000000U /*!< Periodic scheduling interval */
+#define USB_OTG_DCFG_PERSCHIVL_0 0x01000000U /*!<Bit 0 */
+#define USB_OTG_DCFG_PERSCHIVL_1 0x02000000U /*!<Bit 1 */
+
+/******************** Bit definition forUSB_OTG_PCGCR register ********************/
+#define USB_OTG_PCGCR_STPPCLK 0x00000001U /*!< Stop PHY clock */
+#define USB_OTG_PCGCR_GATEHCLK 0x00000002U /*!< Gate HCLK */
+#define USB_OTG_PCGCR_PHYSUSP 0x00000010U /*!< PHY suspended */
+
+/******************** Bit definition forUSB_OTG_GOTGINT register ********************/
+#define USB_OTG_GOTGINT_SEDET 0x00000004U /*!< Session end detected */
+#define USB_OTG_GOTGINT_SRSSCHG 0x00000100U /*!< Session request success status change */
+#define USB_OTG_GOTGINT_HNSSCHG 0x00000200U /*!< Host negotiation success status change */
+#define USB_OTG_GOTGINT_HNGDET 0x00020000U /*!< Host negotiation detected */
+#define USB_OTG_GOTGINT_ADTOCHG 0x00040000U /*!< A-device timeout change */
+#define USB_OTG_GOTGINT_DBCDNE 0x00080000U /*!< Debounce done */
+
+/******************** Bit definition forUSB_OTG_DCTL register ********************/
+#define USB_OTG_DCTL_RWUSIG 0x00000001U /*!< Remote wakeup signaling */
+#define USB_OTG_DCTL_SDIS 0x00000002U /*!< Soft disconnect */
+#define USB_OTG_DCTL_GINSTS 0x00000004U /*!< Global IN NAK status */
+#define USB_OTG_DCTL_GONSTS 0x00000008U /*!< Global OUT NAK status */
+
+#define USB_OTG_DCTL_TCTL 0x00000070U /*!< Test control */
+#define USB_OTG_DCTL_TCTL_0 0x00000010U /*!<Bit 0 */
+#define USB_OTG_DCTL_TCTL_1 0x00000020U /*!<Bit 1 */
+#define USB_OTG_DCTL_TCTL_2 0x00000040U /*!<Bit 2 */
+#define USB_OTG_DCTL_SGINAK 0x00000080U /*!< Set global IN NAK */
+#define USB_OTG_DCTL_CGINAK 0x00000100U /*!< Clear global IN NAK */
+#define USB_OTG_DCTL_SGONAK 0x00000200U /*!< Set global OUT NAK */
+#define USB_OTG_DCTL_CGONAK 0x00000400U /*!< Clear global OUT NAK */
+#define USB_OTG_DCTL_POPRGDNE 0x00000800U /*!< Power-on programming done */
+
+/******************** Bit definition forUSB_OTG_HFIR register ********************/
+#define USB_OTG_HFIR_FRIVL 0x0000FFFFU /*!< Frame interval */
+
+/******************** Bit definition forUSB_OTG_HFNUM register ********************/
+#define USB_OTG_HFNUM_FRNUM 0x0000FFFFU /*!< Frame number */
+#define USB_OTG_HFNUM_FTREM 0xFFFF0000U /*!< Frame time remaining */
+
+/******************** Bit definition forUSB_OTG_DSTS register ********************/
+#define USB_OTG_DSTS_SUSPSTS 0x00000001U /*!< Suspend status */
+
+#define USB_OTG_DSTS_ENUMSPD 0x00000006U /*!< Enumerated speed */
+#define USB_OTG_DSTS_ENUMSPD_0 0x00000002U /*!<Bit 0 */
+#define USB_OTG_DSTS_ENUMSPD_1 0x00000004U /*!<Bit 1 */
+#define USB_OTG_DSTS_EERR 0x00000008U /*!< Erratic error */
+#define USB_OTG_DSTS_FNSOF 0x003FFF00U /*!< Frame number of the received SOF */
+
+/******************** Bit definition forUSB_OTG_GAHBCFG register ********************/
+#define USB_OTG_GAHBCFG_GINT 0x00000001U /*!< Global interrupt mask */
+
+#define USB_OTG_GAHBCFG_HBSTLEN 0x0000001EU /*!< Burst length/type */
+#define USB_OTG_GAHBCFG_HBSTLEN_0 0x00000002U /*!<Bit 0 */
+#define USB_OTG_GAHBCFG_HBSTLEN_1 0x00000004U /*!<Bit 1 */
+#define USB_OTG_GAHBCFG_HBSTLEN_2 0x00000008U /*!<Bit 2 */
+#define USB_OTG_GAHBCFG_HBSTLEN_3 0x00000010U /*!<Bit 3 */
+#define USB_OTG_GAHBCFG_DMAEN 0x00000020U /*!< DMA enable */
+#define USB_OTG_GAHBCFG_TXFELVL 0x00000080U /*!< TxFIFO empty level */
+#define USB_OTG_GAHBCFG_PTXFELVL 0x00000100U /*!< Periodic TxFIFO empty level */
+
+/******************** Bit definition forUSB_OTG_GUSBCFG register ********************/
+
+#define USB_OTG_GUSBCFG_TOCAL 0x00000007U /*!< FS timeout calibration */
+#define USB_OTG_GUSBCFG_TOCAL_0 0x00000001U /*!<Bit 0 */
+#define USB_OTG_GUSBCFG_TOCAL_1 0x00000002U /*!<Bit 1 */
+#define USB_OTG_GUSBCFG_TOCAL_2 0x00000004U /*!<Bit 2 */
+#define USB_OTG_GUSBCFG_PHYSEL 0x00000040U /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */
+#define USB_OTG_GUSBCFG_SRPCAP 0x00000100U /*!< SRP-capable */
+#define USB_OTG_GUSBCFG_HNPCAP 0x00000200U /*!< HNP-capable */
+
+#define USB_OTG_GUSBCFG_TRDT 0x00003C00U /*!< USB turnaround time */
+#define USB_OTG_GUSBCFG_TRDT_0 0x00000400U /*!<Bit 0 */
+#define USB_OTG_GUSBCFG_TRDT_1 0x00000800U /*!<Bit 1 */
+#define USB_OTG_GUSBCFG_TRDT_2 0x00001000U /*!<Bit 2 */
+#define USB_OTG_GUSBCFG_TRDT_3 0x00002000U /*!<Bit 3 */
+#define USB_OTG_GUSBCFG_PHYLPCS 0x00008000U /*!< PHY Low-power clock select */
+#define USB_OTG_GUSBCFG_ULPIFSLS 0x00020000U /*!< ULPI FS/LS select */
+#define USB_OTG_GUSBCFG_ULPIAR 0x00040000U /*!< ULPI Auto-resume */
+#define USB_OTG_GUSBCFG_ULPICSM 0x00080000U /*!< ULPI Clock SuspendM */
+#define USB_OTG_GUSBCFG_ULPIEVBUSD 0x00100000U /*!< ULPI External VBUS Drive */
+#define USB_OTG_GUSBCFG_ULPIEVBUSI 0x00200000U /*!< ULPI external VBUS indicator */
+#define USB_OTG_GUSBCFG_TSDPS 0x00400000U /*!< TermSel DLine pulsing selection */
+#define USB_OTG_GUSBCFG_PCCI 0x00800000U /*!< Indicator complement */
+#define USB_OTG_GUSBCFG_PTCI 0x01000000U /*!< Indicator pass through */
+#define USB_OTG_GUSBCFG_ULPIIPD 0x02000000U /*!< ULPI interface protect disable */
+#define USB_OTG_GUSBCFG_FHMOD 0x20000000U /*!< Forced host mode */
+#define USB_OTG_GUSBCFG_FDMOD 0x40000000U /*!< Forced peripheral mode */
+#define USB_OTG_GUSBCFG_CTXPKT 0x80000000U /*!< Corrupt Tx packet */
+
+/******************** Bit definition forUSB_OTG_GRSTCTL register ********************/
+#define USB_OTG_GRSTCTL_CSRST 0x00000001U /*!< Core soft reset */
+#define USB_OTG_GRSTCTL_HSRST 0x00000002U /*!< HCLK soft reset */
+#define USB_OTG_GRSTCTL_FCRST 0x00000004U /*!< Host frame counter reset */
+#define USB_OTG_GRSTCTL_RXFFLSH 0x00000010U /*!< RxFIFO flush */
+#define USB_OTG_GRSTCTL_TXFFLSH 0x00000020U /*!< TxFIFO flush */
+
+#define USB_OTG_GRSTCTL_TXFNUM 0x000007C0U /*!< TxFIFO number */
+#define USB_OTG_GRSTCTL_TXFNUM_0 0x00000040U /*!<Bit 0 */
+#define USB_OTG_GRSTCTL_TXFNUM_1 0x00000080U /*!<Bit 1 */
+#define USB_OTG_GRSTCTL_TXFNUM_2 0x00000100U /*!<Bit 2 */
+#define USB_OTG_GRSTCTL_TXFNUM_3 0x00000200U /*!<Bit 3 */
+#define USB_OTG_GRSTCTL_TXFNUM_4 0x00000400U /*!<Bit 4 */
+#define USB_OTG_GRSTCTL_DMAREQ 0x40000000U /*!< DMA request signal */
+#define USB_OTG_GRSTCTL_AHBIDL 0x80000000U /*!< AHB master idle */
+
+/******************** Bit definition forUSB_OTG_DIEPMSK register ********************/
+#define USB_OTG_DIEPMSK_XFRCM 0x00000001U /*!< Transfer completed interrupt mask */
+#define USB_OTG_DIEPMSK_EPDM 0x00000002U /*!< Endpoint disabled interrupt mask */
+#define USB_OTG_DIEPMSK_TOM 0x00000008U /*!< Timeout condition mask (nonisochronous endpoints) */
+#define USB_OTG_DIEPMSK_ITTXFEMSK 0x00000010U /*!< IN token received when TxFIFO empty mask */
+#define USB_OTG_DIEPMSK_INEPNMM 0x00000020U /*!< IN token received with EP mismatch mask */
+#define USB_OTG_DIEPMSK_INEPNEM 0x00000040U /*!< IN endpoint NAK effective mask */
+#define USB_OTG_DIEPMSK_TXFURM 0x00000100U /*!< FIFO underrun mask */
+#define USB_OTG_DIEPMSK_BIM 0x00000200U /*!< BNA interrupt mask */
+
+/******************** Bit definition forUSB_OTG_HPTXSTS register ********************/
+#define USB_OTG_HPTXSTS_PTXFSAVL 0x0000FFFFU /*!< Periodic transmit data FIFO space available */
+
+#define USB_OTG_HPTXSTS_PTXQSAV 0x00FF0000U /*!< Periodic transmit request queue space available */
+#define USB_OTG_HPTXSTS_PTXQSAV_0 0x00010000U /*!<Bit 0 */
+#define USB_OTG_HPTXSTS_PTXQSAV_1 0x00020000U /*!<Bit 1 */
+#define USB_OTG_HPTXSTS_PTXQSAV_2 0x00040000U /*!<Bit 2 */
+#define USB_OTG_HPTXSTS_PTXQSAV_3 0x00080000U /*!<Bit 3 */
+#define USB_OTG_HPTXSTS_PTXQSAV_4 0x00100000U /*!<Bit 4 */
+#define USB_OTG_HPTXSTS_PTXQSAV_5 0x00200000U /*!<Bit 5 */
+#define USB_OTG_HPTXSTS_PTXQSAV_6 0x00400000U /*!<Bit 6 */
+#define USB_OTG_HPTXSTS_PTXQSAV_7 0x00800000U /*!<Bit 7 */
+
+#define USB_OTG_HPTXSTS_PTXQTOP 0xFF000000U /*!< Top of the periodic transmit request queue */
+#define USB_OTG_HPTXSTS_PTXQTOP_0 0x01000000U /*!<Bit 0 */
+#define USB_OTG_HPTXSTS_PTXQTOP_1 0x02000000U /*!<Bit 1 */
+#define USB_OTG_HPTXSTS_PTXQTOP_2 0x04000000U /*!<Bit 2 */
+#define USB_OTG_HPTXSTS_PTXQTOP_3 0x08000000U /*!<Bit 3 */
+#define USB_OTG_HPTXSTS_PTXQTOP_4 0x10000000U /*!<Bit 4 */
+#define USB_OTG_HPTXSTS_PTXQTOP_5 0x20000000U /*!<Bit 5 */
+#define USB_OTG_HPTXSTS_PTXQTOP_6 0x40000000U /*!<Bit 6 */
+#define USB_OTG_HPTXSTS_PTXQTOP_7 0x80000000U /*!<Bit 7 */
+
+/******************** Bit definition forUSB_OTG_HAINT register ********************/
+#define USB_OTG_HAINT_HAINT 0x0000FFFFU /*!< Channel interrupts */
+
+/******************** Bit definition forUSB_OTG_DOEPMSK register ********************/
+#define USB_OTG_DOEPMSK_XFRCM 0x00000001U /*!< Transfer completed interrupt mask */
+#define USB_OTG_DOEPMSK_EPDM 0x00000002U /*!< Endpoint disabled interrupt mask */
+#define USB_OTG_DOEPMSK_STUPM 0x00000008U /*!< SETUP phase done mask */
+#define USB_OTG_DOEPMSK_OTEPDM 0x00000010U /*!< OUT token received when endpoint disabled mask */
+#define USB_OTG_DOEPMSK_B2BSTUP 0x00000040U /*!< Back-to-back SETUP packets received mask */
+#define USB_OTG_DOEPMSK_OPEM 0x00000100U /*!< OUT packet error mask */
+#define USB_OTG_DOEPMSK_BOIM 0x00000200U /*!< BNA interrupt mask */
+
+/******************** Bit definition forUSB_OTG_GINTSTS register ********************/
+#define USB_OTG_GINTSTS_CMOD 0x00000001U /*!< Current mode of operation */
+#define USB_OTG_GINTSTS_MMIS 0x00000002U /*!< Mode mismatch interrupt */
+#define USB_OTG_GINTSTS_OTGINT 0x00000004U /*!< OTG interrupt */
+#define USB_OTG_GINTSTS_SOF 0x00000008U /*!< Start of frame */
+#define USB_OTG_GINTSTS_RXFLVL 0x00000010U /*!< RxFIFO nonempty */
+#define USB_OTG_GINTSTS_NPTXFE 0x00000020U /*!< Nonperiodic TxFIFO empty */
+#define USB_OTG_GINTSTS_GINAKEFF 0x00000040U /*!< Global IN nonperiodic NAK effective */
+#define USB_OTG_GINTSTS_BOUTNAKEFF 0x00000080U /*!< Global OUT NAK effective */
+#define USB_OTG_GINTSTS_ESUSP 0x00000400U /*!< Early suspend */
+#define USB_OTG_GINTSTS_USBSUSP 0x00000800U /*!< USB suspend */
+#define USB_OTG_GINTSTS_USBRST 0x00001000U /*!< USB reset */
+#define USB_OTG_GINTSTS_ENUMDNE 0x00002000U /*!< Enumeration done */
+#define USB_OTG_GINTSTS_ISOODRP 0x00004000U /*!< Isochronous OUT packet dropped interrupt */
+#define USB_OTG_GINTSTS_EOPF 0x00008000U /*!< End of periodic frame interrupt */
+#define USB_OTG_GINTSTS_IEPINT 0x00040000U /*!< IN endpoint interrupt */
+#define USB_OTG_GINTSTS_OEPINT 0x00080000U /*!< OUT endpoint interrupt */
+#define USB_OTG_GINTSTS_IISOIXFR 0x00100000U /*!< Incomplete isochronous IN transfer */
+#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT 0x00200000U /*!< Incomplete periodic transfer */
+#define USB_OTG_GINTSTS_DATAFSUSP 0x00400000U /*!< Data fetch suspended */
+#define USB_OTG_GINTSTS_HPRTINT 0x01000000U /*!< Host port interrupt */
+#define USB_OTG_GINTSTS_HCINT 0x02000000U /*!< Host channels interrupt */
+#define USB_OTG_GINTSTS_PTXFE 0x04000000U /*!< Periodic TxFIFO empty */
+#define USB_OTG_GINTSTS_CIDSCHG 0x10000000U /*!< Connector ID status change */
+#define USB_OTG_GINTSTS_DISCINT 0x20000000U /*!< Disconnect detected interrupt */
+#define USB_OTG_GINTSTS_SRQINT 0x40000000U /*!< Session request/new session detected interrupt */
+#define USB_OTG_GINTSTS_WKUINT 0x80000000U /*!< Resume/remote wakeup detected interrupt */
+
+/******************** Bit definition forUSB_OTG_GINTMSK register ********************/
+#define USB_OTG_GINTMSK_MMISM 0x00000002U /*!< Mode mismatch interrupt mask */
+#define USB_OTG_GINTMSK_OTGINT 0x00000004U /*!< OTG interrupt mask */
+#define USB_OTG_GINTMSK_SOFM 0x00000008U /*!< Start of frame mask */
+#define USB_OTG_GINTMSK_RXFLVLM 0x00000010U /*!< Receive FIFO nonempty mask */
+#define USB_OTG_GINTMSK_NPTXFEM 0x00000020U /*!< Nonperiodic TxFIFO empty mask */
+#define USB_OTG_GINTMSK_GINAKEFFM 0x00000040U /*!< Global nonperiodic IN NAK effective mask */
+#define USB_OTG_GINTMSK_GONAKEFFM 0x00000080U /*!< Global OUT NAK effective mask */
+#define USB_OTG_GINTMSK_ESUSPM 0x00000400U /*!< Early suspend mask */
+#define USB_OTG_GINTMSK_USBSUSPM 0x00000800U /*!< USB suspend mask */
+#define USB_OTG_GINTMSK_USBRST 0x00001000U /*!< USB reset mask */
+#define USB_OTG_GINTMSK_ENUMDNEM 0x00002000U /*!< Enumeration done mask */
+#define USB_OTG_GINTMSK_ISOODRPM 0x00004000U /*!< Isochronous OUT packet dropped interrupt mask */
+#define USB_OTG_GINTMSK_EOPFM 0x00008000U /*!< End of periodic frame interrupt mask */
+#define USB_OTG_GINTMSK_EPMISM 0x00020000U /*!< Endpoint mismatch interrupt mask */
+#define USB_OTG_GINTMSK_IEPINT 0x00040000U /*!< IN endpoints interrupt mask */
+#define USB_OTG_GINTMSK_OEPINT 0x00080000U /*!< OUT endpoints interrupt mask */
+#define USB_OTG_GINTMSK_IISOIXFRM 0x00100000U /*!< Incomplete isochronous IN transfer mask */
+#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM 0x00200000U /*!< Incomplete periodic transfer mask */
+#define USB_OTG_GINTMSK_FSUSPM 0x00400000U /*!< Data fetch suspended mask */
+#define USB_OTG_GINTMSK_PRTIM 0x01000000U /*!< Host port interrupt mask */
+#define USB_OTG_GINTMSK_HCIM 0x02000000U /*!< Host channels interrupt mask */
+#define USB_OTG_GINTMSK_PTXFEM 0x04000000U /*!< Periodic TxFIFO empty mask */
+#define USB_OTG_GINTMSK_CIDSCHGM 0x10000000U /*!< Connector ID status change mask */
+#define USB_OTG_GINTMSK_DISCINT 0x20000000U /*!< Disconnect detected interrupt mask */
+#define USB_OTG_GINTMSK_SRQIM 0x40000000U /*!< Session request/new session detected interrupt mask */
+#define USB_OTG_GINTMSK_WUIM 0x80000000U /*!< Resume/remote wakeup detected interrupt mask */
+
+/******************** Bit definition forUSB_OTG_DAINT register ********************/
+#define USB_OTG_DAINT_IEPINT 0x0000FFFFU /*!< IN endpoint interrupt bits */
+#define USB_OTG_DAINT_OEPINT 0xFFFF0000U /*!< OUT endpoint interrupt bits */
+
+/******************** Bit definition forUSB_OTG_HAINTMSK register ********************/
+#define USB_OTG_HAINTMSK_HAINTM 0x0000FFFFU /*!< Channel interrupt mask */
+
+/******************** Bit definition for USB_OTG_GRXSTSP register ********************/
+#define USB_OTG_GRXSTSP_EPNUM 0x0000000FU /*!< IN EP interrupt mask bits */
+#define USB_OTG_GRXSTSP_BCNT 0x00007FF0U /*!< OUT EP interrupt mask bits */
+#define USB_OTG_GRXSTSP_DPID 0x00018000U /*!< OUT EP interrupt mask bits */
+#define USB_OTG_GRXSTSP_PKTSTS 0x001E0000U /*!< OUT EP interrupt mask bits */
+
+/******************** Bit definition forUSB_OTG_DAINTMSK register ********************/
+#define USB_OTG_DAINTMSK_IEPM 0x0000FFFFU /*!< IN EP interrupt mask bits */
+#define USB_OTG_DAINTMSK_OEPM 0xFFFF0000U /*!< OUT EP interrupt mask bits */
+
+/******************** Bit definition for OTG register ********************/
+
+#define USB_OTG_CHNUM 0x0000000FU /*!< Channel number */
+#define USB_OTG_CHNUM_0 0x00000001U /*!<Bit 0 */
+#define USB_OTG_CHNUM_1 0x00000002U /*!<Bit 1 */
+#define USB_OTG_CHNUM_2 0x00000004U /*!<Bit 2 */
+#define USB_OTG_CHNUM_3 0x00000008U /*!<Bit 3 */
+#define USB_OTG_BCNT 0x00007FF0U /*!< Byte count */
+
+#define USB_OTG_DPID 0x00018000U /*!< Data PID */
+#define USB_OTG_DPID_0 0x00008000U /*!<Bit 0 */
+#define USB_OTG_DPID_1 0x00010000U /*!<Bit 1 */
+
+#define USB_OTG_PKTSTS 0x001E0000U /*!< Packet status */
+#define USB_OTG_PKTSTS_0 0x00020000U /*!<Bit 0 */
+#define USB_OTG_PKTSTS_1 0x00040000U /*!<Bit 1 */
+#define USB_OTG_PKTSTS_2 0x00080000U /*!<Bit 2 */
+#define USB_OTG_PKTSTS_3 0x00100000U /*!<Bit 3 */
+
+#define USB_OTG_EPNUM 0x0000000FU /*!< Endpoint number */
+#define USB_OTG_EPNUM_0 0x00000001U /*!<Bit 0 */
+#define USB_OTG_EPNUM_1 0x00000002U /*!<Bit 1 */
+#define USB_OTG_EPNUM_2 0x00000004U /*!<Bit 2 */
+#define USB_OTG_EPNUM_3 0x00000008U /*!<Bit 3 */
+
+#define USB_OTG_FRMNUM 0x01E00000U /*!< Frame number */
+#define USB_OTG_FRMNUM_0 0x00200000U /*!<Bit 0 */
+#define USB_OTG_FRMNUM_1 0x00400000U /*!<Bit 1 */
+#define USB_OTG_FRMNUM_2 0x00800000U /*!<Bit 2 */
+#define USB_OTG_FRMNUM_3 0x01000000U /*!<Bit 3 */
+
+/******************** Bit definition for OTG register ********************/
+
+#define USB_OTG_CHNUM 0x0000000FU /*!< Channel number */
+#define USB_OTG_CHNUM_0 0x00000001U /*!<Bit 0 */
+#define USB_OTG_CHNUM_1 0x00000002U /*!<Bit 1 */
+#define USB_OTG_CHNUM_2 0x00000004U /*!<Bit 2 */
+#define USB_OTG_CHNUM_3 0x00000008U /*!<Bit 3 */
+#define USB_OTG_BCNT 0x00007FF0U /*!< Byte count */
+
+#define USB_OTG_DPID 0x00018000U /*!< Data PID */
+#define USB_OTG_DPID_0 0x00008000U /*!<Bit 0 */
+#define USB_OTG_DPID_1 0x00010000U /*!<Bit 1 */
+
+#define USB_OTG_PKTSTS 0x001E0000U /*!< Packet status */
+#define USB_OTG_PKTSTS_0 0x00020000U /*!<Bit 0 */
+#define USB_OTG_PKTSTS_1 0x00040000U /*!<Bit 1 */
+#define USB_OTG_PKTSTS_2 0x00080000U /*!<Bit 2 */
+#define USB_OTG_PKTSTS_3 0x00100000U /*!<Bit 3 */
+
+#define USB_OTG_EPNUM 0x0000000FU /*!< Endpoint number */
+#define USB_OTG_EPNUM_0 0x00000001U /*!<Bit 0 */
+#define USB_OTG_EPNUM_1 0x00000002U /*!<Bit 1 */
+#define USB_OTG_EPNUM_2 0x00000004U /*!<Bit 2 */
+#define USB_OTG_EPNUM_3 0x00000008U /*!<Bit 3 */
+
+#define USB_OTG_FRMNUM 0x01E00000U /*!< Frame number */
+#define USB_OTG_FRMNUM_0 0x00200000U /*!<Bit 0 */
+#define USB_OTG_FRMNUM_1 0x00400000U /*!<Bit 1 */
+#define USB_OTG_FRMNUM_2 0x00800000U /*!<Bit 2 */
+#define USB_OTG_FRMNUM_3 0x01000000U /*!<Bit 3 */
+
+/******************** Bit definition forUSB_OTG_GRXFSIZ register ********************/
+#define USB_OTG_GRXFSIZ_RXFD 0x0000FFFFU /*!< RxFIFO depth */
+
+/******************** Bit definition forUSB_OTG_DVBUSDIS register ********************/
+#define USB_OTG_DVBUSDIS_VBUSDT 0x0000FFFFU /*!< Device VBUS discharge time */
+
+/******************** Bit definition for OTG register ********************/
+#define USB_OTG_NPTXFSA 0x0000FFFFU /*!< Nonperiodic transmit RAM start address */
+#define USB_OTG_NPTXFD 0xFFFF0000U /*!< Nonperiodic TxFIFO depth */
+#define USB_OTG_TX0FSA 0x0000FFFFU /*!< Endpoint 0 transmit RAM start address */
+#define USB_OTG_TX0FD 0xFFFF0000U /*!< Endpoint 0 TxFIFO depth */
+
+/******************** Bit definition forUSB_OTG_DVBUSPULSE register ********************/
+#define USB_OTG_DVBUSPULSE_DVBUSP 0x00000FFFU /*!< Device VBUS pulsing time */
+
+/******************** Bit definition forUSB_OTG_GNPTXSTS register ********************/
+#define USB_OTG_GNPTXSTS_NPTXFSAV 0x0000FFFFU /*!< Nonperiodic TxFIFO space available */
+
+#define USB_OTG_GNPTXSTS_NPTQXSAV 0x00FF0000U /*!< Nonperiodic transmit request queue space available */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_0 0x00010000U /*!<Bit 0 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_1 0x00020000U /*!<Bit 1 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_2 0x00040000U /*!<Bit 2 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_3 0x00080000U /*!<Bit 3 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_4 0x00100000U /*!<Bit 4 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_5 0x00200000U /*!<Bit 5 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_6 0x00400000U /*!<Bit 6 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_7 0x00800000U /*!<Bit 7 */
+
+#define USB_OTG_GNPTXSTS_NPTXQTOP 0x7F000000U /*!< Top of the nonperiodic transmit request queue */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_0 0x01000000U /*!<Bit 0 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_1 0x02000000U /*!<Bit 1 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_2 0x04000000U /*!<Bit 2 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_3 0x08000000U /*!<Bit 3 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_4 0x10000000U /*!<Bit 4 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_5 0x20000000U /*!<Bit 5 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_6 0x40000000U /*!<Bit 6 */
+
+/******************** Bit definition forUSB_OTG_DTHRCTL register ********************/
+#define USB_OTG_DTHRCTL_NONISOTHREN 0x00000001U /*!< Nonisochronous IN endpoints threshold enable */
+#define USB_OTG_DTHRCTL_ISOTHREN 0x00000002U /*!< ISO IN endpoint threshold enable */
+
+#define USB_OTG_DTHRCTL_TXTHRLEN 0x000007FCU /*!< Transmit threshold length */
+#define USB_OTG_DTHRCTL_TXTHRLEN_0 0x00000004U /*!<Bit 0 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_1 0x00000008U /*!<Bit 1 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_2 0x00000010U /*!<Bit 2 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_3 0x00000020U /*!<Bit 3 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_4 0x00000040U /*!<Bit 4 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_5 0x00000080U /*!<Bit 5 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_6 0x00000100U /*!<Bit 6 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_7 0x00000200U /*!<Bit 7 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_8 0x00000400U /*!<Bit 8 */
+#define USB_OTG_DTHRCTL_RXTHREN 0x00010000U /*!< Receive threshold enable */
+
+#define USB_OTG_DTHRCTL_RXTHRLEN 0x03FE0000U /*!< Receive threshold length */
+#define USB_OTG_DTHRCTL_RXTHRLEN_0 0x00020000U /*!<Bit 0 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_1 0x00040000U /*!<Bit 1 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_2 0x00080000U /*!<Bit 2 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_3 0x00100000U /*!<Bit 3 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_4 0x00200000U /*!<Bit 4 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_5 0x00400000U /*!<Bit 5 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_6 0x00800000U /*!<Bit 6 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_7 0x01000000U /*!<Bit 7 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_8 0x02000000U /*!<Bit 8 */
+#define USB_OTG_DTHRCTL_ARPEN 0x08000000U /*!< Arbiter parking enable */
+
+/******************** Bit definition forUSB_OTG_DIEPEMPMSK register ********************/
+#define USB_OTG_DIEPEMPMSK_INEPTXFEM 0x0000FFFFU /*!< IN EP Tx FIFO empty interrupt mask bits */
+
+/******************** Bit definition forUSB_OTG_DEACHINT register ********************/
+#define USB_OTG_DEACHINT_IEP1INT 0x00000002U /*!< IN endpoint 1interrupt bit */
+#define USB_OTG_DEACHINT_OEP1INT 0x00020000U /*!< OUT endpoint 1 interrupt bit */
+
+/******************** Bit definition forUSB_OTG_GCCFG register ********************/
+#define USB_OTG_GCCFG_PWRDWN 0x00010000U /*!< Power down */
+#define USB_OTG_GCCFG_I2CPADEN 0x00020000U /*!< Enable I2C bus connection for the external I2C PHY interface */
+#define USB_OTG_GCCFG_VBUSASEN 0x00040000U /*!< Enable the VBUS sensing device */
+#define USB_OTG_GCCFG_VBUSBSEN 0x00080000U /*!< Enable the VBUS sensing device */
+#define USB_OTG_GCCFG_SOFOUTEN 0x00100000U /*!< SOF output enable */
+#define USB_OTG_GCCFG_NOVBUSSENS 0x00200000U /*!< VBUS sensing disable option */
+
+/******************** Bit definition forUSB_OTG_DEACHINTMSK register ********************/
+#define USB_OTG_DEACHINTMSK_IEP1INTM 0x00000002U /*!< IN Endpoint 1 interrupt mask bit */
+#define USB_OTG_DEACHINTMSK_OEP1INTM 0x00020000U /*!< OUT Endpoint 1 interrupt mask bit */
+
+/******************** Bit definition forUSB_OTG_CID register ********************/
+#define USB_OTG_CID_PRODUCT_ID 0xFFFFFFFFU /*!< Product ID field */
+
+/******************** Bit definition forUSB_OTG_DIEPEACHMSK1 register ********************/
+#define USB_OTG_DIEPEACHMSK1_XFRCM 0x00000001U /*!< Transfer completed interrupt mask */
+#define USB_OTG_DIEPEACHMSK1_EPDM 0x00000002U /*!< Endpoint disabled interrupt mask */
+#define USB_OTG_DIEPEACHMSK1_TOM 0x00000008U /*!< Timeout condition mask (nonisochronous endpoints) */
+#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK 0x00000010U /*!< IN token received when TxFIFO empty mask */
+#define USB_OTG_DIEPEACHMSK1_INEPNMM 0x00000020U /*!< IN token received with EP mismatch mask */
+#define USB_OTG_DIEPEACHMSK1_INEPNEM 0x00000040U /*!< IN endpoint NAK effective mask */
+#define USB_OTG_DIEPEACHMSK1_TXFURM 0x00000100U /*!< FIFO underrun mask */
+#define USB_OTG_DIEPEACHMSK1_BIM 0x00000200U /*!< BNA interrupt mask */
+#define USB_OTG_DIEPEACHMSK1_NAKM 0x00002000U /*!< NAK interrupt mask */
+
+/******************** Bit definition forUSB_OTG_HPRT register ********************/
+#define USB_OTG_HPRT_PCSTS 0x00000001U /*!< Port connect status */
+#define USB_OTG_HPRT_PCDET 0x00000002U /*!< Port connect detected */
+#define USB_OTG_HPRT_PENA 0x00000004U /*!< Port enable */
+#define USB_OTG_HPRT_PENCHNG 0x00000008U /*!< Port enable/disable change */
+#define USB_OTG_HPRT_POCA 0x00000010U /*!< Port overcurrent active */
+#define USB_OTG_HPRT_POCCHNG 0x00000020U /*!< Port overcurrent change */
+#define USB_OTG_HPRT_PRES 0x00000040U /*!< Port resume */
+#define USB_OTG_HPRT_PSUSP 0x00000080U /*!< Port suspend */
+#define USB_OTG_HPRT_PRST 0x00000100U /*!< Port reset */
+
+#define USB_OTG_HPRT_PLSTS 0x00000C00U /*!< Port line status */
+#define USB_OTG_HPRT_PLSTS_0 0x00000400U /*!<Bit 0 */
+#define USB_OTG_HPRT_PLSTS_1 0x00000800U /*!<Bit 1 */
+#define USB_OTG_HPRT_PPWR 0x00001000U /*!< Port power */
+
+#define USB_OTG_HPRT_PTCTL 0x0001E000U /*!< Port test control */
+#define USB_OTG_HPRT_PTCTL_0 0x00002000U /*!<Bit 0 */
+#define USB_OTG_HPRT_PTCTL_1 0x00004000U /*!<Bit 1 */
+#define USB_OTG_HPRT_PTCTL_2 0x00008000U /*!<Bit 2 */
+#define USB_OTG_HPRT_PTCTL_3 0x00010000U /*!<Bit 3 */
+
+#define USB_OTG_HPRT_PSPD 0x00060000U /*!< Port speed */
+#define USB_OTG_HPRT_PSPD_0 0x00020000U /*!<Bit 0 */
+#define USB_OTG_HPRT_PSPD_1 0x00040000U /*!<Bit 1 */
+
+/******************** Bit definition forUSB_OTG_DOEPEACHMSK1 register ********************/
+#define USB_OTG_DOEPEACHMSK1_XFRCM 0x00000001U /*!< Transfer completed interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_EPDM 0x00000002U /*!< Endpoint disabled interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_TOM 0x00000008U /*!< Timeout condition mask */
+#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK 0x00000010U /*!< IN token received when TxFIFO empty mask */
+#define USB_OTG_DOEPEACHMSK1_INEPNMM 0x00000020U /*!< IN token received with EP mismatch mask */
+#define USB_OTG_DOEPEACHMSK1_INEPNEM 0x00000040U /*!< IN endpoint NAK effective mask */
+#define USB_OTG_DOEPEACHMSK1_TXFURM 0x00000100U /*!< OUT packet error mask */
+#define USB_OTG_DOEPEACHMSK1_BIM 0x00000200U /*!< BNA interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_BERRM 0x00001000U /*!< Bubble error interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_NAKM 0x00002000U /*!< NAK interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_NYETM 0x00004000U /*!< NYET interrupt mask */
+
+/******************** Bit definition forUSB_OTG_HPTXFSIZ register ********************/
+#define USB_OTG_HPTXFSIZ_PTXSA 0x0000FFFFU /*!< Host periodic TxFIFO start address */
+#define USB_OTG_HPTXFSIZ_PTXFD 0xFFFF0000U /*!< Host periodic TxFIFO depth */
+
+/******************** Bit definition forUSB_OTG_DIEPCTL register ********************/
+#define USB_OTG_DIEPCTL_MPSIZ 0x000007FFU /*!< Maximum packet size */
+#define USB_OTG_DIEPCTL_USBAEP 0x00008000U /*!< USB active endpoint */
+#define USB_OTG_DIEPCTL_EONUM_DPID 0x00010000U /*!< Even/odd frame */
+#define USB_OTG_DIEPCTL_NAKSTS 0x00020000U /*!< NAK status */
+
+#define USB_OTG_DIEPCTL_EPTYP 0x000C0000U /*!< Endpoint type */
+#define USB_OTG_DIEPCTL_EPTYP_0 0x00040000U /*!<Bit 0 */
+#define USB_OTG_DIEPCTL_EPTYP_1 0x00080000U /*!<Bit 1 */
+#define USB_OTG_DIEPCTL_STALL 0x00200000U /*!< STALL handshake */
+
+#define USB_OTG_DIEPCTL_TXFNUM 0x03C00000U /*!< TxFIFO number */
+#define USB_OTG_DIEPCTL_TXFNUM_0 0x00400000U /*!<Bit 0 */
+#define USB_OTG_DIEPCTL_TXFNUM_1 0x00800000U /*!<Bit 1 */
+#define USB_OTG_DIEPCTL_TXFNUM_2 0x01000000U /*!<Bit 2 */
+#define USB_OTG_DIEPCTL_TXFNUM_3 0x02000000U /*!<Bit 3 */
+#define USB_OTG_DIEPCTL_CNAK 0x04000000U /*!< Clear NAK */
+#define USB_OTG_DIEPCTL_SNAK 0x08000000U /*!< Set NAK */
+#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM 0x10000000U /*!< Set DATA0 PID */
+#define USB_OTG_DIEPCTL_SODDFRM 0x20000000U /*!< Set odd frame */
+#define USB_OTG_DIEPCTL_EPDIS 0x40000000U /*!< Endpoint disable */
+#define USB_OTG_DIEPCTL_EPENA 0x80000000U /*!< Endpoint enable */
+
+/******************** Bit definition forUSB_OTG_HCCHAR register ********************/
+#define USB_OTG_HCCHAR_MPSIZ 0x000007FFU /*!< Maximum packet size */
+
+#define USB_OTG_HCCHAR_EPNUM 0x00007800U /*!< Endpoint number */
+#define USB_OTG_HCCHAR_EPNUM_0 0x00000800U /*!<Bit 0 */
+#define USB_OTG_HCCHAR_EPNUM_1 0x00001000U /*!<Bit 1 */
+#define USB_OTG_HCCHAR_EPNUM_2 0x00002000U /*!<Bit 2 */
+#define USB_OTG_HCCHAR_EPNUM_3 0x00004000U /*!<Bit 3 */
+#define USB_OTG_HCCHAR_EPDIR 0x00008000U /*!< Endpoint direction */
+#define USB_OTG_HCCHAR_LSDEV 0x00020000U /*!< Low-speed device */
+
+#define USB_OTG_HCCHAR_EPTYP 0x000C0000U /*!< Endpoint type */
+#define USB_OTG_HCCHAR_EPTYP_0 0x00040000U /*!<Bit 0 */
+#define USB_OTG_HCCHAR_EPTYP_1 0x00080000U /*!<Bit 1 */
+
+#define USB_OTG_HCCHAR_MC 0x00300000U /*!< Multi Count (MC) / Error Count (EC) */
+#define USB_OTG_HCCHAR_MC_0 0x00100000U /*!<Bit 0 */
+#define USB_OTG_HCCHAR_MC_1 0x00200000U /*!<Bit 1 */
+
+#define USB_OTG_HCCHAR_DAD 0x1FC00000U /*!< Device address */
+#define USB_OTG_HCCHAR_DAD_0 0x00400000U /*!<Bit 0 */
+#define USB_OTG_HCCHAR_DAD_1 0x00800000U /*!<Bit 1 */
+#define USB_OTG_HCCHAR_DAD_2 0x01000000U /*!<Bit 2 */
+#define USB_OTG_HCCHAR_DAD_3 0x02000000U /*!<Bit 3 */
+#define USB_OTG_HCCHAR_DAD_4 0x04000000U /*!<Bit 4 */
+#define USB_OTG_HCCHAR_DAD_5 0x08000000U /*!<Bit 5 */
+#define USB_OTG_HCCHAR_DAD_6 0x10000000U /*!<Bit 6 */
+#define USB_OTG_HCCHAR_ODDFRM 0x20000000U /*!< Odd frame */
+#define USB_OTG_HCCHAR_CHDIS 0x40000000U /*!< Channel disable */
+#define USB_OTG_HCCHAR_CHENA 0x80000000U /*!< Channel enable */
+
+/******************** Bit definition forUSB_OTG_HCSPLT register ********************/
+
+#define USB_OTG_HCSPLT_PRTADDR 0x0000007FU /*!< Port address */
+#define USB_OTG_HCSPLT_PRTADDR_0 0x00000001U /*!<Bit 0 */
+#define USB_OTG_HCSPLT_PRTADDR_1 0x00000002U /*!<Bit 1 */
+#define USB_OTG_HCSPLT_PRTADDR_2 0x00000004U /*!<Bit 2 */
+#define USB_OTG_HCSPLT_PRTADDR_3 0x00000008U /*!<Bit 3 */
+#define USB_OTG_HCSPLT_PRTADDR_4 0x00000010U /*!<Bit 4 */
+#define USB_OTG_HCSPLT_PRTADDR_5 0x00000020U /*!<Bit 5 */
+#define USB_OTG_HCSPLT_PRTADDR_6 0x00000040U /*!<Bit 6 */
+
+#define USB_OTG_HCSPLT_HUBADDR 0x00003F80U /*!< Hub address */
+#define USB_OTG_HCSPLT_HUBADDR_0 0x00000080U /*!<Bit 0 */
+#define USB_OTG_HCSPLT_HUBADDR_1 0x00000100U /*!<Bit 1 */
+#define USB_OTG_HCSPLT_HUBADDR_2 0x00000200U /*!<Bit 2 */
+#define USB_OTG_HCSPLT_HUBADDR_3 0x00000400U /*!<Bit 3 */
+#define USB_OTG_HCSPLT_HUBADDR_4 0x00000800U /*!<Bit 4 */
+#define USB_OTG_HCSPLT_HUBADDR_5 0x00001000U /*!<Bit 5 */
+#define USB_OTG_HCSPLT_HUBADDR_6 0x00002000U /*!<Bit 6 */
+
+#define USB_OTG_HCSPLT_XACTPOS 0x0000C000U /*!< XACTPOS */
+#define USB_OTG_HCSPLT_XACTPOS_0 0x00004000U /*!<Bit 0 */
+#define USB_OTG_HCSPLT_XACTPOS_1 0x00008000U /*!<Bit 1 */
+#define USB_OTG_HCSPLT_COMPLSPLT 0x00010000U /*!< Do complete split */
+#define USB_OTG_HCSPLT_SPLITEN 0x80000000U /*!< Split enable */
+
+/******************** Bit definition forUSB_OTG_HCINT register ********************/
+#define USB_OTG_HCINT_XFRC 0x00000001U /*!< Transfer completed */
+#define USB_OTG_HCINT_CHH 0x00000002U /*!< Channel halted */
+#define USB_OTG_HCINT_AHBERR 0x00000004U /*!< AHB error */
+#define USB_OTG_HCINT_STALL 0x00000008U /*!< STALL response received interrupt */
+#define USB_OTG_HCINT_NAK 0x00000010U /*!< NAK response received interrupt */
+#define USB_OTG_HCINT_ACK 0x00000020U /*!< ACK response received/transmitted interrupt */
+#define USB_OTG_HCINT_NYET 0x00000040U /*!< Response received interrupt */
+#define USB_OTG_HCINT_TXERR 0x00000080U /*!< Transaction error */
+#define USB_OTG_HCINT_BBERR 0x00000100U /*!< Babble error */
+#define USB_OTG_HCINT_FRMOR 0x00000200U /*!< Frame overrun */
+#define USB_OTG_HCINT_DTERR 0x00000400U /*!< Data toggle error */
+
+/******************** Bit definition forUSB_OTG_DIEPINT register ********************/
+#define USB_OTG_DIEPINT_XFRC 0x00000001U /*!< Transfer completed interrupt */
+#define USB_OTG_DIEPINT_EPDISD 0x00000002U /*!< Endpoint disabled interrupt */
+#define USB_OTG_DIEPINT_TOC 0x00000008U /*!< Timeout condition */
+#define USB_OTG_DIEPINT_ITTXFE 0x00000010U /*!< IN token received when TxFIFO is empty */
+#define USB_OTG_DIEPINT_INEPNE 0x00000040U /*!< IN endpoint NAK effective */
+#define USB_OTG_DIEPINT_TXFE 0x00000080U /*!< Transmit FIFO empty */
+#define USB_OTG_DIEPINT_TXFIFOUDRN 0x00000100U /*!< Transmit Fifo Underrun */
+#define USB_OTG_DIEPINT_BNA 0x00000200U /*!< Buffer not available interrupt */
+#define USB_OTG_DIEPINT_PKTDRPSTS 0x00000800U /*!< Packet dropped status */
+#define USB_OTG_DIEPINT_BERR 0x00001000U /*!< Babble error interrupt */
+#define USB_OTG_DIEPINT_NAK 0x00002000U /*!< NAK interrupt */
+
+/******************** Bit definition forUSB_OTG_HCINTMSK register ********************/
+#define USB_OTG_HCINTMSK_XFRCM 0x00000001U /*!< Transfer completed mask */
+#define USB_OTG_HCINTMSK_CHHM 0x00000002U /*!< Channel halted mask */
+#define USB_OTG_HCINTMSK_AHBERR 0x00000004U /*!< AHB error */
+#define USB_OTG_HCINTMSK_STALLM 0x00000008U /*!< STALL response received interrupt mask */
+#define USB_OTG_HCINTMSK_NAKM 0x00000010U /*!< NAK response received interrupt mask */
+#define USB_OTG_HCINTMSK_ACKM 0x00000020U /*!< ACK response received/transmitted interrupt mask */
+#define USB_OTG_HCINTMSK_NYET 0x00000040U /*!< response received interrupt mask */
+#define USB_OTG_HCINTMSK_TXERRM 0x00000080U /*!< Transaction error mask */
+#define USB_OTG_HCINTMSK_BBERRM 0x00000100U /*!< Babble error mask */
+#define USB_OTG_HCINTMSK_FRMORM 0x00000200U /*!< Frame overrun mask */
+#define USB_OTG_HCINTMSK_DTERRM 0x00000400U /*!< Data toggle error mask */
+
+/******************** Bit definition for USB_OTG_DIEPTSIZ register ********************/
+
+#define USB_OTG_DIEPTSIZ_XFRSIZ 0x0007FFFFU /*!< Transfer size */
+#define USB_OTG_DIEPTSIZ_PKTCNT 0x1FF80000U /*!< Packet count */
+#define USB_OTG_DIEPTSIZ_MULCNT 0x60000000U /*!< Packet count */
+/******************** Bit definition forUSB_OTG_HCTSIZ register ********************/
+#define USB_OTG_HCTSIZ_XFRSIZ 0x0007FFFFU /*!< Transfer size */
+#define USB_OTG_HCTSIZ_PKTCNT 0x1FF80000U /*!< Packet count */
+#define USB_OTG_HCTSIZ_DOPING 0x80000000U /*!< Do PING */
+#define USB_OTG_HCTSIZ_DPID 0x60000000U /*!< Data PID */
+#define USB_OTG_HCTSIZ_DPID_0 0x20000000U /*!<Bit 0 */
+#define USB_OTG_HCTSIZ_DPID_1 0x40000000U /*!<Bit 1 */
+
+/******************** Bit definition forUSB_OTG_DIEPDMA register ********************/
+#define USB_OTG_DIEPDMA_DMAADDR 0xFFFFFFFFU /*!< DMA address */
+
+/******************** Bit definition forUSB_OTG_HCDMA register ********************/
+#define USB_OTG_HCDMA_DMAADDR 0xFFFFFFFFU /*!< DMA address */
+
+/******************** Bit definition forUSB_OTG_DTXFSTS register ********************/
+#define USB_OTG_DTXFSTS_INEPTFSAV 0x0000FFFFU /*!< IN endpoint TxFIFO space avail */
+
+/******************** Bit definition forUSB_OTG_DIEPTXF register ********************/
+#define USB_OTG_DIEPTXF_INEPTXSA 0x0000FFFFU /*!< IN endpoint FIFOx transmit RAM start address */
+#define USB_OTG_DIEPTXF_INEPTXFD 0xFFFF0000U /*!< IN endpoint TxFIFO depth */
+
+/******************** Bit definition forUSB_OTG_DOEPCTL register ********************/
+
+#define USB_OTG_DOEPCTL_MPSIZ 0x000007FFU /*!< Maximum packet size */ /*!<Bit 1 */
+#define USB_OTG_DOEPCTL_USBAEP 0x00008000U /*!< USB active endpoint */
+#define USB_OTG_DOEPCTL_NAKSTS 0x00020000U /*!< NAK status */
+#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM 0x10000000U /*!< Set DATA0 PID */
+#define USB_OTG_DOEPCTL_SODDFRM 0x20000000U /*!< Set odd frame */
+#define USB_OTG_DOEPCTL_EPTYP 0x000C0000U /*!< Endpoint type */
+#define USB_OTG_DOEPCTL_EPTYP_0 0x00040000U /*!<Bit 0 */
+#define USB_OTG_DOEPCTL_EPTYP_1 0x00080000U /*!<Bit 1 */
+#define USB_OTG_DOEPCTL_SNPM 0x00100000U /*!< Snoop mode */
+#define USB_OTG_DOEPCTL_STALL 0x00200000U /*!< STALL handshake */
+#define USB_OTG_DOEPCTL_CNAK 0x04000000U /*!< Clear NAK */
+#define USB_OTG_DOEPCTL_SNAK 0x08000000U /*!< Set NAK */
+#define USB_OTG_DOEPCTL_EPDIS 0x40000000U /*!< Endpoint disable */
+#define USB_OTG_DOEPCTL_EPENA 0x80000000U /*!< Endpoint enable */
+
+/******************** Bit definition forUSB_OTG_DOEPINT register ********************/
+#define USB_OTG_DOEPINT_XFRC 0x00000001U /*!< Transfer completed interrupt */
+#define USB_OTG_DOEPINT_EPDISD 0x00000002U /*!< Endpoint disabled interrupt */
+#define USB_OTG_DOEPINT_STUP 0x00000008U /*!< SETUP phase done */
+#define USB_OTG_DOEPINT_OTEPDIS 0x00000010U /*!< OUT token received when endpoint disabled */
+#define USB_OTG_DOEPINT_B2BSTUP 0x00000040U /*!< Back-to-back SETUP packets received */
+#define USB_OTG_DOEPINT_NYET 0x00004000U /*!< NYET interrupt */
+
+/******************** Bit definition forUSB_OTG_DOEPTSIZ register ********************/
+
+#define USB_OTG_DOEPTSIZ_XFRSIZ 0x0007FFFFU /*!< Transfer size */
+#define USB_OTG_DOEPTSIZ_PKTCNT 0x1FF80000U /*!< Packet count */
+
+#define USB_OTG_DOEPTSIZ_STUPCNT 0x60000000U /*!< SETUP packet count */
+#define USB_OTG_DOEPTSIZ_STUPCNT_0 0x20000000U /*!<Bit 0 */
+#define USB_OTG_DOEPTSIZ_STUPCNT_1 0x40000000U /*!<Bit 1 */
+
+/******************** Bit definition for PCGCCTL register ********************/
+#define USB_OTG_PCGCCTL_STOPCLK 0x00000001U /*!< SETUP packet count */
+#define USB_OTG_PCGCCTL_GATECLK 0x00000002U /*!<Bit 0 */
+#define USB_OTG_PCGCCTL_PHYSUSP 0x00000010U /*!<Bit 1 */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup Exported_macros
+ * @{
+ */
+
+/******************************* ADC Instances ********************************/
+#define IS_ADC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
+
+/******************************* CRC Instances ********************************/
+#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
+
+/******************************** DMA Instances *******************************/
+#define IS_DMA_STREAM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0) || \
+ ((INSTANCE) == DMA1_Stream1) || \
+ ((INSTANCE) == DMA1_Stream2) || \
+ ((INSTANCE) == DMA1_Stream3) || \
+ ((INSTANCE) == DMA1_Stream4) || \
+ ((INSTANCE) == DMA1_Stream5) || \
+ ((INSTANCE) == DMA1_Stream6) || \
+ ((INSTANCE) == DMA1_Stream7) || \
+ ((INSTANCE) == DMA2_Stream0) || \
+ ((INSTANCE) == DMA2_Stream1) || \
+ ((INSTANCE) == DMA2_Stream2) || \
+ ((INSTANCE) == DMA2_Stream3) || \
+ ((INSTANCE) == DMA2_Stream4) || \
+ ((INSTANCE) == DMA2_Stream5) || \
+ ((INSTANCE) == DMA2_Stream6) || \
+ ((INSTANCE) == DMA2_Stream7))
+
+/******************************* GPIO Instances *******************************/
+#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
+ ((INSTANCE) == GPIOB) || \
+ ((INSTANCE) == GPIOC) || \
+ ((INSTANCE) == GPIOD) || \
+ ((INSTANCE) == GPIOE) || \
+ ((INSTANCE) == GPIOH))
+
+/******************************** I2C Instances *******************************/
+#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
+ ((INSTANCE) == I2C2) || \
+ ((INSTANCE) == I2C3))
+
+/******************************** I2S Instances *******************************/
+#define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI2) || \
+ ((INSTANCE) == SPI3))
+
+/*************************** I2S Extended Instances ***************************/
+#define IS_I2S_ALL_INSTANCE_EXT(PERIPH) (((INSTANCE) == SPI2) || \
+ ((INSTANCE) == SPI3) || \
+ ((INSTANCE) == I2S2ext) || \
+ ((INSTANCE) == I2S3ext))
+
+/****************************** RTC Instances *********************************/
+#define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
+
+/******************************** SPI Instances *******************************/
+#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
+ ((INSTANCE) == SPI2) || \
+ ((INSTANCE) == SPI3) || \
+ ((INSTANCE) == SPI4))
+
+/*************************** SPI Extended Instances ***************************/
+#define IS_SPI_ALL_INSTANCE_EXT(INSTANCE) (((INSTANCE) == SPI1) || \
+ ((INSTANCE) == SPI2) || \
+ ((INSTANCE) == SPI3) || \
+ ((INSTANCE) == I2S2ext) || \
+ ((INSTANCE) == I2S3ext))
+
+/****************** TIM Instances : All supported instances *******************/
+#define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM9) || \
+ ((INSTANCE) == TIM10) || \
+ ((INSTANCE) == TIM11))
+
+/************* TIM Instances : at least 1 capture/compare channel *************/
+#define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM9) || \
+ ((INSTANCE) == TIM10) || \
+ ((INSTANCE) == TIM11))
+
+/************ TIM Instances : at least 2 capture/compare channels *************/
+#define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM9))
+
+/************ TIM Instances : at least 3 capture/compare channels *************/
+#define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5))
+
+/************ TIM Instances : at least 4 capture/compare channels *************/
+#define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5))
+
+/******************** TIM Instances : Advanced-control timers *****************/
+#define IS_TIM_ADVANCED_INSTANCE(INSTANCE) ((INSTANCE) == TIM1)
+
+/******************* TIM Instances : Timer input XOR function *****************/
+#define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5))
+
+/****************** TIM Instances : DMA requests generation (UDE) *************/
+#define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5))
+
+/************ TIM Instances : DMA requests generation (CCxDE) *****************/
+#define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5))
+
+/************ TIM Instances : DMA requests generation (COMDE) *****************/
+#define IS_TIM_CCDMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5))
+
+/******************** TIM Instances : DMA burst feature ***********************/
+#define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5))
+
+/****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/
+#define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM9))
+
+/*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
+#define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM9))
+
+/********************** TIM Instances : 32 bit Counter ************************/
+#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)(((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM5))
+
+/***************** TIM Instances : external trigger input availabe ************/
+#define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5))
+
+/****************** TIM Instances : remapping capability **********************/
+#define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM11))
+
+/******************* TIM Instances : output(s) available **********************/
+#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
+ ((((INSTANCE) == TIM1) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM2) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM3) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM4) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM5) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM9) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2))) \
+ || \
+ (((INSTANCE) == TIM10) && \
+ (((CHANNEL) == TIM_CHANNEL_1))) \
+ || \
+ (((INSTANCE) == TIM11) && \
+ (((CHANNEL) == TIM_CHANNEL_1))))
+
+/************ TIM Instances : complementary output(s) available ***************/
+#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
+ ((((INSTANCE) == TIM1) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3))))
+
+/******************** USART Instances : Synchronous mode **********************/
+#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART6))
+
+/******************** UART Instances : Asynchronous mode **********************/
+#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART6))
+
+/****************** UART Instances : Hardware Flow control ********************/
+#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART6))
+
+/********************* UART Instances : Smard card mode ***********************/
+#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART6))
+
+/*********************** UART Instances : IRDA mode ***************************/
+#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART6))
+
+
+/*********************** PCD Instances ****************************************/
+#define IS_PCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS))
+
+/*********************** HCD Instances ****************************************/
+#define IS_HCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS))
+
+/****************************** IWDG Instances ********************************/
+#define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
+
+/****************************** WWDG Instances ********************************/
+#define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
+
+/****************************** SDIO Instances ********************************/
+#define IS_SDIO_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SDIO)
+
+/****************************** USB Exported Constants ************************/
+#define USB_OTG_FS_HOST_MAX_CHANNEL_NBR 8U
+#define USB_OTG_FS_MAX_IN_ENDPOINTS 4U /* Including EP0 */
+#define USB_OTG_FS_MAX_OUT_ENDPOINTS 4U /* Including EP0 */
+#define USB_OTG_FS_TOTAL_FIFO_SIZE 1280U /* in Bytes */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* __STM32F401xE_H */
+
+
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Device/ST/STM32F4xx/Include/stm32f405xx.h b/Device/ST/STM32F4xx/Include/stm32f405xx.h
new file mode 100644
index 0000000..ff2694a
--- /dev/null
+++ b/Device/ST/STM32F4xx/Include/stm32f405xx.h
@@ -0,0 +1,7491 @@
+/**
+ ******************************************************************************
+ * @file stm32f405xx.h
+ * @author MCD Application Team
+ * @version V2.5.0
+ * @date 22-April-2016
+ * @brief CMSIS STM32F405xx Device Peripheral Access Layer Header File.
+ *
+ * This file contains:
+ * - Data structures and the address mapping for all peripherals
+ * - peripherals registers declarations and bits definition
+ * - Macros to access peripheral’s registers hardware
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/** @addtogroup CMSIS
+ * @{
+ */
+
+/** @addtogroup stm32f405xx
+ * @{
+ */
+
+#ifndef __STM32F405xx_H
+#define __STM32F405xx_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif /* __cplusplus */
+
+
+/** @addtogroup Configuration_section_for_CMSIS
+ * @{
+ */
+
+/**
+ * @brief Configuration of the Cortex-M4 Processor and Core Peripherals
+ */
+#define __CM4_REV 0x0001U /*!< Core revision r0p1 */
+#define __MPU_PRESENT 1U /*!< STM32F4XX provides an MPU */
+#define __NVIC_PRIO_BITS 4U /*!< STM32F4XX uses 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */
+#define __FPU_PRESENT 1U /*!< FPU present */
+
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_interrupt_number_definition
+ * @{
+ */
+
+/**
+ * @brief STM32F4XX Interrupt Number Definition, according to the selected device
+ * in @ref Library_configuration_section
+ */
+typedef enum
+{
+/****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/
+ NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
+ MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */
+ BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */
+ UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */
+ SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */
+ DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */
+ PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */
+ SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */
+/****** STM32 specific Interrupt Numbers **********************************************************************/
+ WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
+ PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */
+ TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */
+ RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */
+ FLASH_IRQn = 4, /*!< FLASH global Interrupt */
+ RCC_IRQn = 5, /*!< RCC global Interrupt */
+ EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */
+ EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */
+ EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */
+ EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */
+ EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */
+ DMA1_Stream0_IRQn = 11, /*!< DMA1 Stream 0 global Interrupt */
+ DMA1_Stream1_IRQn = 12, /*!< DMA1 Stream 1 global Interrupt */
+ DMA1_Stream2_IRQn = 13, /*!< DMA1 Stream 2 global Interrupt */
+ DMA1_Stream3_IRQn = 14, /*!< DMA1 Stream 3 global Interrupt */
+ DMA1_Stream4_IRQn = 15, /*!< DMA1 Stream 4 global Interrupt */
+ DMA1_Stream5_IRQn = 16, /*!< DMA1 Stream 5 global Interrupt */
+ DMA1_Stream6_IRQn = 17, /*!< DMA1 Stream 6 global Interrupt */
+ ADC_IRQn = 18, /*!< ADC1, ADC2 and ADC3 global Interrupts */
+ CAN1_TX_IRQn = 19, /*!< CAN1 TX Interrupt */
+ CAN1_RX0_IRQn = 20, /*!< CAN1 RX0 Interrupt */
+ CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */
+ CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */
+ EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
+ TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break interrupt and TIM9 global interrupt */
+ TIM1_UP_TIM10_IRQn = 25, /*!< TIM1 Update Interrupt and TIM10 global interrupt */
+ TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */
+ TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
+ TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
+ TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
+ TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
+ I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
+ I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
+ I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
+ I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
+ SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
+ SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
+ USART1_IRQn = 37, /*!< USART1 global Interrupt */
+ USART2_IRQn = 38, /*!< USART2 global Interrupt */
+ USART3_IRQn = 39, /*!< USART3 global Interrupt */
+ EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
+ RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */
+ OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS Wakeup through EXTI line interrupt */
+ TIM8_BRK_TIM12_IRQn = 43, /*!< TIM8 Break Interrupt and TIM12 global interrupt */
+ TIM8_UP_TIM13_IRQn = 44, /*!< TIM8 Update Interrupt and TIM13 global interrupt */
+ TIM8_TRG_COM_TIM14_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */
+ TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */
+ DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */
+ FSMC_IRQn = 48, /*!< FSMC global Interrupt */
+ SDIO_IRQn = 49, /*!< SDIO global Interrupt */
+ TIM5_IRQn = 50, /*!< TIM5 global Interrupt */
+ SPI3_IRQn = 51, /*!< SPI3 global Interrupt */
+ UART4_IRQn = 52, /*!< UART4 global Interrupt */
+ UART5_IRQn = 53, /*!< UART5 global Interrupt */
+ TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC1&2 underrun error interrupts */
+ TIM7_IRQn = 55, /*!< TIM7 global interrupt */
+ DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */
+ DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */
+ DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */
+ DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */
+ DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */
+ CAN2_TX_IRQn = 63, /*!< CAN2 TX Interrupt */
+ CAN2_RX0_IRQn = 64, /*!< CAN2 RX0 Interrupt */
+ CAN2_RX1_IRQn = 65, /*!< CAN2 RX1 Interrupt */
+ CAN2_SCE_IRQn = 66, /*!< CAN2 SCE Interrupt */
+ OTG_FS_IRQn = 67, /*!< USB OTG FS global Interrupt */
+ DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */
+ DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */
+ DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */
+ USART6_IRQn = 71, /*!< USART6 global interrupt */
+ I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */
+ I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */
+ OTG_HS_EP1_OUT_IRQn = 74, /*!< USB OTG HS End Point 1 Out global interrupt */
+ OTG_HS_EP1_IN_IRQn = 75, /*!< USB OTG HS End Point 1 In global interrupt */
+ OTG_HS_WKUP_IRQn = 76, /*!< USB OTG HS Wakeup through EXTI interrupt */
+ OTG_HS_IRQn = 77, /*!< USB OTG HS global interrupt */
+ HASH_RNG_IRQn = 80, /*!< Hash and RNG global interrupt */
+ FPU_IRQn = 81 /*!< FPU global interrupt */
+} IRQn_Type;
+
+/**
+ * @}
+ */
+
+#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
+#include "system_stm32f4xx.h"
+#include <stdint.h>
+
+/** @addtogroup Peripheral_registers_structures
+ * @{
+ */
+
+/**
+ * @brief Analog to Digital Converter
+ */
+
+typedef struct
+{
+ __IO uint32_t SR; /*!< ADC status register, Address offset: 0x00 */
+ __IO uint32_t CR1; /*!< ADC control register 1, Address offset: 0x04 */
+ __IO uint32_t CR2; /*!< ADC control register 2, Address offset: 0x08 */
+ __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x0C */
+ __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x10 */
+ __IO uint32_t JOFR1; /*!< ADC injected channel data offset register 1, Address offset: 0x14 */
+ __IO uint32_t JOFR2; /*!< ADC injected channel data offset register 2, Address offset: 0x18 */
+ __IO uint32_t JOFR3; /*!< ADC injected channel data offset register 3, Address offset: 0x1C */
+ __IO uint32_t JOFR4; /*!< ADC injected channel data offset register 4, Address offset: 0x20 */
+ __IO uint32_t HTR; /*!< ADC watchdog higher threshold register, Address offset: 0x24 */
+ __IO uint32_t LTR; /*!< ADC watchdog lower threshold register, Address offset: 0x28 */
+ __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x2C */
+ __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x30 */
+ __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x34 */
+ __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x38*/
+ __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x3C */
+ __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x40 */
+ __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x44 */
+ __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x48 */
+ __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x4C */
+} ADC_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1 base address + 0x300 */
+ __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1 base address + 0x304 */
+ __IO uint32_t CDR; /*!< ADC common regular data register for dual
+ AND triple modes, Address offset: ADC1 base address + 0x308 */
+} ADC_Common_TypeDef;
+
+
+/**
+ * @brief Controller Area Network TxMailBox
+ */
+
+typedef struct
+{
+ __IO uint32_t TIR; /*!< CAN TX mailbox identifier register */
+ __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */
+ __IO uint32_t TDLR; /*!< CAN mailbox data low register */
+ __IO uint32_t TDHR; /*!< CAN mailbox data high register */
+} CAN_TxMailBox_TypeDef;
+
+/**
+ * @brief Controller Area Network FIFOMailBox
+ */
+
+typedef struct
+{
+ __IO uint32_t RIR; /*!< CAN receive FIFO mailbox identifier register */
+ __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */
+ __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */
+ __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */
+} CAN_FIFOMailBox_TypeDef;
+
+/**
+ * @brief Controller Area Network FilterRegister
+ */
+
+typedef struct
+{
+ __IO uint32_t FR1; /*!< CAN Filter bank register 1 */
+ __IO uint32_t FR2; /*!< CAN Filter bank register 1 */
+} CAN_FilterRegister_TypeDef;
+
+/**
+ * @brief Controller Area Network
+ */
+
+typedef struct
+{
+ __IO uint32_t MCR; /*!< CAN master control register, Address offset: 0x00 */
+ __IO uint32_t MSR; /*!< CAN master status register, Address offset: 0x04 */
+ __IO uint32_t TSR; /*!< CAN transmit status register, Address offset: 0x08 */
+ __IO uint32_t RF0R; /*!< CAN receive FIFO 0 register, Address offset: 0x0C */
+ __IO uint32_t RF1R; /*!< CAN receive FIFO 1 register, Address offset: 0x10 */
+ __IO uint32_t IER; /*!< CAN interrupt enable register, Address offset: 0x14 */
+ __IO uint32_t ESR; /*!< CAN error status register, Address offset: 0x18 */
+ __IO uint32_t BTR; /*!< CAN bit timing register, Address offset: 0x1C */
+ uint32_t RESERVED0[88]; /*!< Reserved, 0x020 - 0x17F */
+ CAN_TxMailBox_TypeDef sTxMailBox[3]; /*!< CAN Tx MailBox, Address offset: 0x180 - 0x1AC */
+ CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; /*!< CAN FIFO MailBox, Address offset: 0x1B0 - 0x1CC */
+ uint32_t RESERVED1[12]; /*!< Reserved, 0x1D0 - 0x1FF */
+ __IO uint32_t FMR; /*!< CAN filter master register, Address offset: 0x200 */
+ __IO uint32_t FM1R; /*!< CAN filter mode register, Address offset: 0x204 */
+ uint32_t RESERVED2; /*!< Reserved, 0x208 */
+ __IO uint32_t FS1R; /*!< CAN filter scale register, Address offset: 0x20C */
+ uint32_t RESERVED3; /*!< Reserved, 0x210 */
+ __IO uint32_t FFA1R; /*!< CAN filter FIFO assignment register, Address offset: 0x214 */
+ uint32_t RESERVED4; /*!< Reserved, 0x218 */
+ __IO uint32_t FA1R; /*!< CAN filter activation register, Address offset: 0x21C */
+ uint32_t RESERVED5[8]; /*!< Reserved, 0x220-0x23F */
+ CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register, Address offset: 0x240-0x31C */
+} CAN_TypeDef;
+
+/**
+ * @brief CRC calculation unit
+ */
+
+typedef struct
+{
+ __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
+ __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
+ uint8_t RESERVED0; /*!< Reserved, 0x05 */
+ uint16_t RESERVED1; /*!< Reserved, 0x06 */
+ __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
+} CRC_TypeDef;
+
+/**
+ * @brief Digital to Analog Converter
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */
+ __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */
+ __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
+ __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */
+ __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */
+ __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
+ __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */
+ __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */
+ __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */
+ __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */
+ __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */
+ __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */
+ __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */
+ __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */
+} DAC_TypeDef;
+
+/**
+ * @brief Debug MCU
+ */
+
+typedef struct
+{
+ __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
+ __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
+ __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */
+ __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */
+}DBGMCU_TypeDef;
+
+
+/**
+ * @brief DMA Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< DMA stream x configuration register */
+ __IO uint32_t NDTR; /*!< DMA stream x number of data register */
+ __IO uint32_t PAR; /*!< DMA stream x peripheral address register */
+ __IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */
+ __IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */
+ __IO uint32_t FCR; /*!< DMA stream x FIFO control register */
+} DMA_Stream_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t LISR; /*!< DMA low interrupt status register, Address offset: 0x00 */
+ __IO uint32_t HISR; /*!< DMA high interrupt status register, Address offset: 0x04 */
+ __IO uint32_t LIFCR; /*!< DMA low interrupt flag clear register, Address offset: 0x08 */
+ __IO uint32_t HIFCR; /*!< DMA high interrupt flag clear register, Address offset: 0x0C */
+} DMA_TypeDef;
+
+
+/**
+ * @brief External Interrupt/Event Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t IMR; /*!< EXTI Interrupt mask register, Address offset: 0x00 */
+ __IO uint32_t EMR; /*!< EXTI Event mask register, Address offset: 0x04 */
+ __IO uint32_t RTSR; /*!< EXTI Rising trigger selection register, Address offset: 0x08 */
+ __IO uint32_t FTSR; /*!< EXTI Falling trigger selection register, Address offset: 0x0C */
+ __IO uint32_t SWIER; /*!< EXTI Software interrupt event register, Address offset: 0x10 */
+ __IO uint32_t PR; /*!< EXTI Pending register, Address offset: 0x14 */
+} EXTI_TypeDef;
+
+/**
+ * @brief FLASH Registers
+ */
+
+typedef struct
+{
+ __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */
+ __IO uint32_t KEYR; /*!< FLASH key register, Address offset: 0x04 */
+ __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x08 */
+ __IO uint32_t SR; /*!< FLASH status register, Address offset: 0x0C */
+ __IO uint32_t CR; /*!< FLASH control register, Address offset: 0x10 */
+ __IO uint32_t OPTCR; /*!< FLASH option control register , Address offset: 0x14 */
+ __IO uint32_t OPTCR1; /*!< FLASH option control register 1, Address offset: 0x18 */
+} FLASH_TypeDef;
+
+
+/**
+ * @brief Flexible Static Memory Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */
+} FSMC_Bank1_TypeDef;
+
+/**
+ * @brief Flexible Static Memory Controller Bank1E
+ */
+
+typedef struct
+{
+ __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */
+} FSMC_Bank1E_TypeDef;
+
+/**
+ * @brief Flexible Static Memory Controller Bank2
+ */
+
+typedef struct
+{
+ __IO uint32_t PCR2; /*!< NAND Flash control register 2, Address offset: 0x60 */
+ __IO uint32_t SR2; /*!< NAND Flash FIFO status and interrupt register 2, Address offset: 0x64 */
+ __IO uint32_t PMEM2; /*!< NAND Flash Common memory space timing register 2, Address offset: 0x68 */
+ __IO uint32_t PATT2; /*!< NAND Flash Attribute memory space timing register 2, Address offset: 0x6C */
+ uint32_t RESERVED0; /*!< Reserved, 0x70 */
+ __IO uint32_t ECCR2; /*!< NAND Flash ECC result registers 2, Address offset: 0x74 */
+ uint32_t RESERVED1; /*!< Reserved, 0x78 */
+ uint32_t RESERVED2; /*!< Reserved, 0x7C */
+ __IO uint32_t PCR3; /*!< NAND Flash control register 3, Address offset: 0x80 */
+ __IO uint32_t SR3; /*!< NAND Flash FIFO status and interrupt register 3, Address offset: 0x84 */
+ __IO uint32_t PMEM3; /*!< NAND Flash Common memory space timing register 3, Address offset: 0x88 */
+ __IO uint32_t PATT3; /*!< NAND Flash Attribute memory space timing register 3, Address offset: 0x8C */
+ uint32_t RESERVED3; /*!< Reserved, 0x90 */
+ __IO uint32_t ECCR3; /*!< NAND Flash ECC result registers 3, Address offset: 0x94 */
+} FSMC_Bank2_3_TypeDef;
+
+/**
+ * @brief Flexible Static Memory Controller Bank4
+ */
+
+typedef struct
+{
+ __IO uint32_t PCR4; /*!< PC Card control register 4, Address offset: 0xA0 */
+ __IO uint32_t SR4; /*!< PC Card FIFO status and interrupt register 4, Address offset: 0xA4 */
+ __IO uint32_t PMEM4; /*!< PC Card Common memory space timing register 4, Address offset: 0xA8 */
+ __IO uint32_t PATT4; /*!< PC Card Attribute memory space timing register 4, Address offset: 0xAC */
+ __IO uint32_t PIO4; /*!< PC Card I/O space timing register 4, Address offset: 0xB0 */
+} FSMC_Bank4_TypeDef;
+
+
+/**
+ * @brief General Purpose I/O
+ */
+
+typedef struct
+{
+ __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
+ __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */
+ __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */
+ __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
+ __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
+ __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
+ __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */
+ __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
+ __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */
+} GPIO_TypeDef;
+
+/**
+ * @brief System configuration controller
+ */
+
+typedef struct
+{
+ __IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */
+ __IO uint32_t PMC; /*!< SYSCFG peripheral mode configuration register, Address offset: 0x04 */
+ __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
+ uint32_t RESERVED[2]; /*!< Reserved, 0x18-0x1C */
+ __IO uint32_t CMPCR; /*!< SYSCFG Compensation cell control register, Address offset: 0x20 */
+} SYSCFG_TypeDef;
+
+/**
+ * @brief Inter-integrated Circuit Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */
+ __IO uint32_t OAR1; /*!< I2C Own address register 1, Address offset: 0x08 */
+ __IO uint32_t OAR2; /*!< I2C Own address register 2, Address offset: 0x0C */
+ __IO uint32_t DR; /*!< I2C Data register, Address offset: 0x10 */
+ __IO uint32_t SR1; /*!< I2C Status register 1, Address offset: 0x14 */
+ __IO uint32_t SR2; /*!< I2C Status register 2, Address offset: 0x18 */
+ __IO uint32_t CCR; /*!< I2C Clock control register, Address offset: 0x1C */
+ __IO uint32_t TRISE; /*!< I2C TRISE register, Address offset: 0x20 */
+ __IO uint32_t FLTR; /*!< I2C FLTR register, Address offset: 0x24 */
+} I2C_TypeDef;
+
+/**
+ * @brief Independent WATCHDOG
+ */
+
+typedef struct
+{
+ __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */
+ __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */
+ __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */
+ __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */
+} IWDG_TypeDef;
+
+/**
+ * @brief Power Control
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */
+ __IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */
+} PWR_TypeDef;
+
+/**
+ * @brief Reset and Clock Control
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */
+ __IO uint32_t PLLCFGR; /*!< RCC PLL configuration register, Address offset: 0x04 */
+ __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x08 */
+ __IO uint32_t CIR; /*!< RCC clock interrupt register, Address offset: 0x0C */
+ __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x10 */
+ __IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x14 */
+ __IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0x18 */
+ uint32_t RESERVED0; /*!< Reserved, 0x1C */
+ __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x20 */
+ __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x24 */
+ uint32_t RESERVED1[2]; /*!< Reserved, 0x28-0x2C */
+ __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clock register, Address offset: 0x30 */
+ __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clock register, Address offset: 0x34 */
+ __IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clock register, Address offset: 0x38 */
+ uint32_t RESERVED2; /*!< Reserved, 0x3C */
+ __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x40 */
+ __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x44 */
+ uint32_t RESERVED3[2]; /*!< Reserved, 0x48-0x4C */
+ __IO uint32_t AHB1LPENR; /*!< RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 */
+ __IO uint32_t AHB2LPENR; /*!< RCC AHB2 peripheral clock enable in low power mode register, Address offset: 0x54 */
+ __IO uint32_t AHB3LPENR; /*!< RCC AHB3 peripheral clock enable in low power mode register, Address offset: 0x58 */
+ uint32_t RESERVED4; /*!< Reserved, 0x5C */
+ __IO uint32_t APB1LPENR; /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 */
+ __IO uint32_t APB2LPENR; /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 */
+ uint32_t RESERVED5[2]; /*!< Reserved, 0x68-0x6C */
+ __IO uint32_t BDCR; /*!< RCC Backup domain control register, Address offset: 0x70 */
+ __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x74 */
+ uint32_t RESERVED6[2]; /*!< Reserved, 0x78-0x7C */
+ __IO uint32_t SSCGR; /*!< RCC spread spectrum clock generation register, Address offset: 0x80 */
+ __IO uint32_t PLLI2SCFGR; /*!< RCC PLLI2S configuration register, Address offset: 0x84 */
+
+} RCC_TypeDef;
+
+/**
+ * @brief Real-Time Clock
+ */
+
+typedef struct
+{
+ __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
+ __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */
+ __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */
+ __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */
+ __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */
+ __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */
+ __IO uint32_t CALIBR; /*!< RTC calibration register, Address offset: 0x18 */
+ __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */
+ __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */
+ __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */
+ __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */
+ __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */
+ __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */
+ __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */
+ __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */
+ __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */
+ __IO uint32_t TAFCR; /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */
+ __IO uint32_t ALRMASSR;/*!< RTC alarm A sub second register, Address offset: 0x44 */
+ __IO uint32_t ALRMBSSR;/*!< RTC alarm B sub second register, Address offset: 0x48 */
+ uint32_t RESERVED7; /*!< Reserved, 0x4C */
+ __IO uint32_t BKP0R; /*!< RTC backup register 1, Address offset: 0x50 */
+ __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */
+ __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */
+ __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */
+ __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */
+ __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */
+ __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */
+ __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */
+ __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */
+ __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */
+ __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */
+ __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */
+ __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */
+ __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */
+ __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */
+ __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */
+ __IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */
+ __IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */
+ __IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */
+ __IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */
+} RTC_TypeDef;
+
+
+/**
+ * @brief SD host Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t POWER; /*!< SDIO power control register, Address offset: 0x00 */
+ __IO uint32_t CLKCR; /*!< SDI clock control register, Address offset: 0x04 */
+ __IO uint32_t ARG; /*!< SDIO argument register, Address offset: 0x08 */
+ __IO uint32_t CMD; /*!< SDIO command register, Address offset: 0x0C */
+ __I uint32_t RESPCMD; /*!< SDIO command response register, Address offset: 0x10 */
+ __I uint32_t RESP1; /*!< SDIO response 1 register, Address offset: 0x14 */
+ __I uint32_t RESP2; /*!< SDIO response 2 register, Address offset: 0x18 */
+ __I uint32_t RESP3; /*!< SDIO response 3 register, Address offset: 0x1C */
+ __I uint32_t RESP4; /*!< SDIO response 4 register, Address offset: 0x20 */
+ __IO uint32_t DTIMER; /*!< SDIO data timer register, Address offset: 0x24 */
+ __IO uint32_t DLEN; /*!< SDIO data length register, Address offset: 0x28 */
+ __IO uint32_t DCTRL; /*!< SDIO data control register, Address offset: 0x2C */
+ __I uint32_t DCOUNT; /*!< SDIO data counter register, Address offset: 0x30 */
+ __I uint32_t STA; /*!< SDIO status register, Address offset: 0x34 */
+ __IO uint32_t ICR; /*!< SDIO interrupt clear register, Address offset: 0x38 */
+ __IO uint32_t MASK; /*!< SDIO mask register, Address offset: 0x3C */
+ uint32_t RESERVED0[2]; /*!< Reserved, 0x40-0x44 */
+ __I uint32_t FIFOCNT; /*!< SDIO FIFO counter register, Address offset: 0x48 */
+ uint32_t RESERVED1[13]; /*!< Reserved, 0x4C-0x7C */
+ __IO uint32_t FIFO; /*!< SDIO data FIFO register, Address offset: 0x80 */
+} SDIO_TypeDef;
+
+/**
+ * @brief Serial Peripheral Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t CR1; /*!< SPI control register 1 (not used in I2S mode), Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< SPI control register 2, Address offset: 0x04 */
+ __IO uint32_t SR; /*!< SPI status register, Address offset: 0x08 */
+ __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */
+ __IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
+ __IO uint32_t RXCRCR; /*!< SPI RX CRC register (not used in I2S mode), Address offset: 0x14 */
+ __IO uint32_t TXCRCR; /*!< SPI TX CRC register (not used in I2S mode), Address offset: 0x18 */
+ __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */
+ __IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */
+} SPI_TypeDef;
+
+/**
+ * @brief TIM
+ */
+
+typedef struct
+{
+ __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
+ __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */
+ __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
+ __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
+ __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
+ __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
+ __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
+ __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
+ __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
+ __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */
+ __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
+ __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */
+ __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
+ __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
+ __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
+ __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
+ __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
+ __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
+ __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */
+ __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */
+} TIM_TypeDef;
+
+/**
+ * @brief Universal Synchronous Asynchronous Receiver Transmitter
+ */
+
+typedef struct
+{
+ __IO uint32_t SR; /*!< USART Status register, Address offset: 0x00 */
+ __IO uint32_t DR; /*!< USART Data register, Address offset: 0x04 */
+ __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x08 */
+ __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x0C */
+ __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x10 */
+ __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x14 */
+ __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x18 */
+} USART_TypeDef;
+
+/**
+ * @brief Window WATCHDOG
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
+ __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
+ __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
+} WWDG_TypeDef;
+
+
+/**
+ * @brief RNG
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */
+ __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */
+ __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */
+} RNG_TypeDef;
+
+
+
+/**
+ * @brief __USB_OTG_Core_register
+ */
+typedef struct
+{
+ __IO uint32_t GOTGCTL; /*!< USB_OTG Control and Status Register Address offset : 0x00 */
+ __IO uint32_t GOTGINT; /*!< USB_OTG Interrupt Register Address offset : 0x04 */
+ __IO uint32_t GAHBCFG; /*!< Core AHB Configuration Register Address offset : 0x08 */
+ __IO uint32_t GUSBCFG; /*!< Core USB Configuration Register Address offset : 0x0C */
+ __IO uint32_t GRSTCTL; /*!< Core Reset Register Address offset : 0x10 */
+ __IO uint32_t GINTSTS; /*!< Core Interrupt Register Address offset : 0x14 */
+ __IO uint32_t GINTMSK; /*!< Core Interrupt Mask Register Address offset : 0x18 */
+ __IO uint32_t GRXSTSR; /*!< Receive Sts Q Read Register Address offset : 0x1C */
+ __IO uint32_t GRXSTSP; /*!< Receive Sts Q Read & POP Register Address offset : 0x20 */
+ __IO uint32_t GRXFSIZ; /* Receive FIFO Size Register Address offset : 0x24 */
+ __IO uint32_t DIEPTXF0_HNPTXFSIZ; /*!< EP0 / Non Periodic Tx FIFO Size Register Address offset : 0x28 */
+ __IO uint32_t HNPTXSTS; /*!< Non Periodic Tx FIFO/Queue Sts reg Address offset : 0x2C */
+ uint32_t Reserved30[2]; /* Reserved Address offset : 0x30 */
+ __IO uint32_t GCCFG; /*!< General Purpose IO Register Address offset : 0x38 */
+ __IO uint32_t CID; /*!< User ID Register Address offset : 0x3C */
+ uint32_t Reserved40[48]; /*!< Reserved Address offset : 0x40-0xFF */
+ __IO uint32_t HPTXFSIZ; /*!< Host Periodic Tx FIFO Size Reg Address offset : 0x100 */
+ __IO uint32_t DIEPTXF[0x0F]; /*!< dev Periodic Transmit FIFO */
+}
+USB_OTG_GlobalTypeDef;
+
+
+
+/**
+ * @brief __device_Registers
+ */
+typedef struct
+{
+ __IO uint32_t DCFG; /*!< dev Configuration Register Address offset : 0x800 */
+ __IO uint32_t DCTL; /*!< dev Control Register Address offset : 0x804 */
+ __IO uint32_t DSTS; /*!< dev Status Register (RO) Address offset : 0x808 */
+ uint32_t Reserved0C; /*!< Reserved Address offset : 0x80C */
+ __IO uint32_t DIEPMSK; /* !< dev IN Endpoint Mask Address offset : 0x810 */
+ __IO uint32_t DOEPMSK; /*!< dev OUT Endpoint Mask Address offset : 0x814 */
+ __IO uint32_t DAINT; /*!< dev All Endpoints Itr Reg Address offset : 0x818 */
+ __IO uint32_t DAINTMSK; /*!< dev All Endpoints Itr Mask Address offset : 0x81C */
+ uint32_t Reserved20; /*!< Reserved Address offset : 0x820 */
+ uint32_t Reserved9; /*!< Reserved Address offset : 0x824 */
+ __IO uint32_t DVBUSDIS; /*!< dev VBUS discharge Register Address offset : 0x828 */
+ __IO uint32_t DVBUSPULSE; /*!< dev VBUS Pulse Register Address offset : 0x82C */
+ __IO uint32_t DTHRCTL; /*!< dev thr Address offset : 0x830 */
+ __IO uint32_t DIEPEMPMSK; /*!< dev empty msk Address offset : 0x834 */
+ __IO uint32_t DEACHINT; /*!< dedicated EP interrupt Address offset : 0x838 */
+ __IO uint32_t DEACHMSK; /*!< dedicated EP msk Address offset : 0x83C */
+ uint32_t Reserved40; /*!< dedicated EP mask Address offset : 0x840 */
+ __IO uint32_t DINEP1MSK; /*!< dedicated EP mask Address offset : 0x844 */
+ uint32_t Reserved44[15]; /*!< Reserved Address offset : 0x844-0x87C */
+ __IO uint32_t DOUTEP1MSK; /*!< dedicated EP msk Address offset : 0x884 */
+}
+USB_OTG_DeviceTypeDef;
+
+
+/**
+ * @brief __IN_Endpoint-Specific_Register
+ */
+typedef struct
+{
+ __IO uint32_t DIEPCTL; /* dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h */
+ uint32_t Reserved04; /* Reserved 900h + (ep_num * 20h) + 04h */
+ __IO uint32_t DIEPINT; /* dev IN Endpoint Itr Reg 900h + (ep_num * 20h) + 08h */
+ uint32_t Reserved0C; /* Reserved 900h + (ep_num * 20h) + 0Ch */
+ __IO uint32_t DIEPTSIZ; /* IN Endpoint Txfer Size 900h + (ep_num * 20h) + 10h */
+ __IO uint32_t DIEPDMA; /* IN Endpoint DMA Address Reg 900h + (ep_num * 20h) + 14h */
+ __IO uint32_t DTXFSTS; /*IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h */
+ uint32_t Reserved18; /* Reserved 900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch */
+}
+USB_OTG_INEndpointTypeDef;
+
+
+/**
+ * @brief __OUT_Endpoint-Specific_Registers
+ */
+typedef struct
+{
+ __IO uint32_t DOEPCTL; /* dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h*/
+ uint32_t Reserved04; /* Reserved B00h + (ep_num * 20h) + 04h*/
+ __IO uint32_t DOEPINT; /* dev OUT Endpoint Itr Reg B00h + (ep_num * 20h) + 08h*/
+ uint32_t Reserved0C; /* Reserved B00h + (ep_num * 20h) + 0Ch*/
+ __IO uint32_t DOEPTSIZ; /* dev OUT Endpoint Txfer Size B00h + (ep_num * 20h) + 10h*/
+ __IO uint32_t DOEPDMA; /* dev OUT Endpoint DMA Address B00h + (ep_num * 20h) + 14h*/
+ uint32_t Reserved18[2]; /* Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch*/
+}
+USB_OTG_OUTEndpointTypeDef;
+
+
+/**
+ * @brief __Host_Mode_Register_Structures
+ */
+typedef struct
+{
+ __IO uint32_t HCFG; /* Host Configuration Register 400h*/
+ __IO uint32_t HFIR; /* Host Frame Interval Register 404h*/
+ __IO uint32_t HFNUM; /* Host Frame Nbr/Frame Remaining 408h*/
+ uint32_t Reserved40C; /* Reserved 40Ch*/
+ __IO uint32_t HPTXSTS; /* Host Periodic Tx FIFO/ Queue Status 410h*/
+ __IO uint32_t HAINT; /* Host All Channels Interrupt Register 414h*/
+ __IO uint32_t HAINTMSK; /* Host All Channels Interrupt Mask 418h*/
+}
+USB_OTG_HostTypeDef;
+
+
+/**
+ * @brief __Host_Channel_Specific_Registers
+ */
+typedef struct
+{
+ __IO uint32_t HCCHAR;
+ __IO uint32_t HCSPLT;
+ __IO uint32_t HCINT;
+ __IO uint32_t HCINTMSK;
+ __IO uint32_t HCTSIZ;
+ __IO uint32_t HCDMA;
+ uint32_t Reserved[2];
+}
+USB_OTG_HostChannelTypeDef;
+
+
+/**
+ * @brief Peripheral_memory_map
+ */
+#define FLASH_BASE 0x08000000U /*!< FLASH(up to 1 MB) base address in the alias region */
+#define CCMDATARAM_BASE 0x10000000U /*!< CCM(core coupled memory) data RAM(64 KB) base address in the alias region */
+#define SRAM1_BASE 0x20000000U /*!< SRAM1(112 KB) base address in the alias region */
+#define SRAM2_BASE 0x2001C000U /*!< SRAM2(16 KB) base address in the alias region */
+#define PERIPH_BASE 0x40000000U /*!< Peripheral base address in the alias region */
+#define BKPSRAM_BASE 0x40024000U /*!< Backup SRAM(4 KB) base address in the alias region */
+#define FSMC_R_BASE 0xA0000000U /*!< FSMC registers base address */
+#define SRAM1_BB_BASE 0x22000000U /*!< SRAM1(112 KB) base address in the bit-band region */
+#define SRAM2_BB_BASE 0x22380000U /*!< SRAM2(16 KB) base address in the bit-band region */
+#define PERIPH_BB_BASE 0x42000000U /*!< Peripheral base address in the bit-band region */
+#define BKPSRAM_BB_BASE 0x42480000U /*!< Backup SRAM(4 KB) base address in the bit-band region */
+#define FLASH_END 0x080FFFFFU /*!< FLASH end address */
+#define CCMDATARAM_END 0x1000FFFFU /*!< CCM data RAM end address */
+
+/* Legacy defines */
+#define SRAM_BASE SRAM1_BASE
+#define SRAM_BB_BASE SRAM1_BB_BASE
+
+
+/*!< Peripheral memory map */
+#define APB1PERIPH_BASE PERIPH_BASE
+#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000U)
+#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000U)
+#define AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000U)
+
+/*!< APB1 peripherals */
+#define TIM2_BASE (APB1PERIPH_BASE + 0x0000U)
+#define TIM3_BASE (APB1PERIPH_BASE + 0x0400U)
+#define TIM4_BASE (APB1PERIPH_BASE + 0x0800U)
+#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00U)
+#define TIM6_BASE (APB1PERIPH_BASE + 0x1000U)
+#define TIM7_BASE (APB1PERIPH_BASE + 0x1400U)
+#define TIM12_BASE (APB1PERIPH_BASE + 0x1800U)
+#define TIM13_BASE (APB1PERIPH_BASE + 0x1C00U)
+#define TIM14_BASE (APB1PERIPH_BASE + 0x2000U)
+#define RTC_BASE (APB1PERIPH_BASE + 0x2800U)
+#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00U)
+#define IWDG_BASE (APB1PERIPH_BASE + 0x3000U)
+#define I2S2ext_BASE (APB1PERIPH_BASE + 0x3400U)
+#define SPI2_BASE (APB1PERIPH_BASE + 0x3800U)
+#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00U)
+#define I2S3ext_BASE (APB1PERIPH_BASE + 0x4000U)
+#define USART2_BASE (APB1PERIPH_BASE + 0x4400U)
+#define USART3_BASE (APB1PERIPH_BASE + 0x4800U)
+#define UART4_BASE (APB1PERIPH_BASE + 0x4C00U)
+#define UART5_BASE (APB1PERIPH_BASE + 0x5000U)
+#define I2C1_BASE (APB1PERIPH_BASE + 0x5400U)
+#define I2C2_BASE (APB1PERIPH_BASE + 0x5800U)
+#define I2C3_BASE (APB1PERIPH_BASE + 0x5C00U)
+#define CAN1_BASE (APB1PERIPH_BASE + 0x6400U)
+#define CAN2_BASE (APB1PERIPH_BASE + 0x6800U)
+#define PWR_BASE (APB1PERIPH_BASE + 0x7000U)
+#define DAC_BASE (APB1PERIPH_BASE + 0x7400U)
+
+/*!< APB2 peripherals */
+#define TIM1_BASE (APB2PERIPH_BASE + 0x0000U)
+#define TIM8_BASE (APB2PERIPH_BASE + 0x0400U)
+#define USART1_BASE (APB2PERIPH_BASE + 0x1000U)
+#define USART6_BASE (APB2PERIPH_BASE + 0x1400U)
+#define ADC1_BASE (APB2PERIPH_BASE + 0x2000U)
+#define ADC2_BASE (APB2PERIPH_BASE + 0x2100U)
+#define ADC3_BASE (APB2PERIPH_BASE + 0x2200U)
+#define ADC_BASE (APB2PERIPH_BASE + 0x2300U)
+#define SDIO_BASE (APB2PERIPH_BASE + 0x2C00U)
+#define SPI1_BASE (APB2PERIPH_BASE + 0x3000U)
+#define SYSCFG_BASE (APB2PERIPH_BASE + 0x3800U)
+#define EXTI_BASE (APB2PERIPH_BASE + 0x3C00U)
+#define TIM9_BASE (APB2PERIPH_BASE + 0x4000U)
+#define TIM10_BASE (APB2PERIPH_BASE + 0x4400U)
+#define TIM11_BASE (APB2PERIPH_BASE + 0x4800U)
+
+/*!< AHB1 peripherals */
+#define GPIOA_BASE (AHB1PERIPH_BASE + 0x0000U)
+#define GPIOB_BASE (AHB1PERIPH_BASE + 0x0400U)
+#define GPIOC_BASE (AHB1PERIPH_BASE + 0x0800U)
+#define GPIOD_BASE (AHB1PERIPH_BASE + 0x0C00U)
+#define GPIOE_BASE (AHB1PERIPH_BASE + 0x1000U)
+#define GPIOF_BASE (AHB1PERIPH_BASE + 0x1400U)
+#define GPIOG_BASE (AHB1PERIPH_BASE + 0x1800U)
+#define GPIOH_BASE (AHB1PERIPH_BASE + 0x1C00U)
+#define GPIOI_BASE (AHB1PERIPH_BASE + 0x2000U)
+#define CRC_BASE (AHB1PERIPH_BASE + 0x3000U)
+#define RCC_BASE (AHB1PERIPH_BASE + 0x3800U)
+#define FLASH_R_BASE (AHB1PERIPH_BASE + 0x3C00U)
+#define DMA1_BASE (AHB1PERIPH_BASE + 0x6000U)
+#define DMA1_Stream0_BASE (DMA1_BASE + 0x010U)
+#define DMA1_Stream1_BASE (DMA1_BASE + 0x028U)
+#define DMA1_Stream2_BASE (DMA1_BASE + 0x040U)
+#define DMA1_Stream3_BASE (DMA1_BASE + 0x058U)
+#define DMA1_Stream4_BASE (DMA1_BASE + 0x070U)
+#define DMA1_Stream5_BASE (DMA1_BASE + 0x088U)
+#define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0U)
+#define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8U)
+#define DMA2_BASE (AHB1PERIPH_BASE + 0x6400U)
+#define DMA2_Stream0_BASE (DMA2_BASE + 0x010U)
+#define DMA2_Stream1_BASE (DMA2_BASE + 0x028U)
+#define DMA2_Stream2_BASE (DMA2_BASE + 0x040U)
+#define DMA2_Stream3_BASE (DMA2_BASE + 0x058U)
+#define DMA2_Stream4_BASE (DMA2_BASE + 0x070U)
+#define DMA2_Stream5_BASE (DMA2_BASE + 0x088U)
+#define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0U)
+#define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8U)
+
+/*!< AHB2 peripherals */
+#define RNG_BASE (AHB2PERIPH_BASE + 0x60800U)
+
+/*!< FSMC Bankx registers base address */
+#define FSMC_Bank1_R_BASE (FSMC_R_BASE + 0x0000U)
+#define FSMC_Bank1E_R_BASE (FSMC_R_BASE + 0x0104U)
+#define FSMC_Bank2_3_R_BASE (FSMC_R_BASE + 0x0060U)
+#define FSMC_Bank4_R_BASE (FSMC_R_BASE + 0x00A0U)
+
+/* Debug MCU registers base address */
+#define DBGMCU_BASE 0xE0042000U
+
+/*!< USB registers base address */
+#define USB_OTG_HS_PERIPH_BASE 0x40040000U
+#define USB_OTG_FS_PERIPH_BASE 0x50000000U
+
+#define USB_OTG_GLOBAL_BASE 0x000U
+#define USB_OTG_DEVICE_BASE 0x800U
+#define USB_OTG_IN_ENDPOINT_BASE 0x900U
+#define USB_OTG_OUT_ENDPOINT_BASE 0xB00U
+#define USB_OTG_EP_REG_SIZE 0x20U
+#define USB_OTG_HOST_BASE 0x400U
+#define USB_OTG_HOST_PORT_BASE 0x440U
+#define USB_OTG_HOST_CHANNEL_BASE 0x500U
+#define USB_OTG_HOST_CHANNEL_SIZE 0x20U
+#define USB_OTG_PCGCCTL_BASE 0xE00U
+#define USB_OTG_FIFO_BASE 0x1000U
+#define USB_OTG_FIFO_SIZE 0x1000U
+
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_declaration
+ * @{
+ */
+#define TIM2 ((TIM_TypeDef *) TIM2_BASE)
+#define TIM3 ((TIM_TypeDef *) TIM3_BASE)
+#define TIM4 ((TIM_TypeDef *) TIM4_BASE)
+#define TIM5 ((TIM_TypeDef *) TIM5_BASE)
+#define TIM6 ((TIM_TypeDef *) TIM6_BASE)
+#define TIM7 ((TIM_TypeDef *) TIM7_BASE)
+#define TIM12 ((TIM_TypeDef *) TIM12_BASE)
+#define TIM13 ((TIM_TypeDef *) TIM13_BASE)
+#define TIM14 ((TIM_TypeDef *) TIM14_BASE)
+#define RTC ((RTC_TypeDef *) RTC_BASE)
+#define WWDG ((WWDG_TypeDef *) WWDG_BASE)
+#define IWDG ((IWDG_TypeDef *) IWDG_BASE)
+#define I2S2ext ((SPI_TypeDef *) I2S2ext_BASE)
+#define SPI2 ((SPI_TypeDef *) SPI2_BASE)
+#define SPI3 ((SPI_TypeDef *) SPI3_BASE)
+#define I2S3ext ((SPI_TypeDef *) I2S3ext_BASE)
+#define USART2 ((USART_TypeDef *) USART2_BASE)
+#define USART3 ((USART_TypeDef *) USART3_BASE)
+#define UART4 ((USART_TypeDef *) UART4_BASE)
+#define UART5 ((USART_TypeDef *) UART5_BASE)
+#define I2C1 ((I2C_TypeDef *) I2C1_BASE)
+#define I2C2 ((I2C_TypeDef *) I2C2_BASE)
+#define I2C3 ((I2C_TypeDef *) I2C3_BASE)
+#define CAN1 ((CAN_TypeDef *) CAN1_BASE)
+#define CAN2 ((CAN_TypeDef *) CAN2_BASE)
+#define PWR ((PWR_TypeDef *) PWR_BASE)
+#define DAC ((DAC_TypeDef *) DAC_BASE)
+#define TIM1 ((TIM_TypeDef *) TIM1_BASE)
+#define TIM8 ((TIM_TypeDef *) TIM8_BASE)
+#define USART1 ((USART_TypeDef *) USART1_BASE)
+#define USART6 ((USART_TypeDef *) USART6_BASE)
+#define ADC ((ADC_Common_TypeDef *) ADC_BASE)
+#define ADC1 ((ADC_TypeDef *) ADC1_BASE)
+#define ADC2 ((ADC_TypeDef *) ADC2_BASE)
+#define ADC3 ((ADC_TypeDef *) ADC3_BASE)
+#define SDIO ((SDIO_TypeDef *) SDIO_BASE)
+#define SPI1 ((SPI_TypeDef *) SPI1_BASE)
+#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
+#define EXTI ((EXTI_TypeDef *) EXTI_BASE)
+#define TIM9 ((TIM_TypeDef *) TIM9_BASE)
+#define TIM10 ((TIM_TypeDef *) TIM10_BASE)
+#define TIM11 ((TIM_TypeDef *) TIM11_BASE)
+#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
+#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
+#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
+#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
+#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
+#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
+#define GPIOG ((GPIO_TypeDef *) GPIOG_BASE)
+#define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
+#define GPIOI ((GPIO_TypeDef *) GPIOI_BASE)
+#define CRC ((CRC_TypeDef *) CRC_BASE)
+#define RCC ((RCC_TypeDef *) RCC_BASE)
+#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
+#define DMA1 ((DMA_TypeDef *) DMA1_BASE)
+#define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)
+#define DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)
+#define DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)
+#define DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)
+#define DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)
+#define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)
+#define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)
+#define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)
+#define DMA2 ((DMA_TypeDef *) DMA2_BASE)
+#define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)
+#define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
+#define DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)
+#define DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)
+#define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)
+#define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)
+#define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)
+#define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)
+#define RNG ((RNG_TypeDef *) RNG_BASE)
+#define FSMC_Bank1 ((FSMC_Bank1_TypeDef *) FSMC_Bank1_R_BASE)
+#define FSMC_Bank1E ((FSMC_Bank1E_TypeDef *) FSMC_Bank1E_R_BASE)
+#define FSMC_Bank2_3 ((FSMC_Bank2_3_TypeDef *) FSMC_Bank2_3_R_BASE)
+#define FSMC_Bank4 ((FSMC_Bank4_TypeDef *) FSMC_Bank4_R_BASE)
+
+#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
+
+#define USB_OTG_FS ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE)
+#define USB_OTG_HS ((USB_OTG_GlobalTypeDef *) USB_OTG_HS_PERIPH_BASE)
+
+/**
+ * @}
+ */
+
+/** @addtogroup Exported_constants
+ * @{
+ */
+
+ /** @addtogroup Peripheral_Registers_Bits_Definition
+ * @{
+ */
+
+/******************************************************************************/
+/* Peripheral Registers_Bits_Definition */
+/******************************************************************************/
+
+/******************************************************************************/
+/* */
+/* Analog to Digital Converter */
+/* */
+/******************************************************************************/
+/******************** Bit definition for ADC_SR register ********************/
+#define ADC_SR_AWD 0x00000001U /*!<Analog watchdog flag */
+#define ADC_SR_EOC 0x00000002U /*!<End of conversion */
+#define ADC_SR_JEOC 0x00000004U /*!<Injected channel end of conversion */
+#define ADC_SR_JSTRT 0x00000008U /*!<Injected channel Start flag */
+#define ADC_SR_STRT 0x00000010U /*!<Regular channel Start flag */
+#define ADC_SR_OVR 0x00000020U /*!<Overrun flag */
+
+/******************* Bit definition for ADC_CR1 register ********************/
+#define ADC_CR1_AWDCH 0x0000001FU /*!<AWDCH[4:0] bits (Analog watchdog channel select bits) */
+#define ADC_CR1_AWDCH_0 0x00000001U /*!<Bit 0 */
+#define ADC_CR1_AWDCH_1 0x00000002U /*!<Bit 1 */
+#define ADC_CR1_AWDCH_2 0x00000004U /*!<Bit 2 */
+#define ADC_CR1_AWDCH_3 0x00000008U /*!<Bit 3 */
+#define ADC_CR1_AWDCH_4 0x00000010U /*!<Bit 4 */
+#define ADC_CR1_EOCIE 0x00000020U /*!<Interrupt enable for EOC */
+#define ADC_CR1_AWDIE 0x00000040U /*!<AAnalog Watchdog interrupt enable */
+#define ADC_CR1_JEOCIE 0x00000080U /*!<Interrupt enable for injected channels */
+#define ADC_CR1_SCAN 0x00000100U /*!<Scan mode */
+#define ADC_CR1_AWDSGL 0x00000200U /*!<Enable the watchdog on a single channel in scan mode */
+#define ADC_CR1_JAUTO 0x00000400U /*!<Automatic injected group conversion */
+#define ADC_CR1_DISCEN 0x00000800U /*!<Discontinuous mode on regular channels */
+#define ADC_CR1_JDISCEN 0x00001000U /*!<Discontinuous mode on injected channels */
+#define ADC_CR1_DISCNUM 0x0000E000U /*!<DISCNUM[2:0] bits (Discontinuous mode channel count) */
+#define ADC_CR1_DISCNUM_0 0x00002000U /*!<Bit 0 */
+#define ADC_CR1_DISCNUM_1 0x00004000U /*!<Bit 1 */
+#define ADC_CR1_DISCNUM_2 0x00008000U /*!<Bit 2 */
+#define ADC_CR1_JAWDEN 0x00400000U /*!<Analog watchdog enable on injected channels */
+#define ADC_CR1_AWDEN 0x00800000U /*!<Analog watchdog enable on regular channels */
+#define ADC_CR1_RES 0x03000000U /*!<RES[2:0] bits (Resolution) */
+#define ADC_CR1_RES_0 0x01000000U /*!<Bit 0 */
+#define ADC_CR1_RES_1 0x02000000U /*!<Bit 1 */
+#define ADC_CR1_OVRIE 0x04000000U /*!<overrun interrupt enable */
+
+/******************* Bit definition for ADC_CR2 register ********************/
+#define ADC_CR2_ADON 0x00000001U /*!<A/D Converter ON / OFF */
+#define ADC_CR2_CONT 0x00000002U /*!<Continuous Conversion */
+#define ADC_CR2_DMA 0x00000100U /*!<Direct Memory access mode */
+#define ADC_CR2_DDS 0x00000200U /*!<DMA disable selection (Single ADC) */
+#define ADC_CR2_EOCS 0x00000400U /*!<End of conversion selection */
+#define ADC_CR2_ALIGN 0x00000800U /*!<Data Alignment */
+#define ADC_CR2_JEXTSEL 0x000F0000U /*!<JEXTSEL[3:0] bits (External event select for injected group) */
+#define ADC_CR2_JEXTSEL_0 0x00010000U /*!<Bit 0 */
+#define ADC_CR2_JEXTSEL_1 0x00020000U /*!<Bit 1 */
+#define ADC_CR2_JEXTSEL_2 0x00040000U /*!<Bit 2 */
+#define ADC_CR2_JEXTSEL_3 0x00080000U /*!<Bit 3 */
+#define ADC_CR2_JEXTEN 0x00300000U /*!<JEXTEN[1:0] bits (External Trigger Conversion mode for injected channelsp) */
+#define ADC_CR2_JEXTEN_0 0x00100000U /*!<Bit 0 */
+#define ADC_CR2_JEXTEN_1 0x00200000U /*!<Bit 1 */
+#define ADC_CR2_JSWSTART 0x00400000U /*!<Start Conversion of injected channels */
+#define ADC_CR2_EXTSEL 0x0F000000U /*!<EXTSEL[3:0] bits (External Event Select for regular group) */
+#define ADC_CR2_EXTSEL_0 0x01000000U /*!<Bit 0 */
+#define ADC_CR2_EXTSEL_1 0x02000000U /*!<Bit 1 */
+#define ADC_CR2_EXTSEL_2 0x04000000U /*!<Bit 2 */
+#define ADC_CR2_EXTSEL_3 0x08000000U /*!<Bit 3 */
+#define ADC_CR2_EXTEN 0x30000000U /*!<EXTEN[1:0] bits (External Trigger Conversion mode for regular channelsp) */
+#define ADC_CR2_EXTEN_0 0x10000000U /*!<Bit 0 */
+#define ADC_CR2_EXTEN_1 0x20000000U /*!<Bit 1 */
+#define ADC_CR2_SWSTART 0x40000000U /*!<Start Conversion of regular channels */
+
+/****************** Bit definition for ADC_SMPR1 register *******************/
+#define ADC_SMPR1_SMP10 0x00000007U /*!<SMP10[2:0] bits (Channel 10 Sample time selection) */
+#define ADC_SMPR1_SMP10_0 0x00000001U /*!<Bit 0 */
+#define ADC_SMPR1_SMP10_1 0x00000002U /*!<Bit 1 */
+#define ADC_SMPR1_SMP10_2 0x00000004U /*!<Bit 2 */
+#define ADC_SMPR1_SMP11 0x00000038U /*!<SMP11[2:0] bits (Channel 11 Sample time selection) */
+#define ADC_SMPR1_SMP11_0 0x00000008U /*!<Bit 0 */
+#define ADC_SMPR1_SMP11_1 0x00000010U /*!<Bit 1 */
+#define ADC_SMPR1_SMP11_2 0x00000020U /*!<Bit 2 */
+#define ADC_SMPR1_SMP12 0x000001C0U /*!<SMP12[2:0] bits (Channel 12 Sample time selection) */
+#define ADC_SMPR1_SMP12_0 0x00000040U /*!<Bit 0 */
+#define ADC_SMPR1_SMP12_1 0x00000080U /*!<Bit 1 */
+#define ADC_SMPR1_SMP12_2 0x00000100U /*!<Bit 2 */
+#define ADC_SMPR1_SMP13 0x00000E00U /*!<SMP13[2:0] bits (Channel 13 Sample time selection) */
+#define ADC_SMPR1_SMP13_0 0x00000200U /*!<Bit 0 */
+#define ADC_SMPR1_SMP13_1 0x00000400U /*!<Bit 1 */
+#define ADC_SMPR1_SMP13_2 0x00000800U /*!<Bit 2 */
+#define ADC_SMPR1_SMP14 0x00007000U /*!<SMP14[2:0] bits (Channel 14 Sample time selection) */
+#define ADC_SMPR1_SMP14_0 0x00001000U /*!<Bit 0 */
+#define ADC_SMPR1_SMP14_1 0x00002000U /*!<Bit 1 */
+#define ADC_SMPR1_SMP14_2 0x00004000U /*!<Bit 2 */
+#define ADC_SMPR1_SMP15 0x00038000U /*!<SMP15[2:0] bits (Channel 15 Sample time selection) */
+#define ADC_SMPR1_SMP15_0 0x00008000U /*!<Bit 0 */
+#define ADC_SMPR1_SMP15_1 0x00010000U /*!<Bit 1 */
+#define ADC_SMPR1_SMP15_2 0x00020000U /*!<Bit 2 */
+#define ADC_SMPR1_SMP16 0x001C0000U /*!<SMP16[2:0] bits (Channel 16 Sample time selection) */
+#define ADC_SMPR1_SMP16_0 0x00040000U /*!<Bit 0 */
+#define ADC_SMPR1_SMP16_1 0x00080000U /*!<Bit 1 */
+#define ADC_SMPR1_SMP16_2 0x00100000U /*!<Bit 2 */
+#define ADC_SMPR1_SMP17 0x00E00000U /*!<SMP17[2:0] bits (Channel 17 Sample time selection) */
+#define ADC_SMPR1_SMP17_0 0x00200000U /*!<Bit 0 */
+#define ADC_SMPR1_SMP17_1 0x00400000U /*!<Bit 1 */
+#define ADC_SMPR1_SMP17_2 0x00800000U /*!<Bit 2 */
+#define ADC_SMPR1_SMP18 0x07000000U /*!<SMP18[2:0] bits (Channel 18 Sample time selection) */
+#define ADC_SMPR1_SMP18_0 0x01000000U /*!<Bit 0 */
+#define ADC_SMPR1_SMP18_1 0x02000000U /*!<Bit 1 */
+#define ADC_SMPR1_SMP18_2 0x04000000U /*!<Bit 2 */
+
+/****************** Bit definition for ADC_SMPR2 register *******************/
+#define ADC_SMPR2_SMP0 0x00000007U /*!<SMP0[2:0] bits (Channel 0 Sample time selection) */
+#define ADC_SMPR2_SMP0_0 0x00000001U /*!<Bit 0 */
+#define ADC_SMPR2_SMP0_1 0x00000002U /*!<Bit 1 */
+#define ADC_SMPR2_SMP0_2 0x00000004U /*!<Bit 2 */
+#define ADC_SMPR2_SMP1 0x00000038U /*!<SMP1[2:0] bits (Channel 1 Sample time selection) */
+#define ADC_SMPR2_SMP1_0 0x00000008U /*!<Bit 0 */
+#define ADC_SMPR2_SMP1_1 0x00000010U /*!<Bit 1 */
+#define ADC_SMPR2_SMP1_2 0x00000020U /*!<Bit 2 */
+#define ADC_SMPR2_SMP2 0x000001C0U /*!<SMP2[2:0] bits (Channel 2 Sample time selection) */
+#define ADC_SMPR2_SMP2_0 0x00000040U /*!<Bit 0 */
+#define ADC_SMPR2_SMP2_1 0x00000080U /*!<Bit 1 */
+#define ADC_SMPR2_SMP2_2 0x00000100U /*!<Bit 2 */
+#define ADC_SMPR2_SMP3 0x00000E00U /*!<SMP3[2:0] bits (Channel 3 Sample time selection) */
+#define ADC_SMPR2_SMP3_0 0x00000200U /*!<Bit 0 */
+#define ADC_SMPR2_SMP3_1 0x00000400U /*!<Bit 1 */
+#define ADC_SMPR2_SMP3_2 0x00000800U /*!<Bit 2 */
+#define ADC_SMPR2_SMP4 0x00007000U /*!<SMP4[2:0] bits (Channel 4 Sample time selection) */
+#define ADC_SMPR2_SMP4_0 0x00001000U /*!<Bit 0 */
+#define ADC_SMPR2_SMP4_1 0x00002000U /*!<Bit 1 */
+#define ADC_SMPR2_SMP4_2 0x00004000U /*!<Bit 2 */
+#define ADC_SMPR2_SMP5 0x00038000U /*!<SMP5[2:0] bits (Channel 5 Sample time selection) */
+#define ADC_SMPR2_SMP5_0 0x00008000U /*!<Bit 0 */
+#define ADC_SMPR2_SMP5_1 0x00010000U /*!<Bit 1 */
+#define ADC_SMPR2_SMP5_2 0x00020000U /*!<Bit 2 */
+#define ADC_SMPR2_SMP6 0x001C0000U /*!<SMP6[2:0] bits (Channel 6 Sample time selection) */
+#define ADC_SMPR2_SMP6_0 0x00040000U /*!<Bit 0 */
+#define ADC_SMPR2_SMP6_1 0x00080000U /*!<Bit 1 */
+#define ADC_SMPR2_SMP6_2 0x00100000U /*!<Bit 2 */
+#define ADC_SMPR2_SMP7 0x00E00000U /*!<SMP7[2:0] bits (Channel 7 Sample time selection) */
+#define ADC_SMPR2_SMP7_0 0x00200000U /*!<Bit 0 */
+#define ADC_SMPR2_SMP7_1 0x00400000U /*!<Bit 1 */
+#define ADC_SMPR2_SMP7_2 0x00800000U /*!<Bit 2 */
+#define ADC_SMPR2_SMP8 0x07000000U /*!<SMP8[2:0] bits (Channel 8 Sample time selection) */
+#define ADC_SMPR2_SMP8_0 0x01000000U /*!<Bit 0 */
+#define ADC_SMPR2_SMP8_1 0x02000000U /*!<Bit 1 */
+#define ADC_SMPR2_SMP8_2 0x04000000U /*!<Bit 2 */
+#define ADC_SMPR2_SMP9 0x38000000U /*!<SMP9[2:0] bits (Channel 9 Sample time selection) */
+#define ADC_SMPR2_SMP9_0 0x08000000U /*!<Bit 0 */
+#define ADC_SMPR2_SMP9_1 0x10000000U /*!<Bit 1 */
+#define ADC_SMPR2_SMP9_2 0x20000000U /*!<Bit 2 */
+
+/****************** Bit definition for ADC_JOFR1 register *******************/
+#define ADC_JOFR1_JOFFSET1 0x0FFFU /*!<Data offset for injected channel 1 */
+
+/****************** Bit definition for ADC_JOFR2 register *******************/
+#define ADC_JOFR2_JOFFSET2 0x0FFFU /*!<Data offset for injected channel 2 */
+
+/****************** Bit definition for ADC_JOFR3 register *******************/
+#define ADC_JOFR3_JOFFSET3 0x0FFFU /*!<Data offset for injected channel 3 */
+
+/****************** Bit definition for ADC_JOFR4 register *******************/
+#define ADC_JOFR4_JOFFSET4 0x0FFFU /*!<Data offset for injected channel 4 */
+
+/******************* Bit definition for ADC_HTR register ********************/
+#define ADC_HTR_HT 0x0FFFU /*!<Analog watchdog high threshold */
+
+/******************* Bit definition for ADC_LTR register ********************/
+#define ADC_LTR_LT 0x0FFFU /*!<Analog watchdog low threshold */
+
+/******************* Bit definition for ADC_SQR1 register *******************/
+#define ADC_SQR1_SQ13 0x0000001FU /*!<SQ13[4:0] bits (13th conversion in regular sequence) */
+#define ADC_SQR1_SQ13_0 0x00000001U /*!<Bit 0 */
+#define ADC_SQR1_SQ13_1 0x00000002U /*!<Bit 1 */
+#define ADC_SQR1_SQ13_2 0x00000004U /*!<Bit 2 */
+#define ADC_SQR1_SQ13_3 0x00000008U /*!<Bit 3 */
+#define ADC_SQR1_SQ13_4 0x00000010U /*!<Bit 4 */
+#define ADC_SQR1_SQ14 0x000003E0U /*!<SQ14[4:0] bits (14th conversion in regular sequence) */
+#define ADC_SQR1_SQ14_0 0x00000020U /*!<Bit 0 */
+#define ADC_SQR1_SQ14_1 0x00000040U /*!<Bit 1 */
+#define ADC_SQR1_SQ14_2 0x00000080U /*!<Bit 2 */
+#define ADC_SQR1_SQ14_3 0x00000100U /*!<Bit 3 */
+#define ADC_SQR1_SQ14_4 0x00000200U /*!<Bit 4 */
+#define ADC_SQR1_SQ15 0x00007C00U /*!<SQ15[4:0] bits (15th conversion in regular sequence) */
+#define ADC_SQR1_SQ15_0 0x00000400U /*!<Bit 0 */
+#define ADC_SQR1_SQ15_1 0x00000800U /*!<Bit 1 */
+#define ADC_SQR1_SQ15_2 0x00001000U /*!<Bit 2 */
+#define ADC_SQR1_SQ15_3 0x00002000U /*!<Bit 3 */
+#define ADC_SQR1_SQ15_4 0x00004000U /*!<Bit 4 */
+#define ADC_SQR1_SQ16 0x000F8000U /*!<SQ16[4:0] bits (16th conversion in regular sequence) */
+#define ADC_SQR1_SQ16_0 0x00008000U /*!<Bit 0 */
+#define ADC_SQR1_SQ16_1 0x00010000U /*!<Bit 1 */
+#define ADC_SQR1_SQ16_2 0x00020000U /*!<Bit 2 */
+#define ADC_SQR1_SQ16_3 0x00040000U /*!<Bit 3 */
+#define ADC_SQR1_SQ16_4 0x00080000U /*!<Bit 4 */
+#define ADC_SQR1_L 0x00F00000U /*!<L[3:0] bits (Regular channel sequence length) */
+#define ADC_SQR1_L_0 0x00100000U /*!<Bit 0 */
+#define ADC_SQR1_L_1 0x00200000U /*!<Bit 1 */
+#define ADC_SQR1_L_2 0x00400000U /*!<Bit 2 */
+#define ADC_SQR1_L_3 0x00800000U /*!<Bit 3 */
+
+/******************* Bit definition for ADC_SQR2 register *******************/
+#define ADC_SQR2_SQ7 0x0000001FU /*!<SQ7[4:0] bits (7th conversion in regular sequence) */
+#define ADC_SQR2_SQ7_0 0x00000001U /*!<Bit 0 */
+#define ADC_SQR2_SQ7_1 0x00000002U /*!<Bit 1 */
+#define ADC_SQR2_SQ7_2 0x00000004U /*!<Bit 2 */
+#define ADC_SQR2_SQ7_3 0x00000008U /*!<Bit 3 */
+#define ADC_SQR2_SQ7_4 0x00000010U /*!<Bit 4 */
+#define ADC_SQR2_SQ8 0x000003E0U /*!<SQ8[4:0] bits (8th conversion in regular sequence) */
+#define ADC_SQR2_SQ8_0 0x00000020U /*!<Bit 0 */
+#define ADC_SQR2_SQ8_1 0x00000040U /*!<Bit 1 */
+#define ADC_SQR2_SQ8_2 0x00000080U /*!<Bit 2 */
+#define ADC_SQR2_SQ8_3 0x00000100U /*!<Bit 3 */
+#define ADC_SQR2_SQ8_4 0x00000200U /*!<Bit 4 */
+#define ADC_SQR2_SQ9 0x00007C00U /*!<SQ9[4:0] bits (9th conversion in regular sequence) */
+#define ADC_SQR2_SQ9_0 0x00000400U /*!<Bit 0 */
+#define ADC_SQR2_SQ9_1 0x00000800U /*!<Bit 1 */
+#define ADC_SQR2_SQ9_2 0x00001000U /*!<Bit 2 */
+#define ADC_SQR2_SQ9_3 0x00002000U /*!<Bit 3 */
+#define ADC_SQR2_SQ9_4 0x00004000U /*!<Bit 4 */
+#define ADC_SQR2_SQ10 0x000F8000U /*!<SQ10[4:0] bits (10th conversion in regular sequence) */
+#define ADC_SQR2_SQ10_0 0x00008000U /*!<Bit 0 */
+#define ADC_SQR2_SQ10_1 0x00010000U /*!<Bit 1 */
+#define ADC_SQR2_SQ10_2 0x00020000U /*!<Bit 2 */
+#define ADC_SQR2_SQ10_3 0x00040000U /*!<Bit 3 */
+#define ADC_SQR2_SQ10_4 0x00080000U /*!<Bit 4 */
+#define ADC_SQR2_SQ11 0x01F00000U /*!<SQ11[4:0] bits (11th conversion in regular sequence) */
+#define ADC_SQR2_SQ11_0 0x00100000U /*!<Bit 0 */
+#define ADC_SQR2_SQ11_1 0x00200000U /*!<Bit 1 */
+#define ADC_SQR2_SQ11_2 0x00400000U /*!<Bit 2 */
+#define ADC_SQR2_SQ11_3 0x00800000U /*!<Bit 3 */
+#define ADC_SQR2_SQ11_4 0x01000000U /*!<Bit 4 */
+#define ADC_SQR2_SQ12 0x3E000000U /*!<SQ12[4:0] bits (12th conversion in regular sequence) */
+#define ADC_SQR2_SQ12_0 0x02000000U /*!<Bit 0 */
+#define ADC_SQR2_SQ12_1 0x04000000U /*!<Bit 1 */
+#define ADC_SQR2_SQ12_2 0x08000000U /*!<Bit 2 */
+#define ADC_SQR2_SQ12_3 0x10000000U /*!<Bit 3 */
+#define ADC_SQR2_SQ12_4 0x20000000U /*!<Bit 4 */
+
+/******************* Bit definition for ADC_SQR3 register *******************/
+#define ADC_SQR3_SQ1 0x0000001FU /*!<SQ1[4:0] bits (1st conversion in regular sequence) */
+#define ADC_SQR3_SQ1_0 0x00000001U /*!<Bit 0 */
+#define ADC_SQR3_SQ1_1 0x00000002U /*!<Bit 1 */
+#define ADC_SQR3_SQ1_2 0x00000004U /*!<Bit 2 */
+#define ADC_SQR3_SQ1_3 0x00000008U /*!<Bit 3 */
+#define ADC_SQR3_SQ1_4 0x00000010U /*!<Bit 4 */
+#define ADC_SQR3_SQ2 0x000003E0U /*!<SQ2[4:0] bits (2nd conversion in regular sequence) */
+#define ADC_SQR3_SQ2_0 0x00000020U /*!<Bit 0 */
+#define ADC_SQR3_SQ2_1 0x00000040U /*!<Bit 1 */
+#define ADC_SQR3_SQ2_2 0x00000080U /*!<Bit 2 */
+#define ADC_SQR3_SQ2_3 0x00000100U /*!<Bit 3 */
+#define ADC_SQR3_SQ2_4 0x00000200U /*!<Bit 4 */
+#define ADC_SQR3_SQ3 0x00007C00U /*!<SQ3[4:0] bits (3rd conversion in regular sequence) */
+#define ADC_SQR3_SQ3_0 0x00000400U /*!<Bit 0 */
+#define ADC_SQR3_SQ3_1 0x00000800U /*!<Bit 1 */
+#define ADC_SQR3_SQ3_2 0x00001000U /*!<Bit 2 */
+#define ADC_SQR3_SQ3_3 0x00002000U /*!<Bit 3 */
+#define ADC_SQR3_SQ3_4 0x00004000U /*!<Bit 4 */
+#define ADC_SQR3_SQ4 0x000F8000U /*!<SQ4[4:0] bits (4th conversion in regular sequence) */
+#define ADC_SQR3_SQ4_0 0x00008000U /*!<Bit 0 */
+#define ADC_SQR3_SQ4_1 0x00010000U /*!<Bit 1 */
+#define ADC_SQR3_SQ4_2 0x00020000U /*!<Bit 2 */
+#define ADC_SQR3_SQ4_3 0x00040000U /*!<Bit 3 */
+#define ADC_SQR3_SQ4_4 0x00080000U /*!<Bit 4 */
+#define ADC_SQR3_SQ5 0x01F00000U /*!<SQ5[4:0] bits (5th conversion in regular sequence) */
+#define ADC_SQR3_SQ5_0 0x00100000U /*!<Bit 0 */
+#define ADC_SQR3_SQ5_1 0x00200000U /*!<Bit 1 */
+#define ADC_SQR3_SQ5_2 0x00400000U /*!<Bit 2 */
+#define ADC_SQR3_SQ5_3 0x00800000U /*!<Bit 3 */
+#define ADC_SQR3_SQ5_4 0x01000000U /*!<Bit 4 */
+#define ADC_SQR3_SQ6 0x3E000000U /*!<SQ6[4:0] bits (6th conversion in regular sequence) */
+#define ADC_SQR3_SQ6_0 0x02000000U /*!<Bit 0 */
+#define ADC_SQR3_SQ6_1 0x04000000U /*!<Bit 1 */
+#define ADC_SQR3_SQ6_2 0x08000000U /*!<Bit 2 */
+#define ADC_SQR3_SQ6_3 0x10000000U /*!<Bit 3 */
+#define ADC_SQR3_SQ6_4 0x20000000U /*!<Bit 4 */
+
+/******************* Bit definition for ADC_JSQR register *******************/
+#define ADC_JSQR_JSQ1 0x0000001FU /*!<JSQ1[4:0] bits (1st conversion in injected sequence) */
+#define ADC_JSQR_JSQ1_0 0x00000001U /*!<Bit 0 */
+#define ADC_JSQR_JSQ1_1 0x00000002U /*!<Bit 1 */
+#define ADC_JSQR_JSQ1_2 0x00000004U /*!<Bit 2 */
+#define ADC_JSQR_JSQ1_3 0x00000008U /*!<Bit 3 */
+#define ADC_JSQR_JSQ1_4 0x00000010U /*!<Bit 4 */
+#define ADC_JSQR_JSQ2 0x000003E0U /*!<JSQ2[4:0] bits (2nd conversion in injected sequence) */
+#define ADC_JSQR_JSQ2_0 0x00000020U /*!<Bit 0 */
+#define ADC_JSQR_JSQ2_1 0x00000040U /*!<Bit 1 */
+#define ADC_JSQR_JSQ2_2 0x00000080U /*!<Bit 2 */
+#define ADC_JSQR_JSQ2_3 0x00000100U /*!<Bit 3 */
+#define ADC_JSQR_JSQ2_4 0x00000200U /*!<Bit 4 */
+#define ADC_JSQR_JSQ3 0x00007C00U /*!<JSQ3[4:0] bits (3rd conversion in injected sequence) */
+#define ADC_JSQR_JSQ3_0 0x00000400U /*!<Bit 0 */
+#define ADC_JSQR_JSQ3_1 0x00000800U /*!<Bit 1 */
+#define ADC_JSQR_JSQ3_2 0x00001000U /*!<Bit 2 */
+#define ADC_JSQR_JSQ3_3 0x00002000U /*!<Bit 3 */
+#define ADC_JSQR_JSQ3_4 0x00004000U /*!<Bit 4 */
+#define ADC_JSQR_JSQ4 0x000F8000U /*!<JSQ4[4:0] bits (4th conversion in injected sequence) */
+#define ADC_JSQR_JSQ4_0 0x00008000U /*!<Bit 0 */
+#define ADC_JSQR_JSQ4_1 0x00010000U /*!<Bit 1 */
+#define ADC_JSQR_JSQ4_2 0x00020000U /*!<Bit 2 */
+#define ADC_JSQR_JSQ4_3 0x00040000U /*!<Bit 3 */
+#define ADC_JSQR_JSQ4_4 0x00080000U /*!<Bit 4 */
+#define ADC_JSQR_JL 0x00300000U /*!<JL[1:0] bits (Injected Sequence length) */
+#define ADC_JSQR_JL_0 0x00100000U /*!<Bit 0 */
+#define ADC_JSQR_JL_1 0x00200000U /*!<Bit 1 */
+
+/******************* Bit definition for ADC_JDR1 register *******************/
+#define ADC_JDR1_JDATA 0xFFFFU /*!<Injected data */
+
+/******************* Bit definition for ADC_JDR2 register *******************/
+#define ADC_JDR2_JDATA 0xFFFFU /*!<Injected data */
+
+/******************* Bit definition for ADC_JDR3 register *******************/
+#define ADC_JDR3_JDATA 0xFFFFU /*!<Injected data */
+
+/******************* Bit definition for ADC_JDR4 register *******************/
+#define ADC_JDR4_JDATA 0xFFFFU /*!<Injected data */
+
+/******************** Bit definition for ADC_DR register ********************/
+#define ADC_DR_DATA 0x0000FFFFU /*!<Regular data */
+#define ADC_DR_ADC2DATA 0xFFFF0000U /*!<ADC2 data */
+
+/******************* Bit definition for ADC_CSR register ********************/
+#define ADC_CSR_AWD1 0x00000001U /*!<ADC1 Analog watchdog flag */
+#define ADC_CSR_EOC1 0x00000002U /*!<ADC1 End of conversion */
+#define ADC_CSR_JEOC1 0x00000004U /*!<ADC1 Injected channel end of conversion */
+#define ADC_CSR_JSTRT1 0x00000008U /*!<ADC1 Injected channel Start flag */
+#define ADC_CSR_STRT1 0x00000010U /*!<ADC1 Regular channel Start flag */
+#define ADC_CSR_OVR1 0x00000020U /*!<ADC1 DMA overrun flag */
+#define ADC_CSR_AWD2 0x00000100U /*!<ADC2 Analog watchdog flag */
+#define ADC_CSR_EOC2 0x00000200U /*!<ADC2 End of conversion */
+#define ADC_CSR_JEOC2 0x00000400U /*!<ADC2 Injected channel end of conversion */
+#define ADC_CSR_JSTRT2 0x00000800U /*!<ADC2 Injected channel Start flag */
+#define ADC_CSR_STRT2 0x00001000U /*!<ADC2 Regular channel Start flag */
+#define ADC_CSR_OVR2 0x00002000U /*!<ADC2 DMA overrun flag */
+#define ADC_CSR_AWD3 0x00010000U /*!<ADC3 Analog watchdog flag */
+#define ADC_CSR_EOC3 0x00020000U /*!<ADC3 End of conversion */
+#define ADC_CSR_JEOC3 0x00040000U /*!<ADC3 Injected channel end of conversion */
+#define ADC_CSR_JSTRT3 0x00080000U /*!<ADC3 Injected channel Start flag */
+#define ADC_CSR_STRT3 0x00100000U /*!<ADC3 Regular channel Start flag */
+#define ADC_CSR_OVR3 0x00200000U /*!<ADC3 DMA overrun flag */
+
+/* Legacy defines */
+#define ADC_CSR_DOVR1 ADC_CSR_OVR1
+#define ADC_CSR_DOVR2 ADC_CSR_OVR2
+#define ADC_CSR_DOVR3 ADC_CSR_OVR3
+
+/******************* Bit definition for ADC_CCR register ********************/
+#define ADC_CCR_MULTI 0x0000001FU /*!<MULTI[4:0] bits (Multi-ADC mode selection) */
+#define ADC_CCR_MULTI_0 0x00000001U /*!<Bit 0 */
+#define ADC_CCR_MULTI_1 0x00000002U /*!<Bit 1 */
+#define ADC_CCR_MULTI_2 0x00000004U /*!<Bit 2 */
+#define ADC_CCR_MULTI_3 0x00000008U /*!<Bit 3 */
+#define ADC_CCR_MULTI_4 0x00000010U /*!<Bit 4 */
+#define ADC_CCR_DELAY 0x00000F00U /*!<DELAY[3:0] bits (Delay between 2 sampling phases) */
+#define ADC_CCR_DELAY_0 0x00000100U /*!<Bit 0 */
+#define ADC_CCR_DELAY_1 0x00000200U /*!<Bit 1 */
+#define ADC_CCR_DELAY_2 0x00000400U /*!<Bit 2 */
+#define ADC_CCR_DELAY_3 0x00000800U /*!<Bit 3 */
+#define ADC_CCR_DDS 0x00002000U /*!<DMA disable selection (Multi-ADC mode) */
+#define ADC_CCR_DMA 0x0000C000U /*!<DMA[1:0] bits (Direct Memory Access mode for multimode) */
+#define ADC_CCR_DMA_0 0x00004000U /*!<Bit 0 */
+#define ADC_CCR_DMA_1 0x00008000U /*!<Bit 1 */
+#define ADC_CCR_ADCPRE 0x00030000U /*!<ADCPRE[1:0] bits (ADC prescaler) */
+#define ADC_CCR_ADCPRE_0 0x00010000U /*!<Bit 0 */
+#define ADC_CCR_ADCPRE_1 0x00020000U /*!<Bit 1 */
+#define ADC_CCR_VBATE 0x00400000U /*!<VBAT Enable */
+#define ADC_CCR_TSVREFE 0x00800000U /*!<Temperature Sensor and VREFINT Enable */
+
+/******************* Bit definition for ADC_CDR register ********************/
+#define ADC_CDR_DATA1 0x0000FFFFU /*!<1st data of a pair of regular conversions */
+#define ADC_CDR_DATA2 0xFFFF0000U /*!<2nd data of a pair of regular conversions */
+
+/******************************************************************************/
+/* */
+/* Controller Area Network */
+/* */
+/******************************************************************************/
+/*!<CAN control and status registers */
+/******************* Bit definition for CAN_MCR register ********************/
+#define CAN_MCR_INRQ 0x00000001U /*!<Initialization Request */
+#define CAN_MCR_SLEEP 0x00000002U /*!<Sleep Mode Request */
+#define CAN_MCR_TXFP 0x00000004U /*!<Transmit FIFO Priority */
+#define CAN_MCR_RFLM 0x00000008U /*!<Receive FIFO Locked Mode */
+#define CAN_MCR_NART 0x00000010U /*!<No Automatic Retransmission */
+#define CAN_MCR_AWUM 0x00000020U /*!<Automatic Wakeup Mode */
+#define CAN_MCR_ABOM 0x00000040U /*!<Automatic Bus-Off Management */
+#define CAN_MCR_TTCM 0x00000080U /*!<Time Triggered Communication Mode */
+#define CAN_MCR_RESET 0x00008000U /*!<bxCAN software master reset */
+#define CAN_MCR_DBF 0x00010000U /*!<bxCAN Debug freeze */
+/******************* Bit definition for CAN_MSR register ********************/
+#define CAN_MSR_INAK 0x0001U /*!<Initialization Acknowledge */
+#define CAN_MSR_SLAK 0x0002U /*!<Sleep Acknowledge */
+#define CAN_MSR_ERRI 0x0004U /*!<Error Interrupt */
+#define CAN_MSR_WKUI 0x0008U /*!<Wakeup Interrupt */
+#define CAN_MSR_SLAKI 0x0010U /*!<Sleep Acknowledge Interrupt */
+#define CAN_MSR_TXM 0x0100U /*!<Transmit Mode */
+#define CAN_MSR_RXM 0x0200U /*!<Receive Mode */
+#define CAN_MSR_SAMP 0x0400U /*!<Last Sample Point */
+#define CAN_MSR_RX 0x0800U /*!<CAN Rx Signal */
+
+/******************* Bit definition for CAN_TSR register ********************/
+#define CAN_TSR_RQCP0 0x00000001U /*!<Request Completed Mailbox0 */
+#define CAN_TSR_TXOK0 0x00000002U /*!<Transmission OK of Mailbox0 */
+#define CAN_TSR_ALST0 0x00000004U /*!<Arbitration Lost for Mailbox0 */
+#define CAN_TSR_TERR0 0x00000008U /*!<Transmission Error of Mailbox0 */
+#define CAN_TSR_ABRQ0 0x00000080U /*!<Abort Request for Mailbox0 */
+#define CAN_TSR_RQCP1 0x00000100U /*!<Request Completed Mailbox1 */
+#define CAN_TSR_TXOK1 0x00000200U /*!<Transmission OK of Mailbox1 */
+#define CAN_TSR_ALST1 0x00000400U /*!<Arbitration Lost for Mailbox1 */
+#define CAN_TSR_TERR1 0x00000800U /*!<Transmission Error of Mailbox1 */
+#define CAN_TSR_ABRQ1 0x00008000U /*!<Abort Request for Mailbox 1 */
+#define CAN_TSR_RQCP2 0x00010000U /*!<Request Completed Mailbox2 */
+#define CAN_TSR_TXOK2 0x00020000U /*!<Transmission OK of Mailbox 2 */
+#define CAN_TSR_ALST2 0x00040000U /*!<Arbitration Lost for mailbox 2 */
+#define CAN_TSR_TERR2 0x00080000U /*!<Transmission Error of Mailbox 2 */
+#define CAN_TSR_ABRQ2 0x00800000U /*!<Abort Request for Mailbox 2 */
+#define CAN_TSR_CODE 0x03000000U /*!<Mailbox Code */
+
+#define CAN_TSR_TME 0x1C000000U /*!<TME[2:0] bits */
+#define CAN_TSR_TME0 0x04000000U /*!<Transmit Mailbox 0 Empty */
+#define CAN_TSR_TME1 0x08000000U /*!<Transmit Mailbox 1 Empty */
+#define CAN_TSR_TME2 0x10000000U /*!<Transmit Mailbox 2 Empty */
+
+#define CAN_TSR_LOW 0xE0000000U /*!<LOW[2:0] bits */
+#define CAN_TSR_LOW0 0x20000000U /*!<Lowest Priority Flag for Mailbox 0 */
+#define CAN_TSR_LOW1 0x40000000U /*!<Lowest Priority Flag for Mailbox 1 */
+#define CAN_TSR_LOW2 0x80000000U /*!<Lowest Priority Flag for Mailbox 2 */
+
+/******************* Bit definition for CAN_RF0R register *******************/
+#define CAN_RF0R_FMP0 0x03U /*!<FIFO 0 Message Pending */
+#define CAN_RF0R_FULL0 0x08U /*!<FIFO 0 Full */
+#define CAN_RF0R_FOVR0 0x10U /*!<FIFO 0 Overrun */
+#define CAN_RF0R_RFOM0 0x20U /*!<Release FIFO 0 Output Mailbox */
+
+/******************* Bit definition for CAN_RF1R register *******************/
+#define CAN_RF1R_FMP1 0x03U /*!<FIFO 1 Message Pending */
+#define CAN_RF1R_FULL1 0x08U /*!<FIFO 1 Full */
+#define CAN_RF1R_FOVR1 0x10U /*!<FIFO 1 Overrun */
+#define CAN_RF1R_RFOM1 0x20U /*!<Release FIFO 1 Output Mailbox */
+
+/******************** Bit definition for CAN_IER register *******************/
+#define CAN_IER_TMEIE 0x00000001U /*!<Transmit Mailbox Empty Interrupt Enable */
+#define CAN_IER_FMPIE0 0x00000002U /*!<FIFO Message Pending Interrupt Enable */
+#define CAN_IER_FFIE0 0x00000004U /*!<FIFO Full Interrupt Enable */
+#define CAN_IER_FOVIE0 0x00000008U /*!<FIFO Overrun Interrupt Enable */
+#define CAN_IER_FMPIE1 0x00000010U /*!<FIFO Message Pending Interrupt Enable */
+#define CAN_IER_FFIE1 0x00000020U /*!<FIFO Full Interrupt Enable */
+#define CAN_IER_FOVIE1 0x00000040U /*!<FIFO Overrun Interrupt Enable */
+#define CAN_IER_EWGIE 0x00000100U /*!<Error Warning Interrupt Enable */
+#define CAN_IER_EPVIE 0x00000200U /*!<Error Passive Interrupt Enable */
+#define CAN_IER_BOFIE 0x00000400U /*!<Bus-Off Interrupt Enable */
+#define CAN_IER_LECIE 0x00000800U /*!<Last Error Code Interrupt Enable */
+#define CAN_IER_ERRIE 0x00008000U /*!<Error Interrupt Enable */
+#define CAN_IER_WKUIE 0x00010000U /*!<Wakeup Interrupt Enable */
+#define CAN_IER_SLKIE 0x00020000U /*!<Sleep Interrupt Enable */
+#define CAN_IER_EWGIE 0x00000100U /*!<Error warning interrupt enable */
+#define CAN_IER_EPVIE 0x00000200U /*!<Error passive interrupt enable */
+#define CAN_IER_BOFIE 0x00000400U /*!<Bus-off interrupt enable */
+#define CAN_IER_LECIE 0x00000800U /*!<Last error code interrupt enable */
+#define CAN_IER_ERRIE 0x00008000U /*!<Error interrupt enable */
+
+
+/******************** Bit definition for CAN_ESR register *******************/
+#define CAN_ESR_EWGF 0x00000001U /*!<Error Warning Flag */
+#define CAN_ESR_EPVF 0x00000002U /*!<Error Passive Flag */
+#define CAN_ESR_BOFF 0x00000004U /*!<Bus-Off Flag */
+
+#define CAN_ESR_LEC 0x00000070U /*!<LEC[2:0] bits (Last Error Code) */
+#define CAN_ESR_LEC_0 0x00000010U /*!<Bit 0 */
+#define CAN_ESR_LEC_1 0x00000020U /*!<Bit 1 */
+#define CAN_ESR_LEC_2 0x00000040U /*!<Bit 2 */
+
+#define CAN_ESR_TEC 0x00FF0000U /*!<Least significant byte of the 9-bit Transmit Error Counter */
+#define CAN_ESR_REC 0xFF000000U /*!<Receive Error Counter */
+
+/******************* Bit definition for CAN_BTR register ********************/
+#define CAN_BTR_BRP 0x000003FFU /*!<Baud Rate Prescaler */
+#define CAN_BTR_TS1 0x000F0000U /*!<Time Segment 1 */
+#define CAN_BTR_TS1_0 0x00010000U /*!<Bit 0 */
+#define CAN_BTR_TS1_1 0x00020000U /*!<Bit 1 */
+#define CAN_BTR_TS1_2 0x00040000U /*!<Bit 2 */
+#define CAN_BTR_TS1_3 0x00080000U /*!<Bit 3 */
+#define CAN_BTR_TS2 0x00700000U /*!<Time Segment 2 */
+#define CAN_BTR_TS2_0 0x00100000U /*!<Bit 0 */
+#define CAN_BTR_TS2_1 0x00200000U /*!<Bit 1 */
+#define CAN_BTR_TS2_2 0x00400000U /*!<Bit 2 */
+#define CAN_BTR_SJW 0x03000000U /*!<Resynchronization Jump Width */
+#define CAN_BTR_SJW_0 0x01000000U /*!<Bit 0 */
+#define CAN_BTR_SJW_1 0x02000000U /*!<Bit 1 */
+#define CAN_BTR_LBKM 0x40000000U /*!<Loop Back Mode (Debug) */
+#define CAN_BTR_SILM 0x80000000U /*!<Silent Mode */
+
+
+/*!<Mailbox registers */
+/****************** Bit definition for CAN_TI0R register ********************/
+#define CAN_TI0R_TXRQ 0x00000001U /*!<Transmit Mailbox Request */
+#define CAN_TI0R_RTR 0x00000002U /*!<Remote Transmission Request */
+#define CAN_TI0R_IDE 0x00000004U /*!<Identifier Extension */
+#define CAN_TI0R_EXID 0x001FFFF8U /*!<Extended Identifier */
+#define CAN_TI0R_STID 0xFFE00000U /*!<Standard Identifier or Extended Identifier */
+
+/****************** Bit definition for CAN_TDT0R register *******************/
+#define CAN_TDT0R_DLC 0x0000000FU /*!<Data Length Code */
+#define CAN_TDT0R_TGT 0x00000100U /*!<Transmit Global Time */
+#define CAN_TDT0R_TIME 0xFFFF0000U /*!<Message Time Stamp */
+
+/****************** Bit definition for CAN_TDL0R register *******************/
+#define CAN_TDL0R_DATA0 0x000000FFU /*!<Data byte 0 */
+#define CAN_TDL0R_DATA1 0x0000FF00U /*!<Data byte 1 */
+#define CAN_TDL0R_DATA2 0x00FF0000U /*!<Data byte 2 */
+#define CAN_TDL0R_DATA3 0xFF000000U /*!<Data byte 3 */
+
+/****************** Bit definition for CAN_TDH0R register *******************/
+#define CAN_TDH0R_DATA4 0x000000FFU /*!<Data byte 4 */
+#define CAN_TDH0R_DATA5 0x0000FF00U /*!<Data byte 5 */
+#define CAN_TDH0R_DATA6 0x00FF0000U /*!<Data byte 6 */
+#define CAN_TDH0R_DATA7 0xFF000000U /*!<Data byte 7 */
+
+/******************* Bit definition for CAN_TI1R register *******************/
+#define CAN_TI1R_TXRQ 0x00000001U /*!<Transmit Mailbox Request */
+#define CAN_TI1R_RTR 0x00000002U /*!<Remote Transmission Request */
+#define CAN_TI1R_IDE 0x00000004U /*!<Identifier Extension */
+#define CAN_TI1R_EXID 0x001FFFF8U /*!<Extended Identifier */
+#define CAN_TI1R_STID 0xFFE00000U /*!<Standard Identifier or Extended Identifier */
+
+/******************* Bit definition for CAN_TDT1R register ******************/
+#define CAN_TDT1R_DLC 0x0000000FU /*!<Data Length Code */
+#define CAN_TDT1R_TGT 0x00000100U /*!<Transmit Global Time */
+#define CAN_TDT1R_TIME 0xFFFF0000U /*!<Message Time Stamp */
+
+/******************* Bit definition for CAN_TDL1R register ******************/
+#define CAN_TDL1R_DATA0 0x000000FFU /*!<Data byte 0 */
+#define CAN_TDL1R_DATA1 0x0000FF00U /*!<Data byte 1 */
+#define CAN_TDL1R_DATA2 0x00FF0000U /*!<Data byte 2 */
+#define CAN_TDL1R_DATA3 0xFF000000U /*!<Data byte 3 */
+
+/******************* Bit definition for CAN_TDH1R register ******************/
+#define CAN_TDH1R_DATA4 0x000000FFU /*!<Data byte 4 */
+#define CAN_TDH1R_DATA5 0x0000FF00U /*!<Data byte 5 */
+#define CAN_TDH1R_DATA6 0x00FF0000U /*!<Data byte 6 */
+#define CAN_TDH1R_DATA7 0xFF000000U /*!<Data byte 7 */
+
+/******************* Bit definition for CAN_TI2R register *******************/
+#define CAN_TI2R_TXRQ 0x00000001U /*!<Transmit Mailbox Request */
+#define CAN_TI2R_RTR 0x00000002U /*!<Remote Transmission Request */
+#define CAN_TI2R_IDE 0x00000004U /*!<Identifier Extension */
+#define CAN_TI2R_EXID 0x001FFFF8U /*!<Extended identifier */
+#define CAN_TI2R_STID 0xFFE00000U /*!<Standard Identifier or Extended Identifier */
+
+/******************* Bit definition for CAN_TDT2R register ******************/
+#define CAN_TDT2R_DLC 0x0000000FU /*!<Data Length Code */
+#define CAN_TDT2R_TGT 0x00000100U /*!<Transmit Global Time */
+#define CAN_TDT2R_TIME 0xFFFF0000U /*!<Message Time Stamp */
+
+/******************* Bit definition for CAN_TDL2R register ******************/
+#define CAN_TDL2R_DATA0 0x000000FFU /*!<Data byte 0 */
+#define CAN_TDL2R_DATA1 0x0000FF00U /*!<Data byte 1 */
+#define CAN_TDL2R_DATA2 0x00FF0000U /*!<Data byte 2 */
+#define CAN_TDL2R_DATA3 0xFF000000U /*!<Data byte 3 */
+
+/******************* Bit definition for CAN_TDH2R register ******************/
+#define CAN_TDH2R_DATA4 0x000000FFU /*!<Data byte 4 */
+#define CAN_TDH2R_DATA5 0x0000FF00U /*!<Data byte 5 */
+#define CAN_TDH2R_DATA6 0x00FF0000U /*!<Data byte 6 */
+#define CAN_TDH2R_DATA7 0xFF000000U /*!<Data byte 7 */
+
+/******************* Bit definition for CAN_RI0R register *******************/
+#define CAN_RI0R_RTR 0x00000002U /*!<Remote Transmission Request */
+#define CAN_RI0R_IDE 0x00000004U /*!<Identifier Extension */
+#define CAN_RI0R_EXID 0x001FFFF8U /*!<Extended Identifier */
+#define CAN_RI0R_STID 0xFFE00000U /*!<Standard Identifier or Extended Identifier */
+
+/******************* Bit definition for CAN_RDT0R register ******************/
+#define CAN_RDT0R_DLC 0x0000000FU /*!<Data Length Code */
+#define CAN_RDT0R_FMI 0x0000FF00U /*!<Filter Match Index */
+#define CAN_RDT0R_TIME 0xFFFF0000U /*!<Message Time Stamp */
+
+/******************* Bit definition for CAN_RDL0R register ******************/
+#define CAN_RDL0R_DATA0 0x000000FFU /*!<Data byte 0 */
+#define CAN_RDL0R_DATA1 0x0000FF00U /*!<Data byte 1 */
+#define CAN_RDL0R_DATA2 0x00FF0000U /*!<Data byte 2 */
+#define CAN_RDL0R_DATA3 0xFF000000U /*!<Data byte 3 */
+
+/******************* Bit definition for CAN_RDH0R register ******************/
+#define CAN_RDH0R_DATA4 0x000000FFU /*!<Data byte 4 */
+#define CAN_RDH0R_DATA5 0x0000FF00U /*!<Data byte 5 */
+#define CAN_RDH0R_DATA6 0x00FF0000U /*!<Data byte 6 */
+#define CAN_RDH0R_DATA7 0xFF000000U /*!<Data byte 7 */
+
+/******************* Bit definition for CAN_RI1R register *******************/
+#define CAN_RI1R_RTR 0x00000002U /*!<Remote Transmission Request */
+#define CAN_RI1R_IDE 0x00000004U /*!<Identifier Extension */
+#define CAN_RI1R_EXID 0x001FFFF8U /*!<Extended identifier */
+#define CAN_RI1R_STID 0xFFE00000U /*!<Standard Identifier or Extended Identifier */
+
+/******************* Bit definition for CAN_RDT1R register ******************/
+#define CAN_RDT1R_DLC 0x0000000FU /*!<Data Length Code */
+#define CAN_RDT1R_FMI 0x0000FF00U /*!<Filter Match Index */
+#define CAN_RDT1R_TIME 0xFFFF0000U /*!<Message Time Stamp */
+
+/******************* Bit definition for CAN_RDL1R register ******************/
+#define CAN_RDL1R_DATA0 0x000000FFU /*!<Data byte 0 */
+#define CAN_RDL1R_DATA1 0x0000FF00U /*!<Data byte 1 */
+#define CAN_RDL1R_DATA2 0x00FF0000U /*!<Data byte 2 */
+#define CAN_RDL1R_DATA3 0xFF000000U /*!<Data byte 3 */
+
+/******************* Bit definition for CAN_RDH1R register ******************/
+#define CAN_RDH1R_DATA4 0x000000FFU /*!<Data byte 4 */
+#define CAN_RDH1R_DATA5 0x0000FF00U /*!<Data byte 5 */
+#define CAN_RDH1R_DATA6 0x00FF0000U /*!<Data byte 6 */
+#define CAN_RDH1R_DATA7 0xFF000000U /*!<Data byte 7 */
+
+/*!<CAN filter registers */
+/******************* Bit definition for CAN_FMR register ********************/
+#define CAN_FMR_FINIT 0x01U /*!<Filter Init Mode */
+#define CAN_FMR_CAN2SB 0x00003F00U /*!<CAN2 start bank */
+
+/******************* Bit definition for CAN_FM1R register *******************/
+#define CAN_FM1R_FBM 0x0FFFFFFFU /*!<Filter Mode */
+#define CAN_FM1R_FBM0 0x00000001U /*!<Filter Init Mode bit 0 */
+#define CAN_FM1R_FBM1 0x00000002U /*!<Filter Init Mode bit 1 */
+#define CAN_FM1R_FBM2 0x00000004U /*!<Filter Init Mode bit 2 */
+#define CAN_FM1R_FBM3 0x00000008U /*!<Filter Init Mode bit 3 */
+#define CAN_FM1R_FBM4 0x00000010U /*!<Filter Init Mode bit 4 */
+#define CAN_FM1R_FBM5 0x00000020U /*!<Filter Init Mode bit 5 */
+#define CAN_FM1R_FBM6 0x00000040U /*!<Filter Init Mode bit 6 */
+#define CAN_FM1R_FBM7 0x00000080U /*!<Filter Init Mode bit 7 */
+#define CAN_FM1R_FBM8 0x00000100U /*!<Filter Init Mode bit 8 */
+#define CAN_FM1R_FBM9 0x00000200U /*!<Filter Init Mode bit 9 */
+#define CAN_FM1R_FBM10 0x00000400U /*!<Filter Init Mode bit 10 */
+#define CAN_FM1R_FBM11 0x00000800U /*!<Filter Init Mode bit 11 */
+#define CAN_FM1R_FBM12 0x00001000U /*!<Filter Init Mode bit 12 */
+#define CAN_FM1R_FBM13 0x00002000U /*!<Filter Init Mode bit 13 */
+#define CAN_FM1R_FBM14 0x00004000U /*!<Filter Init Mode bit 14 */
+#define CAN_FM1R_FBM15 0x00008000U /*!<Filter Init Mode bit 15 */
+#define CAN_FM1R_FBM16 0x00010000U /*!<Filter Init Mode bit 16 */
+#define CAN_FM1R_FBM17 0x00020000U /*!<Filter Init Mode bit 17 */
+#define CAN_FM1R_FBM18 0x00040000U /*!<Filter Init Mode bit 18 */
+#define CAN_FM1R_FBM19 0x00080000U /*!<Filter Init Mode bit 19 */
+#define CAN_FM1R_FBM20 0x00100000U /*!<Filter Init Mode bit 20 */
+#define CAN_FM1R_FBM21 0x00200000U /*!<Filter Init Mode bit 21 */
+#define CAN_FM1R_FBM22 0x00400000U /*!<Filter Init Mode bit 22 */
+#define CAN_FM1R_FBM23 0x00800000U /*!<Filter Init Mode bit 23 */
+#define CAN_FM1R_FBM24 0x01000000U /*!<Filter Init Mode bit 24 */
+#define CAN_FM1R_FBM25 0x02000000U /*!<Filter Init Mode bit 25 */
+#define CAN_FM1R_FBM26 0x04000000U /*!<Filter Init Mode bit 26 */
+#define CAN_FM1R_FBM27 0x08000000U /*!<Filter Init Mode bit 27 */
+
+/******************* Bit definition for CAN_FS1R register *******************/
+#define CAN_FS1R_FSC 0x0FFFFFFFU /*!<Filter Scale Configuration */
+#define CAN_FS1R_FSC0 0x00000001U /*!<Filter Scale Configuration bit 0 */
+#define CAN_FS1R_FSC1 0x00000002U /*!<Filter Scale Configuration bit 1 */
+#define CAN_FS1R_FSC2 0x00000004U /*!<Filter Scale Configuration bit 2 */
+#define CAN_FS1R_FSC3 0x00000008U /*!<Filter Scale Configuration bit 3 */
+#define CAN_FS1R_FSC4 0x00000010U /*!<Filter Scale Configuration bit 4 */
+#define CAN_FS1R_FSC5 0x00000020U /*!<Filter Scale Configuration bit 5 */
+#define CAN_FS1R_FSC6 0x00000040U /*!<Filter Scale Configuration bit 6 */
+#define CAN_FS1R_FSC7 0x00000080U /*!<Filter Scale Configuration bit 7 */
+#define CAN_FS1R_FSC8 0x00000100U /*!<Filter Scale Configuration bit 8 */
+#define CAN_FS1R_FSC9 0x00000200U /*!<Filter Scale Configuration bit 9 */
+#define CAN_FS1R_FSC10 0x00000400U /*!<Filter Scale Configuration bit 10 */
+#define CAN_FS1R_FSC11 0x00000800U /*!<Filter Scale Configuration bit 11 */
+#define CAN_FS1R_FSC12 0x00001000U /*!<Filter Scale Configuration bit 12 */
+#define CAN_FS1R_FSC13 0x00002000U /*!<Filter Scale Configuration bit 13 */
+#define CAN_FS1R_FSC14 0x00004000U /*!<Filter Scale Configuration bit 14 */
+#define CAN_FS1R_FSC15 0x00008000U /*!<Filter Scale Configuration bit 15 */
+#define CAN_FS1R_FSC16 0x00010000U /*!<Filter Scale Configuration bit 16 */
+#define CAN_FS1R_FSC17 0x00020000U /*!<Filter Scale Configuration bit 17 */
+#define CAN_FS1R_FSC18 0x00040000U /*!<Filter Scale Configuration bit 18 */
+#define CAN_FS1R_FSC19 0x00080000U /*!<Filter Scale Configuration bit 19 */
+#define CAN_FS1R_FSC20 0x00100000U /*!<Filter Scale Configuration bit 20 */
+#define CAN_FS1R_FSC21 0x00200000U /*!<Filter Scale Configuration bit 21 */
+#define CAN_FS1R_FSC22 0x00400000U /*!<Filter Scale Configuration bit 22 */
+#define CAN_FS1R_FSC23 0x00800000U /*!<Filter Scale Configuration bit 23 */
+#define CAN_FS1R_FSC24 0x01000000U /*!<Filter Scale Configuration bit 24 */
+#define CAN_FS1R_FSC25 0x02000000U /*!<Filter Scale Configuration bit 25 */
+#define CAN_FS1R_FSC26 0x04000000U /*!<Filter Scale Configuration bit 26 */
+#define CAN_FS1R_FSC27 0x08000000U /*!<Filter Scale Configuration bit 27 */
+
+/****************** Bit definition for CAN_FFA1R register *******************/
+#define CAN_FFA1R_FFA 0x0FFFFFFFU /*!<Filter FIFO Assignment */
+#define CAN_FFA1R_FFA0 0x00000001U /*!<Filter FIFO Assignment bit 0 */
+#define CAN_FFA1R_FFA1 0x00000002U /*!<Filter FIFO Assignment bit 1 */
+#define CAN_FFA1R_FFA2 0x00000004U /*!<Filter FIFO Assignment bit 2 */
+#define CAN_FFA1R_FFA3 0x00000008U /*!<Filter FIFO Assignment bit 3 */
+#define CAN_FFA1R_FFA4 0x00000010U /*!<Filter FIFO Assignment bit 4 */
+#define CAN_FFA1R_FFA5 0x00000020U /*!<Filter FIFO Assignment bit 5 */
+#define CAN_FFA1R_FFA6 0x00000040U /*!<Filter FIFO Assignment bit 6 */
+#define CAN_FFA1R_FFA7 0x00000080U /*!<Filter FIFO Assignment bit 7 */
+#define CAN_FFA1R_FFA8 0x00000100U /*!<Filter FIFO Assignment bit 8 */
+#define CAN_FFA1R_FFA9 0x00000200U /*!<Filter FIFO Assignment bit 9 */
+#define CAN_FFA1R_FFA10 0x00000400U /*!<Filter FIFO Assignment bit 10 */
+#define CAN_FFA1R_FFA11 0x00000800U /*!<Filter FIFO Assignment bit 11 */
+#define CAN_FFA1R_FFA12 0x00001000U /*!<Filter FIFO Assignment bit 12 */
+#define CAN_FFA1R_FFA13 0x00002000U /*!<Filter FIFO Assignment bit 13 */
+#define CAN_FFA1R_FFA14 0x00004000U /*!<Filter FIFO Assignment bit 14 */
+#define CAN_FFA1R_FFA15 0x00008000U /*!<Filter FIFO Assignment bit 15 */
+#define CAN_FFA1R_FFA16 0x00010000U /*!<Filter FIFO Assignment bit 16 */
+#define CAN_FFA1R_FFA17 0x00020000U /*!<Filter FIFO Assignment bit 17 */
+#define CAN_FFA1R_FFA18 0x00040000U /*!<Filter FIFO Assignment bit 18 */
+#define CAN_FFA1R_FFA19 0x00080000U /*!<Filter FIFO Assignment bit 19 */
+#define CAN_FFA1R_FFA20 0x00100000U /*!<Filter FIFO Assignment bit 20 */
+#define CAN_FFA1R_FFA21 0x00200000U /*!<Filter FIFO Assignment bit 21 */
+#define CAN_FFA1R_FFA22 0x00400000U /*!<Filter FIFO Assignment bit 22 */
+#define CAN_FFA1R_FFA23 0x00800000U /*!<Filter FIFO Assignment bit 23 */
+#define CAN_FFA1R_FFA24 0x01000000U /*!<Filter FIFO Assignment bit 24 */
+#define CAN_FFA1R_FFA25 0x02000000U /*!<Filter FIFO Assignment bit 25 */
+#define CAN_FFA1R_FFA26 0x04000000U /*!<Filter FIFO Assignment bit 26 */
+#define CAN_FFA1R_FFA27 0x08000000U /*!<Filter FIFO Assignment bit 27 */
+
+/******************* Bit definition for CAN_FA1R register *******************/
+#define CAN_FA1R_FACT 0x0FFFFFFFU /*!<Filter Active */
+#define CAN_FA1R_FACT0 0x00000001U /*!<Filter Active bit 0 */
+#define CAN_FA1R_FACT1 0x00000002U /*!<Filter Active bit 1 */
+#define CAN_FA1R_FACT2 0x00000004U /*!<Filter Active bit 2 */
+#define CAN_FA1R_FACT3 0x00000008U /*!<Filter Active bit 3 */
+#define CAN_FA1R_FACT4 0x00000010U /*!<Filter Active bit 4 */
+#define CAN_FA1R_FACT5 0x00000020U /*!<Filter Active bit 5 */
+#define CAN_FA1R_FACT6 0x00000040U /*!<Filter Active bit 6 */
+#define CAN_FA1R_FACT7 0x00000080U /*!<Filter Active bit 7 */
+#define CAN_FA1R_FACT8 0x00000100U /*!<Filter Active bit 8 */
+#define CAN_FA1R_FACT9 0x00000200U /*!<Filter Active bit 9 */
+#define CAN_FA1R_FACT10 0x00000400U /*!<Filter Active bit 10 */
+#define CAN_FA1R_FACT11 0x00000800U /*!<Filter Active bit 11 */
+#define CAN_FA1R_FACT12 0x00001000U /*!<Filter Active bit 12 */
+#define CAN_FA1R_FACT13 0x00002000U /*!<Filter Active bit 13 */
+#define CAN_FA1R_FACT14 0x00004000U /*!<Filter Active bit 14 */
+#define CAN_FA1R_FACT15 0x00008000U /*!<Filter Active bit 15 */
+#define CAN_FA1R_FACT16 0x00010000U /*!<Filter Active bit 16 */
+#define CAN_FA1R_FACT17 0x00020000U /*!<Filter Active bit 17 */
+#define CAN_FA1R_FACT18 0x00040000U /*!<Filter Active bit 18 */
+#define CAN_FA1R_FACT19 0x00080000U /*!<Filter Active bit 19 */
+#define CAN_FA1R_FACT20 0x00100000U /*!<Filter Active bit 20 */
+#define CAN_FA1R_FACT21 0x00200000U /*!<Filter Active bit 21 */
+#define CAN_FA1R_FACT22 0x00400000U /*!<Filter Active bit 22 */
+#define CAN_FA1R_FACT23 0x00800000U /*!<Filter Active bit 23 */
+#define CAN_FA1R_FACT24 0x01000000U /*!<Filter Active bit 24 */
+#define CAN_FA1R_FACT25 0x02000000U /*!<Filter Active bit 25 */
+#define CAN_FA1R_FACT26 0x04000000U /*!<Filter Active bit 26 */
+#define CAN_FA1R_FACT27 0x08000000U /*!<Filter Active bit 27 */
+
+/******************* Bit definition for CAN_F0R1 register *******************/
+#define CAN_F0R1_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F0R1_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F0R1_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F0R1_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F0R1_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F0R1_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F0R1_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F0R1_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F0R1_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F0R1_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F0R1_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F0R1_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F0R1_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F0R1_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F0R1_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F0R1_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F0R1_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F0R1_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F0R1_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F0R1_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F0R1_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F0R1_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F0R1_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F0R1_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F0R1_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F0R1_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F0R1_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F0R1_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F0R1_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F0R1_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F0R1_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F0R1_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F1R1 register *******************/
+#define CAN_F1R1_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F1R1_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F1R1_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F1R1_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F1R1_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F1R1_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F1R1_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F1R1_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F1R1_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F1R1_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F1R1_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F1R1_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F1R1_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F1R1_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F1R1_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F1R1_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F1R1_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F1R1_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F1R1_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F1R1_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F1R1_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F1R1_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F1R1_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F1R1_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F1R1_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F1R1_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F1R1_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F1R1_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F1R1_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F1R1_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F1R1_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F1R1_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F2R1 register *******************/
+#define CAN_F2R1_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F2R1_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F2R1_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F2R1_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F2R1_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F2R1_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F2R1_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F2R1_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F2R1_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F2R1_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F2R1_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F2R1_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F2R1_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F2R1_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F2R1_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F2R1_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F2R1_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F2R1_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F2R1_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F2R1_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F2R1_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F2R1_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F2R1_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F2R1_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F2R1_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F2R1_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F2R1_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F2R1_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F2R1_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F2R1_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F2R1_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F2R1_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F3R1 register *******************/
+#define CAN_F3R1_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F3R1_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F3R1_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F3R1_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F3R1_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F3R1_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F3R1_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F3R1_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F3R1_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F3R1_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F3R1_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F3R1_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F3R1_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F3R1_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F3R1_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F3R1_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F3R1_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F3R1_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F3R1_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F3R1_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F3R1_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F3R1_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F3R1_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F3R1_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F3R1_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F3R1_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F3R1_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F3R1_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F3R1_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F3R1_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F3R1_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F3R1_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F4R1 register *******************/
+#define CAN_F4R1_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F4R1_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F4R1_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F4R1_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F4R1_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F4R1_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F4R1_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F4R1_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F4R1_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F4R1_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F4R1_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F4R1_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F4R1_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F4R1_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F4R1_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F4R1_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F4R1_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F4R1_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F4R1_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F4R1_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F4R1_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F4R1_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F4R1_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F4R1_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F4R1_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F4R1_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F4R1_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F4R1_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F4R1_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F4R1_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F4R1_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F4R1_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F5R1 register *******************/
+#define CAN_F5R1_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F5R1_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F5R1_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F5R1_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F5R1_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F5R1_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F5R1_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F5R1_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F5R1_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F5R1_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F5R1_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F5R1_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F5R1_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F5R1_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F5R1_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F5R1_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F5R1_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F5R1_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F5R1_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F5R1_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F5R1_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F5R1_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F5R1_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F5R1_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F5R1_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F5R1_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F5R1_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F5R1_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F5R1_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F5R1_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F5R1_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F5R1_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F6R1 register *******************/
+#define CAN_F6R1_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F6R1_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F6R1_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F6R1_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F6R1_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F6R1_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F6R1_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F6R1_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F6R1_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F6R1_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F6R1_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F6R1_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F6R1_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F6R1_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F6R1_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F6R1_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F6R1_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F6R1_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F6R1_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F6R1_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F6R1_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F6R1_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F6R1_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F6R1_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F6R1_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F6R1_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F6R1_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F6R1_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F6R1_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F6R1_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F6R1_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F6R1_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F7R1 register *******************/
+#define CAN_F7R1_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F7R1_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F7R1_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F7R1_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F7R1_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F7R1_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F7R1_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F7R1_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F7R1_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F7R1_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F7R1_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F7R1_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F7R1_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F7R1_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F7R1_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F7R1_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F7R1_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F7R1_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F7R1_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F7R1_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F7R1_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F7R1_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F7R1_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F7R1_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F7R1_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F7R1_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F7R1_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F7R1_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F7R1_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F7R1_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F7R1_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F7R1_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F8R1 register *******************/
+#define CAN_F8R1_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F8R1_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F8R1_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F8R1_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F8R1_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F8R1_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F8R1_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F8R1_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F8R1_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F8R1_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F8R1_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F8R1_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F8R1_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F8R1_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F8R1_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F8R1_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F8R1_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F8R1_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F8R1_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F8R1_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F8R1_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F8R1_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F8R1_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F8R1_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F8R1_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F8R1_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F8R1_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F8R1_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F8R1_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F8R1_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F8R1_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F8R1_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F9R1 register *******************/
+#define CAN_F9R1_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F9R1_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F9R1_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F9R1_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F9R1_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F9R1_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F9R1_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F9R1_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F9R1_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F9R1_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F9R1_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F9R1_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F9R1_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F9R1_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F9R1_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F9R1_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F9R1_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F9R1_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F9R1_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F9R1_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F9R1_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F9R1_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F9R1_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F9R1_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F9R1_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F9R1_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F9R1_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F9R1_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F9R1_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F9R1_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F9R1_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F9R1_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F10R1 register ******************/
+#define CAN_F10R1_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F10R1_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F10R1_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F10R1_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F10R1_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F10R1_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F10R1_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F10R1_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F10R1_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F10R1_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F10R1_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F10R1_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F10R1_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F10R1_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F10R1_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F10R1_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F10R1_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F10R1_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F10R1_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F10R1_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F10R1_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F10R1_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F10R1_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F10R1_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F10R1_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F10R1_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F10R1_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F10R1_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F10R1_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F10R1_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F10R1_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F10R1_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F11R1 register ******************/
+#define CAN_F11R1_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F11R1_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F11R1_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F11R1_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F11R1_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F11R1_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F11R1_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F11R1_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F11R1_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F11R1_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F11R1_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F11R1_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F11R1_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F11R1_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F11R1_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F11R1_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F11R1_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F11R1_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F11R1_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F11R1_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F11R1_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F11R1_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F11R1_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F11R1_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F11R1_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F11R1_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F11R1_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F11R1_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F11R1_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F11R1_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F11R1_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F11R1_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F12R1 register ******************/
+#define CAN_F12R1_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F12R1_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F12R1_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F12R1_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F12R1_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F12R1_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F12R1_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F12R1_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F12R1_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F12R1_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F12R1_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F12R1_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F12R1_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F12R1_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F12R1_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F12R1_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F12R1_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F12R1_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F12R1_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F12R1_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F12R1_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F12R1_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F12R1_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F12R1_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F12R1_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F12R1_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F12R1_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F12R1_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F12R1_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F12R1_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F12R1_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F12R1_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F13R1 register ******************/
+#define CAN_F13R1_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F13R1_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F13R1_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F13R1_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F13R1_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F13R1_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F13R1_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F13R1_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F13R1_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F13R1_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F13R1_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F13R1_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F13R1_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F13R1_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F13R1_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F13R1_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F13R1_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F13R1_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F13R1_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F13R1_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F13R1_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F13R1_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F13R1_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F13R1_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F13R1_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F13R1_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F13R1_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F13R1_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F13R1_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F13R1_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F13R1_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F13R1_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F0R2 register *******************/
+#define CAN_F0R2_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F0R2_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F0R2_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F0R2_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F0R2_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F0R2_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F0R2_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F0R2_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F0R2_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F0R2_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F0R2_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F0R2_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F0R2_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F0R2_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F0R2_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F0R2_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F0R2_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F0R2_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F0R2_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F0R2_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F0R2_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F0R2_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F0R2_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F0R2_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F0R2_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F0R2_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F0R2_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F0R2_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F0R2_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F0R2_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F0R2_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F0R2_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F1R2 register *******************/
+#define CAN_F1R2_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F1R2_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F1R2_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F1R2_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F1R2_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F1R2_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F1R2_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F1R2_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F1R2_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F1R2_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F1R2_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F1R2_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F1R2_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F1R2_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F1R2_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F1R2_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F1R2_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F1R2_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F1R2_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F1R2_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F1R2_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F1R2_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F1R2_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F1R2_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F1R2_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F1R2_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F1R2_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F1R2_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F1R2_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F1R2_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F1R2_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F1R2_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F2R2 register *******************/
+#define CAN_F2R2_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F2R2_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F2R2_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F2R2_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F2R2_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F2R2_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F2R2_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F2R2_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F2R2_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F2R2_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F2R2_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F2R2_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F2R2_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F2R2_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F2R2_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F2R2_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F2R2_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F2R2_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F2R2_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F2R2_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F2R2_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F2R2_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F2R2_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F2R2_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F2R2_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F2R2_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F2R2_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F2R2_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F2R2_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F2R2_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F2R2_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F2R2_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F3R2 register *******************/
+#define CAN_F3R2_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F3R2_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F3R2_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F3R2_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F3R2_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F3R2_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F3R2_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F3R2_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F3R2_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F3R2_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F3R2_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F3R2_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F3R2_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F3R2_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F3R2_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F3R2_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F3R2_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F3R2_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F3R2_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F3R2_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F3R2_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F3R2_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F3R2_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F3R2_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F3R2_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F3R2_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F3R2_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F3R2_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F3R2_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F3R2_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F3R2_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F3R2_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F4R2 register *******************/
+#define CAN_F4R2_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F4R2_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F4R2_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F4R2_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F4R2_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F4R2_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F4R2_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F4R2_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F4R2_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F4R2_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F4R2_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F4R2_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F4R2_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F4R2_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F4R2_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F4R2_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F4R2_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F4R2_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F4R2_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F4R2_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F4R2_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F4R2_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F4R2_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F4R2_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F4R2_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F4R2_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F4R2_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F4R2_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F4R2_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F4R2_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F4R2_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F4R2_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F5R2 register *******************/
+#define CAN_F5R2_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F5R2_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F5R2_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F5R2_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F5R2_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F5R2_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F5R2_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F5R2_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F5R2_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F5R2_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F5R2_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F5R2_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F5R2_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F5R2_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F5R2_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F5R2_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F5R2_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F5R2_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F5R2_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F5R2_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F5R2_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F5R2_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F5R2_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F5R2_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F5R2_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F5R2_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F5R2_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F5R2_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F5R2_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F5R2_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F5R2_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F5R2_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F6R2 register *******************/
+#define CAN_F6R2_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F6R2_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F6R2_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F6R2_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F6R2_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F6R2_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F6R2_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F6R2_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F6R2_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F6R2_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F6R2_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F6R2_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F6R2_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F6R2_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F6R2_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F6R2_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F6R2_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F6R2_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F6R2_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F6R2_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F6R2_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F6R2_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F6R2_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F6R2_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F6R2_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F6R2_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F6R2_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F6R2_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F6R2_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F6R2_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F6R2_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F6R2_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F7R2 register *******************/
+#define CAN_F7R2_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F7R2_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F7R2_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F7R2_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F7R2_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F7R2_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F7R2_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F7R2_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F7R2_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F7R2_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F7R2_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F7R2_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F7R2_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F7R2_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F7R2_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F7R2_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F7R2_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F7R2_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F7R2_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F7R2_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F7R2_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F7R2_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F7R2_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F7R2_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F7R2_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F7R2_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F7R2_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F7R2_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F7R2_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F7R2_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F7R2_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F7R2_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F8R2 register *******************/
+#define CAN_F8R2_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F8R2_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F8R2_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F8R2_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F8R2_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F8R2_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F8R2_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F8R2_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F8R2_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F8R2_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F8R2_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F8R2_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F8R2_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F8R2_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F8R2_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F8R2_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F8R2_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F8R2_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F8R2_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F8R2_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F8R2_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F8R2_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F8R2_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F8R2_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F8R2_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F8R2_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F8R2_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F8R2_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F8R2_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F8R2_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F8R2_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F8R2_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F9R2 register *******************/
+#define CAN_F9R2_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F9R2_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F9R2_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F9R2_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F9R2_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F9R2_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F9R2_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F9R2_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F9R2_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F9R2_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F9R2_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F9R2_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F9R2_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F9R2_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F9R2_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F9R2_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F9R2_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F9R2_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F9R2_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F9R2_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F9R2_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F9R2_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F9R2_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F9R2_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F9R2_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F9R2_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F9R2_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F9R2_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F9R2_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F9R2_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F9R2_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F9R2_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F10R2 register ******************/
+#define CAN_F10R2_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F10R2_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F10R2_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F10R2_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F10R2_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F10R2_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F10R2_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F10R2_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F10R2_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F10R2_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F10R2_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F10R2_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F10R2_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F10R2_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F10R2_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F10R2_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F10R2_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F10R2_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F10R2_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F10R2_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F10R2_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F10R2_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F10R2_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F10R2_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F10R2_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F10R2_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F10R2_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F10R2_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F10R2_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F10R2_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F10R2_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F10R2_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F11R2 register ******************/
+#define CAN_F11R2_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F11R2_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F11R2_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F11R2_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F11R2_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F11R2_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F11R2_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F11R2_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F11R2_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F11R2_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F11R2_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F11R2_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F11R2_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F11R2_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F11R2_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F11R2_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F11R2_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F11R2_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F11R2_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F11R2_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F11R2_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F11R2_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F11R2_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F11R2_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F11R2_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F11R2_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F11R2_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F11R2_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F11R2_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F11R2_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F11R2_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F11R2_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F12R2 register ******************/
+#define CAN_F12R2_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F12R2_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F12R2_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F12R2_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F12R2_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F12R2_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F12R2_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F12R2_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F12R2_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F12R2_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F12R2_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F12R2_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F12R2_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F12R2_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F12R2_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F12R2_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F12R2_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F12R2_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F12R2_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F12R2_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F12R2_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F12R2_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F12R2_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F12R2_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F12R2_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F12R2_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F12R2_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F12R2_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F12R2_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F12R2_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F12R2_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F12R2_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F13R2 register ******************/
+#define CAN_F13R2_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F13R2_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F13R2_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F13R2_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F13R2_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F13R2_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F13R2_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F13R2_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F13R2_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F13R2_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F13R2_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F13R2_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F13R2_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F13R2_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F13R2_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F13R2_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F13R2_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F13R2_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F13R2_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F13R2_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F13R2_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F13R2_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F13R2_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F13R2_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F13R2_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F13R2_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F13R2_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F13R2_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F13R2_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F13R2_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F13R2_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F13R2_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************************************************************************/
+/* */
+/* CRC calculation unit */
+/* */
+/******************************************************************************/
+/******************* Bit definition for CRC_DR register *********************/
+#define CRC_DR_DR 0xFFFFFFFFU /*!< Data register bits */
+
+
+/******************* Bit definition for CRC_IDR register ********************/
+#define CRC_IDR_IDR 0xFFU /*!< General-purpose 8-bit data register bits */
+
+
+/******************** Bit definition for CRC_CR register ********************/
+#define CRC_CR_RESET 0x01U /*!< RESET bit */
+
+
+/******************************************************************************/
+/* */
+/* Digital to Analog Converter */
+/* */
+/******************************************************************************/
+/******************** Bit definition for DAC_CR register ********************/
+#define DAC_CR_EN1 0x00000001U /*!<DAC channel1 enable */
+#define DAC_CR_BOFF1 0x00000002U /*!<DAC channel1 output buffer disable */
+#define DAC_CR_TEN1 0x00000004U /*!<DAC channel1 Trigger enable */
+
+#define DAC_CR_TSEL1 0x00000038U /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */
+#define DAC_CR_TSEL1_0 0x00000008U /*!<Bit 0 */
+#define DAC_CR_TSEL1_1 0x00000010U /*!<Bit 1 */
+#define DAC_CR_TSEL1_2 0x00000020U /*!<Bit 2 */
+
+#define DAC_CR_WAVE1 0x000000C0U /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
+#define DAC_CR_WAVE1_0 0x00000040U /*!<Bit 0 */
+#define DAC_CR_WAVE1_1 0x00000080U /*!<Bit 1 */
+
+#define DAC_CR_MAMP1 0x00000F00U /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
+#define DAC_CR_MAMP1_0 0x00000100U /*!<Bit 0 */
+#define DAC_CR_MAMP1_1 0x00000200U /*!<Bit 1 */
+#define DAC_CR_MAMP1_2 0x00000400U /*!<Bit 2 */
+#define DAC_CR_MAMP1_3 0x00000800U /*!<Bit 3 */
+
+#define DAC_CR_DMAEN1 0x00001000U /*!<DAC channel1 DMA enable */
+#define DAC_CR_DMAUDRIE1 0x00002000U /*!<DAC channel1 DMA underrun interrupt enable*/
+#define DAC_CR_EN2 0x00010000U /*!<DAC channel2 enable */
+#define DAC_CR_BOFF2 0x00020000U /*!<DAC channel2 output buffer disable */
+#define DAC_CR_TEN2 0x00040000U /*!<DAC channel2 Trigger enable */
+
+#define DAC_CR_TSEL2 0x00380000U /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */
+#define DAC_CR_TSEL2_0 0x00080000U /*!<Bit 0 */
+#define DAC_CR_TSEL2_1 0x00100000U /*!<Bit 1 */
+#define DAC_CR_TSEL2_2 0x00200000U /*!<Bit 2 */
+
+#define DAC_CR_WAVE2 0x00C00000U /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
+#define DAC_CR_WAVE2_0 0x00400000U /*!<Bit 0 */
+#define DAC_CR_WAVE2_1 0x00800000U /*!<Bit 1 */
+
+#define DAC_CR_MAMP2 0x0F000000U /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
+#define DAC_CR_MAMP2_0 0x01000000U /*!<Bit 0 */
+#define DAC_CR_MAMP2_1 0x02000000U /*!<Bit 1 */
+#define DAC_CR_MAMP2_2 0x04000000U /*!<Bit 2 */
+#define DAC_CR_MAMP2_3 0x08000000U /*!<Bit 3 */
+
+#define DAC_CR_DMAEN2 0x10000000U /*!<DAC channel2 DMA enabled */
+#define DAC_CR_DMAUDRIE2 0x20000000U /*!<DAC channel2 DMA underrun interrupt enable*/
+
+/***************** Bit definition for DAC_SWTRIGR register ******************/
+#define DAC_SWTRIGR_SWTRIG1 0x01U /*!<DAC channel1 software trigger */
+#define DAC_SWTRIGR_SWTRIG2 0x02U /*!<DAC channel2 software trigger */
+
+/***************** Bit definition for DAC_DHR12R1 register ******************/
+#define DAC_DHR12R1_DACC1DHR 0x0FFFU /*!<DAC channel1 12-bit Right aligned data */
+
+/***************** Bit definition for DAC_DHR12L1 register ******************/
+#define DAC_DHR12L1_DACC1DHR 0xFFF0U /*!<DAC channel1 12-bit Left aligned data */
+
+/****************** Bit definition for DAC_DHR8R1 register ******************/
+#define DAC_DHR8R1_DACC1DHR 0xFFU /*!<DAC channel1 8-bit Right aligned data */
+
+/***************** Bit definition for DAC_DHR12R2 register ******************/
+#define DAC_DHR12R2_DACC2DHR 0x0FFFU /*!<DAC channel2 12-bit Right aligned data */
+
+/***************** Bit definition for DAC_DHR12L2 register ******************/
+#define DAC_DHR12L2_DACC2DHR 0xFFF0U /*!<DAC channel2 12-bit Left aligned data */
+
+/****************** Bit definition for DAC_DHR8R2 register ******************/
+#define DAC_DHR8R2_DACC2DHR 0xFFU /*!<DAC channel2 8-bit Right aligned data */
+
+/***************** Bit definition for DAC_DHR12RD register ******************/
+#define DAC_DHR12RD_DACC1DHR 0x00000FFFU /*!<DAC channel1 12-bit Right aligned data */
+#define DAC_DHR12RD_DACC2DHR 0x0FFF0000U /*!<DAC channel2 12-bit Right aligned data */
+
+/***************** Bit definition for DAC_DHR12LD register ******************/
+#define DAC_DHR12LD_DACC1DHR 0x0000FFF0U /*!<DAC channel1 12-bit Left aligned data */
+#define DAC_DHR12LD_DACC2DHR 0xFFF00000U /*!<DAC channel2 12-bit Left aligned data */
+
+/****************** Bit definition for DAC_DHR8RD register ******************/
+#define DAC_DHR8RD_DACC1DHR 0x00FFU /*!<DAC channel1 8-bit Right aligned data */
+#define DAC_DHR8RD_DACC2DHR 0xFF00U /*!<DAC channel2 8-bit Right aligned data */
+
+/******************* Bit definition for DAC_DOR1 register *******************/
+#define DAC_DOR1_DACC1DOR 0x0FFFU /*!<DAC channel1 data output */
+
+/******************* Bit definition for DAC_DOR2 register *******************/
+#define DAC_DOR2_DACC2DOR 0x0FFFU /*!<DAC channel2 data output */
+
+/******************** Bit definition for DAC_SR register ********************/
+#define DAC_SR_DMAUDR1 0x00002000U /*!<DAC channel1 DMA underrun flag */
+#define DAC_SR_DMAUDR2 0x20000000U /*!<DAC channel2 DMA underrun flag */
+
+/******************************************************************************/
+/* */
+/* Debug MCU */
+/* */
+/******************************************************************************/
+
+/******************************************************************************/
+/* */
+/* DMA Controller */
+/* */
+/******************************************************************************/
+/******************** Bits definition for DMA_SxCR register *****************/
+#define DMA_SxCR_CHSEL 0x0E000000U
+#define DMA_SxCR_CHSEL_0 0x02000000U
+#define DMA_SxCR_CHSEL_1 0x04000000U
+#define DMA_SxCR_CHSEL_2 0x08000000U
+#define DMA_SxCR_MBURST 0x01800000U
+#define DMA_SxCR_MBURST_0 0x00800000U
+#define DMA_SxCR_MBURST_1 0x01000000U
+#define DMA_SxCR_PBURST 0x00600000U
+#define DMA_SxCR_PBURST_0 0x00200000U
+#define DMA_SxCR_PBURST_1 0x00400000U
+#define DMA_SxCR_CT 0x00080000U
+#define DMA_SxCR_DBM 0x00040000U
+#define DMA_SxCR_PL 0x00030000U
+#define DMA_SxCR_PL_0 0x00010000U
+#define DMA_SxCR_PL_1 0x00020000U
+#define DMA_SxCR_PINCOS 0x00008000U
+#define DMA_SxCR_MSIZE 0x00006000U
+#define DMA_SxCR_MSIZE_0 0x00002000U
+#define DMA_SxCR_MSIZE_1 0x00004000U
+#define DMA_SxCR_PSIZE 0x00001800U
+#define DMA_SxCR_PSIZE_0 0x00000800U
+#define DMA_SxCR_PSIZE_1 0x00001000U
+#define DMA_SxCR_MINC 0x00000400U
+#define DMA_SxCR_PINC 0x00000200U
+#define DMA_SxCR_CIRC 0x00000100U
+#define DMA_SxCR_DIR 0x000000C0U
+#define DMA_SxCR_DIR_0 0x00000040U
+#define DMA_SxCR_DIR_1 0x00000080U
+#define DMA_SxCR_PFCTRL 0x00000020U
+#define DMA_SxCR_TCIE 0x00000010U
+#define DMA_SxCR_HTIE 0x00000008U
+#define DMA_SxCR_TEIE 0x00000004U
+#define DMA_SxCR_DMEIE 0x00000002U
+#define DMA_SxCR_EN 0x00000001U
+
+/* Legacy defines */
+#define DMA_SxCR_ACK 0x00100000U
+
+/******************** Bits definition for DMA_SxCNDTR register **************/
+#define DMA_SxNDT 0x0000FFFFU
+#define DMA_SxNDT_0 0x00000001U
+#define DMA_SxNDT_1 0x00000002U
+#define DMA_SxNDT_2 0x00000004U
+#define DMA_SxNDT_3 0x00000008U
+#define DMA_SxNDT_4 0x00000010U
+#define DMA_SxNDT_5 0x00000020U
+#define DMA_SxNDT_6 0x00000040U
+#define DMA_SxNDT_7 0x00000080U
+#define DMA_SxNDT_8 0x00000100U
+#define DMA_SxNDT_9 0x00000200U
+#define DMA_SxNDT_10 0x00000400U
+#define DMA_SxNDT_11 0x00000800U
+#define DMA_SxNDT_12 0x00001000U
+#define DMA_SxNDT_13 0x00002000U
+#define DMA_SxNDT_14 0x00004000U
+#define DMA_SxNDT_15 0x00008000U
+
+/******************** Bits definition for DMA_SxFCR register ****************/
+#define DMA_SxFCR_FEIE 0x00000080U
+#define DMA_SxFCR_FS 0x00000038U
+#define DMA_SxFCR_FS_0 0x00000008U
+#define DMA_SxFCR_FS_1 0x00000010U
+#define DMA_SxFCR_FS_2 0x00000020U
+#define DMA_SxFCR_DMDIS 0x00000004U
+#define DMA_SxFCR_FTH 0x00000003U
+#define DMA_SxFCR_FTH_0 0x00000001U
+#define DMA_SxFCR_FTH_1 0x00000002U
+
+/******************** Bits definition for DMA_LISR register *****************/
+#define DMA_LISR_TCIF3 0x08000000U
+#define DMA_LISR_HTIF3 0x04000000U
+#define DMA_LISR_TEIF3 0x02000000U
+#define DMA_LISR_DMEIF3 0x01000000U
+#define DMA_LISR_FEIF3 0x00400000U
+#define DMA_LISR_TCIF2 0x00200000U
+#define DMA_LISR_HTIF2 0x00100000U
+#define DMA_LISR_TEIF2 0x00080000U
+#define DMA_LISR_DMEIF2 0x00040000U
+#define DMA_LISR_FEIF2 0x00010000U
+#define DMA_LISR_TCIF1 0x00000800U
+#define DMA_LISR_HTIF1 0x00000400U
+#define DMA_LISR_TEIF1 0x00000200U
+#define DMA_LISR_DMEIF1 0x00000100U
+#define DMA_LISR_FEIF1 0x00000040U
+#define DMA_LISR_TCIF0 0x00000020U
+#define DMA_LISR_HTIF0 0x00000010U
+#define DMA_LISR_TEIF0 0x00000008U
+#define DMA_LISR_DMEIF0 0x00000004U
+#define DMA_LISR_FEIF0 0x00000001U
+
+/******************** Bits definition for DMA_HISR register *****************/
+#define DMA_HISR_TCIF7 0x08000000U
+#define DMA_HISR_HTIF7 0x04000000U
+#define DMA_HISR_TEIF7 0x02000000U
+#define DMA_HISR_DMEIF7 0x01000000U
+#define DMA_HISR_FEIF7 0x00400000U
+#define DMA_HISR_TCIF6 0x00200000U
+#define DMA_HISR_HTIF6 0x00100000U
+#define DMA_HISR_TEIF6 0x00080000U
+#define DMA_HISR_DMEIF6 0x00040000U
+#define DMA_HISR_FEIF6 0x00010000U
+#define DMA_HISR_TCIF5 0x00000800U
+#define DMA_HISR_HTIF5 0x00000400U
+#define DMA_HISR_TEIF5 0x00000200U
+#define DMA_HISR_DMEIF5 0x00000100U
+#define DMA_HISR_FEIF5 0x00000040U
+#define DMA_HISR_TCIF4 0x00000020U
+#define DMA_HISR_HTIF4 0x00000010U
+#define DMA_HISR_TEIF4 0x00000008U
+#define DMA_HISR_DMEIF4 0x00000004U
+#define DMA_HISR_FEIF4 0x00000001U
+
+/******************** Bits definition for DMA_LIFCR register ****************/
+#define DMA_LIFCR_CTCIF3 0x08000000U
+#define DMA_LIFCR_CHTIF3 0x04000000U
+#define DMA_LIFCR_CTEIF3 0x02000000U
+#define DMA_LIFCR_CDMEIF3 0x01000000U
+#define DMA_LIFCR_CFEIF3 0x00400000U
+#define DMA_LIFCR_CTCIF2 0x00200000U
+#define DMA_LIFCR_CHTIF2 0x00100000U
+#define DMA_LIFCR_CTEIF2 0x00080000U
+#define DMA_LIFCR_CDMEIF2 0x00040000U
+#define DMA_LIFCR_CFEIF2 0x00010000U
+#define DMA_LIFCR_CTCIF1 0x00000800U
+#define DMA_LIFCR_CHTIF1 0x00000400U
+#define DMA_LIFCR_CTEIF1 0x00000200U
+#define DMA_LIFCR_CDMEIF1 0x00000100U
+#define DMA_LIFCR_CFEIF1 0x00000040U
+#define DMA_LIFCR_CTCIF0 0x00000020U
+#define DMA_LIFCR_CHTIF0 0x00000010U
+#define DMA_LIFCR_CTEIF0 0x00000008U
+#define DMA_LIFCR_CDMEIF0 0x00000004U
+#define DMA_LIFCR_CFEIF0 0x00000001U
+
+/******************** Bits definition for DMA_HIFCR register ****************/
+#define DMA_HIFCR_CTCIF7 0x08000000U
+#define DMA_HIFCR_CHTIF7 0x04000000U
+#define DMA_HIFCR_CTEIF7 0x02000000U
+#define DMA_HIFCR_CDMEIF7 0x01000000U
+#define DMA_HIFCR_CFEIF7 0x00400000U
+#define DMA_HIFCR_CTCIF6 0x00200000U
+#define DMA_HIFCR_CHTIF6 0x00100000U
+#define DMA_HIFCR_CTEIF6 0x00080000U
+#define DMA_HIFCR_CDMEIF6 0x00040000U
+#define DMA_HIFCR_CFEIF6 0x00010000U
+#define DMA_HIFCR_CTCIF5 0x00000800U
+#define DMA_HIFCR_CHTIF5 0x00000400U
+#define DMA_HIFCR_CTEIF5 0x00000200U
+#define DMA_HIFCR_CDMEIF5 0x00000100U
+#define DMA_HIFCR_CFEIF5 0x00000040U
+#define DMA_HIFCR_CTCIF4 0x00000020U
+#define DMA_HIFCR_CHTIF4 0x00000010U
+#define DMA_HIFCR_CTEIF4 0x00000008U
+#define DMA_HIFCR_CDMEIF4 0x00000004U
+#define DMA_HIFCR_CFEIF4 0x00000001U
+
+
+/******************************************************************************/
+/* */
+/* External Interrupt/Event Controller */
+/* */
+/******************************************************************************/
+/******************* Bit definition for EXTI_IMR register *******************/
+#define EXTI_IMR_MR0 0x00000001U /*!< Interrupt Mask on line 0 */
+#define EXTI_IMR_MR1 0x00000002U /*!< Interrupt Mask on line 1 */
+#define EXTI_IMR_MR2 0x00000004U /*!< Interrupt Mask on line 2 */
+#define EXTI_IMR_MR3 0x00000008U /*!< Interrupt Mask on line 3 */
+#define EXTI_IMR_MR4 0x00000010U /*!< Interrupt Mask on line 4 */
+#define EXTI_IMR_MR5 0x00000020U /*!< Interrupt Mask on line 5 */
+#define EXTI_IMR_MR6 0x00000040U /*!< Interrupt Mask on line 6 */
+#define EXTI_IMR_MR7 0x00000080U /*!< Interrupt Mask on line 7 */
+#define EXTI_IMR_MR8 0x00000100U /*!< Interrupt Mask on line 8 */
+#define EXTI_IMR_MR9 0x00000200U /*!< Interrupt Mask on line 9 */
+#define EXTI_IMR_MR10 0x00000400U /*!< Interrupt Mask on line 10 */
+#define EXTI_IMR_MR11 0x00000800U /*!< Interrupt Mask on line 11 */
+#define EXTI_IMR_MR12 0x00001000U /*!< Interrupt Mask on line 12 */
+#define EXTI_IMR_MR13 0x00002000U /*!< Interrupt Mask on line 13 */
+#define EXTI_IMR_MR14 0x00004000U /*!< Interrupt Mask on line 14 */
+#define EXTI_IMR_MR15 0x00008000U /*!< Interrupt Mask on line 15 */
+#define EXTI_IMR_MR16 0x00010000U /*!< Interrupt Mask on line 16 */
+#define EXTI_IMR_MR17 0x00020000U /*!< Interrupt Mask on line 17 */
+#define EXTI_IMR_MR18 0x00040000U /*!< Interrupt Mask on line 18 */
+#define EXTI_IMR_MR19 0x00080000U /*!< Interrupt Mask on line 19 */
+#define EXTI_IMR_MR20 0x00100000U /*!< Interrupt Mask on line 20 */
+#define EXTI_IMR_MR21 0x00200000U /*!< Interrupt Mask on line 21 */
+#define EXTI_IMR_MR22 0x00400000U /*!< Interrupt Mask on line 22 */
+
+/******************* Bit definition for EXTI_EMR register *******************/
+#define EXTI_EMR_MR0 0x00000001U /*!< Event Mask on line 0 */
+#define EXTI_EMR_MR1 0x00000002U /*!< Event Mask on line 1 */
+#define EXTI_EMR_MR2 0x00000004U /*!< Event Mask on line 2 */
+#define EXTI_EMR_MR3 0x00000008U /*!< Event Mask on line 3 */
+#define EXTI_EMR_MR4 0x00000010U /*!< Event Mask on line 4 */
+#define EXTI_EMR_MR5 0x00000020U /*!< Event Mask on line 5 */
+#define EXTI_EMR_MR6 0x00000040U /*!< Event Mask on line 6 */
+#define EXTI_EMR_MR7 0x00000080U /*!< Event Mask on line 7 */
+#define EXTI_EMR_MR8 0x00000100U /*!< Event Mask on line 8 */
+#define EXTI_EMR_MR9 0x00000200U /*!< Event Mask on line 9 */
+#define EXTI_EMR_MR10 0x00000400U /*!< Event Mask on line 10 */
+#define EXTI_EMR_MR11 0x00000800U /*!< Event Mask on line 11 */
+#define EXTI_EMR_MR12 0x00001000U /*!< Event Mask on line 12 */
+#define EXTI_EMR_MR13 0x00002000U /*!< Event Mask on line 13 */
+#define EXTI_EMR_MR14 0x00004000U /*!< Event Mask on line 14 */
+#define EXTI_EMR_MR15 0x00008000U /*!< Event Mask on line 15 */
+#define EXTI_EMR_MR16 0x00010000U /*!< Event Mask on line 16 */
+#define EXTI_EMR_MR17 0x00020000U /*!< Event Mask on line 17 */
+#define EXTI_EMR_MR18 0x00040000U /*!< Event Mask on line 18 */
+#define EXTI_EMR_MR19 0x00080000U /*!< Event Mask on line 19 */
+#define EXTI_EMR_MR20 0x00100000U /*!< Event Mask on line 20 */
+#define EXTI_EMR_MR21 0x00200000U /*!< Event Mask on line 21 */
+#define EXTI_EMR_MR22 0x00400000U /*!< Event Mask on line 22 */
+
+/****************** Bit definition for EXTI_RTSR register *******************/
+#define EXTI_RTSR_TR0 0x00000001U /*!< Rising trigger event configuration bit of line 0 */
+#define EXTI_RTSR_TR1 0x00000002U /*!< Rising trigger event configuration bit of line 1 */
+#define EXTI_RTSR_TR2 0x00000004U /*!< Rising trigger event configuration bit of line 2 */
+#define EXTI_RTSR_TR3 0x00000008U /*!< Rising trigger event configuration bit of line 3 */
+#define EXTI_RTSR_TR4 0x00000010U /*!< Rising trigger event configuration bit of line 4 */
+#define EXTI_RTSR_TR5 0x00000020U /*!< Rising trigger event configuration bit of line 5 */
+#define EXTI_RTSR_TR6 0x00000040U /*!< Rising trigger event configuration bit of line 6 */
+#define EXTI_RTSR_TR7 0x00000080U /*!< Rising trigger event configuration bit of line 7 */
+#define EXTI_RTSR_TR8 0x00000100U /*!< Rising trigger event configuration bit of line 8 */
+#define EXTI_RTSR_TR9 0x00000200U /*!< Rising trigger event configuration bit of line 9 */
+#define EXTI_RTSR_TR10 0x00000400U /*!< Rising trigger event configuration bit of line 10 */
+#define EXTI_RTSR_TR11 0x00000800U /*!< Rising trigger event configuration bit of line 11 */
+#define EXTI_RTSR_TR12 0x00001000U /*!< Rising trigger event configuration bit of line 12 */
+#define EXTI_RTSR_TR13 0x00002000U /*!< Rising trigger event configuration bit of line 13 */
+#define EXTI_RTSR_TR14 0x00004000U /*!< Rising trigger event configuration bit of line 14 */
+#define EXTI_RTSR_TR15 0x00008000U /*!< Rising trigger event configuration bit of line 15 */
+#define EXTI_RTSR_TR16 0x00010000U /*!< Rising trigger event configuration bit of line 16 */
+#define EXTI_RTSR_TR17 0x00020000U /*!< Rising trigger event configuration bit of line 17 */
+#define EXTI_RTSR_TR18 0x00040000U /*!< Rising trigger event configuration bit of line 18 */
+#define EXTI_RTSR_TR19 0x00080000U /*!< Rising trigger event configuration bit of line 19 */
+#define EXTI_RTSR_TR20 0x00100000U /*!< Rising trigger event configuration bit of line 20 */
+#define EXTI_RTSR_TR21 0x00200000U /*!< Rising trigger event configuration bit of line 21 */
+#define EXTI_RTSR_TR22 0x00400000U /*!< Rising trigger event configuration bit of line 22 */
+
+/****************** Bit definition for EXTI_FTSR register *******************/
+#define EXTI_FTSR_TR0 0x00000001U /*!< Falling trigger event configuration bit of line 0 */
+#define EXTI_FTSR_TR1 0x00000002U /*!< Falling trigger event configuration bit of line 1 */
+#define EXTI_FTSR_TR2 0x00000004U /*!< Falling trigger event configuration bit of line 2 */
+#define EXTI_FTSR_TR3 0x00000008U /*!< Falling trigger event configuration bit of line 3 */
+#define EXTI_FTSR_TR4 0x00000010U /*!< Falling trigger event configuration bit of line 4 */
+#define EXTI_FTSR_TR5 0x00000020U /*!< Falling trigger event configuration bit of line 5 */
+#define EXTI_FTSR_TR6 0x00000040U /*!< Falling trigger event configuration bit of line 6 */
+#define EXTI_FTSR_TR7 0x00000080U /*!< Falling trigger event configuration bit of line 7 */
+#define EXTI_FTSR_TR8 0x00000100U /*!< Falling trigger event configuration bit of line 8 */
+#define EXTI_FTSR_TR9 0x00000200U /*!< Falling trigger event configuration bit of line 9 */
+#define EXTI_FTSR_TR10 0x00000400U /*!< Falling trigger event configuration bit of line 10 */
+#define EXTI_FTSR_TR11 0x00000800U /*!< Falling trigger event configuration bit of line 11 */
+#define EXTI_FTSR_TR12 0x00001000U /*!< Falling trigger event configuration bit of line 12 */
+#define EXTI_FTSR_TR13 0x00002000U /*!< Falling trigger event configuration bit of line 13 */
+#define EXTI_FTSR_TR14 0x00004000U /*!< Falling trigger event configuration bit of line 14 */
+#define EXTI_FTSR_TR15 0x00008000U /*!< Falling trigger event configuration bit of line 15 */
+#define EXTI_FTSR_TR16 0x00010000U /*!< Falling trigger event configuration bit of line 16 */
+#define EXTI_FTSR_TR17 0x00020000U /*!< Falling trigger event configuration bit of line 17 */
+#define EXTI_FTSR_TR18 0x00040000U /*!< Falling trigger event configuration bit of line 18 */
+#define EXTI_FTSR_TR19 0x00080000U /*!< Falling trigger event configuration bit of line 19 */
+#define EXTI_FTSR_TR20 0x00100000U /*!< Falling trigger event configuration bit of line 20 */
+#define EXTI_FTSR_TR21 0x00200000U /*!< Falling trigger event configuration bit of line 21 */
+#define EXTI_FTSR_TR22 0x00400000U /*!< Falling trigger event configuration bit of line 22 */
+
+/****************** Bit definition for EXTI_SWIER register ******************/
+#define EXTI_SWIER_SWIER0 0x00000001U /*!< Software Interrupt on line 0 */
+#define EXTI_SWIER_SWIER1 0x00000002U /*!< Software Interrupt on line 1 */
+#define EXTI_SWIER_SWIER2 0x00000004U /*!< Software Interrupt on line 2 */
+#define EXTI_SWIER_SWIER3 0x00000008U /*!< Software Interrupt on line 3 */
+#define EXTI_SWIER_SWIER4 0x00000010U /*!< Software Interrupt on line 4 */
+#define EXTI_SWIER_SWIER5 0x00000020U /*!< Software Interrupt on line 5 */
+#define EXTI_SWIER_SWIER6 0x00000040U /*!< Software Interrupt on line 6 */
+#define EXTI_SWIER_SWIER7 0x00000080U /*!< Software Interrupt on line 7 */
+#define EXTI_SWIER_SWIER8 0x00000100U /*!< Software Interrupt on line 8 */
+#define EXTI_SWIER_SWIER9 0x00000200U /*!< Software Interrupt on line 9 */
+#define EXTI_SWIER_SWIER10 0x00000400U /*!< Software Interrupt on line 10 */
+#define EXTI_SWIER_SWIER11 0x00000800U /*!< Software Interrupt on line 11 */
+#define EXTI_SWIER_SWIER12 0x00001000U /*!< Software Interrupt on line 12 */
+#define EXTI_SWIER_SWIER13 0x00002000U /*!< Software Interrupt on line 13 */
+#define EXTI_SWIER_SWIER14 0x00004000U /*!< Software Interrupt on line 14 */
+#define EXTI_SWIER_SWIER15 0x00008000U /*!< Software Interrupt on line 15 */
+#define EXTI_SWIER_SWIER16 0x00010000U /*!< Software Interrupt on line 16 */
+#define EXTI_SWIER_SWIER17 0x00020000U /*!< Software Interrupt on line 17 */
+#define EXTI_SWIER_SWIER18 0x00040000U /*!< Software Interrupt on line 18 */
+#define EXTI_SWIER_SWIER19 0x00080000U /*!< Software Interrupt on line 19 */
+#define EXTI_SWIER_SWIER20 0x00100000U /*!< Software Interrupt on line 20 */
+#define EXTI_SWIER_SWIER21 0x00200000U /*!< Software Interrupt on line 21 */
+#define EXTI_SWIER_SWIER22 0x00400000U /*!< Software Interrupt on line 22 */
+
+/******************* Bit definition for EXTI_PR register ********************/
+#define EXTI_PR_PR0 0x00000001U /*!< Pending bit for line 0 */
+#define EXTI_PR_PR1 0x00000002U /*!< Pending bit for line 1 */
+#define EXTI_PR_PR2 0x00000004U /*!< Pending bit for line 2 */
+#define EXTI_PR_PR3 0x00000008U /*!< Pending bit for line 3 */
+#define EXTI_PR_PR4 0x00000010U /*!< Pending bit for line 4 */
+#define EXTI_PR_PR5 0x00000020U /*!< Pending bit for line 5 */
+#define EXTI_PR_PR6 0x00000040U /*!< Pending bit for line 6 */
+#define EXTI_PR_PR7 0x00000080U /*!< Pending bit for line 7 */
+#define EXTI_PR_PR8 0x00000100U /*!< Pending bit for line 8 */
+#define EXTI_PR_PR9 0x00000200U /*!< Pending bit for line 9 */
+#define EXTI_PR_PR10 0x00000400U /*!< Pending bit for line 10 */
+#define EXTI_PR_PR11 0x00000800U /*!< Pending bit for line 11 */
+#define EXTI_PR_PR12 0x00001000U /*!< Pending bit for line 12 */
+#define EXTI_PR_PR13 0x00002000U /*!< Pending bit for line 13 */
+#define EXTI_PR_PR14 0x00004000U /*!< Pending bit for line 14 */
+#define EXTI_PR_PR15 0x00008000U /*!< Pending bit for line 15 */
+#define EXTI_PR_PR16 0x00010000U /*!< Pending bit for line 16 */
+#define EXTI_PR_PR17 0x00020000U /*!< Pending bit for line 17 */
+#define EXTI_PR_PR18 0x00040000U /*!< Pending bit for line 18 */
+#define EXTI_PR_PR19 0x00080000U /*!< Pending bit for line 19 */
+#define EXTI_PR_PR20 0x00100000U /*!< Pending bit for line 20 */
+#define EXTI_PR_PR21 0x00200000U /*!< Pending bit for line 21 */
+#define EXTI_PR_PR22 0x00400000U /*!< Pending bit for line 22 */
+
+/******************************************************************************/
+/* */
+/* FLASH */
+/* */
+/******************************************************************************/
+/******************* Bits definition for FLASH_ACR register *****************/
+#define FLASH_ACR_LATENCY 0x0000000FU
+#define FLASH_ACR_LATENCY_0WS 0x00000000U
+#define FLASH_ACR_LATENCY_1WS 0x00000001U
+#define FLASH_ACR_LATENCY_2WS 0x00000002U
+#define FLASH_ACR_LATENCY_3WS 0x00000003U
+#define FLASH_ACR_LATENCY_4WS 0x00000004U
+#define FLASH_ACR_LATENCY_5WS 0x00000005U
+#define FLASH_ACR_LATENCY_6WS 0x00000006U
+#define FLASH_ACR_LATENCY_7WS 0x00000007U
+
+#define FLASH_ACR_PRFTEN 0x00000100U
+#define FLASH_ACR_ICEN 0x00000200U
+#define FLASH_ACR_DCEN 0x00000400U
+#define FLASH_ACR_ICRST 0x00000800U
+#define FLASH_ACR_DCRST 0x00001000U
+#define FLASH_ACR_BYTE0_ADDRESS 0x40023C00U
+#define FLASH_ACR_BYTE2_ADDRESS 0x40023C03U
+
+/******************* Bits definition for FLASH_SR register ******************/
+#define FLASH_SR_EOP 0x00000001U
+#define FLASH_SR_SOP 0x00000002U
+#define FLASH_SR_WRPERR 0x00000010U
+#define FLASH_SR_PGAERR 0x00000020U
+#define FLASH_SR_PGPERR 0x00000040U
+#define FLASH_SR_PGSERR 0x00000080U
+#define FLASH_SR_BSY 0x00010000U
+
+/******************* Bits definition for FLASH_CR register ******************/
+#define FLASH_CR_PG 0x00000001U
+#define FLASH_CR_SER 0x00000002U
+#define FLASH_CR_MER 0x00000004U
+#define FLASH_CR_SNB 0x000000F8U
+#define FLASH_CR_SNB_0 0x00000008U
+#define FLASH_CR_SNB_1 0x00000010U
+#define FLASH_CR_SNB_2 0x00000020U
+#define FLASH_CR_SNB_3 0x00000040U
+#define FLASH_CR_SNB_4 0x00000080U
+#define FLASH_CR_PSIZE 0x00000300U
+#define FLASH_CR_PSIZE_0 0x00000100U
+#define FLASH_CR_PSIZE_1 0x00000200U
+#define FLASH_CR_STRT 0x00010000U
+#define FLASH_CR_EOPIE 0x01000000U
+#define FLASH_CR_LOCK 0x80000000U
+
+/******************* Bits definition for FLASH_OPTCR register ***************/
+#define FLASH_OPTCR_OPTLOCK 0x00000001U
+#define FLASH_OPTCR_OPTSTRT 0x00000002U
+#define FLASH_OPTCR_BOR_LEV_0 0x00000004U
+#define FLASH_OPTCR_BOR_LEV_1 0x00000008U
+#define FLASH_OPTCR_BOR_LEV 0x0000000CU
+
+#define FLASH_OPTCR_WDG_SW 0x00000020U
+#define FLASH_OPTCR_nRST_STOP 0x00000040U
+#define FLASH_OPTCR_nRST_STDBY 0x00000080U
+#define FLASH_OPTCR_RDP 0x0000FF00U
+#define FLASH_OPTCR_RDP_0 0x00000100U
+#define FLASH_OPTCR_RDP_1 0x00000200U
+#define FLASH_OPTCR_RDP_2 0x00000400U
+#define FLASH_OPTCR_RDP_3 0x00000800U
+#define FLASH_OPTCR_RDP_4 0x00001000U
+#define FLASH_OPTCR_RDP_5 0x00002000U
+#define FLASH_OPTCR_RDP_6 0x00004000U
+#define FLASH_OPTCR_RDP_7 0x00008000U
+#define FLASH_OPTCR_nWRP 0x0FFF0000U
+#define FLASH_OPTCR_nWRP_0 0x00010000U
+#define FLASH_OPTCR_nWRP_1 0x00020000U
+#define FLASH_OPTCR_nWRP_2 0x00040000U
+#define FLASH_OPTCR_nWRP_3 0x00080000U
+#define FLASH_OPTCR_nWRP_4 0x00100000U
+#define FLASH_OPTCR_nWRP_5 0x00200000U
+#define FLASH_OPTCR_nWRP_6 0x00400000U
+#define FLASH_OPTCR_nWRP_7 0x00800000U
+#define FLASH_OPTCR_nWRP_8 0x01000000U
+#define FLASH_OPTCR_nWRP_9 0x02000000U
+#define FLASH_OPTCR_nWRP_10 0x04000000U
+#define FLASH_OPTCR_nWRP_11 0x08000000U
+
+/****************** Bits definition for FLASH_OPTCR1 register ***************/
+#define FLASH_OPTCR1_nWRP 0x0FFF0000U
+#define FLASH_OPTCR1_nWRP_0 0x00010000U
+#define FLASH_OPTCR1_nWRP_1 0x00020000U
+#define FLASH_OPTCR1_nWRP_2 0x00040000U
+#define FLASH_OPTCR1_nWRP_3 0x00080000U
+#define FLASH_OPTCR1_nWRP_4 0x00100000U
+#define FLASH_OPTCR1_nWRP_5 0x00200000U
+#define FLASH_OPTCR1_nWRP_6 0x00400000U
+#define FLASH_OPTCR1_nWRP_7 0x00800000U
+#define FLASH_OPTCR1_nWRP_8 0x01000000U
+#define FLASH_OPTCR1_nWRP_9 0x02000000U
+#define FLASH_OPTCR1_nWRP_10 0x04000000U
+#define FLASH_OPTCR1_nWRP_11 0x08000000U
+
+/******************************************************************************/
+/* */
+/* Flexible Static Memory Controller */
+/* */
+/******************************************************************************/
+/****************** Bit definition for FSMC_BCR1 register *******************/
+#define FSMC_BCR1_MBKEN 0x00000001U /*!<Memory bank enable bit */
+#define FSMC_BCR1_MUXEN 0x00000002U /*!<Address/data multiplexing enable bit */
+
+#define FSMC_BCR1_MTYP 0x0000000CU /*!<MTYP[1:0] bits (Memory type) */
+#define FSMC_BCR1_MTYP_0 0x00000004U /*!<Bit 0 */
+#define FSMC_BCR1_MTYP_1 0x00000008U /*!<Bit 1 */
+
+#define FSMC_BCR1_MWID 0x00000030U /*!<MWID[1:0] bits (Memory data bus width) */
+#define FSMC_BCR1_MWID_0 0x00000010U /*!<Bit 0 */
+#define FSMC_BCR1_MWID_1 0x00000020U /*!<Bit 1 */
+
+#define FSMC_BCR1_FACCEN 0x00000040U /*!<Flash access enable */
+#define FSMC_BCR1_BURSTEN 0x00000100U /*!<Burst enable bit */
+#define FSMC_BCR1_WAITPOL 0x00000200U /*!<Wait signal polarity bit */
+#define FSMC_BCR1_WRAPMOD 0x00000400U /*!<Wrapped burst mode support */
+#define FSMC_BCR1_WAITCFG 0x00000800U /*!<Wait timing configuration */
+#define FSMC_BCR1_WREN 0x00001000U /*!<Write enable bit */
+#define FSMC_BCR1_WAITEN 0x00002000U /*!<Wait enable bit */
+#define FSMC_BCR1_EXTMOD 0x00004000U /*!<Extended mode enable */
+#define FSMC_BCR1_ASYNCWAIT 0x00008000U /*!<Asynchronous wait */
+#define FSMC_BCR1_CPSIZE 0x00070000U /*!<CRAM page size */
+#define FSMC_BCR1_CPSIZE_0 0x00010000U /*!<Bit 0 */
+#define FSMC_BCR1_CPSIZE_1 0x00020000U /*!<Bit 1 */
+#define FSMC_BCR1_CPSIZE_2 0x00040000U /*!<Bit 2 */
+#define FSMC_BCR1_CBURSTRW 0x00080000U /*!<Write burst enable */
+
+/****************** Bit definition for FSMC_BCR2 register *******************/
+#define FSMC_BCR2_MBKEN 0x00000001U /*!<Memory bank enable bit */
+#define FSMC_BCR2_MUXEN 0x00000002U /*!<Address/data multiplexing enable bit */
+
+#define FSMC_BCR2_MTYP 0x0000000CU /*!<MTYP[1:0] bits (Memory type) */
+#define FSMC_BCR2_MTYP_0 0x00000004U /*!<Bit 0 */
+#define FSMC_BCR2_MTYP_1 0x00000008U /*!<Bit 1 */
+
+#define FSMC_BCR2_MWID 0x00000030U /*!<MWID[1:0] bits (Memory data bus width) */
+#define FSMC_BCR2_MWID_0 0x00000010U /*!<Bit 0 */
+#define FSMC_BCR2_MWID_1 0x00000020U /*!<Bit 1 */
+
+#define FSMC_BCR2_FACCEN 0x00000040U /*!<Flash access enable */
+#define FSMC_BCR2_BURSTEN 0x00000100U /*!<Burst enable bit */
+#define FSMC_BCR2_WAITPOL 0x00000200U /*!<Wait signal polarity bit */
+#define FSMC_BCR2_WRAPMOD 0x00000400U /*!<Wrapped burst mode support */
+#define FSMC_BCR2_WAITCFG 0x00000800U /*!<Wait timing configuration */
+#define FSMC_BCR2_WREN 0x00001000U /*!<Write enable bit */
+#define FSMC_BCR2_WAITEN 0x00002000U /*!<Wait enable bit */
+#define FSMC_BCR2_EXTMOD 0x00004000U /*!<Extended mode enable */
+#define FSMC_BCR2_ASYNCWAIT 0x00008000U /*!<Asynchronous wait */
+#define FSMC_BCR2_CPSIZE 0x00070000U /*!<CRAM page size */
+#define FSMC_BCR2_CPSIZE_0 0x00010000U /*!<Bit 0 */
+#define FSMC_BCR2_CPSIZE_1 0x00020000U /*!<Bit 1 */
+#define FSMC_BCR2_CPSIZE_2 0x00040000U /*!<Bit 2 */
+#define FSMC_BCR2_CBURSTRW 0x00080000U /*!<Write burst enable */
+
+/****************** Bit definition for FSMC_BCR3 register *******************/
+#define FSMC_BCR3_MBKEN 0x00000001U /*!<Memory bank enable bit */
+#define FSMC_BCR3_MUXEN 0x00000002U /*!<Address/data multiplexing enable bit */
+
+#define FSMC_BCR3_MTYP 0x0000000CU /*!<MTYP[1:0] bits (Memory type) */
+#define FSMC_BCR3_MTYP_0 0x00000004U /*!<Bit 0 */
+#define FSMC_BCR3_MTYP_1 0x00000008U /*!<Bit 1 */
+
+#define FSMC_BCR3_MWID 0x00000030U /*!<MWID[1:0] bits (Memory data bus width) */
+#define FSMC_BCR3_MWID_0 0x00000010U /*!<Bit 0 */
+#define FSMC_BCR3_MWID_1 0x00000020U /*!<Bit 1 */
+
+#define FSMC_BCR3_FACCEN 0x00000040U /*!<Flash access enable */
+#define FSMC_BCR3_BURSTEN 0x00000100U /*!<Burst enable bit */
+#define FSMC_BCR3_WAITPOL 0x00000200U /*!<Wait signal polarity bit */
+#define FSMC_BCR3_WRAPMOD 0x00000400U /*!<Wrapped burst mode support */
+#define FSMC_BCR3_WAITCFG 0x00000800U /*!<Wait timing configuration */
+#define FSMC_BCR3_WREN 0x00001000U /*!<Write enable bit */
+#define FSMC_BCR3_WAITEN 0x00002000U /*!<Wait enable bit */
+#define FSMC_BCR3_EXTMOD 0x00004000U /*!<Extended mode enable */
+#define FSMC_BCR3_ASYNCWAIT 0x00008000U /*!<Asynchronous wait */
+#define FSMC_BCR3_CPSIZE 0x00070000U /*!<CRAM page size */
+#define FSMC_BCR3_CPSIZE_0 0x00010000U /*!<Bit 0 */
+#define FSMC_BCR3_CPSIZE_1 0x00020000U /*!<Bit 1 */
+#define FSMC_BCR3_CPSIZE_2 0x00040000U /*!<Bit 2 */
+#define FSMC_BCR3_CBURSTRW 0x00080000U /*!<Write burst enable */
+
+/****************** Bit definition for FSMC_BCR4 register *******************/
+#define FSMC_BCR4_MBKEN 0x00000001U /*!<Memory bank enable bit */
+#define FSMC_BCR4_MUXEN 0x00000002U /*!<Address/data multiplexing enable bit */
+
+#define FSMC_BCR4_MTYP 0x0000000CU /*!<MTYP[1:0] bits (Memory type) */
+#define FSMC_BCR4_MTYP_0 0x00000004U /*!<Bit 0 */
+#define FSMC_BCR4_MTYP_1 0x00000008U /*!<Bit 1 */
+
+#define FSMC_BCR4_MWID 0x00000030U /*!<MWID[1:0] bits (Memory data bus width) */
+#define FSMC_BCR4_MWID_0 0x00000010U /*!<Bit 0 */
+#define FSMC_BCR4_MWID_1 0x00000020U /*!<Bit 1 */
+
+#define FSMC_BCR4_FACCEN 0x00000040U /*!<Flash access enable */
+#define FSMC_BCR4_BURSTEN 0x00000100U /*!<Burst enable bit */
+#define FSMC_BCR4_WAITPOL 0x00000200U /*!<Wait signal polarity bit */
+#define FSMC_BCR4_WRAPMOD 0x00000400U /*!<Wrapped burst mode support */
+#define FSMC_BCR4_WAITCFG 0x00000800U /*!<Wait timing configuration */
+#define FSMC_BCR4_WREN 0x00001000U /*!<Write enable bit */
+#define FSMC_BCR4_WAITEN 0x00002000U /*!<Wait enable bit */
+#define FSMC_BCR4_EXTMOD 0x00004000U /*!<Extended mode enable */
+#define FSMC_BCR4_ASYNCWAIT 0x00008000U /*!<Asynchronous wait */
+#define FSMC_BCR4_CPSIZE 0x00070000U /*!<CRAM page size */
+#define FSMC_BCR4_CPSIZE_0 0x00010000U /*!<Bit 0 */
+#define FSMC_BCR4_CPSIZE_1 0x00020000U /*!<Bit 1 */
+#define FSMC_BCR4_CPSIZE_2 0x00040000U /*!<Bit 2 */
+#define FSMC_BCR4_CBURSTRW 0x00080000U /*!<Write burst enable */
+
+/****************** Bit definition for FSMC_BTR1 register ******************/
+#define FSMC_BTR1_ADDSET 0x0000000FU /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FSMC_BTR1_ADDSET_0 0x00000001U /*!<Bit 0 */
+#define FSMC_BTR1_ADDSET_1 0x00000002U /*!<Bit 1 */
+#define FSMC_BTR1_ADDSET_2 0x00000004U /*!<Bit 2 */
+#define FSMC_BTR1_ADDSET_3 0x00000008U /*!<Bit 3 */
+
+#define FSMC_BTR1_ADDHLD 0x000000F0U /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FSMC_BTR1_ADDHLD_0 0x00000010U /*!<Bit 0 */
+#define FSMC_BTR1_ADDHLD_1 0x00000020U /*!<Bit 1 */
+#define FSMC_BTR1_ADDHLD_2 0x00000040U /*!<Bit 2 */
+#define FSMC_BTR1_ADDHLD_3 0x00000080U /*!<Bit 3 */
+
+#define FSMC_BTR1_DATAST 0x0000FF00U /*!<DATAST [7:0] bits (Data-phase duration) */
+#define FSMC_BTR1_DATAST_0 0x00000100U /*!<Bit 0 */
+#define FSMC_BTR1_DATAST_1 0x00000200U /*!<Bit 1 */
+#define FSMC_BTR1_DATAST_2 0x00000400U /*!<Bit 2 */
+#define FSMC_BTR1_DATAST_3 0x00000800U /*!<Bit 3 */
+#define FSMC_BTR1_DATAST_4 0x00001000U /*!<Bit 4 */
+#define FSMC_BTR1_DATAST_5 0x00002000U /*!<Bit 5 */
+#define FSMC_BTR1_DATAST_6 0x00004000U /*!<Bit 6 */
+#define FSMC_BTR1_DATAST_7 0x00008000U /*!<Bit 7 */
+
+#define FSMC_BTR1_BUSTURN 0x000F0000U /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define FSMC_BTR1_BUSTURN_0 0x00010000U /*!<Bit 0 */
+#define FSMC_BTR1_BUSTURN_1 0x00020000U /*!<Bit 1 */
+#define FSMC_BTR1_BUSTURN_2 0x00040000U /*!<Bit 2 */
+#define FSMC_BTR1_BUSTURN_3 0x00080000U /*!<Bit 3 */
+
+#define FSMC_BTR1_CLKDIV 0x00F00000U /*!<CLKDIV[3:0] bits (Clock divide ratio) */
+#define FSMC_BTR1_CLKDIV_0 0x00100000U /*!<Bit 0 */
+#define FSMC_BTR1_CLKDIV_1 0x00200000U /*!<Bit 1 */
+#define FSMC_BTR1_CLKDIV_2 0x00400000U /*!<Bit 2 */
+#define FSMC_BTR1_CLKDIV_3 0x00800000U /*!<Bit 3 */
+
+#define FSMC_BTR1_DATLAT 0x0F000000U /*!<DATLA[3:0] bits (Data latency) */
+#define FSMC_BTR1_DATLAT_0 0x01000000U /*!<Bit 0 */
+#define FSMC_BTR1_DATLAT_1 0x02000000U /*!<Bit 1 */
+#define FSMC_BTR1_DATLAT_2 0x04000000U /*!<Bit 2 */
+#define FSMC_BTR1_DATLAT_3 0x08000000U /*!<Bit 3 */
+
+#define FSMC_BTR1_ACCMOD 0x30000000U /*!<ACCMOD[1:0] bits (Access mode) */
+#define FSMC_BTR1_ACCMOD_0 0x10000000U /*!<Bit 0 */
+#define FSMC_BTR1_ACCMOD_1 0x20000000U /*!<Bit 1 */
+
+/****************** Bit definition for FSMC_BTR2 register *******************/
+#define FSMC_BTR2_ADDSET 0x0000000FU /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FSMC_BTR2_ADDSET_0 0x00000001U /*!<Bit 0 */
+#define FSMC_BTR2_ADDSET_1 0x00000002U /*!<Bit 1 */
+#define FSMC_BTR2_ADDSET_2 0x00000004U /*!<Bit 2 */
+#define FSMC_BTR2_ADDSET_3 0x00000008U /*!<Bit 3 */
+
+#define FSMC_BTR2_ADDHLD 0x000000F0U /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FSMC_BTR2_ADDHLD_0 0x00000010U /*!<Bit 0 */
+#define FSMC_BTR2_ADDHLD_1 0x00000020U /*!<Bit 1 */
+#define FSMC_BTR2_ADDHLD_2 0x00000040U /*!<Bit 2 */
+#define FSMC_BTR2_ADDHLD_3 0x00000080U /*!<Bit 3 */
+
+#define FSMC_BTR2_DATAST 0x0000FF00U /*!<DATAST [7:0] bits (Data-phase duration) */
+#define FSMC_BTR2_DATAST_0 0x00000100U /*!<Bit 0 */
+#define FSMC_BTR2_DATAST_1 0x00000200U /*!<Bit 1 */
+#define FSMC_BTR2_DATAST_2 0x00000400U /*!<Bit 2 */
+#define FSMC_BTR2_DATAST_3 0x00000800U /*!<Bit 3 */
+#define FSMC_BTR2_DATAST_4 0x00001000U /*!<Bit 4 */
+#define FSMC_BTR2_DATAST_5 0x00002000U /*!<Bit 5 */
+#define FSMC_BTR2_DATAST_6 0x00004000U /*!<Bit 6 */
+#define FSMC_BTR2_DATAST_7 0x00008000U /*!<Bit 7 */
+
+#define FSMC_BTR2_BUSTURN 0x000F0000U /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define FSMC_BTR2_BUSTURN_0 0x00010000U /*!<Bit 0 */
+#define FSMC_BTR2_BUSTURN_1 0x00020000U /*!<Bit 1 */
+#define FSMC_BTR2_BUSTURN_2 0x00040000U /*!<Bit 2 */
+#define FSMC_BTR2_BUSTURN_3 0x00080000U /*!<Bit 3 */
+
+#define FSMC_BTR2_CLKDIV 0x00F00000U /*!<CLKDIV[3:0] bits (Clock divide ratio) */
+#define FSMC_BTR2_CLKDIV_0 0x00100000U /*!<Bit 0 */
+#define FSMC_BTR2_CLKDIV_1 0x00200000U /*!<Bit 1 */
+#define FSMC_BTR2_CLKDIV_2 0x00400000U /*!<Bit 2 */
+#define FSMC_BTR2_CLKDIV_3 0x00800000U /*!<Bit 3 */
+
+#define FSMC_BTR2_DATLAT 0x0F000000U /*!<DATLA[3:0] bits (Data latency) */
+#define FSMC_BTR2_DATLAT_0 0x01000000U /*!<Bit 0 */
+#define FSMC_BTR2_DATLAT_1 0x02000000U /*!<Bit 1 */
+#define FSMC_BTR2_DATLAT_2 0x04000000U /*!<Bit 2 */
+#define FSMC_BTR2_DATLAT_3 0x08000000U /*!<Bit 3 */
+
+#define FSMC_BTR2_ACCMOD 0x30000000U /*!<ACCMOD[1:0] bits (Access mode) */
+#define FSMC_BTR2_ACCMOD_0 0x10000000U /*!<Bit 0 */
+#define FSMC_BTR2_ACCMOD_1 0x20000000U /*!<Bit 1 */
+
+/******************* Bit definition for FSMC_BTR3 register *******************/
+#define FSMC_BTR3_ADDSET 0x0000000FU /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FSMC_BTR3_ADDSET_0 0x00000001U /*!<Bit 0 */
+#define FSMC_BTR3_ADDSET_1 0x00000002U /*!<Bit 1 */
+#define FSMC_BTR3_ADDSET_2 0x00000004U /*!<Bit 2 */
+#define FSMC_BTR3_ADDSET_3 0x00000008U /*!<Bit 3 */
+
+#define FSMC_BTR3_ADDHLD 0x000000F0U /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FSMC_BTR3_ADDHLD_0 0x00000010U /*!<Bit 0 */
+#define FSMC_BTR3_ADDHLD_1 0x00000020U /*!<Bit 1 */
+#define FSMC_BTR3_ADDHLD_2 0x00000040U /*!<Bit 2 */
+#define FSMC_BTR3_ADDHLD_3 0x00000080U /*!<Bit 3 */
+
+#define FSMC_BTR3_DATAST 0x0000FF00U /*!<DATAST [7:0] bits (Data-phase duration) */
+#define FSMC_BTR3_DATAST_0 0x00000100U /*!<Bit 0 */
+#define FSMC_BTR3_DATAST_1 0x00000200U /*!<Bit 1 */
+#define FSMC_BTR3_DATAST_2 0x00000400U /*!<Bit 2 */
+#define FSMC_BTR3_DATAST_3 0x00000800U /*!<Bit 3 */
+#define FSMC_BTR3_DATAST_4 0x00001000U /*!<Bit 4 */
+#define FSMC_BTR3_DATAST_5 0x00002000U /*!<Bit 5 */
+#define FSMC_BTR3_DATAST_6 0x00004000U /*!<Bit 6 */
+#define FSMC_BTR3_DATAST_7 0x00008000U /*!<Bit 7 */
+
+#define FSMC_BTR3_BUSTURN 0x000F0000U /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define FSMC_BTR3_BUSTURN_0 0x00010000U /*!<Bit 0 */
+#define FSMC_BTR3_BUSTURN_1 0x00020000U /*!<Bit 1 */
+#define FSMC_BTR3_BUSTURN_2 0x00040000U /*!<Bit 2 */
+#define FSMC_BTR3_BUSTURN_3 0x00080000U /*!<Bit 3 */
+
+#define FSMC_BTR3_CLKDIV 0x00F00000U /*!<CLKDIV[3:0] bits (Clock divide ratio) */
+#define FSMC_BTR3_CLKDIV_0 0x00100000U /*!<Bit 0 */
+#define FSMC_BTR3_CLKDIV_1 0x00200000U /*!<Bit 1 */
+#define FSMC_BTR3_CLKDIV_2 0x00400000U /*!<Bit 2 */
+#define FSMC_BTR3_CLKDIV_3 0x00800000U /*!<Bit 3 */
+
+#define FSMC_BTR3_DATLAT 0x0F000000U /*!<DATLA[3:0] bits (Data latency) */
+#define FSMC_BTR3_DATLAT_0 0x01000000U /*!<Bit 0 */
+#define FSMC_BTR3_DATLAT_1 0x02000000U /*!<Bit 1 */
+#define FSMC_BTR3_DATLAT_2 0x04000000U /*!<Bit 2 */
+#define FSMC_BTR3_DATLAT_3 0x08000000U /*!<Bit 3 */
+
+#define FSMC_BTR3_ACCMOD 0x30000000U /*!<ACCMOD[1:0] bits (Access mode) */
+#define FSMC_BTR3_ACCMOD_0 0x10000000U /*!<Bit 0 */
+#define FSMC_BTR3_ACCMOD_1 0x20000000U /*!<Bit 1 */
+
+/****************** Bit definition for FSMC_BTR4 register *******************/
+#define FSMC_BTR4_ADDSET 0x0000000FU /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FSMC_BTR4_ADDSET_0 0x00000001U /*!<Bit 0 */
+#define FSMC_BTR4_ADDSET_1 0x00000002U /*!<Bit 1 */
+#define FSMC_BTR4_ADDSET_2 0x00000004U /*!<Bit 2 */
+#define FSMC_BTR4_ADDSET_3 0x00000008U /*!<Bit 3 */
+
+#define FSMC_BTR4_ADDHLD 0x000000F0U /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FSMC_BTR4_ADDHLD_0 0x00000010U /*!<Bit 0 */
+#define FSMC_BTR4_ADDHLD_1 0x00000020U /*!<Bit 1 */
+#define FSMC_BTR4_ADDHLD_2 0x00000040U /*!<Bit 2 */
+#define FSMC_BTR4_ADDHLD_3 0x00000080U /*!<Bit 3 */
+
+#define FSMC_BTR4_DATAST 0x0000FF00U /*!<DATAST [7:0] bits (Data-phase duration) */
+#define FSMC_BTR4_DATAST_0 0x00000100U /*!<Bit 0 */
+#define FSMC_BTR4_DATAST_1 0x00000200U /*!<Bit 1 */
+#define FSMC_BTR4_DATAST_2 0x00000400U /*!<Bit 2 */
+#define FSMC_BTR4_DATAST_3 0x00000800U /*!<Bit 3 */
+#define FSMC_BTR4_DATAST_4 0x00001000U /*!<Bit 4 */
+#define FSMC_BTR4_DATAST_5 0x00002000U /*!<Bit 5 */
+#define FSMC_BTR4_DATAST_6 0x00004000U /*!<Bit 6 */
+#define FSMC_BTR4_DATAST_7 0x00008000U /*!<Bit 7 */
+
+#define FSMC_BTR4_BUSTURN 0x000F0000U /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define FSMC_BTR4_BUSTURN_0 0x00010000U /*!<Bit 0 */
+#define FSMC_BTR4_BUSTURN_1 0x00020000U /*!<Bit 1 */
+#define FSMC_BTR4_BUSTURN_2 0x00040000U /*!<Bit 2 */
+#define FSMC_BTR4_BUSTURN_3 0x00080000U /*!<Bit 3 */
+
+#define FSMC_BTR4_CLKDIV 0x00F00000U /*!<CLKDIV[3:0] bits (Clock divide ratio) */
+#define FSMC_BTR4_CLKDIV_0 0x00100000U /*!<Bit 0 */
+#define FSMC_BTR4_CLKDIV_1 0x00200000U /*!<Bit 1 */
+#define FSMC_BTR4_CLKDIV_2 0x00400000U /*!<Bit 2 */
+#define FSMC_BTR4_CLKDIV_3 0x00800000U /*!<Bit 3 */
+
+#define FSMC_BTR4_DATLAT 0x0F000000U /*!<DATLA[3:0] bits (Data latency) */
+#define FSMC_BTR4_DATLAT_0 0x01000000U /*!<Bit 0 */
+#define FSMC_BTR4_DATLAT_1 0x02000000U /*!<Bit 1 */
+#define FSMC_BTR4_DATLAT_2 0x04000000U /*!<Bit 2 */
+#define FSMC_BTR4_DATLAT_3 0x08000000U /*!<Bit 3 */
+
+#define FSMC_BTR4_ACCMOD 0x30000000U /*!<ACCMOD[1:0] bits (Access mode) */
+#define FSMC_BTR4_ACCMOD_0 0x10000000U /*!<Bit 0 */
+#define FSMC_BTR4_ACCMOD_1 0x20000000U /*!<Bit 1 */
+
+/****************** Bit definition for FSMC_BWTR1 register ******************/
+#define FSMC_BWTR1_ADDSET 0x0000000FU /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FSMC_BWTR1_ADDSET_0 0x00000001U /*!<Bit 0 */
+#define FSMC_BWTR1_ADDSET_1 0x00000002U /*!<Bit 1 */
+#define FSMC_BWTR1_ADDSET_2 0x00000004U /*!<Bit 2 */
+#define FSMC_BWTR1_ADDSET_3 0x00000008U /*!<Bit 3 */
+
+#define FSMC_BWTR1_ADDHLD 0x000000F0U /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FSMC_BWTR1_ADDHLD_0 0x00000010U /*!<Bit 0 */
+#define FSMC_BWTR1_ADDHLD_1 0x00000020U /*!<Bit 1 */
+#define FSMC_BWTR1_ADDHLD_2 0x00000040U /*!<Bit 2 */
+#define FSMC_BWTR1_ADDHLD_3 0x00000080U /*!<Bit 3 */
+
+#define FSMC_BWTR1_DATAST 0x0000FF00U /*!<DATAST [7:0] bits (Data-phase duration) */
+#define FSMC_BWTR1_DATAST_0 0x00000100U /*!<Bit 0 */
+#define FSMC_BWTR1_DATAST_1 0x00000200U /*!<Bit 1 */
+#define FSMC_BWTR1_DATAST_2 0x00000400U /*!<Bit 2 */
+#define FSMC_BWTR1_DATAST_3 0x00000800U /*!<Bit 3 */
+#define FSMC_BWTR1_DATAST_4 0x00001000U /*!<Bit 4 */
+#define FSMC_BWTR1_DATAST_5 0x00002000U /*!<Bit 5 */
+#define FSMC_BWTR1_DATAST_6 0x00004000U /*!<Bit 6 */
+#define FSMC_BWTR1_DATAST_7 0x00008000U /*!<Bit 7 */
+
+#define FSMC_BWTR1_BUSTURN 0x000F0000U /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
+#define FSMC_BWTR1_BUSTURN_0 0x00010000U /*!<Bit 0 */
+#define FSMC_BWTR1_BUSTURN_1 0x00020000U /*!<Bit 1 */
+#define FSMC_BWTR1_BUSTURN_2 0x00040000U /*!<Bit 2 */
+#define FSMC_BWTR1_BUSTURN_3 0x00080000U /*!<Bit 3 */
+
+#define FSMC_BWTR1_ACCMOD 0x30000000U /*!<ACCMOD[1:0] bits (Access mode) */
+#define FSMC_BWTR1_ACCMOD_0 0x10000000U /*!<Bit 0 */
+#define FSMC_BWTR1_ACCMOD_1 0x20000000U /*!<Bit 1 */
+
+/****************** Bit definition for FSMC_BWTR2 register ******************/
+#define FSMC_BWTR2_ADDSET 0x0000000FU /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FSMC_BWTR2_ADDSET_0 0x00000001U /*!<Bit 0 */
+#define FSMC_BWTR2_ADDSET_1 0x00000002U /*!<Bit 1 */
+#define FSMC_BWTR2_ADDSET_2 0x00000004U /*!<Bit 2 */
+#define FSMC_BWTR2_ADDSET_3 0x00000008U /*!<Bit 3 */
+
+#define FSMC_BWTR2_ADDHLD 0x000000F0U /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FSMC_BWTR2_ADDHLD_0 0x00000010U /*!<Bit 0 */
+#define FSMC_BWTR2_ADDHLD_1 0x00000020U /*!<Bit 1 */
+#define FSMC_BWTR2_ADDHLD_2 0x00000040U /*!<Bit 2 */
+#define FSMC_BWTR2_ADDHLD_3 0x00000080U /*!<Bit 3 */
+
+#define FSMC_BWTR2_DATAST 0x0000FF00U /*!<DATAST [7:0] bits (Data-phase duration) */
+#define FSMC_BWTR2_DATAST_0 0x00000100U /*!<Bit 0 */
+#define FSMC_BWTR2_DATAST_1 0x00000200U /*!<Bit 1 */
+#define FSMC_BWTR2_DATAST_2 0x00000400U /*!<Bit 2 */
+#define FSMC_BWTR2_DATAST_3 0x00000800U /*!<Bit 3 */
+#define FSMC_BWTR2_DATAST_4 0x00001000U /*!<Bit 4 */
+#define FSMC_BWTR2_DATAST_5 0x00002000U /*!<Bit 5 */
+#define FSMC_BWTR2_DATAST_6 0x00004000U /*!<Bit 6 */
+#define FSMC_BWTR2_DATAST_7 0x00008000U /*!<Bit 7 */
+
+#define FSMC_BWTR2_BUSTURN 0x000F0000U /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
+#define FSMC_BWTR2_BUSTURN_0 0x00010000U /*!<Bit 0 */
+#define FSMC_BWTR2_BUSTURN_1 0x00020000U /*!<Bit 1 */
+#define FSMC_BWTR2_BUSTURN_2 0x00040000U /*!<Bit 2 */
+#define FSMC_BWTR2_BUSTURN_3 0x00080000U /*!<Bit 3 */
+
+#define FSMC_BWTR2_ACCMOD 0x30000000U /*!<ACCMOD[1:0] bits (Access mode) */
+#define FSMC_BWTR2_ACCMOD_0 0x10000000U /*!<Bit 0 */
+#define FSMC_BWTR2_ACCMOD_1 0x20000000U /*!<Bit 1 */
+
+/****************** Bit definition for FSMC_BWTR3 register ******************/
+#define FSMC_BWTR3_ADDSET 0x0000000FU /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FSMC_BWTR3_ADDSET_0 0x00000001U /*!<Bit 0 */
+#define FSMC_BWTR3_ADDSET_1 0x00000002U /*!<Bit 1 */
+#define FSMC_BWTR3_ADDSET_2 0x00000004U /*!<Bit 2 */
+#define FSMC_BWTR3_ADDSET_3 0x00000008U /*!<Bit 3 */
+
+#define FSMC_BWTR3_ADDHLD 0x000000F0U /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FSMC_BWTR3_ADDHLD_0 0x00000010U /*!<Bit 0 */
+#define FSMC_BWTR3_ADDHLD_1 0x00000020U /*!<Bit 1 */
+#define FSMC_BWTR3_ADDHLD_2 0x00000040U /*!<Bit 2 */
+#define FSMC_BWTR3_ADDHLD_3 0x00000080U /*!<Bit 3 */
+
+#define FSMC_BWTR3_DATAST 0x0000FF00U /*!<DATAST [7:0] bits (Data-phase duration) */
+#define FSMC_BWTR3_DATAST_0 0x00000100U /*!<Bit 0 */
+#define FSMC_BWTR3_DATAST_1 0x00000200U /*!<Bit 1 */
+#define FSMC_BWTR3_DATAST_2 0x00000400U /*!<Bit 2 */
+#define FSMC_BWTR3_DATAST_3 0x00000800U /*!<Bit 3 */
+#define FSMC_BWTR3_DATAST_4 0x00001000U /*!<Bit 4 */
+#define FSMC_BWTR3_DATAST_5 0x00002000U /*!<Bit 5 */
+#define FSMC_BWTR3_DATAST_6 0x00004000U /*!<Bit 6 */
+#define FSMC_BWTR3_DATAST_7 0x00008000U /*!<Bit 7 */
+
+#define FSMC_BWTR3_BUSTURN 0x000F0000U /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
+#define FSMC_BWTR3_BUSTURN_0 0x00010000U /*!<Bit 0 */
+#define FSMC_BWTR3_BUSTURN_1 0x00020000U /*!<Bit 1 */
+#define FSMC_BWTR3_BUSTURN_2 0x00040000U /*!<Bit 2 */
+#define FSMC_BWTR3_BUSTURN_3 0x00080000U /*!<Bit 3 */
+
+#define FSMC_BWTR3_ACCMOD 0x30000000U /*!<ACCMOD[1:0] bits (Access mode) */
+#define FSMC_BWTR3_ACCMOD_0 0x10000000U /*!<Bit 0 */
+#define FSMC_BWTR3_ACCMOD_1 0x20000000U /*!<Bit 1 */
+
+/****************** Bit definition for FSMC_BWTR4 register ******************/
+#define FSMC_BWTR4_ADDSET 0x0000000FU /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FSMC_BWTR4_ADDSET_0 0x00000001U /*!<Bit 0 */
+#define FSMC_BWTR4_ADDSET_1 0x00000002U /*!<Bit 1 */
+#define FSMC_BWTR4_ADDSET_2 0x00000004U /*!<Bit 2 */
+#define FSMC_BWTR4_ADDSET_3 0x00000008U /*!<Bit 3 */
+
+#define FSMC_BWTR4_ADDHLD 0x000000F0U /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FSMC_BWTR4_ADDHLD_0 0x00000010U /*!<Bit 0 */
+#define FSMC_BWTR4_ADDHLD_1 0x00000020U /*!<Bit 1 */
+#define FSMC_BWTR4_ADDHLD_2 0x00000040U /*!<Bit 2 */
+#define FSMC_BWTR4_ADDHLD_3 0x00000080U /*!<Bit 3 */
+
+#define FSMC_BWTR4_DATAST 0x0000FF00U /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FSMC_BWTR4_DATAST_0 0x00000100U /*!<Bit 0 */
+#define FSMC_BWTR4_DATAST_1 0x00000200U /*!<Bit 1 */
+#define FSMC_BWTR4_DATAST_2 0x00000400U /*!<Bit 2 */
+#define FSMC_BWTR4_DATAST_3 0x00000800U /*!<Bit 3 */
+#define FSMC_BWTR4_DATAST_4 0x00001000U /*!<Bit 4 */
+#define FSMC_BWTR4_DATAST_5 0x00002000U /*!<Bit 5 */
+#define FSMC_BWTR4_DATAST_6 0x00004000U /*!<Bit 6 */
+#define FSMC_BWTR4_DATAST_7 0x00008000U /*!<Bit 7 */
+
+#define FSMC_BWTR4_BUSTURN 0x000F0000U /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
+#define FSMC_BWTR4_BUSTURN_0 0x00010000U /*!<Bit 0 */
+#define FSMC_BWTR4_BUSTURN_1 0x00020000U /*!<Bit 1 */
+#define FSMC_BWTR4_BUSTURN_2 0x00040000U /*!<Bit 2 */
+#define FSMC_BWTR4_BUSTURN_3 0x00080000U /*!<Bit 3 */
+
+#define FSMC_BWTR4_ACCMOD 0x30000000U /*!<ACCMOD[1:0] bits (Access mode) */
+#define FSMC_BWTR4_ACCMOD_0 0x10000000U /*!<Bit 0 */
+#define FSMC_BWTR4_ACCMOD_1 0x20000000U /*!<Bit 1 */
+
+/****************** Bit definition for FSMC_PCR2 register *******************/
+#define FSMC_PCR2_PWAITEN 0x00000002U /*!<Wait feature enable bit */
+#define FSMC_PCR2_PBKEN 0x00000004U /*!<PC Card/NAND Flash memory bank enable bit */
+#define FSMC_PCR2_PTYP 0x00000008U /*!<Memory type */
+
+#define FSMC_PCR2_PWID 0x00000030U /*!<PWID[1:0] bits (NAND Flash databus width) */
+#define FSMC_PCR2_PWID_0 0x00000010U /*!<Bit 0 */
+#define FSMC_PCR2_PWID_1 0x00000020U /*!<Bit 1 */
+
+#define FSMC_PCR2_ECCEN 0x00000040U /*!<ECC computation logic enable bit */
+
+#define FSMC_PCR2_TCLR 0x00001E00U /*!<TCLR[3:0] bits (CLE to RE delay) */
+#define FSMC_PCR2_TCLR_0 0x00000200U /*!<Bit 0 */
+#define FSMC_PCR2_TCLR_1 0x00000400U /*!<Bit 1 */
+#define FSMC_PCR2_TCLR_2 0x00000800U /*!<Bit 2 */
+#define FSMC_PCR2_TCLR_3 0x00001000U /*!<Bit 3 */
+
+#define FSMC_PCR2_TAR 0x0001E000U /*!<TAR[3:0] bits (ALE to RE delay) */
+#define FSMC_PCR2_TAR_0 0x00002000U /*!<Bit 0 */
+#define FSMC_PCR2_TAR_1 0x00004000U /*!<Bit 1 */
+#define FSMC_PCR2_TAR_2 0x00008000U /*!<Bit 2 */
+#define FSMC_PCR2_TAR_3 0x00010000U /*!<Bit 3 */
+
+#define FSMC_PCR2_ECCPS 0x000E0000U /*!<ECCPS[1:0] bits (ECC page size) */
+#define FSMC_PCR2_ECCPS_0 0x00020000U /*!<Bit 0 */
+#define FSMC_PCR2_ECCPS_1 0x00040000U /*!<Bit 1 */
+#define FSMC_PCR2_ECCPS_2 0x00080000U /*!<Bit 2 */
+
+/****************** Bit definition for FSMC_PCR3 register *******************/
+#define FSMC_PCR3_PWAITEN 0x00000002U /*!<Wait feature enable bit */
+#define FSMC_PCR3_PBKEN 0x00000004U /*!<PC Card/NAND Flash memory bank enable bit */
+#define FSMC_PCR3_PTYP 0x00000008U /*!<Memory type */
+
+#define FSMC_PCR3_PWID 0x00000030U /*!<PWID[1:0] bits (NAND Flash databus width) */
+#define FSMC_PCR3_PWID_0 0x00000010U /*!<Bit 0 */
+#define FSMC_PCR3_PWID_1 0x00000020U /*!<Bit 1 */
+
+#define FSMC_PCR3_ECCEN 0x00000040U /*!<ECC computation logic enable bit */
+
+#define FSMC_PCR3_TCLR 0x00001E00U /*!<TCLR[3:0] bits (CLE to RE delay) */
+#define FSMC_PCR3_TCLR_0 0x00000200U /*!<Bit 0 */
+#define FSMC_PCR3_TCLR_1 0x00000400U /*!<Bit 1 */
+#define FSMC_PCR3_TCLR_2 0x00000800U /*!<Bit 2 */
+#define FSMC_PCR3_TCLR_3 0x00001000U /*!<Bit 3 */
+
+#define FSMC_PCR3_TAR 0x0001E000U /*!<TAR[3:0] bits (ALE to RE delay) */
+#define FSMC_PCR3_TAR_0 0x00002000U /*!<Bit 0 */
+#define FSMC_PCR3_TAR_1 0x00004000U /*!<Bit 1 */
+#define FSMC_PCR3_TAR_2 0x00008000U /*!<Bit 2 */
+#define FSMC_PCR3_TAR_3 0x00010000U /*!<Bit 3 */
+
+#define FSMC_PCR3_ECCPS 0x000E0000U /*!<ECCPS[2:0] bits (ECC page size) */
+#define FSMC_PCR3_ECCPS_0 0x00020000U /*!<Bit 0 */
+#define FSMC_PCR3_ECCPS_1 0x00040000U /*!<Bit 1 */
+#define FSMC_PCR3_ECCPS_2 0x00080000U /*!<Bit 2 */
+
+/****************** Bit definition for FSMC_PCR4 register *******************/
+#define FSMC_PCR4_PWAITEN 0x00000002U /*!<Wait feature enable bit */
+#define FSMC_PCR4_PBKEN 0x00000004U /*!<PC Card/NAND Flash memory bank enable bit */
+#define FSMC_PCR4_PTYP 0x00000008U /*!<Memory type */
+
+#define FSMC_PCR4_PWID 0x00000030U /*!<PWID[1:0] bits (NAND Flash databus width) */
+#define FSMC_PCR4_PWID_0 0x00000010U /*!<Bit 0 */
+#define FSMC_PCR4_PWID_1 0x00000020U /*!<Bit 1 */
+
+#define FSMC_PCR4_ECCEN 0x00000040U /*!<ECC computation logic enable bit */
+
+#define FSMC_PCR4_TCLR 0x00001E00U /*!<TCLR[3:0] bits (CLE to RE delay) */
+#define FSMC_PCR4_TCLR_0 0x00000200U /*!<Bit 0 */
+#define FSMC_PCR4_TCLR_1 0x00000400U /*!<Bit 1 */
+#define FSMC_PCR4_TCLR_2 0x00000800U /*!<Bit 2 */
+#define FSMC_PCR4_TCLR_3 0x00001000U /*!<Bit 3 */
+
+#define FSMC_PCR4_TAR 0x0001E000U /*!<TAR[3:0] bits (ALE to RE delay) */
+#define FSMC_PCR4_TAR_0 0x00002000U /*!<Bit 0 */
+#define FSMC_PCR4_TAR_1 0x00004000U /*!<Bit 1 */
+#define FSMC_PCR4_TAR_2 0x00008000U /*!<Bit 2 */
+#define FSMC_PCR4_TAR_3 0x00010000U /*!<Bit 3 */
+
+#define FSMC_PCR4_ECCPS 0x000E0000U /*!<ECCPS[2:0] bits (ECC page size) */
+#define FSMC_PCR4_ECCPS_0 0x00020000U /*!<Bit 0 */
+#define FSMC_PCR4_ECCPS_1 0x00040000U /*!<Bit 1 */
+#define FSMC_PCR4_ECCPS_2 0x00080000U /*!<Bit 2 */
+
+/******************* Bit definition for FSMC_SR2 register *******************/
+#define FSMC_SR2_IRS 0x01U /*!<Interrupt Rising Edge status */
+#define FSMC_SR2_ILS 0x02U /*!<Interrupt Level status */
+#define FSMC_SR2_IFS 0x04U /*!<Interrupt Falling Edge status */
+#define FSMC_SR2_IREN 0x08U /*!<Interrupt Rising Edge detection Enable bit */
+#define FSMC_SR2_ILEN 0x10U /*!<Interrupt Level detection Enable bit */
+#define FSMC_SR2_IFEN 0x20U /*!<Interrupt Falling Edge detection Enable bit */
+#define FSMC_SR2_FEMPT 0x40U /*!<FIFO empty */
+
+/******************* Bit definition for FSMC_SR3 register *******************/
+#define FSMC_SR3_IRS 0x01U /*!<Interrupt Rising Edge status */
+#define FSMC_SR3_ILS 0x02U /*!<Interrupt Level status */
+#define FSMC_SR3_IFS 0x04U /*!<Interrupt Falling Edge status */
+#define FSMC_SR3_IREN 0x08U /*!<Interrupt Rising Edge detection Enable bit */
+#define FSMC_SR3_ILEN 0x10U /*!<Interrupt Level detection Enable bit */
+#define FSMC_SR3_IFEN 0x20U /*!<Interrupt Falling Edge detection Enable bit */
+#define FSMC_SR3_FEMPT 0x40U /*!<FIFO empty */
+
+/******************* Bit definition for FSMC_SR4 register *******************/
+#define FSMC_SR4_IRS 0x01U /*!<Interrupt Rising Edge status */
+#define FSMC_SR4_ILS 0x02U /*!<Interrupt Level status */
+#define FSMC_SR4_IFS 0x04U /*!<Interrupt Falling Edge status */
+#define FSMC_SR4_IREN 0x08U /*!<Interrupt Rising Edge detection Enable bit */
+#define FSMC_SR4_ILEN 0x10U /*!<Interrupt Level detection Enable bit */
+#define FSMC_SR4_IFEN 0x20U /*!<Interrupt Falling Edge detection Enable bit */
+#define FSMC_SR4_FEMPT 0x40U /*!<FIFO empty */
+
+/****************** Bit definition for FSMC_PMEM2 register ******************/
+#define FSMC_PMEM2_MEMSET2 0x000000FFU /*!<MEMSET2[7:0] bits (Common memory 2 setup time) */
+#define FSMC_PMEM2_MEMSET2_0 0x00000001U /*!<Bit 0 */
+#define FSMC_PMEM2_MEMSET2_1 0x00000002U /*!<Bit 1 */
+#define FSMC_PMEM2_MEMSET2_2 0x00000004U /*!<Bit 2 */
+#define FSMC_PMEM2_MEMSET2_3 0x00000008U /*!<Bit 3 */
+#define FSMC_PMEM2_MEMSET2_4 0x00000010U /*!<Bit 4 */
+#define FSMC_PMEM2_MEMSET2_5 0x00000020U /*!<Bit 5 */
+#define FSMC_PMEM2_MEMSET2_6 0x00000040U /*!<Bit 6 */
+#define FSMC_PMEM2_MEMSET2_7 0x00000080U /*!<Bit 7 */
+
+#define FSMC_PMEM2_MEMWAIT2 0x0000FF00U /*!<MEMWAIT2[7:0] bits (Common memory 2 wait time) */
+#define FSMC_PMEM2_MEMWAIT2_0 0x00000100U /*!<Bit 0 */
+#define FSMC_PMEM2_MEMWAIT2_1 0x00000200U /*!<Bit 1 */
+#define FSMC_PMEM2_MEMWAIT2_2 0x00000400U /*!<Bit 2 */
+#define FSMC_PMEM2_MEMWAIT2_3 0x00000800U /*!<Bit 3 */
+#define FSMC_PMEM2_MEMWAIT2_4 0x00001000U /*!<Bit 4 */
+#define FSMC_PMEM2_MEMWAIT2_5 0x00002000U /*!<Bit 5 */
+#define FSMC_PMEM2_MEMWAIT2_6 0x00004000U /*!<Bit 6 */
+#define FSMC_PMEM2_MEMWAIT2_7 0x00008000U /*!<Bit 7 */
+
+#define FSMC_PMEM2_MEMHOLD2 0x00FF0000U /*!<MEMHOLD2[7:0] bits (Common memory 2 hold time) */
+#define FSMC_PMEM2_MEMHOLD2_0 0x00010000U /*!<Bit 0 */
+#define FSMC_PMEM2_MEMHOLD2_1 0x00020000U /*!<Bit 1 */
+#define FSMC_PMEM2_MEMHOLD2_2 0x00040000U /*!<Bit 2 */
+#define FSMC_PMEM2_MEMHOLD2_3 0x00080000U /*!<Bit 3 */
+#define FSMC_PMEM2_MEMHOLD2_4 0x00100000U /*!<Bit 4 */
+#define FSMC_PMEM2_MEMHOLD2_5 0x00200000U /*!<Bit 5 */
+#define FSMC_PMEM2_MEMHOLD2_6 0x00400000U /*!<Bit 6 */
+#define FSMC_PMEM2_MEMHOLD2_7 0x00800000U /*!<Bit 7 */
+
+#define FSMC_PMEM2_MEMHIZ2 0xFF000000U /*!<MEMHIZ2[7:0] bits (Common memory 2 databus HiZ time) */
+#define FSMC_PMEM2_MEMHIZ2_0 0x01000000U /*!<Bit 0 */
+#define FSMC_PMEM2_MEMHIZ2_1 0x02000000U /*!<Bit 1 */
+#define FSMC_PMEM2_MEMHIZ2_2 0x04000000U /*!<Bit 2 */
+#define FSMC_PMEM2_MEMHIZ2_3 0x08000000U /*!<Bit 3 */
+#define FSMC_PMEM2_MEMHIZ2_4 0x10000000U /*!<Bit 4 */
+#define FSMC_PMEM2_MEMHIZ2_5 0x20000000U /*!<Bit 5 */
+#define FSMC_PMEM2_MEMHIZ2_6 0x40000000U /*!<Bit 6 */
+#define FSMC_PMEM2_MEMHIZ2_7 0x80000000U /*!<Bit 7 */
+
+/****************** Bit definition for FSMC_PMEM3 register ******************/
+#define FSMC_PMEM3_MEMSET3 0x000000FFU /*!<MEMSET3[7:0] bits (Common memory 3 setup time) */
+#define FSMC_PMEM3_MEMSET3_0 0x00000001U /*!<Bit 0 */
+#define FSMC_PMEM3_MEMSET3_1 0x00000002U /*!<Bit 1 */
+#define FSMC_PMEM3_MEMSET3_2 0x00000004U /*!<Bit 2 */
+#define FSMC_PMEM3_MEMSET3_3 0x00000008U /*!<Bit 3 */
+#define FSMC_PMEM3_MEMSET3_4 0x00000010U /*!<Bit 4 */
+#define FSMC_PMEM3_MEMSET3_5 0x00000020U /*!<Bit 5 */
+#define FSMC_PMEM3_MEMSET3_6 0x00000040U /*!<Bit 6 */
+#define FSMC_PMEM3_MEMSET3_7 0x00000080U /*!<Bit 7 */
+
+#define FSMC_PMEM3_MEMWAIT3 0x0000FF00U /*!<MEMWAIT3[7:0] bits (Common memory 3 wait time) */
+#define FSMC_PMEM3_MEMWAIT3_0 0x00000100U /*!<Bit 0 */
+#define FSMC_PMEM3_MEMWAIT3_1 0x00000200U /*!<Bit 1 */
+#define FSMC_PMEM3_MEMWAIT3_2 0x00000400U /*!<Bit 2 */
+#define FSMC_PMEM3_MEMWAIT3_3 0x00000800U /*!<Bit 3 */
+#define FSMC_PMEM3_MEMWAIT3_4 0x00001000U /*!<Bit 4 */
+#define FSMC_PMEM3_MEMWAIT3_5 0x00002000U /*!<Bit 5 */
+#define FSMC_PMEM3_MEMWAIT3_6 0x00004000U /*!<Bit 6 */
+#define FSMC_PMEM3_MEMWAIT3_7 0x00008000U /*!<Bit 7 */
+
+#define FSMC_PMEM3_MEMHOLD3 0x00FF0000U /*!<MEMHOLD3[7:0] bits (Common memory 3 hold time) */
+#define FSMC_PMEM3_MEMHOLD3_0 0x00010000U /*!<Bit 0 */
+#define FSMC_PMEM3_MEMHOLD3_1 0x00020000U /*!<Bit 1 */
+#define FSMC_PMEM3_MEMHOLD3_2 0x00040000U /*!<Bit 2 */
+#define FSMC_PMEM3_MEMHOLD3_3 0x00080000U /*!<Bit 3 */
+#define FSMC_PMEM3_MEMHOLD3_4 0x00100000U /*!<Bit 4 */
+#define FSMC_PMEM3_MEMHOLD3_5 0x00200000U /*!<Bit 5 */
+#define FSMC_PMEM3_MEMHOLD3_6 0x00400000U /*!<Bit 6 */
+#define FSMC_PMEM3_MEMHOLD3_7 0x00800000U /*!<Bit 7 */
+
+#define FSMC_PMEM3_MEMHIZ3 0xFF000000U /*!<MEMHIZ3[7:0] bits (Common memory 3 databus HiZ time) */
+#define FSMC_PMEM3_MEMHIZ3_0 0x01000000U /*!<Bit 0 */
+#define FSMC_PMEM3_MEMHIZ3_1 0x02000000U /*!<Bit 1 */
+#define FSMC_PMEM3_MEMHIZ3_2 0x04000000U /*!<Bit 2 */
+#define FSMC_PMEM3_MEMHIZ3_3 0x08000000U /*!<Bit 3 */
+#define FSMC_PMEM3_MEMHIZ3_4 0x10000000U /*!<Bit 4 */
+#define FSMC_PMEM3_MEMHIZ3_5 0x20000000U /*!<Bit 5 */
+#define FSMC_PMEM3_MEMHIZ3_6 0x40000000U /*!<Bit 6 */
+#define FSMC_PMEM3_MEMHIZ3_7 0x80000000U /*!<Bit 7 */
+
+/****************** Bit definition for FSMC_PMEM4 register ******************/
+#define FSMC_PMEM4_MEMSET4 0x000000FFU /*!<MEMSET4[7:0] bits (Common memory 4 setup time) */
+#define FSMC_PMEM4_MEMSET4_0 0x00000001U /*!<Bit 0 */
+#define FSMC_PMEM4_MEMSET4_1 0x00000002U /*!<Bit 1 */
+#define FSMC_PMEM4_MEMSET4_2 0x00000004U /*!<Bit 2 */
+#define FSMC_PMEM4_MEMSET4_3 0x00000008U /*!<Bit 3 */
+#define FSMC_PMEM4_MEMSET4_4 0x00000010U /*!<Bit 4 */
+#define FSMC_PMEM4_MEMSET4_5 0x00000020U /*!<Bit 5 */
+#define FSMC_PMEM4_MEMSET4_6 0x00000040U /*!<Bit 6 */
+#define FSMC_PMEM4_MEMSET4_7 0x00000080U /*!<Bit 7 */
+
+#define FSMC_PMEM4_MEMWAIT4 0x0000FF00U /*!<MEMWAIT4[7:0] bits (Common memory 4 wait time) */
+#define FSMC_PMEM4_MEMWAIT4_0 0x00000100U /*!<Bit 0 */
+#define FSMC_PMEM4_MEMWAIT4_1 0x00000200U /*!<Bit 1 */
+#define FSMC_PMEM4_MEMWAIT4_2 0x00000400U /*!<Bit 2 */
+#define FSMC_PMEM4_MEMWAIT4_3 0x00000800U /*!<Bit 3 */
+#define FSMC_PMEM4_MEMWAIT4_4 0x00001000U /*!<Bit 4 */
+#define FSMC_PMEM4_MEMWAIT4_5 0x00002000U /*!<Bit 5 */
+#define FSMC_PMEM4_MEMWAIT4_6 0x00004000U /*!<Bit 6 */
+#define FSMC_PMEM4_MEMWAIT4_7 0x00008000U /*!<Bit 7 */
+
+#define FSMC_PMEM4_MEMHOLD4 0x00FF0000U /*!<MEMHOLD4[7:0] bits (Common memory 4 hold time) */
+#define FSMC_PMEM4_MEMHOLD4_0 0x00010000U /*!<Bit 0 */
+#define FSMC_PMEM4_MEMHOLD4_1 0x00020000U /*!<Bit 1 */
+#define FSMC_PMEM4_MEMHOLD4_2 0x00040000U /*!<Bit 2 */
+#define FSMC_PMEM4_MEMHOLD4_3 0x00080000U /*!<Bit 3 */
+#define FSMC_PMEM4_MEMHOLD4_4 0x00100000U /*!<Bit 4 */
+#define FSMC_PMEM4_MEMHOLD4_5 0x00200000U /*!<Bit 5 */
+#define FSMC_PMEM4_MEMHOLD4_6 0x00400000U /*!<Bit 6 */
+#define FSMC_PMEM4_MEMHOLD4_7 0x00800000U /*!<Bit 7 */
+
+#define FSMC_PMEM4_MEMHIZ4 0xFF000000U /*!<MEMHIZ4[7:0] bits (Common memory 4 databus HiZ time) */
+#define FSMC_PMEM4_MEMHIZ4_0 0x01000000U /*!<Bit 0 */
+#define FSMC_PMEM4_MEMHIZ4_1 0x02000000U /*!<Bit 1 */
+#define FSMC_PMEM4_MEMHIZ4_2 0x04000000U /*!<Bit 2 */
+#define FSMC_PMEM4_MEMHIZ4_3 0x08000000U /*!<Bit 3 */
+#define FSMC_PMEM4_MEMHIZ4_4 0x10000000U /*!<Bit 4 */
+#define FSMC_PMEM4_MEMHIZ4_5 0x20000000U /*!<Bit 5 */
+#define FSMC_PMEM4_MEMHIZ4_6 0x40000000U /*!<Bit 6 */
+#define FSMC_PMEM4_MEMHIZ4_7 0x80000000U /*!<Bit 7 */
+
+/****************** Bit definition for FSMC_PATT2 register ******************/
+#define FSMC_PATT2_ATTSET2 0x000000FFU /*!<ATTSET2[7:0] bits (Attribute memory 2 setup time) */
+#define FSMC_PATT2_ATTSET2_0 0x00000001U /*!<Bit 0 */
+#define FSMC_PATT2_ATTSET2_1 0x00000002U /*!<Bit 1 */
+#define FSMC_PATT2_ATTSET2_2 0x00000004U /*!<Bit 2 */
+#define FSMC_PATT2_ATTSET2_3 0x00000008U /*!<Bit 3 */
+#define FSMC_PATT2_ATTSET2_4 0x00000010U /*!<Bit 4 */
+#define FSMC_PATT2_ATTSET2_5 0x00000020U /*!<Bit 5 */
+#define FSMC_PATT2_ATTSET2_6 0x00000040U /*!<Bit 6 */
+#define FSMC_PATT2_ATTSET2_7 0x00000080U /*!<Bit 7 */
+
+#define FSMC_PATT2_ATTWAIT2 0x0000FF00U /*!<ATTWAIT2[7:0] bits (Attribute memory 2 wait time) */
+#define FSMC_PATT2_ATTWAIT2_0 0x00000100U /*!<Bit 0 */
+#define FSMC_PATT2_ATTWAIT2_1 0x00000200U /*!<Bit 1 */
+#define FSMC_PATT2_ATTWAIT2_2 0x00000400U /*!<Bit 2 */
+#define FSMC_PATT2_ATTWAIT2_3 0x00000800U /*!<Bit 3 */
+#define FSMC_PATT2_ATTWAIT2_4 0x00001000U /*!<Bit 4 */
+#define FSMC_PATT2_ATTWAIT2_5 0x00002000U /*!<Bit 5 */
+#define FSMC_PATT2_ATTWAIT2_6 0x00004000U /*!<Bit 6 */
+#define FSMC_PATT2_ATTWAIT2_7 0x00008000U /*!<Bit 7 */
+
+#define FSMC_PATT2_ATTHOLD2 0x00FF0000U /*!<ATTHOLD2[7:0] bits (Attribute memory 2 hold time) */
+#define FSMC_PATT2_ATTHOLD2_0 0x00010000U /*!<Bit 0 */
+#define FSMC_PATT2_ATTHOLD2_1 0x00020000U /*!<Bit 1 */
+#define FSMC_PATT2_ATTHOLD2_2 0x00040000U /*!<Bit 2 */
+#define FSMC_PATT2_ATTHOLD2_3 0x00080000U /*!<Bit 3 */
+#define FSMC_PATT2_ATTHOLD2_4 0x00100000U /*!<Bit 4 */
+#define FSMC_PATT2_ATTHOLD2_5 0x00200000U /*!<Bit 5 */
+#define FSMC_PATT2_ATTHOLD2_6 0x00400000U /*!<Bit 6 */
+#define FSMC_PATT2_ATTHOLD2_7 0x00800000U /*!<Bit 7 */
+
+#define FSMC_PATT2_ATTHIZ2 0xFF000000U /*!<ATTHIZ2[7:0] bits (Attribute memory 2 databus HiZ time) */
+#define FSMC_PATT2_ATTHIZ2_0 0x01000000U /*!<Bit 0 */
+#define FSMC_PATT2_ATTHIZ2_1 0x02000000U /*!<Bit 1 */
+#define FSMC_PATT2_ATTHIZ2_2 0x04000000U /*!<Bit 2 */
+#define FSMC_PATT2_ATTHIZ2_3 0x08000000U /*!<Bit 3 */
+#define FSMC_PATT2_ATTHIZ2_4 0x10000000U /*!<Bit 4 */
+#define FSMC_PATT2_ATTHIZ2_5 0x20000000U /*!<Bit 5 */
+#define FSMC_PATT2_ATTHIZ2_6 0x40000000U /*!<Bit 6 */
+#define FSMC_PATT2_ATTHIZ2_7 0x80000000U /*!<Bit 7 */
+
+/****************** Bit definition for FSMC_PATT3 register ******************/
+#define FSMC_PATT3_ATTSET3 0x000000FFU /*!<ATTSET3[7:0] bits (Attribute memory 3 setup time) */
+#define FSMC_PATT3_ATTSET3_0 0x00000001U /*!<Bit 0 */
+#define FSMC_PATT3_ATTSET3_1 0x00000002U /*!<Bit 1 */
+#define FSMC_PATT3_ATTSET3_2 0x00000004U /*!<Bit 2 */
+#define FSMC_PATT3_ATTSET3_3 0x00000008U /*!<Bit 3 */
+#define FSMC_PATT3_ATTSET3_4 0x00000010U /*!<Bit 4 */
+#define FSMC_PATT3_ATTSET3_5 0x00000020U /*!<Bit 5 */
+#define FSMC_PATT3_ATTSET3_6 0x00000040U /*!<Bit 6 */
+#define FSMC_PATT3_ATTSET3_7 0x00000080U /*!<Bit 7 */
+
+#define FSMC_PATT3_ATTWAIT3 0x0000FF00U /*!<ATTWAIT3[7:0] bits (Attribute memory 3 wait time) */
+#define FSMC_PATT3_ATTWAIT3_0 0x00000100U /*!<Bit 0 */
+#define FSMC_PATT3_ATTWAIT3_1 0x00000200U /*!<Bit 1 */
+#define FSMC_PATT3_ATTWAIT3_2 0x00000400U /*!<Bit 2 */
+#define FSMC_PATT3_ATTWAIT3_3 0x00000800U /*!<Bit 3 */
+#define FSMC_PATT3_ATTWAIT3_4 0x00001000U /*!<Bit 4 */
+#define FSMC_PATT3_ATTWAIT3_5 0x00002000U /*!<Bit 5 */
+#define FSMC_PATT3_ATTWAIT3_6 0x00004000U /*!<Bit 6 */
+#define FSMC_PATT3_ATTWAIT3_7 0x00008000U /*!<Bit 7 */
+
+#define FSMC_PATT3_ATTHOLD3 0x00FF0000U /*!<ATTHOLD3[7:0] bits (Attribute memory 3 hold time) */
+#define FSMC_PATT3_ATTHOLD3_0 0x00010000U /*!<Bit 0 */
+#define FSMC_PATT3_ATTHOLD3_1 0x00020000U /*!<Bit 1 */
+#define FSMC_PATT3_ATTHOLD3_2 0x00040000U /*!<Bit 2 */
+#define FSMC_PATT3_ATTHOLD3_3 0x00080000U /*!<Bit 3 */
+#define FSMC_PATT3_ATTHOLD3_4 0x00100000U /*!<Bit 4 */
+#define FSMC_PATT3_ATTHOLD3_5 0x00200000U /*!<Bit 5 */
+#define FSMC_PATT3_ATTHOLD3_6 0x00400000U /*!<Bit 6 */
+#define FSMC_PATT3_ATTHOLD3_7 0x00800000U /*!<Bit 7 */
+
+#define FSMC_PATT3_ATTHIZ3 0xFF000000U /*!<ATTHIZ3[7:0] bits (Attribute memory 3 databus HiZ time) */
+#define FSMC_PATT3_ATTHIZ3_0 0x01000000U /*!<Bit 0 */
+#define FSMC_PATT3_ATTHIZ3_1 0x02000000U /*!<Bit 1 */
+#define FSMC_PATT3_ATTHIZ3_2 0x04000000U /*!<Bit 2 */
+#define FSMC_PATT3_ATTHIZ3_3 0x08000000U /*!<Bit 3 */
+#define FSMC_PATT3_ATTHIZ3_4 0x10000000U /*!<Bit 4 */
+#define FSMC_PATT3_ATTHIZ3_5 0x20000000U /*!<Bit 5 */
+#define FSMC_PATT3_ATTHIZ3_6 0x40000000U /*!<Bit 6 */
+#define FSMC_PATT3_ATTHIZ3_7 0x80000000U /*!<Bit 7 */
+
+/****************** Bit definition for FSMC_PATT4 register ******************/
+#define FSMC_PATT4_ATTSET4 0x000000FFU /*!<ATTSET4[7:0] bits (Attribute memory 4 setup time) */
+#define FSMC_PATT4_ATTSET4_0 0x00000001U /*!<Bit 0 */
+#define FSMC_PATT4_ATTSET4_1 0x00000002U /*!<Bit 1 */
+#define FSMC_PATT4_ATTSET4_2 0x00000004U /*!<Bit 2 */
+#define FSMC_PATT4_ATTSET4_3 0x00000008U /*!<Bit 3 */
+#define FSMC_PATT4_ATTSET4_4 0x00000010U /*!<Bit 4 */
+#define FSMC_PATT4_ATTSET4_5 0x00000020U /*!<Bit 5 */
+#define FSMC_PATT4_ATTSET4_6 0x00000040U /*!<Bit 6 */
+#define FSMC_PATT4_ATTSET4_7 0x00000080U /*!<Bit 7 */
+
+#define FSMC_PATT4_ATTWAIT4 0x0000FF00U /*!<ATTWAIT4[7:0] bits (Attribute memory 4 wait time) */
+#define FSMC_PATT4_ATTWAIT4_0 0x00000100U /*!<Bit 0 */
+#define FSMC_PATT4_ATTWAIT4_1 0x00000200U /*!<Bit 1 */
+#define FSMC_PATT4_ATTWAIT4_2 0x00000400U /*!<Bit 2 */
+#define FSMC_PATT4_ATTWAIT4_3 0x00000800U /*!<Bit 3 */
+#define FSMC_PATT4_ATTWAIT4_4 0x00001000U /*!<Bit 4 */
+#define FSMC_PATT4_ATTWAIT4_5 0x00002000U /*!<Bit 5 */
+#define FSMC_PATT4_ATTWAIT4_6 0x00004000U /*!<Bit 6 */
+#define FSMC_PATT4_ATTWAIT4_7 0x00008000U /*!<Bit 7 */
+
+#define FSMC_PATT4_ATTHOLD4 0x00FF0000U /*!<ATTHOLD4[7:0] bits (Attribute memory 4 hold time) */
+#define FSMC_PATT4_ATTHOLD4_0 0x00010000U /*!<Bit 0 */
+#define FSMC_PATT4_ATTHOLD4_1 0x00020000U /*!<Bit 1 */
+#define FSMC_PATT4_ATTHOLD4_2 0x00040000U /*!<Bit 2 */
+#define FSMC_PATT4_ATTHOLD4_3 0x00080000U /*!<Bit 3 */
+#define FSMC_PATT4_ATTHOLD4_4 0x00100000U /*!<Bit 4 */
+#define FSMC_PATT4_ATTHOLD4_5 0x00200000U /*!<Bit 5 */
+#define FSMC_PATT4_ATTHOLD4_6 0x00400000U /*!<Bit 6 */
+#define FSMC_PATT4_ATTHOLD4_7 0x00800000U /*!<Bit 7 */
+
+#define FSMC_PATT4_ATTHIZ4 0xFF000000U /*!<ATTHIZ4[7:0] bits (Attribute memory 4 databus HiZ time) */
+#define FSMC_PATT4_ATTHIZ4_0 0x01000000U /*!<Bit 0 */
+#define FSMC_PATT4_ATTHIZ4_1 0x02000000U /*!<Bit 1 */
+#define FSMC_PATT4_ATTHIZ4_2 0x04000000U /*!<Bit 2 */
+#define FSMC_PATT4_ATTHIZ4_3 0x08000000U /*!<Bit 3 */
+#define FSMC_PATT4_ATTHIZ4_4 0x10000000U /*!<Bit 4 */
+#define FSMC_PATT4_ATTHIZ4_5 0x20000000U /*!<Bit 5 */
+#define FSMC_PATT4_ATTHIZ4_6 0x40000000U /*!<Bit 6 */
+#define FSMC_PATT4_ATTHIZ4_7 0x80000000U /*!<Bit 7 */
+
+/****************** Bit definition for FSMC_PIO4 register *******************/
+#define FSMC_PIO4_IOSET4 0x000000FFU /*!<IOSET4[7:0] bits (I/O 4 setup time) */
+#define FSMC_PIO4_IOSET4_0 0x00000001U /*!<Bit 0 */
+#define FSMC_PIO4_IOSET4_1 0x00000002U /*!<Bit 1 */
+#define FSMC_PIO4_IOSET4_2 0x00000004U /*!<Bit 2 */
+#define FSMC_PIO4_IOSET4_3 0x00000008U /*!<Bit 3 */
+#define FSMC_PIO4_IOSET4_4 0x00000010U /*!<Bit 4 */
+#define FSMC_PIO4_IOSET4_5 0x00000020U /*!<Bit 5 */
+#define FSMC_PIO4_IOSET4_6 0x00000040U /*!<Bit 6 */
+#define FSMC_PIO4_IOSET4_7 0x00000080U /*!<Bit 7 */
+
+#define FSMC_PIO4_IOWAIT4 0x0000FF00U /*!<IOWAIT4[7:0] bits (I/O 4 wait time) */
+#define FSMC_PIO4_IOWAIT4_0 0x00000100U /*!<Bit 0 */
+#define FSMC_PIO4_IOWAIT4_1 0x00000200U /*!<Bit 1 */
+#define FSMC_PIO4_IOWAIT4_2 0x00000400U /*!<Bit 2 */
+#define FSMC_PIO4_IOWAIT4_3 0x00000800U /*!<Bit 3 */
+#define FSMC_PIO4_IOWAIT4_4 0x00001000U /*!<Bit 4 */
+#define FSMC_PIO4_IOWAIT4_5 0x00002000U /*!<Bit 5 */
+#define FSMC_PIO4_IOWAIT4_6 0x00004000U /*!<Bit 6 */
+#define FSMC_PIO4_IOWAIT4_7 0x00008000U /*!<Bit 7 */
+
+#define FSMC_PIO4_IOHOLD4 0x00FF0000U /*!<IOHOLD4[7:0] bits (I/O 4 hold time) */
+#define FSMC_PIO4_IOHOLD4_0 0x00010000U /*!<Bit 0 */
+#define FSMC_PIO4_IOHOLD4_1 0x00020000U /*!<Bit 1 */
+#define FSMC_PIO4_IOHOLD4_2 0x00040000U /*!<Bit 2 */
+#define FSMC_PIO4_IOHOLD4_3 0x00080000U /*!<Bit 3 */
+#define FSMC_PIO4_IOHOLD4_4 0x00100000U /*!<Bit 4 */
+#define FSMC_PIO4_IOHOLD4_5 0x00200000U /*!<Bit 5 */
+#define FSMC_PIO4_IOHOLD4_6 0x00400000U /*!<Bit 6 */
+#define FSMC_PIO4_IOHOLD4_7 0x00800000U /*!<Bit 7 */
+
+#define FSMC_PIO4_IOHIZ4 0xFF000000U /*!<IOHIZ4[7:0] bits (I/O 4 databus HiZ time) */
+#define FSMC_PIO4_IOHIZ4_0 0x01000000U /*!<Bit 0 */
+#define FSMC_PIO4_IOHIZ4_1 0x02000000U /*!<Bit 1 */
+#define FSMC_PIO4_IOHIZ4_2 0x04000000U /*!<Bit 2 */
+#define FSMC_PIO4_IOHIZ4_3 0x08000000U /*!<Bit 3 */
+#define FSMC_PIO4_IOHIZ4_4 0x10000000U /*!<Bit 4 */
+#define FSMC_PIO4_IOHIZ4_5 0x20000000U /*!<Bit 5 */
+#define FSMC_PIO4_IOHIZ4_6 0x40000000U /*!<Bit 6 */
+#define FSMC_PIO4_IOHIZ4_7 0x80000000U /*!<Bit 7 */
+
+/****************** Bit definition for FSMC_ECCR2 register ******************/
+#define FSMC_ECCR2_ECC2 0xFFFFFFFFU /*!<ECC result */
+
+/****************** Bit definition for FSMC_ECCR3 register ******************/
+#define FSMC_ECCR3_ECC3 0xFFFFFFFFU /*!<ECC result */
+
+/******************************************************************************/
+/* */
+/* General Purpose I/O */
+/* */
+/******************************************************************************/
+/****************** Bits definition for GPIO_MODER register *****************/
+#define GPIO_MODER_MODER0 0x00000003U
+#define GPIO_MODER_MODER0_0 0x00000001U
+#define GPIO_MODER_MODER0_1 0x00000002U
+
+#define GPIO_MODER_MODER1 0x0000000CU
+#define GPIO_MODER_MODER1_0 0x00000004U
+#define GPIO_MODER_MODER1_1 0x00000008U
+
+#define GPIO_MODER_MODER2 0x00000030U
+#define GPIO_MODER_MODER2_0 0x00000010U
+#define GPIO_MODER_MODER2_1 0x00000020U
+
+#define GPIO_MODER_MODER3 0x000000C0U
+#define GPIO_MODER_MODER3_0 0x00000040U
+#define GPIO_MODER_MODER3_1 0x00000080U
+
+#define GPIO_MODER_MODER4 0x00000300U
+#define GPIO_MODER_MODER4_0 0x00000100U
+#define GPIO_MODER_MODER4_1 0x00000200U
+
+#define GPIO_MODER_MODER5 0x00000C00U
+#define GPIO_MODER_MODER5_0 0x00000400U
+#define GPIO_MODER_MODER5_1 0x00000800U
+
+#define GPIO_MODER_MODER6 0x00003000U
+#define GPIO_MODER_MODER6_0 0x00001000U
+#define GPIO_MODER_MODER6_1 0x00002000U
+
+#define GPIO_MODER_MODER7 0x0000C000U
+#define GPIO_MODER_MODER7_0 0x00004000U
+#define GPIO_MODER_MODER7_1 0x00008000U
+
+#define GPIO_MODER_MODER8 0x00030000U
+#define GPIO_MODER_MODER8_0 0x00010000U
+#define GPIO_MODER_MODER8_1 0x00020000U
+
+#define GPIO_MODER_MODER9 0x000C0000U
+#define GPIO_MODER_MODER9_0 0x00040000U
+#define GPIO_MODER_MODER9_1 0x00080000U
+
+#define GPIO_MODER_MODER10 0x00300000U
+#define GPIO_MODER_MODER10_0 0x00100000U
+#define GPIO_MODER_MODER10_1 0x00200000U
+
+#define GPIO_MODER_MODER11 0x00C00000U
+#define GPIO_MODER_MODER11_0 0x00400000U
+#define GPIO_MODER_MODER11_1 0x00800000U
+
+#define GPIO_MODER_MODER12 0x03000000U
+#define GPIO_MODER_MODER12_0 0x01000000U
+#define GPIO_MODER_MODER12_1 0x02000000U
+
+#define GPIO_MODER_MODER13 0x0C000000U
+#define GPIO_MODER_MODER13_0 0x04000000U
+#define GPIO_MODER_MODER13_1 0x08000000U
+
+#define GPIO_MODER_MODER14 0x30000000U
+#define GPIO_MODER_MODER14_0 0x10000000U
+#define GPIO_MODER_MODER14_1 0x20000000U
+
+#define GPIO_MODER_MODER15 0xC0000000U
+#define GPIO_MODER_MODER15_0 0x40000000U
+#define GPIO_MODER_MODER15_1 0x80000000U
+
+/****************** Bits definition for GPIO_OTYPER register ****************/
+#define GPIO_OTYPER_OT_0 0x00000001U
+#define GPIO_OTYPER_OT_1 0x00000002U
+#define GPIO_OTYPER_OT_2 0x00000004U
+#define GPIO_OTYPER_OT_3 0x00000008U
+#define GPIO_OTYPER_OT_4 0x00000010U
+#define GPIO_OTYPER_OT_5 0x00000020U
+#define GPIO_OTYPER_OT_6 0x00000040U
+#define GPIO_OTYPER_OT_7 0x00000080U
+#define GPIO_OTYPER_OT_8 0x00000100U
+#define GPIO_OTYPER_OT_9 0x00000200U
+#define GPIO_OTYPER_OT_10 0x00000400U
+#define GPIO_OTYPER_OT_11 0x00000800U
+#define GPIO_OTYPER_OT_12 0x00001000U
+#define GPIO_OTYPER_OT_13 0x00002000U
+#define GPIO_OTYPER_OT_14 0x00004000U
+#define GPIO_OTYPER_OT_15 0x00008000U
+
+/****************** Bits definition for GPIO_OSPEEDR register ***************/
+#define GPIO_OSPEEDER_OSPEEDR0 0x00000003U
+#define GPIO_OSPEEDER_OSPEEDR0_0 0x00000001U
+#define GPIO_OSPEEDER_OSPEEDR0_1 0x00000002U
+
+#define GPIO_OSPEEDER_OSPEEDR1 0x0000000CU
+#define GPIO_OSPEEDER_OSPEEDR1_0 0x00000004U
+#define GPIO_OSPEEDER_OSPEEDR1_1 0x00000008U
+
+#define GPIO_OSPEEDER_OSPEEDR2 0x00000030U
+#define GPIO_OSPEEDER_OSPEEDR2_0 0x00000010U
+#define GPIO_OSPEEDER_OSPEEDR2_1 0x00000020U
+
+#define GPIO_OSPEEDER_OSPEEDR3 0x000000C0U
+#define GPIO_OSPEEDER_OSPEEDR3_0 0x00000040U
+#define GPIO_OSPEEDER_OSPEEDR3_1 0x00000080U
+
+#define GPIO_OSPEEDER_OSPEEDR4 0x00000300U
+#define GPIO_OSPEEDER_OSPEEDR4_0 0x00000100U
+#define GPIO_OSPEEDER_OSPEEDR4_1 0x00000200U
+
+#define GPIO_OSPEEDER_OSPEEDR5 0x00000C00U
+#define GPIO_OSPEEDER_OSPEEDR5_0 0x00000400U
+#define GPIO_OSPEEDER_OSPEEDR5_1 0x00000800U
+
+#define GPIO_OSPEEDER_OSPEEDR6 0x00003000U
+#define GPIO_OSPEEDER_OSPEEDR6_0 0x00001000U
+#define GPIO_OSPEEDER_OSPEEDR6_1 0x00002000U
+
+#define GPIO_OSPEEDER_OSPEEDR7 0x0000C000U
+#define GPIO_OSPEEDER_OSPEEDR7_0 0x00004000U
+#define GPIO_OSPEEDER_OSPEEDR7_1 0x00008000U
+
+#define GPIO_OSPEEDER_OSPEEDR8 0x00030000U
+#define GPIO_OSPEEDER_OSPEEDR8_0 0x00010000U
+#define GPIO_OSPEEDER_OSPEEDR8_1 0x00020000U
+
+#define GPIO_OSPEEDER_OSPEEDR9 0x000C0000U
+#define GPIO_OSPEEDER_OSPEEDR9_0 0x00040000U
+#define GPIO_OSPEEDER_OSPEEDR9_1 0x00080000U
+
+#define GPIO_OSPEEDER_OSPEEDR10 0x00300000U
+#define GPIO_OSPEEDER_OSPEEDR10_0 0x00100000U
+#define GPIO_OSPEEDER_OSPEEDR10_1 0x00200000U
+
+#define GPIO_OSPEEDER_OSPEEDR11 0x00C00000U
+#define GPIO_OSPEEDER_OSPEEDR11_0 0x00400000U
+#define GPIO_OSPEEDER_OSPEEDR11_1 0x00800000U
+
+#define GPIO_OSPEEDER_OSPEEDR12 0x03000000U
+#define GPIO_OSPEEDER_OSPEEDR12_0 0x01000000U
+#define GPIO_OSPEEDER_OSPEEDR12_1 0x02000000U
+
+#define GPIO_OSPEEDER_OSPEEDR13 0x0C000000U
+#define GPIO_OSPEEDER_OSPEEDR13_0 0x04000000U
+#define GPIO_OSPEEDER_OSPEEDR13_1 0x08000000U
+
+#define GPIO_OSPEEDER_OSPEEDR14 0x30000000U
+#define GPIO_OSPEEDER_OSPEEDR14_0 0x10000000U
+#define GPIO_OSPEEDER_OSPEEDR14_1 0x20000000U
+
+#define GPIO_OSPEEDER_OSPEEDR15 0xC0000000U
+#define GPIO_OSPEEDER_OSPEEDR15_0 0x40000000U
+#define GPIO_OSPEEDER_OSPEEDR15_1 0x80000000U
+
+/****************** Bits definition for GPIO_PUPDR register *****************/
+#define GPIO_PUPDR_PUPDR0 0x00000003U
+#define GPIO_PUPDR_PUPDR0_0 0x00000001U
+#define GPIO_PUPDR_PUPDR0_1 0x00000002U
+
+#define GPIO_PUPDR_PUPDR1 0x0000000CU
+#define GPIO_PUPDR_PUPDR1_0 0x00000004U
+#define GPIO_PUPDR_PUPDR1_1 0x00000008U
+
+#define GPIO_PUPDR_PUPDR2 0x00000030U
+#define GPIO_PUPDR_PUPDR2_0 0x00000010U
+#define GPIO_PUPDR_PUPDR2_1 0x00000020U
+
+#define GPIO_PUPDR_PUPDR3 0x000000C0U
+#define GPIO_PUPDR_PUPDR3_0 0x00000040U
+#define GPIO_PUPDR_PUPDR3_1 0x00000080U
+
+#define GPIO_PUPDR_PUPDR4 0x00000300U
+#define GPIO_PUPDR_PUPDR4_0 0x00000100U
+#define GPIO_PUPDR_PUPDR4_1 0x00000200U
+
+#define GPIO_PUPDR_PUPDR5 0x00000C00U
+#define GPIO_PUPDR_PUPDR5_0 0x00000400U
+#define GPIO_PUPDR_PUPDR5_1 0x00000800U
+
+#define GPIO_PUPDR_PUPDR6 0x00003000U
+#define GPIO_PUPDR_PUPDR6_0 0x00001000U
+#define GPIO_PUPDR_PUPDR6_1 0x00002000U
+
+#define GPIO_PUPDR_PUPDR7 0x0000C000U
+#define GPIO_PUPDR_PUPDR7_0 0x00004000U
+#define GPIO_PUPDR_PUPDR7_1 0x00008000U
+
+#define GPIO_PUPDR_PUPDR8 0x00030000U
+#define GPIO_PUPDR_PUPDR8_0 0x00010000U
+#define GPIO_PUPDR_PUPDR8_1 0x00020000U
+
+#define GPIO_PUPDR_PUPDR9 0x000C0000U
+#define GPIO_PUPDR_PUPDR9_0 0x00040000U
+#define GPIO_PUPDR_PUPDR9_1 0x00080000U
+
+#define GPIO_PUPDR_PUPDR10 0x00300000U
+#define GPIO_PUPDR_PUPDR10_0 0x00100000U
+#define GPIO_PUPDR_PUPDR10_1 0x00200000U
+
+#define GPIO_PUPDR_PUPDR11 0x00C00000U
+#define GPIO_PUPDR_PUPDR11_0 0x00400000U
+#define GPIO_PUPDR_PUPDR11_1 0x00800000U
+
+#define GPIO_PUPDR_PUPDR12 0x03000000U
+#define GPIO_PUPDR_PUPDR12_0 0x01000000U
+#define GPIO_PUPDR_PUPDR12_1 0x02000000U
+
+#define GPIO_PUPDR_PUPDR13 0x0C000000U
+#define GPIO_PUPDR_PUPDR13_0 0x04000000U
+#define GPIO_PUPDR_PUPDR13_1 0x08000000U
+
+#define GPIO_PUPDR_PUPDR14 0x30000000U
+#define GPIO_PUPDR_PUPDR14_0 0x10000000U
+#define GPIO_PUPDR_PUPDR14_1 0x20000000U
+
+#define GPIO_PUPDR_PUPDR15 0xC0000000U
+#define GPIO_PUPDR_PUPDR15_0 0x40000000U
+#define GPIO_PUPDR_PUPDR15_1 0x80000000U
+
+/****************** Bits definition for GPIO_IDR register *******************/
+#define GPIO_IDR_IDR_0 0x00000001U
+#define GPIO_IDR_IDR_1 0x00000002U
+#define GPIO_IDR_IDR_2 0x00000004U
+#define GPIO_IDR_IDR_3 0x00000008U
+#define GPIO_IDR_IDR_4 0x00000010U
+#define GPIO_IDR_IDR_5 0x00000020U
+#define GPIO_IDR_IDR_6 0x00000040U
+#define GPIO_IDR_IDR_7 0x00000080U
+#define GPIO_IDR_IDR_8 0x00000100U
+#define GPIO_IDR_IDR_9 0x00000200U
+#define GPIO_IDR_IDR_10 0x00000400U
+#define GPIO_IDR_IDR_11 0x00000800U
+#define GPIO_IDR_IDR_12 0x00001000U
+#define GPIO_IDR_IDR_13 0x00002000U
+#define GPIO_IDR_IDR_14 0x00004000U
+#define GPIO_IDR_IDR_15 0x00008000U
+/* Old GPIO_IDR register bits definition, maintained for legacy purpose */
+#define GPIO_OTYPER_IDR_0 GPIO_IDR_IDR_0
+#define GPIO_OTYPER_IDR_1 GPIO_IDR_IDR_1
+#define GPIO_OTYPER_IDR_2 GPIO_IDR_IDR_2
+#define GPIO_OTYPER_IDR_3 GPIO_IDR_IDR_3
+#define GPIO_OTYPER_IDR_4 GPIO_IDR_IDR_4
+#define GPIO_OTYPER_IDR_5 GPIO_IDR_IDR_5
+#define GPIO_OTYPER_IDR_6 GPIO_IDR_IDR_6
+#define GPIO_OTYPER_IDR_7 GPIO_IDR_IDR_7
+#define GPIO_OTYPER_IDR_8 GPIO_IDR_IDR_8
+#define GPIO_OTYPER_IDR_9 GPIO_IDR_IDR_9
+#define GPIO_OTYPER_IDR_10 GPIO_IDR_IDR_10
+#define GPIO_OTYPER_IDR_11 GPIO_IDR_IDR_11
+#define GPIO_OTYPER_IDR_12 GPIO_IDR_IDR_12
+#define GPIO_OTYPER_IDR_13 GPIO_IDR_IDR_13
+#define GPIO_OTYPER_IDR_14 GPIO_IDR_IDR_14
+#define GPIO_OTYPER_IDR_15 GPIO_IDR_IDR_15
+
+/****************** Bits definition for GPIO_ODR register *******************/
+#define GPIO_ODR_ODR_0 0x00000001U
+#define GPIO_ODR_ODR_1 0x00000002U
+#define GPIO_ODR_ODR_2 0x00000004U
+#define GPIO_ODR_ODR_3 0x00000008U
+#define GPIO_ODR_ODR_4 0x00000010U
+#define GPIO_ODR_ODR_5 0x00000020U
+#define GPIO_ODR_ODR_6 0x00000040U
+#define GPIO_ODR_ODR_7 0x00000080U
+#define GPIO_ODR_ODR_8 0x00000100U
+#define GPIO_ODR_ODR_9 0x00000200U
+#define GPIO_ODR_ODR_10 0x00000400U
+#define GPIO_ODR_ODR_11 0x00000800U
+#define GPIO_ODR_ODR_12 0x00001000U
+#define GPIO_ODR_ODR_13 0x00002000U
+#define GPIO_ODR_ODR_14 0x00004000U
+#define GPIO_ODR_ODR_15 0x00008000U
+/* Old GPIO_ODR register bits definition, maintained for legacy purpose */
+#define GPIO_OTYPER_ODR_0 GPIO_ODR_ODR_0
+#define GPIO_OTYPER_ODR_1 GPIO_ODR_ODR_1
+#define GPIO_OTYPER_ODR_2 GPIO_ODR_ODR_2
+#define GPIO_OTYPER_ODR_3 GPIO_ODR_ODR_3
+#define GPIO_OTYPER_ODR_4 GPIO_ODR_ODR_4
+#define GPIO_OTYPER_ODR_5 GPIO_ODR_ODR_5
+#define GPIO_OTYPER_ODR_6 GPIO_ODR_ODR_6
+#define GPIO_OTYPER_ODR_7 GPIO_ODR_ODR_7
+#define GPIO_OTYPER_ODR_8 GPIO_ODR_ODR_8
+#define GPIO_OTYPER_ODR_9 GPIO_ODR_ODR_9
+#define GPIO_OTYPER_ODR_10 GPIO_ODR_ODR_10
+#define GPIO_OTYPER_ODR_11 GPIO_ODR_ODR_11
+#define GPIO_OTYPER_ODR_12 GPIO_ODR_ODR_12
+#define GPIO_OTYPER_ODR_13 GPIO_ODR_ODR_13
+#define GPIO_OTYPER_ODR_14 GPIO_ODR_ODR_14
+#define GPIO_OTYPER_ODR_15 GPIO_ODR_ODR_15
+
+/****************** Bits definition for GPIO_BSRR register ******************/
+#define GPIO_BSRR_BS_0 0x00000001U
+#define GPIO_BSRR_BS_1 0x00000002U
+#define GPIO_BSRR_BS_2 0x00000004U
+#define GPIO_BSRR_BS_3 0x00000008U
+#define GPIO_BSRR_BS_4 0x00000010U
+#define GPIO_BSRR_BS_5 0x00000020U
+#define GPIO_BSRR_BS_6 0x00000040U
+#define GPIO_BSRR_BS_7 0x00000080U
+#define GPIO_BSRR_BS_8 0x00000100U
+#define GPIO_BSRR_BS_9 0x00000200U
+#define GPIO_BSRR_BS_10 0x00000400U
+#define GPIO_BSRR_BS_11 0x00000800U
+#define GPIO_BSRR_BS_12 0x00001000U
+#define GPIO_BSRR_BS_13 0x00002000U
+#define GPIO_BSRR_BS_14 0x00004000U
+#define GPIO_BSRR_BS_15 0x00008000U
+#define GPIO_BSRR_BR_0 0x00010000U
+#define GPIO_BSRR_BR_1 0x00020000U
+#define GPIO_BSRR_BR_2 0x00040000U
+#define GPIO_BSRR_BR_3 0x00080000U
+#define GPIO_BSRR_BR_4 0x00100000U
+#define GPIO_BSRR_BR_5 0x00200000U
+#define GPIO_BSRR_BR_6 0x00400000U
+#define GPIO_BSRR_BR_7 0x00800000U
+#define GPIO_BSRR_BR_8 0x01000000U
+#define GPIO_BSRR_BR_9 0x02000000U
+#define GPIO_BSRR_BR_10 0x04000000U
+#define GPIO_BSRR_BR_11 0x08000000U
+#define GPIO_BSRR_BR_12 0x10000000U
+#define GPIO_BSRR_BR_13 0x20000000U
+#define GPIO_BSRR_BR_14 0x40000000U
+#define GPIO_BSRR_BR_15 0x80000000U
+
+/****************** Bit definition for GPIO_LCKR register *********************/
+#define GPIO_LCKR_LCK0 0x00000001U
+#define GPIO_LCKR_LCK1 0x00000002U
+#define GPIO_LCKR_LCK2 0x00000004U
+#define GPIO_LCKR_LCK3 0x00000008U
+#define GPIO_LCKR_LCK4 0x00000010U
+#define GPIO_LCKR_LCK5 0x00000020U
+#define GPIO_LCKR_LCK6 0x00000040U
+#define GPIO_LCKR_LCK7 0x00000080U
+#define GPIO_LCKR_LCK8 0x00000100U
+#define GPIO_LCKR_LCK9 0x00000200U
+#define GPIO_LCKR_LCK10 0x00000400U
+#define GPIO_LCKR_LCK11 0x00000800U
+#define GPIO_LCKR_LCK12 0x00001000U
+#define GPIO_LCKR_LCK13 0x00002000U
+#define GPIO_LCKR_LCK14 0x00004000U
+#define GPIO_LCKR_LCK15 0x00008000U
+#define GPIO_LCKR_LCKK 0x00010000U
+
+/******************************************************************************/
+/* */
+/* Inter-integrated Circuit Interface */
+/* */
+/******************************************************************************/
+/******************* Bit definition for I2C_CR1 register ********************/
+#define I2C_CR1_PE 0x00000001U /*!<Peripheral Enable */
+#define I2C_CR1_SMBUS 0x00000002U /*!<SMBus Mode */
+#define I2C_CR1_SMBTYPE 0x00000008U /*!<SMBus Type */
+#define I2C_CR1_ENARP 0x00000010U /*!<ARP Enable */
+#define I2C_CR1_ENPEC 0x00000020U /*!<PEC Enable */
+#define I2C_CR1_ENGC 0x00000040U /*!<General Call Enable */
+#define I2C_CR1_NOSTRETCH 0x00000080U /*!<Clock Stretching Disable (Slave mode) */
+#define I2C_CR1_START 0x00000100U /*!<Start Generation */
+#define I2C_CR1_STOP 0x00000200U /*!<Stop Generation */
+#define I2C_CR1_ACK 0x00000400U /*!<Acknowledge Enable */
+#define I2C_CR1_POS 0x00000800U /*!<Acknowledge/PEC Position (for data reception) */
+#define I2C_CR1_PEC 0x00001000U /*!<Packet Error Checking */
+#define I2C_CR1_ALERT 0x00002000U /*!<SMBus Alert */
+#define I2C_CR1_SWRST 0x00008000U /*!<Software Reset */
+
+/******************* Bit definition for I2C_CR2 register ********************/
+#define I2C_CR2_FREQ 0x0000003FU /*!<FREQ[5:0] bits (Peripheral Clock Frequency) */
+#define I2C_CR2_FREQ_0 0x00000001U /*!<Bit 0 */
+#define I2C_CR2_FREQ_1 0x00000002U /*!<Bit 1 */
+#define I2C_CR2_FREQ_2 0x00000004U /*!<Bit 2 */
+#define I2C_CR2_FREQ_3 0x00000008U /*!<Bit 3 */
+#define I2C_CR2_FREQ_4 0x00000010U /*!<Bit 4 */
+#define I2C_CR2_FREQ_5 0x00000020U /*!<Bit 5 */
+
+#define I2C_CR2_ITERREN 0x00000100U /*!<Error Interrupt Enable */
+#define I2C_CR2_ITEVTEN 0x00000200U /*!<Event Interrupt Enable */
+#define I2C_CR2_ITBUFEN 0x00000400U /*!<Buffer Interrupt Enable */
+#define I2C_CR2_DMAEN 0x00000800U /*!<DMA Requests Enable */
+#define I2C_CR2_LAST 0x00001000U /*!<DMA Last Transfer */
+
+/******************* Bit definition for I2C_OAR1 register *******************/
+#define I2C_OAR1_ADD1_7 0x000000FEU /*!<Interface Address */
+#define I2C_OAR1_ADD8_9 0x00000300U /*!<Interface Address */
+
+#define I2C_OAR1_ADD0 0x00000001U /*!<Bit 0 */
+#define I2C_OAR1_ADD1 0x00000002U /*!<Bit 1 */
+#define I2C_OAR1_ADD2 0x00000004U /*!<Bit 2 */
+#define I2C_OAR1_ADD3 0x00000008U /*!<Bit 3 */
+#define I2C_OAR1_ADD4 0x00000010U /*!<Bit 4 */
+#define I2C_OAR1_ADD5 0x00000020U /*!<Bit 5 */
+#define I2C_OAR1_ADD6 0x00000040U /*!<Bit 6 */
+#define I2C_OAR1_ADD7 0x00000080U /*!<Bit 7 */
+#define I2C_OAR1_ADD8 0x00000100U /*!<Bit 8 */
+#define I2C_OAR1_ADD9 0x00000200U /*!<Bit 9 */
+
+#define I2C_OAR1_ADDMODE 0x00008000U /*!<Addressing Mode (Slave mode) */
+
+/******************* Bit definition for I2C_OAR2 register *******************/
+#define I2C_OAR2_ENDUAL 0x00000001U /*!<Dual addressing mode enable */
+#define I2C_OAR2_ADD2 0x000000FEU /*!<Interface address */
+
+/******************** Bit definition for I2C_DR register ********************/
+#define I2C_DR_DR 0x000000FFU /*!<8-bit Data Register */
+
+/******************* Bit definition for I2C_SR1 register ********************/
+#define I2C_SR1_SB 0x00000001U /*!<Start Bit (Master mode) */
+#define I2C_SR1_ADDR 0x00000002U /*!<Address sent (master mode)/matched (slave mode) */
+#define I2C_SR1_BTF 0x00000004U /*!<Byte Transfer Finished */
+#define I2C_SR1_ADD10 0x00000008U /*!<10-bit header sent (Master mode) */
+#define I2C_SR1_STOPF 0x00000010U /*!<Stop detection (Slave mode) */
+#define I2C_SR1_RXNE 0x00000040U /*!<Data Register not Empty (receivers) */
+#define I2C_SR1_TXE 0x00000080U /*!<Data Register Empty (transmitters) */
+#define I2C_SR1_BERR 0x00000100U /*!<Bus Error */
+#define I2C_SR1_ARLO 0x00000200U /*!<Arbitration Lost (master mode) */
+#define I2C_SR1_AF 0x00000400U /*!<Acknowledge Failure */
+#define I2C_SR1_OVR 0x00000800U /*!<Overrun/Underrun */
+#define I2C_SR1_PECERR 0x00001000U /*!<PEC Error in reception */
+#define I2C_SR1_TIMEOUT 0x00004000U /*!<Timeout or Tlow Error */
+#define I2C_SR1_SMBALERT 0x00008000U /*!<SMBus Alert */
+
+/******************* Bit definition for I2C_SR2 register ********************/
+#define I2C_SR2_MSL 0x00000001U /*!<Master/Slave */
+#define I2C_SR2_BUSY 0x00000002U /*!<Bus Busy */
+#define I2C_SR2_TRA 0x00000004U /*!<Transmitter/Receiver */
+#define I2C_SR2_GENCALL 0x00000010U /*!<General Call Address (Slave mode) */
+#define I2C_SR2_SMBDEFAULT 0x00000020U /*!<SMBus Device Default Address (Slave mode) */
+#define I2C_SR2_SMBHOST 0x00000040U /*!<SMBus Host Header (Slave mode) */
+#define I2C_SR2_DUALF 0x00000080U /*!<Dual Flag (Slave mode) */
+#define I2C_SR2_PEC 0x0000FF00U /*!<Packet Error Checking Register */
+
+/******************* Bit definition for I2C_CCR register ********************/
+#define I2C_CCR_CCR 0x00000FFFU /*!<Clock Control Register in Fast/Standard mode (Master mode) */
+#define I2C_CCR_DUTY 0x00004000U /*!<Fast Mode Duty Cycle */
+#define I2C_CCR_FS 0x00008000U /*!<I2C Master Mode Selection */
+
+/****************** Bit definition for I2C_TRISE register *******************/
+#define I2C_TRISE_TRISE 0x0000003FU /*!<Maximum Rise Time in Fast/Standard mode (Master mode) */
+
+/****************** Bit definition for I2C_FLTR register *******************/
+#define I2C_FLTR_DNF 0x0000000FU /*!<Digital Noise Filter */
+#define I2C_FLTR_ANOFF 0x00000010U /*!<Analog Noise Filter OFF */
+
+/******************************************************************************/
+/* */
+/* Independent WATCHDOG */
+/* */
+/******************************************************************************/
+/******************* Bit definition for IWDG_KR register ********************/
+#define IWDG_KR_KEY 0xFFFFU /*!<Key value (write only, read 0000h) */
+
+/******************* Bit definition for IWDG_PR register ********************/
+#define IWDG_PR_PR 0x07U /*!<PR[2:0] (Prescaler divider) */
+#define IWDG_PR_PR_0 0x01U /*!<Bit 0 */
+#define IWDG_PR_PR_1 0x02U /*!<Bit 1 */
+#define IWDG_PR_PR_2 0x04U /*!<Bit 2 */
+
+/******************* Bit definition for IWDG_RLR register *******************/
+#define IWDG_RLR_RL 0x0FFFU /*!<Watchdog counter reload value */
+
+/******************* Bit definition for IWDG_SR register ********************/
+#define IWDG_SR_PVU 0x01U /*!<Watchdog prescaler value update */
+#define IWDG_SR_RVU 0x02U /*!<Watchdog counter reload value update */
+
+
+/******************************************************************************/
+/* */
+/* Power Control */
+/* */
+/******************************************************************************/
+/******************** Bit definition for PWR_CR register ********************/
+#define PWR_CR_LPDS 0x00000001U /*!< Low-Power Deepsleep */
+#define PWR_CR_PDDS 0x00000002U /*!< Power Down Deepsleep */
+#define PWR_CR_CWUF 0x00000004U /*!< Clear Wakeup Flag */
+#define PWR_CR_CSBF 0x00000008U /*!< Clear Standby Flag */
+#define PWR_CR_PVDE 0x00000010U /*!< Power Voltage Detector Enable */
+
+#define PWR_CR_PLS 0x000000E0U /*!< PLS[2:0] bits (PVD Level Selection) */
+#define PWR_CR_PLS_0 0x00000020U /*!< Bit 0 */
+#define PWR_CR_PLS_1 0x00000040U /*!< Bit 1 */
+#define PWR_CR_PLS_2 0x00000080U /*!< Bit 2 */
+
+/*!< PVD level configuration */
+#define PWR_CR_PLS_LEV0 0x00000000U /*!< PVD level 0 */
+#define PWR_CR_PLS_LEV1 0x00000020U /*!< PVD level 1 */
+#define PWR_CR_PLS_LEV2 0x00000040U /*!< PVD level 2 */
+#define PWR_CR_PLS_LEV3 0x00000060U /*!< PVD level 3 */
+#define PWR_CR_PLS_LEV4 0x00000080U /*!< PVD level 4 */
+#define PWR_CR_PLS_LEV5 0x000000A0U /*!< PVD level 5 */
+#define PWR_CR_PLS_LEV6 0x000000C0U /*!< PVD level 6 */
+#define PWR_CR_PLS_LEV7 0x000000E0U /*!< PVD level 7 */
+
+#define PWR_CR_DBP 0x00000100U /*!< Disable Backup Domain write protection */
+#define PWR_CR_FPDS 0x00000200U /*!< Flash power down in Stop mode */
+#define PWR_CR_VOS 0x00004000U /*!< VOS bit (Regulator voltage scaling output selection) */
+
+/* Legacy define */
+#define PWR_CR_PMODE PWR_CR_VOS
+
+/******************* Bit definition for PWR_CSR register ********************/
+#define PWR_CSR_WUF 0x00000001U /*!< Wakeup Flag */
+#define PWR_CSR_SBF 0x00000002U /*!< Standby Flag */
+#define PWR_CSR_PVDO 0x00000004U /*!< PVD Output */
+#define PWR_CSR_BRR 0x00000008U /*!< Backup regulator ready */
+#define PWR_CSR_EWUP 0x00000100U /*!< Enable WKUP pin */
+#define PWR_CSR_BRE 0x00000200U /*!< Backup regulator enable */
+#define PWR_CSR_VOSRDY 0x00004000U /*!< Regulator voltage scaling output selection ready */
+
+/* Legacy define */
+#define PWR_CSR_REGRDY PWR_CSR_VOSRDY
+
+/******************************************************************************/
+/* */
+/* Reset and Clock Control */
+/* */
+/******************************************************************************/
+/******************** Bit definition for RCC_CR register ********************/
+#define RCC_CR_HSION 0x00000001U
+#define RCC_CR_HSIRDY 0x00000002U
+
+#define RCC_CR_HSITRIM 0x000000F8U
+#define RCC_CR_HSITRIM_0 0x00000008U/*!<Bit 0 */
+#define RCC_CR_HSITRIM_1 0x00000010U/*!<Bit 1 */
+#define RCC_CR_HSITRIM_2 0x00000020U/*!<Bit 2 */
+#define RCC_CR_HSITRIM_3 0x00000040U/*!<Bit 3 */
+#define RCC_CR_HSITRIM_4 0x00000080U/*!<Bit 4 */
+
+#define RCC_CR_HSICAL 0x0000FF00U
+#define RCC_CR_HSICAL_0 0x00000100U/*!<Bit 0 */
+#define RCC_CR_HSICAL_1 0x00000200U/*!<Bit 1 */
+#define RCC_CR_HSICAL_2 0x00000400U/*!<Bit 2 */
+#define RCC_CR_HSICAL_3 0x00000800U/*!<Bit 3 */
+#define RCC_CR_HSICAL_4 0x00001000U/*!<Bit 4 */
+#define RCC_CR_HSICAL_5 0x00002000U/*!<Bit 5 */
+#define RCC_CR_HSICAL_6 0x00004000U/*!<Bit 6 */
+#define RCC_CR_HSICAL_7 0x00008000U/*!<Bit 7 */
+
+#define RCC_CR_HSEON 0x00010000U
+#define RCC_CR_HSERDY 0x00020000U
+#define RCC_CR_HSEBYP 0x00040000U
+#define RCC_CR_CSSON 0x00080000U
+#define RCC_CR_PLLON 0x01000000U
+#define RCC_CR_PLLRDY 0x02000000U
+#define RCC_CR_PLLI2SON 0x04000000U
+#define RCC_CR_PLLI2SRDY 0x08000000U
+
+/******************** Bit definition for RCC_PLLCFGR register ***************/
+#define RCC_PLLCFGR_PLLM 0x0000003FU
+#define RCC_PLLCFGR_PLLM_0 0x00000001U
+#define RCC_PLLCFGR_PLLM_1 0x00000002U
+#define RCC_PLLCFGR_PLLM_2 0x00000004U
+#define RCC_PLLCFGR_PLLM_3 0x00000008U
+#define RCC_PLLCFGR_PLLM_4 0x00000010U
+#define RCC_PLLCFGR_PLLM_5 0x00000020U
+
+#define RCC_PLLCFGR_PLLN 0x00007FC0U
+#define RCC_PLLCFGR_PLLN_0 0x00000040U
+#define RCC_PLLCFGR_PLLN_1 0x00000080U
+#define RCC_PLLCFGR_PLLN_2 0x00000100U
+#define RCC_PLLCFGR_PLLN_3 0x00000200U
+#define RCC_PLLCFGR_PLLN_4 0x00000400U
+#define RCC_PLLCFGR_PLLN_5 0x00000800U
+#define RCC_PLLCFGR_PLLN_6 0x00001000U
+#define RCC_PLLCFGR_PLLN_7 0x00002000U
+#define RCC_PLLCFGR_PLLN_8 0x00004000U
+
+#define RCC_PLLCFGR_PLLP 0x00030000U
+#define RCC_PLLCFGR_PLLP_0 0x00010000U
+#define RCC_PLLCFGR_PLLP_1 0x00020000U
+
+#define RCC_PLLCFGR_PLLSRC 0x00400000U
+#define RCC_PLLCFGR_PLLSRC_HSE 0x00400000U
+#define RCC_PLLCFGR_PLLSRC_HSI 0x00000000U
+
+#define RCC_PLLCFGR_PLLQ 0x0F000000U
+#define RCC_PLLCFGR_PLLQ_0 0x01000000U
+#define RCC_PLLCFGR_PLLQ_1 0x02000000U
+#define RCC_PLLCFGR_PLLQ_2 0x04000000U
+#define RCC_PLLCFGR_PLLQ_3 0x08000000U
+
+/******************** Bit definition for RCC_CFGR register ******************/
+/*!< SW configuration */
+#define RCC_CFGR_SW 0x00000003U /*!< SW[1:0] bits (System clock Switch) */
+#define RCC_CFGR_SW_0 0x00000001U /*!< Bit 0 */
+#define RCC_CFGR_SW_1 0x00000002U /*!< Bit 1 */
+
+#define RCC_CFGR_SW_HSI 0x00000000U /*!< HSI selected as system clock */
+#define RCC_CFGR_SW_HSE 0x00000001U /*!< HSE selected as system clock */
+#define RCC_CFGR_SW_PLL 0x00000002U /*!< PLL selected as system clock */
+
+/*!< SWS configuration */
+#define RCC_CFGR_SWS 0x0000000CU /*!< SWS[1:0] bits (System Clock Switch Status) */
+#define RCC_CFGR_SWS_0 0x00000004U /*!< Bit 0 */
+#define RCC_CFGR_SWS_1 0x00000008U /*!< Bit 1 */
+
+#define RCC_CFGR_SWS_HSI 0x00000000U /*!< HSI oscillator used as system clock */
+#define RCC_CFGR_SWS_HSE 0x00000004U /*!< HSE oscillator used as system clock */
+#define RCC_CFGR_SWS_PLL 0x00000008U /*!< PLL used as system clock */
+
+/*!< HPRE configuration */
+#define RCC_CFGR_HPRE 0x000000F0U /*!< HPRE[3:0] bits (AHB prescaler) */
+#define RCC_CFGR_HPRE_0 0x00000010U /*!< Bit 0 */
+#define RCC_CFGR_HPRE_1 0x00000020U /*!< Bit 1 */
+#define RCC_CFGR_HPRE_2 0x00000040U /*!< Bit 2 */
+#define RCC_CFGR_HPRE_3 0x00000080U /*!< Bit 3 */
+
+#define RCC_CFGR_HPRE_DIV1 0x00000000U /*!< SYSCLK not divided */
+#define RCC_CFGR_HPRE_DIV2 0x00000080U /*!< SYSCLK divided by 2 */
+#define RCC_CFGR_HPRE_DIV4 0x00000090U /*!< SYSCLK divided by 4 */
+#define RCC_CFGR_HPRE_DIV8 0x000000A0U /*!< SYSCLK divided by 8 */
+#define RCC_CFGR_HPRE_DIV16 0x000000B0U /*!< SYSCLK divided by 16 */
+#define RCC_CFGR_HPRE_DIV64 0x000000C0U /*!< SYSCLK divided by 64 */
+#define RCC_CFGR_HPRE_DIV128 0x000000D0U /*!< SYSCLK divided by 128 */
+#define RCC_CFGR_HPRE_DIV256 0x000000E0U /*!< SYSCLK divided by 256 */
+#define RCC_CFGR_HPRE_DIV512 0x000000F0U /*!< SYSCLK divided by 512 */
+
+/*!< PPRE1 configuration */
+#define RCC_CFGR_PPRE1 0x00001C00U /*!< PRE1[2:0] bits (APB1 prescaler) */
+#define RCC_CFGR_PPRE1_0 0x00000400U /*!< Bit 0 */
+#define RCC_CFGR_PPRE1_1 0x00000800U /*!< Bit 1 */
+#define RCC_CFGR_PPRE1_2 0x00001000U /*!< Bit 2 */
+
+#define RCC_CFGR_PPRE1_DIV1 0x00000000U /*!< HCLK not divided */
+#define RCC_CFGR_PPRE1_DIV2 0x00001000U /*!< HCLK divided by 2 */
+#define RCC_CFGR_PPRE1_DIV4 0x00001400U /*!< HCLK divided by 4 */
+#define RCC_CFGR_PPRE1_DIV8 0x00001800U /*!< HCLK divided by 8 */
+#define RCC_CFGR_PPRE1_DIV16 0x00001C00U /*!< HCLK divided by 16 */
+
+/*!< PPRE2 configuration */
+#define RCC_CFGR_PPRE2 0x0000E000U /*!< PRE2[2:0] bits (APB2 prescaler) */
+#define RCC_CFGR_PPRE2_0 0x00002000U /*!< Bit 0 */
+#define RCC_CFGR_PPRE2_1 0x00004000U /*!< Bit 1 */
+#define RCC_CFGR_PPRE2_2 0x00008000U /*!< Bit 2 */
+
+#define RCC_CFGR_PPRE2_DIV1 0x00000000U /*!< HCLK not divided */
+#define RCC_CFGR_PPRE2_DIV2 0x00008000U /*!< HCLK divided by 2 */
+#define RCC_CFGR_PPRE2_DIV4 0x0000A000U /*!< HCLK divided by 4 */
+#define RCC_CFGR_PPRE2_DIV8 0x0000C000U /*!< HCLK divided by 8 */
+#define RCC_CFGR_PPRE2_DIV16 0x0000E000U /*!< HCLK divided by 16 */
+
+/*!< RTCPRE configuration */
+#define RCC_CFGR_RTCPRE 0x001F0000U
+#define RCC_CFGR_RTCPRE_0 0x00010000U
+#define RCC_CFGR_RTCPRE_1 0x00020000U
+#define RCC_CFGR_RTCPRE_2 0x00040000U
+#define RCC_CFGR_RTCPRE_3 0x00080000U
+#define RCC_CFGR_RTCPRE_4 0x00100000U
+
+/*!< MCO1 configuration */
+#define RCC_CFGR_MCO1 0x00600000U
+#define RCC_CFGR_MCO1_0 0x00200000U
+#define RCC_CFGR_MCO1_1 0x00400000U
+
+#define RCC_CFGR_I2SSRC 0x00800000U
+
+#define RCC_CFGR_MCO1PRE 0x07000000U
+#define RCC_CFGR_MCO1PRE_0 0x01000000U
+#define RCC_CFGR_MCO1PRE_1 0x02000000U
+#define RCC_CFGR_MCO1PRE_2 0x04000000U
+
+#define RCC_CFGR_MCO2PRE 0x38000000U
+#define RCC_CFGR_MCO2PRE_0 0x08000000U
+#define RCC_CFGR_MCO2PRE_1 0x10000000U
+#define RCC_CFGR_MCO2PRE_2 0x20000000U
+
+#define RCC_CFGR_MCO2 0xC0000000U
+#define RCC_CFGR_MCO2_0 0x40000000U
+#define RCC_CFGR_MCO2_1 0x80000000U
+
+/******************** Bit definition for RCC_CIR register *******************/
+#define RCC_CIR_LSIRDYF 0x00000001U
+#define RCC_CIR_LSERDYF 0x00000002U
+#define RCC_CIR_HSIRDYF 0x00000004U
+#define RCC_CIR_HSERDYF 0x00000008U
+#define RCC_CIR_PLLRDYF 0x00000010U
+#define RCC_CIR_PLLI2SRDYF 0x00000020U
+
+#define RCC_CIR_CSSF 0x00000080U
+#define RCC_CIR_LSIRDYIE 0x00000100U
+#define RCC_CIR_LSERDYIE 0x00000200U
+#define RCC_CIR_HSIRDYIE 0x00000400U
+#define RCC_CIR_HSERDYIE 0x00000800U
+#define RCC_CIR_PLLRDYIE 0x00001000U
+#define RCC_CIR_PLLI2SRDYIE 0x00002000U
+
+#define RCC_CIR_LSIRDYC 0x00010000U
+#define RCC_CIR_LSERDYC 0x00020000U
+#define RCC_CIR_HSIRDYC 0x00040000U
+#define RCC_CIR_HSERDYC 0x00080000U
+#define RCC_CIR_PLLRDYC 0x00100000U
+#define RCC_CIR_PLLI2SRDYC 0x00200000U
+
+#define RCC_CIR_CSSC 0x00800000U
+
+/******************** Bit definition for RCC_AHB1RSTR register **************/
+#define RCC_AHB1RSTR_GPIOARST 0x00000001U
+#define RCC_AHB1RSTR_GPIOBRST 0x00000002U
+#define RCC_AHB1RSTR_GPIOCRST 0x00000004U
+#define RCC_AHB1RSTR_GPIODRST 0x00000008U
+#define RCC_AHB1RSTR_GPIOERST 0x00000010U
+#define RCC_AHB1RSTR_GPIOFRST 0x00000020U
+#define RCC_AHB1RSTR_GPIOGRST 0x00000040U
+#define RCC_AHB1RSTR_GPIOHRST 0x00000080U
+#define RCC_AHB1RSTR_GPIOIRST 0x00000100U
+#define RCC_AHB1RSTR_CRCRST 0x00001000U
+#define RCC_AHB1RSTR_DMA1RST 0x00200000U
+#define RCC_AHB1RSTR_DMA2RST 0x00400000U
+#define RCC_AHB1RSTR_OTGHRST 0x20000000U
+
+/******************** Bit definition for RCC_AHB2RSTR register **************/
+#define RCC_AHB2RSTR_RNGRST 0x00000040U
+#define RCC_AHB2RSTR_OTGFSRST 0x00000080U
+
+/******************** Bit definition for RCC_AHB3RSTR register **************/
+
+#define RCC_AHB3RSTR_FSMCRST 0x00000001U
+
+/******************** Bit definition for RCC_APB1RSTR register **************/
+#define RCC_APB1RSTR_TIM2RST 0x00000001U
+#define RCC_APB1RSTR_TIM3RST 0x00000002U
+#define RCC_APB1RSTR_TIM4RST 0x00000004U
+#define RCC_APB1RSTR_TIM5RST 0x00000008U
+#define RCC_APB1RSTR_TIM6RST 0x00000010U
+#define RCC_APB1RSTR_TIM7RST 0x00000020U
+#define RCC_APB1RSTR_TIM12RST 0x00000040U
+#define RCC_APB1RSTR_TIM13RST 0x00000080U
+#define RCC_APB1RSTR_TIM14RST 0x00000100U
+#define RCC_APB1RSTR_WWDGRST 0x00000800U
+#define RCC_APB1RSTR_SPI2RST 0x00004000U
+#define RCC_APB1RSTR_SPI3RST 0x00008000U
+#define RCC_APB1RSTR_USART2RST 0x00020000U
+#define RCC_APB1RSTR_USART3RST 0x00040000U
+#define RCC_APB1RSTR_UART4RST 0x00080000U
+#define RCC_APB1RSTR_UART5RST 0x00100000U
+#define RCC_APB1RSTR_I2C1RST 0x00200000U
+#define RCC_APB1RSTR_I2C2RST 0x00400000U
+#define RCC_APB1RSTR_I2C3RST 0x00800000U
+#define RCC_APB1RSTR_CAN1RST 0x02000000U
+#define RCC_APB1RSTR_CAN2RST 0x04000000U
+#define RCC_APB1RSTR_PWRRST 0x10000000U
+#define RCC_APB1RSTR_DACRST 0x20000000U
+
+/******************** Bit definition for RCC_APB2RSTR register **************/
+#define RCC_APB2RSTR_TIM1RST 0x00000001U
+#define RCC_APB2RSTR_TIM8RST 0x00000002U
+#define RCC_APB2RSTR_USART1RST 0x00000010U
+#define RCC_APB2RSTR_USART6RST 0x00000020U
+#define RCC_APB2RSTR_ADCRST 0x00000100U
+#define RCC_APB2RSTR_SDIORST 0x00000800U
+#define RCC_APB2RSTR_SPI1RST 0x00001000U
+#define RCC_APB2RSTR_SYSCFGRST 0x00004000U
+#define RCC_APB2RSTR_TIM9RST 0x00010000U
+#define RCC_APB2RSTR_TIM10RST 0x00020000U
+#define RCC_APB2RSTR_TIM11RST 0x00040000U
+
+/* Old SPI1RST bit definition, maintained for legacy purpose */
+#define RCC_APB2RSTR_SPI1 RCC_APB2RSTR_SPI1RST
+
+/******************** Bit definition for RCC_AHB1ENR register ***************/
+#define RCC_AHB1ENR_GPIOAEN 0x00000001U
+#define RCC_AHB1ENR_GPIOBEN 0x00000002U
+#define RCC_AHB1ENR_GPIOCEN 0x00000004U
+#define RCC_AHB1ENR_GPIODEN 0x00000008U
+#define RCC_AHB1ENR_GPIOEEN 0x00000010U
+#define RCC_AHB1ENR_GPIOFEN 0x00000020U
+#define RCC_AHB1ENR_GPIOGEN 0x00000040U
+#define RCC_AHB1ENR_GPIOHEN 0x00000080U
+#define RCC_AHB1ENR_GPIOIEN 0x00000100U
+#define RCC_AHB1ENR_CRCEN 0x00001000U
+#define RCC_AHB1ENR_BKPSRAMEN 0x00040000U
+#define RCC_AHB1ENR_CCMDATARAMEN 0x00100000U
+#define RCC_AHB1ENR_DMA1EN 0x00200000U
+#define RCC_AHB1ENR_DMA2EN 0x00400000U
+
+#define RCC_AHB1ENR_OTGHSEN 0x20000000U
+#define RCC_AHB1ENR_OTGHSULPIEN 0x40000000U
+
+/******************** Bit definition for RCC_AHB2ENR register ***************/
+#define RCC_AHB2ENR_RNGEN 0x00000040U
+#define RCC_AHB2ENR_OTGFSEN 0x00000080U
+
+/******************** Bit definition for RCC_AHB3ENR register ***************/
+
+#define RCC_AHB3ENR_FSMCEN 0x00000001U
+
+/******************** Bit definition for RCC_APB1ENR register ***************/
+#define RCC_APB1ENR_TIM2EN 0x00000001U
+#define RCC_APB1ENR_TIM3EN 0x00000002U
+#define RCC_APB1ENR_TIM4EN 0x00000004U
+#define RCC_APB1ENR_TIM5EN 0x00000008U
+#define RCC_APB1ENR_TIM6EN 0x00000010U
+#define RCC_APB1ENR_TIM7EN 0x00000020U
+#define RCC_APB1ENR_TIM12EN 0x00000040U
+#define RCC_APB1ENR_TIM13EN 0x00000080U
+#define RCC_APB1ENR_TIM14EN 0x00000100U
+#define RCC_APB1ENR_WWDGEN 0x00000800U
+#define RCC_APB1ENR_SPI2EN 0x00004000U
+#define RCC_APB1ENR_SPI3EN 0x00008000U
+#define RCC_APB1ENR_USART2EN 0x00020000U
+#define RCC_APB1ENR_USART3EN 0x00040000U
+#define RCC_APB1ENR_UART4EN 0x00080000U
+#define RCC_APB1ENR_UART5EN 0x00100000U
+#define RCC_APB1ENR_I2C1EN 0x00200000U
+#define RCC_APB1ENR_I2C2EN 0x00400000U
+#define RCC_APB1ENR_I2C3EN 0x00800000U
+#define RCC_APB1ENR_CAN1EN 0x02000000U
+#define RCC_APB1ENR_CAN2EN 0x04000000U
+#define RCC_APB1ENR_PWREN 0x10000000U
+#define RCC_APB1ENR_DACEN 0x20000000U
+
+/******************** Bit definition for RCC_APB2ENR register ***************/
+#define RCC_APB2ENR_TIM1EN 0x00000001U
+#define RCC_APB2ENR_TIM8EN 0x00000002U
+#define RCC_APB2ENR_USART1EN 0x00000010U
+#define RCC_APB2ENR_USART6EN 0x00000020U
+#define RCC_APB2ENR_ADC1EN 0x00000100U
+#define RCC_APB2ENR_ADC2EN 0x00000200U
+#define RCC_APB2ENR_ADC3EN 0x00000400U
+#define RCC_APB2ENR_SDIOEN 0x00000800U
+#define RCC_APB2ENR_SPI1EN 0x00001000U
+#define RCC_APB2ENR_SYSCFGEN 0x00004000U
+#define RCC_APB2ENR_TIM9EN 0x00010000U
+#define RCC_APB2ENR_TIM10EN 0x00020000U
+#define RCC_APB2ENR_TIM11EN 0x00040000U
+#define RCC_APB2ENR_SPI5EN 0x00100000U
+#define RCC_APB2ENR_SPI6EN 0x00200000U
+
+/******************** Bit definition for RCC_AHB1LPENR register *************/
+#define RCC_AHB1LPENR_GPIOALPEN 0x00000001U
+#define RCC_AHB1LPENR_GPIOBLPEN 0x00000002U
+#define RCC_AHB1LPENR_GPIOCLPEN 0x00000004U
+#define RCC_AHB1LPENR_GPIODLPEN 0x00000008U
+#define RCC_AHB1LPENR_GPIOELPEN 0x00000010U
+#define RCC_AHB1LPENR_GPIOFLPEN 0x00000020U
+#define RCC_AHB1LPENR_GPIOGLPEN 0x00000040U
+#define RCC_AHB1LPENR_GPIOHLPEN 0x00000080U
+#define RCC_AHB1LPENR_GPIOILPEN 0x00000100U
+#define RCC_AHB1LPENR_CRCLPEN 0x00001000U
+#define RCC_AHB1LPENR_FLITFLPEN 0x00008000U
+#define RCC_AHB1LPENR_SRAM1LPEN 0x00010000U
+#define RCC_AHB1LPENR_SRAM2LPEN 0x00020000U
+#define RCC_AHB1LPENR_BKPSRAMLPEN 0x00040000U
+#define RCC_AHB1LPENR_DMA1LPEN 0x00200000U
+#define RCC_AHB1LPENR_DMA2LPEN 0x00400000U
+#define RCC_AHB1LPENR_OTGHSLPEN 0x20000000U
+#define RCC_AHB1LPENR_OTGHSULPILPEN 0x40000000U
+
+/******************** Bit definition for RCC_AHB2LPENR register *************/
+#define RCC_AHB2LPENR_RNGLPEN 0x00000040U
+#define RCC_AHB2LPENR_OTGFSLPEN 0x00000080U
+
+/******************** Bit definition for RCC_AHB3LPENR register *************/
+
+#define RCC_AHB3LPENR_FSMCLPEN 0x00000001U
+
+/******************** Bit definition for RCC_APB1LPENR register *************/
+#define RCC_APB1LPENR_TIM2LPEN 0x00000001U
+#define RCC_APB1LPENR_TIM3LPEN 0x00000002U
+#define RCC_APB1LPENR_TIM4LPEN 0x00000004U
+#define RCC_APB1LPENR_TIM5LPEN 0x00000008U
+#define RCC_APB1LPENR_TIM6LPEN 0x00000010U
+#define RCC_APB1LPENR_TIM7LPEN 0x00000020U
+#define RCC_APB1LPENR_TIM12LPEN 0x00000040U
+#define RCC_APB1LPENR_TIM13LPEN 0x00000080U
+#define RCC_APB1LPENR_TIM14LPEN 0x00000100U
+#define RCC_APB1LPENR_WWDGLPEN 0x00000800U
+#define RCC_APB1LPENR_SPI2LPEN 0x00004000U
+#define RCC_APB1LPENR_SPI3LPEN 0x00008000U
+#define RCC_APB1LPENR_USART2LPEN 0x00020000U
+#define RCC_APB1LPENR_USART3LPEN 0x00040000U
+#define RCC_APB1LPENR_UART4LPEN 0x00080000U
+#define RCC_APB1LPENR_UART5LPEN 0x00100000U
+#define RCC_APB1LPENR_I2C1LPEN 0x00200000U
+#define RCC_APB1LPENR_I2C2LPEN 0x00400000U
+#define RCC_APB1LPENR_I2C3LPEN 0x00800000U
+#define RCC_APB1LPENR_CAN1LPEN 0x02000000U
+#define RCC_APB1LPENR_CAN2LPEN 0x04000000U
+#define RCC_APB1LPENR_PWRLPEN 0x10000000U
+#define RCC_APB1LPENR_DACLPEN 0x20000000U
+
+/******************** Bit definition for RCC_APB2LPENR register *************/
+#define RCC_APB2LPENR_TIM1LPEN 0x00000001U
+#define RCC_APB2LPENR_TIM8LPEN 0x00000002U
+#define RCC_APB2LPENR_USART1LPEN 0x00000010U
+#define RCC_APB2LPENR_USART6LPEN 0x00000020U
+#define RCC_APB2LPENR_ADC1LPEN 0x00000100U
+#define RCC_APB2LPENR_ADC2LPEN 0x00000200U
+#define RCC_APB2LPENR_ADC3LPEN 0x00000400U
+#define RCC_APB2LPENR_SDIOLPEN 0x00000800U
+#define RCC_APB2LPENR_SPI1LPEN 0x00001000U
+#define RCC_APB2LPENR_SYSCFGLPEN 0x00004000U
+#define RCC_APB2LPENR_TIM9LPEN 0x00010000U
+#define RCC_APB2LPENR_TIM10LPEN 0x00020000U
+#define RCC_APB2LPENR_TIM11LPEN 0x00040000U
+
+/******************** Bit definition for RCC_BDCR register ******************/
+#define RCC_BDCR_LSEON 0x00000001U
+#define RCC_BDCR_LSERDY 0x00000002U
+#define RCC_BDCR_LSEBYP 0x00000004U
+
+#define RCC_BDCR_RTCSEL 0x00000300U
+#define RCC_BDCR_RTCSEL_0 0x00000100U
+#define RCC_BDCR_RTCSEL_1 0x00000200U
+
+#define RCC_BDCR_RTCEN 0x00008000U
+#define RCC_BDCR_BDRST 0x00010000U
+
+/******************** Bit definition for RCC_CSR register *******************/
+#define RCC_CSR_LSION 0x00000001U
+#define RCC_CSR_LSIRDY 0x00000002U
+#define RCC_CSR_RMVF 0x01000000U
+#define RCC_CSR_BORRSTF 0x02000000U
+#define RCC_CSR_PADRSTF 0x04000000U
+#define RCC_CSR_PORRSTF 0x08000000U
+#define RCC_CSR_SFTRSTF 0x10000000U
+#define RCC_CSR_WDGRSTF 0x20000000U
+#define RCC_CSR_WWDGRSTF 0x40000000U
+#define RCC_CSR_LPWRRSTF 0x80000000U
+
+/******************** Bit definition for RCC_SSCGR register *****************/
+#define RCC_SSCGR_MODPER 0x00001FFFU
+#define RCC_SSCGR_INCSTEP 0x0FFFE000U
+#define RCC_SSCGR_SPREADSEL 0x40000000U
+#define RCC_SSCGR_SSCGEN 0x80000000U
+
+/******************** Bit definition for RCC_PLLI2SCFGR register ************/
+#define RCC_PLLI2SCFGR_PLLI2SN 0x00007FC0U
+#define RCC_PLLI2SCFGR_PLLI2SN_0 0x00000040U
+#define RCC_PLLI2SCFGR_PLLI2SN_1 0x00000080U
+#define RCC_PLLI2SCFGR_PLLI2SN_2 0x00000100U
+#define RCC_PLLI2SCFGR_PLLI2SN_3 0x00000200U
+#define RCC_PLLI2SCFGR_PLLI2SN_4 0x00000400U
+#define RCC_PLLI2SCFGR_PLLI2SN_5 0x00000800U
+#define RCC_PLLI2SCFGR_PLLI2SN_6 0x00001000U
+#define RCC_PLLI2SCFGR_PLLI2SN_7 0x00002000U
+#define RCC_PLLI2SCFGR_PLLI2SN_8 0x00004000U
+
+#define RCC_PLLI2SCFGR_PLLI2SR 0x70000000U
+#define RCC_PLLI2SCFGR_PLLI2SR_0 0x10000000U
+#define RCC_PLLI2SCFGR_PLLI2SR_1 0x20000000U
+#define RCC_PLLI2SCFGR_PLLI2SR_2 0x40000000U
+
+/******************************************************************************/
+/* */
+/* RNG */
+/* */
+/******************************************************************************/
+/******************** Bits definition for RNG_CR register *******************/
+#define RNG_CR_RNGEN 0x00000004U
+#define RNG_CR_IE 0x00000008U
+
+/******************** Bits definition for RNG_SR register *******************/
+#define RNG_SR_DRDY 0x00000001U
+#define RNG_SR_CECS 0x00000002U
+#define RNG_SR_SECS 0x00000004U
+#define RNG_SR_CEIS 0x00000020U
+#define RNG_SR_SEIS 0x00000040U
+
+/******************************************************************************/
+/* */
+/* Real-Time Clock (RTC) */
+/* */
+/******************************************************************************/
+/******************** Bits definition for RTC_TR register *******************/
+#define RTC_TR_PM 0x00400000U
+#define RTC_TR_HT 0x00300000U
+#define RTC_TR_HT_0 0x00100000U
+#define RTC_TR_HT_1 0x00200000U
+#define RTC_TR_HU 0x000F0000U
+#define RTC_TR_HU_0 0x00010000U
+#define RTC_TR_HU_1 0x00020000U
+#define RTC_TR_HU_2 0x00040000U
+#define RTC_TR_HU_3 0x00080000U
+#define RTC_TR_MNT 0x00007000U
+#define RTC_TR_MNT_0 0x00001000U
+#define RTC_TR_MNT_1 0x00002000U
+#define RTC_TR_MNT_2 0x00004000U
+#define RTC_TR_MNU 0x00000F00U
+#define RTC_TR_MNU_0 0x00000100U
+#define RTC_TR_MNU_1 0x00000200U
+#define RTC_TR_MNU_2 0x00000400U
+#define RTC_TR_MNU_3 0x00000800U
+#define RTC_TR_ST 0x00000070U
+#define RTC_TR_ST_0 0x00000010U
+#define RTC_TR_ST_1 0x00000020U
+#define RTC_TR_ST_2 0x00000040U
+#define RTC_TR_SU 0x0000000FU
+#define RTC_TR_SU_0 0x00000001U
+#define RTC_TR_SU_1 0x00000002U
+#define RTC_TR_SU_2 0x00000004U
+#define RTC_TR_SU_3 0x00000008U
+
+/******************** Bits definition for RTC_DR register *******************/
+#define RTC_DR_YT 0x00F00000U
+#define RTC_DR_YT_0 0x00100000U
+#define RTC_DR_YT_1 0x00200000U
+#define RTC_DR_YT_2 0x00400000U
+#define RTC_DR_YT_3 0x00800000U
+#define RTC_DR_YU 0x000F0000U
+#define RTC_DR_YU_0 0x00010000U
+#define RTC_DR_YU_1 0x00020000U
+#define RTC_DR_YU_2 0x00040000U
+#define RTC_DR_YU_3 0x00080000U
+#define RTC_DR_WDU 0x0000E000U
+#define RTC_DR_WDU_0 0x00002000U
+#define RTC_DR_WDU_1 0x00004000U
+#define RTC_DR_WDU_2 0x00008000U
+#define RTC_DR_MT 0x00001000U
+#define RTC_DR_MU 0x00000F00U
+#define RTC_DR_MU_0 0x00000100U
+#define RTC_DR_MU_1 0x00000200U
+#define RTC_DR_MU_2 0x00000400U
+#define RTC_DR_MU_3 0x00000800U
+#define RTC_DR_DT 0x00000030U
+#define RTC_DR_DT_0 0x00000010U
+#define RTC_DR_DT_1 0x00000020U
+#define RTC_DR_DU 0x0000000FU
+#define RTC_DR_DU_0 0x00000001U
+#define RTC_DR_DU_1 0x00000002U
+#define RTC_DR_DU_2 0x00000004U
+#define RTC_DR_DU_3 0x00000008U
+
+/******************** Bits definition for RTC_CR register *******************/
+#define RTC_CR_COE 0x00800000U
+#define RTC_CR_OSEL 0x00600000U
+#define RTC_CR_OSEL_0 0x00200000U
+#define RTC_CR_OSEL_1 0x00400000U
+#define RTC_CR_POL 0x00100000U
+#define RTC_CR_COSEL 0x00080000U
+#define RTC_CR_BCK 0x00040000U
+#define RTC_CR_SUB1H 0x00020000U
+#define RTC_CR_ADD1H 0x00010000U
+#define RTC_CR_TSIE 0x00008000U
+#define RTC_CR_WUTIE 0x00004000U
+#define RTC_CR_ALRBIE 0x00002000U
+#define RTC_CR_ALRAIE 0x00001000U
+#define RTC_CR_TSE 0x00000800U
+#define RTC_CR_WUTE 0x00000400U
+#define RTC_CR_ALRBE 0x00000200U
+#define RTC_CR_ALRAE 0x00000100U
+#define RTC_CR_DCE 0x00000080U
+#define RTC_CR_FMT 0x00000040U
+#define RTC_CR_BYPSHAD 0x00000020U
+#define RTC_CR_REFCKON 0x00000010U
+#define RTC_CR_TSEDGE 0x00000008U
+#define RTC_CR_WUCKSEL 0x00000007U
+#define RTC_CR_WUCKSEL_0 0x00000001U
+#define RTC_CR_WUCKSEL_1 0x00000002U
+#define RTC_CR_WUCKSEL_2 0x00000004U
+
+/******************** Bits definition for RTC_ISR register ******************/
+#define RTC_ISR_RECALPF 0x00010000U
+#define RTC_ISR_TAMP1F 0x00002000U
+#define RTC_ISR_TAMP2F 0x00004000U
+#define RTC_ISR_TSOVF 0x00001000U
+#define RTC_ISR_TSF 0x00000800U
+#define RTC_ISR_WUTF 0x00000400U
+#define RTC_ISR_ALRBF 0x00000200U
+#define RTC_ISR_ALRAF 0x00000100U
+#define RTC_ISR_INIT 0x00000080U
+#define RTC_ISR_INITF 0x00000040U
+#define RTC_ISR_RSF 0x00000020U
+#define RTC_ISR_INITS 0x00000010U
+#define RTC_ISR_SHPF 0x00000008U
+#define RTC_ISR_WUTWF 0x00000004U
+#define RTC_ISR_ALRBWF 0x00000002U
+#define RTC_ISR_ALRAWF 0x00000001U
+
+/******************** Bits definition for RTC_PRER register *****************/
+#define RTC_PRER_PREDIV_A 0x007F0000U
+#define RTC_PRER_PREDIV_S 0x00007FFFU
+
+/******************** Bits definition for RTC_WUTR register *****************/
+#define RTC_WUTR_WUT 0x0000FFFFU
+
+/******************** Bits definition for RTC_CALIBR register ***************/
+#define RTC_CALIBR_DCS 0x00000080U
+#define RTC_CALIBR_DC 0x0000001FU
+
+/******************** Bits definition for RTC_ALRMAR register ***************/
+#define RTC_ALRMAR_MSK4 0x80000000U
+#define RTC_ALRMAR_WDSEL 0x40000000U
+#define RTC_ALRMAR_DT 0x30000000U
+#define RTC_ALRMAR_DT_0 0x10000000U
+#define RTC_ALRMAR_DT_1 0x20000000U
+#define RTC_ALRMAR_DU 0x0F000000U
+#define RTC_ALRMAR_DU_0 0x01000000U
+#define RTC_ALRMAR_DU_1 0x02000000U
+#define RTC_ALRMAR_DU_2 0x04000000U
+#define RTC_ALRMAR_DU_3 0x08000000U
+#define RTC_ALRMAR_MSK3 0x00800000U
+#define RTC_ALRMAR_PM 0x00400000U
+#define RTC_ALRMAR_HT 0x00300000U
+#define RTC_ALRMAR_HT_0 0x00100000U
+#define RTC_ALRMAR_HT_1 0x00200000U
+#define RTC_ALRMAR_HU 0x000F0000U
+#define RTC_ALRMAR_HU_0 0x00010000U
+#define RTC_ALRMAR_HU_1 0x00020000U
+#define RTC_ALRMAR_HU_2 0x00040000U
+#define RTC_ALRMAR_HU_3 0x00080000U
+#define RTC_ALRMAR_MSK2 0x00008000U
+#define RTC_ALRMAR_MNT 0x00007000U
+#define RTC_ALRMAR_MNT_0 0x00001000U
+#define RTC_ALRMAR_MNT_1 0x00002000U
+#define RTC_ALRMAR_MNT_2 0x00004000U
+#define RTC_ALRMAR_MNU 0x00000F00U
+#define RTC_ALRMAR_MNU_0 0x00000100U
+#define RTC_ALRMAR_MNU_1 0x00000200U
+#define RTC_ALRMAR_MNU_2 0x00000400U
+#define RTC_ALRMAR_MNU_3 0x00000800U
+#define RTC_ALRMAR_MSK1 0x00000080U
+#define RTC_ALRMAR_ST 0x00000070U
+#define RTC_ALRMAR_ST_0 0x00000010U
+#define RTC_ALRMAR_ST_1 0x00000020U
+#define RTC_ALRMAR_ST_2 0x00000040U
+#define RTC_ALRMAR_SU 0x0000000FU
+#define RTC_ALRMAR_SU_0 0x00000001U
+#define RTC_ALRMAR_SU_1 0x00000002U
+#define RTC_ALRMAR_SU_2 0x00000004U
+#define RTC_ALRMAR_SU_3 0x00000008U
+
+/******************** Bits definition for RTC_ALRMBR register ***************/
+#define RTC_ALRMBR_MSK4 0x80000000U
+#define RTC_ALRMBR_WDSEL 0x40000000U
+#define RTC_ALRMBR_DT 0x30000000U
+#define RTC_ALRMBR_DT_0 0x10000000U
+#define RTC_ALRMBR_DT_1 0x20000000U
+#define RTC_ALRMBR_DU 0x0F000000U
+#define RTC_ALRMBR_DU_0 0x01000000U
+#define RTC_ALRMBR_DU_1 0x02000000U
+#define RTC_ALRMBR_DU_2 0x04000000U
+#define RTC_ALRMBR_DU_3 0x08000000U
+#define RTC_ALRMBR_MSK3 0x00800000U
+#define RTC_ALRMBR_PM 0x00400000U
+#define RTC_ALRMBR_HT 0x00300000U
+#define RTC_ALRMBR_HT_0 0x00100000U
+#define RTC_ALRMBR_HT_1 0x00200000U
+#define RTC_ALRMBR_HU 0x000F0000U
+#define RTC_ALRMBR_HU_0 0x00010000U
+#define RTC_ALRMBR_HU_1 0x00020000U
+#define RTC_ALRMBR_HU_2 0x00040000U
+#define RTC_ALRMBR_HU_3 0x00080000U
+#define RTC_ALRMBR_MSK2 0x00008000U
+#define RTC_ALRMBR_MNT 0x00007000U
+#define RTC_ALRMBR_MNT_0 0x00001000U
+#define RTC_ALRMBR_MNT_1 0x00002000U
+#define RTC_ALRMBR_MNT_2 0x00004000U
+#define RTC_ALRMBR_MNU 0x00000F00U
+#define RTC_ALRMBR_MNU_0 0x00000100U
+#define RTC_ALRMBR_MNU_1 0x00000200U
+#define RTC_ALRMBR_MNU_2 0x00000400U
+#define RTC_ALRMBR_MNU_3 0x00000800U
+#define RTC_ALRMBR_MSK1 0x00000080U
+#define RTC_ALRMBR_ST 0x00000070U
+#define RTC_ALRMBR_ST_0 0x00000010U
+#define RTC_ALRMBR_ST_1 0x00000020U
+#define RTC_ALRMBR_ST_2 0x00000040U
+#define RTC_ALRMBR_SU 0x0000000FU
+#define RTC_ALRMBR_SU_0 0x00000001U
+#define RTC_ALRMBR_SU_1 0x00000002U
+#define RTC_ALRMBR_SU_2 0x00000004U
+#define RTC_ALRMBR_SU_3 0x00000008U
+
+/******************** Bits definition for RTC_WPR register ******************/
+#define RTC_WPR_KEY 0x000000FFU
+
+/******************** Bits definition for RTC_SSR register ******************/
+#define RTC_SSR_SS 0x0000FFFFU
+
+/******************** Bits definition for RTC_SHIFTR register ***************/
+#define RTC_SHIFTR_SUBFS 0x00007FFFU
+#define RTC_SHIFTR_ADD1S 0x80000000U
+
+/******************** Bits definition for RTC_TSTR register *****************/
+#define RTC_TSTR_PM 0x00400000U
+#define RTC_TSTR_HT 0x00300000U
+#define RTC_TSTR_HT_0 0x00100000U
+#define RTC_TSTR_HT_1 0x00200000U
+#define RTC_TSTR_HU 0x000F0000U
+#define RTC_TSTR_HU_0 0x00010000U
+#define RTC_TSTR_HU_1 0x00020000U
+#define RTC_TSTR_HU_2 0x00040000U
+#define RTC_TSTR_HU_3 0x00080000U
+#define RTC_TSTR_MNT 0x00007000U
+#define RTC_TSTR_MNT_0 0x00001000U
+#define RTC_TSTR_MNT_1 0x00002000U
+#define RTC_TSTR_MNT_2 0x00004000U
+#define RTC_TSTR_MNU 0x00000F00U
+#define RTC_TSTR_MNU_0 0x00000100U
+#define RTC_TSTR_MNU_1 0x00000200U
+#define RTC_TSTR_MNU_2 0x00000400U
+#define RTC_TSTR_MNU_3 0x00000800U
+#define RTC_TSTR_ST 0x00000070U
+#define RTC_TSTR_ST_0 0x00000010U
+#define RTC_TSTR_ST_1 0x00000020U
+#define RTC_TSTR_ST_2 0x00000040U
+#define RTC_TSTR_SU 0x0000000FU
+#define RTC_TSTR_SU_0 0x00000001U
+#define RTC_TSTR_SU_1 0x00000002U
+#define RTC_TSTR_SU_2 0x00000004U
+#define RTC_TSTR_SU_3 0x00000008U
+
+/******************** Bits definition for RTC_TSDR register *****************/
+#define RTC_TSDR_WDU 0x0000E000U
+#define RTC_TSDR_WDU_0 0x00002000U
+#define RTC_TSDR_WDU_1 0x00004000U
+#define RTC_TSDR_WDU_2 0x00008000U
+#define RTC_TSDR_MT 0x00001000U
+#define RTC_TSDR_MU 0x00000F00U
+#define RTC_TSDR_MU_0 0x00000100U
+#define RTC_TSDR_MU_1 0x00000200U
+#define RTC_TSDR_MU_2 0x00000400U
+#define RTC_TSDR_MU_3 0x00000800U
+#define RTC_TSDR_DT 0x00000030U
+#define RTC_TSDR_DT_0 0x00000010U
+#define RTC_TSDR_DT_1 0x00000020U
+#define RTC_TSDR_DU 0x0000000FU
+#define RTC_TSDR_DU_0 0x00000001U
+#define RTC_TSDR_DU_1 0x00000002U
+#define RTC_TSDR_DU_2 0x00000004U
+#define RTC_TSDR_DU_3 0x00000008U
+
+/******************** Bits definition for RTC_TSSSR register ****************/
+#define RTC_TSSSR_SS 0x0000FFFFU
+
+/******************** Bits definition for RTC_CAL register *****************/
+#define RTC_CALR_CALP 0x00008000U
+#define RTC_CALR_CALW8 0x00004000U
+#define RTC_CALR_CALW16 0x00002000U
+#define RTC_CALR_CALM 0x000001FFU
+#define RTC_CALR_CALM_0 0x00000001U
+#define RTC_CALR_CALM_1 0x00000002U
+#define RTC_CALR_CALM_2 0x00000004U
+#define RTC_CALR_CALM_3 0x00000008U
+#define RTC_CALR_CALM_4 0x00000010U
+#define RTC_CALR_CALM_5 0x00000020U
+#define RTC_CALR_CALM_6 0x00000040U
+#define RTC_CALR_CALM_7 0x00000080U
+#define RTC_CALR_CALM_8 0x00000100U
+
+/******************** Bits definition for RTC_TAFCR register ****************/
+#define RTC_TAFCR_ALARMOUTTYPE 0x00040000U
+#define RTC_TAFCR_TSINSEL 0x00020000U
+#define RTC_TAFCR_TAMPINSEL 0x00010000U
+#define RTC_TAFCR_TAMPPUDIS 0x00008000U
+#define RTC_TAFCR_TAMPPRCH 0x00006000U
+#define RTC_TAFCR_TAMPPRCH_0 0x00002000U
+#define RTC_TAFCR_TAMPPRCH_1 0x00004000U
+#define RTC_TAFCR_TAMPFLT 0x00001800U
+#define RTC_TAFCR_TAMPFLT_0 0x00000800U
+#define RTC_TAFCR_TAMPFLT_1 0x00001000U
+#define RTC_TAFCR_TAMPFREQ 0x00000700U
+#define RTC_TAFCR_TAMPFREQ_0 0x00000100U
+#define RTC_TAFCR_TAMPFREQ_1 0x00000200U
+#define RTC_TAFCR_TAMPFREQ_2 0x00000400U
+#define RTC_TAFCR_TAMPTS 0x00000080U
+#define RTC_TAFCR_TAMP2TRG 0x00000010U
+#define RTC_TAFCR_TAMP2E 0x00000008U
+#define RTC_TAFCR_TAMPIE 0x00000004U
+#define RTC_TAFCR_TAMP1TRG 0x00000002U
+#define RTC_TAFCR_TAMP1E 0x00000001U
+
+/******************** Bits definition for RTC_ALRMASSR register *************/
+#define RTC_ALRMASSR_MASKSS 0x0F000000U
+#define RTC_ALRMASSR_MASKSS_0 0x01000000U
+#define RTC_ALRMASSR_MASKSS_1 0x02000000U
+#define RTC_ALRMASSR_MASKSS_2 0x04000000U
+#define RTC_ALRMASSR_MASKSS_3 0x08000000U
+#define RTC_ALRMASSR_SS 0x00007FFFU
+
+/******************** Bits definition for RTC_ALRMBSSR register *************/
+#define RTC_ALRMBSSR_MASKSS 0x0F000000U
+#define RTC_ALRMBSSR_MASKSS_0 0x01000000U
+#define RTC_ALRMBSSR_MASKSS_1 0x02000000U
+#define RTC_ALRMBSSR_MASKSS_2 0x04000000U
+#define RTC_ALRMBSSR_MASKSS_3 0x08000000U
+#define RTC_ALRMBSSR_SS 0x00007FFFU
+
+/******************** Bits definition for RTC_BKP0R register ****************/
+#define RTC_BKP0R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP1R register ****************/
+#define RTC_BKP1R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP2R register ****************/
+#define RTC_BKP2R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP3R register ****************/
+#define RTC_BKP3R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP4R register ****************/
+#define RTC_BKP4R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP5R register ****************/
+#define RTC_BKP5R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP6R register ****************/
+#define RTC_BKP6R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP7R register ****************/
+#define RTC_BKP7R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP8R register ****************/
+#define RTC_BKP8R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP9R register ****************/
+#define RTC_BKP9R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP10R register ***************/
+#define RTC_BKP10R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP11R register ***************/
+#define RTC_BKP11R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP12R register ***************/
+#define RTC_BKP12R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP13R register ***************/
+#define RTC_BKP13R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP14R register ***************/
+#define RTC_BKP14R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP15R register ***************/
+#define RTC_BKP15R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP16R register ***************/
+#define RTC_BKP16R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP17R register ***************/
+#define RTC_BKP17R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP18R register ***************/
+#define RTC_BKP18R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP19R register ***************/
+#define RTC_BKP19R 0xFFFFFFFFU
+
+
+
+/******************************************************************************/
+/* */
+/* SD host Interface */
+/* */
+/******************************************************************************/
+/****************** Bit definition for SDIO_POWER register ******************/
+#define SDIO_POWER_PWRCTRL 0x03U /*!<PWRCTRL[1:0] bits (Power supply control bits) */
+#define SDIO_POWER_PWRCTRL_0 0x01U /*!<Bit 0 */
+#define SDIO_POWER_PWRCTRL_1 0x02U /*!<Bit 1 */
+
+/****************** Bit definition for SDIO_CLKCR register ******************/
+#define SDIO_CLKCR_CLKDIV 0x00FFU /*!<Clock divide factor */
+#define SDIO_CLKCR_CLKEN 0x0100U /*!<Clock enable bit */
+#define SDIO_CLKCR_PWRSAV 0x0200U /*!<Power saving configuration bit */
+#define SDIO_CLKCR_BYPASS 0x0400U /*!<Clock divider bypass enable bit */
+
+#define SDIO_CLKCR_WIDBUS 0x1800U /*!<WIDBUS[1:0] bits (Wide bus mode enable bit) */
+#define SDIO_CLKCR_WIDBUS_0 0x0800U /*!<Bit 0 */
+#define SDIO_CLKCR_WIDBUS_1 0x1000U /*!<Bit 1 */
+
+#define SDIO_CLKCR_NEGEDGE 0x2000U /*!<SDIO_CK dephasing selection bit */
+#define SDIO_CLKCR_HWFC_EN 0x4000U /*!<HW Flow Control enable */
+
+/******************* Bit definition for SDIO_ARG register *******************/
+#define SDIO_ARG_CMDARG 0xFFFFFFFFU /*!<Command argument */
+
+/******************* Bit definition for SDIO_CMD register *******************/
+#define SDIO_CMD_CMDINDEX 0x003FU /*!<Command Index */
+
+#define SDIO_CMD_WAITRESP 0x00C0U /*!<WAITRESP[1:0] bits (Wait for response bits) */
+#define SDIO_CMD_WAITRESP_0 0x0040U /*!< Bit 0 */
+#define SDIO_CMD_WAITRESP_1 0x0080U /*!< Bit 1 */
+
+#define SDIO_CMD_WAITINT 0x0100U /*!<CPSM Waits for Interrupt Request */
+#define SDIO_CMD_WAITPEND 0x0200U /*!<CPSM Waits for ends of data transfer (CmdPend internal signal) */
+#define SDIO_CMD_CPSMEN 0x0400U /*!<Command path state machine (CPSM) Enable bit */
+#define SDIO_CMD_SDIOSUSPEND 0x0800U /*!<SD I/O suspend command */
+#define SDIO_CMD_ENCMDCOMPL 0x1000U /*!<Enable CMD completion */
+#define SDIO_CMD_NIEN 0x2000U /*!<Not Interrupt Enable */
+#define SDIO_CMD_CEATACMD 0x4000U /*!<CE-ATA command */
+
+/***************** Bit definition for SDIO_RESPCMD register *****************/
+#define SDIO_RESPCMD_RESPCMD 0x3FU /*!<Response command index */
+
+/****************** Bit definition for SDIO_RESP0 register ******************/
+#define SDIO_RESP0_CARDSTATUS0 0xFFFFFFFFU /*!<Card Status */
+
+/****************** Bit definition for SDIO_RESP1 register ******************/
+#define SDIO_RESP1_CARDSTATUS1 0xFFFFFFFFU /*!<Card Status */
+
+/****************** Bit definition for SDIO_RESP2 register ******************/
+#define SDIO_RESP2_CARDSTATUS2 0xFFFFFFFFU /*!<Card Status */
+
+/****************** Bit definition for SDIO_RESP3 register ******************/
+#define SDIO_RESP3_CARDSTATUS3 0xFFFFFFFFU /*!<Card Status */
+
+/****************** Bit definition for SDIO_RESP4 register ******************/
+#define SDIO_RESP4_CARDSTATUS4 0xFFFFFFFFU /*!<Card Status */
+
+/****************** Bit definition for SDIO_DTIMER register *****************/
+#define SDIO_DTIMER_DATATIME 0xFFFFFFFFU /*!<Data timeout period. */
+
+/****************** Bit definition for SDIO_DLEN register *******************/
+#define SDIO_DLEN_DATALENGTH 0x01FFFFFFU /*!<Data length value */
+
+/****************** Bit definition for SDIO_DCTRL register ******************/
+#define SDIO_DCTRL_DTEN 0x0001U /*!<Data transfer enabled bit */
+#define SDIO_DCTRL_DTDIR 0x0002U /*!<Data transfer direction selection */
+#define SDIO_DCTRL_DTMODE 0x0004U /*!<Data transfer mode selection */
+#define SDIO_DCTRL_DMAEN 0x0008U /*!<DMA enabled bit */
+
+#define SDIO_DCTRL_DBLOCKSIZE 0x00F0U /*!<DBLOCKSIZE[3:0] bits (Data block size) */
+#define SDIO_DCTRL_DBLOCKSIZE_0 0x0010U /*!<Bit 0 */
+#define SDIO_DCTRL_DBLOCKSIZE_1 0x0020U /*!<Bit 1 */
+#define SDIO_DCTRL_DBLOCKSIZE_2 0x0040U /*!<Bit 2 */
+#define SDIO_DCTRL_DBLOCKSIZE_3 0x0080U /*!<Bit 3 */
+
+#define SDIO_DCTRL_RWSTART 0x0100U /*!<Read wait start */
+#define SDIO_DCTRL_RWSTOP 0x0200U /*!<Read wait stop */
+#define SDIO_DCTRL_RWMOD 0x0400U /*!<Read wait mode */
+#define SDIO_DCTRL_SDIOEN 0x0800U /*!<SD I/O enable functions */
+
+/****************** Bit definition for SDIO_DCOUNT register *****************/
+#define SDIO_DCOUNT_DATACOUNT 0x01FFFFFFU /*!<Data count value */
+
+/****************** Bit definition for SDIO_STA register ********************/
+#define SDIO_STA_CCRCFAIL 0x00000001U /*!<Command response received (CRC check failed) */
+#define SDIO_STA_DCRCFAIL 0x00000002U /*!<Data block sent/received (CRC check failed) */
+#define SDIO_STA_CTIMEOUT 0x00000004U /*!<Command response timeout */
+#define SDIO_STA_DTIMEOUT 0x00000008U /*!<Data timeout */
+#define SDIO_STA_TXUNDERR 0x00000010U /*!<Transmit FIFO underrun error */
+#define SDIO_STA_RXOVERR 0x00000020U /*!<Received FIFO overrun error */
+#define SDIO_STA_CMDREND 0x00000040U /*!<Command response received (CRC check passed) */
+#define SDIO_STA_CMDSENT 0x00000080U /*!<Command sent (no response required) */
+#define SDIO_STA_DATAEND 0x00000100U /*!<Data end (data counter, SDIDCOUNT, is zero) */
+#define SDIO_STA_STBITERR 0x00000200U /*!<Start bit not detected on all data signals in wide bus mode */
+#define SDIO_STA_DBCKEND 0x00000400U /*!<Data block sent/received (CRC check passed) */
+#define SDIO_STA_CMDACT 0x00000800U /*!<Command transfer in progress */
+#define SDIO_STA_TXACT 0x00001000U /*!<Data transmit in progress */
+#define SDIO_STA_RXACT 0x00002000U /*!<Data receive in progress */
+#define SDIO_STA_TXFIFOHE 0x00004000U /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
+#define SDIO_STA_RXFIFOHF 0x00008000U /*!<Receive FIFO Half Full: there are at least 8 words in the FIFO */
+#define SDIO_STA_TXFIFOF 0x00010000U /*!<Transmit FIFO full */
+#define SDIO_STA_RXFIFOF 0x00020000U /*!<Receive FIFO full */
+#define SDIO_STA_TXFIFOE 0x00040000U /*!<Transmit FIFO empty */
+#define SDIO_STA_RXFIFOE 0x00080000U /*!<Receive FIFO empty */
+#define SDIO_STA_TXDAVL 0x00100000U /*!<Data available in transmit FIFO */
+#define SDIO_STA_RXDAVL 0x00200000U /*!<Data available in receive FIFO */
+#define SDIO_STA_SDIOIT 0x00400000U /*!<SDIO interrupt received */
+#define SDIO_STA_CEATAEND 0x00800000U /*!<CE-ATA command completion signal received for CMD61 */
+
+/******************* Bit definition for SDIO_ICR register *******************/
+#define SDIO_ICR_CCRCFAILC 0x00000001U /*!<CCRCFAIL flag clear bit */
+#define SDIO_ICR_DCRCFAILC 0x00000002U /*!<DCRCFAIL flag clear bit */
+#define SDIO_ICR_CTIMEOUTC 0x00000004U /*!<CTIMEOUT flag clear bit */
+#define SDIO_ICR_DTIMEOUTC 0x00000008U /*!<DTIMEOUT flag clear bit */
+#define SDIO_ICR_TXUNDERRC 0x00000010U /*!<TXUNDERR flag clear bit */
+#define SDIO_ICR_RXOVERRC 0x00000020U /*!<RXOVERR flag clear bit */
+#define SDIO_ICR_CMDRENDC 0x00000040U /*!<CMDREND flag clear bit */
+#define SDIO_ICR_CMDSENTC 0x00000080U /*!<CMDSENT flag clear bit */
+#define SDIO_ICR_DATAENDC 0x00000100U /*!<DATAEND flag clear bit */
+#define SDIO_ICR_STBITERRC 0x00000200U /*!<STBITERR flag clear bit */
+#define SDIO_ICR_DBCKENDC 0x00000400U /*!<DBCKEND flag clear bit */
+#define SDIO_ICR_SDIOITC 0x00400000U /*!<SDIOIT flag clear bit */
+#define SDIO_ICR_CEATAENDC 0x00800000U /*!<CEATAEND flag clear bit */
+
+/****************** Bit definition for SDIO_MASK register *******************/
+#define SDIO_MASK_CCRCFAILIE 0x00000001U /*!<Command CRC Fail Interrupt Enable */
+#define SDIO_MASK_DCRCFAILIE 0x00000002U /*!<Data CRC Fail Interrupt Enable */
+#define SDIO_MASK_CTIMEOUTIE 0x00000004U /*!<Command TimeOut Interrupt Enable */
+#define SDIO_MASK_DTIMEOUTIE 0x00000008U /*!<Data TimeOut Interrupt Enable */
+#define SDIO_MASK_TXUNDERRIE 0x00000010U /*!<Tx FIFO UnderRun Error Interrupt Enable */
+#define SDIO_MASK_RXOVERRIE 0x00000020U /*!<Rx FIFO OverRun Error Interrupt Enable */
+#define SDIO_MASK_CMDRENDIE 0x00000040U /*!<Command Response Received Interrupt Enable */
+#define SDIO_MASK_CMDSENTIE 0x00000080U /*!<Command Sent Interrupt Enable */
+#define SDIO_MASK_DATAENDIE 0x00000100U /*!<Data End Interrupt Enable */
+#define SDIO_MASK_STBITERRIE 0x00000200U /*!<Start Bit Error Interrupt Enable */
+#define SDIO_MASK_DBCKENDIE 0x00000400U /*!<Data Block End Interrupt Enable */
+#define SDIO_MASK_CMDACTIE 0x00000800U /*!<CCommand Acting Interrupt Enable */
+#define SDIO_MASK_TXACTIE 0x00001000U /*!<Data Transmit Acting Interrupt Enable */
+#define SDIO_MASK_RXACTIE 0x00002000U /*!<Data receive acting interrupt enabled */
+#define SDIO_MASK_TXFIFOHEIE 0x00004000U /*!<Tx FIFO Half Empty interrupt Enable */
+#define SDIO_MASK_RXFIFOHFIE 0x00008000U /*!<Rx FIFO Half Full interrupt Enable */
+#define SDIO_MASK_TXFIFOFIE 0x00010000U /*!<Tx FIFO Full interrupt Enable */
+#define SDIO_MASK_RXFIFOFIE 0x00020000U /*!<Rx FIFO Full interrupt Enable */
+#define SDIO_MASK_TXFIFOEIE 0x00040000U /*!<Tx FIFO Empty interrupt Enable */
+#define SDIO_MASK_RXFIFOEIE 0x00080000U /*!<Rx FIFO Empty interrupt Enable */
+#define SDIO_MASK_TXDAVLIE 0x00100000U /*!<Data available in Tx FIFO interrupt Enable */
+#define SDIO_MASK_RXDAVLIE 0x00200000U /*!<Data available in Rx FIFO interrupt Enable */
+#define SDIO_MASK_SDIOITIE 0x00400000U /*!<SDIO Mode Interrupt Received interrupt Enable */
+#define SDIO_MASK_CEATAENDIE 0x00800000U /*!<CE-ATA command completion signal received Interrupt Enable */
+
+/***************** Bit definition for SDIO_FIFOCNT register *****************/
+#define SDIO_FIFOCNT_FIFOCOUNT 0x00FFFFFFU /*!<Remaining number of words to be written to or read from the FIFO */
+
+/****************** Bit definition for SDIO_FIFO register *******************/
+#define SDIO_FIFO_FIFODATA 0xFFFFFFFFU /*!<Receive and transmit FIFO data */
+
+/******************************************************************************/
+/* */
+/* Serial Peripheral Interface */
+/* */
+/******************************************************************************/
+/******************* Bit definition for SPI_CR1 register ********************/
+#define SPI_CR1_CPHA 0x00000001U /*!<Clock Phase */
+#define SPI_CR1_CPOL 0x00000002U /*!<Clock Polarity */
+#define SPI_CR1_MSTR 0x00000004U /*!<Master Selection */
+
+#define SPI_CR1_BR 0x00000038U /*!<BR[2:0] bits (Baud Rate Control) */
+#define SPI_CR1_BR_0 0x00000008U /*!<Bit 0 */
+#define SPI_CR1_BR_1 0x00000010U /*!<Bit 1 */
+#define SPI_CR1_BR_2 0x00000020U /*!<Bit 2 */
+
+#define SPI_CR1_SPE 0x00000040U /*!<SPI Enable */
+#define SPI_CR1_LSBFIRST 0x00000080U /*!<Frame Format */
+#define SPI_CR1_SSI 0x00000100U /*!<Internal slave select */
+#define SPI_CR1_SSM 0x00000200U /*!<Software slave management */
+#define SPI_CR1_RXONLY 0x00000400U /*!<Receive only */
+#define SPI_CR1_DFF 0x00000800U /*!<Data Frame Format */
+#define SPI_CR1_CRCNEXT 0x00001000U /*!<Transmit CRC next */
+#define SPI_CR1_CRCEN 0x00002000U /*!<Hardware CRC calculation enable */
+#define SPI_CR1_BIDIOE 0x00004000U /*!<Output enable in bidirectional mode */
+#define SPI_CR1_BIDIMODE 0x00008000U /*!<Bidirectional data mode enable */
+
+/******************* Bit definition for SPI_CR2 register ********************/
+#define SPI_CR2_RXDMAEN 0x00000001U /*!<Rx Buffer DMA Enable */
+#define SPI_CR2_TXDMAEN 0x00000002U /*!<Tx Buffer DMA Enable */
+#define SPI_CR2_SSOE 0x00000004U /*!<SS Output Enable */
+#define SPI_CR2_FRF 0x00000010U /*!<Frame Format */
+#define SPI_CR2_ERRIE 0x00000020U /*!<Error Interrupt Enable */
+#define SPI_CR2_RXNEIE 0x00000040U /*!<RX buffer Not Empty Interrupt Enable */
+#define SPI_CR2_TXEIE 0x00000080U /*!<Tx buffer Empty Interrupt Enable */
+
+/******************** Bit definition for SPI_SR register ********************/
+#define SPI_SR_RXNE 0x00000001U /*!<Receive buffer Not Empty */
+#define SPI_SR_TXE 0x00000002U /*!<Transmit buffer Empty */
+#define SPI_SR_CHSIDE 0x00000004U /*!<Channel side */
+#define SPI_SR_UDR 0x00000008U /*!<Underrun flag */
+#define SPI_SR_CRCERR 0x00000010U /*!<CRC Error flag */
+#define SPI_SR_MODF 0x00000020U /*!<Mode fault */
+#define SPI_SR_OVR 0x00000040U /*!<Overrun flag */
+#define SPI_SR_BSY 0x00000080U /*!<Busy flag */
+#define SPI_SR_FRE 0x00000100U /*!<Frame format error flag */
+
+/******************** Bit definition for SPI_DR register ********************/
+#define SPI_DR_DR 0x0000FFFFU /*!<Data Register */
+
+/******************* Bit definition for SPI_CRCPR register ******************/
+#define SPI_CRCPR_CRCPOLY 0x0000FFFFU /*!<CRC polynomial register */
+
+/****************** Bit definition for SPI_RXCRCR register ******************/
+#define SPI_RXCRCR_RXCRC 0x0000FFFFU /*!<Rx CRC Register */
+
+/****************** Bit definition for SPI_TXCRCR register ******************/
+#define SPI_TXCRCR_TXCRC 0x0000FFFFU /*!<Tx CRC Register */
+
+/****************** Bit definition for SPI_I2SCFGR register *****************/
+#define SPI_I2SCFGR_CHLEN 0x00000001U /*!<Channel length (number of bits per audio channel) */
+
+#define SPI_I2SCFGR_DATLEN 0x00000006U /*!<DATLEN[1:0] bits (Data length to be transferred) */
+#define SPI_I2SCFGR_DATLEN_0 0x00000002U /*!<Bit 0 */
+#define SPI_I2SCFGR_DATLEN_1 0x00000004U /*!<Bit 1 */
+
+#define SPI_I2SCFGR_CKPOL 0x00000008U /*!<steady state clock polarity */
+
+#define SPI_I2SCFGR_I2SSTD 0x00000030U /*!<I2SSTD[1:0] bits (I2S standard selection) */
+#define SPI_I2SCFGR_I2SSTD_0 0x00000010U /*!<Bit 0 */
+#define SPI_I2SCFGR_I2SSTD_1 0x00000020U /*!<Bit 1 */
+
+#define SPI_I2SCFGR_PCMSYNC 0x00000080U /*!<PCM frame synchronization */
+
+#define SPI_I2SCFGR_I2SCFG 0x00000300U /*!<I2SCFG[1:0] bits (I2S configuration mode) */
+#define SPI_I2SCFGR_I2SCFG_0 0x00000100U /*!<Bit 0 */
+#define SPI_I2SCFGR_I2SCFG_1 0x00000200U /*!<Bit 1 */
+
+#define SPI_I2SCFGR_I2SE 0x00000400U /*!<I2S Enable */
+#define SPI_I2SCFGR_I2SMOD 0x00000800U /*!<I2S mode selection */
+
+/****************** Bit definition for SPI_I2SPR register *******************/
+#define SPI_I2SPR_I2SDIV 0x000000FFU /*!<I2S Linear prescaler */
+#define SPI_I2SPR_ODD 0x00000100U /*!<Odd factor for the prescaler */
+#define SPI_I2SPR_MCKOE 0x00000200U /*!<Master Clock Output Enable */
+
+/******************************************************************************/
+/* */
+/* SYSCFG */
+/* */
+/******************************************************************************/
+/****************** Bit definition for SYSCFG_MEMRMP register ***************/
+#define SYSCFG_MEMRMP_MEM_MODE 0x00000007U /*!< SYSCFG_Memory Remap Config */
+#define SYSCFG_MEMRMP_MEM_MODE_0 0x00000001U
+#define SYSCFG_MEMRMP_MEM_MODE_1 0x00000002U
+#define SYSCFG_MEMRMP_MEM_MODE_2 0x00000004U
+
+/****************** Bit definition for SYSCFG_PMC register ******************/
+#define SYSCFG_PMC_MII_RMII_SEL 0x00800000U /*!<Ethernet PHY interface selection */
+/* Old MII_RMII_SEL bit definition, maintained for legacy purpose */
+#define SYSCFG_PMC_MII_RMII SYSCFG_PMC_MII_RMII_SEL
+
+/***************** Bit definition for SYSCFG_EXTICR1 register ***************/
+#define SYSCFG_EXTICR1_EXTI0 0x000FU /*!<EXTI 0 configuration */
+#define SYSCFG_EXTICR1_EXTI1 0x00F0U /*!<EXTI 1 configuration */
+#define SYSCFG_EXTICR1_EXTI2 0x0F00U /*!<EXTI 2 configuration */
+#define SYSCFG_EXTICR1_EXTI3 0xF000U /*!<EXTI 3 configuration */
+/**
+ * @brief EXTI0 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI0_PA 0x0000U /*!<PA[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PB 0x0001U /*!<PB[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PC 0x0002U /*!<PC[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PD 0x0003U /*!<PD[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PE 0x0004U /*!<PE[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PF 0x0005U /*!<PF[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PG 0x0006U /*!<PG[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PH 0x0007U /*!<PH[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PI 0x0008U /*!<PI[0] pin */
+
+/**
+ * @brief EXTI1 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI1_PA 0x0000U /*!<PA[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PB 0x0010U /*!<PB[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PC 0x0020U /*!<PC[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PD 0x0030U /*!<PD[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PE 0x0040U /*!<PE[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PF 0x0050U /*!<PF[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PG 0x0060U /*!<PG[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PH 0x0070U /*!<PH[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PI 0x0080U /*!<PI[1] pin */
+
+/**
+ * @brief EXTI2 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI2_PA 0x0000U /*!<PA[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PB 0x0100U /*!<PB[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PC 0x0200U /*!<PC[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PD 0x0300U /*!<PD[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PE 0x0400U /*!<PE[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PF 0x0500U /*!<PF[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PG 0x0600U /*!<PG[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PH 0x0700U /*!<PH[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PI 0x0800U /*!<PI[2] pin */
+
+/**
+ * @brief EXTI3 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI3_PA 0x0000U /*!<PA[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PB 0x1000U /*!<PB[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PC 0x2000U /*!<PC[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PD 0x3000U /*!<PD[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PE 0x4000U /*!<PE[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PF 0x5000U /*!<PF[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PG 0x6000U /*!<PG[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PH 0x7000U /*!<PH[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PI 0x8000U /*!<PI[3] pin */
+
+/***************** Bit definition for SYSCFG_EXTICR2 register ***************/
+#define SYSCFG_EXTICR2_EXTI4 0x000FU /*!<EXTI 4 configuration */
+#define SYSCFG_EXTICR2_EXTI5 0x00F0U /*!<EXTI 5 configuration */
+#define SYSCFG_EXTICR2_EXTI6 0x0F00U /*!<EXTI 6 configuration */
+#define SYSCFG_EXTICR2_EXTI7 0xF000U /*!<EXTI 7 configuration */
+/**
+ * @brief EXTI4 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI4_PA 0x0000U /*!<PA[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PB 0x0001U /*!<PB[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PC 0x0002U /*!<PC[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PD 0x0003U /*!<PD[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PE 0x0004U /*!<PE[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PF 0x0005U /*!<PF[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PG 0x0006U /*!<PG[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PH 0x0007U /*!<PH[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PI 0x0008U /*!<PI[4] pin */
+
+/**
+ * @brief EXTI5 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI5_PA 0x0000U /*!<PA[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PB 0x0010U /*!<PB[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PC 0x0020U /*!<PC[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PD 0x0030U /*!<PD[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PE 0x0040U /*!<PE[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PF 0x0050U /*!<PF[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PG 0x0060U /*!<PG[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PH 0x0070U /*!<PH[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PI 0x0080U /*!<PI[5] pin */
+
+/**
+ * @brief EXTI6 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI6_PA 0x0000U /*!<PA[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PB 0x0100U /*!<PB[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PC 0x0200U /*!<PC[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PD 0x0300U /*!<PD[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PE 0x0400U /*!<PE[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PF 0x0500U /*!<PF[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PG 0x0600U /*!<PG[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PH 0x0700U /*!<PH[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PI 0x0800U /*!<PI[6] pin */
+
+/**
+ * @brief EXTI7 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI7_PA 0x0000U /*!<PA[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PB 0x1000U /*!<PB[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PC 0x2000U /*!<PC[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PD 0x3000U /*!<PD[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PE 0x4000U /*!<PE[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PF 0x5000U /*!<PF[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PG 0x6000U /*!<PG[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PH 0x7000U /*!<PH[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PI 0x8000U /*!<PI[7] pin */
+
+
+/***************** Bit definition for SYSCFG_EXTICR3 register ***************/
+#define SYSCFG_EXTICR3_EXTI8 0x000FU /*!<EXTI 8 configuration */
+#define SYSCFG_EXTICR3_EXTI9 0x00F0U /*!<EXTI 9 configuration */
+#define SYSCFG_EXTICR3_EXTI10 0x0F00U /*!<EXTI 10 configuration */
+#define SYSCFG_EXTICR3_EXTI11 0xF000U /*!<EXTI 11 configuration */
+
+/**
+ * @brief EXTI8 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI8_PA 0x0000U /*!<PA[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PB 0x0001U /*!<PB[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PC 0x0002U /*!<PC[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PD 0x0003U /*!<PD[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PE 0x0004U /*!<PE[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PF 0x0005U /*!<PF[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PG 0x0006U /*!<PG[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PH 0x0007U /*!<PH[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PI 0x0008U /*!<PI[8] pin */
+
+/**
+ * @brief EXTI9 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI9_PA 0x0000U /*!<PA[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PB 0x0010U /*!<PB[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PC 0x0020U /*!<PC[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PD 0x0030U /*!<PD[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PE 0x0040U /*!<PE[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PF 0x0050U /*!<PF[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PG 0x0060U /*!<PG[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PH 0x0070U /*!<PH[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PI 0x0080U /*!<PI[9] pin */
+
+/**
+ * @brief EXTI10 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI10_PA 0x0000U /*!<PA[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PB 0x0100U /*!<PB[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PC 0x0200U /*!<PC[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PD 0x0300U /*!<PD[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PE 0x0400U /*!<PE[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PF 0x0500U /*!<PF[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PG 0x0600U /*!<PG[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PH 0x0700U /*!<PH[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PI 0x0800U /*!<PI[10] pin */
+
+/**
+ * @brief EXTI11 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI11_PA 0x0000U /*!<PA[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PB 0x1000U /*!<PB[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PC 0x2000U /*!<PC[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PD 0x3000U /*!<PD[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PE 0x4000U /*!<PE[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PF 0x5000U /*!<PF[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PG 0x6000U /*!<PG[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PH 0x7000U /*!<PH[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PI 0x8000U /*!<PI[11] pin */
+
+/***************** Bit definition for SYSCFG_EXTICR4 register ***************/
+#define SYSCFG_EXTICR4_EXTI12 0x000FU /*!<EXTI 12 configuration */
+#define SYSCFG_EXTICR4_EXTI13 0x00F0U /*!<EXTI 13 configuration */
+#define SYSCFG_EXTICR4_EXTI14 0x0F00U /*!<EXTI 14 configuration */
+#define SYSCFG_EXTICR4_EXTI15 0xF000U /*!<EXTI 15 configuration */
+/**
+ * @brief EXTI12 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI12_PA 0x0000U /*!<PA[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PB 0x0001U /*!<PB[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PC 0x0002U /*!<PC[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PD 0x0003U /*!<PD[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PE 0x0004U /*!<PE[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PF 0x0005U /*!<PF[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PG 0x0006U /*!<PG[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PH 0x0007U /*!<PH[12] pin */
+
+/**
+ * @brief EXTI13 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI13_PA 0x0000U /*!<PA[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PB 0x0010U /*!<PB[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PC 0x0020U /*!<PC[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PD 0x0030U /*!<PD[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PE 0x0040U /*!<PE[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PF 0x0050U /*!<PF[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PG 0x0060U /*!<PG[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PH 0x0070U /*!<PH[13] pin */
+
+/**
+ * @brief EXTI14 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI14_PA 0x0000U /*!<PA[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PB 0x0100U /*!<PB[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PC 0x0200U /*!<PC[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PD 0x0300U /*!<PD[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PE 0x0400U /*!<PE[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PF 0x0500U /*!<PF[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PG 0x0600U /*!<PG[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PH 0x0700U /*!<PH[14] pin */
+
+/**
+ * @brief EXTI15 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI15_PA 0x0000U /*!<PA[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PB 0x1000U /*!<PB[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PC 0x2000U /*!<PC[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PD 0x3000U /*!<PD[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PE 0x4000U /*!<PE[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PF 0x5000U /*!<PF[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PG 0x6000U /*!<PG[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PH 0x7000U /*!<PH[15] pin */
+
+/****************** Bit definition for SYSCFG_CMPCR register ****************/
+#define SYSCFG_CMPCR_CMP_PD 0x00000001U /*!<Compensation cell ready flag */
+#define SYSCFG_CMPCR_READY 0x00000100U /*!<Compensation cell power-down */
+
+/******************************************************************************/
+/* */
+/* TIM */
+/* */
+/******************************************************************************/
+/******************* Bit definition for TIM_CR1 register ********************/
+#define TIM_CR1_CEN 0x0001U /*!<Counter enable */
+#define TIM_CR1_UDIS 0x0002U /*!<Update disable */
+#define TIM_CR1_URS 0x0004U /*!<Update request source */
+#define TIM_CR1_OPM 0x0008U /*!<One pulse mode */
+#define TIM_CR1_DIR 0x0010U /*!<Direction */
+
+#define TIM_CR1_CMS 0x0060U /*!<CMS[1:0] bits (Center-aligned mode selection) */
+#define TIM_CR1_CMS_0 0x0020U /*!<Bit 0 */
+#define TIM_CR1_CMS_1 0x0040U /*!<Bit 1 */
+
+#define TIM_CR1_ARPE 0x0080U /*!<Auto-reload preload enable */
+
+#define TIM_CR1_CKD 0x0300U /*!<CKD[1:0] bits (clock division) */
+#define TIM_CR1_CKD_0 0x0100U /*!<Bit 0 */
+#define TIM_CR1_CKD_1 0x0200U /*!<Bit 1 */
+
+/******************* Bit definition for TIM_CR2 register ********************/
+#define TIM_CR2_CCPC 0x0001U /*!<Capture/Compare Preloaded Control */
+#define TIM_CR2_CCUS 0x0004U /*!<Capture/Compare Control Update Selection */
+#define TIM_CR2_CCDS 0x0008U /*!<Capture/Compare DMA Selection */
+
+#define TIM_CR2_MMS 0x0070U /*!<MMS[2:0] bits (Master Mode Selection) */
+#define TIM_CR2_MMS_0 0x0010U /*!<Bit 0 */
+#define TIM_CR2_MMS_1 0x0020U /*!<Bit 1 */
+#define TIM_CR2_MMS_2 0x0040U /*!<Bit 2 */
+
+#define TIM_CR2_TI1S 0x0080U /*!<TI1 Selection */
+#define TIM_CR2_OIS1 0x0100U /*!<Output Idle state 1 (OC1 output) */
+#define TIM_CR2_OIS1N 0x0200U /*!<Output Idle state 1 (OC1N output) */
+#define TIM_CR2_OIS2 0x0400U /*!<Output Idle state 2 (OC2 output) */
+#define TIM_CR2_OIS2N 0x0800U /*!<Output Idle state 2 (OC2N output) */
+#define TIM_CR2_OIS3 0x1000U /*!<Output Idle state 3 (OC3 output) */
+#define TIM_CR2_OIS3N 0x2000U /*!<Output Idle state 3 (OC3N output) */
+#define TIM_CR2_OIS4 0x4000U /*!<Output Idle state 4 (OC4 output) */
+
+/******************* Bit definition for TIM_SMCR register *******************/
+#define TIM_SMCR_SMS 0x0007U /*!<SMS[2:0] bits (Slave mode selection) */
+#define TIM_SMCR_SMS_0 0x0001U /*!<Bit 0 */
+#define TIM_SMCR_SMS_1 0x0002U /*!<Bit 1 */
+#define TIM_SMCR_SMS_2 0x0004U /*!<Bit 2 */
+
+#define TIM_SMCR_TS 0x0070U /*!<TS[2:0] bits (Trigger selection) */
+#define TIM_SMCR_TS_0 0x0010U /*!<Bit 0 */
+#define TIM_SMCR_TS_1 0x0020U /*!<Bit 1 */
+#define TIM_SMCR_TS_2 0x0040U /*!<Bit 2 */
+
+#define TIM_SMCR_MSM 0x0080U /*!<Master/slave mode */
+
+#define TIM_SMCR_ETF 0x0F00U /*!<ETF[3:0] bits (External trigger filter) */
+#define TIM_SMCR_ETF_0 0x0100U /*!<Bit 0 */
+#define TIM_SMCR_ETF_1 0x0200U /*!<Bit 1 */
+#define TIM_SMCR_ETF_2 0x0400U /*!<Bit 2 */
+#define TIM_SMCR_ETF_3 0x0800U /*!<Bit 3 */
+
+#define TIM_SMCR_ETPS 0x3000U /*!<ETPS[1:0] bits (External trigger prescaler) */
+#define TIM_SMCR_ETPS_0 0x1000U /*!<Bit 0 */
+#define TIM_SMCR_ETPS_1 0x2000U /*!<Bit 1 */
+
+#define TIM_SMCR_ECE 0x4000U /*!<External clock enable */
+#define TIM_SMCR_ETP 0x8000U /*!<External trigger polarity */
+
+/******************* Bit definition for TIM_DIER register *******************/
+#define TIM_DIER_UIE 0x0001U /*!<Update interrupt enable */
+#define TIM_DIER_CC1IE 0x0002U /*!<Capture/Compare 1 interrupt enable */
+#define TIM_DIER_CC2IE 0x0004U /*!<Capture/Compare 2 interrupt enable */
+#define TIM_DIER_CC3IE 0x0008U /*!<Capture/Compare 3 interrupt enable */
+#define TIM_DIER_CC4IE 0x0010U /*!<Capture/Compare 4 interrupt enable */
+#define TIM_DIER_COMIE 0x0020U /*!<COM interrupt enable */
+#define TIM_DIER_TIE 0x0040U /*!<Trigger interrupt enable */
+#define TIM_DIER_BIE 0x0080U /*!<Break interrupt enable */
+#define TIM_DIER_UDE 0x0100U /*!<Update DMA request enable */
+#define TIM_DIER_CC1DE 0x0200U /*!<Capture/Compare 1 DMA request enable */
+#define TIM_DIER_CC2DE 0x0400U /*!<Capture/Compare 2 DMA request enable */
+#define TIM_DIER_CC3DE 0x0800U /*!<Capture/Compare 3 DMA request enable */
+#define TIM_DIER_CC4DE 0x1000U /*!<Capture/Compare 4 DMA request enable */
+#define TIM_DIER_COMDE 0x2000U /*!<COM DMA request enable */
+#define TIM_DIER_TDE 0x4000U /*!<Trigger DMA request enable */
+
+/******************** Bit definition for TIM_SR register ********************/
+#define TIM_SR_UIF 0x0001U /*!<Update interrupt Flag */
+#define TIM_SR_CC1IF 0x0002U /*!<Capture/Compare 1 interrupt Flag */
+#define TIM_SR_CC2IF 0x0004U /*!<Capture/Compare 2 interrupt Flag */
+#define TIM_SR_CC3IF 0x0008U /*!<Capture/Compare 3 interrupt Flag */
+#define TIM_SR_CC4IF 0x0010U /*!<Capture/Compare 4 interrupt Flag */
+#define TIM_SR_COMIF 0x0020U /*!<COM interrupt Flag */
+#define TIM_SR_TIF 0x0040U /*!<Trigger interrupt Flag */
+#define TIM_SR_BIF 0x0080U /*!<Break interrupt Flag */
+#define TIM_SR_CC1OF 0x0200U /*!<Capture/Compare 1 Overcapture Flag */
+#define TIM_SR_CC2OF 0x0400U /*!<Capture/Compare 2 Overcapture Flag */
+#define TIM_SR_CC3OF 0x0800U /*!<Capture/Compare 3 Overcapture Flag */
+#define TIM_SR_CC4OF 0x1000U /*!<Capture/Compare 4 Overcapture Flag */
+
+/******************* Bit definition for TIM_EGR register ********************/
+#define TIM_EGR_UG 0x01U /*!<Update Generation */
+#define TIM_EGR_CC1G 0x02U /*!<Capture/Compare 1 Generation */
+#define TIM_EGR_CC2G 0x04U /*!<Capture/Compare 2 Generation */
+#define TIM_EGR_CC3G 0x08U /*!<Capture/Compare 3 Generation */
+#define TIM_EGR_CC4G 0x10U /*!<Capture/Compare 4 Generation */
+#define TIM_EGR_COMG 0x20U /*!<Capture/Compare Control Update Generation */
+#define TIM_EGR_TG 0x40U /*!<Trigger Generation */
+#define TIM_EGR_BG 0x80U /*!<Break Generation */
+
+/****************** Bit definition for TIM_CCMR1 register *******************/
+#define TIM_CCMR1_CC1S 0x0003U /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
+#define TIM_CCMR1_CC1S_0 0x0001U /*!<Bit 0 */
+#define TIM_CCMR1_CC1S_1 0x0002U /*!<Bit 1 */
+
+#define TIM_CCMR1_OC1FE 0x0004U /*!<Output Compare 1 Fast enable */
+#define TIM_CCMR1_OC1PE 0x0008U /*!<Output Compare 1 Preload enable */
+
+#define TIM_CCMR1_OC1M 0x0070U /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
+#define TIM_CCMR1_OC1M_0 0x0010U /*!<Bit 0 */
+#define TIM_CCMR1_OC1M_1 0x0020U /*!<Bit 1 */
+#define TIM_CCMR1_OC1M_2 0x0040U /*!<Bit 2 */
+
+#define TIM_CCMR1_OC1CE 0x0080U /*!<Output Compare 1Clear Enable */
+
+#define TIM_CCMR1_CC2S 0x0300U /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
+#define TIM_CCMR1_CC2S_0 0x0100U /*!<Bit 0 */
+#define TIM_CCMR1_CC2S_1 0x0200U /*!<Bit 1 */
+
+#define TIM_CCMR1_OC2FE 0x0400U /*!<Output Compare 2 Fast enable */
+#define TIM_CCMR1_OC2PE 0x0800U /*!<Output Compare 2 Preload enable */
+
+#define TIM_CCMR1_OC2M 0x7000U /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
+#define TIM_CCMR1_OC2M_0 0x1000U /*!<Bit 0 */
+#define TIM_CCMR1_OC2M_1 0x2000U /*!<Bit 1 */
+#define TIM_CCMR1_OC2M_2 0x4000U /*!<Bit 2 */
+
+#define TIM_CCMR1_OC2CE 0x8000U /*!<Output Compare 2 Clear Enable */
+
+/*----------------------------------------------------------------------------*/
+
+#define TIM_CCMR1_IC1PSC 0x000CU /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
+#define TIM_CCMR1_IC1PSC_0 0x0004U /*!<Bit 0 */
+#define TIM_CCMR1_IC1PSC_1 0x0008U /*!<Bit 1 */
+
+#define TIM_CCMR1_IC1F 0x00F0U /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
+#define TIM_CCMR1_IC1F_0 0x0010U /*!<Bit 0 */
+#define TIM_CCMR1_IC1F_1 0x0020U /*!<Bit 1 */
+#define TIM_CCMR1_IC1F_2 0x0040U /*!<Bit 2 */
+#define TIM_CCMR1_IC1F_3 0x0080U /*!<Bit 3 */
+
+#define TIM_CCMR1_IC2PSC 0x0C00U /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
+#define TIM_CCMR1_IC2PSC_0 0x0400U /*!<Bit 0 */
+#define TIM_CCMR1_IC2PSC_1 0x0800U /*!<Bit 1 */
+
+#define TIM_CCMR1_IC2F 0xF000U /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
+#define TIM_CCMR1_IC2F_0 0x1000U /*!<Bit 0 */
+#define TIM_CCMR1_IC2F_1 0x2000U /*!<Bit 1 */
+#define TIM_CCMR1_IC2F_2 0x4000U /*!<Bit 2 */
+#define TIM_CCMR1_IC2F_3 0x8000U /*!<Bit 3 */
+
+/****************** Bit definition for TIM_CCMR2 register *******************/
+#define TIM_CCMR2_CC3S 0x0003U /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
+#define TIM_CCMR2_CC3S_0 0x0001U /*!<Bit 0 */
+#define TIM_CCMR2_CC3S_1 0x0002U /*!<Bit 1 */
+
+#define TIM_CCMR2_OC3FE 0x0004U /*!<Output Compare 3 Fast enable */
+#define TIM_CCMR2_OC3PE 0x0008U /*!<Output Compare 3 Preload enable */
+
+#define TIM_CCMR2_OC3M 0x0070U /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
+#define TIM_CCMR2_OC3M_0 0x0010U /*!<Bit 0 */
+#define TIM_CCMR2_OC3M_1 0x0020U /*!<Bit 1 */
+#define TIM_CCMR2_OC3M_2 0x0040U /*!<Bit 2 */
+
+#define TIM_CCMR2_OC3CE 0x0080U /*!<Output Compare 3 Clear Enable */
+
+#define TIM_CCMR2_CC4S 0x0300U /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
+#define TIM_CCMR2_CC4S_0 0x0100U /*!<Bit 0 */
+#define TIM_CCMR2_CC4S_1 0x0200U /*!<Bit 1 */
+
+#define TIM_CCMR2_OC4FE 0x0400U /*!<Output Compare 4 Fast enable */
+#define TIM_CCMR2_OC4PE 0x0800U /*!<Output Compare 4 Preload enable */
+
+#define TIM_CCMR2_OC4M 0x7000U /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
+#define TIM_CCMR2_OC4M_0 0x1000U /*!<Bit 0 */
+#define TIM_CCMR2_OC4M_1 0x2000U /*!<Bit 1 */
+#define TIM_CCMR2_OC4M_2 0x4000U /*!<Bit 2 */
+
+#define TIM_CCMR2_OC4CE 0x8000U /*!<Output Compare 4 Clear Enable */
+
+/*----------------------------------------------------------------------------*/
+
+#define TIM_CCMR2_IC3PSC 0x000CU /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
+#define TIM_CCMR2_IC3PSC_0 0x0004U /*!<Bit 0 */
+#define TIM_CCMR2_IC3PSC_1 0x0008U /*!<Bit 1 */
+
+#define TIM_CCMR2_IC3F 0x00F0U /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
+#define TIM_CCMR2_IC3F_0 0x0010U /*!<Bit 0 */
+#define TIM_CCMR2_IC3F_1 0x0020U /*!<Bit 1 */
+#define TIM_CCMR2_IC3F_2 0x0040U /*!<Bit 2 */
+#define TIM_CCMR2_IC3F_3 0x0080U /*!<Bit 3 */
+
+#define TIM_CCMR2_IC4PSC 0x0C00U /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
+#define TIM_CCMR2_IC4PSC_0 0x0400U /*!<Bit 0 */
+#define TIM_CCMR2_IC4PSC_1 0x0800U /*!<Bit 1 */
+
+#define TIM_CCMR2_IC4F 0xF000U /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
+#define TIM_CCMR2_IC4F_0 0x1000U /*!<Bit 0 */
+#define TIM_CCMR2_IC4F_1 0x2000U /*!<Bit 1 */
+#define TIM_CCMR2_IC4F_2 0x4000U /*!<Bit 2 */
+#define TIM_CCMR2_IC4F_3 0x8000U /*!<Bit 3 */
+
+/******************* Bit definition for TIM_CCER register *******************/
+#define TIM_CCER_CC1E 0x0001U /*!<Capture/Compare 1 output enable */
+#define TIM_CCER_CC1P 0x0002U /*!<Capture/Compare 1 output Polarity */
+#define TIM_CCER_CC1NE 0x0004U /*!<Capture/Compare 1 Complementary output enable */
+#define TIM_CCER_CC1NP 0x0008U /*!<Capture/Compare 1 Complementary output Polarity */
+#define TIM_CCER_CC2E 0x0010U /*!<Capture/Compare 2 output enable */
+#define TIM_CCER_CC2P 0x0020U /*!<Capture/Compare 2 output Polarity */
+#define TIM_CCER_CC2NE 0x0040U /*!<Capture/Compare 2 Complementary output enable */
+#define TIM_CCER_CC2NP 0x0080U /*!<Capture/Compare 2 Complementary output Polarity */
+#define TIM_CCER_CC3E 0x0100U /*!<Capture/Compare 3 output enable */
+#define TIM_CCER_CC3P 0x0200U /*!<Capture/Compare 3 output Polarity */
+#define TIM_CCER_CC3NE 0x0400U /*!<Capture/Compare 3 Complementary output enable */
+#define TIM_CCER_CC3NP 0x0800U /*!<Capture/Compare 3 Complementary output Polarity */
+#define TIM_CCER_CC4E 0x1000U /*!<Capture/Compare 4 output enable */
+#define TIM_CCER_CC4P 0x2000U /*!<Capture/Compare 4 output Polarity */
+#define TIM_CCER_CC4NP 0x8000U /*!<Capture/Compare 4 Complementary output Polarity */
+
+/******************* Bit definition for TIM_CNT register ********************/
+#define TIM_CNT_CNT 0xFFFFU /*!<Counter Value */
+
+/******************* Bit definition for TIM_PSC register ********************/
+#define TIM_PSC_PSC 0xFFFFU /*!<Prescaler Value */
+
+/******************* Bit definition for TIM_ARR register ********************/
+#define TIM_ARR_ARR 0xFFFFU /*!<actual auto-reload Value */
+
+/******************* Bit definition for TIM_RCR register ********************/
+#define TIM_RCR_REP 0xFFU /*!<Repetition Counter Value */
+
+/******************* Bit definition for TIM_CCR1 register *******************/
+#define TIM_CCR1_CCR1 0xFFFFU /*!<Capture/Compare 1 Value */
+
+/******************* Bit definition for TIM_CCR2 register *******************/
+#define TIM_CCR2_CCR2 0xFFFFU /*!<Capture/Compare 2 Value */
+
+/******************* Bit definition for TIM_CCR3 register *******************/
+#define TIM_CCR3_CCR3 0xFFFFU /*!<Capture/Compare 3 Value */
+
+/******************* Bit definition for TIM_CCR4 register *******************/
+#define TIM_CCR4_CCR4 0xFFFFU /*!<Capture/Compare 4 Value */
+
+/******************* Bit definition for TIM_BDTR register *******************/
+#define TIM_BDTR_DTG 0x00FFU /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
+#define TIM_BDTR_DTG_0 0x0001U /*!<Bit 0 */
+#define TIM_BDTR_DTG_1 0x0002U /*!<Bit 1 */
+#define TIM_BDTR_DTG_2 0x0004U /*!<Bit 2 */
+#define TIM_BDTR_DTG_3 0x0008U /*!<Bit 3 */
+#define TIM_BDTR_DTG_4 0x0010U /*!<Bit 4 */
+#define TIM_BDTR_DTG_5 0x0020U /*!<Bit 5 */
+#define TIM_BDTR_DTG_6 0x0040U /*!<Bit 6 */
+#define TIM_BDTR_DTG_7 0x0080U /*!<Bit 7 */
+
+#define TIM_BDTR_LOCK 0x0300U /*!<LOCK[1:0] bits (Lock Configuration) */
+#define TIM_BDTR_LOCK_0 0x0100U /*!<Bit 0 */
+#define TIM_BDTR_LOCK_1 0x0200U /*!<Bit 1 */
+
+#define TIM_BDTR_OSSI 0x0400U /*!<Off-State Selection for Idle mode */
+#define TIM_BDTR_OSSR 0x0800U /*!<Off-State Selection for Run mode */
+#define TIM_BDTR_BKE 0x1000U /*!<Break enable */
+#define TIM_BDTR_BKP 0x2000U /*!<Break Polarity */
+#define TIM_BDTR_AOE 0x4000U /*!<Automatic Output enable */
+#define TIM_BDTR_MOE 0x8000U /*!<Main Output enable */
+
+/******************* Bit definition for TIM_DCR register ********************/
+#define TIM_DCR_DBA 0x001FU /*!<DBA[4:0] bits (DMA Base Address) */
+#define TIM_DCR_DBA_0 0x0001U /*!<Bit 0 */
+#define TIM_DCR_DBA_1 0x0002U /*!<Bit 1 */
+#define TIM_DCR_DBA_2 0x0004U /*!<Bit 2 */
+#define TIM_DCR_DBA_3 0x0008U /*!<Bit 3 */
+#define TIM_DCR_DBA_4 0x0010U /*!<Bit 4 */
+
+#define TIM_DCR_DBL 0x1F00U /*!<DBL[4:0] bits (DMA Burst Length) */
+#define TIM_DCR_DBL_0 0x0100U /*!<Bit 0 */
+#define TIM_DCR_DBL_1 0x0200U /*!<Bit 1 */
+#define TIM_DCR_DBL_2 0x0400U /*!<Bit 2 */
+#define TIM_DCR_DBL_3 0x0800U /*!<Bit 3 */
+#define TIM_DCR_DBL_4 0x1000U /*!<Bit 4 */
+
+/******************* Bit definition for TIM_DMAR register *******************/
+#define TIM_DMAR_DMAB 0xFFFFU /*!<DMA register for burst accesses */
+
+/******************* Bit definition for TIM_OR register *********************/
+#define TIM_OR_TI4_RMP 0x00C0U /*!<TI4_RMP[1:0] bits (TIM5 Input 4 remap) */
+#define TIM_OR_TI4_RMP_0 0x0040U /*!<Bit 0 */
+#define TIM_OR_TI4_RMP_1 0x0080U /*!<Bit 1 */
+#define TIM_OR_ITR1_RMP 0x0C00U /*!<ITR1_RMP[1:0] bits (TIM2 Internal trigger 1 remap) */
+#define TIM_OR_ITR1_RMP_0 0x0400U /*!<Bit 0 */
+#define TIM_OR_ITR1_RMP_1 0x0800U /*!<Bit 1 */
+
+
+/******************************************************************************/
+/* */
+/* Universal Synchronous Asynchronous Receiver Transmitter */
+/* */
+/******************************************************************************/
+/******************* Bit definition for USART_SR register *******************/
+#define USART_SR_PE 0x0001U /*!<Parity Error */
+#define USART_SR_FE 0x0002U /*!<Framing Error */
+#define USART_SR_NE 0x0004U /*!<Noise Error Flag */
+#define USART_SR_ORE 0x0008U /*!<OverRun Error */
+#define USART_SR_IDLE 0x0010U /*!<IDLE line detected */
+#define USART_SR_RXNE 0x0020U /*!<Read Data Register Not Empty */
+#define USART_SR_TC 0x0040U /*!<Transmission Complete */
+#define USART_SR_TXE 0x0080U /*!<Transmit Data Register Empty */
+#define USART_SR_LBD 0x0100U /*!<LIN Break Detection Flag */
+#define USART_SR_CTS 0x0200U /*!<CTS Flag */
+
+/******************* Bit definition for USART_DR register *******************/
+#define USART_DR_DR 0x01FFU /*!<Data value */
+
+/****************** Bit definition for USART_BRR register *******************/
+#define USART_BRR_DIV_Fraction 0x000FU /*!<Fraction of USARTDIV */
+#define USART_BRR_DIV_Mantissa 0xFFF0U /*!<Mantissa of USARTDIV */
+
+/****************** Bit definition for USART_CR1 register *******************/
+#define USART_CR1_SBK 0x0001U /*!<Send Break */
+#define USART_CR1_RWU 0x0002U /*!<Receiver wakeup */
+#define USART_CR1_RE 0x0004U /*!<Receiver Enable */
+#define USART_CR1_TE 0x0008U /*!<Transmitter Enable */
+#define USART_CR1_IDLEIE 0x0010U /*!<IDLE Interrupt Enable */
+#define USART_CR1_RXNEIE 0x0020U /*!<RXNE Interrupt Enable */
+#define USART_CR1_TCIE 0x0040U /*!<Transmission Complete Interrupt Enable */
+#define USART_CR1_TXEIE 0x0080U /*!<PE Interrupt Enable */
+#define USART_CR1_PEIE 0x0100U /*!<PE Interrupt Enable */
+#define USART_CR1_PS 0x0200U /*!<Parity Selection */
+#define USART_CR1_PCE 0x0400U /*!<Parity Control Enable */
+#define USART_CR1_WAKE 0x0800U /*!<Wakeup method */
+#define USART_CR1_M 0x1000U /*!<Word length */
+#define USART_CR1_UE 0x2000U /*!<USART Enable */
+#define USART_CR1_OVER8 0x8000U /*!<USART Oversampling by 8 enable */
+
+/****************** Bit definition for USART_CR2 register *******************/
+#define USART_CR2_ADD 0x000FU /*!<Address of the USART node */
+#define USART_CR2_LBDL 0x0020U /*!<LIN Break Detection Length */
+#define USART_CR2_LBDIE 0x0040U /*!<LIN Break Detection Interrupt Enable */
+#define USART_CR2_LBCL 0x0100U /*!<Last Bit Clock pulse */
+#define USART_CR2_CPHA 0x0200U /*!<Clock Phase */
+#define USART_CR2_CPOL 0x0400U /*!<Clock Polarity */
+#define USART_CR2_CLKEN 0x0800U /*!<Clock Enable */
+
+#define USART_CR2_STOP 0x3000U /*!<STOP[1:0] bits (STOP bits) */
+#define USART_CR2_STOP_0 0x1000U /*!<Bit 0 */
+#define USART_CR2_STOP_1 0x2000U /*!<Bit 1 */
+
+#define USART_CR2_LINEN 0x4000U /*!<LIN mode enable */
+
+/****************** Bit definition for USART_CR3 register *******************/
+#define USART_CR3_EIE 0x0001U /*!<Error Interrupt Enable */
+#define USART_CR3_IREN 0x0002U /*!<IrDA mode Enable */
+#define USART_CR3_IRLP 0x0004U /*!<IrDA Low-Power */
+#define USART_CR3_HDSEL 0x0008U /*!<Half-Duplex Selection */
+#define USART_CR3_NACK 0x0010U /*!<Smartcard NACK enable */
+#define USART_CR3_SCEN 0x0020U /*!<Smartcard mode enable */
+#define USART_CR3_DMAR 0x0040U /*!<DMA Enable Receiver */
+#define USART_CR3_DMAT 0x0080U /*!<DMA Enable Transmitter */
+#define USART_CR3_RTSE 0x0100U /*!<RTS Enable */
+#define USART_CR3_CTSE 0x0200U /*!<CTS Enable */
+#define USART_CR3_CTSIE 0x0400U /*!<CTS Interrupt Enable */
+#define USART_CR3_ONEBIT 0x0800U /*!<USART One bit method enable */
+
+/****************** Bit definition for USART_GTPR register ******************/
+#define USART_GTPR_PSC 0x00FFU /*!<PSC[7:0] bits (Prescaler value) */
+#define USART_GTPR_PSC_0 0x0001U /*!<Bit 0 */
+#define USART_GTPR_PSC_1 0x0002U /*!<Bit 1 */
+#define USART_GTPR_PSC_2 0x0004U /*!<Bit 2 */
+#define USART_GTPR_PSC_3 0x0008U /*!<Bit 3 */
+#define USART_GTPR_PSC_4 0x0010U /*!<Bit 4 */
+#define USART_GTPR_PSC_5 0x0020U /*!<Bit 5 */
+#define USART_GTPR_PSC_6 0x0040U /*!<Bit 6 */
+#define USART_GTPR_PSC_7 0x0080U /*!<Bit 7 */
+
+#define USART_GTPR_GT 0xFF00U /*!<Guard time value */
+
+/******************************************************************************/
+/* */
+/* Window WATCHDOG */
+/* */
+/******************************************************************************/
+/******************* Bit definition for WWDG_CR register ********************/
+#define WWDG_CR_T 0x7FU /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
+#define WWDG_CR_T_0 0x01U /*!<Bit 0 */
+#define WWDG_CR_T_1 0x02U /*!<Bit 1 */
+#define WWDG_CR_T_2 0x04U /*!<Bit 2 */
+#define WWDG_CR_T_3 0x08U /*!<Bit 3 */
+#define WWDG_CR_T_4 0x10U /*!<Bit 4 */
+#define WWDG_CR_T_5 0x20U /*!<Bit 5 */
+#define WWDG_CR_T_6 0x40U /*!<Bit 6 */
+/* Legacy defines */
+#define WWDG_CR_T0 WWDG_CR_T_0
+#define WWDG_CR_T1 WWDG_CR_T_1
+#define WWDG_CR_T2 WWDG_CR_T_2
+#define WWDG_CR_T3 WWDG_CR_T_3
+#define WWDG_CR_T4 WWDG_CR_T_4
+#define WWDG_CR_T5 WWDG_CR_T_5
+#define WWDG_CR_T6 WWDG_CR_T_6
+
+#define WWDG_CR_WDGA 0x80U /*!<Activation bit */
+
+/******************* Bit definition for WWDG_CFR register *******************/
+#define WWDG_CFR_W 0x007FU /*!<W[6:0] bits (7-bit window value) */
+#define WWDG_CFR_W_0 0x0001U /*!<Bit 0 */
+#define WWDG_CFR_W_1 0x0002U /*!<Bit 1 */
+#define WWDG_CFR_W_2 0x0004U /*!<Bit 2 */
+#define WWDG_CFR_W_3 0x0008U /*!<Bit 3 */
+#define WWDG_CFR_W_4 0x0010U /*!<Bit 4 */
+#define WWDG_CFR_W_5 0x0020U /*!<Bit 5 */
+#define WWDG_CFR_W_6 0x0040U /*!<Bit 6 */
+/* Legacy defines */
+#define WWDG_CFR_W0 WWDG_CFR_W_0
+#define WWDG_CFR_W1 WWDG_CFR_W_1
+#define WWDG_CFR_W2 WWDG_CFR_W_2
+#define WWDG_CFR_W3 WWDG_CFR_W_3
+#define WWDG_CFR_W4 WWDG_CFR_W_4
+#define WWDG_CFR_W5 WWDG_CFR_W_5
+#define WWDG_CFR_W6 WWDG_CFR_W_6
+
+#define WWDG_CFR_WDGTB 0x0180U /*!<WDGTB[1:0] bits (Timer Base) */
+#define WWDG_CFR_WDGTB_0 0x0080U /*!<Bit 0 */
+#define WWDG_CFR_WDGTB_1 0x0100U /*!<Bit 1 */
+/* Legacy defines */
+#define WWDG_CFR_WDGTB0 WWDG_CFR_WDGTB_0
+#define WWDG_CFR_WDGTB1 WWDG_CFR_WDGTB_1
+
+#define WWDG_CFR_EWI 0x0200U /*!<Early Wakeup Interrupt */
+
+/******************* Bit definition for WWDG_SR register ********************/
+#define WWDG_SR_EWIF 0x01U /*!<Early Wakeup Interrupt Flag */
+
+
+/******************************************************************************/
+/* */
+/* DBG */
+/* */
+/******************************************************************************/
+/******************** Bit definition for DBGMCU_IDCODE register *************/
+#define DBGMCU_IDCODE_DEV_ID 0x00000FFFU
+#define DBGMCU_IDCODE_REV_ID 0xFFFF0000U
+
+/******************** Bit definition for DBGMCU_CR register *****************/
+#define DBGMCU_CR_DBG_SLEEP 0x00000001U
+#define DBGMCU_CR_DBG_STOP 0x00000002U
+#define DBGMCU_CR_DBG_STANDBY 0x00000004U
+#define DBGMCU_CR_TRACE_IOEN 0x00000020U
+
+#define DBGMCU_CR_TRACE_MODE 0x000000C0U
+#define DBGMCU_CR_TRACE_MODE_0 0x00000040U/*!<Bit 0 */
+#define DBGMCU_CR_TRACE_MODE_1 0x00000080U/*!<Bit 1 */
+
+/******************** Bit definition for DBGMCU_APB1_FZ register ************/
+#define DBGMCU_APB1_FZ_DBG_TIM2_STOP 0x00000001U
+#define DBGMCU_APB1_FZ_DBG_TIM3_STOP 0x00000002U
+#define DBGMCU_APB1_FZ_DBG_TIM4_STOP 0x00000004U
+#define DBGMCU_APB1_FZ_DBG_TIM5_STOP 0x00000008U
+#define DBGMCU_APB1_FZ_DBG_TIM6_STOP 0x00000010U
+#define DBGMCU_APB1_FZ_DBG_TIM7_STOP 0x00000020U
+#define DBGMCU_APB1_FZ_DBG_TIM12_STOP 0x00000040U
+#define DBGMCU_APB1_FZ_DBG_TIM13_STOP 0x00000080U
+#define DBGMCU_APB1_FZ_DBG_TIM14_STOP 0x00000100U
+#define DBGMCU_APB1_FZ_DBG_RTC_STOP 0x00000400U
+#define DBGMCU_APB1_FZ_DBG_WWDG_STOP 0x00000800U
+#define DBGMCU_APB1_FZ_DBG_IWDG_STOP 0x00001000U
+#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT 0x00200000U
+#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT 0x00400000U
+#define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT 0x00800000U
+#define DBGMCU_APB1_FZ_DBG_CAN1_STOP 0x02000000U
+#define DBGMCU_APB1_FZ_DBG_CAN2_STOP 0x04000000U
+/* Old IWDGSTOP bit definition, maintained for legacy purpose */
+#define DBGMCU_APB1_FZ_DBG_IWDEG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP
+
+/******************** Bit definition for DBGMCU_APB2_FZ register ************/
+#define DBGMCU_APB2_FZ_DBG_TIM1_STOP 0x00000001U
+#define DBGMCU_APB2_FZ_DBG_TIM8_STOP 0x00000002U
+#define DBGMCU_APB2_FZ_DBG_TIM9_STOP 0x00010000U
+#define DBGMCU_APB2_FZ_DBG_TIM10_STOP 0x00020000U
+#define DBGMCU_APB2_FZ_DBG_TIM11_STOP 0x00040000U
+
+/******************************************************************************/
+/* */
+/* USB_OTG */
+/* */
+/******************************************************************************/
+/******************** Bit definition forUSB_OTG_GOTGCTL register ********************/
+#define USB_OTG_GOTGCTL_SRQSCS 0x00000001U /*!< Session request success */
+#define USB_OTG_GOTGCTL_SRQ 0x00000002U /*!< Session request */
+#define USB_OTG_GOTGCTL_HNGSCS 0x00000100U /*!< Host negotiation success */
+#define USB_OTG_GOTGCTL_HNPRQ 0x00000200U /*!< HNP request */
+#define USB_OTG_GOTGCTL_HSHNPEN 0x00000400U /*!< Host set HNP enable */
+#define USB_OTG_GOTGCTL_DHNPEN 0x00000800U /*!< Device HNP enabled */
+#define USB_OTG_GOTGCTL_CIDSTS 0x00010000U /*!< Connector ID status */
+#define USB_OTG_GOTGCTL_DBCT 0x00020000U /*!< Long/short debounce time */
+#define USB_OTG_GOTGCTL_ASVLD 0x00040000U /*!< A-session valid */
+#define USB_OTG_GOTGCTL_BSVLD 0x00080000U /*!< B-session valid */
+
+/******************** Bit definition forUSB_OTG_HCFG register ********************/
+
+#define USB_OTG_HCFG_FSLSPCS 0x00000003U /*!< FS/LS PHY clock select */
+#define USB_OTG_HCFG_FSLSPCS_0 0x00000001U /*!<Bit 0 */
+#define USB_OTG_HCFG_FSLSPCS_1 0x00000002U /*!<Bit 1 */
+#define USB_OTG_HCFG_FSLSS 0x00000004U /*!< FS- and LS-only support */
+
+/******************** Bit definition forUSB_OTG_DCFG register ********************/
+
+#define USB_OTG_DCFG_DSPD 0x00000003U /*!< Device speed */
+#define USB_OTG_DCFG_DSPD_0 0x00000001U /*!<Bit 0 */
+#define USB_OTG_DCFG_DSPD_1 0x00000002U /*!<Bit 1 */
+#define USB_OTG_DCFG_NZLSOHSK 0x00000004U /*!< Nonzero-length status OUT handshake */
+
+#define USB_OTG_DCFG_DAD 0x000007F0U /*!< Device address */
+#define USB_OTG_DCFG_DAD_0 0x00000010U /*!<Bit 0 */
+#define USB_OTG_DCFG_DAD_1 0x00000020U /*!<Bit 1 */
+#define USB_OTG_DCFG_DAD_2 0x00000040U /*!<Bit 2 */
+#define USB_OTG_DCFG_DAD_3 0x00000080U /*!<Bit 3 */
+#define USB_OTG_DCFG_DAD_4 0x00000100U /*!<Bit 4 */
+#define USB_OTG_DCFG_DAD_5 0x00000200U /*!<Bit 5 */
+#define USB_OTG_DCFG_DAD_6 0x00000400U /*!<Bit 6 */
+
+#define USB_OTG_DCFG_PFIVL 0x00001800U /*!< Periodic (micro)frame interval */
+#define USB_OTG_DCFG_PFIVL_0 0x00000800U /*!<Bit 0 */
+#define USB_OTG_DCFG_PFIVL_1 0x00001000U /*!<Bit 1 */
+
+#define USB_OTG_DCFG_PERSCHIVL 0x03000000U /*!< Periodic scheduling interval */
+#define USB_OTG_DCFG_PERSCHIVL_0 0x01000000U /*!<Bit 0 */
+#define USB_OTG_DCFG_PERSCHIVL_1 0x02000000U /*!<Bit 1 */
+
+/******************** Bit definition forUSB_OTG_PCGCR register ********************/
+#define USB_OTG_PCGCR_STPPCLK 0x00000001U /*!< Stop PHY clock */
+#define USB_OTG_PCGCR_GATEHCLK 0x00000002U /*!< Gate HCLK */
+#define USB_OTG_PCGCR_PHYSUSP 0x00000010U /*!< PHY suspended */
+
+/******************** Bit definition forUSB_OTG_GOTGINT register ********************/
+#define USB_OTG_GOTGINT_SEDET 0x00000004U /*!< Session end detected */
+#define USB_OTG_GOTGINT_SRSSCHG 0x00000100U /*!< Session request success status change */
+#define USB_OTG_GOTGINT_HNSSCHG 0x00000200U /*!< Host negotiation success status change */
+#define USB_OTG_GOTGINT_HNGDET 0x00020000U /*!< Host negotiation detected */
+#define USB_OTG_GOTGINT_ADTOCHG 0x00040000U /*!< A-device timeout change */
+#define USB_OTG_GOTGINT_DBCDNE 0x00080000U /*!< Debounce done */
+
+/******************** Bit definition forUSB_OTG_DCTL register ********************/
+#define USB_OTG_DCTL_RWUSIG 0x00000001U /*!< Remote wakeup signaling */
+#define USB_OTG_DCTL_SDIS 0x00000002U /*!< Soft disconnect */
+#define USB_OTG_DCTL_GINSTS 0x00000004U /*!< Global IN NAK status */
+#define USB_OTG_DCTL_GONSTS 0x00000008U /*!< Global OUT NAK status */
+
+#define USB_OTG_DCTL_TCTL 0x00000070U /*!< Test control */
+#define USB_OTG_DCTL_TCTL_0 0x00000010U /*!<Bit 0 */
+#define USB_OTG_DCTL_TCTL_1 0x00000020U /*!<Bit 1 */
+#define USB_OTG_DCTL_TCTL_2 0x00000040U /*!<Bit 2 */
+#define USB_OTG_DCTL_SGINAK 0x00000080U /*!< Set global IN NAK */
+#define USB_OTG_DCTL_CGINAK 0x00000100U /*!< Clear global IN NAK */
+#define USB_OTG_DCTL_SGONAK 0x00000200U /*!< Set global OUT NAK */
+#define USB_OTG_DCTL_CGONAK 0x00000400U /*!< Clear global OUT NAK */
+#define USB_OTG_DCTL_POPRGDNE 0x00000800U /*!< Power-on programming done */
+
+/******************** Bit definition forUSB_OTG_HFIR register ********************/
+#define USB_OTG_HFIR_FRIVL 0x0000FFFFU /*!< Frame interval */
+
+/******************** Bit definition forUSB_OTG_HFNUM register ********************/
+#define USB_OTG_HFNUM_FRNUM 0x0000FFFFU /*!< Frame number */
+#define USB_OTG_HFNUM_FTREM 0xFFFF0000U /*!< Frame time remaining */
+
+/******************** Bit definition forUSB_OTG_DSTS register ********************/
+#define USB_OTG_DSTS_SUSPSTS 0x00000001U /*!< Suspend status */
+
+#define USB_OTG_DSTS_ENUMSPD 0x00000006U /*!< Enumerated speed */
+#define USB_OTG_DSTS_ENUMSPD_0 0x00000002U /*!<Bit 0 */
+#define USB_OTG_DSTS_ENUMSPD_1 0x00000004U /*!<Bit 1 */
+#define USB_OTG_DSTS_EERR 0x00000008U /*!< Erratic error */
+#define USB_OTG_DSTS_FNSOF 0x003FFF00U /*!< Frame number of the received SOF */
+
+/******************** Bit definition forUSB_OTG_GAHBCFG register ********************/
+#define USB_OTG_GAHBCFG_GINT 0x00000001U /*!< Global interrupt mask */
+
+#define USB_OTG_GAHBCFG_HBSTLEN 0x0000001EU /*!< Burst length/type */
+#define USB_OTG_GAHBCFG_HBSTLEN_0 0x00000002U /*!<Bit 0 */
+#define USB_OTG_GAHBCFG_HBSTLEN_1 0x00000004U /*!<Bit 1 */
+#define USB_OTG_GAHBCFG_HBSTLEN_2 0x00000008U /*!<Bit 2 */
+#define USB_OTG_GAHBCFG_HBSTLEN_3 0x00000010U /*!<Bit 3 */
+#define USB_OTG_GAHBCFG_DMAEN 0x00000020U /*!< DMA enable */
+#define USB_OTG_GAHBCFG_TXFELVL 0x00000080U /*!< TxFIFO empty level */
+#define USB_OTG_GAHBCFG_PTXFELVL 0x00000100U /*!< Periodic TxFIFO empty level */
+
+/******************** Bit definition forUSB_OTG_GUSBCFG register ********************/
+
+#define USB_OTG_GUSBCFG_TOCAL 0x00000007U /*!< FS timeout calibration */
+#define USB_OTG_GUSBCFG_TOCAL_0 0x00000001U /*!<Bit 0 */
+#define USB_OTG_GUSBCFG_TOCAL_1 0x00000002U /*!<Bit 1 */
+#define USB_OTG_GUSBCFG_TOCAL_2 0x00000004U /*!<Bit 2 */
+#define USB_OTG_GUSBCFG_PHYSEL 0x00000040U /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */
+#define USB_OTG_GUSBCFG_SRPCAP 0x00000100U /*!< SRP-capable */
+#define USB_OTG_GUSBCFG_HNPCAP 0x00000200U /*!< HNP-capable */
+
+#define USB_OTG_GUSBCFG_TRDT 0x00003C00U /*!< USB turnaround time */
+#define USB_OTG_GUSBCFG_TRDT_0 0x00000400U /*!<Bit 0 */
+#define USB_OTG_GUSBCFG_TRDT_1 0x00000800U /*!<Bit 1 */
+#define USB_OTG_GUSBCFG_TRDT_2 0x00001000U /*!<Bit 2 */
+#define USB_OTG_GUSBCFG_TRDT_3 0x00002000U /*!<Bit 3 */
+#define USB_OTG_GUSBCFG_PHYLPCS 0x00008000U /*!< PHY Low-power clock select */
+#define USB_OTG_GUSBCFG_ULPIFSLS 0x00020000U /*!< ULPI FS/LS select */
+#define USB_OTG_GUSBCFG_ULPIAR 0x00040000U /*!< ULPI Auto-resume */
+#define USB_OTG_GUSBCFG_ULPICSM 0x00080000U /*!< ULPI Clock SuspendM */
+#define USB_OTG_GUSBCFG_ULPIEVBUSD 0x00100000U /*!< ULPI External VBUS Drive */
+#define USB_OTG_GUSBCFG_ULPIEVBUSI 0x00200000U /*!< ULPI external VBUS indicator */
+#define USB_OTG_GUSBCFG_TSDPS 0x00400000U /*!< TermSel DLine pulsing selection */
+#define USB_OTG_GUSBCFG_PCCI 0x00800000U /*!< Indicator complement */
+#define USB_OTG_GUSBCFG_PTCI 0x01000000U /*!< Indicator pass through */
+#define USB_OTG_GUSBCFG_ULPIIPD 0x02000000U /*!< ULPI interface protect disable */
+#define USB_OTG_GUSBCFG_FHMOD 0x20000000U /*!< Forced host mode */
+#define USB_OTG_GUSBCFG_FDMOD 0x40000000U /*!< Forced peripheral mode */
+#define USB_OTG_GUSBCFG_CTXPKT 0x80000000U /*!< Corrupt Tx packet */
+
+/******************** Bit definition forUSB_OTG_GRSTCTL register ********************/
+#define USB_OTG_GRSTCTL_CSRST 0x00000001U /*!< Core soft reset */
+#define USB_OTG_GRSTCTL_HSRST 0x00000002U /*!< HCLK soft reset */
+#define USB_OTG_GRSTCTL_FCRST 0x00000004U /*!< Host frame counter reset */
+#define USB_OTG_GRSTCTL_RXFFLSH 0x00000010U /*!< RxFIFO flush */
+#define USB_OTG_GRSTCTL_TXFFLSH 0x00000020U /*!< TxFIFO flush */
+
+#define USB_OTG_GRSTCTL_TXFNUM 0x000007C0U /*!< TxFIFO number */
+#define USB_OTG_GRSTCTL_TXFNUM_0 0x00000040U /*!<Bit 0 */
+#define USB_OTG_GRSTCTL_TXFNUM_1 0x00000080U /*!<Bit 1 */
+#define USB_OTG_GRSTCTL_TXFNUM_2 0x00000100U /*!<Bit 2 */
+#define USB_OTG_GRSTCTL_TXFNUM_3 0x00000200U /*!<Bit 3 */
+#define USB_OTG_GRSTCTL_TXFNUM_4 0x00000400U /*!<Bit 4 */
+#define USB_OTG_GRSTCTL_DMAREQ 0x40000000U /*!< DMA request signal */
+#define USB_OTG_GRSTCTL_AHBIDL 0x80000000U /*!< AHB master idle */
+
+/******************** Bit definition forUSB_OTG_DIEPMSK register ********************/
+#define USB_OTG_DIEPMSK_XFRCM 0x00000001U /*!< Transfer completed interrupt mask */
+#define USB_OTG_DIEPMSK_EPDM 0x00000002U /*!< Endpoint disabled interrupt mask */
+#define USB_OTG_DIEPMSK_TOM 0x00000008U /*!< Timeout condition mask (nonisochronous endpoints) */
+#define USB_OTG_DIEPMSK_ITTXFEMSK 0x00000010U /*!< IN token received when TxFIFO empty mask */
+#define USB_OTG_DIEPMSK_INEPNMM 0x00000020U /*!< IN token received with EP mismatch mask */
+#define USB_OTG_DIEPMSK_INEPNEM 0x00000040U /*!< IN endpoint NAK effective mask */
+#define USB_OTG_DIEPMSK_TXFURM 0x00000100U /*!< FIFO underrun mask */
+#define USB_OTG_DIEPMSK_BIM 0x00000200U /*!< BNA interrupt mask */
+
+/******************** Bit definition forUSB_OTG_HPTXSTS register ********************/
+#define USB_OTG_HPTXSTS_PTXFSAVL 0x0000FFFFU /*!< Periodic transmit data FIFO space available */
+
+#define USB_OTG_HPTXSTS_PTXQSAV 0x00FF0000U /*!< Periodic transmit request queue space available */
+#define USB_OTG_HPTXSTS_PTXQSAV_0 0x00010000U /*!<Bit 0 */
+#define USB_OTG_HPTXSTS_PTXQSAV_1 0x00020000U /*!<Bit 1 */
+#define USB_OTG_HPTXSTS_PTXQSAV_2 0x00040000U /*!<Bit 2 */
+#define USB_OTG_HPTXSTS_PTXQSAV_3 0x00080000U /*!<Bit 3 */
+#define USB_OTG_HPTXSTS_PTXQSAV_4 0x00100000U /*!<Bit 4 */
+#define USB_OTG_HPTXSTS_PTXQSAV_5 0x00200000U /*!<Bit 5 */
+#define USB_OTG_HPTXSTS_PTXQSAV_6 0x00400000U /*!<Bit 6 */
+#define USB_OTG_HPTXSTS_PTXQSAV_7 0x00800000U /*!<Bit 7 */
+
+#define USB_OTG_HPTXSTS_PTXQTOP 0xFF000000U /*!< Top of the periodic transmit request queue */
+#define USB_OTG_HPTXSTS_PTXQTOP_0 0x01000000U /*!<Bit 0 */
+#define USB_OTG_HPTXSTS_PTXQTOP_1 0x02000000U /*!<Bit 1 */
+#define USB_OTG_HPTXSTS_PTXQTOP_2 0x04000000U /*!<Bit 2 */
+#define USB_OTG_HPTXSTS_PTXQTOP_3 0x08000000U /*!<Bit 3 */
+#define USB_OTG_HPTXSTS_PTXQTOP_4 0x10000000U /*!<Bit 4 */
+#define USB_OTG_HPTXSTS_PTXQTOP_5 0x20000000U /*!<Bit 5 */
+#define USB_OTG_HPTXSTS_PTXQTOP_6 0x40000000U /*!<Bit 6 */
+#define USB_OTG_HPTXSTS_PTXQTOP_7 0x80000000U /*!<Bit 7 */
+
+/******************** Bit definition forUSB_OTG_HAINT register ********************/
+#define USB_OTG_HAINT_HAINT 0x0000FFFFU /*!< Channel interrupts */
+
+/******************** Bit definition forUSB_OTG_DOEPMSK register ********************/
+#define USB_OTG_DOEPMSK_XFRCM 0x00000001U /*!< Transfer completed interrupt mask */
+#define USB_OTG_DOEPMSK_EPDM 0x00000002U /*!< Endpoint disabled interrupt mask */
+#define USB_OTG_DOEPMSK_STUPM 0x00000008U /*!< SETUP phase done mask */
+#define USB_OTG_DOEPMSK_OTEPDM 0x00000010U /*!< OUT token received when endpoint disabled mask */
+#define USB_OTG_DOEPMSK_B2BSTUP 0x00000040U /*!< Back-to-back SETUP packets received mask */
+#define USB_OTG_DOEPMSK_OPEM 0x00000100U /*!< OUT packet error mask */
+#define USB_OTG_DOEPMSK_BOIM 0x00000200U /*!< BNA interrupt mask */
+
+/******************** Bit definition forUSB_OTG_GINTSTS register ********************/
+#define USB_OTG_GINTSTS_CMOD 0x00000001U /*!< Current mode of operation */
+#define USB_OTG_GINTSTS_MMIS 0x00000002U /*!< Mode mismatch interrupt */
+#define USB_OTG_GINTSTS_OTGINT 0x00000004U /*!< OTG interrupt */
+#define USB_OTG_GINTSTS_SOF 0x00000008U /*!< Start of frame */
+#define USB_OTG_GINTSTS_RXFLVL 0x00000010U /*!< RxFIFO nonempty */
+#define USB_OTG_GINTSTS_NPTXFE 0x00000020U /*!< Nonperiodic TxFIFO empty */
+#define USB_OTG_GINTSTS_GINAKEFF 0x00000040U /*!< Global IN nonperiodic NAK effective */
+#define USB_OTG_GINTSTS_BOUTNAKEFF 0x00000080U /*!< Global OUT NAK effective */
+#define USB_OTG_GINTSTS_ESUSP 0x00000400U /*!< Early suspend */
+#define USB_OTG_GINTSTS_USBSUSP 0x00000800U /*!< USB suspend */
+#define USB_OTG_GINTSTS_USBRST 0x00001000U /*!< USB reset */
+#define USB_OTG_GINTSTS_ENUMDNE 0x00002000U /*!< Enumeration done */
+#define USB_OTG_GINTSTS_ISOODRP 0x00004000U /*!< Isochronous OUT packet dropped interrupt */
+#define USB_OTG_GINTSTS_EOPF 0x00008000U /*!< End of periodic frame interrupt */
+#define USB_OTG_GINTSTS_IEPINT 0x00040000U /*!< IN endpoint interrupt */
+#define USB_OTG_GINTSTS_OEPINT 0x00080000U /*!< OUT endpoint interrupt */
+#define USB_OTG_GINTSTS_IISOIXFR 0x00100000U /*!< Incomplete isochronous IN transfer */
+#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT 0x00200000U /*!< Incomplete periodic transfer */
+#define USB_OTG_GINTSTS_DATAFSUSP 0x00400000U /*!< Data fetch suspended */
+#define USB_OTG_GINTSTS_HPRTINT 0x01000000U /*!< Host port interrupt */
+#define USB_OTG_GINTSTS_HCINT 0x02000000U /*!< Host channels interrupt */
+#define USB_OTG_GINTSTS_PTXFE 0x04000000U /*!< Periodic TxFIFO empty */
+#define USB_OTG_GINTSTS_CIDSCHG 0x10000000U /*!< Connector ID status change */
+#define USB_OTG_GINTSTS_DISCINT 0x20000000U /*!< Disconnect detected interrupt */
+#define USB_OTG_GINTSTS_SRQINT 0x40000000U /*!< Session request/new session detected interrupt */
+#define USB_OTG_GINTSTS_WKUINT 0x80000000U /*!< Resume/remote wakeup detected interrupt */
+
+/******************** Bit definition forUSB_OTG_GINTMSK register ********************/
+#define USB_OTG_GINTMSK_MMISM 0x00000002U /*!< Mode mismatch interrupt mask */
+#define USB_OTG_GINTMSK_OTGINT 0x00000004U /*!< OTG interrupt mask */
+#define USB_OTG_GINTMSK_SOFM 0x00000008U /*!< Start of frame mask */
+#define USB_OTG_GINTMSK_RXFLVLM 0x00000010U /*!< Receive FIFO nonempty mask */
+#define USB_OTG_GINTMSK_NPTXFEM 0x00000020U /*!< Nonperiodic TxFIFO empty mask */
+#define USB_OTG_GINTMSK_GINAKEFFM 0x00000040U /*!< Global nonperiodic IN NAK effective mask */
+#define USB_OTG_GINTMSK_GONAKEFFM 0x00000080U /*!< Global OUT NAK effective mask */
+#define USB_OTG_GINTMSK_ESUSPM 0x00000400U /*!< Early suspend mask */
+#define USB_OTG_GINTMSK_USBSUSPM 0x00000800U /*!< USB suspend mask */
+#define USB_OTG_GINTMSK_USBRST 0x00001000U /*!< USB reset mask */
+#define USB_OTG_GINTMSK_ENUMDNEM 0x00002000U /*!< Enumeration done mask */
+#define USB_OTG_GINTMSK_ISOODRPM 0x00004000U /*!< Isochronous OUT packet dropped interrupt mask */
+#define USB_OTG_GINTMSK_EOPFM 0x00008000U /*!< End of periodic frame interrupt mask */
+#define USB_OTG_GINTMSK_EPMISM 0x00020000U /*!< Endpoint mismatch interrupt mask */
+#define USB_OTG_GINTMSK_IEPINT 0x00040000U /*!< IN endpoints interrupt mask */
+#define USB_OTG_GINTMSK_OEPINT 0x00080000U /*!< OUT endpoints interrupt mask */
+#define USB_OTG_GINTMSK_IISOIXFRM 0x00100000U /*!< Incomplete isochronous IN transfer mask */
+#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM 0x00200000U /*!< Incomplete periodic transfer mask */
+#define USB_OTG_GINTMSK_FSUSPM 0x00400000U /*!< Data fetch suspended mask */
+#define USB_OTG_GINTMSK_PRTIM 0x01000000U /*!< Host port interrupt mask */
+#define USB_OTG_GINTMSK_HCIM 0x02000000U /*!< Host channels interrupt mask */
+#define USB_OTG_GINTMSK_PTXFEM 0x04000000U /*!< Periodic TxFIFO empty mask */
+#define USB_OTG_GINTMSK_CIDSCHGM 0x10000000U /*!< Connector ID status change mask */
+#define USB_OTG_GINTMSK_DISCINT 0x20000000U /*!< Disconnect detected interrupt mask */
+#define USB_OTG_GINTMSK_SRQIM 0x40000000U /*!< Session request/new session detected interrupt mask */
+#define USB_OTG_GINTMSK_WUIM 0x80000000U /*!< Resume/remote wakeup detected interrupt mask */
+
+/******************** Bit definition forUSB_OTG_DAINT register ********************/
+#define USB_OTG_DAINT_IEPINT 0x0000FFFFU /*!< IN endpoint interrupt bits */
+#define USB_OTG_DAINT_OEPINT 0xFFFF0000U /*!< OUT endpoint interrupt bits */
+
+/******************** Bit definition forUSB_OTG_HAINTMSK register ********************/
+#define USB_OTG_HAINTMSK_HAINTM 0x0000FFFFU /*!< Channel interrupt mask */
+
+/******************** Bit definition for USB_OTG_GRXSTSP register ********************/
+#define USB_OTG_GRXSTSP_EPNUM 0x0000000FU /*!< IN EP interrupt mask bits */
+#define USB_OTG_GRXSTSP_BCNT 0x00007FF0U /*!< OUT EP interrupt mask bits */
+#define USB_OTG_GRXSTSP_DPID 0x00018000U /*!< OUT EP interrupt mask bits */
+#define USB_OTG_GRXSTSP_PKTSTS 0x001E0000U /*!< OUT EP interrupt mask bits */
+
+/******************** Bit definition forUSB_OTG_DAINTMSK register ********************/
+#define USB_OTG_DAINTMSK_IEPM 0x0000FFFFU /*!< IN EP interrupt mask bits */
+#define USB_OTG_DAINTMSK_OEPM 0xFFFF0000U /*!< OUT EP interrupt mask bits */
+
+/******************** Bit definition for OTG register ********************/
+
+#define USB_OTG_CHNUM 0x0000000FU /*!< Channel number */
+#define USB_OTG_CHNUM_0 0x00000001U /*!<Bit 0 */
+#define USB_OTG_CHNUM_1 0x00000002U /*!<Bit 1 */
+#define USB_OTG_CHNUM_2 0x00000004U /*!<Bit 2 */
+#define USB_OTG_CHNUM_3 0x00000008U /*!<Bit 3 */
+#define USB_OTG_BCNT 0x00007FF0U /*!< Byte count */
+
+#define USB_OTG_DPID 0x00018000U /*!< Data PID */
+#define USB_OTG_DPID_0 0x00008000U /*!<Bit 0 */
+#define USB_OTG_DPID_1 0x00010000U /*!<Bit 1 */
+
+#define USB_OTG_PKTSTS 0x001E0000U /*!< Packet status */
+#define USB_OTG_PKTSTS_0 0x00020000U /*!<Bit 0 */
+#define USB_OTG_PKTSTS_1 0x00040000U /*!<Bit 1 */
+#define USB_OTG_PKTSTS_2 0x00080000U /*!<Bit 2 */
+#define USB_OTG_PKTSTS_3 0x00100000U /*!<Bit 3 */
+
+#define USB_OTG_EPNUM 0x0000000FU /*!< Endpoint number */
+#define USB_OTG_EPNUM_0 0x00000001U /*!<Bit 0 */
+#define USB_OTG_EPNUM_1 0x00000002U /*!<Bit 1 */
+#define USB_OTG_EPNUM_2 0x00000004U /*!<Bit 2 */
+#define USB_OTG_EPNUM_3 0x00000008U /*!<Bit 3 */
+
+#define USB_OTG_FRMNUM 0x01E00000U /*!< Frame number */
+#define USB_OTG_FRMNUM_0 0x00200000U /*!<Bit 0 */
+#define USB_OTG_FRMNUM_1 0x00400000U /*!<Bit 1 */
+#define USB_OTG_FRMNUM_2 0x00800000U /*!<Bit 2 */
+#define USB_OTG_FRMNUM_3 0x01000000U /*!<Bit 3 */
+
+/******************** Bit definition for OTG register ********************/
+
+#define USB_OTG_CHNUM 0x0000000FU /*!< Channel number */
+#define USB_OTG_CHNUM_0 0x00000001U /*!<Bit 0 */
+#define USB_OTG_CHNUM_1 0x00000002U /*!<Bit 1 */
+#define USB_OTG_CHNUM_2 0x00000004U /*!<Bit 2 */
+#define USB_OTG_CHNUM_3 0x00000008U /*!<Bit 3 */
+#define USB_OTG_BCNT 0x00007FF0U /*!< Byte count */
+
+#define USB_OTG_DPID 0x00018000U /*!< Data PID */
+#define USB_OTG_DPID_0 0x00008000U /*!<Bit 0 */
+#define USB_OTG_DPID_1 0x00010000U /*!<Bit 1 */
+
+#define USB_OTG_PKTSTS 0x001E0000U /*!< Packet status */
+#define USB_OTG_PKTSTS_0 0x00020000U /*!<Bit 0 */
+#define USB_OTG_PKTSTS_1 0x00040000U /*!<Bit 1 */
+#define USB_OTG_PKTSTS_2 0x00080000U /*!<Bit 2 */
+#define USB_OTG_PKTSTS_3 0x00100000U /*!<Bit 3 */
+
+#define USB_OTG_EPNUM 0x0000000FU /*!< Endpoint number */
+#define USB_OTG_EPNUM_0 0x00000001U /*!<Bit 0 */
+#define USB_OTG_EPNUM_1 0x00000002U /*!<Bit 1 */
+#define USB_OTG_EPNUM_2 0x00000004U /*!<Bit 2 */
+#define USB_OTG_EPNUM_3 0x00000008U /*!<Bit 3 */
+
+#define USB_OTG_FRMNUM 0x01E00000U /*!< Frame number */
+#define USB_OTG_FRMNUM_0 0x00200000U /*!<Bit 0 */
+#define USB_OTG_FRMNUM_1 0x00400000U /*!<Bit 1 */
+#define USB_OTG_FRMNUM_2 0x00800000U /*!<Bit 2 */
+#define USB_OTG_FRMNUM_3 0x01000000U /*!<Bit 3 */
+
+/******************** Bit definition forUSB_OTG_GRXFSIZ register ********************/
+#define USB_OTG_GRXFSIZ_RXFD 0x0000FFFFU /*!< RxFIFO depth */
+
+/******************** Bit definition forUSB_OTG_DVBUSDIS register ********************/
+#define USB_OTG_DVBUSDIS_VBUSDT 0x0000FFFFU /*!< Device VBUS discharge time */
+
+/******************** Bit definition for OTG register ********************/
+#define USB_OTG_NPTXFSA 0x0000FFFFU /*!< Nonperiodic transmit RAM start address */
+#define USB_OTG_NPTXFD 0xFFFF0000U /*!< Nonperiodic TxFIFO depth */
+#define USB_OTG_TX0FSA 0x0000FFFFU /*!< Endpoint 0 transmit RAM start address */
+#define USB_OTG_TX0FD 0xFFFF0000U /*!< Endpoint 0 TxFIFO depth */
+
+/******************** Bit definition forUSB_OTG_DVBUSPULSE register ********************/
+#define USB_OTG_DVBUSPULSE_DVBUSP 0x00000FFFU /*!< Device VBUS pulsing time */
+
+/******************** Bit definition forUSB_OTG_GNPTXSTS register ********************/
+#define USB_OTG_GNPTXSTS_NPTXFSAV 0x0000FFFFU /*!< Nonperiodic TxFIFO space available */
+
+#define USB_OTG_GNPTXSTS_NPTQXSAV 0x00FF0000U /*!< Nonperiodic transmit request queue space available */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_0 0x00010000U /*!<Bit 0 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_1 0x00020000U /*!<Bit 1 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_2 0x00040000U /*!<Bit 2 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_3 0x00080000U /*!<Bit 3 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_4 0x00100000U /*!<Bit 4 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_5 0x00200000U /*!<Bit 5 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_6 0x00400000U /*!<Bit 6 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_7 0x00800000U /*!<Bit 7 */
+
+#define USB_OTG_GNPTXSTS_NPTXQTOP 0x7F000000U /*!< Top of the nonperiodic transmit request queue */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_0 0x01000000U /*!<Bit 0 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_1 0x02000000U /*!<Bit 1 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_2 0x04000000U /*!<Bit 2 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_3 0x08000000U /*!<Bit 3 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_4 0x10000000U /*!<Bit 4 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_5 0x20000000U /*!<Bit 5 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_6 0x40000000U /*!<Bit 6 */
+
+/******************** Bit definition forUSB_OTG_DTHRCTL register ********************/
+#define USB_OTG_DTHRCTL_NONISOTHREN 0x00000001U /*!< Nonisochronous IN endpoints threshold enable */
+#define USB_OTG_DTHRCTL_ISOTHREN 0x00000002U /*!< ISO IN endpoint threshold enable */
+
+#define USB_OTG_DTHRCTL_TXTHRLEN 0x000007FCU /*!< Transmit threshold length */
+#define USB_OTG_DTHRCTL_TXTHRLEN_0 0x00000004U /*!<Bit 0 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_1 0x00000008U /*!<Bit 1 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_2 0x00000010U /*!<Bit 2 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_3 0x00000020U /*!<Bit 3 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_4 0x00000040U /*!<Bit 4 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_5 0x00000080U /*!<Bit 5 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_6 0x00000100U /*!<Bit 6 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_7 0x00000200U /*!<Bit 7 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_8 0x00000400U /*!<Bit 8 */
+#define USB_OTG_DTHRCTL_RXTHREN 0x00010000U /*!< Receive threshold enable */
+
+#define USB_OTG_DTHRCTL_RXTHRLEN 0x03FE0000U /*!< Receive threshold length */
+#define USB_OTG_DTHRCTL_RXTHRLEN_0 0x00020000U /*!<Bit 0 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_1 0x00040000U /*!<Bit 1 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_2 0x00080000U /*!<Bit 2 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_3 0x00100000U /*!<Bit 3 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_4 0x00200000U /*!<Bit 4 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_5 0x00400000U /*!<Bit 5 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_6 0x00800000U /*!<Bit 6 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_7 0x01000000U /*!<Bit 7 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_8 0x02000000U /*!<Bit 8 */
+#define USB_OTG_DTHRCTL_ARPEN 0x08000000U /*!< Arbiter parking enable */
+
+/******************** Bit definition forUSB_OTG_DIEPEMPMSK register ********************/
+#define USB_OTG_DIEPEMPMSK_INEPTXFEM 0x0000FFFFU /*!< IN EP Tx FIFO empty interrupt mask bits */
+
+/******************** Bit definition forUSB_OTG_DEACHINT register ********************/
+#define USB_OTG_DEACHINT_IEP1INT 0x00000002U /*!< IN endpoint 1interrupt bit */
+#define USB_OTG_DEACHINT_OEP1INT 0x00020000U /*!< OUT endpoint 1 interrupt bit */
+
+/******************** Bit definition forUSB_OTG_GCCFG register ********************/
+#define USB_OTG_GCCFG_PWRDWN 0x00010000U /*!< Power down */
+#define USB_OTG_GCCFG_I2CPADEN 0x00020000U /*!< Enable I2C bus connection for the external I2C PHY interface */
+#define USB_OTG_GCCFG_VBUSASEN 0x00040000U /*!< Enable the VBUS sensing device */
+#define USB_OTG_GCCFG_VBUSBSEN 0x00080000U /*!< Enable the VBUS sensing device */
+#define USB_OTG_GCCFG_SOFOUTEN 0x00100000U /*!< SOF output enable */
+#define USB_OTG_GCCFG_NOVBUSSENS 0x00200000U /*!< VBUS sensing disable option */
+
+/******************** Bit definition forUSB_OTG_DEACHINTMSK register ********************/
+#define USB_OTG_DEACHINTMSK_IEP1INTM 0x00000002U /*!< IN Endpoint 1 interrupt mask bit */
+#define USB_OTG_DEACHINTMSK_OEP1INTM 0x00020000U /*!< OUT Endpoint 1 interrupt mask bit */
+
+/******************** Bit definition forUSB_OTG_CID register ********************/
+#define USB_OTG_CID_PRODUCT_ID 0xFFFFFFFFU /*!< Product ID field */
+
+/******************** Bit definition forUSB_OTG_DIEPEACHMSK1 register ********************/
+#define USB_OTG_DIEPEACHMSK1_XFRCM 0x00000001U /*!< Transfer completed interrupt mask */
+#define USB_OTG_DIEPEACHMSK1_EPDM 0x00000002U /*!< Endpoint disabled interrupt mask */
+#define USB_OTG_DIEPEACHMSK1_TOM 0x00000008U /*!< Timeout condition mask (nonisochronous endpoints) */
+#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK 0x00000010U /*!< IN token received when TxFIFO empty mask */
+#define USB_OTG_DIEPEACHMSK1_INEPNMM 0x00000020U /*!< IN token received with EP mismatch mask */
+#define USB_OTG_DIEPEACHMSK1_INEPNEM 0x00000040U /*!< IN endpoint NAK effective mask */
+#define USB_OTG_DIEPEACHMSK1_TXFURM 0x00000100U /*!< FIFO underrun mask */
+#define USB_OTG_DIEPEACHMSK1_BIM 0x00000200U /*!< BNA interrupt mask */
+#define USB_OTG_DIEPEACHMSK1_NAKM 0x00002000U /*!< NAK interrupt mask */
+
+/******************** Bit definition forUSB_OTG_HPRT register ********************/
+#define USB_OTG_HPRT_PCSTS 0x00000001U /*!< Port connect status */
+#define USB_OTG_HPRT_PCDET 0x00000002U /*!< Port connect detected */
+#define USB_OTG_HPRT_PENA 0x00000004U /*!< Port enable */
+#define USB_OTG_HPRT_PENCHNG 0x00000008U /*!< Port enable/disable change */
+#define USB_OTG_HPRT_POCA 0x00000010U /*!< Port overcurrent active */
+#define USB_OTG_HPRT_POCCHNG 0x00000020U /*!< Port overcurrent change */
+#define USB_OTG_HPRT_PRES 0x00000040U /*!< Port resume */
+#define USB_OTG_HPRT_PSUSP 0x00000080U /*!< Port suspend */
+#define USB_OTG_HPRT_PRST 0x00000100U /*!< Port reset */
+
+#define USB_OTG_HPRT_PLSTS 0x00000C00U /*!< Port line status */
+#define USB_OTG_HPRT_PLSTS_0 0x00000400U /*!<Bit 0 */
+#define USB_OTG_HPRT_PLSTS_1 0x00000800U /*!<Bit 1 */
+#define USB_OTG_HPRT_PPWR 0x00001000U /*!< Port power */
+
+#define USB_OTG_HPRT_PTCTL 0x0001E000U /*!< Port test control */
+#define USB_OTG_HPRT_PTCTL_0 0x00002000U /*!<Bit 0 */
+#define USB_OTG_HPRT_PTCTL_1 0x00004000U /*!<Bit 1 */
+#define USB_OTG_HPRT_PTCTL_2 0x00008000U /*!<Bit 2 */
+#define USB_OTG_HPRT_PTCTL_3 0x00010000U /*!<Bit 3 */
+
+#define USB_OTG_HPRT_PSPD 0x00060000U /*!< Port speed */
+#define USB_OTG_HPRT_PSPD_0 0x00020000U /*!<Bit 0 */
+#define USB_OTG_HPRT_PSPD_1 0x00040000U /*!<Bit 1 */
+
+/******************** Bit definition forUSB_OTG_DOEPEACHMSK1 register ********************/
+#define USB_OTG_DOEPEACHMSK1_XFRCM 0x00000001U /*!< Transfer completed interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_EPDM 0x00000002U /*!< Endpoint disabled interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_TOM 0x00000008U /*!< Timeout condition mask */
+#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK 0x00000010U /*!< IN token received when TxFIFO empty mask */
+#define USB_OTG_DOEPEACHMSK1_INEPNMM 0x00000020U /*!< IN token received with EP mismatch mask */
+#define USB_OTG_DOEPEACHMSK1_INEPNEM 0x00000040U /*!< IN endpoint NAK effective mask */
+#define USB_OTG_DOEPEACHMSK1_TXFURM 0x00000100U /*!< OUT packet error mask */
+#define USB_OTG_DOEPEACHMSK1_BIM 0x00000200U /*!< BNA interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_BERRM 0x00001000U /*!< Bubble error interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_NAKM 0x00002000U /*!< NAK interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_NYETM 0x00004000U /*!< NYET interrupt mask */
+
+/******************** Bit definition forUSB_OTG_HPTXFSIZ register ********************/
+#define USB_OTG_HPTXFSIZ_PTXSA 0x0000FFFFU /*!< Host periodic TxFIFO start address */
+#define USB_OTG_HPTXFSIZ_PTXFD 0xFFFF0000U /*!< Host periodic TxFIFO depth */
+
+/******************** Bit definition forUSB_OTG_DIEPCTL register ********************/
+#define USB_OTG_DIEPCTL_MPSIZ 0x000007FFU /*!< Maximum packet size */
+#define USB_OTG_DIEPCTL_USBAEP 0x00008000U /*!< USB active endpoint */
+#define USB_OTG_DIEPCTL_EONUM_DPID 0x00010000U /*!< Even/odd frame */
+#define USB_OTG_DIEPCTL_NAKSTS 0x00020000U /*!< NAK status */
+
+#define USB_OTG_DIEPCTL_EPTYP 0x000C0000U /*!< Endpoint type */
+#define USB_OTG_DIEPCTL_EPTYP_0 0x00040000U /*!<Bit 0 */
+#define USB_OTG_DIEPCTL_EPTYP_1 0x00080000U /*!<Bit 1 */
+#define USB_OTG_DIEPCTL_STALL 0x00200000U /*!< STALL handshake */
+
+#define USB_OTG_DIEPCTL_TXFNUM 0x03C00000U /*!< TxFIFO number */
+#define USB_OTG_DIEPCTL_TXFNUM_0 0x00400000U /*!<Bit 0 */
+#define USB_OTG_DIEPCTL_TXFNUM_1 0x00800000U /*!<Bit 1 */
+#define USB_OTG_DIEPCTL_TXFNUM_2 0x01000000U /*!<Bit 2 */
+#define USB_OTG_DIEPCTL_TXFNUM_3 0x02000000U /*!<Bit 3 */
+#define USB_OTG_DIEPCTL_CNAK 0x04000000U /*!< Clear NAK */
+#define USB_OTG_DIEPCTL_SNAK 0x08000000U /*!< Set NAK */
+#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM 0x10000000U /*!< Set DATA0 PID */
+#define USB_OTG_DIEPCTL_SODDFRM 0x20000000U /*!< Set odd frame */
+#define USB_OTG_DIEPCTL_EPDIS 0x40000000U /*!< Endpoint disable */
+#define USB_OTG_DIEPCTL_EPENA 0x80000000U /*!< Endpoint enable */
+
+/******************** Bit definition forUSB_OTG_HCCHAR register ********************/
+#define USB_OTG_HCCHAR_MPSIZ 0x000007FFU /*!< Maximum packet size */
+
+#define USB_OTG_HCCHAR_EPNUM 0x00007800U /*!< Endpoint number */
+#define USB_OTG_HCCHAR_EPNUM_0 0x00000800U /*!<Bit 0 */
+#define USB_OTG_HCCHAR_EPNUM_1 0x00001000U /*!<Bit 1 */
+#define USB_OTG_HCCHAR_EPNUM_2 0x00002000U /*!<Bit 2 */
+#define USB_OTG_HCCHAR_EPNUM_3 0x00004000U /*!<Bit 3 */
+#define USB_OTG_HCCHAR_EPDIR 0x00008000U /*!< Endpoint direction */
+#define USB_OTG_HCCHAR_LSDEV 0x00020000U /*!< Low-speed device */
+
+#define USB_OTG_HCCHAR_EPTYP 0x000C0000U /*!< Endpoint type */
+#define USB_OTG_HCCHAR_EPTYP_0 0x00040000U /*!<Bit 0 */
+#define USB_OTG_HCCHAR_EPTYP_1 0x00080000U /*!<Bit 1 */
+
+#define USB_OTG_HCCHAR_MC 0x00300000U /*!< Multi Count (MC) / Error Count (EC) */
+#define USB_OTG_HCCHAR_MC_0 0x00100000U /*!<Bit 0 */
+#define USB_OTG_HCCHAR_MC_1 0x00200000U /*!<Bit 1 */
+
+#define USB_OTG_HCCHAR_DAD 0x1FC00000U /*!< Device address */
+#define USB_OTG_HCCHAR_DAD_0 0x00400000U /*!<Bit 0 */
+#define USB_OTG_HCCHAR_DAD_1 0x00800000U /*!<Bit 1 */
+#define USB_OTG_HCCHAR_DAD_2 0x01000000U /*!<Bit 2 */
+#define USB_OTG_HCCHAR_DAD_3 0x02000000U /*!<Bit 3 */
+#define USB_OTG_HCCHAR_DAD_4 0x04000000U /*!<Bit 4 */
+#define USB_OTG_HCCHAR_DAD_5 0x08000000U /*!<Bit 5 */
+#define USB_OTG_HCCHAR_DAD_6 0x10000000U /*!<Bit 6 */
+#define USB_OTG_HCCHAR_ODDFRM 0x20000000U /*!< Odd frame */
+#define USB_OTG_HCCHAR_CHDIS 0x40000000U /*!< Channel disable */
+#define USB_OTG_HCCHAR_CHENA 0x80000000U /*!< Channel enable */
+
+/******************** Bit definition forUSB_OTG_HCSPLT register ********************/
+
+#define USB_OTG_HCSPLT_PRTADDR 0x0000007FU /*!< Port address */
+#define USB_OTG_HCSPLT_PRTADDR_0 0x00000001U /*!<Bit 0 */
+#define USB_OTG_HCSPLT_PRTADDR_1 0x00000002U /*!<Bit 1 */
+#define USB_OTG_HCSPLT_PRTADDR_2 0x00000004U /*!<Bit 2 */
+#define USB_OTG_HCSPLT_PRTADDR_3 0x00000008U /*!<Bit 3 */
+#define USB_OTG_HCSPLT_PRTADDR_4 0x00000010U /*!<Bit 4 */
+#define USB_OTG_HCSPLT_PRTADDR_5 0x00000020U /*!<Bit 5 */
+#define USB_OTG_HCSPLT_PRTADDR_6 0x00000040U /*!<Bit 6 */
+
+#define USB_OTG_HCSPLT_HUBADDR 0x00003F80U /*!< Hub address */
+#define USB_OTG_HCSPLT_HUBADDR_0 0x00000080U /*!<Bit 0 */
+#define USB_OTG_HCSPLT_HUBADDR_1 0x00000100U /*!<Bit 1 */
+#define USB_OTG_HCSPLT_HUBADDR_2 0x00000200U /*!<Bit 2 */
+#define USB_OTG_HCSPLT_HUBADDR_3 0x00000400U /*!<Bit 3 */
+#define USB_OTG_HCSPLT_HUBADDR_4 0x00000800U /*!<Bit 4 */
+#define USB_OTG_HCSPLT_HUBADDR_5 0x00001000U /*!<Bit 5 */
+#define USB_OTG_HCSPLT_HUBADDR_6 0x00002000U /*!<Bit 6 */
+
+#define USB_OTG_HCSPLT_XACTPOS 0x0000C000U /*!< XACTPOS */
+#define USB_OTG_HCSPLT_XACTPOS_0 0x00004000U /*!<Bit 0 */
+#define USB_OTG_HCSPLT_XACTPOS_1 0x00008000U /*!<Bit 1 */
+#define USB_OTG_HCSPLT_COMPLSPLT 0x00010000U /*!< Do complete split */
+#define USB_OTG_HCSPLT_SPLITEN 0x80000000U /*!< Split enable */
+
+/******************** Bit definition forUSB_OTG_HCINT register ********************/
+#define USB_OTG_HCINT_XFRC 0x00000001U /*!< Transfer completed */
+#define USB_OTG_HCINT_CHH 0x00000002U /*!< Channel halted */
+#define USB_OTG_HCINT_AHBERR 0x00000004U /*!< AHB error */
+#define USB_OTG_HCINT_STALL 0x00000008U /*!< STALL response received interrupt */
+#define USB_OTG_HCINT_NAK 0x00000010U /*!< NAK response received interrupt */
+#define USB_OTG_HCINT_ACK 0x00000020U /*!< ACK response received/transmitted interrupt */
+#define USB_OTG_HCINT_NYET 0x00000040U /*!< Response received interrupt */
+#define USB_OTG_HCINT_TXERR 0x00000080U /*!< Transaction error */
+#define USB_OTG_HCINT_BBERR 0x00000100U /*!< Babble error */
+#define USB_OTG_HCINT_FRMOR 0x00000200U /*!< Frame overrun */
+#define USB_OTG_HCINT_DTERR 0x00000400U /*!< Data toggle error */
+
+/******************** Bit definition forUSB_OTG_DIEPINT register ********************/
+#define USB_OTG_DIEPINT_XFRC 0x00000001U /*!< Transfer completed interrupt */
+#define USB_OTG_DIEPINT_EPDISD 0x00000002U /*!< Endpoint disabled interrupt */
+#define USB_OTG_DIEPINT_TOC 0x00000008U /*!< Timeout condition */
+#define USB_OTG_DIEPINT_ITTXFE 0x00000010U /*!< IN token received when TxFIFO is empty */
+#define USB_OTG_DIEPINT_INEPNE 0x00000040U /*!< IN endpoint NAK effective */
+#define USB_OTG_DIEPINT_TXFE 0x00000080U /*!< Transmit FIFO empty */
+#define USB_OTG_DIEPINT_TXFIFOUDRN 0x00000100U /*!< Transmit Fifo Underrun */
+#define USB_OTG_DIEPINT_BNA 0x00000200U /*!< Buffer not available interrupt */
+#define USB_OTG_DIEPINT_PKTDRPSTS 0x00000800U /*!< Packet dropped status */
+#define USB_OTG_DIEPINT_BERR 0x00001000U /*!< Babble error interrupt */
+#define USB_OTG_DIEPINT_NAK 0x00002000U /*!< NAK interrupt */
+
+/******************** Bit definition forUSB_OTG_HCINTMSK register ********************/
+#define USB_OTG_HCINTMSK_XFRCM 0x00000001U /*!< Transfer completed mask */
+#define USB_OTG_HCINTMSK_CHHM 0x00000002U /*!< Channel halted mask */
+#define USB_OTG_HCINTMSK_AHBERR 0x00000004U /*!< AHB error */
+#define USB_OTG_HCINTMSK_STALLM 0x00000008U /*!< STALL response received interrupt mask */
+#define USB_OTG_HCINTMSK_NAKM 0x00000010U /*!< NAK response received interrupt mask */
+#define USB_OTG_HCINTMSK_ACKM 0x00000020U /*!< ACK response received/transmitted interrupt mask */
+#define USB_OTG_HCINTMSK_NYET 0x00000040U /*!< response received interrupt mask */
+#define USB_OTG_HCINTMSK_TXERRM 0x00000080U /*!< Transaction error mask */
+#define USB_OTG_HCINTMSK_BBERRM 0x00000100U /*!< Babble error mask */
+#define USB_OTG_HCINTMSK_FRMORM 0x00000200U /*!< Frame overrun mask */
+#define USB_OTG_HCINTMSK_DTERRM 0x00000400U /*!< Data toggle error mask */
+
+/******************** Bit definition for USB_OTG_DIEPTSIZ register ********************/
+
+#define USB_OTG_DIEPTSIZ_XFRSIZ 0x0007FFFFU /*!< Transfer size */
+#define USB_OTG_DIEPTSIZ_PKTCNT 0x1FF80000U /*!< Packet count */
+#define USB_OTG_DIEPTSIZ_MULCNT 0x60000000U /*!< Packet count */
+/******************** Bit definition forUSB_OTG_HCTSIZ register ********************/
+#define USB_OTG_HCTSIZ_XFRSIZ 0x0007FFFFU /*!< Transfer size */
+#define USB_OTG_HCTSIZ_PKTCNT 0x1FF80000U /*!< Packet count */
+#define USB_OTG_HCTSIZ_DOPING 0x80000000U /*!< Do PING */
+#define USB_OTG_HCTSIZ_DPID 0x60000000U /*!< Data PID */
+#define USB_OTG_HCTSIZ_DPID_0 0x20000000U /*!<Bit 0 */
+#define USB_OTG_HCTSIZ_DPID_1 0x40000000U /*!<Bit 1 */
+
+/******************** Bit definition forUSB_OTG_DIEPDMA register ********************/
+#define USB_OTG_DIEPDMA_DMAADDR 0xFFFFFFFFU /*!< DMA address */
+
+/******************** Bit definition forUSB_OTG_HCDMA register ********************/
+#define USB_OTG_HCDMA_DMAADDR 0xFFFFFFFFU /*!< DMA address */
+
+/******************** Bit definition forUSB_OTG_DTXFSTS register ********************/
+#define USB_OTG_DTXFSTS_INEPTFSAV 0x0000FFFFU /*!< IN endpoint TxFIFO space avail */
+
+/******************** Bit definition forUSB_OTG_DIEPTXF register ********************/
+#define USB_OTG_DIEPTXF_INEPTXSA 0x0000FFFFU /*!< IN endpoint FIFOx transmit RAM start address */
+#define USB_OTG_DIEPTXF_INEPTXFD 0xFFFF0000U /*!< IN endpoint TxFIFO depth */
+
+/******************** Bit definition forUSB_OTG_DOEPCTL register ********************/
+
+#define USB_OTG_DOEPCTL_MPSIZ 0x000007FFU /*!< Maximum packet size */ /*!<Bit 1 */
+#define USB_OTG_DOEPCTL_USBAEP 0x00008000U /*!< USB active endpoint */
+#define USB_OTG_DOEPCTL_NAKSTS 0x00020000U /*!< NAK status */
+#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM 0x10000000U /*!< Set DATA0 PID */
+#define USB_OTG_DOEPCTL_SODDFRM 0x20000000U /*!< Set odd frame */
+#define USB_OTG_DOEPCTL_EPTYP 0x000C0000U /*!< Endpoint type */
+#define USB_OTG_DOEPCTL_EPTYP_0 0x00040000U /*!<Bit 0 */
+#define USB_OTG_DOEPCTL_EPTYP_1 0x00080000U /*!<Bit 1 */
+#define USB_OTG_DOEPCTL_SNPM 0x00100000U /*!< Snoop mode */
+#define USB_OTG_DOEPCTL_STALL 0x00200000U /*!< STALL handshake */
+#define USB_OTG_DOEPCTL_CNAK 0x04000000U /*!< Clear NAK */
+#define USB_OTG_DOEPCTL_SNAK 0x08000000U /*!< Set NAK */
+#define USB_OTG_DOEPCTL_EPDIS 0x40000000U /*!< Endpoint disable */
+#define USB_OTG_DOEPCTL_EPENA 0x80000000U /*!< Endpoint enable */
+
+/******************** Bit definition forUSB_OTG_DOEPINT register ********************/
+#define USB_OTG_DOEPINT_XFRC 0x00000001U /*!< Transfer completed interrupt */
+#define USB_OTG_DOEPINT_EPDISD 0x00000002U /*!< Endpoint disabled interrupt */
+#define USB_OTG_DOEPINT_STUP 0x00000008U /*!< SETUP phase done */
+#define USB_OTG_DOEPINT_OTEPDIS 0x00000010U /*!< OUT token received when endpoint disabled */
+#define USB_OTG_DOEPINT_B2BSTUP 0x00000040U /*!< Back-to-back SETUP packets received */
+#define USB_OTG_DOEPINT_NYET 0x00004000U /*!< NYET interrupt */
+
+/******************** Bit definition forUSB_OTG_DOEPTSIZ register ********************/
+
+#define USB_OTG_DOEPTSIZ_XFRSIZ 0x0007FFFFU /*!< Transfer size */
+#define USB_OTG_DOEPTSIZ_PKTCNT 0x1FF80000U /*!< Packet count */
+
+#define USB_OTG_DOEPTSIZ_STUPCNT 0x60000000U /*!< SETUP packet count */
+#define USB_OTG_DOEPTSIZ_STUPCNT_0 0x20000000U /*!<Bit 0 */
+#define USB_OTG_DOEPTSIZ_STUPCNT_1 0x40000000U /*!<Bit 1 */
+
+/******************** Bit definition for PCGCCTL register ********************/
+#define USB_OTG_PCGCCTL_STOPCLK 0x00000001U /*!< SETUP packet count */
+#define USB_OTG_PCGCCTL_GATECLK 0x00000002U /*!<Bit 0 */
+#define USB_OTG_PCGCCTL_PHYSUSP 0x00000010U /*!<Bit 1 */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup Exported_macros
+ * @{
+ */
+
+/******************************* ADC Instances ********************************/
+#define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) || \
+ ((INSTANCE) == ADC2) || \
+ ((INSTANCE) == ADC3))
+
+/******************************* CAN Instances ********************************/
+#define IS_CAN_ALL_INSTANCE(INSTANCE) (((INSTANCE) == CAN1) || \
+ ((INSTANCE) == CAN2))
+
+/******************************* CRC Instances ********************************/
+#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
+
+/******************************* DAC Instances ********************************/
+#define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC)
+
+/******************************** DMA Instances *******************************/
+#define IS_DMA_STREAM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0) || \
+ ((INSTANCE) == DMA1_Stream1) || \
+ ((INSTANCE) == DMA1_Stream2) || \
+ ((INSTANCE) == DMA1_Stream3) || \
+ ((INSTANCE) == DMA1_Stream4) || \
+ ((INSTANCE) == DMA1_Stream5) || \
+ ((INSTANCE) == DMA1_Stream6) || \
+ ((INSTANCE) == DMA1_Stream7) || \
+ ((INSTANCE) == DMA2_Stream0) || \
+ ((INSTANCE) == DMA2_Stream1) || \
+ ((INSTANCE) == DMA2_Stream2) || \
+ ((INSTANCE) == DMA2_Stream3) || \
+ ((INSTANCE) == DMA2_Stream4) || \
+ ((INSTANCE) == DMA2_Stream5) || \
+ ((INSTANCE) == DMA2_Stream6) || \
+ ((INSTANCE) == DMA2_Stream7))
+
+/******************************* GPIO Instances *******************************/
+#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
+ ((INSTANCE) == GPIOB) || \
+ ((INSTANCE) == GPIOC) || \
+ ((INSTANCE) == GPIOD) || \
+ ((INSTANCE) == GPIOE) || \
+ ((INSTANCE) == GPIOF) || \
+ ((INSTANCE) == GPIOG) || \
+ ((INSTANCE) == GPIOH) || \
+ ((INSTANCE) == GPIOI))
+
+/******************************** I2C Instances *******************************/
+#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
+ ((INSTANCE) == I2C2) || \
+ ((INSTANCE) == I2C3))
+
+/******************************** I2S Instances *******************************/
+#define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI2) || \
+ ((INSTANCE) == SPI3))
+
+/*************************** I2S Extended Instances ***************************/
+#define IS_I2S_ALL_INSTANCE_EXT(PERIPH) (((INSTANCE) == SPI2) || \
+ ((INSTANCE) == SPI3) || \
+ ((INSTANCE) == I2S2ext) || \
+ ((INSTANCE) == I2S3ext))
+
+/******************************* RNG Instances ********************************/
+#define IS_RNG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RNG)
+
+/****************************** RTC Instances *********************************/
+#define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
+
+/******************************** SPI Instances *******************************/
+#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
+ ((INSTANCE) == SPI2) || \
+ ((INSTANCE) == SPI3))
+
+/*************************** SPI Extended Instances ***************************/
+#define IS_SPI_ALL_INSTANCE_EXT(INSTANCE) (((INSTANCE) == SPI1) || \
+ ((INSTANCE) == SPI2) || \
+ ((INSTANCE) == SPI3) || \
+ ((INSTANCE) == I2S2ext) || \
+ ((INSTANCE) == I2S3ext))
+
+/****************** TIM Instances : All supported instances *******************/
+#define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM6) || \
+ ((INSTANCE) == TIM7) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM9) || \
+ ((INSTANCE) == TIM10) || \
+ ((INSTANCE) == TIM11) || \
+ ((INSTANCE) == TIM12) || \
+ ((INSTANCE) == TIM13) || \
+ ((INSTANCE) == TIM14))
+
+/************* TIM Instances : at least 1 capture/compare channel *************/
+#define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM9) || \
+ ((INSTANCE) == TIM10) || \
+ ((INSTANCE) == TIM11) || \
+ ((INSTANCE) == TIM12) || \
+ ((INSTANCE) == TIM13) || \
+ ((INSTANCE) == TIM14))
+
+/************ TIM Instances : at least 2 capture/compare channels *************/
+#define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM9) || \
+ ((INSTANCE) == TIM12))
+
+/************ TIM Instances : at least 3 capture/compare channels *************/
+#define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8))
+
+/************ TIM Instances : at least 4 capture/compare channels *************/
+#define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8))
+
+/******************** TIM Instances : Advanced-control timers *****************/
+#define IS_TIM_ADVANCED_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM8))
+
+/******************* TIM Instances : Timer input XOR function *****************/
+#define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8))
+
+/****************** TIM Instances : DMA requests generation (UDE) *************/
+#define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM6) || \
+ ((INSTANCE) == TIM7) || \
+ ((INSTANCE) == TIM8))
+
+/************ TIM Instances : DMA requests generation (CCxDE) *****************/
+#define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8))
+
+/************ TIM Instances : DMA requests generation (COMDE) *****************/
+#define IS_TIM_CCDMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8))
+
+/******************** TIM Instances : DMA burst feature ***********************/
+#define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8))
+
+/****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/
+#define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM6) || \
+ ((INSTANCE) == TIM7) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM9) || \
+ ((INSTANCE) == TIM12))
+
+/*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
+#define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM9) || \
+ ((INSTANCE) == TIM12))
+
+/********************** TIM Instances : 32 bit Counter ************************/
+#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)(((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM5))
+
+/***************** TIM Instances : external trigger input availabe ************/
+#define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8))
+
+/****************** TIM Instances : remapping capability **********************/
+#define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM11))
+
+/******************* TIM Instances : output(s) available **********************/
+#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
+ ((((INSTANCE) == TIM1) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM2) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM3) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM4) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM5) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM8) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM9) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2))) \
+ || \
+ (((INSTANCE) == TIM10) && \
+ (((CHANNEL) == TIM_CHANNEL_1))) \
+ || \
+ (((INSTANCE) == TIM11) && \
+ (((CHANNEL) == TIM_CHANNEL_1))) \
+ || \
+ (((INSTANCE) == TIM12) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2))) \
+ || \
+ (((INSTANCE) == TIM13) && \
+ (((CHANNEL) == TIM_CHANNEL_1))) \
+ || \
+ (((INSTANCE) == TIM14) && \
+ (((CHANNEL) == TIM_CHANNEL_1))))
+
+/************ TIM Instances : complementary output(s) available ***************/
+#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
+ ((((INSTANCE) == TIM1) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3))) \
+ || \
+ (((INSTANCE) == TIM8) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3))))
+
+/******************** USART Instances : Synchronous mode **********************/
+#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3) || \
+ ((INSTANCE) == USART6))
+
+/******************** UART Instances : Asynchronous mode **********************/
+#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3) || \
+ ((INSTANCE) == UART4) || \
+ ((INSTANCE) == UART5) || \
+ ((INSTANCE) == USART6))
+
+/****************** UART Instances : Hardware Flow control ********************/
+#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3) || \
+ ((INSTANCE) == USART6))
+
+/********************* UART Instances : Smard card mode ***********************/
+#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3) || \
+ ((INSTANCE) == USART6))
+
+/*********************** UART Instances : IRDA mode ***************************/
+#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3) || \
+ ((INSTANCE) == UART4) || \
+ ((INSTANCE) == UART5) || \
+ ((INSTANCE) == USART6))
+
+/*********************** PCD Instances ****************************************/
+/*********************** PCD Instances ****************************************/
+#define IS_PCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS) || \
+ ((INSTANCE) == USB_OTG_HS))
+
+/*********************** HCD Instances ****************************************/
+#define IS_HCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS) || \
+ ((INSTANCE) == USB_OTG_HS))
+
+/****************************** IWDG Instances ********************************/
+#define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
+
+/****************************** WWDG Instances ********************************/
+#define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
+
+/****************************** SDIO Instances ********************************/
+#define IS_SDIO_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SDIO)
+
+/****************************** USB Exported Constants ************************/
+#define USB_OTG_FS_HOST_MAX_CHANNEL_NBR 8U
+#define USB_OTG_FS_MAX_IN_ENDPOINTS 4U /* Including EP0 */
+#define USB_OTG_FS_MAX_OUT_ENDPOINTS 4U /* Including EP0 */
+#define USB_OTG_FS_TOTAL_FIFO_SIZE 1280U /* in Bytes */
+
+#define USB_OTG_HS_HOST_MAX_CHANNEL_NBR 12U
+#define USB_OTG_HS_MAX_IN_ENDPOINTS 6U /* Including EP0 */
+#define USB_OTG_HS_MAX_OUT_ENDPOINTS 6U /* Including EP0 */
+#define USB_OTG_HS_TOTAL_FIFO_SIZE 4096U /* in Bytes */
+
+/******************************************************************************/
+/* For a painless codes migration between the STM32F4xx device product */
+/* lines, the aliases defined below are put in place to overcome the */
+/* differences in the interrupt handlers and IRQn definitions. */
+/* No need to update developed interrupt code when moving across */
+/* product lines within the same STM32F4 Family */
+/******************************************************************************/
+
+/* Aliases for __IRQn */
+#define FMC_IRQn FSMC_IRQn
+
+/* Aliases for __IRQHandler */
+#define FMC_IRQHandler FSMC_IRQHandler
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* __STM32F405xx_H */
+
+
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Device/ST/STM32F4xx/Include/stm32f407xx.h b/Device/ST/STM32F4xx/Include/stm32f407xx.h
new file mode 100644
index 0000000..57dccd5
--- /dev/null
+++ b/Device/ST/STM32F4xx/Include/stm32f407xx.h
@@ -0,0 +1,8140 @@
+/**
+ ******************************************************************************
+ * @file stm32f407xx.h
+ * @author MCD Application Team
+ * @version V2.5.0
+ * @date 22-April-2016
+ * @brief CMSIS STM32F407xx Device Peripheral Access Layer Header File.
+ *
+ * This file contains:
+ * - Data structures and the address mapping for all peripherals
+ * - peripherals registers declarations and bits definition
+ * - Macros to access peripheral’s registers hardware
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/** @addtogroup CMSIS
+ * @{
+ */
+
+/** @addtogroup stm32f407xx
+ * @{
+ */
+
+#ifndef __STM32F407xx_H
+#define __STM32F407xx_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif /* __cplusplus */
+
+
+/** @addtogroup Configuration_section_for_CMSIS
+ * @{
+ */
+
+/**
+ * @brief Configuration of the Cortex-M4 Processor and Core Peripherals
+ */
+#define __CM4_REV 0x0001U /*!< Core revision r0p1 */
+#define __MPU_PRESENT 1U /*!< STM32F4XX provides an MPU */
+#define __NVIC_PRIO_BITS 4U /*!< STM32F4XX uses 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */
+#define __FPU_PRESENT 1U /*!< FPU present */
+
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_interrupt_number_definition
+ * @{
+ */
+
+/**
+ * @brief STM32F4XX Interrupt Number Definition, according to the selected device
+ * in @ref Library_configuration_section
+ */
+typedef enum
+{
+/****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/
+ NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
+ MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */
+ BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */
+ UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */
+ SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */
+ DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */
+ PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */
+ SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */
+/****** STM32 specific Interrupt Numbers **********************************************************************/
+ WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
+ PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */
+ TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */
+ RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */
+ FLASH_IRQn = 4, /*!< FLASH global Interrupt */
+ RCC_IRQn = 5, /*!< RCC global Interrupt */
+ EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */
+ EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */
+ EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */
+ EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */
+ EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */
+ DMA1_Stream0_IRQn = 11, /*!< DMA1 Stream 0 global Interrupt */
+ DMA1_Stream1_IRQn = 12, /*!< DMA1 Stream 1 global Interrupt */
+ DMA1_Stream2_IRQn = 13, /*!< DMA1 Stream 2 global Interrupt */
+ DMA1_Stream3_IRQn = 14, /*!< DMA1 Stream 3 global Interrupt */
+ DMA1_Stream4_IRQn = 15, /*!< DMA1 Stream 4 global Interrupt */
+ DMA1_Stream5_IRQn = 16, /*!< DMA1 Stream 5 global Interrupt */
+ DMA1_Stream6_IRQn = 17, /*!< DMA1 Stream 6 global Interrupt */
+ ADC_IRQn = 18, /*!< ADC1, ADC2 and ADC3 global Interrupts */
+ CAN1_TX_IRQn = 19, /*!< CAN1 TX Interrupt */
+ CAN1_RX0_IRQn = 20, /*!< CAN1 RX0 Interrupt */
+ CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */
+ CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */
+ EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
+ TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break interrupt and TIM9 global interrupt */
+ TIM1_UP_TIM10_IRQn = 25, /*!< TIM1 Update Interrupt and TIM10 global interrupt */
+ TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */
+ TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
+ TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
+ TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
+ TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
+ I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
+ I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
+ I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
+ I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
+ SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
+ SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
+ USART1_IRQn = 37, /*!< USART1 global Interrupt */
+ USART2_IRQn = 38, /*!< USART2 global Interrupt */
+ USART3_IRQn = 39, /*!< USART3 global Interrupt */
+ EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
+ RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */
+ OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS Wakeup through EXTI line interrupt */
+ TIM8_BRK_TIM12_IRQn = 43, /*!< TIM8 Break Interrupt and TIM12 global interrupt */
+ TIM8_UP_TIM13_IRQn = 44, /*!< TIM8 Update Interrupt and TIM13 global interrupt */
+ TIM8_TRG_COM_TIM14_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */
+ TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */
+ DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */
+ FSMC_IRQn = 48, /*!< FSMC global Interrupt */
+ SDIO_IRQn = 49, /*!< SDIO global Interrupt */
+ TIM5_IRQn = 50, /*!< TIM5 global Interrupt */
+ SPI3_IRQn = 51, /*!< SPI3 global Interrupt */
+ UART4_IRQn = 52, /*!< UART4 global Interrupt */
+ UART5_IRQn = 53, /*!< UART5 global Interrupt */
+ TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC1&2 underrun error interrupts */
+ TIM7_IRQn = 55, /*!< TIM7 global interrupt */
+ DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */
+ DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */
+ DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */
+ DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */
+ DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */
+ ETH_IRQn = 61, /*!< Ethernet global Interrupt */
+ ETH_WKUP_IRQn = 62, /*!< Ethernet Wakeup through EXTI line Interrupt */
+ CAN2_TX_IRQn = 63, /*!< CAN2 TX Interrupt */
+ CAN2_RX0_IRQn = 64, /*!< CAN2 RX0 Interrupt */
+ CAN2_RX1_IRQn = 65, /*!< CAN2 RX1 Interrupt */
+ CAN2_SCE_IRQn = 66, /*!< CAN2 SCE Interrupt */
+ OTG_FS_IRQn = 67, /*!< USB OTG FS global Interrupt */
+ DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */
+ DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */
+ DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */
+ USART6_IRQn = 71, /*!< USART6 global interrupt */
+ I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */
+ I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */
+ OTG_HS_EP1_OUT_IRQn = 74, /*!< USB OTG HS End Point 1 Out global interrupt */
+ OTG_HS_EP1_IN_IRQn = 75, /*!< USB OTG HS End Point 1 In global interrupt */
+ OTG_HS_WKUP_IRQn = 76, /*!< USB OTG HS Wakeup through EXTI interrupt */
+ OTG_HS_IRQn = 77, /*!< USB OTG HS global interrupt */
+ DCMI_IRQn = 78, /*!< DCMI global interrupt */
+ HASH_RNG_IRQn = 80, /*!< Hash and RNG global interrupt */
+ FPU_IRQn = 81 /*!< FPU global interrupt */
+} IRQn_Type;
+
+/**
+ * @}
+ */
+
+#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
+#include "system_stm32f4xx.h"
+#include <stdint.h>
+
+/** @addtogroup Peripheral_registers_structures
+ * @{
+ */
+
+/**
+ * @brief Analog to Digital Converter
+ */
+
+typedef struct
+{
+ __IO uint32_t SR; /*!< ADC status register, Address offset: 0x00 */
+ __IO uint32_t CR1; /*!< ADC control register 1, Address offset: 0x04 */
+ __IO uint32_t CR2; /*!< ADC control register 2, Address offset: 0x08 */
+ __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x0C */
+ __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x10 */
+ __IO uint32_t JOFR1; /*!< ADC injected channel data offset register 1, Address offset: 0x14 */
+ __IO uint32_t JOFR2; /*!< ADC injected channel data offset register 2, Address offset: 0x18 */
+ __IO uint32_t JOFR3; /*!< ADC injected channel data offset register 3, Address offset: 0x1C */
+ __IO uint32_t JOFR4; /*!< ADC injected channel data offset register 4, Address offset: 0x20 */
+ __IO uint32_t HTR; /*!< ADC watchdog higher threshold register, Address offset: 0x24 */
+ __IO uint32_t LTR; /*!< ADC watchdog lower threshold register, Address offset: 0x28 */
+ __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x2C */
+ __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x30 */
+ __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x34 */
+ __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x38*/
+ __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x3C */
+ __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x40 */
+ __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x44 */
+ __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x48 */
+ __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x4C */
+} ADC_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1 base address + 0x300 */
+ __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1 base address + 0x304 */
+ __IO uint32_t CDR; /*!< ADC common regular data register for dual
+ AND triple modes, Address offset: ADC1 base address + 0x308 */
+} ADC_Common_TypeDef;
+
+
+/**
+ * @brief Controller Area Network TxMailBox
+ */
+
+typedef struct
+{
+ __IO uint32_t TIR; /*!< CAN TX mailbox identifier register */
+ __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */
+ __IO uint32_t TDLR; /*!< CAN mailbox data low register */
+ __IO uint32_t TDHR; /*!< CAN mailbox data high register */
+} CAN_TxMailBox_TypeDef;
+
+/**
+ * @brief Controller Area Network FIFOMailBox
+ */
+
+typedef struct
+{
+ __IO uint32_t RIR; /*!< CAN receive FIFO mailbox identifier register */
+ __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */
+ __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */
+ __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */
+} CAN_FIFOMailBox_TypeDef;
+
+/**
+ * @brief Controller Area Network FilterRegister
+ */
+
+typedef struct
+{
+ __IO uint32_t FR1; /*!< CAN Filter bank register 1 */
+ __IO uint32_t FR2; /*!< CAN Filter bank register 1 */
+} CAN_FilterRegister_TypeDef;
+
+/**
+ * @brief Controller Area Network
+ */
+
+typedef struct
+{
+ __IO uint32_t MCR; /*!< CAN master control register, Address offset: 0x00 */
+ __IO uint32_t MSR; /*!< CAN master status register, Address offset: 0x04 */
+ __IO uint32_t TSR; /*!< CAN transmit status register, Address offset: 0x08 */
+ __IO uint32_t RF0R; /*!< CAN receive FIFO 0 register, Address offset: 0x0C */
+ __IO uint32_t RF1R; /*!< CAN receive FIFO 1 register, Address offset: 0x10 */
+ __IO uint32_t IER; /*!< CAN interrupt enable register, Address offset: 0x14 */
+ __IO uint32_t ESR; /*!< CAN error status register, Address offset: 0x18 */
+ __IO uint32_t BTR; /*!< CAN bit timing register, Address offset: 0x1C */
+ uint32_t RESERVED0[88]; /*!< Reserved, 0x020 - 0x17F */
+ CAN_TxMailBox_TypeDef sTxMailBox[3]; /*!< CAN Tx MailBox, Address offset: 0x180 - 0x1AC */
+ CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; /*!< CAN FIFO MailBox, Address offset: 0x1B0 - 0x1CC */
+ uint32_t RESERVED1[12]; /*!< Reserved, 0x1D0 - 0x1FF */
+ __IO uint32_t FMR; /*!< CAN filter master register, Address offset: 0x200 */
+ __IO uint32_t FM1R; /*!< CAN filter mode register, Address offset: 0x204 */
+ uint32_t RESERVED2; /*!< Reserved, 0x208 */
+ __IO uint32_t FS1R; /*!< CAN filter scale register, Address offset: 0x20C */
+ uint32_t RESERVED3; /*!< Reserved, 0x210 */
+ __IO uint32_t FFA1R; /*!< CAN filter FIFO assignment register, Address offset: 0x214 */
+ uint32_t RESERVED4; /*!< Reserved, 0x218 */
+ __IO uint32_t FA1R; /*!< CAN filter activation register, Address offset: 0x21C */
+ uint32_t RESERVED5[8]; /*!< Reserved, 0x220-0x23F */
+ CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register, Address offset: 0x240-0x31C */
+} CAN_TypeDef;
+
+/**
+ * @brief CRC calculation unit
+ */
+
+typedef struct
+{
+ __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
+ __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
+ uint8_t RESERVED0; /*!< Reserved, 0x05 */
+ uint16_t RESERVED1; /*!< Reserved, 0x06 */
+ __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
+} CRC_TypeDef;
+
+/**
+ * @brief Digital to Analog Converter
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */
+ __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */
+ __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
+ __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */
+ __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */
+ __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
+ __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */
+ __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */
+ __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */
+ __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */
+ __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */
+ __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */
+ __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */
+ __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */
+} DAC_TypeDef;
+
+/**
+ * @brief Debug MCU
+ */
+
+typedef struct
+{
+ __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
+ __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
+ __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */
+ __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */
+}DBGMCU_TypeDef;
+
+/**
+ * @brief DCMI
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< DCMI control register 1, Address offset: 0x00 */
+ __IO uint32_t SR; /*!< DCMI status register, Address offset: 0x04 */
+ __IO uint32_t RISR; /*!< DCMI raw interrupt status register, Address offset: 0x08 */
+ __IO uint32_t IER; /*!< DCMI interrupt enable register, Address offset: 0x0C */
+ __IO uint32_t MISR; /*!< DCMI masked interrupt status register, Address offset: 0x10 */
+ __IO uint32_t ICR; /*!< DCMI interrupt clear register, Address offset: 0x14 */
+ __IO uint32_t ESCR; /*!< DCMI embedded synchronization code register, Address offset: 0x18 */
+ __IO uint32_t ESUR; /*!< DCMI embedded synchronization unmask register, Address offset: 0x1C */
+ __IO uint32_t CWSTRTR; /*!< DCMI crop window start, Address offset: 0x20 */
+ __IO uint32_t CWSIZER; /*!< DCMI crop window size, Address offset: 0x24 */
+ __IO uint32_t DR; /*!< DCMI data register, Address offset: 0x28 */
+} DCMI_TypeDef;
+
+/**
+ * @brief DMA Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< DMA stream x configuration register */
+ __IO uint32_t NDTR; /*!< DMA stream x number of data register */
+ __IO uint32_t PAR; /*!< DMA stream x peripheral address register */
+ __IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */
+ __IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */
+ __IO uint32_t FCR; /*!< DMA stream x FIFO control register */
+} DMA_Stream_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t LISR; /*!< DMA low interrupt status register, Address offset: 0x00 */
+ __IO uint32_t HISR; /*!< DMA high interrupt status register, Address offset: 0x04 */
+ __IO uint32_t LIFCR; /*!< DMA low interrupt flag clear register, Address offset: 0x08 */
+ __IO uint32_t HIFCR; /*!< DMA high interrupt flag clear register, Address offset: 0x0C */
+} DMA_TypeDef;
+
+
+/**
+ * @brief Ethernet MAC
+ */
+
+typedef struct
+{
+ __IO uint32_t MACCR;
+ __IO uint32_t MACFFR;
+ __IO uint32_t MACHTHR;
+ __IO uint32_t MACHTLR;
+ __IO uint32_t MACMIIAR;
+ __IO uint32_t MACMIIDR;
+ __IO uint32_t MACFCR;
+ __IO uint32_t MACVLANTR; /* 8 */
+ uint32_t RESERVED0[2];
+ __IO uint32_t MACRWUFFR; /* 11 */
+ __IO uint32_t MACPMTCSR;
+ uint32_t RESERVED1[2];
+ __IO uint32_t MACSR; /* 15 */
+ __IO uint32_t MACIMR;
+ __IO uint32_t MACA0HR;
+ __IO uint32_t MACA0LR;
+ __IO uint32_t MACA1HR;
+ __IO uint32_t MACA1LR;
+ __IO uint32_t MACA2HR;
+ __IO uint32_t MACA2LR;
+ __IO uint32_t MACA3HR;
+ __IO uint32_t MACA3LR; /* 24 */
+ uint32_t RESERVED2[40];
+ __IO uint32_t MMCCR; /* 65 */
+ __IO uint32_t MMCRIR;
+ __IO uint32_t MMCTIR;
+ __IO uint32_t MMCRIMR;
+ __IO uint32_t MMCTIMR; /* 69 */
+ uint32_t RESERVED3[14];
+ __IO uint32_t MMCTGFSCCR; /* 84 */
+ __IO uint32_t MMCTGFMSCCR;
+ uint32_t RESERVED4[5];
+ __IO uint32_t MMCTGFCR;
+ uint32_t RESERVED5[10];
+ __IO uint32_t MMCRFCECR;
+ __IO uint32_t MMCRFAECR;
+ uint32_t RESERVED6[10];
+ __IO uint32_t MMCRGUFCR;
+ uint32_t RESERVED7[334];
+ __IO uint32_t PTPTSCR;
+ __IO uint32_t PTPSSIR;
+ __IO uint32_t PTPTSHR;
+ __IO uint32_t PTPTSLR;
+ __IO uint32_t PTPTSHUR;
+ __IO uint32_t PTPTSLUR;
+ __IO uint32_t PTPTSAR;
+ __IO uint32_t PTPTTHR;
+ __IO uint32_t PTPTTLR;
+ __IO uint32_t RESERVED8;
+ __IO uint32_t PTPTSSR;
+ uint32_t RESERVED9[565];
+ __IO uint32_t DMABMR;
+ __IO uint32_t DMATPDR;
+ __IO uint32_t DMARPDR;
+ __IO uint32_t DMARDLAR;
+ __IO uint32_t DMATDLAR;
+ __IO uint32_t DMASR;
+ __IO uint32_t DMAOMR;
+ __IO uint32_t DMAIER;
+ __IO uint32_t DMAMFBOCR;
+ __IO uint32_t DMARSWTR;
+ uint32_t RESERVED10[8];
+ __IO uint32_t DMACHTDR;
+ __IO uint32_t DMACHRDR;
+ __IO uint32_t DMACHTBAR;
+ __IO uint32_t DMACHRBAR;
+} ETH_TypeDef;
+
+/**
+ * @brief External Interrupt/Event Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t IMR; /*!< EXTI Interrupt mask register, Address offset: 0x00 */
+ __IO uint32_t EMR; /*!< EXTI Event mask register, Address offset: 0x04 */
+ __IO uint32_t RTSR; /*!< EXTI Rising trigger selection register, Address offset: 0x08 */
+ __IO uint32_t FTSR; /*!< EXTI Falling trigger selection register, Address offset: 0x0C */
+ __IO uint32_t SWIER; /*!< EXTI Software interrupt event register, Address offset: 0x10 */
+ __IO uint32_t PR; /*!< EXTI Pending register, Address offset: 0x14 */
+} EXTI_TypeDef;
+
+/**
+ * @brief FLASH Registers
+ */
+
+typedef struct
+{
+ __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */
+ __IO uint32_t KEYR; /*!< FLASH key register, Address offset: 0x04 */
+ __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x08 */
+ __IO uint32_t SR; /*!< FLASH status register, Address offset: 0x0C */
+ __IO uint32_t CR; /*!< FLASH control register, Address offset: 0x10 */
+ __IO uint32_t OPTCR; /*!< FLASH option control register , Address offset: 0x14 */
+ __IO uint32_t OPTCR1; /*!< FLASH option control register 1, Address offset: 0x18 */
+} FLASH_TypeDef;
+
+
+/**
+ * @brief Flexible Static Memory Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */
+} FSMC_Bank1_TypeDef;
+
+/**
+ * @brief Flexible Static Memory Controller Bank1E
+ */
+
+typedef struct
+{
+ __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */
+} FSMC_Bank1E_TypeDef;
+
+/**
+ * @brief Flexible Static Memory Controller Bank2
+ */
+
+typedef struct
+{
+ __IO uint32_t PCR2; /*!< NAND Flash control register 2, Address offset: 0x60 */
+ __IO uint32_t SR2; /*!< NAND Flash FIFO status and interrupt register 2, Address offset: 0x64 */
+ __IO uint32_t PMEM2; /*!< NAND Flash Common memory space timing register 2, Address offset: 0x68 */
+ __IO uint32_t PATT2; /*!< NAND Flash Attribute memory space timing register 2, Address offset: 0x6C */
+ uint32_t RESERVED0; /*!< Reserved, 0x70 */
+ __IO uint32_t ECCR2; /*!< NAND Flash ECC result registers 2, Address offset: 0x74 */
+ uint32_t RESERVED1; /*!< Reserved, 0x78 */
+ uint32_t RESERVED2; /*!< Reserved, 0x7C */
+ __IO uint32_t PCR3; /*!< NAND Flash control register 3, Address offset: 0x80 */
+ __IO uint32_t SR3; /*!< NAND Flash FIFO status and interrupt register 3, Address offset: 0x84 */
+ __IO uint32_t PMEM3; /*!< NAND Flash Common memory space timing register 3, Address offset: 0x88 */
+ __IO uint32_t PATT3; /*!< NAND Flash Attribute memory space timing register 3, Address offset: 0x8C */
+ uint32_t RESERVED3; /*!< Reserved, 0x90 */
+ __IO uint32_t ECCR3; /*!< NAND Flash ECC result registers 3, Address offset: 0x94 */
+} FSMC_Bank2_3_TypeDef;
+
+/**
+ * @brief Flexible Static Memory Controller Bank4
+ */
+
+typedef struct
+{
+ __IO uint32_t PCR4; /*!< PC Card control register 4, Address offset: 0xA0 */
+ __IO uint32_t SR4; /*!< PC Card FIFO status and interrupt register 4, Address offset: 0xA4 */
+ __IO uint32_t PMEM4; /*!< PC Card Common memory space timing register 4, Address offset: 0xA8 */
+ __IO uint32_t PATT4; /*!< PC Card Attribute memory space timing register 4, Address offset: 0xAC */
+ __IO uint32_t PIO4; /*!< PC Card I/O space timing register 4, Address offset: 0xB0 */
+} FSMC_Bank4_TypeDef;
+
+
+/**
+ * @brief General Purpose I/O
+ */
+
+typedef struct
+{
+ __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
+ __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */
+ __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */
+ __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
+ __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
+ __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
+ __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */
+ __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
+ __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */
+} GPIO_TypeDef;
+
+/**
+ * @brief System configuration controller
+ */
+
+typedef struct
+{
+ __IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */
+ __IO uint32_t PMC; /*!< SYSCFG peripheral mode configuration register, Address offset: 0x04 */
+ __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
+ uint32_t RESERVED[2]; /*!< Reserved, 0x18-0x1C */
+ __IO uint32_t CMPCR; /*!< SYSCFG Compensation cell control register, Address offset: 0x20 */
+} SYSCFG_TypeDef;
+
+/**
+ * @brief Inter-integrated Circuit Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */
+ __IO uint32_t OAR1; /*!< I2C Own address register 1, Address offset: 0x08 */
+ __IO uint32_t OAR2; /*!< I2C Own address register 2, Address offset: 0x0C */
+ __IO uint32_t DR; /*!< I2C Data register, Address offset: 0x10 */
+ __IO uint32_t SR1; /*!< I2C Status register 1, Address offset: 0x14 */
+ __IO uint32_t SR2; /*!< I2C Status register 2, Address offset: 0x18 */
+ __IO uint32_t CCR; /*!< I2C Clock control register, Address offset: 0x1C */
+ __IO uint32_t TRISE; /*!< I2C TRISE register, Address offset: 0x20 */
+ __IO uint32_t FLTR; /*!< I2C FLTR register, Address offset: 0x24 */
+} I2C_TypeDef;
+
+/**
+ * @brief Independent WATCHDOG
+ */
+
+typedef struct
+{
+ __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */
+ __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */
+ __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */
+ __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */
+} IWDG_TypeDef;
+
+/**
+ * @brief Power Control
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */
+ __IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */
+} PWR_TypeDef;
+
+/**
+ * @brief Reset and Clock Control
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */
+ __IO uint32_t PLLCFGR; /*!< RCC PLL configuration register, Address offset: 0x04 */
+ __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x08 */
+ __IO uint32_t CIR; /*!< RCC clock interrupt register, Address offset: 0x0C */
+ __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x10 */
+ __IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x14 */
+ __IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0x18 */
+ uint32_t RESERVED0; /*!< Reserved, 0x1C */
+ __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x20 */
+ __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x24 */
+ uint32_t RESERVED1[2]; /*!< Reserved, 0x28-0x2C */
+ __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clock register, Address offset: 0x30 */
+ __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clock register, Address offset: 0x34 */
+ __IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clock register, Address offset: 0x38 */
+ uint32_t RESERVED2; /*!< Reserved, 0x3C */
+ __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x40 */
+ __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x44 */
+ uint32_t RESERVED3[2]; /*!< Reserved, 0x48-0x4C */
+ __IO uint32_t AHB1LPENR; /*!< RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 */
+ __IO uint32_t AHB2LPENR; /*!< RCC AHB2 peripheral clock enable in low power mode register, Address offset: 0x54 */
+ __IO uint32_t AHB3LPENR; /*!< RCC AHB3 peripheral clock enable in low power mode register, Address offset: 0x58 */
+ uint32_t RESERVED4; /*!< Reserved, 0x5C */
+ __IO uint32_t APB1LPENR; /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 */
+ __IO uint32_t APB2LPENR; /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 */
+ uint32_t RESERVED5[2]; /*!< Reserved, 0x68-0x6C */
+ __IO uint32_t BDCR; /*!< RCC Backup domain control register, Address offset: 0x70 */
+ __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x74 */
+ uint32_t RESERVED6[2]; /*!< Reserved, 0x78-0x7C */
+ __IO uint32_t SSCGR; /*!< RCC spread spectrum clock generation register, Address offset: 0x80 */
+ __IO uint32_t PLLI2SCFGR; /*!< RCC PLLI2S configuration register, Address offset: 0x84 */
+
+} RCC_TypeDef;
+
+/**
+ * @brief Real-Time Clock
+ */
+
+typedef struct
+{
+ __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
+ __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */
+ __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */
+ __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */
+ __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */
+ __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */
+ __IO uint32_t CALIBR; /*!< RTC calibration register, Address offset: 0x18 */
+ __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */
+ __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */
+ __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */
+ __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */
+ __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */
+ __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */
+ __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */
+ __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */
+ __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */
+ __IO uint32_t TAFCR; /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */
+ __IO uint32_t ALRMASSR;/*!< RTC alarm A sub second register, Address offset: 0x44 */
+ __IO uint32_t ALRMBSSR;/*!< RTC alarm B sub second register, Address offset: 0x48 */
+ uint32_t RESERVED7; /*!< Reserved, 0x4C */
+ __IO uint32_t BKP0R; /*!< RTC backup register 1, Address offset: 0x50 */
+ __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */
+ __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */
+ __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */
+ __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */
+ __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */
+ __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */
+ __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */
+ __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */
+ __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */
+ __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */
+ __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */
+ __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */
+ __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */
+ __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */
+ __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */
+ __IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */
+ __IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */
+ __IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */
+ __IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */
+} RTC_TypeDef;
+
+
+/**
+ * @brief SD host Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t POWER; /*!< SDIO power control register, Address offset: 0x00 */
+ __IO uint32_t CLKCR; /*!< SDI clock control register, Address offset: 0x04 */
+ __IO uint32_t ARG; /*!< SDIO argument register, Address offset: 0x08 */
+ __IO uint32_t CMD; /*!< SDIO command register, Address offset: 0x0C */
+ __I uint32_t RESPCMD; /*!< SDIO command response register, Address offset: 0x10 */
+ __I uint32_t RESP1; /*!< SDIO response 1 register, Address offset: 0x14 */
+ __I uint32_t RESP2; /*!< SDIO response 2 register, Address offset: 0x18 */
+ __I uint32_t RESP3; /*!< SDIO response 3 register, Address offset: 0x1C */
+ __I uint32_t RESP4; /*!< SDIO response 4 register, Address offset: 0x20 */
+ __IO uint32_t DTIMER; /*!< SDIO data timer register, Address offset: 0x24 */
+ __IO uint32_t DLEN; /*!< SDIO data length register, Address offset: 0x28 */
+ __IO uint32_t DCTRL; /*!< SDIO data control register, Address offset: 0x2C */
+ __I uint32_t DCOUNT; /*!< SDIO data counter register, Address offset: 0x30 */
+ __I uint32_t STA; /*!< SDIO status register, Address offset: 0x34 */
+ __IO uint32_t ICR; /*!< SDIO interrupt clear register, Address offset: 0x38 */
+ __IO uint32_t MASK; /*!< SDIO mask register, Address offset: 0x3C */
+ uint32_t RESERVED0[2]; /*!< Reserved, 0x40-0x44 */
+ __I uint32_t FIFOCNT; /*!< SDIO FIFO counter register, Address offset: 0x48 */
+ uint32_t RESERVED1[13]; /*!< Reserved, 0x4C-0x7C */
+ __IO uint32_t FIFO; /*!< SDIO data FIFO register, Address offset: 0x80 */
+} SDIO_TypeDef;
+
+/**
+ * @brief Serial Peripheral Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t CR1; /*!< SPI control register 1 (not used in I2S mode), Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< SPI control register 2, Address offset: 0x04 */
+ __IO uint32_t SR; /*!< SPI status register, Address offset: 0x08 */
+ __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */
+ __IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
+ __IO uint32_t RXCRCR; /*!< SPI RX CRC register (not used in I2S mode), Address offset: 0x14 */
+ __IO uint32_t TXCRCR; /*!< SPI TX CRC register (not used in I2S mode), Address offset: 0x18 */
+ __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */
+ __IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */
+} SPI_TypeDef;
+
+/**
+ * @brief TIM
+ */
+
+typedef struct
+{
+ __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
+ __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */
+ __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
+ __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
+ __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
+ __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
+ __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
+ __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
+ __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
+ __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */
+ __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
+ __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */
+ __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
+ __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
+ __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
+ __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
+ __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
+ __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
+ __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */
+ __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */
+} TIM_TypeDef;
+
+/**
+ * @brief Universal Synchronous Asynchronous Receiver Transmitter
+ */
+
+typedef struct
+{
+ __IO uint32_t SR; /*!< USART Status register, Address offset: 0x00 */
+ __IO uint32_t DR; /*!< USART Data register, Address offset: 0x04 */
+ __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x08 */
+ __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x0C */
+ __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x10 */
+ __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x14 */
+ __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x18 */
+} USART_TypeDef;
+
+/**
+ * @brief Window WATCHDOG
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
+ __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
+ __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
+} WWDG_TypeDef;
+
+/**
+ * @brief RNG
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */
+ __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */
+ __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */
+} RNG_TypeDef;
+
+
+
+/**
+ * @brief __USB_OTG_Core_register
+ */
+typedef struct
+{
+ __IO uint32_t GOTGCTL; /*!< USB_OTG Control and Status Register 000h*/
+ __IO uint32_t GOTGINT; /*!< USB_OTG Interrupt Register 004h*/
+ __IO uint32_t GAHBCFG; /*!< Core AHB Configuration Register 008h*/
+ __IO uint32_t GUSBCFG; /*!< Core USB Configuration Register 00Ch*/
+ __IO uint32_t GRSTCTL; /*!< Core Reset Register 010h*/
+ __IO uint32_t GINTSTS; /*!< Core Interrupt Register 014h*/
+ __IO uint32_t GINTMSK; /*!< Core Interrupt Mask Register 018h*/
+ __IO uint32_t GRXSTSR; /*!< Receive Sts Q Read Register 01Ch*/
+ __IO uint32_t GRXSTSP; /*!< Receive Sts Q Read & POP Register 020h*/
+ __IO uint32_t GRXFSIZ; /* Receive FIFO Size Register 024h*/
+ __IO uint32_t DIEPTXF0_HNPTXFSIZ; /*!< EP0 / Non Periodic Tx FIFO Size Register 028h*/
+ __IO uint32_t HNPTXSTS; /*!< Non Periodic Tx FIFO/Queue Sts reg 02Ch*/
+ uint32_t Reserved30[2]; /* Reserved 030h*/
+ __IO uint32_t GCCFG; /* General Purpose IO Register 038h*/
+ __IO uint32_t CID; /* User ID Register 03Ch*/
+ uint32_t Reserved40[48]; /* Reserved 040h-0FFh*/
+ __IO uint32_t HPTXFSIZ; /* Host Periodic Tx FIFO Size Reg 100h*/
+ __IO uint32_t DIEPTXF[0x0F];/* dev Periodic Transmit FIFO */
+}
+USB_OTG_GlobalTypeDef;
+
+
+
+/**
+ * @brief __device_Registers
+ */
+typedef struct
+{
+ __IO uint32_t DCFG; /* dev Configuration Register 800h*/
+ __IO uint32_t DCTL; /* dev Control Register 804h*/
+ __IO uint32_t DSTS; /* dev Status Register (RO) 808h*/
+ uint32_t Reserved0C; /* Reserved 80Ch*/
+ __IO uint32_t DIEPMSK; /* dev IN Endpoint Mask 810h*/
+ __IO uint32_t DOEPMSK; /* dev OUT Endpoint Mask 814h*/
+ __IO uint32_t DAINT; /* dev All Endpoints Itr Reg 818h*/
+ __IO uint32_t DAINTMSK; /* dev All Endpoints Itr Mask 81Ch*/
+ uint32_t Reserved20; /* Reserved 820h*/
+ uint32_t Reserved9; /* Reserved 824h*/
+ __IO uint32_t DVBUSDIS; /* dev VBUS discharge Register 828h*/
+ __IO uint32_t DVBUSPULSE; /* dev VBUS Pulse Register 82Ch*/
+ __IO uint32_t DTHRCTL; /* dev thr 830h*/
+ __IO uint32_t DIEPEMPMSK; /* dev empty msk 834h*/
+ __IO uint32_t DEACHINT; /* dedicated EP interrupt 838h*/
+ __IO uint32_t DEACHMSK; /* dedicated EP msk 83Ch*/
+ uint32_t Reserved40; /* dedicated EP mask 840h*/
+ __IO uint32_t DINEP1MSK; /* dedicated EP mask 844h*/
+ uint32_t Reserved44[15]; /* Reserved 844-87Ch*/
+ __IO uint32_t DOUTEP1MSK; /* dedicated EP msk 884h*/
+}
+USB_OTG_DeviceTypeDef;
+
+
+/**
+ * @brief __IN_Endpoint-Specific_Register
+ */
+typedef struct
+{
+ __IO uint32_t DIEPCTL; /* dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h*/
+ uint32_t Reserved04; /* Reserved 900h + (ep_num * 20h) + 04h*/
+ __IO uint32_t DIEPINT; /* dev IN Endpoint Itr Reg 900h + (ep_num * 20h) + 08h*/
+ uint32_t Reserved0C; /* Reserved 900h + (ep_num * 20h) + 0Ch*/
+ __IO uint32_t DIEPTSIZ; /* IN Endpoint Txfer Size 900h + (ep_num * 20h) + 10h*/
+ __IO uint32_t DIEPDMA; /* IN Endpoint DMA Address Reg 900h + (ep_num * 20h) + 14h*/
+ __IO uint32_t DTXFSTS;/*IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h*/
+ uint32_t Reserved18; /* Reserved 900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch*/
+}
+USB_OTG_INEndpointTypeDef;
+
+
+/**
+ * @brief __OUT_Endpoint-Specific_Registers
+ */
+typedef struct
+{
+ __IO uint32_t DOEPCTL; /* dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h*/
+ uint32_t Reserved04; /* Reserved B00h + (ep_num * 20h) + 04h*/
+ __IO uint32_t DOEPINT; /* dev OUT Endpoint Itr Reg B00h + (ep_num * 20h) + 08h*/
+ uint32_t Reserved0C; /* Reserved B00h + (ep_num * 20h) + 0Ch*/
+ __IO uint32_t DOEPTSIZ; /* dev OUT Endpoint Txfer Size B00h + (ep_num * 20h) + 10h*/
+ __IO uint32_t DOEPDMA; /* dev OUT Endpoint DMA Address B00h + (ep_num * 20h) + 14h*/
+ uint32_t Reserved18[2]; /* Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch*/
+}
+USB_OTG_OUTEndpointTypeDef;
+
+
+/**
+ * @brief __Host_Mode_Register_Structures
+ */
+typedef struct
+{
+ __IO uint32_t HCFG; /* Host Configuration Register 400h*/
+ __IO uint32_t HFIR; /* Host Frame Interval Register 404h*/
+ __IO uint32_t HFNUM; /* Host Frame Nbr/Frame Remaining 408h*/
+ uint32_t Reserved40C; /* Reserved 40Ch*/
+ __IO uint32_t HPTXSTS; /* Host Periodic Tx FIFO/ Queue Status 410h*/
+ __IO uint32_t HAINT; /* Host All Channels Interrupt Register 414h*/
+ __IO uint32_t HAINTMSK; /* Host All Channels Interrupt Mask 418h*/
+}
+USB_OTG_HostTypeDef;
+
+
+/**
+ * @brief __Host_Channel_Specific_Registers
+ */
+typedef struct
+{
+ __IO uint32_t HCCHAR;
+ __IO uint32_t HCSPLT;
+ __IO uint32_t HCINT;
+ __IO uint32_t HCINTMSK;
+ __IO uint32_t HCTSIZ;
+ __IO uint32_t HCDMA;
+ uint32_t Reserved[2];
+}
+USB_OTG_HostChannelTypeDef;
+
+
+/**
+ * @brief Peripheral_memory_map
+ */
+#define FLASH_BASE 0x08000000U /*!< FLASH(up to 1 MB) base address in the alias region */
+#define CCMDATARAM_BASE 0x10000000U /*!< CCM(core coupled memory) data RAM(64 KB) base address in the alias region */
+#define SRAM1_BASE 0x20000000U /*!< SRAM1(112 KB) base address in the alias region */
+#define SRAM2_BASE 0x2001C000U /*!< SRAM2(16 KB) base address in the alias region */
+#define PERIPH_BASE 0x40000000U /*!< Peripheral base address in the alias region */
+#define BKPSRAM_BASE 0x40024000U /*!< Backup SRAM(4 KB) base address in the alias region */
+#define FSMC_R_BASE 0xA0000000U /*!< FSMC registers base address */
+#define SRAM1_BB_BASE 0x22000000U /*!< SRAM1(112 KB) base address in the bit-band region */
+#define SRAM2_BB_BASE 0x22380000U /*!< SRAM2(16 KB) base address in the bit-band region */
+#define PERIPH_BB_BASE 0x42000000U /*!< Peripheral base address in the bit-band region */
+#define BKPSRAM_BB_BASE 0x42480000U /*!< Backup SRAM(4 KB) base address in the bit-band region */
+#define FLASH_END 0x080FFFFFU /*!< FLASH end address */
+#define CCMDATARAM_END 0x1000FFFFU /*!< CCM data RAM end address */
+
+/* Legacy defines */
+#define SRAM_BASE SRAM1_BASE
+#define SRAM_BB_BASE SRAM1_BB_BASE
+
+
+/*!< Peripheral memory map */
+#define APB1PERIPH_BASE PERIPH_BASE
+#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000U)
+#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000U)
+#define AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000U)
+
+/*!< APB1 peripherals */
+#define TIM2_BASE (APB1PERIPH_BASE + 0x0000U)
+#define TIM3_BASE (APB1PERIPH_BASE + 0x0400U)
+#define TIM4_BASE (APB1PERIPH_BASE + 0x0800U)
+#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00U)
+#define TIM6_BASE (APB1PERIPH_BASE + 0x1000U)
+#define TIM7_BASE (APB1PERIPH_BASE + 0x1400U)
+#define TIM12_BASE (APB1PERIPH_BASE + 0x1800U)
+#define TIM13_BASE (APB1PERIPH_BASE + 0x1C00U)
+#define TIM14_BASE (APB1PERIPH_BASE + 0x2000U)
+#define RTC_BASE (APB1PERIPH_BASE + 0x2800U)
+#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00U)
+#define IWDG_BASE (APB1PERIPH_BASE + 0x3000U)
+#define I2S2ext_BASE (APB1PERIPH_BASE + 0x3400U)
+#define SPI2_BASE (APB1PERIPH_BASE + 0x3800U)
+#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00U)
+#define I2S3ext_BASE (APB1PERIPH_BASE + 0x4000U)
+#define USART2_BASE (APB1PERIPH_BASE + 0x4400U)
+#define USART3_BASE (APB1PERIPH_BASE + 0x4800U)
+#define UART4_BASE (APB1PERIPH_BASE + 0x4C00U)
+#define UART5_BASE (APB1PERIPH_BASE + 0x5000U)
+#define I2C1_BASE (APB1PERIPH_BASE + 0x5400U)
+#define I2C2_BASE (APB1PERIPH_BASE + 0x5800U)
+#define I2C3_BASE (APB1PERIPH_BASE + 0x5C00U)
+#define CAN1_BASE (APB1PERIPH_BASE + 0x6400U)
+#define CAN2_BASE (APB1PERIPH_BASE + 0x6800U)
+#define PWR_BASE (APB1PERIPH_BASE + 0x7000U)
+#define DAC_BASE (APB1PERIPH_BASE + 0x7400U)
+
+/*!< APB2 peripherals */
+#define TIM1_BASE (APB2PERIPH_BASE + 0x0000U)
+#define TIM8_BASE (APB2PERIPH_BASE + 0x0400U)
+#define USART1_BASE (APB2PERIPH_BASE + 0x1000U)
+#define USART6_BASE (APB2PERIPH_BASE + 0x1400U)
+#define ADC1_BASE (APB2PERIPH_BASE + 0x2000U)
+#define ADC2_BASE (APB2PERIPH_BASE + 0x2100U)
+#define ADC3_BASE (APB2PERIPH_BASE + 0x2200U)
+#define ADC_BASE (APB2PERIPH_BASE + 0x2300U)
+#define SDIO_BASE (APB2PERIPH_BASE + 0x2C00U)
+#define SPI1_BASE (APB2PERIPH_BASE + 0x3000U)
+#define SYSCFG_BASE (APB2PERIPH_BASE + 0x3800U)
+#define EXTI_BASE (APB2PERIPH_BASE + 0x3C00U)
+#define TIM9_BASE (APB2PERIPH_BASE + 0x4000U)
+#define TIM10_BASE (APB2PERIPH_BASE + 0x4400U)
+#define TIM11_BASE (APB2PERIPH_BASE + 0x4800U)
+
+/*!< AHB1 peripherals */
+#define GPIOA_BASE (AHB1PERIPH_BASE + 0x0000U)
+#define GPIOB_BASE (AHB1PERIPH_BASE + 0x0400U)
+#define GPIOC_BASE (AHB1PERIPH_BASE + 0x0800U)
+#define GPIOD_BASE (AHB1PERIPH_BASE + 0x0C00U)
+#define GPIOE_BASE (AHB1PERIPH_BASE + 0x1000U)
+#define GPIOF_BASE (AHB1PERIPH_BASE + 0x1400U)
+#define GPIOG_BASE (AHB1PERIPH_BASE + 0x1800U)
+#define GPIOH_BASE (AHB1PERIPH_BASE + 0x1C00U)
+#define GPIOI_BASE (AHB1PERIPH_BASE + 0x2000U)
+#define CRC_BASE (AHB1PERIPH_BASE + 0x3000U)
+#define RCC_BASE (AHB1PERIPH_BASE + 0x3800U)
+#define FLASH_R_BASE (AHB1PERIPH_BASE + 0x3C00U)
+#define DMA1_BASE (AHB1PERIPH_BASE + 0x6000U)
+#define DMA1_Stream0_BASE (DMA1_BASE + 0x010U)
+#define DMA1_Stream1_BASE (DMA1_BASE + 0x028U)
+#define DMA1_Stream2_BASE (DMA1_BASE + 0x040U)
+#define DMA1_Stream3_BASE (DMA1_BASE + 0x058U)
+#define DMA1_Stream4_BASE (DMA1_BASE + 0x070U)
+#define DMA1_Stream5_BASE (DMA1_BASE + 0x088U)
+#define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0U)
+#define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8U)
+#define DMA2_BASE (AHB1PERIPH_BASE + 0x6400U)
+#define DMA2_Stream0_BASE (DMA2_BASE + 0x010U)
+#define DMA2_Stream1_BASE (DMA2_BASE + 0x028U)
+#define DMA2_Stream2_BASE (DMA2_BASE + 0x040U)
+#define DMA2_Stream3_BASE (DMA2_BASE + 0x058U)
+#define DMA2_Stream4_BASE (DMA2_BASE + 0x070U)
+#define DMA2_Stream5_BASE (DMA2_BASE + 0x088U)
+#define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0U)
+#define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8U)
+#define ETH_BASE (AHB1PERIPH_BASE + 0x8000U)
+#define ETH_MAC_BASE (ETH_BASE)
+#define ETH_MMC_BASE (ETH_BASE + 0x0100U)
+#define ETH_PTP_BASE (ETH_BASE + 0x0700U)
+#define ETH_DMA_BASE (ETH_BASE + 0x1000U)
+
+/*!< AHB2 peripherals */
+#define DCMI_BASE (AHB2PERIPH_BASE + 0x50000U)
+#define RNG_BASE (AHB2PERIPH_BASE + 0x60800U)
+
+/*!< FSMC Bankx registers base address */
+#define FSMC_Bank1_R_BASE (FSMC_R_BASE + 0x0000U)
+#define FSMC_Bank1E_R_BASE (FSMC_R_BASE + 0x0104U)
+#define FSMC_Bank2_3_R_BASE (FSMC_R_BASE + 0x0060U)
+#define FSMC_Bank4_R_BASE (FSMC_R_BASE + 0x00A0U)
+
+/* Debug MCU registers base address */
+#define DBGMCU_BASE 0xE0042000U
+
+/*!< USB registers base address */
+#define USB_OTG_HS_PERIPH_BASE 0x40040000U
+#define USB_OTG_FS_PERIPH_BASE 0x50000000U
+
+#define USB_OTG_GLOBAL_BASE 0x000U
+#define USB_OTG_DEVICE_BASE 0x800U
+#define USB_OTG_IN_ENDPOINT_BASE 0x900U
+#define USB_OTG_OUT_ENDPOINT_BASE 0xB00U
+#define USB_OTG_EP_REG_SIZE 0x20U
+#define USB_OTG_HOST_BASE 0x400U
+#define USB_OTG_HOST_PORT_BASE 0x440U
+#define USB_OTG_HOST_CHANNEL_BASE 0x500U
+#define USB_OTG_HOST_CHANNEL_SIZE 0x20U
+#define USB_OTG_PCGCCTL_BASE 0xE00U
+#define USB_OTG_FIFO_BASE 0x1000U
+#define USB_OTG_FIFO_SIZE 0x1000U
+
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_declaration
+ * @{
+ */
+#define TIM2 ((TIM_TypeDef *) TIM2_BASE)
+#define TIM3 ((TIM_TypeDef *) TIM3_BASE)
+#define TIM4 ((TIM_TypeDef *) TIM4_BASE)
+#define TIM5 ((TIM_TypeDef *) TIM5_BASE)
+#define TIM6 ((TIM_TypeDef *) TIM6_BASE)
+#define TIM7 ((TIM_TypeDef *) TIM7_BASE)
+#define TIM12 ((TIM_TypeDef *) TIM12_BASE)
+#define TIM13 ((TIM_TypeDef *) TIM13_BASE)
+#define TIM14 ((TIM_TypeDef *) TIM14_BASE)
+#define RTC ((RTC_TypeDef *) RTC_BASE)
+#define WWDG ((WWDG_TypeDef *) WWDG_BASE)
+#define IWDG ((IWDG_TypeDef *) IWDG_BASE)
+#define I2S2ext ((SPI_TypeDef *) I2S2ext_BASE)
+#define SPI2 ((SPI_TypeDef *) SPI2_BASE)
+#define SPI3 ((SPI_TypeDef *) SPI3_BASE)
+#define I2S3ext ((SPI_TypeDef *) I2S3ext_BASE)
+#define USART2 ((USART_TypeDef *) USART2_BASE)
+#define USART3 ((USART_TypeDef *) USART3_BASE)
+#define UART4 ((USART_TypeDef *) UART4_BASE)
+#define UART5 ((USART_TypeDef *) UART5_BASE)
+#define I2C1 ((I2C_TypeDef *) I2C1_BASE)
+#define I2C2 ((I2C_TypeDef *) I2C2_BASE)
+#define I2C3 ((I2C_TypeDef *) I2C3_BASE)
+#define CAN1 ((CAN_TypeDef *) CAN1_BASE)
+#define CAN2 ((CAN_TypeDef *) CAN2_BASE)
+#define PWR ((PWR_TypeDef *) PWR_BASE)
+#define DAC ((DAC_TypeDef *) DAC_BASE)
+#define TIM1 ((TIM_TypeDef *) TIM1_BASE)
+#define TIM8 ((TIM_TypeDef *) TIM8_BASE)
+#define USART1 ((USART_TypeDef *) USART1_BASE)
+#define USART6 ((USART_TypeDef *) USART6_BASE)
+#define ADC ((ADC_Common_TypeDef *) ADC_BASE)
+#define ADC1 ((ADC_TypeDef *) ADC1_BASE)
+#define ADC2 ((ADC_TypeDef *) ADC2_BASE)
+#define ADC3 ((ADC_TypeDef *) ADC3_BASE)
+#define SDIO ((SDIO_TypeDef *) SDIO_BASE)
+#define SPI1 ((SPI_TypeDef *) SPI1_BASE)
+#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
+#define EXTI ((EXTI_TypeDef *) EXTI_BASE)
+#define TIM9 ((TIM_TypeDef *) TIM9_BASE)
+#define TIM10 ((TIM_TypeDef *) TIM10_BASE)
+#define TIM11 ((TIM_TypeDef *) TIM11_BASE)
+#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
+#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
+#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
+#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
+#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
+#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
+#define GPIOG ((GPIO_TypeDef *) GPIOG_BASE)
+#define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
+#define GPIOI ((GPIO_TypeDef *) GPIOI_BASE)
+#define CRC ((CRC_TypeDef *) CRC_BASE)
+#define RCC ((RCC_TypeDef *) RCC_BASE)
+#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
+#define DMA1 ((DMA_TypeDef *) DMA1_BASE)
+#define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)
+#define DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)
+#define DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)
+#define DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)
+#define DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)
+#define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)
+#define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)
+#define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)
+#define DMA2 ((DMA_TypeDef *) DMA2_BASE)
+#define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)
+#define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
+#define DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)
+#define DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)
+#define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)
+#define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)
+#define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)
+#define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)
+#define ETH ((ETH_TypeDef *) ETH_BASE)
+#define DCMI ((DCMI_TypeDef *) DCMI_BASE)
+#define RNG ((RNG_TypeDef *) RNG_BASE)
+#define FSMC_Bank1 ((FSMC_Bank1_TypeDef *) FSMC_Bank1_R_BASE)
+#define FSMC_Bank1E ((FSMC_Bank1E_TypeDef *) FSMC_Bank1E_R_BASE)
+#define FSMC_Bank2_3 ((FSMC_Bank2_3_TypeDef *) FSMC_Bank2_3_R_BASE)
+#define FSMC_Bank4 ((FSMC_Bank4_TypeDef *) FSMC_Bank4_R_BASE)
+
+#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
+
+#define USB_OTG_FS ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE)
+#define USB_OTG_HS ((USB_OTG_GlobalTypeDef *) USB_OTG_HS_PERIPH_BASE)
+
+/**
+ * @}
+ */
+
+/** @addtogroup Exported_constants
+ * @{
+ */
+
+ /** @addtogroup Peripheral_Registers_Bits_Definition
+ * @{
+ */
+
+/******************************************************************************/
+/* Peripheral Registers_Bits_Definition */
+/******************************************************************************/
+
+/******************************************************************************/
+/* */
+/* Analog to Digital Converter */
+/* */
+/******************************************************************************/
+/******************** Bit definition for ADC_SR register ********************/
+#define ADC_SR_AWD 0x00000001U /*!<Analog watchdog flag */
+#define ADC_SR_EOC 0x00000002U /*!<End of conversion */
+#define ADC_SR_JEOC 0x00000004U /*!<Injected channel end of conversion */
+#define ADC_SR_JSTRT 0x00000008U /*!<Injected channel Start flag */
+#define ADC_SR_STRT 0x00000010U /*!<Regular channel Start flag */
+#define ADC_SR_OVR 0x00000020U /*!<Overrun flag */
+
+/******************* Bit definition for ADC_CR1 register ********************/
+#define ADC_CR1_AWDCH 0x0000001FU /*!<AWDCH[4:0] bits (Analog watchdog channel select bits) */
+#define ADC_CR1_AWDCH_0 0x00000001U /*!<Bit 0 */
+#define ADC_CR1_AWDCH_1 0x00000002U /*!<Bit 1 */
+#define ADC_CR1_AWDCH_2 0x00000004U /*!<Bit 2 */
+#define ADC_CR1_AWDCH_3 0x00000008U /*!<Bit 3 */
+#define ADC_CR1_AWDCH_4 0x00000010U /*!<Bit 4 */
+#define ADC_CR1_EOCIE 0x00000020U /*!<Interrupt enable for EOC */
+#define ADC_CR1_AWDIE 0x00000040U /*!<AAnalog Watchdog interrupt enable */
+#define ADC_CR1_JEOCIE 0x00000080U /*!<Interrupt enable for injected channels */
+#define ADC_CR1_SCAN 0x00000100U /*!<Scan mode */
+#define ADC_CR1_AWDSGL 0x00000200U /*!<Enable the watchdog on a single channel in scan mode */
+#define ADC_CR1_JAUTO 0x00000400U /*!<Automatic injected group conversion */
+#define ADC_CR1_DISCEN 0x00000800U /*!<Discontinuous mode on regular channels */
+#define ADC_CR1_JDISCEN 0x00001000U /*!<Discontinuous mode on injected channels */
+#define ADC_CR1_DISCNUM 0x0000E000U /*!<DISCNUM[2:0] bits (Discontinuous mode channel count) */
+#define ADC_CR1_DISCNUM_0 0x00002000U /*!<Bit 0 */
+#define ADC_CR1_DISCNUM_1 0x00004000U /*!<Bit 1 */
+#define ADC_CR1_DISCNUM_2 0x00008000U /*!<Bit 2 */
+#define ADC_CR1_JAWDEN 0x00400000U /*!<Analog watchdog enable on injected channels */
+#define ADC_CR1_AWDEN 0x00800000U /*!<Analog watchdog enable on regular channels */
+#define ADC_CR1_RES 0x03000000U /*!<RES[2:0] bits (Resolution) */
+#define ADC_CR1_RES_0 0x01000000U /*!<Bit 0 */
+#define ADC_CR1_RES_1 0x02000000U /*!<Bit 1 */
+#define ADC_CR1_OVRIE 0x04000000U /*!<overrun interrupt enable */
+
+/******************* Bit definition for ADC_CR2 register ********************/
+#define ADC_CR2_ADON 0x00000001U /*!<A/D Converter ON / OFF */
+#define ADC_CR2_CONT 0x00000002U /*!<Continuous Conversion */
+#define ADC_CR2_DMA 0x00000100U /*!<Direct Memory access mode */
+#define ADC_CR2_DDS 0x00000200U /*!<DMA disable selection (Single ADC) */
+#define ADC_CR2_EOCS 0x00000400U /*!<End of conversion selection */
+#define ADC_CR2_ALIGN 0x00000800U /*!<Data Alignment */
+#define ADC_CR2_JEXTSEL 0x000F0000U /*!<JEXTSEL[3:0] bits (External event select for injected group) */
+#define ADC_CR2_JEXTSEL_0 0x00010000U /*!<Bit 0 */
+#define ADC_CR2_JEXTSEL_1 0x00020000U /*!<Bit 1 */
+#define ADC_CR2_JEXTSEL_2 0x00040000U /*!<Bit 2 */
+#define ADC_CR2_JEXTSEL_3 0x00080000U /*!<Bit 3 */
+#define ADC_CR2_JEXTEN 0x00300000U /*!<JEXTEN[1:0] bits (External Trigger Conversion mode for injected channelsp) */
+#define ADC_CR2_JEXTEN_0 0x00100000U /*!<Bit 0 */
+#define ADC_CR2_JEXTEN_1 0x00200000U /*!<Bit 1 */
+#define ADC_CR2_JSWSTART 0x00400000U /*!<Start Conversion of injected channels */
+#define ADC_CR2_EXTSEL 0x0F000000U /*!<EXTSEL[3:0] bits (External Event Select for regular group) */
+#define ADC_CR2_EXTSEL_0 0x01000000U /*!<Bit 0 */
+#define ADC_CR2_EXTSEL_1 0x02000000U /*!<Bit 1 */
+#define ADC_CR2_EXTSEL_2 0x04000000U /*!<Bit 2 */
+#define ADC_CR2_EXTSEL_3 0x08000000U /*!<Bit 3 */
+#define ADC_CR2_EXTEN 0x30000000U /*!<EXTEN[1:0] bits (External Trigger Conversion mode for regular channelsp) */
+#define ADC_CR2_EXTEN_0 0x10000000U /*!<Bit 0 */
+#define ADC_CR2_EXTEN_1 0x20000000U /*!<Bit 1 */
+#define ADC_CR2_SWSTART 0x40000000U /*!<Start Conversion of regular channels */
+
+/****************** Bit definition for ADC_SMPR1 register *******************/
+#define ADC_SMPR1_SMP10 0x00000007U /*!<SMP10[2:0] bits (Channel 10 Sample time selection) */
+#define ADC_SMPR1_SMP10_0 0x00000001U /*!<Bit 0 */
+#define ADC_SMPR1_SMP10_1 0x00000002U /*!<Bit 1 */
+#define ADC_SMPR1_SMP10_2 0x00000004U /*!<Bit 2 */
+#define ADC_SMPR1_SMP11 0x00000038U /*!<SMP11[2:0] bits (Channel 11 Sample time selection) */
+#define ADC_SMPR1_SMP11_0 0x00000008U /*!<Bit 0 */
+#define ADC_SMPR1_SMP11_1 0x00000010U /*!<Bit 1 */
+#define ADC_SMPR1_SMP11_2 0x00000020U /*!<Bit 2 */
+#define ADC_SMPR1_SMP12 0x000001C0U /*!<SMP12[2:0] bits (Channel 12 Sample time selection) */
+#define ADC_SMPR1_SMP12_0 0x00000040U /*!<Bit 0 */
+#define ADC_SMPR1_SMP12_1 0x00000080U /*!<Bit 1 */
+#define ADC_SMPR1_SMP12_2 0x00000100U /*!<Bit 2 */
+#define ADC_SMPR1_SMP13 0x00000E00U /*!<SMP13[2:0] bits (Channel 13 Sample time selection) */
+#define ADC_SMPR1_SMP13_0 0x00000200U /*!<Bit 0 */
+#define ADC_SMPR1_SMP13_1 0x00000400U /*!<Bit 1 */
+#define ADC_SMPR1_SMP13_2 0x00000800U /*!<Bit 2 */
+#define ADC_SMPR1_SMP14 0x00007000U /*!<SMP14[2:0] bits (Channel 14 Sample time selection) */
+#define ADC_SMPR1_SMP14_0 0x00001000U /*!<Bit 0 */
+#define ADC_SMPR1_SMP14_1 0x00002000U /*!<Bit 1 */
+#define ADC_SMPR1_SMP14_2 0x00004000U /*!<Bit 2 */
+#define ADC_SMPR1_SMP15 0x00038000U /*!<SMP15[2:0] bits (Channel 15 Sample time selection) */
+#define ADC_SMPR1_SMP15_0 0x00008000U /*!<Bit 0 */
+#define ADC_SMPR1_SMP15_1 0x00010000U /*!<Bit 1 */
+#define ADC_SMPR1_SMP15_2 0x00020000U /*!<Bit 2 */
+#define ADC_SMPR1_SMP16 0x001C0000U /*!<SMP16[2:0] bits (Channel 16 Sample time selection) */
+#define ADC_SMPR1_SMP16_0 0x00040000U /*!<Bit 0 */
+#define ADC_SMPR1_SMP16_1 0x00080000U /*!<Bit 1 */
+#define ADC_SMPR1_SMP16_2 0x00100000U /*!<Bit 2 */
+#define ADC_SMPR1_SMP17 0x00E00000U /*!<SMP17[2:0] bits (Channel 17 Sample time selection) */
+#define ADC_SMPR1_SMP17_0 0x00200000U /*!<Bit 0 */
+#define ADC_SMPR1_SMP17_1 0x00400000U /*!<Bit 1 */
+#define ADC_SMPR1_SMP17_2 0x00800000U /*!<Bit 2 */
+#define ADC_SMPR1_SMP18 0x07000000U /*!<SMP18[2:0] bits (Channel 18 Sample time selection) */
+#define ADC_SMPR1_SMP18_0 0x01000000U /*!<Bit 0 */
+#define ADC_SMPR1_SMP18_1 0x02000000U /*!<Bit 1 */
+#define ADC_SMPR1_SMP18_2 0x04000000U /*!<Bit 2 */
+
+/****************** Bit definition for ADC_SMPR2 register *******************/
+#define ADC_SMPR2_SMP0 0x00000007U /*!<SMP0[2:0] bits (Channel 0 Sample time selection) */
+#define ADC_SMPR2_SMP0_0 0x00000001U /*!<Bit 0 */
+#define ADC_SMPR2_SMP0_1 0x00000002U /*!<Bit 1 */
+#define ADC_SMPR2_SMP0_2 0x00000004U /*!<Bit 2 */
+#define ADC_SMPR2_SMP1 0x00000038U /*!<SMP1[2:0] bits (Channel 1 Sample time selection) */
+#define ADC_SMPR2_SMP1_0 0x00000008U /*!<Bit 0 */
+#define ADC_SMPR2_SMP1_1 0x00000010U /*!<Bit 1 */
+#define ADC_SMPR2_SMP1_2 0x00000020U /*!<Bit 2 */
+#define ADC_SMPR2_SMP2 0x000001C0U /*!<SMP2[2:0] bits (Channel 2 Sample time selection) */
+#define ADC_SMPR2_SMP2_0 0x00000040U /*!<Bit 0 */
+#define ADC_SMPR2_SMP2_1 0x00000080U /*!<Bit 1 */
+#define ADC_SMPR2_SMP2_2 0x00000100U /*!<Bit 2 */
+#define ADC_SMPR2_SMP3 0x00000E00U /*!<SMP3[2:0] bits (Channel 3 Sample time selection) */
+#define ADC_SMPR2_SMP3_0 0x00000200U /*!<Bit 0 */
+#define ADC_SMPR2_SMP3_1 0x00000400U /*!<Bit 1 */
+#define ADC_SMPR2_SMP3_2 0x00000800U /*!<Bit 2 */
+#define ADC_SMPR2_SMP4 0x00007000U /*!<SMP4[2:0] bits (Channel 4 Sample time selection) */
+#define ADC_SMPR2_SMP4_0 0x00001000U /*!<Bit 0 */
+#define ADC_SMPR2_SMP4_1 0x00002000U /*!<Bit 1 */
+#define ADC_SMPR2_SMP4_2 0x00004000U /*!<Bit 2 */
+#define ADC_SMPR2_SMP5 0x00038000U /*!<SMP5[2:0] bits (Channel 5 Sample time selection) */
+#define ADC_SMPR2_SMP5_0 0x00008000U /*!<Bit 0 */
+#define ADC_SMPR2_SMP5_1 0x00010000U /*!<Bit 1 */
+#define ADC_SMPR2_SMP5_2 0x00020000U /*!<Bit 2 */
+#define ADC_SMPR2_SMP6 0x001C0000U /*!<SMP6[2:0] bits (Channel 6 Sample time selection) */
+#define ADC_SMPR2_SMP6_0 0x00040000U /*!<Bit 0 */
+#define ADC_SMPR2_SMP6_1 0x00080000U /*!<Bit 1 */
+#define ADC_SMPR2_SMP6_2 0x00100000U /*!<Bit 2 */
+#define ADC_SMPR2_SMP7 0x00E00000U /*!<SMP7[2:0] bits (Channel 7 Sample time selection) */
+#define ADC_SMPR2_SMP7_0 0x00200000U /*!<Bit 0 */
+#define ADC_SMPR2_SMP7_1 0x00400000U /*!<Bit 1 */
+#define ADC_SMPR2_SMP7_2 0x00800000U /*!<Bit 2 */
+#define ADC_SMPR2_SMP8 0x07000000U /*!<SMP8[2:0] bits (Channel 8 Sample time selection) */
+#define ADC_SMPR2_SMP8_0 0x01000000U /*!<Bit 0 */
+#define ADC_SMPR2_SMP8_1 0x02000000U /*!<Bit 1 */
+#define ADC_SMPR2_SMP8_2 0x04000000U /*!<Bit 2 */
+#define ADC_SMPR2_SMP9 0x38000000U /*!<SMP9[2:0] bits (Channel 9 Sample time selection) */
+#define ADC_SMPR2_SMP9_0 0x08000000U /*!<Bit 0 */
+#define ADC_SMPR2_SMP9_1 0x10000000U /*!<Bit 1 */
+#define ADC_SMPR2_SMP9_2 0x20000000U /*!<Bit 2 */
+
+/****************** Bit definition for ADC_JOFR1 register *******************/
+#define ADC_JOFR1_JOFFSET1 0x0FFFU /*!<Data offset for injected channel 1 */
+
+/****************** Bit definition for ADC_JOFR2 register *******************/
+#define ADC_JOFR2_JOFFSET2 0x0FFFU /*!<Data offset for injected channel 2 */
+
+/****************** Bit definition for ADC_JOFR3 register *******************/
+#define ADC_JOFR3_JOFFSET3 0x0FFFU /*!<Data offset for injected channel 3 */
+
+/****************** Bit definition for ADC_JOFR4 register *******************/
+#define ADC_JOFR4_JOFFSET4 0x0FFFU /*!<Data offset for injected channel 4 */
+
+/******************* Bit definition for ADC_HTR register ********************/
+#define ADC_HTR_HT 0x0FFFU /*!<Analog watchdog high threshold */
+
+/******************* Bit definition for ADC_LTR register ********************/
+#define ADC_LTR_LT 0x0FFFU /*!<Analog watchdog low threshold */
+
+/******************* Bit definition for ADC_SQR1 register *******************/
+#define ADC_SQR1_SQ13 0x0000001FU /*!<SQ13[4:0] bits (13th conversion in regular sequence) */
+#define ADC_SQR1_SQ13_0 0x00000001U /*!<Bit 0 */
+#define ADC_SQR1_SQ13_1 0x00000002U /*!<Bit 1 */
+#define ADC_SQR1_SQ13_2 0x00000004U /*!<Bit 2 */
+#define ADC_SQR1_SQ13_3 0x00000008U /*!<Bit 3 */
+#define ADC_SQR1_SQ13_4 0x00000010U /*!<Bit 4 */
+#define ADC_SQR1_SQ14 0x000003E0U /*!<SQ14[4:0] bits (14th conversion in regular sequence) */
+#define ADC_SQR1_SQ14_0 0x00000020U /*!<Bit 0 */
+#define ADC_SQR1_SQ14_1 0x00000040U /*!<Bit 1 */
+#define ADC_SQR1_SQ14_2 0x00000080U /*!<Bit 2 */
+#define ADC_SQR1_SQ14_3 0x00000100U /*!<Bit 3 */
+#define ADC_SQR1_SQ14_4 0x00000200U /*!<Bit 4 */
+#define ADC_SQR1_SQ15 0x00007C00U /*!<SQ15[4:0] bits (15th conversion in regular sequence) */
+#define ADC_SQR1_SQ15_0 0x00000400U /*!<Bit 0 */
+#define ADC_SQR1_SQ15_1 0x00000800U /*!<Bit 1 */
+#define ADC_SQR1_SQ15_2 0x00001000U /*!<Bit 2 */
+#define ADC_SQR1_SQ15_3 0x00002000U /*!<Bit 3 */
+#define ADC_SQR1_SQ15_4 0x00004000U /*!<Bit 4 */
+#define ADC_SQR1_SQ16 0x000F8000U /*!<SQ16[4:0] bits (16th conversion in regular sequence) */
+#define ADC_SQR1_SQ16_0 0x00008000U /*!<Bit 0 */
+#define ADC_SQR1_SQ16_1 0x00010000U /*!<Bit 1 */
+#define ADC_SQR1_SQ16_2 0x00020000U /*!<Bit 2 */
+#define ADC_SQR1_SQ16_3 0x00040000U /*!<Bit 3 */
+#define ADC_SQR1_SQ16_4 0x00080000U /*!<Bit 4 */
+#define ADC_SQR1_L 0x00F00000U /*!<L[3:0] bits (Regular channel sequence length) */
+#define ADC_SQR1_L_0 0x00100000U /*!<Bit 0 */
+#define ADC_SQR1_L_1 0x00200000U /*!<Bit 1 */
+#define ADC_SQR1_L_2 0x00400000U /*!<Bit 2 */
+#define ADC_SQR1_L_3 0x00800000U /*!<Bit 3 */
+
+/******************* Bit definition for ADC_SQR2 register *******************/
+#define ADC_SQR2_SQ7 0x0000001FU /*!<SQ7[4:0] bits (7th conversion in regular sequence) */
+#define ADC_SQR2_SQ7_0 0x00000001U /*!<Bit 0 */
+#define ADC_SQR2_SQ7_1 0x00000002U /*!<Bit 1 */
+#define ADC_SQR2_SQ7_2 0x00000004U /*!<Bit 2 */
+#define ADC_SQR2_SQ7_3 0x00000008U /*!<Bit 3 */
+#define ADC_SQR2_SQ7_4 0x00000010U /*!<Bit 4 */
+#define ADC_SQR2_SQ8 0x000003E0U /*!<SQ8[4:0] bits (8th conversion in regular sequence) */
+#define ADC_SQR2_SQ8_0 0x00000020U /*!<Bit 0 */
+#define ADC_SQR2_SQ8_1 0x00000040U /*!<Bit 1 */
+#define ADC_SQR2_SQ8_2 0x00000080U /*!<Bit 2 */
+#define ADC_SQR2_SQ8_3 0x00000100U /*!<Bit 3 */
+#define ADC_SQR2_SQ8_4 0x00000200U /*!<Bit 4 */
+#define ADC_SQR2_SQ9 0x00007C00U /*!<SQ9[4:0] bits (9th conversion in regular sequence) */
+#define ADC_SQR2_SQ9_0 0x00000400U /*!<Bit 0 */
+#define ADC_SQR2_SQ9_1 0x00000800U /*!<Bit 1 */
+#define ADC_SQR2_SQ9_2 0x00001000U /*!<Bit 2 */
+#define ADC_SQR2_SQ9_3 0x00002000U /*!<Bit 3 */
+#define ADC_SQR2_SQ9_4 0x00004000U /*!<Bit 4 */
+#define ADC_SQR2_SQ10 0x000F8000U /*!<SQ10[4:0] bits (10th conversion in regular sequence) */
+#define ADC_SQR2_SQ10_0 0x00008000U /*!<Bit 0 */
+#define ADC_SQR2_SQ10_1 0x00010000U /*!<Bit 1 */
+#define ADC_SQR2_SQ10_2 0x00020000U /*!<Bit 2 */
+#define ADC_SQR2_SQ10_3 0x00040000U /*!<Bit 3 */
+#define ADC_SQR2_SQ10_4 0x00080000U /*!<Bit 4 */
+#define ADC_SQR2_SQ11 0x01F00000U /*!<SQ11[4:0] bits (11th conversion in regular sequence) */
+#define ADC_SQR2_SQ11_0 0x00100000U /*!<Bit 0 */
+#define ADC_SQR2_SQ11_1 0x00200000U /*!<Bit 1 */
+#define ADC_SQR2_SQ11_2 0x00400000U /*!<Bit 2 */
+#define ADC_SQR2_SQ11_3 0x00800000U /*!<Bit 3 */
+#define ADC_SQR2_SQ11_4 0x01000000U /*!<Bit 4 */
+#define ADC_SQR2_SQ12 0x3E000000U /*!<SQ12[4:0] bits (12th conversion in regular sequence) */
+#define ADC_SQR2_SQ12_0 0x02000000U /*!<Bit 0 */
+#define ADC_SQR2_SQ12_1 0x04000000U /*!<Bit 1 */
+#define ADC_SQR2_SQ12_2 0x08000000U /*!<Bit 2 */
+#define ADC_SQR2_SQ12_3 0x10000000U /*!<Bit 3 */
+#define ADC_SQR2_SQ12_4 0x20000000U /*!<Bit 4 */
+
+/******************* Bit definition for ADC_SQR3 register *******************/
+#define ADC_SQR3_SQ1 0x0000001FU /*!<SQ1[4:0] bits (1st conversion in regular sequence) */
+#define ADC_SQR3_SQ1_0 0x00000001U /*!<Bit 0 */
+#define ADC_SQR3_SQ1_1 0x00000002U /*!<Bit 1 */
+#define ADC_SQR3_SQ1_2 0x00000004U /*!<Bit 2 */
+#define ADC_SQR3_SQ1_3 0x00000008U /*!<Bit 3 */
+#define ADC_SQR3_SQ1_4 0x00000010U /*!<Bit 4 */
+#define ADC_SQR3_SQ2 0x000003E0U /*!<SQ2[4:0] bits (2nd conversion in regular sequence) */
+#define ADC_SQR3_SQ2_0 0x00000020U /*!<Bit 0 */
+#define ADC_SQR3_SQ2_1 0x00000040U /*!<Bit 1 */
+#define ADC_SQR3_SQ2_2 0x00000080U /*!<Bit 2 */
+#define ADC_SQR3_SQ2_3 0x00000100U /*!<Bit 3 */
+#define ADC_SQR3_SQ2_4 0x00000200U /*!<Bit 4 */
+#define ADC_SQR3_SQ3 0x00007C00U /*!<SQ3[4:0] bits (3rd conversion in regular sequence) */
+#define ADC_SQR3_SQ3_0 0x00000400U /*!<Bit 0 */
+#define ADC_SQR3_SQ3_1 0x00000800U /*!<Bit 1 */
+#define ADC_SQR3_SQ3_2 0x00001000U /*!<Bit 2 */
+#define ADC_SQR3_SQ3_3 0x00002000U /*!<Bit 3 */
+#define ADC_SQR3_SQ3_4 0x00004000U /*!<Bit 4 */
+#define ADC_SQR3_SQ4 0x000F8000U /*!<SQ4[4:0] bits (4th conversion in regular sequence) */
+#define ADC_SQR3_SQ4_0 0x00008000U /*!<Bit 0 */
+#define ADC_SQR3_SQ4_1 0x00010000U /*!<Bit 1 */
+#define ADC_SQR3_SQ4_2 0x00020000U /*!<Bit 2 */
+#define ADC_SQR3_SQ4_3 0x00040000U /*!<Bit 3 */
+#define ADC_SQR3_SQ4_4 0x00080000U /*!<Bit 4 */
+#define ADC_SQR3_SQ5 0x01F00000U /*!<SQ5[4:0] bits (5th conversion in regular sequence) */
+#define ADC_SQR3_SQ5_0 0x00100000U /*!<Bit 0 */
+#define ADC_SQR3_SQ5_1 0x00200000U /*!<Bit 1 */
+#define ADC_SQR3_SQ5_2 0x00400000U /*!<Bit 2 */
+#define ADC_SQR3_SQ5_3 0x00800000U /*!<Bit 3 */
+#define ADC_SQR3_SQ5_4 0x01000000U /*!<Bit 4 */
+#define ADC_SQR3_SQ6 0x3E000000U /*!<SQ6[4:0] bits (6th conversion in regular sequence) */
+#define ADC_SQR3_SQ6_0 0x02000000U /*!<Bit 0 */
+#define ADC_SQR3_SQ6_1 0x04000000U /*!<Bit 1 */
+#define ADC_SQR3_SQ6_2 0x08000000U /*!<Bit 2 */
+#define ADC_SQR3_SQ6_3 0x10000000U /*!<Bit 3 */
+#define ADC_SQR3_SQ6_4 0x20000000U /*!<Bit 4 */
+
+/******************* Bit definition for ADC_JSQR register *******************/
+#define ADC_JSQR_JSQ1 0x0000001FU /*!<JSQ1[4:0] bits (1st conversion in injected sequence) */
+#define ADC_JSQR_JSQ1_0 0x00000001U /*!<Bit 0 */
+#define ADC_JSQR_JSQ1_1 0x00000002U /*!<Bit 1 */
+#define ADC_JSQR_JSQ1_2 0x00000004U /*!<Bit 2 */
+#define ADC_JSQR_JSQ1_3 0x00000008U /*!<Bit 3 */
+#define ADC_JSQR_JSQ1_4 0x00000010U /*!<Bit 4 */
+#define ADC_JSQR_JSQ2 0x000003E0U /*!<JSQ2[4:0] bits (2nd conversion in injected sequence) */
+#define ADC_JSQR_JSQ2_0 0x00000020U /*!<Bit 0 */
+#define ADC_JSQR_JSQ2_1 0x00000040U /*!<Bit 1 */
+#define ADC_JSQR_JSQ2_2 0x00000080U /*!<Bit 2 */
+#define ADC_JSQR_JSQ2_3 0x00000100U /*!<Bit 3 */
+#define ADC_JSQR_JSQ2_4 0x00000200U /*!<Bit 4 */
+#define ADC_JSQR_JSQ3 0x00007C00U /*!<JSQ3[4:0] bits (3rd conversion in injected sequence) */
+#define ADC_JSQR_JSQ3_0 0x00000400U /*!<Bit 0 */
+#define ADC_JSQR_JSQ3_1 0x00000800U /*!<Bit 1 */
+#define ADC_JSQR_JSQ3_2 0x00001000U /*!<Bit 2 */
+#define ADC_JSQR_JSQ3_3 0x00002000U /*!<Bit 3 */
+#define ADC_JSQR_JSQ3_4 0x00004000U /*!<Bit 4 */
+#define ADC_JSQR_JSQ4 0x000F8000U /*!<JSQ4[4:0] bits (4th conversion in injected sequence) */
+#define ADC_JSQR_JSQ4_0 0x00008000U /*!<Bit 0 */
+#define ADC_JSQR_JSQ4_1 0x00010000U /*!<Bit 1 */
+#define ADC_JSQR_JSQ4_2 0x00020000U /*!<Bit 2 */
+#define ADC_JSQR_JSQ4_3 0x00040000U /*!<Bit 3 */
+#define ADC_JSQR_JSQ4_4 0x00080000U /*!<Bit 4 */
+#define ADC_JSQR_JL 0x00300000U /*!<JL[1:0] bits (Injected Sequence length) */
+#define ADC_JSQR_JL_0 0x00100000U /*!<Bit 0 */
+#define ADC_JSQR_JL_1 0x00200000U /*!<Bit 1 */
+
+/******************* Bit definition for ADC_JDR1 register *******************/
+#define ADC_JDR1_JDATA 0xFFFFU /*!<Injected data */
+
+/******************* Bit definition for ADC_JDR2 register *******************/
+#define ADC_JDR2_JDATA 0xFFFFU /*!<Injected data */
+
+/******************* Bit definition for ADC_JDR3 register *******************/
+#define ADC_JDR3_JDATA 0xFFFFU /*!<Injected data */
+
+/******************* Bit definition for ADC_JDR4 register *******************/
+#define ADC_JDR4_JDATA 0xFFFFU /*!<Injected data */
+
+/******************** Bit definition for ADC_DR register ********************/
+#define ADC_DR_DATA 0x0000FFFFU /*!<Regular data */
+#define ADC_DR_ADC2DATA 0xFFFF0000U /*!<ADC2 data */
+
+/******************* Bit definition for ADC_CSR register ********************/
+#define ADC_CSR_AWD1 0x00000001U /*!<ADC1 Analog watchdog flag */
+#define ADC_CSR_EOC1 0x00000002U /*!<ADC1 End of conversion */
+#define ADC_CSR_JEOC1 0x00000004U /*!<ADC1 Injected channel end of conversion */
+#define ADC_CSR_JSTRT1 0x00000008U /*!<ADC1 Injected channel Start flag */
+#define ADC_CSR_STRT1 0x00000010U /*!<ADC1 Regular channel Start flag */
+#define ADC_CSR_OVR1 0x00000020U /*!<ADC1 DMA overrun flag */
+#define ADC_CSR_AWD2 0x00000100U /*!<ADC2 Analog watchdog flag */
+#define ADC_CSR_EOC2 0x00000200U /*!<ADC2 End of conversion */
+#define ADC_CSR_JEOC2 0x00000400U /*!<ADC2 Injected channel end of conversion */
+#define ADC_CSR_JSTRT2 0x00000800U /*!<ADC2 Injected channel Start flag */
+#define ADC_CSR_STRT2 0x00001000U /*!<ADC2 Regular channel Start flag */
+#define ADC_CSR_OVR2 0x00002000U /*!<ADC2 DMA overrun flag */
+#define ADC_CSR_AWD3 0x00010000U /*!<ADC3 Analog watchdog flag */
+#define ADC_CSR_EOC3 0x00020000U /*!<ADC3 End of conversion */
+#define ADC_CSR_JEOC3 0x00040000U /*!<ADC3 Injected channel end of conversion */
+#define ADC_CSR_JSTRT3 0x00080000U /*!<ADC3 Injected channel Start flag */
+#define ADC_CSR_STRT3 0x00100000U /*!<ADC3 Regular channel Start flag */
+#define ADC_CSR_OVR3 0x00200000U /*!<ADC3 DMA overrun flag */
+
+/* Legacy defines */
+#define ADC_CSR_DOVR1 ADC_CSR_OVR1
+#define ADC_CSR_DOVR2 ADC_CSR_OVR2
+#define ADC_CSR_DOVR3 ADC_CSR_OVR3
+
+/******************* Bit definition for ADC_CCR register ********************/
+#define ADC_CCR_MULTI 0x0000001FU /*!<MULTI[4:0] bits (Multi-ADC mode selection) */
+#define ADC_CCR_MULTI_0 0x00000001U /*!<Bit 0 */
+#define ADC_CCR_MULTI_1 0x00000002U /*!<Bit 1 */
+#define ADC_CCR_MULTI_2 0x00000004U /*!<Bit 2 */
+#define ADC_CCR_MULTI_3 0x00000008U /*!<Bit 3 */
+#define ADC_CCR_MULTI_4 0x00000010U /*!<Bit 4 */
+#define ADC_CCR_DELAY 0x00000F00U /*!<DELAY[3:0] bits (Delay between 2 sampling phases) */
+#define ADC_CCR_DELAY_0 0x00000100U /*!<Bit 0 */
+#define ADC_CCR_DELAY_1 0x00000200U /*!<Bit 1 */
+#define ADC_CCR_DELAY_2 0x00000400U /*!<Bit 2 */
+#define ADC_CCR_DELAY_3 0x00000800U /*!<Bit 3 */
+#define ADC_CCR_DDS 0x00002000U /*!<DMA disable selection (Multi-ADC mode) */
+#define ADC_CCR_DMA 0x0000C000U /*!<DMA[1:0] bits (Direct Memory Access mode for multimode) */
+#define ADC_CCR_DMA_0 0x00004000U /*!<Bit 0 */
+#define ADC_CCR_DMA_1 0x00008000U /*!<Bit 1 */
+#define ADC_CCR_ADCPRE 0x00030000U /*!<ADCPRE[1:0] bits (ADC prescaler) */
+#define ADC_CCR_ADCPRE_0 0x00010000U /*!<Bit 0 */
+#define ADC_CCR_ADCPRE_1 0x00020000U /*!<Bit 1 */
+#define ADC_CCR_VBATE 0x00400000U /*!<VBAT Enable */
+#define ADC_CCR_TSVREFE 0x00800000U /*!<Temperature Sensor and VREFINT Enable */
+
+/******************* Bit definition for ADC_CDR register ********************/
+#define ADC_CDR_DATA1 0x0000FFFFU /*!<1st data of a pair of regular conversions */
+#define ADC_CDR_DATA2 0xFFFF0000U /*!<2nd data of a pair of regular conversions */
+
+/******************************************************************************/
+/* */
+/* Controller Area Network */
+/* */
+/******************************************************************************/
+/*!<CAN control and status registers */
+/******************* Bit definition for CAN_MCR register ********************/
+#define CAN_MCR_INRQ 0x00000001U /*!<Initialization Request */
+#define CAN_MCR_SLEEP 0x00000002U /*!<Sleep Mode Request */
+#define CAN_MCR_TXFP 0x00000004U /*!<Transmit FIFO Priority */
+#define CAN_MCR_RFLM 0x00000008U /*!<Receive FIFO Locked Mode */
+#define CAN_MCR_NART 0x00000010U /*!<No Automatic Retransmission */
+#define CAN_MCR_AWUM 0x00000020U /*!<Automatic Wakeup Mode */
+#define CAN_MCR_ABOM 0x00000040U /*!<Automatic Bus-Off Management */
+#define CAN_MCR_TTCM 0x00000080U /*!<Time Triggered Communication Mode */
+#define CAN_MCR_RESET 0x00008000U /*!<bxCAN software master reset */
+#define CAN_MCR_DBF 0x00010000U /*!<bxCAN Debug freeze */
+/******************* Bit definition for CAN_MSR register ********************/
+#define CAN_MSR_INAK 0x0001U /*!<Initialization Acknowledge */
+#define CAN_MSR_SLAK 0x0002U /*!<Sleep Acknowledge */
+#define CAN_MSR_ERRI 0x0004U /*!<Error Interrupt */
+#define CAN_MSR_WKUI 0x0008U /*!<Wakeup Interrupt */
+#define CAN_MSR_SLAKI 0x0010U /*!<Sleep Acknowledge Interrupt */
+#define CAN_MSR_TXM 0x0100U /*!<Transmit Mode */
+#define CAN_MSR_RXM 0x0200U /*!<Receive Mode */
+#define CAN_MSR_SAMP 0x0400U /*!<Last Sample Point */
+#define CAN_MSR_RX 0x0800U /*!<CAN Rx Signal */
+
+/******************* Bit definition for CAN_TSR register ********************/
+#define CAN_TSR_RQCP0 0x00000001U /*!<Request Completed Mailbox0 */
+#define CAN_TSR_TXOK0 0x00000002U /*!<Transmission OK of Mailbox0 */
+#define CAN_TSR_ALST0 0x00000004U /*!<Arbitration Lost for Mailbox0 */
+#define CAN_TSR_TERR0 0x00000008U /*!<Transmission Error of Mailbox0 */
+#define CAN_TSR_ABRQ0 0x00000080U /*!<Abort Request for Mailbox0 */
+#define CAN_TSR_RQCP1 0x00000100U /*!<Request Completed Mailbox1 */
+#define CAN_TSR_TXOK1 0x00000200U /*!<Transmission OK of Mailbox1 */
+#define CAN_TSR_ALST1 0x00000400U /*!<Arbitration Lost for Mailbox1 */
+#define CAN_TSR_TERR1 0x00000800U /*!<Transmission Error of Mailbox1 */
+#define CAN_TSR_ABRQ1 0x00008000U /*!<Abort Request for Mailbox 1 */
+#define CAN_TSR_RQCP2 0x00010000U /*!<Request Completed Mailbox2 */
+#define CAN_TSR_TXOK2 0x00020000U /*!<Transmission OK of Mailbox 2 */
+#define CAN_TSR_ALST2 0x00040000U /*!<Arbitration Lost for mailbox 2 */
+#define CAN_TSR_TERR2 0x00080000U /*!<Transmission Error of Mailbox 2 */
+#define CAN_TSR_ABRQ2 0x00800000U /*!<Abort Request for Mailbox 2 */
+#define CAN_TSR_CODE 0x03000000U /*!<Mailbox Code */
+
+#define CAN_TSR_TME 0x1C000000U /*!<TME[2:0] bits */
+#define CAN_TSR_TME0 0x04000000U /*!<Transmit Mailbox 0 Empty */
+#define CAN_TSR_TME1 0x08000000U /*!<Transmit Mailbox 1 Empty */
+#define CAN_TSR_TME2 0x10000000U /*!<Transmit Mailbox 2 Empty */
+
+#define CAN_TSR_LOW 0xE0000000U /*!<LOW[2:0] bits */
+#define CAN_TSR_LOW0 0x20000000U /*!<Lowest Priority Flag for Mailbox 0 */
+#define CAN_TSR_LOW1 0x40000000U /*!<Lowest Priority Flag for Mailbox 1 */
+#define CAN_TSR_LOW2 0x80000000U /*!<Lowest Priority Flag for Mailbox 2 */
+
+/******************* Bit definition for CAN_RF0R register *******************/
+#define CAN_RF0R_FMP0 0x03U /*!<FIFO 0 Message Pending */
+#define CAN_RF0R_FULL0 0x08U /*!<FIFO 0 Full */
+#define CAN_RF0R_FOVR0 0x10U /*!<FIFO 0 Overrun */
+#define CAN_RF0R_RFOM0 0x20U /*!<Release FIFO 0 Output Mailbox */
+
+/******************* Bit definition for CAN_RF1R register *******************/
+#define CAN_RF1R_FMP1 0x03U /*!<FIFO 1 Message Pending */
+#define CAN_RF1R_FULL1 0x08U /*!<FIFO 1 Full */
+#define CAN_RF1R_FOVR1 0x10U /*!<FIFO 1 Overrun */
+#define CAN_RF1R_RFOM1 0x20U /*!<Release FIFO 1 Output Mailbox */
+
+/******************** Bit definition for CAN_IER register *******************/
+#define CAN_IER_TMEIE 0x00000001U /*!<Transmit Mailbox Empty Interrupt Enable */
+#define CAN_IER_FMPIE0 0x00000002U /*!<FIFO Message Pending Interrupt Enable */
+#define CAN_IER_FFIE0 0x00000004U /*!<FIFO Full Interrupt Enable */
+#define CAN_IER_FOVIE0 0x00000008U /*!<FIFO Overrun Interrupt Enable */
+#define CAN_IER_FMPIE1 0x00000010U /*!<FIFO Message Pending Interrupt Enable */
+#define CAN_IER_FFIE1 0x00000020U /*!<FIFO Full Interrupt Enable */
+#define CAN_IER_FOVIE1 0x00000040U /*!<FIFO Overrun Interrupt Enable */
+#define CAN_IER_EWGIE 0x00000100U /*!<Error Warning Interrupt Enable */
+#define CAN_IER_EPVIE 0x00000200U /*!<Error Passive Interrupt Enable */
+#define CAN_IER_BOFIE 0x00000400U /*!<Bus-Off Interrupt Enable */
+#define CAN_IER_LECIE 0x00000800U /*!<Last Error Code Interrupt Enable */
+#define CAN_IER_ERRIE 0x00008000U /*!<Error Interrupt Enable */
+#define CAN_IER_WKUIE 0x00010000U /*!<Wakeup Interrupt Enable */
+#define CAN_IER_SLKIE 0x00020000U /*!<Sleep Interrupt Enable */
+#define CAN_IER_EWGIE 0x00000100U /*!<Error warning interrupt enable */
+#define CAN_IER_EPVIE 0x00000200U /*!<Error passive interrupt enable */
+#define CAN_IER_BOFIE 0x00000400U /*!<Bus-off interrupt enable */
+#define CAN_IER_LECIE 0x00000800U /*!<Last error code interrupt enable */
+#define CAN_IER_ERRIE 0x00008000U /*!<Error interrupt enable */
+
+
+/******************** Bit definition for CAN_ESR register *******************/
+#define CAN_ESR_EWGF 0x00000001U /*!<Error Warning Flag */
+#define CAN_ESR_EPVF 0x00000002U /*!<Error Passive Flag */
+#define CAN_ESR_BOFF 0x00000004U /*!<Bus-Off Flag */
+
+#define CAN_ESR_LEC 0x00000070U /*!<LEC[2:0] bits (Last Error Code) */
+#define CAN_ESR_LEC_0 0x00000010U /*!<Bit 0 */
+#define CAN_ESR_LEC_1 0x00000020U /*!<Bit 1 */
+#define CAN_ESR_LEC_2 0x00000040U /*!<Bit 2 */
+
+#define CAN_ESR_TEC 0x00FF0000U /*!<Least significant byte of the 9-bit Transmit Error Counter */
+#define CAN_ESR_REC 0xFF000000U /*!<Receive Error Counter */
+
+/******************* Bit definition for CAN_BTR register ********************/
+#define CAN_BTR_BRP 0x000003FFU /*!<Baud Rate Prescaler */
+#define CAN_BTR_TS1 0x000F0000U /*!<Time Segment 1 */
+#define CAN_BTR_TS1_0 0x00010000U /*!<Bit 0 */
+#define CAN_BTR_TS1_1 0x00020000U /*!<Bit 1 */
+#define CAN_BTR_TS1_2 0x00040000U /*!<Bit 2 */
+#define CAN_BTR_TS1_3 0x00080000U /*!<Bit 3 */
+#define CAN_BTR_TS2 0x00700000U /*!<Time Segment 2 */
+#define CAN_BTR_TS2_0 0x00100000U /*!<Bit 0 */
+#define CAN_BTR_TS2_1 0x00200000U /*!<Bit 1 */
+#define CAN_BTR_TS2_2 0x00400000U /*!<Bit 2 */
+#define CAN_BTR_SJW 0x03000000U /*!<Resynchronization Jump Width */
+#define CAN_BTR_SJW_0 0x01000000U /*!<Bit 0 */
+#define CAN_BTR_SJW_1 0x02000000U /*!<Bit 1 */
+#define CAN_BTR_LBKM 0x40000000U /*!<Loop Back Mode (Debug) */
+#define CAN_BTR_SILM 0x80000000U /*!<Silent Mode */
+
+
+/*!<Mailbox registers */
+/****************** Bit definition for CAN_TI0R register ********************/
+#define CAN_TI0R_TXRQ 0x00000001U /*!<Transmit Mailbox Request */
+#define CAN_TI0R_RTR 0x00000002U /*!<Remote Transmission Request */
+#define CAN_TI0R_IDE 0x00000004U /*!<Identifier Extension */
+#define CAN_TI0R_EXID 0x001FFFF8U /*!<Extended Identifier */
+#define CAN_TI0R_STID 0xFFE00000U /*!<Standard Identifier or Extended Identifier */
+
+/****************** Bit definition for CAN_TDT0R register *******************/
+#define CAN_TDT0R_DLC 0x0000000FU /*!<Data Length Code */
+#define CAN_TDT0R_TGT 0x00000100U /*!<Transmit Global Time */
+#define CAN_TDT0R_TIME 0xFFFF0000U /*!<Message Time Stamp */
+
+/****************** Bit definition for CAN_TDL0R register *******************/
+#define CAN_TDL0R_DATA0 0x000000FFU /*!<Data byte 0 */
+#define CAN_TDL0R_DATA1 0x0000FF00U /*!<Data byte 1 */
+#define CAN_TDL0R_DATA2 0x00FF0000U /*!<Data byte 2 */
+#define CAN_TDL0R_DATA3 0xFF000000U /*!<Data byte 3 */
+
+/****************** Bit definition for CAN_TDH0R register *******************/
+#define CAN_TDH0R_DATA4 0x000000FFU /*!<Data byte 4 */
+#define CAN_TDH0R_DATA5 0x0000FF00U /*!<Data byte 5 */
+#define CAN_TDH0R_DATA6 0x00FF0000U /*!<Data byte 6 */
+#define CAN_TDH0R_DATA7 0xFF000000U /*!<Data byte 7 */
+
+/******************* Bit definition for CAN_TI1R register *******************/
+#define CAN_TI1R_TXRQ 0x00000001U /*!<Transmit Mailbox Request */
+#define CAN_TI1R_RTR 0x00000002U /*!<Remote Transmission Request */
+#define CAN_TI1R_IDE 0x00000004U /*!<Identifier Extension */
+#define CAN_TI1R_EXID 0x001FFFF8U /*!<Extended Identifier */
+#define CAN_TI1R_STID 0xFFE00000U /*!<Standard Identifier or Extended Identifier */
+
+/******************* Bit definition for CAN_TDT1R register ******************/
+#define CAN_TDT1R_DLC 0x0000000FU /*!<Data Length Code */
+#define CAN_TDT1R_TGT 0x00000100U /*!<Transmit Global Time */
+#define CAN_TDT1R_TIME 0xFFFF0000U /*!<Message Time Stamp */
+
+/******************* Bit definition for CAN_TDL1R register ******************/
+#define CAN_TDL1R_DATA0 0x000000FFU /*!<Data byte 0 */
+#define CAN_TDL1R_DATA1 0x0000FF00U /*!<Data byte 1 */
+#define CAN_TDL1R_DATA2 0x00FF0000U /*!<Data byte 2 */
+#define CAN_TDL1R_DATA3 0xFF000000U /*!<Data byte 3 */
+
+/******************* Bit definition for CAN_TDH1R register ******************/
+#define CAN_TDH1R_DATA4 0x000000FFU /*!<Data byte 4 */
+#define CAN_TDH1R_DATA5 0x0000FF00U /*!<Data byte 5 */
+#define CAN_TDH1R_DATA6 0x00FF0000U /*!<Data byte 6 */
+#define CAN_TDH1R_DATA7 0xFF000000U /*!<Data byte 7 */
+
+/******************* Bit definition for CAN_TI2R register *******************/
+#define CAN_TI2R_TXRQ 0x00000001U /*!<Transmit Mailbox Request */
+#define CAN_TI2R_RTR 0x00000002U /*!<Remote Transmission Request */
+#define CAN_TI2R_IDE 0x00000004U /*!<Identifier Extension */
+#define CAN_TI2R_EXID 0x001FFFF8U /*!<Extended identifier */
+#define CAN_TI2R_STID 0xFFE00000U /*!<Standard Identifier or Extended Identifier */
+
+/******************* Bit definition for CAN_TDT2R register ******************/
+#define CAN_TDT2R_DLC 0x0000000FU /*!<Data Length Code */
+#define CAN_TDT2R_TGT 0x00000100U /*!<Transmit Global Time */
+#define CAN_TDT2R_TIME 0xFFFF0000U /*!<Message Time Stamp */
+
+/******************* Bit definition for CAN_TDL2R register ******************/
+#define CAN_TDL2R_DATA0 0x000000FFU /*!<Data byte 0 */
+#define CAN_TDL2R_DATA1 0x0000FF00U /*!<Data byte 1 */
+#define CAN_TDL2R_DATA2 0x00FF0000U /*!<Data byte 2 */
+#define CAN_TDL2R_DATA3 0xFF000000U /*!<Data byte 3 */
+
+/******************* Bit definition for CAN_TDH2R register ******************/
+#define CAN_TDH2R_DATA4 0x000000FFU /*!<Data byte 4 */
+#define CAN_TDH2R_DATA5 0x0000FF00U /*!<Data byte 5 */
+#define CAN_TDH2R_DATA6 0x00FF0000U /*!<Data byte 6 */
+#define CAN_TDH2R_DATA7 0xFF000000U /*!<Data byte 7 */
+
+/******************* Bit definition for CAN_RI0R register *******************/
+#define CAN_RI0R_RTR 0x00000002U /*!<Remote Transmission Request */
+#define CAN_RI0R_IDE 0x00000004U /*!<Identifier Extension */
+#define CAN_RI0R_EXID 0x001FFFF8U /*!<Extended Identifier */
+#define CAN_RI0R_STID 0xFFE00000U /*!<Standard Identifier or Extended Identifier */
+
+/******************* Bit definition for CAN_RDT0R register ******************/
+#define CAN_RDT0R_DLC 0x0000000FU /*!<Data Length Code */
+#define CAN_RDT0R_FMI 0x0000FF00U /*!<Filter Match Index */
+#define CAN_RDT0R_TIME 0xFFFF0000U /*!<Message Time Stamp */
+
+/******************* Bit definition for CAN_RDL0R register ******************/
+#define CAN_RDL0R_DATA0 0x000000FFU /*!<Data byte 0 */
+#define CAN_RDL0R_DATA1 0x0000FF00U /*!<Data byte 1 */
+#define CAN_RDL0R_DATA2 0x00FF0000U /*!<Data byte 2 */
+#define CAN_RDL0R_DATA3 0xFF000000U /*!<Data byte 3 */
+
+/******************* Bit definition for CAN_RDH0R register ******************/
+#define CAN_RDH0R_DATA4 0x000000FFU /*!<Data byte 4 */
+#define CAN_RDH0R_DATA5 0x0000FF00U /*!<Data byte 5 */
+#define CAN_RDH0R_DATA6 0x00FF0000U /*!<Data byte 6 */
+#define CAN_RDH0R_DATA7 0xFF000000U /*!<Data byte 7 */
+
+/******************* Bit definition for CAN_RI1R register *******************/
+#define CAN_RI1R_RTR 0x00000002U /*!<Remote Transmission Request */
+#define CAN_RI1R_IDE 0x00000004U /*!<Identifier Extension */
+#define CAN_RI1R_EXID 0x001FFFF8U /*!<Extended identifier */
+#define CAN_RI1R_STID 0xFFE00000U /*!<Standard Identifier or Extended Identifier */
+
+/******************* Bit definition for CAN_RDT1R register ******************/
+#define CAN_RDT1R_DLC 0x0000000FU /*!<Data Length Code */
+#define CAN_RDT1R_FMI 0x0000FF00U /*!<Filter Match Index */
+#define CAN_RDT1R_TIME 0xFFFF0000U /*!<Message Time Stamp */
+
+/******************* Bit definition for CAN_RDL1R register ******************/
+#define CAN_RDL1R_DATA0 0x000000FFU /*!<Data byte 0 */
+#define CAN_RDL1R_DATA1 0x0000FF00U /*!<Data byte 1 */
+#define CAN_RDL1R_DATA2 0x00FF0000U /*!<Data byte 2 */
+#define CAN_RDL1R_DATA3 0xFF000000U /*!<Data byte 3 */
+
+/******************* Bit definition for CAN_RDH1R register ******************/
+#define CAN_RDH1R_DATA4 0x000000FFU /*!<Data byte 4 */
+#define CAN_RDH1R_DATA5 0x0000FF00U /*!<Data byte 5 */
+#define CAN_RDH1R_DATA6 0x00FF0000U /*!<Data byte 6 */
+#define CAN_RDH1R_DATA7 0xFF000000U /*!<Data byte 7 */
+
+/*!<CAN filter registers */
+/******************* Bit definition for CAN_FMR register ********************/
+#define CAN_FMR_FINIT 0x01U /*!<Filter Init Mode */
+#define CAN_FMR_CAN2SB 0x00003F00U /*!<CAN2 start bank */
+
+/******************* Bit definition for CAN_FM1R register *******************/
+#define CAN_FM1R_FBM 0x0FFFFFFFU /*!<Filter Mode */
+#define CAN_FM1R_FBM0 0x00000001U /*!<Filter Init Mode bit 0 */
+#define CAN_FM1R_FBM1 0x00000002U /*!<Filter Init Mode bit 1 */
+#define CAN_FM1R_FBM2 0x00000004U /*!<Filter Init Mode bit 2 */
+#define CAN_FM1R_FBM3 0x00000008U /*!<Filter Init Mode bit 3 */
+#define CAN_FM1R_FBM4 0x00000010U /*!<Filter Init Mode bit 4 */
+#define CAN_FM1R_FBM5 0x00000020U /*!<Filter Init Mode bit 5 */
+#define CAN_FM1R_FBM6 0x00000040U /*!<Filter Init Mode bit 6 */
+#define CAN_FM1R_FBM7 0x00000080U /*!<Filter Init Mode bit 7 */
+#define CAN_FM1R_FBM8 0x00000100U /*!<Filter Init Mode bit 8 */
+#define CAN_FM1R_FBM9 0x00000200U /*!<Filter Init Mode bit 9 */
+#define CAN_FM1R_FBM10 0x00000400U /*!<Filter Init Mode bit 10 */
+#define CAN_FM1R_FBM11 0x00000800U /*!<Filter Init Mode bit 11 */
+#define CAN_FM1R_FBM12 0x00001000U /*!<Filter Init Mode bit 12 */
+#define CAN_FM1R_FBM13 0x00002000U /*!<Filter Init Mode bit 13 */
+#define CAN_FM1R_FBM14 0x00004000U /*!<Filter Init Mode bit 14 */
+#define CAN_FM1R_FBM15 0x00008000U /*!<Filter Init Mode bit 15 */
+#define CAN_FM1R_FBM16 0x00010000U /*!<Filter Init Mode bit 16 */
+#define CAN_FM1R_FBM17 0x00020000U /*!<Filter Init Mode bit 17 */
+#define CAN_FM1R_FBM18 0x00040000U /*!<Filter Init Mode bit 18 */
+#define CAN_FM1R_FBM19 0x00080000U /*!<Filter Init Mode bit 19 */
+#define CAN_FM1R_FBM20 0x00100000U /*!<Filter Init Mode bit 20 */
+#define CAN_FM1R_FBM21 0x00200000U /*!<Filter Init Mode bit 21 */
+#define CAN_FM1R_FBM22 0x00400000U /*!<Filter Init Mode bit 22 */
+#define CAN_FM1R_FBM23 0x00800000U /*!<Filter Init Mode bit 23 */
+#define CAN_FM1R_FBM24 0x01000000U /*!<Filter Init Mode bit 24 */
+#define CAN_FM1R_FBM25 0x02000000U /*!<Filter Init Mode bit 25 */
+#define CAN_FM1R_FBM26 0x04000000U /*!<Filter Init Mode bit 26 */
+#define CAN_FM1R_FBM27 0x08000000U /*!<Filter Init Mode bit 27 */
+
+/******************* Bit definition for CAN_FS1R register *******************/
+#define CAN_FS1R_FSC 0x0FFFFFFFU /*!<Filter Scale Configuration */
+#define CAN_FS1R_FSC0 0x00000001U /*!<Filter Scale Configuration bit 0 */
+#define CAN_FS1R_FSC1 0x00000002U /*!<Filter Scale Configuration bit 1 */
+#define CAN_FS1R_FSC2 0x00000004U /*!<Filter Scale Configuration bit 2 */
+#define CAN_FS1R_FSC3 0x00000008U /*!<Filter Scale Configuration bit 3 */
+#define CAN_FS1R_FSC4 0x00000010U /*!<Filter Scale Configuration bit 4 */
+#define CAN_FS1R_FSC5 0x00000020U /*!<Filter Scale Configuration bit 5 */
+#define CAN_FS1R_FSC6 0x00000040U /*!<Filter Scale Configuration bit 6 */
+#define CAN_FS1R_FSC7 0x00000080U /*!<Filter Scale Configuration bit 7 */
+#define CAN_FS1R_FSC8 0x00000100U /*!<Filter Scale Configuration bit 8 */
+#define CAN_FS1R_FSC9 0x00000200U /*!<Filter Scale Configuration bit 9 */
+#define CAN_FS1R_FSC10 0x00000400U /*!<Filter Scale Configuration bit 10 */
+#define CAN_FS1R_FSC11 0x00000800U /*!<Filter Scale Configuration bit 11 */
+#define CAN_FS1R_FSC12 0x00001000U /*!<Filter Scale Configuration bit 12 */
+#define CAN_FS1R_FSC13 0x00002000U /*!<Filter Scale Configuration bit 13 */
+#define CAN_FS1R_FSC14 0x00004000U /*!<Filter Scale Configuration bit 14 */
+#define CAN_FS1R_FSC15 0x00008000U /*!<Filter Scale Configuration bit 15 */
+#define CAN_FS1R_FSC16 0x00010000U /*!<Filter Scale Configuration bit 16 */
+#define CAN_FS1R_FSC17 0x00020000U /*!<Filter Scale Configuration bit 17 */
+#define CAN_FS1R_FSC18 0x00040000U /*!<Filter Scale Configuration bit 18 */
+#define CAN_FS1R_FSC19 0x00080000U /*!<Filter Scale Configuration bit 19 */
+#define CAN_FS1R_FSC20 0x00100000U /*!<Filter Scale Configuration bit 20 */
+#define CAN_FS1R_FSC21 0x00200000U /*!<Filter Scale Configuration bit 21 */
+#define CAN_FS1R_FSC22 0x00400000U /*!<Filter Scale Configuration bit 22 */
+#define CAN_FS1R_FSC23 0x00800000U /*!<Filter Scale Configuration bit 23 */
+#define CAN_FS1R_FSC24 0x01000000U /*!<Filter Scale Configuration bit 24 */
+#define CAN_FS1R_FSC25 0x02000000U /*!<Filter Scale Configuration bit 25 */
+#define CAN_FS1R_FSC26 0x04000000U /*!<Filter Scale Configuration bit 26 */
+#define CAN_FS1R_FSC27 0x08000000U /*!<Filter Scale Configuration bit 27 */
+
+/****************** Bit definition for CAN_FFA1R register *******************/
+#define CAN_FFA1R_FFA 0x0FFFFFFFU /*!<Filter FIFO Assignment */
+#define CAN_FFA1R_FFA0 0x00000001U /*!<Filter FIFO Assignment bit 0 */
+#define CAN_FFA1R_FFA1 0x00000002U /*!<Filter FIFO Assignment bit 1 */
+#define CAN_FFA1R_FFA2 0x00000004U /*!<Filter FIFO Assignment bit 2 */
+#define CAN_FFA1R_FFA3 0x00000008U /*!<Filter FIFO Assignment bit 3 */
+#define CAN_FFA1R_FFA4 0x00000010U /*!<Filter FIFO Assignment bit 4 */
+#define CAN_FFA1R_FFA5 0x00000020U /*!<Filter FIFO Assignment bit 5 */
+#define CAN_FFA1R_FFA6 0x00000040U /*!<Filter FIFO Assignment bit 6 */
+#define CAN_FFA1R_FFA7 0x00000080U /*!<Filter FIFO Assignment bit 7 */
+#define CAN_FFA1R_FFA8 0x00000100U /*!<Filter FIFO Assignment bit 8 */
+#define CAN_FFA1R_FFA9 0x00000200U /*!<Filter FIFO Assignment bit 9 */
+#define CAN_FFA1R_FFA10 0x00000400U /*!<Filter FIFO Assignment bit 10 */
+#define CAN_FFA1R_FFA11 0x00000800U /*!<Filter FIFO Assignment bit 11 */
+#define CAN_FFA1R_FFA12 0x00001000U /*!<Filter FIFO Assignment bit 12 */
+#define CAN_FFA1R_FFA13 0x00002000U /*!<Filter FIFO Assignment bit 13 */
+#define CAN_FFA1R_FFA14 0x00004000U /*!<Filter FIFO Assignment bit 14 */
+#define CAN_FFA1R_FFA15 0x00008000U /*!<Filter FIFO Assignment bit 15 */
+#define CAN_FFA1R_FFA16 0x00010000U /*!<Filter FIFO Assignment bit 16 */
+#define CAN_FFA1R_FFA17 0x00020000U /*!<Filter FIFO Assignment bit 17 */
+#define CAN_FFA1R_FFA18 0x00040000U /*!<Filter FIFO Assignment bit 18 */
+#define CAN_FFA1R_FFA19 0x00080000U /*!<Filter FIFO Assignment bit 19 */
+#define CAN_FFA1R_FFA20 0x00100000U /*!<Filter FIFO Assignment bit 20 */
+#define CAN_FFA1R_FFA21 0x00200000U /*!<Filter FIFO Assignment bit 21 */
+#define CAN_FFA1R_FFA22 0x00400000U /*!<Filter FIFO Assignment bit 22 */
+#define CAN_FFA1R_FFA23 0x00800000U /*!<Filter FIFO Assignment bit 23 */
+#define CAN_FFA1R_FFA24 0x01000000U /*!<Filter FIFO Assignment bit 24 */
+#define CAN_FFA1R_FFA25 0x02000000U /*!<Filter FIFO Assignment bit 25 */
+#define CAN_FFA1R_FFA26 0x04000000U /*!<Filter FIFO Assignment bit 26 */
+#define CAN_FFA1R_FFA27 0x08000000U /*!<Filter FIFO Assignment bit 27 */
+
+/******************* Bit definition for CAN_FA1R register *******************/
+#define CAN_FA1R_FACT 0x0FFFFFFFU /*!<Filter Active */
+#define CAN_FA1R_FACT0 0x00000001U /*!<Filter Active bit 0 */
+#define CAN_FA1R_FACT1 0x00000002U /*!<Filter Active bit 1 */
+#define CAN_FA1R_FACT2 0x00000004U /*!<Filter Active bit 2 */
+#define CAN_FA1R_FACT3 0x00000008U /*!<Filter Active bit 3 */
+#define CAN_FA1R_FACT4 0x00000010U /*!<Filter Active bit 4 */
+#define CAN_FA1R_FACT5 0x00000020U /*!<Filter Active bit 5 */
+#define CAN_FA1R_FACT6 0x00000040U /*!<Filter Active bit 6 */
+#define CAN_FA1R_FACT7 0x00000080U /*!<Filter Active bit 7 */
+#define CAN_FA1R_FACT8 0x00000100U /*!<Filter Active bit 8 */
+#define CAN_FA1R_FACT9 0x00000200U /*!<Filter Active bit 9 */
+#define CAN_FA1R_FACT10 0x00000400U /*!<Filter Active bit 10 */
+#define CAN_FA1R_FACT11 0x00000800U /*!<Filter Active bit 11 */
+#define CAN_FA1R_FACT12 0x00001000U /*!<Filter Active bit 12 */
+#define CAN_FA1R_FACT13 0x00002000U /*!<Filter Active bit 13 */
+#define CAN_FA1R_FACT14 0x00004000U /*!<Filter Active bit 14 */
+#define CAN_FA1R_FACT15 0x00008000U /*!<Filter Active bit 15 */
+#define CAN_FA1R_FACT16 0x00010000U /*!<Filter Active bit 16 */
+#define CAN_FA1R_FACT17 0x00020000U /*!<Filter Active bit 17 */
+#define CAN_FA1R_FACT18 0x00040000U /*!<Filter Active bit 18 */
+#define CAN_FA1R_FACT19 0x00080000U /*!<Filter Active bit 19 */
+#define CAN_FA1R_FACT20 0x00100000U /*!<Filter Active bit 20 */
+#define CAN_FA1R_FACT21 0x00200000U /*!<Filter Active bit 21 */
+#define CAN_FA1R_FACT22 0x00400000U /*!<Filter Active bit 22 */
+#define CAN_FA1R_FACT23 0x00800000U /*!<Filter Active bit 23 */
+#define CAN_FA1R_FACT24 0x01000000U /*!<Filter Active bit 24 */
+#define CAN_FA1R_FACT25 0x02000000U /*!<Filter Active bit 25 */
+#define CAN_FA1R_FACT26 0x04000000U /*!<Filter Active bit 26 */
+#define CAN_FA1R_FACT27 0x08000000U /*!<Filter Active bit 27 */
+
+/******************* Bit definition for CAN_F0R1 register *******************/
+#define CAN_F0R1_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F0R1_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F0R1_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F0R1_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F0R1_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F0R1_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F0R1_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F0R1_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F0R1_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F0R1_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F0R1_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F0R1_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F0R1_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F0R1_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F0R1_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F0R1_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F0R1_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F0R1_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F0R1_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F0R1_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F0R1_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F0R1_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F0R1_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F0R1_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F0R1_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F0R1_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F0R1_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F0R1_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F0R1_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F0R1_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F0R1_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F0R1_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F1R1 register *******************/
+#define CAN_F1R1_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F1R1_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F1R1_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F1R1_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F1R1_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F1R1_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F1R1_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F1R1_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F1R1_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F1R1_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F1R1_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F1R1_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F1R1_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F1R1_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F1R1_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F1R1_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F1R1_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F1R1_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F1R1_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F1R1_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F1R1_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F1R1_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F1R1_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F1R1_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F1R1_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F1R1_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F1R1_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F1R1_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F1R1_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F1R1_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F1R1_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F1R1_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F2R1 register *******************/
+#define CAN_F2R1_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F2R1_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F2R1_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F2R1_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F2R1_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F2R1_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F2R1_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F2R1_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F2R1_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F2R1_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F2R1_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F2R1_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F2R1_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F2R1_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F2R1_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F2R1_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F2R1_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F2R1_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F2R1_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F2R1_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F2R1_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F2R1_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F2R1_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F2R1_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F2R1_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F2R1_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F2R1_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F2R1_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F2R1_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F2R1_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F2R1_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F2R1_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F3R1 register *******************/
+#define CAN_F3R1_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F3R1_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F3R1_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F3R1_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F3R1_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F3R1_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F3R1_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F3R1_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F3R1_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F3R1_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F3R1_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F3R1_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F3R1_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F3R1_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F3R1_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F3R1_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F3R1_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F3R1_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F3R1_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F3R1_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F3R1_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F3R1_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F3R1_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F3R1_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F3R1_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F3R1_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F3R1_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F3R1_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F3R1_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F3R1_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F3R1_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F3R1_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F4R1 register *******************/
+#define CAN_F4R1_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F4R1_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F4R1_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F4R1_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F4R1_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F4R1_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F4R1_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F4R1_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F4R1_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F4R1_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F4R1_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F4R1_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F4R1_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F4R1_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F4R1_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F4R1_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F4R1_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F4R1_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F4R1_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F4R1_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F4R1_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F4R1_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F4R1_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F4R1_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F4R1_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F4R1_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F4R1_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F4R1_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F4R1_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F4R1_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F4R1_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F4R1_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F5R1 register *******************/
+#define CAN_F5R1_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F5R1_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F5R1_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F5R1_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F5R1_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F5R1_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F5R1_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F5R1_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F5R1_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F5R1_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F5R1_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F5R1_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F5R1_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F5R1_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F5R1_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F5R1_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F5R1_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F5R1_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F5R1_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F5R1_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F5R1_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F5R1_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F5R1_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F5R1_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F5R1_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F5R1_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F5R1_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F5R1_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F5R1_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F5R1_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F5R1_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F5R1_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F6R1 register *******************/
+#define CAN_F6R1_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F6R1_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F6R1_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F6R1_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F6R1_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F6R1_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F6R1_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F6R1_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F6R1_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F6R1_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F6R1_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F6R1_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F6R1_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F6R1_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F6R1_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F6R1_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F6R1_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F6R1_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F6R1_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F6R1_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F6R1_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F6R1_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F6R1_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F6R1_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F6R1_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F6R1_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F6R1_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F6R1_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F6R1_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F6R1_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F6R1_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F6R1_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F7R1 register *******************/
+#define CAN_F7R1_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F7R1_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F7R1_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F7R1_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F7R1_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F7R1_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F7R1_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F7R1_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F7R1_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F7R1_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F7R1_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F7R1_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F7R1_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F7R1_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F7R1_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F7R1_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F7R1_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F7R1_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F7R1_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F7R1_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F7R1_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F7R1_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F7R1_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F7R1_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F7R1_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F7R1_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F7R1_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F7R1_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F7R1_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F7R1_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F7R1_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F7R1_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F8R1 register *******************/
+#define CAN_F8R1_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F8R1_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F8R1_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F8R1_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F8R1_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F8R1_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F8R1_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F8R1_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F8R1_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F8R1_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F8R1_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F8R1_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F8R1_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F8R1_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F8R1_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F8R1_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F8R1_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F8R1_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F8R1_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F8R1_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F8R1_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F8R1_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F8R1_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F8R1_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F8R1_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F8R1_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F8R1_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F8R1_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F8R1_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F8R1_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F8R1_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F8R1_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F9R1 register *******************/
+#define CAN_F9R1_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F9R1_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F9R1_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F9R1_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F9R1_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F9R1_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F9R1_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F9R1_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F9R1_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F9R1_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F9R1_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F9R1_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F9R1_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F9R1_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F9R1_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F9R1_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F9R1_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F9R1_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F9R1_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F9R1_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F9R1_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F9R1_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F9R1_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F9R1_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F9R1_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F9R1_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F9R1_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F9R1_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F9R1_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F9R1_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F9R1_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F9R1_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F10R1 register ******************/
+#define CAN_F10R1_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F10R1_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F10R1_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F10R1_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F10R1_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F10R1_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F10R1_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F10R1_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F10R1_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F10R1_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F10R1_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F10R1_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F10R1_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F10R1_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F10R1_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F10R1_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F10R1_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F10R1_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F10R1_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F10R1_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F10R1_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F10R1_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F10R1_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F10R1_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F10R1_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F10R1_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F10R1_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F10R1_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F10R1_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F10R1_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F10R1_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F10R1_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F11R1 register ******************/
+#define CAN_F11R1_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F11R1_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F11R1_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F11R1_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F11R1_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F11R1_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F11R1_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F11R1_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F11R1_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F11R1_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F11R1_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F11R1_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F11R1_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F11R1_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F11R1_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F11R1_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F11R1_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F11R1_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F11R1_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F11R1_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F11R1_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F11R1_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F11R1_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F11R1_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F11R1_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F11R1_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F11R1_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F11R1_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F11R1_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F11R1_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F11R1_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F11R1_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F12R1 register ******************/
+#define CAN_F12R1_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F12R1_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F12R1_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F12R1_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F12R1_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F12R1_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F12R1_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F12R1_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F12R1_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F12R1_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F12R1_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F12R1_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F12R1_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F12R1_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F12R1_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F12R1_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F12R1_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F12R1_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F12R1_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F12R1_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F12R1_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F12R1_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F12R1_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F12R1_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F12R1_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F12R1_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F12R1_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F12R1_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F12R1_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F12R1_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F12R1_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F12R1_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F13R1 register ******************/
+#define CAN_F13R1_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F13R1_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F13R1_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F13R1_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F13R1_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F13R1_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F13R1_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F13R1_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F13R1_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F13R1_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F13R1_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F13R1_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F13R1_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F13R1_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F13R1_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F13R1_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F13R1_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F13R1_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F13R1_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F13R1_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F13R1_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F13R1_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F13R1_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F13R1_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F13R1_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F13R1_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F13R1_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F13R1_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F13R1_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F13R1_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F13R1_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F13R1_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F0R2 register *******************/
+#define CAN_F0R2_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F0R2_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F0R2_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F0R2_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F0R2_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F0R2_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F0R2_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F0R2_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F0R2_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F0R2_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F0R2_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F0R2_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F0R2_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F0R2_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F0R2_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F0R2_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F0R2_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F0R2_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F0R2_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F0R2_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F0R2_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F0R2_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F0R2_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F0R2_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F0R2_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F0R2_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F0R2_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F0R2_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F0R2_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F0R2_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F0R2_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F0R2_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F1R2 register *******************/
+#define CAN_F1R2_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F1R2_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F1R2_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F1R2_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F1R2_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F1R2_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F1R2_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F1R2_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F1R2_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F1R2_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F1R2_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F1R2_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F1R2_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F1R2_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F1R2_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F1R2_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F1R2_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F1R2_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F1R2_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F1R2_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F1R2_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F1R2_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F1R2_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F1R2_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F1R2_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F1R2_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F1R2_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F1R2_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F1R2_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F1R2_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F1R2_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F1R2_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F2R2 register *******************/
+#define CAN_F2R2_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F2R2_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F2R2_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F2R2_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F2R2_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F2R2_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F2R2_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F2R2_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F2R2_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F2R2_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F2R2_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F2R2_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F2R2_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F2R2_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F2R2_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F2R2_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F2R2_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F2R2_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F2R2_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F2R2_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F2R2_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F2R2_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F2R2_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F2R2_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F2R2_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F2R2_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F2R2_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F2R2_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F2R2_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F2R2_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F2R2_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F2R2_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F3R2 register *******************/
+#define CAN_F3R2_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F3R2_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F3R2_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F3R2_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F3R2_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F3R2_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F3R2_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F3R2_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F3R2_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F3R2_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F3R2_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F3R2_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F3R2_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F3R2_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F3R2_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F3R2_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F3R2_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F3R2_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F3R2_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F3R2_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F3R2_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F3R2_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F3R2_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F3R2_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F3R2_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F3R2_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F3R2_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F3R2_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F3R2_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F3R2_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F3R2_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F3R2_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F4R2 register *******************/
+#define CAN_F4R2_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F4R2_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F4R2_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F4R2_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F4R2_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F4R2_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F4R2_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F4R2_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F4R2_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F4R2_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F4R2_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F4R2_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F4R2_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F4R2_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F4R2_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F4R2_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F4R2_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F4R2_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F4R2_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F4R2_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F4R2_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F4R2_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F4R2_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F4R2_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F4R2_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F4R2_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F4R2_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F4R2_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F4R2_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F4R2_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F4R2_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F4R2_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F5R2 register *******************/
+#define CAN_F5R2_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F5R2_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F5R2_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F5R2_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F5R2_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F5R2_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F5R2_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F5R2_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F5R2_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F5R2_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F5R2_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F5R2_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F5R2_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F5R2_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F5R2_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F5R2_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F5R2_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F5R2_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F5R2_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F5R2_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F5R2_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F5R2_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F5R2_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F5R2_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F5R2_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F5R2_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F5R2_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F5R2_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F5R2_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F5R2_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F5R2_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F5R2_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F6R2 register *******************/
+#define CAN_F6R2_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F6R2_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F6R2_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F6R2_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F6R2_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F6R2_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F6R2_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F6R2_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F6R2_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F6R2_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F6R2_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F6R2_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F6R2_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F6R2_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F6R2_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F6R2_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F6R2_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F6R2_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F6R2_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F6R2_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F6R2_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F6R2_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F6R2_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F6R2_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F6R2_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F6R2_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F6R2_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F6R2_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F6R2_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F6R2_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F6R2_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F6R2_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F7R2 register *******************/
+#define CAN_F7R2_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F7R2_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F7R2_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F7R2_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F7R2_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F7R2_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F7R2_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F7R2_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F7R2_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F7R2_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F7R2_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F7R2_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F7R2_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F7R2_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F7R2_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F7R2_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F7R2_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F7R2_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F7R2_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F7R2_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F7R2_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F7R2_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F7R2_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F7R2_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F7R2_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F7R2_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F7R2_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F7R2_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F7R2_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F7R2_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F7R2_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F7R2_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F8R2 register *******************/
+#define CAN_F8R2_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F8R2_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F8R2_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F8R2_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F8R2_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F8R2_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F8R2_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F8R2_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F8R2_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F8R2_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F8R2_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F8R2_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F8R2_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F8R2_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F8R2_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F8R2_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F8R2_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F8R2_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F8R2_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F8R2_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F8R2_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F8R2_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F8R2_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F8R2_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F8R2_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F8R2_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F8R2_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F8R2_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F8R2_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F8R2_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F8R2_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F8R2_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F9R2 register *******************/
+#define CAN_F9R2_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F9R2_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F9R2_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F9R2_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F9R2_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F9R2_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F9R2_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F9R2_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F9R2_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F9R2_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F9R2_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F9R2_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F9R2_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F9R2_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F9R2_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F9R2_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F9R2_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F9R2_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F9R2_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F9R2_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F9R2_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F9R2_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F9R2_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F9R2_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F9R2_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F9R2_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F9R2_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F9R2_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F9R2_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F9R2_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F9R2_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F9R2_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F10R2 register ******************/
+#define CAN_F10R2_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F10R2_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F10R2_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F10R2_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F10R2_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F10R2_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F10R2_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F10R2_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F10R2_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F10R2_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F10R2_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F10R2_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F10R2_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F10R2_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F10R2_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F10R2_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F10R2_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F10R2_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F10R2_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F10R2_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F10R2_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F10R2_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F10R2_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F10R2_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F10R2_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F10R2_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F10R2_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F10R2_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F10R2_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F10R2_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F10R2_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F10R2_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F11R2 register ******************/
+#define CAN_F11R2_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F11R2_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F11R2_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F11R2_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F11R2_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F11R2_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F11R2_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F11R2_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F11R2_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F11R2_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F11R2_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F11R2_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F11R2_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F11R2_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F11R2_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F11R2_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F11R2_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F11R2_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F11R2_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F11R2_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F11R2_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F11R2_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F11R2_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F11R2_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F11R2_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F11R2_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F11R2_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F11R2_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F11R2_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F11R2_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F11R2_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F11R2_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F12R2 register ******************/
+#define CAN_F12R2_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F12R2_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F12R2_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F12R2_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F12R2_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F12R2_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F12R2_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F12R2_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F12R2_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F12R2_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F12R2_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F12R2_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F12R2_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F12R2_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F12R2_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F12R2_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F12R2_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F12R2_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F12R2_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F12R2_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F12R2_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F12R2_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F12R2_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F12R2_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F12R2_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F12R2_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F12R2_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F12R2_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F12R2_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F12R2_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F12R2_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F12R2_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F13R2 register ******************/
+#define CAN_F13R2_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F13R2_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F13R2_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F13R2_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F13R2_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F13R2_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F13R2_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F13R2_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F13R2_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F13R2_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F13R2_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F13R2_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F13R2_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F13R2_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F13R2_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F13R2_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F13R2_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F13R2_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F13R2_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F13R2_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F13R2_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F13R2_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F13R2_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F13R2_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F13R2_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F13R2_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F13R2_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F13R2_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F13R2_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F13R2_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F13R2_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F13R2_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************************************************************************/
+/* */
+/* CRC calculation unit */
+/* */
+/******************************************************************************/
+/******************* Bit definition for CRC_DR register *********************/
+#define CRC_DR_DR 0xFFFFFFFFU /*!< Data register bits */
+
+
+/******************* Bit definition for CRC_IDR register ********************/
+#define CRC_IDR_IDR 0xFFU /*!< General-purpose 8-bit data register bits */
+
+
+/******************** Bit definition for CRC_CR register ********************/
+#define CRC_CR_RESET 0x01U /*!< RESET bit */
+
+
+/******************************************************************************/
+/* */
+/* Digital to Analog Converter */
+/* */
+/******************************************************************************/
+/******************** Bit definition for DAC_CR register ********************/
+#define DAC_CR_EN1 0x00000001U /*!<DAC channel1 enable */
+#define DAC_CR_BOFF1 0x00000002U /*!<DAC channel1 output buffer disable */
+#define DAC_CR_TEN1 0x00000004U /*!<DAC channel1 Trigger enable */
+
+#define DAC_CR_TSEL1 0x00000038U /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */
+#define DAC_CR_TSEL1_0 0x00000008U /*!<Bit 0 */
+#define DAC_CR_TSEL1_1 0x00000010U /*!<Bit 1 */
+#define DAC_CR_TSEL1_2 0x00000020U /*!<Bit 2 */
+
+#define DAC_CR_WAVE1 0x000000C0U /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
+#define DAC_CR_WAVE1_0 0x00000040U /*!<Bit 0 */
+#define DAC_CR_WAVE1_1 0x00000080U /*!<Bit 1 */
+
+#define DAC_CR_MAMP1 0x00000F00U /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
+#define DAC_CR_MAMP1_0 0x00000100U /*!<Bit 0 */
+#define DAC_CR_MAMP1_1 0x00000200U /*!<Bit 1 */
+#define DAC_CR_MAMP1_2 0x00000400U /*!<Bit 2 */
+#define DAC_CR_MAMP1_3 0x00000800U /*!<Bit 3 */
+
+#define DAC_CR_DMAEN1 0x00001000U /*!<DAC channel1 DMA enable */
+#define DAC_CR_DMAUDRIE1 0x00002000U /*!<DAC channel1 DMA underrun interrupt enable*/
+#define DAC_CR_EN2 0x00010000U /*!<DAC channel2 enable */
+#define DAC_CR_BOFF2 0x00020000U /*!<DAC channel2 output buffer disable */
+#define DAC_CR_TEN2 0x00040000U /*!<DAC channel2 Trigger enable */
+
+#define DAC_CR_TSEL2 0x00380000U /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */
+#define DAC_CR_TSEL2_0 0x00080000U /*!<Bit 0 */
+#define DAC_CR_TSEL2_1 0x00100000U /*!<Bit 1 */
+#define DAC_CR_TSEL2_2 0x00200000U /*!<Bit 2 */
+
+#define DAC_CR_WAVE2 0x00C00000U /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
+#define DAC_CR_WAVE2_0 0x00400000U /*!<Bit 0 */
+#define DAC_CR_WAVE2_1 0x00800000U /*!<Bit 1 */
+
+#define DAC_CR_MAMP2 0x0F000000U /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
+#define DAC_CR_MAMP2_0 0x01000000U /*!<Bit 0 */
+#define DAC_CR_MAMP2_1 0x02000000U /*!<Bit 1 */
+#define DAC_CR_MAMP2_2 0x04000000U /*!<Bit 2 */
+#define DAC_CR_MAMP2_3 0x08000000U /*!<Bit 3 */
+
+#define DAC_CR_DMAEN2 0x10000000U /*!<DAC channel2 DMA enabled */
+#define DAC_CR_DMAUDRIE2 0x20000000U /*!<DAC channel2 DMA underrun interrupt enable*/
+
+/***************** Bit definition for DAC_SWTRIGR register ******************/
+#define DAC_SWTRIGR_SWTRIG1 0x01U /*!<DAC channel1 software trigger */
+#define DAC_SWTRIGR_SWTRIG2 0x02U /*!<DAC channel2 software trigger */
+
+/***************** Bit definition for DAC_DHR12R1 register ******************/
+#define DAC_DHR12R1_DACC1DHR 0x0FFFU /*!<DAC channel1 12-bit Right aligned data */
+
+/***************** Bit definition for DAC_DHR12L1 register ******************/
+#define DAC_DHR12L1_DACC1DHR 0xFFF0U /*!<DAC channel1 12-bit Left aligned data */
+
+/****************** Bit definition for DAC_DHR8R1 register ******************/
+#define DAC_DHR8R1_DACC1DHR 0xFFU /*!<DAC channel1 8-bit Right aligned data */
+
+/***************** Bit definition for DAC_DHR12R2 register ******************/
+#define DAC_DHR12R2_DACC2DHR 0x0FFFU /*!<DAC channel2 12-bit Right aligned data */
+
+/***************** Bit definition for DAC_DHR12L2 register ******************/
+#define DAC_DHR12L2_DACC2DHR 0xFFF0U /*!<DAC channel2 12-bit Left aligned data */
+
+/****************** Bit definition for DAC_DHR8R2 register ******************/
+#define DAC_DHR8R2_DACC2DHR 0xFFU /*!<DAC channel2 8-bit Right aligned data */
+
+/***************** Bit definition for DAC_DHR12RD register ******************/
+#define DAC_DHR12RD_DACC1DHR 0x00000FFFU /*!<DAC channel1 12-bit Right aligned data */
+#define DAC_DHR12RD_DACC2DHR 0x0FFF0000U /*!<DAC channel2 12-bit Right aligned data */
+
+/***************** Bit definition for DAC_DHR12LD register ******************/
+#define DAC_DHR12LD_DACC1DHR 0x0000FFF0U /*!<DAC channel1 12-bit Left aligned data */
+#define DAC_DHR12LD_DACC2DHR 0xFFF00000U /*!<DAC channel2 12-bit Left aligned data */
+
+/****************** Bit definition for DAC_DHR8RD register ******************/
+#define DAC_DHR8RD_DACC1DHR 0x00FFU /*!<DAC channel1 8-bit Right aligned data */
+#define DAC_DHR8RD_DACC2DHR 0xFF00U /*!<DAC channel2 8-bit Right aligned data */
+
+/******************* Bit definition for DAC_DOR1 register *******************/
+#define DAC_DOR1_DACC1DOR 0x0FFFU /*!<DAC channel1 data output */
+
+/******************* Bit definition for DAC_DOR2 register *******************/
+#define DAC_DOR2_DACC2DOR 0x0FFFU /*!<DAC channel2 data output */
+
+/******************** Bit definition for DAC_SR register ********************/
+#define DAC_SR_DMAUDR1 0x00002000U /*!<DAC channel1 DMA underrun flag */
+#define DAC_SR_DMAUDR2 0x20000000U /*!<DAC channel2 DMA underrun flag */
+
+/******************************************************************************/
+/* */
+/* Debug MCU */
+/* */
+/******************************************************************************/
+
+/******************************************************************************/
+/* */
+/* DCMI */
+/* */
+/******************************************************************************/
+/******************** Bits definition for DCMI_CR register ******************/
+#define DCMI_CR_CAPTURE 0x00000001U
+#define DCMI_CR_CM 0x00000002U
+#define DCMI_CR_CROP 0x00000004U
+#define DCMI_CR_JPEG 0x00000008U
+#define DCMI_CR_ESS 0x00000010U
+#define DCMI_CR_PCKPOL 0x00000020U
+#define DCMI_CR_HSPOL 0x00000040U
+#define DCMI_CR_VSPOL 0x00000080U
+#define DCMI_CR_FCRC_0 0x00000100U
+#define DCMI_CR_FCRC_1 0x00000200U
+#define DCMI_CR_EDM_0 0x00000400U
+#define DCMI_CR_EDM_1 0x00000800U
+#define DCMI_CR_CRE 0x00001000U
+#define DCMI_CR_ENABLE 0x00004000U
+
+/******************** Bits definition for DCMI_SR register ******************/
+#define DCMI_SR_HSYNC 0x00000001U
+#define DCMI_SR_VSYNC 0x00000002U
+#define DCMI_SR_FNE 0x00000004U
+
+/******************** Bits definition for DCMI_RIS register *****************/
+#define DCMI_RIS_FRAME_RIS 0x00000001U
+#define DCMI_RIS_OVR_RIS 0x00000002U
+#define DCMI_RIS_ERR_RIS 0x00000004U
+#define DCMI_RIS_VSYNC_RIS 0x00000008U
+#define DCMI_RIS_LINE_RIS 0x00000010U
+/* Legacy defines */
+#define DCMI_RISR_FRAME_RIS DCMI_RIS_FRAME_RIS
+#define DCMI_RISR_OVR_RIS DCMI_RIS_OVR_RIS
+#define DCMI_RISR_ERR_RIS DCMI_RIS_ERR_RIS
+#define DCMI_RISR_VSYNC_RIS DCMI_RIS_VSYNC_RIS
+#define DCMI_RISR_LINE_RIS DCMI_RIS_LINE_RIS
+#define DCMI_RISR_OVF_RIS DCMI_RIS_OVR_RIS
+
+/******************** Bits definition for DCMI_IER register *****************/
+#define DCMI_IER_FRAME_IE 0x00000001U
+#define DCMI_IER_OVR_IE 0x00000002U
+#define DCMI_IER_ERR_IE 0x00000004U
+#define DCMI_IER_VSYNC_IE 0x00000008U
+#define DCMI_IER_LINE_IE 0x00000010U
+/* Legacy defines */
+#define DCMI_IER_OVF_IE DCMI_IER_OVR_IE
+
+/******************** Bits definition for DCMI_MIS register *****************/
+#define DCMI_MIS_FRAME_MIS 0x00000001U
+#define DCMI_MIS_OVR_MIS 0x00000002U
+#define DCMI_MIS_ERR_MIS 0x00000004U
+#define DCMI_MIS_VSYNC_MIS 0x00000008U
+#define DCMI_MIS_LINE_MIS 0x00000010U
+
+/* Legacy defines */
+#define DCMI_MISR_FRAME_MIS DCMI_MIS_FRAME_MIS
+#define DCMI_MISR_OVF_MIS DCMI_MIS_OVR_MIS
+#define DCMI_MISR_ERR_MIS DCMI_MIS_ERR_MIS
+#define DCMI_MISR_VSYNC_MIS DCMI_MIS_VSYNC_MIS
+#define DCMI_MISR_LINE_MIS DCMI_MIS_LINE_MIS
+
+/******************** Bits definition for DCMI_ICR register *****************/
+#define DCMI_ICR_FRAME_ISC 0x00000001U
+#define DCMI_ICR_OVR_ISC 0x00000002U
+#define DCMI_ICR_ERR_ISC 0x00000004U
+#define DCMI_ICR_VSYNC_ISC 0x00000008U
+#define DCMI_ICR_LINE_ISC 0x00000010U
+
+/* Legacy defines */
+#define DCMI_ICR_OVF_ISC DCMI_ICR_OVR_ISC
+
+/******************** Bits definition for DCMI_ESCR register ******************/
+#define DCMI_ESCR_FSC 0x000000FFU
+#define DCMI_ESCR_LSC 0x0000FF00U
+#define DCMI_ESCR_LEC 0x00FF0000U
+#define DCMI_ESCR_FEC 0xFF000000U
+
+/******************** Bits definition for DCMI_ESUR register ******************/
+#define DCMI_ESUR_FSU 0x000000FFU
+#define DCMI_ESUR_LSU 0x0000FF00U
+#define DCMI_ESUR_LEU 0x00FF0000U
+#define DCMI_ESUR_FEU 0xFF000000U
+
+/******************** Bits definition for DCMI_CWSTRT register ******************/
+#define DCMI_CWSTRT_HOFFCNT 0x00003FFFU
+#define DCMI_CWSTRT_VST 0x1FFF0000U
+
+/******************** Bits definition for DCMI_CWSIZE register ******************/
+#define DCMI_CWSIZE_CAPCNT 0x00003FFFU
+#define DCMI_CWSIZE_VLINE 0x3FFF0000U
+
+/******************** Bits definition for DCMI_DR register ******************/
+#define DCMI_DR_BYTE0 0x000000FFU
+#define DCMI_DR_BYTE1 0x0000FF00U
+#define DCMI_DR_BYTE2 0x00FF0000U
+#define DCMI_DR_BYTE3 0xFF000000U
+
+/******************************************************************************/
+/* */
+/* DMA Controller */
+/* */
+/******************************************************************************/
+/******************** Bits definition for DMA_SxCR register *****************/
+#define DMA_SxCR_CHSEL 0x0E000000U
+#define DMA_SxCR_CHSEL_0 0x02000000U
+#define DMA_SxCR_CHSEL_1 0x04000000U
+#define DMA_SxCR_CHSEL_2 0x08000000U
+#define DMA_SxCR_MBURST 0x01800000U
+#define DMA_SxCR_MBURST_0 0x00800000U
+#define DMA_SxCR_MBURST_1 0x01000000U
+#define DMA_SxCR_PBURST 0x00600000U
+#define DMA_SxCR_PBURST_0 0x00200000U
+#define DMA_SxCR_PBURST_1 0x00400000U
+#define DMA_SxCR_CT 0x00080000U
+#define DMA_SxCR_DBM 0x00040000U
+#define DMA_SxCR_PL 0x00030000U
+#define DMA_SxCR_PL_0 0x00010000U
+#define DMA_SxCR_PL_1 0x00020000U
+#define DMA_SxCR_PINCOS 0x00008000U
+#define DMA_SxCR_MSIZE 0x00006000U
+#define DMA_SxCR_MSIZE_0 0x00002000U
+#define DMA_SxCR_MSIZE_1 0x00004000U
+#define DMA_SxCR_PSIZE 0x00001800U
+#define DMA_SxCR_PSIZE_0 0x00000800U
+#define DMA_SxCR_PSIZE_1 0x00001000U
+#define DMA_SxCR_MINC 0x00000400U
+#define DMA_SxCR_PINC 0x00000200U
+#define DMA_SxCR_CIRC 0x00000100U
+#define DMA_SxCR_DIR 0x000000C0U
+#define DMA_SxCR_DIR_0 0x00000040U
+#define DMA_SxCR_DIR_1 0x00000080U
+#define DMA_SxCR_PFCTRL 0x00000020U
+#define DMA_SxCR_TCIE 0x00000010U
+#define DMA_SxCR_HTIE 0x00000008U
+#define DMA_SxCR_TEIE 0x00000004U
+#define DMA_SxCR_DMEIE 0x00000002U
+#define DMA_SxCR_EN 0x00000001U
+
+/* Legacy defines */
+#define DMA_SxCR_ACK 0x00100000U
+
+/******************** Bits definition for DMA_SxCNDTR register **************/
+#define DMA_SxNDT 0x0000FFFFU
+#define DMA_SxNDT_0 0x00000001U
+#define DMA_SxNDT_1 0x00000002U
+#define DMA_SxNDT_2 0x00000004U
+#define DMA_SxNDT_3 0x00000008U
+#define DMA_SxNDT_4 0x00000010U
+#define DMA_SxNDT_5 0x00000020U
+#define DMA_SxNDT_6 0x00000040U
+#define DMA_SxNDT_7 0x00000080U
+#define DMA_SxNDT_8 0x00000100U
+#define DMA_SxNDT_9 0x00000200U
+#define DMA_SxNDT_10 0x00000400U
+#define DMA_SxNDT_11 0x00000800U
+#define DMA_SxNDT_12 0x00001000U
+#define DMA_SxNDT_13 0x00002000U
+#define DMA_SxNDT_14 0x00004000U
+#define DMA_SxNDT_15 0x00008000U
+
+/******************** Bits definition for DMA_SxFCR register ****************/
+#define DMA_SxFCR_FEIE 0x00000080U
+#define DMA_SxFCR_FS 0x00000038U
+#define DMA_SxFCR_FS_0 0x00000008U
+#define DMA_SxFCR_FS_1 0x00000010U
+#define DMA_SxFCR_FS_2 0x00000020U
+#define DMA_SxFCR_DMDIS 0x00000004U
+#define DMA_SxFCR_FTH 0x00000003U
+#define DMA_SxFCR_FTH_0 0x00000001U
+#define DMA_SxFCR_FTH_1 0x00000002U
+
+/******************** Bits definition for DMA_LISR register *****************/
+#define DMA_LISR_TCIF3 0x08000000U
+#define DMA_LISR_HTIF3 0x04000000U
+#define DMA_LISR_TEIF3 0x02000000U
+#define DMA_LISR_DMEIF3 0x01000000U
+#define DMA_LISR_FEIF3 0x00400000U
+#define DMA_LISR_TCIF2 0x00200000U
+#define DMA_LISR_HTIF2 0x00100000U
+#define DMA_LISR_TEIF2 0x00080000U
+#define DMA_LISR_DMEIF2 0x00040000U
+#define DMA_LISR_FEIF2 0x00010000U
+#define DMA_LISR_TCIF1 0x00000800U
+#define DMA_LISR_HTIF1 0x00000400U
+#define DMA_LISR_TEIF1 0x00000200U
+#define DMA_LISR_DMEIF1 0x00000100U
+#define DMA_LISR_FEIF1 0x00000040U
+#define DMA_LISR_TCIF0 0x00000020U
+#define DMA_LISR_HTIF0 0x00000010U
+#define DMA_LISR_TEIF0 0x00000008U
+#define DMA_LISR_DMEIF0 0x00000004U
+#define DMA_LISR_FEIF0 0x00000001U
+
+/******************** Bits definition for DMA_HISR register *****************/
+#define DMA_HISR_TCIF7 0x08000000U
+#define DMA_HISR_HTIF7 0x04000000U
+#define DMA_HISR_TEIF7 0x02000000U
+#define DMA_HISR_DMEIF7 0x01000000U
+#define DMA_HISR_FEIF7 0x00400000U
+#define DMA_HISR_TCIF6 0x00200000U
+#define DMA_HISR_HTIF6 0x00100000U
+#define DMA_HISR_TEIF6 0x00080000U
+#define DMA_HISR_DMEIF6 0x00040000U
+#define DMA_HISR_FEIF6 0x00010000U
+#define DMA_HISR_TCIF5 0x00000800U
+#define DMA_HISR_HTIF5 0x00000400U
+#define DMA_HISR_TEIF5 0x00000200U
+#define DMA_HISR_DMEIF5 0x00000100U
+#define DMA_HISR_FEIF5 0x00000040U
+#define DMA_HISR_TCIF4 0x00000020U
+#define DMA_HISR_HTIF4 0x00000010U
+#define DMA_HISR_TEIF4 0x00000008U
+#define DMA_HISR_DMEIF4 0x00000004U
+#define DMA_HISR_FEIF4 0x00000001U
+
+/******************** Bits definition for DMA_LIFCR register ****************/
+#define DMA_LIFCR_CTCIF3 0x08000000U
+#define DMA_LIFCR_CHTIF3 0x04000000U
+#define DMA_LIFCR_CTEIF3 0x02000000U
+#define DMA_LIFCR_CDMEIF3 0x01000000U
+#define DMA_LIFCR_CFEIF3 0x00400000U
+#define DMA_LIFCR_CTCIF2 0x00200000U
+#define DMA_LIFCR_CHTIF2 0x00100000U
+#define DMA_LIFCR_CTEIF2 0x00080000U
+#define DMA_LIFCR_CDMEIF2 0x00040000U
+#define DMA_LIFCR_CFEIF2 0x00010000U
+#define DMA_LIFCR_CTCIF1 0x00000800U
+#define DMA_LIFCR_CHTIF1 0x00000400U
+#define DMA_LIFCR_CTEIF1 0x00000200U
+#define DMA_LIFCR_CDMEIF1 0x00000100U
+#define DMA_LIFCR_CFEIF1 0x00000040U
+#define DMA_LIFCR_CTCIF0 0x00000020U
+#define DMA_LIFCR_CHTIF0 0x00000010U
+#define DMA_LIFCR_CTEIF0 0x00000008U
+#define DMA_LIFCR_CDMEIF0 0x00000004U
+#define DMA_LIFCR_CFEIF0 0x00000001U
+
+/******************** Bits definition for DMA_HIFCR register ****************/
+#define DMA_HIFCR_CTCIF7 0x08000000U
+#define DMA_HIFCR_CHTIF7 0x04000000U
+#define DMA_HIFCR_CTEIF7 0x02000000U
+#define DMA_HIFCR_CDMEIF7 0x01000000U
+#define DMA_HIFCR_CFEIF7 0x00400000U
+#define DMA_HIFCR_CTCIF6 0x00200000U
+#define DMA_HIFCR_CHTIF6 0x00100000U
+#define DMA_HIFCR_CTEIF6 0x00080000U
+#define DMA_HIFCR_CDMEIF6 0x00040000U
+#define DMA_HIFCR_CFEIF6 0x00010000U
+#define DMA_HIFCR_CTCIF5 0x00000800U
+#define DMA_HIFCR_CHTIF5 0x00000400U
+#define DMA_HIFCR_CTEIF5 0x00000200U
+#define DMA_HIFCR_CDMEIF5 0x00000100U
+#define DMA_HIFCR_CFEIF5 0x00000040U
+#define DMA_HIFCR_CTCIF4 0x00000020U
+#define DMA_HIFCR_CHTIF4 0x00000010U
+#define DMA_HIFCR_CTEIF4 0x00000008U
+#define DMA_HIFCR_CDMEIF4 0x00000004U
+#define DMA_HIFCR_CFEIF4 0x00000001U
+
+
+/******************************************************************************/
+/* */
+/* External Interrupt/Event Controller */
+/* */
+/******************************************************************************/
+/******************* Bit definition for EXTI_IMR register *******************/
+#define EXTI_IMR_MR0 0x00000001U /*!< Interrupt Mask on line 0 */
+#define EXTI_IMR_MR1 0x00000002U /*!< Interrupt Mask on line 1 */
+#define EXTI_IMR_MR2 0x00000004U /*!< Interrupt Mask on line 2 */
+#define EXTI_IMR_MR3 0x00000008U /*!< Interrupt Mask on line 3 */
+#define EXTI_IMR_MR4 0x00000010U /*!< Interrupt Mask on line 4 */
+#define EXTI_IMR_MR5 0x00000020U /*!< Interrupt Mask on line 5 */
+#define EXTI_IMR_MR6 0x00000040U /*!< Interrupt Mask on line 6 */
+#define EXTI_IMR_MR7 0x00000080U /*!< Interrupt Mask on line 7 */
+#define EXTI_IMR_MR8 0x00000100U /*!< Interrupt Mask on line 8 */
+#define EXTI_IMR_MR9 0x00000200U /*!< Interrupt Mask on line 9 */
+#define EXTI_IMR_MR10 0x00000400U /*!< Interrupt Mask on line 10 */
+#define EXTI_IMR_MR11 0x00000800U /*!< Interrupt Mask on line 11 */
+#define EXTI_IMR_MR12 0x00001000U /*!< Interrupt Mask on line 12 */
+#define EXTI_IMR_MR13 0x00002000U /*!< Interrupt Mask on line 13 */
+#define EXTI_IMR_MR14 0x00004000U /*!< Interrupt Mask on line 14 */
+#define EXTI_IMR_MR15 0x00008000U /*!< Interrupt Mask on line 15 */
+#define EXTI_IMR_MR16 0x00010000U /*!< Interrupt Mask on line 16 */
+#define EXTI_IMR_MR17 0x00020000U /*!< Interrupt Mask on line 17 */
+#define EXTI_IMR_MR18 0x00040000U /*!< Interrupt Mask on line 18 */
+#define EXTI_IMR_MR19 0x00080000U /*!< Interrupt Mask on line 19 */
+#define EXTI_IMR_MR20 0x00100000U /*!< Interrupt Mask on line 20 */
+#define EXTI_IMR_MR21 0x00200000U /*!< Interrupt Mask on line 21 */
+#define EXTI_IMR_MR22 0x00400000U /*!< Interrupt Mask on line 22 */
+
+/******************* Bit definition for EXTI_EMR register *******************/
+#define EXTI_EMR_MR0 0x00000001U /*!< Event Mask on line 0 */
+#define EXTI_EMR_MR1 0x00000002U /*!< Event Mask on line 1 */
+#define EXTI_EMR_MR2 0x00000004U /*!< Event Mask on line 2 */
+#define EXTI_EMR_MR3 0x00000008U /*!< Event Mask on line 3 */
+#define EXTI_EMR_MR4 0x00000010U /*!< Event Mask on line 4 */
+#define EXTI_EMR_MR5 0x00000020U /*!< Event Mask on line 5 */
+#define EXTI_EMR_MR6 0x00000040U /*!< Event Mask on line 6 */
+#define EXTI_EMR_MR7 0x00000080U /*!< Event Mask on line 7 */
+#define EXTI_EMR_MR8 0x00000100U /*!< Event Mask on line 8 */
+#define EXTI_EMR_MR9 0x00000200U /*!< Event Mask on line 9 */
+#define EXTI_EMR_MR10 0x00000400U /*!< Event Mask on line 10 */
+#define EXTI_EMR_MR11 0x00000800U /*!< Event Mask on line 11 */
+#define EXTI_EMR_MR12 0x00001000U /*!< Event Mask on line 12 */
+#define EXTI_EMR_MR13 0x00002000U /*!< Event Mask on line 13 */
+#define EXTI_EMR_MR14 0x00004000U /*!< Event Mask on line 14 */
+#define EXTI_EMR_MR15 0x00008000U /*!< Event Mask on line 15 */
+#define EXTI_EMR_MR16 0x00010000U /*!< Event Mask on line 16 */
+#define EXTI_EMR_MR17 0x00020000U /*!< Event Mask on line 17 */
+#define EXTI_EMR_MR18 0x00040000U /*!< Event Mask on line 18 */
+#define EXTI_EMR_MR19 0x00080000U /*!< Event Mask on line 19 */
+#define EXTI_EMR_MR20 0x00100000U /*!< Event Mask on line 20 */
+#define EXTI_EMR_MR21 0x00200000U /*!< Event Mask on line 21 */
+#define EXTI_EMR_MR22 0x00400000U /*!< Event Mask on line 22 */
+
+/****************** Bit definition for EXTI_RTSR register *******************/
+#define EXTI_RTSR_TR0 0x00000001U /*!< Rising trigger event configuration bit of line 0 */
+#define EXTI_RTSR_TR1 0x00000002U /*!< Rising trigger event configuration bit of line 1 */
+#define EXTI_RTSR_TR2 0x00000004U /*!< Rising trigger event configuration bit of line 2 */
+#define EXTI_RTSR_TR3 0x00000008U /*!< Rising trigger event configuration bit of line 3 */
+#define EXTI_RTSR_TR4 0x00000010U /*!< Rising trigger event configuration bit of line 4 */
+#define EXTI_RTSR_TR5 0x00000020U /*!< Rising trigger event configuration bit of line 5 */
+#define EXTI_RTSR_TR6 0x00000040U /*!< Rising trigger event configuration bit of line 6 */
+#define EXTI_RTSR_TR7 0x00000080U /*!< Rising trigger event configuration bit of line 7 */
+#define EXTI_RTSR_TR8 0x00000100U /*!< Rising trigger event configuration bit of line 8 */
+#define EXTI_RTSR_TR9 0x00000200U /*!< Rising trigger event configuration bit of line 9 */
+#define EXTI_RTSR_TR10 0x00000400U /*!< Rising trigger event configuration bit of line 10 */
+#define EXTI_RTSR_TR11 0x00000800U /*!< Rising trigger event configuration bit of line 11 */
+#define EXTI_RTSR_TR12 0x00001000U /*!< Rising trigger event configuration bit of line 12 */
+#define EXTI_RTSR_TR13 0x00002000U /*!< Rising trigger event configuration bit of line 13 */
+#define EXTI_RTSR_TR14 0x00004000U /*!< Rising trigger event configuration bit of line 14 */
+#define EXTI_RTSR_TR15 0x00008000U /*!< Rising trigger event configuration bit of line 15 */
+#define EXTI_RTSR_TR16 0x00010000U /*!< Rising trigger event configuration bit of line 16 */
+#define EXTI_RTSR_TR17 0x00020000U /*!< Rising trigger event configuration bit of line 17 */
+#define EXTI_RTSR_TR18 0x00040000U /*!< Rising trigger event configuration bit of line 18 */
+#define EXTI_RTSR_TR19 0x00080000U /*!< Rising trigger event configuration bit of line 19 */
+#define EXTI_RTSR_TR20 0x00100000U /*!< Rising trigger event configuration bit of line 20 */
+#define EXTI_RTSR_TR21 0x00200000U /*!< Rising trigger event configuration bit of line 21 */
+#define EXTI_RTSR_TR22 0x00400000U /*!< Rising trigger event configuration bit of line 22 */
+
+/****************** Bit definition for EXTI_FTSR register *******************/
+#define EXTI_FTSR_TR0 0x00000001U /*!< Falling trigger event configuration bit of line 0 */
+#define EXTI_FTSR_TR1 0x00000002U /*!< Falling trigger event configuration bit of line 1 */
+#define EXTI_FTSR_TR2 0x00000004U /*!< Falling trigger event configuration bit of line 2 */
+#define EXTI_FTSR_TR3 0x00000008U /*!< Falling trigger event configuration bit of line 3 */
+#define EXTI_FTSR_TR4 0x00000010U /*!< Falling trigger event configuration bit of line 4 */
+#define EXTI_FTSR_TR5 0x00000020U /*!< Falling trigger event configuration bit of line 5 */
+#define EXTI_FTSR_TR6 0x00000040U /*!< Falling trigger event configuration bit of line 6 */
+#define EXTI_FTSR_TR7 0x00000080U /*!< Falling trigger event configuration bit of line 7 */
+#define EXTI_FTSR_TR8 0x00000100U /*!< Falling trigger event configuration bit of line 8 */
+#define EXTI_FTSR_TR9 0x00000200U /*!< Falling trigger event configuration bit of line 9 */
+#define EXTI_FTSR_TR10 0x00000400U /*!< Falling trigger event configuration bit of line 10 */
+#define EXTI_FTSR_TR11 0x00000800U /*!< Falling trigger event configuration bit of line 11 */
+#define EXTI_FTSR_TR12 0x00001000U /*!< Falling trigger event configuration bit of line 12 */
+#define EXTI_FTSR_TR13 0x00002000U /*!< Falling trigger event configuration bit of line 13 */
+#define EXTI_FTSR_TR14 0x00004000U /*!< Falling trigger event configuration bit of line 14 */
+#define EXTI_FTSR_TR15 0x00008000U /*!< Falling trigger event configuration bit of line 15 */
+#define EXTI_FTSR_TR16 0x00010000U /*!< Falling trigger event configuration bit of line 16 */
+#define EXTI_FTSR_TR17 0x00020000U /*!< Falling trigger event configuration bit of line 17 */
+#define EXTI_FTSR_TR18 0x00040000U /*!< Falling trigger event configuration bit of line 18 */
+#define EXTI_FTSR_TR19 0x00080000U /*!< Falling trigger event configuration bit of line 19 */
+#define EXTI_FTSR_TR20 0x00100000U /*!< Falling trigger event configuration bit of line 20 */
+#define EXTI_FTSR_TR21 0x00200000U /*!< Falling trigger event configuration bit of line 21 */
+#define EXTI_FTSR_TR22 0x00400000U /*!< Falling trigger event configuration bit of line 22 */
+
+/****************** Bit definition for EXTI_SWIER register ******************/
+#define EXTI_SWIER_SWIER0 0x00000001U /*!< Software Interrupt on line 0 */
+#define EXTI_SWIER_SWIER1 0x00000002U /*!< Software Interrupt on line 1 */
+#define EXTI_SWIER_SWIER2 0x00000004U /*!< Software Interrupt on line 2 */
+#define EXTI_SWIER_SWIER3 0x00000008U /*!< Software Interrupt on line 3 */
+#define EXTI_SWIER_SWIER4 0x00000010U /*!< Software Interrupt on line 4 */
+#define EXTI_SWIER_SWIER5 0x00000020U /*!< Software Interrupt on line 5 */
+#define EXTI_SWIER_SWIER6 0x00000040U /*!< Software Interrupt on line 6 */
+#define EXTI_SWIER_SWIER7 0x00000080U /*!< Software Interrupt on line 7 */
+#define EXTI_SWIER_SWIER8 0x00000100U /*!< Software Interrupt on line 8 */
+#define EXTI_SWIER_SWIER9 0x00000200U /*!< Software Interrupt on line 9 */
+#define EXTI_SWIER_SWIER10 0x00000400U /*!< Software Interrupt on line 10 */
+#define EXTI_SWIER_SWIER11 0x00000800U /*!< Software Interrupt on line 11 */
+#define EXTI_SWIER_SWIER12 0x00001000U /*!< Software Interrupt on line 12 */
+#define EXTI_SWIER_SWIER13 0x00002000U /*!< Software Interrupt on line 13 */
+#define EXTI_SWIER_SWIER14 0x00004000U /*!< Software Interrupt on line 14 */
+#define EXTI_SWIER_SWIER15 0x00008000U /*!< Software Interrupt on line 15 */
+#define EXTI_SWIER_SWIER16 0x00010000U /*!< Software Interrupt on line 16 */
+#define EXTI_SWIER_SWIER17 0x00020000U /*!< Software Interrupt on line 17 */
+#define EXTI_SWIER_SWIER18 0x00040000U /*!< Software Interrupt on line 18 */
+#define EXTI_SWIER_SWIER19 0x00080000U /*!< Software Interrupt on line 19 */
+#define EXTI_SWIER_SWIER20 0x00100000U /*!< Software Interrupt on line 20 */
+#define EXTI_SWIER_SWIER21 0x00200000U /*!< Software Interrupt on line 21 */
+#define EXTI_SWIER_SWIER22 0x00400000U /*!< Software Interrupt on line 22 */
+
+/******************* Bit definition for EXTI_PR register ********************/
+#define EXTI_PR_PR0 0x00000001U /*!< Pending bit for line 0 */
+#define EXTI_PR_PR1 0x00000002U /*!< Pending bit for line 1 */
+#define EXTI_PR_PR2 0x00000004U /*!< Pending bit for line 2 */
+#define EXTI_PR_PR3 0x00000008U /*!< Pending bit for line 3 */
+#define EXTI_PR_PR4 0x00000010U /*!< Pending bit for line 4 */
+#define EXTI_PR_PR5 0x00000020U /*!< Pending bit for line 5 */
+#define EXTI_PR_PR6 0x00000040U /*!< Pending bit for line 6 */
+#define EXTI_PR_PR7 0x00000080U /*!< Pending bit for line 7 */
+#define EXTI_PR_PR8 0x00000100U /*!< Pending bit for line 8 */
+#define EXTI_PR_PR9 0x00000200U /*!< Pending bit for line 9 */
+#define EXTI_PR_PR10 0x00000400U /*!< Pending bit for line 10 */
+#define EXTI_PR_PR11 0x00000800U /*!< Pending bit for line 11 */
+#define EXTI_PR_PR12 0x00001000U /*!< Pending bit for line 12 */
+#define EXTI_PR_PR13 0x00002000U /*!< Pending bit for line 13 */
+#define EXTI_PR_PR14 0x00004000U /*!< Pending bit for line 14 */
+#define EXTI_PR_PR15 0x00008000U /*!< Pending bit for line 15 */
+#define EXTI_PR_PR16 0x00010000U /*!< Pending bit for line 16 */
+#define EXTI_PR_PR17 0x00020000U /*!< Pending bit for line 17 */
+#define EXTI_PR_PR18 0x00040000U /*!< Pending bit for line 18 */
+#define EXTI_PR_PR19 0x00080000U /*!< Pending bit for line 19 */
+#define EXTI_PR_PR20 0x00100000U /*!< Pending bit for line 20 */
+#define EXTI_PR_PR21 0x00200000U /*!< Pending bit for line 21 */
+#define EXTI_PR_PR22 0x00400000U /*!< Pending bit for line 22 */
+
+/******************************************************************************/
+/* */
+/* FLASH */
+/* */
+/******************************************************************************/
+/******************* Bits definition for FLASH_ACR register *****************/
+#define FLASH_ACR_LATENCY 0x0000000FU
+#define FLASH_ACR_LATENCY_0WS 0x00000000U
+#define FLASH_ACR_LATENCY_1WS 0x00000001U
+#define FLASH_ACR_LATENCY_2WS 0x00000002U
+#define FLASH_ACR_LATENCY_3WS 0x00000003U
+#define FLASH_ACR_LATENCY_4WS 0x00000004U
+#define FLASH_ACR_LATENCY_5WS 0x00000005U
+#define FLASH_ACR_LATENCY_6WS 0x00000006U
+#define FLASH_ACR_LATENCY_7WS 0x00000007U
+
+#define FLASH_ACR_PRFTEN 0x00000100U
+#define FLASH_ACR_ICEN 0x00000200U
+#define FLASH_ACR_DCEN 0x00000400U
+#define FLASH_ACR_ICRST 0x00000800U
+#define FLASH_ACR_DCRST 0x00001000U
+#define FLASH_ACR_BYTE0_ADDRESS 0x40023C00U
+#define FLASH_ACR_BYTE2_ADDRESS 0x40023C03U
+
+/******************* Bits definition for FLASH_SR register ******************/
+#define FLASH_SR_EOP 0x00000001U
+#define FLASH_SR_SOP 0x00000002U
+#define FLASH_SR_WRPERR 0x00000010U
+#define FLASH_SR_PGAERR 0x00000020U
+#define FLASH_SR_PGPERR 0x00000040U
+#define FLASH_SR_PGSERR 0x00000080U
+#define FLASH_SR_BSY 0x00010000U
+
+/******************* Bits definition for FLASH_CR register ******************/
+#define FLASH_CR_PG 0x00000001U
+#define FLASH_CR_SER 0x00000002U
+#define FLASH_CR_MER 0x00000004U
+#define FLASH_CR_SNB 0x000000F8U
+#define FLASH_CR_SNB_0 0x00000008U
+#define FLASH_CR_SNB_1 0x00000010U
+#define FLASH_CR_SNB_2 0x00000020U
+#define FLASH_CR_SNB_3 0x00000040U
+#define FLASH_CR_SNB_4 0x00000080U
+#define FLASH_CR_PSIZE 0x00000300U
+#define FLASH_CR_PSIZE_0 0x00000100U
+#define FLASH_CR_PSIZE_1 0x00000200U
+#define FLASH_CR_STRT 0x00010000U
+#define FLASH_CR_EOPIE 0x01000000U
+#define FLASH_CR_LOCK 0x80000000U
+
+/******************* Bits definition for FLASH_OPTCR register ***************/
+#define FLASH_OPTCR_OPTLOCK 0x00000001U
+#define FLASH_OPTCR_OPTSTRT 0x00000002U
+#define FLASH_OPTCR_BOR_LEV_0 0x00000004U
+#define FLASH_OPTCR_BOR_LEV_1 0x00000008U
+#define FLASH_OPTCR_BOR_LEV 0x0000000CU
+
+#define FLASH_OPTCR_WDG_SW 0x00000020U
+#define FLASH_OPTCR_nRST_STOP 0x00000040U
+#define FLASH_OPTCR_nRST_STDBY 0x00000080U
+#define FLASH_OPTCR_RDP 0x0000FF00U
+#define FLASH_OPTCR_RDP_0 0x00000100U
+#define FLASH_OPTCR_RDP_1 0x00000200U
+#define FLASH_OPTCR_RDP_2 0x00000400U
+#define FLASH_OPTCR_RDP_3 0x00000800U
+#define FLASH_OPTCR_RDP_4 0x00001000U
+#define FLASH_OPTCR_RDP_5 0x00002000U
+#define FLASH_OPTCR_RDP_6 0x00004000U
+#define FLASH_OPTCR_RDP_7 0x00008000U
+#define FLASH_OPTCR_nWRP 0x0FFF0000U
+#define FLASH_OPTCR_nWRP_0 0x00010000U
+#define FLASH_OPTCR_nWRP_1 0x00020000U
+#define FLASH_OPTCR_nWRP_2 0x00040000U
+#define FLASH_OPTCR_nWRP_3 0x00080000U
+#define FLASH_OPTCR_nWRP_4 0x00100000U
+#define FLASH_OPTCR_nWRP_5 0x00200000U
+#define FLASH_OPTCR_nWRP_6 0x00400000U
+#define FLASH_OPTCR_nWRP_7 0x00800000U
+#define FLASH_OPTCR_nWRP_8 0x01000000U
+#define FLASH_OPTCR_nWRP_9 0x02000000U
+#define FLASH_OPTCR_nWRP_10 0x04000000U
+#define FLASH_OPTCR_nWRP_11 0x08000000U
+
+/****************** Bits definition for FLASH_OPTCR1 register ***************/
+#define FLASH_OPTCR1_nWRP 0x0FFF0000U
+#define FLASH_OPTCR1_nWRP_0 0x00010000U
+#define FLASH_OPTCR1_nWRP_1 0x00020000U
+#define FLASH_OPTCR1_nWRP_2 0x00040000U
+#define FLASH_OPTCR1_nWRP_3 0x00080000U
+#define FLASH_OPTCR1_nWRP_4 0x00100000U
+#define FLASH_OPTCR1_nWRP_5 0x00200000U
+#define FLASH_OPTCR1_nWRP_6 0x00400000U
+#define FLASH_OPTCR1_nWRP_7 0x00800000U
+#define FLASH_OPTCR1_nWRP_8 0x01000000U
+#define FLASH_OPTCR1_nWRP_9 0x02000000U
+#define FLASH_OPTCR1_nWRP_10 0x04000000U
+#define FLASH_OPTCR1_nWRP_11 0x08000000U
+
+/******************************************************************************/
+/* */
+/* Flexible Static Memory Controller */
+/* */
+/******************************************************************************/
+/****************** Bit definition for FSMC_BCR1 register *******************/
+#define FSMC_BCR1_MBKEN 0x00000001U /*!<Memory bank enable bit */
+#define FSMC_BCR1_MUXEN 0x00000002U /*!<Address/data multiplexing enable bit */
+
+#define FSMC_BCR1_MTYP 0x0000000CU /*!<MTYP[1:0] bits (Memory type) */
+#define FSMC_BCR1_MTYP_0 0x00000004U /*!<Bit 0 */
+#define FSMC_BCR1_MTYP_1 0x00000008U /*!<Bit 1 */
+
+#define FSMC_BCR1_MWID 0x00000030U /*!<MWID[1:0] bits (Memory data bus width) */
+#define FSMC_BCR1_MWID_0 0x00000010U /*!<Bit 0 */
+#define FSMC_BCR1_MWID_1 0x00000020U /*!<Bit 1 */
+
+#define FSMC_BCR1_FACCEN 0x00000040U /*!<Flash access enable */
+#define FSMC_BCR1_BURSTEN 0x00000100U /*!<Burst enable bit */
+#define FSMC_BCR1_WAITPOL 0x00000200U /*!<Wait signal polarity bit */
+#define FSMC_BCR1_WRAPMOD 0x00000400U /*!<Wrapped burst mode support */
+#define FSMC_BCR1_WAITCFG 0x00000800U /*!<Wait timing configuration */
+#define FSMC_BCR1_WREN 0x00001000U /*!<Write enable bit */
+#define FSMC_BCR1_WAITEN 0x00002000U /*!<Wait enable bit */
+#define FSMC_BCR1_EXTMOD 0x00004000U /*!<Extended mode enable */
+#define FSMC_BCR1_ASYNCWAIT 0x00008000U /*!<Asynchronous wait */
+#define FSMC_BCR1_CPSIZE 0x00070000U /*!<CRAM page size */
+#define FSMC_BCR1_CPSIZE_0 0x00010000U /*!<Bit 0 */
+#define FSMC_BCR1_CPSIZE_1 0x00020000U /*!<Bit 1 */
+#define FSMC_BCR1_CPSIZE_2 0x00040000U /*!<Bit 2 */
+#define FSMC_BCR1_CBURSTRW 0x00080000U /*!<Write burst enable */
+
+/****************** Bit definition for FSMC_BCR2 register *******************/
+#define FSMC_BCR2_MBKEN 0x00000001U /*!<Memory bank enable bit */
+#define FSMC_BCR2_MUXEN 0x00000002U /*!<Address/data multiplexing enable bit */
+
+#define FSMC_BCR2_MTYP 0x0000000CU /*!<MTYP[1:0] bits (Memory type) */
+#define FSMC_BCR2_MTYP_0 0x00000004U /*!<Bit 0 */
+#define FSMC_BCR2_MTYP_1 0x00000008U /*!<Bit 1 */
+
+#define FSMC_BCR2_MWID 0x00000030U /*!<MWID[1:0] bits (Memory data bus width) */
+#define FSMC_BCR2_MWID_0 0x00000010U /*!<Bit 0 */
+#define FSMC_BCR2_MWID_1 0x00000020U /*!<Bit 1 */
+
+#define FSMC_BCR2_FACCEN 0x00000040U /*!<Flash access enable */
+#define FSMC_BCR2_BURSTEN 0x00000100U /*!<Burst enable bit */
+#define FSMC_BCR2_WAITPOL 0x00000200U /*!<Wait signal polarity bit */
+#define FSMC_BCR2_WRAPMOD 0x00000400U /*!<Wrapped burst mode support */
+#define FSMC_BCR2_WAITCFG 0x00000800U /*!<Wait timing configuration */
+#define FSMC_BCR2_WREN 0x00001000U /*!<Write enable bit */
+#define FSMC_BCR2_WAITEN 0x00002000U /*!<Wait enable bit */
+#define FSMC_BCR2_EXTMOD 0x00004000U /*!<Extended mode enable */
+#define FSMC_BCR2_ASYNCWAIT 0x00008000U /*!<Asynchronous wait */
+#define FSMC_BCR2_CPSIZE 0x00070000U /*!<CRAM page size */
+#define FSMC_BCR2_CPSIZE_0 0x00010000U /*!<Bit 0 */
+#define FSMC_BCR2_CPSIZE_1 0x00020000U /*!<Bit 1 */
+#define FSMC_BCR2_CPSIZE_2 0x00040000U /*!<Bit 2 */
+#define FSMC_BCR2_CBURSTRW 0x00080000U /*!<Write burst enable */
+
+/****************** Bit definition for FSMC_BCR3 register *******************/
+#define FSMC_BCR3_MBKEN 0x00000001U /*!<Memory bank enable bit */
+#define FSMC_BCR3_MUXEN 0x00000002U /*!<Address/data multiplexing enable bit */
+
+#define FSMC_BCR3_MTYP 0x0000000CU /*!<MTYP[1:0] bits (Memory type) */
+#define FSMC_BCR3_MTYP_0 0x00000004U /*!<Bit 0 */
+#define FSMC_BCR3_MTYP_1 0x00000008U /*!<Bit 1 */
+
+#define FSMC_BCR3_MWID 0x00000030U /*!<MWID[1:0] bits (Memory data bus width) */
+#define FSMC_BCR3_MWID_0 0x00000010U /*!<Bit 0 */
+#define FSMC_BCR3_MWID_1 0x00000020U /*!<Bit 1 */
+
+#define FSMC_BCR3_FACCEN 0x00000040U /*!<Flash access enable */
+#define FSMC_BCR3_BURSTEN 0x00000100U /*!<Burst enable bit */
+#define FSMC_BCR3_WAITPOL 0x00000200U /*!<Wait signal polarity bit */
+#define FSMC_BCR3_WRAPMOD 0x00000400U /*!<Wrapped burst mode support */
+#define FSMC_BCR3_WAITCFG 0x00000800U /*!<Wait timing configuration */
+#define FSMC_BCR3_WREN 0x00001000U /*!<Write enable bit */
+#define FSMC_BCR3_WAITEN 0x00002000U /*!<Wait enable bit */
+#define FSMC_BCR3_EXTMOD 0x00004000U /*!<Extended mode enable */
+#define FSMC_BCR3_ASYNCWAIT 0x00008000U /*!<Asynchronous wait */
+#define FSMC_BCR3_CPSIZE 0x00070000U /*!<CRAM page size */
+#define FSMC_BCR3_CPSIZE_0 0x00010000U /*!<Bit 0 */
+#define FSMC_BCR3_CPSIZE_1 0x00020000U /*!<Bit 1 */
+#define FSMC_BCR3_CPSIZE_2 0x00040000U /*!<Bit 2 */
+#define FSMC_BCR3_CBURSTRW 0x00080000U /*!<Write burst enable */
+
+/****************** Bit definition for FSMC_BCR4 register *******************/
+#define FSMC_BCR4_MBKEN 0x00000001U /*!<Memory bank enable bit */
+#define FSMC_BCR4_MUXEN 0x00000002U /*!<Address/data multiplexing enable bit */
+
+#define FSMC_BCR4_MTYP 0x0000000CU /*!<MTYP[1:0] bits (Memory type) */
+#define FSMC_BCR4_MTYP_0 0x00000004U /*!<Bit 0 */
+#define FSMC_BCR4_MTYP_1 0x00000008U /*!<Bit 1 */
+
+#define FSMC_BCR4_MWID 0x00000030U /*!<MWID[1:0] bits (Memory data bus width) */
+#define FSMC_BCR4_MWID_0 0x00000010U /*!<Bit 0 */
+#define FSMC_BCR4_MWID_1 0x00000020U /*!<Bit 1 */
+
+#define FSMC_BCR4_FACCEN 0x00000040U /*!<Flash access enable */
+#define FSMC_BCR4_BURSTEN 0x00000100U /*!<Burst enable bit */
+#define FSMC_BCR4_WAITPOL 0x00000200U /*!<Wait signal polarity bit */
+#define FSMC_BCR4_WRAPMOD 0x00000400U /*!<Wrapped burst mode support */
+#define FSMC_BCR4_WAITCFG 0x00000800U /*!<Wait timing configuration */
+#define FSMC_BCR4_WREN 0x00001000U /*!<Write enable bit */
+#define FSMC_BCR4_WAITEN 0x00002000U /*!<Wait enable bit */
+#define FSMC_BCR4_EXTMOD 0x00004000U /*!<Extended mode enable */
+#define FSMC_BCR4_ASYNCWAIT 0x00008000U /*!<Asynchronous wait */
+#define FSMC_BCR4_CPSIZE 0x00070000U /*!<CRAM page size */
+#define FSMC_BCR4_CPSIZE_0 0x00010000U /*!<Bit 0 */
+#define FSMC_BCR4_CPSIZE_1 0x00020000U /*!<Bit 1 */
+#define FSMC_BCR4_CPSIZE_2 0x00040000U /*!<Bit 2 */
+#define FSMC_BCR4_CBURSTRW 0x00080000U /*!<Write burst enable */
+
+/****************** Bit definition for FSMC_BTR1 register ******************/
+#define FSMC_BTR1_ADDSET 0x0000000FU /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FSMC_BTR1_ADDSET_0 0x00000001U /*!<Bit 0 */
+#define FSMC_BTR1_ADDSET_1 0x00000002U /*!<Bit 1 */
+#define FSMC_BTR1_ADDSET_2 0x00000004U /*!<Bit 2 */
+#define FSMC_BTR1_ADDSET_3 0x00000008U /*!<Bit 3 */
+
+#define FSMC_BTR1_ADDHLD 0x000000F0U /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FSMC_BTR1_ADDHLD_0 0x00000010U /*!<Bit 0 */
+#define FSMC_BTR1_ADDHLD_1 0x00000020U /*!<Bit 1 */
+#define FSMC_BTR1_ADDHLD_2 0x00000040U /*!<Bit 2 */
+#define FSMC_BTR1_ADDHLD_3 0x00000080U /*!<Bit 3 */
+
+#define FSMC_BTR1_DATAST 0x0000FF00U /*!<DATAST [7:0] bits (Data-phase duration) */
+#define FSMC_BTR1_DATAST_0 0x00000100U /*!<Bit 0 */
+#define FSMC_BTR1_DATAST_1 0x00000200U /*!<Bit 1 */
+#define FSMC_BTR1_DATAST_2 0x00000400U /*!<Bit 2 */
+#define FSMC_BTR1_DATAST_3 0x00000800U /*!<Bit 3 */
+#define FSMC_BTR1_DATAST_4 0x00001000U /*!<Bit 4 */
+#define FSMC_BTR1_DATAST_5 0x00002000U /*!<Bit 5 */
+#define FSMC_BTR1_DATAST_6 0x00004000U /*!<Bit 6 */
+#define FSMC_BTR1_DATAST_7 0x00008000U /*!<Bit 7 */
+
+#define FSMC_BTR1_BUSTURN 0x000F0000U /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define FSMC_BTR1_BUSTURN_0 0x00010000U /*!<Bit 0 */
+#define FSMC_BTR1_BUSTURN_1 0x00020000U /*!<Bit 1 */
+#define FSMC_BTR1_BUSTURN_2 0x00040000U /*!<Bit 2 */
+#define FSMC_BTR1_BUSTURN_3 0x00080000U /*!<Bit 3 */
+
+#define FSMC_BTR1_CLKDIV 0x00F00000U /*!<CLKDIV[3:0] bits (Clock divide ratio) */
+#define FSMC_BTR1_CLKDIV_0 0x00100000U /*!<Bit 0 */
+#define FSMC_BTR1_CLKDIV_1 0x00200000U /*!<Bit 1 */
+#define FSMC_BTR1_CLKDIV_2 0x00400000U /*!<Bit 2 */
+#define FSMC_BTR1_CLKDIV_3 0x00800000U /*!<Bit 3 */
+
+#define FSMC_BTR1_DATLAT 0x0F000000U /*!<DATLA[3:0] bits (Data latency) */
+#define FSMC_BTR1_DATLAT_0 0x01000000U /*!<Bit 0 */
+#define FSMC_BTR1_DATLAT_1 0x02000000U /*!<Bit 1 */
+#define FSMC_BTR1_DATLAT_2 0x04000000U /*!<Bit 2 */
+#define FSMC_BTR1_DATLAT_3 0x08000000U /*!<Bit 3 */
+
+#define FSMC_BTR1_ACCMOD 0x30000000U /*!<ACCMOD[1:0] bits (Access mode) */
+#define FSMC_BTR1_ACCMOD_0 0x10000000U /*!<Bit 0 */
+#define FSMC_BTR1_ACCMOD_1 0x20000000U /*!<Bit 1 */
+
+/****************** Bit definition for FSMC_BTR2 register *******************/
+#define FSMC_BTR2_ADDSET 0x0000000FU /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FSMC_BTR2_ADDSET_0 0x00000001U /*!<Bit 0 */
+#define FSMC_BTR2_ADDSET_1 0x00000002U /*!<Bit 1 */
+#define FSMC_BTR2_ADDSET_2 0x00000004U /*!<Bit 2 */
+#define FSMC_BTR2_ADDSET_3 0x00000008U /*!<Bit 3 */
+
+#define FSMC_BTR2_ADDHLD 0x000000F0U /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FSMC_BTR2_ADDHLD_0 0x00000010U /*!<Bit 0 */
+#define FSMC_BTR2_ADDHLD_1 0x00000020U /*!<Bit 1 */
+#define FSMC_BTR2_ADDHLD_2 0x00000040U /*!<Bit 2 */
+#define FSMC_BTR2_ADDHLD_3 0x00000080U /*!<Bit 3 */
+
+#define FSMC_BTR2_DATAST 0x0000FF00U /*!<DATAST [7:0] bits (Data-phase duration) */
+#define FSMC_BTR2_DATAST_0 0x00000100U /*!<Bit 0 */
+#define FSMC_BTR2_DATAST_1 0x00000200U /*!<Bit 1 */
+#define FSMC_BTR2_DATAST_2 0x00000400U /*!<Bit 2 */
+#define FSMC_BTR2_DATAST_3 0x00000800U /*!<Bit 3 */
+#define FSMC_BTR2_DATAST_4 0x00001000U /*!<Bit 4 */
+#define FSMC_BTR2_DATAST_5 0x00002000U /*!<Bit 5 */
+#define FSMC_BTR2_DATAST_6 0x00004000U /*!<Bit 6 */
+#define FSMC_BTR2_DATAST_7 0x00008000U /*!<Bit 7 */
+
+#define FSMC_BTR2_BUSTURN 0x000F0000U /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define FSMC_BTR2_BUSTURN_0 0x00010000U /*!<Bit 0 */
+#define FSMC_BTR2_BUSTURN_1 0x00020000U /*!<Bit 1 */
+#define FSMC_BTR2_BUSTURN_2 0x00040000U /*!<Bit 2 */
+#define FSMC_BTR2_BUSTURN_3 0x00080000U /*!<Bit 3 */
+
+#define FSMC_BTR2_CLKDIV 0x00F00000U /*!<CLKDIV[3:0] bits (Clock divide ratio) */
+#define FSMC_BTR2_CLKDIV_0 0x00100000U /*!<Bit 0 */
+#define FSMC_BTR2_CLKDIV_1 0x00200000U /*!<Bit 1 */
+#define FSMC_BTR2_CLKDIV_2 0x00400000U /*!<Bit 2 */
+#define FSMC_BTR2_CLKDIV_3 0x00800000U /*!<Bit 3 */
+
+#define FSMC_BTR2_DATLAT 0x0F000000U /*!<DATLA[3:0] bits (Data latency) */
+#define FSMC_BTR2_DATLAT_0 0x01000000U /*!<Bit 0 */
+#define FSMC_BTR2_DATLAT_1 0x02000000U /*!<Bit 1 */
+#define FSMC_BTR2_DATLAT_2 0x04000000U /*!<Bit 2 */
+#define FSMC_BTR2_DATLAT_3 0x08000000U /*!<Bit 3 */
+
+#define FSMC_BTR2_ACCMOD 0x30000000U /*!<ACCMOD[1:0] bits (Access mode) */
+#define FSMC_BTR2_ACCMOD_0 0x10000000U /*!<Bit 0 */
+#define FSMC_BTR2_ACCMOD_1 0x20000000U /*!<Bit 1 */
+
+/******************* Bit definition for FSMC_BTR3 register *******************/
+#define FSMC_BTR3_ADDSET 0x0000000FU /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FSMC_BTR3_ADDSET_0 0x00000001U /*!<Bit 0 */
+#define FSMC_BTR3_ADDSET_1 0x00000002U /*!<Bit 1 */
+#define FSMC_BTR3_ADDSET_2 0x00000004U /*!<Bit 2 */
+#define FSMC_BTR3_ADDSET_3 0x00000008U /*!<Bit 3 */
+
+#define FSMC_BTR3_ADDHLD 0x000000F0U /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FSMC_BTR3_ADDHLD_0 0x00000010U /*!<Bit 0 */
+#define FSMC_BTR3_ADDHLD_1 0x00000020U /*!<Bit 1 */
+#define FSMC_BTR3_ADDHLD_2 0x00000040U /*!<Bit 2 */
+#define FSMC_BTR3_ADDHLD_3 0x00000080U /*!<Bit 3 */
+
+#define FSMC_BTR3_DATAST 0x0000FF00U /*!<DATAST [7:0] bits (Data-phase duration) */
+#define FSMC_BTR3_DATAST_0 0x00000100U /*!<Bit 0 */
+#define FSMC_BTR3_DATAST_1 0x00000200U /*!<Bit 1 */
+#define FSMC_BTR3_DATAST_2 0x00000400U /*!<Bit 2 */
+#define FSMC_BTR3_DATAST_3 0x00000800U /*!<Bit 3 */
+#define FSMC_BTR3_DATAST_4 0x00001000U /*!<Bit 4 */
+#define FSMC_BTR3_DATAST_5 0x00002000U /*!<Bit 5 */
+#define FSMC_BTR3_DATAST_6 0x00004000U /*!<Bit 6 */
+#define FSMC_BTR3_DATAST_7 0x00008000U /*!<Bit 7 */
+
+#define FSMC_BTR3_BUSTURN 0x000F0000U /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define FSMC_BTR3_BUSTURN_0 0x00010000U /*!<Bit 0 */
+#define FSMC_BTR3_BUSTURN_1 0x00020000U /*!<Bit 1 */
+#define FSMC_BTR3_BUSTURN_2 0x00040000U /*!<Bit 2 */
+#define FSMC_BTR3_BUSTURN_3 0x00080000U /*!<Bit 3 */
+
+#define FSMC_BTR3_CLKDIV 0x00F00000U /*!<CLKDIV[3:0] bits (Clock divide ratio) */
+#define FSMC_BTR3_CLKDIV_0 0x00100000U /*!<Bit 0 */
+#define FSMC_BTR3_CLKDIV_1 0x00200000U /*!<Bit 1 */
+#define FSMC_BTR3_CLKDIV_2 0x00400000U /*!<Bit 2 */
+#define FSMC_BTR3_CLKDIV_3 0x00800000U /*!<Bit 3 */
+
+#define FSMC_BTR3_DATLAT 0x0F000000U /*!<DATLA[3:0] bits (Data latency) */
+#define FSMC_BTR3_DATLAT_0 0x01000000U /*!<Bit 0 */
+#define FSMC_BTR3_DATLAT_1 0x02000000U /*!<Bit 1 */
+#define FSMC_BTR3_DATLAT_2 0x04000000U /*!<Bit 2 */
+#define FSMC_BTR3_DATLAT_3 0x08000000U /*!<Bit 3 */
+
+#define FSMC_BTR3_ACCMOD 0x30000000U /*!<ACCMOD[1:0] bits (Access mode) */
+#define FSMC_BTR3_ACCMOD_0 0x10000000U /*!<Bit 0 */
+#define FSMC_BTR3_ACCMOD_1 0x20000000U /*!<Bit 1 */
+
+/****************** Bit definition for FSMC_BTR4 register *******************/
+#define FSMC_BTR4_ADDSET 0x0000000FU /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FSMC_BTR4_ADDSET_0 0x00000001U /*!<Bit 0 */
+#define FSMC_BTR4_ADDSET_1 0x00000002U /*!<Bit 1 */
+#define FSMC_BTR4_ADDSET_2 0x00000004U /*!<Bit 2 */
+#define FSMC_BTR4_ADDSET_3 0x00000008U /*!<Bit 3 */
+
+#define FSMC_BTR4_ADDHLD 0x000000F0U /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FSMC_BTR4_ADDHLD_0 0x00000010U /*!<Bit 0 */
+#define FSMC_BTR4_ADDHLD_1 0x00000020U /*!<Bit 1 */
+#define FSMC_BTR4_ADDHLD_2 0x00000040U /*!<Bit 2 */
+#define FSMC_BTR4_ADDHLD_3 0x00000080U /*!<Bit 3 */
+
+#define FSMC_BTR4_DATAST 0x0000FF00U /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FSMC_BTR4_DATAST_0 0x00000100U /*!<Bit 0 */
+#define FSMC_BTR4_DATAST_1 0x00000200U /*!<Bit 1 */
+#define FSMC_BTR4_DATAST_2 0x00000400U /*!<Bit 2 */
+#define FSMC_BTR4_DATAST_3 0x00000800U /*!<Bit 3 */
+#define FSMC_BTR4_DATAST_4 0x00001000U /*!<Bit 4 */
+#define FSMC_BTR4_DATAST_5 0x00002000U /*!<Bit 5 */
+#define FSMC_BTR4_DATAST_6 0x00004000U /*!<Bit 6 */
+#define FSMC_BTR4_DATAST_7 0x00008000U /*!<Bit 7 */
+
+#define FSMC_BTR4_BUSTURN 0x000F0000U /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define FSMC_BTR4_BUSTURN_0 0x00010000U /*!<Bit 0 */
+#define FSMC_BTR4_BUSTURN_1 0x00020000U /*!<Bit 1 */
+#define FSMC_BTR4_BUSTURN_2 0x00040000U /*!<Bit 2 */
+#define FSMC_BTR4_BUSTURN_3 0x00080000U /*!<Bit 3 */
+
+#define FSMC_BTR4_CLKDIV 0x00F00000U /*!<CLKDIV[3:0] bits (Clock divide ratio) */
+#define FSMC_BTR4_CLKDIV_0 0x00100000U /*!<Bit 0 */
+#define FSMC_BTR4_CLKDIV_1 0x00200000U /*!<Bit 1 */
+#define FSMC_BTR4_CLKDIV_2 0x00400000U /*!<Bit 2 */
+#define FSMC_BTR4_CLKDIV_3 0x00800000U /*!<Bit 3 */
+
+#define FSMC_BTR4_DATLAT 0x0F000000U /*!<DATLA[3:0] bits (Data latency) */
+#define FSMC_BTR4_DATLAT_0 0x01000000U /*!<Bit 0 */
+#define FSMC_BTR4_DATLAT_1 0x02000000U /*!<Bit 1 */
+#define FSMC_BTR4_DATLAT_2 0x04000000U /*!<Bit 2 */
+#define FSMC_BTR4_DATLAT_3 0x08000000U /*!<Bit 3 */
+
+#define FSMC_BTR4_ACCMOD 0x30000000U /*!<ACCMOD[1:0] bits (Access mode) */
+#define FSMC_BTR4_ACCMOD_0 0x10000000U /*!<Bit 0 */
+#define FSMC_BTR4_ACCMOD_1 0x20000000U /*!<Bit 1 */
+
+/****************** Bit definition for FSMC_BWTR1 register ******************/
+#define FSMC_BWTR1_ADDSET 0x0000000FU /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FSMC_BWTR1_ADDSET_0 0x00000001U /*!<Bit 0 */
+#define FSMC_BWTR1_ADDSET_1 0x00000002U /*!<Bit 1 */
+#define FSMC_BWTR1_ADDSET_2 0x00000004U /*!<Bit 2 */
+#define FSMC_BWTR1_ADDSET_3 0x00000008U /*!<Bit 3 */
+
+#define FSMC_BWTR1_ADDHLD 0x000000F0U /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FSMC_BWTR1_ADDHLD_0 0x00000010U /*!<Bit 0 */
+#define FSMC_BWTR1_ADDHLD_1 0x00000020U /*!<Bit 1 */
+#define FSMC_BWTR1_ADDHLD_2 0x00000040U /*!<Bit 2 */
+#define FSMC_BWTR1_ADDHLD_3 0x00000080U /*!<Bit 3 */
+
+#define FSMC_BWTR1_DATAST 0x0000FF00U /*!<DATAST [7:0] bits (Data-phase duration) */
+#define FSMC_BWTR1_DATAST_0 0x00000100U /*!<Bit 0 */
+#define FSMC_BWTR1_DATAST_1 0x00000200U /*!<Bit 1 */
+#define FSMC_BWTR1_DATAST_2 0x00000400U /*!<Bit 2 */
+#define FSMC_BWTR1_DATAST_3 0x00000800U /*!<Bit 3 */
+#define FSMC_BWTR1_DATAST_4 0x00001000U /*!<Bit 4 */
+#define FSMC_BWTR1_DATAST_5 0x00002000U /*!<Bit 5 */
+#define FSMC_BWTR1_DATAST_6 0x00004000U /*!<Bit 6 */
+#define FSMC_BWTR1_DATAST_7 0x00008000U /*!<Bit 7 */
+
+#define FSMC_BWTR1_BUSTURN 0x000F0000U /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
+#define FSMC_BWTR1_BUSTURN_0 0x00010000U /*!<Bit 0 */
+#define FSMC_BWTR1_BUSTURN_1 0x00020000U /*!<Bit 1 */
+#define FSMC_BWTR1_BUSTURN_2 0x00040000U /*!<Bit 2 */
+#define FSMC_BWTR1_BUSTURN_3 0x00080000U /*!<Bit 3 */
+
+#define FSMC_BWTR1_ACCMOD 0x30000000U /*!<ACCMOD[1:0] bits (Access mode) */
+#define FSMC_BWTR1_ACCMOD_0 0x10000000U /*!<Bit 0 */
+#define FSMC_BWTR1_ACCMOD_1 0x20000000U /*!<Bit 1 */
+
+/****************** Bit definition for FSMC_BWTR2 register ******************/
+#define FSMC_BWTR2_ADDSET 0x0000000FU /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FSMC_BWTR2_ADDSET_0 0x00000001U /*!<Bit 0 */
+#define FSMC_BWTR2_ADDSET_1 0x00000002U /*!<Bit 1 */
+#define FSMC_BWTR2_ADDSET_2 0x00000004U /*!<Bit 2 */
+#define FSMC_BWTR2_ADDSET_3 0x00000008U /*!<Bit 3 */
+
+#define FSMC_BWTR2_ADDHLD 0x000000F0U /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FSMC_BWTR2_ADDHLD_0 0x00000010U /*!<Bit 0 */
+#define FSMC_BWTR2_ADDHLD_1 0x00000020U /*!<Bit 1 */
+#define FSMC_BWTR2_ADDHLD_2 0x00000040U /*!<Bit 2 */
+#define FSMC_BWTR2_ADDHLD_3 0x00000080U /*!<Bit 3 */
+
+#define FSMC_BWTR2_DATAST 0x0000FF00U /*!<DATAST [7:0] bits (Data-phase duration) */
+#define FSMC_BWTR2_DATAST_0 0x00000100U /*!<Bit 0 */
+#define FSMC_BWTR2_DATAST_1 0x00000200U /*!<Bit 1 */
+#define FSMC_BWTR2_DATAST_2 0x00000400U /*!<Bit 2 */
+#define FSMC_BWTR2_DATAST_3 0x00000800U /*!<Bit 3 */
+#define FSMC_BWTR2_DATAST_4 0x00001000U /*!<Bit 4 */
+#define FSMC_BWTR2_DATAST_5 0x00002000U /*!<Bit 5 */
+#define FSMC_BWTR2_DATAST_6 0x00004000U /*!<Bit 6 */
+#define FSMC_BWTR2_DATAST_7 0x00008000U /*!<Bit 7 */
+
+#define FSMC_BWTR2_BUSTURN 0x000F0000U /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
+#define FSMC_BWTR2_BUSTURN_0 0x00010000U /*!<Bit 0 */
+#define FSMC_BWTR2_BUSTURN_1 0x00020000U /*!<Bit 1 */
+#define FSMC_BWTR2_BUSTURN_2 0x00040000U /*!<Bit 2 */
+#define FSMC_BWTR2_BUSTURN_3 0x00080000U /*!<Bit 3 */
+
+#define FSMC_BWTR2_ACCMOD 0x30000000U /*!<ACCMOD[1:0] bits (Access mode) */
+#define FSMC_BWTR2_ACCMOD_0 0x10000000U /*!<Bit 0 */
+#define FSMC_BWTR2_ACCMOD_1 0x20000000U /*!<Bit 1 */
+
+/****************** Bit definition for FSMC_BWTR3 register ******************/
+#define FSMC_BWTR3_ADDSET 0x0000000FU /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FSMC_BWTR3_ADDSET_0 0x00000001U /*!<Bit 0 */
+#define FSMC_BWTR3_ADDSET_1 0x00000002U /*!<Bit 1 */
+#define FSMC_BWTR3_ADDSET_2 0x00000004U /*!<Bit 2 */
+#define FSMC_BWTR3_ADDSET_3 0x00000008U /*!<Bit 3 */
+
+#define FSMC_BWTR3_ADDHLD 0x000000F0U /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FSMC_BWTR3_ADDHLD_0 0x00000010U /*!<Bit 0 */
+#define FSMC_BWTR3_ADDHLD_1 0x00000020U /*!<Bit 1 */
+#define FSMC_BWTR3_ADDHLD_2 0x00000040U /*!<Bit 2 */
+#define FSMC_BWTR3_ADDHLD_3 0x00000080U /*!<Bit 3 */
+
+#define FSMC_BWTR3_DATAST 0x0000FF00U /*!<DATAST [7:0] bits (Data-phase duration) */
+#define FSMC_BWTR3_DATAST_0 0x00000100U /*!<Bit 0 */
+#define FSMC_BWTR3_DATAST_1 0x00000200U /*!<Bit 1 */
+#define FSMC_BWTR3_DATAST_2 0x00000400U /*!<Bit 2 */
+#define FSMC_BWTR3_DATAST_3 0x00000800U /*!<Bit 3 */
+#define FSMC_BWTR3_DATAST_4 0x00001000U /*!<Bit 4 */
+#define FSMC_BWTR3_DATAST_5 0x00002000U /*!<Bit 5 */
+#define FSMC_BWTR3_DATAST_6 0x00004000U /*!<Bit 6 */
+#define FSMC_BWTR3_DATAST_7 0x00008000U /*!<Bit 7 */
+
+#define FSMC_BWTR3_BUSTURN 0x000F0000U /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
+#define FSMC_BWTR3_BUSTURN_0 0x00010000U /*!<Bit 0 */
+#define FSMC_BWTR3_BUSTURN_1 0x00020000U /*!<Bit 1 */
+#define FSMC_BWTR3_BUSTURN_2 0x00040000U /*!<Bit 2 */
+#define FSMC_BWTR3_BUSTURN_3 0x00080000U /*!<Bit 3 */
+
+#define FSMC_BWTR3_ACCMOD 0x30000000U /*!<ACCMOD[1:0] bits (Access mode) */
+#define FSMC_BWTR3_ACCMOD_0 0x10000000U /*!<Bit 0 */
+#define FSMC_BWTR3_ACCMOD_1 0x20000000U /*!<Bit 1 */
+
+/****************** Bit definition for FSMC_BWTR4 register ******************/
+#define FSMC_BWTR4_ADDSET 0x0000000FU /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FSMC_BWTR4_ADDSET_0 0x00000001U /*!<Bit 0 */
+#define FSMC_BWTR4_ADDSET_1 0x00000002U /*!<Bit 1 */
+#define FSMC_BWTR4_ADDSET_2 0x00000004U /*!<Bit 2 */
+#define FSMC_BWTR4_ADDSET_3 0x00000008U /*!<Bit 3 */
+
+#define FSMC_BWTR4_ADDHLD 0x000000F0U /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FSMC_BWTR4_ADDHLD_0 0x00000010U /*!<Bit 0 */
+#define FSMC_BWTR4_ADDHLD_1 0x00000020U /*!<Bit 1 */
+#define FSMC_BWTR4_ADDHLD_2 0x00000040U /*!<Bit 2 */
+#define FSMC_BWTR4_ADDHLD_3 0x00000080U /*!<Bit 3 */
+
+#define FSMC_BWTR4_DATAST 0x0000FF00U /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FSMC_BWTR4_DATAST_0 0x00000100U /*!<Bit 0 */
+#define FSMC_BWTR4_DATAST_1 0x00000200U /*!<Bit 1 */
+#define FSMC_BWTR4_DATAST_2 0x00000400U /*!<Bit 2 */
+#define FSMC_BWTR4_DATAST_3 0x00000800U /*!<Bit 3 */
+#define FSMC_BWTR4_DATAST_4 0x00001000U /*!<Bit 4 */
+#define FSMC_BWTR4_DATAST_5 0x00002000U /*!<Bit 5 */
+#define FSMC_BWTR4_DATAST_6 0x00004000U /*!<Bit 6 */
+#define FSMC_BWTR4_DATAST_7 0x00008000U /*!<Bit 7 */
+
+#define FSMC_BWTR4_BUSTURN 0x000F0000U /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
+#define FSMC_BWTR4_BUSTURN_0 0x00010000U /*!<Bit 0 */
+#define FSMC_BWTR4_BUSTURN_1 0x00020000U /*!<Bit 1 */
+#define FSMC_BWTR4_BUSTURN_2 0x00040000U /*!<Bit 2 */
+#define FSMC_BWTR4_BUSTURN_3 0x00080000U /*!<Bit 3 */
+
+#define FSMC_BWTR4_ACCMOD 0x30000000U /*!<ACCMOD[1:0] bits (Access mode) */
+#define FSMC_BWTR4_ACCMOD_0 0x10000000U /*!<Bit 0 */
+#define FSMC_BWTR4_ACCMOD_1 0x20000000U /*!<Bit 1 */
+
+/****************** Bit definition for FSMC_PCR2 register *******************/
+#define FSMC_PCR2_PWAITEN 0x00000002U /*!<Wait feature enable bit */
+#define FSMC_PCR2_PBKEN 0x00000004U /*!<PC Card/NAND Flash memory bank enable bit */
+#define FSMC_PCR2_PTYP 0x00000008U /*!<Memory type */
+
+#define FSMC_PCR2_PWID 0x00000030U /*!<PWID[1:0] bits (NAND Flash databus width) */
+#define FSMC_PCR2_PWID_0 0x00000010U /*!<Bit 0 */
+#define FSMC_PCR2_PWID_1 0x00000020U /*!<Bit 1 */
+
+#define FSMC_PCR2_ECCEN 0x00000040U /*!<ECC computation logic enable bit */
+
+#define FSMC_PCR2_TCLR 0x00001E00U /*!<TCLR[3:0] bits (CLE to RE delay) */
+#define FSMC_PCR2_TCLR_0 0x00000200U /*!<Bit 0 */
+#define FSMC_PCR2_TCLR_1 0x00000400U /*!<Bit 1 */
+#define FSMC_PCR2_TCLR_2 0x00000800U /*!<Bit 2 */
+#define FSMC_PCR2_TCLR_3 0x00001000U /*!<Bit 3 */
+
+#define FSMC_PCR2_TAR 0x0001E000U /*!<TAR[3:0] bits (ALE to RE delay) */
+#define FSMC_PCR2_TAR_0 0x00002000U /*!<Bit 0 */
+#define FSMC_PCR2_TAR_1 0x00004000U /*!<Bit 1 */
+#define FSMC_PCR2_TAR_2 0x00008000U /*!<Bit 2 */
+#define FSMC_PCR2_TAR_3 0x00010000U /*!<Bit 3 */
+
+#define FSMC_PCR2_ECCPS 0x000E0000U /*!<ECCPS[1:0] bits (ECC page size) */
+#define FSMC_PCR2_ECCPS_0 0x00020000U /*!<Bit 0 */
+#define FSMC_PCR2_ECCPS_1 0x00040000U /*!<Bit 1 */
+#define FSMC_PCR2_ECCPS_2 0x00080000U /*!<Bit 2 */
+
+/****************** Bit definition for FSMC_PCR3 register *******************/
+#define FSMC_PCR3_PWAITEN 0x00000002U /*!<Wait feature enable bit */
+#define FSMC_PCR3_PBKEN 0x00000004U /*!<PC Card/NAND Flash memory bank enable bit */
+#define FSMC_PCR3_PTYP 0x00000008U /*!<Memory type */
+
+#define FSMC_PCR3_PWID 0x00000030U /*!<PWID[1:0] bits (NAND Flash databus width) */
+#define FSMC_PCR3_PWID_0 0x00000010U /*!<Bit 0 */
+#define FSMC_PCR3_PWID_1 0x00000020U /*!<Bit 1 */
+
+#define FSMC_PCR3_ECCEN 0x00000040U /*!<ECC computation logic enable bit */
+
+#define FSMC_PCR3_TCLR 0x00001E00U /*!<TCLR[3:0] bits (CLE to RE delay) */
+#define FSMC_PCR3_TCLR_0 0x00000200U /*!<Bit 0 */
+#define FSMC_PCR3_TCLR_1 0x00000400U /*!<Bit 1 */
+#define FSMC_PCR3_TCLR_2 0x00000800U /*!<Bit 2 */
+#define FSMC_PCR3_TCLR_3 0x00001000U /*!<Bit 3 */
+
+#define FSMC_PCR3_TAR 0x0001E000U /*!<TAR[3:0] bits (ALE to RE delay) */
+#define FSMC_PCR3_TAR_0 0x00002000U /*!<Bit 0 */
+#define FSMC_PCR3_TAR_1 0x00004000U /*!<Bit 1 */
+#define FSMC_PCR3_TAR_2 0x00008000U /*!<Bit 2 */
+#define FSMC_PCR3_TAR_3 0x00010000U /*!<Bit 3 */
+
+#define FSMC_PCR3_ECCPS 0x000E0000U /*!<ECCPS[2:0] bits (ECC page size) */
+#define FSMC_PCR3_ECCPS_0 0x00020000U /*!<Bit 0 */
+#define FSMC_PCR3_ECCPS_1 0x00040000U /*!<Bit 1 */
+#define FSMC_PCR3_ECCPS_2 0x00080000U /*!<Bit 2 */
+
+/****************** Bit definition for FSMC_PCR4 register *******************/
+#define FSMC_PCR4_PWAITEN 0x00000002U /*!<Wait feature enable bit */
+#define FSMC_PCR4_PBKEN 0x00000004U /*!<PC Card/NAND Flash memory bank enable bit */
+#define FSMC_PCR4_PTYP 0x00000008U /*!<Memory type */
+
+#define FSMC_PCR4_PWID 0x00000030U /*!<PWID[1:0] bits (NAND Flash databus width) */
+#define FSMC_PCR4_PWID_0 0x00000010U /*!<Bit 0 */
+#define FSMC_PCR4_PWID_1 0x00000020U /*!<Bit 1 */
+
+#define FSMC_PCR4_ECCEN 0x00000040U /*!<ECC computation logic enable bit */
+
+#define FSMC_PCR4_TCLR 0x00001E00U /*!<TCLR[3:0] bits (CLE to RE delay) */
+#define FSMC_PCR4_TCLR_0 0x00000200U /*!<Bit 0 */
+#define FSMC_PCR4_TCLR_1 0x00000400U /*!<Bit 1 */
+#define FSMC_PCR4_TCLR_2 0x00000800U /*!<Bit 2 */
+#define FSMC_PCR4_TCLR_3 0x00001000U /*!<Bit 3 */
+
+#define FSMC_PCR4_TAR 0x0001E000U /*!<TAR[3:0] bits (ALE to RE delay) */
+#define FSMC_PCR4_TAR_0 0x00002000U /*!<Bit 0 */
+#define FSMC_PCR4_TAR_1 0x00004000U /*!<Bit 1 */
+#define FSMC_PCR4_TAR_2 0x00008000U /*!<Bit 2 */
+#define FSMC_PCR4_TAR_3 0x00010000U /*!<Bit 3 */
+
+#define FSMC_PCR4_ECCPS 0x000E0000U /*!<ECCPS[2:0] bits (ECC page size) */
+#define FSMC_PCR4_ECCPS_0 0x00020000U /*!<Bit 0 */
+#define FSMC_PCR4_ECCPS_1 0x00040000U /*!<Bit 1 */
+#define FSMC_PCR4_ECCPS_2 0x00080000U /*!<Bit 2 */
+
+/******************* Bit definition for FSMC_SR2 register *******************/
+#define FSMC_SR2_IRS 0x01U /*!<Interrupt Rising Edge status */
+#define FSMC_SR2_ILS 0x02U /*!<Interrupt Level status */
+#define FSMC_SR2_IFS 0x04U /*!<Interrupt Falling Edge status */
+#define FSMC_SR2_IREN 0x08U /*!<Interrupt Rising Edge detection Enable bit */
+#define FSMC_SR2_ILEN 0x10U /*!<Interrupt Level detection Enable bit */
+#define FSMC_SR2_IFEN 0x20U /*!<Interrupt Falling Edge detection Enable bit */
+#define FSMC_SR2_FEMPT 0x40U /*!<FIFO empty */
+
+/******************* Bit definition for FSMC_SR3 register *******************/
+#define FSMC_SR3_IRS 0x01U /*!<Interrupt Rising Edge status */
+#define FSMC_SR3_ILS 0x02U /*!<Interrupt Level status */
+#define FSMC_SR3_IFS 0x04U /*!<Interrupt Falling Edge status */
+#define FSMC_SR3_IREN 0x08U /*!<Interrupt Rising Edge detection Enable bit */
+#define FSMC_SR3_ILEN 0x10U /*!<Interrupt Level detection Enable bit */
+#define FSMC_SR3_IFEN 0x20U /*!<Interrupt Falling Edge detection Enable bit */
+#define FSMC_SR3_FEMPT 0x40U /*!<FIFO empty */
+
+/******************* Bit definition for FSMC_SR4 register *******************/
+#define FSMC_SR4_IRS 0x01U /*!<Interrupt Rising Edge status */
+#define FSMC_SR4_ILS 0x02U /*!<Interrupt Level status */
+#define FSMC_SR4_IFS 0x04U /*!<Interrupt Falling Edge status */
+#define FSMC_SR4_IREN 0x08U /*!<Interrupt Rising Edge detection Enable bit */
+#define FSMC_SR4_ILEN 0x10U /*!<Interrupt Level detection Enable bit */
+#define FSMC_SR4_IFEN 0x20U /*!<Interrupt Falling Edge detection Enable bit */
+#define FSMC_SR4_FEMPT 0x40U /*!<FIFO empty */
+
+/****************** Bit definition for FSMC_PMEM2 register ******************/
+#define FSMC_PMEM2_MEMSET2 0x000000FFU /*!<MEMSET2[7:0] bits (Common memory 2 setup time) */
+#define FSMC_PMEM2_MEMSET2_0 0x00000001U /*!<Bit 0 */
+#define FSMC_PMEM2_MEMSET2_1 0x00000002U /*!<Bit 1 */
+#define FSMC_PMEM2_MEMSET2_2 0x00000004U /*!<Bit 2 */
+#define FSMC_PMEM2_MEMSET2_3 0x00000008U /*!<Bit 3 */
+#define FSMC_PMEM2_MEMSET2_4 0x00000010U /*!<Bit 4 */
+#define FSMC_PMEM2_MEMSET2_5 0x00000020U /*!<Bit 5 */
+#define FSMC_PMEM2_MEMSET2_6 0x00000040U /*!<Bit 6 */
+#define FSMC_PMEM2_MEMSET2_7 0x00000080U /*!<Bit 7 */
+
+#define FSMC_PMEM2_MEMWAIT2 0x0000FF00U /*!<MEMWAIT2[7:0] bits (Common memory 2 wait time) */
+#define FSMC_PMEM2_MEMWAIT2_0 0x00000100U /*!<Bit 0 */
+#define FSMC_PMEM2_MEMWAIT2_1 0x00000200U /*!<Bit 1 */
+#define FSMC_PMEM2_MEMWAIT2_2 0x00000400U /*!<Bit 2 */
+#define FSMC_PMEM2_MEMWAIT2_3 0x00000800U /*!<Bit 3 */
+#define FSMC_PMEM2_MEMWAIT2_4 0x00001000U /*!<Bit 4 */
+#define FSMC_PMEM2_MEMWAIT2_5 0x00002000U /*!<Bit 5 */
+#define FSMC_PMEM2_MEMWAIT2_6 0x00004000U /*!<Bit 6 */
+#define FSMC_PMEM2_MEMWAIT2_7 0x00008000U /*!<Bit 7 */
+
+#define FSMC_PMEM2_MEMHOLD2 0x00FF0000U /*!<MEMHOLD2[7:0] bits (Common memory 2 hold time) */
+#define FSMC_PMEM2_MEMHOLD2_0 0x00010000U /*!<Bit 0 */
+#define FSMC_PMEM2_MEMHOLD2_1 0x00020000U /*!<Bit 1 */
+#define FSMC_PMEM2_MEMHOLD2_2 0x00040000U /*!<Bit 2 */
+#define FSMC_PMEM2_MEMHOLD2_3 0x00080000U /*!<Bit 3 */
+#define FSMC_PMEM2_MEMHOLD2_4 0x00100000U /*!<Bit 4 */
+#define FSMC_PMEM2_MEMHOLD2_5 0x00200000U /*!<Bit 5 */
+#define FSMC_PMEM2_MEMHOLD2_6 0x00400000U /*!<Bit 6 */
+#define FSMC_PMEM2_MEMHOLD2_7 0x00800000U /*!<Bit 7 */
+
+#define FSMC_PMEM2_MEMHIZ2 0xFF000000U /*!<MEMHIZ2[7:0] bits (Common memory 2 databus HiZ time) */
+#define FSMC_PMEM2_MEMHIZ2_0 0x01000000U /*!<Bit 0 */
+#define FSMC_PMEM2_MEMHIZ2_1 0x02000000U /*!<Bit 1 */
+#define FSMC_PMEM2_MEMHIZ2_2 0x04000000U /*!<Bit 2 */
+#define FSMC_PMEM2_MEMHIZ2_3 0x08000000U /*!<Bit 3 */
+#define FSMC_PMEM2_MEMHIZ2_4 0x10000000U /*!<Bit 4 */
+#define FSMC_PMEM2_MEMHIZ2_5 0x20000000U /*!<Bit 5 */
+#define FSMC_PMEM2_MEMHIZ2_6 0x40000000U /*!<Bit 6 */
+#define FSMC_PMEM2_MEMHIZ2_7 0x80000000U /*!<Bit 7 */
+
+/****************** Bit definition for FSMC_PMEM3 register ******************/
+#define FSMC_PMEM3_MEMSET3 0x000000FFU /*!<MEMSET3[7:0] bits (Common memory 3 setup time) */
+#define FSMC_PMEM3_MEMSET3_0 0x00000001U /*!<Bit 0 */
+#define FSMC_PMEM3_MEMSET3_1 0x00000002U /*!<Bit 1 */
+#define FSMC_PMEM3_MEMSET3_2 0x00000004U /*!<Bit 2 */
+#define FSMC_PMEM3_MEMSET3_3 0x00000008U /*!<Bit 3 */
+#define FSMC_PMEM3_MEMSET3_4 0x00000010U /*!<Bit 4 */
+#define FSMC_PMEM3_MEMSET3_5 0x00000020U /*!<Bit 5 */
+#define FSMC_PMEM3_MEMSET3_6 0x00000040U /*!<Bit 6 */
+#define FSMC_PMEM3_MEMSET3_7 0x00000080U /*!<Bit 7 */
+
+#define FSMC_PMEM3_MEMWAIT3 0x0000FF00U /*!<MEMWAIT3[7:0] bits (Common memory 3 wait time) */
+#define FSMC_PMEM3_MEMWAIT3_0 0x00000100U /*!<Bit 0 */
+#define FSMC_PMEM3_MEMWAIT3_1 0x00000200U /*!<Bit 1 */
+#define FSMC_PMEM3_MEMWAIT3_2 0x00000400U /*!<Bit 2 */
+#define FSMC_PMEM3_MEMWAIT3_3 0x00000800U /*!<Bit 3 */
+#define FSMC_PMEM3_MEMWAIT3_4 0x00001000U /*!<Bit 4 */
+#define FSMC_PMEM3_MEMWAIT3_5 0x00002000U /*!<Bit 5 */
+#define FSMC_PMEM3_MEMWAIT3_6 0x00004000U /*!<Bit 6 */
+#define FSMC_PMEM3_MEMWAIT3_7 0x00008000U /*!<Bit 7 */
+
+#define FSMC_PMEM3_MEMHOLD3 0x00FF0000U /*!<MEMHOLD3[7:0] bits (Common memory 3 hold time) */
+#define FSMC_PMEM3_MEMHOLD3_0 0x00010000U /*!<Bit 0 */
+#define FSMC_PMEM3_MEMHOLD3_1 0x00020000U /*!<Bit 1 */
+#define FSMC_PMEM3_MEMHOLD3_2 0x00040000U /*!<Bit 2 */
+#define FSMC_PMEM3_MEMHOLD3_3 0x00080000U /*!<Bit 3 */
+#define FSMC_PMEM3_MEMHOLD3_4 0x00100000U /*!<Bit 4 */
+#define FSMC_PMEM3_MEMHOLD3_5 0x00200000U /*!<Bit 5 */
+#define FSMC_PMEM3_MEMHOLD3_6 0x00400000U /*!<Bit 6 */
+#define FSMC_PMEM3_MEMHOLD3_7 0x00800000U /*!<Bit 7 */
+
+#define FSMC_PMEM3_MEMHIZ3 0xFF000000U /*!<MEMHIZ3[7:0] bits (Common memory 3 databus HiZ time) */
+#define FSMC_PMEM3_MEMHIZ3_0 0x01000000U /*!<Bit 0 */
+#define FSMC_PMEM3_MEMHIZ3_1 0x02000000U /*!<Bit 1 */
+#define FSMC_PMEM3_MEMHIZ3_2 0x04000000U /*!<Bit 2 */
+#define FSMC_PMEM3_MEMHIZ3_3 0x08000000U /*!<Bit 3 */
+#define FSMC_PMEM3_MEMHIZ3_4 0x10000000U /*!<Bit 4 */
+#define FSMC_PMEM3_MEMHIZ3_5 0x20000000U /*!<Bit 5 */
+#define FSMC_PMEM3_MEMHIZ3_6 0x40000000U /*!<Bit 6 */
+#define FSMC_PMEM3_MEMHIZ3_7 0x80000000U /*!<Bit 7 */
+
+/****************** Bit definition for FSMC_PMEM4 register ******************/
+#define FSMC_PMEM4_MEMSET4 0x000000FFU /*!<MEMSET4[7:0] bits (Common memory 4 setup time) */
+#define FSMC_PMEM4_MEMSET4_0 0x00000001U /*!<Bit 0 */
+#define FSMC_PMEM4_MEMSET4_1 0x00000002U /*!<Bit 1 */
+#define FSMC_PMEM4_MEMSET4_2 0x00000004U /*!<Bit 2 */
+#define FSMC_PMEM4_MEMSET4_3 0x00000008U /*!<Bit 3 */
+#define FSMC_PMEM4_MEMSET4_4 0x00000010U /*!<Bit 4 */
+#define FSMC_PMEM4_MEMSET4_5 0x00000020U /*!<Bit 5 */
+#define FSMC_PMEM4_MEMSET4_6 0x00000040U /*!<Bit 6 */
+#define FSMC_PMEM4_MEMSET4_7 0x00000080U /*!<Bit 7 */
+
+#define FSMC_PMEM4_MEMWAIT4 0x0000FF00U /*!<MEMWAIT4[7:0] bits (Common memory 4 wait time) */
+#define FSMC_PMEM4_MEMWAIT4_0 0x00000100U /*!<Bit 0 */
+#define FSMC_PMEM4_MEMWAIT4_1 0x00000200U /*!<Bit 1 */
+#define FSMC_PMEM4_MEMWAIT4_2 0x00000400U /*!<Bit 2 */
+#define FSMC_PMEM4_MEMWAIT4_3 0x00000800U /*!<Bit 3 */
+#define FSMC_PMEM4_MEMWAIT4_4 0x00001000U /*!<Bit 4 */
+#define FSMC_PMEM4_MEMWAIT4_5 0x00002000U /*!<Bit 5 */
+#define FSMC_PMEM4_MEMWAIT4_6 0x00004000U /*!<Bit 6 */
+#define FSMC_PMEM4_MEMWAIT4_7 0x00008000U /*!<Bit 7 */
+
+#define FSMC_PMEM4_MEMHOLD4 0x00FF0000U /*!<MEMHOLD4[7:0] bits (Common memory 4 hold time) */
+#define FSMC_PMEM4_MEMHOLD4_0 0x00010000U /*!<Bit 0 */
+#define FSMC_PMEM4_MEMHOLD4_1 0x00020000U /*!<Bit 1 */
+#define FSMC_PMEM4_MEMHOLD4_2 0x00040000U /*!<Bit 2 */
+#define FSMC_PMEM4_MEMHOLD4_3 0x00080000U /*!<Bit 3 */
+#define FSMC_PMEM4_MEMHOLD4_4 0x00100000U /*!<Bit 4 */
+#define FSMC_PMEM4_MEMHOLD4_5 0x00200000U /*!<Bit 5 */
+#define FSMC_PMEM4_MEMHOLD4_6 0x00400000U /*!<Bit 6 */
+#define FSMC_PMEM4_MEMHOLD4_7 0x00800000U /*!<Bit 7 */
+
+#define FSMC_PMEM4_MEMHIZ4 0xFF000000U /*!<MEMHIZ4[7:0] bits (Common memory 4 databus HiZ time) */
+#define FSMC_PMEM4_MEMHIZ4_0 0x01000000U /*!<Bit 0 */
+#define FSMC_PMEM4_MEMHIZ4_1 0x02000000U /*!<Bit 1 */
+#define FSMC_PMEM4_MEMHIZ4_2 0x04000000U /*!<Bit 2 */
+#define FSMC_PMEM4_MEMHIZ4_3 0x08000000U /*!<Bit 3 */
+#define FSMC_PMEM4_MEMHIZ4_4 0x10000000U /*!<Bit 4 */
+#define FSMC_PMEM4_MEMHIZ4_5 0x20000000U /*!<Bit 5 */
+#define FSMC_PMEM4_MEMHIZ4_6 0x40000000U /*!<Bit 6 */
+#define FSMC_PMEM4_MEMHIZ4_7 0x80000000U /*!<Bit 7 */
+
+/****************** Bit definition for FSMC_PATT2 register ******************/
+#define FSMC_PATT2_ATTSET2 0x000000FFU /*!<ATTSET2[7:0] bits (Attribute memory 2 setup time) */
+#define FSMC_PATT2_ATTSET2_0 0x00000001U /*!<Bit 0 */
+#define FSMC_PATT2_ATTSET2_1 0x00000002U /*!<Bit 1 */
+#define FSMC_PATT2_ATTSET2_2 0x00000004U /*!<Bit 2 */
+#define FSMC_PATT2_ATTSET2_3 0x00000008U /*!<Bit 3 */
+#define FSMC_PATT2_ATTSET2_4 0x00000010U /*!<Bit 4 */
+#define FSMC_PATT2_ATTSET2_5 0x00000020U /*!<Bit 5 */
+#define FSMC_PATT2_ATTSET2_6 0x00000040U /*!<Bit 6 */
+#define FSMC_PATT2_ATTSET2_7 0x00000080U /*!<Bit 7 */
+
+#define FSMC_PATT2_ATTWAIT2 0x0000FF00U /*!<ATTWAIT2[7:0] bits (Attribute memory 2 wait time) */
+#define FSMC_PATT2_ATTWAIT2_0 0x00000100U /*!<Bit 0 */
+#define FSMC_PATT2_ATTWAIT2_1 0x00000200U /*!<Bit 1 */
+#define FSMC_PATT2_ATTWAIT2_2 0x00000400U /*!<Bit 2 */
+#define FSMC_PATT2_ATTWAIT2_3 0x00000800U /*!<Bit 3 */
+#define FSMC_PATT2_ATTWAIT2_4 0x00001000U /*!<Bit 4 */
+#define FSMC_PATT2_ATTWAIT2_5 0x00002000U /*!<Bit 5 */
+#define FSMC_PATT2_ATTWAIT2_6 0x00004000U /*!<Bit 6 */
+#define FSMC_PATT2_ATTWAIT2_7 0x00008000U /*!<Bit 7 */
+
+#define FSMC_PATT2_ATTHOLD2 0x00FF0000U /*!<ATTHOLD2[7:0] bits (Attribute memory 2 hold time) */
+#define FSMC_PATT2_ATTHOLD2_0 0x00010000U /*!<Bit 0 */
+#define FSMC_PATT2_ATTHOLD2_1 0x00020000U /*!<Bit 1 */
+#define FSMC_PATT2_ATTHOLD2_2 0x00040000U /*!<Bit 2 */
+#define FSMC_PATT2_ATTHOLD2_3 0x00080000U /*!<Bit 3 */
+#define FSMC_PATT2_ATTHOLD2_4 0x00100000U /*!<Bit 4 */
+#define FSMC_PATT2_ATTHOLD2_5 0x00200000U /*!<Bit 5 */
+#define FSMC_PATT2_ATTHOLD2_6 0x00400000U /*!<Bit 6 */
+#define FSMC_PATT2_ATTHOLD2_7 0x00800000U /*!<Bit 7 */
+
+#define FSMC_PATT2_ATTHIZ2 0xFF000000U /*!<ATTHIZ2[7:0] bits (Attribute memory 2 databus HiZ time) */
+#define FSMC_PATT2_ATTHIZ2_0 0x01000000U /*!<Bit 0 */
+#define FSMC_PATT2_ATTHIZ2_1 0x02000000U /*!<Bit 1 */
+#define FSMC_PATT2_ATTHIZ2_2 0x04000000U /*!<Bit 2 */
+#define FSMC_PATT2_ATTHIZ2_3 0x08000000U /*!<Bit 3 */
+#define FSMC_PATT2_ATTHIZ2_4 0x10000000U /*!<Bit 4 */
+#define FSMC_PATT2_ATTHIZ2_5 0x20000000U /*!<Bit 5 */
+#define FSMC_PATT2_ATTHIZ2_6 0x40000000U /*!<Bit 6 */
+#define FSMC_PATT2_ATTHIZ2_7 0x80000000U /*!<Bit 7 */
+
+/****************** Bit definition for FSMC_PATT3 register ******************/
+#define FSMC_PATT3_ATTSET3 0x000000FFU /*!<ATTSET3[7:0] bits (Attribute memory 3 setup time) */
+#define FSMC_PATT3_ATTSET3_0 0x00000001U /*!<Bit 0 */
+#define FSMC_PATT3_ATTSET3_1 0x00000002U /*!<Bit 1 */
+#define FSMC_PATT3_ATTSET3_2 0x00000004U /*!<Bit 2 */
+#define FSMC_PATT3_ATTSET3_3 0x00000008U /*!<Bit 3 */
+#define FSMC_PATT3_ATTSET3_4 0x00000010U /*!<Bit 4 */
+#define FSMC_PATT3_ATTSET3_5 0x00000020U /*!<Bit 5 */
+#define FSMC_PATT3_ATTSET3_6 0x00000040U /*!<Bit 6 */
+#define FSMC_PATT3_ATTSET3_7 0x00000080U /*!<Bit 7 */
+
+#define FSMC_PATT3_ATTWAIT3 0x0000FF00U /*!<ATTWAIT3[7:0] bits (Attribute memory 3 wait time) */
+#define FSMC_PATT3_ATTWAIT3_0 0x00000100U /*!<Bit 0 */
+#define FSMC_PATT3_ATTWAIT3_1 0x00000200U /*!<Bit 1 */
+#define FSMC_PATT3_ATTWAIT3_2 0x00000400U /*!<Bit 2 */
+#define FSMC_PATT3_ATTWAIT3_3 0x00000800U /*!<Bit 3 */
+#define FSMC_PATT3_ATTWAIT3_4 0x00001000U /*!<Bit 4 */
+#define FSMC_PATT3_ATTWAIT3_5 0x00002000U /*!<Bit 5 */
+#define FSMC_PATT3_ATTWAIT3_6 0x00004000U /*!<Bit 6 */
+#define FSMC_PATT3_ATTWAIT3_7 0x00008000U /*!<Bit 7 */
+
+#define FSMC_PATT3_ATTHOLD3 0x00FF0000U /*!<ATTHOLD3[7:0] bits (Attribute memory 3 hold time) */
+#define FSMC_PATT3_ATTHOLD3_0 0x00010000U /*!<Bit 0 */
+#define FSMC_PATT3_ATTHOLD3_1 0x00020000U /*!<Bit 1 */
+#define FSMC_PATT3_ATTHOLD3_2 0x00040000U /*!<Bit 2 */
+#define FSMC_PATT3_ATTHOLD3_3 0x00080000U /*!<Bit 3 */
+#define FSMC_PATT3_ATTHOLD3_4 0x00100000U /*!<Bit 4 */
+#define FSMC_PATT3_ATTHOLD3_5 0x00200000U /*!<Bit 5 */
+#define FSMC_PATT3_ATTHOLD3_6 0x00400000U /*!<Bit 6 */
+#define FSMC_PATT3_ATTHOLD3_7 0x00800000U /*!<Bit 7 */
+
+#define FSMC_PATT3_ATTHIZ3 0xFF000000U /*!<ATTHIZ3[7:0] bits (Attribute memory 3 databus HiZ time) */
+#define FSMC_PATT3_ATTHIZ3_0 0x01000000U /*!<Bit 0 */
+#define FSMC_PATT3_ATTHIZ3_1 0x02000000U /*!<Bit 1 */
+#define FSMC_PATT3_ATTHIZ3_2 0x04000000U /*!<Bit 2 */
+#define FSMC_PATT3_ATTHIZ3_3 0x08000000U /*!<Bit 3 */
+#define FSMC_PATT3_ATTHIZ3_4 0x10000000U /*!<Bit 4 */
+#define FSMC_PATT3_ATTHIZ3_5 0x20000000U /*!<Bit 5 */
+#define FSMC_PATT3_ATTHIZ3_6 0x40000000U /*!<Bit 6 */
+#define FSMC_PATT3_ATTHIZ3_7 0x80000000U /*!<Bit 7 */
+
+/****************** Bit definition for FSMC_PATT4 register ******************/
+#define FSMC_PATT4_ATTSET4 0x000000FFU /*!<ATTSET4[7:0] bits (Attribute memory 4 setup time) */
+#define FSMC_PATT4_ATTSET4_0 0x00000001U /*!<Bit 0 */
+#define FSMC_PATT4_ATTSET4_1 0x00000002U /*!<Bit 1 */
+#define FSMC_PATT4_ATTSET4_2 0x00000004U /*!<Bit 2 */
+#define FSMC_PATT4_ATTSET4_3 0x00000008U /*!<Bit 3 */
+#define FSMC_PATT4_ATTSET4_4 0x00000010U /*!<Bit 4 */
+#define FSMC_PATT4_ATTSET4_5 0x00000020U /*!<Bit 5 */
+#define FSMC_PATT4_ATTSET4_6 0x00000040U /*!<Bit 6 */
+#define FSMC_PATT4_ATTSET4_7 0x00000080U /*!<Bit 7 */
+
+#define FSMC_PATT4_ATTWAIT4 0x0000FF00U /*!<ATTWAIT4[7:0] bits (Attribute memory 4 wait time) */
+#define FSMC_PATT4_ATTWAIT4_0 0x00000100U /*!<Bit 0 */
+#define FSMC_PATT4_ATTWAIT4_1 0x00000200U /*!<Bit 1 */
+#define FSMC_PATT4_ATTWAIT4_2 0x00000400U /*!<Bit 2 */
+#define FSMC_PATT4_ATTWAIT4_3 0x00000800U /*!<Bit 3 */
+#define FSMC_PATT4_ATTWAIT4_4 0x00001000U /*!<Bit 4 */
+#define FSMC_PATT4_ATTWAIT4_5 0x00002000U /*!<Bit 5 */
+#define FSMC_PATT4_ATTWAIT4_6 0x00004000U /*!<Bit 6 */
+#define FSMC_PATT4_ATTWAIT4_7 0x00008000U /*!<Bit 7 */
+
+#define FSMC_PATT4_ATTHOLD4 0x00FF0000U /*!<ATTHOLD4[7:0] bits (Attribute memory 4 hold time) */
+#define FSMC_PATT4_ATTHOLD4_0 0x00010000U /*!<Bit 0 */
+#define FSMC_PATT4_ATTHOLD4_1 0x00020000U /*!<Bit 1 */
+#define FSMC_PATT4_ATTHOLD4_2 0x00040000U /*!<Bit 2 */
+#define FSMC_PATT4_ATTHOLD4_3 0x00080000U /*!<Bit 3 */
+#define FSMC_PATT4_ATTHOLD4_4 0x00100000U /*!<Bit 4 */
+#define FSMC_PATT4_ATTHOLD4_5 0x00200000U /*!<Bit 5 */
+#define FSMC_PATT4_ATTHOLD4_6 0x00400000U /*!<Bit 6 */
+#define FSMC_PATT4_ATTHOLD4_7 0x00800000U /*!<Bit 7 */
+
+#define FSMC_PATT4_ATTHIZ4 0xFF000000U /*!<ATTHIZ4[7:0] bits (Attribute memory 4 databus HiZ time) */
+#define FSMC_PATT4_ATTHIZ4_0 0x01000000U /*!<Bit 0 */
+#define FSMC_PATT4_ATTHIZ4_1 0x02000000U /*!<Bit 1 */
+#define FSMC_PATT4_ATTHIZ4_2 0x04000000U /*!<Bit 2 */
+#define FSMC_PATT4_ATTHIZ4_3 0x08000000U /*!<Bit 3 */
+#define FSMC_PATT4_ATTHIZ4_4 0x10000000U /*!<Bit 4 */
+#define FSMC_PATT4_ATTHIZ4_5 0x20000000U /*!<Bit 5 */
+#define FSMC_PATT4_ATTHIZ4_6 0x40000000U /*!<Bit 6 */
+#define FSMC_PATT4_ATTHIZ4_7 0x80000000U /*!<Bit 7 */
+
+/****************** Bit definition for FSMC_PIO4 register *******************/
+#define FSMC_PIO4_IOSET4 0x000000FFU /*!<IOSET4[7:0] bits (I/O 4 setup time) */
+#define FSMC_PIO4_IOSET4_0 0x00000001U /*!<Bit 0 */
+#define FSMC_PIO4_IOSET4_1 0x00000002U /*!<Bit 1 */
+#define FSMC_PIO4_IOSET4_2 0x00000004U /*!<Bit 2 */
+#define FSMC_PIO4_IOSET4_3 0x00000008U /*!<Bit 3 */
+#define FSMC_PIO4_IOSET4_4 0x00000010U /*!<Bit 4 */
+#define FSMC_PIO4_IOSET4_5 0x00000020U /*!<Bit 5 */
+#define FSMC_PIO4_IOSET4_6 0x00000040U /*!<Bit 6 */
+#define FSMC_PIO4_IOSET4_7 0x00000080U /*!<Bit 7 */
+
+#define FSMC_PIO4_IOWAIT4 0x0000FF00U /*!<IOWAIT4[7:0] bits (I/O 4 wait time) */
+#define FSMC_PIO4_IOWAIT4_0 0x00000100U /*!<Bit 0 */
+#define FSMC_PIO4_IOWAIT4_1 0x00000200U /*!<Bit 1 */
+#define FSMC_PIO4_IOWAIT4_2 0x00000400U /*!<Bit 2 */
+#define FSMC_PIO4_IOWAIT4_3 0x00000800U /*!<Bit 3 */
+#define FSMC_PIO4_IOWAIT4_4 0x00001000U /*!<Bit 4 */
+#define FSMC_PIO4_IOWAIT4_5 0x00002000U /*!<Bit 5 */
+#define FSMC_PIO4_IOWAIT4_6 0x00004000U /*!<Bit 6 */
+#define FSMC_PIO4_IOWAIT4_7 0x00008000U /*!<Bit 7 */
+
+#define FSMC_PIO4_IOHOLD4 0x00FF0000U /*!<IOHOLD4[7:0] bits (I/O 4 hold time) */
+#define FSMC_PIO4_IOHOLD4_0 0x00010000U /*!<Bit 0 */
+#define FSMC_PIO4_IOHOLD4_1 0x00020000U /*!<Bit 1 */
+#define FSMC_PIO4_IOHOLD4_2 0x00040000U /*!<Bit 2 */
+#define FSMC_PIO4_IOHOLD4_3 0x00080000U /*!<Bit 3 */
+#define FSMC_PIO4_IOHOLD4_4 0x00100000U /*!<Bit 4 */
+#define FSMC_PIO4_IOHOLD4_5 0x00200000U /*!<Bit 5 */
+#define FSMC_PIO4_IOHOLD4_6 0x00400000U /*!<Bit 6 */
+#define FSMC_PIO4_IOHOLD4_7 0x00800000U /*!<Bit 7 */
+
+#define FSMC_PIO4_IOHIZ4 0xFF000000U /*!<IOHIZ4[7:0] bits (I/O 4 databus HiZ time) */
+#define FSMC_PIO4_IOHIZ4_0 0x01000000U /*!<Bit 0 */
+#define FSMC_PIO4_IOHIZ4_1 0x02000000U /*!<Bit 1 */
+#define FSMC_PIO4_IOHIZ4_2 0x04000000U /*!<Bit 2 */
+#define FSMC_PIO4_IOHIZ4_3 0x08000000U /*!<Bit 3 */
+#define FSMC_PIO4_IOHIZ4_4 0x10000000U /*!<Bit 4 */
+#define FSMC_PIO4_IOHIZ4_5 0x20000000U /*!<Bit 5 */
+#define FSMC_PIO4_IOHIZ4_6 0x40000000U /*!<Bit 6 */
+#define FSMC_PIO4_IOHIZ4_7 0x80000000U /*!<Bit 7 */
+
+/****************** Bit definition for FSMC_ECCR2 register ******************/
+#define FSMC_ECCR2_ECC2 0xFFFFFFFFU /*!<ECC result */
+
+/****************** Bit definition for FSMC_ECCR3 register ******************/
+#define FSMC_ECCR3_ECC3 0xFFFFFFFFU /*!<ECC result */
+
+/******************************************************************************/
+/* */
+/* General Purpose I/O */
+/* */
+/******************************************************************************/
+/****************** Bits definition for GPIO_MODER register *****************/
+#define GPIO_MODER_MODER0 0x00000003U
+#define GPIO_MODER_MODER0_0 0x00000001U
+#define GPIO_MODER_MODER0_1 0x00000002U
+
+#define GPIO_MODER_MODER1 0x0000000CU
+#define GPIO_MODER_MODER1_0 0x00000004U
+#define GPIO_MODER_MODER1_1 0x00000008U
+
+#define GPIO_MODER_MODER2 0x00000030U
+#define GPIO_MODER_MODER2_0 0x00000010U
+#define GPIO_MODER_MODER2_1 0x00000020U
+
+#define GPIO_MODER_MODER3 0x000000C0U
+#define GPIO_MODER_MODER3_0 0x00000040U
+#define GPIO_MODER_MODER3_1 0x00000080U
+
+#define GPIO_MODER_MODER4 0x00000300U
+#define GPIO_MODER_MODER4_0 0x00000100U
+#define GPIO_MODER_MODER4_1 0x00000200U
+
+#define GPIO_MODER_MODER5 0x00000C00U
+#define GPIO_MODER_MODER5_0 0x00000400U
+#define GPIO_MODER_MODER5_1 0x00000800U
+
+#define GPIO_MODER_MODER6 0x00003000U
+#define GPIO_MODER_MODER6_0 0x00001000U
+#define GPIO_MODER_MODER6_1 0x00002000U
+
+#define GPIO_MODER_MODER7 0x0000C000U
+#define GPIO_MODER_MODER7_0 0x00004000U
+#define GPIO_MODER_MODER7_1 0x00008000U
+
+#define GPIO_MODER_MODER8 0x00030000U
+#define GPIO_MODER_MODER8_0 0x00010000U
+#define GPIO_MODER_MODER8_1 0x00020000U
+
+#define GPIO_MODER_MODER9 0x000C0000U
+#define GPIO_MODER_MODER9_0 0x00040000U
+#define GPIO_MODER_MODER9_1 0x00080000U
+
+#define GPIO_MODER_MODER10 0x00300000U
+#define GPIO_MODER_MODER10_0 0x00100000U
+#define GPIO_MODER_MODER10_1 0x00200000U
+
+#define GPIO_MODER_MODER11 0x00C00000U
+#define GPIO_MODER_MODER11_0 0x00400000U
+#define GPIO_MODER_MODER11_1 0x00800000U
+
+#define GPIO_MODER_MODER12 0x03000000U
+#define GPIO_MODER_MODER12_0 0x01000000U
+#define GPIO_MODER_MODER12_1 0x02000000U
+
+#define GPIO_MODER_MODER13 0x0C000000U
+#define GPIO_MODER_MODER13_0 0x04000000U
+#define GPIO_MODER_MODER13_1 0x08000000U
+
+#define GPIO_MODER_MODER14 0x30000000U
+#define GPIO_MODER_MODER14_0 0x10000000U
+#define GPIO_MODER_MODER14_1 0x20000000U
+
+#define GPIO_MODER_MODER15 0xC0000000U
+#define GPIO_MODER_MODER15_0 0x40000000U
+#define GPIO_MODER_MODER15_1 0x80000000U
+
+/****************** Bits definition for GPIO_OTYPER register ****************/
+#define GPIO_OTYPER_OT_0 0x00000001U
+#define GPIO_OTYPER_OT_1 0x00000002U
+#define GPIO_OTYPER_OT_2 0x00000004U
+#define GPIO_OTYPER_OT_3 0x00000008U
+#define GPIO_OTYPER_OT_4 0x00000010U
+#define GPIO_OTYPER_OT_5 0x00000020U
+#define GPIO_OTYPER_OT_6 0x00000040U
+#define GPIO_OTYPER_OT_7 0x00000080U
+#define GPIO_OTYPER_OT_8 0x00000100U
+#define GPIO_OTYPER_OT_9 0x00000200U
+#define GPIO_OTYPER_OT_10 0x00000400U
+#define GPIO_OTYPER_OT_11 0x00000800U
+#define GPIO_OTYPER_OT_12 0x00001000U
+#define GPIO_OTYPER_OT_13 0x00002000U
+#define GPIO_OTYPER_OT_14 0x00004000U
+#define GPIO_OTYPER_OT_15 0x00008000U
+
+/****************** Bits definition for GPIO_OSPEEDR register ***************/
+#define GPIO_OSPEEDER_OSPEEDR0 0x00000003U
+#define GPIO_OSPEEDER_OSPEEDR0_0 0x00000001U
+#define GPIO_OSPEEDER_OSPEEDR0_1 0x00000002U
+
+#define GPIO_OSPEEDER_OSPEEDR1 0x0000000CU
+#define GPIO_OSPEEDER_OSPEEDR1_0 0x00000004U
+#define GPIO_OSPEEDER_OSPEEDR1_1 0x00000008U
+
+#define GPIO_OSPEEDER_OSPEEDR2 0x00000030U
+#define GPIO_OSPEEDER_OSPEEDR2_0 0x00000010U
+#define GPIO_OSPEEDER_OSPEEDR2_1 0x00000020U
+
+#define GPIO_OSPEEDER_OSPEEDR3 0x000000C0U
+#define GPIO_OSPEEDER_OSPEEDR3_0 0x00000040U
+#define GPIO_OSPEEDER_OSPEEDR3_1 0x00000080U
+
+#define GPIO_OSPEEDER_OSPEEDR4 0x00000300U
+#define GPIO_OSPEEDER_OSPEEDR4_0 0x00000100U
+#define GPIO_OSPEEDER_OSPEEDR4_1 0x00000200U
+
+#define GPIO_OSPEEDER_OSPEEDR5 0x00000C00U
+#define GPIO_OSPEEDER_OSPEEDR5_0 0x00000400U
+#define GPIO_OSPEEDER_OSPEEDR5_1 0x00000800U
+
+#define GPIO_OSPEEDER_OSPEEDR6 0x00003000U
+#define GPIO_OSPEEDER_OSPEEDR6_0 0x00001000U
+#define GPIO_OSPEEDER_OSPEEDR6_1 0x00002000U
+
+#define GPIO_OSPEEDER_OSPEEDR7 0x0000C000U
+#define GPIO_OSPEEDER_OSPEEDR7_0 0x00004000U
+#define GPIO_OSPEEDER_OSPEEDR7_1 0x00008000U
+
+#define GPIO_OSPEEDER_OSPEEDR8 0x00030000U
+#define GPIO_OSPEEDER_OSPEEDR8_0 0x00010000U
+#define GPIO_OSPEEDER_OSPEEDR8_1 0x00020000U
+
+#define GPIO_OSPEEDER_OSPEEDR9 0x000C0000U
+#define GPIO_OSPEEDER_OSPEEDR9_0 0x00040000U
+#define GPIO_OSPEEDER_OSPEEDR9_1 0x00080000U
+
+#define GPIO_OSPEEDER_OSPEEDR10 0x00300000U
+#define GPIO_OSPEEDER_OSPEEDR10_0 0x00100000U
+#define GPIO_OSPEEDER_OSPEEDR10_1 0x00200000U
+
+#define GPIO_OSPEEDER_OSPEEDR11 0x00C00000U
+#define GPIO_OSPEEDER_OSPEEDR11_0 0x00400000U
+#define GPIO_OSPEEDER_OSPEEDR11_1 0x00800000U
+
+#define GPIO_OSPEEDER_OSPEEDR12 0x03000000U
+#define GPIO_OSPEEDER_OSPEEDR12_0 0x01000000U
+#define GPIO_OSPEEDER_OSPEEDR12_1 0x02000000U
+
+#define GPIO_OSPEEDER_OSPEEDR13 0x0C000000U
+#define GPIO_OSPEEDER_OSPEEDR13_0 0x04000000U
+#define GPIO_OSPEEDER_OSPEEDR13_1 0x08000000U
+
+#define GPIO_OSPEEDER_OSPEEDR14 0x30000000U
+#define GPIO_OSPEEDER_OSPEEDR14_0 0x10000000U
+#define GPIO_OSPEEDER_OSPEEDR14_1 0x20000000U
+
+#define GPIO_OSPEEDER_OSPEEDR15 0xC0000000U
+#define GPIO_OSPEEDER_OSPEEDR15_0 0x40000000U
+#define GPIO_OSPEEDER_OSPEEDR15_1 0x80000000U
+
+/****************** Bits definition for GPIO_PUPDR register *****************/
+#define GPIO_PUPDR_PUPDR0 0x00000003U
+#define GPIO_PUPDR_PUPDR0_0 0x00000001U
+#define GPIO_PUPDR_PUPDR0_1 0x00000002U
+
+#define GPIO_PUPDR_PUPDR1 0x0000000CU
+#define GPIO_PUPDR_PUPDR1_0 0x00000004U
+#define GPIO_PUPDR_PUPDR1_1 0x00000008U
+
+#define GPIO_PUPDR_PUPDR2 0x00000030U
+#define GPIO_PUPDR_PUPDR2_0 0x00000010U
+#define GPIO_PUPDR_PUPDR2_1 0x00000020U
+
+#define GPIO_PUPDR_PUPDR3 0x000000C0U
+#define GPIO_PUPDR_PUPDR3_0 0x00000040U
+#define GPIO_PUPDR_PUPDR3_1 0x00000080U
+
+#define GPIO_PUPDR_PUPDR4 0x00000300U
+#define GPIO_PUPDR_PUPDR4_0 0x00000100U
+#define GPIO_PUPDR_PUPDR4_1 0x00000200U
+
+#define GPIO_PUPDR_PUPDR5 0x00000C00U
+#define GPIO_PUPDR_PUPDR5_0 0x00000400U
+#define GPIO_PUPDR_PUPDR5_1 0x00000800U
+
+#define GPIO_PUPDR_PUPDR6 0x00003000U
+#define GPIO_PUPDR_PUPDR6_0 0x00001000U
+#define GPIO_PUPDR_PUPDR6_1 0x00002000U
+
+#define GPIO_PUPDR_PUPDR7 0x0000C000U
+#define GPIO_PUPDR_PUPDR7_0 0x00004000U
+#define GPIO_PUPDR_PUPDR7_1 0x00008000U
+
+#define GPIO_PUPDR_PUPDR8 0x00030000U
+#define GPIO_PUPDR_PUPDR8_0 0x00010000U
+#define GPIO_PUPDR_PUPDR8_1 0x00020000U
+
+#define GPIO_PUPDR_PUPDR9 0x000C0000U
+#define GPIO_PUPDR_PUPDR9_0 0x00040000U
+#define GPIO_PUPDR_PUPDR9_1 0x00080000U
+
+#define GPIO_PUPDR_PUPDR10 0x00300000U
+#define GPIO_PUPDR_PUPDR10_0 0x00100000U
+#define GPIO_PUPDR_PUPDR10_1 0x00200000U
+
+#define GPIO_PUPDR_PUPDR11 0x00C00000U
+#define GPIO_PUPDR_PUPDR11_0 0x00400000U
+#define GPIO_PUPDR_PUPDR11_1 0x00800000U
+
+#define GPIO_PUPDR_PUPDR12 0x03000000U
+#define GPIO_PUPDR_PUPDR12_0 0x01000000U
+#define GPIO_PUPDR_PUPDR12_1 0x02000000U
+
+#define GPIO_PUPDR_PUPDR13 0x0C000000U
+#define GPIO_PUPDR_PUPDR13_0 0x04000000U
+#define GPIO_PUPDR_PUPDR13_1 0x08000000U
+
+#define GPIO_PUPDR_PUPDR14 0x30000000U
+#define GPIO_PUPDR_PUPDR14_0 0x10000000U
+#define GPIO_PUPDR_PUPDR14_1 0x20000000U
+
+#define GPIO_PUPDR_PUPDR15 0xC0000000U
+#define GPIO_PUPDR_PUPDR15_0 0x40000000U
+#define GPIO_PUPDR_PUPDR15_1 0x80000000U
+
+/****************** Bits definition for GPIO_IDR register *******************/
+#define GPIO_IDR_IDR_0 0x00000001U
+#define GPIO_IDR_IDR_1 0x00000002U
+#define GPIO_IDR_IDR_2 0x00000004U
+#define GPIO_IDR_IDR_3 0x00000008U
+#define GPIO_IDR_IDR_4 0x00000010U
+#define GPIO_IDR_IDR_5 0x00000020U
+#define GPIO_IDR_IDR_6 0x00000040U
+#define GPIO_IDR_IDR_7 0x00000080U
+#define GPIO_IDR_IDR_8 0x00000100U
+#define GPIO_IDR_IDR_9 0x00000200U
+#define GPIO_IDR_IDR_10 0x00000400U
+#define GPIO_IDR_IDR_11 0x00000800U
+#define GPIO_IDR_IDR_12 0x00001000U
+#define GPIO_IDR_IDR_13 0x00002000U
+#define GPIO_IDR_IDR_14 0x00004000U
+#define GPIO_IDR_IDR_15 0x00008000U
+/* Old GPIO_IDR register bits definition, maintained for legacy purpose */
+#define GPIO_OTYPER_IDR_0 GPIO_IDR_IDR_0
+#define GPIO_OTYPER_IDR_1 GPIO_IDR_IDR_1
+#define GPIO_OTYPER_IDR_2 GPIO_IDR_IDR_2
+#define GPIO_OTYPER_IDR_3 GPIO_IDR_IDR_3
+#define GPIO_OTYPER_IDR_4 GPIO_IDR_IDR_4
+#define GPIO_OTYPER_IDR_5 GPIO_IDR_IDR_5
+#define GPIO_OTYPER_IDR_6 GPIO_IDR_IDR_6
+#define GPIO_OTYPER_IDR_7 GPIO_IDR_IDR_7
+#define GPIO_OTYPER_IDR_8 GPIO_IDR_IDR_8
+#define GPIO_OTYPER_IDR_9 GPIO_IDR_IDR_9
+#define GPIO_OTYPER_IDR_10 GPIO_IDR_IDR_10
+#define GPIO_OTYPER_IDR_11 GPIO_IDR_IDR_11
+#define GPIO_OTYPER_IDR_12 GPIO_IDR_IDR_12
+#define GPIO_OTYPER_IDR_13 GPIO_IDR_IDR_13
+#define GPIO_OTYPER_IDR_14 GPIO_IDR_IDR_14
+#define GPIO_OTYPER_IDR_15 GPIO_IDR_IDR_15
+
+/****************** Bits definition for GPIO_ODR register *******************/
+#define GPIO_ODR_ODR_0 0x00000001U
+#define GPIO_ODR_ODR_1 0x00000002U
+#define GPIO_ODR_ODR_2 0x00000004U
+#define GPIO_ODR_ODR_3 0x00000008U
+#define GPIO_ODR_ODR_4 0x00000010U
+#define GPIO_ODR_ODR_5 0x00000020U
+#define GPIO_ODR_ODR_6 0x00000040U
+#define GPIO_ODR_ODR_7 0x00000080U
+#define GPIO_ODR_ODR_8 0x00000100U
+#define GPIO_ODR_ODR_9 0x00000200U
+#define GPIO_ODR_ODR_10 0x00000400U
+#define GPIO_ODR_ODR_11 0x00000800U
+#define GPIO_ODR_ODR_12 0x00001000U
+#define GPIO_ODR_ODR_13 0x00002000U
+#define GPIO_ODR_ODR_14 0x00004000U
+#define GPIO_ODR_ODR_15 0x00008000U
+/* Old GPIO_ODR register bits definition, maintained for legacy purpose */
+#define GPIO_OTYPER_ODR_0 GPIO_ODR_ODR_0
+#define GPIO_OTYPER_ODR_1 GPIO_ODR_ODR_1
+#define GPIO_OTYPER_ODR_2 GPIO_ODR_ODR_2
+#define GPIO_OTYPER_ODR_3 GPIO_ODR_ODR_3
+#define GPIO_OTYPER_ODR_4 GPIO_ODR_ODR_4
+#define GPIO_OTYPER_ODR_5 GPIO_ODR_ODR_5
+#define GPIO_OTYPER_ODR_6 GPIO_ODR_ODR_6
+#define GPIO_OTYPER_ODR_7 GPIO_ODR_ODR_7
+#define GPIO_OTYPER_ODR_8 GPIO_ODR_ODR_8
+#define GPIO_OTYPER_ODR_9 GPIO_ODR_ODR_9
+#define GPIO_OTYPER_ODR_10 GPIO_ODR_ODR_10
+#define GPIO_OTYPER_ODR_11 GPIO_ODR_ODR_11
+#define GPIO_OTYPER_ODR_12 GPIO_ODR_ODR_12
+#define GPIO_OTYPER_ODR_13 GPIO_ODR_ODR_13
+#define GPIO_OTYPER_ODR_14 GPIO_ODR_ODR_14
+#define GPIO_OTYPER_ODR_15 GPIO_ODR_ODR_15
+
+/****************** Bits definition for GPIO_BSRR register ******************/
+#define GPIO_BSRR_BS_0 0x00000001U
+#define GPIO_BSRR_BS_1 0x00000002U
+#define GPIO_BSRR_BS_2 0x00000004U
+#define GPIO_BSRR_BS_3 0x00000008U
+#define GPIO_BSRR_BS_4 0x00000010U
+#define GPIO_BSRR_BS_5 0x00000020U
+#define GPIO_BSRR_BS_6 0x00000040U
+#define GPIO_BSRR_BS_7 0x00000080U
+#define GPIO_BSRR_BS_8 0x00000100U
+#define GPIO_BSRR_BS_9 0x00000200U
+#define GPIO_BSRR_BS_10 0x00000400U
+#define GPIO_BSRR_BS_11 0x00000800U
+#define GPIO_BSRR_BS_12 0x00001000U
+#define GPIO_BSRR_BS_13 0x00002000U
+#define GPIO_BSRR_BS_14 0x00004000U
+#define GPIO_BSRR_BS_15 0x00008000U
+#define GPIO_BSRR_BR_0 0x00010000U
+#define GPIO_BSRR_BR_1 0x00020000U
+#define GPIO_BSRR_BR_2 0x00040000U
+#define GPIO_BSRR_BR_3 0x00080000U
+#define GPIO_BSRR_BR_4 0x00100000U
+#define GPIO_BSRR_BR_5 0x00200000U
+#define GPIO_BSRR_BR_6 0x00400000U
+#define GPIO_BSRR_BR_7 0x00800000U
+#define GPIO_BSRR_BR_8 0x01000000U
+#define GPIO_BSRR_BR_9 0x02000000U
+#define GPIO_BSRR_BR_10 0x04000000U
+#define GPIO_BSRR_BR_11 0x08000000U
+#define GPIO_BSRR_BR_12 0x10000000U
+#define GPIO_BSRR_BR_13 0x20000000U
+#define GPIO_BSRR_BR_14 0x40000000U
+#define GPIO_BSRR_BR_15 0x80000000U
+
+/****************** Bit definition for GPIO_LCKR register *********************/
+#define GPIO_LCKR_LCK0 0x00000001U
+#define GPIO_LCKR_LCK1 0x00000002U
+#define GPIO_LCKR_LCK2 0x00000004U
+#define GPIO_LCKR_LCK3 0x00000008U
+#define GPIO_LCKR_LCK4 0x00000010U
+#define GPIO_LCKR_LCK5 0x00000020U
+#define GPIO_LCKR_LCK6 0x00000040U
+#define GPIO_LCKR_LCK7 0x00000080U
+#define GPIO_LCKR_LCK8 0x00000100U
+#define GPIO_LCKR_LCK9 0x00000200U
+#define GPIO_LCKR_LCK10 0x00000400U
+#define GPIO_LCKR_LCK11 0x00000800U
+#define GPIO_LCKR_LCK12 0x00001000U
+#define GPIO_LCKR_LCK13 0x00002000U
+#define GPIO_LCKR_LCK14 0x00004000U
+#define GPIO_LCKR_LCK15 0x00008000U
+#define GPIO_LCKR_LCKK 0x00010000U
+
+/******************************************************************************/
+/* */
+/* Inter-integrated Circuit Interface */
+/* */
+/******************************************************************************/
+/******************* Bit definition for I2C_CR1 register ********************/
+#define I2C_CR1_PE 0x00000001U /*!<Peripheral Enable */
+#define I2C_CR1_SMBUS 0x00000002U /*!<SMBus Mode */
+#define I2C_CR1_SMBTYPE 0x00000008U /*!<SMBus Type */
+#define I2C_CR1_ENARP 0x00000010U /*!<ARP Enable */
+#define I2C_CR1_ENPEC 0x00000020U /*!<PEC Enable */
+#define I2C_CR1_ENGC 0x00000040U /*!<General Call Enable */
+#define I2C_CR1_NOSTRETCH 0x00000080U /*!<Clock Stretching Disable (Slave mode) */
+#define I2C_CR1_START 0x00000100U /*!<Start Generation */
+#define I2C_CR1_STOP 0x00000200U /*!<Stop Generation */
+#define I2C_CR1_ACK 0x00000400U /*!<Acknowledge Enable */
+#define I2C_CR1_POS 0x00000800U /*!<Acknowledge/PEC Position (for data reception) */
+#define I2C_CR1_PEC 0x00001000U /*!<Packet Error Checking */
+#define I2C_CR1_ALERT 0x00002000U /*!<SMBus Alert */
+#define I2C_CR1_SWRST 0x00008000U /*!<Software Reset */
+
+/******************* Bit definition for I2C_CR2 register ********************/
+#define I2C_CR2_FREQ 0x0000003FU /*!<FREQ[5:0] bits (Peripheral Clock Frequency) */
+#define I2C_CR2_FREQ_0 0x00000001U /*!<Bit 0 */
+#define I2C_CR2_FREQ_1 0x00000002U /*!<Bit 1 */
+#define I2C_CR2_FREQ_2 0x00000004U /*!<Bit 2 */
+#define I2C_CR2_FREQ_3 0x00000008U /*!<Bit 3 */
+#define I2C_CR2_FREQ_4 0x00000010U /*!<Bit 4 */
+#define I2C_CR2_FREQ_5 0x00000020U /*!<Bit 5 */
+
+#define I2C_CR2_ITERREN 0x00000100U /*!<Error Interrupt Enable */
+#define I2C_CR2_ITEVTEN 0x00000200U /*!<Event Interrupt Enable */
+#define I2C_CR2_ITBUFEN 0x00000400U /*!<Buffer Interrupt Enable */
+#define I2C_CR2_DMAEN 0x00000800U /*!<DMA Requests Enable */
+#define I2C_CR2_LAST 0x00001000U /*!<DMA Last Transfer */
+
+/******************* Bit definition for I2C_OAR1 register *******************/
+#define I2C_OAR1_ADD1_7 0x000000FEU /*!<Interface Address */
+#define I2C_OAR1_ADD8_9 0x00000300U /*!<Interface Address */
+
+#define I2C_OAR1_ADD0 0x00000001U /*!<Bit 0 */
+#define I2C_OAR1_ADD1 0x00000002U /*!<Bit 1 */
+#define I2C_OAR1_ADD2 0x00000004U /*!<Bit 2 */
+#define I2C_OAR1_ADD3 0x00000008U /*!<Bit 3 */
+#define I2C_OAR1_ADD4 0x00000010U /*!<Bit 4 */
+#define I2C_OAR1_ADD5 0x00000020U /*!<Bit 5 */
+#define I2C_OAR1_ADD6 0x00000040U /*!<Bit 6 */
+#define I2C_OAR1_ADD7 0x00000080U /*!<Bit 7 */
+#define I2C_OAR1_ADD8 0x00000100U /*!<Bit 8 */
+#define I2C_OAR1_ADD9 0x00000200U /*!<Bit 9 */
+
+#define I2C_OAR1_ADDMODE 0x00008000U /*!<Addressing Mode (Slave mode) */
+
+/******************* Bit definition for I2C_OAR2 register *******************/
+#define I2C_OAR2_ENDUAL 0x00000001U /*!<Dual addressing mode enable */
+#define I2C_OAR2_ADD2 0x000000FEU /*!<Interface address */
+
+/******************** Bit definition for I2C_DR register ********************/
+#define I2C_DR_DR 0x000000FFU /*!<8-bit Data Register */
+
+/******************* Bit definition for I2C_SR1 register ********************/
+#define I2C_SR1_SB 0x00000001U /*!<Start Bit (Master mode) */
+#define I2C_SR1_ADDR 0x00000002U /*!<Address sent (master mode)/matched (slave mode) */
+#define I2C_SR1_BTF 0x00000004U /*!<Byte Transfer Finished */
+#define I2C_SR1_ADD10 0x00000008U /*!<10-bit header sent (Master mode) */
+#define I2C_SR1_STOPF 0x00000010U /*!<Stop detection (Slave mode) */
+#define I2C_SR1_RXNE 0x00000040U /*!<Data Register not Empty (receivers) */
+#define I2C_SR1_TXE 0x00000080U /*!<Data Register Empty (transmitters) */
+#define I2C_SR1_BERR 0x00000100U /*!<Bus Error */
+#define I2C_SR1_ARLO 0x00000200U /*!<Arbitration Lost (master mode) */
+#define I2C_SR1_AF 0x00000400U /*!<Acknowledge Failure */
+#define I2C_SR1_OVR 0x00000800U /*!<Overrun/Underrun */
+#define I2C_SR1_PECERR 0x00001000U /*!<PEC Error in reception */
+#define I2C_SR1_TIMEOUT 0x00004000U /*!<Timeout or Tlow Error */
+#define I2C_SR1_SMBALERT 0x00008000U /*!<SMBus Alert */
+
+/******************* Bit definition for I2C_SR2 register ********************/
+#define I2C_SR2_MSL 0x00000001U /*!<Master/Slave */
+#define I2C_SR2_BUSY 0x00000002U /*!<Bus Busy */
+#define I2C_SR2_TRA 0x00000004U /*!<Transmitter/Receiver */
+#define I2C_SR2_GENCALL 0x00000010U /*!<General Call Address (Slave mode) */
+#define I2C_SR2_SMBDEFAULT 0x00000020U /*!<SMBus Device Default Address (Slave mode) */
+#define I2C_SR2_SMBHOST 0x00000040U /*!<SMBus Host Header (Slave mode) */
+#define I2C_SR2_DUALF 0x00000080U /*!<Dual Flag (Slave mode) */
+#define I2C_SR2_PEC 0x0000FF00U /*!<Packet Error Checking Register */
+
+/******************* Bit definition for I2C_CCR register ********************/
+#define I2C_CCR_CCR 0x00000FFFU /*!<Clock Control Register in Fast/Standard mode (Master mode) */
+#define I2C_CCR_DUTY 0x00004000U /*!<Fast Mode Duty Cycle */
+#define I2C_CCR_FS 0x00008000U /*!<I2C Master Mode Selection */
+
+/****************** Bit definition for I2C_TRISE register *******************/
+#define I2C_TRISE_TRISE 0x0000003FU /*!<Maximum Rise Time in Fast/Standard mode (Master mode) */
+
+/****************** Bit definition for I2C_FLTR register *******************/
+#define I2C_FLTR_DNF 0x0000000FU /*!<Digital Noise Filter */
+#define I2C_FLTR_ANOFF 0x00000010U /*!<Analog Noise Filter OFF */
+
+/******************************************************************************/
+/* */
+/* Independent WATCHDOG */
+/* */
+/******************************************************************************/
+/******************* Bit definition for IWDG_KR register ********************/
+#define IWDG_KR_KEY 0xFFFFU /*!<Key value (write only, read 0000h) */
+
+/******************* Bit definition for IWDG_PR register ********************/
+#define IWDG_PR_PR 0x07U /*!<PR[2:0] (Prescaler divider) */
+#define IWDG_PR_PR_0 0x01U /*!<Bit 0 */
+#define IWDG_PR_PR_1 0x02U /*!<Bit 1 */
+#define IWDG_PR_PR_2 0x04U /*!<Bit 2 */
+
+/******************* Bit definition for IWDG_RLR register *******************/
+#define IWDG_RLR_RL 0x0FFFU /*!<Watchdog counter reload value */
+
+/******************* Bit definition for IWDG_SR register ********************/
+#define IWDG_SR_PVU 0x01U /*!<Watchdog prescaler value update */
+#define IWDG_SR_RVU 0x02U /*!<Watchdog counter reload value update */
+
+
+/******************************************************************************/
+/* */
+/* Power Control */
+/* */
+/******************************************************************************/
+/******************** Bit definition for PWR_CR register ********************/
+#define PWR_CR_LPDS 0x00000001U /*!< Low-Power Deepsleep */
+#define PWR_CR_PDDS 0x00000002U /*!< Power Down Deepsleep */
+#define PWR_CR_CWUF 0x00000004U /*!< Clear Wakeup Flag */
+#define PWR_CR_CSBF 0x00000008U /*!< Clear Standby Flag */
+#define PWR_CR_PVDE 0x00000010U /*!< Power Voltage Detector Enable */
+
+#define PWR_CR_PLS 0x000000E0U /*!< PLS[2:0] bits (PVD Level Selection) */
+#define PWR_CR_PLS_0 0x00000020U /*!< Bit 0 */
+#define PWR_CR_PLS_1 0x00000040U /*!< Bit 1 */
+#define PWR_CR_PLS_2 0x00000080U /*!< Bit 2 */
+
+/*!< PVD level configuration */
+#define PWR_CR_PLS_LEV0 0x00000000U /*!< PVD level 0 */
+#define PWR_CR_PLS_LEV1 0x00000020U /*!< PVD level 1 */
+#define PWR_CR_PLS_LEV2 0x00000040U /*!< PVD level 2 */
+#define PWR_CR_PLS_LEV3 0x00000060U /*!< PVD level 3 */
+#define PWR_CR_PLS_LEV4 0x00000080U /*!< PVD level 4 */
+#define PWR_CR_PLS_LEV5 0x000000A0U /*!< PVD level 5 */
+#define PWR_CR_PLS_LEV6 0x000000C0U /*!< PVD level 6 */
+#define PWR_CR_PLS_LEV7 0x000000E0U /*!< PVD level 7 */
+
+#define PWR_CR_DBP 0x00000100U /*!< Disable Backup Domain write protection */
+#define PWR_CR_FPDS 0x00000200U /*!< Flash power down in Stop mode */
+#define PWR_CR_VOS 0x00004000U /*!< VOS bit (Regulator voltage scaling output selection) */
+
+/* Legacy define */
+#define PWR_CR_PMODE PWR_CR_VOS
+
+/******************* Bit definition for PWR_CSR register ********************/
+#define PWR_CSR_WUF 0x00000001U /*!< Wakeup Flag */
+#define PWR_CSR_SBF 0x00000002U /*!< Standby Flag */
+#define PWR_CSR_PVDO 0x00000004U /*!< PVD Output */
+#define PWR_CSR_BRR 0x00000008U /*!< Backup regulator ready */
+#define PWR_CSR_EWUP 0x00000100U /*!< Enable WKUP pin */
+#define PWR_CSR_BRE 0x00000200U /*!< Backup regulator enable */
+#define PWR_CSR_VOSRDY 0x00004000U /*!< Regulator voltage scaling output selection ready */
+
+/* Legacy define */
+#define PWR_CSR_REGRDY PWR_CSR_VOSRDY
+
+/******************************************************************************/
+/* */
+/* Reset and Clock Control */
+/* */
+/******************************************************************************/
+/******************** Bit definition for RCC_CR register ********************/
+#define RCC_CR_HSION 0x00000001U
+#define RCC_CR_HSIRDY 0x00000002U
+
+#define RCC_CR_HSITRIM 0x000000F8U
+#define RCC_CR_HSITRIM_0 0x00000008U/*!<Bit 0 */
+#define RCC_CR_HSITRIM_1 0x00000010U/*!<Bit 1 */
+#define RCC_CR_HSITRIM_2 0x00000020U/*!<Bit 2 */
+#define RCC_CR_HSITRIM_3 0x00000040U/*!<Bit 3 */
+#define RCC_CR_HSITRIM_4 0x00000080U/*!<Bit 4 */
+
+#define RCC_CR_HSICAL 0x0000FF00U
+#define RCC_CR_HSICAL_0 0x00000100U/*!<Bit 0 */
+#define RCC_CR_HSICAL_1 0x00000200U/*!<Bit 1 */
+#define RCC_CR_HSICAL_2 0x00000400U/*!<Bit 2 */
+#define RCC_CR_HSICAL_3 0x00000800U/*!<Bit 3 */
+#define RCC_CR_HSICAL_4 0x00001000U/*!<Bit 4 */
+#define RCC_CR_HSICAL_5 0x00002000U/*!<Bit 5 */
+#define RCC_CR_HSICAL_6 0x00004000U/*!<Bit 6 */
+#define RCC_CR_HSICAL_7 0x00008000U/*!<Bit 7 */
+
+#define RCC_CR_HSEON 0x00010000U
+#define RCC_CR_HSERDY 0x00020000U
+#define RCC_CR_HSEBYP 0x00040000U
+#define RCC_CR_CSSON 0x00080000U
+#define RCC_CR_PLLON 0x01000000U
+#define RCC_CR_PLLRDY 0x02000000U
+#define RCC_CR_PLLI2SON 0x04000000U
+#define RCC_CR_PLLI2SRDY 0x08000000U
+
+/******************** Bit definition for RCC_PLLCFGR register ***************/
+#define RCC_PLLCFGR_PLLM 0x0000003FU
+#define RCC_PLLCFGR_PLLM_0 0x00000001U
+#define RCC_PLLCFGR_PLLM_1 0x00000002U
+#define RCC_PLLCFGR_PLLM_2 0x00000004U
+#define RCC_PLLCFGR_PLLM_3 0x00000008U
+#define RCC_PLLCFGR_PLLM_4 0x00000010U
+#define RCC_PLLCFGR_PLLM_5 0x00000020U
+
+#define RCC_PLLCFGR_PLLN 0x00007FC0U
+#define RCC_PLLCFGR_PLLN_0 0x00000040U
+#define RCC_PLLCFGR_PLLN_1 0x00000080U
+#define RCC_PLLCFGR_PLLN_2 0x00000100U
+#define RCC_PLLCFGR_PLLN_3 0x00000200U
+#define RCC_PLLCFGR_PLLN_4 0x00000400U
+#define RCC_PLLCFGR_PLLN_5 0x00000800U
+#define RCC_PLLCFGR_PLLN_6 0x00001000U
+#define RCC_PLLCFGR_PLLN_7 0x00002000U
+#define RCC_PLLCFGR_PLLN_8 0x00004000U
+
+#define RCC_PLLCFGR_PLLP 0x00030000U
+#define RCC_PLLCFGR_PLLP_0 0x00010000U
+#define RCC_PLLCFGR_PLLP_1 0x00020000U
+
+#define RCC_PLLCFGR_PLLSRC 0x00400000U
+#define RCC_PLLCFGR_PLLSRC_HSE 0x00400000U
+#define RCC_PLLCFGR_PLLSRC_HSI 0x00000000U
+
+#define RCC_PLLCFGR_PLLQ 0x0F000000U
+#define RCC_PLLCFGR_PLLQ_0 0x01000000U
+#define RCC_PLLCFGR_PLLQ_1 0x02000000U
+#define RCC_PLLCFGR_PLLQ_2 0x04000000U
+#define RCC_PLLCFGR_PLLQ_3 0x08000000U
+
+/******************** Bit definition for RCC_CFGR register ******************/
+/*!< SW configuration */
+#define RCC_CFGR_SW 0x00000003U /*!< SW[1:0] bits (System clock Switch) */
+#define RCC_CFGR_SW_0 0x00000001U /*!< Bit 0 */
+#define RCC_CFGR_SW_1 0x00000002U /*!< Bit 1 */
+
+#define RCC_CFGR_SW_HSI 0x00000000U /*!< HSI selected as system clock */
+#define RCC_CFGR_SW_HSE 0x00000001U /*!< HSE selected as system clock */
+#define RCC_CFGR_SW_PLL 0x00000002U /*!< PLL selected as system clock */
+
+/*!< SWS configuration */
+#define RCC_CFGR_SWS 0x0000000CU /*!< SWS[1:0] bits (System Clock Switch Status) */
+#define RCC_CFGR_SWS_0 0x00000004U /*!< Bit 0 */
+#define RCC_CFGR_SWS_1 0x00000008U /*!< Bit 1 */
+
+#define RCC_CFGR_SWS_HSI 0x00000000U /*!< HSI oscillator used as system clock */
+#define RCC_CFGR_SWS_HSE 0x00000004U /*!< HSE oscillator used as system clock */
+#define RCC_CFGR_SWS_PLL 0x00000008U /*!< PLL used as system clock */
+
+/*!< HPRE configuration */
+#define RCC_CFGR_HPRE 0x000000F0U /*!< HPRE[3:0] bits (AHB prescaler) */
+#define RCC_CFGR_HPRE_0 0x00000010U /*!< Bit 0 */
+#define RCC_CFGR_HPRE_1 0x00000020U /*!< Bit 1 */
+#define RCC_CFGR_HPRE_2 0x00000040U /*!< Bit 2 */
+#define RCC_CFGR_HPRE_3 0x00000080U /*!< Bit 3 */
+
+#define RCC_CFGR_HPRE_DIV1 0x00000000U /*!< SYSCLK not divided */
+#define RCC_CFGR_HPRE_DIV2 0x00000080U /*!< SYSCLK divided by 2 */
+#define RCC_CFGR_HPRE_DIV4 0x00000090U /*!< SYSCLK divided by 4 */
+#define RCC_CFGR_HPRE_DIV8 0x000000A0U /*!< SYSCLK divided by 8 */
+#define RCC_CFGR_HPRE_DIV16 0x000000B0U /*!< SYSCLK divided by 16 */
+#define RCC_CFGR_HPRE_DIV64 0x000000C0U /*!< SYSCLK divided by 64 */
+#define RCC_CFGR_HPRE_DIV128 0x000000D0U /*!< SYSCLK divided by 128 */
+#define RCC_CFGR_HPRE_DIV256 0x000000E0U /*!< SYSCLK divided by 256 */
+#define RCC_CFGR_HPRE_DIV512 0x000000F0U /*!< SYSCLK divided by 512 */
+
+/*!< PPRE1 configuration */
+#define RCC_CFGR_PPRE1 0x00001C00U /*!< PRE1[2:0] bits (APB1 prescaler) */
+#define RCC_CFGR_PPRE1_0 0x00000400U /*!< Bit 0 */
+#define RCC_CFGR_PPRE1_1 0x00000800U /*!< Bit 1 */
+#define RCC_CFGR_PPRE1_2 0x00001000U /*!< Bit 2 */
+
+#define RCC_CFGR_PPRE1_DIV1 0x00000000U /*!< HCLK not divided */
+#define RCC_CFGR_PPRE1_DIV2 0x00001000U /*!< HCLK divided by 2 */
+#define RCC_CFGR_PPRE1_DIV4 0x00001400U /*!< HCLK divided by 4 */
+#define RCC_CFGR_PPRE1_DIV8 0x00001800U /*!< HCLK divided by 8 */
+#define RCC_CFGR_PPRE1_DIV16 0x00001C00U /*!< HCLK divided by 16 */
+
+/*!< PPRE2 configuration */
+#define RCC_CFGR_PPRE2 0x0000E000U /*!< PRE2[2:0] bits (APB2 prescaler) */
+#define RCC_CFGR_PPRE2_0 0x00002000U /*!< Bit 0 */
+#define RCC_CFGR_PPRE2_1 0x00004000U /*!< Bit 1 */
+#define RCC_CFGR_PPRE2_2 0x00008000U /*!< Bit 2 */
+
+#define RCC_CFGR_PPRE2_DIV1 0x00000000U /*!< HCLK not divided */
+#define RCC_CFGR_PPRE2_DIV2 0x00008000U /*!< HCLK divided by 2 */
+#define RCC_CFGR_PPRE2_DIV4 0x0000A000U /*!< HCLK divided by 4 */
+#define RCC_CFGR_PPRE2_DIV8 0x0000C000U /*!< HCLK divided by 8 */
+#define RCC_CFGR_PPRE2_DIV16 0x0000E000U /*!< HCLK divided by 16 */
+
+/*!< RTCPRE configuration */
+#define RCC_CFGR_RTCPRE 0x001F0000U
+#define RCC_CFGR_RTCPRE_0 0x00010000U
+#define RCC_CFGR_RTCPRE_1 0x00020000U
+#define RCC_CFGR_RTCPRE_2 0x00040000U
+#define RCC_CFGR_RTCPRE_3 0x00080000U
+#define RCC_CFGR_RTCPRE_4 0x00100000U
+
+/*!< MCO1 configuration */
+#define RCC_CFGR_MCO1 0x00600000U
+#define RCC_CFGR_MCO1_0 0x00200000U
+#define RCC_CFGR_MCO1_1 0x00400000U
+
+#define RCC_CFGR_I2SSRC 0x00800000U
+
+#define RCC_CFGR_MCO1PRE 0x07000000U
+#define RCC_CFGR_MCO1PRE_0 0x01000000U
+#define RCC_CFGR_MCO1PRE_1 0x02000000U
+#define RCC_CFGR_MCO1PRE_2 0x04000000U
+
+#define RCC_CFGR_MCO2PRE 0x38000000U
+#define RCC_CFGR_MCO2PRE_0 0x08000000U
+#define RCC_CFGR_MCO2PRE_1 0x10000000U
+#define RCC_CFGR_MCO2PRE_2 0x20000000U
+
+#define RCC_CFGR_MCO2 0xC0000000U
+#define RCC_CFGR_MCO2_0 0x40000000U
+#define RCC_CFGR_MCO2_1 0x80000000U
+
+/******************** Bit definition for RCC_CIR register *******************/
+#define RCC_CIR_LSIRDYF 0x00000001U
+#define RCC_CIR_LSERDYF 0x00000002U
+#define RCC_CIR_HSIRDYF 0x00000004U
+#define RCC_CIR_HSERDYF 0x00000008U
+#define RCC_CIR_PLLRDYF 0x00000010U
+#define RCC_CIR_PLLI2SRDYF 0x00000020U
+
+#define RCC_CIR_CSSF 0x00000080U
+#define RCC_CIR_LSIRDYIE 0x00000100U
+#define RCC_CIR_LSERDYIE 0x00000200U
+#define RCC_CIR_HSIRDYIE 0x00000400U
+#define RCC_CIR_HSERDYIE 0x00000800U
+#define RCC_CIR_PLLRDYIE 0x00001000U
+#define RCC_CIR_PLLI2SRDYIE 0x00002000U
+
+#define RCC_CIR_LSIRDYC 0x00010000U
+#define RCC_CIR_LSERDYC 0x00020000U
+#define RCC_CIR_HSIRDYC 0x00040000U
+#define RCC_CIR_HSERDYC 0x00080000U
+#define RCC_CIR_PLLRDYC 0x00100000U
+#define RCC_CIR_PLLI2SRDYC 0x00200000U
+
+#define RCC_CIR_CSSC 0x00800000U
+
+/******************** Bit definition for RCC_AHB1RSTR register **************/
+#define RCC_AHB1RSTR_GPIOARST 0x00000001U
+#define RCC_AHB1RSTR_GPIOBRST 0x00000002U
+#define RCC_AHB1RSTR_GPIOCRST 0x00000004U
+#define RCC_AHB1RSTR_GPIODRST 0x00000008U
+#define RCC_AHB1RSTR_GPIOERST 0x00000010U
+#define RCC_AHB1RSTR_GPIOFRST 0x00000020U
+#define RCC_AHB1RSTR_GPIOGRST 0x00000040U
+#define RCC_AHB1RSTR_GPIOHRST 0x00000080U
+#define RCC_AHB1RSTR_GPIOIRST 0x00000100U
+#define RCC_AHB1RSTR_CRCRST 0x00001000U
+#define RCC_AHB1RSTR_DMA1RST 0x00200000U
+#define RCC_AHB1RSTR_DMA2RST 0x00400000U
+#define RCC_AHB1RSTR_ETHMACRST 0x02000000U
+#define RCC_AHB1RSTR_OTGHRST 0x20000000U
+
+/******************** Bit definition for RCC_AHB2RSTR register **************/
+#define RCC_AHB2RSTR_DCMIRST 0x00000001U
+#define RCC_AHB2RSTR_RNGRST 0x00000040U
+#define RCC_AHB2RSTR_OTGFSRST 0x00000080U
+
+/******************** Bit definition for RCC_AHB3RSTR register **************/
+
+#define RCC_AHB3RSTR_FSMCRST 0x00000001U
+
+/******************** Bit definition for RCC_APB1RSTR register **************/
+#define RCC_APB1RSTR_TIM2RST 0x00000001U
+#define RCC_APB1RSTR_TIM3RST 0x00000002U
+#define RCC_APB1RSTR_TIM4RST 0x00000004U
+#define RCC_APB1RSTR_TIM5RST 0x00000008U
+#define RCC_APB1RSTR_TIM6RST 0x00000010U
+#define RCC_APB1RSTR_TIM7RST 0x00000020U
+#define RCC_APB1RSTR_TIM12RST 0x00000040U
+#define RCC_APB1RSTR_TIM13RST 0x00000080U
+#define RCC_APB1RSTR_TIM14RST 0x00000100U
+#define RCC_APB1RSTR_WWDGRST 0x00000800U
+#define RCC_APB1RSTR_SPI2RST 0x00004000U
+#define RCC_APB1RSTR_SPI3RST 0x00008000U
+#define RCC_APB1RSTR_USART2RST 0x00020000U
+#define RCC_APB1RSTR_USART3RST 0x00040000U
+#define RCC_APB1RSTR_UART4RST 0x00080000U
+#define RCC_APB1RSTR_UART5RST 0x00100000U
+#define RCC_APB1RSTR_I2C1RST 0x00200000U
+#define RCC_APB1RSTR_I2C2RST 0x00400000U
+#define RCC_APB1RSTR_I2C3RST 0x00800000U
+#define RCC_APB1RSTR_CAN1RST 0x02000000U
+#define RCC_APB1RSTR_CAN2RST 0x04000000U
+#define RCC_APB1RSTR_PWRRST 0x10000000U
+#define RCC_APB1RSTR_DACRST 0x20000000U
+
+/******************** Bit definition for RCC_APB2RSTR register **************/
+#define RCC_APB2RSTR_TIM1RST 0x00000001U
+#define RCC_APB2RSTR_TIM8RST 0x00000002U
+#define RCC_APB2RSTR_USART1RST 0x00000010U
+#define RCC_APB2RSTR_USART6RST 0x00000020U
+#define RCC_APB2RSTR_ADCRST 0x00000100U
+#define RCC_APB2RSTR_SDIORST 0x00000800U
+#define RCC_APB2RSTR_SPI1RST 0x00001000U
+#define RCC_APB2RSTR_SYSCFGRST 0x00004000U
+#define RCC_APB2RSTR_TIM9RST 0x00010000U
+#define RCC_APB2RSTR_TIM10RST 0x00020000U
+#define RCC_APB2RSTR_TIM11RST 0x00040000U
+
+/* Old SPI1RST bit definition, maintained for legacy purpose */
+#define RCC_APB2RSTR_SPI1 RCC_APB2RSTR_SPI1RST
+
+/******************** Bit definition for RCC_AHB1ENR register ***************/
+#define RCC_AHB1ENR_GPIOAEN 0x00000001U
+#define RCC_AHB1ENR_GPIOBEN 0x00000002U
+#define RCC_AHB1ENR_GPIOCEN 0x00000004U
+#define RCC_AHB1ENR_GPIODEN 0x00000008U
+#define RCC_AHB1ENR_GPIOEEN 0x00000010U
+#define RCC_AHB1ENR_GPIOFEN 0x00000020U
+#define RCC_AHB1ENR_GPIOGEN 0x00000040U
+#define RCC_AHB1ENR_GPIOHEN 0x00000080U
+#define RCC_AHB1ENR_GPIOIEN 0x00000100U
+#define RCC_AHB1ENR_CRCEN 0x00001000U
+#define RCC_AHB1ENR_BKPSRAMEN 0x00040000U
+#define RCC_AHB1ENR_CCMDATARAMEN 0x00100000U
+#define RCC_AHB1ENR_DMA1EN 0x00200000U
+#define RCC_AHB1ENR_DMA2EN 0x00400000U
+
+#define RCC_AHB1ENR_ETHMACEN 0x02000000U
+#define RCC_AHB1ENR_ETHMACTXEN 0x04000000U
+#define RCC_AHB1ENR_ETHMACRXEN 0x08000000U
+#define RCC_AHB1ENR_ETHMACPTPEN 0x10000000U
+#define RCC_AHB1ENR_OTGHSEN 0x20000000U
+#define RCC_AHB1ENR_OTGHSULPIEN 0x40000000U
+
+/******************** Bit definition for RCC_AHB2ENR register ***************/
+#define RCC_AHB2ENR_DCMIEN 0x00000001U
+#define RCC_AHB2ENR_RNGEN 0x00000040U
+#define RCC_AHB2ENR_OTGFSEN 0x00000080U
+
+/******************** Bit definition for RCC_AHB3ENR register ***************/
+
+#define RCC_AHB3ENR_FSMCEN 0x00000001U
+
+/******************** Bit definition for RCC_APB1ENR register ***************/
+#define RCC_APB1ENR_TIM2EN 0x00000001U
+#define RCC_APB1ENR_TIM3EN 0x00000002U
+#define RCC_APB1ENR_TIM4EN 0x00000004U
+#define RCC_APB1ENR_TIM5EN 0x00000008U
+#define RCC_APB1ENR_TIM6EN 0x00000010U
+#define RCC_APB1ENR_TIM7EN 0x00000020U
+#define RCC_APB1ENR_TIM12EN 0x00000040U
+#define RCC_APB1ENR_TIM13EN 0x00000080U
+#define RCC_APB1ENR_TIM14EN 0x00000100U
+#define RCC_APB1ENR_WWDGEN 0x00000800U
+#define RCC_APB1ENR_SPI2EN 0x00004000U
+#define RCC_APB1ENR_SPI3EN 0x00008000U
+#define RCC_APB1ENR_USART2EN 0x00020000U
+#define RCC_APB1ENR_USART3EN 0x00040000U
+#define RCC_APB1ENR_UART4EN 0x00080000U
+#define RCC_APB1ENR_UART5EN 0x00100000U
+#define RCC_APB1ENR_I2C1EN 0x00200000U
+#define RCC_APB1ENR_I2C2EN 0x00400000U
+#define RCC_APB1ENR_I2C3EN 0x00800000U
+#define RCC_APB1ENR_CAN1EN 0x02000000U
+#define RCC_APB1ENR_CAN2EN 0x04000000U
+#define RCC_APB1ENR_PWREN 0x10000000U
+#define RCC_APB1ENR_DACEN 0x20000000U
+
+/******************** Bit definition for RCC_APB2ENR register ***************/
+#define RCC_APB2ENR_TIM1EN 0x00000001U
+#define RCC_APB2ENR_TIM8EN 0x00000002U
+#define RCC_APB2ENR_USART1EN 0x00000010U
+#define RCC_APB2ENR_USART6EN 0x00000020U
+#define RCC_APB2ENR_ADC1EN 0x00000100U
+#define RCC_APB2ENR_ADC2EN 0x00000200U
+#define RCC_APB2ENR_ADC3EN 0x00000400U
+#define RCC_APB2ENR_SDIOEN 0x00000800U
+#define RCC_APB2ENR_SPI1EN 0x00001000U
+#define RCC_APB2ENR_SYSCFGEN 0x00004000U
+#define RCC_APB2ENR_TIM9EN 0x00010000U
+#define RCC_APB2ENR_TIM10EN 0x00020000U
+#define RCC_APB2ENR_TIM11EN 0x00040000U
+#define RCC_APB2ENR_SPI5EN 0x00100000U
+#define RCC_APB2ENR_SPI6EN 0x00200000U
+
+/******************** Bit definition for RCC_AHB1LPENR register *************/
+#define RCC_AHB1LPENR_GPIOALPEN 0x00000001U
+#define RCC_AHB1LPENR_GPIOBLPEN 0x00000002U
+#define RCC_AHB1LPENR_GPIOCLPEN 0x00000004U
+#define RCC_AHB1LPENR_GPIODLPEN 0x00000008U
+#define RCC_AHB1LPENR_GPIOELPEN 0x00000010U
+#define RCC_AHB1LPENR_GPIOFLPEN 0x00000020U
+#define RCC_AHB1LPENR_GPIOGLPEN 0x00000040U
+#define RCC_AHB1LPENR_GPIOHLPEN 0x00000080U
+#define RCC_AHB1LPENR_GPIOILPEN 0x00000100U
+#define RCC_AHB1LPENR_CRCLPEN 0x00001000U
+#define RCC_AHB1LPENR_FLITFLPEN 0x00008000U
+#define RCC_AHB1LPENR_SRAM1LPEN 0x00010000U
+#define RCC_AHB1LPENR_SRAM2LPEN 0x00020000U
+#define RCC_AHB1LPENR_BKPSRAMLPEN 0x00040000U
+#define RCC_AHB1LPENR_DMA1LPEN 0x00200000U
+#define RCC_AHB1LPENR_DMA2LPEN 0x00400000U
+#define RCC_AHB1LPENR_ETHMACLPEN 0x02000000U
+#define RCC_AHB1LPENR_ETHMACTXLPEN 0x04000000U
+#define RCC_AHB1LPENR_ETHMACRXLPEN 0x08000000U
+#define RCC_AHB1LPENR_ETHMACPTPLPEN 0x10000000U
+#define RCC_AHB1LPENR_OTGHSLPEN 0x20000000U
+#define RCC_AHB1LPENR_OTGHSULPILPEN 0x40000000U
+
+/******************** Bit definition for RCC_AHB2LPENR register *************/
+#define RCC_AHB2LPENR_DCMILPEN 0x00000001U
+#define RCC_AHB2LPENR_RNGLPEN 0x00000040U
+#define RCC_AHB2LPENR_OTGFSLPEN 0x00000080U
+
+/******************** Bit definition for RCC_AHB3LPENR register *************/
+
+#define RCC_AHB3LPENR_FSMCLPEN 0x00000001U
+
+/******************** Bit definition for RCC_APB1LPENR register *************/
+#define RCC_APB1LPENR_TIM2LPEN 0x00000001U
+#define RCC_APB1LPENR_TIM3LPEN 0x00000002U
+#define RCC_APB1LPENR_TIM4LPEN 0x00000004U
+#define RCC_APB1LPENR_TIM5LPEN 0x00000008U
+#define RCC_APB1LPENR_TIM6LPEN 0x00000010U
+#define RCC_APB1LPENR_TIM7LPEN 0x00000020U
+#define RCC_APB1LPENR_TIM12LPEN 0x00000040U
+#define RCC_APB1LPENR_TIM13LPEN 0x00000080U
+#define RCC_APB1LPENR_TIM14LPEN 0x00000100U
+#define RCC_APB1LPENR_WWDGLPEN 0x00000800U
+#define RCC_APB1LPENR_SPI2LPEN 0x00004000U
+#define RCC_APB1LPENR_SPI3LPEN 0x00008000U
+#define RCC_APB1LPENR_USART2LPEN 0x00020000U
+#define RCC_APB1LPENR_USART3LPEN 0x00040000U
+#define RCC_APB1LPENR_UART4LPEN 0x00080000U
+#define RCC_APB1LPENR_UART5LPEN 0x00100000U
+#define RCC_APB1LPENR_I2C1LPEN 0x00200000U
+#define RCC_APB1LPENR_I2C2LPEN 0x00400000U
+#define RCC_APB1LPENR_I2C3LPEN 0x00800000U
+#define RCC_APB1LPENR_CAN1LPEN 0x02000000U
+#define RCC_APB1LPENR_CAN2LPEN 0x04000000U
+#define RCC_APB1LPENR_PWRLPEN 0x10000000U
+#define RCC_APB1LPENR_DACLPEN 0x20000000U
+
+/******************** Bit definition for RCC_APB2LPENR register *************/
+#define RCC_APB2LPENR_TIM1LPEN 0x00000001U
+#define RCC_APB2LPENR_TIM8LPEN 0x00000002U
+#define RCC_APB2LPENR_USART1LPEN 0x00000010U
+#define RCC_APB2LPENR_USART6LPEN 0x00000020U
+#define RCC_APB2LPENR_ADC1LPEN 0x00000100U
+#define RCC_APB2LPENR_ADC2LPEN 0x00000200U
+#define RCC_APB2LPENR_ADC3LPEN 0x00000400U
+#define RCC_APB2LPENR_SDIOLPEN 0x00000800U
+#define RCC_APB2LPENR_SPI1LPEN 0x00001000U
+#define RCC_APB2LPENR_SYSCFGLPEN 0x00004000U
+#define RCC_APB2LPENR_TIM9LPEN 0x00010000U
+#define RCC_APB2LPENR_TIM10LPEN 0x00020000U
+#define RCC_APB2LPENR_TIM11LPEN 0x00040000U
+
+/******************** Bit definition for RCC_BDCR register ******************/
+#define RCC_BDCR_LSEON 0x00000001U
+#define RCC_BDCR_LSERDY 0x00000002U
+#define RCC_BDCR_LSEBYP 0x00000004U
+
+#define RCC_BDCR_RTCSEL 0x00000300U
+#define RCC_BDCR_RTCSEL_0 0x00000100U
+#define RCC_BDCR_RTCSEL_1 0x00000200U
+
+#define RCC_BDCR_RTCEN 0x00008000U
+#define RCC_BDCR_BDRST 0x00010000U
+
+/******************** Bit definition for RCC_CSR register *******************/
+#define RCC_CSR_LSION 0x00000001U
+#define RCC_CSR_LSIRDY 0x00000002U
+#define RCC_CSR_RMVF 0x01000000U
+#define RCC_CSR_BORRSTF 0x02000000U
+#define RCC_CSR_PADRSTF 0x04000000U
+#define RCC_CSR_PORRSTF 0x08000000U
+#define RCC_CSR_SFTRSTF 0x10000000U
+#define RCC_CSR_WDGRSTF 0x20000000U
+#define RCC_CSR_WWDGRSTF 0x40000000U
+#define RCC_CSR_LPWRRSTF 0x80000000U
+
+/******************** Bit definition for RCC_SSCGR register *****************/
+#define RCC_SSCGR_MODPER 0x00001FFFU
+#define RCC_SSCGR_INCSTEP 0x0FFFE000U
+#define RCC_SSCGR_SPREADSEL 0x40000000U
+#define RCC_SSCGR_SSCGEN 0x80000000U
+
+/******************** Bit definition for RCC_PLLI2SCFGR register ************/
+#define RCC_PLLI2SCFGR_PLLI2SN 0x00007FC0U
+#define RCC_PLLI2SCFGR_PLLI2SN_0 0x00000040U
+#define RCC_PLLI2SCFGR_PLLI2SN_1 0x00000080U
+#define RCC_PLLI2SCFGR_PLLI2SN_2 0x00000100U
+#define RCC_PLLI2SCFGR_PLLI2SN_3 0x00000200U
+#define RCC_PLLI2SCFGR_PLLI2SN_4 0x00000400U
+#define RCC_PLLI2SCFGR_PLLI2SN_5 0x00000800U
+#define RCC_PLLI2SCFGR_PLLI2SN_6 0x00001000U
+#define RCC_PLLI2SCFGR_PLLI2SN_7 0x00002000U
+#define RCC_PLLI2SCFGR_PLLI2SN_8 0x00004000U
+
+#define RCC_PLLI2SCFGR_PLLI2SR 0x70000000U
+#define RCC_PLLI2SCFGR_PLLI2SR_0 0x10000000U
+#define RCC_PLLI2SCFGR_PLLI2SR_1 0x20000000U
+#define RCC_PLLI2SCFGR_PLLI2SR_2 0x40000000U
+
+/******************************************************************************/
+/* */
+/* RNG */
+/* */
+/******************************************************************************/
+/******************** Bits definition for RNG_CR register *******************/
+#define RNG_CR_RNGEN 0x00000004U
+#define RNG_CR_IE 0x00000008U
+
+/******************** Bits definition for RNG_SR register *******************/
+#define RNG_SR_DRDY 0x00000001U
+#define RNG_SR_CECS 0x00000002U
+#define RNG_SR_SECS 0x00000004U
+#define RNG_SR_CEIS 0x00000020U
+#define RNG_SR_SEIS 0x00000040U
+
+/******************************************************************************/
+/* */
+/* Real-Time Clock (RTC) */
+/* */
+/******************************************************************************/
+/******************** Bits definition for RTC_TR register *******************/
+#define RTC_TR_PM 0x00400000U
+#define RTC_TR_HT 0x00300000U
+#define RTC_TR_HT_0 0x00100000U
+#define RTC_TR_HT_1 0x00200000U
+#define RTC_TR_HU 0x000F0000U
+#define RTC_TR_HU_0 0x00010000U
+#define RTC_TR_HU_1 0x00020000U
+#define RTC_TR_HU_2 0x00040000U
+#define RTC_TR_HU_3 0x00080000U
+#define RTC_TR_MNT 0x00007000U
+#define RTC_TR_MNT_0 0x00001000U
+#define RTC_TR_MNT_1 0x00002000U
+#define RTC_TR_MNT_2 0x00004000U
+#define RTC_TR_MNU 0x00000F00U
+#define RTC_TR_MNU_0 0x00000100U
+#define RTC_TR_MNU_1 0x00000200U
+#define RTC_TR_MNU_2 0x00000400U
+#define RTC_TR_MNU_3 0x00000800U
+#define RTC_TR_ST 0x00000070U
+#define RTC_TR_ST_0 0x00000010U
+#define RTC_TR_ST_1 0x00000020U
+#define RTC_TR_ST_2 0x00000040U
+#define RTC_TR_SU 0x0000000FU
+#define RTC_TR_SU_0 0x00000001U
+#define RTC_TR_SU_1 0x00000002U
+#define RTC_TR_SU_2 0x00000004U
+#define RTC_TR_SU_3 0x00000008U
+
+/******************** Bits definition for RTC_DR register *******************/
+#define RTC_DR_YT 0x00F00000U
+#define RTC_DR_YT_0 0x00100000U
+#define RTC_DR_YT_1 0x00200000U
+#define RTC_DR_YT_2 0x00400000U
+#define RTC_DR_YT_3 0x00800000U
+#define RTC_DR_YU 0x000F0000U
+#define RTC_DR_YU_0 0x00010000U
+#define RTC_DR_YU_1 0x00020000U
+#define RTC_DR_YU_2 0x00040000U
+#define RTC_DR_YU_3 0x00080000U
+#define RTC_DR_WDU 0x0000E000U
+#define RTC_DR_WDU_0 0x00002000U
+#define RTC_DR_WDU_1 0x00004000U
+#define RTC_DR_WDU_2 0x00008000U
+#define RTC_DR_MT 0x00001000U
+#define RTC_DR_MU 0x00000F00U
+#define RTC_DR_MU_0 0x00000100U
+#define RTC_DR_MU_1 0x00000200U
+#define RTC_DR_MU_2 0x00000400U
+#define RTC_DR_MU_3 0x00000800U
+#define RTC_DR_DT 0x00000030U
+#define RTC_DR_DT_0 0x00000010U
+#define RTC_DR_DT_1 0x00000020U
+#define RTC_DR_DU 0x0000000FU
+#define RTC_DR_DU_0 0x00000001U
+#define RTC_DR_DU_1 0x00000002U
+#define RTC_DR_DU_2 0x00000004U
+#define RTC_DR_DU_3 0x00000008U
+
+/******************** Bits definition for RTC_CR register *******************/
+#define RTC_CR_COE 0x00800000U
+#define RTC_CR_OSEL 0x00600000U
+#define RTC_CR_OSEL_0 0x00200000U
+#define RTC_CR_OSEL_1 0x00400000U
+#define RTC_CR_POL 0x00100000U
+#define RTC_CR_COSEL 0x00080000U
+#define RTC_CR_BCK 0x00040000U
+#define RTC_CR_SUB1H 0x00020000U
+#define RTC_CR_ADD1H 0x00010000U
+#define RTC_CR_TSIE 0x00008000U
+#define RTC_CR_WUTIE 0x00004000U
+#define RTC_CR_ALRBIE 0x00002000U
+#define RTC_CR_ALRAIE 0x00001000U
+#define RTC_CR_TSE 0x00000800U
+#define RTC_CR_WUTE 0x00000400U
+#define RTC_CR_ALRBE 0x00000200U
+#define RTC_CR_ALRAE 0x00000100U
+#define RTC_CR_DCE 0x00000080U
+#define RTC_CR_FMT 0x00000040U
+#define RTC_CR_BYPSHAD 0x00000020U
+#define RTC_CR_REFCKON 0x00000010U
+#define RTC_CR_TSEDGE 0x00000008U
+#define RTC_CR_WUCKSEL 0x00000007U
+#define RTC_CR_WUCKSEL_0 0x00000001U
+#define RTC_CR_WUCKSEL_1 0x00000002U
+#define RTC_CR_WUCKSEL_2 0x00000004U
+
+/******************** Bits definition for RTC_ISR register ******************/
+#define RTC_ISR_RECALPF 0x00010000U
+#define RTC_ISR_TAMP1F 0x00002000U
+#define RTC_ISR_TAMP2F 0x00004000U
+#define RTC_ISR_TSOVF 0x00001000U
+#define RTC_ISR_TSF 0x00000800U
+#define RTC_ISR_WUTF 0x00000400U
+#define RTC_ISR_ALRBF 0x00000200U
+#define RTC_ISR_ALRAF 0x00000100U
+#define RTC_ISR_INIT 0x00000080U
+#define RTC_ISR_INITF 0x00000040U
+#define RTC_ISR_RSF 0x00000020U
+#define RTC_ISR_INITS 0x00000010U
+#define RTC_ISR_SHPF 0x00000008U
+#define RTC_ISR_WUTWF 0x00000004U
+#define RTC_ISR_ALRBWF 0x00000002U
+#define RTC_ISR_ALRAWF 0x00000001U
+
+/******************** Bits definition for RTC_PRER register *****************/
+#define RTC_PRER_PREDIV_A 0x007F0000U
+#define RTC_PRER_PREDIV_S 0x00007FFFU
+
+/******************** Bits definition for RTC_WUTR register *****************/
+#define RTC_WUTR_WUT 0x0000FFFFU
+
+/******************** Bits definition for RTC_CALIBR register ***************/
+#define RTC_CALIBR_DCS 0x00000080U
+#define RTC_CALIBR_DC 0x0000001FU
+
+/******************** Bits definition for RTC_ALRMAR register ***************/
+#define RTC_ALRMAR_MSK4 0x80000000U
+#define RTC_ALRMAR_WDSEL 0x40000000U
+#define RTC_ALRMAR_DT 0x30000000U
+#define RTC_ALRMAR_DT_0 0x10000000U
+#define RTC_ALRMAR_DT_1 0x20000000U
+#define RTC_ALRMAR_DU 0x0F000000U
+#define RTC_ALRMAR_DU_0 0x01000000U
+#define RTC_ALRMAR_DU_1 0x02000000U
+#define RTC_ALRMAR_DU_2 0x04000000U
+#define RTC_ALRMAR_DU_3 0x08000000U
+#define RTC_ALRMAR_MSK3 0x00800000U
+#define RTC_ALRMAR_PM 0x00400000U
+#define RTC_ALRMAR_HT 0x00300000U
+#define RTC_ALRMAR_HT_0 0x00100000U
+#define RTC_ALRMAR_HT_1 0x00200000U
+#define RTC_ALRMAR_HU 0x000F0000U
+#define RTC_ALRMAR_HU_0 0x00010000U
+#define RTC_ALRMAR_HU_1 0x00020000U
+#define RTC_ALRMAR_HU_2 0x00040000U
+#define RTC_ALRMAR_HU_3 0x00080000U
+#define RTC_ALRMAR_MSK2 0x00008000U
+#define RTC_ALRMAR_MNT 0x00007000U
+#define RTC_ALRMAR_MNT_0 0x00001000U
+#define RTC_ALRMAR_MNT_1 0x00002000U
+#define RTC_ALRMAR_MNT_2 0x00004000U
+#define RTC_ALRMAR_MNU 0x00000F00U
+#define RTC_ALRMAR_MNU_0 0x00000100U
+#define RTC_ALRMAR_MNU_1 0x00000200U
+#define RTC_ALRMAR_MNU_2 0x00000400U
+#define RTC_ALRMAR_MNU_3 0x00000800U
+#define RTC_ALRMAR_MSK1 0x00000080U
+#define RTC_ALRMAR_ST 0x00000070U
+#define RTC_ALRMAR_ST_0 0x00000010U
+#define RTC_ALRMAR_ST_1 0x00000020U
+#define RTC_ALRMAR_ST_2 0x00000040U
+#define RTC_ALRMAR_SU 0x0000000FU
+#define RTC_ALRMAR_SU_0 0x00000001U
+#define RTC_ALRMAR_SU_1 0x00000002U
+#define RTC_ALRMAR_SU_2 0x00000004U
+#define RTC_ALRMAR_SU_3 0x00000008U
+
+/******************** Bits definition for RTC_ALRMBR register ***************/
+#define RTC_ALRMBR_MSK4 0x80000000U
+#define RTC_ALRMBR_WDSEL 0x40000000U
+#define RTC_ALRMBR_DT 0x30000000U
+#define RTC_ALRMBR_DT_0 0x10000000U
+#define RTC_ALRMBR_DT_1 0x20000000U
+#define RTC_ALRMBR_DU 0x0F000000U
+#define RTC_ALRMBR_DU_0 0x01000000U
+#define RTC_ALRMBR_DU_1 0x02000000U
+#define RTC_ALRMBR_DU_2 0x04000000U
+#define RTC_ALRMBR_DU_3 0x08000000U
+#define RTC_ALRMBR_MSK3 0x00800000U
+#define RTC_ALRMBR_PM 0x00400000U
+#define RTC_ALRMBR_HT 0x00300000U
+#define RTC_ALRMBR_HT_0 0x00100000U
+#define RTC_ALRMBR_HT_1 0x00200000U
+#define RTC_ALRMBR_HU 0x000F0000U
+#define RTC_ALRMBR_HU_0 0x00010000U
+#define RTC_ALRMBR_HU_1 0x00020000U
+#define RTC_ALRMBR_HU_2 0x00040000U
+#define RTC_ALRMBR_HU_3 0x00080000U
+#define RTC_ALRMBR_MSK2 0x00008000U
+#define RTC_ALRMBR_MNT 0x00007000U
+#define RTC_ALRMBR_MNT_0 0x00001000U
+#define RTC_ALRMBR_MNT_1 0x00002000U
+#define RTC_ALRMBR_MNT_2 0x00004000U
+#define RTC_ALRMBR_MNU 0x00000F00U
+#define RTC_ALRMBR_MNU_0 0x00000100U
+#define RTC_ALRMBR_MNU_1 0x00000200U
+#define RTC_ALRMBR_MNU_2 0x00000400U
+#define RTC_ALRMBR_MNU_3 0x00000800U
+#define RTC_ALRMBR_MSK1 0x00000080U
+#define RTC_ALRMBR_ST 0x00000070U
+#define RTC_ALRMBR_ST_0 0x00000010U
+#define RTC_ALRMBR_ST_1 0x00000020U
+#define RTC_ALRMBR_ST_2 0x00000040U
+#define RTC_ALRMBR_SU 0x0000000FU
+#define RTC_ALRMBR_SU_0 0x00000001U
+#define RTC_ALRMBR_SU_1 0x00000002U
+#define RTC_ALRMBR_SU_2 0x00000004U
+#define RTC_ALRMBR_SU_3 0x00000008U
+
+/******************** Bits definition for RTC_WPR register ******************/
+#define RTC_WPR_KEY 0x000000FFU
+
+/******************** Bits definition for RTC_SSR register ******************/
+#define RTC_SSR_SS 0x0000FFFFU
+
+/******************** Bits definition for RTC_SHIFTR register ***************/
+#define RTC_SHIFTR_SUBFS 0x00007FFFU
+#define RTC_SHIFTR_ADD1S 0x80000000U
+
+/******************** Bits definition for RTC_TSTR register *****************/
+#define RTC_TSTR_PM 0x00400000U
+#define RTC_TSTR_HT 0x00300000U
+#define RTC_TSTR_HT_0 0x00100000U
+#define RTC_TSTR_HT_1 0x00200000U
+#define RTC_TSTR_HU 0x000F0000U
+#define RTC_TSTR_HU_0 0x00010000U
+#define RTC_TSTR_HU_1 0x00020000U
+#define RTC_TSTR_HU_2 0x00040000U
+#define RTC_TSTR_HU_3 0x00080000U
+#define RTC_TSTR_MNT 0x00007000U
+#define RTC_TSTR_MNT_0 0x00001000U
+#define RTC_TSTR_MNT_1 0x00002000U
+#define RTC_TSTR_MNT_2 0x00004000U
+#define RTC_TSTR_MNU 0x00000F00U
+#define RTC_TSTR_MNU_0 0x00000100U
+#define RTC_TSTR_MNU_1 0x00000200U
+#define RTC_TSTR_MNU_2 0x00000400U
+#define RTC_TSTR_MNU_3 0x00000800U
+#define RTC_TSTR_ST 0x00000070U
+#define RTC_TSTR_ST_0 0x00000010U
+#define RTC_TSTR_ST_1 0x00000020U
+#define RTC_TSTR_ST_2 0x00000040U
+#define RTC_TSTR_SU 0x0000000FU
+#define RTC_TSTR_SU_0 0x00000001U
+#define RTC_TSTR_SU_1 0x00000002U
+#define RTC_TSTR_SU_2 0x00000004U
+#define RTC_TSTR_SU_3 0x00000008U
+
+/******************** Bits definition for RTC_TSDR register *****************/
+#define RTC_TSDR_WDU 0x0000E000U
+#define RTC_TSDR_WDU_0 0x00002000U
+#define RTC_TSDR_WDU_1 0x00004000U
+#define RTC_TSDR_WDU_2 0x00008000U
+#define RTC_TSDR_MT 0x00001000U
+#define RTC_TSDR_MU 0x00000F00U
+#define RTC_TSDR_MU_0 0x00000100U
+#define RTC_TSDR_MU_1 0x00000200U
+#define RTC_TSDR_MU_2 0x00000400U
+#define RTC_TSDR_MU_3 0x00000800U
+#define RTC_TSDR_DT 0x00000030U
+#define RTC_TSDR_DT_0 0x00000010U
+#define RTC_TSDR_DT_1 0x00000020U
+#define RTC_TSDR_DU 0x0000000FU
+#define RTC_TSDR_DU_0 0x00000001U
+#define RTC_TSDR_DU_1 0x00000002U
+#define RTC_TSDR_DU_2 0x00000004U
+#define RTC_TSDR_DU_3 0x00000008U
+
+/******************** Bits definition for RTC_TSSSR register ****************/
+#define RTC_TSSSR_SS 0x0000FFFFU
+
+/******************** Bits definition for RTC_CAL register *****************/
+#define RTC_CALR_CALP 0x00008000U
+#define RTC_CALR_CALW8 0x00004000U
+#define RTC_CALR_CALW16 0x00002000U
+#define RTC_CALR_CALM 0x000001FFU
+#define RTC_CALR_CALM_0 0x00000001U
+#define RTC_CALR_CALM_1 0x00000002U
+#define RTC_CALR_CALM_2 0x00000004U
+#define RTC_CALR_CALM_3 0x00000008U
+#define RTC_CALR_CALM_4 0x00000010U
+#define RTC_CALR_CALM_5 0x00000020U
+#define RTC_CALR_CALM_6 0x00000040U
+#define RTC_CALR_CALM_7 0x00000080U
+#define RTC_CALR_CALM_8 0x00000100U
+
+/******************** Bits definition for RTC_TAFCR register ****************/
+#define RTC_TAFCR_ALARMOUTTYPE 0x00040000U
+#define RTC_TAFCR_TSINSEL 0x00020000U
+#define RTC_TAFCR_TAMPINSEL 0x00010000U
+#define RTC_TAFCR_TAMPPUDIS 0x00008000U
+#define RTC_TAFCR_TAMPPRCH 0x00006000U
+#define RTC_TAFCR_TAMPPRCH_0 0x00002000U
+#define RTC_TAFCR_TAMPPRCH_1 0x00004000U
+#define RTC_TAFCR_TAMPFLT 0x00001800U
+#define RTC_TAFCR_TAMPFLT_0 0x00000800U
+#define RTC_TAFCR_TAMPFLT_1 0x00001000U
+#define RTC_TAFCR_TAMPFREQ 0x00000700U
+#define RTC_TAFCR_TAMPFREQ_0 0x00000100U
+#define RTC_TAFCR_TAMPFREQ_1 0x00000200U
+#define RTC_TAFCR_TAMPFREQ_2 0x00000400U
+#define RTC_TAFCR_TAMPTS 0x00000080U
+#define RTC_TAFCR_TAMP2TRG 0x00000010U
+#define RTC_TAFCR_TAMP2E 0x00000008U
+#define RTC_TAFCR_TAMPIE 0x00000004U
+#define RTC_TAFCR_TAMP1TRG 0x00000002U
+#define RTC_TAFCR_TAMP1E 0x00000001U
+
+/******************** Bits definition for RTC_ALRMASSR register *************/
+#define RTC_ALRMASSR_MASKSS 0x0F000000U
+#define RTC_ALRMASSR_MASKSS_0 0x01000000U
+#define RTC_ALRMASSR_MASKSS_1 0x02000000U
+#define RTC_ALRMASSR_MASKSS_2 0x04000000U
+#define RTC_ALRMASSR_MASKSS_3 0x08000000U
+#define RTC_ALRMASSR_SS 0x00007FFFU
+
+/******************** Bits definition for RTC_ALRMBSSR register *************/
+#define RTC_ALRMBSSR_MASKSS 0x0F000000U
+#define RTC_ALRMBSSR_MASKSS_0 0x01000000U
+#define RTC_ALRMBSSR_MASKSS_1 0x02000000U
+#define RTC_ALRMBSSR_MASKSS_2 0x04000000U
+#define RTC_ALRMBSSR_MASKSS_3 0x08000000U
+#define RTC_ALRMBSSR_SS 0x00007FFFU
+
+/******************** Bits definition for RTC_BKP0R register ****************/
+#define RTC_BKP0R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP1R register ****************/
+#define RTC_BKP1R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP2R register ****************/
+#define RTC_BKP2R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP3R register ****************/
+#define RTC_BKP3R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP4R register ****************/
+#define RTC_BKP4R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP5R register ****************/
+#define RTC_BKP5R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP6R register ****************/
+#define RTC_BKP6R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP7R register ****************/
+#define RTC_BKP7R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP8R register ****************/
+#define RTC_BKP8R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP9R register ****************/
+#define RTC_BKP9R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP10R register ***************/
+#define RTC_BKP10R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP11R register ***************/
+#define RTC_BKP11R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP12R register ***************/
+#define RTC_BKP12R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP13R register ***************/
+#define RTC_BKP13R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP14R register ***************/
+#define RTC_BKP14R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP15R register ***************/
+#define RTC_BKP15R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP16R register ***************/
+#define RTC_BKP16R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP17R register ***************/
+#define RTC_BKP17R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP18R register ***************/
+#define RTC_BKP18R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP19R register ***************/
+#define RTC_BKP19R 0xFFFFFFFFU
+
+
+
+/******************************************************************************/
+/* */
+/* SD host Interface */
+/* */
+/******************************************************************************/
+/****************** Bit definition for SDIO_POWER register ******************/
+#define SDIO_POWER_PWRCTRL 0x03U /*!<PWRCTRL[1:0] bits (Power supply control bits) */
+#define SDIO_POWER_PWRCTRL_0 0x01U /*!<Bit 0 */
+#define SDIO_POWER_PWRCTRL_1 0x02U /*!<Bit 1 */
+
+/****************** Bit definition for SDIO_CLKCR register ******************/
+#define SDIO_CLKCR_CLKDIV 0x00FFU /*!<Clock divide factor */
+#define SDIO_CLKCR_CLKEN 0x0100U /*!<Clock enable bit */
+#define SDIO_CLKCR_PWRSAV 0x0200U /*!<Power saving configuration bit */
+#define SDIO_CLKCR_BYPASS 0x0400U /*!<Clock divider bypass enable bit */
+
+#define SDIO_CLKCR_WIDBUS 0x1800U /*!<WIDBUS[1:0] bits (Wide bus mode enable bit) */
+#define SDIO_CLKCR_WIDBUS_0 0x0800U /*!<Bit 0 */
+#define SDIO_CLKCR_WIDBUS_1 0x1000U /*!<Bit 1 */
+
+#define SDIO_CLKCR_NEGEDGE 0x2000U /*!<SDIO_CK dephasing selection bit */
+#define SDIO_CLKCR_HWFC_EN 0x4000U /*!<HW Flow Control enable */
+
+/******************* Bit definition for SDIO_ARG register *******************/
+#define SDIO_ARG_CMDARG 0xFFFFFFFFU /*!<Command argument */
+
+/******************* Bit definition for SDIO_CMD register *******************/
+#define SDIO_CMD_CMDINDEX 0x003FU /*!<Command Index */
+
+#define SDIO_CMD_WAITRESP 0x00C0U /*!<WAITRESP[1:0] bits (Wait for response bits) */
+#define SDIO_CMD_WAITRESP_0 0x0040U /*!< Bit 0 */
+#define SDIO_CMD_WAITRESP_1 0x0080U /*!< Bit 1 */
+
+#define SDIO_CMD_WAITINT 0x0100U /*!<CPSM Waits for Interrupt Request */
+#define SDIO_CMD_WAITPEND 0x0200U /*!<CPSM Waits for ends of data transfer (CmdPend internal signal) */
+#define SDIO_CMD_CPSMEN 0x0400U /*!<Command path state machine (CPSM) Enable bit */
+#define SDIO_CMD_SDIOSUSPEND 0x0800U /*!<SD I/O suspend command */
+#define SDIO_CMD_ENCMDCOMPL 0x1000U /*!<Enable CMD completion */
+#define SDIO_CMD_NIEN 0x2000U /*!<Not Interrupt Enable */
+#define SDIO_CMD_CEATACMD 0x4000U /*!<CE-ATA command */
+
+/***************** Bit definition for SDIO_RESPCMD register *****************/
+#define SDIO_RESPCMD_RESPCMD 0x3FU /*!<Response command index */
+
+/****************** Bit definition for SDIO_RESP0 register ******************/
+#define SDIO_RESP0_CARDSTATUS0 0xFFFFFFFFU /*!<Card Status */
+
+/****************** Bit definition for SDIO_RESP1 register ******************/
+#define SDIO_RESP1_CARDSTATUS1 0xFFFFFFFFU /*!<Card Status */
+
+/****************** Bit definition for SDIO_RESP2 register ******************/
+#define SDIO_RESP2_CARDSTATUS2 0xFFFFFFFFU /*!<Card Status */
+
+/****************** Bit definition for SDIO_RESP3 register ******************/
+#define SDIO_RESP3_CARDSTATUS3 0xFFFFFFFFU /*!<Card Status */
+
+/****************** Bit definition for SDIO_RESP4 register ******************/
+#define SDIO_RESP4_CARDSTATUS4 0xFFFFFFFFU /*!<Card Status */
+
+/****************** Bit definition for SDIO_DTIMER register *****************/
+#define SDIO_DTIMER_DATATIME 0xFFFFFFFFU /*!<Data timeout period. */
+
+/****************** Bit definition for SDIO_DLEN register *******************/
+#define SDIO_DLEN_DATALENGTH 0x01FFFFFFU /*!<Data length value */
+
+/****************** Bit definition for SDIO_DCTRL register ******************/
+#define SDIO_DCTRL_DTEN 0x0001U /*!<Data transfer enabled bit */
+#define SDIO_DCTRL_DTDIR 0x0002U /*!<Data transfer direction selection */
+#define SDIO_DCTRL_DTMODE 0x0004U /*!<Data transfer mode selection */
+#define SDIO_DCTRL_DMAEN 0x0008U /*!<DMA enabled bit */
+
+#define SDIO_DCTRL_DBLOCKSIZE 0x00F0U /*!<DBLOCKSIZE[3:0] bits (Data block size) */
+#define SDIO_DCTRL_DBLOCKSIZE_0 0x0010U /*!<Bit 0 */
+#define SDIO_DCTRL_DBLOCKSIZE_1 0x0020U /*!<Bit 1 */
+#define SDIO_DCTRL_DBLOCKSIZE_2 0x0040U /*!<Bit 2 */
+#define SDIO_DCTRL_DBLOCKSIZE_3 0x0080U /*!<Bit 3 */
+
+#define SDIO_DCTRL_RWSTART 0x0100U /*!<Read wait start */
+#define SDIO_DCTRL_RWSTOP 0x0200U /*!<Read wait stop */
+#define SDIO_DCTRL_RWMOD 0x0400U /*!<Read wait mode */
+#define SDIO_DCTRL_SDIOEN 0x0800U /*!<SD I/O enable functions */
+
+/****************** Bit definition for SDIO_DCOUNT register *****************/
+#define SDIO_DCOUNT_DATACOUNT 0x01FFFFFFU /*!<Data count value */
+
+/****************** Bit definition for SDIO_STA register ********************/
+#define SDIO_STA_CCRCFAIL 0x00000001U /*!<Command response received (CRC check failed) */
+#define SDIO_STA_DCRCFAIL 0x00000002U /*!<Data block sent/received (CRC check failed) */
+#define SDIO_STA_CTIMEOUT 0x00000004U /*!<Command response timeout */
+#define SDIO_STA_DTIMEOUT 0x00000008U /*!<Data timeout */
+#define SDIO_STA_TXUNDERR 0x00000010U /*!<Transmit FIFO underrun error */
+#define SDIO_STA_RXOVERR 0x00000020U /*!<Received FIFO overrun error */
+#define SDIO_STA_CMDREND 0x00000040U /*!<Command response received (CRC check passed) */
+#define SDIO_STA_CMDSENT 0x00000080U /*!<Command sent (no response required) */
+#define SDIO_STA_DATAEND 0x00000100U /*!<Data end (data counter, SDIDCOUNT, is zero) */
+#define SDIO_STA_STBITERR 0x00000200U /*!<Start bit not detected on all data signals in wide bus mode */
+#define SDIO_STA_DBCKEND 0x00000400U /*!<Data block sent/received (CRC check passed) */
+#define SDIO_STA_CMDACT 0x00000800U /*!<Command transfer in progress */
+#define SDIO_STA_TXACT 0x00001000U /*!<Data transmit in progress */
+#define SDIO_STA_RXACT 0x00002000U /*!<Data receive in progress */
+#define SDIO_STA_TXFIFOHE 0x00004000U /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
+#define SDIO_STA_RXFIFOHF 0x00008000U /*!<Receive FIFO Half Full: there are at least 8 words in the FIFO */
+#define SDIO_STA_TXFIFOF 0x00010000U /*!<Transmit FIFO full */
+#define SDIO_STA_RXFIFOF 0x00020000U /*!<Receive FIFO full */
+#define SDIO_STA_TXFIFOE 0x00040000U /*!<Transmit FIFO empty */
+#define SDIO_STA_RXFIFOE 0x00080000U /*!<Receive FIFO empty */
+#define SDIO_STA_TXDAVL 0x00100000U /*!<Data available in transmit FIFO */
+#define SDIO_STA_RXDAVL 0x00200000U /*!<Data available in receive FIFO */
+#define SDIO_STA_SDIOIT 0x00400000U /*!<SDIO interrupt received */
+#define SDIO_STA_CEATAEND 0x00800000U /*!<CE-ATA command completion signal received for CMD61 */
+
+/******************* Bit definition for SDIO_ICR register *******************/
+#define SDIO_ICR_CCRCFAILC 0x00000001U /*!<CCRCFAIL flag clear bit */
+#define SDIO_ICR_DCRCFAILC 0x00000002U /*!<DCRCFAIL flag clear bit */
+#define SDIO_ICR_CTIMEOUTC 0x00000004U /*!<CTIMEOUT flag clear bit */
+#define SDIO_ICR_DTIMEOUTC 0x00000008U /*!<DTIMEOUT flag clear bit */
+#define SDIO_ICR_TXUNDERRC 0x00000010U /*!<TXUNDERR flag clear bit */
+#define SDIO_ICR_RXOVERRC 0x00000020U /*!<RXOVERR flag clear bit */
+#define SDIO_ICR_CMDRENDC 0x00000040U /*!<CMDREND flag clear bit */
+#define SDIO_ICR_CMDSENTC 0x00000080U /*!<CMDSENT flag clear bit */
+#define SDIO_ICR_DATAENDC 0x00000100U /*!<DATAEND flag clear bit */
+#define SDIO_ICR_STBITERRC 0x00000200U /*!<STBITERR flag clear bit */
+#define SDIO_ICR_DBCKENDC 0x00000400U /*!<DBCKEND flag clear bit */
+#define SDIO_ICR_SDIOITC 0x00400000U /*!<SDIOIT flag clear bit */
+#define SDIO_ICR_CEATAENDC 0x00800000U /*!<CEATAEND flag clear bit */
+
+/****************** Bit definition for SDIO_MASK register *******************/
+#define SDIO_MASK_CCRCFAILIE 0x00000001U /*!<Command CRC Fail Interrupt Enable */
+#define SDIO_MASK_DCRCFAILIE 0x00000002U /*!<Data CRC Fail Interrupt Enable */
+#define SDIO_MASK_CTIMEOUTIE 0x00000004U /*!<Command TimeOut Interrupt Enable */
+#define SDIO_MASK_DTIMEOUTIE 0x00000008U /*!<Data TimeOut Interrupt Enable */
+#define SDIO_MASK_TXUNDERRIE 0x00000010U /*!<Tx FIFO UnderRun Error Interrupt Enable */
+#define SDIO_MASK_RXOVERRIE 0x00000020U /*!<Rx FIFO OverRun Error Interrupt Enable */
+#define SDIO_MASK_CMDRENDIE 0x00000040U /*!<Command Response Received Interrupt Enable */
+#define SDIO_MASK_CMDSENTIE 0x00000080U /*!<Command Sent Interrupt Enable */
+#define SDIO_MASK_DATAENDIE 0x00000100U /*!<Data End Interrupt Enable */
+#define SDIO_MASK_STBITERRIE 0x00000200U /*!<Start Bit Error Interrupt Enable */
+#define SDIO_MASK_DBCKENDIE 0x00000400U /*!<Data Block End Interrupt Enable */
+#define SDIO_MASK_CMDACTIE 0x00000800U /*!<CCommand Acting Interrupt Enable */
+#define SDIO_MASK_TXACTIE 0x00001000U /*!<Data Transmit Acting Interrupt Enable */
+#define SDIO_MASK_RXACTIE 0x00002000U /*!<Data receive acting interrupt enabled */
+#define SDIO_MASK_TXFIFOHEIE 0x00004000U /*!<Tx FIFO Half Empty interrupt Enable */
+#define SDIO_MASK_RXFIFOHFIE 0x00008000U /*!<Rx FIFO Half Full interrupt Enable */
+#define SDIO_MASK_TXFIFOFIE 0x00010000U /*!<Tx FIFO Full interrupt Enable */
+#define SDIO_MASK_RXFIFOFIE 0x00020000U /*!<Rx FIFO Full interrupt Enable */
+#define SDIO_MASK_TXFIFOEIE 0x00040000U /*!<Tx FIFO Empty interrupt Enable */
+#define SDIO_MASK_RXFIFOEIE 0x00080000U /*!<Rx FIFO Empty interrupt Enable */
+#define SDIO_MASK_TXDAVLIE 0x00100000U /*!<Data available in Tx FIFO interrupt Enable */
+#define SDIO_MASK_RXDAVLIE 0x00200000U /*!<Data available in Rx FIFO interrupt Enable */
+#define SDIO_MASK_SDIOITIE 0x00400000U /*!<SDIO Mode Interrupt Received interrupt Enable */
+#define SDIO_MASK_CEATAENDIE 0x00800000U /*!<CE-ATA command completion signal received Interrupt Enable */
+
+/***************** Bit definition for SDIO_FIFOCNT register *****************/
+#define SDIO_FIFOCNT_FIFOCOUNT 0x00FFFFFFU /*!<Remaining number of words to be written to or read from the FIFO */
+
+/****************** Bit definition for SDIO_FIFO register *******************/
+#define SDIO_FIFO_FIFODATA 0xFFFFFFFFU /*!<Receive and transmit FIFO data */
+
+/******************************************************************************/
+/* */
+/* Serial Peripheral Interface */
+/* */
+/******************************************************************************/
+/******************* Bit definition for SPI_CR1 register ********************/
+#define SPI_CR1_CPHA 0x00000001U /*!<Clock Phase */
+#define SPI_CR1_CPOL 0x00000002U /*!<Clock Polarity */
+#define SPI_CR1_MSTR 0x00000004U /*!<Master Selection */
+
+#define SPI_CR1_BR 0x00000038U /*!<BR[2:0] bits (Baud Rate Control) */
+#define SPI_CR1_BR_0 0x00000008U /*!<Bit 0 */
+#define SPI_CR1_BR_1 0x00000010U /*!<Bit 1 */
+#define SPI_CR1_BR_2 0x00000020U /*!<Bit 2 */
+
+#define SPI_CR1_SPE 0x00000040U /*!<SPI Enable */
+#define SPI_CR1_LSBFIRST 0x00000080U /*!<Frame Format */
+#define SPI_CR1_SSI 0x00000100U /*!<Internal slave select */
+#define SPI_CR1_SSM 0x00000200U /*!<Software slave management */
+#define SPI_CR1_RXONLY 0x00000400U /*!<Receive only */
+#define SPI_CR1_DFF 0x00000800U /*!<Data Frame Format */
+#define SPI_CR1_CRCNEXT 0x00001000U /*!<Transmit CRC next */
+#define SPI_CR1_CRCEN 0x00002000U /*!<Hardware CRC calculation enable */
+#define SPI_CR1_BIDIOE 0x00004000U /*!<Output enable in bidirectional mode */
+#define SPI_CR1_BIDIMODE 0x00008000U /*!<Bidirectional data mode enable */
+
+/******************* Bit definition for SPI_CR2 register ********************/
+#define SPI_CR2_RXDMAEN 0x00000001U /*!<Rx Buffer DMA Enable */
+#define SPI_CR2_TXDMAEN 0x00000002U /*!<Tx Buffer DMA Enable */
+#define SPI_CR2_SSOE 0x00000004U /*!<SS Output Enable */
+#define SPI_CR2_FRF 0x00000010U /*!<Frame Format */
+#define SPI_CR2_ERRIE 0x00000020U /*!<Error Interrupt Enable */
+#define SPI_CR2_RXNEIE 0x00000040U /*!<RX buffer Not Empty Interrupt Enable */
+#define SPI_CR2_TXEIE 0x00000080U /*!<Tx buffer Empty Interrupt Enable */
+
+/******************** Bit definition for SPI_SR register ********************/
+#define SPI_SR_RXNE 0x00000001U /*!<Receive buffer Not Empty */
+#define SPI_SR_TXE 0x00000002U /*!<Transmit buffer Empty */
+#define SPI_SR_CHSIDE 0x00000004U /*!<Channel side */
+#define SPI_SR_UDR 0x00000008U /*!<Underrun flag */
+#define SPI_SR_CRCERR 0x00000010U /*!<CRC Error flag */
+#define SPI_SR_MODF 0x00000020U /*!<Mode fault */
+#define SPI_SR_OVR 0x00000040U /*!<Overrun flag */
+#define SPI_SR_BSY 0x00000080U /*!<Busy flag */
+#define SPI_SR_FRE 0x00000100U /*!<Frame format error flag */
+
+/******************** Bit definition for SPI_DR register ********************/
+#define SPI_DR_DR 0x0000FFFFU /*!<Data Register */
+
+/******************* Bit definition for SPI_CRCPR register ******************/
+#define SPI_CRCPR_CRCPOLY 0x0000FFFFU /*!<CRC polynomial register */
+
+/****************** Bit definition for SPI_RXCRCR register ******************/
+#define SPI_RXCRCR_RXCRC 0x0000FFFFU /*!<Rx CRC Register */
+
+/****************** Bit definition for SPI_TXCRCR register ******************/
+#define SPI_TXCRCR_TXCRC 0x0000FFFFU /*!<Tx CRC Register */
+
+/****************** Bit definition for SPI_I2SCFGR register *****************/
+#define SPI_I2SCFGR_CHLEN 0x00000001U /*!<Channel length (number of bits per audio channel) */
+
+#define SPI_I2SCFGR_DATLEN 0x00000006U /*!<DATLEN[1:0] bits (Data length to be transferred) */
+#define SPI_I2SCFGR_DATLEN_0 0x00000002U /*!<Bit 0 */
+#define SPI_I2SCFGR_DATLEN_1 0x00000004U /*!<Bit 1 */
+
+#define SPI_I2SCFGR_CKPOL 0x00000008U /*!<steady state clock polarity */
+
+#define SPI_I2SCFGR_I2SSTD 0x00000030U /*!<I2SSTD[1:0] bits (I2S standard selection) */
+#define SPI_I2SCFGR_I2SSTD_0 0x00000010U /*!<Bit 0 */
+#define SPI_I2SCFGR_I2SSTD_1 0x00000020U /*!<Bit 1 */
+
+#define SPI_I2SCFGR_PCMSYNC 0x00000080U /*!<PCM frame synchronization */
+
+#define SPI_I2SCFGR_I2SCFG 0x00000300U /*!<I2SCFG[1:0] bits (I2S configuration mode) */
+#define SPI_I2SCFGR_I2SCFG_0 0x00000100U /*!<Bit 0 */
+#define SPI_I2SCFGR_I2SCFG_1 0x00000200U /*!<Bit 1 */
+
+#define SPI_I2SCFGR_I2SE 0x00000400U /*!<I2S Enable */
+#define SPI_I2SCFGR_I2SMOD 0x00000800U /*!<I2S mode selection */
+
+/****************** Bit definition for SPI_I2SPR register *******************/
+#define SPI_I2SPR_I2SDIV 0x000000FFU /*!<I2S Linear prescaler */
+#define SPI_I2SPR_ODD 0x00000100U /*!<Odd factor for the prescaler */
+#define SPI_I2SPR_MCKOE 0x00000200U /*!<Master Clock Output Enable */
+
+/******************************************************************************/
+/* */
+/* SYSCFG */
+/* */
+/******************************************************************************/
+/****************** Bit definition for SYSCFG_MEMRMP register ***************/
+#define SYSCFG_MEMRMP_MEM_MODE 0x00000007U /*!< SYSCFG_Memory Remap Config */
+#define SYSCFG_MEMRMP_MEM_MODE_0 0x00000001U
+#define SYSCFG_MEMRMP_MEM_MODE_1 0x00000002U
+#define SYSCFG_MEMRMP_MEM_MODE_2 0x00000004U
+
+/****************** Bit definition for SYSCFG_PMC register ******************/
+#define SYSCFG_PMC_MII_RMII_SEL 0x00800000U /*!<Ethernet PHY interface selection */
+/* Old MII_RMII_SEL bit definition, maintained for legacy purpose */
+#define SYSCFG_PMC_MII_RMII SYSCFG_PMC_MII_RMII_SEL
+
+/***************** Bit definition for SYSCFG_EXTICR1 register ***************/
+#define SYSCFG_EXTICR1_EXTI0 0x000FU /*!<EXTI 0 configuration */
+#define SYSCFG_EXTICR1_EXTI1 0x00F0U /*!<EXTI 1 configuration */
+#define SYSCFG_EXTICR1_EXTI2 0x0F00U /*!<EXTI 2 configuration */
+#define SYSCFG_EXTICR1_EXTI3 0xF000U /*!<EXTI 3 configuration */
+/**
+ * @brief EXTI0 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI0_PA 0x0000U /*!<PA[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PB 0x0001U /*!<PB[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PC 0x0002U /*!<PC[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PD 0x0003U /*!<PD[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PE 0x0004U /*!<PE[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PF 0x0005U /*!<PF[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PG 0x0006U /*!<PG[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PH 0x0007U /*!<PH[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PI 0x0008U /*!<PI[0] pin */
+
+/**
+ * @brief EXTI1 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI1_PA 0x0000U /*!<PA[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PB 0x0010U /*!<PB[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PC 0x0020U /*!<PC[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PD 0x0030U /*!<PD[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PE 0x0040U /*!<PE[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PF 0x0050U /*!<PF[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PG 0x0060U /*!<PG[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PH 0x0070U /*!<PH[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PI 0x0080U /*!<PI[1] pin */
+
+/**
+ * @brief EXTI2 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI2_PA 0x0000U /*!<PA[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PB 0x0100U /*!<PB[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PC 0x0200U /*!<PC[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PD 0x0300U /*!<PD[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PE 0x0400U /*!<PE[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PF 0x0500U /*!<PF[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PG 0x0600U /*!<PG[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PH 0x0700U /*!<PH[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PI 0x0800U /*!<PI[2] pin */
+
+/**
+ * @brief EXTI3 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI3_PA 0x0000U /*!<PA[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PB 0x1000U /*!<PB[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PC 0x2000U /*!<PC[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PD 0x3000U /*!<PD[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PE 0x4000U /*!<PE[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PF 0x5000U /*!<PF[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PG 0x6000U /*!<PG[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PH 0x7000U /*!<PH[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PI 0x8000U /*!<PI[3] pin */
+
+/***************** Bit definition for SYSCFG_EXTICR2 register ***************/
+#define SYSCFG_EXTICR2_EXTI4 0x000FU /*!<EXTI 4 configuration */
+#define SYSCFG_EXTICR2_EXTI5 0x00F0U /*!<EXTI 5 configuration */
+#define SYSCFG_EXTICR2_EXTI6 0x0F00U /*!<EXTI 6 configuration */
+#define SYSCFG_EXTICR2_EXTI7 0xF000U /*!<EXTI 7 configuration */
+/**
+ * @brief EXTI4 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI4_PA 0x0000U /*!<PA[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PB 0x0001U /*!<PB[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PC 0x0002U /*!<PC[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PD 0x0003U /*!<PD[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PE 0x0004U /*!<PE[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PF 0x0005U /*!<PF[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PG 0x0006U /*!<PG[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PH 0x0007U /*!<PH[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PI 0x0008U /*!<PI[4] pin */
+
+/**
+ * @brief EXTI5 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI5_PA 0x0000U /*!<PA[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PB 0x0010U /*!<PB[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PC 0x0020U /*!<PC[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PD 0x0030U /*!<PD[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PE 0x0040U /*!<PE[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PF 0x0050U /*!<PF[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PG 0x0060U /*!<PG[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PH 0x0070U /*!<PH[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PI 0x0080U /*!<PI[5] pin */
+
+/**
+ * @brief EXTI6 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI6_PA 0x0000U /*!<PA[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PB 0x0100U /*!<PB[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PC 0x0200U /*!<PC[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PD 0x0300U /*!<PD[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PE 0x0400U /*!<PE[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PF 0x0500U /*!<PF[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PG 0x0600U /*!<PG[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PH 0x0700U /*!<PH[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PI 0x0800U /*!<PI[6] pin */
+
+/**
+ * @brief EXTI7 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI7_PA 0x0000U /*!<PA[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PB 0x1000U /*!<PB[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PC 0x2000U /*!<PC[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PD 0x3000U /*!<PD[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PE 0x4000U /*!<PE[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PF 0x5000U /*!<PF[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PG 0x6000U /*!<PG[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PH 0x7000U /*!<PH[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PI 0x8000U /*!<PI[7] pin */
+
+
+/***************** Bit definition for SYSCFG_EXTICR3 register ***************/
+#define SYSCFG_EXTICR3_EXTI8 0x000FU /*!<EXTI 8 configuration */
+#define SYSCFG_EXTICR3_EXTI9 0x00F0U /*!<EXTI 9 configuration */
+#define SYSCFG_EXTICR3_EXTI10 0x0F00U /*!<EXTI 10 configuration */
+#define SYSCFG_EXTICR3_EXTI11 0xF000U /*!<EXTI 11 configuration */
+
+/**
+ * @brief EXTI8 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI8_PA 0x0000U /*!<PA[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PB 0x0001U /*!<PB[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PC 0x0002U /*!<PC[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PD 0x0003U /*!<PD[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PE 0x0004U /*!<PE[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PF 0x0005U /*!<PF[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PG 0x0006U /*!<PG[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PH 0x0007U /*!<PH[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PI 0x0008U /*!<PI[8] pin */
+
+/**
+ * @brief EXTI9 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI9_PA 0x0000U /*!<PA[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PB 0x0010U /*!<PB[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PC 0x0020U /*!<PC[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PD 0x0030U /*!<PD[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PE 0x0040U /*!<PE[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PF 0x0050U /*!<PF[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PG 0x0060U /*!<PG[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PH 0x0070U /*!<PH[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PI 0x0080U /*!<PI[9] pin */
+
+/**
+ * @brief EXTI10 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI10_PA 0x0000U /*!<PA[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PB 0x0100U /*!<PB[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PC 0x0200U /*!<PC[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PD 0x0300U /*!<PD[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PE 0x0400U /*!<PE[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PF 0x0500U /*!<PF[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PG 0x0600U /*!<PG[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PH 0x0700U /*!<PH[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PI 0x0800U /*!<PI[10] pin */
+
+/**
+ * @brief EXTI11 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI11_PA 0x0000U /*!<PA[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PB 0x1000U /*!<PB[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PC 0x2000U /*!<PC[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PD 0x3000U /*!<PD[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PE 0x4000U /*!<PE[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PF 0x5000U /*!<PF[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PG 0x6000U /*!<PG[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PH 0x7000U /*!<PH[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PI 0x8000U /*!<PI[11] pin */
+
+/***************** Bit definition for SYSCFG_EXTICR4 register ***************/
+#define SYSCFG_EXTICR4_EXTI12 0x000FU /*!<EXTI 12 configuration */
+#define SYSCFG_EXTICR4_EXTI13 0x00F0U /*!<EXTI 13 configuration */
+#define SYSCFG_EXTICR4_EXTI14 0x0F00U /*!<EXTI 14 configuration */
+#define SYSCFG_EXTICR4_EXTI15 0xF000U /*!<EXTI 15 configuration */
+/**
+ * @brief EXTI12 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI12_PA 0x0000U /*!<PA[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PB 0x0001U /*!<PB[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PC 0x0002U /*!<PC[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PD 0x0003U /*!<PD[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PE 0x0004U /*!<PE[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PF 0x0005U /*!<PF[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PG 0x0006U /*!<PG[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PH 0x0007U /*!<PH[12] pin */
+
+/**
+ * @brief EXTI13 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI13_PA 0x0000U /*!<PA[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PB 0x0010U /*!<PB[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PC 0x0020U /*!<PC[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PD 0x0030U /*!<PD[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PE 0x0040U /*!<PE[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PF 0x0050U /*!<PF[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PG 0x0060U /*!<PG[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PH 0x0070U /*!<PH[13] pin */
+
+/**
+ * @brief EXTI14 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI14_PA 0x0000U /*!<PA[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PB 0x0100U /*!<PB[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PC 0x0200U /*!<PC[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PD 0x0300U /*!<PD[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PE 0x0400U /*!<PE[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PF 0x0500U /*!<PF[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PG 0x0600U /*!<PG[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PH 0x0700U /*!<PH[14] pin */
+
+/**
+ * @brief EXTI15 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI15_PA 0x0000U /*!<PA[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PB 0x1000U /*!<PB[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PC 0x2000U /*!<PC[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PD 0x3000U /*!<PD[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PE 0x4000U /*!<PE[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PF 0x5000U /*!<PF[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PG 0x6000U /*!<PG[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PH 0x7000U /*!<PH[15] pin */
+
+/****************** Bit definition for SYSCFG_CMPCR register ****************/
+#define SYSCFG_CMPCR_CMP_PD 0x00000001U /*!<Compensation cell ready flag */
+#define SYSCFG_CMPCR_READY 0x00000100U /*!<Compensation cell power-down */
+
+/******************************************************************************/
+/* */
+/* TIM */
+/* */
+/******************************************************************************/
+/******************* Bit definition for TIM_CR1 register ********************/
+#define TIM_CR1_CEN 0x0001U /*!<Counter enable */
+#define TIM_CR1_UDIS 0x0002U /*!<Update disable */
+#define TIM_CR1_URS 0x0004U /*!<Update request source */
+#define TIM_CR1_OPM 0x0008U /*!<One pulse mode */
+#define TIM_CR1_DIR 0x0010U /*!<Direction */
+
+#define TIM_CR1_CMS 0x0060U /*!<CMS[1:0] bits (Center-aligned mode selection) */
+#define TIM_CR1_CMS_0 0x0020U /*!<Bit 0 */
+#define TIM_CR1_CMS_1 0x0040U /*!<Bit 1 */
+
+#define TIM_CR1_ARPE 0x0080U /*!<Auto-reload preload enable */
+
+#define TIM_CR1_CKD 0x0300U /*!<CKD[1:0] bits (clock division) */
+#define TIM_CR1_CKD_0 0x0100U /*!<Bit 0 */
+#define TIM_CR1_CKD_1 0x0200U /*!<Bit 1 */
+
+/******************* Bit definition for TIM_CR2 register ********************/
+#define TIM_CR2_CCPC 0x0001U /*!<Capture/Compare Preloaded Control */
+#define TIM_CR2_CCUS 0x0004U /*!<Capture/Compare Control Update Selection */
+#define TIM_CR2_CCDS 0x0008U /*!<Capture/Compare DMA Selection */
+
+#define TIM_CR2_MMS 0x0070U /*!<MMS[2:0] bits (Master Mode Selection) */
+#define TIM_CR2_MMS_0 0x0010U /*!<Bit 0 */
+#define TIM_CR2_MMS_1 0x0020U /*!<Bit 1 */
+#define TIM_CR2_MMS_2 0x0040U /*!<Bit 2 */
+
+#define TIM_CR2_TI1S 0x0080U /*!<TI1 Selection */
+#define TIM_CR2_OIS1 0x0100U /*!<Output Idle state 1 (OC1 output) */
+#define TIM_CR2_OIS1N 0x0200U /*!<Output Idle state 1 (OC1N output) */
+#define TIM_CR2_OIS2 0x0400U /*!<Output Idle state 2 (OC2 output) */
+#define TIM_CR2_OIS2N 0x0800U /*!<Output Idle state 2 (OC2N output) */
+#define TIM_CR2_OIS3 0x1000U /*!<Output Idle state 3 (OC3 output) */
+#define TIM_CR2_OIS3N 0x2000U /*!<Output Idle state 3 (OC3N output) */
+#define TIM_CR2_OIS4 0x4000U /*!<Output Idle state 4 (OC4 output) */
+
+/******************* Bit definition for TIM_SMCR register *******************/
+#define TIM_SMCR_SMS 0x0007U /*!<SMS[2:0] bits (Slave mode selection) */
+#define TIM_SMCR_SMS_0 0x0001U /*!<Bit 0 */
+#define TIM_SMCR_SMS_1 0x0002U /*!<Bit 1 */
+#define TIM_SMCR_SMS_2 0x0004U /*!<Bit 2 */
+
+#define TIM_SMCR_TS 0x0070U /*!<TS[2:0] bits (Trigger selection) */
+#define TIM_SMCR_TS_0 0x0010U /*!<Bit 0 */
+#define TIM_SMCR_TS_1 0x0020U /*!<Bit 1 */
+#define TIM_SMCR_TS_2 0x0040U /*!<Bit 2 */
+
+#define TIM_SMCR_MSM 0x0080U /*!<Master/slave mode */
+
+#define TIM_SMCR_ETF 0x0F00U /*!<ETF[3:0] bits (External trigger filter) */
+#define TIM_SMCR_ETF_0 0x0100U /*!<Bit 0 */
+#define TIM_SMCR_ETF_1 0x0200U /*!<Bit 1 */
+#define TIM_SMCR_ETF_2 0x0400U /*!<Bit 2 */
+#define TIM_SMCR_ETF_3 0x0800U /*!<Bit 3 */
+
+#define TIM_SMCR_ETPS 0x3000U /*!<ETPS[1:0] bits (External trigger prescaler) */
+#define TIM_SMCR_ETPS_0 0x1000U /*!<Bit 0 */
+#define TIM_SMCR_ETPS_1 0x2000U /*!<Bit 1 */
+
+#define TIM_SMCR_ECE 0x4000U /*!<External clock enable */
+#define TIM_SMCR_ETP 0x8000U /*!<External trigger polarity */
+
+/******************* Bit definition for TIM_DIER register *******************/
+#define TIM_DIER_UIE 0x0001U /*!<Update interrupt enable */
+#define TIM_DIER_CC1IE 0x0002U /*!<Capture/Compare 1 interrupt enable */
+#define TIM_DIER_CC2IE 0x0004U /*!<Capture/Compare 2 interrupt enable */
+#define TIM_DIER_CC3IE 0x0008U /*!<Capture/Compare 3 interrupt enable */
+#define TIM_DIER_CC4IE 0x0010U /*!<Capture/Compare 4 interrupt enable */
+#define TIM_DIER_COMIE 0x0020U /*!<COM interrupt enable */
+#define TIM_DIER_TIE 0x0040U /*!<Trigger interrupt enable */
+#define TIM_DIER_BIE 0x0080U /*!<Break interrupt enable */
+#define TIM_DIER_UDE 0x0100U /*!<Update DMA request enable */
+#define TIM_DIER_CC1DE 0x0200U /*!<Capture/Compare 1 DMA request enable */
+#define TIM_DIER_CC2DE 0x0400U /*!<Capture/Compare 2 DMA request enable */
+#define TIM_DIER_CC3DE 0x0800U /*!<Capture/Compare 3 DMA request enable */
+#define TIM_DIER_CC4DE 0x1000U /*!<Capture/Compare 4 DMA request enable */
+#define TIM_DIER_COMDE 0x2000U /*!<COM DMA request enable */
+#define TIM_DIER_TDE 0x4000U /*!<Trigger DMA request enable */
+
+/******************** Bit definition for TIM_SR register ********************/
+#define TIM_SR_UIF 0x0001U /*!<Update interrupt Flag */
+#define TIM_SR_CC1IF 0x0002U /*!<Capture/Compare 1 interrupt Flag */
+#define TIM_SR_CC2IF 0x0004U /*!<Capture/Compare 2 interrupt Flag */
+#define TIM_SR_CC3IF 0x0008U /*!<Capture/Compare 3 interrupt Flag */
+#define TIM_SR_CC4IF 0x0010U /*!<Capture/Compare 4 interrupt Flag */
+#define TIM_SR_COMIF 0x0020U /*!<COM interrupt Flag */
+#define TIM_SR_TIF 0x0040U /*!<Trigger interrupt Flag */
+#define TIM_SR_BIF 0x0080U /*!<Break interrupt Flag */
+#define TIM_SR_CC1OF 0x0200U /*!<Capture/Compare 1 Overcapture Flag */
+#define TIM_SR_CC2OF 0x0400U /*!<Capture/Compare 2 Overcapture Flag */
+#define TIM_SR_CC3OF 0x0800U /*!<Capture/Compare 3 Overcapture Flag */
+#define TIM_SR_CC4OF 0x1000U /*!<Capture/Compare 4 Overcapture Flag */
+
+/******************* Bit definition for TIM_EGR register ********************/
+#define TIM_EGR_UG 0x01U /*!<Update Generation */
+#define TIM_EGR_CC1G 0x02U /*!<Capture/Compare 1 Generation */
+#define TIM_EGR_CC2G 0x04U /*!<Capture/Compare 2 Generation */
+#define TIM_EGR_CC3G 0x08U /*!<Capture/Compare 3 Generation */
+#define TIM_EGR_CC4G 0x10U /*!<Capture/Compare 4 Generation */
+#define TIM_EGR_COMG 0x20U /*!<Capture/Compare Control Update Generation */
+#define TIM_EGR_TG 0x40U /*!<Trigger Generation */
+#define TIM_EGR_BG 0x80U /*!<Break Generation */
+
+/****************** Bit definition for TIM_CCMR1 register *******************/
+#define TIM_CCMR1_CC1S 0x0003U /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
+#define TIM_CCMR1_CC1S_0 0x0001U /*!<Bit 0 */
+#define TIM_CCMR1_CC1S_1 0x0002U /*!<Bit 1 */
+
+#define TIM_CCMR1_OC1FE 0x0004U /*!<Output Compare 1 Fast enable */
+#define TIM_CCMR1_OC1PE 0x0008U /*!<Output Compare 1 Preload enable */
+
+#define TIM_CCMR1_OC1M 0x0070U /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
+#define TIM_CCMR1_OC1M_0 0x0010U /*!<Bit 0 */
+#define TIM_CCMR1_OC1M_1 0x0020U /*!<Bit 1 */
+#define TIM_CCMR1_OC1M_2 0x0040U /*!<Bit 2 */
+
+#define TIM_CCMR1_OC1CE 0x0080U /*!<Output Compare 1Clear Enable */
+
+#define TIM_CCMR1_CC2S 0x0300U /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
+#define TIM_CCMR1_CC2S_0 0x0100U /*!<Bit 0 */
+#define TIM_CCMR1_CC2S_1 0x0200U /*!<Bit 1 */
+
+#define TIM_CCMR1_OC2FE 0x0400U /*!<Output Compare 2 Fast enable */
+#define TIM_CCMR1_OC2PE 0x0800U /*!<Output Compare 2 Preload enable */
+
+#define TIM_CCMR1_OC2M 0x7000U /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
+#define TIM_CCMR1_OC2M_0 0x1000U /*!<Bit 0 */
+#define TIM_CCMR1_OC2M_1 0x2000U /*!<Bit 1 */
+#define TIM_CCMR1_OC2M_2 0x4000U /*!<Bit 2 */
+
+#define TIM_CCMR1_OC2CE 0x8000U /*!<Output Compare 2 Clear Enable */
+
+/*----------------------------------------------------------------------------*/
+
+#define TIM_CCMR1_IC1PSC 0x000CU /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
+#define TIM_CCMR1_IC1PSC_0 0x0004U /*!<Bit 0 */
+#define TIM_CCMR1_IC1PSC_1 0x0008U /*!<Bit 1 */
+
+#define TIM_CCMR1_IC1F 0x00F0U /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
+#define TIM_CCMR1_IC1F_0 0x0010U /*!<Bit 0 */
+#define TIM_CCMR1_IC1F_1 0x0020U /*!<Bit 1 */
+#define TIM_CCMR1_IC1F_2 0x0040U /*!<Bit 2 */
+#define TIM_CCMR1_IC1F_3 0x0080U /*!<Bit 3 */
+
+#define TIM_CCMR1_IC2PSC 0x0C00U /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
+#define TIM_CCMR1_IC2PSC_0 0x0400U /*!<Bit 0 */
+#define TIM_CCMR1_IC2PSC_1 0x0800U /*!<Bit 1 */
+
+#define TIM_CCMR1_IC2F 0xF000U /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
+#define TIM_CCMR1_IC2F_0 0x1000U /*!<Bit 0 */
+#define TIM_CCMR1_IC2F_1 0x2000U /*!<Bit 1 */
+#define TIM_CCMR1_IC2F_2 0x4000U /*!<Bit 2 */
+#define TIM_CCMR1_IC2F_3 0x8000U /*!<Bit 3 */
+
+/****************** Bit definition for TIM_CCMR2 register *******************/
+#define TIM_CCMR2_CC3S 0x0003U /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
+#define TIM_CCMR2_CC3S_0 0x0001U /*!<Bit 0 */
+#define TIM_CCMR2_CC3S_1 0x0002U /*!<Bit 1 */
+
+#define TIM_CCMR2_OC3FE 0x0004U /*!<Output Compare 3 Fast enable */
+#define TIM_CCMR2_OC3PE 0x0008U /*!<Output Compare 3 Preload enable */
+
+#define TIM_CCMR2_OC3M 0x0070U /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
+#define TIM_CCMR2_OC3M_0 0x0010U /*!<Bit 0 */
+#define TIM_CCMR2_OC3M_1 0x0020U /*!<Bit 1 */
+#define TIM_CCMR2_OC3M_2 0x0040U /*!<Bit 2 */
+
+#define TIM_CCMR2_OC3CE 0x0080U /*!<Output Compare 3 Clear Enable */
+
+#define TIM_CCMR2_CC4S 0x0300U /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
+#define TIM_CCMR2_CC4S_0 0x0100U /*!<Bit 0 */
+#define TIM_CCMR2_CC4S_1 0x0200U /*!<Bit 1 */
+
+#define TIM_CCMR2_OC4FE 0x0400U /*!<Output Compare 4 Fast enable */
+#define TIM_CCMR2_OC4PE 0x0800U /*!<Output Compare 4 Preload enable */
+
+#define TIM_CCMR2_OC4M 0x7000U /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
+#define TIM_CCMR2_OC4M_0 0x1000U /*!<Bit 0 */
+#define TIM_CCMR2_OC4M_1 0x2000U /*!<Bit 1 */
+#define TIM_CCMR2_OC4M_2 0x4000U /*!<Bit 2 */
+
+#define TIM_CCMR2_OC4CE 0x8000U /*!<Output Compare 4 Clear Enable */
+
+/*----------------------------------------------------------------------------*/
+
+#define TIM_CCMR2_IC3PSC 0x000CU /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
+#define TIM_CCMR2_IC3PSC_0 0x0004U /*!<Bit 0 */
+#define TIM_CCMR2_IC3PSC_1 0x0008U /*!<Bit 1 */
+
+#define TIM_CCMR2_IC3F 0x00F0U /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
+#define TIM_CCMR2_IC3F_0 0x0010U /*!<Bit 0 */
+#define TIM_CCMR2_IC3F_1 0x0020U /*!<Bit 1 */
+#define TIM_CCMR2_IC3F_2 0x0040U /*!<Bit 2 */
+#define TIM_CCMR2_IC3F_3 0x0080U /*!<Bit 3 */
+
+#define TIM_CCMR2_IC4PSC 0x0C00U /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
+#define TIM_CCMR2_IC4PSC_0 0x0400U /*!<Bit 0 */
+#define TIM_CCMR2_IC4PSC_1 0x0800U /*!<Bit 1 */
+
+#define TIM_CCMR2_IC4F 0xF000U /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
+#define TIM_CCMR2_IC4F_0 0x1000U /*!<Bit 0 */
+#define TIM_CCMR2_IC4F_1 0x2000U /*!<Bit 1 */
+#define TIM_CCMR2_IC4F_2 0x4000U /*!<Bit 2 */
+#define TIM_CCMR2_IC4F_3 0x8000U /*!<Bit 3 */
+
+/******************* Bit definition for TIM_CCER register *******************/
+#define TIM_CCER_CC1E 0x0001U /*!<Capture/Compare 1 output enable */
+#define TIM_CCER_CC1P 0x0002U /*!<Capture/Compare 1 output Polarity */
+#define TIM_CCER_CC1NE 0x0004U /*!<Capture/Compare 1 Complementary output enable */
+#define TIM_CCER_CC1NP 0x0008U /*!<Capture/Compare 1 Complementary output Polarity */
+#define TIM_CCER_CC2E 0x0010U /*!<Capture/Compare 2 output enable */
+#define TIM_CCER_CC2P 0x0020U /*!<Capture/Compare 2 output Polarity */
+#define TIM_CCER_CC2NE 0x0040U /*!<Capture/Compare 2 Complementary output enable */
+#define TIM_CCER_CC2NP 0x0080U /*!<Capture/Compare 2 Complementary output Polarity */
+#define TIM_CCER_CC3E 0x0100U /*!<Capture/Compare 3 output enable */
+#define TIM_CCER_CC3P 0x0200U /*!<Capture/Compare 3 output Polarity */
+#define TIM_CCER_CC3NE 0x0400U /*!<Capture/Compare 3 Complementary output enable */
+#define TIM_CCER_CC3NP 0x0800U /*!<Capture/Compare 3 Complementary output Polarity */
+#define TIM_CCER_CC4E 0x1000U /*!<Capture/Compare 4 output enable */
+#define TIM_CCER_CC4P 0x2000U /*!<Capture/Compare 4 output Polarity */
+#define TIM_CCER_CC4NP 0x8000U /*!<Capture/Compare 4 Complementary output Polarity */
+
+/******************* Bit definition for TIM_CNT register ********************/
+#define TIM_CNT_CNT 0xFFFFU /*!<Counter Value */
+
+/******************* Bit definition for TIM_PSC register ********************/
+#define TIM_PSC_PSC 0xFFFFU /*!<Prescaler Value */
+
+/******************* Bit definition for TIM_ARR register ********************/
+#define TIM_ARR_ARR 0xFFFFU /*!<actual auto-reload Value */
+
+/******************* Bit definition for TIM_RCR register ********************/
+#define TIM_RCR_REP 0xFFU /*!<Repetition Counter Value */
+
+/******************* Bit definition for TIM_CCR1 register *******************/
+#define TIM_CCR1_CCR1 0xFFFFU /*!<Capture/Compare 1 Value */
+
+/******************* Bit definition for TIM_CCR2 register *******************/
+#define TIM_CCR2_CCR2 0xFFFFU /*!<Capture/Compare 2 Value */
+
+/******************* Bit definition for TIM_CCR3 register *******************/
+#define TIM_CCR3_CCR3 0xFFFFU /*!<Capture/Compare 3 Value */
+
+/******************* Bit definition for TIM_CCR4 register *******************/
+#define TIM_CCR4_CCR4 0xFFFFU /*!<Capture/Compare 4 Value */
+
+/******************* Bit definition for TIM_BDTR register *******************/
+#define TIM_BDTR_DTG 0x00FFU /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
+#define TIM_BDTR_DTG_0 0x0001U /*!<Bit 0 */
+#define TIM_BDTR_DTG_1 0x0002U /*!<Bit 1 */
+#define TIM_BDTR_DTG_2 0x0004U /*!<Bit 2 */
+#define TIM_BDTR_DTG_3 0x0008U /*!<Bit 3 */
+#define TIM_BDTR_DTG_4 0x0010U /*!<Bit 4 */
+#define TIM_BDTR_DTG_5 0x0020U /*!<Bit 5 */
+#define TIM_BDTR_DTG_6 0x0040U /*!<Bit 6 */
+#define TIM_BDTR_DTG_7 0x0080U /*!<Bit 7 */
+
+#define TIM_BDTR_LOCK 0x0300U /*!<LOCK[1:0] bits (Lock Configuration) */
+#define TIM_BDTR_LOCK_0 0x0100U /*!<Bit 0 */
+#define TIM_BDTR_LOCK_1 0x0200U /*!<Bit 1 */
+
+#define TIM_BDTR_OSSI 0x0400U /*!<Off-State Selection for Idle mode */
+#define TIM_BDTR_OSSR 0x0800U /*!<Off-State Selection for Run mode */
+#define TIM_BDTR_BKE 0x1000U /*!<Break enable */
+#define TIM_BDTR_BKP 0x2000U /*!<Break Polarity */
+#define TIM_BDTR_AOE 0x4000U /*!<Automatic Output enable */
+#define TIM_BDTR_MOE 0x8000U /*!<Main Output enable */
+
+/******************* Bit definition for TIM_DCR register ********************/
+#define TIM_DCR_DBA 0x001FU /*!<DBA[4:0] bits (DMA Base Address) */
+#define TIM_DCR_DBA_0 0x0001U /*!<Bit 0 */
+#define TIM_DCR_DBA_1 0x0002U /*!<Bit 1 */
+#define TIM_DCR_DBA_2 0x0004U /*!<Bit 2 */
+#define TIM_DCR_DBA_3 0x0008U /*!<Bit 3 */
+#define TIM_DCR_DBA_4 0x0010U /*!<Bit 4 */
+
+#define TIM_DCR_DBL 0x1F00U /*!<DBL[4:0] bits (DMA Burst Length) */
+#define TIM_DCR_DBL_0 0x0100U /*!<Bit 0 */
+#define TIM_DCR_DBL_1 0x0200U /*!<Bit 1 */
+#define TIM_DCR_DBL_2 0x0400U /*!<Bit 2 */
+#define TIM_DCR_DBL_3 0x0800U /*!<Bit 3 */
+#define TIM_DCR_DBL_4 0x1000U /*!<Bit 4 */
+
+/******************* Bit definition for TIM_DMAR register *******************/
+#define TIM_DMAR_DMAB 0xFFFFU /*!<DMA register for burst accesses */
+
+/******************* Bit definition for TIM_OR register *********************/
+#define TIM_OR_TI4_RMP 0x00C0U /*!<TI4_RMP[1:0] bits (TIM5 Input 4 remap) */
+#define TIM_OR_TI4_RMP_0 0x0040U /*!<Bit 0 */
+#define TIM_OR_TI4_RMP_1 0x0080U /*!<Bit 1 */
+#define TIM_OR_ITR1_RMP 0x0C00U /*!<ITR1_RMP[1:0] bits (TIM2 Internal trigger 1 remap) */
+#define TIM_OR_ITR1_RMP_0 0x0400U /*!<Bit 0 */
+#define TIM_OR_ITR1_RMP_1 0x0800U /*!<Bit 1 */
+
+
+/******************************************************************************/
+/* */
+/* Universal Synchronous Asynchronous Receiver Transmitter */
+/* */
+/******************************************************************************/
+/******************* Bit definition for USART_SR register *******************/
+#define USART_SR_PE 0x0001U /*!<Parity Error */
+#define USART_SR_FE 0x0002U /*!<Framing Error */
+#define USART_SR_NE 0x0004U /*!<Noise Error Flag */
+#define USART_SR_ORE 0x0008U /*!<OverRun Error */
+#define USART_SR_IDLE 0x0010U /*!<IDLE line detected */
+#define USART_SR_RXNE 0x0020U /*!<Read Data Register Not Empty */
+#define USART_SR_TC 0x0040U /*!<Transmission Complete */
+#define USART_SR_TXE 0x0080U /*!<Transmit Data Register Empty */
+#define USART_SR_LBD 0x0100U /*!<LIN Break Detection Flag */
+#define USART_SR_CTS 0x0200U /*!<CTS Flag */
+
+/******************* Bit definition for USART_DR register *******************/
+#define USART_DR_DR 0x01FFU /*!<Data value */
+
+/****************** Bit definition for USART_BRR register *******************/
+#define USART_BRR_DIV_Fraction 0x000FU /*!<Fraction of USARTDIV */
+#define USART_BRR_DIV_Mantissa 0xFFF0U /*!<Mantissa of USARTDIV */
+
+/****************** Bit definition for USART_CR1 register *******************/
+#define USART_CR1_SBK 0x0001U /*!<Send Break */
+#define USART_CR1_RWU 0x0002U /*!<Receiver wakeup */
+#define USART_CR1_RE 0x0004U /*!<Receiver Enable */
+#define USART_CR1_TE 0x0008U /*!<Transmitter Enable */
+#define USART_CR1_IDLEIE 0x0010U /*!<IDLE Interrupt Enable */
+#define USART_CR1_RXNEIE 0x0020U /*!<RXNE Interrupt Enable */
+#define USART_CR1_TCIE 0x0040U /*!<Transmission Complete Interrupt Enable */
+#define USART_CR1_TXEIE 0x0080U /*!<PE Interrupt Enable */
+#define USART_CR1_PEIE 0x0100U /*!<PE Interrupt Enable */
+#define USART_CR1_PS 0x0200U /*!<Parity Selection */
+#define USART_CR1_PCE 0x0400U /*!<Parity Control Enable */
+#define USART_CR1_WAKE 0x0800U /*!<Wakeup method */
+#define USART_CR1_M 0x1000U /*!<Word length */
+#define USART_CR1_UE 0x2000U /*!<USART Enable */
+#define USART_CR1_OVER8 0x8000U /*!<USART Oversampling by 8 enable */
+
+/****************** Bit definition for USART_CR2 register *******************/
+#define USART_CR2_ADD 0x000FU /*!<Address of the USART node */
+#define USART_CR2_LBDL 0x0020U /*!<LIN Break Detection Length */
+#define USART_CR2_LBDIE 0x0040U /*!<LIN Break Detection Interrupt Enable */
+#define USART_CR2_LBCL 0x0100U /*!<Last Bit Clock pulse */
+#define USART_CR2_CPHA 0x0200U /*!<Clock Phase */
+#define USART_CR2_CPOL 0x0400U /*!<Clock Polarity */
+#define USART_CR2_CLKEN 0x0800U /*!<Clock Enable */
+
+#define USART_CR2_STOP 0x3000U /*!<STOP[1:0] bits (STOP bits) */
+#define USART_CR2_STOP_0 0x1000U /*!<Bit 0 */
+#define USART_CR2_STOP_1 0x2000U /*!<Bit 1 */
+
+#define USART_CR2_LINEN 0x4000U /*!<LIN mode enable */
+
+/****************** Bit definition for USART_CR3 register *******************/
+#define USART_CR3_EIE 0x0001U /*!<Error Interrupt Enable */
+#define USART_CR3_IREN 0x0002U /*!<IrDA mode Enable */
+#define USART_CR3_IRLP 0x0004U /*!<IrDA Low-Power */
+#define USART_CR3_HDSEL 0x0008U /*!<Half-Duplex Selection */
+#define USART_CR3_NACK 0x0010U /*!<Smartcard NACK enable */
+#define USART_CR3_SCEN 0x0020U /*!<Smartcard mode enable */
+#define USART_CR3_DMAR 0x0040U /*!<DMA Enable Receiver */
+#define USART_CR3_DMAT 0x0080U /*!<DMA Enable Transmitter */
+#define USART_CR3_RTSE 0x0100U /*!<RTS Enable */
+#define USART_CR3_CTSE 0x0200U /*!<CTS Enable */
+#define USART_CR3_CTSIE 0x0400U /*!<CTS Interrupt Enable */
+#define USART_CR3_ONEBIT 0x0800U /*!<USART One bit method enable */
+
+/****************** Bit definition for USART_GTPR register ******************/
+#define USART_GTPR_PSC 0x00FFU /*!<PSC[7:0] bits (Prescaler value) */
+#define USART_GTPR_PSC_0 0x0001U /*!<Bit 0 */
+#define USART_GTPR_PSC_1 0x0002U /*!<Bit 1 */
+#define USART_GTPR_PSC_2 0x0004U /*!<Bit 2 */
+#define USART_GTPR_PSC_3 0x0008U /*!<Bit 3 */
+#define USART_GTPR_PSC_4 0x0010U /*!<Bit 4 */
+#define USART_GTPR_PSC_5 0x0020U /*!<Bit 5 */
+#define USART_GTPR_PSC_6 0x0040U /*!<Bit 6 */
+#define USART_GTPR_PSC_7 0x0080U /*!<Bit 7 */
+
+#define USART_GTPR_GT 0xFF00U /*!<Guard time value */
+
+/******************************************************************************/
+/* */
+/* Window WATCHDOG */
+/* */
+/******************************************************************************/
+/******************* Bit definition for WWDG_CR register ********************/
+#define WWDG_CR_T 0x7FU /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
+#define WWDG_CR_T_0 0x01U /*!<Bit 0 */
+#define WWDG_CR_T_1 0x02U /*!<Bit 1 */
+#define WWDG_CR_T_2 0x04U /*!<Bit 2 */
+#define WWDG_CR_T_3 0x08U /*!<Bit 3 */
+#define WWDG_CR_T_4 0x10U /*!<Bit 4 */
+#define WWDG_CR_T_5 0x20U /*!<Bit 5 */
+#define WWDG_CR_T_6 0x40U /*!<Bit 6 */
+/* Legacy defines */
+#define WWDG_CR_T0 WWDG_CR_T_0
+#define WWDG_CR_T1 WWDG_CR_T_1
+#define WWDG_CR_T2 WWDG_CR_T_2
+#define WWDG_CR_T3 WWDG_CR_T_3
+#define WWDG_CR_T4 WWDG_CR_T_4
+#define WWDG_CR_T5 WWDG_CR_T_5
+#define WWDG_CR_T6 WWDG_CR_T_6
+
+#define WWDG_CR_WDGA 0x80U /*!<Activation bit */
+
+/******************* Bit definition for WWDG_CFR register *******************/
+#define WWDG_CFR_W 0x007FU /*!<W[6:0] bits (7-bit window value) */
+#define WWDG_CFR_W_0 0x0001U /*!<Bit 0 */
+#define WWDG_CFR_W_1 0x0002U /*!<Bit 1 */
+#define WWDG_CFR_W_2 0x0004U /*!<Bit 2 */
+#define WWDG_CFR_W_3 0x0008U /*!<Bit 3 */
+#define WWDG_CFR_W_4 0x0010U /*!<Bit 4 */
+#define WWDG_CFR_W_5 0x0020U /*!<Bit 5 */
+#define WWDG_CFR_W_6 0x0040U /*!<Bit 6 */
+/* Legacy defines */
+#define WWDG_CFR_W0 WWDG_CFR_W_0
+#define WWDG_CFR_W1 WWDG_CFR_W_1
+#define WWDG_CFR_W2 WWDG_CFR_W_2
+#define WWDG_CFR_W3 WWDG_CFR_W_3
+#define WWDG_CFR_W4 WWDG_CFR_W_4
+#define WWDG_CFR_W5 WWDG_CFR_W_5
+#define WWDG_CFR_W6 WWDG_CFR_W_6
+
+#define WWDG_CFR_WDGTB 0x0180U /*!<WDGTB[1:0] bits (Timer Base) */
+#define WWDG_CFR_WDGTB_0 0x0080U /*!<Bit 0 */
+#define WWDG_CFR_WDGTB_1 0x0100U /*!<Bit 1 */
+/* Legacy defines */
+#define WWDG_CFR_WDGTB0 WWDG_CFR_WDGTB_0
+#define WWDG_CFR_WDGTB1 WWDG_CFR_WDGTB_1
+
+#define WWDG_CFR_EWI 0x0200U /*!<Early Wakeup Interrupt */
+
+/******************* Bit definition for WWDG_SR register ********************/
+#define WWDG_SR_EWIF 0x01U /*!<Early Wakeup Interrupt Flag */
+
+
+/******************************************************************************/
+/* */
+/* DBG */
+/* */
+/******************************************************************************/
+/******************** Bit definition for DBGMCU_IDCODE register *************/
+#define DBGMCU_IDCODE_DEV_ID 0x00000FFFU
+#define DBGMCU_IDCODE_REV_ID 0xFFFF0000U
+
+/******************** Bit definition for DBGMCU_CR register *****************/
+#define DBGMCU_CR_DBG_SLEEP 0x00000001U
+#define DBGMCU_CR_DBG_STOP 0x00000002U
+#define DBGMCU_CR_DBG_STANDBY 0x00000004U
+#define DBGMCU_CR_TRACE_IOEN 0x00000020U
+
+#define DBGMCU_CR_TRACE_MODE 0x000000C0U
+#define DBGMCU_CR_TRACE_MODE_0 0x00000040U/*!<Bit 0 */
+#define DBGMCU_CR_TRACE_MODE_1 0x00000080U/*!<Bit 1 */
+
+/******************** Bit definition for DBGMCU_APB1_FZ register ************/
+#define DBGMCU_APB1_FZ_DBG_TIM2_STOP 0x00000001U
+#define DBGMCU_APB1_FZ_DBG_TIM3_STOP 0x00000002U
+#define DBGMCU_APB1_FZ_DBG_TIM4_STOP 0x00000004U
+#define DBGMCU_APB1_FZ_DBG_TIM5_STOP 0x00000008U
+#define DBGMCU_APB1_FZ_DBG_TIM6_STOP 0x00000010U
+#define DBGMCU_APB1_FZ_DBG_TIM7_STOP 0x00000020U
+#define DBGMCU_APB1_FZ_DBG_TIM12_STOP 0x00000040U
+#define DBGMCU_APB1_FZ_DBG_TIM13_STOP 0x00000080U
+#define DBGMCU_APB1_FZ_DBG_TIM14_STOP 0x00000100U
+#define DBGMCU_APB1_FZ_DBG_RTC_STOP 0x00000400U
+#define DBGMCU_APB1_FZ_DBG_WWDG_STOP 0x00000800U
+#define DBGMCU_APB1_FZ_DBG_IWDG_STOP 0x00001000U
+#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT 0x00200000U
+#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT 0x00400000U
+#define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT 0x00800000U
+#define DBGMCU_APB1_FZ_DBG_CAN1_STOP 0x02000000U
+#define DBGMCU_APB1_FZ_DBG_CAN2_STOP 0x04000000U
+/* Old IWDGSTOP bit definition, maintained for legacy purpose */
+#define DBGMCU_APB1_FZ_DBG_IWDEG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP
+
+/******************** Bit definition for DBGMCU_APB2_FZ register ************/
+#define DBGMCU_APB2_FZ_DBG_TIM1_STOP 0x00000001U
+#define DBGMCU_APB2_FZ_DBG_TIM8_STOP 0x00000002U
+#define DBGMCU_APB2_FZ_DBG_TIM9_STOP 0x00010000U
+#define DBGMCU_APB2_FZ_DBG_TIM10_STOP 0x00020000U
+#define DBGMCU_APB2_FZ_DBG_TIM11_STOP 0x00040000U
+
+/******************************************************************************/
+/* */
+/* Ethernet MAC Registers bits definitions */
+/* */
+/******************************************************************************/
+/* Bit definition for Ethernet MAC Control Register register */
+#define ETH_MACCR_WD 0x00800000U /* Watchdog disable */
+#define ETH_MACCR_JD 0x00400000U /* Jabber disable */
+#define ETH_MACCR_IFG 0x000E0000U /* Inter-frame gap */
+#define ETH_MACCR_IFG_96Bit 0x00000000U /* Minimum IFG between frames during transmission is 96Bit */
+ #define ETH_MACCR_IFG_88Bit 0x00020000U /* Minimum IFG between frames during transmission is 88Bit */
+ #define ETH_MACCR_IFG_80Bit 0x00040000U /* Minimum IFG between frames during transmission is 80Bit */
+ #define ETH_MACCR_IFG_72Bit 0x00060000U /* Minimum IFG between frames during transmission is 72Bit */
+ #define ETH_MACCR_IFG_64Bit 0x00080000U /* Minimum IFG between frames during transmission is 64Bit */
+ #define ETH_MACCR_IFG_56Bit 0x000A0000U /* Minimum IFG between frames during transmission is 56Bit */
+ #define ETH_MACCR_IFG_48Bit 0x000C0000U /* Minimum IFG between frames during transmission is 48Bit */
+ #define ETH_MACCR_IFG_40Bit 0x000E0000U /* Minimum IFG between frames during transmission is 40Bit */
+#define ETH_MACCR_CSD 0x00010000U /* Carrier sense disable (during transmission) */
+#define ETH_MACCR_FES 0x00004000U /* Fast ethernet speed */
+#define ETH_MACCR_ROD 0x00002000U /* Receive own disable */
+#define ETH_MACCR_LM 0x00001000U /* loopback mode */
+#define ETH_MACCR_DM 0x00000800U /* Duplex mode */
+#define ETH_MACCR_IPCO 0x00000400U /* IP Checksum offload */
+#define ETH_MACCR_RD 0x00000200U /* Retry disable */
+#define ETH_MACCR_APCS 0x00000080U /* Automatic Pad/CRC stripping */
+#define ETH_MACCR_BL 0x00000060U /* Back-off limit: random integer number (r) of slot time delays before rescheduling
+ a transmission attempt during retries after a collision: 0 =< r <2^k */
+ #define ETH_MACCR_BL_10 0x00000000U /* k = min (n, 10) */
+ #define ETH_MACCR_BL_8 0x00000020U /* k = min (n, 8) */
+ #define ETH_MACCR_BL_4 0x00000040U /* k = min (n, 4) */
+ #define ETH_MACCR_BL_1 0x00000060U /* k = min (n, 1) */
+#define ETH_MACCR_DC 0x00000010U /* Defferal check */
+#define ETH_MACCR_TE 0x00000008U /* Transmitter enable */
+#define ETH_MACCR_RE 0x00000004U /* Receiver enable */
+
+/* Bit definition for Ethernet MAC Frame Filter Register */
+#define ETH_MACFFR_RA 0x80000000U /* Receive all */
+#define ETH_MACFFR_HPF 0x00000400U /* Hash or perfect filter */
+#define ETH_MACFFR_SAF 0x00000200U /* Source address filter enable */
+#define ETH_MACFFR_SAIF 0x00000100U /* SA inverse filtering */
+#define ETH_MACFFR_PCF 0x000000C0U /* Pass control frames: 3 cases */
+ #define ETH_MACFFR_PCF_BlockAll 0x00000040U /* MAC filters all control frames from reaching the application */
+ #define ETH_MACFFR_PCF_ForwardAll 0x00000080U /* MAC forwards all control frames to application even if they fail the Address Filter */
+ #define ETH_MACFFR_PCF_ForwardPassedAddrFilter 0x000000C0U /* MAC forwards control frames that pass the Address Filter. */
+#define ETH_MACFFR_BFD 0x00000020U /* Broadcast frame disable */
+#define ETH_MACFFR_PAM 0x00000010U /* Pass all mutlicast */
+#define ETH_MACFFR_DAIF 0x00000008U /* DA Inverse filtering */
+#define ETH_MACFFR_HM 0x00000004U /* Hash multicast */
+#define ETH_MACFFR_HU 0x00000002U /* Hash unicast */
+#define ETH_MACFFR_PM 0x00000001U /* Promiscuous mode */
+
+/* Bit definition for Ethernet MAC Hash Table High Register */
+#define ETH_MACHTHR_HTH 0xFFFFFFFFU /* Hash table high */
+
+/* Bit definition for Ethernet MAC Hash Table Low Register */
+#define ETH_MACHTLR_HTL 0xFFFFFFFFU /* Hash table low */
+
+/* Bit definition for Ethernet MAC MII Address Register */
+#define ETH_MACMIIAR_PA 0x0000F800U /* Physical layer address */
+#define ETH_MACMIIAR_MR 0x000007C0U /* MII register in the selected PHY */
+#define ETH_MACMIIAR_CR 0x0000001CU /* CR clock range: 6 cases */
+ #define ETH_MACMIIAR_CR_Div42 0x00000000U /* HCLK:60-100 MHz; MDC clock= HCLK/42 */
+ #define ETH_MACMIIAR_CR_Div62 0x00000004U /* HCLK:100-150 MHz; MDC clock= HCLK/62 */
+ #define ETH_MACMIIAR_CR_Div16 0x00000008U /* HCLK:20-35 MHz; MDC clock= HCLK/16 */
+ #define ETH_MACMIIAR_CR_Div26 0x0000000CU /* HCLK:35-60 MHz; MDC clock= HCLK/26 */
+ #define ETH_MACMIIAR_CR_Div102 0x00000010U /* HCLK:150-168 MHz; MDC clock= HCLK/102 */
+#define ETH_MACMIIAR_MW 0x00000002U /* MII write */
+#define ETH_MACMIIAR_MB 0x00000001U /* MII busy */
+
+/* Bit definition for Ethernet MAC MII Data Register */
+#define ETH_MACMIIDR_MD 0x0000FFFFU /* MII data: read/write data from/to PHY */
+
+/* Bit definition for Ethernet MAC Flow Control Register */
+#define ETH_MACFCR_PT 0xFFFF0000U /* Pause time */
+#define ETH_MACFCR_ZQPD 0x00000080U /* Zero-quanta pause disable */
+#define ETH_MACFCR_PLT 0x00000030U /* Pause low threshold: 4 cases */
+ #define ETH_MACFCR_PLT_Minus4 0x00000000U /* Pause time minus 4 slot times */
+ #define ETH_MACFCR_PLT_Minus28 0x00000010U /* Pause time minus 28 slot times */
+ #define ETH_MACFCR_PLT_Minus144 0x00000020U /* Pause time minus 144 slot times */
+ #define ETH_MACFCR_PLT_Minus256 0x00000030U /* Pause time minus 256 slot times */
+#define ETH_MACFCR_UPFD 0x00000008U /* Unicast pause frame detect */
+#define ETH_MACFCR_RFCE 0x00000004U /* Receive flow control enable */
+#define ETH_MACFCR_TFCE 0x00000002U /* Transmit flow control enable */
+#define ETH_MACFCR_FCBBPA 0x00000001U /* Flow control busy/backpressure activate */
+
+/* Bit definition for Ethernet MAC VLAN Tag Register */
+#define ETH_MACVLANTR_VLANTC 0x00010000U /* 12-bit VLAN tag comparison */
+#define ETH_MACVLANTR_VLANTI 0x0000FFFFU /* VLAN tag identifier (for receive frames) */
+
+/* Bit definition for Ethernet MAC Remote Wake-UpFrame Filter Register */
+#define ETH_MACRWUFFR_D 0xFFFFFFFFU /* Wake-up frame filter register data */
+/* Eight sequential Writes to this address (offset 0x28) will write all Wake-UpFrame Filter Registers.
+ Eight sequential Reads from this address (offset 0x28) will read all Wake-UpFrame Filter Registers. */
+/* Wake-UpFrame Filter Reg0 : Filter 0 Byte Mask
+ Wake-UpFrame Filter Reg1 : Filter 1 Byte Mask
+ Wake-UpFrame Filter Reg2 : Filter 2 Byte Mask
+ Wake-UpFrame Filter Reg3 : Filter 3 Byte Mask
+ Wake-UpFrame Filter Reg4 : RSVD - Filter3 Command - RSVD - Filter2 Command -
+ RSVD - Filter1 Command - RSVD - Filter0 Command
+ Wake-UpFrame Filter Re5 : Filter3 Offset - Filter2 Offset - Filter1 Offset - Filter0 Offset
+ Wake-UpFrame Filter Re6 : Filter1 CRC16 - Filter0 CRC16
+ Wake-UpFrame Filter Re7 : Filter3 CRC16 - Filter2 CRC16 */
+
+/* Bit definition for Ethernet MAC PMT Control and Status Register */
+#define ETH_MACPMTCSR_WFFRPR 0x80000000U /* Wake-Up Frame Filter Register Pointer Reset */
+#define ETH_MACPMTCSR_GU 0x00000200U /* Global Unicast */
+#define ETH_MACPMTCSR_WFR 0x00000040U /* Wake-Up Frame Received */
+#define ETH_MACPMTCSR_MPR 0x00000020U /* Magic Packet Received */
+#define ETH_MACPMTCSR_WFE 0x00000004U /* Wake-Up Frame Enable */
+#define ETH_MACPMTCSR_MPE 0x00000002U /* Magic Packet Enable */
+#define ETH_MACPMTCSR_PD 0x00000001U /* Power Down */
+
+/* Bit definition for Ethernet MAC Status Register */
+#define ETH_MACSR_TSTS 0x00000200U /* Time stamp trigger status */
+#define ETH_MACSR_MMCTS 0x00000040U /* MMC transmit status */
+#define ETH_MACSR_MMMCRS 0x00000020U /* MMC receive status */
+#define ETH_MACSR_MMCS 0x00000010U /* MMC status */
+#define ETH_MACSR_PMTS 0x00000008U /* PMT status */
+
+/* Bit definition for Ethernet MAC Interrupt Mask Register */
+#define ETH_MACIMR_TSTIM 0x00000200U /* Time stamp trigger interrupt mask */
+#define ETH_MACIMR_PMTIM 0x00000008U /* PMT interrupt mask */
+
+/* Bit definition for Ethernet MAC Address0 High Register */
+#define ETH_MACA0HR_MACA0H 0x0000FFFFU /* MAC address0 high */
+
+/* Bit definition for Ethernet MAC Address0 Low Register */
+#define ETH_MACA0LR_MACA0L 0xFFFFFFFFU /* MAC address0 low */
+
+/* Bit definition for Ethernet MAC Address1 High Register */
+#define ETH_MACA1HR_AE 0x80000000U /* Address enable */
+#define ETH_MACA1HR_SA 0x40000000U /* Source address */
+#define ETH_MACA1HR_MBC 0x3F000000U /* Mask byte control: bits to mask for comparison of the MAC Address bytes */
+ #define ETH_MACA1HR_MBC_HBits15_8 0x20000000U /* Mask MAC Address high reg bits [15:8] */
+ #define ETH_MACA1HR_MBC_HBits7_0 0x10000000U /* Mask MAC Address high reg bits [7:0] */
+ #define ETH_MACA1HR_MBC_LBits31_24 0x08000000U /* Mask MAC Address low reg bits [31:24] */
+ #define ETH_MACA1HR_MBC_LBits23_16 0x04000000U /* Mask MAC Address low reg bits [23:16] */
+ #define ETH_MACA1HR_MBC_LBits15_8 0x02000000U /* Mask MAC Address low reg bits [15:8] */
+ #define ETH_MACA1HR_MBC_LBits7_0 0x01000000U /* Mask MAC Address low reg bits [7:0] */
+#define ETH_MACA1HR_MACA1H 0x0000FFFFU /* MAC address1 high */
+
+/* Bit definition for Ethernet MAC Address1 Low Register */
+#define ETH_MACA1LR_MACA1L 0xFFFFFFFFU /* MAC address1 low */
+
+/* Bit definition for Ethernet MAC Address2 High Register */
+#define ETH_MACA2HR_AE 0x80000000U /* Address enable */
+#define ETH_MACA2HR_SA 0x40000000U /* Source address */
+#define ETH_MACA2HR_MBC 0x3F000000U /* Mask byte control */
+ #define ETH_MACA2HR_MBC_HBits15_8 0x20000000U /* Mask MAC Address high reg bits [15:8] */
+ #define ETH_MACA2HR_MBC_HBits7_0 0x10000000U /* Mask MAC Address high reg bits [7:0] */
+ #define ETH_MACA2HR_MBC_LBits31_24 0x08000000U /* Mask MAC Address low reg bits [31:24] */
+ #define ETH_MACA2HR_MBC_LBits23_16 0x04000000U /* Mask MAC Address low reg bits [23:16] */
+ #define ETH_MACA2HR_MBC_LBits15_8 0x02000000U /* Mask MAC Address low reg bits [15:8] */
+ #define ETH_MACA2HR_MBC_LBits7_0 0x01000000U /* Mask MAC Address low reg bits [70] */
+#define ETH_MACA2HR_MACA2H 0x0000FFFFU /* MAC address1 high */
+
+/* Bit definition for Ethernet MAC Address2 Low Register */
+#define ETH_MACA2LR_MACA2L 0xFFFFFFFFU /* MAC address2 low */
+
+/* Bit definition for Ethernet MAC Address3 High Register */
+#define ETH_MACA3HR_AE 0x80000000U /* Address enable */
+#define ETH_MACA3HR_SA 0x40000000U /* Source address */
+#define ETH_MACA3HR_MBC 0x3F000000U /* Mask byte control */
+ #define ETH_MACA3HR_MBC_HBits15_8 0x20000000U /* Mask MAC Address high reg bits [15:8] */
+ #define ETH_MACA3HR_MBC_HBits7_0 0x10000000U /* Mask MAC Address high reg bits [7:0] */
+ #define ETH_MACA3HR_MBC_LBits31_24 0x08000000U /* Mask MAC Address low reg bits [31:24] */
+ #define ETH_MACA3HR_MBC_LBits23_16 0x04000000U /* Mask MAC Address low reg bits [23:16] */
+ #define ETH_MACA3HR_MBC_LBits15_8 0x02000000U /* Mask MAC Address low reg bits [15:8] */
+ #define ETH_MACA3HR_MBC_LBits7_0 0x01000000U /* Mask MAC Address low reg bits [70] */
+#define ETH_MACA3HR_MACA3H 0x0000FFFFU /* MAC address3 high */
+
+/* Bit definition for Ethernet MAC Address3 Low Register */
+#define ETH_MACA3LR_MACA3L 0xFFFFFFFFU /* MAC address3 low */
+
+/******************************************************************************/
+/* Ethernet MMC Registers bits definition */
+/******************************************************************************/
+
+/* Bit definition for Ethernet MMC Contol Register */
+#define ETH_MMCCR_MCFHP 0x00000020U /* MMC counter Full-Half preset */
+#define ETH_MMCCR_MCP 0x00000010U /* MMC counter preset */
+#define ETH_MMCCR_MCF 0x00000008U /* MMC Counter Freeze */
+#define ETH_MMCCR_ROR 0x00000004U /* Reset on Read */
+#define ETH_MMCCR_CSR 0x00000002U /* Counter Stop Rollover */
+#define ETH_MMCCR_CR 0x00000001U /* Counters Reset */
+
+/* Bit definition for Ethernet MMC Receive Interrupt Register */
+#define ETH_MMCRIR_RGUFS 0x00020000U /* Set when Rx good unicast frames counter reaches half the maximum value */
+#define ETH_MMCRIR_RFAES 0x00000040U /* Set when Rx alignment error counter reaches half the maximum value */
+#define ETH_MMCRIR_RFCES 0x00000020U /* Set when Rx crc error counter reaches half the maximum value */
+
+/* Bit definition for Ethernet MMC Transmit Interrupt Register */
+#define ETH_MMCTIR_TGFS 0x00200000U /* Set when Tx good frame count counter reaches half the maximum value */
+#define ETH_MMCTIR_TGFMSCS 0x00008000U /* Set when Tx good multi col counter reaches half the maximum value */
+#define ETH_MMCTIR_TGFSCS 0x00004000U /* Set when Tx good single col counter reaches half the maximum value */
+
+/* Bit definition for Ethernet MMC Receive Interrupt Mask Register */
+#define ETH_MMCRIMR_RGUFM 0x00020000U /* Mask the interrupt when Rx good unicast frames counter reaches half the maximum value */
+#define ETH_MMCRIMR_RFAEM 0x00000040U /* Mask the interrupt when when Rx alignment error counter reaches half the maximum value */
+#define ETH_MMCRIMR_RFCEM 0x00000020U /* Mask the interrupt when Rx crc error counter reaches half the maximum value */
+
+/* Bit definition for Ethernet MMC Transmit Interrupt Mask Register */
+#define ETH_MMCTIMR_TGFM 0x00200000U /* Mask the interrupt when Tx good frame count counter reaches half the maximum value */
+#define ETH_MMCTIMR_TGFMSCM 0x00008000U /* Mask the interrupt when Tx good multi col counter reaches half the maximum value */
+#define ETH_MMCTIMR_TGFSCM 0x00004000U /* Mask the interrupt when Tx good single col counter reaches half the maximum value */
+
+/* Bit definition for Ethernet MMC Transmitted Good Frames after Single Collision Counter Register */
+#define ETH_MMCTGFSCCR_TGFSCC 0xFFFFFFFFU /* Number of successfully transmitted frames after a single collision in Half-duplex mode. */
+
+/* Bit definition for Ethernet MMC Transmitted Good Frames after More than a Single Collision Counter Register */
+#define ETH_MMCTGFMSCCR_TGFMSCC 0xFFFFFFFFU /* Number of successfully transmitted frames after more than a single collision in Half-duplex mode. */
+
+/* Bit definition for Ethernet MMC Transmitted Good Frames Counter Register */
+#define ETH_MMCTGFCR_TGFC 0xFFFFFFFFU /* Number of good frames transmitted. */
+
+/* Bit definition for Ethernet MMC Received Frames with CRC Error Counter Register */
+#define ETH_MMCRFCECR_RFCEC 0xFFFFFFFFU /* Number of frames received with CRC error. */
+
+/* Bit definition for Ethernet MMC Received Frames with Alignement Error Counter Register */
+#define ETH_MMCRFAECR_RFAEC 0xFFFFFFFFU /* Number of frames received with alignment (dribble) error */
+
+/* Bit definition for Ethernet MMC Received Good Unicast Frames Counter Register */
+#define ETH_MMCRGUFCR_RGUFC 0xFFFFFFFFU /* Number of good unicast frames received. */
+
+/******************************************************************************/
+/* Ethernet PTP Registers bits definition */
+/******************************************************************************/
+
+/* Bit definition for Ethernet PTP Time Stamp Contol Register */
+#define ETH_PTPTSCR_TSCNT 0x00030000U /* Time stamp clock node type */
+#define ETH_PTPTSSR_TSSMRME 0x00008000U /* Time stamp snapshot for message relevant to master enable */
+#define ETH_PTPTSSR_TSSEME 0x00004000U /* Time stamp snapshot for event message enable */
+#define ETH_PTPTSSR_TSSIPV4FE 0x00002000U /* Time stamp snapshot for IPv4 frames enable */
+#define ETH_PTPTSSR_TSSIPV6FE 0x00001000U /* Time stamp snapshot for IPv6 frames enable */
+#define ETH_PTPTSSR_TSSPTPOEFE 0x00000800U /* Time stamp snapshot for PTP over ethernet frames enable */
+#define ETH_PTPTSSR_TSPTPPSV2E 0x00000400U /* Time stamp PTP packet snooping for version2 format enable */
+#define ETH_PTPTSSR_TSSSR 0x00000200U /* Time stamp Sub-seconds rollover */
+#define ETH_PTPTSSR_TSSARFE 0x00000100U /* Time stamp snapshot for all received frames enable */
+
+#define ETH_PTPTSCR_TSARU 0x00000020U /* Addend register update */
+#define ETH_PTPTSCR_TSITE 0x00000010U /* Time stamp interrupt trigger enable */
+#define ETH_PTPTSCR_TSSTU 0x00000008U /* Time stamp update */
+#define ETH_PTPTSCR_TSSTI 0x00000004U /* Time stamp initialize */
+#define ETH_PTPTSCR_TSFCU 0x00000002U /* Time stamp fine or coarse update */
+#define ETH_PTPTSCR_TSE 0x00000001U /* Time stamp enable */
+
+/* Bit definition for Ethernet PTP Sub-Second Increment Register */
+#define ETH_PTPSSIR_STSSI 0x000000FFU /* System time Sub-second increment value */
+
+/* Bit definition for Ethernet PTP Time Stamp High Register */
+#define ETH_PTPTSHR_STS 0xFFFFFFFFU /* System Time second */
+
+/* Bit definition for Ethernet PTP Time Stamp Low Register */
+#define ETH_PTPTSLR_STPNS 0x80000000U /* System Time Positive or negative time */
+#define ETH_PTPTSLR_STSS 0x7FFFFFFFU /* System Time sub-seconds */
+
+/* Bit definition for Ethernet PTP Time Stamp High Update Register */
+#define ETH_PTPTSHUR_TSUS 0xFFFFFFFFU /* Time stamp update seconds */
+
+/* Bit definition for Ethernet PTP Time Stamp Low Update Register */
+#define ETH_PTPTSLUR_TSUPNS 0x80000000U /* Time stamp update Positive or negative time */
+#define ETH_PTPTSLUR_TSUSS 0x7FFFFFFFU /* Time stamp update sub-seconds */
+
+/* Bit definition for Ethernet PTP Time Stamp Addend Register */
+#define ETH_PTPTSAR_TSA 0xFFFFFFFFU /* Time stamp addend */
+
+/* Bit definition for Ethernet PTP Target Time High Register */
+#define ETH_PTPTTHR_TTSH 0xFFFFFFFFU /* Target time stamp high */
+
+/* Bit definition for Ethernet PTP Target Time Low Register */
+#define ETH_PTPTTLR_TTSL 0xFFFFFFFFU /* Target time stamp low */
+
+/* Bit definition for Ethernet PTP Time Stamp Status Register */
+#define ETH_PTPTSSR_TSTTR 0x00000020U /* Time stamp target time reached */
+#define ETH_PTPTSSR_TSSO 0x00000010U /* Time stamp seconds overflow */
+
+/******************************************************************************/
+/* Ethernet DMA Registers bits definition */
+/******************************************************************************/
+
+/* Bit definition for Ethernet DMA Bus Mode Register */
+#define ETH_DMABMR_AAB 0x02000000U /* Address-Aligned beats */
+#define ETH_DMABMR_FPM 0x01000000U /* 4xPBL mode */
+#define ETH_DMABMR_USP 0x00800000U /* Use separate PBL */
+#define ETH_DMABMR_RDP 0x007E0000U /* RxDMA PBL */
+ #define ETH_DMABMR_RDP_1Beat 0x00020000U /* maximum number of beats to be transferred in one RxDMA transaction is 1 */
+ #define ETH_DMABMR_RDP_2Beat 0x00040000U /* maximum number of beats to be transferred in one RxDMA transaction is 2 */
+ #define ETH_DMABMR_RDP_4Beat 0x00080000U /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
+ #define ETH_DMABMR_RDP_8Beat 0x00100000U /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
+ #define ETH_DMABMR_RDP_16Beat 0x00200000U /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
+ #define ETH_DMABMR_RDP_32Beat 0x00400000U /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
+ #define ETH_DMABMR_RDP_4xPBL_4Beat 0x01020000U /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
+ #define ETH_DMABMR_RDP_4xPBL_8Beat 0x01040000U /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
+ #define ETH_DMABMR_RDP_4xPBL_16Beat 0x01080000U /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
+ #define ETH_DMABMR_RDP_4xPBL_32Beat 0x01100000U /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
+ #define ETH_DMABMR_RDP_4xPBL_64Beat 0x01200000U /* maximum number of beats to be transferred in one RxDMA transaction is 64 */
+ #define ETH_DMABMR_RDP_4xPBL_128Beat 0x01400000U /* maximum number of beats to be transferred in one RxDMA transaction is 128 */
+#define ETH_DMABMR_FB 0x00010000U /* Fixed Burst */
+#define ETH_DMABMR_RTPR 0x0000C000U /* Rx Tx priority ratio */
+ #define ETH_DMABMR_RTPR_1_1 0x00000000U /* Rx Tx priority ratio */
+ #define ETH_DMABMR_RTPR_2_1 0x00004000U /* Rx Tx priority ratio */
+ #define ETH_DMABMR_RTPR_3_1 0x00008000U /* Rx Tx priority ratio */
+ #define ETH_DMABMR_RTPR_4_1 0x0000C000U /* Rx Tx priority ratio */
+#define ETH_DMABMR_PBL 0x00003F00U /* Programmable burst length */
+ #define ETH_DMABMR_PBL_1Beat 0x00000100U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */
+ #define ETH_DMABMR_PBL_2Beat 0x00000200U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */
+ #define ETH_DMABMR_PBL_4Beat 0x00000400U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
+ #define ETH_DMABMR_PBL_8Beat 0x00000800U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
+ #define ETH_DMABMR_PBL_16Beat 0x00001000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
+ #define ETH_DMABMR_PBL_32Beat 0x00002000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
+ #define ETH_DMABMR_PBL_4xPBL_4Beat 0x01000100U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
+ #define ETH_DMABMR_PBL_4xPBL_8Beat 0x01000200U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
+ #define ETH_DMABMR_PBL_4xPBL_16Beat 0x01000400U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
+ #define ETH_DMABMR_PBL_4xPBL_32Beat 0x01000800U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
+ #define ETH_DMABMR_PBL_4xPBL_64Beat 0x01001000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */
+ #define ETH_DMABMR_PBL_4xPBL_128Beat 0x01002000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */
+#define ETH_DMABMR_EDE 0x00000080U /* Enhanced Descriptor Enable */
+#define ETH_DMABMR_DSL 0x0000007CU /* Descriptor Skip Length */
+#define ETH_DMABMR_DA 0x00000002U /* DMA arbitration scheme */
+#define ETH_DMABMR_SR 0x00000001U /* Software reset */
+
+/* Bit definition for Ethernet DMA Transmit Poll Demand Register */
+#define ETH_DMATPDR_TPD 0xFFFFFFFFU /* Transmit poll demand */
+
+/* Bit definition for Ethernet DMA Receive Poll Demand Register */
+#define ETH_DMARPDR_RPD 0xFFFFFFFFU /* Receive poll demand */
+
+/* Bit definition for Ethernet DMA Receive Descriptor List Address Register */
+#define ETH_DMARDLAR_SRL 0xFFFFFFFFU /* Start of receive list */
+
+/* Bit definition for Ethernet DMA Transmit Descriptor List Address Register */
+#define ETH_DMATDLAR_STL 0xFFFFFFFFU /* Start of transmit list */
+
+/* Bit definition for Ethernet DMA Status Register */
+#define ETH_DMASR_TSTS 0x20000000U /* Time-stamp trigger status */
+#define ETH_DMASR_PMTS 0x10000000U /* PMT status */
+#define ETH_DMASR_MMCS 0x08000000U /* MMC status */
+#define ETH_DMASR_EBS 0x03800000U /* Error bits status */
+ /* combination with EBS[2:0] for GetFlagStatus function */
+ #define ETH_DMASR_EBS_DescAccess 0x02000000U /* Error bits 0-data buffer, 1-desc. access */
+ #define ETH_DMASR_EBS_ReadTransf 0x01000000U /* Error bits 0-write trnsf, 1-read transfr */
+ #define ETH_DMASR_EBS_DataTransfTx 0x00800000U /* Error bits 0-Rx DMA, 1-Tx DMA */
+#define ETH_DMASR_TPS 0x00700000U /* Transmit process state */
+ #define ETH_DMASR_TPS_Stopped 0x00000000U /* Stopped - Reset or Stop Tx Command issued */
+ #define ETH_DMASR_TPS_Fetching 0x00100000U /* Running - fetching the Tx descriptor */
+ #define ETH_DMASR_TPS_Waiting 0x00200000U /* Running - waiting for status */
+ #define ETH_DMASR_TPS_Reading 0x00300000U /* Running - reading the data from host memory */
+ #define ETH_DMASR_TPS_Suspended 0x00600000U /* Suspended - Tx Descriptor unavailabe */
+ #define ETH_DMASR_TPS_Closing 0x00700000U /* Running - closing Rx descriptor */
+#define ETH_DMASR_RPS 0x000E0000U /* Receive process state */
+ #define ETH_DMASR_RPS_Stopped 0x00000000U /* Stopped - Reset or Stop Rx Command issued */
+ #define ETH_DMASR_RPS_Fetching 0x00020000U /* Running - fetching the Rx descriptor */
+ #define ETH_DMASR_RPS_Waiting 0x00060000U /* Running - waiting for packet */
+ #define ETH_DMASR_RPS_Suspended 0x00080000U /* Suspended - Rx Descriptor unavailable */
+ #define ETH_DMASR_RPS_Closing 0x000A0000U /* Running - closing descriptor */
+ #define ETH_DMASR_RPS_Queuing 0x000E0000U /* Running - queuing the recieve frame into host memory */
+#define ETH_DMASR_NIS 0x00010000U /* Normal interrupt summary */
+#define ETH_DMASR_AIS 0x00008000U /* Abnormal interrupt summary */
+#define ETH_DMASR_ERS 0x00004000U /* Early receive status */
+#define ETH_DMASR_FBES 0x00002000U /* Fatal bus error status */
+#define ETH_DMASR_ETS 0x00000400U /* Early transmit status */
+#define ETH_DMASR_RWTS 0x00000200U /* Receive watchdog timeout status */
+#define ETH_DMASR_RPSS 0x00000100U /* Receive process stopped status */
+#define ETH_DMASR_RBUS 0x00000080U /* Receive buffer unavailable status */
+#define ETH_DMASR_RS 0x00000040U /* Receive status */
+#define ETH_DMASR_TUS 0x00000020U /* Transmit underflow status */
+#define ETH_DMASR_ROS 0x00000010U /* Receive overflow status */
+#define ETH_DMASR_TJTS 0x00000008U /* Transmit jabber timeout status */
+#define ETH_DMASR_TBUS 0x00000004U /* Transmit buffer unavailable status */
+#define ETH_DMASR_TPSS 0x00000002U /* Transmit process stopped status */
+#define ETH_DMASR_TS 0x00000001U /* Transmit status */
+
+/* Bit definition for Ethernet DMA Operation Mode Register */
+#define ETH_DMAOMR_DTCEFD 0x04000000U /* Disable Dropping of TCP/IP checksum error frames */
+#define ETH_DMAOMR_RSF 0x02000000U /* Receive store and forward */
+#define ETH_DMAOMR_DFRF 0x01000000U /* Disable flushing of received frames */
+#define ETH_DMAOMR_TSF 0x00200000U /* Transmit store and forward */
+#define ETH_DMAOMR_FTF 0x00100000U /* Flush transmit FIFO */
+#define ETH_DMAOMR_TTC 0x0001C000U /* Transmit threshold control */
+ #define ETH_DMAOMR_TTC_64Bytes 0x00000000U /* threshold level of the MTL Transmit FIFO is 64 Bytes */
+ #define ETH_DMAOMR_TTC_128Bytes 0x00004000U /* threshold level of the MTL Transmit FIFO is 128 Bytes */
+ #define ETH_DMAOMR_TTC_192Bytes 0x00008000U /* threshold level of the MTL Transmit FIFO is 192 Bytes */
+ #define ETH_DMAOMR_TTC_256Bytes 0x0000C000U /* threshold level of the MTL Transmit FIFO is 256 Bytes */
+ #define ETH_DMAOMR_TTC_40Bytes 0x00010000U /* threshold level of the MTL Transmit FIFO is 40 Bytes */
+ #define ETH_DMAOMR_TTC_32Bytes 0x00014000U /* threshold level of the MTL Transmit FIFO is 32 Bytes */
+ #define ETH_DMAOMR_TTC_24Bytes 0x00018000U /* threshold level of the MTL Transmit FIFO is 24 Bytes */
+ #define ETH_DMAOMR_TTC_16Bytes 0x0001C000U /* threshold level of the MTL Transmit FIFO is 16 Bytes */
+#define ETH_DMAOMR_ST 0x00002000U /* Start/stop transmission command */
+#define ETH_DMAOMR_FEF 0x00000080U /* Forward error frames */
+#define ETH_DMAOMR_FUGF 0x00000040U /* Forward undersized good frames */
+#define ETH_DMAOMR_RTC 0x00000018U /* receive threshold control */
+ #define ETH_DMAOMR_RTC_64Bytes 0x00000000U /* threshold level of the MTL Receive FIFO is 64 Bytes */
+ #define ETH_DMAOMR_RTC_32Bytes 0x00000008U /* threshold level of the MTL Receive FIFO is 32 Bytes */
+ #define ETH_DMAOMR_RTC_96Bytes 0x00000010U /* threshold level of the MTL Receive FIFO is 96 Bytes */
+ #define ETH_DMAOMR_RTC_128Bytes 0x00000018U /* threshold level of the MTL Receive FIFO is 128 Bytes */
+#define ETH_DMAOMR_OSF 0x00000004U /* operate on second frame */
+#define ETH_DMAOMR_SR 0x00000002U /* Start/stop receive */
+
+/* Bit definition for Ethernet DMA Interrupt Enable Register */
+#define ETH_DMAIER_NISE 0x00010000U /* Normal interrupt summary enable */
+#define ETH_DMAIER_AISE 0x00008000U /* Abnormal interrupt summary enable */
+#define ETH_DMAIER_ERIE 0x00004000U /* Early receive interrupt enable */
+#define ETH_DMAIER_FBEIE 0x00002000U /* Fatal bus error interrupt enable */
+#define ETH_DMAIER_ETIE 0x00000400U /* Early transmit interrupt enable */
+#define ETH_DMAIER_RWTIE 0x00000200U /* Receive watchdog timeout interrupt enable */
+#define ETH_DMAIER_RPSIE 0x00000100U /* Receive process stopped interrupt enable */
+#define ETH_DMAIER_RBUIE 0x00000080U /* Receive buffer unavailable interrupt enable */
+#define ETH_DMAIER_RIE 0x00000040U /* Receive interrupt enable */
+#define ETH_DMAIER_TUIE 0x00000020U /* Transmit Underflow interrupt enable */
+#define ETH_DMAIER_ROIE 0x00000010U /* Receive Overflow interrupt enable */
+#define ETH_DMAIER_TJTIE 0x00000008U /* Transmit jabber timeout interrupt enable */
+#define ETH_DMAIER_TBUIE 0x00000004U /* Transmit buffer unavailable interrupt enable */
+#define ETH_DMAIER_TPSIE 0x00000002U /* Transmit process stopped interrupt enable */
+#define ETH_DMAIER_TIE 0x00000001U /* Transmit interrupt enable */
+
+/* Bit definition for Ethernet DMA Missed Frame and Buffer Overflow Counter Register */
+#define ETH_DMAMFBOCR_OFOC 0x10000000U /* Overflow bit for FIFO overflow counter */
+#define ETH_DMAMFBOCR_MFA 0x0FFE0000U /* Number of frames missed by the application */
+#define ETH_DMAMFBOCR_OMFC 0x00010000U /* Overflow bit for missed frame counter */
+#define ETH_DMAMFBOCR_MFC 0x0000FFFFU /* Number of frames missed by the controller */
+
+/* Bit definition for Ethernet DMA Current Host Transmit Descriptor Register */
+#define ETH_DMACHTDR_HTDAP 0xFFFFFFFFU /* Host transmit descriptor address pointer */
+
+/* Bit definition for Ethernet DMA Current Host Receive Descriptor Register */
+#define ETH_DMACHRDR_HRDAP 0xFFFFFFFFU /* Host receive descriptor address pointer */
+
+/* Bit definition for Ethernet DMA Current Host Transmit Buffer Address Register */
+#define ETH_DMACHTBAR_HTBAP 0xFFFFFFFFU /* Host transmit buffer address pointer */
+
+/* Bit definition for Ethernet DMA Current Host Receive Buffer Address Register */
+#define ETH_DMACHRBAR_HRBAP 0xFFFFFFFFU /* Host receive buffer address pointer */
+
+/******************************************************************************/
+/* */
+/* USB_OTG */
+/* */
+/******************************************************************************/
+/******************** Bit definition forUSB_OTG_GOTGCTL register ********************/
+#define USB_OTG_GOTGCTL_SRQSCS 0x00000001U /*!< Session request success */
+#define USB_OTG_GOTGCTL_SRQ 0x00000002U /*!< Session request */
+#define USB_OTG_GOTGCTL_HNGSCS 0x00000100U /*!< Host negotiation success */
+#define USB_OTG_GOTGCTL_HNPRQ 0x00000200U /*!< HNP request */
+#define USB_OTG_GOTGCTL_HSHNPEN 0x00000400U /*!< Host set HNP enable */
+#define USB_OTG_GOTGCTL_DHNPEN 0x00000800U /*!< Device HNP enabled */
+#define USB_OTG_GOTGCTL_CIDSTS 0x00010000U /*!< Connector ID status */
+#define USB_OTG_GOTGCTL_DBCT 0x00020000U /*!< Long/short debounce time */
+#define USB_OTG_GOTGCTL_ASVLD 0x00040000U /*!< A-session valid */
+#define USB_OTG_GOTGCTL_BSVLD 0x00080000U /*!< B-session valid */
+
+/******************** Bit definition forUSB_OTG_HCFG register ********************/
+
+#define USB_OTG_HCFG_FSLSPCS 0x00000003U /*!< FS/LS PHY clock select */
+#define USB_OTG_HCFG_FSLSPCS_0 0x00000001U /*!<Bit 0 */
+#define USB_OTG_HCFG_FSLSPCS_1 0x00000002U /*!<Bit 1 */
+#define USB_OTG_HCFG_FSLSS 0x00000004U /*!< FS- and LS-only support */
+
+/******************** Bit definition forUSB_OTG_DCFG register ********************/
+
+#define USB_OTG_DCFG_DSPD 0x00000003U /*!< Device speed */
+#define USB_OTG_DCFG_DSPD_0 0x00000001U /*!<Bit 0 */
+#define USB_OTG_DCFG_DSPD_1 0x00000002U /*!<Bit 1 */
+#define USB_OTG_DCFG_NZLSOHSK 0x00000004U /*!< Nonzero-length status OUT handshake */
+
+#define USB_OTG_DCFG_DAD 0x000007F0U /*!< Device address */
+#define USB_OTG_DCFG_DAD_0 0x00000010U /*!<Bit 0 */
+#define USB_OTG_DCFG_DAD_1 0x00000020U /*!<Bit 1 */
+#define USB_OTG_DCFG_DAD_2 0x00000040U /*!<Bit 2 */
+#define USB_OTG_DCFG_DAD_3 0x00000080U /*!<Bit 3 */
+#define USB_OTG_DCFG_DAD_4 0x00000100U /*!<Bit 4 */
+#define USB_OTG_DCFG_DAD_5 0x00000200U /*!<Bit 5 */
+#define USB_OTG_DCFG_DAD_6 0x00000400U /*!<Bit 6 */
+
+#define USB_OTG_DCFG_PFIVL 0x00001800U /*!< Periodic (micro)frame interval */
+#define USB_OTG_DCFG_PFIVL_0 0x00000800U /*!<Bit 0 */
+#define USB_OTG_DCFG_PFIVL_1 0x00001000U /*!<Bit 1 */
+
+#define USB_OTG_DCFG_PERSCHIVL 0x03000000U /*!< Periodic scheduling interval */
+#define USB_OTG_DCFG_PERSCHIVL_0 0x01000000U /*!<Bit 0 */
+#define USB_OTG_DCFG_PERSCHIVL_1 0x02000000U /*!<Bit 1 */
+
+/******************** Bit definition forUSB_OTG_PCGCR register ********************/
+#define USB_OTG_PCGCR_STPPCLK 0x00000001U /*!< Stop PHY clock */
+#define USB_OTG_PCGCR_GATEHCLK 0x00000002U /*!< Gate HCLK */
+#define USB_OTG_PCGCR_PHYSUSP 0x00000010U /*!< PHY suspended */
+
+/******************** Bit definition forUSB_OTG_GOTGINT register ********************/
+#define USB_OTG_GOTGINT_SEDET 0x00000004U /*!< Session end detected */
+#define USB_OTG_GOTGINT_SRSSCHG 0x00000100U /*!< Session request success status change */
+#define USB_OTG_GOTGINT_HNSSCHG 0x00000200U /*!< Host negotiation success status change */
+#define USB_OTG_GOTGINT_HNGDET 0x00020000U /*!< Host negotiation detected */
+#define USB_OTG_GOTGINT_ADTOCHG 0x00040000U /*!< A-device timeout change */
+#define USB_OTG_GOTGINT_DBCDNE 0x00080000U /*!< Debounce done */
+
+/******************** Bit definition forUSB_OTG_DCTL register ********************/
+#define USB_OTG_DCTL_RWUSIG 0x00000001U /*!< Remote wakeup signaling */
+#define USB_OTG_DCTL_SDIS 0x00000002U /*!< Soft disconnect */
+#define USB_OTG_DCTL_GINSTS 0x00000004U /*!< Global IN NAK status */
+#define USB_OTG_DCTL_GONSTS 0x00000008U /*!< Global OUT NAK status */
+
+#define USB_OTG_DCTL_TCTL 0x00000070U /*!< Test control */
+#define USB_OTG_DCTL_TCTL_0 0x00000010U /*!<Bit 0 */
+#define USB_OTG_DCTL_TCTL_1 0x00000020U /*!<Bit 1 */
+#define USB_OTG_DCTL_TCTL_2 0x00000040U /*!<Bit 2 */
+#define USB_OTG_DCTL_SGINAK 0x00000080U /*!< Set global IN NAK */
+#define USB_OTG_DCTL_CGINAK 0x00000100U /*!< Clear global IN NAK */
+#define USB_OTG_DCTL_SGONAK 0x00000200U /*!< Set global OUT NAK */
+#define USB_OTG_DCTL_CGONAK 0x00000400U /*!< Clear global OUT NAK */
+#define USB_OTG_DCTL_POPRGDNE 0x00000800U /*!< Power-on programming done */
+
+/******************** Bit definition forUSB_OTG_HFIR register ********************/
+#define USB_OTG_HFIR_FRIVL 0x0000FFFFU /*!< Frame interval */
+
+/******************** Bit definition forUSB_OTG_HFNUM register ********************/
+#define USB_OTG_HFNUM_FRNUM 0x0000FFFFU /*!< Frame number */
+#define USB_OTG_HFNUM_FTREM 0xFFFF0000U /*!< Frame time remaining */
+
+/******************** Bit definition forUSB_OTG_DSTS register ********************/
+#define USB_OTG_DSTS_SUSPSTS 0x00000001U /*!< Suspend status */
+
+#define USB_OTG_DSTS_ENUMSPD 0x00000006U /*!< Enumerated speed */
+#define USB_OTG_DSTS_ENUMSPD_0 0x00000002U /*!<Bit 0 */
+#define USB_OTG_DSTS_ENUMSPD_1 0x00000004U /*!<Bit 1 */
+#define USB_OTG_DSTS_EERR 0x00000008U /*!< Erratic error */
+#define USB_OTG_DSTS_FNSOF 0x003FFF00U /*!< Frame number of the received SOF */
+
+/******************** Bit definition forUSB_OTG_GAHBCFG register ********************/
+#define USB_OTG_GAHBCFG_GINT 0x00000001U /*!< Global interrupt mask */
+
+#define USB_OTG_GAHBCFG_HBSTLEN 0x0000001EU /*!< Burst length/type */
+#define USB_OTG_GAHBCFG_HBSTLEN_0 0x00000002U /*!<Bit 0 */
+#define USB_OTG_GAHBCFG_HBSTLEN_1 0x00000004U /*!<Bit 1 */
+#define USB_OTG_GAHBCFG_HBSTLEN_2 0x00000008U /*!<Bit 2 */
+#define USB_OTG_GAHBCFG_HBSTLEN_3 0x00000010U /*!<Bit 3 */
+#define USB_OTG_GAHBCFG_DMAEN 0x00000020U /*!< DMA enable */
+#define USB_OTG_GAHBCFG_TXFELVL 0x00000080U /*!< TxFIFO empty level */
+#define USB_OTG_GAHBCFG_PTXFELVL 0x00000100U /*!< Periodic TxFIFO empty level */
+
+/******************** Bit definition forUSB_OTG_GUSBCFG register ********************/
+
+#define USB_OTG_GUSBCFG_TOCAL 0x00000007U /*!< FS timeout calibration */
+#define USB_OTG_GUSBCFG_TOCAL_0 0x00000001U /*!<Bit 0 */
+#define USB_OTG_GUSBCFG_TOCAL_1 0x00000002U /*!<Bit 1 */
+#define USB_OTG_GUSBCFG_TOCAL_2 0x00000004U /*!<Bit 2 */
+#define USB_OTG_GUSBCFG_PHYSEL 0x00000040U /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */
+#define USB_OTG_GUSBCFG_SRPCAP 0x00000100U /*!< SRP-capable */
+#define USB_OTG_GUSBCFG_HNPCAP 0x00000200U /*!< HNP-capable */
+
+#define USB_OTG_GUSBCFG_TRDT 0x00003C00U /*!< USB turnaround time */
+#define USB_OTG_GUSBCFG_TRDT_0 0x00000400U /*!<Bit 0 */
+#define USB_OTG_GUSBCFG_TRDT_1 0x00000800U /*!<Bit 1 */
+#define USB_OTG_GUSBCFG_TRDT_2 0x00001000U /*!<Bit 2 */
+#define USB_OTG_GUSBCFG_TRDT_3 0x00002000U /*!<Bit 3 */
+#define USB_OTG_GUSBCFG_PHYLPCS 0x00008000U /*!< PHY Low-power clock select */
+#define USB_OTG_GUSBCFG_ULPIFSLS 0x00020000U /*!< ULPI FS/LS select */
+#define USB_OTG_GUSBCFG_ULPIAR 0x00040000U /*!< ULPI Auto-resume */
+#define USB_OTG_GUSBCFG_ULPICSM 0x00080000U /*!< ULPI Clock SuspendM */
+#define USB_OTG_GUSBCFG_ULPIEVBUSD 0x00100000U /*!< ULPI External VBUS Drive */
+#define USB_OTG_GUSBCFG_ULPIEVBUSI 0x00200000U /*!< ULPI external VBUS indicator */
+#define USB_OTG_GUSBCFG_TSDPS 0x00400000U /*!< TermSel DLine pulsing selection */
+#define USB_OTG_GUSBCFG_PCCI 0x00800000U /*!< Indicator complement */
+#define USB_OTG_GUSBCFG_PTCI 0x01000000U /*!< Indicator pass through */
+#define USB_OTG_GUSBCFG_ULPIIPD 0x02000000U /*!< ULPI interface protect disable */
+#define USB_OTG_GUSBCFG_FHMOD 0x20000000U /*!< Forced host mode */
+#define USB_OTG_GUSBCFG_FDMOD 0x40000000U /*!< Forced peripheral mode */
+#define USB_OTG_GUSBCFG_CTXPKT 0x80000000U /*!< Corrupt Tx packet */
+
+/******************** Bit definition forUSB_OTG_GRSTCTL register ********************/
+#define USB_OTG_GRSTCTL_CSRST 0x00000001U /*!< Core soft reset */
+#define USB_OTG_GRSTCTL_HSRST 0x00000002U /*!< HCLK soft reset */
+#define USB_OTG_GRSTCTL_FCRST 0x00000004U /*!< Host frame counter reset */
+#define USB_OTG_GRSTCTL_RXFFLSH 0x00000010U /*!< RxFIFO flush */
+#define USB_OTG_GRSTCTL_TXFFLSH 0x00000020U /*!< TxFIFO flush */
+
+#define USB_OTG_GRSTCTL_TXFNUM 0x000007C0U /*!< TxFIFO number */
+#define USB_OTG_GRSTCTL_TXFNUM_0 0x00000040U /*!<Bit 0 */
+#define USB_OTG_GRSTCTL_TXFNUM_1 0x00000080U /*!<Bit 1 */
+#define USB_OTG_GRSTCTL_TXFNUM_2 0x00000100U /*!<Bit 2 */
+#define USB_OTG_GRSTCTL_TXFNUM_3 0x00000200U /*!<Bit 3 */
+#define USB_OTG_GRSTCTL_TXFNUM_4 0x00000400U /*!<Bit 4 */
+#define USB_OTG_GRSTCTL_DMAREQ 0x40000000U /*!< DMA request signal */
+#define USB_OTG_GRSTCTL_AHBIDL 0x80000000U /*!< AHB master idle */
+
+/******************** Bit definition forUSB_OTG_DIEPMSK register ********************/
+#define USB_OTG_DIEPMSK_XFRCM 0x00000001U /*!< Transfer completed interrupt mask */
+#define USB_OTG_DIEPMSK_EPDM 0x00000002U /*!< Endpoint disabled interrupt mask */
+#define USB_OTG_DIEPMSK_TOM 0x00000008U /*!< Timeout condition mask (nonisochronous endpoints) */
+#define USB_OTG_DIEPMSK_ITTXFEMSK 0x00000010U /*!< IN token received when TxFIFO empty mask */
+#define USB_OTG_DIEPMSK_INEPNMM 0x00000020U /*!< IN token received with EP mismatch mask */
+#define USB_OTG_DIEPMSK_INEPNEM 0x00000040U /*!< IN endpoint NAK effective mask */
+#define USB_OTG_DIEPMSK_TXFURM 0x00000100U /*!< FIFO underrun mask */
+#define USB_OTG_DIEPMSK_BIM 0x00000200U /*!< BNA interrupt mask */
+
+/******************** Bit definition forUSB_OTG_HPTXSTS register ********************/
+#define USB_OTG_HPTXSTS_PTXFSAVL 0x0000FFFFU /*!< Periodic transmit data FIFO space available */
+
+#define USB_OTG_HPTXSTS_PTXQSAV 0x00FF0000U /*!< Periodic transmit request queue space available */
+#define USB_OTG_HPTXSTS_PTXQSAV_0 0x00010000U /*!<Bit 0 */
+#define USB_OTG_HPTXSTS_PTXQSAV_1 0x00020000U /*!<Bit 1 */
+#define USB_OTG_HPTXSTS_PTXQSAV_2 0x00040000U /*!<Bit 2 */
+#define USB_OTG_HPTXSTS_PTXQSAV_3 0x00080000U /*!<Bit 3 */
+#define USB_OTG_HPTXSTS_PTXQSAV_4 0x00100000U /*!<Bit 4 */
+#define USB_OTG_HPTXSTS_PTXQSAV_5 0x00200000U /*!<Bit 5 */
+#define USB_OTG_HPTXSTS_PTXQSAV_6 0x00400000U /*!<Bit 6 */
+#define USB_OTG_HPTXSTS_PTXQSAV_7 0x00800000U /*!<Bit 7 */
+
+#define USB_OTG_HPTXSTS_PTXQTOP 0xFF000000U /*!< Top of the periodic transmit request queue */
+#define USB_OTG_HPTXSTS_PTXQTOP_0 0x01000000U /*!<Bit 0 */
+#define USB_OTG_HPTXSTS_PTXQTOP_1 0x02000000U /*!<Bit 1 */
+#define USB_OTG_HPTXSTS_PTXQTOP_2 0x04000000U /*!<Bit 2 */
+#define USB_OTG_HPTXSTS_PTXQTOP_3 0x08000000U /*!<Bit 3 */
+#define USB_OTG_HPTXSTS_PTXQTOP_4 0x10000000U /*!<Bit 4 */
+#define USB_OTG_HPTXSTS_PTXQTOP_5 0x20000000U /*!<Bit 5 */
+#define USB_OTG_HPTXSTS_PTXQTOP_6 0x40000000U /*!<Bit 6 */
+#define USB_OTG_HPTXSTS_PTXQTOP_7 0x80000000U /*!<Bit 7 */
+
+/******************** Bit definition forUSB_OTG_HAINT register ********************/
+#define USB_OTG_HAINT_HAINT 0x0000FFFFU /*!< Channel interrupts */
+
+/******************** Bit definition forUSB_OTG_DOEPMSK register ********************/
+#define USB_OTG_DOEPMSK_XFRCM 0x00000001U /*!< Transfer completed interrupt mask */
+#define USB_OTG_DOEPMSK_EPDM 0x00000002U /*!< Endpoint disabled interrupt mask */
+#define USB_OTG_DOEPMSK_STUPM 0x00000008U /*!< SETUP phase done mask */
+#define USB_OTG_DOEPMSK_OTEPDM 0x00000010U /*!< OUT token received when endpoint disabled mask */
+#define USB_OTG_DOEPMSK_B2BSTUP 0x00000040U /*!< Back-to-back SETUP packets received mask */
+#define USB_OTG_DOEPMSK_OPEM 0x00000100U /*!< OUT packet error mask */
+#define USB_OTG_DOEPMSK_BOIM 0x00000200U /*!< BNA interrupt mask */
+
+/******************** Bit definition forUSB_OTG_GINTSTS register ********************/
+#define USB_OTG_GINTSTS_CMOD 0x00000001U /*!< Current mode of operation */
+#define USB_OTG_GINTSTS_MMIS 0x00000002U /*!< Mode mismatch interrupt */
+#define USB_OTG_GINTSTS_OTGINT 0x00000004U /*!< OTG interrupt */
+#define USB_OTG_GINTSTS_SOF 0x00000008U /*!< Start of frame */
+#define USB_OTG_GINTSTS_RXFLVL 0x00000010U /*!< RxFIFO nonempty */
+#define USB_OTG_GINTSTS_NPTXFE 0x00000020U /*!< Nonperiodic TxFIFO empty */
+#define USB_OTG_GINTSTS_GINAKEFF 0x00000040U /*!< Global IN nonperiodic NAK effective */
+#define USB_OTG_GINTSTS_BOUTNAKEFF 0x00000080U /*!< Global OUT NAK effective */
+#define USB_OTG_GINTSTS_ESUSP 0x00000400U /*!< Early suspend */
+#define USB_OTG_GINTSTS_USBSUSP 0x00000800U /*!< USB suspend */
+#define USB_OTG_GINTSTS_USBRST 0x00001000U /*!< USB reset */
+#define USB_OTG_GINTSTS_ENUMDNE 0x00002000U /*!< Enumeration done */
+#define USB_OTG_GINTSTS_ISOODRP 0x00004000U /*!< Isochronous OUT packet dropped interrupt */
+#define USB_OTG_GINTSTS_EOPF 0x00008000U /*!< End of periodic frame interrupt */
+#define USB_OTG_GINTSTS_IEPINT 0x00040000U /*!< IN endpoint interrupt */
+#define USB_OTG_GINTSTS_OEPINT 0x00080000U /*!< OUT endpoint interrupt */
+#define USB_OTG_GINTSTS_IISOIXFR 0x00100000U /*!< Incomplete isochronous IN transfer */
+#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT 0x00200000U /*!< Incomplete periodic transfer */
+#define USB_OTG_GINTSTS_DATAFSUSP 0x00400000U /*!< Data fetch suspended */
+#define USB_OTG_GINTSTS_HPRTINT 0x01000000U /*!< Host port interrupt */
+#define USB_OTG_GINTSTS_HCINT 0x02000000U /*!< Host channels interrupt */
+#define USB_OTG_GINTSTS_PTXFE 0x04000000U /*!< Periodic TxFIFO empty */
+#define USB_OTG_GINTSTS_CIDSCHG 0x10000000U /*!< Connector ID status change */
+#define USB_OTG_GINTSTS_DISCINT 0x20000000U /*!< Disconnect detected interrupt */
+#define USB_OTG_GINTSTS_SRQINT 0x40000000U /*!< Session request/new session detected interrupt */
+#define USB_OTG_GINTSTS_WKUINT 0x80000000U /*!< Resume/remote wakeup detected interrupt */
+
+/******************** Bit definition forUSB_OTG_GINTMSK register ********************/
+#define USB_OTG_GINTMSK_MMISM 0x00000002U /*!< Mode mismatch interrupt mask */
+#define USB_OTG_GINTMSK_OTGINT 0x00000004U /*!< OTG interrupt mask */
+#define USB_OTG_GINTMSK_SOFM 0x00000008U /*!< Start of frame mask */
+#define USB_OTG_GINTMSK_RXFLVLM 0x00000010U /*!< Receive FIFO nonempty mask */
+#define USB_OTG_GINTMSK_NPTXFEM 0x00000020U /*!< Nonperiodic TxFIFO empty mask */
+#define USB_OTG_GINTMSK_GINAKEFFM 0x00000040U /*!< Global nonperiodic IN NAK effective mask */
+#define USB_OTG_GINTMSK_GONAKEFFM 0x00000080U /*!< Global OUT NAK effective mask */
+#define USB_OTG_GINTMSK_ESUSPM 0x00000400U /*!< Early suspend mask */
+#define USB_OTG_GINTMSK_USBSUSPM 0x00000800U /*!< USB suspend mask */
+#define USB_OTG_GINTMSK_USBRST 0x00001000U /*!< USB reset mask */
+#define USB_OTG_GINTMSK_ENUMDNEM 0x00002000U /*!< Enumeration done mask */
+#define USB_OTG_GINTMSK_ISOODRPM 0x00004000U /*!< Isochronous OUT packet dropped interrupt mask */
+#define USB_OTG_GINTMSK_EOPFM 0x00008000U /*!< End of periodic frame interrupt mask */
+#define USB_OTG_GINTMSK_EPMISM 0x00020000U /*!< Endpoint mismatch interrupt mask */
+#define USB_OTG_GINTMSK_IEPINT 0x00040000U /*!< IN endpoints interrupt mask */
+#define USB_OTG_GINTMSK_OEPINT 0x00080000U /*!< OUT endpoints interrupt mask */
+#define USB_OTG_GINTMSK_IISOIXFRM 0x00100000U /*!< Incomplete isochronous IN transfer mask */
+#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM 0x00200000U /*!< Incomplete periodic transfer mask */
+#define USB_OTG_GINTMSK_FSUSPM 0x00400000U /*!< Data fetch suspended mask */
+#define USB_OTG_GINTMSK_PRTIM 0x01000000U /*!< Host port interrupt mask */
+#define USB_OTG_GINTMSK_HCIM 0x02000000U /*!< Host channels interrupt mask */
+#define USB_OTG_GINTMSK_PTXFEM 0x04000000U /*!< Periodic TxFIFO empty mask */
+#define USB_OTG_GINTMSK_CIDSCHGM 0x10000000U /*!< Connector ID status change mask */
+#define USB_OTG_GINTMSK_DISCINT 0x20000000U /*!< Disconnect detected interrupt mask */
+#define USB_OTG_GINTMSK_SRQIM 0x40000000U /*!< Session request/new session detected interrupt mask */
+#define USB_OTG_GINTMSK_WUIM 0x80000000U /*!< Resume/remote wakeup detected interrupt mask */
+
+/******************** Bit definition forUSB_OTG_DAINT register ********************/
+#define USB_OTG_DAINT_IEPINT 0x0000FFFFU /*!< IN endpoint interrupt bits */
+#define USB_OTG_DAINT_OEPINT 0xFFFF0000U /*!< OUT endpoint interrupt bits */
+
+/******************** Bit definition forUSB_OTG_HAINTMSK register ********************/
+#define USB_OTG_HAINTMSK_HAINTM 0x0000FFFFU /*!< Channel interrupt mask */
+
+/******************** Bit definition for USB_OTG_GRXSTSP register ********************/
+#define USB_OTG_GRXSTSP_EPNUM 0x0000000FU /*!< IN EP interrupt mask bits */
+#define USB_OTG_GRXSTSP_BCNT 0x00007FF0U /*!< OUT EP interrupt mask bits */
+#define USB_OTG_GRXSTSP_DPID 0x00018000U /*!< OUT EP interrupt mask bits */
+#define USB_OTG_GRXSTSP_PKTSTS 0x001E0000U /*!< OUT EP interrupt mask bits */
+
+/******************** Bit definition forUSB_OTG_DAINTMSK register ********************/
+#define USB_OTG_DAINTMSK_IEPM 0x0000FFFFU /*!< IN EP interrupt mask bits */
+#define USB_OTG_DAINTMSK_OEPM 0xFFFF0000U /*!< OUT EP interrupt mask bits */
+
+/******************** Bit definition for OTG register ********************/
+
+#define USB_OTG_CHNUM 0x0000000FU /*!< Channel number */
+#define USB_OTG_CHNUM_0 0x00000001U /*!<Bit 0 */
+#define USB_OTG_CHNUM_1 0x00000002U /*!<Bit 1 */
+#define USB_OTG_CHNUM_2 0x00000004U /*!<Bit 2 */
+#define USB_OTG_CHNUM_3 0x00000008U /*!<Bit 3 */
+#define USB_OTG_BCNT 0x00007FF0U /*!< Byte count */
+
+#define USB_OTG_DPID 0x00018000U /*!< Data PID */
+#define USB_OTG_DPID_0 0x00008000U /*!<Bit 0 */
+#define USB_OTG_DPID_1 0x00010000U /*!<Bit 1 */
+
+#define USB_OTG_PKTSTS 0x001E0000U /*!< Packet status */
+#define USB_OTG_PKTSTS_0 0x00020000U /*!<Bit 0 */
+#define USB_OTG_PKTSTS_1 0x00040000U /*!<Bit 1 */
+#define USB_OTG_PKTSTS_2 0x00080000U /*!<Bit 2 */
+#define USB_OTG_PKTSTS_3 0x00100000U /*!<Bit 3 */
+
+#define USB_OTG_EPNUM 0x0000000FU /*!< Endpoint number */
+#define USB_OTG_EPNUM_0 0x00000001U /*!<Bit 0 */
+#define USB_OTG_EPNUM_1 0x00000002U /*!<Bit 1 */
+#define USB_OTG_EPNUM_2 0x00000004U /*!<Bit 2 */
+#define USB_OTG_EPNUM_3 0x00000008U /*!<Bit 3 */
+
+#define USB_OTG_FRMNUM 0x01E00000U /*!< Frame number */
+#define USB_OTG_FRMNUM_0 0x00200000U /*!<Bit 0 */
+#define USB_OTG_FRMNUM_1 0x00400000U /*!<Bit 1 */
+#define USB_OTG_FRMNUM_2 0x00800000U /*!<Bit 2 */
+#define USB_OTG_FRMNUM_3 0x01000000U /*!<Bit 3 */
+
+/******************** Bit definition for OTG register ********************/
+
+#define USB_OTG_CHNUM 0x0000000FU /*!< Channel number */
+#define USB_OTG_CHNUM_0 0x00000001U /*!<Bit 0 */
+#define USB_OTG_CHNUM_1 0x00000002U /*!<Bit 1 */
+#define USB_OTG_CHNUM_2 0x00000004U /*!<Bit 2 */
+#define USB_OTG_CHNUM_3 0x00000008U /*!<Bit 3 */
+#define USB_OTG_BCNT 0x00007FF0U /*!< Byte count */
+
+#define USB_OTG_DPID 0x00018000U /*!< Data PID */
+#define USB_OTG_DPID_0 0x00008000U /*!<Bit 0 */
+#define USB_OTG_DPID_1 0x00010000U /*!<Bit 1 */
+
+#define USB_OTG_PKTSTS 0x001E0000U /*!< Packet status */
+#define USB_OTG_PKTSTS_0 0x00020000U /*!<Bit 0 */
+#define USB_OTG_PKTSTS_1 0x00040000U /*!<Bit 1 */
+#define USB_OTG_PKTSTS_2 0x00080000U /*!<Bit 2 */
+#define USB_OTG_PKTSTS_3 0x00100000U /*!<Bit 3 */
+
+#define USB_OTG_EPNUM 0x0000000FU /*!< Endpoint number */
+#define USB_OTG_EPNUM_0 0x00000001U /*!<Bit 0 */
+#define USB_OTG_EPNUM_1 0x00000002U /*!<Bit 1 */
+#define USB_OTG_EPNUM_2 0x00000004U /*!<Bit 2 */
+#define USB_OTG_EPNUM_3 0x00000008U /*!<Bit 3 */
+
+#define USB_OTG_FRMNUM 0x01E00000U /*!< Frame number */
+#define USB_OTG_FRMNUM_0 0x00200000U /*!<Bit 0 */
+#define USB_OTG_FRMNUM_1 0x00400000U /*!<Bit 1 */
+#define USB_OTG_FRMNUM_2 0x00800000U /*!<Bit 2 */
+#define USB_OTG_FRMNUM_3 0x01000000U /*!<Bit 3 */
+
+/******************** Bit definition forUSB_OTG_GRXFSIZ register ********************/
+#define USB_OTG_GRXFSIZ_RXFD 0x0000FFFFU /*!< RxFIFO depth */
+
+/******************** Bit definition forUSB_OTG_DVBUSDIS register ********************/
+#define USB_OTG_DVBUSDIS_VBUSDT 0x0000FFFFU /*!< Device VBUS discharge time */
+
+/******************** Bit definition for OTG register ********************/
+#define USB_OTG_NPTXFSA 0x0000FFFFU /*!< Nonperiodic transmit RAM start address */
+#define USB_OTG_NPTXFD 0xFFFF0000U /*!< Nonperiodic TxFIFO depth */
+#define USB_OTG_TX0FSA 0x0000FFFFU /*!< Endpoint 0 transmit RAM start address */
+#define USB_OTG_TX0FD 0xFFFF0000U /*!< Endpoint 0 TxFIFO depth */
+
+/******************** Bit definition forUSB_OTG_DVBUSPULSE register ********************/
+#define USB_OTG_DVBUSPULSE_DVBUSP 0x00000FFFU /*!< Device VBUS pulsing time */
+
+/******************** Bit definition forUSB_OTG_GNPTXSTS register ********************/
+#define USB_OTG_GNPTXSTS_NPTXFSAV 0x0000FFFFU /*!< Nonperiodic TxFIFO space available */
+
+#define USB_OTG_GNPTXSTS_NPTQXSAV 0x00FF0000U /*!< Nonperiodic transmit request queue space available */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_0 0x00010000U /*!<Bit 0 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_1 0x00020000U /*!<Bit 1 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_2 0x00040000U /*!<Bit 2 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_3 0x00080000U /*!<Bit 3 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_4 0x00100000U /*!<Bit 4 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_5 0x00200000U /*!<Bit 5 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_6 0x00400000U /*!<Bit 6 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_7 0x00800000U /*!<Bit 7 */
+
+#define USB_OTG_GNPTXSTS_NPTXQTOP 0x7F000000U /*!< Top of the nonperiodic transmit request queue */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_0 0x01000000U /*!<Bit 0 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_1 0x02000000U /*!<Bit 1 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_2 0x04000000U /*!<Bit 2 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_3 0x08000000U /*!<Bit 3 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_4 0x10000000U /*!<Bit 4 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_5 0x20000000U /*!<Bit 5 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_6 0x40000000U /*!<Bit 6 */
+
+/******************** Bit definition forUSB_OTG_DTHRCTL register ********************/
+#define USB_OTG_DTHRCTL_NONISOTHREN 0x00000001U /*!< Nonisochronous IN endpoints threshold enable */
+#define USB_OTG_DTHRCTL_ISOTHREN 0x00000002U /*!< ISO IN endpoint threshold enable */
+
+#define USB_OTG_DTHRCTL_TXTHRLEN 0x000007FCU /*!< Transmit threshold length */
+#define USB_OTG_DTHRCTL_TXTHRLEN_0 0x00000004U /*!<Bit 0 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_1 0x00000008U /*!<Bit 1 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_2 0x00000010U /*!<Bit 2 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_3 0x00000020U /*!<Bit 3 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_4 0x00000040U /*!<Bit 4 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_5 0x00000080U /*!<Bit 5 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_6 0x00000100U /*!<Bit 6 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_7 0x00000200U /*!<Bit 7 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_8 0x00000400U /*!<Bit 8 */
+#define USB_OTG_DTHRCTL_RXTHREN 0x00010000U /*!< Receive threshold enable */
+
+#define USB_OTG_DTHRCTL_RXTHRLEN 0x03FE0000U /*!< Receive threshold length */
+#define USB_OTG_DTHRCTL_RXTHRLEN_0 0x00020000U /*!<Bit 0 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_1 0x00040000U /*!<Bit 1 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_2 0x00080000U /*!<Bit 2 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_3 0x00100000U /*!<Bit 3 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_4 0x00200000U /*!<Bit 4 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_5 0x00400000U /*!<Bit 5 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_6 0x00800000U /*!<Bit 6 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_7 0x01000000U /*!<Bit 7 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_8 0x02000000U /*!<Bit 8 */
+#define USB_OTG_DTHRCTL_ARPEN 0x08000000U /*!< Arbiter parking enable */
+
+/******************** Bit definition forUSB_OTG_DIEPEMPMSK register ********************/
+#define USB_OTG_DIEPEMPMSK_INEPTXFEM 0x0000FFFFU /*!< IN EP Tx FIFO empty interrupt mask bits */
+
+/******************** Bit definition forUSB_OTG_DEACHINT register ********************/
+#define USB_OTG_DEACHINT_IEP1INT 0x00000002U /*!< IN endpoint 1interrupt bit */
+#define USB_OTG_DEACHINT_OEP1INT 0x00020000U /*!< OUT endpoint 1 interrupt bit */
+
+/******************** Bit definition forUSB_OTG_GCCFG register ********************/
+#define USB_OTG_GCCFG_PWRDWN 0x00010000U /*!< Power down */
+#define USB_OTG_GCCFG_I2CPADEN 0x00020000U /*!< Enable I2C bus connection for the external I2C PHY interface */
+#define USB_OTG_GCCFG_VBUSASEN 0x00040000U /*!< Enable the VBUS sensing device */
+#define USB_OTG_GCCFG_VBUSBSEN 0x00080000U /*!< Enable the VBUS sensing device */
+#define USB_OTG_GCCFG_SOFOUTEN 0x00100000U /*!< SOF output enable */
+#define USB_OTG_GCCFG_NOVBUSSENS 0x00200000U /*!< VBUS sensing disable option */
+
+/******************** Bit definition forUSB_OTG_DEACHINTMSK register ********************/
+#define USB_OTG_DEACHINTMSK_IEP1INTM 0x00000002U /*!< IN Endpoint 1 interrupt mask bit */
+#define USB_OTG_DEACHINTMSK_OEP1INTM 0x00020000U /*!< OUT Endpoint 1 interrupt mask bit */
+
+/******************** Bit definition forUSB_OTG_CID register ********************/
+#define USB_OTG_CID_PRODUCT_ID 0xFFFFFFFFU /*!< Product ID field */
+
+/******************** Bit definition forUSB_OTG_DIEPEACHMSK1 register ********************/
+#define USB_OTG_DIEPEACHMSK1_XFRCM 0x00000001U /*!< Transfer completed interrupt mask */
+#define USB_OTG_DIEPEACHMSK1_EPDM 0x00000002U /*!< Endpoint disabled interrupt mask */
+#define USB_OTG_DIEPEACHMSK1_TOM 0x00000008U /*!< Timeout condition mask (nonisochronous endpoints) */
+#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK 0x00000010U /*!< IN token received when TxFIFO empty mask */
+#define USB_OTG_DIEPEACHMSK1_INEPNMM 0x00000020U /*!< IN token received with EP mismatch mask */
+#define USB_OTG_DIEPEACHMSK1_INEPNEM 0x00000040U /*!< IN endpoint NAK effective mask */
+#define USB_OTG_DIEPEACHMSK1_TXFURM 0x00000100U /*!< FIFO underrun mask */
+#define USB_OTG_DIEPEACHMSK1_BIM 0x00000200U /*!< BNA interrupt mask */
+#define USB_OTG_DIEPEACHMSK1_NAKM 0x00002000U /*!< NAK interrupt mask */
+
+/******************** Bit definition forUSB_OTG_HPRT register ********************/
+#define USB_OTG_HPRT_PCSTS 0x00000001U /*!< Port connect status */
+#define USB_OTG_HPRT_PCDET 0x00000002U /*!< Port connect detected */
+#define USB_OTG_HPRT_PENA 0x00000004U /*!< Port enable */
+#define USB_OTG_HPRT_PENCHNG 0x00000008U /*!< Port enable/disable change */
+#define USB_OTG_HPRT_POCA 0x00000010U /*!< Port overcurrent active */
+#define USB_OTG_HPRT_POCCHNG 0x00000020U /*!< Port overcurrent change */
+#define USB_OTG_HPRT_PRES 0x00000040U /*!< Port resume */
+#define USB_OTG_HPRT_PSUSP 0x00000080U /*!< Port suspend */
+#define USB_OTG_HPRT_PRST 0x00000100U /*!< Port reset */
+
+#define USB_OTG_HPRT_PLSTS 0x00000C00U /*!< Port line status */
+#define USB_OTG_HPRT_PLSTS_0 0x00000400U /*!<Bit 0 */
+#define USB_OTG_HPRT_PLSTS_1 0x00000800U /*!<Bit 1 */
+#define USB_OTG_HPRT_PPWR 0x00001000U /*!< Port power */
+
+#define USB_OTG_HPRT_PTCTL 0x0001E000U /*!< Port test control */
+#define USB_OTG_HPRT_PTCTL_0 0x00002000U /*!<Bit 0 */
+#define USB_OTG_HPRT_PTCTL_1 0x00004000U /*!<Bit 1 */
+#define USB_OTG_HPRT_PTCTL_2 0x00008000U /*!<Bit 2 */
+#define USB_OTG_HPRT_PTCTL_3 0x00010000U /*!<Bit 3 */
+
+#define USB_OTG_HPRT_PSPD 0x00060000U /*!< Port speed */
+#define USB_OTG_HPRT_PSPD_0 0x00020000U /*!<Bit 0 */
+#define USB_OTG_HPRT_PSPD_1 0x00040000U /*!<Bit 1 */
+
+/******************** Bit definition forUSB_OTG_DOEPEACHMSK1 register ********************/
+#define USB_OTG_DOEPEACHMSK1_XFRCM 0x00000001U /*!< Transfer completed interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_EPDM 0x00000002U /*!< Endpoint disabled interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_TOM 0x00000008U /*!< Timeout condition mask */
+#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK 0x00000010U /*!< IN token received when TxFIFO empty mask */
+#define USB_OTG_DOEPEACHMSK1_INEPNMM 0x00000020U /*!< IN token received with EP mismatch mask */
+#define USB_OTG_DOEPEACHMSK1_INEPNEM 0x00000040U /*!< IN endpoint NAK effective mask */
+#define USB_OTG_DOEPEACHMSK1_TXFURM 0x00000100U /*!< OUT packet error mask */
+#define USB_OTG_DOEPEACHMSK1_BIM 0x00000200U /*!< BNA interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_BERRM 0x00001000U /*!< Bubble error interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_NAKM 0x00002000U /*!< NAK interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_NYETM 0x00004000U /*!< NYET interrupt mask */
+
+/******************** Bit definition forUSB_OTG_HPTXFSIZ register ********************/
+#define USB_OTG_HPTXFSIZ_PTXSA 0x0000FFFFU /*!< Host periodic TxFIFO start address */
+#define USB_OTG_HPTXFSIZ_PTXFD 0xFFFF0000U /*!< Host periodic TxFIFO depth */
+
+/******************** Bit definition forUSB_OTG_DIEPCTL register ********************/
+#define USB_OTG_DIEPCTL_MPSIZ 0x000007FFU /*!< Maximum packet size */
+#define USB_OTG_DIEPCTL_USBAEP 0x00008000U /*!< USB active endpoint */
+#define USB_OTG_DIEPCTL_EONUM_DPID 0x00010000U /*!< Even/odd frame */
+#define USB_OTG_DIEPCTL_NAKSTS 0x00020000U /*!< NAK status */
+
+#define USB_OTG_DIEPCTL_EPTYP 0x000C0000U /*!< Endpoint type */
+#define USB_OTG_DIEPCTL_EPTYP_0 0x00040000U /*!<Bit 0 */
+#define USB_OTG_DIEPCTL_EPTYP_1 0x00080000U /*!<Bit 1 */
+#define USB_OTG_DIEPCTL_STALL 0x00200000U /*!< STALL handshake */
+
+#define USB_OTG_DIEPCTL_TXFNUM 0x03C00000U /*!< TxFIFO number */
+#define USB_OTG_DIEPCTL_TXFNUM_0 0x00400000U /*!<Bit 0 */
+#define USB_OTG_DIEPCTL_TXFNUM_1 0x00800000U /*!<Bit 1 */
+#define USB_OTG_DIEPCTL_TXFNUM_2 0x01000000U /*!<Bit 2 */
+#define USB_OTG_DIEPCTL_TXFNUM_3 0x02000000U /*!<Bit 3 */
+#define USB_OTG_DIEPCTL_CNAK 0x04000000U /*!< Clear NAK */
+#define USB_OTG_DIEPCTL_SNAK 0x08000000U /*!< Set NAK */
+#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM 0x10000000U /*!< Set DATA0 PID */
+#define USB_OTG_DIEPCTL_SODDFRM 0x20000000U /*!< Set odd frame */
+#define USB_OTG_DIEPCTL_EPDIS 0x40000000U /*!< Endpoint disable */
+#define USB_OTG_DIEPCTL_EPENA 0x80000000U /*!< Endpoint enable */
+
+/******************** Bit definition forUSB_OTG_HCCHAR register ********************/
+#define USB_OTG_HCCHAR_MPSIZ 0x000007FFU /*!< Maximum packet size */
+
+#define USB_OTG_HCCHAR_EPNUM 0x00007800U /*!< Endpoint number */
+#define USB_OTG_HCCHAR_EPNUM_0 0x00000800U /*!<Bit 0 */
+#define USB_OTG_HCCHAR_EPNUM_1 0x00001000U /*!<Bit 1 */
+#define USB_OTG_HCCHAR_EPNUM_2 0x00002000U /*!<Bit 2 */
+#define USB_OTG_HCCHAR_EPNUM_3 0x00004000U /*!<Bit 3 */
+#define USB_OTG_HCCHAR_EPDIR 0x00008000U /*!< Endpoint direction */
+#define USB_OTG_HCCHAR_LSDEV 0x00020000U /*!< Low-speed device */
+
+#define USB_OTG_HCCHAR_EPTYP 0x000C0000U /*!< Endpoint type */
+#define USB_OTG_HCCHAR_EPTYP_0 0x00040000U /*!<Bit 0 */
+#define USB_OTG_HCCHAR_EPTYP_1 0x00080000U /*!<Bit 1 */
+
+#define USB_OTG_HCCHAR_MC 0x00300000U /*!< Multi Count (MC) / Error Count (EC) */
+#define USB_OTG_HCCHAR_MC_0 0x00100000U /*!<Bit 0 */
+#define USB_OTG_HCCHAR_MC_1 0x00200000U /*!<Bit 1 */
+
+#define USB_OTG_HCCHAR_DAD 0x1FC00000U /*!< Device address */
+#define USB_OTG_HCCHAR_DAD_0 0x00400000U /*!<Bit 0 */
+#define USB_OTG_HCCHAR_DAD_1 0x00800000U /*!<Bit 1 */
+#define USB_OTG_HCCHAR_DAD_2 0x01000000U /*!<Bit 2 */
+#define USB_OTG_HCCHAR_DAD_3 0x02000000U /*!<Bit 3 */
+#define USB_OTG_HCCHAR_DAD_4 0x04000000U /*!<Bit 4 */
+#define USB_OTG_HCCHAR_DAD_5 0x08000000U /*!<Bit 5 */
+#define USB_OTG_HCCHAR_DAD_6 0x10000000U /*!<Bit 6 */
+#define USB_OTG_HCCHAR_ODDFRM 0x20000000U /*!< Odd frame */
+#define USB_OTG_HCCHAR_CHDIS 0x40000000U /*!< Channel disable */
+#define USB_OTG_HCCHAR_CHENA 0x80000000U /*!< Channel enable */
+
+/******************** Bit definition forUSB_OTG_HCSPLT register ********************/
+
+#define USB_OTG_HCSPLT_PRTADDR 0x0000007FU /*!< Port address */
+#define USB_OTG_HCSPLT_PRTADDR_0 0x00000001U /*!<Bit 0 */
+#define USB_OTG_HCSPLT_PRTADDR_1 0x00000002U /*!<Bit 1 */
+#define USB_OTG_HCSPLT_PRTADDR_2 0x00000004U /*!<Bit 2 */
+#define USB_OTG_HCSPLT_PRTADDR_3 0x00000008U /*!<Bit 3 */
+#define USB_OTG_HCSPLT_PRTADDR_4 0x00000010U /*!<Bit 4 */
+#define USB_OTG_HCSPLT_PRTADDR_5 0x00000020U /*!<Bit 5 */
+#define USB_OTG_HCSPLT_PRTADDR_6 0x00000040U /*!<Bit 6 */
+
+#define USB_OTG_HCSPLT_HUBADDR 0x00003F80U /*!< Hub address */
+#define USB_OTG_HCSPLT_HUBADDR_0 0x00000080U /*!<Bit 0 */
+#define USB_OTG_HCSPLT_HUBADDR_1 0x00000100U /*!<Bit 1 */
+#define USB_OTG_HCSPLT_HUBADDR_2 0x00000200U /*!<Bit 2 */
+#define USB_OTG_HCSPLT_HUBADDR_3 0x00000400U /*!<Bit 3 */
+#define USB_OTG_HCSPLT_HUBADDR_4 0x00000800U /*!<Bit 4 */
+#define USB_OTG_HCSPLT_HUBADDR_5 0x00001000U /*!<Bit 5 */
+#define USB_OTG_HCSPLT_HUBADDR_6 0x00002000U /*!<Bit 6 */
+
+#define USB_OTG_HCSPLT_XACTPOS 0x0000C000U /*!< XACTPOS */
+#define USB_OTG_HCSPLT_XACTPOS_0 0x00004000U /*!<Bit 0 */
+#define USB_OTG_HCSPLT_XACTPOS_1 0x00008000U /*!<Bit 1 */
+#define USB_OTG_HCSPLT_COMPLSPLT 0x00010000U /*!< Do complete split */
+#define USB_OTG_HCSPLT_SPLITEN 0x80000000U /*!< Split enable */
+
+/******************** Bit definition forUSB_OTG_HCINT register ********************/
+#define USB_OTG_HCINT_XFRC 0x00000001U /*!< Transfer completed */
+#define USB_OTG_HCINT_CHH 0x00000002U /*!< Channel halted */
+#define USB_OTG_HCINT_AHBERR 0x00000004U /*!< AHB error */
+#define USB_OTG_HCINT_STALL 0x00000008U /*!< STALL response received interrupt */
+#define USB_OTG_HCINT_NAK 0x00000010U /*!< NAK response received interrupt */
+#define USB_OTG_HCINT_ACK 0x00000020U /*!< ACK response received/transmitted interrupt */
+#define USB_OTG_HCINT_NYET 0x00000040U /*!< Response received interrupt */
+#define USB_OTG_HCINT_TXERR 0x00000080U /*!< Transaction error */
+#define USB_OTG_HCINT_BBERR 0x00000100U /*!< Babble error */
+#define USB_OTG_HCINT_FRMOR 0x00000200U /*!< Frame overrun */
+#define USB_OTG_HCINT_DTERR 0x00000400U /*!< Data toggle error */
+
+/******************** Bit definition forUSB_OTG_DIEPINT register ********************/
+#define USB_OTG_DIEPINT_XFRC 0x00000001U /*!< Transfer completed interrupt */
+#define USB_OTG_DIEPINT_EPDISD 0x00000002U /*!< Endpoint disabled interrupt */
+#define USB_OTG_DIEPINT_TOC 0x00000008U /*!< Timeout condition */
+#define USB_OTG_DIEPINT_ITTXFE 0x00000010U /*!< IN token received when TxFIFO is empty */
+#define USB_OTG_DIEPINT_INEPNE 0x00000040U /*!< IN endpoint NAK effective */
+#define USB_OTG_DIEPINT_TXFE 0x00000080U /*!< Transmit FIFO empty */
+#define USB_OTG_DIEPINT_TXFIFOUDRN 0x00000100U /*!< Transmit Fifo Underrun */
+#define USB_OTG_DIEPINT_BNA 0x00000200U /*!< Buffer not available interrupt */
+#define USB_OTG_DIEPINT_PKTDRPSTS 0x00000800U /*!< Packet dropped status */
+#define USB_OTG_DIEPINT_BERR 0x00001000U /*!< Babble error interrupt */
+#define USB_OTG_DIEPINT_NAK 0x00002000U /*!< NAK interrupt */
+
+/******************** Bit definition forUSB_OTG_HCINTMSK register ********************/
+#define USB_OTG_HCINTMSK_XFRCM 0x00000001U /*!< Transfer completed mask */
+#define USB_OTG_HCINTMSK_CHHM 0x00000002U /*!< Channel halted mask */
+#define USB_OTG_HCINTMSK_AHBERR 0x00000004U /*!< AHB error */
+#define USB_OTG_HCINTMSK_STALLM 0x00000008U /*!< STALL response received interrupt mask */
+#define USB_OTG_HCINTMSK_NAKM 0x00000010U /*!< NAK response received interrupt mask */
+#define USB_OTG_HCINTMSK_ACKM 0x00000020U /*!< ACK response received/transmitted interrupt mask */
+#define USB_OTG_HCINTMSK_NYET 0x00000040U /*!< response received interrupt mask */
+#define USB_OTG_HCINTMSK_TXERRM 0x00000080U /*!< Transaction error mask */
+#define USB_OTG_HCINTMSK_BBERRM 0x00000100U /*!< Babble error mask */
+#define USB_OTG_HCINTMSK_FRMORM 0x00000200U /*!< Frame overrun mask */
+#define USB_OTG_HCINTMSK_DTERRM 0x00000400U /*!< Data toggle error mask */
+
+/******************** Bit definition for USB_OTG_DIEPTSIZ register ********************/
+
+#define USB_OTG_DIEPTSIZ_XFRSIZ 0x0007FFFFU /*!< Transfer size */
+#define USB_OTG_DIEPTSIZ_PKTCNT 0x1FF80000U /*!< Packet count */
+#define USB_OTG_DIEPTSIZ_MULCNT 0x60000000U /*!< Packet count */
+/******************** Bit definition forUSB_OTG_HCTSIZ register ********************/
+#define USB_OTG_HCTSIZ_XFRSIZ 0x0007FFFFU /*!< Transfer size */
+#define USB_OTG_HCTSIZ_PKTCNT 0x1FF80000U /*!< Packet count */
+#define USB_OTG_HCTSIZ_DOPING 0x80000000U /*!< Do PING */
+#define USB_OTG_HCTSIZ_DPID 0x60000000U /*!< Data PID */
+#define USB_OTG_HCTSIZ_DPID_0 0x20000000U /*!<Bit 0 */
+#define USB_OTG_HCTSIZ_DPID_1 0x40000000U /*!<Bit 1 */
+
+/******************** Bit definition forUSB_OTG_DIEPDMA register ********************/
+#define USB_OTG_DIEPDMA_DMAADDR 0xFFFFFFFFU /*!< DMA address */
+
+/******************** Bit definition forUSB_OTG_HCDMA register ********************/
+#define USB_OTG_HCDMA_DMAADDR 0xFFFFFFFFU /*!< DMA address */
+
+/******************** Bit definition forUSB_OTG_DTXFSTS register ********************/
+#define USB_OTG_DTXFSTS_INEPTFSAV 0x0000FFFFU /*!< IN endpoint TxFIFO space avail */
+
+/******************** Bit definition forUSB_OTG_DIEPTXF register ********************/
+#define USB_OTG_DIEPTXF_INEPTXSA 0x0000FFFFU /*!< IN endpoint FIFOx transmit RAM start address */
+#define USB_OTG_DIEPTXF_INEPTXFD 0xFFFF0000U /*!< IN endpoint TxFIFO depth */
+
+/******************** Bit definition forUSB_OTG_DOEPCTL register ********************/
+
+#define USB_OTG_DOEPCTL_MPSIZ 0x000007FFU /*!< Maximum packet size */ /*!<Bit 1 */
+#define USB_OTG_DOEPCTL_USBAEP 0x00008000U /*!< USB active endpoint */
+#define USB_OTG_DOEPCTL_NAKSTS 0x00020000U /*!< NAK status */
+#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM 0x10000000U /*!< Set DATA0 PID */
+#define USB_OTG_DOEPCTL_SODDFRM 0x20000000U /*!< Set odd frame */
+#define USB_OTG_DOEPCTL_EPTYP 0x000C0000U /*!< Endpoint type */
+#define USB_OTG_DOEPCTL_EPTYP_0 0x00040000U /*!<Bit 0 */
+#define USB_OTG_DOEPCTL_EPTYP_1 0x00080000U /*!<Bit 1 */
+#define USB_OTG_DOEPCTL_SNPM 0x00100000U /*!< Snoop mode */
+#define USB_OTG_DOEPCTL_STALL 0x00200000U /*!< STALL handshake */
+#define USB_OTG_DOEPCTL_CNAK 0x04000000U /*!< Clear NAK */
+#define USB_OTG_DOEPCTL_SNAK 0x08000000U /*!< Set NAK */
+#define USB_OTG_DOEPCTL_EPDIS 0x40000000U /*!< Endpoint disable */
+#define USB_OTG_DOEPCTL_EPENA 0x80000000U /*!< Endpoint enable */
+
+/******************** Bit definition forUSB_OTG_DOEPINT register ********************/
+#define USB_OTG_DOEPINT_XFRC 0x00000001U /*!< Transfer completed interrupt */
+#define USB_OTG_DOEPINT_EPDISD 0x00000002U /*!< Endpoint disabled interrupt */
+#define USB_OTG_DOEPINT_STUP 0x00000008U /*!< SETUP phase done */
+#define USB_OTG_DOEPINT_OTEPDIS 0x00000010U /*!< OUT token received when endpoint disabled */
+#define USB_OTG_DOEPINT_B2BSTUP 0x00000040U /*!< Back-to-back SETUP packets received */
+#define USB_OTG_DOEPINT_NYET 0x00004000U /*!< NYET interrupt */
+
+/******************** Bit definition forUSB_OTG_DOEPTSIZ register ********************/
+
+#define USB_OTG_DOEPTSIZ_XFRSIZ 0x0007FFFFU /*!< Transfer size */
+#define USB_OTG_DOEPTSIZ_PKTCNT 0x1FF80000U /*!< Packet count */
+
+#define USB_OTG_DOEPTSIZ_STUPCNT 0x60000000U /*!< SETUP packet count */
+#define USB_OTG_DOEPTSIZ_STUPCNT_0 0x20000000U /*!<Bit 0 */
+#define USB_OTG_DOEPTSIZ_STUPCNT_1 0x40000000U /*!<Bit 1 */
+
+/******************** Bit definition for PCGCCTL register ********************/
+#define USB_OTG_PCGCCTL_STOPCLK 0x00000001U /*!< SETUP packet count */
+#define USB_OTG_PCGCCTL_GATECLK 0x00000002U /*!<Bit 0 */
+#define USB_OTG_PCGCCTL_PHYSUSP 0x00000010U /*!<Bit 1 */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup Exported_macros
+ * @{
+ */
+
+/******************************* ADC Instances ********************************/
+#define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) || \
+ ((INSTANCE) == ADC2) || \
+ ((INSTANCE) == ADC3))
+
+/******************************* CAN Instances ********************************/
+#define IS_CAN_ALL_INSTANCE(INSTANCE) (((INSTANCE) == CAN1) || \
+ ((INSTANCE) == CAN2))
+
+/******************************* CRC Instances ********************************/
+#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
+
+/******************************* DAC Instances ********************************/
+#define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC)
+
+/******************************* DCMI Instances *******************************/
+#define IS_DCMI_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DCMI)
+
+/******************************** DMA Instances *******************************/
+#define IS_DMA_STREAM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0) || \
+ ((INSTANCE) == DMA1_Stream1) || \
+ ((INSTANCE) == DMA1_Stream2) || \
+ ((INSTANCE) == DMA1_Stream3) || \
+ ((INSTANCE) == DMA1_Stream4) || \
+ ((INSTANCE) == DMA1_Stream5) || \
+ ((INSTANCE) == DMA1_Stream6) || \
+ ((INSTANCE) == DMA1_Stream7) || \
+ ((INSTANCE) == DMA2_Stream0) || \
+ ((INSTANCE) == DMA2_Stream1) || \
+ ((INSTANCE) == DMA2_Stream2) || \
+ ((INSTANCE) == DMA2_Stream3) || \
+ ((INSTANCE) == DMA2_Stream4) || \
+ ((INSTANCE) == DMA2_Stream5) || \
+ ((INSTANCE) == DMA2_Stream6) || \
+ ((INSTANCE) == DMA2_Stream7))
+
+/******************************* GPIO Instances *******************************/
+#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
+ ((INSTANCE) == GPIOB) || \
+ ((INSTANCE) == GPIOC) || \
+ ((INSTANCE) == GPIOD) || \
+ ((INSTANCE) == GPIOE) || \
+ ((INSTANCE) == GPIOF) || \
+ ((INSTANCE) == GPIOG) || \
+ ((INSTANCE) == GPIOH) || \
+ ((INSTANCE) == GPIOI))
+
+/******************************** I2C Instances *******************************/
+#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
+ ((INSTANCE) == I2C2) || \
+ ((INSTANCE) == I2C3))
+
+/******************************** I2S Instances *******************************/
+#define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI2) || \
+ ((INSTANCE) == SPI3))
+
+/*************************** I2S Extended Instances ***************************/
+#define IS_I2S_ALL_INSTANCE_EXT(PERIPH) (((INSTANCE) == SPI2) || \
+ ((INSTANCE) == SPI3) || \
+ ((INSTANCE) == I2S2ext) || \
+ ((INSTANCE) == I2S3ext))
+
+/******************************* RNG Instances ********************************/
+#define IS_RNG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RNG)
+
+/****************************** RTC Instances *********************************/
+#define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
+
+/******************************** SPI Instances *******************************/
+#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
+ ((INSTANCE) == SPI2) || \
+ ((INSTANCE) == SPI3))
+
+/*************************** SPI Extended Instances ***************************/
+#define IS_SPI_ALL_INSTANCE_EXT(INSTANCE) (((INSTANCE) == SPI1) || \
+ ((INSTANCE) == SPI2) || \
+ ((INSTANCE) == SPI3) || \
+ ((INSTANCE) == I2S2ext) || \
+ ((INSTANCE) == I2S3ext))
+
+/****************** TIM Instances : All supported instances *******************/
+#define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM6) || \
+ ((INSTANCE) == TIM7) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM9) || \
+ ((INSTANCE) == TIM10) || \
+ ((INSTANCE) == TIM11) || \
+ ((INSTANCE) == TIM12) || \
+ ((INSTANCE) == TIM13) || \
+ ((INSTANCE) == TIM14))
+
+/************* TIM Instances : at least 1 capture/compare channel *************/
+#define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM9) || \
+ ((INSTANCE) == TIM10) || \
+ ((INSTANCE) == TIM11) || \
+ ((INSTANCE) == TIM12) || \
+ ((INSTANCE) == TIM13) || \
+ ((INSTANCE) == TIM14))
+
+/************ TIM Instances : at least 2 capture/compare channels *************/
+#define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM9) || \
+ ((INSTANCE) == TIM12))
+
+/************ TIM Instances : at least 3 capture/compare channels *************/
+#define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8))
+
+/************ TIM Instances : at least 4 capture/compare channels *************/
+#define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8))
+
+/******************** TIM Instances : Advanced-control timers *****************/
+#define IS_TIM_ADVANCED_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM8))
+
+/******************* TIM Instances : Timer input XOR function *****************/
+#define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8))
+
+/****************** TIM Instances : DMA requests generation (UDE) *************/
+#define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM6) || \
+ ((INSTANCE) == TIM7) || \
+ ((INSTANCE) == TIM8))
+
+/************ TIM Instances : DMA requests generation (CCxDE) *****************/
+#define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8))
+
+/************ TIM Instances : DMA requests generation (COMDE) *****************/
+#define IS_TIM_CCDMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8))
+
+/******************** TIM Instances : DMA burst feature ***********************/
+#define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8))
+
+/****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/
+#define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM6) || \
+ ((INSTANCE) == TIM7) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM9) || \
+ ((INSTANCE) == TIM12))
+
+/*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
+#define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM9) || \
+ ((INSTANCE) == TIM12))
+
+/********************** TIM Instances : 32 bit Counter ************************/
+#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)(((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM5))
+
+/***************** TIM Instances : external trigger input availabe ************/
+#define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8))
+
+/****************** TIM Instances : remapping capability **********************/
+#define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM11))
+
+/******************* TIM Instances : output(s) available **********************/
+#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
+ ((((INSTANCE) == TIM1) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM2) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM3) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM4) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM5) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM8) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM9) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2))) \
+ || \
+ (((INSTANCE) == TIM10) && \
+ (((CHANNEL) == TIM_CHANNEL_1))) \
+ || \
+ (((INSTANCE) == TIM11) && \
+ (((CHANNEL) == TIM_CHANNEL_1))) \
+ || \
+ (((INSTANCE) == TIM12) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2))) \
+ || \
+ (((INSTANCE) == TIM13) && \
+ (((CHANNEL) == TIM_CHANNEL_1))) \
+ || \
+ (((INSTANCE) == TIM14) && \
+ (((CHANNEL) == TIM_CHANNEL_1))))
+
+/************ TIM Instances : complementary output(s) available ***************/
+#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
+ ((((INSTANCE) == TIM1) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3))) \
+ || \
+ (((INSTANCE) == TIM8) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3))))
+
+/******************** USART Instances : Synchronous mode **********************/
+#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3) || \
+ ((INSTANCE) == USART6))
+
+/******************** UART Instances : Asynchronous mode **********************/
+#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3) || \
+ ((INSTANCE) == UART4) || \
+ ((INSTANCE) == UART5) || \
+ ((INSTANCE) == USART6))
+
+/****************** UART Instances : Hardware Flow control ********************/
+#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3) || \
+ ((INSTANCE) == USART6))
+
+/********************* UART Instances : Smard card mode ***********************/
+#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3) || \
+ ((INSTANCE) == USART6))
+
+/*********************** UART Instances : IRDA mode ***************************/
+#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3) || \
+ ((INSTANCE) == UART4) || \
+ ((INSTANCE) == UART5) || \
+ ((INSTANCE) == USART6))
+
+/*********************** PCD Instances ****************************************/
+/*********************** PCD Instances ****************************************/
+#define IS_PCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS) || \
+ ((INSTANCE) == USB_OTG_HS))
+
+/*********************** HCD Instances ****************************************/
+#define IS_HCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS) || \
+ ((INSTANCE) == USB_OTG_HS))
+
+/****************************** IWDG Instances ********************************/
+#define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
+
+/****************************** WWDG Instances ********************************/
+#define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
+
+/****************************** SDIO Instances ********************************/
+#define IS_SDIO_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SDIO)
+
+/****************************** USB Exported Constants ************************/
+#define USB_OTG_FS_HOST_MAX_CHANNEL_NBR 8U
+#define USB_OTG_FS_MAX_IN_ENDPOINTS 4U /* Including EP0 */
+#define USB_OTG_FS_MAX_OUT_ENDPOINTS 4U /* Including EP0 */
+#define USB_OTG_FS_TOTAL_FIFO_SIZE 1280U /* in Bytes */
+
+#define USB_OTG_HS_HOST_MAX_CHANNEL_NBR 12U
+#define USB_OTG_HS_MAX_IN_ENDPOINTS 6U /* Including EP0 */
+#define USB_OTG_HS_MAX_OUT_ENDPOINTS 6U /* Including EP0 */
+#define USB_OTG_HS_TOTAL_FIFO_SIZE 4096U /* in Bytes */
+
+/******************************************************************************/
+/* For a painless codes migration between the STM32F4xx device product */
+/* lines, the aliases defined below are put in place to overcome the */
+/* differences in the interrupt handlers and IRQn definitions. */
+/* No need to update developed interrupt code when moving across */
+/* product lines within the same STM32F4 Family */
+/******************************************************************************/
+
+/* Aliases for __IRQn */
+#define FMC_IRQn FSMC_IRQn
+
+/* Aliases for __IRQHandler */
+#define FMC_IRQHandler FSMC_IRQHandler
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* __STM32F407xx_H */
+
+
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Device/ST/STM32F4xx/Include/stm32f410cx.h b/Device/ST/STM32F4xx/Include/stm32f410cx.h
new file mode 100644
index 0000000..93d880d
--- /dev/null
+++ b/Device/ST/STM32F4xx/Include/stm32f410cx.h
@@ -0,0 +1,3997 @@
+/**
+ ******************************************************************************
+ * @file stm32f410cx.h
+ * @author MCD Application Team
+ * @version V2.5.0
+ * @date 22-April-2016
+ * @brief CMSIS STM32F410Cx Device Peripheral Access Layer Header File.
+ *
+ * This file contains:
+ * - Data structures and the address mapping for all peripherals
+ * - peripherals registers declarations and bits definition
+ * - Macros to access peripheral’s registers hardware
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/** @addtogroup CMSIS
+ * @{
+ */
+
+/** @addtogroup stm32f410cx
+ * @{
+ */
+
+#ifndef __STM32F410Cx_H
+#define __STM32F410Cx_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif /* __cplusplus */
+
+
+/** @addtogroup Configuration_section_for_CMSIS
+ * @{
+ */
+
+/**
+ * @brief Configuration of the Cortex-M4 Processor and Core Peripherals
+ */
+#define __CM4_REV 0x0001U /*!< Core revision r0p1 */
+#define __MPU_PRESENT 1U /*!< STM32F4XX provides an MPU */
+#define __NVIC_PRIO_BITS 4U /*!< STM32F4XX uses 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */
+#define __FPU_PRESENT 1U /*!< FPU present */
+
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_interrupt_number_definition
+ * @{
+ */
+
+/**
+ * @brief STM32F4XX Interrupt Number Definition, according to the selected device
+ * in @ref Library_configuration_section
+ */
+typedef enum
+{
+/****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/
+ NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
+ MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */
+ BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */
+ UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */
+ SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */
+ DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */
+ PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */
+ SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */
+/****** STM32 specific Interrupt Numbers **********************************************************************/
+ WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
+ PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */
+ TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */
+ RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */
+ FLASH_IRQn = 4, /*!< FLASH global Interrupt */
+ RCC_IRQn = 5, /*!< RCC global Interrupt */
+ EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */
+ EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */
+ EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */
+ EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */
+ EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */
+ DMA1_Stream0_IRQn = 11, /*!< DMA1 Stream 0 global Interrupt */
+ DMA1_Stream1_IRQn = 12, /*!< DMA1 Stream 1 global Interrupt */
+ DMA1_Stream2_IRQn = 13, /*!< DMA1 Stream 2 global Interrupt */
+ DMA1_Stream3_IRQn = 14, /*!< DMA1 Stream 3 global Interrupt */
+ DMA1_Stream4_IRQn = 15, /*!< DMA1 Stream 4 global Interrupt */
+ DMA1_Stream5_IRQn = 16, /*!< DMA1 Stream 5 global Interrupt */
+ DMA1_Stream6_IRQn = 17, /*!< DMA1 Stream 6 global Interrupt */
+ ADC_IRQn = 18, /*!< ADC1 global Interrupts */
+ EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
+ TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break interrupt and TIM9 global interrupt */
+ TIM1_UP_IRQn = 25, /*!< TIM1 Update Interrupt */
+ TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */
+ TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
+ I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
+ I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
+ I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
+ I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
+ SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
+ SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
+ USART1_IRQn = 37, /*!< USART1 global Interrupt */
+ USART2_IRQn = 38, /*!< USART2 global Interrupt */
+ EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
+ RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */
+ DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */
+ TIM5_IRQn = 50, /*!< TIM5 global Interrupt */
+ TIM6_DAC_IRQn = 54, /*!< TIM6 global Interrupt and DAC Global Interrupt */
+ DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */
+ DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */
+ DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */
+ DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */
+ DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */
+ DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */
+ DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */
+ DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */
+ USART6_IRQn = 71, /*!< USART6 global interrupt */
+ RNG_IRQn = 80, /*!< RNG global Interrupt */
+ FPU_IRQn = 81, /*!< FPU global interrupt */
+ SPI5_IRQn = 85, /*!< SPI5 global Interrupt */
+ FMPI2C1_EV_IRQn = 95, /*!< FMPI2C1 Event Interrupt */
+ FMPI2C1_ER_IRQn = 96, /*!< FMPI2C1 Error Interrupt */
+ LPTIM1_IRQn = 97 /*!< LPTIM1 interrupt */
+} IRQn_Type;
+
+/**
+ * @}
+ */
+
+#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
+#include "system_stm32f4xx.h"
+#include <stdint.h>
+
+/** @addtogroup Peripheral_registers_structures
+ * @{
+ */
+
+/**
+ * @brief Analog to Digital Converter
+ */
+
+typedef struct
+{
+ __IO uint32_t SR; /*!< ADC status register, Address offset: 0x00 */
+ __IO uint32_t CR1; /*!< ADC control register 1, Address offset: 0x04 */
+ __IO uint32_t CR2; /*!< ADC control register 2, Address offset: 0x08 */
+ __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x0C */
+ __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x10 */
+ __IO uint32_t JOFR1; /*!< ADC injected channel data offset register 1, Address offset: 0x14 */
+ __IO uint32_t JOFR2; /*!< ADC injected channel data offset register 2, Address offset: 0x18 */
+ __IO uint32_t JOFR3; /*!< ADC injected channel data offset register 3, Address offset: 0x1C */
+ __IO uint32_t JOFR4; /*!< ADC injected channel data offset register 4, Address offset: 0x20 */
+ __IO uint32_t HTR; /*!< ADC watchdog higher threshold register, Address offset: 0x24 */
+ __IO uint32_t LTR; /*!< ADC watchdog lower threshold register, Address offset: 0x28 */
+ __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x2C */
+ __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x30 */
+ __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x34 */
+ __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x38*/
+ __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x3C */
+ __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x40 */
+ __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x44 */
+ __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x48 */
+ __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x4C */
+} ADC_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1 base address + 0x300 */
+ __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1 base address + 0x304 */
+ __IO uint32_t CDR; /*!< ADC common regular data register for dual
+ AND triple modes, Address offset: ADC1 base address + 0x308 */
+} ADC_Common_TypeDef;
+
+/**
+ * @brief CRC calculation unit
+ */
+
+typedef struct
+{
+ __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
+ __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
+ uint8_t RESERVED0; /*!< Reserved, 0x05 */
+ uint16_t RESERVED1; /*!< Reserved, 0x06 */
+ __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
+} CRC_TypeDef;
+
+/**
+ * @brief Digital to Analog Converter
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */
+ __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */
+ __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
+ __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */
+ __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */
+ __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
+ __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */
+ __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */
+ __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */
+ __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */
+ __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */
+ __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */
+ __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */
+ __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */
+} DAC_TypeDef;
+
+/**
+ * @brief Debug MCU
+ */
+
+typedef struct
+{
+ __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
+ __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
+ __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */
+ __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */
+}DBGMCU_TypeDef;
+
+
+/**
+ * @brief DMA Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< DMA stream x configuration register */
+ __IO uint32_t NDTR; /*!< DMA stream x number of data register */
+ __IO uint32_t PAR; /*!< DMA stream x peripheral address register */
+ __IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */
+ __IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */
+ __IO uint32_t FCR; /*!< DMA stream x FIFO control register */
+} DMA_Stream_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t LISR; /*!< DMA low interrupt status register, Address offset: 0x00 */
+ __IO uint32_t HISR; /*!< DMA high interrupt status register, Address offset: 0x04 */
+ __IO uint32_t LIFCR; /*!< DMA low interrupt flag clear register, Address offset: 0x08 */
+ __IO uint32_t HIFCR; /*!< DMA high interrupt flag clear register, Address offset: 0x0C */
+} DMA_TypeDef;
+
+
+/**
+ * @brief External Interrupt/Event Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t IMR; /*!< EXTI Interrupt mask register, Address offset: 0x00 */
+ __IO uint32_t EMR; /*!< EXTI Event mask register, Address offset: 0x04 */
+ __IO uint32_t RTSR; /*!< EXTI Rising trigger selection register, Address offset: 0x08 */
+ __IO uint32_t FTSR; /*!< EXTI Falling trigger selection register, Address offset: 0x0C */
+ __IO uint32_t SWIER; /*!< EXTI Software interrupt event register, Address offset: 0x10 */
+ __IO uint32_t PR; /*!< EXTI Pending register, Address offset: 0x14 */
+} EXTI_TypeDef;
+
+/**
+ * @brief FLASH Registers
+ */
+
+typedef struct
+{
+ __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */
+ __IO uint32_t KEYR; /*!< FLASH key register, Address offset: 0x04 */
+ __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x08 */
+ __IO uint32_t SR; /*!< FLASH status register, Address offset: 0x0C */
+ __IO uint32_t CR; /*!< FLASH control register, Address offset: 0x10 */
+ __IO uint32_t OPTCR; /*!< FLASH option control register , Address offset: 0x14 */
+ __IO uint32_t OPTCR1; /*!< FLASH option control register 1, Address offset: 0x18 */
+} FLASH_TypeDef;
+
+/**
+ * @brief General Purpose I/O
+ */
+
+typedef struct
+{
+ __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
+ __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */
+ __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */
+ __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
+ __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
+ __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
+ __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */
+ __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
+ __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */
+} GPIO_TypeDef;
+
+/**
+ * @brief System configuration controller
+ */
+
+typedef struct
+{
+ __IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */
+ __IO uint32_t PMC; /*!< SYSCFG peripheral mode configuration register, Address offset: 0x04 */
+ __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
+ uint32_t RESERVED; /*!< Reserved, 0x18 */
+ uint32_t CFGR2; /*!< Reserved, 0x1C */
+ __IO uint32_t CMPCR; /*!< SYSCFG Compensation cell control register, Address offset: 0x20 */
+ uint32_t RESERVED1[2]; /*!< Reserved, 0x24-0x28 */
+ __IO uint32_t CFGR; /*!< SYSCFG Configuration register, Address offset: 0x2C */
+} SYSCFG_TypeDef;
+
+/**
+ * @brief Inter-integrated Circuit Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */
+ __IO uint32_t OAR1; /*!< I2C Own address register 1, Address offset: 0x08 */
+ __IO uint32_t OAR2; /*!< I2C Own address register 2, Address offset: 0x0C */
+ __IO uint32_t DR; /*!< I2C Data register, Address offset: 0x10 */
+ __IO uint32_t SR1; /*!< I2C Status register 1, Address offset: 0x14 */
+ __IO uint32_t SR2; /*!< I2C Status register 2, Address offset: 0x18 */
+ __IO uint32_t CCR; /*!< I2C Clock control register, Address offset: 0x1C */
+ __IO uint32_t TRISE; /*!< I2C TRISE register, Address offset: 0x20 */
+ __IO uint32_t FLTR; /*!< I2C FLTR register, Address offset: 0x24 */
+} I2C_TypeDef;
+
+/**
+ * @brief Inter-integrated Circuit Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t CR1; /*!< FMPI2C Control register 1, Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< FMPI2C Control register 2, Address offset: 0x04 */
+ __IO uint32_t OAR1; /*!< FMPI2C Own address 1 register, Address offset: 0x08 */
+ __IO uint32_t OAR2; /*!< FMPI2C Own address 2 register, Address offset: 0x0C */
+ __IO uint32_t TIMINGR; /*!< FMPI2C Timing register, Address offset: 0x10 */
+ __IO uint32_t TIMEOUTR; /*!< FMPI2C Timeout register, Address offset: 0x14 */
+ __IO uint32_t ISR; /*!< FMPI2C Interrupt and status register, Address offset: 0x18 */
+ __IO uint32_t ICR; /*!< FMPI2C Interrupt clear register, Address offset: 0x1C */
+ __IO uint32_t PECR; /*!< FMPI2C PEC register, Address offset: 0x20 */
+ __IO uint32_t RXDR; /*!< FMPI2C Receive data register, Address offset: 0x24 */
+ __IO uint32_t TXDR; /*!< FMPI2C Transmit data register, Address offset: 0x28 */
+} FMPI2C_TypeDef;
+
+/**
+ * @brief Independent WATCHDOG
+ */
+
+typedef struct
+{
+ __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */
+ __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */
+ __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */
+ __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */
+} IWDG_TypeDef;
+
+/**
+ * @brief Power Control
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */
+ __IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */
+} PWR_TypeDef;
+
+/**
+ * @brief Reset and Clock Control
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */
+ __IO uint32_t PLLCFGR; /*!< RCC PLL configuration register, Address offset: 0x04 */
+ __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x08 */
+ __IO uint32_t CIR; /*!< RCC clock interrupt register, Address offset: 0x0C */
+ __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x10 */
+ uint32_t RESERVED0[3]; /*!< Reserved, 0x14-0x1C */
+ __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x20 */
+ __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x24 */
+ uint32_t RESERVED1[2]; /*!< Reserved, 0x28-0x2C */
+ __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clock register, Address offset: 0x30 */
+ uint32_t RESERVED2[3]; /*!< Reserved, 0x34-0x3C */
+ __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x40 */
+ __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x44 */
+ uint32_t RESERVED3[2]; /*!< Reserved, 0x48-0x4C */
+ __IO uint32_t AHB1LPENR; /*!< RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 */
+ uint32_t RESERVED4[3]; /*!< Reserved, 0x54-0x5C */
+ __IO uint32_t APB1LPENR; /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 */
+ __IO uint32_t APB2LPENR; /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 */
+ uint32_t RESERVED5[2]; /*!< Reserved, 0x68-0x6C */
+ __IO uint32_t BDCR; /*!< RCC Backup domain control register, Address offset: 0x70 */
+ __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x74 */
+ uint32_t RESERVED6[2]; /*!< Reserved, 0x78-0x7C */
+ __IO uint32_t SSCGR; /*!< RCC spread spectrum clock generation register, Address offset: 0x80 */
+ uint32_t RESERVED7[2]; /*!< Reserved, 0x84-0x88 */
+ __IO uint32_t DCKCFGR; /*!< RCC Dedicated Clocks configuration register, Address offset: 0x8C */
+ __IO uint32_t CKGATENR; /*!< RCC Clocks Gated ENable Register, Address offset: 0x90 */
+ __IO uint32_t DCKCFGR2; /*!< RCC Dedicated Clocks configuration register 2, Address offset: 0x94 */
+
+} RCC_TypeDef;
+
+/**
+ * @brief Real-Time Clock
+ */
+
+typedef struct
+{
+ __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
+ __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */
+ __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */
+ __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */
+ __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */
+ __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */
+ __IO uint32_t CALIBR; /*!< RTC calibration register, Address offset: 0x18 */
+ __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */
+ __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */
+ __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */
+ __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */
+ __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */
+ __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */
+ __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */
+ __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */
+ __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */
+ __IO uint32_t TAFCR; /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */
+ __IO uint32_t ALRMASSR;/*!< RTC alarm A sub second register, Address offset: 0x44 */
+ __IO uint32_t ALRMBSSR;/*!< RTC alarm B sub second register, Address offset: 0x48 */
+ uint32_t RESERVED7; /*!< Reserved, 0x4C */
+ __IO uint32_t BKP0R; /*!< RTC backup register 1, Address offset: 0x50 */
+ __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */
+ __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */
+ __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */
+ __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */
+ __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */
+ __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */
+ __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */
+ __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */
+ __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */
+ __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */
+ __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */
+ __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */
+ __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */
+ __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */
+ __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */
+ __IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */
+ __IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */
+ __IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */
+ __IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */
+} RTC_TypeDef;
+
+/**
+ * @brief Serial Peripheral Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t CR1; /*!< SPI control register 1 (not used in I2S mode), Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< SPI control register 2, Address offset: 0x04 */
+ __IO uint32_t SR; /*!< SPI status register, Address offset: 0x08 */
+ __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */
+ __IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
+ __IO uint32_t RXCRCR; /*!< SPI RX CRC register (not used in I2S mode), Address offset: 0x14 */
+ __IO uint32_t TXCRCR; /*!< SPI TX CRC register (not used in I2S mode), Address offset: 0x18 */
+ __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */
+ __IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */
+} SPI_TypeDef;
+
+/**
+ * @brief TIM
+ */
+
+typedef struct
+{
+ __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
+ __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */
+ __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
+ __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
+ __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
+ __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
+ __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
+ __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
+ __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
+ __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */
+ __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
+ __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */
+ __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
+ __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
+ __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
+ __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
+ __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
+ __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
+ __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */
+ __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */
+} TIM_TypeDef;
+
+/**
+ * @brief Universal Synchronous Asynchronous Receiver Transmitter
+ */
+
+typedef struct
+{
+ __IO uint32_t SR; /*!< USART Status register, Address offset: 0x00 */
+ __IO uint32_t DR; /*!< USART Data register, Address offset: 0x04 */
+ __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x08 */
+ __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x0C */
+ __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x10 */
+ __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x14 */
+ __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x18 */
+} USART_TypeDef;
+
+/**
+ * @brief Window WATCHDOG
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
+ __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
+ __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
+} WWDG_TypeDef;
+
+
+/**
+ * @brief RNG
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */
+ __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */
+ __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */
+} RNG_TypeDef;
+
+
+/**
+ * @brief LPTIMER
+ */
+typedef struct
+{
+ __IO uint32_t ISR; /*!< LPTIM Interrupt and Status register, Address offset: 0x00 */
+ __IO uint32_t ICR; /*!< LPTIM Interrupt Clear register, Address offset: 0x04 */
+ __IO uint32_t IER; /*!< LPTIM Interrupt Enable register, Address offset: 0x08 */
+ __IO uint32_t CFGR; /*!< LPTIM Configuration register, Address offset: 0x0C */
+ __IO uint32_t CR; /*!< LPTIM Control register, Address offset: 0x10 */
+ __IO uint32_t CMP; /*!< LPTIM Compare register, Address offset: 0x14 */
+ __IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */
+ __IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */
+ __IO uint32_t OR; /*!< LPTIM Option register, Address offset: 0x20 */
+} LPTIM_TypeDef;
+
+/**
+ * @brief Peripheral_memory_map
+ */
+#define FLASH_BASE 0x08000000U /*!< FLASH(up to 1 MB) base address in the alias region */
+#define SRAM1_BASE 0x20000000U /*!< SRAM1(32 KB) base address in the alias region */
+#define PERIPH_BASE 0x40000000U /*!< Peripheral base address in the alias region */
+#define SRAM1_BB_BASE 0x22000000U /*!< SRAM1(32 KB) base address in the bit-band region */
+#define PERIPH_BB_BASE 0x42000000U /*!< Peripheral base address in the bit-band region */
+#define FLASH_END 0x0801FFFFU /*!< FLASH end address */
+
+/* Legacy defines */
+#define SRAM_BASE SRAM1_BASE
+#define SRAM_BB_BASE SRAM1_BB_BASE
+
+/*!< Peripheral memory map */
+#define APB1PERIPH_BASE PERIPH_BASE
+#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000U)
+#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000U)
+
+/*!< APB1 peripherals */
+#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00U)
+#define TIM6_BASE (APB1PERIPH_BASE + 0x1000U)
+#define LPTIM1_BASE (APB1PERIPH_BASE + 0x2400U)
+#define RTC_BASE (APB1PERIPH_BASE + 0x2800U)
+#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00U)
+#define IWDG_BASE (APB1PERIPH_BASE + 0x3000U)
+#define I2S2ext_BASE (APB1PERIPH_BASE + 0x3400U)
+#define SPI2_BASE (APB1PERIPH_BASE + 0x3800U)
+#define USART2_BASE (APB1PERIPH_BASE + 0x4400U)
+#define I2C1_BASE (APB1PERIPH_BASE + 0x5400U)
+#define I2C2_BASE (APB1PERIPH_BASE + 0x5800U)
+#define FMPI2C1_BASE (APB1PERIPH_BASE + 0x6000U)
+#define PWR_BASE (APB1PERIPH_BASE + 0x7000U)
+#define DAC_BASE (APB1PERIPH_BASE + 0x7400U)
+/*!< APB2 peripherals */
+#define TIM1_BASE (APB2PERIPH_BASE + 0x0000U)
+#define USART1_BASE (APB2PERIPH_BASE + 0x1000U)
+#define USART6_BASE (APB2PERIPH_BASE + 0x1400U)
+#define ADC1_BASE (APB2PERIPH_BASE + 0x2000U)
+#define ADC_BASE (APB2PERIPH_BASE + 0x2300U)
+#define SPI1_BASE (APB2PERIPH_BASE + 0x3000U)
+#define SYSCFG_BASE (APB2PERIPH_BASE + 0x3800U)
+#define EXTI_BASE (APB2PERIPH_BASE + 0x3C00U)
+#define TIM9_BASE (APB2PERIPH_BASE + 0x4000U)
+#define TIM11_BASE (APB2PERIPH_BASE + 0x4800U)
+#define SPI5_BASE (APB2PERIPH_BASE + 0x5000U)
+
+/*!< AHB1 peripherals */
+#define GPIOA_BASE (AHB1PERIPH_BASE + 0x0000U)
+#define GPIOB_BASE (AHB1PERIPH_BASE + 0x0400U)
+#define GPIOC_BASE (AHB1PERIPH_BASE + 0x0800U)
+#define GPIOH_BASE (AHB1PERIPH_BASE + 0x1C00U)
+#define CRC_BASE (AHB1PERIPH_BASE + 0x3000U)
+#define RCC_BASE (AHB1PERIPH_BASE + 0x3800U)
+#define FLASH_R_BASE (AHB1PERIPH_BASE + 0x3C00U)
+#define DMA1_BASE (AHB1PERIPH_BASE + 0x6000U)
+#define DMA1_Stream0_BASE (DMA1_BASE + 0x010U)
+#define DMA1_Stream1_BASE (DMA1_BASE + 0x028U)
+#define DMA1_Stream2_BASE (DMA1_BASE + 0x040U)
+#define DMA1_Stream3_BASE (DMA1_BASE + 0x058U)
+#define DMA1_Stream4_BASE (DMA1_BASE + 0x070U)
+#define DMA1_Stream5_BASE (DMA1_BASE + 0x088U)
+#define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0U)
+#define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8U)
+#define DMA2_BASE (AHB1PERIPH_BASE + 0x6400U)
+#define DMA2_Stream0_BASE (DMA2_BASE + 0x010U)
+#define DMA2_Stream1_BASE (DMA2_BASE + 0x028U)
+#define DMA2_Stream2_BASE (DMA2_BASE + 0x040U)
+#define DMA2_Stream3_BASE (DMA2_BASE + 0x058U)
+#define DMA2_Stream4_BASE (DMA2_BASE + 0x070U)
+#define DMA2_Stream5_BASE (DMA2_BASE + 0x088U)
+#define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0U)
+#define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8U)
+#define RNG_BASE (PERIPH_BASE + 0x80000U)
+
+/* Debug MCU registers base address */
+#define DBGMCU_BASE 0xE0042000U
+
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_declaration
+ * @{
+ */
+#define TIM5 ((TIM_TypeDef *) TIM5_BASE)
+#define TIM6 ((TIM_TypeDef *) TIM6_BASE)
+#define RTC ((RTC_TypeDef *) RTC_BASE)
+#define WWDG ((WWDG_TypeDef *) WWDG_BASE)
+#define IWDG ((IWDG_TypeDef *) IWDG_BASE)
+#define SPI2 ((SPI_TypeDef *) SPI2_BASE)
+#define USART2 ((USART_TypeDef *) USART2_BASE)
+#define I2C1 ((I2C_TypeDef *) I2C1_BASE)
+#define I2C2 ((I2C_TypeDef *) I2C2_BASE)
+#define FMPI2C1 ((FMPI2C_TypeDef *) FMPI2C1_BASE)
+#define LPTIM1 ((LPTIM_TypeDef *) LPTIM1_BASE)
+#define PWR ((PWR_TypeDef *) PWR_BASE)
+#define DAC ((DAC_TypeDef *) DAC_BASE)
+#define TIM1 ((TIM_TypeDef *) TIM1_BASE)
+#define USART1 ((USART_TypeDef *) USART1_BASE)
+#define USART6 ((USART_TypeDef *) USART6_BASE)
+#define ADC ((ADC_Common_TypeDef *) ADC_BASE)
+#define ADC1 ((ADC_TypeDef *) ADC1_BASE)
+#define SPI1 ((SPI_TypeDef *) SPI1_BASE)
+#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
+#define EXTI ((EXTI_TypeDef *) EXTI_BASE)
+#define TIM9 ((TIM_TypeDef *) TIM9_BASE)
+#define TIM11 ((TIM_TypeDef *) TIM11_BASE)
+#define SPI5 ((SPI_TypeDef *) SPI5_BASE)
+#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
+#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
+#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
+#define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
+#define CRC ((CRC_TypeDef *) CRC_BASE)
+#define RCC ((RCC_TypeDef *) RCC_BASE)
+#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
+#define DMA1 ((DMA_TypeDef *) DMA1_BASE)
+#define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)
+#define DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)
+#define DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)
+#define DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)
+#define DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)
+#define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)
+#define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)
+#define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)
+#define DMA2 ((DMA_TypeDef *) DMA2_BASE)
+#define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)
+#define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
+#define DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)
+#define DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)
+#define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)
+#define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)
+#define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)
+#define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)
+#define RNG ((RNG_TypeDef *) RNG_BASE)
+
+#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
+
+/**
+ * @}
+ */
+
+/** @addtogroup Exported_constants
+ * @{
+ */
+
+ /** @addtogroup Peripheral_Registers_Bits_Definition
+ * @{
+ */
+
+/******************************************************************************/
+/* Peripheral Registers_Bits_Definition */
+/******************************************************************************/
+
+/******************************************************************************/
+/* */
+/* Analog to Digital Converter */
+/* */
+/******************************************************************************/
+/******************** Bit definition for ADC_SR register ********************/
+#define ADC_SR_AWD 0x00000001U /*!<Analog watchdog flag */
+#define ADC_SR_EOC 0x00000002U /*!<End of conversion */
+#define ADC_SR_JEOC 0x00000004U /*!<Injected channel end of conversion */
+#define ADC_SR_JSTRT 0x00000008U /*!<Injected channel Start flag */
+#define ADC_SR_STRT 0x00000010U /*!<Regular channel Start flag */
+#define ADC_SR_OVR 0x00000020U /*!<Overrun flag */
+
+/******************* Bit definition for ADC_CR1 register ********************/
+#define ADC_CR1_AWDCH 0x0000001FU /*!<AWDCH[4:0] bits (Analog watchdog channel select bits) */
+#define ADC_CR1_AWDCH_0 0x00000001U /*!<Bit 0 */
+#define ADC_CR1_AWDCH_1 0x00000002U /*!<Bit 1 */
+#define ADC_CR1_AWDCH_2 0x00000004U /*!<Bit 2 */
+#define ADC_CR1_AWDCH_3 0x00000008U /*!<Bit 3 */
+#define ADC_CR1_AWDCH_4 0x00000010U /*!<Bit 4 */
+#define ADC_CR1_EOCIE 0x00000020U /*!<Interrupt enable for EOC */
+#define ADC_CR1_AWDIE 0x00000040U /*!<AAnalog Watchdog interrupt enable */
+#define ADC_CR1_JEOCIE 0x00000080U /*!<Interrupt enable for injected channels */
+#define ADC_CR1_SCAN 0x00000100U /*!<Scan mode */
+#define ADC_CR1_AWDSGL 0x00000200U /*!<Enable the watchdog on a single channel in scan mode */
+#define ADC_CR1_JAUTO 0x00000400U /*!<Automatic injected group conversion */
+#define ADC_CR1_DISCEN 0x00000800U /*!<Discontinuous mode on regular channels */
+#define ADC_CR1_JDISCEN 0x00001000U /*!<Discontinuous mode on injected channels */
+#define ADC_CR1_DISCNUM 0x0000E000U /*!<DISCNUM[2:0] bits (Discontinuous mode channel count) */
+#define ADC_CR1_DISCNUM_0 0x00002000U /*!<Bit 0 */
+#define ADC_CR1_DISCNUM_1 0x00004000U /*!<Bit 1 */
+#define ADC_CR1_DISCNUM_2 0x00008000U /*!<Bit 2 */
+#define ADC_CR1_JAWDEN 0x00400000U /*!<Analog watchdog enable on injected channels */
+#define ADC_CR1_AWDEN 0x00800000U /*!<Analog watchdog enable on regular channels */
+#define ADC_CR1_RES 0x03000000U /*!<RES[2:0] bits (Resolution) */
+#define ADC_CR1_RES_0 0x01000000U /*!<Bit 0 */
+#define ADC_CR1_RES_1 0x02000000U /*!<Bit 1 */
+#define ADC_CR1_OVRIE 0x04000000U /*!<overrun interrupt enable */
+
+/******************* Bit definition for ADC_CR2 register ********************/
+#define ADC_CR2_ADON 0x00000001U /*!<A/D Converter ON / OFF */
+#define ADC_CR2_CONT 0x00000002U /*!<Continuous Conversion */
+#define ADC_CR2_DMA 0x00000100U /*!<Direct Memory access mode */
+#define ADC_CR2_DDS 0x00000200U /*!<DMA disable selection (Single ADC) */
+#define ADC_CR2_EOCS 0x00000400U /*!<End of conversion selection */
+#define ADC_CR2_ALIGN 0x00000800U /*!<Data Alignment */
+#define ADC_CR2_JEXTSEL 0x000F0000U /*!<JEXTSEL[3:0] bits (External event select for injected group) */
+#define ADC_CR2_JEXTSEL_0 0x00010000U /*!<Bit 0 */
+#define ADC_CR2_JEXTSEL_1 0x00020000U /*!<Bit 1 */
+#define ADC_CR2_JEXTSEL_2 0x00040000U /*!<Bit 2 */
+#define ADC_CR2_JEXTSEL_3 0x00080000U /*!<Bit 3 */
+#define ADC_CR2_JEXTEN 0x00300000U /*!<JEXTEN[1:0] bits (External Trigger Conversion mode for injected channelsp) */
+#define ADC_CR2_JEXTEN_0 0x00100000U /*!<Bit 0 */
+#define ADC_CR2_JEXTEN_1 0x00200000U /*!<Bit 1 */
+#define ADC_CR2_JSWSTART 0x00400000U /*!<Start Conversion of injected channels */
+#define ADC_CR2_EXTSEL 0x0F000000U /*!<EXTSEL[3:0] bits (External Event Select for regular group) */
+#define ADC_CR2_EXTSEL_0 0x01000000U /*!<Bit 0 */
+#define ADC_CR2_EXTSEL_1 0x02000000U /*!<Bit 1 */
+#define ADC_CR2_EXTSEL_2 0x04000000U /*!<Bit 2 */
+#define ADC_CR2_EXTSEL_3 0x08000000U /*!<Bit 3 */
+#define ADC_CR2_EXTEN 0x30000000U /*!<EXTEN[1:0] bits (External Trigger Conversion mode for regular channelsp) */
+#define ADC_CR2_EXTEN_0 0x10000000U /*!<Bit 0 */
+#define ADC_CR2_EXTEN_1 0x20000000U /*!<Bit 1 */
+#define ADC_CR2_SWSTART 0x40000000U /*!<Start Conversion of regular channels */
+
+/****************** Bit definition for ADC_SMPR1 register *******************/
+#define ADC_SMPR1_SMP10 0x00000007U /*!<SMP10[2:0] bits (Channel 10 Sample time selection) */
+#define ADC_SMPR1_SMP10_0 0x00000001U /*!<Bit 0 */
+#define ADC_SMPR1_SMP10_1 0x00000002U /*!<Bit 1 */
+#define ADC_SMPR1_SMP10_2 0x00000004U /*!<Bit 2 */
+#define ADC_SMPR1_SMP11 0x00000038U /*!<SMP11[2:0] bits (Channel 11 Sample time selection) */
+#define ADC_SMPR1_SMP11_0 0x00000008U /*!<Bit 0 */
+#define ADC_SMPR1_SMP11_1 0x00000010U /*!<Bit 1 */
+#define ADC_SMPR1_SMP11_2 0x00000020U /*!<Bit 2 */
+#define ADC_SMPR1_SMP12 0x000001C0U /*!<SMP12[2:0] bits (Channel 12 Sample time selection) */
+#define ADC_SMPR1_SMP12_0 0x00000040U /*!<Bit 0 */
+#define ADC_SMPR1_SMP12_1 0x00000080U /*!<Bit 1 */
+#define ADC_SMPR1_SMP12_2 0x00000100U /*!<Bit 2 */
+#define ADC_SMPR1_SMP13 0x00000E00U /*!<SMP13[2:0] bits (Channel 13 Sample time selection) */
+#define ADC_SMPR1_SMP13_0 0x00000200U /*!<Bit 0 */
+#define ADC_SMPR1_SMP13_1 0x00000400U /*!<Bit 1 */
+#define ADC_SMPR1_SMP13_2 0x00000800U /*!<Bit 2 */
+#define ADC_SMPR1_SMP14 0x00007000U /*!<SMP14[2:0] bits (Channel 14 Sample time selection) */
+#define ADC_SMPR1_SMP14_0 0x00001000U /*!<Bit 0 */
+#define ADC_SMPR1_SMP14_1 0x00002000U /*!<Bit 1 */
+#define ADC_SMPR1_SMP14_2 0x00004000U /*!<Bit 2 */
+#define ADC_SMPR1_SMP15 0x00038000U /*!<SMP15[2:0] bits (Channel 15 Sample time selection) */
+#define ADC_SMPR1_SMP15_0 0x00008000U /*!<Bit 0 */
+#define ADC_SMPR1_SMP15_1 0x00010000U /*!<Bit 1 */
+#define ADC_SMPR1_SMP15_2 0x00020000U /*!<Bit 2 */
+#define ADC_SMPR1_SMP16 0x001C0000U /*!<SMP16[2:0] bits (Channel 16 Sample time selection) */
+#define ADC_SMPR1_SMP16_0 0x00040000U /*!<Bit 0 */
+#define ADC_SMPR1_SMP16_1 0x00080000U /*!<Bit 1 */
+#define ADC_SMPR1_SMP16_2 0x00100000U /*!<Bit 2 */
+#define ADC_SMPR1_SMP17 0x00E00000U /*!<SMP17[2:0] bits (Channel 17 Sample time selection) */
+#define ADC_SMPR1_SMP17_0 0x00200000U /*!<Bit 0 */
+#define ADC_SMPR1_SMP17_1 0x00400000U /*!<Bit 1 */
+#define ADC_SMPR1_SMP17_2 0x00800000U /*!<Bit 2 */
+#define ADC_SMPR1_SMP18 0x07000000U /*!<SMP18[2:0] bits (Channel 18 Sample time selection) */
+#define ADC_SMPR1_SMP18_0 0x01000000U /*!<Bit 0 */
+#define ADC_SMPR1_SMP18_1 0x02000000U /*!<Bit 1 */
+#define ADC_SMPR1_SMP18_2 0x04000000U /*!<Bit 2 */
+
+/****************** Bit definition for ADC_SMPR2 register *******************/
+#define ADC_SMPR2_SMP0 0x00000007U /*!<SMP0[2:0] bits (Channel 0 Sample time selection) */
+#define ADC_SMPR2_SMP0_0 0x00000001U /*!<Bit 0 */
+#define ADC_SMPR2_SMP0_1 0x00000002U /*!<Bit 1 */
+#define ADC_SMPR2_SMP0_2 0x00000004U /*!<Bit 2 */
+#define ADC_SMPR2_SMP1 0x00000038U /*!<SMP1[2:0] bits (Channel 1 Sample time selection) */
+#define ADC_SMPR2_SMP1_0 0x00000008U /*!<Bit 0 */
+#define ADC_SMPR2_SMP1_1 0x00000010U /*!<Bit 1 */
+#define ADC_SMPR2_SMP1_2 0x00000020U /*!<Bit 2 */
+#define ADC_SMPR2_SMP2 0x000001C0U /*!<SMP2[2:0] bits (Channel 2 Sample time selection) */
+#define ADC_SMPR2_SMP2_0 0x00000040U /*!<Bit 0 */
+#define ADC_SMPR2_SMP2_1 0x00000080U /*!<Bit 1 */
+#define ADC_SMPR2_SMP2_2 0x00000100U /*!<Bit 2 */
+#define ADC_SMPR2_SMP3 0x00000E00U /*!<SMP3[2:0] bits (Channel 3 Sample time selection) */
+#define ADC_SMPR2_SMP3_0 0x00000200U /*!<Bit 0 */
+#define ADC_SMPR2_SMP3_1 0x00000400U /*!<Bit 1 */
+#define ADC_SMPR2_SMP3_2 0x00000800U /*!<Bit 2 */
+#define ADC_SMPR2_SMP4 0x00007000U /*!<SMP4[2:0] bits (Channel 4 Sample time selection) */
+#define ADC_SMPR2_SMP4_0 0x00001000U /*!<Bit 0 */
+#define ADC_SMPR2_SMP4_1 0x00002000U /*!<Bit 1 */
+#define ADC_SMPR2_SMP4_2 0x00004000U /*!<Bit 2 */
+#define ADC_SMPR2_SMP5 0x00038000U /*!<SMP5[2:0] bits (Channel 5 Sample time selection) */
+#define ADC_SMPR2_SMP5_0 0x00008000U /*!<Bit 0 */
+#define ADC_SMPR2_SMP5_1 0x00010000U /*!<Bit 1 */
+#define ADC_SMPR2_SMP5_2 0x00020000U /*!<Bit 2 */
+#define ADC_SMPR2_SMP6 0x001C0000U /*!<SMP6[2:0] bits (Channel 6 Sample time selection) */
+#define ADC_SMPR2_SMP6_0 0x00040000U /*!<Bit 0 */
+#define ADC_SMPR2_SMP6_1 0x00080000U /*!<Bit 1 */
+#define ADC_SMPR2_SMP6_2 0x00100000U /*!<Bit 2 */
+#define ADC_SMPR2_SMP7 0x00E00000U /*!<SMP7[2:0] bits (Channel 7 Sample time selection) */
+#define ADC_SMPR2_SMP7_0 0x00200000U /*!<Bit 0 */
+#define ADC_SMPR2_SMP7_1 0x00400000U /*!<Bit 1 */
+#define ADC_SMPR2_SMP7_2 0x00800000U /*!<Bit 2 */
+#define ADC_SMPR2_SMP8 0x07000000U /*!<SMP8[2:0] bits (Channel 8 Sample time selection) */
+#define ADC_SMPR2_SMP8_0 0x01000000U /*!<Bit 0 */
+#define ADC_SMPR2_SMP8_1 0x02000000U /*!<Bit 1 */
+#define ADC_SMPR2_SMP8_2 0x04000000U /*!<Bit 2 */
+#define ADC_SMPR2_SMP9 0x38000000U /*!<SMP9[2:0] bits (Channel 9 Sample time selection) */
+#define ADC_SMPR2_SMP9_0 0x08000000U /*!<Bit 0 */
+#define ADC_SMPR2_SMP9_1 0x10000000U /*!<Bit 1 */
+#define ADC_SMPR2_SMP9_2 0x20000000U /*!<Bit 2 */
+
+/****************** Bit definition for ADC_JOFR1 register *******************/
+#define ADC_JOFR1_JOFFSET1 0x0FFFU /*!<Data offset for injected channel 1 */
+
+/****************** Bit definition for ADC_JOFR2 register *******************/
+#define ADC_JOFR2_JOFFSET2 0x0FFFU /*!<Data offset for injected channel 2 */
+
+/****************** Bit definition for ADC_JOFR3 register *******************/
+#define ADC_JOFR3_JOFFSET3 0x0FFFU /*!<Data offset for injected channel 3 */
+
+/****************** Bit definition for ADC_JOFR4 register *******************/
+#define ADC_JOFR4_JOFFSET4 0x0FFFU /*!<Data offset for injected channel 4 */
+
+/******************* Bit definition for ADC_HTR register ********************/
+#define ADC_HTR_HT 0x0FFFU /*!<Analog watchdog high threshold */
+
+/******************* Bit definition for ADC_LTR register ********************/
+#define ADC_LTR_LT 0x0FFFU /*!<Analog watchdog low threshold */
+
+/******************* Bit definition for ADC_SQR1 register *******************/
+#define ADC_SQR1_SQ13 0x0000001FU /*!<SQ13[4:0] bits (13th conversion in regular sequence) */
+#define ADC_SQR1_SQ13_0 0x00000001U /*!<Bit 0 */
+#define ADC_SQR1_SQ13_1 0x00000002U /*!<Bit 1 */
+#define ADC_SQR1_SQ13_2 0x00000004U /*!<Bit 2 */
+#define ADC_SQR1_SQ13_3 0x00000008U /*!<Bit 3 */
+#define ADC_SQR1_SQ13_4 0x00000010U /*!<Bit 4 */
+#define ADC_SQR1_SQ14 0x000003E0U /*!<SQ14[4:0] bits (14th conversion in regular sequence) */
+#define ADC_SQR1_SQ14_0 0x00000020U /*!<Bit 0 */
+#define ADC_SQR1_SQ14_1 0x00000040U /*!<Bit 1 */
+#define ADC_SQR1_SQ14_2 0x00000080U /*!<Bit 2 */
+#define ADC_SQR1_SQ14_3 0x00000100U /*!<Bit 3 */
+#define ADC_SQR1_SQ14_4 0x00000200U /*!<Bit 4 */
+#define ADC_SQR1_SQ15 0x00007C00U /*!<SQ15[4:0] bits (15th conversion in regular sequence) */
+#define ADC_SQR1_SQ15_0 0x00000400U /*!<Bit 0 */
+#define ADC_SQR1_SQ15_1 0x00000800U /*!<Bit 1 */
+#define ADC_SQR1_SQ15_2 0x00001000U /*!<Bit 2 */
+#define ADC_SQR1_SQ15_3 0x00002000U /*!<Bit 3 */
+#define ADC_SQR1_SQ15_4 0x00004000U /*!<Bit 4 */
+#define ADC_SQR1_SQ16 0x000F8000U /*!<SQ16[4:0] bits (16th conversion in regular sequence) */
+#define ADC_SQR1_SQ16_0 0x00008000U /*!<Bit 0 */
+#define ADC_SQR1_SQ16_1 0x00010000U /*!<Bit 1 */
+#define ADC_SQR1_SQ16_2 0x00020000U /*!<Bit 2 */
+#define ADC_SQR1_SQ16_3 0x00040000U /*!<Bit 3 */
+#define ADC_SQR1_SQ16_4 0x00080000U /*!<Bit 4 */
+#define ADC_SQR1_L 0x00F00000U /*!<L[3:0] bits (Regular channel sequence length) */
+#define ADC_SQR1_L_0 0x00100000U /*!<Bit 0 */
+#define ADC_SQR1_L_1 0x00200000U /*!<Bit 1 */
+#define ADC_SQR1_L_2 0x00400000U /*!<Bit 2 */
+#define ADC_SQR1_L_3 0x00800000U /*!<Bit 3 */
+
+/******************* Bit definition for ADC_SQR2 register *******************/
+#define ADC_SQR2_SQ7 0x0000001FU /*!<SQ7[4:0] bits (7th conversion in regular sequence) */
+#define ADC_SQR2_SQ7_0 0x00000001U /*!<Bit 0 */
+#define ADC_SQR2_SQ7_1 0x00000002U /*!<Bit 1 */
+#define ADC_SQR2_SQ7_2 0x00000004U /*!<Bit 2 */
+#define ADC_SQR2_SQ7_3 0x00000008U /*!<Bit 3 */
+#define ADC_SQR2_SQ7_4 0x00000010U /*!<Bit 4 */
+#define ADC_SQR2_SQ8 0x000003E0U /*!<SQ8[4:0] bits (8th conversion in regular sequence) */
+#define ADC_SQR2_SQ8_0 0x00000020U /*!<Bit 0 */
+#define ADC_SQR2_SQ8_1 0x00000040U /*!<Bit 1 */
+#define ADC_SQR2_SQ8_2 0x00000080U /*!<Bit 2 */
+#define ADC_SQR2_SQ8_3 0x00000100U /*!<Bit 3 */
+#define ADC_SQR2_SQ8_4 0x00000200U /*!<Bit 4 */
+#define ADC_SQR2_SQ9 0x00007C00U /*!<SQ9[4:0] bits (9th conversion in regular sequence) */
+#define ADC_SQR2_SQ9_0 0x00000400U /*!<Bit 0 */
+#define ADC_SQR2_SQ9_1 0x00000800U /*!<Bit 1 */
+#define ADC_SQR2_SQ9_2 0x00001000U /*!<Bit 2 */
+#define ADC_SQR2_SQ9_3 0x00002000U /*!<Bit 3 */
+#define ADC_SQR2_SQ9_4 0x00004000U /*!<Bit 4 */
+#define ADC_SQR2_SQ10 0x000F8000U /*!<SQ10[4:0] bits (10th conversion in regular sequence) */
+#define ADC_SQR2_SQ10_0 0x00008000U /*!<Bit 0 */
+#define ADC_SQR2_SQ10_1 0x00010000U /*!<Bit 1 */
+#define ADC_SQR2_SQ10_2 0x00020000U /*!<Bit 2 */
+#define ADC_SQR2_SQ10_3 0x00040000U /*!<Bit 3 */
+#define ADC_SQR2_SQ10_4 0x00080000U /*!<Bit 4 */
+#define ADC_SQR2_SQ11 0x01F00000U /*!<SQ11[4:0] bits (11th conversion in regular sequence) */
+#define ADC_SQR2_SQ11_0 0x00100000U /*!<Bit 0 */
+#define ADC_SQR2_SQ11_1 0x00200000U /*!<Bit 1 */
+#define ADC_SQR2_SQ11_2 0x00400000U /*!<Bit 2 */
+#define ADC_SQR2_SQ11_3 0x00800000U /*!<Bit 3 */
+#define ADC_SQR2_SQ11_4 0x01000000U /*!<Bit 4 */
+#define ADC_SQR2_SQ12 0x3E000000U /*!<SQ12[4:0] bits (12th conversion in regular sequence) */
+#define ADC_SQR2_SQ12_0 0x02000000U /*!<Bit 0 */
+#define ADC_SQR2_SQ12_1 0x04000000U /*!<Bit 1 */
+#define ADC_SQR2_SQ12_2 0x08000000U /*!<Bit 2 */
+#define ADC_SQR2_SQ12_3 0x10000000U /*!<Bit 3 */
+#define ADC_SQR2_SQ12_4 0x20000000U /*!<Bit 4 */
+
+/******************* Bit definition for ADC_SQR3 register *******************/
+#define ADC_SQR3_SQ1 0x0000001FU /*!<SQ1[4:0] bits (1st conversion in regular sequence) */
+#define ADC_SQR3_SQ1_0 0x00000001U /*!<Bit 0 */
+#define ADC_SQR3_SQ1_1 0x00000002U /*!<Bit 1 */
+#define ADC_SQR3_SQ1_2 0x00000004U /*!<Bit 2 */
+#define ADC_SQR3_SQ1_3 0x00000008U /*!<Bit 3 */
+#define ADC_SQR3_SQ1_4 0x00000010U /*!<Bit 4 */
+#define ADC_SQR3_SQ2 0x000003E0U /*!<SQ2[4:0] bits (2nd conversion in regular sequence) */
+#define ADC_SQR3_SQ2_0 0x00000020U /*!<Bit 0 */
+#define ADC_SQR3_SQ2_1 0x00000040U /*!<Bit 1 */
+#define ADC_SQR3_SQ2_2 0x00000080U /*!<Bit 2 */
+#define ADC_SQR3_SQ2_3 0x00000100U /*!<Bit 3 */
+#define ADC_SQR3_SQ2_4 0x00000200U /*!<Bit 4 */
+#define ADC_SQR3_SQ3 0x00007C00U /*!<SQ3[4:0] bits (3rd conversion in regular sequence) */
+#define ADC_SQR3_SQ3_0 0x00000400U /*!<Bit 0 */
+#define ADC_SQR3_SQ3_1 0x00000800U /*!<Bit 1 */
+#define ADC_SQR3_SQ3_2 0x00001000U /*!<Bit 2 */
+#define ADC_SQR3_SQ3_3 0x00002000U /*!<Bit 3 */
+#define ADC_SQR3_SQ3_4 0x00004000U /*!<Bit 4 */
+#define ADC_SQR3_SQ4 0x000F8000U /*!<SQ4[4:0] bits (4th conversion in regular sequence) */
+#define ADC_SQR3_SQ4_0 0x00008000U /*!<Bit 0 */
+#define ADC_SQR3_SQ4_1 0x00010000U /*!<Bit 1 */
+#define ADC_SQR3_SQ4_2 0x00020000U /*!<Bit 2 */
+#define ADC_SQR3_SQ4_3 0x00040000U /*!<Bit 3 */
+#define ADC_SQR3_SQ4_4 0x00080000U /*!<Bit 4 */
+#define ADC_SQR3_SQ5 0x01F00000U /*!<SQ5[4:0] bits (5th conversion in regular sequence) */
+#define ADC_SQR3_SQ5_0 0x00100000U /*!<Bit 0 */
+#define ADC_SQR3_SQ5_1 0x00200000U /*!<Bit 1 */
+#define ADC_SQR3_SQ5_2 0x00400000U /*!<Bit 2 */
+#define ADC_SQR3_SQ5_3 0x00800000U /*!<Bit 3 */
+#define ADC_SQR3_SQ5_4 0x01000000U /*!<Bit 4 */
+#define ADC_SQR3_SQ6 0x3E000000U /*!<SQ6[4:0] bits (6th conversion in regular sequence) */
+#define ADC_SQR3_SQ6_0 0x02000000U /*!<Bit 0 */
+#define ADC_SQR3_SQ6_1 0x04000000U /*!<Bit 1 */
+#define ADC_SQR3_SQ6_2 0x08000000U /*!<Bit 2 */
+#define ADC_SQR3_SQ6_3 0x10000000U /*!<Bit 3 */
+#define ADC_SQR3_SQ6_4 0x20000000U /*!<Bit 4 */
+
+/******************* Bit definition for ADC_JSQR register *******************/
+#define ADC_JSQR_JSQ1 0x0000001FU /*!<JSQ1[4:0] bits (1st conversion in injected sequence) */
+#define ADC_JSQR_JSQ1_0 0x00000001U /*!<Bit 0 */
+#define ADC_JSQR_JSQ1_1 0x00000002U /*!<Bit 1 */
+#define ADC_JSQR_JSQ1_2 0x00000004U /*!<Bit 2 */
+#define ADC_JSQR_JSQ1_3 0x00000008U /*!<Bit 3 */
+#define ADC_JSQR_JSQ1_4 0x00000010U /*!<Bit 4 */
+#define ADC_JSQR_JSQ2 0x000003E0U /*!<JSQ2[4:0] bits (2nd conversion in injected sequence) */
+#define ADC_JSQR_JSQ2_0 0x00000020U /*!<Bit 0 */
+#define ADC_JSQR_JSQ2_1 0x00000040U /*!<Bit 1 */
+#define ADC_JSQR_JSQ2_2 0x00000080U /*!<Bit 2 */
+#define ADC_JSQR_JSQ2_3 0x00000100U /*!<Bit 3 */
+#define ADC_JSQR_JSQ2_4 0x00000200U /*!<Bit 4 */
+#define ADC_JSQR_JSQ3 0x00007C00U /*!<JSQ3[4:0] bits (3rd conversion in injected sequence) */
+#define ADC_JSQR_JSQ3_0 0x00000400U /*!<Bit 0 */
+#define ADC_JSQR_JSQ3_1 0x00000800U /*!<Bit 1 */
+#define ADC_JSQR_JSQ3_2 0x00001000U /*!<Bit 2 */
+#define ADC_JSQR_JSQ3_3 0x00002000U /*!<Bit 3 */
+#define ADC_JSQR_JSQ3_4 0x00004000U /*!<Bit 4 */
+#define ADC_JSQR_JSQ4 0x000F8000U /*!<JSQ4[4:0] bits (4th conversion in injected sequence) */
+#define ADC_JSQR_JSQ4_0 0x00008000U /*!<Bit 0 */
+#define ADC_JSQR_JSQ4_1 0x00010000U /*!<Bit 1 */
+#define ADC_JSQR_JSQ4_2 0x00020000U /*!<Bit 2 */
+#define ADC_JSQR_JSQ4_3 0x00040000U /*!<Bit 3 */
+#define ADC_JSQR_JSQ4_4 0x00080000U /*!<Bit 4 */
+#define ADC_JSQR_JL 0x00300000U /*!<JL[1:0] bits (Injected Sequence length) */
+#define ADC_JSQR_JL_0 0x00100000U /*!<Bit 0 */
+#define ADC_JSQR_JL_1 0x00200000U /*!<Bit 1 */
+
+/******************* Bit definition for ADC_JDR1 register *******************/
+#define ADC_JDR1_JDATA 0xFFFFU /*!<Injected data */
+
+/******************* Bit definition for ADC_JDR2 register *******************/
+#define ADC_JDR2_JDATA 0xFFFFU /*!<Injected data */
+
+/******************* Bit definition for ADC_JDR3 register *******************/
+#define ADC_JDR3_JDATA 0xFFFFU /*!<Injected data */
+
+/******************* Bit definition for ADC_JDR4 register *******************/
+#define ADC_JDR4_JDATA 0xFFFFU /*!<Injected data */
+
+/******************** Bit definition for ADC_DR register ********************/
+#define ADC_DR_DATA 0x0000FFFFU /*!<Regular data */
+#define ADC_DR_ADC2DATA 0xFFFF0000U /*!<ADC2 data */
+
+/******************* Bit definition for ADC_CSR register ********************/
+#define ADC_CSR_AWD1 0x00000001U /*!<ADC1 Analog watchdog flag */
+#define ADC_CSR_EOC1 0x00000002U /*!<ADC1 End of conversion */
+#define ADC_CSR_JEOC1 0x00000004U /*!<ADC1 Injected channel end of conversion */
+#define ADC_CSR_JSTRT1 0x00000008U /*!<ADC1 Injected channel Start flag */
+#define ADC_CSR_STRT1 0x00000010U /*!<ADC1 Regular channel Start flag */
+#define ADC_CSR_OVR1 0x00000020U /*!<ADC1 DMA overrun flag */
+#define ADC_CSR_AWD2 0x00000100U /*!<ADC2 Analog watchdog flag */
+#define ADC_CSR_EOC2 0x00000200U /*!<ADC2 End of conversion */
+#define ADC_CSR_JEOC2 0x00000400U /*!<ADC2 Injected channel end of conversion */
+#define ADC_CSR_JSTRT2 0x00000800U /*!<ADC2 Injected channel Start flag */
+#define ADC_CSR_STRT2 0x00001000U /*!<ADC2 Regular channel Start flag */
+#define ADC_CSR_OVR2 0x00002000U /*!<ADC2 DMA overrun flag */
+#define ADC_CSR_AWD3 0x00010000U /*!<ADC3 Analog watchdog flag */
+#define ADC_CSR_EOC3 0x00020000U /*!<ADC3 End of conversion */
+#define ADC_CSR_JEOC3 0x00040000U /*!<ADC3 Injected channel end of conversion */
+#define ADC_CSR_JSTRT3 0x00080000U /*!<ADC3 Injected channel Start flag */
+#define ADC_CSR_STRT3 0x00100000U /*!<ADC3 Regular channel Start flag */
+#define ADC_CSR_OVR3 0x00200000U /*!<ADC3 DMA overrun flag */
+
+/* Legacy defines */
+#define ADC_CSR_DOVR1 ADC_CSR_OVR1
+#define ADC_CSR_DOVR2 ADC_CSR_OVR2
+#define ADC_CSR_DOVR3 ADC_CSR_OVR3
+
+/******************* Bit definition for ADC_CCR register ********************/
+#define ADC_CCR_MULTI 0x0000001FU /*!<MULTI[4:0] bits (Multi-ADC mode selection) */
+#define ADC_CCR_MULTI_0 0x00000001U /*!<Bit 0 */
+#define ADC_CCR_MULTI_1 0x00000002U /*!<Bit 1 */
+#define ADC_CCR_MULTI_2 0x00000004U /*!<Bit 2 */
+#define ADC_CCR_MULTI_3 0x00000008U /*!<Bit 3 */
+#define ADC_CCR_MULTI_4 0x00000010U /*!<Bit 4 */
+#define ADC_CCR_DELAY 0x00000F00U /*!<DELAY[3:0] bits (Delay between 2 sampling phases) */
+#define ADC_CCR_DELAY_0 0x00000100U /*!<Bit 0 */
+#define ADC_CCR_DELAY_1 0x00000200U /*!<Bit 1 */
+#define ADC_CCR_DELAY_2 0x00000400U /*!<Bit 2 */
+#define ADC_CCR_DELAY_3 0x00000800U /*!<Bit 3 */
+#define ADC_CCR_DDS 0x00002000U /*!<DMA disable selection (Multi-ADC mode) */
+#define ADC_CCR_DMA 0x0000C000U /*!<DMA[1:0] bits (Direct Memory Access mode for multimode) */
+#define ADC_CCR_DMA_0 0x00004000U /*!<Bit 0 */
+#define ADC_CCR_DMA_1 0x00008000U /*!<Bit 1 */
+#define ADC_CCR_ADCPRE 0x00030000U /*!<ADCPRE[1:0] bits (ADC prescaler) */
+#define ADC_CCR_ADCPRE_0 0x00010000U /*!<Bit 0 */
+#define ADC_CCR_ADCPRE_1 0x00020000U /*!<Bit 1 */
+#define ADC_CCR_VBATE 0x00400000U /*!<VBAT Enable */
+#define ADC_CCR_TSVREFE 0x00800000U /*!<Temperature Sensor and VREFINT Enable */
+
+/******************* Bit definition for ADC_CDR register ********************/
+#define ADC_CDR_DATA1 0x0000FFFFU /*!<1st data of a pair of regular conversions */
+#define ADC_CDR_DATA2 0xFFFF0000U /*!<2nd data of a pair of regular conversions */
+
+/******************************************************************************/
+/* */
+/* CRC calculation unit */
+/* */
+/******************************************************************************/
+/******************* Bit definition for CRC_DR register *********************/
+#define CRC_DR_DR 0xFFFFFFFFU /*!< Data register bits */
+
+
+/******************* Bit definition for CRC_IDR register ********************/
+#define CRC_IDR_IDR 0xFFU /*!< General-purpose 8-bit data register bits */
+
+
+/******************** Bit definition for CRC_CR register ********************/
+#define CRC_CR_RESET 0x01U /*!< RESET bit */
+
+/******************************************************************************/
+/* */
+/* Debug MCU */
+/* */
+/******************************************************************************/
+
+/******************************************************************************/
+/* */
+/* DMA Controller */
+/* */
+/******************************************************************************/
+/******************** Bits definition for DMA_SxCR register *****************/
+#define DMA_SxCR_CHSEL 0x0E000000U
+#define DMA_SxCR_CHSEL_0 0x02000000U
+#define DMA_SxCR_CHSEL_1 0x04000000U
+#define DMA_SxCR_CHSEL_2 0x08000000U
+#define DMA_SxCR_MBURST 0x01800000U
+#define DMA_SxCR_MBURST_0 0x00800000U
+#define DMA_SxCR_MBURST_1 0x01000000U
+#define DMA_SxCR_PBURST 0x00600000U
+#define DMA_SxCR_PBURST_0 0x00200000U
+#define DMA_SxCR_PBURST_1 0x00400000U
+#define DMA_SxCR_CT 0x00080000U
+#define DMA_SxCR_DBM 0x00040000U
+#define DMA_SxCR_PL 0x00030000U
+#define DMA_SxCR_PL_0 0x00010000U
+#define DMA_SxCR_PL_1 0x00020000U
+#define DMA_SxCR_PINCOS 0x00008000U
+#define DMA_SxCR_MSIZE 0x00006000U
+#define DMA_SxCR_MSIZE_0 0x00002000U
+#define DMA_SxCR_MSIZE_1 0x00004000U
+#define DMA_SxCR_PSIZE 0x00001800U
+#define DMA_SxCR_PSIZE_0 0x00000800U
+#define DMA_SxCR_PSIZE_1 0x00001000U
+#define DMA_SxCR_MINC 0x00000400U
+#define DMA_SxCR_PINC 0x00000200U
+#define DMA_SxCR_CIRC 0x00000100U
+#define DMA_SxCR_DIR 0x000000C0U
+#define DMA_SxCR_DIR_0 0x00000040U
+#define DMA_SxCR_DIR_1 0x00000080U
+#define DMA_SxCR_PFCTRL 0x00000020U
+#define DMA_SxCR_TCIE 0x00000010U
+#define DMA_SxCR_HTIE 0x00000008U
+#define DMA_SxCR_TEIE 0x00000004U
+#define DMA_SxCR_DMEIE 0x00000002U
+#define DMA_SxCR_EN 0x00000001U
+
+/* Legacy defines */
+#define DMA_SxCR_ACK 0x00100000U
+
+/******************** Bits definition for DMA_SxCNDTR register **************/
+#define DMA_SxNDT 0x0000FFFFU
+#define DMA_SxNDT_0 0x00000001U
+#define DMA_SxNDT_1 0x00000002U
+#define DMA_SxNDT_2 0x00000004U
+#define DMA_SxNDT_3 0x00000008U
+#define DMA_SxNDT_4 0x00000010U
+#define DMA_SxNDT_5 0x00000020U
+#define DMA_SxNDT_6 0x00000040U
+#define DMA_SxNDT_7 0x00000080U
+#define DMA_SxNDT_8 0x00000100U
+#define DMA_SxNDT_9 0x00000200U
+#define DMA_SxNDT_10 0x00000400U
+#define DMA_SxNDT_11 0x00000800U
+#define DMA_SxNDT_12 0x00001000U
+#define DMA_SxNDT_13 0x00002000U
+#define DMA_SxNDT_14 0x00004000U
+#define DMA_SxNDT_15 0x00008000U
+
+/******************** Bits definition for DMA_SxFCR register ****************/
+#define DMA_SxFCR_FEIE 0x00000080U
+#define DMA_SxFCR_FS 0x00000038U
+#define DMA_SxFCR_FS_0 0x00000008U
+#define DMA_SxFCR_FS_1 0x00000010U
+#define DMA_SxFCR_FS_2 0x00000020U
+#define DMA_SxFCR_DMDIS 0x00000004U
+#define DMA_SxFCR_FTH 0x00000003U
+#define DMA_SxFCR_FTH_0 0x00000001U
+#define DMA_SxFCR_FTH_1 0x00000002U
+
+/******************** Bits definition for DMA_LISR register *****************/
+#define DMA_LISR_TCIF3 0x08000000U
+#define DMA_LISR_HTIF3 0x04000000U
+#define DMA_LISR_TEIF3 0x02000000U
+#define DMA_LISR_DMEIF3 0x01000000U
+#define DMA_LISR_FEIF3 0x00400000U
+#define DMA_LISR_TCIF2 0x00200000U
+#define DMA_LISR_HTIF2 0x00100000U
+#define DMA_LISR_TEIF2 0x00080000U
+#define DMA_LISR_DMEIF2 0x00040000U
+#define DMA_LISR_FEIF2 0x00010000U
+#define DMA_LISR_TCIF1 0x00000800U
+#define DMA_LISR_HTIF1 0x00000400U
+#define DMA_LISR_TEIF1 0x00000200U
+#define DMA_LISR_DMEIF1 0x00000100U
+#define DMA_LISR_FEIF1 0x00000040U
+#define DMA_LISR_TCIF0 0x00000020U
+#define DMA_LISR_HTIF0 0x00000010U
+#define DMA_LISR_TEIF0 0x00000008U
+#define DMA_LISR_DMEIF0 0x00000004U
+#define DMA_LISR_FEIF0 0x00000001U
+
+/******************** Bits definition for DMA_HISR register *****************/
+#define DMA_HISR_TCIF7 0x08000000U
+#define DMA_HISR_HTIF7 0x04000000U
+#define DMA_HISR_TEIF7 0x02000000U
+#define DMA_HISR_DMEIF7 0x01000000U
+#define DMA_HISR_FEIF7 0x00400000U
+#define DMA_HISR_TCIF6 0x00200000U
+#define DMA_HISR_HTIF6 0x00100000U
+#define DMA_HISR_TEIF6 0x00080000U
+#define DMA_HISR_DMEIF6 0x00040000U
+#define DMA_HISR_FEIF6 0x00010000U
+#define DMA_HISR_TCIF5 0x00000800U
+#define DMA_HISR_HTIF5 0x00000400U
+#define DMA_HISR_TEIF5 0x00000200U
+#define DMA_HISR_DMEIF5 0x00000100U
+#define DMA_HISR_FEIF5 0x00000040U
+#define DMA_HISR_TCIF4 0x00000020U
+#define DMA_HISR_HTIF4 0x00000010U
+#define DMA_HISR_TEIF4 0x00000008U
+#define DMA_HISR_DMEIF4 0x00000004U
+#define DMA_HISR_FEIF4 0x00000001U
+
+/******************** Bits definition for DMA_LIFCR register ****************/
+#define DMA_LIFCR_CTCIF3 0x08000000U
+#define DMA_LIFCR_CHTIF3 0x04000000U
+#define DMA_LIFCR_CTEIF3 0x02000000U
+#define DMA_LIFCR_CDMEIF3 0x01000000U
+#define DMA_LIFCR_CFEIF3 0x00400000U
+#define DMA_LIFCR_CTCIF2 0x00200000U
+#define DMA_LIFCR_CHTIF2 0x00100000U
+#define DMA_LIFCR_CTEIF2 0x00080000U
+#define DMA_LIFCR_CDMEIF2 0x00040000U
+#define DMA_LIFCR_CFEIF2 0x00010000U
+#define DMA_LIFCR_CTCIF1 0x00000800U
+#define DMA_LIFCR_CHTIF1 0x00000400U
+#define DMA_LIFCR_CTEIF1 0x00000200U
+#define DMA_LIFCR_CDMEIF1 0x00000100U
+#define DMA_LIFCR_CFEIF1 0x00000040U
+#define DMA_LIFCR_CTCIF0 0x00000020U
+#define DMA_LIFCR_CHTIF0 0x00000010U
+#define DMA_LIFCR_CTEIF0 0x00000008U
+#define DMA_LIFCR_CDMEIF0 0x00000004U
+#define DMA_LIFCR_CFEIF0 0x00000001U
+
+/******************** Bits definition for DMA_HIFCR register ****************/
+#define DMA_HIFCR_CTCIF7 0x08000000U
+#define DMA_HIFCR_CHTIF7 0x04000000U
+#define DMA_HIFCR_CTEIF7 0x02000000U
+#define DMA_HIFCR_CDMEIF7 0x01000000U
+#define DMA_HIFCR_CFEIF7 0x00400000U
+#define DMA_HIFCR_CTCIF6 0x00200000U
+#define DMA_HIFCR_CHTIF6 0x00100000U
+#define DMA_HIFCR_CTEIF6 0x00080000U
+#define DMA_HIFCR_CDMEIF6 0x00040000U
+#define DMA_HIFCR_CFEIF6 0x00010000U
+#define DMA_HIFCR_CTCIF5 0x00000800U
+#define DMA_HIFCR_CHTIF5 0x00000400U
+#define DMA_HIFCR_CTEIF5 0x00000200U
+#define DMA_HIFCR_CDMEIF5 0x00000100U
+#define DMA_HIFCR_CFEIF5 0x00000040U
+#define DMA_HIFCR_CTCIF4 0x00000020U
+#define DMA_HIFCR_CHTIF4 0x00000010U
+#define DMA_HIFCR_CTEIF4 0x00000008U
+#define DMA_HIFCR_CDMEIF4 0x00000004U
+#define DMA_HIFCR_CFEIF4 0x00000001U
+
+
+/******************************************************************************/
+/* */
+/* External Interrupt/Event Controller */
+/* */
+/******************************************************************************/
+/******************* Bit definition for EXTI_IMR register *******************/
+#define EXTI_IMR_MR0 0x00000001U /*!< Interrupt Mask on line 0 */
+#define EXTI_IMR_MR1 0x00000002U /*!< Interrupt Mask on line 1 */
+#define EXTI_IMR_MR2 0x00000004U /*!< Interrupt Mask on line 2 */
+#define EXTI_IMR_MR3 0x00000008U /*!< Interrupt Mask on line 3 */
+#define EXTI_IMR_MR4 0x00000010U /*!< Interrupt Mask on line 4 */
+#define EXTI_IMR_MR5 0x00000020U /*!< Interrupt Mask on line 5 */
+#define EXTI_IMR_MR6 0x00000040U /*!< Interrupt Mask on line 6 */
+#define EXTI_IMR_MR7 0x00000080U /*!< Interrupt Mask on line 7 */
+#define EXTI_IMR_MR8 0x00000100U /*!< Interrupt Mask on line 8 */
+#define EXTI_IMR_MR9 0x00000200U /*!< Interrupt Mask on line 9 */
+#define EXTI_IMR_MR10 0x00000400U /*!< Interrupt Mask on line 10 */
+#define EXTI_IMR_MR11 0x00000800U /*!< Interrupt Mask on line 11 */
+#define EXTI_IMR_MR12 0x00001000U /*!< Interrupt Mask on line 12 */
+#define EXTI_IMR_MR13 0x00002000U /*!< Interrupt Mask on line 13 */
+#define EXTI_IMR_MR14 0x00004000U /*!< Interrupt Mask on line 14 */
+#define EXTI_IMR_MR15 0x00008000U /*!< Interrupt Mask on line 15 */
+#define EXTI_IMR_MR16 0x00010000U /*!< Interrupt Mask on line 16 */
+#define EXTI_IMR_MR17 0x00020000U /*!< Interrupt Mask on line 17 */
+#define EXTI_IMR_MR18 0x00040000U /*!< Interrupt Mask on line 18 */
+#define EXTI_IMR_MR19 0x00080000U /*!< Interrupt Mask on line 19 */
+#define EXTI_IMR_MR20 0x00100000U /*!< Interrupt Mask on line 20 */
+#define EXTI_IMR_MR21 0x00200000U /*!< Interrupt Mask on line 21 */
+#define EXTI_IMR_MR22 0x00400000U /*!< Interrupt Mask on line 22 */
+#define EXTI_IMR_MR23 0x00800000U /*!< Interrupt Mask on line 23 */
+
+/******************* Bit definition for EXTI_EMR register *******************/
+#define EXTI_EMR_MR0 0x00000001U /*!< Event Mask on line 0 */
+#define EXTI_EMR_MR1 0x00000002U /*!< Event Mask on line 1 */
+#define EXTI_EMR_MR2 0x00000004U /*!< Event Mask on line 2 */
+#define EXTI_EMR_MR3 0x00000008U /*!< Event Mask on line 3 */
+#define EXTI_EMR_MR4 0x00000010U /*!< Event Mask on line 4 */
+#define EXTI_EMR_MR5 0x00000020U /*!< Event Mask on line 5 */
+#define EXTI_EMR_MR6 0x00000040U /*!< Event Mask on line 6 */
+#define EXTI_EMR_MR7 0x00000080U /*!< Event Mask on line 7 */
+#define EXTI_EMR_MR8 0x00000100U /*!< Event Mask on line 8 */
+#define EXTI_EMR_MR9 0x00000200U /*!< Event Mask on line 9 */
+#define EXTI_EMR_MR10 0x00000400U /*!< Event Mask on line 10 */
+#define EXTI_EMR_MR11 0x00000800U /*!< Event Mask on line 11 */
+#define EXTI_EMR_MR12 0x00001000U /*!< Event Mask on line 12 */
+#define EXTI_EMR_MR13 0x00002000U /*!< Event Mask on line 13 */
+#define EXTI_EMR_MR14 0x00004000U /*!< Event Mask on line 14 */
+#define EXTI_EMR_MR15 0x00008000U /*!< Event Mask on line 15 */
+#define EXTI_EMR_MR16 0x00010000U /*!< Event Mask on line 16 */
+#define EXTI_EMR_MR17 0x00020000U /*!< Event Mask on line 17 */
+#define EXTI_EMR_MR18 0x00040000U /*!< Event Mask on line 18 */
+#define EXTI_EMR_MR19 0x00080000U /*!< Event Mask on line 19 */
+#define EXTI_EMR_MR20 0x00100000U /*!< Event Mask on line 20 */
+#define EXTI_EMR_MR21 0x00200000U /*!< Event Mask on line 21 */
+#define EXTI_EMR_MR22 0x00400000U /*!< Event Mask on line 22 */
+#define EXTI_EMR_MR23 0x00800000U /*!< Event Mask on line 23 */
+
+/****************** Bit definition for EXTI_RTSR register *******************/
+#define EXTI_RTSR_TR0 0x00000001U /*!< Rising trigger event configuration bit of line 0 */
+#define EXTI_RTSR_TR1 0x00000002U /*!< Rising trigger event configuration bit of line 1 */
+#define EXTI_RTSR_TR2 0x00000004U /*!< Rising trigger event configuration bit of line 2 */
+#define EXTI_RTSR_TR3 0x00000008U /*!< Rising trigger event configuration bit of line 3 */
+#define EXTI_RTSR_TR4 0x00000010U /*!< Rising trigger event configuration bit of line 4 */
+#define EXTI_RTSR_TR5 0x00000020U /*!< Rising trigger event configuration bit of line 5 */
+#define EXTI_RTSR_TR6 0x00000040U /*!< Rising trigger event configuration bit of line 6 */
+#define EXTI_RTSR_TR7 0x00000080U /*!< Rising trigger event configuration bit of line 7 */
+#define EXTI_RTSR_TR8 0x00000100U /*!< Rising trigger event configuration bit of line 8 */
+#define EXTI_RTSR_TR9 0x00000200U /*!< Rising trigger event configuration bit of line 9 */
+#define EXTI_RTSR_TR10 0x00000400U /*!< Rising trigger event configuration bit of line 10 */
+#define EXTI_RTSR_TR11 0x00000800U /*!< Rising trigger event configuration bit of line 11 */
+#define EXTI_RTSR_TR12 0x00001000U /*!< Rising trigger event configuration bit of line 12 */
+#define EXTI_RTSR_TR13 0x00002000U /*!< Rising trigger event configuration bit of line 13 */
+#define EXTI_RTSR_TR14 0x00004000U /*!< Rising trigger event configuration bit of line 14 */
+#define EXTI_RTSR_TR15 0x00008000U /*!< Rising trigger event configuration bit of line 15 */
+#define EXTI_RTSR_TR16 0x00010000U /*!< Rising trigger event configuration bit of line 16 */
+#define EXTI_RTSR_TR17 0x00020000U /*!< Rising trigger event configuration bit of line 17 */
+#define EXTI_RTSR_TR18 0x00040000U /*!< Rising trigger event configuration bit of line 18 */
+#define EXTI_RTSR_TR19 0x00080000U /*!< Rising trigger event configuration bit of line 19 */
+#define EXTI_RTSR_TR20 0x00100000U /*!< Rising trigger event configuration bit of line 20 */
+#define EXTI_RTSR_TR21 0x00200000U /*!< Rising trigger event configuration bit of line 21 */
+#define EXTI_RTSR_TR22 0x00400000U /*!< Rising trigger event configuration bit of line 22 */
+#define EXTI_RTSR_TR23 0x00800000U /*!< Rising trigger event configuration bit of line 23 */
+
+/****************** Bit definition for EXTI_FTSR register *******************/
+#define EXTI_FTSR_TR0 0x00000001U /*!< Falling trigger event configuration bit of line 0 */
+#define EXTI_FTSR_TR1 0x00000002U /*!< Falling trigger event configuration bit of line 1 */
+#define EXTI_FTSR_TR2 0x00000004U /*!< Falling trigger event configuration bit of line 2 */
+#define EXTI_FTSR_TR3 0x00000008U /*!< Falling trigger event configuration bit of line 3 */
+#define EXTI_FTSR_TR4 0x00000010U /*!< Falling trigger event configuration bit of line 4 */
+#define EXTI_FTSR_TR5 0x00000020U /*!< Falling trigger event configuration bit of line 5 */
+#define EXTI_FTSR_TR6 0x00000040U /*!< Falling trigger event configuration bit of line 6 */
+#define EXTI_FTSR_TR7 0x00000080U /*!< Falling trigger event configuration bit of line 7 */
+#define EXTI_FTSR_TR8 0x00000100U /*!< Falling trigger event configuration bit of line 8 */
+#define EXTI_FTSR_TR9 0x00000200U /*!< Falling trigger event configuration bit of line 9 */
+#define EXTI_FTSR_TR10 0x00000400U /*!< Falling trigger event configuration bit of line 10 */
+#define EXTI_FTSR_TR11 0x00000800U /*!< Falling trigger event configuration bit of line 11 */
+#define EXTI_FTSR_TR12 0x00001000U /*!< Falling trigger event configuration bit of line 12 */
+#define EXTI_FTSR_TR13 0x00002000U /*!< Falling trigger event configuration bit of line 13 */
+#define EXTI_FTSR_TR14 0x00004000U /*!< Falling trigger event configuration bit of line 14 */
+#define EXTI_FTSR_TR15 0x00008000U /*!< Falling trigger event configuration bit of line 15 */
+#define EXTI_FTSR_TR16 0x00010000U /*!< Falling trigger event configuration bit of line 16 */
+#define EXTI_FTSR_TR17 0x00020000U /*!< Falling trigger event configuration bit of line 17 */
+#define EXTI_FTSR_TR18 0x00040000U /*!< Falling trigger event configuration bit of line 18 */
+#define EXTI_FTSR_TR19 0x00080000U /*!< Falling trigger event configuration bit of line 19 */
+#define EXTI_FTSR_TR20 0x00100000U /*!< Falling trigger event configuration bit of line 20 */
+#define EXTI_FTSR_TR21 0x00200000U /*!< Falling trigger event configuration bit of line 21 */
+#define EXTI_FTSR_TR22 0x00400000U /*!< Falling trigger event configuration bit of line 22 */
+#define EXTI_FTSR_TR23 0x00800000U /*!< Falling trigger event configuration bit of line 23 */
+
+/****************** Bit definition for EXTI_SWIER register ******************/
+#define EXTI_SWIER_SWIER0 0x00000001U /*!< Software Interrupt on line 0 */
+#define EXTI_SWIER_SWIER1 0x00000002U /*!< Software Interrupt on line 1 */
+#define EXTI_SWIER_SWIER2 0x00000004U /*!< Software Interrupt on line 2 */
+#define EXTI_SWIER_SWIER3 0x00000008U /*!< Software Interrupt on line 3 */
+#define EXTI_SWIER_SWIER4 0x00000010U /*!< Software Interrupt on line 4 */
+#define EXTI_SWIER_SWIER5 0x00000020U /*!< Software Interrupt on line 5 */
+#define EXTI_SWIER_SWIER6 0x00000040U /*!< Software Interrupt on line 6 */
+#define EXTI_SWIER_SWIER7 0x00000080U /*!< Software Interrupt on line 7 */
+#define EXTI_SWIER_SWIER8 0x00000100U /*!< Software Interrupt on line 8 */
+#define EXTI_SWIER_SWIER9 0x00000200U /*!< Software Interrupt on line 9 */
+#define EXTI_SWIER_SWIER10 0x00000400U /*!< Software Interrupt on line 10 */
+#define EXTI_SWIER_SWIER11 0x00000800U /*!< Software Interrupt on line 11 */
+#define EXTI_SWIER_SWIER12 0x00001000U /*!< Software Interrupt on line 12 */
+#define EXTI_SWIER_SWIER13 0x00002000U /*!< Software Interrupt on line 13 */
+#define EXTI_SWIER_SWIER14 0x00004000U /*!< Software Interrupt on line 14 */
+#define EXTI_SWIER_SWIER15 0x00008000U /*!< Software Interrupt on line 15 */
+#define EXTI_SWIER_SWIER16 0x00010000U /*!< Software Interrupt on line 16 */
+#define EXTI_SWIER_SWIER17 0x00020000U /*!< Software Interrupt on line 17 */
+#define EXTI_SWIER_SWIER18 0x00040000U /*!< Software Interrupt on line 18 */
+#define EXTI_SWIER_SWIER19 0x00080000U /*!< Software Interrupt on line 19 */
+#define EXTI_SWIER_SWIER20 0x00100000U /*!< Software Interrupt on line 20 */
+#define EXTI_SWIER_SWIER21 0x00200000U /*!< Software Interrupt on line 21 */
+#define EXTI_SWIER_SWIER22 0x00400000U /*!< Software Interrupt on line 22 */
+#define EXTI_SWIER_SWIER23 0x00800000U /*!< Software Interrupt on line 23 */
+
+/******************* Bit definition for EXTI_PR register ********************/
+#define EXTI_PR_PR0 0x00000001U /*!< Pending bit for line 0 */
+#define EXTI_PR_PR1 0x00000002U /*!< Pending bit for line 1 */
+#define EXTI_PR_PR2 0x00000004U /*!< Pending bit for line 2 */
+#define EXTI_PR_PR3 0x00000008U /*!< Pending bit for line 3 */
+#define EXTI_PR_PR4 0x00000010U /*!< Pending bit for line 4 */
+#define EXTI_PR_PR5 0x00000020U /*!< Pending bit for line 5 */
+#define EXTI_PR_PR6 0x00000040U /*!< Pending bit for line 6 */
+#define EXTI_PR_PR7 0x00000080U /*!< Pending bit for line 7 */
+#define EXTI_PR_PR8 0x00000100U /*!< Pending bit for line 8 */
+#define EXTI_PR_PR9 0x00000200U /*!< Pending bit for line 9 */
+#define EXTI_PR_PR10 0x00000400U /*!< Pending bit for line 10 */
+#define EXTI_PR_PR11 0x00000800U /*!< Pending bit for line 11 */
+#define EXTI_PR_PR12 0x00001000U /*!< Pending bit for line 12 */
+#define EXTI_PR_PR13 0x00002000U /*!< Pending bit for line 13 */
+#define EXTI_PR_PR14 0x00004000U /*!< Pending bit for line 14 */
+#define EXTI_PR_PR15 0x00008000U /*!< Pending bit for line 15 */
+#define EXTI_PR_PR16 0x00010000U /*!< Pending bit for line 16 */
+#define EXTI_PR_PR17 0x00020000U /*!< Pending bit for line 17 */
+#define EXTI_PR_PR18 0x00040000U /*!< Pending bit for line 18 */
+#define EXTI_PR_PR19 0x00080000U /*!< Pending bit for line 19 */
+#define EXTI_PR_PR20 0x00100000U /*!< Pending bit for line 20 */
+#define EXTI_PR_PR21 0x00200000U /*!< Pending bit for line 21 */
+#define EXTI_PR_PR22 0x00400000U /*!< Pending bit for line 22 */
+#define EXTI_PR_PR23 0x00800000U /*!< Pending bit for line 23 */
+
+/******************************************************************************/
+/* */
+/* FLASH */
+/* */
+/******************************************************************************/
+/******************* Bits definition for FLASH_ACR register *****************/
+#define FLASH_ACR_LATENCY 0x0000000FU
+#define FLASH_ACR_LATENCY_0WS 0x00000000U
+#define FLASH_ACR_LATENCY_1WS 0x00000001U
+#define FLASH_ACR_LATENCY_2WS 0x00000002U
+#define FLASH_ACR_LATENCY_3WS 0x00000003U
+#define FLASH_ACR_LATENCY_4WS 0x00000004U
+#define FLASH_ACR_LATENCY_5WS 0x00000005U
+#define FLASH_ACR_LATENCY_6WS 0x00000006U
+#define FLASH_ACR_LATENCY_7WS 0x00000007U
+
+#define FLASH_ACR_PRFTEN 0x00000100U
+#define FLASH_ACR_ICEN 0x00000200U
+#define FLASH_ACR_DCEN 0x00000400U
+#define FLASH_ACR_ICRST 0x00000800U
+#define FLASH_ACR_DCRST 0x00001000U
+#define FLASH_ACR_BYTE0_ADDRESS 0x40023C00U
+#define FLASH_ACR_BYTE2_ADDRESS 0x40023C03U
+
+/******************* Bits definition for FLASH_SR register ******************/
+#define FLASH_SR_EOP 0x00000001U
+#define FLASH_SR_SOP 0x00000002U
+#define FLASH_SR_WRPERR 0x00000010U
+#define FLASH_SR_PGAERR 0x00000020U
+#define FLASH_SR_PGPERR 0x00000040U
+#define FLASH_SR_PGSERR 0x00000080U
+#define FLASH_SR_BSY 0x00010000U
+
+/******************* Bits definition for FLASH_CR register ******************/
+#define FLASH_CR_PG 0x00000001U
+#define FLASH_CR_SER 0x00000002U
+#define FLASH_CR_MER 0x00000004U
+#define FLASH_CR_SNB 0x000000F8U
+#define FLASH_CR_SNB_0 0x00000008U
+#define FLASH_CR_SNB_1 0x00000010U
+#define FLASH_CR_SNB_2 0x00000020U
+#define FLASH_CR_SNB_3 0x00000040U
+#define FLASH_CR_SNB_4 0x00000080U
+#define FLASH_CR_PSIZE 0x00000300U
+#define FLASH_CR_PSIZE_0 0x00000100U
+#define FLASH_CR_PSIZE_1 0x00000200U
+#define FLASH_CR_STRT 0x00010000U
+#define FLASH_CR_EOPIE 0x01000000U
+#define FLASH_CR_LOCK 0x80000000U
+
+/******************* Bits definition for FLASH_OPTCR register ***************/
+#define FLASH_OPTCR_OPTLOCK 0x00000001U
+#define FLASH_OPTCR_OPTSTRT 0x00000002U
+#define FLASH_OPTCR_BOR_LEV_0 0x00000004U
+#define FLASH_OPTCR_BOR_LEV_1 0x00000008U
+#define FLASH_OPTCR_BOR_LEV 0x0000000CU
+
+#define FLASH_OPTCR_WDG_SW 0x00000020U
+#define FLASH_OPTCR_nRST_STOP 0x00000040U
+#define FLASH_OPTCR_nRST_STDBY 0x00000080U
+#define FLASH_OPTCR_RDP 0x0000FF00U
+#define FLASH_OPTCR_RDP_0 0x00000100U
+#define FLASH_OPTCR_RDP_1 0x00000200U
+#define FLASH_OPTCR_RDP_2 0x00000400U
+#define FLASH_OPTCR_RDP_3 0x00000800U
+#define FLASH_OPTCR_RDP_4 0x00001000U
+#define FLASH_OPTCR_RDP_5 0x00002000U
+#define FLASH_OPTCR_RDP_6 0x00004000U
+#define FLASH_OPTCR_RDP_7 0x00008000U
+#define FLASH_OPTCR_nWRP 0x0FFF0000U
+#define FLASH_OPTCR_nWRP_0 0x00010000U
+#define FLASH_OPTCR_nWRP_1 0x00020000U
+#define FLASH_OPTCR_nWRP_2 0x00040000U
+#define FLASH_OPTCR_nWRP_3 0x00080000U
+#define FLASH_OPTCR_nWRP_4 0x00100000U
+#define FLASH_OPTCR_nWRP_5 0x00200000U
+#define FLASH_OPTCR_nWRP_6 0x00400000U
+#define FLASH_OPTCR_nWRP_7 0x00800000U
+#define FLASH_OPTCR_nWRP_8 0x01000000U
+#define FLASH_OPTCR_nWRP_9 0x02000000U
+#define FLASH_OPTCR_nWRP_10 0x04000000U
+#define FLASH_OPTCR_nWRP_11 0x08000000U
+
+/****************** Bits definition for FLASH_OPTCR1 register ***************/
+#define FLASH_OPTCR1_nWRP 0x0FFF0000U
+#define FLASH_OPTCR1_nWRP_0 0x00010000U
+#define FLASH_OPTCR1_nWRP_1 0x00020000U
+#define FLASH_OPTCR1_nWRP_2 0x00040000U
+#define FLASH_OPTCR1_nWRP_3 0x00080000U
+#define FLASH_OPTCR1_nWRP_4 0x00100000U
+#define FLASH_OPTCR1_nWRP_5 0x00200000U
+#define FLASH_OPTCR1_nWRP_6 0x00400000U
+#define FLASH_OPTCR1_nWRP_7 0x00800000U
+#define FLASH_OPTCR1_nWRP_8 0x01000000U
+#define FLASH_OPTCR1_nWRP_9 0x02000000U
+#define FLASH_OPTCR1_nWRP_10 0x04000000U
+#define FLASH_OPTCR1_nWRP_11 0x08000000U
+
+/******************************************************************************/
+/* */
+/* General Purpose I/O */
+/* */
+/******************************************************************************/
+/****************** Bits definition for GPIO_MODER register *****************/
+#define GPIO_MODER_MODER0 0x00000003U
+#define GPIO_MODER_MODER0_0 0x00000001U
+#define GPIO_MODER_MODER0_1 0x00000002U
+
+#define GPIO_MODER_MODER1 0x0000000CU
+#define GPIO_MODER_MODER1_0 0x00000004U
+#define GPIO_MODER_MODER1_1 0x00000008U
+
+#define GPIO_MODER_MODER2 0x00000030U
+#define GPIO_MODER_MODER2_0 0x00000010U
+#define GPIO_MODER_MODER2_1 0x00000020U
+
+#define GPIO_MODER_MODER3 0x000000C0U
+#define GPIO_MODER_MODER3_0 0x00000040U
+#define GPIO_MODER_MODER3_1 0x00000080U
+
+#define GPIO_MODER_MODER4 0x00000300U
+#define GPIO_MODER_MODER4_0 0x00000100U
+#define GPIO_MODER_MODER4_1 0x00000200U
+
+#define GPIO_MODER_MODER5 0x00000C00U
+#define GPIO_MODER_MODER5_0 0x00000400U
+#define GPIO_MODER_MODER5_1 0x00000800U
+
+#define GPIO_MODER_MODER6 0x00003000U
+#define GPIO_MODER_MODER6_0 0x00001000U
+#define GPIO_MODER_MODER6_1 0x00002000U
+
+#define GPIO_MODER_MODER7 0x0000C000U
+#define GPIO_MODER_MODER7_0 0x00004000U
+#define GPIO_MODER_MODER7_1 0x00008000U
+
+#define GPIO_MODER_MODER8 0x00030000U
+#define GPIO_MODER_MODER8_0 0x00010000U
+#define GPIO_MODER_MODER8_1 0x00020000U
+
+#define GPIO_MODER_MODER9 0x000C0000U
+#define GPIO_MODER_MODER9_0 0x00040000U
+#define GPIO_MODER_MODER9_1 0x00080000U
+
+#define GPIO_MODER_MODER10 0x00300000U
+#define GPIO_MODER_MODER10_0 0x00100000U
+#define GPIO_MODER_MODER10_1 0x00200000U
+
+#define GPIO_MODER_MODER11 0x00C00000U
+#define GPIO_MODER_MODER11_0 0x00400000U
+#define GPIO_MODER_MODER11_1 0x00800000U
+
+#define GPIO_MODER_MODER12 0x03000000U
+#define GPIO_MODER_MODER12_0 0x01000000U
+#define GPIO_MODER_MODER12_1 0x02000000U
+
+#define GPIO_MODER_MODER13 0x0C000000U
+#define GPIO_MODER_MODER13_0 0x04000000U
+#define GPIO_MODER_MODER13_1 0x08000000U
+
+#define GPIO_MODER_MODER14 0x30000000U
+#define GPIO_MODER_MODER14_0 0x10000000U
+#define GPIO_MODER_MODER14_1 0x20000000U
+
+#define GPIO_MODER_MODER15 0xC0000000U
+#define GPIO_MODER_MODER15_0 0x40000000U
+#define GPIO_MODER_MODER15_1 0x80000000U
+
+/****************** Bits definition for GPIO_OTYPER register ****************/
+#define GPIO_OTYPER_OT_0 0x00000001U
+#define GPIO_OTYPER_OT_1 0x00000002U
+#define GPIO_OTYPER_OT_2 0x00000004U
+#define GPIO_OTYPER_OT_3 0x00000008U
+#define GPIO_OTYPER_OT_4 0x00000010U
+#define GPIO_OTYPER_OT_5 0x00000020U
+#define GPIO_OTYPER_OT_6 0x00000040U
+#define GPIO_OTYPER_OT_7 0x00000080U
+#define GPIO_OTYPER_OT_8 0x00000100U
+#define GPIO_OTYPER_OT_9 0x00000200U
+#define GPIO_OTYPER_OT_10 0x00000400U
+#define GPIO_OTYPER_OT_11 0x00000800U
+#define GPIO_OTYPER_OT_12 0x00001000U
+#define GPIO_OTYPER_OT_13 0x00002000U
+#define GPIO_OTYPER_OT_14 0x00004000U
+#define GPIO_OTYPER_OT_15 0x00008000U
+
+/****************** Bits definition for GPIO_OSPEEDR register ***************/
+#define GPIO_OSPEEDER_OSPEEDR0 0x00000003U
+#define GPIO_OSPEEDER_OSPEEDR0_0 0x00000001U
+#define GPIO_OSPEEDER_OSPEEDR0_1 0x00000002U
+
+#define GPIO_OSPEEDER_OSPEEDR1 0x0000000CU
+#define GPIO_OSPEEDER_OSPEEDR1_0 0x00000004U
+#define GPIO_OSPEEDER_OSPEEDR1_1 0x00000008U
+
+#define GPIO_OSPEEDER_OSPEEDR2 0x00000030U
+#define GPIO_OSPEEDER_OSPEEDR2_0 0x00000010U
+#define GPIO_OSPEEDER_OSPEEDR2_1 0x00000020U
+
+#define GPIO_OSPEEDER_OSPEEDR3 0x000000C0U
+#define GPIO_OSPEEDER_OSPEEDR3_0 0x00000040U
+#define GPIO_OSPEEDER_OSPEEDR3_1 0x00000080U
+
+#define GPIO_OSPEEDER_OSPEEDR4 0x00000300U
+#define GPIO_OSPEEDER_OSPEEDR4_0 0x00000100U
+#define GPIO_OSPEEDER_OSPEEDR4_1 0x00000200U
+
+#define GPIO_OSPEEDER_OSPEEDR5 0x00000C00U
+#define GPIO_OSPEEDER_OSPEEDR5_0 0x00000400U
+#define GPIO_OSPEEDER_OSPEEDR5_1 0x00000800U
+
+#define GPIO_OSPEEDER_OSPEEDR6 0x00003000U
+#define GPIO_OSPEEDER_OSPEEDR6_0 0x00001000U
+#define GPIO_OSPEEDER_OSPEEDR6_1 0x00002000U
+
+#define GPIO_OSPEEDER_OSPEEDR7 0x0000C000U
+#define GPIO_OSPEEDER_OSPEEDR7_0 0x00004000U
+#define GPIO_OSPEEDER_OSPEEDR7_1 0x00008000U
+
+#define GPIO_OSPEEDER_OSPEEDR8 0x00030000U
+#define GPIO_OSPEEDER_OSPEEDR8_0 0x00010000U
+#define GPIO_OSPEEDER_OSPEEDR8_1 0x00020000U
+
+#define GPIO_OSPEEDER_OSPEEDR9 0x000C0000U
+#define GPIO_OSPEEDER_OSPEEDR9_0 0x00040000U
+#define GPIO_OSPEEDER_OSPEEDR9_1 0x00080000U
+
+#define GPIO_OSPEEDER_OSPEEDR10 0x00300000U
+#define GPIO_OSPEEDER_OSPEEDR10_0 0x00100000U
+#define GPIO_OSPEEDER_OSPEEDR10_1 0x00200000U
+
+#define GPIO_OSPEEDER_OSPEEDR11 0x00C00000U
+#define GPIO_OSPEEDER_OSPEEDR11_0 0x00400000U
+#define GPIO_OSPEEDER_OSPEEDR11_1 0x00800000U
+
+#define GPIO_OSPEEDER_OSPEEDR12 0x03000000U
+#define GPIO_OSPEEDER_OSPEEDR12_0 0x01000000U
+#define GPIO_OSPEEDER_OSPEEDR12_1 0x02000000U
+
+#define GPIO_OSPEEDER_OSPEEDR13 0x0C000000U
+#define GPIO_OSPEEDER_OSPEEDR13_0 0x04000000U
+#define GPIO_OSPEEDER_OSPEEDR13_1 0x08000000U
+
+#define GPIO_OSPEEDER_OSPEEDR14 0x30000000U
+#define GPIO_OSPEEDER_OSPEEDR14_0 0x10000000U
+#define GPIO_OSPEEDER_OSPEEDR14_1 0x20000000U
+
+#define GPIO_OSPEEDER_OSPEEDR15 0xC0000000U
+#define GPIO_OSPEEDER_OSPEEDR15_0 0x40000000U
+#define GPIO_OSPEEDER_OSPEEDR15_1 0x80000000U
+
+/****************** Bits definition for GPIO_PUPDR register *****************/
+#define GPIO_PUPDR_PUPDR0 0x00000003U
+#define GPIO_PUPDR_PUPDR0_0 0x00000001U
+#define GPIO_PUPDR_PUPDR0_1 0x00000002U
+
+#define GPIO_PUPDR_PUPDR1 0x0000000CU
+#define GPIO_PUPDR_PUPDR1_0 0x00000004U
+#define GPIO_PUPDR_PUPDR1_1 0x00000008U
+
+#define GPIO_PUPDR_PUPDR2 0x00000030U
+#define GPIO_PUPDR_PUPDR2_0 0x00000010U
+#define GPIO_PUPDR_PUPDR2_1 0x00000020U
+
+#define GPIO_PUPDR_PUPDR3 0x000000C0U
+#define GPIO_PUPDR_PUPDR3_0 0x00000040U
+#define GPIO_PUPDR_PUPDR3_1 0x00000080U
+
+#define GPIO_PUPDR_PUPDR4 0x00000300U
+#define GPIO_PUPDR_PUPDR4_0 0x00000100U
+#define GPIO_PUPDR_PUPDR4_1 0x00000200U
+
+#define GPIO_PUPDR_PUPDR5 0x00000C00U
+#define GPIO_PUPDR_PUPDR5_0 0x00000400U
+#define GPIO_PUPDR_PUPDR5_1 0x00000800U
+
+#define GPIO_PUPDR_PUPDR6 0x00003000U
+#define GPIO_PUPDR_PUPDR6_0 0x00001000U
+#define GPIO_PUPDR_PUPDR6_1 0x00002000U
+
+#define GPIO_PUPDR_PUPDR7 0x0000C000U
+#define GPIO_PUPDR_PUPDR7_0 0x00004000U
+#define GPIO_PUPDR_PUPDR7_1 0x00008000U
+
+#define GPIO_PUPDR_PUPDR8 0x00030000U
+#define GPIO_PUPDR_PUPDR8_0 0x00010000U
+#define GPIO_PUPDR_PUPDR8_1 0x00020000U
+
+#define GPIO_PUPDR_PUPDR9 0x000C0000U
+#define GPIO_PUPDR_PUPDR9_0 0x00040000U
+#define GPIO_PUPDR_PUPDR9_1 0x00080000U
+
+#define GPIO_PUPDR_PUPDR10 0x00300000U
+#define GPIO_PUPDR_PUPDR10_0 0x00100000U
+#define GPIO_PUPDR_PUPDR10_1 0x00200000U
+
+#define GPIO_PUPDR_PUPDR11 0x00C00000U
+#define GPIO_PUPDR_PUPDR11_0 0x00400000U
+#define GPIO_PUPDR_PUPDR11_1 0x00800000U
+
+#define GPIO_PUPDR_PUPDR12 0x03000000U
+#define GPIO_PUPDR_PUPDR12_0 0x01000000U
+#define GPIO_PUPDR_PUPDR12_1 0x02000000U
+
+#define GPIO_PUPDR_PUPDR13 0x0C000000U
+#define GPIO_PUPDR_PUPDR13_0 0x04000000U
+#define GPIO_PUPDR_PUPDR13_1 0x08000000U
+
+#define GPIO_PUPDR_PUPDR14 0x30000000U
+#define GPIO_PUPDR_PUPDR14_0 0x10000000U
+#define GPIO_PUPDR_PUPDR14_1 0x20000000U
+
+#define GPIO_PUPDR_PUPDR15 0xC0000000U
+#define GPIO_PUPDR_PUPDR15_0 0x40000000U
+#define GPIO_PUPDR_PUPDR15_1 0x80000000U
+
+/****************** Bits definition for GPIO_IDR register *******************/
+#define GPIO_IDR_IDR_0 0x00000001U
+#define GPIO_IDR_IDR_1 0x00000002U
+#define GPIO_IDR_IDR_2 0x00000004U
+#define GPIO_IDR_IDR_3 0x00000008U
+#define GPIO_IDR_IDR_4 0x00000010U
+#define GPIO_IDR_IDR_5 0x00000020U
+#define GPIO_IDR_IDR_6 0x00000040U
+#define GPIO_IDR_IDR_7 0x00000080U
+#define GPIO_IDR_IDR_8 0x00000100U
+#define GPIO_IDR_IDR_9 0x00000200U
+#define GPIO_IDR_IDR_10 0x00000400U
+#define GPIO_IDR_IDR_11 0x00000800U
+#define GPIO_IDR_IDR_12 0x00001000U
+#define GPIO_IDR_IDR_13 0x00002000U
+#define GPIO_IDR_IDR_14 0x00004000U
+#define GPIO_IDR_IDR_15 0x00008000U
+
+/****************** Bits definition for GPIO_ODR register *******************/
+#define GPIO_ODR_ODR_0 0x00000001U
+#define GPIO_ODR_ODR_1 0x00000002U
+#define GPIO_ODR_ODR_2 0x00000004U
+#define GPIO_ODR_ODR_3 0x00000008U
+#define GPIO_ODR_ODR_4 0x00000010U
+#define GPIO_ODR_ODR_5 0x00000020U
+#define GPIO_ODR_ODR_6 0x00000040U
+#define GPIO_ODR_ODR_7 0x00000080U
+#define GPIO_ODR_ODR_8 0x00000100U
+#define GPIO_ODR_ODR_9 0x00000200U
+#define GPIO_ODR_ODR_10 0x00000400U
+#define GPIO_ODR_ODR_11 0x00000800U
+#define GPIO_ODR_ODR_12 0x00001000U
+#define GPIO_ODR_ODR_13 0x00002000U
+#define GPIO_ODR_ODR_14 0x00004000U
+#define GPIO_ODR_ODR_15 0x00008000U
+
+/****************** Bits definition for GPIO_BSRR register ******************/
+#define GPIO_BSRR_BS_0 0x00000001U
+#define GPIO_BSRR_BS_1 0x00000002U
+#define GPIO_BSRR_BS_2 0x00000004U
+#define GPIO_BSRR_BS_3 0x00000008U
+#define GPIO_BSRR_BS_4 0x00000010U
+#define GPIO_BSRR_BS_5 0x00000020U
+#define GPIO_BSRR_BS_6 0x00000040U
+#define GPIO_BSRR_BS_7 0x00000080U
+#define GPIO_BSRR_BS_8 0x00000100U
+#define GPIO_BSRR_BS_9 0x00000200U
+#define GPIO_BSRR_BS_10 0x00000400U
+#define GPIO_BSRR_BS_11 0x00000800U
+#define GPIO_BSRR_BS_12 0x00001000U
+#define GPIO_BSRR_BS_13 0x00002000U
+#define GPIO_BSRR_BS_14 0x00004000U
+#define GPIO_BSRR_BS_15 0x00008000U
+#define GPIO_BSRR_BR_0 0x00010000U
+#define GPIO_BSRR_BR_1 0x00020000U
+#define GPIO_BSRR_BR_2 0x00040000U
+#define GPIO_BSRR_BR_3 0x00080000U
+#define GPIO_BSRR_BR_4 0x00100000U
+#define GPIO_BSRR_BR_5 0x00200000U
+#define GPIO_BSRR_BR_6 0x00400000U
+#define GPIO_BSRR_BR_7 0x00800000U
+#define GPIO_BSRR_BR_8 0x01000000U
+#define GPIO_BSRR_BR_9 0x02000000U
+#define GPIO_BSRR_BR_10 0x04000000U
+#define GPIO_BSRR_BR_11 0x08000000U
+#define GPIO_BSRR_BR_12 0x10000000U
+#define GPIO_BSRR_BR_13 0x20000000U
+#define GPIO_BSRR_BR_14 0x40000000U
+#define GPIO_BSRR_BR_15 0x80000000U
+
+/****************** Bit definition for GPIO_LCKR register *********************/
+#define GPIO_LCKR_LCK0 0x00000001U
+#define GPIO_LCKR_LCK1 0x00000002U
+#define GPIO_LCKR_LCK2 0x00000004U
+#define GPIO_LCKR_LCK3 0x00000008U
+#define GPIO_LCKR_LCK4 0x00000010U
+#define GPIO_LCKR_LCK5 0x00000020U
+#define GPIO_LCKR_LCK6 0x00000040U
+#define GPIO_LCKR_LCK7 0x00000080U
+#define GPIO_LCKR_LCK8 0x00000100U
+#define GPIO_LCKR_LCK9 0x00000200U
+#define GPIO_LCKR_LCK10 0x00000400U
+#define GPIO_LCKR_LCK11 0x00000800U
+#define GPIO_LCKR_LCK12 0x00001000U
+#define GPIO_LCKR_LCK13 0x00002000U
+#define GPIO_LCKR_LCK14 0x00004000U
+#define GPIO_LCKR_LCK15 0x00008000U
+#define GPIO_LCKR_LCKK 0x00010000U
+
+/******************************************************************************/
+/* */
+/* Inter-integrated Circuit Interface */
+/* */
+/******************************************************************************/
+/******************* Bit definition for I2C_CR1 register ********************/
+#define I2C_CR1_PE 0x00000001U /*!<Peripheral Enable */
+#define I2C_CR1_SMBUS 0x00000002U /*!<SMBus Mode */
+#define I2C_CR1_SMBTYPE 0x00000008U /*!<SMBus Type */
+#define I2C_CR1_ENARP 0x00000010U /*!<ARP Enable */
+#define I2C_CR1_ENPEC 0x00000020U /*!<PEC Enable */
+#define I2C_CR1_ENGC 0x00000040U /*!<General Call Enable */
+#define I2C_CR1_NOSTRETCH 0x00000080U /*!<Clock Stretching Disable (Slave mode) */
+#define I2C_CR1_START 0x00000100U /*!<Start Generation */
+#define I2C_CR1_STOP 0x00000200U /*!<Stop Generation */
+#define I2C_CR1_ACK 0x00000400U /*!<Acknowledge Enable */
+#define I2C_CR1_POS 0x00000800U /*!<Acknowledge/PEC Position (for data reception) */
+#define I2C_CR1_PEC 0x00001000U /*!<Packet Error Checking */
+#define I2C_CR1_ALERT 0x00002000U /*!<SMBus Alert */
+#define I2C_CR1_SWRST 0x00008000U /*!<Software Reset */
+
+/******************* Bit definition for I2C_CR2 register ********************/
+#define I2C_CR2_FREQ 0x0000003FU /*!<FREQ[5:0] bits (Peripheral Clock Frequency) */
+#define I2C_CR2_FREQ_0 0x00000001U /*!<Bit 0 */
+#define I2C_CR2_FREQ_1 0x00000002U /*!<Bit 1 */
+#define I2C_CR2_FREQ_2 0x00000004U /*!<Bit 2 */
+#define I2C_CR2_FREQ_3 0x00000008U /*!<Bit 3 */
+#define I2C_CR2_FREQ_4 0x00000010U /*!<Bit 4 */
+#define I2C_CR2_FREQ_5 0x00000020U /*!<Bit 5 */
+
+#define I2C_CR2_ITERREN 0x00000100U /*!<Error Interrupt Enable */
+#define I2C_CR2_ITEVTEN 0x00000200U /*!<Event Interrupt Enable */
+#define I2C_CR2_ITBUFEN 0x00000400U /*!<Buffer Interrupt Enable */
+#define I2C_CR2_DMAEN 0x00000800U /*!<DMA Requests Enable */
+#define I2C_CR2_LAST 0x00001000U /*!<DMA Last Transfer */
+
+/******************* Bit definition for I2C_OAR1 register *******************/
+#define I2C_OAR1_ADD1_7 0x000000FEU /*!<Interface Address */
+#define I2C_OAR1_ADD8_9 0x00000300U /*!<Interface Address */
+
+#define I2C_OAR1_ADD0 0x00000001U /*!<Bit 0 */
+#define I2C_OAR1_ADD1 0x00000002U /*!<Bit 1 */
+#define I2C_OAR1_ADD2 0x00000004U /*!<Bit 2 */
+#define I2C_OAR1_ADD3 0x00000008U /*!<Bit 3 */
+#define I2C_OAR1_ADD4 0x00000010U /*!<Bit 4 */
+#define I2C_OAR1_ADD5 0x00000020U /*!<Bit 5 */
+#define I2C_OAR1_ADD6 0x00000040U /*!<Bit 6 */
+#define I2C_OAR1_ADD7 0x00000080U /*!<Bit 7 */
+#define I2C_OAR1_ADD8 0x00000100U /*!<Bit 8 */
+#define I2C_OAR1_ADD9 0x00000200U /*!<Bit 9 */
+
+#define I2C_OAR1_ADDMODE 0x00008000U /*!<Addressing Mode (Slave mode) */
+
+/******************* Bit definition for I2C_OAR2 register *******************/
+#define I2C_OAR2_ENDUAL 0x00000001U /*!<Dual addressing mode enable */
+#define I2C_OAR2_ADD2 0x000000FEU /*!<Interface address */
+
+/******************** Bit definition for I2C_DR register ********************/
+#define I2C_DR_DR 0x000000FFU /*!<8-bit Data Register */
+
+/******************* Bit definition for I2C_SR1 register ********************/
+#define I2C_SR1_SB 0x00000001U /*!<Start Bit (Master mode) */
+#define I2C_SR1_ADDR 0x00000002U /*!<Address sent (master mode)/matched (slave mode) */
+#define I2C_SR1_BTF 0x00000004U /*!<Byte Transfer Finished */
+#define I2C_SR1_ADD10 0x00000008U /*!<10-bit header sent (Master mode) */
+#define I2C_SR1_STOPF 0x00000010U /*!<Stop detection (Slave mode) */
+#define I2C_SR1_RXNE 0x00000040U /*!<Data Register not Empty (receivers) */
+#define I2C_SR1_TXE 0x00000080U /*!<Data Register Empty (transmitters) */
+#define I2C_SR1_BERR 0x00000100U /*!<Bus Error */
+#define I2C_SR1_ARLO 0x00000200U /*!<Arbitration Lost (master mode) */
+#define I2C_SR1_AF 0x00000400U /*!<Acknowledge Failure */
+#define I2C_SR1_OVR 0x00000800U /*!<Overrun/Underrun */
+#define I2C_SR1_PECERR 0x00001000U /*!<PEC Error in reception */
+#define I2C_SR1_TIMEOUT 0x00004000U /*!<Timeout or Tlow Error */
+#define I2C_SR1_SMBALERT 0x00008000U /*!<SMBus Alert */
+
+/******************* Bit definition for I2C_SR2 register ********************/
+#define I2C_SR2_MSL 0x00000001U /*!<Master/Slave */
+#define I2C_SR2_BUSY 0x00000002U /*!<Bus Busy */
+#define I2C_SR2_TRA 0x00000004U /*!<Transmitter/Receiver */
+#define I2C_SR2_GENCALL 0x00000010U /*!<General Call Address (Slave mode) */
+#define I2C_SR2_SMBDEFAULT 0x00000020U /*!<SMBus Device Default Address (Slave mode) */
+#define I2C_SR2_SMBHOST 0x00000040U /*!<SMBus Host Header (Slave mode) */
+#define I2C_SR2_DUALF 0x00000080U /*!<Dual Flag (Slave mode) */
+#define I2C_SR2_PEC 0x0000FF00U /*!<Packet Error Checking Register */
+
+/******************* Bit definition for I2C_CCR register ********************/
+#define I2C_CCR_CCR 0x00000FFFU /*!<Clock Control Register in Fast/Standard mode (Master mode) */
+#define I2C_CCR_DUTY 0x00004000U /*!<Fast Mode Duty Cycle */
+#define I2C_CCR_FS 0x00008000U /*!<I2C Master Mode Selection */
+
+/****************** Bit definition for I2C_TRISE register *******************/
+#define I2C_TRISE_TRISE 0x0000003FU /*!<Maximum Rise Time in Fast/Standard mode (Master mode) */
+
+/****************** Bit definition for I2C_FLTR register *******************/
+#define I2C_FLTR_DNF 0x0000000FU /*!<Digital Noise Filter */
+#define I2C_FLTR_ANOFF 0x00000010U /*!<Analog Noise Filter OFF */
+
+/******************************************************************************/
+/* */
+/* Fast Mode Plus Inter-integrated Circuit Interface (I2C) */
+/* */
+/******************************************************************************/
+/******************* Bit definition for I2C_CR1 register *******************/
+#define FMPI2C_CR1_PE 0x00000001U /*!< Peripheral enable */
+#define FMPI2C_CR1_TXIE 0x00000002U /*!< TX interrupt enable */
+#define FMPI2C_CR1_RXIE 0x00000004U /*!< RX interrupt enable */
+#define FMPI2C_CR1_ADDRIE 0x00000008U /*!< Address match interrupt enable */
+#define FMPI2C_CR1_NACKIE 0x00000010U /*!< NACK received interrupt enable */
+#define FMPI2C_CR1_STOPIE 0x00000020U /*!< STOP detection interrupt enable */
+#define FMPI2C_CR1_TCIE 0x00000040U /*!< Transfer complete interrupt enable */
+#define FMPI2C_CR1_ERRIE 0x00000080U /*!< Errors interrupt enable */
+#define FMPI2C_CR1_DFN 0x00000F00U /*!< Digital noise filter */
+#define FMPI2C_CR1_ANFOFF 0x00001000U /*!< Analog noise filter OFF */
+#define FMPI2C_CR1_TXDMAEN 0x00004000U /*!< DMA transmission requests enable */
+#define FMPI2C_CR1_RXDMAEN 0x00008000U /*!< DMA reception requests enable */
+#define FMPI2C_CR1_SBC 0x00010000U /*!< Slave byte control */
+#define FMPI2C_CR1_NOSTRETCH 0x00020000U /*!< Clock stretching disable */
+#define FMPI2C_CR1_GCEN 0x00080000U /*!< General call enable */
+#define FMPI2C_CR1_SMBHEN 0x00100000U /*!< SMBus host address enable */
+#define FMPI2C_CR1_SMBDEN 0x00200000U /*!< SMBus device default address enable */
+#define FMPI2C_CR1_ALERTEN 0x00400000U /*!< SMBus alert enable */
+#define FMPI2C_CR1_PECEN 0x00800000U /*!< PEC enable */
+
+/****************** Bit definition for I2C_CR2 register ********************/
+#define FMPI2C_CR2_SADD 0x000003FFU /*!< Slave address (master mode) */
+#define FMPI2C_CR2_RD_WRN 0x00000400U /*!< Transfer direction (master mode) */
+#define FMPI2C_CR2_ADD10 0x00000800U /*!< 10-bit addressing mode (master mode) */
+#define FMPI2C_CR2_HEAD10R 0x00001000U /*!< 10-bit address header only read direction (master mode) */
+#define FMPI2C_CR2_START 0x00002000U /*!< START generation */
+#define FMPI2C_CR2_STOP 0x00004000U /*!< STOP generation (master mode) */
+#define FMPI2C_CR2_NACK 0x00008000U /*!< NACK generation (slave mode) */
+#define FMPI2C_CR2_NBYTES 0x00FF0000U /*!< Number of bytes */
+#define FMPI2C_CR2_RELOAD 0x01000000U /*!< NBYTES reload mode */
+#define FMPI2C_CR2_AUTOEND 0x02000000U /*!< Automatic end mode (master mode) */
+#define FMPI2C_CR2_PECBYTE 0x04000000U /*!< Packet error checking byte */
+
+/******************* Bit definition for I2C_OAR1 register ******************/
+#define FMPI2C_OAR1_OA1 0x000003FFU /*!< Interface own address 1 */
+#define FMPI2C_OAR1_OA1MODE 0x00000400U /*!< Own address 1 10-bit mode */
+#define FMPI2C_OAR1_OA1EN 0x00008000U /*!< Own address 1 enable */
+
+/******************* Bit definition for I2C_OAR2 register ******************/
+#define FMPI2C_OAR2_OA2 0x000000FEU /*!< Interface own address 2 */
+#define FMPI2C_OAR2_OA2MSK 0x00000700U /*!< Own address 2 masks */
+#define FMPI2C_OAR2_OA2EN 0x00008000U /*!< Own address 2 enable */
+
+/******************* Bit definition for I2C_TIMINGR register *******************/
+#define FMPI2C_TIMINGR_SCLL 0x000000FFU /*!< SCL low period (master mode) */
+#define FMPI2C_TIMINGR_SCLH 0x0000FF00U /*!< SCL high period (master mode) */
+#define FMPI2C_TIMINGR_SDADEL 0x000F0000U /*!< Data hold time */
+#define FMPI2C_TIMINGR_SCLDEL 0x00F00000U /*!< Data setup time */
+#define FMPI2C_TIMINGR_PRESC 0xF0000000U /*!< Timings prescaler */
+
+/******************* Bit definition for I2C_TIMEOUTR register *******************/
+#define FMPI2C_TIMEOUTR_TIMEOUTA 0x00000FFFU /*!< Bus timeout A */
+#define FMPI2C_TIMEOUTR_TIDLE 0x00001000U /*!< Idle clock timeout detection */
+#define FMPI2C_TIMEOUTR_TIMOUTEN 0x00008000U /*!< Clock timeout enable */
+#define FMPI2C_TIMEOUTR_TIMEOUTB 0x0FFF0000U /*!< Bus timeout B */
+#define FMPI2C_TIMEOUTR_TEXTEN 0x80000000U /*!< Extended clock timeout enable */
+
+/****************** Bit definition for I2C_ISR register *********************/
+#define FMPI2C_ISR_TXE 0x00000001U /*!< Transmit data register empty */
+#define FMPI2C_ISR_TXIS 0x00000002U /*!< Transmit interrupt status */
+#define FMPI2C_ISR_RXNE 0x00000004U /*!< Receive data register not empty */
+#define FMPI2C_ISR_ADDR 0x00000008U /*!< Address matched (slave mode) */
+#define FMPI2C_ISR_NACKF 0x00000010U /*!< NACK received flag */
+#define FMPI2C_ISR_STOPF 0x00000020U /*!< STOP detection flag */
+#define FMPI2C_ISR_TC 0x00000040U /*!< Transfer complete (master mode) */
+#define FMPI2C_ISR_TCR 0x00000080U /*!< Transfer complete reload */
+#define FMPI2C_ISR_BERR 0x00000100U /*!< Bus error */
+#define FMPI2C_ISR_ARLO 0x00000200U /*!< Arbitration lost */
+#define FMPI2C_ISR_OVR 0x00000400U /*!< Overrun/Underrun */
+#define FMPI2C_ISR_PECERR 0x00000800U /*!< PEC error in reception */
+#define FMPI2C_ISR_TIMEOUT 0x00001000U /*!< Timeout or Tlow detection flag */
+#define FMPI2C_ISR_ALERT 0x00002000U /*!< SMBus alert */
+#define FMPI2C_ISR_BUSY 0x00008000U /*!< Bus busy */
+#define FMPI2C_ISR_DIR 0x00010000U /*!< Transfer direction (slave mode) */
+#define FMPI2C_ISR_ADDCODE 0x00FE0000U /*!< Address match code (slave mode) */
+
+/****************** Bit definition for I2C_ICR register *********************/
+#define FMPI2C_ICR_ADDRCF 0x00000008U /*!< Address matched clear flag */
+#define FMPI2C_ICR_NACKCF 0x00000010U /*!< NACK clear flag */
+#define FMPI2C_ICR_STOPCF 0x00000020U /*!< STOP detection clear flag */
+#define FMPI2C_ICR_BERRCF 0x00000100U /*!< Bus error clear flag */
+#define FMPI2C_ICR_ARLOCF 0x00000200U /*!< Arbitration lost clear flag */
+#define FMPI2C_ICR_OVRCF 0x00000400U /*!< Overrun/Underrun clear flag */
+#define FMPI2C_ICR_PECCF 0x00000800U /*!< PAC error clear flag */
+#define FMPI2C_ICR_TIMOUTCF 0x00001000U /*!< Timeout clear flag */
+#define FMPI2C_ICR_ALERTCF 0x00002000U /*!< Alert clear flag */
+
+/****************** Bit definition for I2C_PECR register *********************/
+#define FMPI2C_PECR_PEC 0x000000FFU /*!< PEC register */
+
+/****************** Bit definition for I2C_RXDR register *********************/
+#define FMPI2C_RXDR_RXDATA 0x000000FFU /*!< 8-bit receive data */
+
+/****************** Bit definition for I2C_TXDR register *********************/
+#define FMPI2C_TXDR_TXDATA 0x000000FFU /*!< 8-bit transmit data */
+
+/******************************************************************************/
+/* */
+/* Independent WATCHDOG */
+/* */
+/******************************************************************************/
+/******************* Bit definition for IWDG_KR register ********************/
+#define IWDG_KR_KEY 0xFFFFU /*!<Key value (write only, read 0000h) */
+
+/******************* Bit definition for IWDG_PR register ********************/
+#define IWDG_PR_PR 0x07U /*!<PR[2:0] (Prescaler divider) */
+#define IWDG_PR_PR_0 0x01U /*!<Bit 0 */
+#define IWDG_PR_PR_1 0x02U /*!<Bit 1 */
+#define IWDG_PR_PR_2 0x04U /*!<Bit 2 */
+
+/******************* Bit definition for IWDG_RLR register *******************/
+#define IWDG_RLR_RL 0x0FFFU /*!<Watchdog counter reload value */
+
+/******************* Bit definition for IWDG_SR register ********************/
+#define IWDG_SR_PVU 0x01U /*!<Watchdog prescaler value update */
+#define IWDG_SR_RVU 0x02U /*!<Watchdog counter reload value update */
+
+
+/******************************************************************************/
+/* */
+/* Power Control */
+/* */
+/******************************************************************************/
+/******************** Bit definition for PWR_CR register ********************/
+#define PWR_CR_LPDS 0x00000001U /*!< Low-Power Deepsleep */
+#define PWR_CR_PDDS 0x00000002U /*!< Power Down Deepsleep */
+#define PWR_CR_CWUF 0x00000004U /*!< Clear Wakeup Flag */
+#define PWR_CR_CSBF 0x00000008U /*!< Clear Standby Flag */
+#define PWR_CR_PVDE 0x00000010U /*!< Power Voltage Detector Enable */
+
+#define PWR_CR_PLS 0x000000E0U /*!< PLS[2:0] bits (PVD Level Selection) */
+#define PWR_CR_PLS_0 0x00000020U /*!< Bit 0 */
+#define PWR_CR_PLS_1 0x00000040U /*!< Bit 1 */
+#define PWR_CR_PLS_2 0x00000080U /*!< Bit 2 */
+
+/*!< PVD level configuration */
+#define PWR_CR_PLS_LEV0 0x00000000U /*!< PVD level 0 */
+#define PWR_CR_PLS_LEV1 0x00000020U /*!< PVD level 1 */
+#define PWR_CR_PLS_LEV2 0x00000040U /*!< PVD level 2 */
+#define PWR_CR_PLS_LEV3 0x00000060U /*!< PVD level 3 */
+#define PWR_CR_PLS_LEV4 0x00000080U /*!< PVD level 4 */
+#define PWR_CR_PLS_LEV5 0x000000A0U /*!< PVD level 5 */
+#define PWR_CR_PLS_LEV6 0x000000C0U /*!< PVD level 6 */
+#define PWR_CR_PLS_LEV7 0x000000E0U /*!< PVD level 7 */
+
+#define PWR_CR_DBP 0x00000100U /*!< Disable Backup Domain write protection */
+#define PWR_CR_FPDS 0x00000200U /*!< Flash power down in Stop mode */
+#define PWR_CR_LPLVDS 0x00000400U /*!< Low Power Regulator Low Voltage in Deep Sleep mode */
+#define PWR_CR_MRLVDS 0x00000800U /*!< Main Regulator Low Voltage in Deep Sleep mode */
+#define PWR_CR_ADCDC1 0x00002000U /*!< Refer to AN4073 on how to use this bit */
+
+#define PWR_CR_VOS 0x0000C000U /*!< VOS[1:0] bits (Regulator voltage scaling output selection) */
+#define PWR_CR_VOS_0 0x00004000U /*!< Bit 0 */
+#define PWR_CR_VOS_1 0x00008000U /*!< Bit 1 */
+
+#define PWR_CR_FMSSR 0x00100000U /*!< Flash Memory Sleep System Run */
+#define PWR_CR_FISSR 0x00200000U /*!< Flash Interface Stop while System Run */
+/* Legacy define */
+#define PWR_CR_PMODE PWR_CR_VOS
+
+/******************* Bit definition for PWR_CSR register ********************/
+#define PWR_CSR_WUF 0x00000001U /*!< Wakeup Flag */
+#define PWR_CSR_SBF 0x00000002U /*!< Standby Flag */
+#define PWR_CSR_PVDO 0x00000004U /*!< PVD Output */
+#define PWR_CSR_BRR 0x00000008U /*!< Backup regulator ready */
+#define PWR_CSR_EWUP 0x00000100U /*!< Enable WKUP pin */
+#define PWR_CSR_BRE 0x00000200U /*!< Backup regulator enable */
+#define PWR_CSR_VOSRDY 0x00004000U /*!< Regulator voltage scaling output selection ready */
+
+/* Legacy define */
+#define PWR_CSR_REGRDY PWR_CSR_VOSRDY
+
+/******************************************************************************/
+/* */
+/* Reset and Clock Control */
+/* */
+/******************************************************************************/
+/******************** Bit definition for RCC_CR register ********************/
+#define RCC_CR_HSION 0x00000001U
+#define RCC_CR_HSIRDY 0x00000002U
+
+#define RCC_CR_HSITRIM 0x000000F8U
+#define RCC_CR_HSITRIM_0 0x00000008U/*!<Bit 0 */
+#define RCC_CR_HSITRIM_1 0x00000010U/*!<Bit 1 */
+#define RCC_CR_HSITRIM_2 0x00000020U/*!<Bit 2 */
+#define RCC_CR_HSITRIM_3 0x00000040U/*!<Bit 3 */
+#define RCC_CR_HSITRIM_4 0x00000080U/*!<Bit 4 */
+
+#define RCC_CR_HSICAL 0x0000FF00U
+#define RCC_CR_HSICAL_0 0x00000100U/*!<Bit 0 */
+#define RCC_CR_HSICAL_1 0x00000200U/*!<Bit 1 */
+#define RCC_CR_HSICAL_2 0x00000400U/*!<Bit 2 */
+#define RCC_CR_HSICAL_3 0x00000800U/*!<Bit 3 */
+#define RCC_CR_HSICAL_4 0x00001000U/*!<Bit 4 */
+#define RCC_CR_HSICAL_5 0x00002000U/*!<Bit 5 */
+#define RCC_CR_HSICAL_6 0x00004000U/*!<Bit 6 */
+#define RCC_CR_HSICAL_7 0x00008000U/*!<Bit 7 */
+
+#define RCC_CR_HSEON 0x00010000U
+#define RCC_CR_HSERDY 0x00020000U
+#define RCC_CR_HSEBYP 0x00040000U
+#define RCC_CR_CSSON 0x00080000U
+#define RCC_CR_PLLON 0x01000000U
+#define RCC_CR_PLLRDY 0x02000000U
+
+/******************** Bit definition for RCC_PLLCFGR register ***************/
+#define RCC_PLLCFGR_PLLM 0x0000003FU
+#define RCC_PLLCFGR_PLLM_0 0x00000001U
+#define RCC_PLLCFGR_PLLM_1 0x00000002U
+#define RCC_PLLCFGR_PLLM_2 0x00000004U
+#define RCC_PLLCFGR_PLLM_3 0x00000008U
+#define RCC_PLLCFGR_PLLM_4 0x00000010U
+#define RCC_PLLCFGR_PLLM_5 0x00000020U
+
+#define RCC_PLLCFGR_PLLN 0x00007FC0U
+#define RCC_PLLCFGR_PLLN_0 0x00000040U
+#define RCC_PLLCFGR_PLLN_1 0x00000080U
+#define RCC_PLLCFGR_PLLN_2 0x00000100U
+#define RCC_PLLCFGR_PLLN_3 0x00000200U
+#define RCC_PLLCFGR_PLLN_4 0x00000400U
+#define RCC_PLLCFGR_PLLN_5 0x00000800U
+#define RCC_PLLCFGR_PLLN_6 0x00001000U
+#define RCC_PLLCFGR_PLLN_7 0x00002000U
+#define RCC_PLLCFGR_PLLN_8 0x00004000U
+
+#define RCC_PLLCFGR_PLLP 0x00030000U
+#define RCC_PLLCFGR_PLLP_0 0x00010000U
+#define RCC_PLLCFGR_PLLP_1 0x00020000U
+
+#define RCC_PLLCFGR_PLLSRC 0x00400000U
+#define RCC_PLLCFGR_PLLSRC_HSE 0x00400000U
+#define RCC_PLLCFGR_PLLSRC_HSI 0x00000000U
+
+#define RCC_PLLCFGR_PLLQ 0x0F000000U
+#define RCC_PLLCFGR_PLLQ_0 0x01000000U
+#define RCC_PLLCFGR_PLLQ_1 0x02000000U
+#define RCC_PLLCFGR_PLLQ_2 0x04000000U
+#define RCC_PLLCFGR_PLLQ_3 0x08000000U
+
+#define RCC_PLLCFGR_PLLR 0x70000000U
+#define RCC_PLLCFGR_PLLR_0 0x10000000U
+#define RCC_PLLCFGR_PLLR_1 0x20000000U
+#define RCC_PLLCFGR_PLLR_2 0x40000000U
+/******************** Bit definition for RCC_CFGR register ******************/
+/*!< SW configuration */
+#define RCC_CFGR_SW 0x00000003U /*!< SW[1:0] bits (System clock Switch) */
+#define RCC_CFGR_SW_0 0x00000001U /*!< Bit 0 */
+#define RCC_CFGR_SW_1 0x00000002U /*!< Bit 1 */
+
+#define RCC_CFGR_SW_HSI 0x00000000U /*!< HSI selected as system clock */
+#define RCC_CFGR_SW_HSE 0x00000001U /*!< HSE selected as system clock */
+#define RCC_CFGR_SW_PLL 0x00000002U /*!< PLL selected as system clock */
+
+/*!< SWS configuration */
+#define RCC_CFGR_SWS 0x0000000CU /*!< SWS[1:0] bits (System Clock Switch Status) */
+#define RCC_CFGR_SWS_0 0x00000004U /*!< Bit 0 */
+#define RCC_CFGR_SWS_1 0x00000008U /*!< Bit 1 */
+
+#define RCC_CFGR_SWS_HSI 0x00000000U /*!< HSI oscillator used as system clock */
+#define RCC_CFGR_SWS_HSE 0x00000004U /*!< HSE oscillator used as system clock */
+#define RCC_CFGR_SWS_PLL 0x00000008U /*!< PLL used as system clock */
+
+/*!< HPRE configuration */
+#define RCC_CFGR_HPRE 0x000000F0U /*!< HPRE[3:0] bits (AHB prescaler) */
+#define RCC_CFGR_HPRE_0 0x00000010U /*!< Bit 0 */
+#define RCC_CFGR_HPRE_1 0x00000020U /*!< Bit 1 */
+#define RCC_CFGR_HPRE_2 0x00000040U /*!< Bit 2 */
+#define RCC_CFGR_HPRE_3 0x00000080U /*!< Bit 3 */
+
+#define RCC_CFGR_HPRE_DIV1 0x00000000U /*!< SYSCLK not divided */
+#define RCC_CFGR_HPRE_DIV2 0x00000080U /*!< SYSCLK divided by 2 */
+#define RCC_CFGR_HPRE_DIV4 0x00000090U /*!< SYSCLK divided by 4 */
+#define RCC_CFGR_HPRE_DIV8 0x000000A0U /*!< SYSCLK divided by 8 */
+#define RCC_CFGR_HPRE_DIV16 0x000000B0U /*!< SYSCLK divided by 16 */
+#define RCC_CFGR_HPRE_DIV64 0x000000C0U /*!< SYSCLK divided by 64 */
+#define RCC_CFGR_HPRE_DIV128 0x000000D0U /*!< SYSCLK divided by 128 */
+#define RCC_CFGR_HPRE_DIV256 0x000000E0U /*!< SYSCLK divided by 256 */
+#define RCC_CFGR_HPRE_DIV512 0x000000F0U /*!< SYSCLK divided by 512 */
+
+/*!< MCO1EN configuration */
+#define RCC_CFGR_MCO1EN 0x00000100U /*!< MCO1EN bit */
+
+/*!< PPRE1 configuration */
+#define RCC_CFGR_PPRE1 0x00001C00U /*!< PRE1[2:0] bits (APB1 prescaler) */
+#define RCC_CFGR_PPRE1_0 0x00000400U /*!< Bit 0 */
+#define RCC_CFGR_PPRE1_1 0x00000800U /*!< Bit 1 */
+#define RCC_CFGR_PPRE1_2 0x00001000U /*!< Bit 2 */
+
+#define RCC_CFGR_PPRE1_DIV1 0x00000000U /*!< HCLK not divided */
+#define RCC_CFGR_PPRE1_DIV2 0x00001000U /*!< HCLK divided by 2 */
+#define RCC_CFGR_PPRE1_DIV4 0x00001400U /*!< HCLK divided by 4 */
+#define RCC_CFGR_PPRE1_DIV8 0x00001800U /*!< HCLK divided by 8 */
+#define RCC_CFGR_PPRE1_DIV16 0x00001C00U /*!< HCLK divided by 16 */
+
+/*!< PPRE2 configuration */
+#define RCC_CFGR_PPRE2 0x0000E000U /*!< PRE2[2:0] bits (APB2 prescaler) */
+#define RCC_CFGR_PPRE2_0 0x00002000U /*!< Bit 0 */
+#define RCC_CFGR_PPRE2_1 0x00004000U /*!< Bit 1 */
+#define RCC_CFGR_PPRE2_2 0x00008000U /*!< Bit 2 */
+
+#define RCC_CFGR_PPRE2_DIV1 0x00000000U /*!< HCLK not divided */
+#define RCC_CFGR_PPRE2_DIV2 0x00008000U /*!< HCLK divided by 2 */
+#define RCC_CFGR_PPRE2_DIV4 0x0000A000U /*!< HCLK divided by 4 */
+#define RCC_CFGR_PPRE2_DIV8 0x0000C000U /*!< HCLK divided by 8 */
+#define RCC_CFGR_PPRE2_DIV16 0x0000E000U /*!< HCLK divided by 16 */
+
+/*!< RTCPRE configuration */
+#define RCC_CFGR_RTCPRE 0x001F0000U
+#define RCC_CFGR_RTCPRE_0 0x00010000U
+#define RCC_CFGR_RTCPRE_1 0x00020000U
+#define RCC_CFGR_RTCPRE_2 0x00040000U
+#define RCC_CFGR_RTCPRE_3 0x00080000U
+#define RCC_CFGR_RTCPRE_4 0x00100000U
+
+/*!< MCO1 configuration */
+#define RCC_CFGR_MCO1 0x00600000U
+#define RCC_CFGR_MCO1_0 0x00200000U
+#define RCC_CFGR_MCO1_1 0x00400000U
+
+#define RCC_CFGR_MCO1PRE 0x07000000U
+#define RCC_CFGR_MCO1PRE_0 0x01000000U
+#define RCC_CFGR_MCO1PRE_1 0x02000000U
+#define RCC_CFGR_MCO1PRE_2 0x04000000U
+
+#define RCC_CFGR_MCO2PRE 0x38000000U
+#define RCC_CFGR_MCO2PRE_0 0x08000000U
+#define RCC_CFGR_MCO2PRE_1 0x10000000U
+#define RCC_CFGR_MCO2PRE_2 0x20000000U
+
+#define RCC_CFGR_MCO2 0xC0000000U
+#define RCC_CFGR_MCO2_0 0x40000000U
+#define RCC_CFGR_MCO2_1 0x80000000U
+
+/******************** Bit definition for RCC_CIR register *******************/
+#define RCC_CIR_LSIRDYF 0x00000001U
+#define RCC_CIR_LSERDYF 0x00000002U
+#define RCC_CIR_HSIRDYF 0x00000004U
+#define RCC_CIR_HSERDYF 0x00000008U
+#define RCC_CIR_PLLRDYF 0x00000010U
+
+#define RCC_CIR_CSSF 0x00000080U
+#define RCC_CIR_LSIRDYIE 0x00000100U
+#define RCC_CIR_LSERDYIE 0x00000200U
+#define RCC_CIR_HSIRDYIE 0x00000400U
+#define RCC_CIR_HSERDYIE 0x00000800U
+#define RCC_CIR_PLLRDYIE 0x00001000U
+
+#define RCC_CIR_LSIRDYC 0x00010000U
+#define RCC_CIR_LSERDYC 0x00020000U
+#define RCC_CIR_HSIRDYC 0x00040000U
+#define RCC_CIR_HSERDYC 0x00080000U
+#define RCC_CIR_PLLRDYC 0x00100000U
+
+#define RCC_CIR_CSSC 0x00800000U
+
+/******************** Bit definition for RCC_AHB1RSTR register **************/
+#define RCC_AHB1RSTR_GPIOARST 0x00000001U
+#define RCC_AHB1RSTR_GPIOBRST 0x00000002U
+#define RCC_AHB1RSTR_GPIOCRST 0x00000004U
+#define RCC_AHB1RSTR_GPIOHRST 0x00000080U
+#define RCC_AHB1RSTR_CRCRST 0x00001000U
+#define RCC_AHB1RSTR_DMA1RST 0x00200000U
+#define RCC_AHB1RSTR_DMA2RST 0x00400000U
+#define RCC_AHB1RSTR_RNGRST 0x80000000U
+
+/******************** Bit definition for RCC_APB1RSTR register **************/
+#define RCC_APB1RSTR_TIM5RST 0x00000008U
+#define RCC_APB1RSTR_TIM6RST 0x00000010U
+#define RCC_APB1RSTR_LPTIM1RST 0x00000200U
+#define RCC_APB1RSTR_WWDGRST 0x00000800U
+#define RCC_APB1RSTR_SPI2RST 0x00004000U
+#define RCC_APB1RSTR_USART2RST 0x00020000U
+#define RCC_APB1RSTR_I2C1RST 0x00200000U
+#define RCC_APB1RSTR_I2C2RST 0x00400000U
+#define RCC_APB1RSTR_FMPI2C1RST 0x01000000U
+#define RCC_APB1RSTR_PWRRST 0x10000000U
+#define RCC_APB1RSTR_DACRST 0x20000000U
+
+/******************** Bit definition for RCC_APB2RSTR register **************/
+#define RCC_APB2RSTR_TIM1RST 0x00000001U
+#define RCC_APB2RSTR_USART1RST 0x00000010U
+#define RCC_APB2RSTR_USART6RST 0x00000020U
+#define RCC_APB2RSTR_ADCRST 0x00000100U
+#define RCC_APB2RSTR_SPI1RST 0x00001000U
+#define RCC_APB2RSTR_SYSCFGRST 0x00004000U
+#define RCC_APB2RSTR_TIM9RST 0x00010000U
+#define RCC_APB2RSTR_TIM11RST 0x00040000U
+#define RCC_APB2RSTR_SPI5RST 0x00100000U
+
+/******************** Bit definition for RCC_AHB1ENR register ***************/
+#define RCC_AHB1ENR_GPIOAEN 0x00000001U
+#define RCC_AHB1ENR_GPIOBEN 0x00000002U
+#define RCC_AHB1ENR_GPIOCEN 0x00000004U
+#define RCC_AHB1ENR_GPIOHEN 0x00000080U
+#define RCC_AHB1ENR_CRCEN 0x00001000U
+#define RCC_AHB1ENR_DMA1EN 0x00200000U
+#define RCC_AHB1ENR_DMA2EN 0x00400000U
+#define RCC_AHB1ENR_RNGEN 0x80000000U
+
+/******************** Bit definition for RCC_APB1ENR register ***************/
+#define RCC_APB1ENR_TIM5EN 0x00000008U
+#define RCC_APB1ENR_TIM6EN 0x00000010U
+#define RCC_APB1ENR_LPTIM1EN 0x00000200U
+#define RCC_APB1ENR_RTCAPBEN 0x00000400U
+#define RCC_APB1ENR_WWDGEN 0x00000800U
+#define RCC_APB1ENR_SPI2EN 0x00004000U
+#define RCC_APB1ENR_USART2EN 0x00020000U
+#define RCC_APB1ENR_I2C1EN 0x00200000U
+#define RCC_APB1ENR_I2C2EN 0x00400000U
+#define RCC_APB1ENR_FMPI2C1EN 0x01000000U
+#define RCC_APB1ENR_PWREN 0x10000000U
+#define RCC_APB1ENR_DACEN 0x20000000U
+
+/******************** Bit definition for RCC_APB2ENR register ***************/
+#define RCC_APB2ENR_TIM1EN 0x00000001U
+#define RCC_APB2ENR_USART1EN 0x00000010U
+#define RCC_APB2ENR_USART6EN 0x00000020U
+#define RCC_APB2ENR_ADC1EN 0x00000100U
+#define RCC_APB2ENR_SPI1EN 0x00001000U
+#define RCC_APB2ENR_SYSCFGEN 0x00004000U
+#define RCC_APB2ENR_EXTITEN 0x00008000U
+#define RCC_APB2ENR_TIM9EN 0x00010000U
+#define RCC_APB2ENR_TIM11EN 0x00040000U
+#define RCC_APB2ENR_SPI5EN 0x00100000U
+
+/******************** Bit definition for RCC_AHB1LPENR register *************/
+#define RCC_AHB1LPENR_GPIOALPEN 0x00000001U
+#define RCC_AHB1LPENR_GPIOBLPEN 0x00000002U
+#define RCC_AHB1LPENR_GPIOCLPEN 0x00000004U
+#define RCC_AHB1LPENR_GPIOHLPEN 0x00000080U
+#define RCC_AHB1LPENR_CRCLPEN 0x00001000U
+#define RCC_AHB1LPENR_FLITFLPEN 0x00008000U
+#define RCC_AHB1LPENR_SRAM1LPEN 0x00010000U
+#define RCC_AHB1LPENR_DMA1LPEN 0x00200000U
+#define RCC_AHB1LPENR_DMA2LPEN 0x00400000U
+#define RCC_AHB1LPENR_RNGLPEN 0x80000000U
+
+/******************** Bit definition for RCC_APB1LPENR register *************/
+#define RCC_APB1LPENR_TIM5LPEN 0x00000008U
+#define RCC_APB1LPENR_TIM6LPEN 0x00000010U
+#define RCC_APB1LPENR_LPTIM1LPEN 0x00000200U
+#define RCC_APB1LPENR_RTCAPBLPEN 0x00000400U
+#define RCC_APB1LPENR_WWDGLPEN 0x00000800U
+#define RCC_APB1LPENR_SPI2LPEN 0x00004000U
+#define RCC_APB1LPENR_USART2LPEN 0x00020000U
+#define RCC_APB1LPENR_I2C1LPEN 0x00200000U
+#define RCC_APB1LPENR_I2C2LPEN 0x00400000U
+#define RCC_APB1LPENR_FMPI2C1LPEN 0x01000000U
+#define RCC_APB1LPENR_PWRLPEN 0x10000000U
+#define RCC_APB1LPENR_DACLPEN 0x20000000U
+
+/******************** Bit definition for RCC_APB2LPENR register *************/
+#define RCC_APB2LPENR_TIM1LPEN 0x00000001U
+#define RCC_APB2LPENR_USART1LPEN 0x00000010U
+#define RCC_APB2LPENR_USART6LPEN 0x00000020U
+#define RCC_APB2LPENR_ADC1LPEN 0x00000100U
+#define RCC_APB2LPENR_SPI1LPEN 0x00001000U
+#define RCC_APB2LPENR_SYSCFGLPEN 0x00004000U
+#define RCC_APB2LPENR_EXTITLPEN 0x00008000U
+#define RCC_APB2LPENR_TIM9LPEN 0x00010000U
+#define RCC_APB2LPENR_TIM11LPEN 0x00040000U
+#define RCC_APB2LPENR_SPI5LPEN 0x00100000U
+
+/******************** Bit definition for RCC_BDCR register ******************/
+#define RCC_BDCR_LSEON 0x00000001U
+#define RCC_BDCR_LSERDY 0x00000002U
+#define RCC_BDCR_LSEBYP 0x00000004U
+#define RCC_BDCR_LSEMOD 0x00000008U
+
+#define RCC_BDCR_RTCSEL 0x00000300U
+#define RCC_BDCR_RTCSEL_0 0x00000100U
+#define RCC_BDCR_RTCSEL_1 0x00000200U
+
+#define RCC_BDCR_RTCEN 0x00008000U
+#define RCC_BDCR_BDRST 0x00010000U
+
+/******************** Bit definition for RCC_CSR register *******************/
+#define RCC_CSR_LSION 0x00000001U
+#define RCC_CSR_LSIRDY 0x00000002U
+#define RCC_CSR_RMVF 0x01000000U
+#define RCC_CSR_BORRSTF 0x02000000U
+#define RCC_CSR_PADRSTF 0x04000000U
+#define RCC_CSR_PORRSTF 0x08000000U
+#define RCC_CSR_SFTRSTF 0x10000000U
+#define RCC_CSR_WDGRSTF 0x20000000U
+#define RCC_CSR_WWDGRSTF 0x40000000U
+#define RCC_CSR_LPWRRSTF 0x80000000U
+
+/******************** Bit definition for RCC_SSCGR register *****************/
+#define RCC_SSCGR_MODPER 0x00001FFFU
+#define RCC_SSCGR_INCSTEP 0x0FFFE000U
+#define RCC_SSCGR_SPREADSEL 0x40000000U
+#define RCC_SSCGR_SSCGEN 0x80000000U
+
+/******************** Bit definition for RCC_DCKCFGR register ***************/
+#define RCC_DCKCFGR_TIMPRE 0x01000000U
+#define RCC_DCKCFGR_I2SSRC 0x06000000U
+#define RCC_DCKCFGR_I2SSRC_0 0x02000000U
+#define RCC_DCKCFGR_I2SSRC_1 0x04000000U
+
+/******************** Bit definition for RCC_CKGATENR register **************/
+#define RCC_CKGATENR_AHB2APB1_CKEN 0x00000001U
+#define RCC_CKGATENR_AHB2APB2_CKEN 0x00000002U
+#define RCC_CKGATENR_CM4DBG_CKEN 0x00000004U
+#define RCC_CKGATENR_SPARE_CKEN 0x00000008U
+#define RCC_CKGATENR_SRAM_CKEN 0x00000010U
+#define RCC_CKGATENR_FLITF_CKEN 0x00000020U
+#define RCC_CKGATENR_RCC_CKEN 0x00000040U
+
+/******************** Bit definition for RCC_DCKCFGR2 register **************/
+#define RCC_DCKCFGR2_FMPI2C1SEL 0x00C00000U
+#define RCC_DCKCFGR2_FMPI2C1SEL_0 0x00400000U
+#define RCC_DCKCFGR2_FMPI2C1SEL_1 0x00800000U
+#define RCC_DCKCFGR2_LPTIM1SEL 0xC0000000U
+#define RCC_DCKCFGR2_LPTIM1SEL_0 0x40000000U
+#define RCC_DCKCFGR2_LPTIM1SEL_1 0x80000000U
+
+/******************************************************************************/
+/* */
+/* RNG */
+/* */
+/******************************************************************************/
+/******************** Bits definition for RNG_CR register *******************/
+#define RNG_CR_RNGEN 0x00000004U
+#define RNG_CR_IE 0x00000008U
+
+/******************** Bits definition for RNG_SR register *******************/
+#define RNG_SR_DRDY 0x00000001U
+#define RNG_SR_CECS 0x00000002U
+#define RNG_SR_SECS 0x00000004U
+#define RNG_SR_CEIS 0x00000020U
+#define RNG_SR_SEIS 0x00000040U
+
+/******************************************************************************/
+/* */
+/* Real-Time Clock (RTC) */
+/* */
+/******************************************************************************/
+/******************** Bits definition for RTC_TR register *******************/
+#define RTC_TR_PM 0x00400000U
+#define RTC_TR_HT 0x00300000U
+#define RTC_TR_HT_0 0x00100000U
+#define RTC_TR_HT_1 0x00200000U
+#define RTC_TR_HU 0x000F0000U
+#define RTC_TR_HU_0 0x00010000U
+#define RTC_TR_HU_1 0x00020000U
+#define RTC_TR_HU_2 0x00040000U
+#define RTC_TR_HU_3 0x00080000U
+#define RTC_TR_MNT 0x00007000U
+#define RTC_TR_MNT_0 0x00001000U
+#define RTC_TR_MNT_1 0x00002000U
+#define RTC_TR_MNT_2 0x00004000U
+#define RTC_TR_MNU 0x00000F00U
+#define RTC_TR_MNU_0 0x00000100U
+#define RTC_TR_MNU_1 0x00000200U
+#define RTC_TR_MNU_2 0x00000400U
+#define RTC_TR_MNU_3 0x00000800U
+#define RTC_TR_ST 0x00000070U
+#define RTC_TR_ST_0 0x00000010U
+#define RTC_TR_ST_1 0x00000020U
+#define RTC_TR_ST_2 0x00000040U
+#define RTC_TR_SU 0x0000000FU
+#define RTC_TR_SU_0 0x00000001U
+#define RTC_TR_SU_1 0x00000002U
+#define RTC_TR_SU_2 0x00000004U
+#define RTC_TR_SU_3 0x00000008U
+
+/******************** Bits definition for RTC_DR register *******************/
+#define RTC_DR_YT 0x00F00000U
+#define RTC_DR_YT_0 0x00100000U
+#define RTC_DR_YT_1 0x00200000U
+#define RTC_DR_YT_2 0x00400000U
+#define RTC_DR_YT_3 0x00800000U
+#define RTC_DR_YU 0x000F0000U
+#define RTC_DR_YU_0 0x00010000U
+#define RTC_DR_YU_1 0x00020000U
+#define RTC_DR_YU_2 0x00040000U
+#define RTC_DR_YU_3 0x00080000U
+#define RTC_DR_WDU 0x0000E000U
+#define RTC_DR_WDU_0 0x00002000U
+#define RTC_DR_WDU_1 0x00004000U
+#define RTC_DR_WDU_2 0x00008000U
+#define RTC_DR_MT 0x00001000U
+#define RTC_DR_MU 0x00000F00U
+#define RTC_DR_MU_0 0x00000100U
+#define RTC_DR_MU_1 0x00000200U
+#define RTC_DR_MU_2 0x00000400U
+#define RTC_DR_MU_3 0x00000800U
+#define RTC_DR_DT 0x00000030U
+#define RTC_DR_DT_0 0x00000010U
+#define RTC_DR_DT_1 0x00000020U
+#define RTC_DR_DU 0x0000000FU
+#define RTC_DR_DU_0 0x00000001U
+#define RTC_DR_DU_1 0x00000002U
+#define RTC_DR_DU_2 0x00000004U
+#define RTC_DR_DU_3 0x00000008U
+
+/******************** Bits definition for RTC_CR register *******************/
+#define RTC_CR_COE 0x00800000U
+#define RTC_CR_OSEL 0x00600000U
+#define RTC_CR_OSEL_0 0x00200000U
+#define RTC_CR_OSEL_1 0x00400000U
+#define RTC_CR_POL 0x00100000U
+#define RTC_CR_COSEL 0x00080000U
+#define RTC_CR_BCK 0x00040000U
+#define RTC_CR_SUB1H 0x00020000U
+#define RTC_CR_ADD1H 0x00010000U
+#define RTC_CR_TSIE 0x00008000U
+#define RTC_CR_WUTIE 0x00004000U
+#define RTC_CR_ALRBIE 0x00002000U
+#define RTC_CR_ALRAIE 0x00001000U
+#define RTC_CR_TSE 0x00000800U
+#define RTC_CR_WUTE 0x00000400U
+#define RTC_CR_ALRBE 0x00000200U
+#define RTC_CR_ALRAE 0x00000100U
+#define RTC_CR_DCE 0x00000080U
+#define RTC_CR_FMT 0x00000040U
+#define RTC_CR_BYPSHAD 0x00000020U
+#define RTC_CR_REFCKON 0x00000010U
+#define RTC_CR_TSEDGE 0x00000008U
+#define RTC_CR_WUCKSEL 0x00000007U
+#define RTC_CR_WUCKSEL_0 0x00000001U
+#define RTC_CR_WUCKSEL_1 0x00000002U
+#define RTC_CR_WUCKSEL_2 0x00000004U
+
+/******************** Bits definition for RTC_ISR register ******************/
+#define RTC_ISR_RECALPF 0x00010000U
+#define RTC_ISR_TAMP1F 0x00002000U
+#define RTC_ISR_TAMP2F 0x00004000U
+#define RTC_ISR_TSOVF 0x00001000U
+#define RTC_ISR_TSF 0x00000800U
+#define RTC_ISR_WUTF 0x00000400U
+#define RTC_ISR_ALRBF 0x00000200U
+#define RTC_ISR_ALRAF 0x00000100U
+#define RTC_ISR_INIT 0x00000080U
+#define RTC_ISR_INITF 0x00000040U
+#define RTC_ISR_RSF 0x00000020U
+#define RTC_ISR_INITS 0x00000010U
+#define RTC_ISR_SHPF 0x00000008U
+#define RTC_ISR_WUTWF 0x00000004U
+#define RTC_ISR_ALRBWF 0x00000002U
+#define RTC_ISR_ALRAWF 0x00000001U
+
+/******************** Bits definition for RTC_PRER register *****************/
+#define RTC_PRER_PREDIV_A 0x007F0000U
+#define RTC_PRER_PREDIV_S 0x00007FFFU
+
+/******************** Bits definition for RTC_WUTR register *****************/
+#define RTC_WUTR_WUT 0x0000FFFFU
+
+/******************** Bits definition for RTC_CALIBR register ***************/
+#define RTC_CALIBR_DCS 0x00000080U
+#define RTC_CALIBR_DC 0x0000001FU
+
+/******************** Bits definition for RTC_ALRMAR register ***************/
+#define RTC_ALRMAR_MSK4 0x80000000U
+#define RTC_ALRMAR_WDSEL 0x40000000U
+#define RTC_ALRMAR_DT 0x30000000U
+#define RTC_ALRMAR_DT_0 0x10000000U
+#define RTC_ALRMAR_DT_1 0x20000000U
+#define RTC_ALRMAR_DU 0x0F000000U
+#define RTC_ALRMAR_DU_0 0x01000000U
+#define RTC_ALRMAR_DU_1 0x02000000U
+#define RTC_ALRMAR_DU_2 0x04000000U
+#define RTC_ALRMAR_DU_3 0x08000000U
+#define RTC_ALRMAR_MSK3 0x00800000U
+#define RTC_ALRMAR_PM 0x00400000U
+#define RTC_ALRMAR_HT 0x00300000U
+#define RTC_ALRMAR_HT_0 0x00100000U
+#define RTC_ALRMAR_HT_1 0x00200000U
+#define RTC_ALRMAR_HU 0x000F0000U
+#define RTC_ALRMAR_HU_0 0x00010000U
+#define RTC_ALRMAR_HU_1 0x00020000U
+#define RTC_ALRMAR_HU_2 0x00040000U
+#define RTC_ALRMAR_HU_3 0x00080000U
+#define RTC_ALRMAR_MSK2 0x00008000U
+#define RTC_ALRMAR_MNT 0x00007000U
+#define RTC_ALRMAR_MNT_0 0x00001000U
+#define RTC_ALRMAR_MNT_1 0x00002000U
+#define RTC_ALRMAR_MNT_2 0x00004000U
+#define RTC_ALRMAR_MNU 0x00000F00U
+#define RTC_ALRMAR_MNU_0 0x00000100U
+#define RTC_ALRMAR_MNU_1 0x00000200U
+#define RTC_ALRMAR_MNU_2 0x00000400U
+#define RTC_ALRMAR_MNU_3 0x00000800U
+#define RTC_ALRMAR_MSK1 0x00000080U
+#define RTC_ALRMAR_ST 0x00000070U
+#define RTC_ALRMAR_ST_0 0x00000010U
+#define RTC_ALRMAR_ST_1 0x00000020U
+#define RTC_ALRMAR_ST_2 0x00000040U
+#define RTC_ALRMAR_SU 0x0000000FU
+#define RTC_ALRMAR_SU_0 0x00000001U
+#define RTC_ALRMAR_SU_1 0x00000002U
+#define RTC_ALRMAR_SU_2 0x00000004U
+#define RTC_ALRMAR_SU_3 0x00000008U
+
+/******************** Bits definition for RTC_ALRMBR register ***************/
+#define RTC_ALRMBR_MSK4 0x80000000U
+#define RTC_ALRMBR_WDSEL 0x40000000U
+#define RTC_ALRMBR_DT 0x30000000U
+#define RTC_ALRMBR_DT_0 0x10000000U
+#define RTC_ALRMBR_DT_1 0x20000000U
+#define RTC_ALRMBR_DU 0x0F000000U
+#define RTC_ALRMBR_DU_0 0x01000000U
+#define RTC_ALRMBR_DU_1 0x02000000U
+#define RTC_ALRMBR_DU_2 0x04000000U
+#define RTC_ALRMBR_DU_3 0x08000000U
+#define RTC_ALRMBR_MSK3 0x00800000U
+#define RTC_ALRMBR_PM 0x00400000U
+#define RTC_ALRMBR_HT 0x00300000U
+#define RTC_ALRMBR_HT_0 0x00100000U
+#define RTC_ALRMBR_HT_1 0x00200000U
+#define RTC_ALRMBR_HU 0x000F0000U
+#define RTC_ALRMBR_HU_0 0x00010000U
+#define RTC_ALRMBR_HU_1 0x00020000U
+#define RTC_ALRMBR_HU_2 0x00040000U
+#define RTC_ALRMBR_HU_3 0x00080000U
+#define RTC_ALRMBR_MSK2 0x00008000U
+#define RTC_ALRMBR_MNT 0x00007000U
+#define RTC_ALRMBR_MNT_0 0x00001000U
+#define RTC_ALRMBR_MNT_1 0x00002000U
+#define RTC_ALRMBR_MNT_2 0x00004000U
+#define RTC_ALRMBR_MNU 0x00000F00U
+#define RTC_ALRMBR_MNU_0 0x00000100U
+#define RTC_ALRMBR_MNU_1 0x00000200U
+#define RTC_ALRMBR_MNU_2 0x00000400U
+#define RTC_ALRMBR_MNU_3 0x00000800U
+#define RTC_ALRMBR_MSK1 0x00000080U
+#define RTC_ALRMBR_ST 0x00000070U
+#define RTC_ALRMBR_ST_0 0x00000010U
+#define RTC_ALRMBR_ST_1 0x00000020U
+#define RTC_ALRMBR_ST_2 0x00000040U
+#define RTC_ALRMBR_SU 0x0000000FU
+#define RTC_ALRMBR_SU_0 0x00000001U
+#define RTC_ALRMBR_SU_1 0x00000002U
+#define RTC_ALRMBR_SU_2 0x00000004U
+#define RTC_ALRMBR_SU_3 0x00000008U
+
+/******************** Bits definition for RTC_WPR register ******************/
+#define RTC_WPR_KEY 0x000000FFU
+
+/******************** Bits definition for RTC_SSR register ******************/
+#define RTC_SSR_SS 0x0000FFFFU
+
+/******************** Bits definition for RTC_SHIFTR register ***************/
+#define RTC_SHIFTR_SUBFS 0x00007FFFU
+#define RTC_SHIFTR_ADD1S 0x80000000U
+
+/******************** Bits definition for RTC_TSTR register *****************/
+#define RTC_TSTR_PM 0x00400000U
+#define RTC_TSTR_HT 0x00300000U
+#define RTC_TSTR_HT_0 0x00100000U
+#define RTC_TSTR_HT_1 0x00200000U
+#define RTC_TSTR_HU 0x000F0000U
+#define RTC_TSTR_HU_0 0x00010000U
+#define RTC_TSTR_HU_1 0x00020000U
+#define RTC_TSTR_HU_2 0x00040000U
+#define RTC_TSTR_HU_3 0x00080000U
+#define RTC_TSTR_MNT 0x00007000U
+#define RTC_TSTR_MNT_0 0x00001000U
+#define RTC_TSTR_MNT_1 0x00002000U
+#define RTC_TSTR_MNT_2 0x00004000U
+#define RTC_TSTR_MNU 0x00000F00U
+#define RTC_TSTR_MNU_0 0x00000100U
+#define RTC_TSTR_MNU_1 0x00000200U
+#define RTC_TSTR_MNU_2 0x00000400U
+#define RTC_TSTR_MNU_3 0x00000800U
+#define RTC_TSTR_ST 0x00000070U
+#define RTC_TSTR_ST_0 0x00000010U
+#define RTC_TSTR_ST_1 0x00000020U
+#define RTC_TSTR_ST_2 0x00000040U
+#define RTC_TSTR_SU 0x0000000FU
+#define RTC_TSTR_SU_0 0x00000001U
+#define RTC_TSTR_SU_1 0x00000002U
+#define RTC_TSTR_SU_2 0x00000004U
+#define RTC_TSTR_SU_3 0x00000008U
+
+/******************** Bits definition for RTC_TSDR register *****************/
+#define RTC_TSDR_WDU 0x0000E000U
+#define RTC_TSDR_WDU_0 0x00002000U
+#define RTC_TSDR_WDU_1 0x00004000U
+#define RTC_TSDR_WDU_2 0x00008000U
+#define RTC_TSDR_MT 0x00001000U
+#define RTC_TSDR_MU 0x00000F00U
+#define RTC_TSDR_MU_0 0x00000100U
+#define RTC_TSDR_MU_1 0x00000200U
+#define RTC_TSDR_MU_2 0x00000400U
+#define RTC_TSDR_MU_3 0x00000800U
+#define RTC_TSDR_DT 0x00000030U
+#define RTC_TSDR_DT_0 0x00000010U
+#define RTC_TSDR_DT_1 0x00000020U
+#define RTC_TSDR_DU 0x0000000FU
+#define RTC_TSDR_DU_0 0x00000001U
+#define RTC_TSDR_DU_1 0x00000002U
+#define RTC_TSDR_DU_2 0x00000004U
+#define RTC_TSDR_DU_3 0x00000008U
+
+/******************** Bits definition for RTC_TSSSR register ****************/
+#define RTC_TSSSR_SS 0x0000FFFFU
+
+/******************** Bits definition for RTC_CAL register *****************/
+#define RTC_CALR_CALP 0x00008000U
+#define RTC_CALR_CALW8 0x00004000U
+#define RTC_CALR_CALW16 0x00002000U
+#define RTC_CALR_CALM 0x000001FFU
+#define RTC_CALR_CALM_0 0x00000001U
+#define RTC_CALR_CALM_1 0x00000002U
+#define RTC_CALR_CALM_2 0x00000004U
+#define RTC_CALR_CALM_3 0x00000008U
+#define RTC_CALR_CALM_4 0x00000010U
+#define RTC_CALR_CALM_5 0x00000020U
+#define RTC_CALR_CALM_6 0x00000040U
+#define RTC_CALR_CALM_7 0x00000080U
+#define RTC_CALR_CALM_8 0x00000100U
+
+/******************** Bits definition for RTC_TAFCR register ****************/
+#define RTC_TAFCR_ALARMOUTTYPE 0x00040000U
+#define RTC_TAFCR_TSINSEL 0x00020000U
+#define RTC_TAFCR_TAMPINSEL 0x00010000U
+#define RTC_TAFCR_TAMPPUDIS 0x00008000U
+#define RTC_TAFCR_TAMPPRCH 0x00006000U
+#define RTC_TAFCR_TAMPPRCH_0 0x00002000U
+#define RTC_TAFCR_TAMPPRCH_1 0x00004000U
+#define RTC_TAFCR_TAMPFLT 0x00001800U
+#define RTC_TAFCR_TAMPFLT_0 0x00000800U
+#define RTC_TAFCR_TAMPFLT_1 0x00001000U
+#define RTC_TAFCR_TAMPFREQ 0x00000700U
+#define RTC_TAFCR_TAMPFREQ_0 0x00000100U
+#define RTC_TAFCR_TAMPFREQ_1 0x00000200U
+#define RTC_TAFCR_TAMPFREQ_2 0x00000400U
+#define RTC_TAFCR_TAMPTS 0x00000080U
+#define RTC_TAFCR_TAMP2TRG 0x00000010U
+#define RTC_TAFCR_TAMP2E 0x00000008U
+#define RTC_TAFCR_TAMPIE 0x00000004U
+#define RTC_TAFCR_TAMP1TRG 0x00000002U
+#define RTC_TAFCR_TAMP1E 0x00000001U
+
+/******************** Bits definition for RTC_ALRMASSR register *************/
+#define RTC_ALRMASSR_MASKSS 0x0F000000U
+#define RTC_ALRMASSR_MASKSS_0 0x01000000U
+#define RTC_ALRMASSR_MASKSS_1 0x02000000U
+#define RTC_ALRMASSR_MASKSS_2 0x04000000U
+#define RTC_ALRMASSR_MASKSS_3 0x08000000U
+#define RTC_ALRMASSR_SS 0x00007FFFU
+
+/******************** Bits definition for RTC_ALRMBSSR register *************/
+#define RTC_ALRMBSSR_MASKSS 0x0F000000U
+#define RTC_ALRMBSSR_MASKSS_0 0x01000000U
+#define RTC_ALRMBSSR_MASKSS_1 0x02000000U
+#define RTC_ALRMBSSR_MASKSS_2 0x04000000U
+#define RTC_ALRMBSSR_MASKSS_3 0x08000000U
+#define RTC_ALRMBSSR_SS 0x00007FFFU
+
+/******************** Bits definition for RTC_BKP0R register ****************/
+#define RTC_BKP0R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP1R register ****************/
+#define RTC_BKP1R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP2R register ****************/
+#define RTC_BKP2R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP3R register ****************/
+#define RTC_BKP3R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP4R register ****************/
+#define RTC_BKP4R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP5R register ****************/
+#define RTC_BKP5R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP6R register ****************/
+#define RTC_BKP6R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP7R register ****************/
+#define RTC_BKP7R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP8R register ****************/
+#define RTC_BKP8R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP9R register ****************/
+#define RTC_BKP9R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP10R register ***************/
+#define RTC_BKP10R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP11R register ***************/
+#define RTC_BKP11R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP12R register ***************/
+#define RTC_BKP12R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP13R register ***************/
+#define RTC_BKP13R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP14R register ***************/
+#define RTC_BKP14R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP15R register ***************/
+#define RTC_BKP15R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP16R register ***************/
+#define RTC_BKP16R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP17R register ***************/
+#define RTC_BKP17R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP18R register ***************/
+#define RTC_BKP18R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP19R register ***************/
+#define RTC_BKP19R 0xFFFFFFFFU
+
+/******************************************************************************/
+/* */
+/* Serial Peripheral Interface */
+/* */
+/******************************************************************************/
+/******************* Bit definition for SPI_CR1 register ********************/
+#define SPI_CR1_CPHA 0x00000001U /*!<Clock Phase */
+#define SPI_CR1_CPOL 0x00000002U /*!<Clock Polarity */
+#define SPI_CR1_MSTR 0x00000004U /*!<Master Selection */
+
+#define SPI_CR1_BR 0x00000038U /*!<BR[2:0] bits (Baud Rate Control) */
+#define SPI_CR1_BR_0 0x00000008U /*!<Bit 0 */
+#define SPI_CR1_BR_1 0x00000010U /*!<Bit 1 */
+#define SPI_CR1_BR_2 0x00000020U /*!<Bit 2 */
+
+#define SPI_CR1_SPE 0x00000040U /*!<SPI Enable */
+#define SPI_CR1_LSBFIRST 0x00000080U /*!<Frame Format */
+#define SPI_CR1_SSI 0x00000100U /*!<Internal slave select */
+#define SPI_CR1_SSM 0x00000200U /*!<Software slave management */
+#define SPI_CR1_RXONLY 0x00000400U /*!<Receive only */
+#define SPI_CR1_DFF 0x00000800U /*!<Data Frame Format */
+#define SPI_CR1_CRCNEXT 0x00001000U /*!<Transmit CRC next */
+#define SPI_CR1_CRCEN 0x00002000U /*!<Hardware CRC calculation enable */
+#define SPI_CR1_BIDIOE 0x00004000U /*!<Output enable in bidirectional mode */
+#define SPI_CR1_BIDIMODE 0x00008000U /*!<Bidirectional data mode enable */
+
+/******************* Bit definition for SPI_CR2 register ********************/
+#define SPI_CR2_RXDMAEN 0x00000001U /*!<Rx Buffer DMA Enable */
+#define SPI_CR2_TXDMAEN 0x00000002U /*!<Tx Buffer DMA Enable */
+#define SPI_CR2_SSOE 0x00000004U /*!<SS Output Enable */
+#define SPI_CR2_FRF 0x00000010U /*!<Frame Format */
+#define SPI_CR2_ERRIE 0x00000020U /*!<Error Interrupt Enable */
+#define SPI_CR2_RXNEIE 0x00000040U /*!<RX buffer Not Empty Interrupt Enable */
+#define SPI_CR2_TXEIE 0x00000080U /*!<Tx buffer Empty Interrupt Enable */
+
+/******************** Bit definition for SPI_SR register ********************/
+#define SPI_SR_RXNE 0x00000001U /*!<Receive buffer Not Empty */
+#define SPI_SR_TXE 0x00000002U /*!<Transmit buffer Empty */
+#define SPI_SR_CHSIDE 0x00000004U /*!<Channel side */
+#define SPI_SR_UDR 0x00000008U /*!<Underrun flag */
+#define SPI_SR_CRCERR 0x00000010U /*!<CRC Error flag */
+#define SPI_SR_MODF 0x00000020U /*!<Mode fault */
+#define SPI_SR_OVR 0x00000040U /*!<Overrun flag */
+#define SPI_SR_BSY 0x00000080U /*!<Busy flag */
+#define SPI_SR_FRE 0x00000100U /*!<Frame format error flag */
+
+/******************** Bit definition for SPI_DR register ********************/
+#define SPI_DR_DR 0x0000FFFFU /*!<Data Register */
+
+/******************* Bit definition for SPI_CRCPR register ******************/
+#define SPI_CRCPR_CRCPOLY 0x0000FFFFU /*!<CRC polynomial register */
+
+/****************** Bit definition for SPI_RXCRCR register ******************/
+#define SPI_RXCRCR_RXCRC 0x0000FFFFU /*!<Rx CRC Register */
+
+/****************** Bit definition for SPI_TXCRCR register ******************/
+#define SPI_TXCRCR_TXCRC 0x0000FFFFU /*!<Tx CRC Register */
+
+/****************** Bit definition for SPI_I2SCFGR register *****************/
+#define SPI_I2SCFGR_CHLEN 0x00000001U /*!<Channel length (number of bits per audio channel) */
+
+#define SPI_I2SCFGR_DATLEN 0x00000006U /*!<DATLEN[1:0] bits (Data length to be transferred) */
+#define SPI_I2SCFGR_DATLEN_0 0x00000002U /*!<Bit 0 */
+#define SPI_I2SCFGR_DATLEN_1 0x00000004U /*!<Bit 1 */
+
+#define SPI_I2SCFGR_CKPOL 0x00000008U /*!<steady state clock polarity */
+
+#define SPI_I2SCFGR_I2SSTD 0x00000030U /*!<I2SSTD[1:0] bits (I2S standard selection) */
+#define SPI_I2SCFGR_I2SSTD_0 0x00000010U /*!<Bit 0 */
+#define SPI_I2SCFGR_I2SSTD_1 0x00000020U /*!<Bit 1 */
+
+#define SPI_I2SCFGR_PCMSYNC 0x00000080U /*!<PCM frame synchronization */
+
+#define SPI_I2SCFGR_I2SCFG 0x00000300U /*!<I2SCFG[1:0] bits (I2S configuration mode) */
+#define SPI_I2SCFGR_I2SCFG_0 0x00000100U /*!<Bit 0 */
+#define SPI_I2SCFGR_I2SCFG_1 0x00000200U /*!<Bit 1 */
+
+#define SPI_I2SCFGR_I2SE 0x00000400U /*!<I2S Enable */
+#define SPI_I2SCFGR_I2SMOD 0x00000800U /*!<I2S mode selection */
+
+/****************** Bit definition for SPI_I2SPR register *******************/
+#define SPI_I2SPR_I2SDIV 0x000000FFU /*!<I2S Linear prescaler */
+#define SPI_I2SPR_ODD 0x00000100U /*!<Odd factor for the prescaler */
+#define SPI_I2SPR_MCKOE 0x00000200U /*!<Master Clock Output Enable */
+
+/******************************************************************************/
+/* */
+/* SYSCFG */
+/* */
+/******************************************************************************/
+/****************** Bit definition for SYSCFG_MEMRMP register ***************/
+#define SYSCFG_MEMRMP_MEM_MODE 0x00000007U /*!< SYSCFG_Memory Remap Config */
+#define SYSCFG_MEMRMP_MEM_MODE_0 0x00000001U
+#define SYSCFG_MEMRMP_MEM_MODE_1 0x00000002U
+#define SYSCFG_MEMRMP_MEM_MODE_2 0x00000004U
+
+/****************** Bit definition for SYSCFG_PMC register ******************/
+#define SYSCFG_PMC_ADC1DC2 0x00010000U /*!< Refer to AN4073 on how to use this bit */
+
+/***************** Bit definition for SYSCFG_EXTICR1 register ***************/
+#define SYSCFG_EXTICR1_EXTI0 0x000FU /*!<EXTI 0 configuration */
+#define SYSCFG_EXTICR1_EXTI1 0x00F0U /*!<EXTI 1 configuration */
+#define SYSCFG_EXTICR1_EXTI2 0x0F00U /*!<EXTI 2 configuration */
+#define SYSCFG_EXTICR1_EXTI3 0xF000U /*!<EXTI 3 configuration */
+/**
+ * @brief EXTI0 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI0_PA 0x0000U /*!<PA[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PB 0x0001U /*!<PB[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PC 0x0002U /*!<PC[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PH 0x0007U /*!<PH[0] pin */
+
+/**
+ * @brief EXTI1 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI1_PA 0x0000U /*!<PA[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PB 0x0010U /*!<PB[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PC 0x0020U /*!<PC[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PH 0x0070U /*!<PH[1] pin */
+
+/**
+ * @brief EXTI2 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI2_PA 0x0000U /*!<PA[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PB 0x0100U /*!<PB[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PC 0x0200U /*!<PC[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PH 0x0700U /*!<PH[2] pin */
+
+/**
+ * @brief EXTI3 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI3_PA 0x0000U /*!<PA[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PB 0x1000U /*!<PB[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PC 0x2000U /*!<PC[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PH 0x7000U /*!<PH[3] pin */
+
+/***************** Bit definition for SYSCFG_EXTICR2 register ***************/
+#define SYSCFG_EXTICR2_EXTI4 0x000FU /*!<EXTI 4 configuration */
+#define SYSCFG_EXTICR2_EXTI5 0x00F0U /*!<EXTI 5 configuration */
+#define SYSCFG_EXTICR2_EXTI6 0x0F00U /*!<EXTI 6 configuration */
+#define SYSCFG_EXTICR2_EXTI7 0xF000U /*!<EXTI 7 configuration */
+/**
+ * @brief EXTI4 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI4_PA 0x0000U /*!<PA[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PB 0x0001U /*!<PB[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PC 0x0002U /*!<PC[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PH 0x0007U /*!<PH[4] pin */
+
+/**
+ * @brief EXTI5 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI5_PA 0x0000U /*!<PA[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PB 0x0010U /*!<PB[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PC 0x0020U /*!<PC[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PH 0x0070U /*!<PH[5] pin */
+
+/**
+ * @brief EXTI6 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI6_PA 0x0000U /*!<PA[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PB 0x0100U /*!<PB[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PC 0x0200U /*!<PC[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PH 0x0700U /*!<PH[6] pin */
+
+/**
+ * @brief EXTI7 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI7_PA 0x0000U /*!<PA[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PB 0x1000U /*!<PB[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PC 0x2000U /*!<PC[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PH 0x7000U /*!<PH[7] pin */
+
+
+/***************** Bit definition for SYSCFG_EXTICR3 register ***************/
+#define SYSCFG_EXTICR3_EXTI8 0x000FU /*!<EXTI 8 configuration */
+#define SYSCFG_EXTICR3_EXTI9 0x00F0U /*!<EXTI 9 configuration */
+#define SYSCFG_EXTICR3_EXTI10 0x0F00U /*!<EXTI 10 configuration */
+#define SYSCFG_EXTICR3_EXTI11 0xF000U /*!<EXTI 11 configuration */
+
+/**
+ * @brief EXTI8 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI8_PA 0x0000U /*!<PA[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PB 0x0001U /*!<PB[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PC 0x0002U /*!<PC[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PH 0x0007U /*!<PH[8] pin */
+
+/**
+ * @brief EXTI9 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI9_PA 0x0000U /*!<PA[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PB 0x0010U /*!<PB[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PC 0x0020U /*!<PC[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PH 0x0070U /*!<PH[9] pin */
+
+/**
+ * @brief EXTI10 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI10_PA 0x0000U /*!<PA[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PB 0x0100U /*!<PB[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PC 0x0200U /*!<PC[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PH 0x0700U /*!<PH[10] pin */
+
+/**
+ * @brief EXTI11 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI11_PA 0x0000U /*!<PA[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PB 0x1000U /*!<PB[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PC 0x2000U /*!<PC[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PH 0x7000U /*!<PH[11] pin */
+
+/***************** Bit definition for SYSCFG_EXTICR4 register ***************/
+#define SYSCFG_EXTICR4_EXTI12 0x000FU /*!<EXTI 12 configuration */
+#define SYSCFG_EXTICR4_EXTI13 0x00F0U /*!<EXTI 13 configuration */
+#define SYSCFG_EXTICR4_EXTI14 0x0F00U /*!<EXTI 14 configuration */
+#define SYSCFG_EXTICR4_EXTI15 0xF000U /*!<EXTI 15 configuration */
+/**
+ * @brief EXTI12 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI12_PA 0x0000U /*!<PA[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PB 0x0001U /*!<PB[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PC 0x0002U /*!<PC[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PH 0x0007U /*!<PH[12] pin */
+
+/**
+ * @brief EXTI13 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI13_PA 0x0000U /*!<PA[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PB 0x0010U /*!<PB[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PC 0x0020U /*!<PC[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PH 0x0070U /*!<PH[13] pin */
+
+/**
+ * @brief EXTI14 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI14_PA 0x0000U /*!<PA[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PB 0x0100U /*!<PB[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PC 0x0200U /*!<PC[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PH 0x0700U /*!<PH[14] pin */
+
+/**
+ * @brief EXTI15 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI15_PA 0x0000U /*!<PA[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PB 0x1000U /*!<PB[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PC 0x2000U /*!<PC[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PH 0x7000U /*!<PH[15] pin */
+
+/****************** Bit definition for SYSCFG_CMPCR register ****************/
+#define SYSCFG_CMPCR_CMP_PD 0x00000001U /*!<Compensation cell ready flag */
+#define SYSCFG_CMPCR_READY 0x00000100U /*!<Compensation cell power-down */
+
+/****************** Bit definition for SYSCFG_CFGR register *****************/
+#define SYSCFG_CFGR_FMPI2C1_SCL 0x00000001U /*!<FM+ drive capability for FMPI2C1_SCL pin */
+#define SYSCFG_CFGR_FMPI2C1_SDA 0x00000002U /*!<FM+ drive capability for FMPI2C1_SDA pin */
+
+/****************** Bit definition for SYSCFG_CFGR2 register *****************/
+#define SYSCFG_CFGR2_LOCKUP_LOCK 0x00000001U /*!<Core Lockup lock */
+#define SYSCFG_CFGR2_PVD_LOCK 0x00000004U /*!<PVD Lock */
+
+/******************************************************************************/
+/* */
+/* TIM */
+/* */
+/******************************************************************************/
+/******************* Bit definition for TIM_CR1 register ********************/
+#define TIM_CR1_CEN 0x0001U /*!<Counter enable */
+#define TIM_CR1_UDIS 0x0002U /*!<Update disable */
+#define TIM_CR1_URS 0x0004U /*!<Update request source */
+#define TIM_CR1_OPM 0x0008U /*!<One pulse mode */
+#define TIM_CR1_DIR 0x0010U /*!<Direction */
+
+#define TIM_CR1_CMS 0x0060U /*!<CMS[1:0] bits (Center-aligned mode selection) */
+#define TIM_CR1_CMS_0 0x0020U /*!<Bit 0 */
+#define TIM_CR1_CMS_1 0x0040U /*!<Bit 1 */
+
+#define TIM_CR1_ARPE 0x0080U /*!<Auto-reload preload enable */
+
+#define TIM_CR1_CKD 0x0300U /*!<CKD[1:0] bits (clock division) */
+#define TIM_CR1_CKD_0 0x0100U /*!<Bit 0 */
+#define TIM_CR1_CKD_1 0x0200U /*!<Bit 1 */
+
+/******************* Bit definition for TIM_CR2 register ********************/
+#define TIM_CR2_CCPC 0x0001U /*!<Capture/Compare Preloaded Control */
+#define TIM_CR2_CCUS 0x0004U /*!<Capture/Compare Control Update Selection */
+#define TIM_CR2_CCDS 0x0008U /*!<Capture/Compare DMA Selection */
+
+#define TIM_CR2_MMS 0x0070U /*!<MMS[2:0] bits (Master Mode Selection) */
+#define TIM_CR2_MMS_0 0x0010U /*!<Bit 0 */
+#define TIM_CR2_MMS_1 0x0020U /*!<Bit 1 */
+#define TIM_CR2_MMS_2 0x0040U /*!<Bit 2 */
+
+#define TIM_CR2_TI1S 0x0080U /*!<TI1 Selection */
+#define TIM_CR2_OIS1 0x0100U /*!<Output Idle state 1 (OC1 output) */
+#define TIM_CR2_OIS1N 0x0200U /*!<Output Idle state 1 (OC1N output) */
+#define TIM_CR2_OIS2 0x0400U /*!<Output Idle state 2 (OC2 output) */
+#define TIM_CR2_OIS2N 0x0800U /*!<Output Idle state 2 (OC2N output) */
+#define TIM_CR2_OIS3 0x1000U /*!<Output Idle state 3 (OC3 output) */
+#define TIM_CR2_OIS3N 0x2000U /*!<Output Idle state 3 (OC3N output) */
+#define TIM_CR2_OIS4 0x4000U /*!<Output Idle state 4 (OC4 output) */
+
+/******************* Bit definition for TIM_SMCR register *******************/
+#define TIM_SMCR_SMS 0x0007U /*!<SMS[2:0] bits (Slave mode selection) */
+#define TIM_SMCR_SMS_0 0x0001U /*!<Bit 0 */
+#define TIM_SMCR_SMS_1 0x0002U /*!<Bit 1 */
+#define TIM_SMCR_SMS_2 0x0004U /*!<Bit 2 */
+
+#define TIM_SMCR_TS 0x0070U /*!<TS[2:0] bits (Trigger selection) */
+#define TIM_SMCR_TS_0 0x0010U /*!<Bit 0 */
+#define TIM_SMCR_TS_1 0x0020U /*!<Bit 1 */
+#define TIM_SMCR_TS_2 0x0040U /*!<Bit 2 */
+
+#define TIM_SMCR_MSM 0x0080U /*!<Master/slave mode */
+
+#define TIM_SMCR_ETF 0x0F00U /*!<ETF[3:0] bits (External trigger filter) */
+#define TIM_SMCR_ETF_0 0x0100U /*!<Bit 0 */
+#define TIM_SMCR_ETF_1 0x0200U /*!<Bit 1 */
+#define TIM_SMCR_ETF_2 0x0400U /*!<Bit 2 */
+#define TIM_SMCR_ETF_3 0x0800U /*!<Bit 3 */
+
+#define TIM_SMCR_ETPS 0x3000U /*!<ETPS[1:0] bits (External trigger prescaler) */
+#define TIM_SMCR_ETPS_0 0x1000U /*!<Bit 0 */
+#define TIM_SMCR_ETPS_1 0x2000U /*!<Bit 1 */
+
+#define TIM_SMCR_ECE 0x4000U /*!<External clock enable */
+#define TIM_SMCR_ETP 0x8000U /*!<External trigger polarity */
+
+/******************* Bit definition for TIM_DIER register *******************/
+#define TIM_DIER_UIE 0x0001U /*!<Update interrupt enable */
+#define TIM_DIER_CC1IE 0x0002U /*!<Capture/Compare 1 interrupt enable */
+#define TIM_DIER_CC2IE 0x0004U /*!<Capture/Compare 2 interrupt enable */
+#define TIM_DIER_CC3IE 0x0008U /*!<Capture/Compare 3 interrupt enable */
+#define TIM_DIER_CC4IE 0x0010U /*!<Capture/Compare 4 interrupt enable */
+#define TIM_DIER_COMIE 0x0020U /*!<COM interrupt enable */
+#define TIM_DIER_TIE 0x0040U /*!<Trigger interrupt enable */
+#define TIM_DIER_BIE 0x0080U /*!<Break interrupt enable */
+#define TIM_DIER_UDE 0x0100U /*!<Update DMA request enable */
+#define TIM_DIER_CC1DE 0x0200U /*!<Capture/Compare 1 DMA request enable */
+#define TIM_DIER_CC2DE 0x0400U /*!<Capture/Compare 2 DMA request enable */
+#define TIM_DIER_CC3DE 0x0800U /*!<Capture/Compare 3 DMA request enable */
+#define TIM_DIER_CC4DE 0x1000U /*!<Capture/Compare 4 DMA request enable */
+#define TIM_DIER_COMDE 0x2000U /*!<COM DMA request enable */
+#define TIM_DIER_TDE 0x4000U /*!<Trigger DMA request enable */
+
+/******************** Bit definition for TIM_SR register ********************/
+#define TIM_SR_UIF 0x0001U /*!<Update interrupt Flag */
+#define TIM_SR_CC1IF 0x0002U /*!<Capture/Compare 1 interrupt Flag */
+#define TIM_SR_CC2IF 0x0004U /*!<Capture/Compare 2 interrupt Flag */
+#define TIM_SR_CC3IF 0x0008U /*!<Capture/Compare 3 interrupt Flag */
+#define TIM_SR_CC4IF 0x0010U /*!<Capture/Compare 4 interrupt Flag */
+#define TIM_SR_COMIF 0x0020U /*!<COM interrupt Flag */
+#define TIM_SR_TIF 0x0040U /*!<Trigger interrupt Flag */
+#define TIM_SR_BIF 0x0080U /*!<Break interrupt Flag */
+#define TIM_SR_CC1OF 0x0200U /*!<Capture/Compare 1 Overcapture Flag */
+#define TIM_SR_CC2OF 0x0400U /*!<Capture/Compare 2 Overcapture Flag */
+#define TIM_SR_CC3OF 0x0800U /*!<Capture/Compare 3 Overcapture Flag */
+#define TIM_SR_CC4OF 0x1000U /*!<Capture/Compare 4 Overcapture Flag */
+
+/******************* Bit definition for TIM_EGR register ********************/
+#define TIM_EGR_UG 0x01U /*!<Update Generation */
+#define TIM_EGR_CC1G 0x02U /*!<Capture/Compare 1 Generation */
+#define TIM_EGR_CC2G 0x04U /*!<Capture/Compare 2 Generation */
+#define TIM_EGR_CC3G 0x08U /*!<Capture/Compare 3 Generation */
+#define TIM_EGR_CC4G 0x10U /*!<Capture/Compare 4 Generation */
+#define TIM_EGR_COMG 0x20U /*!<Capture/Compare Control Update Generation */
+#define TIM_EGR_TG 0x40U /*!<Trigger Generation */
+#define TIM_EGR_BG 0x80U /*!<Break Generation */
+
+/****************** Bit definition for TIM_CCMR1 register *******************/
+#define TIM_CCMR1_CC1S 0x0003U /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
+#define TIM_CCMR1_CC1S_0 0x0001U /*!<Bit 0 */
+#define TIM_CCMR1_CC1S_1 0x0002U /*!<Bit 1 */
+
+#define TIM_CCMR1_OC1FE 0x0004U /*!<Output Compare 1 Fast enable */
+#define TIM_CCMR1_OC1PE 0x0008U /*!<Output Compare 1 Preload enable */
+
+#define TIM_CCMR1_OC1M 0x0070U /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
+#define TIM_CCMR1_OC1M_0 0x0010U /*!<Bit 0 */
+#define TIM_CCMR1_OC1M_1 0x0020U /*!<Bit 1 */
+#define TIM_CCMR1_OC1M_2 0x0040U /*!<Bit 2 */
+
+#define TIM_CCMR1_OC1CE 0x0080U /*!<Output Compare 1Clear Enable */
+
+#define TIM_CCMR1_CC2S 0x0300U /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
+#define TIM_CCMR1_CC2S_0 0x0100U /*!<Bit 0 */
+#define TIM_CCMR1_CC2S_1 0x0200U /*!<Bit 1 */
+
+#define TIM_CCMR1_OC2FE 0x0400U /*!<Output Compare 2 Fast enable */
+#define TIM_CCMR1_OC2PE 0x0800U /*!<Output Compare 2 Preload enable */
+
+#define TIM_CCMR1_OC2M 0x7000U /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
+#define TIM_CCMR1_OC2M_0 0x1000U /*!<Bit 0 */
+#define TIM_CCMR1_OC2M_1 0x2000U /*!<Bit 1 */
+#define TIM_CCMR1_OC2M_2 0x4000U /*!<Bit 2 */
+
+#define TIM_CCMR1_OC2CE 0x8000U /*!<Output Compare 2 Clear Enable */
+
+/*----------------------------------------------------------------------------*/
+
+#define TIM_CCMR1_IC1PSC 0x000CU /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
+#define TIM_CCMR1_IC1PSC_0 0x0004U /*!<Bit 0 */
+#define TIM_CCMR1_IC1PSC_1 0x0008U /*!<Bit 1 */
+
+#define TIM_CCMR1_IC1F 0x00F0U /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
+#define TIM_CCMR1_IC1F_0 0x0010U /*!<Bit 0 */
+#define TIM_CCMR1_IC1F_1 0x0020U /*!<Bit 1 */
+#define TIM_CCMR1_IC1F_2 0x0040U /*!<Bit 2 */
+#define TIM_CCMR1_IC1F_3 0x0080U /*!<Bit 3 */
+
+#define TIM_CCMR1_IC2PSC 0x0C00U /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
+#define TIM_CCMR1_IC2PSC_0 0x0400U /*!<Bit 0 */
+#define TIM_CCMR1_IC2PSC_1 0x0800U /*!<Bit 1 */
+
+#define TIM_CCMR1_IC2F 0xF000U /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
+#define TIM_CCMR1_IC2F_0 0x1000U /*!<Bit 0 */
+#define TIM_CCMR1_IC2F_1 0x2000U /*!<Bit 1 */
+#define TIM_CCMR1_IC2F_2 0x4000U /*!<Bit 2 */
+#define TIM_CCMR1_IC2F_3 0x8000U /*!<Bit 3 */
+
+/****************** Bit definition for TIM_CCMR2 register *******************/
+#define TIM_CCMR2_CC3S 0x0003U /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
+#define TIM_CCMR2_CC3S_0 0x0001U /*!<Bit 0 */
+#define TIM_CCMR2_CC3S_1 0x0002U /*!<Bit 1 */
+
+#define TIM_CCMR2_OC3FE 0x0004U /*!<Output Compare 3 Fast enable */
+#define TIM_CCMR2_OC3PE 0x0008U /*!<Output Compare 3 Preload enable */
+
+#define TIM_CCMR2_OC3M 0x0070U /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
+#define TIM_CCMR2_OC3M_0 0x0010U /*!<Bit 0 */
+#define TIM_CCMR2_OC3M_1 0x0020U /*!<Bit 1 */
+#define TIM_CCMR2_OC3M_2 0x0040U /*!<Bit 2 */
+
+#define TIM_CCMR2_OC3CE 0x0080U /*!<Output Compare 3 Clear Enable */
+
+#define TIM_CCMR2_CC4S 0x0300U /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
+#define TIM_CCMR2_CC4S_0 0x0100U /*!<Bit 0 */
+#define TIM_CCMR2_CC4S_1 0x0200U /*!<Bit 1 */
+
+#define TIM_CCMR2_OC4FE 0x0400U /*!<Output Compare 4 Fast enable */
+#define TIM_CCMR2_OC4PE 0x0800U /*!<Output Compare 4 Preload enable */
+
+#define TIM_CCMR2_OC4M 0x7000U /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
+#define TIM_CCMR2_OC4M_0 0x1000U /*!<Bit 0 */
+#define TIM_CCMR2_OC4M_1 0x2000U /*!<Bit 1 */
+#define TIM_CCMR2_OC4M_2 0x4000U /*!<Bit 2 */
+
+#define TIM_CCMR2_OC4CE 0x8000U /*!<Output Compare 4 Clear Enable */
+
+/*----------------------------------------------------------------------------*/
+
+#define TIM_CCMR2_IC3PSC 0x000CU /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
+#define TIM_CCMR2_IC3PSC_0 0x0004U /*!<Bit 0 */
+#define TIM_CCMR2_IC3PSC_1 0x0008U /*!<Bit 1 */
+
+#define TIM_CCMR2_IC3F 0x00F0U /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
+#define TIM_CCMR2_IC3F_0 0x0010U /*!<Bit 0 */
+#define TIM_CCMR2_IC3F_1 0x0020U /*!<Bit 1 */
+#define TIM_CCMR2_IC3F_2 0x0040U /*!<Bit 2 */
+#define TIM_CCMR2_IC3F_3 0x0080U /*!<Bit 3 */
+
+#define TIM_CCMR2_IC4PSC 0x0C00U /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
+#define TIM_CCMR2_IC4PSC_0 0x0400U /*!<Bit 0 */
+#define TIM_CCMR2_IC4PSC_1 0x0800U /*!<Bit 1 */
+
+#define TIM_CCMR2_IC4F 0xF000U /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
+#define TIM_CCMR2_IC4F_0 0x1000U /*!<Bit 0 */
+#define TIM_CCMR2_IC4F_1 0x2000U /*!<Bit 1 */
+#define TIM_CCMR2_IC4F_2 0x4000U /*!<Bit 2 */
+#define TIM_CCMR2_IC4F_3 0x8000U /*!<Bit 3 */
+
+/******************* Bit definition for TIM_CCER register *******************/
+#define TIM_CCER_CC1E 0x0001U /*!<Capture/Compare 1 output enable */
+#define TIM_CCER_CC1P 0x0002U /*!<Capture/Compare 1 output Polarity */
+#define TIM_CCER_CC1NE 0x0004U /*!<Capture/Compare 1 Complementary output enable */
+#define TIM_CCER_CC1NP 0x0008U /*!<Capture/Compare 1 Complementary output Polarity */
+#define TIM_CCER_CC2E 0x0010U /*!<Capture/Compare 2 output enable */
+#define TIM_CCER_CC2P 0x0020U /*!<Capture/Compare 2 output Polarity */
+#define TIM_CCER_CC2NE 0x0040U /*!<Capture/Compare 2 Complementary output enable */
+#define TIM_CCER_CC2NP 0x0080U /*!<Capture/Compare 2 Complementary output Polarity */
+#define TIM_CCER_CC3E 0x0100U /*!<Capture/Compare 3 output enable */
+#define TIM_CCER_CC3P 0x0200U /*!<Capture/Compare 3 output Polarity */
+#define TIM_CCER_CC3NE 0x0400U /*!<Capture/Compare 3 Complementary output enable */
+#define TIM_CCER_CC3NP 0x0800U /*!<Capture/Compare 3 Complementary output Polarity */
+#define TIM_CCER_CC4E 0x1000U /*!<Capture/Compare 4 output enable */
+#define TIM_CCER_CC4P 0x2000U /*!<Capture/Compare 4 output Polarity */
+#define TIM_CCER_CC4NP 0x8000U /*!<Capture/Compare 4 Complementary output Polarity */
+
+/******************* Bit definition for TIM_CNT register ********************/
+#define TIM_CNT_CNT 0xFFFFU /*!<Counter Value */
+
+/******************* Bit definition for TIM_PSC register ********************/
+#define TIM_PSC_PSC 0xFFFFU /*!<Prescaler Value */
+
+/******************* Bit definition for TIM_ARR register ********************/
+#define TIM_ARR_ARR 0xFFFFU /*!<actual auto-reload Value */
+
+/******************* Bit definition for TIM_RCR register ********************/
+#define TIM_RCR_REP 0xFFU /*!<Repetition Counter Value */
+
+/******************* Bit definition for TIM_CCR1 register *******************/
+#define TIM_CCR1_CCR1 0xFFFFU /*!<Capture/Compare 1 Value */
+
+/******************* Bit definition for TIM_CCR2 register *******************/
+#define TIM_CCR2_CCR2 0xFFFFU /*!<Capture/Compare 2 Value */
+
+/******************* Bit definition for TIM_CCR3 register *******************/
+#define TIM_CCR3_CCR3 0xFFFFU /*!<Capture/Compare 3 Value */
+
+/******************* Bit definition for TIM_CCR4 register *******************/
+#define TIM_CCR4_CCR4 0xFFFFU /*!<Capture/Compare 4 Value */
+
+/******************* Bit definition for TIM_BDTR register *******************/
+#define TIM_BDTR_DTG 0x00FFU /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
+#define TIM_BDTR_DTG_0 0x0001U /*!<Bit 0 */
+#define TIM_BDTR_DTG_1 0x0002U /*!<Bit 1 */
+#define TIM_BDTR_DTG_2 0x0004U /*!<Bit 2 */
+#define TIM_BDTR_DTG_3 0x0008U /*!<Bit 3 */
+#define TIM_BDTR_DTG_4 0x0010U /*!<Bit 4 */
+#define TIM_BDTR_DTG_5 0x0020U /*!<Bit 5 */
+#define TIM_BDTR_DTG_6 0x0040U /*!<Bit 6 */
+#define TIM_BDTR_DTG_7 0x0080U /*!<Bit 7 */
+
+#define TIM_BDTR_LOCK 0x0300U /*!<LOCK[1:0] bits (Lock Configuration) */
+#define TIM_BDTR_LOCK_0 0x0100U /*!<Bit 0 */
+#define TIM_BDTR_LOCK_1 0x0200U /*!<Bit 1 */
+
+#define TIM_BDTR_OSSI 0x0400U /*!<Off-State Selection for Idle mode */
+#define TIM_BDTR_OSSR 0x0800U /*!<Off-State Selection for Run mode */
+#define TIM_BDTR_BKE 0x1000U /*!<Break enable */
+#define TIM_BDTR_BKP 0x2000U /*!<Break Polarity */
+#define TIM_BDTR_AOE 0x4000U /*!<Automatic Output enable */
+#define TIM_BDTR_MOE 0x8000U /*!<Main Output enable */
+
+/******************* Bit definition for TIM_DCR register ********************/
+#define TIM_DCR_DBA 0x001FU /*!<DBA[4:0] bits (DMA Base Address) */
+#define TIM_DCR_DBA_0 0x0001U /*!<Bit 0 */
+#define TIM_DCR_DBA_1 0x0002U /*!<Bit 1 */
+#define TIM_DCR_DBA_2 0x0004U /*!<Bit 2 */
+#define TIM_DCR_DBA_3 0x0008U /*!<Bit 3 */
+#define TIM_DCR_DBA_4 0x0010U /*!<Bit 4 */
+
+#define TIM_DCR_DBL 0x1F00U /*!<DBL[4:0] bits (DMA Burst Length) */
+#define TIM_DCR_DBL_0 0x0100U /*!<Bit 0 */
+#define TIM_DCR_DBL_1 0x0200U /*!<Bit 1 */
+#define TIM_DCR_DBL_2 0x0400U /*!<Bit 2 */
+#define TIM_DCR_DBL_3 0x0800U /*!<Bit 3 */
+#define TIM_DCR_DBL_4 0x1000U /*!<Bit 4 */
+
+/******************* Bit definition for TIM_DMAR register *******************/
+#define TIM_DMAR_DMAB 0xFFFFU /*!<DMA register for burst accesses */
+
+/******************* Bit definition for TIM_OR register *********************/
+#define TIM_OR_TI4_RMP 0x00C0U /*!<TI4_RMP[1:0] bits (TIM5 Input 4 remap) */
+#define TIM_OR_TI4_RMP_0 0x0040U /*!<Bit 0 */
+#define TIM_OR_TI4_RMP_1 0x0080U /*!<Bit 1 */
+
+/******************************************************************************/
+/* */
+/* Low Power Timer (LPTIM) */
+/* */
+/******************************************************************************/
+/****************** Bit definition for LPTIM_ISR register *******************/
+#define LPTIM_ISR_CMPM 0x00000001U /*!< Compare match */
+#define LPTIM_ISR_ARRM 0x00000002U /*!< Autoreload match */
+#define LPTIM_ISR_EXTTRIG 0x00000004U /*!< External trigger edge event */
+#define LPTIM_ISR_CMPOK 0x00000008U /*!< Compare register update OK */
+#define LPTIM_ISR_ARROK 0x00000010U /*!< Autoreload register update OK */
+#define LPTIM_ISR_UP 0x00000020U /*!< Counter direction change down to up */
+#define LPTIM_ISR_DOWN 0x00000040U /*!< Counter direction change up to down */
+
+/****************** Bit definition for LPTIM_ICR register *******************/
+#define LPTIM_ICR_CMPMCF 0x00000001U /*!< Compare match Clear Flag */
+#define LPTIM_ICR_ARRMCF 0x00000002U /*!< Autoreload match Clear Flag */
+#define LPTIM_ICR_EXTTRIGCF 0x00000004U /*!< External trigger edge event Clear Flag */
+#define LPTIM_ICR_CMPOKCF 0x00000008U /*!< Compare register update OK Clear Flag */
+#define LPTIM_ICR_ARROKCF 0x00000010U /*!< Autoreload register update OK Clear Flag */
+#define LPTIM_ICR_UPCF 0x00000020U /*!< Counter direction change down to up Clear Flag */
+#define LPTIM_ICR_DOWNCF 0x00000040U /*!< Counter direction change up to down Clear Flag */
+
+/****************** Bit definition for LPTIM_IER register ********************/
+#define LPTIM_IER_CMPMIE 0x00000001U /*!< Compare match Interrupt Enable */
+#define LPTIM_IER_ARRMIE 0x00000002U /*!< Autoreload match Interrupt Enable */
+#define LPTIM_IER_EXTTRIGIE 0x00000004U /*!< External trigger edge event Interrupt Enable */
+#define LPTIM_IER_CMPOKIE 0x00000008U /*!< Compare register update OK Interrupt Enable */
+#define LPTIM_IER_ARROKIE 0x00000010U /*!< Autoreload register update OK Interrupt Enable */
+#define LPTIM_IER_UPIE 0x00000020U /*!< Counter direction change down to up Interrupt Enable */
+#define LPTIM_IER_DOWNIE 0x00000040U /*!< Counter direction change up to down Interrupt Enable */
+
+/****************** Bit definition for LPTIM_CFGR register *******************/
+#define LPTIM_CFGR_CKSEL 0x00000001U /*!< Clock selector */
+
+#define LPTIM_CFGR_CKPOL 0x00000006U /*!< CKPOL[1:0] bits (Clock polarity) */
+#define LPTIM_CFGR_CKPOL_0 0x00000002U /*!< Bit 0 */
+#define LPTIM_CFGR_CKPOL_1 0x00000004U /*!< Bit 1 */
+
+#define LPTIM_CFGR_CKFLT 0x00000018U /*!< CKFLT[1:0] bits (Configurable digital filter for external clock) */
+#define LPTIM_CFGR_CKFLT_0 0x00000008U /*!< Bit 0 */
+#define LPTIM_CFGR_CKFLT_1 0x00000010U /*!< Bit 1 */
+
+#define LPTIM_CFGR_TRGFLT 0x000000C0U /*!< TRGFLT[1:0] bits (Configurable digital filter for trigger) */
+#define LPTIM_CFGR_TRGFLT_0 0x00000040U /*!< Bit 0 */
+#define LPTIM_CFGR_TRGFLT_1 0x00000080U /*!< Bit 1 */
+
+#define LPTIM_CFGR_PRESC 0x00000E00U /*!< PRESC[2:0] bits (Clock prescaler) */
+#define LPTIM_CFGR_PRESC_0 0x00000200U /*!< Bit 0 */
+#define LPTIM_CFGR_PRESC_1 0x00000400U /*!< Bit 1 */
+#define LPTIM_CFGR_PRESC_2 0x00000800U /*!< Bit 2 */
+
+#define LPTIM_CFGR_TRIGSEL 0x0000E000U /*!< TRIGSEL[2:0]] bits (Trigger selector) */
+#define LPTIM_CFGR_TRIGSEL_0 0x00002000U /*!< Bit 0 */
+#define LPTIM_CFGR_TRIGSEL_1 0x00004000U /*!< Bit 1 */
+#define LPTIM_CFGR_TRIGSEL_2 0x00008000U /*!< Bit 2 */
+
+#define LPTIM_CFGR_TRIGEN 0x00060000U /*!< TRIGEN[1:0] bits (Trigger enable and polarity) */
+#define LPTIM_CFGR_TRIGEN_0 0x00020000U /*!< Bit 0 */
+#define LPTIM_CFGR_TRIGEN_1 0x00040000U /*!< Bit 1 */
+
+#define LPTIM_CFGR_TIMOUT 0x00080000U /*!< Timout enable */
+#define LPTIM_CFGR_WAVE 0x00100000U /*!< Waveform shape */
+#define LPTIM_CFGR_WAVPOL 0x00200000U /*!< Waveform shape polarity */
+#define LPTIM_CFGR_PRELOAD 0x00400000U /*!< Reg update mode */
+#define LPTIM_CFGR_COUNTMODE 0x00800000U /*!< Counter mode enable */
+#define LPTIM_CFGR_ENC 0x01000000U /*!< Encoder mode enable */
+
+/****************** Bit definition for LPTIM_CR register ********************/
+#define LPTIM_CR_ENABLE 0x00000001U /*!< LPTIMer enable */
+#define LPTIM_CR_SNGSTRT 0x00000002U /*!< Timer start in single mode */
+#define LPTIM_CR_CNTSTRT 0x00000004U /*!< Timer start in continuous mode */
+
+/****************** Bit definition for LPTIM_CMP register *******************/
+#define LPTIM_CMP_CMP 0x0000FFFFU /*!< Compare register */
+
+/****************** Bit definition for LPTIM_ARR register *******************/
+#define LPTIM_ARR_ARR 0x0000FFFFU /*!< Auto reload register */
+
+/****************** Bit definition for LPTIM_CNT register *******************/
+#define LPTIM_CNT_CNT 0x0000FFFFU /*!< Counter register */
+
+/****************** Bit definition for LPTIM_OR register *******************/
+#define LPTIM_OR_OR 0x00000003U /*!< LPTIMER[1:0] bits (Remap selection) */
+#define LPTIM_OR_OR_0 0x00000001U /*!< Bit 0 */
+#define LPTIM_OR_OR_1 0x00000002U /*!< Bit 1 */
+
+/******************************************************************************/
+/* */
+/* Universal Synchronous Asynchronous Receiver Transmitter */
+/* */
+/******************************************************************************/
+/******************* Bit definition for USART_SR register *******************/
+#define USART_SR_PE 0x0001U /*!<Parity Error */
+#define USART_SR_FE 0x0002U /*!<Framing Error */
+#define USART_SR_NE 0x0004U /*!<Noise Error Flag */
+#define USART_SR_ORE 0x0008U /*!<OverRun Error */
+#define USART_SR_IDLE 0x0010U /*!<IDLE line detected */
+#define USART_SR_RXNE 0x0020U /*!<Read Data Register Not Empty */
+#define USART_SR_TC 0x0040U /*!<Transmission Complete */
+#define USART_SR_TXE 0x0080U /*!<Transmit Data Register Empty */
+#define USART_SR_LBD 0x0100U /*!<LIN Break Detection Flag */
+#define USART_SR_CTS 0x0200U /*!<CTS Flag */
+
+/******************* Bit definition for USART_DR register *******************/
+#define USART_DR_DR 0x01FFU /*!<Data value */
+
+/****************** Bit definition for USART_BRR register *******************/
+#define USART_BRR_DIV_Fraction 0x000FU /*!<Fraction of USARTDIV */
+#define USART_BRR_DIV_Mantissa 0xFFF0U /*!<Mantissa of USARTDIV */
+
+/****************** Bit definition for USART_CR1 register *******************/
+#define USART_CR1_SBK 0x0001U /*!<Send Break */
+#define USART_CR1_RWU 0x0002U /*!<Receiver wakeup */
+#define USART_CR1_RE 0x0004U /*!<Receiver Enable */
+#define USART_CR1_TE 0x0008U /*!<Transmitter Enable */
+#define USART_CR1_IDLEIE 0x0010U /*!<IDLE Interrupt Enable */
+#define USART_CR1_RXNEIE 0x0020U /*!<RXNE Interrupt Enable */
+#define USART_CR1_TCIE 0x0040U /*!<Transmission Complete Interrupt Enable */
+#define USART_CR1_TXEIE 0x0080U /*!<PE Interrupt Enable */
+#define USART_CR1_PEIE 0x0100U /*!<PE Interrupt Enable */
+#define USART_CR1_PS 0x0200U /*!<Parity Selection */
+#define USART_CR1_PCE 0x0400U /*!<Parity Control Enable */
+#define USART_CR1_WAKE 0x0800U /*!<Wakeup method */
+#define USART_CR1_M 0x1000U /*!<Word length */
+#define USART_CR1_UE 0x2000U /*!<USART Enable */
+#define USART_CR1_OVER8 0x8000U /*!<USART Oversampling by 8 enable */
+
+/****************** Bit definition for USART_CR2 register *******************/
+#define USART_CR2_ADD 0x000FU /*!<Address of the USART node */
+#define USART_CR2_LBDL 0x0020U /*!<LIN Break Detection Length */
+#define USART_CR2_LBDIE 0x0040U /*!<LIN Break Detection Interrupt Enable */
+#define USART_CR2_LBCL 0x0100U /*!<Last Bit Clock pulse */
+#define USART_CR2_CPHA 0x0200U /*!<Clock Phase */
+#define USART_CR2_CPOL 0x0400U /*!<Clock Polarity */
+#define USART_CR2_CLKEN 0x0800U /*!<Clock Enable */
+
+#define USART_CR2_STOP 0x3000U /*!<STOP[1:0] bits (STOP bits) */
+#define USART_CR2_STOP_0 0x1000U /*!<Bit 0 */
+#define USART_CR2_STOP_1 0x2000U /*!<Bit 1 */
+
+#define USART_CR2_LINEN 0x4000U /*!<LIN mode enable */
+
+/****************** Bit definition for USART_CR3 register *******************/
+#define USART_CR3_EIE 0x0001U /*!<Error Interrupt Enable */
+#define USART_CR3_IREN 0x0002U /*!<IrDA mode Enable */
+#define USART_CR3_IRLP 0x0004U /*!<IrDA Low-Power */
+#define USART_CR3_HDSEL 0x0008U /*!<Half-Duplex Selection */
+#define USART_CR3_NACK 0x0010U /*!<Smartcard NACK enable */
+#define USART_CR3_SCEN 0x0020U /*!<Smartcard mode enable */
+#define USART_CR3_DMAR 0x0040U /*!<DMA Enable Receiver */
+#define USART_CR3_DMAT 0x0080U /*!<DMA Enable Transmitter */
+#define USART_CR3_RTSE 0x0100U /*!<RTS Enable */
+#define USART_CR3_CTSE 0x0200U /*!<CTS Enable */
+#define USART_CR3_CTSIE 0x0400U /*!<CTS Interrupt Enable */
+#define USART_CR3_ONEBIT 0x0800U /*!<USART One bit method enable */
+
+/****************** Bit definition for USART_GTPR register ******************/
+#define USART_GTPR_PSC 0x00FFU /*!<PSC[7:0] bits (Prescaler value) */
+#define USART_GTPR_PSC_0 0x0001U /*!<Bit 0 */
+#define USART_GTPR_PSC_1 0x0002U /*!<Bit 1 */
+#define USART_GTPR_PSC_2 0x0004U /*!<Bit 2 */
+#define USART_GTPR_PSC_3 0x0008U /*!<Bit 3 */
+#define USART_GTPR_PSC_4 0x0010U /*!<Bit 4 */
+#define USART_GTPR_PSC_5 0x0020U /*!<Bit 5 */
+#define USART_GTPR_PSC_6 0x0040U /*!<Bit 6 */
+#define USART_GTPR_PSC_7 0x0080U /*!<Bit 7 */
+
+#define USART_GTPR_GT 0xFF00U /*!<Guard time value */
+
+/******************************************************************************/
+/* */
+/* Window WATCHDOG */
+/* */
+/******************************************************************************/
+/******************* Bit definition for WWDG_CR register ********************/
+#define WWDG_CR_T 0x7FU /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
+#define WWDG_CR_T_0 0x01U /*!<Bit 0 */
+#define WWDG_CR_T_1 0x02U /*!<Bit 1 */
+#define WWDG_CR_T_2 0x04U /*!<Bit 2 */
+#define WWDG_CR_T_3 0x08U /*!<Bit 3 */
+#define WWDG_CR_T_4 0x10U /*!<Bit 4 */
+#define WWDG_CR_T_5 0x20U /*!<Bit 5 */
+#define WWDG_CR_T_6 0x40U /*!<Bit 6 */
+/* Legacy defines */
+#define WWDG_CR_T0 WWDG_CR_T_0
+#define WWDG_CR_T1 WWDG_CR_T_1
+#define WWDG_CR_T2 WWDG_CR_T_2
+#define WWDG_CR_T3 WWDG_CR_T_3
+#define WWDG_CR_T4 WWDG_CR_T_4
+#define WWDG_CR_T5 WWDG_CR_T_5
+#define WWDG_CR_T6 WWDG_CR_T_6
+
+#define WWDG_CR_WDGA 0x80U /*!<Activation bit */
+
+/******************* Bit definition for WWDG_CFR register *******************/
+#define WWDG_CFR_W 0x007FU /*!<W[6:0] bits (7-bit window value) */
+#define WWDG_CFR_W_0 0x0001U /*!<Bit 0 */
+#define WWDG_CFR_W_1 0x0002U /*!<Bit 1 */
+#define WWDG_CFR_W_2 0x0004U /*!<Bit 2 */
+#define WWDG_CFR_W_3 0x0008U /*!<Bit 3 */
+#define WWDG_CFR_W_4 0x0010U /*!<Bit 4 */
+#define WWDG_CFR_W_5 0x0020U /*!<Bit 5 */
+#define WWDG_CFR_W_6 0x0040U /*!<Bit 6 */
+/* Legacy defines */
+#define WWDG_CFR_W0 WWDG_CFR_W_0
+#define WWDG_CFR_W1 WWDG_CFR_W_1
+#define WWDG_CFR_W2 WWDG_CFR_W_2
+#define WWDG_CFR_W3 WWDG_CFR_W_3
+#define WWDG_CFR_W4 WWDG_CFR_W_4
+#define WWDG_CFR_W5 WWDG_CFR_W_5
+#define WWDG_CFR_W6 WWDG_CFR_W_6
+
+#define WWDG_CFR_WDGTB 0x0180U /*!<WDGTB[1:0] bits (Timer Base) */
+#define WWDG_CFR_WDGTB_0 0x0080U /*!<Bit 0 */
+#define WWDG_CFR_WDGTB_1 0x0100U /*!<Bit 1 */
+/* Legacy defines */
+#define WWDG_CFR_WDGTB0 WWDG_CFR_WDGTB_0
+#define WWDG_CFR_WDGTB1 WWDG_CFR_WDGTB_1
+
+#define WWDG_CFR_EWI 0x0200U /*!<Early Wakeup Interrupt */
+
+/******************* Bit definition for WWDG_SR register ********************/
+#define WWDG_SR_EWIF 0x01U /*!<Early Wakeup Interrupt Flag */
+
+/******************************************************************************/
+/* */
+/* Digital to Analog Converter */
+/* */
+/******************************************************************************/
+/******************** Bit definition for DAC_CR register ********************/
+#define DAC_CR_EN1 0x00000001U /*!<DAC channel1 enable */
+#define DAC_CR_BOFF1 0x00000002U /*!<DAC channel1 output buffer disable */
+#define DAC_CR_TEN1 0x00000004U /*!<DAC channel1 Trigger enable */
+
+#define DAC_CR_TSEL1 0x00000038U /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */
+#define DAC_CR_TSEL1_0 0x00000008U /*!<Bit 0 */
+#define DAC_CR_TSEL1_1 0x00000010U /*!<Bit 1 */
+#define DAC_CR_TSEL1_2 0x00000020U /*!<Bit 2 */
+
+#define DAC_CR_WAVE1 0x000000C0U /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
+#define DAC_CR_WAVE1_0 0x00000040U /*!<Bit 0 */
+#define DAC_CR_WAVE1_1 0x00000080U /*!<Bit 1 */
+
+#define DAC_CR_MAMP1 0x00000F00U /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
+#define DAC_CR_MAMP1_0 0x00000100U /*!<Bit 0 */
+#define DAC_CR_MAMP1_1 0x00000200U /*!<Bit 1 */
+#define DAC_CR_MAMP1_2 0x00000400U /*!<Bit 2 */
+#define DAC_CR_MAMP1_3 0x00000800U /*!<Bit 3 */
+
+#define DAC_CR_DMAEN1 0x00001000U /*!<DAC channel1 DMA enable */
+#define DAC_CR_DMAUDRIE1 0x00002000U /*!<DAC channel1 DMA underrun interrupt enable*/
+#define DAC_CR_EN2 0x00010000U /*!<DAC channel2 enable */
+#define DAC_CR_BOFF2 0x00020000U /*!<DAC channel2 output buffer disable */
+#define DAC_CR_TEN2 0x00040000U /*!<DAC channel2 Trigger enable */
+
+#define DAC_CR_TSEL2 0x00380000U /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */
+#define DAC_CR_TSEL2_0 0x00080000U /*!<Bit 0 */
+#define DAC_CR_TSEL2_1 0x00100000U /*!<Bit 1 */
+#define DAC_CR_TSEL2_2 0x00200000U /*!<Bit 2 */
+
+#define DAC_CR_WAVE2 0x00C00000U /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
+#define DAC_CR_WAVE2_0 0x00400000U /*!<Bit 0 */
+#define DAC_CR_WAVE2_1 0x00800000U /*!<Bit 1 */
+
+#define DAC_CR_MAMP2 0x0F000000U /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
+#define DAC_CR_MAMP2_0 0x01000000U /*!<Bit 0 */
+#define DAC_CR_MAMP2_1 0x02000000U /*!<Bit 1 */
+#define DAC_CR_MAMP2_2 0x04000000U /*!<Bit 2 */
+#define DAC_CR_MAMP2_3 0x08000000U /*!<Bit 3 */
+
+#define DAC_CR_DMAEN2 0x10000000U /*!<DAC channel2 DMA enabled */
+#define DAC_CR_DMAUDRIE2 0x20000000U /*!<DAC channel2 DMA underrun interrupt enable*/
+
+/***************** Bit definition for DAC_SWTRIGR register ******************/
+#define DAC_SWTRIGR_SWTRIG1 0x01U /*!<DAC channel1 software trigger */
+#define DAC_SWTRIGR_SWTRIG2 0x02U /*!<DAC channel2 software trigger */
+
+/***************** Bit definition for DAC_DHR12R1 register ******************/
+#define DAC_DHR12R1_DACC1DHR 0x0FFFU /*!<DAC channel1 12-bit Right aligned data */
+
+/***************** Bit definition for DAC_DHR12L1 register ******************/
+#define DAC_DHR12L1_DACC1DHR 0xFFF0U /*!<DAC channel1 12-bit Left aligned data */
+
+/****************** Bit definition for DAC_DHR8R1 register ******************/
+#define DAC_DHR8R1_DACC1DHR 0xFFU /*!<DAC channel1 8-bit Right aligned data */
+
+/***************** Bit definition for DAC_DHR12R2 register ******************/
+#define DAC_DHR12R2_DACC2DHR 0x0FFFU /*!<DAC channel2 12-bit Right aligned data */
+
+/***************** Bit definition for DAC_DHR12L2 register ******************/
+#define DAC_DHR12L2_DACC2DHR 0xFFF0U /*!<DAC channel2 12-bit Left aligned data */
+
+/****************** Bit definition for DAC_DHR8R2 register ******************/
+#define DAC_DHR8R2_DACC2DHR 0xFFU /*!<DAC channel2 8-bit Right aligned data */
+
+/***************** Bit definition for DAC_DHR12RD register ******************/
+#define DAC_DHR12RD_DACC1DHR 0x00000FFFU /*!<DAC channel1 12-bit Right aligned data */
+#define DAC_DHR12RD_DACC2DHR 0x0FFF0000U /*!<DAC channel2 12-bit Right aligned data */
+
+/***************** Bit definition for DAC_DHR12LD register ******************/
+#define DAC_DHR12LD_DACC1DHR 0x0000FFF0U /*!<DAC channel1 12-bit Left aligned data */
+#define DAC_DHR12LD_DACC2DHR 0xFFF00000U /*!<DAC channel2 12-bit Left aligned data */
+
+/****************** Bit definition for DAC_DHR8RD register ******************/
+#define DAC_DHR8RD_DACC1DHR 0x00FFU /*!<DAC channel1 8-bit Right aligned data */
+#define DAC_DHR8RD_DACC2DHR 0xFF00U /*!<DAC channel2 8-bit Right aligned data */
+
+/******************* Bit definition for DAC_DOR1 register *******************/
+#define DAC_DOR1_DACC1DOR 0x0FFFU /*!<DAC channel1 data output */
+
+/******************* Bit definition for DAC_DOR2 register *******************/
+#define DAC_DOR2_DACC2DOR 0x0FFFU /*!<DAC channel2 data output */
+
+/******************** Bit definition for DAC_SR register ********************/
+#define DAC_SR_DMAUDR1 0x00002000U /*!<DAC channel1 DMA underrun flag */
+#define DAC_SR_DMAUDR2 0x20000000U /*!<DAC channel2 DMA underrun flag */
+/******************************************************************************/
+/* */
+/* DBG */
+/* */
+/******************************************************************************/
+/******************** Bit definition for DBGMCU_IDCODE register *************/
+#define DBGMCU_IDCODE_DEV_ID 0x00000FFFU
+#define DBGMCU_IDCODE_REV_ID 0xFFFF0000U
+
+/******************** Bit definition for DBGMCU_CR register *****************/
+#define DBGMCU_CR_DBG_SLEEP 0x00000001U
+#define DBGMCU_CR_DBG_STOP 0x00000002U
+#define DBGMCU_CR_DBG_STANDBY 0x00000004U
+#define DBGMCU_CR_TRACE_IOEN 0x00000020U
+
+#define DBGMCU_CR_TRACE_MODE 0x000000C0U
+#define DBGMCU_CR_TRACE_MODE_0 0x00000040U/*!<Bit 0 */
+#define DBGMCU_CR_TRACE_MODE_1 0x00000080U/*!<Bit 1 */
+
+/******************** Bit definition for DBGMCU_APB1_FZ register ************/
+#define DBGMCU_APB1_FZ_DBG_TIM5_STOP 0x00000008U
+#define DBGMCU_APB1_FZ_DBG_TIM6_STOP 0x00000010U
+#define DBGMCU_APB1_FZ_DBG_RTC_STOP 0x00000400U
+#define DBGMCU_APB1_FZ_DBG_WWDG_STOP 0x00000800U
+#define DBGMCU_APB1_FZ_DBG_IWDG_STOP 0x00001000U
+#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT 0x00200000U
+#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT 0x00400000U
+#define DBGMCU_APB1_FZ_DBG_CAN1_STOP 0x02000000U
+#define DBGMCU_APB1_FZ_DBG_CAN2_STOP 0x04000000U
+
+/******************** Bit definition for DBGMCU_APB2_FZ register ************/
+#define DBGMCU_APB2_FZ_DBG_TIM1_STOP 0x00000001U
+#define DBGMCU_APB2_FZ_DBG_TIM9_STOP 0x00010000U
+#define DBGMCU_APB2_FZ_DBG_TIM11_STOP 0x00040000U
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup Exported_macros
+ * @{
+ */
+
+/******************************* ADC Instances ********************************/
+#define IS_ADC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
+
+/******************************* CRC Instances ********************************/
+#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
+
+/******************************* DAC Instances ********************************/
+#define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC)
+
+/******************************** DMA Instances *******************************/
+#define IS_DMA_STREAM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0) || \
+ ((INSTANCE) == DMA1_Stream1) || \
+ ((INSTANCE) == DMA1_Stream2) || \
+ ((INSTANCE) == DMA1_Stream3) || \
+ ((INSTANCE) == DMA1_Stream4) || \
+ ((INSTANCE) == DMA1_Stream5) || \
+ ((INSTANCE) == DMA1_Stream6) || \
+ ((INSTANCE) == DMA1_Stream7) || \
+ ((INSTANCE) == DMA2_Stream0) || \
+ ((INSTANCE) == DMA2_Stream1) || \
+ ((INSTANCE) == DMA2_Stream2) || \
+ ((INSTANCE) == DMA2_Stream3) || \
+ ((INSTANCE) == DMA2_Stream4) || \
+ ((INSTANCE) == DMA2_Stream5) || \
+ ((INSTANCE) == DMA2_Stream6) || \
+ ((INSTANCE) == DMA2_Stream7))
+
+/******************************* GPIO Instances *******************************/
+#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
+ ((INSTANCE) == GPIOB) || \
+ ((INSTANCE) == GPIOC) || \
+ ((INSTANCE) == GPIOH))
+
+/******************************** I2C Instances *******************************/
+#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
+ ((INSTANCE) == I2C2))
+/******************************** I2S Instances *******************************/
+#define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
+ ((INSTANCE) == SPI2) || \
+ ((INSTANCE) == SPI5))
+
+/******************************* LPTIM Instances ******************************/
+#define IS_LPTIM_INSTANCE(__INSTANCE__) ((__INSTANCE__) == LPTIM1)
+
+/******************************* RNG Instances ********************************/
+#define IS_RNG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RNG)
+
+/****************************** RTC Instances *********************************/
+#define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
+
+/******************************** SPI Instances *******************************/
+#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
+ ((INSTANCE) == SPI2) || \
+ ((INSTANCE) == SPI5))
+/*************************** SPI Extended Instances ***************************/
+#define IS_SPI_ALL_INSTANCE_EXT(INSTANCE) (((INSTANCE) == SPI1) || \
+ ((INSTANCE) == SPI2) || \
+ ((INSTANCE) == SPI5))
+
+/****************** TIM Instances : All supported instances *******************/
+#define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM6) || \
+ ((INSTANCE) == TIM9) || \
+ ((INSTANCE) == TIM11))
+
+/************* TIM Instances : at least 1 capture/compare channel *************/
+#define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM9) || \
+ ((INSTANCE) == TIM11))
+
+/************ TIM Instances : at least 2 capture/compare channels *************/
+#define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM9))
+
+/************ TIM Instances : at least 3 capture/compare channels *************/
+#define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM5))
+
+/************ TIM Instances : at least 4 capture/compare channels *************/
+#define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM5))
+
+/******************** TIM Instances : Advanced-control timers *****************/
+#define IS_TIM_ADVANCED_INSTANCE(INSTANCE) ((INSTANCE) == TIM1)
+
+/******************* TIM Instances : Timer input XOR function *****************/
+#define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM5))
+
+/****************** TIM Instances : DMA requests generation (UDE) *************/
+#define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM6))
+
+/************ TIM Instances : DMA requests generation (CCxDE) *****************/
+#define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM5))
+
+/************ TIM Instances : DMA requests generation (COMDE) *****************/
+#define IS_TIM_CCDMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM5))
+
+/******************** TIM Instances : DMA burst feature ***********************/
+#define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM5))
+
+/****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/
+#define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM6) || \
+ ((INSTANCE) == TIM9))
+
+/*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
+#define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM9))
+
+/********************** TIM Instances : 32 bit Counter ************************/
+#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)(((INSTANCE) == TIM5))
+
+/***************** TIM Instances : external trigger input availabe ************/
+#define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM5))
+
+/****************** TIM Instances : remapping capability **********************/
+#define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM11))
+
+/******************* TIM Instances : output(s) available **********************/
+#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
+ ((((INSTANCE) == TIM1) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM5) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM9) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2))) \
+ || \
+ (((INSTANCE) == TIM11) && \
+ (((CHANNEL) == TIM_CHANNEL_1))))
+
+/************ TIM Instances : complementary output(s) available ***************/
+#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
+ ((((INSTANCE) == TIM1) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3))))
+
+/******************** USART Instances : Synchronous mode **********************/
+#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART6))
+
+/******************** UART Instances : Asynchronous mode **********************/
+#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART6))
+
+/****************** UART Instances : Hardware Flow control ********************/
+#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2))
+
+/********************* UART Instances : Smard card mode ***********************/
+#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART6))
+
+/*********************** UART Instances : IRDA mode ***************************/
+#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART6))
+
+/****************************** IWDG Instances ********************************/
+#define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
+
+/****************************** WWDG Instances ********************************/
+#define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
+
+/***************************** FMPI2C Instances *******************************/
+#define IS_FMPI2C_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == FMPI2C1)
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* __STM32F410Cx_H */
+
+
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Device/ST/STM32F4xx/Include/stm32f410rx.h b/Device/ST/STM32F4xx/Include/stm32f410rx.h
new file mode 100644
index 0000000..59e3c93
--- /dev/null
+++ b/Device/ST/STM32F4xx/Include/stm32f410rx.h
@@ -0,0 +1,4001 @@
+/**
+ ******************************************************************************
+ * @file stm32f410rx.h
+ * @author MCD Application Team
+ * @version V2.5.0
+ * @date 22-April-2016
+ * @brief CMSIS STM32F410Rx Device Peripheral Access Layer Header File.
+ *
+ * This file contains:
+ * - Data structures and the address mapping for all peripherals
+ * - peripherals registers declarations and bits definition
+ * - Macros to access peripheral’s registers hardware
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/** @addtogroup CMSIS
+ * @{
+ */
+
+/** @addtogroup stm32f410rx
+ * @{
+ */
+
+#ifndef __STM32F410Rx_H
+#define __STM32F410Rx_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif /* __cplusplus */
+
+
+/** @addtogroup Configuration_section_for_CMSIS
+ * @{
+ */
+
+/**
+ * @brief Configuration of the Cortex-M4 Processor and Core Peripherals
+ */
+#define __CM4_REV 0x0001U /*!< Core revision r0p1 */
+#define __MPU_PRESENT 1U /*!< STM32F4XX provides an MPU */
+#define __NVIC_PRIO_BITS 4U /*!< STM32F4XX uses 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */
+#define __FPU_PRESENT 1U /*!< FPU present */
+
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_interrupt_number_definition
+ * @{
+ */
+
+/**
+ * @brief STM32F4XX Interrupt Number Definition, according to the selected device
+ * in @ref Library_configuration_section
+ */
+typedef enum
+{
+/****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/
+ NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
+ MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */
+ BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */
+ UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */
+ SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */
+ DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */
+ PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */
+ SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */
+/****** STM32 specific Interrupt Numbers **********************************************************************/
+ WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
+ PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */
+ TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */
+ RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */
+ FLASH_IRQn = 4, /*!< FLASH global Interrupt */
+ RCC_IRQn = 5, /*!< RCC global Interrupt */
+ EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */
+ EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */
+ EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */
+ EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */
+ EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */
+ DMA1_Stream0_IRQn = 11, /*!< DMA1 Stream 0 global Interrupt */
+ DMA1_Stream1_IRQn = 12, /*!< DMA1 Stream 1 global Interrupt */
+ DMA1_Stream2_IRQn = 13, /*!< DMA1 Stream 2 global Interrupt */
+ DMA1_Stream3_IRQn = 14, /*!< DMA1 Stream 3 global Interrupt */
+ DMA1_Stream4_IRQn = 15, /*!< DMA1 Stream 4 global Interrupt */
+ DMA1_Stream5_IRQn = 16, /*!< DMA1 Stream 5 global Interrupt */
+ DMA1_Stream6_IRQn = 17, /*!< DMA1 Stream 6 global Interrupt */
+ ADC_IRQn = 18, /*!< ADC1 global Interrupts */
+ EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
+ TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break interrupt and TIM9 global interrupt */
+ TIM1_UP_IRQn = 25, /*!< TIM1 Update Interrupt */
+ TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */
+ TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
+ I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
+ I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
+ I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
+ I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
+ SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
+ SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
+ USART1_IRQn = 37, /*!< USART1 global Interrupt */
+ USART2_IRQn = 38, /*!< USART2 global Interrupt */
+ EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
+ RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */
+ DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */
+ TIM5_IRQn = 50, /*!< TIM5 global Interrupt */
+ TIM6_DAC_IRQn = 54, /*!< TIM6 global Interrupt and DAC Global Interrupt */
+ DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */
+ DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */
+ DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */
+ DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */
+ DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */
+ DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */
+ DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */
+ DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */
+ USART6_IRQn = 71, /*!< USART6 global interrupt */
+ RNG_IRQn = 80, /*!< RNG global Interrupt */
+ FPU_IRQn = 81, /*!< FPU global interrupt */
+ SPI5_IRQn = 85, /*!< SPI5 global Interrupt */
+ FMPI2C1_EV_IRQn = 95, /*!< FMPI2C1 Event Interrupt */
+ FMPI2C1_ER_IRQn = 96, /*!< FMPI2C1 Error Interrupt */
+ LPTIM1_IRQn = 97 /*!< LPTIM1 interrupt */
+} IRQn_Type;
+
+/**
+ * @}
+ */
+
+#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
+#include "system_stm32f4xx.h"
+#include <stdint.h>
+
+/** @addtogroup Peripheral_registers_structures
+ * @{
+ */
+
+/**
+ * @brief Analog to Digital Converter
+ */
+
+typedef struct
+{
+ __IO uint32_t SR; /*!< ADC status register, Address offset: 0x00 */
+ __IO uint32_t CR1; /*!< ADC control register 1, Address offset: 0x04 */
+ __IO uint32_t CR2; /*!< ADC control register 2, Address offset: 0x08 */
+ __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x0C */
+ __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x10 */
+ __IO uint32_t JOFR1; /*!< ADC injected channel data offset register 1, Address offset: 0x14 */
+ __IO uint32_t JOFR2; /*!< ADC injected channel data offset register 2, Address offset: 0x18 */
+ __IO uint32_t JOFR3; /*!< ADC injected channel data offset register 3, Address offset: 0x1C */
+ __IO uint32_t JOFR4; /*!< ADC injected channel data offset register 4, Address offset: 0x20 */
+ __IO uint32_t HTR; /*!< ADC watchdog higher threshold register, Address offset: 0x24 */
+ __IO uint32_t LTR; /*!< ADC watchdog lower threshold register, Address offset: 0x28 */
+ __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x2C */
+ __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x30 */
+ __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x34 */
+ __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x38*/
+ __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x3C */
+ __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x40 */
+ __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x44 */
+ __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x48 */
+ __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x4C */
+} ADC_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1 base address + 0x300 */
+ __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1 base address + 0x304 */
+ __IO uint32_t CDR; /*!< ADC common regular data register for dual
+ AND triple modes, Address offset: ADC1 base address + 0x308 */
+} ADC_Common_TypeDef;
+
+/**
+ * @brief CRC calculation unit
+ */
+
+typedef struct
+{
+ __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
+ __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
+ uint8_t RESERVED0; /*!< Reserved, 0x05 */
+ uint16_t RESERVED1; /*!< Reserved, 0x06 */
+ __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
+} CRC_TypeDef;
+
+/**
+ * @brief Digital to Analog Converter
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */
+ __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */
+ __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
+ __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */
+ __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */
+ __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
+ __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */
+ __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */
+ __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */
+ __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */
+ __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */
+ __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */
+ __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */
+ __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */
+} DAC_TypeDef;
+
+/**
+ * @brief Debug MCU
+ */
+
+typedef struct
+{
+ __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
+ __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
+ __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */
+ __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */
+}DBGMCU_TypeDef;
+
+
+/**
+ * @brief DMA Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< DMA stream x configuration register */
+ __IO uint32_t NDTR; /*!< DMA stream x number of data register */
+ __IO uint32_t PAR; /*!< DMA stream x peripheral address register */
+ __IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */
+ __IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */
+ __IO uint32_t FCR; /*!< DMA stream x FIFO control register */
+} DMA_Stream_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t LISR; /*!< DMA low interrupt status register, Address offset: 0x00 */
+ __IO uint32_t HISR; /*!< DMA high interrupt status register, Address offset: 0x04 */
+ __IO uint32_t LIFCR; /*!< DMA low interrupt flag clear register, Address offset: 0x08 */
+ __IO uint32_t HIFCR; /*!< DMA high interrupt flag clear register, Address offset: 0x0C */
+} DMA_TypeDef;
+
+
+/**
+ * @brief External Interrupt/Event Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t IMR; /*!< EXTI Interrupt mask register, Address offset: 0x00 */
+ __IO uint32_t EMR; /*!< EXTI Event mask register, Address offset: 0x04 */
+ __IO uint32_t RTSR; /*!< EXTI Rising trigger selection register, Address offset: 0x08 */
+ __IO uint32_t FTSR; /*!< EXTI Falling trigger selection register, Address offset: 0x0C */
+ __IO uint32_t SWIER; /*!< EXTI Software interrupt event register, Address offset: 0x10 */
+ __IO uint32_t PR; /*!< EXTI Pending register, Address offset: 0x14 */
+} EXTI_TypeDef;
+
+/**
+ * @brief FLASH Registers
+ */
+
+typedef struct
+{
+ __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */
+ __IO uint32_t KEYR; /*!< FLASH key register, Address offset: 0x04 */
+ __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x08 */
+ __IO uint32_t SR; /*!< FLASH status register, Address offset: 0x0C */
+ __IO uint32_t CR; /*!< FLASH control register, Address offset: 0x10 */
+ __IO uint32_t OPTCR; /*!< FLASH option control register , Address offset: 0x14 */
+ __IO uint32_t OPTCR1; /*!< FLASH option control register 1, Address offset: 0x18 */
+} FLASH_TypeDef;
+
+/**
+ * @brief General Purpose I/O
+ */
+
+typedef struct
+{
+ __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
+ __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */
+ __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */
+ __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
+ __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
+ __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
+ __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */
+ __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
+ __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */
+} GPIO_TypeDef;
+
+/**
+ * @brief System configuration controller
+ */
+
+typedef struct
+{
+ __IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */
+ __IO uint32_t PMC; /*!< SYSCFG peripheral mode configuration register, Address offset: 0x04 */
+ __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
+ uint32_t RESERVED; /*!< Reserved, 0x18 */
+ uint32_t CFGR2; /*!< Reserved, 0x1C */
+ __IO uint32_t CMPCR; /*!< SYSCFG Compensation cell control register, Address offset: 0x20 */
+ uint32_t RESERVED1[2]; /*!< Reserved, 0x24-0x28 */
+ __IO uint32_t CFGR; /*!< SYSCFG Configuration register, Address offset: 0x2C */
+} SYSCFG_TypeDef;
+
+/**
+ * @brief Inter-integrated Circuit Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */
+ __IO uint32_t OAR1; /*!< I2C Own address register 1, Address offset: 0x08 */
+ __IO uint32_t OAR2; /*!< I2C Own address register 2, Address offset: 0x0C */
+ __IO uint32_t DR; /*!< I2C Data register, Address offset: 0x10 */
+ __IO uint32_t SR1; /*!< I2C Status register 1, Address offset: 0x14 */
+ __IO uint32_t SR2; /*!< I2C Status register 2, Address offset: 0x18 */
+ __IO uint32_t CCR; /*!< I2C Clock control register, Address offset: 0x1C */
+ __IO uint32_t TRISE; /*!< I2C TRISE register, Address offset: 0x20 */
+ __IO uint32_t FLTR; /*!< I2C FLTR register, Address offset: 0x24 */
+} I2C_TypeDef;
+
+/**
+ * @brief Inter-integrated Circuit Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t CR1; /*!< FMPI2C Control register 1, Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< FMPI2C Control register 2, Address offset: 0x04 */
+ __IO uint32_t OAR1; /*!< FMPI2C Own address 1 register, Address offset: 0x08 */
+ __IO uint32_t OAR2; /*!< FMPI2C Own address 2 register, Address offset: 0x0C */
+ __IO uint32_t TIMINGR; /*!< FMPI2C Timing register, Address offset: 0x10 */
+ __IO uint32_t TIMEOUTR; /*!< FMPI2C Timeout register, Address offset: 0x14 */
+ __IO uint32_t ISR; /*!< FMPI2C Interrupt and status register, Address offset: 0x18 */
+ __IO uint32_t ICR; /*!< FMPI2C Interrupt clear register, Address offset: 0x1C */
+ __IO uint32_t PECR; /*!< FMPI2C PEC register, Address offset: 0x20 */
+ __IO uint32_t RXDR; /*!< FMPI2C Receive data register, Address offset: 0x24 */
+ __IO uint32_t TXDR; /*!< FMPI2C Transmit data register, Address offset: 0x28 */
+} FMPI2C_TypeDef;
+
+/**
+ * @brief Independent WATCHDOG
+ */
+
+typedef struct
+{
+ __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */
+ __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */
+ __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */
+ __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */
+} IWDG_TypeDef;
+
+/**
+ * @brief Power Control
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */
+ __IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */
+} PWR_TypeDef;
+
+/**
+ * @brief Reset and Clock Control
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */
+ __IO uint32_t PLLCFGR; /*!< RCC PLL configuration register, Address offset: 0x04 */
+ __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x08 */
+ __IO uint32_t CIR; /*!< RCC clock interrupt register, Address offset: 0x0C */
+ __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x10 */
+ uint32_t RESERVED0[3]; /*!< Reserved, 0x14-0x1C */
+ __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x20 */
+ __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x24 */
+ uint32_t RESERVED1[2]; /*!< Reserved, 0x28-0x2C */
+ __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clock register, Address offset: 0x30 */
+ uint32_t RESERVED2[3]; /*!< Reserved, 0x34-0x3C */
+ __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x40 */
+ __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x44 */
+ uint32_t RESERVED3[2]; /*!< Reserved, 0x48-0x4C */
+ __IO uint32_t AHB1LPENR; /*!< RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 */
+ uint32_t RESERVED4[3]; /*!< Reserved, 0x54-0x5C */
+ __IO uint32_t APB1LPENR; /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 */
+ __IO uint32_t APB2LPENR; /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 */
+ uint32_t RESERVED5[2]; /*!< Reserved, 0x68-0x6C */
+ __IO uint32_t BDCR; /*!< RCC Backup domain control register, Address offset: 0x70 */
+ __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x74 */
+ uint32_t RESERVED6[2]; /*!< Reserved, 0x78-0x7C */
+ __IO uint32_t SSCGR; /*!< RCC spread spectrum clock generation register, Address offset: 0x80 */
+ uint32_t RESERVED7[2]; /*!< Reserved, 0x84-0x88 */
+ __IO uint32_t DCKCFGR; /*!< RCC Dedicated Clocks configuration register, Address offset: 0x8C */
+ __IO uint32_t CKGATENR; /*!< RCC Clocks Gated ENable Register, Address offset: 0x90 */
+ __IO uint32_t DCKCFGR2; /*!< RCC Dedicated Clocks configuration register 2, Address offset: 0x94 */
+
+} RCC_TypeDef;
+
+/**
+ * @brief Real-Time Clock
+ */
+
+typedef struct
+{
+ __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
+ __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */
+ __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */
+ __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */
+ __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */
+ __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */
+ __IO uint32_t CALIBR; /*!< RTC calibration register, Address offset: 0x18 */
+ __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */
+ __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */
+ __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */
+ __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */
+ __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */
+ __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */
+ __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */
+ __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */
+ __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */
+ __IO uint32_t TAFCR; /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */
+ __IO uint32_t ALRMASSR;/*!< RTC alarm A sub second register, Address offset: 0x44 */
+ __IO uint32_t ALRMBSSR;/*!< RTC alarm B sub second register, Address offset: 0x48 */
+ uint32_t RESERVED7; /*!< Reserved, 0x4C */
+ __IO uint32_t BKP0R; /*!< RTC backup register 1, Address offset: 0x50 */
+ __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */
+ __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */
+ __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */
+ __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */
+ __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */
+ __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */
+ __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */
+ __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */
+ __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */
+ __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */
+ __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */
+ __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */
+ __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */
+ __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */
+ __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */
+ __IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */
+ __IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */
+ __IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */
+ __IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */
+} RTC_TypeDef;
+
+/**
+ * @brief Serial Peripheral Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t CR1; /*!< SPI control register 1 (not used in I2S mode), Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< SPI control register 2, Address offset: 0x04 */
+ __IO uint32_t SR; /*!< SPI status register, Address offset: 0x08 */
+ __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */
+ __IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
+ __IO uint32_t RXCRCR; /*!< SPI RX CRC register (not used in I2S mode), Address offset: 0x14 */
+ __IO uint32_t TXCRCR; /*!< SPI TX CRC register (not used in I2S mode), Address offset: 0x18 */
+ __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */
+ __IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */
+} SPI_TypeDef;
+
+/**
+ * @brief TIM
+ */
+
+typedef struct
+{
+ __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
+ __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */
+ __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
+ __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
+ __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
+ __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
+ __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
+ __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
+ __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
+ __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */
+ __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
+ __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */
+ __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
+ __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
+ __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
+ __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
+ __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
+ __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
+ __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */
+ __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */
+} TIM_TypeDef;
+
+/**
+ * @brief Universal Synchronous Asynchronous Receiver Transmitter
+ */
+
+typedef struct
+{
+ __IO uint32_t SR; /*!< USART Status register, Address offset: 0x00 */
+ __IO uint32_t DR; /*!< USART Data register, Address offset: 0x04 */
+ __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x08 */
+ __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x0C */
+ __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x10 */
+ __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x14 */
+ __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x18 */
+} USART_TypeDef;
+
+/**
+ * @brief Window WATCHDOG
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
+ __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
+ __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
+} WWDG_TypeDef;
+
+
+/**
+ * @brief RNG
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */
+ __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */
+ __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */
+} RNG_TypeDef;
+
+
+/**
+ * @brief LPTIMER
+ */
+typedef struct
+{
+ __IO uint32_t ISR; /*!< LPTIM Interrupt and Status register, Address offset: 0x00 */
+ __IO uint32_t ICR; /*!< LPTIM Interrupt Clear register, Address offset: 0x04 */
+ __IO uint32_t IER; /*!< LPTIM Interrupt Enable register, Address offset: 0x08 */
+ __IO uint32_t CFGR; /*!< LPTIM Configuration register, Address offset: 0x0C */
+ __IO uint32_t CR; /*!< LPTIM Control register, Address offset: 0x10 */
+ __IO uint32_t CMP; /*!< LPTIM Compare register, Address offset: 0x14 */
+ __IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */
+ __IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */
+ __IO uint32_t OR; /*!< LPTIM Option register, Address offset: 0x20 */
+} LPTIM_TypeDef;
+
+/**
+ * @brief Peripheral_memory_map
+ */
+#define FLASH_BASE 0x08000000U /*!< FLASH(up to 1 MB) base address in the alias region */
+#define SRAM1_BASE 0x20000000U /*!< SRAM1(32 KB) base address in the alias region */
+#define PERIPH_BASE 0x40000000U /*!< Peripheral base address in the alias region */
+#define SRAM1_BB_BASE 0x22000000U /*!< SRAM1(32 KB) base address in the bit-band region */
+#define PERIPH_BB_BASE 0x42000000U /*!< Peripheral base address in the bit-band region */
+#define FLASH_END 0x0801FFFFU /*!< FLASH end address */
+
+/* Legacy defines */
+#define SRAM_BASE SRAM1_BASE
+#define SRAM_BB_BASE SRAM1_BB_BASE
+
+/*!< Peripheral memory map */
+#define APB1PERIPH_BASE PERIPH_BASE
+#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000U)
+#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000U)
+
+/*!< APB1 peripherals */
+#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00U)
+#define TIM6_BASE (APB1PERIPH_BASE + 0x1000U)
+#define LPTIM1_BASE (APB1PERIPH_BASE + 0x2400U)
+#define RTC_BASE (APB1PERIPH_BASE + 0x2800U)
+#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00U)
+#define IWDG_BASE (APB1PERIPH_BASE + 0x3000U)
+#define I2S2ext_BASE (APB1PERIPH_BASE + 0x3400U)
+#define SPI2_BASE (APB1PERIPH_BASE + 0x3800U)
+#define USART2_BASE (APB1PERIPH_BASE + 0x4400U)
+#define I2C1_BASE (APB1PERIPH_BASE + 0x5400U)
+#define I2C2_BASE (APB1PERIPH_BASE + 0x5800U)
+#define FMPI2C1_BASE (APB1PERIPH_BASE + 0x6000U)
+#define PWR_BASE (APB1PERIPH_BASE + 0x7000U)
+#define DAC_BASE (APB1PERIPH_BASE + 0x7400U)
+/*!< APB2 peripherals */
+#define TIM1_BASE (APB2PERIPH_BASE + 0x0000U)
+#define USART1_BASE (APB2PERIPH_BASE + 0x1000U)
+#define USART6_BASE (APB2PERIPH_BASE + 0x1400U)
+#define ADC1_BASE (APB2PERIPH_BASE + 0x2000U)
+#define ADC_BASE (APB2PERIPH_BASE + 0x2300U)
+#define SPI1_BASE (APB2PERIPH_BASE + 0x3000U)
+#define SYSCFG_BASE (APB2PERIPH_BASE + 0x3800U)
+#define EXTI_BASE (APB2PERIPH_BASE + 0x3C00U)
+#define TIM9_BASE (APB2PERIPH_BASE + 0x4000U)
+#define TIM11_BASE (APB2PERIPH_BASE + 0x4800U)
+#define SPI5_BASE (APB2PERIPH_BASE + 0x5000U)
+
+/*!< AHB1 peripherals */
+#define GPIOA_BASE (AHB1PERIPH_BASE + 0x0000U)
+#define GPIOB_BASE (AHB1PERIPH_BASE + 0x0400U)
+#define GPIOC_BASE (AHB1PERIPH_BASE + 0x0800U)
+#define GPIOH_BASE (AHB1PERIPH_BASE + 0x1C00U)
+#define CRC_BASE (AHB1PERIPH_BASE + 0x3000U)
+#define RCC_BASE (AHB1PERIPH_BASE + 0x3800U)
+#define FLASH_R_BASE (AHB1PERIPH_BASE + 0x3C00U)
+#define DMA1_BASE (AHB1PERIPH_BASE + 0x6000U)
+#define DMA1_Stream0_BASE (DMA1_BASE + 0x010U)
+#define DMA1_Stream1_BASE (DMA1_BASE + 0x028U)
+#define DMA1_Stream2_BASE (DMA1_BASE + 0x040U)
+#define DMA1_Stream3_BASE (DMA1_BASE + 0x058U)
+#define DMA1_Stream4_BASE (DMA1_BASE + 0x070U)
+#define DMA1_Stream5_BASE (DMA1_BASE + 0x088U)
+#define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0U)
+#define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8U)
+#define DMA2_BASE (AHB1PERIPH_BASE + 0x6400U)
+#define DMA2_Stream0_BASE (DMA2_BASE + 0x010U)
+#define DMA2_Stream1_BASE (DMA2_BASE + 0x028U)
+#define DMA2_Stream2_BASE (DMA2_BASE + 0x040U)
+#define DMA2_Stream3_BASE (DMA2_BASE + 0x058U)
+#define DMA2_Stream4_BASE (DMA2_BASE + 0x070U)
+#define DMA2_Stream5_BASE (DMA2_BASE + 0x088U)
+#define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0U)
+#define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8U)
+#define RNG_BASE (PERIPH_BASE + 0x80000U)
+
+/* Debug MCU registers base address */
+#define DBGMCU_BASE 0xE0042000U
+
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_declaration
+ * @{
+ */
+#define TIM5 ((TIM_TypeDef *) TIM5_BASE)
+#define TIM6 ((TIM_TypeDef *) TIM6_BASE)
+#define RTC ((RTC_TypeDef *) RTC_BASE)
+#define WWDG ((WWDG_TypeDef *) WWDG_BASE)
+#define IWDG ((IWDG_TypeDef *) IWDG_BASE)
+#define SPI2 ((SPI_TypeDef *) SPI2_BASE)
+#define USART2 ((USART_TypeDef *) USART2_BASE)
+#define I2C1 ((I2C_TypeDef *) I2C1_BASE)
+#define I2C2 ((I2C_TypeDef *) I2C2_BASE)
+#define FMPI2C1 ((FMPI2C_TypeDef *) FMPI2C1_BASE)
+#define LPTIM1 ((LPTIM_TypeDef *) LPTIM1_BASE)
+#define PWR ((PWR_TypeDef *) PWR_BASE)
+#define DAC ((DAC_TypeDef *) DAC_BASE)
+#define TIM1 ((TIM_TypeDef *) TIM1_BASE)
+#define USART1 ((USART_TypeDef *) USART1_BASE)
+#define USART6 ((USART_TypeDef *) USART6_BASE)
+#define ADC ((ADC_Common_TypeDef *) ADC_BASE)
+#define ADC1 ((ADC_TypeDef *) ADC1_BASE)
+#define SPI1 ((SPI_TypeDef *) SPI1_BASE)
+#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
+#define EXTI ((EXTI_TypeDef *) EXTI_BASE)
+#define TIM9 ((TIM_TypeDef *) TIM9_BASE)
+#define TIM11 ((TIM_TypeDef *) TIM11_BASE)
+#define SPI5 ((SPI_TypeDef *) SPI5_BASE)
+#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
+#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
+#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
+#define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
+#define CRC ((CRC_TypeDef *) CRC_BASE)
+#define RCC ((RCC_TypeDef *) RCC_BASE)
+#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
+#define DMA1 ((DMA_TypeDef *) DMA1_BASE)
+#define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)
+#define DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)
+#define DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)
+#define DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)
+#define DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)
+#define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)
+#define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)
+#define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)
+#define DMA2 ((DMA_TypeDef *) DMA2_BASE)
+#define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)
+#define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
+#define DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)
+#define DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)
+#define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)
+#define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)
+#define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)
+#define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)
+#define RNG ((RNG_TypeDef *) RNG_BASE)
+
+#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
+
+/**
+ * @}
+ */
+
+/** @addtogroup Exported_constants
+ * @{
+ */
+
+ /** @addtogroup Peripheral_Registers_Bits_Definition
+ * @{
+ */
+
+/******************************************************************************/
+/* Peripheral Registers_Bits_Definition */
+/******************************************************************************/
+
+/******************************************************************************/
+/* */
+/* Analog to Digital Converter */
+/* */
+/******************************************************************************/
+/******************** Bit definition for ADC_SR register ********************/
+#define ADC_SR_AWD 0x00000001U /*!<Analog watchdog flag */
+#define ADC_SR_EOC 0x00000002U /*!<End of conversion */
+#define ADC_SR_JEOC 0x00000004U /*!<Injected channel end of conversion */
+#define ADC_SR_JSTRT 0x00000008U /*!<Injected channel Start flag */
+#define ADC_SR_STRT 0x00000010U /*!<Regular channel Start flag */
+#define ADC_SR_OVR 0x00000020U /*!<Overrun flag */
+
+/******************* Bit definition for ADC_CR1 register ********************/
+#define ADC_CR1_AWDCH 0x0000001FU /*!<AWDCH[4:0] bits (Analog watchdog channel select bits) */
+#define ADC_CR1_AWDCH_0 0x00000001U /*!<Bit 0 */
+#define ADC_CR1_AWDCH_1 0x00000002U /*!<Bit 1 */
+#define ADC_CR1_AWDCH_2 0x00000004U /*!<Bit 2 */
+#define ADC_CR1_AWDCH_3 0x00000008U /*!<Bit 3 */
+#define ADC_CR1_AWDCH_4 0x00000010U /*!<Bit 4 */
+#define ADC_CR1_EOCIE 0x00000020U /*!<Interrupt enable for EOC */
+#define ADC_CR1_AWDIE 0x00000040U /*!<AAnalog Watchdog interrupt enable */
+#define ADC_CR1_JEOCIE 0x00000080U /*!<Interrupt enable for injected channels */
+#define ADC_CR1_SCAN 0x00000100U /*!<Scan mode */
+#define ADC_CR1_AWDSGL 0x00000200U /*!<Enable the watchdog on a single channel in scan mode */
+#define ADC_CR1_JAUTO 0x00000400U /*!<Automatic injected group conversion */
+#define ADC_CR1_DISCEN 0x00000800U /*!<Discontinuous mode on regular channels */
+#define ADC_CR1_JDISCEN 0x00001000U /*!<Discontinuous mode on injected channels */
+#define ADC_CR1_DISCNUM 0x0000E000U /*!<DISCNUM[2:0] bits (Discontinuous mode channel count) */
+#define ADC_CR1_DISCNUM_0 0x00002000U /*!<Bit 0 */
+#define ADC_CR1_DISCNUM_1 0x00004000U /*!<Bit 1 */
+#define ADC_CR1_DISCNUM_2 0x00008000U /*!<Bit 2 */
+#define ADC_CR1_JAWDEN 0x00400000U /*!<Analog watchdog enable on injected channels */
+#define ADC_CR1_AWDEN 0x00800000U /*!<Analog watchdog enable on regular channels */
+#define ADC_CR1_RES 0x03000000U /*!<RES[2:0] bits (Resolution) */
+#define ADC_CR1_RES_0 0x01000000U /*!<Bit 0 */
+#define ADC_CR1_RES_1 0x02000000U /*!<Bit 1 */
+#define ADC_CR1_OVRIE 0x04000000U /*!<overrun interrupt enable */
+
+/******************* Bit definition for ADC_CR2 register ********************/
+#define ADC_CR2_ADON 0x00000001U /*!<A/D Converter ON / OFF */
+#define ADC_CR2_CONT 0x00000002U /*!<Continuous Conversion */
+#define ADC_CR2_DMA 0x00000100U /*!<Direct Memory access mode */
+#define ADC_CR2_DDS 0x00000200U /*!<DMA disable selection (Single ADC) */
+#define ADC_CR2_EOCS 0x00000400U /*!<End of conversion selection */
+#define ADC_CR2_ALIGN 0x00000800U /*!<Data Alignment */
+#define ADC_CR2_JEXTSEL 0x000F0000U /*!<JEXTSEL[3:0] bits (External event select for injected group) */
+#define ADC_CR2_JEXTSEL_0 0x00010000U /*!<Bit 0 */
+#define ADC_CR2_JEXTSEL_1 0x00020000U /*!<Bit 1 */
+#define ADC_CR2_JEXTSEL_2 0x00040000U /*!<Bit 2 */
+#define ADC_CR2_JEXTSEL_3 0x00080000U /*!<Bit 3 */
+#define ADC_CR2_JEXTEN 0x00300000U /*!<JEXTEN[1:0] bits (External Trigger Conversion mode for injected channelsp) */
+#define ADC_CR2_JEXTEN_0 0x00100000U /*!<Bit 0 */
+#define ADC_CR2_JEXTEN_1 0x00200000U /*!<Bit 1 */
+#define ADC_CR2_JSWSTART 0x00400000U /*!<Start Conversion of injected channels */
+#define ADC_CR2_EXTSEL 0x0F000000U /*!<EXTSEL[3:0] bits (External Event Select for regular group) */
+#define ADC_CR2_EXTSEL_0 0x01000000U /*!<Bit 0 */
+#define ADC_CR2_EXTSEL_1 0x02000000U /*!<Bit 1 */
+#define ADC_CR2_EXTSEL_2 0x04000000U /*!<Bit 2 */
+#define ADC_CR2_EXTSEL_3 0x08000000U /*!<Bit 3 */
+#define ADC_CR2_EXTEN 0x30000000U /*!<EXTEN[1:0] bits (External Trigger Conversion mode for regular channelsp) */
+#define ADC_CR2_EXTEN_0 0x10000000U /*!<Bit 0 */
+#define ADC_CR2_EXTEN_1 0x20000000U /*!<Bit 1 */
+#define ADC_CR2_SWSTART 0x40000000U /*!<Start Conversion of regular channels */
+
+/****************** Bit definition for ADC_SMPR1 register *******************/
+#define ADC_SMPR1_SMP10 0x00000007U /*!<SMP10[2:0] bits (Channel 10 Sample time selection) */
+#define ADC_SMPR1_SMP10_0 0x00000001U /*!<Bit 0 */
+#define ADC_SMPR1_SMP10_1 0x00000002U /*!<Bit 1 */
+#define ADC_SMPR1_SMP10_2 0x00000004U /*!<Bit 2 */
+#define ADC_SMPR1_SMP11 0x00000038U /*!<SMP11[2:0] bits (Channel 11 Sample time selection) */
+#define ADC_SMPR1_SMP11_0 0x00000008U /*!<Bit 0 */
+#define ADC_SMPR1_SMP11_1 0x00000010U /*!<Bit 1 */
+#define ADC_SMPR1_SMP11_2 0x00000020U /*!<Bit 2 */
+#define ADC_SMPR1_SMP12 0x000001C0U /*!<SMP12[2:0] bits (Channel 12 Sample time selection) */
+#define ADC_SMPR1_SMP12_0 0x00000040U /*!<Bit 0 */
+#define ADC_SMPR1_SMP12_1 0x00000080U /*!<Bit 1 */
+#define ADC_SMPR1_SMP12_2 0x00000100U /*!<Bit 2 */
+#define ADC_SMPR1_SMP13 0x00000E00U /*!<SMP13[2:0] bits (Channel 13 Sample time selection) */
+#define ADC_SMPR1_SMP13_0 0x00000200U /*!<Bit 0 */
+#define ADC_SMPR1_SMP13_1 0x00000400U /*!<Bit 1 */
+#define ADC_SMPR1_SMP13_2 0x00000800U /*!<Bit 2 */
+#define ADC_SMPR1_SMP14 0x00007000U /*!<SMP14[2:0] bits (Channel 14 Sample time selection) */
+#define ADC_SMPR1_SMP14_0 0x00001000U /*!<Bit 0 */
+#define ADC_SMPR1_SMP14_1 0x00002000U /*!<Bit 1 */
+#define ADC_SMPR1_SMP14_2 0x00004000U /*!<Bit 2 */
+#define ADC_SMPR1_SMP15 0x00038000U /*!<SMP15[2:0] bits (Channel 15 Sample time selection) */
+#define ADC_SMPR1_SMP15_0 0x00008000U /*!<Bit 0 */
+#define ADC_SMPR1_SMP15_1 0x00010000U /*!<Bit 1 */
+#define ADC_SMPR1_SMP15_2 0x00020000U /*!<Bit 2 */
+#define ADC_SMPR1_SMP16 0x001C0000U /*!<SMP16[2:0] bits (Channel 16 Sample time selection) */
+#define ADC_SMPR1_SMP16_0 0x00040000U /*!<Bit 0 */
+#define ADC_SMPR1_SMP16_1 0x00080000U /*!<Bit 1 */
+#define ADC_SMPR1_SMP16_2 0x00100000U /*!<Bit 2 */
+#define ADC_SMPR1_SMP17 0x00E00000U /*!<SMP17[2:0] bits (Channel 17 Sample time selection) */
+#define ADC_SMPR1_SMP17_0 0x00200000U /*!<Bit 0 */
+#define ADC_SMPR1_SMP17_1 0x00400000U /*!<Bit 1 */
+#define ADC_SMPR1_SMP17_2 0x00800000U /*!<Bit 2 */
+#define ADC_SMPR1_SMP18 0x07000000U /*!<SMP18[2:0] bits (Channel 18 Sample time selection) */
+#define ADC_SMPR1_SMP18_0 0x01000000U /*!<Bit 0 */
+#define ADC_SMPR1_SMP18_1 0x02000000U /*!<Bit 1 */
+#define ADC_SMPR1_SMP18_2 0x04000000U /*!<Bit 2 */
+
+/****************** Bit definition for ADC_SMPR2 register *******************/
+#define ADC_SMPR2_SMP0 0x00000007U /*!<SMP0[2:0] bits (Channel 0 Sample time selection) */
+#define ADC_SMPR2_SMP0_0 0x00000001U /*!<Bit 0 */
+#define ADC_SMPR2_SMP0_1 0x00000002U /*!<Bit 1 */
+#define ADC_SMPR2_SMP0_2 0x00000004U /*!<Bit 2 */
+#define ADC_SMPR2_SMP1 0x00000038U /*!<SMP1[2:0] bits (Channel 1 Sample time selection) */
+#define ADC_SMPR2_SMP1_0 0x00000008U /*!<Bit 0 */
+#define ADC_SMPR2_SMP1_1 0x00000010U /*!<Bit 1 */
+#define ADC_SMPR2_SMP1_2 0x00000020U /*!<Bit 2 */
+#define ADC_SMPR2_SMP2 0x000001C0U /*!<SMP2[2:0] bits (Channel 2 Sample time selection) */
+#define ADC_SMPR2_SMP2_0 0x00000040U /*!<Bit 0 */
+#define ADC_SMPR2_SMP2_1 0x00000080U /*!<Bit 1 */
+#define ADC_SMPR2_SMP2_2 0x00000100U /*!<Bit 2 */
+#define ADC_SMPR2_SMP3 0x00000E00U /*!<SMP3[2:0] bits (Channel 3 Sample time selection) */
+#define ADC_SMPR2_SMP3_0 0x00000200U /*!<Bit 0 */
+#define ADC_SMPR2_SMP3_1 0x00000400U /*!<Bit 1 */
+#define ADC_SMPR2_SMP3_2 0x00000800U /*!<Bit 2 */
+#define ADC_SMPR2_SMP4 0x00007000U /*!<SMP4[2:0] bits (Channel 4 Sample time selection) */
+#define ADC_SMPR2_SMP4_0 0x00001000U /*!<Bit 0 */
+#define ADC_SMPR2_SMP4_1 0x00002000U /*!<Bit 1 */
+#define ADC_SMPR2_SMP4_2 0x00004000U /*!<Bit 2 */
+#define ADC_SMPR2_SMP5 0x00038000U /*!<SMP5[2:0] bits (Channel 5 Sample time selection) */
+#define ADC_SMPR2_SMP5_0 0x00008000U /*!<Bit 0 */
+#define ADC_SMPR2_SMP5_1 0x00010000U /*!<Bit 1 */
+#define ADC_SMPR2_SMP5_2 0x00020000U /*!<Bit 2 */
+#define ADC_SMPR2_SMP6 0x001C0000U /*!<SMP6[2:0] bits (Channel 6 Sample time selection) */
+#define ADC_SMPR2_SMP6_0 0x00040000U /*!<Bit 0 */
+#define ADC_SMPR2_SMP6_1 0x00080000U /*!<Bit 1 */
+#define ADC_SMPR2_SMP6_2 0x00100000U /*!<Bit 2 */
+#define ADC_SMPR2_SMP7 0x00E00000U /*!<SMP7[2:0] bits (Channel 7 Sample time selection) */
+#define ADC_SMPR2_SMP7_0 0x00200000U /*!<Bit 0 */
+#define ADC_SMPR2_SMP7_1 0x00400000U /*!<Bit 1 */
+#define ADC_SMPR2_SMP7_2 0x00800000U /*!<Bit 2 */
+#define ADC_SMPR2_SMP8 0x07000000U /*!<SMP8[2:0] bits (Channel 8 Sample time selection) */
+#define ADC_SMPR2_SMP8_0 0x01000000U /*!<Bit 0 */
+#define ADC_SMPR2_SMP8_1 0x02000000U /*!<Bit 1 */
+#define ADC_SMPR2_SMP8_2 0x04000000U /*!<Bit 2 */
+#define ADC_SMPR2_SMP9 0x38000000U /*!<SMP9[2:0] bits (Channel 9 Sample time selection) */
+#define ADC_SMPR2_SMP9_0 0x08000000U /*!<Bit 0 */
+#define ADC_SMPR2_SMP9_1 0x10000000U /*!<Bit 1 */
+#define ADC_SMPR2_SMP9_2 0x20000000U /*!<Bit 2 */
+
+/****************** Bit definition for ADC_JOFR1 register *******************/
+#define ADC_JOFR1_JOFFSET1 0x0FFFU /*!<Data offset for injected channel 1 */
+
+/****************** Bit definition for ADC_JOFR2 register *******************/
+#define ADC_JOFR2_JOFFSET2 0x0FFFU /*!<Data offset for injected channel 2 */
+
+/****************** Bit definition for ADC_JOFR3 register *******************/
+#define ADC_JOFR3_JOFFSET3 0x0FFFU /*!<Data offset for injected channel 3 */
+
+/****************** Bit definition for ADC_JOFR4 register *******************/
+#define ADC_JOFR4_JOFFSET4 0x0FFFU /*!<Data offset for injected channel 4 */
+
+/******************* Bit definition for ADC_HTR register ********************/
+#define ADC_HTR_HT 0x0FFFU /*!<Analog watchdog high threshold */
+
+/******************* Bit definition for ADC_LTR register ********************/
+#define ADC_LTR_LT 0x0FFFU /*!<Analog watchdog low threshold */
+
+/******************* Bit definition for ADC_SQR1 register *******************/
+#define ADC_SQR1_SQ13 0x0000001FU /*!<SQ13[4:0] bits (13th conversion in regular sequence) */
+#define ADC_SQR1_SQ13_0 0x00000001U /*!<Bit 0 */
+#define ADC_SQR1_SQ13_1 0x00000002U /*!<Bit 1 */
+#define ADC_SQR1_SQ13_2 0x00000004U /*!<Bit 2 */
+#define ADC_SQR1_SQ13_3 0x00000008U /*!<Bit 3 */
+#define ADC_SQR1_SQ13_4 0x00000010U /*!<Bit 4 */
+#define ADC_SQR1_SQ14 0x000003E0U /*!<SQ14[4:0] bits (14th conversion in regular sequence) */
+#define ADC_SQR1_SQ14_0 0x00000020U /*!<Bit 0 */
+#define ADC_SQR1_SQ14_1 0x00000040U /*!<Bit 1 */
+#define ADC_SQR1_SQ14_2 0x00000080U /*!<Bit 2 */
+#define ADC_SQR1_SQ14_3 0x00000100U /*!<Bit 3 */
+#define ADC_SQR1_SQ14_4 0x00000200U /*!<Bit 4 */
+#define ADC_SQR1_SQ15 0x00007C00U /*!<SQ15[4:0] bits (15th conversion in regular sequence) */
+#define ADC_SQR1_SQ15_0 0x00000400U /*!<Bit 0 */
+#define ADC_SQR1_SQ15_1 0x00000800U /*!<Bit 1 */
+#define ADC_SQR1_SQ15_2 0x00001000U /*!<Bit 2 */
+#define ADC_SQR1_SQ15_3 0x00002000U /*!<Bit 3 */
+#define ADC_SQR1_SQ15_4 0x00004000U /*!<Bit 4 */
+#define ADC_SQR1_SQ16 0x000F8000U /*!<SQ16[4:0] bits (16th conversion in regular sequence) */
+#define ADC_SQR1_SQ16_0 0x00008000U /*!<Bit 0 */
+#define ADC_SQR1_SQ16_1 0x00010000U /*!<Bit 1 */
+#define ADC_SQR1_SQ16_2 0x00020000U /*!<Bit 2 */
+#define ADC_SQR1_SQ16_3 0x00040000U /*!<Bit 3 */
+#define ADC_SQR1_SQ16_4 0x00080000U /*!<Bit 4 */
+#define ADC_SQR1_L 0x00F00000U /*!<L[3:0] bits (Regular channel sequence length) */
+#define ADC_SQR1_L_0 0x00100000U /*!<Bit 0 */
+#define ADC_SQR1_L_1 0x00200000U /*!<Bit 1 */
+#define ADC_SQR1_L_2 0x00400000U /*!<Bit 2 */
+#define ADC_SQR1_L_3 0x00800000U /*!<Bit 3 */
+
+/******************* Bit definition for ADC_SQR2 register *******************/
+#define ADC_SQR2_SQ7 0x0000001FU /*!<SQ7[4:0] bits (7th conversion in regular sequence) */
+#define ADC_SQR2_SQ7_0 0x00000001U /*!<Bit 0 */
+#define ADC_SQR2_SQ7_1 0x00000002U /*!<Bit 1 */
+#define ADC_SQR2_SQ7_2 0x00000004U /*!<Bit 2 */
+#define ADC_SQR2_SQ7_3 0x00000008U /*!<Bit 3 */
+#define ADC_SQR2_SQ7_4 0x00000010U /*!<Bit 4 */
+#define ADC_SQR2_SQ8 0x000003E0U /*!<SQ8[4:0] bits (8th conversion in regular sequence) */
+#define ADC_SQR2_SQ8_0 0x00000020U /*!<Bit 0 */
+#define ADC_SQR2_SQ8_1 0x00000040U /*!<Bit 1 */
+#define ADC_SQR2_SQ8_2 0x00000080U /*!<Bit 2 */
+#define ADC_SQR2_SQ8_3 0x00000100U /*!<Bit 3 */
+#define ADC_SQR2_SQ8_4 0x00000200U /*!<Bit 4 */
+#define ADC_SQR2_SQ9 0x00007C00U /*!<SQ9[4:0] bits (9th conversion in regular sequence) */
+#define ADC_SQR2_SQ9_0 0x00000400U /*!<Bit 0 */
+#define ADC_SQR2_SQ9_1 0x00000800U /*!<Bit 1 */
+#define ADC_SQR2_SQ9_2 0x00001000U /*!<Bit 2 */
+#define ADC_SQR2_SQ9_3 0x00002000U /*!<Bit 3 */
+#define ADC_SQR2_SQ9_4 0x00004000U /*!<Bit 4 */
+#define ADC_SQR2_SQ10 0x000F8000U /*!<SQ10[4:0] bits (10th conversion in regular sequence) */
+#define ADC_SQR2_SQ10_0 0x00008000U /*!<Bit 0 */
+#define ADC_SQR2_SQ10_1 0x00010000U /*!<Bit 1 */
+#define ADC_SQR2_SQ10_2 0x00020000U /*!<Bit 2 */
+#define ADC_SQR2_SQ10_3 0x00040000U /*!<Bit 3 */
+#define ADC_SQR2_SQ10_4 0x00080000U /*!<Bit 4 */
+#define ADC_SQR2_SQ11 0x01F00000U /*!<SQ11[4:0] bits (11th conversion in regular sequence) */
+#define ADC_SQR2_SQ11_0 0x00100000U /*!<Bit 0 */
+#define ADC_SQR2_SQ11_1 0x00200000U /*!<Bit 1 */
+#define ADC_SQR2_SQ11_2 0x00400000U /*!<Bit 2 */
+#define ADC_SQR2_SQ11_3 0x00800000U /*!<Bit 3 */
+#define ADC_SQR2_SQ11_4 0x01000000U /*!<Bit 4 */
+#define ADC_SQR2_SQ12 0x3E000000U /*!<SQ12[4:0] bits (12th conversion in regular sequence) */
+#define ADC_SQR2_SQ12_0 0x02000000U /*!<Bit 0 */
+#define ADC_SQR2_SQ12_1 0x04000000U /*!<Bit 1 */
+#define ADC_SQR2_SQ12_2 0x08000000U /*!<Bit 2 */
+#define ADC_SQR2_SQ12_3 0x10000000U /*!<Bit 3 */
+#define ADC_SQR2_SQ12_4 0x20000000U /*!<Bit 4 */
+
+/******************* Bit definition for ADC_SQR3 register *******************/
+#define ADC_SQR3_SQ1 0x0000001FU /*!<SQ1[4:0] bits (1st conversion in regular sequence) */
+#define ADC_SQR3_SQ1_0 0x00000001U /*!<Bit 0 */
+#define ADC_SQR3_SQ1_1 0x00000002U /*!<Bit 1 */
+#define ADC_SQR3_SQ1_2 0x00000004U /*!<Bit 2 */
+#define ADC_SQR3_SQ1_3 0x00000008U /*!<Bit 3 */
+#define ADC_SQR3_SQ1_4 0x00000010U /*!<Bit 4 */
+#define ADC_SQR3_SQ2 0x000003E0U /*!<SQ2[4:0] bits (2nd conversion in regular sequence) */
+#define ADC_SQR3_SQ2_0 0x00000020U /*!<Bit 0 */
+#define ADC_SQR3_SQ2_1 0x00000040U /*!<Bit 1 */
+#define ADC_SQR3_SQ2_2 0x00000080U /*!<Bit 2 */
+#define ADC_SQR3_SQ2_3 0x00000100U /*!<Bit 3 */
+#define ADC_SQR3_SQ2_4 0x00000200U /*!<Bit 4 */
+#define ADC_SQR3_SQ3 0x00007C00U /*!<SQ3[4:0] bits (3rd conversion in regular sequence) */
+#define ADC_SQR3_SQ3_0 0x00000400U /*!<Bit 0 */
+#define ADC_SQR3_SQ3_1 0x00000800U /*!<Bit 1 */
+#define ADC_SQR3_SQ3_2 0x00001000U /*!<Bit 2 */
+#define ADC_SQR3_SQ3_3 0x00002000U /*!<Bit 3 */
+#define ADC_SQR3_SQ3_4 0x00004000U /*!<Bit 4 */
+#define ADC_SQR3_SQ4 0x000F8000U /*!<SQ4[4:0] bits (4th conversion in regular sequence) */
+#define ADC_SQR3_SQ4_0 0x00008000U /*!<Bit 0 */
+#define ADC_SQR3_SQ4_1 0x00010000U /*!<Bit 1 */
+#define ADC_SQR3_SQ4_2 0x00020000U /*!<Bit 2 */
+#define ADC_SQR3_SQ4_3 0x00040000U /*!<Bit 3 */
+#define ADC_SQR3_SQ4_4 0x00080000U /*!<Bit 4 */
+#define ADC_SQR3_SQ5 0x01F00000U /*!<SQ5[4:0] bits (5th conversion in regular sequence) */
+#define ADC_SQR3_SQ5_0 0x00100000U /*!<Bit 0 */
+#define ADC_SQR3_SQ5_1 0x00200000U /*!<Bit 1 */
+#define ADC_SQR3_SQ5_2 0x00400000U /*!<Bit 2 */
+#define ADC_SQR3_SQ5_3 0x00800000U /*!<Bit 3 */
+#define ADC_SQR3_SQ5_4 0x01000000U /*!<Bit 4 */
+#define ADC_SQR3_SQ6 0x3E000000U /*!<SQ6[4:0] bits (6th conversion in regular sequence) */
+#define ADC_SQR3_SQ6_0 0x02000000U /*!<Bit 0 */
+#define ADC_SQR3_SQ6_1 0x04000000U /*!<Bit 1 */
+#define ADC_SQR3_SQ6_2 0x08000000U /*!<Bit 2 */
+#define ADC_SQR3_SQ6_3 0x10000000U /*!<Bit 3 */
+#define ADC_SQR3_SQ6_4 0x20000000U /*!<Bit 4 */
+
+/******************* Bit definition for ADC_JSQR register *******************/
+#define ADC_JSQR_JSQ1 0x0000001FU /*!<JSQ1[4:0] bits (1st conversion in injected sequence) */
+#define ADC_JSQR_JSQ1_0 0x00000001U /*!<Bit 0 */
+#define ADC_JSQR_JSQ1_1 0x00000002U /*!<Bit 1 */
+#define ADC_JSQR_JSQ1_2 0x00000004U /*!<Bit 2 */
+#define ADC_JSQR_JSQ1_3 0x00000008U /*!<Bit 3 */
+#define ADC_JSQR_JSQ1_4 0x00000010U /*!<Bit 4 */
+#define ADC_JSQR_JSQ2 0x000003E0U /*!<JSQ2[4:0] bits (2nd conversion in injected sequence) */
+#define ADC_JSQR_JSQ2_0 0x00000020U /*!<Bit 0 */
+#define ADC_JSQR_JSQ2_1 0x00000040U /*!<Bit 1 */
+#define ADC_JSQR_JSQ2_2 0x00000080U /*!<Bit 2 */
+#define ADC_JSQR_JSQ2_3 0x00000100U /*!<Bit 3 */
+#define ADC_JSQR_JSQ2_4 0x00000200U /*!<Bit 4 */
+#define ADC_JSQR_JSQ3 0x00007C00U /*!<JSQ3[4:0] bits (3rd conversion in injected sequence) */
+#define ADC_JSQR_JSQ3_0 0x00000400U /*!<Bit 0 */
+#define ADC_JSQR_JSQ3_1 0x00000800U /*!<Bit 1 */
+#define ADC_JSQR_JSQ3_2 0x00001000U /*!<Bit 2 */
+#define ADC_JSQR_JSQ3_3 0x00002000U /*!<Bit 3 */
+#define ADC_JSQR_JSQ3_4 0x00004000U /*!<Bit 4 */
+#define ADC_JSQR_JSQ4 0x000F8000U /*!<JSQ4[4:0] bits (4th conversion in injected sequence) */
+#define ADC_JSQR_JSQ4_0 0x00008000U /*!<Bit 0 */
+#define ADC_JSQR_JSQ4_1 0x00010000U /*!<Bit 1 */
+#define ADC_JSQR_JSQ4_2 0x00020000U /*!<Bit 2 */
+#define ADC_JSQR_JSQ4_3 0x00040000U /*!<Bit 3 */
+#define ADC_JSQR_JSQ4_4 0x00080000U /*!<Bit 4 */
+#define ADC_JSQR_JL 0x00300000U /*!<JL[1:0] bits (Injected Sequence length) */
+#define ADC_JSQR_JL_0 0x00100000U /*!<Bit 0 */
+#define ADC_JSQR_JL_1 0x00200000U /*!<Bit 1 */
+
+/******************* Bit definition for ADC_JDR1 register *******************/
+#define ADC_JDR1_JDATA 0xFFFFU /*!<Injected data */
+
+/******************* Bit definition for ADC_JDR2 register *******************/
+#define ADC_JDR2_JDATA 0xFFFFU /*!<Injected data */
+
+/******************* Bit definition for ADC_JDR3 register *******************/
+#define ADC_JDR3_JDATA 0xFFFFU /*!<Injected data */
+
+/******************* Bit definition for ADC_JDR4 register *******************/
+#define ADC_JDR4_JDATA 0xFFFFU /*!<Injected data */
+
+/******************** Bit definition for ADC_DR register ********************/
+#define ADC_DR_DATA 0x0000FFFFU /*!<Regular data */
+#define ADC_DR_ADC2DATA 0xFFFF0000U /*!<ADC2 data */
+
+/******************* Bit definition for ADC_CSR register ********************/
+#define ADC_CSR_AWD1 0x00000001U /*!<ADC1 Analog watchdog flag */
+#define ADC_CSR_EOC1 0x00000002U /*!<ADC1 End of conversion */
+#define ADC_CSR_JEOC1 0x00000004U /*!<ADC1 Injected channel end of conversion */
+#define ADC_CSR_JSTRT1 0x00000008U /*!<ADC1 Injected channel Start flag */
+#define ADC_CSR_STRT1 0x00000010U /*!<ADC1 Regular channel Start flag */
+#define ADC_CSR_OVR1 0x00000020U /*!<ADC1 DMA overrun flag */
+#define ADC_CSR_AWD2 0x00000100U /*!<ADC2 Analog watchdog flag */
+#define ADC_CSR_EOC2 0x00000200U /*!<ADC2 End of conversion */
+#define ADC_CSR_JEOC2 0x00000400U /*!<ADC2 Injected channel end of conversion */
+#define ADC_CSR_JSTRT2 0x00000800U /*!<ADC2 Injected channel Start flag */
+#define ADC_CSR_STRT2 0x00001000U /*!<ADC2 Regular channel Start flag */
+#define ADC_CSR_OVR2 0x00002000U /*!<ADC2 DMA overrun flag */
+#define ADC_CSR_AWD3 0x00010000U /*!<ADC3 Analog watchdog flag */
+#define ADC_CSR_EOC3 0x00020000U /*!<ADC3 End of conversion */
+#define ADC_CSR_JEOC3 0x00040000U /*!<ADC3 Injected channel end of conversion */
+#define ADC_CSR_JSTRT3 0x00080000U /*!<ADC3 Injected channel Start flag */
+#define ADC_CSR_STRT3 0x00100000U /*!<ADC3 Regular channel Start flag */
+#define ADC_CSR_OVR3 0x00200000U /*!<ADC3 DMA overrun flag */
+
+/* Legacy defines */
+#define ADC_CSR_DOVR1 ADC_CSR_OVR1
+#define ADC_CSR_DOVR2 ADC_CSR_OVR2
+#define ADC_CSR_DOVR3 ADC_CSR_OVR3
+
+/******************* Bit definition for ADC_CCR register ********************/
+#define ADC_CCR_MULTI 0x0000001FU /*!<MULTI[4:0] bits (Multi-ADC mode selection) */
+#define ADC_CCR_MULTI_0 0x00000001U /*!<Bit 0 */
+#define ADC_CCR_MULTI_1 0x00000002U /*!<Bit 1 */
+#define ADC_CCR_MULTI_2 0x00000004U /*!<Bit 2 */
+#define ADC_CCR_MULTI_3 0x00000008U /*!<Bit 3 */
+#define ADC_CCR_MULTI_4 0x00000010U /*!<Bit 4 */
+#define ADC_CCR_DELAY 0x00000F00U /*!<DELAY[3:0] bits (Delay between 2 sampling phases) */
+#define ADC_CCR_DELAY_0 0x00000100U /*!<Bit 0 */
+#define ADC_CCR_DELAY_1 0x00000200U /*!<Bit 1 */
+#define ADC_CCR_DELAY_2 0x00000400U /*!<Bit 2 */
+#define ADC_CCR_DELAY_3 0x00000800U /*!<Bit 3 */
+#define ADC_CCR_DDS 0x00002000U /*!<DMA disable selection (Multi-ADC mode) */
+#define ADC_CCR_DMA 0x0000C000U /*!<DMA[1:0] bits (Direct Memory Access mode for multimode) */
+#define ADC_CCR_DMA_0 0x00004000U /*!<Bit 0 */
+#define ADC_CCR_DMA_1 0x00008000U /*!<Bit 1 */
+#define ADC_CCR_ADCPRE 0x00030000U /*!<ADCPRE[1:0] bits (ADC prescaler) */
+#define ADC_CCR_ADCPRE_0 0x00010000U /*!<Bit 0 */
+#define ADC_CCR_ADCPRE_1 0x00020000U /*!<Bit 1 */
+#define ADC_CCR_VBATE 0x00400000U /*!<VBAT Enable */
+#define ADC_CCR_TSVREFE 0x00800000U /*!<Temperature Sensor and VREFINT Enable */
+
+/******************* Bit definition for ADC_CDR register ********************/
+#define ADC_CDR_DATA1 0x0000FFFFU /*!<1st data of a pair of regular conversions */
+#define ADC_CDR_DATA2 0xFFFF0000U /*!<2nd data of a pair of regular conversions */
+
+/******************************************************************************/
+/* */
+/* CRC calculation unit */
+/* */
+/******************************************************************************/
+/******************* Bit definition for CRC_DR register *********************/
+#define CRC_DR_DR 0xFFFFFFFFU /*!< Data register bits */
+
+
+/******************* Bit definition for CRC_IDR register ********************/
+#define CRC_IDR_IDR 0xFFU /*!< General-purpose 8-bit data register bits */
+
+
+/******************** Bit definition for CRC_CR register ********************/
+#define CRC_CR_RESET 0x01U /*!< RESET bit */
+
+/******************************************************************************/
+/* */
+/* Debug MCU */
+/* */
+/******************************************************************************/
+
+/******************************************************************************/
+/* */
+/* DMA Controller */
+/* */
+/******************************************************************************/
+/******************** Bits definition for DMA_SxCR register *****************/
+#define DMA_SxCR_CHSEL 0x0E000000U
+#define DMA_SxCR_CHSEL_0 0x02000000U
+#define DMA_SxCR_CHSEL_1 0x04000000U
+#define DMA_SxCR_CHSEL_2 0x08000000U
+#define DMA_SxCR_MBURST 0x01800000U
+#define DMA_SxCR_MBURST_0 0x00800000U
+#define DMA_SxCR_MBURST_1 0x01000000U
+#define DMA_SxCR_PBURST 0x00600000U
+#define DMA_SxCR_PBURST_0 0x00200000U
+#define DMA_SxCR_PBURST_1 0x00400000U
+#define DMA_SxCR_CT 0x00080000U
+#define DMA_SxCR_DBM 0x00040000U
+#define DMA_SxCR_PL 0x00030000U
+#define DMA_SxCR_PL_0 0x00010000U
+#define DMA_SxCR_PL_1 0x00020000U
+#define DMA_SxCR_PINCOS 0x00008000U
+#define DMA_SxCR_MSIZE 0x00006000U
+#define DMA_SxCR_MSIZE_0 0x00002000U
+#define DMA_SxCR_MSIZE_1 0x00004000U
+#define DMA_SxCR_PSIZE 0x00001800U
+#define DMA_SxCR_PSIZE_0 0x00000800U
+#define DMA_SxCR_PSIZE_1 0x00001000U
+#define DMA_SxCR_MINC 0x00000400U
+#define DMA_SxCR_PINC 0x00000200U
+#define DMA_SxCR_CIRC 0x00000100U
+#define DMA_SxCR_DIR 0x000000C0U
+#define DMA_SxCR_DIR_0 0x00000040U
+#define DMA_SxCR_DIR_1 0x00000080U
+#define DMA_SxCR_PFCTRL 0x00000020U
+#define DMA_SxCR_TCIE 0x00000010U
+#define DMA_SxCR_HTIE 0x00000008U
+#define DMA_SxCR_TEIE 0x00000004U
+#define DMA_SxCR_DMEIE 0x00000002U
+#define DMA_SxCR_EN 0x00000001U
+
+/* Legacy defines */
+#define DMA_SxCR_ACK 0x00100000U
+
+/******************** Bits definition for DMA_SxCNDTR register **************/
+#define DMA_SxNDT 0x0000FFFFU
+#define DMA_SxNDT_0 0x00000001U
+#define DMA_SxNDT_1 0x00000002U
+#define DMA_SxNDT_2 0x00000004U
+#define DMA_SxNDT_3 0x00000008U
+#define DMA_SxNDT_4 0x00000010U
+#define DMA_SxNDT_5 0x00000020U
+#define DMA_SxNDT_6 0x00000040U
+#define DMA_SxNDT_7 0x00000080U
+#define DMA_SxNDT_8 0x00000100U
+#define DMA_SxNDT_9 0x00000200U
+#define DMA_SxNDT_10 0x00000400U
+#define DMA_SxNDT_11 0x00000800U
+#define DMA_SxNDT_12 0x00001000U
+#define DMA_SxNDT_13 0x00002000U
+#define DMA_SxNDT_14 0x00004000U
+#define DMA_SxNDT_15 0x00008000U
+
+/******************** Bits definition for DMA_SxFCR register ****************/
+#define DMA_SxFCR_FEIE 0x00000080U
+#define DMA_SxFCR_FS 0x00000038U
+#define DMA_SxFCR_FS_0 0x00000008U
+#define DMA_SxFCR_FS_1 0x00000010U
+#define DMA_SxFCR_FS_2 0x00000020U
+#define DMA_SxFCR_DMDIS 0x00000004U
+#define DMA_SxFCR_FTH 0x00000003U
+#define DMA_SxFCR_FTH_0 0x00000001U
+#define DMA_SxFCR_FTH_1 0x00000002U
+
+/******************** Bits definition for DMA_LISR register *****************/
+#define DMA_LISR_TCIF3 0x08000000U
+#define DMA_LISR_HTIF3 0x04000000U
+#define DMA_LISR_TEIF3 0x02000000U
+#define DMA_LISR_DMEIF3 0x01000000U
+#define DMA_LISR_FEIF3 0x00400000U
+#define DMA_LISR_TCIF2 0x00200000U
+#define DMA_LISR_HTIF2 0x00100000U
+#define DMA_LISR_TEIF2 0x00080000U
+#define DMA_LISR_DMEIF2 0x00040000U
+#define DMA_LISR_FEIF2 0x00010000U
+#define DMA_LISR_TCIF1 0x00000800U
+#define DMA_LISR_HTIF1 0x00000400U
+#define DMA_LISR_TEIF1 0x00000200U
+#define DMA_LISR_DMEIF1 0x00000100U
+#define DMA_LISR_FEIF1 0x00000040U
+#define DMA_LISR_TCIF0 0x00000020U
+#define DMA_LISR_HTIF0 0x00000010U
+#define DMA_LISR_TEIF0 0x00000008U
+#define DMA_LISR_DMEIF0 0x00000004U
+#define DMA_LISR_FEIF0 0x00000001U
+
+/******************** Bits definition for DMA_HISR register *****************/
+#define DMA_HISR_TCIF7 0x08000000U
+#define DMA_HISR_HTIF7 0x04000000U
+#define DMA_HISR_TEIF7 0x02000000U
+#define DMA_HISR_DMEIF7 0x01000000U
+#define DMA_HISR_FEIF7 0x00400000U
+#define DMA_HISR_TCIF6 0x00200000U
+#define DMA_HISR_HTIF6 0x00100000U
+#define DMA_HISR_TEIF6 0x00080000U
+#define DMA_HISR_DMEIF6 0x00040000U
+#define DMA_HISR_FEIF6 0x00010000U
+#define DMA_HISR_TCIF5 0x00000800U
+#define DMA_HISR_HTIF5 0x00000400U
+#define DMA_HISR_TEIF5 0x00000200U
+#define DMA_HISR_DMEIF5 0x00000100U
+#define DMA_HISR_FEIF5 0x00000040U
+#define DMA_HISR_TCIF4 0x00000020U
+#define DMA_HISR_HTIF4 0x00000010U
+#define DMA_HISR_TEIF4 0x00000008U
+#define DMA_HISR_DMEIF4 0x00000004U
+#define DMA_HISR_FEIF4 0x00000001U
+
+/******************** Bits definition for DMA_LIFCR register ****************/
+#define DMA_LIFCR_CTCIF3 0x08000000U
+#define DMA_LIFCR_CHTIF3 0x04000000U
+#define DMA_LIFCR_CTEIF3 0x02000000U
+#define DMA_LIFCR_CDMEIF3 0x01000000U
+#define DMA_LIFCR_CFEIF3 0x00400000U
+#define DMA_LIFCR_CTCIF2 0x00200000U
+#define DMA_LIFCR_CHTIF2 0x00100000U
+#define DMA_LIFCR_CTEIF2 0x00080000U
+#define DMA_LIFCR_CDMEIF2 0x00040000U
+#define DMA_LIFCR_CFEIF2 0x00010000U
+#define DMA_LIFCR_CTCIF1 0x00000800U
+#define DMA_LIFCR_CHTIF1 0x00000400U
+#define DMA_LIFCR_CTEIF1 0x00000200U
+#define DMA_LIFCR_CDMEIF1 0x00000100U
+#define DMA_LIFCR_CFEIF1 0x00000040U
+#define DMA_LIFCR_CTCIF0 0x00000020U
+#define DMA_LIFCR_CHTIF0 0x00000010U
+#define DMA_LIFCR_CTEIF0 0x00000008U
+#define DMA_LIFCR_CDMEIF0 0x00000004U
+#define DMA_LIFCR_CFEIF0 0x00000001U
+
+/******************** Bits definition for DMA_HIFCR register ****************/
+#define DMA_HIFCR_CTCIF7 0x08000000U
+#define DMA_HIFCR_CHTIF7 0x04000000U
+#define DMA_HIFCR_CTEIF7 0x02000000U
+#define DMA_HIFCR_CDMEIF7 0x01000000U
+#define DMA_HIFCR_CFEIF7 0x00400000U
+#define DMA_HIFCR_CTCIF6 0x00200000U
+#define DMA_HIFCR_CHTIF6 0x00100000U
+#define DMA_HIFCR_CTEIF6 0x00080000U
+#define DMA_HIFCR_CDMEIF6 0x00040000U
+#define DMA_HIFCR_CFEIF6 0x00010000U
+#define DMA_HIFCR_CTCIF5 0x00000800U
+#define DMA_HIFCR_CHTIF5 0x00000400U
+#define DMA_HIFCR_CTEIF5 0x00000200U
+#define DMA_HIFCR_CDMEIF5 0x00000100U
+#define DMA_HIFCR_CFEIF5 0x00000040U
+#define DMA_HIFCR_CTCIF4 0x00000020U
+#define DMA_HIFCR_CHTIF4 0x00000010U
+#define DMA_HIFCR_CTEIF4 0x00000008U
+#define DMA_HIFCR_CDMEIF4 0x00000004U
+#define DMA_HIFCR_CFEIF4 0x00000001U
+
+
+/******************************************************************************/
+/* */
+/* External Interrupt/Event Controller */
+/* */
+/******************************************************************************/
+/******************* Bit definition for EXTI_IMR register *******************/
+#define EXTI_IMR_MR0 0x00000001U /*!< Interrupt Mask on line 0 */
+#define EXTI_IMR_MR1 0x00000002U /*!< Interrupt Mask on line 1 */
+#define EXTI_IMR_MR2 0x00000004U /*!< Interrupt Mask on line 2 */
+#define EXTI_IMR_MR3 0x00000008U /*!< Interrupt Mask on line 3 */
+#define EXTI_IMR_MR4 0x00000010U /*!< Interrupt Mask on line 4 */
+#define EXTI_IMR_MR5 0x00000020U /*!< Interrupt Mask on line 5 */
+#define EXTI_IMR_MR6 0x00000040U /*!< Interrupt Mask on line 6 */
+#define EXTI_IMR_MR7 0x00000080U /*!< Interrupt Mask on line 7 */
+#define EXTI_IMR_MR8 0x00000100U /*!< Interrupt Mask on line 8 */
+#define EXTI_IMR_MR9 0x00000200U /*!< Interrupt Mask on line 9 */
+#define EXTI_IMR_MR10 0x00000400U /*!< Interrupt Mask on line 10 */
+#define EXTI_IMR_MR11 0x00000800U /*!< Interrupt Mask on line 11 */
+#define EXTI_IMR_MR12 0x00001000U /*!< Interrupt Mask on line 12 */
+#define EXTI_IMR_MR13 0x00002000U /*!< Interrupt Mask on line 13 */
+#define EXTI_IMR_MR14 0x00004000U /*!< Interrupt Mask on line 14 */
+#define EXTI_IMR_MR15 0x00008000U /*!< Interrupt Mask on line 15 */
+#define EXTI_IMR_MR16 0x00010000U /*!< Interrupt Mask on line 16 */
+#define EXTI_IMR_MR17 0x00020000U /*!< Interrupt Mask on line 17 */
+#define EXTI_IMR_MR18 0x00040000U /*!< Interrupt Mask on line 18 */
+#define EXTI_IMR_MR19 0x00080000U /*!< Interrupt Mask on line 19 */
+#define EXTI_IMR_MR20 0x00100000U /*!< Interrupt Mask on line 20 */
+#define EXTI_IMR_MR21 0x00200000U /*!< Interrupt Mask on line 21 */
+#define EXTI_IMR_MR22 0x00400000U /*!< Interrupt Mask on line 22 */
+#define EXTI_IMR_MR23 0x00800000U /*!< Interrupt Mask on line 23 */
+
+/******************* Bit definition for EXTI_EMR register *******************/
+#define EXTI_EMR_MR0 0x00000001U /*!< Event Mask on line 0 */
+#define EXTI_EMR_MR1 0x00000002U /*!< Event Mask on line 1 */
+#define EXTI_EMR_MR2 0x00000004U /*!< Event Mask on line 2 */
+#define EXTI_EMR_MR3 0x00000008U /*!< Event Mask on line 3 */
+#define EXTI_EMR_MR4 0x00000010U /*!< Event Mask on line 4 */
+#define EXTI_EMR_MR5 0x00000020U /*!< Event Mask on line 5 */
+#define EXTI_EMR_MR6 0x00000040U /*!< Event Mask on line 6 */
+#define EXTI_EMR_MR7 0x00000080U /*!< Event Mask on line 7 */
+#define EXTI_EMR_MR8 0x00000100U /*!< Event Mask on line 8 */
+#define EXTI_EMR_MR9 0x00000200U /*!< Event Mask on line 9 */
+#define EXTI_EMR_MR10 0x00000400U /*!< Event Mask on line 10 */
+#define EXTI_EMR_MR11 0x00000800U /*!< Event Mask on line 11 */
+#define EXTI_EMR_MR12 0x00001000U /*!< Event Mask on line 12 */
+#define EXTI_EMR_MR13 0x00002000U /*!< Event Mask on line 13 */
+#define EXTI_EMR_MR14 0x00004000U /*!< Event Mask on line 14 */
+#define EXTI_EMR_MR15 0x00008000U /*!< Event Mask on line 15 */
+#define EXTI_EMR_MR16 0x00010000U /*!< Event Mask on line 16 */
+#define EXTI_EMR_MR17 0x00020000U /*!< Event Mask on line 17 */
+#define EXTI_EMR_MR18 0x00040000U /*!< Event Mask on line 18 */
+#define EXTI_EMR_MR19 0x00080000U /*!< Event Mask on line 19 */
+#define EXTI_EMR_MR20 0x00100000U /*!< Event Mask on line 20 */
+#define EXTI_EMR_MR21 0x00200000U /*!< Event Mask on line 21 */
+#define EXTI_EMR_MR22 0x00400000U /*!< Event Mask on line 22 */
+#define EXTI_EMR_MR23 0x00800000U /*!< Event Mask on line 23 */
+
+/****************** Bit definition for EXTI_RTSR register *******************/
+#define EXTI_RTSR_TR0 0x00000001U /*!< Rising trigger event configuration bit of line 0 */
+#define EXTI_RTSR_TR1 0x00000002U /*!< Rising trigger event configuration bit of line 1 */
+#define EXTI_RTSR_TR2 0x00000004U /*!< Rising trigger event configuration bit of line 2 */
+#define EXTI_RTSR_TR3 0x00000008U /*!< Rising trigger event configuration bit of line 3 */
+#define EXTI_RTSR_TR4 0x00000010U /*!< Rising trigger event configuration bit of line 4 */
+#define EXTI_RTSR_TR5 0x00000020U /*!< Rising trigger event configuration bit of line 5 */
+#define EXTI_RTSR_TR6 0x00000040U /*!< Rising trigger event configuration bit of line 6 */
+#define EXTI_RTSR_TR7 0x00000080U /*!< Rising trigger event configuration bit of line 7 */
+#define EXTI_RTSR_TR8 0x00000100U /*!< Rising trigger event configuration bit of line 8 */
+#define EXTI_RTSR_TR9 0x00000200U /*!< Rising trigger event configuration bit of line 9 */
+#define EXTI_RTSR_TR10 0x00000400U /*!< Rising trigger event configuration bit of line 10 */
+#define EXTI_RTSR_TR11 0x00000800U /*!< Rising trigger event configuration bit of line 11 */
+#define EXTI_RTSR_TR12 0x00001000U /*!< Rising trigger event configuration bit of line 12 */
+#define EXTI_RTSR_TR13 0x00002000U /*!< Rising trigger event configuration bit of line 13 */
+#define EXTI_RTSR_TR14 0x00004000U /*!< Rising trigger event configuration bit of line 14 */
+#define EXTI_RTSR_TR15 0x00008000U /*!< Rising trigger event configuration bit of line 15 */
+#define EXTI_RTSR_TR16 0x00010000U /*!< Rising trigger event configuration bit of line 16 */
+#define EXTI_RTSR_TR17 0x00020000U /*!< Rising trigger event configuration bit of line 17 */
+#define EXTI_RTSR_TR18 0x00040000U /*!< Rising trigger event configuration bit of line 18 */
+#define EXTI_RTSR_TR19 0x00080000U /*!< Rising trigger event configuration bit of line 19 */
+#define EXTI_RTSR_TR20 0x00100000U /*!< Rising trigger event configuration bit of line 20 */
+#define EXTI_RTSR_TR21 0x00200000U /*!< Rising trigger event configuration bit of line 21 */
+#define EXTI_RTSR_TR22 0x00400000U /*!< Rising trigger event configuration bit of line 22 */
+#define EXTI_RTSR_TR23 0x00800000U /*!< Rising trigger event configuration bit of line 23 */
+
+/****************** Bit definition for EXTI_FTSR register *******************/
+#define EXTI_FTSR_TR0 0x00000001U /*!< Falling trigger event configuration bit of line 0 */
+#define EXTI_FTSR_TR1 0x00000002U /*!< Falling trigger event configuration bit of line 1 */
+#define EXTI_FTSR_TR2 0x00000004U /*!< Falling trigger event configuration bit of line 2 */
+#define EXTI_FTSR_TR3 0x00000008U /*!< Falling trigger event configuration bit of line 3 */
+#define EXTI_FTSR_TR4 0x00000010U /*!< Falling trigger event configuration bit of line 4 */
+#define EXTI_FTSR_TR5 0x00000020U /*!< Falling trigger event configuration bit of line 5 */
+#define EXTI_FTSR_TR6 0x00000040U /*!< Falling trigger event configuration bit of line 6 */
+#define EXTI_FTSR_TR7 0x00000080U /*!< Falling trigger event configuration bit of line 7 */
+#define EXTI_FTSR_TR8 0x00000100U /*!< Falling trigger event configuration bit of line 8 */
+#define EXTI_FTSR_TR9 0x00000200U /*!< Falling trigger event configuration bit of line 9 */
+#define EXTI_FTSR_TR10 0x00000400U /*!< Falling trigger event configuration bit of line 10 */
+#define EXTI_FTSR_TR11 0x00000800U /*!< Falling trigger event configuration bit of line 11 */
+#define EXTI_FTSR_TR12 0x00001000U /*!< Falling trigger event configuration bit of line 12 */
+#define EXTI_FTSR_TR13 0x00002000U /*!< Falling trigger event configuration bit of line 13 */
+#define EXTI_FTSR_TR14 0x00004000U /*!< Falling trigger event configuration bit of line 14 */
+#define EXTI_FTSR_TR15 0x00008000U /*!< Falling trigger event configuration bit of line 15 */
+#define EXTI_FTSR_TR16 0x00010000U /*!< Falling trigger event configuration bit of line 16 */
+#define EXTI_FTSR_TR17 0x00020000U /*!< Falling trigger event configuration bit of line 17 */
+#define EXTI_FTSR_TR18 0x00040000U /*!< Falling trigger event configuration bit of line 18 */
+#define EXTI_FTSR_TR19 0x00080000U /*!< Falling trigger event configuration bit of line 19 */
+#define EXTI_FTSR_TR20 0x00100000U /*!< Falling trigger event configuration bit of line 20 */
+#define EXTI_FTSR_TR21 0x00200000U /*!< Falling trigger event configuration bit of line 21 */
+#define EXTI_FTSR_TR22 0x00400000U /*!< Falling trigger event configuration bit of line 22 */
+#define EXTI_FTSR_TR23 0x00800000U /*!< Falling trigger event configuration bit of line 23 */
+
+/****************** Bit definition for EXTI_SWIER register ******************/
+#define EXTI_SWIER_SWIER0 0x00000001U /*!< Software Interrupt on line 0 */
+#define EXTI_SWIER_SWIER1 0x00000002U /*!< Software Interrupt on line 1 */
+#define EXTI_SWIER_SWIER2 0x00000004U /*!< Software Interrupt on line 2 */
+#define EXTI_SWIER_SWIER3 0x00000008U /*!< Software Interrupt on line 3 */
+#define EXTI_SWIER_SWIER4 0x00000010U /*!< Software Interrupt on line 4 */
+#define EXTI_SWIER_SWIER5 0x00000020U /*!< Software Interrupt on line 5 */
+#define EXTI_SWIER_SWIER6 0x00000040U /*!< Software Interrupt on line 6 */
+#define EXTI_SWIER_SWIER7 0x00000080U /*!< Software Interrupt on line 7 */
+#define EXTI_SWIER_SWIER8 0x00000100U /*!< Software Interrupt on line 8 */
+#define EXTI_SWIER_SWIER9 0x00000200U /*!< Software Interrupt on line 9 */
+#define EXTI_SWIER_SWIER10 0x00000400U /*!< Software Interrupt on line 10 */
+#define EXTI_SWIER_SWIER11 0x00000800U /*!< Software Interrupt on line 11 */
+#define EXTI_SWIER_SWIER12 0x00001000U /*!< Software Interrupt on line 12 */
+#define EXTI_SWIER_SWIER13 0x00002000U /*!< Software Interrupt on line 13 */
+#define EXTI_SWIER_SWIER14 0x00004000U /*!< Software Interrupt on line 14 */
+#define EXTI_SWIER_SWIER15 0x00008000U /*!< Software Interrupt on line 15 */
+#define EXTI_SWIER_SWIER16 0x00010000U /*!< Software Interrupt on line 16 */
+#define EXTI_SWIER_SWIER17 0x00020000U /*!< Software Interrupt on line 17 */
+#define EXTI_SWIER_SWIER18 0x00040000U /*!< Software Interrupt on line 18 */
+#define EXTI_SWIER_SWIER19 0x00080000U /*!< Software Interrupt on line 19 */
+#define EXTI_SWIER_SWIER20 0x00100000U /*!< Software Interrupt on line 20 */
+#define EXTI_SWIER_SWIER21 0x00200000U /*!< Software Interrupt on line 21 */
+#define EXTI_SWIER_SWIER22 0x00400000U /*!< Software Interrupt on line 22 */
+#define EXTI_SWIER_SWIER23 0x00800000U /*!< Software Interrupt on line 23 */
+
+/******************* Bit definition for EXTI_PR register ********************/
+#define EXTI_PR_PR0 0x00000001U /*!< Pending bit for line 0 */
+#define EXTI_PR_PR1 0x00000002U /*!< Pending bit for line 1 */
+#define EXTI_PR_PR2 0x00000004U /*!< Pending bit for line 2 */
+#define EXTI_PR_PR3 0x00000008U /*!< Pending bit for line 3 */
+#define EXTI_PR_PR4 0x00000010U /*!< Pending bit for line 4 */
+#define EXTI_PR_PR5 0x00000020U /*!< Pending bit for line 5 */
+#define EXTI_PR_PR6 0x00000040U /*!< Pending bit for line 6 */
+#define EXTI_PR_PR7 0x00000080U /*!< Pending bit for line 7 */
+#define EXTI_PR_PR8 0x00000100U /*!< Pending bit for line 8 */
+#define EXTI_PR_PR9 0x00000200U /*!< Pending bit for line 9 */
+#define EXTI_PR_PR10 0x00000400U /*!< Pending bit for line 10 */
+#define EXTI_PR_PR11 0x00000800U /*!< Pending bit for line 11 */
+#define EXTI_PR_PR12 0x00001000U /*!< Pending bit for line 12 */
+#define EXTI_PR_PR13 0x00002000U /*!< Pending bit for line 13 */
+#define EXTI_PR_PR14 0x00004000U /*!< Pending bit for line 14 */
+#define EXTI_PR_PR15 0x00008000U /*!< Pending bit for line 15 */
+#define EXTI_PR_PR16 0x00010000U /*!< Pending bit for line 16 */
+#define EXTI_PR_PR17 0x00020000U /*!< Pending bit for line 17 */
+#define EXTI_PR_PR18 0x00040000U /*!< Pending bit for line 18 */
+#define EXTI_PR_PR19 0x00080000U /*!< Pending bit for line 19 */
+#define EXTI_PR_PR20 0x00100000U /*!< Pending bit for line 20 */
+#define EXTI_PR_PR21 0x00200000U /*!< Pending bit for line 21 */
+#define EXTI_PR_PR22 0x00400000U /*!< Pending bit for line 22 */
+#define EXTI_PR_PR23 0x00800000U /*!< Pending bit for line 23 */
+
+/******************************************************************************/
+/* */
+/* FLASH */
+/* */
+/******************************************************************************/
+/******************* Bits definition for FLASH_ACR register *****************/
+#define FLASH_ACR_LATENCY 0x0000000FU
+#define FLASH_ACR_LATENCY_0WS 0x00000000U
+#define FLASH_ACR_LATENCY_1WS 0x00000001U
+#define FLASH_ACR_LATENCY_2WS 0x00000002U
+#define FLASH_ACR_LATENCY_3WS 0x00000003U
+#define FLASH_ACR_LATENCY_4WS 0x00000004U
+#define FLASH_ACR_LATENCY_5WS 0x00000005U
+#define FLASH_ACR_LATENCY_6WS 0x00000006U
+#define FLASH_ACR_LATENCY_7WS 0x00000007U
+
+#define FLASH_ACR_PRFTEN 0x00000100U
+#define FLASH_ACR_ICEN 0x00000200U
+#define FLASH_ACR_DCEN 0x00000400U
+#define FLASH_ACR_ICRST 0x00000800U
+#define FLASH_ACR_DCRST 0x00001000U
+#define FLASH_ACR_BYTE0_ADDRESS 0x40023C00U
+#define FLASH_ACR_BYTE2_ADDRESS 0x40023C03U
+
+/******************* Bits definition for FLASH_SR register ******************/
+#define FLASH_SR_EOP 0x00000001U
+#define FLASH_SR_SOP 0x00000002U
+#define FLASH_SR_WRPERR 0x00000010U
+#define FLASH_SR_PGAERR 0x00000020U
+#define FLASH_SR_PGPERR 0x00000040U
+#define FLASH_SR_PGSERR 0x00000080U
+#define FLASH_SR_BSY 0x00010000U
+
+/******************* Bits definition for FLASH_CR register ******************/
+#define FLASH_CR_PG 0x00000001U
+#define FLASH_CR_SER 0x00000002U
+#define FLASH_CR_MER 0x00000004U
+#define FLASH_CR_SNB 0x000000F8U
+#define FLASH_CR_SNB_0 0x00000008U
+#define FLASH_CR_SNB_1 0x00000010U
+#define FLASH_CR_SNB_2 0x00000020U
+#define FLASH_CR_SNB_3 0x00000040U
+#define FLASH_CR_SNB_4 0x00000080U
+#define FLASH_CR_PSIZE 0x00000300U
+#define FLASH_CR_PSIZE_0 0x00000100U
+#define FLASH_CR_PSIZE_1 0x00000200U
+#define FLASH_CR_STRT 0x00010000U
+#define FLASH_CR_EOPIE 0x01000000U
+#define FLASH_CR_LOCK 0x80000000U
+
+/******************* Bits definition for FLASH_OPTCR register ***************/
+#define FLASH_OPTCR_OPTLOCK 0x00000001U
+#define FLASH_OPTCR_OPTSTRT 0x00000002U
+#define FLASH_OPTCR_BOR_LEV_0 0x00000004U
+#define FLASH_OPTCR_BOR_LEV_1 0x00000008U
+#define FLASH_OPTCR_BOR_LEV 0x0000000CU
+
+#define FLASH_OPTCR_WDG_SW 0x00000020U
+#define FLASH_OPTCR_nRST_STOP 0x00000040U
+#define FLASH_OPTCR_nRST_STDBY 0x00000080U
+#define FLASH_OPTCR_RDP 0x0000FF00U
+#define FLASH_OPTCR_RDP_0 0x00000100U
+#define FLASH_OPTCR_RDP_1 0x00000200U
+#define FLASH_OPTCR_RDP_2 0x00000400U
+#define FLASH_OPTCR_RDP_3 0x00000800U
+#define FLASH_OPTCR_RDP_4 0x00001000U
+#define FLASH_OPTCR_RDP_5 0x00002000U
+#define FLASH_OPTCR_RDP_6 0x00004000U
+#define FLASH_OPTCR_RDP_7 0x00008000U
+#define FLASH_OPTCR_nWRP 0x0FFF0000U
+#define FLASH_OPTCR_nWRP_0 0x00010000U
+#define FLASH_OPTCR_nWRP_1 0x00020000U
+#define FLASH_OPTCR_nWRP_2 0x00040000U
+#define FLASH_OPTCR_nWRP_3 0x00080000U
+#define FLASH_OPTCR_nWRP_4 0x00100000U
+#define FLASH_OPTCR_nWRP_5 0x00200000U
+#define FLASH_OPTCR_nWRP_6 0x00400000U
+#define FLASH_OPTCR_nWRP_7 0x00800000U
+#define FLASH_OPTCR_nWRP_8 0x01000000U
+#define FLASH_OPTCR_nWRP_9 0x02000000U
+#define FLASH_OPTCR_nWRP_10 0x04000000U
+#define FLASH_OPTCR_nWRP_11 0x08000000U
+
+/****************** Bits definition for FLASH_OPTCR1 register ***************/
+#define FLASH_OPTCR1_nWRP 0x0FFF0000U
+#define FLASH_OPTCR1_nWRP_0 0x00010000U
+#define FLASH_OPTCR1_nWRP_1 0x00020000U
+#define FLASH_OPTCR1_nWRP_2 0x00040000U
+#define FLASH_OPTCR1_nWRP_3 0x00080000U
+#define FLASH_OPTCR1_nWRP_4 0x00100000U
+#define FLASH_OPTCR1_nWRP_5 0x00200000U
+#define FLASH_OPTCR1_nWRP_6 0x00400000U
+#define FLASH_OPTCR1_nWRP_7 0x00800000U
+#define FLASH_OPTCR1_nWRP_8 0x01000000U
+#define FLASH_OPTCR1_nWRP_9 0x02000000U
+#define FLASH_OPTCR1_nWRP_10 0x04000000U
+#define FLASH_OPTCR1_nWRP_11 0x08000000U
+
+/******************************************************************************/
+/* */
+/* General Purpose I/O */
+/* */
+/******************************************************************************/
+/****************** Bits definition for GPIO_MODER register *****************/
+#define GPIO_MODER_MODER0 0x00000003U
+#define GPIO_MODER_MODER0_0 0x00000001U
+#define GPIO_MODER_MODER0_1 0x00000002U
+
+#define GPIO_MODER_MODER1 0x0000000CU
+#define GPIO_MODER_MODER1_0 0x00000004U
+#define GPIO_MODER_MODER1_1 0x00000008U
+
+#define GPIO_MODER_MODER2 0x00000030U
+#define GPIO_MODER_MODER2_0 0x00000010U
+#define GPIO_MODER_MODER2_1 0x00000020U
+
+#define GPIO_MODER_MODER3 0x000000C0U
+#define GPIO_MODER_MODER3_0 0x00000040U
+#define GPIO_MODER_MODER3_1 0x00000080U
+
+#define GPIO_MODER_MODER4 0x00000300U
+#define GPIO_MODER_MODER4_0 0x00000100U
+#define GPIO_MODER_MODER4_1 0x00000200U
+
+#define GPIO_MODER_MODER5 0x00000C00U
+#define GPIO_MODER_MODER5_0 0x00000400U
+#define GPIO_MODER_MODER5_1 0x00000800U
+
+#define GPIO_MODER_MODER6 0x00003000U
+#define GPIO_MODER_MODER6_0 0x00001000U
+#define GPIO_MODER_MODER6_1 0x00002000U
+
+#define GPIO_MODER_MODER7 0x0000C000U
+#define GPIO_MODER_MODER7_0 0x00004000U
+#define GPIO_MODER_MODER7_1 0x00008000U
+
+#define GPIO_MODER_MODER8 0x00030000U
+#define GPIO_MODER_MODER8_0 0x00010000U
+#define GPIO_MODER_MODER8_1 0x00020000U
+
+#define GPIO_MODER_MODER9 0x000C0000U
+#define GPIO_MODER_MODER9_0 0x00040000U
+#define GPIO_MODER_MODER9_1 0x00080000U
+
+#define GPIO_MODER_MODER10 0x00300000U
+#define GPIO_MODER_MODER10_0 0x00100000U
+#define GPIO_MODER_MODER10_1 0x00200000U
+
+#define GPIO_MODER_MODER11 0x00C00000U
+#define GPIO_MODER_MODER11_0 0x00400000U
+#define GPIO_MODER_MODER11_1 0x00800000U
+
+#define GPIO_MODER_MODER12 0x03000000U
+#define GPIO_MODER_MODER12_0 0x01000000U
+#define GPIO_MODER_MODER12_1 0x02000000U
+
+#define GPIO_MODER_MODER13 0x0C000000U
+#define GPIO_MODER_MODER13_0 0x04000000U
+#define GPIO_MODER_MODER13_1 0x08000000U
+
+#define GPIO_MODER_MODER14 0x30000000U
+#define GPIO_MODER_MODER14_0 0x10000000U
+#define GPIO_MODER_MODER14_1 0x20000000U
+
+#define GPIO_MODER_MODER15 0xC0000000U
+#define GPIO_MODER_MODER15_0 0x40000000U
+#define GPIO_MODER_MODER15_1 0x80000000U
+
+/****************** Bits definition for GPIO_OTYPER register ****************/
+#define GPIO_OTYPER_OT_0 0x00000001U
+#define GPIO_OTYPER_OT_1 0x00000002U
+#define GPIO_OTYPER_OT_2 0x00000004U
+#define GPIO_OTYPER_OT_3 0x00000008U
+#define GPIO_OTYPER_OT_4 0x00000010U
+#define GPIO_OTYPER_OT_5 0x00000020U
+#define GPIO_OTYPER_OT_6 0x00000040U
+#define GPIO_OTYPER_OT_7 0x00000080U
+#define GPIO_OTYPER_OT_8 0x00000100U
+#define GPIO_OTYPER_OT_9 0x00000200U
+#define GPIO_OTYPER_OT_10 0x00000400U
+#define GPIO_OTYPER_OT_11 0x00000800U
+#define GPIO_OTYPER_OT_12 0x00001000U
+#define GPIO_OTYPER_OT_13 0x00002000U
+#define GPIO_OTYPER_OT_14 0x00004000U
+#define GPIO_OTYPER_OT_15 0x00008000U
+
+/****************** Bits definition for GPIO_OSPEEDR register ***************/
+#define GPIO_OSPEEDER_OSPEEDR0 0x00000003U
+#define GPIO_OSPEEDER_OSPEEDR0_0 0x00000001U
+#define GPIO_OSPEEDER_OSPEEDR0_1 0x00000002U
+
+#define GPIO_OSPEEDER_OSPEEDR1 0x0000000CU
+#define GPIO_OSPEEDER_OSPEEDR1_0 0x00000004U
+#define GPIO_OSPEEDER_OSPEEDR1_1 0x00000008U
+
+#define GPIO_OSPEEDER_OSPEEDR2 0x00000030U
+#define GPIO_OSPEEDER_OSPEEDR2_0 0x00000010U
+#define GPIO_OSPEEDER_OSPEEDR2_1 0x00000020U
+
+#define GPIO_OSPEEDER_OSPEEDR3 0x000000C0U
+#define GPIO_OSPEEDER_OSPEEDR3_0 0x00000040U
+#define GPIO_OSPEEDER_OSPEEDR3_1 0x00000080U
+
+#define GPIO_OSPEEDER_OSPEEDR4 0x00000300U
+#define GPIO_OSPEEDER_OSPEEDR4_0 0x00000100U
+#define GPIO_OSPEEDER_OSPEEDR4_1 0x00000200U
+
+#define GPIO_OSPEEDER_OSPEEDR5 0x00000C00U
+#define GPIO_OSPEEDER_OSPEEDR5_0 0x00000400U
+#define GPIO_OSPEEDER_OSPEEDR5_1 0x00000800U
+
+#define GPIO_OSPEEDER_OSPEEDR6 0x00003000U
+#define GPIO_OSPEEDER_OSPEEDR6_0 0x00001000U
+#define GPIO_OSPEEDER_OSPEEDR6_1 0x00002000U
+
+#define GPIO_OSPEEDER_OSPEEDR7 0x0000C000U
+#define GPIO_OSPEEDER_OSPEEDR7_0 0x00004000U
+#define GPIO_OSPEEDER_OSPEEDR7_1 0x00008000U
+
+#define GPIO_OSPEEDER_OSPEEDR8 0x00030000U
+#define GPIO_OSPEEDER_OSPEEDR8_0 0x00010000U
+#define GPIO_OSPEEDER_OSPEEDR8_1 0x00020000U
+
+#define GPIO_OSPEEDER_OSPEEDR9 0x000C0000U
+#define GPIO_OSPEEDER_OSPEEDR9_0 0x00040000U
+#define GPIO_OSPEEDER_OSPEEDR9_1 0x00080000U
+
+#define GPIO_OSPEEDER_OSPEEDR10 0x00300000U
+#define GPIO_OSPEEDER_OSPEEDR10_0 0x00100000U
+#define GPIO_OSPEEDER_OSPEEDR10_1 0x00200000U
+
+#define GPIO_OSPEEDER_OSPEEDR11 0x00C00000U
+#define GPIO_OSPEEDER_OSPEEDR11_0 0x00400000U
+#define GPIO_OSPEEDER_OSPEEDR11_1 0x00800000U
+
+#define GPIO_OSPEEDER_OSPEEDR12 0x03000000U
+#define GPIO_OSPEEDER_OSPEEDR12_0 0x01000000U
+#define GPIO_OSPEEDER_OSPEEDR12_1 0x02000000U
+
+#define GPIO_OSPEEDER_OSPEEDR13 0x0C000000U
+#define GPIO_OSPEEDER_OSPEEDR13_0 0x04000000U
+#define GPIO_OSPEEDER_OSPEEDR13_1 0x08000000U
+
+#define GPIO_OSPEEDER_OSPEEDR14 0x30000000U
+#define GPIO_OSPEEDER_OSPEEDR14_0 0x10000000U
+#define GPIO_OSPEEDER_OSPEEDR14_1 0x20000000U
+
+#define GPIO_OSPEEDER_OSPEEDR15 0xC0000000U
+#define GPIO_OSPEEDER_OSPEEDR15_0 0x40000000U
+#define GPIO_OSPEEDER_OSPEEDR15_1 0x80000000U
+
+/****************** Bits definition for GPIO_PUPDR register *****************/
+#define GPIO_PUPDR_PUPDR0 0x00000003U
+#define GPIO_PUPDR_PUPDR0_0 0x00000001U
+#define GPIO_PUPDR_PUPDR0_1 0x00000002U
+
+#define GPIO_PUPDR_PUPDR1 0x0000000CU
+#define GPIO_PUPDR_PUPDR1_0 0x00000004U
+#define GPIO_PUPDR_PUPDR1_1 0x00000008U
+
+#define GPIO_PUPDR_PUPDR2 0x00000030U
+#define GPIO_PUPDR_PUPDR2_0 0x00000010U
+#define GPIO_PUPDR_PUPDR2_1 0x00000020U
+
+#define GPIO_PUPDR_PUPDR3 0x000000C0U
+#define GPIO_PUPDR_PUPDR3_0 0x00000040U
+#define GPIO_PUPDR_PUPDR3_1 0x00000080U
+
+#define GPIO_PUPDR_PUPDR4 0x00000300U
+#define GPIO_PUPDR_PUPDR4_0 0x00000100U
+#define GPIO_PUPDR_PUPDR4_1 0x00000200U
+
+#define GPIO_PUPDR_PUPDR5 0x00000C00U
+#define GPIO_PUPDR_PUPDR5_0 0x00000400U
+#define GPIO_PUPDR_PUPDR5_1 0x00000800U
+
+#define GPIO_PUPDR_PUPDR6 0x00003000U
+#define GPIO_PUPDR_PUPDR6_0 0x00001000U
+#define GPIO_PUPDR_PUPDR6_1 0x00002000U
+
+#define GPIO_PUPDR_PUPDR7 0x0000C000U
+#define GPIO_PUPDR_PUPDR7_0 0x00004000U
+#define GPIO_PUPDR_PUPDR7_1 0x00008000U
+
+#define GPIO_PUPDR_PUPDR8 0x00030000U
+#define GPIO_PUPDR_PUPDR8_0 0x00010000U
+#define GPIO_PUPDR_PUPDR8_1 0x00020000U
+
+#define GPIO_PUPDR_PUPDR9 0x000C0000U
+#define GPIO_PUPDR_PUPDR9_0 0x00040000U
+#define GPIO_PUPDR_PUPDR9_1 0x00080000U
+
+#define GPIO_PUPDR_PUPDR10 0x00300000U
+#define GPIO_PUPDR_PUPDR10_0 0x00100000U
+#define GPIO_PUPDR_PUPDR10_1 0x00200000U
+
+#define GPIO_PUPDR_PUPDR11 0x00C00000U
+#define GPIO_PUPDR_PUPDR11_0 0x00400000U
+#define GPIO_PUPDR_PUPDR11_1 0x00800000U
+
+#define GPIO_PUPDR_PUPDR12 0x03000000U
+#define GPIO_PUPDR_PUPDR12_0 0x01000000U
+#define GPIO_PUPDR_PUPDR12_1 0x02000000U
+
+#define GPIO_PUPDR_PUPDR13 0x0C000000U
+#define GPIO_PUPDR_PUPDR13_0 0x04000000U
+#define GPIO_PUPDR_PUPDR13_1 0x08000000U
+
+#define GPIO_PUPDR_PUPDR14 0x30000000U
+#define GPIO_PUPDR_PUPDR14_0 0x10000000U
+#define GPIO_PUPDR_PUPDR14_1 0x20000000U
+
+#define GPIO_PUPDR_PUPDR15 0xC0000000U
+#define GPIO_PUPDR_PUPDR15_0 0x40000000U
+#define GPIO_PUPDR_PUPDR15_1 0x80000000U
+
+/****************** Bits definition for GPIO_IDR register *******************/
+#define GPIO_IDR_IDR_0 0x00000001U
+#define GPIO_IDR_IDR_1 0x00000002U
+#define GPIO_IDR_IDR_2 0x00000004U
+#define GPIO_IDR_IDR_3 0x00000008U
+#define GPIO_IDR_IDR_4 0x00000010U
+#define GPIO_IDR_IDR_5 0x00000020U
+#define GPIO_IDR_IDR_6 0x00000040U
+#define GPIO_IDR_IDR_7 0x00000080U
+#define GPIO_IDR_IDR_8 0x00000100U
+#define GPIO_IDR_IDR_9 0x00000200U
+#define GPIO_IDR_IDR_10 0x00000400U
+#define GPIO_IDR_IDR_11 0x00000800U
+#define GPIO_IDR_IDR_12 0x00001000U
+#define GPIO_IDR_IDR_13 0x00002000U
+#define GPIO_IDR_IDR_14 0x00004000U
+#define GPIO_IDR_IDR_15 0x00008000U
+
+/****************** Bits definition for GPIO_ODR register *******************/
+#define GPIO_ODR_ODR_0 0x00000001U
+#define GPIO_ODR_ODR_1 0x00000002U
+#define GPIO_ODR_ODR_2 0x00000004U
+#define GPIO_ODR_ODR_3 0x00000008U
+#define GPIO_ODR_ODR_4 0x00000010U
+#define GPIO_ODR_ODR_5 0x00000020U
+#define GPIO_ODR_ODR_6 0x00000040U
+#define GPIO_ODR_ODR_7 0x00000080U
+#define GPIO_ODR_ODR_8 0x00000100U
+#define GPIO_ODR_ODR_9 0x00000200U
+#define GPIO_ODR_ODR_10 0x00000400U
+#define GPIO_ODR_ODR_11 0x00000800U
+#define GPIO_ODR_ODR_12 0x00001000U
+#define GPIO_ODR_ODR_13 0x00002000U
+#define GPIO_ODR_ODR_14 0x00004000U
+#define GPIO_ODR_ODR_15 0x00008000U
+
+/****************** Bits definition for GPIO_BSRR register ******************/
+#define GPIO_BSRR_BS_0 0x00000001U
+#define GPIO_BSRR_BS_1 0x00000002U
+#define GPIO_BSRR_BS_2 0x00000004U
+#define GPIO_BSRR_BS_3 0x00000008U
+#define GPIO_BSRR_BS_4 0x00000010U
+#define GPIO_BSRR_BS_5 0x00000020U
+#define GPIO_BSRR_BS_6 0x00000040U
+#define GPIO_BSRR_BS_7 0x00000080U
+#define GPIO_BSRR_BS_8 0x00000100U
+#define GPIO_BSRR_BS_9 0x00000200U
+#define GPIO_BSRR_BS_10 0x00000400U
+#define GPIO_BSRR_BS_11 0x00000800U
+#define GPIO_BSRR_BS_12 0x00001000U
+#define GPIO_BSRR_BS_13 0x00002000U
+#define GPIO_BSRR_BS_14 0x00004000U
+#define GPIO_BSRR_BS_15 0x00008000U
+#define GPIO_BSRR_BR_0 0x00010000U
+#define GPIO_BSRR_BR_1 0x00020000U
+#define GPIO_BSRR_BR_2 0x00040000U
+#define GPIO_BSRR_BR_3 0x00080000U
+#define GPIO_BSRR_BR_4 0x00100000U
+#define GPIO_BSRR_BR_5 0x00200000U
+#define GPIO_BSRR_BR_6 0x00400000U
+#define GPIO_BSRR_BR_7 0x00800000U
+#define GPIO_BSRR_BR_8 0x01000000U
+#define GPIO_BSRR_BR_9 0x02000000U
+#define GPIO_BSRR_BR_10 0x04000000U
+#define GPIO_BSRR_BR_11 0x08000000U
+#define GPIO_BSRR_BR_12 0x10000000U
+#define GPIO_BSRR_BR_13 0x20000000U
+#define GPIO_BSRR_BR_14 0x40000000U
+#define GPIO_BSRR_BR_15 0x80000000U
+
+/****************** Bit definition for GPIO_LCKR register *********************/
+#define GPIO_LCKR_LCK0 0x00000001U
+#define GPIO_LCKR_LCK1 0x00000002U
+#define GPIO_LCKR_LCK2 0x00000004U
+#define GPIO_LCKR_LCK3 0x00000008U
+#define GPIO_LCKR_LCK4 0x00000010U
+#define GPIO_LCKR_LCK5 0x00000020U
+#define GPIO_LCKR_LCK6 0x00000040U
+#define GPIO_LCKR_LCK7 0x00000080U
+#define GPIO_LCKR_LCK8 0x00000100U
+#define GPIO_LCKR_LCK9 0x00000200U
+#define GPIO_LCKR_LCK10 0x00000400U
+#define GPIO_LCKR_LCK11 0x00000800U
+#define GPIO_LCKR_LCK12 0x00001000U
+#define GPIO_LCKR_LCK13 0x00002000U
+#define GPIO_LCKR_LCK14 0x00004000U
+#define GPIO_LCKR_LCK15 0x00008000U
+#define GPIO_LCKR_LCKK 0x00010000U
+
+/******************************************************************************/
+/* */
+/* Inter-integrated Circuit Interface */
+/* */
+/******************************************************************************/
+/******************* Bit definition for I2C_CR1 register ********************/
+#define I2C_CR1_PE 0x00000001U /*!<Peripheral Enable */
+#define I2C_CR1_SMBUS 0x00000002U /*!<SMBus Mode */
+#define I2C_CR1_SMBTYPE 0x00000008U /*!<SMBus Type */
+#define I2C_CR1_ENARP 0x00000010U /*!<ARP Enable */
+#define I2C_CR1_ENPEC 0x00000020U /*!<PEC Enable */
+#define I2C_CR1_ENGC 0x00000040U /*!<General Call Enable */
+#define I2C_CR1_NOSTRETCH 0x00000080U /*!<Clock Stretching Disable (Slave mode) */
+#define I2C_CR1_START 0x00000100U /*!<Start Generation */
+#define I2C_CR1_STOP 0x00000200U /*!<Stop Generation */
+#define I2C_CR1_ACK 0x00000400U /*!<Acknowledge Enable */
+#define I2C_CR1_POS 0x00000800U /*!<Acknowledge/PEC Position (for data reception) */
+#define I2C_CR1_PEC 0x00001000U /*!<Packet Error Checking */
+#define I2C_CR1_ALERT 0x00002000U /*!<SMBus Alert */
+#define I2C_CR1_SWRST 0x00008000U /*!<Software Reset */
+
+/******************* Bit definition for I2C_CR2 register ********************/
+#define I2C_CR2_FREQ 0x0000003FU /*!<FREQ[5:0] bits (Peripheral Clock Frequency) */
+#define I2C_CR2_FREQ_0 0x00000001U /*!<Bit 0 */
+#define I2C_CR2_FREQ_1 0x00000002U /*!<Bit 1 */
+#define I2C_CR2_FREQ_2 0x00000004U /*!<Bit 2 */
+#define I2C_CR2_FREQ_3 0x00000008U /*!<Bit 3 */
+#define I2C_CR2_FREQ_4 0x00000010U /*!<Bit 4 */
+#define I2C_CR2_FREQ_5 0x00000020U /*!<Bit 5 */
+
+#define I2C_CR2_ITERREN 0x00000100U /*!<Error Interrupt Enable */
+#define I2C_CR2_ITEVTEN 0x00000200U /*!<Event Interrupt Enable */
+#define I2C_CR2_ITBUFEN 0x00000400U /*!<Buffer Interrupt Enable */
+#define I2C_CR2_DMAEN 0x00000800U /*!<DMA Requests Enable */
+#define I2C_CR2_LAST 0x00001000U /*!<DMA Last Transfer */
+
+/******************* Bit definition for I2C_OAR1 register *******************/
+#define I2C_OAR1_ADD1_7 0x000000FEU /*!<Interface Address */
+#define I2C_OAR1_ADD8_9 0x00000300U /*!<Interface Address */
+
+#define I2C_OAR1_ADD0 0x00000001U /*!<Bit 0 */
+#define I2C_OAR1_ADD1 0x00000002U /*!<Bit 1 */
+#define I2C_OAR1_ADD2 0x00000004U /*!<Bit 2 */
+#define I2C_OAR1_ADD3 0x00000008U /*!<Bit 3 */
+#define I2C_OAR1_ADD4 0x00000010U /*!<Bit 4 */
+#define I2C_OAR1_ADD5 0x00000020U /*!<Bit 5 */
+#define I2C_OAR1_ADD6 0x00000040U /*!<Bit 6 */
+#define I2C_OAR1_ADD7 0x00000080U /*!<Bit 7 */
+#define I2C_OAR1_ADD8 0x00000100U /*!<Bit 8 */
+#define I2C_OAR1_ADD9 0x00000200U /*!<Bit 9 */
+
+#define I2C_OAR1_ADDMODE 0x00008000U /*!<Addressing Mode (Slave mode) */
+
+/******************* Bit definition for I2C_OAR2 register *******************/
+#define I2C_OAR2_ENDUAL 0x00000001U /*!<Dual addressing mode enable */
+#define I2C_OAR2_ADD2 0x000000FEU /*!<Interface address */
+
+/******************** Bit definition for I2C_DR register ********************/
+#define I2C_DR_DR 0x000000FFU /*!<8-bit Data Register */
+
+/******************* Bit definition for I2C_SR1 register ********************/
+#define I2C_SR1_SB 0x00000001U /*!<Start Bit (Master mode) */
+#define I2C_SR1_ADDR 0x00000002U /*!<Address sent (master mode)/matched (slave mode) */
+#define I2C_SR1_BTF 0x00000004U /*!<Byte Transfer Finished */
+#define I2C_SR1_ADD10 0x00000008U /*!<10-bit header sent (Master mode) */
+#define I2C_SR1_STOPF 0x00000010U /*!<Stop detection (Slave mode) */
+#define I2C_SR1_RXNE 0x00000040U /*!<Data Register not Empty (receivers) */
+#define I2C_SR1_TXE 0x00000080U /*!<Data Register Empty (transmitters) */
+#define I2C_SR1_BERR 0x00000100U /*!<Bus Error */
+#define I2C_SR1_ARLO 0x00000200U /*!<Arbitration Lost (master mode) */
+#define I2C_SR1_AF 0x00000400U /*!<Acknowledge Failure */
+#define I2C_SR1_OVR 0x00000800U /*!<Overrun/Underrun */
+#define I2C_SR1_PECERR 0x00001000U /*!<PEC Error in reception */
+#define I2C_SR1_TIMEOUT 0x00004000U /*!<Timeout or Tlow Error */
+#define I2C_SR1_SMBALERT 0x00008000U /*!<SMBus Alert */
+
+/******************* Bit definition for I2C_SR2 register ********************/
+#define I2C_SR2_MSL 0x00000001U /*!<Master/Slave */
+#define I2C_SR2_BUSY 0x00000002U /*!<Bus Busy */
+#define I2C_SR2_TRA 0x00000004U /*!<Transmitter/Receiver */
+#define I2C_SR2_GENCALL 0x00000010U /*!<General Call Address (Slave mode) */
+#define I2C_SR2_SMBDEFAULT 0x00000020U /*!<SMBus Device Default Address (Slave mode) */
+#define I2C_SR2_SMBHOST 0x00000040U /*!<SMBus Host Header (Slave mode) */
+#define I2C_SR2_DUALF 0x00000080U /*!<Dual Flag (Slave mode) */
+#define I2C_SR2_PEC 0x0000FF00U /*!<Packet Error Checking Register */
+
+/******************* Bit definition for I2C_CCR register ********************/
+#define I2C_CCR_CCR 0x00000FFFU /*!<Clock Control Register in Fast/Standard mode (Master mode) */
+#define I2C_CCR_DUTY 0x00004000U /*!<Fast Mode Duty Cycle */
+#define I2C_CCR_FS 0x00008000U /*!<I2C Master Mode Selection */
+
+/****************** Bit definition for I2C_TRISE register *******************/
+#define I2C_TRISE_TRISE 0x0000003FU /*!<Maximum Rise Time in Fast/Standard mode (Master mode) */
+
+/****************** Bit definition for I2C_FLTR register *******************/
+#define I2C_FLTR_DNF 0x0000000FU /*!<Digital Noise Filter */
+#define I2C_FLTR_ANOFF 0x00000010U /*!<Analog Noise Filter OFF */
+
+/******************************************************************************/
+/* */
+/* Fast Mode Plus Inter-integrated Circuit Interface (I2C) */
+/* */
+/******************************************************************************/
+/******************* Bit definition for I2C_CR1 register *******************/
+#define FMPI2C_CR1_PE 0x00000001U /*!< Peripheral enable */
+#define FMPI2C_CR1_TXIE 0x00000002U /*!< TX interrupt enable */
+#define FMPI2C_CR1_RXIE 0x00000004U /*!< RX interrupt enable */
+#define FMPI2C_CR1_ADDRIE 0x00000008U /*!< Address match interrupt enable */
+#define FMPI2C_CR1_NACKIE 0x00000010U /*!< NACK received interrupt enable */
+#define FMPI2C_CR1_STOPIE 0x00000020U /*!< STOP detection interrupt enable */
+#define FMPI2C_CR1_TCIE 0x00000040U /*!< Transfer complete interrupt enable */
+#define FMPI2C_CR1_ERRIE 0x00000080U /*!< Errors interrupt enable */
+#define FMPI2C_CR1_DFN 0x00000F00U /*!< Digital noise filter */
+#define FMPI2C_CR1_ANFOFF 0x00001000U /*!< Analog noise filter OFF */
+#define FMPI2C_CR1_TXDMAEN 0x00004000U /*!< DMA transmission requests enable */
+#define FMPI2C_CR1_RXDMAEN 0x00008000U /*!< DMA reception requests enable */
+#define FMPI2C_CR1_SBC 0x00010000U /*!< Slave byte control */
+#define FMPI2C_CR1_NOSTRETCH 0x00020000U /*!< Clock stretching disable */
+#define FMPI2C_CR1_GCEN 0x00080000U /*!< General call enable */
+#define FMPI2C_CR1_SMBHEN 0x00100000U /*!< SMBus host address enable */
+#define FMPI2C_CR1_SMBDEN 0x00200000U /*!< SMBus device default address enable */
+#define FMPI2C_CR1_ALERTEN 0x00400000U /*!< SMBus alert enable */
+#define FMPI2C_CR1_PECEN 0x00800000U /*!< PEC enable */
+
+/****************** Bit definition for I2C_CR2 register ********************/
+#define FMPI2C_CR2_SADD 0x000003FFU /*!< Slave address (master mode) */
+#define FMPI2C_CR2_RD_WRN 0x00000400U /*!< Transfer direction (master mode) */
+#define FMPI2C_CR2_ADD10 0x00000800U /*!< 10-bit addressing mode (master mode) */
+#define FMPI2C_CR2_HEAD10R 0x00001000U /*!< 10-bit address header only read direction (master mode) */
+#define FMPI2C_CR2_START 0x00002000U /*!< START generation */
+#define FMPI2C_CR2_STOP 0x00004000U /*!< STOP generation (master mode) */
+#define FMPI2C_CR2_NACK 0x00008000U /*!< NACK generation (slave mode) */
+#define FMPI2C_CR2_NBYTES 0x00FF0000U /*!< Number of bytes */
+#define FMPI2C_CR2_RELOAD 0x01000000U /*!< NBYTES reload mode */
+#define FMPI2C_CR2_AUTOEND 0x02000000U /*!< Automatic end mode (master mode) */
+#define FMPI2C_CR2_PECBYTE 0x04000000U /*!< Packet error checking byte */
+
+/******************* Bit definition for I2C_OAR1 register ******************/
+#define FMPI2C_OAR1_OA1 0x000003FFU /*!< Interface own address 1 */
+#define FMPI2C_OAR1_OA1MODE 0x00000400U /*!< Own address 1 10-bit mode */
+#define FMPI2C_OAR1_OA1EN 0x00008000U /*!< Own address 1 enable */
+
+/******************* Bit definition for I2C_OAR2 register ******************/
+#define FMPI2C_OAR2_OA2 0x000000FEU /*!< Interface own address 2 */
+#define FMPI2C_OAR2_OA2MSK 0x00000700U /*!< Own address 2 masks */
+#define FMPI2C_OAR2_OA2EN 0x00008000U /*!< Own address 2 enable */
+
+/******************* Bit definition for I2C_TIMINGR register *******************/
+#define FMPI2C_TIMINGR_SCLL 0x000000FFU /*!< SCL low period (master mode) */
+#define FMPI2C_TIMINGR_SCLH 0x0000FF00U /*!< SCL high period (master mode) */
+#define FMPI2C_TIMINGR_SDADEL 0x000F0000U /*!< Data hold time */
+#define FMPI2C_TIMINGR_SCLDEL 0x00F00000U /*!< Data setup time */
+#define FMPI2C_TIMINGR_PRESC 0xF0000000U /*!< Timings prescaler */
+
+/******************* Bit definition for I2C_TIMEOUTR register *******************/
+#define FMPI2C_TIMEOUTR_TIMEOUTA 0x00000FFFU /*!< Bus timeout A */
+#define FMPI2C_TIMEOUTR_TIDLE 0x00001000U /*!< Idle clock timeout detection */
+#define FMPI2C_TIMEOUTR_TIMOUTEN 0x00008000U /*!< Clock timeout enable */
+#define FMPI2C_TIMEOUTR_TIMEOUTB 0x0FFF0000U /*!< Bus timeout B */
+#define FMPI2C_TIMEOUTR_TEXTEN 0x80000000U /*!< Extended clock timeout enable */
+
+/****************** Bit definition for I2C_ISR register *********************/
+#define FMPI2C_ISR_TXE 0x00000001U /*!< Transmit data register empty */
+#define FMPI2C_ISR_TXIS 0x00000002U /*!< Transmit interrupt status */
+#define FMPI2C_ISR_RXNE 0x00000004U /*!< Receive data register not empty */
+#define FMPI2C_ISR_ADDR 0x00000008U /*!< Address matched (slave mode) */
+#define FMPI2C_ISR_NACKF 0x00000010U /*!< NACK received flag */
+#define FMPI2C_ISR_STOPF 0x00000020U /*!< STOP detection flag */
+#define FMPI2C_ISR_TC 0x00000040U /*!< Transfer complete (master mode) */
+#define FMPI2C_ISR_TCR 0x00000080U /*!< Transfer complete reload */
+#define FMPI2C_ISR_BERR 0x00000100U /*!< Bus error */
+#define FMPI2C_ISR_ARLO 0x00000200U /*!< Arbitration lost */
+#define FMPI2C_ISR_OVR 0x00000400U /*!< Overrun/Underrun */
+#define FMPI2C_ISR_PECERR 0x00000800U /*!< PEC error in reception */
+#define FMPI2C_ISR_TIMEOUT 0x00001000U /*!< Timeout or Tlow detection flag */
+#define FMPI2C_ISR_ALERT 0x00002000U /*!< SMBus alert */
+#define FMPI2C_ISR_BUSY 0x00008000U /*!< Bus busy */
+#define FMPI2C_ISR_DIR 0x00010000U /*!< Transfer direction (slave mode) */
+#define FMPI2C_ISR_ADDCODE 0x00FE0000U /*!< Address match code (slave mode) */
+
+/****************** Bit definition for I2C_ICR register *********************/
+#define FMPI2C_ICR_ADDRCF 0x00000008U /*!< Address matched clear flag */
+#define FMPI2C_ICR_NACKCF 0x00000010U /*!< NACK clear flag */
+#define FMPI2C_ICR_STOPCF 0x00000020U /*!< STOP detection clear flag */
+#define FMPI2C_ICR_BERRCF 0x00000100U /*!< Bus error clear flag */
+#define FMPI2C_ICR_ARLOCF 0x00000200U /*!< Arbitration lost clear flag */
+#define FMPI2C_ICR_OVRCF 0x00000400U /*!< Overrun/Underrun clear flag */
+#define FMPI2C_ICR_PECCF 0x00000800U /*!< PAC error clear flag */
+#define FMPI2C_ICR_TIMOUTCF 0x00001000U /*!< Timeout clear flag */
+#define FMPI2C_ICR_ALERTCF 0x00002000U /*!< Alert clear flag */
+
+/****************** Bit definition for I2C_PECR register *********************/
+#define FMPI2C_PECR_PEC 0x000000FFU /*!< PEC register */
+
+/****************** Bit definition for I2C_RXDR register *********************/
+#define FMPI2C_RXDR_RXDATA 0x000000FFU /*!< 8-bit receive data */
+
+/****************** Bit definition for I2C_TXDR register *********************/
+#define FMPI2C_TXDR_TXDATA 0x000000FFU /*!< 8-bit transmit data */
+
+/******************************************************************************/
+/* */
+/* Independent WATCHDOG */
+/* */
+/******************************************************************************/
+/******************* Bit definition for IWDG_KR register ********************/
+#define IWDG_KR_KEY 0xFFFFU /*!<Key value (write only, read 0000h) */
+
+/******************* Bit definition for IWDG_PR register ********************/
+#define IWDG_PR_PR 0x07U /*!<PR[2:0] (Prescaler divider) */
+#define IWDG_PR_PR_0 0x01U /*!<Bit 0 */
+#define IWDG_PR_PR_1 0x02U /*!<Bit 1 */
+#define IWDG_PR_PR_2 0x04U /*!<Bit 2 */
+
+/******************* Bit definition for IWDG_RLR register *******************/
+#define IWDG_RLR_RL 0x0FFFU /*!<Watchdog counter reload value */
+
+/******************* Bit definition for IWDG_SR register ********************/
+#define IWDG_SR_PVU 0x01U /*!<Watchdog prescaler value update */
+#define IWDG_SR_RVU 0x02U /*!<Watchdog counter reload value update */
+
+
+/******************************************************************************/
+/* */
+/* Power Control */
+/* */
+/******************************************************************************/
+/******************** Bit definition for PWR_CR register ********************/
+#define PWR_CR_LPDS 0x00000001U /*!< Low-Power Deepsleep */
+#define PWR_CR_PDDS 0x00000002U /*!< Power Down Deepsleep */
+#define PWR_CR_CWUF 0x00000004U /*!< Clear Wakeup Flag */
+#define PWR_CR_CSBF 0x00000008U /*!< Clear Standby Flag */
+#define PWR_CR_PVDE 0x00000010U /*!< Power Voltage Detector Enable */
+
+#define PWR_CR_PLS 0x000000E0U /*!< PLS[2:0] bits (PVD Level Selection) */
+#define PWR_CR_PLS_0 0x00000020U /*!< Bit 0 */
+#define PWR_CR_PLS_1 0x00000040U /*!< Bit 1 */
+#define PWR_CR_PLS_2 0x00000080U /*!< Bit 2 */
+
+/*!< PVD level configuration */
+#define PWR_CR_PLS_LEV0 0x00000000U /*!< PVD level 0 */
+#define PWR_CR_PLS_LEV1 0x00000020U /*!< PVD level 1 */
+#define PWR_CR_PLS_LEV2 0x00000040U /*!< PVD level 2 */
+#define PWR_CR_PLS_LEV3 0x00000060U /*!< PVD level 3 */
+#define PWR_CR_PLS_LEV4 0x00000080U /*!< PVD level 4 */
+#define PWR_CR_PLS_LEV5 0x000000A0U /*!< PVD level 5 */
+#define PWR_CR_PLS_LEV6 0x000000C0U /*!< PVD level 6 */
+#define PWR_CR_PLS_LEV7 0x000000E0U /*!< PVD level 7 */
+
+#define PWR_CR_DBP 0x00000100U /*!< Disable Backup Domain write protection */
+#define PWR_CR_FPDS 0x00000200U /*!< Flash power down in Stop mode */
+#define PWR_CR_LPLVDS 0x00000400U /*!< Low Power Regulator Low Voltage in Deep Sleep mode */
+#define PWR_CR_MRLVDS 0x00000800U /*!< Main Regulator Low Voltage in Deep Sleep mode */
+#define PWR_CR_ADCDC1 0x00002000U /*!< Refer to AN4073 on how to use this bit */
+
+#define PWR_CR_VOS 0x0000C000U /*!< VOS[1:0] bits (Regulator voltage scaling output selection) */
+#define PWR_CR_VOS_0 0x00004000U /*!< Bit 0 */
+#define PWR_CR_VOS_1 0x00008000U /*!< Bit 1 */
+
+#define PWR_CR_FMSSR 0x00100000U /*!< Flash Memory Sleep System Run */
+#define PWR_CR_FISSR 0x00200000U /*!< Flash Interface Stop while System Run */
+/* Legacy define */
+#define PWR_CR_PMODE PWR_CR_VOS
+
+/******************* Bit definition for PWR_CSR register ********************/
+#define PWR_CSR_WUF 0x00000001U /*!< Wakeup Flag */
+#define PWR_CSR_SBF 0x00000002U /*!< Standby Flag */
+#define PWR_CSR_PVDO 0x00000004U /*!< PVD Output */
+#define PWR_CSR_BRR 0x00000008U /*!< Backup regulator ready */
+#define PWR_CSR_EWUP 0x00000100U /*!< Enable WKUP pin */
+#define PWR_CSR_BRE 0x00000200U /*!< Backup regulator enable */
+#define PWR_CSR_VOSRDY 0x00004000U /*!< Regulator voltage scaling output selection ready */
+
+/* Legacy define */
+#define PWR_CSR_REGRDY PWR_CSR_VOSRDY
+
+/******************************************************************************/
+/* */
+/* Reset and Clock Control */
+/* */
+/******************************************************************************/
+/******************** Bit definition for RCC_CR register ********************/
+#define RCC_CR_HSION 0x00000001U
+#define RCC_CR_HSIRDY 0x00000002U
+
+#define RCC_CR_HSITRIM 0x000000F8U
+#define RCC_CR_HSITRIM_0 0x00000008U/*!<Bit 0 */
+#define RCC_CR_HSITRIM_1 0x00000010U/*!<Bit 1 */
+#define RCC_CR_HSITRIM_2 0x00000020U/*!<Bit 2 */
+#define RCC_CR_HSITRIM_3 0x00000040U/*!<Bit 3 */
+#define RCC_CR_HSITRIM_4 0x00000080U/*!<Bit 4 */
+
+#define RCC_CR_HSICAL 0x0000FF00U
+#define RCC_CR_HSICAL_0 0x00000100U/*!<Bit 0 */
+#define RCC_CR_HSICAL_1 0x00000200U/*!<Bit 1 */
+#define RCC_CR_HSICAL_2 0x00000400U/*!<Bit 2 */
+#define RCC_CR_HSICAL_3 0x00000800U/*!<Bit 3 */
+#define RCC_CR_HSICAL_4 0x00001000U/*!<Bit 4 */
+#define RCC_CR_HSICAL_5 0x00002000U/*!<Bit 5 */
+#define RCC_CR_HSICAL_6 0x00004000U/*!<Bit 6 */
+#define RCC_CR_HSICAL_7 0x00008000U/*!<Bit 7 */
+
+#define RCC_CR_HSEON 0x00010000U
+#define RCC_CR_HSERDY 0x00020000U
+#define RCC_CR_HSEBYP 0x00040000U
+#define RCC_CR_CSSON 0x00080000U
+#define RCC_CR_PLLON 0x01000000U
+#define RCC_CR_PLLRDY 0x02000000U
+
+/******************** Bit definition for RCC_PLLCFGR register ***************/
+#define RCC_PLLCFGR_PLLM 0x0000003FU
+#define RCC_PLLCFGR_PLLM_0 0x00000001U
+#define RCC_PLLCFGR_PLLM_1 0x00000002U
+#define RCC_PLLCFGR_PLLM_2 0x00000004U
+#define RCC_PLLCFGR_PLLM_3 0x00000008U
+#define RCC_PLLCFGR_PLLM_4 0x00000010U
+#define RCC_PLLCFGR_PLLM_5 0x00000020U
+
+#define RCC_PLLCFGR_PLLN 0x00007FC0U
+#define RCC_PLLCFGR_PLLN_0 0x00000040U
+#define RCC_PLLCFGR_PLLN_1 0x00000080U
+#define RCC_PLLCFGR_PLLN_2 0x00000100U
+#define RCC_PLLCFGR_PLLN_3 0x00000200U
+#define RCC_PLLCFGR_PLLN_4 0x00000400U
+#define RCC_PLLCFGR_PLLN_5 0x00000800U
+#define RCC_PLLCFGR_PLLN_6 0x00001000U
+#define RCC_PLLCFGR_PLLN_7 0x00002000U
+#define RCC_PLLCFGR_PLLN_8 0x00004000U
+
+#define RCC_PLLCFGR_PLLP 0x00030000U
+#define RCC_PLLCFGR_PLLP_0 0x00010000U
+#define RCC_PLLCFGR_PLLP_1 0x00020000U
+
+#define RCC_PLLCFGR_PLLSRC 0x00400000U
+#define RCC_PLLCFGR_PLLSRC_HSE 0x00400000U
+#define RCC_PLLCFGR_PLLSRC_HSI 0x00000000U
+
+#define RCC_PLLCFGR_PLLQ 0x0F000000U
+#define RCC_PLLCFGR_PLLQ_0 0x01000000U
+#define RCC_PLLCFGR_PLLQ_1 0x02000000U
+#define RCC_PLLCFGR_PLLQ_2 0x04000000U
+#define RCC_PLLCFGR_PLLQ_3 0x08000000U
+
+#define RCC_PLLCFGR_PLLR 0x70000000U
+#define RCC_PLLCFGR_PLLR_0 0x10000000U
+#define RCC_PLLCFGR_PLLR_1 0x20000000U
+#define RCC_PLLCFGR_PLLR_2 0x40000000U
+/******************** Bit definition for RCC_CFGR register ******************/
+/*!< SW configuration */
+#define RCC_CFGR_SW 0x00000003U /*!< SW[1:0] bits (System clock Switch) */
+#define RCC_CFGR_SW_0 0x00000001U /*!< Bit 0 */
+#define RCC_CFGR_SW_1 0x00000002U /*!< Bit 1 */
+
+#define RCC_CFGR_SW_HSI 0x00000000U /*!< HSI selected as system clock */
+#define RCC_CFGR_SW_HSE 0x00000001U /*!< HSE selected as system clock */
+#define RCC_CFGR_SW_PLL 0x00000002U /*!< PLL selected as system clock */
+
+/*!< SWS configuration */
+#define RCC_CFGR_SWS 0x0000000CU /*!< SWS[1:0] bits (System Clock Switch Status) */
+#define RCC_CFGR_SWS_0 0x00000004U /*!< Bit 0 */
+#define RCC_CFGR_SWS_1 0x00000008U /*!< Bit 1 */
+
+#define RCC_CFGR_SWS_HSI 0x00000000U /*!< HSI oscillator used as system clock */
+#define RCC_CFGR_SWS_HSE 0x00000004U /*!< HSE oscillator used as system clock */
+#define RCC_CFGR_SWS_PLL 0x00000008U /*!< PLL used as system clock */
+
+/*!< HPRE configuration */
+#define RCC_CFGR_HPRE 0x000000F0U /*!< HPRE[3:0] bits (AHB prescaler) */
+#define RCC_CFGR_HPRE_0 0x00000010U /*!< Bit 0 */
+#define RCC_CFGR_HPRE_1 0x00000020U /*!< Bit 1 */
+#define RCC_CFGR_HPRE_2 0x00000040U /*!< Bit 2 */
+#define RCC_CFGR_HPRE_3 0x00000080U /*!< Bit 3 */
+
+#define RCC_CFGR_HPRE_DIV1 0x00000000U /*!< SYSCLK not divided */
+#define RCC_CFGR_HPRE_DIV2 0x00000080U /*!< SYSCLK divided by 2 */
+#define RCC_CFGR_HPRE_DIV4 0x00000090U /*!< SYSCLK divided by 4 */
+#define RCC_CFGR_HPRE_DIV8 0x000000A0U /*!< SYSCLK divided by 8 */
+#define RCC_CFGR_HPRE_DIV16 0x000000B0U /*!< SYSCLK divided by 16 */
+#define RCC_CFGR_HPRE_DIV64 0x000000C0U /*!< SYSCLK divided by 64 */
+#define RCC_CFGR_HPRE_DIV128 0x000000D0U /*!< SYSCLK divided by 128 */
+#define RCC_CFGR_HPRE_DIV256 0x000000E0U /*!< SYSCLK divided by 256 */
+#define RCC_CFGR_HPRE_DIV512 0x000000F0U /*!< SYSCLK divided by 512 */
+
+/*!< MCO1EN configuration */
+#define RCC_CFGR_MCO1EN 0x00000100U /*!< MCO1EN bit */
+
+/*!< MCO2EN configuration */
+#define RCC_CFGR_MCO2EN 0x00000200U /*!< MCO2EN bit */
+
+/*!< PPRE1 configuration */
+#define RCC_CFGR_PPRE1 0x00001C00U /*!< PRE1[2:0] bits (APB1 prescaler) */
+#define RCC_CFGR_PPRE1_0 0x00000400U /*!< Bit 0 */
+#define RCC_CFGR_PPRE1_1 0x00000800U /*!< Bit 1 */
+#define RCC_CFGR_PPRE1_2 0x00001000U /*!< Bit 2 */
+
+#define RCC_CFGR_PPRE1_DIV1 0x00000000U /*!< HCLK not divided */
+#define RCC_CFGR_PPRE1_DIV2 0x00001000U /*!< HCLK divided by 2 */
+#define RCC_CFGR_PPRE1_DIV4 0x00001400U /*!< HCLK divided by 4 */
+#define RCC_CFGR_PPRE1_DIV8 0x00001800U /*!< HCLK divided by 8 */
+#define RCC_CFGR_PPRE1_DIV16 0x00001C00U /*!< HCLK divided by 16 */
+
+/*!< PPRE2 configuration */
+#define RCC_CFGR_PPRE2 0x0000E000U /*!< PRE2[2:0] bits (APB2 prescaler) */
+#define RCC_CFGR_PPRE2_0 0x00002000U /*!< Bit 0 */
+#define RCC_CFGR_PPRE2_1 0x00004000U /*!< Bit 1 */
+#define RCC_CFGR_PPRE2_2 0x00008000U /*!< Bit 2 */
+
+#define RCC_CFGR_PPRE2_DIV1 0x00000000U /*!< HCLK not divided */
+#define RCC_CFGR_PPRE2_DIV2 0x00008000U /*!< HCLK divided by 2 */
+#define RCC_CFGR_PPRE2_DIV4 0x0000A000U /*!< HCLK divided by 4 */
+#define RCC_CFGR_PPRE2_DIV8 0x0000C000U /*!< HCLK divided by 8 */
+#define RCC_CFGR_PPRE2_DIV16 0x0000E000U /*!< HCLK divided by 16 */
+
+/*!< RTCPRE configuration */
+#define RCC_CFGR_RTCPRE 0x001F0000U
+#define RCC_CFGR_RTCPRE_0 0x00010000U
+#define RCC_CFGR_RTCPRE_1 0x00020000U
+#define RCC_CFGR_RTCPRE_2 0x00040000U
+#define RCC_CFGR_RTCPRE_3 0x00080000U
+#define RCC_CFGR_RTCPRE_4 0x00100000U
+
+/*!< MCO1 configuration */
+#define RCC_CFGR_MCO1 0x00600000U
+#define RCC_CFGR_MCO1_0 0x00200000U
+#define RCC_CFGR_MCO1_1 0x00400000U
+
+#define RCC_CFGR_MCO1PRE 0x07000000U
+#define RCC_CFGR_MCO1PRE_0 0x01000000U
+#define RCC_CFGR_MCO1PRE_1 0x02000000U
+#define RCC_CFGR_MCO1PRE_2 0x04000000U
+
+#define RCC_CFGR_MCO2PRE 0x38000000U
+#define RCC_CFGR_MCO2PRE_0 0x08000000U
+#define RCC_CFGR_MCO2PRE_1 0x10000000U
+#define RCC_CFGR_MCO2PRE_2 0x20000000U
+
+#define RCC_CFGR_MCO2 0xC0000000U
+#define RCC_CFGR_MCO2_0 0x40000000U
+#define RCC_CFGR_MCO2_1 0x80000000U
+
+/******************** Bit definition for RCC_CIR register *******************/
+#define RCC_CIR_LSIRDYF 0x00000001U
+#define RCC_CIR_LSERDYF 0x00000002U
+#define RCC_CIR_HSIRDYF 0x00000004U
+#define RCC_CIR_HSERDYF 0x00000008U
+#define RCC_CIR_PLLRDYF 0x00000010U
+
+#define RCC_CIR_CSSF 0x00000080U
+#define RCC_CIR_LSIRDYIE 0x00000100U
+#define RCC_CIR_LSERDYIE 0x00000200U
+#define RCC_CIR_HSIRDYIE 0x00000400U
+#define RCC_CIR_HSERDYIE 0x00000800U
+#define RCC_CIR_PLLRDYIE 0x00001000U
+
+#define RCC_CIR_LSIRDYC 0x00010000U
+#define RCC_CIR_LSERDYC 0x00020000U
+#define RCC_CIR_HSIRDYC 0x00040000U
+#define RCC_CIR_HSERDYC 0x00080000U
+#define RCC_CIR_PLLRDYC 0x00100000U
+
+#define RCC_CIR_CSSC 0x00800000U
+
+/******************** Bit definition for RCC_AHB1RSTR register **************/
+#define RCC_AHB1RSTR_GPIOARST 0x00000001U
+#define RCC_AHB1RSTR_GPIOBRST 0x00000002U
+#define RCC_AHB1RSTR_GPIOCRST 0x00000004U
+#define RCC_AHB1RSTR_GPIOHRST 0x00000080U
+#define RCC_AHB1RSTR_CRCRST 0x00001000U
+#define RCC_AHB1RSTR_DMA1RST 0x00200000U
+#define RCC_AHB1RSTR_DMA2RST 0x00400000U
+#define RCC_AHB1RSTR_RNGRST 0x80000000U
+
+/******************** Bit definition for RCC_APB1RSTR register **************/
+#define RCC_APB1RSTR_TIM5RST 0x00000008U
+#define RCC_APB1RSTR_TIM6RST 0x00000010U
+#define RCC_APB1RSTR_LPTIM1RST 0x00000200U
+#define RCC_APB1RSTR_WWDGRST 0x00000800U
+#define RCC_APB1RSTR_SPI2RST 0x00004000U
+#define RCC_APB1RSTR_USART2RST 0x00020000U
+#define RCC_APB1RSTR_I2C1RST 0x00200000U
+#define RCC_APB1RSTR_I2C2RST 0x00400000U
+#define RCC_APB1RSTR_FMPI2C1RST 0x01000000U
+#define RCC_APB1RSTR_PWRRST 0x10000000U
+#define RCC_APB1RSTR_DACRST 0x20000000U
+
+/******************** Bit definition for RCC_APB2RSTR register **************/
+#define RCC_APB2RSTR_TIM1RST 0x00000001U
+#define RCC_APB2RSTR_USART1RST 0x00000010U
+#define RCC_APB2RSTR_USART6RST 0x00000020U
+#define RCC_APB2RSTR_ADCRST 0x00000100U
+#define RCC_APB2RSTR_SPI1RST 0x00001000U
+#define RCC_APB2RSTR_SYSCFGRST 0x00004000U
+#define RCC_APB2RSTR_TIM9RST 0x00010000U
+#define RCC_APB2RSTR_TIM11RST 0x00040000U
+#define RCC_APB2RSTR_SPI5RST 0x00100000U
+
+/******************** Bit definition for RCC_AHB1ENR register ***************/
+#define RCC_AHB1ENR_GPIOAEN 0x00000001U
+#define RCC_AHB1ENR_GPIOBEN 0x00000002U
+#define RCC_AHB1ENR_GPIOCEN 0x00000004U
+#define RCC_AHB1ENR_GPIOHEN 0x00000080U
+#define RCC_AHB1ENR_CRCEN 0x00001000U
+#define RCC_AHB1ENR_DMA1EN 0x00200000U
+#define RCC_AHB1ENR_DMA2EN 0x00400000U
+#define RCC_AHB1ENR_RNGEN 0x80000000U
+
+/******************** Bit definition for RCC_APB1ENR register ***************/
+#define RCC_APB1ENR_TIM5EN 0x00000008U
+#define RCC_APB1ENR_TIM6EN 0x00000010U
+#define RCC_APB1ENR_LPTIM1EN 0x00000200U
+#define RCC_APB1ENR_RTCAPBEN 0x00000400U
+#define RCC_APB1ENR_WWDGEN 0x00000800U
+#define RCC_APB1ENR_SPI2EN 0x00004000U
+#define RCC_APB1ENR_USART2EN 0x00020000U
+#define RCC_APB1ENR_I2C1EN 0x00200000U
+#define RCC_APB1ENR_I2C2EN 0x00400000U
+#define RCC_APB1ENR_FMPI2C1EN 0x01000000U
+#define RCC_APB1ENR_PWREN 0x10000000U
+#define RCC_APB1ENR_DACEN 0x20000000U
+
+/******************** Bit definition for RCC_APB2ENR register ***************/
+#define RCC_APB2ENR_TIM1EN 0x00000001U
+#define RCC_APB2ENR_USART1EN 0x00000010U
+#define RCC_APB2ENR_USART6EN 0x00000020U
+#define RCC_APB2ENR_ADC1EN 0x00000100U
+#define RCC_APB2ENR_SPI1EN 0x00001000U
+#define RCC_APB2ENR_SYSCFGEN 0x00004000U
+#define RCC_APB2ENR_EXTITEN 0x00008000U
+#define RCC_APB2ENR_TIM9EN 0x00010000U
+#define RCC_APB2ENR_TIM11EN 0x00040000U
+#define RCC_APB2ENR_SPI5EN 0x00100000U
+
+/******************** Bit definition for RCC_AHB1LPENR register *************/
+#define RCC_AHB1LPENR_GPIOALPEN 0x00000001U
+#define RCC_AHB1LPENR_GPIOBLPEN 0x00000002U
+#define RCC_AHB1LPENR_GPIOCLPEN 0x00000004U
+#define RCC_AHB1LPENR_GPIOHLPEN 0x00000080U
+#define RCC_AHB1LPENR_CRCLPEN 0x00001000U
+#define RCC_AHB1LPENR_FLITFLPEN 0x00008000U
+#define RCC_AHB1LPENR_SRAM1LPEN 0x00010000U
+#define RCC_AHB1LPENR_DMA1LPEN 0x00200000U
+#define RCC_AHB1LPENR_DMA2LPEN 0x00400000U
+#define RCC_AHB1LPENR_RNGLPEN 0x80000000U
+
+/******************** Bit definition for RCC_APB1LPENR register *************/
+#define RCC_APB1LPENR_TIM5LPEN 0x00000008U
+#define RCC_APB1LPENR_TIM6LPEN 0x00000010U
+#define RCC_APB1LPENR_LPTIM1LPEN 0x00000200U
+#define RCC_APB1LPENR_RTCAPBLPEN 0x00000400U
+#define RCC_APB1LPENR_WWDGLPEN 0x00000800U
+#define RCC_APB1LPENR_SPI2LPEN 0x00004000U
+#define RCC_APB1LPENR_USART2LPEN 0x00020000U
+#define RCC_APB1LPENR_I2C1LPEN 0x00200000U
+#define RCC_APB1LPENR_I2C2LPEN 0x00400000U
+#define RCC_APB1LPENR_FMPI2C1LPEN 0x01000000U
+#define RCC_APB1LPENR_PWRLPEN 0x10000000U
+#define RCC_APB1LPENR_DACLPEN 0x20000000U
+
+/******************** Bit definition for RCC_APB2LPENR register *************/
+#define RCC_APB2LPENR_TIM1LPEN 0x00000001U
+#define RCC_APB2LPENR_USART1LPEN 0x00000010U
+#define RCC_APB2LPENR_USART6LPEN 0x00000020U
+#define RCC_APB2LPENR_ADC1LPEN 0x00000100U
+#define RCC_APB2LPENR_SPI1LPEN 0x00001000U
+#define RCC_APB2LPENR_SYSCFGLPEN 0x00004000U
+#define RCC_APB2LPENR_EXTITLPEN 0x00008000U
+#define RCC_APB2LPENR_TIM9LPEN 0x00010000U
+#define RCC_APB2LPENR_TIM11LPEN 0x00040000U
+#define RCC_APB2LPENR_SPI5LPEN 0x00100000U
+
+/******************** Bit definition for RCC_BDCR register ******************/
+#define RCC_BDCR_LSEON 0x00000001U
+#define RCC_BDCR_LSERDY 0x00000002U
+#define RCC_BDCR_LSEBYP 0x00000004U
+#define RCC_BDCR_LSEMOD 0x00000008U
+
+#define RCC_BDCR_RTCSEL 0x00000300U
+#define RCC_BDCR_RTCSEL_0 0x00000100U
+#define RCC_BDCR_RTCSEL_1 0x00000200U
+
+#define RCC_BDCR_RTCEN 0x00008000U
+#define RCC_BDCR_BDRST 0x00010000U
+
+/******************** Bit definition for RCC_CSR register *******************/
+#define RCC_CSR_LSION 0x00000001U
+#define RCC_CSR_LSIRDY 0x00000002U
+#define RCC_CSR_RMVF 0x01000000U
+#define RCC_CSR_BORRSTF 0x02000000U
+#define RCC_CSR_PADRSTF 0x04000000U
+#define RCC_CSR_PORRSTF 0x08000000U
+#define RCC_CSR_SFTRSTF 0x10000000U
+#define RCC_CSR_WDGRSTF 0x20000000U
+#define RCC_CSR_WWDGRSTF 0x40000000U
+#define RCC_CSR_LPWRRSTF 0x80000000U
+
+/******************** Bit definition for RCC_SSCGR register *****************/
+#define RCC_SSCGR_MODPER 0x00001FFFU
+#define RCC_SSCGR_INCSTEP 0x0FFFE000U
+#define RCC_SSCGR_SPREADSEL 0x40000000U
+#define RCC_SSCGR_SSCGEN 0x80000000U
+
+/******************** Bit definition for RCC_DCKCFGR register ***************/
+#define RCC_DCKCFGR_TIMPRE 0x01000000U
+#define RCC_DCKCFGR_I2SSRC 0x06000000U
+#define RCC_DCKCFGR_I2SSRC_0 0x02000000U
+#define RCC_DCKCFGR_I2SSRC_1 0x04000000U
+
+/******************** Bit definition for RCC_CKGATENR register **************/
+#define RCC_CKGATENR_AHB2APB1_CKEN 0x00000001U
+#define RCC_CKGATENR_AHB2APB2_CKEN 0x00000002U
+#define RCC_CKGATENR_CM4DBG_CKEN 0x00000004U
+#define RCC_CKGATENR_SPARE_CKEN 0x00000008U
+#define RCC_CKGATENR_SRAM_CKEN 0x00000010U
+#define RCC_CKGATENR_FLITF_CKEN 0x00000020U
+#define RCC_CKGATENR_RCC_CKEN 0x00000040U
+
+/******************** Bit definition for RCC_DCKCFGR2 register **************/
+#define RCC_DCKCFGR2_FMPI2C1SEL 0x00C00000U
+#define RCC_DCKCFGR2_FMPI2C1SEL_0 0x00400000U
+#define RCC_DCKCFGR2_FMPI2C1SEL_1 0x00800000U
+#define RCC_DCKCFGR2_LPTIM1SEL 0xC0000000U
+#define RCC_DCKCFGR2_LPTIM1SEL_0 0x40000000U
+#define RCC_DCKCFGR2_LPTIM1SEL_1 0x80000000U
+
+/******************************************************************************/
+/* */
+/* RNG */
+/* */
+/******************************************************************************/
+/******************** Bits definition for RNG_CR register *******************/
+#define RNG_CR_RNGEN 0x00000004U
+#define RNG_CR_IE 0x00000008U
+
+/******************** Bits definition for RNG_SR register *******************/
+#define RNG_SR_DRDY 0x00000001U
+#define RNG_SR_CECS 0x00000002U
+#define RNG_SR_SECS 0x00000004U
+#define RNG_SR_CEIS 0x00000020U
+#define RNG_SR_SEIS 0x00000040U
+
+/******************************************************************************/
+/* */
+/* Real-Time Clock (RTC) */
+/* */
+/******************************************************************************/
+/******************** Bits definition for RTC_TR register *******************/
+#define RTC_TR_PM 0x00400000U
+#define RTC_TR_HT 0x00300000U
+#define RTC_TR_HT_0 0x00100000U
+#define RTC_TR_HT_1 0x00200000U
+#define RTC_TR_HU 0x000F0000U
+#define RTC_TR_HU_0 0x00010000U
+#define RTC_TR_HU_1 0x00020000U
+#define RTC_TR_HU_2 0x00040000U
+#define RTC_TR_HU_3 0x00080000U
+#define RTC_TR_MNT 0x00007000U
+#define RTC_TR_MNT_0 0x00001000U
+#define RTC_TR_MNT_1 0x00002000U
+#define RTC_TR_MNT_2 0x00004000U
+#define RTC_TR_MNU 0x00000F00U
+#define RTC_TR_MNU_0 0x00000100U
+#define RTC_TR_MNU_1 0x00000200U
+#define RTC_TR_MNU_2 0x00000400U
+#define RTC_TR_MNU_3 0x00000800U
+#define RTC_TR_ST 0x00000070U
+#define RTC_TR_ST_0 0x00000010U
+#define RTC_TR_ST_1 0x00000020U
+#define RTC_TR_ST_2 0x00000040U
+#define RTC_TR_SU 0x0000000FU
+#define RTC_TR_SU_0 0x00000001U
+#define RTC_TR_SU_1 0x00000002U
+#define RTC_TR_SU_2 0x00000004U
+#define RTC_TR_SU_3 0x00000008U
+
+/******************** Bits definition for RTC_DR register *******************/
+#define RTC_DR_YT 0x00F00000U
+#define RTC_DR_YT_0 0x00100000U
+#define RTC_DR_YT_1 0x00200000U
+#define RTC_DR_YT_2 0x00400000U
+#define RTC_DR_YT_3 0x00800000U
+#define RTC_DR_YU 0x000F0000U
+#define RTC_DR_YU_0 0x00010000U
+#define RTC_DR_YU_1 0x00020000U
+#define RTC_DR_YU_2 0x00040000U
+#define RTC_DR_YU_3 0x00080000U
+#define RTC_DR_WDU 0x0000E000U
+#define RTC_DR_WDU_0 0x00002000U
+#define RTC_DR_WDU_1 0x00004000U
+#define RTC_DR_WDU_2 0x00008000U
+#define RTC_DR_MT 0x00001000U
+#define RTC_DR_MU 0x00000F00U
+#define RTC_DR_MU_0 0x00000100U
+#define RTC_DR_MU_1 0x00000200U
+#define RTC_DR_MU_2 0x00000400U
+#define RTC_DR_MU_3 0x00000800U
+#define RTC_DR_DT 0x00000030U
+#define RTC_DR_DT_0 0x00000010U
+#define RTC_DR_DT_1 0x00000020U
+#define RTC_DR_DU 0x0000000FU
+#define RTC_DR_DU_0 0x00000001U
+#define RTC_DR_DU_1 0x00000002U
+#define RTC_DR_DU_2 0x00000004U
+#define RTC_DR_DU_3 0x00000008U
+
+/******************** Bits definition for RTC_CR register *******************/
+#define RTC_CR_COE 0x00800000U
+#define RTC_CR_OSEL 0x00600000U
+#define RTC_CR_OSEL_0 0x00200000U
+#define RTC_CR_OSEL_1 0x00400000U
+#define RTC_CR_POL 0x00100000U
+#define RTC_CR_COSEL 0x00080000U
+#define RTC_CR_BCK 0x00040000U
+#define RTC_CR_SUB1H 0x00020000U
+#define RTC_CR_ADD1H 0x00010000U
+#define RTC_CR_TSIE 0x00008000U
+#define RTC_CR_WUTIE 0x00004000U
+#define RTC_CR_ALRBIE 0x00002000U
+#define RTC_CR_ALRAIE 0x00001000U
+#define RTC_CR_TSE 0x00000800U
+#define RTC_CR_WUTE 0x00000400U
+#define RTC_CR_ALRBE 0x00000200U
+#define RTC_CR_ALRAE 0x00000100U
+#define RTC_CR_DCE 0x00000080U
+#define RTC_CR_FMT 0x00000040U
+#define RTC_CR_BYPSHAD 0x00000020U
+#define RTC_CR_REFCKON 0x00000010U
+#define RTC_CR_TSEDGE 0x00000008U
+#define RTC_CR_WUCKSEL 0x00000007U
+#define RTC_CR_WUCKSEL_0 0x00000001U
+#define RTC_CR_WUCKSEL_1 0x00000002U
+#define RTC_CR_WUCKSEL_2 0x00000004U
+
+/******************** Bits definition for RTC_ISR register ******************/
+#define RTC_ISR_RECALPF 0x00010000U
+#define RTC_ISR_TAMP1F 0x00002000U
+#define RTC_ISR_TAMP2F 0x00004000U
+#define RTC_ISR_TSOVF 0x00001000U
+#define RTC_ISR_TSF 0x00000800U
+#define RTC_ISR_WUTF 0x00000400U
+#define RTC_ISR_ALRBF 0x00000200U
+#define RTC_ISR_ALRAF 0x00000100U
+#define RTC_ISR_INIT 0x00000080U
+#define RTC_ISR_INITF 0x00000040U
+#define RTC_ISR_RSF 0x00000020U
+#define RTC_ISR_INITS 0x00000010U
+#define RTC_ISR_SHPF 0x00000008U
+#define RTC_ISR_WUTWF 0x00000004U
+#define RTC_ISR_ALRBWF 0x00000002U
+#define RTC_ISR_ALRAWF 0x00000001U
+
+/******************** Bits definition for RTC_PRER register *****************/
+#define RTC_PRER_PREDIV_A 0x007F0000U
+#define RTC_PRER_PREDIV_S 0x00007FFFU
+
+/******************** Bits definition for RTC_WUTR register *****************/
+#define RTC_WUTR_WUT 0x0000FFFFU
+
+/******************** Bits definition for RTC_CALIBR register ***************/
+#define RTC_CALIBR_DCS 0x00000080U
+#define RTC_CALIBR_DC 0x0000001FU
+
+/******************** Bits definition for RTC_ALRMAR register ***************/
+#define RTC_ALRMAR_MSK4 0x80000000U
+#define RTC_ALRMAR_WDSEL 0x40000000U
+#define RTC_ALRMAR_DT 0x30000000U
+#define RTC_ALRMAR_DT_0 0x10000000U
+#define RTC_ALRMAR_DT_1 0x20000000U
+#define RTC_ALRMAR_DU 0x0F000000U
+#define RTC_ALRMAR_DU_0 0x01000000U
+#define RTC_ALRMAR_DU_1 0x02000000U
+#define RTC_ALRMAR_DU_2 0x04000000U
+#define RTC_ALRMAR_DU_3 0x08000000U
+#define RTC_ALRMAR_MSK3 0x00800000U
+#define RTC_ALRMAR_PM 0x00400000U
+#define RTC_ALRMAR_HT 0x00300000U
+#define RTC_ALRMAR_HT_0 0x00100000U
+#define RTC_ALRMAR_HT_1 0x00200000U
+#define RTC_ALRMAR_HU 0x000F0000U
+#define RTC_ALRMAR_HU_0 0x00010000U
+#define RTC_ALRMAR_HU_1 0x00020000U
+#define RTC_ALRMAR_HU_2 0x00040000U
+#define RTC_ALRMAR_HU_3 0x00080000U
+#define RTC_ALRMAR_MSK2 0x00008000U
+#define RTC_ALRMAR_MNT 0x00007000U
+#define RTC_ALRMAR_MNT_0 0x00001000U
+#define RTC_ALRMAR_MNT_1 0x00002000U
+#define RTC_ALRMAR_MNT_2 0x00004000U
+#define RTC_ALRMAR_MNU 0x00000F00U
+#define RTC_ALRMAR_MNU_0 0x00000100U
+#define RTC_ALRMAR_MNU_1 0x00000200U
+#define RTC_ALRMAR_MNU_2 0x00000400U
+#define RTC_ALRMAR_MNU_3 0x00000800U
+#define RTC_ALRMAR_MSK1 0x00000080U
+#define RTC_ALRMAR_ST 0x00000070U
+#define RTC_ALRMAR_ST_0 0x00000010U
+#define RTC_ALRMAR_ST_1 0x00000020U
+#define RTC_ALRMAR_ST_2 0x00000040U
+#define RTC_ALRMAR_SU 0x0000000FU
+#define RTC_ALRMAR_SU_0 0x00000001U
+#define RTC_ALRMAR_SU_1 0x00000002U
+#define RTC_ALRMAR_SU_2 0x00000004U
+#define RTC_ALRMAR_SU_3 0x00000008U
+
+/******************** Bits definition for RTC_ALRMBR register ***************/
+#define RTC_ALRMBR_MSK4 0x80000000U
+#define RTC_ALRMBR_WDSEL 0x40000000U
+#define RTC_ALRMBR_DT 0x30000000U
+#define RTC_ALRMBR_DT_0 0x10000000U
+#define RTC_ALRMBR_DT_1 0x20000000U
+#define RTC_ALRMBR_DU 0x0F000000U
+#define RTC_ALRMBR_DU_0 0x01000000U
+#define RTC_ALRMBR_DU_1 0x02000000U
+#define RTC_ALRMBR_DU_2 0x04000000U
+#define RTC_ALRMBR_DU_3 0x08000000U
+#define RTC_ALRMBR_MSK3 0x00800000U
+#define RTC_ALRMBR_PM 0x00400000U
+#define RTC_ALRMBR_HT 0x00300000U
+#define RTC_ALRMBR_HT_0 0x00100000U
+#define RTC_ALRMBR_HT_1 0x00200000U
+#define RTC_ALRMBR_HU 0x000F0000U
+#define RTC_ALRMBR_HU_0 0x00010000U
+#define RTC_ALRMBR_HU_1 0x00020000U
+#define RTC_ALRMBR_HU_2 0x00040000U
+#define RTC_ALRMBR_HU_3 0x00080000U
+#define RTC_ALRMBR_MSK2 0x00008000U
+#define RTC_ALRMBR_MNT 0x00007000U
+#define RTC_ALRMBR_MNT_0 0x00001000U
+#define RTC_ALRMBR_MNT_1 0x00002000U
+#define RTC_ALRMBR_MNT_2 0x00004000U
+#define RTC_ALRMBR_MNU 0x00000F00U
+#define RTC_ALRMBR_MNU_0 0x00000100U
+#define RTC_ALRMBR_MNU_1 0x00000200U
+#define RTC_ALRMBR_MNU_2 0x00000400U
+#define RTC_ALRMBR_MNU_3 0x00000800U
+#define RTC_ALRMBR_MSK1 0x00000080U
+#define RTC_ALRMBR_ST 0x00000070U
+#define RTC_ALRMBR_ST_0 0x00000010U
+#define RTC_ALRMBR_ST_1 0x00000020U
+#define RTC_ALRMBR_ST_2 0x00000040U
+#define RTC_ALRMBR_SU 0x0000000FU
+#define RTC_ALRMBR_SU_0 0x00000001U
+#define RTC_ALRMBR_SU_1 0x00000002U
+#define RTC_ALRMBR_SU_2 0x00000004U
+#define RTC_ALRMBR_SU_3 0x00000008U
+
+/******************** Bits definition for RTC_WPR register ******************/
+#define RTC_WPR_KEY 0x000000FFU
+
+/******************** Bits definition for RTC_SSR register ******************/
+#define RTC_SSR_SS 0x0000FFFFU
+
+/******************** Bits definition for RTC_SHIFTR register ***************/
+#define RTC_SHIFTR_SUBFS 0x00007FFFU
+#define RTC_SHIFTR_ADD1S 0x80000000U
+
+/******************** Bits definition for RTC_TSTR register *****************/
+#define RTC_TSTR_PM 0x00400000U
+#define RTC_TSTR_HT 0x00300000U
+#define RTC_TSTR_HT_0 0x00100000U
+#define RTC_TSTR_HT_1 0x00200000U
+#define RTC_TSTR_HU 0x000F0000U
+#define RTC_TSTR_HU_0 0x00010000U
+#define RTC_TSTR_HU_1 0x00020000U
+#define RTC_TSTR_HU_2 0x00040000U
+#define RTC_TSTR_HU_3 0x00080000U
+#define RTC_TSTR_MNT 0x00007000U
+#define RTC_TSTR_MNT_0 0x00001000U
+#define RTC_TSTR_MNT_1 0x00002000U
+#define RTC_TSTR_MNT_2 0x00004000U
+#define RTC_TSTR_MNU 0x00000F00U
+#define RTC_TSTR_MNU_0 0x00000100U
+#define RTC_TSTR_MNU_1 0x00000200U
+#define RTC_TSTR_MNU_2 0x00000400U
+#define RTC_TSTR_MNU_3 0x00000800U
+#define RTC_TSTR_ST 0x00000070U
+#define RTC_TSTR_ST_0 0x00000010U
+#define RTC_TSTR_ST_1 0x00000020U
+#define RTC_TSTR_ST_2 0x00000040U
+#define RTC_TSTR_SU 0x0000000FU
+#define RTC_TSTR_SU_0 0x00000001U
+#define RTC_TSTR_SU_1 0x00000002U
+#define RTC_TSTR_SU_2 0x00000004U
+#define RTC_TSTR_SU_3 0x00000008U
+
+/******************** Bits definition for RTC_TSDR register *****************/
+#define RTC_TSDR_WDU 0x0000E000U
+#define RTC_TSDR_WDU_0 0x00002000U
+#define RTC_TSDR_WDU_1 0x00004000U
+#define RTC_TSDR_WDU_2 0x00008000U
+#define RTC_TSDR_MT 0x00001000U
+#define RTC_TSDR_MU 0x00000F00U
+#define RTC_TSDR_MU_0 0x00000100U
+#define RTC_TSDR_MU_1 0x00000200U
+#define RTC_TSDR_MU_2 0x00000400U
+#define RTC_TSDR_MU_3 0x00000800U
+#define RTC_TSDR_DT 0x00000030U
+#define RTC_TSDR_DT_0 0x00000010U
+#define RTC_TSDR_DT_1 0x00000020U
+#define RTC_TSDR_DU 0x0000000FU
+#define RTC_TSDR_DU_0 0x00000001U
+#define RTC_TSDR_DU_1 0x00000002U
+#define RTC_TSDR_DU_2 0x00000004U
+#define RTC_TSDR_DU_3 0x00000008U
+
+/******************** Bits definition for RTC_TSSSR register ****************/
+#define RTC_TSSSR_SS 0x0000FFFFU
+
+/******************** Bits definition for RTC_CAL register *****************/
+#define RTC_CALR_CALP 0x00008000U
+#define RTC_CALR_CALW8 0x00004000U
+#define RTC_CALR_CALW16 0x00002000U
+#define RTC_CALR_CALM 0x000001FFU
+#define RTC_CALR_CALM_0 0x00000001U
+#define RTC_CALR_CALM_1 0x00000002U
+#define RTC_CALR_CALM_2 0x00000004U
+#define RTC_CALR_CALM_3 0x00000008U
+#define RTC_CALR_CALM_4 0x00000010U
+#define RTC_CALR_CALM_5 0x00000020U
+#define RTC_CALR_CALM_6 0x00000040U
+#define RTC_CALR_CALM_7 0x00000080U
+#define RTC_CALR_CALM_8 0x00000100U
+
+/******************** Bits definition for RTC_TAFCR register ****************/
+#define RTC_TAFCR_ALARMOUTTYPE 0x00040000U
+#define RTC_TAFCR_TSINSEL 0x00020000U
+#define RTC_TAFCR_TAMPINSEL 0x00010000U
+#define RTC_TAFCR_TAMPPUDIS 0x00008000U
+#define RTC_TAFCR_TAMPPRCH 0x00006000U
+#define RTC_TAFCR_TAMPPRCH_0 0x00002000U
+#define RTC_TAFCR_TAMPPRCH_1 0x00004000U
+#define RTC_TAFCR_TAMPFLT 0x00001800U
+#define RTC_TAFCR_TAMPFLT_0 0x00000800U
+#define RTC_TAFCR_TAMPFLT_1 0x00001000U
+#define RTC_TAFCR_TAMPFREQ 0x00000700U
+#define RTC_TAFCR_TAMPFREQ_0 0x00000100U
+#define RTC_TAFCR_TAMPFREQ_1 0x00000200U
+#define RTC_TAFCR_TAMPFREQ_2 0x00000400U
+#define RTC_TAFCR_TAMPTS 0x00000080U
+#define RTC_TAFCR_TAMP2TRG 0x00000010U
+#define RTC_TAFCR_TAMP2E 0x00000008U
+#define RTC_TAFCR_TAMPIE 0x00000004U
+#define RTC_TAFCR_TAMP1TRG 0x00000002U
+#define RTC_TAFCR_TAMP1E 0x00000001U
+
+/******************** Bits definition for RTC_ALRMASSR register *************/
+#define RTC_ALRMASSR_MASKSS 0x0F000000U
+#define RTC_ALRMASSR_MASKSS_0 0x01000000U
+#define RTC_ALRMASSR_MASKSS_1 0x02000000U
+#define RTC_ALRMASSR_MASKSS_2 0x04000000U
+#define RTC_ALRMASSR_MASKSS_3 0x08000000U
+#define RTC_ALRMASSR_SS 0x00007FFFU
+
+/******************** Bits definition for RTC_ALRMBSSR register *************/
+#define RTC_ALRMBSSR_MASKSS 0x0F000000U
+#define RTC_ALRMBSSR_MASKSS_0 0x01000000U
+#define RTC_ALRMBSSR_MASKSS_1 0x02000000U
+#define RTC_ALRMBSSR_MASKSS_2 0x04000000U
+#define RTC_ALRMBSSR_MASKSS_3 0x08000000U
+#define RTC_ALRMBSSR_SS 0x00007FFFU
+
+/******************** Bits definition for RTC_BKP0R register ****************/
+#define RTC_BKP0R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP1R register ****************/
+#define RTC_BKP1R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP2R register ****************/
+#define RTC_BKP2R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP3R register ****************/
+#define RTC_BKP3R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP4R register ****************/
+#define RTC_BKP4R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP5R register ****************/
+#define RTC_BKP5R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP6R register ****************/
+#define RTC_BKP6R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP7R register ****************/
+#define RTC_BKP7R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP8R register ****************/
+#define RTC_BKP8R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP9R register ****************/
+#define RTC_BKP9R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP10R register ***************/
+#define RTC_BKP10R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP11R register ***************/
+#define RTC_BKP11R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP12R register ***************/
+#define RTC_BKP12R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP13R register ***************/
+#define RTC_BKP13R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP14R register ***************/
+#define RTC_BKP14R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP15R register ***************/
+#define RTC_BKP15R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP16R register ***************/
+#define RTC_BKP16R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP17R register ***************/
+#define RTC_BKP17R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP18R register ***************/
+#define RTC_BKP18R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP19R register ***************/
+#define RTC_BKP19R 0xFFFFFFFFU
+
+/******************************************************************************/
+/* */
+/* Serial Peripheral Interface */
+/* */
+/******************************************************************************/
+/******************* Bit definition for SPI_CR1 register ********************/
+#define SPI_CR1_CPHA 0x00000001U /*!<Clock Phase */
+#define SPI_CR1_CPOL 0x00000002U /*!<Clock Polarity */
+#define SPI_CR1_MSTR 0x00000004U /*!<Master Selection */
+
+#define SPI_CR1_BR 0x00000038U /*!<BR[2:0] bits (Baud Rate Control) */
+#define SPI_CR1_BR_0 0x00000008U /*!<Bit 0 */
+#define SPI_CR1_BR_1 0x00000010U /*!<Bit 1 */
+#define SPI_CR1_BR_2 0x00000020U /*!<Bit 2 */
+
+#define SPI_CR1_SPE 0x00000040U /*!<SPI Enable */
+#define SPI_CR1_LSBFIRST 0x00000080U /*!<Frame Format */
+#define SPI_CR1_SSI 0x00000100U /*!<Internal slave select */
+#define SPI_CR1_SSM 0x00000200U /*!<Software slave management */
+#define SPI_CR1_RXONLY 0x00000400U /*!<Receive only */
+#define SPI_CR1_DFF 0x00000800U /*!<Data Frame Format */
+#define SPI_CR1_CRCNEXT 0x00001000U /*!<Transmit CRC next */
+#define SPI_CR1_CRCEN 0x00002000U /*!<Hardware CRC calculation enable */
+#define SPI_CR1_BIDIOE 0x00004000U /*!<Output enable in bidirectional mode */
+#define SPI_CR1_BIDIMODE 0x00008000U /*!<Bidirectional data mode enable */
+
+/******************* Bit definition for SPI_CR2 register ********************/
+#define SPI_CR2_RXDMAEN 0x00000001U /*!<Rx Buffer DMA Enable */
+#define SPI_CR2_TXDMAEN 0x00000002U /*!<Tx Buffer DMA Enable */
+#define SPI_CR2_SSOE 0x00000004U /*!<SS Output Enable */
+#define SPI_CR2_FRF 0x00000010U /*!<Frame Format */
+#define SPI_CR2_ERRIE 0x00000020U /*!<Error Interrupt Enable */
+#define SPI_CR2_RXNEIE 0x00000040U /*!<RX buffer Not Empty Interrupt Enable */
+#define SPI_CR2_TXEIE 0x00000080U /*!<Tx buffer Empty Interrupt Enable */
+
+/******************** Bit definition for SPI_SR register ********************/
+#define SPI_SR_RXNE 0x00000001U /*!<Receive buffer Not Empty */
+#define SPI_SR_TXE 0x00000002U /*!<Transmit buffer Empty */
+#define SPI_SR_CHSIDE 0x00000004U /*!<Channel side */
+#define SPI_SR_UDR 0x00000008U /*!<Underrun flag */
+#define SPI_SR_CRCERR 0x00000010U /*!<CRC Error flag */
+#define SPI_SR_MODF 0x00000020U /*!<Mode fault */
+#define SPI_SR_OVR 0x00000040U /*!<Overrun flag */
+#define SPI_SR_BSY 0x00000080U /*!<Busy flag */
+#define SPI_SR_FRE 0x00000100U /*!<Frame format error flag */
+
+/******************** Bit definition for SPI_DR register ********************/
+#define SPI_DR_DR 0x0000FFFFU /*!<Data Register */
+
+/******************* Bit definition for SPI_CRCPR register ******************/
+#define SPI_CRCPR_CRCPOLY 0x0000FFFFU /*!<CRC polynomial register */
+
+/****************** Bit definition for SPI_RXCRCR register ******************/
+#define SPI_RXCRCR_RXCRC 0x0000FFFFU /*!<Rx CRC Register */
+
+/****************** Bit definition for SPI_TXCRCR register ******************/
+#define SPI_TXCRCR_TXCRC 0x0000FFFFU /*!<Tx CRC Register */
+
+/****************** Bit definition for SPI_I2SCFGR register *****************/
+#define SPI_I2SCFGR_CHLEN 0x00000001U /*!<Channel length (number of bits per audio channel) */
+
+#define SPI_I2SCFGR_DATLEN 0x00000006U /*!<DATLEN[1:0] bits (Data length to be transferred) */
+#define SPI_I2SCFGR_DATLEN_0 0x00000002U /*!<Bit 0 */
+#define SPI_I2SCFGR_DATLEN_1 0x00000004U /*!<Bit 1 */
+
+#define SPI_I2SCFGR_CKPOL 0x00000008U /*!<steady state clock polarity */
+
+#define SPI_I2SCFGR_I2SSTD 0x00000030U /*!<I2SSTD[1:0] bits (I2S standard selection) */
+#define SPI_I2SCFGR_I2SSTD_0 0x00000010U /*!<Bit 0 */
+#define SPI_I2SCFGR_I2SSTD_1 0x00000020U /*!<Bit 1 */
+
+#define SPI_I2SCFGR_PCMSYNC 0x00000080U /*!<PCM frame synchronization */
+
+#define SPI_I2SCFGR_I2SCFG 0x00000300U /*!<I2SCFG[1:0] bits (I2S configuration mode) */
+#define SPI_I2SCFGR_I2SCFG_0 0x00000100U /*!<Bit 0 */
+#define SPI_I2SCFGR_I2SCFG_1 0x00000200U /*!<Bit 1 */
+
+#define SPI_I2SCFGR_I2SE 0x00000400U /*!<I2S Enable */
+#define SPI_I2SCFGR_I2SMOD 0x00000800U /*!<I2S mode selection */
+
+/****************** Bit definition for SPI_I2SPR register *******************/
+#define SPI_I2SPR_I2SDIV 0x000000FFU /*!<I2S Linear prescaler */
+#define SPI_I2SPR_ODD 0x00000100U /*!<Odd factor for the prescaler */
+#define SPI_I2SPR_MCKOE 0x00000200U /*!<Master Clock Output Enable */
+
+/******************************************************************************/
+/* */
+/* SYSCFG */
+/* */
+/******************************************************************************/
+/****************** Bit definition for SYSCFG_MEMRMP register ***************/
+#define SYSCFG_MEMRMP_MEM_MODE 0x00000007U /*!< SYSCFG_Memory Remap Config */
+#define SYSCFG_MEMRMP_MEM_MODE_0 0x00000001U
+#define SYSCFG_MEMRMP_MEM_MODE_1 0x00000002U
+#define SYSCFG_MEMRMP_MEM_MODE_2 0x00000004U
+
+/****************** Bit definition for SYSCFG_PMC register ******************/
+#define SYSCFG_PMC_ADC1DC2 0x00010000U /*!< Refer to AN4073 on how to use this bit */
+
+/***************** Bit definition for SYSCFG_EXTICR1 register ***************/
+#define SYSCFG_EXTICR1_EXTI0 0x000FU /*!<EXTI 0 configuration */
+#define SYSCFG_EXTICR1_EXTI1 0x00F0U /*!<EXTI 1 configuration */
+#define SYSCFG_EXTICR1_EXTI2 0x0F00U /*!<EXTI 2 configuration */
+#define SYSCFG_EXTICR1_EXTI3 0xF000U /*!<EXTI 3 configuration */
+/**
+ * @brief EXTI0 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI0_PA 0x0000U /*!<PA[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PB 0x0001U /*!<PB[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PC 0x0002U /*!<PC[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PH 0x0007U /*!<PH[0] pin */
+
+/**
+ * @brief EXTI1 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI1_PA 0x0000U /*!<PA[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PB 0x0010U /*!<PB[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PC 0x0020U /*!<PC[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PH 0x0070U /*!<PH[1] pin */
+
+/**
+ * @brief EXTI2 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI2_PA 0x0000U /*!<PA[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PB 0x0100U /*!<PB[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PC 0x0200U /*!<PC[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PH 0x0700U /*!<PH[2] pin */
+
+/**
+ * @brief EXTI3 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI3_PA 0x0000U /*!<PA[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PB 0x1000U /*!<PB[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PC 0x2000U /*!<PC[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PH 0x7000U /*!<PH[3] pin */
+
+/***************** Bit definition for SYSCFG_EXTICR2 register ***************/
+#define SYSCFG_EXTICR2_EXTI4 0x000FU /*!<EXTI 4 configuration */
+#define SYSCFG_EXTICR2_EXTI5 0x00F0U /*!<EXTI 5 configuration */
+#define SYSCFG_EXTICR2_EXTI6 0x0F00U /*!<EXTI 6 configuration */
+#define SYSCFG_EXTICR2_EXTI7 0xF000U /*!<EXTI 7 configuration */
+/**
+ * @brief EXTI4 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI4_PA 0x0000U /*!<PA[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PB 0x0001U /*!<PB[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PC 0x0002U /*!<PC[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PH 0x0007U /*!<PH[4] pin */
+
+/**
+ * @brief EXTI5 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI5_PA 0x0000U /*!<PA[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PB 0x0010U /*!<PB[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PC 0x0020U /*!<PC[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PH 0x0070U /*!<PH[5] pin */
+
+/**
+ * @brief EXTI6 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI6_PA 0x0000U /*!<PA[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PB 0x0100U /*!<PB[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PC 0x0200U /*!<PC[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PH 0x0700U /*!<PH[6] pin */
+
+/**
+ * @brief EXTI7 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI7_PA 0x0000U /*!<PA[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PB 0x1000U /*!<PB[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PC 0x2000U /*!<PC[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PH 0x7000U /*!<PH[7] pin */
+
+
+/***************** Bit definition for SYSCFG_EXTICR3 register ***************/
+#define SYSCFG_EXTICR3_EXTI8 0x000FU /*!<EXTI 8 configuration */
+#define SYSCFG_EXTICR3_EXTI9 0x00F0U /*!<EXTI 9 configuration */
+#define SYSCFG_EXTICR3_EXTI10 0x0F00U /*!<EXTI 10 configuration */
+#define SYSCFG_EXTICR3_EXTI11 0xF000U /*!<EXTI 11 configuration */
+
+/**
+ * @brief EXTI8 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI8_PA 0x0000U /*!<PA[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PB 0x0001U /*!<PB[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PC 0x0002U /*!<PC[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PH 0x0007U /*!<PH[8] pin */
+
+/**
+ * @brief EXTI9 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI9_PA 0x0000U /*!<PA[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PB 0x0010U /*!<PB[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PC 0x0020U /*!<PC[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PH 0x0070U /*!<PH[9] pin */
+
+/**
+ * @brief EXTI10 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI10_PA 0x0000U /*!<PA[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PB 0x0100U /*!<PB[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PC 0x0200U /*!<PC[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PH 0x0700U /*!<PH[10] pin */
+
+/**
+ * @brief EXTI11 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI11_PA 0x0000U /*!<PA[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PB 0x1000U /*!<PB[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PC 0x2000U /*!<PC[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PH 0x7000U /*!<PH[11] pin */
+
+/***************** Bit definition for SYSCFG_EXTICR4 register ***************/
+#define SYSCFG_EXTICR4_EXTI12 0x000FU /*!<EXTI 12 configuration */
+#define SYSCFG_EXTICR4_EXTI13 0x00F0U /*!<EXTI 13 configuration */
+#define SYSCFG_EXTICR4_EXTI14 0x0F00U /*!<EXTI 14 configuration */
+#define SYSCFG_EXTICR4_EXTI15 0xF000U /*!<EXTI 15 configuration */
+/**
+ * @brief EXTI12 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI12_PA 0x0000U /*!<PA[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PB 0x0001U /*!<PB[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PC 0x0002U /*!<PC[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PH 0x0007U /*!<PH[12] pin */
+
+/**
+ * @brief EXTI13 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI13_PA 0x0000U /*!<PA[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PB 0x0010U /*!<PB[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PC 0x0020U /*!<PC[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PH 0x0070U /*!<PH[13] pin */
+
+/**
+ * @brief EXTI14 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI14_PA 0x0000U /*!<PA[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PB 0x0100U /*!<PB[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PC 0x0200U /*!<PC[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PH 0x0700U /*!<PH[14] pin */
+
+/**
+ * @brief EXTI15 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI15_PA 0x0000U /*!<PA[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PB 0x1000U /*!<PB[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PC 0x2000U /*!<PC[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PH 0x7000U /*!<PH[15] pin */
+
+/****************** Bit definition for SYSCFG_CMPCR register ****************/
+#define SYSCFG_CMPCR_CMP_PD 0x00000001U /*!<Compensation cell ready flag */
+#define SYSCFG_CMPCR_READY 0x00000100U /*!<Compensation cell power-down */
+
+/****************** Bit definition for SYSCFG_CFGR register *****************/
+#define SYSCFG_CFGR_FMPI2C1_SCL 0x00000001U /*!<FM+ drive capability for FMPI2C1_SCL pin */
+#define SYSCFG_CFGR_FMPI2C1_SDA 0x00000002U /*!<FM+ drive capability for FMPI2C1_SDA pin */
+
+/****************** Bit definition for SYSCFG_CFGR2 register *****************/
+#define SYSCFG_CFGR2_LOCKUP_LOCK 0x00000001U /*!<Core Lockup lock */
+#define SYSCFG_CFGR2_PVD_LOCK 0x00000004U /*!<PVD Lock */
+
+/******************************************************************************/
+/* */
+/* TIM */
+/* */
+/******************************************************************************/
+/******************* Bit definition for TIM_CR1 register ********************/
+#define TIM_CR1_CEN 0x0001U /*!<Counter enable */
+#define TIM_CR1_UDIS 0x0002U /*!<Update disable */
+#define TIM_CR1_URS 0x0004U /*!<Update request source */
+#define TIM_CR1_OPM 0x0008U /*!<One pulse mode */
+#define TIM_CR1_DIR 0x0010U /*!<Direction */
+
+#define TIM_CR1_CMS 0x0060U /*!<CMS[1:0] bits (Center-aligned mode selection) */
+#define TIM_CR1_CMS_0 0x0020U /*!<Bit 0 */
+#define TIM_CR1_CMS_1 0x0040U /*!<Bit 1 */
+
+#define TIM_CR1_ARPE 0x0080U /*!<Auto-reload preload enable */
+
+#define TIM_CR1_CKD 0x0300U /*!<CKD[1:0] bits (clock division) */
+#define TIM_CR1_CKD_0 0x0100U /*!<Bit 0 */
+#define TIM_CR1_CKD_1 0x0200U /*!<Bit 1 */
+
+/******************* Bit definition for TIM_CR2 register ********************/
+#define TIM_CR2_CCPC 0x0001U /*!<Capture/Compare Preloaded Control */
+#define TIM_CR2_CCUS 0x0004U /*!<Capture/Compare Control Update Selection */
+#define TIM_CR2_CCDS 0x0008U /*!<Capture/Compare DMA Selection */
+
+#define TIM_CR2_MMS 0x0070U /*!<MMS[2:0] bits (Master Mode Selection) */
+#define TIM_CR2_MMS_0 0x0010U /*!<Bit 0 */
+#define TIM_CR2_MMS_1 0x0020U /*!<Bit 1 */
+#define TIM_CR2_MMS_2 0x0040U /*!<Bit 2 */
+
+#define TIM_CR2_TI1S 0x0080U /*!<TI1 Selection */
+#define TIM_CR2_OIS1 0x0100U /*!<Output Idle state 1 (OC1 output) */
+#define TIM_CR2_OIS1N 0x0200U /*!<Output Idle state 1 (OC1N output) */
+#define TIM_CR2_OIS2 0x0400U /*!<Output Idle state 2 (OC2 output) */
+#define TIM_CR2_OIS2N 0x0800U /*!<Output Idle state 2 (OC2N output) */
+#define TIM_CR2_OIS3 0x1000U /*!<Output Idle state 3 (OC3 output) */
+#define TIM_CR2_OIS3N 0x2000U /*!<Output Idle state 3 (OC3N output) */
+#define TIM_CR2_OIS4 0x4000U /*!<Output Idle state 4 (OC4 output) */
+
+/******************* Bit definition for TIM_SMCR register *******************/
+#define TIM_SMCR_SMS 0x0007U /*!<SMS[2:0] bits (Slave mode selection) */
+#define TIM_SMCR_SMS_0 0x0001U /*!<Bit 0 */
+#define TIM_SMCR_SMS_1 0x0002U /*!<Bit 1 */
+#define TIM_SMCR_SMS_2 0x0004U /*!<Bit 2 */
+
+#define TIM_SMCR_TS 0x0070U /*!<TS[2:0] bits (Trigger selection) */
+#define TIM_SMCR_TS_0 0x0010U /*!<Bit 0 */
+#define TIM_SMCR_TS_1 0x0020U /*!<Bit 1 */
+#define TIM_SMCR_TS_2 0x0040U /*!<Bit 2 */
+
+#define TIM_SMCR_MSM 0x0080U /*!<Master/slave mode */
+
+#define TIM_SMCR_ETF 0x0F00U /*!<ETF[3:0] bits (External trigger filter) */
+#define TIM_SMCR_ETF_0 0x0100U /*!<Bit 0 */
+#define TIM_SMCR_ETF_1 0x0200U /*!<Bit 1 */
+#define TIM_SMCR_ETF_2 0x0400U /*!<Bit 2 */
+#define TIM_SMCR_ETF_3 0x0800U /*!<Bit 3 */
+
+#define TIM_SMCR_ETPS 0x3000U /*!<ETPS[1:0] bits (External trigger prescaler) */
+#define TIM_SMCR_ETPS_0 0x1000U /*!<Bit 0 */
+#define TIM_SMCR_ETPS_1 0x2000U /*!<Bit 1 */
+
+#define TIM_SMCR_ECE 0x4000U /*!<External clock enable */
+#define TIM_SMCR_ETP 0x8000U /*!<External trigger polarity */
+
+/******************* Bit definition for TIM_DIER register *******************/
+#define TIM_DIER_UIE 0x0001U /*!<Update interrupt enable */
+#define TIM_DIER_CC1IE 0x0002U /*!<Capture/Compare 1 interrupt enable */
+#define TIM_DIER_CC2IE 0x0004U /*!<Capture/Compare 2 interrupt enable */
+#define TIM_DIER_CC3IE 0x0008U /*!<Capture/Compare 3 interrupt enable */
+#define TIM_DIER_CC4IE 0x0010U /*!<Capture/Compare 4 interrupt enable */
+#define TIM_DIER_COMIE 0x0020U /*!<COM interrupt enable */
+#define TIM_DIER_TIE 0x0040U /*!<Trigger interrupt enable */
+#define TIM_DIER_BIE 0x0080U /*!<Break interrupt enable */
+#define TIM_DIER_UDE 0x0100U /*!<Update DMA request enable */
+#define TIM_DIER_CC1DE 0x0200U /*!<Capture/Compare 1 DMA request enable */
+#define TIM_DIER_CC2DE 0x0400U /*!<Capture/Compare 2 DMA request enable */
+#define TIM_DIER_CC3DE 0x0800U /*!<Capture/Compare 3 DMA request enable */
+#define TIM_DIER_CC4DE 0x1000U /*!<Capture/Compare 4 DMA request enable */
+#define TIM_DIER_COMDE 0x2000U /*!<COM DMA request enable */
+#define TIM_DIER_TDE 0x4000U /*!<Trigger DMA request enable */
+
+/******************** Bit definition for TIM_SR register ********************/
+#define TIM_SR_UIF 0x0001U /*!<Update interrupt Flag */
+#define TIM_SR_CC1IF 0x0002U /*!<Capture/Compare 1 interrupt Flag */
+#define TIM_SR_CC2IF 0x0004U /*!<Capture/Compare 2 interrupt Flag */
+#define TIM_SR_CC3IF 0x0008U /*!<Capture/Compare 3 interrupt Flag */
+#define TIM_SR_CC4IF 0x0010U /*!<Capture/Compare 4 interrupt Flag */
+#define TIM_SR_COMIF 0x0020U /*!<COM interrupt Flag */
+#define TIM_SR_TIF 0x0040U /*!<Trigger interrupt Flag */
+#define TIM_SR_BIF 0x0080U /*!<Break interrupt Flag */
+#define TIM_SR_CC1OF 0x0200U /*!<Capture/Compare 1 Overcapture Flag */
+#define TIM_SR_CC2OF 0x0400U /*!<Capture/Compare 2 Overcapture Flag */
+#define TIM_SR_CC3OF 0x0800U /*!<Capture/Compare 3 Overcapture Flag */
+#define TIM_SR_CC4OF 0x1000U /*!<Capture/Compare 4 Overcapture Flag */
+
+/******************* Bit definition for TIM_EGR register ********************/
+#define TIM_EGR_UG 0x01U /*!<Update Generation */
+#define TIM_EGR_CC1G 0x02U /*!<Capture/Compare 1 Generation */
+#define TIM_EGR_CC2G 0x04U /*!<Capture/Compare 2 Generation */
+#define TIM_EGR_CC3G 0x08U /*!<Capture/Compare 3 Generation */
+#define TIM_EGR_CC4G 0x10U /*!<Capture/Compare 4 Generation */
+#define TIM_EGR_COMG 0x20U /*!<Capture/Compare Control Update Generation */
+#define TIM_EGR_TG 0x40U /*!<Trigger Generation */
+#define TIM_EGR_BG 0x80U /*!<Break Generation */
+
+/****************** Bit definition for TIM_CCMR1 register *******************/
+#define TIM_CCMR1_CC1S 0x0003U /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
+#define TIM_CCMR1_CC1S_0 0x0001U /*!<Bit 0 */
+#define TIM_CCMR1_CC1S_1 0x0002U /*!<Bit 1 */
+
+#define TIM_CCMR1_OC1FE 0x0004U /*!<Output Compare 1 Fast enable */
+#define TIM_CCMR1_OC1PE 0x0008U /*!<Output Compare 1 Preload enable */
+
+#define TIM_CCMR1_OC1M 0x0070U /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
+#define TIM_CCMR1_OC1M_0 0x0010U /*!<Bit 0 */
+#define TIM_CCMR1_OC1M_1 0x0020U /*!<Bit 1 */
+#define TIM_CCMR1_OC1M_2 0x0040U /*!<Bit 2 */
+
+#define TIM_CCMR1_OC1CE 0x0080U /*!<Output Compare 1Clear Enable */
+
+#define TIM_CCMR1_CC2S 0x0300U /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
+#define TIM_CCMR1_CC2S_0 0x0100U /*!<Bit 0 */
+#define TIM_CCMR1_CC2S_1 0x0200U /*!<Bit 1 */
+
+#define TIM_CCMR1_OC2FE 0x0400U /*!<Output Compare 2 Fast enable */
+#define TIM_CCMR1_OC2PE 0x0800U /*!<Output Compare 2 Preload enable */
+
+#define TIM_CCMR1_OC2M 0x7000U /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
+#define TIM_CCMR1_OC2M_0 0x1000U /*!<Bit 0 */
+#define TIM_CCMR1_OC2M_1 0x2000U /*!<Bit 1 */
+#define TIM_CCMR1_OC2M_2 0x4000U /*!<Bit 2 */
+
+#define TIM_CCMR1_OC2CE 0x8000U /*!<Output Compare 2 Clear Enable */
+
+/*----------------------------------------------------------------------------*/
+
+#define TIM_CCMR1_IC1PSC 0x000CU /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
+#define TIM_CCMR1_IC1PSC_0 0x0004U /*!<Bit 0 */
+#define TIM_CCMR1_IC1PSC_1 0x0008U /*!<Bit 1 */
+
+#define TIM_CCMR1_IC1F 0x00F0U /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
+#define TIM_CCMR1_IC1F_0 0x0010U /*!<Bit 0 */
+#define TIM_CCMR1_IC1F_1 0x0020U /*!<Bit 1 */
+#define TIM_CCMR1_IC1F_2 0x0040U /*!<Bit 2 */
+#define TIM_CCMR1_IC1F_3 0x0080U /*!<Bit 3 */
+
+#define TIM_CCMR1_IC2PSC 0x0C00U /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
+#define TIM_CCMR1_IC2PSC_0 0x0400U /*!<Bit 0 */
+#define TIM_CCMR1_IC2PSC_1 0x0800U /*!<Bit 1 */
+
+#define TIM_CCMR1_IC2F 0xF000U /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
+#define TIM_CCMR1_IC2F_0 0x1000U /*!<Bit 0 */
+#define TIM_CCMR1_IC2F_1 0x2000U /*!<Bit 1 */
+#define TIM_CCMR1_IC2F_2 0x4000U /*!<Bit 2 */
+#define TIM_CCMR1_IC2F_3 0x8000U /*!<Bit 3 */
+
+/****************** Bit definition for TIM_CCMR2 register *******************/
+#define TIM_CCMR2_CC3S 0x0003U /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
+#define TIM_CCMR2_CC3S_0 0x0001U /*!<Bit 0 */
+#define TIM_CCMR2_CC3S_1 0x0002U /*!<Bit 1 */
+
+#define TIM_CCMR2_OC3FE 0x0004U /*!<Output Compare 3 Fast enable */
+#define TIM_CCMR2_OC3PE 0x0008U /*!<Output Compare 3 Preload enable */
+
+#define TIM_CCMR2_OC3M 0x0070U /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
+#define TIM_CCMR2_OC3M_0 0x0010U /*!<Bit 0 */
+#define TIM_CCMR2_OC3M_1 0x0020U /*!<Bit 1 */
+#define TIM_CCMR2_OC3M_2 0x0040U /*!<Bit 2 */
+
+#define TIM_CCMR2_OC3CE 0x0080U /*!<Output Compare 3 Clear Enable */
+
+#define TIM_CCMR2_CC4S 0x0300U /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
+#define TIM_CCMR2_CC4S_0 0x0100U /*!<Bit 0 */
+#define TIM_CCMR2_CC4S_1 0x0200U /*!<Bit 1 */
+
+#define TIM_CCMR2_OC4FE 0x0400U /*!<Output Compare 4 Fast enable */
+#define TIM_CCMR2_OC4PE 0x0800U /*!<Output Compare 4 Preload enable */
+
+#define TIM_CCMR2_OC4M 0x7000U /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
+#define TIM_CCMR2_OC4M_0 0x1000U /*!<Bit 0 */
+#define TIM_CCMR2_OC4M_1 0x2000U /*!<Bit 1 */
+#define TIM_CCMR2_OC4M_2 0x4000U /*!<Bit 2 */
+
+#define TIM_CCMR2_OC4CE 0x8000U /*!<Output Compare 4 Clear Enable */
+
+/*----------------------------------------------------------------------------*/
+
+#define TIM_CCMR2_IC3PSC 0x000CU /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
+#define TIM_CCMR2_IC3PSC_0 0x0004U /*!<Bit 0 */
+#define TIM_CCMR2_IC3PSC_1 0x0008U /*!<Bit 1 */
+
+#define TIM_CCMR2_IC3F 0x00F0U /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
+#define TIM_CCMR2_IC3F_0 0x0010U /*!<Bit 0 */
+#define TIM_CCMR2_IC3F_1 0x0020U /*!<Bit 1 */
+#define TIM_CCMR2_IC3F_2 0x0040U /*!<Bit 2 */
+#define TIM_CCMR2_IC3F_3 0x0080U /*!<Bit 3 */
+
+#define TIM_CCMR2_IC4PSC 0x0C00U /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
+#define TIM_CCMR2_IC4PSC_0 0x0400U /*!<Bit 0 */
+#define TIM_CCMR2_IC4PSC_1 0x0800U /*!<Bit 1 */
+
+#define TIM_CCMR2_IC4F 0xF000U /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
+#define TIM_CCMR2_IC4F_0 0x1000U /*!<Bit 0 */
+#define TIM_CCMR2_IC4F_1 0x2000U /*!<Bit 1 */
+#define TIM_CCMR2_IC4F_2 0x4000U /*!<Bit 2 */
+#define TIM_CCMR2_IC4F_3 0x8000U /*!<Bit 3 */
+
+/******************* Bit definition for TIM_CCER register *******************/
+#define TIM_CCER_CC1E 0x0001U /*!<Capture/Compare 1 output enable */
+#define TIM_CCER_CC1P 0x0002U /*!<Capture/Compare 1 output Polarity */
+#define TIM_CCER_CC1NE 0x0004U /*!<Capture/Compare 1 Complementary output enable */
+#define TIM_CCER_CC1NP 0x0008U /*!<Capture/Compare 1 Complementary output Polarity */
+#define TIM_CCER_CC2E 0x0010U /*!<Capture/Compare 2 output enable */
+#define TIM_CCER_CC2P 0x0020U /*!<Capture/Compare 2 output Polarity */
+#define TIM_CCER_CC2NE 0x0040U /*!<Capture/Compare 2 Complementary output enable */
+#define TIM_CCER_CC2NP 0x0080U /*!<Capture/Compare 2 Complementary output Polarity */
+#define TIM_CCER_CC3E 0x0100U /*!<Capture/Compare 3 output enable */
+#define TIM_CCER_CC3P 0x0200U /*!<Capture/Compare 3 output Polarity */
+#define TIM_CCER_CC3NE 0x0400U /*!<Capture/Compare 3 Complementary output enable */
+#define TIM_CCER_CC3NP 0x0800U /*!<Capture/Compare 3 Complementary output Polarity */
+#define TIM_CCER_CC4E 0x1000U /*!<Capture/Compare 4 output enable */
+#define TIM_CCER_CC4P 0x2000U /*!<Capture/Compare 4 output Polarity */
+#define TIM_CCER_CC4NP 0x8000U /*!<Capture/Compare 4 Complementary output Polarity */
+
+/******************* Bit definition for TIM_CNT register ********************/
+#define TIM_CNT_CNT 0xFFFFU /*!<Counter Value */
+
+/******************* Bit definition for TIM_PSC register ********************/
+#define TIM_PSC_PSC 0xFFFFU /*!<Prescaler Value */
+
+/******************* Bit definition for TIM_ARR register ********************/
+#define TIM_ARR_ARR 0xFFFFU /*!<actual auto-reload Value */
+
+/******************* Bit definition for TIM_RCR register ********************/
+#define TIM_RCR_REP 0xFFU /*!<Repetition Counter Value */
+
+/******************* Bit definition for TIM_CCR1 register *******************/
+#define TIM_CCR1_CCR1 0xFFFFU /*!<Capture/Compare 1 Value */
+
+/******************* Bit definition for TIM_CCR2 register *******************/
+#define TIM_CCR2_CCR2 0xFFFFU /*!<Capture/Compare 2 Value */
+
+/******************* Bit definition for TIM_CCR3 register *******************/
+#define TIM_CCR3_CCR3 0xFFFFU /*!<Capture/Compare 3 Value */
+
+/******************* Bit definition for TIM_CCR4 register *******************/
+#define TIM_CCR4_CCR4 0xFFFFU /*!<Capture/Compare 4 Value */
+
+/******************* Bit definition for TIM_BDTR register *******************/
+#define TIM_BDTR_DTG 0x00FFU /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
+#define TIM_BDTR_DTG_0 0x0001U /*!<Bit 0 */
+#define TIM_BDTR_DTG_1 0x0002U /*!<Bit 1 */
+#define TIM_BDTR_DTG_2 0x0004U /*!<Bit 2 */
+#define TIM_BDTR_DTG_3 0x0008U /*!<Bit 3 */
+#define TIM_BDTR_DTG_4 0x0010U /*!<Bit 4 */
+#define TIM_BDTR_DTG_5 0x0020U /*!<Bit 5 */
+#define TIM_BDTR_DTG_6 0x0040U /*!<Bit 6 */
+#define TIM_BDTR_DTG_7 0x0080U /*!<Bit 7 */
+
+#define TIM_BDTR_LOCK 0x0300U /*!<LOCK[1:0] bits (Lock Configuration) */
+#define TIM_BDTR_LOCK_0 0x0100U /*!<Bit 0 */
+#define TIM_BDTR_LOCK_1 0x0200U /*!<Bit 1 */
+
+#define TIM_BDTR_OSSI 0x0400U /*!<Off-State Selection for Idle mode */
+#define TIM_BDTR_OSSR 0x0800U /*!<Off-State Selection for Run mode */
+#define TIM_BDTR_BKE 0x1000U /*!<Break enable */
+#define TIM_BDTR_BKP 0x2000U /*!<Break Polarity */
+#define TIM_BDTR_AOE 0x4000U /*!<Automatic Output enable */
+#define TIM_BDTR_MOE 0x8000U /*!<Main Output enable */
+
+/******************* Bit definition for TIM_DCR register ********************/
+#define TIM_DCR_DBA 0x001FU /*!<DBA[4:0] bits (DMA Base Address) */
+#define TIM_DCR_DBA_0 0x0001U /*!<Bit 0 */
+#define TIM_DCR_DBA_1 0x0002U /*!<Bit 1 */
+#define TIM_DCR_DBA_2 0x0004U /*!<Bit 2 */
+#define TIM_DCR_DBA_3 0x0008U /*!<Bit 3 */
+#define TIM_DCR_DBA_4 0x0010U /*!<Bit 4 */
+
+#define TIM_DCR_DBL 0x1F00U /*!<DBL[4:0] bits (DMA Burst Length) */
+#define TIM_DCR_DBL_0 0x0100U /*!<Bit 0 */
+#define TIM_DCR_DBL_1 0x0200U /*!<Bit 1 */
+#define TIM_DCR_DBL_2 0x0400U /*!<Bit 2 */
+#define TIM_DCR_DBL_3 0x0800U /*!<Bit 3 */
+#define TIM_DCR_DBL_4 0x1000U /*!<Bit 4 */
+
+/******************* Bit definition for TIM_DMAR register *******************/
+#define TIM_DMAR_DMAB 0xFFFFU /*!<DMA register for burst accesses */
+
+/******************* Bit definition for TIM_OR register *********************/
+#define TIM_OR_TI4_RMP 0x00C0U /*!<TI4_RMP[1:0] bits (TIM5 Input 4 remap) */
+#define TIM_OR_TI4_RMP_0 0x0040U /*!<Bit 0 */
+#define TIM_OR_TI4_RMP_1 0x0080U /*!<Bit 1 */
+
+/******************************************************************************/
+/* */
+/* Low Power Timer (LPTIM) */
+/* */
+/******************************************************************************/
+/****************** Bit definition for LPTIM_ISR register *******************/
+#define LPTIM_ISR_CMPM 0x00000001U /*!< Compare match */
+#define LPTIM_ISR_ARRM 0x00000002U /*!< Autoreload match */
+#define LPTIM_ISR_EXTTRIG 0x00000004U /*!< External trigger edge event */
+#define LPTIM_ISR_CMPOK 0x00000008U /*!< Compare register update OK */
+#define LPTIM_ISR_ARROK 0x00000010U /*!< Autoreload register update OK */
+#define LPTIM_ISR_UP 0x00000020U /*!< Counter direction change down to up */
+#define LPTIM_ISR_DOWN 0x00000040U /*!< Counter direction change up to down */
+
+/****************** Bit definition for LPTIM_ICR register *******************/
+#define LPTIM_ICR_CMPMCF 0x00000001U /*!< Compare match Clear Flag */
+#define LPTIM_ICR_ARRMCF 0x00000002U /*!< Autoreload match Clear Flag */
+#define LPTIM_ICR_EXTTRIGCF 0x00000004U /*!< External trigger edge event Clear Flag */
+#define LPTIM_ICR_CMPOKCF 0x00000008U /*!< Compare register update OK Clear Flag */
+#define LPTIM_ICR_ARROKCF 0x00000010U /*!< Autoreload register update OK Clear Flag */
+#define LPTIM_ICR_UPCF 0x00000020U /*!< Counter direction change down to up Clear Flag */
+#define LPTIM_ICR_DOWNCF 0x00000040U /*!< Counter direction change up to down Clear Flag */
+
+/****************** Bit definition for LPTIM_IER register ********************/
+#define LPTIM_IER_CMPMIE 0x00000001U /*!< Compare match Interrupt Enable */
+#define LPTIM_IER_ARRMIE 0x00000002U /*!< Autoreload match Interrupt Enable */
+#define LPTIM_IER_EXTTRIGIE 0x00000004U /*!< External trigger edge event Interrupt Enable */
+#define LPTIM_IER_CMPOKIE 0x00000008U /*!< Compare register update OK Interrupt Enable */
+#define LPTIM_IER_ARROKIE 0x00000010U /*!< Autoreload register update OK Interrupt Enable */
+#define LPTIM_IER_UPIE 0x00000020U /*!< Counter direction change down to up Interrupt Enable */
+#define LPTIM_IER_DOWNIE 0x00000040U /*!< Counter direction change up to down Interrupt Enable */
+
+/****************** Bit definition for LPTIM_CFGR register *******************/
+#define LPTIM_CFGR_CKSEL 0x00000001U /*!< Clock selector */
+
+#define LPTIM_CFGR_CKPOL 0x00000006U /*!< CKPOL[1:0] bits (Clock polarity) */
+#define LPTIM_CFGR_CKPOL_0 0x00000002U /*!< Bit 0 */
+#define LPTIM_CFGR_CKPOL_1 0x00000004U /*!< Bit 1 */
+
+#define LPTIM_CFGR_CKFLT 0x00000018U /*!< CKFLT[1:0] bits (Configurable digital filter for external clock) */
+#define LPTIM_CFGR_CKFLT_0 0x00000008U /*!< Bit 0 */
+#define LPTIM_CFGR_CKFLT_1 0x00000010U /*!< Bit 1 */
+
+#define LPTIM_CFGR_TRGFLT 0x000000C0U /*!< TRGFLT[1:0] bits (Configurable digital filter for trigger) */
+#define LPTIM_CFGR_TRGFLT_0 0x00000040U /*!< Bit 0 */
+#define LPTIM_CFGR_TRGFLT_1 0x00000080U /*!< Bit 1 */
+
+#define LPTIM_CFGR_PRESC 0x00000E00U /*!< PRESC[2:0] bits (Clock prescaler) */
+#define LPTIM_CFGR_PRESC_0 0x00000200U /*!< Bit 0 */
+#define LPTIM_CFGR_PRESC_1 0x00000400U /*!< Bit 1 */
+#define LPTIM_CFGR_PRESC_2 0x00000800U /*!< Bit 2 */
+
+#define LPTIM_CFGR_TRIGSEL 0x0000E000U /*!< TRIGSEL[2:0]] bits (Trigger selector) */
+#define LPTIM_CFGR_TRIGSEL_0 0x00002000U /*!< Bit 0 */
+#define LPTIM_CFGR_TRIGSEL_1 0x00004000U /*!< Bit 1 */
+#define LPTIM_CFGR_TRIGSEL_2 0x00008000U /*!< Bit 2 */
+
+#define LPTIM_CFGR_TRIGEN 0x00060000U /*!< TRIGEN[1:0] bits (Trigger enable and polarity) */
+#define LPTIM_CFGR_TRIGEN_0 0x00020000U /*!< Bit 0 */
+#define LPTIM_CFGR_TRIGEN_1 0x00040000U /*!< Bit 1 */
+
+#define LPTIM_CFGR_TIMOUT 0x00080000U /*!< Timout enable */
+#define LPTIM_CFGR_WAVE 0x00100000U /*!< Waveform shape */
+#define LPTIM_CFGR_WAVPOL 0x00200000U /*!< Waveform shape polarity */
+#define LPTIM_CFGR_PRELOAD 0x00400000U /*!< Reg update mode */
+#define LPTIM_CFGR_COUNTMODE 0x00800000U /*!< Counter mode enable */
+#define LPTIM_CFGR_ENC 0x01000000U /*!< Encoder mode enable */
+
+/****************** Bit definition for LPTIM_CR register ********************/
+#define LPTIM_CR_ENABLE 0x00000001U /*!< LPTIMer enable */
+#define LPTIM_CR_SNGSTRT 0x00000002U /*!< Timer start in single mode */
+#define LPTIM_CR_CNTSTRT 0x00000004U /*!< Timer start in continuous mode */
+
+/****************** Bit definition for LPTIM_CMP register *******************/
+#define LPTIM_CMP_CMP 0x0000FFFFU /*!< Compare register */
+
+/****************** Bit definition for LPTIM_ARR register *******************/
+#define LPTIM_ARR_ARR 0x0000FFFFU /*!< Auto reload register */
+
+/****************** Bit definition for LPTIM_CNT register *******************/
+#define LPTIM_CNT_CNT 0x0000FFFFU /*!< Counter register */
+
+/****************** Bit definition for LPTIM_OR register *******************/
+#define LPTIM_OR_OR 0x00000003U /*!< LPTIMER[1:0] bits (Remap selection) */
+#define LPTIM_OR_OR_0 0x00000001U /*!< Bit 0 */
+#define LPTIM_OR_OR_1 0x00000002U /*!< Bit 1 */
+
+/******************************************************************************/
+/* */
+/* Universal Synchronous Asynchronous Receiver Transmitter */
+/* */
+/******************************************************************************/
+/******************* Bit definition for USART_SR register *******************/
+#define USART_SR_PE 0x0001U /*!<Parity Error */
+#define USART_SR_FE 0x0002U /*!<Framing Error */
+#define USART_SR_NE 0x0004U /*!<Noise Error Flag */
+#define USART_SR_ORE 0x0008U /*!<OverRun Error */
+#define USART_SR_IDLE 0x0010U /*!<IDLE line detected */
+#define USART_SR_RXNE 0x0020U /*!<Read Data Register Not Empty */
+#define USART_SR_TC 0x0040U /*!<Transmission Complete */
+#define USART_SR_TXE 0x0080U /*!<Transmit Data Register Empty */
+#define USART_SR_LBD 0x0100U /*!<LIN Break Detection Flag */
+#define USART_SR_CTS 0x0200U /*!<CTS Flag */
+
+/******************* Bit definition for USART_DR register *******************/
+#define USART_DR_DR 0x01FFU /*!<Data value */
+
+/****************** Bit definition for USART_BRR register *******************/
+#define USART_BRR_DIV_Fraction 0x000FU /*!<Fraction of USARTDIV */
+#define USART_BRR_DIV_Mantissa 0xFFF0U /*!<Mantissa of USARTDIV */
+
+/****************** Bit definition for USART_CR1 register *******************/
+#define USART_CR1_SBK 0x0001U /*!<Send Break */
+#define USART_CR1_RWU 0x0002U /*!<Receiver wakeup */
+#define USART_CR1_RE 0x0004U /*!<Receiver Enable */
+#define USART_CR1_TE 0x0008U /*!<Transmitter Enable */
+#define USART_CR1_IDLEIE 0x0010U /*!<IDLE Interrupt Enable */
+#define USART_CR1_RXNEIE 0x0020U /*!<RXNE Interrupt Enable */
+#define USART_CR1_TCIE 0x0040U /*!<Transmission Complete Interrupt Enable */
+#define USART_CR1_TXEIE 0x0080U /*!<PE Interrupt Enable */
+#define USART_CR1_PEIE 0x0100U /*!<PE Interrupt Enable */
+#define USART_CR1_PS 0x0200U /*!<Parity Selection */
+#define USART_CR1_PCE 0x0400U /*!<Parity Control Enable */
+#define USART_CR1_WAKE 0x0800U /*!<Wakeup method */
+#define USART_CR1_M 0x1000U /*!<Word length */
+#define USART_CR1_UE 0x2000U /*!<USART Enable */
+#define USART_CR1_OVER8 0x8000U /*!<USART Oversampling by 8 enable */
+
+/****************** Bit definition for USART_CR2 register *******************/
+#define USART_CR2_ADD 0x000FU /*!<Address of the USART node */
+#define USART_CR2_LBDL 0x0020U /*!<LIN Break Detection Length */
+#define USART_CR2_LBDIE 0x0040U /*!<LIN Break Detection Interrupt Enable */
+#define USART_CR2_LBCL 0x0100U /*!<Last Bit Clock pulse */
+#define USART_CR2_CPHA 0x0200U /*!<Clock Phase */
+#define USART_CR2_CPOL 0x0400U /*!<Clock Polarity */
+#define USART_CR2_CLKEN 0x0800U /*!<Clock Enable */
+
+#define USART_CR2_STOP 0x3000U /*!<STOP[1:0] bits (STOP bits) */
+#define USART_CR2_STOP_0 0x1000U /*!<Bit 0 */
+#define USART_CR2_STOP_1 0x2000U /*!<Bit 1 */
+
+#define USART_CR2_LINEN 0x4000U /*!<LIN mode enable */
+
+/****************** Bit definition for USART_CR3 register *******************/
+#define USART_CR3_EIE 0x0001U /*!<Error Interrupt Enable */
+#define USART_CR3_IREN 0x0002U /*!<IrDA mode Enable */
+#define USART_CR3_IRLP 0x0004U /*!<IrDA Low-Power */
+#define USART_CR3_HDSEL 0x0008U /*!<Half-Duplex Selection */
+#define USART_CR3_NACK 0x0010U /*!<Smartcard NACK enable */
+#define USART_CR3_SCEN 0x0020U /*!<Smartcard mode enable */
+#define USART_CR3_DMAR 0x0040U /*!<DMA Enable Receiver */
+#define USART_CR3_DMAT 0x0080U /*!<DMA Enable Transmitter */
+#define USART_CR3_RTSE 0x0100U /*!<RTS Enable */
+#define USART_CR3_CTSE 0x0200U /*!<CTS Enable */
+#define USART_CR3_CTSIE 0x0400U /*!<CTS Interrupt Enable */
+#define USART_CR3_ONEBIT 0x0800U /*!<USART One bit method enable */
+
+/****************** Bit definition for USART_GTPR register ******************/
+#define USART_GTPR_PSC 0x00FFU /*!<PSC[7:0] bits (Prescaler value) */
+#define USART_GTPR_PSC_0 0x0001U /*!<Bit 0 */
+#define USART_GTPR_PSC_1 0x0002U /*!<Bit 1 */
+#define USART_GTPR_PSC_2 0x0004U /*!<Bit 2 */
+#define USART_GTPR_PSC_3 0x0008U /*!<Bit 3 */
+#define USART_GTPR_PSC_4 0x0010U /*!<Bit 4 */
+#define USART_GTPR_PSC_5 0x0020U /*!<Bit 5 */
+#define USART_GTPR_PSC_6 0x0040U /*!<Bit 6 */
+#define USART_GTPR_PSC_7 0x0080U /*!<Bit 7 */
+
+#define USART_GTPR_GT 0xFF00U /*!<Guard time value */
+
+/******************************************************************************/
+/* */
+/* Window WATCHDOG */
+/* */
+/******************************************************************************/
+/******************* Bit definition for WWDG_CR register ********************/
+#define WWDG_CR_T 0x7FU /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
+#define WWDG_CR_T_0 0x01U /*!<Bit 0 */
+#define WWDG_CR_T_1 0x02U /*!<Bit 1 */
+#define WWDG_CR_T_2 0x04U /*!<Bit 2 */
+#define WWDG_CR_T_3 0x08U /*!<Bit 3 */
+#define WWDG_CR_T_4 0x10U /*!<Bit 4 */
+#define WWDG_CR_T_5 0x20U /*!<Bit 5 */
+#define WWDG_CR_T_6 0x40U /*!<Bit 6 */
+/* Legacy defines */
+#define WWDG_CR_T0 WWDG_CR_T_0
+#define WWDG_CR_T1 WWDG_CR_T_1
+#define WWDG_CR_T2 WWDG_CR_T_2
+#define WWDG_CR_T3 WWDG_CR_T_3
+#define WWDG_CR_T4 WWDG_CR_T_4
+#define WWDG_CR_T5 WWDG_CR_T_5
+#define WWDG_CR_T6 WWDG_CR_T_6
+
+#define WWDG_CR_WDGA 0x80U /*!<Activation bit */
+
+/******************* Bit definition for WWDG_CFR register *******************/
+#define WWDG_CFR_W 0x007FU /*!<W[6:0] bits (7-bit window value) */
+#define WWDG_CFR_W_0 0x0001U /*!<Bit 0 */
+#define WWDG_CFR_W_1 0x0002U /*!<Bit 1 */
+#define WWDG_CFR_W_2 0x0004U /*!<Bit 2 */
+#define WWDG_CFR_W_3 0x0008U /*!<Bit 3 */
+#define WWDG_CFR_W_4 0x0010U /*!<Bit 4 */
+#define WWDG_CFR_W_5 0x0020U /*!<Bit 5 */
+#define WWDG_CFR_W_6 0x0040U /*!<Bit 6 */
+/* Legacy defines */
+#define WWDG_CFR_W0 WWDG_CFR_W_0
+#define WWDG_CFR_W1 WWDG_CFR_W_1
+#define WWDG_CFR_W2 WWDG_CFR_W_2
+#define WWDG_CFR_W3 WWDG_CFR_W_3
+#define WWDG_CFR_W4 WWDG_CFR_W_4
+#define WWDG_CFR_W5 WWDG_CFR_W_5
+#define WWDG_CFR_W6 WWDG_CFR_W_6
+
+#define WWDG_CFR_WDGTB 0x0180U /*!<WDGTB[1:0] bits (Timer Base) */
+#define WWDG_CFR_WDGTB_0 0x0080U /*!<Bit 0 */
+#define WWDG_CFR_WDGTB_1 0x0100U /*!<Bit 1 */
+/* Legacy defines */
+#define WWDG_CFR_WDGTB0 WWDG_CFR_WDGTB_0
+#define WWDG_CFR_WDGTB1 WWDG_CFR_WDGTB_1
+
+#define WWDG_CFR_EWI 0x0200U /*!<Early Wakeup Interrupt */
+
+/******************* Bit definition for WWDG_SR register ********************/
+#define WWDG_SR_EWIF 0x01U /*!<Early Wakeup Interrupt Flag */
+
+/******************************************************************************/
+/* */
+/* Digital to Analog Converter */
+/* */
+/******************************************************************************/
+/******************** Bit definition for DAC_CR register ********************/
+#define DAC_CR_EN1 0x00000001U /*!<DAC channel1 enable */
+#define DAC_CR_BOFF1 0x00000002U /*!<DAC channel1 output buffer disable */
+#define DAC_CR_TEN1 0x00000004U /*!<DAC channel1 Trigger enable */
+
+#define DAC_CR_TSEL1 0x00000038U /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */
+#define DAC_CR_TSEL1_0 0x00000008U /*!<Bit 0 */
+#define DAC_CR_TSEL1_1 0x00000010U /*!<Bit 1 */
+#define DAC_CR_TSEL1_2 0x00000020U /*!<Bit 2 */
+
+#define DAC_CR_WAVE1 0x000000C0U /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
+#define DAC_CR_WAVE1_0 0x00000040U /*!<Bit 0 */
+#define DAC_CR_WAVE1_1 0x00000080U /*!<Bit 1 */
+
+#define DAC_CR_MAMP1 0x00000F00U /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
+#define DAC_CR_MAMP1_0 0x00000100U /*!<Bit 0 */
+#define DAC_CR_MAMP1_1 0x00000200U /*!<Bit 1 */
+#define DAC_CR_MAMP1_2 0x00000400U /*!<Bit 2 */
+#define DAC_CR_MAMP1_3 0x00000800U /*!<Bit 3 */
+
+#define DAC_CR_DMAEN1 0x00001000U /*!<DAC channel1 DMA enable */
+#define DAC_CR_DMAUDRIE1 0x00002000U /*!<DAC channel1 DMA underrun interrupt enable*/
+#define DAC_CR_EN2 0x00010000U /*!<DAC channel2 enable */
+#define DAC_CR_BOFF2 0x00020000U /*!<DAC channel2 output buffer disable */
+#define DAC_CR_TEN2 0x00040000U /*!<DAC channel2 Trigger enable */
+
+#define DAC_CR_TSEL2 0x00380000U /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */
+#define DAC_CR_TSEL2_0 0x00080000U /*!<Bit 0 */
+#define DAC_CR_TSEL2_1 0x00100000U /*!<Bit 1 */
+#define DAC_CR_TSEL2_2 0x00200000U /*!<Bit 2 */
+
+#define DAC_CR_WAVE2 0x00C00000U /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
+#define DAC_CR_WAVE2_0 0x00400000U /*!<Bit 0 */
+#define DAC_CR_WAVE2_1 0x00800000U /*!<Bit 1 */
+
+#define DAC_CR_MAMP2 0x0F000000U /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
+#define DAC_CR_MAMP2_0 0x01000000U /*!<Bit 0 */
+#define DAC_CR_MAMP2_1 0x02000000U /*!<Bit 1 */
+#define DAC_CR_MAMP2_2 0x04000000U /*!<Bit 2 */
+#define DAC_CR_MAMP2_3 0x08000000U /*!<Bit 3 */
+
+#define DAC_CR_DMAEN2 0x10000000U /*!<DAC channel2 DMA enabled */
+#define DAC_CR_DMAUDRIE2 0x20000000U /*!<DAC channel2 DMA underrun interrupt enable*/
+
+/***************** Bit definition for DAC_SWTRIGR register ******************/
+#define DAC_SWTRIGR_SWTRIG1 0x01U /*!<DAC channel1 software trigger */
+#define DAC_SWTRIGR_SWTRIG2 0x02U /*!<DAC channel2 software trigger */
+
+/***************** Bit definition for DAC_DHR12R1 register ******************/
+#define DAC_DHR12R1_DACC1DHR 0x0FFFU /*!<DAC channel1 12-bit Right aligned data */
+
+/***************** Bit definition for DAC_DHR12L1 register ******************/
+#define DAC_DHR12L1_DACC1DHR 0xFFF0U /*!<DAC channel1 12-bit Left aligned data */
+
+/****************** Bit definition for DAC_DHR8R1 register ******************/
+#define DAC_DHR8R1_DACC1DHR 0xFFU /*!<DAC channel1 8-bit Right aligned data */
+
+/***************** Bit definition for DAC_DHR12R2 register ******************/
+#define DAC_DHR12R2_DACC2DHR 0x0FFFU /*!<DAC channel2 12-bit Right aligned data */
+
+/***************** Bit definition for DAC_DHR12L2 register ******************/
+#define DAC_DHR12L2_DACC2DHR 0xFFF0U /*!<DAC channel2 12-bit Left aligned data */
+
+/****************** Bit definition for DAC_DHR8R2 register ******************/
+#define DAC_DHR8R2_DACC2DHR 0xFFU /*!<DAC channel2 8-bit Right aligned data */
+
+/***************** Bit definition for DAC_DHR12RD register ******************/
+#define DAC_DHR12RD_DACC1DHR 0x00000FFFU /*!<DAC channel1 12-bit Right aligned data */
+#define DAC_DHR12RD_DACC2DHR 0x0FFF0000U /*!<DAC channel2 12-bit Right aligned data */
+
+/***************** Bit definition for DAC_DHR12LD register ******************/
+#define DAC_DHR12LD_DACC1DHR 0x0000FFF0U /*!<DAC channel1 12-bit Left aligned data */
+#define DAC_DHR12LD_DACC2DHR 0xFFF00000U /*!<DAC channel2 12-bit Left aligned data */
+
+/****************** Bit definition for DAC_DHR8RD register ******************/
+#define DAC_DHR8RD_DACC1DHR 0x00FFU /*!<DAC channel1 8-bit Right aligned data */
+#define DAC_DHR8RD_DACC2DHR 0xFF00U /*!<DAC channel2 8-bit Right aligned data */
+
+/******************* Bit definition for DAC_DOR1 register *******************/
+#define DAC_DOR1_DACC1DOR 0x0FFFU /*!<DAC channel1 data output */
+
+/******************* Bit definition for DAC_DOR2 register *******************/
+#define DAC_DOR2_DACC2DOR 0x0FFFU /*!<DAC channel2 data output */
+
+/******************** Bit definition for DAC_SR register ********************/
+#define DAC_SR_DMAUDR1 0x00002000U /*!<DAC channel1 DMA underrun flag */
+#define DAC_SR_DMAUDR2 0x20000000U /*!<DAC channel2 DMA underrun flag */
+/******************************************************************************/
+/* */
+/* DBG */
+/* */
+/******************************************************************************/
+/******************** Bit definition for DBGMCU_IDCODE register *************/
+#define DBGMCU_IDCODE_DEV_ID 0x00000FFFU
+#define DBGMCU_IDCODE_REV_ID 0xFFFF0000U
+
+/******************** Bit definition for DBGMCU_CR register *****************/
+#define DBGMCU_CR_DBG_SLEEP 0x00000001U
+#define DBGMCU_CR_DBG_STOP 0x00000002U
+#define DBGMCU_CR_DBG_STANDBY 0x00000004U
+#define DBGMCU_CR_TRACE_IOEN 0x00000020U
+
+#define DBGMCU_CR_TRACE_MODE 0x000000C0U
+#define DBGMCU_CR_TRACE_MODE_0 0x00000040U/*!<Bit 0 */
+#define DBGMCU_CR_TRACE_MODE_1 0x00000080U/*!<Bit 1 */
+
+/******************** Bit definition for DBGMCU_APB1_FZ register ************/
+#define DBGMCU_APB1_FZ_DBG_TIM5_STOP 0x00000008U
+#define DBGMCU_APB1_FZ_DBG_TIM6_STOP 0x00000010U
+#define DBGMCU_APB1_FZ_DBG_RTC_STOP 0x00000400U
+#define DBGMCU_APB1_FZ_DBG_WWDG_STOP 0x00000800U
+#define DBGMCU_APB1_FZ_DBG_IWDG_STOP 0x00001000U
+#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT 0x00200000U
+#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT 0x00400000U
+#define DBGMCU_APB1_FZ_DBG_CAN1_STOP 0x02000000U
+#define DBGMCU_APB1_FZ_DBG_CAN2_STOP 0x04000000U
+
+/******************** Bit definition for DBGMCU_APB2_FZ register ************/
+#define DBGMCU_APB2_FZ_DBG_TIM1_STOP 0x00000001U
+#define DBGMCU_APB2_FZ_DBG_TIM9_STOP 0x00010000U
+#define DBGMCU_APB2_FZ_DBG_TIM11_STOP 0x00040000U
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup Exported_macros
+ * @{
+ */
+
+/******************************* ADC Instances ********************************/
+#define IS_ADC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
+
+/******************************* CRC Instances ********************************/
+#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
+
+/******************************* DAC Instances ********************************/
+#define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC)
+
+/******************************** DMA Instances *******************************/
+#define IS_DMA_STREAM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0) || \
+ ((INSTANCE) == DMA1_Stream1) || \
+ ((INSTANCE) == DMA1_Stream2) || \
+ ((INSTANCE) == DMA1_Stream3) || \
+ ((INSTANCE) == DMA1_Stream4) || \
+ ((INSTANCE) == DMA1_Stream5) || \
+ ((INSTANCE) == DMA1_Stream6) || \
+ ((INSTANCE) == DMA1_Stream7) || \
+ ((INSTANCE) == DMA2_Stream0) || \
+ ((INSTANCE) == DMA2_Stream1) || \
+ ((INSTANCE) == DMA2_Stream2) || \
+ ((INSTANCE) == DMA2_Stream3) || \
+ ((INSTANCE) == DMA2_Stream4) || \
+ ((INSTANCE) == DMA2_Stream5) || \
+ ((INSTANCE) == DMA2_Stream6) || \
+ ((INSTANCE) == DMA2_Stream7))
+
+/******************************* GPIO Instances *******************************/
+#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
+ ((INSTANCE) == GPIOB) || \
+ ((INSTANCE) == GPIOC) || \
+ ((INSTANCE) == GPIOH))
+
+/******************************** I2C Instances *******************************/
+#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
+ ((INSTANCE) == I2C2))
+/******************************** I2S Instances *******************************/
+#define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
+ ((INSTANCE) == SPI2) || \
+ ((INSTANCE) == SPI5))
+
+/******************************* LPTIM Instances ******************************/
+#define IS_LPTIM_INSTANCE(__INSTANCE__) ((__INSTANCE__) == LPTIM1)
+
+/******************************* RNG Instances ********************************/
+#define IS_RNG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RNG)
+
+/****************************** RTC Instances *********************************/
+#define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
+
+/******************************** SPI Instances *******************************/
+#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
+ ((INSTANCE) == SPI2) || \
+ ((INSTANCE) == SPI5))
+/*************************** SPI Extended Instances ***************************/
+#define IS_SPI_ALL_INSTANCE_EXT(INSTANCE) (((INSTANCE) == SPI1) || \
+ ((INSTANCE) == SPI2) || \
+ ((INSTANCE) == SPI5))
+
+/****************** TIM Instances : All supported instances *******************/
+#define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM6) || \
+ ((INSTANCE) == TIM9) || \
+ ((INSTANCE) == TIM11))
+
+/************* TIM Instances : at least 1 capture/compare channel *************/
+#define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM9) || \
+ ((INSTANCE) == TIM11))
+
+/************ TIM Instances : at least 2 capture/compare channels *************/
+#define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM9))
+
+/************ TIM Instances : at least 3 capture/compare channels *************/
+#define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM5))
+
+/************ TIM Instances : at least 4 capture/compare channels *************/
+#define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM5))
+
+/******************** TIM Instances : Advanced-control timers *****************/
+#define IS_TIM_ADVANCED_INSTANCE(INSTANCE) ((INSTANCE) == TIM1)
+
+/******************* TIM Instances : Timer input XOR function *****************/
+#define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM5))
+
+/****************** TIM Instances : DMA requests generation (UDE) *************/
+#define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM6))
+
+/************ TIM Instances : DMA requests generation (CCxDE) *****************/
+#define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM5))
+
+/************ TIM Instances : DMA requests generation (COMDE) *****************/
+#define IS_TIM_CCDMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM5))
+
+/******************** TIM Instances : DMA burst feature ***********************/
+#define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM5))
+
+/****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/
+#define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM6) || \
+ ((INSTANCE) == TIM9))
+
+/*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
+#define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM9))
+
+/********************** TIM Instances : 32 bit Counter ************************/
+#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)(((INSTANCE) == TIM5))
+
+/***************** TIM Instances : external trigger input availabe ************/
+#define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM5))
+
+/****************** TIM Instances : remapping capability **********************/
+#define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM11))
+
+/******************* TIM Instances : output(s) available **********************/
+#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
+ ((((INSTANCE) == TIM1) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM5) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM9) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2))) \
+ || \
+ (((INSTANCE) == TIM11) && \
+ (((CHANNEL) == TIM_CHANNEL_1))))
+
+/************ TIM Instances : complementary output(s) available ***************/
+#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
+ ((((INSTANCE) == TIM1) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3))))
+
+/******************** USART Instances : Synchronous mode **********************/
+#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART6))
+
+/******************** UART Instances : Asynchronous mode **********************/
+#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART6))
+
+/****************** UART Instances : Hardware Flow control ********************/
+#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART6))
+
+/********************* UART Instances : Smard card mode ***********************/
+#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART6))
+
+/*********************** UART Instances : IRDA mode ***************************/
+#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART6))
+
+/****************************** IWDG Instances ********************************/
+#define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
+
+/****************************** WWDG Instances ********************************/
+#define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
+
+/***************************** FMPI2C Instances *******************************/
+#define IS_FMPI2C_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == FMPI2C1)
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* __STM32F410Rx_H */
+
+
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Device/ST/STM32F4xx/Include/stm32f410tx.h b/Device/ST/STM32F4xx/Include/stm32f410tx.h
new file mode 100644
index 0000000..536addc
--- /dev/null
+++ b/Device/ST/STM32F4xx/Include/stm32f410tx.h
@@ -0,0 +1,3967 @@
+/**
+ ******************************************************************************
+ * @file stm32f410tx.h
+ * @author MCD Application Team
+ * @version V2.5.0
+ * @date 22-April-2016
+ * @brief CMSIS STM32F410Tx Device Peripheral Access Layer Header File.
+ *
+ * This file contains:
+ * - Data structures and the address mapping for all peripherals
+ * - peripherals registers declarations and bits definition
+ * - Macros to access peripheral’s registers hardware
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/** @addtogroup CMSIS
+ * @{
+ */
+
+/** @addtogroup stm32f410tx
+ * @{
+ */
+
+#ifndef __STM32F410Tx_H
+#define __STM32F410Tx_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif /* __cplusplus */
+
+
+/** @addtogroup Configuration_section_for_CMSIS
+ * @{
+ */
+
+/**
+ * @brief Configuration of the Cortex-M4 Processor and Core Peripherals
+ */
+#define __CM4_REV 0x0001U /*!< Core revision r0p1 */
+#define __MPU_PRESENT 1U /*!< STM32F4XX provides an MPU */
+#define __NVIC_PRIO_BITS 4U /*!< STM32F4XX uses 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */
+#define __FPU_PRESENT 1U /*!< FPU present */
+
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_interrupt_number_definition
+ * @{
+ */
+
+/**
+ * @brief STM32F4XX Interrupt Number Definition, according to the selected device
+ * in @ref Library_configuration_section
+ */
+typedef enum
+{
+/****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/
+ NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
+ MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */
+ BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */
+ UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */
+ SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */
+ DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */
+ PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */
+ SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */
+/****** STM32 specific Interrupt Numbers **********************************************************************/
+ WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
+ PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */
+ TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */
+ RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */
+ FLASH_IRQn = 4, /*!< FLASH global Interrupt */
+ RCC_IRQn = 5, /*!< RCC global Interrupt */
+ EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */
+ EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */
+ EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */
+ EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */
+ EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */
+ DMA1_Stream0_IRQn = 11, /*!< DMA1 Stream 0 global Interrupt */
+ DMA1_Stream1_IRQn = 12, /*!< DMA1 Stream 1 global Interrupt */
+ DMA1_Stream2_IRQn = 13, /*!< DMA1 Stream 2 global Interrupt */
+ DMA1_Stream3_IRQn = 14, /*!< DMA1 Stream 3 global Interrupt */
+ DMA1_Stream4_IRQn = 15, /*!< DMA1 Stream 4 global Interrupt */
+ DMA1_Stream5_IRQn = 16, /*!< DMA1 Stream 5 global Interrupt */
+ DMA1_Stream6_IRQn = 17, /*!< DMA1 Stream 6 global Interrupt */
+ ADC_IRQn = 18, /*!< ADC1 global Interrupts */
+ EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
+ TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break interrupt and TIM9 global interrupt */
+ TIM1_UP_IRQn = 25, /*!< TIM1 Update Interrupt */
+ TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */
+ TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
+ I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
+ I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
+ I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
+ I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
+ SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
+ USART1_IRQn = 37, /*!< USART1 global Interrupt */
+ USART2_IRQn = 38, /*!< USART2 global Interrupt */
+ EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
+ RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */
+ DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */
+ TIM5_IRQn = 50, /*!< TIM5 global Interrupt */
+ TIM6_DAC_IRQn = 54, /*!< TIM6 global Interrupt and DAC Global Interrupt */
+ DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */
+ DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */
+ DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */
+ DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */
+ DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */
+ DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */
+ DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */
+ DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */
+ RNG_IRQn = 80, /*!< RNG global Interrupt */
+ FPU_IRQn = 81, /*!< FPU global interrupt */
+ FMPI2C1_EV_IRQn = 95, /*!< FMPI2C1 Event Interrupt */
+ FMPI2C1_ER_IRQn = 96, /*!< FMPI2C1 Error Interrupt */
+ LPTIM1_IRQn = 97 /*!< LPTIM1 interrupt */
+} IRQn_Type;
+
+/**
+ * @}
+ */
+
+#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
+#include "system_stm32f4xx.h"
+#include <stdint.h>
+
+/** @addtogroup Peripheral_registers_structures
+ * @{
+ */
+
+/**
+ * @brief Analog to Digital Converter
+ */
+
+typedef struct
+{
+ __IO uint32_t SR; /*!< ADC status register, Address offset: 0x00 */
+ __IO uint32_t CR1; /*!< ADC control register 1, Address offset: 0x04 */
+ __IO uint32_t CR2; /*!< ADC control register 2, Address offset: 0x08 */
+ __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x0C */
+ __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x10 */
+ __IO uint32_t JOFR1; /*!< ADC injected channel data offset register 1, Address offset: 0x14 */
+ __IO uint32_t JOFR2; /*!< ADC injected channel data offset register 2, Address offset: 0x18 */
+ __IO uint32_t JOFR3; /*!< ADC injected channel data offset register 3, Address offset: 0x1C */
+ __IO uint32_t JOFR4; /*!< ADC injected channel data offset register 4, Address offset: 0x20 */
+ __IO uint32_t HTR; /*!< ADC watchdog higher threshold register, Address offset: 0x24 */
+ __IO uint32_t LTR; /*!< ADC watchdog lower threshold register, Address offset: 0x28 */
+ __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x2C */
+ __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x30 */
+ __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x34 */
+ __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x38*/
+ __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x3C */
+ __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x40 */
+ __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x44 */
+ __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x48 */
+ __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x4C */
+} ADC_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1 base address + 0x300 */
+ __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1 base address + 0x304 */
+ __IO uint32_t CDR; /*!< ADC common regular data register for dual
+ AND triple modes, Address offset: ADC1 base address + 0x308 */
+} ADC_Common_TypeDef;
+
+/**
+ * @brief CRC calculation unit
+ */
+
+typedef struct
+{
+ __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
+ __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
+ uint8_t RESERVED0; /*!< Reserved, 0x05 */
+ uint16_t RESERVED1; /*!< Reserved, 0x06 */
+ __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
+} CRC_TypeDef;
+
+/**
+ * @brief Digital to Analog Converter
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */
+ __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */
+ __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
+ __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */
+ __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */
+ __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
+ __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */
+ __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */
+ __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */
+ __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */
+ __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */
+ __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */
+ __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */
+ __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */
+} DAC_TypeDef;
+
+/**
+ * @brief Debug MCU
+ */
+
+typedef struct
+{
+ __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
+ __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
+ __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */
+ __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */
+}DBGMCU_TypeDef;
+
+
+/**
+ * @brief DMA Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< DMA stream x configuration register */
+ __IO uint32_t NDTR; /*!< DMA stream x number of data register */
+ __IO uint32_t PAR; /*!< DMA stream x peripheral address register */
+ __IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */
+ __IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */
+ __IO uint32_t FCR; /*!< DMA stream x FIFO control register */
+} DMA_Stream_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t LISR; /*!< DMA low interrupt status register, Address offset: 0x00 */
+ __IO uint32_t HISR; /*!< DMA high interrupt status register, Address offset: 0x04 */
+ __IO uint32_t LIFCR; /*!< DMA low interrupt flag clear register, Address offset: 0x08 */
+ __IO uint32_t HIFCR; /*!< DMA high interrupt flag clear register, Address offset: 0x0C */
+} DMA_TypeDef;
+
+
+/**
+ * @brief External Interrupt/Event Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t IMR; /*!< EXTI Interrupt mask register, Address offset: 0x00 */
+ __IO uint32_t EMR; /*!< EXTI Event mask register, Address offset: 0x04 */
+ __IO uint32_t RTSR; /*!< EXTI Rising trigger selection register, Address offset: 0x08 */
+ __IO uint32_t FTSR; /*!< EXTI Falling trigger selection register, Address offset: 0x0C */
+ __IO uint32_t SWIER; /*!< EXTI Software interrupt event register, Address offset: 0x10 */
+ __IO uint32_t PR; /*!< EXTI Pending register, Address offset: 0x14 */
+} EXTI_TypeDef;
+
+/**
+ * @brief FLASH Registers
+ */
+
+typedef struct
+{
+ __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */
+ __IO uint32_t KEYR; /*!< FLASH key register, Address offset: 0x04 */
+ __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x08 */
+ __IO uint32_t SR; /*!< FLASH status register, Address offset: 0x0C */
+ __IO uint32_t CR; /*!< FLASH control register, Address offset: 0x10 */
+ __IO uint32_t OPTCR; /*!< FLASH option control register , Address offset: 0x14 */
+ __IO uint32_t OPTCR1; /*!< FLASH option control register 1, Address offset: 0x18 */
+} FLASH_TypeDef;
+
+/**
+ * @brief General Purpose I/O
+ */
+
+typedef struct
+{
+ __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
+ __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */
+ __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */
+ __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
+ __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
+ __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
+ __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */
+ __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
+ __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */
+} GPIO_TypeDef;
+
+/**
+ * @brief System configuration controller
+ */
+
+typedef struct
+{
+ __IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */
+ __IO uint32_t PMC; /*!< SYSCFG peripheral mode configuration register, Address offset: 0x04 */
+ __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
+ uint32_t RESERVED; /*!< Reserved, 0x18 */
+ uint32_t CFGR2; /*!< Reserved, 0x1C */
+ __IO uint32_t CMPCR; /*!< SYSCFG Compensation cell control register, Address offset: 0x20 */
+ uint32_t RESERVED1[2]; /*!< Reserved, 0x24-0x28 */
+ __IO uint32_t CFGR; /*!< SYSCFG Configuration register, Address offset: 0x2C */
+} SYSCFG_TypeDef;
+
+/**
+ * @brief Inter-integrated Circuit Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */
+ __IO uint32_t OAR1; /*!< I2C Own address register 1, Address offset: 0x08 */
+ __IO uint32_t OAR2; /*!< I2C Own address register 2, Address offset: 0x0C */
+ __IO uint32_t DR; /*!< I2C Data register, Address offset: 0x10 */
+ __IO uint32_t SR1; /*!< I2C Status register 1, Address offset: 0x14 */
+ __IO uint32_t SR2; /*!< I2C Status register 2, Address offset: 0x18 */
+ __IO uint32_t CCR; /*!< I2C Clock control register, Address offset: 0x1C */
+ __IO uint32_t TRISE; /*!< I2C TRISE register, Address offset: 0x20 */
+ __IO uint32_t FLTR; /*!< I2C FLTR register, Address offset: 0x24 */
+} I2C_TypeDef;
+
+/**
+ * @brief Inter-integrated Circuit Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t CR1; /*!< FMPI2C Control register 1, Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< FMPI2C Control register 2, Address offset: 0x04 */
+ __IO uint32_t OAR1; /*!< FMPI2C Own address 1 register, Address offset: 0x08 */
+ __IO uint32_t OAR2; /*!< FMPI2C Own address 2 register, Address offset: 0x0C */
+ __IO uint32_t TIMINGR; /*!< FMPI2C Timing register, Address offset: 0x10 */
+ __IO uint32_t TIMEOUTR; /*!< FMPI2C Timeout register, Address offset: 0x14 */
+ __IO uint32_t ISR; /*!< FMPI2C Interrupt and status register, Address offset: 0x18 */
+ __IO uint32_t ICR; /*!< FMPI2C Interrupt clear register, Address offset: 0x1C */
+ __IO uint32_t PECR; /*!< FMPI2C PEC register, Address offset: 0x20 */
+ __IO uint32_t RXDR; /*!< FMPI2C Receive data register, Address offset: 0x24 */
+ __IO uint32_t TXDR; /*!< FMPI2C Transmit data register, Address offset: 0x28 */
+} FMPI2C_TypeDef;
+
+/**
+ * @brief Independent WATCHDOG
+ */
+
+typedef struct
+{
+ __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */
+ __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */
+ __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */
+ __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */
+} IWDG_TypeDef;
+
+/**
+ * @brief Power Control
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */
+ __IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */
+} PWR_TypeDef;
+
+/**
+ * @brief Reset and Clock Control
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */
+ __IO uint32_t PLLCFGR; /*!< RCC PLL configuration register, Address offset: 0x04 */
+ __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x08 */
+ __IO uint32_t CIR; /*!< RCC clock interrupt register, Address offset: 0x0C */
+ __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x10 */
+ uint32_t RESERVED0[3]; /*!< Reserved, 0x14-0x1C */
+ __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x20 */
+ __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x24 */
+ uint32_t RESERVED1[2]; /*!< Reserved, 0x28-0x2C */
+ __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clock register, Address offset: 0x30 */
+ uint32_t RESERVED2[3]; /*!< Reserved, 0x34-0x3C */
+ __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x40 */
+ __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x44 */
+ uint32_t RESERVED3[2]; /*!< Reserved, 0x48-0x4C */
+ __IO uint32_t AHB1LPENR; /*!< RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 */
+ uint32_t RESERVED4[3]; /*!< Reserved, 0x54-0x5C */
+ __IO uint32_t APB1LPENR; /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 */
+ __IO uint32_t APB2LPENR; /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 */
+ uint32_t RESERVED5[2]; /*!< Reserved, 0x68-0x6C */
+ __IO uint32_t BDCR; /*!< RCC Backup domain control register, Address offset: 0x70 */
+ __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x74 */
+ uint32_t RESERVED6[2]; /*!< Reserved, 0x78-0x7C */
+ __IO uint32_t SSCGR; /*!< RCC spread spectrum clock generation register, Address offset: 0x80 */
+ uint32_t RESERVED7[2]; /*!< Reserved, 0x84-0x88 */
+ __IO uint32_t DCKCFGR; /*!< RCC Dedicated Clocks configuration register, Address offset: 0x8C */
+ __IO uint32_t CKGATENR; /*!< RCC Clocks Gated ENable Register, Address offset: 0x90 */
+ __IO uint32_t DCKCFGR2; /*!< RCC Dedicated Clocks configuration register 2, Address offset: 0x94 */
+
+} RCC_TypeDef;
+
+/**
+ * @brief Real-Time Clock
+ */
+
+typedef struct
+{
+ __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
+ __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */
+ __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */
+ __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */
+ __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */
+ __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */
+ __IO uint32_t CALIBR; /*!< RTC calibration register, Address offset: 0x18 */
+ __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */
+ __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */
+ __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */
+ __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */
+ __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */
+ __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */
+ __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */
+ __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */
+ __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */
+ __IO uint32_t TAFCR; /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */
+ __IO uint32_t ALRMASSR;/*!< RTC alarm A sub second register, Address offset: 0x44 */
+ __IO uint32_t ALRMBSSR;/*!< RTC alarm B sub second register, Address offset: 0x48 */
+ uint32_t RESERVED7; /*!< Reserved, 0x4C */
+ __IO uint32_t BKP0R; /*!< RTC backup register 1, Address offset: 0x50 */
+ __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */
+ __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */
+ __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */
+ __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */
+ __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */
+ __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */
+ __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */
+ __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */
+ __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */
+ __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */
+ __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */
+ __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */
+ __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */
+ __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */
+ __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */
+ __IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */
+ __IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */
+ __IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */
+ __IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */
+} RTC_TypeDef;
+
+/**
+ * @brief Serial Peripheral Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t CR1; /*!< SPI control register 1 (not used in I2S mode), Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< SPI control register 2, Address offset: 0x04 */
+ __IO uint32_t SR; /*!< SPI status register, Address offset: 0x08 */
+ __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */
+ __IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
+ __IO uint32_t RXCRCR; /*!< SPI RX CRC register (not used in I2S mode), Address offset: 0x14 */
+ __IO uint32_t TXCRCR; /*!< SPI TX CRC register (not used in I2S mode), Address offset: 0x18 */
+ __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */
+ __IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */
+} SPI_TypeDef;
+
+/**
+ * @brief TIM
+ */
+
+typedef struct
+{
+ __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
+ __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */
+ __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
+ __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
+ __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
+ __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
+ __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
+ __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
+ __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
+ __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */
+ __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
+ __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */
+ __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
+ __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
+ __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
+ __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
+ __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
+ __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
+ __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */
+ __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */
+} TIM_TypeDef;
+
+/**
+ * @brief Universal Synchronous Asynchronous Receiver Transmitter
+ */
+
+typedef struct
+{
+ __IO uint32_t SR; /*!< USART Status register, Address offset: 0x00 */
+ __IO uint32_t DR; /*!< USART Data register, Address offset: 0x04 */
+ __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x08 */
+ __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x0C */
+ __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x10 */
+ __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x14 */
+ __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x18 */
+} USART_TypeDef;
+
+/**
+ * @brief Window WATCHDOG
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
+ __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
+ __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
+} WWDG_TypeDef;
+
+
+/**
+ * @brief RNG
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */
+ __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */
+ __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */
+} RNG_TypeDef;
+
+
+/**
+ * @brief LPTIMER
+ */
+typedef struct
+{
+ __IO uint32_t ISR; /*!< LPTIM Interrupt and Status register, Address offset: 0x00 */
+ __IO uint32_t ICR; /*!< LPTIM Interrupt Clear register, Address offset: 0x04 */
+ __IO uint32_t IER; /*!< LPTIM Interrupt Enable register, Address offset: 0x08 */
+ __IO uint32_t CFGR; /*!< LPTIM Configuration register, Address offset: 0x0C */
+ __IO uint32_t CR; /*!< LPTIM Control register, Address offset: 0x10 */
+ __IO uint32_t CMP; /*!< LPTIM Compare register, Address offset: 0x14 */
+ __IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */
+ __IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */
+ __IO uint32_t OR; /*!< LPTIM Option register, Address offset: 0x20 */
+} LPTIM_TypeDef;
+
+/**
+ * @brief Peripheral_memory_map
+ */
+#define FLASH_BASE 0x08000000U /*!< FLASH(up to 1 MB) base address in the alias region */
+#define SRAM1_BASE 0x20000000U /*!< SRAM1(32 KB) base address in the alias region */
+#define PERIPH_BASE 0x40000000U /*!< Peripheral base address in the alias region */
+#define SRAM1_BB_BASE 0x22000000U /*!< SRAM1(32 KB) base address in the bit-band region */
+#define PERIPH_BB_BASE 0x42000000U /*!< Peripheral base address in the bit-band region */
+#define FLASH_END 0x0801FFFFU /*!< FLASH end address */
+
+/* Legacy defines */
+#define SRAM_BASE SRAM1_BASE
+#define SRAM_BB_BASE SRAM1_BB_BASE
+
+/*!< Peripheral memory map */
+#define APB1PERIPH_BASE PERIPH_BASE
+#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000U)
+#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000U)
+
+/*!< APB1 peripherals */
+#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00U)
+#define TIM6_BASE (APB1PERIPH_BASE + 0x1000U)
+#define LPTIM1_BASE (APB1PERIPH_BASE + 0x2400U)
+#define RTC_BASE (APB1PERIPH_BASE + 0x2800U)
+#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00U)
+#define IWDG_BASE (APB1PERIPH_BASE + 0x3000U)
+#define USART2_BASE (APB1PERIPH_BASE + 0x4400U)
+#define I2C1_BASE (APB1PERIPH_BASE + 0x5400U)
+#define I2C2_BASE (APB1PERIPH_BASE + 0x5800U)
+#define FMPI2C1_BASE (APB1PERIPH_BASE + 0x6000U)
+#define PWR_BASE (APB1PERIPH_BASE + 0x7000U)
+#define DAC_BASE (APB1PERIPH_BASE + 0x7400U)
+/*!< APB2 peripherals */
+#define TIM1_BASE (APB2PERIPH_BASE + 0x0000U)
+#define USART1_BASE (APB2PERIPH_BASE + 0x1000U)
+#define USART6_BASE (APB2PERIPH_BASE + 0x1400U)
+#define ADC1_BASE (APB2PERIPH_BASE + 0x2000U)
+#define ADC_BASE (APB2PERIPH_BASE + 0x2300U)
+#define SPI1_BASE (APB2PERIPH_BASE + 0x3000U)
+#define SYSCFG_BASE (APB2PERIPH_BASE + 0x3800U)
+#define EXTI_BASE (APB2PERIPH_BASE + 0x3C00U)
+#define TIM9_BASE (APB2PERIPH_BASE + 0x4000U)
+#define TIM11_BASE (APB2PERIPH_BASE + 0x4800U)
+
+/*!< AHB1 peripherals */
+#define GPIOA_BASE (AHB1PERIPH_BASE + 0x0000U)
+#define GPIOB_BASE (AHB1PERIPH_BASE + 0x0400U)
+#define GPIOC_BASE (AHB1PERIPH_BASE + 0x0800U)
+#define GPIOH_BASE (AHB1PERIPH_BASE + 0x1C00U)
+#define CRC_BASE (AHB1PERIPH_BASE + 0x3000U)
+#define RCC_BASE (AHB1PERIPH_BASE + 0x3800U)
+#define FLASH_R_BASE (AHB1PERIPH_BASE + 0x3C00U)
+#define DMA1_BASE (AHB1PERIPH_BASE + 0x6000U)
+#define DMA1_Stream0_BASE (DMA1_BASE + 0x010U)
+#define DMA1_Stream1_BASE (DMA1_BASE + 0x028U)
+#define DMA1_Stream2_BASE (DMA1_BASE + 0x040U)
+#define DMA1_Stream3_BASE (DMA1_BASE + 0x058U)
+#define DMA1_Stream4_BASE (DMA1_BASE + 0x070U)
+#define DMA1_Stream5_BASE (DMA1_BASE + 0x088U)
+#define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0U)
+#define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8U)
+#define DMA2_BASE (AHB1PERIPH_BASE + 0x6400U)
+#define DMA2_Stream0_BASE (DMA2_BASE + 0x010U)
+#define DMA2_Stream1_BASE (DMA2_BASE + 0x028U)
+#define DMA2_Stream2_BASE (DMA2_BASE + 0x040U)
+#define DMA2_Stream3_BASE (DMA2_BASE + 0x058U)
+#define DMA2_Stream4_BASE (DMA2_BASE + 0x070U)
+#define DMA2_Stream5_BASE (DMA2_BASE + 0x088U)
+#define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0U)
+#define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8U)
+#define RNG_BASE (PERIPH_BASE + 0x80000U)
+
+/* Debug MCU registers base address */
+#define DBGMCU_BASE 0xE0042000U
+
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_declaration
+ * @{
+ */
+#define TIM5 ((TIM_TypeDef *) TIM5_BASE)
+#define TIM6 ((TIM_TypeDef *) TIM6_BASE)
+#define RTC ((RTC_TypeDef *) RTC_BASE)
+#define WWDG ((WWDG_TypeDef *) WWDG_BASE)
+#define IWDG ((IWDG_TypeDef *) IWDG_BASE)
+#define USART2 ((USART_TypeDef *) USART2_BASE)
+#define I2C1 ((I2C_TypeDef *) I2C1_BASE)
+#define I2C2 ((I2C_TypeDef *) I2C2_BASE)
+#define FMPI2C1 ((FMPI2C_TypeDef *) FMPI2C1_BASE)
+#define LPTIM1 ((LPTIM_TypeDef *) LPTIM1_BASE)
+#define PWR ((PWR_TypeDef *) PWR_BASE)
+#define DAC ((DAC_TypeDef *) DAC_BASE)
+#define TIM1 ((TIM_TypeDef *) TIM1_BASE)
+#define USART1 ((USART_TypeDef *) USART1_BASE)
+#define USART6 ((USART_TypeDef *) USART6_BASE)
+#define ADC ((ADC_Common_TypeDef *) ADC_BASE)
+#define ADC1 ((ADC_TypeDef *) ADC1_BASE)
+#define SPI1 ((SPI_TypeDef *) SPI1_BASE)
+#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
+#define EXTI ((EXTI_TypeDef *) EXTI_BASE)
+#define TIM9 ((TIM_TypeDef *) TIM9_BASE)
+#define TIM11 ((TIM_TypeDef *) TIM11_BASE)
+#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
+#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
+#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
+#define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
+#define CRC ((CRC_TypeDef *) CRC_BASE)
+#define RCC ((RCC_TypeDef *) RCC_BASE)
+#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
+#define DMA1 ((DMA_TypeDef *) DMA1_BASE)
+#define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)
+#define DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)
+#define DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)
+#define DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)
+#define DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)
+#define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)
+#define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)
+#define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)
+#define DMA2 ((DMA_TypeDef *) DMA2_BASE)
+#define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)
+#define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
+#define DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)
+#define DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)
+#define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)
+#define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)
+#define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)
+#define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)
+#define RNG ((RNG_TypeDef *) RNG_BASE)
+
+#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
+
+/**
+ * @}
+ */
+
+/** @addtogroup Exported_constants
+ * @{
+ */
+
+ /** @addtogroup Peripheral_Registers_Bits_Definition
+ * @{
+ */
+
+/******************************************************************************/
+/* Peripheral Registers_Bits_Definition */
+/******************************************************************************/
+
+/******************************************************************************/
+/* */
+/* Analog to Digital Converter */
+/* */
+/******************************************************************************/
+/******************** Bit definition for ADC_SR register ********************/
+#define ADC_SR_AWD 0x00000001U /*!<Analog watchdog flag */
+#define ADC_SR_EOC 0x00000002U /*!<End of conversion */
+#define ADC_SR_JEOC 0x00000004U /*!<Injected channel end of conversion */
+#define ADC_SR_JSTRT 0x00000008U /*!<Injected channel Start flag */
+#define ADC_SR_STRT 0x00000010U /*!<Regular channel Start flag */
+#define ADC_SR_OVR 0x00000020U /*!<Overrun flag */
+
+/******************* Bit definition for ADC_CR1 register ********************/
+#define ADC_CR1_AWDCH 0x0000001FU /*!<AWDCH[4:0] bits (Analog watchdog channel select bits) */
+#define ADC_CR1_AWDCH_0 0x00000001U /*!<Bit 0 */
+#define ADC_CR1_AWDCH_1 0x00000002U /*!<Bit 1 */
+#define ADC_CR1_AWDCH_2 0x00000004U /*!<Bit 2 */
+#define ADC_CR1_AWDCH_3 0x00000008U /*!<Bit 3 */
+#define ADC_CR1_AWDCH_4 0x00000010U /*!<Bit 4 */
+#define ADC_CR1_EOCIE 0x00000020U /*!<Interrupt enable for EOC */
+#define ADC_CR1_AWDIE 0x00000040U /*!<AAnalog Watchdog interrupt enable */
+#define ADC_CR1_JEOCIE 0x00000080U /*!<Interrupt enable for injected channels */
+#define ADC_CR1_SCAN 0x00000100U /*!<Scan mode */
+#define ADC_CR1_AWDSGL 0x00000200U /*!<Enable the watchdog on a single channel in scan mode */
+#define ADC_CR1_JAUTO 0x00000400U /*!<Automatic injected group conversion */
+#define ADC_CR1_DISCEN 0x00000800U /*!<Discontinuous mode on regular channels */
+#define ADC_CR1_JDISCEN 0x00001000U /*!<Discontinuous mode on injected channels */
+#define ADC_CR1_DISCNUM 0x0000E000U /*!<DISCNUM[2:0] bits (Discontinuous mode channel count) */
+#define ADC_CR1_DISCNUM_0 0x00002000U /*!<Bit 0 */
+#define ADC_CR1_DISCNUM_1 0x00004000U /*!<Bit 1 */
+#define ADC_CR1_DISCNUM_2 0x00008000U /*!<Bit 2 */
+#define ADC_CR1_JAWDEN 0x00400000U /*!<Analog watchdog enable on injected channels */
+#define ADC_CR1_AWDEN 0x00800000U /*!<Analog watchdog enable on regular channels */
+#define ADC_CR1_RES 0x03000000U /*!<RES[2:0] bits (Resolution) */
+#define ADC_CR1_RES_0 0x01000000U /*!<Bit 0 */
+#define ADC_CR1_RES_1 0x02000000U /*!<Bit 1 */
+#define ADC_CR1_OVRIE 0x04000000U /*!<overrun interrupt enable */
+
+/******************* Bit definition for ADC_CR2 register ********************/
+#define ADC_CR2_ADON 0x00000001U /*!<A/D Converter ON / OFF */
+#define ADC_CR2_CONT 0x00000002U /*!<Continuous Conversion */
+#define ADC_CR2_DMA 0x00000100U /*!<Direct Memory access mode */
+#define ADC_CR2_DDS 0x00000200U /*!<DMA disable selection (Single ADC) */
+#define ADC_CR2_EOCS 0x00000400U /*!<End of conversion selection */
+#define ADC_CR2_ALIGN 0x00000800U /*!<Data Alignment */
+#define ADC_CR2_JEXTSEL 0x000F0000U /*!<JEXTSEL[3:0] bits (External event select for injected group) */
+#define ADC_CR2_JEXTSEL_0 0x00010000U /*!<Bit 0 */
+#define ADC_CR2_JEXTSEL_1 0x00020000U /*!<Bit 1 */
+#define ADC_CR2_JEXTSEL_2 0x00040000U /*!<Bit 2 */
+#define ADC_CR2_JEXTSEL_3 0x00080000U /*!<Bit 3 */
+#define ADC_CR2_JEXTEN 0x00300000U /*!<JEXTEN[1:0] bits (External Trigger Conversion mode for injected channelsp) */
+#define ADC_CR2_JEXTEN_0 0x00100000U /*!<Bit 0 */
+#define ADC_CR2_JEXTEN_1 0x00200000U /*!<Bit 1 */
+#define ADC_CR2_JSWSTART 0x00400000U /*!<Start Conversion of injected channels */
+#define ADC_CR2_EXTSEL 0x0F000000U /*!<EXTSEL[3:0] bits (External Event Select for regular group) */
+#define ADC_CR2_EXTSEL_0 0x01000000U /*!<Bit 0 */
+#define ADC_CR2_EXTSEL_1 0x02000000U /*!<Bit 1 */
+#define ADC_CR2_EXTSEL_2 0x04000000U /*!<Bit 2 */
+#define ADC_CR2_EXTSEL_3 0x08000000U /*!<Bit 3 */
+#define ADC_CR2_EXTEN 0x30000000U /*!<EXTEN[1:0] bits (External Trigger Conversion mode for regular channelsp) */
+#define ADC_CR2_EXTEN_0 0x10000000U /*!<Bit 0 */
+#define ADC_CR2_EXTEN_1 0x20000000U /*!<Bit 1 */
+#define ADC_CR2_SWSTART 0x40000000U /*!<Start Conversion of regular channels */
+
+/****************** Bit definition for ADC_SMPR1 register *******************/
+#define ADC_SMPR1_SMP10 0x00000007U /*!<SMP10[2:0] bits (Channel 10 Sample time selection) */
+#define ADC_SMPR1_SMP10_0 0x00000001U /*!<Bit 0 */
+#define ADC_SMPR1_SMP10_1 0x00000002U /*!<Bit 1 */
+#define ADC_SMPR1_SMP10_2 0x00000004U /*!<Bit 2 */
+#define ADC_SMPR1_SMP11 0x00000038U /*!<SMP11[2:0] bits (Channel 11 Sample time selection) */
+#define ADC_SMPR1_SMP11_0 0x00000008U /*!<Bit 0 */
+#define ADC_SMPR1_SMP11_1 0x00000010U /*!<Bit 1 */
+#define ADC_SMPR1_SMP11_2 0x00000020U /*!<Bit 2 */
+#define ADC_SMPR1_SMP12 0x000001C0U /*!<SMP12[2:0] bits (Channel 12 Sample time selection) */
+#define ADC_SMPR1_SMP12_0 0x00000040U /*!<Bit 0 */
+#define ADC_SMPR1_SMP12_1 0x00000080U /*!<Bit 1 */
+#define ADC_SMPR1_SMP12_2 0x00000100U /*!<Bit 2 */
+#define ADC_SMPR1_SMP13 0x00000E00U /*!<SMP13[2:0] bits (Channel 13 Sample time selection) */
+#define ADC_SMPR1_SMP13_0 0x00000200U /*!<Bit 0 */
+#define ADC_SMPR1_SMP13_1 0x00000400U /*!<Bit 1 */
+#define ADC_SMPR1_SMP13_2 0x00000800U /*!<Bit 2 */
+#define ADC_SMPR1_SMP14 0x00007000U /*!<SMP14[2:0] bits (Channel 14 Sample time selection) */
+#define ADC_SMPR1_SMP14_0 0x00001000U /*!<Bit 0 */
+#define ADC_SMPR1_SMP14_1 0x00002000U /*!<Bit 1 */
+#define ADC_SMPR1_SMP14_2 0x00004000U /*!<Bit 2 */
+#define ADC_SMPR1_SMP15 0x00038000U /*!<SMP15[2:0] bits (Channel 15 Sample time selection) */
+#define ADC_SMPR1_SMP15_0 0x00008000U /*!<Bit 0 */
+#define ADC_SMPR1_SMP15_1 0x00010000U /*!<Bit 1 */
+#define ADC_SMPR1_SMP15_2 0x00020000U /*!<Bit 2 */
+#define ADC_SMPR1_SMP16 0x001C0000U /*!<SMP16[2:0] bits (Channel 16 Sample time selection) */
+#define ADC_SMPR1_SMP16_0 0x00040000U /*!<Bit 0 */
+#define ADC_SMPR1_SMP16_1 0x00080000U /*!<Bit 1 */
+#define ADC_SMPR1_SMP16_2 0x00100000U /*!<Bit 2 */
+#define ADC_SMPR1_SMP17 0x00E00000U /*!<SMP17[2:0] bits (Channel 17 Sample time selection) */
+#define ADC_SMPR1_SMP17_0 0x00200000U /*!<Bit 0 */
+#define ADC_SMPR1_SMP17_1 0x00400000U /*!<Bit 1 */
+#define ADC_SMPR1_SMP17_2 0x00800000U /*!<Bit 2 */
+#define ADC_SMPR1_SMP18 0x07000000U /*!<SMP18[2:0] bits (Channel 18 Sample time selection) */
+#define ADC_SMPR1_SMP18_0 0x01000000U /*!<Bit 0 */
+#define ADC_SMPR1_SMP18_1 0x02000000U /*!<Bit 1 */
+#define ADC_SMPR1_SMP18_2 0x04000000U /*!<Bit 2 */
+
+/****************** Bit definition for ADC_SMPR2 register *******************/
+#define ADC_SMPR2_SMP0 0x00000007U /*!<SMP0[2:0] bits (Channel 0 Sample time selection) */
+#define ADC_SMPR2_SMP0_0 0x00000001U /*!<Bit 0 */
+#define ADC_SMPR2_SMP0_1 0x00000002U /*!<Bit 1 */
+#define ADC_SMPR2_SMP0_2 0x00000004U /*!<Bit 2 */
+#define ADC_SMPR2_SMP1 0x00000038U /*!<SMP1[2:0] bits (Channel 1 Sample time selection) */
+#define ADC_SMPR2_SMP1_0 0x00000008U /*!<Bit 0 */
+#define ADC_SMPR2_SMP1_1 0x00000010U /*!<Bit 1 */
+#define ADC_SMPR2_SMP1_2 0x00000020U /*!<Bit 2 */
+#define ADC_SMPR2_SMP2 0x000001C0U /*!<SMP2[2:0] bits (Channel 2 Sample time selection) */
+#define ADC_SMPR2_SMP2_0 0x00000040U /*!<Bit 0 */
+#define ADC_SMPR2_SMP2_1 0x00000080U /*!<Bit 1 */
+#define ADC_SMPR2_SMP2_2 0x00000100U /*!<Bit 2 */
+#define ADC_SMPR2_SMP3 0x00000E00U /*!<SMP3[2:0] bits (Channel 3 Sample time selection) */
+#define ADC_SMPR2_SMP3_0 0x00000200U /*!<Bit 0 */
+#define ADC_SMPR2_SMP3_1 0x00000400U /*!<Bit 1 */
+#define ADC_SMPR2_SMP3_2 0x00000800U /*!<Bit 2 */
+#define ADC_SMPR2_SMP4 0x00007000U /*!<SMP4[2:0] bits (Channel 4 Sample time selection) */
+#define ADC_SMPR2_SMP4_0 0x00001000U /*!<Bit 0 */
+#define ADC_SMPR2_SMP4_1 0x00002000U /*!<Bit 1 */
+#define ADC_SMPR2_SMP4_2 0x00004000U /*!<Bit 2 */
+#define ADC_SMPR2_SMP5 0x00038000U /*!<SMP5[2:0] bits (Channel 5 Sample time selection) */
+#define ADC_SMPR2_SMP5_0 0x00008000U /*!<Bit 0 */
+#define ADC_SMPR2_SMP5_1 0x00010000U /*!<Bit 1 */
+#define ADC_SMPR2_SMP5_2 0x00020000U /*!<Bit 2 */
+#define ADC_SMPR2_SMP6 0x001C0000U /*!<SMP6[2:0] bits (Channel 6 Sample time selection) */
+#define ADC_SMPR2_SMP6_0 0x00040000U /*!<Bit 0 */
+#define ADC_SMPR2_SMP6_1 0x00080000U /*!<Bit 1 */
+#define ADC_SMPR2_SMP6_2 0x00100000U /*!<Bit 2 */
+#define ADC_SMPR2_SMP7 0x00E00000U /*!<SMP7[2:0] bits (Channel 7 Sample time selection) */
+#define ADC_SMPR2_SMP7_0 0x00200000U /*!<Bit 0 */
+#define ADC_SMPR2_SMP7_1 0x00400000U /*!<Bit 1 */
+#define ADC_SMPR2_SMP7_2 0x00800000U /*!<Bit 2 */
+#define ADC_SMPR2_SMP8 0x07000000U /*!<SMP8[2:0] bits (Channel 8 Sample time selection) */
+#define ADC_SMPR2_SMP8_0 0x01000000U /*!<Bit 0 */
+#define ADC_SMPR2_SMP8_1 0x02000000U /*!<Bit 1 */
+#define ADC_SMPR2_SMP8_2 0x04000000U /*!<Bit 2 */
+#define ADC_SMPR2_SMP9 0x38000000U /*!<SMP9[2:0] bits (Channel 9 Sample time selection) */
+#define ADC_SMPR2_SMP9_0 0x08000000U /*!<Bit 0 */
+#define ADC_SMPR2_SMP9_1 0x10000000U /*!<Bit 1 */
+#define ADC_SMPR2_SMP9_2 0x20000000U /*!<Bit 2 */
+
+/****************** Bit definition for ADC_JOFR1 register *******************/
+#define ADC_JOFR1_JOFFSET1 0x0FFFU /*!<Data offset for injected channel 1 */
+
+/****************** Bit definition for ADC_JOFR2 register *******************/
+#define ADC_JOFR2_JOFFSET2 0x0FFFU /*!<Data offset for injected channel 2 */
+
+/****************** Bit definition for ADC_JOFR3 register *******************/
+#define ADC_JOFR3_JOFFSET3 0x0FFFU /*!<Data offset for injected channel 3 */
+
+/****************** Bit definition for ADC_JOFR4 register *******************/
+#define ADC_JOFR4_JOFFSET4 0x0FFFU /*!<Data offset for injected channel 4 */
+
+/******************* Bit definition for ADC_HTR register ********************/
+#define ADC_HTR_HT 0x0FFFU /*!<Analog watchdog high threshold */
+
+/******************* Bit definition for ADC_LTR register ********************/
+#define ADC_LTR_LT 0x0FFFU /*!<Analog watchdog low threshold */
+
+/******************* Bit definition for ADC_SQR1 register *******************/
+#define ADC_SQR1_SQ13 0x0000001FU /*!<SQ13[4:0] bits (13th conversion in regular sequence) */
+#define ADC_SQR1_SQ13_0 0x00000001U /*!<Bit 0 */
+#define ADC_SQR1_SQ13_1 0x00000002U /*!<Bit 1 */
+#define ADC_SQR1_SQ13_2 0x00000004U /*!<Bit 2 */
+#define ADC_SQR1_SQ13_3 0x00000008U /*!<Bit 3 */
+#define ADC_SQR1_SQ13_4 0x00000010U /*!<Bit 4 */
+#define ADC_SQR1_SQ14 0x000003E0U /*!<SQ14[4:0] bits (14th conversion in regular sequence) */
+#define ADC_SQR1_SQ14_0 0x00000020U /*!<Bit 0 */
+#define ADC_SQR1_SQ14_1 0x00000040U /*!<Bit 1 */
+#define ADC_SQR1_SQ14_2 0x00000080U /*!<Bit 2 */
+#define ADC_SQR1_SQ14_3 0x00000100U /*!<Bit 3 */
+#define ADC_SQR1_SQ14_4 0x00000200U /*!<Bit 4 */
+#define ADC_SQR1_SQ15 0x00007C00U /*!<SQ15[4:0] bits (15th conversion in regular sequence) */
+#define ADC_SQR1_SQ15_0 0x00000400U /*!<Bit 0 */
+#define ADC_SQR1_SQ15_1 0x00000800U /*!<Bit 1 */
+#define ADC_SQR1_SQ15_2 0x00001000U /*!<Bit 2 */
+#define ADC_SQR1_SQ15_3 0x00002000U /*!<Bit 3 */
+#define ADC_SQR1_SQ15_4 0x00004000U /*!<Bit 4 */
+#define ADC_SQR1_SQ16 0x000F8000U /*!<SQ16[4:0] bits (16th conversion in regular sequence) */
+#define ADC_SQR1_SQ16_0 0x00008000U /*!<Bit 0 */
+#define ADC_SQR1_SQ16_1 0x00010000U /*!<Bit 1 */
+#define ADC_SQR1_SQ16_2 0x00020000U /*!<Bit 2 */
+#define ADC_SQR1_SQ16_3 0x00040000U /*!<Bit 3 */
+#define ADC_SQR1_SQ16_4 0x00080000U /*!<Bit 4 */
+#define ADC_SQR1_L 0x00F00000U /*!<L[3:0] bits (Regular channel sequence length) */
+#define ADC_SQR1_L_0 0x00100000U /*!<Bit 0 */
+#define ADC_SQR1_L_1 0x00200000U /*!<Bit 1 */
+#define ADC_SQR1_L_2 0x00400000U /*!<Bit 2 */
+#define ADC_SQR1_L_3 0x00800000U /*!<Bit 3 */
+
+/******************* Bit definition for ADC_SQR2 register *******************/
+#define ADC_SQR2_SQ7 0x0000001FU /*!<SQ7[4:0] bits (7th conversion in regular sequence) */
+#define ADC_SQR2_SQ7_0 0x00000001U /*!<Bit 0 */
+#define ADC_SQR2_SQ7_1 0x00000002U /*!<Bit 1 */
+#define ADC_SQR2_SQ7_2 0x00000004U /*!<Bit 2 */
+#define ADC_SQR2_SQ7_3 0x00000008U /*!<Bit 3 */
+#define ADC_SQR2_SQ7_4 0x00000010U /*!<Bit 4 */
+#define ADC_SQR2_SQ8 0x000003E0U /*!<SQ8[4:0] bits (8th conversion in regular sequence) */
+#define ADC_SQR2_SQ8_0 0x00000020U /*!<Bit 0 */
+#define ADC_SQR2_SQ8_1 0x00000040U /*!<Bit 1 */
+#define ADC_SQR2_SQ8_2 0x00000080U /*!<Bit 2 */
+#define ADC_SQR2_SQ8_3 0x00000100U /*!<Bit 3 */
+#define ADC_SQR2_SQ8_4 0x00000200U /*!<Bit 4 */
+#define ADC_SQR2_SQ9 0x00007C00U /*!<SQ9[4:0] bits (9th conversion in regular sequence) */
+#define ADC_SQR2_SQ9_0 0x00000400U /*!<Bit 0 */
+#define ADC_SQR2_SQ9_1 0x00000800U /*!<Bit 1 */
+#define ADC_SQR2_SQ9_2 0x00001000U /*!<Bit 2 */
+#define ADC_SQR2_SQ9_3 0x00002000U /*!<Bit 3 */
+#define ADC_SQR2_SQ9_4 0x00004000U /*!<Bit 4 */
+#define ADC_SQR2_SQ10 0x000F8000U /*!<SQ10[4:0] bits (10th conversion in regular sequence) */
+#define ADC_SQR2_SQ10_0 0x00008000U /*!<Bit 0 */
+#define ADC_SQR2_SQ10_1 0x00010000U /*!<Bit 1 */
+#define ADC_SQR2_SQ10_2 0x00020000U /*!<Bit 2 */
+#define ADC_SQR2_SQ10_3 0x00040000U /*!<Bit 3 */
+#define ADC_SQR2_SQ10_4 0x00080000U /*!<Bit 4 */
+#define ADC_SQR2_SQ11 0x01F00000U /*!<SQ11[4:0] bits (11th conversion in regular sequence) */
+#define ADC_SQR2_SQ11_0 0x00100000U /*!<Bit 0 */
+#define ADC_SQR2_SQ11_1 0x00200000U /*!<Bit 1 */
+#define ADC_SQR2_SQ11_2 0x00400000U /*!<Bit 2 */
+#define ADC_SQR2_SQ11_3 0x00800000U /*!<Bit 3 */
+#define ADC_SQR2_SQ11_4 0x01000000U /*!<Bit 4 */
+#define ADC_SQR2_SQ12 0x3E000000U /*!<SQ12[4:0] bits (12th conversion in regular sequence) */
+#define ADC_SQR2_SQ12_0 0x02000000U /*!<Bit 0 */
+#define ADC_SQR2_SQ12_1 0x04000000U /*!<Bit 1 */
+#define ADC_SQR2_SQ12_2 0x08000000U /*!<Bit 2 */
+#define ADC_SQR2_SQ12_3 0x10000000U /*!<Bit 3 */
+#define ADC_SQR2_SQ12_4 0x20000000U /*!<Bit 4 */
+
+/******************* Bit definition for ADC_SQR3 register *******************/
+#define ADC_SQR3_SQ1 0x0000001FU /*!<SQ1[4:0] bits (1st conversion in regular sequence) */
+#define ADC_SQR3_SQ1_0 0x00000001U /*!<Bit 0 */
+#define ADC_SQR3_SQ1_1 0x00000002U /*!<Bit 1 */
+#define ADC_SQR3_SQ1_2 0x00000004U /*!<Bit 2 */
+#define ADC_SQR3_SQ1_3 0x00000008U /*!<Bit 3 */
+#define ADC_SQR3_SQ1_4 0x00000010U /*!<Bit 4 */
+#define ADC_SQR3_SQ2 0x000003E0U /*!<SQ2[4:0] bits (2nd conversion in regular sequence) */
+#define ADC_SQR3_SQ2_0 0x00000020U /*!<Bit 0 */
+#define ADC_SQR3_SQ2_1 0x00000040U /*!<Bit 1 */
+#define ADC_SQR3_SQ2_2 0x00000080U /*!<Bit 2 */
+#define ADC_SQR3_SQ2_3 0x00000100U /*!<Bit 3 */
+#define ADC_SQR3_SQ2_4 0x00000200U /*!<Bit 4 */
+#define ADC_SQR3_SQ3 0x00007C00U /*!<SQ3[4:0] bits (3rd conversion in regular sequence) */
+#define ADC_SQR3_SQ3_0 0x00000400U /*!<Bit 0 */
+#define ADC_SQR3_SQ3_1 0x00000800U /*!<Bit 1 */
+#define ADC_SQR3_SQ3_2 0x00001000U /*!<Bit 2 */
+#define ADC_SQR3_SQ3_3 0x00002000U /*!<Bit 3 */
+#define ADC_SQR3_SQ3_4 0x00004000U /*!<Bit 4 */
+#define ADC_SQR3_SQ4 0x000F8000U /*!<SQ4[4:0] bits (4th conversion in regular sequence) */
+#define ADC_SQR3_SQ4_0 0x00008000U /*!<Bit 0 */
+#define ADC_SQR3_SQ4_1 0x00010000U /*!<Bit 1 */
+#define ADC_SQR3_SQ4_2 0x00020000U /*!<Bit 2 */
+#define ADC_SQR3_SQ4_3 0x00040000U /*!<Bit 3 */
+#define ADC_SQR3_SQ4_4 0x00080000U /*!<Bit 4 */
+#define ADC_SQR3_SQ5 0x01F00000U /*!<SQ5[4:0] bits (5th conversion in regular sequence) */
+#define ADC_SQR3_SQ5_0 0x00100000U /*!<Bit 0 */
+#define ADC_SQR3_SQ5_1 0x00200000U /*!<Bit 1 */
+#define ADC_SQR3_SQ5_2 0x00400000U /*!<Bit 2 */
+#define ADC_SQR3_SQ5_3 0x00800000U /*!<Bit 3 */
+#define ADC_SQR3_SQ5_4 0x01000000U /*!<Bit 4 */
+#define ADC_SQR3_SQ6 0x3E000000U /*!<SQ6[4:0] bits (6th conversion in regular sequence) */
+#define ADC_SQR3_SQ6_0 0x02000000U /*!<Bit 0 */
+#define ADC_SQR3_SQ6_1 0x04000000U /*!<Bit 1 */
+#define ADC_SQR3_SQ6_2 0x08000000U /*!<Bit 2 */
+#define ADC_SQR3_SQ6_3 0x10000000U /*!<Bit 3 */
+#define ADC_SQR3_SQ6_4 0x20000000U /*!<Bit 4 */
+
+/******************* Bit definition for ADC_JSQR register *******************/
+#define ADC_JSQR_JSQ1 0x0000001FU /*!<JSQ1[4:0] bits (1st conversion in injected sequence) */
+#define ADC_JSQR_JSQ1_0 0x00000001U /*!<Bit 0 */
+#define ADC_JSQR_JSQ1_1 0x00000002U /*!<Bit 1 */
+#define ADC_JSQR_JSQ1_2 0x00000004U /*!<Bit 2 */
+#define ADC_JSQR_JSQ1_3 0x00000008U /*!<Bit 3 */
+#define ADC_JSQR_JSQ1_4 0x00000010U /*!<Bit 4 */
+#define ADC_JSQR_JSQ2 0x000003E0U /*!<JSQ2[4:0] bits (2nd conversion in injected sequence) */
+#define ADC_JSQR_JSQ2_0 0x00000020U /*!<Bit 0 */
+#define ADC_JSQR_JSQ2_1 0x00000040U /*!<Bit 1 */
+#define ADC_JSQR_JSQ2_2 0x00000080U /*!<Bit 2 */
+#define ADC_JSQR_JSQ2_3 0x00000100U /*!<Bit 3 */
+#define ADC_JSQR_JSQ2_4 0x00000200U /*!<Bit 4 */
+#define ADC_JSQR_JSQ3 0x00007C00U /*!<JSQ3[4:0] bits (3rd conversion in injected sequence) */
+#define ADC_JSQR_JSQ3_0 0x00000400U /*!<Bit 0 */
+#define ADC_JSQR_JSQ3_1 0x00000800U /*!<Bit 1 */
+#define ADC_JSQR_JSQ3_2 0x00001000U /*!<Bit 2 */
+#define ADC_JSQR_JSQ3_3 0x00002000U /*!<Bit 3 */
+#define ADC_JSQR_JSQ3_4 0x00004000U /*!<Bit 4 */
+#define ADC_JSQR_JSQ4 0x000F8000U /*!<JSQ4[4:0] bits (4th conversion in injected sequence) */
+#define ADC_JSQR_JSQ4_0 0x00008000U /*!<Bit 0 */
+#define ADC_JSQR_JSQ4_1 0x00010000U /*!<Bit 1 */
+#define ADC_JSQR_JSQ4_2 0x00020000U /*!<Bit 2 */
+#define ADC_JSQR_JSQ4_3 0x00040000U /*!<Bit 3 */
+#define ADC_JSQR_JSQ4_4 0x00080000U /*!<Bit 4 */
+#define ADC_JSQR_JL 0x00300000U /*!<JL[1:0] bits (Injected Sequence length) */
+#define ADC_JSQR_JL_0 0x00100000U /*!<Bit 0 */
+#define ADC_JSQR_JL_1 0x00200000U /*!<Bit 1 */
+
+/******************* Bit definition for ADC_JDR1 register *******************/
+#define ADC_JDR1_JDATA 0xFFFFU /*!<Injected data */
+
+/******************* Bit definition for ADC_JDR2 register *******************/
+#define ADC_JDR2_JDATA 0xFFFFU /*!<Injected data */
+
+/******************* Bit definition for ADC_JDR3 register *******************/
+#define ADC_JDR3_JDATA 0xFFFFU /*!<Injected data */
+
+/******************* Bit definition for ADC_JDR4 register *******************/
+#define ADC_JDR4_JDATA 0xFFFFU /*!<Injected data */
+
+/******************** Bit definition for ADC_DR register ********************/
+#define ADC_DR_DATA 0x0000FFFFU /*!<Regular data */
+#define ADC_DR_ADC2DATA 0xFFFF0000U /*!<ADC2 data */
+
+/******************* Bit definition for ADC_CSR register ********************/
+#define ADC_CSR_AWD1 0x00000001U /*!<ADC1 Analog watchdog flag */
+#define ADC_CSR_EOC1 0x00000002U /*!<ADC1 End of conversion */
+#define ADC_CSR_JEOC1 0x00000004U /*!<ADC1 Injected channel end of conversion */
+#define ADC_CSR_JSTRT1 0x00000008U /*!<ADC1 Injected channel Start flag */
+#define ADC_CSR_STRT1 0x00000010U /*!<ADC1 Regular channel Start flag */
+#define ADC_CSR_OVR1 0x00000020U /*!<ADC1 DMA overrun flag */
+#define ADC_CSR_AWD2 0x00000100U /*!<ADC2 Analog watchdog flag */
+#define ADC_CSR_EOC2 0x00000200U /*!<ADC2 End of conversion */
+#define ADC_CSR_JEOC2 0x00000400U /*!<ADC2 Injected channel end of conversion */
+#define ADC_CSR_JSTRT2 0x00000800U /*!<ADC2 Injected channel Start flag */
+#define ADC_CSR_STRT2 0x00001000U /*!<ADC2 Regular channel Start flag */
+#define ADC_CSR_OVR2 0x00002000U /*!<ADC2 DMA overrun flag */
+#define ADC_CSR_AWD3 0x00010000U /*!<ADC3 Analog watchdog flag */
+#define ADC_CSR_EOC3 0x00020000U /*!<ADC3 End of conversion */
+#define ADC_CSR_JEOC3 0x00040000U /*!<ADC3 Injected channel end of conversion */
+#define ADC_CSR_JSTRT3 0x00080000U /*!<ADC3 Injected channel Start flag */
+#define ADC_CSR_STRT3 0x00100000U /*!<ADC3 Regular channel Start flag */
+#define ADC_CSR_OVR3 0x00200000U /*!<ADC3 DMA overrun flag */
+
+/* Legacy defines */
+#define ADC_CSR_DOVR1 ADC_CSR_OVR1
+#define ADC_CSR_DOVR2 ADC_CSR_OVR2
+#define ADC_CSR_DOVR3 ADC_CSR_OVR3
+
+/******************* Bit definition for ADC_CCR register ********************/
+#define ADC_CCR_MULTI 0x0000001FU /*!<MULTI[4:0] bits (Multi-ADC mode selection) */
+#define ADC_CCR_MULTI_0 0x00000001U /*!<Bit 0 */
+#define ADC_CCR_MULTI_1 0x00000002U /*!<Bit 1 */
+#define ADC_CCR_MULTI_2 0x00000004U /*!<Bit 2 */
+#define ADC_CCR_MULTI_3 0x00000008U /*!<Bit 3 */
+#define ADC_CCR_MULTI_4 0x00000010U /*!<Bit 4 */
+#define ADC_CCR_DELAY 0x00000F00U /*!<DELAY[3:0] bits (Delay between 2 sampling phases) */
+#define ADC_CCR_DELAY_0 0x00000100U /*!<Bit 0 */
+#define ADC_CCR_DELAY_1 0x00000200U /*!<Bit 1 */
+#define ADC_CCR_DELAY_2 0x00000400U /*!<Bit 2 */
+#define ADC_CCR_DELAY_3 0x00000800U /*!<Bit 3 */
+#define ADC_CCR_DDS 0x00002000U /*!<DMA disable selection (Multi-ADC mode) */
+#define ADC_CCR_DMA 0x0000C000U /*!<DMA[1:0] bits (Direct Memory Access mode for multimode) */
+#define ADC_CCR_DMA_0 0x00004000U /*!<Bit 0 */
+#define ADC_CCR_DMA_1 0x00008000U /*!<Bit 1 */
+#define ADC_CCR_ADCPRE 0x00030000U /*!<ADCPRE[1:0] bits (ADC prescaler) */
+#define ADC_CCR_ADCPRE_0 0x00010000U /*!<Bit 0 */
+#define ADC_CCR_ADCPRE_1 0x00020000U /*!<Bit 1 */
+#define ADC_CCR_VBATE 0x00400000U /*!<VBAT Enable */
+#define ADC_CCR_TSVREFE 0x00800000U /*!<Temperature Sensor and VREFINT Enable */
+
+/******************* Bit definition for ADC_CDR register ********************/
+#define ADC_CDR_DATA1 0x0000FFFFU /*!<1st data of a pair of regular conversions */
+#define ADC_CDR_DATA2 0xFFFF0000U /*!<2nd data of a pair of regular conversions */
+
+/******************************************************************************/
+/* */
+/* CRC calculation unit */
+/* */
+/******************************************************************************/
+/******************* Bit definition for CRC_DR register *********************/
+#define CRC_DR_DR 0xFFFFFFFFU /*!< Data register bits */
+
+
+/******************* Bit definition for CRC_IDR register ********************/
+#define CRC_IDR_IDR 0xFFU /*!< General-purpose 8-bit data register bits */
+
+
+/******************** Bit definition for CRC_CR register ********************/
+#define CRC_CR_RESET 0x01U /*!< RESET bit */
+
+/******************************************************************************/
+/* */
+/* Debug MCU */
+/* */
+/******************************************************************************/
+
+/******************************************************************************/
+/* */
+/* DMA Controller */
+/* */
+/******************************************************************************/
+/******************** Bits definition for DMA_SxCR register *****************/
+#define DMA_SxCR_CHSEL 0x0E000000U
+#define DMA_SxCR_CHSEL_0 0x02000000U
+#define DMA_SxCR_CHSEL_1 0x04000000U
+#define DMA_SxCR_CHSEL_2 0x08000000U
+#define DMA_SxCR_MBURST 0x01800000U
+#define DMA_SxCR_MBURST_0 0x00800000U
+#define DMA_SxCR_MBURST_1 0x01000000U
+#define DMA_SxCR_PBURST 0x00600000U
+#define DMA_SxCR_PBURST_0 0x00200000U
+#define DMA_SxCR_PBURST_1 0x00400000U
+#define DMA_SxCR_CT 0x00080000U
+#define DMA_SxCR_DBM 0x00040000U
+#define DMA_SxCR_PL 0x00030000U
+#define DMA_SxCR_PL_0 0x00010000U
+#define DMA_SxCR_PL_1 0x00020000U
+#define DMA_SxCR_PINCOS 0x00008000U
+#define DMA_SxCR_MSIZE 0x00006000U
+#define DMA_SxCR_MSIZE_0 0x00002000U
+#define DMA_SxCR_MSIZE_1 0x00004000U
+#define DMA_SxCR_PSIZE 0x00001800U
+#define DMA_SxCR_PSIZE_0 0x00000800U
+#define DMA_SxCR_PSIZE_1 0x00001000U
+#define DMA_SxCR_MINC 0x00000400U
+#define DMA_SxCR_PINC 0x00000200U
+#define DMA_SxCR_CIRC 0x00000100U
+#define DMA_SxCR_DIR 0x000000C0U
+#define DMA_SxCR_DIR_0 0x00000040U
+#define DMA_SxCR_DIR_1 0x00000080U
+#define DMA_SxCR_PFCTRL 0x00000020U
+#define DMA_SxCR_TCIE 0x00000010U
+#define DMA_SxCR_HTIE 0x00000008U
+#define DMA_SxCR_TEIE 0x00000004U
+#define DMA_SxCR_DMEIE 0x00000002U
+#define DMA_SxCR_EN 0x00000001U
+
+/* Legacy defines */
+#define DMA_SxCR_ACK 0x00100000U
+
+/******************** Bits definition for DMA_SxCNDTR register **************/
+#define DMA_SxNDT 0x0000FFFFU
+#define DMA_SxNDT_0 0x00000001U
+#define DMA_SxNDT_1 0x00000002U
+#define DMA_SxNDT_2 0x00000004U
+#define DMA_SxNDT_3 0x00000008U
+#define DMA_SxNDT_4 0x00000010U
+#define DMA_SxNDT_5 0x00000020U
+#define DMA_SxNDT_6 0x00000040U
+#define DMA_SxNDT_7 0x00000080U
+#define DMA_SxNDT_8 0x00000100U
+#define DMA_SxNDT_9 0x00000200U
+#define DMA_SxNDT_10 0x00000400U
+#define DMA_SxNDT_11 0x00000800U
+#define DMA_SxNDT_12 0x00001000U
+#define DMA_SxNDT_13 0x00002000U
+#define DMA_SxNDT_14 0x00004000U
+#define DMA_SxNDT_15 0x00008000U
+
+/******************** Bits definition for DMA_SxFCR register ****************/
+#define DMA_SxFCR_FEIE 0x00000080U
+#define DMA_SxFCR_FS 0x00000038U
+#define DMA_SxFCR_FS_0 0x00000008U
+#define DMA_SxFCR_FS_1 0x00000010U
+#define DMA_SxFCR_FS_2 0x00000020U
+#define DMA_SxFCR_DMDIS 0x00000004U
+#define DMA_SxFCR_FTH 0x00000003U
+#define DMA_SxFCR_FTH_0 0x00000001U
+#define DMA_SxFCR_FTH_1 0x00000002U
+
+/******************** Bits definition for DMA_LISR register *****************/
+#define DMA_LISR_TCIF3 0x08000000U
+#define DMA_LISR_HTIF3 0x04000000U
+#define DMA_LISR_TEIF3 0x02000000U
+#define DMA_LISR_DMEIF3 0x01000000U
+#define DMA_LISR_FEIF3 0x00400000U
+#define DMA_LISR_TCIF2 0x00200000U
+#define DMA_LISR_HTIF2 0x00100000U
+#define DMA_LISR_TEIF2 0x00080000U
+#define DMA_LISR_DMEIF2 0x00040000U
+#define DMA_LISR_FEIF2 0x00010000U
+#define DMA_LISR_TCIF1 0x00000800U
+#define DMA_LISR_HTIF1 0x00000400U
+#define DMA_LISR_TEIF1 0x00000200U
+#define DMA_LISR_DMEIF1 0x00000100U
+#define DMA_LISR_FEIF1 0x00000040U
+#define DMA_LISR_TCIF0 0x00000020U
+#define DMA_LISR_HTIF0 0x00000010U
+#define DMA_LISR_TEIF0 0x00000008U
+#define DMA_LISR_DMEIF0 0x00000004U
+#define DMA_LISR_FEIF0 0x00000001U
+
+/******************** Bits definition for DMA_HISR register *****************/
+#define DMA_HISR_TCIF7 0x08000000U
+#define DMA_HISR_HTIF7 0x04000000U
+#define DMA_HISR_TEIF7 0x02000000U
+#define DMA_HISR_DMEIF7 0x01000000U
+#define DMA_HISR_FEIF7 0x00400000U
+#define DMA_HISR_TCIF6 0x00200000U
+#define DMA_HISR_HTIF6 0x00100000U
+#define DMA_HISR_TEIF6 0x00080000U
+#define DMA_HISR_DMEIF6 0x00040000U
+#define DMA_HISR_FEIF6 0x00010000U
+#define DMA_HISR_TCIF5 0x00000800U
+#define DMA_HISR_HTIF5 0x00000400U
+#define DMA_HISR_TEIF5 0x00000200U
+#define DMA_HISR_DMEIF5 0x00000100U
+#define DMA_HISR_FEIF5 0x00000040U
+#define DMA_HISR_TCIF4 0x00000020U
+#define DMA_HISR_HTIF4 0x00000010U
+#define DMA_HISR_TEIF4 0x00000008U
+#define DMA_HISR_DMEIF4 0x00000004U
+#define DMA_HISR_FEIF4 0x00000001U
+
+/******************** Bits definition for DMA_LIFCR register ****************/
+#define DMA_LIFCR_CTCIF3 0x08000000U
+#define DMA_LIFCR_CHTIF3 0x04000000U
+#define DMA_LIFCR_CTEIF3 0x02000000U
+#define DMA_LIFCR_CDMEIF3 0x01000000U
+#define DMA_LIFCR_CFEIF3 0x00400000U
+#define DMA_LIFCR_CTCIF2 0x00200000U
+#define DMA_LIFCR_CHTIF2 0x00100000U
+#define DMA_LIFCR_CTEIF2 0x00080000U
+#define DMA_LIFCR_CDMEIF2 0x00040000U
+#define DMA_LIFCR_CFEIF2 0x00010000U
+#define DMA_LIFCR_CTCIF1 0x00000800U
+#define DMA_LIFCR_CHTIF1 0x00000400U
+#define DMA_LIFCR_CTEIF1 0x00000200U
+#define DMA_LIFCR_CDMEIF1 0x00000100U
+#define DMA_LIFCR_CFEIF1 0x00000040U
+#define DMA_LIFCR_CTCIF0 0x00000020U
+#define DMA_LIFCR_CHTIF0 0x00000010U
+#define DMA_LIFCR_CTEIF0 0x00000008U
+#define DMA_LIFCR_CDMEIF0 0x00000004U
+#define DMA_LIFCR_CFEIF0 0x00000001U
+
+/******************** Bits definition for DMA_HIFCR register ****************/
+#define DMA_HIFCR_CTCIF7 0x08000000U
+#define DMA_HIFCR_CHTIF7 0x04000000U
+#define DMA_HIFCR_CTEIF7 0x02000000U
+#define DMA_HIFCR_CDMEIF7 0x01000000U
+#define DMA_HIFCR_CFEIF7 0x00400000U
+#define DMA_HIFCR_CTCIF6 0x00200000U
+#define DMA_HIFCR_CHTIF6 0x00100000U
+#define DMA_HIFCR_CTEIF6 0x00080000U
+#define DMA_HIFCR_CDMEIF6 0x00040000U
+#define DMA_HIFCR_CFEIF6 0x00010000U
+#define DMA_HIFCR_CTCIF5 0x00000800U
+#define DMA_HIFCR_CHTIF5 0x00000400U
+#define DMA_HIFCR_CTEIF5 0x00000200U
+#define DMA_HIFCR_CDMEIF5 0x00000100U
+#define DMA_HIFCR_CFEIF5 0x00000040U
+#define DMA_HIFCR_CTCIF4 0x00000020U
+#define DMA_HIFCR_CHTIF4 0x00000010U
+#define DMA_HIFCR_CTEIF4 0x00000008U
+#define DMA_HIFCR_CDMEIF4 0x00000004U
+#define DMA_HIFCR_CFEIF4 0x00000001U
+
+
+/******************************************************************************/
+/* */
+/* External Interrupt/Event Controller */
+/* */
+/******************************************************************************/
+/******************* Bit definition for EXTI_IMR register *******************/
+#define EXTI_IMR_MR0 0x00000001U /*!< Interrupt Mask on line 0 */
+#define EXTI_IMR_MR1 0x00000002U /*!< Interrupt Mask on line 1 */
+#define EXTI_IMR_MR2 0x00000004U /*!< Interrupt Mask on line 2 */
+#define EXTI_IMR_MR3 0x00000008U /*!< Interrupt Mask on line 3 */
+#define EXTI_IMR_MR4 0x00000010U /*!< Interrupt Mask on line 4 */
+#define EXTI_IMR_MR5 0x00000020U /*!< Interrupt Mask on line 5 */
+#define EXTI_IMR_MR6 0x00000040U /*!< Interrupt Mask on line 6 */
+#define EXTI_IMR_MR7 0x00000080U /*!< Interrupt Mask on line 7 */
+#define EXTI_IMR_MR8 0x00000100U /*!< Interrupt Mask on line 8 */
+#define EXTI_IMR_MR9 0x00000200U /*!< Interrupt Mask on line 9 */
+#define EXTI_IMR_MR10 0x00000400U /*!< Interrupt Mask on line 10 */
+#define EXTI_IMR_MR11 0x00000800U /*!< Interrupt Mask on line 11 */
+#define EXTI_IMR_MR12 0x00001000U /*!< Interrupt Mask on line 12 */
+#define EXTI_IMR_MR13 0x00002000U /*!< Interrupt Mask on line 13 */
+#define EXTI_IMR_MR14 0x00004000U /*!< Interrupt Mask on line 14 */
+#define EXTI_IMR_MR15 0x00008000U /*!< Interrupt Mask on line 15 */
+#define EXTI_IMR_MR16 0x00010000U /*!< Interrupt Mask on line 16 */
+#define EXTI_IMR_MR17 0x00020000U /*!< Interrupt Mask on line 17 */
+#define EXTI_IMR_MR18 0x00040000U /*!< Interrupt Mask on line 18 */
+#define EXTI_IMR_MR19 0x00080000U /*!< Interrupt Mask on line 19 */
+#define EXTI_IMR_MR20 0x00100000U /*!< Interrupt Mask on line 20 */
+#define EXTI_IMR_MR21 0x00200000U /*!< Interrupt Mask on line 21 */
+#define EXTI_IMR_MR22 0x00400000U /*!< Interrupt Mask on line 22 */
+#define EXTI_IMR_MR23 0x00800000U /*!< Interrupt Mask on line 23 */
+
+/******************* Bit definition for EXTI_EMR register *******************/
+#define EXTI_EMR_MR0 0x00000001U /*!< Event Mask on line 0 */
+#define EXTI_EMR_MR1 0x00000002U /*!< Event Mask on line 1 */
+#define EXTI_EMR_MR2 0x00000004U /*!< Event Mask on line 2 */
+#define EXTI_EMR_MR3 0x00000008U /*!< Event Mask on line 3 */
+#define EXTI_EMR_MR4 0x00000010U /*!< Event Mask on line 4 */
+#define EXTI_EMR_MR5 0x00000020U /*!< Event Mask on line 5 */
+#define EXTI_EMR_MR6 0x00000040U /*!< Event Mask on line 6 */
+#define EXTI_EMR_MR7 0x00000080U /*!< Event Mask on line 7 */
+#define EXTI_EMR_MR8 0x00000100U /*!< Event Mask on line 8 */
+#define EXTI_EMR_MR9 0x00000200U /*!< Event Mask on line 9 */
+#define EXTI_EMR_MR10 0x00000400U /*!< Event Mask on line 10 */
+#define EXTI_EMR_MR11 0x00000800U /*!< Event Mask on line 11 */
+#define EXTI_EMR_MR12 0x00001000U /*!< Event Mask on line 12 */
+#define EXTI_EMR_MR13 0x00002000U /*!< Event Mask on line 13 */
+#define EXTI_EMR_MR14 0x00004000U /*!< Event Mask on line 14 */
+#define EXTI_EMR_MR15 0x00008000U /*!< Event Mask on line 15 */
+#define EXTI_EMR_MR16 0x00010000U /*!< Event Mask on line 16 */
+#define EXTI_EMR_MR17 0x00020000U /*!< Event Mask on line 17 */
+#define EXTI_EMR_MR18 0x00040000U /*!< Event Mask on line 18 */
+#define EXTI_EMR_MR19 0x00080000U /*!< Event Mask on line 19 */
+#define EXTI_EMR_MR20 0x00100000U /*!< Event Mask on line 20 */
+#define EXTI_EMR_MR21 0x00200000U /*!< Event Mask on line 21 */
+#define EXTI_EMR_MR22 0x00400000U /*!< Event Mask on line 22 */
+#define EXTI_EMR_MR23 0x00800000U /*!< Event Mask on line 23 */
+
+/****************** Bit definition for EXTI_RTSR register *******************/
+#define EXTI_RTSR_TR0 0x00000001U /*!< Rising trigger event configuration bit of line 0 */
+#define EXTI_RTSR_TR1 0x00000002U /*!< Rising trigger event configuration bit of line 1 */
+#define EXTI_RTSR_TR2 0x00000004U /*!< Rising trigger event configuration bit of line 2 */
+#define EXTI_RTSR_TR3 0x00000008U /*!< Rising trigger event configuration bit of line 3 */
+#define EXTI_RTSR_TR4 0x00000010U /*!< Rising trigger event configuration bit of line 4 */
+#define EXTI_RTSR_TR5 0x00000020U /*!< Rising trigger event configuration bit of line 5 */
+#define EXTI_RTSR_TR6 0x00000040U /*!< Rising trigger event configuration bit of line 6 */
+#define EXTI_RTSR_TR7 0x00000080U /*!< Rising trigger event configuration bit of line 7 */
+#define EXTI_RTSR_TR8 0x00000100U /*!< Rising trigger event configuration bit of line 8 */
+#define EXTI_RTSR_TR9 0x00000200U /*!< Rising trigger event configuration bit of line 9 */
+#define EXTI_RTSR_TR10 0x00000400U /*!< Rising trigger event configuration bit of line 10 */
+#define EXTI_RTSR_TR11 0x00000800U /*!< Rising trigger event configuration bit of line 11 */
+#define EXTI_RTSR_TR12 0x00001000U /*!< Rising trigger event configuration bit of line 12 */
+#define EXTI_RTSR_TR13 0x00002000U /*!< Rising trigger event configuration bit of line 13 */
+#define EXTI_RTSR_TR14 0x00004000U /*!< Rising trigger event configuration bit of line 14 */
+#define EXTI_RTSR_TR15 0x00008000U /*!< Rising trigger event configuration bit of line 15 */
+#define EXTI_RTSR_TR16 0x00010000U /*!< Rising trigger event configuration bit of line 16 */
+#define EXTI_RTSR_TR17 0x00020000U /*!< Rising trigger event configuration bit of line 17 */
+#define EXTI_RTSR_TR18 0x00040000U /*!< Rising trigger event configuration bit of line 18 */
+#define EXTI_RTSR_TR19 0x00080000U /*!< Rising trigger event configuration bit of line 19 */
+#define EXTI_RTSR_TR20 0x00100000U /*!< Rising trigger event configuration bit of line 20 */
+#define EXTI_RTSR_TR21 0x00200000U /*!< Rising trigger event configuration bit of line 21 */
+#define EXTI_RTSR_TR22 0x00400000U /*!< Rising trigger event configuration bit of line 22 */
+#define EXTI_RTSR_TR23 0x00800000U /*!< Rising trigger event configuration bit of line 23 */
+
+/****************** Bit definition for EXTI_FTSR register *******************/
+#define EXTI_FTSR_TR0 0x00000001U /*!< Falling trigger event configuration bit of line 0 */
+#define EXTI_FTSR_TR1 0x00000002U /*!< Falling trigger event configuration bit of line 1 */
+#define EXTI_FTSR_TR2 0x00000004U /*!< Falling trigger event configuration bit of line 2 */
+#define EXTI_FTSR_TR3 0x00000008U /*!< Falling trigger event configuration bit of line 3 */
+#define EXTI_FTSR_TR4 0x00000010U /*!< Falling trigger event configuration bit of line 4 */
+#define EXTI_FTSR_TR5 0x00000020U /*!< Falling trigger event configuration bit of line 5 */
+#define EXTI_FTSR_TR6 0x00000040U /*!< Falling trigger event configuration bit of line 6 */
+#define EXTI_FTSR_TR7 0x00000080U /*!< Falling trigger event configuration bit of line 7 */
+#define EXTI_FTSR_TR8 0x00000100U /*!< Falling trigger event configuration bit of line 8 */
+#define EXTI_FTSR_TR9 0x00000200U /*!< Falling trigger event configuration bit of line 9 */
+#define EXTI_FTSR_TR10 0x00000400U /*!< Falling trigger event configuration bit of line 10 */
+#define EXTI_FTSR_TR11 0x00000800U /*!< Falling trigger event configuration bit of line 11 */
+#define EXTI_FTSR_TR12 0x00001000U /*!< Falling trigger event configuration bit of line 12 */
+#define EXTI_FTSR_TR13 0x00002000U /*!< Falling trigger event configuration bit of line 13 */
+#define EXTI_FTSR_TR14 0x00004000U /*!< Falling trigger event configuration bit of line 14 */
+#define EXTI_FTSR_TR15 0x00008000U /*!< Falling trigger event configuration bit of line 15 */
+#define EXTI_FTSR_TR16 0x00010000U /*!< Falling trigger event configuration bit of line 16 */
+#define EXTI_FTSR_TR17 0x00020000U /*!< Falling trigger event configuration bit of line 17 */
+#define EXTI_FTSR_TR18 0x00040000U /*!< Falling trigger event configuration bit of line 18 */
+#define EXTI_FTSR_TR19 0x00080000U /*!< Falling trigger event configuration bit of line 19 */
+#define EXTI_FTSR_TR20 0x00100000U /*!< Falling trigger event configuration bit of line 20 */
+#define EXTI_FTSR_TR21 0x00200000U /*!< Falling trigger event configuration bit of line 21 */
+#define EXTI_FTSR_TR22 0x00400000U /*!< Falling trigger event configuration bit of line 22 */
+#define EXTI_FTSR_TR23 0x00800000U /*!< Falling trigger event configuration bit of line 23 */
+
+/****************** Bit definition for EXTI_SWIER register ******************/
+#define EXTI_SWIER_SWIER0 0x00000001U /*!< Software Interrupt on line 0 */
+#define EXTI_SWIER_SWIER1 0x00000002U /*!< Software Interrupt on line 1 */
+#define EXTI_SWIER_SWIER2 0x00000004U /*!< Software Interrupt on line 2 */
+#define EXTI_SWIER_SWIER3 0x00000008U /*!< Software Interrupt on line 3 */
+#define EXTI_SWIER_SWIER4 0x00000010U /*!< Software Interrupt on line 4 */
+#define EXTI_SWIER_SWIER5 0x00000020U /*!< Software Interrupt on line 5 */
+#define EXTI_SWIER_SWIER6 0x00000040U /*!< Software Interrupt on line 6 */
+#define EXTI_SWIER_SWIER7 0x00000080U /*!< Software Interrupt on line 7 */
+#define EXTI_SWIER_SWIER8 0x00000100U /*!< Software Interrupt on line 8 */
+#define EXTI_SWIER_SWIER9 0x00000200U /*!< Software Interrupt on line 9 */
+#define EXTI_SWIER_SWIER10 0x00000400U /*!< Software Interrupt on line 10 */
+#define EXTI_SWIER_SWIER11 0x00000800U /*!< Software Interrupt on line 11 */
+#define EXTI_SWIER_SWIER12 0x00001000U /*!< Software Interrupt on line 12 */
+#define EXTI_SWIER_SWIER13 0x00002000U /*!< Software Interrupt on line 13 */
+#define EXTI_SWIER_SWIER14 0x00004000U /*!< Software Interrupt on line 14 */
+#define EXTI_SWIER_SWIER15 0x00008000U /*!< Software Interrupt on line 15 */
+#define EXTI_SWIER_SWIER16 0x00010000U /*!< Software Interrupt on line 16 */
+#define EXTI_SWIER_SWIER17 0x00020000U /*!< Software Interrupt on line 17 */
+#define EXTI_SWIER_SWIER18 0x00040000U /*!< Software Interrupt on line 18 */
+#define EXTI_SWIER_SWIER19 0x00080000U /*!< Software Interrupt on line 19 */
+#define EXTI_SWIER_SWIER20 0x00100000U /*!< Software Interrupt on line 20 */
+#define EXTI_SWIER_SWIER21 0x00200000U /*!< Software Interrupt on line 21 */
+#define EXTI_SWIER_SWIER22 0x00400000U /*!< Software Interrupt on line 22 */
+#define EXTI_SWIER_SWIER23 0x00800000U /*!< Software Interrupt on line 23 */
+
+/******************* Bit definition for EXTI_PR register ********************/
+#define EXTI_PR_PR0 0x00000001U /*!< Pending bit for line 0 */
+#define EXTI_PR_PR1 0x00000002U /*!< Pending bit for line 1 */
+#define EXTI_PR_PR2 0x00000004U /*!< Pending bit for line 2 */
+#define EXTI_PR_PR3 0x00000008U /*!< Pending bit for line 3 */
+#define EXTI_PR_PR4 0x00000010U /*!< Pending bit for line 4 */
+#define EXTI_PR_PR5 0x00000020U /*!< Pending bit for line 5 */
+#define EXTI_PR_PR6 0x00000040U /*!< Pending bit for line 6 */
+#define EXTI_PR_PR7 0x00000080U /*!< Pending bit for line 7 */
+#define EXTI_PR_PR8 0x00000100U /*!< Pending bit for line 8 */
+#define EXTI_PR_PR9 0x00000200U /*!< Pending bit for line 9 */
+#define EXTI_PR_PR10 0x00000400U /*!< Pending bit for line 10 */
+#define EXTI_PR_PR11 0x00000800U /*!< Pending bit for line 11 */
+#define EXTI_PR_PR12 0x00001000U /*!< Pending bit for line 12 */
+#define EXTI_PR_PR13 0x00002000U /*!< Pending bit for line 13 */
+#define EXTI_PR_PR14 0x00004000U /*!< Pending bit for line 14 */
+#define EXTI_PR_PR15 0x00008000U /*!< Pending bit for line 15 */
+#define EXTI_PR_PR16 0x00010000U /*!< Pending bit for line 16 */
+#define EXTI_PR_PR17 0x00020000U /*!< Pending bit for line 17 */
+#define EXTI_PR_PR18 0x00040000U /*!< Pending bit for line 18 */
+#define EXTI_PR_PR19 0x00080000U /*!< Pending bit for line 19 */
+#define EXTI_PR_PR20 0x00100000U /*!< Pending bit for line 20 */
+#define EXTI_PR_PR21 0x00200000U /*!< Pending bit for line 21 */
+#define EXTI_PR_PR22 0x00400000U /*!< Pending bit for line 22 */
+#define EXTI_PR_PR23 0x00800000U /*!< Pending bit for line 23 */
+
+/******************************************************************************/
+/* */
+/* FLASH */
+/* */
+/******************************************************************************/
+/******************* Bits definition for FLASH_ACR register *****************/
+#define FLASH_ACR_LATENCY 0x0000000FU
+#define FLASH_ACR_LATENCY_0WS 0x00000000U
+#define FLASH_ACR_LATENCY_1WS 0x00000001U
+#define FLASH_ACR_LATENCY_2WS 0x00000002U
+#define FLASH_ACR_LATENCY_3WS 0x00000003U
+#define FLASH_ACR_LATENCY_4WS 0x00000004U
+#define FLASH_ACR_LATENCY_5WS 0x00000005U
+#define FLASH_ACR_LATENCY_6WS 0x00000006U
+#define FLASH_ACR_LATENCY_7WS 0x00000007U
+
+#define FLASH_ACR_PRFTEN 0x00000100U
+#define FLASH_ACR_ICEN 0x00000200U
+#define FLASH_ACR_DCEN 0x00000400U
+#define FLASH_ACR_ICRST 0x00000800U
+#define FLASH_ACR_DCRST 0x00001000U
+#define FLASH_ACR_BYTE0_ADDRESS 0x40023C00U
+#define FLASH_ACR_BYTE2_ADDRESS 0x40023C03U
+
+/******************* Bits definition for FLASH_SR register ******************/
+#define FLASH_SR_EOP 0x00000001U
+#define FLASH_SR_SOP 0x00000002U
+#define FLASH_SR_WRPERR 0x00000010U
+#define FLASH_SR_PGAERR 0x00000020U
+#define FLASH_SR_PGPERR 0x00000040U
+#define FLASH_SR_PGSERR 0x00000080U
+#define FLASH_SR_BSY 0x00010000U
+
+/******************* Bits definition for FLASH_CR register ******************/
+#define FLASH_CR_PG 0x00000001U
+#define FLASH_CR_SER 0x00000002U
+#define FLASH_CR_MER 0x00000004U
+#define FLASH_CR_SNB 0x000000F8U
+#define FLASH_CR_SNB_0 0x00000008U
+#define FLASH_CR_SNB_1 0x00000010U
+#define FLASH_CR_SNB_2 0x00000020U
+#define FLASH_CR_SNB_3 0x00000040U
+#define FLASH_CR_SNB_4 0x00000080U
+#define FLASH_CR_PSIZE 0x00000300U
+#define FLASH_CR_PSIZE_0 0x00000100U
+#define FLASH_CR_PSIZE_1 0x00000200U
+#define FLASH_CR_STRT 0x00010000U
+#define FLASH_CR_EOPIE 0x01000000U
+#define FLASH_CR_LOCK 0x80000000U
+
+/******************* Bits definition for FLASH_OPTCR register ***************/
+#define FLASH_OPTCR_OPTLOCK 0x00000001U
+#define FLASH_OPTCR_OPTSTRT 0x00000002U
+#define FLASH_OPTCR_BOR_LEV_0 0x00000004U
+#define FLASH_OPTCR_BOR_LEV_1 0x00000008U
+#define FLASH_OPTCR_BOR_LEV 0x0000000CU
+
+#define FLASH_OPTCR_WDG_SW 0x00000020U
+#define FLASH_OPTCR_nRST_STOP 0x00000040U
+#define FLASH_OPTCR_nRST_STDBY 0x00000080U
+#define FLASH_OPTCR_RDP 0x0000FF00U
+#define FLASH_OPTCR_RDP_0 0x00000100U
+#define FLASH_OPTCR_RDP_1 0x00000200U
+#define FLASH_OPTCR_RDP_2 0x00000400U
+#define FLASH_OPTCR_RDP_3 0x00000800U
+#define FLASH_OPTCR_RDP_4 0x00001000U
+#define FLASH_OPTCR_RDP_5 0x00002000U
+#define FLASH_OPTCR_RDP_6 0x00004000U
+#define FLASH_OPTCR_RDP_7 0x00008000U
+#define FLASH_OPTCR_nWRP 0x0FFF0000U
+#define FLASH_OPTCR_nWRP_0 0x00010000U
+#define FLASH_OPTCR_nWRP_1 0x00020000U
+#define FLASH_OPTCR_nWRP_2 0x00040000U
+#define FLASH_OPTCR_nWRP_3 0x00080000U
+#define FLASH_OPTCR_nWRP_4 0x00100000U
+#define FLASH_OPTCR_nWRP_5 0x00200000U
+#define FLASH_OPTCR_nWRP_6 0x00400000U
+#define FLASH_OPTCR_nWRP_7 0x00800000U
+#define FLASH_OPTCR_nWRP_8 0x01000000U
+#define FLASH_OPTCR_nWRP_9 0x02000000U
+#define FLASH_OPTCR_nWRP_10 0x04000000U
+#define FLASH_OPTCR_nWRP_11 0x08000000U
+
+/****************** Bits definition for FLASH_OPTCR1 register ***************/
+#define FLASH_OPTCR1_nWRP 0x0FFF0000U
+#define FLASH_OPTCR1_nWRP_0 0x00010000U
+#define FLASH_OPTCR1_nWRP_1 0x00020000U
+#define FLASH_OPTCR1_nWRP_2 0x00040000U
+#define FLASH_OPTCR1_nWRP_3 0x00080000U
+#define FLASH_OPTCR1_nWRP_4 0x00100000U
+#define FLASH_OPTCR1_nWRP_5 0x00200000U
+#define FLASH_OPTCR1_nWRP_6 0x00400000U
+#define FLASH_OPTCR1_nWRP_7 0x00800000U
+#define FLASH_OPTCR1_nWRP_8 0x01000000U
+#define FLASH_OPTCR1_nWRP_9 0x02000000U
+#define FLASH_OPTCR1_nWRP_10 0x04000000U
+#define FLASH_OPTCR1_nWRP_11 0x08000000U
+
+/******************************************************************************/
+/* */
+/* General Purpose I/O */
+/* */
+/******************************************************************************/
+/****************** Bits definition for GPIO_MODER register *****************/
+#define GPIO_MODER_MODER0 0x00000003U
+#define GPIO_MODER_MODER0_0 0x00000001U
+#define GPIO_MODER_MODER0_1 0x00000002U
+
+#define GPIO_MODER_MODER1 0x0000000CU
+#define GPIO_MODER_MODER1_0 0x00000004U
+#define GPIO_MODER_MODER1_1 0x00000008U
+
+#define GPIO_MODER_MODER2 0x00000030U
+#define GPIO_MODER_MODER2_0 0x00000010U
+#define GPIO_MODER_MODER2_1 0x00000020U
+
+#define GPIO_MODER_MODER3 0x000000C0U
+#define GPIO_MODER_MODER3_0 0x00000040U
+#define GPIO_MODER_MODER3_1 0x00000080U
+
+#define GPIO_MODER_MODER4 0x00000300U
+#define GPIO_MODER_MODER4_0 0x00000100U
+#define GPIO_MODER_MODER4_1 0x00000200U
+
+#define GPIO_MODER_MODER5 0x00000C00U
+#define GPIO_MODER_MODER5_0 0x00000400U
+#define GPIO_MODER_MODER5_1 0x00000800U
+
+#define GPIO_MODER_MODER6 0x00003000U
+#define GPIO_MODER_MODER6_0 0x00001000U
+#define GPIO_MODER_MODER6_1 0x00002000U
+
+#define GPIO_MODER_MODER7 0x0000C000U
+#define GPIO_MODER_MODER7_0 0x00004000U
+#define GPIO_MODER_MODER7_1 0x00008000U
+
+#define GPIO_MODER_MODER8 0x00030000U
+#define GPIO_MODER_MODER8_0 0x00010000U
+#define GPIO_MODER_MODER8_1 0x00020000U
+
+#define GPIO_MODER_MODER9 0x000C0000U
+#define GPIO_MODER_MODER9_0 0x00040000U
+#define GPIO_MODER_MODER9_1 0x00080000U
+
+#define GPIO_MODER_MODER10 0x00300000U
+#define GPIO_MODER_MODER10_0 0x00100000U
+#define GPIO_MODER_MODER10_1 0x00200000U
+
+#define GPIO_MODER_MODER11 0x00C00000U
+#define GPIO_MODER_MODER11_0 0x00400000U
+#define GPIO_MODER_MODER11_1 0x00800000U
+
+#define GPIO_MODER_MODER12 0x03000000U
+#define GPIO_MODER_MODER12_0 0x01000000U
+#define GPIO_MODER_MODER12_1 0x02000000U
+
+#define GPIO_MODER_MODER13 0x0C000000U
+#define GPIO_MODER_MODER13_0 0x04000000U
+#define GPIO_MODER_MODER13_1 0x08000000U
+
+#define GPIO_MODER_MODER14 0x30000000U
+#define GPIO_MODER_MODER14_0 0x10000000U
+#define GPIO_MODER_MODER14_1 0x20000000U
+
+#define GPIO_MODER_MODER15 0xC0000000U
+#define GPIO_MODER_MODER15_0 0x40000000U
+#define GPIO_MODER_MODER15_1 0x80000000U
+
+/****************** Bits definition for GPIO_OTYPER register ****************/
+#define GPIO_OTYPER_OT_0 0x00000001U
+#define GPIO_OTYPER_OT_1 0x00000002U
+#define GPIO_OTYPER_OT_2 0x00000004U
+#define GPIO_OTYPER_OT_3 0x00000008U
+#define GPIO_OTYPER_OT_4 0x00000010U
+#define GPIO_OTYPER_OT_5 0x00000020U
+#define GPIO_OTYPER_OT_6 0x00000040U
+#define GPIO_OTYPER_OT_7 0x00000080U
+#define GPIO_OTYPER_OT_8 0x00000100U
+#define GPIO_OTYPER_OT_9 0x00000200U
+#define GPIO_OTYPER_OT_10 0x00000400U
+#define GPIO_OTYPER_OT_11 0x00000800U
+#define GPIO_OTYPER_OT_12 0x00001000U
+#define GPIO_OTYPER_OT_13 0x00002000U
+#define GPIO_OTYPER_OT_14 0x00004000U
+#define GPIO_OTYPER_OT_15 0x00008000U
+
+/****************** Bits definition for GPIO_OSPEEDR register ***************/
+#define GPIO_OSPEEDER_OSPEEDR0 0x00000003U
+#define GPIO_OSPEEDER_OSPEEDR0_0 0x00000001U
+#define GPIO_OSPEEDER_OSPEEDR0_1 0x00000002U
+
+#define GPIO_OSPEEDER_OSPEEDR1 0x0000000CU
+#define GPIO_OSPEEDER_OSPEEDR1_0 0x00000004U
+#define GPIO_OSPEEDER_OSPEEDR1_1 0x00000008U
+
+#define GPIO_OSPEEDER_OSPEEDR2 0x00000030U
+#define GPIO_OSPEEDER_OSPEEDR2_0 0x00000010U
+#define GPIO_OSPEEDER_OSPEEDR2_1 0x00000020U
+
+#define GPIO_OSPEEDER_OSPEEDR3 0x000000C0U
+#define GPIO_OSPEEDER_OSPEEDR3_0 0x00000040U
+#define GPIO_OSPEEDER_OSPEEDR3_1 0x00000080U
+
+#define GPIO_OSPEEDER_OSPEEDR4 0x00000300U
+#define GPIO_OSPEEDER_OSPEEDR4_0 0x00000100U
+#define GPIO_OSPEEDER_OSPEEDR4_1 0x00000200U
+
+#define GPIO_OSPEEDER_OSPEEDR5 0x00000C00U
+#define GPIO_OSPEEDER_OSPEEDR5_0 0x00000400U
+#define GPIO_OSPEEDER_OSPEEDR5_1 0x00000800U
+
+#define GPIO_OSPEEDER_OSPEEDR6 0x00003000U
+#define GPIO_OSPEEDER_OSPEEDR6_0 0x00001000U
+#define GPIO_OSPEEDER_OSPEEDR6_1 0x00002000U
+
+#define GPIO_OSPEEDER_OSPEEDR7 0x0000C000U
+#define GPIO_OSPEEDER_OSPEEDR7_0 0x00004000U
+#define GPIO_OSPEEDER_OSPEEDR7_1 0x00008000U
+
+#define GPIO_OSPEEDER_OSPEEDR8 0x00030000U
+#define GPIO_OSPEEDER_OSPEEDR8_0 0x00010000U
+#define GPIO_OSPEEDER_OSPEEDR8_1 0x00020000U
+
+#define GPIO_OSPEEDER_OSPEEDR9 0x000C0000U
+#define GPIO_OSPEEDER_OSPEEDR9_0 0x00040000U
+#define GPIO_OSPEEDER_OSPEEDR9_1 0x00080000U
+
+#define GPIO_OSPEEDER_OSPEEDR10 0x00300000U
+#define GPIO_OSPEEDER_OSPEEDR10_0 0x00100000U
+#define GPIO_OSPEEDER_OSPEEDR10_1 0x00200000U
+
+#define GPIO_OSPEEDER_OSPEEDR11 0x00C00000U
+#define GPIO_OSPEEDER_OSPEEDR11_0 0x00400000U
+#define GPIO_OSPEEDER_OSPEEDR11_1 0x00800000U
+
+#define GPIO_OSPEEDER_OSPEEDR12 0x03000000U
+#define GPIO_OSPEEDER_OSPEEDR12_0 0x01000000U
+#define GPIO_OSPEEDER_OSPEEDR12_1 0x02000000U
+
+#define GPIO_OSPEEDER_OSPEEDR13 0x0C000000U
+#define GPIO_OSPEEDER_OSPEEDR13_0 0x04000000U
+#define GPIO_OSPEEDER_OSPEEDR13_1 0x08000000U
+
+#define GPIO_OSPEEDER_OSPEEDR14 0x30000000U
+#define GPIO_OSPEEDER_OSPEEDR14_0 0x10000000U
+#define GPIO_OSPEEDER_OSPEEDR14_1 0x20000000U
+
+#define GPIO_OSPEEDER_OSPEEDR15 0xC0000000U
+#define GPIO_OSPEEDER_OSPEEDR15_0 0x40000000U
+#define GPIO_OSPEEDER_OSPEEDR15_1 0x80000000U
+
+/****************** Bits definition for GPIO_PUPDR register *****************/
+#define GPIO_PUPDR_PUPDR0 0x00000003U
+#define GPIO_PUPDR_PUPDR0_0 0x00000001U
+#define GPIO_PUPDR_PUPDR0_1 0x00000002U
+
+#define GPIO_PUPDR_PUPDR1 0x0000000CU
+#define GPIO_PUPDR_PUPDR1_0 0x00000004U
+#define GPIO_PUPDR_PUPDR1_1 0x00000008U
+
+#define GPIO_PUPDR_PUPDR2 0x00000030U
+#define GPIO_PUPDR_PUPDR2_0 0x00000010U
+#define GPIO_PUPDR_PUPDR2_1 0x00000020U
+
+#define GPIO_PUPDR_PUPDR3 0x000000C0U
+#define GPIO_PUPDR_PUPDR3_0 0x00000040U
+#define GPIO_PUPDR_PUPDR3_1 0x00000080U
+
+#define GPIO_PUPDR_PUPDR4 0x00000300U
+#define GPIO_PUPDR_PUPDR4_0 0x00000100U
+#define GPIO_PUPDR_PUPDR4_1 0x00000200U
+
+#define GPIO_PUPDR_PUPDR5 0x00000C00U
+#define GPIO_PUPDR_PUPDR5_0 0x00000400U
+#define GPIO_PUPDR_PUPDR5_1 0x00000800U
+
+#define GPIO_PUPDR_PUPDR6 0x00003000U
+#define GPIO_PUPDR_PUPDR6_0 0x00001000U
+#define GPIO_PUPDR_PUPDR6_1 0x00002000U
+
+#define GPIO_PUPDR_PUPDR7 0x0000C000U
+#define GPIO_PUPDR_PUPDR7_0 0x00004000U
+#define GPIO_PUPDR_PUPDR7_1 0x00008000U
+
+#define GPIO_PUPDR_PUPDR8 0x00030000U
+#define GPIO_PUPDR_PUPDR8_0 0x00010000U
+#define GPIO_PUPDR_PUPDR8_1 0x00020000U
+
+#define GPIO_PUPDR_PUPDR9 0x000C0000U
+#define GPIO_PUPDR_PUPDR9_0 0x00040000U
+#define GPIO_PUPDR_PUPDR9_1 0x00080000U
+
+#define GPIO_PUPDR_PUPDR10 0x00300000U
+#define GPIO_PUPDR_PUPDR10_0 0x00100000U
+#define GPIO_PUPDR_PUPDR10_1 0x00200000U
+
+#define GPIO_PUPDR_PUPDR11 0x00C00000U
+#define GPIO_PUPDR_PUPDR11_0 0x00400000U
+#define GPIO_PUPDR_PUPDR11_1 0x00800000U
+
+#define GPIO_PUPDR_PUPDR12 0x03000000U
+#define GPIO_PUPDR_PUPDR12_0 0x01000000U
+#define GPIO_PUPDR_PUPDR12_1 0x02000000U
+
+#define GPIO_PUPDR_PUPDR13 0x0C000000U
+#define GPIO_PUPDR_PUPDR13_0 0x04000000U
+#define GPIO_PUPDR_PUPDR13_1 0x08000000U
+
+#define GPIO_PUPDR_PUPDR14 0x30000000U
+#define GPIO_PUPDR_PUPDR14_0 0x10000000U
+#define GPIO_PUPDR_PUPDR14_1 0x20000000U
+
+#define GPIO_PUPDR_PUPDR15 0xC0000000U
+#define GPIO_PUPDR_PUPDR15_0 0x40000000U
+#define GPIO_PUPDR_PUPDR15_1 0x80000000U
+
+/****************** Bits definition for GPIO_IDR register *******************/
+#define GPIO_IDR_IDR_0 0x00000001U
+#define GPIO_IDR_IDR_1 0x00000002U
+#define GPIO_IDR_IDR_2 0x00000004U
+#define GPIO_IDR_IDR_3 0x00000008U
+#define GPIO_IDR_IDR_4 0x00000010U
+#define GPIO_IDR_IDR_5 0x00000020U
+#define GPIO_IDR_IDR_6 0x00000040U
+#define GPIO_IDR_IDR_7 0x00000080U
+#define GPIO_IDR_IDR_8 0x00000100U
+#define GPIO_IDR_IDR_9 0x00000200U
+#define GPIO_IDR_IDR_10 0x00000400U
+#define GPIO_IDR_IDR_11 0x00000800U
+#define GPIO_IDR_IDR_12 0x00001000U
+#define GPIO_IDR_IDR_13 0x00002000U
+#define GPIO_IDR_IDR_14 0x00004000U
+#define GPIO_IDR_IDR_15 0x00008000U
+
+/****************** Bits definition for GPIO_ODR register *******************/
+#define GPIO_ODR_ODR_0 0x00000001U
+#define GPIO_ODR_ODR_1 0x00000002U
+#define GPIO_ODR_ODR_2 0x00000004U
+#define GPIO_ODR_ODR_3 0x00000008U
+#define GPIO_ODR_ODR_4 0x00000010U
+#define GPIO_ODR_ODR_5 0x00000020U
+#define GPIO_ODR_ODR_6 0x00000040U
+#define GPIO_ODR_ODR_7 0x00000080U
+#define GPIO_ODR_ODR_8 0x00000100U
+#define GPIO_ODR_ODR_9 0x00000200U
+#define GPIO_ODR_ODR_10 0x00000400U
+#define GPIO_ODR_ODR_11 0x00000800U
+#define GPIO_ODR_ODR_12 0x00001000U
+#define GPIO_ODR_ODR_13 0x00002000U
+#define GPIO_ODR_ODR_14 0x00004000U
+#define GPIO_ODR_ODR_15 0x00008000U
+
+/****************** Bits definition for GPIO_BSRR register ******************/
+#define GPIO_BSRR_BS_0 0x00000001U
+#define GPIO_BSRR_BS_1 0x00000002U
+#define GPIO_BSRR_BS_2 0x00000004U
+#define GPIO_BSRR_BS_3 0x00000008U
+#define GPIO_BSRR_BS_4 0x00000010U
+#define GPIO_BSRR_BS_5 0x00000020U
+#define GPIO_BSRR_BS_6 0x00000040U
+#define GPIO_BSRR_BS_7 0x00000080U
+#define GPIO_BSRR_BS_8 0x00000100U
+#define GPIO_BSRR_BS_9 0x00000200U
+#define GPIO_BSRR_BS_10 0x00000400U
+#define GPIO_BSRR_BS_11 0x00000800U
+#define GPIO_BSRR_BS_12 0x00001000U
+#define GPIO_BSRR_BS_13 0x00002000U
+#define GPIO_BSRR_BS_14 0x00004000U
+#define GPIO_BSRR_BS_15 0x00008000U
+#define GPIO_BSRR_BR_0 0x00010000U
+#define GPIO_BSRR_BR_1 0x00020000U
+#define GPIO_BSRR_BR_2 0x00040000U
+#define GPIO_BSRR_BR_3 0x00080000U
+#define GPIO_BSRR_BR_4 0x00100000U
+#define GPIO_BSRR_BR_5 0x00200000U
+#define GPIO_BSRR_BR_6 0x00400000U
+#define GPIO_BSRR_BR_7 0x00800000U
+#define GPIO_BSRR_BR_8 0x01000000U
+#define GPIO_BSRR_BR_9 0x02000000U
+#define GPIO_BSRR_BR_10 0x04000000U
+#define GPIO_BSRR_BR_11 0x08000000U
+#define GPIO_BSRR_BR_12 0x10000000U
+#define GPIO_BSRR_BR_13 0x20000000U
+#define GPIO_BSRR_BR_14 0x40000000U
+#define GPIO_BSRR_BR_15 0x80000000U
+
+/****************** Bit definition for GPIO_LCKR register *********************/
+#define GPIO_LCKR_LCK0 0x00000001U
+#define GPIO_LCKR_LCK1 0x00000002U
+#define GPIO_LCKR_LCK2 0x00000004U
+#define GPIO_LCKR_LCK3 0x00000008U
+#define GPIO_LCKR_LCK4 0x00000010U
+#define GPIO_LCKR_LCK5 0x00000020U
+#define GPIO_LCKR_LCK6 0x00000040U
+#define GPIO_LCKR_LCK7 0x00000080U
+#define GPIO_LCKR_LCK8 0x00000100U
+#define GPIO_LCKR_LCK9 0x00000200U
+#define GPIO_LCKR_LCK10 0x00000400U
+#define GPIO_LCKR_LCK11 0x00000800U
+#define GPIO_LCKR_LCK12 0x00001000U
+#define GPIO_LCKR_LCK13 0x00002000U
+#define GPIO_LCKR_LCK14 0x00004000U
+#define GPIO_LCKR_LCK15 0x00008000U
+#define GPIO_LCKR_LCKK 0x00010000U
+
+/******************************************************************************/
+/* */
+/* Inter-integrated Circuit Interface */
+/* */
+/******************************************************************************/
+/******************* Bit definition for I2C_CR1 register ********************/
+#define I2C_CR1_PE 0x00000001U /*!<Peripheral Enable */
+#define I2C_CR1_SMBUS 0x00000002U /*!<SMBus Mode */
+#define I2C_CR1_SMBTYPE 0x00000008U /*!<SMBus Type */
+#define I2C_CR1_ENARP 0x00000010U /*!<ARP Enable */
+#define I2C_CR1_ENPEC 0x00000020U /*!<PEC Enable */
+#define I2C_CR1_ENGC 0x00000040U /*!<General Call Enable */
+#define I2C_CR1_NOSTRETCH 0x00000080U /*!<Clock Stretching Disable (Slave mode) */
+#define I2C_CR1_START 0x00000100U /*!<Start Generation */
+#define I2C_CR1_STOP 0x00000200U /*!<Stop Generation */
+#define I2C_CR1_ACK 0x00000400U /*!<Acknowledge Enable */
+#define I2C_CR1_POS 0x00000800U /*!<Acknowledge/PEC Position (for data reception) */
+#define I2C_CR1_PEC 0x00001000U /*!<Packet Error Checking */
+#define I2C_CR1_ALERT 0x00002000U /*!<SMBus Alert */
+#define I2C_CR1_SWRST 0x00008000U /*!<Software Reset */
+
+/******************* Bit definition for I2C_CR2 register ********************/
+#define I2C_CR2_FREQ 0x0000003FU /*!<FREQ[5:0] bits (Peripheral Clock Frequency) */
+#define I2C_CR2_FREQ_0 0x00000001U /*!<Bit 0 */
+#define I2C_CR2_FREQ_1 0x00000002U /*!<Bit 1 */
+#define I2C_CR2_FREQ_2 0x00000004U /*!<Bit 2 */
+#define I2C_CR2_FREQ_3 0x00000008U /*!<Bit 3 */
+#define I2C_CR2_FREQ_4 0x00000010U /*!<Bit 4 */
+#define I2C_CR2_FREQ_5 0x00000020U /*!<Bit 5 */
+
+#define I2C_CR2_ITERREN 0x00000100U /*!<Error Interrupt Enable */
+#define I2C_CR2_ITEVTEN 0x00000200U /*!<Event Interrupt Enable */
+#define I2C_CR2_ITBUFEN 0x00000400U /*!<Buffer Interrupt Enable */
+#define I2C_CR2_DMAEN 0x00000800U /*!<DMA Requests Enable */
+#define I2C_CR2_LAST 0x00001000U /*!<DMA Last Transfer */
+
+/******************* Bit definition for I2C_OAR1 register *******************/
+#define I2C_OAR1_ADD1_7 0x000000FEU /*!<Interface Address */
+#define I2C_OAR1_ADD8_9 0x00000300U /*!<Interface Address */
+
+#define I2C_OAR1_ADD0 0x00000001U /*!<Bit 0 */
+#define I2C_OAR1_ADD1 0x00000002U /*!<Bit 1 */
+#define I2C_OAR1_ADD2 0x00000004U /*!<Bit 2 */
+#define I2C_OAR1_ADD3 0x00000008U /*!<Bit 3 */
+#define I2C_OAR1_ADD4 0x00000010U /*!<Bit 4 */
+#define I2C_OAR1_ADD5 0x00000020U /*!<Bit 5 */
+#define I2C_OAR1_ADD6 0x00000040U /*!<Bit 6 */
+#define I2C_OAR1_ADD7 0x00000080U /*!<Bit 7 */
+#define I2C_OAR1_ADD8 0x00000100U /*!<Bit 8 */
+#define I2C_OAR1_ADD9 0x00000200U /*!<Bit 9 */
+
+#define I2C_OAR1_ADDMODE 0x00008000U /*!<Addressing Mode (Slave mode) */
+
+/******************* Bit definition for I2C_OAR2 register *******************/
+#define I2C_OAR2_ENDUAL 0x00000001U /*!<Dual addressing mode enable */
+#define I2C_OAR2_ADD2 0x000000FEU /*!<Interface address */
+
+/******************** Bit definition for I2C_DR register ********************/
+#define I2C_DR_DR 0x000000FFU /*!<8-bit Data Register */
+
+/******************* Bit definition for I2C_SR1 register ********************/
+#define I2C_SR1_SB 0x00000001U /*!<Start Bit (Master mode) */
+#define I2C_SR1_ADDR 0x00000002U /*!<Address sent (master mode)/matched (slave mode) */
+#define I2C_SR1_BTF 0x00000004U /*!<Byte Transfer Finished */
+#define I2C_SR1_ADD10 0x00000008U /*!<10-bit header sent (Master mode) */
+#define I2C_SR1_STOPF 0x00000010U /*!<Stop detection (Slave mode) */
+#define I2C_SR1_RXNE 0x00000040U /*!<Data Register not Empty (receivers) */
+#define I2C_SR1_TXE 0x00000080U /*!<Data Register Empty (transmitters) */
+#define I2C_SR1_BERR 0x00000100U /*!<Bus Error */
+#define I2C_SR1_ARLO 0x00000200U /*!<Arbitration Lost (master mode) */
+#define I2C_SR1_AF 0x00000400U /*!<Acknowledge Failure */
+#define I2C_SR1_OVR 0x00000800U /*!<Overrun/Underrun */
+#define I2C_SR1_PECERR 0x00001000U /*!<PEC Error in reception */
+#define I2C_SR1_TIMEOUT 0x00004000U /*!<Timeout or Tlow Error */
+#define I2C_SR1_SMBALERT 0x00008000U /*!<SMBus Alert */
+
+/******************* Bit definition for I2C_SR2 register ********************/
+#define I2C_SR2_MSL 0x00000001U /*!<Master/Slave */
+#define I2C_SR2_BUSY 0x00000002U /*!<Bus Busy */
+#define I2C_SR2_TRA 0x00000004U /*!<Transmitter/Receiver */
+#define I2C_SR2_GENCALL 0x00000010U /*!<General Call Address (Slave mode) */
+#define I2C_SR2_SMBDEFAULT 0x00000020U /*!<SMBus Device Default Address (Slave mode) */
+#define I2C_SR2_SMBHOST 0x00000040U /*!<SMBus Host Header (Slave mode) */
+#define I2C_SR2_DUALF 0x00000080U /*!<Dual Flag (Slave mode) */
+#define I2C_SR2_PEC 0x0000FF00U /*!<Packet Error Checking Register */
+
+/******************* Bit definition for I2C_CCR register ********************/
+#define I2C_CCR_CCR 0x00000FFFU /*!<Clock Control Register in Fast/Standard mode (Master mode) */
+#define I2C_CCR_DUTY 0x00004000U /*!<Fast Mode Duty Cycle */
+#define I2C_CCR_FS 0x00008000U /*!<I2C Master Mode Selection */
+
+/****************** Bit definition for I2C_TRISE register *******************/
+#define I2C_TRISE_TRISE 0x0000003FU /*!<Maximum Rise Time in Fast/Standard mode (Master mode) */
+
+/****************** Bit definition for I2C_FLTR register *******************/
+#define I2C_FLTR_DNF 0x0000000FU /*!<Digital Noise Filter */
+#define I2C_FLTR_ANOFF 0x00000010U /*!<Analog Noise Filter OFF */
+
+/******************************************************************************/
+/* */
+/* Fast Mode Plus Inter-integrated Circuit Interface (I2C) */
+/* */
+/******************************************************************************/
+/******************* Bit definition for I2C_CR1 register *******************/
+#define FMPI2C_CR1_PE 0x00000001U /*!< Peripheral enable */
+#define FMPI2C_CR1_TXIE 0x00000002U /*!< TX interrupt enable */
+#define FMPI2C_CR1_RXIE 0x00000004U /*!< RX interrupt enable */
+#define FMPI2C_CR1_ADDRIE 0x00000008U /*!< Address match interrupt enable */
+#define FMPI2C_CR1_NACKIE 0x00000010U /*!< NACK received interrupt enable */
+#define FMPI2C_CR1_STOPIE 0x00000020U /*!< STOP detection interrupt enable */
+#define FMPI2C_CR1_TCIE 0x00000040U /*!< Transfer complete interrupt enable */
+#define FMPI2C_CR1_ERRIE 0x00000080U /*!< Errors interrupt enable */
+#define FMPI2C_CR1_DFN 0x00000F00U /*!< Digital noise filter */
+#define FMPI2C_CR1_ANFOFF 0x00001000U /*!< Analog noise filter OFF */
+#define FMPI2C_CR1_TXDMAEN 0x00004000U /*!< DMA transmission requests enable */
+#define FMPI2C_CR1_RXDMAEN 0x00008000U /*!< DMA reception requests enable */
+#define FMPI2C_CR1_SBC 0x00010000U /*!< Slave byte control */
+#define FMPI2C_CR1_NOSTRETCH 0x00020000U /*!< Clock stretching disable */
+#define FMPI2C_CR1_GCEN 0x00080000U /*!< General call enable */
+#define FMPI2C_CR1_ALERTEN 0x00400000U /*!< SMBus alert enable */
+#define FMPI2C_CR1_PECEN 0x00800000U /*!< PEC enable */
+
+/****************** Bit definition for I2C_CR2 register ********************/
+#define FMPI2C_CR2_SADD 0x000003FFU /*!< Slave address (master mode) */
+#define FMPI2C_CR2_RD_WRN 0x00000400U /*!< Transfer direction (master mode) */
+#define FMPI2C_CR2_ADD10 0x00000800U /*!< 10-bit addressing mode (master mode) */
+#define FMPI2C_CR2_HEAD10R 0x00001000U /*!< 10-bit address header only read direction (master mode) */
+#define FMPI2C_CR2_START 0x00002000U /*!< START generation */
+#define FMPI2C_CR2_STOP 0x00004000U /*!< STOP generation (master mode) */
+#define FMPI2C_CR2_NACK 0x00008000U /*!< NACK generation (slave mode) */
+#define FMPI2C_CR2_NBYTES 0x00FF0000U /*!< Number of bytes */
+#define FMPI2C_CR2_RELOAD 0x01000000U /*!< NBYTES reload mode */
+#define FMPI2C_CR2_AUTOEND 0x02000000U /*!< Automatic end mode (master mode) */
+#define FMPI2C_CR2_PECBYTE 0x04000000U /*!< Packet error checking byte */
+
+/******************* Bit definition for I2C_OAR1 register ******************/
+#define FMPI2C_OAR1_OA1 0x000003FFU /*!< Interface own address 1 */
+#define FMPI2C_OAR1_OA1MODE 0x00000400U /*!< Own address 1 10-bit mode */
+#define FMPI2C_OAR1_OA1EN 0x00008000U /*!< Own address 1 enable */
+
+/******************* Bit definition for I2C_OAR2 register ******************/
+#define FMPI2C_OAR2_OA2 0x000000FEU /*!< Interface own address 2 */
+#define FMPI2C_OAR2_OA2MSK 0x00000700U /*!< Own address 2 masks */
+#define FMPI2C_OAR2_OA2EN 0x00008000U /*!< Own address 2 enable */
+
+/******************* Bit definition for I2C_TIMINGR register *******************/
+#define FMPI2C_TIMINGR_SCLL 0x000000FFU /*!< SCL low period (master mode) */
+#define FMPI2C_TIMINGR_SCLH 0x0000FF00U /*!< SCL high period (master mode) */
+#define FMPI2C_TIMINGR_SDADEL 0x000F0000U /*!< Data hold time */
+#define FMPI2C_TIMINGR_SCLDEL 0x00F00000U /*!< Data setup time */
+#define FMPI2C_TIMINGR_PRESC 0xF0000000U /*!< Timings prescaler */
+
+/******************* Bit definition for I2C_TIMEOUTR register *******************/
+#define FMPI2C_TIMEOUTR_TIMEOUTA 0x00000FFFU /*!< Bus timeout A */
+#define FMPI2C_TIMEOUTR_TIDLE 0x00001000U /*!< Idle clock timeout detection */
+#define FMPI2C_TIMEOUTR_TIMOUTEN 0x00008000U /*!< Clock timeout enable */
+#define FMPI2C_TIMEOUTR_TIMEOUTB 0x0FFF0000U /*!< Bus timeout B */
+#define FMPI2C_TIMEOUTR_TEXTEN 0x80000000U /*!< Extended clock timeout enable */
+
+/****************** Bit definition for I2C_ISR register *********************/
+#define FMPI2C_ISR_TXE 0x00000001U /*!< Transmit data register empty */
+#define FMPI2C_ISR_TXIS 0x00000002U /*!< Transmit interrupt status */
+#define FMPI2C_ISR_RXNE 0x00000004U /*!< Receive data register not empty */
+#define FMPI2C_ISR_ADDR 0x00000008U /*!< Address matched (slave mode) */
+#define FMPI2C_ISR_NACKF 0x00000010U /*!< NACK received flag */
+#define FMPI2C_ISR_STOPF 0x00000020U /*!< STOP detection flag */
+#define FMPI2C_ISR_TC 0x00000040U /*!< Transfer complete (master mode) */
+#define FMPI2C_ISR_TCR 0x00000080U /*!< Transfer complete reload */
+#define FMPI2C_ISR_BERR 0x00000100U /*!< Bus error */
+#define FMPI2C_ISR_ARLO 0x00000200U /*!< Arbitration lost */
+#define FMPI2C_ISR_OVR 0x00000400U /*!< Overrun/Underrun */
+#define FMPI2C_ISR_PECERR 0x00000800U /*!< PEC error in reception */
+#define FMPI2C_ISR_TIMEOUT 0x00001000U /*!< Timeout or Tlow detection flag */
+#define FMPI2C_ISR_ALERT 0x00002000U /*!< SMBus alert */
+#define FMPI2C_ISR_BUSY 0x00008000U /*!< Bus busy */
+#define FMPI2C_ISR_DIR 0x00010000U /*!< Transfer direction (slave mode) */
+#define FMPI2C_ISR_ADDCODE 0x00FE0000U /*!< Address match code (slave mode) */
+
+/****************** Bit definition for I2C_ICR register *********************/
+#define FMPI2C_ICR_ADDRCF 0x00000008U /*!< Address matched clear flag */
+#define FMPI2C_ICR_NACKCF 0x00000010U /*!< NACK clear flag */
+#define FMPI2C_ICR_STOPCF 0x00000020U /*!< STOP detection clear flag */
+#define FMPI2C_ICR_BERRCF 0x00000100U /*!< Bus error clear flag */
+#define FMPI2C_ICR_ARLOCF 0x00000200U /*!< Arbitration lost clear flag */
+#define FMPI2C_ICR_OVRCF 0x00000400U /*!< Overrun/Underrun clear flag */
+#define FMPI2C_ICR_PECCF 0x00000800U /*!< PAC error clear flag */
+#define FMPI2C_ICR_TIMOUTCF 0x00001000U /*!< Timeout clear flag */
+#define FMPI2C_ICR_ALERTCF 0x00002000U /*!< Alert clear flag */
+
+/****************** Bit definition for I2C_PECR register *********************/
+#define FMPI2C_PECR_PEC 0x000000FFU /*!< PEC register */
+
+/****************** Bit definition for I2C_RXDR register *********************/
+#define FMPI2C_RXDR_RXDATA 0x000000FFU /*!< 8-bit receive data */
+
+/****************** Bit definition for I2C_TXDR register *********************/
+#define FMPI2C_TXDR_TXDATA 0x000000FFU /*!< 8-bit transmit data */
+
+/******************************************************************************/
+/* */
+/* Independent WATCHDOG */
+/* */
+/******************************************************************************/
+/******************* Bit definition for IWDG_KR register ********************/
+#define IWDG_KR_KEY 0xFFFFU /*!<Key value (write only, read 0000h) */
+
+/******************* Bit definition for IWDG_PR register ********************/
+#define IWDG_PR_PR 0x07U /*!<PR[2:0] (Prescaler divider) */
+#define IWDG_PR_PR_0 0x01U /*!<Bit 0 */
+#define IWDG_PR_PR_1 0x02U /*!<Bit 1 */
+#define IWDG_PR_PR_2 0x04U /*!<Bit 2 */
+
+/******************* Bit definition for IWDG_RLR register *******************/
+#define IWDG_RLR_RL 0x0FFFU /*!<Watchdog counter reload value */
+
+/******************* Bit definition for IWDG_SR register ********************/
+#define IWDG_SR_PVU 0x01U /*!<Watchdog prescaler value update */
+#define IWDG_SR_RVU 0x02U /*!<Watchdog counter reload value update */
+
+
+/******************************************************************************/
+/* */
+/* Power Control */
+/* */
+/******************************************************************************/
+/******************** Bit definition for PWR_CR register ********************/
+#define PWR_CR_LPDS 0x00000001U /*!< Low-Power Deepsleep */
+#define PWR_CR_PDDS 0x00000002U /*!< Power Down Deepsleep */
+#define PWR_CR_CWUF 0x00000004U /*!< Clear Wakeup Flag */
+#define PWR_CR_CSBF 0x00000008U /*!< Clear Standby Flag */
+#define PWR_CR_PVDE 0x00000010U /*!< Power Voltage Detector Enable */
+
+#define PWR_CR_PLS 0x000000E0U /*!< PLS[2:0] bits (PVD Level Selection) */
+#define PWR_CR_PLS_0 0x00000020U /*!< Bit 0 */
+#define PWR_CR_PLS_1 0x00000040U /*!< Bit 1 */
+#define PWR_CR_PLS_2 0x00000080U /*!< Bit 2 */
+
+/*!< PVD level configuration */
+#define PWR_CR_PLS_LEV0 0x00000000U /*!< PVD level 0 */
+#define PWR_CR_PLS_LEV1 0x00000020U /*!< PVD level 1 */
+#define PWR_CR_PLS_LEV2 0x00000040U /*!< PVD level 2 */
+#define PWR_CR_PLS_LEV3 0x00000060U /*!< PVD level 3 */
+#define PWR_CR_PLS_LEV4 0x00000080U /*!< PVD level 4 */
+#define PWR_CR_PLS_LEV5 0x000000A0U /*!< PVD level 5 */
+#define PWR_CR_PLS_LEV6 0x000000C0U /*!< PVD level 6 */
+#define PWR_CR_PLS_LEV7 0x000000E0U /*!< PVD level 7 */
+
+#define PWR_CR_DBP 0x00000100U /*!< Disable Backup Domain write protection */
+#define PWR_CR_FPDS 0x00000200U /*!< Flash power down in Stop mode */
+#define PWR_CR_LPLVDS 0x00000400U /*!< Low Power Regulator Low Voltage in Deep Sleep mode */
+#define PWR_CR_MRLVDS 0x00000800U /*!< Main Regulator Low Voltage in Deep Sleep mode */
+#define PWR_CR_ADCDC1 0x00002000U /*!< Refer to AN4073 on how to use this bit */
+
+#define PWR_CR_VOS 0x0000C000U /*!< VOS[1:0] bits (Regulator voltage scaling output selection) */
+#define PWR_CR_VOS_0 0x00004000U /*!< Bit 0 */
+#define PWR_CR_VOS_1 0x00008000U /*!< Bit 1 */
+
+#define PWR_CR_FMSSR 0x00100000U /*!< Flash Memory Sleep System Run */
+#define PWR_CR_FISSR 0x00200000U /*!< Flash Interface Stop while System Run */
+/* Legacy define */
+#define PWR_CR_PMODE PWR_CR_VOS
+
+/******************* Bit definition for PWR_CSR register ********************/
+#define PWR_CSR_WUF 0x00000001U /*!< Wakeup Flag */
+#define PWR_CSR_SBF 0x00000002U /*!< Standby Flag */
+#define PWR_CSR_PVDO 0x00000004U /*!< PVD Output */
+#define PWR_CSR_BRR 0x00000008U /*!< Backup regulator ready */
+#define PWR_CSR_EWUP 0x00000100U /*!< Enable WKUP pin */
+#define PWR_CSR_BRE 0x00000200U /*!< Backup regulator enable */
+#define PWR_CSR_VOSRDY 0x00004000U /*!< Regulator voltage scaling output selection ready */
+
+/* Legacy define */
+#define PWR_CSR_REGRDY PWR_CSR_VOSRDY
+
+/******************************************************************************/
+/* */
+/* Reset and Clock Control */
+/* */
+/******************************************************************************/
+/******************** Bit definition for RCC_CR register ********************/
+#define RCC_CR_HSION 0x00000001U
+#define RCC_CR_HSIRDY 0x00000002U
+
+#define RCC_CR_HSITRIM 0x000000F8U
+#define RCC_CR_HSITRIM_0 0x00000008U/*!<Bit 0 */
+#define RCC_CR_HSITRIM_1 0x00000010U/*!<Bit 1 */
+#define RCC_CR_HSITRIM_2 0x00000020U/*!<Bit 2 */
+#define RCC_CR_HSITRIM_3 0x00000040U/*!<Bit 3 */
+#define RCC_CR_HSITRIM_4 0x00000080U/*!<Bit 4 */
+
+#define RCC_CR_HSICAL 0x0000FF00U
+#define RCC_CR_HSICAL_0 0x00000100U/*!<Bit 0 */
+#define RCC_CR_HSICAL_1 0x00000200U/*!<Bit 1 */
+#define RCC_CR_HSICAL_2 0x00000400U/*!<Bit 2 */
+#define RCC_CR_HSICAL_3 0x00000800U/*!<Bit 3 */
+#define RCC_CR_HSICAL_4 0x00001000U/*!<Bit 4 */
+#define RCC_CR_HSICAL_5 0x00002000U/*!<Bit 5 */
+#define RCC_CR_HSICAL_6 0x00004000U/*!<Bit 6 */
+#define RCC_CR_HSICAL_7 0x00008000U/*!<Bit 7 */
+
+#define RCC_CR_HSEON 0x00010000U
+#define RCC_CR_HSERDY 0x00020000U
+#define RCC_CR_HSEBYP 0x00040000U
+#define RCC_CR_CSSON 0x00080000U
+#define RCC_CR_PLLON 0x01000000U
+#define RCC_CR_PLLRDY 0x02000000U
+
+/******************** Bit definition for RCC_PLLCFGR register ***************/
+#define RCC_PLLCFGR_PLLM 0x0000003FU
+#define RCC_PLLCFGR_PLLM_0 0x00000001U
+#define RCC_PLLCFGR_PLLM_1 0x00000002U
+#define RCC_PLLCFGR_PLLM_2 0x00000004U
+#define RCC_PLLCFGR_PLLM_3 0x00000008U
+#define RCC_PLLCFGR_PLLM_4 0x00000010U
+#define RCC_PLLCFGR_PLLM_5 0x00000020U
+
+#define RCC_PLLCFGR_PLLN 0x00007FC0U
+#define RCC_PLLCFGR_PLLN_0 0x00000040U
+#define RCC_PLLCFGR_PLLN_1 0x00000080U
+#define RCC_PLLCFGR_PLLN_2 0x00000100U
+#define RCC_PLLCFGR_PLLN_3 0x00000200U
+#define RCC_PLLCFGR_PLLN_4 0x00000400U
+#define RCC_PLLCFGR_PLLN_5 0x00000800U
+#define RCC_PLLCFGR_PLLN_6 0x00001000U
+#define RCC_PLLCFGR_PLLN_7 0x00002000U
+#define RCC_PLLCFGR_PLLN_8 0x00004000U
+
+#define RCC_PLLCFGR_PLLP 0x00030000U
+#define RCC_PLLCFGR_PLLP_0 0x00010000U
+#define RCC_PLLCFGR_PLLP_1 0x00020000U
+
+#define RCC_PLLCFGR_PLLSRC 0x00400000U
+#define RCC_PLLCFGR_PLLSRC_HSE 0x00400000U
+#define RCC_PLLCFGR_PLLSRC_HSI 0x00000000U
+
+#define RCC_PLLCFGR_PLLQ 0x0F000000U
+#define RCC_PLLCFGR_PLLQ_0 0x01000000U
+#define RCC_PLLCFGR_PLLQ_1 0x02000000U
+#define RCC_PLLCFGR_PLLQ_2 0x04000000U
+#define RCC_PLLCFGR_PLLQ_3 0x08000000U
+
+#define RCC_PLLCFGR_PLLR 0x70000000U
+#define RCC_PLLCFGR_PLLR_0 0x10000000U
+#define RCC_PLLCFGR_PLLR_1 0x20000000U
+#define RCC_PLLCFGR_PLLR_2 0x40000000U
+/******************** Bit definition for RCC_CFGR register ******************/
+/*!< SW configuration */
+#define RCC_CFGR_SW 0x00000003U /*!< SW[1:0] bits (System clock Switch) */
+#define RCC_CFGR_SW_0 0x00000001U /*!< Bit 0 */
+#define RCC_CFGR_SW_1 0x00000002U /*!< Bit 1 */
+
+#define RCC_CFGR_SW_HSI 0x00000000U /*!< HSI selected as system clock */
+#define RCC_CFGR_SW_HSE 0x00000001U /*!< HSE selected as system clock */
+#define RCC_CFGR_SW_PLL 0x00000002U /*!< PLL selected as system clock */
+
+/*!< SWS configuration */
+#define RCC_CFGR_SWS 0x0000000CU /*!< SWS[1:0] bits (System Clock Switch Status) */
+#define RCC_CFGR_SWS_0 0x00000004U /*!< Bit 0 */
+#define RCC_CFGR_SWS_1 0x00000008U /*!< Bit 1 */
+
+#define RCC_CFGR_SWS_HSI 0x00000000U /*!< HSI oscillator used as system clock */
+#define RCC_CFGR_SWS_HSE 0x00000004U /*!< HSE oscillator used as system clock */
+#define RCC_CFGR_SWS_PLL 0x00000008U /*!< PLL used as system clock */
+
+/*!< HPRE configuration */
+#define RCC_CFGR_HPRE 0x000000F0U /*!< HPRE[3:0] bits (AHB prescaler) */
+#define RCC_CFGR_HPRE_0 0x00000010U /*!< Bit 0 */
+#define RCC_CFGR_HPRE_1 0x00000020U /*!< Bit 1 */
+#define RCC_CFGR_HPRE_2 0x00000040U /*!< Bit 2 */
+#define RCC_CFGR_HPRE_3 0x00000080U /*!< Bit 3 */
+
+#define RCC_CFGR_HPRE_DIV1 0x00000000U /*!< SYSCLK not divided */
+#define RCC_CFGR_HPRE_DIV2 0x00000080U /*!< SYSCLK divided by 2 */
+#define RCC_CFGR_HPRE_DIV4 0x00000090U /*!< SYSCLK divided by 4 */
+#define RCC_CFGR_HPRE_DIV8 0x000000A0U /*!< SYSCLK divided by 8 */
+#define RCC_CFGR_HPRE_DIV16 0x000000B0U /*!< SYSCLK divided by 16 */
+#define RCC_CFGR_HPRE_DIV64 0x000000C0U /*!< SYSCLK divided by 64 */
+#define RCC_CFGR_HPRE_DIV128 0x000000D0U /*!< SYSCLK divided by 128 */
+#define RCC_CFGR_HPRE_DIV256 0x000000E0U /*!< SYSCLK divided by 256 */
+#define RCC_CFGR_HPRE_DIV512 0x000000F0U /*!< SYSCLK divided by 512 */
+
+/*!< MCO1EN configuration */
+#define RCC_CFGR_MCO1EN 0x00000100U /*!< MCO1EN bit */
+
+/*!< PPRE1 configuration */
+#define RCC_CFGR_PPRE1 0x00001C00U /*!< PRE1[2:0] bits (APB1 prescaler) */
+#define RCC_CFGR_PPRE1_0 0x00000400U /*!< Bit 0 */
+#define RCC_CFGR_PPRE1_1 0x00000800U /*!< Bit 1 */
+#define RCC_CFGR_PPRE1_2 0x00001000U /*!< Bit 2 */
+
+#define RCC_CFGR_PPRE1_DIV1 0x00000000U /*!< HCLK not divided */
+#define RCC_CFGR_PPRE1_DIV2 0x00001000U /*!< HCLK divided by 2 */
+#define RCC_CFGR_PPRE1_DIV4 0x00001400U /*!< HCLK divided by 4 */
+#define RCC_CFGR_PPRE1_DIV8 0x00001800U /*!< HCLK divided by 8 */
+#define RCC_CFGR_PPRE1_DIV16 0x00001C00U /*!< HCLK divided by 16 */
+
+/*!< PPRE2 configuration */
+#define RCC_CFGR_PPRE2 0x0000E000U /*!< PRE2[2:0] bits (APB2 prescaler) */
+#define RCC_CFGR_PPRE2_0 0x00002000U /*!< Bit 0 */
+#define RCC_CFGR_PPRE2_1 0x00004000U /*!< Bit 1 */
+#define RCC_CFGR_PPRE2_2 0x00008000U /*!< Bit 2 */
+
+#define RCC_CFGR_PPRE2_DIV1 0x00000000U /*!< HCLK not divided */
+#define RCC_CFGR_PPRE2_DIV2 0x00008000U /*!< HCLK divided by 2 */
+#define RCC_CFGR_PPRE2_DIV4 0x0000A000U /*!< HCLK divided by 4 */
+#define RCC_CFGR_PPRE2_DIV8 0x0000C000U /*!< HCLK divided by 8 */
+#define RCC_CFGR_PPRE2_DIV16 0x0000E000U /*!< HCLK divided by 16 */
+
+/*!< RTCPRE configuration */
+#define RCC_CFGR_RTCPRE 0x001F0000U
+#define RCC_CFGR_RTCPRE_0 0x00010000U
+#define RCC_CFGR_RTCPRE_1 0x00020000U
+#define RCC_CFGR_RTCPRE_2 0x00040000U
+#define RCC_CFGR_RTCPRE_3 0x00080000U
+#define RCC_CFGR_RTCPRE_4 0x00100000U
+
+/*!< MCO1 configuration */
+#define RCC_CFGR_MCO1 0x00600000U
+#define RCC_CFGR_MCO1_0 0x00200000U
+#define RCC_CFGR_MCO1_1 0x00400000U
+
+#define RCC_CFGR_MCO1PRE 0x07000000U
+#define RCC_CFGR_MCO1PRE_0 0x01000000U
+#define RCC_CFGR_MCO1PRE_1 0x02000000U
+#define RCC_CFGR_MCO1PRE_2 0x04000000U
+
+#define RCC_CFGR_MCO2PRE 0x38000000U
+#define RCC_CFGR_MCO2PRE_0 0x08000000U
+#define RCC_CFGR_MCO2PRE_1 0x10000000U
+#define RCC_CFGR_MCO2PRE_2 0x20000000U
+
+#define RCC_CFGR_MCO2 0xC0000000U
+#define RCC_CFGR_MCO2_0 0x40000000U
+#define RCC_CFGR_MCO2_1 0x80000000U
+
+/******************** Bit definition for RCC_CIR register *******************/
+#define RCC_CIR_LSIRDYF 0x00000001U
+#define RCC_CIR_LSERDYF 0x00000002U
+#define RCC_CIR_HSIRDYF 0x00000004U
+#define RCC_CIR_HSERDYF 0x00000008U
+#define RCC_CIR_PLLRDYF 0x00000010U
+
+#define RCC_CIR_CSSF 0x00000080U
+#define RCC_CIR_LSIRDYIE 0x00000100U
+#define RCC_CIR_LSERDYIE 0x00000200U
+#define RCC_CIR_HSIRDYIE 0x00000400U
+#define RCC_CIR_HSERDYIE 0x00000800U
+#define RCC_CIR_PLLRDYIE 0x00001000U
+
+#define RCC_CIR_LSIRDYC 0x00010000U
+#define RCC_CIR_LSERDYC 0x00020000U
+#define RCC_CIR_HSIRDYC 0x00040000U
+#define RCC_CIR_HSERDYC 0x00080000U
+#define RCC_CIR_PLLRDYC 0x00100000U
+
+#define RCC_CIR_CSSC 0x00800000U
+
+/******************** Bit definition for RCC_AHB1RSTR register **************/
+#define RCC_AHB1RSTR_GPIOARST 0x00000001U
+#define RCC_AHB1RSTR_GPIOBRST 0x00000002U
+#define RCC_AHB1RSTR_GPIOCRST 0x00000004U
+#define RCC_AHB1RSTR_GPIOHRST 0x00000080U
+#define RCC_AHB1RSTR_CRCRST 0x00001000U
+#define RCC_AHB1RSTR_DMA1RST 0x00200000U
+#define RCC_AHB1RSTR_DMA2RST 0x00400000U
+#define RCC_AHB1RSTR_RNGRST 0x80000000U
+
+/******************** Bit definition for RCC_APB1RSTR register **************/
+#define RCC_APB1RSTR_TIM5RST 0x00000008U
+#define RCC_APB1RSTR_TIM6RST 0x00000010U
+#define RCC_APB1RSTR_LPTIM1RST 0x00000200U
+#define RCC_APB1RSTR_WWDGRST 0x00000800U
+#define RCC_APB1RSTR_USART2RST 0x00020000U
+#define RCC_APB1RSTR_I2C1RST 0x00200000U
+#define RCC_APB1RSTR_I2C2RST 0x00400000U
+#define RCC_APB1RSTR_FMPI2C1RST 0x01000000U
+#define RCC_APB1RSTR_PWRRST 0x10000000U
+#define RCC_APB1RSTR_DACRST 0x20000000U
+
+/******************** Bit definition for RCC_APB2RSTR register **************/
+#define RCC_APB2RSTR_TIM1RST 0x00000001U
+#define RCC_APB2RSTR_USART1RST 0x00000010U
+#define RCC_APB2RSTR_ADCRST 0x00000100U
+#define RCC_APB2RSTR_SPI1RST 0x00001000U
+#define RCC_APB2RSTR_SYSCFGRST 0x00004000U
+#define RCC_APB2RSTR_TIM9RST 0x00010000U
+#define RCC_APB2RSTR_TIM11RST 0x00040000U
+
+/******************** Bit definition for RCC_AHB1ENR register ***************/
+#define RCC_AHB1ENR_GPIOAEN 0x00000001U
+#define RCC_AHB1ENR_GPIOBEN 0x00000002U
+#define RCC_AHB1ENR_GPIOCEN 0x00000004U
+#define RCC_AHB1ENR_GPIOHEN 0x00000080U
+#define RCC_AHB1ENR_CRCEN 0x00001000U
+#define RCC_AHB1ENR_DMA1EN 0x00200000U
+#define RCC_AHB1ENR_DMA2EN 0x00400000U
+#define RCC_AHB1ENR_RNGEN 0x80000000U
+
+/******************** Bit definition for RCC_APB1ENR register ***************/
+#define RCC_APB1ENR_TIM5EN 0x00000008U
+#define RCC_APB1ENR_TIM6EN 0x00000010U
+#define RCC_APB1ENR_LPTIM1EN 0x00000200U
+#define RCC_APB1ENR_RTCAPBEN 0x00000400U
+#define RCC_APB1ENR_WWDGEN 0x00000800U
+#define RCC_APB1ENR_USART2EN 0x00020000U
+#define RCC_APB1ENR_I2C1EN 0x00200000U
+#define RCC_APB1ENR_I2C2EN 0x00400000U
+#define RCC_APB1ENR_FMPI2C1EN 0x01000000U
+#define RCC_APB1ENR_PWREN 0x10000000U
+#define RCC_APB1ENR_DACEN 0x20000000U
+
+/******************** Bit definition for RCC_APB2ENR register ***************/
+#define RCC_APB2ENR_TIM1EN 0x00000001U
+#define RCC_APB2ENR_USART1EN 0x00000010U
+#define RCC_APB2ENR_ADC1EN 0x00000100U
+#define RCC_APB2ENR_SPI1EN 0x00001000U
+#define RCC_APB2ENR_SYSCFGEN 0x00004000U
+#define RCC_APB2ENR_EXTITEN 0x00008000U
+#define RCC_APB2ENR_TIM9EN 0x00010000U
+#define RCC_APB2ENR_TIM11EN 0x00040000U
+
+/******************** Bit definition for RCC_AHB1LPENR register *************/
+#define RCC_AHB1LPENR_GPIOALPEN 0x00000001U
+#define RCC_AHB1LPENR_GPIOBLPEN 0x00000002U
+#define RCC_AHB1LPENR_GPIOCLPEN 0x00000004U
+#define RCC_AHB1LPENR_GPIOHLPEN 0x00000080U
+#define RCC_AHB1LPENR_CRCLPEN 0x00001000U
+#define RCC_AHB1LPENR_FLITFLPEN 0x00008000U
+#define RCC_AHB1LPENR_SRAM1LPEN 0x00010000U
+#define RCC_AHB1LPENR_DMA1LPEN 0x00200000U
+#define RCC_AHB1LPENR_DMA2LPEN 0x00400000U
+#define RCC_AHB1LPENR_RNGLPEN 0x80000000U
+
+/******************** Bit definition for RCC_APB1LPENR register *************/
+#define RCC_APB1LPENR_TIM5LPEN 0x00000008U
+#define RCC_APB1LPENR_TIM6LPEN 0x00000010U
+#define RCC_APB1LPENR_LPTIM1LPEN 0x00000200U
+#define RCC_APB1LPENR_RTCAPBLPEN 0x00000400U
+#define RCC_APB1LPENR_WWDGLPEN 0x00000800U
+#define RCC_APB1LPENR_USART2LPEN 0x00020000U
+#define RCC_APB1LPENR_I2C1LPEN 0x00200000U
+#define RCC_APB1LPENR_I2C2LPEN 0x00400000U
+#define RCC_APB1LPENR_FMPI2C1LPEN 0x01000000U
+#define RCC_APB1LPENR_PWRLPEN 0x10000000U
+#define RCC_APB1LPENR_DACLPEN 0x20000000U
+
+/******************** Bit definition for RCC_APB2LPENR register *************/
+#define RCC_APB2LPENR_TIM1LPEN 0x00000001U
+#define RCC_APB2LPENR_USART1LPEN 0x00000010U
+#define RCC_APB2LPENR_ADC1LPEN 0x00000100U
+#define RCC_APB2LPENR_SPI1LPEN 0x00001000U
+#define RCC_APB2LPENR_SYSCFGLPEN 0x00004000U
+#define RCC_APB2LPENR_EXTITLPEN 0x00008000U
+#define RCC_APB2LPENR_TIM9LPEN 0x00010000U
+#define RCC_APB2LPENR_TIM11LPEN 0x00040000U
+
+/******************** Bit definition for RCC_BDCR register ******************/
+#define RCC_BDCR_LSEON 0x00000001U
+#define RCC_BDCR_LSERDY 0x00000002U
+#define RCC_BDCR_LSEBYP 0x00000004U
+#define RCC_BDCR_LSEMOD 0x00000008U
+
+#define RCC_BDCR_RTCSEL 0x00000300U
+#define RCC_BDCR_RTCSEL_0 0x00000100U
+#define RCC_BDCR_RTCSEL_1 0x00000200U
+
+#define RCC_BDCR_RTCEN 0x00008000U
+#define RCC_BDCR_BDRST 0x00010000U
+
+/******************** Bit definition for RCC_CSR register *******************/
+#define RCC_CSR_LSION 0x00000001U
+#define RCC_CSR_LSIRDY 0x00000002U
+#define RCC_CSR_RMVF 0x01000000U
+#define RCC_CSR_BORRSTF 0x02000000U
+#define RCC_CSR_PADRSTF 0x04000000U
+#define RCC_CSR_PORRSTF 0x08000000U
+#define RCC_CSR_SFTRSTF 0x10000000U
+#define RCC_CSR_WDGRSTF 0x20000000U
+#define RCC_CSR_WWDGRSTF 0x40000000U
+#define RCC_CSR_LPWRRSTF 0x80000000U
+
+/******************** Bit definition for RCC_SSCGR register *****************/
+#define RCC_SSCGR_MODPER 0x00001FFFU
+#define RCC_SSCGR_INCSTEP 0x0FFFE000U
+#define RCC_SSCGR_SPREADSEL 0x40000000U
+#define RCC_SSCGR_SSCGEN 0x80000000U
+
+/******************** Bit definition for RCC_DCKCFGR register ***************/
+#define RCC_DCKCFGR_TIMPRE 0x01000000U
+#define RCC_DCKCFGR_I2SSRC 0x06000000U
+#define RCC_DCKCFGR_I2SSRC_0 0x02000000U
+#define RCC_DCKCFGR_I2SSRC_1 0x04000000U
+
+/******************** Bit definition for RCC_CKGATENR register **************/
+#define RCC_CKGATENR_AHB2APB1_CKEN 0x00000001U
+#define RCC_CKGATENR_AHB2APB2_CKEN 0x00000002U
+#define RCC_CKGATENR_CM4DBG_CKEN 0x00000004U
+#define RCC_CKGATENR_SPARE_CKEN 0x00000008U
+#define RCC_CKGATENR_SRAM_CKEN 0x00000010U
+#define RCC_CKGATENR_FLITF_CKEN 0x00000020U
+#define RCC_CKGATENR_RCC_CKEN 0x00000040U
+
+/******************** Bit definition for RCC_DCKCFGR2 register **************/
+#define RCC_DCKCFGR2_FMPI2C1SEL 0x00C00000U
+#define RCC_DCKCFGR2_FMPI2C1SEL_0 0x00400000U
+#define RCC_DCKCFGR2_FMPI2C1SEL_1 0x00800000U
+#define RCC_DCKCFGR2_LPTIM1SEL 0xC0000000U
+#define RCC_DCKCFGR2_LPTIM1SEL_0 0x40000000U
+#define RCC_DCKCFGR2_LPTIM1SEL_1 0x80000000U
+
+/******************************************************************************/
+/* */
+/* RNG */
+/* */
+/******************************************************************************/
+/******************** Bits definition for RNG_CR register *******************/
+#define RNG_CR_RNGEN 0x00000004U
+#define RNG_CR_IE 0x00000008U
+
+/******************** Bits definition for RNG_SR register *******************/
+#define RNG_SR_DRDY 0x00000001U
+#define RNG_SR_CECS 0x00000002U
+#define RNG_SR_SECS 0x00000004U
+#define RNG_SR_CEIS 0x00000020U
+#define RNG_SR_SEIS 0x00000040U
+
+/******************************************************************************/
+/* */
+/* Real-Time Clock (RTC) */
+/* */
+/******************************************************************************/
+/******************** Bits definition for RTC_TR register *******************/
+#define RTC_TR_PM 0x00400000U
+#define RTC_TR_HT 0x00300000U
+#define RTC_TR_HT_0 0x00100000U
+#define RTC_TR_HT_1 0x00200000U
+#define RTC_TR_HU 0x000F0000U
+#define RTC_TR_HU_0 0x00010000U
+#define RTC_TR_HU_1 0x00020000U
+#define RTC_TR_HU_2 0x00040000U
+#define RTC_TR_HU_3 0x00080000U
+#define RTC_TR_MNT 0x00007000U
+#define RTC_TR_MNT_0 0x00001000U
+#define RTC_TR_MNT_1 0x00002000U
+#define RTC_TR_MNT_2 0x00004000U
+#define RTC_TR_MNU 0x00000F00U
+#define RTC_TR_MNU_0 0x00000100U
+#define RTC_TR_MNU_1 0x00000200U
+#define RTC_TR_MNU_2 0x00000400U
+#define RTC_TR_MNU_3 0x00000800U
+#define RTC_TR_ST 0x00000070U
+#define RTC_TR_ST_0 0x00000010U
+#define RTC_TR_ST_1 0x00000020U
+#define RTC_TR_ST_2 0x00000040U
+#define RTC_TR_SU 0x0000000FU
+#define RTC_TR_SU_0 0x00000001U
+#define RTC_TR_SU_1 0x00000002U
+#define RTC_TR_SU_2 0x00000004U
+#define RTC_TR_SU_3 0x00000008U
+
+/******************** Bits definition for RTC_DR register *******************/
+#define RTC_DR_YT 0x00F00000U
+#define RTC_DR_YT_0 0x00100000U
+#define RTC_DR_YT_1 0x00200000U
+#define RTC_DR_YT_2 0x00400000U
+#define RTC_DR_YT_3 0x00800000U
+#define RTC_DR_YU 0x000F0000U
+#define RTC_DR_YU_0 0x00010000U
+#define RTC_DR_YU_1 0x00020000U
+#define RTC_DR_YU_2 0x00040000U
+#define RTC_DR_YU_3 0x00080000U
+#define RTC_DR_WDU 0x0000E000U
+#define RTC_DR_WDU_0 0x00002000U
+#define RTC_DR_WDU_1 0x00004000U
+#define RTC_DR_WDU_2 0x00008000U
+#define RTC_DR_MT 0x00001000U
+#define RTC_DR_MU 0x00000F00U
+#define RTC_DR_MU_0 0x00000100U
+#define RTC_DR_MU_1 0x00000200U
+#define RTC_DR_MU_2 0x00000400U
+#define RTC_DR_MU_3 0x00000800U
+#define RTC_DR_DT 0x00000030U
+#define RTC_DR_DT_0 0x00000010U
+#define RTC_DR_DT_1 0x00000020U
+#define RTC_DR_DU 0x0000000FU
+#define RTC_DR_DU_0 0x00000001U
+#define RTC_DR_DU_1 0x00000002U
+#define RTC_DR_DU_2 0x00000004U
+#define RTC_DR_DU_3 0x00000008U
+
+/******************** Bits definition for RTC_CR register *******************/
+#define RTC_CR_COE 0x00800000U
+#define RTC_CR_OSEL 0x00600000U
+#define RTC_CR_OSEL_0 0x00200000U
+#define RTC_CR_OSEL_1 0x00400000U
+#define RTC_CR_POL 0x00100000U
+#define RTC_CR_COSEL 0x00080000U
+#define RTC_CR_BCK 0x00040000U
+#define RTC_CR_SUB1H 0x00020000U
+#define RTC_CR_ADD1H 0x00010000U
+#define RTC_CR_TSIE 0x00008000U
+#define RTC_CR_WUTIE 0x00004000U
+#define RTC_CR_ALRBIE 0x00002000U
+#define RTC_CR_ALRAIE 0x00001000U
+#define RTC_CR_TSE 0x00000800U
+#define RTC_CR_WUTE 0x00000400U
+#define RTC_CR_ALRBE 0x00000200U
+#define RTC_CR_ALRAE 0x00000100U
+#define RTC_CR_DCE 0x00000080U
+#define RTC_CR_FMT 0x00000040U
+#define RTC_CR_BYPSHAD 0x00000020U
+#define RTC_CR_REFCKON 0x00000010U
+#define RTC_CR_TSEDGE 0x00000008U
+#define RTC_CR_WUCKSEL 0x00000007U
+#define RTC_CR_WUCKSEL_0 0x00000001U
+#define RTC_CR_WUCKSEL_1 0x00000002U
+#define RTC_CR_WUCKSEL_2 0x00000004U
+
+/******************** Bits definition for RTC_ISR register ******************/
+#define RTC_ISR_RECALPF 0x00010000U
+#define RTC_ISR_TAMP1F 0x00002000U
+#define RTC_ISR_TAMP2F 0x00004000U
+#define RTC_ISR_TSOVF 0x00001000U
+#define RTC_ISR_TSF 0x00000800U
+#define RTC_ISR_WUTF 0x00000400U
+#define RTC_ISR_ALRBF 0x00000200U
+#define RTC_ISR_ALRAF 0x00000100U
+#define RTC_ISR_INIT 0x00000080U
+#define RTC_ISR_INITF 0x00000040U
+#define RTC_ISR_RSF 0x00000020U
+#define RTC_ISR_INITS 0x00000010U
+#define RTC_ISR_SHPF 0x00000008U
+#define RTC_ISR_WUTWF 0x00000004U
+#define RTC_ISR_ALRBWF 0x00000002U
+#define RTC_ISR_ALRAWF 0x00000001U
+
+/******************** Bits definition for RTC_PRER register *****************/
+#define RTC_PRER_PREDIV_A 0x007F0000U
+#define RTC_PRER_PREDIV_S 0x00007FFFU
+
+/******************** Bits definition for RTC_WUTR register *****************/
+#define RTC_WUTR_WUT 0x0000FFFFU
+
+/******************** Bits definition for RTC_CALIBR register ***************/
+#define RTC_CALIBR_DCS 0x00000080U
+#define RTC_CALIBR_DC 0x0000001FU
+
+/******************** Bits definition for RTC_ALRMAR register ***************/
+#define RTC_ALRMAR_MSK4 0x80000000U
+#define RTC_ALRMAR_WDSEL 0x40000000U
+#define RTC_ALRMAR_DT 0x30000000U
+#define RTC_ALRMAR_DT_0 0x10000000U
+#define RTC_ALRMAR_DT_1 0x20000000U
+#define RTC_ALRMAR_DU 0x0F000000U
+#define RTC_ALRMAR_DU_0 0x01000000U
+#define RTC_ALRMAR_DU_1 0x02000000U
+#define RTC_ALRMAR_DU_2 0x04000000U
+#define RTC_ALRMAR_DU_3 0x08000000U
+#define RTC_ALRMAR_MSK3 0x00800000U
+#define RTC_ALRMAR_PM 0x00400000U
+#define RTC_ALRMAR_HT 0x00300000U
+#define RTC_ALRMAR_HT_0 0x00100000U
+#define RTC_ALRMAR_HT_1 0x00200000U
+#define RTC_ALRMAR_HU 0x000F0000U
+#define RTC_ALRMAR_HU_0 0x00010000U
+#define RTC_ALRMAR_HU_1 0x00020000U
+#define RTC_ALRMAR_HU_2 0x00040000U
+#define RTC_ALRMAR_HU_3 0x00080000U
+#define RTC_ALRMAR_MSK2 0x00008000U
+#define RTC_ALRMAR_MNT 0x00007000U
+#define RTC_ALRMAR_MNT_0 0x00001000U
+#define RTC_ALRMAR_MNT_1 0x00002000U
+#define RTC_ALRMAR_MNT_2 0x00004000U
+#define RTC_ALRMAR_MNU 0x00000F00U
+#define RTC_ALRMAR_MNU_0 0x00000100U
+#define RTC_ALRMAR_MNU_1 0x00000200U
+#define RTC_ALRMAR_MNU_2 0x00000400U
+#define RTC_ALRMAR_MNU_3 0x00000800U
+#define RTC_ALRMAR_MSK1 0x00000080U
+#define RTC_ALRMAR_ST 0x00000070U
+#define RTC_ALRMAR_ST_0 0x00000010U
+#define RTC_ALRMAR_ST_1 0x00000020U
+#define RTC_ALRMAR_ST_2 0x00000040U
+#define RTC_ALRMAR_SU 0x0000000FU
+#define RTC_ALRMAR_SU_0 0x00000001U
+#define RTC_ALRMAR_SU_1 0x00000002U
+#define RTC_ALRMAR_SU_2 0x00000004U
+#define RTC_ALRMAR_SU_3 0x00000008U
+
+/******************** Bits definition for RTC_ALRMBR register ***************/
+#define RTC_ALRMBR_MSK4 0x80000000U
+#define RTC_ALRMBR_WDSEL 0x40000000U
+#define RTC_ALRMBR_DT 0x30000000U
+#define RTC_ALRMBR_DT_0 0x10000000U
+#define RTC_ALRMBR_DT_1 0x20000000U
+#define RTC_ALRMBR_DU 0x0F000000U
+#define RTC_ALRMBR_DU_0 0x01000000U
+#define RTC_ALRMBR_DU_1 0x02000000U
+#define RTC_ALRMBR_DU_2 0x04000000U
+#define RTC_ALRMBR_DU_3 0x08000000U
+#define RTC_ALRMBR_MSK3 0x00800000U
+#define RTC_ALRMBR_PM 0x00400000U
+#define RTC_ALRMBR_HT 0x00300000U
+#define RTC_ALRMBR_HT_0 0x00100000U
+#define RTC_ALRMBR_HT_1 0x00200000U
+#define RTC_ALRMBR_HU 0x000F0000U
+#define RTC_ALRMBR_HU_0 0x00010000U
+#define RTC_ALRMBR_HU_1 0x00020000U
+#define RTC_ALRMBR_HU_2 0x00040000U
+#define RTC_ALRMBR_HU_3 0x00080000U
+#define RTC_ALRMBR_MSK2 0x00008000U
+#define RTC_ALRMBR_MNT 0x00007000U
+#define RTC_ALRMBR_MNT_0 0x00001000U
+#define RTC_ALRMBR_MNT_1 0x00002000U
+#define RTC_ALRMBR_MNT_2 0x00004000U
+#define RTC_ALRMBR_MNU 0x00000F00U
+#define RTC_ALRMBR_MNU_0 0x00000100U
+#define RTC_ALRMBR_MNU_1 0x00000200U
+#define RTC_ALRMBR_MNU_2 0x00000400U
+#define RTC_ALRMBR_MNU_3 0x00000800U
+#define RTC_ALRMBR_MSK1 0x00000080U
+#define RTC_ALRMBR_ST 0x00000070U
+#define RTC_ALRMBR_ST_0 0x00000010U
+#define RTC_ALRMBR_ST_1 0x00000020U
+#define RTC_ALRMBR_ST_2 0x00000040U
+#define RTC_ALRMBR_SU 0x0000000FU
+#define RTC_ALRMBR_SU_0 0x00000001U
+#define RTC_ALRMBR_SU_1 0x00000002U
+#define RTC_ALRMBR_SU_2 0x00000004U
+#define RTC_ALRMBR_SU_3 0x00000008U
+
+/******************** Bits definition for RTC_WPR register ******************/
+#define RTC_WPR_KEY 0x000000FFU
+
+/******************** Bits definition for RTC_SSR register ******************/
+#define RTC_SSR_SS 0x0000FFFFU
+
+/******************** Bits definition for RTC_SHIFTR register ***************/
+#define RTC_SHIFTR_SUBFS 0x00007FFFU
+#define RTC_SHIFTR_ADD1S 0x80000000U
+
+/******************** Bits definition for RTC_TSTR register *****************/
+#define RTC_TSTR_PM 0x00400000U
+#define RTC_TSTR_HT 0x00300000U
+#define RTC_TSTR_HT_0 0x00100000U
+#define RTC_TSTR_HT_1 0x00200000U
+#define RTC_TSTR_HU 0x000F0000U
+#define RTC_TSTR_HU_0 0x00010000U
+#define RTC_TSTR_HU_1 0x00020000U
+#define RTC_TSTR_HU_2 0x00040000U
+#define RTC_TSTR_HU_3 0x00080000U
+#define RTC_TSTR_MNT 0x00007000U
+#define RTC_TSTR_MNT_0 0x00001000U
+#define RTC_TSTR_MNT_1 0x00002000U
+#define RTC_TSTR_MNT_2 0x00004000U
+#define RTC_TSTR_MNU 0x00000F00U
+#define RTC_TSTR_MNU_0 0x00000100U
+#define RTC_TSTR_MNU_1 0x00000200U
+#define RTC_TSTR_MNU_2 0x00000400U
+#define RTC_TSTR_MNU_3 0x00000800U
+#define RTC_TSTR_ST 0x00000070U
+#define RTC_TSTR_ST_0 0x00000010U
+#define RTC_TSTR_ST_1 0x00000020U
+#define RTC_TSTR_ST_2 0x00000040U
+#define RTC_TSTR_SU 0x0000000FU
+#define RTC_TSTR_SU_0 0x00000001U
+#define RTC_TSTR_SU_1 0x00000002U
+#define RTC_TSTR_SU_2 0x00000004U
+#define RTC_TSTR_SU_3 0x00000008U
+
+/******************** Bits definition for RTC_TSDR register *****************/
+#define RTC_TSDR_WDU 0x0000E000U
+#define RTC_TSDR_WDU_0 0x00002000U
+#define RTC_TSDR_WDU_1 0x00004000U
+#define RTC_TSDR_WDU_2 0x00008000U
+#define RTC_TSDR_MT 0x00001000U
+#define RTC_TSDR_MU 0x00000F00U
+#define RTC_TSDR_MU_0 0x00000100U
+#define RTC_TSDR_MU_1 0x00000200U
+#define RTC_TSDR_MU_2 0x00000400U
+#define RTC_TSDR_MU_3 0x00000800U
+#define RTC_TSDR_DT 0x00000030U
+#define RTC_TSDR_DT_0 0x00000010U
+#define RTC_TSDR_DT_1 0x00000020U
+#define RTC_TSDR_DU 0x0000000FU
+#define RTC_TSDR_DU_0 0x00000001U
+#define RTC_TSDR_DU_1 0x00000002U
+#define RTC_TSDR_DU_2 0x00000004U
+#define RTC_TSDR_DU_3 0x00000008U
+
+/******************** Bits definition for RTC_TSSSR register ****************/
+#define RTC_TSSSR_SS 0x0000FFFFU
+
+/******************** Bits definition for RTC_CAL register *****************/
+#define RTC_CALR_CALP 0x00008000U
+#define RTC_CALR_CALW8 0x00004000U
+#define RTC_CALR_CALW16 0x00002000U
+#define RTC_CALR_CALM 0x000001FFU
+#define RTC_CALR_CALM_0 0x00000001U
+#define RTC_CALR_CALM_1 0x00000002U
+#define RTC_CALR_CALM_2 0x00000004U
+#define RTC_CALR_CALM_3 0x00000008U
+#define RTC_CALR_CALM_4 0x00000010U
+#define RTC_CALR_CALM_5 0x00000020U
+#define RTC_CALR_CALM_6 0x00000040U
+#define RTC_CALR_CALM_7 0x00000080U
+#define RTC_CALR_CALM_8 0x00000100U
+
+/******************** Bits definition for RTC_TAFCR register ****************/
+#define RTC_TAFCR_ALARMOUTTYPE 0x00040000U
+#define RTC_TAFCR_TSINSEL 0x00020000U
+#define RTC_TAFCR_TAMPINSEL 0x00010000U
+#define RTC_TAFCR_TAMPPUDIS 0x00008000U
+#define RTC_TAFCR_TAMPPRCH 0x00006000U
+#define RTC_TAFCR_TAMPPRCH_0 0x00002000U
+#define RTC_TAFCR_TAMPPRCH_1 0x00004000U
+#define RTC_TAFCR_TAMPFLT 0x00001800U
+#define RTC_TAFCR_TAMPFLT_0 0x00000800U
+#define RTC_TAFCR_TAMPFLT_1 0x00001000U
+#define RTC_TAFCR_TAMPFREQ 0x00000700U
+#define RTC_TAFCR_TAMPFREQ_0 0x00000100U
+#define RTC_TAFCR_TAMPFREQ_1 0x00000200U
+#define RTC_TAFCR_TAMPFREQ_2 0x00000400U
+#define RTC_TAFCR_TAMPTS 0x00000080U
+#define RTC_TAFCR_TAMP2TRG 0x00000010U
+#define RTC_TAFCR_TAMP2E 0x00000008U
+#define RTC_TAFCR_TAMPIE 0x00000004U
+#define RTC_TAFCR_TAMP1TRG 0x00000002U
+#define RTC_TAFCR_TAMP1E 0x00000001U
+
+/******************** Bits definition for RTC_ALRMASSR register *************/
+#define RTC_ALRMASSR_MASKSS 0x0F000000U
+#define RTC_ALRMASSR_MASKSS_0 0x01000000U
+#define RTC_ALRMASSR_MASKSS_1 0x02000000U
+#define RTC_ALRMASSR_MASKSS_2 0x04000000U
+#define RTC_ALRMASSR_MASKSS_3 0x08000000U
+#define RTC_ALRMASSR_SS 0x00007FFFU
+
+/******************** Bits definition for RTC_ALRMBSSR register *************/
+#define RTC_ALRMBSSR_MASKSS 0x0F000000U
+#define RTC_ALRMBSSR_MASKSS_0 0x01000000U
+#define RTC_ALRMBSSR_MASKSS_1 0x02000000U
+#define RTC_ALRMBSSR_MASKSS_2 0x04000000U
+#define RTC_ALRMBSSR_MASKSS_3 0x08000000U
+#define RTC_ALRMBSSR_SS 0x00007FFFU
+
+/******************** Bits definition for RTC_BKP0R register ****************/
+#define RTC_BKP0R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP1R register ****************/
+#define RTC_BKP1R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP2R register ****************/
+#define RTC_BKP2R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP3R register ****************/
+#define RTC_BKP3R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP4R register ****************/
+#define RTC_BKP4R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP5R register ****************/
+#define RTC_BKP5R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP6R register ****************/
+#define RTC_BKP6R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP7R register ****************/
+#define RTC_BKP7R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP8R register ****************/
+#define RTC_BKP8R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP9R register ****************/
+#define RTC_BKP9R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP10R register ***************/
+#define RTC_BKP10R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP11R register ***************/
+#define RTC_BKP11R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP12R register ***************/
+#define RTC_BKP12R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP13R register ***************/
+#define RTC_BKP13R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP14R register ***************/
+#define RTC_BKP14R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP15R register ***************/
+#define RTC_BKP15R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP16R register ***************/
+#define RTC_BKP16R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP17R register ***************/
+#define RTC_BKP17R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP18R register ***************/
+#define RTC_BKP18R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP19R register ***************/
+#define RTC_BKP19R 0xFFFFFFFFU
+
+/******************************************************************************/
+/* */
+/* Serial Peripheral Interface */
+/* */
+/******************************************************************************/
+/******************* Bit definition for SPI_CR1 register ********************/
+#define SPI_CR1_CPHA 0x00000001U /*!<Clock Phase */
+#define SPI_CR1_CPOL 0x00000002U /*!<Clock Polarity */
+#define SPI_CR1_MSTR 0x00000004U /*!<Master Selection */
+
+#define SPI_CR1_BR 0x00000038U /*!<BR[2:0] bits (Baud Rate Control) */
+#define SPI_CR1_BR_0 0x00000008U /*!<Bit 0 */
+#define SPI_CR1_BR_1 0x00000010U /*!<Bit 1 */
+#define SPI_CR1_BR_2 0x00000020U /*!<Bit 2 */
+
+#define SPI_CR1_SPE 0x00000040U /*!<SPI Enable */
+#define SPI_CR1_LSBFIRST 0x00000080U /*!<Frame Format */
+#define SPI_CR1_SSI 0x00000100U /*!<Internal slave select */
+#define SPI_CR1_SSM 0x00000200U /*!<Software slave management */
+#define SPI_CR1_RXONLY 0x00000400U /*!<Receive only */
+#define SPI_CR1_DFF 0x00000800U /*!<Data Frame Format */
+#define SPI_CR1_CRCNEXT 0x00001000U /*!<Transmit CRC next */
+#define SPI_CR1_CRCEN 0x00002000U /*!<Hardware CRC calculation enable */
+#define SPI_CR1_BIDIOE 0x00004000U /*!<Output enable in bidirectional mode */
+#define SPI_CR1_BIDIMODE 0x00008000U /*!<Bidirectional data mode enable */
+
+/******************* Bit definition for SPI_CR2 register ********************/
+#define SPI_CR2_RXDMAEN 0x00000001U /*!<Rx Buffer DMA Enable */
+#define SPI_CR2_TXDMAEN 0x00000002U /*!<Tx Buffer DMA Enable */
+#define SPI_CR2_SSOE 0x00000004U /*!<SS Output Enable */
+#define SPI_CR2_FRF 0x00000010U /*!<Frame Format */
+#define SPI_CR2_ERRIE 0x00000020U /*!<Error Interrupt Enable */
+#define SPI_CR2_RXNEIE 0x00000040U /*!<RX buffer Not Empty Interrupt Enable */
+#define SPI_CR2_TXEIE 0x00000080U /*!<Tx buffer Empty Interrupt Enable */
+
+/******************** Bit definition for SPI_SR register ********************/
+#define SPI_SR_RXNE 0x00000001U /*!<Receive buffer Not Empty */
+#define SPI_SR_TXE 0x00000002U /*!<Transmit buffer Empty */
+#define SPI_SR_CHSIDE 0x00000004U /*!<Channel side */
+#define SPI_SR_UDR 0x00000008U /*!<Underrun flag */
+#define SPI_SR_CRCERR 0x00000010U /*!<CRC Error flag */
+#define SPI_SR_MODF 0x00000020U /*!<Mode fault */
+#define SPI_SR_OVR 0x00000040U /*!<Overrun flag */
+#define SPI_SR_BSY 0x00000080U /*!<Busy flag */
+#define SPI_SR_FRE 0x00000100U /*!<Frame format error flag */
+
+/******************** Bit definition for SPI_DR register ********************/
+#define SPI_DR_DR 0x0000FFFFU /*!<Data Register */
+
+/******************* Bit definition for SPI_CRCPR register ******************/
+#define SPI_CRCPR_CRCPOLY 0x0000FFFFU /*!<CRC polynomial register */
+
+/****************** Bit definition for SPI_RXCRCR register ******************/
+#define SPI_RXCRCR_RXCRC 0x0000FFFFU /*!<Rx CRC Register */
+
+/****************** Bit definition for SPI_TXCRCR register ******************/
+#define SPI_TXCRCR_TXCRC 0x0000FFFFU /*!<Tx CRC Register */
+
+/****************** Bit definition for SPI_I2SCFGR register *****************/
+#define SPI_I2SCFGR_CHLEN 0x00000001U /*!<Channel length (number of bits per audio channel) */
+
+#define SPI_I2SCFGR_DATLEN 0x00000006U /*!<DATLEN[1:0] bits (Data length to be transferred) */
+#define SPI_I2SCFGR_DATLEN_0 0x00000002U /*!<Bit 0 */
+#define SPI_I2SCFGR_DATLEN_1 0x00000004U /*!<Bit 1 */
+
+#define SPI_I2SCFGR_CKPOL 0x00000008U /*!<steady state clock polarity */
+
+#define SPI_I2SCFGR_I2SSTD 0x00000030U /*!<I2SSTD[1:0] bits (I2S standard selection) */
+#define SPI_I2SCFGR_I2SSTD_0 0x00000010U /*!<Bit 0 */
+#define SPI_I2SCFGR_I2SSTD_1 0x00000020U /*!<Bit 1 */
+
+#define SPI_I2SCFGR_PCMSYNC 0x00000080U /*!<PCM frame synchronization */
+
+#define SPI_I2SCFGR_I2SCFG 0x00000300U /*!<I2SCFG[1:0] bits (I2S configuration mode) */
+#define SPI_I2SCFGR_I2SCFG_0 0x00000100U /*!<Bit 0 */
+#define SPI_I2SCFGR_I2SCFG_1 0x00000200U /*!<Bit 1 */
+
+#define SPI_I2SCFGR_I2SE 0x00000400U /*!<I2S Enable */
+#define SPI_I2SCFGR_I2SMOD 0x00000800U /*!<I2S mode selection */
+
+/****************** Bit definition for SPI_I2SPR register *******************/
+#define SPI_I2SPR_I2SDIV 0x000000FFU /*!<I2S Linear prescaler */
+#define SPI_I2SPR_ODD 0x00000100U /*!<Odd factor for the prescaler */
+#define SPI_I2SPR_MCKOE 0x00000200U /*!<Master Clock Output Enable */
+
+/******************************************************************************/
+/* */
+/* SYSCFG */
+/* */
+/******************************************************************************/
+/****************** Bit definition for SYSCFG_MEMRMP register ***************/
+#define SYSCFG_MEMRMP_MEM_MODE 0x00000007U /*!< SYSCFG_Memory Remap Config */
+#define SYSCFG_MEMRMP_MEM_MODE_0 0x00000001U
+#define SYSCFG_MEMRMP_MEM_MODE_1 0x00000002U
+#define SYSCFG_MEMRMP_MEM_MODE_2 0x00000004U
+
+/****************** Bit definition for SYSCFG_PMC register ******************/
+#define SYSCFG_PMC_ADC1DC2 0x00010000U /*!< Refer to AN4073 on how to use this bit */
+
+/***************** Bit definition for SYSCFG_EXTICR1 register ***************/
+#define SYSCFG_EXTICR1_EXTI0 0x000FU /*!<EXTI 0 configuration */
+#define SYSCFG_EXTICR1_EXTI1 0x00F0U /*!<EXTI 1 configuration */
+#define SYSCFG_EXTICR1_EXTI2 0x0F00U /*!<EXTI 2 configuration */
+#define SYSCFG_EXTICR1_EXTI3 0xF000U /*!<EXTI 3 configuration */
+/**
+ * @brief EXTI0 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI0_PA 0x0000U /*!<PA[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PB 0x0001U /*!<PB[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PC 0x0002U /*!<PC[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PH 0x0007U /*!<PH[0] pin */
+
+/**
+ * @brief EXTI1 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI1_PA 0x0000U /*!<PA[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PB 0x0010U /*!<PB[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PC 0x0020U /*!<PC[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PH 0x0070U /*!<PH[1] pin */
+
+/**
+ * @brief EXTI2 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI2_PA 0x0000U /*!<PA[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PB 0x0100U /*!<PB[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PC 0x0200U /*!<PC[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PH 0x0700U /*!<PH[2] pin */
+
+/**
+ * @brief EXTI3 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI3_PA 0x0000U /*!<PA[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PB 0x1000U /*!<PB[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PC 0x2000U /*!<PC[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PH 0x7000U /*!<PH[3] pin */
+
+/***************** Bit definition for SYSCFG_EXTICR2 register ***************/
+#define SYSCFG_EXTICR2_EXTI4 0x000FU /*!<EXTI 4 configuration */
+#define SYSCFG_EXTICR2_EXTI5 0x00F0U /*!<EXTI 5 configuration */
+#define SYSCFG_EXTICR2_EXTI6 0x0F00U /*!<EXTI 6 configuration */
+#define SYSCFG_EXTICR2_EXTI7 0xF000U /*!<EXTI 7 configuration */
+/**
+ * @brief EXTI4 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI4_PA 0x0000U /*!<PA[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PB 0x0001U /*!<PB[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PC 0x0002U /*!<PC[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PH 0x0007U /*!<PH[4] pin */
+
+/**
+ * @brief EXTI5 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI5_PA 0x0000U /*!<PA[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PB 0x0010U /*!<PB[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PC 0x0020U /*!<PC[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PH 0x0070U /*!<PH[5] pin */
+
+/**
+ * @brief EXTI6 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI6_PA 0x0000U /*!<PA[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PB 0x0100U /*!<PB[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PC 0x0200U /*!<PC[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PH 0x0700U /*!<PH[6] pin */
+
+/**
+ * @brief EXTI7 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI7_PA 0x0000U /*!<PA[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PB 0x1000U /*!<PB[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PC 0x2000U /*!<PC[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PH 0x7000U /*!<PH[7] pin */
+
+
+/***************** Bit definition for SYSCFG_EXTICR3 register ***************/
+#define SYSCFG_EXTICR3_EXTI8 0x000FU /*!<EXTI 8 configuration */
+#define SYSCFG_EXTICR3_EXTI9 0x00F0U /*!<EXTI 9 configuration */
+#define SYSCFG_EXTICR3_EXTI10 0x0F00U /*!<EXTI 10 configuration */
+#define SYSCFG_EXTICR3_EXTI11 0xF000U /*!<EXTI 11 configuration */
+
+/**
+ * @brief EXTI8 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI8_PA 0x0000U /*!<PA[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PB 0x0001U /*!<PB[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PC 0x0002U /*!<PC[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PH 0x0007U /*!<PH[8] pin */
+
+/**
+ * @brief EXTI9 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI9_PA 0x0000U /*!<PA[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PB 0x0010U /*!<PB[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PC 0x0020U /*!<PC[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PH 0x0070U /*!<PH[9] pin */
+
+/**
+ * @brief EXTI10 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI10_PA 0x0000U /*!<PA[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PB 0x0100U /*!<PB[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PC 0x0200U /*!<PC[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PH 0x0700U /*!<PH[10] pin */
+
+/**
+ * @brief EXTI11 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI11_PA 0x0000U /*!<PA[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PB 0x1000U /*!<PB[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PC 0x2000U /*!<PC[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PH 0x7000U /*!<PH[11] pin */
+
+/***************** Bit definition for SYSCFG_EXTICR4 register ***************/
+#define SYSCFG_EXTICR4_EXTI12 0x000FU /*!<EXTI 12 configuration */
+#define SYSCFG_EXTICR4_EXTI13 0x00F0U /*!<EXTI 13 configuration */
+#define SYSCFG_EXTICR4_EXTI14 0x0F00U /*!<EXTI 14 configuration */
+#define SYSCFG_EXTICR4_EXTI15 0xF000U /*!<EXTI 15 configuration */
+/**
+ * @brief EXTI12 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI12_PA 0x0000U /*!<PA[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PB 0x0001U /*!<PB[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PC 0x0002U /*!<PC[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PH 0x0007U /*!<PH[12] pin */
+
+/**
+ * @brief EXTI13 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI13_PA 0x0000U /*!<PA[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PB 0x0010U /*!<PB[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PC 0x0020U /*!<PC[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PH 0x0070U /*!<PH[13] pin */
+
+/**
+ * @brief EXTI14 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI14_PA 0x0000U /*!<PA[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PB 0x0100U /*!<PB[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PC 0x0200U /*!<PC[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PH 0x0700U /*!<PH[14] pin */
+
+/**
+ * @brief EXTI15 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI15_PA 0x0000U /*!<PA[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PB 0x1000U /*!<PB[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PC 0x2000U /*!<PC[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PH 0x7000U /*!<PH[15] pin */
+
+/****************** Bit definition for SYSCFG_CMPCR register ****************/
+#define SYSCFG_CMPCR_CMP_PD 0x00000001U /*!<Compensation cell ready flag */
+#define SYSCFG_CMPCR_READY 0x00000100U /*!<Compensation cell power-down */
+
+/****************** Bit definition for SYSCFG_CFGR register *****************/
+#define SYSCFG_CFGR_FMPI2C1_SCL 0x00000001U /*!<FM+ drive capability for FMPI2C1_SCL pin */
+#define SYSCFG_CFGR_FMPI2C1_SDA 0x00000002U /*!<FM+ drive capability for FMPI2C1_SDA pin */
+
+/****************** Bit definition for SYSCFG_CFGR2 register *****************/
+#define SYSCFG_CFGR2_LOCKUP_LOCK 0x00000001U /*!<Core Lockup lock */
+#define SYSCFG_CFGR2_PVD_LOCK 0x00000004U /*!<PVD Lock */
+
+/******************************************************************************/
+/* */
+/* TIM */
+/* */
+/******************************************************************************/
+/******************* Bit definition for TIM_CR1 register ********************/
+#define TIM_CR1_CEN 0x0001U /*!<Counter enable */
+#define TIM_CR1_UDIS 0x0002U /*!<Update disable */
+#define TIM_CR1_URS 0x0004U /*!<Update request source */
+#define TIM_CR1_OPM 0x0008U /*!<One pulse mode */
+#define TIM_CR1_DIR 0x0010U /*!<Direction */
+
+#define TIM_CR1_CMS 0x0060U /*!<CMS[1:0] bits (Center-aligned mode selection) */
+#define TIM_CR1_CMS_0 0x0020U /*!<Bit 0 */
+#define TIM_CR1_CMS_1 0x0040U /*!<Bit 1 */
+
+#define TIM_CR1_ARPE 0x0080U /*!<Auto-reload preload enable */
+
+#define TIM_CR1_CKD 0x0300U /*!<CKD[1:0] bits (clock division) */
+#define TIM_CR1_CKD_0 0x0100U /*!<Bit 0 */
+#define TIM_CR1_CKD_1 0x0200U /*!<Bit 1 */
+
+/******************* Bit definition for TIM_CR2 register ********************/
+#define TIM_CR2_CCPC 0x0001U /*!<Capture/Compare Preloaded Control */
+#define TIM_CR2_CCUS 0x0004U /*!<Capture/Compare Control Update Selection */
+#define TIM_CR2_CCDS 0x0008U /*!<Capture/Compare DMA Selection */
+
+#define TIM_CR2_MMS 0x0070U /*!<MMS[2:0] bits (Master Mode Selection) */
+#define TIM_CR2_MMS_0 0x0010U /*!<Bit 0 */
+#define TIM_CR2_MMS_1 0x0020U /*!<Bit 1 */
+#define TIM_CR2_MMS_2 0x0040U /*!<Bit 2 */
+
+#define TIM_CR2_TI1S 0x0080U /*!<TI1 Selection */
+#define TIM_CR2_OIS1 0x0100U /*!<Output Idle state 1 (OC1 output) */
+#define TIM_CR2_OIS1N 0x0200U /*!<Output Idle state 1 (OC1N output) */
+#define TIM_CR2_OIS2 0x0400U /*!<Output Idle state 2 (OC2 output) */
+#define TIM_CR2_OIS2N 0x0800U /*!<Output Idle state 2 (OC2N output) */
+#define TIM_CR2_OIS3 0x1000U /*!<Output Idle state 3 (OC3 output) */
+#define TIM_CR2_OIS3N 0x2000U /*!<Output Idle state 3 (OC3N output) */
+#define TIM_CR2_OIS4 0x4000U /*!<Output Idle state 4 (OC4 output) */
+
+/******************* Bit definition for TIM_SMCR register *******************/
+#define TIM_SMCR_SMS 0x0007U /*!<SMS[2:0] bits (Slave mode selection) */
+#define TIM_SMCR_SMS_0 0x0001U /*!<Bit 0 */
+#define TIM_SMCR_SMS_1 0x0002U /*!<Bit 1 */
+#define TIM_SMCR_SMS_2 0x0004U /*!<Bit 2 */
+
+#define TIM_SMCR_TS 0x0070U /*!<TS[2:0] bits (Trigger selection) */
+#define TIM_SMCR_TS_0 0x0010U /*!<Bit 0 */
+#define TIM_SMCR_TS_1 0x0020U /*!<Bit 1 */
+#define TIM_SMCR_TS_2 0x0040U /*!<Bit 2 */
+
+#define TIM_SMCR_MSM 0x0080U /*!<Master/slave mode */
+
+#define TIM_SMCR_ETF 0x0F00U /*!<ETF[3:0] bits (External trigger filter) */
+#define TIM_SMCR_ETF_0 0x0100U /*!<Bit 0 */
+#define TIM_SMCR_ETF_1 0x0200U /*!<Bit 1 */
+#define TIM_SMCR_ETF_2 0x0400U /*!<Bit 2 */
+#define TIM_SMCR_ETF_3 0x0800U /*!<Bit 3 */
+
+#define TIM_SMCR_ETPS 0x3000U /*!<ETPS[1:0] bits (External trigger prescaler) */
+#define TIM_SMCR_ETPS_0 0x1000U /*!<Bit 0 */
+#define TIM_SMCR_ETPS_1 0x2000U /*!<Bit 1 */
+
+#define TIM_SMCR_ECE 0x4000U /*!<External clock enable */
+#define TIM_SMCR_ETP 0x8000U /*!<External trigger polarity */
+
+/******************* Bit definition for TIM_DIER register *******************/
+#define TIM_DIER_UIE 0x0001U /*!<Update interrupt enable */
+#define TIM_DIER_CC1IE 0x0002U /*!<Capture/Compare 1 interrupt enable */
+#define TIM_DIER_CC2IE 0x0004U /*!<Capture/Compare 2 interrupt enable */
+#define TIM_DIER_CC3IE 0x0008U /*!<Capture/Compare 3 interrupt enable */
+#define TIM_DIER_CC4IE 0x0010U /*!<Capture/Compare 4 interrupt enable */
+#define TIM_DIER_COMIE 0x0020U /*!<COM interrupt enable */
+#define TIM_DIER_TIE 0x0040U /*!<Trigger interrupt enable */
+#define TIM_DIER_BIE 0x0080U /*!<Break interrupt enable */
+#define TIM_DIER_UDE 0x0100U /*!<Update DMA request enable */
+#define TIM_DIER_CC1DE 0x0200U /*!<Capture/Compare 1 DMA request enable */
+#define TIM_DIER_CC2DE 0x0400U /*!<Capture/Compare 2 DMA request enable */
+#define TIM_DIER_CC3DE 0x0800U /*!<Capture/Compare 3 DMA request enable */
+#define TIM_DIER_CC4DE 0x1000U /*!<Capture/Compare 4 DMA request enable */
+#define TIM_DIER_COMDE 0x2000U /*!<COM DMA request enable */
+#define TIM_DIER_TDE 0x4000U /*!<Trigger DMA request enable */
+
+/******************** Bit definition for TIM_SR register ********************/
+#define TIM_SR_UIF 0x0001U /*!<Update interrupt Flag */
+#define TIM_SR_CC1IF 0x0002U /*!<Capture/Compare 1 interrupt Flag */
+#define TIM_SR_CC2IF 0x0004U /*!<Capture/Compare 2 interrupt Flag */
+#define TIM_SR_CC3IF 0x0008U /*!<Capture/Compare 3 interrupt Flag */
+#define TIM_SR_CC4IF 0x0010U /*!<Capture/Compare 4 interrupt Flag */
+#define TIM_SR_COMIF 0x0020U /*!<COM interrupt Flag */
+#define TIM_SR_TIF 0x0040U /*!<Trigger interrupt Flag */
+#define TIM_SR_BIF 0x0080U /*!<Break interrupt Flag */
+#define TIM_SR_CC1OF 0x0200U /*!<Capture/Compare 1 Overcapture Flag */
+#define TIM_SR_CC2OF 0x0400U /*!<Capture/Compare 2 Overcapture Flag */
+#define TIM_SR_CC3OF 0x0800U /*!<Capture/Compare 3 Overcapture Flag */
+#define TIM_SR_CC4OF 0x1000U /*!<Capture/Compare 4 Overcapture Flag */
+
+/******************* Bit definition for TIM_EGR register ********************/
+#define TIM_EGR_UG 0x01U /*!<Update Generation */
+#define TIM_EGR_CC1G 0x02U /*!<Capture/Compare 1 Generation */
+#define TIM_EGR_CC2G 0x04U /*!<Capture/Compare 2 Generation */
+#define TIM_EGR_CC3G 0x08U /*!<Capture/Compare 3 Generation */
+#define TIM_EGR_CC4G 0x10U /*!<Capture/Compare 4 Generation */
+#define TIM_EGR_COMG 0x20U /*!<Capture/Compare Control Update Generation */
+#define TIM_EGR_TG 0x40U /*!<Trigger Generation */
+#define TIM_EGR_BG 0x80U /*!<Break Generation */
+
+/****************** Bit definition for TIM_CCMR1 register *******************/
+#define TIM_CCMR1_CC1S 0x0003U /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
+#define TIM_CCMR1_CC1S_0 0x0001U /*!<Bit 0 */
+#define TIM_CCMR1_CC1S_1 0x0002U /*!<Bit 1 */
+
+#define TIM_CCMR1_OC1FE 0x0004U /*!<Output Compare 1 Fast enable */
+#define TIM_CCMR1_OC1PE 0x0008U /*!<Output Compare 1 Preload enable */
+
+#define TIM_CCMR1_OC1M 0x0070U /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
+#define TIM_CCMR1_OC1M_0 0x0010U /*!<Bit 0 */
+#define TIM_CCMR1_OC1M_1 0x0020U /*!<Bit 1 */
+#define TIM_CCMR1_OC1M_2 0x0040U /*!<Bit 2 */
+
+#define TIM_CCMR1_OC1CE 0x0080U /*!<Output Compare 1Clear Enable */
+
+#define TIM_CCMR1_CC2S 0x0300U /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
+#define TIM_CCMR1_CC2S_0 0x0100U /*!<Bit 0 */
+#define TIM_CCMR1_CC2S_1 0x0200U /*!<Bit 1 */
+
+#define TIM_CCMR1_OC2FE 0x0400U /*!<Output Compare 2 Fast enable */
+#define TIM_CCMR1_OC2PE 0x0800U /*!<Output Compare 2 Preload enable */
+
+#define TIM_CCMR1_OC2M 0x7000U /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
+#define TIM_CCMR1_OC2M_0 0x1000U /*!<Bit 0 */
+#define TIM_CCMR1_OC2M_1 0x2000U /*!<Bit 1 */
+#define TIM_CCMR1_OC2M_2 0x4000U /*!<Bit 2 */
+
+#define TIM_CCMR1_OC2CE 0x8000U /*!<Output Compare 2 Clear Enable */
+
+/*----------------------------------------------------------------------------*/
+
+#define TIM_CCMR1_IC1PSC 0x000CU /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
+#define TIM_CCMR1_IC1PSC_0 0x0004U /*!<Bit 0 */
+#define TIM_CCMR1_IC1PSC_1 0x0008U /*!<Bit 1 */
+
+#define TIM_CCMR1_IC1F 0x00F0U /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
+#define TIM_CCMR1_IC1F_0 0x0010U /*!<Bit 0 */
+#define TIM_CCMR1_IC1F_1 0x0020U /*!<Bit 1 */
+#define TIM_CCMR1_IC1F_2 0x0040U /*!<Bit 2 */
+#define TIM_CCMR1_IC1F_3 0x0080U /*!<Bit 3 */
+
+#define TIM_CCMR1_IC2PSC 0x0C00U /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
+#define TIM_CCMR1_IC2PSC_0 0x0400U /*!<Bit 0 */
+#define TIM_CCMR1_IC2PSC_1 0x0800U /*!<Bit 1 */
+
+#define TIM_CCMR1_IC2F 0xF000U /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
+#define TIM_CCMR1_IC2F_0 0x1000U /*!<Bit 0 */
+#define TIM_CCMR1_IC2F_1 0x2000U /*!<Bit 1 */
+#define TIM_CCMR1_IC2F_2 0x4000U /*!<Bit 2 */
+#define TIM_CCMR1_IC2F_3 0x8000U /*!<Bit 3 */
+
+/****************** Bit definition for TIM_CCMR2 register *******************/
+#define TIM_CCMR2_CC3S 0x0003U /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
+#define TIM_CCMR2_CC3S_0 0x0001U /*!<Bit 0 */
+#define TIM_CCMR2_CC3S_1 0x0002U /*!<Bit 1 */
+
+#define TIM_CCMR2_OC3FE 0x0004U /*!<Output Compare 3 Fast enable */
+#define TIM_CCMR2_OC3PE 0x0008U /*!<Output Compare 3 Preload enable */
+
+#define TIM_CCMR2_OC3M 0x0070U /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
+#define TIM_CCMR2_OC3M_0 0x0010U /*!<Bit 0 */
+#define TIM_CCMR2_OC3M_1 0x0020U /*!<Bit 1 */
+#define TIM_CCMR2_OC3M_2 0x0040U /*!<Bit 2 */
+
+#define TIM_CCMR2_OC3CE 0x0080U /*!<Output Compare 3 Clear Enable */
+
+#define TIM_CCMR2_CC4S 0x0300U /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
+#define TIM_CCMR2_CC4S_0 0x0100U /*!<Bit 0 */
+#define TIM_CCMR2_CC4S_1 0x0200U /*!<Bit 1 */
+
+#define TIM_CCMR2_OC4FE 0x0400U /*!<Output Compare 4 Fast enable */
+#define TIM_CCMR2_OC4PE 0x0800U /*!<Output Compare 4 Preload enable */
+
+#define TIM_CCMR2_OC4M 0x7000U /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
+#define TIM_CCMR2_OC4M_0 0x1000U /*!<Bit 0 */
+#define TIM_CCMR2_OC4M_1 0x2000U /*!<Bit 1 */
+#define TIM_CCMR2_OC4M_2 0x4000U /*!<Bit 2 */
+
+#define TIM_CCMR2_OC4CE 0x8000U /*!<Output Compare 4 Clear Enable */
+
+/*----------------------------------------------------------------------------*/
+
+#define TIM_CCMR2_IC3PSC 0x000CU /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
+#define TIM_CCMR2_IC3PSC_0 0x0004U /*!<Bit 0 */
+#define TIM_CCMR2_IC3PSC_1 0x0008U /*!<Bit 1 */
+
+#define TIM_CCMR2_IC3F 0x00F0U /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
+#define TIM_CCMR2_IC3F_0 0x0010U /*!<Bit 0 */
+#define TIM_CCMR2_IC3F_1 0x0020U /*!<Bit 1 */
+#define TIM_CCMR2_IC3F_2 0x0040U /*!<Bit 2 */
+#define TIM_CCMR2_IC3F_3 0x0080U /*!<Bit 3 */
+
+#define TIM_CCMR2_IC4PSC 0x0C00U /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
+#define TIM_CCMR2_IC4PSC_0 0x0400U /*!<Bit 0 */
+#define TIM_CCMR2_IC4PSC_1 0x0800U /*!<Bit 1 */
+
+#define TIM_CCMR2_IC4F 0xF000U /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
+#define TIM_CCMR2_IC4F_0 0x1000U /*!<Bit 0 */
+#define TIM_CCMR2_IC4F_1 0x2000U /*!<Bit 1 */
+#define TIM_CCMR2_IC4F_2 0x4000U /*!<Bit 2 */
+#define TIM_CCMR2_IC4F_3 0x8000U /*!<Bit 3 */
+
+/******************* Bit definition for TIM_CCER register *******************/
+#define TIM_CCER_CC1E 0x0001U /*!<Capture/Compare 1 output enable */
+#define TIM_CCER_CC1P 0x0002U /*!<Capture/Compare 1 output Polarity */
+#define TIM_CCER_CC1NE 0x0004U /*!<Capture/Compare 1 Complementary output enable */
+#define TIM_CCER_CC1NP 0x0008U /*!<Capture/Compare 1 Complementary output Polarity */
+#define TIM_CCER_CC2E 0x0010U /*!<Capture/Compare 2 output enable */
+#define TIM_CCER_CC2P 0x0020U /*!<Capture/Compare 2 output Polarity */
+#define TIM_CCER_CC2NE 0x0040U /*!<Capture/Compare 2 Complementary output enable */
+#define TIM_CCER_CC2NP 0x0080U /*!<Capture/Compare 2 Complementary output Polarity */
+#define TIM_CCER_CC3E 0x0100U /*!<Capture/Compare 3 output enable */
+#define TIM_CCER_CC3P 0x0200U /*!<Capture/Compare 3 output Polarity */
+#define TIM_CCER_CC3NE 0x0400U /*!<Capture/Compare 3 Complementary output enable */
+#define TIM_CCER_CC3NP 0x0800U /*!<Capture/Compare 3 Complementary output Polarity */
+#define TIM_CCER_CC4E 0x1000U /*!<Capture/Compare 4 output enable */
+#define TIM_CCER_CC4P 0x2000U /*!<Capture/Compare 4 output Polarity */
+#define TIM_CCER_CC4NP 0x8000U /*!<Capture/Compare 4 Complementary output Polarity */
+
+/******************* Bit definition for TIM_CNT register ********************/
+#define TIM_CNT_CNT 0xFFFFU /*!<Counter Value */
+
+/******************* Bit definition for TIM_PSC register ********************/
+#define TIM_PSC_PSC 0xFFFFU /*!<Prescaler Value */
+
+/******************* Bit definition for TIM_ARR register ********************/
+#define TIM_ARR_ARR 0xFFFFU /*!<actual auto-reload Value */
+
+/******************* Bit definition for TIM_RCR register ********************/
+#define TIM_RCR_REP 0xFFU /*!<Repetition Counter Value */
+
+/******************* Bit definition for TIM_CCR1 register *******************/
+#define TIM_CCR1_CCR1 0xFFFFU /*!<Capture/Compare 1 Value */
+
+/******************* Bit definition for TIM_CCR2 register *******************/
+#define TIM_CCR2_CCR2 0xFFFFU /*!<Capture/Compare 2 Value */
+
+/******************* Bit definition for TIM_CCR3 register *******************/
+#define TIM_CCR3_CCR3 0xFFFFU /*!<Capture/Compare 3 Value */
+
+/******************* Bit definition for TIM_CCR4 register *******************/
+#define TIM_CCR4_CCR4 0xFFFFU /*!<Capture/Compare 4 Value */
+
+/******************* Bit definition for TIM_BDTR register *******************/
+#define TIM_BDTR_DTG 0x00FFU /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
+#define TIM_BDTR_DTG_0 0x0001U /*!<Bit 0 */
+#define TIM_BDTR_DTG_1 0x0002U /*!<Bit 1 */
+#define TIM_BDTR_DTG_2 0x0004U /*!<Bit 2 */
+#define TIM_BDTR_DTG_3 0x0008U /*!<Bit 3 */
+#define TIM_BDTR_DTG_4 0x0010U /*!<Bit 4 */
+#define TIM_BDTR_DTG_5 0x0020U /*!<Bit 5 */
+#define TIM_BDTR_DTG_6 0x0040U /*!<Bit 6 */
+#define TIM_BDTR_DTG_7 0x0080U /*!<Bit 7 */
+
+#define TIM_BDTR_LOCK 0x0300U /*!<LOCK[1:0] bits (Lock Configuration) */
+#define TIM_BDTR_LOCK_0 0x0100U /*!<Bit 0 */
+#define TIM_BDTR_LOCK_1 0x0200U /*!<Bit 1 */
+
+#define TIM_BDTR_OSSI 0x0400U /*!<Off-State Selection for Idle mode */
+#define TIM_BDTR_OSSR 0x0800U /*!<Off-State Selection for Run mode */
+#define TIM_BDTR_BKE 0x1000U /*!<Break enable */
+#define TIM_BDTR_BKP 0x2000U /*!<Break Polarity */
+#define TIM_BDTR_AOE 0x4000U /*!<Automatic Output enable */
+#define TIM_BDTR_MOE 0x8000U /*!<Main Output enable */
+
+/******************* Bit definition for TIM_DCR register ********************/
+#define TIM_DCR_DBA 0x001FU /*!<DBA[4:0] bits (DMA Base Address) */
+#define TIM_DCR_DBA_0 0x0001U /*!<Bit 0 */
+#define TIM_DCR_DBA_1 0x0002U /*!<Bit 1 */
+#define TIM_DCR_DBA_2 0x0004U /*!<Bit 2 */
+#define TIM_DCR_DBA_3 0x0008U /*!<Bit 3 */
+#define TIM_DCR_DBA_4 0x0010U /*!<Bit 4 */
+
+#define TIM_DCR_DBL 0x1F00U /*!<DBL[4:0] bits (DMA Burst Length) */
+#define TIM_DCR_DBL_0 0x0100U /*!<Bit 0 */
+#define TIM_DCR_DBL_1 0x0200U /*!<Bit 1 */
+#define TIM_DCR_DBL_2 0x0400U /*!<Bit 2 */
+#define TIM_DCR_DBL_3 0x0800U /*!<Bit 3 */
+#define TIM_DCR_DBL_4 0x1000U /*!<Bit 4 */
+
+/******************* Bit definition for TIM_DMAR register *******************/
+#define TIM_DMAR_DMAB 0xFFFFU /*!<DMA register for burst accesses */
+
+/******************* Bit definition for TIM_OR register *********************/
+#define TIM_OR_TI4_RMP 0x00C0U /*!<TI4_RMP[1:0] bits (TIM5 Input 4 remap) */
+#define TIM_OR_TI4_RMP_0 0x0040U /*!<Bit 0 */
+#define TIM_OR_TI4_RMP_1 0x0080U /*!<Bit 1 */
+
+/******************************************************************************/
+/* */
+/* Low Power Timer (LPTIM) */
+/* */
+/******************************************************************************/
+/****************** Bit definition for LPTIM_ISR register *******************/
+#define LPTIM_ISR_CMPM 0x00000001U /*!< Compare match */
+#define LPTIM_ISR_ARRM 0x00000002U /*!< Autoreload match */
+#define LPTIM_ISR_EXTTRIG 0x00000004U /*!< External trigger edge event */
+#define LPTIM_ISR_CMPOK 0x00000008U /*!< Compare register update OK */
+#define LPTIM_ISR_ARROK 0x00000010U /*!< Autoreload register update OK */
+#define LPTIM_ISR_UP 0x00000020U /*!< Counter direction change down to up */
+#define LPTIM_ISR_DOWN 0x00000040U /*!< Counter direction change up to down */
+
+/****************** Bit definition for LPTIM_ICR register *******************/
+#define LPTIM_ICR_CMPMCF 0x00000001U /*!< Compare match Clear Flag */
+#define LPTIM_ICR_ARRMCF 0x00000002U /*!< Autoreload match Clear Flag */
+#define LPTIM_ICR_EXTTRIGCF 0x00000004U /*!< External trigger edge event Clear Flag */
+#define LPTIM_ICR_CMPOKCF 0x00000008U /*!< Compare register update OK Clear Flag */
+#define LPTIM_ICR_ARROKCF 0x00000010U /*!< Autoreload register update OK Clear Flag */
+#define LPTIM_ICR_UPCF 0x00000020U /*!< Counter direction change down to up Clear Flag */
+#define LPTIM_ICR_DOWNCF 0x00000040U /*!< Counter direction change up to down Clear Flag */
+
+/****************** Bit definition for LPTIM_IER register ********************/
+#define LPTIM_IER_CMPMIE 0x00000001U /*!< Compare match Interrupt Enable */
+#define LPTIM_IER_ARRMIE 0x00000002U /*!< Autoreload match Interrupt Enable */
+#define LPTIM_IER_EXTTRIGIE 0x00000004U /*!< External trigger edge event Interrupt Enable */
+#define LPTIM_IER_CMPOKIE 0x00000008U /*!< Compare register update OK Interrupt Enable */
+#define LPTIM_IER_ARROKIE 0x00000010U /*!< Autoreload register update OK Interrupt Enable */
+#define LPTIM_IER_UPIE 0x00000020U /*!< Counter direction change down to up Interrupt Enable */
+#define LPTIM_IER_DOWNIE 0x00000040U /*!< Counter direction change up to down Interrupt Enable */
+
+/****************** Bit definition for LPTIM_CFGR register *******************/
+#define LPTIM_CFGR_CKSEL 0x00000001U /*!< Clock selector */
+
+#define LPTIM_CFGR_CKPOL 0x00000006U /*!< CKPOL[1:0] bits (Clock polarity) */
+#define LPTIM_CFGR_CKPOL_0 0x00000002U /*!< Bit 0 */
+#define LPTIM_CFGR_CKPOL_1 0x00000004U /*!< Bit 1 */
+
+#define LPTIM_CFGR_CKFLT 0x00000018U /*!< CKFLT[1:0] bits (Configurable digital filter for external clock) */
+#define LPTIM_CFGR_CKFLT_0 0x00000008U /*!< Bit 0 */
+#define LPTIM_CFGR_CKFLT_1 0x00000010U /*!< Bit 1 */
+
+#define LPTIM_CFGR_TRGFLT 0x000000C0U /*!< TRGFLT[1:0] bits (Configurable digital filter for trigger) */
+#define LPTIM_CFGR_TRGFLT_0 0x00000040U /*!< Bit 0 */
+#define LPTIM_CFGR_TRGFLT_1 0x00000080U /*!< Bit 1 */
+
+#define LPTIM_CFGR_PRESC 0x00000E00U /*!< PRESC[2:0] bits (Clock prescaler) */
+#define LPTIM_CFGR_PRESC_0 0x00000200U /*!< Bit 0 */
+#define LPTIM_CFGR_PRESC_1 0x00000400U /*!< Bit 1 */
+#define LPTIM_CFGR_PRESC_2 0x00000800U /*!< Bit 2 */
+
+#define LPTIM_CFGR_TRIGSEL 0x0000E000U /*!< TRIGSEL[2:0]] bits (Trigger selector) */
+#define LPTIM_CFGR_TRIGSEL_0 0x00002000U /*!< Bit 0 */
+#define LPTIM_CFGR_TRIGSEL_1 0x00004000U /*!< Bit 1 */
+#define LPTIM_CFGR_TRIGSEL_2 0x00008000U /*!< Bit 2 */
+
+#define LPTIM_CFGR_TRIGEN 0x00060000U /*!< TRIGEN[1:0] bits (Trigger enable and polarity) */
+#define LPTIM_CFGR_TRIGEN_0 0x00020000U /*!< Bit 0 */
+#define LPTIM_CFGR_TRIGEN_1 0x00040000U /*!< Bit 1 */
+
+#define LPTIM_CFGR_TIMOUT 0x00080000U /*!< Timout enable */
+#define LPTIM_CFGR_WAVE 0x00100000U /*!< Waveform shape */
+#define LPTIM_CFGR_WAVPOL 0x00200000U /*!< Waveform shape polarity */
+#define LPTIM_CFGR_PRELOAD 0x00400000U /*!< Reg update mode */
+#define LPTIM_CFGR_COUNTMODE 0x00800000U /*!< Counter mode enable */
+#define LPTIM_CFGR_ENC 0x01000000U /*!< Encoder mode enable */
+
+/****************** Bit definition for LPTIM_CR register ********************/
+#define LPTIM_CR_ENABLE 0x00000001U /*!< LPTIMer enable */
+#define LPTIM_CR_SNGSTRT 0x00000002U /*!< Timer start in single mode */
+#define LPTIM_CR_CNTSTRT 0x00000004U /*!< Timer start in continuous mode */
+
+/****************** Bit definition for LPTIM_CMP register *******************/
+#define LPTIM_CMP_CMP 0x0000FFFFU /*!< Compare register */
+
+/****************** Bit definition for LPTIM_ARR register *******************/
+#define LPTIM_ARR_ARR 0x0000FFFFU /*!< Auto reload register */
+
+/****************** Bit definition for LPTIM_CNT register *******************/
+#define LPTIM_CNT_CNT 0x0000FFFFU /*!< Counter register */
+
+/****************** Bit definition for LPTIM_OR register *******************/
+#define LPTIM_OR_OR 0x00000003U /*!< LPTIMER[1:0] bits (Remap selection) */
+#define LPTIM_OR_OR_0 0x00000001U /*!< Bit 0 */
+#define LPTIM_OR_OR_1 0x00000002U /*!< Bit 1 */
+
+/******************************************************************************/
+/* */
+/* Universal Synchronous Asynchronous Receiver Transmitter */
+/* */
+/******************************************************************************/
+/******************* Bit definition for USART_SR register *******************/
+#define USART_SR_PE 0x0001U /*!<Parity Error */
+#define USART_SR_FE 0x0002U /*!<Framing Error */
+#define USART_SR_NE 0x0004U /*!<Noise Error Flag */
+#define USART_SR_ORE 0x0008U /*!<OverRun Error */
+#define USART_SR_IDLE 0x0010U /*!<IDLE line detected */
+#define USART_SR_RXNE 0x0020U /*!<Read Data Register Not Empty */
+#define USART_SR_TC 0x0040U /*!<Transmission Complete */
+#define USART_SR_TXE 0x0080U /*!<Transmit Data Register Empty */
+#define USART_SR_LBD 0x0100U /*!<LIN Break Detection Flag */
+#define USART_SR_CTS 0x0200U /*!<CTS Flag */
+
+/******************* Bit definition for USART_DR register *******************/
+#define USART_DR_DR 0x01FFU /*!<Data value */
+
+/****************** Bit definition for USART_BRR register *******************/
+#define USART_BRR_DIV_Fraction 0x000FU /*!<Fraction of USARTDIV */
+#define USART_BRR_DIV_Mantissa 0xFFF0U /*!<Mantissa of USARTDIV */
+
+/****************** Bit definition for USART_CR1 register *******************/
+#define USART_CR1_SBK 0x0001U /*!<Send Break */
+#define USART_CR1_RWU 0x0002U /*!<Receiver wakeup */
+#define USART_CR1_RE 0x0004U /*!<Receiver Enable */
+#define USART_CR1_TE 0x0008U /*!<Transmitter Enable */
+#define USART_CR1_IDLEIE 0x0010U /*!<IDLE Interrupt Enable */
+#define USART_CR1_RXNEIE 0x0020U /*!<RXNE Interrupt Enable */
+#define USART_CR1_TCIE 0x0040U /*!<Transmission Complete Interrupt Enable */
+#define USART_CR1_TXEIE 0x0080U /*!<PE Interrupt Enable */
+#define USART_CR1_PEIE 0x0100U /*!<PE Interrupt Enable */
+#define USART_CR1_PS 0x0200U /*!<Parity Selection */
+#define USART_CR1_PCE 0x0400U /*!<Parity Control Enable */
+#define USART_CR1_WAKE 0x0800U /*!<Wakeup method */
+#define USART_CR1_M 0x1000U /*!<Word length */
+#define USART_CR1_UE 0x2000U /*!<USART Enable */
+#define USART_CR1_OVER8 0x8000U /*!<USART Oversampling by 8 enable */
+
+/****************** Bit definition for USART_CR2 register *******************/
+#define USART_CR2_ADD 0x000FU /*!<Address of the USART node */
+#define USART_CR2_LBDL 0x0020U /*!<LIN Break Detection Length */
+#define USART_CR2_LBDIE 0x0040U /*!<LIN Break Detection Interrupt Enable */
+#define USART_CR2_LBCL 0x0100U /*!<Last Bit Clock pulse */
+#define USART_CR2_CPHA 0x0200U /*!<Clock Phase */
+#define USART_CR2_CPOL 0x0400U /*!<Clock Polarity */
+#define USART_CR2_CLKEN 0x0800U /*!<Clock Enable */
+
+#define USART_CR2_STOP 0x3000U /*!<STOP[1:0] bits (STOP bits) */
+#define USART_CR2_STOP_0 0x1000U /*!<Bit 0 */
+#define USART_CR2_STOP_1 0x2000U /*!<Bit 1 */
+
+#define USART_CR2_LINEN 0x4000U /*!<LIN mode enable */
+
+/****************** Bit definition for USART_CR3 register *******************/
+#define USART_CR3_EIE 0x0001U /*!<Error Interrupt Enable */
+#define USART_CR3_IREN 0x0002U /*!<IrDA mode Enable */
+#define USART_CR3_IRLP 0x0004U /*!<IrDA Low-Power */
+#define USART_CR3_HDSEL 0x0008U /*!<Half-Duplex Selection */
+#define USART_CR3_NACK 0x0010U /*!<Smartcard NACK enable */
+#define USART_CR3_SCEN 0x0020U /*!<Smartcard mode enable */
+#define USART_CR3_DMAR 0x0040U /*!<DMA Enable Receiver */
+#define USART_CR3_DMAT 0x0080U /*!<DMA Enable Transmitter */
+#define USART_CR3_RTSE 0x0100U /*!<RTS Enable */
+#define USART_CR3_CTSE 0x0200U /*!<CTS Enable */
+#define USART_CR3_CTSIE 0x0400U /*!<CTS Interrupt Enable */
+#define USART_CR3_ONEBIT 0x0800U /*!<USART One bit method enable */
+
+/****************** Bit definition for USART_GTPR register ******************/
+#define USART_GTPR_PSC 0x00FFU /*!<PSC[7:0] bits (Prescaler value) */
+#define USART_GTPR_PSC_0 0x0001U /*!<Bit 0 */
+#define USART_GTPR_PSC_1 0x0002U /*!<Bit 1 */
+#define USART_GTPR_PSC_2 0x0004U /*!<Bit 2 */
+#define USART_GTPR_PSC_3 0x0008U /*!<Bit 3 */
+#define USART_GTPR_PSC_4 0x0010U /*!<Bit 4 */
+#define USART_GTPR_PSC_5 0x0020U /*!<Bit 5 */
+#define USART_GTPR_PSC_6 0x0040U /*!<Bit 6 */
+#define USART_GTPR_PSC_7 0x0080U /*!<Bit 7 */
+
+#define USART_GTPR_GT 0xFF00U /*!<Guard time value */
+
+/******************************************************************************/
+/* */
+/* Window WATCHDOG */
+/* */
+/******************************************************************************/
+/******************* Bit definition for WWDG_CR register ********************/
+#define WWDG_CR_T 0x7FU /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
+#define WWDG_CR_T_0 0x01U /*!<Bit 0 */
+#define WWDG_CR_T_1 0x02U /*!<Bit 1 */
+#define WWDG_CR_T_2 0x04U /*!<Bit 2 */
+#define WWDG_CR_T_3 0x08U /*!<Bit 3 */
+#define WWDG_CR_T_4 0x10U /*!<Bit 4 */
+#define WWDG_CR_T_5 0x20U /*!<Bit 5 */
+#define WWDG_CR_T_6 0x40U /*!<Bit 6 */
+/* Legacy defines */
+#define WWDG_CR_T0 WWDG_CR_T_0
+#define WWDG_CR_T1 WWDG_CR_T_1
+#define WWDG_CR_T2 WWDG_CR_T_2
+#define WWDG_CR_T3 WWDG_CR_T_3
+#define WWDG_CR_T4 WWDG_CR_T_4
+#define WWDG_CR_T5 WWDG_CR_T_5
+#define WWDG_CR_T6 WWDG_CR_T_6
+
+#define WWDG_CR_WDGA 0x80U /*!<Activation bit */
+
+/******************* Bit definition for WWDG_CFR register *******************/
+#define WWDG_CFR_W 0x007FU /*!<W[6:0] bits (7-bit window value) */
+#define WWDG_CFR_W_0 0x0001U /*!<Bit 0 */
+#define WWDG_CFR_W_1 0x0002U /*!<Bit 1 */
+#define WWDG_CFR_W_2 0x0004U /*!<Bit 2 */
+#define WWDG_CFR_W_3 0x0008U /*!<Bit 3 */
+#define WWDG_CFR_W_4 0x0010U /*!<Bit 4 */
+#define WWDG_CFR_W_5 0x0020U /*!<Bit 5 */
+#define WWDG_CFR_W_6 0x0040U /*!<Bit 6 */
+/* Legacy defines */
+#define WWDG_CFR_W0 WWDG_CFR_W_0
+#define WWDG_CFR_W1 WWDG_CFR_W_1
+#define WWDG_CFR_W2 WWDG_CFR_W_2
+#define WWDG_CFR_W3 WWDG_CFR_W_3
+#define WWDG_CFR_W4 WWDG_CFR_W_4
+#define WWDG_CFR_W5 WWDG_CFR_W_5
+#define WWDG_CFR_W6 WWDG_CFR_W_6
+
+#define WWDG_CFR_WDGTB 0x0180U /*!<WDGTB[1:0] bits (Timer Base) */
+#define WWDG_CFR_WDGTB_0 0x0080U /*!<Bit 0 */
+#define WWDG_CFR_WDGTB_1 0x0100U /*!<Bit 1 */
+/* Legacy defines */
+#define WWDG_CFR_WDGTB0 WWDG_CFR_WDGTB_0
+#define WWDG_CFR_WDGTB1 WWDG_CFR_WDGTB_1
+
+#define WWDG_CFR_EWI 0x0200U /*!<Early Wakeup Interrupt */
+
+/******************* Bit definition for WWDG_SR register ********************/
+#define WWDG_SR_EWIF 0x01U /*!<Early Wakeup Interrupt Flag */
+
+/******************************************************************************/
+/* */
+/* Digital to Analog Converter */
+/* */
+/******************************************************************************/
+/******************** Bit definition for DAC_CR register ********************/
+#define DAC_CR_EN1 0x00000001U /*!<DAC channel1 enable */
+#define DAC_CR_BOFF1 0x00000002U /*!<DAC channel1 output buffer disable */
+#define DAC_CR_TEN1 0x00000004U /*!<DAC channel1 Trigger enable */
+
+#define DAC_CR_TSEL1 0x00000038U /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */
+#define DAC_CR_TSEL1_0 0x00000008U /*!<Bit 0 */
+#define DAC_CR_TSEL1_1 0x00000010U /*!<Bit 1 */
+#define DAC_CR_TSEL1_2 0x00000020U /*!<Bit 2 */
+
+#define DAC_CR_WAVE1 0x000000C0U /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
+#define DAC_CR_WAVE1_0 0x00000040U /*!<Bit 0 */
+#define DAC_CR_WAVE1_1 0x00000080U /*!<Bit 1 */
+
+#define DAC_CR_MAMP1 0x00000F00U /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
+#define DAC_CR_MAMP1_0 0x00000100U /*!<Bit 0 */
+#define DAC_CR_MAMP1_1 0x00000200U /*!<Bit 1 */
+#define DAC_CR_MAMP1_2 0x00000400U /*!<Bit 2 */
+#define DAC_CR_MAMP1_3 0x00000800U /*!<Bit 3 */
+
+#define DAC_CR_DMAEN1 0x00001000U /*!<DAC channel1 DMA enable */
+#define DAC_CR_DMAUDRIE1 0x00002000U /*!<DAC channel1 DMA underrun interrupt enable*/
+#define DAC_CR_EN2 0x00010000U /*!<DAC channel2 enable */
+#define DAC_CR_BOFF2 0x00020000U /*!<DAC channel2 output buffer disable */
+#define DAC_CR_TEN2 0x00040000U /*!<DAC channel2 Trigger enable */
+
+#define DAC_CR_TSEL2 0x00380000U /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */
+#define DAC_CR_TSEL2_0 0x00080000U /*!<Bit 0 */
+#define DAC_CR_TSEL2_1 0x00100000U /*!<Bit 1 */
+#define DAC_CR_TSEL2_2 0x00200000U /*!<Bit 2 */
+
+#define DAC_CR_WAVE2 0x00C00000U /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
+#define DAC_CR_WAVE2_0 0x00400000U /*!<Bit 0 */
+#define DAC_CR_WAVE2_1 0x00800000U /*!<Bit 1 */
+
+#define DAC_CR_MAMP2 0x0F000000U /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
+#define DAC_CR_MAMP2_0 0x01000000U /*!<Bit 0 */
+#define DAC_CR_MAMP2_1 0x02000000U /*!<Bit 1 */
+#define DAC_CR_MAMP2_2 0x04000000U /*!<Bit 2 */
+#define DAC_CR_MAMP2_3 0x08000000U /*!<Bit 3 */
+
+#define DAC_CR_DMAEN2 0x10000000U /*!<DAC channel2 DMA enabled */
+#define DAC_CR_DMAUDRIE2 0x20000000U /*!<DAC channel2 DMA underrun interrupt enable*/
+
+/***************** Bit definition for DAC_SWTRIGR register ******************/
+#define DAC_SWTRIGR_SWTRIG1 0x01U /*!<DAC channel1 software trigger */
+#define DAC_SWTRIGR_SWTRIG2 0x02U /*!<DAC channel2 software trigger */
+
+/***************** Bit definition for DAC_DHR12R1 register ******************/
+#define DAC_DHR12R1_DACC1DHR 0x0FFFU /*!<DAC channel1 12-bit Right aligned data */
+
+/***************** Bit definition for DAC_DHR12L1 register ******************/
+#define DAC_DHR12L1_DACC1DHR 0xFFF0U /*!<DAC channel1 12-bit Left aligned data */
+
+/****************** Bit definition for DAC_DHR8R1 register ******************/
+#define DAC_DHR8R1_DACC1DHR 0xFFU /*!<DAC channel1 8-bit Right aligned data */
+
+/***************** Bit definition for DAC_DHR12R2 register ******************/
+#define DAC_DHR12R2_DACC2DHR 0x0FFFU /*!<DAC channel2 12-bit Right aligned data */
+
+/***************** Bit definition for DAC_DHR12L2 register ******************/
+#define DAC_DHR12L2_DACC2DHR 0xFFF0U /*!<DAC channel2 12-bit Left aligned data */
+
+/****************** Bit definition for DAC_DHR8R2 register ******************/
+#define DAC_DHR8R2_DACC2DHR 0xFFU /*!<DAC channel2 8-bit Right aligned data */
+
+/***************** Bit definition for DAC_DHR12RD register ******************/
+#define DAC_DHR12RD_DACC1DHR 0x00000FFFU /*!<DAC channel1 12-bit Right aligned data */
+#define DAC_DHR12RD_DACC2DHR 0x0FFF0000U /*!<DAC channel2 12-bit Right aligned data */
+
+/***************** Bit definition for DAC_DHR12LD register ******************/
+#define DAC_DHR12LD_DACC1DHR 0x0000FFF0U /*!<DAC channel1 12-bit Left aligned data */
+#define DAC_DHR12LD_DACC2DHR 0xFFF00000U /*!<DAC channel2 12-bit Left aligned data */
+
+/****************** Bit definition for DAC_DHR8RD register ******************/
+#define DAC_DHR8RD_DACC1DHR 0x00FFU /*!<DAC channel1 8-bit Right aligned data */
+#define DAC_DHR8RD_DACC2DHR 0xFF00U /*!<DAC channel2 8-bit Right aligned data */
+
+/******************* Bit definition for DAC_DOR1 register *******************/
+#define DAC_DOR1_DACC1DOR 0x0FFFU /*!<DAC channel1 data output */
+
+/******************* Bit definition for DAC_DOR2 register *******************/
+#define DAC_DOR2_DACC2DOR 0x0FFFU /*!<DAC channel2 data output */
+
+/******************** Bit definition for DAC_SR register ********************/
+#define DAC_SR_DMAUDR1 0x00002000U /*!<DAC channel1 DMA underrun flag */
+#define DAC_SR_DMAUDR2 0x20000000U /*!<DAC channel2 DMA underrun flag */
+/******************************************************************************/
+/* */
+/* DBG */
+/* */
+/******************************************************************************/
+/******************** Bit definition for DBGMCU_IDCODE register *************/
+#define DBGMCU_IDCODE_DEV_ID 0x00000FFFU
+#define DBGMCU_IDCODE_REV_ID 0xFFFF0000U
+
+/******************** Bit definition for DBGMCU_CR register *****************/
+#define DBGMCU_CR_DBG_SLEEP 0x00000001U
+#define DBGMCU_CR_DBG_STOP 0x00000002U
+#define DBGMCU_CR_DBG_STANDBY 0x00000004U
+#define DBGMCU_CR_TRACE_IOEN 0x00000020U
+
+#define DBGMCU_CR_TRACE_MODE 0x000000C0U
+#define DBGMCU_CR_TRACE_MODE_0 0x00000040U/*!<Bit 0 */
+#define DBGMCU_CR_TRACE_MODE_1 0x00000080U/*!<Bit 1 */
+
+/******************** Bit definition for DBGMCU_APB1_FZ register ************/
+#define DBGMCU_APB1_FZ_DBG_TIM5_STOP 0x00000008U
+#define DBGMCU_APB1_FZ_DBG_TIM6_STOP 0x00000010U
+#define DBGMCU_APB1_FZ_DBG_RTC_STOP 0x00000400U
+#define DBGMCU_APB1_FZ_DBG_WWDG_STOP 0x00000800U
+#define DBGMCU_APB1_FZ_DBG_IWDG_STOP 0x00001000U
+#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT 0x00200000U
+#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT 0x00400000U
+#define DBGMCU_APB1_FZ_DBG_CAN1_STOP 0x02000000U
+#define DBGMCU_APB1_FZ_DBG_CAN2_STOP 0x04000000U
+
+/******************** Bit definition for DBGMCU_APB2_FZ register ************/
+#define DBGMCU_APB2_FZ_DBG_TIM1_STOP 0x00000001U
+#define DBGMCU_APB2_FZ_DBG_TIM9_STOP 0x00010000U
+#define DBGMCU_APB2_FZ_DBG_TIM11_STOP 0x00040000U
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup Exported_macros
+ * @{
+ */
+
+/******************************* ADC Instances ********************************/
+#define IS_ADC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
+
+/******************************* CRC Instances ********************************/
+#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
+
+/******************************* DAC Instances ********************************/
+#define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC)
+
+/******************************** DMA Instances *******************************/
+#define IS_DMA_STREAM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0) || \
+ ((INSTANCE) == DMA1_Stream1) || \
+ ((INSTANCE) == DMA1_Stream2) || \
+ ((INSTANCE) == DMA1_Stream3) || \
+ ((INSTANCE) == DMA1_Stream4) || \
+ ((INSTANCE) == DMA1_Stream5) || \
+ ((INSTANCE) == DMA1_Stream6) || \
+ ((INSTANCE) == DMA1_Stream7) || \
+ ((INSTANCE) == DMA2_Stream0) || \
+ ((INSTANCE) == DMA2_Stream1) || \
+ ((INSTANCE) == DMA2_Stream2) || \
+ ((INSTANCE) == DMA2_Stream3) || \
+ ((INSTANCE) == DMA2_Stream4) || \
+ ((INSTANCE) == DMA2_Stream5) || \
+ ((INSTANCE) == DMA2_Stream6) || \
+ ((INSTANCE) == DMA2_Stream7))
+
+/******************************* GPIO Instances *******************************/
+#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
+ ((INSTANCE) == GPIOB) || \
+ ((INSTANCE) == GPIOC) || \
+ ((INSTANCE) == GPIOH))
+
+/******************************** I2C Instances *******************************/
+#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
+ ((INSTANCE) == I2C2))
+/******************************** I2S Instances *******************************/
+#define IS_I2S_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SPI1)
+
+/******************************* LPTIM Instances ******************************/
+#define IS_LPTIM_INSTANCE(__INSTANCE__) ((__INSTANCE__) == LPTIM1)
+
+/******************************* RNG Instances ********************************/
+#define IS_RNG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RNG)
+
+/****************************** RTC Instances *********************************/
+#define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
+
+/******************************** SPI Instances *******************************/
+#define IS_SPI_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SPI1)
+/*************************** SPI Extended Instances ***************************/
+#define IS_SPI_ALL_INSTANCE_EXT(INSTANCE) ((INSTANCE) == SPI1)
+
+/****************** TIM Instances : All supported instances *******************/
+#define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM6) || \
+ ((INSTANCE) == TIM9) || \
+ ((INSTANCE) == TIM11))
+
+/************* TIM Instances : at least 1 capture/compare channel *************/
+#define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM9) || \
+ ((INSTANCE) == TIM11))
+
+/************ TIM Instances : at least 2 capture/compare channels *************/
+#define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM9))
+
+/************ TIM Instances : at least 3 capture/compare channels *************/
+#define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM5))
+
+/************ TIM Instances : at least 4 capture/compare channels *************/
+#define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM5))
+
+/******************** TIM Instances : Advanced-control timers *****************/
+#define IS_TIM_ADVANCED_INSTANCE(INSTANCE) ((INSTANCE) == TIM1)
+
+/******************* TIM Instances : Timer input XOR function *****************/
+#define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM5))
+
+/****************** TIM Instances : DMA requests generation (UDE) *************/
+#define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM6))
+
+/************ TIM Instances : DMA requests generation (CCxDE) *****************/
+#define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM5))
+
+/************ TIM Instances : DMA requests generation (COMDE) *****************/
+#define IS_TIM_CCDMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM5))
+
+/******************** TIM Instances : DMA burst feature ***********************/
+#define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM5))
+
+/****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/
+#define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM6) || \
+ ((INSTANCE) == TIM9))
+
+/*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
+#define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM9))
+
+/********************** TIM Instances : 32 bit Counter ************************/
+#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)(((INSTANCE) == TIM5))
+
+/***************** TIM Instances : external trigger input availabe ************/
+#define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM5))
+
+/****************** TIM Instances : remapping capability **********************/
+#define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM11))
+
+/******************* TIM Instances : output(s) available **********************/
+#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
+ ((((INSTANCE) == TIM1) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM5) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM9) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2))) \
+ || \
+ (((INSTANCE) == TIM11) && \
+ (((CHANNEL) == TIM_CHANNEL_1))))
+
+/************ TIM Instances : complementary output(s) available ***************/
+#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
+ ((((INSTANCE) == TIM1) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3))))
+
+/******************** USART Instances : Synchronous mode **********************/
+#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2))
+
+/******************** UART Instances : Asynchronous mode **********************/
+#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2))
+
+/****************** UART Instances : Hardware Flow control ********************/
+#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (0)
+
+/********************* UART Instances : Smard card mode ***********************/
+#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2))
+
+/*********************** UART Instances : IRDA mode ***************************/
+#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2))
+
+/****************************** IWDG Instances ********************************/
+#define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
+
+/****************************** WWDG Instances ********************************/
+#define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
+
+/***************************** FMPI2C Instances *******************************/
+#define IS_FMPI2C_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == FMPI2C1)
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* __STM32F410Tx_H */
+
+
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Device/ST/STM32F4xx/Include/stm32f411xe.h b/Device/ST/STM32F4xx/Include/stm32f411xe.h
new file mode 100644
index 0000000..ebd088f
--- /dev/null
+++ b/Device/ST/STM32F4xx/Include/stm32f411xe.h
@@ -0,0 +1,4830 @@
+/**
+ ******************************************************************************
+ * @file stm32f411xe.h
+ * @author MCD Application Team
+ * @version V2.5.0
+ * @date 22-April-2016
+ * @brief CMSIS STM32F411xExx Device Peripheral Access Layer Header File.
+ *
+ * This file contains:
+ * - Data structures and the address mapping for all peripherals
+ * - peripherals registers declarations and bits definition
+ * - Macros to access peripheral’s registers hardware
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/** @addtogroup CMSIS
+ * @{
+ */
+
+/** @addtogroup stm32f411xe
+ * @{
+ */
+
+#ifndef __STM32F411xE_H
+#define __STM32F411xE_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif /* __cplusplus */
+
+
+/** @addtogroup Configuration_section_for_CMSIS
+ * @{
+ */
+
+/**
+ * @brief Configuration of the Cortex-M4 Processor and Core Peripherals
+ */
+#define __CM4_REV 0x0001U /*!< Core revision r0p1 */
+#define __MPU_PRESENT 1U /*!< STM32F4XX provides an MPU */
+#define __NVIC_PRIO_BITS 4U /*!< STM32F4XX uses 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */
+#define __FPU_PRESENT 1U /*!< FPU present */
+
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_interrupt_number_definition
+ * @{
+ */
+
+/**
+ * @brief STM32F4XX Interrupt Number Definition, according to the selected device
+ * in @ref Library_configuration_section
+ */
+typedef enum
+{
+/****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/
+ NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
+ MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */
+ BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */
+ UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */
+ SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */
+ DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */
+ PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */
+ SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */
+/****** STM32 specific Interrupt Numbers **********************************************************************/
+ WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
+ PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */
+ TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */
+ RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */
+ FLASH_IRQn = 4, /*!< FLASH global Interrupt */
+ RCC_IRQn = 5, /*!< RCC global Interrupt */
+ EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */
+ EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */
+ EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */
+ EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */
+ EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */
+ DMA1_Stream0_IRQn = 11, /*!< DMA1 Stream 0 global Interrupt */
+ DMA1_Stream1_IRQn = 12, /*!< DMA1 Stream 1 global Interrupt */
+ DMA1_Stream2_IRQn = 13, /*!< DMA1 Stream 2 global Interrupt */
+ DMA1_Stream3_IRQn = 14, /*!< DMA1 Stream 3 global Interrupt */
+ DMA1_Stream4_IRQn = 15, /*!< DMA1 Stream 4 global Interrupt */
+ DMA1_Stream5_IRQn = 16, /*!< DMA1 Stream 5 global Interrupt */
+ DMA1_Stream6_IRQn = 17, /*!< DMA1 Stream 6 global Interrupt */
+ ADC_IRQn = 18, /*!< ADC1, ADC2 and ADC3 global Interrupts */
+ EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
+ TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break interrupt and TIM9 global interrupt */
+ TIM1_UP_TIM10_IRQn = 25, /*!< TIM1 Update Interrupt and TIM10 global interrupt */
+ TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */
+ TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
+ TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
+ TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
+ TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
+ I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
+ I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
+ I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
+ I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
+ SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
+ SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
+ USART1_IRQn = 37, /*!< USART1 global Interrupt */
+ USART2_IRQn = 38, /*!< USART2 global Interrupt */
+ EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
+ RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */
+ OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS Wakeup through EXTI line interrupt */
+ DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */
+ SDIO_IRQn = 49, /*!< SDIO global Interrupt */
+ TIM5_IRQn = 50, /*!< TIM5 global Interrupt */
+ SPI3_IRQn = 51, /*!< SPI3 global Interrupt */
+ DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */
+ DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */
+ DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */
+ DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */
+ DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */
+ OTG_FS_IRQn = 67, /*!< USB OTG FS global Interrupt */
+ DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */
+ DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */
+ DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */
+ USART6_IRQn = 71, /*!< USART6 global interrupt */
+ I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */
+ I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */
+ FPU_IRQn = 81, /*!< FPU global interrupt */
+ SPI4_IRQn = 84, /*!< SPI4 global Interrupt */
+ SPI5_IRQn = 85 /*!< SPI5 global Interrupt */
+} IRQn_Type;
+
+/**
+ * @}
+ */
+
+#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
+#include "system_stm32f4xx.h"
+#include <stdint.h>
+
+/** @addtogroup Peripheral_registers_structures
+ * @{
+ */
+
+/**
+ * @brief Analog to Digital Converter
+ */
+
+typedef struct
+{
+ __IO uint32_t SR; /*!< ADC status register, Address offset: 0x00 */
+ __IO uint32_t CR1; /*!< ADC control register 1, Address offset: 0x04 */
+ __IO uint32_t CR2; /*!< ADC control register 2, Address offset: 0x08 */
+ __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x0C */
+ __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x10 */
+ __IO uint32_t JOFR1; /*!< ADC injected channel data offset register 1, Address offset: 0x14 */
+ __IO uint32_t JOFR2; /*!< ADC injected channel data offset register 2, Address offset: 0x18 */
+ __IO uint32_t JOFR3; /*!< ADC injected channel data offset register 3, Address offset: 0x1C */
+ __IO uint32_t JOFR4; /*!< ADC injected channel data offset register 4, Address offset: 0x20 */
+ __IO uint32_t HTR; /*!< ADC watchdog higher threshold register, Address offset: 0x24 */
+ __IO uint32_t LTR; /*!< ADC watchdog lower threshold register, Address offset: 0x28 */
+ __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x2C */
+ __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x30 */
+ __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x34 */
+ __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x38*/
+ __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x3C */
+ __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x40 */
+ __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x44 */
+ __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x48 */
+ __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x4C */
+} ADC_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1 base address + 0x300 */
+ __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1 base address + 0x304 */
+ __IO uint32_t CDR; /*!< ADC common regular data register for dual
+ AND triple modes, Address offset: ADC1 base address + 0x308 */
+} ADC_Common_TypeDef;
+
+/**
+ * @brief CRC calculation unit
+ */
+
+typedef struct
+{
+ __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
+ __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
+ uint8_t RESERVED0; /*!< Reserved, 0x05 */
+ uint16_t RESERVED1; /*!< Reserved, 0x06 */
+ __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
+} CRC_TypeDef;
+
+/**
+ * @brief Debug MCU
+ */
+
+typedef struct
+{
+ __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
+ __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
+ __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */
+ __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */
+}DBGMCU_TypeDef;
+
+
+/**
+ * @brief DMA Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< DMA stream x configuration register */
+ __IO uint32_t NDTR; /*!< DMA stream x number of data register */
+ __IO uint32_t PAR; /*!< DMA stream x peripheral address register */
+ __IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */
+ __IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */
+ __IO uint32_t FCR; /*!< DMA stream x FIFO control register */
+} DMA_Stream_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t LISR; /*!< DMA low interrupt status register, Address offset: 0x00 */
+ __IO uint32_t HISR; /*!< DMA high interrupt status register, Address offset: 0x04 */
+ __IO uint32_t LIFCR; /*!< DMA low interrupt flag clear register, Address offset: 0x08 */
+ __IO uint32_t HIFCR; /*!< DMA high interrupt flag clear register, Address offset: 0x0C */
+} DMA_TypeDef;
+
+
+/**
+ * @brief External Interrupt/Event Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t IMR; /*!< EXTI Interrupt mask register, Address offset: 0x00 */
+ __IO uint32_t EMR; /*!< EXTI Event mask register, Address offset: 0x04 */
+ __IO uint32_t RTSR; /*!< EXTI Rising trigger selection register, Address offset: 0x08 */
+ __IO uint32_t FTSR; /*!< EXTI Falling trigger selection register, Address offset: 0x0C */
+ __IO uint32_t SWIER; /*!< EXTI Software interrupt event register, Address offset: 0x10 */
+ __IO uint32_t PR; /*!< EXTI Pending register, Address offset: 0x14 */
+} EXTI_TypeDef;
+
+/**
+ * @brief FLASH Registers
+ */
+
+typedef struct
+{
+ __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */
+ __IO uint32_t KEYR; /*!< FLASH key register, Address offset: 0x04 */
+ __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x08 */
+ __IO uint32_t SR; /*!< FLASH status register, Address offset: 0x0C */
+ __IO uint32_t CR; /*!< FLASH control register, Address offset: 0x10 */
+ __IO uint32_t OPTCR; /*!< FLASH option control register , Address offset: 0x14 */
+ __IO uint32_t OPTCR1; /*!< FLASH option control register 1, Address offset: 0x18 */
+} FLASH_TypeDef;
+
+/**
+ * @brief General Purpose I/O
+ */
+
+typedef struct
+{
+ __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
+ __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */
+ __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */
+ __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
+ __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
+ __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
+ __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */
+ __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
+ __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */
+} GPIO_TypeDef;
+
+/**
+ * @brief System configuration controller
+ */
+
+typedef struct
+{
+ __IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */
+ __IO uint32_t PMC; /*!< SYSCFG peripheral mode configuration register, Address offset: 0x04 */
+ __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
+ uint32_t RESERVED[2]; /*!< Reserved, 0x18-0x1C */
+ __IO uint32_t CMPCR; /*!< SYSCFG Compensation cell control register, Address offset: 0x20 */
+} SYSCFG_TypeDef;
+
+/**
+ * @brief Inter-integrated Circuit Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */
+ __IO uint32_t OAR1; /*!< I2C Own address register 1, Address offset: 0x08 */
+ __IO uint32_t OAR2; /*!< I2C Own address register 2, Address offset: 0x0C */
+ __IO uint32_t DR; /*!< I2C Data register, Address offset: 0x10 */
+ __IO uint32_t SR1; /*!< I2C Status register 1, Address offset: 0x14 */
+ __IO uint32_t SR2; /*!< I2C Status register 2, Address offset: 0x18 */
+ __IO uint32_t CCR; /*!< I2C Clock control register, Address offset: 0x1C */
+ __IO uint32_t TRISE; /*!< I2C TRISE register, Address offset: 0x20 */
+ __IO uint32_t FLTR; /*!< I2C FLTR register, Address offset: 0x24 */
+} I2C_TypeDef;
+
+/**
+ * @brief Independent WATCHDOG
+ */
+
+typedef struct
+{
+ __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */
+ __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */
+ __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */
+ __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */
+} IWDG_TypeDef;
+
+/**
+ * @brief Power Control
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */
+ __IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */
+} PWR_TypeDef;
+
+/**
+ * @brief Reset and Clock Control
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */
+ __IO uint32_t PLLCFGR; /*!< RCC PLL configuration register, Address offset: 0x04 */
+ __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x08 */
+ __IO uint32_t CIR; /*!< RCC clock interrupt register, Address offset: 0x0C */
+ __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x10 */
+ __IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x14 */
+ __IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0x18 */
+ uint32_t RESERVED0; /*!< Reserved, 0x1C */
+ __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x20 */
+ __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x24 */
+ uint32_t RESERVED1[2]; /*!< Reserved, 0x28-0x2C */
+ __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clock register, Address offset: 0x30 */
+ __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clock register, Address offset: 0x34 */
+ __IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clock register, Address offset: 0x38 */
+ uint32_t RESERVED2; /*!< Reserved, 0x3C */
+ __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x40 */
+ __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x44 */
+ uint32_t RESERVED3[2]; /*!< Reserved, 0x48-0x4C */
+ __IO uint32_t AHB1LPENR; /*!< RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 */
+ __IO uint32_t AHB2LPENR; /*!< RCC AHB2 peripheral clock enable in low power mode register, Address offset: 0x54 */
+ __IO uint32_t AHB3LPENR; /*!< RCC AHB3 peripheral clock enable in low power mode register, Address offset: 0x58 */
+ uint32_t RESERVED4; /*!< Reserved, 0x5C */
+ __IO uint32_t APB1LPENR; /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 */
+ __IO uint32_t APB2LPENR; /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 */
+ uint32_t RESERVED5[2]; /*!< Reserved, 0x68-0x6C */
+ __IO uint32_t BDCR; /*!< RCC Backup domain control register, Address offset: 0x70 */
+ __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x74 */
+ uint32_t RESERVED6[2]; /*!< Reserved, 0x78-0x7C */
+ __IO uint32_t SSCGR; /*!< RCC spread spectrum clock generation register, Address offset: 0x80 */
+ __IO uint32_t PLLI2SCFGR; /*!< RCC PLLI2S configuration register, Address offset: 0x84 */
+ uint32_t RESERVED7[1]; /*!< Reserved, 0x88 */
+ __IO uint32_t DCKCFGR; /*!< RCC DCKCFGR configuration register, Address offset: 0x8C */
+} RCC_TypeDef;
+
+/**
+ * @brief Real-Time Clock
+ */
+
+typedef struct
+{
+ __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
+ __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */
+ __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */
+ __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */
+ __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */
+ __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */
+ __IO uint32_t CALIBR; /*!< RTC calibration register, Address offset: 0x18 */
+ __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */
+ __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */
+ __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */
+ __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */
+ __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */
+ __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */
+ __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */
+ __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */
+ __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */
+ __IO uint32_t TAFCR; /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */
+ __IO uint32_t ALRMASSR;/*!< RTC alarm A sub second register, Address offset: 0x44 */
+ __IO uint32_t ALRMBSSR;/*!< RTC alarm B sub second register, Address offset: 0x48 */
+ uint32_t RESERVED7; /*!< Reserved, 0x4C */
+ __IO uint32_t BKP0R; /*!< RTC backup register 1, Address offset: 0x50 */
+ __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */
+ __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */
+ __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */
+ __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */
+ __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */
+ __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */
+ __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */
+ __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */
+ __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */
+ __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */
+ __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */
+ __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */
+ __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */
+ __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */
+ __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */
+ __IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */
+ __IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */
+ __IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */
+ __IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */
+} RTC_TypeDef;
+
+
+/**
+ * @brief SD host Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t POWER; /*!< SDIO power control register, Address offset: 0x00 */
+ __IO uint32_t CLKCR; /*!< SDI clock control register, Address offset: 0x04 */
+ __IO uint32_t ARG; /*!< SDIO argument register, Address offset: 0x08 */
+ __IO uint32_t CMD; /*!< SDIO command register, Address offset: 0x0C */
+ __I uint32_t RESPCMD; /*!< SDIO command response register, Address offset: 0x10 */
+ __I uint32_t RESP1; /*!< SDIO response 1 register, Address offset: 0x14 */
+ __I uint32_t RESP2; /*!< SDIO response 2 register, Address offset: 0x18 */
+ __I uint32_t RESP3; /*!< SDIO response 3 register, Address offset: 0x1C */
+ __I uint32_t RESP4; /*!< SDIO response 4 register, Address offset: 0x20 */
+ __IO uint32_t DTIMER; /*!< SDIO data timer register, Address offset: 0x24 */
+ __IO uint32_t DLEN; /*!< SDIO data length register, Address offset: 0x28 */
+ __IO uint32_t DCTRL; /*!< SDIO data control register, Address offset: 0x2C */
+ __I uint32_t DCOUNT; /*!< SDIO data counter register, Address offset: 0x30 */
+ __I uint32_t STA; /*!< SDIO status register, Address offset: 0x34 */
+ __IO uint32_t ICR; /*!< SDIO interrupt clear register, Address offset: 0x38 */
+ __IO uint32_t MASK; /*!< SDIO mask register, Address offset: 0x3C */
+ uint32_t RESERVED0[2]; /*!< Reserved, 0x40-0x44 */
+ __I uint32_t FIFOCNT; /*!< SDIO FIFO counter register, Address offset: 0x48 */
+ uint32_t RESERVED1[13]; /*!< Reserved, 0x4C-0x7C */
+ __IO uint32_t FIFO; /*!< SDIO data FIFO register, Address offset: 0x80 */
+} SDIO_TypeDef;
+
+/**
+ * @brief Serial Peripheral Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t CR1; /*!< SPI control register 1 (not used in I2S mode), Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< SPI control register 2, Address offset: 0x04 */
+ __IO uint32_t SR; /*!< SPI status register, Address offset: 0x08 */
+ __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */
+ __IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
+ __IO uint32_t RXCRCR; /*!< SPI RX CRC register (not used in I2S mode), Address offset: 0x14 */
+ __IO uint32_t TXCRCR; /*!< SPI TX CRC register (not used in I2S mode), Address offset: 0x18 */
+ __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */
+ __IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */
+} SPI_TypeDef;
+
+/**
+ * @brief TIM
+ */
+
+typedef struct
+{
+ __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
+ __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */
+ __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
+ __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
+ __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
+ __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
+ __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
+ __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
+ __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
+ __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */
+ __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
+ __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */
+ __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
+ __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
+ __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
+ __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
+ __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
+ __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
+ __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */
+ __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */
+} TIM_TypeDef;
+
+/**
+ * @brief Universal Synchronous Asynchronous Receiver Transmitter
+ */
+
+typedef struct
+{
+ __IO uint32_t SR; /*!< USART Status register, Address offset: 0x00 */
+ __IO uint32_t DR; /*!< USART Data register, Address offset: 0x04 */
+ __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x08 */
+ __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x0C */
+ __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x10 */
+ __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x14 */
+ __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x18 */
+} USART_TypeDef;
+
+/**
+ * @brief Window WATCHDOG
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
+ __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
+ __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
+} WWDG_TypeDef;
+
+
+/**
+ * @brief __USB_OTG_Core_register
+ */
+typedef struct
+{
+ __IO uint32_t GOTGCTL; /*!< USB_OTG Control and Status Register Address offset : 0x00 */
+ __IO uint32_t GOTGINT; /*!< USB_OTG Interrupt Register Address offset : 0x04 */
+ __IO uint32_t GAHBCFG; /*!< Core AHB Configuration Register Address offset : 0x08 */
+ __IO uint32_t GUSBCFG; /*!< Core USB Configuration Register Address offset : 0x0C */
+ __IO uint32_t GRSTCTL; /*!< Core Reset Register Address offset : 0x10 */
+ __IO uint32_t GINTSTS; /*!< Core Interrupt Register Address offset : 0x14 */
+ __IO uint32_t GINTMSK; /*!< Core Interrupt Mask Register Address offset : 0x18 */
+ __IO uint32_t GRXSTSR; /*!< Receive Sts Q Read Register Address offset : 0x1C */
+ __IO uint32_t GRXSTSP; /*!< Receive Sts Q Read & POP Register Address offset : 0x20 */
+ __IO uint32_t GRXFSIZ; /* Receive FIFO Size Register Address offset : 0x24 */
+ __IO uint32_t DIEPTXF0_HNPTXFSIZ; /*!< EP0 / Non Periodic Tx FIFO Size Register Address offset : 0x28 */
+ __IO uint32_t HNPTXSTS; /*!< Non Periodic Tx FIFO/Queue Sts reg Address offset : 0x2C */
+ uint32_t Reserved30[2]; /* Reserved Address offset : 0x30 */
+ __IO uint32_t GCCFG; /*!< General Purpose IO Register Address offset : 0x38 */
+ __IO uint32_t CID; /*!< User ID Register Address offset : 0x3C */
+ uint32_t Reserved40[48]; /*!< Reserved Address offset : 0x40-0xFF */
+ __IO uint32_t HPTXFSIZ; /*!< Host Periodic Tx FIFO Size Reg Address offset : 0x100 */
+ __IO uint32_t DIEPTXF[0x0F]; /*!< dev Periodic Transmit FIFO */
+}
+USB_OTG_GlobalTypeDef;
+
+
+
+/**
+ * @brief __device_Registers
+ */
+typedef struct
+{
+ __IO uint32_t DCFG; /*!< dev Configuration Register Address offset : 0x800 */
+ __IO uint32_t DCTL; /*!< dev Control Register Address offset : 0x804 */
+ __IO uint32_t DSTS; /*!< dev Status Register (RO) Address offset : 0x808 */
+ uint32_t Reserved0C; /*!< Reserved Address offset : 0x80C */
+ __IO uint32_t DIEPMSK; /* !< dev IN Endpoint Mask Address offset : 0x810 */
+ __IO uint32_t DOEPMSK; /*!< dev OUT Endpoint Mask Address offset : 0x814 */
+ __IO uint32_t DAINT; /*!< dev All Endpoints Itr Reg Address offset : 0x818 */
+ __IO uint32_t DAINTMSK; /*!< dev All Endpoints Itr Mask Address offset : 0x81C */
+ uint32_t Reserved20; /*!< Reserved Address offset : 0x820 */
+ uint32_t Reserved9; /*!< Reserved Address offset : 0x824 */
+ __IO uint32_t DVBUSDIS; /*!< dev VBUS discharge Register Address offset : 0x828 */
+ __IO uint32_t DVBUSPULSE; /*!< dev VBUS Pulse Register Address offset : 0x82C */
+ __IO uint32_t DTHRCTL; /*!< dev thr Address offset : 0x830 */
+ __IO uint32_t DIEPEMPMSK; /*!< dev empty msk Address offset : 0x834 */
+ __IO uint32_t DEACHINT; /*!< dedicated EP interrupt Address offset : 0x838 */
+ __IO uint32_t DEACHMSK; /*!< dedicated EP msk Address offset : 0x83C */
+ uint32_t Reserved40; /*!< dedicated EP mask Address offset : 0x840 */
+ __IO uint32_t DINEP1MSK; /*!< dedicated EP mask Address offset : 0x844 */
+ uint32_t Reserved44[15]; /*!< Reserved Address offset : 0x844-0x87C */
+ __IO uint32_t DOUTEP1MSK; /*!< dedicated EP msk Address offset : 0x884 */
+}
+USB_OTG_DeviceTypeDef;
+
+
+/**
+ * @brief __IN_Endpoint-Specific_Register
+ */
+typedef struct
+{
+ __IO uint32_t DIEPCTL; /* dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h */
+ uint32_t Reserved04; /* Reserved 900h + (ep_num * 20h) + 04h */
+ __IO uint32_t DIEPINT; /* dev IN Endpoint Itr Reg 900h + (ep_num * 20h) + 08h */
+ uint32_t Reserved0C; /* Reserved 900h + (ep_num * 20h) + 0Ch */
+ __IO uint32_t DIEPTSIZ; /* IN Endpoint Txfer Size 900h + (ep_num * 20h) + 10h */
+ __IO uint32_t DIEPDMA; /* IN Endpoint DMA Address Reg 900h + (ep_num * 20h) + 14h */
+ __IO uint32_t DTXFSTS; /*IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h */
+ uint32_t Reserved18; /* Reserved 900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch */
+}
+USB_OTG_INEndpointTypeDef;
+
+
+/**
+ * @brief __OUT_Endpoint-Specific_Registers
+ */
+typedef struct
+{
+ __IO uint32_t DOEPCTL; /* dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h*/
+ uint32_t Reserved04; /* Reserved B00h + (ep_num * 20h) + 04h*/
+ __IO uint32_t DOEPINT; /* dev OUT Endpoint Itr Reg B00h + (ep_num * 20h) + 08h*/
+ uint32_t Reserved0C; /* Reserved B00h + (ep_num * 20h) + 0Ch*/
+ __IO uint32_t DOEPTSIZ; /* dev OUT Endpoint Txfer Size B00h + (ep_num * 20h) + 10h*/
+ __IO uint32_t DOEPDMA; /* dev OUT Endpoint DMA Address B00h + (ep_num * 20h) + 14h*/
+ uint32_t Reserved18[2]; /* Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch*/
+}
+USB_OTG_OUTEndpointTypeDef;
+
+
+/**
+ * @brief __Host_Mode_Register_Structures
+ */
+typedef struct
+{
+ __IO uint32_t HCFG; /* Host Configuration Register 400h*/
+ __IO uint32_t HFIR; /* Host Frame Interval Register 404h*/
+ __IO uint32_t HFNUM; /* Host Frame Nbr/Frame Remaining 408h*/
+ uint32_t Reserved40C; /* Reserved 40Ch*/
+ __IO uint32_t HPTXSTS; /* Host Periodic Tx FIFO/ Queue Status 410h*/
+ __IO uint32_t HAINT; /* Host All Channels Interrupt Register 414h*/
+ __IO uint32_t HAINTMSK; /* Host All Channels Interrupt Mask 418h*/
+}
+USB_OTG_HostTypeDef;
+
+
+/**
+ * @brief __Host_Channel_Specific_Registers
+ */
+typedef struct
+{
+ __IO uint32_t HCCHAR;
+ __IO uint32_t HCSPLT;
+ __IO uint32_t HCINT;
+ __IO uint32_t HCINTMSK;
+ __IO uint32_t HCTSIZ;
+ __IO uint32_t HCDMA;
+ uint32_t Reserved[2];
+}
+USB_OTG_HostChannelTypeDef;
+
+
+/**
+ * @brief Peripheral_memory_map
+ */
+#define FLASH_BASE 0x08000000U /*!< FLASH(up to 1 MB) base address in the alias region */
+#define SRAM1_BASE 0x20000000U /*!< SRAM1(128 KB) base address in the alias region */
+#define PERIPH_BASE 0x40000000U /*!< Peripheral base address in the alias region */
+#define BKPSRAM_BASE 0x40024000U /*!< Backup SRAM(4 KB) base address in the alias region */
+#define SRAM1_BB_BASE 0x22000000U /*!< SRAM1(128 KB) base address in the bit-band region */
+#define PERIPH_BB_BASE 0x42000000U /*!< Peripheral base address in the bit-band region */
+#define BKPSRAM_BB_BASE 0x42480000U /*!< Backup SRAM(4 KB) base address in the bit-band region */
+#define FLASH_END 0x0807FFFFU /*!< FLASH end address */
+
+/* Legacy defines */
+#define SRAM_BASE SRAM1_BASE
+#define SRAM_BB_BASE SRAM1_BB_BASE
+
+
+/*!< Peripheral memory map */
+#define APB1PERIPH_BASE PERIPH_BASE
+#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000U)
+#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000U)
+#define AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000U)
+
+/*!< APB1 peripherals */
+#define TIM2_BASE (APB1PERIPH_BASE + 0x0000U)
+#define TIM3_BASE (APB1PERIPH_BASE + 0x0400U)
+#define TIM4_BASE (APB1PERIPH_BASE + 0x0800U)
+#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00U)
+#define RTC_BASE (APB1PERIPH_BASE + 0x2800U)
+#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00U)
+#define IWDG_BASE (APB1PERIPH_BASE + 0x3000U)
+#define I2S2ext_BASE (APB1PERIPH_BASE + 0x3400U)
+#define SPI2_BASE (APB1PERIPH_BASE + 0x3800U)
+#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00U)
+#define I2S3ext_BASE (APB1PERIPH_BASE + 0x4000U)
+#define USART2_BASE (APB1PERIPH_BASE + 0x4400U)
+#define I2C1_BASE (APB1PERIPH_BASE + 0x5400U)
+#define I2C2_BASE (APB1PERIPH_BASE + 0x5800U)
+#define I2C3_BASE (APB1PERIPH_BASE + 0x5C00U)
+#define PWR_BASE (APB1PERIPH_BASE + 0x7000U)
+
+/*!< APB2 peripherals */
+#define TIM1_BASE (APB2PERIPH_BASE + 0x0000U)
+#define USART1_BASE (APB2PERIPH_BASE + 0x1000U)
+#define USART6_BASE (APB2PERIPH_BASE + 0x1400U)
+#define ADC1_BASE (APB2PERIPH_BASE + 0x2000U)
+#define ADC_BASE (APB2PERIPH_BASE + 0x2300U)
+#define SDIO_BASE (APB2PERIPH_BASE + 0x2C00U)
+#define SPI1_BASE (APB2PERIPH_BASE + 0x3000U)
+#define SPI4_BASE (APB2PERIPH_BASE + 0x3400U)
+#define SYSCFG_BASE (APB2PERIPH_BASE + 0x3800U)
+#define EXTI_BASE (APB2PERIPH_BASE + 0x3C00U)
+#define TIM9_BASE (APB2PERIPH_BASE + 0x4000U)
+#define TIM10_BASE (APB2PERIPH_BASE + 0x4400U)
+#define TIM11_BASE (APB2PERIPH_BASE + 0x4800U)
+#define SPI5_BASE (APB2PERIPH_BASE + 0x5000U)
+
+/*!< AHB1 peripherals */
+#define GPIOA_BASE (AHB1PERIPH_BASE + 0x0000U)
+#define GPIOB_BASE (AHB1PERIPH_BASE + 0x0400U)
+#define GPIOC_BASE (AHB1PERIPH_BASE + 0x0800U)
+#define GPIOD_BASE (AHB1PERIPH_BASE + 0x0C00U)
+#define GPIOE_BASE (AHB1PERIPH_BASE + 0x1000U)
+#define GPIOH_BASE (AHB1PERIPH_BASE + 0x1C00U)
+#define CRC_BASE (AHB1PERIPH_BASE + 0x3000U)
+#define RCC_BASE (AHB1PERIPH_BASE + 0x3800U)
+#define FLASH_R_BASE (AHB1PERIPH_BASE + 0x3C00U)
+#define DMA1_BASE (AHB1PERIPH_BASE + 0x6000U)
+#define DMA1_Stream0_BASE (DMA1_BASE + 0x010U)
+#define DMA1_Stream1_BASE (DMA1_BASE + 0x028U)
+#define DMA1_Stream2_BASE (DMA1_BASE + 0x040U)
+#define DMA1_Stream3_BASE (DMA1_BASE + 0x058U)
+#define DMA1_Stream4_BASE (DMA1_BASE + 0x070U)
+#define DMA1_Stream5_BASE (DMA1_BASE + 0x088U)
+#define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0U)
+#define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8U)
+#define DMA2_BASE (AHB1PERIPH_BASE + 0x6400U)
+#define DMA2_Stream0_BASE (DMA2_BASE + 0x010U)
+#define DMA2_Stream1_BASE (DMA2_BASE + 0x028U)
+#define DMA2_Stream2_BASE (DMA2_BASE + 0x040U)
+#define DMA2_Stream3_BASE (DMA2_BASE + 0x058U)
+#define DMA2_Stream4_BASE (DMA2_BASE + 0x070U)
+#define DMA2_Stream5_BASE (DMA2_BASE + 0x088U)
+#define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0U)
+#define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8U)
+
+/* Debug MCU registers base address */
+#define DBGMCU_BASE 0xE0042000U
+
+/*!< USB registers base address */
+#define USB_OTG_FS_PERIPH_BASE 0x50000000U
+
+#define USB_OTG_GLOBAL_BASE 0x000U
+#define USB_OTG_DEVICE_BASE 0x800U
+#define USB_OTG_IN_ENDPOINT_BASE 0x900U
+#define USB_OTG_OUT_ENDPOINT_BASE 0xB00U
+#define USB_OTG_EP_REG_SIZE 0x20U
+#define USB_OTG_HOST_BASE 0x400U
+#define USB_OTG_HOST_PORT_BASE 0x440U
+#define USB_OTG_HOST_CHANNEL_BASE 0x500U
+#define USB_OTG_HOST_CHANNEL_SIZE 0x20U
+#define USB_OTG_PCGCCTL_BASE 0xE00U
+#define USB_OTG_FIFO_BASE 0x1000U
+#define USB_OTG_FIFO_SIZE 0x1000U
+
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_declaration
+ * @{
+ */
+#define TIM2 ((TIM_TypeDef *) TIM2_BASE)
+#define TIM3 ((TIM_TypeDef *) TIM3_BASE)
+#define TIM4 ((TIM_TypeDef *) TIM4_BASE)
+#define TIM5 ((TIM_TypeDef *) TIM5_BASE)
+#define RTC ((RTC_TypeDef *) RTC_BASE)
+#define WWDG ((WWDG_TypeDef *) WWDG_BASE)
+#define IWDG ((IWDG_TypeDef *) IWDG_BASE)
+#define I2S2ext ((SPI_TypeDef *) I2S2ext_BASE)
+#define SPI2 ((SPI_TypeDef *) SPI2_BASE)
+#define SPI3 ((SPI_TypeDef *) SPI3_BASE)
+#define I2S3ext ((SPI_TypeDef *) I2S3ext_BASE)
+#define USART2 ((USART_TypeDef *) USART2_BASE)
+#define I2C1 ((I2C_TypeDef *) I2C1_BASE)
+#define I2C2 ((I2C_TypeDef *) I2C2_BASE)
+#define I2C3 ((I2C_TypeDef *) I2C3_BASE)
+#define PWR ((PWR_TypeDef *) PWR_BASE)
+#define TIM1 ((TIM_TypeDef *) TIM1_BASE)
+#define USART1 ((USART_TypeDef *) USART1_BASE)
+#define USART6 ((USART_TypeDef *) USART6_BASE)
+#define ADC ((ADC_Common_TypeDef *) ADC_BASE)
+#define ADC1 ((ADC_TypeDef *) ADC1_BASE)
+#define SDIO ((SDIO_TypeDef *) SDIO_BASE)
+#define SPI1 ((SPI_TypeDef *) SPI1_BASE)
+#define SPI4 ((SPI_TypeDef *) SPI4_BASE)
+#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
+#define EXTI ((EXTI_TypeDef *) EXTI_BASE)
+#define TIM9 ((TIM_TypeDef *) TIM9_BASE)
+#define TIM10 ((TIM_TypeDef *) TIM10_BASE)
+#define TIM11 ((TIM_TypeDef *) TIM11_BASE)
+#define SPI5 ((SPI_TypeDef *) SPI5_BASE)
+#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
+#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
+#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
+#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
+#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
+#define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
+#define CRC ((CRC_TypeDef *) CRC_BASE)
+#define RCC ((RCC_TypeDef *) RCC_BASE)
+#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
+#define DMA1 ((DMA_TypeDef *) DMA1_BASE)
+#define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)
+#define DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)
+#define DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)
+#define DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)
+#define DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)
+#define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)
+#define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)
+#define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)
+#define DMA2 ((DMA_TypeDef *) DMA2_BASE)
+#define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)
+#define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
+#define DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)
+#define DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)
+#define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)
+#define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)
+#define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)
+#define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)
+
+#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
+
+#define USB_OTG_FS ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE)
+
+/**
+ * @}
+ */
+
+/** @addtogroup Exported_constants
+ * @{
+ */
+
+ /** @addtogroup Peripheral_Registers_Bits_Definition
+ * @{
+ */
+
+/******************************************************************************/
+/* Peripheral Registers_Bits_Definition */
+/******************************************************************************/
+
+/******************************************************************************/
+/* */
+/* Analog to Digital Converter */
+/* */
+/******************************************************************************/
+/******************** Bit definition for ADC_SR register ********************/
+#define ADC_SR_AWD 0x00000001U /*!<Analog watchdog flag */
+#define ADC_SR_EOC 0x00000002U /*!<End of conversion */
+#define ADC_SR_JEOC 0x00000004U /*!<Injected channel end of conversion */
+#define ADC_SR_JSTRT 0x00000008U /*!<Injected channel Start flag */
+#define ADC_SR_STRT 0x00000010U /*!<Regular channel Start flag */
+#define ADC_SR_OVR 0x00000020U /*!<Overrun flag */
+
+/******************* Bit definition for ADC_CR1 register ********************/
+#define ADC_CR1_AWDCH 0x0000001FU /*!<AWDCH[4:0] bits (Analog watchdog channel select bits) */
+#define ADC_CR1_AWDCH_0 0x00000001U /*!<Bit 0 */
+#define ADC_CR1_AWDCH_1 0x00000002U /*!<Bit 1 */
+#define ADC_CR1_AWDCH_2 0x00000004U /*!<Bit 2 */
+#define ADC_CR1_AWDCH_3 0x00000008U /*!<Bit 3 */
+#define ADC_CR1_AWDCH_4 0x00000010U /*!<Bit 4 */
+#define ADC_CR1_EOCIE 0x00000020U /*!<Interrupt enable for EOC */
+#define ADC_CR1_AWDIE 0x00000040U /*!<AAnalog Watchdog interrupt enable */
+#define ADC_CR1_JEOCIE 0x00000080U /*!<Interrupt enable for injected channels */
+#define ADC_CR1_SCAN 0x00000100U /*!<Scan mode */
+#define ADC_CR1_AWDSGL 0x00000200U /*!<Enable the watchdog on a single channel in scan mode */
+#define ADC_CR1_JAUTO 0x00000400U /*!<Automatic injected group conversion */
+#define ADC_CR1_DISCEN 0x00000800U /*!<Discontinuous mode on regular channels */
+#define ADC_CR1_JDISCEN 0x00001000U /*!<Discontinuous mode on injected channels */
+#define ADC_CR1_DISCNUM 0x0000E000U /*!<DISCNUM[2:0] bits (Discontinuous mode channel count) */
+#define ADC_CR1_DISCNUM_0 0x00002000U /*!<Bit 0 */
+#define ADC_CR1_DISCNUM_1 0x00004000U /*!<Bit 1 */
+#define ADC_CR1_DISCNUM_2 0x00008000U /*!<Bit 2 */
+#define ADC_CR1_JAWDEN 0x00400000U /*!<Analog watchdog enable on injected channels */
+#define ADC_CR1_AWDEN 0x00800000U /*!<Analog watchdog enable on regular channels */
+#define ADC_CR1_RES 0x03000000U /*!<RES[2:0] bits (Resolution) */
+#define ADC_CR1_RES_0 0x01000000U /*!<Bit 0 */
+#define ADC_CR1_RES_1 0x02000000U /*!<Bit 1 */
+#define ADC_CR1_OVRIE 0x04000000U /*!<overrun interrupt enable */
+
+/******************* Bit definition for ADC_CR2 register ********************/
+#define ADC_CR2_ADON 0x00000001U /*!<A/D Converter ON / OFF */
+#define ADC_CR2_CONT 0x00000002U /*!<Continuous Conversion */
+#define ADC_CR2_DMA 0x00000100U /*!<Direct Memory access mode */
+#define ADC_CR2_DDS 0x00000200U /*!<DMA disable selection (Single ADC) */
+#define ADC_CR2_EOCS 0x00000400U /*!<End of conversion selection */
+#define ADC_CR2_ALIGN 0x00000800U /*!<Data Alignment */
+#define ADC_CR2_JEXTSEL 0x000F0000U /*!<JEXTSEL[3:0] bits (External event select for injected group) */
+#define ADC_CR2_JEXTSEL_0 0x00010000U /*!<Bit 0 */
+#define ADC_CR2_JEXTSEL_1 0x00020000U /*!<Bit 1 */
+#define ADC_CR2_JEXTSEL_2 0x00040000U /*!<Bit 2 */
+#define ADC_CR2_JEXTSEL_3 0x00080000U /*!<Bit 3 */
+#define ADC_CR2_JEXTEN 0x00300000U /*!<JEXTEN[1:0] bits (External Trigger Conversion mode for injected channelsp) */
+#define ADC_CR2_JEXTEN_0 0x00100000U /*!<Bit 0 */
+#define ADC_CR2_JEXTEN_1 0x00200000U /*!<Bit 1 */
+#define ADC_CR2_JSWSTART 0x00400000U /*!<Start Conversion of injected channels */
+#define ADC_CR2_EXTSEL 0x0F000000U /*!<EXTSEL[3:0] bits (External Event Select for regular group) */
+#define ADC_CR2_EXTSEL_0 0x01000000U /*!<Bit 0 */
+#define ADC_CR2_EXTSEL_1 0x02000000U /*!<Bit 1 */
+#define ADC_CR2_EXTSEL_2 0x04000000U /*!<Bit 2 */
+#define ADC_CR2_EXTSEL_3 0x08000000U /*!<Bit 3 */
+#define ADC_CR2_EXTEN 0x30000000U /*!<EXTEN[1:0] bits (External Trigger Conversion mode for regular channelsp) */
+#define ADC_CR2_EXTEN_0 0x10000000U /*!<Bit 0 */
+#define ADC_CR2_EXTEN_1 0x20000000U /*!<Bit 1 */
+#define ADC_CR2_SWSTART 0x40000000U /*!<Start Conversion of regular channels */
+
+/****************** Bit definition for ADC_SMPR1 register *******************/
+#define ADC_SMPR1_SMP10 0x00000007U /*!<SMP10[2:0] bits (Channel 10 Sample time selection) */
+#define ADC_SMPR1_SMP10_0 0x00000001U /*!<Bit 0 */
+#define ADC_SMPR1_SMP10_1 0x00000002U /*!<Bit 1 */
+#define ADC_SMPR1_SMP10_2 0x00000004U /*!<Bit 2 */
+#define ADC_SMPR1_SMP11 0x00000038U /*!<SMP11[2:0] bits (Channel 11 Sample time selection) */
+#define ADC_SMPR1_SMP11_0 0x00000008U /*!<Bit 0 */
+#define ADC_SMPR1_SMP11_1 0x00000010U /*!<Bit 1 */
+#define ADC_SMPR1_SMP11_2 0x00000020U /*!<Bit 2 */
+#define ADC_SMPR1_SMP12 0x000001C0U /*!<SMP12[2:0] bits (Channel 12 Sample time selection) */
+#define ADC_SMPR1_SMP12_0 0x00000040U /*!<Bit 0 */
+#define ADC_SMPR1_SMP12_1 0x00000080U /*!<Bit 1 */
+#define ADC_SMPR1_SMP12_2 0x00000100U /*!<Bit 2 */
+#define ADC_SMPR1_SMP13 0x00000E00U /*!<SMP13[2:0] bits (Channel 13 Sample time selection) */
+#define ADC_SMPR1_SMP13_0 0x00000200U /*!<Bit 0 */
+#define ADC_SMPR1_SMP13_1 0x00000400U /*!<Bit 1 */
+#define ADC_SMPR1_SMP13_2 0x00000800U /*!<Bit 2 */
+#define ADC_SMPR1_SMP14 0x00007000U /*!<SMP14[2:0] bits (Channel 14 Sample time selection) */
+#define ADC_SMPR1_SMP14_0 0x00001000U /*!<Bit 0 */
+#define ADC_SMPR1_SMP14_1 0x00002000U /*!<Bit 1 */
+#define ADC_SMPR1_SMP14_2 0x00004000U /*!<Bit 2 */
+#define ADC_SMPR1_SMP15 0x00038000U /*!<SMP15[2:0] bits (Channel 15 Sample time selection) */
+#define ADC_SMPR1_SMP15_0 0x00008000U /*!<Bit 0 */
+#define ADC_SMPR1_SMP15_1 0x00010000U /*!<Bit 1 */
+#define ADC_SMPR1_SMP15_2 0x00020000U /*!<Bit 2 */
+#define ADC_SMPR1_SMP16 0x001C0000U /*!<SMP16[2:0] bits (Channel 16 Sample time selection) */
+#define ADC_SMPR1_SMP16_0 0x00040000U /*!<Bit 0 */
+#define ADC_SMPR1_SMP16_1 0x00080000U /*!<Bit 1 */
+#define ADC_SMPR1_SMP16_2 0x00100000U /*!<Bit 2 */
+#define ADC_SMPR1_SMP17 0x00E00000U /*!<SMP17[2:0] bits (Channel 17 Sample time selection) */
+#define ADC_SMPR1_SMP17_0 0x00200000U /*!<Bit 0 */
+#define ADC_SMPR1_SMP17_1 0x00400000U /*!<Bit 1 */
+#define ADC_SMPR1_SMP17_2 0x00800000U /*!<Bit 2 */
+#define ADC_SMPR1_SMP18 0x07000000U /*!<SMP18[2:0] bits (Channel 18 Sample time selection) */
+#define ADC_SMPR1_SMP18_0 0x01000000U /*!<Bit 0 */
+#define ADC_SMPR1_SMP18_1 0x02000000U /*!<Bit 1 */
+#define ADC_SMPR1_SMP18_2 0x04000000U /*!<Bit 2 */
+
+/****************** Bit definition for ADC_SMPR2 register *******************/
+#define ADC_SMPR2_SMP0 0x00000007U /*!<SMP0[2:0] bits (Channel 0 Sample time selection) */
+#define ADC_SMPR2_SMP0_0 0x00000001U /*!<Bit 0 */
+#define ADC_SMPR2_SMP0_1 0x00000002U /*!<Bit 1 */
+#define ADC_SMPR2_SMP0_2 0x00000004U /*!<Bit 2 */
+#define ADC_SMPR2_SMP1 0x00000038U /*!<SMP1[2:0] bits (Channel 1 Sample time selection) */
+#define ADC_SMPR2_SMP1_0 0x00000008U /*!<Bit 0 */
+#define ADC_SMPR2_SMP1_1 0x00000010U /*!<Bit 1 */
+#define ADC_SMPR2_SMP1_2 0x00000020U /*!<Bit 2 */
+#define ADC_SMPR2_SMP2 0x000001C0U /*!<SMP2[2:0] bits (Channel 2 Sample time selection) */
+#define ADC_SMPR2_SMP2_0 0x00000040U /*!<Bit 0 */
+#define ADC_SMPR2_SMP2_1 0x00000080U /*!<Bit 1 */
+#define ADC_SMPR2_SMP2_2 0x00000100U /*!<Bit 2 */
+#define ADC_SMPR2_SMP3 0x00000E00U /*!<SMP3[2:0] bits (Channel 3 Sample time selection) */
+#define ADC_SMPR2_SMP3_0 0x00000200U /*!<Bit 0 */
+#define ADC_SMPR2_SMP3_1 0x00000400U /*!<Bit 1 */
+#define ADC_SMPR2_SMP3_2 0x00000800U /*!<Bit 2 */
+#define ADC_SMPR2_SMP4 0x00007000U /*!<SMP4[2:0] bits (Channel 4 Sample time selection) */
+#define ADC_SMPR2_SMP4_0 0x00001000U /*!<Bit 0 */
+#define ADC_SMPR2_SMP4_1 0x00002000U /*!<Bit 1 */
+#define ADC_SMPR2_SMP4_2 0x00004000U /*!<Bit 2 */
+#define ADC_SMPR2_SMP5 0x00038000U /*!<SMP5[2:0] bits (Channel 5 Sample time selection) */
+#define ADC_SMPR2_SMP5_0 0x00008000U /*!<Bit 0 */
+#define ADC_SMPR2_SMP5_1 0x00010000U /*!<Bit 1 */
+#define ADC_SMPR2_SMP5_2 0x00020000U /*!<Bit 2 */
+#define ADC_SMPR2_SMP6 0x001C0000U /*!<SMP6[2:0] bits (Channel 6 Sample time selection) */
+#define ADC_SMPR2_SMP6_0 0x00040000U /*!<Bit 0 */
+#define ADC_SMPR2_SMP6_1 0x00080000U /*!<Bit 1 */
+#define ADC_SMPR2_SMP6_2 0x00100000U /*!<Bit 2 */
+#define ADC_SMPR2_SMP7 0x00E00000U /*!<SMP7[2:0] bits (Channel 7 Sample time selection) */
+#define ADC_SMPR2_SMP7_0 0x00200000U /*!<Bit 0 */
+#define ADC_SMPR2_SMP7_1 0x00400000U /*!<Bit 1 */
+#define ADC_SMPR2_SMP7_2 0x00800000U /*!<Bit 2 */
+#define ADC_SMPR2_SMP8 0x07000000U /*!<SMP8[2:0] bits (Channel 8 Sample time selection) */
+#define ADC_SMPR2_SMP8_0 0x01000000U /*!<Bit 0 */
+#define ADC_SMPR2_SMP8_1 0x02000000U /*!<Bit 1 */
+#define ADC_SMPR2_SMP8_2 0x04000000U /*!<Bit 2 */
+#define ADC_SMPR2_SMP9 0x38000000U /*!<SMP9[2:0] bits (Channel 9 Sample time selection) */
+#define ADC_SMPR2_SMP9_0 0x08000000U /*!<Bit 0 */
+#define ADC_SMPR2_SMP9_1 0x10000000U /*!<Bit 1 */
+#define ADC_SMPR2_SMP9_2 0x20000000U /*!<Bit 2 */
+
+/****************** Bit definition for ADC_JOFR1 register *******************/
+#define ADC_JOFR1_JOFFSET1 0x0FFFU /*!<Data offset for injected channel 1 */
+
+/****************** Bit definition for ADC_JOFR2 register *******************/
+#define ADC_JOFR2_JOFFSET2 0x0FFFU /*!<Data offset for injected channel 2 */
+
+/****************** Bit definition for ADC_JOFR3 register *******************/
+#define ADC_JOFR3_JOFFSET3 0x0FFFU /*!<Data offset for injected channel 3 */
+
+/****************** Bit definition for ADC_JOFR4 register *******************/
+#define ADC_JOFR4_JOFFSET4 0x0FFFU /*!<Data offset for injected channel 4 */
+
+/******************* Bit definition for ADC_HTR register ********************/
+#define ADC_HTR_HT 0x0FFFU /*!<Analog watchdog high threshold */
+
+/******************* Bit definition for ADC_LTR register ********************/
+#define ADC_LTR_LT 0x0FFFU /*!<Analog watchdog low threshold */
+
+/******************* Bit definition for ADC_SQR1 register *******************/
+#define ADC_SQR1_SQ13 0x0000001FU /*!<SQ13[4:0] bits (13th conversion in regular sequence) */
+#define ADC_SQR1_SQ13_0 0x00000001U /*!<Bit 0 */
+#define ADC_SQR1_SQ13_1 0x00000002U /*!<Bit 1 */
+#define ADC_SQR1_SQ13_2 0x00000004U /*!<Bit 2 */
+#define ADC_SQR1_SQ13_3 0x00000008U /*!<Bit 3 */
+#define ADC_SQR1_SQ13_4 0x00000010U /*!<Bit 4 */
+#define ADC_SQR1_SQ14 0x000003E0U /*!<SQ14[4:0] bits (14th conversion in regular sequence) */
+#define ADC_SQR1_SQ14_0 0x00000020U /*!<Bit 0 */
+#define ADC_SQR1_SQ14_1 0x00000040U /*!<Bit 1 */
+#define ADC_SQR1_SQ14_2 0x00000080U /*!<Bit 2 */
+#define ADC_SQR1_SQ14_3 0x00000100U /*!<Bit 3 */
+#define ADC_SQR1_SQ14_4 0x00000200U /*!<Bit 4 */
+#define ADC_SQR1_SQ15 0x00007C00U /*!<SQ15[4:0] bits (15th conversion in regular sequence) */
+#define ADC_SQR1_SQ15_0 0x00000400U /*!<Bit 0 */
+#define ADC_SQR1_SQ15_1 0x00000800U /*!<Bit 1 */
+#define ADC_SQR1_SQ15_2 0x00001000U /*!<Bit 2 */
+#define ADC_SQR1_SQ15_3 0x00002000U /*!<Bit 3 */
+#define ADC_SQR1_SQ15_4 0x00004000U /*!<Bit 4 */
+#define ADC_SQR1_SQ16 0x000F8000U /*!<SQ16[4:0] bits (16th conversion in regular sequence) */
+#define ADC_SQR1_SQ16_0 0x00008000U /*!<Bit 0 */
+#define ADC_SQR1_SQ16_1 0x00010000U /*!<Bit 1 */
+#define ADC_SQR1_SQ16_2 0x00020000U /*!<Bit 2 */
+#define ADC_SQR1_SQ16_3 0x00040000U /*!<Bit 3 */
+#define ADC_SQR1_SQ16_4 0x00080000U /*!<Bit 4 */
+#define ADC_SQR1_L 0x00F00000U /*!<L[3:0] bits (Regular channel sequence length) */
+#define ADC_SQR1_L_0 0x00100000U /*!<Bit 0 */
+#define ADC_SQR1_L_1 0x00200000U /*!<Bit 1 */
+#define ADC_SQR1_L_2 0x00400000U /*!<Bit 2 */
+#define ADC_SQR1_L_3 0x00800000U /*!<Bit 3 */
+
+/******************* Bit definition for ADC_SQR2 register *******************/
+#define ADC_SQR2_SQ7 0x0000001FU /*!<SQ7[4:0] bits (7th conversion in regular sequence) */
+#define ADC_SQR2_SQ7_0 0x00000001U /*!<Bit 0 */
+#define ADC_SQR2_SQ7_1 0x00000002U /*!<Bit 1 */
+#define ADC_SQR2_SQ7_2 0x00000004U /*!<Bit 2 */
+#define ADC_SQR2_SQ7_3 0x00000008U /*!<Bit 3 */
+#define ADC_SQR2_SQ7_4 0x00000010U /*!<Bit 4 */
+#define ADC_SQR2_SQ8 0x000003E0U /*!<SQ8[4:0] bits (8th conversion in regular sequence) */
+#define ADC_SQR2_SQ8_0 0x00000020U /*!<Bit 0 */
+#define ADC_SQR2_SQ8_1 0x00000040U /*!<Bit 1 */
+#define ADC_SQR2_SQ8_2 0x00000080U /*!<Bit 2 */
+#define ADC_SQR2_SQ8_3 0x00000100U /*!<Bit 3 */
+#define ADC_SQR2_SQ8_4 0x00000200U /*!<Bit 4 */
+#define ADC_SQR2_SQ9 0x00007C00U /*!<SQ9[4:0] bits (9th conversion in regular sequence) */
+#define ADC_SQR2_SQ9_0 0x00000400U /*!<Bit 0 */
+#define ADC_SQR2_SQ9_1 0x00000800U /*!<Bit 1 */
+#define ADC_SQR2_SQ9_2 0x00001000U /*!<Bit 2 */
+#define ADC_SQR2_SQ9_3 0x00002000U /*!<Bit 3 */
+#define ADC_SQR2_SQ9_4 0x00004000U /*!<Bit 4 */
+#define ADC_SQR2_SQ10 0x000F8000U /*!<SQ10[4:0] bits (10th conversion in regular sequence) */
+#define ADC_SQR2_SQ10_0 0x00008000U /*!<Bit 0 */
+#define ADC_SQR2_SQ10_1 0x00010000U /*!<Bit 1 */
+#define ADC_SQR2_SQ10_2 0x00020000U /*!<Bit 2 */
+#define ADC_SQR2_SQ10_3 0x00040000U /*!<Bit 3 */
+#define ADC_SQR2_SQ10_4 0x00080000U /*!<Bit 4 */
+#define ADC_SQR2_SQ11 0x01F00000U /*!<SQ11[4:0] bits (11th conversion in regular sequence) */
+#define ADC_SQR2_SQ11_0 0x00100000U /*!<Bit 0 */
+#define ADC_SQR2_SQ11_1 0x00200000U /*!<Bit 1 */
+#define ADC_SQR2_SQ11_2 0x00400000U /*!<Bit 2 */
+#define ADC_SQR2_SQ11_3 0x00800000U /*!<Bit 3 */
+#define ADC_SQR2_SQ11_4 0x01000000U /*!<Bit 4 */
+#define ADC_SQR2_SQ12 0x3E000000U /*!<SQ12[4:0] bits (12th conversion in regular sequence) */
+#define ADC_SQR2_SQ12_0 0x02000000U /*!<Bit 0 */
+#define ADC_SQR2_SQ12_1 0x04000000U /*!<Bit 1 */
+#define ADC_SQR2_SQ12_2 0x08000000U /*!<Bit 2 */
+#define ADC_SQR2_SQ12_3 0x10000000U /*!<Bit 3 */
+#define ADC_SQR2_SQ12_4 0x20000000U /*!<Bit 4 */
+
+/******************* Bit definition for ADC_SQR3 register *******************/
+#define ADC_SQR3_SQ1 0x0000001FU /*!<SQ1[4:0] bits (1st conversion in regular sequence) */
+#define ADC_SQR3_SQ1_0 0x00000001U /*!<Bit 0 */
+#define ADC_SQR3_SQ1_1 0x00000002U /*!<Bit 1 */
+#define ADC_SQR3_SQ1_2 0x00000004U /*!<Bit 2 */
+#define ADC_SQR3_SQ1_3 0x00000008U /*!<Bit 3 */
+#define ADC_SQR3_SQ1_4 0x00000010U /*!<Bit 4 */
+#define ADC_SQR3_SQ2 0x000003E0U /*!<SQ2[4:0] bits (2nd conversion in regular sequence) */
+#define ADC_SQR3_SQ2_0 0x00000020U /*!<Bit 0 */
+#define ADC_SQR3_SQ2_1 0x00000040U /*!<Bit 1 */
+#define ADC_SQR3_SQ2_2 0x00000080U /*!<Bit 2 */
+#define ADC_SQR3_SQ2_3 0x00000100U /*!<Bit 3 */
+#define ADC_SQR3_SQ2_4 0x00000200U /*!<Bit 4 */
+#define ADC_SQR3_SQ3 0x00007C00U /*!<SQ3[4:0] bits (3rd conversion in regular sequence) */
+#define ADC_SQR3_SQ3_0 0x00000400U /*!<Bit 0 */
+#define ADC_SQR3_SQ3_1 0x00000800U /*!<Bit 1 */
+#define ADC_SQR3_SQ3_2 0x00001000U /*!<Bit 2 */
+#define ADC_SQR3_SQ3_3 0x00002000U /*!<Bit 3 */
+#define ADC_SQR3_SQ3_4 0x00004000U /*!<Bit 4 */
+#define ADC_SQR3_SQ4 0x000F8000U /*!<SQ4[4:0] bits (4th conversion in regular sequence) */
+#define ADC_SQR3_SQ4_0 0x00008000U /*!<Bit 0 */
+#define ADC_SQR3_SQ4_1 0x00010000U /*!<Bit 1 */
+#define ADC_SQR3_SQ4_2 0x00020000U /*!<Bit 2 */
+#define ADC_SQR3_SQ4_3 0x00040000U /*!<Bit 3 */
+#define ADC_SQR3_SQ4_4 0x00080000U /*!<Bit 4 */
+#define ADC_SQR3_SQ5 0x01F00000U /*!<SQ5[4:0] bits (5th conversion in regular sequence) */
+#define ADC_SQR3_SQ5_0 0x00100000U /*!<Bit 0 */
+#define ADC_SQR3_SQ5_1 0x00200000U /*!<Bit 1 */
+#define ADC_SQR3_SQ5_2 0x00400000U /*!<Bit 2 */
+#define ADC_SQR3_SQ5_3 0x00800000U /*!<Bit 3 */
+#define ADC_SQR3_SQ5_4 0x01000000U /*!<Bit 4 */
+#define ADC_SQR3_SQ6 0x3E000000U /*!<SQ6[4:0] bits (6th conversion in regular sequence) */
+#define ADC_SQR3_SQ6_0 0x02000000U /*!<Bit 0 */
+#define ADC_SQR3_SQ6_1 0x04000000U /*!<Bit 1 */
+#define ADC_SQR3_SQ6_2 0x08000000U /*!<Bit 2 */
+#define ADC_SQR3_SQ6_3 0x10000000U /*!<Bit 3 */
+#define ADC_SQR3_SQ6_4 0x20000000U /*!<Bit 4 */
+
+/******************* Bit definition for ADC_JSQR register *******************/
+#define ADC_JSQR_JSQ1 0x0000001FU /*!<JSQ1[4:0] bits (1st conversion in injected sequence) */
+#define ADC_JSQR_JSQ1_0 0x00000001U /*!<Bit 0 */
+#define ADC_JSQR_JSQ1_1 0x00000002U /*!<Bit 1 */
+#define ADC_JSQR_JSQ1_2 0x00000004U /*!<Bit 2 */
+#define ADC_JSQR_JSQ1_3 0x00000008U /*!<Bit 3 */
+#define ADC_JSQR_JSQ1_4 0x00000010U /*!<Bit 4 */
+#define ADC_JSQR_JSQ2 0x000003E0U /*!<JSQ2[4:0] bits (2nd conversion in injected sequence) */
+#define ADC_JSQR_JSQ2_0 0x00000020U /*!<Bit 0 */
+#define ADC_JSQR_JSQ2_1 0x00000040U /*!<Bit 1 */
+#define ADC_JSQR_JSQ2_2 0x00000080U /*!<Bit 2 */
+#define ADC_JSQR_JSQ2_3 0x00000100U /*!<Bit 3 */
+#define ADC_JSQR_JSQ2_4 0x00000200U /*!<Bit 4 */
+#define ADC_JSQR_JSQ3 0x00007C00U /*!<JSQ3[4:0] bits (3rd conversion in injected sequence) */
+#define ADC_JSQR_JSQ3_0 0x00000400U /*!<Bit 0 */
+#define ADC_JSQR_JSQ3_1 0x00000800U /*!<Bit 1 */
+#define ADC_JSQR_JSQ3_2 0x00001000U /*!<Bit 2 */
+#define ADC_JSQR_JSQ3_3 0x00002000U /*!<Bit 3 */
+#define ADC_JSQR_JSQ3_4 0x00004000U /*!<Bit 4 */
+#define ADC_JSQR_JSQ4 0x000F8000U /*!<JSQ4[4:0] bits (4th conversion in injected sequence) */
+#define ADC_JSQR_JSQ4_0 0x00008000U /*!<Bit 0 */
+#define ADC_JSQR_JSQ4_1 0x00010000U /*!<Bit 1 */
+#define ADC_JSQR_JSQ4_2 0x00020000U /*!<Bit 2 */
+#define ADC_JSQR_JSQ4_3 0x00040000U /*!<Bit 3 */
+#define ADC_JSQR_JSQ4_4 0x00080000U /*!<Bit 4 */
+#define ADC_JSQR_JL 0x00300000U /*!<JL[1:0] bits (Injected Sequence length) */
+#define ADC_JSQR_JL_0 0x00100000U /*!<Bit 0 */
+#define ADC_JSQR_JL_1 0x00200000U /*!<Bit 1 */
+
+/******************* Bit definition for ADC_JDR1 register *******************/
+#define ADC_JDR1_JDATA 0xFFFFU /*!<Injected data */
+
+/******************* Bit definition for ADC_JDR2 register *******************/
+#define ADC_JDR2_JDATA 0xFFFFU /*!<Injected data */
+
+/******************* Bit definition for ADC_JDR3 register *******************/
+#define ADC_JDR3_JDATA 0xFFFFU /*!<Injected data */
+
+/******************* Bit definition for ADC_JDR4 register *******************/
+#define ADC_JDR4_JDATA 0xFFFFU /*!<Injected data */
+
+/******************** Bit definition for ADC_DR register ********************/
+#define ADC_DR_DATA 0x0000FFFFU /*!<Regular data */
+#define ADC_DR_ADC2DATA 0xFFFF0000U /*!<ADC2 data */
+
+/******************* Bit definition for ADC_CSR register ********************/
+#define ADC_CSR_AWD1 0x00000001U /*!<ADC1 Analog watchdog flag */
+#define ADC_CSR_EOC1 0x00000002U /*!<ADC1 End of conversion */
+#define ADC_CSR_JEOC1 0x00000004U /*!<ADC1 Injected channel end of conversion */
+#define ADC_CSR_JSTRT1 0x00000008U /*!<ADC1 Injected channel Start flag */
+#define ADC_CSR_STRT1 0x00000010U /*!<ADC1 Regular channel Start flag */
+#define ADC_CSR_OVR1 0x00000020U /*!<ADC1 DMA overrun flag */
+#define ADC_CSR_AWD2 0x00000100U /*!<ADC2 Analog watchdog flag */
+#define ADC_CSR_EOC2 0x00000200U /*!<ADC2 End of conversion */
+#define ADC_CSR_JEOC2 0x00000400U /*!<ADC2 Injected channel end of conversion */
+#define ADC_CSR_JSTRT2 0x00000800U /*!<ADC2 Injected channel Start flag */
+#define ADC_CSR_STRT2 0x00001000U /*!<ADC2 Regular channel Start flag */
+#define ADC_CSR_OVR2 0x00002000U /*!<ADC2 DMA overrun flag */
+#define ADC_CSR_AWD3 0x00010000U /*!<ADC3 Analog watchdog flag */
+#define ADC_CSR_EOC3 0x00020000U /*!<ADC3 End of conversion */
+#define ADC_CSR_JEOC3 0x00040000U /*!<ADC3 Injected channel end of conversion */
+#define ADC_CSR_JSTRT3 0x00080000U /*!<ADC3 Injected channel Start flag */
+#define ADC_CSR_STRT3 0x00100000U /*!<ADC3 Regular channel Start flag */
+#define ADC_CSR_OVR3 0x00200000U /*!<ADC3 DMA overrun flag */
+
+/* Legacy defines */
+#define ADC_CSR_DOVR1 ADC_CSR_OVR1
+#define ADC_CSR_DOVR2 ADC_CSR_OVR2
+#define ADC_CSR_DOVR3 ADC_CSR_OVR3
+
+/******************* Bit definition for ADC_CCR register ********************/
+#define ADC_CCR_MULTI 0x0000001FU /*!<MULTI[4:0] bits (Multi-ADC mode selection) */
+#define ADC_CCR_MULTI_0 0x00000001U /*!<Bit 0 */
+#define ADC_CCR_MULTI_1 0x00000002U /*!<Bit 1 */
+#define ADC_CCR_MULTI_2 0x00000004U /*!<Bit 2 */
+#define ADC_CCR_MULTI_3 0x00000008U /*!<Bit 3 */
+#define ADC_CCR_MULTI_4 0x00000010U /*!<Bit 4 */
+#define ADC_CCR_DELAY 0x00000F00U /*!<DELAY[3:0] bits (Delay between 2 sampling phases) */
+#define ADC_CCR_DELAY_0 0x00000100U /*!<Bit 0 */
+#define ADC_CCR_DELAY_1 0x00000200U /*!<Bit 1 */
+#define ADC_CCR_DELAY_2 0x00000400U /*!<Bit 2 */
+#define ADC_CCR_DELAY_3 0x00000800U /*!<Bit 3 */
+#define ADC_CCR_DDS 0x00002000U /*!<DMA disable selection (Multi-ADC mode) */
+#define ADC_CCR_DMA 0x0000C000U /*!<DMA[1:0] bits (Direct Memory Access mode for multimode) */
+#define ADC_CCR_DMA_0 0x00004000U /*!<Bit 0 */
+#define ADC_CCR_DMA_1 0x00008000U /*!<Bit 1 */
+#define ADC_CCR_ADCPRE 0x00030000U /*!<ADCPRE[1:0] bits (ADC prescaler) */
+#define ADC_CCR_ADCPRE_0 0x00010000U /*!<Bit 0 */
+#define ADC_CCR_ADCPRE_1 0x00020000U /*!<Bit 1 */
+#define ADC_CCR_VBATE 0x00400000U /*!<VBAT Enable */
+#define ADC_CCR_TSVREFE 0x00800000U /*!<Temperature Sensor and VREFINT Enable */
+
+/******************* Bit definition for ADC_CDR register ********************/
+#define ADC_CDR_DATA1 0x0000FFFFU /*!<1st data of a pair of regular conversions */
+#define ADC_CDR_DATA2 0xFFFF0000U /*!<2nd data of a pair of regular conversions */
+
+/******************************************************************************/
+/* */
+/* CRC calculation unit */
+/* */
+/******************************************************************************/
+/******************* Bit definition for CRC_DR register *********************/
+#define CRC_DR_DR 0xFFFFFFFFU /*!< Data register bits */
+
+
+/******************* Bit definition for CRC_IDR register ********************/
+#define CRC_IDR_IDR 0xFFU /*!< General-purpose 8-bit data register bits */
+
+
+/******************** Bit definition for CRC_CR register ********************/
+#define CRC_CR_RESET 0x01U /*!< RESET bit */
+
+/******************************************************************************/
+/* */
+/* Debug MCU */
+/* */
+/******************************************************************************/
+
+/******************************************************************************/
+/* */
+/* DMA Controller */
+/* */
+/******************************************************************************/
+/******************** Bits definition for DMA_SxCR register *****************/
+#define DMA_SxCR_CHSEL 0x0E000000U
+#define DMA_SxCR_CHSEL_0 0x02000000U
+#define DMA_SxCR_CHSEL_1 0x04000000U
+#define DMA_SxCR_CHSEL_2 0x08000000U
+#define DMA_SxCR_MBURST 0x01800000U
+#define DMA_SxCR_MBURST_0 0x00800000U
+#define DMA_SxCR_MBURST_1 0x01000000U
+#define DMA_SxCR_PBURST 0x00600000U
+#define DMA_SxCR_PBURST_0 0x00200000U
+#define DMA_SxCR_PBURST_1 0x00400000U
+#define DMA_SxCR_CT 0x00080000U
+#define DMA_SxCR_DBM 0x00040000U
+#define DMA_SxCR_PL 0x00030000U
+#define DMA_SxCR_PL_0 0x00010000U
+#define DMA_SxCR_PL_1 0x00020000U
+#define DMA_SxCR_PINCOS 0x00008000U
+#define DMA_SxCR_MSIZE 0x00006000U
+#define DMA_SxCR_MSIZE_0 0x00002000U
+#define DMA_SxCR_MSIZE_1 0x00004000U
+#define DMA_SxCR_PSIZE 0x00001800U
+#define DMA_SxCR_PSIZE_0 0x00000800U
+#define DMA_SxCR_PSIZE_1 0x00001000U
+#define DMA_SxCR_MINC 0x00000400U
+#define DMA_SxCR_PINC 0x00000200U
+#define DMA_SxCR_CIRC 0x00000100U
+#define DMA_SxCR_DIR 0x000000C0U
+#define DMA_SxCR_DIR_0 0x00000040U
+#define DMA_SxCR_DIR_1 0x00000080U
+#define DMA_SxCR_PFCTRL 0x00000020U
+#define DMA_SxCR_TCIE 0x00000010U
+#define DMA_SxCR_HTIE 0x00000008U
+#define DMA_SxCR_TEIE 0x00000004U
+#define DMA_SxCR_DMEIE 0x00000002U
+#define DMA_SxCR_EN 0x00000001U
+
+/* Legacy defines */
+#define DMA_SxCR_ACK 0x00100000U
+
+/******************** Bits definition for DMA_SxCNDTR register **************/
+#define DMA_SxNDT 0x0000FFFFU
+#define DMA_SxNDT_0 0x00000001U
+#define DMA_SxNDT_1 0x00000002U
+#define DMA_SxNDT_2 0x00000004U
+#define DMA_SxNDT_3 0x00000008U
+#define DMA_SxNDT_4 0x00000010U
+#define DMA_SxNDT_5 0x00000020U
+#define DMA_SxNDT_6 0x00000040U
+#define DMA_SxNDT_7 0x00000080U
+#define DMA_SxNDT_8 0x00000100U
+#define DMA_SxNDT_9 0x00000200U
+#define DMA_SxNDT_10 0x00000400U
+#define DMA_SxNDT_11 0x00000800U
+#define DMA_SxNDT_12 0x00001000U
+#define DMA_SxNDT_13 0x00002000U
+#define DMA_SxNDT_14 0x00004000U
+#define DMA_SxNDT_15 0x00008000U
+
+/******************** Bits definition for DMA_SxFCR register ****************/
+#define DMA_SxFCR_FEIE 0x00000080U
+#define DMA_SxFCR_FS 0x00000038U
+#define DMA_SxFCR_FS_0 0x00000008U
+#define DMA_SxFCR_FS_1 0x00000010U
+#define DMA_SxFCR_FS_2 0x00000020U
+#define DMA_SxFCR_DMDIS 0x00000004U
+#define DMA_SxFCR_FTH 0x00000003U
+#define DMA_SxFCR_FTH_0 0x00000001U
+#define DMA_SxFCR_FTH_1 0x00000002U
+
+/******************** Bits definition for DMA_LISR register *****************/
+#define DMA_LISR_TCIF3 0x08000000U
+#define DMA_LISR_HTIF3 0x04000000U
+#define DMA_LISR_TEIF3 0x02000000U
+#define DMA_LISR_DMEIF3 0x01000000U
+#define DMA_LISR_FEIF3 0x00400000U
+#define DMA_LISR_TCIF2 0x00200000U
+#define DMA_LISR_HTIF2 0x00100000U
+#define DMA_LISR_TEIF2 0x00080000U
+#define DMA_LISR_DMEIF2 0x00040000U
+#define DMA_LISR_FEIF2 0x00010000U
+#define DMA_LISR_TCIF1 0x00000800U
+#define DMA_LISR_HTIF1 0x00000400U
+#define DMA_LISR_TEIF1 0x00000200U
+#define DMA_LISR_DMEIF1 0x00000100U
+#define DMA_LISR_FEIF1 0x00000040U
+#define DMA_LISR_TCIF0 0x00000020U
+#define DMA_LISR_HTIF0 0x00000010U
+#define DMA_LISR_TEIF0 0x00000008U
+#define DMA_LISR_DMEIF0 0x00000004U
+#define DMA_LISR_FEIF0 0x00000001U
+
+/******************** Bits definition for DMA_HISR register *****************/
+#define DMA_HISR_TCIF7 0x08000000U
+#define DMA_HISR_HTIF7 0x04000000U
+#define DMA_HISR_TEIF7 0x02000000U
+#define DMA_HISR_DMEIF7 0x01000000U
+#define DMA_HISR_FEIF7 0x00400000U
+#define DMA_HISR_TCIF6 0x00200000U
+#define DMA_HISR_HTIF6 0x00100000U
+#define DMA_HISR_TEIF6 0x00080000U
+#define DMA_HISR_DMEIF6 0x00040000U
+#define DMA_HISR_FEIF6 0x00010000U
+#define DMA_HISR_TCIF5 0x00000800U
+#define DMA_HISR_HTIF5 0x00000400U
+#define DMA_HISR_TEIF5 0x00000200U
+#define DMA_HISR_DMEIF5 0x00000100U
+#define DMA_HISR_FEIF5 0x00000040U
+#define DMA_HISR_TCIF4 0x00000020U
+#define DMA_HISR_HTIF4 0x00000010U
+#define DMA_HISR_TEIF4 0x00000008U
+#define DMA_HISR_DMEIF4 0x00000004U
+#define DMA_HISR_FEIF4 0x00000001U
+
+/******************** Bits definition for DMA_LIFCR register ****************/
+#define DMA_LIFCR_CTCIF3 0x08000000U
+#define DMA_LIFCR_CHTIF3 0x04000000U
+#define DMA_LIFCR_CTEIF3 0x02000000U
+#define DMA_LIFCR_CDMEIF3 0x01000000U
+#define DMA_LIFCR_CFEIF3 0x00400000U
+#define DMA_LIFCR_CTCIF2 0x00200000U
+#define DMA_LIFCR_CHTIF2 0x00100000U
+#define DMA_LIFCR_CTEIF2 0x00080000U
+#define DMA_LIFCR_CDMEIF2 0x00040000U
+#define DMA_LIFCR_CFEIF2 0x00010000U
+#define DMA_LIFCR_CTCIF1 0x00000800U
+#define DMA_LIFCR_CHTIF1 0x00000400U
+#define DMA_LIFCR_CTEIF1 0x00000200U
+#define DMA_LIFCR_CDMEIF1 0x00000100U
+#define DMA_LIFCR_CFEIF1 0x00000040U
+#define DMA_LIFCR_CTCIF0 0x00000020U
+#define DMA_LIFCR_CHTIF0 0x00000010U
+#define DMA_LIFCR_CTEIF0 0x00000008U
+#define DMA_LIFCR_CDMEIF0 0x00000004U
+#define DMA_LIFCR_CFEIF0 0x00000001U
+
+/******************** Bits definition for DMA_HIFCR register ****************/
+#define DMA_HIFCR_CTCIF7 0x08000000U
+#define DMA_HIFCR_CHTIF7 0x04000000U
+#define DMA_HIFCR_CTEIF7 0x02000000U
+#define DMA_HIFCR_CDMEIF7 0x01000000U
+#define DMA_HIFCR_CFEIF7 0x00400000U
+#define DMA_HIFCR_CTCIF6 0x00200000U
+#define DMA_HIFCR_CHTIF6 0x00100000U
+#define DMA_HIFCR_CTEIF6 0x00080000U
+#define DMA_HIFCR_CDMEIF6 0x00040000U
+#define DMA_HIFCR_CFEIF6 0x00010000U
+#define DMA_HIFCR_CTCIF5 0x00000800U
+#define DMA_HIFCR_CHTIF5 0x00000400U
+#define DMA_HIFCR_CTEIF5 0x00000200U
+#define DMA_HIFCR_CDMEIF5 0x00000100U
+#define DMA_HIFCR_CFEIF5 0x00000040U
+#define DMA_HIFCR_CTCIF4 0x00000020U
+#define DMA_HIFCR_CHTIF4 0x00000010U
+#define DMA_HIFCR_CTEIF4 0x00000008U
+#define DMA_HIFCR_CDMEIF4 0x00000004U
+#define DMA_HIFCR_CFEIF4 0x00000001U
+
+
+/******************************************************************************/
+/* */
+/* External Interrupt/Event Controller */
+/* */
+/******************************************************************************/
+/******************* Bit definition for EXTI_IMR register *******************/
+#define EXTI_IMR_MR0 0x00000001U /*!< Interrupt Mask on line 0 */
+#define EXTI_IMR_MR1 0x00000002U /*!< Interrupt Mask on line 1 */
+#define EXTI_IMR_MR2 0x00000004U /*!< Interrupt Mask on line 2 */
+#define EXTI_IMR_MR3 0x00000008U /*!< Interrupt Mask on line 3 */
+#define EXTI_IMR_MR4 0x00000010U /*!< Interrupt Mask on line 4 */
+#define EXTI_IMR_MR5 0x00000020U /*!< Interrupt Mask on line 5 */
+#define EXTI_IMR_MR6 0x00000040U /*!< Interrupt Mask on line 6 */
+#define EXTI_IMR_MR7 0x00000080U /*!< Interrupt Mask on line 7 */
+#define EXTI_IMR_MR8 0x00000100U /*!< Interrupt Mask on line 8 */
+#define EXTI_IMR_MR9 0x00000200U /*!< Interrupt Mask on line 9 */
+#define EXTI_IMR_MR10 0x00000400U /*!< Interrupt Mask on line 10 */
+#define EXTI_IMR_MR11 0x00000800U /*!< Interrupt Mask on line 11 */
+#define EXTI_IMR_MR12 0x00001000U /*!< Interrupt Mask on line 12 */
+#define EXTI_IMR_MR13 0x00002000U /*!< Interrupt Mask on line 13 */
+#define EXTI_IMR_MR14 0x00004000U /*!< Interrupt Mask on line 14 */
+#define EXTI_IMR_MR15 0x00008000U /*!< Interrupt Mask on line 15 */
+#define EXTI_IMR_MR16 0x00010000U /*!< Interrupt Mask on line 16 */
+#define EXTI_IMR_MR17 0x00020000U /*!< Interrupt Mask on line 17 */
+#define EXTI_IMR_MR18 0x00040000U /*!< Interrupt Mask on line 18 */
+#define EXTI_IMR_MR19 0x00080000U /*!< Interrupt Mask on line 19 */
+#define EXTI_IMR_MR20 0x00100000U /*!< Interrupt Mask on line 20 */
+#define EXTI_IMR_MR21 0x00200000U /*!< Interrupt Mask on line 21 */
+#define EXTI_IMR_MR22 0x00400000U /*!< Interrupt Mask on line 22 */
+
+/******************* Bit definition for EXTI_EMR register *******************/
+#define EXTI_EMR_MR0 0x00000001U /*!< Event Mask on line 0 */
+#define EXTI_EMR_MR1 0x00000002U /*!< Event Mask on line 1 */
+#define EXTI_EMR_MR2 0x00000004U /*!< Event Mask on line 2 */
+#define EXTI_EMR_MR3 0x00000008U /*!< Event Mask on line 3 */
+#define EXTI_EMR_MR4 0x00000010U /*!< Event Mask on line 4 */
+#define EXTI_EMR_MR5 0x00000020U /*!< Event Mask on line 5 */
+#define EXTI_EMR_MR6 0x00000040U /*!< Event Mask on line 6 */
+#define EXTI_EMR_MR7 0x00000080U /*!< Event Mask on line 7 */
+#define EXTI_EMR_MR8 0x00000100U /*!< Event Mask on line 8 */
+#define EXTI_EMR_MR9 0x00000200U /*!< Event Mask on line 9 */
+#define EXTI_EMR_MR10 0x00000400U /*!< Event Mask on line 10 */
+#define EXTI_EMR_MR11 0x00000800U /*!< Event Mask on line 11 */
+#define EXTI_EMR_MR12 0x00001000U /*!< Event Mask on line 12 */
+#define EXTI_EMR_MR13 0x00002000U /*!< Event Mask on line 13 */
+#define EXTI_EMR_MR14 0x00004000U /*!< Event Mask on line 14 */
+#define EXTI_EMR_MR15 0x00008000U /*!< Event Mask on line 15 */
+#define EXTI_EMR_MR16 0x00010000U /*!< Event Mask on line 16 */
+#define EXTI_EMR_MR17 0x00020000U /*!< Event Mask on line 17 */
+#define EXTI_EMR_MR18 0x00040000U /*!< Event Mask on line 18 */
+#define EXTI_EMR_MR19 0x00080000U /*!< Event Mask on line 19 */
+#define EXTI_EMR_MR20 0x00100000U /*!< Event Mask on line 20 */
+#define EXTI_EMR_MR21 0x00200000U /*!< Event Mask on line 21 */
+#define EXTI_EMR_MR22 0x00400000U /*!< Event Mask on line 22 */
+
+/****************** Bit definition for EXTI_RTSR register *******************/
+#define EXTI_RTSR_TR0 0x00000001U /*!< Rising trigger event configuration bit of line 0 */
+#define EXTI_RTSR_TR1 0x00000002U /*!< Rising trigger event configuration bit of line 1 */
+#define EXTI_RTSR_TR2 0x00000004U /*!< Rising trigger event configuration bit of line 2 */
+#define EXTI_RTSR_TR3 0x00000008U /*!< Rising trigger event configuration bit of line 3 */
+#define EXTI_RTSR_TR4 0x00000010U /*!< Rising trigger event configuration bit of line 4 */
+#define EXTI_RTSR_TR5 0x00000020U /*!< Rising trigger event configuration bit of line 5 */
+#define EXTI_RTSR_TR6 0x00000040U /*!< Rising trigger event configuration bit of line 6 */
+#define EXTI_RTSR_TR7 0x00000080U /*!< Rising trigger event configuration bit of line 7 */
+#define EXTI_RTSR_TR8 0x00000100U /*!< Rising trigger event configuration bit of line 8 */
+#define EXTI_RTSR_TR9 0x00000200U /*!< Rising trigger event configuration bit of line 9 */
+#define EXTI_RTSR_TR10 0x00000400U /*!< Rising trigger event configuration bit of line 10 */
+#define EXTI_RTSR_TR11 0x00000800U /*!< Rising trigger event configuration bit of line 11 */
+#define EXTI_RTSR_TR12 0x00001000U /*!< Rising trigger event configuration bit of line 12 */
+#define EXTI_RTSR_TR13 0x00002000U /*!< Rising trigger event configuration bit of line 13 */
+#define EXTI_RTSR_TR14 0x00004000U /*!< Rising trigger event configuration bit of line 14 */
+#define EXTI_RTSR_TR15 0x00008000U /*!< Rising trigger event configuration bit of line 15 */
+#define EXTI_RTSR_TR16 0x00010000U /*!< Rising trigger event configuration bit of line 16 */
+#define EXTI_RTSR_TR17 0x00020000U /*!< Rising trigger event configuration bit of line 17 */
+#define EXTI_RTSR_TR18 0x00040000U /*!< Rising trigger event configuration bit of line 18 */
+#define EXTI_RTSR_TR19 0x00080000U /*!< Rising trigger event configuration bit of line 19 */
+#define EXTI_RTSR_TR20 0x00100000U /*!< Rising trigger event configuration bit of line 20 */
+#define EXTI_RTSR_TR21 0x00200000U /*!< Rising trigger event configuration bit of line 21 */
+#define EXTI_RTSR_TR22 0x00400000U /*!< Rising trigger event configuration bit of line 22 */
+
+/****************** Bit definition for EXTI_FTSR register *******************/
+#define EXTI_FTSR_TR0 0x00000001U /*!< Falling trigger event configuration bit of line 0 */
+#define EXTI_FTSR_TR1 0x00000002U /*!< Falling trigger event configuration bit of line 1 */
+#define EXTI_FTSR_TR2 0x00000004U /*!< Falling trigger event configuration bit of line 2 */
+#define EXTI_FTSR_TR3 0x00000008U /*!< Falling trigger event configuration bit of line 3 */
+#define EXTI_FTSR_TR4 0x00000010U /*!< Falling trigger event configuration bit of line 4 */
+#define EXTI_FTSR_TR5 0x00000020U /*!< Falling trigger event configuration bit of line 5 */
+#define EXTI_FTSR_TR6 0x00000040U /*!< Falling trigger event configuration bit of line 6 */
+#define EXTI_FTSR_TR7 0x00000080U /*!< Falling trigger event configuration bit of line 7 */
+#define EXTI_FTSR_TR8 0x00000100U /*!< Falling trigger event configuration bit of line 8 */
+#define EXTI_FTSR_TR9 0x00000200U /*!< Falling trigger event configuration bit of line 9 */
+#define EXTI_FTSR_TR10 0x00000400U /*!< Falling trigger event configuration bit of line 10 */
+#define EXTI_FTSR_TR11 0x00000800U /*!< Falling trigger event configuration bit of line 11 */
+#define EXTI_FTSR_TR12 0x00001000U /*!< Falling trigger event configuration bit of line 12 */
+#define EXTI_FTSR_TR13 0x00002000U /*!< Falling trigger event configuration bit of line 13 */
+#define EXTI_FTSR_TR14 0x00004000U /*!< Falling trigger event configuration bit of line 14 */
+#define EXTI_FTSR_TR15 0x00008000U /*!< Falling trigger event configuration bit of line 15 */
+#define EXTI_FTSR_TR16 0x00010000U /*!< Falling trigger event configuration bit of line 16 */
+#define EXTI_FTSR_TR17 0x00020000U /*!< Falling trigger event configuration bit of line 17 */
+#define EXTI_FTSR_TR18 0x00040000U /*!< Falling trigger event configuration bit of line 18 */
+#define EXTI_FTSR_TR19 0x00080000U /*!< Falling trigger event configuration bit of line 19 */
+#define EXTI_FTSR_TR20 0x00100000U /*!< Falling trigger event configuration bit of line 20 */
+#define EXTI_FTSR_TR21 0x00200000U /*!< Falling trigger event configuration bit of line 21 */
+#define EXTI_FTSR_TR22 0x00400000U /*!< Falling trigger event configuration bit of line 22 */
+
+/****************** Bit definition for EXTI_SWIER register ******************/
+#define EXTI_SWIER_SWIER0 0x00000001U /*!< Software Interrupt on line 0 */
+#define EXTI_SWIER_SWIER1 0x00000002U /*!< Software Interrupt on line 1 */
+#define EXTI_SWIER_SWIER2 0x00000004U /*!< Software Interrupt on line 2 */
+#define EXTI_SWIER_SWIER3 0x00000008U /*!< Software Interrupt on line 3 */
+#define EXTI_SWIER_SWIER4 0x00000010U /*!< Software Interrupt on line 4 */
+#define EXTI_SWIER_SWIER5 0x00000020U /*!< Software Interrupt on line 5 */
+#define EXTI_SWIER_SWIER6 0x00000040U /*!< Software Interrupt on line 6 */
+#define EXTI_SWIER_SWIER7 0x00000080U /*!< Software Interrupt on line 7 */
+#define EXTI_SWIER_SWIER8 0x00000100U /*!< Software Interrupt on line 8 */
+#define EXTI_SWIER_SWIER9 0x00000200U /*!< Software Interrupt on line 9 */
+#define EXTI_SWIER_SWIER10 0x00000400U /*!< Software Interrupt on line 10 */
+#define EXTI_SWIER_SWIER11 0x00000800U /*!< Software Interrupt on line 11 */
+#define EXTI_SWIER_SWIER12 0x00001000U /*!< Software Interrupt on line 12 */
+#define EXTI_SWIER_SWIER13 0x00002000U /*!< Software Interrupt on line 13 */
+#define EXTI_SWIER_SWIER14 0x00004000U /*!< Software Interrupt on line 14 */
+#define EXTI_SWIER_SWIER15 0x00008000U /*!< Software Interrupt on line 15 */
+#define EXTI_SWIER_SWIER16 0x00010000U /*!< Software Interrupt on line 16 */
+#define EXTI_SWIER_SWIER17 0x00020000U /*!< Software Interrupt on line 17 */
+#define EXTI_SWIER_SWIER18 0x00040000U /*!< Software Interrupt on line 18 */
+#define EXTI_SWIER_SWIER19 0x00080000U /*!< Software Interrupt on line 19 */
+#define EXTI_SWIER_SWIER20 0x00100000U /*!< Software Interrupt on line 20 */
+#define EXTI_SWIER_SWIER21 0x00200000U /*!< Software Interrupt on line 21 */
+#define EXTI_SWIER_SWIER22 0x00400000U /*!< Software Interrupt on line 22 */
+
+/******************* Bit definition for EXTI_PR register ********************/
+#define EXTI_PR_PR0 0x00000001U /*!< Pending bit for line 0 */
+#define EXTI_PR_PR1 0x00000002U /*!< Pending bit for line 1 */
+#define EXTI_PR_PR2 0x00000004U /*!< Pending bit for line 2 */
+#define EXTI_PR_PR3 0x00000008U /*!< Pending bit for line 3 */
+#define EXTI_PR_PR4 0x00000010U /*!< Pending bit for line 4 */
+#define EXTI_PR_PR5 0x00000020U /*!< Pending bit for line 5 */
+#define EXTI_PR_PR6 0x00000040U /*!< Pending bit for line 6 */
+#define EXTI_PR_PR7 0x00000080U /*!< Pending bit for line 7 */
+#define EXTI_PR_PR8 0x00000100U /*!< Pending bit for line 8 */
+#define EXTI_PR_PR9 0x00000200U /*!< Pending bit for line 9 */
+#define EXTI_PR_PR10 0x00000400U /*!< Pending bit for line 10 */
+#define EXTI_PR_PR11 0x00000800U /*!< Pending bit for line 11 */
+#define EXTI_PR_PR12 0x00001000U /*!< Pending bit for line 12 */
+#define EXTI_PR_PR13 0x00002000U /*!< Pending bit for line 13 */
+#define EXTI_PR_PR14 0x00004000U /*!< Pending bit for line 14 */
+#define EXTI_PR_PR15 0x00008000U /*!< Pending bit for line 15 */
+#define EXTI_PR_PR16 0x00010000U /*!< Pending bit for line 16 */
+#define EXTI_PR_PR17 0x00020000U /*!< Pending bit for line 17 */
+#define EXTI_PR_PR18 0x00040000U /*!< Pending bit for line 18 */
+#define EXTI_PR_PR19 0x00080000U /*!< Pending bit for line 19 */
+#define EXTI_PR_PR20 0x00100000U /*!< Pending bit for line 20 */
+#define EXTI_PR_PR21 0x00200000U /*!< Pending bit for line 21 */
+#define EXTI_PR_PR22 0x00400000U /*!< Pending bit for line 22 */
+
+/******************************************************************************/
+/* */
+/* FLASH */
+/* */
+/******************************************************************************/
+/******************* Bits definition for FLASH_ACR register *****************/
+#define FLASH_ACR_LATENCY 0x0000000FU
+#define FLASH_ACR_LATENCY_0WS 0x00000000U
+#define FLASH_ACR_LATENCY_1WS 0x00000001U
+#define FLASH_ACR_LATENCY_2WS 0x00000002U
+#define FLASH_ACR_LATENCY_3WS 0x00000003U
+#define FLASH_ACR_LATENCY_4WS 0x00000004U
+#define FLASH_ACR_LATENCY_5WS 0x00000005U
+#define FLASH_ACR_LATENCY_6WS 0x00000006U
+#define FLASH_ACR_LATENCY_7WS 0x00000007U
+
+#define FLASH_ACR_PRFTEN 0x00000100U
+#define FLASH_ACR_ICEN 0x00000200U
+#define FLASH_ACR_DCEN 0x00000400U
+#define FLASH_ACR_ICRST 0x00000800U
+#define FLASH_ACR_DCRST 0x00001000U
+#define FLASH_ACR_BYTE0_ADDRESS 0x40023C00U
+#define FLASH_ACR_BYTE2_ADDRESS 0x40023C03U
+
+/******************* Bits definition for FLASH_SR register ******************/
+#define FLASH_SR_EOP 0x00000001U
+#define FLASH_SR_SOP 0x00000002U
+#define FLASH_SR_WRPERR 0x00000010U
+#define FLASH_SR_PGAERR 0x00000020U
+#define FLASH_SR_PGPERR 0x00000040U
+#define FLASH_SR_PGSERR 0x00000080U
+#define FLASH_SR_BSY 0x00010000U
+
+/******************* Bits definition for FLASH_CR register ******************/
+#define FLASH_CR_PG 0x00000001U
+#define FLASH_CR_SER 0x00000002U
+#define FLASH_CR_MER 0x00000004U
+#define FLASH_CR_SNB 0x000000F8U
+#define FLASH_CR_SNB_0 0x00000008U
+#define FLASH_CR_SNB_1 0x00000010U
+#define FLASH_CR_SNB_2 0x00000020U
+#define FLASH_CR_SNB_3 0x00000040U
+#define FLASH_CR_SNB_4 0x00000080U
+#define FLASH_CR_PSIZE 0x00000300U
+#define FLASH_CR_PSIZE_0 0x00000100U
+#define FLASH_CR_PSIZE_1 0x00000200U
+#define FLASH_CR_STRT 0x00010000U
+#define FLASH_CR_EOPIE 0x01000000U
+#define FLASH_CR_LOCK 0x80000000U
+
+/******************* Bits definition for FLASH_OPTCR register ***************/
+#define FLASH_OPTCR_OPTLOCK 0x00000001U
+#define FLASH_OPTCR_OPTSTRT 0x00000002U
+#define FLASH_OPTCR_BOR_LEV_0 0x00000004U
+#define FLASH_OPTCR_BOR_LEV_1 0x00000008U
+#define FLASH_OPTCR_BOR_LEV 0x0000000CU
+
+#define FLASH_OPTCR_WDG_SW 0x00000020U
+#define FLASH_OPTCR_nRST_STOP 0x00000040U
+#define FLASH_OPTCR_nRST_STDBY 0x00000080U
+#define FLASH_OPTCR_RDP 0x0000FF00U
+#define FLASH_OPTCR_RDP_0 0x00000100U
+#define FLASH_OPTCR_RDP_1 0x00000200U
+#define FLASH_OPTCR_RDP_2 0x00000400U
+#define FLASH_OPTCR_RDP_3 0x00000800U
+#define FLASH_OPTCR_RDP_4 0x00001000U
+#define FLASH_OPTCR_RDP_5 0x00002000U
+#define FLASH_OPTCR_RDP_6 0x00004000U
+#define FLASH_OPTCR_RDP_7 0x00008000U
+#define FLASH_OPTCR_nWRP 0x0FFF0000U
+#define FLASH_OPTCR_nWRP_0 0x00010000U
+#define FLASH_OPTCR_nWRP_1 0x00020000U
+#define FLASH_OPTCR_nWRP_2 0x00040000U
+#define FLASH_OPTCR_nWRP_3 0x00080000U
+#define FLASH_OPTCR_nWRP_4 0x00100000U
+#define FLASH_OPTCR_nWRP_5 0x00200000U
+#define FLASH_OPTCR_nWRP_6 0x00400000U
+#define FLASH_OPTCR_nWRP_7 0x00800000U
+#define FLASH_OPTCR_nWRP_8 0x01000000U
+#define FLASH_OPTCR_nWRP_9 0x02000000U
+#define FLASH_OPTCR_nWRP_10 0x04000000U
+#define FLASH_OPTCR_nWRP_11 0x08000000U
+
+/****************** Bits definition for FLASH_OPTCR1 register ***************/
+#define FLASH_OPTCR1_nWRP 0x0FFF0000U
+#define FLASH_OPTCR1_nWRP_0 0x00010000U
+#define FLASH_OPTCR1_nWRP_1 0x00020000U
+#define FLASH_OPTCR1_nWRP_2 0x00040000U
+#define FLASH_OPTCR1_nWRP_3 0x00080000U
+#define FLASH_OPTCR1_nWRP_4 0x00100000U
+#define FLASH_OPTCR1_nWRP_5 0x00200000U
+#define FLASH_OPTCR1_nWRP_6 0x00400000U
+#define FLASH_OPTCR1_nWRP_7 0x00800000U
+#define FLASH_OPTCR1_nWRP_8 0x01000000U
+#define FLASH_OPTCR1_nWRP_9 0x02000000U
+#define FLASH_OPTCR1_nWRP_10 0x04000000U
+#define FLASH_OPTCR1_nWRP_11 0x08000000U
+
+/******************************************************************************/
+/* */
+/* General Purpose I/O */
+/* */
+/******************************************************************************/
+/****************** Bits definition for GPIO_MODER register *****************/
+#define GPIO_MODER_MODER0 0x00000003U
+#define GPIO_MODER_MODER0_0 0x00000001U
+#define GPIO_MODER_MODER0_1 0x00000002U
+
+#define GPIO_MODER_MODER1 0x0000000CU
+#define GPIO_MODER_MODER1_0 0x00000004U
+#define GPIO_MODER_MODER1_1 0x00000008U
+
+#define GPIO_MODER_MODER2 0x00000030U
+#define GPIO_MODER_MODER2_0 0x00000010U
+#define GPIO_MODER_MODER2_1 0x00000020U
+
+#define GPIO_MODER_MODER3 0x000000C0U
+#define GPIO_MODER_MODER3_0 0x00000040U
+#define GPIO_MODER_MODER3_1 0x00000080U
+
+#define GPIO_MODER_MODER4 0x00000300U
+#define GPIO_MODER_MODER4_0 0x00000100U
+#define GPIO_MODER_MODER4_1 0x00000200U
+
+#define GPIO_MODER_MODER5 0x00000C00U
+#define GPIO_MODER_MODER5_0 0x00000400U
+#define GPIO_MODER_MODER5_1 0x00000800U
+
+#define GPIO_MODER_MODER6 0x00003000U
+#define GPIO_MODER_MODER6_0 0x00001000U
+#define GPIO_MODER_MODER6_1 0x00002000U
+
+#define GPIO_MODER_MODER7 0x0000C000U
+#define GPIO_MODER_MODER7_0 0x00004000U
+#define GPIO_MODER_MODER7_1 0x00008000U
+
+#define GPIO_MODER_MODER8 0x00030000U
+#define GPIO_MODER_MODER8_0 0x00010000U
+#define GPIO_MODER_MODER8_1 0x00020000U
+
+#define GPIO_MODER_MODER9 0x000C0000U
+#define GPIO_MODER_MODER9_0 0x00040000U
+#define GPIO_MODER_MODER9_1 0x00080000U
+
+#define GPIO_MODER_MODER10 0x00300000U
+#define GPIO_MODER_MODER10_0 0x00100000U
+#define GPIO_MODER_MODER10_1 0x00200000U
+
+#define GPIO_MODER_MODER11 0x00C00000U
+#define GPIO_MODER_MODER11_0 0x00400000U
+#define GPIO_MODER_MODER11_1 0x00800000U
+
+#define GPIO_MODER_MODER12 0x03000000U
+#define GPIO_MODER_MODER12_0 0x01000000U
+#define GPIO_MODER_MODER12_1 0x02000000U
+
+#define GPIO_MODER_MODER13 0x0C000000U
+#define GPIO_MODER_MODER13_0 0x04000000U
+#define GPIO_MODER_MODER13_1 0x08000000U
+
+#define GPIO_MODER_MODER14 0x30000000U
+#define GPIO_MODER_MODER14_0 0x10000000U
+#define GPIO_MODER_MODER14_1 0x20000000U
+
+#define GPIO_MODER_MODER15 0xC0000000U
+#define GPIO_MODER_MODER15_0 0x40000000U
+#define GPIO_MODER_MODER15_1 0x80000000U
+
+/****************** Bits definition for GPIO_OTYPER register ****************/
+#define GPIO_OTYPER_OT_0 0x00000001U
+#define GPIO_OTYPER_OT_1 0x00000002U
+#define GPIO_OTYPER_OT_2 0x00000004U
+#define GPIO_OTYPER_OT_3 0x00000008U
+#define GPIO_OTYPER_OT_4 0x00000010U
+#define GPIO_OTYPER_OT_5 0x00000020U
+#define GPIO_OTYPER_OT_6 0x00000040U
+#define GPIO_OTYPER_OT_7 0x00000080U
+#define GPIO_OTYPER_OT_8 0x00000100U
+#define GPIO_OTYPER_OT_9 0x00000200U
+#define GPIO_OTYPER_OT_10 0x00000400U
+#define GPIO_OTYPER_OT_11 0x00000800U
+#define GPIO_OTYPER_OT_12 0x00001000U
+#define GPIO_OTYPER_OT_13 0x00002000U
+#define GPIO_OTYPER_OT_14 0x00004000U
+#define GPIO_OTYPER_OT_15 0x00008000U
+
+/****************** Bits definition for GPIO_OSPEEDR register ***************/
+#define GPIO_OSPEEDER_OSPEEDR0 0x00000003U
+#define GPIO_OSPEEDER_OSPEEDR0_0 0x00000001U
+#define GPIO_OSPEEDER_OSPEEDR0_1 0x00000002U
+
+#define GPIO_OSPEEDER_OSPEEDR1 0x0000000CU
+#define GPIO_OSPEEDER_OSPEEDR1_0 0x00000004U
+#define GPIO_OSPEEDER_OSPEEDR1_1 0x00000008U
+
+#define GPIO_OSPEEDER_OSPEEDR2 0x00000030U
+#define GPIO_OSPEEDER_OSPEEDR2_0 0x00000010U
+#define GPIO_OSPEEDER_OSPEEDR2_1 0x00000020U
+
+#define GPIO_OSPEEDER_OSPEEDR3 0x000000C0U
+#define GPIO_OSPEEDER_OSPEEDR3_0 0x00000040U
+#define GPIO_OSPEEDER_OSPEEDR3_1 0x00000080U
+
+#define GPIO_OSPEEDER_OSPEEDR4 0x00000300U
+#define GPIO_OSPEEDER_OSPEEDR4_0 0x00000100U
+#define GPIO_OSPEEDER_OSPEEDR4_1 0x00000200U
+
+#define GPIO_OSPEEDER_OSPEEDR5 0x00000C00U
+#define GPIO_OSPEEDER_OSPEEDR5_0 0x00000400U
+#define GPIO_OSPEEDER_OSPEEDR5_1 0x00000800U
+
+#define GPIO_OSPEEDER_OSPEEDR6 0x00003000U
+#define GPIO_OSPEEDER_OSPEEDR6_0 0x00001000U
+#define GPIO_OSPEEDER_OSPEEDR6_1 0x00002000U
+
+#define GPIO_OSPEEDER_OSPEEDR7 0x0000C000U
+#define GPIO_OSPEEDER_OSPEEDR7_0 0x00004000U
+#define GPIO_OSPEEDER_OSPEEDR7_1 0x00008000U
+
+#define GPIO_OSPEEDER_OSPEEDR8 0x00030000U
+#define GPIO_OSPEEDER_OSPEEDR8_0 0x00010000U
+#define GPIO_OSPEEDER_OSPEEDR8_1 0x00020000U
+
+#define GPIO_OSPEEDER_OSPEEDR9 0x000C0000U
+#define GPIO_OSPEEDER_OSPEEDR9_0 0x00040000U
+#define GPIO_OSPEEDER_OSPEEDR9_1 0x00080000U
+
+#define GPIO_OSPEEDER_OSPEEDR10 0x00300000U
+#define GPIO_OSPEEDER_OSPEEDR10_0 0x00100000U
+#define GPIO_OSPEEDER_OSPEEDR10_1 0x00200000U
+
+#define GPIO_OSPEEDER_OSPEEDR11 0x00C00000U
+#define GPIO_OSPEEDER_OSPEEDR11_0 0x00400000U
+#define GPIO_OSPEEDER_OSPEEDR11_1 0x00800000U
+
+#define GPIO_OSPEEDER_OSPEEDR12 0x03000000U
+#define GPIO_OSPEEDER_OSPEEDR12_0 0x01000000U
+#define GPIO_OSPEEDER_OSPEEDR12_1 0x02000000U
+
+#define GPIO_OSPEEDER_OSPEEDR13 0x0C000000U
+#define GPIO_OSPEEDER_OSPEEDR13_0 0x04000000U
+#define GPIO_OSPEEDER_OSPEEDR13_1 0x08000000U
+
+#define GPIO_OSPEEDER_OSPEEDR14 0x30000000U
+#define GPIO_OSPEEDER_OSPEEDR14_0 0x10000000U
+#define GPIO_OSPEEDER_OSPEEDR14_1 0x20000000U
+
+#define GPIO_OSPEEDER_OSPEEDR15 0xC0000000U
+#define GPIO_OSPEEDER_OSPEEDR15_0 0x40000000U
+#define GPIO_OSPEEDER_OSPEEDR15_1 0x80000000U
+
+/****************** Bits definition for GPIO_PUPDR register *****************/
+#define GPIO_PUPDR_PUPDR0 0x00000003U
+#define GPIO_PUPDR_PUPDR0_0 0x00000001U
+#define GPIO_PUPDR_PUPDR0_1 0x00000002U
+
+#define GPIO_PUPDR_PUPDR1 0x0000000CU
+#define GPIO_PUPDR_PUPDR1_0 0x00000004U
+#define GPIO_PUPDR_PUPDR1_1 0x00000008U
+
+#define GPIO_PUPDR_PUPDR2 0x00000030U
+#define GPIO_PUPDR_PUPDR2_0 0x00000010U
+#define GPIO_PUPDR_PUPDR2_1 0x00000020U
+
+#define GPIO_PUPDR_PUPDR3 0x000000C0U
+#define GPIO_PUPDR_PUPDR3_0 0x00000040U
+#define GPIO_PUPDR_PUPDR3_1 0x00000080U
+
+#define GPIO_PUPDR_PUPDR4 0x00000300U
+#define GPIO_PUPDR_PUPDR4_0 0x00000100U
+#define GPIO_PUPDR_PUPDR4_1 0x00000200U
+
+#define GPIO_PUPDR_PUPDR5 0x00000C00U
+#define GPIO_PUPDR_PUPDR5_0 0x00000400U
+#define GPIO_PUPDR_PUPDR5_1 0x00000800U
+
+#define GPIO_PUPDR_PUPDR6 0x00003000U
+#define GPIO_PUPDR_PUPDR6_0 0x00001000U
+#define GPIO_PUPDR_PUPDR6_1 0x00002000U
+
+#define GPIO_PUPDR_PUPDR7 0x0000C000U
+#define GPIO_PUPDR_PUPDR7_0 0x00004000U
+#define GPIO_PUPDR_PUPDR7_1 0x00008000U
+
+#define GPIO_PUPDR_PUPDR8 0x00030000U
+#define GPIO_PUPDR_PUPDR8_0 0x00010000U
+#define GPIO_PUPDR_PUPDR8_1 0x00020000U
+
+#define GPIO_PUPDR_PUPDR9 0x000C0000U
+#define GPIO_PUPDR_PUPDR9_0 0x00040000U
+#define GPIO_PUPDR_PUPDR9_1 0x00080000U
+
+#define GPIO_PUPDR_PUPDR10 0x00300000U
+#define GPIO_PUPDR_PUPDR10_0 0x00100000U
+#define GPIO_PUPDR_PUPDR10_1 0x00200000U
+
+#define GPIO_PUPDR_PUPDR11 0x00C00000U
+#define GPIO_PUPDR_PUPDR11_0 0x00400000U
+#define GPIO_PUPDR_PUPDR11_1 0x00800000U
+
+#define GPIO_PUPDR_PUPDR12 0x03000000U
+#define GPIO_PUPDR_PUPDR12_0 0x01000000U
+#define GPIO_PUPDR_PUPDR12_1 0x02000000U
+
+#define GPIO_PUPDR_PUPDR13 0x0C000000U
+#define GPIO_PUPDR_PUPDR13_0 0x04000000U
+#define GPIO_PUPDR_PUPDR13_1 0x08000000U
+
+#define GPIO_PUPDR_PUPDR14 0x30000000U
+#define GPIO_PUPDR_PUPDR14_0 0x10000000U
+#define GPIO_PUPDR_PUPDR14_1 0x20000000U
+
+#define GPIO_PUPDR_PUPDR15 0xC0000000U
+#define GPIO_PUPDR_PUPDR15_0 0x40000000U
+#define GPIO_PUPDR_PUPDR15_1 0x80000000U
+
+/****************** Bits definition for GPIO_IDR register *******************/
+#define GPIO_IDR_IDR_0 0x00000001U
+#define GPIO_IDR_IDR_1 0x00000002U
+#define GPIO_IDR_IDR_2 0x00000004U
+#define GPIO_IDR_IDR_3 0x00000008U
+#define GPIO_IDR_IDR_4 0x00000010U
+#define GPIO_IDR_IDR_5 0x00000020U
+#define GPIO_IDR_IDR_6 0x00000040U
+#define GPIO_IDR_IDR_7 0x00000080U
+#define GPIO_IDR_IDR_8 0x00000100U
+#define GPIO_IDR_IDR_9 0x00000200U
+#define GPIO_IDR_IDR_10 0x00000400U
+#define GPIO_IDR_IDR_11 0x00000800U
+#define GPIO_IDR_IDR_12 0x00001000U
+#define GPIO_IDR_IDR_13 0x00002000U
+#define GPIO_IDR_IDR_14 0x00004000U
+#define GPIO_IDR_IDR_15 0x00008000U
+/* Old GPIO_IDR register bits definition, maintained for legacy purpose */
+#define GPIO_OTYPER_IDR_0 GPIO_IDR_IDR_0
+#define GPIO_OTYPER_IDR_1 GPIO_IDR_IDR_1
+#define GPIO_OTYPER_IDR_2 GPIO_IDR_IDR_2
+#define GPIO_OTYPER_IDR_3 GPIO_IDR_IDR_3
+#define GPIO_OTYPER_IDR_4 GPIO_IDR_IDR_4
+#define GPIO_OTYPER_IDR_5 GPIO_IDR_IDR_5
+#define GPIO_OTYPER_IDR_6 GPIO_IDR_IDR_6
+#define GPIO_OTYPER_IDR_7 GPIO_IDR_IDR_7
+#define GPIO_OTYPER_IDR_8 GPIO_IDR_IDR_8
+#define GPIO_OTYPER_IDR_9 GPIO_IDR_IDR_9
+#define GPIO_OTYPER_IDR_10 GPIO_IDR_IDR_10
+#define GPIO_OTYPER_IDR_11 GPIO_IDR_IDR_11
+#define GPIO_OTYPER_IDR_12 GPIO_IDR_IDR_12
+#define GPIO_OTYPER_IDR_13 GPIO_IDR_IDR_13
+#define GPIO_OTYPER_IDR_14 GPIO_IDR_IDR_14
+#define GPIO_OTYPER_IDR_15 GPIO_IDR_IDR_15
+
+/****************** Bits definition for GPIO_ODR register *******************/
+#define GPIO_ODR_ODR_0 0x00000001U
+#define GPIO_ODR_ODR_1 0x00000002U
+#define GPIO_ODR_ODR_2 0x00000004U
+#define GPIO_ODR_ODR_3 0x00000008U
+#define GPIO_ODR_ODR_4 0x00000010U
+#define GPIO_ODR_ODR_5 0x00000020U
+#define GPIO_ODR_ODR_6 0x00000040U
+#define GPIO_ODR_ODR_7 0x00000080U
+#define GPIO_ODR_ODR_8 0x00000100U
+#define GPIO_ODR_ODR_9 0x00000200U
+#define GPIO_ODR_ODR_10 0x00000400U
+#define GPIO_ODR_ODR_11 0x00000800U
+#define GPIO_ODR_ODR_12 0x00001000U
+#define GPIO_ODR_ODR_13 0x00002000U
+#define GPIO_ODR_ODR_14 0x00004000U
+#define GPIO_ODR_ODR_15 0x00008000U
+/* Old GPIO_ODR register bits definition, maintained for legacy purpose */
+#define GPIO_OTYPER_ODR_0 GPIO_ODR_ODR_0
+#define GPIO_OTYPER_ODR_1 GPIO_ODR_ODR_1
+#define GPIO_OTYPER_ODR_2 GPIO_ODR_ODR_2
+#define GPIO_OTYPER_ODR_3 GPIO_ODR_ODR_3
+#define GPIO_OTYPER_ODR_4 GPIO_ODR_ODR_4
+#define GPIO_OTYPER_ODR_5 GPIO_ODR_ODR_5
+#define GPIO_OTYPER_ODR_6 GPIO_ODR_ODR_6
+#define GPIO_OTYPER_ODR_7 GPIO_ODR_ODR_7
+#define GPIO_OTYPER_ODR_8 GPIO_ODR_ODR_8
+#define GPIO_OTYPER_ODR_9 GPIO_ODR_ODR_9
+#define GPIO_OTYPER_ODR_10 GPIO_ODR_ODR_10
+#define GPIO_OTYPER_ODR_11 GPIO_ODR_ODR_11
+#define GPIO_OTYPER_ODR_12 GPIO_ODR_ODR_12
+#define GPIO_OTYPER_ODR_13 GPIO_ODR_ODR_13
+#define GPIO_OTYPER_ODR_14 GPIO_ODR_ODR_14
+#define GPIO_OTYPER_ODR_15 GPIO_ODR_ODR_15
+
+/****************** Bits definition for GPIO_BSRR register ******************/
+#define GPIO_BSRR_BS_0 0x00000001U
+#define GPIO_BSRR_BS_1 0x00000002U
+#define GPIO_BSRR_BS_2 0x00000004U
+#define GPIO_BSRR_BS_3 0x00000008U
+#define GPIO_BSRR_BS_4 0x00000010U
+#define GPIO_BSRR_BS_5 0x00000020U
+#define GPIO_BSRR_BS_6 0x00000040U
+#define GPIO_BSRR_BS_7 0x00000080U
+#define GPIO_BSRR_BS_8 0x00000100U
+#define GPIO_BSRR_BS_9 0x00000200U
+#define GPIO_BSRR_BS_10 0x00000400U
+#define GPIO_BSRR_BS_11 0x00000800U
+#define GPIO_BSRR_BS_12 0x00001000U
+#define GPIO_BSRR_BS_13 0x00002000U
+#define GPIO_BSRR_BS_14 0x00004000U
+#define GPIO_BSRR_BS_15 0x00008000U
+#define GPIO_BSRR_BR_0 0x00010000U
+#define GPIO_BSRR_BR_1 0x00020000U
+#define GPIO_BSRR_BR_2 0x00040000U
+#define GPIO_BSRR_BR_3 0x00080000U
+#define GPIO_BSRR_BR_4 0x00100000U
+#define GPIO_BSRR_BR_5 0x00200000U
+#define GPIO_BSRR_BR_6 0x00400000U
+#define GPIO_BSRR_BR_7 0x00800000U
+#define GPIO_BSRR_BR_8 0x01000000U
+#define GPIO_BSRR_BR_9 0x02000000U
+#define GPIO_BSRR_BR_10 0x04000000U
+#define GPIO_BSRR_BR_11 0x08000000U
+#define GPIO_BSRR_BR_12 0x10000000U
+#define GPIO_BSRR_BR_13 0x20000000U
+#define GPIO_BSRR_BR_14 0x40000000U
+#define GPIO_BSRR_BR_15 0x80000000U
+
+/****************** Bit definition for GPIO_LCKR register *********************/
+#define GPIO_LCKR_LCK0 0x00000001U
+#define GPIO_LCKR_LCK1 0x00000002U
+#define GPIO_LCKR_LCK2 0x00000004U
+#define GPIO_LCKR_LCK3 0x00000008U
+#define GPIO_LCKR_LCK4 0x00000010U
+#define GPIO_LCKR_LCK5 0x00000020U
+#define GPIO_LCKR_LCK6 0x00000040U
+#define GPIO_LCKR_LCK7 0x00000080U
+#define GPIO_LCKR_LCK8 0x00000100U
+#define GPIO_LCKR_LCK9 0x00000200U
+#define GPIO_LCKR_LCK10 0x00000400U
+#define GPIO_LCKR_LCK11 0x00000800U
+#define GPIO_LCKR_LCK12 0x00001000U
+#define GPIO_LCKR_LCK13 0x00002000U
+#define GPIO_LCKR_LCK14 0x00004000U
+#define GPIO_LCKR_LCK15 0x00008000U
+#define GPIO_LCKR_LCKK 0x00010000U
+
+/******************************************************************************/
+/* */
+/* Inter-integrated Circuit Interface */
+/* */
+/******************************************************************************/
+/******************* Bit definition for I2C_CR1 register ********************/
+#define I2C_CR1_PE 0x00000001U /*!<Peripheral Enable */
+#define I2C_CR1_SMBUS 0x00000002U /*!<SMBus Mode */
+#define I2C_CR1_SMBTYPE 0x00000008U /*!<SMBus Type */
+#define I2C_CR1_ENARP 0x00000010U /*!<ARP Enable */
+#define I2C_CR1_ENPEC 0x00000020U /*!<PEC Enable */
+#define I2C_CR1_ENGC 0x00000040U /*!<General Call Enable */
+#define I2C_CR1_NOSTRETCH 0x00000080U /*!<Clock Stretching Disable (Slave mode) */
+#define I2C_CR1_START 0x00000100U /*!<Start Generation */
+#define I2C_CR1_STOP 0x00000200U /*!<Stop Generation */
+#define I2C_CR1_ACK 0x00000400U /*!<Acknowledge Enable */
+#define I2C_CR1_POS 0x00000800U /*!<Acknowledge/PEC Position (for data reception) */
+#define I2C_CR1_PEC 0x00001000U /*!<Packet Error Checking */
+#define I2C_CR1_ALERT 0x00002000U /*!<SMBus Alert */
+#define I2C_CR1_SWRST 0x00008000U /*!<Software Reset */
+
+/******************* Bit definition for I2C_CR2 register ********************/
+#define I2C_CR2_FREQ 0x0000003FU /*!<FREQ[5:0] bits (Peripheral Clock Frequency) */
+#define I2C_CR2_FREQ_0 0x00000001U /*!<Bit 0 */
+#define I2C_CR2_FREQ_1 0x00000002U /*!<Bit 1 */
+#define I2C_CR2_FREQ_2 0x00000004U /*!<Bit 2 */
+#define I2C_CR2_FREQ_3 0x00000008U /*!<Bit 3 */
+#define I2C_CR2_FREQ_4 0x00000010U /*!<Bit 4 */
+#define I2C_CR2_FREQ_5 0x00000020U /*!<Bit 5 */
+
+#define I2C_CR2_ITERREN 0x00000100U /*!<Error Interrupt Enable */
+#define I2C_CR2_ITEVTEN 0x00000200U /*!<Event Interrupt Enable */
+#define I2C_CR2_ITBUFEN 0x00000400U /*!<Buffer Interrupt Enable */
+#define I2C_CR2_DMAEN 0x00000800U /*!<DMA Requests Enable */
+#define I2C_CR2_LAST 0x00001000U /*!<DMA Last Transfer */
+
+/******************* Bit definition for I2C_OAR1 register *******************/
+#define I2C_OAR1_ADD1_7 0x000000FEU /*!<Interface Address */
+#define I2C_OAR1_ADD8_9 0x00000300U /*!<Interface Address */
+
+#define I2C_OAR1_ADD0 0x00000001U /*!<Bit 0 */
+#define I2C_OAR1_ADD1 0x00000002U /*!<Bit 1 */
+#define I2C_OAR1_ADD2 0x00000004U /*!<Bit 2 */
+#define I2C_OAR1_ADD3 0x00000008U /*!<Bit 3 */
+#define I2C_OAR1_ADD4 0x00000010U /*!<Bit 4 */
+#define I2C_OAR1_ADD5 0x00000020U /*!<Bit 5 */
+#define I2C_OAR1_ADD6 0x00000040U /*!<Bit 6 */
+#define I2C_OAR1_ADD7 0x00000080U /*!<Bit 7 */
+#define I2C_OAR1_ADD8 0x00000100U /*!<Bit 8 */
+#define I2C_OAR1_ADD9 0x00000200U /*!<Bit 9 */
+
+#define I2C_OAR1_ADDMODE 0x00008000U /*!<Addressing Mode (Slave mode) */
+
+/******************* Bit definition for I2C_OAR2 register *******************/
+#define I2C_OAR2_ENDUAL 0x00000001U /*!<Dual addressing mode enable */
+#define I2C_OAR2_ADD2 0x000000FEU /*!<Interface address */
+
+/******************** Bit definition for I2C_DR register ********************/
+#define I2C_DR_DR 0x000000FFU /*!<8-bit Data Register */
+
+/******************* Bit definition for I2C_SR1 register ********************/
+#define I2C_SR1_SB 0x00000001U /*!<Start Bit (Master mode) */
+#define I2C_SR1_ADDR 0x00000002U /*!<Address sent (master mode)/matched (slave mode) */
+#define I2C_SR1_BTF 0x00000004U /*!<Byte Transfer Finished */
+#define I2C_SR1_ADD10 0x00000008U /*!<10-bit header sent (Master mode) */
+#define I2C_SR1_STOPF 0x00000010U /*!<Stop detection (Slave mode) */
+#define I2C_SR1_RXNE 0x00000040U /*!<Data Register not Empty (receivers) */
+#define I2C_SR1_TXE 0x00000080U /*!<Data Register Empty (transmitters) */
+#define I2C_SR1_BERR 0x00000100U /*!<Bus Error */
+#define I2C_SR1_ARLO 0x00000200U /*!<Arbitration Lost (master mode) */
+#define I2C_SR1_AF 0x00000400U /*!<Acknowledge Failure */
+#define I2C_SR1_OVR 0x00000800U /*!<Overrun/Underrun */
+#define I2C_SR1_PECERR 0x00001000U /*!<PEC Error in reception */
+#define I2C_SR1_TIMEOUT 0x00004000U /*!<Timeout or Tlow Error */
+#define I2C_SR1_SMBALERT 0x00008000U /*!<SMBus Alert */
+
+/******************* Bit definition for I2C_SR2 register ********************/
+#define I2C_SR2_MSL 0x00000001U /*!<Master/Slave */
+#define I2C_SR2_BUSY 0x00000002U /*!<Bus Busy */
+#define I2C_SR2_TRA 0x00000004U /*!<Transmitter/Receiver */
+#define I2C_SR2_GENCALL 0x00000010U /*!<General Call Address (Slave mode) */
+#define I2C_SR2_SMBDEFAULT 0x00000020U /*!<SMBus Device Default Address (Slave mode) */
+#define I2C_SR2_SMBHOST 0x00000040U /*!<SMBus Host Header (Slave mode) */
+#define I2C_SR2_DUALF 0x00000080U /*!<Dual Flag (Slave mode) */
+#define I2C_SR2_PEC 0x0000FF00U /*!<Packet Error Checking Register */
+
+/******************* Bit definition for I2C_CCR register ********************/
+#define I2C_CCR_CCR 0x00000FFFU /*!<Clock Control Register in Fast/Standard mode (Master mode) */
+#define I2C_CCR_DUTY 0x00004000U /*!<Fast Mode Duty Cycle */
+#define I2C_CCR_FS 0x00008000U /*!<I2C Master Mode Selection */
+
+/****************** Bit definition for I2C_TRISE register *******************/
+#define I2C_TRISE_TRISE 0x0000003FU /*!<Maximum Rise Time in Fast/Standard mode (Master mode) */
+
+/****************** Bit definition for I2C_FLTR register *******************/
+#define I2C_FLTR_DNF 0x0000000FU /*!<Digital Noise Filter */
+#define I2C_FLTR_ANOFF 0x00000010U /*!<Analog Noise Filter OFF */
+
+/******************************************************************************/
+/* */
+/* Independent WATCHDOG */
+/* */
+/******************************************************************************/
+/******************* Bit definition for IWDG_KR register ********************/
+#define IWDG_KR_KEY 0xFFFFU /*!<Key value (write only, read 0000h) */
+
+/******************* Bit definition for IWDG_PR register ********************/
+#define IWDG_PR_PR 0x07U /*!<PR[2:0] (Prescaler divider) */
+#define IWDG_PR_PR_0 0x01U /*!<Bit 0 */
+#define IWDG_PR_PR_1 0x02U /*!<Bit 1 */
+#define IWDG_PR_PR_2 0x04U /*!<Bit 2 */
+
+/******************* Bit definition for IWDG_RLR register *******************/
+#define IWDG_RLR_RL 0x0FFFU /*!<Watchdog counter reload value */
+
+/******************* Bit definition for IWDG_SR register ********************/
+#define IWDG_SR_PVU 0x01U /*!<Watchdog prescaler value update */
+#define IWDG_SR_RVU 0x02U /*!<Watchdog counter reload value update */
+
+
+/******************************************************************************/
+/* */
+/* Power Control */
+/* */
+/******************************************************************************/
+/******************** Bit definition for PWR_CR register ********************/
+#define PWR_CR_LPDS 0x00000001U /*!< Low-Power Deepsleep */
+#define PWR_CR_PDDS 0x00000002U /*!< Power Down Deepsleep */
+#define PWR_CR_CWUF 0x00000004U /*!< Clear Wakeup Flag */
+#define PWR_CR_CSBF 0x00000008U /*!< Clear Standby Flag */
+#define PWR_CR_PVDE 0x00000010U /*!< Power Voltage Detector Enable */
+
+#define PWR_CR_PLS 0x000000E0U /*!< PLS[2:0] bits (PVD Level Selection) */
+#define PWR_CR_PLS_0 0x00000020U /*!< Bit 0 */
+#define PWR_CR_PLS_1 0x00000040U /*!< Bit 1 */
+#define PWR_CR_PLS_2 0x00000080U /*!< Bit 2 */
+
+/*!< PVD level configuration */
+#define PWR_CR_PLS_LEV0 0x00000000U /*!< PVD level 0 */
+#define PWR_CR_PLS_LEV1 0x00000020U /*!< PVD level 1 */
+#define PWR_CR_PLS_LEV2 0x00000040U /*!< PVD level 2 */
+#define PWR_CR_PLS_LEV3 0x00000060U /*!< PVD level 3 */
+#define PWR_CR_PLS_LEV4 0x00000080U /*!< PVD level 4 */
+#define PWR_CR_PLS_LEV5 0x000000A0U /*!< PVD level 5 */
+#define PWR_CR_PLS_LEV6 0x000000C0U /*!< PVD level 6 */
+#define PWR_CR_PLS_LEV7 0x000000E0U /*!< PVD level 7 */
+
+#define PWR_CR_DBP 0x00000100U /*!< Disable Backup Domain write protection */
+#define PWR_CR_FPDS 0x00000200U /*!< Flash power down in Stop mode */
+#define PWR_CR_LPLVDS 0x00000400U /*!< Low Power Regulator Low Voltage in Deep Sleep mode */
+#define PWR_CR_MRLVDS 0x00000800U /*!< Main Regulator Low Voltage in Deep Sleep mode */
+#define PWR_CR_ADCDC1 0x00002000U /*!< Refer to AN4073 on how to use this bit */
+
+#define PWR_CR_VOS 0x0000C000U /*!< VOS[1:0] bits (Regulator voltage scaling output selection) */
+#define PWR_CR_VOS_0 0x00004000U /*!< Bit 0 */
+#define PWR_CR_VOS_1 0x00008000U /*!< Bit 1 */
+
+#define PWR_CR_FMSSR 0x00100000U /*!< Flash Memory Sleep System Run */
+#define PWR_CR_FISSR 0x00200000U /*!< Flash Interface Stop while System Run */
+/* Legacy define */
+#define PWR_CR_PMODE PWR_CR_VOS
+
+/******************* Bit definition for PWR_CSR register ********************/
+#define PWR_CSR_WUF 0x00000001U /*!< Wakeup Flag */
+#define PWR_CSR_SBF 0x00000002U /*!< Standby Flag */
+#define PWR_CSR_PVDO 0x00000004U /*!< PVD Output */
+#define PWR_CSR_BRR 0x00000008U /*!< Backup regulator ready */
+#define PWR_CSR_EWUP 0x00000100U /*!< Enable WKUP pin */
+#define PWR_CSR_BRE 0x00000200U /*!< Backup regulator enable */
+#define PWR_CSR_VOSRDY 0x00004000U /*!< Regulator voltage scaling output selection ready */
+
+/* Legacy define */
+#define PWR_CSR_REGRDY PWR_CSR_VOSRDY
+
+/******************************************************************************/
+/* */
+/* Reset and Clock Control */
+/* */
+/******************************************************************************/
+/******************** Bit definition for RCC_CR register ********************/
+#define RCC_CR_HSION 0x00000001U
+#define RCC_CR_HSIRDY 0x00000002U
+
+#define RCC_CR_HSITRIM 0x000000F8U
+#define RCC_CR_HSITRIM_0 0x00000008U/*!<Bit 0 */
+#define RCC_CR_HSITRIM_1 0x00000010U/*!<Bit 1 */
+#define RCC_CR_HSITRIM_2 0x00000020U/*!<Bit 2 */
+#define RCC_CR_HSITRIM_3 0x00000040U/*!<Bit 3 */
+#define RCC_CR_HSITRIM_4 0x00000080U/*!<Bit 4 */
+
+#define RCC_CR_HSICAL 0x0000FF00U
+#define RCC_CR_HSICAL_0 0x00000100U/*!<Bit 0 */
+#define RCC_CR_HSICAL_1 0x00000200U/*!<Bit 1 */
+#define RCC_CR_HSICAL_2 0x00000400U/*!<Bit 2 */
+#define RCC_CR_HSICAL_3 0x00000800U/*!<Bit 3 */
+#define RCC_CR_HSICAL_4 0x00001000U/*!<Bit 4 */
+#define RCC_CR_HSICAL_5 0x00002000U/*!<Bit 5 */
+#define RCC_CR_HSICAL_6 0x00004000U/*!<Bit 6 */
+#define RCC_CR_HSICAL_7 0x00008000U/*!<Bit 7 */
+
+#define RCC_CR_HSEON 0x00010000U
+#define RCC_CR_HSERDY 0x00020000U
+#define RCC_CR_HSEBYP 0x00040000U
+#define RCC_CR_CSSON 0x00080000U
+#define RCC_CR_PLLON 0x01000000U
+#define RCC_CR_PLLRDY 0x02000000U
+#define RCC_CR_PLLI2SON 0x04000000U
+#define RCC_CR_PLLI2SRDY 0x08000000U
+
+/******************** Bit definition for RCC_PLLCFGR register ***************/
+#define RCC_PLLCFGR_PLLM 0x0000003FU
+#define RCC_PLLCFGR_PLLM_0 0x00000001U
+#define RCC_PLLCFGR_PLLM_1 0x00000002U
+#define RCC_PLLCFGR_PLLM_2 0x00000004U
+#define RCC_PLLCFGR_PLLM_3 0x00000008U
+#define RCC_PLLCFGR_PLLM_4 0x00000010U
+#define RCC_PLLCFGR_PLLM_5 0x00000020U
+
+#define RCC_PLLCFGR_PLLN 0x00007FC0U
+#define RCC_PLLCFGR_PLLN_0 0x00000040U
+#define RCC_PLLCFGR_PLLN_1 0x00000080U
+#define RCC_PLLCFGR_PLLN_2 0x00000100U
+#define RCC_PLLCFGR_PLLN_3 0x00000200U
+#define RCC_PLLCFGR_PLLN_4 0x00000400U
+#define RCC_PLLCFGR_PLLN_5 0x00000800U
+#define RCC_PLLCFGR_PLLN_6 0x00001000U
+#define RCC_PLLCFGR_PLLN_7 0x00002000U
+#define RCC_PLLCFGR_PLLN_8 0x00004000U
+
+#define RCC_PLLCFGR_PLLP 0x00030000U
+#define RCC_PLLCFGR_PLLP_0 0x00010000U
+#define RCC_PLLCFGR_PLLP_1 0x00020000U
+
+#define RCC_PLLCFGR_PLLSRC 0x00400000U
+#define RCC_PLLCFGR_PLLSRC_HSE 0x00400000U
+#define RCC_PLLCFGR_PLLSRC_HSI 0x00000000U
+
+#define RCC_PLLCFGR_PLLQ 0x0F000000U
+#define RCC_PLLCFGR_PLLQ_0 0x01000000U
+#define RCC_PLLCFGR_PLLQ_1 0x02000000U
+#define RCC_PLLCFGR_PLLQ_2 0x04000000U
+#define RCC_PLLCFGR_PLLQ_3 0x08000000U
+
+/******************** Bit definition for RCC_CFGR register ******************/
+/*!< SW configuration */
+#define RCC_CFGR_SW 0x00000003U /*!< SW[1:0] bits (System clock Switch) */
+#define RCC_CFGR_SW_0 0x00000001U /*!< Bit 0 */
+#define RCC_CFGR_SW_1 0x00000002U /*!< Bit 1 */
+
+#define RCC_CFGR_SW_HSI 0x00000000U /*!< HSI selected as system clock */
+#define RCC_CFGR_SW_HSE 0x00000001U /*!< HSE selected as system clock */
+#define RCC_CFGR_SW_PLL 0x00000002U /*!< PLL selected as system clock */
+
+/*!< SWS configuration */
+#define RCC_CFGR_SWS 0x0000000CU /*!< SWS[1:0] bits (System Clock Switch Status) */
+#define RCC_CFGR_SWS_0 0x00000004U /*!< Bit 0 */
+#define RCC_CFGR_SWS_1 0x00000008U /*!< Bit 1 */
+
+#define RCC_CFGR_SWS_HSI 0x00000000U /*!< HSI oscillator used as system clock */
+#define RCC_CFGR_SWS_HSE 0x00000004U /*!< HSE oscillator used as system clock */
+#define RCC_CFGR_SWS_PLL 0x00000008U /*!< PLL used as system clock */
+
+/*!< HPRE configuration */
+#define RCC_CFGR_HPRE 0x000000F0U /*!< HPRE[3:0] bits (AHB prescaler) */
+#define RCC_CFGR_HPRE_0 0x00000010U /*!< Bit 0 */
+#define RCC_CFGR_HPRE_1 0x00000020U /*!< Bit 1 */
+#define RCC_CFGR_HPRE_2 0x00000040U /*!< Bit 2 */
+#define RCC_CFGR_HPRE_3 0x00000080U /*!< Bit 3 */
+
+#define RCC_CFGR_HPRE_DIV1 0x00000000U /*!< SYSCLK not divided */
+#define RCC_CFGR_HPRE_DIV2 0x00000080U /*!< SYSCLK divided by 2 */
+#define RCC_CFGR_HPRE_DIV4 0x00000090U /*!< SYSCLK divided by 4 */
+#define RCC_CFGR_HPRE_DIV8 0x000000A0U /*!< SYSCLK divided by 8 */
+#define RCC_CFGR_HPRE_DIV16 0x000000B0U /*!< SYSCLK divided by 16 */
+#define RCC_CFGR_HPRE_DIV64 0x000000C0U /*!< SYSCLK divided by 64 */
+#define RCC_CFGR_HPRE_DIV128 0x000000D0U /*!< SYSCLK divided by 128 */
+#define RCC_CFGR_HPRE_DIV256 0x000000E0U /*!< SYSCLK divided by 256 */
+#define RCC_CFGR_HPRE_DIV512 0x000000F0U /*!< SYSCLK divided by 512 */
+
+/*!< PPRE1 configuration */
+#define RCC_CFGR_PPRE1 0x00001C00U /*!< PRE1[2:0] bits (APB1 prescaler) */
+#define RCC_CFGR_PPRE1_0 0x00000400U /*!< Bit 0 */
+#define RCC_CFGR_PPRE1_1 0x00000800U /*!< Bit 1 */
+#define RCC_CFGR_PPRE1_2 0x00001000U /*!< Bit 2 */
+
+#define RCC_CFGR_PPRE1_DIV1 0x00000000U /*!< HCLK not divided */
+#define RCC_CFGR_PPRE1_DIV2 0x00001000U /*!< HCLK divided by 2 */
+#define RCC_CFGR_PPRE1_DIV4 0x00001400U /*!< HCLK divided by 4 */
+#define RCC_CFGR_PPRE1_DIV8 0x00001800U /*!< HCLK divided by 8 */
+#define RCC_CFGR_PPRE1_DIV16 0x00001C00U /*!< HCLK divided by 16 */
+
+/*!< PPRE2 configuration */
+#define RCC_CFGR_PPRE2 0x0000E000U /*!< PRE2[2:0] bits (APB2 prescaler) */
+#define RCC_CFGR_PPRE2_0 0x00002000U /*!< Bit 0 */
+#define RCC_CFGR_PPRE2_1 0x00004000U /*!< Bit 1 */
+#define RCC_CFGR_PPRE2_2 0x00008000U /*!< Bit 2 */
+
+#define RCC_CFGR_PPRE2_DIV1 0x00000000U /*!< HCLK not divided */
+#define RCC_CFGR_PPRE2_DIV2 0x00008000U /*!< HCLK divided by 2 */
+#define RCC_CFGR_PPRE2_DIV4 0x0000A000U /*!< HCLK divided by 4 */
+#define RCC_CFGR_PPRE2_DIV8 0x0000C000U /*!< HCLK divided by 8 */
+#define RCC_CFGR_PPRE2_DIV16 0x0000E000U /*!< HCLK divided by 16 */
+
+/*!< RTCPRE configuration */
+#define RCC_CFGR_RTCPRE 0x001F0000U
+#define RCC_CFGR_RTCPRE_0 0x00010000U
+#define RCC_CFGR_RTCPRE_1 0x00020000U
+#define RCC_CFGR_RTCPRE_2 0x00040000U
+#define RCC_CFGR_RTCPRE_3 0x00080000U
+#define RCC_CFGR_RTCPRE_4 0x00100000U
+
+/*!< MCO1 configuration */
+#define RCC_CFGR_MCO1 0x00600000U
+#define RCC_CFGR_MCO1_0 0x00200000U
+#define RCC_CFGR_MCO1_1 0x00400000U
+
+#define RCC_CFGR_I2SSRC 0x00800000U
+
+#define RCC_CFGR_MCO1PRE 0x07000000U
+#define RCC_CFGR_MCO1PRE_0 0x01000000U
+#define RCC_CFGR_MCO1PRE_1 0x02000000U
+#define RCC_CFGR_MCO1PRE_2 0x04000000U
+
+#define RCC_CFGR_MCO2PRE 0x38000000U
+#define RCC_CFGR_MCO2PRE_0 0x08000000U
+#define RCC_CFGR_MCO2PRE_1 0x10000000U
+#define RCC_CFGR_MCO2PRE_2 0x20000000U
+
+#define RCC_CFGR_MCO2 0xC0000000U
+#define RCC_CFGR_MCO2_0 0x40000000U
+#define RCC_CFGR_MCO2_1 0x80000000U
+
+/******************** Bit definition for RCC_CIR register *******************/
+#define RCC_CIR_LSIRDYF 0x00000001U
+#define RCC_CIR_LSERDYF 0x00000002U
+#define RCC_CIR_HSIRDYF 0x00000004U
+#define RCC_CIR_HSERDYF 0x00000008U
+#define RCC_CIR_PLLRDYF 0x00000010U
+#define RCC_CIR_PLLI2SRDYF 0x00000020U
+
+#define RCC_CIR_CSSF 0x00000080U
+#define RCC_CIR_LSIRDYIE 0x00000100U
+#define RCC_CIR_LSERDYIE 0x00000200U
+#define RCC_CIR_HSIRDYIE 0x00000400U
+#define RCC_CIR_HSERDYIE 0x00000800U
+#define RCC_CIR_PLLRDYIE 0x00001000U
+#define RCC_CIR_PLLI2SRDYIE 0x00002000U
+
+#define RCC_CIR_LSIRDYC 0x00010000U
+#define RCC_CIR_LSERDYC 0x00020000U
+#define RCC_CIR_HSIRDYC 0x00040000U
+#define RCC_CIR_HSERDYC 0x00080000U
+#define RCC_CIR_PLLRDYC 0x00100000U
+#define RCC_CIR_PLLI2SRDYC 0x00200000U
+
+#define RCC_CIR_CSSC 0x00800000U
+
+/******************** Bit definition for RCC_AHB1RSTR register **************/
+#define RCC_AHB1RSTR_GPIOARST 0x00000001U
+#define RCC_AHB1RSTR_GPIOBRST 0x00000002U
+#define RCC_AHB1RSTR_GPIOCRST 0x00000004U
+#define RCC_AHB1RSTR_GPIODRST 0x00000008U
+#define RCC_AHB1RSTR_GPIOERST 0x00000010U
+#define RCC_AHB1RSTR_GPIOHRST 0x00000080U
+#define RCC_AHB1RSTR_CRCRST 0x00001000U
+#define RCC_AHB1RSTR_DMA1RST 0x00200000U
+#define RCC_AHB1RSTR_DMA2RST 0x00400000U
+
+/******************** Bit definition for RCC_AHB2RSTR register **************/
+#define RCC_AHB2RSTR_OTGFSRST 0x00000080U
+
+/******************** Bit definition for RCC_AHB3RSTR register **************/
+
+/******************** Bit definition for RCC_APB1RSTR register **************/
+#define RCC_APB1RSTR_TIM2RST 0x00000001U
+#define RCC_APB1RSTR_TIM3RST 0x00000002U
+#define RCC_APB1RSTR_TIM4RST 0x00000004U
+#define RCC_APB1RSTR_TIM5RST 0x00000008U
+#define RCC_APB1RSTR_WWDGRST 0x00000800U
+#define RCC_APB1RSTR_SPI2RST 0x00004000U
+#define RCC_APB1RSTR_SPI3RST 0x00008000U
+#define RCC_APB1RSTR_USART2RST 0x00020000U
+#define RCC_APB1RSTR_I2C1RST 0x00200000U
+#define RCC_APB1RSTR_I2C2RST 0x00400000U
+#define RCC_APB1RSTR_I2C3RST 0x00800000U
+#define RCC_APB1RSTR_PWRRST 0x10000000U
+
+/******************** Bit definition for RCC_APB2RSTR register **************/
+#define RCC_APB2RSTR_TIM1RST 0x00000001U
+#define RCC_APB2RSTR_USART1RST 0x00000010U
+#define RCC_APB2RSTR_USART6RST 0x00000020U
+#define RCC_APB2RSTR_ADCRST 0x00000100U
+#define RCC_APB2RSTR_SDIORST 0x00000800U
+#define RCC_APB2RSTR_SPI1RST 0x00001000U
+#define RCC_APB2RSTR_SPI4RST 0x00002000U
+#define RCC_APB2RSTR_SYSCFGRST 0x00004000U
+#define RCC_APB2RSTR_TIM9RST 0x00010000U
+#define RCC_APB2RSTR_TIM10RST 0x00020000U
+#define RCC_APB2RSTR_TIM11RST 0x00040000U
+#define RCC_APB2RSTR_SPI5RST 0x00100000U
+
+/* Old SPI1RST bit definition, maintained for legacy purpose */
+#define RCC_APB2RSTR_SPI1 RCC_APB2RSTR_SPI1RST
+
+/******************** Bit definition for RCC_AHB1ENR register ***************/
+#define RCC_AHB1ENR_GPIOAEN 0x00000001U
+#define RCC_AHB1ENR_GPIOBEN 0x00000002U
+#define RCC_AHB1ENR_GPIOCEN 0x00000004U
+#define RCC_AHB1ENR_GPIODEN 0x00000008U
+#define RCC_AHB1ENR_GPIOEEN 0x00000010U
+#define RCC_AHB1ENR_GPIOHEN 0x00000080U
+#define RCC_AHB1ENR_CRCEN 0x00001000U
+#define RCC_AHB1ENR_BKPSRAMEN 0x00040000U
+#define RCC_AHB1ENR_DMA1EN 0x00200000U
+#define RCC_AHB1ENR_DMA2EN 0x00400000U
+
+/******************** Bit definition for RCC_AHB2ENR register ***************/
+#define RCC_AHB2ENR_OTGFSEN 0x00000080U
+
+/******************** Bit definition for RCC_AHB3ENR register ***************/
+
+/******************** Bit definition for RCC_APB1ENR register ***************/
+#define RCC_APB1ENR_TIM2EN 0x00000001U
+#define RCC_APB1ENR_TIM3EN 0x00000002U
+#define RCC_APB1ENR_TIM4EN 0x00000004U
+#define RCC_APB1ENR_TIM5EN 0x00000008U
+#define RCC_APB1ENR_WWDGEN 0x00000800U
+#define RCC_APB1ENR_SPI2EN 0x00004000U
+#define RCC_APB1ENR_SPI3EN 0x00008000U
+#define RCC_APB1ENR_USART2EN 0x00020000U
+#define RCC_APB1ENR_I2C1EN 0x00200000U
+#define RCC_APB1ENR_I2C2EN 0x00400000U
+#define RCC_APB1ENR_I2C3EN 0x00800000U
+#define RCC_APB1ENR_PWREN 0x10000000U
+
+/******************** Bit definition for RCC_APB2ENR register ***************/
+#define RCC_APB2ENR_TIM1EN 0x00000001U
+#define RCC_APB2ENR_USART1EN 0x00000010U
+#define RCC_APB2ENR_USART6EN 0x00000020U
+#define RCC_APB2ENR_ADC1EN 0x00000100U
+#define RCC_APB2ENR_SDIOEN 0x00000800U
+#define RCC_APB2ENR_SPI1EN 0x00001000U
+#define RCC_APB2ENR_SPI4EN 0x00002000U
+#define RCC_APB2ENR_SYSCFGEN 0x00004000U
+#define RCC_APB2ENR_TIM9EN 0x00010000U
+#define RCC_APB2ENR_TIM10EN 0x00020000U
+#define RCC_APB2ENR_TIM11EN 0x00040000U
+#define RCC_APB2ENR_SPI5EN 0x00100000U
+
+/******************** Bit definition for RCC_AHB1LPENR register *************/
+#define RCC_AHB1LPENR_GPIOALPEN 0x00000001U
+#define RCC_AHB1LPENR_GPIOBLPEN 0x00000002U
+#define RCC_AHB1LPENR_GPIOCLPEN 0x00000004U
+#define RCC_AHB1LPENR_GPIODLPEN 0x00000008U
+#define RCC_AHB1LPENR_GPIOELPEN 0x00000010U
+#define RCC_AHB1LPENR_GPIOHLPEN 0x00000080U
+#define RCC_AHB1LPENR_CRCLPEN 0x00001000U
+#define RCC_AHB1LPENR_FLITFLPEN 0x00008000U
+#define RCC_AHB1LPENR_SRAM1LPEN 0x00010000U
+#define RCC_AHB1LPENR_SRAM2LPEN 0x00020000U
+#define RCC_AHB1LPENR_BKPSRAMLPEN 0x00040000U
+#define RCC_AHB1LPENR_DMA1LPEN 0x00200000U
+#define RCC_AHB1LPENR_DMA2LPEN 0x00400000U
+
+/******************** Bit definition for RCC_AHB2LPENR register *************/
+#define RCC_AHB2LPENR_OTGFSLPEN 0x00000080U
+
+/******************** Bit definition for RCC_AHB3LPENR register *************/
+
+/******************** Bit definition for RCC_APB1LPENR register *************/
+#define RCC_APB1LPENR_TIM2LPEN 0x00000001U
+#define RCC_APB1LPENR_TIM3LPEN 0x00000002U
+#define RCC_APB1LPENR_TIM4LPEN 0x00000004U
+#define RCC_APB1LPENR_TIM5LPEN 0x00000008U
+#define RCC_APB1LPENR_WWDGLPEN 0x00000800U
+#define RCC_APB1LPENR_SPI2LPEN 0x00004000U
+#define RCC_APB1LPENR_SPI3LPEN 0x00008000U
+#define RCC_APB1LPENR_USART2LPEN 0x00020000U
+#define RCC_APB1LPENR_I2C1LPEN 0x00200000U
+#define RCC_APB1LPENR_I2C2LPEN 0x00400000U
+#define RCC_APB1LPENR_I2C3LPEN 0x00800000U
+#define RCC_APB1LPENR_PWRLPEN 0x10000000U
+#define RCC_APB1LPENR_DACLPEN 0x20000000U
+
+/******************** Bit definition for RCC_APB2LPENR register *************/
+#define RCC_APB2LPENR_TIM1LPEN 0x00000001U
+#define RCC_APB2LPENR_USART1LPEN 0x00000010U
+#define RCC_APB2LPENR_USART6LPEN 0x00000020U
+#define RCC_APB2LPENR_ADC1LPEN 0x00000100U
+#define RCC_APB2LPENR_SDIOLPEN 0x00000800U
+#define RCC_APB2LPENR_SPI1LPEN 0x00001000U
+#define RCC_APB2LPENR_SPI4LPEN 0x00002000U
+#define RCC_APB2LPENR_SYSCFGLPEN 0x00004000U
+#define RCC_APB2LPENR_TIM9LPEN 0x00010000U
+#define RCC_APB2LPENR_TIM10LPEN 0x00020000U
+#define RCC_APB2LPENR_TIM11LPEN 0x00040000U
+#define RCC_APB2LPENR_SPI5LPEN 0x00100000U
+
+/******************** Bit definition for RCC_BDCR register ******************/
+#define RCC_BDCR_LSEON 0x00000001U
+#define RCC_BDCR_LSERDY 0x00000002U
+#define RCC_BDCR_LSEBYP 0x00000004U
+#define RCC_BDCR_LSEMOD 0x00000008U
+
+#define RCC_BDCR_RTCSEL 0x00000300U
+#define RCC_BDCR_RTCSEL_0 0x00000100U
+#define RCC_BDCR_RTCSEL_1 0x00000200U
+
+#define RCC_BDCR_RTCEN 0x00008000U
+#define RCC_BDCR_BDRST 0x00010000U
+
+/******************** Bit definition for RCC_CSR register *******************/
+#define RCC_CSR_LSION 0x00000001U
+#define RCC_CSR_LSIRDY 0x00000002U
+#define RCC_CSR_RMVF 0x01000000U
+#define RCC_CSR_BORRSTF 0x02000000U
+#define RCC_CSR_PADRSTF 0x04000000U
+#define RCC_CSR_PORRSTF 0x08000000U
+#define RCC_CSR_SFTRSTF 0x10000000U
+#define RCC_CSR_WDGRSTF 0x20000000U
+#define RCC_CSR_WWDGRSTF 0x40000000U
+#define RCC_CSR_LPWRRSTF 0x80000000U
+
+/******************** Bit definition for RCC_SSCGR register *****************/
+#define RCC_SSCGR_MODPER 0x00001FFFU
+#define RCC_SSCGR_INCSTEP 0x0FFFE000U
+#define RCC_SSCGR_SPREADSEL 0x40000000U
+#define RCC_SSCGR_SSCGEN 0x80000000U
+
+/******************** Bit definition for RCC_PLLI2SCFGR register ************/
+#define RCC_PLLI2SCFGR_PLLI2SM 0x0000003FU
+#define RCC_PLLI2SCFGR_PLLI2SM_0 0x00000001U
+#define RCC_PLLI2SCFGR_PLLI2SM_1 0x00000002U
+#define RCC_PLLI2SCFGR_PLLI2SM_2 0x00000004U
+#define RCC_PLLI2SCFGR_PLLI2SM_3 0x00000008U
+#define RCC_PLLI2SCFGR_PLLI2SM_4 0x00000010U
+#define RCC_PLLI2SCFGR_PLLI2SM_5 0x00000020U
+
+#define RCC_PLLI2SCFGR_PLLI2SN 0x00007FC0U
+#define RCC_PLLI2SCFGR_PLLI2SN_0 0x00000040U
+#define RCC_PLLI2SCFGR_PLLI2SN_1 0x00000080U
+#define RCC_PLLI2SCFGR_PLLI2SN_2 0x00000100U
+#define RCC_PLLI2SCFGR_PLLI2SN_3 0x00000200U
+#define RCC_PLLI2SCFGR_PLLI2SN_4 0x00000400U
+#define RCC_PLLI2SCFGR_PLLI2SN_5 0x00000800U
+#define RCC_PLLI2SCFGR_PLLI2SN_6 0x00001000U
+#define RCC_PLLI2SCFGR_PLLI2SN_7 0x00002000U
+#define RCC_PLLI2SCFGR_PLLI2SN_8 0x00004000U
+
+#define RCC_PLLI2SCFGR_PLLI2SR 0x70000000U
+#define RCC_PLLI2SCFGR_PLLI2SR_0 0x10000000U
+#define RCC_PLLI2SCFGR_PLLI2SR_1 0x20000000U
+#define RCC_PLLI2SCFGR_PLLI2SR_2 0x40000000U
+
+/******************** Bit definition for RCC_DCKCFGR register ***************/
+#define RCC_DCKCFGR_TIMPRE 0x01000000U
+
+/******************************************************************************/
+/* */
+/* Real-Time Clock (RTC) */
+/* */
+/******************************************************************************/
+/******************** Bits definition for RTC_TR register *******************/
+#define RTC_TR_PM 0x00400000U
+#define RTC_TR_HT 0x00300000U
+#define RTC_TR_HT_0 0x00100000U
+#define RTC_TR_HT_1 0x00200000U
+#define RTC_TR_HU 0x000F0000U
+#define RTC_TR_HU_0 0x00010000U
+#define RTC_TR_HU_1 0x00020000U
+#define RTC_TR_HU_2 0x00040000U
+#define RTC_TR_HU_3 0x00080000U
+#define RTC_TR_MNT 0x00007000U
+#define RTC_TR_MNT_0 0x00001000U
+#define RTC_TR_MNT_1 0x00002000U
+#define RTC_TR_MNT_2 0x00004000U
+#define RTC_TR_MNU 0x00000F00U
+#define RTC_TR_MNU_0 0x00000100U
+#define RTC_TR_MNU_1 0x00000200U
+#define RTC_TR_MNU_2 0x00000400U
+#define RTC_TR_MNU_3 0x00000800U
+#define RTC_TR_ST 0x00000070U
+#define RTC_TR_ST_0 0x00000010U
+#define RTC_TR_ST_1 0x00000020U
+#define RTC_TR_ST_2 0x00000040U
+#define RTC_TR_SU 0x0000000FU
+#define RTC_TR_SU_0 0x00000001U
+#define RTC_TR_SU_1 0x00000002U
+#define RTC_TR_SU_2 0x00000004U
+#define RTC_TR_SU_3 0x00000008U
+
+/******************** Bits definition for RTC_DR register *******************/
+#define RTC_DR_YT 0x00F00000U
+#define RTC_DR_YT_0 0x00100000U
+#define RTC_DR_YT_1 0x00200000U
+#define RTC_DR_YT_2 0x00400000U
+#define RTC_DR_YT_3 0x00800000U
+#define RTC_DR_YU 0x000F0000U
+#define RTC_DR_YU_0 0x00010000U
+#define RTC_DR_YU_1 0x00020000U
+#define RTC_DR_YU_2 0x00040000U
+#define RTC_DR_YU_3 0x00080000U
+#define RTC_DR_WDU 0x0000E000U
+#define RTC_DR_WDU_0 0x00002000U
+#define RTC_DR_WDU_1 0x00004000U
+#define RTC_DR_WDU_2 0x00008000U
+#define RTC_DR_MT 0x00001000U
+#define RTC_DR_MU 0x00000F00U
+#define RTC_DR_MU_0 0x00000100U
+#define RTC_DR_MU_1 0x00000200U
+#define RTC_DR_MU_2 0x00000400U
+#define RTC_DR_MU_3 0x00000800U
+#define RTC_DR_DT 0x00000030U
+#define RTC_DR_DT_0 0x00000010U
+#define RTC_DR_DT_1 0x00000020U
+#define RTC_DR_DU 0x0000000FU
+#define RTC_DR_DU_0 0x00000001U
+#define RTC_DR_DU_1 0x00000002U
+#define RTC_DR_DU_2 0x00000004U
+#define RTC_DR_DU_3 0x00000008U
+
+/******************** Bits definition for RTC_CR register *******************/
+#define RTC_CR_COE 0x00800000U
+#define RTC_CR_OSEL 0x00600000U
+#define RTC_CR_OSEL_0 0x00200000U
+#define RTC_CR_OSEL_1 0x00400000U
+#define RTC_CR_POL 0x00100000U
+#define RTC_CR_COSEL 0x00080000U
+#define RTC_CR_BCK 0x00040000U
+#define RTC_CR_SUB1H 0x00020000U
+#define RTC_CR_ADD1H 0x00010000U
+#define RTC_CR_TSIE 0x00008000U
+#define RTC_CR_WUTIE 0x00004000U
+#define RTC_CR_ALRBIE 0x00002000U
+#define RTC_CR_ALRAIE 0x00001000U
+#define RTC_CR_TSE 0x00000800U
+#define RTC_CR_WUTE 0x00000400U
+#define RTC_CR_ALRBE 0x00000200U
+#define RTC_CR_ALRAE 0x00000100U
+#define RTC_CR_DCE 0x00000080U
+#define RTC_CR_FMT 0x00000040U
+#define RTC_CR_BYPSHAD 0x00000020U
+#define RTC_CR_REFCKON 0x00000010U
+#define RTC_CR_TSEDGE 0x00000008U
+#define RTC_CR_WUCKSEL 0x00000007U
+#define RTC_CR_WUCKSEL_0 0x00000001U
+#define RTC_CR_WUCKSEL_1 0x00000002U
+#define RTC_CR_WUCKSEL_2 0x00000004U
+
+/******************** Bits definition for RTC_ISR register ******************/
+#define RTC_ISR_RECALPF 0x00010000U
+#define RTC_ISR_TAMP1F 0x00002000U
+#define RTC_ISR_TAMP2F 0x00004000U
+#define RTC_ISR_TSOVF 0x00001000U
+#define RTC_ISR_TSF 0x00000800U
+#define RTC_ISR_WUTF 0x00000400U
+#define RTC_ISR_ALRBF 0x00000200U
+#define RTC_ISR_ALRAF 0x00000100U
+#define RTC_ISR_INIT 0x00000080U
+#define RTC_ISR_INITF 0x00000040U
+#define RTC_ISR_RSF 0x00000020U
+#define RTC_ISR_INITS 0x00000010U
+#define RTC_ISR_SHPF 0x00000008U
+#define RTC_ISR_WUTWF 0x00000004U
+#define RTC_ISR_ALRBWF 0x00000002U
+#define RTC_ISR_ALRAWF 0x00000001U
+
+/******************** Bits definition for RTC_PRER register *****************/
+#define RTC_PRER_PREDIV_A 0x007F0000U
+#define RTC_PRER_PREDIV_S 0x00007FFFU
+
+/******************** Bits definition for RTC_WUTR register *****************/
+#define RTC_WUTR_WUT 0x0000FFFFU
+
+/******************** Bits definition for RTC_CALIBR register ***************/
+#define RTC_CALIBR_DCS 0x00000080U
+#define RTC_CALIBR_DC 0x0000001FU
+
+/******************** Bits definition for RTC_ALRMAR register ***************/
+#define RTC_ALRMAR_MSK4 0x80000000U
+#define RTC_ALRMAR_WDSEL 0x40000000U
+#define RTC_ALRMAR_DT 0x30000000U
+#define RTC_ALRMAR_DT_0 0x10000000U
+#define RTC_ALRMAR_DT_1 0x20000000U
+#define RTC_ALRMAR_DU 0x0F000000U
+#define RTC_ALRMAR_DU_0 0x01000000U
+#define RTC_ALRMAR_DU_1 0x02000000U
+#define RTC_ALRMAR_DU_2 0x04000000U
+#define RTC_ALRMAR_DU_3 0x08000000U
+#define RTC_ALRMAR_MSK3 0x00800000U
+#define RTC_ALRMAR_PM 0x00400000U
+#define RTC_ALRMAR_HT 0x00300000U
+#define RTC_ALRMAR_HT_0 0x00100000U
+#define RTC_ALRMAR_HT_1 0x00200000U
+#define RTC_ALRMAR_HU 0x000F0000U
+#define RTC_ALRMAR_HU_0 0x00010000U
+#define RTC_ALRMAR_HU_1 0x00020000U
+#define RTC_ALRMAR_HU_2 0x00040000U
+#define RTC_ALRMAR_HU_3 0x00080000U
+#define RTC_ALRMAR_MSK2 0x00008000U
+#define RTC_ALRMAR_MNT 0x00007000U
+#define RTC_ALRMAR_MNT_0 0x00001000U
+#define RTC_ALRMAR_MNT_1 0x00002000U
+#define RTC_ALRMAR_MNT_2 0x00004000U
+#define RTC_ALRMAR_MNU 0x00000F00U
+#define RTC_ALRMAR_MNU_0 0x00000100U
+#define RTC_ALRMAR_MNU_1 0x00000200U
+#define RTC_ALRMAR_MNU_2 0x00000400U
+#define RTC_ALRMAR_MNU_3 0x00000800U
+#define RTC_ALRMAR_MSK1 0x00000080U
+#define RTC_ALRMAR_ST 0x00000070U
+#define RTC_ALRMAR_ST_0 0x00000010U
+#define RTC_ALRMAR_ST_1 0x00000020U
+#define RTC_ALRMAR_ST_2 0x00000040U
+#define RTC_ALRMAR_SU 0x0000000FU
+#define RTC_ALRMAR_SU_0 0x00000001U
+#define RTC_ALRMAR_SU_1 0x00000002U
+#define RTC_ALRMAR_SU_2 0x00000004U
+#define RTC_ALRMAR_SU_3 0x00000008U
+
+/******************** Bits definition for RTC_ALRMBR register ***************/
+#define RTC_ALRMBR_MSK4 0x80000000U
+#define RTC_ALRMBR_WDSEL 0x40000000U
+#define RTC_ALRMBR_DT 0x30000000U
+#define RTC_ALRMBR_DT_0 0x10000000U
+#define RTC_ALRMBR_DT_1 0x20000000U
+#define RTC_ALRMBR_DU 0x0F000000U
+#define RTC_ALRMBR_DU_0 0x01000000U
+#define RTC_ALRMBR_DU_1 0x02000000U
+#define RTC_ALRMBR_DU_2 0x04000000U
+#define RTC_ALRMBR_DU_3 0x08000000U
+#define RTC_ALRMBR_MSK3 0x00800000U
+#define RTC_ALRMBR_PM 0x00400000U
+#define RTC_ALRMBR_HT 0x00300000U
+#define RTC_ALRMBR_HT_0 0x00100000U
+#define RTC_ALRMBR_HT_1 0x00200000U
+#define RTC_ALRMBR_HU 0x000F0000U
+#define RTC_ALRMBR_HU_0 0x00010000U
+#define RTC_ALRMBR_HU_1 0x00020000U
+#define RTC_ALRMBR_HU_2 0x00040000U
+#define RTC_ALRMBR_HU_3 0x00080000U
+#define RTC_ALRMBR_MSK2 0x00008000U
+#define RTC_ALRMBR_MNT 0x00007000U
+#define RTC_ALRMBR_MNT_0 0x00001000U
+#define RTC_ALRMBR_MNT_1 0x00002000U
+#define RTC_ALRMBR_MNT_2 0x00004000U
+#define RTC_ALRMBR_MNU 0x00000F00U
+#define RTC_ALRMBR_MNU_0 0x00000100U
+#define RTC_ALRMBR_MNU_1 0x00000200U
+#define RTC_ALRMBR_MNU_2 0x00000400U
+#define RTC_ALRMBR_MNU_3 0x00000800U
+#define RTC_ALRMBR_MSK1 0x00000080U
+#define RTC_ALRMBR_ST 0x00000070U
+#define RTC_ALRMBR_ST_0 0x00000010U
+#define RTC_ALRMBR_ST_1 0x00000020U
+#define RTC_ALRMBR_ST_2 0x00000040U
+#define RTC_ALRMBR_SU 0x0000000FU
+#define RTC_ALRMBR_SU_0 0x00000001U
+#define RTC_ALRMBR_SU_1 0x00000002U
+#define RTC_ALRMBR_SU_2 0x00000004U
+#define RTC_ALRMBR_SU_3 0x00000008U
+
+/******************** Bits definition for RTC_WPR register ******************/
+#define RTC_WPR_KEY 0x000000FFU
+
+/******************** Bits definition for RTC_SSR register ******************/
+#define RTC_SSR_SS 0x0000FFFFU
+
+/******************** Bits definition for RTC_SHIFTR register ***************/
+#define RTC_SHIFTR_SUBFS 0x00007FFFU
+#define RTC_SHIFTR_ADD1S 0x80000000U
+
+/******************** Bits definition for RTC_TSTR register *****************/
+#define RTC_TSTR_PM 0x00400000U
+#define RTC_TSTR_HT 0x00300000U
+#define RTC_TSTR_HT_0 0x00100000U
+#define RTC_TSTR_HT_1 0x00200000U
+#define RTC_TSTR_HU 0x000F0000U
+#define RTC_TSTR_HU_0 0x00010000U
+#define RTC_TSTR_HU_1 0x00020000U
+#define RTC_TSTR_HU_2 0x00040000U
+#define RTC_TSTR_HU_3 0x00080000U
+#define RTC_TSTR_MNT 0x00007000U
+#define RTC_TSTR_MNT_0 0x00001000U
+#define RTC_TSTR_MNT_1 0x00002000U
+#define RTC_TSTR_MNT_2 0x00004000U
+#define RTC_TSTR_MNU 0x00000F00U
+#define RTC_TSTR_MNU_0 0x00000100U
+#define RTC_TSTR_MNU_1 0x00000200U
+#define RTC_TSTR_MNU_2 0x00000400U
+#define RTC_TSTR_MNU_3 0x00000800U
+#define RTC_TSTR_ST 0x00000070U
+#define RTC_TSTR_ST_0 0x00000010U
+#define RTC_TSTR_ST_1 0x00000020U
+#define RTC_TSTR_ST_2 0x00000040U
+#define RTC_TSTR_SU 0x0000000FU
+#define RTC_TSTR_SU_0 0x00000001U
+#define RTC_TSTR_SU_1 0x00000002U
+#define RTC_TSTR_SU_2 0x00000004U
+#define RTC_TSTR_SU_3 0x00000008U
+
+/******************** Bits definition for RTC_TSDR register *****************/
+#define RTC_TSDR_WDU 0x0000E000U
+#define RTC_TSDR_WDU_0 0x00002000U
+#define RTC_TSDR_WDU_1 0x00004000U
+#define RTC_TSDR_WDU_2 0x00008000U
+#define RTC_TSDR_MT 0x00001000U
+#define RTC_TSDR_MU 0x00000F00U
+#define RTC_TSDR_MU_0 0x00000100U
+#define RTC_TSDR_MU_1 0x00000200U
+#define RTC_TSDR_MU_2 0x00000400U
+#define RTC_TSDR_MU_3 0x00000800U
+#define RTC_TSDR_DT 0x00000030U
+#define RTC_TSDR_DT_0 0x00000010U
+#define RTC_TSDR_DT_1 0x00000020U
+#define RTC_TSDR_DU 0x0000000FU
+#define RTC_TSDR_DU_0 0x00000001U
+#define RTC_TSDR_DU_1 0x00000002U
+#define RTC_TSDR_DU_2 0x00000004U
+#define RTC_TSDR_DU_3 0x00000008U
+
+/******************** Bits definition for RTC_TSSSR register ****************/
+#define RTC_TSSSR_SS 0x0000FFFFU
+
+/******************** Bits definition for RTC_CAL register *****************/
+#define RTC_CALR_CALP 0x00008000U
+#define RTC_CALR_CALW8 0x00004000U
+#define RTC_CALR_CALW16 0x00002000U
+#define RTC_CALR_CALM 0x000001FFU
+#define RTC_CALR_CALM_0 0x00000001U
+#define RTC_CALR_CALM_1 0x00000002U
+#define RTC_CALR_CALM_2 0x00000004U
+#define RTC_CALR_CALM_3 0x00000008U
+#define RTC_CALR_CALM_4 0x00000010U
+#define RTC_CALR_CALM_5 0x00000020U
+#define RTC_CALR_CALM_6 0x00000040U
+#define RTC_CALR_CALM_7 0x00000080U
+#define RTC_CALR_CALM_8 0x00000100U
+
+/******************** Bits definition for RTC_TAFCR register ****************/
+#define RTC_TAFCR_ALARMOUTTYPE 0x00040000U
+#define RTC_TAFCR_TSINSEL 0x00020000U
+#define RTC_TAFCR_TAMPINSEL 0x00010000U
+#define RTC_TAFCR_TAMPPUDIS 0x00008000U
+#define RTC_TAFCR_TAMPPRCH 0x00006000U
+#define RTC_TAFCR_TAMPPRCH_0 0x00002000U
+#define RTC_TAFCR_TAMPPRCH_1 0x00004000U
+#define RTC_TAFCR_TAMPFLT 0x00001800U
+#define RTC_TAFCR_TAMPFLT_0 0x00000800U
+#define RTC_TAFCR_TAMPFLT_1 0x00001000U
+#define RTC_TAFCR_TAMPFREQ 0x00000700U
+#define RTC_TAFCR_TAMPFREQ_0 0x00000100U
+#define RTC_TAFCR_TAMPFREQ_1 0x00000200U
+#define RTC_TAFCR_TAMPFREQ_2 0x00000400U
+#define RTC_TAFCR_TAMPTS 0x00000080U
+#define RTC_TAFCR_TAMP2TRG 0x00000010U
+#define RTC_TAFCR_TAMP2E 0x00000008U
+#define RTC_TAFCR_TAMPIE 0x00000004U
+#define RTC_TAFCR_TAMP1TRG 0x00000002U
+#define RTC_TAFCR_TAMP1E 0x00000001U
+
+/******************** Bits definition for RTC_ALRMASSR register *************/
+#define RTC_ALRMASSR_MASKSS 0x0F000000U
+#define RTC_ALRMASSR_MASKSS_0 0x01000000U
+#define RTC_ALRMASSR_MASKSS_1 0x02000000U
+#define RTC_ALRMASSR_MASKSS_2 0x04000000U
+#define RTC_ALRMASSR_MASKSS_3 0x08000000U
+#define RTC_ALRMASSR_SS 0x00007FFFU
+
+/******************** Bits definition for RTC_ALRMBSSR register *************/
+#define RTC_ALRMBSSR_MASKSS 0x0F000000U
+#define RTC_ALRMBSSR_MASKSS_0 0x01000000U
+#define RTC_ALRMBSSR_MASKSS_1 0x02000000U
+#define RTC_ALRMBSSR_MASKSS_2 0x04000000U
+#define RTC_ALRMBSSR_MASKSS_3 0x08000000U
+#define RTC_ALRMBSSR_SS 0x00007FFFU
+
+/******************** Bits definition for RTC_BKP0R register ****************/
+#define RTC_BKP0R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP1R register ****************/
+#define RTC_BKP1R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP2R register ****************/
+#define RTC_BKP2R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP3R register ****************/
+#define RTC_BKP3R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP4R register ****************/
+#define RTC_BKP4R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP5R register ****************/
+#define RTC_BKP5R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP6R register ****************/
+#define RTC_BKP6R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP7R register ****************/
+#define RTC_BKP7R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP8R register ****************/
+#define RTC_BKP8R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP9R register ****************/
+#define RTC_BKP9R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP10R register ***************/
+#define RTC_BKP10R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP11R register ***************/
+#define RTC_BKP11R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP12R register ***************/
+#define RTC_BKP12R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP13R register ***************/
+#define RTC_BKP13R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP14R register ***************/
+#define RTC_BKP14R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP15R register ***************/
+#define RTC_BKP15R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP16R register ***************/
+#define RTC_BKP16R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP17R register ***************/
+#define RTC_BKP17R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP18R register ***************/
+#define RTC_BKP18R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP19R register ***************/
+#define RTC_BKP19R 0xFFFFFFFFU
+
+
+
+/******************************************************************************/
+/* */
+/* SD host Interface */
+/* */
+/******************************************************************************/
+/****************** Bit definition for SDIO_POWER register ******************/
+#define SDIO_POWER_PWRCTRL 0x03U /*!<PWRCTRL[1:0] bits (Power supply control bits) */
+#define SDIO_POWER_PWRCTRL_0 0x01U /*!<Bit 0 */
+#define SDIO_POWER_PWRCTRL_1 0x02U /*!<Bit 1 */
+
+/****************** Bit definition for SDIO_CLKCR register ******************/
+#define SDIO_CLKCR_CLKDIV 0x00FFU /*!<Clock divide factor */
+#define SDIO_CLKCR_CLKEN 0x0100U /*!<Clock enable bit */
+#define SDIO_CLKCR_PWRSAV 0x0200U /*!<Power saving configuration bit */
+#define SDIO_CLKCR_BYPASS 0x0400U /*!<Clock divider bypass enable bit */
+
+#define SDIO_CLKCR_WIDBUS 0x1800U /*!<WIDBUS[1:0] bits (Wide bus mode enable bit) */
+#define SDIO_CLKCR_WIDBUS_0 0x0800U /*!<Bit 0 */
+#define SDIO_CLKCR_WIDBUS_1 0x1000U /*!<Bit 1 */
+
+#define SDIO_CLKCR_NEGEDGE 0x2000U /*!<SDIO_CK dephasing selection bit */
+#define SDIO_CLKCR_HWFC_EN 0x4000U /*!<HW Flow Control enable */
+
+/******************* Bit definition for SDIO_ARG register *******************/
+#define SDIO_ARG_CMDARG 0xFFFFFFFFU /*!<Command argument */
+
+/******************* Bit definition for SDIO_CMD register *******************/
+#define SDIO_CMD_CMDINDEX 0x003FU /*!<Command Index */
+
+#define SDIO_CMD_WAITRESP 0x00C0U /*!<WAITRESP[1:0] bits (Wait for response bits) */
+#define SDIO_CMD_WAITRESP_0 0x0040U /*!< Bit 0 */
+#define SDIO_CMD_WAITRESP_1 0x0080U /*!< Bit 1 */
+
+#define SDIO_CMD_WAITINT 0x0100U /*!<CPSM Waits for Interrupt Request */
+#define SDIO_CMD_WAITPEND 0x0200U /*!<CPSM Waits for ends of data transfer (CmdPend internal signal) */
+#define SDIO_CMD_CPSMEN 0x0400U /*!<Command path state machine (CPSM) Enable bit */
+#define SDIO_CMD_SDIOSUSPEND 0x0800U /*!<SD I/O suspend command */
+#define SDIO_CMD_ENCMDCOMPL 0x1000U /*!<Enable CMD completion */
+#define SDIO_CMD_NIEN 0x2000U /*!<Not Interrupt Enable */
+#define SDIO_CMD_CEATACMD 0x4000U /*!<CE-ATA command */
+
+/***************** Bit definition for SDIO_RESPCMD register *****************/
+#define SDIO_RESPCMD_RESPCMD 0x3FU /*!<Response command index */
+
+/****************** Bit definition for SDIO_RESP0 register ******************/
+#define SDIO_RESP0_CARDSTATUS0 0xFFFFFFFFU /*!<Card Status */
+
+/****************** Bit definition for SDIO_RESP1 register ******************/
+#define SDIO_RESP1_CARDSTATUS1 0xFFFFFFFFU /*!<Card Status */
+
+/****************** Bit definition for SDIO_RESP2 register ******************/
+#define SDIO_RESP2_CARDSTATUS2 0xFFFFFFFFU /*!<Card Status */
+
+/****************** Bit definition for SDIO_RESP3 register ******************/
+#define SDIO_RESP3_CARDSTATUS3 0xFFFFFFFFU /*!<Card Status */
+
+/****************** Bit definition for SDIO_RESP4 register ******************/
+#define SDIO_RESP4_CARDSTATUS4 0xFFFFFFFFU /*!<Card Status */
+
+/****************** Bit definition for SDIO_DTIMER register *****************/
+#define SDIO_DTIMER_DATATIME 0xFFFFFFFFU /*!<Data timeout period. */
+
+/****************** Bit definition for SDIO_DLEN register *******************/
+#define SDIO_DLEN_DATALENGTH 0x01FFFFFFU /*!<Data length value */
+
+/****************** Bit definition for SDIO_DCTRL register ******************/
+#define SDIO_DCTRL_DTEN 0x0001U /*!<Data transfer enabled bit */
+#define SDIO_DCTRL_DTDIR 0x0002U /*!<Data transfer direction selection */
+#define SDIO_DCTRL_DTMODE 0x0004U /*!<Data transfer mode selection */
+#define SDIO_DCTRL_DMAEN 0x0008U /*!<DMA enabled bit */
+
+#define SDIO_DCTRL_DBLOCKSIZE 0x00F0U /*!<DBLOCKSIZE[3:0] bits (Data block size) */
+#define SDIO_DCTRL_DBLOCKSIZE_0 0x0010U /*!<Bit 0 */
+#define SDIO_DCTRL_DBLOCKSIZE_1 0x0020U /*!<Bit 1 */
+#define SDIO_DCTRL_DBLOCKSIZE_2 0x0040U /*!<Bit 2 */
+#define SDIO_DCTRL_DBLOCKSIZE_3 0x0080U /*!<Bit 3 */
+
+#define SDIO_DCTRL_RWSTART 0x0100U /*!<Read wait start */
+#define SDIO_DCTRL_RWSTOP 0x0200U /*!<Read wait stop */
+#define SDIO_DCTRL_RWMOD 0x0400U /*!<Read wait mode */
+#define SDIO_DCTRL_SDIOEN 0x0800U /*!<SD I/O enable functions */
+
+/****************** Bit definition for SDIO_DCOUNT register *****************/
+#define SDIO_DCOUNT_DATACOUNT 0x01FFFFFFU /*!<Data count value */
+
+/****************** Bit definition for SDIO_STA register ********************/
+#define SDIO_STA_CCRCFAIL 0x00000001U /*!<Command response received (CRC check failed) */
+#define SDIO_STA_DCRCFAIL 0x00000002U /*!<Data block sent/received (CRC check failed) */
+#define SDIO_STA_CTIMEOUT 0x00000004U /*!<Command response timeout */
+#define SDIO_STA_DTIMEOUT 0x00000008U /*!<Data timeout */
+#define SDIO_STA_TXUNDERR 0x00000010U /*!<Transmit FIFO underrun error */
+#define SDIO_STA_RXOVERR 0x00000020U /*!<Received FIFO overrun error */
+#define SDIO_STA_CMDREND 0x00000040U /*!<Command response received (CRC check passed) */
+#define SDIO_STA_CMDSENT 0x00000080U /*!<Command sent (no response required) */
+#define SDIO_STA_DATAEND 0x00000100U /*!<Data end (data counter, SDIDCOUNT, is zero) */
+#define SDIO_STA_STBITERR 0x00000200U /*!<Start bit not detected on all data signals in wide bus mode */
+#define SDIO_STA_DBCKEND 0x00000400U /*!<Data block sent/received (CRC check passed) */
+#define SDIO_STA_CMDACT 0x00000800U /*!<Command transfer in progress */
+#define SDIO_STA_TXACT 0x00001000U /*!<Data transmit in progress */
+#define SDIO_STA_RXACT 0x00002000U /*!<Data receive in progress */
+#define SDIO_STA_TXFIFOHE 0x00004000U /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
+#define SDIO_STA_RXFIFOHF 0x00008000U /*!<Receive FIFO Half Full: there are at least 8 words in the FIFO */
+#define SDIO_STA_TXFIFOF 0x00010000U /*!<Transmit FIFO full */
+#define SDIO_STA_RXFIFOF 0x00020000U /*!<Receive FIFO full */
+#define SDIO_STA_TXFIFOE 0x00040000U /*!<Transmit FIFO empty */
+#define SDIO_STA_RXFIFOE 0x00080000U /*!<Receive FIFO empty */
+#define SDIO_STA_TXDAVL 0x00100000U /*!<Data available in transmit FIFO */
+#define SDIO_STA_RXDAVL 0x00200000U /*!<Data available in receive FIFO */
+#define SDIO_STA_SDIOIT 0x00400000U /*!<SDIO interrupt received */
+#define SDIO_STA_CEATAEND 0x00800000U /*!<CE-ATA command completion signal received for CMD61 */
+
+/******************* Bit definition for SDIO_ICR register *******************/
+#define SDIO_ICR_CCRCFAILC 0x00000001U /*!<CCRCFAIL flag clear bit */
+#define SDIO_ICR_DCRCFAILC 0x00000002U /*!<DCRCFAIL flag clear bit */
+#define SDIO_ICR_CTIMEOUTC 0x00000004U /*!<CTIMEOUT flag clear bit */
+#define SDIO_ICR_DTIMEOUTC 0x00000008U /*!<DTIMEOUT flag clear bit */
+#define SDIO_ICR_TXUNDERRC 0x00000010U /*!<TXUNDERR flag clear bit */
+#define SDIO_ICR_RXOVERRC 0x00000020U /*!<RXOVERR flag clear bit */
+#define SDIO_ICR_CMDRENDC 0x00000040U /*!<CMDREND flag clear bit */
+#define SDIO_ICR_CMDSENTC 0x00000080U /*!<CMDSENT flag clear bit */
+#define SDIO_ICR_DATAENDC 0x00000100U /*!<DATAEND flag clear bit */
+#define SDIO_ICR_STBITERRC 0x00000200U /*!<STBITERR flag clear bit */
+#define SDIO_ICR_DBCKENDC 0x00000400U /*!<DBCKEND flag clear bit */
+#define SDIO_ICR_SDIOITC 0x00400000U /*!<SDIOIT flag clear bit */
+#define SDIO_ICR_CEATAENDC 0x00800000U /*!<CEATAEND flag clear bit */
+
+/****************** Bit definition for SDIO_MASK register *******************/
+#define SDIO_MASK_CCRCFAILIE 0x00000001U /*!<Command CRC Fail Interrupt Enable */
+#define SDIO_MASK_DCRCFAILIE 0x00000002U /*!<Data CRC Fail Interrupt Enable */
+#define SDIO_MASK_CTIMEOUTIE 0x00000004U /*!<Command TimeOut Interrupt Enable */
+#define SDIO_MASK_DTIMEOUTIE 0x00000008U /*!<Data TimeOut Interrupt Enable */
+#define SDIO_MASK_TXUNDERRIE 0x00000010U /*!<Tx FIFO UnderRun Error Interrupt Enable */
+#define SDIO_MASK_RXOVERRIE 0x00000020U /*!<Rx FIFO OverRun Error Interrupt Enable */
+#define SDIO_MASK_CMDRENDIE 0x00000040U /*!<Command Response Received Interrupt Enable */
+#define SDIO_MASK_CMDSENTIE 0x00000080U /*!<Command Sent Interrupt Enable */
+#define SDIO_MASK_DATAENDIE 0x00000100U /*!<Data End Interrupt Enable */
+#define SDIO_MASK_STBITERRIE 0x00000200U /*!<Start Bit Error Interrupt Enable */
+#define SDIO_MASK_DBCKENDIE 0x00000400U /*!<Data Block End Interrupt Enable */
+#define SDIO_MASK_CMDACTIE 0x00000800U /*!<CCommand Acting Interrupt Enable */
+#define SDIO_MASK_TXACTIE 0x00001000U /*!<Data Transmit Acting Interrupt Enable */
+#define SDIO_MASK_RXACTIE 0x00002000U /*!<Data receive acting interrupt enabled */
+#define SDIO_MASK_TXFIFOHEIE 0x00004000U /*!<Tx FIFO Half Empty interrupt Enable */
+#define SDIO_MASK_RXFIFOHFIE 0x00008000U /*!<Rx FIFO Half Full interrupt Enable */
+#define SDIO_MASK_TXFIFOFIE 0x00010000U /*!<Tx FIFO Full interrupt Enable */
+#define SDIO_MASK_RXFIFOFIE 0x00020000U /*!<Rx FIFO Full interrupt Enable */
+#define SDIO_MASK_TXFIFOEIE 0x00040000U /*!<Tx FIFO Empty interrupt Enable */
+#define SDIO_MASK_RXFIFOEIE 0x00080000U /*!<Rx FIFO Empty interrupt Enable */
+#define SDIO_MASK_TXDAVLIE 0x00100000U /*!<Data available in Tx FIFO interrupt Enable */
+#define SDIO_MASK_RXDAVLIE 0x00200000U /*!<Data available in Rx FIFO interrupt Enable */
+#define SDIO_MASK_SDIOITIE 0x00400000U /*!<SDIO Mode Interrupt Received interrupt Enable */
+#define SDIO_MASK_CEATAENDIE 0x00800000U /*!<CE-ATA command completion signal received Interrupt Enable */
+
+/***************** Bit definition for SDIO_FIFOCNT register *****************/
+#define SDIO_FIFOCNT_FIFOCOUNT 0x00FFFFFFU /*!<Remaining number of words to be written to or read from the FIFO */
+
+/****************** Bit definition for SDIO_FIFO register *******************/
+#define SDIO_FIFO_FIFODATA 0xFFFFFFFFU /*!<Receive and transmit FIFO data */
+
+/******************************************************************************/
+/* */
+/* Serial Peripheral Interface */
+/* */
+/******************************************************************************/
+/******************* Bit definition for SPI_CR1 register ********************/
+#define SPI_CR1_CPHA 0x00000001U /*!<Clock Phase */
+#define SPI_CR1_CPOL 0x00000002U /*!<Clock Polarity */
+#define SPI_CR1_MSTR 0x00000004U /*!<Master Selection */
+
+#define SPI_CR1_BR 0x00000038U /*!<BR[2:0] bits (Baud Rate Control) */
+#define SPI_CR1_BR_0 0x00000008U /*!<Bit 0 */
+#define SPI_CR1_BR_1 0x00000010U /*!<Bit 1 */
+#define SPI_CR1_BR_2 0x00000020U /*!<Bit 2 */
+
+#define SPI_CR1_SPE 0x00000040U /*!<SPI Enable */
+#define SPI_CR1_LSBFIRST 0x00000080U /*!<Frame Format */
+#define SPI_CR1_SSI 0x00000100U /*!<Internal slave select */
+#define SPI_CR1_SSM 0x00000200U /*!<Software slave management */
+#define SPI_CR1_RXONLY 0x00000400U /*!<Receive only */
+#define SPI_CR1_DFF 0x00000800U /*!<Data Frame Format */
+#define SPI_CR1_CRCNEXT 0x00001000U /*!<Transmit CRC next */
+#define SPI_CR1_CRCEN 0x00002000U /*!<Hardware CRC calculation enable */
+#define SPI_CR1_BIDIOE 0x00004000U /*!<Output enable in bidirectional mode */
+#define SPI_CR1_BIDIMODE 0x00008000U /*!<Bidirectional data mode enable */
+
+/******************* Bit definition for SPI_CR2 register ********************/
+#define SPI_CR2_RXDMAEN 0x00000001U /*!<Rx Buffer DMA Enable */
+#define SPI_CR2_TXDMAEN 0x00000002U /*!<Tx Buffer DMA Enable */
+#define SPI_CR2_SSOE 0x00000004U /*!<SS Output Enable */
+#define SPI_CR2_FRF 0x00000010U /*!<Frame Format */
+#define SPI_CR2_ERRIE 0x00000020U /*!<Error Interrupt Enable */
+#define SPI_CR2_RXNEIE 0x00000040U /*!<RX buffer Not Empty Interrupt Enable */
+#define SPI_CR2_TXEIE 0x00000080U /*!<Tx buffer Empty Interrupt Enable */
+
+/******************** Bit definition for SPI_SR register ********************/
+#define SPI_SR_RXNE 0x00000001U /*!<Receive buffer Not Empty */
+#define SPI_SR_TXE 0x00000002U /*!<Transmit buffer Empty */
+#define SPI_SR_CHSIDE 0x00000004U /*!<Channel side */
+#define SPI_SR_UDR 0x00000008U /*!<Underrun flag */
+#define SPI_SR_CRCERR 0x00000010U /*!<CRC Error flag */
+#define SPI_SR_MODF 0x00000020U /*!<Mode fault */
+#define SPI_SR_OVR 0x00000040U /*!<Overrun flag */
+#define SPI_SR_BSY 0x00000080U /*!<Busy flag */
+#define SPI_SR_FRE 0x00000100U /*!<Frame format error flag */
+
+/******************** Bit definition for SPI_DR register ********************/
+#define SPI_DR_DR 0x0000FFFFU /*!<Data Register */
+
+/******************* Bit definition for SPI_CRCPR register ******************/
+#define SPI_CRCPR_CRCPOLY 0x0000FFFFU /*!<CRC polynomial register */
+
+/****************** Bit definition for SPI_RXCRCR register ******************/
+#define SPI_RXCRCR_RXCRC 0x0000FFFFU /*!<Rx CRC Register */
+
+/****************** Bit definition for SPI_TXCRCR register ******************/
+#define SPI_TXCRCR_TXCRC 0x0000FFFFU /*!<Tx CRC Register */
+
+/****************** Bit definition for SPI_I2SCFGR register *****************/
+#define SPI_I2SCFGR_CHLEN 0x00000001U /*!<Channel length (number of bits per audio channel) */
+
+#define SPI_I2SCFGR_DATLEN 0x00000006U /*!<DATLEN[1:0] bits (Data length to be transferred) */
+#define SPI_I2SCFGR_DATLEN_0 0x00000002U /*!<Bit 0 */
+#define SPI_I2SCFGR_DATLEN_1 0x00000004U /*!<Bit 1 */
+
+#define SPI_I2SCFGR_CKPOL 0x00000008U /*!<steady state clock polarity */
+
+#define SPI_I2SCFGR_I2SSTD 0x00000030U /*!<I2SSTD[1:0] bits (I2S standard selection) */
+#define SPI_I2SCFGR_I2SSTD_0 0x00000010U /*!<Bit 0 */
+#define SPI_I2SCFGR_I2SSTD_1 0x00000020U /*!<Bit 1 */
+
+#define SPI_I2SCFGR_PCMSYNC 0x00000080U /*!<PCM frame synchronization */
+
+#define SPI_I2SCFGR_I2SCFG 0x00000300U /*!<I2SCFG[1:0] bits (I2S configuration mode) */
+#define SPI_I2SCFGR_I2SCFG_0 0x00000100U /*!<Bit 0 */
+#define SPI_I2SCFGR_I2SCFG_1 0x00000200U /*!<Bit 1 */
+
+#define SPI_I2SCFGR_I2SE 0x00000400U /*!<I2S Enable */
+#define SPI_I2SCFGR_I2SMOD 0x00000800U /*!<I2S mode selection */
+
+/****************** Bit definition for SPI_I2SPR register *******************/
+#define SPI_I2SPR_I2SDIV 0x000000FFU /*!<I2S Linear prescaler */
+#define SPI_I2SPR_ODD 0x00000100U /*!<Odd factor for the prescaler */
+#define SPI_I2SPR_MCKOE 0x00000200U /*!<Master Clock Output Enable */
+
+/******************************************************************************/
+/* */
+/* SYSCFG */
+/* */
+/******************************************************************************/
+/****************** Bit definition for SYSCFG_MEMRMP register ***************/
+#define SYSCFG_MEMRMP_MEM_MODE 0x00000007U /*!< SYSCFG_Memory Remap Config */
+#define SYSCFG_MEMRMP_MEM_MODE_0 0x00000001U
+#define SYSCFG_MEMRMP_MEM_MODE_1 0x00000002U
+#define SYSCFG_MEMRMP_MEM_MODE_2 0x00000004U
+
+/****************** Bit definition for SYSCFG_PMC register ******************/
+#define SYSCFG_PMC_ADC1DC2 0x00010000U /*!< Refer to AN4073 on how to use this bit */
+
+/***************** Bit definition for SYSCFG_EXTICR1 register ***************/
+#define SYSCFG_EXTICR1_EXTI0 0x000FU /*!<EXTI 0 configuration */
+#define SYSCFG_EXTICR1_EXTI1 0x00F0U /*!<EXTI 1 configuration */
+#define SYSCFG_EXTICR1_EXTI2 0x0F00U /*!<EXTI 2 configuration */
+#define SYSCFG_EXTICR1_EXTI3 0xF000U /*!<EXTI 3 configuration */
+/**
+ * @brief EXTI0 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI0_PA 0x0000U /*!<PA[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PB 0x0001U /*!<PB[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PC 0x0002U /*!<PC[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PD 0x0003U /*!<PD[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PE 0x0004U /*!<PE[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PH 0x0007U /*!<PH[0] pin */
+
+/**
+ * @brief EXTI1 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI1_PA 0x0000U /*!<PA[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PB 0x0010U /*!<PB[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PC 0x0020U /*!<PC[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PD 0x0030U /*!<PD[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PE 0x0040U /*!<PE[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PH 0x0070U /*!<PH[1] pin */
+
+/**
+ * @brief EXTI2 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI2_PA 0x0000U /*!<PA[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PB 0x0100U /*!<PB[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PC 0x0200U /*!<PC[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PD 0x0300U /*!<PD[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PE 0x0400U /*!<PE[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PH 0x0700U /*!<PH[2] pin */
+
+/**
+ * @brief EXTI3 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI3_PA 0x0000U /*!<PA[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PB 0x1000U /*!<PB[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PC 0x2000U /*!<PC[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PD 0x3000U /*!<PD[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PE 0x4000U /*!<PE[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PH 0x7000U /*!<PH[3] pin */
+
+/***************** Bit definition for SYSCFG_EXTICR2 register ***************/
+#define SYSCFG_EXTICR2_EXTI4 0x000FU /*!<EXTI 4 configuration */
+#define SYSCFG_EXTICR2_EXTI5 0x00F0U /*!<EXTI 5 configuration */
+#define SYSCFG_EXTICR2_EXTI6 0x0F00U /*!<EXTI 6 configuration */
+#define SYSCFG_EXTICR2_EXTI7 0xF000U /*!<EXTI 7 configuration */
+/**
+ * @brief EXTI4 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI4_PA 0x0000U /*!<PA[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PB 0x0001U /*!<PB[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PC 0x0002U /*!<PC[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PD 0x0003U /*!<PD[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PE 0x0004U /*!<PE[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PH 0x0007U /*!<PH[4] pin */
+
+/**
+ * @brief EXTI5 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI5_PA 0x0000U /*!<PA[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PB 0x0010U /*!<PB[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PC 0x0020U /*!<PC[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PD 0x0030U /*!<PD[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PE 0x0040U /*!<PE[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PH 0x0070U /*!<PH[5] pin */
+
+/**
+ * @brief EXTI6 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI6_PA 0x0000U /*!<PA[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PB 0x0100U /*!<PB[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PC 0x0200U /*!<PC[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PD 0x0300U /*!<PD[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PE 0x0400U /*!<PE[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PH 0x0700U /*!<PH[6] pin */
+
+/**
+ * @brief EXTI7 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI7_PA 0x0000U /*!<PA[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PB 0x1000U /*!<PB[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PC 0x2000U /*!<PC[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PD 0x3000U /*!<PD[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PE 0x4000U /*!<PE[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PH 0x7000U /*!<PH[7] pin */
+
+
+/***************** Bit definition for SYSCFG_EXTICR3 register ***************/
+#define SYSCFG_EXTICR3_EXTI8 0x000FU /*!<EXTI 8 configuration */
+#define SYSCFG_EXTICR3_EXTI9 0x00F0U /*!<EXTI 9 configuration */
+#define SYSCFG_EXTICR3_EXTI10 0x0F00U /*!<EXTI 10 configuration */
+#define SYSCFG_EXTICR3_EXTI11 0xF000U /*!<EXTI 11 configuration */
+
+/**
+ * @brief EXTI8 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI8_PA 0x0000U /*!<PA[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PB 0x0001U /*!<PB[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PC 0x0002U /*!<PC[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PD 0x0003U /*!<PD[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PE 0x0004U /*!<PE[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PH 0x0007U /*!<PH[8] pin */
+
+/**
+ * @brief EXTI9 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI9_PA 0x0000U /*!<PA[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PB 0x0010U /*!<PB[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PC 0x0020U /*!<PC[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PD 0x0030U /*!<PD[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PE 0x0040U /*!<PE[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PH 0x0070U /*!<PH[9] pin */
+
+/**
+ * @brief EXTI10 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI10_PA 0x0000U /*!<PA[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PB 0x0100U /*!<PB[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PC 0x0200U /*!<PC[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PD 0x0300U /*!<PD[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PE 0x0400U /*!<PE[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PH 0x0700U /*!<PH[10] pin */
+
+/**
+ * @brief EXTI11 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI11_PA 0x0000U /*!<PA[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PB 0x1000U /*!<PB[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PC 0x2000U /*!<PC[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PD 0x3000U /*!<PD[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PE 0x4000U /*!<PE[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PH 0x7000U /*!<PH[11] pin */
+
+/***************** Bit definition for SYSCFG_EXTICR4 register ***************/
+#define SYSCFG_EXTICR4_EXTI12 0x000FU /*!<EXTI 12 configuration */
+#define SYSCFG_EXTICR4_EXTI13 0x00F0U /*!<EXTI 13 configuration */
+#define SYSCFG_EXTICR4_EXTI14 0x0F00U /*!<EXTI 14 configuration */
+#define SYSCFG_EXTICR4_EXTI15 0xF000U /*!<EXTI 15 configuration */
+/**
+ * @brief EXTI12 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI12_PA 0x0000U /*!<PA[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PB 0x0001U /*!<PB[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PC 0x0002U /*!<PC[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PD 0x0003U /*!<PD[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PE 0x0004U /*!<PE[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PH 0x0007U /*!<PH[12] pin */
+
+/**
+ * @brief EXTI13 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI13_PA 0x0000U /*!<PA[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PB 0x0010U /*!<PB[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PC 0x0020U /*!<PC[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PD 0x0030U /*!<PD[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PE 0x0040U /*!<PE[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PH 0x0070U /*!<PH[13] pin */
+
+/**
+ * @brief EXTI14 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI14_PA 0x0000U /*!<PA[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PB 0x0100U /*!<PB[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PC 0x0200U /*!<PC[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PD 0x0300U /*!<PD[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PE 0x0400U /*!<PE[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PH 0x0700U /*!<PH[14] pin */
+
+/**
+ * @brief EXTI15 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI15_PA 0x0000U /*!<PA[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PB 0x1000U /*!<PB[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PC 0x2000U /*!<PC[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PD 0x3000U /*!<PD[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PE 0x4000U /*!<PE[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PH 0x7000U /*!<PH[15] pin */
+
+/****************** Bit definition for SYSCFG_CMPCR register ****************/
+#define SYSCFG_CMPCR_CMP_PD 0x00000001U /*!<Compensation cell ready flag */
+#define SYSCFG_CMPCR_READY 0x00000100U /*!<Compensation cell power-down */
+
+/******************************************************************************/
+/* */
+/* TIM */
+/* */
+/******************************************************************************/
+/******************* Bit definition for TIM_CR1 register ********************/
+#define TIM_CR1_CEN 0x0001U /*!<Counter enable */
+#define TIM_CR1_UDIS 0x0002U /*!<Update disable */
+#define TIM_CR1_URS 0x0004U /*!<Update request source */
+#define TIM_CR1_OPM 0x0008U /*!<One pulse mode */
+#define TIM_CR1_DIR 0x0010U /*!<Direction */
+
+#define TIM_CR1_CMS 0x0060U /*!<CMS[1:0] bits (Center-aligned mode selection) */
+#define TIM_CR1_CMS_0 0x0020U /*!<Bit 0 */
+#define TIM_CR1_CMS_1 0x0040U /*!<Bit 1 */
+
+#define TIM_CR1_ARPE 0x0080U /*!<Auto-reload preload enable */
+
+#define TIM_CR1_CKD 0x0300U /*!<CKD[1:0] bits (clock division) */
+#define TIM_CR1_CKD_0 0x0100U /*!<Bit 0 */
+#define TIM_CR1_CKD_1 0x0200U /*!<Bit 1 */
+
+/******************* Bit definition for TIM_CR2 register ********************/
+#define TIM_CR2_CCPC 0x0001U /*!<Capture/Compare Preloaded Control */
+#define TIM_CR2_CCUS 0x0004U /*!<Capture/Compare Control Update Selection */
+#define TIM_CR2_CCDS 0x0008U /*!<Capture/Compare DMA Selection */
+
+#define TIM_CR2_MMS 0x0070U /*!<MMS[2:0] bits (Master Mode Selection) */
+#define TIM_CR2_MMS_0 0x0010U /*!<Bit 0 */
+#define TIM_CR2_MMS_1 0x0020U /*!<Bit 1 */
+#define TIM_CR2_MMS_2 0x0040U /*!<Bit 2 */
+
+#define TIM_CR2_TI1S 0x0080U /*!<TI1 Selection */
+#define TIM_CR2_OIS1 0x0100U /*!<Output Idle state 1 (OC1 output) */
+#define TIM_CR2_OIS1N 0x0200U /*!<Output Idle state 1 (OC1N output) */
+#define TIM_CR2_OIS2 0x0400U /*!<Output Idle state 2 (OC2 output) */
+#define TIM_CR2_OIS2N 0x0800U /*!<Output Idle state 2 (OC2N output) */
+#define TIM_CR2_OIS3 0x1000U /*!<Output Idle state 3 (OC3 output) */
+#define TIM_CR2_OIS3N 0x2000U /*!<Output Idle state 3 (OC3N output) */
+#define TIM_CR2_OIS4 0x4000U /*!<Output Idle state 4 (OC4 output) */
+
+/******************* Bit definition for TIM_SMCR register *******************/
+#define TIM_SMCR_SMS 0x0007U /*!<SMS[2:0] bits (Slave mode selection) */
+#define TIM_SMCR_SMS_0 0x0001U /*!<Bit 0 */
+#define TIM_SMCR_SMS_1 0x0002U /*!<Bit 1 */
+#define TIM_SMCR_SMS_2 0x0004U /*!<Bit 2 */
+
+#define TIM_SMCR_TS 0x0070U /*!<TS[2:0] bits (Trigger selection) */
+#define TIM_SMCR_TS_0 0x0010U /*!<Bit 0 */
+#define TIM_SMCR_TS_1 0x0020U /*!<Bit 1 */
+#define TIM_SMCR_TS_2 0x0040U /*!<Bit 2 */
+
+#define TIM_SMCR_MSM 0x0080U /*!<Master/slave mode */
+
+#define TIM_SMCR_ETF 0x0F00U /*!<ETF[3:0] bits (External trigger filter) */
+#define TIM_SMCR_ETF_0 0x0100U /*!<Bit 0 */
+#define TIM_SMCR_ETF_1 0x0200U /*!<Bit 1 */
+#define TIM_SMCR_ETF_2 0x0400U /*!<Bit 2 */
+#define TIM_SMCR_ETF_3 0x0800U /*!<Bit 3 */
+
+#define TIM_SMCR_ETPS 0x3000U /*!<ETPS[1:0] bits (External trigger prescaler) */
+#define TIM_SMCR_ETPS_0 0x1000U /*!<Bit 0 */
+#define TIM_SMCR_ETPS_1 0x2000U /*!<Bit 1 */
+
+#define TIM_SMCR_ECE 0x4000U /*!<External clock enable */
+#define TIM_SMCR_ETP 0x8000U /*!<External trigger polarity */
+
+/******************* Bit definition for TIM_DIER register *******************/
+#define TIM_DIER_UIE 0x0001U /*!<Update interrupt enable */
+#define TIM_DIER_CC1IE 0x0002U /*!<Capture/Compare 1 interrupt enable */
+#define TIM_DIER_CC2IE 0x0004U /*!<Capture/Compare 2 interrupt enable */
+#define TIM_DIER_CC3IE 0x0008U /*!<Capture/Compare 3 interrupt enable */
+#define TIM_DIER_CC4IE 0x0010U /*!<Capture/Compare 4 interrupt enable */
+#define TIM_DIER_COMIE 0x0020U /*!<COM interrupt enable */
+#define TIM_DIER_TIE 0x0040U /*!<Trigger interrupt enable */
+#define TIM_DIER_BIE 0x0080U /*!<Break interrupt enable */
+#define TIM_DIER_UDE 0x0100U /*!<Update DMA request enable */
+#define TIM_DIER_CC1DE 0x0200U /*!<Capture/Compare 1 DMA request enable */
+#define TIM_DIER_CC2DE 0x0400U /*!<Capture/Compare 2 DMA request enable */
+#define TIM_DIER_CC3DE 0x0800U /*!<Capture/Compare 3 DMA request enable */
+#define TIM_DIER_CC4DE 0x1000U /*!<Capture/Compare 4 DMA request enable */
+#define TIM_DIER_COMDE 0x2000U /*!<COM DMA request enable */
+#define TIM_DIER_TDE 0x4000U /*!<Trigger DMA request enable */
+
+/******************** Bit definition for TIM_SR register ********************/
+#define TIM_SR_UIF 0x0001U /*!<Update interrupt Flag */
+#define TIM_SR_CC1IF 0x0002U /*!<Capture/Compare 1 interrupt Flag */
+#define TIM_SR_CC2IF 0x0004U /*!<Capture/Compare 2 interrupt Flag */
+#define TIM_SR_CC3IF 0x0008U /*!<Capture/Compare 3 interrupt Flag */
+#define TIM_SR_CC4IF 0x0010U /*!<Capture/Compare 4 interrupt Flag */
+#define TIM_SR_COMIF 0x0020U /*!<COM interrupt Flag */
+#define TIM_SR_TIF 0x0040U /*!<Trigger interrupt Flag */
+#define TIM_SR_BIF 0x0080U /*!<Break interrupt Flag */
+#define TIM_SR_CC1OF 0x0200U /*!<Capture/Compare 1 Overcapture Flag */
+#define TIM_SR_CC2OF 0x0400U /*!<Capture/Compare 2 Overcapture Flag */
+#define TIM_SR_CC3OF 0x0800U /*!<Capture/Compare 3 Overcapture Flag */
+#define TIM_SR_CC4OF 0x1000U /*!<Capture/Compare 4 Overcapture Flag */
+
+/******************* Bit definition for TIM_EGR register ********************/
+#define TIM_EGR_UG 0x01U /*!<Update Generation */
+#define TIM_EGR_CC1G 0x02U /*!<Capture/Compare 1 Generation */
+#define TIM_EGR_CC2G 0x04U /*!<Capture/Compare 2 Generation */
+#define TIM_EGR_CC3G 0x08U /*!<Capture/Compare 3 Generation */
+#define TIM_EGR_CC4G 0x10U /*!<Capture/Compare 4 Generation */
+#define TIM_EGR_COMG 0x20U /*!<Capture/Compare Control Update Generation */
+#define TIM_EGR_TG 0x40U /*!<Trigger Generation */
+#define TIM_EGR_BG 0x80U /*!<Break Generation */
+
+/****************** Bit definition for TIM_CCMR1 register *******************/
+#define TIM_CCMR1_CC1S 0x0003U /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
+#define TIM_CCMR1_CC1S_0 0x0001U /*!<Bit 0 */
+#define TIM_CCMR1_CC1S_1 0x0002U /*!<Bit 1 */
+
+#define TIM_CCMR1_OC1FE 0x0004U /*!<Output Compare 1 Fast enable */
+#define TIM_CCMR1_OC1PE 0x0008U /*!<Output Compare 1 Preload enable */
+
+#define TIM_CCMR1_OC1M 0x0070U /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
+#define TIM_CCMR1_OC1M_0 0x0010U /*!<Bit 0 */
+#define TIM_CCMR1_OC1M_1 0x0020U /*!<Bit 1 */
+#define TIM_CCMR1_OC1M_2 0x0040U /*!<Bit 2 */
+
+#define TIM_CCMR1_OC1CE 0x0080U /*!<Output Compare 1Clear Enable */
+
+#define TIM_CCMR1_CC2S 0x0300U /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
+#define TIM_CCMR1_CC2S_0 0x0100U /*!<Bit 0 */
+#define TIM_CCMR1_CC2S_1 0x0200U /*!<Bit 1 */
+
+#define TIM_CCMR1_OC2FE 0x0400U /*!<Output Compare 2 Fast enable */
+#define TIM_CCMR1_OC2PE 0x0800U /*!<Output Compare 2 Preload enable */
+
+#define TIM_CCMR1_OC2M 0x7000U /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
+#define TIM_CCMR1_OC2M_0 0x1000U /*!<Bit 0 */
+#define TIM_CCMR1_OC2M_1 0x2000U /*!<Bit 1 */
+#define TIM_CCMR1_OC2M_2 0x4000U /*!<Bit 2 */
+
+#define TIM_CCMR1_OC2CE 0x8000U /*!<Output Compare 2 Clear Enable */
+
+/*----------------------------------------------------------------------------*/
+
+#define TIM_CCMR1_IC1PSC 0x000CU /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
+#define TIM_CCMR1_IC1PSC_0 0x0004U /*!<Bit 0 */
+#define TIM_CCMR1_IC1PSC_1 0x0008U /*!<Bit 1 */
+
+#define TIM_CCMR1_IC1F 0x00F0U /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
+#define TIM_CCMR1_IC1F_0 0x0010U /*!<Bit 0 */
+#define TIM_CCMR1_IC1F_1 0x0020U /*!<Bit 1 */
+#define TIM_CCMR1_IC1F_2 0x0040U /*!<Bit 2 */
+#define TIM_CCMR1_IC1F_3 0x0080U /*!<Bit 3 */
+
+#define TIM_CCMR1_IC2PSC 0x0C00U /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
+#define TIM_CCMR1_IC2PSC_0 0x0400U /*!<Bit 0 */
+#define TIM_CCMR1_IC2PSC_1 0x0800U /*!<Bit 1 */
+
+#define TIM_CCMR1_IC2F 0xF000U /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
+#define TIM_CCMR1_IC2F_0 0x1000U /*!<Bit 0 */
+#define TIM_CCMR1_IC2F_1 0x2000U /*!<Bit 1 */
+#define TIM_CCMR1_IC2F_2 0x4000U /*!<Bit 2 */
+#define TIM_CCMR1_IC2F_3 0x8000U /*!<Bit 3 */
+
+/****************** Bit definition for TIM_CCMR2 register *******************/
+#define TIM_CCMR2_CC3S 0x0003U /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
+#define TIM_CCMR2_CC3S_0 0x0001U /*!<Bit 0 */
+#define TIM_CCMR2_CC3S_1 0x0002U /*!<Bit 1 */
+
+#define TIM_CCMR2_OC3FE 0x0004U /*!<Output Compare 3 Fast enable */
+#define TIM_CCMR2_OC3PE 0x0008U /*!<Output Compare 3 Preload enable */
+
+#define TIM_CCMR2_OC3M 0x0070U /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
+#define TIM_CCMR2_OC3M_0 0x0010U /*!<Bit 0 */
+#define TIM_CCMR2_OC3M_1 0x0020U /*!<Bit 1 */
+#define TIM_CCMR2_OC3M_2 0x0040U /*!<Bit 2 */
+
+#define TIM_CCMR2_OC3CE 0x0080U /*!<Output Compare 3 Clear Enable */
+
+#define TIM_CCMR2_CC4S 0x0300U /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
+#define TIM_CCMR2_CC4S_0 0x0100U /*!<Bit 0 */
+#define TIM_CCMR2_CC4S_1 0x0200U /*!<Bit 1 */
+
+#define TIM_CCMR2_OC4FE 0x0400U /*!<Output Compare 4 Fast enable */
+#define TIM_CCMR2_OC4PE 0x0800U /*!<Output Compare 4 Preload enable */
+
+#define TIM_CCMR2_OC4M 0x7000U /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
+#define TIM_CCMR2_OC4M_0 0x1000U /*!<Bit 0 */
+#define TIM_CCMR2_OC4M_1 0x2000U /*!<Bit 1 */
+#define TIM_CCMR2_OC4M_2 0x4000U /*!<Bit 2 */
+
+#define TIM_CCMR2_OC4CE 0x8000U /*!<Output Compare 4 Clear Enable */
+
+/*----------------------------------------------------------------------------*/
+
+#define TIM_CCMR2_IC3PSC 0x000CU /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
+#define TIM_CCMR2_IC3PSC_0 0x0004U /*!<Bit 0 */
+#define TIM_CCMR2_IC3PSC_1 0x0008U /*!<Bit 1 */
+
+#define TIM_CCMR2_IC3F 0x00F0U /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
+#define TIM_CCMR2_IC3F_0 0x0010U /*!<Bit 0 */
+#define TIM_CCMR2_IC3F_1 0x0020U /*!<Bit 1 */
+#define TIM_CCMR2_IC3F_2 0x0040U /*!<Bit 2 */
+#define TIM_CCMR2_IC3F_3 0x0080U /*!<Bit 3 */
+
+#define TIM_CCMR2_IC4PSC 0x0C00U /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
+#define TIM_CCMR2_IC4PSC_0 0x0400U /*!<Bit 0 */
+#define TIM_CCMR2_IC4PSC_1 0x0800U /*!<Bit 1 */
+
+#define TIM_CCMR2_IC4F 0xF000U /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
+#define TIM_CCMR2_IC4F_0 0x1000U /*!<Bit 0 */
+#define TIM_CCMR2_IC4F_1 0x2000U /*!<Bit 1 */
+#define TIM_CCMR2_IC4F_2 0x4000U /*!<Bit 2 */
+#define TIM_CCMR2_IC4F_3 0x8000U /*!<Bit 3 */
+
+/******************* Bit definition for TIM_CCER register *******************/
+#define TIM_CCER_CC1E 0x0001U /*!<Capture/Compare 1 output enable */
+#define TIM_CCER_CC1P 0x0002U /*!<Capture/Compare 1 output Polarity */
+#define TIM_CCER_CC1NE 0x0004U /*!<Capture/Compare 1 Complementary output enable */
+#define TIM_CCER_CC1NP 0x0008U /*!<Capture/Compare 1 Complementary output Polarity */
+#define TIM_CCER_CC2E 0x0010U /*!<Capture/Compare 2 output enable */
+#define TIM_CCER_CC2P 0x0020U /*!<Capture/Compare 2 output Polarity */
+#define TIM_CCER_CC2NE 0x0040U /*!<Capture/Compare 2 Complementary output enable */
+#define TIM_CCER_CC2NP 0x0080U /*!<Capture/Compare 2 Complementary output Polarity */
+#define TIM_CCER_CC3E 0x0100U /*!<Capture/Compare 3 output enable */
+#define TIM_CCER_CC3P 0x0200U /*!<Capture/Compare 3 output Polarity */
+#define TIM_CCER_CC3NE 0x0400U /*!<Capture/Compare 3 Complementary output enable */
+#define TIM_CCER_CC3NP 0x0800U /*!<Capture/Compare 3 Complementary output Polarity */
+#define TIM_CCER_CC4E 0x1000U /*!<Capture/Compare 4 output enable */
+#define TIM_CCER_CC4P 0x2000U /*!<Capture/Compare 4 output Polarity */
+#define TIM_CCER_CC4NP 0x8000U /*!<Capture/Compare 4 Complementary output Polarity */
+
+/******************* Bit definition for TIM_CNT register ********************/
+#define TIM_CNT_CNT 0xFFFFU /*!<Counter Value */
+
+/******************* Bit definition for TIM_PSC register ********************/
+#define TIM_PSC_PSC 0xFFFFU /*!<Prescaler Value */
+
+/******************* Bit definition for TIM_ARR register ********************/
+#define TIM_ARR_ARR 0xFFFFU /*!<actual auto-reload Value */
+
+/******************* Bit definition for TIM_RCR register ********************/
+#define TIM_RCR_REP 0xFFU /*!<Repetition Counter Value */
+
+/******************* Bit definition for TIM_CCR1 register *******************/
+#define TIM_CCR1_CCR1 0xFFFFU /*!<Capture/Compare 1 Value */
+
+/******************* Bit definition for TIM_CCR2 register *******************/
+#define TIM_CCR2_CCR2 0xFFFFU /*!<Capture/Compare 2 Value */
+
+/******************* Bit definition for TIM_CCR3 register *******************/
+#define TIM_CCR3_CCR3 0xFFFFU /*!<Capture/Compare 3 Value */
+
+/******************* Bit definition for TIM_CCR4 register *******************/
+#define TIM_CCR4_CCR4 0xFFFFU /*!<Capture/Compare 4 Value */
+
+/******************* Bit definition for TIM_BDTR register *******************/
+#define TIM_BDTR_DTG 0x00FFU /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
+#define TIM_BDTR_DTG_0 0x0001U /*!<Bit 0 */
+#define TIM_BDTR_DTG_1 0x0002U /*!<Bit 1 */
+#define TIM_BDTR_DTG_2 0x0004U /*!<Bit 2 */
+#define TIM_BDTR_DTG_3 0x0008U /*!<Bit 3 */
+#define TIM_BDTR_DTG_4 0x0010U /*!<Bit 4 */
+#define TIM_BDTR_DTG_5 0x0020U /*!<Bit 5 */
+#define TIM_BDTR_DTG_6 0x0040U /*!<Bit 6 */
+#define TIM_BDTR_DTG_7 0x0080U /*!<Bit 7 */
+
+#define TIM_BDTR_LOCK 0x0300U /*!<LOCK[1:0] bits (Lock Configuration) */
+#define TIM_BDTR_LOCK_0 0x0100U /*!<Bit 0 */
+#define TIM_BDTR_LOCK_1 0x0200U /*!<Bit 1 */
+
+#define TIM_BDTR_OSSI 0x0400U /*!<Off-State Selection for Idle mode */
+#define TIM_BDTR_OSSR 0x0800U /*!<Off-State Selection for Run mode */
+#define TIM_BDTR_BKE 0x1000U /*!<Break enable */
+#define TIM_BDTR_BKP 0x2000U /*!<Break Polarity */
+#define TIM_BDTR_AOE 0x4000U /*!<Automatic Output enable */
+#define TIM_BDTR_MOE 0x8000U /*!<Main Output enable */
+
+/******************* Bit definition for TIM_DCR register ********************/
+#define TIM_DCR_DBA 0x001FU /*!<DBA[4:0] bits (DMA Base Address) */
+#define TIM_DCR_DBA_0 0x0001U /*!<Bit 0 */
+#define TIM_DCR_DBA_1 0x0002U /*!<Bit 1 */
+#define TIM_DCR_DBA_2 0x0004U /*!<Bit 2 */
+#define TIM_DCR_DBA_3 0x0008U /*!<Bit 3 */
+#define TIM_DCR_DBA_4 0x0010U /*!<Bit 4 */
+
+#define TIM_DCR_DBL 0x1F00U /*!<DBL[4:0] bits (DMA Burst Length) */
+#define TIM_DCR_DBL_0 0x0100U /*!<Bit 0 */
+#define TIM_DCR_DBL_1 0x0200U /*!<Bit 1 */
+#define TIM_DCR_DBL_2 0x0400U /*!<Bit 2 */
+#define TIM_DCR_DBL_3 0x0800U /*!<Bit 3 */
+#define TIM_DCR_DBL_4 0x1000U /*!<Bit 4 */
+
+/******************* Bit definition for TIM_DMAR register *******************/
+#define TIM_DMAR_DMAB 0xFFFFU /*!<DMA register for burst accesses */
+
+/******************* Bit definition for TIM_OR register *********************/
+#define TIM_OR_TI4_RMP 0x00C0U /*!<TI4_RMP[1:0] bits (TIM5 Input 4 remap) */
+#define TIM_OR_TI4_RMP_0 0x0040U /*!<Bit 0 */
+#define TIM_OR_TI4_RMP_1 0x0080U /*!<Bit 1 */
+#define TIM_OR_ITR1_RMP 0x0C00U /*!<ITR1_RMP[1:0] bits (TIM2 Internal trigger 1 remap) */
+#define TIM_OR_ITR1_RMP_0 0x0400U /*!<Bit 0 */
+#define TIM_OR_ITR1_RMP_1 0x0800U /*!<Bit 1 */
+
+
+/******************************************************************************/
+/* */
+/* Universal Synchronous Asynchronous Receiver Transmitter */
+/* */
+/******************************************************************************/
+/******************* Bit definition for USART_SR register *******************/
+#define USART_SR_PE 0x0001U /*!<Parity Error */
+#define USART_SR_FE 0x0002U /*!<Framing Error */
+#define USART_SR_NE 0x0004U /*!<Noise Error Flag */
+#define USART_SR_ORE 0x0008U /*!<OverRun Error */
+#define USART_SR_IDLE 0x0010U /*!<IDLE line detected */
+#define USART_SR_RXNE 0x0020U /*!<Read Data Register Not Empty */
+#define USART_SR_TC 0x0040U /*!<Transmission Complete */
+#define USART_SR_TXE 0x0080U /*!<Transmit Data Register Empty */
+#define USART_SR_LBD 0x0100U /*!<LIN Break Detection Flag */
+#define USART_SR_CTS 0x0200U /*!<CTS Flag */
+
+/******************* Bit definition for USART_DR register *******************/
+#define USART_DR_DR 0x01FFU /*!<Data value */
+
+/****************** Bit definition for USART_BRR register *******************/
+#define USART_BRR_DIV_Fraction 0x000FU /*!<Fraction of USARTDIV */
+#define USART_BRR_DIV_Mantissa 0xFFF0U /*!<Mantissa of USARTDIV */
+
+/****************** Bit definition for USART_CR1 register *******************/
+#define USART_CR1_SBK 0x0001U /*!<Send Break */
+#define USART_CR1_RWU 0x0002U /*!<Receiver wakeup */
+#define USART_CR1_RE 0x0004U /*!<Receiver Enable */
+#define USART_CR1_TE 0x0008U /*!<Transmitter Enable */
+#define USART_CR1_IDLEIE 0x0010U /*!<IDLE Interrupt Enable */
+#define USART_CR1_RXNEIE 0x0020U /*!<RXNE Interrupt Enable */
+#define USART_CR1_TCIE 0x0040U /*!<Transmission Complete Interrupt Enable */
+#define USART_CR1_TXEIE 0x0080U /*!<PE Interrupt Enable */
+#define USART_CR1_PEIE 0x0100U /*!<PE Interrupt Enable */
+#define USART_CR1_PS 0x0200U /*!<Parity Selection */
+#define USART_CR1_PCE 0x0400U /*!<Parity Control Enable */
+#define USART_CR1_WAKE 0x0800U /*!<Wakeup method */
+#define USART_CR1_M 0x1000U /*!<Word length */
+#define USART_CR1_UE 0x2000U /*!<USART Enable */
+#define USART_CR1_OVER8 0x8000U /*!<USART Oversampling by 8 enable */
+
+/****************** Bit definition for USART_CR2 register *******************/
+#define USART_CR2_ADD 0x000FU /*!<Address of the USART node */
+#define USART_CR2_LBDL 0x0020U /*!<LIN Break Detection Length */
+#define USART_CR2_LBDIE 0x0040U /*!<LIN Break Detection Interrupt Enable */
+#define USART_CR2_LBCL 0x0100U /*!<Last Bit Clock pulse */
+#define USART_CR2_CPHA 0x0200U /*!<Clock Phase */
+#define USART_CR2_CPOL 0x0400U /*!<Clock Polarity */
+#define USART_CR2_CLKEN 0x0800U /*!<Clock Enable */
+
+#define USART_CR2_STOP 0x3000U /*!<STOP[1:0] bits (STOP bits) */
+#define USART_CR2_STOP_0 0x1000U /*!<Bit 0 */
+#define USART_CR2_STOP_1 0x2000U /*!<Bit 1 */
+
+#define USART_CR2_LINEN 0x4000U /*!<LIN mode enable */
+
+/****************** Bit definition for USART_CR3 register *******************/
+#define USART_CR3_EIE 0x0001U /*!<Error Interrupt Enable */
+#define USART_CR3_IREN 0x0002U /*!<IrDA mode Enable */
+#define USART_CR3_IRLP 0x0004U /*!<IrDA Low-Power */
+#define USART_CR3_HDSEL 0x0008U /*!<Half-Duplex Selection */
+#define USART_CR3_NACK 0x0010U /*!<Smartcard NACK enable */
+#define USART_CR3_SCEN 0x0020U /*!<Smartcard mode enable */
+#define USART_CR3_DMAR 0x0040U /*!<DMA Enable Receiver */
+#define USART_CR3_DMAT 0x0080U /*!<DMA Enable Transmitter */
+#define USART_CR3_RTSE 0x0100U /*!<RTS Enable */
+#define USART_CR3_CTSE 0x0200U /*!<CTS Enable */
+#define USART_CR3_CTSIE 0x0400U /*!<CTS Interrupt Enable */
+#define USART_CR3_ONEBIT 0x0800U /*!<USART One bit method enable */
+
+/****************** Bit definition for USART_GTPR register ******************/
+#define USART_GTPR_PSC 0x00FFU /*!<PSC[7:0] bits (Prescaler value) */
+#define USART_GTPR_PSC_0 0x0001U /*!<Bit 0 */
+#define USART_GTPR_PSC_1 0x0002U /*!<Bit 1 */
+#define USART_GTPR_PSC_2 0x0004U /*!<Bit 2 */
+#define USART_GTPR_PSC_3 0x0008U /*!<Bit 3 */
+#define USART_GTPR_PSC_4 0x0010U /*!<Bit 4 */
+#define USART_GTPR_PSC_5 0x0020U /*!<Bit 5 */
+#define USART_GTPR_PSC_6 0x0040U /*!<Bit 6 */
+#define USART_GTPR_PSC_7 0x0080U /*!<Bit 7 */
+
+#define USART_GTPR_GT 0xFF00U /*!<Guard time value */
+
+/******************************************************************************/
+/* */
+/* Window WATCHDOG */
+/* */
+/******************************************************************************/
+/******************* Bit definition for WWDG_CR register ********************/
+#define WWDG_CR_T 0x7FU /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
+#define WWDG_CR_T_0 0x01U /*!<Bit 0 */
+#define WWDG_CR_T_1 0x02U /*!<Bit 1 */
+#define WWDG_CR_T_2 0x04U /*!<Bit 2 */
+#define WWDG_CR_T_3 0x08U /*!<Bit 3 */
+#define WWDG_CR_T_4 0x10U /*!<Bit 4 */
+#define WWDG_CR_T_5 0x20U /*!<Bit 5 */
+#define WWDG_CR_T_6 0x40U /*!<Bit 6 */
+/* Legacy defines */
+#define WWDG_CR_T0 WWDG_CR_T_0
+#define WWDG_CR_T1 WWDG_CR_T_1
+#define WWDG_CR_T2 WWDG_CR_T_2
+#define WWDG_CR_T3 WWDG_CR_T_3
+#define WWDG_CR_T4 WWDG_CR_T_4
+#define WWDG_CR_T5 WWDG_CR_T_5
+#define WWDG_CR_T6 WWDG_CR_T_6
+
+#define WWDG_CR_WDGA 0x80U /*!<Activation bit */
+
+/******************* Bit definition for WWDG_CFR register *******************/
+#define WWDG_CFR_W 0x007FU /*!<W[6:0] bits (7-bit window value) */
+#define WWDG_CFR_W_0 0x0001U /*!<Bit 0 */
+#define WWDG_CFR_W_1 0x0002U /*!<Bit 1 */
+#define WWDG_CFR_W_2 0x0004U /*!<Bit 2 */
+#define WWDG_CFR_W_3 0x0008U /*!<Bit 3 */
+#define WWDG_CFR_W_4 0x0010U /*!<Bit 4 */
+#define WWDG_CFR_W_5 0x0020U /*!<Bit 5 */
+#define WWDG_CFR_W_6 0x0040U /*!<Bit 6 */
+/* Legacy defines */
+#define WWDG_CFR_W0 WWDG_CFR_W_0
+#define WWDG_CFR_W1 WWDG_CFR_W_1
+#define WWDG_CFR_W2 WWDG_CFR_W_2
+#define WWDG_CFR_W3 WWDG_CFR_W_3
+#define WWDG_CFR_W4 WWDG_CFR_W_4
+#define WWDG_CFR_W5 WWDG_CFR_W_5
+#define WWDG_CFR_W6 WWDG_CFR_W_6
+
+#define WWDG_CFR_WDGTB 0x0180U /*!<WDGTB[1:0] bits (Timer Base) */
+#define WWDG_CFR_WDGTB_0 0x0080U /*!<Bit 0 */
+#define WWDG_CFR_WDGTB_1 0x0100U /*!<Bit 1 */
+/* Legacy defines */
+#define WWDG_CFR_WDGTB0 WWDG_CFR_WDGTB_0
+#define WWDG_CFR_WDGTB1 WWDG_CFR_WDGTB_1
+
+#define WWDG_CFR_EWI 0x0200U /*!<Early Wakeup Interrupt */
+
+/******************* Bit definition for WWDG_SR register ********************/
+#define WWDG_SR_EWIF 0x01U /*!<Early Wakeup Interrupt Flag */
+
+
+/******************************************************************************/
+/* */
+/* DBG */
+/* */
+/******************************************************************************/
+/******************** Bit definition for DBGMCU_IDCODE register *************/
+#define DBGMCU_IDCODE_DEV_ID 0x00000FFFU
+#define DBGMCU_IDCODE_REV_ID 0xFFFF0000U
+
+/******************** Bit definition for DBGMCU_CR register *****************/
+#define DBGMCU_CR_DBG_SLEEP 0x00000001U
+#define DBGMCU_CR_DBG_STOP 0x00000002U
+#define DBGMCU_CR_DBG_STANDBY 0x00000004U
+#define DBGMCU_CR_TRACE_IOEN 0x00000020U
+
+#define DBGMCU_CR_TRACE_MODE 0x000000C0U
+#define DBGMCU_CR_TRACE_MODE_0 0x00000040U/*!<Bit 0 */
+#define DBGMCU_CR_TRACE_MODE_1 0x00000080U/*!<Bit 1 */
+
+/******************** Bit definition for DBGMCU_APB1_FZ register ************/
+#define DBGMCU_APB1_FZ_DBG_TIM2_STOP 0x00000001U
+#define DBGMCU_APB1_FZ_DBG_TIM3_STOP 0x00000002U
+#define DBGMCU_APB1_FZ_DBG_TIM4_STOP 0x00000004U
+#define DBGMCU_APB1_FZ_DBG_TIM5_STOP 0x00000008U
+#define DBGMCU_APB1_FZ_DBG_TIM6_STOP 0x00000010U
+#define DBGMCU_APB1_FZ_DBG_TIM7_STOP 0x00000020U
+#define DBGMCU_APB1_FZ_DBG_TIM12_STOP 0x00000040U
+#define DBGMCU_APB1_FZ_DBG_TIM13_STOP 0x00000080U
+#define DBGMCU_APB1_FZ_DBG_TIM14_STOP 0x00000100U
+#define DBGMCU_APB1_FZ_DBG_RTC_STOP 0x00000400U
+#define DBGMCU_APB1_FZ_DBG_WWDG_STOP 0x00000800U
+#define DBGMCU_APB1_FZ_DBG_IWDG_STOP 0x00001000U
+#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT 0x00200000U
+#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT 0x00400000U
+#define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT 0x00800000U
+#define DBGMCU_APB1_FZ_DBG_CAN1_STOP 0x02000000U
+#define DBGMCU_APB1_FZ_DBG_CAN2_STOP 0x04000000U
+/* Old IWDGSTOP bit definition, maintained for legacy purpose */
+#define DBGMCU_APB1_FZ_DBG_IWDEG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP
+
+/******************** Bit definition for DBGMCU_APB2_FZ register ************/
+#define DBGMCU_APB2_FZ_DBG_TIM1_STOP 0x00000001U
+#define DBGMCU_APB2_FZ_DBG_TIM8_STOP 0x00000002U
+#define DBGMCU_APB2_FZ_DBG_TIM9_STOP 0x00010000U
+#define DBGMCU_APB2_FZ_DBG_TIM10_STOP 0x00020000U
+#define DBGMCU_APB2_FZ_DBG_TIM11_STOP 0x00040000U
+
+/******************************************************************************/
+/* */
+/* USB_OTG */
+/* */
+/******************************************************************************/
+/******************** Bit definition forUSB_OTG_GOTGCTL register ********************/
+#define USB_OTG_GOTGCTL_SRQSCS 0x00000001U /*!< Session request success */
+#define USB_OTG_GOTGCTL_SRQ 0x00000002U /*!< Session request */
+#define USB_OTG_GOTGCTL_HNGSCS 0x00000100U /*!< Host negotiation success */
+#define USB_OTG_GOTGCTL_HNPRQ 0x00000200U /*!< HNP request */
+#define USB_OTG_GOTGCTL_HSHNPEN 0x00000400U /*!< Host set HNP enable */
+#define USB_OTG_GOTGCTL_DHNPEN 0x00000800U /*!< Device HNP enabled */
+#define USB_OTG_GOTGCTL_CIDSTS 0x00010000U /*!< Connector ID status */
+#define USB_OTG_GOTGCTL_DBCT 0x00020000U /*!< Long/short debounce time */
+#define USB_OTG_GOTGCTL_ASVLD 0x00040000U /*!< A-session valid */
+#define USB_OTG_GOTGCTL_BSVLD 0x00080000U /*!< B-session valid */
+
+/******************** Bit definition forUSB_OTG_HCFG register ********************/
+
+#define USB_OTG_HCFG_FSLSPCS 0x00000003U /*!< FS/LS PHY clock select */
+#define USB_OTG_HCFG_FSLSPCS_0 0x00000001U /*!<Bit 0 */
+#define USB_OTG_HCFG_FSLSPCS_1 0x00000002U /*!<Bit 1 */
+#define USB_OTG_HCFG_FSLSS 0x00000004U /*!< FS- and LS-only support */
+
+/******************** Bit definition forUSB_OTG_DCFG register ********************/
+
+#define USB_OTG_DCFG_DSPD 0x00000003U /*!< Device speed */
+#define USB_OTG_DCFG_DSPD_0 0x00000001U /*!<Bit 0 */
+#define USB_OTG_DCFG_DSPD_1 0x00000002U /*!<Bit 1 */
+#define USB_OTG_DCFG_NZLSOHSK 0x00000004U /*!< Nonzero-length status OUT handshake */
+
+#define USB_OTG_DCFG_DAD 0x000007F0U /*!< Device address */
+#define USB_OTG_DCFG_DAD_0 0x00000010U /*!<Bit 0 */
+#define USB_OTG_DCFG_DAD_1 0x00000020U /*!<Bit 1 */
+#define USB_OTG_DCFG_DAD_2 0x00000040U /*!<Bit 2 */
+#define USB_OTG_DCFG_DAD_3 0x00000080U /*!<Bit 3 */
+#define USB_OTG_DCFG_DAD_4 0x00000100U /*!<Bit 4 */
+#define USB_OTG_DCFG_DAD_5 0x00000200U /*!<Bit 5 */
+#define USB_OTG_DCFG_DAD_6 0x00000400U /*!<Bit 6 */
+
+#define USB_OTG_DCFG_PFIVL 0x00001800U /*!< Periodic (micro)frame interval */
+#define USB_OTG_DCFG_PFIVL_0 0x00000800U /*!<Bit 0 */
+#define USB_OTG_DCFG_PFIVL_1 0x00001000U /*!<Bit 1 */
+
+#define USB_OTG_DCFG_PERSCHIVL 0x03000000U /*!< Periodic scheduling interval */
+#define USB_OTG_DCFG_PERSCHIVL_0 0x01000000U /*!<Bit 0 */
+#define USB_OTG_DCFG_PERSCHIVL_1 0x02000000U /*!<Bit 1 */
+
+/******************** Bit definition forUSB_OTG_PCGCR register ********************/
+#define USB_OTG_PCGCR_STPPCLK 0x00000001U /*!< Stop PHY clock */
+#define USB_OTG_PCGCR_GATEHCLK 0x00000002U /*!< Gate HCLK */
+#define USB_OTG_PCGCR_PHYSUSP 0x00000010U /*!< PHY suspended */
+
+/******************** Bit definition forUSB_OTG_GOTGINT register ********************/
+#define USB_OTG_GOTGINT_SEDET 0x00000004U /*!< Session end detected */
+#define USB_OTG_GOTGINT_SRSSCHG 0x00000100U /*!< Session request success status change */
+#define USB_OTG_GOTGINT_HNSSCHG 0x00000200U /*!< Host negotiation success status change */
+#define USB_OTG_GOTGINT_HNGDET 0x00020000U /*!< Host negotiation detected */
+#define USB_OTG_GOTGINT_ADTOCHG 0x00040000U /*!< A-device timeout change */
+#define USB_OTG_GOTGINT_DBCDNE 0x00080000U /*!< Debounce done */
+
+/******************** Bit definition forUSB_OTG_DCTL register ********************/
+#define USB_OTG_DCTL_RWUSIG 0x00000001U /*!< Remote wakeup signaling */
+#define USB_OTG_DCTL_SDIS 0x00000002U /*!< Soft disconnect */
+#define USB_OTG_DCTL_GINSTS 0x00000004U /*!< Global IN NAK status */
+#define USB_OTG_DCTL_GONSTS 0x00000008U /*!< Global OUT NAK status */
+
+#define USB_OTG_DCTL_TCTL 0x00000070U /*!< Test control */
+#define USB_OTG_DCTL_TCTL_0 0x00000010U /*!<Bit 0 */
+#define USB_OTG_DCTL_TCTL_1 0x00000020U /*!<Bit 1 */
+#define USB_OTG_DCTL_TCTL_2 0x00000040U /*!<Bit 2 */
+#define USB_OTG_DCTL_SGINAK 0x00000080U /*!< Set global IN NAK */
+#define USB_OTG_DCTL_CGINAK 0x00000100U /*!< Clear global IN NAK */
+#define USB_OTG_DCTL_SGONAK 0x00000200U /*!< Set global OUT NAK */
+#define USB_OTG_DCTL_CGONAK 0x00000400U /*!< Clear global OUT NAK */
+#define USB_OTG_DCTL_POPRGDNE 0x00000800U /*!< Power-on programming done */
+
+/******************** Bit definition forUSB_OTG_HFIR register ********************/
+#define USB_OTG_HFIR_FRIVL 0x0000FFFFU /*!< Frame interval */
+
+/******************** Bit definition forUSB_OTG_HFNUM register ********************/
+#define USB_OTG_HFNUM_FRNUM 0x0000FFFFU /*!< Frame number */
+#define USB_OTG_HFNUM_FTREM 0xFFFF0000U /*!< Frame time remaining */
+
+/******************** Bit definition forUSB_OTG_DSTS register ********************/
+#define USB_OTG_DSTS_SUSPSTS 0x00000001U /*!< Suspend status */
+
+#define USB_OTG_DSTS_ENUMSPD 0x00000006U /*!< Enumerated speed */
+#define USB_OTG_DSTS_ENUMSPD_0 0x00000002U /*!<Bit 0 */
+#define USB_OTG_DSTS_ENUMSPD_1 0x00000004U /*!<Bit 1 */
+#define USB_OTG_DSTS_EERR 0x00000008U /*!< Erratic error */
+#define USB_OTG_DSTS_FNSOF 0x003FFF00U /*!< Frame number of the received SOF */
+
+/******************** Bit definition forUSB_OTG_GAHBCFG register ********************/
+#define USB_OTG_GAHBCFG_GINT 0x00000001U /*!< Global interrupt mask */
+
+#define USB_OTG_GAHBCFG_HBSTLEN 0x0000001EU /*!< Burst length/type */
+#define USB_OTG_GAHBCFG_HBSTLEN_0 0x00000002U /*!<Bit 0 */
+#define USB_OTG_GAHBCFG_HBSTLEN_1 0x00000004U /*!<Bit 1 */
+#define USB_OTG_GAHBCFG_HBSTLEN_2 0x00000008U /*!<Bit 2 */
+#define USB_OTG_GAHBCFG_HBSTLEN_3 0x00000010U /*!<Bit 3 */
+#define USB_OTG_GAHBCFG_DMAEN 0x00000020U /*!< DMA enable */
+#define USB_OTG_GAHBCFG_TXFELVL 0x00000080U /*!< TxFIFO empty level */
+#define USB_OTG_GAHBCFG_PTXFELVL 0x00000100U /*!< Periodic TxFIFO empty level */
+
+/******************** Bit definition forUSB_OTG_GUSBCFG register ********************/
+
+#define USB_OTG_GUSBCFG_TOCAL 0x00000007U /*!< FS timeout calibration */
+#define USB_OTG_GUSBCFG_TOCAL_0 0x00000001U /*!<Bit 0 */
+#define USB_OTG_GUSBCFG_TOCAL_1 0x00000002U /*!<Bit 1 */
+#define USB_OTG_GUSBCFG_TOCAL_2 0x00000004U /*!<Bit 2 */
+#define USB_OTG_GUSBCFG_PHYSEL 0x00000040U /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */
+#define USB_OTG_GUSBCFG_SRPCAP 0x00000100U /*!< SRP-capable */
+#define USB_OTG_GUSBCFG_HNPCAP 0x00000200U /*!< HNP-capable */
+
+#define USB_OTG_GUSBCFG_TRDT 0x00003C00U /*!< USB turnaround time */
+#define USB_OTG_GUSBCFG_TRDT_0 0x00000400U /*!<Bit 0 */
+#define USB_OTG_GUSBCFG_TRDT_1 0x00000800U /*!<Bit 1 */
+#define USB_OTG_GUSBCFG_TRDT_2 0x00001000U /*!<Bit 2 */
+#define USB_OTG_GUSBCFG_TRDT_3 0x00002000U /*!<Bit 3 */
+#define USB_OTG_GUSBCFG_PHYLPCS 0x00008000U /*!< PHY Low-power clock select */
+#define USB_OTG_GUSBCFG_ULPIFSLS 0x00020000U /*!< ULPI FS/LS select */
+#define USB_OTG_GUSBCFG_ULPIAR 0x00040000U /*!< ULPI Auto-resume */
+#define USB_OTG_GUSBCFG_ULPICSM 0x00080000U /*!< ULPI Clock SuspendM */
+#define USB_OTG_GUSBCFG_ULPIEVBUSD 0x00100000U /*!< ULPI External VBUS Drive */
+#define USB_OTG_GUSBCFG_ULPIEVBUSI 0x00200000U /*!< ULPI external VBUS indicator */
+#define USB_OTG_GUSBCFG_TSDPS 0x00400000U /*!< TermSel DLine pulsing selection */
+#define USB_OTG_GUSBCFG_PCCI 0x00800000U /*!< Indicator complement */
+#define USB_OTG_GUSBCFG_PTCI 0x01000000U /*!< Indicator pass through */
+#define USB_OTG_GUSBCFG_ULPIIPD 0x02000000U /*!< ULPI interface protect disable */
+#define USB_OTG_GUSBCFG_FHMOD 0x20000000U /*!< Forced host mode */
+#define USB_OTG_GUSBCFG_FDMOD 0x40000000U /*!< Forced peripheral mode */
+#define USB_OTG_GUSBCFG_CTXPKT 0x80000000U /*!< Corrupt Tx packet */
+
+/******************** Bit definition forUSB_OTG_GRSTCTL register ********************/
+#define USB_OTG_GRSTCTL_CSRST 0x00000001U /*!< Core soft reset */
+#define USB_OTG_GRSTCTL_HSRST 0x00000002U /*!< HCLK soft reset */
+#define USB_OTG_GRSTCTL_FCRST 0x00000004U /*!< Host frame counter reset */
+#define USB_OTG_GRSTCTL_RXFFLSH 0x00000010U /*!< RxFIFO flush */
+#define USB_OTG_GRSTCTL_TXFFLSH 0x00000020U /*!< TxFIFO flush */
+
+#define USB_OTG_GRSTCTL_TXFNUM 0x000007C0U /*!< TxFIFO number */
+#define USB_OTG_GRSTCTL_TXFNUM_0 0x00000040U /*!<Bit 0 */
+#define USB_OTG_GRSTCTL_TXFNUM_1 0x00000080U /*!<Bit 1 */
+#define USB_OTG_GRSTCTL_TXFNUM_2 0x00000100U /*!<Bit 2 */
+#define USB_OTG_GRSTCTL_TXFNUM_3 0x00000200U /*!<Bit 3 */
+#define USB_OTG_GRSTCTL_TXFNUM_4 0x00000400U /*!<Bit 4 */
+#define USB_OTG_GRSTCTL_DMAREQ 0x40000000U /*!< DMA request signal */
+#define USB_OTG_GRSTCTL_AHBIDL 0x80000000U /*!< AHB master idle */
+
+/******************** Bit definition forUSB_OTG_DIEPMSK register ********************/
+#define USB_OTG_DIEPMSK_XFRCM 0x00000001U /*!< Transfer completed interrupt mask */
+#define USB_OTG_DIEPMSK_EPDM 0x00000002U /*!< Endpoint disabled interrupt mask */
+#define USB_OTG_DIEPMSK_TOM 0x00000008U /*!< Timeout condition mask (nonisochronous endpoints) */
+#define USB_OTG_DIEPMSK_ITTXFEMSK 0x00000010U /*!< IN token received when TxFIFO empty mask */
+#define USB_OTG_DIEPMSK_INEPNMM 0x00000020U /*!< IN token received with EP mismatch mask */
+#define USB_OTG_DIEPMSK_INEPNEM 0x00000040U /*!< IN endpoint NAK effective mask */
+#define USB_OTG_DIEPMSK_TXFURM 0x00000100U /*!< FIFO underrun mask */
+#define USB_OTG_DIEPMSK_BIM 0x00000200U /*!< BNA interrupt mask */
+
+/******************** Bit definition forUSB_OTG_HPTXSTS register ********************/
+#define USB_OTG_HPTXSTS_PTXFSAVL 0x0000FFFFU /*!< Periodic transmit data FIFO space available */
+
+#define USB_OTG_HPTXSTS_PTXQSAV 0x00FF0000U /*!< Periodic transmit request queue space available */
+#define USB_OTG_HPTXSTS_PTXQSAV_0 0x00010000U /*!<Bit 0 */
+#define USB_OTG_HPTXSTS_PTXQSAV_1 0x00020000U /*!<Bit 1 */
+#define USB_OTG_HPTXSTS_PTXQSAV_2 0x00040000U /*!<Bit 2 */
+#define USB_OTG_HPTXSTS_PTXQSAV_3 0x00080000U /*!<Bit 3 */
+#define USB_OTG_HPTXSTS_PTXQSAV_4 0x00100000U /*!<Bit 4 */
+#define USB_OTG_HPTXSTS_PTXQSAV_5 0x00200000U /*!<Bit 5 */
+#define USB_OTG_HPTXSTS_PTXQSAV_6 0x00400000U /*!<Bit 6 */
+#define USB_OTG_HPTXSTS_PTXQSAV_7 0x00800000U /*!<Bit 7 */
+
+#define USB_OTG_HPTXSTS_PTXQTOP 0xFF000000U /*!< Top of the periodic transmit request queue */
+#define USB_OTG_HPTXSTS_PTXQTOP_0 0x01000000U /*!<Bit 0 */
+#define USB_OTG_HPTXSTS_PTXQTOP_1 0x02000000U /*!<Bit 1 */
+#define USB_OTG_HPTXSTS_PTXQTOP_2 0x04000000U /*!<Bit 2 */
+#define USB_OTG_HPTXSTS_PTXQTOP_3 0x08000000U /*!<Bit 3 */
+#define USB_OTG_HPTXSTS_PTXQTOP_4 0x10000000U /*!<Bit 4 */
+#define USB_OTG_HPTXSTS_PTXQTOP_5 0x20000000U /*!<Bit 5 */
+#define USB_OTG_HPTXSTS_PTXQTOP_6 0x40000000U /*!<Bit 6 */
+#define USB_OTG_HPTXSTS_PTXQTOP_7 0x80000000U /*!<Bit 7 */
+
+/******************** Bit definition forUSB_OTG_HAINT register ********************/
+#define USB_OTG_HAINT_HAINT 0x0000FFFFU /*!< Channel interrupts */
+
+/******************** Bit definition forUSB_OTG_DOEPMSK register ********************/
+#define USB_OTG_DOEPMSK_XFRCM 0x00000001U /*!< Transfer completed interrupt mask */
+#define USB_OTG_DOEPMSK_EPDM 0x00000002U /*!< Endpoint disabled interrupt mask */
+#define USB_OTG_DOEPMSK_STUPM 0x00000008U /*!< SETUP phase done mask */
+#define USB_OTG_DOEPMSK_OTEPDM 0x00000010U /*!< OUT token received when endpoint disabled mask */
+#define USB_OTG_DOEPMSK_B2BSTUP 0x00000040U /*!< Back-to-back SETUP packets received mask */
+#define USB_OTG_DOEPMSK_OPEM 0x00000100U /*!< OUT packet error mask */
+#define USB_OTG_DOEPMSK_BOIM 0x00000200U /*!< BNA interrupt mask */
+
+/******************** Bit definition forUSB_OTG_GINTSTS register ********************/
+#define USB_OTG_GINTSTS_CMOD 0x00000001U /*!< Current mode of operation */
+#define USB_OTG_GINTSTS_MMIS 0x00000002U /*!< Mode mismatch interrupt */
+#define USB_OTG_GINTSTS_OTGINT 0x00000004U /*!< OTG interrupt */
+#define USB_OTG_GINTSTS_SOF 0x00000008U /*!< Start of frame */
+#define USB_OTG_GINTSTS_RXFLVL 0x00000010U /*!< RxFIFO nonempty */
+#define USB_OTG_GINTSTS_NPTXFE 0x00000020U /*!< Nonperiodic TxFIFO empty */
+#define USB_OTG_GINTSTS_GINAKEFF 0x00000040U /*!< Global IN nonperiodic NAK effective */
+#define USB_OTG_GINTSTS_BOUTNAKEFF 0x00000080U /*!< Global OUT NAK effective */
+#define USB_OTG_GINTSTS_ESUSP 0x00000400U /*!< Early suspend */
+#define USB_OTG_GINTSTS_USBSUSP 0x00000800U /*!< USB suspend */
+#define USB_OTG_GINTSTS_USBRST 0x00001000U /*!< USB reset */
+#define USB_OTG_GINTSTS_ENUMDNE 0x00002000U /*!< Enumeration done */
+#define USB_OTG_GINTSTS_ISOODRP 0x00004000U /*!< Isochronous OUT packet dropped interrupt */
+#define USB_OTG_GINTSTS_EOPF 0x00008000U /*!< End of periodic frame interrupt */
+#define USB_OTG_GINTSTS_IEPINT 0x00040000U /*!< IN endpoint interrupt */
+#define USB_OTG_GINTSTS_OEPINT 0x00080000U /*!< OUT endpoint interrupt */
+#define USB_OTG_GINTSTS_IISOIXFR 0x00100000U /*!< Incomplete isochronous IN transfer */
+#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT 0x00200000U /*!< Incomplete periodic transfer */
+#define USB_OTG_GINTSTS_DATAFSUSP 0x00400000U /*!< Data fetch suspended */
+#define USB_OTG_GINTSTS_HPRTINT 0x01000000U /*!< Host port interrupt */
+#define USB_OTG_GINTSTS_HCINT 0x02000000U /*!< Host channels interrupt */
+#define USB_OTG_GINTSTS_PTXFE 0x04000000U /*!< Periodic TxFIFO empty */
+#define USB_OTG_GINTSTS_CIDSCHG 0x10000000U /*!< Connector ID status change */
+#define USB_OTG_GINTSTS_DISCINT 0x20000000U /*!< Disconnect detected interrupt */
+#define USB_OTG_GINTSTS_SRQINT 0x40000000U /*!< Session request/new session detected interrupt */
+#define USB_OTG_GINTSTS_WKUINT 0x80000000U /*!< Resume/remote wakeup detected interrupt */
+
+/******************** Bit definition forUSB_OTG_GINTMSK register ********************/
+#define USB_OTG_GINTMSK_MMISM 0x00000002U /*!< Mode mismatch interrupt mask */
+#define USB_OTG_GINTMSK_OTGINT 0x00000004U /*!< OTG interrupt mask */
+#define USB_OTG_GINTMSK_SOFM 0x00000008U /*!< Start of frame mask */
+#define USB_OTG_GINTMSK_RXFLVLM 0x00000010U /*!< Receive FIFO nonempty mask */
+#define USB_OTG_GINTMSK_NPTXFEM 0x00000020U /*!< Nonperiodic TxFIFO empty mask */
+#define USB_OTG_GINTMSK_GINAKEFFM 0x00000040U /*!< Global nonperiodic IN NAK effective mask */
+#define USB_OTG_GINTMSK_GONAKEFFM 0x00000080U /*!< Global OUT NAK effective mask */
+#define USB_OTG_GINTMSK_ESUSPM 0x00000400U /*!< Early suspend mask */
+#define USB_OTG_GINTMSK_USBSUSPM 0x00000800U /*!< USB suspend mask */
+#define USB_OTG_GINTMSK_USBRST 0x00001000U /*!< USB reset mask */
+#define USB_OTG_GINTMSK_ENUMDNEM 0x00002000U /*!< Enumeration done mask */
+#define USB_OTG_GINTMSK_ISOODRPM 0x00004000U /*!< Isochronous OUT packet dropped interrupt mask */
+#define USB_OTG_GINTMSK_EOPFM 0x00008000U /*!< End of periodic frame interrupt mask */
+#define USB_OTG_GINTMSK_EPMISM 0x00020000U /*!< Endpoint mismatch interrupt mask */
+#define USB_OTG_GINTMSK_IEPINT 0x00040000U /*!< IN endpoints interrupt mask */
+#define USB_OTG_GINTMSK_OEPINT 0x00080000U /*!< OUT endpoints interrupt mask */
+#define USB_OTG_GINTMSK_IISOIXFRM 0x00100000U /*!< Incomplete isochronous IN transfer mask */
+#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM 0x00200000U /*!< Incomplete periodic transfer mask */
+#define USB_OTG_GINTMSK_FSUSPM 0x00400000U /*!< Data fetch suspended mask */
+#define USB_OTG_GINTMSK_PRTIM 0x01000000U /*!< Host port interrupt mask */
+#define USB_OTG_GINTMSK_HCIM 0x02000000U /*!< Host channels interrupt mask */
+#define USB_OTG_GINTMSK_PTXFEM 0x04000000U /*!< Periodic TxFIFO empty mask */
+#define USB_OTG_GINTMSK_CIDSCHGM 0x10000000U /*!< Connector ID status change mask */
+#define USB_OTG_GINTMSK_DISCINT 0x20000000U /*!< Disconnect detected interrupt mask */
+#define USB_OTG_GINTMSK_SRQIM 0x40000000U /*!< Session request/new session detected interrupt mask */
+#define USB_OTG_GINTMSK_WUIM 0x80000000U /*!< Resume/remote wakeup detected interrupt mask */
+
+/******************** Bit definition forUSB_OTG_DAINT register ********************/
+#define USB_OTG_DAINT_IEPINT 0x0000FFFFU /*!< IN endpoint interrupt bits */
+#define USB_OTG_DAINT_OEPINT 0xFFFF0000U /*!< OUT endpoint interrupt bits */
+
+/******************** Bit definition forUSB_OTG_HAINTMSK register ********************/
+#define USB_OTG_HAINTMSK_HAINTM 0x0000FFFFU /*!< Channel interrupt mask */
+
+/******************** Bit definition for USB_OTG_GRXSTSP register ********************/
+#define USB_OTG_GRXSTSP_EPNUM 0x0000000FU /*!< IN EP interrupt mask bits */
+#define USB_OTG_GRXSTSP_BCNT 0x00007FF0U /*!< OUT EP interrupt mask bits */
+#define USB_OTG_GRXSTSP_DPID 0x00018000U /*!< OUT EP interrupt mask bits */
+#define USB_OTG_GRXSTSP_PKTSTS 0x001E0000U /*!< OUT EP interrupt mask bits */
+
+/******************** Bit definition forUSB_OTG_DAINTMSK register ********************/
+#define USB_OTG_DAINTMSK_IEPM 0x0000FFFFU /*!< IN EP interrupt mask bits */
+#define USB_OTG_DAINTMSK_OEPM 0xFFFF0000U /*!< OUT EP interrupt mask bits */
+
+/******************** Bit definition for OTG register ********************/
+
+#define USB_OTG_CHNUM 0x0000000FU /*!< Channel number */
+#define USB_OTG_CHNUM_0 0x00000001U /*!<Bit 0 */
+#define USB_OTG_CHNUM_1 0x00000002U /*!<Bit 1 */
+#define USB_OTG_CHNUM_2 0x00000004U /*!<Bit 2 */
+#define USB_OTG_CHNUM_3 0x00000008U /*!<Bit 3 */
+#define USB_OTG_BCNT 0x00007FF0U /*!< Byte count */
+
+#define USB_OTG_DPID 0x00018000U /*!< Data PID */
+#define USB_OTG_DPID_0 0x00008000U /*!<Bit 0 */
+#define USB_OTG_DPID_1 0x00010000U /*!<Bit 1 */
+
+#define USB_OTG_PKTSTS 0x001E0000U /*!< Packet status */
+#define USB_OTG_PKTSTS_0 0x00020000U /*!<Bit 0 */
+#define USB_OTG_PKTSTS_1 0x00040000U /*!<Bit 1 */
+#define USB_OTG_PKTSTS_2 0x00080000U /*!<Bit 2 */
+#define USB_OTG_PKTSTS_3 0x00100000U /*!<Bit 3 */
+
+#define USB_OTG_EPNUM 0x0000000FU /*!< Endpoint number */
+#define USB_OTG_EPNUM_0 0x00000001U /*!<Bit 0 */
+#define USB_OTG_EPNUM_1 0x00000002U /*!<Bit 1 */
+#define USB_OTG_EPNUM_2 0x00000004U /*!<Bit 2 */
+#define USB_OTG_EPNUM_3 0x00000008U /*!<Bit 3 */
+
+#define USB_OTG_FRMNUM 0x01E00000U /*!< Frame number */
+#define USB_OTG_FRMNUM_0 0x00200000U /*!<Bit 0 */
+#define USB_OTG_FRMNUM_1 0x00400000U /*!<Bit 1 */
+#define USB_OTG_FRMNUM_2 0x00800000U /*!<Bit 2 */
+#define USB_OTG_FRMNUM_3 0x01000000U /*!<Bit 3 */
+
+/******************** Bit definition for OTG register ********************/
+
+#define USB_OTG_CHNUM 0x0000000FU /*!< Channel number */
+#define USB_OTG_CHNUM_0 0x00000001U /*!<Bit 0 */
+#define USB_OTG_CHNUM_1 0x00000002U /*!<Bit 1 */
+#define USB_OTG_CHNUM_2 0x00000004U /*!<Bit 2 */
+#define USB_OTG_CHNUM_3 0x00000008U /*!<Bit 3 */
+#define USB_OTG_BCNT 0x00007FF0U /*!< Byte count */
+
+#define USB_OTG_DPID 0x00018000U /*!< Data PID */
+#define USB_OTG_DPID_0 0x00008000U /*!<Bit 0 */
+#define USB_OTG_DPID_1 0x00010000U /*!<Bit 1 */
+
+#define USB_OTG_PKTSTS 0x001E0000U /*!< Packet status */
+#define USB_OTG_PKTSTS_0 0x00020000U /*!<Bit 0 */
+#define USB_OTG_PKTSTS_1 0x00040000U /*!<Bit 1 */
+#define USB_OTG_PKTSTS_2 0x00080000U /*!<Bit 2 */
+#define USB_OTG_PKTSTS_3 0x00100000U /*!<Bit 3 */
+
+#define USB_OTG_EPNUM 0x0000000FU /*!< Endpoint number */
+#define USB_OTG_EPNUM_0 0x00000001U /*!<Bit 0 */
+#define USB_OTG_EPNUM_1 0x00000002U /*!<Bit 1 */
+#define USB_OTG_EPNUM_2 0x00000004U /*!<Bit 2 */
+#define USB_OTG_EPNUM_3 0x00000008U /*!<Bit 3 */
+
+#define USB_OTG_FRMNUM 0x01E00000U /*!< Frame number */
+#define USB_OTG_FRMNUM_0 0x00200000U /*!<Bit 0 */
+#define USB_OTG_FRMNUM_1 0x00400000U /*!<Bit 1 */
+#define USB_OTG_FRMNUM_2 0x00800000U /*!<Bit 2 */
+#define USB_OTG_FRMNUM_3 0x01000000U /*!<Bit 3 */
+
+/******************** Bit definition forUSB_OTG_GRXFSIZ register ********************/
+#define USB_OTG_GRXFSIZ_RXFD 0x0000FFFFU /*!< RxFIFO depth */
+
+/******************** Bit definition forUSB_OTG_DVBUSDIS register ********************/
+#define USB_OTG_DVBUSDIS_VBUSDT 0x0000FFFFU /*!< Device VBUS discharge time */
+
+/******************** Bit definition for OTG register ********************/
+#define USB_OTG_NPTXFSA 0x0000FFFFU /*!< Nonperiodic transmit RAM start address */
+#define USB_OTG_NPTXFD 0xFFFF0000U /*!< Nonperiodic TxFIFO depth */
+#define USB_OTG_TX0FSA 0x0000FFFFU /*!< Endpoint 0 transmit RAM start address */
+#define USB_OTG_TX0FD 0xFFFF0000U /*!< Endpoint 0 TxFIFO depth */
+
+/******************** Bit definition forUSB_OTG_DVBUSPULSE register ********************/
+#define USB_OTG_DVBUSPULSE_DVBUSP 0x00000FFFU /*!< Device VBUS pulsing time */
+
+/******************** Bit definition forUSB_OTG_GNPTXSTS register ********************/
+#define USB_OTG_GNPTXSTS_NPTXFSAV 0x0000FFFFU /*!< Nonperiodic TxFIFO space available */
+
+#define USB_OTG_GNPTXSTS_NPTQXSAV 0x00FF0000U /*!< Nonperiodic transmit request queue space available */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_0 0x00010000U /*!<Bit 0 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_1 0x00020000U /*!<Bit 1 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_2 0x00040000U /*!<Bit 2 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_3 0x00080000U /*!<Bit 3 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_4 0x00100000U /*!<Bit 4 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_5 0x00200000U /*!<Bit 5 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_6 0x00400000U /*!<Bit 6 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_7 0x00800000U /*!<Bit 7 */
+
+#define USB_OTG_GNPTXSTS_NPTXQTOP 0x7F000000U /*!< Top of the nonperiodic transmit request queue */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_0 0x01000000U /*!<Bit 0 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_1 0x02000000U /*!<Bit 1 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_2 0x04000000U /*!<Bit 2 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_3 0x08000000U /*!<Bit 3 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_4 0x10000000U /*!<Bit 4 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_5 0x20000000U /*!<Bit 5 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_6 0x40000000U /*!<Bit 6 */
+
+/******************** Bit definition forUSB_OTG_DTHRCTL register ********************/
+#define USB_OTG_DTHRCTL_NONISOTHREN 0x00000001U /*!< Nonisochronous IN endpoints threshold enable */
+#define USB_OTG_DTHRCTL_ISOTHREN 0x00000002U /*!< ISO IN endpoint threshold enable */
+
+#define USB_OTG_DTHRCTL_TXTHRLEN 0x000007FCU /*!< Transmit threshold length */
+#define USB_OTG_DTHRCTL_TXTHRLEN_0 0x00000004U /*!<Bit 0 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_1 0x00000008U /*!<Bit 1 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_2 0x00000010U /*!<Bit 2 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_3 0x00000020U /*!<Bit 3 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_4 0x00000040U /*!<Bit 4 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_5 0x00000080U /*!<Bit 5 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_6 0x00000100U /*!<Bit 6 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_7 0x00000200U /*!<Bit 7 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_8 0x00000400U /*!<Bit 8 */
+#define USB_OTG_DTHRCTL_RXTHREN 0x00010000U /*!< Receive threshold enable */
+
+#define USB_OTG_DTHRCTL_RXTHRLEN 0x03FE0000U /*!< Receive threshold length */
+#define USB_OTG_DTHRCTL_RXTHRLEN_0 0x00020000U /*!<Bit 0 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_1 0x00040000U /*!<Bit 1 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_2 0x00080000U /*!<Bit 2 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_3 0x00100000U /*!<Bit 3 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_4 0x00200000U /*!<Bit 4 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_5 0x00400000U /*!<Bit 5 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_6 0x00800000U /*!<Bit 6 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_7 0x01000000U /*!<Bit 7 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_8 0x02000000U /*!<Bit 8 */
+#define USB_OTG_DTHRCTL_ARPEN 0x08000000U /*!< Arbiter parking enable */
+
+/******************** Bit definition forUSB_OTG_DIEPEMPMSK register ********************/
+#define USB_OTG_DIEPEMPMSK_INEPTXFEM 0x0000FFFFU /*!< IN EP Tx FIFO empty interrupt mask bits */
+
+/******************** Bit definition forUSB_OTG_DEACHINT register ********************/
+#define USB_OTG_DEACHINT_IEP1INT 0x00000002U /*!< IN endpoint 1interrupt bit */
+#define USB_OTG_DEACHINT_OEP1INT 0x00020000U /*!< OUT endpoint 1 interrupt bit */
+
+/******************** Bit definition forUSB_OTG_GCCFG register ********************/
+#define USB_OTG_GCCFG_PWRDWN 0x00010000U /*!< Power down */
+#define USB_OTG_GCCFG_I2CPADEN 0x00020000U /*!< Enable I2C bus connection for the external I2C PHY interface */
+#define USB_OTG_GCCFG_VBUSASEN 0x00040000U /*!< Enable the VBUS sensing device */
+#define USB_OTG_GCCFG_VBUSBSEN 0x00080000U /*!< Enable the VBUS sensing device */
+#define USB_OTG_GCCFG_SOFOUTEN 0x00100000U /*!< SOF output enable */
+#define USB_OTG_GCCFG_NOVBUSSENS 0x00200000U /*!< VBUS sensing disable option */
+
+/******************** Bit definition forUSB_OTG_DEACHINTMSK register ********************/
+#define USB_OTG_DEACHINTMSK_IEP1INTM 0x00000002U /*!< IN Endpoint 1 interrupt mask bit */
+#define USB_OTG_DEACHINTMSK_OEP1INTM 0x00020000U /*!< OUT Endpoint 1 interrupt mask bit */
+
+/******************** Bit definition forUSB_OTG_CID register ********************/
+#define USB_OTG_CID_PRODUCT_ID 0xFFFFFFFFU /*!< Product ID field */
+
+/******************** Bit definition forUSB_OTG_DIEPEACHMSK1 register ********************/
+#define USB_OTG_DIEPEACHMSK1_XFRCM 0x00000001U /*!< Transfer completed interrupt mask */
+#define USB_OTG_DIEPEACHMSK1_EPDM 0x00000002U /*!< Endpoint disabled interrupt mask */
+#define USB_OTG_DIEPEACHMSK1_TOM 0x00000008U /*!< Timeout condition mask (nonisochronous endpoints) */
+#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK 0x00000010U /*!< IN token received when TxFIFO empty mask */
+#define USB_OTG_DIEPEACHMSK1_INEPNMM 0x00000020U /*!< IN token received with EP mismatch mask */
+#define USB_OTG_DIEPEACHMSK1_INEPNEM 0x00000040U /*!< IN endpoint NAK effective mask */
+#define USB_OTG_DIEPEACHMSK1_TXFURM 0x00000100U /*!< FIFO underrun mask */
+#define USB_OTG_DIEPEACHMSK1_BIM 0x00000200U /*!< BNA interrupt mask */
+#define USB_OTG_DIEPEACHMSK1_NAKM 0x00002000U /*!< NAK interrupt mask */
+
+/******************** Bit definition forUSB_OTG_HPRT register ********************/
+#define USB_OTG_HPRT_PCSTS 0x00000001U /*!< Port connect status */
+#define USB_OTG_HPRT_PCDET 0x00000002U /*!< Port connect detected */
+#define USB_OTG_HPRT_PENA 0x00000004U /*!< Port enable */
+#define USB_OTG_HPRT_PENCHNG 0x00000008U /*!< Port enable/disable change */
+#define USB_OTG_HPRT_POCA 0x00000010U /*!< Port overcurrent active */
+#define USB_OTG_HPRT_POCCHNG 0x00000020U /*!< Port overcurrent change */
+#define USB_OTG_HPRT_PRES 0x00000040U /*!< Port resume */
+#define USB_OTG_HPRT_PSUSP 0x00000080U /*!< Port suspend */
+#define USB_OTG_HPRT_PRST 0x00000100U /*!< Port reset */
+
+#define USB_OTG_HPRT_PLSTS 0x00000C00U /*!< Port line status */
+#define USB_OTG_HPRT_PLSTS_0 0x00000400U /*!<Bit 0 */
+#define USB_OTG_HPRT_PLSTS_1 0x00000800U /*!<Bit 1 */
+#define USB_OTG_HPRT_PPWR 0x00001000U /*!< Port power */
+
+#define USB_OTG_HPRT_PTCTL 0x0001E000U /*!< Port test control */
+#define USB_OTG_HPRT_PTCTL_0 0x00002000U /*!<Bit 0 */
+#define USB_OTG_HPRT_PTCTL_1 0x00004000U /*!<Bit 1 */
+#define USB_OTG_HPRT_PTCTL_2 0x00008000U /*!<Bit 2 */
+#define USB_OTG_HPRT_PTCTL_3 0x00010000U /*!<Bit 3 */
+
+#define USB_OTG_HPRT_PSPD 0x00060000U /*!< Port speed */
+#define USB_OTG_HPRT_PSPD_0 0x00020000U /*!<Bit 0 */
+#define USB_OTG_HPRT_PSPD_1 0x00040000U /*!<Bit 1 */
+
+/******************** Bit definition forUSB_OTG_DOEPEACHMSK1 register ********************/
+#define USB_OTG_DOEPEACHMSK1_XFRCM 0x00000001U /*!< Transfer completed interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_EPDM 0x00000002U /*!< Endpoint disabled interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_TOM 0x00000008U /*!< Timeout condition mask */
+#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK 0x00000010U /*!< IN token received when TxFIFO empty mask */
+#define USB_OTG_DOEPEACHMSK1_INEPNMM 0x00000020U /*!< IN token received with EP mismatch mask */
+#define USB_OTG_DOEPEACHMSK1_INEPNEM 0x00000040U /*!< IN endpoint NAK effective mask */
+#define USB_OTG_DOEPEACHMSK1_TXFURM 0x00000100U /*!< OUT packet error mask */
+#define USB_OTG_DOEPEACHMSK1_BIM 0x00000200U /*!< BNA interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_BERRM 0x00001000U /*!< Bubble error interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_NAKM 0x00002000U /*!< NAK interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_NYETM 0x00004000U /*!< NYET interrupt mask */
+
+/******************** Bit definition forUSB_OTG_HPTXFSIZ register ********************/
+#define USB_OTG_HPTXFSIZ_PTXSA 0x0000FFFFU /*!< Host periodic TxFIFO start address */
+#define USB_OTG_HPTXFSIZ_PTXFD 0xFFFF0000U /*!< Host periodic TxFIFO depth */
+
+/******************** Bit definition forUSB_OTG_DIEPCTL register ********************/
+#define USB_OTG_DIEPCTL_MPSIZ 0x000007FFU /*!< Maximum packet size */
+#define USB_OTG_DIEPCTL_USBAEP 0x00008000U /*!< USB active endpoint */
+#define USB_OTG_DIEPCTL_EONUM_DPID 0x00010000U /*!< Even/odd frame */
+#define USB_OTG_DIEPCTL_NAKSTS 0x00020000U /*!< NAK status */
+
+#define USB_OTG_DIEPCTL_EPTYP 0x000C0000U /*!< Endpoint type */
+#define USB_OTG_DIEPCTL_EPTYP_0 0x00040000U /*!<Bit 0 */
+#define USB_OTG_DIEPCTL_EPTYP_1 0x00080000U /*!<Bit 1 */
+#define USB_OTG_DIEPCTL_STALL 0x00200000U /*!< STALL handshake */
+
+#define USB_OTG_DIEPCTL_TXFNUM 0x03C00000U /*!< TxFIFO number */
+#define USB_OTG_DIEPCTL_TXFNUM_0 0x00400000U /*!<Bit 0 */
+#define USB_OTG_DIEPCTL_TXFNUM_1 0x00800000U /*!<Bit 1 */
+#define USB_OTG_DIEPCTL_TXFNUM_2 0x01000000U /*!<Bit 2 */
+#define USB_OTG_DIEPCTL_TXFNUM_3 0x02000000U /*!<Bit 3 */
+#define USB_OTG_DIEPCTL_CNAK 0x04000000U /*!< Clear NAK */
+#define USB_OTG_DIEPCTL_SNAK 0x08000000U /*!< Set NAK */
+#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM 0x10000000U /*!< Set DATA0 PID */
+#define USB_OTG_DIEPCTL_SODDFRM 0x20000000U /*!< Set odd frame */
+#define USB_OTG_DIEPCTL_EPDIS 0x40000000U /*!< Endpoint disable */
+#define USB_OTG_DIEPCTL_EPENA 0x80000000U /*!< Endpoint enable */
+
+/******************** Bit definition forUSB_OTG_HCCHAR register ********************/
+#define USB_OTG_HCCHAR_MPSIZ 0x000007FFU /*!< Maximum packet size */
+
+#define USB_OTG_HCCHAR_EPNUM 0x00007800U /*!< Endpoint number */
+#define USB_OTG_HCCHAR_EPNUM_0 0x00000800U /*!<Bit 0 */
+#define USB_OTG_HCCHAR_EPNUM_1 0x00001000U /*!<Bit 1 */
+#define USB_OTG_HCCHAR_EPNUM_2 0x00002000U /*!<Bit 2 */
+#define USB_OTG_HCCHAR_EPNUM_3 0x00004000U /*!<Bit 3 */
+#define USB_OTG_HCCHAR_EPDIR 0x00008000U /*!< Endpoint direction */
+#define USB_OTG_HCCHAR_LSDEV 0x00020000U /*!< Low-speed device */
+
+#define USB_OTG_HCCHAR_EPTYP 0x000C0000U /*!< Endpoint type */
+#define USB_OTG_HCCHAR_EPTYP_0 0x00040000U /*!<Bit 0 */
+#define USB_OTG_HCCHAR_EPTYP_1 0x00080000U /*!<Bit 1 */
+
+#define USB_OTG_HCCHAR_MC 0x00300000U /*!< Multi Count (MC) / Error Count (EC) */
+#define USB_OTG_HCCHAR_MC_0 0x00100000U /*!<Bit 0 */
+#define USB_OTG_HCCHAR_MC_1 0x00200000U /*!<Bit 1 */
+
+#define USB_OTG_HCCHAR_DAD 0x1FC00000U /*!< Device address */
+#define USB_OTG_HCCHAR_DAD_0 0x00400000U /*!<Bit 0 */
+#define USB_OTG_HCCHAR_DAD_1 0x00800000U /*!<Bit 1 */
+#define USB_OTG_HCCHAR_DAD_2 0x01000000U /*!<Bit 2 */
+#define USB_OTG_HCCHAR_DAD_3 0x02000000U /*!<Bit 3 */
+#define USB_OTG_HCCHAR_DAD_4 0x04000000U /*!<Bit 4 */
+#define USB_OTG_HCCHAR_DAD_5 0x08000000U /*!<Bit 5 */
+#define USB_OTG_HCCHAR_DAD_6 0x10000000U /*!<Bit 6 */
+#define USB_OTG_HCCHAR_ODDFRM 0x20000000U /*!< Odd frame */
+#define USB_OTG_HCCHAR_CHDIS 0x40000000U /*!< Channel disable */
+#define USB_OTG_HCCHAR_CHENA 0x80000000U /*!< Channel enable */
+
+/******************** Bit definition forUSB_OTG_HCSPLT register ********************/
+
+#define USB_OTG_HCSPLT_PRTADDR 0x0000007FU /*!< Port address */
+#define USB_OTG_HCSPLT_PRTADDR_0 0x00000001U /*!<Bit 0 */
+#define USB_OTG_HCSPLT_PRTADDR_1 0x00000002U /*!<Bit 1 */
+#define USB_OTG_HCSPLT_PRTADDR_2 0x00000004U /*!<Bit 2 */
+#define USB_OTG_HCSPLT_PRTADDR_3 0x00000008U /*!<Bit 3 */
+#define USB_OTG_HCSPLT_PRTADDR_4 0x00000010U /*!<Bit 4 */
+#define USB_OTG_HCSPLT_PRTADDR_5 0x00000020U /*!<Bit 5 */
+#define USB_OTG_HCSPLT_PRTADDR_6 0x00000040U /*!<Bit 6 */
+
+#define USB_OTG_HCSPLT_HUBADDR 0x00003F80U /*!< Hub address */
+#define USB_OTG_HCSPLT_HUBADDR_0 0x00000080U /*!<Bit 0 */
+#define USB_OTG_HCSPLT_HUBADDR_1 0x00000100U /*!<Bit 1 */
+#define USB_OTG_HCSPLT_HUBADDR_2 0x00000200U /*!<Bit 2 */
+#define USB_OTG_HCSPLT_HUBADDR_3 0x00000400U /*!<Bit 3 */
+#define USB_OTG_HCSPLT_HUBADDR_4 0x00000800U /*!<Bit 4 */
+#define USB_OTG_HCSPLT_HUBADDR_5 0x00001000U /*!<Bit 5 */
+#define USB_OTG_HCSPLT_HUBADDR_6 0x00002000U /*!<Bit 6 */
+
+#define USB_OTG_HCSPLT_XACTPOS 0x0000C000U /*!< XACTPOS */
+#define USB_OTG_HCSPLT_XACTPOS_0 0x00004000U /*!<Bit 0 */
+#define USB_OTG_HCSPLT_XACTPOS_1 0x00008000U /*!<Bit 1 */
+#define USB_OTG_HCSPLT_COMPLSPLT 0x00010000U /*!< Do complete split */
+#define USB_OTG_HCSPLT_SPLITEN 0x80000000U /*!< Split enable */
+
+/******************** Bit definition forUSB_OTG_HCINT register ********************/
+#define USB_OTG_HCINT_XFRC 0x00000001U /*!< Transfer completed */
+#define USB_OTG_HCINT_CHH 0x00000002U /*!< Channel halted */
+#define USB_OTG_HCINT_AHBERR 0x00000004U /*!< AHB error */
+#define USB_OTG_HCINT_STALL 0x00000008U /*!< STALL response received interrupt */
+#define USB_OTG_HCINT_NAK 0x00000010U /*!< NAK response received interrupt */
+#define USB_OTG_HCINT_ACK 0x00000020U /*!< ACK response received/transmitted interrupt */
+#define USB_OTG_HCINT_NYET 0x00000040U /*!< Response received interrupt */
+#define USB_OTG_HCINT_TXERR 0x00000080U /*!< Transaction error */
+#define USB_OTG_HCINT_BBERR 0x00000100U /*!< Babble error */
+#define USB_OTG_HCINT_FRMOR 0x00000200U /*!< Frame overrun */
+#define USB_OTG_HCINT_DTERR 0x00000400U /*!< Data toggle error */
+
+/******************** Bit definition forUSB_OTG_DIEPINT register ********************/
+#define USB_OTG_DIEPINT_XFRC 0x00000001U /*!< Transfer completed interrupt */
+#define USB_OTG_DIEPINT_EPDISD 0x00000002U /*!< Endpoint disabled interrupt */
+#define USB_OTG_DIEPINT_TOC 0x00000008U /*!< Timeout condition */
+#define USB_OTG_DIEPINT_ITTXFE 0x00000010U /*!< IN token received when TxFIFO is empty */
+#define USB_OTG_DIEPINT_INEPNE 0x00000040U /*!< IN endpoint NAK effective */
+#define USB_OTG_DIEPINT_TXFE 0x00000080U /*!< Transmit FIFO empty */
+#define USB_OTG_DIEPINT_TXFIFOUDRN 0x00000100U /*!< Transmit Fifo Underrun */
+#define USB_OTG_DIEPINT_BNA 0x00000200U /*!< Buffer not available interrupt */
+#define USB_OTG_DIEPINT_PKTDRPSTS 0x00000800U /*!< Packet dropped status */
+#define USB_OTG_DIEPINT_BERR 0x00001000U /*!< Babble error interrupt */
+#define USB_OTG_DIEPINT_NAK 0x00002000U /*!< NAK interrupt */
+
+/******************** Bit definition forUSB_OTG_HCINTMSK register ********************/
+#define USB_OTG_HCINTMSK_XFRCM 0x00000001U /*!< Transfer completed mask */
+#define USB_OTG_HCINTMSK_CHHM 0x00000002U /*!< Channel halted mask */
+#define USB_OTG_HCINTMSK_AHBERR 0x00000004U /*!< AHB error */
+#define USB_OTG_HCINTMSK_STALLM 0x00000008U /*!< STALL response received interrupt mask */
+#define USB_OTG_HCINTMSK_NAKM 0x00000010U /*!< NAK response received interrupt mask */
+#define USB_OTG_HCINTMSK_ACKM 0x00000020U /*!< ACK response received/transmitted interrupt mask */
+#define USB_OTG_HCINTMSK_NYET 0x00000040U /*!< response received interrupt mask */
+#define USB_OTG_HCINTMSK_TXERRM 0x00000080U /*!< Transaction error mask */
+#define USB_OTG_HCINTMSK_BBERRM 0x00000100U /*!< Babble error mask */
+#define USB_OTG_HCINTMSK_FRMORM 0x00000200U /*!< Frame overrun mask */
+#define USB_OTG_HCINTMSK_DTERRM 0x00000400U /*!< Data toggle error mask */
+
+/******************** Bit definition for USB_OTG_DIEPTSIZ register ********************/
+
+#define USB_OTG_DIEPTSIZ_XFRSIZ 0x0007FFFFU /*!< Transfer size */
+#define USB_OTG_DIEPTSIZ_PKTCNT 0x1FF80000U /*!< Packet count */
+#define USB_OTG_DIEPTSIZ_MULCNT 0x60000000U /*!< Packet count */
+/******************** Bit definition forUSB_OTG_HCTSIZ register ********************/
+#define USB_OTG_HCTSIZ_XFRSIZ 0x0007FFFFU /*!< Transfer size */
+#define USB_OTG_HCTSIZ_PKTCNT 0x1FF80000U /*!< Packet count */
+#define USB_OTG_HCTSIZ_DOPING 0x80000000U /*!< Do PING */
+#define USB_OTG_HCTSIZ_DPID 0x60000000U /*!< Data PID */
+#define USB_OTG_HCTSIZ_DPID_0 0x20000000U /*!<Bit 0 */
+#define USB_OTG_HCTSIZ_DPID_1 0x40000000U /*!<Bit 1 */
+
+/******************** Bit definition forUSB_OTG_DIEPDMA register ********************/
+#define USB_OTG_DIEPDMA_DMAADDR 0xFFFFFFFFU /*!< DMA address */
+
+/******************** Bit definition forUSB_OTG_HCDMA register ********************/
+#define USB_OTG_HCDMA_DMAADDR 0xFFFFFFFFU /*!< DMA address */
+
+/******************** Bit definition forUSB_OTG_DTXFSTS register ********************/
+#define USB_OTG_DTXFSTS_INEPTFSAV 0x0000FFFFU /*!< IN endpoint TxFIFO space avail */
+
+/******************** Bit definition forUSB_OTG_DIEPTXF register ********************/
+#define USB_OTG_DIEPTXF_INEPTXSA 0x0000FFFFU /*!< IN endpoint FIFOx transmit RAM start address */
+#define USB_OTG_DIEPTXF_INEPTXFD 0xFFFF0000U /*!< IN endpoint TxFIFO depth */
+
+/******************** Bit definition forUSB_OTG_DOEPCTL register ********************/
+
+#define USB_OTG_DOEPCTL_MPSIZ 0x000007FFU /*!< Maximum packet size */ /*!<Bit 1 */
+#define USB_OTG_DOEPCTL_USBAEP 0x00008000U /*!< USB active endpoint */
+#define USB_OTG_DOEPCTL_NAKSTS 0x00020000U /*!< NAK status */
+#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM 0x10000000U /*!< Set DATA0 PID */
+#define USB_OTG_DOEPCTL_SODDFRM 0x20000000U /*!< Set odd frame */
+#define USB_OTG_DOEPCTL_EPTYP 0x000C0000U /*!< Endpoint type */
+#define USB_OTG_DOEPCTL_EPTYP_0 0x00040000U /*!<Bit 0 */
+#define USB_OTG_DOEPCTL_EPTYP_1 0x00080000U /*!<Bit 1 */
+#define USB_OTG_DOEPCTL_SNPM 0x00100000U /*!< Snoop mode */
+#define USB_OTG_DOEPCTL_STALL 0x00200000U /*!< STALL handshake */
+#define USB_OTG_DOEPCTL_CNAK 0x04000000U /*!< Clear NAK */
+#define USB_OTG_DOEPCTL_SNAK 0x08000000U /*!< Set NAK */
+#define USB_OTG_DOEPCTL_EPDIS 0x40000000U /*!< Endpoint disable */
+#define USB_OTG_DOEPCTL_EPENA 0x80000000U /*!< Endpoint enable */
+
+/******************** Bit definition forUSB_OTG_DOEPINT register ********************/
+#define USB_OTG_DOEPINT_XFRC 0x00000001U /*!< Transfer completed interrupt */
+#define USB_OTG_DOEPINT_EPDISD 0x00000002U /*!< Endpoint disabled interrupt */
+#define USB_OTG_DOEPINT_STUP 0x00000008U /*!< SETUP phase done */
+#define USB_OTG_DOEPINT_OTEPDIS 0x00000010U /*!< OUT token received when endpoint disabled */
+#define USB_OTG_DOEPINT_B2BSTUP 0x00000040U /*!< Back-to-back SETUP packets received */
+#define USB_OTG_DOEPINT_NYET 0x00004000U /*!< NYET interrupt */
+
+/******************** Bit definition forUSB_OTG_DOEPTSIZ register ********************/
+
+#define USB_OTG_DOEPTSIZ_XFRSIZ 0x0007FFFFU /*!< Transfer size */
+#define USB_OTG_DOEPTSIZ_PKTCNT 0x1FF80000U /*!< Packet count */
+
+#define USB_OTG_DOEPTSIZ_STUPCNT 0x60000000U /*!< SETUP packet count */
+#define USB_OTG_DOEPTSIZ_STUPCNT_0 0x20000000U /*!<Bit 0 */
+#define USB_OTG_DOEPTSIZ_STUPCNT_1 0x40000000U /*!<Bit 1 */
+
+/******************** Bit definition for PCGCCTL register ********************/
+#define USB_OTG_PCGCCTL_STOPCLK 0x00000001U /*!< SETUP packet count */
+#define USB_OTG_PCGCCTL_GATECLK 0x00000002U /*!<Bit 0 */
+#define USB_OTG_PCGCCTL_PHYSUSP 0x00000010U /*!<Bit 1 */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup Exported_macros
+ * @{
+ */
+
+/******************************* ADC Instances ********************************/
+#define IS_ADC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
+
+/******************************* CRC Instances ********************************/
+#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
+
+/******************************** DMA Instances *******************************/
+#define IS_DMA_STREAM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0) || \
+ ((INSTANCE) == DMA1_Stream1) || \
+ ((INSTANCE) == DMA1_Stream2) || \
+ ((INSTANCE) == DMA1_Stream3) || \
+ ((INSTANCE) == DMA1_Stream4) || \
+ ((INSTANCE) == DMA1_Stream5) || \
+ ((INSTANCE) == DMA1_Stream6) || \
+ ((INSTANCE) == DMA1_Stream7) || \
+ ((INSTANCE) == DMA2_Stream0) || \
+ ((INSTANCE) == DMA2_Stream1) || \
+ ((INSTANCE) == DMA2_Stream2) || \
+ ((INSTANCE) == DMA2_Stream3) || \
+ ((INSTANCE) == DMA2_Stream4) || \
+ ((INSTANCE) == DMA2_Stream5) || \
+ ((INSTANCE) == DMA2_Stream6) || \
+ ((INSTANCE) == DMA2_Stream7))
+
+/******************************* GPIO Instances *******************************/
+#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
+ ((INSTANCE) == GPIOB) || \
+ ((INSTANCE) == GPIOC) || \
+ ((INSTANCE) == GPIOD) || \
+ ((INSTANCE) == GPIOE) || \
+ ((INSTANCE) == GPIOH))
+
+/******************************** I2C Instances *******************************/
+#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
+ ((INSTANCE) == I2C2) || \
+ ((INSTANCE) == I2C3))
+
+/******************************** I2S Instances *******************************/
+#define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
+ ((INSTANCE) == SPI2) || \
+ ((INSTANCE) == SPI3) || \
+ ((INSTANCE) == SPI4) || \
+ ((INSTANCE) == SPI5))
+
+/*************************** I2S Extended Instances ***************************/
+#define IS_I2S_ALL_INSTANCE_EXT(PERIPH) (((INSTANCE) == SPI2) || \
+ ((INSTANCE) == SPI3) || \
+ ((INSTANCE) == I2S2ext) || \
+ ((INSTANCE) == I2S3ext))
+
+
+/****************************** RTC Instances *********************************/
+#define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
+
+/******************************** SPI Instances *******************************/
+#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
+ ((INSTANCE) == SPI2) || \
+ ((INSTANCE) == SPI3) || \
+ ((INSTANCE) == SPI4) || \
+ ((INSTANCE) == SPI5))
+/*************************** SPI Extended Instances ***************************/
+#define IS_SPI_ALL_INSTANCE_EXT(INSTANCE) (((INSTANCE) == SPI1) || \
+ ((INSTANCE) == SPI2) || \
+ ((INSTANCE) == SPI3) || \
+ ((INSTANCE) == SPI4) || \
+ ((INSTANCE) == SPI5) || \
+ ((INSTANCE) == I2S2ext) || \
+ ((INSTANCE) == I2S3ext))
+
+/****************** TIM Instances : All supported instances *******************/
+#define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM9) || \
+ ((INSTANCE) == TIM10) || \
+ ((INSTANCE) == TIM11))
+
+/************* TIM Instances : at least 1 capture/compare channel *************/
+#define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM9) || \
+ ((INSTANCE) == TIM10) || \
+ ((INSTANCE) == TIM11))
+
+/************ TIM Instances : at least 2 capture/compare channels *************/
+#define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM9))
+
+/************ TIM Instances : at least 3 capture/compare channels *************/
+#define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5))
+
+/************ TIM Instances : at least 4 capture/compare channels *************/
+#define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5))
+
+/******************** TIM Instances : Advanced-control timers *****************/
+#define IS_TIM_ADVANCED_INSTANCE(INSTANCE) ((INSTANCE) == TIM1)
+
+/******************* TIM Instances : Timer input XOR function *****************/
+#define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5))
+
+/****************** TIM Instances : DMA requests generation (UDE) *************/
+#define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5))
+
+/************ TIM Instances : DMA requests generation (CCxDE) *****************/
+#define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5))
+
+/************ TIM Instances : DMA requests generation (COMDE) *****************/
+#define IS_TIM_CCDMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5))
+
+/******************** TIM Instances : DMA burst feature ***********************/
+#define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5))
+
+/****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/
+#define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM9))
+
+/*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
+#define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM9))
+
+/********************** TIM Instances : 32 bit Counter ************************/
+#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)(((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM5))
+
+/***************** TIM Instances : external trigger input availabe ************/
+#define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5))
+
+/****************** TIM Instances : remapping capability **********************/
+#define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM11))
+
+/******************* TIM Instances : output(s) available **********************/
+#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
+ ((((INSTANCE) == TIM1) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM2) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM3) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM4) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM5) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM9) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2))) \
+ || \
+ (((INSTANCE) == TIM10) && \
+ (((CHANNEL) == TIM_CHANNEL_1))) \
+ || \
+ (((INSTANCE) == TIM11) && \
+ (((CHANNEL) == TIM_CHANNEL_1))))
+
+/************ TIM Instances : complementary output(s) available ***************/
+#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
+ ((((INSTANCE) == TIM1) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3))))
+
+/******************** USART Instances : Synchronous mode **********************/
+#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART6))
+
+/******************** UART Instances : Asynchronous mode **********************/
+#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART6))
+
+/****************** UART Instances : Hardware Flow control ********************/
+#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART6))
+
+/********************* UART Instances : Smard card mode ***********************/
+#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART6))
+
+/*********************** UART Instances : IRDA mode ***************************/
+#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART6))
+
+/*********************** PCD Instances ****************************************/
+#define IS_PCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS))
+
+/*********************** HCD Instances ****************************************/
+#define IS_HCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS))
+
+/****************************** IWDG Instances ********************************/
+#define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
+
+/****************************** WWDG Instances ********************************/
+#define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
+
+/****************************** SDIO Instances ********************************/
+#define IS_SDIO_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SDIO)
+
+/****************************** USB Exported Constants ************************/
+#define USB_OTG_FS_HOST_MAX_CHANNEL_NBR 8U
+#define USB_OTG_FS_MAX_IN_ENDPOINTS 4U /* Including EP0 */
+#define USB_OTG_FS_MAX_OUT_ENDPOINTS 4U /* Including EP0 */
+#define USB_OTG_FS_TOTAL_FIFO_SIZE 1280U /* in Bytes */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* __STM32F411xE_H */
+
+
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Device/ST/STM32F4xx/Include/stm32f412cx.h b/Device/ST/STM32F4xx/Include/stm32f412cx.h
new file mode 100644
index 0000000..f488b29
--- /dev/null
+++ b/Device/ST/STM32F4xx/Include/stm32f412cx.h
@@ -0,0 +1,6743 @@
+/**
+ ******************************************************************************
+ * @file stm32f412cx.h
+ * @author MCD Application Team
+ * @version V2.5.0
+ * @date 22-April-2016
+ * @brief CMSIS STM32F412Cx Device Peripheral Access Layer Header File.
+ *
+ * This file contains:
+ * - Data structures and the address mapping for all peripherals
+ * - peripherals registers declarations and bits definition
+ * - Macros to access peripheral’s registers hardware
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/** @addtogroup CMSIS
+ * @{
+ */
+
+/** @addtogroup stm32f412cx
+ * @{
+ */
+
+#ifndef __STM32F412Cx_H
+#define __STM32F412Cx_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif /* __cplusplus */
+
+
+/** @addtogroup Configuration_section_for_CMSIS
+ * @{
+ */
+
+/**
+ * @brief Configuration of the Cortex-M4 Processor and Core Peripherals
+ */
+#define __CM4_REV 0x0001U /*!< Core revision r0p1 */
+#define __MPU_PRESENT 1U /*!< STM32F4XX provides an MPU */
+#define __NVIC_PRIO_BITS 4U /*!< STM32F4XX uses 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */
+#define __FPU_PRESENT 1U /*!< FPU present */
+
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_interrupt_number_definition
+ * @{
+ */
+
+/**
+ * @brief STM32F4XX Interrupt Number Definition, according to the selected device
+ * in @ref Library_configuration_section
+ */
+typedef enum
+{
+/****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/
+ NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
+ MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */
+ BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */
+ UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */
+ SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */
+ DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */
+ PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */
+ SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */
+/****** STM32 specific Interrupt Numbers **********************************************************************/
+ WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
+ PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */
+ TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */
+ RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */
+ FLASH_IRQn = 4, /*!< FLASH global Interrupt */
+ RCC_IRQn = 5, /*!< RCC global Interrupt */
+ EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */
+ EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */
+ EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */
+ EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */
+ EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */
+ DMA1_Stream0_IRQn = 11, /*!< DMA1 Stream 0 global Interrupt */
+ DMA1_Stream1_IRQn = 12, /*!< DMA1 Stream 1 global Interrupt */
+ DMA1_Stream2_IRQn = 13, /*!< DMA1 Stream 2 global Interrupt */
+ DMA1_Stream3_IRQn = 14, /*!< DMA1 Stream 3 global Interrupt */
+ DMA1_Stream4_IRQn = 15, /*!< DMA1 Stream 4 global Interrupt */
+ DMA1_Stream5_IRQn = 16, /*!< DMA1 Stream 5 global Interrupt */
+ DMA1_Stream6_IRQn = 17, /*!< DMA1 Stream 6 global Interrupt */
+ ADC_IRQn = 18, /*!< ADC1 global Interrupts */
+ CAN1_TX_IRQn = 19, /*!< CAN1 TX Interrupt */
+ CAN1_RX0_IRQn = 20, /*!< CAN1 RX0 Interrupt */
+ CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */
+ CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */
+ EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
+ TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break interrupt and TIM9 global interrupt */
+ TIM1_UP_TIM10_IRQn = 25, /*!< TIM1 Update Interrupt and TIM10 global interrupt */
+ TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */
+ TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
+ TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
+ TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
+ TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
+ I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
+ I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
+ I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
+ I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
+ SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
+ SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
+ USART1_IRQn = 37, /*!< USART1 global Interrupt */
+ USART2_IRQn = 38, /*!< USART2 global Interrupt */
+ EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
+ RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */
+ OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS Wakeup through EXTI line interrupt */
+ TIM8_BRK_TIM12_IRQn = 43, /*!< TIM8 Break Interrupt and TIM12 global interrupt */
+ TIM8_UP_TIM13_IRQn = 44, /*!< TIM8 Update Interrupt and TIM13 global interrupt */
+ TIM8_TRG_COM_TIM14_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */
+ TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */
+ DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */
+ SDIO_IRQn = 49, /*!< SDIO global Interrupt */
+ TIM5_IRQn = 50, /*!< TIM5 global Interrupt */
+ SPI3_IRQn = 51, /*!< SPI3 global Interrupt */
+ TIM6_IRQn = 54, /*!< TIM6 global interrupt */
+ TIM7_IRQn = 55, /*!< TIM7 global interrupt */
+ DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */
+ DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */
+ DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */
+ DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */
+ DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */
+ DFSDM1_FLT0_IRQn = 61, /*!< DFSDM1 Filter 0 global Interrupt */
+ DFSDM1_FLT1_IRQn = 62, /*!< DFSDM1 Filter 1 global Interrupt */
+ CAN2_TX_IRQn = 63, /*!< CAN2 TX Interrupt */
+ CAN2_RX0_IRQn = 64, /*!< CAN2 RX0 Interrupt */
+ CAN2_RX1_IRQn = 65, /*!< CAN2 RX1 Interrupt */
+ CAN2_SCE_IRQn = 66, /*!< CAN2 SCE Interrupt */
+ OTG_FS_IRQn = 67, /*!< USB OTG FS global Interrupt */
+ DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */
+ DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */
+ DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */
+ USART6_IRQn = 71, /*!< USART6 global interrupt */
+ I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */
+ I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */
+ RNG_IRQn = 80, /*!< RNG global Interrupt */
+ FPU_IRQn = 81, /*!< FPU global interrupt */
+ SPI4_IRQn = 84, /*!< SPI4 global Interrupt */
+ SPI5_IRQn = 85, /*!< SPI5 global Interrupt */
+ FMPI2C1_EV_IRQn = 95, /*!< FMPI2C1 Event Interrupt */
+ FMPI2C1_ER_IRQn = 96 /*!< FMPI2C1 Error Interrupt */
+} IRQn_Type;
+
+/**
+ * @}
+ */
+
+#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
+#include "system_stm32f4xx.h"
+#include <stdint.h>
+
+/** @addtogroup Peripheral_registers_structures
+ * @{
+ */
+
+/**
+ * @brief Analog to Digital Converter
+ */
+
+typedef struct
+{
+ __IO uint32_t SR; /*!< ADC status register, Address offset: 0x00 */
+ __IO uint32_t CR1; /*!< ADC control register 1, Address offset: 0x04 */
+ __IO uint32_t CR2; /*!< ADC control register 2, Address offset: 0x08 */
+ __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x0C */
+ __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x10 */
+ __IO uint32_t JOFR1; /*!< ADC injected channel data offset register 1, Address offset: 0x14 */
+ __IO uint32_t JOFR2; /*!< ADC injected channel data offset register 2, Address offset: 0x18 */
+ __IO uint32_t JOFR3; /*!< ADC injected channel data offset register 3, Address offset: 0x1C */
+ __IO uint32_t JOFR4; /*!< ADC injected channel data offset register 4, Address offset: 0x20 */
+ __IO uint32_t HTR; /*!< ADC watchdog higher threshold register, Address offset: 0x24 */
+ __IO uint32_t LTR; /*!< ADC watchdog lower threshold register, Address offset: 0x28 */
+ __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x2C */
+ __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x30 */
+ __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x34 */
+ __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x38*/
+ __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x3C */
+ __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x40 */
+ __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x44 */
+ __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x48 */
+ __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x4C */
+} ADC_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1 base address + 0x300 */
+ __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1 base address + 0x304 */
+ __IO uint32_t CDR; /*!< ADC common regular data register for dual
+ AND triple modes, Address offset: ADC1 base address + 0x308 */
+} ADC_Common_TypeDef;
+
+/**
+ * @brief Controller Area Network TxMailBox
+ */
+
+typedef struct
+{
+ __IO uint32_t TIR; /*!< CAN TX mailbox identifier register */
+ __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */
+ __IO uint32_t TDLR; /*!< CAN mailbox data low register */
+ __IO uint32_t TDHR; /*!< CAN mailbox data high register */
+} CAN_TxMailBox_TypeDef;
+
+/**
+ * @brief Controller Area Network FIFOMailBox
+ */
+
+typedef struct
+{
+ __IO uint32_t RIR; /*!< CAN receive FIFO mailbox identifier register */
+ __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */
+ __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */
+ __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */
+} CAN_FIFOMailBox_TypeDef;
+
+/**
+ * @brief Controller Area Network FilterRegister
+ */
+
+typedef struct
+{
+ __IO uint32_t FR1; /*!< CAN Filter bank register 1 */
+ __IO uint32_t FR2; /*!< CAN Filter bank register 1 */
+} CAN_FilterRegister_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t MCR; /*!< CAN master control register, Address offset: 0x00 */
+ __IO uint32_t MSR; /*!< CAN master status register, Address offset: 0x04 */
+ __IO uint32_t TSR; /*!< CAN transmit status register, Address offset: 0x08 */
+ __IO uint32_t RF0R; /*!< CAN receive FIFO 0 register, Address offset: 0x0C */
+ __IO uint32_t RF1R; /*!< CAN receive FIFO 1 register, Address offset: 0x10 */
+ __IO uint32_t IER; /*!< CAN interrupt enable register, Address offset: 0x14 */
+ __IO uint32_t ESR; /*!< CAN error status register, Address offset: 0x18 */
+ __IO uint32_t BTR; /*!< CAN bit timing register, Address offset: 0x1C */
+ uint32_t RESERVED0[88]; /*!< Reserved, 0x020 - 0x17F */
+ CAN_TxMailBox_TypeDef sTxMailBox[3]; /*!< CAN Tx MailBox, Address offset: 0x180 - 0x1AC */
+ CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; /*!< CAN FIFO MailBox, Address offset: 0x1B0 - 0x1CC */
+ uint32_t RESERVED1[12]; /*!< Reserved, 0x1D0 - 0x1FF */
+ __IO uint32_t FMR; /*!< CAN filter master register, Address offset: 0x200 */
+ __IO uint32_t FM1R; /*!< CAN filter mode register, Address offset: 0x204 */
+ uint32_t RESERVED2; /*!< Reserved, 0x208 */
+ __IO uint32_t FS1R; /*!< CAN filter scale register, Address offset: 0x20C */
+ uint32_t RESERVED3; /*!< Reserved, 0x210 */
+ __IO uint32_t FFA1R; /*!< CAN filter FIFO assignment register, Address offset: 0x214 */
+ uint32_t RESERVED4; /*!< Reserved, 0x218 */
+ __IO uint32_t FA1R; /*!< CAN filter activation register, Address offset: 0x21C */
+ uint32_t RESERVED5[8]; /*!< Reserved, 0x220-0x23F */
+ CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register, Address offset: 0x240-0x31C */
+} CAN_TypeDef;
+
+/**
+ * @brief CRC calculation unit
+ */
+
+typedef struct
+{
+ __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
+ __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
+ uint8_t RESERVED0; /*!< Reserved, 0x05 */
+ uint16_t RESERVED1; /*!< Reserved, 0x06 */
+ __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
+}CRC_TypeDef;
+
+/**
+ * @brief DFSDM module registers
+ */
+typedef struct
+{
+ __IO uint32_t FLTCR1; /*!< DFSDM control register1, Address offset: 0x100 */
+ __IO uint32_t FLTCR2; /*!< DFSDM control register2, Address offset: 0x104 */
+ __IO uint32_t FLTISR; /*!< DFSDM interrupt and status register, Address offset: 0x108 */
+ __IO uint32_t FLTICR; /*!< DFSDM interrupt flag clear register, Address offset: 0x10C */
+ __IO uint32_t FLTJCHGR; /*!< DFSDM injected channel group selection register, Address offset: 0x110 */
+ __IO uint32_t FLTFCR; /*!< DFSDM filter control register, Address offset: 0x114 */
+ __IO uint32_t FLTJDATAR; /*!< DFSDM data register for injected group, Address offset: 0x118 */
+ __IO uint32_t FLTRDATAR; /*!< DFSDM data register for regular group, Address offset: 0x11C */
+ __IO uint32_t FLTAWHTR; /*!< DFSDM analog watchdog high threshold register, Address offset: 0x120 */
+ __IO uint32_t FLTAWLTR; /*!< DFSDM analog watchdog low threshold register, Address offset: 0x124 */
+ __IO uint32_t FLTAWSR; /*!< DFSDM analog watchdog status register Address offset: 0x128 */
+ __IO uint32_t FLTAWCFR; /*!< DFSDM analog watchdog clear flag register Address offset: 0x12C */
+ __IO uint32_t FLTEXMAX; /*!< DFSDM extreme detector maximum register, Address offset: 0x130 */
+ __IO uint32_t FLTEXMIN; /*!< DFSDM extreme detector minimum register Address offset: 0x134 */
+ __IO uint32_t FLTCNVTIMR; /*!< DFSDM conversion timer, Address offset: 0x138 */
+} DFSDM_Filter_TypeDef;
+
+/**
+ * @brief DFSDM channel configuration registers
+ */
+typedef struct
+{
+ __IO uint32_t CHCFGR1; /*!< DFSDM channel configuration register1, Address offset: 0x00 */
+ __IO uint32_t CHCFGR2; /*!< DFSDM channel configuration register2, Address offset: 0x04 */
+ __IO uint32_t CHAWSCDR; /*!< DFSDM channel analog watchdog and
+ short circuit detector register, Address offset: 0x08 */
+ __IO uint32_t CHWDATAR; /*!< DFSDM channel watchdog filter data register, Address offset: 0x0C */
+ __IO uint32_t CHDATINR; /*!< DFSDM channel data input register, Address offset: 0x10 */
+} DFSDM_Channel_TypeDef;
+
+/**
+ * @brief Debug MCU
+ */
+typedef struct
+{
+ __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
+ __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
+ __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */
+ __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */
+}DBGMCU_TypeDef;
+
+
+/**
+ * @brief DMA Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< DMA stream x configuration register */
+ __IO uint32_t NDTR; /*!< DMA stream x number of data register */
+ __IO uint32_t PAR; /*!< DMA stream x peripheral address register */
+ __IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */
+ __IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */
+ __IO uint32_t FCR; /*!< DMA stream x FIFO control register */
+} DMA_Stream_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t LISR; /*!< DMA low interrupt status register, Address offset: 0x00 */
+ __IO uint32_t HISR; /*!< DMA high interrupt status register, Address offset: 0x04 */
+ __IO uint32_t LIFCR; /*!< DMA low interrupt flag clear register, Address offset: 0x08 */
+ __IO uint32_t HIFCR; /*!< DMA high interrupt flag clear register, Address offset: 0x0C */
+} DMA_TypeDef;
+
+
+/**
+ * @brief External Interrupt/Event Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t IMR; /*!< EXTI Interrupt mask register, Address offset: 0x00 */
+ __IO uint32_t EMR; /*!< EXTI Event mask register, Address offset: 0x04 */
+ __IO uint32_t RTSR; /*!< EXTI Rising trigger selection register, Address offset: 0x08 */
+ __IO uint32_t FTSR; /*!< EXTI Falling trigger selection register, Address offset: 0x0C */
+ __IO uint32_t SWIER; /*!< EXTI Software interrupt event register, Address offset: 0x10 */
+ __IO uint32_t PR; /*!< EXTI Pending register, Address offset: 0x14 */
+} EXTI_TypeDef;
+
+/**
+ * @brief FLASH Registers
+ */
+
+typedef struct
+{
+ __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */
+ __IO uint32_t KEYR; /*!< FLASH key register, Address offset: 0x04 */
+ __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x08 */
+ __IO uint32_t SR; /*!< FLASH status register, Address offset: 0x0C */
+ __IO uint32_t CR; /*!< FLASH control register, Address offset: 0x10 */
+ __IO uint32_t OPTCR; /*!< FLASH option control register , Address offset: 0x14 */
+ __IO uint32_t OPTCR1; /*!< FLASH option control register 1, Address offset: 0x18 */
+} FLASH_TypeDef;
+
+/**
+ * @brief General Purpose I/O
+ */
+
+typedef struct
+{
+ __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
+ __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */
+ __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */
+ __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
+ __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
+ __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
+ __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */
+ __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
+ __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */
+} GPIO_TypeDef;
+
+/**
+ * @brief System configuration controller
+ */
+typedef struct
+{
+ __IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */
+ __IO uint32_t PMC; /*!< SYSCFG peripheral mode configuration register, Address offset: 0x04 */
+ __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
+ uint32_t RESERVED[2]; /*!< Reserved, 0x18-0x1C */
+ __IO uint32_t CMPCR; /*!< SYSCFG Compensation cell control register, Address offset: 0x20 */
+ uint32_t RESERVED1[2]; /*!< Reserved, 0x24-0x28 */
+ __IO uint32_t CFGR; /*!< SYSCFG Configuration register, Address offset: 0x2C */
+} SYSCFG_TypeDef;
+
+/**
+ * @brief Inter-integrated Circuit Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */
+ __IO uint32_t OAR1; /*!< I2C Own address register 1, Address offset: 0x08 */
+ __IO uint32_t OAR2; /*!< I2C Own address register 2, Address offset: 0x0C */
+ __IO uint32_t DR; /*!< I2C Data register, Address offset: 0x10 */
+ __IO uint32_t SR1; /*!< I2C Status register 1, Address offset: 0x14 */
+ __IO uint32_t SR2; /*!< I2C Status register 2, Address offset: 0x18 */
+ __IO uint32_t CCR; /*!< I2C Clock control register, Address offset: 0x1C */
+ __IO uint32_t TRISE; /*!< I2C TRISE register, Address offset: 0x20 */
+ __IO uint32_t FLTR; /*!< I2C FLTR register, Address offset: 0x24 */
+} I2C_TypeDef;
+
+/**
+ * @brief Inter-integrated Circuit Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t CR1; /*!< FMPI2C Control register 1, Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< FMPI2C Control register 2, Address offset: 0x04 */
+ __IO uint32_t OAR1; /*!< FMPI2C Own address 1 register, Address offset: 0x08 */
+ __IO uint32_t OAR2; /*!< FMPI2C Own address 2 register, Address offset: 0x0C */
+ __IO uint32_t TIMINGR; /*!< FMPI2C Timing register, Address offset: 0x10 */
+ __IO uint32_t TIMEOUTR; /*!< FMPI2C Timeout register, Address offset: 0x14 */
+ __IO uint32_t ISR; /*!< FMPI2C Interrupt and status register, Address offset: 0x18 */
+ __IO uint32_t ICR; /*!< FMPI2C Interrupt clear register, Address offset: 0x1C */
+ __IO uint32_t PECR; /*!< FMPI2C PEC register, Address offset: 0x20 */
+ __IO uint32_t RXDR; /*!< FMPI2C Receive data register, Address offset: 0x24 */
+ __IO uint32_t TXDR; /*!< FMPI2C Transmit data register, Address offset: 0x28 */
+} FMPI2C_TypeDef;
+
+/**
+ * @brief Independent WATCHDOG
+ */
+
+typedef struct
+{
+ __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */
+ __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */
+ __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */
+ __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */
+} IWDG_TypeDef;
+
+/**
+ * @brief Power Control
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */
+ __IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */
+} PWR_TypeDef;
+
+/**
+ * @brief Reset and Clock Control
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */
+ __IO uint32_t PLLCFGR; /*!< RCC PLL configuration register, Address offset: 0x04 */
+ __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x08 */
+ __IO uint32_t CIR; /*!< RCC clock interrupt register, Address offset: 0x0C */
+ __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x10 */
+ __IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x14 */
+ uint32_t RESERVED0[2]; /*!< Reserved, 0x18-0x1C */
+ __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x20 */
+ __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x24 */
+ uint32_t RESERVED1[2]; /*!< Reserved, 0x28-0x2C */
+ __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clock register, Address offset: 0x30 */
+ __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clock register, Address offset: 0x34 */
+ uint32_t RESERVED2[2]; /*!< Reserved, 0x38-0x3C */
+ __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x40 */
+ __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x44 */
+ uint32_t RESERVED3[2]; /*!< Reserved, 0x48-0x4C */
+ __IO uint32_t AHB1LPENR; /*!< RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 */
+ __IO uint32_t AHB2LPENR; /*!< RCC AHB2 peripheral clock enable in low power mode register, Address offset: 0x54 */
+ uint32_t RESERVED4[2]; /*!< Reserved, 0x58-0x5C */
+ __IO uint32_t APB1LPENR; /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 */
+ __IO uint32_t APB2LPENR; /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 */
+ uint32_t RESERVED5[2]; /*!< Reserved, 0x68-0x6C */
+ __IO uint32_t BDCR; /*!< RCC Backup domain control register, Address offset: 0x70 */
+ __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x74 */
+ uint32_t RESERVED6[2]; /*!< Reserved, 0x78-0x7C */
+ __IO uint32_t SSCGR; /*!< RCC spread spectrum clock generation register, Address offset: 0x80 */
+ __IO uint32_t PLLI2SCFGR; /*!< RCC PLLI2S configuration register, Address offset: 0x84 */
+ uint32_t RESERVED7; /*!< Reserved, 0x84 */
+ __IO uint32_t DCKCFGR; /*!< RCC Dedicated Clocks configuration register, Address offset: 0x8C */
+ __IO uint32_t CKGATENR; /*!< RCC Clocks Gated ENable Register, Address offset: 0x90 */
+ __IO uint32_t DCKCFGR2; /*!< RCC Dedicated Clocks configuration register 2, Address offset: 0x94 */
+} RCC_TypeDef;
+
+/**
+ * @brief Real-Time Clock
+ */
+
+typedef struct
+{
+ __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
+ __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */
+ __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */
+ __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */
+ __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */
+ __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */
+ __IO uint32_t CALIBR; /*!< RTC calibration register, Address offset: 0x18 */
+ __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */
+ __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */
+ __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */
+ __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */
+ __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */
+ __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */
+ __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */
+ __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */
+ __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */
+ __IO uint32_t TAFCR; /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */
+ __IO uint32_t ALRMASSR;/*!< RTC alarm A sub second register, Address offset: 0x44 */
+ __IO uint32_t ALRMBSSR;/*!< RTC alarm B sub second register, Address offset: 0x48 */
+ uint32_t RESERVED7; /*!< Reserved, 0x4C */
+ __IO uint32_t BKP0R; /*!< RTC backup register 1, Address offset: 0x50 */
+ __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */
+ __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */
+ __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */
+ __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */
+ __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */
+ __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */
+ __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */
+ __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */
+ __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */
+ __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */
+ __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */
+ __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */
+ __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */
+ __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */
+ __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */
+ __IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */
+ __IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */
+ __IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */
+ __IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */
+} RTC_TypeDef;
+
+
+/**
+ * @brief SD host Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t POWER; /*!< SDIO power control register, Address offset: 0x00 */
+ __IO uint32_t CLKCR; /*!< SDI clock control register, Address offset: 0x04 */
+ __IO uint32_t ARG; /*!< SDIO argument register, Address offset: 0x08 */
+ __IO uint32_t CMD; /*!< SDIO command register, Address offset: 0x0C */
+ __I uint32_t RESPCMD; /*!< SDIO command response register, Address offset: 0x10 */
+ __I uint32_t RESP1; /*!< SDIO response 1 register, Address offset: 0x14 */
+ __I uint32_t RESP2; /*!< SDIO response 2 register, Address offset: 0x18 */
+ __I uint32_t RESP3; /*!< SDIO response 3 register, Address offset: 0x1C */
+ __I uint32_t RESP4; /*!< SDIO response 4 register, Address offset: 0x20 */
+ __IO uint32_t DTIMER; /*!< SDIO data timer register, Address offset: 0x24 */
+ __IO uint32_t DLEN; /*!< SDIO data length register, Address offset: 0x28 */
+ __IO uint32_t DCTRL; /*!< SDIO data control register, Address offset: 0x2C */
+ __I uint32_t DCOUNT; /*!< SDIO data counter register, Address offset: 0x30 */
+ __I uint32_t STA; /*!< SDIO status register, Address offset: 0x34 */
+ __IO uint32_t ICR; /*!< SDIO interrupt clear register, Address offset: 0x38 */
+ __IO uint32_t MASK; /*!< SDIO mask register, Address offset: 0x3C */
+ uint32_t RESERVED0[2]; /*!< Reserved, 0x40-0x44 */
+ __I uint32_t FIFOCNT; /*!< SDIO FIFO counter register, Address offset: 0x48 */
+ uint32_t RESERVED1[13]; /*!< Reserved, 0x4C-0x7C */
+ __IO uint32_t FIFO; /*!< SDIO data FIFO register, Address offset: 0x80 */
+} SDIO_TypeDef;
+
+/**
+ * @brief Serial Peripheral Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t CR1; /*!< SPI control register 1 (not used in I2S mode), Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< SPI control register 2, Address offset: 0x04 */
+ __IO uint32_t SR; /*!< SPI status register, Address offset: 0x08 */
+ __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */
+ __IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
+ __IO uint32_t RXCRCR; /*!< SPI RX CRC register (not used in I2S mode), Address offset: 0x14 */
+ __IO uint32_t TXCRCR; /*!< SPI TX CRC register (not used in I2S mode), Address offset: 0x18 */
+ __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */
+ __IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */
+} SPI_TypeDef;
+
+/**
+ * @brief TIM
+ */
+
+typedef struct
+{
+ __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
+ __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */
+ __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
+ __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
+ __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
+ __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
+ __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
+ __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
+ __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
+ __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */
+ __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
+ __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */
+ __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
+ __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
+ __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
+ __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
+ __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
+ __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
+ __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */
+ __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */
+} TIM_TypeDef;
+
+/**
+ * @brief Universal Synchronous Asynchronous Receiver Transmitter
+ */
+
+typedef struct
+{
+ __IO uint32_t SR; /*!< USART Status register, Address offset: 0x00 */
+ __IO uint32_t DR; /*!< USART Data register, Address offset: 0x04 */
+ __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x08 */
+ __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x0C */
+ __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x10 */
+ __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x14 */
+ __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x18 */
+} USART_TypeDef;
+
+/**
+ * @brief Window WATCHDOG
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
+ __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
+ __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
+} WWDG_TypeDef;
+
+
+/**
+ * @brief RNG
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */
+ __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */
+ __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */
+} RNG_TypeDef;
+
+
+/**
+ * @brief USB_OTG_Core_Registers
+ */
+typedef struct
+{
+ __IO uint32_t GOTGCTL; /*!< USB_OTG Control and Status Register 000h*/
+ __IO uint32_t GOTGINT; /*!< USB_OTG Interrupt Register 004h*/
+ __IO uint32_t GAHBCFG; /*!< Core AHB Configuration Register 008h*/
+ __IO uint32_t GUSBCFG; /*!< Core USB Configuration Register 00Ch*/
+ __IO uint32_t GRSTCTL; /*!< Core Reset Register 010h*/
+ __IO uint32_t GINTSTS; /*!< Core Interrupt Register 014h*/
+ __IO uint32_t GINTMSK; /*!< Core Interrupt Mask Register 018h*/
+ __IO uint32_t GRXSTSR; /*!< Receive Sts Q Read Register 01Ch*/
+ __IO uint32_t GRXSTSP; /*!< Receive Sts Q Read & POP Register 020h*/
+ __IO uint32_t GRXFSIZ; /*!< Receive FIFO Size Register 024h*/
+ __IO uint32_t DIEPTXF0_HNPTXFSIZ; /*!< EP0 / Non Periodic Tx FIFO Size Register 028h*/
+ __IO uint32_t HNPTXSTS; /*!< Non Periodic Tx FIFO/Queue Sts reg 02Ch*/
+ uint32_t Reserved30[2]; /*!< Reserved 030h*/
+ __IO uint32_t GCCFG; /*!< General Purpose IO Register 038h*/
+ __IO uint32_t CID; /*!< User ID Register 03Ch*/
+ uint32_t Reserved5[3]; /*!< Reserved 040h-048h*/
+ __IO uint32_t GHWCFG3; /*!< User HW config3 04Ch*/
+ uint32_t Reserved6; /*!< Reserved 050h*/
+ __IO uint32_t GLPMCFG; /*!< LPM Register 054h*/
+ uint32_t Reserved; /*!< Reserved 058h */
+ __IO uint32_t GDFIFOCFG; /*!< DFIFO Software Config Register 05Ch*/
+ uint32_t Reserved43[40]; /*!< Reserved 058h-0FFh*/
+ __IO uint32_t HPTXFSIZ; /*!< Host Periodic Tx FIFO Size Reg 100h*/
+ __IO uint32_t DIEPTXF[0x0F]; /*!< dev Periodic Transmit FIFO */
+} USB_OTG_GlobalTypeDef;
+
+
+/**
+ * @brief USB_OTG_device_Registers
+ */
+typedef struct
+{
+ __IO uint32_t DCFG; /*!< dev Configuration Register 800h */
+ __IO uint32_t DCTL; /*!< dev Control Register 804h */
+ __IO uint32_t DSTS; /*!< dev Status Register (RO) 808h */
+ uint32_t Reserved0C; /*!< Reserved 80Ch */
+ __IO uint32_t DIEPMSK; /*!< dev IN Endpoint Mask 810h */
+ __IO uint32_t DOEPMSK; /*!< dev OUT Endpoint Mask 814h */
+ __IO uint32_t DAINT; /*!< dev All Endpoints Itr Reg 818h */
+ __IO uint32_t DAINTMSK; /*!< dev All Endpoints Itr Mask 81Ch */
+ uint32_t Reserved20; /*!< Reserved 820h */
+ uint32_t Reserved9; /*!< Reserved 824h */
+ __IO uint32_t DVBUSDIS; /*!< dev VBUS discharge Register 828h */
+ __IO uint32_t DVBUSPULSE; /*!< dev VBUS Pulse Register 82Ch */
+ __IO uint32_t DTHRCTL; /*!< dev threshold 830h */
+ __IO uint32_t DIEPEMPMSK; /*!< dev empty msk 834h */
+ __IO uint32_t DEACHINT; /*!< dedicated EP interrupt 838h */
+ __IO uint32_t DEACHMSK; /*!< dedicated EP msk 83Ch */
+ uint32_t Reserved40; /*!< dedicated EP mask 840h */
+ __IO uint32_t DINEP1MSK; /*!< dedicated EP mask 844h */
+ uint32_t Reserved44[15]; /*!< Reserved 844-87Ch */
+ __IO uint32_t DOUTEP1MSK; /*!< dedicated EP msk 884h */
+} USB_OTG_DeviceTypeDef;
+
+
+/**
+ * @brief USB_OTG_IN_Endpoint-Specific_Register
+ */
+typedef struct
+{
+ __IO uint32_t DIEPCTL; /*!< dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h */
+ uint32_t Reserved04; /*!< Reserved 900h + (ep_num * 20h) + 04h */
+ __IO uint32_t DIEPINT; /*!< dev IN Endpoint Itr Reg 900h + (ep_num * 20h) + 08h */
+ uint32_t Reserved0C; /*!< Reserved 900h + (ep_num * 20h) + 0Ch */
+ __IO uint32_t DIEPTSIZ; /*!< IN Endpoint Txfer Size 900h + (ep_num * 20h) + 10h */
+ __IO uint32_t DIEPDMA; /*!< IN Endpoint DMA Address Reg 900h + (ep_num * 20h) + 14h */
+ __IO uint32_t DTXFSTS; /*!< IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h */
+ uint32_t Reserved18; /*!< Reserved 900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch */
+} USB_OTG_INEndpointTypeDef;
+
+
+/**
+ * @brief USB_OTG_OUT_Endpoint-Specific_Registers
+ */
+typedef struct
+{
+ __IO uint32_t DOEPCTL; /*!< dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h */
+ uint32_t Reserved04; /*!< Reserved B00h + (ep_num * 20h) + 04h */
+ __IO uint32_t DOEPINT; /*!< dev OUT Endpoint Itr Reg B00h + (ep_num * 20h) + 08h */
+ uint32_t Reserved0C; /*!< Reserved B00h + (ep_num * 20h) + 0Ch */
+ __IO uint32_t DOEPTSIZ; /*!< dev OUT Endpoint Txfer Size B00h + (ep_num * 20h) + 10h */
+ __IO uint32_t DOEPDMA; /*!< dev OUT Endpoint DMA Address B00h + (ep_num * 20h) + 14h */
+ uint32_t Reserved18[2]; /*!< Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch */
+} USB_OTG_OUTEndpointTypeDef;
+
+
+/**
+ * @brief USB_OTG_Host_Mode_Register_Structures
+ */
+typedef struct
+{
+ __IO uint32_t HCFG; /*!< Host Configuration Register 400h */
+ __IO uint32_t HFIR; /*!< Host Frame Interval Register 404h */
+ __IO uint32_t HFNUM; /*!< Host Frame Nbr/Frame Remaining 408h */
+ uint32_t Reserved40C; /*!< Reserved 40Ch */
+ __IO uint32_t HPTXSTS; /*!< Host Periodic Tx FIFO/ Queue Status 410h */
+ __IO uint32_t HAINT; /*!< Host All Channels Interrupt Register 414h */
+ __IO uint32_t HAINTMSK; /*!< Host All Channels Interrupt Mask 418h */
+} USB_OTG_HostTypeDef;
+
+
+/**
+ * @brief USB_OTG_Host_Channel_Specific_Registers
+ */
+typedef struct
+{
+ __IO uint32_t HCCHAR; /*!< Host Channel Characteristics Register 500h */
+ __IO uint32_t HCSPLT; /*!< Host Channel Split Control Register 504h */
+ __IO uint32_t HCINT; /*!< Host Channel Interrupt Register 508h */
+ __IO uint32_t HCINTMSK; /*!< Host Channel Interrupt Mask Register 50Ch */
+ __IO uint32_t HCTSIZ; /*!< Host Channel Transfer Size Register 510h */
+ __IO uint32_t HCDMA; /*!< Host Channel DMA Address Register 514h */
+ uint32_t Reserved[2]; /*!< Reserved */
+} USB_OTG_HostChannelTypeDef;
+
+
+/**
+ * @brief Peripheral_memory_map
+ */
+#define FLASH_BASE 0x08000000U /*!< FLASH(up to 1 MB) base address in the alias region */
+#define SRAM1_BASE 0x20000000U /*!< SRAM1(256 KB) base address in the alias region */
+#define PERIPH_BASE 0x40000000U /*!< Peripheral base address in the alias region */
+
+#define SRAM1_BB_BASE 0x22000000U /*!< SRAM1(256 KB) base address in the bit-band region */
+#define PERIPH_BB_BASE 0x42000000U /*!< Peripheral base address in the bit-band region */
+#define FLASH_END 0x080FFFFFU /*!< FLASH end address */
+
+/* Legacy defines */
+#define SRAM_BASE SRAM1_BASE
+#define SRAM_BB_BASE SRAM1_BB_BASE
+
+/*!< Peripheral memory map */
+#define APB1PERIPH_BASE PERIPH_BASE
+#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000U)
+#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000U)
+#define AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000U)
+
+/*!< APB1 peripherals */
+#define TIM2_BASE (APB1PERIPH_BASE + 0x0000U)
+#define TIM3_BASE (APB1PERIPH_BASE + 0x0400U)
+#define TIM4_BASE (APB1PERIPH_BASE + 0x0800U)
+#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00U)
+#define TIM6_BASE (APB1PERIPH_BASE + 0x1000U)
+#define TIM7_BASE (APB1PERIPH_BASE + 0x1400U)
+#define TIM12_BASE (APB1PERIPH_BASE + 0x1800U)
+#define TIM13_BASE (APB1PERIPH_BASE + 0x1C00U)
+#define TIM14_BASE (APB1PERIPH_BASE + 0x2000U)
+#define RTC_BASE (APB1PERIPH_BASE + 0x2800U)
+#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00U)
+#define IWDG_BASE (APB1PERIPH_BASE + 0x3000U)
+#define I2S2ext_BASE (APB1PERIPH_BASE + 0x3400U)
+#define SPI2_BASE (APB1PERIPH_BASE + 0x3800U)
+#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00U)
+#define I2S3ext_BASE (APB1PERIPH_BASE + 0x4000U)
+#define USART2_BASE (APB1PERIPH_BASE + 0x4400U)
+#define I2C1_BASE (APB1PERIPH_BASE + 0x5400U)
+#define I2C2_BASE (APB1PERIPH_BASE + 0x5800U)
+#define I2C3_BASE (APB1PERIPH_BASE + 0x5C00U)
+#define FMPI2C1_BASE (APB1PERIPH_BASE + 0x6000U)
+#define CAN1_BASE (APB1PERIPH_BASE + 0x6400U)
+#define CAN2_BASE (APB1PERIPH_BASE + 0x6800U)
+#define PWR_BASE (APB1PERIPH_BASE + 0x7000U)
+
+/*!< APB2 peripherals */
+#define TIM1_BASE (APB2PERIPH_BASE + 0x0000U)
+#define TIM8_BASE (APB2PERIPH_BASE + 0x0400U)
+#define USART1_BASE (APB2PERIPH_BASE + 0x1000U)
+#define USART6_BASE (APB2PERIPH_BASE + 0x1400U)
+#define ADC1_BASE (APB2PERIPH_BASE + 0x2000U)
+#define ADC_BASE (APB2PERIPH_BASE + 0x2300U)
+#define SDIO_BASE (APB2PERIPH_BASE + 0x2C00U)
+#define SPI1_BASE (APB2PERIPH_BASE + 0x3000U)
+#define SPI4_BASE (APB2PERIPH_BASE + 0x3400U)
+#define SYSCFG_BASE (APB2PERIPH_BASE + 0x3800U)
+#define EXTI_BASE (APB2PERIPH_BASE + 0x3C00U)
+#define TIM9_BASE (APB2PERIPH_BASE + 0x4000U)
+#define TIM10_BASE (APB2PERIPH_BASE + 0x4400U)
+#define TIM11_BASE (APB2PERIPH_BASE + 0x4800U)
+#define SPI5_BASE (APB2PERIPH_BASE + 0x5000U)
+#define DFSDM1_BASE (APB2PERIPH_BASE + 0x6000U)
+#define DFSDM1_Channel0_BASE (DFSDM1_BASE + 0x00U)
+#define DFSDM1_Channel1_BASE (DFSDM1_BASE + 0x20U)
+#define DFSDM1_Channel2_BASE (DFSDM1_BASE + 0x40U)
+#define DFSDM1_Channel3_BASE (DFSDM1_BASE + 0x60U)
+#define DFSDM1_Filter0_BASE (DFSDM1_BASE + 0x100U)
+#define DFSDM1_Filter1_BASE (DFSDM1_BASE + 0x180U)
+
+/*!< AHB1 peripherals */
+#define GPIOA_BASE (AHB1PERIPH_BASE + 0x0000U)
+#define GPIOB_BASE (AHB1PERIPH_BASE + 0x0400U)
+#define GPIOC_BASE (AHB1PERIPH_BASE + 0x0800U)
+#define GPIOD_BASE (AHB1PERIPH_BASE + 0x0C00U)
+#define GPIOE_BASE (AHB1PERIPH_BASE + 0x1000U)
+#define GPIOF_BASE (AHB1PERIPH_BASE + 0x1400U)
+#define GPIOG_BASE (AHB1PERIPH_BASE + 0x1800U)
+#define GPIOH_BASE (AHB1PERIPH_BASE + 0x1C00U)
+#define CRC_BASE (AHB1PERIPH_BASE + 0x3000U)
+#define RCC_BASE (AHB1PERIPH_BASE + 0x3800U)
+#define FLASH_R_BASE (AHB1PERIPH_BASE + 0x3C00U)
+#define DMA1_BASE (AHB1PERIPH_BASE + 0x6000U)
+#define DMA1_Stream0_BASE (DMA1_BASE + 0x010U)
+#define DMA1_Stream1_BASE (DMA1_BASE + 0x028U)
+#define DMA1_Stream2_BASE (DMA1_BASE + 0x040U)
+#define DMA1_Stream3_BASE (DMA1_BASE + 0x058U)
+#define DMA1_Stream4_BASE (DMA1_BASE + 0x070U)
+#define DMA1_Stream5_BASE (DMA1_BASE + 0x088U)
+#define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0U)
+#define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8U)
+#define DMA2_BASE (AHB1PERIPH_BASE + 0x6400U)
+#define DMA2_Stream0_BASE (DMA2_BASE + 0x010U)
+#define DMA2_Stream1_BASE (DMA2_BASE + 0x028U)
+#define DMA2_Stream2_BASE (DMA2_BASE + 0x040U)
+#define DMA2_Stream3_BASE (DMA2_BASE + 0x058U)
+#define DMA2_Stream4_BASE (DMA2_BASE + 0x070U)
+#define DMA2_Stream5_BASE (DMA2_BASE + 0x088U)
+#define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0U)
+#define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8U)
+
+/*!< AHB2 peripherals */
+#define RNG_BASE (AHB2PERIPH_BASE + 0x60800U)
+
+/* Debug MCU registers base address */
+#define DBGMCU_BASE 0xE0042000U
+
+/*!< USB registers base address */
+#define USB_OTG_FS_PERIPH_BASE 0x50000000U
+
+#define USB_OTG_GLOBAL_BASE 0x000U
+#define USB_OTG_DEVICE_BASE 0x800U
+#define USB_OTG_IN_ENDPOINT_BASE 0x900U
+#define USB_OTG_OUT_ENDPOINT_BASE 0xB00U
+#define USB_OTG_EP_REG_SIZE 0x20U
+#define USB_OTG_HOST_BASE 0x400U
+#define USB_OTG_HOST_PORT_BASE 0x440U
+#define USB_OTG_HOST_CHANNEL_BASE 0x500U
+#define USB_OTG_HOST_CHANNEL_SIZE 0x20U
+#define USB_OTG_PCGCCTL_BASE 0xE00U
+#define USB_OTG_FIFO_BASE 0x1000U
+#define USB_OTG_FIFO_SIZE 0x1000U
+
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_declaration
+ * @{
+ */
+#define TIM2 ((TIM_TypeDef *) TIM2_BASE)
+#define TIM3 ((TIM_TypeDef *) TIM3_BASE)
+#define TIM4 ((TIM_TypeDef *) TIM4_BASE)
+#define TIM5 ((TIM_TypeDef *) TIM5_BASE)
+#define TIM6 ((TIM_TypeDef *) TIM6_BASE)
+#define TIM7 ((TIM_TypeDef *) TIM7_BASE)
+#define TIM12 ((TIM_TypeDef *) TIM12_BASE)
+#define TIM13 ((TIM_TypeDef *) TIM13_BASE)
+#define TIM14 ((TIM_TypeDef *) TIM14_BASE)
+#define RTC ((RTC_TypeDef *) RTC_BASE)
+#define WWDG ((WWDG_TypeDef *) WWDG_BASE)
+#define IWDG ((IWDG_TypeDef *) IWDG_BASE)
+#define I2S2ext ((SPI_TypeDef *) I2S2ext_BASE)
+#define SPI2 ((SPI_TypeDef *) SPI2_BASE)
+#define SPI3 ((SPI_TypeDef *) SPI3_BASE)
+#define I2S3ext ((SPI_TypeDef *) I2S3ext_BASE)
+#define USART2 ((USART_TypeDef *) USART2_BASE)
+#define I2C1 ((I2C_TypeDef *) I2C1_BASE)
+#define I2C2 ((I2C_TypeDef *) I2C2_BASE)
+#define I2C3 ((I2C_TypeDef *) I2C3_BASE)
+#define FMPI2C1 ((FMPI2C_TypeDef *) FMPI2C1_BASE)
+#define CAN1 ((CAN_TypeDef *) CAN1_BASE)
+#define CAN2 ((CAN_TypeDef *) CAN2_BASE)
+#define PWR ((PWR_TypeDef *) PWR_BASE)
+#define TIM1 ((TIM_TypeDef *) TIM1_BASE)
+#define TIM8 ((TIM_TypeDef *) TIM8_BASE)
+#define USART1 ((USART_TypeDef *) USART1_BASE)
+#define USART6 ((USART_TypeDef *) USART6_BASE)
+#define ADC ((ADC_Common_TypeDef *) ADC_BASE)
+#define ADC1 ((ADC_TypeDef *) ADC1_BASE)
+#define SDIO ((SDIO_TypeDef *) SDIO_BASE)
+#define SPI1 ((SPI_TypeDef *) SPI1_BASE)
+#define SPI4 ((SPI_TypeDef *) SPI4_BASE)
+#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
+#define EXTI ((EXTI_TypeDef *) EXTI_BASE)
+#define TIM9 ((TIM_TypeDef *) TIM9_BASE)
+#define TIM10 ((TIM_TypeDef *) TIM10_BASE)
+#define TIM11 ((TIM_TypeDef *) TIM11_BASE)
+#define SPI5 ((SPI_TypeDef *) SPI5_BASE)
+#define DFSDM1_Channel0 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel0_BASE)
+#define DFSDM1_Channel1 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel1_BASE)
+#define DFSDM1_Channel2 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel2_BASE)
+#define DFSDM1_Channel3 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel3_BASE)
+#define DFSDM1_Filter0 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter0_BASE)
+#define DFSDM1_Filter1 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter1_BASE)
+#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
+#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
+#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
+#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
+#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
+#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
+#define GPIOG ((GPIO_TypeDef *) GPIOG_BASE)
+#define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
+#define CRC ((CRC_TypeDef *) CRC_BASE)
+#define RCC ((RCC_TypeDef *) RCC_BASE)
+#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
+#define DMA1 ((DMA_TypeDef *) DMA1_BASE)
+#define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)
+#define DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)
+#define DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)
+#define DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)
+#define DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)
+#define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)
+#define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)
+#define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)
+#define DMA2 ((DMA_TypeDef *) DMA2_BASE)
+#define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)
+#define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
+#define DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)
+#define DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)
+#define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)
+#define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)
+#define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)
+#define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)
+#define RNG ((RNG_TypeDef *) RNG_BASE)
+
+#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
+
+#define USB_OTG_FS ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE)
+
+/**
+ * @}
+ */
+
+/** @addtogroup Exported_constants
+ * @{
+ */
+
+ /** @addtogroup Peripheral_Registers_Bits_Definition
+ * @{
+ */
+
+/******************************************************************************/
+/* Peripheral Registers_Bits_Definition */
+/******************************************************************************/
+
+/******************************************************************************/
+/* */
+/* Analog to Digital Converter */
+/* */
+/******************************************************************************/
+/******************** Bit definition for ADC_SR register ********************/
+#define ADC_SR_AWD 0x00000001U /*!<Analog watchdog flag */
+#define ADC_SR_EOC 0x00000002U /*!<End of conversion */
+#define ADC_SR_JEOC 0x00000004U /*!<Injected channel end of conversion */
+#define ADC_SR_JSTRT 0x00000008U /*!<Injected channel Start flag */
+#define ADC_SR_STRT 0x00000010U /*!<Regular channel Start flag */
+#define ADC_SR_OVR 0x00000020U /*!<Overrun flag */
+
+/******************* Bit definition for ADC_CR1 register ********************/
+#define ADC_CR1_AWDCH 0x0000001FU /*!<AWDCH[4:0] bits (Analog watchdog channel select bits) */
+#define ADC_CR1_AWDCH_0 0x00000001U /*!<Bit 0 */
+#define ADC_CR1_AWDCH_1 0x00000002U /*!<Bit 1 */
+#define ADC_CR1_AWDCH_2 0x00000004U /*!<Bit 2 */
+#define ADC_CR1_AWDCH_3 0x00000008U /*!<Bit 3 */
+#define ADC_CR1_AWDCH_4 0x00000010U /*!<Bit 4 */
+#define ADC_CR1_EOCIE 0x00000020U /*!<Interrupt enable for EOC */
+#define ADC_CR1_AWDIE 0x00000040U /*!<AAnalog Watchdog interrupt enable */
+#define ADC_CR1_JEOCIE 0x00000080U /*!<Interrupt enable for injected channels */
+#define ADC_CR1_SCAN 0x00000100U /*!<Scan mode */
+#define ADC_CR1_AWDSGL 0x00000200U /*!<Enable the watchdog on a single channel in scan mode */
+#define ADC_CR1_JAUTO 0x00000400U /*!<Automatic injected group conversion */
+#define ADC_CR1_DISCEN 0x00000800U /*!<Discontinuous mode on regular channels */
+#define ADC_CR1_JDISCEN 0x00001000U /*!<Discontinuous mode on injected channels */
+#define ADC_CR1_DISCNUM 0x0000E000U /*!<DISCNUM[2:0] bits (Discontinuous mode channel count) */
+#define ADC_CR1_DISCNUM_0 0x00002000U /*!<Bit 0 */
+#define ADC_CR1_DISCNUM_1 0x00004000U /*!<Bit 1 */
+#define ADC_CR1_DISCNUM_2 0x00008000U /*!<Bit 2 */
+#define ADC_CR1_JAWDEN 0x00400000U /*!<Analog watchdog enable on injected channels */
+#define ADC_CR1_AWDEN 0x00800000U /*!<Analog watchdog enable on regular channels */
+#define ADC_CR1_RES 0x03000000U /*!<RES[2:0] bits (Resolution) */
+#define ADC_CR1_RES_0 0x01000000U /*!<Bit 0 */
+#define ADC_CR1_RES_1 0x02000000U /*!<Bit 1 */
+#define ADC_CR1_OVRIE 0x04000000U /*!<overrun interrupt enable */
+
+/******************* Bit definition for ADC_CR2 register ********************/
+#define ADC_CR2_ADON 0x00000001U /*!<A/D Converter ON / OFF */
+#define ADC_CR2_CONT 0x00000002U /*!<Continuous Conversion */
+#define ADC_CR2_DMA 0x00000100U /*!<Direct Memory access mode */
+#define ADC_CR2_DDS 0x00000200U /*!<DMA disable selection (Single ADC) */
+#define ADC_CR2_EOCS 0x00000400U /*!<End of conversion selection */
+#define ADC_CR2_ALIGN 0x00000800U /*!<Data Alignment */
+#define ADC_CR2_JEXTSEL 0x000F0000U /*!<JEXTSEL[3:0] bits (External event select for injected group) */
+#define ADC_CR2_JEXTSEL_0 0x00010000U /*!<Bit 0 */
+#define ADC_CR2_JEXTSEL_1 0x00020000U /*!<Bit 1 */
+#define ADC_CR2_JEXTSEL_2 0x00040000U /*!<Bit 2 */
+#define ADC_CR2_JEXTSEL_3 0x00080000U /*!<Bit 3 */
+#define ADC_CR2_JEXTEN 0x00300000U /*!<JEXTEN[1:0] bits (External Trigger Conversion mode for injected channelsp) */
+#define ADC_CR2_JEXTEN_0 0x00100000U /*!<Bit 0 */
+#define ADC_CR2_JEXTEN_1 0x00200000U /*!<Bit 1 */
+#define ADC_CR2_JSWSTART 0x00400000U /*!<Start Conversion of injected channels */
+#define ADC_CR2_EXTSEL 0x0F000000U /*!<EXTSEL[3:0] bits (External Event Select for regular group) */
+#define ADC_CR2_EXTSEL_0 0x01000000U /*!<Bit 0 */
+#define ADC_CR2_EXTSEL_1 0x02000000U /*!<Bit 1 */
+#define ADC_CR2_EXTSEL_2 0x04000000U /*!<Bit 2 */
+#define ADC_CR2_EXTSEL_3 0x08000000U /*!<Bit 3 */
+#define ADC_CR2_EXTEN 0x30000000U /*!<EXTEN[1:0] bits (External Trigger Conversion mode for regular channelsp) */
+#define ADC_CR2_EXTEN_0 0x10000000U /*!<Bit 0 */
+#define ADC_CR2_EXTEN_1 0x20000000U /*!<Bit 1 */
+#define ADC_CR2_SWSTART 0x40000000U /*!<Start Conversion of regular channels */
+
+/****************** Bit definition for ADC_SMPR1 register *******************/
+#define ADC_SMPR1_SMP10 0x00000007U /*!<SMP10[2:0] bits (Channel 10 Sample time selection) */
+#define ADC_SMPR1_SMP10_0 0x00000001U /*!<Bit 0 */
+#define ADC_SMPR1_SMP10_1 0x00000002U /*!<Bit 1 */
+#define ADC_SMPR1_SMP10_2 0x00000004U /*!<Bit 2 */
+#define ADC_SMPR1_SMP11 0x00000038U /*!<SMP11[2:0] bits (Channel 11 Sample time selection) */
+#define ADC_SMPR1_SMP11_0 0x00000008U /*!<Bit 0 */
+#define ADC_SMPR1_SMP11_1 0x00000010U /*!<Bit 1 */
+#define ADC_SMPR1_SMP11_2 0x00000020U /*!<Bit 2 */
+#define ADC_SMPR1_SMP12 0x000001C0U /*!<SMP12[2:0] bits (Channel 12 Sample time selection) */
+#define ADC_SMPR1_SMP12_0 0x00000040U /*!<Bit 0 */
+#define ADC_SMPR1_SMP12_1 0x00000080U /*!<Bit 1 */
+#define ADC_SMPR1_SMP12_2 0x00000100U /*!<Bit 2 */
+#define ADC_SMPR1_SMP13 0x00000E00U /*!<SMP13[2:0] bits (Channel 13 Sample time selection) */
+#define ADC_SMPR1_SMP13_0 0x00000200U /*!<Bit 0 */
+#define ADC_SMPR1_SMP13_1 0x00000400U /*!<Bit 1 */
+#define ADC_SMPR1_SMP13_2 0x00000800U /*!<Bit 2 */
+#define ADC_SMPR1_SMP14 0x00007000U /*!<SMP14[2:0] bits (Channel 14 Sample time selection) */
+#define ADC_SMPR1_SMP14_0 0x00001000U /*!<Bit 0 */
+#define ADC_SMPR1_SMP14_1 0x00002000U /*!<Bit 1 */
+#define ADC_SMPR1_SMP14_2 0x00004000U /*!<Bit 2 */
+#define ADC_SMPR1_SMP15 0x00038000U /*!<SMP15[2:0] bits (Channel 15 Sample time selection) */
+#define ADC_SMPR1_SMP15_0 0x00008000U /*!<Bit 0 */
+#define ADC_SMPR1_SMP15_1 0x00010000U /*!<Bit 1 */
+#define ADC_SMPR1_SMP15_2 0x00020000U /*!<Bit 2 */
+#define ADC_SMPR1_SMP16 0x001C0000U /*!<SMP16[2:0] bits (Channel 16 Sample time selection) */
+#define ADC_SMPR1_SMP16_0 0x00040000U /*!<Bit 0 */
+#define ADC_SMPR1_SMP16_1 0x00080000U /*!<Bit 1 */
+#define ADC_SMPR1_SMP16_2 0x00100000U /*!<Bit 2 */
+#define ADC_SMPR1_SMP17 0x00E00000U /*!<SMP17[2:0] bits (Channel 17 Sample time selection) */
+#define ADC_SMPR1_SMP17_0 0x00200000U /*!<Bit 0 */
+#define ADC_SMPR1_SMP17_1 0x00400000U /*!<Bit 1 */
+#define ADC_SMPR1_SMP17_2 0x00800000U /*!<Bit 2 */
+#define ADC_SMPR1_SMP18 0x07000000U /*!<SMP18[2:0] bits (Channel 18 Sample time selection) */
+#define ADC_SMPR1_SMP18_0 0x01000000U /*!<Bit 0 */
+#define ADC_SMPR1_SMP18_1 0x02000000U /*!<Bit 1 */
+#define ADC_SMPR1_SMP18_2 0x04000000U /*!<Bit 2 */
+
+/****************** Bit definition for ADC_SMPR2 register *******************/
+#define ADC_SMPR2_SMP0 0x00000007U /*!<SMP0[2:0] bits (Channel 0 Sample time selection) */
+#define ADC_SMPR2_SMP0_0 0x00000001U /*!<Bit 0 */
+#define ADC_SMPR2_SMP0_1 0x00000002U /*!<Bit 1 */
+#define ADC_SMPR2_SMP0_2 0x00000004U /*!<Bit 2 */
+#define ADC_SMPR2_SMP1 0x00000038U /*!<SMP1[2:0] bits (Channel 1 Sample time selection) */
+#define ADC_SMPR2_SMP1_0 0x00000008U /*!<Bit 0 */
+#define ADC_SMPR2_SMP1_1 0x00000010U /*!<Bit 1 */
+#define ADC_SMPR2_SMP1_2 0x00000020U /*!<Bit 2 */
+#define ADC_SMPR2_SMP2 0x000001C0U /*!<SMP2[2:0] bits (Channel 2 Sample time selection) */
+#define ADC_SMPR2_SMP2_0 0x00000040U /*!<Bit 0 */
+#define ADC_SMPR2_SMP2_1 0x00000080U /*!<Bit 1 */
+#define ADC_SMPR2_SMP2_2 0x00000100U /*!<Bit 2 */
+#define ADC_SMPR2_SMP3 0x00000E00U /*!<SMP3[2:0] bits (Channel 3 Sample time selection) */
+#define ADC_SMPR2_SMP3_0 0x00000200U /*!<Bit 0 */
+#define ADC_SMPR2_SMP3_1 0x00000400U /*!<Bit 1 */
+#define ADC_SMPR2_SMP3_2 0x00000800U /*!<Bit 2 */
+#define ADC_SMPR2_SMP4 0x00007000U /*!<SMP4[2:0] bits (Channel 4 Sample time selection) */
+#define ADC_SMPR2_SMP4_0 0x00001000U /*!<Bit 0 */
+#define ADC_SMPR2_SMP4_1 0x00002000U /*!<Bit 1 */
+#define ADC_SMPR2_SMP4_2 0x00004000U /*!<Bit 2 */
+#define ADC_SMPR2_SMP5 0x00038000U /*!<SMP5[2:0] bits (Channel 5 Sample time selection) */
+#define ADC_SMPR2_SMP5_0 0x00008000U /*!<Bit 0 */
+#define ADC_SMPR2_SMP5_1 0x00010000U /*!<Bit 1 */
+#define ADC_SMPR2_SMP5_2 0x00020000U /*!<Bit 2 */
+#define ADC_SMPR2_SMP6 0x001C0000U /*!<SMP6[2:0] bits (Channel 6 Sample time selection) */
+#define ADC_SMPR2_SMP6_0 0x00040000U /*!<Bit 0 */
+#define ADC_SMPR2_SMP6_1 0x00080000U /*!<Bit 1 */
+#define ADC_SMPR2_SMP6_2 0x00100000U /*!<Bit 2 */
+#define ADC_SMPR2_SMP7 0x00E00000U /*!<SMP7[2:0] bits (Channel 7 Sample time selection) */
+#define ADC_SMPR2_SMP7_0 0x00200000U /*!<Bit 0 */
+#define ADC_SMPR2_SMP7_1 0x00400000U /*!<Bit 1 */
+#define ADC_SMPR2_SMP7_2 0x00800000U /*!<Bit 2 */
+#define ADC_SMPR2_SMP8 0x07000000U /*!<SMP8[2:0] bits (Channel 8 Sample time selection) */
+#define ADC_SMPR2_SMP8_0 0x01000000U /*!<Bit 0 */
+#define ADC_SMPR2_SMP8_1 0x02000000U /*!<Bit 1 */
+#define ADC_SMPR2_SMP8_2 0x04000000U /*!<Bit 2 */
+#define ADC_SMPR2_SMP9 0x38000000U /*!<SMP9[2:0] bits (Channel 9 Sample time selection) */
+#define ADC_SMPR2_SMP9_0 0x08000000U /*!<Bit 0 */
+#define ADC_SMPR2_SMP9_1 0x10000000U /*!<Bit 1 */
+#define ADC_SMPR2_SMP9_2 0x20000000U /*!<Bit 2 */
+
+/****************** Bit definition for ADC_JOFR1 register *******************/
+#define ADC_JOFR1_JOFFSET1 0x0FFFU /*!<Data offset for injected channel 1 */
+
+/****************** Bit definition for ADC_JOFR2 register *******************/
+#define ADC_JOFR2_JOFFSET2 0x0FFFU /*!<Data offset for injected channel 2 */
+
+/****************** Bit definition for ADC_JOFR3 register *******************/
+#define ADC_JOFR3_JOFFSET3 0x0FFFU /*!<Data offset for injected channel 3 */
+
+/****************** Bit definition for ADC_JOFR4 register *******************/
+#define ADC_JOFR4_JOFFSET4 0x0FFFU /*!<Data offset for injected channel 4 */
+
+/******************* Bit definition for ADC_HTR register ********************/
+#define ADC_HTR_HT 0x0FFFU /*!<Analog watchdog high threshold */
+
+/******************* Bit definition for ADC_LTR register ********************/
+#define ADC_LTR_LT 0x0FFFU /*!<Analog watchdog low threshold */
+
+/******************* Bit definition for ADC_SQR1 register *******************/
+#define ADC_SQR1_SQ13 0x0000001FU /*!<SQ13[4:0] bits (13th conversion in regular sequence) */
+#define ADC_SQR1_SQ13_0 0x00000001U /*!<Bit 0 */
+#define ADC_SQR1_SQ13_1 0x00000002U /*!<Bit 1 */
+#define ADC_SQR1_SQ13_2 0x00000004U /*!<Bit 2 */
+#define ADC_SQR1_SQ13_3 0x00000008U /*!<Bit 3 */
+#define ADC_SQR1_SQ13_4 0x00000010U /*!<Bit 4 */
+#define ADC_SQR1_SQ14 0x000003E0U /*!<SQ14[4:0] bits (14th conversion in regular sequence) */
+#define ADC_SQR1_SQ14_0 0x00000020U /*!<Bit 0 */
+#define ADC_SQR1_SQ14_1 0x00000040U /*!<Bit 1 */
+#define ADC_SQR1_SQ14_2 0x00000080U /*!<Bit 2 */
+#define ADC_SQR1_SQ14_3 0x00000100U /*!<Bit 3 */
+#define ADC_SQR1_SQ14_4 0x00000200U /*!<Bit 4 */
+#define ADC_SQR1_SQ15 0x00007C00U /*!<SQ15[4:0] bits (15th conversion in regular sequence) */
+#define ADC_SQR1_SQ15_0 0x00000400U /*!<Bit 0 */
+#define ADC_SQR1_SQ15_1 0x00000800U /*!<Bit 1 */
+#define ADC_SQR1_SQ15_2 0x00001000U /*!<Bit 2 */
+#define ADC_SQR1_SQ15_3 0x00002000U /*!<Bit 3 */
+#define ADC_SQR1_SQ15_4 0x00004000U /*!<Bit 4 */
+#define ADC_SQR1_SQ16 0x000F8000U /*!<SQ16[4:0] bits (16th conversion in regular sequence) */
+#define ADC_SQR1_SQ16_0 0x00008000U /*!<Bit 0 */
+#define ADC_SQR1_SQ16_1 0x00010000U /*!<Bit 1 */
+#define ADC_SQR1_SQ16_2 0x00020000U /*!<Bit 2 */
+#define ADC_SQR1_SQ16_3 0x00040000U /*!<Bit 3 */
+#define ADC_SQR1_SQ16_4 0x00080000U /*!<Bit 4 */
+#define ADC_SQR1_L 0x00F00000U /*!<L[3:0] bits (Regular channel sequence length) */
+#define ADC_SQR1_L_0 0x00100000U /*!<Bit 0 */
+#define ADC_SQR1_L_1 0x00200000U /*!<Bit 1 */
+#define ADC_SQR1_L_2 0x00400000U /*!<Bit 2 */
+#define ADC_SQR1_L_3 0x00800000U /*!<Bit 3 */
+
+/******************* Bit definition for ADC_SQR2 register *******************/
+#define ADC_SQR2_SQ7 0x0000001FU /*!<SQ7[4:0] bits (7th conversion in regular sequence) */
+#define ADC_SQR2_SQ7_0 0x00000001U /*!<Bit 0 */
+#define ADC_SQR2_SQ7_1 0x00000002U /*!<Bit 1 */
+#define ADC_SQR2_SQ7_2 0x00000004U /*!<Bit 2 */
+#define ADC_SQR2_SQ7_3 0x00000008U /*!<Bit 3 */
+#define ADC_SQR2_SQ7_4 0x00000010U /*!<Bit 4 */
+#define ADC_SQR2_SQ8 0x000003E0U /*!<SQ8[4:0] bits (8th conversion in regular sequence) */
+#define ADC_SQR2_SQ8_0 0x00000020U /*!<Bit 0 */
+#define ADC_SQR2_SQ8_1 0x00000040U /*!<Bit 1 */
+#define ADC_SQR2_SQ8_2 0x00000080U /*!<Bit 2 */
+#define ADC_SQR2_SQ8_3 0x00000100U /*!<Bit 3 */
+#define ADC_SQR2_SQ8_4 0x00000200U /*!<Bit 4 */
+#define ADC_SQR2_SQ9 0x00007C00U /*!<SQ9[4:0] bits (9th conversion in regular sequence) */
+#define ADC_SQR2_SQ9_0 0x00000400U /*!<Bit 0 */
+#define ADC_SQR2_SQ9_1 0x00000800U /*!<Bit 1 */
+#define ADC_SQR2_SQ9_2 0x00001000U /*!<Bit 2 */
+#define ADC_SQR2_SQ9_3 0x00002000U /*!<Bit 3 */
+#define ADC_SQR2_SQ9_4 0x00004000U /*!<Bit 4 */
+#define ADC_SQR2_SQ10 0x000F8000U /*!<SQ10[4:0] bits (10th conversion in regular sequence) */
+#define ADC_SQR2_SQ10_0 0x00008000U /*!<Bit 0 */
+#define ADC_SQR2_SQ10_1 0x00010000U /*!<Bit 1 */
+#define ADC_SQR2_SQ10_2 0x00020000U /*!<Bit 2 */
+#define ADC_SQR2_SQ10_3 0x00040000U /*!<Bit 3 */
+#define ADC_SQR2_SQ10_4 0x00080000U /*!<Bit 4 */
+#define ADC_SQR2_SQ11 0x01F00000U /*!<SQ11[4:0] bits (11th conversion in regular sequence) */
+#define ADC_SQR2_SQ11_0 0x00100000U /*!<Bit 0 */
+#define ADC_SQR2_SQ11_1 0x00200000U /*!<Bit 1 */
+#define ADC_SQR2_SQ11_2 0x00400000U /*!<Bit 2 */
+#define ADC_SQR2_SQ11_3 0x00800000U /*!<Bit 3 */
+#define ADC_SQR2_SQ11_4 0x01000000U /*!<Bit 4 */
+#define ADC_SQR2_SQ12 0x3E000000U /*!<SQ12[4:0] bits (12th conversion in regular sequence) */
+#define ADC_SQR2_SQ12_0 0x02000000U /*!<Bit 0 */
+#define ADC_SQR2_SQ12_1 0x04000000U /*!<Bit 1 */
+#define ADC_SQR2_SQ12_2 0x08000000U /*!<Bit 2 */
+#define ADC_SQR2_SQ12_3 0x10000000U /*!<Bit 3 */
+#define ADC_SQR2_SQ12_4 0x20000000U /*!<Bit 4 */
+
+/******************* Bit definition for ADC_SQR3 register *******************/
+#define ADC_SQR3_SQ1 0x0000001FU /*!<SQ1[4:0] bits (1st conversion in regular sequence) */
+#define ADC_SQR3_SQ1_0 0x00000001U /*!<Bit 0 */
+#define ADC_SQR3_SQ1_1 0x00000002U /*!<Bit 1 */
+#define ADC_SQR3_SQ1_2 0x00000004U /*!<Bit 2 */
+#define ADC_SQR3_SQ1_3 0x00000008U /*!<Bit 3 */
+#define ADC_SQR3_SQ1_4 0x00000010U /*!<Bit 4 */
+#define ADC_SQR3_SQ2 0x000003E0U /*!<SQ2[4:0] bits (2nd conversion in regular sequence) */
+#define ADC_SQR3_SQ2_0 0x00000020U /*!<Bit 0 */
+#define ADC_SQR3_SQ2_1 0x00000040U /*!<Bit 1 */
+#define ADC_SQR3_SQ2_2 0x00000080U /*!<Bit 2 */
+#define ADC_SQR3_SQ2_3 0x00000100U /*!<Bit 3 */
+#define ADC_SQR3_SQ2_4 0x00000200U /*!<Bit 4 */
+#define ADC_SQR3_SQ3 0x00007C00U /*!<SQ3[4:0] bits (3rd conversion in regular sequence) */
+#define ADC_SQR3_SQ3_0 0x00000400U /*!<Bit 0 */
+#define ADC_SQR3_SQ3_1 0x00000800U /*!<Bit 1 */
+#define ADC_SQR3_SQ3_2 0x00001000U /*!<Bit 2 */
+#define ADC_SQR3_SQ3_3 0x00002000U /*!<Bit 3 */
+#define ADC_SQR3_SQ3_4 0x00004000U /*!<Bit 4 */
+#define ADC_SQR3_SQ4 0x000F8000U /*!<SQ4[4:0] bits (4th conversion in regular sequence) */
+#define ADC_SQR3_SQ4_0 0x00008000U /*!<Bit 0 */
+#define ADC_SQR3_SQ4_1 0x00010000U /*!<Bit 1 */
+#define ADC_SQR3_SQ4_2 0x00020000U /*!<Bit 2 */
+#define ADC_SQR3_SQ4_3 0x00040000U /*!<Bit 3 */
+#define ADC_SQR3_SQ4_4 0x00080000U /*!<Bit 4 */
+#define ADC_SQR3_SQ5 0x01F00000U /*!<SQ5[4:0] bits (5th conversion in regular sequence) */
+#define ADC_SQR3_SQ5_0 0x00100000U /*!<Bit 0 */
+#define ADC_SQR3_SQ5_1 0x00200000U /*!<Bit 1 */
+#define ADC_SQR3_SQ5_2 0x00400000U /*!<Bit 2 */
+#define ADC_SQR3_SQ5_3 0x00800000U /*!<Bit 3 */
+#define ADC_SQR3_SQ5_4 0x01000000U /*!<Bit 4 */
+#define ADC_SQR3_SQ6 0x3E000000U /*!<SQ6[4:0] bits (6th conversion in regular sequence) */
+#define ADC_SQR3_SQ6_0 0x02000000U /*!<Bit 0 */
+#define ADC_SQR3_SQ6_1 0x04000000U /*!<Bit 1 */
+#define ADC_SQR3_SQ6_2 0x08000000U /*!<Bit 2 */
+#define ADC_SQR3_SQ6_3 0x10000000U /*!<Bit 3 */
+#define ADC_SQR3_SQ6_4 0x20000000U /*!<Bit 4 */
+
+/******************* Bit definition for ADC_JSQR register *******************/
+#define ADC_JSQR_JSQ1 0x0000001FU /*!<JSQ1[4:0] bits (1st conversion in injected sequence) */
+#define ADC_JSQR_JSQ1_0 0x00000001U /*!<Bit 0 */
+#define ADC_JSQR_JSQ1_1 0x00000002U /*!<Bit 1 */
+#define ADC_JSQR_JSQ1_2 0x00000004U /*!<Bit 2 */
+#define ADC_JSQR_JSQ1_3 0x00000008U /*!<Bit 3 */
+#define ADC_JSQR_JSQ1_4 0x00000010U /*!<Bit 4 */
+#define ADC_JSQR_JSQ2 0x000003E0U /*!<JSQ2[4:0] bits (2nd conversion in injected sequence) */
+#define ADC_JSQR_JSQ2_0 0x00000020U /*!<Bit 0 */
+#define ADC_JSQR_JSQ2_1 0x00000040U /*!<Bit 1 */
+#define ADC_JSQR_JSQ2_2 0x00000080U /*!<Bit 2 */
+#define ADC_JSQR_JSQ2_3 0x00000100U /*!<Bit 3 */
+#define ADC_JSQR_JSQ2_4 0x00000200U /*!<Bit 4 */
+#define ADC_JSQR_JSQ3 0x00007C00U /*!<JSQ3[4:0] bits (3rd conversion in injected sequence) */
+#define ADC_JSQR_JSQ3_0 0x00000400U /*!<Bit 0 */
+#define ADC_JSQR_JSQ3_1 0x00000800U /*!<Bit 1 */
+#define ADC_JSQR_JSQ3_2 0x00001000U /*!<Bit 2 */
+#define ADC_JSQR_JSQ3_3 0x00002000U /*!<Bit 3 */
+#define ADC_JSQR_JSQ3_4 0x00004000U /*!<Bit 4 */
+#define ADC_JSQR_JSQ4 0x000F8000U /*!<JSQ4[4:0] bits (4th conversion in injected sequence) */
+#define ADC_JSQR_JSQ4_0 0x00008000U /*!<Bit 0 */
+#define ADC_JSQR_JSQ4_1 0x00010000U /*!<Bit 1 */
+#define ADC_JSQR_JSQ4_2 0x00020000U /*!<Bit 2 */
+#define ADC_JSQR_JSQ4_3 0x00040000U /*!<Bit 3 */
+#define ADC_JSQR_JSQ4_4 0x00080000U /*!<Bit 4 */
+#define ADC_JSQR_JL 0x00300000U /*!<JL[1:0] bits (Injected Sequence length) */
+#define ADC_JSQR_JL_0 0x00100000U /*!<Bit 0 */
+#define ADC_JSQR_JL_1 0x00200000U /*!<Bit 1 */
+
+/******************* Bit definition for ADC_JDR1 register *******************/
+#define ADC_JDR1_JDATA 0xFFFFU /*!<Injected data */
+
+/******************* Bit definition for ADC_JDR2 register *******************/
+#define ADC_JDR2_JDATA 0xFFFFU /*!<Injected data */
+
+/******************* Bit definition for ADC_JDR3 register *******************/
+#define ADC_JDR3_JDATA 0xFFFFU /*!<Injected data */
+
+/******************* Bit definition for ADC_JDR4 register *******************/
+#define ADC_JDR4_JDATA 0xFFFFU /*!<Injected data */
+
+/******************** Bit definition for ADC_DR register ********************/
+#define ADC_DR_DATA 0x0000FFFFU /*!<Regular data */
+#define ADC_DR_ADC2DATA 0xFFFF0000U /*!<ADC2 data */
+
+/******************* Bit definition for ADC_CSR register ********************/
+#define ADC_CSR_AWD1 0x00000001U /*!<ADC1 Analog watchdog flag */
+#define ADC_CSR_EOC1 0x00000002U /*!<ADC1 End of conversion */
+#define ADC_CSR_JEOC1 0x00000004U /*!<ADC1 Injected channel end of conversion */
+#define ADC_CSR_JSTRT1 0x00000008U /*!<ADC1 Injected channel Start flag */
+#define ADC_CSR_STRT1 0x00000010U /*!<ADC1 Regular channel Start flag */
+#define ADC_CSR_DOVR1 0x00000020U /*!<ADC1 DMA overrun flag */
+#define ADC_CSR_AWD2 0x00000100U /*!<ADC2 Analog watchdog flag */
+#define ADC_CSR_EOC2 0x00000200U /*!<ADC2 End of conversion */
+#define ADC_CSR_JEOC2 0x00000400U /*!<ADC2 Injected channel end of conversion */
+#define ADC_CSR_JSTRT2 0x00000800U /*!<ADC2 Injected channel Start flag */
+#define ADC_CSR_STRT2 0x00001000U /*!<ADC2 Regular channel Start flag */
+#define ADC_CSR_DOVR2 0x00002000U /*!<ADC2 DMA overrun flag */
+
+/******************* Bit definition for ADC_CCR register ********************/
+#define ADC_CCR_MULTI 0x0000001FU /*!<MULTI[4:0] bits (Multi-ADC mode selection) */
+#define ADC_CCR_MULTI_0 0x00000001U /*!<Bit 0 */
+#define ADC_CCR_MULTI_1 0x00000002U /*!<Bit 1 */
+#define ADC_CCR_MULTI_2 0x00000004U /*!<Bit 2 */
+#define ADC_CCR_MULTI_3 0x00000008U /*!<Bit 3 */
+#define ADC_CCR_MULTI_4 0x00000010U /*!<Bit 4 */
+#define ADC_CCR_DELAY 0x00000F00U /*!<DELAY[3:0] bits (Delay between 2 sampling phases) */
+#define ADC_CCR_DELAY_0 0x00000100U /*!<Bit 0 */
+#define ADC_CCR_DELAY_1 0x00000200U /*!<Bit 1 */
+#define ADC_CCR_DELAY_2 0x00000400U /*!<Bit 2 */
+#define ADC_CCR_DELAY_3 0x00000800U /*!<Bit 3 */
+#define ADC_CCR_DDS 0x00002000U /*!<DMA disable selection (Multi-ADC mode) */
+#define ADC_CCR_DMA 0x0000C000U /*!<DMA[1:0] bits (Direct Memory Access mode for multimode) */
+#define ADC_CCR_DMA_0 0x00004000U /*!<Bit 0 */
+#define ADC_CCR_DMA_1 0x00008000U /*!<Bit 1 */
+#define ADC_CCR_ADCPRE 0x00030000U /*!<ADCPRE[1:0] bits (ADC prescaler) */
+#define ADC_CCR_ADCPRE_0 0x00010000U /*!<Bit 0 */
+#define ADC_CCR_ADCPRE_1 0x00020000U /*!<Bit 1 */
+#define ADC_CCR_VBATE 0x00400000U /*!<VBAT Enable */
+#define ADC_CCR_TSVREFE 0x00800000U /*!<Temperature Sensor and VREFINT Enable */
+
+/******************* Bit definition for ADC_CDR register ********************/
+#define ADC_CDR_DATA1 0x0000FFFFU /*!<1st data of a pair of regular conversions */
+#define ADC_CDR_DATA2 0xFFFF0000U /*!<2nd data of a pair of regular conversions */
+
+/******************************************************************************/
+/* */
+/* Controller Area Network */
+/* */
+/******************************************************************************/
+/*!<CAN control and status registers */
+/******************* Bit definition for CAN_MCR register ********************/
+#define CAN_MCR_INRQ 0x00000001U /*!<Initialization Request */
+#define CAN_MCR_SLEEP 0x00000002U /*!<Sleep Mode Request */
+#define CAN_MCR_TXFP 0x00000004U /*!<Transmit FIFO Priority */
+#define CAN_MCR_RFLM 0x00000008U /*!<Receive FIFO Locked Mode */
+#define CAN_MCR_NART 0x00000010U /*!<No Automatic Retransmission */
+#define CAN_MCR_AWUM 0x00000020U /*!<Automatic Wakeup Mode */
+#define CAN_MCR_ABOM 0x00000040U /*!<Automatic Bus-Off Management */
+#define CAN_MCR_TTCM 0x00000080U /*!<Time Triggered Communication Mode */
+#define CAN_MCR_RESET 0x00008000U /*!<bxCAN software master reset */
+#define CAN_MCR_DBF 0x00010000U /*!<bxCAN Debug freeze */
+/******************* Bit definition for CAN_MSR register ********************/
+#define CAN_MSR_INAK 0x0001U /*!<Initialization Acknowledge */
+#define CAN_MSR_SLAK 0x0002U /*!<Sleep Acknowledge */
+#define CAN_MSR_ERRI 0x0004U /*!<Error Interrupt */
+#define CAN_MSR_WKUI 0x0008U /*!<Wakeup Interrupt */
+#define CAN_MSR_SLAKI 0x0010U /*!<Sleep Acknowledge Interrupt */
+#define CAN_MSR_TXM 0x0100U /*!<Transmit Mode */
+#define CAN_MSR_RXM 0x0200U /*!<Receive Mode */
+#define CAN_MSR_SAMP 0x0400U /*!<Last Sample Point */
+#define CAN_MSR_RX 0x0800U /*!<CAN Rx Signal */
+
+/******************* Bit definition for CAN_TSR register ********************/
+#define CAN_TSR_RQCP0 0x00000001U /*!<Request Completed Mailbox0 */
+#define CAN_TSR_TXOK0 0x00000002U /*!<Transmission OK of Mailbox0 */
+#define CAN_TSR_ALST0 0x00000004U /*!<Arbitration Lost for Mailbox0 */
+#define CAN_TSR_TERR0 0x00000008U /*!<Transmission Error of Mailbox0 */
+#define CAN_TSR_ABRQ0 0x00000080U /*!<Abort Request for Mailbox0 */
+#define CAN_TSR_RQCP1 0x00000100U /*!<Request Completed Mailbox1 */
+#define CAN_TSR_TXOK1 0x00000200U /*!<Transmission OK of Mailbox1 */
+#define CAN_TSR_ALST1 0x00000400U /*!<Arbitration Lost for Mailbox1 */
+#define CAN_TSR_TERR1 0x00000800U /*!<Transmission Error of Mailbox1 */
+#define CAN_TSR_ABRQ1 0x00008000U /*!<Abort Request for Mailbox 1 */
+#define CAN_TSR_RQCP2 0x00010000U /*!<Request Completed Mailbox2 */
+#define CAN_TSR_TXOK2 0x00020000U /*!<Transmission OK of Mailbox 2 */
+#define CAN_TSR_ALST2 0x00040000U /*!<Arbitration Lost for mailbox 2 */
+#define CAN_TSR_TERR2 0x00080000U /*!<Transmission Error of Mailbox 2 */
+#define CAN_TSR_ABRQ2 0x00800000U /*!<Abort Request for Mailbox 2 */
+#define CAN_TSR_CODE 0x03000000U /*!<Mailbox Code */
+
+#define CAN_TSR_TME 0x1C000000U /*!<TME[2:0] bits */
+#define CAN_TSR_TME0 0x04000000U /*!<Transmit Mailbox 0 Empty */
+#define CAN_TSR_TME1 0x08000000U /*!<Transmit Mailbox 1 Empty */
+#define CAN_TSR_TME2 0x10000000U /*!<Transmit Mailbox 2 Empty */
+
+#define CAN_TSR_LOW 0xE0000000U /*!<LOW[2:0] bits */
+#define CAN_TSR_LOW0 0x20000000U /*!<Lowest Priority Flag for Mailbox 0 */
+#define CAN_TSR_LOW1 0x40000000U /*!<Lowest Priority Flag for Mailbox 1 */
+#define CAN_TSR_LOW2 0x80000000U /*!<Lowest Priority Flag for Mailbox 2 */
+
+/******************* Bit definition for CAN_RF0R register *******************/
+#define CAN_RF0R_FMP0 0x03U /*!<FIFO 0 Message Pending */
+#define CAN_RF0R_FULL0 0x08U /*!<FIFO 0 Full */
+#define CAN_RF0R_FOVR0 0x10U /*!<FIFO 0 Overrun */
+#define CAN_RF0R_RFOM0 0x20U /*!<Release FIFO 0 Output Mailbox */
+
+/******************* Bit definition for CAN_RF1R register *******************/
+#define CAN_RF1R_FMP1 0x03U /*!<FIFO 1 Message Pending */
+#define CAN_RF1R_FULL1 0x08U /*!<FIFO 1 Full */
+#define CAN_RF1R_FOVR1 0x10U /*!<FIFO 1 Overrun */
+#define CAN_RF1R_RFOM1 0x20U /*!<Release FIFO 1 Output Mailbox */
+
+/******************** Bit definition for CAN_IER register *******************/
+#define CAN_IER_TMEIE 0x00000001U /*!<Transmit Mailbox Empty Interrupt Enable */
+#define CAN_IER_FMPIE0 0x00000002U /*!<FIFO Message Pending Interrupt Enable */
+#define CAN_IER_FFIE0 0x00000004U /*!<FIFO Full Interrupt Enable */
+#define CAN_IER_FOVIE0 0x00000008U /*!<FIFO Overrun Interrupt Enable */
+#define CAN_IER_FMPIE1 0x00000010U /*!<FIFO Message Pending Interrupt Enable */
+#define CAN_IER_FFIE1 0x00000020U /*!<FIFO Full Interrupt Enable */
+#define CAN_IER_FOVIE1 0x00000040U /*!<FIFO Overrun Interrupt Enable */
+#define CAN_IER_EWGIE 0x00000100U /*!<Error Warning Interrupt Enable */
+#define CAN_IER_EPVIE 0x00000200U /*!<Error Passive Interrupt Enable */
+#define CAN_IER_BOFIE 0x00000400U /*!<Bus-Off Interrupt Enable */
+#define CAN_IER_LECIE 0x00000800U /*!<Last Error Code Interrupt Enable */
+#define CAN_IER_ERRIE 0x00008000U /*!<Error Interrupt Enable */
+#define CAN_IER_WKUIE 0x00010000U /*!<Wakeup Interrupt Enable */
+#define CAN_IER_SLKIE 0x00020000U /*!<Sleep Interrupt Enable */
+#define CAN_IER_EWGIE 0x00000100U /*!<Error warning interrupt enable */
+#define CAN_IER_EPVIE 0x00000200U /*!<Error passive interrupt enable */
+#define CAN_IER_BOFIE 0x00000400U /*!<Bus-off interrupt enable */
+#define CAN_IER_LECIE 0x00000800U /*!<Last error code interrupt enable */
+#define CAN_IER_ERRIE 0x00008000U /*!<Error interrupt enable */
+
+
+/******************** Bit definition for CAN_ESR register *******************/
+#define CAN_ESR_EWGF 0x00000001U /*!<Error Warning Flag */
+#define CAN_ESR_EPVF 0x00000002U /*!<Error Passive Flag */
+#define CAN_ESR_BOFF 0x00000004U /*!<Bus-Off Flag */
+
+#define CAN_ESR_LEC 0x00000070U /*!<LEC[2:0] bits (Last Error Code) */
+#define CAN_ESR_LEC_0 0x00000010U /*!<Bit 0 */
+#define CAN_ESR_LEC_1 0x00000020U /*!<Bit 1 */
+#define CAN_ESR_LEC_2 0x00000040U /*!<Bit 2 */
+
+#define CAN_ESR_TEC 0x00FF0000U /*!<Least significant byte of the 9-bit Transmit Error Counter */
+#define CAN_ESR_REC 0xFF000000U /*!<Receive Error Counter */
+
+/******************* Bit definition for CAN_BTR register ********************/
+#define CAN_BTR_BRP 0x000003FFU /*!<Baud Rate Prescaler */
+#define CAN_BTR_TS1 0x000F0000U /*!<Time Segment 1 */
+#define CAN_BTR_TS1_0 0x00010000U /*!<Bit 0 */
+#define CAN_BTR_TS1_1 0x00020000U /*!<Bit 1 */
+#define CAN_BTR_TS1_2 0x00040000U /*!<Bit 2 */
+#define CAN_BTR_TS1_3 0x00080000U /*!<Bit 3 */
+#define CAN_BTR_TS2 0x00700000U /*!<Time Segment 2 */
+#define CAN_BTR_TS2_0 0x00100000U /*!<Bit 0 */
+#define CAN_BTR_TS2_1 0x00200000U /*!<Bit 1 */
+#define CAN_BTR_TS2_2 0x00400000U /*!<Bit 2 */
+#define CAN_BTR_SJW 0x03000000U /*!<Resynchronization Jump Width */
+#define CAN_BTR_SJW_0 0x01000000U /*!<Bit 0 */
+#define CAN_BTR_SJW_1 0x02000000U /*!<Bit 1 */
+#define CAN_BTR_LBKM 0x40000000U /*!<Loop Back Mode (Debug) */
+#define CAN_BTR_SILM 0x80000000U /*!<Silent Mode */
+
+
+/*!<Mailbox registers */
+/****************** Bit definition for CAN_TI0R register ********************/
+#define CAN_TI0R_TXRQ 0x00000001U /*!<Transmit Mailbox Request */
+#define CAN_TI0R_RTR 0x00000002U /*!<Remote Transmission Request */
+#define CAN_TI0R_IDE 0x00000004U /*!<Identifier Extension */
+#define CAN_TI0R_EXID 0x001FFFF8U /*!<Extended Identifier */
+#define CAN_TI0R_STID 0xFFE00000U /*!<Standard Identifier or Extended Identifier */
+
+/****************** Bit definition for CAN_TDT0R register *******************/
+#define CAN_TDT0R_DLC 0x0000000FU /*!<Data Length Code */
+#define CAN_TDT0R_TGT 0x00000100U /*!<Transmit Global Time */
+#define CAN_TDT0R_TIME 0xFFFF0000U /*!<Message Time Stamp */
+
+/****************** Bit definition for CAN_TDL0R register *******************/
+#define CAN_TDL0R_DATA0 0x000000FFU /*!<Data byte 0 */
+#define CAN_TDL0R_DATA1 0x0000FF00U /*!<Data byte 1 */
+#define CAN_TDL0R_DATA2 0x00FF0000U /*!<Data byte 2 */
+#define CAN_TDL0R_DATA3 0xFF000000U /*!<Data byte 3 */
+
+/****************** Bit definition for CAN_TDH0R register *******************/
+#define CAN_TDH0R_DATA4 0x000000FFU /*!<Data byte 4 */
+#define CAN_TDH0R_DATA5 0x0000FF00U /*!<Data byte 5 */
+#define CAN_TDH0R_DATA6 0x00FF0000U /*!<Data byte 6 */
+#define CAN_TDH0R_DATA7 0xFF000000U /*!<Data byte 7 */
+
+/******************* Bit definition for CAN_TI1R register *******************/
+#define CAN_TI1R_TXRQ 0x00000001U /*!<Transmit Mailbox Request */
+#define CAN_TI1R_RTR 0x00000002U /*!<Remote Transmission Request */
+#define CAN_TI1R_IDE 0x00000004U /*!<Identifier Extension */
+#define CAN_TI1R_EXID 0x001FFFF8U /*!<Extended Identifier */
+#define CAN_TI1R_STID 0xFFE00000U /*!<Standard Identifier or Extended Identifier */
+
+/******************* Bit definition for CAN_TDT1R register ******************/
+#define CAN_TDT1R_DLC 0x0000000FU /*!<Data Length Code */
+#define CAN_TDT1R_TGT 0x00000100U /*!<Transmit Global Time */
+#define CAN_TDT1R_TIME 0xFFFF0000U /*!<Message Time Stamp */
+
+/******************* Bit definition for CAN_TDL1R register ******************/
+#define CAN_TDL1R_DATA0 0x000000FFU /*!<Data byte 0 */
+#define CAN_TDL1R_DATA1 0x0000FF00U /*!<Data byte 1 */
+#define CAN_TDL1R_DATA2 0x00FF0000U /*!<Data byte 2 */
+#define CAN_TDL1R_DATA3 0xFF000000U /*!<Data byte 3 */
+
+/******************* Bit definition for CAN_TDH1R register ******************/
+#define CAN_TDH1R_DATA4 0x000000FFU /*!<Data byte 4 */
+#define CAN_TDH1R_DATA5 0x0000FF00U /*!<Data byte 5 */
+#define CAN_TDH1R_DATA6 0x00FF0000U /*!<Data byte 6 */
+#define CAN_TDH1R_DATA7 0xFF000000U /*!<Data byte 7 */
+
+/******************* Bit definition for CAN_TI2R register *******************/
+#define CAN_TI2R_TXRQ 0x00000001U /*!<Transmit Mailbox Request */
+#define CAN_TI2R_RTR 0x00000002U /*!<Remote Transmission Request */
+#define CAN_TI2R_IDE 0x00000004U /*!<Identifier Extension */
+#define CAN_TI2R_EXID 0x001FFFF8U /*!<Extended identifier */
+#define CAN_TI2R_STID 0xFFE00000U /*!<Standard Identifier or Extended Identifier */
+
+/******************* Bit definition for CAN_TDT2R register ******************/
+#define CAN_TDT2R_DLC 0x0000000FU /*!<Data Length Code */
+#define CAN_TDT2R_TGT 0x00000100U /*!<Transmit Global Time */
+#define CAN_TDT2R_TIME 0xFFFF0000U /*!<Message Time Stamp */
+
+/******************* Bit definition for CAN_TDL2R register ******************/
+#define CAN_TDL2R_DATA0 0x000000FFU /*!<Data byte 0 */
+#define CAN_TDL2R_DATA1 0x0000FF00U /*!<Data byte 1 */
+#define CAN_TDL2R_DATA2 0x00FF0000U /*!<Data byte 2 */
+#define CAN_TDL2R_DATA3 0xFF000000U /*!<Data byte 3 */
+
+/******************* Bit definition for CAN_TDH2R register ******************/
+#define CAN_TDH2R_DATA4 0x000000FFU /*!<Data byte 4 */
+#define CAN_TDH2R_DATA5 0x0000FF00U /*!<Data byte 5 */
+#define CAN_TDH2R_DATA6 0x00FF0000U /*!<Data byte 6 */
+#define CAN_TDH2R_DATA7 0xFF000000U /*!<Data byte 7 */
+
+/******************* Bit definition for CAN_RI0R register *******************/
+#define CAN_RI0R_RTR 0x00000002U /*!<Remote Transmission Request */
+#define CAN_RI0R_IDE 0x00000004U /*!<Identifier Extension */
+#define CAN_RI0R_EXID 0x001FFFF8U /*!<Extended Identifier */
+#define CAN_RI0R_STID 0xFFE00000U /*!<Standard Identifier or Extended Identifier */
+
+/******************* Bit definition for CAN_RDT0R register ******************/
+#define CAN_RDT0R_DLC 0x0000000FU /*!<Data Length Code */
+#define CAN_RDT0R_FMI 0x0000FF00U /*!<Filter Match Index */
+#define CAN_RDT0R_TIME 0xFFFF0000U /*!<Message Time Stamp */
+
+/******************* Bit definition for CAN_RDL0R register ******************/
+#define CAN_RDL0R_DATA0 0x000000FFU /*!<Data byte 0 */
+#define CAN_RDL0R_DATA1 0x0000FF00U /*!<Data byte 1 */
+#define CAN_RDL0R_DATA2 0x00FF0000U /*!<Data byte 2 */
+#define CAN_RDL0R_DATA3 0xFF000000U /*!<Data byte 3 */
+
+/******************* Bit definition for CAN_RDH0R register ******************/
+#define CAN_RDH0R_DATA4 0x000000FFU /*!<Data byte 4 */
+#define CAN_RDH0R_DATA5 0x0000FF00U /*!<Data byte 5 */
+#define CAN_RDH0R_DATA6 0x00FF0000U /*!<Data byte 6 */
+#define CAN_RDH0R_DATA7 0xFF000000U /*!<Data byte 7 */
+
+/******************* Bit definition for CAN_RI1R register *******************/
+#define CAN_RI1R_RTR 0x00000002U /*!<Remote Transmission Request */
+#define CAN_RI1R_IDE 0x00000004U /*!<Identifier Extension */
+#define CAN_RI1R_EXID 0x001FFFF8U /*!<Extended identifier */
+#define CAN_RI1R_STID 0xFFE00000U /*!<Standard Identifier or Extended Identifier */
+
+/******************* Bit definition for CAN_RDT1R register ******************/
+#define CAN_RDT1R_DLC 0x0000000FU /*!<Data Length Code */
+#define CAN_RDT1R_FMI 0x0000FF00U /*!<Filter Match Index */
+#define CAN_RDT1R_TIME 0xFFFF0000U /*!<Message Time Stamp */
+
+/******************* Bit definition for CAN_RDL1R register ******************/
+#define CAN_RDL1R_DATA0 0x000000FFU /*!<Data byte 0 */
+#define CAN_RDL1R_DATA1 0x0000FF00U /*!<Data byte 1 */
+#define CAN_RDL1R_DATA2 0x00FF0000U /*!<Data byte 2 */
+#define CAN_RDL1R_DATA3 0xFF000000U /*!<Data byte 3 */
+
+/******************* Bit definition for CAN_RDH1R register ******************/
+#define CAN_RDH1R_DATA4 0x000000FFU /*!<Data byte 4 */
+#define CAN_RDH1R_DATA5 0x0000FF00U /*!<Data byte 5 */
+#define CAN_RDH1R_DATA6 0x00FF0000U /*!<Data byte 6 */
+#define CAN_RDH1R_DATA7 0xFF000000U /*!<Data byte 7 */
+
+/*!<CAN filter registers */
+/******************* Bit definition for CAN_FMR register ********************/
+#define CAN_FMR_FINIT 0x01U /*!<Filter Init Mode */
+#define CAN_FMR_CAN2SB 0x00003F00U /*!<CAN2 start bank */
+
+/******************* Bit definition for CAN_FM1R register *******************/
+#define CAN_FM1R_FBM 0x0FFFFFFFU /*!<Filter Mode */
+#define CAN_FM1R_FBM0 0x00000001U /*!<Filter Init Mode bit 0 */
+#define CAN_FM1R_FBM1 0x00000002U /*!<Filter Init Mode bit 1 */
+#define CAN_FM1R_FBM2 0x00000004U /*!<Filter Init Mode bit 2 */
+#define CAN_FM1R_FBM3 0x00000008U /*!<Filter Init Mode bit 3 */
+#define CAN_FM1R_FBM4 0x00000010U /*!<Filter Init Mode bit 4 */
+#define CAN_FM1R_FBM5 0x00000020U /*!<Filter Init Mode bit 5 */
+#define CAN_FM1R_FBM6 0x00000040U /*!<Filter Init Mode bit 6 */
+#define CAN_FM1R_FBM7 0x00000080U /*!<Filter Init Mode bit 7 */
+#define CAN_FM1R_FBM8 0x00000100U /*!<Filter Init Mode bit 8 */
+#define CAN_FM1R_FBM9 0x00000200U /*!<Filter Init Mode bit 9 */
+#define CAN_FM1R_FBM10 0x00000400U /*!<Filter Init Mode bit 10 */
+#define CAN_FM1R_FBM11 0x00000800U /*!<Filter Init Mode bit 11 */
+#define CAN_FM1R_FBM12 0x00001000U /*!<Filter Init Mode bit 12 */
+#define CAN_FM1R_FBM13 0x00002000U /*!<Filter Init Mode bit 13 */
+#define CAN_FM1R_FBM14 0x00004000U /*!<Filter Init Mode bit 14 */
+#define CAN_FM1R_FBM15 0x00008000U /*!<Filter Init Mode bit 15 */
+#define CAN_FM1R_FBM16 0x00010000U /*!<Filter Init Mode bit 16 */
+#define CAN_FM1R_FBM17 0x00020000U /*!<Filter Init Mode bit 17 */
+#define CAN_FM1R_FBM18 0x00040000U /*!<Filter Init Mode bit 18 */
+#define CAN_FM1R_FBM19 0x00080000U /*!<Filter Init Mode bit 19 */
+#define CAN_FM1R_FBM20 0x00100000U /*!<Filter Init Mode bit 20 */
+#define CAN_FM1R_FBM21 0x00200000U /*!<Filter Init Mode bit 21 */
+#define CAN_FM1R_FBM22 0x00400000U /*!<Filter Init Mode bit 22 */
+#define CAN_FM1R_FBM23 0x00800000U /*!<Filter Init Mode bit 23 */
+#define CAN_FM1R_FBM24 0x01000000U /*!<Filter Init Mode bit 24 */
+#define CAN_FM1R_FBM25 0x02000000U /*!<Filter Init Mode bit 25 */
+#define CAN_FM1R_FBM26 0x04000000U /*!<Filter Init Mode bit 26 */
+#define CAN_FM1R_FBM27 0x08000000U /*!<Filter Init Mode bit 27 */
+
+/******************* Bit definition for CAN_FS1R register *******************/
+#define CAN_FS1R_FSC 0x0FFFFFFFU /*!<Filter Scale Configuration */
+#define CAN_FS1R_FSC0 0x00000001U /*!<Filter Scale Configuration bit 0 */
+#define CAN_FS1R_FSC1 0x00000002U /*!<Filter Scale Configuration bit 1 */
+#define CAN_FS1R_FSC2 0x00000004U /*!<Filter Scale Configuration bit 2 */
+#define CAN_FS1R_FSC3 0x00000008U /*!<Filter Scale Configuration bit 3 */
+#define CAN_FS1R_FSC4 0x00000010U /*!<Filter Scale Configuration bit 4 */
+#define CAN_FS1R_FSC5 0x00000020U /*!<Filter Scale Configuration bit 5 */
+#define CAN_FS1R_FSC6 0x00000040U /*!<Filter Scale Configuration bit 6 */
+#define CAN_FS1R_FSC7 0x00000080U /*!<Filter Scale Configuration bit 7 */
+#define CAN_FS1R_FSC8 0x00000100U /*!<Filter Scale Configuration bit 8 */
+#define CAN_FS1R_FSC9 0x00000200U /*!<Filter Scale Configuration bit 9 */
+#define CAN_FS1R_FSC10 0x00000400U /*!<Filter Scale Configuration bit 10 */
+#define CAN_FS1R_FSC11 0x00000800U /*!<Filter Scale Configuration bit 11 */
+#define CAN_FS1R_FSC12 0x00001000U /*!<Filter Scale Configuration bit 12 */
+#define CAN_FS1R_FSC13 0x00002000U /*!<Filter Scale Configuration bit 13 */
+#define CAN_FS1R_FSC14 0x00004000U /*!<Filter Scale Configuration bit 14 */
+#define CAN_FS1R_FSC15 0x00008000U /*!<Filter Scale Configuration bit 15 */
+#define CAN_FS1R_FSC16 0x00010000U /*!<Filter Scale Configuration bit 16 */
+#define CAN_FS1R_FSC17 0x00020000U /*!<Filter Scale Configuration bit 17 */
+#define CAN_FS1R_FSC18 0x00040000U /*!<Filter Scale Configuration bit 18 */
+#define CAN_FS1R_FSC19 0x00080000U /*!<Filter Scale Configuration bit 19 */
+#define CAN_FS1R_FSC20 0x00100000U /*!<Filter Scale Configuration bit 20 */
+#define CAN_FS1R_FSC21 0x00200000U /*!<Filter Scale Configuration bit 21 */
+#define CAN_FS1R_FSC22 0x00400000U /*!<Filter Scale Configuration bit 22 */
+#define CAN_FS1R_FSC23 0x00800000U /*!<Filter Scale Configuration bit 23 */
+#define CAN_FS1R_FSC24 0x01000000U /*!<Filter Scale Configuration bit 24 */
+#define CAN_FS1R_FSC25 0x02000000U /*!<Filter Scale Configuration bit 25 */
+#define CAN_FS1R_FSC26 0x04000000U /*!<Filter Scale Configuration bit 26 */
+#define CAN_FS1R_FSC27 0x08000000U /*!<Filter Scale Configuration bit 27 */
+
+/****************** Bit definition for CAN_FFA1R register *******************/
+#define CAN_FFA1R_FFA 0x0FFFFFFFU /*!<Filter FIFO Assignment */
+#define CAN_FFA1R_FFA0 0x00000001U /*!<Filter FIFO Assignment bit 0 */
+#define CAN_FFA1R_FFA1 0x00000002U /*!<Filter FIFO Assignment bit 1 */
+#define CAN_FFA1R_FFA2 0x00000004U /*!<Filter FIFO Assignment bit 2 */
+#define CAN_FFA1R_FFA3 0x00000008U /*!<Filter FIFO Assignment bit 3 */
+#define CAN_FFA1R_FFA4 0x00000010U /*!<Filter FIFO Assignment bit 4 */
+#define CAN_FFA1R_FFA5 0x00000020U /*!<Filter FIFO Assignment bit 5 */
+#define CAN_FFA1R_FFA6 0x00000040U /*!<Filter FIFO Assignment bit 6 */
+#define CAN_FFA1R_FFA7 0x00000080U /*!<Filter FIFO Assignment bit 7 */
+#define CAN_FFA1R_FFA8 0x00000100U /*!<Filter FIFO Assignment bit 8 */
+#define CAN_FFA1R_FFA9 0x00000200U /*!<Filter FIFO Assignment bit 9 */
+#define CAN_FFA1R_FFA10 0x00000400U /*!<Filter FIFO Assignment bit 10 */
+#define CAN_FFA1R_FFA11 0x00000800U /*!<Filter FIFO Assignment bit 11 */
+#define CAN_FFA1R_FFA12 0x00001000U /*!<Filter FIFO Assignment bit 12 */
+#define CAN_FFA1R_FFA13 0x00002000U /*!<Filter FIFO Assignment bit 13 */
+#define CAN_FFA1R_FFA14 0x00004000U /*!<Filter FIFO Assignment bit 14 */
+#define CAN_FFA1R_FFA15 0x00008000U /*!<Filter FIFO Assignment bit 15 */
+#define CAN_FFA1R_FFA16 0x00010000U /*!<Filter FIFO Assignment bit 16 */
+#define CAN_FFA1R_FFA17 0x00020000U /*!<Filter FIFO Assignment bit 17 */
+#define CAN_FFA1R_FFA18 0x00040000U /*!<Filter FIFO Assignment bit 18 */
+#define CAN_FFA1R_FFA19 0x00080000U /*!<Filter FIFO Assignment bit 19 */
+#define CAN_FFA1R_FFA20 0x00100000U /*!<Filter FIFO Assignment bit 20 */
+#define CAN_FFA1R_FFA21 0x00200000U /*!<Filter FIFO Assignment bit 21 */
+#define CAN_FFA1R_FFA22 0x00400000U /*!<Filter FIFO Assignment bit 22 */
+#define CAN_FFA1R_FFA23 0x00800000U /*!<Filter FIFO Assignment bit 23 */
+#define CAN_FFA1R_FFA24 0x01000000U /*!<Filter FIFO Assignment bit 24 */
+#define CAN_FFA1R_FFA25 0x02000000U /*!<Filter FIFO Assignment bit 25 */
+#define CAN_FFA1R_FFA26 0x04000000U /*!<Filter FIFO Assignment bit 26 */
+#define CAN_FFA1R_FFA27 0x08000000U /*!<Filter FIFO Assignment bit 27 */
+
+/******************* Bit definition for CAN_FA1R register *******************/
+#define CAN_FA1R_FACT 0x0FFFFFFFU /*!<Filter Active */
+#define CAN_FA1R_FACT0 0x00000001U /*!<Filter Active bit 0 */
+#define CAN_FA1R_FACT1 0x00000002U /*!<Filter Active bit 1 */
+#define CAN_FA1R_FACT2 0x00000004U /*!<Filter Active bit 2 */
+#define CAN_FA1R_FACT3 0x00000008U /*!<Filter Active bit 3 */
+#define CAN_FA1R_FACT4 0x00000010U /*!<Filter Active bit 4 */
+#define CAN_FA1R_FACT5 0x00000020U /*!<Filter Active bit 5 */
+#define CAN_FA1R_FACT6 0x00000040U /*!<Filter Active bit 6 */
+#define CAN_FA1R_FACT7 0x00000080U /*!<Filter Active bit 7 */
+#define CAN_FA1R_FACT8 0x00000100U /*!<Filter Active bit 8 */
+#define CAN_FA1R_FACT9 0x00000200U /*!<Filter Active bit 9 */
+#define CAN_FA1R_FACT10 0x00000400U /*!<Filter Active bit 10 */
+#define CAN_FA1R_FACT11 0x00000800U /*!<Filter Active bit 11 */
+#define CAN_FA1R_FACT12 0x00001000U /*!<Filter Active bit 12 */
+#define CAN_FA1R_FACT13 0x00002000U /*!<Filter Active bit 13 */
+#define CAN_FA1R_FACT14 0x00004000U /*!<Filter Active bit 14 */
+#define CAN_FA1R_FACT15 0x00008000U /*!<Filter Active bit 15 */
+#define CAN_FA1R_FACT16 0x00010000U /*!<Filter Active bit 16 */
+#define CAN_FA1R_FACT17 0x00020000U /*!<Filter Active bit 17 */
+#define CAN_FA1R_FACT18 0x00040000U /*!<Filter Active bit 18 */
+#define CAN_FA1R_FACT19 0x00080000U /*!<Filter Active bit 19 */
+#define CAN_FA1R_FACT20 0x00100000U /*!<Filter Active bit 20 */
+#define CAN_FA1R_FACT21 0x00200000U /*!<Filter Active bit 21 */
+#define CAN_FA1R_FACT22 0x00400000U /*!<Filter Active bit 22 */
+#define CAN_FA1R_FACT23 0x00800000U /*!<Filter Active bit 23 */
+#define CAN_FA1R_FACT24 0x01000000U /*!<Filter Active bit 24 */
+#define CAN_FA1R_FACT25 0x02000000U /*!<Filter Active bit 25 */
+#define CAN_FA1R_FACT26 0x04000000U /*!<Filter Active bit 26 */
+#define CAN_FA1R_FACT27 0x08000000U /*!<Filter Active bit 27 */
+
+/******************* Bit definition for CAN_F0R1 register *******************/
+#define CAN_F0R1_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F0R1_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F0R1_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F0R1_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F0R1_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F0R1_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F0R1_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F0R1_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F0R1_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F0R1_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F0R1_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F0R1_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F0R1_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F0R1_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F0R1_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F0R1_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F0R1_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F0R1_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F0R1_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F0R1_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F0R1_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F0R1_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F0R1_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F0R1_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F0R1_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F0R1_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F0R1_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F0R1_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F0R1_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F0R1_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F0R1_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F0R1_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F1R1 register *******************/
+#define CAN_F1R1_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F1R1_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F1R1_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F1R1_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F1R1_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F1R1_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F1R1_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F1R1_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F1R1_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F1R1_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F1R1_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F1R1_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F1R1_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F1R1_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F1R1_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F1R1_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F1R1_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F1R1_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F1R1_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F1R1_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F1R1_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F1R1_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F1R1_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F1R1_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F1R1_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F1R1_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F1R1_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F1R1_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F1R1_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F1R1_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F1R1_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F1R1_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F2R1 register *******************/
+#define CAN_F2R1_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F2R1_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F2R1_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F2R1_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F2R1_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F2R1_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F2R1_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F2R1_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F2R1_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F2R1_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F2R1_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F2R1_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F2R1_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F2R1_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F2R1_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F2R1_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F2R1_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F2R1_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F2R1_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F2R1_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F2R1_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F2R1_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F2R1_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F2R1_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F2R1_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F2R1_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F2R1_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F2R1_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F2R1_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F2R1_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F2R1_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F2R1_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F3R1 register *******************/
+#define CAN_F3R1_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F3R1_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F3R1_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F3R1_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F3R1_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F3R1_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F3R1_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F3R1_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F3R1_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F3R1_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F3R1_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F3R1_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F3R1_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F3R1_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F3R1_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F3R1_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F3R1_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F3R1_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F3R1_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F3R1_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F3R1_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F3R1_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F3R1_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F3R1_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F3R1_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F3R1_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F3R1_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F3R1_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F3R1_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F3R1_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F3R1_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F3R1_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F4R1 register *******************/
+#define CAN_F4R1_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F4R1_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F4R1_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F4R1_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F4R1_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F4R1_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F4R1_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F4R1_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F4R1_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F4R1_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F4R1_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F4R1_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F4R1_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F4R1_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F4R1_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F4R1_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F4R1_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F4R1_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F4R1_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F4R1_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F4R1_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F4R1_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F4R1_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F4R1_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F4R1_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F4R1_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F4R1_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F4R1_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F4R1_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F4R1_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F4R1_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F4R1_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F5R1 register *******************/
+#define CAN_F5R1_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F5R1_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F5R1_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F5R1_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F5R1_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F5R1_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F5R1_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F5R1_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F5R1_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F5R1_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F5R1_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F5R1_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F5R1_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F5R1_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F5R1_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F5R1_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F5R1_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F5R1_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F5R1_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F5R1_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F5R1_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F5R1_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F5R1_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F5R1_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F5R1_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F5R1_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F5R1_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F5R1_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F5R1_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F5R1_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F5R1_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F5R1_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F6R1 register *******************/
+#define CAN_F6R1_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F6R1_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F6R1_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F6R1_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F6R1_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F6R1_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F6R1_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F6R1_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F6R1_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F6R1_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F6R1_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F6R1_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F6R1_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F6R1_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F6R1_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F6R1_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F6R1_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F6R1_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F6R1_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F6R1_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F6R1_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F6R1_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F6R1_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F6R1_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F6R1_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F6R1_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F6R1_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F6R1_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F6R1_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F6R1_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F6R1_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F6R1_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F7R1 register *******************/
+#define CAN_F7R1_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F7R1_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F7R1_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F7R1_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F7R1_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F7R1_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F7R1_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F7R1_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F7R1_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F7R1_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F7R1_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F7R1_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F7R1_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F7R1_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F7R1_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F7R1_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F7R1_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F7R1_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F7R1_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F7R1_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F7R1_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F7R1_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F7R1_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F7R1_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F7R1_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F7R1_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F7R1_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F7R1_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F7R1_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F7R1_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F7R1_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F7R1_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F8R1 register *******************/
+#define CAN_F8R1_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F8R1_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F8R1_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F8R1_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F8R1_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F8R1_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F8R1_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F8R1_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F8R1_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F8R1_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F8R1_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F8R1_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F8R1_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F8R1_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F8R1_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F8R1_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F8R1_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F8R1_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F8R1_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F8R1_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F8R1_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F8R1_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F8R1_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F8R1_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F8R1_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F8R1_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F8R1_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F8R1_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F8R1_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F8R1_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F8R1_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F8R1_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F9R1 register *******************/
+#define CAN_F9R1_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F9R1_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F9R1_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F9R1_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F9R1_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F9R1_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F9R1_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F9R1_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F9R1_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F9R1_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F9R1_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F9R1_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F9R1_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F9R1_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F9R1_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F9R1_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F9R1_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F9R1_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F9R1_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F9R1_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F9R1_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F9R1_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F9R1_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F9R1_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F9R1_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F9R1_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F9R1_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F9R1_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F9R1_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F9R1_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F9R1_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F9R1_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F10R1 register ******************/
+#define CAN_F10R1_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F10R1_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F10R1_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F10R1_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F10R1_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F10R1_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F10R1_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F10R1_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F10R1_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F10R1_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F10R1_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F10R1_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F10R1_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F10R1_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F10R1_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F10R1_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F10R1_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F10R1_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F10R1_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F10R1_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F10R1_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F10R1_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F10R1_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F10R1_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F10R1_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F10R1_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F10R1_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F10R1_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F10R1_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F10R1_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F10R1_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F10R1_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F11R1 register ******************/
+#define CAN_F11R1_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F11R1_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F11R1_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F11R1_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F11R1_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F11R1_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F11R1_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F11R1_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F11R1_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F11R1_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F11R1_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F11R1_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F11R1_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F11R1_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F11R1_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F11R1_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F11R1_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F11R1_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F11R1_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F11R1_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F11R1_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F11R1_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F11R1_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F11R1_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F11R1_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F11R1_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F11R1_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F11R1_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F11R1_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F11R1_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F11R1_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F11R1_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F12R1 register ******************/
+#define CAN_F12R1_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F12R1_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F12R1_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F12R1_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F12R1_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F12R1_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F12R1_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F12R1_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F12R1_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F12R1_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F12R1_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F12R1_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F12R1_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F12R1_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F12R1_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F12R1_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F12R1_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F12R1_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F12R1_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F12R1_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F12R1_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F12R1_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F12R1_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F12R1_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F12R1_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F12R1_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F12R1_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F12R1_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F12R1_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F12R1_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F12R1_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F12R1_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F13R1 register ******************/
+#define CAN_F13R1_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F13R1_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F13R1_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F13R1_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F13R1_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F13R1_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F13R1_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F13R1_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F13R1_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F13R1_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F13R1_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F13R1_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F13R1_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F13R1_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F13R1_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F13R1_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F13R1_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F13R1_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F13R1_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F13R1_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F13R1_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F13R1_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F13R1_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F13R1_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F13R1_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F13R1_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F13R1_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F13R1_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F13R1_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F13R1_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F13R1_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F13R1_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F0R2 register *******************/
+#define CAN_F0R2_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F0R2_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F0R2_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F0R2_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F0R2_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F0R2_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F0R2_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F0R2_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F0R2_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F0R2_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F0R2_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F0R2_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F0R2_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F0R2_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F0R2_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F0R2_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F0R2_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F0R2_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F0R2_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F0R2_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F0R2_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F0R2_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F0R2_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F0R2_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F0R2_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F0R2_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F0R2_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F0R2_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F0R2_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F0R2_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F0R2_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F0R2_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F1R2 register *******************/
+#define CAN_F1R2_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F1R2_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F1R2_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F1R2_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F1R2_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F1R2_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F1R2_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F1R2_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F1R2_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F1R2_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F1R2_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F1R2_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F1R2_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F1R2_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F1R2_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F1R2_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F1R2_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F1R2_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F1R2_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F1R2_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F1R2_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F1R2_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F1R2_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F1R2_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F1R2_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F1R2_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F1R2_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F1R2_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F1R2_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F1R2_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F1R2_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F1R2_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F2R2 register *******************/
+#define CAN_F2R2_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F2R2_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F2R2_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F2R2_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F2R2_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F2R2_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F2R2_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F2R2_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F2R2_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F2R2_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F2R2_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F2R2_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F2R2_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F2R2_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F2R2_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F2R2_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F2R2_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F2R2_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F2R2_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F2R2_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F2R2_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F2R2_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F2R2_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F2R2_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F2R2_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F2R2_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F2R2_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F2R2_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F2R2_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F2R2_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F2R2_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F2R2_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F3R2 register *******************/
+#define CAN_F3R2_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F3R2_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F3R2_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F3R2_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F3R2_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F3R2_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F3R2_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F3R2_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F3R2_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F3R2_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F3R2_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F3R2_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F3R2_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F3R2_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F3R2_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F3R2_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F3R2_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F3R2_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F3R2_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F3R2_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F3R2_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F3R2_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F3R2_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F3R2_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F3R2_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F3R2_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F3R2_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F3R2_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F3R2_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F3R2_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F3R2_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F3R2_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F4R2 register *******************/
+#define CAN_F4R2_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F4R2_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F4R2_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F4R2_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F4R2_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F4R2_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F4R2_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F4R2_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F4R2_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F4R2_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F4R2_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F4R2_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F4R2_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F4R2_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F4R2_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F4R2_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F4R2_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F4R2_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F4R2_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F4R2_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F4R2_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F4R2_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F4R2_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F4R2_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F4R2_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F4R2_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F4R2_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F4R2_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F4R2_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F4R2_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F4R2_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F4R2_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F5R2 register *******************/
+#define CAN_F5R2_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F5R2_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F5R2_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F5R2_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F5R2_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F5R2_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F5R2_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F5R2_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F5R2_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F5R2_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F5R2_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F5R2_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F5R2_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F5R2_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F5R2_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F5R2_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F5R2_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F5R2_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F5R2_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F5R2_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F5R2_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F5R2_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F5R2_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F5R2_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F5R2_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F5R2_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F5R2_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F5R2_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F5R2_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F5R2_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F5R2_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F5R2_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F6R2 register *******************/
+#define CAN_F6R2_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F6R2_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F6R2_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F6R2_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F6R2_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F6R2_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F6R2_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F6R2_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F6R2_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F6R2_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F6R2_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F6R2_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F6R2_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F6R2_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F6R2_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F6R2_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F6R2_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F6R2_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F6R2_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F6R2_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F6R2_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F6R2_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F6R2_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F6R2_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F6R2_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F6R2_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F6R2_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F6R2_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F6R2_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F6R2_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F6R2_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F6R2_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F7R2 register *******************/
+#define CAN_F7R2_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F7R2_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F7R2_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F7R2_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F7R2_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F7R2_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F7R2_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F7R2_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F7R2_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F7R2_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F7R2_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F7R2_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F7R2_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F7R2_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F7R2_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F7R2_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F7R2_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F7R2_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F7R2_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F7R2_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F7R2_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F7R2_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F7R2_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F7R2_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F7R2_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F7R2_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F7R2_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F7R2_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F7R2_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F7R2_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F7R2_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F7R2_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F8R2 register *******************/
+#define CAN_F8R2_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F8R2_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F8R2_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F8R2_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F8R2_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F8R2_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F8R2_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F8R2_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F8R2_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F8R2_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F8R2_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F8R2_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F8R2_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F8R2_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F8R2_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F8R2_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F8R2_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F8R2_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F8R2_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F8R2_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F8R2_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F8R2_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F8R2_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F8R2_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F8R2_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F8R2_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F8R2_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F8R2_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F8R2_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F8R2_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F8R2_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F8R2_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F9R2 register *******************/
+#define CAN_F9R2_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F9R2_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F9R2_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F9R2_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F9R2_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F9R2_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F9R2_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F9R2_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F9R2_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F9R2_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F9R2_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F9R2_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F9R2_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F9R2_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F9R2_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F9R2_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F9R2_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F9R2_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F9R2_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F9R2_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F9R2_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F9R2_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F9R2_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F9R2_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F9R2_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F9R2_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F9R2_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F9R2_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F9R2_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F9R2_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F9R2_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F9R2_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F10R2 register ******************/
+#define CAN_F10R2_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F10R2_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F10R2_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F10R2_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F10R2_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F10R2_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F10R2_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F10R2_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F10R2_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F10R2_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F10R2_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F10R2_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F10R2_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F10R2_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F10R2_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F10R2_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F10R2_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F10R2_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F10R2_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F10R2_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F10R2_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F10R2_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F10R2_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F10R2_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F10R2_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F10R2_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F10R2_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F10R2_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F10R2_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F10R2_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F10R2_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F10R2_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F11R2 register ******************/
+#define CAN_F11R2_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F11R2_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F11R2_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F11R2_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F11R2_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F11R2_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F11R2_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F11R2_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F11R2_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F11R2_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F11R2_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F11R2_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F11R2_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F11R2_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F11R2_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F11R2_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F11R2_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F11R2_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F11R2_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F11R2_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F11R2_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F11R2_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F11R2_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F11R2_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F11R2_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F11R2_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F11R2_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F11R2_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F11R2_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F11R2_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F11R2_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F11R2_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F12R2 register ******************/
+#define CAN_F12R2_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F12R2_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F12R2_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F12R2_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F12R2_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F12R2_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F12R2_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F12R2_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F12R2_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F12R2_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F12R2_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F12R2_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F12R2_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F12R2_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F12R2_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F12R2_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F12R2_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F12R2_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F12R2_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F12R2_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F12R2_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F12R2_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F12R2_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F12R2_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F12R2_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F12R2_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F12R2_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F12R2_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F12R2_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F12R2_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F12R2_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F12R2_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F13R2 register ******************/
+#define CAN_F13R2_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F13R2_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F13R2_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F13R2_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F13R2_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F13R2_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F13R2_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F13R2_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F13R2_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F13R2_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F13R2_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F13R2_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F13R2_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F13R2_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F13R2_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F13R2_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F13R2_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F13R2_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F13R2_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F13R2_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F13R2_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F13R2_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F13R2_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F13R2_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F13R2_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F13R2_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F13R2_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F13R2_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F13R2_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F13R2_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F13R2_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F13R2_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************************************************************************/
+/* */
+/* CRC calculation unit */
+/* */
+/******************************************************************************/
+/******************* Bit definition for CRC_DR register *********************/
+#define CRC_DR_DR 0xFFFFFFFFU /*!< Data register bits */
+
+
+/******************* Bit definition for CRC_IDR register ********************/
+#define CRC_IDR_IDR 0xFFU /*!< General-purpose 8-bit data register bits */
+
+
+/******************** Bit definition for CRC_CR register ********************/
+#define CRC_CR_RESET 0x01U /*!< RESET bit */
+
+/******************************************************************************/
+/* */
+/* Debug MCU */
+/* */
+/******************************************************************************/
+
+/******************************************************************************/
+/* */
+/* Digital Filter for Sigma Delta Modulators */
+/* */
+/******************************************************************************/
+
+/**************** DFSDM channel configuration registers ********************/
+
+/*************** Bit definition for DFSDM_CHCFGR1 register ******************/
+#define DFSDM_CHCFGR1_DFSDMEN 0x80000000U /*!< Global enable for DFSDM interface */
+#define DFSDM_CHCFGR1_CKOUTSRC 0x40000000U /*!< Output serial clock source selection */
+#define DFSDM_CHCFGR1_CKOUTDIV 0x00FF0000U /*!< CKOUTDIV[7:0] output serial clock divider */
+#define DFSDM_CHCFGR1_DATPACK 0x0000C000U /*!< DATPACK[1:0] Data packing mode */
+#define DFSDM_CHCFGR1_DATPACK_1 0x00008000U /*!< Data packing mode, Bit 1 */
+#define DFSDM_CHCFGR1_DATPACK_0 0x00004000U /*!< Data packing mode, Bit 0 */
+#define DFSDM_CHCFGR1_DATMPX 0x00003000U /*!< DATMPX[1:0] Input data multiplexer for channel y */
+#define DFSDM_CHCFGR1_DATMPX_1 0x00002000U /*!< Input data multiplexer for channel y, Bit 1 */
+#define DFSDM_CHCFGR1_DATMPX_0 0x00001000U /*!< Input data multiplexer for channel y, Bit 0 */
+#define DFSDM_CHCFGR1_CHINSEL 0x00000100U /*!< Serial inputs selection for channel y */
+#define DFSDM_CHCFGR1_CHEN 0x00000080U /*!< Channel y enable */
+#define DFSDM_CHCFGR1_CKABEN 0x00000040U /*!< Clock absence detector enable on channel y */
+#define DFSDM_CHCFGR1_SCDEN 0x00000020U /*!< Short circuit detector enable on channel y */
+#define DFSDM_CHCFGR1_SPICKSEL 0x0000000CU /*!< SPICKSEL[1:0] SPI clock select for channel y */
+#define DFSDM_CHCFGR1_SPICKSEL_1 0x00000008U /*!< SPI clock select for channel y, Bit 1 */
+#define DFSDM_CHCFGR1_SPICKSEL_0 0x00000004U /*!< SPI clock select for channel y, Bit 0 */
+#define DFSDM_CHCFGR1_SITP 0x00000003U /*!< SITP[1:0] Serial interface type for channel y */
+#define DFSDM_CHCFGR1_SITP_1 0x00000002U /*!< Serial interface type for channel y, Bit 1 */
+#define DFSDM_CHCFGR1_SITP_0 0x00000001U /*!< Serial interface type for channel y, Bit 0 */
+
+/*************** Bit definition for DFSDM_CHCFGR2 register ******************/
+#define DFSDM_CHCFGR2_OFFSET 0xFFFFFF00U /*!< OFFSET[23:0] 24-bit calibration offset for channel y */
+#define DFSDM_CHCFGR2_DTRBS 0x000000F8U /*!< DTRBS[4:0] Data right bit-shift for channel y */
+
+/**************** Bit definition for DFSDM_CHAWSCDR register *****************/
+#define DFSDM_CHAWSCDR_AWFORD 0x00C00000U /*!< AWFORD[1:0] Analog watchdog Sinc filter order on channel y */
+#define DFSDM_CHAWSCDR_AWFORD_1 0x00800000U /*!< Analog watchdog Sinc filter order on channel y, Bit 1 */
+#define DFSDM_CHAWSCDR_AWFORD_0 0x00400000U /*!< Analog watchdog Sinc filter order on channel y, Bit 0 */
+#define DFSDM_CHAWSCDR_AWFOSR 0x001F0000U /*!< AWFOSR[4:0] Analog watchdog filter oversampling ratio on channel y */
+#define DFSDM_CHAWSCDR_BKSCD 0x0000F000U /*!< BKSCD[3:0] Break signal assignment for short circuit detector on channel y */
+#define DFSDM_CHAWSCDR_SCDT 0x000000FFU /*!< SCDT[7:0] Short circuit detector threshold for channel y */
+
+/**************** Bit definition for DFSDM_CHWDATR register *******************/
+#define DFSDM_CHWDATR_WDATA 0x0000FFFFU /*!< WDATA[15:0] Input channel y watchdog data */
+
+/**************** Bit definition for DFSDM_CHDATINR register *****************/
+#define DFSDM_CHDATINR_INDAT0 0x0000FFFFU /*!< INDAT0[31:16] Input data for channel y or channel (y+1) */
+#define DFSDM_CHDATINR_INDAT1 0xFFFF0000U /*!< INDAT0[15:0] Input data for channel y */
+
+/************************ DFSDM module registers ****************************/
+
+/***************** Bit definition for DFSDM_FLTCR1 register *******************/
+#define DFSDM_FLTCR1_AWFSEL 0x40000000U /*!< Analog watchdog fast mode select */
+#define DFSDM_FLTCR1_FAST 0x20000000U /*!< Fast conversion mode selection */
+#define DFSDM_FLTCR1_RCH 0x07000000U /*!< RCH[2:0] Regular channel selection */
+#define DFSDM_FLTCR1_RDMAEN 0x00200000U /*!< DMA channel enabled to read data for the regular conversion */
+#define DFSDM_FLTCR1_RSYNC 0x00080000U /*!< Launch regular conversion synchronously with DFSDMx */
+#define DFSDM_FLTCR1_RCONT 0x00040000U /*!< Continuous mode selection for regular conversions */
+#define DFSDM_FLTCR1_RSWSTART 0x00020000U /*!< Software start of a conversion on the regular channel */
+#define DFSDM_FLTCR1_JEXTEN 0x00006000U /*!< JEXTEN[1:0] Trigger enable and trigger edge selection for injected conversions */
+#define DFSDM_FLTCR1_JEXTEN_1 0x00004000U /*!< Trigger enable and trigger edge selection for injected conversions, Bit 1 */
+#define DFSDM_FLTCR1_JEXTEN_0 0x00002000U /*!< Trigger enable and trigger edge selection for injected conversions, Bit 0 */
+#define DFSDM_FLTCR1_JEXTSEL 0x00000700U /*!< JEXTSEL[2:0]Trigger signal selection for launching injected conversions */
+#define DFSDM_FLTCR1_JEXTSEL_2 0x00000400U /*!< Trigger signal selection for launching injected conversions, Bit 2 */
+#define DFSDM_FLTCR1_JEXTSEL_1 0x00000200U /*!< Trigger signal selection for launching injected conversions, Bit 1 */
+#define DFSDM_FLTCR1_JEXTSEL_0 0x00000100U /*!< Trigger signal selection for launching injected conversions, Bit 0 */
+#define DFSDM_FLTCR1_JDMAEN 0x00000020U /*!< DMA channel enabled to read data for the injected channel group */
+#define DFSDM_FLTCR1_JSCAN 0x00000010U /*!< Scanning conversion in continuous mode selection for injected conversions */
+#define DFSDM_FLTCR1_JSYNC 0x00000008U /*!< Launch an injected conversion synchronously with DFSDMx JSWSTART trigger */
+#define DFSDM_FLTCR1_JSWSTART 0x00000002U /*!< Start the conversion of the injected group of channels */
+#define DFSDM_FLTCR1_DFEN 0x00000001U /*!< DFSDM enable */
+
+/***************** Bit definition for DFSDM_FLTCR2 register *******************/
+#define DFSDM_FLTCR2_AWDCH 0x000F0000U /*!< AWDCH[7:0] Analog watchdog channel selection */
+#define DFSDM_FLTCR2_EXCH 0x00000F00U /*!< EXCH[7:0] Extreme detector channel selection */
+#define DFSDM_FLTCR2_CKABIE 0x00000040U /*!< Clock absence interrupt enable */
+#define DFSDM_FLTCR2_SCDIE 0x00000020U /*!< Short circuit detector interrupt enable */
+#define DFSDM_FLTCR2_AWDIE 0x00000010U /*!< Analog watchdog interrupt enable */
+#define DFSDM_FLTCR2_ROVRIE 0x00000008U /*!< Regular data overrun interrupt enable */
+#define DFSDM_FLTCR2_JOVRIE 0x00000004U /*!< Injected data overrun interrupt enable */
+#define DFSDM_FLTCR2_REOCIE 0x00000002U /*!< Regular end of conversion interrupt enable */
+#define DFSDM_FLTCR2_JEOCIE 0x00000001U /*!< Injected end of conversion interrupt enable */
+
+/***************** Bit definition for DFSDM_FLTISR register *******************/
+#define DFSDM_FLTISR_SCDF 0x0F000000U /*!< SCDF[7:0] Short circuit detector flag */
+#define DFSDM_FLTISR_CKABF 0x000F0000U /*!< CKABF[7:0] Clock absence flag */
+#define DFSDM_FLTISR_RCIP 0x00004000U /*!< Regular conversion in progress status */
+#define DFSDM_FLTISR_JCIP 0x00002000U /*!< Injected conversion in progress status */
+#define DFSDM_FLTISR_AWDF 0x00000010U /*!< Analog watchdog */
+#define DFSDM_FLTISR_ROVRF 0x00000008U /*!< Regular conversion overrun flag */
+#define DFSDM_FLTISR_JOVRF 0x00000004U /*!< Injected conversion overrun flag */
+#define DFSDM_FLTISR_REOCF 0x00000002U /*!< End of regular conversion flag */
+#define DFSDM_FLTISR_JEOCF 0x00000001U /*!< End of injected conversion flag */
+
+/***************** Bit definition for DFSDM_FLTICR register *******************/
+#define DFSDM_FLTICR_CLRSCSDF 0x0F000000U /*!< CLRSCSDF[7:0] Clear the short circuit detector flag */
+#define DFSDM_FLTICR_CLRCKABF 0x000F0000U /*!< CLRCKABF[7:0] Clear the clock absence flag */
+#define DFSDM_FLTICR_CLRROVRF 0x00000008U /*!< Clear the regular conversion overrun flag */
+#define DFSDM_FLTICR_CLRJOVRF 0x00000004U /*!< Clear the injected conversion overrun flag */
+
+/**************** Bit definition for DFSDM_FLTJCHGR register ******************/
+#define DFSDM_FLTJCHGR_JCHG 0x0000000FU /*!< JCHG[7:0] Injected channel group selection */
+
+/***************** Bit definition for DFSDM_FLTFCR register *******************/
+#define DFSDM_FLTFCR_FORD 0xE0000000U /*!< FORD[2:0] Sinc filter order */
+#define DFSDM_FLTFCR_FORD_2 0x80000000U /*!< Sinc filter order, Bit 2 */
+#define DFSDM_FLTFCR_FORD_1 0x40000000U /*!< Sinc filter order, Bit 1 */
+#define DFSDM_FLTFCR_FORD_0 0x20000000U /*!< Sinc filter order, Bit 0 */
+#define DFSDM_FLTFCR_FOSR 0x03FF0000U /*!< FOSR[9:0] Sinc filter oversampling ratio (decimation rate) */
+#define DFSDM_FLTFCR_IOSR 0x000000FFU /*!< IOSR[7:0] Integrator oversampling ratio (averaging length) */
+
+/*************** Bit definition for DFSDM_FLTJDATAR register *****************/
+#define DFSDM_FLTJDATAR_JDATA 0xFFFFFF00U /*!< JDATA[23:0] Injected group conversion data */
+#define DFSDM_FLTJDATAR_JDATACH 0x00000007U /*!< JDATACH[2:0] Injected channel most recently converted */
+
+/*************** Bit definition for DFSDM_FLTRDATAR register *****************/
+#define DFSDM_FLTRDATAR_RDATA 0xFFFFFF00U /*!< RDATA[23:0] Regular channel conversion data */
+#define DFSDM_FLTRDATAR_RPEND 0x00000010U /*!< RPEND Regular channel pending data */
+#define DFSDM_FLTRDATAR_RDATACH 0x00000007U /*!< RDATACH[2:0] Regular channel most recently converted */
+
+/*************** Bit definition for DFSDM_FLTAWHTR register ******************/
+#define DFSDM_FLTAWHTR_AWHT 0xFFFFFF00U /*!< AWHT[23:0] Analog watchdog high threshold */
+#define DFSDM_FLTAWHTR_BKAWH 0x0000000FU /*!< BKAWH[3:0] Break signal assignment to analog watchdog high threshold event */
+
+/*************** Bit definition for DFSDM_FLTAWLTR register ******************/
+#define DFSDM_FLTAWLTR_AWLT 0xFFFFFF00U /*!< AWLT[23:0] Analog watchdog low threshold */
+#define DFSDM_FLTAWLTR_BKAWL 0x0000000FU /*!< BKAWL[3:0] Break signal assignment to analog watchdog low threshold event */
+
+/*************** Bit definition for DFSDM_FLTAWSR register *******************/
+#define DFSDM_FLTAWSR_AWHTF 0x00000F00U /*!< AWHTF[15:8] Analog watchdog high threshold error on given channels */
+#define DFSDM_FLTAWSR_AWLTF 0x0000000FU /*!< AWLTF[7:0] Analog watchdog low threshold error on given channels */
+
+/*************** Bit definition for DFSDM_FLTAWCFR register ******************/
+#define DFSDM_FLTAWCFR_CLRAWHTF 0x00000F00U /*!< CLRAWHTF[15:8] Clear the Analog watchdog high threshold flag */
+#define DFSDM_FLTAWCFR_CLRAWLTF 0x0000000FU /*!< CLRAWLTF[7:0] Clear the Analog watchdog low threshold flag */
+
+/*************** Bit definition for DFSDM_FLTEXMAX register ******************/
+#define DFSDM_FLTEXMAX_EXMAX 0xFFFFFF00U /*!< EXMAX[23:0] Extreme detector maximum value */
+#define DFSDM_FLTEXMAX_EXMAXCH 0x00000007U /*!< EXMAXCH[2:0] Extreme detector maximum data channel */
+
+/*************** Bit definition for DFSDM_FLTEXMIN register ******************/
+#define DFSDM_FLTEXMIN_EXMIN 0xFFFFFF00U /*!< EXMIN[23:0] Extreme detector minimum value */
+#define DFSDM_FLTEXMIN_EXMINCH 0x00000007U /*!< EXMINCH[2:0] Extreme detector minimum data channel */
+
+/*************** Bit definition for DFSDM_FLTCNVTIMR register ****************/
+#define DFSDM_FLTCNVTIMR_CNVCNT 0xFFFFFFF0U /*!< CNVCNT[27:0]: 28-bit timer counting conversion time */
+
+/******************************************************************************/
+/* */
+/* DMA Controller */
+/* */
+/******************************************************************************/
+/******************** Bits definition for DMA_SxCR register *****************/
+#define DMA_SxCR_CHSEL 0x0E000000U
+#define DMA_SxCR_CHSEL_0 0x02000000U
+#define DMA_SxCR_CHSEL_1 0x04000000U
+#define DMA_SxCR_CHSEL_2 0x08000000U
+#define DMA_SxCR_MBURST 0x01800000U
+#define DMA_SxCR_MBURST_0 0x00800000U
+#define DMA_SxCR_MBURST_1 0x01000000U
+#define DMA_SxCR_PBURST 0x00600000U
+#define DMA_SxCR_PBURST_0 0x00200000U
+#define DMA_SxCR_PBURST_1 0x00400000U
+#define DMA_SxCR_CT 0x00080000U
+#define DMA_SxCR_DBM 0x00040000U
+#define DMA_SxCR_PL 0x00030000U
+#define DMA_SxCR_PL_0 0x00010000U
+#define DMA_SxCR_PL_1 0x00020000U
+#define DMA_SxCR_PINCOS 0x00008000U
+#define DMA_SxCR_MSIZE 0x00006000U
+#define DMA_SxCR_MSIZE_0 0x00002000U
+#define DMA_SxCR_MSIZE_1 0x00004000U
+#define DMA_SxCR_PSIZE 0x00001800U
+#define DMA_SxCR_PSIZE_0 0x00000800U
+#define DMA_SxCR_PSIZE_1 0x00001000U
+#define DMA_SxCR_MINC 0x00000400U
+#define DMA_SxCR_PINC 0x00000200U
+#define DMA_SxCR_CIRC 0x00000100U
+#define DMA_SxCR_DIR 0x000000C0U
+#define DMA_SxCR_DIR_0 0x00000040U
+#define DMA_SxCR_DIR_1 0x00000080U
+#define DMA_SxCR_PFCTRL 0x00000020U
+#define DMA_SxCR_TCIE 0x00000010U
+#define DMA_SxCR_HTIE 0x00000008U
+#define DMA_SxCR_TEIE 0x00000004U
+#define DMA_SxCR_DMEIE 0x00000002U
+#define DMA_SxCR_EN 0x00000001U
+
+/* Legacy defines */
+#define DMA_SxCR_ACK 0x00100000U
+
+/******************** Bits definition for DMA_SxCNDTR register **************/
+#define DMA_SxNDT 0x0000FFFFU
+#define DMA_SxNDT_0 0x00000001U
+#define DMA_SxNDT_1 0x00000002U
+#define DMA_SxNDT_2 0x00000004U
+#define DMA_SxNDT_3 0x00000008U
+#define DMA_SxNDT_4 0x00000010U
+#define DMA_SxNDT_5 0x00000020U
+#define DMA_SxNDT_6 0x00000040U
+#define DMA_SxNDT_7 0x00000080U
+#define DMA_SxNDT_8 0x00000100U
+#define DMA_SxNDT_9 0x00000200U
+#define DMA_SxNDT_10 0x00000400U
+#define DMA_SxNDT_11 0x00000800U
+#define DMA_SxNDT_12 0x00001000U
+#define DMA_SxNDT_13 0x00002000U
+#define DMA_SxNDT_14 0x00004000U
+#define DMA_SxNDT_15 0x00008000U
+
+/******************** Bits definition for DMA_SxFCR register ****************/
+#define DMA_SxFCR_FEIE 0x00000080U
+#define DMA_SxFCR_FS 0x00000038U
+#define DMA_SxFCR_FS_0 0x00000008U
+#define DMA_SxFCR_FS_1 0x00000010U
+#define DMA_SxFCR_FS_2 0x00000020U
+#define DMA_SxFCR_DMDIS 0x00000004U
+#define DMA_SxFCR_FTH 0x00000003U
+#define DMA_SxFCR_FTH_0 0x00000001U
+#define DMA_SxFCR_FTH_1 0x00000002U
+
+/******************** Bits definition for DMA_LISR register *****************/
+#define DMA_LISR_TCIF3 0x08000000U
+#define DMA_LISR_HTIF3 0x04000000U
+#define DMA_LISR_TEIF3 0x02000000U
+#define DMA_LISR_DMEIF3 0x01000000U
+#define DMA_LISR_FEIF3 0x00400000U
+#define DMA_LISR_TCIF2 0x00200000U
+#define DMA_LISR_HTIF2 0x00100000U
+#define DMA_LISR_TEIF2 0x00080000U
+#define DMA_LISR_DMEIF2 0x00040000U
+#define DMA_LISR_FEIF2 0x00010000U
+#define DMA_LISR_TCIF1 0x00000800U
+#define DMA_LISR_HTIF1 0x00000400U
+#define DMA_LISR_TEIF1 0x00000200U
+#define DMA_LISR_DMEIF1 0x00000100U
+#define DMA_LISR_FEIF1 0x00000040U
+#define DMA_LISR_TCIF0 0x00000020U
+#define DMA_LISR_HTIF0 0x00000010U
+#define DMA_LISR_TEIF0 0x00000008U
+#define DMA_LISR_DMEIF0 0x00000004U
+#define DMA_LISR_FEIF0 0x00000001U
+
+/******************** Bits definition for DMA_HISR register *****************/
+#define DMA_HISR_TCIF7 0x08000000U
+#define DMA_HISR_HTIF7 0x04000000U
+#define DMA_HISR_TEIF7 0x02000000U
+#define DMA_HISR_DMEIF7 0x01000000U
+#define DMA_HISR_FEIF7 0x00400000U
+#define DMA_HISR_TCIF6 0x00200000U
+#define DMA_HISR_HTIF6 0x00100000U
+#define DMA_HISR_TEIF6 0x00080000U
+#define DMA_HISR_DMEIF6 0x00040000U
+#define DMA_HISR_FEIF6 0x00010000U
+#define DMA_HISR_TCIF5 0x00000800U
+#define DMA_HISR_HTIF5 0x00000400U
+#define DMA_HISR_TEIF5 0x00000200U
+#define DMA_HISR_DMEIF5 0x00000100U
+#define DMA_HISR_FEIF5 0x00000040U
+#define DMA_HISR_TCIF4 0x00000020U
+#define DMA_HISR_HTIF4 0x00000010U
+#define DMA_HISR_TEIF4 0x00000008U
+#define DMA_HISR_DMEIF4 0x00000004U
+#define DMA_HISR_FEIF4 0x00000001U
+
+/******************** Bits definition for DMA_LIFCR register ****************/
+#define DMA_LIFCR_CTCIF3 0x08000000U
+#define DMA_LIFCR_CHTIF3 0x04000000U
+#define DMA_LIFCR_CTEIF3 0x02000000U
+#define DMA_LIFCR_CDMEIF3 0x01000000U
+#define DMA_LIFCR_CFEIF3 0x00400000U
+#define DMA_LIFCR_CTCIF2 0x00200000U
+#define DMA_LIFCR_CHTIF2 0x00100000U
+#define DMA_LIFCR_CTEIF2 0x00080000U
+#define DMA_LIFCR_CDMEIF2 0x00040000U
+#define DMA_LIFCR_CFEIF2 0x00010000U
+#define DMA_LIFCR_CTCIF1 0x00000800U
+#define DMA_LIFCR_CHTIF1 0x00000400U
+#define DMA_LIFCR_CTEIF1 0x00000200U
+#define DMA_LIFCR_CDMEIF1 0x00000100U
+#define DMA_LIFCR_CFEIF1 0x00000040U
+#define DMA_LIFCR_CTCIF0 0x00000020U
+#define DMA_LIFCR_CHTIF0 0x00000010U
+#define DMA_LIFCR_CTEIF0 0x00000008U
+#define DMA_LIFCR_CDMEIF0 0x00000004U
+#define DMA_LIFCR_CFEIF0 0x00000001U
+
+/******************** Bits definition for DMA_HIFCR register ****************/
+#define DMA_HIFCR_CTCIF7 0x08000000U
+#define DMA_HIFCR_CHTIF7 0x04000000U
+#define DMA_HIFCR_CTEIF7 0x02000000U
+#define DMA_HIFCR_CDMEIF7 0x01000000U
+#define DMA_HIFCR_CFEIF7 0x00400000U
+#define DMA_HIFCR_CTCIF6 0x00200000U
+#define DMA_HIFCR_CHTIF6 0x00100000U
+#define DMA_HIFCR_CTEIF6 0x00080000U
+#define DMA_HIFCR_CDMEIF6 0x00040000U
+#define DMA_HIFCR_CFEIF6 0x00010000U
+#define DMA_HIFCR_CTCIF5 0x00000800U
+#define DMA_HIFCR_CHTIF5 0x00000400U
+#define DMA_HIFCR_CTEIF5 0x00000200U
+#define DMA_HIFCR_CDMEIF5 0x00000100U
+#define DMA_HIFCR_CFEIF5 0x00000040U
+#define DMA_HIFCR_CTCIF4 0x00000020U
+#define DMA_HIFCR_CHTIF4 0x00000010U
+#define DMA_HIFCR_CTEIF4 0x00000008U
+#define DMA_HIFCR_CDMEIF4 0x00000004U
+#define DMA_HIFCR_CFEIF4 0x00000001U
+
+
+/******************************************************************************/
+/* */
+/* External Interrupt/Event Controller */
+/* */
+/******************************************************************************/
+/******************* Bit definition for EXTI_IMR register *******************/
+#define EXTI_IMR_MR0 0x00000001U /*!< Interrupt Mask on line 0 */
+#define EXTI_IMR_MR1 0x00000002U /*!< Interrupt Mask on line 1 */
+#define EXTI_IMR_MR2 0x00000004U /*!< Interrupt Mask on line 2 */
+#define EXTI_IMR_MR3 0x00000008U /*!< Interrupt Mask on line 3 */
+#define EXTI_IMR_MR4 0x00000010U /*!< Interrupt Mask on line 4 */
+#define EXTI_IMR_MR5 0x00000020U /*!< Interrupt Mask on line 5 */
+#define EXTI_IMR_MR6 0x00000040U /*!< Interrupt Mask on line 6 */
+#define EXTI_IMR_MR7 0x00000080U /*!< Interrupt Mask on line 7 */
+#define EXTI_IMR_MR8 0x00000100U /*!< Interrupt Mask on line 8 */
+#define EXTI_IMR_MR9 0x00000200U /*!< Interrupt Mask on line 9 */
+#define EXTI_IMR_MR10 0x00000400U /*!< Interrupt Mask on line 10 */
+#define EXTI_IMR_MR11 0x00000800U /*!< Interrupt Mask on line 11 */
+#define EXTI_IMR_MR12 0x00001000U /*!< Interrupt Mask on line 12 */
+#define EXTI_IMR_MR13 0x00002000U /*!< Interrupt Mask on line 13 */
+#define EXTI_IMR_MR14 0x00004000U /*!< Interrupt Mask on line 14 */
+#define EXTI_IMR_MR15 0x00008000U /*!< Interrupt Mask on line 15 */
+#define EXTI_IMR_MR16 0x00010000U /*!< Interrupt Mask on line 16 */
+#define EXTI_IMR_MR17 0x00020000U /*!< Interrupt Mask on line 17 */
+#define EXTI_IMR_MR18 0x00040000U /*!< Interrupt Mask on line 18 */
+#define EXTI_IMR_MR19 0x00080000U /*!< Interrupt Mask on line 19 */
+#define EXTI_IMR_MR20 0x00100000U /*!< Interrupt Mask on line 20 */
+#define EXTI_IMR_MR21 0x00200000U /*!< Interrupt Mask on line 21 */
+#define EXTI_IMR_MR22 0x00400000U /*!< Interrupt Mask on line 22 */
+
+/******************* Bit definition for EXTI_EMR register *******************/
+#define EXTI_EMR_MR0 0x00000001U /*!< Event Mask on line 0 */
+#define EXTI_EMR_MR1 0x00000002U /*!< Event Mask on line 1 */
+#define EXTI_EMR_MR2 0x00000004U /*!< Event Mask on line 2 */
+#define EXTI_EMR_MR3 0x00000008U /*!< Event Mask on line 3 */
+#define EXTI_EMR_MR4 0x00000010U /*!< Event Mask on line 4 */
+#define EXTI_EMR_MR5 0x00000020U /*!< Event Mask on line 5 */
+#define EXTI_EMR_MR6 0x00000040U /*!< Event Mask on line 6 */
+#define EXTI_EMR_MR7 0x00000080U /*!< Event Mask on line 7 */
+#define EXTI_EMR_MR8 0x00000100U /*!< Event Mask on line 8 */
+#define EXTI_EMR_MR9 0x00000200U /*!< Event Mask on line 9 */
+#define EXTI_EMR_MR10 0x00000400U /*!< Event Mask on line 10 */
+#define EXTI_EMR_MR11 0x00000800U /*!< Event Mask on line 11 */
+#define EXTI_EMR_MR12 0x00001000U /*!< Event Mask on line 12 */
+#define EXTI_EMR_MR13 0x00002000U /*!< Event Mask on line 13 */
+#define EXTI_EMR_MR14 0x00004000U /*!< Event Mask on line 14 */
+#define EXTI_EMR_MR15 0x00008000U /*!< Event Mask on line 15 */
+#define EXTI_EMR_MR16 0x00010000U /*!< Event Mask on line 16 */
+#define EXTI_EMR_MR17 0x00020000U /*!< Event Mask on line 17 */
+#define EXTI_EMR_MR18 0x00040000U /*!< Event Mask on line 18 */
+#define EXTI_EMR_MR19 0x00080000U /*!< Event Mask on line 19 */
+#define EXTI_EMR_MR20 0x00100000U /*!< Event Mask on line 20 */
+#define EXTI_EMR_MR21 0x00200000U /*!< Event Mask on line 21 */
+#define EXTI_EMR_MR22 0x00400000U /*!< Event Mask on line 22 */
+
+/****************** Bit definition for EXTI_RTSR register *******************/
+#define EXTI_RTSR_TR0 0x00000001U /*!< Rising trigger event configuration bit of line 0 */
+#define EXTI_RTSR_TR1 0x00000002U /*!< Rising trigger event configuration bit of line 1 */
+#define EXTI_RTSR_TR2 0x00000004U /*!< Rising trigger event configuration bit of line 2 */
+#define EXTI_RTSR_TR3 0x00000008U /*!< Rising trigger event configuration bit of line 3 */
+#define EXTI_RTSR_TR4 0x00000010U /*!< Rising trigger event configuration bit of line 4 */
+#define EXTI_RTSR_TR5 0x00000020U /*!< Rising trigger event configuration bit of line 5 */
+#define EXTI_RTSR_TR6 0x00000040U /*!< Rising trigger event configuration bit of line 6 */
+#define EXTI_RTSR_TR7 0x00000080U /*!< Rising trigger event configuration bit of line 7 */
+#define EXTI_RTSR_TR8 0x00000100U /*!< Rising trigger event configuration bit of line 8 */
+#define EXTI_RTSR_TR9 0x00000200U /*!< Rising trigger event configuration bit of line 9 */
+#define EXTI_RTSR_TR10 0x00000400U /*!< Rising trigger event configuration bit of line 10 */
+#define EXTI_RTSR_TR11 0x00000800U /*!< Rising trigger event configuration bit of line 11 */
+#define EXTI_RTSR_TR12 0x00001000U /*!< Rising trigger event configuration bit of line 12 */
+#define EXTI_RTSR_TR13 0x00002000U /*!< Rising trigger event configuration bit of line 13 */
+#define EXTI_RTSR_TR14 0x00004000U /*!< Rising trigger event configuration bit of line 14 */
+#define EXTI_RTSR_TR15 0x00008000U /*!< Rising trigger event configuration bit of line 15 */
+#define EXTI_RTSR_TR16 0x00010000U /*!< Rising trigger event configuration bit of line 16 */
+#define EXTI_RTSR_TR17 0x00020000U /*!< Rising trigger event configuration bit of line 17 */
+#define EXTI_RTSR_TR18 0x00040000U /*!< Rising trigger event configuration bit of line 18 */
+#define EXTI_RTSR_TR19 0x00080000U /*!< Rising trigger event configuration bit of line 19 */
+#define EXTI_RTSR_TR20 0x00100000U /*!< Rising trigger event configuration bit of line 20 */
+#define EXTI_RTSR_TR21 0x00200000U /*!< Rising trigger event configuration bit of line 21 */
+#define EXTI_RTSR_TR22 0x00400000U /*!< Rising trigger event configuration bit of line 22 */
+
+/****************** Bit definition for EXTI_FTSR register *******************/
+#define EXTI_FTSR_TR0 0x00000001U /*!< Falling trigger event configuration bit of line 0 */
+#define EXTI_FTSR_TR1 0x00000002U /*!< Falling trigger event configuration bit of line 1 */
+#define EXTI_FTSR_TR2 0x00000004U /*!< Falling trigger event configuration bit of line 2 */
+#define EXTI_FTSR_TR3 0x00000008U /*!< Falling trigger event configuration bit of line 3 */
+#define EXTI_FTSR_TR4 0x00000010U /*!< Falling trigger event configuration bit of line 4 */
+#define EXTI_FTSR_TR5 0x00000020U /*!< Falling trigger event configuration bit of line 5 */
+#define EXTI_FTSR_TR6 0x00000040U /*!< Falling trigger event configuration bit of line 6 */
+#define EXTI_FTSR_TR7 0x00000080U /*!< Falling trigger event configuration bit of line 7 */
+#define EXTI_FTSR_TR8 0x00000100U /*!< Falling trigger event configuration bit of line 8 */
+#define EXTI_FTSR_TR9 0x00000200U /*!< Falling trigger event configuration bit of line 9 */
+#define EXTI_FTSR_TR10 0x00000400U /*!< Falling trigger event configuration bit of line 10 */
+#define EXTI_FTSR_TR11 0x00000800U /*!< Falling trigger event configuration bit of line 11 */
+#define EXTI_FTSR_TR12 0x00001000U /*!< Falling trigger event configuration bit of line 12 */
+#define EXTI_FTSR_TR13 0x00002000U /*!< Falling trigger event configuration bit of line 13 */
+#define EXTI_FTSR_TR14 0x00004000U /*!< Falling trigger event configuration bit of line 14 */
+#define EXTI_FTSR_TR15 0x00008000U /*!< Falling trigger event configuration bit of line 15 */
+#define EXTI_FTSR_TR16 0x00010000U /*!< Falling trigger event configuration bit of line 16 */
+#define EXTI_FTSR_TR17 0x00020000U /*!< Falling trigger event configuration bit of line 17 */
+#define EXTI_FTSR_TR18 0x00040000U /*!< Falling trigger event configuration bit of line 18 */
+#define EXTI_FTSR_TR19 0x00080000U /*!< Falling trigger event configuration bit of line 19 */
+#define EXTI_FTSR_TR20 0x00100000U /*!< Falling trigger event configuration bit of line 20 */
+#define EXTI_FTSR_TR21 0x00200000U /*!< Falling trigger event configuration bit of line 21 */
+#define EXTI_FTSR_TR22 0x00400000U /*!< Falling trigger event configuration bit of line 22 */
+
+/****************** Bit definition for EXTI_SWIER register ******************/
+#define EXTI_SWIER_SWIER0 0x00000001U /*!< Software Interrupt on line 0 */
+#define EXTI_SWIER_SWIER1 0x00000002U /*!< Software Interrupt on line 1 */
+#define EXTI_SWIER_SWIER2 0x00000004U /*!< Software Interrupt on line 2 */
+#define EXTI_SWIER_SWIER3 0x00000008U /*!< Software Interrupt on line 3 */
+#define EXTI_SWIER_SWIER4 0x00000010U /*!< Software Interrupt on line 4 */
+#define EXTI_SWIER_SWIER5 0x00000020U /*!< Software Interrupt on line 5 */
+#define EXTI_SWIER_SWIER6 0x00000040U /*!< Software Interrupt on line 6 */
+#define EXTI_SWIER_SWIER7 0x00000080U /*!< Software Interrupt on line 7 */
+#define EXTI_SWIER_SWIER8 0x00000100U /*!< Software Interrupt on line 8 */
+#define EXTI_SWIER_SWIER9 0x00000200U /*!< Software Interrupt on line 9 */
+#define EXTI_SWIER_SWIER10 0x00000400U /*!< Software Interrupt on line 10 */
+#define EXTI_SWIER_SWIER11 0x00000800U /*!< Software Interrupt on line 11 */
+#define EXTI_SWIER_SWIER12 0x00001000U /*!< Software Interrupt on line 12 */
+#define EXTI_SWIER_SWIER13 0x00002000U /*!< Software Interrupt on line 13 */
+#define EXTI_SWIER_SWIER14 0x00004000U /*!< Software Interrupt on line 14 */
+#define EXTI_SWIER_SWIER15 0x00008000U /*!< Software Interrupt on line 15 */
+#define EXTI_SWIER_SWIER16 0x00010000U /*!< Software Interrupt on line 16 */
+#define EXTI_SWIER_SWIER17 0x00020000U /*!< Software Interrupt on line 17 */
+#define EXTI_SWIER_SWIER18 0x00040000U /*!< Software Interrupt on line 18 */
+#define EXTI_SWIER_SWIER19 0x00080000U /*!< Software Interrupt on line 19 */
+#define EXTI_SWIER_SWIER20 0x00100000U /*!< Software Interrupt on line 20 */
+#define EXTI_SWIER_SWIER21 0x00200000U /*!< Software Interrupt on line 21 */
+#define EXTI_SWIER_SWIER22 0x00400000U /*!< Software Interrupt on line 22 */
+
+/******************* Bit definition for EXTI_PR register ********************/
+#define EXTI_PR_PR0 0x00000001U /*!< Pending bit for line 0 */
+#define EXTI_PR_PR1 0x00000002U /*!< Pending bit for line 1 */
+#define EXTI_PR_PR2 0x00000004U /*!< Pending bit for line 2 */
+#define EXTI_PR_PR3 0x00000008U /*!< Pending bit for line 3 */
+#define EXTI_PR_PR4 0x00000010U /*!< Pending bit for line 4 */
+#define EXTI_PR_PR5 0x00000020U /*!< Pending bit for line 5 */
+#define EXTI_PR_PR6 0x00000040U /*!< Pending bit for line 6 */
+#define EXTI_PR_PR7 0x00000080U /*!< Pending bit for line 7 */
+#define EXTI_PR_PR8 0x00000100U /*!< Pending bit for line 8 */
+#define EXTI_PR_PR9 0x00000200U /*!< Pending bit for line 9 */
+#define EXTI_PR_PR10 0x00000400U /*!< Pending bit for line 10 */
+#define EXTI_PR_PR11 0x00000800U /*!< Pending bit for line 11 */
+#define EXTI_PR_PR12 0x00001000U /*!< Pending bit for line 12 */
+#define EXTI_PR_PR13 0x00002000U /*!< Pending bit for line 13 */
+#define EXTI_PR_PR14 0x00004000U /*!< Pending bit for line 14 */
+#define EXTI_PR_PR15 0x00008000U /*!< Pending bit for line 15 */
+#define EXTI_PR_PR16 0x00010000U /*!< Pending bit for line 16 */
+#define EXTI_PR_PR17 0x00020000U /*!< Pending bit for line 17 */
+#define EXTI_PR_PR18 0x00040000U /*!< Pending bit for line 18 */
+#define EXTI_PR_PR19 0x00080000U /*!< Pending bit for line 19 */
+#define EXTI_PR_PR20 0x00100000U /*!< Pending bit for line 20 */
+#define EXTI_PR_PR21 0x00200000U /*!< Pending bit for line 21 */
+#define EXTI_PR_PR22 0x00400000U /*!< Pending bit for line 22 */
+
+/******************************************************************************/
+/* */
+/* FLASH */
+/* */
+/******************************************************************************/
+/******************* Bits definition for FLASH_ACR register *****************/
+#define FLASH_ACR_LATENCY 0x0000000FU
+#define FLASH_ACR_LATENCY_0WS 0x00000000U
+#define FLASH_ACR_LATENCY_1WS 0x00000001U
+#define FLASH_ACR_LATENCY_2WS 0x00000002U
+#define FLASH_ACR_LATENCY_3WS 0x00000003U
+#define FLASH_ACR_LATENCY_4WS 0x00000004U
+#define FLASH_ACR_LATENCY_5WS 0x00000005U
+#define FLASH_ACR_LATENCY_6WS 0x00000006U
+#define FLASH_ACR_LATENCY_7WS 0x00000007U
+
+#define FLASH_ACR_PRFTEN 0x00000100U
+#define FLASH_ACR_ICEN 0x00000200U
+#define FLASH_ACR_DCEN 0x00000400U
+#define FLASH_ACR_ICRST 0x00000800U
+#define FLASH_ACR_DCRST 0x00001000U
+#define FLASH_ACR_BYTE0_ADDRESS 0x40023C00U
+#define FLASH_ACR_BYTE2_ADDRESS 0x40023C03U
+
+/******************* Bits definition for FLASH_SR register ******************/
+#define FLASH_SR_EOP 0x00000001U
+#define FLASH_SR_SOP 0x00000002U
+#define FLASH_SR_WRPERR 0x00000010U
+#define FLASH_SR_PGAERR 0x00000020U
+#define FLASH_SR_PGPERR 0x00000040U
+#define FLASH_SR_PGSERR 0x00000080U
+#define FLASH_SR_BSY 0x00010000U
+
+/******************* Bits definition for FLASH_CR register ******************/
+#define FLASH_CR_PG 0x00000001U
+#define FLASH_CR_SER 0x00000002U
+#define FLASH_CR_MER 0x00000004U
+#define FLASH_CR_SNB 0x000000F8U
+#define FLASH_CR_SNB_0 0x00000008U
+#define FLASH_CR_SNB_1 0x00000010U
+#define FLASH_CR_SNB_2 0x00000020U
+#define FLASH_CR_SNB_3 0x00000040U
+#define FLASH_CR_SNB_4 0x00000080U
+#define FLASH_CR_PSIZE 0x00000300U
+#define FLASH_CR_PSIZE_0 0x00000100U
+#define FLASH_CR_PSIZE_1 0x00000200U
+#define FLASH_CR_STRT 0x00010000U
+#define FLASH_CR_EOPIE 0x01000000U
+#define FLASH_CR_LOCK 0x80000000U
+
+/******************* Bits definition for FLASH_OPTCR register ***************/
+#define FLASH_OPTCR_OPTLOCK 0x00000001U
+#define FLASH_OPTCR_OPTSTRT 0x00000002U
+#define FLASH_OPTCR_BOR_LEV_0 0x00000004U
+#define FLASH_OPTCR_BOR_LEV_1 0x00000008U
+#define FLASH_OPTCR_BOR_LEV 0x0000000CU
+
+#define FLASH_OPTCR_WDG_SW 0x00000020U
+#define FLASH_OPTCR_nRST_STOP 0x00000040U
+#define FLASH_OPTCR_nRST_STDBY 0x00000080U
+#define FLASH_OPTCR_RDP 0x0000FF00U
+#define FLASH_OPTCR_RDP_0 0x00000100U
+#define FLASH_OPTCR_RDP_1 0x00000200U
+#define FLASH_OPTCR_RDP_2 0x00000400U
+#define FLASH_OPTCR_RDP_3 0x00000800U
+#define FLASH_OPTCR_RDP_4 0x00001000U
+#define FLASH_OPTCR_RDP_5 0x00002000U
+#define FLASH_OPTCR_RDP_6 0x00004000U
+#define FLASH_OPTCR_RDP_7 0x00008000U
+#define FLASH_OPTCR_nWRP 0x0FFF0000U
+#define FLASH_OPTCR_nWRP_0 0x00010000U
+#define FLASH_OPTCR_nWRP_1 0x00020000U
+#define FLASH_OPTCR_nWRP_2 0x00040000U
+#define FLASH_OPTCR_nWRP_3 0x00080000U
+#define FLASH_OPTCR_nWRP_4 0x00100000U
+#define FLASH_OPTCR_nWRP_5 0x00200000U
+#define FLASH_OPTCR_nWRP_6 0x00400000U
+#define FLASH_OPTCR_nWRP_7 0x00800000U
+#define FLASH_OPTCR_nWRP_8 0x01000000U
+#define FLASH_OPTCR_nWRP_9 0x02000000U
+#define FLASH_OPTCR_nWRP_10 0x04000000U
+#define FLASH_OPTCR_nWRP_11 0x08000000U
+
+/****************** Bits definition for FLASH_OPTCR1 register ***************/
+#define FLASH_OPTCR1_nWRP 0x0FFF0000U
+#define FLASH_OPTCR1_nWRP_0 0x00010000U
+#define FLASH_OPTCR1_nWRP_1 0x00020000U
+#define FLASH_OPTCR1_nWRP_2 0x00040000U
+#define FLASH_OPTCR1_nWRP_3 0x00080000U
+#define FLASH_OPTCR1_nWRP_4 0x00100000U
+#define FLASH_OPTCR1_nWRP_5 0x00200000U
+#define FLASH_OPTCR1_nWRP_6 0x00400000U
+#define FLASH_OPTCR1_nWRP_7 0x00800000U
+#define FLASH_OPTCR1_nWRP_8 0x01000000U
+#define FLASH_OPTCR1_nWRP_9 0x02000000U
+#define FLASH_OPTCR1_nWRP_10 0x04000000U
+#define FLASH_OPTCR1_nWRP_11 0x08000000U
+
+/******************************************************************************/
+/* */
+/* General Purpose I/O */
+/* */
+/******************************************************************************/
+/****************** Bits definition for GPIO_MODER register *****************/
+#define GPIO_MODER_MODER0 0x00000003U
+#define GPIO_MODER_MODER0_0 0x00000001U
+#define GPIO_MODER_MODER0_1 0x00000002U
+
+#define GPIO_MODER_MODER1 0x0000000CU
+#define GPIO_MODER_MODER1_0 0x00000004U
+#define GPIO_MODER_MODER1_1 0x00000008U
+
+#define GPIO_MODER_MODER2 0x00000030U
+#define GPIO_MODER_MODER2_0 0x00000010U
+#define GPIO_MODER_MODER2_1 0x00000020U
+
+#define GPIO_MODER_MODER3 0x000000C0U
+#define GPIO_MODER_MODER3_0 0x00000040U
+#define GPIO_MODER_MODER3_1 0x00000080U
+
+#define GPIO_MODER_MODER4 0x00000300U
+#define GPIO_MODER_MODER4_0 0x00000100U
+#define GPIO_MODER_MODER4_1 0x00000200U
+
+#define GPIO_MODER_MODER5 0x00000C00U
+#define GPIO_MODER_MODER5_0 0x00000400U
+#define GPIO_MODER_MODER5_1 0x00000800U
+
+#define GPIO_MODER_MODER6 0x00003000U
+#define GPIO_MODER_MODER6_0 0x00001000U
+#define GPIO_MODER_MODER6_1 0x00002000U
+
+#define GPIO_MODER_MODER7 0x0000C000U
+#define GPIO_MODER_MODER7_0 0x00004000U
+#define GPIO_MODER_MODER7_1 0x00008000U
+
+#define GPIO_MODER_MODER8 0x00030000U
+#define GPIO_MODER_MODER8_0 0x00010000U
+#define GPIO_MODER_MODER8_1 0x00020000U
+
+#define GPIO_MODER_MODER9 0x000C0000U
+#define GPIO_MODER_MODER9_0 0x00040000U
+#define GPIO_MODER_MODER9_1 0x00080000U
+
+#define GPIO_MODER_MODER10 0x00300000U
+#define GPIO_MODER_MODER10_0 0x00100000U
+#define GPIO_MODER_MODER10_1 0x00200000U
+
+#define GPIO_MODER_MODER11 0x00C00000U
+#define GPIO_MODER_MODER11_0 0x00400000U
+#define GPIO_MODER_MODER11_1 0x00800000U
+
+#define GPIO_MODER_MODER12 0x03000000U
+#define GPIO_MODER_MODER12_0 0x01000000U
+#define GPIO_MODER_MODER12_1 0x02000000U
+
+#define GPIO_MODER_MODER13 0x0C000000U
+#define GPIO_MODER_MODER13_0 0x04000000U
+#define GPIO_MODER_MODER13_1 0x08000000U
+
+#define GPIO_MODER_MODER14 0x30000000U
+#define GPIO_MODER_MODER14_0 0x10000000U
+#define GPIO_MODER_MODER14_1 0x20000000U
+
+#define GPIO_MODER_MODER15 0xC0000000U
+#define GPIO_MODER_MODER15_0 0x40000000U
+#define GPIO_MODER_MODER15_1 0x80000000U
+
+/****************** Bits definition for GPIO_OTYPER register ****************/
+#define GPIO_OTYPER_OT_0 0x00000001U
+#define GPIO_OTYPER_OT_1 0x00000002U
+#define GPIO_OTYPER_OT_2 0x00000004U
+#define GPIO_OTYPER_OT_3 0x00000008U
+#define GPIO_OTYPER_OT_4 0x00000010U
+#define GPIO_OTYPER_OT_5 0x00000020U
+#define GPIO_OTYPER_OT_6 0x00000040U
+#define GPIO_OTYPER_OT_7 0x00000080U
+#define GPIO_OTYPER_OT_8 0x00000100U
+#define GPIO_OTYPER_OT_9 0x00000200U
+#define GPIO_OTYPER_OT_10 0x00000400U
+#define GPIO_OTYPER_OT_11 0x00000800U
+#define GPIO_OTYPER_OT_12 0x00001000U
+#define GPIO_OTYPER_OT_13 0x00002000U
+#define GPIO_OTYPER_OT_14 0x00004000U
+#define GPIO_OTYPER_OT_15 0x00008000U
+
+/****************** Bits definition for GPIO_OSPEEDR register ***************/
+#define GPIO_OSPEEDER_OSPEEDR0 0x00000003U
+#define GPIO_OSPEEDER_OSPEEDR0_0 0x00000001U
+#define GPIO_OSPEEDER_OSPEEDR0_1 0x00000002U
+
+#define GPIO_OSPEEDER_OSPEEDR1 0x0000000CU
+#define GPIO_OSPEEDER_OSPEEDR1_0 0x00000004U
+#define GPIO_OSPEEDER_OSPEEDR1_1 0x00000008U
+
+#define GPIO_OSPEEDER_OSPEEDR2 0x00000030U
+#define GPIO_OSPEEDER_OSPEEDR2_0 0x00000010U
+#define GPIO_OSPEEDER_OSPEEDR2_1 0x00000020U
+
+#define GPIO_OSPEEDER_OSPEEDR3 0x000000C0U
+#define GPIO_OSPEEDER_OSPEEDR3_0 0x00000040U
+#define GPIO_OSPEEDER_OSPEEDR3_1 0x00000080U
+
+#define GPIO_OSPEEDER_OSPEEDR4 0x00000300U
+#define GPIO_OSPEEDER_OSPEEDR4_0 0x00000100U
+#define GPIO_OSPEEDER_OSPEEDR4_1 0x00000200U
+
+#define GPIO_OSPEEDER_OSPEEDR5 0x00000C00U
+#define GPIO_OSPEEDER_OSPEEDR5_0 0x00000400U
+#define GPIO_OSPEEDER_OSPEEDR5_1 0x00000800U
+
+#define GPIO_OSPEEDER_OSPEEDR6 0x00003000U
+#define GPIO_OSPEEDER_OSPEEDR6_0 0x00001000U
+#define GPIO_OSPEEDER_OSPEEDR6_1 0x00002000U
+
+#define GPIO_OSPEEDER_OSPEEDR7 0x0000C000U
+#define GPIO_OSPEEDER_OSPEEDR7_0 0x00004000U
+#define GPIO_OSPEEDER_OSPEEDR7_1 0x00008000U
+
+#define GPIO_OSPEEDER_OSPEEDR8 0x00030000U
+#define GPIO_OSPEEDER_OSPEEDR8_0 0x00010000U
+#define GPIO_OSPEEDER_OSPEEDR8_1 0x00020000U
+
+#define GPIO_OSPEEDER_OSPEEDR9 0x000C0000U
+#define GPIO_OSPEEDER_OSPEEDR9_0 0x00040000U
+#define GPIO_OSPEEDER_OSPEEDR9_1 0x00080000U
+
+#define GPIO_OSPEEDER_OSPEEDR10 0x00300000U
+#define GPIO_OSPEEDER_OSPEEDR10_0 0x00100000U
+#define GPIO_OSPEEDER_OSPEEDR10_1 0x00200000U
+
+#define GPIO_OSPEEDER_OSPEEDR11 0x00C00000U
+#define GPIO_OSPEEDER_OSPEEDR11_0 0x00400000U
+#define GPIO_OSPEEDER_OSPEEDR11_1 0x00800000U
+
+#define GPIO_OSPEEDER_OSPEEDR12 0x03000000U
+#define GPIO_OSPEEDER_OSPEEDR12_0 0x01000000U
+#define GPIO_OSPEEDER_OSPEEDR12_1 0x02000000U
+
+#define GPIO_OSPEEDER_OSPEEDR13 0x0C000000U
+#define GPIO_OSPEEDER_OSPEEDR13_0 0x04000000U
+#define GPIO_OSPEEDER_OSPEEDR13_1 0x08000000U
+
+#define GPIO_OSPEEDER_OSPEEDR14 0x30000000U
+#define GPIO_OSPEEDER_OSPEEDR14_0 0x10000000U
+#define GPIO_OSPEEDER_OSPEEDR14_1 0x20000000U
+
+#define GPIO_OSPEEDER_OSPEEDR15 0xC0000000U
+#define GPIO_OSPEEDER_OSPEEDR15_0 0x40000000U
+#define GPIO_OSPEEDER_OSPEEDR15_1 0x80000000U
+
+/****************** Bits definition for GPIO_PUPDR register *****************/
+#define GPIO_PUPDR_PUPDR0 0x00000003U
+#define GPIO_PUPDR_PUPDR0_0 0x00000001U
+#define GPIO_PUPDR_PUPDR0_1 0x00000002U
+
+#define GPIO_PUPDR_PUPDR1 0x0000000CU
+#define GPIO_PUPDR_PUPDR1_0 0x00000004U
+#define GPIO_PUPDR_PUPDR1_1 0x00000008U
+
+#define GPIO_PUPDR_PUPDR2 0x00000030U
+#define GPIO_PUPDR_PUPDR2_0 0x00000010U
+#define GPIO_PUPDR_PUPDR2_1 0x00000020U
+
+#define GPIO_PUPDR_PUPDR3 0x000000C0U
+#define GPIO_PUPDR_PUPDR3_0 0x00000040U
+#define GPIO_PUPDR_PUPDR3_1 0x00000080U
+
+#define GPIO_PUPDR_PUPDR4 0x00000300U
+#define GPIO_PUPDR_PUPDR4_0 0x00000100U
+#define GPIO_PUPDR_PUPDR4_1 0x00000200U
+
+#define GPIO_PUPDR_PUPDR5 0x00000C00U
+#define GPIO_PUPDR_PUPDR5_0 0x00000400U
+#define GPIO_PUPDR_PUPDR5_1 0x00000800U
+
+#define GPIO_PUPDR_PUPDR6 0x00003000U
+#define GPIO_PUPDR_PUPDR6_0 0x00001000U
+#define GPIO_PUPDR_PUPDR6_1 0x00002000U
+
+#define GPIO_PUPDR_PUPDR7 0x0000C000U
+#define GPIO_PUPDR_PUPDR7_0 0x00004000U
+#define GPIO_PUPDR_PUPDR7_1 0x00008000U
+
+#define GPIO_PUPDR_PUPDR8 0x00030000U
+#define GPIO_PUPDR_PUPDR8_0 0x00010000U
+#define GPIO_PUPDR_PUPDR8_1 0x00020000U
+
+#define GPIO_PUPDR_PUPDR9 0x000C0000U
+#define GPIO_PUPDR_PUPDR9_0 0x00040000U
+#define GPIO_PUPDR_PUPDR9_1 0x00080000U
+
+#define GPIO_PUPDR_PUPDR10 0x00300000U
+#define GPIO_PUPDR_PUPDR10_0 0x00100000U
+#define GPIO_PUPDR_PUPDR10_1 0x00200000U
+
+#define GPIO_PUPDR_PUPDR11 0x00C00000U
+#define GPIO_PUPDR_PUPDR11_0 0x00400000U
+#define GPIO_PUPDR_PUPDR11_1 0x00800000U
+
+#define GPIO_PUPDR_PUPDR12 0x03000000U
+#define GPIO_PUPDR_PUPDR12_0 0x01000000U
+#define GPIO_PUPDR_PUPDR12_1 0x02000000U
+
+#define GPIO_PUPDR_PUPDR13 0x0C000000U
+#define GPIO_PUPDR_PUPDR13_0 0x04000000U
+#define GPIO_PUPDR_PUPDR13_1 0x08000000U
+
+#define GPIO_PUPDR_PUPDR14 0x30000000U
+#define GPIO_PUPDR_PUPDR14_0 0x10000000U
+#define GPIO_PUPDR_PUPDR14_1 0x20000000U
+
+#define GPIO_PUPDR_PUPDR15 0xC0000000U
+#define GPIO_PUPDR_PUPDR15_0 0x40000000U
+#define GPIO_PUPDR_PUPDR15_1 0x80000000U
+
+/****************** Bits definition for GPIO_IDR register *******************/
+#define GPIO_IDR_IDR_0 0x00000001U
+#define GPIO_IDR_IDR_1 0x00000002U
+#define GPIO_IDR_IDR_2 0x00000004U
+#define GPIO_IDR_IDR_3 0x00000008U
+#define GPIO_IDR_IDR_4 0x00000010U
+#define GPIO_IDR_IDR_5 0x00000020U
+#define GPIO_IDR_IDR_6 0x00000040U
+#define GPIO_IDR_IDR_7 0x00000080U
+#define GPIO_IDR_IDR_8 0x00000100U
+#define GPIO_IDR_IDR_9 0x00000200U
+#define GPIO_IDR_IDR_10 0x00000400U
+#define GPIO_IDR_IDR_11 0x00000800U
+#define GPIO_IDR_IDR_12 0x00001000U
+#define GPIO_IDR_IDR_13 0x00002000U
+#define GPIO_IDR_IDR_14 0x00004000U
+#define GPIO_IDR_IDR_15 0x00008000U
+
+/****************** Bits definition for GPIO_ODR register *******************/
+#define GPIO_ODR_ODR_0 0x00000001U
+#define GPIO_ODR_ODR_1 0x00000002U
+#define GPIO_ODR_ODR_2 0x00000004U
+#define GPIO_ODR_ODR_3 0x00000008U
+#define GPIO_ODR_ODR_4 0x00000010U
+#define GPIO_ODR_ODR_5 0x00000020U
+#define GPIO_ODR_ODR_6 0x00000040U
+#define GPIO_ODR_ODR_7 0x00000080U
+#define GPIO_ODR_ODR_8 0x00000100U
+#define GPIO_ODR_ODR_9 0x00000200U
+#define GPIO_ODR_ODR_10 0x00000400U
+#define GPIO_ODR_ODR_11 0x00000800U
+#define GPIO_ODR_ODR_12 0x00001000U
+#define GPIO_ODR_ODR_13 0x00002000U
+#define GPIO_ODR_ODR_14 0x00004000U
+#define GPIO_ODR_ODR_15 0x00008000U
+
+/****************** Bits definition for GPIO_BSRR register ******************/
+#define GPIO_BSRR_BS_0 0x00000001U
+#define GPIO_BSRR_BS_1 0x00000002U
+#define GPIO_BSRR_BS_2 0x00000004U
+#define GPIO_BSRR_BS_3 0x00000008U
+#define GPIO_BSRR_BS_4 0x00000010U
+#define GPIO_BSRR_BS_5 0x00000020U
+#define GPIO_BSRR_BS_6 0x00000040U
+#define GPIO_BSRR_BS_7 0x00000080U
+#define GPIO_BSRR_BS_8 0x00000100U
+#define GPIO_BSRR_BS_9 0x00000200U
+#define GPIO_BSRR_BS_10 0x00000400U
+#define GPIO_BSRR_BS_11 0x00000800U
+#define GPIO_BSRR_BS_12 0x00001000U
+#define GPIO_BSRR_BS_13 0x00002000U
+#define GPIO_BSRR_BS_14 0x00004000U
+#define GPIO_BSRR_BS_15 0x00008000U
+#define GPIO_BSRR_BR_0 0x00010000U
+#define GPIO_BSRR_BR_1 0x00020000U
+#define GPIO_BSRR_BR_2 0x00040000U
+#define GPIO_BSRR_BR_3 0x00080000U
+#define GPIO_BSRR_BR_4 0x00100000U
+#define GPIO_BSRR_BR_5 0x00200000U
+#define GPIO_BSRR_BR_6 0x00400000U
+#define GPIO_BSRR_BR_7 0x00800000U
+#define GPIO_BSRR_BR_8 0x01000000U
+#define GPIO_BSRR_BR_9 0x02000000U
+#define GPIO_BSRR_BR_10 0x04000000U
+#define GPIO_BSRR_BR_11 0x08000000U
+#define GPIO_BSRR_BR_12 0x10000000U
+#define GPIO_BSRR_BR_13 0x20000000U
+#define GPIO_BSRR_BR_14 0x40000000U
+#define GPIO_BSRR_BR_15 0x80000000U
+
+/****************** Bit definition for GPIO_LCKR register *********************/
+#define GPIO_LCKR_LCK0 0x00000001U
+#define GPIO_LCKR_LCK1 0x00000002U
+#define GPIO_LCKR_LCK2 0x00000004U
+#define GPIO_LCKR_LCK3 0x00000008U
+#define GPIO_LCKR_LCK4 0x00000010U
+#define GPIO_LCKR_LCK5 0x00000020U
+#define GPIO_LCKR_LCK6 0x00000040U
+#define GPIO_LCKR_LCK7 0x00000080U
+#define GPIO_LCKR_LCK8 0x00000100U
+#define GPIO_LCKR_LCK9 0x00000200U
+#define GPIO_LCKR_LCK10 0x00000400U
+#define GPIO_LCKR_LCK11 0x00000800U
+#define GPIO_LCKR_LCK12 0x00001000U
+#define GPIO_LCKR_LCK13 0x00002000U
+#define GPIO_LCKR_LCK14 0x00004000U
+#define GPIO_LCKR_LCK15 0x00008000U
+#define GPIO_LCKR_LCKK 0x00010000U
+
+/******************************************************************************/
+/* */
+/* Inter-integrated Circuit Interface */
+/* */
+/******************************************************************************/
+/******************* Bit definition for I2C_CR1 register ********************/
+#define I2C_CR1_PE 0x00000001U /*!<Peripheral Enable */
+#define I2C_CR1_SMBUS 0x00000002U /*!<SMBus Mode */
+#define I2C_CR1_SMBTYPE 0x00000008U /*!<SMBus Type */
+#define I2C_CR1_ENARP 0x00000010U /*!<ARP Enable */
+#define I2C_CR1_ENPEC 0x00000020U /*!<PEC Enable */
+#define I2C_CR1_ENGC 0x00000040U /*!<General Call Enable */
+#define I2C_CR1_NOSTRETCH 0x00000080U /*!<Clock Stretching Disable (Slave mode) */
+#define I2C_CR1_START 0x00000100U /*!<Start Generation */
+#define I2C_CR1_STOP 0x00000200U /*!<Stop Generation */
+#define I2C_CR1_ACK 0x00000400U /*!<Acknowledge Enable */
+#define I2C_CR1_POS 0x00000800U /*!<Acknowledge/PEC Position (for data reception) */
+#define I2C_CR1_PEC 0x00001000U /*!<Packet Error Checking */
+#define I2C_CR1_ALERT 0x00002000U /*!<SMBus Alert */
+#define I2C_CR1_SWRST 0x00008000U /*!<Software Reset */
+
+/******************* Bit definition for I2C_CR2 register ********************/
+#define I2C_CR2_FREQ 0x0000003FU /*!<FREQ[5:0] bits (Peripheral Clock Frequency) */
+#define I2C_CR2_FREQ_0 0x00000001U /*!<Bit 0 */
+#define I2C_CR2_FREQ_1 0x00000002U /*!<Bit 1 */
+#define I2C_CR2_FREQ_2 0x00000004U /*!<Bit 2 */
+#define I2C_CR2_FREQ_3 0x00000008U /*!<Bit 3 */
+#define I2C_CR2_FREQ_4 0x00000010U /*!<Bit 4 */
+#define I2C_CR2_FREQ_5 0x00000020U /*!<Bit 5 */
+
+#define I2C_CR2_ITERREN 0x00000100U /*!<Error Interrupt Enable */
+#define I2C_CR2_ITEVTEN 0x00000200U /*!<Event Interrupt Enable */
+#define I2C_CR2_ITBUFEN 0x00000400U /*!<Buffer Interrupt Enable */
+#define I2C_CR2_DMAEN 0x00000800U /*!<DMA Requests Enable */
+#define I2C_CR2_LAST 0x00001000U /*!<DMA Last Transfer */
+
+/******************* Bit definition for I2C_OAR1 register *******************/
+#define I2C_OAR1_ADD1_7 0x000000FEU /*!<Interface Address */
+#define I2C_OAR1_ADD8_9 0x00000300U /*!<Interface Address */
+
+#define I2C_OAR1_ADD0 0x00000001U /*!<Bit 0 */
+#define I2C_OAR1_ADD1 0x00000002U /*!<Bit 1 */
+#define I2C_OAR1_ADD2 0x00000004U /*!<Bit 2 */
+#define I2C_OAR1_ADD3 0x00000008U /*!<Bit 3 */
+#define I2C_OAR1_ADD4 0x00000010U /*!<Bit 4 */
+#define I2C_OAR1_ADD5 0x00000020U /*!<Bit 5 */
+#define I2C_OAR1_ADD6 0x00000040U /*!<Bit 6 */
+#define I2C_OAR1_ADD7 0x00000080U /*!<Bit 7 */
+#define I2C_OAR1_ADD8 0x00000100U /*!<Bit 8 */
+#define I2C_OAR1_ADD9 0x00000200U /*!<Bit 9 */
+
+#define I2C_OAR1_ADDMODE 0x00008000U /*!<Addressing Mode (Slave mode) */
+
+/******************* Bit definition for I2C_OAR2 register *******************/
+#define I2C_OAR2_ENDUAL 0x00000001U /*!<Dual addressing mode enable */
+#define I2C_OAR2_ADD2 0x000000FEU /*!<Interface address */
+
+/******************** Bit definition for I2C_DR register ********************/
+#define I2C_DR_DR 0x000000FFU /*!<8-bit Data Register */
+
+/******************* Bit definition for I2C_SR1 register ********************/
+#define I2C_SR1_SB 0x00000001U /*!<Start Bit (Master mode) */
+#define I2C_SR1_ADDR 0x00000002U /*!<Address sent (master mode)/matched (slave mode) */
+#define I2C_SR1_BTF 0x00000004U /*!<Byte Transfer Finished */
+#define I2C_SR1_ADD10 0x00000008U /*!<10-bit header sent (Master mode) */
+#define I2C_SR1_STOPF 0x00000010U /*!<Stop detection (Slave mode) */
+#define I2C_SR1_RXNE 0x00000040U /*!<Data Register not Empty (receivers) */
+#define I2C_SR1_TXE 0x00000080U /*!<Data Register Empty (transmitters) */
+#define I2C_SR1_BERR 0x00000100U /*!<Bus Error */
+#define I2C_SR1_ARLO 0x00000200U /*!<Arbitration Lost (master mode) */
+#define I2C_SR1_AF 0x00000400U /*!<Acknowledge Failure */
+#define I2C_SR1_OVR 0x00000800U /*!<Overrun/Underrun */
+#define I2C_SR1_PECERR 0x00001000U /*!<PEC Error in reception */
+#define I2C_SR1_TIMEOUT 0x00004000U /*!<Timeout or Tlow Error */
+#define I2C_SR1_SMBALERT 0x00008000U /*!<SMBus Alert */
+
+/******************* Bit definition for I2C_SR2 register ********************/
+#define I2C_SR2_MSL 0x00000001U /*!<Master/Slave */
+#define I2C_SR2_BUSY 0x00000002U /*!<Bus Busy */
+#define I2C_SR2_TRA 0x00000004U /*!<Transmitter/Receiver */
+#define I2C_SR2_GENCALL 0x00000010U /*!<General Call Address (Slave mode) */
+#define I2C_SR2_SMBDEFAULT 0x00000020U /*!<SMBus Device Default Address (Slave mode) */
+#define I2C_SR2_SMBHOST 0x00000040U /*!<SMBus Host Header (Slave mode) */
+#define I2C_SR2_DUALF 0x00000080U /*!<Dual Flag (Slave mode) */
+#define I2C_SR2_PEC 0x0000FF00U /*!<Packet Error Checking Register */
+
+/******************* Bit definition for I2C_CCR register ********************/
+#define I2C_CCR_CCR 0x00000FFFU /*!<Clock Control Register in Fast/Standard mode (Master mode) */
+#define I2C_CCR_DUTY 0x00004000U /*!<Fast Mode Duty Cycle */
+#define I2C_CCR_FS 0x00008000U /*!<I2C Master Mode Selection */
+
+/****************** Bit definition for I2C_TRISE register *******************/
+#define I2C_TRISE_TRISE 0x0000003FU /*!<Maximum Rise Time in Fast/Standard mode (Master mode) */
+
+/****************** Bit definition for I2C_FLTR register *******************/
+#define I2C_FLTR_DNF 0x0000000FU /*!<Digital Noise Filter */
+#define I2C_FLTR_ANOFF 0x00000010U /*!<Analog Noise Filter OFF */
+
+/******************************************************************************/
+/* */
+/* Fast Mode Plus Inter-integrated Circuit Interface (I2C) */
+/* */
+/******************************************************************************/
+/******************* Bit definition for I2C_CR1 register *******************/
+#define FMPI2C_CR1_PE 0x00000001U /*!< Peripheral enable */
+#define FMPI2C_CR1_TXIE 0x00000002U /*!< TX interrupt enable */
+#define FMPI2C_CR1_RXIE 0x00000004U /*!< RX interrupt enable */
+#define FMPI2C_CR1_ADDRIE 0x00000008U /*!< Address match interrupt enable */
+#define FMPI2C_CR1_NACKIE 0x00000010U /*!< NACK received interrupt enable */
+#define FMPI2C_CR1_STOPIE 0x00000020U /*!< STOP detection interrupt enable */
+#define FMPI2C_CR1_TCIE 0x00000040U /*!< Transfer complete interrupt enable */
+#define FMPI2C_CR1_ERRIE 0x00000080U /*!< Errors interrupt enable */
+#define FMPI2C_CR1_DFN 0x00000F00U /*!< Digital noise filter */
+#define FMPI2C_CR1_ANFOFF 0x00001000U /*!< Analog noise filter OFF */
+#define FMPI2C_CR1_TXDMAEN 0x00004000U /*!< DMA transmission requests enable */
+#define FMPI2C_CR1_RXDMAEN 0x00008000U /*!< DMA reception requests enable */
+#define FMPI2C_CR1_SBC 0x00010000U /*!< Slave byte control */
+#define FMPI2C_CR1_NOSTRETCH 0x00020000U /*!< Clock stretching disable */
+#define FMPI2C_CR1_GCEN 0x00080000U /*!< General call enable */
+#define FMPI2C_CR1_SMBHEN 0x00100000U /*!< SMBus host address enable */
+#define FMPI2C_CR1_SMBDEN 0x00200000U /*!< SMBus device default address enable */
+#define FMPI2C_CR1_ALERTEN 0x00400000U /*!< SMBus alert enable */
+#define FMPI2C_CR1_PECEN 0x00800000U /*!< PEC enable */
+
+/****************** Bit definition for I2C_CR2 register ********************/
+#define FMPI2C_CR2_SADD 0x000003FFU /*!< Slave address (master mode) */
+#define FMPI2C_CR2_RD_WRN 0x00000400U /*!< Transfer direction (master mode) */
+#define FMPI2C_CR2_ADD10 0x00000800U /*!< 10-bit addressing mode (master mode) */
+#define FMPI2C_CR2_HEAD10R 0x00001000U /*!< 10-bit address header only read direction (master mode) */
+#define FMPI2C_CR2_START 0x00002000U /*!< START generation */
+#define FMPI2C_CR2_STOP 0x00004000U /*!< STOP generation (master mode) */
+#define FMPI2C_CR2_NACK 0x00008000U /*!< NACK generation (slave mode) */
+#define FMPI2C_CR2_NBYTES 0x00FF0000U /*!< Number of bytes */
+#define FMPI2C_CR2_RELOAD 0x01000000U /*!< NBYTES reload mode */
+#define FMPI2C_CR2_AUTOEND 0x02000000U /*!< Automatic end mode (master mode) */
+#define FMPI2C_CR2_PECBYTE 0x04000000U /*!< Packet error checking byte */
+
+/******************* Bit definition for I2C_OAR1 register ******************/
+#define FMPI2C_OAR1_OA1 0x000003FFU /*!< Interface own address 1 */
+#define FMPI2C_OAR1_OA1MODE 0x00000400U /*!< Own address 1 10-bit mode */
+#define FMPI2C_OAR1_OA1EN 0x00008000U /*!< Own address 1 enable */
+
+/******************* Bit definition for I2C_OAR2 register ******************/
+#define FMPI2C_OAR2_OA2 0x000000FEU /*!< Interface own address 2 */
+#define FMPI2C_OAR2_OA2MSK 0x00000700U /*!< Own address 2 masks */
+#define FMPI2C_OAR2_OA2EN 0x00008000U /*!< Own address 2 enable */
+
+/******************* Bit definition for I2C_TIMINGR register *******************/
+#define FMPI2C_TIMINGR_SCLL 0x000000FFU /*!< SCL low period (master mode) */
+#define FMPI2C_TIMINGR_SCLH 0x0000FF00U /*!< SCL high period (master mode) */
+#define FMPI2C_TIMINGR_SDADEL 0x000F0000U /*!< Data hold time */
+#define FMPI2C_TIMINGR_SCLDEL 0x00F00000U /*!< Data setup time */
+#define FMPI2C_TIMINGR_PRESC 0xF0000000U /*!< Timings prescaler */
+
+/******************* Bit definition for I2C_TIMEOUTR register *******************/
+#define FMPI2C_TIMEOUTR_TIMEOUTA 0x00000FFFU /*!< Bus timeout A */
+#define FMPI2C_TIMEOUTR_TIDLE 0x00001000U /*!< Idle clock timeout detection */
+#define FMPI2C_TIMEOUTR_TIMOUTEN 0x00008000U /*!< Clock timeout enable */
+#define FMPI2C_TIMEOUTR_TIMEOUTB 0x0FFF0000U /*!< Bus timeout B */
+#define FMPI2C_TIMEOUTR_TEXTEN 0x80000000U /*!< Extended clock timeout enable */
+
+/****************** Bit definition for I2C_ISR register *********************/
+#define FMPI2C_ISR_TXE 0x00000001U /*!< Transmit data register empty */
+#define FMPI2C_ISR_TXIS 0x00000002U /*!< Transmit interrupt status */
+#define FMPI2C_ISR_RXNE 0x00000004U /*!< Receive data register not empty */
+#define FMPI2C_ISR_ADDR 0x00000008U /*!< Address matched (slave mode) */
+#define FMPI2C_ISR_NACKF 0x00000010U /*!< NACK received flag */
+#define FMPI2C_ISR_STOPF 0x00000020U /*!< STOP detection flag */
+#define FMPI2C_ISR_TC 0x00000040U /*!< Transfer complete (master mode) */
+#define FMPI2C_ISR_TCR 0x00000080U /*!< Transfer complete reload */
+#define FMPI2C_ISR_BERR 0x00000100U /*!< Bus error */
+#define FMPI2C_ISR_ARLO 0x00000200U /*!< Arbitration lost */
+#define FMPI2C_ISR_OVR 0x00000400U /*!< Overrun/Underrun */
+#define FMPI2C_ISR_PECERR 0x00000800U /*!< PEC error in reception */
+#define FMPI2C_ISR_TIMEOUT 0x00001000U /*!< Timeout or Tlow detection flag */
+#define FMPI2C_ISR_ALERT 0x00002000U /*!< SMBus alert */
+#define FMPI2C_ISR_BUSY 0x00008000U /*!< Bus busy */
+#define FMPI2C_ISR_DIR 0x00010000U /*!< Transfer direction (slave mode) */
+#define FMPI2C_ISR_ADDCODE 0x00FE0000U /*!< Address match code (slave mode) */
+
+/****************** Bit definition for I2C_ICR register *********************/
+#define FMPI2C_ICR_ADDRCF 0x00000008U /*!< Address matched clear flag */
+#define FMPI2C_ICR_NACKCF 0x00000010U /*!< NACK clear flag */
+#define FMPI2C_ICR_STOPCF 0x00000020U /*!< STOP detection clear flag */
+#define FMPI2C_ICR_BERRCF 0x00000100U /*!< Bus error clear flag */
+#define FMPI2C_ICR_ARLOCF 0x00000200U /*!< Arbitration lost clear flag */
+#define FMPI2C_ICR_OVRCF 0x00000400U /*!< Overrun/Underrun clear flag */
+#define FMPI2C_ICR_PECCF 0x00000800U /*!< PAC error clear flag */
+#define FMPI2C_ICR_TIMOUTCF 0x00001000U /*!< Timeout clear flag */
+#define FMPI2C_ICR_ALERTCF 0x00002000U /*!< Alert clear flag */
+
+/****************** Bit definition for I2C_PECR register *********************/
+#define FMPI2C_PECR_PEC 0x000000FFU /*!< PEC register */
+
+/****************** Bit definition for I2C_RXDR register *********************/
+#define FMPI2C_RXDR_RXDATA 0x000000FFU /*!< 8-bit receive data */
+
+/****************** Bit definition for I2C_TXDR register *********************/
+#define FMPI2C_TXDR_TXDATA 0x000000FFU /*!< 8-bit transmit data */
+
+/******************************************************************************/
+/* */
+/* Independent WATCHDOG */
+/* */
+/******************************************************************************/
+/******************* Bit definition for IWDG_KR register ********************/
+#define IWDG_KR_KEY 0xFFFFU /*!<Key value (write only, read 0000h) */
+
+/******************* Bit definition for IWDG_PR register ********************/
+#define IWDG_PR_PR 0x07U /*!<PR[2:0] (Prescaler divider) */
+#define IWDG_PR_PR_0 0x01U /*!<Bit 0 */
+#define IWDG_PR_PR_1 0x02U /*!<Bit 1 */
+#define IWDG_PR_PR_2 0x04U /*!<Bit 2 */
+
+/******************* Bit definition for IWDG_RLR register *******************/
+#define IWDG_RLR_RL 0x0FFFU /*!<Watchdog counter reload value */
+
+/******************* Bit definition for IWDG_SR register ********************/
+#define IWDG_SR_PVU 0x01U /*!<Watchdog prescaler value update */
+#define IWDG_SR_RVU 0x02U /*!<Watchdog counter reload value update */
+
+
+/******************************************************************************/
+/* */
+/* Power Control */
+/* */
+/******************************************************************************/
+/******************** Bit definition for PWR_CR register ********************/
+#define PWR_CR_LPDS 0x00000001U /*!< Low-Power Deepsleep */
+#define PWR_CR_PDDS 0x00000002U /*!< Power Down Deepsleep */
+#define PWR_CR_CWUF 0x00000004U /*!< Clear Wakeup Flag */
+#define PWR_CR_CSBF 0x00000008U /*!< Clear Standby Flag */
+#define PWR_CR_PVDE 0x00000010U /*!< Power Voltage Detector Enable */
+
+#define PWR_CR_PLS 0x000000E0U /*!< PLS[2:0] bits (PVD Level Selection) */
+#define PWR_CR_PLS_0 0x00000020U /*!< Bit 0 */
+#define PWR_CR_PLS_1 0x00000040U /*!< Bit 1 */
+#define PWR_CR_PLS_2 0x00000080U /*!< Bit 2 */
+
+/*!< PVD level configuration */
+#define PWR_CR_PLS_LEV0 0x00000000U /*!< PVD level 0 */
+#define PWR_CR_PLS_LEV1 0x00000020U /*!< PVD level 1 */
+#define PWR_CR_PLS_LEV2 0x00000040U /*!< PVD level 2 */
+#define PWR_CR_PLS_LEV3 0x00000060U /*!< PVD level 3 */
+#define PWR_CR_PLS_LEV4 0x00000080U /*!< PVD level 4 */
+#define PWR_CR_PLS_LEV5 0x000000A0U /*!< PVD level 5 */
+#define PWR_CR_PLS_LEV6 0x000000C0U /*!< PVD level 6 */
+#define PWR_CR_PLS_LEV7 0x000000E0U /*!< PVD level 7 */
+
+#define PWR_CR_DBP 0x00000100U /*!< Disable Backup Domain write protection */
+#define PWR_CR_FPDS 0x00000200U /*!< Flash power down in Stop mode */
+#define PWR_CR_LPLVDS 0x00000400U /*!< Low Power Regulator Low Voltage in Deep Sleep mode */
+#define PWR_CR_MRLVDS 0x00000800U /*!< Main Regulator Low Voltage in Deep Sleep mode */
+#define PWR_CR_ADCDC1 0x00002000U /*!< Refer to AN4073 on how to use this bit */
+
+#define PWR_CR_VOS 0x0000C000U /*!< VOS[1:0] bits (Regulator voltage scaling output selection) */
+#define PWR_CR_VOS_0 0x00004000U /*!< Bit 0 */
+#define PWR_CR_VOS_1 0x00008000U /*!< Bit 1 */
+
+#define PWR_CR_FMSSR 0x00100000U /*!< Flash Memory Sleep System Run */
+#define PWR_CR_FISSR 0x00200000U /*!< Flash Interface Stop while System Run */
+
+/******************* Bit definition for PWR_CSR register ********************/
+#define PWR_CSR_WUF 0x00000001U /*!< Wakeup Flag */
+#define PWR_CSR_SBF 0x00000002U /*!< Standby Flag */
+#define PWR_CSR_PVDO 0x00000004U /*!< PVD Output */
+#define PWR_CSR_BRR 0x00000008U /*!< Backup regulator ready */
+#define PWR_CSR_EWUP 0x00000100U /*!< Enable WKUP pin */
+#define PWR_CSR_BRE 0x00000200U /*!< Backup regulator enable */
+#define PWR_CSR_VOSRDY 0x00004000U /*!< Regulator voltage scaling output selection ready */
+
+/******************************************************************************/
+/* */
+/* Reset and Clock Control */
+/* */
+/******************************************************************************/
+/******************** Bit definition for RCC_CR register ********************/
+#define RCC_CR_HSION 0x00000001U
+#define RCC_CR_HSIRDY 0x00000002U
+
+#define RCC_CR_HSITRIM 0x000000F8U
+#define RCC_CR_HSITRIM_0 0x00000008U/*!<Bit 0 */
+#define RCC_CR_HSITRIM_1 0x00000010U/*!<Bit 1 */
+#define RCC_CR_HSITRIM_2 0x00000020U/*!<Bit 2 */
+#define RCC_CR_HSITRIM_3 0x00000040U/*!<Bit 3 */
+#define RCC_CR_HSITRIM_4 0x00000080U/*!<Bit 4 */
+
+#define RCC_CR_HSICAL 0x0000FF00U
+#define RCC_CR_HSICAL_0 0x00000100U/*!<Bit 0 */
+#define RCC_CR_HSICAL_1 0x00000200U/*!<Bit 1 */
+#define RCC_CR_HSICAL_2 0x00000400U/*!<Bit 2 */
+#define RCC_CR_HSICAL_3 0x00000800U/*!<Bit 3 */
+#define RCC_CR_HSICAL_4 0x00001000U/*!<Bit 4 */
+#define RCC_CR_HSICAL_5 0x00002000U/*!<Bit 5 */
+#define RCC_CR_HSICAL_6 0x00004000U/*!<Bit 6 */
+#define RCC_CR_HSICAL_7 0x00008000U/*!<Bit 7 */
+
+#define RCC_CR_HSEON 0x00010000U
+#define RCC_CR_HSERDY 0x00020000U
+#define RCC_CR_HSEBYP 0x00040000U
+#define RCC_CR_CSSON 0x00080000U
+#define RCC_CR_PLLON 0x01000000U
+#define RCC_CR_PLLRDY 0x02000000U
+#define RCC_CR_PLLI2SON 0x04000000U
+#define RCC_CR_PLLI2SRDY 0x08000000U
+
+/******************** Bit definition for RCC_PLLCFGR register ***************/
+#define RCC_PLLCFGR_PLLM 0x0000003FU
+#define RCC_PLLCFGR_PLLM_0 0x00000001U
+#define RCC_PLLCFGR_PLLM_1 0x00000002U
+#define RCC_PLLCFGR_PLLM_2 0x00000004U
+#define RCC_PLLCFGR_PLLM_3 0x00000008U
+#define RCC_PLLCFGR_PLLM_4 0x00000010U
+#define RCC_PLLCFGR_PLLM_5 0x00000020U
+
+#define RCC_PLLCFGR_PLLN 0x00007FC0U
+#define RCC_PLLCFGR_PLLN_0 0x00000040U
+#define RCC_PLLCFGR_PLLN_1 0x00000080U
+#define RCC_PLLCFGR_PLLN_2 0x00000100U
+#define RCC_PLLCFGR_PLLN_3 0x00000200U
+#define RCC_PLLCFGR_PLLN_4 0x00000400U
+#define RCC_PLLCFGR_PLLN_5 0x00000800U
+#define RCC_PLLCFGR_PLLN_6 0x00001000U
+#define RCC_PLLCFGR_PLLN_7 0x00002000U
+#define RCC_PLLCFGR_PLLN_8 0x00004000U
+
+#define RCC_PLLCFGR_PLLP 0x00030000U
+#define RCC_PLLCFGR_PLLP_0 0x00010000U
+#define RCC_PLLCFGR_PLLP_1 0x00020000U
+
+#define RCC_PLLCFGR_PLLSRC 0x00400000U
+#define RCC_PLLCFGR_PLLSRC_HSE 0x00400000U
+#define RCC_PLLCFGR_PLLSRC_HSI 0x00000000U
+
+#define RCC_PLLCFGR_PLLQ 0x0F000000U
+#define RCC_PLLCFGR_PLLQ_0 0x01000000U
+#define RCC_PLLCFGR_PLLQ_1 0x02000000U
+#define RCC_PLLCFGR_PLLQ_2 0x04000000U
+#define RCC_PLLCFGR_PLLQ_3 0x08000000U
+
+#define RCC_PLLCFGR_PLLR 0x70000000U
+#define RCC_PLLCFGR_PLLR_0 0x10000000U
+#define RCC_PLLCFGR_PLLR_1 0x20000000U
+#define RCC_PLLCFGR_PLLR_2 0x40000000U
+
+/******************** Bit definition for RCC_CFGR register ******************/
+/*!< SW configuration */
+#define RCC_CFGR_SW 0x00000003U /*!< SW[1:0] bits (System clock Switch) */
+#define RCC_CFGR_SW_0 0x00000001U /*!< Bit 0 */
+#define RCC_CFGR_SW_1 0x00000002U /*!< Bit 1 */
+
+#define RCC_CFGR_SW_HSI 0x00000000U /*!< HSI selected as system clock */
+#define RCC_CFGR_SW_HSE 0x00000001U /*!< HSE selected as system clock */
+#define RCC_CFGR_SW_PLL 0x00000002U /*!< PLL/PLLP selected as system clock */
+#define RCC_CFGR_SW_PLLR 0x00000003U /*!< PLL/PLLR selected as system clock */
+
+/*!< SWS configuration */
+#define RCC_CFGR_SWS 0x0000000CU /*!< SWS[1:0] bits (System Clock Switch Status) */
+#define RCC_CFGR_SWS_0 0x00000004U /*!< Bit 0 */
+#define RCC_CFGR_SWS_1 0x00000008U /*!< Bit 1 */
+
+#define RCC_CFGR_SWS_HSI 0x00000000U /*!< HSI oscillator used as system clock */
+#define RCC_CFGR_SWS_HSE 0x00000004U /*!< HSE oscillator used as system clock */
+#define RCC_CFGR_SWS_PLL 0x00000008U /*!< PLL/PLLP used as system clock */
+#define RCC_CFGR_SWS_PLLR 0x0000000CU /*!< PLL/PLLR used as system clock */
+
+/*!< HPRE configuration */
+#define RCC_CFGR_HPRE 0x000000F0U /*!< HPRE[3:0] bits (AHB prescaler) */
+#define RCC_CFGR_HPRE_0 0x00000010U /*!< Bit 0 */
+#define RCC_CFGR_HPRE_1 0x00000020U /*!< Bit 1 */
+#define RCC_CFGR_HPRE_2 0x00000040U /*!< Bit 2 */
+#define RCC_CFGR_HPRE_3 0x00000080U /*!< Bit 3 */
+
+#define RCC_CFGR_HPRE_DIV1 0x00000000U /*!< SYSCLK not divided */
+#define RCC_CFGR_HPRE_DIV2 0x00000080U /*!< SYSCLK divided by 2 */
+#define RCC_CFGR_HPRE_DIV4 0x00000090U /*!< SYSCLK divided by 4 */
+#define RCC_CFGR_HPRE_DIV8 0x000000A0U /*!< SYSCLK divided by 8 */
+#define RCC_CFGR_HPRE_DIV16 0x000000B0U /*!< SYSCLK divided by 16 */
+#define RCC_CFGR_HPRE_DIV64 0x000000C0U /*!< SYSCLK divided by 64 */
+#define RCC_CFGR_HPRE_DIV128 0x000000D0U /*!< SYSCLK divided by 128 */
+#define RCC_CFGR_HPRE_DIV256 0x000000E0U /*!< SYSCLK divided by 256 */
+#define RCC_CFGR_HPRE_DIV512 0x000000F0U /*!< SYSCLK divided by 512 */
+
+/*!< PPRE1 configuration */
+#define RCC_CFGR_PPRE1 0x00001C00U /*!< PRE1[2:0] bits (APB1 prescaler) */
+#define RCC_CFGR_PPRE1_0 0x00000400U /*!< Bit 0 */
+#define RCC_CFGR_PPRE1_1 0x00000800U /*!< Bit 1 */
+#define RCC_CFGR_PPRE1_2 0x00001000U /*!< Bit 2 */
+
+#define RCC_CFGR_PPRE1_DIV1 0x00000000U /*!< HCLK not divided */
+#define RCC_CFGR_PPRE1_DIV2 0x00001000U /*!< HCLK divided by 2 */
+#define RCC_CFGR_PPRE1_DIV4 0x00001400U /*!< HCLK divided by 4 */
+#define RCC_CFGR_PPRE1_DIV8 0x00001800U /*!< HCLK divided by 8 */
+#define RCC_CFGR_PPRE1_DIV16 0x00001C00U /*!< HCLK divided by 16 */
+
+/*!< PPRE2 configuration */
+#define RCC_CFGR_PPRE2 0x0000E000U /*!< PRE2[2:0] bits (APB2 prescaler) */
+#define RCC_CFGR_PPRE2_0 0x00002000U /*!< Bit 0 */
+#define RCC_CFGR_PPRE2_1 0x00004000U /*!< Bit 1 */
+#define RCC_CFGR_PPRE2_2 0x00008000U /*!< Bit 2 */
+
+#define RCC_CFGR_PPRE2_DIV1 0x00000000U /*!< HCLK not divided */
+#define RCC_CFGR_PPRE2_DIV2 0x00008000U /*!< HCLK divided by 2 */
+#define RCC_CFGR_PPRE2_DIV4 0x0000A000U /*!< HCLK divided by 4 */
+#define RCC_CFGR_PPRE2_DIV8 0x0000C000U /*!< HCLK divided by 8 */
+#define RCC_CFGR_PPRE2_DIV16 0x0000E000U /*!< HCLK divided by 16 */
+
+/*!< RTCPRE configuration */
+#define RCC_CFGR_RTCPRE 0x001F0000U
+#define RCC_CFGR_RTCPRE_0 0x00010000U
+#define RCC_CFGR_RTCPRE_1 0x00020000U
+#define RCC_CFGR_RTCPRE_2 0x00040000U
+#define RCC_CFGR_RTCPRE_3 0x00080000U
+#define RCC_CFGR_RTCPRE_4 0x00100000U
+
+/*!< MCO1 configuration */
+#define RCC_CFGR_MCO1 0x00600000U
+#define RCC_CFGR_MCO1_0 0x00200000U
+#define RCC_CFGR_MCO1_1 0x00400000U
+
+#define RCC_CFGR_MCO1PRE 0x07000000U
+#define RCC_CFGR_MCO1PRE_0 0x01000000U
+#define RCC_CFGR_MCO1PRE_1 0x02000000U
+#define RCC_CFGR_MCO1PRE_2 0x04000000U
+
+/******************** Bit definition for RCC_CIR register *******************/
+#define RCC_CIR_LSIRDYF 0x00000001U
+#define RCC_CIR_LSERDYF 0x00000002U
+#define RCC_CIR_HSIRDYF 0x00000004U
+#define RCC_CIR_HSERDYF 0x00000008U
+#define RCC_CIR_PLLRDYF 0x00000010U
+#define RCC_CIR_PLLI2SRDYF 0x00000020U
+
+#define RCC_CIR_CSSF 0x00000080U
+#define RCC_CIR_LSIRDYIE 0x00000100U
+#define RCC_CIR_LSERDYIE 0x00000200U
+#define RCC_CIR_HSIRDYIE 0x00000400U
+#define RCC_CIR_HSERDYIE 0x00000800U
+#define RCC_CIR_PLLRDYIE 0x00001000U
+#define RCC_CIR_PLLI2SRDYIE 0x00002000U
+
+#define RCC_CIR_LSIRDYC 0x00010000U
+#define RCC_CIR_LSERDYC 0x00020000U
+#define RCC_CIR_HSIRDYC 0x00040000U
+#define RCC_CIR_HSERDYC 0x00080000U
+#define RCC_CIR_PLLRDYC 0x00100000U
+#define RCC_CIR_PLLI2SRDYC 0x00200000U
+
+#define RCC_CIR_CSSC 0x00800000U
+
+/******************** Bit definition for RCC_AHB1RSTR register **************/
+#define RCC_AHB1RSTR_GPIOARST 0x00000001U
+#define RCC_AHB1RSTR_GPIOBRST 0x00000002U
+#define RCC_AHB1RSTR_GPIOCRST 0x00000004U
+#define RCC_AHB1RSTR_GPIODRST 0x00000008U
+#define RCC_AHB1RSTR_GPIOERST 0x00000010U
+#define RCC_AHB1RSTR_GPIOFRST 0x00000020U
+#define RCC_AHB1RSTR_GPIOGRST 0x00000040U
+#define RCC_AHB1RSTR_GPIOHRST 0x00000080U
+#define RCC_AHB1RSTR_CRCRST 0x00001000U
+#define RCC_AHB1RSTR_DMA1RST 0x00200000U
+#define RCC_AHB1RSTR_DMA2RST 0x00400000U
+
+/******************** Bit definition for RCC_AHB2RSTR register **************/
+#define RCC_AHB2RSTR_RNGRST 0x00000040U
+#define RCC_AHB2RSTR_OTGFSRST 0x00000080U
+
+/******************** Bit definition for RCC_APB1RSTR register **************/
+#define RCC_APB1RSTR_TIM2RST 0x00000001U
+#define RCC_APB1RSTR_TIM3RST 0x00000002U
+#define RCC_APB1RSTR_TIM4RST 0x00000004U
+#define RCC_APB1RSTR_TIM5RST 0x00000008U
+#define RCC_APB1RSTR_TIM6RST 0x00000010U
+#define RCC_APB1RSTR_TIM7RST 0x00000020U
+#define RCC_APB1RSTR_TIM12RST 0x00000040U
+#define RCC_APB1RSTR_TIM13RST 0x00000080U
+#define RCC_APB1RSTR_TIM14RST 0x00000100U
+#define RCC_APB1RSTR_WWDGRST 0x00000800U
+#define RCC_APB1RSTR_SPI2RST 0x00004000U
+#define RCC_APB1RSTR_SPI3RST 0x00008000U
+#define RCC_APB1RSTR_USART2RST 0x00020000U
+#define RCC_APB1RSTR_I2C1RST 0x00200000U
+#define RCC_APB1RSTR_I2C2RST 0x00400000U
+#define RCC_APB1RSTR_I2C3RST 0x00800000U
+#define RCC_APB1RSTR_FMPI2C1RST 0x01000000U
+#define RCC_APB1RSTR_CAN1RST 0x02000000U
+#define RCC_APB1RSTR_CAN2RST 0x04000000U
+#define RCC_APB1RSTR_PWRRST 0x10000000U
+
+/******************** Bit definition for RCC_APB2RSTR register **************/
+#define RCC_APB2RSTR_TIM1RST 0x00000001U
+#define RCC_APB2RSTR_TIM8RST 0x00000002U
+#define RCC_APB2RSTR_USART1RST 0x00000010U
+#define RCC_APB2RSTR_USART6RST 0x00000020U
+#define RCC_APB2RSTR_ADCRST 0x00000100U
+#define RCC_APB2RSTR_SDIORST 0x00000800U
+#define RCC_APB2RSTR_SPI1RST 0x00001000U
+#define RCC_APB2RSTR_SPI4RST 0x00002000U
+#define RCC_APB2RSTR_SYSCFGRST 0x00004000U
+#define RCC_APB2RSTR_TIM9RST 0x00010000U
+#define RCC_APB2RSTR_TIM10RST 0x00020000U
+#define RCC_APB2RSTR_TIM11RST 0x00040000U
+#define RCC_APB2RSTR_SPI5RST 0x00100000U
+#define RCC_APB2RSTR_DFSDM1RST 0x01000000U
+
+/******************** Bit definition for RCC_AHB1ENR register ***************/
+#define RCC_AHB1ENR_GPIOAEN 0x00000001U
+#define RCC_AHB1ENR_GPIOBEN 0x00000002U
+#define RCC_AHB1ENR_GPIOCEN 0x00000004U
+#define RCC_AHB1ENR_GPIODEN 0x00000008U
+#define RCC_AHB1ENR_GPIOEEN 0x00000010U
+#define RCC_AHB1ENR_GPIOFEN 0x00000020U
+#define RCC_AHB1ENR_GPIOGEN 0x00000040U
+#define RCC_AHB1ENR_GPIOHEN 0x00000080U
+#define RCC_AHB1ENR_CRCEN 0x00001000U
+#define RCC_AHB1ENR_DMA1EN 0x00200000U
+#define RCC_AHB1ENR_DMA2EN 0x00400000U
+
+/******************** Bit definition for RCC_AHB2ENR register ***************/
+#define RCC_AHB2ENR_RNGEN 0x00000040U
+#define RCC_AHB2ENR_OTGFSEN 0x00000080U
+
+/******************** Bit definition for RCC_APB1ENR register ***************/
+#define RCC_APB1ENR_TIM2EN 0x00000001U
+#define RCC_APB1ENR_TIM3EN 0x00000002U
+#define RCC_APB1ENR_TIM4EN 0x00000004U
+#define RCC_APB1ENR_TIM5EN 0x00000008U
+#define RCC_APB1ENR_TIM6EN 0x00000010U
+#define RCC_APB1ENR_TIM7EN 0x00000020U
+#define RCC_APB1ENR_TIM12EN 0x00000040U
+#define RCC_APB1ENR_TIM13EN 0x00000080U
+#define RCC_APB1ENR_TIM14EN 0x00000100U
+#define RCC_APB1ENR_RTCAPBEN 0x00000400U
+#define RCC_APB1ENR_WWDGEN 0x00000800U
+#define RCC_APB1ENR_SPI2EN 0x00004000U
+#define RCC_APB1ENR_SPI3EN 0x00008000U
+#define RCC_APB1ENR_USART2EN 0x00020000U
+#define RCC_APB1ENR_I2C1EN 0x00200000U
+#define RCC_APB1ENR_I2C2EN 0x00400000U
+#define RCC_APB1ENR_I2C3EN 0x00800000U
+#define RCC_APB1ENR_FMPI2C1EN 0x01000000U
+#define RCC_APB1ENR_CAN1EN 0x02000000U
+#define RCC_APB1ENR_CAN2EN 0x04000000U
+#define RCC_APB1ENR_PWREN 0x10000000U
+
+/******************** Bit definition for RCC_APB2ENR register ***************/
+#define RCC_APB2ENR_TIM1EN 0x00000001U
+#define RCC_APB2ENR_TIM8EN 0x00000002U
+#define RCC_APB2ENR_USART1EN 0x00000010U
+#define RCC_APB2ENR_USART6EN 0x00000020U
+#define RCC_APB2ENR_ADC1EN 0x00000100U
+#define RCC_APB2ENR_SDIOEN 0x00000800U
+#define RCC_APB2ENR_SPI1EN 0x00001000U
+#define RCC_APB2ENR_SPI4EN 0x00002000U
+#define RCC_APB2ENR_SYSCFGEN 0x00004000U
+#define RCC_APB2ENR_EXTITEN 0x00008000U
+#define RCC_APB2ENR_TIM9EN 0x00010000U
+#define RCC_APB2ENR_TIM10EN 0x00020000U
+#define RCC_APB2ENR_TIM11EN 0x00040000U
+#define RCC_APB2ENR_SPI5EN 0x00100000U
+#define RCC_APB2ENR_DFSDM1EN 0x01000000U
+/******************** Bit definition for RCC_AHB1LPENR register *************/
+#define RCC_AHB1LPENR_GPIOALPEN 0x00000001U
+#define RCC_AHB1LPENR_GPIOBLPEN 0x00000002U
+#define RCC_AHB1LPENR_GPIOCLPEN 0x00000004U
+#define RCC_AHB1LPENR_GPIODLPEN 0x00000008U
+#define RCC_AHB1LPENR_GPIOELPEN 0x00000010U
+#define RCC_AHB1LPENR_GPIOFLPEN 0x00000020U
+#define RCC_AHB1LPENR_GPIOGLPEN 0x00000040U
+#define RCC_AHB1LPENR_GPIOHLPEN 0x00000080U
+#define RCC_AHB1LPENR_CRCLPEN 0x00001000U
+#define RCC_AHB1LPENR_FLITFLPEN 0x00008000U
+#define RCC_AHB1LPENR_SRAM1LPEN 0x00010000U
+#define RCC_AHB1LPENR_DMA1LPEN 0x00200000U
+#define RCC_AHB1LPENR_DMA2LPEN 0x00400000U
+
+/******************** Bit definition for RCC_AHB2LPENR register *************/
+#define RCC_AHB2LPENR_RNGLPEN 0x00000040U
+#define RCC_AHB2LPENR_OTGFSLPEN 0x00000080U
+
+/******************** Bit definition for RCC_APB1LPENR register *************/
+#define RCC_APB1LPENR_TIM2LPEN 0x00000001U
+#define RCC_APB1LPENR_TIM3LPEN 0x00000002U
+#define RCC_APB1LPENR_TIM4LPEN 0x00000004U
+#define RCC_APB1LPENR_TIM5LPEN 0x00000008U
+#define RCC_APB1LPENR_TIM6LPEN 0x00000010U
+#define RCC_APB1LPENR_TIM7LPEN 0x00000020U
+#define RCC_APB1LPENR_TIM12LPEN 0x00000040U
+#define RCC_APB1LPENR_TIM13LPEN 0x00000080U
+#define RCC_APB1LPENR_TIM14LPEN 0x00000100U
+#define RCC_APB1LPENR_RTCAPBLPEN 0x00000400U
+#define RCC_APB1LPENR_WWDGLPEN 0x00000800U
+#define RCC_APB1LPENR_SPI2LPEN 0x00004000U
+#define RCC_APB1LPENR_SPI3LPEN 0x00008000U
+#define RCC_APB1LPENR_USART2LPEN 0x00020000U
+#define RCC_APB1LPENR_I2C1LPEN 0x00200000U
+#define RCC_APB1LPENR_I2C2LPEN 0x00400000U
+#define RCC_APB1LPENR_I2C3LPEN 0x00800000U
+#define RCC_APB1LPENR_FMPI2C1LPEN 0x01000000U
+#define RCC_APB1LPENR_CAN1LPEN 0x02000000U
+#define RCC_APB1LPENR_CAN2LPEN 0x04000000U
+#define RCC_APB1LPENR_PWRLPEN 0x10000000U
+
+/******************** Bit definition for RCC_APB2LPENR register *************/
+#define RCC_APB2LPENR_TIM1LPEN 0x00000001U
+#define RCC_APB2LPENR_TIM8LPEN 0x00000002U
+#define RCC_APB2LPENR_USART1LPEN 0x00000010U
+#define RCC_APB2LPENR_USART6LPEN 0x00000020U
+#define RCC_APB2LPENR_ADC1LPEN 0x00000100U
+#define RCC_APB2LPENR_SDIOLPEN 0x00000800U
+#define RCC_APB2LPENR_SPI1LPEN 0x00001000U
+#define RCC_APB2LPENR_SPI4LPEN 0x00002000U
+#define RCC_APB2LPENR_SYSCFGLPEN 0x00004000U
+#define RCC_APB2LPENR_EXTITLPEN 0x00008000U
+#define RCC_APB2LPENR_TIM9LPEN 0x00010000U
+#define RCC_APB2LPENR_TIM10LPEN 0x00020000U
+#define RCC_APB2LPENR_TIM11LPEN 0x00040000U
+#define RCC_APB2LPENR_SPI5LPEN 0x00100000U
+#define RCC_APB2LPENR_DFSDM1LPEN 0x01000000U
+
+/******************** Bit definition for RCC_BDCR register ******************/
+#define RCC_BDCR_LSEON 0x00000001U
+#define RCC_BDCR_LSERDY 0x00000002U
+#define RCC_BDCR_LSEBYP 0x00000004U
+#define RCC_BDCR_LSEMOD 0x00000008U
+
+#define RCC_BDCR_RTCSEL 0x00000300U
+#define RCC_BDCR_RTCSEL_0 0x00000100U
+#define RCC_BDCR_RTCSEL_1 0x00000200U
+
+#define RCC_BDCR_RTCEN 0x00008000U
+#define RCC_BDCR_BDRST 0x00010000U
+
+/******************** Bit definition for RCC_CSR register *******************/
+#define RCC_CSR_LSION 0x00000001U
+#define RCC_CSR_LSIRDY 0x00000002U
+#define RCC_CSR_RMVF 0x01000000U
+#define RCC_CSR_PADRSTF 0x04000000U
+#define RCC_CSR_PORRSTF 0x08000000U
+#define RCC_CSR_SFTRSTF 0x10000000U
+#define RCC_CSR_WDGRSTF 0x20000000U
+#define RCC_CSR_WWDGRSTF 0x40000000U
+#define RCC_CSR_LPWRRSTF 0x80000000U
+
+/******************** Bit definition for RCC_SSCGR register *****************/
+#define RCC_SSCGR_MODPER 0x00001FFFU
+#define RCC_SSCGR_INCSTEP 0x0FFFE000U
+#define RCC_SSCGR_SPREADSEL 0x40000000U
+#define RCC_SSCGR_SSCGEN 0x80000000U
+
+/******************** Bit definition for RCC_PLLI2SCFGR register ************/
+#define RCC_PLLI2SCFGR_PLLI2SM 0x0000003FU
+#define RCC_PLLI2SCFGR_PLLI2SM_0 0x00000001U
+#define RCC_PLLI2SCFGR_PLLI2SM_1 0x00000002U
+#define RCC_PLLI2SCFGR_PLLI2SM_2 0x00000004U
+#define RCC_PLLI2SCFGR_PLLI2SM_3 0x00000008U
+#define RCC_PLLI2SCFGR_PLLI2SM_4 0x00000010U
+#define RCC_PLLI2SCFGR_PLLI2SM_5 0x00000020U
+
+#define RCC_PLLI2SCFGR_PLLI2SN 0x00007FC0U
+#define RCC_PLLI2SCFGR_PLLI2SN_0 0x00000040U
+#define RCC_PLLI2SCFGR_PLLI2SN_1 0x00000080U
+#define RCC_PLLI2SCFGR_PLLI2SN_2 0x00000100U
+#define RCC_PLLI2SCFGR_PLLI2SN_3 0x00000200U
+#define RCC_PLLI2SCFGR_PLLI2SN_4 0x00000400U
+#define RCC_PLLI2SCFGR_PLLI2SN_5 0x00000800U
+#define RCC_PLLI2SCFGR_PLLI2SN_6 0x00001000U
+#define RCC_PLLI2SCFGR_PLLI2SN_7 0x00002000U
+#define RCC_PLLI2SCFGR_PLLI2SN_8 0x00004000U
+
+#define RCC_PLLI2SCFGR_PLLI2SSRC 0x00400000U
+
+#define RCC_PLLI2SCFGR_PLLI2SQ 0x0F000000U
+#define RCC_PLLI2SCFGR_PLLI2SQ_0 0x01000000U
+#define RCC_PLLI2SCFGR_PLLI2SQ_1 0x02000000U
+#define RCC_PLLI2SCFGR_PLLI2SQ_2 0x04000000U
+#define RCC_PLLI2SCFGR_PLLI2SQ_3 0x08000000U
+
+#define RCC_PLLI2SCFGR_PLLI2SR 0x70000000U
+#define RCC_PLLI2SCFGR_PLLI2SR_0 0x10000000U
+#define RCC_PLLI2SCFGR_PLLI2SR_1 0x20000000U
+#define RCC_PLLI2SCFGR_PLLI2SR_2 0x40000000U
+
+/******************** Bit definition for RCC_DCKCFGR register ****************/
+#define RCC_DCKCFGR_CKDFSDM1ASEL 0x00008000U
+#define RCC_DCKCFGR_TIMPRE 0x01000000U
+
+#define RCC_DCKCFGR_I2S1SRC 0x06000000U
+#define RCC_DCKCFGR_I2S1SRC_0 0x02000000U
+#define RCC_DCKCFGR_I2S1SRC_1 0x04000000U
+
+#define RCC_DCKCFGR_I2S2SRC 0x18000000U
+#define RCC_DCKCFGR_I2S2SRC_0 0x08000000U
+#define RCC_DCKCFGR_I2S2SRC_1 0x10000000U
+
+#define RCC_DCKCFGR_CKDFSDM1SEL 0x80000000U
+
+/******************** Bit definition for RCC_CKGATENR register ***************/
+#define RCC_CKGATENR_AHB2APB1_CKEN 0x00000001U
+#define RCC_CKGATENR_AHB2APB2_CKEN 0x00000002U
+#define RCC_CKGATENR_CM4DBG_CKEN 0x00000004U
+#define RCC_CKGATENR_SPARE_CKEN 0x00000008U
+#define RCC_CKGATENR_SRAM_CKEN 0x00000010U
+#define RCC_CKGATENR_FLITF_CKEN 0x00000020U
+#define RCC_CKGATENR_RCC_CKEN 0x00000040U
+#define RCC_CKGATENR_RCC_EVTCTL 0x00000080U
+
+/******************** Bit definition for RCC_DCKCFGR2 register ***************/
+#define RCC_DCKCFGR2_FMPI2C1SEL 0x00C00000U
+#define RCC_DCKCFGR2_FMPI2C1SEL_0 0x00400000U
+#define RCC_DCKCFGR2_FMPI2C1SEL_1 0x00800000U
+
+#define RCC_DCKCFGR2_CK48MSEL 0x08000000U
+#define RCC_DCKCFGR2_SDIOSEL 0x10000000U
+
+/******************************************************************************/
+/* */
+/* RNG */
+/* */
+/******************************************************************************/
+/******************** Bits definition for RNG_CR register *******************/
+#define RNG_CR_RNGEN 0x00000004U
+#define RNG_CR_IE 0x00000008U
+
+/******************** Bits definition for RNG_SR register *******************/
+#define RNG_SR_DRDY 0x00000001U
+#define RNG_SR_CECS 0x00000002U
+#define RNG_SR_SECS 0x00000004U
+#define RNG_SR_CEIS 0x00000020U
+#define RNG_SR_SEIS 0x00000040U
+
+/******************************************************************************/
+/* */
+/* Real-Time Clock (RTC) */
+/* */
+/******************************************************************************/
+/******************** Bits definition for RTC_TR register *******************/
+#define RTC_TR_PM 0x00400000U
+#define RTC_TR_HT 0x00300000U
+#define RTC_TR_HT_0 0x00100000U
+#define RTC_TR_HT_1 0x00200000U
+#define RTC_TR_HU 0x000F0000U
+#define RTC_TR_HU_0 0x00010000U
+#define RTC_TR_HU_1 0x00020000U
+#define RTC_TR_HU_2 0x00040000U
+#define RTC_TR_HU_3 0x00080000U
+#define RTC_TR_MNT 0x00007000U
+#define RTC_TR_MNT_0 0x00001000U
+#define RTC_TR_MNT_1 0x00002000U
+#define RTC_TR_MNT_2 0x00004000U
+#define RTC_TR_MNU 0x00000F00U
+#define RTC_TR_MNU_0 0x00000100U
+#define RTC_TR_MNU_1 0x00000200U
+#define RTC_TR_MNU_2 0x00000400U
+#define RTC_TR_MNU_3 0x00000800U
+#define RTC_TR_ST 0x00000070U
+#define RTC_TR_ST_0 0x00000010U
+#define RTC_TR_ST_1 0x00000020U
+#define RTC_TR_ST_2 0x00000040U
+#define RTC_TR_SU 0x0000000FU
+#define RTC_TR_SU_0 0x00000001U
+#define RTC_TR_SU_1 0x00000002U
+#define RTC_TR_SU_2 0x00000004U
+#define RTC_TR_SU_3 0x00000008U
+
+/******************** Bits definition for RTC_DR register *******************/
+#define RTC_DR_YT 0x00F00000U
+#define RTC_DR_YT_0 0x00100000U
+#define RTC_DR_YT_1 0x00200000U
+#define RTC_DR_YT_2 0x00400000U
+#define RTC_DR_YT_3 0x00800000U
+#define RTC_DR_YU 0x000F0000U
+#define RTC_DR_YU_0 0x00010000U
+#define RTC_DR_YU_1 0x00020000U
+#define RTC_DR_YU_2 0x00040000U
+#define RTC_DR_YU_3 0x00080000U
+#define RTC_DR_WDU 0x0000E000U
+#define RTC_DR_WDU_0 0x00002000U
+#define RTC_DR_WDU_1 0x00004000U
+#define RTC_DR_WDU_2 0x00008000U
+#define RTC_DR_MT 0x00001000U
+#define RTC_DR_MU 0x00000F00U
+#define RTC_DR_MU_0 0x00000100U
+#define RTC_DR_MU_1 0x00000200U
+#define RTC_DR_MU_2 0x00000400U
+#define RTC_DR_MU_3 0x00000800U
+#define RTC_DR_DT 0x00000030U
+#define RTC_DR_DT_0 0x00000010U
+#define RTC_DR_DT_1 0x00000020U
+#define RTC_DR_DU 0x0000000FU
+#define RTC_DR_DU_0 0x00000001U
+#define RTC_DR_DU_1 0x00000002U
+#define RTC_DR_DU_2 0x00000004U
+#define RTC_DR_DU_3 0x00000008U
+
+/******************** Bits definition for RTC_CR register *******************/
+#define RTC_CR_COE 0x00800000U
+#define RTC_CR_OSEL 0x00600000U
+#define RTC_CR_OSEL_0 0x00200000U
+#define RTC_CR_OSEL_1 0x00400000U
+#define RTC_CR_POL 0x00100000U
+#define RTC_CR_COSEL 0x00080000U
+#define RTC_CR_BCK 0x00040000U
+#define RTC_CR_SUB1H 0x00020000U
+#define RTC_CR_ADD1H 0x00010000U
+#define RTC_CR_TSIE 0x00008000U
+#define RTC_CR_WUTIE 0x00004000U
+#define RTC_CR_ALRBIE 0x00002000U
+#define RTC_CR_ALRAIE 0x00001000U
+#define RTC_CR_TSE 0x00000800U
+#define RTC_CR_WUTE 0x00000400U
+#define RTC_CR_ALRBE 0x00000200U
+#define RTC_CR_ALRAE 0x00000100U
+#define RTC_CR_DCE 0x00000080U
+#define RTC_CR_FMT 0x00000040U
+#define RTC_CR_BYPSHAD 0x00000020U
+#define RTC_CR_REFCKON 0x00000010U
+#define RTC_CR_TSEDGE 0x00000008U
+#define RTC_CR_WUCKSEL 0x00000007U
+#define RTC_CR_WUCKSEL_0 0x00000001U
+#define RTC_CR_WUCKSEL_1 0x00000002U
+#define RTC_CR_WUCKSEL_2 0x00000004U
+
+/******************** Bits definition for RTC_ISR register ******************/
+#define RTC_ISR_RECALPF 0x00010000U
+#define RTC_ISR_TAMP1F 0x00002000U
+#define RTC_ISR_TAMP2F 0x00004000U
+#define RTC_ISR_TSOVF 0x00001000U
+#define RTC_ISR_TSF 0x00000800U
+#define RTC_ISR_WUTF 0x00000400U
+#define RTC_ISR_ALRBF 0x00000200U
+#define RTC_ISR_ALRAF 0x00000100U
+#define RTC_ISR_INIT 0x00000080U
+#define RTC_ISR_INITF 0x00000040U
+#define RTC_ISR_RSF 0x00000020U
+#define RTC_ISR_INITS 0x00000010U
+#define RTC_ISR_SHPF 0x00000008U
+#define RTC_ISR_WUTWF 0x00000004U
+#define RTC_ISR_ALRBWF 0x00000002U
+#define RTC_ISR_ALRAWF 0x00000001U
+
+/******************** Bits definition for RTC_PRER register *****************/
+#define RTC_PRER_PREDIV_A 0x007F0000U
+#define RTC_PRER_PREDIV_S 0x00007FFFU
+
+/******************** Bits definition for RTC_WUTR register *****************/
+#define RTC_WUTR_WUT 0x0000FFFFU
+
+/******************** Bits definition for RTC_CALIBR register ***************/
+#define RTC_CALIBR_DCS 0x00000080U
+#define RTC_CALIBR_DC 0x0000001FU
+
+/******************** Bits definition for RTC_ALRMAR register ***************/
+#define RTC_ALRMAR_MSK4 0x80000000U
+#define RTC_ALRMAR_WDSEL 0x40000000U
+#define RTC_ALRMAR_DT 0x30000000U
+#define RTC_ALRMAR_DT_0 0x10000000U
+#define RTC_ALRMAR_DT_1 0x20000000U
+#define RTC_ALRMAR_DU 0x0F000000U
+#define RTC_ALRMAR_DU_0 0x01000000U
+#define RTC_ALRMAR_DU_1 0x02000000U
+#define RTC_ALRMAR_DU_2 0x04000000U
+#define RTC_ALRMAR_DU_3 0x08000000U
+#define RTC_ALRMAR_MSK3 0x00800000U
+#define RTC_ALRMAR_PM 0x00400000U
+#define RTC_ALRMAR_HT 0x00300000U
+#define RTC_ALRMAR_HT_0 0x00100000U
+#define RTC_ALRMAR_HT_1 0x00200000U
+#define RTC_ALRMAR_HU 0x000F0000U
+#define RTC_ALRMAR_HU_0 0x00010000U
+#define RTC_ALRMAR_HU_1 0x00020000U
+#define RTC_ALRMAR_HU_2 0x00040000U
+#define RTC_ALRMAR_HU_3 0x00080000U
+#define RTC_ALRMAR_MSK2 0x00008000U
+#define RTC_ALRMAR_MNT 0x00007000U
+#define RTC_ALRMAR_MNT_0 0x00001000U
+#define RTC_ALRMAR_MNT_1 0x00002000U
+#define RTC_ALRMAR_MNT_2 0x00004000U
+#define RTC_ALRMAR_MNU 0x00000F00U
+#define RTC_ALRMAR_MNU_0 0x00000100U
+#define RTC_ALRMAR_MNU_1 0x00000200U
+#define RTC_ALRMAR_MNU_2 0x00000400U
+#define RTC_ALRMAR_MNU_3 0x00000800U
+#define RTC_ALRMAR_MSK1 0x00000080U
+#define RTC_ALRMAR_ST 0x00000070U
+#define RTC_ALRMAR_ST_0 0x00000010U
+#define RTC_ALRMAR_ST_1 0x00000020U
+#define RTC_ALRMAR_ST_2 0x00000040U
+#define RTC_ALRMAR_SU 0x0000000FU
+#define RTC_ALRMAR_SU_0 0x00000001U
+#define RTC_ALRMAR_SU_1 0x00000002U
+#define RTC_ALRMAR_SU_2 0x00000004U
+#define RTC_ALRMAR_SU_3 0x00000008U
+
+/******************** Bits definition for RTC_ALRMBR register ***************/
+#define RTC_ALRMBR_MSK4 0x80000000U
+#define RTC_ALRMBR_WDSEL 0x40000000U
+#define RTC_ALRMBR_DT 0x30000000U
+#define RTC_ALRMBR_DT_0 0x10000000U
+#define RTC_ALRMBR_DT_1 0x20000000U
+#define RTC_ALRMBR_DU 0x0F000000U
+#define RTC_ALRMBR_DU_0 0x01000000U
+#define RTC_ALRMBR_DU_1 0x02000000U
+#define RTC_ALRMBR_DU_2 0x04000000U
+#define RTC_ALRMBR_DU_3 0x08000000U
+#define RTC_ALRMBR_MSK3 0x00800000U
+#define RTC_ALRMBR_PM 0x00400000U
+#define RTC_ALRMBR_HT 0x00300000U
+#define RTC_ALRMBR_HT_0 0x00100000U
+#define RTC_ALRMBR_HT_1 0x00200000U
+#define RTC_ALRMBR_HU 0x000F0000U
+#define RTC_ALRMBR_HU_0 0x00010000U
+#define RTC_ALRMBR_HU_1 0x00020000U
+#define RTC_ALRMBR_HU_2 0x00040000U
+#define RTC_ALRMBR_HU_3 0x00080000U
+#define RTC_ALRMBR_MSK2 0x00008000U
+#define RTC_ALRMBR_MNT 0x00007000U
+#define RTC_ALRMBR_MNT_0 0x00001000U
+#define RTC_ALRMBR_MNT_1 0x00002000U
+#define RTC_ALRMBR_MNT_2 0x00004000U
+#define RTC_ALRMBR_MNU 0x00000F00U
+#define RTC_ALRMBR_MNU_0 0x00000100U
+#define RTC_ALRMBR_MNU_1 0x00000200U
+#define RTC_ALRMBR_MNU_2 0x00000400U
+#define RTC_ALRMBR_MNU_3 0x00000800U
+#define RTC_ALRMBR_MSK1 0x00000080U
+#define RTC_ALRMBR_ST 0x00000070U
+#define RTC_ALRMBR_ST_0 0x00000010U
+#define RTC_ALRMBR_ST_1 0x00000020U
+#define RTC_ALRMBR_ST_2 0x00000040U
+#define RTC_ALRMBR_SU 0x0000000FU
+#define RTC_ALRMBR_SU_0 0x00000001U
+#define RTC_ALRMBR_SU_1 0x00000002U
+#define RTC_ALRMBR_SU_2 0x00000004U
+#define RTC_ALRMBR_SU_3 0x00000008U
+
+/******************** Bits definition for RTC_WPR register ******************/
+#define RTC_WPR_KEY 0x000000FFU
+
+/******************** Bits definition for RTC_SSR register ******************/
+#define RTC_SSR_SS 0x0000FFFFU
+
+/******************** Bits definition for RTC_SHIFTR register ***************/
+#define RTC_SHIFTR_SUBFS 0x00007FFFU
+#define RTC_SHIFTR_ADD1S 0x80000000U
+
+/******************** Bits definition for RTC_TSTR register *****************/
+#define RTC_TSTR_PM 0x00400000U
+#define RTC_TSTR_HT 0x00300000U
+#define RTC_TSTR_HT_0 0x00100000U
+#define RTC_TSTR_HT_1 0x00200000U
+#define RTC_TSTR_HU 0x000F0000U
+#define RTC_TSTR_HU_0 0x00010000U
+#define RTC_TSTR_HU_1 0x00020000U
+#define RTC_TSTR_HU_2 0x00040000U
+#define RTC_TSTR_HU_3 0x00080000U
+#define RTC_TSTR_MNT 0x00007000U
+#define RTC_TSTR_MNT_0 0x00001000U
+#define RTC_TSTR_MNT_1 0x00002000U
+#define RTC_TSTR_MNT_2 0x00004000U
+#define RTC_TSTR_MNU 0x00000F00U
+#define RTC_TSTR_MNU_0 0x00000100U
+#define RTC_TSTR_MNU_1 0x00000200U
+#define RTC_TSTR_MNU_2 0x00000400U
+#define RTC_TSTR_MNU_3 0x00000800U
+#define RTC_TSTR_ST 0x00000070U
+#define RTC_TSTR_ST_0 0x00000010U
+#define RTC_TSTR_ST_1 0x00000020U
+#define RTC_TSTR_ST_2 0x00000040U
+#define RTC_TSTR_SU 0x0000000FU
+#define RTC_TSTR_SU_0 0x00000001U
+#define RTC_TSTR_SU_1 0x00000002U
+#define RTC_TSTR_SU_2 0x00000004U
+#define RTC_TSTR_SU_3 0x00000008U
+
+/******************** Bits definition for RTC_TSDR register *****************/
+#define RTC_TSDR_WDU 0x0000E000U
+#define RTC_TSDR_WDU_0 0x00002000U
+#define RTC_TSDR_WDU_1 0x00004000U
+#define RTC_TSDR_WDU_2 0x00008000U
+#define RTC_TSDR_MT 0x00001000U
+#define RTC_TSDR_MU 0x00000F00U
+#define RTC_TSDR_MU_0 0x00000100U
+#define RTC_TSDR_MU_1 0x00000200U
+#define RTC_TSDR_MU_2 0x00000400U
+#define RTC_TSDR_MU_3 0x00000800U
+#define RTC_TSDR_DT 0x00000030U
+#define RTC_TSDR_DT_0 0x00000010U
+#define RTC_TSDR_DT_1 0x00000020U
+#define RTC_TSDR_DU 0x0000000FU
+#define RTC_TSDR_DU_0 0x00000001U
+#define RTC_TSDR_DU_1 0x00000002U
+#define RTC_TSDR_DU_2 0x00000004U
+#define RTC_TSDR_DU_3 0x00000008U
+
+/******************** Bits definition for RTC_TSSSR register ****************/
+#define RTC_TSSSR_SS 0x0000FFFFU
+
+/******************** Bits definition for RTC_CAL register *****************/
+#define RTC_CALR_CALP 0x00008000U
+#define RTC_CALR_CALW8 0x00004000U
+#define RTC_CALR_CALW16 0x00002000U
+#define RTC_CALR_CALM 0x000001FFU
+#define RTC_CALR_CALM_0 0x00000001U
+#define RTC_CALR_CALM_1 0x00000002U
+#define RTC_CALR_CALM_2 0x00000004U
+#define RTC_CALR_CALM_3 0x00000008U
+#define RTC_CALR_CALM_4 0x00000010U
+#define RTC_CALR_CALM_5 0x00000020U
+#define RTC_CALR_CALM_6 0x00000040U
+#define RTC_CALR_CALM_7 0x00000080U
+#define RTC_CALR_CALM_8 0x00000100U
+
+/******************** Bits definition for RTC_TAFCR register ****************/
+#define RTC_TAFCR_ALARMOUTTYPE 0x00040000U
+#define RTC_TAFCR_TSINSEL 0x00020000U
+#define RTC_TAFCR_TAMPINSEL 0x00010000U
+#define RTC_TAFCR_TAMPPUDIS 0x00008000U
+#define RTC_TAFCR_TAMPPRCH 0x00006000U
+#define RTC_TAFCR_TAMPPRCH_0 0x00002000U
+#define RTC_TAFCR_TAMPPRCH_1 0x00004000U
+#define RTC_TAFCR_TAMPFLT 0x00001800U
+#define RTC_TAFCR_TAMPFLT_0 0x00000800U
+#define RTC_TAFCR_TAMPFLT_1 0x00001000U
+#define RTC_TAFCR_TAMPFREQ 0x00000700U
+#define RTC_TAFCR_TAMPFREQ_0 0x00000100U
+#define RTC_TAFCR_TAMPFREQ_1 0x00000200U
+#define RTC_TAFCR_TAMPFREQ_2 0x00000400U
+#define RTC_TAFCR_TAMPTS 0x00000080U
+#define RTC_TAFCR_TAMP2TRG 0x00000010U
+#define RTC_TAFCR_TAMP2E 0x00000008U
+#define RTC_TAFCR_TAMPIE 0x00000004U
+#define RTC_TAFCR_TAMP1TRG 0x00000002U
+#define RTC_TAFCR_TAMP1E 0x00000001U
+
+/******************** Bits definition for RTC_ALRMASSR register *************/
+#define RTC_ALRMASSR_MASKSS 0x0F000000U
+#define RTC_ALRMASSR_MASKSS_0 0x01000000U
+#define RTC_ALRMASSR_MASKSS_1 0x02000000U
+#define RTC_ALRMASSR_MASKSS_2 0x04000000U
+#define RTC_ALRMASSR_MASKSS_3 0x08000000U
+#define RTC_ALRMASSR_SS 0x00007FFFU
+
+/******************** Bits definition for RTC_ALRMBSSR register *************/
+#define RTC_ALRMBSSR_MASKSS 0x0F000000U
+#define RTC_ALRMBSSR_MASKSS_0 0x01000000U
+#define RTC_ALRMBSSR_MASKSS_1 0x02000000U
+#define RTC_ALRMBSSR_MASKSS_2 0x04000000U
+#define RTC_ALRMBSSR_MASKSS_3 0x08000000U
+#define RTC_ALRMBSSR_SS 0x00007FFFU
+
+/******************** Bits definition for RTC_BKP0R register ****************/
+#define RTC_BKP0R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP1R register ****************/
+#define RTC_BKP1R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP2R register ****************/
+#define RTC_BKP2R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP3R register ****************/
+#define RTC_BKP3R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP4R register ****************/
+#define RTC_BKP4R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP5R register ****************/
+#define RTC_BKP5R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP6R register ****************/
+#define RTC_BKP6R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP7R register ****************/
+#define RTC_BKP7R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP8R register ****************/
+#define RTC_BKP8R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP9R register ****************/
+#define RTC_BKP9R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP10R register ***************/
+#define RTC_BKP10R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP11R register ***************/
+#define RTC_BKP11R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP12R register ***************/
+#define RTC_BKP12R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP13R register ***************/
+#define RTC_BKP13R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP14R register ***************/
+#define RTC_BKP14R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP15R register ***************/
+#define RTC_BKP15R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP16R register ***************/
+#define RTC_BKP16R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP17R register ***************/
+#define RTC_BKP17R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP18R register ***************/
+#define RTC_BKP18R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP19R register ***************/
+#define RTC_BKP19R 0xFFFFFFFFU
+
+
+
+/******************************************************************************/
+/* */
+/* SD host Interface */
+/* */
+/******************************************************************************/
+/****************** Bit definition for SDIO_POWER register ******************/
+#define SDIO_POWER_PWRCTRL 0x03U /*!<PWRCTRL[1:0] bits (Power supply control bits) */
+#define SDIO_POWER_PWRCTRL_0 0x01U /*!<Bit 0 */
+#define SDIO_POWER_PWRCTRL_1 0x02U /*!<Bit 1 */
+
+/****************** Bit definition for SDIO_CLKCR register ******************/
+#define SDIO_CLKCR_CLKDIV 0x00FFU /*!<Clock divide factor */
+#define SDIO_CLKCR_CLKEN 0x0100U /*!<Clock enable bit */
+#define SDIO_CLKCR_PWRSAV 0x0200U /*!<Power saving configuration bit */
+#define SDIO_CLKCR_BYPASS 0x0400U /*!<Clock divider bypass enable bit */
+
+#define SDIO_CLKCR_WIDBUS 0x1800U /*!<WIDBUS[1:0] bits (Wide bus mode enable bit) */
+#define SDIO_CLKCR_WIDBUS_0 0x0800U /*!<Bit 0 */
+#define SDIO_CLKCR_WIDBUS_1 0x1000U /*!<Bit 1 */
+
+#define SDIO_CLKCR_NEGEDGE 0x2000U /*!<SDIO_CK dephasing selection bit */
+#define SDIO_CLKCR_HWFC_EN 0x4000U /*!<HW Flow Control enable */
+
+/******************* Bit definition for SDIO_ARG register *******************/
+#define SDIO_ARG_CMDARG 0xFFFFFFFFU /*!<Command argument */
+
+/******************* Bit definition for SDIO_CMD register *******************/
+#define SDIO_CMD_CMDINDEX 0x003FU /*!<Command Index */
+
+#define SDIO_CMD_WAITRESP 0x00C0U /*!<WAITRESP[1:0] bits (Wait for response bits) */
+#define SDIO_CMD_WAITRESP_0 0x0040U /*!< Bit 0 */
+#define SDIO_CMD_WAITRESP_1 0x0080U /*!< Bit 1 */
+
+#define SDIO_CMD_WAITINT 0x0100U /*!<CPSM Waits for Interrupt Request */
+#define SDIO_CMD_WAITPEND 0x0200U /*!<CPSM Waits for ends of data transfer (CmdPend internal signal) */
+#define SDIO_CMD_CPSMEN 0x0400U /*!<Command path state machine (CPSM) Enable bit */
+#define SDIO_CMD_SDIOSUSPEND 0x0800U /*!<SD I/O suspend command */
+#define SDIO_CMD_ENCMDCOMPL 0x1000U /*!<Enable CMD completion */
+#define SDIO_CMD_NIEN 0x2000U /*!<Not Interrupt Enable */
+#define SDIO_CMD_CEATACMD 0x4000U /*!<CE-ATA command */
+
+/***************** Bit definition for SDIO_RESPCMD register *****************/
+#define SDIO_RESPCMD_RESPCMD 0x3FU /*!<Response command index */
+
+/****************** Bit definition for SDIO_RESP0 register ******************/
+#define SDIO_RESP0_CARDSTATUS0 0xFFFFFFFFU /*!<Card Status */
+
+/****************** Bit definition for SDIO_RESP1 register ******************/
+#define SDIO_RESP1_CARDSTATUS1 0xFFFFFFFFU /*!<Card Status */
+
+/****************** Bit definition for SDIO_RESP2 register ******************/
+#define SDIO_RESP2_CARDSTATUS2 0xFFFFFFFFU /*!<Card Status */
+
+/****************** Bit definition for SDIO_RESP3 register ******************/
+#define SDIO_RESP3_CARDSTATUS3 0xFFFFFFFFU /*!<Card Status */
+
+/****************** Bit definition for SDIO_RESP4 register ******************/
+#define SDIO_RESP4_CARDSTATUS4 0xFFFFFFFFU /*!<Card Status */
+
+/****************** Bit definition for SDIO_DTIMER register *****************/
+#define SDIO_DTIMER_DATATIME 0xFFFFFFFFU /*!<Data timeout period. */
+
+/****************** Bit definition for SDIO_DLEN register *******************/
+#define SDIO_DLEN_DATALENGTH 0x01FFFFFFU /*!<Data length value */
+
+/****************** Bit definition for SDIO_DCTRL register ******************/
+#define SDIO_DCTRL_DTEN 0x0001U /*!<Data transfer enabled bit */
+#define SDIO_DCTRL_DTDIR 0x0002U /*!<Data transfer direction selection */
+#define SDIO_DCTRL_DTMODE 0x0004U /*!<Data transfer mode selection */
+#define SDIO_DCTRL_DMAEN 0x0008U /*!<DMA enabled bit */
+
+#define SDIO_DCTRL_DBLOCKSIZE 0x00F0U /*!<DBLOCKSIZE[3:0] bits (Data block size) */
+#define SDIO_DCTRL_DBLOCKSIZE_0 0x0010U /*!<Bit 0 */
+#define SDIO_DCTRL_DBLOCKSIZE_1 0x0020U /*!<Bit 1 */
+#define SDIO_DCTRL_DBLOCKSIZE_2 0x0040U /*!<Bit 2 */
+#define SDIO_DCTRL_DBLOCKSIZE_3 0x0080U /*!<Bit 3 */
+
+#define SDIO_DCTRL_RWSTART 0x0100U /*!<Read wait start */
+#define SDIO_DCTRL_RWSTOP 0x0200U /*!<Read wait stop */
+#define SDIO_DCTRL_RWMOD 0x0400U /*!<Read wait mode */
+#define SDIO_DCTRL_SDIOEN 0x0800U /*!<SD I/O enable functions */
+
+/****************** Bit definition for SDIO_DCOUNT register *****************/
+#define SDIO_DCOUNT_DATACOUNT 0x01FFFFFFU /*!<Data count value */
+
+/****************** Bit definition for SDIO_STA register ********************/
+#define SDIO_STA_CCRCFAIL 0x00000001U /*!<Command response received (CRC check failed) */
+#define SDIO_STA_DCRCFAIL 0x00000002U /*!<Data block sent/received (CRC check failed) */
+#define SDIO_STA_CTIMEOUT 0x00000004U /*!<Command response timeout */
+#define SDIO_STA_DTIMEOUT 0x00000008U /*!<Data timeout */
+#define SDIO_STA_TXUNDERR 0x00000010U /*!<Transmit FIFO underrun error */
+#define SDIO_STA_RXOVERR 0x00000020U /*!<Received FIFO overrun error */
+#define SDIO_STA_CMDREND 0x00000040U /*!<Command response received (CRC check passed) */
+#define SDIO_STA_CMDSENT 0x00000080U /*!<Command sent (no response required) */
+#define SDIO_STA_DATAEND 0x00000100U /*!<Data end (data counter, SDIDCOUNT, is zero) */
+#define SDIO_STA_STBITERR 0x00000200U /*!<Start bit not detected on all data signals in wide bus mode */
+#define SDIO_STA_DBCKEND 0x00000400U /*!<Data block sent/received (CRC check passed) */
+#define SDIO_STA_CMDACT 0x00000800U /*!<Command transfer in progress */
+#define SDIO_STA_TXACT 0x00001000U /*!<Data transmit in progress */
+#define SDIO_STA_RXACT 0x00002000U /*!<Data receive in progress */
+#define SDIO_STA_TXFIFOHE 0x00004000U /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
+#define SDIO_STA_RXFIFOHF 0x00008000U /*!<Receive FIFO Half Full: there are at least 8 words in the FIFO */
+#define SDIO_STA_TXFIFOF 0x00010000U /*!<Transmit FIFO full */
+#define SDIO_STA_RXFIFOF 0x00020000U /*!<Receive FIFO full */
+#define SDIO_STA_TXFIFOE 0x00040000U /*!<Transmit FIFO empty */
+#define SDIO_STA_RXFIFOE 0x00080000U /*!<Receive FIFO empty */
+#define SDIO_STA_TXDAVL 0x00100000U /*!<Data available in transmit FIFO */
+#define SDIO_STA_RXDAVL 0x00200000U /*!<Data available in receive FIFO */
+#define SDIO_STA_SDIOIT 0x00400000U /*!<SDIO interrupt received */
+#define SDIO_STA_CEATAEND 0x00800000U /*!<CE-ATA command completion signal received for CMD61 */
+
+/******************* Bit definition for SDIO_ICR register *******************/
+#define SDIO_ICR_CCRCFAILC 0x00000001U /*!<CCRCFAIL flag clear bit */
+#define SDIO_ICR_DCRCFAILC 0x00000002U /*!<DCRCFAIL flag clear bit */
+#define SDIO_ICR_CTIMEOUTC 0x00000004U /*!<CTIMEOUT flag clear bit */
+#define SDIO_ICR_DTIMEOUTC 0x00000008U /*!<DTIMEOUT flag clear bit */
+#define SDIO_ICR_TXUNDERRC 0x00000010U /*!<TXUNDERR flag clear bit */
+#define SDIO_ICR_RXOVERRC 0x00000020U /*!<RXOVERR flag clear bit */
+#define SDIO_ICR_CMDRENDC 0x00000040U /*!<CMDREND flag clear bit */
+#define SDIO_ICR_CMDSENTC 0x00000080U /*!<CMDSENT flag clear bit */
+#define SDIO_ICR_DATAENDC 0x00000100U /*!<DATAEND flag clear bit */
+#define SDIO_ICR_STBITERRC 0x00000200U /*!<STBITERR flag clear bit */
+#define SDIO_ICR_DBCKENDC 0x00000400U /*!<DBCKEND flag clear bit */
+#define SDIO_ICR_SDIOITC 0x00400000U /*!<SDIOIT flag clear bit */
+#define SDIO_ICR_CEATAENDC 0x00800000U /*!<CEATAEND flag clear bit */
+
+/****************** Bit definition for SDIO_MASK register *******************/
+#define SDIO_MASK_CCRCFAILIE 0x00000001U /*!<Command CRC Fail Interrupt Enable */
+#define SDIO_MASK_DCRCFAILIE 0x00000002U /*!<Data CRC Fail Interrupt Enable */
+#define SDIO_MASK_CTIMEOUTIE 0x00000004U /*!<Command TimeOut Interrupt Enable */
+#define SDIO_MASK_DTIMEOUTIE 0x00000008U /*!<Data TimeOut Interrupt Enable */
+#define SDIO_MASK_TXUNDERRIE 0x00000010U /*!<Tx FIFO UnderRun Error Interrupt Enable */
+#define SDIO_MASK_RXOVERRIE 0x00000020U /*!<Rx FIFO OverRun Error Interrupt Enable */
+#define SDIO_MASK_CMDRENDIE 0x00000040U /*!<Command Response Received Interrupt Enable */
+#define SDIO_MASK_CMDSENTIE 0x00000080U /*!<Command Sent Interrupt Enable */
+#define SDIO_MASK_DATAENDIE 0x00000100U /*!<Data End Interrupt Enable */
+#define SDIO_MASK_STBITERRIE 0x00000200U /*!<Start Bit Error Interrupt Enable */
+#define SDIO_MASK_DBCKENDIE 0x00000400U /*!<Data Block End Interrupt Enable */
+#define SDIO_MASK_CMDACTIE 0x00000800U /*!<CCommand Acting Interrupt Enable */
+#define SDIO_MASK_TXACTIE 0x00001000U /*!<Data Transmit Acting Interrupt Enable */
+#define SDIO_MASK_RXACTIE 0x00002000U /*!<Data receive acting interrupt enabled */
+#define SDIO_MASK_TXFIFOHEIE 0x00004000U /*!<Tx FIFO Half Empty interrupt Enable */
+#define SDIO_MASK_RXFIFOHFIE 0x00008000U /*!<Rx FIFO Half Full interrupt Enable */
+#define SDIO_MASK_TXFIFOFIE 0x00010000U /*!<Tx FIFO Full interrupt Enable */
+#define SDIO_MASK_RXFIFOFIE 0x00020000U /*!<Rx FIFO Full interrupt Enable */
+#define SDIO_MASK_TXFIFOEIE 0x00040000U /*!<Tx FIFO Empty interrupt Enable */
+#define SDIO_MASK_RXFIFOEIE 0x00080000U /*!<Rx FIFO Empty interrupt Enable */
+#define SDIO_MASK_TXDAVLIE 0x00100000U /*!<Data available in Tx FIFO interrupt Enable */
+#define SDIO_MASK_RXDAVLIE 0x00200000U /*!<Data available in Rx FIFO interrupt Enable */
+#define SDIO_MASK_SDIOITIE 0x00400000U /*!<SDIO Mode Interrupt Received interrupt Enable */
+#define SDIO_MASK_CEATAENDIE 0x00800000U /*!<CE-ATA command completion signal received Interrupt Enable */
+
+/***************** Bit definition for SDIO_FIFOCNT register *****************/
+#define SDIO_FIFOCNT_FIFOCOUNT 0x00FFFFFFU /*!<Remaining number of words to be written to or read from the FIFO */
+
+/****************** Bit definition for SDIO_FIFO register *******************/
+#define SDIO_FIFO_FIFODATA 0xFFFFFFFFU /*!<Receive and transmit FIFO data */
+
+/******************************************************************************/
+/* */
+/* Serial Peripheral Interface */
+/* */
+/******************************************************************************/
+/******************* Bit definition for SPI_CR1 register ********************/
+#define SPI_CR1_CPHA 0x00000001U /*!<Clock Phase */
+#define SPI_CR1_CPOL 0x00000002U /*!<Clock Polarity */
+#define SPI_CR1_MSTR 0x00000004U /*!<Master Selection */
+
+#define SPI_CR1_BR 0x00000038U /*!<BR[2:0] bits (Baud Rate Control) */
+#define SPI_CR1_BR_0 0x00000008U /*!<Bit 0 */
+#define SPI_CR1_BR_1 0x00000010U /*!<Bit 1 */
+#define SPI_CR1_BR_2 0x00000020U /*!<Bit 2 */
+
+#define SPI_CR1_SPE 0x00000040U /*!<SPI Enable */
+#define SPI_CR1_LSBFIRST 0x00000080U /*!<Frame Format */
+#define SPI_CR1_SSI 0x00000100U /*!<Internal slave select */
+#define SPI_CR1_SSM 0x00000200U /*!<Software slave management */
+#define SPI_CR1_RXONLY 0x00000400U /*!<Receive only */
+#define SPI_CR1_DFF 0x00000800U /*!<Data Frame Format */
+#define SPI_CR1_CRCNEXT 0x00001000U /*!<Transmit CRC next */
+#define SPI_CR1_CRCEN 0x00002000U /*!<Hardware CRC calculation enable */
+#define SPI_CR1_BIDIOE 0x00004000U /*!<Output enable in bidirectional mode */
+#define SPI_CR1_BIDIMODE 0x00008000U /*!<Bidirectional data mode enable */
+
+/******************* Bit definition for SPI_CR2 register ********************/
+#define SPI_CR2_RXDMAEN 0x00000001U /*!<Rx Buffer DMA Enable */
+#define SPI_CR2_TXDMAEN 0x00000002U /*!<Tx Buffer DMA Enable */
+#define SPI_CR2_SSOE 0x00000004U /*!<SS Output Enable */
+#define SPI_CR2_FRF 0x00000010U /*!<Frame Format */
+#define SPI_CR2_ERRIE 0x00000020U /*!<Error Interrupt Enable */
+#define SPI_CR2_RXNEIE 0x00000040U /*!<RX buffer Not Empty Interrupt Enable */
+#define SPI_CR2_TXEIE 0x00000080U /*!<Tx buffer Empty Interrupt Enable */
+
+/******************** Bit definition for SPI_SR register ********************/
+#define SPI_SR_RXNE 0x00000001U /*!<Receive buffer Not Empty */
+#define SPI_SR_TXE 0x00000002U /*!<Transmit buffer Empty */
+#define SPI_SR_CHSIDE 0x00000004U /*!<Channel side */
+#define SPI_SR_UDR 0x00000008U /*!<Underrun flag */
+#define SPI_SR_CRCERR 0x00000010U /*!<CRC Error flag */
+#define SPI_SR_MODF 0x00000020U /*!<Mode fault */
+#define SPI_SR_OVR 0x00000040U /*!<Overrun flag */
+#define SPI_SR_BSY 0x00000080U /*!<Busy flag */
+#define SPI_SR_FRE 0x00000100U /*!<Frame format error flag */
+
+/******************** Bit definition for SPI_DR register ********************/
+#define SPI_DR_DR 0x0000FFFFU /*!<Data Register */
+
+/******************* Bit definition for SPI_CRCPR register ******************/
+#define SPI_CRCPR_CRCPOLY 0x0000FFFFU /*!<CRC polynomial register */
+
+/****************** Bit definition for SPI_RXCRCR register ******************/
+#define SPI_RXCRCR_RXCRC 0x0000FFFFU /*!<Rx CRC Register */
+
+/****************** Bit definition for SPI_TXCRCR register ******************/
+#define SPI_TXCRCR_TXCRC 0x0000FFFFU /*!<Tx CRC Register */
+
+/****************** Bit definition for SPI_I2SCFGR register *****************/
+#define SPI_I2SCFGR_CHLEN 0x00000001U /*!<Channel length (number of bits per audio channel) */
+
+#define SPI_I2SCFGR_DATLEN 0x00000006U /*!<DATLEN[1:0] bits (Data length to be transferred) */
+#define SPI_I2SCFGR_DATLEN_0 0x00000002U /*!<Bit 0 */
+#define SPI_I2SCFGR_DATLEN_1 0x00000004U /*!<Bit 1 */
+
+#define SPI_I2SCFGR_CKPOL 0x00000008U /*!<steady state clock polarity */
+
+#define SPI_I2SCFGR_I2SSTD 0x00000030U /*!<I2SSTD[1:0] bits (I2S standard selection) */
+#define SPI_I2SCFGR_I2SSTD_0 0x00000010U /*!<Bit 0 */
+#define SPI_I2SCFGR_I2SSTD_1 0x00000020U /*!<Bit 1 */
+
+#define SPI_I2SCFGR_PCMSYNC 0x00000080U /*!<PCM frame synchronization */
+
+#define SPI_I2SCFGR_I2SCFG 0x00000300U /*!<I2SCFG[1:0] bits (I2S configuration mode) */
+#define SPI_I2SCFGR_I2SCFG_0 0x00000100U /*!<Bit 0 */
+#define SPI_I2SCFGR_I2SCFG_1 0x00000200U /*!<Bit 1 */
+
+#define SPI_I2SCFGR_I2SE 0x00000400U /*!<I2S Enable */
+#define SPI_I2SCFGR_I2SMOD 0x00000800U /*!<I2S mode selection */
+
+/****************** Bit definition for SPI_I2SPR register *******************/
+#define SPI_I2SPR_I2SDIV 0x000000FFU /*!<I2S Linear prescaler */
+#define SPI_I2SPR_ODD 0x00000100U /*!<Odd factor for the prescaler */
+#define SPI_I2SPR_MCKOE 0x00000200U /*!<Master Clock Output Enable */
+
+/******************************************************************************/
+/* */
+/* SYSCFG */
+/* */
+/******************************************************************************/
+/****************** Bit definition for SYSCFG_MEMRMP register ***************/
+#define SYSCFG_MEMRMP_MEM_MODE 0x00000007U /*!< SYSCFG_Memory Remap Config */
+#define SYSCFG_MEMRMP_MEM_MODE_0 0x00000001U
+#define SYSCFG_MEMRMP_MEM_MODE_1 0x00000002U
+#define SYSCFG_MEMRMP_MEM_MODE_2 0x00000004U
+
+/****************** Bit definition for SYSCFG_PMC register ******************/
+#define SYSCFG_PMC_ADC1DC2 0x00010000U /*!< Refer to AN4073 on how to use this bit */
+
+/***************** Bit definition for SYSCFG_EXTICR1 register ***************/
+#define SYSCFG_EXTICR1_EXTI0 0x000FU /*!<EXTI 0 configuration */
+#define SYSCFG_EXTICR1_EXTI1 0x00F0U /*!<EXTI 1 configuration */
+#define SYSCFG_EXTICR1_EXTI2 0x0F00U /*!<EXTI 2 configuration */
+#define SYSCFG_EXTICR1_EXTI3 0xF000U /*!<EXTI 3 configuration */
+/**
+ * @brief EXTI0 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI0_PA 0x0000U /*!<PA[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PB 0x0001U /*!<PB[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PC 0x0002U /*!<PC[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PD 0x0003U /*!<PD[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PE 0x0004U /*!<PE[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PF 0x0005U /*!<PE[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PG 0x0006U /*!<PE[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PH 0x0007U /*!<PH[0] pin */
+
+/**
+ * @brief EXTI1 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI1_PA 0x0000U /*!<PA[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PB 0x0010U /*!<PB[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PC 0x0020U /*!<PC[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PD 0x0030U /*!<PD[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PE 0x0040U /*!<PE[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PF 0x0050U /*!<PD[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PG 0x0060U /*!<PE[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PH 0x0070U /*!<PH[1] pin */
+
+/**
+ * @brief EXTI2 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI2_PA 0x0000U /*!<PA[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PB 0x0100U /*!<PB[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PC 0x0200U /*!<PC[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PD 0x0300U /*!<PD[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PE 0x0400U /*!<PE[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PF 0x0500U /*!<PE[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PG 0x0600U /*!<PE[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PH 0x0700U /*!<PH[2] pin */
+
+/**
+ * @brief EXTI3 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI3_PA 0x0000U /*!<PA[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PB 0x1000U /*!<PB[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PC 0x2000U /*!<PC[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PD 0x3000U /*!<PD[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PE 0x4000U /*!<PE[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PF 0x5000U /*!<PE[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PG 0x6000U /*!<PE[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PH 0x7000U /*!<PH[3] pin */
+
+/***************** Bit definition for SYSCFG_EXTICR2 register ***************/
+#define SYSCFG_EXTICR2_EXTI4 0x000FU /*!<EXTI 4 configuration */
+#define SYSCFG_EXTICR2_EXTI5 0x00F0U /*!<EXTI 5 configuration */
+#define SYSCFG_EXTICR2_EXTI6 0x0F00U /*!<EXTI 6 configuration */
+#define SYSCFG_EXTICR2_EXTI7 0xF000U /*!<EXTI 7 configuration */
+/**
+ * @brief EXTI4 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI4_PA 0x0000U /*!<PA[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PB 0x0001U /*!<PB[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PC 0x0002U /*!<PC[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PD 0x0003U /*!<PD[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PE 0x0004U /*!<PE[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PF 0x0005U /*!<PE[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PG 0x0006U /*!<PE[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PH 0x0007U /*!<PH[4] pin */
+
+/**
+ * @brief EXTI5 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI5_PA 0x0000U /*!<PA[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PB 0x0010U /*!<PB[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PC 0x0020U /*!<PC[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PD 0x0030U /*!<PD[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PE 0x0040U /*!<PE[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PF 0x0050U /*!<PE[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PG 0x0060U /*!<PE[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PH 0x0070U /*!<PH[5] pin */
+
+/**
+ * @brief EXTI6 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI6_PA 0x0000U /*!<PA[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PB 0x0100U /*!<PB[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PC 0x0200U /*!<PC[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PD 0x0300U /*!<PD[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PE 0x0400U /*!<PE[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PF 0x0500U /*!<PE[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PG 0x0600U /*!<PE[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PH 0x0700U /*!<PH[6] pin */
+
+/**
+ * @brief EXTI7 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI7_PA 0x0000U /*!<PA[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PB 0x1000U /*!<PB[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PC 0x2000U /*!<PC[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PD 0x3000U /*!<PD[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PE 0x4000U /*!<PE[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PF 0x5000U /*!<PE[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PG 0x6000U /*!<PE[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PH 0x7000U /*!<PH[7] pin */
+
+
+/***************** Bit definition for SYSCFG_EXTICR3 register ***************/
+#define SYSCFG_EXTICR3_EXTI8 0x000FU /*!<EXTI 8 configuration */
+#define SYSCFG_EXTICR3_EXTI9 0x00F0U /*!<EXTI 9 configuration */
+#define SYSCFG_EXTICR3_EXTI10 0x0F00U /*!<EXTI 10 configuration */
+#define SYSCFG_EXTICR3_EXTI11 0xF000U /*!<EXTI 11 configuration */
+
+/**
+ * @brief EXTI8 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI8_PA 0x0000U /*!<PA[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PB 0x0001U /*!<PB[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PC 0x0002U /*!<PC[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PD 0x0003U /*!<PD[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PE 0x0004U /*!<PE[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PF 0x0005U /*!<PE[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PG 0x0006U /*!<PE[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PH 0x0007U /*!<PH[8] pin */
+
+/**
+ * @brief EXTI9 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI9_PA 0x0000U /*!<PA[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PB 0x0010U /*!<PB[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PC 0x0020U /*!<PC[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PD 0x0030U /*!<PD[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PE 0x0040U /*!<PE[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PF 0x0050U /*!<PE[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PG 0x0060U /*!<PE[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PH 0x0070U /*!<PH[9] pin */
+
+/**
+ * @brief EXTI10 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI10_PA 0x0000U /*!<PA[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PB 0x0100U /*!<PB[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PC 0x0200U /*!<PC[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PD 0x0300U /*!<PD[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PE 0x0400U /*!<PE[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PF 0x0500U /*!<PE[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PG 0x0600U /*!<PE[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PH 0x0700U /*!<PH[10] pin */
+
+/**
+ * @brief EXTI11 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI11_PA 0x0000U /*!<PA[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PB 0x1000U /*!<PB[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PC 0x2000U /*!<PC[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PD 0x3000U /*!<PD[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PE 0x4000U /*!<PE[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PF 0x5000U /*!<PE[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PG 0x6000U /*!<PE[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PH 0x7000U /*!<PH[11] pin */
+
+/***************** Bit definition for SYSCFG_EXTICR4 register ***************/
+#define SYSCFG_EXTICR4_EXTI12 0x000FU /*!<EXTI 12 configuration */
+#define SYSCFG_EXTICR4_EXTI13 0x00F0U /*!<EXTI 13 configuration */
+#define SYSCFG_EXTICR4_EXTI14 0x0F00U /*!<EXTI 14 configuration */
+#define SYSCFG_EXTICR4_EXTI15 0xF000U /*!<EXTI 15 configuration */
+/**
+ * @brief EXTI12 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI12_PA 0x0000U /*!<PA[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PB 0x0001U /*!<PB[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PC 0x0002U /*!<PC[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PD 0x0003U /*!<PD[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PE 0x0004U /*!<PE[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PF 0x0005U /*!<PE[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PG 0x0006U /*!<PE[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PH 0x0007U /*!<PH[12] pin */
+
+/**
+ * @brief EXTI13 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI13_PA 0x0000U /*!<PA[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PB 0x0010U /*!<PB[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PC 0x0020U /*!<PC[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PD 0x0030U /*!<PD[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PE 0x0040U /*!<PE[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PF 0x0050U /*!<PE[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PG 0x0060U /*!<PE[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PH 0x0070U /*!<PH[13] pin */
+
+/**
+ * @brief EXTI14 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI14_PA 0x0000U /*!<PA[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PB 0x0100U /*!<PB[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PC 0x0200U /*!<PC[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PD 0x0300U /*!<PD[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PE 0x0400U /*!<PE[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PF 0x0500U /*!<PE[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PG 0x0600U /*!<PE[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PH 0x0700U /*!<PH[14] pin */
+
+/**
+ * @brief EXTI15 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI15_PA 0x0000U /*!<PA[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PB 0x1000U /*!<PB[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PC 0x2000U /*!<PC[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PD 0x3000U /*!<PD[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PE 0x4000U /*!<PE[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PF 0x5000U /*!<PF[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PG 0x6000U /*!<PG[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PH 0x7000U /*!<PH[15] pin */
+
+/****************** Bit definition for SYSCFG_CMPCR register ****************/
+#define SYSCFG_CMPCR_CMP_PD 0x00000001U /*!<Compensation cell ready flag */
+#define SYSCFG_CMPCR_READY 0x00000100U /*!<Compensation cell power-down */
+
+/****************** Bit definition for SYSCFG_CFGR register *****************/
+#define SYSCFG_CFGR_FMPI2C1_SCL 0x00000001U /*!<FM+ drive capability for FMPI2C1_SCL pin */
+#define SYSCFG_CFGR_FMPI2C1_SDA 0x00000002U /*!<FM+ drive capability for FMPI2C1_SDA pin */
+
+/******************************************************************************/
+/* */
+/* TIM */
+/* */
+/******************************************************************************/
+/******************* Bit definition for TIM_CR1 register ********************/
+#define TIM_CR1_CEN 0x0001U /*!<Counter enable */
+#define TIM_CR1_UDIS 0x0002U /*!<Update disable */
+#define TIM_CR1_URS 0x0004U /*!<Update request source */
+#define TIM_CR1_OPM 0x0008U /*!<One pulse mode */
+#define TIM_CR1_DIR 0x0010U /*!<Direction */
+
+#define TIM_CR1_CMS 0x0060U /*!<CMS[1:0] bits (Center-aligned mode selection) */
+#define TIM_CR1_CMS_0 0x0020U /*!<Bit 0 */
+#define TIM_CR1_CMS_1 0x0040U /*!<Bit 1 */
+
+#define TIM_CR1_ARPE 0x0080U /*!<Auto-reload preload enable */
+
+#define TIM_CR1_CKD 0x0300U /*!<CKD[1:0] bits (clock division) */
+#define TIM_CR1_CKD_0 0x0100U /*!<Bit 0 */
+#define TIM_CR1_CKD_1 0x0200U /*!<Bit 1 */
+
+/******************* Bit definition for TIM_CR2 register ********************/
+#define TIM_CR2_CCPC 0x0001U /*!<Capture/Compare Preloaded Control */
+#define TIM_CR2_CCUS 0x0004U /*!<Capture/Compare Control Update Selection */
+#define TIM_CR2_CCDS 0x0008U /*!<Capture/Compare DMA Selection */
+
+#define TIM_CR2_MMS 0x0070U /*!<MMS[2:0] bits (Master Mode Selection) */
+#define TIM_CR2_MMS_0 0x0010U /*!<Bit 0 */
+#define TIM_CR2_MMS_1 0x0020U /*!<Bit 1 */
+#define TIM_CR2_MMS_2 0x0040U /*!<Bit 2 */
+
+#define TIM_CR2_TI1S 0x0080U /*!<TI1 Selection */
+#define TIM_CR2_OIS1 0x0100U /*!<Output Idle state 1 (OC1 output) */
+#define TIM_CR2_OIS1N 0x0200U /*!<Output Idle state 1 (OC1N output) */
+#define TIM_CR2_OIS2 0x0400U /*!<Output Idle state 2 (OC2 output) */
+#define TIM_CR2_OIS2N 0x0800U /*!<Output Idle state 2 (OC2N output) */
+#define TIM_CR2_OIS3 0x1000U /*!<Output Idle state 3 (OC3 output) */
+#define TIM_CR2_OIS3N 0x2000U /*!<Output Idle state 3 (OC3N output) */
+#define TIM_CR2_OIS4 0x4000U /*!<Output Idle state 4 (OC4 output) */
+
+/******************* Bit definition for TIM_SMCR register *******************/
+#define TIM_SMCR_SMS 0x0007U /*!<SMS[2:0] bits (Slave mode selection) */
+#define TIM_SMCR_SMS_0 0x0001U /*!<Bit 0 */
+#define TIM_SMCR_SMS_1 0x0002U /*!<Bit 1 */
+#define TIM_SMCR_SMS_2 0x0004U /*!<Bit 2 */
+
+#define TIM_SMCR_TS 0x0070U /*!<TS[2:0] bits (Trigger selection) */
+#define TIM_SMCR_TS_0 0x0010U /*!<Bit 0 */
+#define TIM_SMCR_TS_1 0x0020U /*!<Bit 1 */
+#define TIM_SMCR_TS_2 0x0040U /*!<Bit 2 */
+
+#define TIM_SMCR_MSM 0x0080U /*!<Master/slave mode */
+
+#define TIM_SMCR_ETF 0x0F00U /*!<ETF[3:0] bits (External trigger filter) */
+#define TIM_SMCR_ETF_0 0x0100U /*!<Bit 0 */
+#define TIM_SMCR_ETF_1 0x0200U /*!<Bit 1 */
+#define TIM_SMCR_ETF_2 0x0400U /*!<Bit 2 */
+#define TIM_SMCR_ETF_3 0x0800U /*!<Bit 3 */
+
+#define TIM_SMCR_ETPS 0x3000U /*!<ETPS[1:0] bits (External trigger prescaler) */
+#define TIM_SMCR_ETPS_0 0x1000U /*!<Bit 0 */
+#define TIM_SMCR_ETPS_1 0x2000U /*!<Bit 1 */
+
+#define TIM_SMCR_ECE 0x4000U /*!<External clock enable */
+#define TIM_SMCR_ETP 0x8000U /*!<External trigger polarity */
+
+/******************* Bit definition for TIM_DIER register *******************/
+#define TIM_DIER_UIE 0x0001U /*!<Update interrupt enable */
+#define TIM_DIER_CC1IE 0x0002U /*!<Capture/Compare 1 interrupt enable */
+#define TIM_DIER_CC2IE 0x0004U /*!<Capture/Compare 2 interrupt enable */
+#define TIM_DIER_CC3IE 0x0008U /*!<Capture/Compare 3 interrupt enable */
+#define TIM_DIER_CC4IE 0x0010U /*!<Capture/Compare 4 interrupt enable */
+#define TIM_DIER_COMIE 0x0020U /*!<COM interrupt enable */
+#define TIM_DIER_TIE 0x0040U /*!<Trigger interrupt enable */
+#define TIM_DIER_BIE 0x0080U /*!<Break interrupt enable */
+#define TIM_DIER_UDE 0x0100U /*!<Update DMA request enable */
+#define TIM_DIER_CC1DE 0x0200U /*!<Capture/Compare 1 DMA request enable */
+#define TIM_DIER_CC2DE 0x0400U /*!<Capture/Compare 2 DMA request enable */
+#define TIM_DIER_CC3DE 0x0800U /*!<Capture/Compare 3 DMA request enable */
+#define TIM_DIER_CC4DE 0x1000U /*!<Capture/Compare 4 DMA request enable */
+#define TIM_DIER_COMDE 0x2000U /*!<COM DMA request enable */
+#define TIM_DIER_TDE 0x4000U /*!<Trigger DMA request enable */
+
+/******************** Bit definition for TIM_SR register ********************/
+#define TIM_SR_UIF 0x0001U /*!<Update interrupt Flag */
+#define TIM_SR_CC1IF 0x0002U /*!<Capture/Compare 1 interrupt Flag */
+#define TIM_SR_CC2IF 0x0004U /*!<Capture/Compare 2 interrupt Flag */
+#define TIM_SR_CC3IF 0x0008U /*!<Capture/Compare 3 interrupt Flag */
+#define TIM_SR_CC4IF 0x0010U /*!<Capture/Compare 4 interrupt Flag */
+#define TIM_SR_COMIF 0x0020U /*!<COM interrupt Flag */
+#define TIM_SR_TIF 0x0040U /*!<Trigger interrupt Flag */
+#define TIM_SR_BIF 0x0080U /*!<Break interrupt Flag */
+#define TIM_SR_CC1OF 0x0200U /*!<Capture/Compare 1 Overcapture Flag */
+#define TIM_SR_CC2OF 0x0400U /*!<Capture/Compare 2 Overcapture Flag */
+#define TIM_SR_CC3OF 0x0800U /*!<Capture/Compare 3 Overcapture Flag */
+#define TIM_SR_CC4OF 0x1000U /*!<Capture/Compare 4 Overcapture Flag */
+
+/******************* Bit definition for TIM_EGR register ********************/
+#define TIM_EGR_UG 0x01U /*!<Update Generation */
+#define TIM_EGR_CC1G 0x02U /*!<Capture/Compare 1 Generation */
+#define TIM_EGR_CC2G 0x04U /*!<Capture/Compare 2 Generation */
+#define TIM_EGR_CC3G 0x08U /*!<Capture/Compare 3 Generation */
+#define TIM_EGR_CC4G 0x10U /*!<Capture/Compare 4 Generation */
+#define TIM_EGR_COMG 0x20U /*!<Capture/Compare Control Update Generation */
+#define TIM_EGR_TG 0x40U /*!<Trigger Generation */
+#define TIM_EGR_BG 0x80U /*!<Break Generation */
+
+/****************** Bit definition for TIM_CCMR1 register *******************/
+#define TIM_CCMR1_CC1S 0x0003U /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
+#define TIM_CCMR1_CC1S_0 0x0001U /*!<Bit 0 */
+#define TIM_CCMR1_CC1S_1 0x0002U /*!<Bit 1 */
+
+#define TIM_CCMR1_OC1FE 0x0004U /*!<Output Compare 1 Fast enable */
+#define TIM_CCMR1_OC1PE 0x0008U /*!<Output Compare 1 Preload enable */
+
+#define TIM_CCMR1_OC1M 0x0070U /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
+#define TIM_CCMR1_OC1M_0 0x0010U /*!<Bit 0 */
+#define TIM_CCMR1_OC1M_1 0x0020U /*!<Bit 1 */
+#define TIM_CCMR1_OC1M_2 0x0040U /*!<Bit 2 */
+
+#define TIM_CCMR1_OC1CE 0x0080U /*!<Output Compare 1Clear Enable */
+
+#define TIM_CCMR1_CC2S 0x0300U /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
+#define TIM_CCMR1_CC2S_0 0x0100U /*!<Bit 0 */
+#define TIM_CCMR1_CC2S_1 0x0200U /*!<Bit 1 */
+
+#define TIM_CCMR1_OC2FE 0x0400U /*!<Output Compare 2 Fast enable */
+#define TIM_CCMR1_OC2PE 0x0800U /*!<Output Compare 2 Preload enable */
+
+#define TIM_CCMR1_OC2M 0x7000U /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
+#define TIM_CCMR1_OC2M_0 0x1000U /*!<Bit 0 */
+#define TIM_CCMR1_OC2M_1 0x2000U /*!<Bit 1 */
+#define TIM_CCMR1_OC2M_2 0x4000U /*!<Bit 2 */
+
+#define TIM_CCMR1_OC2CE 0x8000U /*!<Output Compare 2 Clear Enable */
+
+/*----------------------------------------------------------------------------*/
+
+#define TIM_CCMR1_IC1PSC 0x000CU /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
+#define TIM_CCMR1_IC1PSC_0 0x0004U /*!<Bit 0 */
+#define TIM_CCMR1_IC1PSC_1 0x0008U /*!<Bit 1 */
+
+#define TIM_CCMR1_IC1F 0x00F0U /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
+#define TIM_CCMR1_IC1F_0 0x0010U /*!<Bit 0 */
+#define TIM_CCMR1_IC1F_1 0x0020U /*!<Bit 1 */
+#define TIM_CCMR1_IC1F_2 0x0040U /*!<Bit 2 */
+#define TIM_CCMR1_IC1F_3 0x0080U /*!<Bit 3 */
+
+#define TIM_CCMR1_IC2PSC 0x0C00U /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
+#define TIM_CCMR1_IC2PSC_0 0x0400U /*!<Bit 0 */
+#define TIM_CCMR1_IC2PSC_1 0x0800U /*!<Bit 1 */
+
+#define TIM_CCMR1_IC2F 0xF000U /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
+#define TIM_CCMR1_IC2F_0 0x1000U /*!<Bit 0 */
+#define TIM_CCMR1_IC2F_1 0x2000U /*!<Bit 1 */
+#define TIM_CCMR1_IC2F_2 0x4000U /*!<Bit 2 */
+#define TIM_CCMR1_IC2F_3 0x8000U /*!<Bit 3 */
+
+/****************** Bit definition for TIM_CCMR2 register *******************/
+#define TIM_CCMR2_CC3S 0x0003U /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
+#define TIM_CCMR2_CC3S_0 0x0001U /*!<Bit 0 */
+#define TIM_CCMR2_CC3S_1 0x0002U /*!<Bit 1 */
+
+#define TIM_CCMR2_OC3FE 0x0004U /*!<Output Compare 3 Fast enable */
+#define TIM_CCMR2_OC3PE 0x0008U /*!<Output Compare 3 Preload enable */
+
+#define TIM_CCMR2_OC3M 0x0070U /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
+#define TIM_CCMR2_OC3M_0 0x0010U /*!<Bit 0 */
+#define TIM_CCMR2_OC3M_1 0x0020U /*!<Bit 1 */
+#define TIM_CCMR2_OC3M_2 0x0040U /*!<Bit 2 */
+
+#define TIM_CCMR2_OC3CE 0x0080U /*!<Output Compare 3 Clear Enable */
+
+#define TIM_CCMR2_CC4S 0x0300U /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
+#define TIM_CCMR2_CC4S_0 0x0100U /*!<Bit 0 */
+#define TIM_CCMR2_CC4S_1 0x0200U /*!<Bit 1 */
+
+#define TIM_CCMR2_OC4FE 0x0400U /*!<Output Compare 4 Fast enable */
+#define TIM_CCMR2_OC4PE 0x0800U /*!<Output Compare 4 Preload enable */
+
+#define TIM_CCMR2_OC4M 0x7000U /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
+#define TIM_CCMR2_OC4M_0 0x1000U /*!<Bit 0 */
+#define TIM_CCMR2_OC4M_1 0x2000U /*!<Bit 1 */
+#define TIM_CCMR2_OC4M_2 0x4000U /*!<Bit 2 */
+
+#define TIM_CCMR2_OC4CE 0x8000U /*!<Output Compare 4 Clear Enable */
+
+/*----------------------------------------------------------------------------*/
+
+#define TIM_CCMR2_IC3PSC 0x000CU /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
+#define TIM_CCMR2_IC3PSC_0 0x0004U /*!<Bit 0 */
+#define TIM_CCMR2_IC3PSC_1 0x0008U /*!<Bit 1 */
+
+#define TIM_CCMR2_IC3F 0x00F0U /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
+#define TIM_CCMR2_IC3F_0 0x0010U /*!<Bit 0 */
+#define TIM_CCMR2_IC3F_1 0x0020U /*!<Bit 1 */
+#define TIM_CCMR2_IC3F_2 0x0040U /*!<Bit 2 */
+#define TIM_CCMR2_IC3F_3 0x0080U /*!<Bit 3 */
+
+#define TIM_CCMR2_IC4PSC 0x0C00U /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
+#define TIM_CCMR2_IC4PSC_0 0x0400U /*!<Bit 0 */
+#define TIM_CCMR2_IC4PSC_1 0x0800U /*!<Bit 1 */
+
+#define TIM_CCMR2_IC4F 0xF000U /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
+#define TIM_CCMR2_IC4F_0 0x1000U /*!<Bit 0 */
+#define TIM_CCMR2_IC4F_1 0x2000U /*!<Bit 1 */
+#define TIM_CCMR2_IC4F_2 0x4000U /*!<Bit 2 */
+#define TIM_CCMR2_IC4F_3 0x8000U /*!<Bit 3 */
+
+/******************* Bit definition for TIM_CCER register *******************/
+#define TIM_CCER_CC1E 0x0001U /*!<Capture/Compare 1 output enable */
+#define TIM_CCER_CC1P 0x0002U /*!<Capture/Compare 1 output Polarity */
+#define TIM_CCER_CC1NE 0x0004U /*!<Capture/Compare 1 Complementary output enable */
+#define TIM_CCER_CC1NP 0x0008U /*!<Capture/Compare 1 Complementary output Polarity */
+#define TIM_CCER_CC2E 0x0010U /*!<Capture/Compare 2 output enable */
+#define TIM_CCER_CC2P 0x0020U /*!<Capture/Compare 2 output Polarity */
+#define TIM_CCER_CC2NE 0x0040U /*!<Capture/Compare 2 Complementary output enable */
+#define TIM_CCER_CC2NP 0x0080U /*!<Capture/Compare 2 Complementary output Polarity */
+#define TIM_CCER_CC3E 0x0100U /*!<Capture/Compare 3 output enable */
+#define TIM_CCER_CC3P 0x0200U /*!<Capture/Compare 3 output Polarity */
+#define TIM_CCER_CC3NE 0x0400U /*!<Capture/Compare 3 Complementary output enable */
+#define TIM_CCER_CC3NP 0x0800U /*!<Capture/Compare 3 Complementary output Polarity */
+#define TIM_CCER_CC4E 0x1000U /*!<Capture/Compare 4 output enable */
+#define TIM_CCER_CC4P 0x2000U /*!<Capture/Compare 4 output Polarity */
+#define TIM_CCER_CC4NP 0x8000U /*!<Capture/Compare 4 Complementary output Polarity */
+
+/******************* Bit definition for TIM_CNT register ********************/
+#define TIM_CNT_CNT 0xFFFFU /*!<Counter Value */
+
+/******************* Bit definition for TIM_PSC register ********************/
+#define TIM_PSC_PSC 0xFFFFU /*!<Prescaler Value */
+
+/******************* Bit definition for TIM_ARR register ********************/
+#define TIM_ARR_ARR 0xFFFFU /*!<actual auto-reload Value */
+
+/******************* Bit definition for TIM_RCR register ********************/
+#define TIM_RCR_REP 0xFFU /*!<Repetition Counter Value */
+
+/******************* Bit definition for TIM_CCR1 register *******************/
+#define TIM_CCR1_CCR1 0xFFFFU /*!<Capture/Compare 1 Value */
+
+/******************* Bit definition for TIM_CCR2 register *******************/
+#define TIM_CCR2_CCR2 0xFFFFU /*!<Capture/Compare 2 Value */
+
+/******************* Bit definition for TIM_CCR3 register *******************/
+#define TIM_CCR3_CCR3 0xFFFFU /*!<Capture/Compare 3 Value */
+
+/******************* Bit definition for TIM_CCR4 register *******************/
+#define TIM_CCR4_CCR4 0xFFFFU /*!<Capture/Compare 4 Value */
+
+/******************* Bit definition for TIM_BDTR register *******************/
+#define TIM_BDTR_DTG 0x00FFU /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
+#define TIM_BDTR_DTG_0 0x0001U /*!<Bit 0 */
+#define TIM_BDTR_DTG_1 0x0002U /*!<Bit 1 */
+#define TIM_BDTR_DTG_2 0x0004U /*!<Bit 2 */
+#define TIM_BDTR_DTG_3 0x0008U /*!<Bit 3 */
+#define TIM_BDTR_DTG_4 0x0010U /*!<Bit 4 */
+#define TIM_BDTR_DTG_5 0x0020U /*!<Bit 5 */
+#define TIM_BDTR_DTG_6 0x0040U /*!<Bit 6 */
+#define TIM_BDTR_DTG_7 0x0080U /*!<Bit 7 */
+
+#define TIM_BDTR_LOCK 0x0300U /*!<LOCK[1:0] bits (Lock Configuration) */
+#define TIM_BDTR_LOCK_0 0x0100U /*!<Bit 0 */
+#define TIM_BDTR_LOCK_1 0x0200U /*!<Bit 1 */
+
+#define TIM_BDTR_OSSI 0x0400U /*!<Off-State Selection for Idle mode */
+#define TIM_BDTR_OSSR 0x0800U /*!<Off-State Selection for Run mode */
+#define TIM_BDTR_BKE 0x1000U /*!<Break enable */
+#define TIM_BDTR_BKP 0x2000U /*!<Break Polarity */
+#define TIM_BDTR_AOE 0x4000U /*!<Automatic Output enable */
+#define TIM_BDTR_MOE 0x8000U /*!<Main Output enable */
+
+/******************* Bit definition for TIM_DCR register ********************/
+#define TIM_DCR_DBA 0x001FU /*!<DBA[4:0] bits (DMA Base Address) */
+#define TIM_DCR_DBA_0 0x0001U /*!<Bit 0 */
+#define TIM_DCR_DBA_1 0x0002U /*!<Bit 1 */
+#define TIM_DCR_DBA_2 0x0004U /*!<Bit 2 */
+#define TIM_DCR_DBA_3 0x0008U /*!<Bit 3 */
+#define TIM_DCR_DBA_4 0x0010U /*!<Bit 4 */
+
+#define TIM_DCR_DBL 0x1F00U /*!<DBL[4:0] bits (DMA Burst Length) */
+#define TIM_DCR_DBL_0 0x0100U /*!<Bit 0 */
+#define TIM_DCR_DBL_1 0x0200U /*!<Bit 1 */
+#define TIM_DCR_DBL_2 0x0400U /*!<Bit 2 */
+#define TIM_DCR_DBL_3 0x0800U /*!<Bit 3 */
+#define TIM_DCR_DBL_4 0x1000U /*!<Bit 4 */
+
+/******************* Bit definition for TIM_DMAR register *******************/
+#define TIM_DMAR_DMAB 0xFFFFU /*!<DMA register for burst accesses */
+
+/******************* Bit definition for TIM_OR register *********************/
+#define TIM_OR_TI4_RMP 0x00C0U /*!<TI4_RMP[1:0] bits (TIM5 Input 4 remap) */
+#define TIM_OR_TI4_RMP_0 0x0040U /*!<Bit 0 */
+#define TIM_OR_TI4_RMP_1 0x0080U /*!<Bit 1 */
+#define TIM_OR_ITR1_RMP 0x0C00U /*!<ITR1_RMP[1:0] bits (TIM2 Internal trigger 1 remap) */
+#define TIM_OR_ITR1_RMP_0 0x0400U /*!<Bit 0 */
+#define TIM_OR_ITR1_RMP_1 0x0800U /*!<Bit 1 */
+
+
+/******************************************************************************/
+/* */
+/* Universal Synchronous Asynchronous Receiver Transmitter */
+/* */
+/******************************************************************************/
+/******************* Bit definition for USART_SR register *******************/
+#define USART_SR_PE 0x0001U /*!<Parity Error */
+#define USART_SR_FE 0x0002U /*!<Framing Error */
+#define USART_SR_NE 0x0004U /*!<Noise Error Flag */
+#define USART_SR_ORE 0x0008U /*!<OverRun Error */
+#define USART_SR_IDLE 0x0010U /*!<IDLE line detected */
+#define USART_SR_RXNE 0x0020U /*!<Read Data Register Not Empty */
+#define USART_SR_TC 0x0040U /*!<Transmission Complete */
+#define USART_SR_TXE 0x0080U /*!<Transmit Data Register Empty */
+#define USART_SR_LBD 0x0100U /*!<LIN Break Detection Flag */
+#define USART_SR_CTS 0x0200U /*!<CTS Flag */
+
+/******************* Bit definition for USART_DR register *******************/
+#define USART_DR_DR 0x01FFU /*!<Data value */
+
+/****************** Bit definition for USART_BRR register *******************/
+#define USART_BRR_DIV_Fraction 0x000FU /*!<Fraction of USARTDIV */
+#define USART_BRR_DIV_Mantissa 0xFFF0U /*!<Mantissa of USARTDIV */
+
+/****************** Bit definition for USART_CR1 register *******************/
+#define USART_CR1_SBK 0x0001U /*!<Send Break */
+#define USART_CR1_RWU 0x0002U /*!<Receiver wakeup */
+#define USART_CR1_RE 0x0004U /*!<Receiver Enable */
+#define USART_CR1_TE 0x0008U /*!<Transmitter Enable */
+#define USART_CR1_IDLEIE 0x0010U /*!<IDLE Interrupt Enable */
+#define USART_CR1_RXNEIE 0x0020U /*!<RXNE Interrupt Enable */
+#define USART_CR1_TCIE 0x0040U /*!<Transmission Complete Interrupt Enable */
+#define USART_CR1_TXEIE 0x0080U /*!<PE Interrupt Enable */
+#define USART_CR1_PEIE 0x0100U /*!<PE Interrupt Enable */
+#define USART_CR1_PS 0x0200U /*!<Parity Selection */
+#define USART_CR1_PCE 0x0400U /*!<Parity Control Enable */
+#define USART_CR1_WAKE 0x0800U /*!<Wakeup method */
+#define USART_CR1_M 0x1000U /*!<Word length */
+#define USART_CR1_UE 0x2000U /*!<USART Enable */
+#define USART_CR1_OVER8 0x8000U /*!<USART Oversampling by 8 enable */
+
+/****************** Bit definition for USART_CR2 register *******************/
+#define USART_CR2_ADD 0x000FU /*!<Address of the USART node */
+#define USART_CR2_LBDL 0x0020U /*!<LIN Break Detection Length */
+#define USART_CR2_LBDIE 0x0040U /*!<LIN Break Detection Interrupt Enable */
+#define USART_CR2_LBCL 0x0100U /*!<Last Bit Clock pulse */
+#define USART_CR2_CPHA 0x0200U /*!<Clock Phase */
+#define USART_CR2_CPOL 0x0400U /*!<Clock Polarity */
+#define USART_CR2_CLKEN 0x0800U /*!<Clock Enable */
+
+#define USART_CR2_STOP 0x3000U /*!<STOP[1:0] bits (STOP bits) */
+#define USART_CR2_STOP_0 0x1000U /*!<Bit 0 */
+#define USART_CR2_STOP_1 0x2000U /*!<Bit 1 */
+
+#define USART_CR2_LINEN 0x4000U /*!<LIN mode enable */
+
+/****************** Bit definition for USART_CR3 register *******************/
+#define USART_CR3_EIE 0x0001U /*!<Error Interrupt Enable */
+#define USART_CR3_IREN 0x0002U /*!<IrDA mode Enable */
+#define USART_CR3_IRLP 0x0004U /*!<IrDA Low-Power */
+#define USART_CR3_HDSEL 0x0008U /*!<Half-Duplex Selection */
+#define USART_CR3_NACK 0x0010U /*!<Smartcard NACK enable */
+#define USART_CR3_SCEN 0x0020U /*!<Smartcard mode enable */
+#define USART_CR3_DMAR 0x0040U /*!<DMA Enable Receiver */
+#define USART_CR3_DMAT 0x0080U /*!<DMA Enable Transmitter */
+#define USART_CR3_RTSE 0x0100U /*!<RTS Enable */
+#define USART_CR3_CTSE 0x0200U /*!<CTS Enable */
+#define USART_CR3_CTSIE 0x0400U /*!<CTS Interrupt Enable */
+#define USART_CR3_ONEBIT 0x0800U /*!<USART One bit method enable */
+
+/****************** Bit definition for USART_GTPR register ******************/
+#define USART_GTPR_PSC 0x00FFU /*!<PSC[7:0] bits (Prescaler value) */
+#define USART_GTPR_PSC_0 0x0001U /*!<Bit 0 */
+#define USART_GTPR_PSC_1 0x0002U /*!<Bit 1 */
+#define USART_GTPR_PSC_2 0x0004U /*!<Bit 2 */
+#define USART_GTPR_PSC_3 0x0008U /*!<Bit 3 */
+#define USART_GTPR_PSC_4 0x0010U /*!<Bit 4 */
+#define USART_GTPR_PSC_5 0x0020U /*!<Bit 5 */
+#define USART_GTPR_PSC_6 0x0040U /*!<Bit 6 */
+#define USART_GTPR_PSC_7 0x0080U /*!<Bit 7 */
+
+#define USART_GTPR_GT 0xFF00U /*!<Guard time value */
+
+/******************************************************************************/
+/* */
+/* Window WATCHDOG */
+/* */
+/******************************************************************************/
+/******************* Bit definition for WWDG_CR register ********************/
+#define WWDG_CR_T 0x7FU /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
+#define WWDG_CR_T_0 0x01U /*!<Bit 0 */
+#define WWDG_CR_T_1 0x02U /*!<Bit 1 */
+#define WWDG_CR_T_2 0x04U /*!<Bit 2 */
+#define WWDG_CR_T_3 0x08U /*!<Bit 3 */
+#define WWDG_CR_T_4 0x10U /*!<Bit 4 */
+#define WWDG_CR_T_5 0x20U /*!<Bit 5 */
+#define WWDG_CR_T_6 0x40U /*!<Bit 6 */
+/* Legacy defines */
+#define WWDG_CR_T0 WWDG_CR_T_0
+#define WWDG_CR_T1 WWDG_CR_T_1
+#define WWDG_CR_T2 WWDG_CR_T_2
+#define WWDG_CR_T3 WWDG_CR_T_3
+#define WWDG_CR_T4 WWDG_CR_T_4
+#define WWDG_CR_T5 WWDG_CR_T_5
+#define WWDG_CR_T6 WWDG_CR_T_6
+
+#define WWDG_CR_WDGA 0x80U /*!<Activation bit */
+
+/******************* Bit definition for WWDG_CFR register *******************/
+#define WWDG_CFR_W 0x007FU /*!<W[6:0] bits (7-bit window value) */
+#define WWDG_CFR_W_0 0x0001U /*!<Bit 0 */
+#define WWDG_CFR_W_1 0x0002U /*!<Bit 1 */
+#define WWDG_CFR_W_2 0x0004U /*!<Bit 2 */
+#define WWDG_CFR_W_3 0x0008U /*!<Bit 3 */
+#define WWDG_CFR_W_4 0x0010U /*!<Bit 4 */
+#define WWDG_CFR_W_5 0x0020U /*!<Bit 5 */
+#define WWDG_CFR_W_6 0x0040U /*!<Bit 6 */
+/* Legacy defines */
+#define WWDG_CFR_W0 WWDG_CFR_W_0
+#define WWDG_CFR_W1 WWDG_CFR_W_1
+#define WWDG_CFR_W2 WWDG_CFR_W_2
+#define WWDG_CFR_W3 WWDG_CFR_W_3
+#define WWDG_CFR_W4 WWDG_CFR_W_4
+#define WWDG_CFR_W5 WWDG_CFR_W_5
+#define WWDG_CFR_W6 WWDG_CFR_W_6
+
+#define WWDG_CFR_WDGTB 0x0180U /*!<WDGTB[1:0] bits (Timer Base) */
+#define WWDG_CFR_WDGTB_0 0x0080U /*!<Bit 0 */
+#define WWDG_CFR_WDGTB_1 0x0100U /*!<Bit 1 */
+/* Legacy defines */
+#define WWDG_CFR_WDGTB0 WWDG_CFR_WDGTB_0
+#define WWDG_CFR_WDGTB1 WWDG_CFR_WDGTB_1
+
+#define WWDG_CFR_EWI 0x0200U /*!<Early Wakeup Interrupt */
+
+/******************* Bit definition for WWDG_SR register ********************/
+#define WWDG_SR_EWIF 0x01U /*!<Early Wakeup Interrupt Flag */
+
+
+/******************************************************************************/
+/* */
+/* DBG */
+/* */
+/******************************************************************************/
+/******************** Bit definition for DBGMCU_IDCODE register *************/
+#define DBGMCU_IDCODE_DEV_ID 0x00000FFFU
+#define DBGMCU_IDCODE_REV_ID 0xFFFF0000U
+
+/******************** Bit definition for DBGMCU_CR register *****************/
+#define DBGMCU_CR_DBG_SLEEP 0x00000001U
+#define DBGMCU_CR_DBG_STOP 0x00000002U
+#define DBGMCU_CR_DBG_STANDBY 0x00000004U
+#define DBGMCU_CR_TRACE_IOEN 0x00000020U
+
+#define DBGMCU_CR_TRACE_MODE 0x000000C0U
+#define DBGMCU_CR_TRACE_MODE_0 0x00000040U/*!<Bit 0 */
+#define DBGMCU_CR_TRACE_MODE_1 0x00000080U/*!<Bit 1 */
+
+/******************** Bit definition for DBGMCU_APB1_FZ register ************/
+#define DBGMCU_APB1_FZ_DBG_TIM2_STOP 0x00000001U
+#define DBGMCU_APB1_FZ_DBG_TIM3_STOP 0x00000002U
+#define DBGMCU_APB1_FZ_DBG_TIM4_STOP 0x00000004U
+#define DBGMCU_APB1_FZ_DBG_TIM5_STOP 0x00000008U
+#define DBGMCU_APB1_FZ_DBG_TIM6_STOP 0x00000010U
+#define DBGMCU_APB1_FZ_DBG_TIM7_STOP 0x00000020U
+#define DBGMCU_APB1_FZ_DBG_TIM12_STOP 0x00000040U
+#define DBGMCU_APB1_FZ_DBG_TIM13_STOP 0x00000080U
+#define DBGMCU_APB1_FZ_DBG_TIM14_STOP 0x00000100U
+#define DBGMCU_APB1_FZ_DBG_RTC_STOP 0x00000400U
+#define DBGMCU_APB1_FZ_DBG_WWDG_STOP 0x00000800U
+#define DBGMCU_APB1_FZ_DBG_IWDG_STOP 0x00001000U
+#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT 0x00200000U
+#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT 0x00400000U
+#define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT 0x00800000U
+#define DBGMCU_APB1_FZ_DBG_CAN1_STOP 0x02000000U
+#define DBGMCU_APB1_FZ_DBG_CAN2_STOP 0x04000000U
+
+/******************** Bit definition for DBGMCU_APB2_FZ register ************/
+#define DBGMCU_APB2_FZ_DBG_TIM1_STOP 0x00000001U
+#define DBGMCU_APB2_FZ_DBG_TIM8_STOP 0x00000002U
+#define DBGMCU_APB2_FZ_DBG_TIM9_STOP 0x00010000U
+#define DBGMCU_APB2_FZ_DBG_TIM10_STOP 0x00020000U
+#define DBGMCU_APB2_FZ_DBG_TIM11_STOP 0x00040000U
+
+/******************************************************************************/
+/* */
+/* USB_OTG */
+/* */
+/******************************************************************************/
+/******************** Bit definition for USB_OTG_GOTGCTL register ***********/
+#define USB_OTG_GOTGCTL_SRQSCS 0x00000001U /*!< Session request success */
+#define USB_OTG_GOTGCTL_SRQ 0x00000002U /*!< Session request */
+#define USB_OTG_GOTGCTL_VBVALOEN 0x00000004U /*!< VBUS valid override enable */
+#define USB_OTG_GOTGCTL_VBVALOVAL 0x00000008U /*!< VBUS valid override value */
+#define USB_OTG_GOTGCTL_AVALOEN 0x00000010U /*!< A-peripheral session valid override enable */
+#define USB_OTG_GOTGCTL_AVALOVAL 0x00000020U /*!< A-peripheral session valid override value */
+#define USB_OTG_GOTGCTL_BVALOEN 0x00000040U /*!< B-peripheral session valid override enable */
+#define USB_OTG_GOTGCTL_BVALOVAL 0x00000080U /*!< B-peripheral session valid override value */
+#define USB_OTG_GOTGCTL_HNGSCS 0x00000100U /*!< Host set HNP enable */
+#define USB_OTG_GOTGCTL_HNPRQ 0x00000200U /*!< HNP request */
+#define USB_OTG_GOTGCTL_HSHNPEN 0x00000400U /*!< Host set HNP enable */
+#define USB_OTG_GOTGCTL_DHNPEN 0x00000800U /*!< Device HNP enabled */
+#define USB_OTG_GOTGCTL_EHEN 0x00001000U /*!< Embedded host enable */
+#define USB_OTG_GOTGCTL_CIDSTS 0x00010000U /*!< Connector ID status */
+#define USB_OTG_GOTGCTL_DBCT 0x00020000U /*!< Long/short debounce time */
+#define USB_OTG_GOTGCTL_ASVLD 0x00040000U /*!< A-session valid */
+#define USB_OTG_GOTGCTL_BSESVLD 0x00080000U /*!< B-session valid */
+#define USB_OTG_GOTGCTL_OTGVER 0x00100000U /*!< OTG version */
+
+/******************** Bit definition for USB_OTG_HCFG register **************/
+
+#define USB_OTG_HCFG_FSLSPCS 0x00000003U /*!< FS/LS PHY clock select */
+#define USB_OTG_HCFG_FSLSPCS_0 0x00000001U /*!<Bit 0 */
+#define USB_OTG_HCFG_FSLSPCS_1 0x00000002U /*!<Bit 1 */
+#define USB_OTG_HCFG_FSLSS 0x00000004U /*!< FS- and LS-only support */
+
+/******************** Bit definition for USB_OTG_DCFG register **************/
+
+#define USB_OTG_DCFG_DSPD 0x00000003U /*!< Device speed */
+#define USB_OTG_DCFG_DSPD_0 0x00000001U /*!<Bit 0 */
+#define USB_OTG_DCFG_DSPD_1 0x00000002U /*!<Bit 1 */
+#define USB_OTG_DCFG_NZLSOHSK 0x00000004U /*!< Nonzero-length status OUT handshake */
+
+#define USB_OTG_DCFG_DAD 0x000007F0U /*!< Device address */
+#define USB_OTG_DCFG_DAD_0 0x00000010U /*!<Bit 0 */
+#define USB_OTG_DCFG_DAD_1 0x00000020U /*!<Bit 1 */
+#define USB_OTG_DCFG_DAD_2 0x00000040U /*!<Bit 2 */
+#define USB_OTG_DCFG_DAD_3 0x00000080U /*!<Bit 3 */
+#define USB_OTG_DCFG_DAD_4 0x00000100U /*!<Bit 4 */
+#define USB_OTG_DCFG_DAD_5 0x00000200U /*!<Bit 5 */
+#define USB_OTG_DCFG_DAD_6 0x00000400U /*!<Bit 6 */
+
+#define USB_OTG_DCFG_PFIVL 0x00001800U /*!< Periodic (micro)frame interval */
+#define USB_OTG_DCFG_PFIVL_0 0x00000800U /*!<Bit 0 */
+#define USB_OTG_DCFG_PFIVL_1 0x00001000U /*!<Bit 1 */
+
+#define USB_OTG_DCFG_PERSCHIVL 0x03000000U /*!< Periodic scheduling interval */
+#define USB_OTG_DCFG_PERSCHIVL_0 0x01000000U /*!<Bit 0 */
+#define USB_OTG_DCFG_PERSCHIVL_1 0x02000000U /*!<Bit 1 */
+
+/******************** Bit definition for USB_OTG_PCGCR register *************/
+#define USB_OTG_PCGCR_STPPCLK 0x00000001U /*!< Stop PHY clock */
+#define USB_OTG_PCGCR_GATEHCLK 0x00000002U /*!< Gate HCLK */
+#define USB_OTG_PCGCR_PHYSUSP 0x00000010U /*!< PHY suspended */
+
+/******************** Bit definition for USB_OTG_GOTGINT register ***********/
+#define USB_OTG_GOTGINT_SEDET 0x00000004U /*!< Session end detected */
+#define USB_OTG_GOTGINT_SRSSCHG 0x00000100U /*!< Session request success status change */
+#define USB_OTG_GOTGINT_HNSSCHG 0x00000200U /*!< Host negotiation success status change */
+#define USB_OTG_GOTGINT_HNGDET 0x00020000U /*!< Host negotiation detected */
+#define USB_OTG_GOTGINT_ADTOCHG 0x00040000U /*!< A-device timeout change */
+#define USB_OTG_GOTGINT_DBCDNE 0x00080000U /*!< Debounce done */
+#define USB_OTG_GOTGINT_IDCHNG 0x00100000U /*!< Change in ID pin input value */
+
+/******************** Bit definition for USB_OTG_DCTL register **************/
+#define USB_OTG_DCTL_RWUSIG 0x00000001U /*!< Remote wakeup signaling */
+#define USB_OTG_DCTL_SDIS 0x00000002U /*!< Soft disconnect */
+#define USB_OTG_DCTL_GINSTS 0x00000004U /*!< Global IN NAK status */
+#define USB_OTG_DCTL_GONSTS 0x00000008U /*!< Global OUT NAK status */
+#define USB_OTG_DCTL_TCTL 0x00000070U /*!< Test control */
+#define USB_OTG_DCTL_TCTL_0 0x00000010U /*!<Bit 0 */
+#define USB_OTG_DCTL_TCTL_1 0x00000020U /*!<Bit 1 */
+#define USB_OTG_DCTL_TCTL_2 0x00000040U /*!<Bit 2 */
+#define USB_OTG_DCTL_SGINAK 0x00000080U /*!< Set global IN NAK */
+#define USB_OTG_DCTL_CGINAK 0x00000100U /*!< Clear global IN NAK */
+#define USB_OTG_DCTL_SGONAK 0x00000200U /*!< Set global OUT NAK */
+#define USB_OTG_DCTL_CGONAK 0x00000400U /*!< Clear global OUT NAK */
+#define USB_OTG_DCTL_POPRGDNE 0x00000800U /*!< Power-on programming done */
+
+/******************** Bit definition for USB_OTG_HFIR register **************/
+#define USB_OTG_HFIR_FRIVL 0x0000FFFFU /*!< Frame interval */
+
+/******************** Bit definition for USB_OTG_HFNUM register *************/
+#define USB_OTG_HFNUM_FRNUM 0x0000FFFFU /*!< Frame number */
+#define USB_OTG_HFNUM_FTREM 0xFFFF0000U /*!< Frame time remaining */
+
+/******************** Bit definition for USB_OTG_DSTS register **************/
+#define USB_OTG_DSTS_SUSPSTS 0x00000001U /*!< Suspend status */
+
+#define USB_OTG_DSTS_ENUMSPD 0x00000006U /*!< Enumerated speed */
+#define USB_OTG_DSTS_ENUMSPD_0 0x00000002U /*!<Bit 0 */
+#define USB_OTG_DSTS_ENUMSPD_1 0x00000004U /*!<Bit 1 */
+#define USB_OTG_DSTS_EERR 0x00000008U /*!< Erratic error */
+#define USB_OTG_DSTS_FNSOF 0x003FFF00U /*!< Frame number of the received SOF */
+
+/******************** Bit definition for USB_OTG_GAHBCFG register ***********/
+#define USB_OTG_GAHBCFG_GINT 0x00000001U /*!< Global interrupt mask */
+#define USB_OTG_GAHBCFG_HBSTLEN 0x0000001EU /*!< Burst length/type */
+#define USB_OTG_GAHBCFG_HBSTLEN_0 0x00000002U /*!<Bit 0 */
+#define USB_OTG_GAHBCFG_HBSTLEN_1 0x00000004U /*!<Bit 1 */
+#define USB_OTG_GAHBCFG_HBSTLEN_2 0x00000008U /*!<Bit 2 */
+#define USB_OTG_GAHBCFG_HBSTLEN_3 0x00000010U /*!<Bit 3 */
+#define USB_OTG_GAHBCFG_DMAEN 0x00000020U /*!< DMA enable */
+#define USB_OTG_GAHBCFG_TXFELVL 0x00000080U /*!< TxFIFO empty level */
+#define USB_OTG_GAHBCFG_PTXFELVL 0x00000100U /*!< Periodic TxFIFO empty level */
+
+/******************** Bit definition for USB_OTG_GUSBCFG register ***********/
+#define USB_OTG_GUSBCFG_TOCAL 0x00000007U /*!< FS timeout calibration */
+#define USB_OTG_GUSBCFG_TOCAL_0 0x00000001U /*!<Bit 0 */
+#define USB_OTG_GUSBCFG_TOCAL_1 0x00000002U /*!<Bit 1 */
+#define USB_OTG_GUSBCFG_TOCAL_2 0x00000004U /*!<Bit 2 */
+#define USB_OTG_GUSBCFG_PHYSEL 0x00000040U /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */
+#define USB_OTG_GUSBCFG_SRPCAP 0x00000100U /*!< SRP-capable */
+#define USB_OTG_GUSBCFG_HNPCAP 0x00000200U /*!< HNP-capable */
+
+#define USB_OTG_GUSBCFG_TRDT 0x00003C00U /*!< USB turnaround time */
+#define USB_OTG_GUSBCFG_TRDT_0 0x00000400U /*!<Bit 0 */
+#define USB_OTG_GUSBCFG_TRDT_1 0x00000800U /*!<Bit 1 */
+#define USB_OTG_GUSBCFG_TRDT_2 0x00001000U /*!<Bit 2 */
+#define USB_OTG_GUSBCFG_TRDT_3 0x00002000U /*!<Bit 3 */
+#define USB_OTG_GUSBCFG_PHYLPCS 0x00008000U /*!< PHY Low-power clock select */
+#define USB_OTG_GUSBCFG_ULPIFSLS 0x00020000U /*!< ULPI FS/LS select */
+#define USB_OTG_GUSBCFG_ULPIAR 0x00040000U /*!< ULPI Auto-resume */
+#define USB_OTG_GUSBCFG_ULPICSM 0x00080000U /*!< ULPI Clock SuspendM */
+#define USB_OTG_GUSBCFG_ULPIEVBUSD 0x00100000U /*!< ULPI External VBUS Drive */
+#define USB_OTG_GUSBCFG_ULPIEVBUSI 0x00200000U /*!< ULPI external VBUS indicator */
+#define USB_OTG_GUSBCFG_TSDPS 0x00400000U /*!< TermSel DLine pulsing selection */
+#define USB_OTG_GUSBCFG_PCCI 0x00800000U /*!< Indicator complement */
+#define USB_OTG_GUSBCFG_PTCI 0x01000000U /*!< Indicator pass through */
+#define USB_OTG_GUSBCFG_ULPIIPD 0x02000000U /*!< ULPI interface protect disable */
+#define USB_OTG_GUSBCFG_FHMOD 0x20000000U /*!< Forced host mode */
+#define USB_OTG_GUSBCFG_FDMOD 0x40000000U /*!< Forced peripheral mode */
+#define USB_OTG_GUSBCFG_CTXPKT 0x80000000U /*!< Corrupt Tx packet */
+
+/******************** Bit definition for USB_OTG_GRSTCTL register ***********/
+#define USB_OTG_GRSTCTL_CSRST 0x00000001U /*!< Core soft reset */
+#define USB_OTG_GRSTCTL_HSRST 0x00000002U /*!< HCLK soft reset */
+#define USB_OTG_GRSTCTL_FCRST 0x00000004U /*!< Host frame counter reset */
+#define USB_OTG_GRSTCTL_RXFFLSH 0x00000010U /*!< RxFIFO flush */
+#define USB_OTG_GRSTCTL_TXFFLSH 0x00000020U /*!< TxFIFO flush */
+
+#define USB_OTG_GRSTCTL_TXFNUM 0x000007C0U /*!< TxFIFO number */
+#define USB_OTG_GRSTCTL_TXFNUM_0 0x00000040U /*!<Bit 0 */
+#define USB_OTG_GRSTCTL_TXFNUM_1 0x00000080U /*!<Bit 1 */
+#define USB_OTG_GRSTCTL_TXFNUM_2 0x00000100U /*!<Bit 2 */
+#define USB_OTG_GRSTCTL_TXFNUM_3 0x00000200U /*!<Bit 3 */
+#define USB_OTG_GRSTCTL_TXFNUM_4 0x00000400U /*!<Bit 4 */
+#define USB_OTG_GRSTCTL_DMAREQ 0x40000000U /*!< DMA request signal */
+#define USB_OTG_GRSTCTL_AHBIDL 0x80000000U /*!< AHB master idle */
+
+/******************** Bit definition for USB_OTG_DIEPMSK register ***********/
+#define USB_OTG_DIEPMSK_XFRCM 0x00000001U /*!< Transfer completed interrupt mask */
+#define USB_OTG_DIEPMSK_EPDM 0x00000002U /*!< Endpoint disabled interrupt mask */
+#define USB_OTG_DIEPMSK_TOM 0x00000008U /*!< Timeout condition mask (nonisochronous endpoints) */
+#define USB_OTG_DIEPMSK_ITTXFEMSK 0x00000010U /*!< IN token received when TxFIFO empty mask */
+#define USB_OTG_DIEPMSK_INEPNMM 0x00000020U /*!< IN token received with EP mismatch mask */
+#define USB_OTG_DIEPMSK_INEPNEM 0x00000040U /*!< IN endpoint NAK effective mask */
+#define USB_OTG_DIEPMSK_TXFURM 0x00000100U /*!< FIFO underrun mask */
+#define USB_OTG_DIEPMSK_BIM 0x00000200U /*!< BNA interrupt mask */
+
+/******************** Bit definition for USB_OTG_HPTXSTS register ***********/
+#define USB_OTG_HPTXSTS_PTXFSAVL 0x0000FFFFU /*!< Periodic transmit data FIFO space available */
+
+#define USB_OTG_HPTXSTS_PTXQSAV 0x00FF0000U /*!< Periodic transmit request queue space available */
+#define USB_OTG_HPTXSTS_PTXQSAV_0 0x00010000U /*!<Bit 0 */
+#define USB_OTG_HPTXSTS_PTXQSAV_1 0x00020000U /*!<Bit 1 */
+#define USB_OTG_HPTXSTS_PTXQSAV_2 0x00040000U /*!<Bit 2 */
+#define USB_OTG_HPTXSTS_PTXQSAV_3 0x00080000U /*!<Bit 3 */
+#define USB_OTG_HPTXSTS_PTXQSAV_4 0x00100000U /*!<Bit 4 */
+#define USB_OTG_HPTXSTS_PTXQSAV_5 0x00200000U /*!<Bit 5 */
+#define USB_OTG_HPTXSTS_PTXQSAV_6 0x00400000U /*!<Bit 6 */
+#define USB_OTG_HPTXSTS_PTXQSAV_7 0x00800000U /*!<Bit 7 */
+
+#define USB_OTG_HPTXSTS_PTXQTOP 0xFF000000U /*!< Top of the periodic transmit request queue */
+#define USB_OTG_HPTXSTS_PTXQTOP_0 0x01000000U /*!<Bit 0 */
+#define USB_OTG_HPTXSTS_PTXQTOP_1 0x02000000U /*!<Bit 1 */
+#define USB_OTG_HPTXSTS_PTXQTOP_2 0x04000000U /*!<Bit 2 */
+#define USB_OTG_HPTXSTS_PTXQTOP_3 0x08000000U /*!<Bit 3 */
+#define USB_OTG_HPTXSTS_PTXQTOP_4 0x10000000U /*!<Bit 4 */
+#define USB_OTG_HPTXSTS_PTXQTOP_5 0x20000000U /*!<Bit 5 */
+#define USB_OTG_HPTXSTS_PTXQTOP_6 0x40000000U /*!<Bit 6 */
+#define USB_OTG_HPTXSTS_PTXQTOP_7 0x80000000U /*!<Bit 7 */
+
+/******************** Bit definition for USB_OTG_HAINT register *************/
+#define USB_OTG_HAINT_HAINT 0x0000FFFFU /*!< Channel interrupts */
+
+/******************** Bit definition for USB_OTG_DOEPMSK register ***********/
+#define USB_OTG_DOEPMSK_XFRCM 0x00000001U /*!< Transfer completed interrupt mask */
+#define USB_OTG_DOEPMSK_EPDM 0x00000002U /*!< Endpoint disabled interrupt mask */
+#define USB_OTG_DOEPMSK_STUPM 0x00000008U /*!< SETUP phase done mask */
+#define USB_OTG_DOEPMSK_OTEPDM 0x00000010U /*!< OUT token received when endpoint disabled mask */
+#define USB_OTG_DOEPMSK_OTEPSPRM 0x00000020U /*!< Status Phase Received mask */
+#define USB_OTG_DOEPMSK_B2BSTUP 0x00000040U /*!< Back-to-back SETUP packets received mask */
+#define USB_OTG_DOEPMSK_OPEM 0x00000100U /*!< OUT packet error mask */
+#define USB_OTG_DOEPMSK_BOIM 0x00000200U /*!< BNA interrupt mask */
+
+/******************** Bit definition for USB_OTG_GINTSTS register ***********/
+#define USB_OTG_GINTSTS_CMOD 0x00000001U /*!< Current mode of operation */
+#define USB_OTG_GINTSTS_MMIS 0x00000002U /*!< Mode mismatch interrupt */
+#define USB_OTG_GINTSTS_OTGINT 0x00000004U /*!< OTG interrupt */
+#define USB_OTG_GINTSTS_SOF 0x00000008U /*!< Start of frame */
+#define USB_OTG_GINTSTS_RXFLVL 0x00000010U /*!< RxFIFO nonempty */
+#define USB_OTG_GINTSTS_NPTXFE 0x00000020U /*!< Nonperiodic TxFIFO empty */
+#define USB_OTG_GINTSTS_GINAKEFF 0x00000040U /*!< Global IN nonperiodic NAK effective */
+#define USB_OTG_GINTSTS_BOUTNAKEFF 0x00000080U /*!< Global OUT NAK effective */
+#define USB_OTG_GINTSTS_ESUSP 0x00000400U /*!< Early suspend */
+#define USB_OTG_GINTSTS_USBSUSP 0x00000800U /*!< USB suspend */
+#define USB_OTG_GINTSTS_USBRST 0x00001000U /*!< USB reset */
+#define USB_OTG_GINTSTS_ENUMDNE 0x00002000U /*!< Enumeration done */
+#define USB_OTG_GINTSTS_ISOODRP 0x00004000U /*!< Isochronous OUT packet dropped interrupt */
+#define USB_OTG_GINTSTS_EOPF 0x00008000U /*!< End of periodic frame interrupt */
+#define USB_OTG_GINTSTS_IEPINT 0x00040000U /*!< IN endpoint interrupt */
+#define USB_OTG_GINTSTS_OEPINT 0x00080000U /*!< OUT endpoint interrupt */
+#define USB_OTG_GINTSTS_IISOIXFR 0x00100000U /*!< Incomplete isochronous IN transfer */
+#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT 0x00200000U /*!< Incomplete periodic transfer */
+#define USB_OTG_GINTSTS_DATAFSUSP 0x00400000U /*!< Data fetch suspended */
+#define USB_OTG_GINTSTS_RSTDET 0x00800000U /*!< Reset detected interrupt */
+#define USB_OTG_GINTSTS_HPRTINT 0x01000000U /*!< Host port interrupt */
+#define USB_OTG_GINTSTS_HCINT 0x02000000U /*!< Host channels interrupt */
+#define USB_OTG_GINTSTS_PTXFE 0x04000000U /*!< Periodic TxFIFO empty */
+#define USB_OTG_GINTSTS_LPMINT 0x08000000U /*!< LPM interrupt */
+#define USB_OTG_GINTSTS_CIDSCHG 0x10000000U /*!< Connector ID status change */
+#define USB_OTG_GINTSTS_DISCINT 0x20000000U /*!< Disconnect detected interrupt */
+#define USB_OTG_GINTSTS_SRQINT 0x40000000U /*!< Session request/new session detected interrupt */
+#define USB_OTG_GINTSTS_WKUINT 0x80000000U /*!< Resume/remote wakeup detected interrupt */
+
+/******************** Bit definition for USB_OTG_GINTMSK register ***********/
+#define USB_OTG_GINTMSK_MMISM 0x00000002U /*!< Mode mismatch interrupt mask */
+#define USB_OTG_GINTMSK_OTGINT 0x00000004U /*!< OTG interrupt mask */
+#define USB_OTG_GINTMSK_SOFM 0x00000008U /*!< Start of frame mask */
+#define USB_OTG_GINTMSK_RXFLVLM 0x00000010U /*!< Receive FIFO nonempty mask */
+#define USB_OTG_GINTMSK_NPTXFEM 0x00000020U /*!< Nonperiodic TxFIFO empty mask */
+#define USB_OTG_GINTMSK_GINAKEFFM 0x00000040U /*!< Global nonperiodic IN NAK effective mask */
+#define USB_OTG_GINTMSK_GONAKEFFM 0x00000080U /*!< Global OUT NAK effective mask */
+#define USB_OTG_GINTMSK_ESUSPM 0x00000400U /*!< Early suspend mask */
+#define USB_OTG_GINTMSK_USBSUSPM 0x00000800U /*!< USB suspend mask */
+#define USB_OTG_GINTMSK_USBRST 0x00001000U /*!< USB reset mask */
+#define USB_OTG_GINTMSK_ENUMDNEM 0x00002000U /*!< Enumeration done mask */
+#define USB_OTG_GINTMSK_ISOODRPM 0x00004000U /*!< Isochronous OUT packet dropped interrupt mask */
+#define USB_OTG_GINTMSK_EOPFM 0x00008000U /*!< End of periodic frame interrupt mask */
+#define USB_OTG_GINTMSK_EPMISM 0x00020000U /*!< Endpoint mismatch interrupt mask */
+#define USB_OTG_GINTMSK_IEPINT 0x00040000U /*!< IN endpoints interrupt mask */
+#define USB_OTG_GINTMSK_OEPINT 0x00080000U /*!< OUT endpoints interrupt mask */
+#define USB_OTG_GINTMSK_IISOIXFRM 0x00100000U /*!< Incomplete isochronous IN transfer mask */
+#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM 0x00200000U /*!< Incomplete periodic transfer mask */
+#define USB_OTG_GINTMSK_FSUSPM 0x00400000U /*!< Data fetch suspended mask */
+#define USB_OTG_GINTMSK_RSTDETM 0x00800000U /*!< Reset detected interrupt mask */
+#define USB_OTG_GINTMSK_PRTIM 0x01000000U /*!< Host port interrupt mask */
+#define USB_OTG_GINTMSK_HCIM 0x02000000U /*!< Host channels interrupt mask */
+#define USB_OTG_GINTMSK_PTXFEM 0x04000000U /*!< Periodic TxFIFO empty mask */
+#define USB_OTG_GINTMSK_LPMINTM 0x08000000U /*!< LPM interrupt Mask */
+#define USB_OTG_GINTMSK_CIDSCHGM 0x10000000U /*!< Connector ID status change mask */
+#define USB_OTG_GINTMSK_DISCINT 0x20000000U /*!< Disconnect detected interrupt mask */
+#define USB_OTG_GINTMSK_SRQIM 0x40000000U /*!< Session request/new session detected interrupt mask */
+#define USB_OTG_GINTMSK_WUIM 0x80000000U /*!< Resume/remote wakeup detected interrupt mask */
+
+/******************** Bit definition for USB_OTG_DAINT register *************/
+#define USB_OTG_DAINT_IEPINT 0x0000FFFFU /*!< IN endpoint interrupt bits */
+#define USB_OTG_DAINT_OEPINT 0xFFFF0000U /*!< OUT endpoint interrupt bits */
+
+/******************** Bit definition for USB_OTG_HAINTMSK register **********/
+#define USB_OTG_HAINTMSK_HAINTM 0x0000FFFFU /*!< Channel interrupt mask */
+
+/******************** Bit definition for USB_OTG_GRXSTSP register ***********/
+#define USB_OTG_GRXSTSP_EPNUM 0x0000000FU /*!< IN EP interrupt mask bits */
+#define USB_OTG_GRXSTSP_BCNT 0x00007FF0U /*!< OUT EP interrupt mask bits */
+#define USB_OTG_GRXSTSP_DPID 0x00018000U /*!< OUT EP interrupt mask bits */
+#define USB_OTG_GRXSTSP_PKTSTS 0x001E0000U /*!< OUT EP interrupt mask bits */
+
+/******************** Bit definition for USB_OTG_DAINTMSK register **********/
+#define USB_OTG_DAINTMSK_IEPM 0x0000FFFFU /*!< IN EP interrupt mask bits */
+#define USB_OTG_DAINTMSK_OEPM 0xFFFF0000U /*!< OUT EP interrupt mask bits */
+
+/******************** Bit definition for OTG register ***********************/
+
+#define USB_OTG_CHNUM 0x0000000FU /*!< Channel number */
+#define USB_OTG_CHNUM_0 0x00000001U /*!<Bit 0 */
+#define USB_OTG_CHNUM_1 0x00000002U /*!<Bit 1 */
+#define USB_OTG_CHNUM_2 0x00000004U /*!<Bit 2 */
+#define USB_OTG_CHNUM_3 0x00000008U /*!<Bit 3 */
+#define USB_OTG_BCNT 0x00007FF0U /*!< Byte count */
+
+#define USB_OTG_DPID 0x00018000U /*!< Data PID */
+#define USB_OTG_DPID_0 0x00008000U /*!<Bit 0 */
+#define USB_OTG_DPID_1 0x00010000U /*!<Bit 1 */
+
+#define USB_OTG_PKTSTS 0x001E0000U /*!< Packet status */
+#define USB_OTG_PKTSTS_0 0x00020000U /*!<Bit 0 */
+#define USB_OTG_PKTSTS_1 0x00040000U /*!<Bit 1 */
+#define USB_OTG_PKTSTS_2 0x00080000U /*!<Bit 2 */
+#define USB_OTG_PKTSTS_3 0x00100000U /*!<Bit 3 */
+
+#define USB_OTG_EPNUM 0x0000000FU /*!< Endpoint number */
+#define USB_OTG_EPNUM_0 0x00000001U /*!<Bit 0 */
+#define USB_OTG_EPNUM_1 0x00000002U /*!<Bit 1 */
+#define USB_OTG_EPNUM_2 0x00000004U /*!<Bit 2 */
+#define USB_OTG_EPNUM_3 0x00000008U /*!<Bit 3 */
+
+#define USB_OTG_FRMNUM 0x01E00000U /*!< Frame number */
+#define USB_OTG_FRMNUM_0 0x00200000U /*!<Bit 0 */
+#define USB_OTG_FRMNUM_1 0x00400000U /*!<Bit 1 */
+#define USB_OTG_FRMNUM_2 0x00800000U /*!<Bit 2 */
+#define USB_OTG_FRMNUM_3 0x01000000U /*!<Bit 3 */
+
+/******************** Bit definition for OTG register ***********************/
+#define USB_OTG_CHNUM 0x0000000FU /*!< Channel number */
+#define USB_OTG_CHNUM_0 0x00000001U /*!<Bit 0 */
+#define USB_OTG_CHNUM_1 0x00000002U /*!<Bit 1 */
+#define USB_OTG_CHNUM_2 0x00000004U /*!<Bit 2 */
+#define USB_OTG_CHNUM_3 0x00000008U /*!<Bit 3 */
+#define USB_OTG_BCNT 0x00007FF0U /*!< Byte count */
+
+#define USB_OTG_DPID 0x00018000U /*!< Data PID */
+#define USB_OTG_DPID_0 0x00008000U /*!<Bit 0 */
+#define USB_OTG_DPID_1 0x00010000U /*!<Bit 1 */
+
+#define USB_OTG_PKTSTS 0x001E0000U /*!< Packet status */
+#define USB_OTG_PKTSTS_0 0x00020000U /*!<Bit 0 */
+#define USB_OTG_PKTSTS_1 0x00040000U /*!<Bit 1 */
+#define USB_OTG_PKTSTS_2 0x00080000U /*!<Bit 2 */
+#define USB_OTG_PKTSTS_3 0x00100000U /*!<Bit 3 */
+
+#define USB_OTG_EPNUM 0x0000000FU /*!< Endpoint number */
+#define USB_OTG_EPNUM_0 0x00000001U /*!<Bit 0 */
+#define USB_OTG_EPNUM_1 0x00000002U /*!<Bit 1 */
+#define USB_OTG_EPNUM_2 0x00000004U /*!<Bit 2 */
+#define USB_OTG_EPNUM_3 0x00000008U /*!<Bit 3 */
+
+#define USB_OTG_FRMNUM 0x01E00000U /*!< Frame number */
+#define USB_OTG_FRMNUM_0 0x00200000U /*!<Bit 0 */
+#define USB_OTG_FRMNUM_1 0x00400000U /*!<Bit 1 */
+#define USB_OTG_FRMNUM_2 0x00800000U /*!<Bit 2 */
+#define USB_OTG_FRMNUM_3 0x01000000U /*!<Bit 3 */
+
+/******************** Bit definition for USB_OTG_GRXFSIZ register ***********/
+#define USB_OTG_GRXFSIZ_RXFD 0x0000FFFFU /*!< RxFIFO depth */
+
+/******************** Bit definition for USB_OTG_DVBUSDIS register **********/
+#define USB_OTG_DVBUSDIS_VBUSDT 0x0000FFFFU /*!< Device VBUS discharge time */
+
+/******************** Bit definition for OTG register ***********************/
+#define USB_OTG_NPTXFSA 0x0000FFFFU /*!< Nonperiodic transmit RAM start address */
+#define USB_OTG_NPTXFD 0xFFFF0000U /*!< Nonperiodic TxFIFO depth */
+#define USB_OTG_TX0FSA 0x0000FFFFU /*!< Endpoint 0 transmit RAM start address */
+#define USB_OTG_TX0FD 0xFFFF0000U /*!< Endpoint 0 TxFIFO depth */
+
+/******************** Bit definition for USB_OTG_DVBUSPULSE register ********/
+#define USB_OTG_DVBUSPULSE_DVBUSP 0x00000FFFU /*!< Device VBUS pulsing time */
+
+/******************** Bit definition for USB_OTG_GNPTXSTS register **********/
+#define USB_OTG_GNPTXSTS_NPTXFSAV 0x0000FFFFU /*!< Nonperiodic TxFIFO space available */
+
+#define USB_OTG_GNPTXSTS_NPTQXSAV 0x00FF0000U /*!< Nonperiodic transmit request queue space available */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_0 0x00010000U /*!<Bit 0 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_1 0x00020000U /*!<Bit 1 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_2 0x00040000U /*!<Bit 2 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_3 0x00080000U /*!<Bit 3 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_4 0x00100000U /*!<Bit 4 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_5 0x00200000U /*!<Bit 5 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_6 0x00400000U /*!<Bit 6 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_7 0x00800000U /*!<Bit 7 */
+
+#define USB_OTG_GNPTXSTS_NPTXQTOP 0x7F000000U /*!< Top of the nonperiodic transmit request queue */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_0 0x01000000U /*!<Bit 0 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_1 0x02000000U /*!<Bit 1 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_2 0x04000000U /*!<Bit 2 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_3 0x08000000U /*!<Bit 3 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_4 0x10000000U /*!<Bit 4 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_5 0x20000000U /*!<Bit 5 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_6 0x40000000U /*!<Bit 6 */
+
+/******************** Bit definition for USB_OTG_DTHRCTL register ***********/
+#define USB_OTG_DTHRCTL_NONISOTHREN 0x00000001U /*!< Nonisochronous IN endpoints threshold enable */
+#define USB_OTG_DTHRCTL_ISOTHREN 0x00000002U /*!< ISO IN endpoint threshold enable */
+
+#define USB_OTG_DTHRCTL_TXTHRLEN 0x000007FCU /*!< Transmit threshold length */
+#define USB_OTG_DTHRCTL_TXTHRLEN_0 0x00000004U /*!<Bit 0 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_1 0x00000008U /*!<Bit 1 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_2 0x00000010U /*!<Bit 2 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_3 0x00000020U /*!<Bit 3 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_4 0x00000040U /*!<Bit 4 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_5 0x00000080U /*!<Bit 5 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_6 0x00000100U /*!<Bit 6 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_7 0x00000200U /*!<Bit 7 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_8 0x00000400U /*!<Bit 8 */
+#define USB_OTG_DTHRCTL_RXTHREN 0x00010000U /*!< Receive threshold enable */
+
+#define USB_OTG_DTHRCTL_RXTHRLEN 0x03FE0000U /*!< Receive threshold length */
+#define USB_OTG_DTHRCTL_RXTHRLEN_0 0x00020000U /*!<Bit 0 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_1 0x00040000U /*!<Bit 1 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_2 0x00080000U /*!<Bit 2 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_3 0x00100000U /*!<Bit 3 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_4 0x00200000U /*!<Bit 4 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_5 0x00400000U /*!<Bit 5 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_6 0x00800000U /*!<Bit 6 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_7 0x01000000U /*!<Bit 7 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_8 0x02000000U /*!<Bit 8 */
+#define USB_OTG_DTHRCTL_ARPEN 0x08000000U /*!< Arbiter parking enable */
+
+/******************** Bit definition for USB_OTG_DIEPEMPMSK register ********/
+#define USB_OTG_DIEPEMPMSK_INEPTXFEM 0x0000FFFFU /*!< IN EP Tx FIFO empty interrupt mask bits */
+
+/******************** Bit definition for USB_OTG_DEACHINT register **********/
+#define USB_OTG_DEACHINT_IEP1INT 0x00000002U /*!< IN endpoint 1interrupt bit */
+#define USB_OTG_DEACHINT_OEP1INT 0x00020000U /*!< OUT endpoint 1 interrupt bit */
+
+/******************** Bit definition for USB_OTG_GCCFG register *************/
+#define USB_OTG_GCCFG_DCDET 0x00000001U /*!< Data contact detection (DCD) status */
+#define USB_OTG_GCCFG_PDET 0x00000002U /*!< Primary detection (PD) status */
+#define USB_OTG_GCCFG_SDET 0x00000004U /*!< Secondary detection (SD) status */
+#define USB_OTG_GCCFG_PS2DET 0x00000008U /*!< DM pull-up detection status */
+#define USB_OTG_GCCFG_PWRDWN 0x00010000U /*!< Power down */
+#define USB_OTG_GCCFG_BCDEN 0x00020000U /*!< Battery charging detector (BCD) enable */
+#define USB_OTG_GCCFG_DCDEN 0x00040000U /*!< Data contact detection (DCD) mode enable*/
+#define USB_OTG_GCCFG_PDEN 0x00080000U /*!< Primary detection (PD) mode enable*/
+#define USB_OTG_GCCFG_SDEN 0x00100000U /*!< Secondary detection (SD) mode enable */
+#define USB_OTG_GCCFG_VBDEN 0x00200000U /*!< USB VBUS Detection Enable */
+
+/******************** Bit definition for USB_OTG_DEACHINTMSK register *******/
+#define USB_OTG_DEACHINTMSK_IEP1INTM 0x00000002U /*!< IN Endpoint 1 interrupt mask bit */
+#define USB_OTG_DEACHINTMSK_OEP1INTM 0x00020000U /*!< OUT Endpoint 1 interrupt mask bit */
+
+/******************** Bit definition for USB_OTG_CID register ***************/
+#define USB_OTG_CID_PRODUCT_ID 0xFFFFFFFFU /*!< Product ID field */
+
+/******************** Bit definition for USB_OTG_GLPMCFG register ***********/
+#define USB_OTG_GLPMCFG_LPMEN 0x00000001U /*!< LPM support enable */
+#define USB_OTG_GLPMCFG_LPMACK 0x00000002U /*!< LPM Token acknowledge enable */
+#define USB_OTG_GLPMCFG_BESL 0x0000003CU /*!< BESL value received with last ACKed LPM Token */
+#define USB_OTG_GLPMCFG_REMWAKE 0x00000040U /*!< bRemoteWake value received with last ACKed LPM Token */
+#define USB_OTG_GLPMCFG_L1SSEN 0x00000080U /*!< L1 shallow sleep enable */
+#define USB_OTG_GLPMCFG_BESLTHRS 0x00000F00U /*!< BESL threshold */
+#define USB_OTG_GLPMCFG_L1DSEN 0x00001000U /*!< L1 deep sleep enable */
+#define USB_OTG_GLPMCFG_LPMRSP 0x00006000U /*!< LPM response */
+#define USB_OTG_GLPMCFG_SLPSTS 0x00008000U /*!< Port sleep status */
+#define USB_OTG_GLPMCFG_L1RSMOK 0x00010000U /*!< Sleep State Resume OK */
+#define USB_OTG_GLPMCFG_LPMCHIDX 0x001E0000U /*!< LPM Channel Index */
+#define USB_OTG_GLPMCFG_LPMRCNT 0x00E00000U /*!< LPM retry count */
+#define USB_OTG_GLPMCFG_SNDLPM 0x01000000U /*!< Send LPM transaction */
+#define USB_OTG_GLPMCFG_LPMRCNTSTS 0x0E000000U /*!< LPM retry count status */
+#define USB_OTG_GLPMCFG_ENBESL 0x10000000U /*!< Enable best effort service latency */
+
+/******************** Bit definition for USB_OTG_DIEPEACHMSK1 register ******/
+#define USB_OTG_DIEPEACHMSK1_XFRCM 0x00000001U /*!< Transfer completed interrupt mask */
+#define USB_OTG_DIEPEACHMSK1_EPDM 0x00000002U /*!< Endpoint disabled interrupt mask */
+#define USB_OTG_DIEPEACHMSK1_TOM 0x00000008U /*!< Timeout condition mask (nonisochronous endpoints) */
+#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK 0x00000010U /*!< IN token received when TxFIFO empty mask */
+#define USB_OTG_DIEPEACHMSK1_INEPNMM 0x00000020U /*!< IN token received with EP mismatch mask */
+#define USB_OTG_DIEPEACHMSK1_INEPNEM 0x00000040U /*!< IN endpoint NAK effective mask */
+#define USB_OTG_DIEPEACHMSK1_TXFURM 0x00000100U /*!< FIFO underrun mask */
+#define USB_OTG_DIEPEACHMSK1_BIM 0x00000200U /*!< BNA interrupt mask */
+#define USB_OTG_DIEPEACHMSK1_NAKM 0x00002000U /*!< NAK interrupt mask */
+
+/******************** Bit definition for USB_OTG_HPRT register **************/
+#define USB_OTG_HPRT_PCSTS 0x00000001U /*!< Port connect status */
+#define USB_OTG_HPRT_PCDET 0x00000002U /*!< Port connect detected */
+#define USB_OTG_HPRT_PENA 0x00000004U /*!< Port enable */
+#define USB_OTG_HPRT_PENCHNG 0x00000008U /*!< Port enable/disable change */
+#define USB_OTG_HPRT_POCA 0x00000010U /*!< Port overcurrent active */
+#define USB_OTG_HPRT_POCCHNG 0x00000020U /*!< Port overcurrent change */
+#define USB_OTG_HPRT_PRES 0x00000040U /*!< Port resume */
+#define USB_OTG_HPRT_PSUSP 0x00000080U /*!< Port suspend */
+#define USB_OTG_HPRT_PRST 0x00000100U /*!< Port reset */
+
+#define USB_OTG_HPRT_PLSTS 0x00000C00U /*!< Port line status */
+#define USB_OTG_HPRT_PLSTS_0 0x00000400U /*!<Bit 0 */
+#define USB_OTG_HPRT_PLSTS_1 0x00000800U /*!<Bit 1 */
+#define USB_OTG_HPRT_PPWR 0x00001000U /*!< Port power */
+
+#define USB_OTG_HPRT_PTCTL 0x0001E000U /*!< Port test control */
+#define USB_OTG_HPRT_PTCTL_0 0x00002000U /*!<Bit 0 */
+#define USB_OTG_HPRT_PTCTL_1 0x00004000U /*!<Bit 1 */
+#define USB_OTG_HPRT_PTCTL_2 0x00008000U /*!<Bit 2 */
+#define USB_OTG_HPRT_PTCTL_3 0x00010000U /*!<Bit 3 */
+
+#define USB_OTG_HPRT_PSPD 0x00060000U /*!< Port speed */
+#define USB_OTG_HPRT_PSPD_0 0x00020000U /*!<Bit 0 */
+#define USB_OTG_HPRT_PSPD_1 0x00040000U /*!<Bit 1 */
+
+/******************** Bit definition for USB_OTG_DOEPEACHMSK1 register ******/
+#define USB_OTG_DOEPEACHMSK1_XFRCM 0x00000001U /*!< Transfer completed interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_EPDM 0x00000002U /*!< Endpoint disabled interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_TOM 0x00000008U /*!< Timeout condition mask */
+#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK 0x00000010U /*!< IN token received when TxFIFO empty mask */
+#define USB_OTG_DOEPEACHMSK1_INEPNMM 0x00000020U /*!< IN token received with EP mismatch mask */
+#define USB_OTG_DOEPEACHMSK1_INEPNEM 0x00000040U /*!< IN endpoint NAK effective mask */
+#define USB_OTG_DOEPEACHMSK1_TXFURM 0x00000100U /*!< OUT packet error mask */
+#define USB_OTG_DOEPEACHMSK1_BIM 0x00000200U /*!< BNA interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_BERRM 0x00001000U /*!< Bubble error interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_NAKM 0x00002000U /*!< NAK interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_NYETM 0x00004000U /*!< NYET interrupt mask */
+
+/******************** Bit definition for USB_OTG_HPTXFSIZ register **********/
+#define USB_OTG_HPTXFSIZ_PTXSA 0x0000FFFFU /*!< Host periodic TxFIFO start address */
+#define USB_OTG_HPTXFSIZ_PTXFD 0xFFFF0000U /*!< Host periodic TxFIFO depth */
+
+/******************** Bit definition for USB_OTG_DIEPCTL register ***********/
+#define USB_OTG_DIEPCTL_MPSIZ 0x000007FFU /*!< Maximum packet size */
+#define USB_OTG_DIEPCTL_USBAEP 0x00008000U /*!< USB active endpoint */
+#define USB_OTG_DIEPCTL_EONUM_DPID 0x00010000U /*!< Even/odd frame */
+#define USB_OTG_DIEPCTL_NAKSTS 0x00020000U /*!< NAK status */
+
+#define USB_OTG_DIEPCTL_EPTYP 0x000C0000U /*!< Endpoint type */
+#define USB_OTG_DIEPCTL_EPTYP_0 0x00040000U /*!<Bit 0 */
+#define USB_OTG_DIEPCTL_EPTYP_1 0x00080000U /*!<Bit 1 */
+#define USB_OTG_DIEPCTL_STALL 0x00200000U /*!< STALL handshake */
+
+#define USB_OTG_DIEPCTL_TXFNUM 0x03C00000U /*!< TxFIFO number */
+#define USB_OTG_DIEPCTL_TXFNUM_0 0x00400000U /*!<Bit 0 */
+#define USB_OTG_DIEPCTL_TXFNUM_1 0x00800000U /*!<Bit 1 */
+#define USB_OTG_DIEPCTL_TXFNUM_2 0x01000000U /*!<Bit 2 */
+#define USB_OTG_DIEPCTL_TXFNUM_3 0x02000000U /*!<Bit 3 */
+#define USB_OTG_DIEPCTL_CNAK 0x04000000U /*!< Clear NAK */
+#define USB_OTG_DIEPCTL_SNAK 0x08000000U /*!< Set NAK */
+#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM 0x10000000U /*!< Set DATA0 PID */
+#define USB_OTG_DIEPCTL_SODDFRM 0x20000000U /*!< Set odd frame */
+#define USB_OTG_DIEPCTL_EPDIS 0x40000000U /*!< Endpoint disable */
+#define USB_OTG_DIEPCTL_EPENA 0x80000000U /*!< Endpoint enable */
+
+/******************** Bit definition for USB_OTG_HCCHAR register ************/
+#define USB_OTG_HCCHAR_MPSIZ 0x000007FFU /*!< Maximum packet size */
+
+#define USB_OTG_HCCHAR_EPNUM 0x00007800U /*!< Endpoint number */
+#define USB_OTG_HCCHAR_EPNUM_0 0x00000800U /*!<Bit 0 */
+#define USB_OTG_HCCHAR_EPNUM_1 0x00001000U /*!<Bit 1 */
+#define USB_OTG_HCCHAR_EPNUM_2 0x00002000U /*!<Bit 2 */
+#define USB_OTG_HCCHAR_EPNUM_3 0x00004000U /*!<Bit 3 */
+#define USB_OTG_HCCHAR_EPDIR 0x00008000U /*!< Endpoint direction */
+#define USB_OTG_HCCHAR_LSDEV 0x00020000U /*!< Low-speed device */
+
+#define USB_OTG_HCCHAR_EPTYP 0x000C0000U /*!< Endpoint type */
+#define USB_OTG_HCCHAR_EPTYP_0 0x00040000U /*!<Bit 0 */
+#define USB_OTG_HCCHAR_EPTYP_1 0x00080000U /*!<Bit 1 */
+
+#define USB_OTG_HCCHAR_MC 0x00300000U /*!< Multi Count (MC) / Error Count (EC) */
+#define USB_OTG_HCCHAR_MC_0 0x00100000U /*!<Bit 0 */
+#define USB_OTG_HCCHAR_MC_1 0x00200000U /*!<Bit 1 */
+
+#define USB_OTG_HCCHAR_DAD 0x1FC00000U /*!< Device address */
+#define USB_OTG_HCCHAR_DAD_0 0x00400000U /*!<Bit 0 */
+#define USB_OTG_HCCHAR_DAD_1 0x00800000U /*!<Bit 1 */
+#define USB_OTG_HCCHAR_DAD_2 0x01000000U /*!<Bit 2 */
+#define USB_OTG_HCCHAR_DAD_3 0x02000000U /*!<Bit 3 */
+#define USB_OTG_HCCHAR_DAD_4 0x04000000U /*!<Bit 4 */
+#define USB_OTG_HCCHAR_DAD_5 0x08000000U /*!<Bit 5 */
+#define USB_OTG_HCCHAR_DAD_6 0x10000000U /*!<Bit 6 */
+#define USB_OTG_HCCHAR_ODDFRM 0x20000000U /*!< Odd frame */
+#define USB_OTG_HCCHAR_CHDIS 0x40000000U /*!< Channel disable */
+#define USB_OTG_HCCHAR_CHENA 0x80000000U /*!< Channel enable */
+
+/******************** Bit definition for USB_OTG_HCSPLT register ************/
+
+#define USB_OTG_HCSPLT_PRTADDR 0x0000007FU /*!< Port address */
+#define USB_OTG_HCSPLT_PRTADDR_0 0x00000001U /*!<Bit 0 */
+#define USB_OTG_HCSPLT_PRTADDR_1 0x00000002U /*!<Bit 1 */
+#define USB_OTG_HCSPLT_PRTADDR_2 0x00000004U /*!<Bit 2 */
+#define USB_OTG_HCSPLT_PRTADDR_3 0x00000008U /*!<Bit 3 */
+#define USB_OTG_HCSPLT_PRTADDR_4 0x00000010U /*!<Bit 4 */
+#define USB_OTG_HCSPLT_PRTADDR_5 0x00000020U /*!<Bit 5 */
+#define USB_OTG_HCSPLT_PRTADDR_6 0x00000040U /*!<Bit 6 */
+
+#define USB_OTG_HCSPLT_HUBADDR 0x00003F80U /*!< Hub address */
+#define USB_OTG_HCSPLT_HUBADDR_0 0x00000080U /*!<Bit 0 */
+#define USB_OTG_HCSPLT_HUBADDR_1 0x00000100U /*!<Bit 1 */
+#define USB_OTG_HCSPLT_HUBADDR_2 0x00000200U /*!<Bit 2 */
+#define USB_OTG_HCSPLT_HUBADDR_3 0x00000400U /*!<Bit 3 */
+#define USB_OTG_HCSPLT_HUBADDR_4 0x00000800U /*!<Bit 4 */
+#define USB_OTG_HCSPLT_HUBADDR_5 0x00001000U /*!<Bit 5 */
+#define USB_OTG_HCSPLT_HUBADDR_6 0x00002000U /*!<Bit 6 */
+
+#define USB_OTG_HCSPLT_XACTPOS 0x0000C000U /*!< XACTPOS */
+#define USB_OTG_HCSPLT_XACTPOS_0 0x00004000U /*!<Bit 0 */
+#define USB_OTG_HCSPLT_XACTPOS_1 0x00008000U /*!<Bit 1 */
+#define USB_OTG_HCSPLT_COMPLSPLT 0x00010000U /*!< Do complete split */
+#define USB_OTG_HCSPLT_SPLITEN 0x80000000U /*!< Split enable */
+
+/******************** Bit definition for USB_OTG_HCINT register *************/
+#define USB_OTG_HCINT_XFRC 0x00000001U /*!< Transfer completed */
+#define USB_OTG_HCINT_CHH 0x00000002U /*!< Channel halted */
+#define USB_OTG_HCINT_AHBERR 0x00000004U /*!< AHB error */
+#define USB_OTG_HCINT_STALL 0x00000008U /*!< STALL response received interrupt */
+#define USB_OTG_HCINT_NAK 0x00000010U /*!< NAK response received interrupt */
+#define USB_OTG_HCINT_ACK 0x00000020U /*!< ACK response received/transmitted interrupt */
+#define USB_OTG_HCINT_NYET 0x00000040U /*!< Response received interrupt */
+#define USB_OTG_HCINT_TXERR 0x00000080U /*!< Transaction error */
+#define USB_OTG_HCINT_BBERR 0x00000100U /*!< Babble error */
+#define USB_OTG_HCINT_FRMOR 0x00000200U /*!< Frame overrun */
+#define USB_OTG_HCINT_DTERR 0x00000400U /*!< Data toggle error */
+
+/******************** Bit definition for USB_OTG_DIEPINT register ***********/
+#define USB_OTG_DIEPINT_XFRC 0x00000001U /*!< Transfer completed interrupt */
+#define USB_OTG_DIEPINT_EPDISD 0x00000002U /*!< Endpoint disabled interrupt */
+#define USB_OTG_DIEPINT_TOC 0x00000008U /*!< Timeout condition */
+#define USB_OTG_DIEPINT_ITTXFE 0x00000010U /*!< IN token received when TxFIFO is empty */
+#define USB_OTG_DIEPINT_INEPNE 0x00000040U /*!< IN endpoint NAK effective */
+#define USB_OTG_DIEPINT_TXFE 0x00000080U /*!< Transmit FIFO empty */
+#define USB_OTG_DIEPINT_TXFIFOUDRN 0x00000100U /*!< Transmit Fifo Underrun */
+#define USB_OTG_DIEPINT_BNA 0x00000200U /*!< Buffer not available interrupt */
+#define USB_OTG_DIEPINT_PKTDRPSTS 0x00000800U /*!< Packet dropped status */
+#define USB_OTG_DIEPINT_BERR 0x00001000U /*!< Babble error interrupt */
+#define USB_OTG_DIEPINT_NAK 0x00002000U /*!< NAK interrupt */
+
+/******************** Bit definition for USB_OTG_HCINTMSK register **********/
+#define USB_OTG_HCINTMSK_XFRCM 0x00000001U /*!< Transfer completed mask */
+#define USB_OTG_HCINTMSK_CHHM 0x00000002U /*!< Channel halted mask */
+#define USB_OTG_HCINTMSK_AHBERR 0x00000004U /*!< AHB error */
+#define USB_OTG_HCINTMSK_STALLM 0x00000008U /*!< STALL response received interrupt mask */
+#define USB_OTG_HCINTMSK_NAKM 0x00000010U /*!< NAK response received interrupt mask */
+#define USB_OTG_HCINTMSK_ACKM 0x00000020U /*!< ACK response received/transmitted interrupt mask */
+#define USB_OTG_HCINTMSK_NYET 0x00000040U /*!< response received interrupt mask */
+#define USB_OTG_HCINTMSK_TXERRM 0x00000080U /*!< Transaction error mask */
+#define USB_OTG_HCINTMSK_BBERRM 0x00000100U /*!< Babble error mask */
+#define USB_OTG_HCINTMSK_FRMORM 0x00000200U /*!< Frame overrun mask */
+#define USB_OTG_HCINTMSK_DTERRM 0x00000400U /*!< Data toggle error mask */
+
+/******************** Bit definition for USB_OTG_DIEPTSIZ register **********/
+
+#define USB_OTG_DIEPTSIZ_XFRSIZ 0x0007FFFFU /*!< Transfer size */
+#define USB_OTG_DIEPTSIZ_PKTCNT 0x1FF80000U /*!< Packet count */
+#define USB_OTG_DIEPTSIZ_MULCNT 0x60000000U /*!< Packet count */
+/******************** Bit definition for USB_OTG_HCTSIZ register ************/
+#define USB_OTG_HCTSIZ_XFRSIZ 0x0007FFFFU /*!< Transfer size */
+#define USB_OTG_HCTSIZ_PKTCNT 0x1FF80000U /*!< Packet count */
+#define USB_OTG_HCTSIZ_DOPING 0x80000000U /*!< Do PING */
+#define USB_OTG_HCTSIZ_DPID 0x60000000U /*!< Data PID */
+#define USB_OTG_HCTSIZ_DPID_0 0x20000000U /*!<Bit 0 */
+#define USB_OTG_HCTSIZ_DPID_1 0x40000000U /*!<Bit 1 */
+
+/******************** Bit definition for USB_OTG_DIEPDMA register ***********/
+#define USB_OTG_DIEPDMA_DMAADDR 0xFFFFFFFFU /*!< DMA address */
+
+/******************** Bit definition for USB_OTG_HCDMA register *************/
+#define USB_OTG_HCDMA_DMAADDR 0xFFFFFFFFU /*!< DMA address */
+
+/******************** Bit definition for USB_OTG_DTXFSTS register ***********/
+#define USB_OTG_DTXFSTS_INEPTFSAV 0x0000FFFFU /*!< IN endpoint TxFIFO space available */
+
+/******************** Bit definition for USB_OTG_DIEPTXF register ***********/
+#define USB_OTG_DIEPTXF_INEPTXSA 0x0000FFFFU /*!< IN endpoint FIFOx transmit RAM start address */
+#define USB_OTG_DIEPTXF_INEPTXFD 0xFFFF0000U /*!< IN endpoint TxFIFO depth */
+
+/******************** Bit definition for USB_OTG_DOEPCTL register ***********/
+
+#define USB_OTG_DOEPCTL_MPSIZ 0x000007FFU /*!< Maximum packet size */ /*!<Bit 1 */
+#define USB_OTG_DOEPCTL_USBAEP 0x00008000U /*!< USB active endpoint */
+#define USB_OTG_DOEPCTL_NAKSTS 0x00020000U /*!< NAK status */
+#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM 0x10000000U /*!< Set DATA0 PID */
+#define USB_OTG_DOEPCTL_SODDFRM 0x20000000U /*!< Set odd frame */
+#define USB_OTG_DOEPCTL_EPTYP 0x000C0000U /*!< Endpoint type */
+#define USB_OTG_DOEPCTL_EPTYP_0 0x00040000U /*!<Bit 0 */
+#define USB_OTG_DOEPCTL_EPTYP_1 0x00080000U /*!<Bit 1 */
+#define USB_OTG_DOEPCTL_SNPM 0x00100000U /*!< Snoop mode */
+#define USB_OTG_DOEPCTL_STALL 0x00200000U /*!< STALL handshake */
+#define USB_OTG_DOEPCTL_CNAK 0x04000000U /*!< Clear NAK */
+#define USB_OTG_DOEPCTL_SNAK 0x08000000U /*!< Set NAK */
+#define USB_OTG_DOEPCTL_EPDIS 0x40000000U /*!< Endpoint disable */
+#define USB_OTG_DOEPCTL_EPENA 0x80000000U /*!< Endpoint enable */
+
+/******************** Bit definition for USB_OTG_DOEPINT register ***********/
+#define USB_OTG_DOEPINT_XFRC 0x00000001U /*!< Transfer completed interrupt */
+#define USB_OTG_DOEPINT_EPDISD 0x00000002U /*!< Endpoint disabled interrupt */
+#define USB_OTG_DOEPINT_STUP 0x00000008U /*!< SETUP phase done */
+#define USB_OTG_DOEPINT_OTEPDIS 0x00000010U /*!< OUT token received when endpoint disabled */
+#define USB_OTG_DOEPINT_OTEPSPR 0x00000020U /*!< Status Phase Received For Control Write */
+#define USB_OTG_DOEPINT_B2BSTUP 0x00000040U /*!< Back-to-back SETUP packets received */
+#define USB_OTG_DOEPINT_NYET 0x00004000U /*!< NYET interrupt */
+
+/******************** Bit definition for USB_OTG_DOEPTSIZ register **********/
+
+#define USB_OTG_DOEPTSIZ_XFRSIZ 0x0007FFFFU /*!< Transfer size */
+#define USB_OTG_DOEPTSIZ_PKTCNT 0x1FF80000U /*!< Packet count */
+
+#define USB_OTG_DOEPTSIZ_STUPCNT 0x60000000U /*!< SETUP packet count */
+#define USB_OTG_DOEPTSIZ_STUPCNT_0 0x20000000U /*!<Bit 0 */
+#define USB_OTG_DOEPTSIZ_STUPCNT_1 0x40000000U /*!<Bit 1 */
+
+/******************** Bit definition for PCGCCTL register *******************/
+#define USB_OTG_PCGCCTL_STOPCLK 0x00000001U /*!< SETUP packet count */
+#define USB_OTG_PCGCCTL_GATECLK 0x00000002U /*!<Bit 0 */
+#define USB_OTG_PCGCCTL_PHYSUSP 0x00000010U /*!<Bit 1 */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup Exported_macros
+ * @{
+ */
+
+/******************************* ADC Instances ********************************/
+#define IS_ADC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
+
+/******************************* CAN Instances ********************************/
+#define IS_CAN_ALL_INSTANCE(INSTANCE) (((INSTANCE) == CAN1) || \
+ ((INSTANCE) == CAN2))
+/****************************** DFSDM Instances *******************************/
+#define IS_DFSDM_FILTER_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DFSDM1_Filter0) || \
+ ((INSTANCE) == DFSDM1_Filter1))
+
+#define IS_DFSDM_CHANNEL_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DFSDM1_Channel0) || \
+ ((INSTANCE) == DFSDM1_Channel1) || \
+ ((INSTANCE) == DFSDM1_Channel2) || \
+ ((INSTANCE) == DFSDM1_Channel3))
+
+/******************************* CRC Instances ********************************/
+#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
+
+/******************************** DMA Instances *******************************/
+#define IS_DMA_STREAM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0) || \
+ ((INSTANCE) == DMA1_Stream1) || \
+ ((INSTANCE) == DMA1_Stream2) || \
+ ((INSTANCE) == DMA1_Stream3) || \
+ ((INSTANCE) == DMA1_Stream4) || \
+ ((INSTANCE) == DMA1_Stream5) || \
+ ((INSTANCE) == DMA1_Stream6) || \
+ ((INSTANCE) == DMA1_Stream7) || \
+ ((INSTANCE) == DMA2_Stream0) || \
+ ((INSTANCE) == DMA2_Stream1) || \
+ ((INSTANCE) == DMA2_Stream2) || \
+ ((INSTANCE) == DMA2_Stream3) || \
+ ((INSTANCE) == DMA2_Stream4) || \
+ ((INSTANCE) == DMA2_Stream5) || \
+ ((INSTANCE) == DMA2_Stream6) || \
+ ((INSTANCE) == DMA2_Stream7))
+
+/******************************* GPIO Instances *******************************/
+#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
+ ((INSTANCE) == GPIOB) || \
+ ((INSTANCE) == GPIOC) || \
+ ((INSTANCE) == GPIOD) || \
+ ((INSTANCE) == GPIOE) || \
+ ((INSTANCE) == GPIOF) || \
+ ((INSTANCE) == GPIOG) || \
+ ((INSTANCE) == GPIOH))
+
+/******************************** I2C Instances *******************************/
+#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
+ ((INSTANCE) == I2C2) || \
+ ((INSTANCE) == I2C3))
+
+/******************************** I2S Instances *******************************/
+#define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
+ ((INSTANCE) == SPI2) || \
+ ((INSTANCE) == SPI3) || \
+ ((INSTANCE) == SPI4) || \
+ ((INSTANCE) == SPI5))
+
+/*************************** I2S Extended Instances ***************************/
+#define IS_I2S_ALL_INSTANCE_EXT(PERIPH) (((INSTANCE) == SPI2) || \
+ ((INSTANCE) == SPI3) || \
+ ((INSTANCE) == I2S2ext) || \
+ ((INSTANCE) == I2S3ext))
+
+/******************************* RNG Instances ********************************/
+#define IS_RNG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RNG)
+
+/****************************** RTC Instances *********************************/
+#define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
+
+/******************************** SPI Instances *******************************/
+#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
+ ((INSTANCE) == SPI2) || \
+ ((INSTANCE) == SPI3) || \
+ ((INSTANCE) == SPI4) || \
+ ((INSTANCE) == SPI5))
+/*************************** SPI Extended Instances ***************************/
+#define IS_SPI_ALL_INSTANCE_EXT(INSTANCE) (((INSTANCE) == SPI1) || \
+ ((INSTANCE) == SPI2) || \
+ ((INSTANCE) == SPI3) || \
+ ((INSTANCE) == SPI4) || \
+ ((INSTANCE) == SPI5) || \
+ ((INSTANCE) == I2S2ext) || \
+ ((INSTANCE) == I2S3ext))
+
+/****************** TIM Instances : All supported instances *******************/
+#define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM6) || \
+ ((INSTANCE) == TIM7) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM9) || \
+ ((INSTANCE) == TIM10) || \
+ ((INSTANCE) == TIM11) || \
+ ((INSTANCE) == TIM12) || \
+ ((INSTANCE) == TIM13) || \
+ ((INSTANCE) == TIM14))
+
+/************* TIM Instances : at least 1 capture/compare channel *************/
+#define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM9) || \
+ ((INSTANCE) == TIM10) || \
+ ((INSTANCE) == TIM11) || \
+ ((INSTANCE) == TIM12) || \
+ ((INSTANCE) == TIM13) || \
+ ((INSTANCE) == TIM14))
+
+/************ TIM Instances : at least 2 capture/compare channels *************/
+#define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM9) || \
+ ((INSTANCE) == TIM12))
+
+/************ TIM Instances : at least 3 capture/compare channels *************/
+#define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8))
+
+/************ TIM Instances : at least 4 capture/compare channels *************/
+#define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8))
+
+/******************** TIM Instances : Advanced-control timers *****************/
+#define IS_TIM_ADVANCED_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM8))
+
+/******************* TIM Instances : Timer input XOR function *****************/
+#define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8))
+
+/****************** TIM Instances : DMA requests generation (UDE) *************/
+#define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM6) || \
+ ((INSTANCE) == TIM7) || \
+ ((INSTANCE) == TIM8))
+
+/************ TIM Instances : DMA requests generation (CCxDE) *****************/
+#define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8))
+
+/************ TIM Instances : DMA requests generation (COMDE) *****************/
+#define IS_TIM_CCDMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8))
+
+/******************** TIM Instances : DMA burst feature ***********************/
+#define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8))
+
+/****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/
+#define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM6) || \
+ ((INSTANCE) == TIM7) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM9) || \
+ ((INSTANCE) == TIM12))
+
+/*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
+#define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM9) || \
+ ((INSTANCE) == TIM12))
+
+/********************** TIM Instances : 32 bit Counter ************************/
+#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)(((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM5))
+
+/***************** TIM Instances : external trigger input available ************/
+#define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8))
+
+/****************** TIM Instances : remapping capability **********************/
+#define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM11))
+
+/******************* TIM Instances : output(s) available **********************/
+#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
+ ((((INSTANCE) == TIM1) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM2) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM3) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM4) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM5) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM8) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM9) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2))) \
+ || \
+ (((INSTANCE) == TIM10) && \
+ (((CHANNEL) == TIM_CHANNEL_1))) \
+ || \
+ (((INSTANCE) == TIM11) && \
+ (((CHANNEL) == TIM_CHANNEL_1))) \
+ || \
+ (((INSTANCE) == TIM12) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2))) \
+ || \
+ (((INSTANCE) == TIM13) && \
+ (((CHANNEL) == TIM_CHANNEL_1))) \
+ || \
+ (((INSTANCE) == TIM14) && \
+ (((CHANNEL) == TIM_CHANNEL_1))))
+
+/************ TIM Instances : complementary output(s) available ***************/
+#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
+ ((((INSTANCE) == TIM1) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3))) \
+ || \
+ (((INSTANCE) == TIM8) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3))))
+
+/******************** USART Instances : Synchronous mode **********************/
+#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2))
+
+/******************** UART Instances : Asynchronous mode **********************/
+#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART6))
+
+/****************** UART Instances : Hardware Flow control ********************/
+#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2))
+
+/********************* UART Instances : Smart card mode ***********************/
+#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART6))
+
+/*********************** UART Instances : IRDA mode ***************************/
+#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART6))
+
+/*********************** PCD Instances ****************************************/
+#define IS_PCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS))
+
+/*********************** HCD Instances ****************************************/
+#define IS_HCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS))
+
+/****************************** IWDG Instances ********************************/
+#define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
+
+/****************************** WWDG Instances ********************************/
+#define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
+
+/***************************** FMPI2C Instances *******************************/
+#define IS_FMPI2C_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == FMPI2C1)
+
+/****************************** SDIO Instances ********************************/
+#define IS_SDIO_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SDIO)
+
+/****************************** USB Instances ********************************/
+#define IS_USB_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB_OTG_FS)
+
+/****************************** USB Exported Constants ************************/
+#define USB_OTG_FS_HOST_MAX_CHANNEL_NBR 12U
+#define USB_OTG_FS_MAX_IN_ENDPOINTS 6U /* Including EP0 */
+#define USB_OTG_FS_MAX_OUT_ENDPOINTS 6U /* Including EP0 */
+#define USB_OTG_FS_TOTAL_FIFO_SIZE 1280U /* in Bytes */
+
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* __STM32F412Cx_H */
+
+
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Device/ST/STM32F4xx/Include/stm32f412rx.h b/Device/ST/STM32F4xx/Include/stm32f412rx.h
new file mode 100644
index 0000000..6af0378
--- /dev/null
+++ b/Device/ST/STM32F4xx/Include/stm32f412rx.h
@@ -0,0 +1,7388 @@
+/**
+ ******************************************************************************
+ * @file stm32f412rx.h
+ * @author MCD Application Team
+ * @version V2.5.0
+ * @date 22-April-2016
+ * @brief CMSIS STM32F412Rx Device Peripheral Access Layer Header File.
+ *
+ * This file contains:
+ * - Data structures and the address mapping for all peripherals
+ * - peripherals registers declarations and bits definition
+ * - Macros to access peripheral’s registers hardware
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/** @addtogroup CMSIS
+ * @{
+ */
+
+/** @addtogroup stm32f412rx
+ * @{
+ */
+
+#ifndef __STM32F412Rx_H
+#define __STM32F412Rx_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif /* __cplusplus */
+
+
+/** @addtogroup Configuration_section_for_CMSIS
+ * @{
+ */
+
+/**
+ * @brief Configuration of the Cortex-M4 Processor and Core Peripherals
+ */
+#define __CM4_REV 0x0001U /*!< Core revision r0p1 */
+#define __MPU_PRESENT 1U /*!< STM32F4XX provides an MPU */
+#define __NVIC_PRIO_BITS 4U /*!< STM32F4XX uses 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */
+#define __FPU_PRESENT 1U /*!< FPU present */
+
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_interrupt_number_definition
+ * @{
+ */
+
+/**
+ * @brief STM32F4XX Interrupt Number Definition, according to the selected device
+ * in @ref Library_configuration_section
+ */
+typedef enum
+{
+/****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/
+ NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
+ MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */
+ BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */
+ UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */
+ SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */
+ DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */
+ PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */
+ SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */
+/****** STM32 specific Interrupt Numbers **********************************************************************/
+ WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
+ PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */
+ TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */
+ RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */
+ FLASH_IRQn = 4, /*!< FLASH global Interrupt */
+ RCC_IRQn = 5, /*!< RCC global Interrupt */
+ EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */
+ EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */
+ EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */
+ EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */
+ EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */
+ DMA1_Stream0_IRQn = 11, /*!< DMA1 Stream 0 global Interrupt */
+ DMA1_Stream1_IRQn = 12, /*!< DMA1 Stream 1 global Interrupt */
+ DMA1_Stream2_IRQn = 13, /*!< DMA1 Stream 2 global Interrupt */
+ DMA1_Stream3_IRQn = 14, /*!< DMA1 Stream 3 global Interrupt */
+ DMA1_Stream4_IRQn = 15, /*!< DMA1 Stream 4 global Interrupt */
+ DMA1_Stream5_IRQn = 16, /*!< DMA1 Stream 5 global Interrupt */
+ DMA1_Stream6_IRQn = 17, /*!< DMA1 Stream 6 global Interrupt */
+ ADC_IRQn = 18, /*!< ADC1 global Interrupts */
+ CAN1_TX_IRQn = 19, /*!< CAN1 TX Interrupt */
+ CAN1_RX0_IRQn = 20, /*!< CAN1 RX0 Interrupt */
+ CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */
+ CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */
+ EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
+ TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break interrupt and TIM9 global interrupt */
+ TIM1_UP_TIM10_IRQn = 25, /*!< TIM1 Update Interrupt and TIM10 global interrupt */
+ TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */
+ TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
+ TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
+ TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
+ TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
+ I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
+ I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
+ I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
+ I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
+ SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
+ SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
+ USART1_IRQn = 37, /*!< USART1 global Interrupt */
+ USART2_IRQn = 38, /*!< USART2 global Interrupt */
+ USART3_IRQn = 39, /*!< USART3 global Interrupt */
+ EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
+ RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */
+ OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS Wakeup through EXTI line interrupt */
+ TIM8_BRK_TIM12_IRQn = 43, /*!< TIM8 Break Interrupt and TIM12 global interrupt */
+ TIM8_UP_TIM13_IRQn = 44, /*!< TIM8 Update Interrupt and TIM13 global interrupt */
+ TIM8_TRG_COM_TIM14_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */
+ TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */
+ DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */
+ SDIO_IRQn = 49, /*!< SDIO global Interrupt */
+ TIM5_IRQn = 50, /*!< TIM5 global Interrupt */
+ SPI3_IRQn = 51, /*!< SPI3 global Interrupt */
+ TIM6_IRQn = 54, /*!< TIM6 global interrupt */
+ TIM7_IRQn = 55, /*!< TIM7 global interrupt */
+ DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */
+ DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */
+ DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */
+ DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */
+ DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */
+ DFSDM1_FLT0_IRQn = 61, /*!< DFSDM1 Filter 0 global Interrupt */
+ DFSDM1_FLT1_IRQn = 62, /*!< DFSDM1 Filter 1 global Interrupt */
+ CAN2_TX_IRQn = 63, /*!< CAN2 TX Interrupt */
+ CAN2_RX0_IRQn = 64, /*!< CAN2 RX0 Interrupt */
+ CAN2_RX1_IRQn = 65, /*!< CAN2 RX1 Interrupt */
+ CAN2_SCE_IRQn = 66, /*!< CAN2 SCE Interrupt */
+ OTG_FS_IRQn = 67, /*!< USB OTG FS global Interrupt */
+ DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */
+ DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */
+ DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */
+ USART6_IRQn = 71, /*!< USART6 global interrupt */
+ I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */
+ I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */
+ RNG_IRQn = 80, /*!< RNG global Interrupt */
+ FPU_IRQn = 81, /*!< FPU global interrupt */
+ SPI4_IRQn = 84, /*!< SPI4 global Interrupt */
+ SPI5_IRQn = 85, /*!< SPI5 global Interrupt */
+ QUADSPI_IRQn = 92, /*!< QuadSPI global Interrupt */
+ FMPI2C1_EV_IRQn = 95, /*!< FMPI2C1 Event Interrupt */
+ FMPI2C1_ER_IRQn = 96 /*!< FMPI2C1 Error Interrupt */
+} IRQn_Type;
+
+/**
+ * @}
+ */
+
+#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
+#include "system_stm32f4xx.h"
+#include <stdint.h>
+
+/** @addtogroup Peripheral_registers_structures
+ * @{
+ */
+
+/**
+ * @brief Analog to Digital Converter
+ */
+
+typedef struct
+{
+ __IO uint32_t SR; /*!< ADC status register, Address offset: 0x00 */
+ __IO uint32_t CR1; /*!< ADC control register 1, Address offset: 0x04 */
+ __IO uint32_t CR2; /*!< ADC control register 2, Address offset: 0x08 */
+ __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x0C */
+ __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x10 */
+ __IO uint32_t JOFR1; /*!< ADC injected channel data offset register 1, Address offset: 0x14 */
+ __IO uint32_t JOFR2; /*!< ADC injected channel data offset register 2, Address offset: 0x18 */
+ __IO uint32_t JOFR3; /*!< ADC injected channel data offset register 3, Address offset: 0x1C */
+ __IO uint32_t JOFR4; /*!< ADC injected channel data offset register 4, Address offset: 0x20 */
+ __IO uint32_t HTR; /*!< ADC watchdog higher threshold register, Address offset: 0x24 */
+ __IO uint32_t LTR; /*!< ADC watchdog lower threshold register, Address offset: 0x28 */
+ __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x2C */
+ __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x30 */
+ __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x34 */
+ __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x38*/
+ __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x3C */
+ __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x40 */
+ __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x44 */
+ __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x48 */
+ __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x4C */
+} ADC_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1 base address + 0x300 */
+ __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1 base address + 0x304 */
+ __IO uint32_t CDR; /*!< ADC common regular data register for dual
+ AND triple modes, Address offset: ADC1 base address + 0x308 */
+} ADC_Common_TypeDef;
+
+/**
+ * @brief Controller Area Network TxMailBox
+ */
+
+typedef struct
+{
+ __IO uint32_t TIR; /*!< CAN TX mailbox identifier register */
+ __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */
+ __IO uint32_t TDLR; /*!< CAN mailbox data low register */
+ __IO uint32_t TDHR; /*!< CAN mailbox data high register */
+} CAN_TxMailBox_TypeDef;
+
+/**
+ * @brief Controller Area Network FIFOMailBox
+ */
+
+typedef struct
+{
+ __IO uint32_t RIR; /*!< CAN receive FIFO mailbox identifier register */
+ __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */
+ __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */
+ __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */
+} CAN_FIFOMailBox_TypeDef;
+
+/**
+ * @brief Controller Area Network FilterRegister
+ */
+
+typedef struct
+{
+ __IO uint32_t FR1; /*!< CAN Filter bank register 1 */
+ __IO uint32_t FR2; /*!< CAN Filter bank register 1 */
+} CAN_FilterRegister_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t MCR; /*!< CAN master control register, Address offset: 0x00 */
+ __IO uint32_t MSR; /*!< CAN master status register, Address offset: 0x04 */
+ __IO uint32_t TSR; /*!< CAN transmit status register, Address offset: 0x08 */
+ __IO uint32_t RF0R; /*!< CAN receive FIFO 0 register, Address offset: 0x0C */
+ __IO uint32_t RF1R; /*!< CAN receive FIFO 1 register, Address offset: 0x10 */
+ __IO uint32_t IER; /*!< CAN interrupt enable register, Address offset: 0x14 */
+ __IO uint32_t ESR; /*!< CAN error status register, Address offset: 0x18 */
+ __IO uint32_t BTR; /*!< CAN bit timing register, Address offset: 0x1C */
+ uint32_t RESERVED0[88]; /*!< Reserved, 0x020 - 0x17F */
+ CAN_TxMailBox_TypeDef sTxMailBox[3]; /*!< CAN Tx MailBox, Address offset: 0x180 - 0x1AC */
+ CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; /*!< CAN FIFO MailBox, Address offset: 0x1B0 - 0x1CC */
+ uint32_t RESERVED1[12]; /*!< Reserved, 0x1D0 - 0x1FF */
+ __IO uint32_t FMR; /*!< CAN filter master register, Address offset: 0x200 */
+ __IO uint32_t FM1R; /*!< CAN filter mode register, Address offset: 0x204 */
+ uint32_t RESERVED2; /*!< Reserved, 0x208 */
+ __IO uint32_t FS1R; /*!< CAN filter scale register, Address offset: 0x20C */
+ uint32_t RESERVED3; /*!< Reserved, 0x210 */
+ __IO uint32_t FFA1R; /*!< CAN filter FIFO assignment register, Address offset: 0x214 */
+ uint32_t RESERVED4; /*!< Reserved, 0x218 */
+ __IO uint32_t FA1R; /*!< CAN filter activation register, Address offset: 0x21C */
+ uint32_t RESERVED5[8]; /*!< Reserved, 0x220-0x23F */
+ CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register, Address offset: 0x240-0x31C */
+} CAN_TypeDef;
+
+/**
+ * @brief CRC calculation unit
+ */
+
+typedef struct
+{
+ __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
+ __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
+ uint8_t RESERVED0; /*!< Reserved, 0x05 */
+ uint16_t RESERVED1; /*!< Reserved, 0x06 */
+ __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
+}CRC_TypeDef;
+
+/**
+ * @brief DFSDM module registers
+ */
+typedef struct
+{
+ __IO uint32_t FLTCR1; /*!< DFSDM control register1, Address offset: 0x100 */
+ __IO uint32_t FLTCR2; /*!< DFSDM control register2, Address offset: 0x104 */
+ __IO uint32_t FLTISR; /*!< DFSDM interrupt and status register, Address offset: 0x108 */
+ __IO uint32_t FLTICR; /*!< DFSDM interrupt flag clear register, Address offset: 0x10C */
+ __IO uint32_t FLTJCHGR; /*!< DFSDM injected channel group selection register, Address offset: 0x110 */
+ __IO uint32_t FLTFCR; /*!< DFSDM filter control register, Address offset: 0x114 */
+ __IO uint32_t FLTJDATAR; /*!< DFSDM data register for injected group, Address offset: 0x118 */
+ __IO uint32_t FLTRDATAR; /*!< DFSDM data register for regular group, Address offset: 0x11C */
+ __IO uint32_t FLTAWHTR; /*!< DFSDM analog watchdog high threshold register, Address offset: 0x120 */
+ __IO uint32_t FLTAWLTR; /*!< DFSDM analog watchdog low threshold register, Address offset: 0x124 */
+ __IO uint32_t FLTAWSR; /*!< DFSDM analog watchdog status register Address offset: 0x128 */
+ __IO uint32_t FLTAWCFR; /*!< DFSDM analog watchdog clear flag register Address offset: 0x12C */
+ __IO uint32_t FLTEXMAX; /*!< DFSDM extreme detector maximum register, Address offset: 0x130 */
+ __IO uint32_t FLTEXMIN; /*!< DFSDM extreme detector minimum register Address offset: 0x134 */
+ __IO uint32_t FLTCNVTIMR; /*!< DFSDM conversion timer, Address offset: 0x138 */
+} DFSDM_Filter_TypeDef;
+
+/**
+ * @brief DFSDM channel configuration registers
+ */
+typedef struct
+{
+ __IO uint32_t CHCFGR1; /*!< DFSDM channel configuration register1, Address offset: 0x00 */
+ __IO uint32_t CHCFGR2; /*!< DFSDM channel configuration register2, Address offset: 0x04 */
+ __IO uint32_t CHAWSCDR; /*!< DFSDM channel analog watchdog and
+ short circuit detector register, Address offset: 0x08 */
+ __IO uint32_t CHWDATAR; /*!< DFSDM channel watchdog filter data register, Address offset: 0x0C */
+ __IO uint32_t CHDATINR; /*!< DFSDM channel data input register, Address offset: 0x10 */
+} DFSDM_Channel_TypeDef;
+
+/**
+ * @brief Debug MCU
+ */
+typedef struct
+{
+ __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
+ __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
+ __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */
+ __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */
+}DBGMCU_TypeDef;
+
+
+/**
+ * @brief DMA Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< DMA stream x configuration register */
+ __IO uint32_t NDTR; /*!< DMA stream x number of data register */
+ __IO uint32_t PAR; /*!< DMA stream x peripheral address register */
+ __IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */
+ __IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */
+ __IO uint32_t FCR; /*!< DMA stream x FIFO control register */
+} DMA_Stream_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t LISR; /*!< DMA low interrupt status register, Address offset: 0x00 */
+ __IO uint32_t HISR; /*!< DMA high interrupt status register, Address offset: 0x04 */
+ __IO uint32_t LIFCR; /*!< DMA low interrupt flag clear register, Address offset: 0x08 */
+ __IO uint32_t HIFCR; /*!< DMA high interrupt flag clear register, Address offset: 0x0C */
+} DMA_TypeDef;
+
+
+/**
+ * @brief External Interrupt/Event Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t IMR; /*!< EXTI Interrupt mask register, Address offset: 0x00 */
+ __IO uint32_t EMR; /*!< EXTI Event mask register, Address offset: 0x04 */
+ __IO uint32_t RTSR; /*!< EXTI Rising trigger selection register, Address offset: 0x08 */
+ __IO uint32_t FTSR; /*!< EXTI Falling trigger selection register, Address offset: 0x0C */
+ __IO uint32_t SWIER; /*!< EXTI Software interrupt event register, Address offset: 0x10 */
+ __IO uint32_t PR; /*!< EXTI Pending register, Address offset: 0x14 */
+} EXTI_TypeDef;
+
+/**
+ * @brief FLASH Registers
+ */
+
+typedef struct
+{
+ __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */
+ __IO uint32_t KEYR; /*!< FLASH key register, Address offset: 0x04 */
+ __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x08 */
+ __IO uint32_t SR; /*!< FLASH status register, Address offset: 0x0C */
+ __IO uint32_t CR; /*!< FLASH control register, Address offset: 0x10 */
+ __IO uint32_t OPTCR; /*!< FLASH option control register , Address offset: 0x14 */
+ __IO uint32_t OPTCR1; /*!< FLASH option control register 1, Address offset: 0x18 */
+} FLASH_TypeDef;
+
+/**
+ * @brief Flexible Memory Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */
+} FSMC_Bank1_TypeDef;
+
+/**
+ * @brief Flexible Memory Controller Bank1E
+ */
+
+typedef struct
+{
+ __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */
+} FSMC_Bank1E_TypeDef;
+
+/**
+ * @brief General Purpose I/O
+ */
+
+typedef struct
+{
+ __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
+ __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */
+ __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */
+ __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
+ __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
+ __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
+ __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */
+ __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
+ __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */
+} GPIO_TypeDef;
+
+/**
+ * @brief System configuration controller
+ */
+typedef struct
+{
+ __IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */
+ __IO uint32_t PMC; /*!< SYSCFG peripheral mode configuration register, Address offset: 0x04 */
+ __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
+ uint32_t RESERVED[2]; /*!< Reserved, 0x18-0x1C */
+ __IO uint32_t CMPCR; /*!< SYSCFG Compensation cell control register, Address offset: 0x20 */
+ uint32_t RESERVED1[2]; /*!< Reserved, 0x24-0x28 */
+ __IO uint32_t CFGR; /*!< SYSCFG Configuration register, Address offset: 0x2C */
+} SYSCFG_TypeDef;
+
+/**
+ * @brief Inter-integrated Circuit Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */
+ __IO uint32_t OAR1; /*!< I2C Own address register 1, Address offset: 0x08 */
+ __IO uint32_t OAR2; /*!< I2C Own address register 2, Address offset: 0x0C */
+ __IO uint32_t DR; /*!< I2C Data register, Address offset: 0x10 */
+ __IO uint32_t SR1; /*!< I2C Status register 1, Address offset: 0x14 */
+ __IO uint32_t SR2; /*!< I2C Status register 2, Address offset: 0x18 */
+ __IO uint32_t CCR; /*!< I2C Clock control register, Address offset: 0x1C */
+ __IO uint32_t TRISE; /*!< I2C TRISE register, Address offset: 0x20 */
+ __IO uint32_t FLTR; /*!< I2C FLTR register, Address offset: 0x24 */
+} I2C_TypeDef;
+
+/**
+ * @brief Inter-integrated Circuit Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t CR1; /*!< FMPI2C Control register 1, Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< FMPI2C Control register 2, Address offset: 0x04 */
+ __IO uint32_t OAR1; /*!< FMPI2C Own address 1 register, Address offset: 0x08 */
+ __IO uint32_t OAR2; /*!< FMPI2C Own address 2 register, Address offset: 0x0C */
+ __IO uint32_t TIMINGR; /*!< FMPI2C Timing register, Address offset: 0x10 */
+ __IO uint32_t TIMEOUTR; /*!< FMPI2C Timeout register, Address offset: 0x14 */
+ __IO uint32_t ISR; /*!< FMPI2C Interrupt and status register, Address offset: 0x18 */
+ __IO uint32_t ICR; /*!< FMPI2C Interrupt clear register, Address offset: 0x1C */
+ __IO uint32_t PECR; /*!< FMPI2C PEC register, Address offset: 0x20 */
+ __IO uint32_t RXDR; /*!< FMPI2C Receive data register, Address offset: 0x24 */
+ __IO uint32_t TXDR; /*!< FMPI2C Transmit data register, Address offset: 0x28 */
+} FMPI2C_TypeDef;
+
+/**
+ * @brief Independent WATCHDOG
+ */
+
+typedef struct
+{
+ __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */
+ __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */
+ __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */
+ __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */
+} IWDG_TypeDef;
+
+/**
+ * @brief Power Control
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */
+ __IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */
+} PWR_TypeDef;
+
+/**
+ * @brief Reset and Clock Control
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */
+ __IO uint32_t PLLCFGR; /*!< RCC PLL configuration register, Address offset: 0x04 */
+ __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x08 */
+ __IO uint32_t CIR; /*!< RCC clock interrupt register, Address offset: 0x0C */
+ __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x10 */
+ __IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x14 */
+ __IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0x18 */
+ uint32_t RESERVED0; /*!< Reserved, 0x1C */
+ __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x20 */
+ __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x24 */
+ uint32_t RESERVED1[2]; /*!< Reserved, 0x28-0x2C */
+ __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clock register, Address offset: 0x30 */
+ __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clock register, Address offset: 0x34 */
+ __IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clock register, Address offset: 0x38 */
+ uint32_t RESERVED2; /*!< Reserved, 0x3C */
+ __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x40 */
+ __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x44 */
+ uint32_t RESERVED3[2]; /*!< Reserved, 0x48-0x4C */
+ __IO uint32_t AHB1LPENR; /*!< RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 */
+ __IO uint32_t AHB2LPENR; /*!< RCC AHB2 peripheral clock enable in low power mode register, Address offset: 0x54 */
+ __IO uint32_t AHB3LPENR; /*!< RCC AHB3 peripheral clock enable in low power mode register, Address offset: 0x58 */
+ uint32_t RESERVED4; /*!< Reserved, 0x5C */
+ __IO uint32_t APB1LPENR; /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 */
+ __IO uint32_t APB2LPENR; /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 */
+ uint32_t RESERVED5[2]; /*!< Reserved, 0x68-0x6C */
+ __IO uint32_t BDCR; /*!< RCC Backup domain control register, Address offset: 0x70 */
+ __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x74 */
+ uint32_t RESERVED6[2]; /*!< Reserved, 0x78-0x7C */
+ __IO uint32_t SSCGR; /*!< RCC spread spectrum clock generation register, Address offset: 0x80 */
+ __IO uint32_t PLLI2SCFGR; /*!< RCC PLLI2S configuration register, Address offset: 0x84 */
+ uint32_t RESERVED7; /*!< Reserved, 0x84 */
+ __IO uint32_t DCKCFGR; /*!< RCC Dedicated Clocks configuration register, Address offset: 0x8C */
+ __IO uint32_t CKGATENR; /*!< RCC Clocks Gated ENable Register, Address offset: 0x90 */
+ __IO uint32_t DCKCFGR2; /*!< RCC Dedicated Clocks configuration register 2, Address offset: 0x94 */
+} RCC_TypeDef;
+
+/**
+ * @brief Real-Time Clock
+ */
+
+typedef struct
+{
+ __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
+ __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */
+ __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */
+ __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */
+ __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */
+ __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */
+ __IO uint32_t CALIBR; /*!< RTC calibration register, Address offset: 0x18 */
+ __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */
+ __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */
+ __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */
+ __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */
+ __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */
+ __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */
+ __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */
+ __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */
+ __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */
+ __IO uint32_t TAFCR; /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */
+ __IO uint32_t ALRMASSR;/*!< RTC alarm A sub second register, Address offset: 0x44 */
+ __IO uint32_t ALRMBSSR;/*!< RTC alarm B sub second register, Address offset: 0x48 */
+ uint32_t RESERVED7; /*!< Reserved, 0x4C */
+ __IO uint32_t BKP0R; /*!< RTC backup register 1, Address offset: 0x50 */
+ __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */
+ __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */
+ __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */
+ __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */
+ __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */
+ __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */
+ __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */
+ __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */
+ __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */
+ __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */
+ __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */
+ __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */
+ __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */
+ __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */
+ __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */
+ __IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */
+ __IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */
+ __IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */
+ __IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */
+} RTC_TypeDef;
+
+
+/**
+ * @brief SD host Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t POWER; /*!< SDIO power control register, Address offset: 0x00 */
+ __IO uint32_t CLKCR; /*!< SDI clock control register, Address offset: 0x04 */
+ __IO uint32_t ARG; /*!< SDIO argument register, Address offset: 0x08 */
+ __IO uint32_t CMD; /*!< SDIO command register, Address offset: 0x0C */
+ __I uint32_t RESPCMD; /*!< SDIO command response register, Address offset: 0x10 */
+ __I uint32_t RESP1; /*!< SDIO response 1 register, Address offset: 0x14 */
+ __I uint32_t RESP2; /*!< SDIO response 2 register, Address offset: 0x18 */
+ __I uint32_t RESP3; /*!< SDIO response 3 register, Address offset: 0x1C */
+ __I uint32_t RESP4; /*!< SDIO response 4 register, Address offset: 0x20 */
+ __IO uint32_t DTIMER; /*!< SDIO data timer register, Address offset: 0x24 */
+ __IO uint32_t DLEN; /*!< SDIO data length register, Address offset: 0x28 */
+ __IO uint32_t DCTRL; /*!< SDIO data control register, Address offset: 0x2C */
+ __I uint32_t DCOUNT; /*!< SDIO data counter register, Address offset: 0x30 */
+ __I uint32_t STA; /*!< SDIO status register, Address offset: 0x34 */
+ __IO uint32_t ICR; /*!< SDIO interrupt clear register, Address offset: 0x38 */
+ __IO uint32_t MASK; /*!< SDIO mask register, Address offset: 0x3C */
+ uint32_t RESERVED0[2]; /*!< Reserved, 0x40-0x44 */
+ __I uint32_t FIFOCNT; /*!< SDIO FIFO counter register, Address offset: 0x48 */
+ uint32_t RESERVED1[13]; /*!< Reserved, 0x4C-0x7C */
+ __IO uint32_t FIFO; /*!< SDIO data FIFO register, Address offset: 0x80 */
+} SDIO_TypeDef;
+
+/**
+ * @brief Serial Peripheral Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t CR1; /*!< SPI control register 1 (not used in I2S mode), Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< SPI control register 2, Address offset: 0x04 */
+ __IO uint32_t SR; /*!< SPI status register, Address offset: 0x08 */
+ __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */
+ __IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
+ __IO uint32_t RXCRCR; /*!< SPI RX CRC register (not used in I2S mode), Address offset: 0x14 */
+ __IO uint32_t TXCRCR; /*!< SPI TX CRC register (not used in I2S mode), Address offset: 0x18 */
+ __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */
+ __IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */
+} SPI_TypeDef;
+
+/**
+ * @brief QUAD Serial Peripheral Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< QUADSPI Control register, Address offset: 0x00 */
+ __IO uint32_t DCR; /*!< QUADSPI Device Configuration register, Address offset: 0x04 */
+ __IO uint32_t SR; /*!< QUADSPI Status register, Address offset: 0x08 */
+ __IO uint32_t FCR; /*!< QUADSPI Flag Clear register, Address offset: 0x0C */
+ __IO uint32_t DLR; /*!< QUADSPI Data Length register, Address offset: 0x10 */
+ __IO uint32_t CCR; /*!< QUADSPI Communication Configuration register, Address offset: 0x14 */
+ __IO uint32_t AR; /*!< QUADSPI Address register, Address offset: 0x18 */
+ __IO uint32_t ABR; /*!< QUADSPI Alternate Bytes register, Address offset: 0x1C */
+ __IO uint32_t DR; /*!< QUADSPI Data register, Address offset: 0x20 */
+ __IO uint32_t PSMKR; /*!< QUADSPI Polling Status Mask register, Address offset: 0x24 */
+ __IO uint32_t PSMAR; /*!< QUADSPI Polling Status Match register, Address offset: 0x28 */
+ __IO uint32_t PIR; /*!< QUADSPI Polling Interval register, Address offset: 0x2C */
+ __IO uint32_t LPTR; /*!< QUADSPI Low Power Timeout register, Address offset: 0x30 */
+} QUADSPI_TypeDef;
+
+/**
+ * @brief TIM
+ */
+
+typedef struct
+{
+ __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
+ __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */
+ __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
+ __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
+ __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
+ __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
+ __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
+ __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
+ __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
+ __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */
+ __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
+ __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */
+ __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
+ __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
+ __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
+ __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
+ __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
+ __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
+ __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */
+ __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */
+} TIM_TypeDef;
+
+/**
+ * @brief Universal Synchronous Asynchronous Receiver Transmitter
+ */
+
+typedef struct
+{
+ __IO uint32_t SR; /*!< USART Status register, Address offset: 0x00 */
+ __IO uint32_t DR; /*!< USART Data register, Address offset: 0x04 */
+ __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x08 */
+ __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x0C */
+ __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x10 */
+ __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x14 */
+ __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x18 */
+} USART_TypeDef;
+
+/**
+ * @brief Window WATCHDOG
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
+ __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
+ __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
+} WWDG_TypeDef;
+
+
+/**
+ * @brief RNG
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */
+ __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */
+ __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */
+} RNG_TypeDef;
+
+
+/**
+ * @brief USB_OTG_Core_Registers
+ */
+typedef struct
+{
+ __IO uint32_t GOTGCTL; /*!< USB_OTG Control and Status Register 000h*/
+ __IO uint32_t GOTGINT; /*!< USB_OTG Interrupt Register 004h*/
+ __IO uint32_t GAHBCFG; /*!< Core AHB Configuration Register 008h*/
+ __IO uint32_t GUSBCFG; /*!< Core USB Configuration Register 00Ch*/
+ __IO uint32_t GRSTCTL; /*!< Core Reset Register 010h*/
+ __IO uint32_t GINTSTS; /*!< Core Interrupt Register 014h*/
+ __IO uint32_t GINTMSK; /*!< Core Interrupt Mask Register 018h*/
+ __IO uint32_t GRXSTSR; /*!< Receive Sts Q Read Register 01Ch*/
+ __IO uint32_t GRXSTSP; /*!< Receive Sts Q Read & POP Register 020h*/
+ __IO uint32_t GRXFSIZ; /*!< Receive FIFO Size Register 024h*/
+ __IO uint32_t DIEPTXF0_HNPTXFSIZ; /*!< EP0 / Non Periodic Tx FIFO Size Register 028h*/
+ __IO uint32_t HNPTXSTS; /*!< Non Periodic Tx FIFO/Queue Sts reg 02Ch*/
+ uint32_t Reserved30[2]; /*!< Reserved 030h*/
+ __IO uint32_t GCCFG; /*!< General Purpose IO Register 038h*/
+ __IO uint32_t CID; /*!< User ID Register 03Ch*/
+ uint32_t Reserved5[3]; /*!< Reserved 040h-048h*/
+ __IO uint32_t GHWCFG3; /*!< User HW config3 04Ch*/
+ uint32_t Reserved6; /*!< Reserved 050h*/
+ __IO uint32_t GLPMCFG; /*!< LPM Register 054h*/
+ uint32_t Reserved; /*!< Reserved 058h */
+ __IO uint32_t GDFIFOCFG; /*!< DFIFO Software Config Register 05Ch */
+ uint32_t Reserved43[40]; /*!< Reserved 058h-0FFh */
+ __IO uint32_t HPTXFSIZ; /*!< Host Periodic Tx FIFO Size Reg 100h*/
+ __IO uint32_t DIEPTXF[0x0F]; /*!< dev Periodic Transmit FIFO */
+} USB_OTG_GlobalTypeDef;
+
+
+/**
+ * @brief USB_OTG_device_Registers
+ */
+typedef struct
+{
+ __IO uint32_t DCFG; /*!< dev Configuration Register 800h */
+ __IO uint32_t DCTL; /*!< dev Control Register 804h */
+ __IO uint32_t DSTS; /*!< dev Status Register (RO) 808h */
+ uint32_t Reserved0C; /*!< Reserved 80Ch */
+ __IO uint32_t DIEPMSK; /*!< dev IN Endpoint Mask 810h */
+ __IO uint32_t DOEPMSK; /*!< dev OUT Endpoint Mask 814h */
+ __IO uint32_t DAINT; /*!< dev All Endpoints Itr Reg 818h */
+ __IO uint32_t DAINTMSK; /*!< dev All Endpoints Itr Mask 81Ch */
+ uint32_t Reserved20; /*!< Reserved 820h */
+ uint32_t Reserved9; /*!< Reserved 824h */
+ __IO uint32_t DVBUSDIS; /*!< dev VBUS discharge Register 828h */
+ __IO uint32_t DVBUSPULSE; /*!< dev VBUS Pulse Register 82Ch */
+ __IO uint32_t DTHRCTL; /*!< dev threshold 830h */
+ __IO uint32_t DIEPEMPMSK; /*!< dev empty msk 834h */
+ __IO uint32_t DEACHINT; /*!< dedicated EP interrupt 838h */
+ __IO uint32_t DEACHMSK; /*!< dedicated EP msk 83Ch */
+ uint32_t Reserved40; /*!< dedicated EP mask 840h */
+ __IO uint32_t DINEP1MSK; /*!< dedicated EP mask 844h */
+ uint32_t Reserved44[15]; /*!< Reserved 844-87Ch */
+ __IO uint32_t DOUTEP1MSK; /*!< dedicated EP msk 884h */
+} USB_OTG_DeviceTypeDef;
+
+
+/**
+ * @brief USB_OTG_IN_Endpoint-Specific_Register
+ */
+typedef struct
+{
+ __IO uint32_t DIEPCTL; /*!< dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h */
+ uint32_t Reserved04; /*!< Reserved 900h + (ep_num * 20h) + 04h */
+ __IO uint32_t DIEPINT; /*!< dev IN Endpoint Itr Reg 900h + (ep_num * 20h) + 08h */
+ uint32_t Reserved0C; /*!< Reserved 900h + (ep_num * 20h) + 0Ch */
+ __IO uint32_t DIEPTSIZ; /*!< IN Endpoint Txfer Size 900h + (ep_num * 20h) + 10h */
+ __IO uint32_t DIEPDMA; /*!< IN Endpoint DMA Address Reg 900h + (ep_num * 20h) + 14h */
+ __IO uint32_t DTXFSTS; /*!< IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h */
+ uint32_t Reserved18; /*!< Reserved 900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch */
+} USB_OTG_INEndpointTypeDef;
+
+
+/**
+ * @brief USB_OTG_OUT_Endpoint-Specific_Registers
+ */
+typedef struct
+{
+ __IO uint32_t DOEPCTL; /*!< dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h */
+ uint32_t Reserved04; /*!< Reserved B00h + (ep_num * 20h) + 04h */
+ __IO uint32_t DOEPINT; /*!< dev OUT Endpoint Itr Reg B00h + (ep_num * 20h) + 08h */
+ uint32_t Reserved0C; /*!< Reserved B00h + (ep_num * 20h) + 0Ch */
+ __IO uint32_t DOEPTSIZ; /*!< dev OUT Endpoint Txfer Size B00h + (ep_num * 20h) + 10h */
+ __IO uint32_t DOEPDMA; /*!< dev OUT Endpoint DMA Address B00h + (ep_num * 20h) + 14h */
+ uint32_t Reserved18[2]; /*!< Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch */
+} USB_OTG_OUTEndpointTypeDef;
+
+
+/**
+ * @brief USB_OTG_Host_Mode_Register_Structures
+ */
+typedef struct
+{
+ __IO uint32_t HCFG; /*!< Host Configuration Register 400h */
+ __IO uint32_t HFIR; /*!< Host Frame Interval Register 404h */
+ __IO uint32_t HFNUM; /*!< Host Frame Nbr/Frame Remaining 408h */
+ uint32_t Reserved40C; /*!< Reserved 40Ch */
+ __IO uint32_t HPTXSTS; /*!< Host Periodic Tx FIFO/ Queue Status 410h */
+ __IO uint32_t HAINT; /*!< Host All Channels Interrupt Register 414h */
+ __IO uint32_t HAINTMSK; /*!< Host All Channels Interrupt Mask 418h */
+} USB_OTG_HostTypeDef;
+
+
+/**
+ * @brief USB_OTG_Host_Channel_Specific_Registers
+ */
+typedef struct
+{
+ __IO uint32_t HCCHAR; /*!< Host Channel Characteristics Register 500h */
+ __IO uint32_t HCSPLT; /*!< Host Channel Split Control Register 504h */
+ __IO uint32_t HCINT; /*!< Host Channel Interrupt Register 508h */
+ __IO uint32_t HCINTMSK; /*!< Host Channel Interrupt Mask Register 50Ch */
+ __IO uint32_t HCTSIZ; /*!< Host Channel Transfer Size Register 510h */
+ __IO uint32_t HCDMA; /*!< Host Channel DMA Address Register 514h */
+ uint32_t Reserved[2]; /*!< Reserved */
+} USB_OTG_HostChannelTypeDef;
+
+
+/**
+ * @brief Peripheral_memory_map
+ */
+#define FLASH_BASE 0x08000000U /*!< FLASH(up to 1 MB) base address in the alias region */
+#define SRAM1_BASE 0x20000000U /*!< SRAM1(256 KB) base address in the alias region */
+#define PERIPH_BASE 0x40000000U /*!< Peripheral base address in the alias region */
+#define FSMC_R_BASE 0xA0000000U /*!< FSMC registers base address */
+#define QSPI_R_BASE 0xA0001000U /*!< QuadSPI registers base address */
+
+#define SRAM1_BB_BASE 0x22000000U /*!< SRAM1(256 KB) base address in the bit-band region */
+#define PERIPH_BB_BASE 0x42000000U /*!< Peripheral base address in the bit-band region */
+#define FLASH_END 0x080FFFFFU /*!< FLASH end address */
+
+/* Legacy defines */
+#define SRAM_BASE SRAM1_BASE
+#define SRAM_BB_BASE SRAM1_BB_BASE
+
+/*!< Peripheral memory map */
+#define APB1PERIPH_BASE PERIPH_BASE
+#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000U)
+#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000U)
+#define AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000U)
+
+/*!< APB1 peripherals */
+#define TIM2_BASE (APB1PERIPH_BASE + 0x0000U)
+#define TIM3_BASE (APB1PERIPH_BASE + 0x0400U)
+#define TIM4_BASE (APB1PERIPH_BASE + 0x0800U)
+#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00U)
+#define TIM6_BASE (APB1PERIPH_BASE + 0x1000U)
+#define TIM7_BASE (APB1PERIPH_BASE + 0x1400U)
+#define TIM12_BASE (APB1PERIPH_BASE + 0x1800U)
+#define TIM13_BASE (APB1PERIPH_BASE + 0x1C00U)
+#define TIM14_BASE (APB1PERIPH_BASE + 0x2000U)
+#define RTC_BASE (APB1PERIPH_BASE + 0x2800U)
+#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00U)
+#define IWDG_BASE (APB1PERIPH_BASE + 0x3000U)
+#define I2S2ext_BASE (APB1PERIPH_BASE + 0x3400U)
+#define SPI2_BASE (APB1PERIPH_BASE + 0x3800U)
+#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00U)
+#define I2S3ext_BASE (APB1PERIPH_BASE + 0x4000U)
+#define USART2_BASE (APB1PERIPH_BASE + 0x4400U)
+#define USART3_BASE (APB1PERIPH_BASE + 0x4800U)
+#define I2C1_BASE (APB1PERIPH_BASE + 0x5400U)
+#define I2C2_BASE (APB1PERIPH_BASE + 0x5800U)
+#define I2C3_BASE (APB1PERIPH_BASE + 0x5C00U)
+#define FMPI2C1_BASE (APB1PERIPH_BASE + 0x6000U)
+#define CAN1_BASE (APB1PERIPH_BASE + 0x6400U)
+#define CAN2_BASE (APB1PERIPH_BASE + 0x6800U)
+#define PWR_BASE (APB1PERIPH_BASE + 0x7000U)
+
+/*!< APB2 peripherals */
+#define TIM1_BASE (APB2PERIPH_BASE + 0x0000U)
+#define TIM8_BASE (APB2PERIPH_BASE + 0x0400U)
+#define USART1_BASE (APB2PERIPH_BASE + 0x1000U)
+#define USART6_BASE (APB2PERIPH_BASE + 0x1400U)
+#define ADC1_BASE (APB2PERIPH_BASE + 0x2000U)
+#define ADC_BASE (APB2PERIPH_BASE + 0x2300U)
+#define SDIO_BASE (APB2PERIPH_BASE + 0x2C00U)
+#define SPI1_BASE (APB2PERIPH_BASE + 0x3000U)
+#define SPI4_BASE (APB2PERIPH_BASE + 0x3400U)
+#define SYSCFG_BASE (APB2PERIPH_BASE + 0x3800U)
+#define EXTI_BASE (APB2PERIPH_BASE + 0x3C00U)
+#define TIM9_BASE (APB2PERIPH_BASE + 0x4000U)
+#define TIM10_BASE (APB2PERIPH_BASE + 0x4400U)
+#define TIM11_BASE (APB2PERIPH_BASE + 0x4800U)
+#define SPI5_BASE (APB2PERIPH_BASE + 0x5000U)
+#define DFSDM1_BASE (APB2PERIPH_BASE + 0x6000U)
+#define DFSDM1_Channel0_BASE (DFSDM1_BASE + 0x00U)
+#define DFSDM1_Channel1_BASE (DFSDM1_BASE + 0x20U)
+#define DFSDM1_Channel2_BASE (DFSDM1_BASE + 0x40U)
+#define DFSDM1_Channel3_BASE (DFSDM1_BASE + 0x60U)
+#define DFSDM1_Filter0_BASE (DFSDM1_BASE + 0x100U)
+#define DFSDM1_Filter1_BASE (DFSDM1_BASE + 0x180U)
+
+/*!< AHB1 peripherals */
+#define GPIOA_BASE (AHB1PERIPH_BASE + 0x0000U)
+#define GPIOB_BASE (AHB1PERIPH_BASE + 0x0400U)
+#define GPIOC_BASE (AHB1PERIPH_BASE + 0x0800U)
+#define GPIOD_BASE (AHB1PERIPH_BASE + 0x0C00U)
+#define GPIOE_BASE (AHB1PERIPH_BASE + 0x1000U)
+#define GPIOF_BASE (AHB1PERIPH_BASE + 0x1400U)
+#define GPIOG_BASE (AHB1PERIPH_BASE + 0x1800U)
+#define GPIOH_BASE (AHB1PERIPH_BASE + 0x1C00U)
+#define CRC_BASE (AHB1PERIPH_BASE + 0x3000U)
+#define RCC_BASE (AHB1PERIPH_BASE + 0x3800U)
+#define FLASH_R_BASE (AHB1PERIPH_BASE + 0x3C00U)
+#define DMA1_BASE (AHB1PERIPH_BASE + 0x6000U)
+#define DMA1_Stream0_BASE (DMA1_BASE + 0x010U)
+#define DMA1_Stream1_BASE (DMA1_BASE + 0x028U)
+#define DMA1_Stream2_BASE (DMA1_BASE + 0x040U)
+#define DMA1_Stream3_BASE (DMA1_BASE + 0x058U)
+#define DMA1_Stream4_BASE (DMA1_BASE + 0x070U)
+#define DMA1_Stream5_BASE (DMA1_BASE + 0x088U)
+#define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0U)
+#define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8U)
+#define DMA2_BASE (AHB1PERIPH_BASE + 0x6400U)
+#define DMA2_Stream0_BASE (DMA2_BASE + 0x010U)
+#define DMA2_Stream1_BASE (DMA2_BASE + 0x028U)
+#define DMA2_Stream2_BASE (DMA2_BASE + 0x040U)
+#define DMA2_Stream3_BASE (DMA2_BASE + 0x058U)
+#define DMA2_Stream4_BASE (DMA2_BASE + 0x070U)
+#define DMA2_Stream5_BASE (DMA2_BASE + 0x088U)
+#define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0U)
+#define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8U)
+
+/*!< AHB2 peripherals */
+#define RNG_BASE (AHB2PERIPH_BASE + 0x60800U)
+
+/*!< FSMC Bankx registers base address */
+#define FSMC_Bank1_R_BASE (FSMC_R_BASE + 0x0000U)
+#define FSMC_Bank1E_R_BASE (FSMC_R_BASE + 0x0104U)
+
+/* Debug MCU registers base address */
+#define DBGMCU_BASE 0xE0042000U
+
+/*!< USB registers base address */
+#define USB_OTG_FS_PERIPH_BASE 0x50000000U
+
+#define USB_OTG_GLOBAL_BASE 0x000U
+#define USB_OTG_DEVICE_BASE 0x800U
+#define USB_OTG_IN_ENDPOINT_BASE 0x900U
+#define USB_OTG_OUT_ENDPOINT_BASE 0xB00U
+#define USB_OTG_EP_REG_SIZE 0x20U
+#define USB_OTG_HOST_BASE 0x400U
+#define USB_OTG_HOST_PORT_BASE 0x440U
+#define USB_OTG_HOST_CHANNEL_BASE 0x500U
+#define USB_OTG_HOST_CHANNEL_SIZE 0x20U
+#define USB_OTG_PCGCCTL_BASE 0xE00U
+#define USB_OTG_FIFO_BASE 0x1000U
+#define USB_OTG_FIFO_SIZE 0x1000U
+
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_declaration
+ * @{
+ */
+#define TIM2 ((TIM_TypeDef *) TIM2_BASE)
+#define TIM3 ((TIM_TypeDef *) TIM3_BASE)
+#define TIM4 ((TIM_TypeDef *) TIM4_BASE)
+#define TIM5 ((TIM_TypeDef *) TIM5_BASE)
+#define TIM6 ((TIM_TypeDef *) TIM6_BASE)
+#define TIM7 ((TIM_TypeDef *) TIM7_BASE)
+#define TIM12 ((TIM_TypeDef *) TIM12_BASE)
+#define TIM13 ((TIM_TypeDef *) TIM13_BASE)
+#define TIM14 ((TIM_TypeDef *) TIM14_BASE)
+#define RTC ((RTC_TypeDef *) RTC_BASE)
+#define WWDG ((WWDG_TypeDef *) WWDG_BASE)
+#define IWDG ((IWDG_TypeDef *) IWDG_BASE)
+#define I2S2ext ((SPI_TypeDef *) I2S2ext_BASE)
+#define SPI2 ((SPI_TypeDef *) SPI2_BASE)
+#define SPI3 ((SPI_TypeDef *) SPI3_BASE)
+#define I2S3ext ((SPI_TypeDef *) I2S3ext_BASE)
+#define USART2 ((USART_TypeDef *) USART2_BASE)
+#define USART3 ((USART_TypeDef *) USART3_BASE)
+#define I2C1 ((I2C_TypeDef *) I2C1_BASE)
+#define I2C2 ((I2C_TypeDef *) I2C2_BASE)
+#define I2C3 ((I2C_TypeDef *) I2C3_BASE)
+#define FMPI2C1 ((FMPI2C_TypeDef *) FMPI2C1_BASE)
+#define CAN1 ((CAN_TypeDef *) CAN1_BASE)
+#define CAN2 ((CAN_TypeDef *) CAN2_BASE)
+#define PWR ((PWR_TypeDef *) PWR_BASE)
+#define TIM1 ((TIM_TypeDef *) TIM1_BASE)
+#define TIM8 ((TIM_TypeDef *) TIM8_BASE)
+#define USART1 ((USART_TypeDef *) USART1_BASE)
+#define USART6 ((USART_TypeDef *) USART6_BASE)
+#define ADC ((ADC_Common_TypeDef *) ADC_BASE)
+#define ADC1 ((ADC_TypeDef *) ADC1_BASE)
+#define SDIO ((SDIO_TypeDef *) SDIO_BASE)
+#define SPI1 ((SPI_TypeDef *) SPI1_BASE)
+#define SPI4 ((SPI_TypeDef *) SPI4_BASE)
+#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
+#define EXTI ((EXTI_TypeDef *) EXTI_BASE)
+#define TIM9 ((TIM_TypeDef *) TIM9_BASE)
+#define TIM10 ((TIM_TypeDef *) TIM10_BASE)
+#define TIM11 ((TIM_TypeDef *) TIM11_BASE)
+#define SPI5 ((SPI_TypeDef *) SPI5_BASE)
+#define DFSDM1_Channel0 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel0_BASE)
+#define DFSDM1_Channel1 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel1_BASE)
+#define DFSDM1_Channel2 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel2_BASE)
+#define DFSDM1_Channel3 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel3_BASE)
+#define DFSDM1_Filter0 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter0_BASE)
+#define DFSDM1_Filter1 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter1_BASE)
+#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
+#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
+#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
+#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
+#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
+#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
+#define GPIOG ((GPIO_TypeDef *) GPIOG_BASE)
+#define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
+#define CRC ((CRC_TypeDef *) CRC_BASE)
+#define RCC ((RCC_TypeDef *) RCC_BASE)
+#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
+#define DMA1 ((DMA_TypeDef *) DMA1_BASE)
+#define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)
+#define DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)
+#define DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)
+#define DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)
+#define DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)
+#define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)
+#define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)
+#define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)
+#define DMA2 ((DMA_TypeDef *) DMA2_BASE)
+#define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)
+#define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
+#define DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)
+#define DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)
+#define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)
+#define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)
+#define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)
+#define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)
+#define RNG ((RNG_TypeDef *) RNG_BASE)
+#define FSMC_Bank1 ((FSMC_Bank1_TypeDef *) FSMC_Bank1_R_BASE)
+#define FSMC_Bank1E ((FSMC_Bank1E_TypeDef *) FSMC_Bank1E_R_BASE)
+#define QUADSPI ((QUADSPI_TypeDef *) QSPI_R_BASE)
+
+#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
+
+#define USB_OTG_FS ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE)
+
+/**
+ * @}
+ */
+
+/** @addtogroup Exported_constants
+ * @{
+ */
+
+ /** @addtogroup Peripheral_Registers_Bits_Definition
+ * @{
+ */
+
+/******************************************************************************/
+/* Peripheral Registers_Bits_Definition */
+/******************************************************************************/
+
+/******************************************************************************/
+/* */
+/* Analog to Digital Converter */
+/* */
+/******************************************************************************/
+/******************** Bit definition for ADC_SR register ********************/
+#define ADC_SR_AWD 0x00000001U /*!<Analog watchdog flag */
+#define ADC_SR_EOC 0x00000002U /*!<End of conversion */
+#define ADC_SR_JEOC 0x00000004U /*!<Injected channel end of conversion */
+#define ADC_SR_JSTRT 0x00000008U /*!<Injected channel Start flag */
+#define ADC_SR_STRT 0x00000010U /*!<Regular channel Start flag */
+#define ADC_SR_OVR 0x00000020U /*!<Overrun flag */
+
+/******************* Bit definition for ADC_CR1 register ********************/
+#define ADC_CR1_AWDCH 0x0000001FU /*!<AWDCH[4:0] bits (Analog watchdog channel select bits) */
+#define ADC_CR1_AWDCH_0 0x00000001U /*!<Bit 0 */
+#define ADC_CR1_AWDCH_1 0x00000002U /*!<Bit 1 */
+#define ADC_CR1_AWDCH_2 0x00000004U /*!<Bit 2 */
+#define ADC_CR1_AWDCH_3 0x00000008U /*!<Bit 3 */
+#define ADC_CR1_AWDCH_4 0x00000010U /*!<Bit 4 */
+#define ADC_CR1_EOCIE 0x00000020U /*!<Interrupt enable for EOC */
+#define ADC_CR1_AWDIE 0x00000040U /*!<AAnalog Watchdog interrupt enable */
+#define ADC_CR1_JEOCIE 0x00000080U /*!<Interrupt enable for injected channels */
+#define ADC_CR1_SCAN 0x00000100U /*!<Scan mode */
+#define ADC_CR1_AWDSGL 0x00000200U /*!<Enable the watchdog on a single channel in scan mode */
+#define ADC_CR1_JAUTO 0x00000400U /*!<Automatic injected group conversion */
+#define ADC_CR1_DISCEN 0x00000800U /*!<Discontinuous mode on regular channels */
+#define ADC_CR1_JDISCEN 0x00001000U /*!<Discontinuous mode on injected channels */
+#define ADC_CR1_DISCNUM 0x0000E000U /*!<DISCNUM[2:0] bits (Discontinuous mode channel count) */
+#define ADC_CR1_DISCNUM_0 0x00002000U /*!<Bit 0 */
+#define ADC_CR1_DISCNUM_1 0x00004000U /*!<Bit 1 */
+#define ADC_CR1_DISCNUM_2 0x00008000U /*!<Bit 2 */
+#define ADC_CR1_JAWDEN 0x00400000U /*!<Analog watchdog enable on injected channels */
+#define ADC_CR1_AWDEN 0x00800000U /*!<Analog watchdog enable on regular channels */
+#define ADC_CR1_RES 0x03000000U /*!<RES[2:0] bits (Resolution) */
+#define ADC_CR1_RES_0 0x01000000U /*!<Bit 0 */
+#define ADC_CR1_RES_1 0x02000000U /*!<Bit 1 */
+#define ADC_CR1_OVRIE 0x04000000U /*!<overrun interrupt enable */
+
+/******************* Bit definition for ADC_CR2 register ********************/
+#define ADC_CR2_ADON 0x00000001U /*!<A/D Converter ON / OFF */
+#define ADC_CR2_CONT 0x00000002U /*!<Continuous Conversion */
+#define ADC_CR2_DMA 0x00000100U /*!<Direct Memory access mode */
+#define ADC_CR2_DDS 0x00000200U /*!<DMA disable selection (Single ADC) */
+#define ADC_CR2_EOCS 0x00000400U /*!<End of conversion selection */
+#define ADC_CR2_ALIGN 0x00000800U /*!<Data Alignment */
+#define ADC_CR2_JEXTSEL 0x000F0000U /*!<JEXTSEL[3:0] bits (External event select for injected group) */
+#define ADC_CR2_JEXTSEL_0 0x00010000U /*!<Bit 0 */
+#define ADC_CR2_JEXTSEL_1 0x00020000U /*!<Bit 1 */
+#define ADC_CR2_JEXTSEL_2 0x00040000U /*!<Bit 2 */
+#define ADC_CR2_JEXTSEL_3 0x00080000U /*!<Bit 3 */
+#define ADC_CR2_JEXTEN 0x00300000U /*!<JEXTEN[1:0] bits (External Trigger Conversion mode for injected channelsp) */
+#define ADC_CR2_JEXTEN_0 0x00100000U /*!<Bit 0 */
+#define ADC_CR2_JEXTEN_1 0x00200000U /*!<Bit 1 */
+#define ADC_CR2_JSWSTART 0x00400000U /*!<Start Conversion of injected channels */
+#define ADC_CR2_EXTSEL 0x0F000000U /*!<EXTSEL[3:0] bits (External Event Select for regular group) */
+#define ADC_CR2_EXTSEL_0 0x01000000U /*!<Bit 0 */
+#define ADC_CR2_EXTSEL_1 0x02000000U /*!<Bit 1 */
+#define ADC_CR2_EXTSEL_2 0x04000000U /*!<Bit 2 */
+#define ADC_CR2_EXTSEL_3 0x08000000U /*!<Bit 3 */
+#define ADC_CR2_EXTEN 0x30000000U /*!<EXTEN[1:0] bits (External Trigger Conversion mode for regular channelsp) */
+#define ADC_CR2_EXTEN_0 0x10000000U /*!<Bit 0 */
+#define ADC_CR2_EXTEN_1 0x20000000U /*!<Bit 1 */
+#define ADC_CR2_SWSTART 0x40000000U /*!<Start Conversion of regular channels */
+
+/****************** Bit definition for ADC_SMPR1 register *******************/
+#define ADC_SMPR1_SMP10 0x00000007U /*!<SMP10[2:0] bits (Channel 10 Sample time selection) */
+#define ADC_SMPR1_SMP10_0 0x00000001U /*!<Bit 0 */
+#define ADC_SMPR1_SMP10_1 0x00000002U /*!<Bit 1 */
+#define ADC_SMPR1_SMP10_2 0x00000004U /*!<Bit 2 */
+#define ADC_SMPR1_SMP11 0x00000038U /*!<SMP11[2:0] bits (Channel 11 Sample time selection) */
+#define ADC_SMPR1_SMP11_0 0x00000008U /*!<Bit 0 */
+#define ADC_SMPR1_SMP11_1 0x00000010U /*!<Bit 1 */
+#define ADC_SMPR1_SMP11_2 0x00000020U /*!<Bit 2 */
+#define ADC_SMPR1_SMP12 0x000001C0U /*!<SMP12[2:0] bits (Channel 12 Sample time selection) */
+#define ADC_SMPR1_SMP12_0 0x00000040U /*!<Bit 0 */
+#define ADC_SMPR1_SMP12_1 0x00000080U /*!<Bit 1 */
+#define ADC_SMPR1_SMP12_2 0x00000100U /*!<Bit 2 */
+#define ADC_SMPR1_SMP13 0x00000E00U /*!<SMP13[2:0] bits (Channel 13 Sample time selection) */
+#define ADC_SMPR1_SMP13_0 0x00000200U /*!<Bit 0 */
+#define ADC_SMPR1_SMP13_1 0x00000400U /*!<Bit 1 */
+#define ADC_SMPR1_SMP13_2 0x00000800U /*!<Bit 2 */
+#define ADC_SMPR1_SMP14 0x00007000U /*!<SMP14[2:0] bits (Channel 14 Sample time selection) */
+#define ADC_SMPR1_SMP14_0 0x00001000U /*!<Bit 0 */
+#define ADC_SMPR1_SMP14_1 0x00002000U /*!<Bit 1 */
+#define ADC_SMPR1_SMP14_2 0x00004000U /*!<Bit 2 */
+#define ADC_SMPR1_SMP15 0x00038000U /*!<SMP15[2:0] bits (Channel 15 Sample time selection) */
+#define ADC_SMPR1_SMP15_0 0x00008000U /*!<Bit 0 */
+#define ADC_SMPR1_SMP15_1 0x00010000U /*!<Bit 1 */
+#define ADC_SMPR1_SMP15_2 0x00020000U /*!<Bit 2 */
+#define ADC_SMPR1_SMP16 0x001C0000U /*!<SMP16[2:0] bits (Channel 16 Sample time selection) */
+#define ADC_SMPR1_SMP16_0 0x00040000U /*!<Bit 0 */
+#define ADC_SMPR1_SMP16_1 0x00080000U /*!<Bit 1 */
+#define ADC_SMPR1_SMP16_2 0x00100000U /*!<Bit 2 */
+#define ADC_SMPR1_SMP17 0x00E00000U /*!<SMP17[2:0] bits (Channel 17 Sample time selection) */
+#define ADC_SMPR1_SMP17_0 0x00200000U /*!<Bit 0 */
+#define ADC_SMPR1_SMP17_1 0x00400000U /*!<Bit 1 */
+#define ADC_SMPR1_SMP17_2 0x00800000U /*!<Bit 2 */
+#define ADC_SMPR1_SMP18 0x07000000U /*!<SMP18[2:0] bits (Channel 18 Sample time selection) */
+#define ADC_SMPR1_SMP18_0 0x01000000U /*!<Bit 0 */
+#define ADC_SMPR1_SMP18_1 0x02000000U /*!<Bit 1 */
+#define ADC_SMPR1_SMP18_2 0x04000000U /*!<Bit 2 */
+
+/****************** Bit definition for ADC_SMPR2 register *******************/
+#define ADC_SMPR2_SMP0 0x00000007U /*!<SMP0[2:0] bits (Channel 0 Sample time selection) */
+#define ADC_SMPR2_SMP0_0 0x00000001U /*!<Bit 0 */
+#define ADC_SMPR2_SMP0_1 0x00000002U /*!<Bit 1 */
+#define ADC_SMPR2_SMP0_2 0x00000004U /*!<Bit 2 */
+#define ADC_SMPR2_SMP1 0x00000038U /*!<SMP1[2:0] bits (Channel 1 Sample time selection) */
+#define ADC_SMPR2_SMP1_0 0x00000008U /*!<Bit 0 */
+#define ADC_SMPR2_SMP1_1 0x00000010U /*!<Bit 1 */
+#define ADC_SMPR2_SMP1_2 0x00000020U /*!<Bit 2 */
+#define ADC_SMPR2_SMP2 0x000001C0U /*!<SMP2[2:0] bits (Channel 2 Sample time selection) */
+#define ADC_SMPR2_SMP2_0 0x00000040U /*!<Bit 0 */
+#define ADC_SMPR2_SMP2_1 0x00000080U /*!<Bit 1 */
+#define ADC_SMPR2_SMP2_2 0x00000100U /*!<Bit 2 */
+#define ADC_SMPR2_SMP3 0x00000E00U /*!<SMP3[2:0] bits (Channel 3 Sample time selection) */
+#define ADC_SMPR2_SMP3_0 0x00000200U /*!<Bit 0 */
+#define ADC_SMPR2_SMP3_1 0x00000400U /*!<Bit 1 */
+#define ADC_SMPR2_SMP3_2 0x00000800U /*!<Bit 2 */
+#define ADC_SMPR2_SMP4 0x00007000U /*!<SMP4[2:0] bits (Channel 4 Sample time selection) */
+#define ADC_SMPR2_SMP4_0 0x00001000U /*!<Bit 0 */
+#define ADC_SMPR2_SMP4_1 0x00002000U /*!<Bit 1 */
+#define ADC_SMPR2_SMP4_2 0x00004000U /*!<Bit 2 */
+#define ADC_SMPR2_SMP5 0x00038000U /*!<SMP5[2:0] bits (Channel 5 Sample time selection) */
+#define ADC_SMPR2_SMP5_0 0x00008000U /*!<Bit 0 */
+#define ADC_SMPR2_SMP5_1 0x00010000U /*!<Bit 1 */
+#define ADC_SMPR2_SMP5_2 0x00020000U /*!<Bit 2 */
+#define ADC_SMPR2_SMP6 0x001C0000U /*!<SMP6[2:0] bits (Channel 6 Sample time selection) */
+#define ADC_SMPR2_SMP6_0 0x00040000U /*!<Bit 0 */
+#define ADC_SMPR2_SMP6_1 0x00080000U /*!<Bit 1 */
+#define ADC_SMPR2_SMP6_2 0x00100000U /*!<Bit 2 */
+#define ADC_SMPR2_SMP7 0x00E00000U /*!<SMP7[2:0] bits (Channel 7 Sample time selection) */
+#define ADC_SMPR2_SMP7_0 0x00200000U /*!<Bit 0 */
+#define ADC_SMPR2_SMP7_1 0x00400000U /*!<Bit 1 */
+#define ADC_SMPR2_SMP7_2 0x00800000U /*!<Bit 2 */
+#define ADC_SMPR2_SMP8 0x07000000U /*!<SMP8[2:0] bits (Channel 8 Sample time selection) */
+#define ADC_SMPR2_SMP8_0 0x01000000U /*!<Bit 0 */
+#define ADC_SMPR2_SMP8_1 0x02000000U /*!<Bit 1 */
+#define ADC_SMPR2_SMP8_2 0x04000000U /*!<Bit 2 */
+#define ADC_SMPR2_SMP9 0x38000000U /*!<SMP9[2:0] bits (Channel 9 Sample time selection) */
+#define ADC_SMPR2_SMP9_0 0x08000000U /*!<Bit 0 */
+#define ADC_SMPR2_SMP9_1 0x10000000U /*!<Bit 1 */
+#define ADC_SMPR2_SMP9_2 0x20000000U /*!<Bit 2 */
+
+/****************** Bit definition for ADC_JOFR1 register *******************/
+#define ADC_JOFR1_JOFFSET1 0x0FFFU /*!<Data offset for injected channel 1 */
+
+/****************** Bit definition for ADC_JOFR2 register *******************/
+#define ADC_JOFR2_JOFFSET2 0x0FFFU /*!<Data offset for injected channel 2 */
+
+/****************** Bit definition for ADC_JOFR3 register *******************/
+#define ADC_JOFR3_JOFFSET3 0x0FFFU /*!<Data offset for injected channel 3 */
+
+/****************** Bit definition for ADC_JOFR4 register *******************/
+#define ADC_JOFR4_JOFFSET4 0x0FFFU /*!<Data offset for injected channel 4 */
+
+/******************* Bit definition for ADC_HTR register ********************/
+#define ADC_HTR_HT 0x0FFFU /*!<Analog watchdog high threshold */
+
+/******************* Bit definition for ADC_LTR register ********************/
+#define ADC_LTR_LT 0x0FFFU /*!<Analog watchdog low threshold */
+
+/******************* Bit definition for ADC_SQR1 register *******************/
+#define ADC_SQR1_SQ13 0x0000001FU /*!<SQ13[4:0] bits (13th conversion in regular sequence) */
+#define ADC_SQR1_SQ13_0 0x00000001U /*!<Bit 0 */
+#define ADC_SQR1_SQ13_1 0x00000002U /*!<Bit 1 */
+#define ADC_SQR1_SQ13_2 0x00000004U /*!<Bit 2 */
+#define ADC_SQR1_SQ13_3 0x00000008U /*!<Bit 3 */
+#define ADC_SQR1_SQ13_4 0x00000010U /*!<Bit 4 */
+#define ADC_SQR1_SQ14 0x000003E0U /*!<SQ14[4:0] bits (14th conversion in regular sequence) */
+#define ADC_SQR1_SQ14_0 0x00000020U /*!<Bit 0 */
+#define ADC_SQR1_SQ14_1 0x00000040U /*!<Bit 1 */
+#define ADC_SQR1_SQ14_2 0x00000080U /*!<Bit 2 */
+#define ADC_SQR1_SQ14_3 0x00000100U /*!<Bit 3 */
+#define ADC_SQR1_SQ14_4 0x00000200U /*!<Bit 4 */
+#define ADC_SQR1_SQ15 0x00007C00U /*!<SQ15[4:0] bits (15th conversion in regular sequence) */
+#define ADC_SQR1_SQ15_0 0x00000400U /*!<Bit 0 */
+#define ADC_SQR1_SQ15_1 0x00000800U /*!<Bit 1 */
+#define ADC_SQR1_SQ15_2 0x00001000U /*!<Bit 2 */
+#define ADC_SQR1_SQ15_3 0x00002000U /*!<Bit 3 */
+#define ADC_SQR1_SQ15_4 0x00004000U /*!<Bit 4 */
+#define ADC_SQR1_SQ16 0x000F8000U /*!<SQ16[4:0] bits (16th conversion in regular sequence) */
+#define ADC_SQR1_SQ16_0 0x00008000U /*!<Bit 0 */
+#define ADC_SQR1_SQ16_1 0x00010000U /*!<Bit 1 */
+#define ADC_SQR1_SQ16_2 0x00020000U /*!<Bit 2 */
+#define ADC_SQR1_SQ16_3 0x00040000U /*!<Bit 3 */
+#define ADC_SQR1_SQ16_4 0x00080000U /*!<Bit 4 */
+#define ADC_SQR1_L 0x00F00000U /*!<L[3:0] bits (Regular channel sequence length) */
+#define ADC_SQR1_L_0 0x00100000U /*!<Bit 0 */
+#define ADC_SQR1_L_1 0x00200000U /*!<Bit 1 */
+#define ADC_SQR1_L_2 0x00400000U /*!<Bit 2 */
+#define ADC_SQR1_L_3 0x00800000U /*!<Bit 3 */
+
+/******************* Bit definition for ADC_SQR2 register *******************/
+#define ADC_SQR2_SQ7 0x0000001FU /*!<SQ7[4:0] bits (7th conversion in regular sequence) */
+#define ADC_SQR2_SQ7_0 0x00000001U /*!<Bit 0 */
+#define ADC_SQR2_SQ7_1 0x00000002U /*!<Bit 1 */
+#define ADC_SQR2_SQ7_2 0x00000004U /*!<Bit 2 */
+#define ADC_SQR2_SQ7_3 0x00000008U /*!<Bit 3 */
+#define ADC_SQR2_SQ7_4 0x00000010U /*!<Bit 4 */
+#define ADC_SQR2_SQ8 0x000003E0U /*!<SQ8[4:0] bits (8th conversion in regular sequence) */
+#define ADC_SQR2_SQ8_0 0x00000020U /*!<Bit 0 */
+#define ADC_SQR2_SQ8_1 0x00000040U /*!<Bit 1 */
+#define ADC_SQR2_SQ8_2 0x00000080U /*!<Bit 2 */
+#define ADC_SQR2_SQ8_3 0x00000100U /*!<Bit 3 */
+#define ADC_SQR2_SQ8_4 0x00000200U /*!<Bit 4 */
+#define ADC_SQR2_SQ9 0x00007C00U /*!<SQ9[4:0] bits (9th conversion in regular sequence) */
+#define ADC_SQR2_SQ9_0 0x00000400U /*!<Bit 0 */
+#define ADC_SQR2_SQ9_1 0x00000800U /*!<Bit 1 */
+#define ADC_SQR2_SQ9_2 0x00001000U /*!<Bit 2 */
+#define ADC_SQR2_SQ9_3 0x00002000U /*!<Bit 3 */
+#define ADC_SQR2_SQ9_4 0x00004000U /*!<Bit 4 */
+#define ADC_SQR2_SQ10 0x000F8000U /*!<SQ10[4:0] bits (10th conversion in regular sequence) */
+#define ADC_SQR2_SQ10_0 0x00008000U /*!<Bit 0 */
+#define ADC_SQR2_SQ10_1 0x00010000U /*!<Bit 1 */
+#define ADC_SQR2_SQ10_2 0x00020000U /*!<Bit 2 */
+#define ADC_SQR2_SQ10_3 0x00040000U /*!<Bit 3 */
+#define ADC_SQR2_SQ10_4 0x00080000U /*!<Bit 4 */
+#define ADC_SQR2_SQ11 0x01F00000U /*!<SQ11[4:0] bits (11th conversion in regular sequence) */
+#define ADC_SQR2_SQ11_0 0x00100000U /*!<Bit 0 */
+#define ADC_SQR2_SQ11_1 0x00200000U /*!<Bit 1 */
+#define ADC_SQR2_SQ11_2 0x00400000U /*!<Bit 2 */
+#define ADC_SQR2_SQ11_3 0x00800000U /*!<Bit 3 */
+#define ADC_SQR2_SQ11_4 0x01000000U /*!<Bit 4 */
+#define ADC_SQR2_SQ12 0x3E000000U /*!<SQ12[4:0] bits (12th conversion in regular sequence) */
+#define ADC_SQR2_SQ12_0 0x02000000U /*!<Bit 0 */
+#define ADC_SQR2_SQ12_1 0x04000000U /*!<Bit 1 */
+#define ADC_SQR2_SQ12_2 0x08000000U /*!<Bit 2 */
+#define ADC_SQR2_SQ12_3 0x10000000U /*!<Bit 3 */
+#define ADC_SQR2_SQ12_4 0x20000000U /*!<Bit 4 */
+
+/******************* Bit definition for ADC_SQR3 register *******************/
+#define ADC_SQR3_SQ1 0x0000001FU /*!<SQ1[4:0] bits (1st conversion in regular sequence) */
+#define ADC_SQR3_SQ1_0 0x00000001U /*!<Bit 0 */
+#define ADC_SQR3_SQ1_1 0x00000002U /*!<Bit 1 */
+#define ADC_SQR3_SQ1_2 0x00000004U /*!<Bit 2 */
+#define ADC_SQR3_SQ1_3 0x00000008U /*!<Bit 3 */
+#define ADC_SQR3_SQ1_4 0x00000010U /*!<Bit 4 */
+#define ADC_SQR3_SQ2 0x000003E0U /*!<SQ2[4:0] bits (2nd conversion in regular sequence) */
+#define ADC_SQR3_SQ2_0 0x00000020U /*!<Bit 0 */
+#define ADC_SQR3_SQ2_1 0x00000040U /*!<Bit 1 */
+#define ADC_SQR3_SQ2_2 0x00000080U /*!<Bit 2 */
+#define ADC_SQR3_SQ2_3 0x00000100U /*!<Bit 3 */
+#define ADC_SQR3_SQ2_4 0x00000200U /*!<Bit 4 */
+#define ADC_SQR3_SQ3 0x00007C00U /*!<SQ3[4:0] bits (3rd conversion in regular sequence) */
+#define ADC_SQR3_SQ3_0 0x00000400U /*!<Bit 0 */
+#define ADC_SQR3_SQ3_1 0x00000800U /*!<Bit 1 */
+#define ADC_SQR3_SQ3_2 0x00001000U /*!<Bit 2 */
+#define ADC_SQR3_SQ3_3 0x00002000U /*!<Bit 3 */
+#define ADC_SQR3_SQ3_4 0x00004000U /*!<Bit 4 */
+#define ADC_SQR3_SQ4 0x000F8000U /*!<SQ4[4:0] bits (4th conversion in regular sequence) */
+#define ADC_SQR3_SQ4_0 0x00008000U /*!<Bit 0 */
+#define ADC_SQR3_SQ4_1 0x00010000U /*!<Bit 1 */
+#define ADC_SQR3_SQ4_2 0x00020000U /*!<Bit 2 */
+#define ADC_SQR3_SQ4_3 0x00040000U /*!<Bit 3 */
+#define ADC_SQR3_SQ4_4 0x00080000U /*!<Bit 4 */
+#define ADC_SQR3_SQ5 0x01F00000U /*!<SQ5[4:0] bits (5th conversion in regular sequence) */
+#define ADC_SQR3_SQ5_0 0x00100000U /*!<Bit 0 */
+#define ADC_SQR3_SQ5_1 0x00200000U /*!<Bit 1 */
+#define ADC_SQR3_SQ5_2 0x00400000U /*!<Bit 2 */
+#define ADC_SQR3_SQ5_3 0x00800000U /*!<Bit 3 */
+#define ADC_SQR3_SQ5_4 0x01000000U /*!<Bit 4 */
+#define ADC_SQR3_SQ6 0x3E000000U /*!<SQ6[4:0] bits (6th conversion in regular sequence) */
+#define ADC_SQR3_SQ6_0 0x02000000U /*!<Bit 0 */
+#define ADC_SQR3_SQ6_1 0x04000000U /*!<Bit 1 */
+#define ADC_SQR3_SQ6_2 0x08000000U /*!<Bit 2 */
+#define ADC_SQR3_SQ6_3 0x10000000U /*!<Bit 3 */
+#define ADC_SQR3_SQ6_4 0x20000000U /*!<Bit 4 */
+
+/******************* Bit definition for ADC_JSQR register *******************/
+#define ADC_JSQR_JSQ1 0x0000001FU /*!<JSQ1[4:0] bits (1st conversion in injected sequence) */
+#define ADC_JSQR_JSQ1_0 0x00000001U /*!<Bit 0 */
+#define ADC_JSQR_JSQ1_1 0x00000002U /*!<Bit 1 */
+#define ADC_JSQR_JSQ1_2 0x00000004U /*!<Bit 2 */
+#define ADC_JSQR_JSQ1_3 0x00000008U /*!<Bit 3 */
+#define ADC_JSQR_JSQ1_4 0x00000010U /*!<Bit 4 */
+#define ADC_JSQR_JSQ2 0x000003E0U /*!<JSQ2[4:0] bits (2nd conversion in injected sequence) */
+#define ADC_JSQR_JSQ2_0 0x00000020U /*!<Bit 0 */
+#define ADC_JSQR_JSQ2_1 0x00000040U /*!<Bit 1 */
+#define ADC_JSQR_JSQ2_2 0x00000080U /*!<Bit 2 */
+#define ADC_JSQR_JSQ2_3 0x00000100U /*!<Bit 3 */
+#define ADC_JSQR_JSQ2_4 0x00000200U /*!<Bit 4 */
+#define ADC_JSQR_JSQ3 0x00007C00U /*!<JSQ3[4:0] bits (3rd conversion in injected sequence) */
+#define ADC_JSQR_JSQ3_0 0x00000400U /*!<Bit 0 */
+#define ADC_JSQR_JSQ3_1 0x00000800U /*!<Bit 1 */
+#define ADC_JSQR_JSQ3_2 0x00001000U /*!<Bit 2 */
+#define ADC_JSQR_JSQ3_3 0x00002000U /*!<Bit 3 */
+#define ADC_JSQR_JSQ3_4 0x00004000U /*!<Bit 4 */
+#define ADC_JSQR_JSQ4 0x000F8000U /*!<JSQ4[4:0] bits (4th conversion in injected sequence) */
+#define ADC_JSQR_JSQ4_0 0x00008000U /*!<Bit 0 */
+#define ADC_JSQR_JSQ4_1 0x00010000U /*!<Bit 1 */
+#define ADC_JSQR_JSQ4_2 0x00020000U /*!<Bit 2 */
+#define ADC_JSQR_JSQ4_3 0x00040000U /*!<Bit 3 */
+#define ADC_JSQR_JSQ4_4 0x00080000U /*!<Bit 4 */
+#define ADC_JSQR_JL 0x00300000U /*!<JL[1:0] bits (Injected Sequence length) */
+#define ADC_JSQR_JL_0 0x00100000U /*!<Bit 0 */
+#define ADC_JSQR_JL_1 0x00200000U /*!<Bit 1 */
+
+/******************* Bit definition for ADC_JDR1 register *******************/
+#define ADC_JDR1_JDATA 0xFFFFU /*!<Injected data */
+
+/******************* Bit definition for ADC_JDR2 register *******************/
+#define ADC_JDR2_JDATA 0xFFFFU /*!<Injected data */
+
+/******************* Bit definition for ADC_JDR3 register *******************/
+#define ADC_JDR3_JDATA 0xFFFFU /*!<Injected data */
+
+/******************* Bit definition for ADC_JDR4 register *******************/
+#define ADC_JDR4_JDATA 0xFFFFU /*!<Injected data */
+
+/******************** Bit definition for ADC_DR register ********************/
+#define ADC_DR_DATA 0x0000FFFFU /*!<Regular data */
+#define ADC_DR_ADC2DATA 0xFFFF0000U /*!<ADC2 data */
+
+/******************* Bit definition for ADC_CSR register ********************/
+#define ADC_CSR_AWD1 0x00000001U /*!<ADC1 Analog watchdog flag */
+#define ADC_CSR_EOC1 0x00000002U /*!<ADC1 End of conversion */
+#define ADC_CSR_JEOC1 0x00000004U /*!<ADC1 Injected channel end of conversion */
+#define ADC_CSR_JSTRT1 0x00000008U /*!<ADC1 Injected channel Start flag */
+#define ADC_CSR_STRT1 0x00000010U /*!<ADC1 Regular channel Start flag */
+#define ADC_CSR_DOVR1 0x00000020U /*!<ADC1 DMA overrun flag */
+#define ADC_CSR_AWD2 0x00000100U /*!<ADC2 Analog watchdog flag */
+#define ADC_CSR_EOC2 0x00000200U /*!<ADC2 End of conversion */
+#define ADC_CSR_JEOC2 0x00000400U /*!<ADC2 Injected channel end of conversion */
+#define ADC_CSR_JSTRT2 0x00000800U /*!<ADC2 Injected channel Start flag */
+#define ADC_CSR_STRT2 0x00001000U /*!<ADC2 Regular channel Start flag */
+#define ADC_CSR_DOVR2 0x00002000U /*!<ADC2 DMA overrun flag */
+
+/******************* Bit definition for ADC_CCR register ********************/
+#define ADC_CCR_MULTI 0x0000001FU /*!<MULTI[4:0] bits (Multi-ADC mode selection) */
+#define ADC_CCR_MULTI_0 0x00000001U /*!<Bit 0 */
+#define ADC_CCR_MULTI_1 0x00000002U /*!<Bit 1 */
+#define ADC_CCR_MULTI_2 0x00000004U /*!<Bit 2 */
+#define ADC_CCR_MULTI_3 0x00000008U /*!<Bit 3 */
+#define ADC_CCR_MULTI_4 0x00000010U /*!<Bit 4 */
+#define ADC_CCR_DELAY 0x00000F00U /*!<DELAY[3:0] bits (Delay between 2 sampling phases) */
+#define ADC_CCR_DELAY_0 0x00000100U /*!<Bit 0 */
+#define ADC_CCR_DELAY_1 0x00000200U /*!<Bit 1 */
+#define ADC_CCR_DELAY_2 0x00000400U /*!<Bit 2 */
+#define ADC_CCR_DELAY_3 0x00000800U /*!<Bit 3 */
+#define ADC_CCR_DDS 0x00002000U /*!<DMA disable selection (Multi-ADC mode) */
+#define ADC_CCR_DMA 0x0000C000U /*!<DMA[1:0] bits (Direct Memory Access mode for multimode) */
+#define ADC_CCR_DMA_0 0x00004000U /*!<Bit 0 */
+#define ADC_CCR_DMA_1 0x00008000U /*!<Bit 1 */
+#define ADC_CCR_ADCPRE 0x00030000U /*!<ADCPRE[1:0] bits (ADC prescaler) */
+#define ADC_CCR_ADCPRE_0 0x00010000U /*!<Bit 0 */
+#define ADC_CCR_ADCPRE_1 0x00020000U /*!<Bit 1 */
+#define ADC_CCR_VBATE 0x00400000U /*!<VBAT Enable */
+#define ADC_CCR_TSVREFE 0x00800000U /*!<Temperature Sensor and VREFINT Enable */
+
+/******************* Bit definition for ADC_CDR register ********************/
+#define ADC_CDR_DATA1 0x0000FFFFU /*!<1st data of a pair of regular conversions */
+#define ADC_CDR_DATA2 0xFFFF0000U /*!<2nd data of a pair of regular conversions */
+
+/******************************************************************************/
+/* */
+/* Controller Area Network */
+/* */
+/******************************************************************************/
+/*!<CAN control and status registers */
+/******************* Bit definition for CAN_MCR register ********************/
+#define CAN_MCR_INRQ 0x00000001U /*!<Initialization Request */
+#define CAN_MCR_SLEEP 0x00000002U /*!<Sleep Mode Request */
+#define CAN_MCR_TXFP 0x00000004U /*!<Transmit FIFO Priority */
+#define CAN_MCR_RFLM 0x00000008U /*!<Receive FIFO Locked Mode */
+#define CAN_MCR_NART 0x00000010U /*!<No Automatic Retransmission */
+#define CAN_MCR_AWUM 0x00000020U /*!<Automatic Wakeup Mode */
+#define CAN_MCR_ABOM 0x00000040U /*!<Automatic Bus-Off Management */
+#define CAN_MCR_TTCM 0x00000080U /*!<Time Triggered Communication Mode */
+#define CAN_MCR_RESET 0x00008000U /*!<bxCAN software master reset */
+#define CAN_MCR_DBF 0x00010000U /*!<bxCAN Debug freeze */
+/******************* Bit definition for CAN_MSR register ********************/
+#define CAN_MSR_INAK 0x0001U /*!<Initialization Acknowledge */
+#define CAN_MSR_SLAK 0x0002U /*!<Sleep Acknowledge */
+#define CAN_MSR_ERRI 0x0004U /*!<Error Interrupt */
+#define CAN_MSR_WKUI 0x0008U /*!<Wakeup Interrupt */
+#define CAN_MSR_SLAKI 0x0010U /*!<Sleep Acknowledge Interrupt */
+#define CAN_MSR_TXM 0x0100U /*!<Transmit Mode */
+#define CAN_MSR_RXM 0x0200U /*!<Receive Mode */
+#define CAN_MSR_SAMP 0x0400U /*!<Last Sample Point */
+#define CAN_MSR_RX 0x0800U /*!<CAN Rx Signal */
+
+/******************* Bit definition for CAN_TSR register ********************/
+#define CAN_TSR_RQCP0 0x00000001U /*!<Request Completed Mailbox0 */
+#define CAN_TSR_TXOK0 0x00000002U /*!<Transmission OK of Mailbox0 */
+#define CAN_TSR_ALST0 0x00000004U /*!<Arbitration Lost for Mailbox0 */
+#define CAN_TSR_TERR0 0x00000008U /*!<Transmission Error of Mailbox0 */
+#define CAN_TSR_ABRQ0 0x00000080U /*!<Abort Request for Mailbox0 */
+#define CAN_TSR_RQCP1 0x00000100U /*!<Request Completed Mailbox1 */
+#define CAN_TSR_TXOK1 0x00000200U /*!<Transmission OK of Mailbox1 */
+#define CAN_TSR_ALST1 0x00000400U /*!<Arbitration Lost for Mailbox1 */
+#define CAN_TSR_TERR1 0x00000800U /*!<Transmission Error of Mailbox1 */
+#define CAN_TSR_ABRQ1 0x00008000U /*!<Abort Request for Mailbox 1 */
+#define CAN_TSR_RQCP2 0x00010000U /*!<Request Completed Mailbox2 */
+#define CAN_TSR_TXOK2 0x00020000U /*!<Transmission OK of Mailbox 2 */
+#define CAN_TSR_ALST2 0x00040000U /*!<Arbitration Lost for mailbox 2 */
+#define CAN_TSR_TERR2 0x00080000U /*!<Transmission Error of Mailbox 2 */
+#define CAN_TSR_ABRQ2 0x00800000U /*!<Abort Request for Mailbox 2 */
+#define CAN_TSR_CODE 0x03000000U /*!<Mailbox Code */
+
+#define CAN_TSR_TME 0x1C000000U /*!<TME[2:0] bits */
+#define CAN_TSR_TME0 0x04000000U /*!<Transmit Mailbox 0 Empty */
+#define CAN_TSR_TME1 0x08000000U /*!<Transmit Mailbox 1 Empty */
+#define CAN_TSR_TME2 0x10000000U /*!<Transmit Mailbox 2 Empty */
+
+#define CAN_TSR_LOW 0xE0000000U /*!<LOW[2:0] bits */
+#define CAN_TSR_LOW0 0x20000000U /*!<Lowest Priority Flag for Mailbox 0 */
+#define CAN_TSR_LOW1 0x40000000U /*!<Lowest Priority Flag for Mailbox 1 */
+#define CAN_TSR_LOW2 0x80000000U /*!<Lowest Priority Flag for Mailbox 2 */
+
+/******************* Bit definition for CAN_RF0R register *******************/
+#define CAN_RF0R_FMP0 0x03U /*!<FIFO 0 Message Pending */
+#define CAN_RF0R_FULL0 0x08U /*!<FIFO 0 Full */
+#define CAN_RF0R_FOVR0 0x10U /*!<FIFO 0 Overrun */
+#define CAN_RF0R_RFOM0 0x20U /*!<Release FIFO 0 Output Mailbox */
+
+/******************* Bit definition for CAN_RF1R register *******************/
+#define CAN_RF1R_FMP1 0x03U /*!<FIFO 1 Message Pending */
+#define CAN_RF1R_FULL1 0x08U /*!<FIFO 1 Full */
+#define CAN_RF1R_FOVR1 0x10U /*!<FIFO 1 Overrun */
+#define CAN_RF1R_RFOM1 0x20U /*!<Release FIFO 1 Output Mailbox */
+
+/******************** Bit definition for CAN_IER register *******************/
+#define CAN_IER_TMEIE 0x00000001U /*!<Transmit Mailbox Empty Interrupt Enable */
+#define CAN_IER_FMPIE0 0x00000002U /*!<FIFO Message Pending Interrupt Enable */
+#define CAN_IER_FFIE0 0x00000004U /*!<FIFO Full Interrupt Enable */
+#define CAN_IER_FOVIE0 0x00000008U /*!<FIFO Overrun Interrupt Enable */
+#define CAN_IER_FMPIE1 0x00000010U /*!<FIFO Message Pending Interrupt Enable */
+#define CAN_IER_FFIE1 0x00000020U /*!<FIFO Full Interrupt Enable */
+#define CAN_IER_FOVIE1 0x00000040U /*!<FIFO Overrun Interrupt Enable */
+#define CAN_IER_EWGIE 0x00000100U /*!<Error Warning Interrupt Enable */
+#define CAN_IER_EPVIE 0x00000200U /*!<Error Passive Interrupt Enable */
+#define CAN_IER_BOFIE 0x00000400U /*!<Bus-Off Interrupt Enable */
+#define CAN_IER_LECIE 0x00000800U /*!<Last Error Code Interrupt Enable */
+#define CAN_IER_ERRIE 0x00008000U /*!<Error Interrupt Enable */
+#define CAN_IER_WKUIE 0x00010000U /*!<Wakeup Interrupt Enable */
+#define CAN_IER_SLKIE 0x00020000U /*!<Sleep Interrupt Enable */
+#define CAN_IER_EWGIE 0x00000100U /*!<Error warning interrupt enable */
+#define CAN_IER_EPVIE 0x00000200U /*!<Error passive interrupt enable */
+#define CAN_IER_BOFIE 0x00000400U /*!<Bus-off interrupt enable */
+#define CAN_IER_LECIE 0x00000800U /*!<Last error code interrupt enable */
+#define CAN_IER_ERRIE 0x00008000U /*!<Error interrupt enable */
+
+
+/******************** Bit definition for CAN_ESR register *******************/
+#define CAN_ESR_EWGF 0x00000001U /*!<Error Warning Flag */
+#define CAN_ESR_EPVF 0x00000002U /*!<Error Passive Flag */
+#define CAN_ESR_BOFF 0x00000004U /*!<Bus-Off Flag */
+
+#define CAN_ESR_LEC 0x00000070U /*!<LEC[2:0] bits (Last Error Code) */
+#define CAN_ESR_LEC_0 0x00000010U /*!<Bit 0 */
+#define CAN_ESR_LEC_1 0x00000020U /*!<Bit 1 */
+#define CAN_ESR_LEC_2 0x00000040U /*!<Bit 2 */
+
+#define CAN_ESR_TEC 0x00FF0000U /*!<Least significant byte of the 9-bit Transmit Error Counter */
+#define CAN_ESR_REC 0xFF000000U /*!<Receive Error Counter */
+
+/******************* Bit definition for CAN_BTR register ********************/
+#define CAN_BTR_BRP 0x000003FFU /*!<Baud Rate Prescaler */
+#define CAN_BTR_TS1 0x000F0000U /*!<Time Segment 1 */
+#define CAN_BTR_TS1_0 0x00010000U /*!<Bit 0 */
+#define CAN_BTR_TS1_1 0x00020000U /*!<Bit 1 */
+#define CAN_BTR_TS1_2 0x00040000U /*!<Bit 2 */
+#define CAN_BTR_TS1_3 0x00080000U /*!<Bit 3 */
+#define CAN_BTR_TS2 0x00700000U /*!<Time Segment 2 */
+#define CAN_BTR_TS2_0 0x00100000U /*!<Bit 0 */
+#define CAN_BTR_TS2_1 0x00200000U /*!<Bit 1 */
+#define CAN_BTR_TS2_2 0x00400000U /*!<Bit 2 */
+#define CAN_BTR_SJW 0x03000000U /*!<Resynchronization Jump Width */
+#define CAN_BTR_SJW_0 0x01000000U /*!<Bit 0 */
+#define CAN_BTR_SJW_1 0x02000000U /*!<Bit 1 */
+#define CAN_BTR_LBKM 0x40000000U /*!<Loop Back Mode (Debug) */
+#define CAN_BTR_SILM 0x80000000U /*!<Silent Mode */
+
+
+/*!<Mailbox registers */
+/****************** Bit definition for CAN_TI0R register ********************/
+#define CAN_TI0R_TXRQ 0x00000001U /*!<Transmit Mailbox Request */
+#define CAN_TI0R_RTR 0x00000002U /*!<Remote Transmission Request */
+#define CAN_TI0R_IDE 0x00000004U /*!<Identifier Extension */
+#define CAN_TI0R_EXID 0x001FFFF8U /*!<Extended Identifier */
+#define CAN_TI0R_STID 0xFFE00000U /*!<Standard Identifier or Extended Identifier */
+
+/****************** Bit definition for CAN_TDT0R register *******************/
+#define CAN_TDT0R_DLC 0x0000000FU /*!<Data Length Code */
+#define CAN_TDT0R_TGT 0x00000100U /*!<Transmit Global Time */
+#define CAN_TDT0R_TIME 0xFFFF0000U /*!<Message Time Stamp */
+
+/****************** Bit definition for CAN_TDL0R register *******************/
+#define CAN_TDL0R_DATA0 0x000000FFU /*!<Data byte 0 */
+#define CAN_TDL0R_DATA1 0x0000FF00U /*!<Data byte 1 */
+#define CAN_TDL0R_DATA2 0x00FF0000U /*!<Data byte 2 */
+#define CAN_TDL0R_DATA3 0xFF000000U /*!<Data byte 3 */
+
+/****************** Bit definition for CAN_TDH0R register *******************/
+#define CAN_TDH0R_DATA4 0x000000FFU /*!<Data byte 4 */
+#define CAN_TDH0R_DATA5 0x0000FF00U /*!<Data byte 5 */
+#define CAN_TDH0R_DATA6 0x00FF0000U /*!<Data byte 6 */
+#define CAN_TDH0R_DATA7 0xFF000000U /*!<Data byte 7 */
+
+/******************* Bit definition for CAN_TI1R register *******************/
+#define CAN_TI1R_TXRQ 0x00000001U /*!<Transmit Mailbox Request */
+#define CAN_TI1R_RTR 0x00000002U /*!<Remote Transmission Request */
+#define CAN_TI1R_IDE 0x00000004U /*!<Identifier Extension */
+#define CAN_TI1R_EXID 0x001FFFF8U /*!<Extended Identifier */
+#define CAN_TI1R_STID 0xFFE00000U /*!<Standard Identifier or Extended Identifier */
+
+/******************* Bit definition for CAN_TDT1R register ******************/
+#define CAN_TDT1R_DLC 0x0000000FU /*!<Data Length Code */
+#define CAN_TDT1R_TGT 0x00000100U /*!<Transmit Global Time */
+#define CAN_TDT1R_TIME 0xFFFF0000U /*!<Message Time Stamp */
+
+/******************* Bit definition for CAN_TDL1R register ******************/
+#define CAN_TDL1R_DATA0 0x000000FFU /*!<Data byte 0 */
+#define CAN_TDL1R_DATA1 0x0000FF00U /*!<Data byte 1 */
+#define CAN_TDL1R_DATA2 0x00FF0000U /*!<Data byte 2 */
+#define CAN_TDL1R_DATA3 0xFF000000U /*!<Data byte 3 */
+
+/******************* Bit definition for CAN_TDH1R register ******************/
+#define CAN_TDH1R_DATA4 0x000000FFU /*!<Data byte 4 */
+#define CAN_TDH1R_DATA5 0x0000FF00U /*!<Data byte 5 */
+#define CAN_TDH1R_DATA6 0x00FF0000U /*!<Data byte 6 */
+#define CAN_TDH1R_DATA7 0xFF000000U /*!<Data byte 7 */
+
+/******************* Bit definition for CAN_TI2R register *******************/
+#define CAN_TI2R_TXRQ 0x00000001U /*!<Transmit Mailbox Request */
+#define CAN_TI2R_RTR 0x00000002U /*!<Remote Transmission Request */
+#define CAN_TI2R_IDE 0x00000004U /*!<Identifier Extension */
+#define CAN_TI2R_EXID 0x001FFFF8U /*!<Extended identifier */
+#define CAN_TI2R_STID 0xFFE00000U /*!<Standard Identifier or Extended Identifier */
+
+/******************* Bit definition for CAN_TDT2R register ******************/
+#define CAN_TDT2R_DLC 0x0000000FU /*!<Data Length Code */
+#define CAN_TDT2R_TGT 0x00000100U /*!<Transmit Global Time */
+#define CAN_TDT2R_TIME 0xFFFF0000U /*!<Message Time Stamp */
+
+/******************* Bit definition for CAN_TDL2R register ******************/
+#define CAN_TDL2R_DATA0 0x000000FFU /*!<Data byte 0 */
+#define CAN_TDL2R_DATA1 0x0000FF00U /*!<Data byte 1 */
+#define CAN_TDL2R_DATA2 0x00FF0000U /*!<Data byte 2 */
+#define CAN_TDL2R_DATA3 0xFF000000U /*!<Data byte 3 */
+
+/******************* Bit definition for CAN_TDH2R register ******************/
+#define CAN_TDH2R_DATA4 0x000000FFU /*!<Data byte 4 */
+#define CAN_TDH2R_DATA5 0x0000FF00U /*!<Data byte 5 */
+#define CAN_TDH2R_DATA6 0x00FF0000U /*!<Data byte 6 */
+#define CAN_TDH2R_DATA7 0xFF000000U /*!<Data byte 7 */
+
+/******************* Bit definition for CAN_RI0R register *******************/
+#define CAN_RI0R_RTR 0x00000002U /*!<Remote Transmission Request */
+#define CAN_RI0R_IDE 0x00000004U /*!<Identifier Extension */
+#define CAN_RI0R_EXID 0x001FFFF8U /*!<Extended Identifier */
+#define CAN_RI0R_STID 0xFFE00000U /*!<Standard Identifier or Extended Identifier */
+
+/******************* Bit definition for CAN_RDT0R register ******************/
+#define CAN_RDT0R_DLC 0x0000000FU /*!<Data Length Code */
+#define CAN_RDT0R_FMI 0x0000FF00U /*!<Filter Match Index */
+#define CAN_RDT0R_TIME 0xFFFF0000U /*!<Message Time Stamp */
+
+/******************* Bit definition for CAN_RDL0R register ******************/
+#define CAN_RDL0R_DATA0 0x000000FFU /*!<Data byte 0 */
+#define CAN_RDL0R_DATA1 0x0000FF00U /*!<Data byte 1 */
+#define CAN_RDL0R_DATA2 0x00FF0000U /*!<Data byte 2 */
+#define CAN_RDL0R_DATA3 0xFF000000U /*!<Data byte 3 */
+
+/******************* Bit definition for CAN_RDH0R register ******************/
+#define CAN_RDH0R_DATA4 0x000000FFU /*!<Data byte 4 */
+#define CAN_RDH0R_DATA5 0x0000FF00U /*!<Data byte 5 */
+#define CAN_RDH0R_DATA6 0x00FF0000U /*!<Data byte 6 */
+#define CAN_RDH0R_DATA7 0xFF000000U /*!<Data byte 7 */
+
+/******************* Bit definition for CAN_RI1R register *******************/
+#define CAN_RI1R_RTR 0x00000002U /*!<Remote Transmission Request */
+#define CAN_RI1R_IDE 0x00000004U /*!<Identifier Extension */
+#define CAN_RI1R_EXID 0x001FFFF8U /*!<Extended identifier */
+#define CAN_RI1R_STID 0xFFE00000U /*!<Standard Identifier or Extended Identifier */
+
+/******************* Bit definition for CAN_RDT1R register ******************/
+#define CAN_RDT1R_DLC 0x0000000FU /*!<Data Length Code */
+#define CAN_RDT1R_FMI 0x0000FF00U /*!<Filter Match Index */
+#define CAN_RDT1R_TIME 0xFFFF0000U /*!<Message Time Stamp */
+
+/******************* Bit definition for CAN_RDL1R register ******************/
+#define CAN_RDL1R_DATA0 0x000000FFU /*!<Data byte 0 */
+#define CAN_RDL1R_DATA1 0x0000FF00U /*!<Data byte 1 */
+#define CAN_RDL1R_DATA2 0x00FF0000U /*!<Data byte 2 */
+#define CAN_RDL1R_DATA3 0xFF000000U /*!<Data byte 3 */
+
+/******************* Bit definition for CAN_RDH1R register ******************/
+#define CAN_RDH1R_DATA4 0x000000FFU /*!<Data byte 4 */
+#define CAN_RDH1R_DATA5 0x0000FF00U /*!<Data byte 5 */
+#define CAN_RDH1R_DATA6 0x00FF0000U /*!<Data byte 6 */
+#define CAN_RDH1R_DATA7 0xFF000000U /*!<Data byte 7 */
+
+/*!<CAN filter registers */
+/******************* Bit definition for CAN_FMR register ********************/
+#define CAN_FMR_FINIT 0x01U /*!<Filter Init Mode */
+#define CAN_FMR_CAN2SB 0x00003F00U /*!<CAN2 start bank */
+
+/******************* Bit definition for CAN_FM1R register *******************/
+#define CAN_FM1R_FBM 0x0FFFFFFFU /*!<Filter Mode */
+#define CAN_FM1R_FBM0 0x00000001U /*!<Filter Init Mode bit 0 */
+#define CAN_FM1R_FBM1 0x00000002U /*!<Filter Init Mode bit 1 */
+#define CAN_FM1R_FBM2 0x00000004U /*!<Filter Init Mode bit 2 */
+#define CAN_FM1R_FBM3 0x00000008U /*!<Filter Init Mode bit 3 */
+#define CAN_FM1R_FBM4 0x00000010U /*!<Filter Init Mode bit 4 */
+#define CAN_FM1R_FBM5 0x00000020U /*!<Filter Init Mode bit 5 */
+#define CAN_FM1R_FBM6 0x00000040U /*!<Filter Init Mode bit 6 */
+#define CAN_FM1R_FBM7 0x00000080U /*!<Filter Init Mode bit 7 */
+#define CAN_FM1R_FBM8 0x00000100U /*!<Filter Init Mode bit 8 */
+#define CAN_FM1R_FBM9 0x00000200U /*!<Filter Init Mode bit 9 */
+#define CAN_FM1R_FBM10 0x00000400U /*!<Filter Init Mode bit 10 */
+#define CAN_FM1R_FBM11 0x00000800U /*!<Filter Init Mode bit 11 */
+#define CAN_FM1R_FBM12 0x00001000U /*!<Filter Init Mode bit 12 */
+#define CAN_FM1R_FBM13 0x00002000U /*!<Filter Init Mode bit 13 */
+#define CAN_FM1R_FBM14 0x00004000U /*!<Filter Init Mode bit 14 */
+#define CAN_FM1R_FBM15 0x00008000U /*!<Filter Init Mode bit 15 */
+#define CAN_FM1R_FBM16 0x00010000U /*!<Filter Init Mode bit 16 */
+#define CAN_FM1R_FBM17 0x00020000U /*!<Filter Init Mode bit 17 */
+#define CAN_FM1R_FBM18 0x00040000U /*!<Filter Init Mode bit 18 */
+#define CAN_FM1R_FBM19 0x00080000U /*!<Filter Init Mode bit 19 */
+#define CAN_FM1R_FBM20 0x00100000U /*!<Filter Init Mode bit 20 */
+#define CAN_FM1R_FBM21 0x00200000U /*!<Filter Init Mode bit 21 */
+#define CAN_FM1R_FBM22 0x00400000U /*!<Filter Init Mode bit 22 */
+#define CAN_FM1R_FBM23 0x00800000U /*!<Filter Init Mode bit 23 */
+#define CAN_FM1R_FBM24 0x01000000U /*!<Filter Init Mode bit 24 */
+#define CAN_FM1R_FBM25 0x02000000U /*!<Filter Init Mode bit 25 */
+#define CAN_FM1R_FBM26 0x04000000U /*!<Filter Init Mode bit 26 */
+#define CAN_FM1R_FBM27 0x08000000U /*!<Filter Init Mode bit 27 */
+
+/******************* Bit definition for CAN_FS1R register *******************/
+#define CAN_FS1R_FSC 0x0FFFFFFFU /*!<Filter Scale Configuration */
+#define CAN_FS1R_FSC0 0x00000001U /*!<Filter Scale Configuration bit 0 */
+#define CAN_FS1R_FSC1 0x00000002U /*!<Filter Scale Configuration bit 1 */
+#define CAN_FS1R_FSC2 0x00000004U /*!<Filter Scale Configuration bit 2 */
+#define CAN_FS1R_FSC3 0x00000008U /*!<Filter Scale Configuration bit 3 */
+#define CAN_FS1R_FSC4 0x00000010U /*!<Filter Scale Configuration bit 4 */
+#define CAN_FS1R_FSC5 0x00000020U /*!<Filter Scale Configuration bit 5 */
+#define CAN_FS1R_FSC6 0x00000040U /*!<Filter Scale Configuration bit 6 */
+#define CAN_FS1R_FSC7 0x00000080U /*!<Filter Scale Configuration bit 7 */
+#define CAN_FS1R_FSC8 0x00000100U /*!<Filter Scale Configuration bit 8 */
+#define CAN_FS1R_FSC9 0x00000200U /*!<Filter Scale Configuration bit 9 */
+#define CAN_FS1R_FSC10 0x00000400U /*!<Filter Scale Configuration bit 10 */
+#define CAN_FS1R_FSC11 0x00000800U /*!<Filter Scale Configuration bit 11 */
+#define CAN_FS1R_FSC12 0x00001000U /*!<Filter Scale Configuration bit 12 */
+#define CAN_FS1R_FSC13 0x00002000U /*!<Filter Scale Configuration bit 13 */
+#define CAN_FS1R_FSC14 0x00004000U /*!<Filter Scale Configuration bit 14 */
+#define CAN_FS1R_FSC15 0x00008000U /*!<Filter Scale Configuration bit 15 */
+#define CAN_FS1R_FSC16 0x00010000U /*!<Filter Scale Configuration bit 16 */
+#define CAN_FS1R_FSC17 0x00020000U /*!<Filter Scale Configuration bit 17 */
+#define CAN_FS1R_FSC18 0x00040000U /*!<Filter Scale Configuration bit 18 */
+#define CAN_FS1R_FSC19 0x00080000U /*!<Filter Scale Configuration bit 19 */
+#define CAN_FS1R_FSC20 0x00100000U /*!<Filter Scale Configuration bit 20 */
+#define CAN_FS1R_FSC21 0x00200000U /*!<Filter Scale Configuration bit 21 */
+#define CAN_FS1R_FSC22 0x00400000U /*!<Filter Scale Configuration bit 22 */
+#define CAN_FS1R_FSC23 0x00800000U /*!<Filter Scale Configuration bit 23 */
+#define CAN_FS1R_FSC24 0x01000000U /*!<Filter Scale Configuration bit 24 */
+#define CAN_FS1R_FSC25 0x02000000U /*!<Filter Scale Configuration bit 25 */
+#define CAN_FS1R_FSC26 0x04000000U /*!<Filter Scale Configuration bit 26 */
+#define CAN_FS1R_FSC27 0x08000000U /*!<Filter Scale Configuration bit 27 */
+
+/****************** Bit definition for CAN_FFA1R register *******************/
+#define CAN_FFA1R_FFA 0x0FFFFFFFU /*!<Filter FIFO Assignment */
+#define CAN_FFA1R_FFA0 0x00000001U /*!<Filter FIFO Assignment bit 0 */
+#define CAN_FFA1R_FFA1 0x00000002U /*!<Filter FIFO Assignment bit 1 */
+#define CAN_FFA1R_FFA2 0x00000004U /*!<Filter FIFO Assignment bit 2 */
+#define CAN_FFA1R_FFA3 0x00000008U /*!<Filter FIFO Assignment bit 3 */
+#define CAN_FFA1R_FFA4 0x00000010U /*!<Filter FIFO Assignment bit 4 */
+#define CAN_FFA1R_FFA5 0x00000020U /*!<Filter FIFO Assignment bit 5 */
+#define CAN_FFA1R_FFA6 0x00000040U /*!<Filter FIFO Assignment bit 6 */
+#define CAN_FFA1R_FFA7 0x00000080U /*!<Filter FIFO Assignment bit 7 */
+#define CAN_FFA1R_FFA8 0x00000100U /*!<Filter FIFO Assignment bit 8 */
+#define CAN_FFA1R_FFA9 0x00000200U /*!<Filter FIFO Assignment bit 9 */
+#define CAN_FFA1R_FFA10 0x00000400U /*!<Filter FIFO Assignment bit 10 */
+#define CAN_FFA1R_FFA11 0x00000800U /*!<Filter FIFO Assignment bit 11 */
+#define CAN_FFA1R_FFA12 0x00001000U /*!<Filter FIFO Assignment bit 12 */
+#define CAN_FFA1R_FFA13 0x00002000U /*!<Filter FIFO Assignment bit 13 */
+#define CAN_FFA1R_FFA14 0x00004000U /*!<Filter FIFO Assignment bit 14 */
+#define CAN_FFA1R_FFA15 0x00008000U /*!<Filter FIFO Assignment bit 15 */
+#define CAN_FFA1R_FFA16 0x00010000U /*!<Filter FIFO Assignment bit 16 */
+#define CAN_FFA1R_FFA17 0x00020000U /*!<Filter FIFO Assignment bit 17 */
+#define CAN_FFA1R_FFA18 0x00040000U /*!<Filter FIFO Assignment bit 18 */
+#define CAN_FFA1R_FFA19 0x00080000U /*!<Filter FIFO Assignment bit 19 */
+#define CAN_FFA1R_FFA20 0x00100000U /*!<Filter FIFO Assignment bit 20 */
+#define CAN_FFA1R_FFA21 0x00200000U /*!<Filter FIFO Assignment bit 21 */
+#define CAN_FFA1R_FFA22 0x00400000U /*!<Filter FIFO Assignment bit 22 */
+#define CAN_FFA1R_FFA23 0x00800000U /*!<Filter FIFO Assignment bit 23 */
+#define CAN_FFA1R_FFA24 0x01000000U /*!<Filter FIFO Assignment bit 24 */
+#define CAN_FFA1R_FFA25 0x02000000U /*!<Filter FIFO Assignment bit 25 */
+#define CAN_FFA1R_FFA26 0x04000000U /*!<Filter FIFO Assignment bit 26 */
+#define CAN_FFA1R_FFA27 0x08000000U /*!<Filter FIFO Assignment bit 27 */
+
+/******************* Bit definition for CAN_FA1R register *******************/
+#define CAN_FA1R_FACT 0x0FFFFFFFU /*!<Filter Active */
+#define CAN_FA1R_FACT0 0x00000001U /*!<Filter Active bit 0 */
+#define CAN_FA1R_FACT1 0x00000002U /*!<Filter Active bit 1 */
+#define CAN_FA1R_FACT2 0x00000004U /*!<Filter Active bit 2 */
+#define CAN_FA1R_FACT3 0x00000008U /*!<Filter Active bit 3 */
+#define CAN_FA1R_FACT4 0x00000010U /*!<Filter Active bit 4 */
+#define CAN_FA1R_FACT5 0x00000020U /*!<Filter Active bit 5 */
+#define CAN_FA1R_FACT6 0x00000040U /*!<Filter Active bit 6 */
+#define CAN_FA1R_FACT7 0x00000080U /*!<Filter Active bit 7 */
+#define CAN_FA1R_FACT8 0x00000100U /*!<Filter Active bit 8 */
+#define CAN_FA1R_FACT9 0x00000200U /*!<Filter Active bit 9 */
+#define CAN_FA1R_FACT10 0x00000400U /*!<Filter Active bit 10 */
+#define CAN_FA1R_FACT11 0x00000800U /*!<Filter Active bit 11 */
+#define CAN_FA1R_FACT12 0x00001000U /*!<Filter Active bit 12 */
+#define CAN_FA1R_FACT13 0x00002000U /*!<Filter Active bit 13 */
+#define CAN_FA1R_FACT14 0x00004000U /*!<Filter Active bit 14 */
+#define CAN_FA1R_FACT15 0x00008000U /*!<Filter Active bit 15 */
+#define CAN_FA1R_FACT16 0x00010000U /*!<Filter Active bit 16 */
+#define CAN_FA1R_FACT17 0x00020000U /*!<Filter Active bit 17 */
+#define CAN_FA1R_FACT18 0x00040000U /*!<Filter Active bit 18 */
+#define CAN_FA1R_FACT19 0x00080000U /*!<Filter Active bit 19 */
+#define CAN_FA1R_FACT20 0x00100000U /*!<Filter Active bit 20 */
+#define CAN_FA1R_FACT21 0x00200000U /*!<Filter Active bit 21 */
+#define CAN_FA1R_FACT22 0x00400000U /*!<Filter Active bit 22 */
+#define CAN_FA1R_FACT23 0x00800000U /*!<Filter Active bit 23 */
+#define CAN_FA1R_FACT24 0x01000000U /*!<Filter Active bit 24 */
+#define CAN_FA1R_FACT25 0x02000000U /*!<Filter Active bit 25 */
+#define CAN_FA1R_FACT26 0x04000000U /*!<Filter Active bit 26 */
+#define CAN_FA1R_FACT27 0x08000000U /*!<Filter Active bit 27 */
+
+/******************* Bit definition for CAN_F0R1 register *******************/
+#define CAN_F0R1_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F0R1_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F0R1_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F0R1_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F0R1_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F0R1_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F0R1_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F0R1_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F0R1_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F0R1_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F0R1_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F0R1_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F0R1_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F0R1_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F0R1_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F0R1_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F0R1_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F0R1_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F0R1_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F0R1_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F0R1_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F0R1_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F0R1_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F0R1_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F0R1_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F0R1_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F0R1_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F0R1_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F0R1_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F0R1_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F0R1_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F0R1_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F1R1 register *******************/
+#define CAN_F1R1_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F1R1_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F1R1_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F1R1_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F1R1_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F1R1_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F1R1_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F1R1_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F1R1_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F1R1_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F1R1_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F1R1_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F1R1_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F1R1_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F1R1_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F1R1_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F1R1_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F1R1_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F1R1_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F1R1_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F1R1_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F1R1_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F1R1_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F1R1_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F1R1_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F1R1_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F1R1_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F1R1_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F1R1_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F1R1_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F1R1_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F1R1_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F2R1 register *******************/
+#define CAN_F2R1_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F2R1_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F2R1_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F2R1_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F2R1_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F2R1_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F2R1_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F2R1_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F2R1_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F2R1_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F2R1_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F2R1_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F2R1_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F2R1_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F2R1_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F2R1_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F2R1_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F2R1_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F2R1_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F2R1_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F2R1_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F2R1_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F2R1_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F2R1_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F2R1_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F2R1_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F2R1_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F2R1_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F2R1_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F2R1_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F2R1_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F2R1_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F3R1 register *******************/
+#define CAN_F3R1_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F3R1_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F3R1_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F3R1_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F3R1_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F3R1_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F3R1_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F3R1_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F3R1_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F3R1_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F3R1_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F3R1_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F3R1_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F3R1_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F3R1_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F3R1_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F3R1_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F3R1_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F3R1_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F3R1_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F3R1_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F3R1_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F3R1_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F3R1_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F3R1_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F3R1_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F3R1_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F3R1_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F3R1_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F3R1_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F3R1_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F3R1_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F4R1 register *******************/
+#define CAN_F4R1_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F4R1_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F4R1_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F4R1_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F4R1_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F4R1_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F4R1_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F4R1_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F4R1_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F4R1_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F4R1_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F4R1_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F4R1_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F4R1_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F4R1_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F4R1_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F4R1_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F4R1_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F4R1_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F4R1_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F4R1_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F4R1_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F4R1_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F4R1_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F4R1_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F4R1_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F4R1_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F4R1_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F4R1_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F4R1_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F4R1_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F4R1_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F5R1 register *******************/
+#define CAN_F5R1_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F5R1_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F5R1_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F5R1_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F5R1_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F5R1_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F5R1_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F5R1_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F5R1_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F5R1_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F5R1_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F5R1_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F5R1_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F5R1_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F5R1_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F5R1_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F5R1_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F5R1_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F5R1_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F5R1_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F5R1_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F5R1_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F5R1_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F5R1_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F5R1_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F5R1_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F5R1_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F5R1_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F5R1_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F5R1_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F5R1_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F5R1_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F6R1 register *******************/
+#define CAN_F6R1_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F6R1_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F6R1_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F6R1_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F6R1_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F6R1_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F6R1_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F6R1_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F6R1_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F6R1_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F6R1_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F6R1_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F6R1_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F6R1_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F6R1_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F6R1_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F6R1_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F6R1_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F6R1_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F6R1_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F6R1_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F6R1_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F6R1_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F6R1_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F6R1_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F6R1_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F6R1_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F6R1_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F6R1_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F6R1_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F6R1_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F6R1_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F7R1 register *******************/
+#define CAN_F7R1_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F7R1_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F7R1_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F7R1_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F7R1_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F7R1_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F7R1_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F7R1_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F7R1_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F7R1_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F7R1_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F7R1_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F7R1_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F7R1_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F7R1_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F7R1_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F7R1_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F7R1_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F7R1_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F7R1_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F7R1_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F7R1_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F7R1_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F7R1_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F7R1_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F7R1_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F7R1_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F7R1_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F7R1_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F7R1_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F7R1_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F7R1_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F8R1 register *******************/
+#define CAN_F8R1_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F8R1_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F8R1_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F8R1_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F8R1_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F8R1_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F8R1_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F8R1_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F8R1_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F8R1_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F8R1_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F8R1_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F8R1_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F8R1_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F8R1_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F8R1_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F8R1_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F8R1_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F8R1_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F8R1_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F8R1_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F8R1_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F8R1_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F8R1_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F8R1_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F8R1_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F8R1_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F8R1_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F8R1_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F8R1_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F8R1_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F8R1_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F9R1 register *******************/
+#define CAN_F9R1_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F9R1_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F9R1_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F9R1_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F9R1_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F9R1_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F9R1_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F9R1_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F9R1_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F9R1_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F9R1_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F9R1_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F9R1_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F9R1_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F9R1_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F9R1_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F9R1_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F9R1_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F9R1_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F9R1_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F9R1_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F9R1_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F9R1_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F9R1_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F9R1_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F9R1_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F9R1_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F9R1_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F9R1_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F9R1_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F9R1_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F9R1_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F10R1 register ******************/
+#define CAN_F10R1_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F10R1_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F10R1_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F10R1_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F10R1_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F10R1_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F10R1_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F10R1_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F10R1_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F10R1_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F10R1_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F10R1_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F10R1_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F10R1_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F10R1_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F10R1_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F10R1_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F10R1_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F10R1_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F10R1_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F10R1_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F10R1_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F10R1_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F10R1_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F10R1_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F10R1_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F10R1_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F10R1_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F10R1_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F10R1_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F10R1_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F10R1_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F11R1 register ******************/
+#define CAN_F11R1_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F11R1_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F11R1_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F11R1_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F11R1_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F11R1_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F11R1_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F11R1_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F11R1_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F11R1_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F11R1_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F11R1_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F11R1_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F11R1_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F11R1_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F11R1_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F11R1_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F11R1_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F11R1_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F11R1_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F11R1_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F11R1_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F11R1_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F11R1_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F11R1_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F11R1_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F11R1_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F11R1_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F11R1_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F11R1_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F11R1_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F11R1_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F12R1 register ******************/
+#define CAN_F12R1_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F12R1_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F12R1_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F12R1_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F12R1_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F12R1_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F12R1_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F12R1_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F12R1_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F12R1_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F12R1_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F12R1_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F12R1_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F12R1_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F12R1_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F12R1_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F12R1_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F12R1_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F12R1_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F12R1_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F12R1_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F12R1_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F12R1_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F12R1_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F12R1_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F12R1_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F12R1_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F12R1_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F12R1_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F12R1_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F12R1_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F12R1_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F13R1 register ******************/
+#define CAN_F13R1_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F13R1_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F13R1_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F13R1_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F13R1_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F13R1_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F13R1_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F13R1_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F13R1_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F13R1_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F13R1_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F13R1_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F13R1_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F13R1_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F13R1_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F13R1_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F13R1_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F13R1_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F13R1_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F13R1_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F13R1_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F13R1_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F13R1_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F13R1_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F13R1_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F13R1_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F13R1_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F13R1_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F13R1_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F13R1_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F13R1_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F13R1_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F0R2 register *******************/
+#define CAN_F0R2_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F0R2_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F0R2_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F0R2_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F0R2_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F0R2_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F0R2_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F0R2_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F0R2_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F0R2_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F0R2_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F0R2_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F0R2_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F0R2_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F0R2_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F0R2_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F0R2_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F0R2_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F0R2_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F0R2_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F0R2_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F0R2_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F0R2_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F0R2_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F0R2_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F0R2_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F0R2_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F0R2_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F0R2_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F0R2_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F0R2_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F0R2_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F1R2 register *******************/
+#define CAN_F1R2_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F1R2_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F1R2_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F1R2_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F1R2_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F1R2_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F1R2_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F1R2_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F1R2_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F1R2_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F1R2_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F1R2_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F1R2_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F1R2_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F1R2_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F1R2_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F1R2_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F1R2_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F1R2_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F1R2_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F1R2_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F1R2_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F1R2_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F1R2_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F1R2_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F1R2_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F1R2_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F1R2_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F1R2_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F1R2_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F1R2_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F1R2_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F2R2 register *******************/
+#define CAN_F2R2_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F2R2_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F2R2_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F2R2_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F2R2_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F2R2_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F2R2_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F2R2_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F2R2_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F2R2_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F2R2_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F2R2_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F2R2_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F2R2_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F2R2_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F2R2_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F2R2_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F2R2_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F2R2_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F2R2_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F2R2_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F2R2_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F2R2_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F2R2_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F2R2_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F2R2_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F2R2_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F2R2_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F2R2_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F2R2_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F2R2_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F2R2_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F3R2 register *******************/
+#define CAN_F3R2_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F3R2_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F3R2_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F3R2_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F3R2_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F3R2_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F3R2_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F3R2_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F3R2_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F3R2_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F3R2_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F3R2_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F3R2_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F3R2_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F3R2_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F3R2_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F3R2_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F3R2_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F3R2_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F3R2_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F3R2_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F3R2_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F3R2_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F3R2_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F3R2_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F3R2_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F3R2_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F3R2_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F3R2_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F3R2_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F3R2_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F3R2_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F4R2 register *******************/
+#define CAN_F4R2_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F4R2_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F4R2_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F4R2_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F4R2_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F4R2_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F4R2_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F4R2_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F4R2_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F4R2_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F4R2_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F4R2_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F4R2_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F4R2_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F4R2_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F4R2_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F4R2_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F4R2_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F4R2_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F4R2_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F4R2_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F4R2_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F4R2_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F4R2_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F4R2_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F4R2_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F4R2_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F4R2_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F4R2_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F4R2_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F4R2_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F4R2_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F5R2 register *******************/
+#define CAN_F5R2_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F5R2_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F5R2_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F5R2_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F5R2_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F5R2_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F5R2_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F5R2_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F5R2_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F5R2_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F5R2_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F5R2_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F5R2_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F5R2_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F5R2_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F5R2_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F5R2_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F5R2_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F5R2_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F5R2_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F5R2_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F5R2_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F5R2_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F5R2_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F5R2_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F5R2_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F5R2_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F5R2_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F5R2_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F5R2_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F5R2_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F5R2_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F6R2 register *******************/
+#define CAN_F6R2_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F6R2_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F6R2_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F6R2_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F6R2_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F6R2_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F6R2_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F6R2_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F6R2_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F6R2_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F6R2_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F6R2_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F6R2_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F6R2_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F6R2_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F6R2_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F6R2_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F6R2_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F6R2_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F6R2_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F6R2_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F6R2_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F6R2_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F6R2_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F6R2_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F6R2_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F6R2_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F6R2_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F6R2_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F6R2_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F6R2_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F6R2_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F7R2 register *******************/
+#define CAN_F7R2_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F7R2_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F7R2_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F7R2_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F7R2_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F7R2_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F7R2_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F7R2_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F7R2_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F7R2_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F7R2_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F7R2_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F7R2_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F7R2_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F7R2_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F7R2_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F7R2_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F7R2_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F7R2_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F7R2_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F7R2_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F7R2_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F7R2_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F7R2_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F7R2_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F7R2_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F7R2_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F7R2_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F7R2_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F7R2_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F7R2_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F7R2_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F8R2 register *******************/
+#define CAN_F8R2_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F8R2_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F8R2_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F8R2_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F8R2_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F8R2_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F8R2_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F8R2_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F8R2_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F8R2_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F8R2_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F8R2_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F8R2_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F8R2_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F8R2_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F8R2_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F8R2_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F8R2_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F8R2_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F8R2_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F8R2_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F8R2_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F8R2_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F8R2_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F8R2_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F8R2_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F8R2_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F8R2_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F8R2_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F8R2_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F8R2_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F8R2_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F9R2 register *******************/
+#define CAN_F9R2_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F9R2_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F9R2_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F9R2_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F9R2_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F9R2_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F9R2_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F9R2_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F9R2_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F9R2_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F9R2_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F9R2_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F9R2_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F9R2_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F9R2_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F9R2_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F9R2_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F9R2_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F9R2_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F9R2_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F9R2_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F9R2_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F9R2_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F9R2_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F9R2_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F9R2_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F9R2_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F9R2_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F9R2_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F9R2_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F9R2_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F9R2_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F10R2 register ******************/
+#define CAN_F10R2_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F10R2_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F10R2_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F10R2_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F10R2_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F10R2_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F10R2_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F10R2_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F10R2_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F10R2_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F10R2_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F10R2_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F10R2_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F10R2_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F10R2_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F10R2_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F10R2_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F10R2_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F10R2_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F10R2_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F10R2_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F10R2_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F10R2_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F10R2_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F10R2_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F10R2_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F10R2_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F10R2_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F10R2_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F10R2_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F10R2_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F10R2_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F11R2 register ******************/
+#define CAN_F11R2_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F11R2_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F11R2_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F11R2_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F11R2_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F11R2_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F11R2_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F11R2_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F11R2_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F11R2_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F11R2_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F11R2_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F11R2_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F11R2_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F11R2_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F11R2_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F11R2_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F11R2_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F11R2_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F11R2_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F11R2_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F11R2_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F11R2_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F11R2_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F11R2_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F11R2_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F11R2_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F11R2_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F11R2_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F11R2_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F11R2_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F11R2_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F12R2 register ******************/
+#define CAN_F12R2_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F12R2_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F12R2_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F12R2_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F12R2_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F12R2_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F12R2_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F12R2_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F12R2_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F12R2_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F12R2_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F12R2_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F12R2_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F12R2_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F12R2_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F12R2_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F12R2_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F12R2_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F12R2_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F12R2_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F12R2_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F12R2_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F12R2_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F12R2_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F12R2_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F12R2_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F12R2_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F12R2_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F12R2_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F12R2_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F12R2_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F12R2_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F13R2 register ******************/
+#define CAN_F13R2_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F13R2_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F13R2_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F13R2_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F13R2_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F13R2_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F13R2_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F13R2_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F13R2_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F13R2_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F13R2_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F13R2_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F13R2_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F13R2_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F13R2_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F13R2_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F13R2_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F13R2_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F13R2_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F13R2_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F13R2_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F13R2_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F13R2_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F13R2_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F13R2_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F13R2_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F13R2_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F13R2_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F13R2_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F13R2_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F13R2_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F13R2_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************************************************************************/
+/* */
+/* CRC calculation unit */
+/* */
+/******************************************************************************/
+/******************* Bit definition for CRC_DR register *********************/
+#define CRC_DR_DR 0xFFFFFFFFU /*!< Data register bits */
+
+
+/******************* Bit definition for CRC_IDR register ********************/
+#define CRC_IDR_IDR 0xFFU /*!< General-purpose 8-bit data register bits */
+
+
+/******************** Bit definition for CRC_CR register ********************/
+#define CRC_CR_RESET 0x01U /*!< RESET bit */
+
+/******************************************************************************/
+/* */
+/* Debug MCU */
+/* */
+/******************************************************************************/
+
+/******************************************************************************/
+/* */
+/* Digital Filter for Sigma Delta Modulators */
+/* */
+/******************************************************************************/
+
+/**************** DFSDM channel configuration registers ********************/
+
+/*************** Bit definition for DFSDM_CHCFGR1 register ******************/
+#define DFSDM_CHCFGR1_DFSDMEN 0x80000000U /*!< Global enable for DFSDM interface */
+#define DFSDM_CHCFGR1_CKOUTSRC 0x40000000U /*!< Output serial clock source selection */
+#define DFSDM_CHCFGR1_CKOUTDIV 0x00FF0000U /*!< CKOUTDIV[7:0] output serial clock divider */
+#define DFSDM_CHCFGR1_DATPACK 0x0000C000U /*!< DATPACK[1:0] Data packing mode */
+#define DFSDM_CHCFGR1_DATPACK_1 0x00008000U /*!< Data packing mode, Bit 1 */
+#define DFSDM_CHCFGR1_DATPACK_0 0x00004000U /*!< Data packing mode, Bit 0 */
+#define DFSDM_CHCFGR1_DATMPX 0x00003000U /*!< DATMPX[1:0] Input data multiplexer for channel y */
+#define DFSDM_CHCFGR1_DATMPX_1 0x00002000U /*!< Input data multiplexer for channel y, Bit 1 */
+#define DFSDM_CHCFGR1_DATMPX_0 0x00001000U /*!< Input data multiplexer for channel y, Bit 0 */
+#define DFSDM_CHCFGR1_CHINSEL 0x00000100U /*!< Serial inputs selection for channel y */
+#define DFSDM_CHCFGR1_CHEN 0x00000080U /*!< Channel y enable */
+#define DFSDM_CHCFGR1_CKABEN 0x00000040U /*!< Clock absence detector enable on channel y */
+#define DFSDM_CHCFGR1_SCDEN 0x00000020U /*!< Short circuit detector enable on channel y */
+#define DFSDM_CHCFGR1_SPICKSEL 0x0000000CU /*!< SPICKSEL[1:0] SPI clock select for channel y */
+#define DFSDM_CHCFGR1_SPICKSEL_1 0x00000008U /*!< SPI clock select for channel y, Bit 1 */
+#define DFSDM_CHCFGR1_SPICKSEL_0 0x00000004U /*!< SPI clock select for channel y, Bit 0 */
+#define DFSDM_CHCFGR1_SITP 0x00000003U /*!< SITP[1:0] Serial interface type for channel y */
+#define DFSDM_CHCFGR1_SITP_1 0x00000002U /*!< Serial interface type for channel y, Bit 1 */
+#define DFSDM_CHCFGR1_SITP_0 0x00000001U /*!< Serial interface type for channel y, Bit 0 */
+
+/*************** Bit definition for DFSDM_CHCFGR2 register ******************/
+#define DFSDM_CHCFGR2_OFFSET 0xFFFFFF00U /*!< OFFSET[23:0] 24-bit calibration offset for channel y */
+#define DFSDM_CHCFGR2_DTRBS 0x000000F8U /*!< DTRBS[4:0] Data right bit-shift for channel y */
+
+/**************** Bit definition for DFSDM_CHAWSCDR register *****************/
+#define DFSDM_CHAWSCDR_AWFORD 0x00C00000U /*!< AWFORD[1:0] Analog watchdog Sinc filter order on channel y */
+#define DFSDM_CHAWSCDR_AWFORD_1 0x00800000U /*!< Analog watchdog Sinc filter order on channel y, Bit 1 */
+#define DFSDM_CHAWSCDR_AWFORD_0 0x00400000U /*!< Analog watchdog Sinc filter order on channel y, Bit 0 */
+#define DFSDM_CHAWSCDR_AWFOSR 0x001F0000U /*!< AWFOSR[4:0] Analog watchdog filter oversampling ratio on channel y */
+#define DFSDM_CHAWSCDR_BKSCD 0x0000F000U /*!< BKSCD[3:0] Break signal assignment for short circuit detector on channel y */
+#define DFSDM_CHAWSCDR_SCDT 0x000000FFU /*!< SCDT[7:0] Short circuit detector threshold for channel y */
+
+/**************** Bit definition for DFSDM_CHWDATR register *******************/
+#define DFSDM_CHWDATR_WDATA 0x0000FFFFU /*!< WDATA[15:0] Input channel y watchdog data */
+
+/**************** Bit definition for DFSDM_CHDATINR register *****************/
+#define DFSDM_CHDATINR_INDAT0 0x0000FFFFU /*!< INDAT0[31:16] Input data for channel y or channel (y+1) */
+#define DFSDM_CHDATINR_INDAT1 0xFFFF0000U /*!< INDAT0[15:0] Input data for channel y */
+
+/************************ DFSDM module registers ****************************/
+
+/***************** Bit definition for DFSDM_FLTCR1 register *******************/
+#define DFSDM_FLTCR1_AWFSEL 0x40000000U /*!< Analog watchdog fast mode select */
+#define DFSDM_FLTCR1_FAST 0x20000000U /*!< Fast conversion mode selection */
+#define DFSDM_FLTCR1_RCH 0x07000000U /*!< RCH[2:0] Regular channel selection */
+#define DFSDM_FLTCR1_RDMAEN 0x00200000U /*!< DMA channel enabled to read data for the regular conversion */
+#define DFSDM_FLTCR1_RSYNC 0x00080000U /*!< Launch regular conversion synchronously with DFSDMx */
+#define DFSDM_FLTCR1_RCONT 0x00040000U /*!< Continuous mode selection for regular conversions */
+#define DFSDM_FLTCR1_RSWSTART 0x00020000U /*!< Software start of a conversion on the regular channel */
+#define DFSDM_FLTCR1_JEXTEN 0x00006000U /*!< JEXTEN[1:0] Trigger enable and trigger edge selection for injected conversions */
+#define DFSDM_FLTCR1_JEXTEN_1 0x00004000U /*!< Trigger enable and trigger edge selection for injected conversions, Bit 1 */
+#define DFSDM_FLTCR1_JEXTEN_0 0x00002000U /*!< Trigger enable and trigger edge selection for injected conversions, Bit 0 */
+#define DFSDM_FLTCR1_JEXTSEL 0x00000700U /*!< JEXTSEL[2:0]Trigger signal selection for launching injected conversions */
+#define DFSDM_FLTCR1_JEXTSEL_2 0x00000400U /*!< Trigger signal selection for launching injected conversions, Bit 2 */
+#define DFSDM_FLTCR1_JEXTSEL_1 0x00000200U /*!< Trigger signal selection for launching injected conversions, Bit 1 */
+#define DFSDM_FLTCR1_JEXTSEL_0 0x00000100U /*!< Trigger signal selection for launching injected conversions, Bit 0 */
+#define DFSDM_FLTCR1_JDMAEN 0x00000020U /*!< DMA channel enabled to read data for the injected channel group */
+#define DFSDM_FLTCR1_JSCAN 0x00000010U /*!< Scanning conversion in continuous mode selection for injected conversions */
+#define DFSDM_FLTCR1_JSYNC 0x00000008U /*!< Launch an injected conversion synchronously with DFSDMx JSWSTART trigger */
+#define DFSDM_FLTCR1_JSWSTART 0x00000002U /*!< Start the conversion of the injected group of channels */
+#define DFSDM_FLTCR1_DFEN 0x00000001U /*!< DFSDM enable */
+
+/***************** Bit definition for DFSDM_FLTCR2 register *******************/
+#define DFSDM_FLTCR2_AWDCH 0x000F0000U /*!< AWDCH[7:0] Analog watchdog channel selection */
+#define DFSDM_FLTCR2_EXCH 0x00000F00U /*!< EXCH[7:0] Extreme detector channel selection */
+#define DFSDM_FLTCR2_CKABIE 0x00000040U /*!< Clock absence interrupt enable */
+#define DFSDM_FLTCR2_SCDIE 0x00000020U /*!< Short circuit detector interrupt enable */
+#define DFSDM_FLTCR2_AWDIE 0x00000010U /*!< Analog watchdog interrupt enable */
+#define DFSDM_FLTCR2_ROVRIE 0x00000008U /*!< Regular data overrun interrupt enable */
+#define DFSDM_FLTCR2_JOVRIE 0x00000004U /*!< Injected data overrun interrupt enable */
+#define DFSDM_FLTCR2_REOCIE 0x00000002U /*!< Regular end of conversion interrupt enable */
+#define DFSDM_FLTCR2_JEOCIE 0x00000001U /*!< Injected end of conversion interrupt enable */
+
+/***************** Bit definition for DFSDM_FLTISR register *******************/
+#define DFSDM_FLTISR_SCDF 0x0F000000U /*!< SCDF[7:0] Short circuit detector flag */
+#define DFSDM_FLTISR_CKABF 0x000F0000U /*!< CKABF[7:0] Clock absence flag */
+#define DFSDM_FLTISR_RCIP 0x00004000U /*!< Regular conversion in progress status */
+#define DFSDM_FLTISR_JCIP 0x00002000U /*!< Injected conversion in progress status */
+#define DFSDM_FLTISR_AWDF 0x00000010U /*!< Analog watchdog */
+#define DFSDM_FLTISR_ROVRF 0x00000008U /*!< Regular conversion overrun flag */
+#define DFSDM_FLTISR_JOVRF 0x00000004U /*!< Injected conversion overrun flag */
+#define DFSDM_FLTISR_REOCF 0x00000002U /*!< End of regular conversion flag */
+#define DFSDM_FLTISR_JEOCF 0x00000001U /*!< End of injected conversion flag */
+
+/***************** Bit definition for DFSDM_FLTICR register *******************/
+#define DFSDM_FLTICR_CLRSCSDF 0x0F000000U /*!< CLRSCSDF[7:0] Clear the short circuit detector flag */
+#define DFSDM_FLTICR_CLRCKABF 0x000F0000U /*!< CLRCKABF[7:0] Clear the clock absence flag */
+#define DFSDM_FLTICR_CLRROVRF 0x00000008U /*!< Clear the regular conversion overrun flag */
+#define DFSDM_FLTICR_CLRJOVRF 0x00000004U /*!< Clear the injected conversion overrun flag */
+
+/**************** Bit definition for DFSDM_FLTJCHGR register ******************/
+#define DFSDM_FLTJCHGR_JCHG 0x0000000FU /*!< JCHG[7:0] Injected channel group selection */
+
+/***************** Bit definition for DFSDM_FLTFCR register *******************/
+#define DFSDM_FLTFCR_FORD 0xE0000000U /*!< FORD[2:0] Sinc filter order */
+#define DFSDM_FLTFCR_FORD_2 0x80000000U /*!< Sinc filter order, Bit 2 */
+#define DFSDM_FLTFCR_FORD_1 0x40000000U /*!< Sinc filter order, Bit 1 */
+#define DFSDM_FLTFCR_FORD_0 0x20000000U /*!< Sinc filter order, Bit 0 */
+#define DFSDM_FLTFCR_FOSR 0x03FF0000U /*!< FOSR[9:0] Sinc filter oversampling ratio (decimation rate) */
+#define DFSDM_FLTFCR_IOSR 0x000000FFU /*!< IOSR[7:0] Integrator oversampling ratio (averaging length) */
+
+/*************** Bit definition for DFSDM_FLTJDATAR register *****************/
+#define DFSDM_FLTJDATAR_JDATA 0xFFFFFF00U /*!< JDATA[23:0] Injected group conversion data */
+#define DFSDM_FLTJDATAR_JDATACH 0x00000007U /*!< JDATACH[2:0] Injected channel most recently converted */
+
+/*************** Bit definition for DFSDM_FLTRDATAR register *****************/
+#define DFSDM_FLTRDATAR_RDATA 0xFFFFFF00U /*!< RDATA[23:0] Regular channel conversion data */
+#define DFSDM_FLTRDATAR_RPEND 0x00000010U /*!< RPEND Regular channel pending data */
+#define DFSDM_FLTRDATAR_RDATACH 0x00000007U /*!< RDATACH[2:0] Regular channel most recently converted */
+
+/*************** Bit definition for DFSDM_FLTAWHTR register ******************/
+#define DFSDM_FLTAWHTR_AWHT 0xFFFFFF00U /*!< AWHT[23:0] Analog watchdog high threshold */
+#define DFSDM_FLTAWHTR_BKAWH 0x0000000FU /*!< BKAWH[3:0] Break signal assignment to analog watchdog high threshold event */
+
+/*************** Bit definition for DFSDM_FLTAWLTR register ******************/
+#define DFSDM_FLTAWLTR_AWLT 0xFFFFFF00U /*!< AWLT[23:0] Analog watchdog low threshold */
+#define DFSDM_FLTAWLTR_BKAWL 0x0000000FU /*!< BKAWL[3:0] Break signal assignment to analog watchdog low threshold event */
+
+/*************** Bit definition for DFSDM_FLTAWSR register *******************/
+#define DFSDM_FLTAWSR_AWHTF 0x00000F00U /*!< AWHTF[15:8] Analog watchdog high threshold error on given channels */
+#define DFSDM_FLTAWSR_AWLTF 0x0000000FU /*!< AWLTF[7:0] Analog watchdog low threshold error on given channels */
+
+/*************** Bit definition for DFSDM_FLTAWCFR register ******************/
+#define DFSDM_FLTAWCFR_CLRAWHTF 0x00000F00U /*!< CLRAWHTF[15:8] Clear the Analog watchdog high threshold flag */
+#define DFSDM_FLTAWCFR_CLRAWLTF 0x0000000FU /*!< CLRAWLTF[7:0] Clear the Analog watchdog low threshold flag */
+
+/*************** Bit definition for DFSDM_FLTEXMAX register ******************/
+#define DFSDM_FLTEXMAX_EXMAX 0xFFFFFF00U /*!< EXMAX[23:0] Extreme detector maximum value */
+#define DFSDM_FLTEXMAX_EXMAXCH 0x00000007U /*!< EXMAXCH[2:0] Extreme detector maximum data channel */
+
+/*************** Bit definition for DFSDM_FLTEXMIN register ******************/
+#define DFSDM_FLTEXMIN_EXMIN 0xFFFFFF00U /*!< EXMIN[23:0] Extreme detector minimum value */
+#define DFSDM_FLTEXMIN_EXMINCH 0x00000007U /*!< EXMINCH[2:0] Extreme detector minimum data channel */
+
+/*************** Bit definition for DFSDM_FLTCNVTIMR register ****************/
+#define DFSDM_FLTCNVTIMR_CNVCNT 0xFFFFFFF0U /*!< CNVCNT[27:0]: 28-bit timer counting conversion time */
+
+/******************************************************************************/
+/* */
+/* DMA Controller */
+/* */
+/******************************************************************************/
+/******************** Bits definition for DMA_SxCR register *****************/
+#define DMA_SxCR_CHSEL 0x0E000000U
+#define DMA_SxCR_CHSEL_0 0x02000000U
+#define DMA_SxCR_CHSEL_1 0x04000000U
+#define DMA_SxCR_CHSEL_2 0x08000000U
+#define DMA_SxCR_MBURST 0x01800000U
+#define DMA_SxCR_MBURST_0 0x00800000U
+#define DMA_SxCR_MBURST_1 0x01000000U
+#define DMA_SxCR_PBURST 0x00600000U
+#define DMA_SxCR_PBURST_0 0x00200000U
+#define DMA_SxCR_PBURST_1 0x00400000U
+#define DMA_SxCR_CT 0x00080000U
+#define DMA_SxCR_DBM 0x00040000U
+#define DMA_SxCR_PL 0x00030000U
+#define DMA_SxCR_PL_0 0x00010000U
+#define DMA_SxCR_PL_1 0x00020000U
+#define DMA_SxCR_PINCOS 0x00008000U
+#define DMA_SxCR_MSIZE 0x00006000U
+#define DMA_SxCR_MSIZE_0 0x00002000U
+#define DMA_SxCR_MSIZE_1 0x00004000U
+#define DMA_SxCR_PSIZE 0x00001800U
+#define DMA_SxCR_PSIZE_0 0x00000800U
+#define DMA_SxCR_PSIZE_1 0x00001000U
+#define DMA_SxCR_MINC 0x00000400U
+#define DMA_SxCR_PINC 0x00000200U
+#define DMA_SxCR_CIRC 0x00000100U
+#define DMA_SxCR_DIR 0x000000C0U
+#define DMA_SxCR_DIR_0 0x00000040U
+#define DMA_SxCR_DIR_1 0x00000080U
+#define DMA_SxCR_PFCTRL 0x00000020U
+#define DMA_SxCR_TCIE 0x00000010U
+#define DMA_SxCR_HTIE 0x00000008U
+#define DMA_SxCR_TEIE 0x00000004U
+#define DMA_SxCR_DMEIE 0x00000002U
+#define DMA_SxCR_EN 0x00000001U
+
+/* Legacy defines */
+#define DMA_SxCR_ACK 0x00100000U
+
+/******************** Bits definition for DMA_SxCNDTR register **************/
+#define DMA_SxNDT 0x0000FFFFU
+#define DMA_SxNDT_0 0x00000001U
+#define DMA_SxNDT_1 0x00000002U
+#define DMA_SxNDT_2 0x00000004U
+#define DMA_SxNDT_3 0x00000008U
+#define DMA_SxNDT_4 0x00000010U
+#define DMA_SxNDT_5 0x00000020U
+#define DMA_SxNDT_6 0x00000040U
+#define DMA_SxNDT_7 0x00000080U
+#define DMA_SxNDT_8 0x00000100U
+#define DMA_SxNDT_9 0x00000200U
+#define DMA_SxNDT_10 0x00000400U
+#define DMA_SxNDT_11 0x00000800U
+#define DMA_SxNDT_12 0x00001000U
+#define DMA_SxNDT_13 0x00002000U
+#define DMA_SxNDT_14 0x00004000U
+#define DMA_SxNDT_15 0x00008000U
+
+/******************** Bits definition for DMA_SxFCR register ****************/
+#define DMA_SxFCR_FEIE 0x00000080U
+#define DMA_SxFCR_FS 0x00000038U
+#define DMA_SxFCR_FS_0 0x00000008U
+#define DMA_SxFCR_FS_1 0x00000010U
+#define DMA_SxFCR_FS_2 0x00000020U
+#define DMA_SxFCR_DMDIS 0x00000004U
+#define DMA_SxFCR_FTH 0x00000003U
+#define DMA_SxFCR_FTH_0 0x00000001U
+#define DMA_SxFCR_FTH_1 0x00000002U
+
+/******************** Bits definition for DMA_LISR register *****************/
+#define DMA_LISR_TCIF3 0x08000000U
+#define DMA_LISR_HTIF3 0x04000000U
+#define DMA_LISR_TEIF3 0x02000000U
+#define DMA_LISR_DMEIF3 0x01000000U
+#define DMA_LISR_FEIF3 0x00400000U
+#define DMA_LISR_TCIF2 0x00200000U
+#define DMA_LISR_HTIF2 0x00100000U
+#define DMA_LISR_TEIF2 0x00080000U
+#define DMA_LISR_DMEIF2 0x00040000U
+#define DMA_LISR_FEIF2 0x00010000U
+#define DMA_LISR_TCIF1 0x00000800U
+#define DMA_LISR_HTIF1 0x00000400U
+#define DMA_LISR_TEIF1 0x00000200U
+#define DMA_LISR_DMEIF1 0x00000100U
+#define DMA_LISR_FEIF1 0x00000040U
+#define DMA_LISR_TCIF0 0x00000020U
+#define DMA_LISR_HTIF0 0x00000010U
+#define DMA_LISR_TEIF0 0x00000008U
+#define DMA_LISR_DMEIF0 0x00000004U
+#define DMA_LISR_FEIF0 0x00000001U
+
+/******************** Bits definition for DMA_HISR register *****************/
+#define DMA_HISR_TCIF7 0x08000000U
+#define DMA_HISR_HTIF7 0x04000000U
+#define DMA_HISR_TEIF7 0x02000000U
+#define DMA_HISR_DMEIF7 0x01000000U
+#define DMA_HISR_FEIF7 0x00400000U
+#define DMA_HISR_TCIF6 0x00200000U
+#define DMA_HISR_HTIF6 0x00100000U
+#define DMA_HISR_TEIF6 0x00080000U
+#define DMA_HISR_DMEIF6 0x00040000U
+#define DMA_HISR_FEIF6 0x00010000U
+#define DMA_HISR_TCIF5 0x00000800U
+#define DMA_HISR_HTIF5 0x00000400U
+#define DMA_HISR_TEIF5 0x00000200U
+#define DMA_HISR_DMEIF5 0x00000100U
+#define DMA_HISR_FEIF5 0x00000040U
+#define DMA_HISR_TCIF4 0x00000020U
+#define DMA_HISR_HTIF4 0x00000010U
+#define DMA_HISR_TEIF4 0x00000008U
+#define DMA_HISR_DMEIF4 0x00000004U
+#define DMA_HISR_FEIF4 0x00000001U
+
+/******************** Bits definition for DMA_LIFCR register ****************/
+#define DMA_LIFCR_CTCIF3 0x08000000U
+#define DMA_LIFCR_CHTIF3 0x04000000U
+#define DMA_LIFCR_CTEIF3 0x02000000U
+#define DMA_LIFCR_CDMEIF3 0x01000000U
+#define DMA_LIFCR_CFEIF3 0x00400000U
+#define DMA_LIFCR_CTCIF2 0x00200000U
+#define DMA_LIFCR_CHTIF2 0x00100000U
+#define DMA_LIFCR_CTEIF2 0x00080000U
+#define DMA_LIFCR_CDMEIF2 0x00040000U
+#define DMA_LIFCR_CFEIF2 0x00010000U
+#define DMA_LIFCR_CTCIF1 0x00000800U
+#define DMA_LIFCR_CHTIF1 0x00000400U
+#define DMA_LIFCR_CTEIF1 0x00000200U
+#define DMA_LIFCR_CDMEIF1 0x00000100U
+#define DMA_LIFCR_CFEIF1 0x00000040U
+#define DMA_LIFCR_CTCIF0 0x00000020U
+#define DMA_LIFCR_CHTIF0 0x00000010U
+#define DMA_LIFCR_CTEIF0 0x00000008U
+#define DMA_LIFCR_CDMEIF0 0x00000004U
+#define DMA_LIFCR_CFEIF0 0x00000001U
+
+/******************** Bits definition for DMA_HIFCR register ****************/
+#define DMA_HIFCR_CTCIF7 0x08000000U
+#define DMA_HIFCR_CHTIF7 0x04000000U
+#define DMA_HIFCR_CTEIF7 0x02000000U
+#define DMA_HIFCR_CDMEIF7 0x01000000U
+#define DMA_HIFCR_CFEIF7 0x00400000U
+#define DMA_HIFCR_CTCIF6 0x00200000U
+#define DMA_HIFCR_CHTIF6 0x00100000U
+#define DMA_HIFCR_CTEIF6 0x00080000U
+#define DMA_HIFCR_CDMEIF6 0x00040000U
+#define DMA_HIFCR_CFEIF6 0x00010000U
+#define DMA_HIFCR_CTCIF5 0x00000800U
+#define DMA_HIFCR_CHTIF5 0x00000400U
+#define DMA_HIFCR_CTEIF5 0x00000200U
+#define DMA_HIFCR_CDMEIF5 0x00000100U
+#define DMA_HIFCR_CFEIF5 0x00000040U
+#define DMA_HIFCR_CTCIF4 0x00000020U
+#define DMA_HIFCR_CHTIF4 0x00000010U
+#define DMA_HIFCR_CTEIF4 0x00000008U
+#define DMA_HIFCR_CDMEIF4 0x00000004U
+#define DMA_HIFCR_CFEIF4 0x00000001U
+
+
+/******************************************************************************/
+/* */
+/* External Interrupt/Event Controller */
+/* */
+/******************************************************************************/
+/******************* Bit definition for EXTI_IMR register *******************/
+#define EXTI_IMR_MR0 0x00000001U /*!< Interrupt Mask on line 0 */
+#define EXTI_IMR_MR1 0x00000002U /*!< Interrupt Mask on line 1 */
+#define EXTI_IMR_MR2 0x00000004U /*!< Interrupt Mask on line 2 */
+#define EXTI_IMR_MR3 0x00000008U /*!< Interrupt Mask on line 3 */
+#define EXTI_IMR_MR4 0x00000010U /*!< Interrupt Mask on line 4 */
+#define EXTI_IMR_MR5 0x00000020U /*!< Interrupt Mask on line 5 */
+#define EXTI_IMR_MR6 0x00000040U /*!< Interrupt Mask on line 6 */
+#define EXTI_IMR_MR7 0x00000080U /*!< Interrupt Mask on line 7 */
+#define EXTI_IMR_MR8 0x00000100U /*!< Interrupt Mask on line 8 */
+#define EXTI_IMR_MR9 0x00000200U /*!< Interrupt Mask on line 9 */
+#define EXTI_IMR_MR10 0x00000400U /*!< Interrupt Mask on line 10 */
+#define EXTI_IMR_MR11 0x00000800U /*!< Interrupt Mask on line 11 */
+#define EXTI_IMR_MR12 0x00001000U /*!< Interrupt Mask on line 12 */
+#define EXTI_IMR_MR13 0x00002000U /*!< Interrupt Mask on line 13 */
+#define EXTI_IMR_MR14 0x00004000U /*!< Interrupt Mask on line 14 */
+#define EXTI_IMR_MR15 0x00008000U /*!< Interrupt Mask on line 15 */
+#define EXTI_IMR_MR16 0x00010000U /*!< Interrupt Mask on line 16 */
+#define EXTI_IMR_MR17 0x00020000U /*!< Interrupt Mask on line 17 */
+#define EXTI_IMR_MR18 0x00040000U /*!< Interrupt Mask on line 18 */
+#define EXTI_IMR_MR19 0x00080000U /*!< Interrupt Mask on line 19 */
+#define EXTI_IMR_MR20 0x00100000U /*!< Interrupt Mask on line 20 */
+#define EXTI_IMR_MR21 0x00200000U /*!< Interrupt Mask on line 21 */
+#define EXTI_IMR_MR22 0x00400000U /*!< Interrupt Mask on line 22 */
+
+/******************* Bit definition for EXTI_EMR register *******************/
+#define EXTI_EMR_MR0 0x00000001U /*!< Event Mask on line 0 */
+#define EXTI_EMR_MR1 0x00000002U /*!< Event Mask on line 1 */
+#define EXTI_EMR_MR2 0x00000004U /*!< Event Mask on line 2 */
+#define EXTI_EMR_MR3 0x00000008U /*!< Event Mask on line 3 */
+#define EXTI_EMR_MR4 0x00000010U /*!< Event Mask on line 4 */
+#define EXTI_EMR_MR5 0x00000020U /*!< Event Mask on line 5 */
+#define EXTI_EMR_MR6 0x00000040U /*!< Event Mask on line 6 */
+#define EXTI_EMR_MR7 0x00000080U /*!< Event Mask on line 7 */
+#define EXTI_EMR_MR8 0x00000100U /*!< Event Mask on line 8 */
+#define EXTI_EMR_MR9 0x00000200U /*!< Event Mask on line 9 */
+#define EXTI_EMR_MR10 0x00000400U /*!< Event Mask on line 10 */
+#define EXTI_EMR_MR11 0x00000800U /*!< Event Mask on line 11 */
+#define EXTI_EMR_MR12 0x00001000U /*!< Event Mask on line 12 */
+#define EXTI_EMR_MR13 0x00002000U /*!< Event Mask on line 13 */
+#define EXTI_EMR_MR14 0x00004000U /*!< Event Mask on line 14 */
+#define EXTI_EMR_MR15 0x00008000U /*!< Event Mask on line 15 */
+#define EXTI_EMR_MR16 0x00010000U /*!< Event Mask on line 16 */
+#define EXTI_EMR_MR17 0x00020000U /*!< Event Mask on line 17 */
+#define EXTI_EMR_MR18 0x00040000U /*!< Event Mask on line 18 */
+#define EXTI_EMR_MR19 0x00080000U /*!< Event Mask on line 19 */
+#define EXTI_EMR_MR20 0x00100000U /*!< Event Mask on line 20 */
+#define EXTI_EMR_MR21 0x00200000U /*!< Event Mask on line 21 */
+#define EXTI_EMR_MR22 0x00400000U /*!< Event Mask on line 22 */
+
+/****************** Bit definition for EXTI_RTSR register *******************/
+#define EXTI_RTSR_TR0 0x00000001U /*!< Rising trigger event configuration bit of line 0 */
+#define EXTI_RTSR_TR1 0x00000002U /*!< Rising trigger event configuration bit of line 1 */
+#define EXTI_RTSR_TR2 0x00000004U /*!< Rising trigger event configuration bit of line 2 */
+#define EXTI_RTSR_TR3 0x00000008U /*!< Rising trigger event configuration bit of line 3 */
+#define EXTI_RTSR_TR4 0x00000010U /*!< Rising trigger event configuration bit of line 4 */
+#define EXTI_RTSR_TR5 0x00000020U /*!< Rising trigger event configuration bit of line 5 */
+#define EXTI_RTSR_TR6 0x00000040U /*!< Rising trigger event configuration bit of line 6 */
+#define EXTI_RTSR_TR7 0x00000080U /*!< Rising trigger event configuration bit of line 7 */
+#define EXTI_RTSR_TR8 0x00000100U /*!< Rising trigger event configuration bit of line 8 */
+#define EXTI_RTSR_TR9 0x00000200U /*!< Rising trigger event configuration bit of line 9 */
+#define EXTI_RTSR_TR10 0x00000400U /*!< Rising trigger event configuration bit of line 10 */
+#define EXTI_RTSR_TR11 0x00000800U /*!< Rising trigger event configuration bit of line 11 */
+#define EXTI_RTSR_TR12 0x00001000U /*!< Rising trigger event configuration bit of line 12 */
+#define EXTI_RTSR_TR13 0x00002000U /*!< Rising trigger event configuration bit of line 13 */
+#define EXTI_RTSR_TR14 0x00004000U /*!< Rising trigger event configuration bit of line 14 */
+#define EXTI_RTSR_TR15 0x00008000U /*!< Rising trigger event configuration bit of line 15 */
+#define EXTI_RTSR_TR16 0x00010000U /*!< Rising trigger event configuration bit of line 16 */
+#define EXTI_RTSR_TR17 0x00020000U /*!< Rising trigger event configuration bit of line 17 */
+#define EXTI_RTSR_TR18 0x00040000U /*!< Rising trigger event configuration bit of line 18 */
+#define EXTI_RTSR_TR19 0x00080000U /*!< Rising trigger event configuration bit of line 19 */
+#define EXTI_RTSR_TR20 0x00100000U /*!< Rising trigger event configuration bit of line 20 */
+#define EXTI_RTSR_TR21 0x00200000U /*!< Rising trigger event configuration bit of line 21 */
+#define EXTI_RTSR_TR22 0x00400000U /*!< Rising trigger event configuration bit of line 22 */
+
+/****************** Bit definition for EXTI_FTSR register *******************/
+#define EXTI_FTSR_TR0 0x00000001U /*!< Falling trigger event configuration bit of line 0 */
+#define EXTI_FTSR_TR1 0x00000002U /*!< Falling trigger event configuration bit of line 1 */
+#define EXTI_FTSR_TR2 0x00000004U /*!< Falling trigger event configuration bit of line 2 */
+#define EXTI_FTSR_TR3 0x00000008U /*!< Falling trigger event configuration bit of line 3 */
+#define EXTI_FTSR_TR4 0x00000010U /*!< Falling trigger event configuration bit of line 4 */
+#define EXTI_FTSR_TR5 0x00000020U /*!< Falling trigger event configuration bit of line 5 */
+#define EXTI_FTSR_TR6 0x00000040U /*!< Falling trigger event configuration bit of line 6 */
+#define EXTI_FTSR_TR7 0x00000080U /*!< Falling trigger event configuration bit of line 7 */
+#define EXTI_FTSR_TR8 0x00000100U /*!< Falling trigger event configuration bit of line 8 */
+#define EXTI_FTSR_TR9 0x00000200U /*!< Falling trigger event configuration bit of line 9 */
+#define EXTI_FTSR_TR10 0x00000400U /*!< Falling trigger event configuration bit of line 10 */
+#define EXTI_FTSR_TR11 0x00000800U /*!< Falling trigger event configuration bit of line 11 */
+#define EXTI_FTSR_TR12 0x00001000U /*!< Falling trigger event configuration bit of line 12 */
+#define EXTI_FTSR_TR13 0x00002000U /*!< Falling trigger event configuration bit of line 13 */
+#define EXTI_FTSR_TR14 0x00004000U /*!< Falling trigger event configuration bit of line 14 */
+#define EXTI_FTSR_TR15 0x00008000U /*!< Falling trigger event configuration bit of line 15 */
+#define EXTI_FTSR_TR16 0x00010000U /*!< Falling trigger event configuration bit of line 16 */
+#define EXTI_FTSR_TR17 0x00020000U /*!< Falling trigger event configuration bit of line 17 */
+#define EXTI_FTSR_TR18 0x00040000U /*!< Falling trigger event configuration bit of line 18 */
+#define EXTI_FTSR_TR19 0x00080000U /*!< Falling trigger event configuration bit of line 19 */
+#define EXTI_FTSR_TR20 0x00100000U /*!< Falling trigger event configuration bit of line 20 */
+#define EXTI_FTSR_TR21 0x00200000U /*!< Falling trigger event configuration bit of line 21 */
+#define EXTI_FTSR_TR22 0x00400000U /*!< Falling trigger event configuration bit of line 22 */
+
+/****************** Bit definition for EXTI_SWIER register ******************/
+#define EXTI_SWIER_SWIER0 0x00000001U /*!< Software Interrupt on line 0 */
+#define EXTI_SWIER_SWIER1 0x00000002U /*!< Software Interrupt on line 1 */
+#define EXTI_SWIER_SWIER2 0x00000004U /*!< Software Interrupt on line 2 */
+#define EXTI_SWIER_SWIER3 0x00000008U /*!< Software Interrupt on line 3 */
+#define EXTI_SWIER_SWIER4 0x00000010U /*!< Software Interrupt on line 4 */
+#define EXTI_SWIER_SWIER5 0x00000020U /*!< Software Interrupt on line 5 */
+#define EXTI_SWIER_SWIER6 0x00000040U /*!< Software Interrupt on line 6 */
+#define EXTI_SWIER_SWIER7 0x00000080U /*!< Software Interrupt on line 7 */
+#define EXTI_SWIER_SWIER8 0x00000100U /*!< Software Interrupt on line 8 */
+#define EXTI_SWIER_SWIER9 0x00000200U /*!< Software Interrupt on line 9 */
+#define EXTI_SWIER_SWIER10 0x00000400U /*!< Software Interrupt on line 10 */
+#define EXTI_SWIER_SWIER11 0x00000800U /*!< Software Interrupt on line 11 */
+#define EXTI_SWIER_SWIER12 0x00001000U /*!< Software Interrupt on line 12 */
+#define EXTI_SWIER_SWIER13 0x00002000U /*!< Software Interrupt on line 13 */
+#define EXTI_SWIER_SWIER14 0x00004000U /*!< Software Interrupt on line 14 */
+#define EXTI_SWIER_SWIER15 0x00008000U /*!< Software Interrupt on line 15 */
+#define EXTI_SWIER_SWIER16 0x00010000U /*!< Software Interrupt on line 16 */
+#define EXTI_SWIER_SWIER17 0x00020000U /*!< Software Interrupt on line 17 */
+#define EXTI_SWIER_SWIER18 0x00040000U /*!< Software Interrupt on line 18 */
+#define EXTI_SWIER_SWIER19 0x00080000U /*!< Software Interrupt on line 19 */
+#define EXTI_SWIER_SWIER20 0x00100000U /*!< Software Interrupt on line 20 */
+#define EXTI_SWIER_SWIER21 0x00200000U /*!< Software Interrupt on line 21 */
+#define EXTI_SWIER_SWIER22 0x00400000U /*!< Software Interrupt on line 22 */
+
+/******************* Bit definition for EXTI_PR register ********************/
+#define EXTI_PR_PR0 0x00000001U /*!< Pending bit for line 0 */
+#define EXTI_PR_PR1 0x00000002U /*!< Pending bit for line 1 */
+#define EXTI_PR_PR2 0x00000004U /*!< Pending bit for line 2 */
+#define EXTI_PR_PR3 0x00000008U /*!< Pending bit for line 3 */
+#define EXTI_PR_PR4 0x00000010U /*!< Pending bit for line 4 */
+#define EXTI_PR_PR5 0x00000020U /*!< Pending bit for line 5 */
+#define EXTI_PR_PR6 0x00000040U /*!< Pending bit for line 6 */
+#define EXTI_PR_PR7 0x00000080U /*!< Pending bit for line 7 */
+#define EXTI_PR_PR8 0x00000100U /*!< Pending bit for line 8 */
+#define EXTI_PR_PR9 0x00000200U /*!< Pending bit for line 9 */
+#define EXTI_PR_PR10 0x00000400U /*!< Pending bit for line 10 */
+#define EXTI_PR_PR11 0x00000800U /*!< Pending bit for line 11 */
+#define EXTI_PR_PR12 0x00001000U /*!< Pending bit for line 12 */
+#define EXTI_PR_PR13 0x00002000U /*!< Pending bit for line 13 */
+#define EXTI_PR_PR14 0x00004000U /*!< Pending bit for line 14 */
+#define EXTI_PR_PR15 0x00008000U /*!< Pending bit for line 15 */
+#define EXTI_PR_PR16 0x00010000U /*!< Pending bit for line 16 */
+#define EXTI_PR_PR17 0x00020000U /*!< Pending bit for line 17 */
+#define EXTI_PR_PR18 0x00040000U /*!< Pending bit for line 18 */
+#define EXTI_PR_PR19 0x00080000U /*!< Pending bit for line 19 */
+#define EXTI_PR_PR20 0x00100000U /*!< Pending bit for line 20 */
+#define EXTI_PR_PR21 0x00200000U /*!< Pending bit for line 21 */
+#define EXTI_PR_PR22 0x00400000U /*!< Pending bit for line 22 */
+
+/******************************************************************************/
+/* */
+/* FLASH */
+/* */
+/******************************************************************************/
+/******************* Bits definition for FLASH_ACR register *****************/
+#define FLASH_ACR_LATENCY 0x0000000FU
+#define FLASH_ACR_LATENCY_0WS 0x00000000U
+#define FLASH_ACR_LATENCY_1WS 0x00000001U
+#define FLASH_ACR_LATENCY_2WS 0x00000002U
+#define FLASH_ACR_LATENCY_3WS 0x00000003U
+#define FLASH_ACR_LATENCY_4WS 0x00000004U
+#define FLASH_ACR_LATENCY_5WS 0x00000005U
+#define FLASH_ACR_LATENCY_6WS 0x00000006U
+#define FLASH_ACR_LATENCY_7WS 0x00000007U
+
+#define FLASH_ACR_PRFTEN 0x00000100U
+#define FLASH_ACR_ICEN 0x00000200U
+#define FLASH_ACR_DCEN 0x00000400U
+#define FLASH_ACR_ICRST 0x00000800U
+#define FLASH_ACR_DCRST 0x00001000U
+#define FLASH_ACR_BYTE0_ADDRESS 0x40023C00U
+#define FLASH_ACR_BYTE2_ADDRESS 0x40023C03U
+
+/******************* Bits definition for FLASH_SR register ******************/
+#define FLASH_SR_EOP 0x00000001U
+#define FLASH_SR_SOP 0x00000002U
+#define FLASH_SR_WRPERR 0x00000010U
+#define FLASH_SR_PGAERR 0x00000020U
+#define FLASH_SR_PGPERR 0x00000040U
+#define FLASH_SR_PGSERR 0x00000080U
+#define FLASH_SR_BSY 0x00010000U
+
+/******************* Bits definition for FLASH_CR register ******************/
+#define FLASH_CR_PG 0x00000001U
+#define FLASH_CR_SER 0x00000002U
+#define FLASH_CR_MER 0x00000004U
+#define FLASH_CR_SNB 0x000000F8U
+#define FLASH_CR_SNB_0 0x00000008U
+#define FLASH_CR_SNB_1 0x00000010U
+#define FLASH_CR_SNB_2 0x00000020U
+#define FLASH_CR_SNB_3 0x00000040U
+#define FLASH_CR_SNB_4 0x00000080U
+#define FLASH_CR_PSIZE 0x00000300U
+#define FLASH_CR_PSIZE_0 0x00000100U
+#define FLASH_CR_PSIZE_1 0x00000200U
+#define FLASH_CR_STRT 0x00010000U
+#define FLASH_CR_EOPIE 0x01000000U
+#define FLASH_CR_LOCK 0x80000000U
+
+/******************* Bits definition for FLASH_OPTCR register ***************/
+#define FLASH_OPTCR_OPTLOCK 0x00000001U
+#define FLASH_OPTCR_OPTSTRT 0x00000002U
+#define FLASH_OPTCR_BOR_LEV_0 0x00000004U
+#define FLASH_OPTCR_BOR_LEV_1 0x00000008U
+#define FLASH_OPTCR_BOR_LEV 0x0000000CU
+
+#define FLASH_OPTCR_WDG_SW 0x00000020U
+#define FLASH_OPTCR_nRST_STOP 0x00000040U
+#define FLASH_OPTCR_nRST_STDBY 0x00000080U
+#define FLASH_OPTCR_RDP 0x0000FF00U
+#define FLASH_OPTCR_RDP_0 0x00000100U
+#define FLASH_OPTCR_RDP_1 0x00000200U
+#define FLASH_OPTCR_RDP_2 0x00000400U
+#define FLASH_OPTCR_RDP_3 0x00000800U
+#define FLASH_OPTCR_RDP_4 0x00001000U
+#define FLASH_OPTCR_RDP_5 0x00002000U
+#define FLASH_OPTCR_RDP_6 0x00004000U
+#define FLASH_OPTCR_RDP_7 0x00008000U
+#define FLASH_OPTCR_nWRP 0x0FFF0000U
+#define FLASH_OPTCR_nWRP_0 0x00010000U
+#define FLASH_OPTCR_nWRP_1 0x00020000U
+#define FLASH_OPTCR_nWRP_2 0x00040000U
+#define FLASH_OPTCR_nWRP_3 0x00080000U
+#define FLASH_OPTCR_nWRP_4 0x00100000U
+#define FLASH_OPTCR_nWRP_5 0x00200000U
+#define FLASH_OPTCR_nWRP_6 0x00400000U
+#define FLASH_OPTCR_nWRP_7 0x00800000U
+#define FLASH_OPTCR_nWRP_8 0x01000000U
+#define FLASH_OPTCR_nWRP_9 0x02000000U
+#define FLASH_OPTCR_nWRP_10 0x04000000U
+#define FLASH_OPTCR_nWRP_11 0x08000000U
+
+/****************** Bits definition for FLASH_OPTCR1 register ***************/
+#define FLASH_OPTCR1_nWRP 0x0FFF0000U
+#define FLASH_OPTCR1_nWRP_0 0x00010000U
+#define FLASH_OPTCR1_nWRP_1 0x00020000U
+#define FLASH_OPTCR1_nWRP_2 0x00040000U
+#define FLASH_OPTCR1_nWRP_3 0x00080000U
+#define FLASH_OPTCR1_nWRP_4 0x00100000U
+#define FLASH_OPTCR1_nWRP_5 0x00200000U
+#define FLASH_OPTCR1_nWRP_6 0x00400000U
+#define FLASH_OPTCR1_nWRP_7 0x00800000U
+#define FLASH_OPTCR1_nWRP_8 0x01000000U
+#define FLASH_OPTCR1_nWRP_9 0x02000000U
+#define FLASH_OPTCR1_nWRP_10 0x04000000U
+#define FLASH_OPTCR1_nWRP_11 0x08000000U
+
+/******************************************************************************/
+/* */
+/* Flexible Static Memory Controller */
+/* */
+/******************************************************************************/
+/****************** Bit definition for FSMC_BCR1 register *******************/
+#define FSMC_BCR1_MBKEN 0x00000001U /*!<Memory bank enable bit */
+#define FSMC_BCR1_MUXEN 0x00000002U /*!<Address/data multiplexing enable bit */
+
+#define FSMC_BCR1_MTYP 0x0000000CU /*!<MTYP[1:0] bits (Memory type) */
+#define FSMC_BCR1_MTYP_0 0x00000004U /*!<Bit 0 */
+#define FSMC_BCR1_MTYP_1 0x00000008U /*!<Bit 1 */
+
+#define FSMC_BCR1_MWID 0x00000030U /*!<MWID[1:0] bits (Memory data bus width) */
+#define FSMC_BCR1_MWID_0 0x00000010U /*!<Bit 0 */
+#define FSMC_BCR1_MWID_1 0x00000020U /*!<Bit 1 */
+
+#define FSMC_BCR1_FACCEN 0x00000040U /*!<Flash access enable */
+#define FSMC_BCR1_BURSTEN 0x00000100U /*!<Burst enable bit */
+#define FSMC_BCR1_WAITPOL 0x00000200U /*!<Wait signal polarity bit */
+#define FSMC_BCR1_WAITCFG 0x00000800U /*!<Wait timing configuration */
+#define FSMC_BCR1_WREN 0x00001000U /*!<Write enable bit */
+#define FSMC_BCR1_WAITEN 0x00002000U /*!<Wait enable bit */
+#define FSMC_BCR1_EXTMOD 0x00004000U /*!<Extended mode enable */
+#define FSMC_BCR1_ASYNCWAIT 0x00008000U /*!<Asynchronous wait */
+#define FSMC_BCR1_CPSIZE 0x00070000U /*!<CRAM page size */
+#define FSMC_BCR1_CPSIZE_0 0x00010000U /*!<Bit 0 */
+#define FSMC_BCR1_CPSIZE_1 0x00020000U /*!<Bit 1 */
+#define FSMC_BCR1_CPSIZE_2 0x00040000U /*!<Bit 2 */
+#define FSMC_BCR1_CBURSTRW 0x00080000U /*!<Write burst enable */
+#define FSMC_BCR1_CCLKEN 0x00100000U /*!<Continous clock enable */
+#define FSMC_BCR1_WFDIS 0x00200000U /*!<Write FIFO Disable */
+
+/****************** Bit definition for FSMC_BCR2 register *******************/
+#define FSMC_BCR2_MBKEN 0x00000001U /*!<Memory bank enable bit */
+#define FSMC_BCR2_MUXEN 0x00000002U /*!<Address/data multiplexing enable bit */
+
+#define FSMC_BCR2_MTYP 0x0000000CU /*!<MTYP[1:0] bits (Memory type) */
+#define FSMC_BCR2_MTYP_0 0x00000004U /*!<Bit 0 */
+#define FSMC_BCR2_MTYP_1 0x00000008U /*!<Bit 1 */
+
+#define FSMC_BCR2_MWID 0x00000030U /*!<MWID[1:0] bits (Memory data bus width) */
+#define FSMC_BCR2_MWID_0 0x00000010U /*!<Bit 0 */
+#define FSMC_BCR2_MWID_1 0x00000020U /*!<Bit 1 */
+
+#define FSMC_BCR2_FACCEN 0x00000040U /*!<Flash access enable */
+#define FSMC_BCR2_BURSTEN 0x00000100U /*!<Burst enable bit */
+#define FSMC_BCR2_WAITPOL 0x00000200U /*!<Wait signal polarity bit */
+#define FSMC_BCR2_WAITCFG 0x00000800U /*!<Wait timing configuration */
+#define FSMC_BCR2_WREN 0x00001000U /*!<Write enable bit */
+#define FSMC_BCR2_WAITEN 0x00002000U /*!<Wait enable bit */
+#define FSMC_BCR2_EXTMOD 0x00004000U /*!<Extended mode enable */
+#define FSMC_BCR2_CPSIZE 0x00070000U /*!<CRAM page size */
+#define FSMC_BCR2_CPSIZE_0 0x00010000U /*!<Bit 0 */
+#define FSMC_BCR2_CPSIZE_1 0x00020000U /*!<Bit 1 */
+#define FSMC_BCR2_CPSIZE_2 0x00040000U /*!<Bit 2 */
+#define FSMC_BCR2_ASYNCWAIT 0x00008000U /*!<Asynchronous wait */
+#define FSMC_BCR2_CBURSTRW 0x00080000U /*!<Write burst enable */
+
+/****************** Bit definition for FSMC_BCR3 register *******************/
+#define FSMC_BCR3_MBKEN 0x00000001U /*!<Memory bank enable bit */
+#define FSMC_BCR3_MUXEN 0x00000002U /*!<Address/data multiplexing enable bit */
+
+#define FSMC_BCR3_MTYP 0x0000000CU /*!<MTYP[1:0] bits (Memory type) */
+#define FSMC_BCR3_MTYP_0 0x00000004U /*!<Bit 0 */
+#define FSMC_BCR3_MTYP_1 0x00000008U /*!<Bit 1 */
+
+#define FSMC_BCR3_MWID 0x00000030U /*!<MWID[1:0] bits (Memory data bus width) */
+#define FSMC_BCR3_MWID_0 0x00000010U /*!<Bit 0 */
+#define FSMC_BCR3_MWID_1 0x00000020U /*!<Bit 1 */
+
+#define FSMC_BCR3_FACCEN 0x00000040U /*!<Flash access enable */
+#define FSMC_BCR3_BURSTEN 0x00000100U /*!<Burst enable bit */
+#define FSMC_BCR3_WAITPOL 0x00000200U /*!<Wait signal polarity bit */
+#define FSMC_BCR3_WAITCFG 0x00000800U /*!<Wait timing configuration */
+#define FSMC_BCR3_WREN 0x00001000U /*!<Write enable bit */
+#define FSMC_BCR3_WAITEN 0x00002000U /*!<Wait enable bit */
+#define FSMC_BCR3_EXTMOD 0x00004000U /*!<Extended mode enable */
+#define FSMC_BCR3_CPSIZE 0x00070000U /*!<CRAM page size */
+#define FSMC_BCR3_CPSIZE_0 0x00010000U /*!<Bit 0 */
+#define FSMC_BCR3_CPSIZE_1 0x00020000U /*!<Bit 1 */
+#define FSMC_BCR3_CPSIZE_2 0x00040000U /*!<Bit 2 */
+#define FSMC_BCR3_ASYNCWAIT 0x00008000U /*!<Asynchronous wait */
+#define FSMC_BCR3_CBURSTRW 0x00080000U /*!<Write burst enable */
+
+/****************** Bit definition for FSMC_BCR4 register *******************/
+#define FSMC_BCR4_MBKEN 0x00000001U /*!<Memory bank enable bit */
+#define FSMC_BCR4_MUXEN 0x00000002U /*!<Address/data multiplexing enable bit */
+
+#define FSMC_BCR4_MTYP 0x0000000CU /*!<MTYP[1:0] bits (Memory type) */
+#define FSMC_BCR4_MTYP_0 0x00000004U /*!<Bit 0 */
+#define FSMC_BCR4_MTYP_1 0x00000008U /*!<Bit 1 */
+
+#define FSMC_BCR4_MWID 0x00000030U /*!<MWID[1:0] bits (Memory data bus width) */
+#define FSMC_BCR4_MWID_0 0x00000010U /*!<Bit 0 */
+#define FSMC_BCR4_MWID_1 0x00000020U /*!<Bit 1 */
+
+#define FSMC_BCR4_FACCEN 0x00000040U /*!<Flash access enable */
+#define FSMC_BCR4_BURSTEN 0x00000100U /*!<Burst enable bit */
+#define FSMC_BCR4_WAITPOL 0x00000200U /*!<Wait signal polarity bit */
+#define FSMC_BCR4_WAITCFG 0x00000800U /*!<Wait timing configuration */
+#define FSMC_BCR4_WREN 0x00001000U /*!<Write enable bit */
+#define FSMC_BCR4_WAITEN 0x00002000U /*!<Wait enable bit */
+#define FSMC_BCR4_EXTMOD 0x00004000U /*!<Extended mode enable */
+#define FSMC_BCR4_CPSIZE 0x00070000U /*!<CRAM page size */
+#define FSMC_BCR4_CPSIZE_0 0x00010000U /*!<Bit 0 */
+#define FSMC_BCR4_CPSIZE_1 0x00020000U /*!<Bit 1 */
+#define FSMC_BCR4_CPSIZE_2 0x00040000U /*!<Bit 2 */
+#define FSMC_BCR4_ASYNCWAIT 0x00008000U /*!<Asynchronous wait */
+#define FSMC_BCR4_CBURSTRW 0x00080000U /*!<Write burst enable */
+
+/****************** Bit definition for FSMC_BTR1 register ******************/
+#define FSMC_BTR1_ADDSET 0x0000000FU /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FSMC_BTR1_ADDSET_0 0x00000001U /*!<Bit 0 */
+#define FSMC_BTR1_ADDSET_1 0x00000002U /*!<Bit 1 */
+#define FSMC_BTR1_ADDSET_2 0x00000004U /*!<Bit 2 */
+#define FSMC_BTR1_ADDSET_3 0x00000008U /*!<Bit 3 */
+
+#define FSMC_BTR1_ADDHLD 0x000000F0U /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FSMC_BTR1_ADDHLD_0 0x00000010U /*!<Bit 0 */
+#define FSMC_BTR1_ADDHLD_1 0x00000020U /*!<Bit 1 */
+#define FSMC_BTR1_ADDHLD_2 0x00000040U /*!<Bit 2 */
+#define FSMC_BTR1_ADDHLD_3 0x00000080U /*!<Bit 3 */
+
+#define FSMC_BTR1_DATAST 0x0000FF00U /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FSMC_BTR1_DATAST_0 0x00000100U /*!<Bit 0 */
+#define FSMC_BTR1_DATAST_1 0x00000200U /*!<Bit 1 */
+#define FSMC_BTR1_DATAST_2 0x00000400U /*!<Bit 2 */
+#define FSMC_BTR1_DATAST_3 0x00000800U /*!<Bit 3 */
+#define FSMC_BTR1_DATAST_4 0x00001000U /*!<Bit 4 */
+#define FSMC_BTR1_DATAST_5 0x00002000U /*!<Bit 5 */
+#define FSMC_BTR1_DATAST_6 0x00004000U /*!<Bit 6 */
+#define FSMC_BTR1_DATAST_7 0x00008000U /*!<Bit 7 */
+
+#define FSMC_BTR1_BUSTURN 0x000F0000U /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define FSMC_BTR1_BUSTURN_0 0x00010000U /*!<Bit 0 */
+#define FSMC_BTR1_BUSTURN_1 0x00020000U /*!<Bit 1 */
+#define FSMC_BTR1_BUSTURN_2 0x00040000U /*!<Bit 2 */
+#define FSMC_BTR1_BUSTURN_3 0x00080000U /*!<Bit 3 */
+
+#define FSMC_BTR1_CLKDIV 0x00F00000U /*!<CLKDIV[3:0] bits (Clock divide ratio) */
+#define FSMC_BTR1_CLKDIV_0 0x00100000U /*!<Bit 0 */
+#define FSMC_BTR1_CLKDIV_1 0x00200000U /*!<Bit 1 */
+#define FSMC_BTR1_CLKDIV_2 0x00400000U /*!<Bit 2 */
+#define FSMC_BTR1_CLKDIV_3 0x00800000U /*!<Bit 3 */
+
+#define FSMC_BTR1_DATLAT 0x0F000000U /*!<DATLA[3:0] bits (Data latency) */
+#define FSMC_BTR1_DATLAT_0 0x01000000U /*!<Bit 0 */
+#define FSMC_BTR1_DATLAT_1 0x02000000U /*!<Bit 1 */
+#define FSMC_BTR1_DATLAT_2 0x04000000U /*!<Bit 2 */
+#define FSMC_BTR1_DATLAT_3 0x08000000U /*!<Bit 3 */
+
+#define FSMC_BTR1_ACCMOD 0x30000000U /*!<ACCMOD[1:0] bits (Access mode) */
+#define FSMC_BTR1_ACCMOD_0 0x10000000U /*!<Bit 0 */
+#define FSMC_BTR1_ACCMOD_1 0x20000000U /*!<Bit 1 */
+
+/****************** Bit definition for FSMC_BTR2 register *******************/
+#define FSMC_BTR2_ADDSET 0x0000000FU /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FSMC_BTR2_ADDSET_0 0x00000001U /*!<Bit 0 */
+#define FSMC_BTR2_ADDSET_1 0x00000002U /*!<Bit 1 */
+#define FSMC_BTR2_ADDSET_2 0x00000004U /*!<Bit 2 */
+#define FSMC_BTR2_ADDSET_3 0x00000008U /*!<Bit 3 */
+
+#define FSMC_BTR2_ADDHLD 0x000000F0U /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FSMC_BTR2_ADDHLD_0 0x00000010U /*!<Bit 0 */
+#define FSMC_BTR2_ADDHLD_1 0x00000020U /*!<Bit 1 */
+#define FSMC_BTR2_ADDHLD_2 0x00000040U /*!<Bit 2 */
+#define FSMC_BTR2_ADDHLD_3 0x00000080U /*!<Bit 3 */
+
+#define FSMC_BTR2_DATAST 0x0000FF00U /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FSMC_BTR2_DATAST_0 0x00000100U /*!<Bit 0 */
+#define FSMC_BTR2_DATAST_1 0x00000200U /*!<Bit 1 */
+#define FSMC_BTR2_DATAST_2 0x00000400U /*!<Bit 2 */
+#define FSMC_BTR2_DATAST_3 0x00000800U /*!<Bit 3 */
+#define FSMC_BTR2_DATAST_4 0x00001000U /*!<Bit 4 */
+#define FSMC_BTR2_DATAST_5 0x00002000U /*!<Bit 5 */
+#define FSMC_BTR2_DATAST_6 0x00004000U /*!<Bit 6 */
+#define FSMC_BTR2_DATAST_7 0x00008000U /*!<Bit 7 */
+
+#define FSMC_BTR2_BUSTURN 0x000F0000U /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define FSMC_BTR2_BUSTURN_0 0x00010000U /*!<Bit 0 */
+#define FSMC_BTR2_BUSTURN_1 0x00020000U /*!<Bit 1 */
+#define FSMC_BTR2_BUSTURN_2 0x00040000U /*!<Bit 2 */
+#define FSMC_BTR2_BUSTURN_3 0x00080000U /*!<Bit 3 */
+
+#define FSMC_BTR2_CLKDIV 0x00F00000U /*!<CLKDIV[3:0] bits (Clock divide ratio) */
+#define FSMC_BTR2_CLKDIV_0 0x00100000U /*!<Bit 0 */
+#define FSMC_BTR2_CLKDIV_1 0x00200000U /*!<Bit 1 */
+#define FSMC_BTR2_CLKDIV_2 0x00400000U /*!<Bit 2 */
+#define FSMC_BTR2_CLKDIV_3 0x00800000U /*!<Bit 3 */
+
+#define FSMC_BTR2_DATLAT 0x0F000000U /*!<DATLA[3:0] bits (Data latency) */
+#define FSMC_BTR2_DATLAT_0 0x01000000U /*!<Bit 0 */
+#define FSMC_BTR2_DATLAT_1 0x02000000U /*!<Bit 1 */
+#define FSMC_BTR2_DATLAT_2 0x04000000U /*!<Bit 2 */
+#define FSMC_BTR2_DATLAT_3 0x08000000U /*!<Bit 3 */
+
+#define FSMC_BTR2_ACCMOD 0x30000000U /*!<ACCMOD[1:0] bits (Access mode) */
+#define FSMC_BTR2_ACCMOD_0 0x10000000U /*!<Bit 0 */
+#define FSMC_BTR2_ACCMOD_1 0x20000000U /*!<Bit 1 */
+
+/******************* Bit definition for FSMC_BTR3 register *******************/
+#define FSMC_BTR3_ADDSET 0x0000000FU /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FSMC_BTR3_ADDSET_0 0x00000001U /*!<Bit 0 */
+#define FSMC_BTR3_ADDSET_1 0x00000002U /*!<Bit 1 */
+#define FSMC_BTR3_ADDSET_2 0x00000004U /*!<Bit 2 */
+#define FSMC_BTR3_ADDSET_3 0x00000008U /*!<Bit 3 */
+
+#define FSMC_BTR3_ADDHLD 0x000000F0U /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FSMC_BTR3_ADDHLD_0 0x00000010U /*!<Bit 0 */
+#define FSMC_BTR3_ADDHLD_1 0x00000020U /*!<Bit 1 */
+#define FSMC_BTR3_ADDHLD_2 0x00000040U /*!<Bit 2 */
+#define FSMC_BTR3_ADDHLD_3 0x00000080U /*!<Bit 3 */
+
+#define FSMC_BTR3_DATAST 0x0000FF00U /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FSMC_BTR3_DATAST_0 0x00000100U /*!<Bit 0 */
+#define FSMC_BTR3_DATAST_1 0x00000200U /*!<Bit 1 */
+#define FSMC_BTR3_DATAST_2 0x00000400U /*!<Bit 2 */
+#define FSMC_BTR3_DATAST_3 0x00000800U /*!<Bit 3 */
+#define FSMC_BTR3_DATAST_4 0x00001000U /*!<Bit 4 */
+#define FSMC_BTR3_DATAST_5 0x00002000U /*!<Bit 5 */
+#define FSMC_BTR3_DATAST_6 0x00004000U /*!<Bit 6 */
+#define FSMC_BTR3_DATAST_7 0x00008000U /*!<Bit 7 */
+
+#define FSMC_BTR3_BUSTURN 0x000F0000U /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define FSMC_BTR3_BUSTURN_0 0x00010000U /*!<Bit 0 */
+#define FSMC_BTR3_BUSTURN_1 0x00020000U /*!<Bit 1 */
+#define FSMC_BTR3_BUSTURN_2 0x00040000U /*!<Bit 2 */
+#define FSMC_BTR3_BUSTURN_3 0x00080000U /*!<Bit 3 */
+
+#define FSMC_BTR3_CLKDIV 0x00F00000U /*!<CLKDIV[3:0] bits (Clock divide ratio) */
+#define FSMC_BTR3_CLKDIV_0 0x00100000U /*!<Bit 0 */
+#define FSMC_BTR3_CLKDIV_1 0x00200000U /*!<Bit 1 */
+#define FSMC_BTR3_CLKDIV_2 0x00400000U /*!<Bit 2 */
+#define FSMC_BTR3_CLKDIV_3 0x00800000U /*!<Bit 3 */
+
+#define FSMC_BTR3_DATLAT 0x0F000000U /*!<DATLA[3:0] bits (Data latency) */
+#define FSMC_BTR3_DATLAT_0 0x01000000U /*!<Bit 0 */
+#define FSMC_BTR3_DATLAT_1 0x02000000U /*!<Bit 1 */
+#define FSMC_BTR3_DATLAT_2 0x04000000U /*!<Bit 2 */
+#define FSMC_BTR3_DATLAT_3 0x08000000U /*!<Bit 3 */
+
+#define FSMC_BTR3_ACCMOD 0x30000000U /*!<ACCMOD[1:0] bits (Access mode) */
+#define FSMC_BTR3_ACCMOD_0 0x10000000U /*!<Bit 0 */
+#define FSMC_BTR3_ACCMOD_1 0x20000000U /*!<Bit 1 */
+
+/****************** Bit definition for FSMC_BTR4 register *******************/
+#define FSMC_BTR4_ADDSET 0x0000000FU /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FSMC_BTR4_ADDSET_0 0x00000001U /*!<Bit 0 */
+#define FSMC_BTR4_ADDSET_1 0x00000002U /*!<Bit 1 */
+#define FSMC_BTR4_ADDSET_2 0x00000004U /*!<Bit 2 */
+#define FSMC_BTR4_ADDSET_3 0x00000008U /*!<Bit 3 */
+
+#define FSMC_BTR4_ADDHLD 0x000000F0U /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FSMC_BTR4_ADDHLD_0 0x00000010U /*!<Bit 0 */
+#define FSMC_BTR4_ADDHLD_1 0x00000020U /*!<Bit 1 */
+#define FSMC_BTR4_ADDHLD_2 0x00000040U /*!<Bit 2 */
+#define FSMC_BTR4_ADDHLD_3 0x00000080U /*!<Bit 3 */
+
+#define FSMC_BTR4_DATAST 0x0000FF00U /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FSMC_BTR4_DATAST_0 0x00000100U /*!<Bit 0 */
+#define FSMC_BTR4_DATAST_1 0x00000200U /*!<Bit 1 */
+#define FSMC_BTR4_DATAST_2 0x00000400U /*!<Bit 2 */
+#define FSMC_BTR4_DATAST_3 0x00000800U /*!<Bit 3 */
+#define FSMC_BTR4_DATAST_4 0x00001000U /*!<Bit 4 */
+#define FSMC_BTR4_DATAST_5 0x00002000U /*!<Bit 5 */
+#define FSMC_BTR4_DATAST_6 0x00004000U /*!<Bit 6 */
+#define FSMC_BTR4_DATAST_7 0x00008000U /*!<Bit 7 */
+
+#define FSMC_BTR4_BUSTURN 0x000F0000U /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define FSMC_BTR4_BUSTURN_0 0x00010000U /*!<Bit 0 */
+#define FSMC_BTR4_BUSTURN_1 0x00020000U /*!<Bit 1 */
+#define FSMC_BTR4_BUSTURN_2 0x00040000U /*!<Bit 2 */
+#define FSMC_BTR4_BUSTURN_3 0x00080000U /*!<Bit 3 */
+
+#define FSMC_BTR4_CLKDIV 0x00F00000U /*!<CLKDIV[3:0] bits (Clock divide ratio) */
+#define FSMC_BTR4_CLKDIV_0 0x00100000U /*!<Bit 0 */
+#define FSMC_BTR4_CLKDIV_1 0x00200000U /*!<Bit 1 */
+#define FSMC_BTR4_CLKDIV_2 0x00400000U /*!<Bit 2 */
+#define FSMC_BTR4_CLKDIV_3 0x00800000U /*!<Bit 3 */
+
+#define FSMC_BTR4_DATLAT 0x0F000000U /*!<DATLA[3:0] bits (Data latency) */
+#define FSMC_BTR4_DATLAT_0 0x01000000U /*!<Bit 0 */
+#define FSMC_BTR4_DATLAT_1 0x02000000U /*!<Bit 1 */
+#define FSMC_BTR4_DATLAT_2 0x04000000U /*!<Bit 2 */
+#define FSMC_BTR4_DATLAT_3 0x08000000U /*!<Bit 3 */
+
+#define FSMC_BTR4_ACCMOD 0x30000000U /*!<ACCMOD[1:0] bits (Access mode) */
+#define FSMC_BTR4_ACCMOD_0 0x10000000U /*!<Bit 0 */
+#define FSMC_BTR4_ACCMOD_1 0x20000000U /*!<Bit 1 */
+
+/****************** Bit definition for FSMC_BWTR1 register ******************/
+#define FSMC_BWTR1_ADDSET 0x0000000FU /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FSMC_BWTR1_ADDSET_0 0x00000001U /*!<Bit 0 */
+#define FSMC_BWTR1_ADDSET_1 0x00000002U /*!<Bit 1 */
+#define FSMC_BWTR1_ADDSET_2 0x00000004U /*!<Bit 2 */
+#define FSMC_BWTR1_ADDSET_3 0x00000008U /*!<Bit 3 */
+
+#define FSMC_BWTR1_ADDHLD 0x000000F0U /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FSMC_BWTR1_ADDHLD_0 0x00000010U /*!<Bit 0 */
+#define FSMC_BWTR1_ADDHLD_1 0x00000020U /*!<Bit 1 */
+#define FSMC_BWTR1_ADDHLD_2 0x00000040U /*!<Bit 2 */
+#define FSMC_BWTR1_ADDHLD_3 0x00000080U /*!<Bit 3 */
+
+#define FSMC_BWTR1_DATAST 0x0000FF00U /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FSMC_BWTR1_DATAST_0 0x00000100U /*!<Bit 0 */
+#define FSMC_BWTR1_DATAST_1 0x00000200U /*!<Bit 1 */
+#define FSMC_BWTR1_DATAST_2 0x00000400U /*!<Bit 2 */
+#define FSMC_BWTR1_DATAST_3 0x00000800U /*!<Bit 3 */
+#define FSMC_BWTR1_DATAST_4 0x00001000U /*!<Bit 4 */
+#define FSMC_BWTR1_DATAST_5 0x00002000U /*!<Bit 5 */
+#define FSMC_BWTR1_DATAST_6 0x00004000U /*!<Bit 6 */
+#define FSMC_BWTR1_DATAST_7 0x00008000U /*!<Bit 7 */
+
+#define FSMC_BWTR1_BUSTURN 0x000F0000U /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
+#define FSMC_BWTR1_BUSTURN_0 0x00010000U /*!<Bit 0 */
+#define FSMC_BWTR1_BUSTURN_1 0x00020000U /*!<Bit 1 */
+#define FSMC_BWTR1_BUSTURN_2 0x00040000U /*!<Bit 2 */
+#define FSMC_BWTR1_BUSTURN_3 0x00080000U /*!<Bit 3 */
+
+#define FSMC_BWTR1_ACCMOD 0x30000000U /*!<ACCMOD[1:0] bits (Access mode) */
+#define FSMC_BWTR1_ACCMOD_0 0x10000000U /*!<Bit 0 */
+#define FSMC_BWTR1_ACCMOD_1 0x20000000U /*!<Bit 1 */
+
+/****************** Bit definition for FSMC_BWTR2 register ******************/
+#define FSMC_BWTR2_ADDSET 0x0000000FU /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FSMC_BWTR2_ADDSET_0 0x00000001U /*!<Bit 0 */
+#define FSMC_BWTR2_ADDSET_1 0x00000002U /*!<Bit 1 */
+#define FSMC_BWTR2_ADDSET_2 0x00000004U /*!<Bit 2 */
+#define FSMC_BWTR2_ADDSET_3 0x00000008U /*!<Bit 3 */
+
+#define FSMC_BWTR2_ADDHLD 0x000000F0U /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FSMC_BWTR2_ADDHLD_0 0x00000010U /*!<Bit 0 */
+#define FSMC_BWTR2_ADDHLD_1 0x00000020U /*!<Bit 1 */
+#define FSMC_BWTR2_ADDHLD_2 0x00000040U /*!<Bit 2 */
+#define FSMC_BWTR2_ADDHLD_3 0x00000080U /*!<Bit 3 */
+
+#define FSMC_BWTR2_DATAST 0x0000FF00U /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FSMC_BWTR2_DATAST_0 0x00000100U /*!<Bit 0 */
+#define FSMC_BWTR2_DATAST_1 0x00000200U /*!<Bit 1 */
+#define FSMC_BWTR2_DATAST_2 0x00000400U /*!<Bit 2 */
+#define FSMC_BWTR2_DATAST_3 0x00000800U /*!<Bit 3 */
+#define FSMC_BWTR2_DATAST_4 0x00001000U /*!<Bit 4 */
+#define FSMC_BWTR2_DATAST_5 0x00002000U /*!<Bit 5 */
+#define FSMC_BWTR2_DATAST_6 0x00004000U /*!<Bit 6 */
+#define FSMC_BWTR2_DATAST_7 0x00008000U /*!<Bit 7 */
+
+#define FSMC_BWTR2_BUSTURN 0x000F0000U /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
+#define FSMC_BWTR2_BUSTURN_0 0x00010000U /*!<Bit 0 */
+#define FSMC_BWTR2_BUSTURN_1 0x00020000U /*!<Bit 1 */
+#define FSMC_BWTR2_BUSTURN_2 0x00040000U /*!<Bit 2 */
+#define FSMC_BWTR2_BUSTURN_3 0x00080000U /*!<Bit 3 */
+
+#define FSMC_BWTR2_ACCMOD 0x30000000U /*!<ACCMOD[1:0] bits (Access mode) */
+#define FSMC_BWTR2_ACCMOD_0 0x10000000U /*!<Bit 0 */
+#define FSMC_BWTR2_ACCMOD_1 0x20000000U /*!<Bit 1 */
+
+/****************** Bit definition for FSMC_BWTR3 register ******************/
+#define FSMC_BWTR3_ADDSET 0x0000000FU /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FSMC_BWTR3_ADDSET_0 0x00000001U /*!<Bit 0 */
+#define FSMC_BWTR3_ADDSET_1 0x00000002U /*!<Bit 1 */
+#define FSMC_BWTR3_ADDSET_2 0x00000004U /*!<Bit 2 */
+#define FSMC_BWTR3_ADDSET_3 0x00000008U /*!<Bit 3 */
+
+#define FSMC_BWTR3_ADDHLD 0x000000F0U /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FSMC_BWTR3_ADDHLD_0 0x00000010U /*!<Bit 0 */
+#define FSMC_BWTR3_ADDHLD_1 0x00000020U /*!<Bit 1 */
+#define FSMC_BWTR3_ADDHLD_2 0x00000040U /*!<Bit 2 */
+#define FSMC_BWTR3_ADDHLD_3 0x00000080U /*!<Bit 3 */
+
+#define FSMC_BWTR3_DATAST 0x0000FF00U /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FSMC_BWTR3_DATAST_0 0x00000100U /*!<Bit 0 */
+#define FSMC_BWTR3_DATAST_1 0x00000200U /*!<Bit 1 */
+#define FSMC_BWTR3_DATAST_2 0x00000400U /*!<Bit 2 */
+#define FSMC_BWTR3_DATAST_3 0x00000800U /*!<Bit 3 */
+#define FSMC_BWTR3_DATAST_4 0x00001000U /*!<Bit 4 */
+#define FSMC_BWTR3_DATAST_5 0x00002000U /*!<Bit 5 */
+#define FSMC_BWTR3_DATAST_6 0x00004000U /*!<Bit 6 */
+#define FSMC_BWTR3_DATAST_7 0x00008000U /*!<Bit 7 */
+
+#define FSMC_BWTR3_BUSTURN 0x000F0000U /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
+#define FSMC_BWTR3_BUSTURN_0 0x00010000U /*!<Bit 0 */
+#define FSMC_BWTR3_BUSTURN_1 0x00020000U /*!<Bit 1 */
+#define FSMC_BWTR3_BUSTURN_2 0x00040000U /*!<Bit 2 */
+#define FSMC_BWTR3_BUSTURN_3 0x00080000U /*!<Bit 3 */
+
+#define FSMC_BWTR3_ACCMOD 0x30000000U /*!<ACCMOD[1:0] bits (Access mode) */
+#define FSMC_BWTR3_ACCMOD_0 0x10000000U /*!<Bit 0 */
+#define FSMC_BWTR3_ACCMOD_1 0x20000000U /*!<Bit 1 */
+
+/****************** Bit definition for FSMC_BWTR4 register ******************/
+#define FSMC_BWTR4_ADDSET 0x0000000FU /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FSMC_BWTR4_ADDSET_0 0x00000001U /*!<Bit 0 */
+#define FSMC_BWTR4_ADDSET_1 0x00000002U /*!<Bit 1 */
+#define FSMC_BWTR4_ADDSET_2 0x00000004U /*!<Bit 2 */
+#define FSMC_BWTR4_ADDSET_3 0x00000008U /*!<Bit 3 */
+
+#define FSMC_BWTR4_ADDHLD 0x000000F0U /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FSMC_BWTR4_ADDHLD_0 0x00000010U /*!<Bit 0 */
+#define FSMC_BWTR4_ADDHLD_1 0x00000020U /*!<Bit 1 */
+#define FSMC_BWTR4_ADDHLD_2 0x00000040U /*!<Bit 2 */
+#define FSMC_BWTR4_ADDHLD_3 0x00000080U /*!<Bit 3 */
+
+#define FSMC_BWTR4_DATAST 0x0000FF00U /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FSMC_BWTR4_DATAST_0 0x00000100U /*!<Bit 0 */
+#define FSMC_BWTR4_DATAST_1 0x00000200U /*!<Bit 1 */
+#define FSMC_BWTR4_DATAST_2 0x00000400U /*!<Bit 2 */
+#define FSMC_BWTR4_DATAST_3 0x00000800U /*!<Bit 3 */
+#define FSMC_BWTR4_DATAST_4 0x00001000U /*!<Bit 4 */
+#define FSMC_BWTR4_DATAST_5 0x00002000U /*!<Bit 5 */
+#define FSMC_BWTR4_DATAST_6 0x00004000U /*!<Bit 6 */
+#define FSMC_BWTR4_DATAST_7 0x00008000U /*!<Bit 7 */
+
+#define FSMC_BWTR4_BUSTURN 0x000F0000U /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
+#define FSMC_BWTR4_BUSTURN_0 0x00010000U /*!<Bit 0 */
+#define FSMC_BWTR4_BUSTURN_1 0x00020000U /*!<Bit 1 */
+#define FSMC_BWTR4_BUSTURN_2 0x00040000U /*!<Bit 2 */
+#define FSMC_BWTR4_BUSTURN_3 0x00080000U /*!<Bit 3 */
+
+#define FSMC_BWTR4_ACCMOD 0x30000000U /*!<ACCMOD[1:0] bits (Access mode) */
+#define FSMC_BWTR4_ACCMOD_0 0x10000000U /*!<Bit 0 */
+#define FSMC_BWTR4_ACCMOD_1 0x20000000U /*!<Bit 1 */
+
+/******************************************************************************/
+/* */
+/* General Purpose I/O */
+/* */
+/******************************************************************************/
+/****************** Bits definition for GPIO_MODER register *****************/
+#define GPIO_MODER_MODER0 0x00000003U
+#define GPIO_MODER_MODER0_0 0x00000001U
+#define GPIO_MODER_MODER0_1 0x00000002U
+
+#define GPIO_MODER_MODER1 0x0000000CU
+#define GPIO_MODER_MODER1_0 0x00000004U
+#define GPIO_MODER_MODER1_1 0x00000008U
+
+#define GPIO_MODER_MODER2 0x00000030U
+#define GPIO_MODER_MODER2_0 0x00000010U
+#define GPIO_MODER_MODER2_1 0x00000020U
+
+#define GPIO_MODER_MODER3 0x000000C0U
+#define GPIO_MODER_MODER3_0 0x00000040U
+#define GPIO_MODER_MODER3_1 0x00000080U
+
+#define GPIO_MODER_MODER4 0x00000300U
+#define GPIO_MODER_MODER4_0 0x00000100U
+#define GPIO_MODER_MODER4_1 0x00000200U
+
+#define GPIO_MODER_MODER5 0x00000C00U
+#define GPIO_MODER_MODER5_0 0x00000400U
+#define GPIO_MODER_MODER5_1 0x00000800U
+
+#define GPIO_MODER_MODER6 0x00003000U
+#define GPIO_MODER_MODER6_0 0x00001000U
+#define GPIO_MODER_MODER6_1 0x00002000U
+
+#define GPIO_MODER_MODER7 0x0000C000U
+#define GPIO_MODER_MODER7_0 0x00004000U
+#define GPIO_MODER_MODER7_1 0x00008000U
+
+#define GPIO_MODER_MODER8 0x00030000U
+#define GPIO_MODER_MODER8_0 0x00010000U
+#define GPIO_MODER_MODER8_1 0x00020000U
+
+#define GPIO_MODER_MODER9 0x000C0000U
+#define GPIO_MODER_MODER9_0 0x00040000U
+#define GPIO_MODER_MODER9_1 0x00080000U
+
+#define GPIO_MODER_MODER10 0x00300000U
+#define GPIO_MODER_MODER10_0 0x00100000U
+#define GPIO_MODER_MODER10_1 0x00200000U
+
+#define GPIO_MODER_MODER11 0x00C00000U
+#define GPIO_MODER_MODER11_0 0x00400000U
+#define GPIO_MODER_MODER11_1 0x00800000U
+
+#define GPIO_MODER_MODER12 0x03000000U
+#define GPIO_MODER_MODER12_0 0x01000000U
+#define GPIO_MODER_MODER12_1 0x02000000U
+
+#define GPIO_MODER_MODER13 0x0C000000U
+#define GPIO_MODER_MODER13_0 0x04000000U
+#define GPIO_MODER_MODER13_1 0x08000000U
+
+#define GPIO_MODER_MODER14 0x30000000U
+#define GPIO_MODER_MODER14_0 0x10000000U
+#define GPIO_MODER_MODER14_1 0x20000000U
+
+#define GPIO_MODER_MODER15 0xC0000000U
+#define GPIO_MODER_MODER15_0 0x40000000U
+#define GPIO_MODER_MODER15_1 0x80000000U
+
+/****************** Bits definition for GPIO_OTYPER register ****************/
+#define GPIO_OTYPER_OT_0 0x00000001U
+#define GPIO_OTYPER_OT_1 0x00000002U
+#define GPIO_OTYPER_OT_2 0x00000004U
+#define GPIO_OTYPER_OT_3 0x00000008U
+#define GPIO_OTYPER_OT_4 0x00000010U
+#define GPIO_OTYPER_OT_5 0x00000020U
+#define GPIO_OTYPER_OT_6 0x00000040U
+#define GPIO_OTYPER_OT_7 0x00000080U
+#define GPIO_OTYPER_OT_8 0x00000100U
+#define GPIO_OTYPER_OT_9 0x00000200U
+#define GPIO_OTYPER_OT_10 0x00000400U
+#define GPIO_OTYPER_OT_11 0x00000800U
+#define GPIO_OTYPER_OT_12 0x00001000U
+#define GPIO_OTYPER_OT_13 0x00002000U
+#define GPIO_OTYPER_OT_14 0x00004000U
+#define GPIO_OTYPER_OT_15 0x00008000U
+
+/****************** Bits definition for GPIO_OSPEEDR register ***************/
+#define GPIO_OSPEEDER_OSPEEDR0 0x00000003U
+#define GPIO_OSPEEDER_OSPEEDR0_0 0x00000001U
+#define GPIO_OSPEEDER_OSPEEDR0_1 0x00000002U
+
+#define GPIO_OSPEEDER_OSPEEDR1 0x0000000CU
+#define GPIO_OSPEEDER_OSPEEDR1_0 0x00000004U
+#define GPIO_OSPEEDER_OSPEEDR1_1 0x00000008U
+
+#define GPIO_OSPEEDER_OSPEEDR2 0x00000030U
+#define GPIO_OSPEEDER_OSPEEDR2_0 0x00000010U
+#define GPIO_OSPEEDER_OSPEEDR2_1 0x00000020U
+
+#define GPIO_OSPEEDER_OSPEEDR3 0x000000C0U
+#define GPIO_OSPEEDER_OSPEEDR3_0 0x00000040U
+#define GPIO_OSPEEDER_OSPEEDR3_1 0x00000080U
+
+#define GPIO_OSPEEDER_OSPEEDR4 0x00000300U
+#define GPIO_OSPEEDER_OSPEEDR4_0 0x00000100U
+#define GPIO_OSPEEDER_OSPEEDR4_1 0x00000200U
+
+#define GPIO_OSPEEDER_OSPEEDR5 0x00000C00U
+#define GPIO_OSPEEDER_OSPEEDR5_0 0x00000400U
+#define GPIO_OSPEEDER_OSPEEDR5_1 0x00000800U
+
+#define GPIO_OSPEEDER_OSPEEDR6 0x00003000U
+#define GPIO_OSPEEDER_OSPEEDR6_0 0x00001000U
+#define GPIO_OSPEEDER_OSPEEDR6_1 0x00002000U
+
+#define GPIO_OSPEEDER_OSPEEDR7 0x0000C000U
+#define GPIO_OSPEEDER_OSPEEDR7_0 0x00004000U
+#define GPIO_OSPEEDER_OSPEEDR7_1 0x00008000U
+
+#define GPIO_OSPEEDER_OSPEEDR8 0x00030000U
+#define GPIO_OSPEEDER_OSPEEDR8_0 0x00010000U
+#define GPIO_OSPEEDER_OSPEEDR8_1 0x00020000U
+
+#define GPIO_OSPEEDER_OSPEEDR9 0x000C0000U
+#define GPIO_OSPEEDER_OSPEEDR9_0 0x00040000U
+#define GPIO_OSPEEDER_OSPEEDR9_1 0x00080000U
+
+#define GPIO_OSPEEDER_OSPEEDR10 0x00300000U
+#define GPIO_OSPEEDER_OSPEEDR10_0 0x00100000U
+#define GPIO_OSPEEDER_OSPEEDR10_1 0x00200000U
+
+#define GPIO_OSPEEDER_OSPEEDR11 0x00C00000U
+#define GPIO_OSPEEDER_OSPEEDR11_0 0x00400000U
+#define GPIO_OSPEEDER_OSPEEDR11_1 0x00800000U
+
+#define GPIO_OSPEEDER_OSPEEDR12 0x03000000U
+#define GPIO_OSPEEDER_OSPEEDR12_0 0x01000000U
+#define GPIO_OSPEEDER_OSPEEDR12_1 0x02000000U
+
+#define GPIO_OSPEEDER_OSPEEDR13 0x0C000000U
+#define GPIO_OSPEEDER_OSPEEDR13_0 0x04000000U
+#define GPIO_OSPEEDER_OSPEEDR13_1 0x08000000U
+
+#define GPIO_OSPEEDER_OSPEEDR14 0x30000000U
+#define GPIO_OSPEEDER_OSPEEDR14_0 0x10000000U
+#define GPIO_OSPEEDER_OSPEEDR14_1 0x20000000U
+
+#define GPIO_OSPEEDER_OSPEEDR15 0xC0000000U
+#define GPIO_OSPEEDER_OSPEEDR15_0 0x40000000U
+#define GPIO_OSPEEDER_OSPEEDR15_1 0x80000000U
+
+/****************** Bits definition for GPIO_PUPDR register *****************/
+#define GPIO_PUPDR_PUPDR0 0x00000003U
+#define GPIO_PUPDR_PUPDR0_0 0x00000001U
+#define GPIO_PUPDR_PUPDR0_1 0x00000002U
+
+#define GPIO_PUPDR_PUPDR1 0x0000000CU
+#define GPIO_PUPDR_PUPDR1_0 0x00000004U
+#define GPIO_PUPDR_PUPDR1_1 0x00000008U
+
+#define GPIO_PUPDR_PUPDR2 0x00000030U
+#define GPIO_PUPDR_PUPDR2_0 0x00000010U
+#define GPIO_PUPDR_PUPDR2_1 0x00000020U
+
+#define GPIO_PUPDR_PUPDR3 0x000000C0U
+#define GPIO_PUPDR_PUPDR3_0 0x00000040U
+#define GPIO_PUPDR_PUPDR3_1 0x00000080U
+
+#define GPIO_PUPDR_PUPDR4 0x00000300U
+#define GPIO_PUPDR_PUPDR4_0 0x00000100U
+#define GPIO_PUPDR_PUPDR4_1 0x00000200U
+
+#define GPIO_PUPDR_PUPDR5 0x00000C00U
+#define GPIO_PUPDR_PUPDR5_0 0x00000400U
+#define GPIO_PUPDR_PUPDR5_1 0x00000800U
+
+#define GPIO_PUPDR_PUPDR6 0x00003000U
+#define GPIO_PUPDR_PUPDR6_0 0x00001000U
+#define GPIO_PUPDR_PUPDR6_1 0x00002000U
+
+#define GPIO_PUPDR_PUPDR7 0x0000C000U
+#define GPIO_PUPDR_PUPDR7_0 0x00004000U
+#define GPIO_PUPDR_PUPDR7_1 0x00008000U
+
+#define GPIO_PUPDR_PUPDR8 0x00030000U
+#define GPIO_PUPDR_PUPDR8_0 0x00010000U
+#define GPIO_PUPDR_PUPDR8_1 0x00020000U
+
+#define GPIO_PUPDR_PUPDR9 0x000C0000U
+#define GPIO_PUPDR_PUPDR9_0 0x00040000U
+#define GPIO_PUPDR_PUPDR9_1 0x00080000U
+
+#define GPIO_PUPDR_PUPDR10 0x00300000U
+#define GPIO_PUPDR_PUPDR10_0 0x00100000U
+#define GPIO_PUPDR_PUPDR10_1 0x00200000U
+
+#define GPIO_PUPDR_PUPDR11 0x00C00000U
+#define GPIO_PUPDR_PUPDR11_0 0x00400000U
+#define GPIO_PUPDR_PUPDR11_1 0x00800000U
+
+#define GPIO_PUPDR_PUPDR12 0x03000000U
+#define GPIO_PUPDR_PUPDR12_0 0x01000000U
+#define GPIO_PUPDR_PUPDR12_1 0x02000000U
+
+#define GPIO_PUPDR_PUPDR13 0x0C000000U
+#define GPIO_PUPDR_PUPDR13_0 0x04000000U
+#define GPIO_PUPDR_PUPDR13_1 0x08000000U
+
+#define GPIO_PUPDR_PUPDR14 0x30000000U
+#define GPIO_PUPDR_PUPDR14_0 0x10000000U
+#define GPIO_PUPDR_PUPDR14_1 0x20000000U
+
+#define GPIO_PUPDR_PUPDR15 0xC0000000U
+#define GPIO_PUPDR_PUPDR15_0 0x40000000U
+#define GPIO_PUPDR_PUPDR15_1 0x80000000U
+
+/****************** Bits definition for GPIO_IDR register *******************/
+#define GPIO_IDR_IDR_0 0x00000001U
+#define GPIO_IDR_IDR_1 0x00000002U
+#define GPIO_IDR_IDR_2 0x00000004U
+#define GPIO_IDR_IDR_3 0x00000008U
+#define GPIO_IDR_IDR_4 0x00000010U
+#define GPIO_IDR_IDR_5 0x00000020U
+#define GPIO_IDR_IDR_6 0x00000040U
+#define GPIO_IDR_IDR_7 0x00000080U
+#define GPIO_IDR_IDR_8 0x00000100U
+#define GPIO_IDR_IDR_9 0x00000200U
+#define GPIO_IDR_IDR_10 0x00000400U
+#define GPIO_IDR_IDR_11 0x00000800U
+#define GPIO_IDR_IDR_12 0x00001000U
+#define GPIO_IDR_IDR_13 0x00002000U
+#define GPIO_IDR_IDR_14 0x00004000U
+#define GPIO_IDR_IDR_15 0x00008000U
+
+/****************** Bits definition for GPIO_ODR register *******************/
+#define GPIO_ODR_ODR_0 0x00000001U
+#define GPIO_ODR_ODR_1 0x00000002U
+#define GPIO_ODR_ODR_2 0x00000004U
+#define GPIO_ODR_ODR_3 0x00000008U
+#define GPIO_ODR_ODR_4 0x00000010U
+#define GPIO_ODR_ODR_5 0x00000020U
+#define GPIO_ODR_ODR_6 0x00000040U
+#define GPIO_ODR_ODR_7 0x00000080U
+#define GPIO_ODR_ODR_8 0x00000100U
+#define GPIO_ODR_ODR_9 0x00000200U
+#define GPIO_ODR_ODR_10 0x00000400U
+#define GPIO_ODR_ODR_11 0x00000800U
+#define GPIO_ODR_ODR_12 0x00001000U
+#define GPIO_ODR_ODR_13 0x00002000U
+#define GPIO_ODR_ODR_14 0x00004000U
+#define GPIO_ODR_ODR_15 0x00008000U
+
+/****************** Bits definition for GPIO_BSRR register ******************/
+#define GPIO_BSRR_BS_0 0x00000001U
+#define GPIO_BSRR_BS_1 0x00000002U
+#define GPIO_BSRR_BS_2 0x00000004U
+#define GPIO_BSRR_BS_3 0x00000008U
+#define GPIO_BSRR_BS_4 0x00000010U
+#define GPIO_BSRR_BS_5 0x00000020U
+#define GPIO_BSRR_BS_6 0x00000040U
+#define GPIO_BSRR_BS_7 0x00000080U
+#define GPIO_BSRR_BS_8 0x00000100U
+#define GPIO_BSRR_BS_9 0x00000200U
+#define GPIO_BSRR_BS_10 0x00000400U
+#define GPIO_BSRR_BS_11 0x00000800U
+#define GPIO_BSRR_BS_12 0x00001000U
+#define GPIO_BSRR_BS_13 0x00002000U
+#define GPIO_BSRR_BS_14 0x00004000U
+#define GPIO_BSRR_BS_15 0x00008000U
+#define GPIO_BSRR_BR_0 0x00010000U
+#define GPIO_BSRR_BR_1 0x00020000U
+#define GPIO_BSRR_BR_2 0x00040000U
+#define GPIO_BSRR_BR_3 0x00080000U
+#define GPIO_BSRR_BR_4 0x00100000U
+#define GPIO_BSRR_BR_5 0x00200000U
+#define GPIO_BSRR_BR_6 0x00400000U
+#define GPIO_BSRR_BR_7 0x00800000U
+#define GPIO_BSRR_BR_8 0x01000000U
+#define GPIO_BSRR_BR_9 0x02000000U
+#define GPIO_BSRR_BR_10 0x04000000U
+#define GPIO_BSRR_BR_11 0x08000000U
+#define GPIO_BSRR_BR_12 0x10000000U
+#define GPIO_BSRR_BR_13 0x20000000U
+#define GPIO_BSRR_BR_14 0x40000000U
+#define GPIO_BSRR_BR_15 0x80000000U
+
+/****************** Bit definition for GPIO_LCKR register *********************/
+#define GPIO_LCKR_LCK0 0x00000001U
+#define GPIO_LCKR_LCK1 0x00000002U
+#define GPIO_LCKR_LCK2 0x00000004U
+#define GPIO_LCKR_LCK3 0x00000008U
+#define GPIO_LCKR_LCK4 0x00000010U
+#define GPIO_LCKR_LCK5 0x00000020U
+#define GPIO_LCKR_LCK6 0x00000040U
+#define GPIO_LCKR_LCK7 0x00000080U
+#define GPIO_LCKR_LCK8 0x00000100U
+#define GPIO_LCKR_LCK9 0x00000200U
+#define GPIO_LCKR_LCK10 0x00000400U
+#define GPIO_LCKR_LCK11 0x00000800U
+#define GPIO_LCKR_LCK12 0x00001000U
+#define GPIO_LCKR_LCK13 0x00002000U
+#define GPIO_LCKR_LCK14 0x00004000U
+#define GPIO_LCKR_LCK15 0x00008000U
+#define GPIO_LCKR_LCKK 0x00010000U
+
+/******************************************************************************/
+/* */
+/* Inter-integrated Circuit Interface */
+/* */
+/******************************************************************************/
+/******************* Bit definition for I2C_CR1 register ********************/
+#define I2C_CR1_PE 0x00000001U /*!<Peripheral Enable */
+#define I2C_CR1_SMBUS 0x00000002U /*!<SMBus Mode */
+#define I2C_CR1_SMBTYPE 0x00000008U /*!<SMBus Type */
+#define I2C_CR1_ENARP 0x00000010U /*!<ARP Enable */
+#define I2C_CR1_ENPEC 0x00000020U /*!<PEC Enable */
+#define I2C_CR1_ENGC 0x00000040U /*!<General Call Enable */
+#define I2C_CR1_NOSTRETCH 0x00000080U /*!<Clock Stretching Disable (Slave mode) */
+#define I2C_CR1_START 0x00000100U /*!<Start Generation */
+#define I2C_CR1_STOP 0x00000200U /*!<Stop Generation */
+#define I2C_CR1_ACK 0x00000400U /*!<Acknowledge Enable */
+#define I2C_CR1_POS 0x00000800U /*!<Acknowledge/PEC Position (for data reception) */
+#define I2C_CR1_PEC 0x00001000U /*!<Packet Error Checking */
+#define I2C_CR1_ALERT 0x00002000U /*!<SMBus Alert */
+#define I2C_CR1_SWRST 0x00008000U /*!<Software Reset */
+
+/******************* Bit definition for I2C_CR2 register ********************/
+#define I2C_CR2_FREQ 0x0000003FU /*!<FREQ[5:0] bits (Peripheral Clock Frequency) */
+#define I2C_CR2_FREQ_0 0x00000001U /*!<Bit 0 */
+#define I2C_CR2_FREQ_1 0x00000002U /*!<Bit 1 */
+#define I2C_CR2_FREQ_2 0x00000004U /*!<Bit 2 */
+#define I2C_CR2_FREQ_3 0x00000008U /*!<Bit 3 */
+#define I2C_CR2_FREQ_4 0x00000010U /*!<Bit 4 */
+#define I2C_CR2_FREQ_5 0x00000020U /*!<Bit 5 */
+
+#define I2C_CR2_ITERREN 0x00000100U /*!<Error Interrupt Enable */
+#define I2C_CR2_ITEVTEN 0x00000200U /*!<Event Interrupt Enable */
+#define I2C_CR2_ITBUFEN 0x00000400U /*!<Buffer Interrupt Enable */
+#define I2C_CR2_DMAEN 0x00000800U /*!<DMA Requests Enable */
+#define I2C_CR2_LAST 0x00001000U /*!<DMA Last Transfer */
+
+/******************* Bit definition for I2C_OAR1 register *******************/
+#define I2C_OAR1_ADD1_7 0x000000FEU /*!<Interface Address */
+#define I2C_OAR1_ADD8_9 0x00000300U /*!<Interface Address */
+
+#define I2C_OAR1_ADD0 0x00000001U /*!<Bit 0 */
+#define I2C_OAR1_ADD1 0x00000002U /*!<Bit 1 */
+#define I2C_OAR1_ADD2 0x00000004U /*!<Bit 2 */
+#define I2C_OAR1_ADD3 0x00000008U /*!<Bit 3 */
+#define I2C_OAR1_ADD4 0x00000010U /*!<Bit 4 */
+#define I2C_OAR1_ADD5 0x00000020U /*!<Bit 5 */
+#define I2C_OAR1_ADD6 0x00000040U /*!<Bit 6 */
+#define I2C_OAR1_ADD7 0x00000080U /*!<Bit 7 */
+#define I2C_OAR1_ADD8 0x00000100U /*!<Bit 8 */
+#define I2C_OAR1_ADD9 0x00000200U /*!<Bit 9 */
+
+#define I2C_OAR1_ADDMODE 0x00008000U /*!<Addressing Mode (Slave mode) */
+
+/******************* Bit definition for I2C_OAR2 register *******************/
+#define I2C_OAR2_ENDUAL 0x00000001U /*!<Dual addressing mode enable */
+#define I2C_OAR2_ADD2 0x000000FEU /*!<Interface address */
+
+/******************** Bit definition for I2C_DR register ********************/
+#define I2C_DR_DR 0x000000FFU /*!<8-bit Data Register */
+
+/******************* Bit definition for I2C_SR1 register ********************/
+#define I2C_SR1_SB 0x00000001U /*!<Start Bit (Master mode) */
+#define I2C_SR1_ADDR 0x00000002U /*!<Address sent (master mode)/matched (slave mode) */
+#define I2C_SR1_BTF 0x00000004U /*!<Byte Transfer Finished */
+#define I2C_SR1_ADD10 0x00000008U /*!<10-bit header sent (Master mode) */
+#define I2C_SR1_STOPF 0x00000010U /*!<Stop detection (Slave mode) */
+#define I2C_SR1_RXNE 0x00000040U /*!<Data Register not Empty (receivers) */
+#define I2C_SR1_TXE 0x00000080U /*!<Data Register Empty (transmitters) */
+#define I2C_SR1_BERR 0x00000100U /*!<Bus Error */
+#define I2C_SR1_ARLO 0x00000200U /*!<Arbitration Lost (master mode) */
+#define I2C_SR1_AF 0x00000400U /*!<Acknowledge Failure */
+#define I2C_SR1_OVR 0x00000800U /*!<Overrun/Underrun */
+#define I2C_SR1_PECERR 0x00001000U /*!<PEC Error in reception */
+#define I2C_SR1_TIMEOUT 0x00004000U /*!<Timeout or Tlow Error */
+#define I2C_SR1_SMBALERT 0x00008000U /*!<SMBus Alert */
+
+/******************* Bit definition for I2C_SR2 register ********************/
+#define I2C_SR2_MSL 0x00000001U /*!<Master/Slave */
+#define I2C_SR2_BUSY 0x00000002U /*!<Bus Busy */
+#define I2C_SR2_TRA 0x00000004U /*!<Transmitter/Receiver */
+#define I2C_SR2_GENCALL 0x00000010U /*!<General Call Address (Slave mode) */
+#define I2C_SR2_SMBDEFAULT 0x00000020U /*!<SMBus Device Default Address (Slave mode) */
+#define I2C_SR2_SMBHOST 0x00000040U /*!<SMBus Host Header (Slave mode) */
+#define I2C_SR2_DUALF 0x00000080U /*!<Dual Flag (Slave mode) */
+#define I2C_SR2_PEC 0x0000FF00U /*!<Packet Error Checking Register */
+
+/******************* Bit definition for I2C_CCR register ********************/
+#define I2C_CCR_CCR 0x00000FFFU /*!<Clock Control Register in Fast/Standard mode (Master mode) */
+#define I2C_CCR_DUTY 0x00004000U /*!<Fast Mode Duty Cycle */
+#define I2C_CCR_FS 0x00008000U /*!<I2C Master Mode Selection */
+
+/****************** Bit definition for I2C_TRISE register *******************/
+#define I2C_TRISE_TRISE 0x0000003FU /*!<Maximum Rise Time in Fast/Standard mode (Master mode) */
+
+/****************** Bit definition for I2C_FLTR register *******************/
+#define I2C_FLTR_DNF 0x0000000FU /*!<Digital Noise Filter */
+#define I2C_FLTR_ANOFF 0x00000010U /*!<Analog Noise Filter OFF */
+
+/******************************************************************************/
+/* */
+/* Fast Mode Plus Inter-integrated Circuit Interface (I2C) */
+/* */
+/******************************************************************************/
+/******************* Bit definition for I2C_CR1 register *******************/
+#define FMPI2C_CR1_PE 0x00000001U /*!< Peripheral enable */
+#define FMPI2C_CR1_TXIE 0x00000002U /*!< TX interrupt enable */
+#define FMPI2C_CR1_RXIE 0x00000004U /*!< RX interrupt enable */
+#define FMPI2C_CR1_ADDRIE 0x00000008U /*!< Address match interrupt enable */
+#define FMPI2C_CR1_NACKIE 0x00000010U /*!< NACK received interrupt enable */
+#define FMPI2C_CR1_STOPIE 0x00000020U /*!< STOP detection interrupt enable */
+#define FMPI2C_CR1_TCIE 0x00000040U /*!< Transfer complete interrupt enable */
+#define FMPI2C_CR1_ERRIE 0x00000080U /*!< Errors interrupt enable */
+#define FMPI2C_CR1_DFN 0x00000F00U /*!< Digital noise filter */
+#define FMPI2C_CR1_ANFOFF 0x00001000U /*!< Analog noise filter OFF */
+#define FMPI2C_CR1_TXDMAEN 0x00004000U /*!< DMA transmission requests enable */
+#define FMPI2C_CR1_RXDMAEN 0x00008000U /*!< DMA reception requests enable */
+#define FMPI2C_CR1_SBC 0x00010000U /*!< Slave byte control */
+#define FMPI2C_CR1_NOSTRETCH 0x00020000U /*!< Clock stretching disable */
+#define FMPI2C_CR1_GCEN 0x00080000U /*!< General call enable */
+#define FMPI2C_CR1_SMBHEN 0x00100000U /*!< SMBus host address enable */
+#define FMPI2C_CR1_SMBDEN 0x00200000U /*!< SMBus device default address enable */
+#define FMPI2C_CR1_ALERTEN 0x00400000U /*!< SMBus alert enable */
+#define FMPI2C_CR1_PECEN 0x00800000U /*!< PEC enable */
+
+/****************** Bit definition for I2C_CR2 register ********************/
+#define FMPI2C_CR2_SADD 0x000003FFU /*!< Slave address (master mode) */
+#define FMPI2C_CR2_RD_WRN 0x00000400U /*!< Transfer direction (master mode) */
+#define FMPI2C_CR2_ADD10 0x00000800U /*!< 10-bit addressing mode (master mode) */
+#define FMPI2C_CR2_HEAD10R 0x00001000U /*!< 10-bit address header only read direction (master mode) */
+#define FMPI2C_CR2_START 0x00002000U /*!< START generation */
+#define FMPI2C_CR2_STOP 0x00004000U /*!< STOP generation (master mode) */
+#define FMPI2C_CR2_NACK 0x00008000U /*!< NACK generation (slave mode) */
+#define FMPI2C_CR2_NBYTES 0x00FF0000U /*!< Number of bytes */
+#define FMPI2C_CR2_RELOAD 0x01000000U /*!< NBYTES reload mode */
+#define FMPI2C_CR2_AUTOEND 0x02000000U /*!< Automatic end mode (master mode) */
+#define FMPI2C_CR2_PECBYTE 0x04000000U /*!< Packet error checking byte */
+
+/******************* Bit definition for I2C_OAR1 register ******************/
+#define FMPI2C_OAR1_OA1 0x000003FFU /*!< Interface own address 1 */
+#define FMPI2C_OAR1_OA1MODE 0x00000400U /*!< Own address 1 10-bit mode */
+#define FMPI2C_OAR1_OA1EN 0x00008000U /*!< Own address 1 enable */
+
+/******************* Bit definition for I2C_OAR2 register ******************/
+#define FMPI2C_OAR2_OA2 0x000000FEU /*!< Interface own address 2 */
+#define FMPI2C_OAR2_OA2MSK 0x00000700U /*!< Own address 2 masks */
+#define FMPI2C_OAR2_OA2EN 0x00008000U /*!< Own address 2 enable */
+
+/******************* Bit definition for I2C_TIMINGR register *******************/
+#define FMPI2C_TIMINGR_SCLL 0x000000FFU /*!< SCL low period (master mode) */
+#define FMPI2C_TIMINGR_SCLH 0x0000FF00U /*!< SCL high period (master mode) */
+#define FMPI2C_TIMINGR_SDADEL 0x000F0000U /*!< Data hold time */
+#define FMPI2C_TIMINGR_SCLDEL 0x00F00000U /*!< Data setup time */
+#define FMPI2C_TIMINGR_PRESC 0xF0000000U /*!< Timings prescaler */
+
+/******************* Bit definition for I2C_TIMEOUTR register *******************/
+#define FMPI2C_TIMEOUTR_TIMEOUTA 0x00000FFFU /*!< Bus timeout A */
+#define FMPI2C_TIMEOUTR_TIDLE 0x00001000U /*!< Idle clock timeout detection */
+#define FMPI2C_TIMEOUTR_TIMOUTEN 0x00008000U /*!< Clock timeout enable */
+#define FMPI2C_TIMEOUTR_TIMEOUTB 0x0FFF0000U /*!< Bus timeout B */
+#define FMPI2C_TIMEOUTR_TEXTEN 0x80000000U /*!< Extended clock timeout enable */
+
+/****************** Bit definition for I2C_ISR register *********************/
+#define FMPI2C_ISR_TXE 0x00000001U /*!< Transmit data register empty */
+#define FMPI2C_ISR_TXIS 0x00000002U /*!< Transmit interrupt status */
+#define FMPI2C_ISR_RXNE 0x00000004U /*!< Receive data register not empty */
+#define FMPI2C_ISR_ADDR 0x00000008U /*!< Address matched (slave mode) */
+#define FMPI2C_ISR_NACKF 0x00000010U /*!< NACK received flag */
+#define FMPI2C_ISR_STOPF 0x00000020U /*!< STOP detection flag */
+#define FMPI2C_ISR_TC 0x00000040U /*!< Transfer complete (master mode) */
+#define FMPI2C_ISR_TCR 0x00000080U /*!< Transfer complete reload */
+#define FMPI2C_ISR_BERR 0x00000100U /*!< Bus error */
+#define FMPI2C_ISR_ARLO 0x00000200U /*!< Arbitration lost */
+#define FMPI2C_ISR_OVR 0x00000400U /*!< Overrun/Underrun */
+#define FMPI2C_ISR_PECERR 0x00000800U /*!< PEC error in reception */
+#define FMPI2C_ISR_TIMEOUT 0x00001000U /*!< Timeout or Tlow detection flag */
+#define FMPI2C_ISR_ALERT 0x00002000U /*!< SMBus alert */
+#define FMPI2C_ISR_BUSY 0x00008000U /*!< Bus busy */
+#define FMPI2C_ISR_DIR 0x00010000U /*!< Transfer direction (slave mode) */
+#define FMPI2C_ISR_ADDCODE 0x00FE0000U /*!< Address match code (slave mode) */
+
+/****************** Bit definition for I2C_ICR register *********************/
+#define FMPI2C_ICR_ADDRCF 0x00000008U /*!< Address matched clear flag */
+#define FMPI2C_ICR_NACKCF 0x00000010U /*!< NACK clear flag */
+#define FMPI2C_ICR_STOPCF 0x00000020U /*!< STOP detection clear flag */
+#define FMPI2C_ICR_BERRCF 0x00000100U /*!< Bus error clear flag */
+#define FMPI2C_ICR_ARLOCF 0x00000200U /*!< Arbitration lost clear flag */
+#define FMPI2C_ICR_OVRCF 0x00000400U /*!< Overrun/Underrun clear flag */
+#define FMPI2C_ICR_PECCF 0x00000800U /*!< PAC error clear flag */
+#define FMPI2C_ICR_TIMOUTCF 0x00001000U /*!< Timeout clear flag */
+#define FMPI2C_ICR_ALERTCF 0x00002000U /*!< Alert clear flag */
+
+/****************** Bit definition for I2C_PECR register *********************/
+#define FMPI2C_PECR_PEC 0x000000FFU /*!< PEC register */
+
+/****************** Bit definition for I2C_RXDR register *********************/
+#define FMPI2C_RXDR_RXDATA 0x000000FFU /*!< 8-bit receive data */
+
+/****************** Bit definition for I2C_TXDR register *********************/
+#define FMPI2C_TXDR_TXDATA 0x000000FFU /*!< 8-bit transmit data */
+
+/******************************************************************************/
+/* */
+/* Independent WATCHDOG */
+/* */
+/******************************************************************************/
+/******************* Bit definition for IWDG_KR register ********************/
+#define IWDG_KR_KEY 0xFFFFU /*!<Key value (write only, read 0000h) */
+
+/******************* Bit definition for IWDG_PR register ********************/
+#define IWDG_PR_PR 0x07U /*!<PR[2:0] (Prescaler divider) */
+#define IWDG_PR_PR_0 0x01U /*!<Bit 0 */
+#define IWDG_PR_PR_1 0x02U /*!<Bit 1 */
+#define IWDG_PR_PR_2 0x04U /*!<Bit 2 */
+
+/******************* Bit definition for IWDG_RLR register *******************/
+#define IWDG_RLR_RL 0x0FFFU /*!<Watchdog counter reload value */
+
+/******************* Bit definition for IWDG_SR register ********************/
+#define IWDG_SR_PVU 0x01U /*!<Watchdog prescaler value update */
+#define IWDG_SR_RVU 0x02U /*!<Watchdog counter reload value update */
+
+
+/******************************************************************************/
+/* */
+/* Power Control */
+/* */
+/******************************************************************************/
+/******************** Bit definition for PWR_CR register ********************/
+#define PWR_CR_LPDS 0x00000001U /*!< Low-Power Deepsleep */
+#define PWR_CR_PDDS 0x00000002U /*!< Power Down Deepsleep */
+#define PWR_CR_CWUF 0x00000004U /*!< Clear Wakeup Flag */
+#define PWR_CR_CSBF 0x00000008U /*!< Clear Standby Flag */
+#define PWR_CR_PVDE 0x00000010U /*!< Power Voltage Detector Enable */
+
+#define PWR_CR_PLS 0x000000E0U /*!< PLS[2:0] bits (PVD Level Selection) */
+#define PWR_CR_PLS_0 0x00000020U /*!< Bit 0 */
+#define PWR_CR_PLS_1 0x00000040U /*!< Bit 1 */
+#define PWR_CR_PLS_2 0x00000080U /*!< Bit 2 */
+
+/*!< PVD level configuration */
+#define PWR_CR_PLS_LEV0 0x00000000U /*!< PVD level 0 */
+#define PWR_CR_PLS_LEV1 0x00000020U /*!< PVD level 1 */
+#define PWR_CR_PLS_LEV2 0x00000040U /*!< PVD level 2 */
+#define PWR_CR_PLS_LEV3 0x00000060U /*!< PVD level 3 */
+#define PWR_CR_PLS_LEV4 0x00000080U /*!< PVD level 4 */
+#define PWR_CR_PLS_LEV5 0x000000A0U /*!< PVD level 5 */
+#define PWR_CR_PLS_LEV6 0x000000C0U /*!< PVD level 6 */
+#define PWR_CR_PLS_LEV7 0x000000E0U /*!< PVD level 7 */
+
+#define PWR_CR_DBP 0x00000100U /*!< Disable Backup Domain write protection */
+#define PWR_CR_FPDS 0x00000200U /*!< Flash power down in Stop mode */
+#define PWR_CR_LPLVDS 0x00000400U /*!< Low Power Regulator Low Voltage in Deep Sleep mode */
+#define PWR_CR_MRLVDS 0x00000800U /*!< Main Regulator Low Voltage in Deep Sleep mode */
+#define PWR_CR_ADCDC1 0x00002000U /*!< Refer to AN4073 on how to use this bit */
+
+#define PWR_CR_VOS 0x0000C000U /*!< VOS[1:0] bits (Regulator voltage scaling output selection) */
+#define PWR_CR_VOS_0 0x00004000U /*!< Bit 0 */
+#define PWR_CR_VOS_1 0x00008000U /*!< Bit 1 */
+
+#define PWR_CR_FMSSR 0x00100000U /*!< Flash Memory Sleep System Run */
+#define PWR_CR_FISSR 0x00200000U /*!< Flash Interface Stop while System Run */
+
+/******************* Bit definition for PWR_CSR register ********************/
+#define PWR_CSR_WUF 0x00000001U /*!< Wakeup Flag */
+#define PWR_CSR_SBF 0x00000002U /*!< Standby Flag */
+#define PWR_CSR_PVDO 0x00000004U /*!< PVD Output */
+#define PWR_CSR_BRR 0x00000008U /*!< Backup regulator ready */
+#define PWR_CSR_EWUP 0x00000100U /*!< Enable WKUP pin */
+#define PWR_CSR_BRE 0x00000200U /*!< Backup regulator enable */
+#define PWR_CSR_VOSRDY 0x00004000U /*!< Regulator voltage scaling output selection ready */
+/******************************************************************************/
+/* */
+/* QUADSPI */
+/* */
+/******************************************************************************/
+/***************** Bit definition for QUADSPI_CR register *******************/
+#define QUADSPI_CR_EN 0x00000001U /*!< Enable */
+#define QUADSPI_CR_ABORT 0x00000002U /*!< Abort request */
+#define QUADSPI_CR_DMAEN 0x00000004U /*!< DMA Enable */
+#define QUADSPI_CR_TCEN 0x00000008U /*!< Timeout Counter Enable */
+#define QUADSPI_CR_SSHIFT 0x00000010U /*!< SSHIFT Sample Shift */
+#define QUADSPI_CR_DFM 0x00000040U /*!< Dual Flash Mode */
+#define QUADSPI_CR_FSEL 0x00000080U /*!< Flash Select */
+#define QUADSPI_CR_FTHRES 0x00001F00U /*!< FTHRES[3:0] FIFO Level */
+#define QUADSPI_CR_FTHRES_0 0x00000100U /*!< Bit 0 */
+#define QUADSPI_CR_FTHRES_1 0x00000200U /*!< Bit 1 */
+#define QUADSPI_CR_FTHRES_2 0x00000400U /*!< Bit 2 */
+#define QUADSPI_CR_FTHRES_3 0x00000800U /*!< Bit 3 */
+#define QUADSPI_CR_FTHRES_4 0x00001000U /*!< Bit 4 */
+#define QUADSPI_CR_TEIE 0x00010000U /*!< Transfer Error Interrupt Enable */
+#define QUADSPI_CR_TCIE 0x00020000U /*!< Transfer Complete Interrupt Enable */
+#define QUADSPI_CR_FTIE 0x00040000U /*!< FIFO Threshold Interrupt Enable */
+#define QUADSPI_CR_SMIE 0x00080000U /*!< Status Match Interrupt Enable */
+#define QUADSPI_CR_TOIE 0x00100000U /*!< TimeOut Interrupt Enable */
+#define QUADSPI_CR_APMS 0x00400000U /*!< Bit 1 */
+#define QUADSPI_CR_PMM 0x00800000U /*!< Polling Match Mode */
+#define QUADSPI_CR_PRESCALER 0xFF000000U /*!< PRESCALER[7:0] Clock prescaler */
+#define QUADSPI_CR_PRESCALER_0 0x01000000U /*!< Bit 0 */
+#define QUADSPI_CR_PRESCALER_1 0x02000000U /*!< Bit 1 */
+#define QUADSPI_CR_PRESCALER_2 0x04000000U /*!< Bit 2 */
+#define QUADSPI_CR_PRESCALER_3 0x08000000U /*!< Bit 3 */
+#define QUADSPI_CR_PRESCALER_4 0x10000000U /*!< Bit 4 */
+#define QUADSPI_CR_PRESCALER_5 0x20000000U /*!< Bit 5 */
+#define QUADSPI_CR_PRESCALER_6 0x40000000U /*!< Bit 6 */
+#define QUADSPI_CR_PRESCALER_7 0x80000000U /*!< Bit 7 */
+
+/***************** Bit definition for QUADSPI_DCR register ******************/
+#define QUADSPI_DCR_CKMODE 0x00000001U /*!< Mode 0 / Mode 3 */
+#define QUADSPI_DCR_CSHT 0x00000700U /*!< CSHT[2:0]: ChipSelect High Time */
+#define QUADSPI_DCR_CSHT_0 0x00000100U /*!< Bit 0 */
+#define QUADSPI_DCR_CSHT_1 0x00000200U /*!< Bit 1 */
+#define QUADSPI_DCR_CSHT_2 0x00000400U /*!< Bit 2 */
+#define QUADSPI_DCR_FSIZE 0x001F0000U /*!< FSIZE[4:0]: Flash Size */
+#define QUADSPI_DCR_FSIZE_0 0x00010000U /*!< Bit 0 */
+#define QUADSPI_DCR_FSIZE_1 0x00020000U /*!< Bit 1 */
+#define QUADSPI_DCR_FSIZE_2 0x00040000U /*!< Bit 2 */
+#define QUADSPI_DCR_FSIZE_3 0x00080000U /*!< Bit 3 */
+#define QUADSPI_DCR_FSIZE_4 0x00100000U /*!< Bit 4 */
+
+/****************** Bit definition for QUADSPI_SR register *******************/
+#define QUADSPI_SR_TEF 0x00000001U /*!< Transfer Error Flag */
+#define QUADSPI_SR_TCF 0x00000002U /*!< Transfer Complete Flag */
+#define QUADSPI_SR_FTF 0x00000004U /*!< FIFO Threshlod Flag */
+#define QUADSPI_SR_SMF 0x00000008U /*!< Status Match Flag */
+#define QUADSPI_SR_TOF 0x00000010U /*!< Timeout Flag */
+#define QUADSPI_SR_BUSY 0x00000020U /*!< Busy */
+#define QUADSPI_SR_FLEVEL 0x00003F00U /*!< FIFO Threshlod Flag */
+#define QUADSPI_SR_FLEVEL_0 0x00000100U /*!< Bit 0 */
+#define QUADSPI_SR_FLEVEL_1 0x00000200U /*!< Bit 1 */
+#define QUADSPI_SR_FLEVEL_2 0x00000400U /*!< Bit 2 */
+#define QUADSPI_SR_FLEVEL_3 0x00000800U /*!< Bit 3 */
+#define QUADSPI_SR_FLEVEL_4 0x00001000U /*!< Bit 4 */
+#define QUADSPI_SR_FLEVEL_5 0x00002000U /*!< Bit 5 */
+
+/****************** Bit definition for QUADSPI_FCR register ******************/
+#define QUADSPI_FCR_CTEF 0x00000001U /*!< Clear Transfer Error Flag */
+#define QUADSPI_FCR_CTCF 0x00000002U /*!< Clear Transfer Complete Flag */
+#define QUADSPI_FCR_CSMF 0x00000008U /*!< Clear Status Match Flag */
+#define QUADSPI_FCR_CTOF 0x00000010U /*!< Clear Timeout Flag */
+
+/****************** Bit definition for QUADSPI_DLR register ******************/
+#define QUADSPI_DLR_DL 0xFFFFFFFFU /*!< DL[31:0]: Data Length */
+
+/****************** Bit definition for QUADSPI_CCR register ******************/
+#define QUADSPI_CCR_INSTRUCTION 0x000000FFU /*!< INSTRUCTION[7:0]: Instruction */
+#define QUADSPI_CCR_INSTRUCTION_0 0x00000001U /*!< Bit 0 */
+#define QUADSPI_CCR_INSTRUCTION_1 0x00000002U /*!< Bit 1 */
+#define QUADSPI_CCR_INSTRUCTION_2 0x00000004U /*!< Bit 2 */
+#define QUADSPI_CCR_INSTRUCTION_3 0x00000008U /*!< Bit 3 */
+#define QUADSPI_CCR_INSTRUCTION_4 0x00000010U /*!< Bit 4 */
+#define QUADSPI_CCR_INSTRUCTION_5 0x00000020U /*!< Bit 5 */
+#define QUADSPI_CCR_INSTRUCTION_6 0x00000040U /*!< Bit 6 */
+#define QUADSPI_CCR_INSTRUCTION_7 0x00000080U /*!< Bit 7 */
+#define QUADSPI_CCR_IMODE 0x00000300U /*!< IMODE[1:0]: Instruction Mode */
+#define QUADSPI_CCR_IMODE_0 0x00000100U /*!< Bit 0 */
+#define QUADSPI_CCR_IMODE_1 0x00000200U /*!< Bit 1 */
+#define QUADSPI_CCR_ADMODE 0x00000C00U /*!< ADMODE[1:0]: Address Mode */
+#define QUADSPI_CCR_ADMODE_0 0x00000400U /*!< Bit 0 */
+#define QUADSPI_CCR_ADMODE_1 0x00000800U /*!< Bit 1 */
+#define QUADSPI_CCR_ADSIZE 0x00003000U /*!< ADSIZE[1:0]: Address Size */
+#define QUADSPI_CCR_ADSIZE_0 0x00001000U /*!< Bit 0 */
+#define QUADSPI_CCR_ADSIZE_1 0x00002000U /*!< Bit 1 */
+#define QUADSPI_CCR_ABMODE 0x0000C000U /*!< ABMODE[1:0]: Alternate Bytes Mode */
+#define QUADSPI_CCR_ABMODE_0 0x00004000U /*!< Bit 0 */
+#define QUADSPI_CCR_ABMODE_1 0x00008000U /*!< Bit 1 */
+#define QUADSPI_CCR_ABSIZE 0x00030000U /*!< ABSIZE[1:0]: Instruction Mode */
+#define QUADSPI_CCR_ABSIZE_0 0x00010000U /*!< Bit 0 */
+#define QUADSPI_CCR_ABSIZE_1 0x00020000U /*!< Bit 1 */
+#define QUADSPI_CCR_DCYC 0x007C0000U /*!< DCYC[4:0]: Dummy Cycles */
+#define QUADSPI_CCR_DCYC_0 0x00040000U /*!< Bit 0 */
+#define QUADSPI_CCR_DCYC_1 0x00080000U /*!< Bit 1 */
+#define QUADSPI_CCR_DCYC_2 0x00100000U /*!< Bit 2 */
+#define QUADSPI_CCR_DCYC_3 0x00200000U /*!< Bit 3 */
+#define QUADSPI_CCR_DCYC_4 0x00400000U /*!< Bit 4 */
+#define QUADSPI_CCR_DMODE 0x03000000U /*!< DMODE[1:0]: Data Mode */
+#define QUADSPI_CCR_DMODE_0 0x01000000U /*!< Bit 0 */
+#define QUADSPI_CCR_DMODE_1 0x02000000U /*!< Bit 1 */
+#define QUADSPI_CCR_FMODE 0x0C000000U /*!< FMODE[1:0]: Functional Mode */
+#define QUADSPI_CCR_FMODE_0 0x04000000U /*!< Bit 0 */
+#define QUADSPI_CCR_FMODE_1 0x08000000U /*!< Bit 1 */
+#define QUADSPI_CCR_SIOO 0x10000000U /*!< SIOO: Send Instruction Only Once Mode */
+#define QUADSPI_CCR_DHHC 0x40000000U /*!< DHHC: Delay Half Hclk Cycle */
+#define QUADSPI_CCR_DDRM 0x80000000U /*!< DDRM: Double Data Rate Mode */
+/****************** Bit definition for QUADSPI_AR register *******************/
+#define QUADSPI_AR_ADDRESS 0xFFFFFFFFU /*!< ADDRESS[31:0]: Address */
+
+/****************** Bit definition for QUADSPI_ABR register ******************/
+#define QUADSPI_ABR_ALTERNATE 0xFFFFFFFFU /*!< ALTERNATE[31:0]: Alternate Bytes */
+
+/****************** Bit definition for QUADSPI_DR register *******************/
+#define QUADSPI_DR_DATA 0xFFFFFFFFU /*!< DATA[31:0]: Data */
+
+/****************** Bit definition for QUADSPI_PSMKR register ****************/
+#define QUADSPI_PSMKR_MASK 0xFFFFFFFFU /*!< MASK[31:0]: Status Mask */
+
+/****************** Bit definition for QUADSPI_PSMAR register ****************/
+#define QUADSPI_PSMAR_MATCH 0xFFFFFFFFU /*!< MATCH[31:0]: Status Match */
+
+/****************** Bit definition for QUADSPI_PIR register *****************/
+#define QUADSPI_PIR_INTERVAL 0x0000FFFFU /*!< INTERVAL[15:0]: Polling Interval */
+
+/****************** Bit definition for QUADSPI_LPTR register *****************/
+#define QUADSPI_LPTR_TIMEOUT 0x0000FFFFU /*!< TIMEOUT[15:0]: Timeout period */
+
+/******************************************************************************/
+/* */
+/* Reset and Clock Control */
+/* */
+/******************************************************************************/
+/******************** Bit definition for RCC_CR register ********************/
+#define RCC_CR_HSION 0x00000001U
+#define RCC_CR_HSIRDY 0x00000002U
+
+#define RCC_CR_HSITRIM 0x000000F8U
+#define RCC_CR_HSITRIM_0 0x00000008U/*!<Bit 0 */
+#define RCC_CR_HSITRIM_1 0x00000010U/*!<Bit 1 */
+#define RCC_CR_HSITRIM_2 0x00000020U/*!<Bit 2 */
+#define RCC_CR_HSITRIM_3 0x00000040U/*!<Bit 3 */
+#define RCC_CR_HSITRIM_4 0x00000080U/*!<Bit 4 */
+
+#define RCC_CR_HSICAL 0x0000FF00U
+#define RCC_CR_HSICAL_0 0x00000100U/*!<Bit 0 */
+#define RCC_CR_HSICAL_1 0x00000200U/*!<Bit 1 */
+#define RCC_CR_HSICAL_2 0x00000400U/*!<Bit 2 */
+#define RCC_CR_HSICAL_3 0x00000800U/*!<Bit 3 */
+#define RCC_CR_HSICAL_4 0x00001000U/*!<Bit 4 */
+#define RCC_CR_HSICAL_5 0x00002000U/*!<Bit 5 */
+#define RCC_CR_HSICAL_6 0x00004000U/*!<Bit 6 */
+#define RCC_CR_HSICAL_7 0x00008000U/*!<Bit 7 */
+
+#define RCC_CR_HSEON 0x00010000U
+#define RCC_CR_HSERDY 0x00020000U
+#define RCC_CR_HSEBYP 0x00040000U
+#define RCC_CR_CSSON 0x00080000U
+#define RCC_CR_PLLON 0x01000000U
+#define RCC_CR_PLLRDY 0x02000000U
+#define RCC_CR_PLLI2SON 0x04000000U
+#define RCC_CR_PLLI2SRDY 0x08000000U
+
+/******************** Bit definition for RCC_PLLCFGR register ***************/
+#define RCC_PLLCFGR_PLLM 0x0000003FU
+#define RCC_PLLCFGR_PLLM_0 0x00000001U
+#define RCC_PLLCFGR_PLLM_1 0x00000002U
+#define RCC_PLLCFGR_PLLM_2 0x00000004U
+#define RCC_PLLCFGR_PLLM_3 0x00000008U
+#define RCC_PLLCFGR_PLLM_4 0x00000010U
+#define RCC_PLLCFGR_PLLM_5 0x00000020U
+
+#define RCC_PLLCFGR_PLLN 0x00007FC0U
+#define RCC_PLLCFGR_PLLN_0 0x00000040U
+#define RCC_PLLCFGR_PLLN_1 0x00000080U
+#define RCC_PLLCFGR_PLLN_2 0x00000100U
+#define RCC_PLLCFGR_PLLN_3 0x00000200U
+#define RCC_PLLCFGR_PLLN_4 0x00000400U
+#define RCC_PLLCFGR_PLLN_5 0x00000800U
+#define RCC_PLLCFGR_PLLN_6 0x00001000U
+#define RCC_PLLCFGR_PLLN_7 0x00002000U
+#define RCC_PLLCFGR_PLLN_8 0x00004000U
+
+#define RCC_PLLCFGR_PLLP 0x00030000U
+#define RCC_PLLCFGR_PLLP_0 0x00010000U
+#define RCC_PLLCFGR_PLLP_1 0x00020000U
+
+#define RCC_PLLCFGR_PLLSRC 0x00400000U
+#define RCC_PLLCFGR_PLLSRC_HSE 0x00400000U
+#define RCC_PLLCFGR_PLLSRC_HSI 0x00000000U
+
+#define RCC_PLLCFGR_PLLQ 0x0F000000U
+#define RCC_PLLCFGR_PLLQ_0 0x01000000U
+#define RCC_PLLCFGR_PLLQ_1 0x02000000U
+#define RCC_PLLCFGR_PLLQ_2 0x04000000U
+#define RCC_PLLCFGR_PLLQ_3 0x08000000U
+
+#define RCC_PLLCFGR_PLLR 0x70000000U
+#define RCC_PLLCFGR_PLLR_0 0x10000000U
+#define RCC_PLLCFGR_PLLR_1 0x20000000U
+#define RCC_PLLCFGR_PLLR_2 0x40000000U
+
+/******************** Bit definition for RCC_CFGR register ******************/
+/*!< SW configuration */
+#define RCC_CFGR_SW 0x00000003U /*!< SW[1:0] bits (System clock Switch) */
+#define RCC_CFGR_SW_0 0x00000001U /*!< Bit 0 */
+#define RCC_CFGR_SW_1 0x00000002U /*!< Bit 1 */
+
+#define RCC_CFGR_SW_HSI 0x00000000U /*!< HSI selected as system clock */
+#define RCC_CFGR_SW_HSE 0x00000001U /*!< HSE selected as system clock */
+#define RCC_CFGR_SW_PLL 0x00000002U /*!< PLL/PLLP selected as system clock */
+#define RCC_CFGR_SW_PLLR 0x00000003U /*!< PLL/PLLR selected as system clock */
+
+/*!< SWS configuration */
+#define RCC_CFGR_SWS 0x0000000CU /*!< SWS[1:0] bits (System Clock Switch Status) */
+#define RCC_CFGR_SWS_0 0x00000004U /*!< Bit 0 */
+#define RCC_CFGR_SWS_1 0x00000008U /*!< Bit 1 */
+
+#define RCC_CFGR_SWS_HSI 0x00000000U /*!< HSI oscillator used as system clock */
+#define RCC_CFGR_SWS_HSE 0x00000004U /*!< HSE oscillator used as system clock */
+#define RCC_CFGR_SWS_PLL 0x00000008U /*!< PLL/PLLP used as system clock */
+#define RCC_CFGR_SWS_PLLR 0x0000000CU /*!< PLL/PLLR used as system clock */
+
+/*!< HPRE configuration */
+#define RCC_CFGR_HPRE 0x000000F0U /*!< HPRE[3:0] bits (AHB prescaler) */
+#define RCC_CFGR_HPRE_0 0x00000010U /*!< Bit 0 */
+#define RCC_CFGR_HPRE_1 0x00000020U /*!< Bit 1 */
+#define RCC_CFGR_HPRE_2 0x00000040U /*!< Bit 2 */
+#define RCC_CFGR_HPRE_3 0x00000080U /*!< Bit 3 */
+
+#define RCC_CFGR_HPRE_DIV1 0x00000000U /*!< SYSCLK not divided */
+#define RCC_CFGR_HPRE_DIV2 0x00000080U /*!< SYSCLK divided by 2 */
+#define RCC_CFGR_HPRE_DIV4 0x00000090U /*!< SYSCLK divided by 4 */
+#define RCC_CFGR_HPRE_DIV8 0x000000A0U /*!< SYSCLK divided by 8 */
+#define RCC_CFGR_HPRE_DIV16 0x000000B0U /*!< SYSCLK divided by 16 */
+#define RCC_CFGR_HPRE_DIV64 0x000000C0U /*!< SYSCLK divided by 64 */
+#define RCC_CFGR_HPRE_DIV128 0x000000D0U /*!< SYSCLK divided by 128 */
+#define RCC_CFGR_HPRE_DIV256 0x000000E0U /*!< SYSCLK divided by 256 */
+#define RCC_CFGR_HPRE_DIV512 0x000000F0U /*!< SYSCLK divided by 512 */
+
+/*!< PPRE1 configuration */
+#define RCC_CFGR_PPRE1 0x00001C00U /*!< PRE1[2:0] bits (APB1 prescaler) */
+#define RCC_CFGR_PPRE1_0 0x00000400U /*!< Bit 0 */
+#define RCC_CFGR_PPRE1_1 0x00000800U /*!< Bit 1 */
+#define RCC_CFGR_PPRE1_2 0x00001000U /*!< Bit 2 */
+
+#define RCC_CFGR_PPRE1_DIV1 0x00000000U /*!< HCLK not divided */
+#define RCC_CFGR_PPRE1_DIV2 0x00001000U /*!< HCLK divided by 2 */
+#define RCC_CFGR_PPRE1_DIV4 0x00001400U /*!< HCLK divided by 4 */
+#define RCC_CFGR_PPRE1_DIV8 0x00001800U /*!< HCLK divided by 8 */
+#define RCC_CFGR_PPRE1_DIV16 0x00001C00U /*!< HCLK divided by 16 */
+
+/*!< PPRE2 configuration */
+#define RCC_CFGR_PPRE2 0x0000E000U /*!< PRE2[2:0] bits (APB2 prescaler) */
+#define RCC_CFGR_PPRE2_0 0x00002000U /*!< Bit 0 */
+#define RCC_CFGR_PPRE2_1 0x00004000U /*!< Bit 1 */
+#define RCC_CFGR_PPRE2_2 0x00008000U /*!< Bit 2 */
+
+#define RCC_CFGR_PPRE2_DIV1 0x00000000U /*!< HCLK not divided */
+#define RCC_CFGR_PPRE2_DIV2 0x00008000U /*!< HCLK divided by 2 */
+#define RCC_CFGR_PPRE2_DIV4 0x0000A000U /*!< HCLK divided by 4 */
+#define RCC_CFGR_PPRE2_DIV8 0x0000C000U /*!< HCLK divided by 8 */
+#define RCC_CFGR_PPRE2_DIV16 0x0000E000U /*!< HCLK divided by 16 */
+
+/*!< RTCPRE configuration */
+#define RCC_CFGR_RTCPRE 0x001F0000U
+#define RCC_CFGR_RTCPRE_0 0x00010000U
+#define RCC_CFGR_RTCPRE_1 0x00020000U
+#define RCC_CFGR_RTCPRE_2 0x00040000U
+#define RCC_CFGR_RTCPRE_3 0x00080000U
+#define RCC_CFGR_RTCPRE_4 0x00100000U
+
+/*!< MCO1 configuration */
+#define RCC_CFGR_MCO1 0x00600000U
+#define RCC_CFGR_MCO1_0 0x00200000U
+#define RCC_CFGR_MCO1_1 0x00400000U
+
+#define RCC_CFGR_MCO1PRE 0x07000000U
+#define RCC_CFGR_MCO1PRE_0 0x01000000U
+#define RCC_CFGR_MCO1PRE_1 0x02000000U
+#define RCC_CFGR_MCO1PRE_2 0x04000000U
+
+#define RCC_CFGR_MCO2PRE 0x38000000U
+#define RCC_CFGR_MCO2PRE_0 0x08000000U
+#define RCC_CFGR_MCO2PRE_1 0x10000000U
+#define RCC_CFGR_MCO2PRE_2 0x20000000U
+
+#define RCC_CFGR_MCO2 0xC0000000U
+#define RCC_CFGR_MCO2_0 0x40000000U
+#define RCC_CFGR_MCO2_1 0x80000000U
+
+/******************** Bit definition for RCC_CIR register *******************/
+#define RCC_CIR_LSIRDYF 0x00000001U
+#define RCC_CIR_LSERDYF 0x00000002U
+#define RCC_CIR_HSIRDYF 0x00000004U
+#define RCC_CIR_HSERDYF 0x00000008U
+#define RCC_CIR_PLLRDYF 0x00000010U
+#define RCC_CIR_PLLI2SRDYF 0x00000020U
+
+#define RCC_CIR_CSSF 0x00000080U
+#define RCC_CIR_LSIRDYIE 0x00000100U
+#define RCC_CIR_LSERDYIE 0x00000200U
+#define RCC_CIR_HSIRDYIE 0x00000400U
+#define RCC_CIR_HSERDYIE 0x00000800U
+#define RCC_CIR_PLLRDYIE 0x00001000U
+#define RCC_CIR_PLLI2SRDYIE 0x00002000U
+
+#define RCC_CIR_LSIRDYC 0x00010000U
+#define RCC_CIR_LSERDYC 0x00020000U
+#define RCC_CIR_HSIRDYC 0x00040000U
+#define RCC_CIR_HSERDYC 0x00080000U
+#define RCC_CIR_PLLRDYC 0x00100000U
+#define RCC_CIR_PLLI2SRDYC 0x00200000U
+
+#define RCC_CIR_CSSC 0x00800000U
+
+/******************** Bit definition for RCC_AHB1RSTR register **************/
+#define RCC_AHB1RSTR_GPIOARST 0x00000001U
+#define RCC_AHB1RSTR_GPIOBRST 0x00000002U
+#define RCC_AHB1RSTR_GPIOCRST 0x00000004U
+#define RCC_AHB1RSTR_GPIODRST 0x00000008U
+#define RCC_AHB1RSTR_GPIOERST 0x00000010U
+#define RCC_AHB1RSTR_GPIOFRST 0x00000020U
+#define RCC_AHB1RSTR_GPIOGRST 0x00000040U
+#define RCC_AHB1RSTR_GPIOHRST 0x00000080U
+#define RCC_AHB1RSTR_CRCRST 0x00001000U
+#define RCC_AHB1RSTR_DMA1RST 0x00200000U
+#define RCC_AHB1RSTR_DMA2RST 0x00400000U
+
+/******************** Bit definition for RCC_AHB2RSTR register **************/
+#define RCC_AHB2RSTR_RNGRST 0x00000040U
+#define RCC_AHB2RSTR_OTGFSRST 0x00000080U
+
+/******************** Bit definition for RCC_AHB3RSTR register **************/
+#define RCC_AHB3RSTR_FSMCRST 0x00000001U
+#define RCC_AHB3RSTR_QSPIRST 0x00000002U
+
+/******************** Bit definition for RCC_APB1RSTR register **************/
+#define RCC_APB1RSTR_TIM2RST 0x00000001U
+#define RCC_APB1RSTR_TIM3RST 0x00000002U
+#define RCC_APB1RSTR_TIM4RST 0x00000004U
+#define RCC_APB1RSTR_TIM5RST 0x00000008U
+#define RCC_APB1RSTR_TIM6RST 0x00000010U
+#define RCC_APB1RSTR_TIM7RST 0x00000020U
+#define RCC_APB1RSTR_TIM12RST 0x00000040U
+#define RCC_APB1RSTR_TIM13RST 0x00000080U
+#define RCC_APB1RSTR_TIM14RST 0x00000100U
+#define RCC_APB1RSTR_WWDGRST 0x00000800U
+#define RCC_APB1RSTR_SPI2RST 0x00004000U
+#define RCC_APB1RSTR_SPI3RST 0x00008000U
+#define RCC_APB1RSTR_USART2RST 0x00020000U
+#define RCC_APB1RSTR_USART3RST 0x00040000U
+#define RCC_APB1RSTR_I2C1RST 0x00200000U
+#define RCC_APB1RSTR_I2C2RST 0x00400000U
+#define RCC_APB1RSTR_I2C3RST 0x00800000U
+#define RCC_APB1RSTR_FMPI2C1RST 0x01000000U
+#define RCC_APB1RSTR_CAN1RST 0x02000000U
+#define RCC_APB1RSTR_CAN2RST 0x04000000U
+#define RCC_APB1RSTR_PWRRST 0x10000000U
+
+/******************** Bit definition for RCC_APB2RSTR register **************/
+#define RCC_APB2RSTR_TIM1RST 0x00000001U
+#define RCC_APB2RSTR_TIM8RST 0x00000002U
+#define RCC_APB2RSTR_USART1RST 0x00000010U
+#define RCC_APB2RSTR_USART6RST 0x00000020U
+#define RCC_APB2RSTR_ADCRST 0x00000100U
+#define RCC_APB2RSTR_SDIORST 0x00000800U
+#define RCC_APB2RSTR_SPI1RST 0x00001000U
+#define RCC_APB2RSTR_SPI4RST 0x00002000U
+#define RCC_APB2RSTR_SYSCFGRST 0x00004000U
+#define RCC_APB2RSTR_TIM9RST 0x00010000U
+#define RCC_APB2RSTR_TIM10RST 0x00020000U
+#define RCC_APB2RSTR_TIM11RST 0x00040000U
+#define RCC_APB2RSTR_SPI5RST 0x00100000U
+#define RCC_APB2RSTR_DFSDM1RST 0x01000000U
+
+/******************** Bit definition for RCC_AHB1ENR register ***************/
+#define RCC_AHB1ENR_GPIOAEN 0x00000001U
+#define RCC_AHB1ENR_GPIOBEN 0x00000002U
+#define RCC_AHB1ENR_GPIOCEN 0x00000004U
+#define RCC_AHB1ENR_GPIODEN 0x00000008U
+#define RCC_AHB1ENR_GPIOEEN 0x00000010U
+#define RCC_AHB1ENR_GPIOFEN 0x00000020U
+#define RCC_AHB1ENR_GPIOGEN 0x00000040U
+#define RCC_AHB1ENR_GPIOHEN 0x00000080U
+#define RCC_AHB1ENR_CRCEN 0x00001000U
+#define RCC_AHB1ENR_DMA1EN 0x00200000U
+#define RCC_AHB1ENR_DMA2EN 0x00400000U
+
+/******************** Bit definition for RCC_AHB2ENR register ***************/
+#define RCC_AHB2ENR_RNGEN 0x00000040U
+#define RCC_AHB2ENR_OTGFSEN 0x00000080U
+
+/******************** Bit definition for RCC_AHB3ENR register ***************/
+#define RCC_AHB3ENR_FSMCEN 0x00000001U
+#define RCC_AHB3ENR_QSPIEN 0x00000002U
+
+/******************** Bit definition for RCC_APB1ENR register ***************/
+#define RCC_APB1ENR_TIM2EN 0x00000001U
+#define RCC_APB1ENR_TIM3EN 0x00000002U
+#define RCC_APB1ENR_TIM4EN 0x00000004U
+#define RCC_APB1ENR_TIM5EN 0x00000008U
+#define RCC_APB1ENR_TIM6EN 0x00000010U
+#define RCC_APB1ENR_TIM7EN 0x00000020U
+#define RCC_APB1ENR_TIM12EN 0x00000040U
+#define RCC_APB1ENR_TIM13EN 0x00000080U
+#define RCC_APB1ENR_TIM14EN 0x00000100U
+#define RCC_APB1ENR_RTCAPBEN 0x00000400U
+#define RCC_APB1ENR_WWDGEN 0x00000800U
+#define RCC_APB1ENR_SPI2EN 0x00004000U
+#define RCC_APB1ENR_SPI3EN 0x00008000U
+#define RCC_APB1ENR_USART2EN 0x00020000U
+#define RCC_APB1ENR_USART3EN 0x00040000U
+#define RCC_APB1ENR_I2C1EN 0x00200000U
+#define RCC_APB1ENR_I2C2EN 0x00400000U
+#define RCC_APB1ENR_I2C3EN 0x00800000U
+#define RCC_APB1ENR_FMPI2C1EN 0x01000000U
+#define RCC_APB1ENR_CAN1EN 0x02000000U
+#define RCC_APB1ENR_CAN2EN 0x04000000U
+#define RCC_APB1ENR_PWREN 0x10000000U
+
+/******************** Bit definition for RCC_APB2ENR register ***************/
+#define RCC_APB2ENR_TIM1EN 0x00000001U
+#define RCC_APB2ENR_TIM8EN 0x00000002U
+#define RCC_APB2ENR_USART1EN 0x00000010U
+#define RCC_APB2ENR_USART6EN 0x00000020U
+#define RCC_APB2ENR_ADC1EN 0x00000100U
+#define RCC_APB2ENR_SDIOEN 0x00000800U
+#define RCC_APB2ENR_SPI1EN 0x00001000U
+#define RCC_APB2ENR_SPI4EN 0x00002000U
+#define RCC_APB2ENR_SYSCFGEN 0x00004000U
+#define RCC_APB2ENR_EXTITEN 0x00008000U
+#define RCC_APB2ENR_TIM9EN 0x00010000U
+#define RCC_APB2ENR_TIM10EN 0x00020000U
+#define RCC_APB2ENR_TIM11EN 0x00040000U
+#define RCC_APB2ENR_SPI5EN 0x00100000U
+#define RCC_APB2ENR_DFSDM1EN 0x01000000U
+/******************** Bit definition for RCC_AHB1LPENR register *************/
+#define RCC_AHB1LPENR_GPIOALPEN 0x00000001U
+#define RCC_AHB1LPENR_GPIOBLPEN 0x00000002U
+#define RCC_AHB1LPENR_GPIOCLPEN 0x00000004U
+#define RCC_AHB1LPENR_GPIODLPEN 0x00000008U
+#define RCC_AHB1LPENR_GPIOELPEN 0x00000010U
+#define RCC_AHB1LPENR_GPIOFLPEN 0x00000020U
+#define RCC_AHB1LPENR_GPIOGLPEN 0x00000040U
+#define RCC_AHB1LPENR_GPIOHLPEN 0x00000080U
+#define RCC_AHB1LPENR_CRCLPEN 0x00001000U
+#define RCC_AHB1LPENR_FLITFLPEN 0x00008000U
+#define RCC_AHB1LPENR_SRAM1LPEN 0x00010000U
+#define RCC_AHB1LPENR_DMA1LPEN 0x00200000U
+#define RCC_AHB1LPENR_DMA2LPEN 0x00400000U
+
+/******************** Bit definition for RCC_AHB2LPENR register *************/
+#define RCC_AHB2LPENR_RNGLPEN 0x00000040U
+#define RCC_AHB2LPENR_OTGFSLPEN 0x00000080U
+
+/******************** Bit definition for RCC_AHB3LPENR register *************/
+#define RCC_AHB3LPENR_FSMCLPEN 0x00000001U
+#define RCC_AHB3LPENR_QSPILPEN 0x00000002U
+
+/******************** Bit definition for RCC_APB1LPENR register *************/
+#define RCC_APB1LPENR_TIM2LPEN 0x00000001U
+#define RCC_APB1LPENR_TIM3LPEN 0x00000002U
+#define RCC_APB1LPENR_TIM4LPEN 0x00000004U
+#define RCC_APB1LPENR_TIM5LPEN 0x00000008U
+#define RCC_APB1LPENR_TIM6LPEN 0x00000010U
+#define RCC_APB1LPENR_TIM7LPEN 0x00000020U
+#define RCC_APB1LPENR_TIM12LPEN 0x00000040U
+#define RCC_APB1LPENR_TIM13LPEN 0x00000080U
+#define RCC_APB1LPENR_TIM14LPEN 0x00000100U
+#define RCC_APB1LPENR_RTCAPBLPEN 0x00000400U
+#define RCC_APB1LPENR_WWDGLPEN 0x00000800U
+#define RCC_APB1LPENR_SPI2LPEN 0x00004000U
+#define RCC_APB1LPENR_SPI3LPEN 0x00008000U
+#define RCC_APB1LPENR_USART2LPEN 0x00020000U
+#define RCC_APB1LPENR_USART3LPEN 0x00040000U
+#define RCC_APB1LPENR_I2C1LPEN 0x00200000U
+#define RCC_APB1LPENR_I2C2LPEN 0x00400000U
+#define RCC_APB1LPENR_I2C3LPEN 0x00800000U
+#define RCC_APB1LPENR_FMPI2C1LPEN 0x01000000U
+#define RCC_APB1LPENR_CAN1LPEN 0x02000000U
+#define RCC_APB1LPENR_CAN2LPEN 0x04000000U
+#define RCC_APB1LPENR_PWRLPEN 0x10000000U
+
+/******************** Bit definition for RCC_APB2LPENR register *************/
+#define RCC_APB2LPENR_TIM1LPEN 0x00000001U
+#define RCC_APB2LPENR_TIM8LPEN 0x00000002U
+#define RCC_APB2LPENR_USART1LPEN 0x00000010U
+#define RCC_APB2LPENR_USART6LPEN 0x00000020U
+#define RCC_APB2LPENR_ADC1LPEN 0x00000100U
+#define RCC_APB2LPENR_SDIOLPEN 0x00000800U
+#define RCC_APB2LPENR_SPI1LPEN 0x00001000U
+#define RCC_APB2LPENR_SPI4LPEN 0x00002000U
+#define RCC_APB2LPENR_SYSCFGLPEN 0x00004000U
+#define RCC_APB2LPENR_EXTITLPEN 0x00008000U
+#define RCC_APB2LPENR_TIM9LPEN 0x00010000U
+#define RCC_APB2LPENR_TIM10LPEN 0x00020000U
+#define RCC_APB2LPENR_TIM11LPEN 0x00040000U
+#define RCC_APB2LPENR_SPI5LPEN 0x00100000U
+#define RCC_APB2LPENR_DFSDM1LPEN 0x01000000U
+
+/******************** Bit definition for RCC_BDCR register ******************/
+#define RCC_BDCR_LSEON 0x00000001U
+#define RCC_BDCR_LSERDY 0x00000002U
+#define RCC_BDCR_LSEBYP 0x00000004U
+#define RCC_BDCR_LSEMOD 0x00000008U
+
+#define RCC_BDCR_RTCSEL 0x00000300U
+#define RCC_BDCR_RTCSEL_0 0x00000100U
+#define RCC_BDCR_RTCSEL_1 0x00000200U
+
+#define RCC_BDCR_RTCEN 0x00008000U
+#define RCC_BDCR_BDRST 0x00010000U
+
+/******************** Bit definition for RCC_CSR register *******************/
+#define RCC_CSR_LSION 0x00000001U
+#define RCC_CSR_LSIRDY 0x00000002U
+#define RCC_CSR_RMVF 0x01000000U
+#define RCC_CSR_PADRSTF 0x04000000U
+#define RCC_CSR_PORRSTF 0x08000000U
+#define RCC_CSR_SFTRSTF 0x10000000U
+#define RCC_CSR_WDGRSTF 0x20000000U
+#define RCC_CSR_WWDGRSTF 0x40000000U
+#define RCC_CSR_LPWRRSTF 0x80000000U
+
+/******************** Bit definition for RCC_SSCGR register *****************/
+#define RCC_SSCGR_MODPER 0x00001FFFU
+#define RCC_SSCGR_INCSTEP 0x0FFFE000U
+#define RCC_SSCGR_SPREADSEL 0x40000000U
+#define RCC_SSCGR_SSCGEN 0x80000000U
+
+/******************** Bit definition for RCC_PLLI2SCFGR register ************/
+#define RCC_PLLI2SCFGR_PLLI2SM 0x0000003FU
+#define RCC_PLLI2SCFGR_PLLI2SM_0 0x00000001U
+#define RCC_PLLI2SCFGR_PLLI2SM_1 0x00000002U
+#define RCC_PLLI2SCFGR_PLLI2SM_2 0x00000004U
+#define RCC_PLLI2SCFGR_PLLI2SM_3 0x00000008U
+#define RCC_PLLI2SCFGR_PLLI2SM_4 0x00000010U
+#define RCC_PLLI2SCFGR_PLLI2SM_5 0x00000020U
+
+#define RCC_PLLI2SCFGR_PLLI2SN 0x00007FC0U
+#define RCC_PLLI2SCFGR_PLLI2SN_0 0x00000040U
+#define RCC_PLLI2SCFGR_PLLI2SN_1 0x00000080U
+#define RCC_PLLI2SCFGR_PLLI2SN_2 0x00000100U
+#define RCC_PLLI2SCFGR_PLLI2SN_3 0x00000200U
+#define RCC_PLLI2SCFGR_PLLI2SN_4 0x00000400U
+#define RCC_PLLI2SCFGR_PLLI2SN_5 0x00000800U
+#define RCC_PLLI2SCFGR_PLLI2SN_6 0x00001000U
+#define RCC_PLLI2SCFGR_PLLI2SN_7 0x00002000U
+#define RCC_PLLI2SCFGR_PLLI2SN_8 0x00004000U
+
+#define RCC_PLLI2SCFGR_PLLI2SSRC 0x00400000U
+
+#define RCC_PLLI2SCFGR_PLLI2SQ 0x0F000000U
+#define RCC_PLLI2SCFGR_PLLI2SQ_0 0x01000000U
+#define RCC_PLLI2SCFGR_PLLI2SQ_1 0x02000000U
+#define RCC_PLLI2SCFGR_PLLI2SQ_2 0x04000000U
+#define RCC_PLLI2SCFGR_PLLI2SQ_3 0x08000000U
+
+#define RCC_PLLI2SCFGR_PLLI2SR 0x70000000U
+#define RCC_PLLI2SCFGR_PLLI2SR_0 0x10000000U
+#define RCC_PLLI2SCFGR_PLLI2SR_1 0x20000000U
+#define RCC_PLLI2SCFGR_PLLI2SR_2 0x40000000U
+
+/******************** Bit definition for RCC_DCKCFGR register ****************/
+#define RCC_DCKCFGR_CKDFSDM1ASEL 0x00008000U
+#define RCC_DCKCFGR_TIMPRE 0x01000000U
+
+#define RCC_DCKCFGR_I2S1SRC 0x06000000U
+#define RCC_DCKCFGR_I2S1SRC_0 0x02000000U
+#define RCC_DCKCFGR_I2S1SRC_1 0x04000000U
+
+#define RCC_DCKCFGR_I2S2SRC 0x18000000U
+#define RCC_DCKCFGR_I2S2SRC_0 0x08000000U
+#define RCC_DCKCFGR_I2S2SRC_1 0x10000000U
+
+#define RCC_DCKCFGR_CKDFSDM1SEL 0x80000000U
+
+/******************** Bit definition for RCC_CKGATENR register ***************/
+#define RCC_CKGATENR_AHB2APB1_CKEN 0x00000001U
+#define RCC_CKGATENR_AHB2APB2_CKEN 0x00000002U
+#define RCC_CKGATENR_CM4DBG_CKEN 0x00000004U
+#define RCC_CKGATENR_SPARE_CKEN 0x00000008U
+#define RCC_CKGATENR_SRAM_CKEN 0x00000010U
+#define RCC_CKGATENR_FLITF_CKEN 0x00000020U
+#define RCC_CKGATENR_RCC_CKEN 0x00000040U
+#define RCC_CKGATENR_RCC_EVTCTL 0x00000080U
+
+/******************** Bit definition for RCC_DCKCFGR2 register ***************/
+#define RCC_DCKCFGR2_FMPI2C1SEL 0x00C00000U
+#define RCC_DCKCFGR2_FMPI2C1SEL_0 0x00400000U
+#define RCC_DCKCFGR2_FMPI2C1SEL_1 0x00800000U
+
+#define RCC_DCKCFGR2_CK48MSEL 0x08000000U
+#define RCC_DCKCFGR2_SDIOSEL 0x10000000U
+
+/******************************************************************************/
+/* */
+/* RNG */
+/* */
+/******************************************************************************/
+/******************** Bits definition for RNG_CR register *******************/
+#define RNG_CR_RNGEN 0x00000004U
+#define RNG_CR_IE 0x00000008U
+
+/******************** Bits definition for RNG_SR register *******************/
+#define RNG_SR_DRDY 0x00000001U
+#define RNG_SR_CECS 0x00000002U
+#define RNG_SR_SECS 0x00000004U
+#define RNG_SR_CEIS 0x00000020U
+#define RNG_SR_SEIS 0x00000040U
+
+/******************************************************************************/
+/* */
+/* Real-Time Clock (RTC) */
+/* */
+/******************************************************************************/
+/******************** Bits definition for RTC_TR register *******************/
+#define RTC_TR_PM 0x00400000U
+#define RTC_TR_HT 0x00300000U
+#define RTC_TR_HT_0 0x00100000U
+#define RTC_TR_HT_1 0x00200000U
+#define RTC_TR_HU 0x000F0000U
+#define RTC_TR_HU_0 0x00010000U
+#define RTC_TR_HU_1 0x00020000U
+#define RTC_TR_HU_2 0x00040000U
+#define RTC_TR_HU_3 0x00080000U
+#define RTC_TR_MNT 0x00007000U
+#define RTC_TR_MNT_0 0x00001000U
+#define RTC_TR_MNT_1 0x00002000U
+#define RTC_TR_MNT_2 0x00004000U
+#define RTC_TR_MNU 0x00000F00U
+#define RTC_TR_MNU_0 0x00000100U
+#define RTC_TR_MNU_1 0x00000200U
+#define RTC_TR_MNU_2 0x00000400U
+#define RTC_TR_MNU_3 0x00000800U
+#define RTC_TR_ST 0x00000070U
+#define RTC_TR_ST_0 0x00000010U
+#define RTC_TR_ST_1 0x00000020U
+#define RTC_TR_ST_2 0x00000040U
+#define RTC_TR_SU 0x0000000FU
+#define RTC_TR_SU_0 0x00000001U
+#define RTC_TR_SU_1 0x00000002U
+#define RTC_TR_SU_2 0x00000004U
+#define RTC_TR_SU_3 0x00000008U
+
+/******************** Bits definition for RTC_DR register *******************/
+#define RTC_DR_YT 0x00F00000U
+#define RTC_DR_YT_0 0x00100000U
+#define RTC_DR_YT_1 0x00200000U
+#define RTC_DR_YT_2 0x00400000U
+#define RTC_DR_YT_3 0x00800000U
+#define RTC_DR_YU 0x000F0000U
+#define RTC_DR_YU_0 0x00010000U
+#define RTC_DR_YU_1 0x00020000U
+#define RTC_DR_YU_2 0x00040000U
+#define RTC_DR_YU_3 0x00080000U
+#define RTC_DR_WDU 0x0000E000U
+#define RTC_DR_WDU_0 0x00002000U
+#define RTC_DR_WDU_1 0x00004000U
+#define RTC_DR_WDU_2 0x00008000U
+#define RTC_DR_MT 0x00001000U
+#define RTC_DR_MU 0x00000F00U
+#define RTC_DR_MU_0 0x00000100U
+#define RTC_DR_MU_1 0x00000200U
+#define RTC_DR_MU_2 0x00000400U
+#define RTC_DR_MU_3 0x00000800U
+#define RTC_DR_DT 0x00000030U
+#define RTC_DR_DT_0 0x00000010U
+#define RTC_DR_DT_1 0x00000020U
+#define RTC_DR_DU 0x0000000FU
+#define RTC_DR_DU_0 0x00000001U
+#define RTC_DR_DU_1 0x00000002U
+#define RTC_DR_DU_2 0x00000004U
+#define RTC_DR_DU_3 0x00000008U
+
+/******************** Bits definition for RTC_CR register *******************/
+#define RTC_CR_COE 0x00800000U
+#define RTC_CR_OSEL 0x00600000U
+#define RTC_CR_OSEL_0 0x00200000U
+#define RTC_CR_OSEL_1 0x00400000U
+#define RTC_CR_POL 0x00100000U
+#define RTC_CR_COSEL 0x00080000U
+#define RTC_CR_BCK 0x00040000U
+#define RTC_CR_SUB1H 0x00020000U
+#define RTC_CR_ADD1H 0x00010000U
+#define RTC_CR_TSIE 0x00008000U
+#define RTC_CR_WUTIE 0x00004000U
+#define RTC_CR_ALRBIE 0x00002000U
+#define RTC_CR_ALRAIE 0x00001000U
+#define RTC_CR_TSE 0x00000800U
+#define RTC_CR_WUTE 0x00000400U
+#define RTC_CR_ALRBE 0x00000200U
+#define RTC_CR_ALRAE 0x00000100U
+#define RTC_CR_DCE 0x00000080U
+#define RTC_CR_FMT 0x00000040U
+#define RTC_CR_BYPSHAD 0x00000020U
+#define RTC_CR_REFCKON 0x00000010U
+#define RTC_CR_TSEDGE 0x00000008U
+#define RTC_CR_WUCKSEL 0x00000007U
+#define RTC_CR_WUCKSEL_0 0x00000001U
+#define RTC_CR_WUCKSEL_1 0x00000002U
+#define RTC_CR_WUCKSEL_2 0x00000004U
+
+/******************** Bits definition for RTC_ISR register ******************/
+#define RTC_ISR_RECALPF 0x00010000U
+#define RTC_ISR_TAMP1F 0x00002000U
+#define RTC_ISR_TAMP2F 0x00004000U
+#define RTC_ISR_TSOVF 0x00001000U
+#define RTC_ISR_TSF 0x00000800U
+#define RTC_ISR_WUTF 0x00000400U
+#define RTC_ISR_ALRBF 0x00000200U
+#define RTC_ISR_ALRAF 0x00000100U
+#define RTC_ISR_INIT 0x00000080U
+#define RTC_ISR_INITF 0x00000040U
+#define RTC_ISR_RSF 0x00000020U
+#define RTC_ISR_INITS 0x00000010U
+#define RTC_ISR_SHPF 0x00000008U
+#define RTC_ISR_WUTWF 0x00000004U
+#define RTC_ISR_ALRBWF 0x00000002U
+#define RTC_ISR_ALRAWF 0x00000001U
+
+/******************** Bits definition for RTC_PRER register *****************/
+#define RTC_PRER_PREDIV_A 0x007F0000U
+#define RTC_PRER_PREDIV_S 0x00007FFFU
+
+/******************** Bits definition for RTC_WUTR register *****************/
+#define RTC_WUTR_WUT 0x0000FFFFU
+
+/******************** Bits definition for RTC_CALIBR register ***************/
+#define RTC_CALIBR_DCS 0x00000080U
+#define RTC_CALIBR_DC 0x0000001FU
+
+/******************** Bits definition for RTC_ALRMAR register ***************/
+#define RTC_ALRMAR_MSK4 0x80000000U
+#define RTC_ALRMAR_WDSEL 0x40000000U
+#define RTC_ALRMAR_DT 0x30000000U
+#define RTC_ALRMAR_DT_0 0x10000000U
+#define RTC_ALRMAR_DT_1 0x20000000U
+#define RTC_ALRMAR_DU 0x0F000000U
+#define RTC_ALRMAR_DU_0 0x01000000U
+#define RTC_ALRMAR_DU_1 0x02000000U
+#define RTC_ALRMAR_DU_2 0x04000000U
+#define RTC_ALRMAR_DU_3 0x08000000U
+#define RTC_ALRMAR_MSK3 0x00800000U
+#define RTC_ALRMAR_PM 0x00400000U
+#define RTC_ALRMAR_HT 0x00300000U
+#define RTC_ALRMAR_HT_0 0x00100000U
+#define RTC_ALRMAR_HT_1 0x00200000U
+#define RTC_ALRMAR_HU 0x000F0000U
+#define RTC_ALRMAR_HU_0 0x00010000U
+#define RTC_ALRMAR_HU_1 0x00020000U
+#define RTC_ALRMAR_HU_2 0x00040000U
+#define RTC_ALRMAR_HU_3 0x00080000U
+#define RTC_ALRMAR_MSK2 0x00008000U
+#define RTC_ALRMAR_MNT 0x00007000U
+#define RTC_ALRMAR_MNT_0 0x00001000U
+#define RTC_ALRMAR_MNT_1 0x00002000U
+#define RTC_ALRMAR_MNT_2 0x00004000U
+#define RTC_ALRMAR_MNU 0x00000F00U
+#define RTC_ALRMAR_MNU_0 0x00000100U
+#define RTC_ALRMAR_MNU_1 0x00000200U
+#define RTC_ALRMAR_MNU_2 0x00000400U
+#define RTC_ALRMAR_MNU_3 0x00000800U
+#define RTC_ALRMAR_MSK1 0x00000080U
+#define RTC_ALRMAR_ST 0x00000070U
+#define RTC_ALRMAR_ST_0 0x00000010U
+#define RTC_ALRMAR_ST_1 0x00000020U
+#define RTC_ALRMAR_ST_2 0x00000040U
+#define RTC_ALRMAR_SU 0x0000000FU
+#define RTC_ALRMAR_SU_0 0x00000001U
+#define RTC_ALRMAR_SU_1 0x00000002U
+#define RTC_ALRMAR_SU_2 0x00000004U
+#define RTC_ALRMAR_SU_3 0x00000008U
+
+/******************** Bits definition for RTC_ALRMBR register ***************/
+#define RTC_ALRMBR_MSK4 0x80000000U
+#define RTC_ALRMBR_WDSEL 0x40000000U
+#define RTC_ALRMBR_DT 0x30000000U
+#define RTC_ALRMBR_DT_0 0x10000000U
+#define RTC_ALRMBR_DT_1 0x20000000U
+#define RTC_ALRMBR_DU 0x0F000000U
+#define RTC_ALRMBR_DU_0 0x01000000U
+#define RTC_ALRMBR_DU_1 0x02000000U
+#define RTC_ALRMBR_DU_2 0x04000000U
+#define RTC_ALRMBR_DU_3 0x08000000U
+#define RTC_ALRMBR_MSK3 0x00800000U
+#define RTC_ALRMBR_PM 0x00400000U
+#define RTC_ALRMBR_HT 0x00300000U
+#define RTC_ALRMBR_HT_0 0x00100000U
+#define RTC_ALRMBR_HT_1 0x00200000U
+#define RTC_ALRMBR_HU 0x000F0000U
+#define RTC_ALRMBR_HU_0 0x00010000U
+#define RTC_ALRMBR_HU_1 0x00020000U
+#define RTC_ALRMBR_HU_2 0x00040000U
+#define RTC_ALRMBR_HU_3 0x00080000U
+#define RTC_ALRMBR_MSK2 0x00008000U
+#define RTC_ALRMBR_MNT 0x00007000U
+#define RTC_ALRMBR_MNT_0 0x00001000U
+#define RTC_ALRMBR_MNT_1 0x00002000U
+#define RTC_ALRMBR_MNT_2 0x00004000U
+#define RTC_ALRMBR_MNU 0x00000F00U
+#define RTC_ALRMBR_MNU_0 0x00000100U
+#define RTC_ALRMBR_MNU_1 0x00000200U
+#define RTC_ALRMBR_MNU_2 0x00000400U
+#define RTC_ALRMBR_MNU_3 0x00000800U
+#define RTC_ALRMBR_MSK1 0x00000080U
+#define RTC_ALRMBR_ST 0x00000070U
+#define RTC_ALRMBR_ST_0 0x00000010U
+#define RTC_ALRMBR_ST_1 0x00000020U
+#define RTC_ALRMBR_ST_2 0x00000040U
+#define RTC_ALRMBR_SU 0x0000000FU
+#define RTC_ALRMBR_SU_0 0x00000001U
+#define RTC_ALRMBR_SU_1 0x00000002U
+#define RTC_ALRMBR_SU_2 0x00000004U
+#define RTC_ALRMBR_SU_3 0x00000008U
+
+/******************** Bits definition for RTC_WPR register ******************/
+#define RTC_WPR_KEY 0x000000FFU
+
+/******************** Bits definition for RTC_SSR register ******************/
+#define RTC_SSR_SS 0x0000FFFFU
+
+/******************** Bits definition for RTC_SHIFTR register ***************/
+#define RTC_SHIFTR_SUBFS 0x00007FFFU
+#define RTC_SHIFTR_ADD1S 0x80000000U
+
+/******************** Bits definition for RTC_TSTR register *****************/
+#define RTC_TSTR_PM 0x00400000U
+#define RTC_TSTR_HT 0x00300000U
+#define RTC_TSTR_HT_0 0x00100000U
+#define RTC_TSTR_HT_1 0x00200000U
+#define RTC_TSTR_HU 0x000F0000U
+#define RTC_TSTR_HU_0 0x00010000U
+#define RTC_TSTR_HU_1 0x00020000U
+#define RTC_TSTR_HU_2 0x00040000U
+#define RTC_TSTR_HU_3 0x00080000U
+#define RTC_TSTR_MNT 0x00007000U
+#define RTC_TSTR_MNT_0 0x00001000U
+#define RTC_TSTR_MNT_1 0x00002000U
+#define RTC_TSTR_MNT_2 0x00004000U
+#define RTC_TSTR_MNU 0x00000F00U
+#define RTC_TSTR_MNU_0 0x00000100U
+#define RTC_TSTR_MNU_1 0x00000200U
+#define RTC_TSTR_MNU_2 0x00000400U
+#define RTC_TSTR_MNU_3 0x00000800U
+#define RTC_TSTR_ST 0x00000070U
+#define RTC_TSTR_ST_0 0x00000010U
+#define RTC_TSTR_ST_1 0x00000020U
+#define RTC_TSTR_ST_2 0x00000040U
+#define RTC_TSTR_SU 0x0000000FU
+#define RTC_TSTR_SU_0 0x00000001U
+#define RTC_TSTR_SU_1 0x00000002U
+#define RTC_TSTR_SU_2 0x00000004U
+#define RTC_TSTR_SU_3 0x00000008U
+
+/******************** Bits definition for RTC_TSDR register *****************/
+#define RTC_TSDR_WDU 0x0000E000U
+#define RTC_TSDR_WDU_0 0x00002000U
+#define RTC_TSDR_WDU_1 0x00004000U
+#define RTC_TSDR_WDU_2 0x00008000U
+#define RTC_TSDR_MT 0x00001000U
+#define RTC_TSDR_MU 0x00000F00U
+#define RTC_TSDR_MU_0 0x00000100U
+#define RTC_TSDR_MU_1 0x00000200U
+#define RTC_TSDR_MU_2 0x00000400U
+#define RTC_TSDR_MU_3 0x00000800U
+#define RTC_TSDR_DT 0x00000030U
+#define RTC_TSDR_DT_0 0x00000010U
+#define RTC_TSDR_DT_1 0x00000020U
+#define RTC_TSDR_DU 0x0000000FU
+#define RTC_TSDR_DU_0 0x00000001U
+#define RTC_TSDR_DU_1 0x00000002U
+#define RTC_TSDR_DU_2 0x00000004U
+#define RTC_TSDR_DU_3 0x00000008U
+
+/******************** Bits definition for RTC_TSSSR register ****************/
+#define RTC_TSSSR_SS 0x0000FFFFU
+
+/******************** Bits definition for RTC_CAL register *****************/
+#define RTC_CALR_CALP 0x00008000U
+#define RTC_CALR_CALW8 0x00004000U
+#define RTC_CALR_CALW16 0x00002000U
+#define RTC_CALR_CALM 0x000001FFU
+#define RTC_CALR_CALM_0 0x00000001U
+#define RTC_CALR_CALM_1 0x00000002U
+#define RTC_CALR_CALM_2 0x00000004U
+#define RTC_CALR_CALM_3 0x00000008U
+#define RTC_CALR_CALM_4 0x00000010U
+#define RTC_CALR_CALM_5 0x00000020U
+#define RTC_CALR_CALM_6 0x00000040U
+#define RTC_CALR_CALM_7 0x00000080U
+#define RTC_CALR_CALM_8 0x00000100U
+
+/******************** Bits definition for RTC_TAFCR register ****************/
+#define RTC_TAFCR_ALARMOUTTYPE 0x00040000U
+#define RTC_TAFCR_TSINSEL 0x00020000U
+#define RTC_TAFCR_TAMPINSEL 0x00010000U
+#define RTC_TAFCR_TAMPPUDIS 0x00008000U
+#define RTC_TAFCR_TAMPPRCH 0x00006000U
+#define RTC_TAFCR_TAMPPRCH_0 0x00002000U
+#define RTC_TAFCR_TAMPPRCH_1 0x00004000U
+#define RTC_TAFCR_TAMPFLT 0x00001800U
+#define RTC_TAFCR_TAMPFLT_0 0x00000800U
+#define RTC_TAFCR_TAMPFLT_1 0x00001000U
+#define RTC_TAFCR_TAMPFREQ 0x00000700U
+#define RTC_TAFCR_TAMPFREQ_0 0x00000100U
+#define RTC_TAFCR_TAMPFREQ_1 0x00000200U
+#define RTC_TAFCR_TAMPFREQ_2 0x00000400U
+#define RTC_TAFCR_TAMPTS 0x00000080U
+#define RTC_TAFCR_TAMP2TRG 0x00000010U
+#define RTC_TAFCR_TAMP2E 0x00000008U
+#define RTC_TAFCR_TAMPIE 0x00000004U
+#define RTC_TAFCR_TAMP1TRG 0x00000002U
+#define RTC_TAFCR_TAMP1E 0x00000001U
+
+/******************** Bits definition for RTC_ALRMASSR register *************/
+#define RTC_ALRMASSR_MASKSS 0x0F000000U
+#define RTC_ALRMASSR_MASKSS_0 0x01000000U
+#define RTC_ALRMASSR_MASKSS_1 0x02000000U
+#define RTC_ALRMASSR_MASKSS_2 0x04000000U
+#define RTC_ALRMASSR_MASKSS_3 0x08000000U
+#define RTC_ALRMASSR_SS 0x00007FFFU
+
+/******************** Bits definition for RTC_ALRMBSSR register *************/
+#define RTC_ALRMBSSR_MASKSS 0x0F000000U
+#define RTC_ALRMBSSR_MASKSS_0 0x01000000U
+#define RTC_ALRMBSSR_MASKSS_1 0x02000000U
+#define RTC_ALRMBSSR_MASKSS_2 0x04000000U
+#define RTC_ALRMBSSR_MASKSS_3 0x08000000U
+#define RTC_ALRMBSSR_SS 0x00007FFFU
+
+/******************** Bits definition for RTC_BKP0R register ****************/
+#define RTC_BKP0R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP1R register ****************/
+#define RTC_BKP1R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP2R register ****************/
+#define RTC_BKP2R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP3R register ****************/
+#define RTC_BKP3R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP4R register ****************/
+#define RTC_BKP4R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP5R register ****************/
+#define RTC_BKP5R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP6R register ****************/
+#define RTC_BKP6R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP7R register ****************/
+#define RTC_BKP7R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP8R register ****************/
+#define RTC_BKP8R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP9R register ****************/
+#define RTC_BKP9R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP10R register ***************/
+#define RTC_BKP10R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP11R register ***************/
+#define RTC_BKP11R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP12R register ***************/
+#define RTC_BKP12R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP13R register ***************/
+#define RTC_BKP13R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP14R register ***************/
+#define RTC_BKP14R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP15R register ***************/
+#define RTC_BKP15R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP16R register ***************/
+#define RTC_BKP16R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP17R register ***************/
+#define RTC_BKP17R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP18R register ***************/
+#define RTC_BKP18R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP19R register ***************/
+#define RTC_BKP19R 0xFFFFFFFFU
+
+
+
+/******************************************************************************/
+/* */
+/* SD host Interface */
+/* */
+/******************************************************************************/
+/****************** Bit definition for SDIO_POWER register ******************/
+#define SDIO_POWER_PWRCTRL 0x03U /*!<PWRCTRL[1:0] bits (Power supply control bits) */
+#define SDIO_POWER_PWRCTRL_0 0x01U /*!<Bit 0 */
+#define SDIO_POWER_PWRCTRL_1 0x02U /*!<Bit 1 */
+
+/****************** Bit definition for SDIO_CLKCR register ******************/
+#define SDIO_CLKCR_CLKDIV 0x00FFU /*!<Clock divide factor */
+#define SDIO_CLKCR_CLKEN 0x0100U /*!<Clock enable bit */
+#define SDIO_CLKCR_PWRSAV 0x0200U /*!<Power saving configuration bit */
+#define SDIO_CLKCR_BYPASS 0x0400U /*!<Clock divider bypass enable bit */
+
+#define SDIO_CLKCR_WIDBUS 0x1800U /*!<WIDBUS[1:0] bits (Wide bus mode enable bit) */
+#define SDIO_CLKCR_WIDBUS_0 0x0800U /*!<Bit 0 */
+#define SDIO_CLKCR_WIDBUS_1 0x1000U /*!<Bit 1 */
+
+#define SDIO_CLKCR_NEGEDGE 0x2000U /*!<SDIO_CK dephasing selection bit */
+#define SDIO_CLKCR_HWFC_EN 0x4000U /*!<HW Flow Control enable */
+
+/******************* Bit definition for SDIO_ARG register *******************/
+#define SDIO_ARG_CMDARG 0xFFFFFFFFU /*!<Command argument */
+
+/******************* Bit definition for SDIO_CMD register *******************/
+#define SDIO_CMD_CMDINDEX 0x003FU /*!<Command Index */
+
+#define SDIO_CMD_WAITRESP 0x00C0U /*!<WAITRESP[1:0] bits (Wait for response bits) */
+#define SDIO_CMD_WAITRESP_0 0x0040U /*!< Bit 0 */
+#define SDIO_CMD_WAITRESP_1 0x0080U /*!< Bit 1 */
+
+#define SDIO_CMD_WAITINT 0x0100U /*!<CPSM Waits for Interrupt Request */
+#define SDIO_CMD_WAITPEND 0x0200U /*!<CPSM Waits for ends of data transfer (CmdPend internal signal) */
+#define SDIO_CMD_CPSMEN 0x0400U /*!<Command path state machine (CPSM) Enable bit */
+#define SDIO_CMD_SDIOSUSPEND 0x0800U /*!<SD I/O suspend command */
+#define SDIO_CMD_ENCMDCOMPL 0x1000U /*!<Enable CMD completion */
+#define SDIO_CMD_NIEN 0x2000U /*!<Not Interrupt Enable */
+#define SDIO_CMD_CEATACMD 0x4000U /*!<CE-ATA command */
+
+/***************** Bit definition for SDIO_RESPCMD register *****************/
+#define SDIO_RESPCMD_RESPCMD 0x3FU /*!<Response command index */
+
+/****************** Bit definition for SDIO_RESP0 register ******************/
+#define SDIO_RESP0_CARDSTATUS0 0xFFFFFFFFU /*!<Card Status */
+
+/****************** Bit definition for SDIO_RESP1 register ******************/
+#define SDIO_RESP1_CARDSTATUS1 0xFFFFFFFFU /*!<Card Status */
+
+/****************** Bit definition for SDIO_RESP2 register ******************/
+#define SDIO_RESP2_CARDSTATUS2 0xFFFFFFFFU /*!<Card Status */
+
+/****************** Bit definition for SDIO_RESP3 register ******************/
+#define SDIO_RESP3_CARDSTATUS3 0xFFFFFFFFU /*!<Card Status */
+
+/****************** Bit definition for SDIO_RESP4 register ******************/
+#define SDIO_RESP4_CARDSTATUS4 0xFFFFFFFFU /*!<Card Status */
+
+/****************** Bit definition for SDIO_DTIMER register *****************/
+#define SDIO_DTIMER_DATATIME 0xFFFFFFFFU /*!<Data timeout period. */
+
+/****************** Bit definition for SDIO_DLEN register *******************/
+#define SDIO_DLEN_DATALENGTH 0x01FFFFFFU /*!<Data length value */
+
+/****************** Bit definition for SDIO_DCTRL register ******************/
+#define SDIO_DCTRL_DTEN 0x0001U /*!<Data transfer enabled bit */
+#define SDIO_DCTRL_DTDIR 0x0002U /*!<Data transfer direction selection */
+#define SDIO_DCTRL_DTMODE 0x0004U /*!<Data transfer mode selection */
+#define SDIO_DCTRL_DMAEN 0x0008U /*!<DMA enabled bit */
+
+#define SDIO_DCTRL_DBLOCKSIZE 0x00F0U /*!<DBLOCKSIZE[3:0] bits (Data block size) */
+#define SDIO_DCTRL_DBLOCKSIZE_0 0x0010U /*!<Bit 0 */
+#define SDIO_DCTRL_DBLOCKSIZE_1 0x0020U /*!<Bit 1 */
+#define SDIO_DCTRL_DBLOCKSIZE_2 0x0040U /*!<Bit 2 */
+#define SDIO_DCTRL_DBLOCKSIZE_3 0x0080U /*!<Bit 3 */
+
+#define SDIO_DCTRL_RWSTART 0x0100U /*!<Read wait start */
+#define SDIO_DCTRL_RWSTOP 0x0200U /*!<Read wait stop */
+#define SDIO_DCTRL_RWMOD 0x0400U /*!<Read wait mode */
+#define SDIO_DCTRL_SDIOEN 0x0800U /*!<SD I/O enable functions */
+
+/****************** Bit definition for SDIO_DCOUNT register *****************/
+#define SDIO_DCOUNT_DATACOUNT 0x01FFFFFFU /*!<Data count value */
+
+/****************** Bit definition for SDIO_STA register ********************/
+#define SDIO_STA_CCRCFAIL 0x00000001U /*!<Command response received (CRC check failed) */
+#define SDIO_STA_DCRCFAIL 0x00000002U /*!<Data block sent/received (CRC check failed) */
+#define SDIO_STA_CTIMEOUT 0x00000004U /*!<Command response timeout */
+#define SDIO_STA_DTIMEOUT 0x00000008U /*!<Data timeout */
+#define SDIO_STA_TXUNDERR 0x00000010U /*!<Transmit FIFO underrun error */
+#define SDIO_STA_RXOVERR 0x00000020U /*!<Received FIFO overrun error */
+#define SDIO_STA_CMDREND 0x00000040U /*!<Command response received (CRC check passed) */
+#define SDIO_STA_CMDSENT 0x00000080U /*!<Command sent (no response required) */
+#define SDIO_STA_DATAEND 0x00000100U /*!<Data end (data counter, SDIDCOUNT, is zero) */
+#define SDIO_STA_STBITERR 0x00000200U /*!<Start bit not detected on all data signals in wide bus mode */
+#define SDIO_STA_DBCKEND 0x00000400U /*!<Data block sent/received (CRC check passed) */
+#define SDIO_STA_CMDACT 0x00000800U /*!<Command transfer in progress */
+#define SDIO_STA_TXACT 0x00001000U /*!<Data transmit in progress */
+#define SDIO_STA_RXACT 0x00002000U /*!<Data receive in progress */
+#define SDIO_STA_TXFIFOHE 0x00004000U /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
+#define SDIO_STA_RXFIFOHF 0x00008000U /*!<Receive FIFO Half Full: there are at least 8 words in the FIFO */
+#define SDIO_STA_TXFIFOF 0x00010000U /*!<Transmit FIFO full */
+#define SDIO_STA_RXFIFOF 0x00020000U /*!<Receive FIFO full */
+#define SDIO_STA_TXFIFOE 0x00040000U /*!<Transmit FIFO empty */
+#define SDIO_STA_RXFIFOE 0x00080000U /*!<Receive FIFO empty */
+#define SDIO_STA_TXDAVL 0x00100000U /*!<Data available in transmit FIFO */
+#define SDIO_STA_RXDAVL 0x00200000U /*!<Data available in receive FIFO */
+#define SDIO_STA_SDIOIT 0x00400000U /*!<SDIO interrupt received */
+#define SDIO_STA_CEATAEND 0x00800000U /*!<CE-ATA command completion signal received for CMD61 */
+
+/******************* Bit definition for SDIO_ICR register *******************/
+#define SDIO_ICR_CCRCFAILC 0x00000001U /*!<CCRCFAIL flag clear bit */
+#define SDIO_ICR_DCRCFAILC 0x00000002U /*!<DCRCFAIL flag clear bit */
+#define SDIO_ICR_CTIMEOUTC 0x00000004U /*!<CTIMEOUT flag clear bit */
+#define SDIO_ICR_DTIMEOUTC 0x00000008U /*!<DTIMEOUT flag clear bit */
+#define SDIO_ICR_TXUNDERRC 0x00000010U /*!<TXUNDERR flag clear bit */
+#define SDIO_ICR_RXOVERRC 0x00000020U /*!<RXOVERR flag clear bit */
+#define SDIO_ICR_CMDRENDC 0x00000040U /*!<CMDREND flag clear bit */
+#define SDIO_ICR_CMDSENTC 0x00000080U /*!<CMDSENT flag clear bit */
+#define SDIO_ICR_DATAENDC 0x00000100U /*!<DATAEND flag clear bit */
+#define SDIO_ICR_STBITERRC 0x00000200U /*!<STBITERR flag clear bit */
+#define SDIO_ICR_DBCKENDC 0x00000400U /*!<DBCKEND flag clear bit */
+#define SDIO_ICR_SDIOITC 0x00400000U /*!<SDIOIT flag clear bit */
+#define SDIO_ICR_CEATAENDC 0x00800000U /*!<CEATAEND flag clear bit */
+
+/****************** Bit definition for SDIO_MASK register *******************/
+#define SDIO_MASK_CCRCFAILIE 0x00000001U /*!<Command CRC Fail Interrupt Enable */
+#define SDIO_MASK_DCRCFAILIE 0x00000002U /*!<Data CRC Fail Interrupt Enable */
+#define SDIO_MASK_CTIMEOUTIE 0x00000004U /*!<Command TimeOut Interrupt Enable */
+#define SDIO_MASK_DTIMEOUTIE 0x00000008U /*!<Data TimeOut Interrupt Enable */
+#define SDIO_MASK_TXUNDERRIE 0x00000010U /*!<Tx FIFO UnderRun Error Interrupt Enable */
+#define SDIO_MASK_RXOVERRIE 0x00000020U /*!<Rx FIFO OverRun Error Interrupt Enable */
+#define SDIO_MASK_CMDRENDIE 0x00000040U /*!<Command Response Received Interrupt Enable */
+#define SDIO_MASK_CMDSENTIE 0x00000080U /*!<Command Sent Interrupt Enable */
+#define SDIO_MASK_DATAENDIE 0x00000100U /*!<Data End Interrupt Enable */
+#define SDIO_MASK_STBITERRIE 0x00000200U /*!<Start Bit Error Interrupt Enable */
+#define SDIO_MASK_DBCKENDIE 0x00000400U /*!<Data Block End Interrupt Enable */
+#define SDIO_MASK_CMDACTIE 0x00000800U /*!<CCommand Acting Interrupt Enable */
+#define SDIO_MASK_TXACTIE 0x00001000U /*!<Data Transmit Acting Interrupt Enable */
+#define SDIO_MASK_RXACTIE 0x00002000U /*!<Data receive acting interrupt enabled */
+#define SDIO_MASK_TXFIFOHEIE 0x00004000U /*!<Tx FIFO Half Empty interrupt Enable */
+#define SDIO_MASK_RXFIFOHFIE 0x00008000U /*!<Rx FIFO Half Full interrupt Enable */
+#define SDIO_MASK_TXFIFOFIE 0x00010000U /*!<Tx FIFO Full interrupt Enable */
+#define SDIO_MASK_RXFIFOFIE 0x00020000U /*!<Rx FIFO Full interrupt Enable */
+#define SDIO_MASK_TXFIFOEIE 0x00040000U /*!<Tx FIFO Empty interrupt Enable */
+#define SDIO_MASK_RXFIFOEIE 0x00080000U /*!<Rx FIFO Empty interrupt Enable */
+#define SDIO_MASK_TXDAVLIE 0x00100000U /*!<Data available in Tx FIFO interrupt Enable */
+#define SDIO_MASK_RXDAVLIE 0x00200000U /*!<Data available in Rx FIFO interrupt Enable */
+#define SDIO_MASK_SDIOITIE 0x00400000U /*!<SDIO Mode Interrupt Received interrupt Enable */
+#define SDIO_MASK_CEATAENDIE 0x00800000U /*!<CE-ATA command completion signal received Interrupt Enable */
+
+/***************** Bit definition for SDIO_FIFOCNT register *****************/
+#define SDIO_FIFOCNT_FIFOCOUNT 0x00FFFFFFU /*!<Remaining number of words to be written to or read from the FIFO */
+
+/****************** Bit definition for SDIO_FIFO register *******************/
+#define SDIO_FIFO_FIFODATA 0xFFFFFFFFU /*!<Receive and transmit FIFO data */
+
+/******************************************************************************/
+/* */
+/* Serial Peripheral Interface */
+/* */
+/******************************************************************************/
+/******************* Bit definition for SPI_CR1 register ********************/
+#define SPI_CR1_CPHA 0x00000001U /*!<Clock Phase */
+#define SPI_CR1_CPOL 0x00000002U /*!<Clock Polarity */
+#define SPI_CR1_MSTR 0x00000004U /*!<Master Selection */
+
+#define SPI_CR1_BR 0x00000038U /*!<BR[2:0] bits (Baud Rate Control) */
+#define SPI_CR1_BR_0 0x00000008U /*!<Bit 0 */
+#define SPI_CR1_BR_1 0x00000010U /*!<Bit 1 */
+#define SPI_CR1_BR_2 0x00000020U /*!<Bit 2 */
+
+#define SPI_CR1_SPE 0x00000040U /*!<SPI Enable */
+#define SPI_CR1_LSBFIRST 0x00000080U /*!<Frame Format */
+#define SPI_CR1_SSI 0x00000100U /*!<Internal slave select */
+#define SPI_CR1_SSM 0x00000200U /*!<Software slave management */
+#define SPI_CR1_RXONLY 0x00000400U /*!<Receive only */
+#define SPI_CR1_DFF 0x00000800U /*!<Data Frame Format */
+#define SPI_CR1_CRCNEXT 0x00001000U /*!<Transmit CRC next */
+#define SPI_CR1_CRCEN 0x00002000U /*!<Hardware CRC calculation enable */
+#define SPI_CR1_BIDIOE 0x00004000U /*!<Output enable in bidirectional mode */
+#define SPI_CR1_BIDIMODE 0x00008000U /*!<Bidirectional data mode enable */
+
+/******************* Bit definition for SPI_CR2 register ********************/
+#define SPI_CR2_RXDMAEN 0x00000001U /*!<Rx Buffer DMA Enable */
+#define SPI_CR2_TXDMAEN 0x00000002U /*!<Tx Buffer DMA Enable */
+#define SPI_CR2_SSOE 0x00000004U /*!<SS Output Enable */
+#define SPI_CR2_FRF 0x00000010U /*!<Frame Format */
+#define SPI_CR2_ERRIE 0x00000020U /*!<Error Interrupt Enable */
+#define SPI_CR2_RXNEIE 0x00000040U /*!<RX buffer Not Empty Interrupt Enable */
+#define SPI_CR2_TXEIE 0x00000080U /*!<Tx buffer Empty Interrupt Enable */
+
+/******************** Bit definition for SPI_SR register ********************/
+#define SPI_SR_RXNE 0x00000001U /*!<Receive buffer Not Empty */
+#define SPI_SR_TXE 0x00000002U /*!<Transmit buffer Empty */
+#define SPI_SR_CHSIDE 0x00000004U /*!<Channel side */
+#define SPI_SR_UDR 0x00000008U /*!<Underrun flag */
+#define SPI_SR_CRCERR 0x00000010U /*!<CRC Error flag */
+#define SPI_SR_MODF 0x00000020U /*!<Mode fault */
+#define SPI_SR_OVR 0x00000040U /*!<Overrun flag */
+#define SPI_SR_BSY 0x00000080U /*!<Busy flag */
+#define SPI_SR_FRE 0x00000100U /*!<Frame format error flag */
+
+/******************** Bit definition for SPI_DR register ********************/
+#define SPI_DR_DR 0x0000FFFFU /*!<Data Register */
+
+/******************* Bit definition for SPI_CRCPR register ******************/
+#define SPI_CRCPR_CRCPOLY 0x0000FFFFU /*!<CRC polynomial register */
+
+/****************** Bit definition for SPI_RXCRCR register ******************/
+#define SPI_RXCRCR_RXCRC 0x0000FFFFU /*!<Rx CRC Register */
+
+/****************** Bit definition for SPI_TXCRCR register ******************/
+#define SPI_TXCRCR_TXCRC 0x0000FFFFU /*!<Tx CRC Register */
+
+/****************** Bit definition for SPI_I2SCFGR register *****************/
+#define SPI_I2SCFGR_CHLEN 0x00000001U /*!<Channel length (number of bits per audio channel) */
+
+#define SPI_I2SCFGR_DATLEN 0x00000006U /*!<DATLEN[1:0] bits (Data length to be transferred) */
+#define SPI_I2SCFGR_DATLEN_0 0x00000002U /*!<Bit 0 */
+#define SPI_I2SCFGR_DATLEN_1 0x00000004U /*!<Bit 1 */
+
+#define SPI_I2SCFGR_CKPOL 0x00000008U /*!<steady state clock polarity */
+
+#define SPI_I2SCFGR_I2SSTD 0x00000030U /*!<I2SSTD[1:0] bits (I2S standard selection) */
+#define SPI_I2SCFGR_I2SSTD_0 0x00000010U /*!<Bit 0 */
+#define SPI_I2SCFGR_I2SSTD_1 0x00000020U /*!<Bit 1 */
+
+#define SPI_I2SCFGR_PCMSYNC 0x00000080U /*!<PCM frame synchronization */
+
+#define SPI_I2SCFGR_I2SCFG 0x00000300U /*!<I2SCFG[1:0] bits (I2S configuration mode) */
+#define SPI_I2SCFGR_I2SCFG_0 0x00000100U /*!<Bit 0 */
+#define SPI_I2SCFGR_I2SCFG_1 0x00000200U /*!<Bit 1 */
+
+#define SPI_I2SCFGR_I2SE 0x00000400U /*!<I2S Enable */
+#define SPI_I2SCFGR_I2SMOD 0x00000800U /*!<I2S mode selection */
+
+/****************** Bit definition for SPI_I2SPR register *******************/
+#define SPI_I2SPR_I2SDIV 0x000000FFU /*!<I2S Linear prescaler */
+#define SPI_I2SPR_ODD 0x00000100U /*!<Odd factor for the prescaler */
+#define SPI_I2SPR_MCKOE 0x00000200U /*!<Master Clock Output Enable */
+
+/******************************************************************************/
+/* */
+/* SYSCFG */
+/* */
+/******************************************************************************/
+/****************** Bit definition for SYSCFG_MEMRMP register ***************/
+#define SYSCFG_MEMRMP_MEM_MODE 0x00000007U /*!< SYSCFG_Memory Remap Config */
+#define SYSCFG_MEMRMP_MEM_MODE_0 0x00000001U
+#define SYSCFG_MEMRMP_MEM_MODE_1 0x00000002U
+#define SYSCFG_MEMRMP_MEM_MODE_2 0x00000004U
+
+#define SYSCFG_SWP_FSMC 0x00000C00U /*!< FSMC memory mapping swap */
+/****************** Bit definition for SYSCFG_PMC register ******************/
+#define SYSCFG_PMC_ADC1DC2 0x00010000U /*!< Refer to AN4073 on how to use this bit */
+
+/***************** Bit definition for SYSCFG_EXTICR1 register ***************/
+#define SYSCFG_EXTICR1_EXTI0 0x000FU /*!<EXTI 0 configuration */
+#define SYSCFG_EXTICR1_EXTI1 0x00F0U /*!<EXTI 1 configuration */
+#define SYSCFG_EXTICR1_EXTI2 0x0F00U /*!<EXTI 2 configuration */
+#define SYSCFG_EXTICR1_EXTI3 0xF000U /*!<EXTI 3 configuration */
+/**
+ * @brief EXTI0 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI0_PA 0x0000U /*!<PA[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PB 0x0001U /*!<PB[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PC 0x0002U /*!<PC[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PD 0x0003U /*!<PD[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PE 0x0004U /*!<PE[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PF 0x0005U /*!<PE[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PG 0x0006U /*!<PE[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PH 0x0007U /*!<PH[0] pin */
+
+/**
+ * @brief EXTI1 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI1_PA 0x0000U /*!<PA[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PB 0x0010U /*!<PB[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PC 0x0020U /*!<PC[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PD 0x0030U /*!<PD[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PE 0x0040U /*!<PE[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PF 0x0050U /*!<PD[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PG 0x0060U /*!<PE[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PH 0x0070U /*!<PH[1] pin */
+
+/**
+ * @brief EXTI2 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI2_PA 0x0000U /*!<PA[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PB 0x0100U /*!<PB[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PC 0x0200U /*!<PC[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PD 0x0300U /*!<PD[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PE 0x0400U /*!<PE[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PF 0x0500U /*!<PE[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PG 0x0600U /*!<PE[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PH 0x0700U /*!<PH[2] pin */
+
+/**
+ * @brief EXTI3 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI3_PA 0x0000U /*!<PA[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PB 0x1000U /*!<PB[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PC 0x2000U /*!<PC[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PD 0x3000U /*!<PD[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PE 0x4000U /*!<PE[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PF 0x5000U /*!<PE[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PG 0x6000U /*!<PE[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PH 0x7000U /*!<PH[3] pin */
+
+/***************** Bit definition for SYSCFG_EXTICR2 register ***************/
+#define SYSCFG_EXTICR2_EXTI4 0x000FU /*!<EXTI 4 configuration */
+#define SYSCFG_EXTICR2_EXTI5 0x00F0U /*!<EXTI 5 configuration */
+#define SYSCFG_EXTICR2_EXTI6 0x0F00U /*!<EXTI 6 configuration */
+#define SYSCFG_EXTICR2_EXTI7 0xF000U /*!<EXTI 7 configuration */
+/**
+ * @brief EXTI4 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI4_PA 0x0000U /*!<PA[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PB 0x0001U /*!<PB[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PC 0x0002U /*!<PC[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PD 0x0003U /*!<PD[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PE 0x0004U /*!<PE[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PF 0x0005U /*!<PE[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PG 0x0006U /*!<PE[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PH 0x0007U /*!<PH[4] pin */
+
+/**
+ * @brief EXTI5 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI5_PA 0x0000U /*!<PA[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PB 0x0010U /*!<PB[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PC 0x0020U /*!<PC[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PD 0x0030U /*!<PD[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PE 0x0040U /*!<PE[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PF 0x0050U /*!<PE[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PG 0x0060U /*!<PE[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PH 0x0070U /*!<PH[5] pin */
+
+/**
+ * @brief EXTI6 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI6_PA 0x0000U /*!<PA[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PB 0x0100U /*!<PB[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PC 0x0200U /*!<PC[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PD 0x0300U /*!<PD[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PE 0x0400U /*!<PE[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PF 0x0500U /*!<PE[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PG 0x0600U /*!<PE[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PH 0x0700U /*!<PH[6] pin */
+
+/**
+ * @brief EXTI7 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI7_PA 0x0000U /*!<PA[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PB 0x1000U /*!<PB[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PC 0x2000U /*!<PC[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PD 0x3000U /*!<PD[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PE 0x4000U /*!<PE[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PF 0x5000U /*!<PE[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PG 0x6000U /*!<PE[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PH 0x7000U /*!<PH[7] pin */
+
+
+/***************** Bit definition for SYSCFG_EXTICR3 register ***************/
+#define SYSCFG_EXTICR3_EXTI8 0x000FU /*!<EXTI 8 configuration */
+#define SYSCFG_EXTICR3_EXTI9 0x00F0U /*!<EXTI 9 configuration */
+#define SYSCFG_EXTICR3_EXTI10 0x0F00U /*!<EXTI 10 configuration */
+#define SYSCFG_EXTICR3_EXTI11 0xF000U /*!<EXTI 11 configuration */
+
+/**
+ * @brief EXTI8 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI8_PA 0x0000U /*!<PA[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PB 0x0001U /*!<PB[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PC 0x0002U /*!<PC[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PD 0x0003U /*!<PD[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PE 0x0004U /*!<PE[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PF 0x0005U /*!<PE[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PG 0x0006U /*!<PE[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PH 0x0007U /*!<PH[8] pin */
+
+/**
+ * @brief EXTI9 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI9_PA 0x0000U /*!<PA[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PB 0x0010U /*!<PB[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PC 0x0020U /*!<PC[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PD 0x0030U /*!<PD[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PE 0x0040U /*!<PE[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PF 0x0050U /*!<PE[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PG 0x0060U /*!<PE[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PH 0x0070U /*!<PH[9] pin */
+
+/**
+ * @brief EXTI10 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI10_PA 0x0000U /*!<PA[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PB 0x0100U /*!<PB[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PC 0x0200U /*!<PC[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PD 0x0300U /*!<PD[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PE 0x0400U /*!<PE[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PF 0x0500U /*!<PE[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PG 0x0600U /*!<PE[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PH 0x0700U /*!<PH[10] pin */
+
+/**
+ * @brief EXTI11 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI11_PA 0x0000U /*!<PA[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PB 0x1000U /*!<PB[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PC 0x2000U /*!<PC[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PD 0x3000U /*!<PD[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PE 0x4000U /*!<PE[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PF 0x5000U /*!<PE[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PG 0x6000U /*!<PE[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PH 0x7000U /*!<PH[11] pin */
+
+/***************** Bit definition for SYSCFG_EXTICR4 register ***************/
+#define SYSCFG_EXTICR4_EXTI12 0x000FU /*!<EXTI 12 configuration */
+#define SYSCFG_EXTICR4_EXTI13 0x00F0U /*!<EXTI 13 configuration */
+#define SYSCFG_EXTICR4_EXTI14 0x0F00U /*!<EXTI 14 configuration */
+#define SYSCFG_EXTICR4_EXTI15 0xF000U /*!<EXTI 15 configuration */
+/**
+ * @brief EXTI12 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI12_PA 0x0000U /*!<PA[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PB 0x0001U /*!<PB[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PC 0x0002U /*!<PC[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PD 0x0003U /*!<PD[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PE 0x0004U /*!<PE[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PF 0x0005U /*!<PE[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PG 0x0006U /*!<PE[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PH 0x0007U /*!<PH[12] pin */
+
+/**
+ * @brief EXTI13 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI13_PA 0x0000U /*!<PA[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PB 0x0010U /*!<PB[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PC 0x0020U /*!<PC[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PD 0x0030U /*!<PD[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PE 0x0040U /*!<PE[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PF 0x0050U /*!<PE[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PG 0x0060U /*!<PE[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PH 0x0070U /*!<PH[13] pin */
+
+/**
+ * @brief EXTI14 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI14_PA 0x0000U /*!<PA[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PB 0x0100U /*!<PB[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PC 0x0200U /*!<PC[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PD 0x0300U /*!<PD[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PE 0x0400U /*!<PE[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PF 0x0500U /*!<PE[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PG 0x0600U /*!<PE[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PH 0x0700U /*!<PH[14] pin */
+
+/**
+ * @brief EXTI15 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI15_PA 0x0000U /*!<PA[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PB 0x1000U /*!<PB[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PC 0x2000U /*!<PC[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PD 0x3000U /*!<PD[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PE 0x4000U /*!<PE[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PF 0x5000U /*!<PF[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PG 0x6000U /*!<PG[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PH 0x7000U /*!<PH[15] pin */
+
+/****************** Bit definition for SYSCFG_CMPCR register ****************/
+#define SYSCFG_CMPCR_CMP_PD 0x00000001U /*!<Compensation cell ready flag */
+#define SYSCFG_CMPCR_READY 0x00000100U /*!<Compensation cell power-down */
+
+/****************** Bit definition for SYSCFG_CFGR register *****************/
+#define SYSCFG_CFGR_FMPI2C1_SCL 0x00000001U /*!<FM+ drive capability for FMPI2C1_SCL pin */
+#define SYSCFG_CFGR_FMPI2C1_SDA 0x00000002U /*!<FM+ drive capability for FMPI2C1_SDA pin */
+
+/******************************************************************************/
+/* */
+/* TIM */
+/* */
+/******************************************************************************/
+/******************* Bit definition for TIM_CR1 register ********************/
+#define TIM_CR1_CEN 0x0001U /*!<Counter enable */
+#define TIM_CR1_UDIS 0x0002U /*!<Update disable */
+#define TIM_CR1_URS 0x0004U /*!<Update request source */
+#define TIM_CR1_OPM 0x0008U /*!<One pulse mode */
+#define TIM_CR1_DIR 0x0010U /*!<Direction */
+
+#define TIM_CR1_CMS 0x0060U /*!<CMS[1:0] bits (Center-aligned mode selection) */
+#define TIM_CR1_CMS_0 0x0020U /*!<Bit 0 */
+#define TIM_CR1_CMS_1 0x0040U /*!<Bit 1 */
+
+#define TIM_CR1_ARPE 0x0080U /*!<Auto-reload preload enable */
+
+#define TIM_CR1_CKD 0x0300U /*!<CKD[1:0] bits (clock division) */
+#define TIM_CR1_CKD_0 0x0100U /*!<Bit 0 */
+#define TIM_CR1_CKD_1 0x0200U /*!<Bit 1 */
+
+/******************* Bit definition for TIM_CR2 register ********************/
+#define TIM_CR2_CCPC 0x0001U /*!<Capture/Compare Preloaded Control */
+#define TIM_CR2_CCUS 0x0004U /*!<Capture/Compare Control Update Selection */
+#define TIM_CR2_CCDS 0x0008U /*!<Capture/Compare DMA Selection */
+
+#define TIM_CR2_MMS 0x0070U /*!<MMS[2:0] bits (Master Mode Selection) */
+#define TIM_CR2_MMS_0 0x0010U /*!<Bit 0 */
+#define TIM_CR2_MMS_1 0x0020U /*!<Bit 1 */
+#define TIM_CR2_MMS_2 0x0040U /*!<Bit 2 */
+
+#define TIM_CR2_TI1S 0x0080U /*!<TI1 Selection */
+#define TIM_CR2_OIS1 0x0100U /*!<Output Idle state 1 (OC1 output) */
+#define TIM_CR2_OIS1N 0x0200U /*!<Output Idle state 1 (OC1N output) */
+#define TIM_CR2_OIS2 0x0400U /*!<Output Idle state 2 (OC2 output) */
+#define TIM_CR2_OIS2N 0x0800U /*!<Output Idle state 2 (OC2N output) */
+#define TIM_CR2_OIS3 0x1000U /*!<Output Idle state 3 (OC3 output) */
+#define TIM_CR2_OIS3N 0x2000U /*!<Output Idle state 3 (OC3N output) */
+#define TIM_CR2_OIS4 0x4000U /*!<Output Idle state 4 (OC4 output) */
+
+/******************* Bit definition for TIM_SMCR register *******************/
+#define TIM_SMCR_SMS 0x0007U /*!<SMS[2:0] bits (Slave mode selection) */
+#define TIM_SMCR_SMS_0 0x0001U /*!<Bit 0 */
+#define TIM_SMCR_SMS_1 0x0002U /*!<Bit 1 */
+#define TIM_SMCR_SMS_2 0x0004U /*!<Bit 2 */
+
+#define TIM_SMCR_TS 0x0070U /*!<TS[2:0] bits (Trigger selection) */
+#define TIM_SMCR_TS_0 0x0010U /*!<Bit 0 */
+#define TIM_SMCR_TS_1 0x0020U /*!<Bit 1 */
+#define TIM_SMCR_TS_2 0x0040U /*!<Bit 2 */
+
+#define TIM_SMCR_MSM 0x0080U /*!<Master/slave mode */
+
+#define TIM_SMCR_ETF 0x0F00U /*!<ETF[3:0] bits (External trigger filter) */
+#define TIM_SMCR_ETF_0 0x0100U /*!<Bit 0 */
+#define TIM_SMCR_ETF_1 0x0200U /*!<Bit 1 */
+#define TIM_SMCR_ETF_2 0x0400U /*!<Bit 2 */
+#define TIM_SMCR_ETF_3 0x0800U /*!<Bit 3 */
+
+#define TIM_SMCR_ETPS 0x3000U /*!<ETPS[1:0] bits (External trigger prescaler) */
+#define TIM_SMCR_ETPS_0 0x1000U /*!<Bit 0 */
+#define TIM_SMCR_ETPS_1 0x2000U /*!<Bit 1 */
+
+#define TIM_SMCR_ECE 0x4000U /*!<External clock enable */
+#define TIM_SMCR_ETP 0x8000U /*!<External trigger polarity */
+
+/******************* Bit definition for TIM_DIER register *******************/
+#define TIM_DIER_UIE 0x0001U /*!<Update interrupt enable */
+#define TIM_DIER_CC1IE 0x0002U /*!<Capture/Compare 1 interrupt enable */
+#define TIM_DIER_CC2IE 0x0004U /*!<Capture/Compare 2 interrupt enable */
+#define TIM_DIER_CC3IE 0x0008U /*!<Capture/Compare 3 interrupt enable */
+#define TIM_DIER_CC4IE 0x0010U /*!<Capture/Compare 4 interrupt enable */
+#define TIM_DIER_COMIE 0x0020U /*!<COM interrupt enable */
+#define TIM_DIER_TIE 0x0040U /*!<Trigger interrupt enable */
+#define TIM_DIER_BIE 0x0080U /*!<Break interrupt enable */
+#define TIM_DIER_UDE 0x0100U /*!<Update DMA request enable */
+#define TIM_DIER_CC1DE 0x0200U /*!<Capture/Compare 1 DMA request enable */
+#define TIM_DIER_CC2DE 0x0400U /*!<Capture/Compare 2 DMA request enable */
+#define TIM_DIER_CC3DE 0x0800U /*!<Capture/Compare 3 DMA request enable */
+#define TIM_DIER_CC4DE 0x1000U /*!<Capture/Compare 4 DMA request enable */
+#define TIM_DIER_COMDE 0x2000U /*!<COM DMA request enable */
+#define TIM_DIER_TDE 0x4000U /*!<Trigger DMA request enable */
+
+/******************** Bit definition for TIM_SR register ********************/
+#define TIM_SR_UIF 0x0001U /*!<Update interrupt Flag */
+#define TIM_SR_CC1IF 0x0002U /*!<Capture/Compare 1 interrupt Flag */
+#define TIM_SR_CC2IF 0x0004U /*!<Capture/Compare 2 interrupt Flag */
+#define TIM_SR_CC3IF 0x0008U /*!<Capture/Compare 3 interrupt Flag */
+#define TIM_SR_CC4IF 0x0010U /*!<Capture/Compare 4 interrupt Flag */
+#define TIM_SR_COMIF 0x0020U /*!<COM interrupt Flag */
+#define TIM_SR_TIF 0x0040U /*!<Trigger interrupt Flag */
+#define TIM_SR_BIF 0x0080U /*!<Break interrupt Flag */
+#define TIM_SR_CC1OF 0x0200U /*!<Capture/Compare 1 Overcapture Flag */
+#define TIM_SR_CC2OF 0x0400U /*!<Capture/Compare 2 Overcapture Flag */
+#define TIM_SR_CC3OF 0x0800U /*!<Capture/Compare 3 Overcapture Flag */
+#define TIM_SR_CC4OF 0x1000U /*!<Capture/Compare 4 Overcapture Flag */
+
+/******************* Bit definition for TIM_EGR register ********************/
+#define TIM_EGR_UG 0x01U /*!<Update Generation */
+#define TIM_EGR_CC1G 0x02U /*!<Capture/Compare 1 Generation */
+#define TIM_EGR_CC2G 0x04U /*!<Capture/Compare 2 Generation */
+#define TIM_EGR_CC3G 0x08U /*!<Capture/Compare 3 Generation */
+#define TIM_EGR_CC4G 0x10U /*!<Capture/Compare 4 Generation */
+#define TIM_EGR_COMG 0x20U /*!<Capture/Compare Control Update Generation */
+#define TIM_EGR_TG 0x40U /*!<Trigger Generation */
+#define TIM_EGR_BG 0x80U /*!<Break Generation */
+
+/****************** Bit definition for TIM_CCMR1 register *******************/
+#define TIM_CCMR1_CC1S 0x0003U /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
+#define TIM_CCMR1_CC1S_0 0x0001U /*!<Bit 0 */
+#define TIM_CCMR1_CC1S_1 0x0002U /*!<Bit 1 */
+
+#define TIM_CCMR1_OC1FE 0x0004U /*!<Output Compare 1 Fast enable */
+#define TIM_CCMR1_OC1PE 0x0008U /*!<Output Compare 1 Preload enable */
+
+#define TIM_CCMR1_OC1M 0x0070U /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
+#define TIM_CCMR1_OC1M_0 0x0010U /*!<Bit 0 */
+#define TIM_CCMR1_OC1M_1 0x0020U /*!<Bit 1 */
+#define TIM_CCMR1_OC1M_2 0x0040U /*!<Bit 2 */
+
+#define TIM_CCMR1_OC1CE 0x0080U /*!<Output Compare 1Clear Enable */
+
+#define TIM_CCMR1_CC2S 0x0300U /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
+#define TIM_CCMR1_CC2S_0 0x0100U /*!<Bit 0 */
+#define TIM_CCMR1_CC2S_1 0x0200U /*!<Bit 1 */
+
+#define TIM_CCMR1_OC2FE 0x0400U /*!<Output Compare 2 Fast enable */
+#define TIM_CCMR1_OC2PE 0x0800U /*!<Output Compare 2 Preload enable */
+
+#define TIM_CCMR1_OC2M 0x7000U /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
+#define TIM_CCMR1_OC2M_0 0x1000U /*!<Bit 0 */
+#define TIM_CCMR1_OC2M_1 0x2000U /*!<Bit 1 */
+#define TIM_CCMR1_OC2M_2 0x4000U /*!<Bit 2 */
+
+#define TIM_CCMR1_OC2CE 0x8000U /*!<Output Compare 2 Clear Enable */
+
+/*----------------------------------------------------------------------------*/
+
+#define TIM_CCMR1_IC1PSC 0x000CU /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
+#define TIM_CCMR1_IC1PSC_0 0x0004U /*!<Bit 0 */
+#define TIM_CCMR1_IC1PSC_1 0x0008U /*!<Bit 1 */
+
+#define TIM_CCMR1_IC1F 0x00F0U /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
+#define TIM_CCMR1_IC1F_0 0x0010U /*!<Bit 0 */
+#define TIM_CCMR1_IC1F_1 0x0020U /*!<Bit 1 */
+#define TIM_CCMR1_IC1F_2 0x0040U /*!<Bit 2 */
+#define TIM_CCMR1_IC1F_3 0x0080U /*!<Bit 3 */
+
+#define TIM_CCMR1_IC2PSC 0x0C00U /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
+#define TIM_CCMR1_IC2PSC_0 0x0400U /*!<Bit 0 */
+#define TIM_CCMR1_IC2PSC_1 0x0800U /*!<Bit 1 */
+
+#define TIM_CCMR1_IC2F 0xF000U /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
+#define TIM_CCMR1_IC2F_0 0x1000U /*!<Bit 0 */
+#define TIM_CCMR1_IC2F_1 0x2000U /*!<Bit 1 */
+#define TIM_CCMR1_IC2F_2 0x4000U /*!<Bit 2 */
+#define TIM_CCMR1_IC2F_3 0x8000U /*!<Bit 3 */
+
+/****************** Bit definition for TIM_CCMR2 register *******************/
+#define TIM_CCMR2_CC3S 0x0003U /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
+#define TIM_CCMR2_CC3S_0 0x0001U /*!<Bit 0 */
+#define TIM_CCMR2_CC3S_1 0x0002U /*!<Bit 1 */
+
+#define TIM_CCMR2_OC3FE 0x0004U /*!<Output Compare 3 Fast enable */
+#define TIM_CCMR2_OC3PE 0x0008U /*!<Output Compare 3 Preload enable */
+
+#define TIM_CCMR2_OC3M 0x0070U /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
+#define TIM_CCMR2_OC3M_0 0x0010U /*!<Bit 0 */
+#define TIM_CCMR2_OC3M_1 0x0020U /*!<Bit 1 */
+#define TIM_CCMR2_OC3M_2 0x0040U /*!<Bit 2 */
+
+#define TIM_CCMR2_OC3CE 0x0080U /*!<Output Compare 3 Clear Enable */
+
+#define TIM_CCMR2_CC4S 0x0300U /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
+#define TIM_CCMR2_CC4S_0 0x0100U /*!<Bit 0 */
+#define TIM_CCMR2_CC4S_1 0x0200U /*!<Bit 1 */
+
+#define TIM_CCMR2_OC4FE 0x0400U /*!<Output Compare 4 Fast enable */
+#define TIM_CCMR2_OC4PE 0x0800U /*!<Output Compare 4 Preload enable */
+
+#define TIM_CCMR2_OC4M 0x7000U /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
+#define TIM_CCMR2_OC4M_0 0x1000U /*!<Bit 0 */
+#define TIM_CCMR2_OC4M_1 0x2000U /*!<Bit 1 */
+#define TIM_CCMR2_OC4M_2 0x4000U /*!<Bit 2 */
+
+#define TIM_CCMR2_OC4CE 0x8000U /*!<Output Compare 4 Clear Enable */
+
+/*----------------------------------------------------------------------------*/
+
+#define TIM_CCMR2_IC3PSC 0x000CU /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
+#define TIM_CCMR2_IC3PSC_0 0x0004U /*!<Bit 0 */
+#define TIM_CCMR2_IC3PSC_1 0x0008U /*!<Bit 1 */
+
+#define TIM_CCMR2_IC3F 0x00F0U /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
+#define TIM_CCMR2_IC3F_0 0x0010U /*!<Bit 0 */
+#define TIM_CCMR2_IC3F_1 0x0020U /*!<Bit 1 */
+#define TIM_CCMR2_IC3F_2 0x0040U /*!<Bit 2 */
+#define TIM_CCMR2_IC3F_3 0x0080U /*!<Bit 3 */
+
+#define TIM_CCMR2_IC4PSC 0x0C00U /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
+#define TIM_CCMR2_IC4PSC_0 0x0400U /*!<Bit 0 */
+#define TIM_CCMR2_IC4PSC_1 0x0800U /*!<Bit 1 */
+
+#define TIM_CCMR2_IC4F 0xF000U /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
+#define TIM_CCMR2_IC4F_0 0x1000U /*!<Bit 0 */
+#define TIM_CCMR2_IC4F_1 0x2000U /*!<Bit 1 */
+#define TIM_CCMR2_IC4F_2 0x4000U /*!<Bit 2 */
+#define TIM_CCMR2_IC4F_3 0x8000U /*!<Bit 3 */
+
+/******************* Bit definition for TIM_CCER register *******************/
+#define TIM_CCER_CC1E 0x0001U /*!<Capture/Compare 1 output enable */
+#define TIM_CCER_CC1P 0x0002U /*!<Capture/Compare 1 output Polarity */
+#define TIM_CCER_CC1NE 0x0004U /*!<Capture/Compare 1 Complementary output enable */
+#define TIM_CCER_CC1NP 0x0008U /*!<Capture/Compare 1 Complementary output Polarity */
+#define TIM_CCER_CC2E 0x0010U /*!<Capture/Compare 2 output enable */
+#define TIM_CCER_CC2P 0x0020U /*!<Capture/Compare 2 output Polarity */
+#define TIM_CCER_CC2NE 0x0040U /*!<Capture/Compare 2 Complementary output enable */
+#define TIM_CCER_CC2NP 0x0080U /*!<Capture/Compare 2 Complementary output Polarity */
+#define TIM_CCER_CC3E 0x0100U /*!<Capture/Compare 3 output enable */
+#define TIM_CCER_CC3P 0x0200U /*!<Capture/Compare 3 output Polarity */
+#define TIM_CCER_CC3NE 0x0400U /*!<Capture/Compare 3 Complementary output enable */
+#define TIM_CCER_CC3NP 0x0800U /*!<Capture/Compare 3 Complementary output Polarity */
+#define TIM_CCER_CC4E 0x1000U /*!<Capture/Compare 4 output enable */
+#define TIM_CCER_CC4P 0x2000U /*!<Capture/Compare 4 output Polarity */
+#define TIM_CCER_CC4NP 0x8000U /*!<Capture/Compare 4 Complementary output Polarity */
+
+/******************* Bit definition for TIM_CNT register ********************/
+#define TIM_CNT_CNT 0xFFFFU /*!<Counter Value */
+
+/******************* Bit definition for TIM_PSC register ********************/
+#define TIM_PSC_PSC 0xFFFFU /*!<Prescaler Value */
+
+/******************* Bit definition for TIM_ARR register ********************/
+#define TIM_ARR_ARR 0xFFFFU /*!<actual auto-reload Value */
+
+/******************* Bit definition for TIM_RCR register ********************/
+#define TIM_RCR_REP 0xFFU /*!<Repetition Counter Value */
+
+/******************* Bit definition for TIM_CCR1 register *******************/
+#define TIM_CCR1_CCR1 0xFFFFU /*!<Capture/Compare 1 Value */
+
+/******************* Bit definition for TIM_CCR2 register *******************/
+#define TIM_CCR2_CCR2 0xFFFFU /*!<Capture/Compare 2 Value */
+
+/******************* Bit definition for TIM_CCR3 register *******************/
+#define TIM_CCR3_CCR3 0xFFFFU /*!<Capture/Compare 3 Value */
+
+/******************* Bit definition for TIM_CCR4 register *******************/
+#define TIM_CCR4_CCR4 0xFFFFU /*!<Capture/Compare 4 Value */
+
+/******************* Bit definition for TIM_BDTR register *******************/
+#define TIM_BDTR_DTG 0x00FFU /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
+#define TIM_BDTR_DTG_0 0x0001U /*!<Bit 0 */
+#define TIM_BDTR_DTG_1 0x0002U /*!<Bit 1 */
+#define TIM_BDTR_DTG_2 0x0004U /*!<Bit 2 */
+#define TIM_BDTR_DTG_3 0x0008U /*!<Bit 3 */
+#define TIM_BDTR_DTG_4 0x0010U /*!<Bit 4 */
+#define TIM_BDTR_DTG_5 0x0020U /*!<Bit 5 */
+#define TIM_BDTR_DTG_6 0x0040U /*!<Bit 6 */
+#define TIM_BDTR_DTG_7 0x0080U /*!<Bit 7 */
+
+#define TIM_BDTR_LOCK 0x0300U /*!<LOCK[1:0] bits (Lock Configuration) */
+#define TIM_BDTR_LOCK_0 0x0100U /*!<Bit 0 */
+#define TIM_BDTR_LOCK_1 0x0200U /*!<Bit 1 */
+
+#define TIM_BDTR_OSSI 0x0400U /*!<Off-State Selection for Idle mode */
+#define TIM_BDTR_OSSR 0x0800U /*!<Off-State Selection for Run mode */
+#define TIM_BDTR_BKE 0x1000U /*!<Break enable */
+#define TIM_BDTR_BKP 0x2000U /*!<Break Polarity */
+#define TIM_BDTR_AOE 0x4000U /*!<Automatic Output enable */
+#define TIM_BDTR_MOE 0x8000U /*!<Main Output enable */
+
+/******************* Bit definition for TIM_DCR register ********************/
+#define TIM_DCR_DBA 0x001FU /*!<DBA[4:0] bits (DMA Base Address) */
+#define TIM_DCR_DBA_0 0x0001U /*!<Bit 0 */
+#define TIM_DCR_DBA_1 0x0002U /*!<Bit 1 */
+#define TIM_DCR_DBA_2 0x0004U /*!<Bit 2 */
+#define TIM_DCR_DBA_3 0x0008U /*!<Bit 3 */
+#define TIM_DCR_DBA_4 0x0010U /*!<Bit 4 */
+
+#define TIM_DCR_DBL 0x1F00U /*!<DBL[4:0] bits (DMA Burst Length) */
+#define TIM_DCR_DBL_0 0x0100U /*!<Bit 0 */
+#define TIM_DCR_DBL_1 0x0200U /*!<Bit 1 */
+#define TIM_DCR_DBL_2 0x0400U /*!<Bit 2 */
+#define TIM_DCR_DBL_3 0x0800U /*!<Bit 3 */
+#define TIM_DCR_DBL_4 0x1000U /*!<Bit 4 */
+
+/******************* Bit definition for TIM_DMAR register *******************/
+#define TIM_DMAR_DMAB 0xFFFFU /*!<DMA register for burst accesses */
+
+/******************* Bit definition for TIM_OR register *********************/
+#define TIM_OR_TI4_RMP 0x00C0U /*!<TI4_RMP[1:0] bits (TIM5 Input 4 remap) */
+#define TIM_OR_TI4_RMP_0 0x0040U /*!<Bit 0 */
+#define TIM_OR_TI4_RMP_1 0x0080U /*!<Bit 1 */
+#define TIM_OR_ITR1_RMP 0x0C00U /*!<ITR1_RMP[1:0] bits (TIM2 Internal trigger 1 remap) */
+#define TIM_OR_ITR1_RMP_0 0x0400U /*!<Bit 0 */
+#define TIM_OR_ITR1_RMP_1 0x0800U /*!<Bit 1 */
+
+
+/******************************************************************************/
+/* */
+/* Universal Synchronous Asynchronous Receiver Transmitter */
+/* */
+/******************************************************************************/
+/******************* Bit definition for USART_SR register *******************/
+#define USART_SR_PE 0x0001U /*!<Parity Error */
+#define USART_SR_FE 0x0002U /*!<Framing Error */
+#define USART_SR_NE 0x0004U /*!<Noise Error Flag */
+#define USART_SR_ORE 0x0008U /*!<OverRun Error */
+#define USART_SR_IDLE 0x0010U /*!<IDLE line detected */
+#define USART_SR_RXNE 0x0020U /*!<Read Data Register Not Empty */
+#define USART_SR_TC 0x0040U /*!<Transmission Complete */
+#define USART_SR_TXE 0x0080U /*!<Transmit Data Register Empty */
+#define USART_SR_LBD 0x0100U /*!<LIN Break Detection Flag */
+#define USART_SR_CTS 0x0200U /*!<CTS Flag */
+
+/******************* Bit definition for USART_DR register *******************/
+#define USART_DR_DR 0x01FFU /*!<Data value */
+
+/****************** Bit definition for USART_BRR register *******************/
+#define USART_BRR_DIV_Fraction 0x000FU /*!<Fraction of USARTDIV */
+#define USART_BRR_DIV_Mantissa 0xFFF0U /*!<Mantissa of USARTDIV */
+
+/****************** Bit definition for USART_CR1 register *******************/
+#define USART_CR1_SBK 0x0001U /*!<Send Break */
+#define USART_CR1_RWU 0x0002U /*!<Receiver wakeup */
+#define USART_CR1_RE 0x0004U /*!<Receiver Enable */
+#define USART_CR1_TE 0x0008U /*!<Transmitter Enable */
+#define USART_CR1_IDLEIE 0x0010U /*!<IDLE Interrupt Enable */
+#define USART_CR1_RXNEIE 0x0020U /*!<RXNE Interrupt Enable */
+#define USART_CR1_TCIE 0x0040U /*!<Transmission Complete Interrupt Enable */
+#define USART_CR1_TXEIE 0x0080U /*!<PE Interrupt Enable */
+#define USART_CR1_PEIE 0x0100U /*!<PE Interrupt Enable */
+#define USART_CR1_PS 0x0200U /*!<Parity Selection */
+#define USART_CR1_PCE 0x0400U /*!<Parity Control Enable */
+#define USART_CR1_WAKE 0x0800U /*!<Wakeup method */
+#define USART_CR1_M 0x1000U /*!<Word length */
+#define USART_CR1_UE 0x2000U /*!<USART Enable */
+#define USART_CR1_OVER8 0x8000U /*!<USART Oversampling by 8 enable */
+
+/****************** Bit definition for USART_CR2 register *******************/
+#define USART_CR2_ADD 0x000FU /*!<Address of the USART node */
+#define USART_CR2_LBDL 0x0020U /*!<LIN Break Detection Length */
+#define USART_CR2_LBDIE 0x0040U /*!<LIN Break Detection Interrupt Enable */
+#define USART_CR2_LBCL 0x0100U /*!<Last Bit Clock pulse */
+#define USART_CR2_CPHA 0x0200U /*!<Clock Phase */
+#define USART_CR2_CPOL 0x0400U /*!<Clock Polarity */
+#define USART_CR2_CLKEN 0x0800U /*!<Clock Enable */
+
+#define USART_CR2_STOP 0x3000U /*!<STOP[1:0] bits (STOP bits) */
+#define USART_CR2_STOP_0 0x1000U /*!<Bit 0 */
+#define USART_CR2_STOP_1 0x2000U /*!<Bit 1 */
+
+#define USART_CR2_LINEN 0x4000U /*!<LIN mode enable */
+
+/****************** Bit definition for USART_CR3 register *******************/
+#define USART_CR3_EIE 0x0001U /*!<Error Interrupt Enable */
+#define USART_CR3_IREN 0x0002U /*!<IrDA mode Enable */
+#define USART_CR3_IRLP 0x0004U /*!<IrDA Low-Power */
+#define USART_CR3_HDSEL 0x0008U /*!<Half-Duplex Selection */
+#define USART_CR3_NACK 0x0010U /*!<Smartcard NACK enable */
+#define USART_CR3_SCEN 0x0020U /*!<Smartcard mode enable */
+#define USART_CR3_DMAR 0x0040U /*!<DMA Enable Receiver */
+#define USART_CR3_DMAT 0x0080U /*!<DMA Enable Transmitter */
+#define USART_CR3_RTSE 0x0100U /*!<RTS Enable */
+#define USART_CR3_CTSE 0x0200U /*!<CTS Enable */
+#define USART_CR3_CTSIE 0x0400U /*!<CTS Interrupt Enable */
+#define USART_CR3_ONEBIT 0x0800U /*!<USART One bit method enable */
+
+/****************** Bit definition for USART_GTPR register ******************/
+#define USART_GTPR_PSC 0x00FFU /*!<PSC[7:0] bits (Prescaler value) */
+#define USART_GTPR_PSC_0 0x0001U /*!<Bit 0 */
+#define USART_GTPR_PSC_1 0x0002U /*!<Bit 1 */
+#define USART_GTPR_PSC_2 0x0004U /*!<Bit 2 */
+#define USART_GTPR_PSC_3 0x0008U /*!<Bit 3 */
+#define USART_GTPR_PSC_4 0x0010U /*!<Bit 4 */
+#define USART_GTPR_PSC_5 0x0020U /*!<Bit 5 */
+#define USART_GTPR_PSC_6 0x0040U /*!<Bit 6 */
+#define USART_GTPR_PSC_7 0x0080U /*!<Bit 7 */
+
+#define USART_GTPR_GT 0xFF00U /*!<Guard time value */
+
+/******************************************************************************/
+/* */
+/* Window WATCHDOG */
+/* */
+/******************************************************************************/
+/******************* Bit definition for WWDG_CR register ********************/
+#define WWDG_CR_T 0x7FU /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
+#define WWDG_CR_T_0 0x01U /*!<Bit 0 */
+#define WWDG_CR_T_1 0x02U /*!<Bit 1 */
+#define WWDG_CR_T_2 0x04U /*!<Bit 2 */
+#define WWDG_CR_T_3 0x08U /*!<Bit 3 */
+#define WWDG_CR_T_4 0x10U /*!<Bit 4 */
+#define WWDG_CR_T_5 0x20U /*!<Bit 5 */
+#define WWDG_CR_T_6 0x40U /*!<Bit 6 */
+/* Legacy defines */
+#define WWDG_CR_T0 WWDG_CR_T_0
+#define WWDG_CR_T1 WWDG_CR_T_1
+#define WWDG_CR_T2 WWDG_CR_T_2
+#define WWDG_CR_T3 WWDG_CR_T_3
+#define WWDG_CR_T4 WWDG_CR_T_4
+#define WWDG_CR_T5 WWDG_CR_T_5
+#define WWDG_CR_T6 WWDG_CR_T_6
+
+#define WWDG_CR_WDGA 0x80U /*!<Activation bit */
+
+/******************* Bit definition for WWDG_CFR register *******************/
+#define WWDG_CFR_W 0x007FU /*!<W[6:0] bits (7-bit window value) */
+#define WWDG_CFR_W_0 0x0001U /*!<Bit 0 */
+#define WWDG_CFR_W_1 0x0002U /*!<Bit 1 */
+#define WWDG_CFR_W_2 0x0004U /*!<Bit 2 */
+#define WWDG_CFR_W_3 0x0008U /*!<Bit 3 */
+#define WWDG_CFR_W_4 0x0010U /*!<Bit 4 */
+#define WWDG_CFR_W_5 0x0020U /*!<Bit 5 */
+#define WWDG_CFR_W_6 0x0040U /*!<Bit 6 */
+/* Legacy defines */
+#define WWDG_CFR_W0 WWDG_CFR_W_0
+#define WWDG_CFR_W1 WWDG_CFR_W_1
+#define WWDG_CFR_W2 WWDG_CFR_W_2
+#define WWDG_CFR_W3 WWDG_CFR_W_3
+#define WWDG_CFR_W4 WWDG_CFR_W_4
+#define WWDG_CFR_W5 WWDG_CFR_W_5
+#define WWDG_CFR_W6 WWDG_CFR_W_6
+
+#define WWDG_CFR_WDGTB 0x0180U /*!<WDGTB[1:0] bits (Timer Base) */
+#define WWDG_CFR_WDGTB_0 0x0080U /*!<Bit 0 */
+#define WWDG_CFR_WDGTB_1 0x0100U /*!<Bit 1 */
+/* Legacy defines */
+#define WWDG_CFR_WDGTB0 WWDG_CFR_WDGTB_0
+#define WWDG_CFR_WDGTB1 WWDG_CFR_WDGTB_1
+
+#define WWDG_CFR_EWI 0x0200U /*!<Early Wakeup Interrupt */
+
+/******************* Bit definition for WWDG_SR register ********************/
+#define WWDG_SR_EWIF 0x01U /*!<Early Wakeup Interrupt Flag */
+
+
+/******************************************************************************/
+/* */
+/* DBG */
+/* */
+/******************************************************************************/
+/******************** Bit definition for DBGMCU_IDCODE register *************/
+#define DBGMCU_IDCODE_DEV_ID 0x00000FFFU
+#define DBGMCU_IDCODE_REV_ID 0xFFFF0000U
+
+/******************** Bit definition for DBGMCU_CR register *****************/
+#define DBGMCU_CR_DBG_SLEEP 0x00000001U
+#define DBGMCU_CR_DBG_STOP 0x00000002U
+#define DBGMCU_CR_DBG_STANDBY 0x00000004U
+#define DBGMCU_CR_TRACE_IOEN 0x00000020U
+
+#define DBGMCU_CR_TRACE_MODE 0x000000C0U
+#define DBGMCU_CR_TRACE_MODE_0 0x00000040U/*!<Bit 0 */
+#define DBGMCU_CR_TRACE_MODE_1 0x00000080U/*!<Bit 1 */
+
+/******************** Bit definition for DBGMCU_APB1_FZ register ************/
+#define DBGMCU_APB1_FZ_DBG_TIM2_STOP 0x00000001U
+#define DBGMCU_APB1_FZ_DBG_TIM3_STOP 0x00000002U
+#define DBGMCU_APB1_FZ_DBG_TIM4_STOP 0x00000004U
+#define DBGMCU_APB1_FZ_DBG_TIM5_STOP 0x00000008U
+#define DBGMCU_APB1_FZ_DBG_TIM6_STOP 0x00000010U
+#define DBGMCU_APB1_FZ_DBG_TIM7_STOP 0x00000020U
+#define DBGMCU_APB1_FZ_DBG_TIM12_STOP 0x00000040U
+#define DBGMCU_APB1_FZ_DBG_TIM13_STOP 0x00000080U
+#define DBGMCU_APB1_FZ_DBG_TIM14_STOP 0x00000100U
+#define DBGMCU_APB1_FZ_DBG_RTC_STOP 0x00000400U
+#define DBGMCU_APB1_FZ_DBG_WWDG_STOP 0x00000800U
+#define DBGMCU_APB1_FZ_DBG_IWDG_STOP 0x00001000U
+#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT 0x00200000U
+#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT 0x00400000U
+#define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT 0x00800000U
+#define DBGMCU_APB1_FZ_DBG_CAN1_STOP 0x02000000U
+#define DBGMCU_APB1_FZ_DBG_CAN2_STOP 0x04000000U
+
+/******************** Bit definition for DBGMCU_APB2_FZ register ************/
+#define DBGMCU_APB2_FZ_DBG_TIM1_STOP 0x00000001U
+#define DBGMCU_APB2_FZ_DBG_TIM8_STOP 0x00000002U
+#define DBGMCU_APB2_FZ_DBG_TIM9_STOP 0x00010000U
+#define DBGMCU_APB2_FZ_DBG_TIM10_STOP 0x00020000U
+#define DBGMCU_APB2_FZ_DBG_TIM11_STOP 0x00040000U
+
+/******************************************************************************/
+/* */
+/* USB_OTG */
+/* */
+/******************************************************************************/
+/******************** Bit definition for USB_OTG_GOTGCTL register ***********/
+#define USB_OTG_GOTGCTL_SRQSCS 0x00000001U /*!< Session request success */
+#define USB_OTG_GOTGCTL_SRQ 0x00000002U /*!< Session request */
+#define USB_OTG_GOTGCTL_VBVALOEN 0x00000004U /*!< VBUS valid override enable */
+#define USB_OTG_GOTGCTL_VBVALOVAL 0x00000008U /*!< VBUS valid override value */
+#define USB_OTG_GOTGCTL_AVALOEN 0x00000010U /*!< A-peripheral session valid override enable */
+#define USB_OTG_GOTGCTL_AVALOVAL 0x00000020U /*!< A-peripheral session valid override value */
+#define USB_OTG_GOTGCTL_BVALOEN 0x00000040U /*!< B-peripheral session valid override enable */
+#define USB_OTG_GOTGCTL_BVALOVAL 0x00000080U /*!< B-peripheral session valid override value */
+#define USB_OTG_GOTGCTL_HNGSCS 0x00000100U /*!< Host set HNP enable */
+#define USB_OTG_GOTGCTL_HNPRQ 0x00000200U /*!< HNP request */
+#define USB_OTG_GOTGCTL_HSHNPEN 0x00000400U /*!< Host set HNP enable */
+#define USB_OTG_GOTGCTL_DHNPEN 0x00000800U /*!< Device HNP enabled */
+#define USB_OTG_GOTGCTL_EHEN 0x00001000U /*!< Embedded host enable */
+#define USB_OTG_GOTGCTL_CIDSTS 0x00010000U /*!< Connector ID status */
+#define USB_OTG_GOTGCTL_DBCT 0x00020000U /*!< Long/short debounce time */
+#define USB_OTG_GOTGCTL_ASVLD 0x00040000U /*!< A-session valid */
+#define USB_OTG_GOTGCTL_BSESVLD 0x00080000U /*!< B-session valid */
+#define USB_OTG_GOTGCTL_OTGVER 0x00100000U /*!< OTG version */
+
+/******************** Bit definition for USB_OTG_HCFG register **************/
+
+#define USB_OTG_HCFG_FSLSPCS 0x00000003U /*!< FS/LS PHY clock select */
+#define USB_OTG_HCFG_FSLSPCS_0 0x00000001U /*!<Bit 0 */
+#define USB_OTG_HCFG_FSLSPCS_1 0x00000002U /*!<Bit 1 */
+#define USB_OTG_HCFG_FSLSS 0x00000004U /*!< FS- and LS-only support */
+
+/******************** Bit definition for USB_OTG_DCFG register **************/
+
+#define USB_OTG_DCFG_DSPD 0x00000003U /*!< Device speed */
+#define USB_OTG_DCFG_DSPD_0 0x00000001U /*!<Bit 0 */
+#define USB_OTG_DCFG_DSPD_1 0x00000002U /*!<Bit 1 */
+#define USB_OTG_DCFG_NZLSOHSK 0x00000004U /*!< Nonzero-length status OUT handshake */
+
+#define USB_OTG_DCFG_DAD 0x000007F0U /*!< Device address */
+#define USB_OTG_DCFG_DAD_0 0x00000010U /*!<Bit 0 */
+#define USB_OTG_DCFG_DAD_1 0x00000020U /*!<Bit 1 */
+#define USB_OTG_DCFG_DAD_2 0x00000040U /*!<Bit 2 */
+#define USB_OTG_DCFG_DAD_3 0x00000080U /*!<Bit 3 */
+#define USB_OTG_DCFG_DAD_4 0x00000100U /*!<Bit 4 */
+#define USB_OTG_DCFG_DAD_5 0x00000200U /*!<Bit 5 */
+#define USB_OTG_DCFG_DAD_6 0x00000400U /*!<Bit 6 */
+
+#define USB_OTG_DCFG_PFIVL 0x00001800U /*!< Periodic (micro)frame interval */
+#define USB_OTG_DCFG_PFIVL_0 0x00000800U /*!<Bit 0 */
+#define USB_OTG_DCFG_PFIVL_1 0x00001000U /*!<Bit 1 */
+
+#define USB_OTG_DCFG_PERSCHIVL 0x03000000U /*!< Periodic scheduling interval */
+#define USB_OTG_DCFG_PERSCHIVL_0 0x01000000U /*!<Bit 0 */
+#define USB_OTG_DCFG_PERSCHIVL_1 0x02000000U /*!<Bit 1 */
+
+/******************** Bit definition for USB_OTG_PCGCR register *************/
+#define USB_OTG_PCGCR_STPPCLK 0x00000001U /*!< Stop PHY clock */
+#define USB_OTG_PCGCR_GATEHCLK 0x00000002U /*!< Gate HCLK */
+#define USB_OTG_PCGCR_PHYSUSP 0x00000010U /*!< PHY suspended */
+
+/******************** Bit definition for USB_OTG_GOTGINT register ***********/
+#define USB_OTG_GOTGINT_SEDET 0x00000004U /*!< Session end detected */
+#define USB_OTG_GOTGINT_SRSSCHG 0x00000100U /*!< Session request success status change */
+#define USB_OTG_GOTGINT_HNSSCHG 0x00000200U /*!< Host negotiation success status change */
+#define USB_OTG_GOTGINT_HNGDET 0x00020000U /*!< Host negotiation detected */
+#define USB_OTG_GOTGINT_ADTOCHG 0x00040000U /*!< A-device timeout change */
+#define USB_OTG_GOTGINT_DBCDNE 0x00080000U /*!< Debounce done */
+#define USB_OTG_GOTGINT_IDCHNG 0x00100000U /*!< Change in ID pin input value */
+
+/******************** Bit definition for USB_OTG_DCTL register **************/
+#define USB_OTG_DCTL_RWUSIG 0x00000001U /*!< Remote wakeup signaling */
+#define USB_OTG_DCTL_SDIS 0x00000002U /*!< Soft disconnect */
+#define USB_OTG_DCTL_GINSTS 0x00000004U /*!< Global IN NAK status */
+#define USB_OTG_DCTL_GONSTS 0x00000008U /*!< Global OUT NAK status */
+#define USB_OTG_DCTL_TCTL 0x00000070U /*!< Test control */
+#define USB_OTG_DCTL_TCTL_0 0x00000010U /*!<Bit 0 */
+#define USB_OTG_DCTL_TCTL_1 0x00000020U /*!<Bit 1 */
+#define USB_OTG_DCTL_TCTL_2 0x00000040U /*!<Bit 2 */
+#define USB_OTG_DCTL_SGINAK 0x00000080U /*!< Set global IN NAK */
+#define USB_OTG_DCTL_CGINAK 0x00000100U /*!< Clear global IN NAK */
+#define USB_OTG_DCTL_SGONAK 0x00000200U /*!< Set global OUT NAK */
+#define USB_OTG_DCTL_CGONAK 0x00000400U /*!< Clear global OUT NAK */
+#define USB_OTG_DCTL_POPRGDNE 0x00000800U /*!< Power-on programming done */
+
+/******************** Bit definition for USB_OTG_HFIR register **************/
+#define USB_OTG_HFIR_FRIVL 0x0000FFFFU /*!< Frame interval */
+
+/******************** Bit definition for USB_OTG_HFNUM register *************/
+#define USB_OTG_HFNUM_FRNUM 0x0000FFFFU /*!< Frame number */
+#define USB_OTG_HFNUM_FTREM 0xFFFF0000U /*!< Frame time remaining */
+
+/******************** Bit definition for USB_OTG_DSTS register **************/
+#define USB_OTG_DSTS_SUSPSTS 0x00000001U /*!< Suspend status */
+
+#define USB_OTG_DSTS_ENUMSPD 0x00000006U /*!< Enumerated speed */
+#define USB_OTG_DSTS_ENUMSPD_0 0x00000002U /*!<Bit 0 */
+#define USB_OTG_DSTS_ENUMSPD_1 0x00000004U /*!<Bit 1 */
+#define USB_OTG_DSTS_EERR 0x00000008U /*!< Erratic error */
+#define USB_OTG_DSTS_FNSOF 0x003FFF00U /*!< Frame number of the received SOF */
+
+/******************** Bit definition for USB_OTG_GAHBCFG register ***********/
+#define USB_OTG_GAHBCFG_GINT 0x00000001U /*!< Global interrupt mask */
+#define USB_OTG_GAHBCFG_HBSTLEN 0x0000001EU /*!< Burst length/type */
+#define USB_OTG_GAHBCFG_HBSTLEN_0 0x00000002U /*!<Bit 0 */
+#define USB_OTG_GAHBCFG_HBSTLEN_1 0x00000004U /*!<Bit 1 */
+#define USB_OTG_GAHBCFG_HBSTLEN_2 0x00000008U /*!<Bit 2 */
+#define USB_OTG_GAHBCFG_HBSTLEN_3 0x00000010U /*!<Bit 3 */
+#define USB_OTG_GAHBCFG_DMAEN 0x00000020U /*!< DMA enable */
+#define USB_OTG_GAHBCFG_TXFELVL 0x00000080U /*!< TxFIFO empty level */
+#define USB_OTG_GAHBCFG_PTXFELVL 0x00000100U /*!< Periodic TxFIFO empty level */
+
+/******************** Bit definition for USB_OTG_GUSBCFG register ***********/
+#define USB_OTG_GUSBCFG_TOCAL 0x00000007U /*!< FS timeout calibration */
+#define USB_OTG_GUSBCFG_TOCAL_0 0x00000001U /*!<Bit 0 */
+#define USB_OTG_GUSBCFG_TOCAL_1 0x00000002U /*!<Bit 1 */
+#define USB_OTG_GUSBCFG_TOCAL_2 0x00000004U /*!<Bit 2 */
+#define USB_OTG_GUSBCFG_PHYSEL 0x00000040U /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */
+#define USB_OTG_GUSBCFG_SRPCAP 0x00000100U /*!< SRP-capable */
+#define USB_OTG_GUSBCFG_HNPCAP 0x00000200U /*!< HNP-capable */
+
+#define USB_OTG_GUSBCFG_TRDT 0x00003C00U /*!< USB turnaround time */
+#define USB_OTG_GUSBCFG_TRDT_0 0x00000400U /*!<Bit 0 */
+#define USB_OTG_GUSBCFG_TRDT_1 0x00000800U /*!<Bit 1 */
+#define USB_OTG_GUSBCFG_TRDT_2 0x00001000U /*!<Bit 2 */
+#define USB_OTG_GUSBCFG_TRDT_3 0x00002000U /*!<Bit 3 */
+#define USB_OTG_GUSBCFG_PHYLPCS 0x00008000U /*!< PHY Low-power clock select */
+#define USB_OTG_GUSBCFG_ULPIFSLS 0x00020000U /*!< ULPI FS/LS select */
+#define USB_OTG_GUSBCFG_ULPIAR 0x00040000U /*!< ULPI Auto-resume */
+#define USB_OTG_GUSBCFG_ULPICSM 0x00080000U /*!< ULPI Clock SuspendM */
+#define USB_OTG_GUSBCFG_ULPIEVBUSD 0x00100000U /*!< ULPI External VBUS Drive */
+#define USB_OTG_GUSBCFG_ULPIEVBUSI 0x00200000U /*!< ULPI external VBUS indicator */
+#define USB_OTG_GUSBCFG_TSDPS 0x00400000U /*!< TermSel DLine pulsing selection */
+#define USB_OTG_GUSBCFG_PCCI 0x00800000U /*!< Indicator complement */
+#define USB_OTG_GUSBCFG_PTCI 0x01000000U /*!< Indicator pass through */
+#define USB_OTG_GUSBCFG_ULPIIPD 0x02000000U /*!< ULPI interface protect disable */
+#define USB_OTG_GUSBCFG_FHMOD 0x20000000U /*!< Forced host mode */
+#define USB_OTG_GUSBCFG_FDMOD 0x40000000U /*!< Forced peripheral mode */
+#define USB_OTG_GUSBCFG_CTXPKT 0x80000000U /*!< Corrupt Tx packet */
+
+/******************** Bit definition for USB_OTG_GRSTCTL register ***********/
+#define USB_OTG_GRSTCTL_CSRST 0x00000001U /*!< Core soft reset */
+#define USB_OTG_GRSTCTL_HSRST 0x00000002U /*!< HCLK soft reset */
+#define USB_OTG_GRSTCTL_FCRST 0x00000004U /*!< Host frame counter reset */
+#define USB_OTG_GRSTCTL_RXFFLSH 0x00000010U /*!< RxFIFO flush */
+#define USB_OTG_GRSTCTL_TXFFLSH 0x00000020U /*!< TxFIFO flush */
+
+#define USB_OTG_GRSTCTL_TXFNUM 0x000007C0U /*!< TxFIFO number */
+#define USB_OTG_GRSTCTL_TXFNUM_0 0x00000040U /*!<Bit 0 */
+#define USB_OTG_GRSTCTL_TXFNUM_1 0x00000080U /*!<Bit 1 */
+#define USB_OTG_GRSTCTL_TXFNUM_2 0x00000100U /*!<Bit 2 */
+#define USB_OTG_GRSTCTL_TXFNUM_3 0x00000200U /*!<Bit 3 */
+#define USB_OTG_GRSTCTL_TXFNUM_4 0x00000400U /*!<Bit 4 */
+#define USB_OTG_GRSTCTL_DMAREQ 0x40000000U /*!< DMA request signal */
+#define USB_OTG_GRSTCTL_AHBIDL 0x80000000U /*!< AHB master idle */
+
+/******************** Bit definition for USB_OTG_DIEPMSK register ***********/
+#define USB_OTG_DIEPMSK_XFRCM 0x00000001U /*!< Transfer completed interrupt mask */
+#define USB_OTG_DIEPMSK_EPDM 0x00000002U /*!< Endpoint disabled interrupt mask */
+#define USB_OTG_DIEPMSK_TOM 0x00000008U /*!< Timeout condition mask (nonisochronous endpoints) */
+#define USB_OTG_DIEPMSK_ITTXFEMSK 0x00000010U /*!< IN token received when TxFIFO empty mask */
+#define USB_OTG_DIEPMSK_INEPNMM 0x00000020U /*!< IN token received with EP mismatch mask */
+#define USB_OTG_DIEPMSK_INEPNEM 0x00000040U /*!< IN endpoint NAK effective mask */
+#define USB_OTG_DIEPMSK_TXFURM 0x00000100U /*!< FIFO underrun mask */
+#define USB_OTG_DIEPMSK_BIM 0x00000200U /*!< BNA interrupt mask */
+
+/******************** Bit definition for USB_OTG_HPTXSTS register ***********/
+#define USB_OTG_HPTXSTS_PTXFSAVL 0x0000FFFFU /*!< Periodic transmit data FIFO space available */
+
+#define USB_OTG_HPTXSTS_PTXQSAV 0x00FF0000U /*!< Periodic transmit request queue space available */
+#define USB_OTG_HPTXSTS_PTXQSAV_0 0x00010000U /*!<Bit 0 */
+#define USB_OTG_HPTXSTS_PTXQSAV_1 0x00020000U /*!<Bit 1 */
+#define USB_OTG_HPTXSTS_PTXQSAV_2 0x00040000U /*!<Bit 2 */
+#define USB_OTG_HPTXSTS_PTXQSAV_3 0x00080000U /*!<Bit 3 */
+#define USB_OTG_HPTXSTS_PTXQSAV_4 0x00100000U /*!<Bit 4 */
+#define USB_OTG_HPTXSTS_PTXQSAV_5 0x00200000U /*!<Bit 5 */
+#define USB_OTG_HPTXSTS_PTXQSAV_6 0x00400000U /*!<Bit 6 */
+#define USB_OTG_HPTXSTS_PTXQSAV_7 0x00800000U /*!<Bit 7 */
+
+#define USB_OTG_HPTXSTS_PTXQTOP 0xFF000000U /*!< Top of the periodic transmit request queue */
+#define USB_OTG_HPTXSTS_PTXQTOP_0 0x01000000U /*!<Bit 0 */
+#define USB_OTG_HPTXSTS_PTXQTOP_1 0x02000000U /*!<Bit 1 */
+#define USB_OTG_HPTXSTS_PTXQTOP_2 0x04000000U /*!<Bit 2 */
+#define USB_OTG_HPTXSTS_PTXQTOP_3 0x08000000U /*!<Bit 3 */
+#define USB_OTG_HPTXSTS_PTXQTOP_4 0x10000000U /*!<Bit 4 */
+#define USB_OTG_HPTXSTS_PTXQTOP_5 0x20000000U /*!<Bit 5 */
+#define USB_OTG_HPTXSTS_PTXQTOP_6 0x40000000U /*!<Bit 6 */
+#define USB_OTG_HPTXSTS_PTXQTOP_7 0x80000000U /*!<Bit 7 */
+
+/******************** Bit definition for USB_OTG_HAINT register *************/
+#define USB_OTG_HAINT_HAINT 0x0000FFFFU /*!< Channel interrupts */
+
+/******************** Bit definition for USB_OTG_DOEPMSK register ***********/
+#define USB_OTG_DOEPMSK_XFRCM 0x00000001U /*!< Transfer completed interrupt mask */
+#define USB_OTG_DOEPMSK_EPDM 0x00000002U /*!< Endpoint disabled interrupt mask */
+#define USB_OTG_DOEPMSK_STUPM 0x00000008U /*!< SETUP phase done mask */
+#define USB_OTG_DOEPMSK_OTEPDM 0x00000010U /*!< OUT token received when endpoint disabled mask */
+#define USB_OTG_DOEPMSK_OTEPSPRM 0x00000020U /*!< Status Phase Received mask */
+#define USB_OTG_DOEPMSK_B2BSTUP 0x00000040U /*!< Back-to-back SETUP packets received mask */
+#define USB_OTG_DOEPMSK_OPEM 0x00000100U /*!< OUT packet error mask */
+#define USB_OTG_DOEPMSK_BOIM 0x00000200U /*!< BNA interrupt mask */
+
+/******************** Bit definition for USB_OTG_GINTSTS register ***********/
+#define USB_OTG_GINTSTS_CMOD 0x00000001U /*!< Current mode of operation */
+#define USB_OTG_GINTSTS_MMIS 0x00000002U /*!< Mode mismatch interrupt */
+#define USB_OTG_GINTSTS_OTGINT 0x00000004U /*!< OTG interrupt */
+#define USB_OTG_GINTSTS_SOF 0x00000008U /*!< Start of frame */
+#define USB_OTG_GINTSTS_RXFLVL 0x00000010U /*!< RxFIFO nonempty */
+#define USB_OTG_GINTSTS_NPTXFE 0x00000020U /*!< Nonperiodic TxFIFO empty */
+#define USB_OTG_GINTSTS_GINAKEFF 0x00000040U /*!< Global IN nonperiodic NAK effective */
+#define USB_OTG_GINTSTS_BOUTNAKEFF 0x00000080U /*!< Global OUT NAK effective */
+#define USB_OTG_GINTSTS_ESUSP 0x00000400U /*!< Early suspend */
+#define USB_OTG_GINTSTS_USBSUSP 0x00000800U /*!< USB suspend */
+#define USB_OTG_GINTSTS_USBRST 0x00001000U /*!< USB reset */
+#define USB_OTG_GINTSTS_ENUMDNE 0x00002000U /*!< Enumeration done */
+#define USB_OTG_GINTSTS_ISOODRP 0x00004000U /*!< Isochronous OUT packet dropped interrupt */
+#define USB_OTG_GINTSTS_EOPF 0x00008000U /*!< End of periodic frame interrupt */
+#define USB_OTG_GINTSTS_IEPINT 0x00040000U /*!< IN endpoint interrupt */
+#define USB_OTG_GINTSTS_OEPINT 0x00080000U /*!< OUT endpoint interrupt */
+#define USB_OTG_GINTSTS_IISOIXFR 0x00100000U /*!< Incomplete isochronous IN transfer */
+#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT 0x00200000U /*!< Incomplete periodic transfer */
+#define USB_OTG_GINTSTS_DATAFSUSP 0x00400000U /*!< Data fetch suspended */
+#define USB_OTG_GINTSTS_RSTDET 0x00800000U /*!< Reset detected interrupt */
+#define USB_OTG_GINTSTS_HPRTINT 0x01000000U /*!< Host port interrupt */
+#define USB_OTG_GINTSTS_HCINT 0x02000000U /*!< Host channels interrupt */
+#define USB_OTG_GINTSTS_PTXFE 0x04000000U /*!< Periodic TxFIFO empty */
+#define USB_OTG_GINTSTS_LPMINT 0x08000000U /*!< LPM interrupt */
+#define USB_OTG_GINTSTS_CIDSCHG 0x10000000U /*!< Connector ID status change */
+#define USB_OTG_GINTSTS_DISCINT 0x20000000U /*!< Disconnect detected interrupt */
+#define USB_OTG_GINTSTS_SRQINT 0x40000000U /*!< Session request/new session detected interrupt */
+#define USB_OTG_GINTSTS_WKUINT 0x80000000U /*!< Resume/remote wakeup detected interrupt */
+
+/******************** Bit definition for USB_OTG_GINTMSK register ***********/
+#define USB_OTG_GINTMSK_MMISM 0x00000002U /*!< Mode mismatch interrupt mask */
+#define USB_OTG_GINTMSK_OTGINT 0x00000004U /*!< OTG interrupt mask */
+#define USB_OTG_GINTMSK_SOFM 0x00000008U /*!< Start of frame mask */
+#define USB_OTG_GINTMSK_RXFLVLM 0x00000010U /*!< Receive FIFO nonempty mask */
+#define USB_OTG_GINTMSK_NPTXFEM 0x00000020U /*!< Nonperiodic TxFIFO empty mask */
+#define USB_OTG_GINTMSK_GINAKEFFM 0x00000040U /*!< Global nonperiodic IN NAK effective mask */
+#define USB_OTG_GINTMSK_GONAKEFFM 0x00000080U /*!< Global OUT NAK effective mask */
+#define USB_OTG_GINTMSK_ESUSPM 0x00000400U /*!< Early suspend mask */
+#define USB_OTG_GINTMSK_USBSUSPM 0x00000800U /*!< USB suspend mask */
+#define USB_OTG_GINTMSK_USBRST 0x00001000U /*!< USB reset mask */
+#define USB_OTG_GINTMSK_ENUMDNEM 0x00002000U /*!< Enumeration done mask */
+#define USB_OTG_GINTMSK_ISOODRPM 0x00004000U /*!< Isochronous OUT packet dropped interrupt mask */
+#define USB_OTG_GINTMSK_EOPFM 0x00008000U /*!< End of periodic frame interrupt mask */
+#define USB_OTG_GINTMSK_EPMISM 0x00020000U /*!< Endpoint mismatch interrupt mask */
+#define USB_OTG_GINTMSK_IEPINT 0x00040000U /*!< IN endpoints interrupt mask */
+#define USB_OTG_GINTMSK_OEPINT 0x00080000U /*!< OUT endpoints interrupt mask */
+#define USB_OTG_GINTMSK_IISOIXFRM 0x00100000U /*!< Incomplete isochronous IN transfer mask */
+#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM 0x00200000U /*!< Incomplete periodic transfer mask */
+#define USB_OTG_GINTMSK_FSUSPM 0x00400000U /*!< Data fetch suspended mask */
+#define USB_OTG_GINTMSK_RSTDETM 0x00800000U /*!< Reset detected interrupt mask */
+#define USB_OTG_GINTMSK_PRTIM 0x01000000U /*!< Host port interrupt mask */
+#define USB_OTG_GINTMSK_HCIM 0x02000000U /*!< Host channels interrupt mask */
+#define USB_OTG_GINTMSK_PTXFEM 0x04000000U /*!< Periodic TxFIFO empty mask */
+#define USB_OTG_GINTMSK_LPMINTM 0x08000000U /*!< LPM interrupt Mask */
+#define USB_OTG_GINTMSK_CIDSCHGM 0x10000000U /*!< Connector ID status change mask */
+#define USB_OTG_GINTMSK_DISCINT 0x20000000U /*!< Disconnect detected interrupt mask */
+#define USB_OTG_GINTMSK_SRQIM 0x40000000U /*!< Session request/new session detected interrupt mask */
+#define USB_OTG_GINTMSK_WUIM 0x80000000U /*!< Resume/remote wakeup detected interrupt mask */
+
+/******************** Bit definition for USB_OTG_DAINT register *************/
+#define USB_OTG_DAINT_IEPINT 0x0000FFFFU /*!< IN endpoint interrupt bits */
+#define USB_OTG_DAINT_OEPINT 0xFFFF0000U /*!< OUT endpoint interrupt bits */
+
+/******************** Bit definition for USB_OTG_HAINTMSK register **********/
+#define USB_OTG_HAINTMSK_HAINTM 0x0000FFFFU /*!< Channel interrupt mask */
+
+/******************** Bit definition for USB_OTG_GRXSTSP register ***********/
+#define USB_OTG_GRXSTSP_EPNUM 0x0000000FU /*!< IN EP interrupt mask bits */
+#define USB_OTG_GRXSTSP_BCNT 0x00007FF0U /*!< OUT EP interrupt mask bits */
+#define USB_OTG_GRXSTSP_DPID 0x00018000U /*!< OUT EP interrupt mask bits */
+#define USB_OTG_GRXSTSP_PKTSTS 0x001E0000U /*!< OUT EP interrupt mask bits */
+
+/******************** Bit definition for USB_OTG_DAINTMSK register **********/
+#define USB_OTG_DAINTMSK_IEPM 0x0000FFFFU /*!< IN EP interrupt mask bits */
+#define USB_OTG_DAINTMSK_OEPM 0xFFFF0000U /*!< OUT EP interrupt mask bits */
+
+/******************** Bit definition for OTG register ***********************/
+
+#define USB_OTG_CHNUM 0x0000000FU /*!< Channel number */
+#define USB_OTG_CHNUM_0 0x00000001U /*!<Bit 0 */
+#define USB_OTG_CHNUM_1 0x00000002U /*!<Bit 1 */
+#define USB_OTG_CHNUM_2 0x00000004U /*!<Bit 2 */
+#define USB_OTG_CHNUM_3 0x00000008U /*!<Bit 3 */
+#define USB_OTG_BCNT 0x00007FF0U /*!< Byte count */
+
+#define USB_OTG_DPID 0x00018000U /*!< Data PID */
+#define USB_OTG_DPID_0 0x00008000U /*!<Bit 0 */
+#define USB_OTG_DPID_1 0x00010000U /*!<Bit 1 */
+
+#define USB_OTG_PKTSTS 0x001E0000U /*!< Packet status */
+#define USB_OTG_PKTSTS_0 0x00020000U /*!<Bit 0 */
+#define USB_OTG_PKTSTS_1 0x00040000U /*!<Bit 1 */
+#define USB_OTG_PKTSTS_2 0x00080000U /*!<Bit 2 */
+#define USB_OTG_PKTSTS_3 0x00100000U /*!<Bit 3 */
+
+#define USB_OTG_EPNUM 0x0000000FU /*!< Endpoint number */
+#define USB_OTG_EPNUM_0 0x00000001U /*!<Bit 0 */
+#define USB_OTG_EPNUM_1 0x00000002U /*!<Bit 1 */
+#define USB_OTG_EPNUM_2 0x00000004U /*!<Bit 2 */
+#define USB_OTG_EPNUM_3 0x00000008U /*!<Bit 3 */
+
+#define USB_OTG_FRMNUM 0x01E00000U /*!< Frame number */
+#define USB_OTG_FRMNUM_0 0x00200000U /*!<Bit 0 */
+#define USB_OTG_FRMNUM_1 0x00400000U /*!<Bit 1 */
+#define USB_OTG_FRMNUM_2 0x00800000U /*!<Bit 2 */
+#define USB_OTG_FRMNUM_3 0x01000000U /*!<Bit 3 */
+
+/******************** Bit definition for OTG register ***********************/
+#define USB_OTG_CHNUM 0x0000000FU /*!< Channel number */
+#define USB_OTG_CHNUM_0 0x00000001U /*!<Bit 0 */
+#define USB_OTG_CHNUM_1 0x00000002U /*!<Bit 1 */
+#define USB_OTG_CHNUM_2 0x00000004U /*!<Bit 2 */
+#define USB_OTG_CHNUM_3 0x00000008U /*!<Bit 3 */
+#define USB_OTG_BCNT 0x00007FF0U /*!< Byte count */
+
+#define USB_OTG_DPID 0x00018000U /*!< Data PID */
+#define USB_OTG_DPID_0 0x00008000U /*!<Bit 0 */
+#define USB_OTG_DPID_1 0x00010000U /*!<Bit 1 */
+
+#define USB_OTG_PKTSTS 0x001E0000U /*!< Packet status */
+#define USB_OTG_PKTSTS_0 0x00020000U /*!<Bit 0 */
+#define USB_OTG_PKTSTS_1 0x00040000U /*!<Bit 1 */
+#define USB_OTG_PKTSTS_2 0x00080000U /*!<Bit 2 */
+#define USB_OTG_PKTSTS_3 0x00100000U /*!<Bit 3 */
+
+#define USB_OTG_EPNUM 0x0000000FU /*!< Endpoint number */
+#define USB_OTG_EPNUM_0 0x00000001U /*!<Bit 0 */
+#define USB_OTG_EPNUM_1 0x00000002U /*!<Bit 1 */
+#define USB_OTG_EPNUM_2 0x00000004U /*!<Bit 2 */
+#define USB_OTG_EPNUM_3 0x00000008U /*!<Bit 3 */
+
+#define USB_OTG_FRMNUM 0x01E00000U /*!< Frame number */
+#define USB_OTG_FRMNUM_0 0x00200000U /*!<Bit 0 */
+#define USB_OTG_FRMNUM_1 0x00400000U /*!<Bit 1 */
+#define USB_OTG_FRMNUM_2 0x00800000U /*!<Bit 2 */
+#define USB_OTG_FRMNUM_3 0x01000000U /*!<Bit 3 */
+
+/******************** Bit definition for USB_OTG_GRXFSIZ register ***********/
+#define USB_OTG_GRXFSIZ_RXFD 0x0000FFFFU /*!< RxFIFO depth */
+
+/******************** Bit definition for USB_OTG_DVBUSDIS register **********/
+#define USB_OTG_DVBUSDIS_VBUSDT 0x0000FFFFU /*!< Device VBUS discharge time */
+
+/******************** Bit definition for OTG register ***********************/
+#define USB_OTG_NPTXFSA 0x0000FFFFU /*!< Nonperiodic transmit RAM start address */
+#define USB_OTG_NPTXFD 0xFFFF0000U /*!< Nonperiodic TxFIFO depth */
+#define USB_OTG_TX0FSA 0x0000FFFFU /*!< Endpoint 0 transmit RAM start address */
+#define USB_OTG_TX0FD 0xFFFF0000U /*!< Endpoint 0 TxFIFO depth */
+
+/******************** Bit definition for USB_OTG_DVBUSPULSE register ********/
+#define USB_OTG_DVBUSPULSE_DVBUSP 0x00000FFFU /*!< Device VBUS pulsing time */
+
+/******************** Bit definition for USB_OTG_GNPTXSTS register **********/
+#define USB_OTG_GNPTXSTS_NPTXFSAV 0x0000FFFFU /*!< Nonperiodic TxFIFO space available */
+
+#define USB_OTG_GNPTXSTS_NPTQXSAV 0x00FF0000U /*!< Nonperiodic transmit request queue space available */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_0 0x00010000U /*!<Bit 0 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_1 0x00020000U /*!<Bit 1 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_2 0x00040000U /*!<Bit 2 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_3 0x00080000U /*!<Bit 3 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_4 0x00100000U /*!<Bit 4 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_5 0x00200000U /*!<Bit 5 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_6 0x00400000U /*!<Bit 6 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_7 0x00800000U /*!<Bit 7 */
+
+#define USB_OTG_GNPTXSTS_NPTXQTOP 0x7F000000U /*!< Top of the nonperiodic transmit request queue */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_0 0x01000000U /*!<Bit 0 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_1 0x02000000U /*!<Bit 1 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_2 0x04000000U /*!<Bit 2 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_3 0x08000000U /*!<Bit 3 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_4 0x10000000U /*!<Bit 4 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_5 0x20000000U /*!<Bit 5 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_6 0x40000000U /*!<Bit 6 */
+
+/******************** Bit definition for USB_OTG_DTHRCTL register ***********/
+#define USB_OTG_DTHRCTL_NONISOTHREN 0x00000001U /*!< Nonisochronous IN endpoints threshold enable */
+#define USB_OTG_DTHRCTL_ISOTHREN 0x00000002U /*!< ISO IN endpoint threshold enable */
+
+#define USB_OTG_DTHRCTL_TXTHRLEN 0x000007FCU /*!< Transmit threshold length */
+#define USB_OTG_DTHRCTL_TXTHRLEN_0 0x00000004U /*!<Bit 0 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_1 0x00000008U /*!<Bit 1 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_2 0x00000010U /*!<Bit 2 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_3 0x00000020U /*!<Bit 3 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_4 0x00000040U /*!<Bit 4 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_5 0x00000080U /*!<Bit 5 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_6 0x00000100U /*!<Bit 6 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_7 0x00000200U /*!<Bit 7 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_8 0x00000400U /*!<Bit 8 */
+#define USB_OTG_DTHRCTL_RXTHREN 0x00010000U /*!< Receive threshold enable */
+
+#define USB_OTG_DTHRCTL_RXTHRLEN 0x03FE0000U /*!< Receive threshold length */
+#define USB_OTG_DTHRCTL_RXTHRLEN_0 0x00020000U /*!<Bit 0 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_1 0x00040000U /*!<Bit 1 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_2 0x00080000U /*!<Bit 2 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_3 0x00100000U /*!<Bit 3 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_4 0x00200000U /*!<Bit 4 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_5 0x00400000U /*!<Bit 5 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_6 0x00800000U /*!<Bit 6 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_7 0x01000000U /*!<Bit 7 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_8 0x02000000U /*!<Bit 8 */
+#define USB_OTG_DTHRCTL_ARPEN 0x08000000U /*!< Arbiter parking enable */
+
+/******************** Bit definition for USB_OTG_DIEPEMPMSK register ********/
+#define USB_OTG_DIEPEMPMSK_INEPTXFEM 0x0000FFFFU /*!< IN EP Tx FIFO empty interrupt mask bits */
+
+/******************** Bit definition for USB_OTG_DEACHINT register **********/
+#define USB_OTG_DEACHINT_IEP1INT 0x00000002U /*!< IN endpoint 1interrupt bit */
+#define USB_OTG_DEACHINT_OEP1INT 0x00020000U /*!< OUT endpoint 1 interrupt bit */
+
+/******************** Bit definition for USB_OTG_GCCFG register *************/
+#define USB_OTG_GCCFG_DCDET 0x00000001U /*!< Data contact detection (DCD) status */
+#define USB_OTG_GCCFG_PDET 0x00000002U /*!< Primary detection (PD) status */
+#define USB_OTG_GCCFG_SDET 0x00000004U /*!< Secondary detection (SD) status */
+#define USB_OTG_GCCFG_PS2DET 0x00000008U /*!< DM pull-up detection status */
+#define USB_OTG_GCCFG_PWRDWN 0x00010000U /*!< Power down */
+#define USB_OTG_GCCFG_BCDEN 0x00020000U /*!< Battery charging detector (BCD) enable */
+#define USB_OTG_GCCFG_DCDEN 0x00040000U /*!< Data contact detection (DCD) mode enable*/
+#define USB_OTG_GCCFG_PDEN 0x00080000U /*!< Primary detection (PD) mode enable*/
+#define USB_OTG_GCCFG_SDEN 0x00100000U /*!< Secondary detection (SD) mode enable */
+#define USB_OTG_GCCFG_VBDEN 0x00200000U /*!< USB VBUS Detection Enable */
+
+/******************** Bit definition for USB_OTG_DEACHINTMSK register *******/
+#define USB_OTG_DEACHINTMSK_IEP1INTM 0x00000002U /*!< IN Endpoint 1 interrupt mask bit */
+#define USB_OTG_DEACHINTMSK_OEP1INTM 0x00020000U /*!< OUT Endpoint 1 interrupt mask bit */
+
+/******************** Bit definition for USB_OTG_CID register ***************/
+#define USB_OTG_CID_PRODUCT_ID 0xFFFFFFFFU /*!< Product ID field */
+
+/******************** Bit definition for USB_OTG_GLPMCFG register ***********/
+#define USB_OTG_GLPMCFG_LPMEN 0x00000001U /*!< LPM support enable */
+#define USB_OTG_GLPMCFG_LPMACK 0x00000002U /*!< LPM Token acknowledge enable */
+#define USB_OTG_GLPMCFG_BESL 0x0000003CU /*!< BESL value received with last ACKed LPM Token */
+#define USB_OTG_GLPMCFG_REMWAKE 0x00000040U /*!< bRemoteWake value received with last ACKed LPM Token */
+#define USB_OTG_GLPMCFG_L1SSEN 0x00000080U /*!< L1 shallow sleep enable */
+#define USB_OTG_GLPMCFG_BESLTHRS 0x00000F00U /*!< BESL threshold */
+#define USB_OTG_GLPMCFG_L1DSEN 0x00001000U /*!< L1 deep sleep enable */
+#define USB_OTG_GLPMCFG_LPMRSP 0x00006000U /*!< LPM response */
+#define USB_OTG_GLPMCFG_SLPSTS 0x00008000U /*!< Port sleep status */
+#define USB_OTG_GLPMCFG_L1RSMOK 0x00010000U /*!< Sleep State Resume OK */
+#define USB_OTG_GLPMCFG_LPMCHIDX 0x001E0000U /*!< LPM Channel Index */
+#define USB_OTG_GLPMCFG_LPMRCNT 0x00E00000U /*!< LPM retry count */
+#define USB_OTG_GLPMCFG_SNDLPM 0x01000000U /*!< Send LPM transaction */
+#define USB_OTG_GLPMCFG_LPMRCNTSTS 0x0E000000U /*!< LPM retry count status */
+#define USB_OTG_GLPMCFG_ENBESL 0x10000000U /*!< Enable best effort service latency */
+
+/******************** Bit definition for USB_OTG_DIEPEACHMSK1 register ******/
+#define USB_OTG_DIEPEACHMSK1_XFRCM 0x00000001U /*!< Transfer completed interrupt mask */
+#define USB_OTG_DIEPEACHMSK1_EPDM 0x00000002U /*!< Endpoint disabled interrupt mask */
+#define USB_OTG_DIEPEACHMSK1_TOM 0x00000008U /*!< Timeout condition mask (nonisochronous endpoints) */
+#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK 0x00000010U /*!< IN token received when TxFIFO empty mask */
+#define USB_OTG_DIEPEACHMSK1_INEPNMM 0x00000020U /*!< IN token received with EP mismatch mask */
+#define USB_OTG_DIEPEACHMSK1_INEPNEM 0x00000040U /*!< IN endpoint NAK effective mask */
+#define USB_OTG_DIEPEACHMSK1_TXFURM 0x00000100U /*!< FIFO underrun mask */
+#define USB_OTG_DIEPEACHMSK1_BIM 0x00000200U /*!< BNA interrupt mask */
+#define USB_OTG_DIEPEACHMSK1_NAKM 0x00002000U /*!< NAK interrupt mask */
+
+/******************** Bit definition for USB_OTG_HPRT register **************/
+#define USB_OTG_HPRT_PCSTS 0x00000001U /*!< Port connect status */
+#define USB_OTG_HPRT_PCDET 0x00000002U /*!< Port connect detected */
+#define USB_OTG_HPRT_PENA 0x00000004U /*!< Port enable */
+#define USB_OTG_HPRT_PENCHNG 0x00000008U /*!< Port enable/disable change */
+#define USB_OTG_HPRT_POCA 0x00000010U /*!< Port overcurrent active */
+#define USB_OTG_HPRT_POCCHNG 0x00000020U /*!< Port overcurrent change */
+#define USB_OTG_HPRT_PRES 0x00000040U /*!< Port resume */
+#define USB_OTG_HPRT_PSUSP 0x00000080U /*!< Port suspend */
+#define USB_OTG_HPRT_PRST 0x00000100U /*!< Port reset */
+
+#define USB_OTG_HPRT_PLSTS 0x00000C00U /*!< Port line status */
+#define USB_OTG_HPRT_PLSTS_0 0x00000400U /*!<Bit 0 */
+#define USB_OTG_HPRT_PLSTS_1 0x00000800U /*!<Bit 1 */
+#define USB_OTG_HPRT_PPWR 0x00001000U /*!< Port power */
+
+#define USB_OTG_HPRT_PTCTL 0x0001E000U /*!< Port test control */
+#define USB_OTG_HPRT_PTCTL_0 0x00002000U /*!<Bit 0 */
+#define USB_OTG_HPRT_PTCTL_1 0x00004000U /*!<Bit 1 */
+#define USB_OTG_HPRT_PTCTL_2 0x00008000U /*!<Bit 2 */
+#define USB_OTG_HPRT_PTCTL_3 0x00010000U /*!<Bit 3 */
+
+#define USB_OTG_HPRT_PSPD 0x00060000U /*!< Port speed */
+#define USB_OTG_HPRT_PSPD_0 0x00020000U /*!<Bit 0 */
+#define USB_OTG_HPRT_PSPD_1 0x00040000U /*!<Bit 1 */
+
+/******************** Bit definition for USB_OTG_DOEPEACHMSK1 register ******/
+#define USB_OTG_DOEPEACHMSK1_XFRCM 0x00000001U /*!< Transfer completed interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_EPDM 0x00000002U /*!< Endpoint disabled interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_TOM 0x00000008U /*!< Timeout condition mask */
+#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK 0x00000010U /*!< IN token received when TxFIFO empty mask */
+#define USB_OTG_DOEPEACHMSK1_INEPNMM 0x00000020U /*!< IN token received with EP mismatch mask */
+#define USB_OTG_DOEPEACHMSK1_INEPNEM 0x00000040U /*!< IN endpoint NAK effective mask */
+#define USB_OTG_DOEPEACHMSK1_TXFURM 0x00000100U /*!< OUT packet error mask */
+#define USB_OTG_DOEPEACHMSK1_BIM 0x00000200U /*!< BNA interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_BERRM 0x00001000U /*!< Bubble error interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_NAKM 0x00002000U /*!< NAK interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_NYETM 0x00004000U /*!< NYET interrupt mask */
+
+/******************** Bit definition for USB_OTG_HPTXFSIZ register **********/
+#define USB_OTG_HPTXFSIZ_PTXSA 0x0000FFFFU /*!< Host periodic TxFIFO start address */
+#define USB_OTG_HPTXFSIZ_PTXFD 0xFFFF0000U /*!< Host periodic TxFIFO depth */
+
+/******************** Bit definition for USB_OTG_DIEPCTL register ***********/
+#define USB_OTG_DIEPCTL_MPSIZ 0x000007FFU /*!< Maximum packet size */
+#define USB_OTG_DIEPCTL_USBAEP 0x00008000U /*!< USB active endpoint */
+#define USB_OTG_DIEPCTL_EONUM_DPID 0x00010000U /*!< Even/odd frame */
+#define USB_OTG_DIEPCTL_NAKSTS 0x00020000U /*!< NAK status */
+
+#define USB_OTG_DIEPCTL_EPTYP 0x000C0000U /*!< Endpoint type */
+#define USB_OTG_DIEPCTL_EPTYP_0 0x00040000U /*!<Bit 0 */
+#define USB_OTG_DIEPCTL_EPTYP_1 0x00080000U /*!<Bit 1 */
+#define USB_OTG_DIEPCTL_STALL 0x00200000U /*!< STALL handshake */
+
+#define USB_OTG_DIEPCTL_TXFNUM 0x03C00000U /*!< TxFIFO number */
+#define USB_OTG_DIEPCTL_TXFNUM_0 0x00400000U /*!<Bit 0 */
+#define USB_OTG_DIEPCTL_TXFNUM_1 0x00800000U /*!<Bit 1 */
+#define USB_OTG_DIEPCTL_TXFNUM_2 0x01000000U /*!<Bit 2 */
+#define USB_OTG_DIEPCTL_TXFNUM_3 0x02000000U /*!<Bit 3 */
+#define USB_OTG_DIEPCTL_CNAK 0x04000000U /*!< Clear NAK */
+#define USB_OTG_DIEPCTL_SNAK 0x08000000U /*!< Set NAK */
+#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM 0x10000000U /*!< Set DATA0 PID */
+#define USB_OTG_DIEPCTL_SODDFRM 0x20000000U /*!< Set odd frame */
+#define USB_OTG_DIEPCTL_EPDIS 0x40000000U /*!< Endpoint disable */
+#define USB_OTG_DIEPCTL_EPENA 0x80000000U /*!< Endpoint enable */
+
+/******************** Bit definition for USB_OTG_HCCHAR register ************/
+#define USB_OTG_HCCHAR_MPSIZ 0x000007FFU /*!< Maximum packet size */
+
+#define USB_OTG_HCCHAR_EPNUM 0x00007800U /*!< Endpoint number */
+#define USB_OTG_HCCHAR_EPNUM_0 0x00000800U /*!<Bit 0 */
+#define USB_OTG_HCCHAR_EPNUM_1 0x00001000U /*!<Bit 1 */
+#define USB_OTG_HCCHAR_EPNUM_2 0x00002000U /*!<Bit 2 */
+#define USB_OTG_HCCHAR_EPNUM_3 0x00004000U /*!<Bit 3 */
+#define USB_OTG_HCCHAR_EPDIR 0x00008000U /*!< Endpoint direction */
+#define USB_OTG_HCCHAR_LSDEV 0x00020000U /*!< Low-speed device */
+
+#define USB_OTG_HCCHAR_EPTYP 0x000C0000U /*!< Endpoint type */
+#define USB_OTG_HCCHAR_EPTYP_0 0x00040000U /*!<Bit 0 */
+#define USB_OTG_HCCHAR_EPTYP_1 0x00080000U /*!<Bit 1 */
+
+#define USB_OTG_HCCHAR_MC 0x00300000U /*!< Multi Count (MC) / Error Count (EC) */
+#define USB_OTG_HCCHAR_MC_0 0x00100000U /*!<Bit 0 */
+#define USB_OTG_HCCHAR_MC_1 0x00200000U /*!<Bit 1 */
+
+#define USB_OTG_HCCHAR_DAD 0x1FC00000U /*!< Device address */
+#define USB_OTG_HCCHAR_DAD_0 0x00400000U /*!<Bit 0 */
+#define USB_OTG_HCCHAR_DAD_1 0x00800000U /*!<Bit 1 */
+#define USB_OTG_HCCHAR_DAD_2 0x01000000U /*!<Bit 2 */
+#define USB_OTG_HCCHAR_DAD_3 0x02000000U /*!<Bit 3 */
+#define USB_OTG_HCCHAR_DAD_4 0x04000000U /*!<Bit 4 */
+#define USB_OTG_HCCHAR_DAD_5 0x08000000U /*!<Bit 5 */
+#define USB_OTG_HCCHAR_DAD_6 0x10000000U /*!<Bit 6 */
+#define USB_OTG_HCCHAR_ODDFRM 0x20000000U /*!< Odd frame */
+#define USB_OTG_HCCHAR_CHDIS 0x40000000U /*!< Channel disable */
+#define USB_OTG_HCCHAR_CHENA 0x80000000U /*!< Channel enable */
+
+/******************** Bit definition for USB_OTG_HCSPLT register ************/
+
+#define USB_OTG_HCSPLT_PRTADDR 0x0000007FU /*!< Port address */
+#define USB_OTG_HCSPLT_PRTADDR_0 0x00000001U /*!<Bit 0 */
+#define USB_OTG_HCSPLT_PRTADDR_1 0x00000002U /*!<Bit 1 */
+#define USB_OTG_HCSPLT_PRTADDR_2 0x00000004U /*!<Bit 2 */
+#define USB_OTG_HCSPLT_PRTADDR_3 0x00000008U /*!<Bit 3 */
+#define USB_OTG_HCSPLT_PRTADDR_4 0x00000010U /*!<Bit 4 */
+#define USB_OTG_HCSPLT_PRTADDR_5 0x00000020U /*!<Bit 5 */
+#define USB_OTG_HCSPLT_PRTADDR_6 0x00000040U /*!<Bit 6 */
+
+#define USB_OTG_HCSPLT_HUBADDR 0x00003F80U /*!< Hub address */
+#define USB_OTG_HCSPLT_HUBADDR_0 0x00000080U /*!<Bit 0 */
+#define USB_OTG_HCSPLT_HUBADDR_1 0x00000100U /*!<Bit 1 */
+#define USB_OTG_HCSPLT_HUBADDR_2 0x00000200U /*!<Bit 2 */
+#define USB_OTG_HCSPLT_HUBADDR_3 0x00000400U /*!<Bit 3 */
+#define USB_OTG_HCSPLT_HUBADDR_4 0x00000800U /*!<Bit 4 */
+#define USB_OTG_HCSPLT_HUBADDR_5 0x00001000U /*!<Bit 5 */
+#define USB_OTG_HCSPLT_HUBADDR_6 0x00002000U /*!<Bit 6 */
+
+#define USB_OTG_HCSPLT_XACTPOS 0x0000C000U /*!< XACTPOS */
+#define USB_OTG_HCSPLT_XACTPOS_0 0x00004000U /*!<Bit 0 */
+#define USB_OTG_HCSPLT_XACTPOS_1 0x00008000U /*!<Bit 1 */
+#define USB_OTG_HCSPLT_COMPLSPLT 0x00010000U /*!< Do complete split */
+#define USB_OTG_HCSPLT_SPLITEN 0x80000000U /*!< Split enable */
+
+/******************** Bit definition for USB_OTG_HCINT register *************/
+#define USB_OTG_HCINT_XFRC 0x00000001U /*!< Transfer completed */
+#define USB_OTG_HCINT_CHH 0x00000002U /*!< Channel halted */
+#define USB_OTG_HCINT_AHBERR 0x00000004U /*!< AHB error */
+#define USB_OTG_HCINT_STALL 0x00000008U /*!< STALL response received interrupt */
+#define USB_OTG_HCINT_NAK 0x00000010U /*!< NAK response received interrupt */
+#define USB_OTG_HCINT_ACK 0x00000020U /*!< ACK response received/transmitted interrupt */
+#define USB_OTG_HCINT_NYET 0x00000040U /*!< Response received interrupt */
+#define USB_OTG_HCINT_TXERR 0x00000080U /*!< Transaction error */
+#define USB_OTG_HCINT_BBERR 0x00000100U /*!< Babble error */
+#define USB_OTG_HCINT_FRMOR 0x00000200U /*!< Frame overrun */
+#define USB_OTG_HCINT_DTERR 0x00000400U /*!< Data toggle error */
+
+/******************** Bit definition for USB_OTG_DIEPINT register ***********/
+#define USB_OTG_DIEPINT_XFRC 0x00000001U /*!< Transfer completed interrupt */
+#define USB_OTG_DIEPINT_EPDISD 0x00000002U /*!< Endpoint disabled interrupt */
+#define USB_OTG_DIEPINT_TOC 0x00000008U /*!< Timeout condition */
+#define USB_OTG_DIEPINT_ITTXFE 0x00000010U /*!< IN token received when TxFIFO is empty */
+#define USB_OTG_DIEPINT_INEPNE 0x00000040U /*!< IN endpoint NAK effective */
+#define USB_OTG_DIEPINT_TXFE 0x00000080U /*!< Transmit FIFO empty */
+#define USB_OTG_DIEPINT_TXFIFOUDRN 0x00000100U /*!< Transmit Fifo Underrun */
+#define USB_OTG_DIEPINT_BNA 0x00000200U /*!< Buffer not available interrupt */
+#define USB_OTG_DIEPINT_PKTDRPSTS 0x00000800U /*!< Packet dropped status */
+#define USB_OTG_DIEPINT_BERR 0x00001000U /*!< Babble error interrupt */
+#define USB_OTG_DIEPINT_NAK 0x00002000U /*!< NAK interrupt */
+
+/******************** Bit definition for USB_OTG_HCINTMSK register **********/
+#define USB_OTG_HCINTMSK_XFRCM 0x00000001U /*!< Transfer completed mask */
+#define USB_OTG_HCINTMSK_CHHM 0x00000002U /*!< Channel halted mask */
+#define USB_OTG_HCINTMSK_AHBERR 0x00000004U /*!< AHB error */
+#define USB_OTG_HCINTMSK_STALLM 0x00000008U /*!< STALL response received interrupt mask */
+#define USB_OTG_HCINTMSK_NAKM 0x00000010U /*!< NAK response received interrupt mask */
+#define USB_OTG_HCINTMSK_ACKM 0x00000020U /*!< ACK response received/transmitted interrupt mask */
+#define USB_OTG_HCINTMSK_NYET 0x00000040U /*!< response received interrupt mask */
+#define USB_OTG_HCINTMSK_TXERRM 0x00000080U /*!< Transaction error mask */
+#define USB_OTG_HCINTMSK_BBERRM 0x00000100U /*!< Babble error mask */
+#define USB_OTG_HCINTMSK_FRMORM 0x00000200U /*!< Frame overrun mask */
+#define USB_OTG_HCINTMSK_DTERRM 0x00000400U /*!< Data toggle error mask */
+
+/******************** Bit definition for USB_OTG_DIEPTSIZ register **********/
+
+#define USB_OTG_DIEPTSIZ_XFRSIZ 0x0007FFFFU /*!< Transfer size */
+#define USB_OTG_DIEPTSIZ_PKTCNT 0x1FF80000U /*!< Packet count */
+#define USB_OTG_DIEPTSIZ_MULCNT 0x60000000U /*!< Packet count */
+/******************** Bit definition for USB_OTG_HCTSIZ register ************/
+#define USB_OTG_HCTSIZ_XFRSIZ 0x0007FFFFU /*!< Transfer size */
+#define USB_OTG_HCTSIZ_PKTCNT 0x1FF80000U /*!< Packet count */
+#define USB_OTG_HCTSIZ_DOPING 0x80000000U /*!< Do PING */
+#define USB_OTG_HCTSIZ_DPID 0x60000000U /*!< Data PID */
+#define USB_OTG_HCTSIZ_DPID_0 0x20000000U /*!<Bit 0 */
+#define USB_OTG_HCTSIZ_DPID_1 0x40000000U /*!<Bit 1 */
+
+/******************** Bit definition for USB_OTG_DIEPDMA register ***********/
+#define USB_OTG_DIEPDMA_DMAADDR 0xFFFFFFFFU /*!< DMA address */
+
+/******************** Bit definition for USB_OTG_HCDMA register *************/
+#define USB_OTG_HCDMA_DMAADDR 0xFFFFFFFFU /*!< DMA address */
+
+/******************** Bit definition for USB_OTG_DTXFSTS register ***********/
+#define USB_OTG_DTXFSTS_INEPTFSAV 0x0000FFFFU /*!< IN endpoint TxFIFO space available */
+
+/******************** Bit definition for USB_OTG_DIEPTXF register ***********/
+#define USB_OTG_DIEPTXF_INEPTXSA 0x0000FFFFU /*!< IN endpoint FIFOx transmit RAM start address */
+#define USB_OTG_DIEPTXF_INEPTXFD 0xFFFF0000U /*!< IN endpoint TxFIFO depth */
+
+/******************** Bit definition for USB_OTG_DOEPCTL register ***********/
+
+#define USB_OTG_DOEPCTL_MPSIZ 0x000007FFU /*!< Maximum packet size */ /*!<Bit 1 */
+#define USB_OTG_DOEPCTL_USBAEP 0x00008000U /*!< USB active endpoint */
+#define USB_OTG_DOEPCTL_NAKSTS 0x00020000U /*!< NAK status */
+#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM 0x10000000U /*!< Set DATA0 PID */
+#define USB_OTG_DOEPCTL_SODDFRM 0x20000000U /*!< Set odd frame */
+#define USB_OTG_DOEPCTL_EPTYP 0x000C0000U /*!< Endpoint type */
+#define USB_OTG_DOEPCTL_EPTYP_0 0x00040000U /*!<Bit 0 */
+#define USB_OTG_DOEPCTL_EPTYP_1 0x00080000U /*!<Bit 1 */
+#define USB_OTG_DOEPCTL_SNPM 0x00100000U /*!< Snoop mode */
+#define USB_OTG_DOEPCTL_STALL 0x00200000U /*!< STALL handshake */
+#define USB_OTG_DOEPCTL_CNAK 0x04000000U /*!< Clear NAK */
+#define USB_OTG_DOEPCTL_SNAK 0x08000000U /*!< Set NAK */
+#define USB_OTG_DOEPCTL_EPDIS 0x40000000U /*!< Endpoint disable */
+#define USB_OTG_DOEPCTL_EPENA 0x80000000U /*!< Endpoint enable */
+
+/******************** Bit definition for USB_OTG_DOEPINT register ***********/
+#define USB_OTG_DOEPINT_XFRC 0x00000001U /*!< Transfer completed interrupt */
+#define USB_OTG_DOEPINT_EPDISD 0x00000002U /*!< Endpoint disabled interrupt */
+#define USB_OTG_DOEPINT_STUP 0x00000008U /*!< SETUP phase done */
+#define USB_OTG_DOEPINT_OTEPDIS 0x00000010U /*!< OUT token received when endpoint disabled */
+#define USB_OTG_DOEPINT_OTEPSPR 0x00000020U /*!< Status Phase Received For Control Write */
+#define USB_OTG_DOEPINT_B2BSTUP 0x00000040U /*!< Back-to-back SETUP packets received */
+#define USB_OTG_DOEPINT_NYET 0x00004000U /*!< NYET interrupt */
+
+/******************** Bit definition for USB_OTG_DOEPTSIZ register **********/
+
+#define USB_OTG_DOEPTSIZ_XFRSIZ 0x0007FFFFU /*!< Transfer size */
+#define USB_OTG_DOEPTSIZ_PKTCNT 0x1FF80000U /*!< Packet count */
+
+#define USB_OTG_DOEPTSIZ_STUPCNT 0x60000000U /*!< SETUP packet count */
+#define USB_OTG_DOEPTSIZ_STUPCNT_0 0x20000000U /*!<Bit 0 */
+#define USB_OTG_DOEPTSIZ_STUPCNT_1 0x40000000U /*!<Bit 1 */
+
+/******************** Bit definition for PCGCCTL register *******************/
+#define USB_OTG_PCGCCTL_STOPCLK 0x00000001U /*!< SETUP packet count */
+#define USB_OTG_PCGCCTL_GATECLK 0x00000002U /*!<Bit 0 */
+#define USB_OTG_PCGCCTL_PHYSUSP 0x00000010U /*!<Bit 1 */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup Exported_macros
+ * @{
+ */
+
+/******************************* ADC Instances ********************************/
+#define IS_ADC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
+
+/******************************* CAN Instances ********************************/
+#define IS_CAN_ALL_INSTANCE(INSTANCE) (((INSTANCE) == CAN1) || \
+ ((INSTANCE) == CAN2))
+/****************************** DFSDM Instances *******************************/
+#define IS_DFSDM_FILTER_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DFSDM1_Filter0) || \
+ ((INSTANCE) == DFSDM1_Filter1))
+
+#define IS_DFSDM_CHANNEL_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DFSDM1_Channel0) || \
+ ((INSTANCE) == DFSDM1_Channel1) || \
+ ((INSTANCE) == DFSDM1_Channel2) || \
+ ((INSTANCE) == DFSDM1_Channel3))
+
+/******************************* CRC Instances ********************************/
+#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
+
+/******************************** DMA Instances *******************************/
+#define IS_DMA_STREAM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0) || \
+ ((INSTANCE) == DMA1_Stream1) || \
+ ((INSTANCE) == DMA1_Stream2) || \
+ ((INSTANCE) == DMA1_Stream3) || \
+ ((INSTANCE) == DMA1_Stream4) || \
+ ((INSTANCE) == DMA1_Stream5) || \
+ ((INSTANCE) == DMA1_Stream6) || \
+ ((INSTANCE) == DMA1_Stream7) || \
+ ((INSTANCE) == DMA2_Stream0) || \
+ ((INSTANCE) == DMA2_Stream1) || \
+ ((INSTANCE) == DMA2_Stream2) || \
+ ((INSTANCE) == DMA2_Stream3) || \
+ ((INSTANCE) == DMA2_Stream4) || \
+ ((INSTANCE) == DMA2_Stream5) || \
+ ((INSTANCE) == DMA2_Stream6) || \
+ ((INSTANCE) == DMA2_Stream7))
+
+/******************************* GPIO Instances *******************************/
+#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
+ ((INSTANCE) == GPIOB) || \
+ ((INSTANCE) == GPIOC) || \
+ ((INSTANCE) == GPIOD) || \
+ ((INSTANCE) == GPIOE) || \
+ ((INSTANCE) == GPIOF) || \
+ ((INSTANCE) == GPIOG) || \
+ ((INSTANCE) == GPIOH))
+
+/******************************** I2C Instances *******************************/
+#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
+ ((INSTANCE) == I2C2) || \
+ ((INSTANCE) == I2C3))
+
+/******************************** I2S Instances *******************************/
+#define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
+ ((INSTANCE) == SPI2) || \
+ ((INSTANCE) == SPI3) || \
+ ((INSTANCE) == SPI4) || \
+ ((INSTANCE) == SPI5))
+
+/*************************** I2S Extended Instances ***************************/
+#define IS_I2S_ALL_INSTANCE_EXT(PERIPH) (((INSTANCE) == SPI2) || \
+ ((INSTANCE) == SPI3) || \
+ ((INSTANCE) == I2S2ext) || \
+ ((INSTANCE) == I2S3ext))
+
+/******************************* RNG Instances ********************************/
+#define IS_RNG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RNG)
+
+/****************************** RTC Instances *********************************/
+#define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
+
+/******************************** SPI Instances *******************************/
+#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
+ ((INSTANCE) == SPI2) || \
+ ((INSTANCE) == SPI3) || \
+ ((INSTANCE) == SPI4) || \
+ ((INSTANCE) == SPI5))
+/*************************** SPI Extended Instances ***************************/
+#define IS_SPI_ALL_INSTANCE_EXT(INSTANCE) (((INSTANCE) == SPI1) || \
+ ((INSTANCE) == SPI2) || \
+ ((INSTANCE) == SPI3) || \
+ ((INSTANCE) == SPI4) || \
+ ((INSTANCE) == SPI5) || \
+ ((INSTANCE) == I2S2ext) || \
+ ((INSTANCE) == I2S3ext))
+
+/****************** TIM Instances : All supported instances *******************/
+#define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM6) || \
+ ((INSTANCE) == TIM7) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM9) || \
+ ((INSTANCE) == TIM10) || \
+ ((INSTANCE) == TIM11) || \
+ ((INSTANCE) == TIM12) || \
+ ((INSTANCE) == TIM13) || \
+ ((INSTANCE) == TIM14))
+
+/************* TIM Instances : at least 1 capture/compare channel *************/
+#define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM9) || \
+ ((INSTANCE) == TIM10) || \
+ ((INSTANCE) == TIM11) || \
+ ((INSTANCE) == TIM12) || \
+ ((INSTANCE) == TIM13) || \
+ ((INSTANCE) == TIM14))
+
+/************ TIM Instances : at least 2 capture/compare channels *************/
+#define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM9) || \
+ ((INSTANCE) == TIM12))
+
+/************ TIM Instances : at least 3 capture/compare channels *************/
+#define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8))
+
+/************ TIM Instances : at least 4 capture/compare channels *************/
+#define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8))
+
+/******************** TIM Instances : Advanced-control timers *****************/
+#define IS_TIM_ADVANCED_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM8))
+
+/******************* TIM Instances : Timer input XOR function *****************/
+#define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8))
+
+/****************** TIM Instances : DMA requests generation (UDE) *************/
+#define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM6) || \
+ ((INSTANCE) == TIM7) || \
+ ((INSTANCE) == TIM8))
+
+/************ TIM Instances : DMA requests generation (CCxDE) *****************/
+#define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8))
+
+/************ TIM Instances : DMA requests generation (COMDE) *****************/
+#define IS_TIM_CCDMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8))
+
+/******************** TIM Instances : DMA burst feature ***********************/
+#define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8))
+
+/****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/
+#define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM6) || \
+ ((INSTANCE) == TIM7) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM9) || \
+ ((INSTANCE) == TIM12))
+
+/*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
+#define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM9) || \
+ ((INSTANCE) == TIM12))
+
+/********************** TIM Instances : 32 bit Counter ************************/
+#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)(((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM5))
+
+/***************** TIM Instances : external trigger input available ************/
+#define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8))
+
+/****************** TIM Instances : remapping capability **********************/
+#define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM11))
+
+/******************* TIM Instances : output(s) available **********************/
+#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
+ ((((INSTANCE) == TIM1) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM2) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM3) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM4) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM5) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM8) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM9) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2))) \
+ || \
+ (((INSTANCE) == TIM10) && \
+ (((CHANNEL) == TIM_CHANNEL_1))) \
+ || \
+ (((INSTANCE) == TIM11) && \
+ (((CHANNEL) == TIM_CHANNEL_1))) \
+ || \
+ (((INSTANCE) == TIM12) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2))) \
+ || \
+ (((INSTANCE) == TIM13) && \
+ (((CHANNEL) == TIM_CHANNEL_1))) \
+ || \
+ (((INSTANCE) == TIM14) && \
+ (((CHANNEL) == TIM_CHANNEL_1))))
+
+/************ TIM Instances : complementary output(s) available ***************/
+#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
+ ((((INSTANCE) == TIM1) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3))) \
+ || \
+ (((INSTANCE) == TIM8) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3))))
+
+/******************** USART Instances : Synchronous mode **********************/
+#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3) || \
+ ((INSTANCE) == USART6))
+
+/******************** UART Instances : Asynchronous mode **********************/
+#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3) || \
+ ((INSTANCE) == USART6))
+
+/****************** UART Instances : Hardware Flow control ********************/
+#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3))
+
+/********************* UART Instances : Smart card mode ***********************/
+#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3) || \
+ ((INSTANCE) == USART6))
+
+/*********************** UART Instances : IRDA mode ***************************/
+#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3) || \
+ ((INSTANCE) == USART6))
+
+/*********************** PCD Instances ****************************************/
+#define IS_PCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS))
+
+/*********************** HCD Instances ****************************************/
+#define IS_HCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS))
+
+/****************************** IWDG Instances ********************************/
+#define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
+
+/****************************** WWDG Instances ********************************/
+#define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
+
+/****************************** QSPI Instances ********************************/
+#define IS_QSPI_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == QUADSPI)
+
+/***************************** FMPI2C Instances *******************************/
+#define IS_FMPI2C_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == FMPI2C1)
+
+/****************************** SDIO Instances ********************************/
+#define IS_SDIO_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SDIO)
+
+/****************************** USB Instances ********************************/
+#define IS_USB_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB_OTG_FS)
+
+/****************************** USB Exported Constants ************************/
+#define USB_OTG_FS_HOST_MAX_CHANNEL_NBR 12U
+#define USB_OTG_FS_MAX_IN_ENDPOINTS 6U /* Including EP0 */
+#define USB_OTG_FS_MAX_OUT_ENDPOINTS 6U /* Including EP0 */
+#define USB_OTG_FS_TOTAL_FIFO_SIZE 1280U /* in Bytes */
+
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* __STM32F412Rx_H */
+
+
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Device/ST/STM32F4xx/Include/stm32f412vx.h b/Device/ST/STM32F4xx/Include/stm32f412vx.h
new file mode 100644
index 0000000..4b05842
--- /dev/null
+++ b/Device/ST/STM32F4xx/Include/stm32f412vx.h
@@ -0,0 +1,7387 @@
+/**
+ ******************************************************************************
+ * @file stm32f412vx.h
+ * @author MCD Application Team
+ * @version V2.5.0
+ * @date 22-April-2016
+ * @brief CMSIS STM32F412Vx Device Peripheral Access Layer Header File.
+ *
+ * This file contains:
+ * - Data structures and the address mapping for all peripherals
+ * - peripherals registers declarations and bits definition
+ * - Macros to access peripheral’s registers hardware
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/** @addtogroup CMSIS
+ * @{
+ */
+
+/** @addtogroup stm32f412vx
+ * @{
+ */
+
+#ifndef __STM32F412Vx_H
+#define __STM32F412Vx_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif /* __cplusplus */
+
+
+/** @addtogroup Configuration_section_for_CMSIS
+ * @{
+ */
+
+/**
+ * @brief Configuration of the Cortex-M4 Processor and Core Peripherals
+ */
+#define __CM4_REV 0x0001U /*!< Core revision r0p1 */
+#define __MPU_PRESENT 1U /*!< STM32F4XX provides an MPU */
+#define __NVIC_PRIO_BITS 4U /*!< STM32F4XX uses 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */
+#define __FPU_PRESENT 1U /*!< FPU present */
+
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_interrupt_number_definition
+ * @{
+ */
+
+/**
+ * @brief STM32F4XX Interrupt Number Definition, according to the selected device
+ * in @ref Library_configuration_section
+ */
+typedef enum
+{
+/****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/
+ NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
+ MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */
+ BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */
+ UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */
+ SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */
+ DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */
+ PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */
+ SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */
+/****** STM32 specific Interrupt Numbers **********************************************************************/
+ WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
+ PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */
+ TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */
+ RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */
+ FLASH_IRQn = 4, /*!< FLASH global Interrupt */
+ RCC_IRQn = 5, /*!< RCC global Interrupt */
+ EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */
+ EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */
+ EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */
+ EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */
+ EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */
+ DMA1_Stream0_IRQn = 11, /*!< DMA1 Stream 0 global Interrupt */
+ DMA1_Stream1_IRQn = 12, /*!< DMA1 Stream 1 global Interrupt */
+ DMA1_Stream2_IRQn = 13, /*!< DMA1 Stream 2 global Interrupt */
+ DMA1_Stream3_IRQn = 14, /*!< DMA1 Stream 3 global Interrupt */
+ DMA1_Stream4_IRQn = 15, /*!< DMA1 Stream 4 global Interrupt */
+ DMA1_Stream5_IRQn = 16, /*!< DMA1 Stream 5 global Interrupt */
+ DMA1_Stream6_IRQn = 17, /*!< DMA1 Stream 6 global Interrupt */
+ ADC_IRQn = 18, /*!< ADC1 global Interrupts */
+ CAN1_TX_IRQn = 19, /*!< CAN1 TX Interrupt */
+ CAN1_RX0_IRQn = 20, /*!< CAN1 RX0 Interrupt */
+ CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */
+ CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */
+ EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
+ TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break interrupt and TIM9 global interrupt */
+ TIM1_UP_TIM10_IRQn = 25, /*!< TIM1 Update Interrupt and TIM10 global interrupt */
+ TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */
+ TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
+ TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
+ TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
+ TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
+ I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
+ I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
+ I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
+ I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
+ SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
+ SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
+ USART1_IRQn = 37, /*!< USART1 global Interrupt */
+ USART2_IRQn = 38, /*!< USART2 global Interrupt */
+ USART3_IRQn = 39, /*!< USART3 global Interrupt */
+ EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
+ RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */
+ OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS Wakeup through EXTI line interrupt */
+ TIM8_BRK_TIM12_IRQn = 43, /*!< TIM8 Break Interrupt and TIM12 global interrupt */
+ TIM8_UP_TIM13_IRQn = 44, /*!< TIM8 Update Interrupt and TIM13 global interrupt */
+ TIM8_TRG_COM_TIM14_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */
+ TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */
+ DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */
+ SDIO_IRQn = 49, /*!< SDIO global Interrupt */
+ TIM5_IRQn = 50, /*!< TIM5 global Interrupt */
+ SPI3_IRQn = 51, /*!< SPI3 global Interrupt */
+ TIM6_IRQn = 54, /*!< TIM6 global interrupt */
+ TIM7_IRQn = 55, /*!< TIM7 global interrupt */
+ DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */
+ DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */
+ DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */
+ DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */
+ DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */
+ DFSDM1_FLT0_IRQn = 61, /*!< DFSDM1 Filter 0 global Interrupt */
+ DFSDM1_FLT1_IRQn = 62, /*!< DFSDM1 Filter 1 global Interrupt */
+ CAN2_TX_IRQn = 63, /*!< CAN2 TX Interrupt */
+ CAN2_RX0_IRQn = 64, /*!< CAN2 RX0 Interrupt */
+ CAN2_RX1_IRQn = 65, /*!< CAN2 RX1 Interrupt */
+ CAN2_SCE_IRQn = 66, /*!< CAN2 SCE Interrupt */
+ OTG_FS_IRQn = 67, /*!< USB OTG FS global Interrupt */
+ DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */
+ DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */
+ DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */
+ USART6_IRQn = 71, /*!< USART6 global interrupt */
+ I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */
+ I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */
+ RNG_IRQn = 80, /*!< RNG global Interrupt */
+ FPU_IRQn = 81, /*!< FPU global interrupt */
+ SPI4_IRQn = 84, /*!< SPI4 global Interrupt */
+ SPI5_IRQn = 85, /*!< SPI5 global Interrupt */
+ QUADSPI_IRQn = 92, /*!< QuadSPI global Interrupt */
+ FMPI2C1_EV_IRQn = 95, /*!< FMPI2C1 Event Interrupt */
+ FMPI2C1_ER_IRQn = 96 /*!< FMPI2C1 Error Interrupt */
+} IRQn_Type;
+
+/**
+ * @}
+ */
+
+#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
+#include "system_stm32f4xx.h"
+#include <stdint.h>
+
+/** @addtogroup Peripheral_registers_structures
+ * @{
+ */
+
+/**
+ * @brief Analog to Digital Converter
+ */
+
+typedef struct
+{
+ __IO uint32_t SR; /*!< ADC status register, Address offset: 0x00 */
+ __IO uint32_t CR1; /*!< ADC control register 1, Address offset: 0x04 */
+ __IO uint32_t CR2; /*!< ADC control register 2, Address offset: 0x08 */
+ __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x0C */
+ __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x10 */
+ __IO uint32_t JOFR1; /*!< ADC injected channel data offset register 1, Address offset: 0x14 */
+ __IO uint32_t JOFR2; /*!< ADC injected channel data offset register 2, Address offset: 0x18 */
+ __IO uint32_t JOFR3; /*!< ADC injected channel data offset register 3, Address offset: 0x1C */
+ __IO uint32_t JOFR4; /*!< ADC injected channel data offset register 4, Address offset: 0x20 */
+ __IO uint32_t HTR; /*!< ADC watchdog higher threshold register, Address offset: 0x24 */
+ __IO uint32_t LTR; /*!< ADC watchdog lower threshold register, Address offset: 0x28 */
+ __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x2C */
+ __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x30 */
+ __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x34 */
+ __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x38*/
+ __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x3C */
+ __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x40 */
+ __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x44 */
+ __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x48 */
+ __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x4C */
+} ADC_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1 base address + 0x300 */
+ __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1 base address + 0x304 */
+ __IO uint32_t CDR; /*!< ADC common regular data register for dual
+ AND triple modes, Address offset: ADC1 base address + 0x308 */
+} ADC_Common_TypeDef;
+
+/**
+ * @brief Controller Area Network TxMailBox
+ */
+
+typedef struct
+{
+ __IO uint32_t TIR; /*!< CAN TX mailbox identifier register */
+ __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */
+ __IO uint32_t TDLR; /*!< CAN mailbox data low register */
+ __IO uint32_t TDHR; /*!< CAN mailbox data high register */
+} CAN_TxMailBox_TypeDef;
+
+/**
+ * @brief Controller Area Network FIFOMailBox
+ */
+
+typedef struct
+{
+ __IO uint32_t RIR; /*!< CAN receive FIFO mailbox identifier register */
+ __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */
+ __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */
+ __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */
+} CAN_FIFOMailBox_TypeDef;
+
+/**
+ * @brief Controller Area Network FilterRegister
+ */
+
+typedef struct
+{
+ __IO uint32_t FR1; /*!< CAN Filter bank register 1 */
+ __IO uint32_t FR2; /*!< CAN Filter bank register 1 */
+} CAN_FilterRegister_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t MCR; /*!< CAN master control register, Address offset: 0x00 */
+ __IO uint32_t MSR; /*!< CAN master status register, Address offset: 0x04 */
+ __IO uint32_t TSR; /*!< CAN transmit status register, Address offset: 0x08 */
+ __IO uint32_t RF0R; /*!< CAN receive FIFO 0 register, Address offset: 0x0C */
+ __IO uint32_t RF1R; /*!< CAN receive FIFO 1 register, Address offset: 0x10 */
+ __IO uint32_t IER; /*!< CAN interrupt enable register, Address offset: 0x14 */
+ __IO uint32_t ESR; /*!< CAN error status register, Address offset: 0x18 */
+ __IO uint32_t BTR; /*!< CAN bit timing register, Address offset: 0x1C */
+ uint32_t RESERVED0[88]; /*!< Reserved, 0x020 - 0x17F */
+ CAN_TxMailBox_TypeDef sTxMailBox[3]; /*!< CAN Tx MailBox, Address offset: 0x180 - 0x1AC */
+ CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; /*!< CAN FIFO MailBox, Address offset: 0x1B0 - 0x1CC */
+ uint32_t RESERVED1[12]; /*!< Reserved, 0x1D0 - 0x1FF */
+ __IO uint32_t FMR; /*!< CAN filter master register, Address offset: 0x200 */
+ __IO uint32_t FM1R; /*!< CAN filter mode register, Address offset: 0x204 */
+ uint32_t RESERVED2; /*!< Reserved, 0x208 */
+ __IO uint32_t FS1R; /*!< CAN filter scale register, Address offset: 0x20C */
+ uint32_t RESERVED3; /*!< Reserved, 0x210 */
+ __IO uint32_t FFA1R; /*!< CAN filter FIFO assignment register, Address offset: 0x214 */
+ uint32_t RESERVED4; /*!< Reserved, 0x218 */
+ __IO uint32_t FA1R; /*!< CAN filter activation register, Address offset: 0x21C */
+ uint32_t RESERVED5[8]; /*!< Reserved, 0x220-0x23F */
+ CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register, Address offset: 0x240-0x31C */
+} CAN_TypeDef;
+
+/**
+ * @brief CRC calculation unit
+ */
+
+typedef struct
+{
+ __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
+ __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
+ uint8_t RESERVED0; /*!< Reserved, 0x05 */
+ uint16_t RESERVED1; /*!< Reserved, 0x06 */
+ __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
+}CRC_TypeDef;
+
+/**
+ * @brief DFSDM module registers
+ */
+typedef struct
+{
+ __IO uint32_t FLTCR1; /*!< DFSDM control register1, Address offset: 0x100 */
+ __IO uint32_t FLTCR2; /*!< DFSDM control register2, Address offset: 0x104 */
+ __IO uint32_t FLTISR; /*!< DFSDM interrupt and status register, Address offset: 0x108 */
+ __IO uint32_t FLTICR; /*!< DFSDM interrupt flag clear register, Address offset: 0x10C */
+ __IO uint32_t FLTJCHGR; /*!< DFSDM injected channel group selection register, Address offset: 0x110 */
+ __IO uint32_t FLTFCR; /*!< DFSDM filter control register, Address offset: 0x114 */
+ __IO uint32_t FLTJDATAR; /*!< DFSDM data register for injected group, Address offset: 0x118 */
+ __IO uint32_t FLTRDATAR; /*!< DFSDM data register for regular group, Address offset: 0x11C */
+ __IO uint32_t FLTAWHTR; /*!< DFSDM analog watchdog high threshold register, Address offset: 0x120 */
+ __IO uint32_t FLTAWLTR; /*!< DFSDM analog watchdog low threshold register, Address offset: 0x124 */
+ __IO uint32_t FLTAWSR; /*!< DFSDM analog watchdog status register Address offset: 0x128 */
+ __IO uint32_t FLTAWCFR; /*!< DFSDM analog watchdog clear flag register Address offset: 0x12C */
+ __IO uint32_t FLTEXMAX; /*!< DFSDM extreme detector maximum register, Address offset: 0x130 */
+ __IO uint32_t FLTEXMIN; /*!< DFSDM extreme detector minimum register Address offset: 0x134 */
+ __IO uint32_t FLTCNVTIMR; /*!< DFSDM conversion timer, Address offset: 0x138 */
+} DFSDM_Filter_TypeDef;
+
+/**
+ * @brief DFSDM channel configuration registers
+ */
+typedef struct
+{
+ __IO uint32_t CHCFGR1; /*!< DFSDM channel configuration register1, Address offset: 0x00 */
+ __IO uint32_t CHCFGR2; /*!< DFSDM channel configuration register2, Address offset: 0x04 */
+ __IO uint32_t CHAWSCDR; /*!< DFSDM channel analog watchdog and
+ short circuit detector register, Address offset: 0x08 */
+ __IO uint32_t CHWDATAR; /*!< DFSDM channel watchdog filter data register, Address offset: 0x0C */
+ __IO uint32_t CHDATINR; /*!< DFSDM channel data input register, Address offset: 0x10 */
+} DFSDM_Channel_TypeDef;
+
+/**
+ * @brief Debug MCU
+ */
+typedef struct
+{
+ __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
+ __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
+ __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */
+ __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */
+}DBGMCU_TypeDef;
+
+
+/**
+ * @brief DMA Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< DMA stream x configuration register */
+ __IO uint32_t NDTR; /*!< DMA stream x number of data register */
+ __IO uint32_t PAR; /*!< DMA stream x peripheral address register */
+ __IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */
+ __IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */
+ __IO uint32_t FCR; /*!< DMA stream x FIFO control register */
+} DMA_Stream_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t LISR; /*!< DMA low interrupt status register, Address offset: 0x00 */
+ __IO uint32_t HISR; /*!< DMA high interrupt status register, Address offset: 0x04 */
+ __IO uint32_t LIFCR; /*!< DMA low interrupt flag clear register, Address offset: 0x08 */
+ __IO uint32_t HIFCR; /*!< DMA high interrupt flag clear register, Address offset: 0x0C */
+} DMA_TypeDef;
+
+
+/**
+ * @brief External Interrupt/Event Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t IMR; /*!< EXTI Interrupt mask register, Address offset: 0x00 */
+ __IO uint32_t EMR; /*!< EXTI Event mask register, Address offset: 0x04 */
+ __IO uint32_t RTSR; /*!< EXTI Rising trigger selection register, Address offset: 0x08 */
+ __IO uint32_t FTSR; /*!< EXTI Falling trigger selection register, Address offset: 0x0C */
+ __IO uint32_t SWIER; /*!< EXTI Software interrupt event register, Address offset: 0x10 */
+ __IO uint32_t PR; /*!< EXTI Pending register, Address offset: 0x14 */
+} EXTI_TypeDef;
+
+/**
+ * @brief FLASH Registers
+ */
+
+typedef struct
+{
+ __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */
+ __IO uint32_t KEYR; /*!< FLASH key register, Address offset: 0x04 */
+ __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x08 */
+ __IO uint32_t SR; /*!< FLASH status register, Address offset: 0x0C */
+ __IO uint32_t CR; /*!< FLASH control register, Address offset: 0x10 */
+ __IO uint32_t OPTCR; /*!< FLASH option control register , Address offset: 0x14 */
+ __IO uint32_t OPTCR1; /*!< FLASH option control register 1, Address offset: 0x18 */
+} FLASH_TypeDef;
+
+/**
+ * @brief Flexible Memory Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */
+} FSMC_Bank1_TypeDef;
+
+/**
+ * @brief Flexible Memory Controller Bank1E
+ */
+
+typedef struct
+{
+ __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */
+} FSMC_Bank1E_TypeDef;
+
+/**
+ * @brief General Purpose I/O
+ */
+
+typedef struct
+{
+ __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
+ __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */
+ __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */
+ __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
+ __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
+ __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
+ __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */
+ __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
+ __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */
+} GPIO_TypeDef;
+
+/**
+ * @brief System configuration controller
+ */
+typedef struct
+{
+ __IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */
+ __IO uint32_t PMC; /*!< SYSCFG peripheral mode configuration register, Address offset: 0x04 */
+ __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
+ uint32_t RESERVED[2]; /*!< Reserved, 0x18-0x1C */
+ __IO uint32_t CMPCR; /*!< SYSCFG Compensation cell control register, Address offset: 0x20 */
+ uint32_t RESERVED1[2]; /*!< Reserved, 0x24-0x28 */
+ __IO uint32_t CFGR; /*!< SYSCFG Configuration register, Address offset: 0x2C */
+} SYSCFG_TypeDef;
+
+/**
+ * @brief Inter-integrated Circuit Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */
+ __IO uint32_t OAR1; /*!< I2C Own address register 1, Address offset: 0x08 */
+ __IO uint32_t OAR2; /*!< I2C Own address register 2, Address offset: 0x0C */
+ __IO uint32_t DR; /*!< I2C Data register, Address offset: 0x10 */
+ __IO uint32_t SR1; /*!< I2C Status register 1, Address offset: 0x14 */
+ __IO uint32_t SR2; /*!< I2C Status register 2, Address offset: 0x18 */
+ __IO uint32_t CCR; /*!< I2C Clock control register, Address offset: 0x1C */
+ __IO uint32_t TRISE; /*!< I2C TRISE register, Address offset: 0x20 */
+ __IO uint32_t FLTR; /*!< I2C FLTR register, Address offset: 0x24 */
+} I2C_TypeDef;
+
+/**
+ * @brief Inter-integrated Circuit Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t CR1; /*!< FMPI2C Control register 1, Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< FMPI2C Control register 2, Address offset: 0x04 */
+ __IO uint32_t OAR1; /*!< FMPI2C Own address 1 register, Address offset: 0x08 */
+ __IO uint32_t OAR2; /*!< FMPI2C Own address 2 register, Address offset: 0x0C */
+ __IO uint32_t TIMINGR; /*!< FMPI2C Timing register, Address offset: 0x10 */
+ __IO uint32_t TIMEOUTR; /*!< FMPI2C Timeout register, Address offset: 0x14 */
+ __IO uint32_t ISR; /*!< FMPI2C Interrupt and status register, Address offset: 0x18 */
+ __IO uint32_t ICR; /*!< FMPI2C Interrupt clear register, Address offset: 0x1C */
+ __IO uint32_t PECR; /*!< FMPI2C PEC register, Address offset: 0x20 */
+ __IO uint32_t RXDR; /*!< FMPI2C Receive data register, Address offset: 0x24 */
+ __IO uint32_t TXDR; /*!< FMPI2C Transmit data register, Address offset: 0x28 */
+} FMPI2C_TypeDef;
+
+/**
+ * @brief Independent WATCHDOG
+ */
+
+typedef struct
+{
+ __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */
+ __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */
+ __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */
+ __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */
+} IWDG_TypeDef;
+
+/**
+ * @brief Power Control
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */
+ __IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */
+} PWR_TypeDef;
+
+/**
+ * @brief Reset and Clock Control
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */
+ __IO uint32_t PLLCFGR; /*!< RCC PLL configuration register, Address offset: 0x04 */
+ __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x08 */
+ __IO uint32_t CIR; /*!< RCC clock interrupt register, Address offset: 0x0C */
+ __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x10 */
+ __IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x14 */
+ __IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0x18 */
+ uint32_t RESERVED0; /*!< Reserved, 0x1C */
+ __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x20 */
+ __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x24 */
+ uint32_t RESERVED1[2]; /*!< Reserved, 0x28-0x2C */
+ __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clock register, Address offset: 0x30 */
+ __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clock register, Address offset: 0x34 */
+ __IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clock register, Address offset: 0x38 */
+ uint32_t RESERVED2; /*!< Reserved, 0x3C */
+ __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x40 */
+ __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x44 */
+ uint32_t RESERVED3[2]; /*!< Reserved, 0x48-0x4C */
+ __IO uint32_t AHB1LPENR; /*!< RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 */
+ __IO uint32_t AHB2LPENR; /*!< RCC AHB2 peripheral clock enable in low power mode register, Address offset: 0x54 */
+ __IO uint32_t AHB3LPENR; /*!< RCC AHB3 peripheral clock enable in low power mode register, Address offset: 0x58 */
+ uint32_t RESERVED4; /*!< Reserved, 0x5C */
+ __IO uint32_t APB1LPENR; /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 */
+ __IO uint32_t APB2LPENR; /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 */
+ uint32_t RESERVED5[2]; /*!< Reserved, 0x68-0x6C */
+ __IO uint32_t BDCR; /*!< RCC Backup domain control register, Address offset: 0x70 */
+ __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x74 */
+ uint32_t RESERVED6[2]; /*!< Reserved, 0x78-0x7C */
+ __IO uint32_t SSCGR; /*!< RCC spread spectrum clock generation register, Address offset: 0x80 */
+ __IO uint32_t PLLI2SCFGR; /*!< RCC PLLI2S configuration register, Address offset: 0x84 */
+ uint32_t RESERVED7; /*!< Reserved, 0x84 */
+ __IO uint32_t DCKCFGR; /*!< RCC Dedicated Clocks configuration register, Address offset: 0x8C */
+ __IO uint32_t CKGATENR; /*!< RCC Clocks Gated ENable Register, Address offset: 0x90 */
+ __IO uint32_t DCKCFGR2; /*!< RCC Dedicated Clocks configuration register 2, Address offset: 0x94 */
+} RCC_TypeDef;
+
+/**
+ * @brief Real-Time Clock
+ */
+
+typedef struct
+{
+ __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
+ __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */
+ __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */
+ __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */
+ __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */
+ __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */
+ __IO uint32_t CALIBR; /*!< RTC calibration register, Address offset: 0x18 */
+ __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */
+ __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */
+ __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */
+ __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */
+ __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */
+ __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */
+ __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */
+ __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */
+ __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */
+ __IO uint32_t TAFCR; /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */
+ __IO uint32_t ALRMASSR;/*!< RTC alarm A sub second register, Address offset: 0x44 */
+ __IO uint32_t ALRMBSSR;/*!< RTC alarm B sub second register, Address offset: 0x48 */
+ uint32_t RESERVED7; /*!< Reserved, 0x4C */
+ __IO uint32_t BKP0R; /*!< RTC backup register 1, Address offset: 0x50 */
+ __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */
+ __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */
+ __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */
+ __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */
+ __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */
+ __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */
+ __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */
+ __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */
+ __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */
+ __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */
+ __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */
+ __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */
+ __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */
+ __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */
+ __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */
+ __IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */
+ __IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */
+ __IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */
+ __IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */
+} RTC_TypeDef;
+
+
+/**
+ * @brief SD host Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t POWER; /*!< SDIO power control register, Address offset: 0x00 */
+ __IO uint32_t CLKCR; /*!< SDI clock control register, Address offset: 0x04 */
+ __IO uint32_t ARG; /*!< SDIO argument register, Address offset: 0x08 */
+ __IO uint32_t CMD; /*!< SDIO command register, Address offset: 0x0C */
+ __I uint32_t RESPCMD; /*!< SDIO command response register, Address offset: 0x10 */
+ __I uint32_t RESP1; /*!< SDIO response 1 register, Address offset: 0x14 */
+ __I uint32_t RESP2; /*!< SDIO response 2 register, Address offset: 0x18 */
+ __I uint32_t RESP3; /*!< SDIO response 3 register, Address offset: 0x1C */
+ __I uint32_t RESP4; /*!< SDIO response 4 register, Address offset: 0x20 */
+ __IO uint32_t DTIMER; /*!< SDIO data timer register, Address offset: 0x24 */
+ __IO uint32_t DLEN; /*!< SDIO data length register, Address offset: 0x28 */
+ __IO uint32_t DCTRL; /*!< SDIO data control register, Address offset: 0x2C */
+ __I uint32_t DCOUNT; /*!< SDIO data counter register, Address offset: 0x30 */
+ __I uint32_t STA; /*!< SDIO status register, Address offset: 0x34 */
+ __IO uint32_t ICR; /*!< SDIO interrupt clear register, Address offset: 0x38 */
+ __IO uint32_t MASK; /*!< SDIO mask register, Address offset: 0x3C */
+ uint32_t RESERVED0[2]; /*!< Reserved, 0x40-0x44 */
+ __I uint32_t FIFOCNT; /*!< SDIO FIFO counter register, Address offset: 0x48 */
+ uint32_t RESERVED1[13]; /*!< Reserved, 0x4C-0x7C */
+ __IO uint32_t FIFO; /*!< SDIO data FIFO register, Address offset: 0x80 */
+} SDIO_TypeDef;
+
+/**
+ * @brief Serial Peripheral Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t CR1; /*!< SPI control register 1 (not used in I2S mode), Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< SPI control register 2, Address offset: 0x04 */
+ __IO uint32_t SR; /*!< SPI status register, Address offset: 0x08 */
+ __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */
+ __IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
+ __IO uint32_t RXCRCR; /*!< SPI RX CRC register (not used in I2S mode), Address offset: 0x14 */
+ __IO uint32_t TXCRCR; /*!< SPI TX CRC register (not used in I2S mode), Address offset: 0x18 */
+ __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */
+ __IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */
+} SPI_TypeDef;
+
+/**
+ * @brief QUAD Serial Peripheral Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< QUADSPI Control register, Address offset: 0x00 */
+ __IO uint32_t DCR; /*!< QUADSPI Device Configuration register, Address offset: 0x04 */
+ __IO uint32_t SR; /*!< QUADSPI Status register, Address offset: 0x08 */
+ __IO uint32_t FCR; /*!< QUADSPI Flag Clear register, Address offset: 0x0C */
+ __IO uint32_t DLR; /*!< QUADSPI Data Length register, Address offset: 0x10 */
+ __IO uint32_t CCR; /*!< QUADSPI Communication Configuration register, Address offset: 0x14 */
+ __IO uint32_t AR; /*!< QUADSPI Address register, Address offset: 0x18 */
+ __IO uint32_t ABR; /*!< QUADSPI Alternate Bytes register, Address offset: 0x1C */
+ __IO uint32_t DR; /*!< QUADSPI Data register, Address offset: 0x20 */
+ __IO uint32_t PSMKR; /*!< QUADSPI Polling Status Mask register, Address offset: 0x24 */
+ __IO uint32_t PSMAR; /*!< QUADSPI Polling Status Match register, Address offset: 0x28 */
+ __IO uint32_t PIR; /*!< QUADSPI Polling Interval register, Address offset: 0x2C */
+ __IO uint32_t LPTR; /*!< QUADSPI Low Power Timeout register, Address offset: 0x30 */
+} QUADSPI_TypeDef;
+
+/**
+ * @brief TIM
+ */
+
+typedef struct
+{
+ __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
+ __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */
+ __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
+ __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
+ __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
+ __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
+ __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
+ __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
+ __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
+ __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */
+ __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
+ __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */
+ __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
+ __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
+ __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
+ __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
+ __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
+ __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
+ __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */
+ __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */
+} TIM_TypeDef;
+
+/**
+ * @brief Universal Synchronous Asynchronous Receiver Transmitter
+ */
+
+typedef struct
+{
+ __IO uint32_t SR; /*!< USART Status register, Address offset: 0x00 */
+ __IO uint32_t DR; /*!< USART Data register, Address offset: 0x04 */
+ __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x08 */
+ __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x0C */
+ __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x10 */
+ __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x14 */
+ __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x18 */
+} USART_TypeDef;
+
+/**
+ * @brief Window WATCHDOG
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
+ __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
+ __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
+} WWDG_TypeDef;
+
+
+/**
+ * @brief RNG
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */
+ __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */
+ __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */
+} RNG_TypeDef;
+
+
+/**
+ * @brief USB_OTG_Core_Registers
+ */
+typedef struct
+{
+ __IO uint32_t GOTGCTL; /*!< USB_OTG Control and Status Register 000h*/
+ __IO uint32_t GOTGINT; /*!< USB_OTG Interrupt Register 004h*/
+ __IO uint32_t GAHBCFG; /*!< Core AHB Configuration Register 008h*/
+ __IO uint32_t GUSBCFG; /*!< Core USB Configuration Register 00Ch*/
+ __IO uint32_t GRSTCTL; /*!< Core Reset Register 010h*/
+ __IO uint32_t GINTSTS; /*!< Core Interrupt Register 014h*/
+ __IO uint32_t GINTMSK; /*!< Core Interrupt Mask Register 018h*/
+ __IO uint32_t GRXSTSR; /*!< Receive Sts Q Read Register 01Ch*/
+ __IO uint32_t GRXSTSP; /*!< Receive Sts Q Read & POP Register 020h*/
+ __IO uint32_t GRXFSIZ; /*!< Receive FIFO Size Register 024h*/
+ __IO uint32_t DIEPTXF0_HNPTXFSIZ; /*!< EP0 / Non Periodic Tx FIFO Size Register 028h*/
+ __IO uint32_t HNPTXSTS; /*!< Non Periodic Tx FIFO/Queue Sts reg 02Ch*/
+ uint32_t Reserved30[2]; /*!< Reserved 030h*/
+ __IO uint32_t GCCFG; /*!< General Purpose IO Register 038h*/
+ __IO uint32_t CID; /*!< User ID Register 03Ch*/
+ uint32_t Reserved5[3]; /*!< Reserved 040h-048h*/
+ __IO uint32_t GHWCFG3; /*!< User HW config3 04Ch*/
+ uint32_t Reserved6; /*!< Reserved 050h*/
+ __IO uint32_t GLPMCFG; /*!< LPM Register 054h*/
+ uint32_t Reserved; /*!< Reserved 058h */
+ __IO uint32_t GDFIFOCFG; /*!< DFIFO Software Config Register 05Ch */
+ uint32_t Reserved43[40]; /*!< Reserved 058h-0FFh */
+ __IO uint32_t HPTXFSIZ; /*!< Host Periodic Tx FIFO Size Reg 100h*/
+ __IO uint32_t DIEPTXF[0x0F]; /*!< dev Periodic Transmit FIFO */
+} USB_OTG_GlobalTypeDef;
+
+
+/**
+ * @brief USB_OTG_device_Registers
+ */
+typedef struct
+{
+ __IO uint32_t DCFG; /*!< dev Configuration Register 800h */
+ __IO uint32_t DCTL; /*!< dev Control Register 804h */
+ __IO uint32_t DSTS; /*!< dev Status Register (RO) 808h */
+ uint32_t Reserved0C; /*!< Reserved 80Ch */
+ __IO uint32_t DIEPMSK; /*!< dev IN Endpoint Mask 810h */
+ __IO uint32_t DOEPMSK; /*!< dev OUT Endpoint Mask 814h */
+ __IO uint32_t DAINT; /*!< dev All Endpoints Itr Reg 818h */
+ __IO uint32_t DAINTMSK; /*!< dev All Endpoints Itr Mask 81Ch */
+ uint32_t Reserved20; /*!< Reserved 820h */
+ uint32_t Reserved9; /*!< Reserved 824h */
+ __IO uint32_t DVBUSDIS; /*!< dev VBUS discharge Register 828h */
+ __IO uint32_t DVBUSPULSE; /*!< dev VBUS Pulse Register 82Ch */
+ __IO uint32_t DTHRCTL; /*!< dev threshold 830h */
+ __IO uint32_t DIEPEMPMSK; /*!< dev empty msk 834h */
+ __IO uint32_t DEACHINT; /*!< dedicated EP interrupt 838h */
+ __IO uint32_t DEACHMSK; /*!< dedicated EP msk 83Ch */
+ uint32_t Reserved40; /*!< dedicated EP mask 840h */
+ __IO uint32_t DINEP1MSK; /*!< dedicated EP mask 844h */
+ uint32_t Reserved44[15]; /*!< Reserved 844-87Ch */
+ __IO uint32_t DOUTEP1MSK; /*!< dedicated EP msk 884h */
+} USB_OTG_DeviceTypeDef;
+
+
+/**
+ * @brief USB_OTG_IN_Endpoint-Specific_Register
+ */
+typedef struct
+{
+ __IO uint32_t DIEPCTL; /*!< dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h */
+ uint32_t Reserved04; /*!< Reserved 900h + (ep_num * 20h) + 04h */
+ __IO uint32_t DIEPINT; /*!< dev IN Endpoint Itr Reg 900h + (ep_num * 20h) + 08h */
+ uint32_t Reserved0C; /*!< Reserved 900h + (ep_num * 20h) + 0Ch */
+ __IO uint32_t DIEPTSIZ; /*!< IN Endpoint Txfer Size 900h + (ep_num * 20h) + 10h */
+ __IO uint32_t DIEPDMA; /*!< IN Endpoint DMA Address Reg 900h + (ep_num * 20h) + 14h */
+ __IO uint32_t DTXFSTS; /*!< IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h */
+ uint32_t Reserved18; /*!< Reserved 900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch */
+} USB_OTG_INEndpointTypeDef;
+
+
+/**
+ * @brief USB_OTG_OUT_Endpoint-Specific_Registers
+ */
+typedef struct
+{
+ __IO uint32_t DOEPCTL; /*!< dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h */
+ uint32_t Reserved04; /*!< Reserved B00h + (ep_num * 20h) + 04h */
+ __IO uint32_t DOEPINT; /*!< dev OUT Endpoint Itr Reg B00h + (ep_num * 20h) + 08h */
+ uint32_t Reserved0C; /*!< Reserved B00h + (ep_num * 20h) + 0Ch */
+ __IO uint32_t DOEPTSIZ; /*!< dev OUT Endpoint Txfer Size B00h + (ep_num * 20h) + 10h */
+ __IO uint32_t DOEPDMA; /*!< dev OUT Endpoint DMA Address B00h + (ep_num * 20h) + 14h */
+ uint32_t Reserved18[2]; /*!< Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch */
+} USB_OTG_OUTEndpointTypeDef;
+
+
+/**
+ * @brief USB_OTG_Host_Mode_Register_Structures
+ */
+typedef struct
+{
+ __IO uint32_t HCFG; /*!< Host Configuration Register 400h */
+ __IO uint32_t HFIR; /*!< Host Frame Interval Register 404h */
+ __IO uint32_t HFNUM; /*!< Host Frame Nbr/Frame Remaining 408h */
+ uint32_t Reserved40C; /*!< Reserved 40Ch */
+ __IO uint32_t HPTXSTS; /*!< Host Periodic Tx FIFO/ Queue Status 410h */
+ __IO uint32_t HAINT; /*!< Host All Channels Interrupt Register 414h */
+ __IO uint32_t HAINTMSK; /*!< Host All Channels Interrupt Mask 418h */
+} USB_OTG_HostTypeDef;
+
+
+/**
+ * @brief USB_OTG_Host_Channel_Specific_Registers
+ */
+typedef struct
+{
+ __IO uint32_t HCCHAR; /*!< Host Channel Characteristics Register 500h */
+ __IO uint32_t HCSPLT; /*!< Host Channel Split Control Register 504h */
+ __IO uint32_t HCINT; /*!< Host Channel Interrupt Register 508h */
+ __IO uint32_t HCINTMSK; /*!< Host Channel Interrupt Mask Register 50Ch */
+ __IO uint32_t HCTSIZ; /*!< Host Channel Transfer Size Register 510h */
+ __IO uint32_t HCDMA; /*!< Host Channel DMA Address Register 514h */
+ uint32_t Reserved[2]; /*!< Reserved */
+} USB_OTG_HostChannelTypeDef;
+
+
+/**
+ * @brief Peripheral_memory_map
+ */
+#define FLASH_BASE 0x08000000U /*!< FLASH(up to 1 MB) base address in the alias region */
+#define SRAM1_BASE 0x20000000U /*!< SRAM1(256 KB) base address in the alias region */
+#define PERIPH_BASE 0x40000000U /*!< Peripheral base address in the alias region */
+#define FSMC_R_BASE 0xA0000000U /*!< FSMC registers base address */
+#define QSPI_R_BASE 0xA0001000U /*!< QuadSPI registers base address */
+
+#define SRAM1_BB_BASE 0x22000000U /*!< SRAM1(256 KB) base address in the bit-band region */
+#define PERIPH_BB_BASE 0x42000000U /*!< Peripheral base address in the bit-band region */
+#define FLASH_END 0x080FFFFFU /*!< FLASH end address */
+
+/* Legacy defines */
+#define SRAM_BASE SRAM1_BASE
+#define SRAM_BB_BASE SRAM1_BB_BASE
+
+/*!< Peripheral memory map */
+#define APB1PERIPH_BASE PERIPH_BASE
+#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000U)
+#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000U)
+#define AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000U)
+
+/*!< APB1 peripherals */
+#define TIM2_BASE (APB1PERIPH_BASE + 0x0000U)
+#define TIM3_BASE (APB1PERIPH_BASE + 0x0400U)
+#define TIM4_BASE (APB1PERIPH_BASE + 0x0800U)
+#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00U)
+#define TIM6_BASE (APB1PERIPH_BASE + 0x1000U)
+#define TIM7_BASE (APB1PERIPH_BASE + 0x1400U)
+#define TIM12_BASE (APB1PERIPH_BASE + 0x1800U)
+#define TIM13_BASE (APB1PERIPH_BASE + 0x1C00U)
+#define TIM14_BASE (APB1PERIPH_BASE + 0x2000U)
+#define RTC_BASE (APB1PERIPH_BASE + 0x2800U)
+#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00U)
+#define IWDG_BASE (APB1PERIPH_BASE + 0x3000U)
+#define I2S2ext_BASE (APB1PERIPH_BASE + 0x3400U)
+#define SPI2_BASE (APB1PERIPH_BASE + 0x3800U)
+#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00U)
+#define I2S3ext_BASE (APB1PERIPH_BASE + 0x4000U)
+#define USART2_BASE (APB1PERIPH_BASE + 0x4400U)
+#define USART3_BASE (APB1PERIPH_BASE + 0x4800U)
+#define I2C1_BASE (APB1PERIPH_BASE + 0x5400U)
+#define I2C2_BASE (APB1PERIPH_BASE + 0x5800U)
+#define I2C3_BASE (APB1PERIPH_BASE + 0x5C00U)
+#define FMPI2C1_BASE (APB1PERIPH_BASE + 0x6000U)
+#define CAN1_BASE (APB1PERIPH_BASE + 0x6400U)
+#define CAN2_BASE (APB1PERIPH_BASE + 0x6800U)
+#define PWR_BASE (APB1PERIPH_BASE + 0x7000U)
+
+/*!< APB2 peripherals */
+#define TIM1_BASE (APB2PERIPH_BASE + 0x0000U)
+#define TIM8_BASE (APB2PERIPH_BASE + 0x0400U)
+#define USART1_BASE (APB2PERIPH_BASE + 0x1000U)
+#define USART6_BASE (APB2PERIPH_BASE + 0x1400U)
+#define ADC1_BASE (APB2PERIPH_BASE + 0x2000U)
+#define ADC_BASE (APB2PERIPH_BASE + 0x2300U)
+#define SDIO_BASE (APB2PERIPH_BASE + 0x2C00U)
+#define SPI1_BASE (APB2PERIPH_BASE + 0x3000U)
+#define SPI4_BASE (APB2PERIPH_BASE + 0x3400U)
+#define SYSCFG_BASE (APB2PERIPH_BASE + 0x3800U)
+#define EXTI_BASE (APB2PERIPH_BASE + 0x3C00U)
+#define TIM9_BASE (APB2PERIPH_BASE + 0x4000U)
+#define TIM10_BASE (APB2PERIPH_BASE + 0x4400U)
+#define TIM11_BASE (APB2PERIPH_BASE + 0x4800U)
+#define SPI5_BASE (APB2PERIPH_BASE + 0x5000U)
+#define DFSDM1_BASE (APB2PERIPH_BASE + 0x6000U)
+#define DFSDM1_Channel0_BASE (DFSDM1_BASE + 0x00U)
+#define DFSDM1_Channel1_BASE (DFSDM1_BASE + 0x20U)
+#define DFSDM1_Channel2_BASE (DFSDM1_BASE + 0x40U)
+#define DFSDM1_Channel3_BASE (DFSDM1_BASE + 0x60U)
+#define DFSDM1_Filter0_BASE (DFSDM1_BASE + 0x100U)
+#define DFSDM1_Filter1_BASE (DFSDM1_BASE + 0x180U)
+
+/*!< AHB1 peripherals */
+#define GPIOA_BASE (AHB1PERIPH_BASE + 0x0000U)
+#define GPIOB_BASE (AHB1PERIPH_BASE + 0x0400U)
+#define GPIOC_BASE (AHB1PERIPH_BASE + 0x0800U)
+#define GPIOD_BASE (AHB1PERIPH_BASE + 0x0C00U)
+#define GPIOE_BASE (AHB1PERIPH_BASE + 0x1000U)
+#define GPIOF_BASE (AHB1PERIPH_BASE + 0x1400U)
+#define GPIOG_BASE (AHB1PERIPH_BASE + 0x1800U)
+#define GPIOH_BASE (AHB1PERIPH_BASE + 0x1C00U)
+#define CRC_BASE (AHB1PERIPH_BASE + 0x3000U)
+#define RCC_BASE (AHB1PERIPH_BASE + 0x3800U)
+#define FLASH_R_BASE (AHB1PERIPH_BASE + 0x3C00U)
+#define DMA1_BASE (AHB1PERIPH_BASE + 0x6000U)
+#define DMA1_Stream0_BASE (DMA1_BASE + 0x010U)
+#define DMA1_Stream1_BASE (DMA1_BASE + 0x028U)
+#define DMA1_Stream2_BASE (DMA1_BASE + 0x040U)
+#define DMA1_Stream3_BASE (DMA1_BASE + 0x058U)
+#define DMA1_Stream4_BASE (DMA1_BASE + 0x070U)
+#define DMA1_Stream5_BASE (DMA1_BASE + 0x088U)
+#define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0U)
+#define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8U)
+#define DMA2_BASE (AHB1PERIPH_BASE + 0x6400U)
+#define DMA2_Stream0_BASE (DMA2_BASE + 0x010U)
+#define DMA2_Stream1_BASE (DMA2_BASE + 0x028U)
+#define DMA2_Stream2_BASE (DMA2_BASE + 0x040U)
+#define DMA2_Stream3_BASE (DMA2_BASE + 0x058U)
+#define DMA2_Stream4_BASE (DMA2_BASE + 0x070U)
+#define DMA2_Stream5_BASE (DMA2_BASE + 0x088U)
+#define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0U)
+#define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8U)
+
+/*!< AHB2 peripherals */
+#define RNG_BASE (AHB2PERIPH_BASE + 0x60800U)
+
+/*!< FSMC Bankx registers base address */
+#define FSMC_Bank1_R_BASE (FSMC_R_BASE + 0x0000U)
+#define FSMC_Bank1E_R_BASE (FSMC_R_BASE + 0x0104U)
+
+/* Debug MCU registers base address */
+#define DBGMCU_BASE 0xE0042000U
+
+/*!< USB registers base address */
+#define USB_OTG_FS_PERIPH_BASE 0x50000000U
+
+#define USB_OTG_GLOBAL_BASE 0x000U
+#define USB_OTG_DEVICE_BASE 0x800U
+#define USB_OTG_IN_ENDPOINT_BASE 0x900U
+#define USB_OTG_OUT_ENDPOINT_BASE 0xB00U
+#define USB_OTG_EP_REG_SIZE 0x20U
+#define USB_OTG_HOST_BASE 0x400U
+#define USB_OTG_HOST_PORT_BASE 0x440U
+#define USB_OTG_HOST_CHANNEL_BASE 0x500U
+#define USB_OTG_HOST_CHANNEL_SIZE 0x20U
+#define USB_OTG_PCGCCTL_BASE 0xE00U
+#define USB_OTG_FIFO_BASE 0x1000U
+#define USB_OTG_FIFO_SIZE 0x1000U
+
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_declaration
+ * @{
+ */
+#define TIM2 ((TIM_TypeDef *) TIM2_BASE)
+#define TIM3 ((TIM_TypeDef *) TIM3_BASE)
+#define TIM4 ((TIM_TypeDef *) TIM4_BASE)
+#define TIM5 ((TIM_TypeDef *) TIM5_BASE)
+#define TIM6 ((TIM_TypeDef *) TIM6_BASE)
+#define TIM7 ((TIM_TypeDef *) TIM7_BASE)
+#define TIM12 ((TIM_TypeDef *) TIM12_BASE)
+#define TIM13 ((TIM_TypeDef *) TIM13_BASE)
+#define TIM14 ((TIM_TypeDef *) TIM14_BASE)
+#define RTC ((RTC_TypeDef *) RTC_BASE)
+#define WWDG ((WWDG_TypeDef *) WWDG_BASE)
+#define IWDG ((IWDG_TypeDef *) IWDG_BASE)
+#define I2S2ext ((SPI_TypeDef *) I2S2ext_BASE)
+#define SPI2 ((SPI_TypeDef *) SPI2_BASE)
+#define SPI3 ((SPI_TypeDef *) SPI3_BASE)
+#define I2S3ext ((SPI_TypeDef *) I2S3ext_BASE)
+#define USART2 ((USART_TypeDef *) USART2_BASE)
+#define USART3 ((USART_TypeDef *) USART3_BASE)
+#define I2C1 ((I2C_TypeDef *) I2C1_BASE)
+#define I2C2 ((I2C_TypeDef *) I2C2_BASE)
+#define I2C3 ((I2C_TypeDef *) I2C3_BASE)
+#define FMPI2C1 ((FMPI2C_TypeDef *) FMPI2C1_BASE)
+#define CAN1 ((CAN_TypeDef *) CAN1_BASE)
+#define CAN2 ((CAN_TypeDef *) CAN2_BASE)
+#define PWR ((PWR_TypeDef *) PWR_BASE)
+#define TIM1 ((TIM_TypeDef *) TIM1_BASE)
+#define TIM8 ((TIM_TypeDef *) TIM8_BASE)
+#define USART1 ((USART_TypeDef *) USART1_BASE)
+#define USART6 ((USART_TypeDef *) USART6_BASE)
+#define ADC ((ADC_Common_TypeDef *) ADC_BASE)
+#define ADC1 ((ADC_TypeDef *) ADC1_BASE)
+#define SDIO ((SDIO_TypeDef *) SDIO_BASE)
+#define SPI1 ((SPI_TypeDef *) SPI1_BASE)
+#define SPI4 ((SPI_TypeDef *) SPI4_BASE)
+#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
+#define EXTI ((EXTI_TypeDef *) EXTI_BASE)
+#define TIM9 ((TIM_TypeDef *) TIM9_BASE)
+#define TIM10 ((TIM_TypeDef *) TIM10_BASE)
+#define TIM11 ((TIM_TypeDef *) TIM11_BASE)
+#define SPI5 ((SPI_TypeDef *) SPI5_BASE)
+#define DFSDM1_Channel0 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel0_BASE)
+#define DFSDM1_Channel1 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel1_BASE)
+#define DFSDM1_Channel2 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel2_BASE)
+#define DFSDM1_Channel3 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel3_BASE)
+#define DFSDM1_Filter0 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter0_BASE)
+#define DFSDM1_Filter1 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter1_BASE)
+#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
+#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
+#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
+#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
+#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
+#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
+#define GPIOG ((GPIO_TypeDef *) GPIOG_BASE)
+#define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
+#define CRC ((CRC_TypeDef *) CRC_BASE)
+#define RCC ((RCC_TypeDef *) RCC_BASE)
+#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
+#define DMA1 ((DMA_TypeDef *) DMA1_BASE)
+#define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)
+#define DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)
+#define DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)
+#define DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)
+#define DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)
+#define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)
+#define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)
+#define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)
+#define DMA2 ((DMA_TypeDef *) DMA2_BASE)
+#define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)
+#define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
+#define DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)
+#define DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)
+#define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)
+#define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)
+#define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)
+#define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)
+#define RNG ((RNG_TypeDef *) RNG_BASE)
+#define FSMC_Bank1 ((FSMC_Bank1_TypeDef *) FSMC_Bank1_R_BASE)
+#define FSMC_Bank1E ((FSMC_Bank1E_TypeDef *) FSMC_Bank1E_R_BASE)
+#define QUADSPI ((QUADSPI_TypeDef *) QSPI_R_BASE)
+
+#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
+
+#define USB_OTG_FS ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE)
+
+/**
+ * @}
+ */
+
+/** @addtogroup Exported_constants
+ * @{
+ */
+
+ /** @addtogroup Peripheral_Registers_Bits_Definition
+ * @{
+ */
+
+/******************************************************************************/
+/* Peripheral Registers_Bits_Definition */
+/******************************************************************************/
+
+/******************************************************************************/
+/* */
+/* Analog to Digital Converter */
+/* */
+/******************************************************************************/
+/******************** Bit definition for ADC_SR register ********************/
+#define ADC_SR_AWD 0x00000001U /*!<Analog watchdog flag */
+#define ADC_SR_EOC 0x00000002U /*!<End of conversion */
+#define ADC_SR_JEOC 0x00000004U /*!<Injected channel end of conversion */
+#define ADC_SR_JSTRT 0x00000008U /*!<Injected channel Start flag */
+#define ADC_SR_STRT 0x00000010U /*!<Regular channel Start flag */
+#define ADC_SR_OVR 0x00000020U /*!<Overrun flag */
+
+/******************* Bit definition for ADC_CR1 register ********************/
+#define ADC_CR1_AWDCH 0x0000001FU /*!<AWDCH[4:0] bits (Analog watchdog channel select bits) */
+#define ADC_CR1_AWDCH_0 0x00000001U /*!<Bit 0 */
+#define ADC_CR1_AWDCH_1 0x00000002U /*!<Bit 1 */
+#define ADC_CR1_AWDCH_2 0x00000004U /*!<Bit 2 */
+#define ADC_CR1_AWDCH_3 0x00000008U /*!<Bit 3 */
+#define ADC_CR1_AWDCH_4 0x00000010U /*!<Bit 4 */
+#define ADC_CR1_EOCIE 0x00000020U /*!<Interrupt enable for EOC */
+#define ADC_CR1_AWDIE 0x00000040U /*!<AAnalog Watchdog interrupt enable */
+#define ADC_CR1_JEOCIE 0x00000080U /*!<Interrupt enable for injected channels */
+#define ADC_CR1_SCAN 0x00000100U /*!<Scan mode */
+#define ADC_CR1_AWDSGL 0x00000200U /*!<Enable the watchdog on a single channel in scan mode */
+#define ADC_CR1_JAUTO 0x00000400U /*!<Automatic injected group conversion */
+#define ADC_CR1_DISCEN 0x00000800U /*!<Discontinuous mode on regular channels */
+#define ADC_CR1_JDISCEN 0x00001000U /*!<Discontinuous mode on injected channels */
+#define ADC_CR1_DISCNUM 0x0000E000U /*!<DISCNUM[2:0] bits (Discontinuous mode channel count) */
+#define ADC_CR1_DISCNUM_0 0x00002000U /*!<Bit 0 */
+#define ADC_CR1_DISCNUM_1 0x00004000U /*!<Bit 1 */
+#define ADC_CR1_DISCNUM_2 0x00008000U /*!<Bit 2 */
+#define ADC_CR1_JAWDEN 0x00400000U /*!<Analog watchdog enable on injected channels */
+#define ADC_CR1_AWDEN 0x00800000U /*!<Analog watchdog enable on regular channels */
+#define ADC_CR1_RES 0x03000000U /*!<RES[2:0] bits (Resolution) */
+#define ADC_CR1_RES_0 0x01000000U /*!<Bit 0 */
+#define ADC_CR1_RES_1 0x02000000U /*!<Bit 1 */
+#define ADC_CR1_OVRIE 0x04000000U /*!<overrun interrupt enable */
+
+/******************* Bit definition for ADC_CR2 register ********************/
+#define ADC_CR2_ADON 0x00000001U /*!<A/D Converter ON / OFF */
+#define ADC_CR2_CONT 0x00000002U /*!<Continuous Conversion */
+#define ADC_CR2_DMA 0x00000100U /*!<Direct Memory access mode */
+#define ADC_CR2_DDS 0x00000200U /*!<DMA disable selection (Single ADC) */
+#define ADC_CR2_EOCS 0x00000400U /*!<End of conversion selection */
+#define ADC_CR2_ALIGN 0x00000800U /*!<Data Alignment */
+#define ADC_CR2_JEXTSEL 0x000F0000U /*!<JEXTSEL[3:0] bits (External event select for injected group) */
+#define ADC_CR2_JEXTSEL_0 0x00010000U /*!<Bit 0 */
+#define ADC_CR2_JEXTSEL_1 0x00020000U /*!<Bit 1 */
+#define ADC_CR2_JEXTSEL_2 0x00040000U /*!<Bit 2 */
+#define ADC_CR2_JEXTSEL_3 0x00080000U /*!<Bit 3 */
+#define ADC_CR2_JEXTEN 0x00300000U /*!<JEXTEN[1:0] bits (External Trigger Conversion mode for injected channelsp) */
+#define ADC_CR2_JEXTEN_0 0x00100000U /*!<Bit 0 */
+#define ADC_CR2_JEXTEN_1 0x00200000U /*!<Bit 1 */
+#define ADC_CR2_JSWSTART 0x00400000U /*!<Start Conversion of injected channels */
+#define ADC_CR2_EXTSEL 0x0F000000U /*!<EXTSEL[3:0] bits (External Event Select for regular group) */
+#define ADC_CR2_EXTSEL_0 0x01000000U /*!<Bit 0 */
+#define ADC_CR2_EXTSEL_1 0x02000000U /*!<Bit 1 */
+#define ADC_CR2_EXTSEL_2 0x04000000U /*!<Bit 2 */
+#define ADC_CR2_EXTSEL_3 0x08000000U /*!<Bit 3 */
+#define ADC_CR2_EXTEN 0x30000000U /*!<EXTEN[1:0] bits (External Trigger Conversion mode for regular channelsp) */
+#define ADC_CR2_EXTEN_0 0x10000000U /*!<Bit 0 */
+#define ADC_CR2_EXTEN_1 0x20000000U /*!<Bit 1 */
+#define ADC_CR2_SWSTART 0x40000000U /*!<Start Conversion of regular channels */
+
+/****************** Bit definition for ADC_SMPR1 register *******************/
+#define ADC_SMPR1_SMP10 0x00000007U /*!<SMP10[2:0] bits (Channel 10 Sample time selection) */
+#define ADC_SMPR1_SMP10_0 0x00000001U /*!<Bit 0 */
+#define ADC_SMPR1_SMP10_1 0x00000002U /*!<Bit 1 */
+#define ADC_SMPR1_SMP10_2 0x00000004U /*!<Bit 2 */
+#define ADC_SMPR1_SMP11 0x00000038U /*!<SMP11[2:0] bits (Channel 11 Sample time selection) */
+#define ADC_SMPR1_SMP11_0 0x00000008U /*!<Bit 0 */
+#define ADC_SMPR1_SMP11_1 0x00000010U /*!<Bit 1 */
+#define ADC_SMPR1_SMP11_2 0x00000020U /*!<Bit 2 */
+#define ADC_SMPR1_SMP12 0x000001C0U /*!<SMP12[2:0] bits (Channel 12 Sample time selection) */
+#define ADC_SMPR1_SMP12_0 0x00000040U /*!<Bit 0 */
+#define ADC_SMPR1_SMP12_1 0x00000080U /*!<Bit 1 */
+#define ADC_SMPR1_SMP12_2 0x00000100U /*!<Bit 2 */
+#define ADC_SMPR1_SMP13 0x00000E00U /*!<SMP13[2:0] bits (Channel 13 Sample time selection) */
+#define ADC_SMPR1_SMP13_0 0x00000200U /*!<Bit 0 */
+#define ADC_SMPR1_SMP13_1 0x00000400U /*!<Bit 1 */
+#define ADC_SMPR1_SMP13_2 0x00000800U /*!<Bit 2 */
+#define ADC_SMPR1_SMP14 0x00007000U /*!<SMP14[2:0] bits (Channel 14 Sample time selection) */
+#define ADC_SMPR1_SMP14_0 0x00001000U /*!<Bit 0 */
+#define ADC_SMPR1_SMP14_1 0x00002000U /*!<Bit 1 */
+#define ADC_SMPR1_SMP14_2 0x00004000U /*!<Bit 2 */
+#define ADC_SMPR1_SMP15 0x00038000U /*!<SMP15[2:0] bits (Channel 15 Sample time selection) */
+#define ADC_SMPR1_SMP15_0 0x00008000U /*!<Bit 0 */
+#define ADC_SMPR1_SMP15_1 0x00010000U /*!<Bit 1 */
+#define ADC_SMPR1_SMP15_2 0x00020000U /*!<Bit 2 */
+#define ADC_SMPR1_SMP16 0x001C0000U /*!<SMP16[2:0] bits (Channel 16 Sample time selection) */
+#define ADC_SMPR1_SMP16_0 0x00040000U /*!<Bit 0 */
+#define ADC_SMPR1_SMP16_1 0x00080000U /*!<Bit 1 */
+#define ADC_SMPR1_SMP16_2 0x00100000U /*!<Bit 2 */
+#define ADC_SMPR1_SMP17 0x00E00000U /*!<SMP17[2:0] bits (Channel 17 Sample time selection) */
+#define ADC_SMPR1_SMP17_0 0x00200000U /*!<Bit 0 */
+#define ADC_SMPR1_SMP17_1 0x00400000U /*!<Bit 1 */
+#define ADC_SMPR1_SMP17_2 0x00800000U /*!<Bit 2 */
+#define ADC_SMPR1_SMP18 0x07000000U /*!<SMP18[2:0] bits (Channel 18 Sample time selection) */
+#define ADC_SMPR1_SMP18_0 0x01000000U /*!<Bit 0 */
+#define ADC_SMPR1_SMP18_1 0x02000000U /*!<Bit 1 */
+#define ADC_SMPR1_SMP18_2 0x04000000U /*!<Bit 2 */
+
+/****************** Bit definition for ADC_SMPR2 register *******************/
+#define ADC_SMPR2_SMP0 0x00000007U /*!<SMP0[2:0] bits (Channel 0 Sample time selection) */
+#define ADC_SMPR2_SMP0_0 0x00000001U /*!<Bit 0 */
+#define ADC_SMPR2_SMP0_1 0x00000002U /*!<Bit 1 */
+#define ADC_SMPR2_SMP0_2 0x00000004U /*!<Bit 2 */
+#define ADC_SMPR2_SMP1 0x00000038U /*!<SMP1[2:0] bits (Channel 1 Sample time selection) */
+#define ADC_SMPR2_SMP1_0 0x00000008U /*!<Bit 0 */
+#define ADC_SMPR2_SMP1_1 0x00000010U /*!<Bit 1 */
+#define ADC_SMPR2_SMP1_2 0x00000020U /*!<Bit 2 */
+#define ADC_SMPR2_SMP2 0x000001C0U /*!<SMP2[2:0] bits (Channel 2 Sample time selection) */
+#define ADC_SMPR2_SMP2_0 0x00000040U /*!<Bit 0 */
+#define ADC_SMPR2_SMP2_1 0x00000080U /*!<Bit 1 */
+#define ADC_SMPR2_SMP2_2 0x00000100U /*!<Bit 2 */
+#define ADC_SMPR2_SMP3 0x00000E00U /*!<SMP3[2:0] bits (Channel 3 Sample time selection) */
+#define ADC_SMPR2_SMP3_0 0x00000200U /*!<Bit 0 */
+#define ADC_SMPR2_SMP3_1 0x00000400U /*!<Bit 1 */
+#define ADC_SMPR2_SMP3_2 0x00000800U /*!<Bit 2 */
+#define ADC_SMPR2_SMP4 0x00007000U /*!<SMP4[2:0] bits (Channel 4 Sample time selection) */
+#define ADC_SMPR2_SMP4_0 0x00001000U /*!<Bit 0 */
+#define ADC_SMPR2_SMP4_1 0x00002000U /*!<Bit 1 */
+#define ADC_SMPR2_SMP4_2 0x00004000U /*!<Bit 2 */
+#define ADC_SMPR2_SMP5 0x00038000U /*!<SMP5[2:0] bits (Channel 5 Sample time selection) */
+#define ADC_SMPR2_SMP5_0 0x00008000U /*!<Bit 0 */
+#define ADC_SMPR2_SMP5_1 0x00010000U /*!<Bit 1 */
+#define ADC_SMPR2_SMP5_2 0x00020000U /*!<Bit 2 */
+#define ADC_SMPR2_SMP6 0x001C0000U /*!<SMP6[2:0] bits (Channel 6 Sample time selection) */
+#define ADC_SMPR2_SMP6_0 0x00040000U /*!<Bit 0 */
+#define ADC_SMPR2_SMP6_1 0x00080000U /*!<Bit 1 */
+#define ADC_SMPR2_SMP6_2 0x00100000U /*!<Bit 2 */
+#define ADC_SMPR2_SMP7 0x00E00000U /*!<SMP7[2:0] bits (Channel 7 Sample time selection) */
+#define ADC_SMPR2_SMP7_0 0x00200000U /*!<Bit 0 */
+#define ADC_SMPR2_SMP7_1 0x00400000U /*!<Bit 1 */
+#define ADC_SMPR2_SMP7_2 0x00800000U /*!<Bit 2 */
+#define ADC_SMPR2_SMP8 0x07000000U /*!<SMP8[2:0] bits (Channel 8 Sample time selection) */
+#define ADC_SMPR2_SMP8_0 0x01000000U /*!<Bit 0 */
+#define ADC_SMPR2_SMP8_1 0x02000000U /*!<Bit 1 */
+#define ADC_SMPR2_SMP8_2 0x04000000U /*!<Bit 2 */
+#define ADC_SMPR2_SMP9 0x38000000U /*!<SMP9[2:0] bits (Channel 9 Sample time selection) */
+#define ADC_SMPR2_SMP9_0 0x08000000U /*!<Bit 0 */
+#define ADC_SMPR2_SMP9_1 0x10000000U /*!<Bit 1 */
+#define ADC_SMPR2_SMP9_2 0x20000000U /*!<Bit 2 */
+
+/****************** Bit definition for ADC_JOFR1 register *******************/
+#define ADC_JOFR1_JOFFSET1 0x0FFFU /*!<Data offset for injected channel 1 */
+
+/****************** Bit definition for ADC_JOFR2 register *******************/
+#define ADC_JOFR2_JOFFSET2 0x0FFFU /*!<Data offset for injected channel 2 */
+
+/****************** Bit definition for ADC_JOFR3 register *******************/
+#define ADC_JOFR3_JOFFSET3 0x0FFFU /*!<Data offset for injected channel 3 */
+
+/****************** Bit definition for ADC_JOFR4 register *******************/
+#define ADC_JOFR4_JOFFSET4 0x0FFFU /*!<Data offset for injected channel 4 */
+
+/******************* Bit definition for ADC_HTR register ********************/
+#define ADC_HTR_HT 0x0FFFU /*!<Analog watchdog high threshold */
+
+/******************* Bit definition for ADC_LTR register ********************/
+#define ADC_LTR_LT 0x0FFFU /*!<Analog watchdog low threshold */
+
+/******************* Bit definition for ADC_SQR1 register *******************/
+#define ADC_SQR1_SQ13 0x0000001FU /*!<SQ13[4:0] bits (13th conversion in regular sequence) */
+#define ADC_SQR1_SQ13_0 0x00000001U /*!<Bit 0 */
+#define ADC_SQR1_SQ13_1 0x00000002U /*!<Bit 1 */
+#define ADC_SQR1_SQ13_2 0x00000004U /*!<Bit 2 */
+#define ADC_SQR1_SQ13_3 0x00000008U /*!<Bit 3 */
+#define ADC_SQR1_SQ13_4 0x00000010U /*!<Bit 4 */
+#define ADC_SQR1_SQ14 0x000003E0U /*!<SQ14[4:0] bits (14th conversion in regular sequence) */
+#define ADC_SQR1_SQ14_0 0x00000020U /*!<Bit 0 */
+#define ADC_SQR1_SQ14_1 0x00000040U /*!<Bit 1 */
+#define ADC_SQR1_SQ14_2 0x00000080U /*!<Bit 2 */
+#define ADC_SQR1_SQ14_3 0x00000100U /*!<Bit 3 */
+#define ADC_SQR1_SQ14_4 0x00000200U /*!<Bit 4 */
+#define ADC_SQR1_SQ15 0x00007C00U /*!<SQ15[4:0] bits (15th conversion in regular sequence) */
+#define ADC_SQR1_SQ15_0 0x00000400U /*!<Bit 0 */
+#define ADC_SQR1_SQ15_1 0x00000800U /*!<Bit 1 */
+#define ADC_SQR1_SQ15_2 0x00001000U /*!<Bit 2 */
+#define ADC_SQR1_SQ15_3 0x00002000U /*!<Bit 3 */
+#define ADC_SQR1_SQ15_4 0x00004000U /*!<Bit 4 */
+#define ADC_SQR1_SQ16 0x000F8000U /*!<SQ16[4:0] bits (16th conversion in regular sequence) */
+#define ADC_SQR1_SQ16_0 0x00008000U /*!<Bit 0 */
+#define ADC_SQR1_SQ16_1 0x00010000U /*!<Bit 1 */
+#define ADC_SQR1_SQ16_2 0x00020000U /*!<Bit 2 */
+#define ADC_SQR1_SQ16_3 0x00040000U /*!<Bit 3 */
+#define ADC_SQR1_SQ16_4 0x00080000U /*!<Bit 4 */
+#define ADC_SQR1_L 0x00F00000U /*!<L[3:0] bits (Regular channel sequence length) */
+#define ADC_SQR1_L_0 0x00100000U /*!<Bit 0 */
+#define ADC_SQR1_L_1 0x00200000U /*!<Bit 1 */
+#define ADC_SQR1_L_2 0x00400000U /*!<Bit 2 */
+#define ADC_SQR1_L_3 0x00800000U /*!<Bit 3 */
+
+/******************* Bit definition for ADC_SQR2 register *******************/
+#define ADC_SQR2_SQ7 0x0000001FU /*!<SQ7[4:0] bits (7th conversion in regular sequence) */
+#define ADC_SQR2_SQ7_0 0x00000001U /*!<Bit 0 */
+#define ADC_SQR2_SQ7_1 0x00000002U /*!<Bit 1 */
+#define ADC_SQR2_SQ7_2 0x00000004U /*!<Bit 2 */
+#define ADC_SQR2_SQ7_3 0x00000008U /*!<Bit 3 */
+#define ADC_SQR2_SQ7_4 0x00000010U /*!<Bit 4 */
+#define ADC_SQR2_SQ8 0x000003E0U /*!<SQ8[4:0] bits (8th conversion in regular sequence) */
+#define ADC_SQR2_SQ8_0 0x00000020U /*!<Bit 0 */
+#define ADC_SQR2_SQ8_1 0x00000040U /*!<Bit 1 */
+#define ADC_SQR2_SQ8_2 0x00000080U /*!<Bit 2 */
+#define ADC_SQR2_SQ8_3 0x00000100U /*!<Bit 3 */
+#define ADC_SQR2_SQ8_4 0x00000200U /*!<Bit 4 */
+#define ADC_SQR2_SQ9 0x00007C00U /*!<SQ9[4:0] bits (9th conversion in regular sequence) */
+#define ADC_SQR2_SQ9_0 0x00000400U /*!<Bit 0 */
+#define ADC_SQR2_SQ9_1 0x00000800U /*!<Bit 1 */
+#define ADC_SQR2_SQ9_2 0x00001000U /*!<Bit 2 */
+#define ADC_SQR2_SQ9_3 0x00002000U /*!<Bit 3 */
+#define ADC_SQR2_SQ9_4 0x00004000U /*!<Bit 4 */
+#define ADC_SQR2_SQ10 0x000F8000U /*!<SQ10[4:0] bits (10th conversion in regular sequence) */
+#define ADC_SQR2_SQ10_0 0x00008000U /*!<Bit 0 */
+#define ADC_SQR2_SQ10_1 0x00010000U /*!<Bit 1 */
+#define ADC_SQR2_SQ10_2 0x00020000U /*!<Bit 2 */
+#define ADC_SQR2_SQ10_3 0x00040000U /*!<Bit 3 */
+#define ADC_SQR2_SQ10_4 0x00080000U /*!<Bit 4 */
+#define ADC_SQR2_SQ11 0x01F00000U /*!<SQ11[4:0] bits (11th conversion in regular sequence) */
+#define ADC_SQR2_SQ11_0 0x00100000U /*!<Bit 0 */
+#define ADC_SQR2_SQ11_1 0x00200000U /*!<Bit 1 */
+#define ADC_SQR2_SQ11_2 0x00400000U /*!<Bit 2 */
+#define ADC_SQR2_SQ11_3 0x00800000U /*!<Bit 3 */
+#define ADC_SQR2_SQ11_4 0x01000000U /*!<Bit 4 */
+#define ADC_SQR2_SQ12 0x3E000000U /*!<SQ12[4:0] bits (12th conversion in regular sequence) */
+#define ADC_SQR2_SQ12_0 0x02000000U /*!<Bit 0 */
+#define ADC_SQR2_SQ12_1 0x04000000U /*!<Bit 1 */
+#define ADC_SQR2_SQ12_2 0x08000000U /*!<Bit 2 */
+#define ADC_SQR2_SQ12_3 0x10000000U /*!<Bit 3 */
+#define ADC_SQR2_SQ12_4 0x20000000U /*!<Bit 4 */
+
+/******************* Bit definition for ADC_SQR3 register *******************/
+#define ADC_SQR3_SQ1 0x0000001FU /*!<SQ1[4:0] bits (1st conversion in regular sequence) */
+#define ADC_SQR3_SQ1_0 0x00000001U /*!<Bit 0 */
+#define ADC_SQR3_SQ1_1 0x00000002U /*!<Bit 1 */
+#define ADC_SQR3_SQ1_2 0x00000004U /*!<Bit 2 */
+#define ADC_SQR3_SQ1_3 0x00000008U /*!<Bit 3 */
+#define ADC_SQR3_SQ1_4 0x00000010U /*!<Bit 4 */
+#define ADC_SQR3_SQ2 0x000003E0U /*!<SQ2[4:0] bits (2nd conversion in regular sequence) */
+#define ADC_SQR3_SQ2_0 0x00000020U /*!<Bit 0 */
+#define ADC_SQR3_SQ2_1 0x00000040U /*!<Bit 1 */
+#define ADC_SQR3_SQ2_2 0x00000080U /*!<Bit 2 */
+#define ADC_SQR3_SQ2_3 0x00000100U /*!<Bit 3 */
+#define ADC_SQR3_SQ2_4 0x00000200U /*!<Bit 4 */
+#define ADC_SQR3_SQ3 0x00007C00U /*!<SQ3[4:0] bits (3rd conversion in regular sequence) */
+#define ADC_SQR3_SQ3_0 0x00000400U /*!<Bit 0 */
+#define ADC_SQR3_SQ3_1 0x00000800U /*!<Bit 1 */
+#define ADC_SQR3_SQ3_2 0x00001000U /*!<Bit 2 */
+#define ADC_SQR3_SQ3_3 0x00002000U /*!<Bit 3 */
+#define ADC_SQR3_SQ3_4 0x00004000U /*!<Bit 4 */
+#define ADC_SQR3_SQ4 0x000F8000U /*!<SQ4[4:0] bits (4th conversion in regular sequence) */
+#define ADC_SQR3_SQ4_0 0x00008000U /*!<Bit 0 */
+#define ADC_SQR3_SQ4_1 0x00010000U /*!<Bit 1 */
+#define ADC_SQR3_SQ4_2 0x00020000U /*!<Bit 2 */
+#define ADC_SQR3_SQ4_3 0x00040000U /*!<Bit 3 */
+#define ADC_SQR3_SQ4_4 0x00080000U /*!<Bit 4 */
+#define ADC_SQR3_SQ5 0x01F00000U /*!<SQ5[4:0] bits (5th conversion in regular sequence) */
+#define ADC_SQR3_SQ5_0 0x00100000U /*!<Bit 0 */
+#define ADC_SQR3_SQ5_1 0x00200000U /*!<Bit 1 */
+#define ADC_SQR3_SQ5_2 0x00400000U /*!<Bit 2 */
+#define ADC_SQR3_SQ5_3 0x00800000U /*!<Bit 3 */
+#define ADC_SQR3_SQ5_4 0x01000000U /*!<Bit 4 */
+#define ADC_SQR3_SQ6 0x3E000000U /*!<SQ6[4:0] bits (6th conversion in regular sequence) */
+#define ADC_SQR3_SQ6_0 0x02000000U /*!<Bit 0 */
+#define ADC_SQR3_SQ6_1 0x04000000U /*!<Bit 1 */
+#define ADC_SQR3_SQ6_2 0x08000000U /*!<Bit 2 */
+#define ADC_SQR3_SQ6_3 0x10000000U /*!<Bit 3 */
+#define ADC_SQR3_SQ6_4 0x20000000U /*!<Bit 4 */
+
+/******************* Bit definition for ADC_JSQR register *******************/
+#define ADC_JSQR_JSQ1 0x0000001FU /*!<JSQ1[4:0] bits (1st conversion in injected sequence) */
+#define ADC_JSQR_JSQ1_0 0x00000001U /*!<Bit 0 */
+#define ADC_JSQR_JSQ1_1 0x00000002U /*!<Bit 1 */
+#define ADC_JSQR_JSQ1_2 0x00000004U /*!<Bit 2 */
+#define ADC_JSQR_JSQ1_3 0x00000008U /*!<Bit 3 */
+#define ADC_JSQR_JSQ1_4 0x00000010U /*!<Bit 4 */
+#define ADC_JSQR_JSQ2 0x000003E0U /*!<JSQ2[4:0] bits (2nd conversion in injected sequence) */
+#define ADC_JSQR_JSQ2_0 0x00000020U /*!<Bit 0 */
+#define ADC_JSQR_JSQ2_1 0x00000040U /*!<Bit 1 */
+#define ADC_JSQR_JSQ2_2 0x00000080U /*!<Bit 2 */
+#define ADC_JSQR_JSQ2_3 0x00000100U /*!<Bit 3 */
+#define ADC_JSQR_JSQ2_4 0x00000200U /*!<Bit 4 */
+#define ADC_JSQR_JSQ3 0x00007C00U /*!<JSQ3[4:0] bits (3rd conversion in injected sequence) */
+#define ADC_JSQR_JSQ3_0 0x00000400U /*!<Bit 0 */
+#define ADC_JSQR_JSQ3_1 0x00000800U /*!<Bit 1 */
+#define ADC_JSQR_JSQ3_2 0x00001000U /*!<Bit 2 */
+#define ADC_JSQR_JSQ3_3 0x00002000U /*!<Bit 3 */
+#define ADC_JSQR_JSQ3_4 0x00004000U /*!<Bit 4 */
+#define ADC_JSQR_JSQ4 0x000F8000U /*!<JSQ4[4:0] bits (4th conversion in injected sequence) */
+#define ADC_JSQR_JSQ4_0 0x00008000U /*!<Bit 0 */
+#define ADC_JSQR_JSQ4_1 0x00010000U /*!<Bit 1 */
+#define ADC_JSQR_JSQ4_2 0x00020000U /*!<Bit 2 */
+#define ADC_JSQR_JSQ4_3 0x00040000U /*!<Bit 3 */
+#define ADC_JSQR_JSQ4_4 0x00080000U /*!<Bit 4 */
+#define ADC_JSQR_JL 0x00300000U /*!<JL[1:0] bits (Injected Sequence length) */
+#define ADC_JSQR_JL_0 0x00100000U /*!<Bit 0 */
+#define ADC_JSQR_JL_1 0x00200000U /*!<Bit 1 */
+
+/******************* Bit definition for ADC_JDR1 register *******************/
+#define ADC_JDR1_JDATA 0xFFFFU /*!<Injected data */
+
+/******************* Bit definition for ADC_JDR2 register *******************/
+#define ADC_JDR2_JDATA 0xFFFFU /*!<Injected data */
+
+/******************* Bit definition for ADC_JDR3 register *******************/
+#define ADC_JDR3_JDATA 0xFFFFU /*!<Injected data */
+
+/******************* Bit definition for ADC_JDR4 register *******************/
+#define ADC_JDR4_JDATA 0xFFFFU /*!<Injected data */
+
+/******************** Bit definition for ADC_DR register ********************/
+#define ADC_DR_DATA 0x0000FFFFU /*!<Regular data */
+#define ADC_DR_ADC2DATA 0xFFFF0000U /*!<ADC2 data */
+
+/******************* Bit definition for ADC_CSR register ********************/
+#define ADC_CSR_AWD1 0x00000001U /*!<ADC1 Analog watchdog flag */
+#define ADC_CSR_EOC1 0x00000002U /*!<ADC1 End of conversion */
+#define ADC_CSR_JEOC1 0x00000004U /*!<ADC1 Injected channel end of conversion */
+#define ADC_CSR_JSTRT1 0x00000008U /*!<ADC1 Injected channel Start flag */
+#define ADC_CSR_STRT1 0x00000010U /*!<ADC1 Regular channel Start flag */
+#define ADC_CSR_DOVR1 0x00000020U /*!<ADC1 DMA overrun flag */
+#define ADC_CSR_AWD2 0x00000100U /*!<ADC2 Analog watchdog flag */
+#define ADC_CSR_EOC2 0x00000200U /*!<ADC2 End of conversion */
+#define ADC_CSR_JEOC2 0x00000400U /*!<ADC2 Injected channel end of conversion */
+#define ADC_CSR_JSTRT2 0x00000800U /*!<ADC2 Injected channel Start flag */
+#define ADC_CSR_STRT2 0x00001000U /*!<ADC2 Regular channel Start flag */
+#define ADC_CSR_DOVR2 0x00002000U /*!<ADC2 DMA overrun flag */
+
+/******************* Bit definition for ADC_CCR register ********************/
+#define ADC_CCR_MULTI 0x0000001FU /*!<MULTI[4:0] bits (Multi-ADC mode selection) */
+#define ADC_CCR_MULTI_0 0x00000001U /*!<Bit 0 */
+#define ADC_CCR_MULTI_1 0x00000002U /*!<Bit 1 */
+#define ADC_CCR_MULTI_2 0x00000004U /*!<Bit 2 */
+#define ADC_CCR_MULTI_3 0x00000008U /*!<Bit 3 */
+#define ADC_CCR_MULTI_4 0x00000010U /*!<Bit 4 */
+#define ADC_CCR_DELAY 0x00000F00U /*!<DELAY[3:0] bits (Delay between 2 sampling phases) */
+#define ADC_CCR_DELAY_0 0x00000100U /*!<Bit 0 */
+#define ADC_CCR_DELAY_1 0x00000200U /*!<Bit 1 */
+#define ADC_CCR_DELAY_2 0x00000400U /*!<Bit 2 */
+#define ADC_CCR_DELAY_3 0x00000800U /*!<Bit 3 */
+#define ADC_CCR_DDS 0x00002000U /*!<DMA disable selection (Multi-ADC mode) */
+#define ADC_CCR_DMA 0x0000C000U /*!<DMA[1:0] bits (Direct Memory Access mode for multimode) */
+#define ADC_CCR_DMA_0 0x00004000U /*!<Bit 0 */
+#define ADC_CCR_DMA_1 0x00008000U /*!<Bit 1 */
+#define ADC_CCR_ADCPRE 0x00030000U /*!<ADCPRE[1:0] bits (ADC prescaler) */
+#define ADC_CCR_ADCPRE_0 0x00010000U /*!<Bit 0 */
+#define ADC_CCR_ADCPRE_1 0x00020000U /*!<Bit 1 */
+#define ADC_CCR_VBATE 0x00400000U /*!<VBAT Enable */
+#define ADC_CCR_TSVREFE 0x00800000U /*!<Temperature Sensor and VREFINT Enable */
+
+/******************* Bit definition for ADC_CDR register ********************/
+#define ADC_CDR_DATA1 0x0000FFFFU /*!<1st data of a pair of regular conversions */
+#define ADC_CDR_DATA2 0xFFFF0000U /*!<2nd data of a pair of regular conversions */
+
+/******************************************************************************/
+/* */
+/* Controller Area Network */
+/* */
+/******************************************************************************/
+/*!<CAN control and status registers */
+/******************* Bit definition for CAN_MCR register ********************/
+#define CAN_MCR_INRQ 0x00000001U /*!<Initialization Request */
+#define CAN_MCR_SLEEP 0x00000002U /*!<Sleep Mode Request */
+#define CAN_MCR_TXFP 0x00000004U /*!<Transmit FIFO Priority */
+#define CAN_MCR_RFLM 0x00000008U /*!<Receive FIFO Locked Mode */
+#define CAN_MCR_NART 0x00000010U /*!<No Automatic Retransmission */
+#define CAN_MCR_AWUM 0x00000020U /*!<Automatic Wakeup Mode */
+#define CAN_MCR_ABOM 0x00000040U /*!<Automatic Bus-Off Management */
+#define CAN_MCR_TTCM 0x00000080U /*!<Time Triggered Communication Mode */
+#define CAN_MCR_RESET 0x00008000U /*!<bxCAN software master reset */
+#define CAN_MCR_DBF 0x00010000U /*!<bxCAN Debug freeze */
+/******************* Bit definition for CAN_MSR register ********************/
+#define CAN_MSR_INAK 0x0001U /*!<Initialization Acknowledge */
+#define CAN_MSR_SLAK 0x0002U /*!<Sleep Acknowledge */
+#define CAN_MSR_ERRI 0x0004U /*!<Error Interrupt */
+#define CAN_MSR_WKUI 0x0008U /*!<Wakeup Interrupt */
+#define CAN_MSR_SLAKI 0x0010U /*!<Sleep Acknowledge Interrupt */
+#define CAN_MSR_TXM 0x0100U /*!<Transmit Mode */
+#define CAN_MSR_RXM 0x0200U /*!<Receive Mode */
+#define CAN_MSR_SAMP 0x0400U /*!<Last Sample Point */
+#define CAN_MSR_RX 0x0800U /*!<CAN Rx Signal */
+
+/******************* Bit definition for CAN_TSR register ********************/
+#define CAN_TSR_RQCP0 0x00000001U /*!<Request Completed Mailbox0 */
+#define CAN_TSR_TXOK0 0x00000002U /*!<Transmission OK of Mailbox0 */
+#define CAN_TSR_ALST0 0x00000004U /*!<Arbitration Lost for Mailbox0 */
+#define CAN_TSR_TERR0 0x00000008U /*!<Transmission Error of Mailbox0 */
+#define CAN_TSR_ABRQ0 0x00000080U /*!<Abort Request for Mailbox0 */
+#define CAN_TSR_RQCP1 0x00000100U /*!<Request Completed Mailbox1 */
+#define CAN_TSR_TXOK1 0x00000200U /*!<Transmission OK of Mailbox1 */
+#define CAN_TSR_ALST1 0x00000400U /*!<Arbitration Lost for Mailbox1 */
+#define CAN_TSR_TERR1 0x00000800U /*!<Transmission Error of Mailbox1 */
+#define CAN_TSR_ABRQ1 0x00008000U /*!<Abort Request for Mailbox 1 */
+#define CAN_TSR_RQCP2 0x00010000U /*!<Request Completed Mailbox2 */
+#define CAN_TSR_TXOK2 0x00020000U /*!<Transmission OK of Mailbox 2 */
+#define CAN_TSR_ALST2 0x00040000U /*!<Arbitration Lost for mailbox 2 */
+#define CAN_TSR_TERR2 0x00080000U /*!<Transmission Error of Mailbox 2 */
+#define CAN_TSR_ABRQ2 0x00800000U /*!<Abort Request for Mailbox 2 */
+#define CAN_TSR_CODE 0x03000000U /*!<Mailbox Code */
+
+#define CAN_TSR_TME 0x1C000000U /*!<TME[2:0] bits */
+#define CAN_TSR_TME0 0x04000000U /*!<Transmit Mailbox 0 Empty */
+#define CAN_TSR_TME1 0x08000000U /*!<Transmit Mailbox 1 Empty */
+#define CAN_TSR_TME2 0x10000000U /*!<Transmit Mailbox 2 Empty */
+
+#define CAN_TSR_LOW 0xE0000000U /*!<LOW[2:0] bits */
+#define CAN_TSR_LOW0 0x20000000U /*!<Lowest Priority Flag for Mailbox 0 */
+#define CAN_TSR_LOW1 0x40000000U /*!<Lowest Priority Flag for Mailbox 1 */
+#define CAN_TSR_LOW2 0x80000000U /*!<Lowest Priority Flag for Mailbox 2 */
+
+/******************* Bit definition for CAN_RF0R register *******************/
+#define CAN_RF0R_FMP0 0x03U /*!<FIFO 0 Message Pending */
+#define CAN_RF0R_FULL0 0x08U /*!<FIFO 0 Full */
+#define CAN_RF0R_FOVR0 0x10U /*!<FIFO 0 Overrun */
+#define CAN_RF0R_RFOM0 0x20U /*!<Release FIFO 0 Output Mailbox */
+
+/******************* Bit definition for CAN_RF1R register *******************/
+#define CAN_RF1R_FMP1 0x03U /*!<FIFO 1 Message Pending */
+#define CAN_RF1R_FULL1 0x08U /*!<FIFO 1 Full */
+#define CAN_RF1R_FOVR1 0x10U /*!<FIFO 1 Overrun */
+#define CAN_RF1R_RFOM1 0x20U /*!<Release FIFO 1 Output Mailbox */
+
+/******************** Bit definition for CAN_IER register *******************/
+#define CAN_IER_TMEIE 0x00000001U /*!<Transmit Mailbox Empty Interrupt Enable */
+#define CAN_IER_FMPIE0 0x00000002U /*!<FIFO Message Pending Interrupt Enable */
+#define CAN_IER_FFIE0 0x00000004U /*!<FIFO Full Interrupt Enable */
+#define CAN_IER_FOVIE0 0x00000008U /*!<FIFO Overrun Interrupt Enable */
+#define CAN_IER_FMPIE1 0x00000010U /*!<FIFO Message Pending Interrupt Enable */
+#define CAN_IER_FFIE1 0x00000020U /*!<FIFO Full Interrupt Enable */
+#define CAN_IER_FOVIE1 0x00000040U /*!<FIFO Overrun Interrupt Enable */
+#define CAN_IER_EWGIE 0x00000100U /*!<Error Warning Interrupt Enable */
+#define CAN_IER_EPVIE 0x00000200U /*!<Error Passive Interrupt Enable */
+#define CAN_IER_BOFIE 0x00000400U /*!<Bus-Off Interrupt Enable */
+#define CAN_IER_LECIE 0x00000800U /*!<Last Error Code Interrupt Enable */
+#define CAN_IER_ERRIE 0x00008000U /*!<Error Interrupt Enable */
+#define CAN_IER_WKUIE 0x00010000U /*!<Wakeup Interrupt Enable */
+#define CAN_IER_SLKIE 0x00020000U /*!<Sleep Interrupt Enable */
+#define CAN_IER_EWGIE 0x00000100U /*!<Error warning interrupt enable */
+#define CAN_IER_EPVIE 0x00000200U /*!<Error passive interrupt enable */
+#define CAN_IER_BOFIE 0x00000400U /*!<Bus-off interrupt enable */
+#define CAN_IER_LECIE 0x00000800U /*!<Last error code interrupt enable */
+#define CAN_IER_ERRIE 0x00008000U /*!<Error interrupt enable */
+
+
+/******************** Bit definition for CAN_ESR register *******************/
+#define CAN_ESR_EWGF 0x00000001U /*!<Error Warning Flag */
+#define CAN_ESR_EPVF 0x00000002U /*!<Error Passive Flag */
+#define CAN_ESR_BOFF 0x00000004U /*!<Bus-Off Flag */
+
+#define CAN_ESR_LEC 0x00000070U /*!<LEC[2:0] bits (Last Error Code) */
+#define CAN_ESR_LEC_0 0x00000010U /*!<Bit 0 */
+#define CAN_ESR_LEC_1 0x00000020U /*!<Bit 1 */
+#define CAN_ESR_LEC_2 0x00000040U /*!<Bit 2 */
+
+#define CAN_ESR_TEC 0x00FF0000U /*!<Least significant byte of the 9-bit Transmit Error Counter */
+#define CAN_ESR_REC 0xFF000000U /*!<Receive Error Counter */
+
+/******************* Bit definition for CAN_BTR register ********************/
+#define CAN_BTR_BRP 0x000003FFU /*!<Baud Rate Prescaler */
+#define CAN_BTR_TS1 0x000F0000U /*!<Time Segment 1 */
+#define CAN_BTR_TS1_0 0x00010000U /*!<Bit 0 */
+#define CAN_BTR_TS1_1 0x00020000U /*!<Bit 1 */
+#define CAN_BTR_TS1_2 0x00040000U /*!<Bit 2 */
+#define CAN_BTR_TS1_3 0x00080000U /*!<Bit 3 */
+#define CAN_BTR_TS2 0x00700000U /*!<Time Segment 2 */
+#define CAN_BTR_TS2_0 0x00100000U /*!<Bit 0 */
+#define CAN_BTR_TS2_1 0x00200000U /*!<Bit 1 */
+#define CAN_BTR_TS2_2 0x00400000U /*!<Bit 2 */
+#define CAN_BTR_SJW 0x03000000U /*!<Resynchronization Jump Width */
+#define CAN_BTR_SJW_0 0x01000000U /*!<Bit 0 */
+#define CAN_BTR_SJW_1 0x02000000U /*!<Bit 1 */
+#define CAN_BTR_LBKM 0x40000000U /*!<Loop Back Mode (Debug) */
+#define CAN_BTR_SILM 0x80000000U /*!<Silent Mode */
+
+
+/*!<Mailbox registers */
+/****************** Bit definition for CAN_TI0R register ********************/
+#define CAN_TI0R_TXRQ 0x00000001U /*!<Transmit Mailbox Request */
+#define CAN_TI0R_RTR 0x00000002U /*!<Remote Transmission Request */
+#define CAN_TI0R_IDE 0x00000004U /*!<Identifier Extension */
+#define CAN_TI0R_EXID 0x001FFFF8U /*!<Extended Identifier */
+#define CAN_TI0R_STID 0xFFE00000U /*!<Standard Identifier or Extended Identifier */
+
+/****************** Bit definition for CAN_TDT0R register *******************/
+#define CAN_TDT0R_DLC 0x0000000FU /*!<Data Length Code */
+#define CAN_TDT0R_TGT 0x00000100U /*!<Transmit Global Time */
+#define CAN_TDT0R_TIME 0xFFFF0000U /*!<Message Time Stamp */
+
+/****************** Bit definition for CAN_TDL0R register *******************/
+#define CAN_TDL0R_DATA0 0x000000FFU /*!<Data byte 0 */
+#define CAN_TDL0R_DATA1 0x0000FF00U /*!<Data byte 1 */
+#define CAN_TDL0R_DATA2 0x00FF0000U /*!<Data byte 2 */
+#define CAN_TDL0R_DATA3 0xFF000000U /*!<Data byte 3 */
+
+/****************** Bit definition for CAN_TDH0R register *******************/
+#define CAN_TDH0R_DATA4 0x000000FFU /*!<Data byte 4 */
+#define CAN_TDH0R_DATA5 0x0000FF00U /*!<Data byte 5 */
+#define CAN_TDH0R_DATA6 0x00FF0000U /*!<Data byte 6 */
+#define CAN_TDH0R_DATA7 0xFF000000U /*!<Data byte 7 */
+
+/******************* Bit definition for CAN_TI1R register *******************/
+#define CAN_TI1R_TXRQ 0x00000001U /*!<Transmit Mailbox Request */
+#define CAN_TI1R_RTR 0x00000002U /*!<Remote Transmission Request */
+#define CAN_TI1R_IDE 0x00000004U /*!<Identifier Extension */
+#define CAN_TI1R_EXID 0x001FFFF8U /*!<Extended Identifier */
+#define CAN_TI1R_STID 0xFFE00000U /*!<Standard Identifier or Extended Identifier */
+
+/******************* Bit definition for CAN_TDT1R register ******************/
+#define CAN_TDT1R_DLC 0x0000000FU /*!<Data Length Code */
+#define CAN_TDT1R_TGT 0x00000100U /*!<Transmit Global Time */
+#define CAN_TDT1R_TIME 0xFFFF0000U /*!<Message Time Stamp */
+
+/******************* Bit definition for CAN_TDL1R register ******************/
+#define CAN_TDL1R_DATA0 0x000000FFU /*!<Data byte 0 */
+#define CAN_TDL1R_DATA1 0x0000FF00U /*!<Data byte 1 */
+#define CAN_TDL1R_DATA2 0x00FF0000U /*!<Data byte 2 */
+#define CAN_TDL1R_DATA3 0xFF000000U /*!<Data byte 3 */
+
+/******************* Bit definition for CAN_TDH1R register ******************/
+#define CAN_TDH1R_DATA4 0x000000FFU /*!<Data byte 4 */
+#define CAN_TDH1R_DATA5 0x0000FF00U /*!<Data byte 5 */
+#define CAN_TDH1R_DATA6 0x00FF0000U /*!<Data byte 6 */
+#define CAN_TDH1R_DATA7 0xFF000000U /*!<Data byte 7 */
+
+/******************* Bit definition for CAN_TI2R register *******************/
+#define CAN_TI2R_TXRQ 0x00000001U /*!<Transmit Mailbox Request */
+#define CAN_TI2R_RTR 0x00000002U /*!<Remote Transmission Request */
+#define CAN_TI2R_IDE 0x00000004U /*!<Identifier Extension */
+#define CAN_TI2R_EXID 0x001FFFF8U /*!<Extended identifier */
+#define CAN_TI2R_STID 0xFFE00000U /*!<Standard Identifier or Extended Identifier */
+
+/******************* Bit definition for CAN_TDT2R register ******************/
+#define CAN_TDT2R_DLC 0x0000000FU /*!<Data Length Code */
+#define CAN_TDT2R_TGT 0x00000100U /*!<Transmit Global Time */
+#define CAN_TDT2R_TIME 0xFFFF0000U /*!<Message Time Stamp */
+
+/******************* Bit definition for CAN_TDL2R register ******************/
+#define CAN_TDL2R_DATA0 0x000000FFU /*!<Data byte 0 */
+#define CAN_TDL2R_DATA1 0x0000FF00U /*!<Data byte 1 */
+#define CAN_TDL2R_DATA2 0x00FF0000U /*!<Data byte 2 */
+#define CAN_TDL2R_DATA3 0xFF000000U /*!<Data byte 3 */
+
+/******************* Bit definition for CAN_TDH2R register ******************/
+#define CAN_TDH2R_DATA4 0x000000FFU /*!<Data byte 4 */
+#define CAN_TDH2R_DATA5 0x0000FF00U /*!<Data byte 5 */
+#define CAN_TDH2R_DATA6 0x00FF0000U /*!<Data byte 6 */
+#define CAN_TDH2R_DATA7 0xFF000000U /*!<Data byte 7 */
+
+/******************* Bit definition for CAN_RI0R register *******************/
+#define CAN_RI0R_RTR 0x00000002U /*!<Remote Transmission Request */
+#define CAN_RI0R_IDE 0x00000004U /*!<Identifier Extension */
+#define CAN_RI0R_EXID 0x001FFFF8U /*!<Extended Identifier */
+#define CAN_RI0R_STID 0xFFE00000U /*!<Standard Identifier or Extended Identifier */
+
+/******************* Bit definition for CAN_RDT0R register ******************/
+#define CAN_RDT0R_DLC 0x0000000FU /*!<Data Length Code */
+#define CAN_RDT0R_FMI 0x0000FF00U /*!<Filter Match Index */
+#define CAN_RDT0R_TIME 0xFFFF0000U /*!<Message Time Stamp */
+
+/******************* Bit definition for CAN_RDL0R register ******************/
+#define CAN_RDL0R_DATA0 0x000000FFU /*!<Data byte 0 */
+#define CAN_RDL0R_DATA1 0x0000FF00U /*!<Data byte 1 */
+#define CAN_RDL0R_DATA2 0x00FF0000U /*!<Data byte 2 */
+#define CAN_RDL0R_DATA3 0xFF000000U /*!<Data byte 3 */
+
+/******************* Bit definition for CAN_RDH0R register ******************/
+#define CAN_RDH0R_DATA4 0x000000FFU /*!<Data byte 4 */
+#define CAN_RDH0R_DATA5 0x0000FF00U /*!<Data byte 5 */
+#define CAN_RDH0R_DATA6 0x00FF0000U /*!<Data byte 6 */
+#define CAN_RDH0R_DATA7 0xFF000000U /*!<Data byte 7 */
+
+/******************* Bit definition for CAN_RI1R register *******************/
+#define CAN_RI1R_RTR 0x00000002U /*!<Remote Transmission Request */
+#define CAN_RI1R_IDE 0x00000004U /*!<Identifier Extension */
+#define CAN_RI1R_EXID 0x001FFFF8U /*!<Extended identifier */
+#define CAN_RI1R_STID 0xFFE00000U /*!<Standard Identifier or Extended Identifier */
+
+/******************* Bit definition for CAN_RDT1R register ******************/
+#define CAN_RDT1R_DLC 0x0000000FU /*!<Data Length Code */
+#define CAN_RDT1R_FMI 0x0000FF00U /*!<Filter Match Index */
+#define CAN_RDT1R_TIME 0xFFFF0000U /*!<Message Time Stamp */
+
+/******************* Bit definition for CAN_RDL1R register ******************/
+#define CAN_RDL1R_DATA0 0x000000FFU /*!<Data byte 0 */
+#define CAN_RDL1R_DATA1 0x0000FF00U /*!<Data byte 1 */
+#define CAN_RDL1R_DATA2 0x00FF0000U /*!<Data byte 2 */
+#define CAN_RDL1R_DATA3 0xFF000000U /*!<Data byte 3 */
+
+/******************* Bit definition for CAN_RDH1R register ******************/
+#define CAN_RDH1R_DATA4 0x000000FFU /*!<Data byte 4 */
+#define CAN_RDH1R_DATA5 0x0000FF00U /*!<Data byte 5 */
+#define CAN_RDH1R_DATA6 0x00FF0000U /*!<Data byte 6 */
+#define CAN_RDH1R_DATA7 0xFF000000U /*!<Data byte 7 */
+
+/*!<CAN filter registers */
+/******************* Bit definition for CAN_FMR register ********************/
+#define CAN_FMR_FINIT 0x01U /*!<Filter Init Mode */
+#define CAN_FMR_CAN2SB 0x00003F00U /*!<CAN2 start bank */
+
+/******************* Bit definition for CAN_FM1R register *******************/
+#define CAN_FM1R_FBM 0x0FFFFFFFU /*!<Filter Mode */
+#define CAN_FM1R_FBM0 0x00000001U /*!<Filter Init Mode bit 0 */
+#define CAN_FM1R_FBM1 0x00000002U /*!<Filter Init Mode bit 1 */
+#define CAN_FM1R_FBM2 0x00000004U /*!<Filter Init Mode bit 2 */
+#define CAN_FM1R_FBM3 0x00000008U /*!<Filter Init Mode bit 3 */
+#define CAN_FM1R_FBM4 0x00000010U /*!<Filter Init Mode bit 4 */
+#define CAN_FM1R_FBM5 0x00000020U /*!<Filter Init Mode bit 5 */
+#define CAN_FM1R_FBM6 0x00000040U /*!<Filter Init Mode bit 6 */
+#define CAN_FM1R_FBM7 0x00000080U /*!<Filter Init Mode bit 7 */
+#define CAN_FM1R_FBM8 0x00000100U /*!<Filter Init Mode bit 8 */
+#define CAN_FM1R_FBM9 0x00000200U /*!<Filter Init Mode bit 9 */
+#define CAN_FM1R_FBM10 0x00000400U /*!<Filter Init Mode bit 10 */
+#define CAN_FM1R_FBM11 0x00000800U /*!<Filter Init Mode bit 11 */
+#define CAN_FM1R_FBM12 0x00001000U /*!<Filter Init Mode bit 12 */
+#define CAN_FM1R_FBM13 0x00002000U /*!<Filter Init Mode bit 13 */
+#define CAN_FM1R_FBM14 0x00004000U /*!<Filter Init Mode bit 14 */
+#define CAN_FM1R_FBM15 0x00008000U /*!<Filter Init Mode bit 15 */
+#define CAN_FM1R_FBM16 0x00010000U /*!<Filter Init Mode bit 16 */
+#define CAN_FM1R_FBM17 0x00020000U /*!<Filter Init Mode bit 17 */
+#define CAN_FM1R_FBM18 0x00040000U /*!<Filter Init Mode bit 18 */
+#define CAN_FM1R_FBM19 0x00080000U /*!<Filter Init Mode bit 19 */
+#define CAN_FM1R_FBM20 0x00100000U /*!<Filter Init Mode bit 20 */
+#define CAN_FM1R_FBM21 0x00200000U /*!<Filter Init Mode bit 21 */
+#define CAN_FM1R_FBM22 0x00400000U /*!<Filter Init Mode bit 22 */
+#define CAN_FM1R_FBM23 0x00800000U /*!<Filter Init Mode bit 23 */
+#define CAN_FM1R_FBM24 0x01000000U /*!<Filter Init Mode bit 24 */
+#define CAN_FM1R_FBM25 0x02000000U /*!<Filter Init Mode bit 25 */
+#define CAN_FM1R_FBM26 0x04000000U /*!<Filter Init Mode bit 26 */
+#define CAN_FM1R_FBM27 0x08000000U /*!<Filter Init Mode bit 27 */
+
+/******************* Bit definition for CAN_FS1R register *******************/
+#define CAN_FS1R_FSC 0x0FFFFFFFU /*!<Filter Scale Configuration */
+#define CAN_FS1R_FSC0 0x00000001U /*!<Filter Scale Configuration bit 0 */
+#define CAN_FS1R_FSC1 0x00000002U /*!<Filter Scale Configuration bit 1 */
+#define CAN_FS1R_FSC2 0x00000004U /*!<Filter Scale Configuration bit 2 */
+#define CAN_FS1R_FSC3 0x00000008U /*!<Filter Scale Configuration bit 3 */
+#define CAN_FS1R_FSC4 0x00000010U /*!<Filter Scale Configuration bit 4 */
+#define CAN_FS1R_FSC5 0x00000020U /*!<Filter Scale Configuration bit 5 */
+#define CAN_FS1R_FSC6 0x00000040U /*!<Filter Scale Configuration bit 6 */
+#define CAN_FS1R_FSC7 0x00000080U /*!<Filter Scale Configuration bit 7 */
+#define CAN_FS1R_FSC8 0x00000100U /*!<Filter Scale Configuration bit 8 */
+#define CAN_FS1R_FSC9 0x00000200U /*!<Filter Scale Configuration bit 9 */
+#define CAN_FS1R_FSC10 0x00000400U /*!<Filter Scale Configuration bit 10 */
+#define CAN_FS1R_FSC11 0x00000800U /*!<Filter Scale Configuration bit 11 */
+#define CAN_FS1R_FSC12 0x00001000U /*!<Filter Scale Configuration bit 12 */
+#define CAN_FS1R_FSC13 0x00002000U /*!<Filter Scale Configuration bit 13 */
+#define CAN_FS1R_FSC14 0x00004000U /*!<Filter Scale Configuration bit 14 */
+#define CAN_FS1R_FSC15 0x00008000U /*!<Filter Scale Configuration bit 15 */
+#define CAN_FS1R_FSC16 0x00010000U /*!<Filter Scale Configuration bit 16 */
+#define CAN_FS1R_FSC17 0x00020000U /*!<Filter Scale Configuration bit 17 */
+#define CAN_FS1R_FSC18 0x00040000U /*!<Filter Scale Configuration bit 18 */
+#define CAN_FS1R_FSC19 0x00080000U /*!<Filter Scale Configuration bit 19 */
+#define CAN_FS1R_FSC20 0x00100000U /*!<Filter Scale Configuration bit 20 */
+#define CAN_FS1R_FSC21 0x00200000U /*!<Filter Scale Configuration bit 21 */
+#define CAN_FS1R_FSC22 0x00400000U /*!<Filter Scale Configuration bit 22 */
+#define CAN_FS1R_FSC23 0x00800000U /*!<Filter Scale Configuration bit 23 */
+#define CAN_FS1R_FSC24 0x01000000U /*!<Filter Scale Configuration bit 24 */
+#define CAN_FS1R_FSC25 0x02000000U /*!<Filter Scale Configuration bit 25 */
+#define CAN_FS1R_FSC26 0x04000000U /*!<Filter Scale Configuration bit 26 */
+#define CAN_FS1R_FSC27 0x08000000U /*!<Filter Scale Configuration bit 27 */
+
+/****************** Bit definition for CAN_FFA1R register *******************/
+#define CAN_FFA1R_FFA 0x0FFFFFFFU /*!<Filter FIFO Assignment */
+#define CAN_FFA1R_FFA0 0x00000001U /*!<Filter FIFO Assignment bit 0 */
+#define CAN_FFA1R_FFA1 0x00000002U /*!<Filter FIFO Assignment bit 1 */
+#define CAN_FFA1R_FFA2 0x00000004U /*!<Filter FIFO Assignment bit 2 */
+#define CAN_FFA1R_FFA3 0x00000008U /*!<Filter FIFO Assignment bit 3 */
+#define CAN_FFA1R_FFA4 0x00000010U /*!<Filter FIFO Assignment bit 4 */
+#define CAN_FFA1R_FFA5 0x00000020U /*!<Filter FIFO Assignment bit 5 */
+#define CAN_FFA1R_FFA6 0x00000040U /*!<Filter FIFO Assignment bit 6 */
+#define CAN_FFA1R_FFA7 0x00000080U /*!<Filter FIFO Assignment bit 7 */
+#define CAN_FFA1R_FFA8 0x00000100U /*!<Filter FIFO Assignment bit 8 */
+#define CAN_FFA1R_FFA9 0x00000200U /*!<Filter FIFO Assignment bit 9 */
+#define CAN_FFA1R_FFA10 0x00000400U /*!<Filter FIFO Assignment bit 10 */
+#define CAN_FFA1R_FFA11 0x00000800U /*!<Filter FIFO Assignment bit 11 */
+#define CAN_FFA1R_FFA12 0x00001000U /*!<Filter FIFO Assignment bit 12 */
+#define CAN_FFA1R_FFA13 0x00002000U /*!<Filter FIFO Assignment bit 13 */
+#define CAN_FFA1R_FFA14 0x00004000U /*!<Filter FIFO Assignment bit 14 */
+#define CAN_FFA1R_FFA15 0x00008000U /*!<Filter FIFO Assignment bit 15 */
+#define CAN_FFA1R_FFA16 0x00010000U /*!<Filter FIFO Assignment bit 16 */
+#define CAN_FFA1R_FFA17 0x00020000U /*!<Filter FIFO Assignment bit 17 */
+#define CAN_FFA1R_FFA18 0x00040000U /*!<Filter FIFO Assignment bit 18 */
+#define CAN_FFA1R_FFA19 0x00080000U /*!<Filter FIFO Assignment bit 19 */
+#define CAN_FFA1R_FFA20 0x00100000U /*!<Filter FIFO Assignment bit 20 */
+#define CAN_FFA1R_FFA21 0x00200000U /*!<Filter FIFO Assignment bit 21 */
+#define CAN_FFA1R_FFA22 0x00400000U /*!<Filter FIFO Assignment bit 22 */
+#define CAN_FFA1R_FFA23 0x00800000U /*!<Filter FIFO Assignment bit 23 */
+#define CAN_FFA1R_FFA24 0x01000000U /*!<Filter FIFO Assignment bit 24 */
+#define CAN_FFA1R_FFA25 0x02000000U /*!<Filter FIFO Assignment bit 25 */
+#define CAN_FFA1R_FFA26 0x04000000U /*!<Filter FIFO Assignment bit 26 */
+#define CAN_FFA1R_FFA27 0x08000000U /*!<Filter FIFO Assignment bit 27 */
+
+/******************* Bit definition for CAN_FA1R register *******************/
+#define CAN_FA1R_FACT 0x0FFFFFFFU /*!<Filter Active */
+#define CAN_FA1R_FACT0 0x00000001U /*!<Filter Active bit 0 */
+#define CAN_FA1R_FACT1 0x00000002U /*!<Filter Active bit 1 */
+#define CAN_FA1R_FACT2 0x00000004U /*!<Filter Active bit 2 */
+#define CAN_FA1R_FACT3 0x00000008U /*!<Filter Active bit 3 */
+#define CAN_FA1R_FACT4 0x00000010U /*!<Filter Active bit 4 */
+#define CAN_FA1R_FACT5 0x00000020U /*!<Filter Active bit 5 */
+#define CAN_FA1R_FACT6 0x00000040U /*!<Filter Active bit 6 */
+#define CAN_FA1R_FACT7 0x00000080U /*!<Filter Active bit 7 */
+#define CAN_FA1R_FACT8 0x00000100U /*!<Filter Active bit 8 */
+#define CAN_FA1R_FACT9 0x00000200U /*!<Filter Active bit 9 */
+#define CAN_FA1R_FACT10 0x00000400U /*!<Filter Active bit 10 */
+#define CAN_FA1R_FACT11 0x00000800U /*!<Filter Active bit 11 */
+#define CAN_FA1R_FACT12 0x00001000U /*!<Filter Active bit 12 */
+#define CAN_FA1R_FACT13 0x00002000U /*!<Filter Active bit 13 */
+#define CAN_FA1R_FACT14 0x00004000U /*!<Filter Active bit 14 */
+#define CAN_FA1R_FACT15 0x00008000U /*!<Filter Active bit 15 */
+#define CAN_FA1R_FACT16 0x00010000U /*!<Filter Active bit 16 */
+#define CAN_FA1R_FACT17 0x00020000U /*!<Filter Active bit 17 */
+#define CAN_FA1R_FACT18 0x00040000U /*!<Filter Active bit 18 */
+#define CAN_FA1R_FACT19 0x00080000U /*!<Filter Active bit 19 */
+#define CAN_FA1R_FACT20 0x00100000U /*!<Filter Active bit 20 */
+#define CAN_FA1R_FACT21 0x00200000U /*!<Filter Active bit 21 */
+#define CAN_FA1R_FACT22 0x00400000U /*!<Filter Active bit 22 */
+#define CAN_FA1R_FACT23 0x00800000U /*!<Filter Active bit 23 */
+#define CAN_FA1R_FACT24 0x01000000U /*!<Filter Active bit 24 */
+#define CAN_FA1R_FACT25 0x02000000U /*!<Filter Active bit 25 */
+#define CAN_FA1R_FACT26 0x04000000U /*!<Filter Active bit 26 */
+#define CAN_FA1R_FACT27 0x08000000U /*!<Filter Active bit 27 */
+
+/******************* Bit definition for CAN_F0R1 register *******************/
+#define CAN_F0R1_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F0R1_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F0R1_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F0R1_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F0R1_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F0R1_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F0R1_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F0R1_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F0R1_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F0R1_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F0R1_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F0R1_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F0R1_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F0R1_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F0R1_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F0R1_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F0R1_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F0R1_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F0R1_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F0R1_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F0R1_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F0R1_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F0R1_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F0R1_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F0R1_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F0R1_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F0R1_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F0R1_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F0R1_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F0R1_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F0R1_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F0R1_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F1R1 register *******************/
+#define CAN_F1R1_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F1R1_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F1R1_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F1R1_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F1R1_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F1R1_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F1R1_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F1R1_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F1R1_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F1R1_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F1R1_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F1R1_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F1R1_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F1R1_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F1R1_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F1R1_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F1R1_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F1R1_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F1R1_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F1R1_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F1R1_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F1R1_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F1R1_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F1R1_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F1R1_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F1R1_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F1R1_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F1R1_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F1R1_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F1R1_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F1R1_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F1R1_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F2R1 register *******************/
+#define CAN_F2R1_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F2R1_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F2R1_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F2R1_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F2R1_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F2R1_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F2R1_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F2R1_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F2R1_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F2R1_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F2R1_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F2R1_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F2R1_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F2R1_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F2R1_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F2R1_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F2R1_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F2R1_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F2R1_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F2R1_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F2R1_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F2R1_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F2R1_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F2R1_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F2R1_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F2R1_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F2R1_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F2R1_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F2R1_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F2R1_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F2R1_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F2R1_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F3R1 register *******************/
+#define CAN_F3R1_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F3R1_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F3R1_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F3R1_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F3R1_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F3R1_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F3R1_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F3R1_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F3R1_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F3R1_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F3R1_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F3R1_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F3R1_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F3R1_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F3R1_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F3R1_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F3R1_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F3R1_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F3R1_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F3R1_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F3R1_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F3R1_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F3R1_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F3R1_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F3R1_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F3R1_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F3R1_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F3R1_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F3R1_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F3R1_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F3R1_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F3R1_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F4R1 register *******************/
+#define CAN_F4R1_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F4R1_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F4R1_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F4R1_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F4R1_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F4R1_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F4R1_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F4R1_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F4R1_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F4R1_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F4R1_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F4R1_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F4R1_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F4R1_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F4R1_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F4R1_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F4R1_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F4R1_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F4R1_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F4R1_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F4R1_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F4R1_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F4R1_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F4R1_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F4R1_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F4R1_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F4R1_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F4R1_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F4R1_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F4R1_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F4R1_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F4R1_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F5R1 register *******************/
+#define CAN_F5R1_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F5R1_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F5R1_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F5R1_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F5R1_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F5R1_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F5R1_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F5R1_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F5R1_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F5R1_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F5R1_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F5R1_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F5R1_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F5R1_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F5R1_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F5R1_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F5R1_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F5R1_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F5R1_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F5R1_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F5R1_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F5R1_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F5R1_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F5R1_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F5R1_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F5R1_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F5R1_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F5R1_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F5R1_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F5R1_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F5R1_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F5R1_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F6R1 register *******************/
+#define CAN_F6R1_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F6R1_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F6R1_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F6R1_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F6R1_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F6R1_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F6R1_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F6R1_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F6R1_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F6R1_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F6R1_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F6R1_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F6R1_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F6R1_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F6R1_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F6R1_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F6R1_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F6R1_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F6R1_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F6R1_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F6R1_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F6R1_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F6R1_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F6R1_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F6R1_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F6R1_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F6R1_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F6R1_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F6R1_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F6R1_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F6R1_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F6R1_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F7R1 register *******************/
+#define CAN_F7R1_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F7R1_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F7R1_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F7R1_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F7R1_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F7R1_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F7R1_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F7R1_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F7R1_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F7R1_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F7R1_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F7R1_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F7R1_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F7R1_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F7R1_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F7R1_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F7R1_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F7R1_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F7R1_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F7R1_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F7R1_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F7R1_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F7R1_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F7R1_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F7R1_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F7R1_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F7R1_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F7R1_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F7R1_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F7R1_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F7R1_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F7R1_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F8R1 register *******************/
+#define CAN_F8R1_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F8R1_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F8R1_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F8R1_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F8R1_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F8R1_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F8R1_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F8R1_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F8R1_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F8R1_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F8R1_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F8R1_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F8R1_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F8R1_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F8R1_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F8R1_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F8R1_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F8R1_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F8R1_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F8R1_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F8R1_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F8R1_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F8R1_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F8R1_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F8R1_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F8R1_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F8R1_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F8R1_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F8R1_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F8R1_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F8R1_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F8R1_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F9R1 register *******************/
+#define CAN_F9R1_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F9R1_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F9R1_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F9R1_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F9R1_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F9R1_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F9R1_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F9R1_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F9R1_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F9R1_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F9R1_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F9R1_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F9R1_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F9R1_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F9R1_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F9R1_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F9R1_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F9R1_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F9R1_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F9R1_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F9R1_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F9R1_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F9R1_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F9R1_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F9R1_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F9R1_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F9R1_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F9R1_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F9R1_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F9R1_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F9R1_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F9R1_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F10R1 register ******************/
+#define CAN_F10R1_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F10R1_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F10R1_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F10R1_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F10R1_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F10R1_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F10R1_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F10R1_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F10R1_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F10R1_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F10R1_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F10R1_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F10R1_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F10R1_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F10R1_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F10R1_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F10R1_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F10R1_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F10R1_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F10R1_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F10R1_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F10R1_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F10R1_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F10R1_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F10R1_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F10R1_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F10R1_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F10R1_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F10R1_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F10R1_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F10R1_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F10R1_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F11R1 register ******************/
+#define CAN_F11R1_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F11R1_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F11R1_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F11R1_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F11R1_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F11R1_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F11R1_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F11R1_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F11R1_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F11R1_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F11R1_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F11R1_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F11R1_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F11R1_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F11R1_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F11R1_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F11R1_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F11R1_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F11R1_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F11R1_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F11R1_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F11R1_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F11R1_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F11R1_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F11R1_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F11R1_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F11R1_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F11R1_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F11R1_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F11R1_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F11R1_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F11R1_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F12R1 register ******************/
+#define CAN_F12R1_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F12R1_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F12R1_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F12R1_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F12R1_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F12R1_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F12R1_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F12R1_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F12R1_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F12R1_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F12R1_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F12R1_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F12R1_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F12R1_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F12R1_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F12R1_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F12R1_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F12R1_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F12R1_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F12R1_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F12R1_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F12R1_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F12R1_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F12R1_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F12R1_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F12R1_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F12R1_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F12R1_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F12R1_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F12R1_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F12R1_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F12R1_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F13R1 register ******************/
+#define CAN_F13R1_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F13R1_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F13R1_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F13R1_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F13R1_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F13R1_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F13R1_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F13R1_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F13R1_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F13R1_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F13R1_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F13R1_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F13R1_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F13R1_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F13R1_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F13R1_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F13R1_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F13R1_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F13R1_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F13R1_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F13R1_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F13R1_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F13R1_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F13R1_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F13R1_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F13R1_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F13R1_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F13R1_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F13R1_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F13R1_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F13R1_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F13R1_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F0R2 register *******************/
+#define CAN_F0R2_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F0R2_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F0R2_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F0R2_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F0R2_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F0R2_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F0R2_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F0R2_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F0R2_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F0R2_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F0R2_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F0R2_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F0R2_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F0R2_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F0R2_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F0R2_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F0R2_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F0R2_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F0R2_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F0R2_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F0R2_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F0R2_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F0R2_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F0R2_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F0R2_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F0R2_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F0R2_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F0R2_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F0R2_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F0R2_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F0R2_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F0R2_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F1R2 register *******************/
+#define CAN_F1R2_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F1R2_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F1R2_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F1R2_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F1R2_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F1R2_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F1R2_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F1R2_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F1R2_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F1R2_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F1R2_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F1R2_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F1R2_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F1R2_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F1R2_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F1R2_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F1R2_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F1R2_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F1R2_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F1R2_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F1R2_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F1R2_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F1R2_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F1R2_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F1R2_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F1R2_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F1R2_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F1R2_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F1R2_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F1R2_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F1R2_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F1R2_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F2R2 register *******************/
+#define CAN_F2R2_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F2R2_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F2R2_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F2R2_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F2R2_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F2R2_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F2R2_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F2R2_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F2R2_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F2R2_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F2R2_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F2R2_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F2R2_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F2R2_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F2R2_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F2R2_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F2R2_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F2R2_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F2R2_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F2R2_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F2R2_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F2R2_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F2R2_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F2R2_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F2R2_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F2R2_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F2R2_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F2R2_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F2R2_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F2R2_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F2R2_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F2R2_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F3R2 register *******************/
+#define CAN_F3R2_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F3R2_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F3R2_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F3R2_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F3R2_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F3R2_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F3R2_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F3R2_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F3R2_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F3R2_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F3R2_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F3R2_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F3R2_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F3R2_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F3R2_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F3R2_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F3R2_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F3R2_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F3R2_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F3R2_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F3R2_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F3R2_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F3R2_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F3R2_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F3R2_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F3R2_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F3R2_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F3R2_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F3R2_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F3R2_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F3R2_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F3R2_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F4R2 register *******************/
+#define CAN_F4R2_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F4R2_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F4R2_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F4R2_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F4R2_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F4R2_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F4R2_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F4R2_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F4R2_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F4R2_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F4R2_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F4R2_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F4R2_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F4R2_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F4R2_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F4R2_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F4R2_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F4R2_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F4R2_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F4R2_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F4R2_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F4R2_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F4R2_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F4R2_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F4R2_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F4R2_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F4R2_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F4R2_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F4R2_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F4R2_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F4R2_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F4R2_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F5R2 register *******************/
+#define CAN_F5R2_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F5R2_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F5R2_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F5R2_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F5R2_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F5R2_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F5R2_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F5R2_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F5R2_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F5R2_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F5R2_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F5R2_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F5R2_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F5R2_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F5R2_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F5R2_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F5R2_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F5R2_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F5R2_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F5R2_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F5R2_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F5R2_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F5R2_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F5R2_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F5R2_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F5R2_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F5R2_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F5R2_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F5R2_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F5R2_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F5R2_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F5R2_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F6R2 register *******************/
+#define CAN_F6R2_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F6R2_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F6R2_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F6R2_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F6R2_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F6R2_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F6R2_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F6R2_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F6R2_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F6R2_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F6R2_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F6R2_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F6R2_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F6R2_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F6R2_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F6R2_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F6R2_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F6R2_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F6R2_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F6R2_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F6R2_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F6R2_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F6R2_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F6R2_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F6R2_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F6R2_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F6R2_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F6R2_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F6R2_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F6R2_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F6R2_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F6R2_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F7R2 register *******************/
+#define CAN_F7R2_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F7R2_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F7R2_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F7R2_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F7R2_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F7R2_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F7R2_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F7R2_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F7R2_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F7R2_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F7R2_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F7R2_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F7R2_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F7R2_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F7R2_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F7R2_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F7R2_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F7R2_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F7R2_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F7R2_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F7R2_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F7R2_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F7R2_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F7R2_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F7R2_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F7R2_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F7R2_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F7R2_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F7R2_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F7R2_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F7R2_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F7R2_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F8R2 register *******************/
+#define CAN_F8R2_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F8R2_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F8R2_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F8R2_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F8R2_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F8R2_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F8R2_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F8R2_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F8R2_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F8R2_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F8R2_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F8R2_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F8R2_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F8R2_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F8R2_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F8R2_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F8R2_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F8R2_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F8R2_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F8R2_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F8R2_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F8R2_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F8R2_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F8R2_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F8R2_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F8R2_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F8R2_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F8R2_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F8R2_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F8R2_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F8R2_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F8R2_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F9R2 register *******************/
+#define CAN_F9R2_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F9R2_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F9R2_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F9R2_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F9R2_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F9R2_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F9R2_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F9R2_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F9R2_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F9R2_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F9R2_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F9R2_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F9R2_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F9R2_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F9R2_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F9R2_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F9R2_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F9R2_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F9R2_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F9R2_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F9R2_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F9R2_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F9R2_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F9R2_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F9R2_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F9R2_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F9R2_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F9R2_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F9R2_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F9R2_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F9R2_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F9R2_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F10R2 register ******************/
+#define CAN_F10R2_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F10R2_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F10R2_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F10R2_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F10R2_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F10R2_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F10R2_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F10R2_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F10R2_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F10R2_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F10R2_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F10R2_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F10R2_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F10R2_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F10R2_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F10R2_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F10R2_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F10R2_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F10R2_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F10R2_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F10R2_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F10R2_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F10R2_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F10R2_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F10R2_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F10R2_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F10R2_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F10R2_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F10R2_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F10R2_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F10R2_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F10R2_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F11R2 register ******************/
+#define CAN_F11R2_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F11R2_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F11R2_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F11R2_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F11R2_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F11R2_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F11R2_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F11R2_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F11R2_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F11R2_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F11R2_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F11R2_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F11R2_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F11R2_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F11R2_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F11R2_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F11R2_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F11R2_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F11R2_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F11R2_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F11R2_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F11R2_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F11R2_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F11R2_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F11R2_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F11R2_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F11R2_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F11R2_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F11R2_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F11R2_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F11R2_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F11R2_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F12R2 register ******************/
+#define CAN_F12R2_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F12R2_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F12R2_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F12R2_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F12R2_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F12R2_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F12R2_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F12R2_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F12R2_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F12R2_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F12R2_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F12R2_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F12R2_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F12R2_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F12R2_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F12R2_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F12R2_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F12R2_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F12R2_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F12R2_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F12R2_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F12R2_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F12R2_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F12R2_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F12R2_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F12R2_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F12R2_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F12R2_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F12R2_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F12R2_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F12R2_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F12R2_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F13R2 register ******************/
+#define CAN_F13R2_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F13R2_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F13R2_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F13R2_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F13R2_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F13R2_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F13R2_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F13R2_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F13R2_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F13R2_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F13R2_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F13R2_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F13R2_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F13R2_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F13R2_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F13R2_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F13R2_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F13R2_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F13R2_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F13R2_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F13R2_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F13R2_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F13R2_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F13R2_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F13R2_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F13R2_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F13R2_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F13R2_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F13R2_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F13R2_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F13R2_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F13R2_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************************************************************************/
+/* */
+/* CRC calculation unit */
+/* */
+/******************************************************************************/
+/******************* Bit definition for CRC_DR register *********************/
+#define CRC_DR_DR 0xFFFFFFFFU /*!< Data register bits */
+
+
+/******************* Bit definition for CRC_IDR register ********************/
+#define CRC_IDR_IDR 0xFFU /*!< General-purpose 8-bit data register bits */
+
+
+/******************** Bit definition for CRC_CR register ********************/
+#define CRC_CR_RESET 0x01U /*!< RESET bit */
+
+/******************************************************************************/
+/* */
+/* Debug MCU */
+/* */
+/******************************************************************************/
+
+/******************************************************************************/
+/* */
+/* Digital Filter for Sigma Delta Modulators */
+/* */
+/******************************************************************************/
+
+/**************** DFSDM channel configuration registers ********************/
+
+/*************** Bit definition for DFSDM_CHCFGR1 register ******************/
+#define DFSDM_CHCFGR1_DFSDMEN 0x80000000U /*!< Global enable for DFSDM interface */
+#define DFSDM_CHCFGR1_CKOUTSRC 0x40000000U /*!< Output serial clock source selection */
+#define DFSDM_CHCFGR1_CKOUTDIV 0x00FF0000U /*!< CKOUTDIV[7:0] output serial clock divider */
+#define DFSDM_CHCFGR1_DATPACK 0x0000C000U /*!< DATPACK[1:0] Data packing mode */
+#define DFSDM_CHCFGR1_DATPACK_1 0x00008000U /*!< Data packing mode, Bit 1 */
+#define DFSDM_CHCFGR1_DATPACK_0 0x00004000U /*!< Data packing mode, Bit 0 */
+#define DFSDM_CHCFGR1_DATMPX 0x00003000U /*!< DATMPX[1:0] Input data multiplexer for channel y */
+#define DFSDM_CHCFGR1_DATMPX_1 0x00002000U /*!< Input data multiplexer for channel y, Bit 1 */
+#define DFSDM_CHCFGR1_DATMPX_0 0x00001000U /*!< Input data multiplexer for channel y, Bit 0 */
+#define DFSDM_CHCFGR1_CHINSEL 0x00000100U /*!< Serial inputs selection for channel y */
+#define DFSDM_CHCFGR1_CHEN 0x00000080U /*!< Channel y enable */
+#define DFSDM_CHCFGR1_CKABEN 0x00000040U /*!< Clock absence detector enable on channel y */
+#define DFSDM_CHCFGR1_SCDEN 0x00000020U /*!< Short circuit detector enable on channel y */
+#define DFSDM_CHCFGR1_SPICKSEL 0x0000000CU /*!< SPICKSEL[1:0] SPI clock select for channel y */
+#define DFSDM_CHCFGR1_SPICKSEL_1 0x00000008U /*!< SPI clock select for channel y, Bit 1 */
+#define DFSDM_CHCFGR1_SPICKSEL_0 0x00000004U /*!< SPI clock select for channel y, Bit 0 */
+#define DFSDM_CHCFGR1_SITP 0x00000003U /*!< SITP[1:0] Serial interface type for channel y */
+#define DFSDM_CHCFGR1_SITP_1 0x00000002U /*!< Serial interface type for channel y, Bit 1 */
+#define DFSDM_CHCFGR1_SITP_0 0x00000001U /*!< Serial interface type for channel y, Bit 0 */
+
+/*************** Bit definition for DFSDM_CHCFGR2 register ******************/
+#define DFSDM_CHCFGR2_OFFSET 0xFFFFFF00U /*!< OFFSET[23:0] 24-bit calibration offset for channel y */
+#define DFSDM_CHCFGR2_DTRBS 0x000000F8U /*!< DTRBS[4:0] Data right bit-shift for channel y */
+
+/**************** Bit definition for DFSDM_CHAWSCDR register *****************/
+#define DFSDM_CHAWSCDR_AWFORD 0x00C00000U /*!< AWFORD[1:0] Analog watchdog Sinc filter order on channel y */
+#define DFSDM_CHAWSCDR_AWFORD_1 0x00800000U /*!< Analog watchdog Sinc filter order on channel y, Bit 1 */
+#define DFSDM_CHAWSCDR_AWFORD_0 0x00400000U /*!< Analog watchdog Sinc filter order on channel y, Bit 0 */
+#define DFSDM_CHAWSCDR_AWFOSR 0x001F0000U /*!< AWFOSR[4:0] Analog watchdog filter oversampling ratio on channel y */
+#define DFSDM_CHAWSCDR_BKSCD 0x0000F000U /*!< BKSCD[3:0] Break signal assignment for short circuit detector on channel y */
+#define DFSDM_CHAWSCDR_SCDT 0x000000FFU /*!< SCDT[7:0] Short circuit detector threshold for channel y */
+
+/**************** Bit definition for DFSDM_CHWDATR register *******************/
+#define DFSDM_CHWDATR_WDATA 0x0000FFFFU /*!< WDATA[15:0] Input channel y watchdog data */
+
+/**************** Bit definition for DFSDM_CHDATINR register *****************/
+#define DFSDM_CHDATINR_INDAT0 0x0000FFFFU /*!< INDAT0[31:16] Input data for channel y or channel (y+1) */
+#define DFSDM_CHDATINR_INDAT1 0xFFFF0000U /*!< INDAT0[15:0] Input data for channel y */
+
+/************************ DFSDM module registers ****************************/
+
+/***************** Bit definition for DFSDM_FLTCR1 register *******************/
+#define DFSDM_FLTCR1_AWFSEL 0x40000000U /*!< Analog watchdog fast mode select */
+#define DFSDM_FLTCR1_FAST 0x20000000U /*!< Fast conversion mode selection */
+#define DFSDM_FLTCR1_RCH 0x07000000U /*!< RCH[2:0] Regular channel selection */
+#define DFSDM_FLTCR1_RDMAEN 0x00200000U /*!< DMA channel enabled to read data for the regular conversion */
+#define DFSDM_FLTCR1_RSYNC 0x00080000U /*!< Launch regular conversion synchronously with DFSDMx */
+#define DFSDM_FLTCR1_RCONT 0x00040000U /*!< Continuous mode selection for regular conversions */
+#define DFSDM_FLTCR1_RSWSTART 0x00020000U /*!< Software start of a conversion on the regular channel */
+#define DFSDM_FLTCR1_JEXTEN 0x00006000U /*!< JEXTEN[1:0] Trigger enable and trigger edge selection for injected conversions */
+#define DFSDM_FLTCR1_JEXTEN_1 0x00004000U /*!< Trigger enable and trigger edge selection for injected conversions, Bit 1 */
+#define DFSDM_FLTCR1_JEXTEN_0 0x00002000U /*!< Trigger enable and trigger edge selection for injected conversions, Bit 0 */
+#define DFSDM_FLTCR1_JEXTSEL 0x00000700U /*!< JEXTSEL[2:0]Trigger signal selection for launching injected conversions */
+#define DFSDM_FLTCR1_JEXTSEL_2 0x00000400U /*!< Trigger signal selection for launching injected conversions, Bit 2 */
+#define DFSDM_FLTCR1_JEXTSEL_1 0x00000200U /*!< Trigger signal selection for launching injected conversions, Bit 1 */
+#define DFSDM_FLTCR1_JEXTSEL_0 0x00000100U /*!< Trigger signal selection for launching injected conversions, Bit 0 */
+#define DFSDM_FLTCR1_JDMAEN 0x00000020U /*!< DMA channel enabled to read data for the injected channel group */
+#define DFSDM_FLTCR1_JSCAN 0x00000010U /*!< Scanning conversion in continuous mode selection for injected conversions */
+#define DFSDM_FLTCR1_JSYNC 0x00000008U /*!< Launch an injected conversion synchronously with DFSDMx JSWSTART trigger */
+#define DFSDM_FLTCR1_JSWSTART 0x00000002U /*!< Start the conversion of the injected group of channels */
+#define DFSDM_FLTCR1_DFEN 0x00000001U /*!< DFSDM enable */
+
+/***************** Bit definition for DFSDM_FLTCR2 register *******************/
+#define DFSDM_FLTCR2_AWDCH 0x000F0000U /*!< AWDCH[7:0] Analog watchdog channel selection */
+#define DFSDM_FLTCR2_EXCH 0x00000F00U /*!< EXCH[7:0] Extreme detector channel selection */
+#define DFSDM_FLTCR2_CKABIE 0x00000040U /*!< Clock absence interrupt enable */
+#define DFSDM_FLTCR2_SCDIE 0x00000020U /*!< Short circuit detector interrupt enable */
+#define DFSDM_FLTCR2_AWDIE 0x00000010U /*!< Analog watchdog interrupt enable */
+#define DFSDM_FLTCR2_ROVRIE 0x00000008U /*!< Regular data overrun interrupt enable */
+#define DFSDM_FLTCR2_JOVRIE 0x00000004U /*!< Injected data overrun interrupt enable */
+#define DFSDM_FLTCR2_REOCIE 0x00000002U /*!< Regular end of conversion interrupt enable */
+#define DFSDM_FLTCR2_JEOCIE 0x00000001U /*!< Injected end of conversion interrupt enable */
+
+/***************** Bit definition for DFSDM_FLTISR register *******************/
+#define DFSDM_FLTISR_SCDF 0x0F000000U /*!< SCDF[7:0] Short circuit detector flag */
+#define DFSDM_FLTISR_CKABF 0x000F0000U /*!< CKABF[7:0] Clock absence flag */
+#define DFSDM_FLTISR_RCIP 0x00004000U /*!< Regular conversion in progress status */
+#define DFSDM_FLTISR_JCIP 0x00002000U /*!< Injected conversion in progress status */
+#define DFSDM_FLTISR_AWDF 0x00000010U /*!< Analog watchdog */
+#define DFSDM_FLTISR_ROVRF 0x00000008U /*!< Regular conversion overrun flag */
+#define DFSDM_FLTISR_JOVRF 0x00000004U /*!< Injected conversion overrun flag */
+#define DFSDM_FLTISR_REOCF 0x00000002U /*!< End of regular conversion flag */
+#define DFSDM_FLTISR_JEOCF 0x00000001U /*!< End of injected conversion flag */
+
+/***************** Bit definition for DFSDM_FLTICR register *******************/
+#define DFSDM_FLTICR_CLRSCSDF 0x0F000000U /*!< CLRSCSDF[7:0] Clear the short circuit detector flag */
+#define DFSDM_FLTICR_CLRCKABF 0x000F0000U /*!< CLRCKABF[7:0] Clear the clock absence flag */
+#define DFSDM_FLTICR_CLRROVRF 0x00000008U /*!< Clear the regular conversion overrun flag */
+#define DFSDM_FLTICR_CLRJOVRF 0x00000004U /*!< Clear the injected conversion overrun flag */
+
+/**************** Bit definition for DFSDM_FLTJCHGR register ******************/
+#define DFSDM_FLTJCHGR_JCHG 0x0000000FU /*!< JCHG[7:0] Injected channel group selection */
+
+/***************** Bit definition for DFSDM_FLTFCR register *******************/
+#define DFSDM_FLTFCR_FORD 0xE0000000U /*!< FORD[2:0] Sinc filter order */
+#define DFSDM_FLTFCR_FORD_2 0x80000000U /*!< Sinc filter order, Bit 2 */
+#define DFSDM_FLTFCR_FORD_1 0x40000000U /*!< Sinc filter order, Bit 1 */
+#define DFSDM_FLTFCR_FORD_0 0x20000000U /*!< Sinc filter order, Bit 0 */
+#define DFSDM_FLTFCR_FOSR 0x03FF0000U /*!< FOSR[9:0] Sinc filter oversampling ratio (decimation rate) */
+#define DFSDM_FLTFCR_IOSR 0x000000FFU /*!< IOSR[7:0] Integrator oversampling ratio (averaging length) */
+
+/*************** Bit definition for DFSDM_FLTJDATAR register *****************/
+#define DFSDM_FLTJDATAR_JDATA 0xFFFFFF00U /*!< JDATA[23:0] Injected group conversion data */
+#define DFSDM_FLTJDATAR_JDATACH 0x00000007U /*!< JDATACH[2:0] Injected channel most recently converted */
+
+/*************** Bit definition for DFSDM_FLTRDATAR register *****************/
+#define DFSDM_FLTRDATAR_RDATA 0xFFFFFF00U /*!< RDATA[23:0] Regular channel conversion data */
+#define DFSDM_FLTRDATAR_RPEND 0x00000010U /*!< RPEND Regular channel pending data */
+#define DFSDM_FLTRDATAR_RDATACH 0x00000007U /*!< RDATACH[2:0] Regular channel most recently converted */
+
+/*************** Bit definition for DFSDM_FLTAWHTR register ******************/
+#define DFSDM_FLTAWHTR_AWHT 0xFFFFFF00U /*!< AWHT[23:0] Analog watchdog high threshold */
+#define DFSDM_FLTAWHTR_BKAWH 0x0000000FU /*!< BKAWH[3:0] Break signal assignment to analog watchdog high threshold event */
+
+/*************** Bit definition for DFSDM_FLTAWLTR register ******************/
+#define DFSDM_FLTAWLTR_AWLT 0xFFFFFF00U /*!< AWLT[23:0] Analog watchdog low threshold */
+#define DFSDM_FLTAWLTR_BKAWL 0x0000000FU /*!< BKAWL[3:0] Break signal assignment to analog watchdog low threshold event */
+
+/*************** Bit definition for DFSDM_FLTAWSR register *******************/
+#define DFSDM_FLTAWSR_AWHTF 0x00000F00U /*!< AWHTF[15:8] Analog watchdog high threshold error on given channels */
+#define DFSDM_FLTAWSR_AWLTF 0x0000000FU /*!< AWLTF[7:0] Analog watchdog low threshold error on given channels */
+
+/*************** Bit definition for DFSDM_FLTAWCFR register ******************/
+#define DFSDM_FLTAWCFR_CLRAWHTF 0x00000F00U /*!< CLRAWHTF[15:8] Clear the Analog watchdog high threshold flag */
+#define DFSDM_FLTAWCFR_CLRAWLTF 0x0000000FU /*!< CLRAWLTF[7:0] Clear the Analog watchdog low threshold flag */
+
+/*************** Bit definition for DFSDM_FLTEXMAX register ******************/
+#define DFSDM_FLTEXMAX_EXMAX 0xFFFFFF00U /*!< EXMAX[23:0] Extreme detector maximum value */
+#define DFSDM_FLTEXMAX_EXMAXCH 0x00000007U /*!< EXMAXCH[2:0] Extreme detector maximum data channel */
+
+/*************** Bit definition for DFSDM_FLTEXMIN register ******************/
+#define DFSDM_FLTEXMIN_EXMIN 0xFFFFFF00U /*!< EXMIN[23:0] Extreme detector minimum value */
+#define DFSDM_FLTEXMIN_EXMINCH 0x00000007U /*!< EXMINCH[2:0] Extreme detector minimum data channel */
+
+/*************** Bit definition for DFSDM_FLTCNVTIMR register ****************/
+#define DFSDM_FLTCNVTIMR_CNVCNT 0xFFFFFFF0U /*!< CNVCNT[27:0]: 28-bit timer counting conversion time */
+
+/******************************************************************************/
+/* */
+/* DMA Controller */
+/* */
+/******************************************************************************/
+/******************** Bits definition for DMA_SxCR register *****************/
+#define DMA_SxCR_CHSEL 0x0E000000U
+#define DMA_SxCR_CHSEL_0 0x02000000U
+#define DMA_SxCR_CHSEL_1 0x04000000U
+#define DMA_SxCR_CHSEL_2 0x08000000U
+#define DMA_SxCR_MBURST 0x01800000U
+#define DMA_SxCR_MBURST_0 0x00800000U
+#define DMA_SxCR_MBURST_1 0x01000000U
+#define DMA_SxCR_PBURST 0x00600000U
+#define DMA_SxCR_PBURST_0 0x00200000U
+#define DMA_SxCR_PBURST_1 0x00400000U
+#define DMA_SxCR_CT 0x00080000U
+#define DMA_SxCR_DBM 0x00040000U
+#define DMA_SxCR_PL 0x00030000U
+#define DMA_SxCR_PL_0 0x00010000U
+#define DMA_SxCR_PL_1 0x00020000U
+#define DMA_SxCR_PINCOS 0x00008000U
+#define DMA_SxCR_MSIZE 0x00006000U
+#define DMA_SxCR_MSIZE_0 0x00002000U
+#define DMA_SxCR_MSIZE_1 0x00004000U
+#define DMA_SxCR_PSIZE 0x00001800U
+#define DMA_SxCR_PSIZE_0 0x00000800U
+#define DMA_SxCR_PSIZE_1 0x00001000U
+#define DMA_SxCR_MINC 0x00000400U
+#define DMA_SxCR_PINC 0x00000200U
+#define DMA_SxCR_CIRC 0x00000100U
+#define DMA_SxCR_DIR 0x000000C0U
+#define DMA_SxCR_DIR_0 0x00000040U
+#define DMA_SxCR_DIR_1 0x00000080U
+#define DMA_SxCR_PFCTRL 0x00000020U
+#define DMA_SxCR_TCIE 0x00000010U
+#define DMA_SxCR_HTIE 0x00000008U
+#define DMA_SxCR_TEIE 0x00000004U
+#define DMA_SxCR_DMEIE 0x00000002U
+#define DMA_SxCR_EN 0x00000001U
+
+/* Legacy defines */
+#define DMA_SxCR_ACK 0x00100000U
+
+/******************** Bits definition for DMA_SxCNDTR register **************/
+#define DMA_SxNDT 0x0000FFFFU
+#define DMA_SxNDT_0 0x00000001U
+#define DMA_SxNDT_1 0x00000002U
+#define DMA_SxNDT_2 0x00000004U
+#define DMA_SxNDT_3 0x00000008U
+#define DMA_SxNDT_4 0x00000010U
+#define DMA_SxNDT_5 0x00000020U
+#define DMA_SxNDT_6 0x00000040U
+#define DMA_SxNDT_7 0x00000080U
+#define DMA_SxNDT_8 0x00000100U
+#define DMA_SxNDT_9 0x00000200U
+#define DMA_SxNDT_10 0x00000400U
+#define DMA_SxNDT_11 0x00000800U
+#define DMA_SxNDT_12 0x00001000U
+#define DMA_SxNDT_13 0x00002000U
+#define DMA_SxNDT_14 0x00004000U
+#define DMA_SxNDT_15 0x00008000U
+
+/******************** Bits definition for DMA_SxFCR register ****************/
+#define DMA_SxFCR_FEIE 0x00000080U
+#define DMA_SxFCR_FS 0x00000038U
+#define DMA_SxFCR_FS_0 0x00000008U
+#define DMA_SxFCR_FS_1 0x00000010U
+#define DMA_SxFCR_FS_2 0x00000020U
+#define DMA_SxFCR_DMDIS 0x00000004U
+#define DMA_SxFCR_FTH 0x00000003U
+#define DMA_SxFCR_FTH_0 0x00000001U
+#define DMA_SxFCR_FTH_1 0x00000002U
+
+/******************** Bits definition for DMA_LISR register *****************/
+#define DMA_LISR_TCIF3 0x08000000U
+#define DMA_LISR_HTIF3 0x04000000U
+#define DMA_LISR_TEIF3 0x02000000U
+#define DMA_LISR_DMEIF3 0x01000000U
+#define DMA_LISR_FEIF3 0x00400000U
+#define DMA_LISR_TCIF2 0x00200000U
+#define DMA_LISR_HTIF2 0x00100000U
+#define DMA_LISR_TEIF2 0x00080000U
+#define DMA_LISR_DMEIF2 0x00040000U
+#define DMA_LISR_FEIF2 0x00010000U
+#define DMA_LISR_TCIF1 0x00000800U
+#define DMA_LISR_HTIF1 0x00000400U
+#define DMA_LISR_TEIF1 0x00000200U
+#define DMA_LISR_DMEIF1 0x00000100U
+#define DMA_LISR_FEIF1 0x00000040U
+#define DMA_LISR_TCIF0 0x00000020U
+#define DMA_LISR_HTIF0 0x00000010U
+#define DMA_LISR_TEIF0 0x00000008U
+#define DMA_LISR_DMEIF0 0x00000004U
+#define DMA_LISR_FEIF0 0x00000001U
+
+/******************** Bits definition for DMA_HISR register *****************/
+#define DMA_HISR_TCIF7 0x08000000U
+#define DMA_HISR_HTIF7 0x04000000U
+#define DMA_HISR_TEIF7 0x02000000U
+#define DMA_HISR_DMEIF7 0x01000000U
+#define DMA_HISR_FEIF7 0x00400000U
+#define DMA_HISR_TCIF6 0x00200000U
+#define DMA_HISR_HTIF6 0x00100000U
+#define DMA_HISR_TEIF6 0x00080000U
+#define DMA_HISR_DMEIF6 0x00040000U
+#define DMA_HISR_FEIF6 0x00010000U
+#define DMA_HISR_TCIF5 0x00000800U
+#define DMA_HISR_HTIF5 0x00000400U
+#define DMA_HISR_TEIF5 0x00000200U
+#define DMA_HISR_DMEIF5 0x00000100U
+#define DMA_HISR_FEIF5 0x00000040U
+#define DMA_HISR_TCIF4 0x00000020U
+#define DMA_HISR_HTIF4 0x00000010U
+#define DMA_HISR_TEIF4 0x00000008U
+#define DMA_HISR_DMEIF4 0x00000004U
+#define DMA_HISR_FEIF4 0x00000001U
+
+/******************** Bits definition for DMA_LIFCR register ****************/
+#define DMA_LIFCR_CTCIF3 0x08000000U
+#define DMA_LIFCR_CHTIF3 0x04000000U
+#define DMA_LIFCR_CTEIF3 0x02000000U
+#define DMA_LIFCR_CDMEIF3 0x01000000U
+#define DMA_LIFCR_CFEIF3 0x00400000U
+#define DMA_LIFCR_CTCIF2 0x00200000U
+#define DMA_LIFCR_CHTIF2 0x00100000U
+#define DMA_LIFCR_CTEIF2 0x00080000U
+#define DMA_LIFCR_CDMEIF2 0x00040000U
+#define DMA_LIFCR_CFEIF2 0x00010000U
+#define DMA_LIFCR_CTCIF1 0x00000800U
+#define DMA_LIFCR_CHTIF1 0x00000400U
+#define DMA_LIFCR_CTEIF1 0x00000200U
+#define DMA_LIFCR_CDMEIF1 0x00000100U
+#define DMA_LIFCR_CFEIF1 0x00000040U
+#define DMA_LIFCR_CTCIF0 0x00000020U
+#define DMA_LIFCR_CHTIF0 0x00000010U
+#define DMA_LIFCR_CTEIF0 0x00000008U
+#define DMA_LIFCR_CDMEIF0 0x00000004U
+#define DMA_LIFCR_CFEIF0 0x00000001U
+
+/******************** Bits definition for DMA_HIFCR register ****************/
+#define DMA_HIFCR_CTCIF7 0x08000000U
+#define DMA_HIFCR_CHTIF7 0x04000000U
+#define DMA_HIFCR_CTEIF7 0x02000000U
+#define DMA_HIFCR_CDMEIF7 0x01000000U
+#define DMA_HIFCR_CFEIF7 0x00400000U
+#define DMA_HIFCR_CTCIF6 0x00200000U
+#define DMA_HIFCR_CHTIF6 0x00100000U
+#define DMA_HIFCR_CTEIF6 0x00080000U
+#define DMA_HIFCR_CDMEIF6 0x00040000U
+#define DMA_HIFCR_CFEIF6 0x00010000U
+#define DMA_HIFCR_CTCIF5 0x00000800U
+#define DMA_HIFCR_CHTIF5 0x00000400U
+#define DMA_HIFCR_CTEIF5 0x00000200U
+#define DMA_HIFCR_CDMEIF5 0x00000100U
+#define DMA_HIFCR_CFEIF5 0x00000040U
+#define DMA_HIFCR_CTCIF4 0x00000020U
+#define DMA_HIFCR_CHTIF4 0x00000010U
+#define DMA_HIFCR_CTEIF4 0x00000008U
+#define DMA_HIFCR_CDMEIF4 0x00000004U
+#define DMA_HIFCR_CFEIF4 0x00000001U
+
+
+/******************************************************************************/
+/* */
+/* External Interrupt/Event Controller */
+/* */
+/******************************************************************************/
+/******************* Bit definition for EXTI_IMR register *******************/
+#define EXTI_IMR_MR0 0x00000001U /*!< Interrupt Mask on line 0 */
+#define EXTI_IMR_MR1 0x00000002U /*!< Interrupt Mask on line 1 */
+#define EXTI_IMR_MR2 0x00000004U /*!< Interrupt Mask on line 2 */
+#define EXTI_IMR_MR3 0x00000008U /*!< Interrupt Mask on line 3 */
+#define EXTI_IMR_MR4 0x00000010U /*!< Interrupt Mask on line 4 */
+#define EXTI_IMR_MR5 0x00000020U /*!< Interrupt Mask on line 5 */
+#define EXTI_IMR_MR6 0x00000040U /*!< Interrupt Mask on line 6 */
+#define EXTI_IMR_MR7 0x00000080U /*!< Interrupt Mask on line 7 */
+#define EXTI_IMR_MR8 0x00000100U /*!< Interrupt Mask on line 8 */
+#define EXTI_IMR_MR9 0x00000200U /*!< Interrupt Mask on line 9 */
+#define EXTI_IMR_MR10 0x00000400U /*!< Interrupt Mask on line 10 */
+#define EXTI_IMR_MR11 0x00000800U /*!< Interrupt Mask on line 11 */
+#define EXTI_IMR_MR12 0x00001000U /*!< Interrupt Mask on line 12 */
+#define EXTI_IMR_MR13 0x00002000U /*!< Interrupt Mask on line 13 */
+#define EXTI_IMR_MR14 0x00004000U /*!< Interrupt Mask on line 14 */
+#define EXTI_IMR_MR15 0x00008000U /*!< Interrupt Mask on line 15 */
+#define EXTI_IMR_MR16 0x00010000U /*!< Interrupt Mask on line 16 */
+#define EXTI_IMR_MR17 0x00020000U /*!< Interrupt Mask on line 17 */
+#define EXTI_IMR_MR18 0x00040000U /*!< Interrupt Mask on line 18 */
+#define EXTI_IMR_MR19 0x00080000U /*!< Interrupt Mask on line 19 */
+#define EXTI_IMR_MR20 0x00100000U /*!< Interrupt Mask on line 20 */
+#define EXTI_IMR_MR21 0x00200000U /*!< Interrupt Mask on line 21 */
+#define EXTI_IMR_MR22 0x00400000U /*!< Interrupt Mask on line 22 */
+
+/******************* Bit definition for EXTI_EMR register *******************/
+#define EXTI_EMR_MR0 0x00000001U /*!< Event Mask on line 0 */
+#define EXTI_EMR_MR1 0x00000002U /*!< Event Mask on line 1 */
+#define EXTI_EMR_MR2 0x00000004U /*!< Event Mask on line 2 */
+#define EXTI_EMR_MR3 0x00000008U /*!< Event Mask on line 3 */
+#define EXTI_EMR_MR4 0x00000010U /*!< Event Mask on line 4 */
+#define EXTI_EMR_MR5 0x00000020U /*!< Event Mask on line 5 */
+#define EXTI_EMR_MR6 0x00000040U /*!< Event Mask on line 6 */
+#define EXTI_EMR_MR7 0x00000080U /*!< Event Mask on line 7 */
+#define EXTI_EMR_MR8 0x00000100U /*!< Event Mask on line 8 */
+#define EXTI_EMR_MR9 0x00000200U /*!< Event Mask on line 9 */
+#define EXTI_EMR_MR10 0x00000400U /*!< Event Mask on line 10 */
+#define EXTI_EMR_MR11 0x00000800U /*!< Event Mask on line 11 */
+#define EXTI_EMR_MR12 0x00001000U /*!< Event Mask on line 12 */
+#define EXTI_EMR_MR13 0x00002000U /*!< Event Mask on line 13 */
+#define EXTI_EMR_MR14 0x00004000U /*!< Event Mask on line 14 */
+#define EXTI_EMR_MR15 0x00008000U /*!< Event Mask on line 15 */
+#define EXTI_EMR_MR16 0x00010000U /*!< Event Mask on line 16 */
+#define EXTI_EMR_MR17 0x00020000U /*!< Event Mask on line 17 */
+#define EXTI_EMR_MR18 0x00040000U /*!< Event Mask on line 18 */
+#define EXTI_EMR_MR19 0x00080000U /*!< Event Mask on line 19 */
+#define EXTI_EMR_MR20 0x00100000U /*!< Event Mask on line 20 */
+#define EXTI_EMR_MR21 0x00200000U /*!< Event Mask on line 21 */
+#define EXTI_EMR_MR22 0x00400000U /*!< Event Mask on line 22 */
+
+/****************** Bit definition for EXTI_RTSR register *******************/
+#define EXTI_RTSR_TR0 0x00000001U /*!< Rising trigger event configuration bit of line 0 */
+#define EXTI_RTSR_TR1 0x00000002U /*!< Rising trigger event configuration bit of line 1 */
+#define EXTI_RTSR_TR2 0x00000004U /*!< Rising trigger event configuration bit of line 2 */
+#define EXTI_RTSR_TR3 0x00000008U /*!< Rising trigger event configuration bit of line 3 */
+#define EXTI_RTSR_TR4 0x00000010U /*!< Rising trigger event configuration bit of line 4 */
+#define EXTI_RTSR_TR5 0x00000020U /*!< Rising trigger event configuration bit of line 5 */
+#define EXTI_RTSR_TR6 0x00000040U /*!< Rising trigger event configuration bit of line 6 */
+#define EXTI_RTSR_TR7 0x00000080U /*!< Rising trigger event configuration bit of line 7 */
+#define EXTI_RTSR_TR8 0x00000100U /*!< Rising trigger event configuration bit of line 8 */
+#define EXTI_RTSR_TR9 0x00000200U /*!< Rising trigger event configuration bit of line 9 */
+#define EXTI_RTSR_TR10 0x00000400U /*!< Rising trigger event configuration bit of line 10 */
+#define EXTI_RTSR_TR11 0x00000800U /*!< Rising trigger event configuration bit of line 11 */
+#define EXTI_RTSR_TR12 0x00001000U /*!< Rising trigger event configuration bit of line 12 */
+#define EXTI_RTSR_TR13 0x00002000U /*!< Rising trigger event configuration bit of line 13 */
+#define EXTI_RTSR_TR14 0x00004000U /*!< Rising trigger event configuration bit of line 14 */
+#define EXTI_RTSR_TR15 0x00008000U /*!< Rising trigger event configuration bit of line 15 */
+#define EXTI_RTSR_TR16 0x00010000U /*!< Rising trigger event configuration bit of line 16 */
+#define EXTI_RTSR_TR17 0x00020000U /*!< Rising trigger event configuration bit of line 17 */
+#define EXTI_RTSR_TR18 0x00040000U /*!< Rising trigger event configuration bit of line 18 */
+#define EXTI_RTSR_TR19 0x00080000U /*!< Rising trigger event configuration bit of line 19 */
+#define EXTI_RTSR_TR20 0x00100000U /*!< Rising trigger event configuration bit of line 20 */
+#define EXTI_RTSR_TR21 0x00200000U /*!< Rising trigger event configuration bit of line 21 */
+#define EXTI_RTSR_TR22 0x00400000U /*!< Rising trigger event configuration bit of line 22 */
+
+/****************** Bit definition for EXTI_FTSR register *******************/
+#define EXTI_FTSR_TR0 0x00000001U /*!< Falling trigger event configuration bit of line 0 */
+#define EXTI_FTSR_TR1 0x00000002U /*!< Falling trigger event configuration bit of line 1 */
+#define EXTI_FTSR_TR2 0x00000004U /*!< Falling trigger event configuration bit of line 2 */
+#define EXTI_FTSR_TR3 0x00000008U /*!< Falling trigger event configuration bit of line 3 */
+#define EXTI_FTSR_TR4 0x00000010U /*!< Falling trigger event configuration bit of line 4 */
+#define EXTI_FTSR_TR5 0x00000020U /*!< Falling trigger event configuration bit of line 5 */
+#define EXTI_FTSR_TR6 0x00000040U /*!< Falling trigger event configuration bit of line 6 */
+#define EXTI_FTSR_TR7 0x00000080U /*!< Falling trigger event configuration bit of line 7 */
+#define EXTI_FTSR_TR8 0x00000100U /*!< Falling trigger event configuration bit of line 8 */
+#define EXTI_FTSR_TR9 0x00000200U /*!< Falling trigger event configuration bit of line 9 */
+#define EXTI_FTSR_TR10 0x00000400U /*!< Falling trigger event configuration bit of line 10 */
+#define EXTI_FTSR_TR11 0x00000800U /*!< Falling trigger event configuration bit of line 11 */
+#define EXTI_FTSR_TR12 0x00001000U /*!< Falling trigger event configuration bit of line 12 */
+#define EXTI_FTSR_TR13 0x00002000U /*!< Falling trigger event configuration bit of line 13 */
+#define EXTI_FTSR_TR14 0x00004000U /*!< Falling trigger event configuration bit of line 14 */
+#define EXTI_FTSR_TR15 0x00008000U /*!< Falling trigger event configuration bit of line 15 */
+#define EXTI_FTSR_TR16 0x00010000U /*!< Falling trigger event configuration bit of line 16 */
+#define EXTI_FTSR_TR17 0x00020000U /*!< Falling trigger event configuration bit of line 17 */
+#define EXTI_FTSR_TR18 0x00040000U /*!< Falling trigger event configuration bit of line 18 */
+#define EXTI_FTSR_TR19 0x00080000U /*!< Falling trigger event configuration bit of line 19 */
+#define EXTI_FTSR_TR20 0x00100000U /*!< Falling trigger event configuration bit of line 20 */
+#define EXTI_FTSR_TR21 0x00200000U /*!< Falling trigger event configuration bit of line 21 */
+#define EXTI_FTSR_TR22 0x00400000U /*!< Falling trigger event configuration bit of line 22 */
+
+/****************** Bit definition for EXTI_SWIER register ******************/
+#define EXTI_SWIER_SWIER0 0x00000001U /*!< Software Interrupt on line 0 */
+#define EXTI_SWIER_SWIER1 0x00000002U /*!< Software Interrupt on line 1 */
+#define EXTI_SWIER_SWIER2 0x00000004U /*!< Software Interrupt on line 2 */
+#define EXTI_SWIER_SWIER3 0x00000008U /*!< Software Interrupt on line 3 */
+#define EXTI_SWIER_SWIER4 0x00000010U /*!< Software Interrupt on line 4 */
+#define EXTI_SWIER_SWIER5 0x00000020U /*!< Software Interrupt on line 5 */
+#define EXTI_SWIER_SWIER6 0x00000040U /*!< Software Interrupt on line 6 */
+#define EXTI_SWIER_SWIER7 0x00000080U /*!< Software Interrupt on line 7 */
+#define EXTI_SWIER_SWIER8 0x00000100U /*!< Software Interrupt on line 8 */
+#define EXTI_SWIER_SWIER9 0x00000200U /*!< Software Interrupt on line 9 */
+#define EXTI_SWIER_SWIER10 0x00000400U /*!< Software Interrupt on line 10 */
+#define EXTI_SWIER_SWIER11 0x00000800U /*!< Software Interrupt on line 11 */
+#define EXTI_SWIER_SWIER12 0x00001000U /*!< Software Interrupt on line 12 */
+#define EXTI_SWIER_SWIER13 0x00002000U /*!< Software Interrupt on line 13 */
+#define EXTI_SWIER_SWIER14 0x00004000U /*!< Software Interrupt on line 14 */
+#define EXTI_SWIER_SWIER15 0x00008000U /*!< Software Interrupt on line 15 */
+#define EXTI_SWIER_SWIER16 0x00010000U /*!< Software Interrupt on line 16 */
+#define EXTI_SWIER_SWIER17 0x00020000U /*!< Software Interrupt on line 17 */
+#define EXTI_SWIER_SWIER18 0x00040000U /*!< Software Interrupt on line 18 */
+#define EXTI_SWIER_SWIER19 0x00080000U /*!< Software Interrupt on line 19 */
+#define EXTI_SWIER_SWIER20 0x00100000U /*!< Software Interrupt on line 20 */
+#define EXTI_SWIER_SWIER21 0x00200000U /*!< Software Interrupt on line 21 */
+#define EXTI_SWIER_SWIER22 0x00400000U /*!< Software Interrupt on line 22 */
+
+/******************* Bit definition for EXTI_PR register ********************/
+#define EXTI_PR_PR0 0x00000001U /*!< Pending bit for line 0 */
+#define EXTI_PR_PR1 0x00000002U /*!< Pending bit for line 1 */
+#define EXTI_PR_PR2 0x00000004U /*!< Pending bit for line 2 */
+#define EXTI_PR_PR3 0x00000008U /*!< Pending bit for line 3 */
+#define EXTI_PR_PR4 0x00000010U /*!< Pending bit for line 4 */
+#define EXTI_PR_PR5 0x00000020U /*!< Pending bit for line 5 */
+#define EXTI_PR_PR6 0x00000040U /*!< Pending bit for line 6 */
+#define EXTI_PR_PR7 0x00000080U /*!< Pending bit for line 7 */
+#define EXTI_PR_PR8 0x00000100U /*!< Pending bit for line 8 */
+#define EXTI_PR_PR9 0x00000200U /*!< Pending bit for line 9 */
+#define EXTI_PR_PR10 0x00000400U /*!< Pending bit for line 10 */
+#define EXTI_PR_PR11 0x00000800U /*!< Pending bit for line 11 */
+#define EXTI_PR_PR12 0x00001000U /*!< Pending bit for line 12 */
+#define EXTI_PR_PR13 0x00002000U /*!< Pending bit for line 13 */
+#define EXTI_PR_PR14 0x00004000U /*!< Pending bit for line 14 */
+#define EXTI_PR_PR15 0x00008000U /*!< Pending bit for line 15 */
+#define EXTI_PR_PR16 0x00010000U /*!< Pending bit for line 16 */
+#define EXTI_PR_PR17 0x00020000U /*!< Pending bit for line 17 */
+#define EXTI_PR_PR18 0x00040000U /*!< Pending bit for line 18 */
+#define EXTI_PR_PR19 0x00080000U /*!< Pending bit for line 19 */
+#define EXTI_PR_PR20 0x00100000U /*!< Pending bit for line 20 */
+#define EXTI_PR_PR21 0x00200000U /*!< Pending bit for line 21 */
+#define EXTI_PR_PR22 0x00400000U /*!< Pending bit for line 22 */
+
+/******************************************************************************/
+/* */
+/* FLASH */
+/* */
+/******************************************************************************/
+/******************* Bits definition for FLASH_ACR register *****************/
+#define FLASH_ACR_LATENCY 0x0000000FU
+#define FLASH_ACR_LATENCY_0WS 0x00000000U
+#define FLASH_ACR_LATENCY_1WS 0x00000001U
+#define FLASH_ACR_LATENCY_2WS 0x00000002U
+#define FLASH_ACR_LATENCY_3WS 0x00000003U
+#define FLASH_ACR_LATENCY_4WS 0x00000004U
+#define FLASH_ACR_LATENCY_5WS 0x00000005U
+#define FLASH_ACR_LATENCY_6WS 0x00000006U
+#define FLASH_ACR_LATENCY_7WS 0x00000007U
+
+#define FLASH_ACR_PRFTEN 0x00000100U
+#define FLASH_ACR_ICEN 0x00000200U
+#define FLASH_ACR_DCEN 0x00000400U
+#define FLASH_ACR_ICRST 0x00000800U
+#define FLASH_ACR_DCRST 0x00001000U
+#define FLASH_ACR_BYTE0_ADDRESS 0x40023C00U
+#define FLASH_ACR_BYTE2_ADDRESS 0x40023C03U
+
+/******************* Bits definition for FLASH_SR register ******************/
+#define FLASH_SR_EOP 0x00000001U
+#define FLASH_SR_SOP 0x00000002U
+#define FLASH_SR_WRPERR 0x00000010U
+#define FLASH_SR_PGAERR 0x00000020U
+#define FLASH_SR_PGPERR 0x00000040U
+#define FLASH_SR_PGSERR 0x00000080U
+#define FLASH_SR_BSY 0x00010000U
+
+/******************* Bits definition for FLASH_CR register ******************/
+#define FLASH_CR_PG 0x00000001U
+#define FLASH_CR_SER 0x00000002U
+#define FLASH_CR_MER 0x00000004U
+#define FLASH_CR_SNB 0x000000F8U
+#define FLASH_CR_SNB_0 0x00000008U
+#define FLASH_CR_SNB_1 0x00000010U
+#define FLASH_CR_SNB_2 0x00000020U
+#define FLASH_CR_SNB_3 0x00000040U
+#define FLASH_CR_SNB_4 0x00000080U
+#define FLASH_CR_PSIZE 0x00000300U
+#define FLASH_CR_PSIZE_0 0x00000100U
+#define FLASH_CR_PSIZE_1 0x00000200U
+#define FLASH_CR_STRT 0x00010000U
+#define FLASH_CR_EOPIE 0x01000000U
+#define FLASH_CR_LOCK 0x80000000U
+
+/******************* Bits definition for FLASH_OPTCR register ***************/
+#define FLASH_OPTCR_OPTLOCK 0x00000001U
+#define FLASH_OPTCR_OPTSTRT 0x00000002U
+#define FLASH_OPTCR_BOR_LEV_0 0x00000004U
+#define FLASH_OPTCR_BOR_LEV_1 0x00000008U
+#define FLASH_OPTCR_BOR_LEV 0x0000000CU
+
+#define FLASH_OPTCR_WDG_SW 0x00000020U
+#define FLASH_OPTCR_nRST_STOP 0x00000040U
+#define FLASH_OPTCR_nRST_STDBY 0x00000080U
+#define FLASH_OPTCR_RDP 0x0000FF00U
+#define FLASH_OPTCR_RDP_0 0x00000100U
+#define FLASH_OPTCR_RDP_1 0x00000200U
+#define FLASH_OPTCR_RDP_2 0x00000400U
+#define FLASH_OPTCR_RDP_3 0x00000800U
+#define FLASH_OPTCR_RDP_4 0x00001000U
+#define FLASH_OPTCR_RDP_5 0x00002000U
+#define FLASH_OPTCR_RDP_6 0x00004000U
+#define FLASH_OPTCR_RDP_7 0x00008000U
+#define FLASH_OPTCR_nWRP 0x0FFF0000U
+#define FLASH_OPTCR_nWRP_0 0x00010000U
+#define FLASH_OPTCR_nWRP_1 0x00020000U
+#define FLASH_OPTCR_nWRP_2 0x00040000U
+#define FLASH_OPTCR_nWRP_3 0x00080000U
+#define FLASH_OPTCR_nWRP_4 0x00100000U
+#define FLASH_OPTCR_nWRP_5 0x00200000U
+#define FLASH_OPTCR_nWRP_6 0x00400000U
+#define FLASH_OPTCR_nWRP_7 0x00800000U
+#define FLASH_OPTCR_nWRP_8 0x01000000U
+#define FLASH_OPTCR_nWRP_9 0x02000000U
+#define FLASH_OPTCR_nWRP_10 0x04000000U
+#define FLASH_OPTCR_nWRP_11 0x08000000U
+
+/****************** Bits definition for FLASH_OPTCR1 register ***************/
+#define FLASH_OPTCR1_nWRP 0x0FFF0000U
+#define FLASH_OPTCR1_nWRP_0 0x00010000U
+#define FLASH_OPTCR1_nWRP_1 0x00020000U
+#define FLASH_OPTCR1_nWRP_2 0x00040000U
+#define FLASH_OPTCR1_nWRP_3 0x00080000U
+#define FLASH_OPTCR1_nWRP_4 0x00100000U
+#define FLASH_OPTCR1_nWRP_5 0x00200000U
+#define FLASH_OPTCR1_nWRP_6 0x00400000U
+#define FLASH_OPTCR1_nWRP_7 0x00800000U
+#define FLASH_OPTCR1_nWRP_8 0x01000000U
+#define FLASH_OPTCR1_nWRP_9 0x02000000U
+#define FLASH_OPTCR1_nWRP_10 0x04000000U
+#define FLASH_OPTCR1_nWRP_11 0x08000000U
+
+/******************************************************************************/
+/* */
+/* Flexible Static Memory Controller */
+/* */
+/******************************************************************************/
+/****************** Bit definition for FSMC_BCR1 register *******************/
+#define FSMC_BCR1_MBKEN 0x00000001U /*!<Memory bank enable bit */
+#define FSMC_BCR1_MUXEN 0x00000002U /*!<Address/data multiplexing enable bit */
+
+#define FSMC_BCR1_MTYP 0x0000000CU /*!<MTYP[1:0] bits (Memory type) */
+#define FSMC_BCR1_MTYP_0 0x00000004U /*!<Bit 0 */
+#define FSMC_BCR1_MTYP_1 0x00000008U /*!<Bit 1 */
+
+#define FSMC_BCR1_MWID 0x00000030U /*!<MWID[1:0] bits (Memory data bus width) */
+#define FSMC_BCR1_MWID_0 0x00000010U /*!<Bit 0 */
+#define FSMC_BCR1_MWID_1 0x00000020U /*!<Bit 1 */
+
+#define FSMC_BCR1_FACCEN 0x00000040U /*!<Flash access enable */
+#define FSMC_BCR1_BURSTEN 0x00000100U /*!<Burst enable bit */
+#define FSMC_BCR1_WAITPOL 0x00000200U /*!<Wait signal polarity bit */
+#define FSMC_BCR1_WAITCFG 0x00000800U /*!<Wait timing configuration */
+#define FSMC_BCR1_WREN 0x00001000U /*!<Write enable bit */
+#define FSMC_BCR1_WAITEN 0x00002000U /*!<Wait enable bit */
+#define FSMC_BCR1_EXTMOD 0x00004000U /*!<Extended mode enable */
+#define FSMC_BCR1_ASYNCWAIT 0x00008000U /*!<Asynchronous wait */
+#define FSMC_BCR1_CPSIZE 0x00070000U /*!<CRAM page size */
+#define FSMC_BCR1_CPSIZE_0 0x00010000U /*!<Bit 0 */
+#define FSMC_BCR1_CPSIZE_1 0x00020000U /*!<Bit 1 */
+#define FSMC_BCR1_CPSIZE_2 0x00040000U /*!<Bit 2 */
+#define FSMC_BCR1_CBURSTRW 0x00080000U /*!<Write burst enable */
+#define FSMC_BCR1_CCLKEN 0x00100000U /*!<Continous clock enable */
+#define FSMC_BCR1_WFDIS 0x00200000U /*!<Write FIFO Disable */
+
+/****************** Bit definition for FSMC_BCR2 register *******************/
+#define FSMC_BCR2_MBKEN 0x00000001U /*!<Memory bank enable bit */
+#define FSMC_BCR2_MUXEN 0x00000002U /*!<Address/data multiplexing enable bit */
+
+#define FSMC_BCR2_MTYP 0x0000000CU /*!<MTYP[1:0] bits (Memory type) */
+#define FSMC_BCR2_MTYP_0 0x00000004U /*!<Bit 0 */
+#define FSMC_BCR2_MTYP_1 0x00000008U /*!<Bit 1 */
+
+#define FSMC_BCR2_MWID 0x00000030U /*!<MWID[1:0] bits (Memory data bus width) */
+#define FSMC_BCR2_MWID_0 0x00000010U /*!<Bit 0 */
+#define FSMC_BCR2_MWID_1 0x00000020U /*!<Bit 1 */
+
+#define FSMC_BCR2_FACCEN 0x00000040U /*!<Flash access enable */
+#define FSMC_BCR2_BURSTEN 0x00000100U /*!<Burst enable bit */
+#define FSMC_BCR2_WAITPOL 0x00000200U /*!<Wait signal polarity bit */
+#define FSMC_BCR2_WAITCFG 0x00000800U /*!<Wait timing configuration */
+#define FSMC_BCR2_WREN 0x00001000U /*!<Write enable bit */
+#define FSMC_BCR2_WAITEN 0x00002000U /*!<Wait enable bit */
+#define FSMC_BCR2_EXTMOD 0x00004000U /*!<Extended mode enable */
+#define FSMC_BCR2_ASYNCWAIT 0x00008000U /*!<Asynchronous wait */
+#define FSMC_BCR2_CPSIZE 0x00070000U /*!<CRAM page size */
+#define FSMC_BCR2_CPSIZE_0 0x00010000U /*!<Bit 0 */
+#define FSMC_BCR2_CPSIZE_1 0x00020000U /*!<Bit 1 */
+#define FSMC_BCR2_CPSIZE_2 0x00040000U /*!<Bit 2 */
+#define FSMC_BCR2_CBURSTRW 0x00080000U /*!<Write burst enable */
+
+/****************** Bit definition for FSMC_BCR3 register *******************/
+#define FSMC_BCR3_MBKEN 0x00000001U /*!<Memory bank enable bit */
+#define FSMC_BCR3_MUXEN 0x00000002U /*!<Address/data multiplexing enable bit */
+
+#define FSMC_BCR3_MTYP 0x0000000CU /*!<MTYP[1:0] bits (Memory type) */
+#define FSMC_BCR3_MTYP_0 0x00000004U /*!<Bit 0 */
+#define FSMC_BCR3_MTYP_1 0x00000008U /*!<Bit 1 */
+
+#define FSMC_BCR3_MWID 0x00000030U /*!<MWID[1:0] bits (Memory data bus width) */
+#define FSMC_BCR3_MWID_0 0x00000010U /*!<Bit 0 */
+#define FSMC_BCR3_MWID_1 0x00000020U /*!<Bit 1 */
+
+#define FSMC_BCR3_FACCEN 0x00000040U /*!<Flash access enable */
+#define FSMC_BCR3_BURSTEN 0x00000100U /*!<Burst enable bit */
+#define FSMC_BCR3_WAITPOL 0x00000200U /*!<Wait signal polarity bit */
+#define FSMC_BCR3_WAITCFG 0x00000800U /*!<Wait timing configuration */
+#define FSMC_BCR3_WREN 0x00001000U /*!<Write enable bit */
+#define FSMC_BCR3_WAITEN 0x00002000U /*!<Wait enable bit */
+#define FSMC_BCR3_EXTMOD 0x00004000U /*!<Extended mode enable */
+#define FSMC_BCR3_ASYNCWAIT 0x00008000U /*!<Asynchronous wait */
+#define FSMC_BCR3_CPSIZE 0x00070000U /*!<CRAM page size */
+#define FSMC_BCR3_CPSIZE_0 0x00010000U /*!<Bit 0 */
+#define FSMC_BCR3_CPSIZE_1 0x00020000U /*!<Bit 1 */
+#define FSMC_BCR3_CPSIZE_2 0x00040000U /*!<Bit 2 */
+#define FSMC_BCR3_CBURSTRW 0x00080000U /*!<Write burst enable */
+
+/****************** Bit definition for FSMC_BCR4 register *******************/
+#define FSMC_BCR4_MBKEN 0x00000001U /*!<Memory bank enable bit */
+#define FSMC_BCR4_MUXEN 0x00000002U /*!<Address/data multiplexing enable bit */
+
+#define FSMC_BCR4_MTYP 0x0000000CU /*!<MTYP[1:0] bits (Memory type) */
+#define FSMC_BCR4_MTYP_0 0x00000004U /*!<Bit 0 */
+#define FSMC_BCR4_MTYP_1 0x00000008U /*!<Bit 1 */
+
+#define FSMC_BCR4_MWID 0x00000030U /*!<MWID[1:0] bits (Memory data bus width) */
+#define FSMC_BCR4_MWID_0 0x00000010U /*!<Bit 0 */
+#define FSMC_BCR4_MWID_1 0x00000020U /*!<Bit 1 */
+
+#define FSMC_BCR4_FACCEN 0x00000040U /*!<Flash access enable */
+#define FSMC_BCR4_BURSTEN 0x00000100U /*!<Burst enable bit */
+#define FSMC_BCR4_WAITPOL 0x00000200U /*!<Wait signal polarity bit */
+#define FSMC_BCR4_WAITCFG 0x00000800U /*!<Wait timing configuration */
+#define FSMC_BCR4_WREN 0x00001000U /*!<Write enable bit */
+#define FSMC_BCR4_WAITEN 0x00002000U /*!<Wait enable bit */
+#define FSMC_BCR4_EXTMOD 0x00004000U /*!<Extended mode enable */
+#define FSMC_BCR4_ASYNCWAIT 0x00008000U /*!<Asynchronous wait */
+#define FSMC_BCR4_CPSIZE 0x00070000U /*!<CRAM page size */
+#define FSMC_BCR4_CPSIZE_0 0x00010000U /*!<Bit 0 */
+#define FSMC_BCR4_CPSIZE_1 0x00020000U /*!<Bit 1 */
+#define FSMC_BCR4_CPSIZE_2 0x00040000U /*!<Bit 2 */
+#define FSMC_BCR4_CBURSTRW 0x00080000U /*!<Write burst enable */
+
+/****************** Bit definition for FSMC_BTR1 register ******************/
+#define FSMC_BTR1_ADDSET 0x0000000FU /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FSMC_BTR1_ADDSET_0 0x00000001U /*!<Bit 0 */
+#define FSMC_BTR1_ADDSET_1 0x00000002U /*!<Bit 1 */
+#define FSMC_BTR1_ADDSET_2 0x00000004U /*!<Bit 2 */
+#define FSMC_BTR1_ADDSET_3 0x00000008U /*!<Bit 3 */
+
+#define FSMC_BTR1_ADDHLD 0x000000F0U /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FSMC_BTR1_ADDHLD_0 0x00000010U /*!<Bit 0 */
+#define FSMC_BTR1_ADDHLD_1 0x00000020U /*!<Bit 1 */
+#define FSMC_BTR1_ADDHLD_2 0x00000040U /*!<Bit 2 */
+#define FSMC_BTR1_ADDHLD_3 0x00000080U /*!<Bit 3 */
+
+#define FSMC_BTR1_DATAST 0x0000FF00U /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FSMC_BTR1_DATAST_0 0x00000100U /*!<Bit 0 */
+#define FSMC_BTR1_DATAST_1 0x00000200U /*!<Bit 1 */
+#define FSMC_BTR1_DATAST_2 0x00000400U /*!<Bit 2 */
+#define FSMC_BTR1_DATAST_3 0x00000800U /*!<Bit 3 */
+#define FSMC_BTR1_DATAST_4 0x00001000U /*!<Bit 4 */
+#define FSMC_BTR1_DATAST_5 0x00002000U /*!<Bit 5 */
+#define FSMC_BTR1_DATAST_6 0x00004000U /*!<Bit 6 */
+#define FSMC_BTR1_DATAST_7 0x00008000U /*!<Bit 7 */
+
+#define FSMC_BTR1_BUSTURN 0x000F0000U /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define FSMC_BTR1_BUSTURN_0 0x00010000U /*!<Bit 0 */
+#define FSMC_BTR1_BUSTURN_1 0x00020000U /*!<Bit 1 */
+#define FSMC_BTR1_BUSTURN_2 0x00040000U /*!<Bit 2 */
+#define FSMC_BTR1_BUSTURN_3 0x00080000U /*!<Bit 3 */
+
+#define FSMC_BTR1_CLKDIV 0x00F00000U /*!<CLKDIV[3:0] bits (Clock divide ratio) */
+#define FSMC_BTR1_CLKDIV_0 0x00100000U /*!<Bit 0 */
+#define FSMC_BTR1_CLKDIV_1 0x00200000U /*!<Bit 1 */
+#define FSMC_BTR1_CLKDIV_2 0x00400000U /*!<Bit 2 */
+#define FSMC_BTR1_CLKDIV_3 0x00800000U /*!<Bit 3 */
+
+#define FSMC_BTR1_DATLAT 0x0F000000U /*!<DATLA[3:0] bits (Data latency) */
+#define FSMC_BTR1_DATLAT_0 0x01000000U /*!<Bit 0 */
+#define FSMC_BTR1_DATLAT_1 0x02000000U /*!<Bit 1 */
+#define FSMC_BTR1_DATLAT_2 0x04000000U /*!<Bit 2 */
+#define FSMC_BTR1_DATLAT_3 0x08000000U /*!<Bit 3 */
+
+#define FSMC_BTR1_ACCMOD 0x30000000U /*!<ACCMOD[1:0] bits (Access mode) */
+#define FSMC_BTR1_ACCMOD_0 0x10000000U /*!<Bit 0 */
+#define FSMC_BTR1_ACCMOD_1 0x20000000U /*!<Bit 1 */
+
+/****************** Bit definition for FSMC_BTR2 register *******************/
+#define FSMC_BTR2_ADDSET 0x0000000FU /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FSMC_BTR2_ADDSET_0 0x00000001U /*!<Bit 0 */
+#define FSMC_BTR2_ADDSET_1 0x00000002U /*!<Bit 1 */
+#define FSMC_BTR2_ADDSET_2 0x00000004U /*!<Bit 2 */
+#define FSMC_BTR2_ADDSET_3 0x00000008U /*!<Bit 3 */
+
+#define FSMC_BTR2_ADDHLD 0x000000F0U /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FSMC_BTR2_ADDHLD_0 0x00000010U /*!<Bit 0 */
+#define FSMC_BTR2_ADDHLD_1 0x00000020U /*!<Bit 1 */
+#define FSMC_BTR2_ADDHLD_2 0x00000040U /*!<Bit 2 */
+#define FSMC_BTR2_ADDHLD_3 0x00000080U /*!<Bit 3 */
+
+#define FSMC_BTR2_DATAST 0x0000FF00U /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FSMC_BTR2_DATAST_0 0x00000100U /*!<Bit 0 */
+#define FSMC_BTR2_DATAST_1 0x00000200U /*!<Bit 1 */
+#define FSMC_BTR2_DATAST_2 0x00000400U /*!<Bit 2 */
+#define FSMC_BTR2_DATAST_3 0x00000800U /*!<Bit 3 */
+#define FSMC_BTR2_DATAST_4 0x00001000U /*!<Bit 4 */
+#define FSMC_BTR2_DATAST_5 0x00002000U /*!<Bit 5 */
+#define FSMC_BTR2_DATAST_6 0x00004000U /*!<Bit 6 */
+#define FSMC_BTR2_DATAST_7 0x00008000U /*!<Bit 7 */
+
+#define FSMC_BTR2_BUSTURN 0x000F0000U /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define FSMC_BTR2_BUSTURN_0 0x00010000U /*!<Bit 0 */
+#define FSMC_BTR2_BUSTURN_1 0x00020000U /*!<Bit 1 */
+#define FSMC_BTR2_BUSTURN_2 0x00040000U /*!<Bit 2 */
+#define FSMC_BTR2_BUSTURN_3 0x00080000U /*!<Bit 3 */
+
+#define FSMC_BTR2_CLKDIV 0x00F00000U /*!<CLKDIV[3:0] bits (Clock divide ratio) */
+#define FSMC_BTR2_CLKDIV_0 0x00100000U /*!<Bit 0 */
+#define FSMC_BTR2_CLKDIV_1 0x00200000U /*!<Bit 1 */
+#define FSMC_BTR2_CLKDIV_2 0x00400000U /*!<Bit 2 */
+#define FSMC_BTR2_CLKDIV_3 0x00800000U /*!<Bit 3 */
+
+#define FSMC_BTR2_DATLAT 0x0F000000U /*!<DATLA[3:0] bits (Data latency) */
+#define FSMC_BTR2_DATLAT_0 0x01000000U /*!<Bit 0 */
+#define FSMC_BTR2_DATLAT_1 0x02000000U /*!<Bit 1 */
+#define FSMC_BTR2_DATLAT_2 0x04000000U /*!<Bit 2 */
+#define FSMC_BTR2_DATLAT_3 0x08000000U /*!<Bit 3 */
+
+#define FSMC_BTR2_ACCMOD 0x30000000U /*!<ACCMOD[1:0] bits (Access mode) */
+#define FSMC_BTR2_ACCMOD_0 0x10000000U /*!<Bit 0 */
+#define FSMC_BTR2_ACCMOD_1 0x20000000U /*!<Bit 1 */
+
+/******************* Bit definition for FSMC_BTR3 register *******************/
+#define FSMC_BTR3_ADDSET 0x0000000FU /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FSMC_BTR3_ADDSET_0 0x00000001U /*!<Bit 0 */
+#define FSMC_BTR3_ADDSET_1 0x00000002U /*!<Bit 1 */
+#define FSMC_BTR3_ADDSET_2 0x00000004U /*!<Bit 2 */
+#define FSMC_BTR3_ADDSET_3 0x00000008U /*!<Bit 3 */
+
+#define FSMC_BTR3_ADDHLD 0x000000F0U /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FSMC_BTR3_ADDHLD_0 0x00000010U /*!<Bit 0 */
+#define FSMC_BTR3_ADDHLD_1 0x00000020U /*!<Bit 1 */
+#define FSMC_BTR3_ADDHLD_2 0x00000040U /*!<Bit 2 */
+#define FSMC_BTR3_ADDHLD_3 0x00000080U /*!<Bit 3 */
+
+#define FSMC_BTR3_DATAST 0x0000FF00U /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FSMC_BTR3_DATAST_0 0x00000100U /*!<Bit 0 */
+#define FSMC_BTR3_DATAST_1 0x00000200U /*!<Bit 1 */
+#define FSMC_BTR3_DATAST_2 0x00000400U /*!<Bit 2 */
+#define FSMC_BTR3_DATAST_3 0x00000800U /*!<Bit 3 */
+#define FSMC_BTR3_DATAST_4 0x00001000U /*!<Bit 4 */
+#define FSMC_BTR3_DATAST_5 0x00002000U /*!<Bit 5 */
+#define FSMC_BTR3_DATAST_6 0x00004000U /*!<Bit 6 */
+#define FSMC_BTR3_DATAST_7 0x00008000U /*!<Bit 7 */
+
+#define FSMC_BTR3_BUSTURN 0x000F0000U /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define FSMC_BTR3_BUSTURN_0 0x00010000U /*!<Bit 0 */
+#define FSMC_BTR3_BUSTURN_1 0x00020000U /*!<Bit 1 */
+#define FSMC_BTR3_BUSTURN_2 0x00040000U /*!<Bit 2 */
+#define FSMC_BTR3_BUSTURN_3 0x00080000U /*!<Bit 3 */
+
+#define FSMC_BTR3_CLKDIV 0x00F00000U /*!<CLKDIV[3:0] bits (Clock divide ratio) */
+#define FSMC_BTR3_CLKDIV_0 0x00100000U /*!<Bit 0 */
+#define FSMC_BTR3_CLKDIV_1 0x00200000U /*!<Bit 1 */
+#define FSMC_BTR3_CLKDIV_2 0x00400000U /*!<Bit 2 */
+#define FSMC_BTR3_CLKDIV_3 0x00800000U /*!<Bit 3 */
+
+#define FSMC_BTR3_DATLAT 0x0F000000U /*!<DATLA[3:0] bits (Data latency) */
+#define FSMC_BTR3_DATLAT_0 0x01000000U /*!<Bit 0 */
+#define FSMC_BTR3_DATLAT_1 0x02000000U /*!<Bit 1 */
+#define FSMC_BTR3_DATLAT_2 0x04000000U /*!<Bit 2 */
+#define FSMC_BTR3_DATLAT_3 0x08000000U /*!<Bit 3 */
+
+#define FSMC_BTR3_ACCMOD 0x30000000U /*!<ACCMOD[1:0] bits (Access mode) */
+#define FSMC_BTR3_ACCMOD_0 0x10000000U /*!<Bit 0 */
+#define FSMC_BTR3_ACCMOD_1 0x20000000U /*!<Bit 1 */
+
+/****************** Bit definition for FSMC_BTR4 register *******************/
+#define FSMC_BTR4_ADDSET 0x0000000FU /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FSMC_BTR4_ADDSET_0 0x00000001U /*!<Bit 0 */
+#define FSMC_BTR4_ADDSET_1 0x00000002U /*!<Bit 1 */
+#define FSMC_BTR4_ADDSET_2 0x00000004U /*!<Bit 2 */
+#define FSMC_BTR4_ADDSET_3 0x00000008U /*!<Bit 3 */
+
+#define FSMC_BTR4_ADDHLD 0x000000F0U /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FSMC_BTR4_ADDHLD_0 0x00000010U /*!<Bit 0 */
+#define FSMC_BTR4_ADDHLD_1 0x00000020U /*!<Bit 1 */
+#define FSMC_BTR4_ADDHLD_2 0x00000040U /*!<Bit 2 */
+#define FSMC_BTR4_ADDHLD_3 0x00000080U /*!<Bit 3 */
+
+#define FSMC_BTR4_DATAST 0x0000FF00U /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FSMC_BTR4_DATAST_0 0x00000100U /*!<Bit 0 */
+#define FSMC_BTR4_DATAST_1 0x00000200U /*!<Bit 1 */
+#define FSMC_BTR4_DATAST_2 0x00000400U /*!<Bit 2 */
+#define FSMC_BTR4_DATAST_3 0x00000800U /*!<Bit 3 */
+#define FSMC_BTR4_DATAST_4 0x00001000U /*!<Bit 4 */
+#define FSMC_BTR4_DATAST_5 0x00002000U /*!<Bit 5 */
+#define FSMC_BTR4_DATAST_6 0x00004000U /*!<Bit 6 */
+#define FSMC_BTR4_DATAST_7 0x00008000U /*!<Bit 7 */
+
+#define FSMC_BTR4_BUSTURN 0x000F0000U /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define FSMC_BTR4_BUSTURN_0 0x00010000U /*!<Bit 0 */
+#define FSMC_BTR4_BUSTURN_1 0x00020000U /*!<Bit 1 */
+#define FSMC_BTR4_BUSTURN_2 0x00040000U /*!<Bit 2 */
+#define FSMC_BTR4_BUSTURN_3 0x00080000U /*!<Bit 3 */
+
+#define FSMC_BTR4_CLKDIV 0x00F00000U /*!<CLKDIV[3:0] bits (Clock divide ratio) */
+#define FSMC_BTR4_CLKDIV_0 0x00100000U /*!<Bit 0 */
+#define FSMC_BTR4_CLKDIV_1 0x00200000U /*!<Bit 1 */
+#define FSMC_BTR4_CLKDIV_2 0x00400000U /*!<Bit 2 */
+#define FSMC_BTR4_CLKDIV_3 0x00800000U /*!<Bit 3 */
+
+#define FSMC_BTR4_DATLAT 0x0F000000U /*!<DATLA[3:0] bits (Data latency) */
+#define FSMC_BTR4_DATLAT_0 0x01000000U /*!<Bit 0 */
+#define FSMC_BTR4_DATLAT_1 0x02000000U /*!<Bit 1 */
+#define FSMC_BTR4_DATLAT_2 0x04000000U /*!<Bit 2 */
+#define FSMC_BTR4_DATLAT_3 0x08000000U /*!<Bit 3 */
+
+#define FSMC_BTR4_ACCMOD 0x30000000U /*!<ACCMOD[1:0] bits (Access mode) */
+#define FSMC_BTR4_ACCMOD_0 0x10000000U /*!<Bit 0 */
+#define FSMC_BTR4_ACCMOD_1 0x20000000U /*!<Bit 1 */
+
+/****************** Bit definition for FSMC_BWTR1 register ******************/
+#define FSMC_BWTR1_ADDSET 0x0000000FU /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FSMC_BWTR1_ADDSET_0 0x00000001U /*!<Bit 0 */
+#define FSMC_BWTR1_ADDSET_1 0x00000002U /*!<Bit 1 */
+#define FSMC_BWTR1_ADDSET_2 0x00000004U /*!<Bit 2 */
+#define FSMC_BWTR1_ADDSET_3 0x00000008U /*!<Bit 3 */
+
+#define FSMC_BWTR1_ADDHLD 0x000000F0U /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FSMC_BWTR1_ADDHLD_0 0x00000010U /*!<Bit 0 */
+#define FSMC_BWTR1_ADDHLD_1 0x00000020U /*!<Bit 1 */
+#define FSMC_BWTR1_ADDHLD_2 0x00000040U /*!<Bit 2 */
+#define FSMC_BWTR1_ADDHLD_3 0x00000080U /*!<Bit 3 */
+
+#define FSMC_BWTR1_DATAST 0x0000FF00U /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FSMC_BWTR1_DATAST_0 0x00000100U /*!<Bit 0 */
+#define FSMC_BWTR1_DATAST_1 0x00000200U /*!<Bit 1 */
+#define FSMC_BWTR1_DATAST_2 0x00000400U /*!<Bit 2 */
+#define FSMC_BWTR1_DATAST_3 0x00000800U /*!<Bit 3 */
+#define FSMC_BWTR1_DATAST_4 0x00001000U /*!<Bit 4 */
+#define FSMC_BWTR1_DATAST_5 0x00002000U /*!<Bit 5 */
+#define FSMC_BWTR1_DATAST_6 0x00004000U /*!<Bit 6 */
+#define FSMC_BWTR1_DATAST_7 0x00008000U /*!<Bit 7 */
+
+#define FSMC_BWTR1_BUSTURN 0x000F0000U /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
+#define FSMC_BWTR1_BUSTURN_0 0x00010000U /*!<Bit 0 */
+#define FSMC_BWTR1_BUSTURN_1 0x00020000U /*!<Bit 1 */
+#define FSMC_BWTR1_BUSTURN_2 0x00040000U /*!<Bit 2 */
+#define FSMC_BWTR1_BUSTURN_3 0x00080000U /*!<Bit 3 */
+
+#define FSMC_BWTR1_ACCMOD 0x30000000U /*!<ACCMOD[1:0] bits (Access mode) */
+#define FSMC_BWTR1_ACCMOD_0 0x10000000U /*!<Bit 0 */
+#define FSMC_BWTR1_ACCMOD_1 0x20000000U /*!<Bit 1 */
+
+/****************** Bit definition for FSMC_BWTR2 register ******************/
+#define FSMC_BWTR2_ADDSET 0x0000000FU /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FSMC_BWTR2_ADDSET_0 0x00000001U /*!<Bit 0 */
+#define FSMC_BWTR2_ADDSET_1 0x00000002U /*!<Bit 1 */
+#define FSMC_BWTR2_ADDSET_2 0x00000004U /*!<Bit 2 */
+#define FSMC_BWTR2_ADDSET_3 0x00000008U /*!<Bit 3 */
+
+#define FSMC_BWTR2_ADDHLD 0x000000F0U /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FSMC_BWTR2_ADDHLD_0 0x00000010U /*!<Bit 0 */
+#define FSMC_BWTR2_ADDHLD_1 0x00000020U /*!<Bit 1 */
+#define FSMC_BWTR2_ADDHLD_2 0x00000040U /*!<Bit 2 */
+#define FSMC_BWTR2_ADDHLD_3 0x00000080U /*!<Bit 3 */
+
+#define FSMC_BWTR2_DATAST 0x0000FF00U /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FSMC_BWTR2_DATAST_0 0x00000100U /*!<Bit 0 */
+#define FSMC_BWTR2_DATAST_1 0x00000200U /*!<Bit 1 */
+#define FSMC_BWTR2_DATAST_2 0x00000400U /*!<Bit 2 */
+#define FSMC_BWTR2_DATAST_3 0x00000800U /*!<Bit 3 */
+#define FSMC_BWTR2_DATAST_4 0x00001000U /*!<Bit 4 */
+#define FSMC_BWTR2_DATAST_5 0x00002000U /*!<Bit 5 */
+#define FSMC_BWTR2_DATAST_6 0x00004000U /*!<Bit 6 */
+#define FSMC_BWTR2_DATAST_7 0x00008000U /*!<Bit 7 */
+
+#define FSMC_BWTR2_BUSTURN 0x000F0000U /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
+#define FSMC_BWTR2_BUSTURN_0 0x00010000U /*!<Bit 0 */
+#define FSMC_BWTR2_BUSTURN_1 0x00020000U /*!<Bit 1 */
+#define FSMC_BWTR2_BUSTURN_2 0x00040000U /*!<Bit 2 */
+#define FSMC_BWTR2_BUSTURN_3 0x00080000U /*!<Bit 3 */
+
+#define FSMC_BWTR2_ACCMOD 0x30000000U /*!<ACCMOD[1:0] bits (Access mode) */
+#define FSMC_BWTR2_ACCMOD_0 0x10000000U /*!<Bit 0 */
+#define FSMC_BWTR2_ACCMOD_1 0x20000000U /*!<Bit 1 */
+
+/****************** Bit definition for FSMC_BWTR3 register ******************/
+#define FSMC_BWTR3_ADDSET 0x0000000FU /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FSMC_BWTR3_ADDSET_0 0x00000001U /*!<Bit 0 */
+#define FSMC_BWTR3_ADDSET_1 0x00000002U /*!<Bit 1 */
+#define FSMC_BWTR3_ADDSET_2 0x00000004U /*!<Bit 2 */
+#define FSMC_BWTR3_ADDSET_3 0x00000008U /*!<Bit 3 */
+
+#define FSMC_BWTR3_ADDHLD 0x000000F0U /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FSMC_BWTR3_ADDHLD_0 0x00000010U /*!<Bit 0 */
+#define FSMC_BWTR3_ADDHLD_1 0x00000020U /*!<Bit 1 */
+#define FSMC_BWTR3_ADDHLD_2 0x00000040U /*!<Bit 2 */
+#define FSMC_BWTR3_ADDHLD_3 0x00000080U /*!<Bit 3 */
+
+#define FSMC_BWTR3_DATAST 0x0000FF00U /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FSMC_BWTR3_DATAST_0 0x00000100U /*!<Bit 0 */
+#define FSMC_BWTR3_DATAST_1 0x00000200U /*!<Bit 1 */
+#define FSMC_BWTR3_DATAST_2 0x00000400U /*!<Bit 2 */
+#define FSMC_BWTR3_DATAST_3 0x00000800U /*!<Bit 3 */
+#define FSMC_BWTR3_DATAST_4 0x00001000U /*!<Bit 4 */
+#define FSMC_BWTR3_DATAST_5 0x00002000U /*!<Bit 5 */
+#define FSMC_BWTR3_DATAST_6 0x00004000U /*!<Bit 6 */
+#define FSMC_BWTR3_DATAST_7 0x00008000U /*!<Bit 7 */
+
+#define FSMC_BWTR3_BUSTURN 0x000F0000U /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
+#define FSMC_BWTR3_BUSTURN_0 0x00010000U /*!<Bit 0 */
+#define FSMC_BWTR3_BUSTURN_1 0x00020000U /*!<Bit 1 */
+#define FSMC_BWTR3_BUSTURN_2 0x00040000U /*!<Bit 2 */
+#define FSMC_BWTR3_BUSTURN_3 0x00080000U /*!<Bit 3 */
+
+#define FSMC_BWTR3_ACCMOD 0x30000000U /*!<ACCMOD[1:0] bits (Access mode) */
+#define FSMC_BWTR3_ACCMOD_0 0x10000000U /*!<Bit 0 */
+#define FSMC_BWTR3_ACCMOD_1 0x20000000U /*!<Bit 1 */
+
+/****************** Bit definition for FSMC_BWTR4 register ******************/
+#define FSMC_BWTR4_ADDSET 0x0000000FU /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FSMC_BWTR4_ADDSET_0 0x00000001U /*!<Bit 0 */
+#define FSMC_BWTR4_ADDSET_1 0x00000002U /*!<Bit 1 */
+#define FSMC_BWTR4_ADDSET_2 0x00000004U /*!<Bit 2 */
+#define FSMC_BWTR4_ADDSET_3 0x00000008U /*!<Bit 3 */
+
+#define FSMC_BWTR4_ADDHLD 0x000000F0U /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FSMC_BWTR4_ADDHLD_0 0x00000010U /*!<Bit 0 */
+#define FSMC_BWTR4_ADDHLD_1 0x00000020U /*!<Bit 1 */
+#define FSMC_BWTR4_ADDHLD_2 0x00000040U /*!<Bit 2 */
+#define FSMC_BWTR4_ADDHLD_3 0x00000080U /*!<Bit 3 */
+
+#define FSMC_BWTR4_DATAST 0x0000FF00U /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FSMC_BWTR4_DATAST_0 0x00000100U /*!<Bit 0 */
+#define FSMC_BWTR4_DATAST_1 0x00000200U /*!<Bit 1 */
+#define FSMC_BWTR4_DATAST_2 0x00000400U /*!<Bit 2 */
+#define FSMC_BWTR4_DATAST_3 0x00000800U /*!<Bit 3 */
+#define FSMC_BWTR4_DATAST_4 0x00001000U /*!<Bit 4 */
+#define FSMC_BWTR4_DATAST_5 0x00002000U /*!<Bit 5 */
+#define FSMC_BWTR4_DATAST_6 0x00004000U /*!<Bit 6 */
+#define FSMC_BWTR4_DATAST_7 0x00008000U /*!<Bit 7 */
+
+#define FSMC_BWTR4_BUSTURN 0x000F0000U /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
+#define FSMC_BWTR4_BUSTURN_0 0x00010000U /*!<Bit 0 */
+#define FSMC_BWTR4_BUSTURN_1 0x00020000U /*!<Bit 1 */
+#define FSMC_BWTR4_BUSTURN_2 0x00040000U /*!<Bit 2 */
+#define FSMC_BWTR4_BUSTURN_3 0x00080000U /*!<Bit 3 */
+
+#define FSMC_BWTR4_ACCMOD 0x30000000U /*!<ACCMOD[1:0] bits (Access mode) */
+#define FSMC_BWTR4_ACCMOD_0 0x10000000U /*!<Bit 0 */
+#define FSMC_BWTR4_ACCMOD_1 0x20000000U /*!<Bit 1 */
+
+/******************************************************************************/
+/* */
+/* General Purpose I/O */
+/* */
+/******************************************************************************/
+/****************** Bits definition for GPIO_MODER register *****************/
+#define GPIO_MODER_MODER0 0x00000003U
+#define GPIO_MODER_MODER0_0 0x00000001U
+#define GPIO_MODER_MODER0_1 0x00000002U
+
+#define GPIO_MODER_MODER1 0x0000000CU
+#define GPIO_MODER_MODER1_0 0x00000004U
+#define GPIO_MODER_MODER1_1 0x00000008U
+
+#define GPIO_MODER_MODER2 0x00000030U
+#define GPIO_MODER_MODER2_0 0x00000010U
+#define GPIO_MODER_MODER2_1 0x00000020U
+
+#define GPIO_MODER_MODER3 0x000000C0U
+#define GPIO_MODER_MODER3_0 0x00000040U
+#define GPIO_MODER_MODER3_1 0x00000080U
+
+#define GPIO_MODER_MODER4 0x00000300U
+#define GPIO_MODER_MODER4_0 0x00000100U
+#define GPIO_MODER_MODER4_1 0x00000200U
+
+#define GPIO_MODER_MODER5 0x00000C00U
+#define GPIO_MODER_MODER5_0 0x00000400U
+#define GPIO_MODER_MODER5_1 0x00000800U
+
+#define GPIO_MODER_MODER6 0x00003000U
+#define GPIO_MODER_MODER6_0 0x00001000U
+#define GPIO_MODER_MODER6_1 0x00002000U
+
+#define GPIO_MODER_MODER7 0x0000C000U
+#define GPIO_MODER_MODER7_0 0x00004000U
+#define GPIO_MODER_MODER7_1 0x00008000U
+
+#define GPIO_MODER_MODER8 0x00030000U
+#define GPIO_MODER_MODER8_0 0x00010000U
+#define GPIO_MODER_MODER8_1 0x00020000U
+
+#define GPIO_MODER_MODER9 0x000C0000U
+#define GPIO_MODER_MODER9_0 0x00040000U
+#define GPIO_MODER_MODER9_1 0x00080000U
+
+#define GPIO_MODER_MODER10 0x00300000U
+#define GPIO_MODER_MODER10_0 0x00100000U
+#define GPIO_MODER_MODER10_1 0x00200000U
+
+#define GPIO_MODER_MODER11 0x00C00000U
+#define GPIO_MODER_MODER11_0 0x00400000U
+#define GPIO_MODER_MODER11_1 0x00800000U
+
+#define GPIO_MODER_MODER12 0x03000000U
+#define GPIO_MODER_MODER12_0 0x01000000U
+#define GPIO_MODER_MODER12_1 0x02000000U
+
+#define GPIO_MODER_MODER13 0x0C000000U
+#define GPIO_MODER_MODER13_0 0x04000000U
+#define GPIO_MODER_MODER13_1 0x08000000U
+
+#define GPIO_MODER_MODER14 0x30000000U
+#define GPIO_MODER_MODER14_0 0x10000000U
+#define GPIO_MODER_MODER14_1 0x20000000U
+
+#define GPIO_MODER_MODER15 0xC0000000U
+#define GPIO_MODER_MODER15_0 0x40000000U
+#define GPIO_MODER_MODER15_1 0x80000000U
+
+/****************** Bits definition for GPIO_OTYPER register ****************/
+#define GPIO_OTYPER_OT_0 0x00000001U
+#define GPIO_OTYPER_OT_1 0x00000002U
+#define GPIO_OTYPER_OT_2 0x00000004U
+#define GPIO_OTYPER_OT_3 0x00000008U
+#define GPIO_OTYPER_OT_4 0x00000010U
+#define GPIO_OTYPER_OT_5 0x00000020U
+#define GPIO_OTYPER_OT_6 0x00000040U
+#define GPIO_OTYPER_OT_7 0x00000080U
+#define GPIO_OTYPER_OT_8 0x00000100U
+#define GPIO_OTYPER_OT_9 0x00000200U
+#define GPIO_OTYPER_OT_10 0x00000400U
+#define GPIO_OTYPER_OT_11 0x00000800U
+#define GPIO_OTYPER_OT_12 0x00001000U
+#define GPIO_OTYPER_OT_13 0x00002000U
+#define GPIO_OTYPER_OT_14 0x00004000U
+#define GPIO_OTYPER_OT_15 0x00008000U
+
+/****************** Bits definition for GPIO_OSPEEDR register ***************/
+#define GPIO_OSPEEDER_OSPEEDR0 0x00000003U
+#define GPIO_OSPEEDER_OSPEEDR0_0 0x00000001U
+#define GPIO_OSPEEDER_OSPEEDR0_1 0x00000002U
+
+#define GPIO_OSPEEDER_OSPEEDR1 0x0000000CU
+#define GPIO_OSPEEDER_OSPEEDR1_0 0x00000004U
+#define GPIO_OSPEEDER_OSPEEDR1_1 0x00000008U
+
+#define GPIO_OSPEEDER_OSPEEDR2 0x00000030U
+#define GPIO_OSPEEDER_OSPEEDR2_0 0x00000010U
+#define GPIO_OSPEEDER_OSPEEDR2_1 0x00000020U
+
+#define GPIO_OSPEEDER_OSPEEDR3 0x000000C0U
+#define GPIO_OSPEEDER_OSPEEDR3_0 0x00000040U
+#define GPIO_OSPEEDER_OSPEEDR3_1 0x00000080U
+
+#define GPIO_OSPEEDER_OSPEEDR4 0x00000300U
+#define GPIO_OSPEEDER_OSPEEDR4_0 0x00000100U
+#define GPIO_OSPEEDER_OSPEEDR4_1 0x00000200U
+
+#define GPIO_OSPEEDER_OSPEEDR5 0x00000C00U
+#define GPIO_OSPEEDER_OSPEEDR5_0 0x00000400U
+#define GPIO_OSPEEDER_OSPEEDR5_1 0x00000800U
+
+#define GPIO_OSPEEDER_OSPEEDR6 0x00003000U
+#define GPIO_OSPEEDER_OSPEEDR6_0 0x00001000U
+#define GPIO_OSPEEDER_OSPEEDR6_1 0x00002000U
+
+#define GPIO_OSPEEDER_OSPEEDR7 0x0000C000U
+#define GPIO_OSPEEDER_OSPEEDR7_0 0x00004000U
+#define GPIO_OSPEEDER_OSPEEDR7_1 0x00008000U
+
+#define GPIO_OSPEEDER_OSPEEDR8 0x00030000U
+#define GPIO_OSPEEDER_OSPEEDR8_0 0x00010000U
+#define GPIO_OSPEEDER_OSPEEDR8_1 0x00020000U
+
+#define GPIO_OSPEEDER_OSPEEDR9 0x000C0000U
+#define GPIO_OSPEEDER_OSPEEDR9_0 0x00040000U
+#define GPIO_OSPEEDER_OSPEEDR9_1 0x00080000U
+
+#define GPIO_OSPEEDER_OSPEEDR10 0x00300000U
+#define GPIO_OSPEEDER_OSPEEDR10_0 0x00100000U
+#define GPIO_OSPEEDER_OSPEEDR10_1 0x00200000U
+
+#define GPIO_OSPEEDER_OSPEEDR11 0x00C00000U
+#define GPIO_OSPEEDER_OSPEEDR11_0 0x00400000U
+#define GPIO_OSPEEDER_OSPEEDR11_1 0x00800000U
+
+#define GPIO_OSPEEDER_OSPEEDR12 0x03000000U
+#define GPIO_OSPEEDER_OSPEEDR12_0 0x01000000U
+#define GPIO_OSPEEDER_OSPEEDR12_1 0x02000000U
+
+#define GPIO_OSPEEDER_OSPEEDR13 0x0C000000U
+#define GPIO_OSPEEDER_OSPEEDR13_0 0x04000000U
+#define GPIO_OSPEEDER_OSPEEDR13_1 0x08000000U
+
+#define GPIO_OSPEEDER_OSPEEDR14 0x30000000U
+#define GPIO_OSPEEDER_OSPEEDR14_0 0x10000000U
+#define GPIO_OSPEEDER_OSPEEDR14_1 0x20000000U
+
+#define GPIO_OSPEEDER_OSPEEDR15 0xC0000000U
+#define GPIO_OSPEEDER_OSPEEDR15_0 0x40000000U
+#define GPIO_OSPEEDER_OSPEEDR15_1 0x80000000U
+
+/****************** Bits definition for GPIO_PUPDR register *****************/
+#define GPIO_PUPDR_PUPDR0 0x00000003U
+#define GPIO_PUPDR_PUPDR0_0 0x00000001U
+#define GPIO_PUPDR_PUPDR0_1 0x00000002U
+
+#define GPIO_PUPDR_PUPDR1 0x0000000CU
+#define GPIO_PUPDR_PUPDR1_0 0x00000004U
+#define GPIO_PUPDR_PUPDR1_1 0x00000008U
+
+#define GPIO_PUPDR_PUPDR2 0x00000030U
+#define GPIO_PUPDR_PUPDR2_0 0x00000010U
+#define GPIO_PUPDR_PUPDR2_1 0x00000020U
+
+#define GPIO_PUPDR_PUPDR3 0x000000C0U
+#define GPIO_PUPDR_PUPDR3_0 0x00000040U
+#define GPIO_PUPDR_PUPDR3_1 0x00000080U
+
+#define GPIO_PUPDR_PUPDR4 0x00000300U
+#define GPIO_PUPDR_PUPDR4_0 0x00000100U
+#define GPIO_PUPDR_PUPDR4_1 0x00000200U
+
+#define GPIO_PUPDR_PUPDR5 0x00000C00U
+#define GPIO_PUPDR_PUPDR5_0 0x00000400U
+#define GPIO_PUPDR_PUPDR5_1 0x00000800U
+
+#define GPIO_PUPDR_PUPDR6 0x00003000U
+#define GPIO_PUPDR_PUPDR6_0 0x00001000U
+#define GPIO_PUPDR_PUPDR6_1 0x00002000U
+
+#define GPIO_PUPDR_PUPDR7 0x0000C000U
+#define GPIO_PUPDR_PUPDR7_0 0x00004000U
+#define GPIO_PUPDR_PUPDR7_1 0x00008000U
+
+#define GPIO_PUPDR_PUPDR8 0x00030000U
+#define GPIO_PUPDR_PUPDR8_0 0x00010000U
+#define GPIO_PUPDR_PUPDR8_1 0x00020000U
+
+#define GPIO_PUPDR_PUPDR9 0x000C0000U
+#define GPIO_PUPDR_PUPDR9_0 0x00040000U
+#define GPIO_PUPDR_PUPDR9_1 0x00080000U
+
+#define GPIO_PUPDR_PUPDR10 0x00300000U
+#define GPIO_PUPDR_PUPDR10_0 0x00100000U
+#define GPIO_PUPDR_PUPDR10_1 0x00200000U
+
+#define GPIO_PUPDR_PUPDR11 0x00C00000U
+#define GPIO_PUPDR_PUPDR11_0 0x00400000U
+#define GPIO_PUPDR_PUPDR11_1 0x00800000U
+
+#define GPIO_PUPDR_PUPDR12 0x03000000U
+#define GPIO_PUPDR_PUPDR12_0 0x01000000U
+#define GPIO_PUPDR_PUPDR12_1 0x02000000U
+
+#define GPIO_PUPDR_PUPDR13 0x0C000000U
+#define GPIO_PUPDR_PUPDR13_0 0x04000000U
+#define GPIO_PUPDR_PUPDR13_1 0x08000000U
+
+#define GPIO_PUPDR_PUPDR14 0x30000000U
+#define GPIO_PUPDR_PUPDR14_0 0x10000000U
+#define GPIO_PUPDR_PUPDR14_1 0x20000000U
+
+#define GPIO_PUPDR_PUPDR15 0xC0000000U
+#define GPIO_PUPDR_PUPDR15_0 0x40000000U
+#define GPIO_PUPDR_PUPDR15_1 0x80000000U
+
+/****************** Bits definition for GPIO_IDR register *******************/
+#define GPIO_IDR_IDR_0 0x00000001U
+#define GPIO_IDR_IDR_1 0x00000002U
+#define GPIO_IDR_IDR_2 0x00000004U
+#define GPIO_IDR_IDR_3 0x00000008U
+#define GPIO_IDR_IDR_4 0x00000010U
+#define GPIO_IDR_IDR_5 0x00000020U
+#define GPIO_IDR_IDR_6 0x00000040U
+#define GPIO_IDR_IDR_7 0x00000080U
+#define GPIO_IDR_IDR_8 0x00000100U
+#define GPIO_IDR_IDR_9 0x00000200U
+#define GPIO_IDR_IDR_10 0x00000400U
+#define GPIO_IDR_IDR_11 0x00000800U
+#define GPIO_IDR_IDR_12 0x00001000U
+#define GPIO_IDR_IDR_13 0x00002000U
+#define GPIO_IDR_IDR_14 0x00004000U
+#define GPIO_IDR_IDR_15 0x00008000U
+
+/****************** Bits definition for GPIO_ODR register *******************/
+#define GPIO_ODR_ODR_0 0x00000001U
+#define GPIO_ODR_ODR_1 0x00000002U
+#define GPIO_ODR_ODR_2 0x00000004U
+#define GPIO_ODR_ODR_3 0x00000008U
+#define GPIO_ODR_ODR_4 0x00000010U
+#define GPIO_ODR_ODR_5 0x00000020U
+#define GPIO_ODR_ODR_6 0x00000040U
+#define GPIO_ODR_ODR_7 0x00000080U
+#define GPIO_ODR_ODR_8 0x00000100U
+#define GPIO_ODR_ODR_9 0x00000200U
+#define GPIO_ODR_ODR_10 0x00000400U
+#define GPIO_ODR_ODR_11 0x00000800U
+#define GPIO_ODR_ODR_12 0x00001000U
+#define GPIO_ODR_ODR_13 0x00002000U
+#define GPIO_ODR_ODR_14 0x00004000U
+#define GPIO_ODR_ODR_15 0x00008000U
+
+/****************** Bits definition for GPIO_BSRR register ******************/
+#define GPIO_BSRR_BS_0 0x00000001U
+#define GPIO_BSRR_BS_1 0x00000002U
+#define GPIO_BSRR_BS_2 0x00000004U
+#define GPIO_BSRR_BS_3 0x00000008U
+#define GPIO_BSRR_BS_4 0x00000010U
+#define GPIO_BSRR_BS_5 0x00000020U
+#define GPIO_BSRR_BS_6 0x00000040U
+#define GPIO_BSRR_BS_7 0x00000080U
+#define GPIO_BSRR_BS_8 0x00000100U
+#define GPIO_BSRR_BS_9 0x00000200U
+#define GPIO_BSRR_BS_10 0x00000400U
+#define GPIO_BSRR_BS_11 0x00000800U
+#define GPIO_BSRR_BS_12 0x00001000U
+#define GPIO_BSRR_BS_13 0x00002000U
+#define GPIO_BSRR_BS_14 0x00004000U
+#define GPIO_BSRR_BS_15 0x00008000U
+#define GPIO_BSRR_BR_0 0x00010000U
+#define GPIO_BSRR_BR_1 0x00020000U
+#define GPIO_BSRR_BR_2 0x00040000U
+#define GPIO_BSRR_BR_3 0x00080000U
+#define GPIO_BSRR_BR_4 0x00100000U
+#define GPIO_BSRR_BR_5 0x00200000U
+#define GPIO_BSRR_BR_6 0x00400000U
+#define GPIO_BSRR_BR_7 0x00800000U
+#define GPIO_BSRR_BR_8 0x01000000U
+#define GPIO_BSRR_BR_9 0x02000000U
+#define GPIO_BSRR_BR_10 0x04000000U
+#define GPIO_BSRR_BR_11 0x08000000U
+#define GPIO_BSRR_BR_12 0x10000000U
+#define GPIO_BSRR_BR_13 0x20000000U
+#define GPIO_BSRR_BR_14 0x40000000U
+#define GPIO_BSRR_BR_15 0x80000000U
+
+/****************** Bit definition for GPIO_LCKR register *********************/
+#define GPIO_LCKR_LCK0 0x00000001U
+#define GPIO_LCKR_LCK1 0x00000002U
+#define GPIO_LCKR_LCK2 0x00000004U
+#define GPIO_LCKR_LCK3 0x00000008U
+#define GPIO_LCKR_LCK4 0x00000010U
+#define GPIO_LCKR_LCK5 0x00000020U
+#define GPIO_LCKR_LCK6 0x00000040U
+#define GPIO_LCKR_LCK7 0x00000080U
+#define GPIO_LCKR_LCK8 0x00000100U
+#define GPIO_LCKR_LCK9 0x00000200U
+#define GPIO_LCKR_LCK10 0x00000400U
+#define GPIO_LCKR_LCK11 0x00000800U
+#define GPIO_LCKR_LCK12 0x00001000U
+#define GPIO_LCKR_LCK13 0x00002000U
+#define GPIO_LCKR_LCK14 0x00004000U
+#define GPIO_LCKR_LCK15 0x00008000U
+#define GPIO_LCKR_LCKK 0x00010000U
+
+/******************************************************************************/
+/* */
+/* Inter-integrated Circuit Interface */
+/* */
+/******************************************************************************/
+/******************* Bit definition for I2C_CR1 register ********************/
+#define I2C_CR1_PE 0x00000001U /*!<Peripheral Enable */
+#define I2C_CR1_SMBUS 0x00000002U /*!<SMBus Mode */
+#define I2C_CR1_SMBTYPE 0x00000008U /*!<SMBus Type */
+#define I2C_CR1_ENARP 0x00000010U /*!<ARP Enable */
+#define I2C_CR1_ENPEC 0x00000020U /*!<PEC Enable */
+#define I2C_CR1_ENGC 0x00000040U /*!<General Call Enable */
+#define I2C_CR1_NOSTRETCH 0x00000080U /*!<Clock Stretching Disable (Slave mode) */
+#define I2C_CR1_START 0x00000100U /*!<Start Generation */
+#define I2C_CR1_STOP 0x00000200U /*!<Stop Generation */
+#define I2C_CR1_ACK 0x00000400U /*!<Acknowledge Enable */
+#define I2C_CR1_POS 0x00000800U /*!<Acknowledge/PEC Position (for data reception) */
+#define I2C_CR1_PEC 0x00001000U /*!<Packet Error Checking */
+#define I2C_CR1_ALERT 0x00002000U /*!<SMBus Alert */
+#define I2C_CR1_SWRST 0x00008000U /*!<Software Reset */
+
+/******************* Bit definition for I2C_CR2 register ********************/
+#define I2C_CR2_FREQ 0x0000003FU /*!<FREQ[5:0] bits (Peripheral Clock Frequency) */
+#define I2C_CR2_FREQ_0 0x00000001U /*!<Bit 0 */
+#define I2C_CR2_FREQ_1 0x00000002U /*!<Bit 1 */
+#define I2C_CR2_FREQ_2 0x00000004U /*!<Bit 2 */
+#define I2C_CR2_FREQ_3 0x00000008U /*!<Bit 3 */
+#define I2C_CR2_FREQ_4 0x00000010U /*!<Bit 4 */
+#define I2C_CR2_FREQ_5 0x00000020U /*!<Bit 5 */
+
+#define I2C_CR2_ITERREN 0x00000100U /*!<Error Interrupt Enable */
+#define I2C_CR2_ITEVTEN 0x00000200U /*!<Event Interrupt Enable */
+#define I2C_CR2_ITBUFEN 0x00000400U /*!<Buffer Interrupt Enable */
+#define I2C_CR2_DMAEN 0x00000800U /*!<DMA Requests Enable */
+#define I2C_CR2_LAST 0x00001000U /*!<DMA Last Transfer */
+
+/******************* Bit definition for I2C_OAR1 register *******************/
+#define I2C_OAR1_ADD1_7 0x000000FEU /*!<Interface Address */
+#define I2C_OAR1_ADD8_9 0x00000300U /*!<Interface Address */
+
+#define I2C_OAR1_ADD0 0x00000001U /*!<Bit 0 */
+#define I2C_OAR1_ADD1 0x00000002U /*!<Bit 1 */
+#define I2C_OAR1_ADD2 0x00000004U /*!<Bit 2 */
+#define I2C_OAR1_ADD3 0x00000008U /*!<Bit 3 */
+#define I2C_OAR1_ADD4 0x00000010U /*!<Bit 4 */
+#define I2C_OAR1_ADD5 0x00000020U /*!<Bit 5 */
+#define I2C_OAR1_ADD6 0x00000040U /*!<Bit 6 */
+#define I2C_OAR1_ADD7 0x00000080U /*!<Bit 7 */
+#define I2C_OAR1_ADD8 0x00000100U /*!<Bit 8 */
+#define I2C_OAR1_ADD9 0x00000200U /*!<Bit 9 */
+
+#define I2C_OAR1_ADDMODE 0x00008000U /*!<Addressing Mode (Slave mode) */
+
+/******************* Bit definition for I2C_OAR2 register *******************/
+#define I2C_OAR2_ENDUAL 0x00000001U /*!<Dual addressing mode enable */
+#define I2C_OAR2_ADD2 0x000000FEU /*!<Interface address */
+
+/******************** Bit definition for I2C_DR register ********************/
+#define I2C_DR_DR 0x000000FFU /*!<8-bit Data Register */
+
+/******************* Bit definition for I2C_SR1 register ********************/
+#define I2C_SR1_SB 0x00000001U /*!<Start Bit (Master mode) */
+#define I2C_SR1_ADDR 0x00000002U /*!<Address sent (master mode)/matched (slave mode) */
+#define I2C_SR1_BTF 0x00000004U /*!<Byte Transfer Finished */
+#define I2C_SR1_ADD10 0x00000008U /*!<10-bit header sent (Master mode) */
+#define I2C_SR1_STOPF 0x00000010U /*!<Stop detection (Slave mode) */
+#define I2C_SR1_RXNE 0x00000040U /*!<Data Register not Empty (receivers) */
+#define I2C_SR1_TXE 0x00000080U /*!<Data Register Empty (transmitters) */
+#define I2C_SR1_BERR 0x00000100U /*!<Bus Error */
+#define I2C_SR1_ARLO 0x00000200U /*!<Arbitration Lost (master mode) */
+#define I2C_SR1_AF 0x00000400U /*!<Acknowledge Failure */
+#define I2C_SR1_OVR 0x00000800U /*!<Overrun/Underrun */
+#define I2C_SR1_PECERR 0x00001000U /*!<PEC Error in reception */
+#define I2C_SR1_TIMEOUT 0x00004000U /*!<Timeout or Tlow Error */
+#define I2C_SR1_SMBALERT 0x00008000U /*!<SMBus Alert */
+
+/******************* Bit definition for I2C_SR2 register ********************/
+#define I2C_SR2_MSL 0x00000001U /*!<Master/Slave */
+#define I2C_SR2_BUSY 0x00000002U /*!<Bus Busy */
+#define I2C_SR2_TRA 0x00000004U /*!<Transmitter/Receiver */
+#define I2C_SR2_GENCALL 0x00000010U /*!<General Call Address (Slave mode) */
+#define I2C_SR2_SMBDEFAULT 0x00000020U /*!<SMBus Device Default Address (Slave mode) */
+#define I2C_SR2_SMBHOST 0x00000040U /*!<SMBus Host Header (Slave mode) */
+#define I2C_SR2_DUALF 0x00000080U /*!<Dual Flag (Slave mode) */
+#define I2C_SR2_PEC 0x0000FF00U /*!<Packet Error Checking Register */
+
+/******************* Bit definition for I2C_CCR register ********************/
+#define I2C_CCR_CCR 0x00000FFFU /*!<Clock Control Register in Fast/Standard mode (Master mode) */
+#define I2C_CCR_DUTY 0x00004000U /*!<Fast Mode Duty Cycle */
+#define I2C_CCR_FS 0x00008000U /*!<I2C Master Mode Selection */
+
+/****************** Bit definition for I2C_TRISE register *******************/
+#define I2C_TRISE_TRISE 0x0000003FU /*!<Maximum Rise Time in Fast/Standard mode (Master mode) */
+
+/****************** Bit definition for I2C_FLTR register *******************/
+#define I2C_FLTR_DNF 0x0000000FU /*!<Digital Noise Filter */
+#define I2C_FLTR_ANOFF 0x00000010U /*!<Analog Noise Filter OFF */
+
+/******************************************************************************/
+/* */
+/* Fast Mode Plus Inter-integrated Circuit Interface (I2C) */
+/* */
+/******************************************************************************/
+/******************* Bit definition for I2C_CR1 register *******************/
+#define FMPI2C_CR1_PE 0x00000001U /*!< Peripheral enable */
+#define FMPI2C_CR1_TXIE 0x00000002U /*!< TX interrupt enable */
+#define FMPI2C_CR1_RXIE 0x00000004U /*!< RX interrupt enable */
+#define FMPI2C_CR1_ADDRIE 0x00000008U /*!< Address match interrupt enable */
+#define FMPI2C_CR1_NACKIE 0x00000010U /*!< NACK received interrupt enable */
+#define FMPI2C_CR1_STOPIE 0x00000020U /*!< STOP detection interrupt enable */
+#define FMPI2C_CR1_TCIE 0x00000040U /*!< Transfer complete interrupt enable */
+#define FMPI2C_CR1_ERRIE 0x00000080U /*!< Errors interrupt enable */
+#define FMPI2C_CR1_DFN 0x00000F00U /*!< Digital noise filter */
+#define FMPI2C_CR1_ANFOFF 0x00001000U /*!< Analog noise filter OFF */
+#define FMPI2C_CR1_TXDMAEN 0x00004000U /*!< DMA transmission requests enable */
+#define FMPI2C_CR1_RXDMAEN 0x00008000U /*!< DMA reception requests enable */
+#define FMPI2C_CR1_SBC 0x00010000U /*!< Slave byte control */
+#define FMPI2C_CR1_NOSTRETCH 0x00020000U /*!< Clock stretching disable */
+#define FMPI2C_CR1_GCEN 0x00080000U /*!< General call enable */
+#define FMPI2C_CR1_SMBHEN 0x00100000U /*!< SMBus host address enable */
+#define FMPI2C_CR1_SMBDEN 0x00200000U /*!< SMBus device default address enable */
+#define FMPI2C_CR1_ALERTEN 0x00400000U /*!< SMBus alert enable */
+#define FMPI2C_CR1_PECEN 0x00800000U /*!< PEC enable */
+
+/****************** Bit definition for I2C_CR2 register ********************/
+#define FMPI2C_CR2_SADD 0x000003FFU /*!< Slave address (master mode) */
+#define FMPI2C_CR2_RD_WRN 0x00000400U /*!< Transfer direction (master mode) */
+#define FMPI2C_CR2_ADD10 0x00000800U /*!< 10-bit addressing mode (master mode) */
+#define FMPI2C_CR2_HEAD10R 0x00001000U /*!< 10-bit address header only read direction (master mode) */
+#define FMPI2C_CR2_START 0x00002000U /*!< START generation */
+#define FMPI2C_CR2_STOP 0x00004000U /*!< STOP generation (master mode) */
+#define FMPI2C_CR2_NACK 0x00008000U /*!< NACK generation (slave mode) */
+#define FMPI2C_CR2_NBYTES 0x00FF0000U /*!< Number of bytes */
+#define FMPI2C_CR2_RELOAD 0x01000000U /*!< NBYTES reload mode */
+#define FMPI2C_CR2_AUTOEND 0x02000000U /*!< Automatic end mode (master mode) */
+#define FMPI2C_CR2_PECBYTE 0x04000000U /*!< Packet error checking byte */
+
+/******************* Bit definition for I2C_OAR1 register ******************/
+#define FMPI2C_OAR1_OA1 0x000003FFU /*!< Interface own address 1 */
+#define FMPI2C_OAR1_OA1MODE 0x00000400U /*!< Own address 1 10-bit mode */
+#define FMPI2C_OAR1_OA1EN 0x00008000U /*!< Own address 1 enable */
+
+/******************* Bit definition for I2C_OAR2 register ******************/
+#define FMPI2C_OAR2_OA2 0x000000FEU /*!< Interface own address 2 */
+#define FMPI2C_OAR2_OA2MSK 0x00000700U /*!< Own address 2 masks */
+#define FMPI2C_OAR2_OA2EN 0x00008000U /*!< Own address 2 enable */
+
+/******************* Bit definition for I2C_TIMINGR register *******************/
+#define FMPI2C_TIMINGR_SCLL 0x000000FFU /*!< SCL low period (master mode) */
+#define FMPI2C_TIMINGR_SCLH 0x0000FF00U /*!< SCL high period (master mode) */
+#define FMPI2C_TIMINGR_SDADEL 0x000F0000U /*!< Data hold time */
+#define FMPI2C_TIMINGR_SCLDEL 0x00F00000U /*!< Data setup time */
+#define FMPI2C_TIMINGR_PRESC 0xF0000000U /*!< Timings prescaler */
+
+/******************* Bit definition for I2C_TIMEOUTR register *******************/
+#define FMPI2C_TIMEOUTR_TIMEOUTA 0x00000FFFU /*!< Bus timeout A */
+#define FMPI2C_TIMEOUTR_TIDLE 0x00001000U /*!< Idle clock timeout detection */
+#define FMPI2C_TIMEOUTR_TIMOUTEN 0x00008000U /*!< Clock timeout enable */
+#define FMPI2C_TIMEOUTR_TIMEOUTB 0x0FFF0000U /*!< Bus timeout B */
+#define FMPI2C_TIMEOUTR_TEXTEN 0x80000000U /*!< Extended clock timeout enable */
+
+/****************** Bit definition for I2C_ISR register *********************/
+#define FMPI2C_ISR_TXE 0x00000001U /*!< Transmit data register empty */
+#define FMPI2C_ISR_TXIS 0x00000002U /*!< Transmit interrupt status */
+#define FMPI2C_ISR_RXNE 0x00000004U /*!< Receive data register not empty */
+#define FMPI2C_ISR_ADDR 0x00000008U /*!< Address matched (slave mode) */
+#define FMPI2C_ISR_NACKF 0x00000010U /*!< NACK received flag */
+#define FMPI2C_ISR_STOPF 0x00000020U /*!< STOP detection flag */
+#define FMPI2C_ISR_TC 0x00000040U /*!< Transfer complete (master mode) */
+#define FMPI2C_ISR_TCR 0x00000080U /*!< Transfer complete reload */
+#define FMPI2C_ISR_BERR 0x00000100U /*!< Bus error */
+#define FMPI2C_ISR_ARLO 0x00000200U /*!< Arbitration lost */
+#define FMPI2C_ISR_OVR 0x00000400U /*!< Overrun/Underrun */
+#define FMPI2C_ISR_PECERR 0x00000800U /*!< PEC error in reception */
+#define FMPI2C_ISR_TIMEOUT 0x00001000U /*!< Timeout or Tlow detection flag */
+#define FMPI2C_ISR_ALERT 0x00002000U /*!< SMBus alert */
+#define FMPI2C_ISR_BUSY 0x00008000U /*!< Bus busy */
+#define FMPI2C_ISR_DIR 0x00010000U /*!< Transfer direction (slave mode) */
+#define FMPI2C_ISR_ADDCODE 0x00FE0000U /*!< Address match code (slave mode) */
+
+/****************** Bit definition for I2C_ICR register *********************/
+#define FMPI2C_ICR_ADDRCF 0x00000008U /*!< Address matched clear flag */
+#define FMPI2C_ICR_NACKCF 0x00000010U /*!< NACK clear flag */
+#define FMPI2C_ICR_STOPCF 0x00000020U /*!< STOP detection clear flag */
+#define FMPI2C_ICR_BERRCF 0x00000100U /*!< Bus error clear flag */
+#define FMPI2C_ICR_ARLOCF 0x00000200U /*!< Arbitration lost clear flag */
+#define FMPI2C_ICR_OVRCF 0x00000400U /*!< Overrun/Underrun clear flag */
+#define FMPI2C_ICR_PECCF 0x00000800U /*!< PAC error clear flag */
+#define FMPI2C_ICR_TIMOUTCF 0x00001000U /*!< Timeout clear flag */
+#define FMPI2C_ICR_ALERTCF 0x00002000U /*!< Alert clear flag */
+
+/****************** Bit definition for I2C_PECR register *********************/
+#define FMPI2C_PECR_PEC 0x000000FFU /*!< PEC register */
+
+/****************** Bit definition for I2C_RXDR register *********************/
+#define FMPI2C_RXDR_RXDATA 0x000000FFU /*!< 8-bit receive data */
+
+/****************** Bit definition for I2C_TXDR register *********************/
+#define FMPI2C_TXDR_TXDATA 0x000000FFU /*!< 8-bit transmit data */
+
+/******************************************************************************/
+/* */
+/* Independent WATCHDOG */
+/* */
+/******************************************************************************/
+/******************* Bit definition for IWDG_KR register ********************/
+#define IWDG_KR_KEY 0xFFFFU /*!<Key value (write only, read 0000h) */
+
+/******************* Bit definition for IWDG_PR register ********************/
+#define IWDG_PR_PR 0x07U /*!<PR[2:0] (Prescaler divider) */
+#define IWDG_PR_PR_0 0x01U /*!<Bit 0 */
+#define IWDG_PR_PR_1 0x02U /*!<Bit 1 */
+#define IWDG_PR_PR_2 0x04U /*!<Bit 2 */
+
+/******************* Bit definition for IWDG_RLR register *******************/
+#define IWDG_RLR_RL 0x0FFFU /*!<Watchdog counter reload value */
+
+/******************* Bit definition for IWDG_SR register ********************/
+#define IWDG_SR_PVU 0x01U /*!<Watchdog prescaler value update */
+#define IWDG_SR_RVU 0x02U /*!<Watchdog counter reload value update */
+
+
+/******************************************************************************/
+/* */
+/* Power Control */
+/* */
+/******************************************************************************/
+/******************** Bit definition for PWR_CR register ********************/
+#define PWR_CR_LPDS 0x00000001U /*!< Low-Power Deepsleep */
+#define PWR_CR_PDDS 0x00000002U /*!< Power Down Deepsleep */
+#define PWR_CR_CWUF 0x00000004U /*!< Clear Wakeup Flag */
+#define PWR_CR_CSBF 0x00000008U /*!< Clear Standby Flag */
+#define PWR_CR_PVDE 0x00000010U /*!< Power Voltage Detector Enable */
+
+#define PWR_CR_PLS 0x000000E0U /*!< PLS[2:0] bits (PVD Level Selection) */
+#define PWR_CR_PLS_0 0x00000020U /*!< Bit 0 */
+#define PWR_CR_PLS_1 0x00000040U /*!< Bit 1 */
+#define PWR_CR_PLS_2 0x00000080U /*!< Bit 2 */
+
+/*!< PVD level configuration */
+#define PWR_CR_PLS_LEV0 0x00000000U /*!< PVD level 0 */
+#define PWR_CR_PLS_LEV1 0x00000020U /*!< PVD level 1 */
+#define PWR_CR_PLS_LEV2 0x00000040U /*!< PVD level 2 */
+#define PWR_CR_PLS_LEV3 0x00000060U /*!< PVD level 3 */
+#define PWR_CR_PLS_LEV4 0x00000080U /*!< PVD level 4 */
+#define PWR_CR_PLS_LEV5 0x000000A0U /*!< PVD level 5 */
+#define PWR_CR_PLS_LEV6 0x000000C0U /*!< PVD level 6 */
+#define PWR_CR_PLS_LEV7 0x000000E0U /*!< PVD level 7 */
+
+#define PWR_CR_DBP 0x00000100U /*!< Disable Backup Domain write protection */
+#define PWR_CR_FPDS 0x00000200U /*!< Flash power down in Stop mode */
+#define PWR_CR_LPLVDS 0x00000400U /*!< Low Power Regulator Low Voltage in Deep Sleep mode */
+#define PWR_CR_MRLVDS 0x00000800U /*!< Main Regulator Low Voltage in Deep Sleep mode */
+#define PWR_CR_ADCDC1 0x00002000U /*!< Refer to AN4073 on how to use this bit */
+
+#define PWR_CR_VOS 0x0000C000U /*!< VOS[1:0] bits (Regulator voltage scaling output selection) */
+#define PWR_CR_VOS_0 0x00004000U /*!< Bit 0 */
+#define PWR_CR_VOS_1 0x00008000U /*!< Bit 1 */
+
+#define PWR_CR_FMSSR 0x00100000U /*!< Flash Memory Sleep System Run */
+#define PWR_CR_FISSR 0x00200000U /*!< Flash Interface Stop while System Run */
+
+/******************* Bit definition for PWR_CSR register ********************/
+#define PWR_CSR_WUF 0x00000001U /*!< Wakeup Flag */
+#define PWR_CSR_SBF 0x00000002U /*!< Standby Flag */
+#define PWR_CSR_PVDO 0x00000004U /*!< PVD Output */
+#define PWR_CSR_BRR 0x00000008U /*!< Backup regulator ready */
+#define PWR_CSR_EWUP 0x00000100U /*!< Enable WKUP pin */
+#define PWR_CSR_BRE 0x00000200U /*!< Backup regulator enable */
+#define PWR_CSR_VOSRDY 0x00004000U /*!< Regulator voltage scaling output selection ready */
+/******************************************************************************/
+/* */
+/* QUADSPI */
+/* */
+/******************************************************************************/
+/***************** Bit definition for QUADSPI_CR register *******************/
+#define QUADSPI_CR_EN 0x00000001U /*!< Enable */
+#define QUADSPI_CR_ABORT 0x00000002U /*!< Abort request */
+#define QUADSPI_CR_DMAEN 0x00000004U /*!< DMA Enable */
+#define QUADSPI_CR_TCEN 0x00000008U /*!< Timeout Counter Enable */
+#define QUADSPI_CR_SSHIFT 0x00000010U /*!< SSHIFT Sample Shift */
+#define QUADSPI_CR_DFM 0x00000040U /*!< Dual Flash Mode */
+#define QUADSPI_CR_FSEL 0x00000080U /*!< Flash Select */
+#define QUADSPI_CR_FTHRES 0x00001F00U /*!< FTHRES[3:0] FIFO Level */
+#define QUADSPI_CR_FTHRES_0 0x00000100U /*!< Bit 0 */
+#define QUADSPI_CR_FTHRES_1 0x00000200U /*!< Bit 1 */
+#define QUADSPI_CR_FTHRES_2 0x00000400U /*!< Bit 2 */
+#define QUADSPI_CR_FTHRES_3 0x00000800U /*!< Bit 3 */
+#define QUADSPI_CR_FTHRES_4 0x00001000U /*!< Bit 4 */
+#define QUADSPI_CR_TEIE 0x00010000U /*!< Transfer Error Interrupt Enable */
+#define QUADSPI_CR_TCIE 0x00020000U /*!< Transfer Complete Interrupt Enable */
+#define QUADSPI_CR_FTIE 0x00040000U /*!< FIFO Threshold Interrupt Enable */
+#define QUADSPI_CR_SMIE 0x00080000U /*!< Status Match Interrupt Enable */
+#define QUADSPI_CR_TOIE 0x00100000U /*!< TimeOut Interrupt Enable */
+#define QUADSPI_CR_APMS 0x00400000U /*!< Bit 1 */
+#define QUADSPI_CR_PMM 0x00800000U /*!< Polling Match Mode */
+#define QUADSPI_CR_PRESCALER 0xFF000000U /*!< PRESCALER[7:0] Clock prescaler */
+#define QUADSPI_CR_PRESCALER_0 0x01000000U /*!< Bit 0 */
+#define QUADSPI_CR_PRESCALER_1 0x02000000U /*!< Bit 1 */
+#define QUADSPI_CR_PRESCALER_2 0x04000000U /*!< Bit 2 */
+#define QUADSPI_CR_PRESCALER_3 0x08000000U /*!< Bit 3 */
+#define QUADSPI_CR_PRESCALER_4 0x10000000U /*!< Bit 4 */
+#define QUADSPI_CR_PRESCALER_5 0x20000000U /*!< Bit 5 */
+#define QUADSPI_CR_PRESCALER_6 0x40000000U /*!< Bit 6 */
+#define QUADSPI_CR_PRESCALER_7 0x80000000U /*!< Bit 7 */
+
+/***************** Bit definition for QUADSPI_DCR register ******************/
+#define QUADSPI_DCR_CKMODE 0x00000001U /*!< Mode 0 / Mode 3 */
+#define QUADSPI_DCR_CSHT 0x00000700U /*!< CSHT[2:0]: ChipSelect High Time */
+#define QUADSPI_DCR_CSHT_0 0x00000100U /*!< Bit 0 */
+#define QUADSPI_DCR_CSHT_1 0x00000200U /*!< Bit 1 */
+#define QUADSPI_DCR_CSHT_2 0x00000400U /*!< Bit 2 */
+#define QUADSPI_DCR_FSIZE 0x001F0000U /*!< FSIZE[4:0]: Flash Size */
+#define QUADSPI_DCR_FSIZE_0 0x00010000U /*!< Bit 0 */
+#define QUADSPI_DCR_FSIZE_1 0x00020000U /*!< Bit 1 */
+#define QUADSPI_DCR_FSIZE_2 0x00040000U /*!< Bit 2 */
+#define QUADSPI_DCR_FSIZE_3 0x00080000U /*!< Bit 3 */
+#define QUADSPI_DCR_FSIZE_4 0x00100000U /*!< Bit 4 */
+
+/****************** Bit definition for QUADSPI_SR register *******************/
+#define QUADSPI_SR_TEF 0x00000001U /*!< Transfer Error Flag */
+#define QUADSPI_SR_TCF 0x00000002U /*!< Transfer Complete Flag */
+#define QUADSPI_SR_FTF 0x00000004U /*!< FIFO Threshlod Flag */
+#define QUADSPI_SR_SMF 0x00000008U /*!< Status Match Flag */
+#define QUADSPI_SR_TOF 0x00000010U /*!< Timeout Flag */
+#define QUADSPI_SR_BUSY 0x00000020U /*!< Busy */
+#define QUADSPI_SR_FLEVEL 0x00003F00U /*!< FIFO Threshlod Flag */
+#define QUADSPI_SR_FLEVEL_0 0x00000100U /*!< Bit 0 */
+#define QUADSPI_SR_FLEVEL_1 0x00000200U /*!< Bit 1 */
+#define QUADSPI_SR_FLEVEL_2 0x00000400U /*!< Bit 2 */
+#define QUADSPI_SR_FLEVEL_3 0x00000800U /*!< Bit 3 */
+#define QUADSPI_SR_FLEVEL_4 0x00001000U /*!< Bit 4 */
+#define QUADSPI_SR_FLEVEL_5 0x00002000U /*!< Bit 5 */
+
+/****************** Bit definition for QUADSPI_FCR register ******************/
+#define QUADSPI_FCR_CTEF 0x00000001U /*!< Clear Transfer Error Flag */
+#define QUADSPI_FCR_CTCF 0x00000002U /*!< Clear Transfer Complete Flag */
+#define QUADSPI_FCR_CSMF 0x00000008U /*!< Clear Status Match Flag */
+#define QUADSPI_FCR_CTOF 0x00000010U /*!< Clear Timeout Flag */
+
+/****************** Bit definition for QUADSPI_DLR register ******************/
+#define QUADSPI_DLR_DL 0xFFFFFFFFU /*!< DL[31:0]: Data Length */
+
+/****************** Bit definition for QUADSPI_CCR register ******************/
+#define QUADSPI_CCR_INSTRUCTION 0x000000FFU /*!< INSTRUCTION[7:0]: Instruction */
+#define QUADSPI_CCR_INSTRUCTION_0 0x00000001U /*!< Bit 0 */
+#define QUADSPI_CCR_INSTRUCTION_1 0x00000002U /*!< Bit 1 */
+#define QUADSPI_CCR_INSTRUCTION_2 0x00000004U /*!< Bit 2 */
+#define QUADSPI_CCR_INSTRUCTION_3 0x00000008U /*!< Bit 3 */
+#define QUADSPI_CCR_INSTRUCTION_4 0x00000010U /*!< Bit 4 */
+#define QUADSPI_CCR_INSTRUCTION_5 0x00000020U /*!< Bit 5 */
+#define QUADSPI_CCR_INSTRUCTION_6 0x00000040U /*!< Bit 6 */
+#define QUADSPI_CCR_INSTRUCTION_7 0x00000080U /*!< Bit 7 */
+#define QUADSPI_CCR_IMODE 0x00000300U /*!< IMODE[1:0]: Instruction Mode */
+#define QUADSPI_CCR_IMODE_0 0x00000100U /*!< Bit 0 */
+#define QUADSPI_CCR_IMODE_1 0x00000200U /*!< Bit 1 */
+#define QUADSPI_CCR_ADMODE 0x00000C00U /*!< ADMODE[1:0]: Address Mode */
+#define QUADSPI_CCR_ADMODE_0 0x00000400U /*!< Bit 0 */
+#define QUADSPI_CCR_ADMODE_1 0x00000800U /*!< Bit 1 */
+#define QUADSPI_CCR_ADSIZE 0x00003000U /*!< ADSIZE[1:0]: Address Size */
+#define QUADSPI_CCR_ADSIZE_0 0x00001000U /*!< Bit 0 */
+#define QUADSPI_CCR_ADSIZE_1 0x00002000U /*!< Bit 1 */
+#define QUADSPI_CCR_ABMODE 0x0000C000U /*!< ABMODE[1:0]: Alternate Bytes Mode */
+#define QUADSPI_CCR_ABMODE_0 0x00004000U /*!< Bit 0 */
+#define QUADSPI_CCR_ABMODE_1 0x00008000U /*!< Bit 1 */
+#define QUADSPI_CCR_ABSIZE 0x00030000U /*!< ABSIZE[1:0]: Instruction Mode */
+#define QUADSPI_CCR_ABSIZE_0 0x00010000U /*!< Bit 0 */
+#define QUADSPI_CCR_ABSIZE_1 0x00020000U /*!< Bit 1 */
+#define QUADSPI_CCR_DCYC 0x007C0000U /*!< DCYC[4:0]: Dummy Cycles */
+#define QUADSPI_CCR_DCYC_0 0x00040000U /*!< Bit 0 */
+#define QUADSPI_CCR_DCYC_1 0x00080000U /*!< Bit 1 */
+#define QUADSPI_CCR_DCYC_2 0x00100000U /*!< Bit 2 */
+#define QUADSPI_CCR_DCYC_3 0x00200000U /*!< Bit 3 */
+#define QUADSPI_CCR_DCYC_4 0x00400000U /*!< Bit 4 */
+#define QUADSPI_CCR_DMODE 0x03000000U /*!< DMODE[1:0]: Data Mode */
+#define QUADSPI_CCR_DMODE_0 0x01000000U /*!< Bit 0 */
+#define QUADSPI_CCR_DMODE_1 0x02000000U /*!< Bit 1 */
+#define QUADSPI_CCR_FMODE 0x0C000000U /*!< FMODE[1:0]: Functional Mode */
+#define QUADSPI_CCR_FMODE_0 0x04000000U /*!< Bit 0 */
+#define QUADSPI_CCR_FMODE_1 0x08000000U /*!< Bit 1 */
+#define QUADSPI_CCR_SIOO 0x10000000U /*!< SIOO: Send Instruction Only Once Mode */
+#define QUADSPI_CCR_DHHC 0x40000000U /*!< DHHC: Delay Half Hclk Cycle */
+#define QUADSPI_CCR_DDRM 0x80000000U /*!< DDRM: Double Data Rate Mode */
+/****************** Bit definition for QUADSPI_AR register *******************/
+#define QUADSPI_AR_ADDRESS 0xFFFFFFFFU /*!< ADDRESS[31:0]: Address */
+
+/****************** Bit definition for QUADSPI_ABR register ******************/
+#define QUADSPI_ABR_ALTERNATE 0xFFFFFFFFU /*!< ALTERNATE[31:0]: Alternate Bytes */
+
+/****************** Bit definition for QUADSPI_DR register *******************/
+#define QUADSPI_DR_DATA 0xFFFFFFFFU /*!< DATA[31:0]: Data */
+
+/****************** Bit definition for QUADSPI_PSMKR register ****************/
+#define QUADSPI_PSMKR_MASK 0xFFFFFFFFU /*!< MASK[31:0]: Status Mask */
+
+/****************** Bit definition for QUADSPI_PSMAR register ****************/
+#define QUADSPI_PSMAR_MATCH 0xFFFFFFFFU /*!< MATCH[31:0]: Status Match */
+
+/****************** Bit definition for QUADSPI_PIR register *****************/
+#define QUADSPI_PIR_INTERVAL 0x0000FFFFU /*!< INTERVAL[15:0]: Polling Interval */
+
+/****************** Bit definition for QUADSPI_LPTR register *****************/
+#define QUADSPI_LPTR_TIMEOUT 0x0000FFFFU /*!< TIMEOUT[15:0]: Timeout period */
+
+/******************************************************************************/
+/* */
+/* Reset and Clock Control */
+/* */
+/******************************************************************************/
+/******************** Bit definition for RCC_CR register ********************/
+#define RCC_CR_HSION 0x00000001U
+#define RCC_CR_HSIRDY 0x00000002U
+
+#define RCC_CR_HSITRIM 0x000000F8U
+#define RCC_CR_HSITRIM_0 0x00000008U/*!<Bit 0 */
+#define RCC_CR_HSITRIM_1 0x00000010U/*!<Bit 1 */
+#define RCC_CR_HSITRIM_2 0x00000020U/*!<Bit 2 */
+#define RCC_CR_HSITRIM_3 0x00000040U/*!<Bit 3 */
+#define RCC_CR_HSITRIM_4 0x00000080U/*!<Bit 4 */
+
+#define RCC_CR_HSICAL 0x0000FF00U
+#define RCC_CR_HSICAL_0 0x00000100U/*!<Bit 0 */
+#define RCC_CR_HSICAL_1 0x00000200U/*!<Bit 1 */
+#define RCC_CR_HSICAL_2 0x00000400U/*!<Bit 2 */
+#define RCC_CR_HSICAL_3 0x00000800U/*!<Bit 3 */
+#define RCC_CR_HSICAL_4 0x00001000U/*!<Bit 4 */
+#define RCC_CR_HSICAL_5 0x00002000U/*!<Bit 5 */
+#define RCC_CR_HSICAL_6 0x00004000U/*!<Bit 6 */
+#define RCC_CR_HSICAL_7 0x00008000U/*!<Bit 7 */
+
+#define RCC_CR_HSEON 0x00010000U
+#define RCC_CR_HSERDY 0x00020000U
+#define RCC_CR_HSEBYP 0x00040000U
+#define RCC_CR_CSSON 0x00080000U
+#define RCC_CR_PLLON 0x01000000U
+#define RCC_CR_PLLRDY 0x02000000U
+#define RCC_CR_PLLI2SON 0x04000000U
+#define RCC_CR_PLLI2SRDY 0x08000000U
+
+/******************** Bit definition for RCC_PLLCFGR register ***************/
+#define RCC_PLLCFGR_PLLM 0x0000003FU
+#define RCC_PLLCFGR_PLLM_0 0x00000001U
+#define RCC_PLLCFGR_PLLM_1 0x00000002U
+#define RCC_PLLCFGR_PLLM_2 0x00000004U
+#define RCC_PLLCFGR_PLLM_3 0x00000008U
+#define RCC_PLLCFGR_PLLM_4 0x00000010U
+#define RCC_PLLCFGR_PLLM_5 0x00000020U
+
+#define RCC_PLLCFGR_PLLN 0x00007FC0U
+#define RCC_PLLCFGR_PLLN_0 0x00000040U
+#define RCC_PLLCFGR_PLLN_1 0x00000080U
+#define RCC_PLLCFGR_PLLN_2 0x00000100U
+#define RCC_PLLCFGR_PLLN_3 0x00000200U
+#define RCC_PLLCFGR_PLLN_4 0x00000400U
+#define RCC_PLLCFGR_PLLN_5 0x00000800U
+#define RCC_PLLCFGR_PLLN_6 0x00001000U
+#define RCC_PLLCFGR_PLLN_7 0x00002000U
+#define RCC_PLLCFGR_PLLN_8 0x00004000U
+
+#define RCC_PLLCFGR_PLLP 0x00030000U
+#define RCC_PLLCFGR_PLLP_0 0x00010000U
+#define RCC_PLLCFGR_PLLP_1 0x00020000U
+
+#define RCC_PLLCFGR_PLLSRC 0x00400000U
+#define RCC_PLLCFGR_PLLSRC_HSE 0x00400000U
+#define RCC_PLLCFGR_PLLSRC_HSI 0x00000000U
+
+#define RCC_PLLCFGR_PLLQ 0x0F000000U
+#define RCC_PLLCFGR_PLLQ_0 0x01000000U
+#define RCC_PLLCFGR_PLLQ_1 0x02000000U
+#define RCC_PLLCFGR_PLLQ_2 0x04000000U
+#define RCC_PLLCFGR_PLLQ_3 0x08000000U
+
+#define RCC_PLLCFGR_PLLR 0x70000000U
+#define RCC_PLLCFGR_PLLR_0 0x10000000U
+#define RCC_PLLCFGR_PLLR_1 0x20000000U
+#define RCC_PLLCFGR_PLLR_2 0x40000000U
+
+/******************** Bit definition for RCC_CFGR register ******************/
+/*!< SW configuration */
+#define RCC_CFGR_SW 0x00000003U /*!< SW[1:0] bits (System clock Switch) */
+#define RCC_CFGR_SW_0 0x00000001U /*!< Bit 0 */
+#define RCC_CFGR_SW_1 0x00000002U /*!< Bit 1 */
+
+#define RCC_CFGR_SW_HSI 0x00000000U /*!< HSI selected as system clock */
+#define RCC_CFGR_SW_HSE 0x00000001U /*!< HSE selected as system clock */
+#define RCC_CFGR_SW_PLL 0x00000002U /*!< PLL/PLLP selected as system clock */
+#define RCC_CFGR_SW_PLLR 0x00000003U /*!< PLL/PLLR selected as system clock */
+
+/*!< SWS configuration */
+#define RCC_CFGR_SWS 0x0000000CU /*!< SWS[1:0] bits (System Clock Switch Status) */
+#define RCC_CFGR_SWS_0 0x00000004U /*!< Bit 0 */
+#define RCC_CFGR_SWS_1 0x00000008U /*!< Bit 1 */
+
+#define RCC_CFGR_SWS_HSI 0x00000000U /*!< HSI oscillator used as system clock */
+#define RCC_CFGR_SWS_HSE 0x00000004U /*!< HSE oscillator used as system clock */
+#define RCC_CFGR_SWS_PLL 0x00000008U /*!< PLL/PLLP used as system clock */
+#define RCC_CFGR_SWS_PLLR 0x0000000CU /*!< PLL/PLLR used as system clock */
+
+/*!< HPRE configuration */
+#define RCC_CFGR_HPRE 0x000000F0U /*!< HPRE[3:0] bits (AHB prescaler) */
+#define RCC_CFGR_HPRE_0 0x00000010U /*!< Bit 0 */
+#define RCC_CFGR_HPRE_1 0x00000020U /*!< Bit 1 */
+#define RCC_CFGR_HPRE_2 0x00000040U /*!< Bit 2 */
+#define RCC_CFGR_HPRE_3 0x00000080U /*!< Bit 3 */
+
+#define RCC_CFGR_HPRE_DIV1 0x00000000U /*!< SYSCLK not divided */
+#define RCC_CFGR_HPRE_DIV2 0x00000080U /*!< SYSCLK divided by 2 */
+#define RCC_CFGR_HPRE_DIV4 0x00000090U /*!< SYSCLK divided by 4 */
+#define RCC_CFGR_HPRE_DIV8 0x000000A0U /*!< SYSCLK divided by 8 */
+#define RCC_CFGR_HPRE_DIV16 0x000000B0U /*!< SYSCLK divided by 16 */
+#define RCC_CFGR_HPRE_DIV64 0x000000C0U /*!< SYSCLK divided by 64 */
+#define RCC_CFGR_HPRE_DIV128 0x000000D0U /*!< SYSCLK divided by 128 */
+#define RCC_CFGR_HPRE_DIV256 0x000000E0U /*!< SYSCLK divided by 256 */
+#define RCC_CFGR_HPRE_DIV512 0x000000F0U /*!< SYSCLK divided by 512 */
+
+/*!< PPRE1 configuration */
+#define RCC_CFGR_PPRE1 0x00001C00U /*!< PRE1[2:0] bits (APB1 prescaler) */
+#define RCC_CFGR_PPRE1_0 0x00000400U /*!< Bit 0 */
+#define RCC_CFGR_PPRE1_1 0x00000800U /*!< Bit 1 */
+#define RCC_CFGR_PPRE1_2 0x00001000U /*!< Bit 2 */
+
+#define RCC_CFGR_PPRE1_DIV1 0x00000000U /*!< HCLK not divided */
+#define RCC_CFGR_PPRE1_DIV2 0x00001000U /*!< HCLK divided by 2 */
+#define RCC_CFGR_PPRE1_DIV4 0x00001400U /*!< HCLK divided by 4 */
+#define RCC_CFGR_PPRE1_DIV8 0x00001800U /*!< HCLK divided by 8 */
+#define RCC_CFGR_PPRE1_DIV16 0x00001C00U /*!< HCLK divided by 16 */
+
+/*!< PPRE2 configuration */
+#define RCC_CFGR_PPRE2 0x0000E000U /*!< PRE2[2:0] bits (APB2 prescaler) */
+#define RCC_CFGR_PPRE2_0 0x00002000U /*!< Bit 0 */
+#define RCC_CFGR_PPRE2_1 0x00004000U /*!< Bit 1 */
+#define RCC_CFGR_PPRE2_2 0x00008000U /*!< Bit 2 */
+
+#define RCC_CFGR_PPRE2_DIV1 0x00000000U /*!< HCLK not divided */
+#define RCC_CFGR_PPRE2_DIV2 0x00008000U /*!< HCLK divided by 2 */
+#define RCC_CFGR_PPRE2_DIV4 0x0000A000U /*!< HCLK divided by 4 */
+#define RCC_CFGR_PPRE2_DIV8 0x0000C000U /*!< HCLK divided by 8 */
+#define RCC_CFGR_PPRE2_DIV16 0x0000E000U /*!< HCLK divided by 16 */
+
+/*!< RTCPRE configuration */
+#define RCC_CFGR_RTCPRE 0x001F0000U
+#define RCC_CFGR_RTCPRE_0 0x00010000U
+#define RCC_CFGR_RTCPRE_1 0x00020000U
+#define RCC_CFGR_RTCPRE_2 0x00040000U
+#define RCC_CFGR_RTCPRE_3 0x00080000U
+#define RCC_CFGR_RTCPRE_4 0x00100000U
+
+/*!< MCO1 configuration */
+#define RCC_CFGR_MCO1 0x00600000U
+#define RCC_CFGR_MCO1_0 0x00200000U
+#define RCC_CFGR_MCO1_1 0x00400000U
+
+#define RCC_CFGR_MCO1PRE 0x07000000U
+#define RCC_CFGR_MCO1PRE_0 0x01000000U
+#define RCC_CFGR_MCO1PRE_1 0x02000000U
+#define RCC_CFGR_MCO1PRE_2 0x04000000U
+
+#define RCC_CFGR_MCO2PRE 0x38000000U
+#define RCC_CFGR_MCO2PRE_0 0x08000000U
+#define RCC_CFGR_MCO2PRE_1 0x10000000U
+#define RCC_CFGR_MCO2PRE_2 0x20000000U
+
+#define RCC_CFGR_MCO2 0xC0000000U
+#define RCC_CFGR_MCO2_0 0x40000000U
+#define RCC_CFGR_MCO2_1 0x80000000U
+
+/******************** Bit definition for RCC_CIR register *******************/
+#define RCC_CIR_LSIRDYF 0x00000001U
+#define RCC_CIR_LSERDYF 0x00000002U
+#define RCC_CIR_HSIRDYF 0x00000004U
+#define RCC_CIR_HSERDYF 0x00000008U
+#define RCC_CIR_PLLRDYF 0x00000010U
+#define RCC_CIR_PLLI2SRDYF 0x00000020U
+
+#define RCC_CIR_CSSF 0x00000080U
+#define RCC_CIR_LSIRDYIE 0x00000100U
+#define RCC_CIR_LSERDYIE 0x00000200U
+#define RCC_CIR_HSIRDYIE 0x00000400U
+#define RCC_CIR_HSERDYIE 0x00000800U
+#define RCC_CIR_PLLRDYIE 0x00001000U
+#define RCC_CIR_PLLI2SRDYIE 0x00002000U
+
+#define RCC_CIR_LSIRDYC 0x00010000U
+#define RCC_CIR_LSERDYC 0x00020000U
+#define RCC_CIR_HSIRDYC 0x00040000U
+#define RCC_CIR_HSERDYC 0x00080000U
+#define RCC_CIR_PLLRDYC 0x00100000U
+#define RCC_CIR_PLLI2SRDYC 0x00200000U
+
+#define RCC_CIR_CSSC 0x00800000U
+
+/******************** Bit definition for RCC_AHB1RSTR register **************/
+#define RCC_AHB1RSTR_GPIOARST 0x00000001U
+#define RCC_AHB1RSTR_GPIOBRST 0x00000002U
+#define RCC_AHB1RSTR_GPIOCRST 0x00000004U
+#define RCC_AHB1RSTR_GPIODRST 0x00000008U
+#define RCC_AHB1RSTR_GPIOERST 0x00000010U
+#define RCC_AHB1RSTR_GPIOFRST 0x00000020U
+#define RCC_AHB1RSTR_GPIOGRST 0x00000040U
+#define RCC_AHB1RSTR_GPIOHRST 0x00000080U
+#define RCC_AHB1RSTR_CRCRST 0x00001000U
+#define RCC_AHB1RSTR_DMA1RST 0x00200000U
+#define RCC_AHB1RSTR_DMA2RST 0x00400000U
+
+/******************** Bit definition for RCC_AHB2RSTR register **************/
+#define RCC_AHB2RSTR_RNGRST 0x00000040U
+#define RCC_AHB2RSTR_OTGFSRST 0x00000080U
+
+/******************** Bit definition for RCC_AHB3RSTR register **************/
+#define RCC_AHB3RSTR_FSMCRST 0x00000001U
+#define RCC_AHB3RSTR_QSPIRST 0x00000002U
+
+/******************** Bit definition for RCC_APB1RSTR register **************/
+#define RCC_APB1RSTR_TIM2RST 0x00000001U
+#define RCC_APB1RSTR_TIM3RST 0x00000002U
+#define RCC_APB1RSTR_TIM4RST 0x00000004U
+#define RCC_APB1RSTR_TIM5RST 0x00000008U
+#define RCC_APB1RSTR_TIM6RST 0x00000010U
+#define RCC_APB1RSTR_TIM7RST 0x00000020U
+#define RCC_APB1RSTR_TIM12RST 0x00000040U
+#define RCC_APB1RSTR_TIM13RST 0x00000080U
+#define RCC_APB1RSTR_TIM14RST 0x00000100U
+#define RCC_APB1RSTR_WWDGRST 0x00000800U
+#define RCC_APB1RSTR_SPI2RST 0x00004000U
+#define RCC_APB1RSTR_SPI3RST 0x00008000U
+#define RCC_APB1RSTR_USART2RST 0x00020000U
+#define RCC_APB1RSTR_USART3RST 0x00040000U
+#define RCC_APB1RSTR_I2C1RST 0x00200000U
+#define RCC_APB1RSTR_I2C2RST 0x00400000U
+#define RCC_APB1RSTR_I2C3RST 0x00800000U
+#define RCC_APB1RSTR_FMPI2C1RST 0x01000000U
+#define RCC_APB1RSTR_CAN1RST 0x02000000U
+#define RCC_APB1RSTR_CAN2RST 0x04000000U
+#define RCC_APB1RSTR_PWRRST 0x10000000U
+
+/******************** Bit definition for RCC_APB2RSTR register **************/
+#define RCC_APB2RSTR_TIM1RST 0x00000001U
+#define RCC_APB2RSTR_TIM8RST 0x00000002U
+#define RCC_APB2RSTR_USART1RST 0x00000010U
+#define RCC_APB2RSTR_USART6RST 0x00000020U
+#define RCC_APB2RSTR_ADCRST 0x00000100U
+#define RCC_APB2RSTR_SDIORST 0x00000800U
+#define RCC_APB2RSTR_SPI1RST 0x00001000U
+#define RCC_APB2RSTR_SPI4RST 0x00002000U
+#define RCC_APB2RSTR_SYSCFGRST 0x00004000U
+#define RCC_APB2RSTR_TIM9RST 0x00010000U
+#define RCC_APB2RSTR_TIM10RST 0x00020000U
+#define RCC_APB2RSTR_TIM11RST 0x00040000U
+#define RCC_APB2RSTR_SPI5RST 0x00100000U
+#define RCC_APB2RSTR_DFSDM1RST 0x01000000U
+
+/******************** Bit definition for RCC_AHB1ENR register ***************/
+#define RCC_AHB1ENR_GPIOAEN 0x00000001U
+#define RCC_AHB1ENR_GPIOBEN 0x00000002U
+#define RCC_AHB1ENR_GPIOCEN 0x00000004U
+#define RCC_AHB1ENR_GPIODEN 0x00000008U
+#define RCC_AHB1ENR_GPIOEEN 0x00000010U
+#define RCC_AHB1ENR_GPIOFEN 0x00000020U
+#define RCC_AHB1ENR_GPIOGEN 0x00000040U
+#define RCC_AHB1ENR_GPIOHEN 0x00000080U
+#define RCC_AHB1ENR_CRCEN 0x00001000U
+#define RCC_AHB1ENR_DMA1EN 0x00200000U
+#define RCC_AHB1ENR_DMA2EN 0x00400000U
+
+/******************** Bit definition for RCC_AHB2ENR register ***************/
+#define RCC_AHB2ENR_RNGEN 0x00000040U
+#define RCC_AHB2ENR_OTGFSEN 0x00000080U
+
+/******************** Bit definition for RCC_AHB3ENR register ***************/
+#define RCC_AHB3ENR_FSMCEN 0x00000001U
+#define RCC_AHB3ENR_QSPIEN 0x00000002U
+
+/******************** Bit definition for RCC_APB1ENR register ***************/
+#define RCC_APB1ENR_TIM2EN 0x00000001U
+#define RCC_APB1ENR_TIM3EN 0x00000002U
+#define RCC_APB1ENR_TIM4EN 0x00000004U
+#define RCC_APB1ENR_TIM5EN 0x00000008U
+#define RCC_APB1ENR_TIM6EN 0x00000010U
+#define RCC_APB1ENR_TIM7EN 0x00000020U
+#define RCC_APB1ENR_TIM12EN 0x00000040U
+#define RCC_APB1ENR_TIM13EN 0x00000080U
+#define RCC_APB1ENR_TIM14EN 0x00000100U
+#define RCC_APB1ENR_RTCAPBEN 0x00000400U
+#define RCC_APB1ENR_WWDGEN 0x00000800U
+#define RCC_APB1ENR_SPI2EN 0x00004000U
+#define RCC_APB1ENR_SPI3EN 0x00008000U
+#define RCC_APB1ENR_USART2EN 0x00020000U
+#define RCC_APB1ENR_USART3EN 0x00040000U
+#define RCC_APB1ENR_I2C1EN 0x00200000U
+#define RCC_APB1ENR_I2C2EN 0x00400000U
+#define RCC_APB1ENR_I2C3EN 0x00800000U
+#define RCC_APB1ENR_FMPI2C1EN 0x01000000U
+#define RCC_APB1ENR_CAN1EN 0x02000000U
+#define RCC_APB1ENR_CAN2EN 0x04000000U
+#define RCC_APB1ENR_PWREN 0x10000000U
+
+/******************** Bit definition for RCC_APB2ENR register ***************/
+#define RCC_APB2ENR_TIM1EN 0x00000001U
+#define RCC_APB2ENR_TIM8EN 0x00000002U
+#define RCC_APB2ENR_USART1EN 0x00000010U
+#define RCC_APB2ENR_USART6EN 0x00000020U
+#define RCC_APB2ENR_ADC1EN 0x00000100U
+#define RCC_APB2ENR_SDIOEN 0x00000800U
+#define RCC_APB2ENR_SPI1EN 0x00001000U
+#define RCC_APB2ENR_SPI4EN 0x00002000U
+#define RCC_APB2ENR_SYSCFGEN 0x00004000U
+#define RCC_APB2ENR_EXTITEN 0x00008000U
+#define RCC_APB2ENR_TIM9EN 0x00010000U
+#define RCC_APB2ENR_TIM10EN 0x00020000U
+#define RCC_APB2ENR_TIM11EN 0x00040000U
+#define RCC_APB2ENR_SPI5EN 0x00100000U
+#define RCC_APB2ENR_DFSDM1EN 0x01000000U
+/******************** Bit definition for RCC_AHB1LPENR register *************/
+#define RCC_AHB1LPENR_GPIOALPEN 0x00000001U
+#define RCC_AHB1LPENR_GPIOBLPEN 0x00000002U
+#define RCC_AHB1LPENR_GPIOCLPEN 0x00000004U
+#define RCC_AHB1LPENR_GPIODLPEN 0x00000008U
+#define RCC_AHB1LPENR_GPIOELPEN 0x00000010U
+#define RCC_AHB1LPENR_GPIOFLPEN 0x00000020U
+#define RCC_AHB1LPENR_GPIOGLPEN 0x00000040U
+#define RCC_AHB1LPENR_GPIOHLPEN 0x00000080U
+#define RCC_AHB1LPENR_CRCLPEN 0x00001000U
+#define RCC_AHB1LPENR_FLITFLPEN 0x00008000U
+#define RCC_AHB1LPENR_SRAM1LPEN 0x00010000U
+#define RCC_AHB1LPENR_DMA1LPEN 0x00200000U
+#define RCC_AHB1LPENR_DMA2LPEN 0x00400000U
+
+/******************** Bit definition for RCC_AHB2LPENR register *************/
+#define RCC_AHB2LPENR_RNGLPEN 0x00000040U
+#define RCC_AHB2LPENR_OTGFSLPEN 0x00000080U
+
+/******************** Bit definition for RCC_AHB3LPENR register *************/
+#define RCC_AHB3LPENR_FSMCLPEN 0x00000001U
+#define RCC_AHB3LPENR_QSPILPEN 0x00000002U
+
+/******************** Bit definition for RCC_APB1LPENR register *************/
+#define RCC_APB1LPENR_TIM2LPEN 0x00000001U
+#define RCC_APB1LPENR_TIM3LPEN 0x00000002U
+#define RCC_APB1LPENR_TIM4LPEN 0x00000004U
+#define RCC_APB1LPENR_TIM5LPEN 0x00000008U
+#define RCC_APB1LPENR_TIM6LPEN 0x00000010U
+#define RCC_APB1LPENR_TIM7LPEN 0x00000020U
+#define RCC_APB1LPENR_TIM12LPEN 0x00000040U
+#define RCC_APB1LPENR_TIM13LPEN 0x00000080U
+#define RCC_APB1LPENR_TIM14LPEN 0x00000100U
+#define RCC_APB1LPENR_RTCAPBLPEN 0x00000400U
+#define RCC_APB1LPENR_WWDGLPEN 0x00000800U
+#define RCC_APB1LPENR_SPI2LPEN 0x00004000U
+#define RCC_APB1LPENR_SPI3LPEN 0x00008000U
+#define RCC_APB1LPENR_USART2LPEN 0x00020000U
+#define RCC_APB1LPENR_USART3LPEN 0x00040000U
+#define RCC_APB1LPENR_I2C1LPEN 0x00200000U
+#define RCC_APB1LPENR_I2C2LPEN 0x00400000U
+#define RCC_APB1LPENR_I2C3LPEN 0x00800000U
+#define RCC_APB1LPENR_FMPI2C1LPEN 0x01000000U
+#define RCC_APB1LPENR_CAN1LPEN 0x02000000U
+#define RCC_APB1LPENR_CAN2LPEN 0x04000000U
+#define RCC_APB1LPENR_PWRLPEN 0x10000000U
+
+/******************** Bit definition for RCC_APB2LPENR register *************/
+#define RCC_APB2LPENR_TIM1LPEN 0x00000001U
+#define RCC_APB2LPENR_TIM8LPEN 0x00000002U
+#define RCC_APB2LPENR_USART1LPEN 0x00000010U
+#define RCC_APB2LPENR_USART6LPEN 0x00000020U
+#define RCC_APB2LPENR_ADC1LPEN 0x00000100U
+#define RCC_APB2LPENR_SDIOLPEN 0x00000800U
+#define RCC_APB2LPENR_SPI1LPEN 0x00001000U
+#define RCC_APB2LPENR_SPI4LPEN 0x00002000U
+#define RCC_APB2LPENR_SYSCFGLPEN 0x00004000U
+#define RCC_APB2LPENR_EXTITLPEN 0x00008000U
+#define RCC_APB2LPENR_TIM9LPEN 0x00010000U
+#define RCC_APB2LPENR_TIM10LPEN 0x00020000U
+#define RCC_APB2LPENR_TIM11LPEN 0x00040000U
+#define RCC_APB2LPENR_SPI5LPEN 0x00100000U
+#define RCC_APB2LPENR_DFSDM1LPEN 0x01000000U
+
+/******************** Bit definition for RCC_BDCR register ******************/
+#define RCC_BDCR_LSEON 0x00000001U
+#define RCC_BDCR_LSERDY 0x00000002U
+#define RCC_BDCR_LSEBYP 0x00000004U
+#define RCC_BDCR_LSEMOD 0x00000008U
+
+#define RCC_BDCR_RTCSEL 0x00000300U
+#define RCC_BDCR_RTCSEL_0 0x00000100U
+#define RCC_BDCR_RTCSEL_1 0x00000200U
+
+#define RCC_BDCR_RTCEN 0x00008000U
+#define RCC_BDCR_BDRST 0x00010000U
+
+/******************** Bit definition for RCC_CSR register *******************/
+#define RCC_CSR_LSION 0x00000001U
+#define RCC_CSR_LSIRDY 0x00000002U
+#define RCC_CSR_RMVF 0x01000000U
+#define RCC_CSR_PADRSTF 0x04000000U
+#define RCC_CSR_PORRSTF 0x08000000U
+#define RCC_CSR_SFTRSTF 0x10000000U
+#define RCC_CSR_WDGRSTF 0x20000000U
+#define RCC_CSR_WWDGRSTF 0x40000000U
+#define RCC_CSR_LPWRRSTF 0x80000000U
+
+/******************** Bit definition for RCC_SSCGR register *****************/
+#define RCC_SSCGR_MODPER 0x00001FFFU
+#define RCC_SSCGR_INCSTEP 0x0FFFE000U
+#define RCC_SSCGR_SPREADSEL 0x40000000U
+#define RCC_SSCGR_SSCGEN 0x80000000U
+
+/******************** Bit definition for RCC_PLLI2SCFGR register ************/
+#define RCC_PLLI2SCFGR_PLLI2SM 0x0000003FU
+#define RCC_PLLI2SCFGR_PLLI2SM_0 0x00000001U
+#define RCC_PLLI2SCFGR_PLLI2SM_1 0x00000002U
+#define RCC_PLLI2SCFGR_PLLI2SM_2 0x00000004U
+#define RCC_PLLI2SCFGR_PLLI2SM_3 0x00000008U
+#define RCC_PLLI2SCFGR_PLLI2SM_4 0x00000010U
+#define RCC_PLLI2SCFGR_PLLI2SM_5 0x00000020U
+
+#define RCC_PLLI2SCFGR_PLLI2SN 0x00007FC0U
+#define RCC_PLLI2SCFGR_PLLI2SN_0 0x00000040U
+#define RCC_PLLI2SCFGR_PLLI2SN_1 0x00000080U
+#define RCC_PLLI2SCFGR_PLLI2SN_2 0x00000100U
+#define RCC_PLLI2SCFGR_PLLI2SN_3 0x00000200U
+#define RCC_PLLI2SCFGR_PLLI2SN_4 0x00000400U
+#define RCC_PLLI2SCFGR_PLLI2SN_5 0x00000800U
+#define RCC_PLLI2SCFGR_PLLI2SN_6 0x00001000U
+#define RCC_PLLI2SCFGR_PLLI2SN_7 0x00002000U
+#define RCC_PLLI2SCFGR_PLLI2SN_8 0x00004000U
+
+#define RCC_PLLI2SCFGR_PLLI2SSRC 0x00400000U
+
+#define RCC_PLLI2SCFGR_PLLI2SQ 0x0F000000U
+#define RCC_PLLI2SCFGR_PLLI2SQ_0 0x01000000U
+#define RCC_PLLI2SCFGR_PLLI2SQ_1 0x02000000U
+#define RCC_PLLI2SCFGR_PLLI2SQ_2 0x04000000U
+#define RCC_PLLI2SCFGR_PLLI2SQ_3 0x08000000U
+
+#define RCC_PLLI2SCFGR_PLLI2SR 0x70000000U
+#define RCC_PLLI2SCFGR_PLLI2SR_0 0x10000000U
+#define RCC_PLLI2SCFGR_PLLI2SR_1 0x20000000U
+#define RCC_PLLI2SCFGR_PLLI2SR_2 0x40000000U
+
+/******************** Bit definition for RCC_DCKCFGR register ****************/
+#define RCC_DCKCFGR_CKDFSDM1ASEL 0x00008000U
+#define RCC_DCKCFGR_TIMPRE 0x01000000U
+
+#define RCC_DCKCFGR_I2S1SRC 0x06000000U
+#define RCC_DCKCFGR_I2S1SRC_0 0x02000000U
+#define RCC_DCKCFGR_I2S1SRC_1 0x04000000U
+
+#define RCC_DCKCFGR_I2S2SRC 0x18000000U
+#define RCC_DCKCFGR_I2S2SRC_0 0x08000000U
+#define RCC_DCKCFGR_I2S2SRC_1 0x10000000U
+
+#define RCC_DCKCFGR_CKDFSDM1SEL 0x80000000U
+
+/******************** Bit definition for RCC_CKGATENR register ***************/
+#define RCC_CKGATENR_AHB2APB1_CKEN 0x00000001U
+#define RCC_CKGATENR_AHB2APB2_CKEN 0x00000002U
+#define RCC_CKGATENR_CM4DBG_CKEN 0x00000004U
+#define RCC_CKGATENR_SPARE_CKEN 0x00000008U
+#define RCC_CKGATENR_SRAM_CKEN 0x00000010U
+#define RCC_CKGATENR_FLITF_CKEN 0x00000020U
+#define RCC_CKGATENR_RCC_CKEN 0x00000040U
+#define RCC_CKGATENR_RCC_EVTCTL 0x00000080U
+
+/******************** Bit definition for RCC_DCKCFGR2 register ***************/
+#define RCC_DCKCFGR2_FMPI2C1SEL 0x00C00000U
+#define RCC_DCKCFGR2_FMPI2C1SEL_0 0x00400000U
+#define RCC_DCKCFGR2_FMPI2C1SEL_1 0x00800000U
+
+#define RCC_DCKCFGR2_CK48MSEL 0x08000000U
+#define RCC_DCKCFGR2_SDIOSEL 0x10000000U
+
+/******************************************************************************/
+/* */
+/* RNG */
+/* */
+/******************************************************************************/
+/******************** Bits definition for RNG_CR register *******************/
+#define RNG_CR_RNGEN 0x00000004U
+#define RNG_CR_IE 0x00000008U
+
+/******************** Bits definition for RNG_SR register *******************/
+#define RNG_SR_DRDY 0x00000001U
+#define RNG_SR_CECS 0x00000002U
+#define RNG_SR_SECS 0x00000004U
+#define RNG_SR_CEIS 0x00000020U
+#define RNG_SR_SEIS 0x00000040U
+
+/******************************************************************************/
+/* */
+/* Real-Time Clock (RTC) */
+/* */
+/******************************************************************************/
+/******************** Bits definition for RTC_TR register *******************/
+#define RTC_TR_PM 0x00400000U
+#define RTC_TR_HT 0x00300000U
+#define RTC_TR_HT_0 0x00100000U
+#define RTC_TR_HT_1 0x00200000U
+#define RTC_TR_HU 0x000F0000U
+#define RTC_TR_HU_0 0x00010000U
+#define RTC_TR_HU_1 0x00020000U
+#define RTC_TR_HU_2 0x00040000U
+#define RTC_TR_HU_3 0x00080000U
+#define RTC_TR_MNT 0x00007000U
+#define RTC_TR_MNT_0 0x00001000U
+#define RTC_TR_MNT_1 0x00002000U
+#define RTC_TR_MNT_2 0x00004000U
+#define RTC_TR_MNU 0x00000F00U
+#define RTC_TR_MNU_0 0x00000100U
+#define RTC_TR_MNU_1 0x00000200U
+#define RTC_TR_MNU_2 0x00000400U
+#define RTC_TR_MNU_3 0x00000800U
+#define RTC_TR_ST 0x00000070U
+#define RTC_TR_ST_0 0x00000010U
+#define RTC_TR_ST_1 0x00000020U
+#define RTC_TR_ST_2 0x00000040U
+#define RTC_TR_SU 0x0000000FU
+#define RTC_TR_SU_0 0x00000001U
+#define RTC_TR_SU_1 0x00000002U
+#define RTC_TR_SU_2 0x00000004U
+#define RTC_TR_SU_3 0x00000008U
+
+/******************** Bits definition for RTC_DR register *******************/
+#define RTC_DR_YT 0x00F00000U
+#define RTC_DR_YT_0 0x00100000U
+#define RTC_DR_YT_1 0x00200000U
+#define RTC_DR_YT_2 0x00400000U
+#define RTC_DR_YT_3 0x00800000U
+#define RTC_DR_YU 0x000F0000U
+#define RTC_DR_YU_0 0x00010000U
+#define RTC_DR_YU_1 0x00020000U
+#define RTC_DR_YU_2 0x00040000U
+#define RTC_DR_YU_3 0x00080000U
+#define RTC_DR_WDU 0x0000E000U
+#define RTC_DR_WDU_0 0x00002000U
+#define RTC_DR_WDU_1 0x00004000U
+#define RTC_DR_WDU_2 0x00008000U
+#define RTC_DR_MT 0x00001000U
+#define RTC_DR_MU 0x00000F00U
+#define RTC_DR_MU_0 0x00000100U
+#define RTC_DR_MU_1 0x00000200U
+#define RTC_DR_MU_2 0x00000400U
+#define RTC_DR_MU_3 0x00000800U
+#define RTC_DR_DT 0x00000030U
+#define RTC_DR_DT_0 0x00000010U
+#define RTC_DR_DT_1 0x00000020U
+#define RTC_DR_DU 0x0000000FU
+#define RTC_DR_DU_0 0x00000001U
+#define RTC_DR_DU_1 0x00000002U
+#define RTC_DR_DU_2 0x00000004U
+#define RTC_DR_DU_3 0x00000008U
+
+/******************** Bits definition for RTC_CR register *******************/
+#define RTC_CR_COE 0x00800000U
+#define RTC_CR_OSEL 0x00600000U
+#define RTC_CR_OSEL_0 0x00200000U
+#define RTC_CR_OSEL_1 0x00400000U
+#define RTC_CR_POL 0x00100000U
+#define RTC_CR_COSEL 0x00080000U
+#define RTC_CR_BCK 0x00040000U
+#define RTC_CR_SUB1H 0x00020000U
+#define RTC_CR_ADD1H 0x00010000U
+#define RTC_CR_TSIE 0x00008000U
+#define RTC_CR_WUTIE 0x00004000U
+#define RTC_CR_ALRBIE 0x00002000U
+#define RTC_CR_ALRAIE 0x00001000U
+#define RTC_CR_TSE 0x00000800U
+#define RTC_CR_WUTE 0x00000400U
+#define RTC_CR_ALRBE 0x00000200U
+#define RTC_CR_ALRAE 0x00000100U
+#define RTC_CR_DCE 0x00000080U
+#define RTC_CR_FMT 0x00000040U
+#define RTC_CR_BYPSHAD 0x00000020U
+#define RTC_CR_REFCKON 0x00000010U
+#define RTC_CR_TSEDGE 0x00000008U
+#define RTC_CR_WUCKSEL 0x00000007U
+#define RTC_CR_WUCKSEL_0 0x00000001U
+#define RTC_CR_WUCKSEL_1 0x00000002U
+#define RTC_CR_WUCKSEL_2 0x00000004U
+
+/******************** Bits definition for RTC_ISR register ******************/
+#define RTC_ISR_RECALPF 0x00010000U
+#define RTC_ISR_TAMP1F 0x00002000U
+#define RTC_ISR_TAMP2F 0x00004000U
+#define RTC_ISR_TSOVF 0x00001000U
+#define RTC_ISR_TSF 0x00000800U
+#define RTC_ISR_WUTF 0x00000400U
+#define RTC_ISR_ALRBF 0x00000200U
+#define RTC_ISR_ALRAF 0x00000100U
+#define RTC_ISR_INIT 0x00000080U
+#define RTC_ISR_INITF 0x00000040U
+#define RTC_ISR_RSF 0x00000020U
+#define RTC_ISR_INITS 0x00000010U
+#define RTC_ISR_SHPF 0x00000008U
+#define RTC_ISR_WUTWF 0x00000004U
+#define RTC_ISR_ALRBWF 0x00000002U
+#define RTC_ISR_ALRAWF 0x00000001U
+
+/******************** Bits definition for RTC_PRER register *****************/
+#define RTC_PRER_PREDIV_A 0x007F0000U
+#define RTC_PRER_PREDIV_S 0x00007FFFU
+
+/******************** Bits definition for RTC_WUTR register *****************/
+#define RTC_WUTR_WUT 0x0000FFFFU
+
+/******************** Bits definition for RTC_CALIBR register ***************/
+#define RTC_CALIBR_DCS 0x00000080U
+#define RTC_CALIBR_DC 0x0000001FU
+
+/******************** Bits definition for RTC_ALRMAR register ***************/
+#define RTC_ALRMAR_MSK4 0x80000000U
+#define RTC_ALRMAR_WDSEL 0x40000000U
+#define RTC_ALRMAR_DT 0x30000000U
+#define RTC_ALRMAR_DT_0 0x10000000U
+#define RTC_ALRMAR_DT_1 0x20000000U
+#define RTC_ALRMAR_DU 0x0F000000U
+#define RTC_ALRMAR_DU_0 0x01000000U
+#define RTC_ALRMAR_DU_1 0x02000000U
+#define RTC_ALRMAR_DU_2 0x04000000U
+#define RTC_ALRMAR_DU_3 0x08000000U
+#define RTC_ALRMAR_MSK3 0x00800000U
+#define RTC_ALRMAR_PM 0x00400000U
+#define RTC_ALRMAR_HT 0x00300000U
+#define RTC_ALRMAR_HT_0 0x00100000U
+#define RTC_ALRMAR_HT_1 0x00200000U
+#define RTC_ALRMAR_HU 0x000F0000U
+#define RTC_ALRMAR_HU_0 0x00010000U
+#define RTC_ALRMAR_HU_1 0x00020000U
+#define RTC_ALRMAR_HU_2 0x00040000U
+#define RTC_ALRMAR_HU_3 0x00080000U
+#define RTC_ALRMAR_MSK2 0x00008000U
+#define RTC_ALRMAR_MNT 0x00007000U
+#define RTC_ALRMAR_MNT_0 0x00001000U
+#define RTC_ALRMAR_MNT_1 0x00002000U
+#define RTC_ALRMAR_MNT_2 0x00004000U
+#define RTC_ALRMAR_MNU 0x00000F00U
+#define RTC_ALRMAR_MNU_0 0x00000100U
+#define RTC_ALRMAR_MNU_1 0x00000200U
+#define RTC_ALRMAR_MNU_2 0x00000400U
+#define RTC_ALRMAR_MNU_3 0x00000800U
+#define RTC_ALRMAR_MSK1 0x00000080U
+#define RTC_ALRMAR_ST 0x00000070U
+#define RTC_ALRMAR_ST_0 0x00000010U
+#define RTC_ALRMAR_ST_1 0x00000020U
+#define RTC_ALRMAR_ST_2 0x00000040U
+#define RTC_ALRMAR_SU 0x0000000FU
+#define RTC_ALRMAR_SU_0 0x00000001U
+#define RTC_ALRMAR_SU_1 0x00000002U
+#define RTC_ALRMAR_SU_2 0x00000004U
+#define RTC_ALRMAR_SU_3 0x00000008U
+
+/******************** Bits definition for RTC_ALRMBR register ***************/
+#define RTC_ALRMBR_MSK4 0x80000000U
+#define RTC_ALRMBR_WDSEL 0x40000000U
+#define RTC_ALRMBR_DT 0x30000000U
+#define RTC_ALRMBR_DT_0 0x10000000U
+#define RTC_ALRMBR_DT_1 0x20000000U
+#define RTC_ALRMBR_DU 0x0F000000U
+#define RTC_ALRMBR_DU_0 0x01000000U
+#define RTC_ALRMBR_DU_1 0x02000000U
+#define RTC_ALRMBR_DU_2 0x04000000U
+#define RTC_ALRMBR_DU_3 0x08000000U
+#define RTC_ALRMBR_MSK3 0x00800000U
+#define RTC_ALRMBR_PM 0x00400000U
+#define RTC_ALRMBR_HT 0x00300000U
+#define RTC_ALRMBR_HT_0 0x00100000U
+#define RTC_ALRMBR_HT_1 0x00200000U
+#define RTC_ALRMBR_HU 0x000F0000U
+#define RTC_ALRMBR_HU_0 0x00010000U
+#define RTC_ALRMBR_HU_1 0x00020000U
+#define RTC_ALRMBR_HU_2 0x00040000U
+#define RTC_ALRMBR_HU_3 0x00080000U
+#define RTC_ALRMBR_MSK2 0x00008000U
+#define RTC_ALRMBR_MNT 0x00007000U
+#define RTC_ALRMBR_MNT_0 0x00001000U
+#define RTC_ALRMBR_MNT_1 0x00002000U
+#define RTC_ALRMBR_MNT_2 0x00004000U
+#define RTC_ALRMBR_MNU 0x00000F00U
+#define RTC_ALRMBR_MNU_0 0x00000100U
+#define RTC_ALRMBR_MNU_1 0x00000200U
+#define RTC_ALRMBR_MNU_2 0x00000400U
+#define RTC_ALRMBR_MNU_3 0x00000800U
+#define RTC_ALRMBR_MSK1 0x00000080U
+#define RTC_ALRMBR_ST 0x00000070U
+#define RTC_ALRMBR_ST_0 0x00000010U
+#define RTC_ALRMBR_ST_1 0x00000020U
+#define RTC_ALRMBR_ST_2 0x00000040U
+#define RTC_ALRMBR_SU 0x0000000FU
+#define RTC_ALRMBR_SU_0 0x00000001U
+#define RTC_ALRMBR_SU_1 0x00000002U
+#define RTC_ALRMBR_SU_2 0x00000004U
+#define RTC_ALRMBR_SU_3 0x00000008U
+
+/******************** Bits definition for RTC_WPR register ******************/
+#define RTC_WPR_KEY 0x000000FFU
+
+/******************** Bits definition for RTC_SSR register ******************/
+#define RTC_SSR_SS 0x0000FFFFU
+
+/******************** Bits definition for RTC_SHIFTR register ***************/
+#define RTC_SHIFTR_SUBFS 0x00007FFFU
+#define RTC_SHIFTR_ADD1S 0x80000000U
+
+/******************** Bits definition for RTC_TSTR register *****************/
+#define RTC_TSTR_PM 0x00400000U
+#define RTC_TSTR_HT 0x00300000U
+#define RTC_TSTR_HT_0 0x00100000U
+#define RTC_TSTR_HT_1 0x00200000U
+#define RTC_TSTR_HU 0x000F0000U
+#define RTC_TSTR_HU_0 0x00010000U
+#define RTC_TSTR_HU_1 0x00020000U
+#define RTC_TSTR_HU_2 0x00040000U
+#define RTC_TSTR_HU_3 0x00080000U
+#define RTC_TSTR_MNT 0x00007000U
+#define RTC_TSTR_MNT_0 0x00001000U
+#define RTC_TSTR_MNT_1 0x00002000U
+#define RTC_TSTR_MNT_2 0x00004000U
+#define RTC_TSTR_MNU 0x00000F00U
+#define RTC_TSTR_MNU_0 0x00000100U
+#define RTC_TSTR_MNU_1 0x00000200U
+#define RTC_TSTR_MNU_2 0x00000400U
+#define RTC_TSTR_MNU_3 0x00000800U
+#define RTC_TSTR_ST 0x00000070U
+#define RTC_TSTR_ST_0 0x00000010U
+#define RTC_TSTR_ST_1 0x00000020U
+#define RTC_TSTR_ST_2 0x00000040U
+#define RTC_TSTR_SU 0x0000000FU
+#define RTC_TSTR_SU_0 0x00000001U
+#define RTC_TSTR_SU_1 0x00000002U
+#define RTC_TSTR_SU_2 0x00000004U
+#define RTC_TSTR_SU_3 0x00000008U
+
+/******************** Bits definition for RTC_TSDR register *****************/
+#define RTC_TSDR_WDU 0x0000E000U
+#define RTC_TSDR_WDU_0 0x00002000U
+#define RTC_TSDR_WDU_1 0x00004000U
+#define RTC_TSDR_WDU_2 0x00008000U
+#define RTC_TSDR_MT 0x00001000U
+#define RTC_TSDR_MU 0x00000F00U
+#define RTC_TSDR_MU_0 0x00000100U
+#define RTC_TSDR_MU_1 0x00000200U
+#define RTC_TSDR_MU_2 0x00000400U
+#define RTC_TSDR_MU_3 0x00000800U
+#define RTC_TSDR_DT 0x00000030U
+#define RTC_TSDR_DT_0 0x00000010U
+#define RTC_TSDR_DT_1 0x00000020U
+#define RTC_TSDR_DU 0x0000000FU
+#define RTC_TSDR_DU_0 0x00000001U
+#define RTC_TSDR_DU_1 0x00000002U
+#define RTC_TSDR_DU_2 0x00000004U
+#define RTC_TSDR_DU_3 0x00000008U
+
+/******************** Bits definition for RTC_TSSSR register ****************/
+#define RTC_TSSSR_SS 0x0000FFFFU
+
+/******************** Bits definition for RTC_CAL register *****************/
+#define RTC_CALR_CALP 0x00008000U
+#define RTC_CALR_CALW8 0x00004000U
+#define RTC_CALR_CALW16 0x00002000U
+#define RTC_CALR_CALM 0x000001FFU
+#define RTC_CALR_CALM_0 0x00000001U
+#define RTC_CALR_CALM_1 0x00000002U
+#define RTC_CALR_CALM_2 0x00000004U
+#define RTC_CALR_CALM_3 0x00000008U
+#define RTC_CALR_CALM_4 0x00000010U
+#define RTC_CALR_CALM_5 0x00000020U
+#define RTC_CALR_CALM_6 0x00000040U
+#define RTC_CALR_CALM_7 0x00000080U
+#define RTC_CALR_CALM_8 0x00000100U
+
+/******************** Bits definition for RTC_TAFCR register ****************/
+#define RTC_TAFCR_ALARMOUTTYPE 0x00040000U
+#define RTC_TAFCR_TSINSEL 0x00020000U
+#define RTC_TAFCR_TAMPINSEL 0x00010000U
+#define RTC_TAFCR_TAMPPUDIS 0x00008000U
+#define RTC_TAFCR_TAMPPRCH 0x00006000U
+#define RTC_TAFCR_TAMPPRCH_0 0x00002000U
+#define RTC_TAFCR_TAMPPRCH_1 0x00004000U
+#define RTC_TAFCR_TAMPFLT 0x00001800U
+#define RTC_TAFCR_TAMPFLT_0 0x00000800U
+#define RTC_TAFCR_TAMPFLT_1 0x00001000U
+#define RTC_TAFCR_TAMPFREQ 0x00000700U
+#define RTC_TAFCR_TAMPFREQ_0 0x00000100U
+#define RTC_TAFCR_TAMPFREQ_1 0x00000200U
+#define RTC_TAFCR_TAMPFREQ_2 0x00000400U
+#define RTC_TAFCR_TAMPTS 0x00000080U
+#define RTC_TAFCR_TAMP2TRG 0x00000010U
+#define RTC_TAFCR_TAMP2E 0x00000008U
+#define RTC_TAFCR_TAMPIE 0x00000004U
+#define RTC_TAFCR_TAMP1TRG 0x00000002U
+#define RTC_TAFCR_TAMP1E 0x00000001U
+
+/******************** Bits definition for RTC_ALRMASSR register *************/
+#define RTC_ALRMASSR_MASKSS 0x0F000000U
+#define RTC_ALRMASSR_MASKSS_0 0x01000000U
+#define RTC_ALRMASSR_MASKSS_1 0x02000000U
+#define RTC_ALRMASSR_MASKSS_2 0x04000000U
+#define RTC_ALRMASSR_MASKSS_3 0x08000000U
+#define RTC_ALRMASSR_SS 0x00007FFFU
+
+/******************** Bits definition for RTC_ALRMBSSR register *************/
+#define RTC_ALRMBSSR_MASKSS 0x0F000000U
+#define RTC_ALRMBSSR_MASKSS_0 0x01000000U
+#define RTC_ALRMBSSR_MASKSS_1 0x02000000U
+#define RTC_ALRMBSSR_MASKSS_2 0x04000000U
+#define RTC_ALRMBSSR_MASKSS_3 0x08000000U
+#define RTC_ALRMBSSR_SS 0x00007FFFU
+
+/******************** Bits definition for RTC_BKP0R register ****************/
+#define RTC_BKP0R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP1R register ****************/
+#define RTC_BKP1R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP2R register ****************/
+#define RTC_BKP2R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP3R register ****************/
+#define RTC_BKP3R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP4R register ****************/
+#define RTC_BKP4R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP5R register ****************/
+#define RTC_BKP5R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP6R register ****************/
+#define RTC_BKP6R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP7R register ****************/
+#define RTC_BKP7R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP8R register ****************/
+#define RTC_BKP8R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP9R register ****************/
+#define RTC_BKP9R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP10R register ***************/
+#define RTC_BKP10R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP11R register ***************/
+#define RTC_BKP11R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP12R register ***************/
+#define RTC_BKP12R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP13R register ***************/
+#define RTC_BKP13R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP14R register ***************/
+#define RTC_BKP14R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP15R register ***************/
+#define RTC_BKP15R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP16R register ***************/
+#define RTC_BKP16R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP17R register ***************/
+#define RTC_BKP17R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP18R register ***************/
+#define RTC_BKP18R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP19R register ***************/
+#define RTC_BKP19R 0xFFFFFFFFU
+
+
+
+/******************************************************************************/
+/* */
+/* SD host Interface */
+/* */
+/******************************************************************************/
+/****************** Bit definition for SDIO_POWER register ******************/
+#define SDIO_POWER_PWRCTRL 0x03U /*!<PWRCTRL[1:0] bits (Power supply control bits) */
+#define SDIO_POWER_PWRCTRL_0 0x01U /*!<Bit 0 */
+#define SDIO_POWER_PWRCTRL_1 0x02U /*!<Bit 1 */
+
+/****************** Bit definition for SDIO_CLKCR register ******************/
+#define SDIO_CLKCR_CLKDIV 0x00FFU /*!<Clock divide factor */
+#define SDIO_CLKCR_CLKEN 0x0100U /*!<Clock enable bit */
+#define SDIO_CLKCR_PWRSAV 0x0200U /*!<Power saving configuration bit */
+#define SDIO_CLKCR_BYPASS 0x0400U /*!<Clock divider bypass enable bit */
+
+#define SDIO_CLKCR_WIDBUS 0x1800U /*!<WIDBUS[1:0] bits (Wide bus mode enable bit) */
+#define SDIO_CLKCR_WIDBUS_0 0x0800U /*!<Bit 0 */
+#define SDIO_CLKCR_WIDBUS_1 0x1000U /*!<Bit 1 */
+
+#define SDIO_CLKCR_NEGEDGE 0x2000U /*!<SDIO_CK dephasing selection bit */
+#define SDIO_CLKCR_HWFC_EN 0x4000U /*!<HW Flow Control enable */
+
+/******************* Bit definition for SDIO_ARG register *******************/
+#define SDIO_ARG_CMDARG 0xFFFFFFFFU /*!<Command argument */
+
+/******************* Bit definition for SDIO_CMD register *******************/
+#define SDIO_CMD_CMDINDEX 0x003FU /*!<Command Index */
+
+#define SDIO_CMD_WAITRESP 0x00C0U /*!<WAITRESP[1:0] bits (Wait for response bits) */
+#define SDIO_CMD_WAITRESP_0 0x0040U /*!< Bit 0 */
+#define SDIO_CMD_WAITRESP_1 0x0080U /*!< Bit 1 */
+
+#define SDIO_CMD_WAITINT 0x0100U /*!<CPSM Waits for Interrupt Request */
+#define SDIO_CMD_WAITPEND 0x0200U /*!<CPSM Waits for ends of data transfer (CmdPend internal signal) */
+#define SDIO_CMD_CPSMEN 0x0400U /*!<Command path state machine (CPSM) Enable bit */
+#define SDIO_CMD_SDIOSUSPEND 0x0800U /*!<SD I/O suspend command */
+#define SDIO_CMD_ENCMDCOMPL 0x1000U /*!<Enable CMD completion */
+#define SDIO_CMD_NIEN 0x2000U /*!<Not Interrupt Enable */
+#define SDIO_CMD_CEATACMD 0x4000U /*!<CE-ATA command */
+
+/***************** Bit definition for SDIO_RESPCMD register *****************/
+#define SDIO_RESPCMD_RESPCMD 0x3FU /*!<Response command index */
+
+/****************** Bit definition for SDIO_RESP0 register ******************/
+#define SDIO_RESP0_CARDSTATUS0 0xFFFFFFFFU /*!<Card Status */
+
+/****************** Bit definition for SDIO_RESP1 register ******************/
+#define SDIO_RESP1_CARDSTATUS1 0xFFFFFFFFU /*!<Card Status */
+
+/****************** Bit definition for SDIO_RESP2 register ******************/
+#define SDIO_RESP2_CARDSTATUS2 0xFFFFFFFFU /*!<Card Status */
+
+/****************** Bit definition for SDIO_RESP3 register ******************/
+#define SDIO_RESP3_CARDSTATUS3 0xFFFFFFFFU /*!<Card Status */
+
+/****************** Bit definition for SDIO_RESP4 register ******************/
+#define SDIO_RESP4_CARDSTATUS4 0xFFFFFFFFU /*!<Card Status */
+
+/****************** Bit definition for SDIO_DTIMER register *****************/
+#define SDIO_DTIMER_DATATIME 0xFFFFFFFFU /*!<Data timeout period. */
+
+/****************** Bit definition for SDIO_DLEN register *******************/
+#define SDIO_DLEN_DATALENGTH 0x01FFFFFFU /*!<Data length value */
+
+/****************** Bit definition for SDIO_DCTRL register ******************/
+#define SDIO_DCTRL_DTEN 0x0001U /*!<Data transfer enabled bit */
+#define SDIO_DCTRL_DTDIR 0x0002U /*!<Data transfer direction selection */
+#define SDIO_DCTRL_DTMODE 0x0004U /*!<Data transfer mode selection */
+#define SDIO_DCTRL_DMAEN 0x0008U /*!<DMA enabled bit */
+
+#define SDIO_DCTRL_DBLOCKSIZE 0x00F0U /*!<DBLOCKSIZE[3:0] bits (Data block size) */
+#define SDIO_DCTRL_DBLOCKSIZE_0 0x0010U /*!<Bit 0 */
+#define SDIO_DCTRL_DBLOCKSIZE_1 0x0020U /*!<Bit 1 */
+#define SDIO_DCTRL_DBLOCKSIZE_2 0x0040U /*!<Bit 2 */
+#define SDIO_DCTRL_DBLOCKSIZE_3 0x0080U /*!<Bit 3 */
+
+#define SDIO_DCTRL_RWSTART 0x0100U /*!<Read wait start */
+#define SDIO_DCTRL_RWSTOP 0x0200U /*!<Read wait stop */
+#define SDIO_DCTRL_RWMOD 0x0400U /*!<Read wait mode */
+#define SDIO_DCTRL_SDIOEN 0x0800U /*!<SD I/O enable functions */
+
+/****************** Bit definition for SDIO_DCOUNT register *****************/
+#define SDIO_DCOUNT_DATACOUNT 0x01FFFFFFU /*!<Data count value */
+
+/****************** Bit definition for SDIO_STA register ********************/
+#define SDIO_STA_CCRCFAIL 0x00000001U /*!<Command response received (CRC check failed) */
+#define SDIO_STA_DCRCFAIL 0x00000002U /*!<Data block sent/received (CRC check failed) */
+#define SDIO_STA_CTIMEOUT 0x00000004U /*!<Command response timeout */
+#define SDIO_STA_DTIMEOUT 0x00000008U /*!<Data timeout */
+#define SDIO_STA_TXUNDERR 0x00000010U /*!<Transmit FIFO underrun error */
+#define SDIO_STA_RXOVERR 0x00000020U /*!<Received FIFO overrun error */
+#define SDIO_STA_CMDREND 0x00000040U /*!<Command response received (CRC check passed) */
+#define SDIO_STA_CMDSENT 0x00000080U /*!<Command sent (no response required) */
+#define SDIO_STA_DATAEND 0x00000100U /*!<Data end (data counter, SDIDCOUNT, is zero) */
+#define SDIO_STA_STBITERR 0x00000200U /*!<Start bit not detected on all data signals in wide bus mode */
+#define SDIO_STA_DBCKEND 0x00000400U /*!<Data block sent/received (CRC check passed) */
+#define SDIO_STA_CMDACT 0x00000800U /*!<Command transfer in progress */
+#define SDIO_STA_TXACT 0x00001000U /*!<Data transmit in progress */
+#define SDIO_STA_RXACT 0x00002000U /*!<Data receive in progress */
+#define SDIO_STA_TXFIFOHE 0x00004000U /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
+#define SDIO_STA_RXFIFOHF 0x00008000U /*!<Receive FIFO Half Full: there are at least 8 words in the FIFO */
+#define SDIO_STA_TXFIFOF 0x00010000U /*!<Transmit FIFO full */
+#define SDIO_STA_RXFIFOF 0x00020000U /*!<Receive FIFO full */
+#define SDIO_STA_TXFIFOE 0x00040000U /*!<Transmit FIFO empty */
+#define SDIO_STA_RXFIFOE 0x00080000U /*!<Receive FIFO empty */
+#define SDIO_STA_TXDAVL 0x00100000U /*!<Data available in transmit FIFO */
+#define SDIO_STA_RXDAVL 0x00200000U /*!<Data available in receive FIFO */
+#define SDIO_STA_SDIOIT 0x00400000U /*!<SDIO interrupt received */
+#define SDIO_STA_CEATAEND 0x00800000U /*!<CE-ATA command completion signal received for CMD61 */
+
+/******************* Bit definition for SDIO_ICR register *******************/
+#define SDIO_ICR_CCRCFAILC 0x00000001U /*!<CCRCFAIL flag clear bit */
+#define SDIO_ICR_DCRCFAILC 0x00000002U /*!<DCRCFAIL flag clear bit */
+#define SDIO_ICR_CTIMEOUTC 0x00000004U /*!<CTIMEOUT flag clear bit */
+#define SDIO_ICR_DTIMEOUTC 0x00000008U /*!<DTIMEOUT flag clear bit */
+#define SDIO_ICR_TXUNDERRC 0x00000010U /*!<TXUNDERR flag clear bit */
+#define SDIO_ICR_RXOVERRC 0x00000020U /*!<RXOVERR flag clear bit */
+#define SDIO_ICR_CMDRENDC 0x00000040U /*!<CMDREND flag clear bit */
+#define SDIO_ICR_CMDSENTC 0x00000080U /*!<CMDSENT flag clear bit */
+#define SDIO_ICR_DATAENDC 0x00000100U /*!<DATAEND flag clear bit */
+#define SDIO_ICR_STBITERRC 0x00000200U /*!<STBITERR flag clear bit */
+#define SDIO_ICR_DBCKENDC 0x00000400U /*!<DBCKEND flag clear bit */
+#define SDIO_ICR_SDIOITC 0x00400000U /*!<SDIOIT flag clear bit */
+#define SDIO_ICR_CEATAENDC 0x00800000U /*!<CEATAEND flag clear bit */
+
+/****************** Bit definition for SDIO_MASK register *******************/
+#define SDIO_MASK_CCRCFAILIE 0x00000001U /*!<Command CRC Fail Interrupt Enable */
+#define SDIO_MASK_DCRCFAILIE 0x00000002U /*!<Data CRC Fail Interrupt Enable */
+#define SDIO_MASK_CTIMEOUTIE 0x00000004U /*!<Command TimeOut Interrupt Enable */
+#define SDIO_MASK_DTIMEOUTIE 0x00000008U /*!<Data TimeOut Interrupt Enable */
+#define SDIO_MASK_TXUNDERRIE 0x00000010U /*!<Tx FIFO UnderRun Error Interrupt Enable */
+#define SDIO_MASK_RXOVERRIE 0x00000020U /*!<Rx FIFO OverRun Error Interrupt Enable */
+#define SDIO_MASK_CMDRENDIE 0x00000040U /*!<Command Response Received Interrupt Enable */
+#define SDIO_MASK_CMDSENTIE 0x00000080U /*!<Command Sent Interrupt Enable */
+#define SDIO_MASK_DATAENDIE 0x00000100U /*!<Data End Interrupt Enable */
+#define SDIO_MASK_STBITERRIE 0x00000200U /*!<Start Bit Error Interrupt Enable */
+#define SDIO_MASK_DBCKENDIE 0x00000400U /*!<Data Block End Interrupt Enable */
+#define SDIO_MASK_CMDACTIE 0x00000800U /*!<CCommand Acting Interrupt Enable */
+#define SDIO_MASK_TXACTIE 0x00001000U /*!<Data Transmit Acting Interrupt Enable */
+#define SDIO_MASK_RXACTIE 0x00002000U /*!<Data receive acting interrupt enabled */
+#define SDIO_MASK_TXFIFOHEIE 0x00004000U /*!<Tx FIFO Half Empty interrupt Enable */
+#define SDIO_MASK_RXFIFOHFIE 0x00008000U /*!<Rx FIFO Half Full interrupt Enable */
+#define SDIO_MASK_TXFIFOFIE 0x00010000U /*!<Tx FIFO Full interrupt Enable */
+#define SDIO_MASK_RXFIFOFIE 0x00020000U /*!<Rx FIFO Full interrupt Enable */
+#define SDIO_MASK_TXFIFOEIE 0x00040000U /*!<Tx FIFO Empty interrupt Enable */
+#define SDIO_MASK_RXFIFOEIE 0x00080000U /*!<Rx FIFO Empty interrupt Enable */
+#define SDIO_MASK_TXDAVLIE 0x00100000U /*!<Data available in Tx FIFO interrupt Enable */
+#define SDIO_MASK_RXDAVLIE 0x00200000U /*!<Data available in Rx FIFO interrupt Enable */
+#define SDIO_MASK_SDIOITIE 0x00400000U /*!<SDIO Mode Interrupt Received interrupt Enable */
+#define SDIO_MASK_CEATAENDIE 0x00800000U /*!<CE-ATA command completion signal received Interrupt Enable */
+
+/***************** Bit definition for SDIO_FIFOCNT register *****************/
+#define SDIO_FIFOCNT_FIFOCOUNT 0x00FFFFFFU /*!<Remaining number of words to be written to or read from the FIFO */
+
+/****************** Bit definition for SDIO_FIFO register *******************/
+#define SDIO_FIFO_FIFODATA 0xFFFFFFFFU /*!<Receive and transmit FIFO data */
+
+/******************************************************************************/
+/* */
+/* Serial Peripheral Interface */
+/* */
+/******************************************************************************/
+/******************* Bit definition for SPI_CR1 register ********************/
+#define SPI_CR1_CPHA 0x00000001U /*!<Clock Phase */
+#define SPI_CR1_CPOL 0x00000002U /*!<Clock Polarity */
+#define SPI_CR1_MSTR 0x00000004U /*!<Master Selection */
+
+#define SPI_CR1_BR 0x00000038U /*!<BR[2:0] bits (Baud Rate Control) */
+#define SPI_CR1_BR_0 0x00000008U /*!<Bit 0 */
+#define SPI_CR1_BR_1 0x00000010U /*!<Bit 1 */
+#define SPI_CR1_BR_2 0x00000020U /*!<Bit 2 */
+
+#define SPI_CR1_SPE 0x00000040U /*!<SPI Enable */
+#define SPI_CR1_LSBFIRST 0x00000080U /*!<Frame Format */
+#define SPI_CR1_SSI 0x00000100U /*!<Internal slave select */
+#define SPI_CR1_SSM 0x00000200U /*!<Software slave management */
+#define SPI_CR1_RXONLY 0x00000400U /*!<Receive only */
+#define SPI_CR1_DFF 0x00000800U /*!<Data Frame Format */
+#define SPI_CR1_CRCNEXT 0x00001000U /*!<Transmit CRC next */
+#define SPI_CR1_CRCEN 0x00002000U /*!<Hardware CRC calculation enable */
+#define SPI_CR1_BIDIOE 0x00004000U /*!<Output enable in bidirectional mode */
+#define SPI_CR1_BIDIMODE 0x00008000U /*!<Bidirectional data mode enable */
+
+/******************* Bit definition for SPI_CR2 register ********************/
+#define SPI_CR2_RXDMAEN 0x00000001U /*!<Rx Buffer DMA Enable */
+#define SPI_CR2_TXDMAEN 0x00000002U /*!<Tx Buffer DMA Enable */
+#define SPI_CR2_SSOE 0x00000004U /*!<SS Output Enable */
+#define SPI_CR2_FRF 0x00000010U /*!<Frame Format */
+#define SPI_CR2_ERRIE 0x00000020U /*!<Error Interrupt Enable */
+#define SPI_CR2_RXNEIE 0x00000040U /*!<RX buffer Not Empty Interrupt Enable */
+#define SPI_CR2_TXEIE 0x00000080U /*!<Tx buffer Empty Interrupt Enable */
+
+/******************** Bit definition for SPI_SR register ********************/
+#define SPI_SR_RXNE 0x00000001U /*!<Receive buffer Not Empty */
+#define SPI_SR_TXE 0x00000002U /*!<Transmit buffer Empty */
+#define SPI_SR_CHSIDE 0x00000004U /*!<Channel side */
+#define SPI_SR_UDR 0x00000008U /*!<Underrun flag */
+#define SPI_SR_CRCERR 0x00000010U /*!<CRC Error flag */
+#define SPI_SR_MODF 0x00000020U /*!<Mode fault */
+#define SPI_SR_OVR 0x00000040U /*!<Overrun flag */
+#define SPI_SR_BSY 0x00000080U /*!<Busy flag */
+#define SPI_SR_FRE 0x00000100U /*!<Frame format error flag */
+
+/******************** Bit definition for SPI_DR register ********************/
+#define SPI_DR_DR 0x0000FFFFU /*!<Data Register */
+
+/******************* Bit definition for SPI_CRCPR register ******************/
+#define SPI_CRCPR_CRCPOLY 0x0000FFFFU /*!<CRC polynomial register */
+
+/****************** Bit definition for SPI_RXCRCR register ******************/
+#define SPI_RXCRCR_RXCRC 0x0000FFFFU /*!<Rx CRC Register */
+
+/****************** Bit definition for SPI_TXCRCR register ******************/
+#define SPI_TXCRCR_TXCRC 0x0000FFFFU /*!<Tx CRC Register */
+
+/****************** Bit definition for SPI_I2SCFGR register *****************/
+#define SPI_I2SCFGR_CHLEN 0x00000001U /*!<Channel length (number of bits per audio channel) */
+
+#define SPI_I2SCFGR_DATLEN 0x00000006U /*!<DATLEN[1:0] bits (Data length to be transferred) */
+#define SPI_I2SCFGR_DATLEN_0 0x00000002U /*!<Bit 0 */
+#define SPI_I2SCFGR_DATLEN_1 0x00000004U /*!<Bit 1 */
+
+#define SPI_I2SCFGR_CKPOL 0x00000008U /*!<steady state clock polarity */
+
+#define SPI_I2SCFGR_I2SSTD 0x00000030U /*!<I2SSTD[1:0] bits (I2S standard selection) */
+#define SPI_I2SCFGR_I2SSTD_0 0x00000010U /*!<Bit 0 */
+#define SPI_I2SCFGR_I2SSTD_1 0x00000020U /*!<Bit 1 */
+
+#define SPI_I2SCFGR_PCMSYNC 0x00000080U /*!<PCM frame synchronization */
+
+#define SPI_I2SCFGR_I2SCFG 0x00000300U /*!<I2SCFG[1:0] bits (I2S configuration mode) */
+#define SPI_I2SCFGR_I2SCFG_0 0x00000100U /*!<Bit 0 */
+#define SPI_I2SCFGR_I2SCFG_1 0x00000200U /*!<Bit 1 */
+
+#define SPI_I2SCFGR_I2SE 0x00000400U /*!<I2S Enable */
+#define SPI_I2SCFGR_I2SMOD 0x00000800U /*!<I2S mode selection */
+
+/****************** Bit definition for SPI_I2SPR register *******************/
+#define SPI_I2SPR_I2SDIV 0x000000FFU /*!<I2S Linear prescaler */
+#define SPI_I2SPR_ODD 0x00000100U /*!<Odd factor for the prescaler */
+#define SPI_I2SPR_MCKOE 0x00000200U /*!<Master Clock Output Enable */
+
+/******************************************************************************/
+/* */
+/* SYSCFG */
+/* */
+/******************************************************************************/
+/****************** Bit definition for SYSCFG_MEMRMP register ***************/
+#define SYSCFG_MEMRMP_MEM_MODE 0x00000007U /*!< SYSCFG_Memory Remap Config */
+#define SYSCFG_MEMRMP_MEM_MODE_0 0x00000001U
+#define SYSCFG_MEMRMP_MEM_MODE_1 0x00000002U
+#define SYSCFG_MEMRMP_MEM_MODE_2 0x00000004U
+
+#define SYSCFG_SWP_FSMC 0x00000C00U /*!< FSMC memory mapping swap */
+/****************** Bit definition for SYSCFG_PMC register ******************/
+#define SYSCFG_PMC_ADC1DC2 0x00010000U /*!< Refer to AN4073 on how to use this bit */
+
+/***************** Bit definition for SYSCFG_EXTICR1 register ***************/
+#define SYSCFG_EXTICR1_EXTI0 0x000FU /*!<EXTI 0 configuration */
+#define SYSCFG_EXTICR1_EXTI1 0x00F0U /*!<EXTI 1 configuration */
+#define SYSCFG_EXTICR1_EXTI2 0x0F00U /*!<EXTI 2 configuration */
+#define SYSCFG_EXTICR1_EXTI3 0xF000U /*!<EXTI 3 configuration */
+/**
+ * @brief EXTI0 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI0_PA 0x0000U /*!<PA[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PB 0x0001U /*!<PB[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PC 0x0002U /*!<PC[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PD 0x0003U /*!<PD[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PE 0x0004U /*!<PE[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PF 0x0005U /*!<PE[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PG 0x0006U /*!<PE[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PH 0x0007U /*!<PH[0] pin */
+
+/**
+ * @brief EXTI1 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI1_PA 0x0000U /*!<PA[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PB 0x0010U /*!<PB[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PC 0x0020U /*!<PC[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PD 0x0030U /*!<PD[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PE 0x0040U /*!<PE[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PF 0x0050U /*!<PD[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PG 0x0060U /*!<PE[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PH 0x0070U /*!<PH[1] pin */
+
+/**
+ * @brief EXTI2 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI2_PA 0x0000U /*!<PA[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PB 0x0100U /*!<PB[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PC 0x0200U /*!<PC[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PD 0x0300U /*!<PD[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PE 0x0400U /*!<PE[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PF 0x0500U /*!<PE[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PG 0x0600U /*!<PE[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PH 0x0700U /*!<PH[2] pin */
+
+/**
+ * @brief EXTI3 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI3_PA 0x0000U /*!<PA[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PB 0x1000U /*!<PB[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PC 0x2000U /*!<PC[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PD 0x3000U /*!<PD[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PE 0x4000U /*!<PE[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PF 0x5000U /*!<PE[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PG 0x6000U /*!<PE[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PH 0x7000U /*!<PH[3] pin */
+
+/***************** Bit definition for SYSCFG_EXTICR2 register ***************/
+#define SYSCFG_EXTICR2_EXTI4 0x000FU /*!<EXTI 4 configuration */
+#define SYSCFG_EXTICR2_EXTI5 0x00F0U /*!<EXTI 5 configuration */
+#define SYSCFG_EXTICR2_EXTI6 0x0F00U /*!<EXTI 6 configuration */
+#define SYSCFG_EXTICR2_EXTI7 0xF000U /*!<EXTI 7 configuration */
+/**
+ * @brief EXTI4 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI4_PA 0x0000U /*!<PA[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PB 0x0001U /*!<PB[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PC 0x0002U /*!<PC[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PD 0x0003U /*!<PD[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PE 0x0004U /*!<PE[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PF 0x0005U /*!<PE[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PG 0x0006U /*!<PE[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PH 0x0007U /*!<PH[4] pin */
+
+/**
+ * @brief EXTI5 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI5_PA 0x0000U /*!<PA[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PB 0x0010U /*!<PB[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PC 0x0020U /*!<PC[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PD 0x0030U /*!<PD[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PE 0x0040U /*!<PE[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PF 0x0050U /*!<PE[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PG 0x0060U /*!<PE[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PH 0x0070U /*!<PH[5] pin */
+
+/**
+ * @brief EXTI6 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI6_PA 0x0000U /*!<PA[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PB 0x0100U /*!<PB[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PC 0x0200U /*!<PC[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PD 0x0300U /*!<PD[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PE 0x0400U /*!<PE[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PF 0x0500U /*!<PE[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PG 0x0600U /*!<PE[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PH 0x0700U /*!<PH[6] pin */
+
+/**
+ * @brief EXTI7 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI7_PA 0x0000U /*!<PA[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PB 0x1000U /*!<PB[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PC 0x2000U /*!<PC[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PD 0x3000U /*!<PD[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PE 0x4000U /*!<PE[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PF 0x5000U /*!<PE[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PG 0x6000U /*!<PE[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PH 0x7000U /*!<PH[7] pin */
+
+
+/***************** Bit definition for SYSCFG_EXTICR3 register ***************/
+#define SYSCFG_EXTICR3_EXTI8 0x000FU /*!<EXTI 8 configuration */
+#define SYSCFG_EXTICR3_EXTI9 0x00F0U /*!<EXTI 9 configuration */
+#define SYSCFG_EXTICR3_EXTI10 0x0F00U /*!<EXTI 10 configuration */
+#define SYSCFG_EXTICR3_EXTI11 0xF000U /*!<EXTI 11 configuration */
+
+/**
+ * @brief EXTI8 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI8_PA 0x0000U /*!<PA[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PB 0x0001U /*!<PB[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PC 0x0002U /*!<PC[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PD 0x0003U /*!<PD[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PE 0x0004U /*!<PE[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PF 0x0005U /*!<PE[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PG 0x0006U /*!<PE[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PH 0x0007U /*!<PH[8] pin */
+
+/**
+ * @brief EXTI9 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI9_PA 0x0000U /*!<PA[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PB 0x0010U /*!<PB[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PC 0x0020U /*!<PC[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PD 0x0030U /*!<PD[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PE 0x0040U /*!<PE[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PF 0x0050U /*!<PE[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PG 0x0060U /*!<PE[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PH 0x0070U /*!<PH[9] pin */
+
+/**
+ * @brief EXTI10 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI10_PA 0x0000U /*!<PA[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PB 0x0100U /*!<PB[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PC 0x0200U /*!<PC[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PD 0x0300U /*!<PD[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PE 0x0400U /*!<PE[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PF 0x0500U /*!<PE[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PG 0x0600U /*!<PE[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PH 0x0700U /*!<PH[10] pin */
+
+/**
+ * @brief EXTI11 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI11_PA 0x0000U /*!<PA[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PB 0x1000U /*!<PB[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PC 0x2000U /*!<PC[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PD 0x3000U /*!<PD[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PE 0x4000U /*!<PE[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PF 0x5000U /*!<PE[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PG 0x6000U /*!<PE[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PH 0x7000U /*!<PH[11] pin */
+
+/***************** Bit definition for SYSCFG_EXTICR4 register ***************/
+#define SYSCFG_EXTICR4_EXTI12 0x000FU /*!<EXTI 12 configuration */
+#define SYSCFG_EXTICR4_EXTI13 0x00F0U /*!<EXTI 13 configuration */
+#define SYSCFG_EXTICR4_EXTI14 0x0F00U /*!<EXTI 14 configuration */
+#define SYSCFG_EXTICR4_EXTI15 0xF000U /*!<EXTI 15 configuration */
+/**
+ * @brief EXTI12 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI12_PA 0x0000U /*!<PA[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PB 0x0001U /*!<PB[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PC 0x0002U /*!<PC[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PD 0x0003U /*!<PD[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PE 0x0004U /*!<PE[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PF 0x0005U /*!<PE[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PG 0x0006U /*!<PE[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PH 0x0007U /*!<PH[12] pin */
+
+/**
+ * @brief EXTI13 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI13_PA 0x0000U /*!<PA[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PB 0x0010U /*!<PB[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PC 0x0020U /*!<PC[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PD 0x0030U /*!<PD[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PE 0x0040U /*!<PE[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PF 0x0050U /*!<PE[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PG 0x0060U /*!<PE[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PH 0x0070U /*!<PH[13] pin */
+
+/**
+ * @brief EXTI14 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI14_PA 0x0000U /*!<PA[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PB 0x0100U /*!<PB[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PC 0x0200U /*!<PC[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PD 0x0300U /*!<PD[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PE 0x0400U /*!<PE[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PF 0x0500U /*!<PE[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PG 0x0600U /*!<PE[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PH 0x0700U /*!<PH[14] pin */
+
+/**
+ * @brief EXTI15 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI15_PA 0x0000U /*!<PA[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PB 0x1000U /*!<PB[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PC 0x2000U /*!<PC[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PD 0x3000U /*!<PD[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PE 0x4000U /*!<PE[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PF 0x5000U /*!<PF[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PG 0x6000U /*!<PG[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PH 0x7000U /*!<PH[15] pin */
+
+/****************** Bit definition for SYSCFG_CMPCR register ****************/
+#define SYSCFG_CMPCR_CMP_PD 0x00000001U /*!<Compensation cell ready flag */
+#define SYSCFG_CMPCR_READY 0x00000100U /*!<Compensation cell power-down */
+
+/****************** Bit definition for SYSCFG_CFGR register *****************/
+#define SYSCFG_CFGR_FMPI2C1_SCL 0x00000001U /*!<FM+ drive capability for FMPI2C1_SCL pin */
+#define SYSCFG_CFGR_FMPI2C1_SDA 0x00000002U /*!<FM+ drive capability for FMPI2C1_SDA pin */
+
+/******************************************************************************/
+/* */
+/* TIM */
+/* */
+/******************************************************************************/
+/******************* Bit definition for TIM_CR1 register ********************/
+#define TIM_CR1_CEN 0x0001U /*!<Counter enable */
+#define TIM_CR1_UDIS 0x0002U /*!<Update disable */
+#define TIM_CR1_URS 0x0004U /*!<Update request source */
+#define TIM_CR1_OPM 0x0008U /*!<One pulse mode */
+#define TIM_CR1_DIR 0x0010U /*!<Direction */
+
+#define TIM_CR1_CMS 0x0060U /*!<CMS[1:0] bits (Center-aligned mode selection) */
+#define TIM_CR1_CMS_0 0x0020U /*!<Bit 0 */
+#define TIM_CR1_CMS_1 0x0040U /*!<Bit 1 */
+
+#define TIM_CR1_ARPE 0x0080U /*!<Auto-reload preload enable */
+
+#define TIM_CR1_CKD 0x0300U /*!<CKD[1:0] bits (clock division) */
+#define TIM_CR1_CKD_0 0x0100U /*!<Bit 0 */
+#define TIM_CR1_CKD_1 0x0200U /*!<Bit 1 */
+
+/******************* Bit definition for TIM_CR2 register ********************/
+#define TIM_CR2_CCPC 0x0001U /*!<Capture/Compare Preloaded Control */
+#define TIM_CR2_CCUS 0x0004U /*!<Capture/Compare Control Update Selection */
+#define TIM_CR2_CCDS 0x0008U /*!<Capture/Compare DMA Selection */
+
+#define TIM_CR2_MMS 0x0070U /*!<MMS[2:0] bits (Master Mode Selection) */
+#define TIM_CR2_MMS_0 0x0010U /*!<Bit 0 */
+#define TIM_CR2_MMS_1 0x0020U /*!<Bit 1 */
+#define TIM_CR2_MMS_2 0x0040U /*!<Bit 2 */
+
+#define TIM_CR2_TI1S 0x0080U /*!<TI1 Selection */
+#define TIM_CR2_OIS1 0x0100U /*!<Output Idle state 1 (OC1 output) */
+#define TIM_CR2_OIS1N 0x0200U /*!<Output Idle state 1 (OC1N output) */
+#define TIM_CR2_OIS2 0x0400U /*!<Output Idle state 2 (OC2 output) */
+#define TIM_CR2_OIS2N 0x0800U /*!<Output Idle state 2 (OC2N output) */
+#define TIM_CR2_OIS3 0x1000U /*!<Output Idle state 3 (OC3 output) */
+#define TIM_CR2_OIS3N 0x2000U /*!<Output Idle state 3 (OC3N output) */
+#define TIM_CR2_OIS4 0x4000U /*!<Output Idle state 4 (OC4 output) */
+
+/******************* Bit definition for TIM_SMCR register *******************/
+#define TIM_SMCR_SMS 0x0007U /*!<SMS[2:0] bits (Slave mode selection) */
+#define TIM_SMCR_SMS_0 0x0001U /*!<Bit 0 */
+#define TIM_SMCR_SMS_1 0x0002U /*!<Bit 1 */
+#define TIM_SMCR_SMS_2 0x0004U /*!<Bit 2 */
+
+#define TIM_SMCR_TS 0x0070U /*!<TS[2:0] bits (Trigger selection) */
+#define TIM_SMCR_TS_0 0x0010U /*!<Bit 0 */
+#define TIM_SMCR_TS_1 0x0020U /*!<Bit 1 */
+#define TIM_SMCR_TS_2 0x0040U /*!<Bit 2 */
+
+#define TIM_SMCR_MSM 0x0080U /*!<Master/slave mode */
+
+#define TIM_SMCR_ETF 0x0F00U /*!<ETF[3:0] bits (External trigger filter) */
+#define TIM_SMCR_ETF_0 0x0100U /*!<Bit 0 */
+#define TIM_SMCR_ETF_1 0x0200U /*!<Bit 1 */
+#define TIM_SMCR_ETF_2 0x0400U /*!<Bit 2 */
+#define TIM_SMCR_ETF_3 0x0800U /*!<Bit 3 */
+
+#define TIM_SMCR_ETPS 0x3000U /*!<ETPS[1:0] bits (External trigger prescaler) */
+#define TIM_SMCR_ETPS_0 0x1000U /*!<Bit 0 */
+#define TIM_SMCR_ETPS_1 0x2000U /*!<Bit 1 */
+
+#define TIM_SMCR_ECE 0x4000U /*!<External clock enable */
+#define TIM_SMCR_ETP 0x8000U /*!<External trigger polarity */
+
+/******************* Bit definition for TIM_DIER register *******************/
+#define TIM_DIER_UIE 0x0001U /*!<Update interrupt enable */
+#define TIM_DIER_CC1IE 0x0002U /*!<Capture/Compare 1 interrupt enable */
+#define TIM_DIER_CC2IE 0x0004U /*!<Capture/Compare 2 interrupt enable */
+#define TIM_DIER_CC3IE 0x0008U /*!<Capture/Compare 3 interrupt enable */
+#define TIM_DIER_CC4IE 0x0010U /*!<Capture/Compare 4 interrupt enable */
+#define TIM_DIER_COMIE 0x0020U /*!<COM interrupt enable */
+#define TIM_DIER_TIE 0x0040U /*!<Trigger interrupt enable */
+#define TIM_DIER_BIE 0x0080U /*!<Break interrupt enable */
+#define TIM_DIER_UDE 0x0100U /*!<Update DMA request enable */
+#define TIM_DIER_CC1DE 0x0200U /*!<Capture/Compare 1 DMA request enable */
+#define TIM_DIER_CC2DE 0x0400U /*!<Capture/Compare 2 DMA request enable */
+#define TIM_DIER_CC3DE 0x0800U /*!<Capture/Compare 3 DMA request enable */
+#define TIM_DIER_CC4DE 0x1000U /*!<Capture/Compare 4 DMA request enable */
+#define TIM_DIER_COMDE 0x2000U /*!<COM DMA request enable */
+#define TIM_DIER_TDE 0x4000U /*!<Trigger DMA request enable */
+
+/******************** Bit definition for TIM_SR register ********************/
+#define TIM_SR_UIF 0x0001U /*!<Update interrupt Flag */
+#define TIM_SR_CC1IF 0x0002U /*!<Capture/Compare 1 interrupt Flag */
+#define TIM_SR_CC2IF 0x0004U /*!<Capture/Compare 2 interrupt Flag */
+#define TIM_SR_CC3IF 0x0008U /*!<Capture/Compare 3 interrupt Flag */
+#define TIM_SR_CC4IF 0x0010U /*!<Capture/Compare 4 interrupt Flag */
+#define TIM_SR_COMIF 0x0020U /*!<COM interrupt Flag */
+#define TIM_SR_TIF 0x0040U /*!<Trigger interrupt Flag */
+#define TIM_SR_BIF 0x0080U /*!<Break interrupt Flag */
+#define TIM_SR_CC1OF 0x0200U /*!<Capture/Compare 1 Overcapture Flag */
+#define TIM_SR_CC2OF 0x0400U /*!<Capture/Compare 2 Overcapture Flag */
+#define TIM_SR_CC3OF 0x0800U /*!<Capture/Compare 3 Overcapture Flag */
+#define TIM_SR_CC4OF 0x1000U /*!<Capture/Compare 4 Overcapture Flag */
+
+/******************* Bit definition for TIM_EGR register ********************/
+#define TIM_EGR_UG 0x01U /*!<Update Generation */
+#define TIM_EGR_CC1G 0x02U /*!<Capture/Compare 1 Generation */
+#define TIM_EGR_CC2G 0x04U /*!<Capture/Compare 2 Generation */
+#define TIM_EGR_CC3G 0x08U /*!<Capture/Compare 3 Generation */
+#define TIM_EGR_CC4G 0x10U /*!<Capture/Compare 4 Generation */
+#define TIM_EGR_COMG 0x20U /*!<Capture/Compare Control Update Generation */
+#define TIM_EGR_TG 0x40U /*!<Trigger Generation */
+#define TIM_EGR_BG 0x80U /*!<Break Generation */
+
+/****************** Bit definition for TIM_CCMR1 register *******************/
+#define TIM_CCMR1_CC1S 0x0003U /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
+#define TIM_CCMR1_CC1S_0 0x0001U /*!<Bit 0 */
+#define TIM_CCMR1_CC1S_1 0x0002U /*!<Bit 1 */
+
+#define TIM_CCMR1_OC1FE 0x0004U /*!<Output Compare 1 Fast enable */
+#define TIM_CCMR1_OC1PE 0x0008U /*!<Output Compare 1 Preload enable */
+
+#define TIM_CCMR1_OC1M 0x0070U /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
+#define TIM_CCMR1_OC1M_0 0x0010U /*!<Bit 0 */
+#define TIM_CCMR1_OC1M_1 0x0020U /*!<Bit 1 */
+#define TIM_CCMR1_OC1M_2 0x0040U /*!<Bit 2 */
+
+#define TIM_CCMR1_OC1CE 0x0080U /*!<Output Compare 1Clear Enable */
+
+#define TIM_CCMR1_CC2S 0x0300U /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
+#define TIM_CCMR1_CC2S_0 0x0100U /*!<Bit 0 */
+#define TIM_CCMR1_CC2S_1 0x0200U /*!<Bit 1 */
+
+#define TIM_CCMR1_OC2FE 0x0400U /*!<Output Compare 2 Fast enable */
+#define TIM_CCMR1_OC2PE 0x0800U /*!<Output Compare 2 Preload enable */
+
+#define TIM_CCMR1_OC2M 0x7000U /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
+#define TIM_CCMR1_OC2M_0 0x1000U /*!<Bit 0 */
+#define TIM_CCMR1_OC2M_1 0x2000U /*!<Bit 1 */
+#define TIM_CCMR1_OC2M_2 0x4000U /*!<Bit 2 */
+
+#define TIM_CCMR1_OC2CE 0x8000U /*!<Output Compare 2 Clear Enable */
+
+/*----------------------------------------------------------------------------*/
+
+#define TIM_CCMR1_IC1PSC 0x000CU /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
+#define TIM_CCMR1_IC1PSC_0 0x0004U /*!<Bit 0 */
+#define TIM_CCMR1_IC1PSC_1 0x0008U /*!<Bit 1 */
+
+#define TIM_CCMR1_IC1F 0x00F0U /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
+#define TIM_CCMR1_IC1F_0 0x0010U /*!<Bit 0 */
+#define TIM_CCMR1_IC1F_1 0x0020U /*!<Bit 1 */
+#define TIM_CCMR1_IC1F_2 0x0040U /*!<Bit 2 */
+#define TIM_CCMR1_IC1F_3 0x0080U /*!<Bit 3 */
+
+#define TIM_CCMR1_IC2PSC 0x0C00U /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
+#define TIM_CCMR1_IC2PSC_0 0x0400U /*!<Bit 0 */
+#define TIM_CCMR1_IC2PSC_1 0x0800U /*!<Bit 1 */
+
+#define TIM_CCMR1_IC2F 0xF000U /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
+#define TIM_CCMR1_IC2F_0 0x1000U /*!<Bit 0 */
+#define TIM_CCMR1_IC2F_1 0x2000U /*!<Bit 1 */
+#define TIM_CCMR1_IC2F_2 0x4000U /*!<Bit 2 */
+#define TIM_CCMR1_IC2F_3 0x8000U /*!<Bit 3 */
+
+/****************** Bit definition for TIM_CCMR2 register *******************/
+#define TIM_CCMR2_CC3S 0x0003U /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
+#define TIM_CCMR2_CC3S_0 0x0001U /*!<Bit 0 */
+#define TIM_CCMR2_CC3S_1 0x0002U /*!<Bit 1 */
+
+#define TIM_CCMR2_OC3FE 0x0004U /*!<Output Compare 3 Fast enable */
+#define TIM_CCMR2_OC3PE 0x0008U /*!<Output Compare 3 Preload enable */
+
+#define TIM_CCMR2_OC3M 0x0070U /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
+#define TIM_CCMR2_OC3M_0 0x0010U /*!<Bit 0 */
+#define TIM_CCMR2_OC3M_1 0x0020U /*!<Bit 1 */
+#define TIM_CCMR2_OC3M_2 0x0040U /*!<Bit 2 */
+
+#define TIM_CCMR2_OC3CE 0x0080U /*!<Output Compare 3 Clear Enable */
+
+#define TIM_CCMR2_CC4S 0x0300U /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
+#define TIM_CCMR2_CC4S_0 0x0100U /*!<Bit 0 */
+#define TIM_CCMR2_CC4S_1 0x0200U /*!<Bit 1 */
+
+#define TIM_CCMR2_OC4FE 0x0400U /*!<Output Compare 4 Fast enable */
+#define TIM_CCMR2_OC4PE 0x0800U /*!<Output Compare 4 Preload enable */
+
+#define TIM_CCMR2_OC4M 0x7000U /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
+#define TIM_CCMR2_OC4M_0 0x1000U /*!<Bit 0 */
+#define TIM_CCMR2_OC4M_1 0x2000U /*!<Bit 1 */
+#define TIM_CCMR2_OC4M_2 0x4000U /*!<Bit 2 */
+
+#define TIM_CCMR2_OC4CE 0x8000U /*!<Output Compare 4 Clear Enable */
+
+/*----------------------------------------------------------------------------*/
+
+#define TIM_CCMR2_IC3PSC 0x000CU /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
+#define TIM_CCMR2_IC3PSC_0 0x0004U /*!<Bit 0 */
+#define TIM_CCMR2_IC3PSC_1 0x0008U /*!<Bit 1 */
+
+#define TIM_CCMR2_IC3F 0x00F0U /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
+#define TIM_CCMR2_IC3F_0 0x0010U /*!<Bit 0 */
+#define TIM_CCMR2_IC3F_1 0x0020U /*!<Bit 1 */
+#define TIM_CCMR2_IC3F_2 0x0040U /*!<Bit 2 */
+#define TIM_CCMR2_IC3F_3 0x0080U /*!<Bit 3 */
+
+#define TIM_CCMR2_IC4PSC 0x0C00U /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
+#define TIM_CCMR2_IC4PSC_0 0x0400U /*!<Bit 0 */
+#define TIM_CCMR2_IC4PSC_1 0x0800U /*!<Bit 1 */
+
+#define TIM_CCMR2_IC4F 0xF000U /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
+#define TIM_CCMR2_IC4F_0 0x1000U /*!<Bit 0 */
+#define TIM_CCMR2_IC4F_1 0x2000U /*!<Bit 1 */
+#define TIM_CCMR2_IC4F_2 0x4000U /*!<Bit 2 */
+#define TIM_CCMR2_IC4F_3 0x8000U /*!<Bit 3 */
+
+/******************* Bit definition for TIM_CCER register *******************/
+#define TIM_CCER_CC1E 0x0001U /*!<Capture/Compare 1 output enable */
+#define TIM_CCER_CC1P 0x0002U /*!<Capture/Compare 1 output Polarity */
+#define TIM_CCER_CC1NE 0x0004U /*!<Capture/Compare 1 Complementary output enable */
+#define TIM_CCER_CC1NP 0x0008U /*!<Capture/Compare 1 Complementary output Polarity */
+#define TIM_CCER_CC2E 0x0010U /*!<Capture/Compare 2 output enable */
+#define TIM_CCER_CC2P 0x0020U /*!<Capture/Compare 2 output Polarity */
+#define TIM_CCER_CC2NE 0x0040U /*!<Capture/Compare 2 Complementary output enable */
+#define TIM_CCER_CC2NP 0x0080U /*!<Capture/Compare 2 Complementary output Polarity */
+#define TIM_CCER_CC3E 0x0100U /*!<Capture/Compare 3 output enable */
+#define TIM_CCER_CC3P 0x0200U /*!<Capture/Compare 3 output Polarity */
+#define TIM_CCER_CC3NE 0x0400U /*!<Capture/Compare 3 Complementary output enable */
+#define TIM_CCER_CC3NP 0x0800U /*!<Capture/Compare 3 Complementary output Polarity */
+#define TIM_CCER_CC4E 0x1000U /*!<Capture/Compare 4 output enable */
+#define TIM_CCER_CC4P 0x2000U /*!<Capture/Compare 4 output Polarity */
+#define TIM_CCER_CC4NP 0x8000U /*!<Capture/Compare 4 Complementary output Polarity */
+
+/******************* Bit definition for TIM_CNT register ********************/
+#define TIM_CNT_CNT 0xFFFFU /*!<Counter Value */
+
+/******************* Bit definition for TIM_PSC register ********************/
+#define TIM_PSC_PSC 0xFFFFU /*!<Prescaler Value */
+
+/******************* Bit definition for TIM_ARR register ********************/
+#define TIM_ARR_ARR 0xFFFFU /*!<actual auto-reload Value */
+
+/******************* Bit definition for TIM_RCR register ********************/
+#define TIM_RCR_REP 0xFFU /*!<Repetition Counter Value */
+
+/******************* Bit definition for TIM_CCR1 register *******************/
+#define TIM_CCR1_CCR1 0xFFFFU /*!<Capture/Compare 1 Value */
+
+/******************* Bit definition for TIM_CCR2 register *******************/
+#define TIM_CCR2_CCR2 0xFFFFU /*!<Capture/Compare 2 Value */
+
+/******************* Bit definition for TIM_CCR3 register *******************/
+#define TIM_CCR3_CCR3 0xFFFFU /*!<Capture/Compare 3 Value */
+
+/******************* Bit definition for TIM_CCR4 register *******************/
+#define TIM_CCR4_CCR4 0xFFFFU /*!<Capture/Compare 4 Value */
+
+/******************* Bit definition for TIM_BDTR register *******************/
+#define TIM_BDTR_DTG 0x00FFU /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
+#define TIM_BDTR_DTG_0 0x0001U /*!<Bit 0 */
+#define TIM_BDTR_DTG_1 0x0002U /*!<Bit 1 */
+#define TIM_BDTR_DTG_2 0x0004U /*!<Bit 2 */
+#define TIM_BDTR_DTG_3 0x0008U /*!<Bit 3 */
+#define TIM_BDTR_DTG_4 0x0010U /*!<Bit 4 */
+#define TIM_BDTR_DTG_5 0x0020U /*!<Bit 5 */
+#define TIM_BDTR_DTG_6 0x0040U /*!<Bit 6 */
+#define TIM_BDTR_DTG_7 0x0080U /*!<Bit 7 */
+
+#define TIM_BDTR_LOCK 0x0300U /*!<LOCK[1:0] bits (Lock Configuration) */
+#define TIM_BDTR_LOCK_0 0x0100U /*!<Bit 0 */
+#define TIM_BDTR_LOCK_1 0x0200U /*!<Bit 1 */
+
+#define TIM_BDTR_OSSI 0x0400U /*!<Off-State Selection for Idle mode */
+#define TIM_BDTR_OSSR 0x0800U /*!<Off-State Selection for Run mode */
+#define TIM_BDTR_BKE 0x1000U /*!<Break enable */
+#define TIM_BDTR_BKP 0x2000U /*!<Break Polarity */
+#define TIM_BDTR_AOE 0x4000U /*!<Automatic Output enable */
+#define TIM_BDTR_MOE 0x8000U /*!<Main Output enable */
+
+/******************* Bit definition for TIM_DCR register ********************/
+#define TIM_DCR_DBA 0x001FU /*!<DBA[4:0] bits (DMA Base Address) */
+#define TIM_DCR_DBA_0 0x0001U /*!<Bit 0 */
+#define TIM_DCR_DBA_1 0x0002U /*!<Bit 1 */
+#define TIM_DCR_DBA_2 0x0004U /*!<Bit 2 */
+#define TIM_DCR_DBA_3 0x0008U /*!<Bit 3 */
+#define TIM_DCR_DBA_4 0x0010U /*!<Bit 4 */
+
+#define TIM_DCR_DBL 0x1F00U /*!<DBL[4:0] bits (DMA Burst Length) */
+#define TIM_DCR_DBL_0 0x0100U /*!<Bit 0 */
+#define TIM_DCR_DBL_1 0x0200U /*!<Bit 1 */
+#define TIM_DCR_DBL_2 0x0400U /*!<Bit 2 */
+#define TIM_DCR_DBL_3 0x0800U /*!<Bit 3 */
+#define TIM_DCR_DBL_4 0x1000U /*!<Bit 4 */
+
+/******************* Bit definition for TIM_DMAR register *******************/
+#define TIM_DMAR_DMAB 0xFFFFU /*!<DMA register for burst accesses */
+
+/******************* Bit definition for TIM_OR register *********************/
+#define TIM_OR_TI4_RMP 0x00C0U /*!<TI4_RMP[1:0] bits (TIM5 Input 4 remap) */
+#define TIM_OR_TI4_RMP_0 0x0040U /*!<Bit 0 */
+#define TIM_OR_TI4_RMP_1 0x0080U /*!<Bit 1 */
+#define TIM_OR_ITR1_RMP 0x0C00U /*!<ITR1_RMP[1:0] bits (TIM2 Internal trigger 1 remap) */
+#define TIM_OR_ITR1_RMP_0 0x0400U /*!<Bit 0 */
+#define TIM_OR_ITR1_RMP_1 0x0800U /*!<Bit 1 */
+
+
+/******************************************************************************/
+/* */
+/* Universal Synchronous Asynchronous Receiver Transmitter */
+/* */
+/******************************************************************************/
+/******************* Bit definition for USART_SR register *******************/
+#define USART_SR_PE 0x0001U /*!<Parity Error */
+#define USART_SR_FE 0x0002U /*!<Framing Error */
+#define USART_SR_NE 0x0004U /*!<Noise Error Flag */
+#define USART_SR_ORE 0x0008U /*!<OverRun Error */
+#define USART_SR_IDLE 0x0010U /*!<IDLE line detected */
+#define USART_SR_RXNE 0x0020U /*!<Read Data Register Not Empty */
+#define USART_SR_TC 0x0040U /*!<Transmission Complete */
+#define USART_SR_TXE 0x0080U /*!<Transmit Data Register Empty */
+#define USART_SR_LBD 0x0100U /*!<LIN Break Detection Flag */
+#define USART_SR_CTS 0x0200U /*!<CTS Flag */
+
+/******************* Bit definition for USART_DR register *******************/
+#define USART_DR_DR 0x01FFU /*!<Data value */
+
+/****************** Bit definition for USART_BRR register *******************/
+#define USART_BRR_DIV_Fraction 0x000FU /*!<Fraction of USARTDIV */
+#define USART_BRR_DIV_Mantissa 0xFFF0U /*!<Mantissa of USARTDIV */
+
+/****************** Bit definition for USART_CR1 register *******************/
+#define USART_CR1_SBK 0x0001U /*!<Send Break */
+#define USART_CR1_RWU 0x0002U /*!<Receiver wakeup */
+#define USART_CR1_RE 0x0004U /*!<Receiver Enable */
+#define USART_CR1_TE 0x0008U /*!<Transmitter Enable */
+#define USART_CR1_IDLEIE 0x0010U /*!<IDLE Interrupt Enable */
+#define USART_CR1_RXNEIE 0x0020U /*!<RXNE Interrupt Enable */
+#define USART_CR1_TCIE 0x0040U /*!<Transmission Complete Interrupt Enable */
+#define USART_CR1_TXEIE 0x0080U /*!<PE Interrupt Enable */
+#define USART_CR1_PEIE 0x0100U /*!<PE Interrupt Enable */
+#define USART_CR1_PS 0x0200U /*!<Parity Selection */
+#define USART_CR1_PCE 0x0400U /*!<Parity Control Enable */
+#define USART_CR1_WAKE 0x0800U /*!<Wakeup method */
+#define USART_CR1_M 0x1000U /*!<Word length */
+#define USART_CR1_UE 0x2000U /*!<USART Enable */
+#define USART_CR1_OVER8 0x8000U /*!<USART Oversampling by 8 enable */
+
+/****************** Bit definition for USART_CR2 register *******************/
+#define USART_CR2_ADD 0x000FU /*!<Address of the USART node */
+#define USART_CR2_LBDL 0x0020U /*!<LIN Break Detection Length */
+#define USART_CR2_LBDIE 0x0040U /*!<LIN Break Detection Interrupt Enable */
+#define USART_CR2_LBCL 0x0100U /*!<Last Bit Clock pulse */
+#define USART_CR2_CPHA 0x0200U /*!<Clock Phase */
+#define USART_CR2_CPOL 0x0400U /*!<Clock Polarity */
+#define USART_CR2_CLKEN 0x0800U /*!<Clock Enable */
+
+#define USART_CR2_STOP 0x3000U /*!<STOP[1:0] bits (STOP bits) */
+#define USART_CR2_STOP_0 0x1000U /*!<Bit 0 */
+#define USART_CR2_STOP_1 0x2000U /*!<Bit 1 */
+
+#define USART_CR2_LINEN 0x4000U /*!<LIN mode enable */
+
+/****************** Bit definition for USART_CR3 register *******************/
+#define USART_CR3_EIE 0x0001U /*!<Error Interrupt Enable */
+#define USART_CR3_IREN 0x0002U /*!<IrDA mode Enable */
+#define USART_CR3_IRLP 0x0004U /*!<IrDA Low-Power */
+#define USART_CR3_HDSEL 0x0008U /*!<Half-Duplex Selection */
+#define USART_CR3_NACK 0x0010U /*!<Smartcard NACK enable */
+#define USART_CR3_SCEN 0x0020U /*!<Smartcard mode enable */
+#define USART_CR3_DMAR 0x0040U /*!<DMA Enable Receiver */
+#define USART_CR3_DMAT 0x0080U /*!<DMA Enable Transmitter */
+#define USART_CR3_RTSE 0x0100U /*!<RTS Enable */
+#define USART_CR3_CTSE 0x0200U /*!<CTS Enable */
+#define USART_CR3_CTSIE 0x0400U /*!<CTS Interrupt Enable */
+#define USART_CR3_ONEBIT 0x0800U /*!<USART One bit method enable */
+
+/****************** Bit definition for USART_GTPR register ******************/
+#define USART_GTPR_PSC 0x00FFU /*!<PSC[7:0] bits (Prescaler value) */
+#define USART_GTPR_PSC_0 0x0001U /*!<Bit 0 */
+#define USART_GTPR_PSC_1 0x0002U /*!<Bit 1 */
+#define USART_GTPR_PSC_2 0x0004U /*!<Bit 2 */
+#define USART_GTPR_PSC_3 0x0008U /*!<Bit 3 */
+#define USART_GTPR_PSC_4 0x0010U /*!<Bit 4 */
+#define USART_GTPR_PSC_5 0x0020U /*!<Bit 5 */
+#define USART_GTPR_PSC_6 0x0040U /*!<Bit 6 */
+#define USART_GTPR_PSC_7 0x0080U /*!<Bit 7 */
+
+#define USART_GTPR_GT 0xFF00U /*!<Guard time value */
+
+/******************************************************************************/
+/* */
+/* Window WATCHDOG */
+/* */
+/******************************************************************************/
+/******************* Bit definition for WWDG_CR register ********************/
+#define WWDG_CR_T 0x7FU /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
+#define WWDG_CR_T_0 0x01U /*!<Bit 0 */
+#define WWDG_CR_T_1 0x02U /*!<Bit 1 */
+#define WWDG_CR_T_2 0x04U /*!<Bit 2 */
+#define WWDG_CR_T_3 0x08U /*!<Bit 3 */
+#define WWDG_CR_T_4 0x10U /*!<Bit 4 */
+#define WWDG_CR_T_5 0x20U /*!<Bit 5 */
+#define WWDG_CR_T_6 0x40U /*!<Bit 6 */
+/* Legacy defines */
+#define WWDG_CR_T0 WWDG_CR_T_0
+#define WWDG_CR_T1 WWDG_CR_T_1
+#define WWDG_CR_T2 WWDG_CR_T_2
+#define WWDG_CR_T3 WWDG_CR_T_3
+#define WWDG_CR_T4 WWDG_CR_T_4
+#define WWDG_CR_T5 WWDG_CR_T_5
+#define WWDG_CR_T6 WWDG_CR_T_6
+
+#define WWDG_CR_WDGA 0x80U /*!<Activation bit */
+
+/******************* Bit definition for WWDG_CFR register *******************/
+#define WWDG_CFR_W 0x007FU /*!<W[6:0] bits (7-bit window value) */
+#define WWDG_CFR_W_0 0x0001U /*!<Bit 0 */
+#define WWDG_CFR_W_1 0x0002U /*!<Bit 1 */
+#define WWDG_CFR_W_2 0x0004U /*!<Bit 2 */
+#define WWDG_CFR_W_3 0x0008U /*!<Bit 3 */
+#define WWDG_CFR_W_4 0x0010U /*!<Bit 4 */
+#define WWDG_CFR_W_5 0x0020U /*!<Bit 5 */
+#define WWDG_CFR_W_6 0x0040U /*!<Bit 6 */
+/* Legacy defines */
+#define WWDG_CFR_W0 WWDG_CFR_W_0
+#define WWDG_CFR_W1 WWDG_CFR_W_1
+#define WWDG_CFR_W2 WWDG_CFR_W_2
+#define WWDG_CFR_W3 WWDG_CFR_W_3
+#define WWDG_CFR_W4 WWDG_CFR_W_4
+#define WWDG_CFR_W5 WWDG_CFR_W_5
+#define WWDG_CFR_W6 WWDG_CFR_W_6
+
+#define WWDG_CFR_WDGTB 0x0180U /*!<WDGTB[1:0] bits (Timer Base) */
+#define WWDG_CFR_WDGTB_0 0x0080U /*!<Bit 0 */
+#define WWDG_CFR_WDGTB_1 0x0100U /*!<Bit 1 */
+/* Legacy defines */
+#define WWDG_CFR_WDGTB0 WWDG_CFR_WDGTB_0
+#define WWDG_CFR_WDGTB1 WWDG_CFR_WDGTB_1
+
+#define WWDG_CFR_EWI 0x0200U /*!<Early Wakeup Interrupt */
+
+/******************* Bit definition for WWDG_SR register ********************/
+#define WWDG_SR_EWIF 0x01U /*!<Early Wakeup Interrupt Flag */
+
+
+/******************************************************************************/
+/* */
+/* DBG */
+/* */
+/******************************************************************************/
+/******************** Bit definition for DBGMCU_IDCODE register *************/
+#define DBGMCU_IDCODE_DEV_ID 0x00000FFFU
+#define DBGMCU_IDCODE_REV_ID 0xFFFF0000U
+
+/******************** Bit definition for DBGMCU_CR register *****************/
+#define DBGMCU_CR_DBG_SLEEP 0x00000001U
+#define DBGMCU_CR_DBG_STOP 0x00000002U
+#define DBGMCU_CR_DBG_STANDBY 0x00000004U
+#define DBGMCU_CR_TRACE_IOEN 0x00000020U
+
+#define DBGMCU_CR_TRACE_MODE 0x000000C0U
+#define DBGMCU_CR_TRACE_MODE_0 0x00000040U/*!<Bit 0 */
+#define DBGMCU_CR_TRACE_MODE_1 0x00000080U/*!<Bit 1 */
+
+/******************** Bit definition for DBGMCU_APB1_FZ register ************/
+#define DBGMCU_APB1_FZ_DBG_TIM2_STOP 0x00000001U
+#define DBGMCU_APB1_FZ_DBG_TIM3_STOP 0x00000002U
+#define DBGMCU_APB1_FZ_DBG_TIM4_STOP 0x00000004U
+#define DBGMCU_APB1_FZ_DBG_TIM5_STOP 0x00000008U
+#define DBGMCU_APB1_FZ_DBG_TIM6_STOP 0x00000010U
+#define DBGMCU_APB1_FZ_DBG_TIM7_STOP 0x00000020U
+#define DBGMCU_APB1_FZ_DBG_TIM12_STOP 0x00000040U
+#define DBGMCU_APB1_FZ_DBG_TIM13_STOP 0x00000080U
+#define DBGMCU_APB1_FZ_DBG_TIM14_STOP 0x00000100U
+#define DBGMCU_APB1_FZ_DBG_RTC_STOP 0x00000400U
+#define DBGMCU_APB1_FZ_DBG_WWDG_STOP 0x00000800U
+#define DBGMCU_APB1_FZ_DBG_IWDG_STOP 0x00001000U
+#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT 0x00200000U
+#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT 0x00400000U
+#define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT 0x00800000U
+#define DBGMCU_APB1_FZ_DBG_CAN1_STOP 0x02000000U
+#define DBGMCU_APB1_FZ_DBG_CAN2_STOP 0x04000000U
+
+/******************** Bit definition for DBGMCU_APB2_FZ register ************/
+#define DBGMCU_APB2_FZ_DBG_TIM1_STOP 0x00000001U
+#define DBGMCU_APB2_FZ_DBG_TIM8_STOP 0x00000002U
+#define DBGMCU_APB2_FZ_DBG_TIM9_STOP 0x00010000U
+#define DBGMCU_APB2_FZ_DBG_TIM10_STOP 0x00020000U
+#define DBGMCU_APB2_FZ_DBG_TIM11_STOP 0x00040000U
+
+/******************************************************************************/
+/* */
+/* USB_OTG */
+/* */
+/******************************************************************************/
+/******************** Bit definition for USB_OTG_GOTGCTL register ***********/
+#define USB_OTG_GOTGCTL_SRQSCS 0x00000001U /*!< Session request success */
+#define USB_OTG_GOTGCTL_SRQ 0x00000002U /*!< Session request */
+#define USB_OTG_GOTGCTL_VBVALOEN 0x00000004U /*!< VBUS valid override enable */
+#define USB_OTG_GOTGCTL_VBVALOVAL 0x00000008U /*!< VBUS valid override value */
+#define USB_OTG_GOTGCTL_AVALOEN 0x00000010U /*!< A-peripheral session valid override enable */
+#define USB_OTG_GOTGCTL_AVALOVAL 0x00000020U /*!< A-peripheral session valid override value */
+#define USB_OTG_GOTGCTL_BVALOEN 0x00000040U /*!< B-peripheral session valid override enable */
+#define USB_OTG_GOTGCTL_BVALOVAL 0x00000080U /*!< B-peripheral session valid override value */
+#define USB_OTG_GOTGCTL_HNGSCS 0x00000100U /*!< Host set HNP enable */
+#define USB_OTG_GOTGCTL_HNPRQ 0x00000200U /*!< HNP request */
+#define USB_OTG_GOTGCTL_HSHNPEN 0x00000400U /*!< Host set HNP enable */
+#define USB_OTG_GOTGCTL_DHNPEN 0x00000800U /*!< Device HNP enabled */
+#define USB_OTG_GOTGCTL_EHEN 0x00001000U /*!< Embedded host enable */
+#define USB_OTG_GOTGCTL_CIDSTS 0x00010000U /*!< Connector ID status */
+#define USB_OTG_GOTGCTL_DBCT 0x00020000U /*!< Long/short debounce time */
+#define USB_OTG_GOTGCTL_ASVLD 0x00040000U /*!< A-session valid */
+#define USB_OTG_GOTGCTL_BSESVLD 0x00080000U /*!< B-session valid */
+#define USB_OTG_GOTGCTL_OTGVER 0x00100000U /*!< OTG version */
+
+/******************** Bit definition for USB_OTG_HCFG register **************/
+
+#define USB_OTG_HCFG_FSLSPCS 0x00000003U /*!< FS/LS PHY clock select */
+#define USB_OTG_HCFG_FSLSPCS_0 0x00000001U /*!<Bit 0 */
+#define USB_OTG_HCFG_FSLSPCS_1 0x00000002U /*!<Bit 1 */
+#define USB_OTG_HCFG_FSLSS 0x00000004U /*!< FS- and LS-only support */
+
+/******************** Bit definition for USB_OTG_DCFG register **************/
+
+#define USB_OTG_DCFG_DSPD 0x00000003U /*!< Device speed */
+#define USB_OTG_DCFG_DSPD_0 0x00000001U /*!<Bit 0 */
+#define USB_OTG_DCFG_DSPD_1 0x00000002U /*!<Bit 1 */
+#define USB_OTG_DCFG_NZLSOHSK 0x00000004U /*!< Nonzero-length status OUT handshake */
+
+#define USB_OTG_DCFG_DAD 0x000007F0U /*!< Device address */
+#define USB_OTG_DCFG_DAD_0 0x00000010U /*!<Bit 0 */
+#define USB_OTG_DCFG_DAD_1 0x00000020U /*!<Bit 1 */
+#define USB_OTG_DCFG_DAD_2 0x00000040U /*!<Bit 2 */
+#define USB_OTG_DCFG_DAD_3 0x00000080U /*!<Bit 3 */
+#define USB_OTG_DCFG_DAD_4 0x00000100U /*!<Bit 4 */
+#define USB_OTG_DCFG_DAD_5 0x00000200U /*!<Bit 5 */
+#define USB_OTG_DCFG_DAD_6 0x00000400U /*!<Bit 6 */
+
+#define USB_OTG_DCFG_PFIVL 0x00001800U /*!< Periodic (micro)frame interval */
+#define USB_OTG_DCFG_PFIVL_0 0x00000800U /*!<Bit 0 */
+#define USB_OTG_DCFG_PFIVL_1 0x00001000U /*!<Bit 1 */
+
+#define USB_OTG_DCFG_PERSCHIVL 0x03000000U /*!< Periodic scheduling interval */
+#define USB_OTG_DCFG_PERSCHIVL_0 0x01000000U /*!<Bit 0 */
+#define USB_OTG_DCFG_PERSCHIVL_1 0x02000000U /*!<Bit 1 */
+
+/******************** Bit definition for USB_OTG_PCGCR register *************/
+#define USB_OTG_PCGCR_STPPCLK 0x00000001U /*!< Stop PHY clock */
+#define USB_OTG_PCGCR_GATEHCLK 0x00000002U /*!< Gate HCLK */
+#define USB_OTG_PCGCR_PHYSUSP 0x00000010U /*!< PHY suspended */
+
+/******************** Bit definition for USB_OTG_GOTGINT register ***********/
+#define USB_OTG_GOTGINT_SEDET 0x00000004U /*!< Session end detected */
+#define USB_OTG_GOTGINT_SRSSCHG 0x00000100U /*!< Session request success status change */
+#define USB_OTG_GOTGINT_HNSSCHG 0x00000200U /*!< Host negotiation success status change */
+#define USB_OTG_GOTGINT_HNGDET 0x00020000U /*!< Host negotiation detected */
+#define USB_OTG_GOTGINT_ADTOCHG 0x00040000U /*!< A-device timeout change */
+#define USB_OTG_GOTGINT_DBCDNE 0x00080000U /*!< Debounce done */
+#define USB_OTG_GOTGINT_IDCHNG 0x00100000U /*!< Change in ID pin input value */
+
+/******************** Bit definition for USB_OTG_DCTL register **************/
+#define USB_OTG_DCTL_RWUSIG 0x00000001U /*!< Remote wakeup signaling */
+#define USB_OTG_DCTL_SDIS 0x00000002U /*!< Soft disconnect */
+#define USB_OTG_DCTL_GINSTS 0x00000004U /*!< Global IN NAK status */
+#define USB_OTG_DCTL_GONSTS 0x00000008U /*!< Global OUT NAK status */
+#define USB_OTG_DCTL_TCTL 0x00000070U /*!< Test control */
+#define USB_OTG_DCTL_TCTL_0 0x00000010U /*!<Bit 0 */
+#define USB_OTG_DCTL_TCTL_1 0x00000020U /*!<Bit 1 */
+#define USB_OTG_DCTL_TCTL_2 0x00000040U /*!<Bit 2 */
+#define USB_OTG_DCTL_SGINAK 0x00000080U /*!< Set global IN NAK */
+#define USB_OTG_DCTL_CGINAK 0x00000100U /*!< Clear global IN NAK */
+#define USB_OTG_DCTL_SGONAK 0x00000200U /*!< Set global OUT NAK */
+#define USB_OTG_DCTL_CGONAK 0x00000400U /*!< Clear global OUT NAK */
+#define USB_OTG_DCTL_POPRGDNE 0x00000800U /*!< Power-on programming done */
+
+/******************** Bit definition for USB_OTG_HFIR register **************/
+#define USB_OTG_HFIR_FRIVL 0x0000FFFFU /*!< Frame interval */
+
+/******************** Bit definition for USB_OTG_HFNUM register *************/
+#define USB_OTG_HFNUM_FRNUM 0x0000FFFFU /*!< Frame number */
+#define USB_OTG_HFNUM_FTREM 0xFFFF0000U /*!< Frame time remaining */
+
+/******************** Bit definition for USB_OTG_DSTS register **************/
+#define USB_OTG_DSTS_SUSPSTS 0x00000001U /*!< Suspend status */
+
+#define USB_OTG_DSTS_ENUMSPD 0x00000006U /*!< Enumerated speed */
+#define USB_OTG_DSTS_ENUMSPD_0 0x00000002U /*!<Bit 0 */
+#define USB_OTG_DSTS_ENUMSPD_1 0x00000004U /*!<Bit 1 */
+#define USB_OTG_DSTS_EERR 0x00000008U /*!< Erratic error */
+#define USB_OTG_DSTS_FNSOF 0x003FFF00U /*!< Frame number of the received SOF */
+
+/******************** Bit definition for USB_OTG_GAHBCFG register ***********/
+#define USB_OTG_GAHBCFG_GINT 0x00000001U /*!< Global interrupt mask */
+#define USB_OTG_GAHBCFG_HBSTLEN 0x0000001EU /*!< Burst length/type */
+#define USB_OTG_GAHBCFG_HBSTLEN_0 0x00000002U /*!<Bit 0 */
+#define USB_OTG_GAHBCFG_HBSTLEN_1 0x00000004U /*!<Bit 1 */
+#define USB_OTG_GAHBCFG_HBSTLEN_2 0x00000008U /*!<Bit 2 */
+#define USB_OTG_GAHBCFG_HBSTLEN_3 0x00000010U /*!<Bit 3 */
+#define USB_OTG_GAHBCFG_DMAEN 0x00000020U /*!< DMA enable */
+#define USB_OTG_GAHBCFG_TXFELVL 0x00000080U /*!< TxFIFO empty level */
+#define USB_OTG_GAHBCFG_PTXFELVL 0x00000100U /*!< Periodic TxFIFO empty level */
+
+/******************** Bit definition for USB_OTG_GUSBCFG register ***********/
+#define USB_OTG_GUSBCFG_TOCAL 0x00000007U /*!< FS timeout calibration */
+#define USB_OTG_GUSBCFG_TOCAL_0 0x00000001U /*!<Bit 0 */
+#define USB_OTG_GUSBCFG_TOCAL_1 0x00000002U /*!<Bit 1 */
+#define USB_OTG_GUSBCFG_TOCAL_2 0x00000004U /*!<Bit 2 */
+#define USB_OTG_GUSBCFG_PHYSEL 0x00000040U /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */
+#define USB_OTG_GUSBCFG_SRPCAP 0x00000100U /*!< SRP-capable */
+#define USB_OTG_GUSBCFG_HNPCAP 0x00000200U /*!< HNP-capable */
+
+#define USB_OTG_GUSBCFG_TRDT 0x00003C00U /*!< USB turnaround time */
+#define USB_OTG_GUSBCFG_TRDT_0 0x00000400U /*!<Bit 0 */
+#define USB_OTG_GUSBCFG_TRDT_1 0x00000800U /*!<Bit 1 */
+#define USB_OTG_GUSBCFG_TRDT_2 0x00001000U /*!<Bit 2 */
+#define USB_OTG_GUSBCFG_TRDT_3 0x00002000U /*!<Bit 3 */
+#define USB_OTG_GUSBCFG_PHYLPCS 0x00008000U /*!< PHY Low-power clock select */
+#define USB_OTG_GUSBCFG_ULPIFSLS 0x00020000U /*!< ULPI FS/LS select */
+#define USB_OTG_GUSBCFG_ULPIAR 0x00040000U /*!< ULPI Auto-resume */
+#define USB_OTG_GUSBCFG_ULPICSM 0x00080000U /*!< ULPI Clock SuspendM */
+#define USB_OTG_GUSBCFG_ULPIEVBUSD 0x00100000U /*!< ULPI External VBUS Drive */
+#define USB_OTG_GUSBCFG_ULPIEVBUSI 0x00200000U /*!< ULPI external VBUS indicator */
+#define USB_OTG_GUSBCFG_TSDPS 0x00400000U /*!< TermSel DLine pulsing selection */
+#define USB_OTG_GUSBCFG_PCCI 0x00800000U /*!< Indicator complement */
+#define USB_OTG_GUSBCFG_PTCI 0x01000000U /*!< Indicator pass through */
+#define USB_OTG_GUSBCFG_ULPIIPD 0x02000000U /*!< ULPI interface protect disable */
+#define USB_OTG_GUSBCFG_FHMOD 0x20000000U /*!< Forced host mode */
+#define USB_OTG_GUSBCFG_FDMOD 0x40000000U /*!< Forced peripheral mode */
+#define USB_OTG_GUSBCFG_CTXPKT 0x80000000U /*!< Corrupt Tx packet */
+
+/******************** Bit definition for USB_OTG_GRSTCTL register ***********/
+#define USB_OTG_GRSTCTL_CSRST 0x00000001U /*!< Core soft reset */
+#define USB_OTG_GRSTCTL_HSRST 0x00000002U /*!< HCLK soft reset */
+#define USB_OTG_GRSTCTL_FCRST 0x00000004U /*!< Host frame counter reset */
+#define USB_OTG_GRSTCTL_RXFFLSH 0x00000010U /*!< RxFIFO flush */
+#define USB_OTG_GRSTCTL_TXFFLSH 0x00000020U /*!< TxFIFO flush */
+
+#define USB_OTG_GRSTCTL_TXFNUM 0x000007C0U /*!< TxFIFO number */
+#define USB_OTG_GRSTCTL_TXFNUM_0 0x00000040U /*!<Bit 0 */
+#define USB_OTG_GRSTCTL_TXFNUM_1 0x00000080U /*!<Bit 1 */
+#define USB_OTG_GRSTCTL_TXFNUM_2 0x00000100U /*!<Bit 2 */
+#define USB_OTG_GRSTCTL_TXFNUM_3 0x00000200U /*!<Bit 3 */
+#define USB_OTG_GRSTCTL_TXFNUM_4 0x00000400U /*!<Bit 4 */
+#define USB_OTG_GRSTCTL_DMAREQ 0x40000000U /*!< DMA request signal */
+#define USB_OTG_GRSTCTL_AHBIDL 0x80000000U /*!< AHB master idle */
+
+/******************** Bit definition for USB_OTG_DIEPMSK register ***********/
+#define USB_OTG_DIEPMSK_XFRCM 0x00000001U /*!< Transfer completed interrupt mask */
+#define USB_OTG_DIEPMSK_EPDM 0x00000002U /*!< Endpoint disabled interrupt mask */
+#define USB_OTG_DIEPMSK_TOM 0x00000008U /*!< Timeout condition mask (nonisochronous endpoints) */
+#define USB_OTG_DIEPMSK_ITTXFEMSK 0x00000010U /*!< IN token received when TxFIFO empty mask */
+#define USB_OTG_DIEPMSK_INEPNMM 0x00000020U /*!< IN token received with EP mismatch mask */
+#define USB_OTG_DIEPMSK_INEPNEM 0x00000040U /*!< IN endpoint NAK effective mask */
+#define USB_OTG_DIEPMSK_TXFURM 0x00000100U /*!< FIFO underrun mask */
+#define USB_OTG_DIEPMSK_BIM 0x00000200U /*!< BNA interrupt mask */
+
+/******************** Bit definition for USB_OTG_HPTXSTS register ***********/
+#define USB_OTG_HPTXSTS_PTXFSAVL 0x0000FFFFU /*!< Periodic transmit data FIFO space available */
+
+#define USB_OTG_HPTXSTS_PTXQSAV 0x00FF0000U /*!< Periodic transmit request queue space available */
+#define USB_OTG_HPTXSTS_PTXQSAV_0 0x00010000U /*!<Bit 0 */
+#define USB_OTG_HPTXSTS_PTXQSAV_1 0x00020000U /*!<Bit 1 */
+#define USB_OTG_HPTXSTS_PTXQSAV_2 0x00040000U /*!<Bit 2 */
+#define USB_OTG_HPTXSTS_PTXQSAV_3 0x00080000U /*!<Bit 3 */
+#define USB_OTG_HPTXSTS_PTXQSAV_4 0x00100000U /*!<Bit 4 */
+#define USB_OTG_HPTXSTS_PTXQSAV_5 0x00200000U /*!<Bit 5 */
+#define USB_OTG_HPTXSTS_PTXQSAV_6 0x00400000U /*!<Bit 6 */
+#define USB_OTG_HPTXSTS_PTXQSAV_7 0x00800000U /*!<Bit 7 */
+
+#define USB_OTG_HPTXSTS_PTXQTOP 0xFF000000U /*!< Top of the periodic transmit request queue */
+#define USB_OTG_HPTXSTS_PTXQTOP_0 0x01000000U /*!<Bit 0 */
+#define USB_OTG_HPTXSTS_PTXQTOP_1 0x02000000U /*!<Bit 1 */
+#define USB_OTG_HPTXSTS_PTXQTOP_2 0x04000000U /*!<Bit 2 */
+#define USB_OTG_HPTXSTS_PTXQTOP_3 0x08000000U /*!<Bit 3 */
+#define USB_OTG_HPTXSTS_PTXQTOP_4 0x10000000U /*!<Bit 4 */
+#define USB_OTG_HPTXSTS_PTXQTOP_5 0x20000000U /*!<Bit 5 */
+#define USB_OTG_HPTXSTS_PTXQTOP_6 0x40000000U /*!<Bit 6 */
+#define USB_OTG_HPTXSTS_PTXQTOP_7 0x80000000U /*!<Bit 7 */
+
+/******************** Bit definition for USB_OTG_HAINT register *************/
+#define USB_OTG_HAINT_HAINT 0x0000FFFFU /*!< Channel interrupts */
+
+/******************** Bit definition for USB_OTG_DOEPMSK register ***********/
+#define USB_OTG_DOEPMSK_XFRCM 0x00000001U /*!< Transfer completed interrupt mask */
+#define USB_OTG_DOEPMSK_EPDM 0x00000002U /*!< Endpoint disabled interrupt mask */
+#define USB_OTG_DOEPMSK_STUPM 0x00000008U /*!< SETUP phase done mask */
+#define USB_OTG_DOEPMSK_OTEPDM 0x00000010U /*!< OUT token received when endpoint disabled mask */
+#define USB_OTG_DOEPMSK_OTEPSPRM 0x00000020U /*!< Status Phase Received mask */
+#define USB_OTG_DOEPMSK_B2BSTUP 0x00000040U /*!< Back-to-back SETUP packets received mask */
+#define USB_OTG_DOEPMSK_OPEM 0x00000100U /*!< OUT packet error mask */
+#define USB_OTG_DOEPMSK_BOIM 0x00000200U /*!< BNA interrupt mask */
+
+/******************** Bit definition for USB_OTG_GINTSTS register ***********/
+#define USB_OTG_GINTSTS_CMOD 0x00000001U /*!< Current mode of operation */
+#define USB_OTG_GINTSTS_MMIS 0x00000002U /*!< Mode mismatch interrupt */
+#define USB_OTG_GINTSTS_OTGINT 0x00000004U /*!< OTG interrupt */
+#define USB_OTG_GINTSTS_SOF 0x00000008U /*!< Start of frame */
+#define USB_OTG_GINTSTS_RXFLVL 0x00000010U /*!< RxFIFO nonempty */
+#define USB_OTG_GINTSTS_NPTXFE 0x00000020U /*!< Nonperiodic TxFIFO empty */
+#define USB_OTG_GINTSTS_GINAKEFF 0x00000040U /*!< Global IN nonperiodic NAK effective */
+#define USB_OTG_GINTSTS_BOUTNAKEFF 0x00000080U /*!< Global OUT NAK effective */
+#define USB_OTG_GINTSTS_ESUSP 0x00000400U /*!< Early suspend */
+#define USB_OTG_GINTSTS_USBSUSP 0x00000800U /*!< USB suspend */
+#define USB_OTG_GINTSTS_USBRST 0x00001000U /*!< USB reset */
+#define USB_OTG_GINTSTS_ENUMDNE 0x00002000U /*!< Enumeration done */
+#define USB_OTG_GINTSTS_ISOODRP 0x00004000U /*!< Isochronous OUT packet dropped interrupt */
+#define USB_OTG_GINTSTS_EOPF 0x00008000U /*!< End of periodic frame interrupt */
+#define USB_OTG_GINTSTS_IEPINT 0x00040000U /*!< IN endpoint interrupt */
+#define USB_OTG_GINTSTS_OEPINT 0x00080000U /*!< OUT endpoint interrupt */
+#define USB_OTG_GINTSTS_IISOIXFR 0x00100000U /*!< Incomplete isochronous IN transfer */
+#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT 0x00200000U /*!< Incomplete periodic transfer */
+#define USB_OTG_GINTSTS_DATAFSUSP 0x00400000U /*!< Data fetch suspended */
+#define USB_OTG_GINTSTS_RSTDET 0x00800000U /*!< Reset detected interrupt */
+#define USB_OTG_GINTSTS_HPRTINT 0x01000000U /*!< Host port interrupt */
+#define USB_OTG_GINTSTS_HCINT 0x02000000U /*!< Host channels interrupt */
+#define USB_OTG_GINTSTS_PTXFE 0x04000000U /*!< Periodic TxFIFO empty */
+#define USB_OTG_GINTSTS_LPMINT 0x08000000U /*!< LPM interrupt */
+#define USB_OTG_GINTSTS_CIDSCHG 0x10000000U /*!< Connector ID status change */
+#define USB_OTG_GINTSTS_DISCINT 0x20000000U /*!< Disconnect detected interrupt */
+#define USB_OTG_GINTSTS_SRQINT 0x40000000U /*!< Session request/new session detected interrupt */
+#define USB_OTG_GINTSTS_WKUINT 0x80000000U /*!< Resume/remote wakeup detected interrupt */
+
+/******************** Bit definition for USB_OTG_GINTMSK register ***********/
+#define USB_OTG_GINTMSK_MMISM 0x00000002U /*!< Mode mismatch interrupt mask */
+#define USB_OTG_GINTMSK_OTGINT 0x00000004U /*!< OTG interrupt mask */
+#define USB_OTG_GINTMSK_SOFM 0x00000008U /*!< Start of frame mask */
+#define USB_OTG_GINTMSK_RXFLVLM 0x00000010U /*!< Receive FIFO nonempty mask */
+#define USB_OTG_GINTMSK_NPTXFEM 0x00000020U /*!< Nonperiodic TxFIFO empty mask */
+#define USB_OTG_GINTMSK_GINAKEFFM 0x00000040U /*!< Global nonperiodic IN NAK effective mask */
+#define USB_OTG_GINTMSK_GONAKEFFM 0x00000080U /*!< Global OUT NAK effective mask */
+#define USB_OTG_GINTMSK_ESUSPM 0x00000400U /*!< Early suspend mask */
+#define USB_OTG_GINTMSK_USBSUSPM 0x00000800U /*!< USB suspend mask */
+#define USB_OTG_GINTMSK_USBRST 0x00001000U /*!< USB reset mask */
+#define USB_OTG_GINTMSK_ENUMDNEM 0x00002000U /*!< Enumeration done mask */
+#define USB_OTG_GINTMSK_ISOODRPM 0x00004000U /*!< Isochronous OUT packet dropped interrupt mask */
+#define USB_OTG_GINTMSK_EOPFM 0x00008000U /*!< End of periodic frame interrupt mask */
+#define USB_OTG_GINTMSK_EPMISM 0x00020000U /*!< Endpoint mismatch interrupt mask */
+#define USB_OTG_GINTMSK_IEPINT 0x00040000U /*!< IN endpoints interrupt mask */
+#define USB_OTG_GINTMSK_OEPINT 0x00080000U /*!< OUT endpoints interrupt mask */
+#define USB_OTG_GINTMSK_IISOIXFRM 0x00100000U /*!< Incomplete isochronous IN transfer mask */
+#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM 0x00200000U /*!< Incomplete periodic transfer mask */
+#define USB_OTG_GINTMSK_FSUSPM 0x00400000U /*!< Data fetch suspended mask */
+#define USB_OTG_GINTMSK_RSTDETM 0x00800000U /*!< Reset detected interrupt mask */
+#define USB_OTG_GINTMSK_PRTIM 0x01000000U /*!< Host port interrupt mask */
+#define USB_OTG_GINTMSK_HCIM 0x02000000U /*!< Host channels interrupt mask */
+#define USB_OTG_GINTMSK_PTXFEM 0x04000000U /*!< Periodic TxFIFO empty mask */
+#define USB_OTG_GINTMSK_LPMINTM 0x08000000U /*!< LPM interrupt Mask */
+#define USB_OTG_GINTMSK_CIDSCHGM 0x10000000U /*!< Connector ID status change mask */
+#define USB_OTG_GINTMSK_DISCINT 0x20000000U /*!< Disconnect detected interrupt mask */
+#define USB_OTG_GINTMSK_SRQIM 0x40000000U /*!< Session request/new session detected interrupt mask */
+#define USB_OTG_GINTMSK_WUIM 0x80000000U /*!< Resume/remote wakeup detected interrupt mask */
+
+/******************** Bit definition for USB_OTG_DAINT register *************/
+#define USB_OTG_DAINT_IEPINT 0x0000FFFFU /*!< IN endpoint interrupt bits */
+#define USB_OTG_DAINT_OEPINT 0xFFFF0000U /*!< OUT endpoint interrupt bits */
+
+/******************** Bit definition for USB_OTG_HAINTMSK register **********/
+#define USB_OTG_HAINTMSK_HAINTM 0x0000FFFFU /*!< Channel interrupt mask */
+
+/******************** Bit definition for USB_OTG_GRXSTSP register ***********/
+#define USB_OTG_GRXSTSP_EPNUM 0x0000000FU /*!< IN EP interrupt mask bits */
+#define USB_OTG_GRXSTSP_BCNT 0x00007FF0U /*!< OUT EP interrupt mask bits */
+#define USB_OTG_GRXSTSP_DPID 0x00018000U /*!< OUT EP interrupt mask bits */
+#define USB_OTG_GRXSTSP_PKTSTS 0x001E0000U /*!< OUT EP interrupt mask bits */
+
+/******************** Bit definition for USB_OTG_DAINTMSK register **********/
+#define USB_OTG_DAINTMSK_IEPM 0x0000FFFFU /*!< IN EP interrupt mask bits */
+#define USB_OTG_DAINTMSK_OEPM 0xFFFF0000U /*!< OUT EP interrupt mask bits */
+
+/******************** Bit definition for OTG register ***********************/
+
+#define USB_OTG_CHNUM 0x0000000FU /*!< Channel number */
+#define USB_OTG_CHNUM_0 0x00000001U /*!<Bit 0 */
+#define USB_OTG_CHNUM_1 0x00000002U /*!<Bit 1 */
+#define USB_OTG_CHNUM_2 0x00000004U /*!<Bit 2 */
+#define USB_OTG_CHNUM_3 0x00000008U /*!<Bit 3 */
+#define USB_OTG_BCNT 0x00007FF0U /*!< Byte count */
+
+#define USB_OTG_DPID 0x00018000U /*!< Data PID */
+#define USB_OTG_DPID_0 0x00008000U /*!<Bit 0 */
+#define USB_OTG_DPID_1 0x00010000U /*!<Bit 1 */
+
+#define USB_OTG_PKTSTS 0x001E0000U /*!< Packet status */
+#define USB_OTG_PKTSTS_0 0x00020000U /*!<Bit 0 */
+#define USB_OTG_PKTSTS_1 0x00040000U /*!<Bit 1 */
+#define USB_OTG_PKTSTS_2 0x00080000U /*!<Bit 2 */
+#define USB_OTG_PKTSTS_3 0x00100000U /*!<Bit 3 */
+
+#define USB_OTG_EPNUM 0x0000000FU /*!< Endpoint number */
+#define USB_OTG_EPNUM_0 0x00000001U /*!<Bit 0 */
+#define USB_OTG_EPNUM_1 0x00000002U /*!<Bit 1 */
+#define USB_OTG_EPNUM_2 0x00000004U /*!<Bit 2 */
+#define USB_OTG_EPNUM_3 0x00000008U /*!<Bit 3 */
+
+#define USB_OTG_FRMNUM 0x01E00000U /*!< Frame number */
+#define USB_OTG_FRMNUM_0 0x00200000U /*!<Bit 0 */
+#define USB_OTG_FRMNUM_1 0x00400000U /*!<Bit 1 */
+#define USB_OTG_FRMNUM_2 0x00800000U /*!<Bit 2 */
+#define USB_OTG_FRMNUM_3 0x01000000U /*!<Bit 3 */
+
+/******************** Bit definition for OTG register ***********************/
+#define USB_OTG_CHNUM 0x0000000FU /*!< Channel number */
+#define USB_OTG_CHNUM_0 0x00000001U /*!<Bit 0 */
+#define USB_OTG_CHNUM_1 0x00000002U /*!<Bit 1 */
+#define USB_OTG_CHNUM_2 0x00000004U /*!<Bit 2 */
+#define USB_OTG_CHNUM_3 0x00000008U /*!<Bit 3 */
+#define USB_OTG_BCNT 0x00007FF0U /*!< Byte count */
+
+#define USB_OTG_DPID 0x00018000U /*!< Data PID */
+#define USB_OTG_DPID_0 0x00008000U /*!<Bit 0 */
+#define USB_OTG_DPID_1 0x00010000U /*!<Bit 1 */
+
+#define USB_OTG_PKTSTS 0x001E0000U /*!< Packet status */
+#define USB_OTG_PKTSTS_0 0x00020000U /*!<Bit 0 */
+#define USB_OTG_PKTSTS_1 0x00040000U /*!<Bit 1 */
+#define USB_OTG_PKTSTS_2 0x00080000U /*!<Bit 2 */
+#define USB_OTG_PKTSTS_3 0x00100000U /*!<Bit 3 */
+
+#define USB_OTG_EPNUM 0x0000000FU /*!< Endpoint number */
+#define USB_OTG_EPNUM_0 0x00000001U /*!<Bit 0 */
+#define USB_OTG_EPNUM_1 0x00000002U /*!<Bit 1 */
+#define USB_OTG_EPNUM_2 0x00000004U /*!<Bit 2 */
+#define USB_OTG_EPNUM_3 0x00000008U /*!<Bit 3 */
+
+#define USB_OTG_FRMNUM 0x01E00000U /*!< Frame number */
+#define USB_OTG_FRMNUM_0 0x00200000U /*!<Bit 0 */
+#define USB_OTG_FRMNUM_1 0x00400000U /*!<Bit 1 */
+#define USB_OTG_FRMNUM_2 0x00800000U /*!<Bit 2 */
+#define USB_OTG_FRMNUM_3 0x01000000U /*!<Bit 3 */
+
+/******************** Bit definition for USB_OTG_GRXFSIZ register ***********/
+#define USB_OTG_GRXFSIZ_RXFD 0x0000FFFFU /*!< RxFIFO depth */
+
+/******************** Bit definition for USB_OTG_DVBUSDIS register **********/
+#define USB_OTG_DVBUSDIS_VBUSDT 0x0000FFFFU /*!< Device VBUS discharge time */
+
+/******************** Bit definition for OTG register ***********************/
+#define USB_OTG_NPTXFSA 0x0000FFFFU /*!< Nonperiodic transmit RAM start address */
+#define USB_OTG_NPTXFD 0xFFFF0000U /*!< Nonperiodic TxFIFO depth */
+#define USB_OTG_TX0FSA 0x0000FFFFU /*!< Endpoint 0 transmit RAM start address */
+#define USB_OTG_TX0FD 0xFFFF0000U /*!< Endpoint 0 TxFIFO depth */
+
+/******************** Bit definition for USB_OTG_DVBUSPULSE register ********/
+#define USB_OTG_DVBUSPULSE_DVBUSP 0x00000FFFU /*!< Device VBUS pulsing time */
+
+/******************** Bit definition for USB_OTG_GNPTXSTS register **********/
+#define USB_OTG_GNPTXSTS_NPTXFSAV 0x0000FFFFU /*!< Nonperiodic TxFIFO space available */
+
+#define USB_OTG_GNPTXSTS_NPTQXSAV 0x00FF0000U /*!< Nonperiodic transmit request queue space available */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_0 0x00010000U /*!<Bit 0 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_1 0x00020000U /*!<Bit 1 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_2 0x00040000U /*!<Bit 2 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_3 0x00080000U /*!<Bit 3 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_4 0x00100000U /*!<Bit 4 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_5 0x00200000U /*!<Bit 5 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_6 0x00400000U /*!<Bit 6 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_7 0x00800000U /*!<Bit 7 */
+
+#define USB_OTG_GNPTXSTS_NPTXQTOP 0x7F000000U /*!< Top of the nonperiodic transmit request queue */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_0 0x01000000U /*!<Bit 0 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_1 0x02000000U /*!<Bit 1 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_2 0x04000000U /*!<Bit 2 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_3 0x08000000U /*!<Bit 3 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_4 0x10000000U /*!<Bit 4 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_5 0x20000000U /*!<Bit 5 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_6 0x40000000U /*!<Bit 6 */
+
+/******************** Bit definition for USB_OTG_DTHRCTL register ***********/
+#define USB_OTG_DTHRCTL_NONISOTHREN 0x00000001U /*!< Nonisochronous IN endpoints threshold enable */
+#define USB_OTG_DTHRCTL_ISOTHREN 0x00000002U /*!< ISO IN endpoint threshold enable */
+
+#define USB_OTG_DTHRCTL_TXTHRLEN 0x000007FCU /*!< Transmit threshold length */
+#define USB_OTG_DTHRCTL_TXTHRLEN_0 0x00000004U /*!<Bit 0 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_1 0x00000008U /*!<Bit 1 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_2 0x00000010U /*!<Bit 2 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_3 0x00000020U /*!<Bit 3 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_4 0x00000040U /*!<Bit 4 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_5 0x00000080U /*!<Bit 5 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_6 0x00000100U /*!<Bit 6 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_7 0x00000200U /*!<Bit 7 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_8 0x00000400U /*!<Bit 8 */
+#define USB_OTG_DTHRCTL_RXTHREN 0x00010000U /*!< Receive threshold enable */
+
+#define USB_OTG_DTHRCTL_RXTHRLEN 0x03FE0000U /*!< Receive threshold length */
+#define USB_OTG_DTHRCTL_RXTHRLEN_0 0x00020000U /*!<Bit 0 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_1 0x00040000U /*!<Bit 1 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_2 0x00080000U /*!<Bit 2 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_3 0x00100000U /*!<Bit 3 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_4 0x00200000U /*!<Bit 4 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_5 0x00400000U /*!<Bit 5 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_6 0x00800000U /*!<Bit 6 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_7 0x01000000U /*!<Bit 7 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_8 0x02000000U /*!<Bit 8 */
+#define USB_OTG_DTHRCTL_ARPEN 0x08000000U /*!< Arbiter parking enable */
+
+/******************** Bit definition for USB_OTG_DIEPEMPMSK register ********/
+#define USB_OTG_DIEPEMPMSK_INEPTXFEM 0x0000FFFFU /*!< IN EP Tx FIFO empty interrupt mask bits */
+
+/******************** Bit definition for USB_OTG_DEACHINT register **********/
+#define USB_OTG_DEACHINT_IEP1INT 0x00000002U /*!< IN endpoint 1interrupt bit */
+#define USB_OTG_DEACHINT_OEP1INT 0x00020000U /*!< OUT endpoint 1 interrupt bit */
+
+/******************** Bit definition for USB_OTG_GCCFG register *************/
+#define USB_OTG_GCCFG_DCDET 0x00000001U /*!< Data contact detection (DCD) status */
+#define USB_OTG_GCCFG_PDET 0x00000002U /*!< Primary detection (PD) status */
+#define USB_OTG_GCCFG_SDET 0x00000004U /*!< Secondary detection (SD) status */
+#define USB_OTG_GCCFG_PS2DET 0x00000008U /*!< DM pull-up detection status */
+#define USB_OTG_GCCFG_PWRDWN 0x00010000U /*!< Power down */
+#define USB_OTG_GCCFG_BCDEN 0x00020000U /*!< Battery charging detector (BCD) enable */
+#define USB_OTG_GCCFG_DCDEN 0x00040000U /*!< Data contact detection (DCD) mode enable*/
+#define USB_OTG_GCCFG_PDEN 0x00080000U /*!< Primary detection (PD) mode enable*/
+#define USB_OTG_GCCFG_SDEN 0x00100000U /*!< Secondary detection (SD) mode enable */
+#define USB_OTG_GCCFG_VBDEN 0x00200000U /*!< USB VBUS Detection Enable */
+
+/******************** Bit definition for USB_OTG_DEACHINTMSK register *******/
+#define USB_OTG_DEACHINTMSK_IEP1INTM 0x00000002U /*!< IN Endpoint 1 interrupt mask bit */
+#define USB_OTG_DEACHINTMSK_OEP1INTM 0x00020000U /*!< OUT Endpoint 1 interrupt mask bit */
+
+/******************** Bit definition for USB_OTG_CID register ***************/
+#define USB_OTG_CID_PRODUCT_ID 0xFFFFFFFFU /*!< Product ID field */
+
+/******************** Bit definition for USB_OTG_GLPMCFG register ***********/
+#define USB_OTG_GLPMCFG_LPMEN 0x00000001U /*!< LPM support enable */
+#define USB_OTG_GLPMCFG_LPMACK 0x00000002U /*!< LPM Token acknowledge enable */
+#define USB_OTG_GLPMCFG_BESL 0x0000003CU /*!< BESL value received with last ACKed LPM Token */
+#define USB_OTG_GLPMCFG_REMWAKE 0x00000040U /*!< bRemoteWake value received with last ACKed LPM Token */
+#define USB_OTG_GLPMCFG_L1SSEN 0x00000080U /*!< L1 shallow sleep enable */
+#define USB_OTG_GLPMCFG_BESLTHRS 0x00000F00U /*!< BESL threshold */
+#define USB_OTG_GLPMCFG_L1DSEN 0x00001000U /*!< L1 deep sleep enable */
+#define USB_OTG_GLPMCFG_LPMRSP 0x00006000U /*!< LPM response */
+#define USB_OTG_GLPMCFG_SLPSTS 0x00008000U /*!< Port sleep status */
+#define USB_OTG_GLPMCFG_L1RSMOK 0x00010000U /*!< Sleep State Resume OK */
+#define USB_OTG_GLPMCFG_LPMCHIDX 0x001E0000U /*!< LPM Channel Index */
+#define USB_OTG_GLPMCFG_LPMRCNT 0x00E00000U /*!< LPM retry count */
+#define USB_OTG_GLPMCFG_SNDLPM 0x01000000U /*!< Send LPM transaction */
+#define USB_OTG_GLPMCFG_LPMRCNTSTS 0x0E000000U /*!< LPM retry count status */
+#define USB_OTG_GLPMCFG_ENBESL 0x10000000U /*!< Enable best effort service latency */
+
+/******************** Bit definition for USB_OTG_DIEPEACHMSK1 register ******/
+#define USB_OTG_DIEPEACHMSK1_XFRCM 0x00000001U /*!< Transfer completed interrupt mask */
+#define USB_OTG_DIEPEACHMSK1_EPDM 0x00000002U /*!< Endpoint disabled interrupt mask */
+#define USB_OTG_DIEPEACHMSK1_TOM 0x00000008U /*!< Timeout condition mask (nonisochronous endpoints) */
+#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK 0x00000010U /*!< IN token received when TxFIFO empty mask */
+#define USB_OTG_DIEPEACHMSK1_INEPNMM 0x00000020U /*!< IN token received with EP mismatch mask */
+#define USB_OTG_DIEPEACHMSK1_INEPNEM 0x00000040U /*!< IN endpoint NAK effective mask */
+#define USB_OTG_DIEPEACHMSK1_TXFURM 0x00000100U /*!< FIFO underrun mask */
+#define USB_OTG_DIEPEACHMSK1_BIM 0x00000200U /*!< BNA interrupt mask */
+#define USB_OTG_DIEPEACHMSK1_NAKM 0x00002000U /*!< NAK interrupt mask */
+
+/******************** Bit definition for USB_OTG_HPRT register **************/
+#define USB_OTG_HPRT_PCSTS 0x00000001U /*!< Port connect status */
+#define USB_OTG_HPRT_PCDET 0x00000002U /*!< Port connect detected */
+#define USB_OTG_HPRT_PENA 0x00000004U /*!< Port enable */
+#define USB_OTG_HPRT_PENCHNG 0x00000008U /*!< Port enable/disable change */
+#define USB_OTG_HPRT_POCA 0x00000010U /*!< Port overcurrent active */
+#define USB_OTG_HPRT_POCCHNG 0x00000020U /*!< Port overcurrent change */
+#define USB_OTG_HPRT_PRES 0x00000040U /*!< Port resume */
+#define USB_OTG_HPRT_PSUSP 0x00000080U /*!< Port suspend */
+#define USB_OTG_HPRT_PRST 0x00000100U /*!< Port reset */
+
+#define USB_OTG_HPRT_PLSTS 0x00000C00U /*!< Port line status */
+#define USB_OTG_HPRT_PLSTS_0 0x00000400U /*!<Bit 0 */
+#define USB_OTG_HPRT_PLSTS_1 0x00000800U /*!<Bit 1 */
+#define USB_OTG_HPRT_PPWR 0x00001000U /*!< Port power */
+
+#define USB_OTG_HPRT_PTCTL 0x0001E000U /*!< Port test control */
+#define USB_OTG_HPRT_PTCTL_0 0x00002000U /*!<Bit 0 */
+#define USB_OTG_HPRT_PTCTL_1 0x00004000U /*!<Bit 1 */
+#define USB_OTG_HPRT_PTCTL_2 0x00008000U /*!<Bit 2 */
+#define USB_OTG_HPRT_PTCTL_3 0x00010000U /*!<Bit 3 */
+
+#define USB_OTG_HPRT_PSPD 0x00060000U /*!< Port speed */
+#define USB_OTG_HPRT_PSPD_0 0x00020000U /*!<Bit 0 */
+#define USB_OTG_HPRT_PSPD_1 0x00040000U /*!<Bit 1 */
+
+/******************** Bit definition for USB_OTG_DOEPEACHMSK1 register ******/
+#define USB_OTG_DOEPEACHMSK1_XFRCM 0x00000001U /*!< Transfer completed interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_EPDM 0x00000002U /*!< Endpoint disabled interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_TOM 0x00000008U /*!< Timeout condition mask */
+#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK 0x00000010U /*!< IN token received when TxFIFO empty mask */
+#define USB_OTG_DOEPEACHMSK1_INEPNMM 0x00000020U /*!< IN token received with EP mismatch mask */
+#define USB_OTG_DOEPEACHMSK1_INEPNEM 0x00000040U /*!< IN endpoint NAK effective mask */
+#define USB_OTG_DOEPEACHMSK1_TXFURM 0x00000100U /*!< OUT packet error mask */
+#define USB_OTG_DOEPEACHMSK1_BIM 0x00000200U /*!< BNA interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_BERRM 0x00001000U /*!< Bubble error interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_NAKM 0x00002000U /*!< NAK interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_NYETM 0x00004000U /*!< NYET interrupt mask */
+
+/******************** Bit definition for USB_OTG_HPTXFSIZ register **********/
+#define USB_OTG_HPTXFSIZ_PTXSA 0x0000FFFFU /*!< Host periodic TxFIFO start address */
+#define USB_OTG_HPTXFSIZ_PTXFD 0xFFFF0000U /*!< Host periodic TxFIFO depth */
+
+/******************** Bit definition for USB_OTG_DIEPCTL register ***********/
+#define USB_OTG_DIEPCTL_MPSIZ 0x000007FFU /*!< Maximum packet size */
+#define USB_OTG_DIEPCTL_USBAEP 0x00008000U /*!< USB active endpoint */
+#define USB_OTG_DIEPCTL_EONUM_DPID 0x00010000U /*!< Even/odd frame */
+#define USB_OTG_DIEPCTL_NAKSTS 0x00020000U /*!< NAK status */
+
+#define USB_OTG_DIEPCTL_EPTYP 0x000C0000U /*!< Endpoint type */
+#define USB_OTG_DIEPCTL_EPTYP_0 0x00040000U /*!<Bit 0 */
+#define USB_OTG_DIEPCTL_EPTYP_1 0x00080000U /*!<Bit 1 */
+#define USB_OTG_DIEPCTL_STALL 0x00200000U /*!< STALL handshake */
+
+#define USB_OTG_DIEPCTL_TXFNUM 0x03C00000U /*!< TxFIFO number */
+#define USB_OTG_DIEPCTL_TXFNUM_0 0x00400000U /*!<Bit 0 */
+#define USB_OTG_DIEPCTL_TXFNUM_1 0x00800000U /*!<Bit 1 */
+#define USB_OTG_DIEPCTL_TXFNUM_2 0x01000000U /*!<Bit 2 */
+#define USB_OTG_DIEPCTL_TXFNUM_3 0x02000000U /*!<Bit 3 */
+#define USB_OTG_DIEPCTL_CNAK 0x04000000U /*!< Clear NAK */
+#define USB_OTG_DIEPCTL_SNAK 0x08000000U /*!< Set NAK */
+#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM 0x10000000U /*!< Set DATA0 PID */
+#define USB_OTG_DIEPCTL_SODDFRM 0x20000000U /*!< Set odd frame */
+#define USB_OTG_DIEPCTL_EPDIS 0x40000000U /*!< Endpoint disable */
+#define USB_OTG_DIEPCTL_EPENA 0x80000000U /*!< Endpoint enable */
+
+/******************** Bit definition for USB_OTG_HCCHAR register ************/
+#define USB_OTG_HCCHAR_MPSIZ 0x000007FFU /*!< Maximum packet size */
+
+#define USB_OTG_HCCHAR_EPNUM 0x00007800U /*!< Endpoint number */
+#define USB_OTG_HCCHAR_EPNUM_0 0x00000800U /*!<Bit 0 */
+#define USB_OTG_HCCHAR_EPNUM_1 0x00001000U /*!<Bit 1 */
+#define USB_OTG_HCCHAR_EPNUM_2 0x00002000U /*!<Bit 2 */
+#define USB_OTG_HCCHAR_EPNUM_3 0x00004000U /*!<Bit 3 */
+#define USB_OTG_HCCHAR_EPDIR 0x00008000U /*!< Endpoint direction */
+#define USB_OTG_HCCHAR_LSDEV 0x00020000U /*!< Low-speed device */
+
+#define USB_OTG_HCCHAR_EPTYP 0x000C0000U /*!< Endpoint type */
+#define USB_OTG_HCCHAR_EPTYP_0 0x00040000U /*!<Bit 0 */
+#define USB_OTG_HCCHAR_EPTYP_1 0x00080000U /*!<Bit 1 */
+
+#define USB_OTG_HCCHAR_MC 0x00300000U /*!< Multi Count (MC) / Error Count (EC) */
+#define USB_OTG_HCCHAR_MC_0 0x00100000U /*!<Bit 0 */
+#define USB_OTG_HCCHAR_MC_1 0x00200000U /*!<Bit 1 */
+
+#define USB_OTG_HCCHAR_DAD 0x1FC00000U /*!< Device address */
+#define USB_OTG_HCCHAR_DAD_0 0x00400000U /*!<Bit 0 */
+#define USB_OTG_HCCHAR_DAD_1 0x00800000U /*!<Bit 1 */
+#define USB_OTG_HCCHAR_DAD_2 0x01000000U /*!<Bit 2 */
+#define USB_OTG_HCCHAR_DAD_3 0x02000000U /*!<Bit 3 */
+#define USB_OTG_HCCHAR_DAD_4 0x04000000U /*!<Bit 4 */
+#define USB_OTG_HCCHAR_DAD_5 0x08000000U /*!<Bit 5 */
+#define USB_OTG_HCCHAR_DAD_6 0x10000000U /*!<Bit 6 */
+#define USB_OTG_HCCHAR_ODDFRM 0x20000000U /*!< Odd frame */
+#define USB_OTG_HCCHAR_CHDIS 0x40000000U /*!< Channel disable */
+#define USB_OTG_HCCHAR_CHENA 0x80000000U /*!< Channel enable */
+
+/******************** Bit definition for USB_OTG_HCSPLT register ************/
+
+#define USB_OTG_HCSPLT_PRTADDR 0x0000007FU /*!< Port address */
+#define USB_OTG_HCSPLT_PRTADDR_0 0x00000001U /*!<Bit 0 */
+#define USB_OTG_HCSPLT_PRTADDR_1 0x00000002U /*!<Bit 1 */
+#define USB_OTG_HCSPLT_PRTADDR_2 0x00000004U /*!<Bit 2 */
+#define USB_OTG_HCSPLT_PRTADDR_3 0x00000008U /*!<Bit 3 */
+#define USB_OTG_HCSPLT_PRTADDR_4 0x00000010U /*!<Bit 4 */
+#define USB_OTG_HCSPLT_PRTADDR_5 0x00000020U /*!<Bit 5 */
+#define USB_OTG_HCSPLT_PRTADDR_6 0x00000040U /*!<Bit 6 */
+
+#define USB_OTG_HCSPLT_HUBADDR 0x00003F80U /*!< Hub address */
+#define USB_OTG_HCSPLT_HUBADDR_0 0x00000080U /*!<Bit 0 */
+#define USB_OTG_HCSPLT_HUBADDR_1 0x00000100U /*!<Bit 1 */
+#define USB_OTG_HCSPLT_HUBADDR_2 0x00000200U /*!<Bit 2 */
+#define USB_OTG_HCSPLT_HUBADDR_3 0x00000400U /*!<Bit 3 */
+#define USB_OTG_HCSPLT_HUBADDR_4 0x00000800U /*!<Bit 4 */
+#define USB_OTG_HCSPLT_HUBADDR_5 0x00001000U /*!<Bit 5 */
+#define USB_OTG_HCSPLT_HUBADDR_6 0x00002000U /*!<Bit 6 */
+
+#define USB_OTG_HCSPLT_XACTPOS 0x0000C000U /*!< XACTPOS */
+#define USB_OTG_HCSPLT_XACTPOS_0 0x00004000U /*!<Bit 0 */
+#define USB_OTG_HCSPLT_XACTPOS_1 0x00008000U /*!<Bit 1 */
+#define USB_OTG_HCSPLT_COMPLSPLT 0x00010000U /*!< Do complete split */
+#define USB_OTG_HCSPLT_SPLITEN 0x80000000U /*!< Split enable */
+
+/******************** Bit definition for USB_OTG_HCINT register *************/
+#define USB_OTG_HCINT_XFRC 0x00000001U /*!< Transfer completed */
+#define USB_OTG_HCINT_CHH 0x00000002U /*!< Channel halted */
+#define USB_OTG_HCINT_AHBERR 0x00000004U /*!< AHB error */
+#define USB_OTG_HCINT_STALL 0x00000008U /*!< STALL response received interrupt */
+#define USB_OTG_HCINT_NAK 0x00000010U /*!< NAK response received interrupt */
+#define USB_OTG_HCINT_ACK 0x00000020U /*!< ACK response received/transmitted interrupt */
+#define USB_OTG_HCINT_NYET 0x00000040U /*!< Response received interrupt */
+#define USB_OTG_HCINT_TXERR 0x00000080U /*!< Transaction error */
+#define USB_OTG_HCINT_BBERR 0x00000100U /*!< Babble error */
+#define USB_OTG_HCINT_FRMOR 0x00000200U /*!< Frame overrun */
+#define USB_OTG_HCINT_DTERR 0x00000400U /*!< Data toggle error */
+
+/******************** Bit definition for USB_OTG_DIEPINT register ***********/
+#define USB_OTG_DIEPINT_XFRC 0x00000001U /*!< Transfer completed interrupt */
+#define USB_OTG_DIEPINT_EPDISD 0x00000002U /*!< Endpoint disabled interrupt */
+#define USB_OTG_DIEPINT_TOC 0x00000008U /*!< Timeout condition */
+#define USB_OTG_DIEPINT_ITTXFE 0x00000010U /*!< IN token received when TxFIFO is empty */
+#define USB_OTG_DIEPINT_INEPNE 0x00000040U /*!< IN endpoint NAK effective */
+#define USB_OTG_DIEPINT_TXFE 0x00000080U /*!< Transmit FIFO empty */
+#define USB_OTG_DIEPINT_TXFIFOUDRN 0x00000100U /*!< Transmit Fifo Underrun */
+#define USB_OTG_DIEPINT_BNA 0x00000200U /*!< Buffer not available interrupt */
+#define USB_OTG_DIEPINT_PKTDRPSTS 0x00000800U /*!< Packet dropped status */
+#define USB_OTG_DIEPINT_BERR 0x00001000U /*!< Babble error interrupt */
+#define USB_OTG_DIEPINT_NAK 0x00002000U /*!< NAK interrupt */
+
+/******************** Bit definition for USB_OTG_HCINTMSK register **********/
+#define USB_OTG_HCINTMSK_XFRCM 0x00000001U /*!< Transfer completed mask */
+#define USB_OTG_HCINTMSK_CHHM 0x00000002U /*!< Channel halted mask */
+#define USB_OTG_HCINTMSK_AHBERR 0x00000004U /*!< AHB error */
+#define USB_OTG_HCINTMSK_STALLM 0x00000008U /*!< STALL response received interrupt mask */
+#define USB_OTG_HCINTMSK_NAKM 0x00000010U /*!< NAK response received interrupt mask */
+#define USB_OTG_HCINTMSK_ACKM 0x00000020U /*!< ACK response received/transmitted interrupt mask */
+#define USB_OTG_HCINTMSK_NYET 0x00000040U /*!< response received interrupt mask */
+#define USB_OTG_HCINTMSK_TXERRM 0x00000080U /*!< Transaction error mask */
+#define USB_OTG_HCINTMSK_BBERRM 0x00000100U /*!< Babble error mask */
+#define USB_OTG_HCINTMSK_FRMORM 0x00000200U /*!< Frame overrun mask */
+#define USB_OTG_HCINTMSK_DTERRM 0x00000400U /*!< Data toggle error mask */
+
+/******************** Bit definition for USB_OTG_DIEPTSIZ register **********/
+
+#define USB_OTG_DIEPTSIZ_XFRSIZ 0x0007FFFFU /*!< Transfer size */
+#define USB_OTG_DIEPTSIZ_PKTCNT 0x1FF80000U /*!< Packet count */
+#define USB_OTG_DIEPTSIZ_MULCNT 0x60000000U /*!< Packet count */
+/******************** Bit definition for USB_OTG_HCTSIZ register ************/
+#define USB_OTG_HCTSIZ_XFRSIZ 0x0007FFFFU /*!< Transfer size */
+#define USB_OTG_HCTSIZ_PKTCNT 0x1FF80000U /*!< Packet count */
+#define USB_OTG_HCTSIZ_DOPING 0x80000000U /*!< Do PING */
+#define USB_OTG_HCTSIZ_DPID 0x60000000U /*!< Data PID */
+#define USB_OTG_HCTSIZ_DPID_0 0x20000000U /*!<Bit 0 */
+#define USB_OTG_HCTSIZ_DPID_1 0x40000000U /*!<Bit 1 */
+
+/******************** Bit definition for USB_OTG_DIEPDMA register ***********/
+#define USB_OTG_DIEPDMA_DMAADDR 0xFFFFFFFFU /*!< DMA address */
+
+/******************** Bit definition for USB_OTG_HCDMA register *************/
+#define USB_OTG_HCDMA_DMAADDR 0xFFFFFFFFU /*!< DMA address */
+
+/******************** Bit definition for USB_OTG_DTXFSTS register ***********/
+#define USB_OTG_DTXFSTS_INEPTFSAV 0x0000FFFFU /*!< IN endpoint TxFIFO space available */
+
+/******************** Bit definition for USB_OTG_DIEPTXF register ***********/
+#define USB_OTG_DIEPTXF_INEPTXSA 0x0000FFFFU /*!< IN endpoint FIFOx transmit RAM start address */
+#define USB_OTG_DIEPTXF_INEPTXFD 0xFFFF0000U /*!< IN endpoint TxFIFO depth */
+
+/******************** Bit definition for USB_OTG_DOEPCTL register ***********/
+
+#define USB_OTG_DOEPCTL_MPSIZ 0x000007FFU /*!< Maximum packet size */ /*!<Bit 1 */
+#define USB_OTG_DOEPCTL_USBAEP 0x00008000U /*!< USB active endpoint */
+#define USB_OTG_DOEPCTL_NAKSTS 0x00020000U /*!< NAK status */
+#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM 0x10000000U /*!< Set DATA0 PID */
+#define USB_OTG_DOEPCTL_SODDFRM 0x20000000U /*!< Set odd frame */
+#define USB_OTG_DOEPCTL_EPTYP 0x000C0000U /*!< Endpoint type */
+#define USB_OTG_DOEPCTL_EPTYP_0 0x00040000U /*!<Bit 0 */
+#define USB_OTG_DOEPCTL_EPTYP_1 0x00080000U /*!<Bit 1 */
+#define USB_OTG_DOEPCTL_SNPM 0x00100000U /*!< Snoop mode */
+#define USB_OTG_DOEPCTL_STALL 0x00200000U /*!< STALL handshake */
+#define USB_OTG_DOEPCTL_CNAK 0x04000000U /*!< Clear NAK */
+#define USB_OTG_DOEPCTL_SNAK 0x08000000U /*!< Set NAK */
+#define USB_OTG_DOEPCTL_EPDIS 0x40000000U /*!< Endpoint disable */
+#define USB_OTG_DOEPCTL_EPENA 0x80000000U /*!< Endpoint enable */
+
+/******************** Bit definition for USB_OTG_DOEPINT register ***********/
+#define USB_OTG_DOEPINT_XFRC 0x00000001U /*!< Transfer completed interrupt */
+#define USB_OTG_DOEPINT_EPDISD 0x00000002U /*!< Endpoint disabled interrupt */
+#define USB_OTG_DOEPINT_STUP 0x00000008U /*!< SETUP phase done */
+#define USB_OTG_DOEPINT_OTEPDIS 0x00000010U /*!< OUT token received when endpoint disabled */
+#define USB_OTG_DOEPINT_OTEPSPR 0x00000020U /*!< Status Phase Received For Control Write */
+#define USB_OTG_DOEPINT_B2BSTUP 0x00000040U /*!< Back-to-back SETUP packets received */
+#define USB_OTG_DOEPINT_NYET 0x00004000U /*!< NYET interrupt */
+
+/******************** Bit definition for USB_OTG_DOEPTSIZ register **********/
+
+#define USB_OTG_DOEPTSIZ_XFRSIZ 0x0007FFFFU /*!< Transfer size */
+#define USB_OTG_DOEPTSIZ_PKTCNT 0x1FF80000U /*!< Packet count */
+
+#define USB_OTG_DOEPTSIZ_STUPCNT 0x60000000U /*!< SETUP packet count */
+#define USB_OTG_DOEPTSIZ_STUPCNT_0 0x20000000U /*!<Bit 0 */
+#define USB_OTG_DOEPTSIZ_STUPCNT_1 0x40000000U /*!<Bit 1 */
+
+/******************** Bit definition for PCGCCTL register *******************/
+#define USB_OTG_PCGCCTL_STOPCLK 0x00000001U /*!< SETUP packet count */
+#define USB_OTG_PCGCCTL_GATECLK 0x00000002U /*!<Bit 0 */
+#define USB_OTG_PCGCCTL_PHYSUSP 0x00000010U /*!<Bit 1 */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup Exported_macros
+ * @{
+ */
+
+/******************************* ADC Instances ********************************/
+#define IS_ADC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
+
+/******************************* CAN Instances ********************************/
+#define IS_CAN_ALL_INSTANCE(INSTANCE) (((INSTANCE) == CAN1) || \
+ ((INSTANCE) == CAN2))
+/****************************** DFSDM Instances *******************************/
+#define IS_DFSDM_FILTER_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DFSDM1_Filter0) || \
+ ((INSTANCE) == DFSDM1_Filter1))
+
+#define IS_DFSDM_CHANNEL_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DFSDM1_Channel0) || \
+ ((INSTANCE) == DFSDM1_Channel1) || \
+ ((INSTANCE) == DFSDM1_Channel2) || \
+ ((INSTANCE) == DFSDM1_Channel3))
+
+/******************************* CRC Instances ********************************/
+#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
+
+/******************************** DMA Instances *******************************/
+#define IS_DMA_STREAM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0) || \
+ ((INSTANCE) == DMA1_Stream1) || \
+ ((INSTANCE) == DMA1_Stream2) || \
+ ((INSTANCE) == DMA1_Stream3) || \
+ ((INSTANCE) == DMA1_Stream4) || \
+ ((INSTANCE) == DMA1_Stream5) || \
+ ((INSTANCE) == DMA1_Stream6) || \
+ ((INSTANCE) == DMA1_Stream7) || \
+ ((INSTANCE) == DMA2_Stream0) || \
+ ((INSTANCE) == DMA2_Stream1) || \
+ ((INSTANCE) == DMA2_Stream2) || \
+ ((INSTANCE) == DMA2_Stream3) || \
+ ((INSTANCE) == DMA2_Stream4) || \
+ ((INSTANCE) == DMA2_Stream5) || \
+ ((INSTANCE) == DMA2_Stream6) || \
+ ((INSTANCE) == DMA2_Stream7))
+
+/******************************* GPIO Instances *******************************/
+#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
+ ((INSTANCE) == GPIOB) || \
+ ((INSTANCE) == GPIOC) || \
+ ((INSTANCE) == GPIOD) || \
+ ((INSTANCE) == GPIOE) || \
+ ((INSTANCE) == GPIOF) || \
+ ((INSTANCE) == GPIOG) || \
+ ((INSTANCE) == GPIOH))
+
+/******************************** I2C Instances *******************************/
+#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
+ ((INSTANCE) == I2C2) || \
+ ((INSTANCE) == I2C3))
+
+/******************************** I2S Instances *******************************/
+#define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
+ ((INSTANCE) == SPI2) || \
+ ((INSTANCE) == SPI3) || \
+ ((INSTANCE) == SPI4) || \
+ ((INSTANCE) == SPI5))
+
+/*************************** I2S Extended Instances ***************************/
+#define IS_I2S_ALL_INSTANCE_EXT(PERIPH) (((INSTANCE) == SPI2) || \
+ ((INSTANCE) == SPI3) || \
+ ((INSTANCE) == I2S2ext) || \
+ ((INSTANCE) == I2S3ext))
+
+/******************************* RNG Instances ********************************/
+#define IS_RNG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RNG)
+
+/****************************** RTC Instances *********************************/
+#define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
+
+/******************************** SPI Instances *******************************/
+#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
+ ((INSTANCE) == SPI2) || \
+ ((INSTANCE) == SPI3) || \
+ ((INSTANCE) == SPI4) || \
+ ((INSTANCE) == SPI5))
+/*************************** SPI Extended Instances ***************************/
+#define IS_SPI_ALL_INSTANCE_EXT(INSTANCE) (((INSTANCE) == SPI1) || \
+ ((INSTANCE) == SPI2) || \
+ ((INSTANCE) == SPI3) || \
+ ((INSTANCE) == SPI4) || \
+ ((INSTANCE) == SPI5) || \
+ ((INSTANCE) == I2S2ext) || \
+ ((INSTANCE) == I2S3ext))
+
+/****************** TIM Instances : All supported instances *******************/
+#define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM6) || \
+ ((INSTANCE) == TIM7) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM9) || \
+ ((INSTANCE) == TIM10) || \
+ ((INSTANCE) == TIM11) || \
+ ((INSTANCE) == TIM12) || \
+ ((INSTANCE) == TIM13) || \
+ ((INSTANCE) == TIM14))
+
+/************* TIM Instances : at least 1 capture/compare channel *************/
+#define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM9) || \
+ ((INSTANCE) == TIM10) || \
+ ((INSTANCE) == TIM11) || \
+ ((INSTANCE) == TIM12) || \
+ ((INSTANCE) == TIM13) || \
+ ((INSTANCE) == TIM14))
+
+/************ TIM Instances : at least 2 capture/compare channels *************/
+#define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM9) || \
+ ((INSTANCE) == TIM12))
+
+/************ TIM Instances : at least 3 capture/compare channels *************/
+#define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8))
+
+/************ TIM Instances : at least 4 capture/compare channels *************/
+#define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8))
+
+/******************** TIM Instances : Advanced-control timers *****************/
+#define IS_TIM_ADVANCED_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM8))
+
+/******************* TIM Instances : Timer input XOR function *****************/
+#define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8))
+
+/****************** TIM Instances : DMA requests generation (UDE) *************/
+#define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM6) || \
+ ((INSTANCE) == TIM7) || \
+ ((INSTANCE) == TIM8))
+
+/************ TIM Instances : DMA requests generation (CCxDE) *****************/
+#define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8))
+
+/************ TIM Instances : DMA requests generation (COMDE) *****************/
+#define IS_TIM_CCDMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8))
+
+/******************** TIM Instances : DMA burst feature ***********************/
+#define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8))
+
+/****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/
+#define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM6) || \
+ ((INSTANCE) == TIM7) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM9) || \
+ ((INSTANCE) == TIM12))
+
+/*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
+#define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM9) || \
+ ((INSTANCE) == TIM12))
+
+/********************** TIM Instances : 32 bit Counter ************************/
+#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)(((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM5))
+
+/***************** TIM Instances : external trigger input available ************/
+#define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8))
+
+/****************** TIM Instances : remapping capability **********************/
+#define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM11))
+
+/******************* TIM Instances : output(s) available **********************/
+#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
+ ((((INSTANCE) == TIM1) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM2) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM3) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM4) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM5) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM8) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM9) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2))) \
+ || \
+ (((INSTANCE) == TIM10) && \
+ (((CHANNEL) == TIM_CHANNEL_1))) \
+ || \
+ (((INSTANCE) == TIM11) && \
+ (((CHANNEL) == TIM_CHANNEL_1))) \
+ || \
+ (((INSTANCE) == TIM12) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2))) \
+ || \
+ (((INSTANCE) == TIM13) && \
+ (((CHANNEL) == TIM_CHANNEL_1))) \
+ || \
+ (((INSTANCE) == TIM14) && \
+ (((CHANNEL) == TIM_CHANNEL_1))))
+
+/************ TIM Instances : complementary output(s) available ***************/
+#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
+ ((((INSTANCE) == TIM1) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3))) \
+ || \
+ (((INSTANCE) == TIM8) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3))))
+
+/******************** USART Instances : Synchronous mode **********************/
+#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3) || \
+ ((INSTANCE) == USART6))
+
+/******************** UART Instances : Asynchronous mode **********************/
+#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3) || \
+ ((INSTANCE) == USART6))
+
+/****************** UART Instances : Hardware Flow control ********************/
+#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3))
+
+/********************* UART Instances : Smart card mode ***********************/
+#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3) || \
+ ((INSTANCE) == USART6))
+
+/*********************** UART Instances : IRDA mode ***************************/
+#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3) || \
+ ((INSTANCE) == USART6))
+
+/*********************** PCD Instances ****************************************/
+#define IS_PCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS))
+
+/*********************** HCD Instances ****************************************/
+#define IS_HCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS))
+
+/****************************** IWDG Instances ********************************/
+#define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
+
+/****************************** WWDG Instances ********************************/
+#define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
+
+/****************************** QSPI Instances ********************************/
+#define IS_QSPI_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == QUADSPI)
+
+/***************************** FMPI2C Instances *******************************/
+#define IS_FMPI2C_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == FMPI2C1)
+
+/****************************** SDIO Instances ********************************/
+#define IS_SDIO_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SDIO)
+
+/****************************** USB Instances ********************************/
+#define IS_USB_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB_OTG_FS)
+
+/****************************** USB Exported Constants ************************/
+#define USB_OTG_FS_HOST_MAX_CHANNEL_NBR 12U
+#define USB_OTG_FS_MAX_IN_ENDPOINTS 6U /* Including EP0 */
+#define USB_OTG_FS_MAX_OUT_ENDPOINTS 6U /* Including EP0 */
+#define USB_OTG_FS_TOTAL_FIFO_SIZE 1280U /* in Bytes */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* __STM32F412Vx_H */
+
+
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Device/ST/STM32F4xx/Include/stm32f412zx.h b/Device/ST/STM32F4xx/Include/stm32f412zx.h
new file mode 100644
index 0000000..0a406a3
--- /dev/null
+++ b/Device/ST/STM32F4xx/Include/stm32f412zx.h
@@ -0,0 +1,7389 @@
+/**
+ ******************************************************************************
+ * @file stm32f412zx.h
+ * @author MCD Application Team
+ * @version V2.5.0
+ * @date 22-April-2016
+ * @brief CMSIS STM32F412Zx Device Peripheral Access Layer Header File.
+ *
+ * This file contains:
+ * - Data structures and the address mapping for all peripherals
+ * - peripherals registers declarations and bits definition
+ * - Macros to access peripheral’s registers hardware
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/** @addtogroup CMSIS
+ * @{
+ */
+
+/** @addtogroup stm32f412zx
+ * @{
+ */
+
+#ifndef __STM32F412Zx_H
+#define __STM32F412Zx_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif /* __cplusplus */
+
+
+/** @addtogroup Configuration_section_for_CMSIS
+ * @{
+ */
+
+/**
+ * @brief Configuration of the Cortex-M4 Processor and Core Peripherals
+ */
+#define __CM4_REV 0x0001U /*!< Core revision r0p1 */
+#define __MPU_PRESENT 1U /*!< STM32F4XX provides an MPU */
+#define __NVIC_PRIO_BITS 4U /*!< STM32F4XX uses 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */
+#define __FPU_PRESENT 1U /*!< FPU present */
+
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_interrupt_number_definition
+ * @{
+ */
+
+/**
+ * @brief STM32F4XX Interrupt Number Definition, according to the selected device
+ * in @ref Library_configuration_section
+ */
+typedef enum
+{
+/****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/
+ NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
+ MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */
+ BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */
+ UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */
+ SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */
+ DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */
+ PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */
+ SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */
+/****** STM32 specific Interrupt Numbers **********************************************************************/
+ WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
+ PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */
+ TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */
+ RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */
+ FLASH_IRQn = 4, /*!< FLASH global Interrupt */
+ RCC_IRQn = 5, /*!< RCC global Interrupt */
+ EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */
+ EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */
+ EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */
+ EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */
+ EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */
+ DMA1_Stream0_IRQn = 11, /*!< DMA1 Stream 0 global Interrupt */
+ DMA1_Stream1_IRQn = 12, /*!< DMA1 Stream 1 global Interrupt */
+ DMA1_Stream2_IRQn = 13, /*!< DMA1 Stream 2 global Interrupt */
+ DMA1_Stream3_IRQn = 14, /*!< DMA1 Stream 3 global Interrupt */
+ DMA1_Stream4_IRQn = 15, /*!< DMA1 Stream 4 global Interrupt */
+ DMA1_Stream5_IRQn = 16, /*!< DMA1 Stream 5 global Interrupt */
+ DMA1_Stream6_IRQn = 17, /*!< DMA1 Stream 6 global Interrupt */
+ ADC_IRQn = 18, /*!< ADC1 global Interrupts */
+ CAN1_TX_IRQn = 19, /*!< CAN1 TX Interrupt */
+ CAN1_RX0_IRQn = 20, /*!< CAN1 RX0 Interrupt */
+ CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */
+ CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */
+ EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
+ TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break interrupt and TIM9 global interrupt */
+ TIM1_UP_TIM10_IRQn = 25, /*!< TIM1 Update Interrupt and TIM10 global interrupt */
+ TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */
+ TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
+ TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
+ TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
+ TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
+ I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
+ I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
+ I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
+ I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
+ SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
+ SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
+ USART1_IRQn = 37, /*!< USART1 global Interrupt */
+ USART2_IRQn = 38, /*!< USART2 global Interrupt */
+ USART3_IRQn = 39, /*!< USART3 global Interrupt */
+ EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
+ RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */
+ OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS Wakeup through EXTI line interrupt */
+ TIM8_BRK_TIM12_IRQn = 43, /*!< TIM8 Break Interrupt and TIM12 global interrupt */
+ TIM8_UP_TIM13_IRQn = 44, /*!< TIM8 Update Interrupt and TIM13 global interrupt */
+ TIM8_TRG_COM_TIM14_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */
+ TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */
+ DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */
+ SDIO_IRQn = 49, /*!< SDIO global Interrupt */
+ TIM5_IRQn = 50, /*!< TIM5 global Interrupt */
+ SPI3_IRQn = 51, /*!< SPI3 global Interrupt */
+ TIM6_IRQn = 54, /*!< TIM6 global interrupt */
+ TIM7_IRQn = 55, /*!< TIM7 global interrupt */
+ DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */
+ DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */
+ DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */
+ DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */
+ DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */
+ DFSDM1_FLT0_IRQn = 61, /*!< DFSDM1 Filter 0 global Interrupt */
+ DFSDM1_FLT1_IRQn = 62, /*!< DFSDM1 Filter 1 global Interrupt */
+ CAN2_TX_IRQn = 63, /*!< CAN2 TX Interrupt */
+ CAN2_RX0_IRQn = 64, /*!< CAN2 RX0 Interrupt */
+ CAN2_RX1_IRQn = 65, /*!< CAN2 RX1 Interrupt */
+ CAN2_SCE_IRQn = 66, /*!< CAN2 SCE Interrupt */
+ OTG_FS_IRQn = 67, /*!< USB OTG FS global Interrupt */
+ DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */
+ DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */
+ DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */
+ USART6_IRQn = 71, /*!< USART6 global interrupt */
+ I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */
+ I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */
+ RNG_IRQn = 80, /*!< RNG global Interrupt */
+ FPU_IRQn = 81, /*!< FPU global interrupt */
+ SPI4_IRQn = 84, /*!< SPI4 global Interrupt */
+ SPI5_IRQn = 85, /*!< SPI5 global Interrupt */
+ QUADSPI_IRQn = 92, /*!< QuadSPI global Interrupt */
+ FMPI2C1_EV_IRQn = 95, /*!< FMPI2C1 Event Interrupt */
+ FMPI2C1_ER_IRQn = 96 /*!< FMPI2C1 Error Interrupt */
+} IRQn_Type;
+
+/**
+ * @}
+ */
+
+#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
+#include "system_stm32f4xx.h"
+#include <stdint.h>
+
+/** @addtogroup Peripheral_registers_structures
+ * @{
+ */
+
+/**
+ * @brief Analog to Digital Converter
+ */
+
+typedef struct
+{
+ __IO uint32_t SR; /*!< ADC status register, Address offset: 0x00 */
+ __IO uint32_t CR1; /*!< ADC control register 1, Address offset: 0x04 */
+ __IO uint32_t CR2; /*!< ADC control register 2, Address offset: 0x08 */
+ __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x0C */
+ __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x10 */
+ __IO uint32_t JOFR1; /*!< ADC injected channel data offset register 1, Address offset: 0x14 */
+ __IO uint32_t JOFR2; /*!< ADC injected channel data offset register 2, Address offset: 0x18 */
+ __IO uint32_t JOFR3; /*!< ADC injected channel data offset register 3, Address offset: 0x1C */
+ __IO uint32_t JOFR4; /*!< ADC injected channel data offset register 4, Address offset: 0x20 */
+ __IO uint32_t HTR; /*!< ADC watchdog higher threshold register, Address offset: 0x24 */
+ __IO uint32_t LTR; /*!< ADC watchdog lower threshold register, Address offset: 0x28 */
+ __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x2C */
+ __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x30 */
+ __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x34 */
+ __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x38*/
+ __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x3C */
+ __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x40 */
+ __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x44 */
+ __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x48 */
+ __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x4C */
+} ADC_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1 base address + 0x300 */
+ __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1 base address + 0x304 */
+ __IO uint32_t CDR; /*!< ADC common regular data register for dual
+ AND triple modes, Address offset: ADC1 base address + 0x308 */
+} ADC_Common_TypeDef;
+
+/**
+ * @brief Controller Area Network TxMailBox
+ */
+
+typedef struct
+{
+ __IO uint32_t TIR; /*!< CAN TX mailbox identifier register */
+ __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */
+ __IO uint32_t TDLR; /*!< CAN mailbox data low register */
+ __IO uint32_t TDHR; /*!< CAN mailbox data high register */
+} CAN_TxMailBox_TypeDef;
+
+/**
+ * @brief Controller Area Network FIFOMailBox
+ */
+
+typedef struct
+{
+ __IO uint32_t RIR; /*!< CAN receive FIFO mailbox identifier register */
+ __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */
+ __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */
+ __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */
+} CAN_FIFOMailBox_TypeDef;
+
+/**
+ * @brief Controller Area Network FilterRegister
+ */
+
+typedef struct
+{
+ __IO uint32_t FR1; /*!< CAN Filter bank register 1 */
+ __IO uint32_t FR2; /*!< CAN Filter bank register 1 */
+} CAN_FilterRegister_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t MCR; /*!< CAN master control register, Address offset: 0x00 */
+ __IO uint32_t MSR; /*!< CAN master status register, Address offset: 0x04 */
+ __IO uint32_t TSR; /*!< CAN transmit status register, Address offset: 0x08 */
+ __IO uint32_t RF0R; /*!< CAN receive FIFO 0 register, Address offset: 0x0C */
+ __IO uint32_t RF1R; /*!< CAN receive FIFO 1 register, Address offset: 0x10 */
+ __IO uint32_t IER; /*!< CAN interrupt enable register, Address offset: 0x14 */
+ __IO uint32_t ESR; /*!< CAN error status register, Address offset: 0x18 */
+ __IO uint32_t BTR; /*!< CAN bit timing register, Address offset: 0x1C */
+ uint32_t RESERVED0[88]; /*!< Reserved, 0x020 - 0x17F */
+ CAN_TxMailBox_TypeDef sTxMailBox[3]; /*!< CAN Tx MailBox, Address offset: 0x180 - 0x1AC */
+ CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; /*!< CAN FIFO MailBox, Address offset: 0x1B0 - 0x1CC */
+ uint32_t RESERVED1[12]; /*!< Reserved, 0x1D0 - 0x1FF */
+ __IO uint32_t FMR; /*!< CAN filter master register, Address offset: 0x200 */
+ __IO uint32_t FM1R; /*!< CAN filter mode register, Address offset: 0x204 */
+ uint32_t RESERVED2; /*!< Reserved, 0x208 */
+ __IO uint32_t FS1R; /*!< CAN filter scale register, Address offset: 0x20C */
+ uint32_t RESERVED3; /*!< Reserved, 0x210 */
+ __IO uint32_t FFA1R; /*!< CAN filter FIFO assignment register, Address offset: 0x214 */
+ uint32_t RESERVED4; /*!< Reserved, 0x218 */
+ __IO uint32_t FA1R; /*!< CAN filter activation register, Address offset: 0x21C */
+ uint32_t RESERVED5[8]; /*!< Reserved, 0x220-0x23F */
+ CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register, Address offset: 0x240-0x31C */
+} CAN_TypeDef;
+
+/**
+ * @brief CRC calculation unit
+ */
+
+typedef struct
+{
+ __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
+ __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
+ uint8_t RESERVED0; /*!< Reserved, 0x05 */
+ uint16_t RESERVED1; /*!< Reserved, 0x06 */
+ __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
+}CRC_TypeDef;
+
+/**
+ * @brief DFSDM module registers
+ */
+typedef struct
+{
+ __IO uint32_t FLTCR1; /*!< DFSDM control register1, Address offset: 0x100 */
+ __IO uint32_t FLTCR2; /*!< DFSDM control register2, Address offset: 0x104 */
+ __IO uint32_t FLTISR; /*!< DFSDM interrupt and status register, Address offset: 0x108 */
+ __IO uint32_t FLTICR; /*!< DFSDM interrupt flag clear register, Address offset: 0x10C */
+ __IO uint32_t FLTJCHGR; /*!< DFSDM injected channel group selection register, Address offset: 0x110 */
+ __IO uint32_t FLTFCR; /*!< DFSDM filter control register, Address offset: 0x114 */
+ __IO uint32_t FLTJDATAR; /*!< DFSDM data register for injected group, Address offset: 0x118 */
+ __IO uint32_t FLTRDATAR; /*!< DFSDM data register for regular group, Address offset: 0x11C */
+ __IO uint32_t FLTAWHTR; /*!< DFSDM analog watchdog high threshold register, Address offset: 0x120 */
+ __IO uint32_t FLTAWLTR; /*!< DFSDM analog watchdog low threshold register, Address offset: 0x124 */
+ __IO uint32_t FLTAWSR; /*!< DFSDM analog watchdog status register Address offset: 0x128 */
+ __IO uint32_t FLTAWCFR; /*!< DFSDM analog watchdog clear flag register Address offset: 0x12C */
+ __IO uint32_t FLTEXMAX; /*!< DFSDM extreme detector maximum register, Address offset: 0x130 */
+ __IO uint32_t FLTEXMIN; /*!< DFSDM extreme detector minimum register Address offset: 0x134 */
+ __IO uint32_t FLTCNVTIMR; /*!< DFSDM conversion timer, Address offset: 0x138 */
+} DFSDM_Filter_TypeDef;
+
+/**
+ * @brief DFSDM channel configuration registers
+ */
+typedef struct
+{
+ __IO uint32_t CHCFGR1; /*!< DFSDM channel configuration register1, Address offset: 0x00 */
+ __IO uint32_t CHCFGR2; /*!< DFSDM channel configuration register2, Address offset: 0x04 */
+ __IO uint32_t CHAWSCDR; /*!< DFSDM channel analog watchdog and
+ short circuit detector register, Address offset: 0x08 */
+ __IO uint32_t CHWDATAR; /*!< DFSDM channel watchdog filter data register, Address offset: 0x0C */
+ __IO uint32_t CHDATINR; /*!< DFSDM channel data input register, Address offset: 0x10 */
+} DFSDM_Channel_TypeDef;
+
+/**
+ * @brief Debug MCU
+ */
+typedef struct
+{
+ __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
+ __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
+ __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */
+ __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */
+}DBGMCU_TypeDef;
+
+
+/**
+ * @brief DMA Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< DMA stream x configuration register */
+ __IO uint32_t NDTR; /*!< DMA stream x number of data register */
+ __IO uint32_t PAR; /*!< DMA stream x peripheral address register */
+ __IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */
+ __IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */
+ __IO uint32_t FCR; /*!< DMA stream x FIFO control register */
+} DMA_Stream_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t LISR; /*!< DMA low interrupt status register, Address offset: 0x00 */
+ __IO uint32_t HISR; /*!< DMA high interrupt status register, Address offset: 0x04 */
+ __IO uint32_t LIFCR; /*!< DMA low interrupt flag clear register, Address offset: 0x08 */
+ __IO uint32_t HIFCR; /*!< DMA high interrupt flag clear register, Address offset: 0x0C */
+} DMA_TypeDef;
+
+
+/**
+ * @brief External Interrupt/Event Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t IMR; /*!< EXTI Interrupt mask register, Address offset: 0x00 */
+ __IO uint32_t EMR; /*!< EXTI Event mask register, Address offset: 0x04 */
+ __IO uint32_t RTSR; /*!< EXTI Rising trigger selection register, Address offset: 0x08 */
+ __IO uint32_t FTSR; /*!< EXTI Falling trigger selection register, Address offset: 0x0C */
+ __IO uint32_t SWIER; /*!< EXTI Software interrupt event register, Address offset: 0x10 */
+ __IO uint32_t PR; /*!< EXTI Pending register, Address offset: 0x14 */
+} EXTI_TypeDef;
+
+/**
+ * @brief FLASH Registers
+ */
+
+typedef struct
+{
+ __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */
+ __IO uint32_t KEYR; /*!< FLASH key register, Address offset: 0x04 */
+ __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x08 */
+ __IO uint32_t SR; /*!< FLASH status register, Address offset: 0x0C */
+ __IO uint32_t CR; /*!< FLASH control register, Address offset: 0x10 */
+ __IO uint32_t OPTCR; /*!< FLASH option control register , Address offset: 0x14 */
+ __IO uint32_t OPTCR1; /*!< FLASH option control register 1, Address offset: 0x18 */
+} FLASH_TypeDef;
+
+/**
+ * @brief Flexible Memory Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */
+} FSMC_Bank1_TypeDef;
+
+/**
+ * @brief Flexible Memory Controller Bank1E
+ */
+
+typedef struct
+{
+ __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */
+} FSMC_Bank1E_TypeDef;
+
+/**
+ * @brief General Purpose I/O
+ */
+
+typedef struct
+{
+ __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
+ __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */
+ __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */
+ __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
+ __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
+ __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
+ __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */
+ __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
+ __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */
+} GPIO_TypeDef;
+
+/**
+ * @brief System configuration controller
+ */
+typedef struct
+{
+ __IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */
+ __IO uint32_t PMC; /*!< SYSCFG peripheral mode configuration register, Address offset: 0x04 */
+ __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
+ uint32_t RESERVED[2]; /*!< Reserved, 0x18-0x1C */
+ __IO uint32_t CMPCR; /*!< SYSCFG Compensation cell control register, Address offset: 0x20 */
+ uint32_t RESERVED1[2]; /*!< Reserved, 0x24-0x28 */
+ __IO uint32_t CFGR; /*!< SYSCFG Configuration register, Address offset: 0x2C */
+} SYSCFG_TypeDef;
+
+/**
+ * @brief Inter-integrated Circuit Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */
+ __IO uint32_t OAR1; /*!< I2C Own address register 1, Address offset: 0x08 */
+ __IO uint32_t OAR2; /*!< I2C Own address register 2, Address offset: 0x0C */
+ __IO uint32_t DR; /*!< I2C Data register, Address offset: 0x10 */
+ __IO uint32_t SR1; /*!< I2C Status register 1, Address offset: 0x14 */
+ __IO uint32_t SR2; /*!< I2C Status register 2, Address offset: 0x18 */
+ __IO uint32_t CCR; /*!< I2C Clock control register, Address offset: 0x1C */
+ __IO uint32_t TRISE; /*!< I2C TRISE register, Address offset: 0x20 */
+ __IO uint32_t FLTR; /*!< I2C FLTR register, Address offset: 0x24 */
+} I2C_TypeDef;
+
+/**
+ * @brief Inter-integrated Circuit Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t CR1; /*!< FMPI2C Control register 1, Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< FMPI2C Control register 2, Address offset: 0x04 */
+ __IO uint32_t OAR1; /*!< FMPI2C Own address 1 register, Address offset: 0x08 */
+ __IO uint32_t OAR2; /*!< FMPI2C Own address 2 register, Address offset: 0x0C */
+ __IO uint32_t TIMINGR; /*!< FMPI2C Timing register, Address offset: 0x10 */
+ __IO uint32_t TIMEOUTR; /*!< FMPI2C Timeout register, Address offset: 0x14 */
+ __IO uint32_t ISR; /*!< FMPI2C Interrupt and status register, Address offset: 0x18 */
+ __IO uint32_t ICR; /*!< FMPI2C Interrupt clear register, Address offset: 0x1C */
+ __IO uint32_t PECR; /*!< FMPI2C PEC register, Address offset: 0x20 */
+ __IO uint32_t RXDR; /*!< FMPI2C Receive data register, Address offset: 0x24 */
+ __IO uint32_t TXDR; /*!< FMPI2C Transmit data register, Address offset: 0x28 */
+} FMPI2C_TypeDef;
+
+/**
+ * @brief Independent WATCHDOG
+ */
+
+typedef struct
+{
+ __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */
+ __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */
+ __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */
+ __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */
+} IWDG_TypeDef;
+
+/**
+ * @brief Power Control
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */
+ __IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */
+} PWR_TypeDef;
+
+/**
+ * @brief Reset and Clock Control
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */
+ __IO uint32_t PLLCFGR; /*!< RCC PLL configuration register, Address offset: 0x04 */
+ __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x08 */
+ __IO uint32_t CIR; /*!< RCC clock interrupt register, Address offset: 0x0C */
+ __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x10 */
+ __IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x14 */
+ __IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0x18 */
+ uint32_t RESERVED0; /*!< Reserved, 0x1C */
+ __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x20 */
+ __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x24 */
+ uint32_t RESERVED1[2]; /*!< Reserved, 0x28-0x2C */
+ __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clock register, Address offset: 0x30 */
+ __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clock register, Address offset: 0x34 */
+ __IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clock register, Address offset: 0x38 */
+ uint32_t RESERVED2; /*!< Reserved, 0x3C */
+ __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x40 */
+ __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x44 */
+ uint32_t RESERVED3[2]; /*!< Reserved, 0x48-0x4C */
+ __IO uint32_t AHB1LPENR; /*!< RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 */
+ __IO uint32_t AHB2LPENR; /*!< RCC AHB2 peripheral clock enable in low power mode register, Address offset: 0x54 */
+ __IO uint32_t AHB3LPENR; /*!< RCC AHB3 peripheral clock enable in low power mode register, Address offset: 0x58 */
+ uint32_t RESERVED4; /*!< Reserved, 0x5C */
+ __IO uint32_t APB1LPENR; /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 */
+ __IO uint32_t APB2LPENR; /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 */
+ uint32_t RESERVED5[2]; /*!< Reserved, 0x68-0x6C */
+ __IO uint32_t BDCR; /*!< RCC Backup domain control register, Address offset: 0x70 */
+ __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x74 */
+ uint32_t RESERVED6[2]; /*!< Reserved, 0x78-0x7C */
+ __IO uint32_t SSCGR; /*!< RCC spread spectrum clock generation register, Address offset: 0x80 */
+ __IO uint32_t PLLI2SCFGR; /*!< RCC PLLI2S configuration register, Address offset: 0x84 */
+ uint32_t RESERVED7; /*!< Reserved, 0x84 */
+ __IO uint32_t DCKCFGR; /*!< RCC Dedicated Clocks configuration register, Address offset: 0x8C */
+ __IO uint32_t CKGATENR; /*!< RCC Clocks Gated ENable Register, Address offset: 0x90 */
+ __IO uint32_t DCKCFGR2; /*!< RCC Dedicated Clocks configuration register 2, Address offset: 0x94 */
+} RCC_TypeDef;
+
+/**
+ * @brief Real-Time Clock
+ */
+
+typedef struct
+{
+ __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
+ __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */
+ __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */
+ __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */
+ __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */
+ __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */
+ __IO uint32_t CALIBR; /*!< RTC calibration register, Address offset: 0x18 */
+ __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */
+ __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */
+ __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */
+ __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */
+ __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */
+ __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */
+ __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */
+ __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */
+ __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */
+ __IO uint32_t TAFCR; /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */
+ __IO uint32_t ALRMASSR;/*!< RTC alarm A sub second register, Address offset: 0x44 */
+ __IO uint32_t ALRMBSSR;/*!< RTC alarm B sub second register, Address offset: 0x48 */
+ uint32_t RESERVED7; /*!< Reserved, 0x4C */
+ __IO uint32_t BKP0R; /*!< RTC backup register 1, Address offset: 0x50 */
+ __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */
+ __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */
+ __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */
+ __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */
+ __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */
+ __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */
+ __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */
+ __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */
+ __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */
+ __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */
+ __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */
+ __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */
+ __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */
+ __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */
+ __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */
+ __IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */
+ __IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */
+ __IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */
+ __IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */
+} RTC_TypeDef;
+
+
+/**
+ * @brief SD host Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t POWER; /*!< SDIO power control register, Address offset: 0x00 */
+ __IO uint32_t CLKCR; /*!< SDI clock control register, Address offset: 0x04 */
+ __IO uint32_t ARG; /*!< SDIO argument register, Address offset: 0x08 */
+ __IO uint32_t CMD; /*!< SDIO command register, Address offset: 0x0C */
+ __I uint32_t RESPCMD; /*!< SDIO command response register, Address offset: 0x10 */
+ __I uint32_t RESP1; /*!< SDIO response 1 register, Address offset: 0x14 */
+ __I uint32_t RESP2; /*!< SDIO response 2 register, Address offset: 0x18 */
+ __I uint32_t RESP3; /*!< SDIO response 3 register, Address offset: 0x1C */
+ __I uint32_t RESP4; /*!< SDIO response 4 register, Address offset: 0x20 */
+ __IO uint32_t DTIMER; /*!< SDIO data timer register, Address offset: 0x24 */
+ __IO uint32_t DLEN; /*!< SDIO data length register, Address offset: 0x28 */
+ __IO uint32_t DCTRL; /*!< SDIO data control register, Address offset: 0x2C */
+ __I uint32_t DCOUNT; /*!< SDIO data counter register, Address offset: 0x30 */
+ __I uint32_t STA; /*!< SDIO status register, Address offset: 0x34 */
+ __IO uint32_t ICR; /*!< SDIO interrupt clear register, Address offset: 0x38 */
+ __IO uint32_t MASK; /*!< SDIO mask register, Address offset: 0x3C */
+ uint32_t RESERVED0[2]; /*!< Reserved, 0x40-0x44 */
+ __I uint32_t FIFOCNT; /*!< SDIO FIFO counter register, Address offset: 0x48 */
+ uint32_t RESERVED1[13]; /*!< Reserved, 0x4C-0x7C */
+ __IO uint32_t FIFO; /*!< SDIO data FIFO register, Address offset: 0x80 */
+} SDIO_TypeDef;
+
+/**
+ * @brief Serial Peripheral Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t CR1; /*!< SPI control register 1 (not used in I2S mode), Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< SPI control register 2, Address offset: 0x04 */
+ __IO uint32_t SR; /*!< SPI status register, Address offset: 0x08 */
+ __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */
+ __IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
+ __IO uint32_t RXCRCR; /*!< SPI RX CRC register (not used in I2S mode), Address offset: 0x14 */
+ __IO uint32_t TXCRCR; /*!< SPI TX CRC register (not used in I2S mode), Address offset: 0x18 */
+ __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */
+ __IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */
+} SPI_TypeDef;
+
+/**
+ * @brief QUAD Serial Peripheral Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< QUADSPI Control register, Address offset: 0x00 */
+ __IO uint32_t DCR; /*!< QUADSPI Device Configuration register, Address offset: 0x04 */
+ __IO uint32_t SR; /*!< QUADSPI Status register, Address offset: 0x08 */
+ __IO uint32_t FCR; /*!< QUADSPI Flag Clear register, Address offset: 0x0C */
+ __IO uint32_t DLR; /*!< QUADSPI Data Length register, Address offset: 0x10 */
+ __IO uint32_t CCR; /*!< QUADSPI Communication Configuration register, Address offset: 0x14 */
+ __IO uint32_t AR; /*!< QUADSPI Address register, Address offset: 0x18 */
+ __IO uint32_t ABR; /*!< QUADSPI Alternate Bytes register, Address offset: 0x1C */
+ __IO uint32_t DR; /*!< QUADSPI Data register, Address offset: 0x20 */
+ __IO uint32_t PSMKR; /*!< QUADSPI Polling Status Mask register, Address offset: 0x24 */
+ __IO uint32_t PSMAR; /*!< QUADSPI Polling Status Match register, Address offset: 0x28 */
+ __IO uint32_t PIR; /*!< QUADSPI Polling Interval register, Address offset: 0x2C */
+ __IO uint32_t LPTR; /*!< QUADSPI Low Power Timeout register, Address offset: 0x30 */
+} QUADSPI_TypeDef;
+
+/**
+ * @brief TIM
+ */
+
+typedef struct
+{
+ __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
+ __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */
+ __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
+ __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
+ __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
+ __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
+ __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
+ __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
+ __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
+ __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */
+ __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
+ __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */
+ __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
+ __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
+ __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
+ __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
+ __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
+ __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
+ __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */
+ __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */
+} TIM_TypeDef;
+
+/**
+ * @brief Universal Synchronous Asynchronous Receiver Transmitter
+ */
+
+typedef struct
+{
+ __IO uint32_t SR; /*!< USART Status register, Address offset: 0x00 */
+ __IO uint32_t DR; /*!< USART Data register, Address offset: 0x04 */
+ __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x08 */
+ __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x0C */
+ __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x10 */
+ __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x14 */
+ __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x18 */
+} USART_TypeDef;
+
+/**
+ * @brief Window WATCHDOG
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
+ __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
+ __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
+} WWDG_TypeDef;
+
+
+/**
+ * @brief RNG
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */
+ __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */
+ __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */
+} RNG_TypeDef;
+
+
+/**
+ * @brief USB_OTG_Core_Registers
+ */
+typedef struct
+{
+ __IO uint32_t GOTGCTL; /*!< USB_OTG Control and Status Register 000h*/
+ __IO uint32_t GOTGINT; /*!< USB_OTG Interrupt Register 004h*/
+ __IO uint32_t GAHBCFG; /*!< Core AHB Configuration Register 008h*/
+ __IO uint32_t GUSBCFG; /*!< Core USB Configuration Register 00Ch*/
+ __IO uint32_t GRSTCTL; /*!< Core Reset Register 010h*/
+ __IO uint32_t GINTSTS; /*!< Core Interrupt Register 014h*/
+ __IO uint32_t GINTMSK; /*!< Core Interrupt Mask Register 018h*/
+ __IO uint32_t GRXSTSR; /*!< Receive Sts Q Read Register 01Ch*/
+ __IO uint32_t GRXSTSP; /*!< Receive Sts Q Read & POP Register 020h*/
+ __IO uint32_t GRXFSIZ; /*!< Receive FIFO Size Register 024h*/
+ __IO uint32_t DIEPTXF0_HNPTXFSIZ; /*!< EP0 / Non Periodic Tx FIFO Size Register 028h*/
+ __IO uint32_t HNPTXSTS; /*!< Non Periodic Tx FIFO/Queue Sts reg 02Ch*/
+ uint32_t Reserved30[2]; /*!< Reserved 030h*/
+ __IO uint32_t GCCFG; /*!< General Purpose IO Register 038h*/
+ __IO uint32_t CID; /*!< User ID Register 03Ch*/
+ uint32_t Reserved5[3]; /*!< Reserved 040h-048h*/
+ __IO uint32_t GHWCFG3; /*!< User HW config3 04Ch*/
+ uint32_t Reserved6; /*!< Reserved 050h*/
+ __IO uint32_t GLPMCFG; /*!< LPM Register 054h*/
+ uint32_t Reserved; /*!< Reserved 058h */
+ __IO uint32_t GDFIFOCFG; /*!< DFIFO Software Config Register 05Ch */
+ uint32_t Reserved43[40]; /*!< Reserved 058h-0FFh */
+ __IO uint32_t HPTXFSIZ; /*!< Host Periodic Tx FIFO Size Reg 100h*/
+ __IO uint32_t DIEPTXF[0x0F]; /*!< dev Periodic Transmit FIFO */
+} USB_OTG_GlobalTypeDef;
+
+
+/**
+ * @brief USB_OTG_device_Registers
+ */
+typedef struct
+{
+ __IO uint32_t DCFG; /*!< dev Configuration Register 800h */
+ __IO uint32_t DCTL; /*!< dev Control Register 804h */
+ __IO uint32_t DSTS; /*!< dev Status Register (RO) 808h */
+ uint32_t Reserved0C; /*!< Reserved 80Ch */
+ __IO uint32_t DIEPMSK; /*!< dev IN Endpoint Mask 810h */
+ __IO uint32_t DOEPMSK; /*!< dev OUT Endpoint Mask 814h */
+ __IO uint32_t DAINT; /*!< dev All Endpoints Itr Reg 818h */
+ __IO uint32_t DAINTMSK; /*!< dev All Endpoints Itr Mask 81Ch */
+ uint32_t Reserved20; /*!< Reserved 820h */
+ uint32_t Reserved9; /*!< Reserved 824h */
+ __IO uint32_t DVBUSDIS; /*!< dev VBUS discharge Register 828h */
+ __IO uint32_t DVBUSPULSE; /*!< dev VBUS Pulse Register 82Ch */
+ __IO uint32_t DTHRCTL; /*!< dev threshold 830h */
+ __IO uint32_t DIEPEMPMSK; /*!< dev empty msk 834h */
+ __IO uint32_t DEACHINT; /*!< dedicated EP interrupt 838h */
+ __IO uint32_t DEACHMSK; /*!< dedicated EP msk 83Ch */
+ uint32_t Reserved40; /*!< dedicated EP mask 840h */
+ __IO uint32_t DINEP1MSK; /*!< dedicated EP mask 844h */
+ uint32_t Reserved44[15]; /*!< Reserved 844-87Ch */
+ __IO uint32_t DOUTEP1MSK; /*!< dedicated EP msk 884h */
+} USB_OTG_DeviceTypeDef;
+
+
+/**
+ * @brief USB_OTG_IN_Endpoint-Specific_Register
+ */
+typedef struct
+{
+ __IO uint32_t DIEPCTL; /*!< dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h */
+ uint32_t Reserved04; /*!< Reserved 900h + (ep_num * 20h) + 04h */
+ __IO uint32_t DIEPINT; /*!< dev IN Endpoint Itr Reg 900h + (ep_num * 20h) + 08h */
+ uint32_t Reserved0C; /*!< Reserved 900h + (ep_num * 20h) + 0Ch */
+ __IO uint32_t DIEPTSIZ; /*!< IN Endpoint Txfer Size 900h + (ep_num * 20h) + 10h */
+ __IO uint32_t DIEPDMA; /*!< IN Endpoint DMA Address Reg 900h + (ep_num * 20h) + 14h */
+ __IO uint32_t DTXFSTS; /*!< IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h */
+ uint32_t Reserved18; /*!< Reserved 900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch */
+} USB_OTG_INEndpointTypeDef;
+
+
+/**
+ * @brief USB_OTG_OUT_Endpoint-Specific_Registers
+ */
+typedef struct
+{
+ __IO uint32_t DOEPCTL; /*!< dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h */
+ uint32_t Reserved04; /*!< Reserved B00h + (ep_num * 20h) + 04h */
+ __IO uint32_t DOEPINT; /*!< dev OUT Endpoint Itr Reg B00h + (ep_num * 20h) + 08h */
+ uint32_t Reserved0C; /*!< Reserved B00h + (ep_num * 20h) + 0Ch */
+ __IO uint32_t DOEPTSIZ; /*!< dev OUT Endpoint Txfer Size B00h + (ep_num * 20h) + 10h */
+ __IO uint32_t DOEPDMA; /*!< dev OUT Endpoint DMA Address B00h + (ep_num * 20h) + 14h */
+ uint32_t Reserved18[2]; /*!< Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch */
+} USB_OTG_OUTEndpointTypeDef;
+
+
+/**
+ * @brief USB_OTG_Host_Mode_Register_Structures
+ */
+typedef struct
+{
+ __IO uint32_t HCFG; /*!< Host Configuration Register 400h */
+ __IO uint32_t HFIR; /*!< Host Frame Interval Register 404h */
+ __IO uint32_t HFNUM; /*!< Host Frame Nbr/Frame Remaining 408h */
+ uint32_t Reserved40C; /*!< Reserved 40Ch */
+ __IO uint32_t HPTXSTS; /*!< Host Periodic Tx FIFO/ Queue Status 410h */
+ __IO uint32_t HAINT; /*!< Host All Channels Interrupt Register 414h */
+ __IO uint32_t HAINTMSK; /*!< Host All Channels Interrupt Mask 418h */
+} USB_OTG_HostTypeDef;
+
+
+/**
+ * @brief USB_OTG_Host_Channel_Specific_Registers
+ */
+typedef struct
+{
+ __IO uint32_t HCCHAR; /*!< Host Channel Characteristics Register 500h */
+ __IO uint32_t HCSPLT; /*!< Host Channel Split Control Register 504h */
+ __IO uint32_t HCINT; /*!< Host Channel Interrupt Register 508h */
+ __IO uint32_t HCINTMSK; /*!< Host Channel Interrupt Mask Register 50Ch */
+ __IO uint32_t HCTSIZ; /*!< Host Channel Transfer Size Register 510h */
+ __IO uint32_t HCDMA; /*!< Host Channel DMA Address Register 514h */
+ uint32_t Reserved[2]; /*!< Reserved */
+} USB_OTG_HostChannelTypeDef;
+
+
+/**
+ * @brief Peripheral_memory_map
+ */
+#define FLASH_BASE 0x08000000U /*!< FLASH(up to 1 MB) base address in the alias region */
+#define SRAM1_BASE 0x20000000U /*!< SRAM1(256 KB) base address in the alias region */
+#define PERIPH_BASE 0x40000000U /*!< Peripheral base address in the alias region */
+#define FSMC_R_BASE 0xA0000000U /*!< FSMC registers base address */
+#define QSPI_R_BASE 0xA0001000U /*!< QuadSPI registers base address */
+
+#define SRAM1_BB_BASE 0x22000000U /*!< SRAM1(256 KB) base address in the bit-band region */
+#define PERIPH_BB_BASE 0x42000000U /*!< Peripheral base address in the bit-band region */
+#define FLASH_END 0x080FFFFFU /*!< FLASH end address */
+
+/* Legacy defines */
+#define SRAM_BASE SRAM1_BASE
+#define SRAM_BB_BASE SRAM1_BB_BASE
+
+/*!< Peripheral memory map */
+#define APB1PERIPH_BASE PERIPH_BASE
+#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000U)
+#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000U)
+#define AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000U)
+
+/*!< APB1 peripherals */
+#define TIM2_BASE (APB1PERIPH_BASE + 0x0000U)
+#define TIM3_BASE (APB1PERIPH_BASE + 0x0400U)
+#define TIM4_BASE (APB1PERIPH_BASE + 0x0800U)
+#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00U)
+#define TIM6_BASE (APB1PERIPH_BASE + 0x1000U)
+#define TIM7_BASE (APB1PERIPH_BASE + 0x1400U)
+#define TIM12_BASE (APB1PERIPH_BASE + 0x1800U)
+#define TIM13_BASE (APB1PERIPH_BASE + 0x1C00U)
+#define TIM14_BASE (APB1PERIPH_BASE + 0x2000U)
+#define RTC_BASE (APB1PERIPH_BASE + 0x2800U)
+#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00U)
+#define IWDG_BASE (APB1PERIPH_BASE + 0x3000U)
+#define I2S2ext_BASE (APB1PERIPH_BASE + 0x3400U)
+#define SPI2_BASE (APB1PERIPH_BASE + 0x3800U)
+#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00U)
+#define I2S3ext_BASE (APB1PERIPH_BASE + 0x4000U)
+#define USART2_BASE (APB1PERIPH_BASE + 0x4400U)
+#define USART3_BASE (APB1PERIPH_BASE + 0x4800U)
+#define I2C1_BASE (APB1PERIPH_BASE + 0x5400U)
+#define I2C2_BASE (APB1PERIPH_BASE + 0x5800U)
+#define I2C3_BASE (APB1PERIPH_BASE + 0x5C00U)
+#define FMPI2C1_BASE (APB1PERIPH_BASE + 0x6000U)
+#define CAN1_BASE (APB1PERIPH_BASE + 0x6400U)
+#define CAN2_BASE (APB1PERIPH_BASE + 0x6800U)
+#define PWR_BASE (APB1PERIPH_BASE + 0x7000U)
+
+/*!< APB2 peripherals */
+#define TIM1_BASE (APB2PERIPH_BASE + 0x0000U)
+#define TIM8_BASE (APB2PERIPH_BASE + 0x0400U)
+#define USART1_BASE (APB2PERIPH_BASE + 0x1000U)
+#define USART6_BASE (APB2PERIPH_BASE + 0x1400U)
+#define ADC1_BASE (APB2PERIPH_BASE + 0x2000U)
+#define ADC_BASE (APB2PERIPH_BASE + 0x2300U)
+#define SDIO_BASE (APB2PERIPH_BASE + 0x2C00U)
+#define SPI1_BASE (APB2PERIPH_BASE + 0x3000U)
+#define SPI4_BASE (APB2PERIPH_BASE + 0x3400U)
+#define SYSCFG_BASE (APB2PERIPH_BASE + 0x3800U)
+#define EXTI_BASE (APB2PERIPH_BASE + 0x3C00U)
+#define TIM9_BASE (APB2PERIPH_BASE + 0x4000U)
+#define TIM10_BASE (APB2PERIPH_BASE + 0x4400U)
+#define TIM11_BASE (APB2PERIPH_BASE + 0x4800U)
+#define SPI5_BASE (APB2PERIPH_BASE + 0x5000U)
+#define DFSDM1_BASE (APB2PERIPH_BASE + 0x6000U)
+#define DFSDM1_Channel0_BASE (DFSDM1_BASE + 0x00U)
+#define DFSDM1_Channel1_BASE (DFSDM1_BASE + 0x20U)
+#define DFSDM1_Channel2_BASE (DFSDM1_BASE + 0x40U)
+#define DFSDM1_Channel3_BASE (DFSDM1_BASE + 0x60U)
+#define DFSDM1_Filter0_BASE (DFSDM1_BASE + 0x100U)
+#define DFSDM1_Filter1_BASE (DFSDM1_BASE + 0x180U)
+
+/*!< AHB1 peripherals */
+#define GPIOA_BASE (AHB1PERIPH_BASE + 0x0000U)
+#define GPIOB_BASE (AHB1PERIPH_BASE + 0x0400U)
+#define GPIOC_BASE (AHB1PERIPH_BASE + 0x0800U)
+#define GPIOD_BASE (AHB1PERIPH_BASE + 0x0C00U)
+#define GPIOE_BASE (AHB1PERIPH_BASE + 0x1000U)
+#define GPIOF_BASE (AHB1PERIPH_BASE + 0x1400U)
+#define GPIOG_BASE (AHB1PERIPH_BASE + 0x1800U)
+#define GPIOH_BASE (AHB1PERIPH_BASE + 0x1C00U)
+#define CRC_BASE (AHB1PERIPH_BASE + 0x3000U)
+#define RCC_BASE (AHB1PERIPH_BASE + 0x3800U)
+#define FLASH_R_BASE (AHB1PERIPH_BASE + 0x3C00U)
+#define DMA1_BASE (AHB1PERIPH_BASE + 0x6000U)
+#define DMA1_Stream0_BASE (DMA1_BASE + 0x010U)
+#define DMA1_Stream1_BASE (DMA1_BASE + 0x028U)
+#define DMA1_Stream2_BASE (DMA1_BASE + 0x040U)
+#define DMA1_Stream3_BASE (DMA1_BASE + 0x058U)
+#define DMA1_Stream4_BASE (DMA1_BASE + 0x070U)
+#define DMA1_Stream5_BASE (DMA1_BASE + 0x088U)
+#define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0U)
+#define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8U)
+#define DMA2_BASE (AHB1PERIPH_BASE + 0x6400U)
+#define DMA2_Stream0_BASE (DMA2_BASE + 0x010U)
+#define DMA2_Stream1_BASE (DMA2_BASE + 0x028U)
+#define DMA2_Stream2_BASE (DMA2_BASE + 0x040U)
+#define DMA2_Stream3_BASE (DMA2_BASE + 0x058U)
+#define DMA2_Stream4_BASE (DMA2_BASE + 0x070U)
+#define DMA2_Stream5_BASE (DMA2_BASE + 0x088U)
+#define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0U)
+#define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8U)
+
+/*!< AHB2 peripherals */
+#define RNG_BASE (AHB2PERIPH_BASE + 0x60800U)
+
+/*!< FSMC Bankx registers base address */
+#define FSMC_Bank1_R_BASE (FSMC_R_BASE + 0x0000U)
+#define FSMC_Bank1E_R_BASE (FSMC_R_BASE + 0x0104U)
+
+/* Debug MCU registers base address */
+#define DBGMCU_BASE 0xE0042000U
+
+/*!< USB registers base address */
+#define USB_OTG_FS_PERIPH_BASE 0x50000000U
+
+#define USB_OTG_GLOBAL_BASE 0x000U
+#define USB_OTG_DEVICE_BASE 0x800U
+#define USB_OTG_IN_ENDPOINT_BASE 0x900U
+#define USB_OTG_OUT_ENDPOINT_BASE 0xB00U
+#define USB_OTG_EP_REG_SIZE 0x20U
+#define USB_OTG_HOST_BASE 0x400U
+#define USB_OTG_HOST_PORT_BASE 0x440U
+#define USB_OTG_HOST_CHANNEL_BASE 0x500U
+#define USB_OTG_HOST_CHANNEL_SIZE 0x20U
+#define USB_OTG_PCGCCTL_BASE 0xE00U
+#define USB_OTG_FIFO_BASE 0x1000U
+#define USB_OTG_FIFO_SIZE 0x1000U
+
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_declaration
+ * @{
+ */
+#define TIM2 ((TIM_TypeDef *) TIM2_BASE)
+#define TIM3 ((TIM_TypeDef *) TIM3_BASE)
+#define TIM4 ((TIM_TypeDef *) TIM4_BASE)
+#define TIM5 ((TIM_TypeDef *) TIM5_BASE)
+#define TIM6 ((TIM_TypeDef *) TIM6_BASE)
+#define TIM7 ((TIM_TypeDef *) TIM7_BASE)
+#define TIM12 ((TIM_TypeDef *) TIM12_BASE)
+#define TIM13 ((TIM_TypeDef *) TIM13_BASE)
+#define TIM14 ((TIM_TypeDef *) TIM14_BASE)
+#define RTC ((RTC_TypeDef *) RTC_BASE)
+#define WWDG ((WWDG_TypeDef *) WWDG_BASE)
+#define IWDG ((IWDG_TypeDef *) IWDG_BASE)
+#define I2S2ext ((SPI_TypeDef *) I2S2ext_BASE)
+#define SPI2 ((SPI_TypeDef *) SPI2_BASE)
+#define SPI3 ((SPI_TypeDef *) SPI3_BASE)
+#define I2S3ext ((SPI_TypeDef *) I2S3ext_BASE)
+#define USART2 ((USART_TypeDef *) USART2_BASE)
+#define USART3 ((USART_TypeDef *) USART3_BASE)
+#define I2C1 ((I2C_TypeDef *) I2C1_BASE)
+#define I2C2 ((I2C_TypeDef *) I2C2_BASE)
+#define I2C3 ((I2C_TypeDef *) I2C3_BASE)
+#define FMPI2C1 ((FMPI2C_TypeDef *) FMPI2C1_BASE)
+#define CAN1 ((CAN_TypeDef *) CAN1_BASE)
+#define CAN2 ((CAN_TypeDef *) CAN2_BASE)
+#define PWR ((PWR_TypeDef *) PWR_BASE)
+#define TIM1 ((TIM_TypeDef *) TIM1_BASE)
+#define TIM8 ((TIM_TypeDef *) TIM8_BASE)
+#define USART1 ((USART_TypeDef *) USART1_BASE)
+#define USART6 ((USART_TypeDef *) USART6_BASE)
+#define ADC ((ADC_Common_TypeDef *) ADC_BASE)
+#define ADC1 ((ADC_TypeDef *) ADC1_BASE)
+#define SDIO ((SDIO_TypeDef *) SDIO_BASE)
+#define SPI1 ((SPI_TypeDef *) SPI1_BASE)
+#define SPI4 ((SPI_TypeDef *) SPI4_BASE)
+#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
+#define EXTI ((EXTI_TypeDef *) EXTI_BASE)
+#define TIM9 ((TIM_TypeDef *) TIM9_BASE)
+#define TIM10 ((TIM_TypeDef *) TIM10_BASE)
+#define TIM11 ((TIM_TypeDef *) TIM11_BASE)
+#define SPI5 ((SPI_TypeDef *) SPI5_BASE)
+#define DFSDM1_Channel0 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel0_BASE)
+#define DFSDM1_Channel1 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel1_BASE)
+#define DFSDM1_Channel2 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel2_BASE)
+#define DFSDM1_Channel3 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel3_BASE)
+#define DFSDM1_Filter0 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter0_BASE)
+#define DFSDM1_Filter1 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter1_BASE)
+#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
+#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
+#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
+#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
+#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
+#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
+#define GPIOG ((GPIO_TypeDef *) GPIOG_BASE)
+#define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
+#define CRC ((CRC_TypeDef *) CRC_BASE)
+#define RCC ((RCC_TypeDef *) RCC_BASE)
+#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
+#define DMA1 ((DMA_TypeDef *) DMA1_BASE)
+#define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)
+#define DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)
+#define DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)
+#define DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)
+#define DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)
+#define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)
+#define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)
+#define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)
+#define DMA2 ((DMA_TypeDef *) DMA2_BASE)
+#define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)
+#define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
+#define DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)
+#define DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)
+#define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)
+#define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)
+#define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)
+#define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)
+#define RNG ((RNG_TypeDef *) RNG_BASE)
+#define FSMC_Bank1 ((FSMC_Bank1_TypeDef *) FSMC_Bank1_R_BASE)
+#define FSMC_Bank1E ((FSMC_Bank1E_TypeDef *) FSMC_Bank1E_R_BASE)
+#define QUADSPI ((QUADSPI_TypeDef *) QSPI_R_BASE)
+
+#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
+
+#define USB_OTG_FS ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE)
+
+/**
+ * @}
+ */
+
+/** @addtogroup Exported_constants
+ * @{
+ */
+
+ /** @addtogroup Peripheral_Registers_Bits_Definition
+ * @{
+ */
+
+/******************************************************************************/
+/* Peripheral Registers_Bits_Definition */
+/******************************************************************************/
+
+/******************************************************************************/
+/* */
+/* Analog to Digital Converter */
+/* */
+/******************************************************************************/
+/******************** Bit definition for ADC_SR register ********************/
+#define ADC_SR_AWD 0x00000001U /*!<Analog watchdog flag */
+#define ADC_SR_EOC 0x00000002U /*!<End of conversion */
+#define ADC_SR_JEOC 0x00000004U /*!<Injected channel end of conversion */
+#define ADC_SR_JSTRT 0x00000008U /*!<Injected channel Start flag */
+#define ADC_SR_STRT 0x00000010U /*!<Regular channel Start flag */
+#define ADC_SR_OVR 0x00000020U /*!<Overrun flag */
+
+/******************* Bit definition for ADC_CR1 register ********************/
+#define ADC_CR1_AWDCH 0x0000001FU /*!<AWDCH[4:0] bits (Analog watchdog channel select bits) */
+#define ADC_CR1_AWDCH_0 0x00000001U /*!<Bit 0 */
+#define ADC_CR1_AWDCH_1 0x00000002U /*!<Bit 1 */
+#define ADC_CR1_AWDCH_2 0x00000004U /*!<Bit 2 */
+#define ADC_CR1_AWDCH_3 0x00000008U /*!<Bit 3 */
+#define ADC_CR1_AWDCH_4 0x00000010U /*!<Bit 4 */
+#define ADC_CR1_EOCIE 0x00000020U /*!<Interrupt enable for EOC */
+#define ADC_CR1_AWDIE 0x00000040U /*!<AAnalog Watchdog interrupt enable */
+#define ADC_CR1_JEOCIE 0x00000080U /*!<Interrupt enable for injected channels */
+#define ADC_CR1_SCAN 0x00000100U /*!<Scan mode */
+#define ADC_CR1_AWDSGL 0x00000200U /*!<Enable the watchdog on a single channel in scan mode */
+#define ADC_CR1_JAUTO 0x00000400U /*!<Automatic injected group conversion */
+#define ADC_CR1_DISCEN 0x00000800U /*!<Discontinuous mode on regular channels */
+#define ADC_CR1_JDISCEN 0x00001000U /*!<Discontinuous mode on injected channels */
+#define ADC_CR1_DISCNUM 0x0000E000U /*!<DISCNUM[2:0] bits (Discontinuous mode channel count) */
+#define ADC_CR1_DISCNUM_0 0x00002000U /*!<Bit 0 */
+#define ADC_CR1_DISCNUM_1 0x00004000U /*!<Bit 1 */
+#define ADC_CR1_DISCNUM_2 0x00008000U /*!<Bit 2 */
+#define ADC_CR1_JAWDEN 0x00400000U /*!<Analog watchdog enable on injected channels */
+#define ADC_CR1_AWDEN 0x00800000U /*!<Analog watchdog enable on regular channels */
+#define ADC_CR1_RES 0x03000000U /*!<RES[2:0] bits (Resolution) */
+#define ADC_CR1_RES_0 0x01000000U /*!<Bit 0 */
+#define ADC_CR1_RES_1 0x02000000U /*!<Bit 1 */
+#define ADC_CR1_OVRIE 0x04000000U /*!<overrun interrupt enable */
+
+/******************* Bit definition for ADC_CR2 register ********************/
+#define ADC_CR2_ADON 0x00000001U /*!<A/D Converter ON / OFF */
+#define ADC_CR2_CONT 0x00000002U /*!<Continuous Conversion */
+#define ADC_CR2_DMA 0x00000100U /*!<Direct Memory access mode */
+#define ADC_CR2_DDS 0x00000200U /*!<DMA disable selection (Single ADC) */
+#define ADC_CR2_EOCS 0x00000400U /*!<End of conversion selection */
+#define ADC_CR2_ALIGN 0x00000800U /*!<Data Alignment */
+#define ADC_CR2_JEXTSEL 0x000F0000U /*!<JEXTSEL[3:0] bits (External event select for injected group) */
+#define ADC_CR2_JEXTSEL_0 0x00010000U /*!<Bit 0 */
+#define ADC_CR2_JEXTSEL_1 0x00020000U /*!<Bit 1 */
+#define ADC_CR2_JEXTSEL_2 0x00040000U /*!<Bit 2 */
+#define ADC_CR2_JEXTSEL_3 0x00080000U /*!<Bit 3 */
+#define ADC_CR2_JEXTEN 0x00300000U /*!<JEXTEN[1:0] bits (External Trigger Conversion mode for injected channelsp) */
+#define ADC_CR2_JEXTEN_0 0x00100000U /*!<Bit 0 */
+#define ADC_CR2_JEXTEN_1 0x00200000U /*!<Bit 1 */
+#define ADC_CR2_JSWSTART 0x00400000U /*!<Start Conversion of injected channels */
+#define ADC_CR2_EXTSEL 0x0F000000U /*!<EXTSEL[3:0] bits (External Event Select for regular group) */
+#define ADC_CR2_EXTSEL_0 0x01000000U /*!<Bit 0 */
+#define ADC_CR2_EXTSEL_1 0x02000000U /*!<Bit 1 */
+#define ADC_CR2_EXTSEL_2 0x04000000U /*!<Bit 2 */
+#define ADC_CR2_EXTSEL_3 0x08000000U /*!<Bit 3 */
+#define ADC_CR2_EXTEN 0x30000000U /*!<EXTEN[1:0] bits (External Trigger Conversion mode for regular channelsp) */
+#define ADC_CR2_EXTEN_0 0x10000000U /*!<Bit 0 */
+#define ADC_CR2_EXTEN_1 0x20000000U /*!<Bit 1 */
+#define ADC_CR2_SWSTART 0x40000000U /*!<Start Conversion of regular channels */
+
+/****************** Bit definition for ADC_SMPR1 register *******************/
+#define ADC_SMPR1_SMP10 0x00000007U /*!<SMP10[2:0] bits (Channel 10 Sample time selection) */
+#define ADC_SMPR1_SMP10_0 0x00000001U /*!<Bit 0 */
+#define ADC_SMPR1_SMP10_1 0x00000002U /*!<Bit 1 */
+#define ADC_SMPR1_SMP10_2 0x00000004U /*!<Bit 2 */
+#define ADC_SMPR1_SMP11 0x00000038U /*!<SMP11[2:0] bits (Channel 11 Sample time selection) */
+#define ADC_SMPR1_SMP11_0 0x00000008U /*!<Bit 0 */
+#define ADC_SMPR1_SMP11_1 0x00000010U /*!<Bit 1 */
+#define ADC_SMPR1_SMP11_2 0x00000020U /*!<Bit 2 */
+#define ADC_SMPR1_SMP12 0x000001C0U /*!<SMP12[2:0] bits (Channel 12 Sample time selection) */
+#define ADC_SMPR1_SMP12_0 0x00000040U /*!<Bit 0 */
+#define ADC_SMPR1_SMP12_1 0x00000080U /*!<Bit 1 */
+#define ADC_SMPR1_SMP12_2 0x00000100U /*!<Bit 2 */
+#define ADC_SMPR1_SMP13 0x00000E00U /*!<SMP13[2:0] bits (Channel 13 Sample time selection) */
+#define ADC_SMPR1_SMP13_0 0x00000200U /*!<Bit 0 */
+#define ADC_SMPR1_SMP13_1 0x00000400U /*!<Bit 1 */
+#define ADC_SMPR1_SMP13_2 0x00000800U /*!<Bit 2 */
+#define ADC_SMPR1_SMP14 0x00007000U /*!<SMP14[2:0] bits (Channel 14 Sample time selection) */
+#define ADC_SMPR1_SMP14_0 0x00001000U /*!<Bit 0 */
+#define ADC_SMPR1_SMP14_1 0x00002000U /*!<Bit 1 */
+#define ADC_SMPR1_SMP14_2 0x00004000U /*!<Bit 2 */
+#define ADC_SMPR1_SMP15 0x00038000U /*!<SMP15[2:0] bits (Channel 15 Sample time selection) */
+#define ADC_SMPR1_SMP15_0 0x00008000U /*!<Bit 0 */
+#define ADC_SMPR1_SMP15_1 0x00010000U /*!<Bit 1 */
+#define ADC_SMPR1_SMP15_2 0x00020000U /*!<Bit 2 */
+#define ADC_SMPR1_SMP16 0x001C0000U /*!<SMP16[2:0] bits (Channel 16 Sample time selection) */
+#define ADC_SMPR1_SMP16_0 0x00040000U /*!<Bit 0 */
+#define ADC_SMPR1_SMP16_1 0x00080000U /*!<Bit 1 */
+#define ADC_SMPR1_SMP16_2 0x00100000U /*!<Bit 2 */
+#define ADC_SMPR1_SMP17 0x00E00000U /*!<SMP17[2:0] bits (Channel 17 Sample time selection) */
+#define ADC_SMPR1_SMP17_0 0x00200000U /*!<Bit 0 */
+#define ADC_SMPR1_SMP17_1 0x00400000U /*!<Bit 1 */
+#define ADC_SMPR1_SMP17_2 0x00800000U /*!<Bit 2 */
+#define ADC_SMPR1_SMP18 0x07000000U /*!<SMP18[2:0] bits (Channel 18 Sample time selection) */
+#define ADC_SMPR1_SMP18_0 0x01000000U /*!<Bit 0 */
+#define ADC_SMPR1_SMP18_1 0x02000000U /*!<Bit 1 */
+#define ADC_SMPR1_SMP18_2 0x04000000U /*!<Bit 2 */
+
+/****************** Bit definition for ADC_SMPR2 register *******************/
+#define ADC_SMPR2_SMP0 0x00000007U /*!<SMP0[2:0] bits (Channel 0 Sample time selection) */
+#define ADC_SMPR2_SMP0_0 0x00000001U /*!<Bit 0 */
+#define ADC_SMPR2_SMP0_1 0x00000002U /*!<Bit 1 */
+#define ADC_SMPR2_SMP0_2 0x00000004U /*!<Bit 2 */
+#define ADC_SMPR2_SMP1 0x00000038U /*!<SMP1[2:0] bits (Channel 1 Sample time selection) */
+#define ADC_SMPR2_SMP1_0 0x00000008U /*!<Bit 0 */
+#define ADC_SMPR2_SMP1_1 0x00000010U /*!<Bit 1 */
+#define ADC_SMPR2_SMP1_2 0x00000020U /*!<Bit 2 */
+#define ADC_SMPR2_SMP2 0x000001C0U /*!<SMP2[2:0] bits (Channel 2 Sample time selection) */
+#define ADC_SMPR2_SMP2_0 0x00000040U /*!<Bit 0 */
+#define ADC_SMPR2_SMP2_1 0x00000080U /*!<Bit 1 */
+#define ADC_SMPR2_SMP2_2 0x00000100U /*!<Bit 2 */
+#define ADC_SMPR2_SMP3 0x00000E00U /*!<SMP3[2:0] bits (Channel 3 Sample time selection) */
+#define ADC_SMPR2_SMP3_0 0x00000200U /*!<Bit 0 */
+#define ADC_SMPR2_SMP3_1 0x00000400U /*!<Bit 1 */
+#define ADC_SMPR2_SMP3_2 0x00000800U /*!<Bit 2 */
+#define ADC_SMPR2_SMP4 0x00007000U /*!<SMP4[2:0] bits (Channel 4 Sample time selection) */
+#define ADC_SMPR2_SMP4_0 0x00001000U /*!<Bit 0 */
+#define ADC_SMPR2_SMP4_1 0x00002000U /*!<Bit 1 */
+#define ADC_SMPR2_SMP4_2 0x00004000U /*!<Bit 2 */
+#define ADC_SMPR2_SMP5 0x00038000U /*!<SMP5[2:0] bits (Channel 5 Sample time selection) */
+#define ADC_SMPR2_SMP5_0 0x00008000U /*!<Bit 0 */
+#define ADC_SMPR2_SMP5_1 0x00010000U /*!<Bit 1 */
+#define ADC_SMPR2_SMP5_2 0x00020000U /*!<Bit 2 */
+#define ADC_SMPR2_SMP6 0x001C0000U /*!<SMP6[2:0] bits (Channel 6 Sample time selection) */
+#define ADC_SMPR2_SMP6_0 0x00040000U /*!<Bit 0 */
+#define ADC_SMPR2_SMP6_1 0x00080000U /*!<Bit 1 */
+#define ADC_SMPR2_SMP6_2 0x00100000U /*!<Bit 2 */
+#define ADC_SMPR2_SMP7 0x00E00000U /*!<SMP7[2:0] bits (Channel 7 Sample time selection) */
+#define ADC_SMPR2_SMP7_0 0x00200000U /*!<Bit 0 */
+#define ADC_SMPR2_SMP7_1 0x00400000U /*!<Bit 1 */
+#define ADC_SMPR2_SMP7_2 0x00800000U /*!<Bit 2 */
+#define ADC_SMPR2_SMP8 0x07000000U /*!<SMP8[2:0] bits (Channel 8 Sample time selection) */
+#define ADC_SMPR2_SMP8_0 0x01000000U /*!<Bit 0 */
+#define ADC_SMPR2_SMP8_1 0x02000000U /*!<Bit 1 */
+#define ADC_SMPR2_SMP8_2 0x04000000U /*!<Bit 2 */
+#define ADC_SMPR2_SMP9 0x38000000U /*!<SMP9[2:0] bits (Channel 9 Sample time selection) */
+#define ADC_SMPR2_SMP9_0 0x08000000U /*!<Bit 0 */
+#define ADC_SMPR2_SMP9_1 0x10000000U /*!<Bit 1 */
+#define ADC_SMPR2_SMP9_2 0x20000000U /*!<Bit 2 */
+
+/****************** Bit definition for ADC_JOFR1 register *******************/
+#define ADC_JOFR1_JOFFSET1 0x0FFFU /*!<Data offset for injected channel 1 */
+
+/****************** Bit definition for ADC_JOFR2 register *******************/
+#define ADC_JOFR2_JOFFSET2 0x0FFFU /*!<Data offset for injected channel 2 */
+
+/****************** Bit definition for ADC_JOFR3 register *******************/
+#define ADC_JOFR3_JOFFSET3 0x0FFFU /*!<Data offset for injected channel 3 */
+
+/****************** Bit definition for ADC_JOFR4 register *******************/
+#define ADC_JOFR4_JOFFSET4 0x0FFFU /*!<Data offset for injected channel 4 */
+
+/******************* Bit definition for ADC_HTR register ********************/
+#define ADC_HTR_HT 0x0FFFU /*!<Analog watchdog high threshold */
+
+/******************* Bit definition for ADC_LTR register ********************/
+#define ADC_LTR_LT 0x0FFFU /*!<Analog watchdog low threshold */
+
+/******************* Bit definition for ADC_SQR1 register *******************/
+#define ADC_SQR1_SQ13 0x0000001FU /*!<SQ13[4:0] bits (13th conversion in regular sequence) */
+#define ADC_SQR1_SQ13_0 0x00000001U /*!<Bit 0 */
+#define ADC_SQR1_SQ13_1 0x00000002U /*!<Bit 1 */
+#define ADC_SQR1_SQ13_2 0x00000004U /*!<Bit 2 */
+#define ADC_SQR1_SQ13_3 0x00000008U /*!<Bit 3 */
+#define ADC_SQR1_SQ13_4 0x00000010U /*!<Bit 4 */
+#define ADC_SQR1_SQ14 0x000003E0U /*!<SQ14[4:0] bits (14th conversion in regular sequence) */
+#define ADC_SQR1_SQ14_0 0x00000020U /*!<Bit 0 */
+#define ADC_SQR1_SQ14_1 0x00000040U /*!<Bit 1 */
+#define ADC_SQR1_SQ14_2 0x00000080U /*!<Bit 2 */
+#define ADC_SQR1_SQ14_3 0x00000100U /*!<Bit 3 */
+#define ADC_SQR1_SQ14_4 0x00000200U /*!<Bit 4 */
+#define ADC_SQR1_SQ15 0x00007C00U /*!<SQ15[4:0] bits (15th conversion in regular sequence) */
+#define ADC_SQR1_SQ15_0 0x00000400U /*!<Bit 0 */
+#define ADC_SQR1_SQ15_1 0x00000800U /*!<Bit 1 */
+#define ADC_SQR1_SQ15_2 0x00001000U /*!<Bit 2 */
+#define ADC_SQR1_SQ15_3 0x00002000U /*!<Bit 3 */
+#define ADC_SQR1_SQ15_4 0x00004000U /*!<Bit 4 */
+#define ADC_SQR1_SQ16 0x000F8000U /*!<SQ16[4:0] bits (16th conversion in regular sequence) */
+#define ADC_SQR1_SQ16_0 0x00008000U /*!<Bit 0 */
+#define ADC_SQR1_SQ16_1 0x00010000U /*!<Bit 1 */
+#define ADC_SQR1_SQ16_2 0x00020000U /*!<Bit 2 */
+#define ADC_SQR1_SQ16_3 0x00040000U /*!<Bit 3 */
+#define ADC_SQR1_SQ16_4 0x00080000U /*!<Bit 4 */
+#define ADC_SQR1_L 0x00F00000U /*!<L[3:0] bits (Regular channel sequence length) */
+#define ADC_SQR1_L_0 0x00100000U /*!<Bit 0 */
+#define ADC_SQR1_L_1 0x00200000U /*!<Bit 1 */
+#define ADC_SQR1_L_2 0x00400000U /*!<Bit 2 */
+#define ADC_SQR1_L_3 0x00800000U /*!<Bit 3 */
+
+/******************* Bit definition for ADC_SQR2 register *******************/
+#define ADC_SQR2_SQ7 0x0000001FU /*!<SQ7[4:0] bits (7th conversion in regular sequence) */
+#define ADC_SQR2_SQ7_0 0x00000001U /*!<Bit 0 */
+#define ADC_SQR2_SQ7_1 0x00000002U /*!<Bit 1 */
+#define ADC_SQR2_SQ7_2 0x00000004U /*!<Bit 2 */
+#define ADC_SQR2_SQ7_3 0x00000008U /*!<Bit 3 */
+#define ADC_SQR2_SQ7_4 0x00000010U /*!<Bit 4 */
+#define ADC_SQR2_SQ8 0x000003E0U /*!<SQ8[4:0] bits (8th conversion in regular sequence) */
+#define ADC_SQR2_SQ8_0 0x00000020U /*!<Bit 0 */
+#define ADC_SQR2_SQ8_1 0x00000040U /*!<Bit 1 */
+#define ADC_SQR2_SQ8_2 0x00000080U /*!<Bit 2 */
+#define ADC_SQR2_SQ8_3 0x00000100U /*!<Bit 3 */
+#define ADC_SQR2_SQ8_4 0x00000200U /*!<Bit 4 */
+#define ADC_SQR2_SQ9 0x00007C00U /*!<SQ9[4:0] bits (9th conversion in regular sequence) */
+#define ADC_SQR2_SQ9_0 0x00000400U /*!<Bit 0 */
+#define ADC_SQR2_SQ9_1 0x00000800U /*!<Bit 1 */
+#define ADC_SQR2_SQ9_2 0x00001000U /*!<Bit 2 */
+#define ADC_SQR2_SQ9_3 0x00002000U /*!<Bit 3 */
+#define ADC_SQR2_SQ9_4 0x00004000U /*!<Bit 4 */
+#define ADC_SQR2_SQ10 0x000F8000U /*!<SQ10[4:0] bits (10th conversion in regular sequence) */
+#define ADC_SQR2_SQ10_0 0x00008000U /*!<Bit 0 */
+#define ADC_SQR2_SQ10_1 0x00010000U /*!<Bit 1 */
+#define ADC_SQR2_SQ10_2 0x00020000U /*!<Bit 2 */
+#define ADC_SQR2_SQ10_3 0x00040000U /*!<Bit 3 */
+#define ADC_SQR2_SQ10_4 0x00080000U /*!<Bit 4 */
+#define ADC_SQR2_SQ11 0x01F00000U /*!<SQ11[4:0] bits (11th conversion in regular sequence) */
+#define ADC_SQR2_SQ11_0 0x00100000U /*!<Bit 0 */
+#define ADC_SQR2_SQ11_1 0x00200000U /*!<Bit 1 */
+#define ADC_SQR2_SQ11_2 0x00400000U /*!<Bit 2 */
+#define ADC_SQR2_SQ11_3 0x00800000U /*!<Bit 3 */
+#define ADC_SQR2_SQ11_4 0x01000000U /*!<Bit 4 */
+#define ADC_SQR2_SQ12 0x3E000000U /*!<SQ12[4:0] bits (12th conversion in regular sequence) */
+#define ADC_SQR2_SQ12_0 0x02000000U /*!<Bit 0 */
+#define ADC_SQR2_SQ12_1 0x04000000U /*!<Bit 1 */
+#define ADC_SQR2_SQ12_2 0x08000000U /*!<Bit 2 */
+#define ADC_SQR2_SQ12_3 0x10000000U /*!<Bit 3 */
+#define ADC_SQR2_SQ12_4 0x20000000U /*!<Bit 4 */
+
+/******************* Bit definition for ADC_SQR3 register *******************/
+#define ADC_SQR3_SQ1 0x0000001FU /*!<SQ1[4:0] bits (1st conversion in regular sequence) */
+#define ADC_SQR3_SQ1_0 0x00000001U /*!<Bit 0 */
+#define ADC_SQR3_SQ1_1 0x00000002U /*!<Bit 1 */
+#define ADC_SQR3_SQ1_2 0x00000004U /*!<Bit 2 */
+#define ADC_SQR3_SQ1_3 0x00000008U /*!<Bit 3 */
+#define ADC_SQR3_SQ1_4 0x00000010U /*!<Bit 4 */
+#define ADC_SQR3_SQ2 0x000003E0U /*!<SQ2[4:0] bits (2nd conversion in regular sequence) */
+#define ADC_SQR3_SQ2_0 0x00000020U /*!<Bit 0 */
+#define ADC_SQR3_SQ2_1 0x00000040U /*!<Bit 1 */
+#define ADC_SQR3_SQ2_2 0x00000080U /*!<Bit 2 */
+#define ADC_SQR3_SQ2_3 0x00000100U /*!<Bit 3 */
+#define ADC_SQR3_SQ2_4 0x00000200U /*!<Bit 4 */
+#define ADC_SQR3_SQ3 0x00007C00U /*!<SQ3[4:0] bits (3rd conversion in regular sequence) */
+#define ADC_SQR3_SQ3_0 0x00000400U /*!<Bit 0 */
+#define ADC_SQR3_SQ3_1 0x00000800U /*!<Bit 1 */
+#define ADC_SQR3_SQ3_2 0x00001000U /*!<Bit 2 */
+#define ADC_SQR3_SQ3_3 0x00002000U /*!<Bit 3 */
+#define ADC_SQR3_SQ3_4 0x00004000U /*!<Bit 4 */
+#define ADC_SQR3_SQ4 0x000F8000U /*!<SQ4[4:0] bits (4th conversion in regular sequence) */
+#define ADC_SQR3_SQ4_0 0x00008000U /*!<Bit 0 */
+#define ADC_SQR3_SQ4_1 0x00010000U /*!<Bit 1 */
+#define ADC_SQR3_SQ4_2 0x00020000U /*!<Bit 2 */
+#define ADC_SQR3_SQ4_3 0x00040000U /*!<Bit 3 */
+#define ADC_SQR3_SQ4_4 0x00080000U /*!<Bit 4 */
+#define ADC_SQR3_SQ5 0x01F00000U /*!<SQ5[4:0] bits (5th conversion in regular sequence) */
+#define ADC_SQR3_SQ5_0 0x00100000U /*!<Bit 0 */
+#define ADC_SQR3_SQ5_1 0x00200000U /*!<Bit 1 */
+#define ADC_SQR3_SQ5_2 0x00400000U /*!<Bit 2 */
+#define ADC_SQR3_SQ5_3 0x00800000U /*!<Bit 3 */
+#define ADC_SQR3_SQ5_4 0x01000000U /*!<Bit 4 */
+#define ADC_SQR3_SQ6 0x3E000000U /*!<SQ6[4:0] bits (6th conversion in regular sequence) */
+#define ADC_SQR3_SQ6_0 0x02000000U /*!<Bit 0 */
+#define ADC_SQR3_SQ6_1 0x04000000U /*!<Bit 1 */
+#define ADC_SQR3_SQ6_2 0x08000000U /*!<Bit 2 */
+#define ADC_SQR3_SQ6_3 0x10000000U /*!<Bit 3 */
+#define ADC_SQR3_SQ6_4 0x20000000U /*!<Bit 4 */
+
+/******************* Bit definition for ADC_JSQR register *******************/
+#define ADC_JSQR_JSQ1 0x0000001FU /*!<JSQ1[4:0] bits (1st conversion in injected sequence) */
+#define ADC_JSQR_JSQ1_0 0x00000001U /*!<Bit 0 */
+#define ADC_JSQR_JSQ1_1 0x00000002U /*!<Bit 1 */
+#define ADC_JSQR_JSQ1_2 0x00000004U /*!<Bit 2 */
+#define ADC_JSQR_JSQ1_3 0x00000008U /*!<Bit 3 */
+#define ADC_JSQR_JSQ1_4 0x00000010U /*!<Bit 4 */
+#define ADC_JSQR_JSQ2 0x000003E0U /*!<JSQ2[4:0] bits (2nd conversion in injected sequence) */
+#define ADC_JSQR_JSQ2_0 0x00000020U /*!<Bit 0 */
+#define ADC_JSQR_JSQ2_1 0x00000040U /*!<Bit 1 */
+#define ADC_JSQR_JSQ2_2 0x00000080U /*!<Bit 2 */
+#define ADC_JSQR_JSQ2_3 0x00000100U /*!<Bit 3 */
+#define ADC_JSQR_JSQ2_4 0x00000200U /*!<Bit 4 */
+#define ADC_JSQR_JSQ3 0x00007C00U /*!<JSQ3[4:0] bits (3rd conversion in injected sequence) */
+#define ADC_JSQR_JSQ3_0 0x00000400U /*!<Bit 0 */
+#define ADC_JSQR_JSQ3_1 0x00000800U /*!<Bit 1 */
+#define ADC_JSQR_JSQ3_2 0x00001000U /*!<Bit 2 */
+#define ADC_JSQR_JSQ3_3 0x00002000U /*!<Bit 3 */
+#define ADC_JSQR_JSQ3_4 0x00004000U /*!<Bit 4 */
+#define ADC_JSQR_JSQ4 0x000F8000U /*!<JSQ4[4:0] bits (4th conversion in injected sequence) */
+#define ADC_JSQR_JSQ4_0 0x00008000U /*!<Bit 0 */
+#define ADC_JSQR_JSQ4_1 0x00010000U /*!<Bit 1 */
+#define ADC_JSQR_JSQ4_2 0x00020000U /*!<Bit 2 */
+#define ADC_JSQR_JSQ4_3 0x00040000U /*!<Bit 3 */
+#define ADC_JSQR_JSQ4_4 0x00080000U /*!<Bit 4 */
+#define ADC_JSQR_JL 0x00300000U /*!<JL[1:0] bits (Injected Sequence length) */
+#define ADC_JSQR_JL_0 0x00100000U /*!<Bit 0 */
+#define ADC_JSQR_JL_1 0x00200000U /*!<Bit 1 */
+
+/******************* Bit definition for ADC_JDR1 register *******************/
+#define ADC_JDR1_JDATA 0xFFFFU /*!<Injected data */
+
+/******************* Bit definition for ADC_JDR2 register *******************/
+#define ADC_JDR2_JDATA 0xFFFFU /*!<Injected data */
+
+/******************* Bit definition for ADC_JDR3 register *******************/
+#define ADC_JDR3_JDATA 0xFFFFU /*!<Injected data */
+
+/******************* Bit definition for ADC_JDR4 register *******************/
+#define ADC_JDR4_JDATA 0xFFFFU /*!<Injected data */
+
+/******************** Bit definition for ADC_DR register ********************/
+#define ADC_DR_DATA 0x0000FFFFU /*!<Regular data */
+#define ADC_DR_ADC2DATA 0xFFFF0000U /*!<ADC2 data */
+
+/******************* Bit definition for ADC_CSR register ********************/
+#define ADC_CSR_AWD1 0x00000001U /*!<ADC1 Analog watchdog flag */
+#define ADC_CSR_EOC1 0x00000002U /*!<ADC1 End of conversion */
+#define ADC_CSR_JEOC1 0x00000004U /*!<ADC1 Injected channel end of conversion */
+#define ADC_CSR_JSTRT1 0x00000008U /*!<ADC1 Injected channel Start flag */
+#define ADC_CSR_STRT1 0x00000010U /*!<ADC1 Regular channel Start flag */
+#define ADC_CSR_DOVR1 0x00000020U /*!<ADC1 DMA overrun flag */
+#define ADC_CSR_AWD2 0x00000100U /*!<ADC2 Analog watchdog flag */
+#define ADC_CSR_EOC2 0x00000200U /*!<ADC2 End of conversion */
+#define ADC_CSR_JEOC2 0x00000400U /*!<ADC2 Injected channel end of conversion */
+#define ADC_CSR_JSTRT2 0x00000800U /*!<ADC2 Injected channel Start flag */
+#define ADC_CSR_STRT2 0x00001000U /*!<ADC2 Regular channel Start flag */
+#define ADC_CSR_DOVR2 0x00002000U /*!<ADC2 DMA overrun flag */
+
+/******************* Bit definition for ADC_CCR register ********************/
+#define ADC_CCR_MULTI 0x0000001FU /*!<MULTI[4:0] bits (Multi-ADC mode selection) */
+#define ADC_CCR_MULTI_0 0x00000001U /*!<Bit 0 */
+#define ADC_CCR_MULTI_1 0x00000002U /*!<Bit 1 */
+#define ADC_CCR_MULTI_2 0x00000004U /*!<Bit 2 */
+#define ADC_CCR_MULTI_3 0x00000008U /*!<Bit 3 */
+#define ADC_CCR_MULTI_4 0x00000010U /*!<Bit 4 */
+#define ADC_CCR_DELAY 0x00000F00U /*!<DELAY[3:0] bits (Delay between 2 sampling phases) */
+#define ADC_CCR_DELAY_0 0x00000100U /*!<Bit 0 */
+#define ADC_CCR_DELAY_1 0x00000200U /*!<Bit 1 */
+#define ADC_CCR_DELAY_2 0x00000400U /*!<Bit 2 */
+#define ADC_CCR_DELAY_3 0x00000800U /*!<Bit 3 */
+#define ADC_CCR_DDS 0x00002000U /*!<DMA disable selection (Multi-ADC mode) */
+#define ADC_CCR_DMA 0x0000C000U /*!<DMA[1:0] bits (Direct Memory Access mode for multimode) */
+#define ADC_CCR_DMA_0 0x00004000U /*!<Bit 0 */
+#define ADC_CCR_DMA_1 0x00008000U /*!<Bit 1 */
+#define ADC_CCR_ADCPRE 0x00030000U /*!<ADCPRE[1:0] bits (ADC prescaler) */
+#define ADC_CCR_ADCPRE_0 0x00010000U /*!<Bit 0 */
+#define ADC_CCR_ADCPRE_1 0x00020000U /*!<Bit 1 */
+#define ADC_CCR_VBATE 0x00400000U /*!<VBAT Enable */
+#define ADC_CCR_TSVREFE 0x00800000U /*!<Temperature Sensor and VREFINT Enable */
+
+/******************* Bit definition for ADC_CDR register ********************/
+#define ADC_CDR_DATA1 0x0000FFFFU /*!<1st data of a pair of regular conversions */
+#define ADC_CDR_DATA2 0xFFFF0000U /*!<2nd data of a pair of regular conversions */
+
+/******************************************************************************/
+/* */
+/* Controller Area Network */
+/* */
+/******************************************************************************/
+/*!<CAN control and status registers */
+/******************* Bit definition for CAN_MCR register ********************/
+#define CAN_MCR_INRQ 0x00000001U /*!<Initialization Request */
+#define CAN_MCR_SLEEP 0x00000002U /*!<Sleep Mode Request */
+#define CAN_MCR_TXFP 0x00000004U /*!<Transmit FIFO Priority */
+#define CAN_MCR_RFLM 0x00000008U /*!<Receive FIFO Locked Mode */
+#define CAN_MCR_NART 0x00000010U /*!<No Automatic Retransmission */
+#define CAN_MCR_AWUM 0x00000020U /*!<Automatic Wakeup Mode */
+#define CAN_MCR_ABOM 0x00000040U /*!<Automatic Bus-Off Management */
+#define CAN_MCR_TTCM 0x00000080U /*!<Time Triggered Communication Mode */
+#define CAN_MCR_RESET 0x00008000U /*!<bxCAN software master reset */
+#define CAN_MCR_DBF 0x00010000U /*!<bxCAN Debug freeze */
+/******************* Bit definition for CAN_MSR register ********************/
+#define CAN_MSR_INAK 0x0001U /*!<Initialization Acknowledge */
+#define CAN_MSR_SLAK 0x0002U /*!<Sleep Acknowledge */
+#define CAN_MSR_ERRI 0x0004U /*!<Error Interrupt */
+#define CAN_MSR_WKUI 0x0008U /*!<Wakeup Interrupt */
+#define CAN_MSR_SLAKI 0x0010U /*!<Sleep Acknowledge Interrupt */
+#define CAN_MSR_TXM 0x0100U /*!<Transmit Mode */
+#define CAN_MSR_RXM 0x0200U /*!<Receive Mode */
+#define CAN_MSR_SAMP 0x0400U /*!<Last Sample Point */
+#define CAN_MSR_RX 0x0800U /*!<CAN Rx Signal */
+
+/******************* Bit definition for CAN_TSR register ********************/
+#define CAN_TSR_RQCP0 0x00000001U /*!<Request Completed Mailbox0 */
+#define CAN_TSR_TXOK0 0x00000002U /*!<Transmission OK of Mailbox0 */
+#define CAN_TSR_ALST0 0x00000004U /*!<Arbitration Lost for Mailbox0 */
+#define CAN_TSR_TERR0 0x00000008U /*!<Transmission Error of Mailbox0 */
+#define CAN_TSR_ABRQ0 0x00000080U /*!<Abort Request for Mailbox0 */
+#define CAN_TSR_RQCP1 0x00000100U /*!<Request Completed Mailbox1 */
+#define CAN_TSR_TXOK1 0x00000200U /*!<Transmission OK of Mailbox1 */
+#define CAN_TSR_ALST1 0x00000400U /*!<Arbitration Lost for Mailbox1 */
+#define CAN_TSR_TERR1 0x00000800U /*!<Transmission Error of Mailbox1 */
+#define CAN_TSR_ABRQ1 0x00008000U /*!<Abort Request for Mailbox 1 */
+#define CAN_TSR_RQCP2 0x00010000U /*!<Request Completed Mailbox2 */
+#define CAN_TSR_TXOK2 0x00020000U /*!<Transmission OK of Mailbox 2 */
+#define CAN_TSR_ALST2 0x00040000U /*!<Arbitration Lost for mailbox 2 */
+#define CAN_TSR_TERR2 0x00080000U /*!<Transmission Error of Mailbox 2 */
+#define CAN_TSR_ABRQ2 0x00800000U /*!<Abort Request for Mailbox 2 */
+#define CAN_TSR_CODE 0x03000000U /*!<Mailbox Code */
+
+#define CAN_TSR_TME 0x1C000000U /*!<TME[2:0] bits */
+#define CAN_TSR_TME0 0x04000000U /*!<Transmit Mailbox 0 Empty */
+#define CAN_TSR_TME1 0x08000000U /*!<Transmit Mailbox 1 Empty */
+#define CAN_TSR_TME2 0x10000000U /*!<Transmit Mailbox 2 Empty */
+
+#define CAN_TSR_LOW 0xE0000000U /*!<LOW[2:0] bits */
+#define CAN_TSR_LOW0 0x20000000U /*!<Lowest Priority Flag for Mailbox 0 */
+#define CAN_TSR_LOW1 0x40000000U /*!<Lowest Priority Flag for Mailbox 1 */
+#define CAN_TSR_LOW2 0x80000000U /*!<Lowest Priority Flag for Mailbox 2 */
+
+/******************* Bit definition for CAN_RF0R register *******************/
+#define CAN_RF0R_FMP0 0x03U /*!<FIFO 0 Message Pending */
+#define CAN_RF0R_FULL0 0x08U /*!<FIFO 0 Full */
+#define CAN_RF0R_FOVR0 0x10U /*!<FIFO 0 Overrun */
+#define CAN_RF0R_RFOM0 0x20U /*!<Release FIFO 0 Output Mailbox */
+
+/******************* Bit definition for CAN_RF1R register *******************/
+#define CAN_RF1R_FMP1 0x03U /*!<FIFO 1 Message Pending */
+#define CAN_RF1R_FULL1 0x08U /*!<FIFO 1 Full */
+#define CAN_RF1R_FOVR1 0x10U /*!<FIFO 1 Overrun */
+#define CAN_RF1R_RFOM1 0x20U /*!<Release FIFO 1 Output Mailbox */
+
+/******************** Bit definition for CAN_IER register *******************/
+#define CAN_IER_TMEIE 0x00000001U /*!<Transmit Mailbox Empty Interrupt Enable */
+#define CAN_IER_FMPIE0 0x00000002U /*!<FIFO Message Pending Interrupt Enable */
+#define CAN_IER_FFIE0 0x00000004U /*!<FIFO Full Interrupt Enable */
+#define CAN_IER_FOVIE0 0x00000008U /*!<FIFO Overrun Interrupt Enable */
+#define CAN_IER_FMPIE1 0x00000010U /*!<FIFO Message Pending Interrupt Enable */
+#define CAN_IER_FFIE1 0x00000020U /*!<FIFO Full Interrupt Enable */
+#define CAN_IER_FOVIE1 0x00000040U /*!<FIFO Overrun Interrupt Enable */
+#define CAN_IER_EWGIE 0x00000100U /*!<Error Warning Interrupt Enable */
+#define CAN_IER_EPVIE 0x00000200U /*!<Error Passive Interrupt Enable */
+#define CAN_IER_BOFIE 0x00000400U /*!<Bus-Off Interrupt Enable */
+#define CAN_IER_LECIE 0x00000800U /*!<Last Error Code Interrupt Enable */
+#define CAN_IER_ERRIE 0x00008000U /*!<Error Interrupt Enable */
+#define CAN_IER_WKUIE 0x00010000U /*!<Wakeup Interrupt Enable */
+#define CAN_IER_SLKIE 0x00020000U /*!<Sleep Interrupt Enable */
+#define CAN_IER_EWGIE 0x00000100U /*!<Error warning interrupt enable */
+#define CAN_IER_EPVIE 0x00000200U /*!<Error passive interrupt enable */
+#define CAN_IER_BOFIE 0x00000400U /*!<Bus-off interrupt enable */
+#define CAN_IER_LECIE 0x00000800U /*!<Last error code interrupt enable */
+#define CAN_IER_ERRIE 0x00008000U /*!<Error interrupt enable */
+
+
+/******************** Bit definition for CAN_ESR register *******************/
+#define CAN_ESR_EWGF 0x00000001U /*!<Error Warning Flag */
+#define CAN_ESR_EPVF 0x00000002U /*!<Error Passive Flag */
+#define CAN_ESR_BOFF 0x00000004U /*!<Bus-Off Flag */
+
+#define CAN_ESR_LEC 0x00000070U /*!<LEC[2:0] bits (Last Error Code) */
+#define CAN_ESR_LEC_0 0x00000010U /*!<Bit 0 */
+#define CAN_ESR_LEC_1 0x00000020U /*!<Bit 1 */
+#define CAN_ESR_LEC_2 0x00000040U /*!<Bit 2 */
+
+#define CAN_ESR_TEC 0x00FF0000U /*!<Least significant byte of the 9-bit Transmit Error Counter */
+#define CAN_ESR_REC 0xFF000000U /*!<Receive Error Counter */
+
+/******************* Bit definition for CAN_BTR register ********************/
+#define CAN_BTR_BRP 0x000003FFU /*!<Baud Rate Prescaler */
+#define CAN_BTR_TS1 0x000F0000U /*!<Time Segment 1 */
+#define CAN_BTR_TS1_0 0x00010000U /*!<Bit 0 */
+#define CAN_BTR_TS1_1 0x00020000U /*!<Bit 1 */
+#define CAN_BTR_TS1_2 0x00040000U /*!<Bit 2 */
+#define CAN_BTR_TS1_3 0x00080000U /*!<Bit 3 */
+#define CAN_BTR_TS2 0x00700000U /*!<Time Segment 2 */
+#define CAN_BTR_TS2_0 0x00100000U /*!<Bit 0 */
+#define CAN_BTR_TS2_1 0x00200000U /*!<Bit 1 */
+#define CAN_BTR_TS2_2 0x00400000U /*!<Bit 2 */
+#define CAN_BTR_SJW 0x03000000U /*!<Resynchronization Jump Width */
+#define CAN_BTR_SJW_0 0x01000000U /*!<Bit 0 */
+#define CAN_BTR_SJW_1 0x02000000U /*!<Bit 1 */
+#define CAN_BTR_LBKM 0x40000000U /*!<Loop Back Mode (Debug) */
+#define CAN_BTR_SILM 0x80000000U /*!<Silent Mode */
+
+
+/*!<Mailbox registers */
+/****************** Bit definition for CAN_TI0R register ********************/
+#define CAN_TI0R_TXRQ 0x00000001U /*!<Transmit Mailbox Request */
+#define CAN_TI0R_RTR 0x00000002U /*!<Remote Transmission Request */
+#define CAN_TI0R_IDE 0x00000004U /*!<Identifier Extension */
+#define CAN_TI0R_EXID 0x001FFFF8U /*!<Extended Identifier */
+#define CAN_TI0R_STID 0xFFE00000U /*!<Standard Identifier or Extended Identifier */
+
+/****************** Bit definition for CAN_TDT0R register *******************/
+#define CAN_TDT0R_DLC 0x0000000FU /*!<Data Length Code */
+#define CAN_TDT0R_TGT 0x00000100U /*!<Transmit Global Time */
+#define CAN_TDT0R_TIME 0xFFFF0000U /*!<Message Time Stamp */
+
+/****************** Bit definition for CAN_TDL0R register *******************/
+#define CAN_TDL0R_DATA0 0x000000FFU /*!<Data byte 0 */
+#define CAN_TDL0R_DATA1 0x0000FF00U /*!<Data byte 1 */
+#define CAN_TDL0R_DATA2 0x00FF0000U /*!<Data byte 2 */
+#define CAN_TDL0R_DATA3 0xFF000000U /*!<Data byte 3 */
+
+/****************** Bit definition for CAN_TDH0R register *******************/
+#define CAN_TDH0R_DATA4 0x000000FFU /*!<Data byte 4 */
+#define CAN_TDH0R_DATA5 0x0000FF00U /*!<Data byte 5 */
+#define CAN_TDH0R_DATA6 0x00FF0000U /*!<Data byte 6 */
+#define CAN_TDH0R_DATA7 0xFF000000U /*!<Data byte 7 */
+
+/******************* Bit definition for CAN_TI1R register *******************/
+#define CAN_TI1R_TXRQ 0x00000001U /*!<Transmit Mailbox Request */
+#define CAN_TI1R_RTR 0x00000002U /*!<Remote Transmission Request */
+#define CAN_TI1R_IDE 0x00000004U /*!<Identifier Extension */
+#define CAN_TI1R_EXID 0x001FFFF8U /*!<Extended Identifier */
+#define CAN_TI1R_STID 0xFFE00000U /*!<Standard Identifier or Extended Identifier */
+
+/******************* Bit definition for CAN_TDT1R register ******************/
+#define CAN_TDT1R_DLC 0x0000000FU /*!<Data Length Code */
+#define CAN_TDT1R_TGT 0x00000100U /*!<Transmit Global Time */
+#define CAN_TDT1R_TIME 0xFFFF0000U /*!<Message Time Stamp */
+
+/******************* Bit definition for CAN_TDL1R register ******************/
+#define CAN_TDL1R_DATA0 0x000000FFU /*!<Data byte 0 */
+#define CAN_TDL1R_DATA1 0x0000FF00U /*!<Data byte 1 */
+#define CAN_TDL1R_DATA2 0x00FF0000U /*!<Data byte 2 */
+#define CAN_TDL1R_DATA3 0xFF000000U /*!<Data byte 3 */
+
+/******************* Bit definition for CAN_TDH1R register ******************/
+#define CAN_TDH1R_DATA4 0x000000FFU /*!<Data byte 4 */
+#define CAN_TDH1R_DATA5 0x0000FF00U /*!<Data byte 5 */
+#define CAN_TDH1R_DATA6 0x00FF0000U /*!<Data byte 6 */
+#define CAN_TDH1R_DATA7 0xFF000000U /*!<Data byte 7 */
+
+/******************* Bit definition for CAN_TI2R register *******************/
+#define CAN_TI2R_TXRQ 0x00000001U /*!<Transmit Mailbox Request */
+#define CAN_TI2R_RTR 0x00000002U /*!<Remote Transmission Request */
+#define CAN_TI2R_IDE 0x00000004U /*!<Identifier Extension */
+#define CAN_TI2R_EXID 0x001FFFF8U /*!<Extended identifier */
+#define CAN_TI2R_STID 0xFFE00000U /*!<Standard Identifier or Extended Identifier */
+
+/******************* Bit definition for CAN_TDT2R register ******************/
+#define CAN_TDT2R_DLC 0x0000000FU /*!<Data Length Code */
+#define CAN_TDT2R_TGT 0x00000100U /*!<Transmit Global Time */
+#define CAN_TDT2R_TIME 0xFFFF0000U /*!<Message Time Stamp */
+
+/******************* Bit definition for CAN_TDL2R register ******************/
+#define CAN_TDL2R_DATA0 0x000000FFU /*!<Data byte 0 */
+#define CAN_TDL2R_DATA1 0x0000FF00U /*!<Data byte 1 */
+#define CAN_TDL2R_DATA2 0x00FF0000U /*!<Data byte 2 */
+#define CAN_TDL2R_DATA3 0xFF000000U /*!<Data byte 3 */
+
+/******************* Bit definition for CAN_TDH2R register ******************/
+#define CAN_TDH2R_DATA4 0x000000FFU /*!<Data byte 4 */
+#define CAN_TDH2R_DATA5 0x0000FF00U /*!<Data byte 5 */
+#define CAN_TDH2R_DATA6 0x00FF0000U /*!<Data byte 6 */
+#define CAN_TDH2R_DATA7 0xFF000000U /*!<Data byte 7 */
+
+/******************* Bit definition for CAN_RI0R register *******************/
+#define CAN_RI0R_RTR 0x00000002U /*!<Remote Transmission Request */
+#define CAN_RI0R_IDE 0x00000004U /*!<Identifier Extension */
+#define CAN_RI0R_EXID 0x001FFFF8U /*!<Extended Identifier */
+#define CAN_RI0R_STID 0xFFE00000U /*!<Standard Identifier or Extended Identifier */
+
+/******************* Bit definition for CAN_RDT0R register ******************/
+#define CAN_RDT0R_DLC 0x0000000FU /*!<Data Length Code */
+#define CAN_RDT0R_FMI 0x0000FF00U /*!<Filter Match Index */
+#define CAN_RDT0R_TIME 0xFFFF0000U /*!<Message Time Stamp */
+
+/******************* Bit definition for CAN_RDL0R register ******************/
+#define CAN_RDL0R_DATA0 0x000000FFU /*!<Data byte 0 */
+#define CAN_RDL0R_DATA1 0x0000FF00U /*!<Data byte 1 */
+#define CAN_RDL0R_DATA2 0x00FF0000U /*!<Data byte 2 */
+#define CAN_RDL0R_DATA3 0xFF000000U /*!<Data byte 3 */
+
+/******************* Bit definition for CAN_RDH0R register ******************/
+#define CAN_RDH0R_DATA4 0x000000FFU /*!<Data byte 4 */
+#define CAN_RDH0R_DATA5 0x0000FF00U /*!<Data byte 5 */
+#define CAN_RDH0R_DATA6 0x00FF0000U /*!<Data byte 6 */
+#define CAN_RDH0R_DATA7 0xFF000000U /*!<Data byte 7 */
+
+/******************* Bit definition for CAN_RI1R register *******************/
+#define CAN_RI1R_RTR 0x00000002U /*!<Remote Transmission Request */
+#define CAN_RI1R_IDE 0x00000004U /*!<Identifier Extension */
+#define CAN_RI1R_EXID 0x001FFFF8U /*!<Extended identifier */
+#define CAN_RI1R_STID 0xFFE00000U /*!<Standard Identifier or Extended Identifier */
+
+/******************* Bit definition for CAN_RDT1R register ******************/
+#define CAN_RDT1R_DLC 0x0000000FU /*!<Data Length Code */
+#define CAN_RDT1R_FMI 0x0000FF00U /*!<Filter Match Index */
+#define CAN_RDT1R_TIME 0xFFFF0000U /*!<Message Time Stamp */
+
+/******************* Bit definition for CAN_RDL1R register ******************/
+#define CAN_RDL1R_DATA0 0x000000FFU /*!<Data byte 0 */
+#define CAN_RDL1R_DATA1 0x0000FF00U /*!<Data byte 1 */
+#define CAN_RDL1R_DATA2 0x00FF0000U /*!<Data byte 2 */
+#define CAN_RDL1R_DATA3 0xFF000000U /*!<Data byte 3 */
+
+/******************* Bit definition for CAN_RDH1R register ******************/
+#define CAN_RDH1R_DATA4 0x000000FFU /*!<Data byte 4 */
+#define CAN_RDH1R_DATA5 0x0000FF00U /*!<Data byte 5 */
+#define CAN_RDH1R_DATA6 0x00FF0000U /*!<Data byte 6 */
+#define CAN_RDH1R_DATA7 0xFF000000U /*!<Data byte 7 */
+
+/*!<CAN filter registers */
+/******************* Bit definition for CAN_FMR register ********************/
+#define CAN_FMR_FINIT 0x01U /*!<Filter Init Mode */
+#define CAN_FMR_CAN2SB 0x00003F00U /*!<CAN2 start bank */
+
+/******************* Bit definition for CAN_FM1R register *******************/
+#define CAN_FM1R_FBM 0x0FFFFFFFU /*!<Filter Mode */
+#define CAN_FM1R_FBM0 0x00000001U /*!<Filter Init Mode bit 0 */
+#define CAN_FM1R_FBM1 0x00000002U /*!<Filter Init Mode bit 1 */
+#define CAN_FM1R_FBM2 0x00000004U /*!<Filter Init Mode bit 2 */
+#define CAN_FM1R_FBM3 0x00000008U /*!<Filter Init Mode bit 3 */
+#define CAN_FM1R_FBM4 0x00000010U /*!<Filter Init Mode bit 4 */
+#define CAN_FM1R_FBM5 0x00000020U /*!<Filter Init Mode bit 5 */
+#define CAN_FM1R_FBM6 0x00000040U /*!<Filter Init Mode bit 6 */
+#define CAN_FM1R_FBM7 0x00000080U /*!<Filter Init Mode bit 7 */
+#define CAN_FM1R_FBM8 0x00000100U /*!<Filter Init Mode bit 8 */
+#define CAN_FM1R_FBM9 0x00000200U /*!<Filter Init Mode bit 9 */
+#define CAN_FM1R_FBM10 0x00000400U /*!<Filter Init Mode bit 10 */
+#define CAN_FM1R_FBM11 0x00000800U /*!<Filter Init Mode bit 11 */
+#define CAN_FM1R_FBM12 0x00001000U /*!<Filter Init Mode bit 12 */
+#define CAN_FM1R_FBM13 0x00002000U /*!<Filter Init Mode bit 13 */
+#define CAN_FM1R_FBM14 0x00004000U /*!<Filter Init Mode bit 14 */
+#define CAN_FM1R_FBM15 0x00008000U /*!<Filter Init Mode bit 15 */
+#define CAN_FM1R_FBM16 0x00010000U /*!<Filter Init Mode bit 16 */
+#define CAN_FM1R_FBM17 0x00020000U /*!<Filter Init Mode bit 17 */
+#define CAN_FM1R_FBM18 0x00040000U /*!<Filter Init Mode bit 18 */
+#define CAN_FM1R_FBM19 0x00080000U /*!<Filter Init Mode bit 19 */
+#define CAN_FM1R_FBM20 0x00100000U /*!<Filter Init Mode bit 20 */
+#define CAN_FM1R_FBM21 0x00200000U /*!<Filter Init Mode bit 21 */
+#define CAN_FM1R_FBM22 0x00400000U /*!<Filter Init Mode bit 22 */
+#define CAN_FM1R_FBM23 0x00800000U /*!<Filter Init Mode bit 23 */
+#define CAN_FM1R_FBM24 0x01000000U /*!<Filter Init Mode bit 24 */
+#define CAN_FM1R_FBM25 0x02000000U /*!<Filter Init Mode bit 25 */
+#define CAN_FM1R_FBM26 0x04000000U /*!<Filter Init Mode bit 26 */
+#define CAN_FM1R_FBM27 0x08000000U /*!<Filter Init Mode bit 27 */
+
+/******************* Bit definition for CAN_FS1R register *******************/
+#define CAN_FS1R_FSC 0x0FFFFFFFU /*!<Filter Scale Configuration */
+#define CAN_FS1R_FSC0 0x00000001U /*!<Filter Scale Configuration bit 0 */
+#define CAN_FS1R_FSC1 0x00000002U /*!<Filter Scale Configuration bit 1 */
+#define CAN_FS1R_FSC2 0x00000004U /*!<Filter Scale Configuration bit 2 */
+#define CAN_FS1R_FSC3 0x00000008U /*!<Filter Scale Configuration bit 3 */
+#define CAN_FS1R_FSC4 0x00000010U /*!<Filter Scale Configuration bit 4 */
+#define CAN_FS1R_FSC5 0x00000020U /*!<Filter Scale Configuration bit 5 */
+#define CAN_FS1R_FSC6 0x00000040U /*!<Filter Scale Configuration bit 6 */
+#define CAN_FS1R_FSC7 0x00000080U /*!<Filter Scale Configuration bit 7 */
+#define CAN_FS1R_FSC8 0x00000100U /*!<Filter Scale Configuration bit 8 */
+#define CAN_FS1R_FSC9 0x00000200U /*!<Filter Scale Configuration bit 9 */
+#define CAN_FS1R_FSC10 0x00000400U /*!<Filter Scale Configuration bit 10 */
+#define CAN_FS1R_FSC11 0x00000800U /*!<Filter Scale Configuration bit 11 */
+#define CAN_FS1R_FSC12 0x00001000U /*!<Filter Scale Configuration bit 12 */
+#define CAN_FS1R_FSC13 0x00002000U /*!<Filter Scale Configuration bit 13 */
+#define CAN_FS1R_FSC14 0x00004000U /*!<Filter Scale Configuration bit 14 */
+#define CAN_FS1R_FSC15 0x00008000U /*!<Filter Scale Configuration bit 15 */
+#define CAN_FS1R_FSC16 0x00010000U /*!<Filter Scale Configuration bit 16 */
+#define CAN_FS1R_FSC17 0x00020000U /*!<Filter Scale Configuration bit 17 */
+#define CAN_FS1R_FSC18 0x00040000U /*!<Filter Scale Configuration bit 18 */
+#define CAN_FS1R_FSC19 0x00080000U /*!<Filter Scale Configuration bit 19 */
+#define CAN_FS1R_FSC20 0x00100000U /*!<Filter Scale Configuration bit 20 */
+#define CAN_FS1R_FSC21 0x00200000U /*!<Filter Scale Configuration bit 21 */
+#define CAN_FS1R_FSC22 0x00400000U /*!<Filter Scale Configuration bit 22 */
+#define CAN_FS1R_FSC23 0x00800000U /*!<Filter Scale Configuration bit 23 */
+#define CAN_FS1R_FSC24 0x01000000U /*!<Filter Scale Configuration bit 24 */
+#define CAN_FS1R_FSC25 0x02000000U /*!<Filter Scale Configuration bit 25 */
+#define CAN_FS1R_FSC26 0x04000000U /*!<Filter Scale Configuration bit 26 */
+#define CAN_FS1R_FSC27 0x08000000U /*!<Filter Scale Configuration bit 27 */
+
+/****************** Bit definition for CAN_FFA1R register *******************/
+#define CAN_FFA1R_FFA 0x0FFFFFFFU /*!<Filter FIFO Assignment */
+#define CAN_FFA1R_FFA0 0x00000001U /*!<Filter FIFO Assignment bit 0 */
+#define CAN_FFA1R_FFA1 0x00000002U /*!<Filter FIFO Assignment bit 1 */
+#define CAN_FFA1R_FFA2 0x00000004U /*!<Filter FIFO Assignment bit 2 */
+#define CAN_FFA1R_FFA3 0x00000008U /*!<Filter FIFO Assignment bit 3 */
+#define CAN_FFA1R_FFA4 0x00000010U /*!<Filter FIFO Assignment bit 4 */
+#define CAN_FFA1R_FFA5 0x00000020U /*!<Filter FIFO Assignment bit 5 */
+#define CAN_FFA1R_FFA6 0x00000040U /*!<Filter FIFO Assignment bit 6 */
+#define CAN_FFA1R_FFA7 0x00000080U /*!<Filter FIFO Assignment bit 7 */
+#define CAN_FFA1R_FFA8 0x00000100U /*!<Filter FIFO Assignment bit 8 */
+#define CAN_FFA1R_FFA9 0x00000200U /*!<Filter FIFO Assignment bit 9 */
+#define CAN_FFA1R_FFA10 0x00000400U /*!<Filter FIFO Assignment bit 10 */
+#define CAN_FFA1R_FFA11 0x00000800U /*!<Filter FIFO Assignment bit 11 */
+#define CAN_FFA1R_FFA12 0x00001000U /*!<Filter FIFO Assignment bit 12 */
+#define CAN_FFA1R_FFA13 0x00002000U /*!<Filter FIFO Assignment bit 13 */
+#define CAN_FFA1R_FFA14 0x00004000U /*!<Filter FIFO Assignment bit 14 */
+#define CAN_FFA1R_FFA15 0x00008000U /*!<Filter FIFO Assignment bit 15 */
+#define CAN_FFA1R_FFA16 0x00010000U /*!<Filter FIFO Assignment bit 16 */
+#define CAN_FFA1R_FFA17 0x00020000U /*!<Filter FIFO Assignment bit 17 */
+#define CAN_FFA1R_FFA18 0x00040000U /*!<Filter FIFO Assignment bit 18 */
+#define CAN_FFA1R_FFA19 0x00080000U /*!<Filter FIFO Assignment bit 19 */
+#define CAN_FFA1R_FFA20 0x00100000U /*!<Filter FIFO Assignment bit 20 */
+#define CAN_FFA1R_FFA21 0x00200000U /*!<Filter FIFO Assignment bit 21 */
+#define CAN_FFA1R_FFA22 0x00400000U /*!<Filter FIFO Assignment bit 22 */
+#define CAN_FFA1R_FFA23 0x00800000U /*!<Filter FIFO Assignment bit 23 */
+#define CAN_FFA1R_FFA24 0x01000000U /*!<Filter FIFO Assignment bit 24 */
+#define CAN_FFA1R_FFA25 0x02000000U /*!<Filter FIFO Assignment bit 25 */
+#define CAN_FFA1R_FFA26 0x04000000U /*!<Filter FIFO Assignment bit 26 */
+#define CAN_FFA1R_FFA27 0x08000000U /*!<Filter FIFO Assignment bit 27 */
+
+/******************* Bit definition for CAN_FA1R register *******************/
+#define CAN_FA1R_FACT 0x0FFFFFFFU /*!<Filter Active */
+#define CAN_FA1R_FACT0 0x00000001U /*!<Filter Active bit 0 */
+#define CAN_FA1R_FACT1 0x00000002U /*!<Filter Active bit 1 */
+#define CAN_FA1R_FACT2 0x00000004U /*!<Filter Active bit 2 */
+#define CAN_FA1R_FACT3 0x00000008U /*!<Filter Active bit 3 */
+#define CAN_FA1R_FACT4 0x00000010U /*!<Filter Active bit 4 */
+#define CAN_FA1R_FACT5 0x00000020U /*!<Filter Active bit 5 */
+#define CAN_FA1R_FACT6 0x00000040U /*!<Filter Active bit 6 */
+#define CAN_FA1R_FACT7 0x00000080U /*!<Filter Active bit 7 */
+#define CAN_FA1R_FACT8 0x00000100U /*!<Filter Active bit 8 */
+#define CAN_FA1R_FACT9 0x00000200U /*!<Filter Active bit 9 */
+#define CAN_FA1R_FACT10 0x00000400U /*!<Filter Active bit 10 */
+#define CAN_FA1R_FACT11 0x00000800U /*!<Filter Active bit 11 */
+#define CAN_FA1R_FACT12 0x00001000U /*!<Filter Active bit 12 */
+#define CAN_FA1R_FACT13 0x00002000U /*!<Filter Active bit 13 */
+#define CAN_FA1R_FACT14 0x00004000U /*!<Filter Active bit 14 */
+#define CAN_FA1R_FACT15 0x00008000U /*!<Filter Active bit 15 */
+#define CAN_FA1R_FACT16 0x00010000U /*!<Filter Active bit 16 */
+#define CAN_FA1R_FACT17 0x00020000U /*!<Filter Active bit 17 */
+#define CAN_FA1R_FACT18 0x00040000U /*!<Filter Active bit 18 */
+#define CAN_FA1R_FACT19 0x00080000U /*!<Filter Active bit 19 */
+#define CAN_FA1R_FACT20 0x00100000U /*!<Filter Active bit 20 */
+#define CAN_FA1R_FACT21 0x00200000U /*!<Filter Active bit 21 */
+#define CAN_FA1R_FACT22 0x00400000U /*!<Filter Active bit 22 */
+#define CAN_FA1R_FACT23 0x00800000U /*!<Filter Active bit 23 */
+#define CAN_FA1R_FACT24 0x01000000U /*!<Filter Active bit 24 */
+#define CAN_FA1R_FACT25 0x02000000U /*!<Filter Active bit 25 */
+#define CAN_FA1R_FACT26 0x04000000U /*!<Filter Active bit 26 */
+#define CAN_FA1R_FACT27 0x08000000U /*!<Filter Active bit 27 */
+
+/******************* Bit definition for CAN_F0R1 register *******************/
+#define CAN_F0R1_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F0R1_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F0R1_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F0R1_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F0R1_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F0R1_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F0R1_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F0R1_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F0R1_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F0R1_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F0R1_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F0R1_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F0R1_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F0R1_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F0R1_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F0R1_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F0R1_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F0R1_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F0R1_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F0R1_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F0R1_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F0R1_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F0R1_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F0R1_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F0R1_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F0R1_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F0R1_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F0R1_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F0R1_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F0R1_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F0R1_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F0R1_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F1R1 register *******************/
+#define CAN_F1R1_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F1R1_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F1R1_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F1R1_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F1R1_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F1R1_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F1R1_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F1R1_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F1R1_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F1R1_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F1R1_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F1R1_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F1R1_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F1R1_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F1R1_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F1R1_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F1R1_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F1R1_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F1R1_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F1R1_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F1R1_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F1R1_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F1R1_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F1R1_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F1R1_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F1R1_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F1R1_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F1R1_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F1R1_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F1R1_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F1R1_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F1R1_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F2R1 register *******************/
+#define CAN_F2R1_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F2R1_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F2R1_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F2R1_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F2R1_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F2R1_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F2R1_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F2R1_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F2R1_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F2R1_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F2R1_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F2R1_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F2R1_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F2R1_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F2R1_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F2R1_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F2R1_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F2R1_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F2R1_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F2R1_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F2R1_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F2R1_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F2R1_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F2R1_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F2R1_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F2R1_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F2R1_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F2R1_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F2R1_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F2R1_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F2R1_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F2R1_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F3R1 register *******************/
+#define CAN_F3R1_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F3R1_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F3R1_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F3R1_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F3R1_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F3R1_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F3R1_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F3R1_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F3R1_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F3R1_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F3R1_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F3R1_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F3R1_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F3R1_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F3R1_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F3R1_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F3R1_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F3R1_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F3R1_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F3R1_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F3R1_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F3R1_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F3R1_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F3R1_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F3R1_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F3R1_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F3R1_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F3R1_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F3R1_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F3R1_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F3R1_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F3R1_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F4R1 register *******************/
+#define CAN_F4R1_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F4R1_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F4R1_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F4R1_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F4R1_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F4R1_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F4R1_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F4R1_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F4R1_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F4R1_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F4R1_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F4R1_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F4R1_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F4R1_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F4R1_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F4R1_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F4R1_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F4R1_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F4R1_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F4R1_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F4R1_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F4R1_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F4R1_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F4R1_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F4R1_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F4R1_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F4R1_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F4R1_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F4R1_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F4R1_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F4R1_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F4R1_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F5R1 register *******************/
+#define CAN_F5R1_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F5R1_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F5R1_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F5R1_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F5R1_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F5R1_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F5R1_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F5R1_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F5R1_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F5R1_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F5R1_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F5R1_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F5R1_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F5R1_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F5R1_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F5R1_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F5R1_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F5R1_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F5R1_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F5R1_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F5R1_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F5R1_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F5R1_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F5R1_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F5R1_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F5R1_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F5R1_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F5R1_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F5R1_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F5R1_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F5R1_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F5R1_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F6R1 register *******************/
+#define CAN_F6R1_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F6R1_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F6R1_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F6R1_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F6R1_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F6R1_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F6R1_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F6R1_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F6R1_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F6R1_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F6R1_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F6R1_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F6R1_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F6R1_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F6R1_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F6R1_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F6R1_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F6R1_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F6R1_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F6R1_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F6R1_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F6R1_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F6R1_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F6R1_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F6R1_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F6R1_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F6R1_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F6R1_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F6R1_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F6R1_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F6R1_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F6R1_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F7R1 register *******************/
+#define CAN_F7R1_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F7R1_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F7R1_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F7R1_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F7R1_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F7R1_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F7R1_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F7R1_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F7R1_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F7R1_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F7R1_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F7R1_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F7R1_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F7R1_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F7R1_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F7R1_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F7R1_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F7R1_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F7R1_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F7R1_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F7R1_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F7R1_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F7R1_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F7R1_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F7R1_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F7R1_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F7R1_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F7R1_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F7R1_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F7R1_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F7R1_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F7R1_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F8R1 register *******************/
+#define CAN_F8R1_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F8R1_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F8R1_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F8R1_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F8R1_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F8R1_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F8R1_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F8R1_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F8R1_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F8R1_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F8R1_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F8R1_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F8R1_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F8R1_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F8R1_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F8R1_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F8R1_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F8R1_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F8R1_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F8R1_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F8R1_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F8R1_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F8R1_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F8R1_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F8R1_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F8R1_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F8R1_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F8R1_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F8R1_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F8R1_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F8R1_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F8R1_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F9R1 register *******************/
+#define CAN_F9R1_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F9R1_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F9R1_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F9R1_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F9R1_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F9R1_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F9R1_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F9R1_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F9R1_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F9R1_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F9R1_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F9R1_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F9R1_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F9R1_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F9R1_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F9R1_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F9R1_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F9R1_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F9R1_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F9R1_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F9R1_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F9R1_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F9R1_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F9R1_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F9R1_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F9R1_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F9R1_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F9R1_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F9R1_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F9R1_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F9R1_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F9R1_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F10R1 register ******************/
+#define CAN_F10R1_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F10R1_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F10R1_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F10R1_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F10R1_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F10R1_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F10R1_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F10R1_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F10R1_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F10R1_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F10R1_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F10R1_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F10R1_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F10R1_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F10R1_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F10R1_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F10R1_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F10R1_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F10R1_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F10R1_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F10R1_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F10R1_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F10R1_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F10R1_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F10R1_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F10R1_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F10R1_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F10R1_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F10R1_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F10R1_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F10R1_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F10R1_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F11R1 register ******************/
+#define CAN_F11R1_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F11R1_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F11R1_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F11R1_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F11R1_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F11R1_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F11R1_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F11R1_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F11R1_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F11R1_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F11R1_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F11R1_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F11R1_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F11R1_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F11R1_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F11R1_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F11R1_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F11R1_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F11R1_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F11R1_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F11R1_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F11R1_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F11R1_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F11R1_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F11R1_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F11R1_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F11R1_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F11R1_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F11R1_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F11R1_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F11R1_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F11R1_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F12R1 register ******************/
+#define CAN_F12R1_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F12R1_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F12R1_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F12R1_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F12R1_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F12R1_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F12R1_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F12R1_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F12R1_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F12R1_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F12R1_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F12R1_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F12R1_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F12R1_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F12R1_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F12R1_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F12R1_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F12R1_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F12R1_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F12R1_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F12R1_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F12R1_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F12R1_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F12R1_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F12R1_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F12R1_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F12R1_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F12R1_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F12R1_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F12R1_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F12R1_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F12R1_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F13R1 register ******************/
+#define CAN_F13R1_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F13R1_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F13R1_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F13R1_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F13R1_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F13R1_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F13R1_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F13R1_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F13R1_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F13R1_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F13R1_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F13R1_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F13R1_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F13R1_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F13R1_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F13R1_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F13R1_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F13R1_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F13R1_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F13R1_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F13R1_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F13R1_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F13R1_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F13R1_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F13R1_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F13R1_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F13R1_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F13R1_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F13R1_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F13R1_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F13R1_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F13R1_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F0R2 register *******************/
+#define CAN_F0R2_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F0R2_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F0R2_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F0R2_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F0R2_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F0R2_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F0R2_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F0R2_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F0R2_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F0R2_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F0R2_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F0R2_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F0R2_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F0R2_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F0R2_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F0R2_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F0R2_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F0R2_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F0R2_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F0R2_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F0R2_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F0R2_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F0R2_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F0R2_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F0R2_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F0R2_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F0R2_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F0R2_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F0R2_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F0R2_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F0R2_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F0R2_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F1R2 register *******************/
+#define CAN_F1R2_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F1R2_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F1R2_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F1R2_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F1R2_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F1R2_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F1R2_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F1R2_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F1R2_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F1R2_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F1R2_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F1R2_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F1R2_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F1R2_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F1R2_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F1R2_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F1R2_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F1R2_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F1R2_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F1R2_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F1R2_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F1R2_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F1R2_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F1R2_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F1R2_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F1R2_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F1R2_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F1R2_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F1R2_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F1R2_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F1R2_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F1R2_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F2R2 register *******************/
+#define CAN_F2R2_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F2R2_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F2R2_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F2R2_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F2R2_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F2R2_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F2R2_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F2R2_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F2R2_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F2R2_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F2R2_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F2R2_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F2R2_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F2R2_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F2R2_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F2R2_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F2R2_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F2R2_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F2R2_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F2R2_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F2R2_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F2R2_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F2R2_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F2R2_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F2R2_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F2R2_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F2R2_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F2R2_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F2R2_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F2R2_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F2R2_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F2R2_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F3R2 register *******************/
+#define CAN_F3R2_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F3R2_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F3R2_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F3R2_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F3R2_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F3R2_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F3R2_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F3R2_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F3R2_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F3R2_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F3R2_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F3R2_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F3R2_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F3R2_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F3R2_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F3R2_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F3R2_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F3R2_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F3R2_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F3R2_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F3R2_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F3R2_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F3R2_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F3R2_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F3R2_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F3R2_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F3R2_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F3R2_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F3R2_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F3R2_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F3R2_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F3R2_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F4R2 register *******************/
+#define CAN_F4R2_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F4R2_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F4R2_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F4R2_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F4R2_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F4R2_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F4R2_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F4R2_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F4R2_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F4R2_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F4R2_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F4R2_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F4R2_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F4R2_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F4R2_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F4R2_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F4R2_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F4R2_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F4R2_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F4R2_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F4R2_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F4R2_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F4R2_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F4R2_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F4R2_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F4R2_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F4R2_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F4R2_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F4R2_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F4R2_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F4R2_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F4R2_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F5R2 register *******************/
+#define CAN_F5R2_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F5R2_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F5R2_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F5R2_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F5R2_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F5R2_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F5R2_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F5R2_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F5R2_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F5R2_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F5R2_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F5R2_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F5R2_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F5R2_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F5R2_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F5R2_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F5R2_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F5R2_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F5R2_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F5R2_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F5R2_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F5R2_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F5R2_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F5R2_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F5R2_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F5R2_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F5R2_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F5R2_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F5R2_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F5R2_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F5R2_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F5R2_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F6R2 register *******************/
+#define CAN_F6R2_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F6R2_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F6R2_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F6R2_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F6R2_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F6R2_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F6R2_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F6R2_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F6R2_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F6R2_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F6R2_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F6R2_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F6R2_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F6R2_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F6R2_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F6R2_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F6R2_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F6R2_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F6R2_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F6R2_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F6R2_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F6R2_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F6R2_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F6R2_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F6R2_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F6R2_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F6R2_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F6R2_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F6R2_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F6R2_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F6R2_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F6R2_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F7R2 register *******************/
+#define CAN_F7R2_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F7R2_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F7R2_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F7R2_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F7R2_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F7R2_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F7R2_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F7R2_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F7R2_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F7R2_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F7R2_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F7R2_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F7R2_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F7R2_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F7R2_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F7R2_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F7R2_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F7R2_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F7R2_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F7R2_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F7R2_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F7R2_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F7R2_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F7R2_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F7R2_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F7R2_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F7R2_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F7R2_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F7R2_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F7R2_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F7R2_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F7R2_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F8R2 register *******************/
+#define CAN_F8R2_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F8R2_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F8R2_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F8R2_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F8R2_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F8R2_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F8R2_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F8R2_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F8R2_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F8R2_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F8R2_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F8R2_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F8R2_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F8R2_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F8R2_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F8R2_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F8R2_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F8R2_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F8R2_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F8R2_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F8R2_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F8R2_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F8R2_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F8R2_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F8R2_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F8R2_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F8R2_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F8R2_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F8R2_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F8R2_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F8R2_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F8R2_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F9R2 register *******************/
+#define CAN_F9R2_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F9R2_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F9R2_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F9R2_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F9R2_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F9R2_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F9R2_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F9R2_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F9R2_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F9R2_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F9R2_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F9R2_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F9R2_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F9R2_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F9R2_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F9R2_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F9R2_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F9R2_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F9R2_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F9R2_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F9R2_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F9R2_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F9R2_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F9R2_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F9R2_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F9R2_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F9R2_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F9R2_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F9R2_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F9R2_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F9R2_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F9R2_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F10R2 register ******************/
+#define CAN_F10R2_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F10R2_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F10R2_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F10R2_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F10R2_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F10R2_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F10R2_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F10R2_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F10R2_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F10R2_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F10R2_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F10R2_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F10R2_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F10R2_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F10R2_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F10R2_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F10R2_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F10R2_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F10R2_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F10R2_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F10R2_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F10R2_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F10R2_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F10R2_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F10R2_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F10R2_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F10R2_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F10R2_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F10R2_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F10R2_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F10R2_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F10R2_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F11R2 register ******************/
+#define CAN_F11R2_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F11R2_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F11R2_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F11R2_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F11R2_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F11R2_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F11R2_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F11R2_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F11R2_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F11R2_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F11R2_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F11R2_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F11R2_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F11R2_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F11R2_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F11R2_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F11R2_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F11R2_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F11R2_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F11R2_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F11R2_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F11R2_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F11R2_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F11R2_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F11R2_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F11R2_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F11R2_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F11R2_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F11R2_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F11R2_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F11R2_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F11R2_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F12R2 register ******************/
+#define CAN_F12R2_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F12R2_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F12R2_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F12R2_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F12R2_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F12R2_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F12R2_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F12R2_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F12R2_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F12R2_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F12R2_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F12R2_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F12R2_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F12R2_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F12R2_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F12R2_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F12R2_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F12R2_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F12R2_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F12R2_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F12R2_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F12R2_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F12R2_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F12R2_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F12R2_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F12R2_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F12R2_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F12R2_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F12R2_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F12R2_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F12R2_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F12R2_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F13R2 register ******************/
+#define CAN_F13R2_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F13R2_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F13R2_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F13R2_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F13R2_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F13R2_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F13R2_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F13R2_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F13R2_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F13R2_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F13R2_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F13R2_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F13R2_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F13R2_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F13R2_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F13R2_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F13R2_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F13R2_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F13R2_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F13R2_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F13R2_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F13R2_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F13R2_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F13R2_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F13R2_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F13R2_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F13R2_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F13R2_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F13R2_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F13R2_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F13R2_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F13R2_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************************************************************************/
+/* */
+/* CRC calculation unit */
+/* */
+/******************************************************************************/
+/******************* Bit definition for CRC_DR register *********************/
+#define CRC_DR_DR 0xFFFFFFFFU /*!< Data register bits */
+
+
+/******************* Bit definition for CRC_IDR register ********************/
+#define CRC_IDR_IDR 0xFFU /*!< General-purpose 8-bit data register bits */
+
+
+/******************** Bit definition for CRC_CR register ********************/
+#define CRC_CR_RESET 0x01U /*!< RESET bit */
+
+/******************************************************************************/
+/* */
+/* Debug MCU */
+/* */
+/******************************************************************************/
+
+/******************************************************************************/
+/* */
+/* Digital Filter for Sigma Delta Modulators */
+/* */
+/******************************************************************************/
+
+/**************** DFSDM channel configuration registers ********************/
+
+/*************** Bit definition for DFSDM_CHCFGR1 register ******************/
+#define DFSDM_CHCFGR1_DFSDMEN 0x80000000U /*!< Global enable for DFSDM interface */
+#define DFSDM_CHCFGR1_CKOUTSRC 0x40000000U /*!< Output serial clock source selection */
+#define DFSDM_CHCFGR1_CKOUTDIV 0x00FF0000U /*!< CKOUTDIV[7:0] output serial clock divider */
+#define DFSDM_CHCFGR1_DATPACK 0x0000C000U /*!< DATPACK[1:0] Data packing mode */
+#define DFSDM_CHCFGR1_DATPACK_1 0x00008000U /*!< Data packing mode, Bit 1 */
+#define DFSDM_CHCFGR1_DATPACK_0 0x00004000U /*!< Data packing mode, Bit 0 */
+#define DFSDM_CHCFGR1_DATMPX 0x00003000U /*!< DATMPX[1:0] Input data multiplexer for channel y */
+#define DFSDM_CHCFGR1_DATMPX_1 0x00002000U /*!< Input data multiplexer for channel y, Bit 1 */
+#define DFSDM_CHCFGR1_DATMPX_0 0x00001000U /*!< Input data multiplexer for channel y, Bit 0 */
+#define DFSDM_CHCFGR1_CHINSEL 0x00000100U /*!< Serial inputs selection for channel y */
+#define DFSDM_CHCFGR1_CHEN 0x00000080U /*!< Channel y enable */
+#define DFSDM_CHCFGR1_CKABEN 0x00000040U /*!< Clock absence detector enable on channel y */
+#define DFSDM_CHCFGR1_SCDEN 0x00000020U /*!< Short circuit detector enable on channel y */
+#define DFSDM_CHCFGR1_SPICKSEL 0x0000000CU /*!< SPICKSEL[1:0] SPI clock select for channel y */
+#define DFSDM_CHCFGR1_SPICKSEL_1 0x00000008U /*!< SPI clock select for channel y, Bit 1 */
+#define DFSDM_CHCFGR1_SPICKSEL_0 0x00000004U /*!< SPI clock select for channel y, Bit 0 */
+#define DFSDM_CHCFGR1_SITP 0x00000003U /*!< SITP[1:0] Serial interface type for channel y */
+#define DFSDM_CHCFGR1_SITP_1 0x00000002U /*!< Serial interface type for channel y, Bit 1 */
+#define DFSDM_CHCFGR1_SITP_0 0x00000001U /*!< Serial interface type for channel y, Bit 0 */
+
+/*************** Bit definition for DFSDM_CHCFGR2 register ******************/
+#define DFSDM_CHCFGR2_OFFSET 0xFFFFFF00U /*!< OFFSET[23:0] 24-bit calibration offset for channel y */
+#define DFSDM_CHCFGR2_DTRBS 0x000000F8U /*!< DTRBS[4:0] Data right bit-shift for channel y */
+
+/**************** Bit definition for DFSDM_CHAWSCDR register *****************/
+#define DFSDM_CHAWSCDR_AWFORD 0x00C00000U /*!< AWFORD[1:0] Analog watchdog Sinc filter order on channel y */
+#define DFSDM_CHAWSCDR_AWFORD_1 0x00800000U /*!< Analog watchdog Sinc filter order on channel y, Bit 1 */
+#define DFSDM_CHAWSCDR_AWFORD_0 0x00400000U /*!< Analog watchdog Sinc filter order on channel y, Bit 0 */
+#define DFSDM_CHAWSCDR_AWFOSR 0x001F0000U /*!< AWFOSR[4:0] Analog watchdog filter oversampling ratio on channel y */
+#define DFSDM_CHAWSCDR_BKSCD 0x0000F000U /*!< BKSCD[3:0] Break signal assignment for short circuit detector on channel y */
+#define DFSDM_CHAWSCDR_SCDT 0x000000FFU /*!< SCDT[7:0] Short circuit detector threshold for channel y */
+
+/**************** Bit definition for DFSDM_CHWDATR register *******************/
+#define DFSDM_CHWDATR_WDATA 0x0000FFFFU /*!< WDATA[15:0] Input channel y watchdog data */
+
+/**************** Bit definition for DFSDM_CHDATINR register *****************/
+#define DFSDM_CHDATINR_INDAT0 0x0000FFFFU /*!< INDAT0[31:16] Input data for channel y or channel (y+1) */
+#define DFSDM_CHDATINR_INDAT1 0xFFFF0000U /*!< INDAT0[15:0] Input data for channel y */
+
+/************************ DFSDM module registers ****************************/
+
+/***************** Bit definition for DFSDM_FLTCR1 register *******************/
+#define DFSDM_FLTCR1_AWFSEL 0x40000000U /*!< Analog watchdog fast mode select */
+#define DFSDM_FLTCR1_FAST 0x20000000U /*!< Fast conversion mode selection */
+#define DFSDM_FLTCR1_RCH 0x07000000U /*!< RCH[2:0] Regular channel selection */
+#define DFSDM_FLTCR1_RDMAEN 0x00200000U /*!< DMA channel enabled to read data for the regular conversion */
+#define DFSDM_FLTCR1_RSYNC 0x00080000U /*!< Launch regular conversion synchronously with DFSDMx */
+#define DFSDM_FLTCR1_RCONT 0x00040000U /*!< Continuous mode selection for regular conversions */
+#define DFSDM_FLTCR1_RSWSTART 0x00020000U /*!< Software start of a conversion on the regular channel */
+#define DFSDM_FLTCR1_JEXTEN 0x00006000U /*!< JEXTEN[1:0] Trigger enable and trigger edge selection for injected conversions */
+#define DFSDM_FLTCR1_JEXTEN_1 0x00004000U /*!< Trigger enable and trigger edge selection for injected conversions, Bit 1 */
+#define DFSDM_FLTCR1_JEXTEN_0 0x00002000U /*!< Trigger enable and trigger edge selection for injected conversions, Bit 0 */
+#define DFSDM_FLTCR1_JEXTSEL 0x00000700U /*!< JEXTSEL[2:0]Trigger signal selection for launching injected conversions */
+#define DFSDM_FLTCR1_JEXTSEL_2 0x00000400U /*!< Trigger signal selection for launching injected conversions, Bit 2 */
+#define DFSDM_FLTCR1_JEXTSEL_1 0x00000200U /*!< Trigger signal selection for launching injected conversions, Bit 1 */
+#define DFSDM_FLTCR1_JEXTSEL_0 0x00000100U /*!< Trigger signal selection for launching injected conversions, Bit 0 */
+#define DFSDM_FLTCR1_JDMAEN 0x00000020U /*!< DMA channel enabled to read data for the injected channel group */
+#define DFSDM_FLTCR1_JSCAN 0x00000010U /*!< Scanning conversion in continuous mode selection for injected conversions */
+#define DFSDM_FLTCR1_JSYNC 0x00000008U /*!< Launch an injected conversion synchronously with DFSDMx JSWSTART trigger */
+#define DFSDM_FLTCR1_JSWSTART 0x00000002U /*!< Start the conversion of the injected group of channels */
+#define DFSDM_FLTCR1_DFEN 0x00000001U /*!< DFSDM enable */
+
+/***************** Bit definition for DFSDM_FLTCR2 register *******************/
+#define DFSDM_FLTCR2_AWDCH 0x000F0000U /*!< AWDCH[7:0] Analog watchdog channel selection */
+#define DFSDM_FLTCR2_EXCH 0x00000F00U /*!< EXCH[7:0] Extreme detector channel selection */
+#define DFSDM_FLTCR2_CKABIE 0x00000040U /*!< Clock absence interrupt enable */
+#define DFSDM_FLTCR2_SCDIE 0x00000020U /*!< Short circuit detector interrupt enable */
+#define DFSDM_FLTCR2_AWDIE 0x00000010U /*!< Analog watchdog interrupt enable */
+#define DFSDM_FLTCR2_ROVRIE 0x00000008U /*!< Regular data overrun interrupt enable */
+#define DFSDM_FLTCR2_JOVRIE 0x00000004U /*!< Injected data overrun interrupt enable */
+#define DFSDM_FLTCR2_REOCIE 0x00000002U /*!< Regular end of conversion interrupt enable */
+#define DFSDM_FLTCR2_JEOCIE 0x00000001U /*!< Injected end of conversion interrupt enable */
+
+/***************** Bit definition for DFSDM_FLTISR register *******************/
+#define DFSDM_FLTISR_SCDF 0x0F000000U /*!< SCDF[7:0] Short circuit detector flag */
+#define DFSDM_FLTISR_CKABF 0x000F0000U /*!< CKABF[7:0] Clock absence flag */
+#define DFSDM_FLTISR_RCIP 0x00004000U /*!< Regular conversion in progress status */
+#define DFSDM_FLTISR_JCIP 0x00002000U /*!< Injected conversion in progress status */
+#define DFSDM_FLTISR_AWDF 0x00000010U /*!< Analog watchdog */
+#define DFSDM_FLTISR_ROVRF 0x00000008U /*!< Regular conversion overrun flag */
+#define DFSDM_FLTISR_JOVRF 0x00000004U /*!< Injected conversion overrun flag */
+#define DFSDM_FLTISR_REOCF 0x00000002U /*!< End of regular conversion flag */
+#define DFSDM_FLTISR_JEOCF 0x00000001U /*!< End of injected conversion flag */
+
+/***************** Bit definition for DFSDM_FLTICR register *******************/
+#define DFSDM_FLTICR_CLRSCSDF 0x0F000000U /*!< CLRSCSDF[7:0] Clear the short circuit detector flag */
+#define DFSDM_FLTICR_CLRCKABF 0x000F0000U /*!< CLRCKABF[7:0] Clear the clock absence flag */
+#define DFSDM_FLTICR_CLRROVRF 0x00000008U /*!< Clear the regular conversion overrun flag */
+#define DFSDM_FLTICR_CLRJOVRF 0x00000004U /*!< Clear the injected conversion overrun flag */
+
+/**************** Bit definition for DFSDM_FLTJCHGR register ******************/
+#define DFSDM_FLTJCHGR_JCHG 0x0000000FU /*!< JCHG[7:0] Injected channel group selection */
+
+/***************** Bit definition for DFSDM_FLTFCR register *******************/
+#define DFSDM_FLTFCR_FORD 0xE0000000U /*!< FORD[2:0] Sinc filter order */
+#define DFSDM_FLTFCR_FORD_2 0x80000000U /*!< Sinc filter order, Bit 2 */
+#define DFSDM_FLTFCR_FORD_1 0x40000000U /*!< Sinc filter order, Bit 1 */
+#define DFSDM_FLTFCR_FORD_0 0x20000000U /*!< Sinc filter order, Bit 0 */
+#define DFSDM_FLTFCR_FOSR 0x03FF0000U /*!< FOSR[9:0] Sinc filter oversampling ratio (decimation rate) */
+#define DFSDM_FLTFCR_IOSR 0x000000FFU /*!< IOSR[7:0] Integrator oversampling ratio (averaging length) */
+
+/*************** Bit definition for DFSDM_FLTJDATAR register *****************/
+#define DFSDM_FLTJDATAR_JDATA 0xFFFFFF00U /*!< JDATA[23:0] Injected group conversion data */
+#define DFSDM_FLTJDATAR_JDATACH 0x00000007U /*!< JDATACH[2:0] Injected channel most recently converted */
+
+/*************** Bit definition for DFSDM_FLTRDATAR register *****************/
+#define DFSDM_FLTRDATAR_RDATA 0xFFFFFF00U /*!< RDATA[23:0] Regular channel conversion data */
+#define DFSDM_FLTRDATAR_RPEND 0x00000010U /*!< RPEND Regular channel pending data */
+#define DFSDM_FLTRDATAR_RDATACH 0x00000007U /*!< RDATACH[2:0] Regular channel most recently converted */
+
+/*************** Bit definition for DFSDM_FLTAWHTR register ******************/
+#define DFSDM_FLTAWHTR_AWHT 0xFFFFFF00U /*!< AWHT[23:0] Analog watchdog high threshold */
+#define DFSDM_FLTAWHTR_BKAWH 0x0000000FU /*!< BKAWH[3:0] Break signal assignment to analog watchdog high threshold event */
+
+/*************** Bit definition for DFSDM_FLTAWLTR register ******************/
+#define DFSDM_FLTAWLTR_AWLT 0xFFFFFF00U /*!< AWLT[23:0] Analog watchdog low threshold */
+#define DFSDM_FLTAWLTR_BKAWL 0x0000000FU /*!< BKAWL[3:0] Break signal assignment to analog watchdog low threshold event */
+
+/*************** Bit definition for DFSDM_FLTAWSR register *******************/
+#define DFSDM_FLTAWSR_AWHTF 0x00000F00U /*!< AWHTF[15:8] Analog watchdog high threshold error on given channels */
+#define DFSDM_FLTAWSR_AWLTF 0x0000000FU /*!< AWLTF[7:0] Analog watchdog low threshold error on given channels */
+
+/*************** Bit definition for DFSDM_FLTAWCFR register ******************/
+#define DFSDM_FLTAWCFR_CLRAWHTF 0x00000F00U /*!< CLRAWHTF[15:8] Clear the Analog watchdog high threshold flag */
+#define DFSDM_FLTAWCFR_CLRAWLTF 0x0000000FU /*!< CLRAWLTF[7:0] Clear the Analog watchdog low threshold flag */
+
+/*************** Bit definition for DFSDM_FLTEXMAX register ******************/
+#define DFSDM_FLTEXMAX_EXMAX 0xFFFFFF00U /*!< EXMAX[23:0] Extreme detector maximum value */
+#define DFSDM_FLTEXMAX_EXMAXCH 0x00000007U /*!< EXMAXCH[2:0] Extreme detector maximum data channel */
+
+/*************** Bit definition for DFSDM_FLTEXMIN register ******************/
+#define DFSDM_FLTEXMIN_EXMIN 0xFFFFFF00U /*!< EXMIN[23:0] Extreme detector minimum value */
+#define DFSDM_FLTEXMIN_EXMINCH 0x00000007U /*!< EXMINCH[2:0] Extreme detector minimum data channel */
+
+/*************** Bit definition for DFSDM_FLTCNVTIMR register ****************/
+#define DFSDM_FLTCNVTIMR_CNVCNT 0xFFFFFFF0U /*!< CNVCNT[27:0]: 28-bit timer counting conversion time */
+
+/******************************************************************************/
+/* */
+/* DMA Controller */
+/* */
+/******************************************************************************/
+/******************** Bits definition for DMA_SxCR register *****************/
+#define DMA_SxCR_CHSEL 0x0E000000U
+#define DMA_SxCR_CHSEL_0 0x02000000U
+#define DMA_SxCR_CHSEL_1 0x04000000U
+#define DMA_SxCR_CHSEL_2 0x08000000U
+#define DMA_SxCR_MBURST 0x01800000U
+#define DMA_SxCR_MBURST_0 0x00800000U
+#define DMA_SxCR_MBURST_1 0x01000000U
+#define DMA_SxCR_PBURST 0x00600000U
+#define DMA_SxCR_PBURST_0 0x00200000U
+#define DMA_SxCR_PBURST_1 0x00400000U
+#define DMA_SxCR_CT 0x00080000U
+#define DMA_SxCR_DBM 0x00040000U
+#define DMA_SxCR_PL 0x00030000U
+#define DMA_SxCR_PL_0 0x00010000U
+#define DMA_SxCR_PL_1 0x00020000U
+#define DMA_SxCR_PINCOS 0x00008000U
+#define DMA_SxCR_MSIZE 0x00006000U
+#define DMA_SxCR_MSIZE_0 0x00002000U
+#define DMA_SxCR_MSIZE_1 0x00004000U
+#define DMA_SxCR_PSIZE 0x00001800U
+#define DMA_SxCR_PSIZE_0 0x00000800U
+#define DMA_SxCR_PSIZE_1 0x00001000U
+#define DMA_SxCR_MINC 0x00000400U
+#define DMA_SxCR_PINC 0x00000200U
+#define DMA_SxCR_CIRC 0x00000100U
+#define DMA_SxCR_DIR 0x000000C0U
+#define DMA_SxCR_DIR_0 0x00000040U
+#define DMA_SxCR_DIR_1 0x00000080U
+#define DMA_SxCR_PFCTRL 0x00000020U
+#define DMA_SxCR_TCIE 0x00000010U
+#define DMA_SxCR_HTIE 0x00000008U
+#define DMA_SxCR_TEIE 0x00000004U
+#define DMA_SxCR_DMEIE 0x00000002U
+#define DMA_SxCR_EN 0x00000001U
+
+/* Legacy defines */
+#define DMA_SxCR_ACK 0x00100000U
+
+/******************** Bits definition for DMA_SxCNDTR register **************/
+#define DMA_SxNDT 0x0000FFFFU
+#define DMA_SxNDT_0 0x00000001U
+#define DMA_SxNDT_1 0x00000002U
+#define DMA_SxNDT_2 0x00000004U
+#define DMA_SxNDT_3 0x00000008U
+#define DMA_SxNDT_4 0x00000010U
+#define DMA_SxNDT_5 0x00000020U
+#define DMA_SxNDT_6 0x00000040U
+#define DMA_SxNDT_7 0x00000080U
+#define DMA_SxNDT_8 0x00000100U
+#define DMA_SxNDT_9 0x00000200U
+#define DMA_SxNDT_10 0x00000400U
+#define DMA_SxNDT_11 0x00000800U
+#define DMA_SxNDT_12 0x00001000U
+#define DMA_SxNDT_13 0x00002000U
+#define DMA_SxNDT_14 0x00004000U
+#define DMA_SxNDT_15 0x00008000U
+
+/******************** Bits definition for DMA_SxFCR register ****************/
+#define DMA_SxFCR_FEIE 0x00000080U
+#define DMA_SxFCR_FS 0x00000038U
+#define DMA_SxFCR_FS_0 0x00000008U
+#define DMA_SxFCR_FS_1 0x00000010U
+#define DMA_SxFCR_FS_2 0x00000020U
+#define DMA_SxFCR_DMDIS 0x00000004U
+#define DMA_SxFCR_FTH 0x00000003U
+#define DMA_SxFCR_FTH_0 0x00000001U
+#define DMA_SxFCR_FTH_1 0x00000002U
+
+/******************** Bits definition for DMA_LISR register *****************/
+#define DMA_LISR_TCIF3 0x08000000U
+#define DMA_LISR_HTIF3 0x04000000U
+#define DMA_LISR_TEIF3 0x02000000U
+#define DMA_LISR_DMEIF3 0x01000000U
+#define DMA_LISR_FEIF3 0x00400000U
+#define DMA_LISR_TCIF2 0x00200000U
+#define DMA_LISR_HTIF2 0x00100000U
+#define DMA_LISR_TEIF2 0x00080000U
+#define DMA_LISR_DMEIF2 0x00040000U
+#define DMA_LISR_FEIF2 0x00010000U
+#define DMA_LISR_TCIF1 0x00000800U
+#define DMA_LISR_HTIF1 0x00000400U
+#define DMA_LISR_TEIF1 0x00000200U
+#define DMA_LISR_DMEIF1 0x00000100U
+#define DMA_LISR_FEIF1 0x00000040U
+#define DMA_LISR_TCIF0 0x00000020U
+#define DMA_LISR_HTIF0 0x00000010U
+#define DMA_LISR_TEIF0 0x00000008U
+#define DMA_LISR_DMEIF0 0x00000004U
+#define DMA_LISR_FEIF0 0x00000001U
+
+/******************** Bits definition for DMA_HISR register *****************/
+#define DMA_HISR_TCIF7 0x08000000U
+#define DMA_HISR_HTIF7 0x04000000U
+#define DMA_HISR_TEIF7 0x02000000U
+#define DMA_HISR_DMEIF7 0x01000000U
+#define DMA_HISR_FEIF7 0x00400000U
+#define DMA_HISR_TCIF6 0x00200000U
+#define DMA_HISR_HTIF6 0x00100000U
+#define DMA_HISR_TEIF6 0x00080000U
+#define DMA_HISR_DMEIF6 0x00040000U
+#define DMA_HISR_FEIF6 0x00010000U
+#define DMA_HISR_TCIF5 0x00000800U
+#define DMA_HISR_HTIF5 0x00000400U
+#define DMA_HISR_TEIF5 0x00000200U
+#define DMA_HISR_DMEIF5 0x00000100U
+#define DMA_HISR_FEIF5 0x00000040U
+#define DMA_HISR_TCIF4 0x00000020U
+#define DMA_HISR_HTIF4 0x00000010U
+#define DMA_HISR_TEIF4 0x00000008U
+#define DMA_HISR_DMEIF4 0x00000004U
+#define DMA_HISR_FEIF4 0x00000001U
+
+/******************** Bits definition for DMA_LIFCR register ****************/
+#define DMA_LIFCR_CTCIF3 0x08000000U
+#define DMA_LIFCR_CHTIF3 0x04000000U
+#define DMA_LIFCR_CTEIF3 0x02000000U
+#define DMA_LIFCR_CDMEIF3 0x01000000U
+#define DMA_LIFCR_CFEIF3 0x00400000U
+#define DMA_LIFCR_CTCIF2 0x00200000U
+#define DMA_LIFCR_CHTIF2 0x00100000U
+#define DMA_LIFCR_CTEIF2 0x00080000U
+#define DMA_LIFCR_CDMEIF2 0x00040000U
+#define DMA_LIFCR_CFEIF2 0x00010000U
+#define DMA_LIFCR_CTCIF1 0x00000800U
+#define DMA_LIFCR_CHTIF1 0x00000400U
+#define DMA_LIFCR_CTEIF1 0x00000200U
+#define DMA_LIFCR_CDMEIF1 0x00000100U
+#define DMA_LIFCR_CFEIF1 0x00000040U
+#define DMA_LIFCR_CTCIF0 0x00000020U
+#define DMA_LIFCR_CHTIF0 0x00000010U
+#define DMA_LIFCR_CTEIF0 0x00000008U
+#define DMA_LIFCR_CDMEIF0 0x00000004U
+#define DMA_LIFCR_CFEIF0 0x00000001U
+
+/******************** Bits definition for DMA_HIFCR register ****************/
+#define DMA_HIFCR_CTCIF7 0x08000000U
+#define DMA_HIFCR_CHTIF7 0x04000000U
+#define DMA_HIFCR_CTEIF7 0x02000000U
+#define DMA_HIFCR_CDMEIF7 0x01000000U
+#define DMA_HIFCR_CFEIF7 0x00400000U
+#define DMA_HIFCR_CTCIF6 0x00200000U
+#define DMA_HIFCR_CHTIF6 0x00100000U
+#define DMA_HIFCR_CTEIF6 0x00080000U
+#define DMA_HIFCR_CDMEIF6 0x00040000U
+#define DMA_HIFCR_CFEIF6 0x00010000U
+#define DMA_HIFCR_CTCIF5 0x00000800U
+#define DMA_HIFCR_CHTIF5 0x00000400U
+#define DMA_HIFCR_CTEIF5 0x00000200U
+#define DMA_HIFCR_CDMEIF5 0x00000100U
+#define DMA_HIFCR_CFEIF5 0x00000040U
+#define DMA_HIFCR_CTCIF4 0x00000020U
+#define DMA_HIFCR_CHTIF4 0x00000010U
+#define DMA_HIFCR_CTEIF4 0x00000008U
+#define DMA_HIFCR_CDMEIF4 0x00000004U
+#define DMA_HIFCR_CFEIF4 0x00000001U
+
+
+/******************************************************************************/
+/* */
+/* External Interrupt/Event Controller */
+/* */
+/******************************************************************************/
+/******************* Bit definition for EXTI_IMR register *******************/
+#define EXTI_IMR_MR0 0x00000001U /*!< Interrupt Mask on line 0 */
+#define EXTI_IMR_MR1 0x00000002U /*!< Interrupt Mask on line 1 */
+#define EXTI_IMR_MR2 0x00000004U /*!< Interrupt Mask on line 2 */
+#define EXTI_IMR_MR3 0x00000008U /*!< Interrupt Mask on line 3 */
+#define EXTI_IMR_MR4 0x00000010U /*!< Interrupt Mask on line 4 */
+#define EXTI_IMR_MR5 0x00000020U /*!< Interrupt Mask on line 5 */
+#define EXTI_IMR_MR6 0x00000040U /*!< Interrupt Mask on line 6 */
+#define EXTI_IMR_MR7 0x00000080U /*!< Interrupt Mask on line 7 */
+#define EXTI_IMR_MR8 0x00000100U /*!< Interrupt Mask on line 8 */
+#define EXTI_IMR_MR9 0x00000200U /*!< Interrupt Mask on line 9 */
+#define EXTI_IMR_MR10 0x00000400U /*!< Interrupt Mask on line 10 */
+#define EXTI_IMR_MR11 0x00000800U /*!< Interrupt Mask on line 11 */
+#define EXTI_IMR_MR12 0x00001000U /*!< Interrupt Mask on line 12 */
+#define EXTI_IMR_MR13 0x00002000U /*!< Interrupt Mask on line 13 */
+#define EXTI_IMR_MR14 0x00004000U /*!< Interrupt Mask on line 14 */
+#define EXTI_IMR_MR15 0x00008000U /*!< Interrupt Mask on line 15 */
+#define EXTI_IMR_MR16 0x00010000U /*!< Interrupt Mask on line 16 */
+#define EXTI_IMR_MR17 0x00020000U /*!< Interrupt Mask on line 17 */
+#define EXTI_IMR_MR18 0x00040000U /*!< Interrupt Mask on line 18 */
+#define EXTI_IMR_MR19 0x00080000U /*!< Interrupt Mask on line 19 */
+#define EXTI_IMR_MR20 0x00100000U /*!< Interrupt Mask on line 20 */
+#define EXTI_IMR_MR21 0x00200000U /*!< Interrupt Mask on line 21 */
+#define EXTI_IMR_MR22 0x00400000U /*!< Interrupt Mask on line 22 */
+
+/******************* Bit definition for EXTI_EMR register *******************/
+#define EXTI_EMR_MR0 0x00000001U /*!< Event Mask on line 0 */
+#define EXTI_EMR_MR1 0x00000002U /*!< Event Mask on line 1 */
+#define EXTI_EMR_MR2 0x00000004U /*!< Event Mask on line 2 */
+#define EXTI_EMR_MR3 0x00000008U /*!< Event Mask on line 3 */
+#define EXTI_EMR_MR4 0x00000010U /*!< Event Mask on line 4 */
+#define EXTI_EMR_MR5 0x00000020U /*!< Event Mask on line 5 */
+#define EXTI_EMR_MR6 0x00000040U /*!< Event Mask on line 6 */
+#define EXTI_EMR_MR7 0x00000080U /*!< Event Mask on line 7 */
+#define EXTI_EMR_MR8 0x00000100U /*!< Event Mask on line 8 */
+#define EXTI_EMR_MR9 0x00000200U /*!< Event Mask on line 9 */
+#define EXTI_EMR_MR10 0x00000400U /*!< Event Mask on line 10 */
+#define EXTI_EMR_MR11 0x00000800U /*!< Event Mask on line 11 */
+#define EXTI_EMR_MR12 0x00001000U /*!< Event Mask on line 12 */
+#define EXTI_EMR_MR13 0x00002000U /*!< Event Mask on line 13 */
+#define EXTI_EMR_MR14 0x00004000U /*!< Event Mask on line 14 */
+#define EXTI_EMR_MR15 0x00008000U /*!< Event Mask on line 15 */
+#define EXTI_EMR_MR16 0x00010000U /*!< Event Mask on line 16 */
+#define EXTI_EMR_MR17 0x00020000U /*!< Event Mask on line 17 */
+#define EXTI_EMR_MR18 0x00040000U /*!< Event Mask on line 18 */
+#define EXTI_EMR_MR19 0x00080000U /*!< Event Mask on line 19 */
+#define EXTI_EMR_MR20 0x00100000U /*!< Event Mask on line 20 */
+#define EXTI_EMR_MR21 0x00200000U /*!< Event Mask on line 21 */
+#define EXTI_EMR_MR22 0x00400000U /*!< Event Mask on line 22 */
+
+/****************** Bit definition for EXTI_RTSR register *******************/
+#define EXTI_RTSR_TR0 0x00000001U /*!< Rising trigger event configuration bit of line 0 */
+#define EXTI_RTSR_TR1 0x00000002U /*!< Rising trigger event configuration bit of line 1 */
+#define EXTI_RTSR_TR2 0x00000004U /*!< Rising trigger event configuration bit of line 2 */
+#define EXTI_RTSR_TR3 0x00000008U /*!< Rising trigger event configuration bit of line 3 */
+#define EXTI_RTSR_TR4 0x00000010U /*!< Rising trigger event configuration bit of line 4 */
+#define EXTI_RTSR_TR5 0x00000020U /*!< Rising trigger event configuration bit of line 5 */
+#define EXTI_RTSR_TR6 0x00000040U /*!< Rising trigger event configuration bit of line 6 */
+#define EXTI_RTSR_TR7 0x00000080U /*!< Rising trigger event configuration bit of line 7 */
+#define EXTI_RTSR_TR8 0x00000100U /*!< Rising trigger event configuration bit of line 8 */
+#define EXTI_RTSR_TR9 0x00000200U /*!< Rising trigger event configuration bit of line 9 */
+#define EXTI_RTSR_TR10 0x00000400U /*!< Rising trigger event configuration bit of line 10 */
+#define EXTI_RTSR_TR11 0x00000800U /*!< Rising trigger event configuration bit of line 11 */
+#define EXTI_RTSR_TR12 0x00001000U /*!< Rising trigger event configuration bit of line 12 */
+#define EXTI_RTSR_TR13 0x00002000U /*!< Rising trigger event configuration bit of line 13 */
+#define EXTI_RTSR_TR14 0x00004000U /*!< Rising trigger event configuration bit of line 14 */
+#define EXTI_RTSR_TR15 0x00008000U /*!< Rising trigger event configuration bit of line 15 */
+#define EXTI_RTSR_TR16 0x00010000U /*!< Rising trigger event configuration bit of line 16 */
+#define EXTI_RTSR_TR17 0x00020000U /*!< Rising trigger event configuration bit of line 17 */
+#define EXTI_RTSR_TR18 0x00040000U /*!< Rising trigger event configuration bit of line 18 */
+#define EXTI_RTSR_TR19 0x00080000U /*!< Rising trigger event configuration bit of line 19 */
+#define EXTI_RTSR_TR20 0x00100000U /*!< Rising trigger event configuration bit of line 20 */
+#define EXTI_RTSR_TR21 0x00200000U /*!< Rising trigger event configuration bit of line 21 */
+#define EXTI_RTSR_TR22 0x00400000U /*!< Rising trigger event configuration bit of line 22 */
+
+/****************** Bit definition for EXTI_FTSR register *******************/
+#define EXTI_FTSR_TR0 0x00000001U /*!< Falling trigger event configuration bit of line 0 */
+#define EXTI_FTSR_TR1 0x00000002U /*!< Falling trigger event configuration bit of line 1 */
+#define EXTI_FTSR_TR2 0x00000004U /*!< Falling trigger event configuration bit of line 2 */
+#define EXTI_FTSR_TR3 0x00000008U /*!< Falling trigger event configuration bit of line 3 */
+#define EXTI_FTSR_TR4 0x00000010U /*!< Falling trigger event configuration bit of line 4 */
+#define EXTI_FTSR_TR5 0x00000020U /*!< Falling trigger event configuration bit of line 5 */
+#define EXTI_FTSR_TR6 0x00000040U /*!< Falling trigger event configuration bit of line 6 */
+#define EXTI_FTSR_TR7 0x00000080U /*!< Falling trigger event configuration bit of line 7 */
+#define EXTI_FTSR_TR8 0x00000100U /*!< Falling trigger event configuration bit of line 8 */
+#define EXTI_FTSR_TR9 0x00000200U /*!< Falling trigger event configuration bit of line 9 */
+#define EXTI_FTSR_TR10 0x00000400U /*!< Falling trigger event configuration bit of line 10 */
+#define EXTI_FTSR_TR11 0x00000800U /*!< Falling trigger event configuration bit of line 11 */
+#define EXTI_FTSR_TR12 0x00001000U /*!< Falling trigger event configuration bit of line 12 */
+#define EXTI_FTSR_TR13 0x00002000U /*!< Falling trigger event configuration bit of line 13 */
+#define EXTI_FTSR_TR14 0x00004000U /*!< Falling trigger event configuration bit of line 14 */
+#define EXTI_FTSR_TR15 0x00008000U /*!< Falling trigger event configuration bit of line 15 */
+#define EXTI_FTSR_TR16 0x00010000U /*!< Falling trigger event configuration bit of line 16 */
+#define EXTI_FTSR_TR17 0x00020000U /*!< Falling trigger event configuration bit of line 17 */
+#define EXTI_FTSR_TR18 0x00040000U /*!< Falling trigger event configuration bit of line 18 */
+#define EXTI_FTSR_TR19 0x00080000U /*!< Falling trigger event configuration bit of line 19 */
+#define EXTI_FTSR_TR20 0x00100000U /*!< Falling trigger event configuration bit of line 20 */
+#define EXTI_FTSR_TR21 0x00200000U /*!< Falling trigger event configuration bit of line 21 */
+#define EXTI_FTSR_TR22 0x00400000U /*!< Falling trigger event configuration bit of line 22 */
+
+/****************** Bit definition for EXTI_SWIER register ******************/
+#define EXTI_SWIER_SWIER0 0x00000001U /*!< Software Interrupt on line 0 */
+#define EXTI_SWIER_SWIER1 0x00000002U /*!< Software Interrupt on line 1 */
+#define EXTI_SWIER_SWIER2 0x00000004U /*!< Software Interrupt on line 2 */
+#define EXTI_SWIER_SWIER3 0x00000008U /*!< Software Interrupt on line 3 */
+#define EXTI_SWIER_SWIER4 0x00000010U /*!< Software Interrupt on line 4 */
+#define EXTI_SWIER_SWIER5 0x00000020U /*!< Software Interrupt on line 5 */
+#define EXTI_SWIER_SWIER6 0x00000040U /*!< Software Interrupt on line 6 */
+#define EXTI_SWIER_SWIER7 0x00000080U /*!< Software Interrupt on line 7 */
+#define EXTI_SWIER_SWIER8 0x00000100U /*!< Software Interrupt on line 8 */
+#define EXTI_SWIER_SWIER9 0x00000200U /*!< Software Interrupt on line 9 */
+#define EXTI_SWIER_SWIER10 0x00000400U /*!< Software Interrupt on line 10 */
+#define EXTI_SWIER_SWIER11 0x00000800U /*!< Software Interrupt on line 11 */
+#define EXTI_SWIER_SWIER12 0x00001000U /*!< Software Interrupt on line 12 */
+#define EXTI_SWIER_SWIER13 0x00002000U /*!< Software Interrupt on line 13 */
+#define EXTI_SWIER_SWIER14 0x00004000U /*!< Software Interrupt on line 14 */
+#define EXTI_SWIER_SWIER15 0x00008000U /*!< Software Interrupt on line 15 */
+#define EXTI_SWIER_SWIER16 0x00010000U /*!< Software Interrupt on line 16 */
+#define EXTI_SWIER_SWIER17 0x00020000U /*!< Software Interrupt on line 17 */
+#define EXTI_SWIER_SWIER18 0x00040000U /*!< Software Interrupt on line 18 */
+#define EXTI_SWIER_SWIER19 0x00080000U /*!< Software Interrupt on line 19 */
+#define EXTI_SWIER_SWIER20 0x00100000U /*!< Software Interrupt on line 20 */
+#define EXTI_SWIER_SWIER21 0x00200000U /*!< Software Interrupt on line 21 */
+#define EXTI_SWIER_SWIER22 0x00400000U /*!< Software Interrupt on line 22 */
+
+/******************* Bit definition for EXTI_PR register ********************/
+#define EXTI_PR_PR0 0x00000001U /*!< Pending bit for line 0 */
+#define EXTI_PR_PR1 0x00000002U /*!< Pending bit for line 1 */
+#define EXTI_PR_PR2 0x00000004U /*!< Pending bit for line 2 */
+#define EXTI_PR_PR3 0x00000008U /*!< Pending bit for line 3 */
+#define EXTI_PR_PR4 0x00000010U /*!< Pending bit for line 4 */
+#define EXTI_PR_PR5 0x00000020U /*!< Pending bit for line 5 */
+#define EXTI_PR_PR6 0x00000040U /*!< Pending bit for line 6 */
+#define EXTI_PR_PR7 0x00000080U /*!< Pending bit for line 7 */
+#define EXTI_PR_PR8 0x00000100U /*!< Pending bit for line 8 */
+#define EXTI_PR_PR9 0x00000200U /*!< Pending bit for line 9 */
+#define EXTI_PR_PR10 0x00000400U /*!< Pending bit for line 10 */
+#define EXTI_PR_PR11 0x00000800U /*!< Pending bit for line 11 */
+#define EXTI_PR_PR12 0x00001000U /*!< Pending bit for line 12 */
+#define EXTI_PR_PR13 0x00002000U /*!< Pending bit for line 13 */
+#define EXTI_PR_PR14 0x00004000U /*!< Pending bit for line 14 */
+#define EXTI_PR_PR15 0x00008000U /*!< Pending bit for line 15 */
+#define EXTI_PR_PR16 0x00010000U /*!< Pending bit for line 16 */
+#define EXTI_PR_PR17 0x00020000U /*!< Pending bit for line 17 */
+#define EXTI_PR_PR18 0x00040000U /*!< Pending bit for line 18 */
+#define EXTI_PR_PR19 0x00080000U /*!< Pending bit for line 19 */
+#define EXTI_PR_PR20 0x00100000U /*!< Pending bit for line 20 */
+#define EXTI_PR_PR21 0x00200000U /*!< Pending bit for line 21 */
+#define EXTI_PR_PR22 0x00400000U /*!< Pending bit for line 22 */
+
+/******************************************************************************/
+/* */
+/* FLASH */
+/* */
+/******************************************************************************/
+/******************* Bits definition for FLASH_ACR register *****************/
+#define FLASH_ACR_LATENCY 0x0000000FU
+#define FLASH_ACR_LATENCY_0WS 0x00000000U
+#define FLASH_ACR_LATENCY_1WS 0x00000001U
+#define FLASH_ACR_LATENCY_2WS 0x00000002U
+#define FLASH_ACR_LATENCY_3WS 0x00000003U
+#define FLASH_ACR_LATENCY_4WS 0x00000004U
+#define FLASH_ACR_LATENCY_5WS 0x00000005U
+#define FLASH_ACR_LATENCY_6WS 0x00000006U
+#define FLASH_ACR_LATENCY_7WS 0x00000007U
+
+#define FLASH_ACR_PRFTEN 0x00000100U
+#define FLASH_ACR_ICEN 0x00000200U
+#define FLASH_ACR_DCEN 0x00000400U
+#define FLASH_ACR_ICRST 0x00000800U
+#define FLASH_ACR_DCRST 0x00001000U
+#define FLASH_ACR_BYTE0_ADDRESS 0x40023C00U
+#define FLASH_ACR_BYTE2_ADDRESS 0x40023C03U
+
+/******************* Bits definition for FLASH_SR register ******************/
+#define FLASH_SR_EOP 0x00000001U
+#define FLASH_SR_SOP 0x00000002U
+#define FLASH_SR_WRPERR 0x00000010U
+#define FLASH_SR_PGAERR 0x00000020U
+#define FLASH_SR_PGPERR 0x00000040U
+#define FLASH_SR_PGSERR 0x00000080U
+#define FLASH_SR_BSY 0x00010000U
+
+/******************* Bits definition for FLASH_CR register ******************/
+#define FLASH_CR_PG 0x00000001U
+#define FLASH_CR_SER 0x00000002U
+#define FLASH_CR_MER 0x00000004U
+#define FLASH_CR_SNB 0x000000F8U
+#define FLASH_CR_SNB_0 0x00000008U
+#define FLASH_CR_SNB_1 0x00000010U
+#define FLASH_CR_SNB_2 0x00000020U
+#define FLASH_CR_SNB_3 0x00000040U
+#define FLASH_CR_SNB_4 0x00000080U
+#define FLASH_CR_PSIZE 0x00000300U
+#define FLASH_CR_PSIZE_0 0x00000100U
+#define FLASH_CR_PSIZE_1 0x00000200U
+#define FLASH_CR_STRT 0x00010000U
+#define FLASH_CR_EOPIE 0x01000000U
+#define FLASH_CR_LOCK 0x80000000U
+
+/******************* Bits definition for FLASH_OPTCR register ***************/
+#define FLASH_OPTCR_OPTLOCK 0x00000001U
+#define FLASH_OPTCR_OPTSTRT 0x00000002U
+#define FLASH_OPTCR_BOR_LEV_0 0x00000004U
+#define FLASH_OPTCR_BOR_LEV_1 0x00000008U
+#define FLASH_OPTCR_BOR_LEV 0x0000000CU
+
+#define FLASH_OPTCR_WDG_SW 0x00000020U
+#define FLASH_OPTCR_nRST_STOP 0x00000040U
+#define FLASH_OPTCR_nRST_STDBY 0x00000080U
+#define FLASH_OPTCR_RDP 0x0000FF00U
+#define FLASH_OPTCR_RDP_0 0x00000100U
+#define FLASH_OPTCR_RDP_1 0x00000200U
+#define FLASH_OPTCR_RDP_2 0x00000400U
+#define FLASH_OPTCR_RDP_3 0x00000800U
+#define FLASH_OPTCR_RDP_4 0x00001000U
+#define FLASH_OPTCR_RDP_5 0x00002000U
+#define FLASH_OPTCR_RDP_6 0x00004000U
+#define FLASH_OPTCR_RDP_7 0x00008000U
+#define FLASH_OPTCR_nWRP 0x0FFF0000U
+#define FLASH_OPTCR_nWRP_0 0x00010000U
+#define FLASH_OPTCR_nWRP_1 0x00020000U
+#define FLASH_OPTCR_nWRP_2 0x00040000U
+#define FLASH_OPTCR_nWRP_3 0x00080000U
+#define FLASH_OPTCR_nWRP_4 0x00100000U
+#define FLASH_OPTCR_nWRP_5 0x00200000U
+#define FLASH_OPTCR_nWRP_6 0x00400000U
+#define FLASH_OPTCR_nWRP_7 0x00800000U
+#define FLASH_OPTCR_nWRP_8 0x01000000U
+#define FLASH_OPTCR_nWRP_9 0x02000000U
+#define FLASH_OPTCR_nWRP_10 0x04000000U
+#define FLASH_OPTCR_nWRP_11 0x08000000U
+
+/****************** Bits definition for FLASH_OPTCR1 register ***************/
+#define FLASH_OPTCR1_nWRP 0x0FFF0000U
+#define FLASH_OPTCR1_nWRP_0 0x00010000U
+#define FLASH_OPTCR1_nWRP_1 0x00020000U
+#define FLASH_OPTCR1_nWRP_2 0x00040000U
+#define FLASH_OPTCR1_nWRP_3 0x00080000U
+#define FLASH_OPTCR1_nWRP_4 0x00100000U
+#define FLASH_OPTCR1_nWRP_5 0x00200000U
+#define FLASH_OPTCR1_nWRP_6 0x00400000U
+#define FLASH_OPTCR1_nWRP_7 0x00800000U
+#define FLASH_OPTCR1_nWRP_8 0x01000000U
+#define FLASH_OPTCR1_nWRP_9 0x02000000U
+#define FLASH_OPTCR1_nWRP_10 0x04000000U
+#define FLASH_OPTCR1_nWRP_11 0x08000000U
+
+/******************************************************************************/
+/* */
+/* Flexible Static Memory Controller */
+/* */
+/******************************************************************************/
+/****************** Bit definition for FSMC_BCR1 register *******************/
+#define FSMC_BCR1_MBKEN 0x00000001U /*!<Memory bank enable bit */
+#define FSMC_BCR1_MUXEN 0x00000002U /*!<Address/data multiplexing enable bit */
+
+#define FSMC_BCR1_MTYP 0x0000000CU /*!<MTYP[1:0] bits (Memory type) */
+#define FSMC_BCR1_MTYP_0 0x00000004U /*!<Bit 0 */
+#define FSMC_BCR1_MTYP_1 0x00000008U /*!<Bit 1 */
+
+#define FSMC_BCR1_MWID 0x00000030U /*!<MWID[1:0] bits (Memory data bus width) */
+#define FSMC_BCR1_MWID_0 0x00000010U /*!<Bit 0 */
+#define FSMC_BCR1_MWID_1 0x00000020U /*!<Bit 1 */
+
+#define FSMC_BCR1_FACCEN 0x00000040U /*!<Flash access enable */
+#define FSMC_BCR1_BURSTEN 0x00000100U /*!<Burst enable bit */
+#define FSMC_BCR1_WAITPOL 0x00000200U /*!<Wait signal polarity bit */
+#define FSMC_BCR1_WAITCFG 0x00000800U /*!<Wait timing configuration */
+#define FSMC_BCR1_WREN 0x00001000U /*!<Write enable bit */
+#define FSMC_BCR1_WAITEN 0x00002000U /*!<Wait enable bit */
+#define FSMC_BCR1_EXTMOD 0x00004000U /*!<Extended mode enable */
+#define FSMC_BCR1_ASYNCWAIT 0x00008000U /*!<Asynchronous wait */
+#define FSMC_BCR1_CPSIZE 0x00070000U /*!<CRAM page size */
+#define FSMC_BCR1_CPSIZE_0 0x00010000U /*!<Bit 0 */
+#define FSMC_BCR1_CPSIZE_1 0x00020000U /*!<Bit 1 */
+#define FSMC_BCR1_CPSIZE_2 0x00040000U /*!<Bit 2 */
+#define FSMC_BCR1_CBURSTRW 0x00080000U /*!<Write burst enable */
+#define FSMC_BCR1_CCLKEN 0x00100000U /*!<Continous clock enable */
+#define FSMC_BCR1_WFDIS 0x00200000U /*!<Write FIFO Disable */
+
+/****************** Bit definition for FSMC_BCR2 register *******************/
+#define FSMC_BCR2_MBKEN 0x00000001U /*!<Memory bank enable bit */
+#define FSMC_BCR2_MUXEN 0x00000002U /*!<Address/data multiplexing enable bit */
+
+#define FSMC_BCR2_MTYP 0x0000000CU /*!<MTYP[1:0] bits (Memory type) */
+#define FSMC_BCR2_MTYP_0 0x00000004U /*!<Bit 0 */
+#define FSMC_BCR2_MTYP_1 0x00000008U /*!<Bit 1 */
+
+#define FSMC_BCR2_MWID 0x00000030U /*!<MWID[1:0] bits (Memory data bus width) */
+#define FSMC_BCR2_MWID_0 0x00000010U /*!<Bit 0 */
+#define FSMC_BCR2_MWID_1 0x00000020U /*!<Bit 1 */
+
+#define FSMC_BCR2_FACCEN 0x00000040U /*!<Flash access enable */
+#define FSMC_BCR2_BURSTEN 0x00000100U /*!<Burst enable bit */
+#define FSMC_BCR2_WAITPOL 0x00000200U /*!<Wait signal polarity bit */
+#define FSMC_BCR2_WAITCFG 0x00000800U /*!<Wait timing configuration */
+#define FSMC_BCR2_WREN 0x00001000U /*!<Write enable bit */
+#define FSMC_BCR2_WAITEN 0x00002000U /*!<Wait enable bit */
+#define FSMC_BCR2_EXTMOD 0x00004000U /*!<Extended mode enable */
+#define FSMC_BCR2_CPSIZE 0x00070000U /*!<CRAM page size */
+#define FSMC_BCR2_CPSIZE_0 0x00010000U /*!<Bit 0 */
+#define FSMC_BCR2_CPSIZE_1 0x00020000U /*!<Bit 1 */
+#define FSMC_BCR2_CPSIZE_2 0x00040000U /*!<Bit 2 */
+#define FSMC_BCR2_ASYNCWAIT 0x00008000U /*!<Asynchronous wait */
+#define FSMC_BCR2_CBURSTRW 0x00080000U /*!<Write burst enable */
+
+/****************** Bit definition for FSMC_BCR3 register *******************/
+#define FSMC_BCR3_MBKEN 0x00000001U /*!<Memory bank enable bit */
+#define FSMC_BCR3_MUXEN 0x00000002U /*!<Address/data multiplexing enable bit */
+
+#define FSMC_BCR3_MTYP 0x0000000CU /*!<MTYP[1:0] bits (Memory type) */
+#define FSMC_BCR3_MTYP_0 0x00000004U /*!<Bit 0 */
+#define FSMC_BCR3_MTYP_1 0x00000008U /*!<Bit 1 */
+
+#define FSMC_BCR3_MWID 0x00000030U /*!<MWID[1:0] bits (Memory data bus width) */
+#define FSMC_BCR3_MWID_0 0x00000010U /*!<Bit 0 */
+#define FSMC_BCR3_MWID_1 0x00000020U /*!<Bit 1 */
+
+#define FSMC_BCR3_FACCEN 0x00000040U /*!<Flash access enable */
+#define FSMC_BCR3_BURSTEN 0x00000100U /*!<Burst enable bit */
+#define FSMC_BCR3_WAITPOL 0x00000200U /*!<Wait signal polarity bit */
+#define FSMC_BCR3_WAITCFG 0x00000800U /*!<Wait timing configuration */
+#define FSMC_BCR3_WREN 0x00001000U /*!<Write enable bit */
+#define FSMC_BCR3_WAITEN 0x00002000U /*!<Wait enable bit */
+#define FSMC_BCR3_EXTMOD 0x00004000U /*!<Extended mode enable */
+#define FSMC_BCR3_CPSIZE 0x00070000U /*!<CRAM page size */
+#define FSMC_BCR3_CPSIZE_0 0x00010000U /*!<Bit 0 */
+#define FSMC_BCR3_CPSIZE_1 0x00020000U /*!<Bit 1 */
+#define FSMC_BCR3_CPSIZE_2 0x00040000U /*!<Bit 2 */
+#define FSMC_BCR3_ASYNCWAIT 0x00008000U /*!<Asynchronous wait */
+#define FSMC_BCR3_CBURSTRW 0x00080000U /*!<Write burst enable */
+
+/****************** Bit definition for FSMC_BCR4 register *******************/
+#define FSMC_BCR4_MBKEN 0x00000001U /*!<Memory bank enable bit */
+#define FSMC_BCR4_MUXEN 0x00000002U /*!<Address/data multiplexing enable bit */
+
+#define FSMC_BCR4_MTYP 0x0000000CU /*!<MTYP[1:0] bits (Memory type) */
+#define FSMC_BCR4_MTYP_0 0x00000004U /*!<Bit 0 */
+#define FSMC_BCR4_MTYP_1 0x00000008U /*!<Bit 1 */
+
+#define FSMC_BCR4_MWID 0x00000030U /*!<MWID[1:0] bits (Memory data bus width) */
+#define FSMC_BCR4_MWID_0 0x00000010U /*!<Bit 0 */
+#define FSMC_BCR4_MWID_1 0x00000020U /*!<Bit 1 */
+
+#define FSMC_BCR4_FACCEN 0x00000040U /*!<Flash access enable */
+#define FSMC_BCR4_BURSTEN 0x00000100U /*!<Burst enable bit */
+#define FSMC_BCR4_WAITPOL 0x00000200U /*!<Wait signal polarity bit */
+#define FSMC_BCR4_WAITCFG 0x00000800U /*!<Wait timing configuration */
+#define FSMC_BCR4_WREN 0x00001000U /*!<Write enable bit */
+#define FSMC_BCR4_WAITEN 0x00002000U /*!<Wait enable bit */
+#define FSMC_BCR4_EXTMOD 0x00004000U /*!<Extended mode enable */
+#define FSMC_BCR4_CPSIZE 0x00070000U /*!<CRAM page size */
+#define FSMC_BCR4_CPSIZE_0 0x00010000U /*!<Bit 0 */
+#define FSMC_BCR4_CPSIZE_1 0x00020000U /*!<Bit 1 */
+#define FSMC_BCR4_CPSIZE_2 0x00040000U /*!<Bit 2 */
+#define FSMC_BCR4_ASYNCWAIT 0x00008000U /*!<Asynchronous wait */
+#define FSMC_BCR4_CBURSTRW 0x00080000U /*!<Write burst enable */
+
+/****************** Bit definition for FSMC_BTR1 register ******************/
+#define FSMC_BTR1_ADDSET 0x0000000FU /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FSMC_BTR1_ADDSET_0 0x00000001U /*!<Bit 0 */
+#define FSMC_BTR1_ADDSET_1 0x00000002U /*!<Bit 1 */
+#define FSMC_BTR1_ADDSET_2 0x00000004U /*!<Bit 2 */
+#define FSMC_BTR1_ADDSET_3 0x00000008U /*!<Bit 3 */
+
+#define FSMC_BTR1_ADDHLD 0x000000F0U /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FSMC_BTR1_ADDHLD_0 0x00000010U /*!<Bit 0 */
+#define FSMC_BTR1_ADDHLD_1 0x00000020U /*!<Bit 1 */
+#define FSMC_BTR1_ADDHLD_2 0x00000040U /*!<Bit 2 */
+#define FSMC_BTR1_ADDHLD_3 0x00000080U /*!<Bit 3 */
+
+#define FSMC_BTR1_DATAST 0x0000FF00U /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FSMC_BTR1_DATAST_0 0x00000100U /*!<Bit 0 */
+#define FSMC_BTR1_DATAST_1 0x00000200U /*!<Bit 1 */
+#define FSMC_BTR1_DATAST_2 0x00000400U /*!<Bit 2 */
+#define FSMC_BTR1_DATAST_3 0x00000800U /*!<Bit 3 */
+#define FSMC_BTR1_DATAST_4 0x00001000U /*!<Bit 4 */
+#define FSMC_BTR1_DATAST_5 0x00002000U /*!<Bit 5 */
+#define FSMC_BTR1_DATAST_6 0x00004000U /*!<Bit 6 */
+#define FSMC_BTR1_DATAST_7 0x00008000U /*!<Bit 7 */
+
+#define FSMC_BTR1_BUSTURN 0x000F0000U /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define FSMC_BTR1_BUSTURN_0 0x00010000U /*!<Bit 0 */
+#define FSMC_BTR1_BUSTURN_1 0x00020000U /*!<Bit 1 */
+#define FSMC_BTR1_BUSTURN_2 0x00040000U /*!<Bit 2 */
+#define FSMC_BTR1_BUSTURN_3 0x00080000U /*!<Bit 3 */
+
+#define FSMC_BTR1_CLKDIV 0x00F00000U /*!<CLKDIV[3:0] bits (Clock divide ratio) */
+#define FSMC_BTR1_CLKDIV_0 0x00100000U /*!<Bit 0 */
+#define FSMC_BTR1_CLKDIV_1 0x00200000U /*!<Bit 1 */
+#define FSMC_BTR1_CLKDIV_2 0x00400000U /*!<Bit 2 */
+#define FSMC_BTR1_CLKDIV_3 0x00800000U /*!<Bit 3 */
+
+#define FSMC_BTR1_DATLAT 0x0F000000U /*!<DATLA[3:0] bits (Data latency) */
+#define FSMC_BTR1_DATLAT_0 0x01000000U /*!<Bit 0 */
+#define FSMC_BTR1_DATLAT_1 0x02000000U /*!<Bit 1 */
+#define FSMC_BTR1_DATLAT_2 0x04000000U /*!<Bit 2 */
+#define FSMC_BTR1_DATLAT_3 0x08000000U /*!<Bit 3 */
+
+#define FSMC_BTR1_ACCMOD 0x30000000U /*!<ACCMOD[1:0] bits (Access mode) */
+#define FSMC_BTR1_ACCMOD_0 0x10000000U /*!<Bit 0 */
+#define FSMC_BTR1_ACCMOD_1 0x20000000U /*!<Bit 1 */
+
+/****************** Bit definition for FSMC_BTR2 register *******************/
+#define FSMC_BTR2_ADDSET 0x0000000FU /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FSMC_BTR2_ADDSET_0 0x00000001U /*!<Bit 0 */
+#define FSMC_BTR2_ADDSET_1 0x00000002U /*!<Bit 1 */
+#define FSMC_BTR2_ADDSET_2 0x00000004U /*!<Bit 2 */
+#define FSMC_BTR2_ADDSET_3 0x00000008U /*!<Bit 3 */
+
+#define FSMC_BTR2_ADDHLD 0x000000F0U /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FSMC_BTR2_ADDHLD_0 0x00000010U /*!<Bit 0 */
+#define FSMC_BTR2_ADDHLD_1 0x00000020U /*!<Bit 1 */
+#define FSMC_BTR2_ADDHLD_2 0x00000040U /*!<Bit 2 */
+#define FSMC_BTR2_ADDHLD_3 0x00000080U /*!<Bit 3 */
+
+#define FSMC_BTR2_DATAST 0x0000FF00U /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FSMC_BTR2_DATAST_0 0x00000100U /*!<Bit 0 */
+#define FSMC_BTR2_DATAST_1 0x00000200U /*!<Bit 1 */
+#define FSMC_BTR2_DATAST_2 0x00000400U /*!<Bit 2 */
+#define FSMC_BTR2_DATAST_3 0x00000800U /*!<Bit 3 */
+#define FSMC_BTR2_DATAST_4 0x00001000U /*!<Bit 4 */
+#define FSMC_BTR2_DATAST_5 0x00002000U /*!<Bit 5 */
+#define FSMC_BTR2_DATAST_6 0x00004000U /*!<Bit 6 */
+#define FSMC_BTR2_DATAST_7 0x00008000U /*!<Bit 7 */
+
+#define FSMC_BTR2_BUSTURN 0x000F0000U /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define FSMC_BTR2_BUSTURN_0 0x00010000U /*!<Bit 0 */
+#define FSMC_BTR2_BUSTURN_1 0x00020000U /*!<Bit 1 */
+#define FSMC_BTR2_BUSTURN_2 0x00040000U /*!<Bit 2 */
+#define FSMC_BTR2_BUSTURN_3 0x00080000U /*!<Bit 3 */
+
+#define FSMC_BTR2_CLKDIV 0x00F00000U /*!<CLKDIV[3:0] bits (Clock divide ratio) */
+#define FSMC_BTR2_CLKDIV_0 0x00100000U /*!<Bit 0 */
+#define FSMC_BTR2_CLKDIV_1 0x00200000U /*!<Bit 1 */
+#define FSMC_BTR2_CLKDIV_2 0x00400000U /*!<Bit 2 */
+#define FSMC_BTR2_CLKDIV_3 0x00800000U /*!<Bit 3 */
+
+#define FSMC_BTR2_DATLAT 0x0F000000U /*!<DATLA[3:0] bits (Data latency) */
+#define FSMC_BTR2_DATLAT_0 0x01000000U /*!<Bit 0 */
+#define FSMC_BTR2_DATLAT_1 0x02000000U /*!<Bit 1 */
+#define FSMC_BTR2_DATLAT_2 0x04000000U /*!<Bit 2 */
+#define FSMC_BTR2_DATLAT_3 0x08000000U /*!<Bit 3 */
+
+#define FSMC_BTR2_ACCMOD 0x30000000U /*!<ACCMOD[1:0] bits (Access mode) */
+#define FSMC_BTR2_ACCMOD_0 0x10000000U /*!<Bit 0 */
+#define FSMC_BTR2_ACCMOD_1 0x20000000U /*!<Bit 1 */
+
+/******************* Bit definition for FSMC_BTR3 register *******************/
+#define FSMC_BTR3_ADDSET 0x0000000FU /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FSMC_BTR3_ADDSET_0 0x00000001U /*!<Bit 0 */
+#define FSMC_BTR3_ADDSET_1 0x00000002U /*!<Bit 1 */
+#define FSMC_BTR3_ADDSET_2 0x00000004U /*!<Bit 2 */
+#define FSMC_BTR3_ADDSET_3 0x00000008U /*!<Bit 3 */
+
+#define FSMC_BTR3_ADDHLD 0x000000F0U /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FSMC_BTR3_ADDHLD_0 0x00000010U /*!<Bit 0 */
+#define FSMC_BTR3_ADDHLD_1 0x00000020U /*!<Bit 1 */
+#define FSMC_BTR3_ADDHLD_2 0x00000040U /*!<Bit 2 */
+#define FSMC_BTR3_ADDHLD_3 0x00000080U /*!<Bit 3 */
+
+#define FSMC_BTR3_DATAST 0x0000FF00U /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FSMC_BTR3_DATAST_0 0x00000100U /*!<Bit 0 */
+#define FSMC_BTR3_DATAST_1 0x00000200U /*!<Bit 1 */
+#define FSMC_BTR3_DATAST_2 0x00000400U /*!<Bit 2 */
+#define FSMC_BTR3_DATAST_3 0x00000800U /*!<Bit 3 */
+#define FSMC_BTR3_DATAST_4 0x00001000U /*!<Bit 4 */
+#define FSMC_BTR3_DATAST_5 0x00002000U /*!<Bit 5 */
+#define FSMC_BTR3_DATAST_6 0x00004000U /*!<Bit 6 */
+#define FSMC_BTR3_DATAST_7 0x00008000U /*!<Bit 7 */
+
+#define FSMC_BTR3_BUSTURN 0x000F0000U /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define FSMC_BTR3_BUSTURN_0 0x00010000U /*!<Bit 0 */
+#define FSMC_BTR3_BUSTURN_1 0x00020000U /*!<Bit 1 */
+#define FSMC_BTR3_BUSTURN_2 0x00040000U /*!<Bit 2 */
+#define FSMC_BTR3_BUSTURN_3 0x00080000U /*!<Bit 3 */
+
+#define FSMC_BTR3_CLKDIV 0x00F00000U /*!<CLKDIV[3:0] bits (Clock divide ratio) */
+#define FSMC_BTR3_CLKDIV_0 0x00100000U /*!<Bit 0 */
+#define FSMC_BTR3_CLKDIV_1 0x00200000U /*!<Bit 1 */
+#define FSMC_BTR3_CLKDIV_2 0x00400000U /*!<Bit 2 */
+#define FSMC_BTR3_CLKDIV_3 0x00800000U /*!<Bit 3 */
+
+#define FSMC_BTR3_DATLAT 0x0F000000U /*!<DATLA[3:0] bits (Data latency) */
+#define FSMC_BTR3_DATLAT_0 0x01000000U /*!<Bit 0 */
+#define FSMC_BTR3_DATLAT_1 0x02000000U /*!<Bit 1 */
+#define FSMC_BTR3_DATLAT_2 0x04000000U /*!<Bit 2 */
+#define FSMC_BTR3_DATLAT_3 0x08000000U /*!<Bit 3 */
+
+#define FSMC_BTR3_ACCMOD 0x30000000U /*!<ACCMOD[1:0] bits (Access mode) */
+#define FSMC_BTR3_ACCMOD_0 0x10000000U /*!<Bit 0 */
+#define FSMC_BTR3_ACCMOD_1 0x20000000U /*!<Bit 1 */
+
+/****************** Bit definition for FSMC_BTR4 register *******************/
+#define FSMC_BTR4_ADDSET 0x0000000FU /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FSMC_BTR4_ADDSET_0 0x00000001U /*!<Bit 0 */
+#define FSMC_BTR4_ADDSET_1 0x00000002U /*!<Bit 1 */
+#define FSMC_BTR4_ADDSET_2 0x00000004U /*!<Bit 2 */
+#define FSMC_BTR4_ADDSET_3 0x00000008U /*!<Bit 3 */
+
+#define FSMC_BTR4_ADDHLD 0x000000F0U /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FSMC_BTR4_ADDHLD_0 0x00000010U /*!<Bit 0 */
+#define FSMC_BTR4_ADDHLD_1 0x00000020U /*!<Bit 1 */
+#define FSMC_BTR4_ADDHLD_2 0x00000040U /*!<Bit 2 */
+#define FSMC_BTR4_ADDHLD_3 0x00000080U /*!<Bit 3 */
+
+#define FSMC_BTR4_DATAST 0x0000FF00U /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FSMC_BTR4_DATAST_0 0x00000100U /*!<Bit 0 */
+#define FSMC_BTR4_DATAST_1 0x00000200U /*!<Bit 1 */
+#define FSMC_BTR4_DATAST_2 0x00000400U /*!<Bit 2 */
+#define FSMC_BTR4_DATAST_3 0x00000800U /*!<Bit 3 */
+#define FSMC_BTR4_DATAST_4 0x00001000U /*!<Bit 4 */
+#define FSMC_BTR4_DATAST_5 0x00002000U /*!<Bit 5 */
+#define FSMC_BTR4_DATAST_6 0x00004000U /*!<Bit 6 */
+#define FSMC_BTR4_DATAST_7 0x00008000U /*!<Bit 7 */
+
+#define FSMC_BTR4_BUSTURN 0x000F0000U /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define FSMC_BTR4_BUSTURN_0 0x00010000U /*!<Bit 0 */
+#define FSMC_BTR4_BUSTURN_1 0x00020000U /*!<Bit 1 */
+#define FSMC_BTR4_BUSTURN_2 0x00040000U /*!<Bit 2 */
+#define FSMC_BTR4_BUSTURN_3 0x00080000U /*!<Bit 3 */
+
+#define FSMC_BTR4_CLKDIV 0x00F00000U /*!<CLKDIV[3:0] bits (Clock divide ratio) */
+#define FSMC_BTR4_CLKDIV_0 0x00100000U /*!<Bit 0 */
+#define FSMC_BTR4_CLKDIV_1 0x00200000U /*!<Bit 1 */
+#define FSMC_BTR4_CLKDIV_2 0x00400000U /*!<Bit 2 */
+#define FSMC_BTR4_CLKDIV_3 0x00800000U /*!<Bit 3 */
+
+#define FSMC_BTR4_DATLAT 0x0F000000U /*!<DATLA[3:0] bits (Data latency) */
+#define FSMC_BTR4_DATLAT_0 0x01000000U /*!<Bit 0 */
+#define FSMC_BTR4_DATLAT_1 0x02000000U /*!<Bit 1 */
+#define FSMC_BTR4_DATLAT_2 0x04000000U /*!<Bit 2 */
+#define FSMC_BTR4_DATLAT_3 0x08000000U /*!<Bit 3 */
+
+#define FSMC_BTR4_ACCMOD 0x30000000U /*!<ACCMOD[1:0] bits (Access mode) */
+#define FSMC_BTR4_ACCMOD_0 0x10000000U /*!<Bit 0 */
+#define FSMC_BTR4_ACCMOD_1 0x20000000U /*!<Bit 1 */
+
+/****************** Bit definition for FSMC_BWTR1 register ******************/
+#define FSMC_BWTR1_ADDSET 0x0000000FU /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FSMC_BWTR1_ADDSET_0 0x00000001U /*!<Bit 0 */
+#define FSMC_BWTR1_ADDSET_1 0x00000002U /*!<Bit 1 */
+#define FSMC_BWTR1_ADDSET_2 0x00000004U /*!<Bit 2 */
+#define FSMC_BWTR1_ADDSET_3 0x00000008U /*!<Bit 3 */
+
+#define FSMC_BWTR1_ADDHLD 0x000000F0U /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FSMC_BWTR1_ADDHLD_0 0x00000010U /*!<Bit 0 */
+#define FSMC_BWTR1_ADDHLD_1 0x00000020U /*!<Bit 1 */
+#define FSMC_BWTR1_ADDHLD_2 0x00000040U /*!<Bit 2 */
+#define FSMC_BWTR1_ADDHLD_3 0x00000080U /*!<Bit 3 */
+
+#define FSMC_BWTR1_DATAST 0x0000FF00U /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FSMC_BWTR1_DATAST_0 0x00000100U /*!<Bit 0 */
+#define FSMC_BWTR1_DATAST_1 0x00000200U /*!<Bit 1 */
+#define FSMC_BWTR1_DATAST_2 0x00000400U /*!<Bit 2 */
+#define FSMC_BWTR1_DATAST_3 0x00000800U /*!<Bit 3 */
+#define FSMC_BWTR1_DATAST_4 0x00001000U /*!<Bit 4 */
+#define FSMC_BWTR1_DATAST_5 0x00002000U /*!<Bit 5 */
+#define FSMC_BWTR1_DATAST_6 0x00004000U /*!<Bit 6 */
+#define FSMC_BWTR1_DATAST_7 0x00008000U /*!<Bit 7 */
+
+#define FSMC_BWTR1_BUSTURN 0x000F0000U /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
+#define FSMC_BWTR1_BUSTURN_0 0x00010000U /*!<Bit 0 */
+#define FSMC_BWTR1_BUSTURN_1 0x00020000U /*!<Bit 1 */
+#define FSMC_BWTR1_BUSTURN_2 0x00040000U /*!<Bit 2 */
+#define FSMC_BWTR1_BUSTURN_3 0x00080000U /*!<Bit 3 */
+
+#define FSMC_BWTR1_ACCMOD 0x30000000U /*!<ACCMOD[1:0] bits (Access mode) */
+#define FSMC_BWTR1_ACCMOD_0 0x10000000U /*!<Bit 0 */
+#define FSMC_BWTR1_ACCMOD_1 0x20000000U /*!<Bit 1 */
+
+/****************** Bit definition for FSMC_BWTR2 register ******************/
+#define FSMC_BWTR2_ADDSET 0x0000000FU /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FSMC_BWTR2_ADDSET_0 0x00000001U /*!<Bit 0 */
+#define FSMC_BWTR2_ADDSET_1 0x00000002U /*!<Bit 1 */
+#define FSMC_BWTR2_ADDSET_2 0x00000004U /*!<Bit 2 */
+#define FSMC_BWTR2_ADDSET_3 0x00000008U /*!<Bit 3 */
+
+#define FSMC_BWTR2_ADDHLD 0x000000F0U /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FSMC_BWTR2_ADDHLD_0 0x00000010U /*!<Bit 0 */
+#define FSMC_BWTR2_ADDHLD_1 0x00000020U /*!<Bit 1 */
+#define FSMC_BWTR2_ADDHLD_2 0x00000040U /*!<Bit 2 */
+#define FSMC_BWTR2_ADDHLD_3 0x00000080U /*!<Bit 3 */
+
+#define FSMC_BWTR2_DATAST 0x0000FF00U /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FSMC_BWTR2_DATAST_0 0x00000100U /*!<Bit 0 */
+#define FSMC_BWTR2_DATAST_1 0x00000200U /*!<Bit 1 */
+#define FSMC_BWTR2_DATAST_2 0x00000400U /*!<Bit 2 */
+#define FSMC_BWTR2_DATAST_3 0x00000800U /*!<Bit 3 */
+#define FSMC_BWTR2_DATAST_4 0x00001000U /*!<Bit 4 */
+#define FSMC_BWTR2_DATAST_5 0x00002000U /*!<Bit 5 */
+#define FSMC_BWTR2_DATAST_6 0x00004000U /*!<Bit 6 */
+#define FSMC_BWTR2_DATAST_7 0x00008000U /*!<Bit 7 */
+
+#define FSMC_BWTR2_BUSTURN 0x000F0000U /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
+#define FSMC_BWTR2_BUSTURN_0 0x00010000U /*!<Bit 0 */
+#define FSMC_BWTR2_BUSTURN_1 0x00020000U /*!<Bit 1 */
+#define FSMC_BWTR2_BUSTURN_2 0x00040000U /*!<Bit 2 */
+#define FSMC_BWTR2_BUSTURN_3 0x00080000U /*!<Bit 3 */
+
+#define FSMC_BWTR2_ACCMOD 0x30000000U /*!<ACCMOD[1:0] bits (Access mode) */
+#define FSMC_BWTR2_ACCMOD_0 0x10000000U /*!<Bit 0 */
+#define FSMC_BWTR2_ACCMOD_1 0x20000000U /*!<Bit 1 */
+
+/****************** Bit definition for FSMC_BWTR3 register ******************/
+#define FSMC_BWTR3_ADDSET 0x0000000FU /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FSMC_BWTR3_ADDSET_0 0x00000001U /*!<Bit 0 */
+#define FSMC_BWTR3_ADDSET_1 0x00000002U /*!<Bit 1 */
+#define FSMC_BWTR3_ADDSET_2 0x00000004U /*!<Bit 2 */
+#define FSMC_BWTR3_ADDSET_3 0x00000008U /*!<Bit 3 */
+
+#define FSMC_BWTR3_ADDHLD 0x000000F0U /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FSMC_BWTR3_ADDHLD_0 0x00000010U /*!<Bit 0 */
+#define FSMC_BWTR3_ADDHLD_1 0x00000020U /*!<Bit 1 */
+#define FSMC_BWTR3_ADDHLD_2 0x00000040U /*!<Bit 2 */
+#define FSMC_BWTR3_ADDHLD_3 0x00000080U /*!<Bit 3 */
+
+#define FSMC_BWTR3_DATAST 0x0000FF00U /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FSMC_BWTR3_DATAST_0 0x00000100U /*!<Bit 0 */
+#define FSMC_BWTR3_DATAST_1 0x00000200U /*!<Bit 1 */
+#define FSMC_BWTR3_DATAST_2 0x00000400U /*!<Bit 2 */
+#define FSMC_BWTR3_DATAST_3 0x00000800U /*!<Bit 3 */
+#define FSMC_BWTR3_DATAST_4 0x00001000U /*!<Bit 4 */
+#define FSMC_BWTR3_DATAST_5 0x00002000U /*!<Bit 5 */
+#define FSMC_BWTR3_DATAST_6 0x00004000U /*!<Bit 6 */
+#define FSMC_BWTR3_DATAST_7 0x00008000U /*!<Bit 7 */
+
+#define FSMC_BWTR3_BUSTURN 0x000F0000U /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
+#define FSMC_BWTR3_BUSTURN_0 0x00010000U /*!<Bit 0 */
+#define FSMC_BWTR3_BUSTURN_1 0x00020000U /*!<Bit 1 */
+#define FSMC_BWTR3_BUSTURN_2 0x00040000U /*!<Bit 2 */
+#define FSMC_BWTR3_BUSTURN_3 0x00080000U /*!<Bit 3 */
+
+#define FSMC_BWTR3_ACCMOD 0x30000000U /*!<ACCMOD[1:0] bits (Access mode) */
+#define FSMC_BWTR3_ACCMOD_0 0x10000000U /*!<Bit 0 */
+#define FSMC_BWTR3_ACCMOD_1 0x20000000U /*!<Bit 1 */
+
+/****************** Bit definition for FSMC_BWTR4 register ******************/
+#define FSMC_BWTR4_ADDSET 0x0000000FU /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FSMC_BWTR4_ADDSET_0 0x00000001U /*!<Bit 0 */
+#define FSMC_BWTR4_ADDSET_1 0x00000002U /*!<Bit 1 */
+#define FSMC_BWTR4_ADDSET_2 0x00000004U /*!<Bit 2 */
+#define FSMC_BWTR4_ADDSET_3 0x00000008U /*!<Bit 3 */
+
+#define FSMC_BWTR4_ADDHLD 0x000000F0U /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FSMC_BWTR4_ADDHLD_0 0x00000010U /*!<Bit 0 */
+#define FSMC_BWTR4_ADDHLD_1 0x00000020U /*!<Bit 1 */
+#define FSMC_BWTR4_ADDHLD_2 0x00000040U /*!<Bit 2 */
+#define FSMC_BWTR4_ADDHLD_3 0x00000080U /*!<Bit 3 */
+
+#define FSMC_BWTR4_DATAST 0x0000FF00U /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FSMC_BWTR4_DATAST_0 0x00000100U /*!<Bit 0 */
+#define FSMC_BWTR4_DATAST_1 0x00000200U /*!<Bit 1 */
+#define FSMC_BWTR4_DATAST_2 0x00000400U /*!<Bit 2 */
+#define FSMC_BWTR4_DATAST_3 0x00000800U /*!<Bit 3 */
+#define FSMC_BWTR4_DATAST_4 0x00001000U /*!<Bit 4 */
+#define FSMC_BWTR4_DATAST_5 0x00002000U /*!<Bit 5 */
+#define FSMC_BWTR4_DATAST_6 0x00004000U /*!<Bit 6 */
+#define FSMC_BWTR4_DATAST_7 0x00008000U /*!<Bit 7 */
+
+#define FSMC_BWTR4_BUSTURN 0x000F0000U /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
+#define FSMC_BWTR4_BUSTURN_0 0x00010000U /*!<Bit 0 */
+#define FSMC_BWTR4_BUSTURN_1 0x00020000U /*!<Bit 1 */
+#define FSMC_BWTR4_BUSTURN_2 0x00040000U /*!<Bit 2 */
+#define FSMC_BWTR4_BUSTURN_3 0x00080000U /*!<Bit 3 */
+
+#define FSMC_BWTR4_ACCMOD 0x30000000U /*!<ACCMOD[1:0] bits (Access mode) */
+#define FSMC_BWTR4_ACCMOD_0 0x10000000U /*!<Bit 0 */
+#define FSMC_BWTR4_ACCMOD_1 0x20000000U /*!<Bit 1 */
+
+/******************************************************************************/
+/* */
+/* General Purpose I/O */
+/* */
+/******************************************************************************/
+/****************** Bits definition for GPIO_MODER register *****************/
+#define GPIO_MODER_MODER0 0x00000003U
+#define GPIO_MODER_MODER0_0 0x00000001U
+#define GPIO_MODER_MODER0_1 0x00000002U
+
+#define GPIO_MODER_MODER1 0x0000000CU
+#define GPIO_MODER_MODER1_0 0x00000004U
+#define GPIO_MODER_MODER1_1 0x00000008U
+
+#define GPIO_MODER_MODER2 0x00000030U
+#define GPIO_MODER_MODER2_0 0x00000010U
+#define GPIO_MODER_MODER2_1 0x00000020U
+
+#define GPIO_MODER_MODER3 0x000000C0U
+#define GPIO_MODER_MODER3_0 0x00000040U
+#define GPIO_MODER_MODER3_1 0x00000080U
+
+#define GPIO_MODER_MODER4 0x00000300U
+#define GPIO_MODER_MODER4_0 0x00000100U
+#define GPIO_MODER_MODER4_1 0x00000200U
+
+#define GPIO_MODER_MODER5 0x00000C00U
+#define GPIO_MODER_MODER5_0 0x00000400U
+#define GPIO_MODER_MODER5_1 0x00000800U
+
+#define GPIO_MODER_MODER6 0x00003000U
+#define GPIO_MODER_MODER6_0 0x00001000U
+#define GPIO_MODER_MODER6_1 0x00002000U
+
+#define GPIO_MODER_MODER7 0x0000C000U
+#define GPIO_MODER_MODER7_0 0x00004000U
+#define GPIO_MODER_MODER7_1 0x00008000U
+
+#define GPIO_MODER_MODER8 0x00030000U
+#define GPIO_MODER_MODER8_0 0x00010000U
+#define GPIO_MODER_MODER8_1 0x00020000U
+
+#define GPIO_MODER_MODER9 0x000C0000U
+#define GPIO_MODER_MODER9_0 0x00040000U
+#define GPIO_MODER_MODER9_1 0x00080000U
+
+#define GPIO_MODER_MODER10 0x00300000U
+#define GPIO_MODER_MODER10_0 0x00100000U
+#define GPIO_MODER_MODER10_1 0x00200000U
+
+#define GPIO_MODER_MODER11 0x00C00000U
+#define GPIO_MODER_MODER11_0 0x00400000U
+#define GPIO_MODER_MODER11_1 0x00800000U
+
+#define GPIO_MODER_MODER12 0x03000000U
+#define GPIO_MODER_MODER12_0 0x01000000U
+#define GPIO_MODER_MODER12_1 0x02000000U
+
+#define GPIO_MODER_MODER13 0x0C000000U
+#define GPIO_MODER_MODER13_0 0x04000000U
+#define GPIO_MODER_MODER13_1 0x08000000U
+
+#define GPIO_MODER_MODER14 0x30000000U
+#define GPIO_MODER_MODER14_0 0x10000000U
+#define GPIO_MODER_MODER14_1 0x20000000U
+
+#define GPIO_MODER_MODER15 0xC0000000U
+#define GPIO_MODER_MODER15_0 0x40000000U
+#define GPIO_MODER_MODER15_1 0x80000000U
+
+/****************** Bits definition for GPIO_OTYPER register ****************/
+#define GPIO_OTYPER_OT_0 0x00000001U
+#define GPIO_OTYPER_OT_1 0x00000002U
+#define GPIO_OTYPER_OT_2 0x00000004U
+#define GPIO_OTYPER_OT_3 0x00000008U
+#define GPIO_OTYPER_OT_4 0x00000010U
+#define GPIO_OTYPER_OT_5 0x00000020U
+#define GPIO_OTYPER_OT_6 0x00000040U
+#define GPIO_OTYPER_OT_7 0x00000080U
+#define GPIO_OTYPER_OT_8 0x00000100U
+#define GPIO_OTYPER_OT_9 0x00000200U
+#define GPIO_OTYPER_OT_10 0x00000400U
+#define GPIO_OTYPER_OT_11 0x00000800U
+#define GPIO_OTYPER_OT_12 0x00001000U
+#define GPIO_OTYPER_OT_13 0x00002000U
+#define GPIO_OTYPER_OT_14 0x00004000U
+#define GPIO_OTYPER_OT_15 0x00008000U
+
+/****************** Bits definition for GPIO_OSPEEDR register ***************/
+#define GPIO_OSPEEDER_OSPEEDR0 0x00000003U
+#define GPIO_OSPEEDER_OSPEEDR0_0 0x00000001U
+#define GPIO_OSPEEDER_OSPEEDR0_1 0x00000002U
+
+#define GPIO_OSPEEDER_OSPEEDR1 0x0000000CU
+#define GPIO_OSPEEDER_OSPEEDR1_0 0x00000004U
+#define GPIO_OSPEEDER_OSPEEDR1_1 0x00000008U
+
+#define GPIO_OSPEEDER_OSPEEDR2 0x00000030U
+#define GPIO_OSPEEDER_OSPEEDR2_0 0x00000010U
+#define GPIO_OSPEEDER_OSPEEDR2_1 0x00000020U
+
+#define GPIO_OSPEEDER_OSPEEDR3 0x000000C0U
+#define GPIO_OSPEEDER_OSPEEDR3_0 0x00000040U
+#define GPIO_OSPEEDER_OSPEEDR3_1 0x00000080U
+
+#define GPIO_OSPEEDER_OSPEEDR4 0x00000300U
+#define GPIO_OSPEEDER_OSPEEDR4_0 0x00000100U
+#define GPIO_OSPEEDER_OSPEEDR4_1 0x00000200U
+
+#define GPIO_OSPEEDER_OSPEEDR5 0x00000C00U
+#define GPIO_OSPEEDER_OSPEEDR5_0 0x00000400U
+#define GPIO_OSPEEDER_OSPEEDR5_1 0x00000800U
+
+#define GPIO_OSPEEDER_OSPEEDR6 0x00003000U
+#define GPIO_OSPEEDER_OSPEEDR6_0 0x00001000U
+#define GPIO_OSPEEDER_OSPEEDR6_1 0x00002000U
+
+#define GPIO_OSPEEDER_OSPEEDR7 0x0000C000U
+#define GPIO_OSPEEDER_OSPEEDR7_0 0x00004000U
+#define GPIO_OSPEEDER_OSPEEDR7_1 0x00008000U
+
+#define GPIO_OSPEEDER_OSPEEDR8 0x00030000U
+#define GPIO_OSPEEDER_OSPEEDR8_0 0x00010000U
+#define GPIO_OSPEEDER_OSPEEDR8_1 0x00020000U
+
+#define GPIO_OSPEEDER_OSPEEDR9 0x000C0000U
+#define GPIO_OSPEEDER_OSPEEDR9_0 0x00040000U
+#define GPIO_OSPEEDER_OSPEEDR9_1 0x00080000U
+
+#define GPIO_OSPEEDER_OSPEEDR10 0x00300000U
+#define GPIO_OSPEEDER_OSPEEDR10_0 0x00100000U
+#define GPIO_OSPEEDER_OSPEEDR10_1 0x00200000U
+
+#define GPIO_OSPEEDER_OSPEEDR11 0x00C00000U
+#define GPIO_OSPEEDER_OSPEEDR11_0 0x00400000U
+#define GPIO_OSPEEDER_OSPEEDR11_1 0x00800000U
+
+#define GPIO_OSPEEDER_OSPEEDR12 0x03000000U
+#define GPIO_OSPEEDER_OSPEEDR12_0 0x01000000U
+#define GPIO_OSPEEDER_OSPEEDR12_1 0x02000000U
+
+#define GPIO_OSPEEDER_OSPEEDR13 0x0C000000U
+#define GPIO_OSPEEDER_OSPEEDR13_0 0x04000000U
+#define GPIO_OSPEEDER_OSPEEDR13_1 0x08000000U
+
+#define GPIO_OSPEEDER_OSPEEDR14 0x30000000U
+#define GPIO_OSPEEDER_OSPEEDR14_0 0x10000000U
+#define GPIO_OSPEEDER_OSPEEDR14_1 0x20000000U
+
+#define GPIO_OSPEEDER_OSPEEDR15 0xC0000000U
+#define GPIO_OSPEEDER_OSPEEDR15_0 0x40000000U
+#define GPIO_OSPEEDER_OSPEEDR15_1 0x80000000U
+
+/****************** Bits definition for GPIO_PUPDR register *****************/
+#define GPIO_PUPDR_PUPDR0 0x00000003U
+#define GPIO_PUPDR_PUPDR0_0 0x00000001U
+#define GPIO_PUPDR_PUPDR0_1 0x00000002U
+
+#define GPIO_PUPDR_PUPDR1 0x0000000CU
+#define GPIO_PUPDR_PUPDR1_0 0x00000004U
+#define GPIO_PUPDR_PUPDR1_1 0x00000008U
+
+#define GPIO_PUPDR_PUPDR2 0x00000030U
+#define GPIO_PUPDR_PUPDR2_0 0x00000010U
+#define GPIO_PUPDR_PUPDR2_1 0x00000020U
+
+#define GPIO_PUPDR_PUPDR3 0x000000C0U
+#define GPIO_PUPDR_PUPDR3_0 0x00000040U
+#define GPIO_PUPDR_PUPDR3_1 0x00000080U
+
+#define GPIO_PUPDR_PUPDR4 0x00000300U
+#define GPIO_PUPDR_PUPDR4_0 0x00000100U
+#define GPIO_PUPDR_PUPDR4_1 0x00000200U
+
+#define GPIO_PUPDR_PUPDR5 0x00000C00U
+#define GPIO_PUPDR_PUPDR5_0 0x00000400U
+#define GPIO_PUPDR_PUPDR5_1 0x00000800U
+
+#define GPIO_PUPDR_PUPDR6 0x00003000U
+#define GPIO_PUPDR_PUPDR6_0 0x00001000U
+#define GPIO_PUPDR_PUPDR6_1 0x00002000U
+
+#define GPIO_PUPDR_PUPDR7 0x0000C000U
+#define GPIO_PUPDR_PUPDR7_0 0x00004000U
+#define GPIO_PUPDR_PUPDR7_1 0x00008000U
+
+#define GPIO_PUPDR_PUPDR8 0x00030000U
+#define GPIO_PUPDR_PUPDR8_0 0x00010000U
+#define GPIO_PUPDR_PUPDR8_1 0x00020000U
+
+#define GPIO_PUPDR_PUPDR9 0x000C0000U
+#define GPIO_PUPDR_PUPDR9_0 0x00040000U
+#define GPIO_PUPDR_PUPDR9_1 0x00080000U
+
+#define GPIO_PUPDR_PUPDR10 0x00300000U
+#define GPIO_PUPDR_PUPDR10_0 0x00100000U
+#define GPIO_PUPDR_PUPDR10_1 0x00200000U
+
+#define GPIO_PUPDR_PUPDR11 0x00C00000U
+#define GPIO_PUPDR_PUPDR11_0 0x00400000U
+#define GPIO_PUPDR_PUPDR11_1 0x00800000U
+
+#define GPIO_PUPDR_PUPDR12 0x03000000U
+#define GPIO_PUPDR_PUPDR12_0 0x01000000U
+#define GPIO_PUPDR_PUPDR12_1 0x02000000U
+
+#define GPIO_PUPDR_PUPDR13 0x0C000000U
+#define GPIO_PUPDR_PUPDR13_0 0x04000000U
+#define GPIO_PUPDR_PUPDR13_1 0x08000000U
+
+#define GPIO_PUPDR_PUPDR14 0x30000000U
+#define GPIO_PUPDR_PUPDR14_0 0x10000000U
+#define GPIO_PUPDR_PUPDR14_1 0x20000000U
+
+#define GPIO_PUPDR_PUPDR15 0xC0000000U
+#define GPIO_PUPDR_PUPDR15_0 0x40000000U
+#define GPIO_PUPDR_PUPDR15_1 0x80000000U
+
+/****************** Bits definition for GPIO_IDR register *******************/
+#define GPIO_IDR_IDR_0 0x00000001U
+#define GPIO_IDR_IDR_1 0x00000002U
+#define GPIO_IDR_IDR_2 0x00000004U
+#define GPIO_IDR_IDR_3 0x00000008U
+#define GPIO_IDR_IDR_4 0x00000010U
+#define GPIO_IDR_IDR_5 0x00000020U
+#define GPIO_IDR_IDR_6 0x00000040U
+#define GPIO_IDR_IDR_7 0x00000080U
+#define GPIO_IDR_IDR_8 0x00000100U
+#define GPIO_IDR_IDR_9 0x00000200U
+#define GPIO_IDR_IDR_10 0x00000400U
+#define GPIO_IDR_IDR_11 0x00000800U
+#define GPIO_IDR_IDR_12 0x00001000U
+#define GPIO_IDR_IDR_13 0x00002000U
+#define GPIO_IDR_IDR_14 0x00004000U
+#define GPIO_IDR_IDR_15 0x00008000U
+
+/****************** Bits definition for GPIO_ODR register *******************/
+#define GPIO_ODR_ODR_0 0x00000001U
+#define GPIO_ODR_ODR_1 0x00000002U
+#define GPIO_ODR_ODR_2 0x00000004U
+#define GPIO_ODR_ODR_3 0x00000008U
+#define GPIO_ODR_ODR_4 0x00000010U
+#define GPIO_ODR_ODR_5 0x00000020U
+#define GPIO_ODR_ODR_6 0x00000040U
+#define GPIO_ODR_ODR_7 0x00000080U
+#define GPIO_ODR_ODR_8 0x00000100U
+#define GPIO_ODR_ODR_9 0x00000200U
+#define GPIO_ODR_ODR_10 0x00000400U
+#define GPIO_ODR_ODR_11 0x00000800U
+#define GPIO_ODR_ODR_12 0x00001000U
+#define GPIO_ODR_ODR_13 0x00002000U
+#define GPIO_ODR_ODR_14 0x00004000U
+#define GPIO_ODR_ODR_15 0x00008000U
+
+/****************** Bits definition for GPIO_BSRR register ******************/
+#define GPIO_BSRR_BS_0 0x00000001U
+#define GPIO_BSRR_BS_1 0x00000002U
+#define GPIO_BSRR_BS_2 0x00000004U
+#define GPIO_BSRR_BS_3 0x00000008U
+#define GPIO_BSRR_BS_4 0x00000010U
+#define GPIO_BSRR_BS_5 0x00000020U
+#define GPIO_BSRR_BS_6 0x00000040U
+#define GPIO_BSRR_BS_7 0x00000080U
+#define GPIO_BSRR_BS_8 0x00000100U
+#define GPIO_BSRR_BS_9 0x00000200U
+#define GPIO_BSRR_BS_10 0x00000400U
+#define GPIO_BSRR_BS_11 0x00000800U
+#define GPIO_BSRR_BS_12 0x00001000U
+#define GPIO_BSRR_BS_13 0x00002000U
+#define GPIO_BSRR_BS_14 0x00004000U
+#define GPIO_BSRR_BS_15 0x00008000U
+#define GPIO_BSRR_BR_0 0x00010000U
+#define GPIO_BSRR_BR_1 0x00020000U
+#define GPIO_BSRR_BR_2 0x00040000U
+#define GPIO_BSRR_BR_3 0x00080000U
+#define GPIO_BSRR_BR_4 0x00100000U
+#define GPIO_BSRR_BR_5 0x00200000U
+#define GPIO_BSRR_BR_6 0x00400000U
+#define GPIO_BSRR_BR_7 0x00800000U
+#define GPIO_BSRR_BR_8 0x01000000U
+#define GPIO_BSRR_BR_9 0x02000000U
+#define GPIO_BSRR_BR_10 0x04000000U
+#define GPIO_BSRR_BR_11 0x08000000U
+#define GPIO_BSRR_BR_12 0x10000000U
+#define GPIO_BSRR_BR_13 0x20000000U
+#define GPIO_BSRR_BR_14 0x40000000U
+#define GPIO_BSRR_BR_15 0x80000000U
+
+/****************** Bit definition for GPIO_LCKR register *********************/
+#define GPIO_LCKR_LCK0 0x00000001U
+#define GPIO_LCKR_LCK1 0x00000002U
+#define GPIO_LCKR_LCK2 0x00000004U
+#define GPIO_LCKR_LCK3 0x00000008U
+#define GPIO_LCKR_LCK4 0x00000010U
+#define GPIO_LCKR_LCK5 0x00000020U
+#define GPIO_LCKR_LCK6 0x00000040U
+#define GPIO_LCKR_LCK7 0x00000080U
+#define GPIO_LCKR_LCK8 0x00000100U
+#define GPIO_LCKR_LCK9 0x00000200U
+#define GPIO_LCKR_LCK10 0x00000400U
+#define GPIO_LCKR_LCK11 0x00000800U
+#define GPIO_LCKR_LCK12 0x00001000U
+#define GPIO_LCKR_LCK13 0x00002000U
+#define GPIO_LCKR_LCK14 0x00004000U
+#define GPIO_LCKR_LCK15 0x00008000U
+#define GPIO_LCKR_LCKK 0x00010000U
+
+/******************************************************************************/
+/* */
+/* Inter-integrated Circuit Interface */
+/* */
+/******************************************************************************/
+/******************* Bit definition for I2C_CR1 register ********************/
+#define I2C_CR1_PE 0x00000001U /*!<Peripheral Enable */
+#define I2C_CR1_SMBUS 0x00000002U /*!<SMBus Mode */
+#define I2C_CR1_SMBTYPE 0x00000008U /*!<SMBus Type */
+#define I2C_CR1_ENARP 0x00000010U /*!<ARP Enable */
+#define I2C_CR1_ENPEC 0x00000020U /*!<PEC Enable */
+#define I2C_CR1_ENGC 0x00000040U /*!<General Call Enable */
+#define I2C_CR1_NOSTRETCH 0x00000080U /*!<Clock Stretching Disable (Slave mode) */
+#define I2C_CR1_START 0x00000100U /*!<Start Generation */
+#define I2C_CR1_STOP 0x00000200U /*!<Stop Generation */
+#define I2C_CR1_ACK 0x00000400U /*!<Acknowledge Enable */
+#define I2C_CR1_POS 0x00000800U /*!<Acknowledge/PEC Position (for data reception) */
+#define I2C_CR1_PEC 0x00001000U /*!<Packet Error Checking */
+#define I2C_CR1_ALERT 0x00002000U /*!<SMBus Alert */
+#define I2C_CR1_SWRST 0x00008000U /*!<Software Reset */
+
+/******************* Bit definition for I2C_CR2 register ********************/
+#define I2C_CR2_FREQ 0x0000003FU /*!<FREQ[5:0] bits (Peripheral Clock Frequency) */
+#define I2C_CR2_FREQ_0 0x00000001U /*!<Bit 0 */
+#define I2C_CR2_FREQ_1 0x00000002U /*!<Bit 1 */
+#define I2C_CR2_FREQ_2 0x00000004U /*!<Bit 2 */
+#define I2C_CR2_FREQ_3 0x00000008U /*!<Bit 3 */
+#define I2C_CR2_FREQ_4 0x00000010U /*!<Bit 4 */
+#define I2C_CR2_FREQ_5 0x00000020U /*!<Bit 5 */
+
+#define I2C_CR2_ITERREN 0x00000100U /*!<Error Interrupt Enable */
+#define I2C_CR2_ITEVTEN 0x00000200U /*!<Event Interrupt Enable */
+#define I2C_CR2_ITBUFEN 0x00000400U /*!<Buffer Interrupt Enable */
+#define I2C_CR2_DMAEN 0x00000800U /*!<DMA Requests Enable */
+#define I2C_CR2_LAST 0x00001000U /*!<DMA Last Transfer */
+
+/******************* Bit definition for I2C_OAR1 register *******************/
+#define I2C_OAR1_ADD1_7 0x000000FEU /*!<Interface Address */
+#define I2C_OAR1_ADD8_9 0x00000300U /*!<Interface Address */
+
+#define I2C_OAR1_ADD0 0x00000001U /*!<Bit 0 */
+#define I2C_OAR1_ADD1 0x00000002U /*!<Bit 1 */
+#define I2C_OAR1_ADD2 0x00000004U /*!<Bit 2 */
+#define I2C_OAR1_ADD3 0x00000008U /*!<Bit 3 */
+#define I2C_OAR1_ADD4 0x00000010U /*!<Bit 4 */
+#define I2C_OAR1_ADD5 0x00000020U /*!<Bit 5 */
+#define I2C_OAR1_ADD6 0x00000040U /*!<Bit 6 */
+#define I2C_OAR1_ADD7 0x00000080U /*!<Bit 7 */
+#define I2C_OAR1_ADD8 0x00000100U /*!<Bit 8 */
+#define I2C_OAR1_ADD9 0x00000200U /*!<Bit 9 */
+
+#define I2C_OAR1_ADDMODE 0x00008000U /*!<Addressing Mode (Slave mode) */
+
+/******************* Bit definition for I2C_OAR2 register *******************/
+#define I2C_OAR2_ENDUAL 0x00000001U /*!<Dual addressing mode enable */
+#define I2C_OAR2_ADD2 0x000000FEU /*!<Interface address */
+
+/******************** Bit definition for I2C_DR register ********************/
+#define I2C_DR_DR 0x000000FFU /*!<8-bit Data Register */
+
+/******************* Bit definition for I2C_SR1 register ********************/
+#define I2C_SR1_SB 0x00000001U /*!<Start Bit (Master mode) */
+#define I2C_SR1_ADDR 0x00000002U /*!<Address sent (master mode)/matched (slave mode) */
+#define I2C_SR1_BTF 0x00000004U /*!<Byte Transfer Finished */
+#define I2C_SR1_ADD10 0x00000008U /*!<10-bit header sent (Master mode) */
+#define I2C_SR1_STOPF 0x00000010U /*!<Stop detection (Slave mode) */
+#define I2C_SR1_RXNE 0x00000040U /*!<Data Register not Empty (receivers) */
+#define I2C_SR1_TXE 0x00000080U /*!<Data Register Empty (transmitters) */
+#define I2C_SR1_BERR 0x00000100U /*!<Bus Error */
+#define I2C_SR1_ARLO 0x00000200U /*!<Arbitration Lost (master mode) */
+#define I2C_SR1_AF 0x00000400U /*!<Acknowledge Failure */
+#define I2C_SR1_OVR 0x00000800U /*!<Overrun/Underrun */
+#define I2C_SR1_PECERR 0x00001000U /*!<PEC Error in reception */
+#define I2C_SR1_TIMEOUT 0x00004000U /*!<Timeout or Tlow Error */
+#define I2C_SR1_SMBALERT 0x00008000U /*!<SMBus Alert */
+
+/******************* Bit definition for I2C_SR2 register ********************/
+#define I2C_SR2_MSL 0x00000001U /*!<Master/Slave */
+#define I2C_SR2_BUSY 0x00000002U /*!<Bus Busy */
+#define I2C_SR2_TRA 0x00000004U /*!<Transmitter/Receiver */
+#define I2C_SR2_GENCALL 0x00000010U /*!<General Call Address (Slave mode) */
+#define I2C_SR2_SMBDEFAULT 0x00000020U /*!<SMBus Device Default Address (Slave mode) */
+#define I2C_SR2_SMBHOST 0x00000040U /*!<SMBus Host Header (Slave mode) */
+#define I2C_SR2_DUALF 0x00000080U /*!<Dual Flag (Slave mode) */
+#define I2C_SR2_PEC 0x0000FF00U /*!<Packet Error Checking Register */
+
+/******************* Bit definition for I2C_CCR register ********************/
+#define I2C_CCR_CCR 0x00000FFFU /*!<Clock Control Register in Fast/Standard mode (Master mode) */
+#define I2C_CCR_DUTY 0x00004000U /*!<Fast Mode Duty Cycle */
+#define I2C_CCR_FS 0x00008000U /*!<I2C Master Mode Selection */
+
+/****************** Bit definition for I2C_TRISE register *******************/
+#define I2C_TRISE_TRISE 0x0000003FU /*!<Maximum Rise Time in Fast/Standard mode (Master mode) */
+
+/****************** Bit definition for I2C_FLTR register *******************/
+#define I2C_FLTR_DNF 0x0000000FU /*!<Digital Noise Filter */
+#define I2C_FLTR_ANOFF 0x00000010U /*!<Analog Noise Filter OFF */
+
+/******************************************************************************/
+/* */
+/* Fast Mode Plus Inter-integrated Circuit Interface (I2C) */
+/* */
+/******************************************************************************/
+/******************* Bit definition for I2C_CR1 register *******************/
+#define FMPI2C_CR1_PE 0x00000001U /*!< Peripheral enable */
+#define FMPI2C_CR1_TXIE 0x00000002U /*!< TX interrupt enable */
+#define FMPI2C_CR1_RXIE 0x00000004U /*!< RX interrupt enable */
+#define FMPI2C_CR1_ADDRIE 0x00000008U /*!< Address match interrupt enable */
+#define FMPI2C_CR1_NACKIE 0x00000010U /*!< NACK received interrupt enable */
+#define FMPI2C_CR1_STOPIE 0x00000020U /*!< STOP detection interrupt enable */
+#define FMPI2C_CR1_TCIE 0x00000040U /*!< Transfer complete interrupt enable */
+#define FMPI2C_CR1_ERRIE 0x00000080U /*!< Errors interrupt enable */
+#define FMPI2C_CR1_DFN 0x00000F00U /*!< Digital noise filter */
+#define FMPI2C_CR1_ANFOFF 0x00001000U /*!< Analog noise filter OFF */
+#define FMPI2C_CR1_TXDMAEN 0x00004000U /*!< DMA transmission requests enable */
+#define FMPI2C_CR1_RXDMAEN 0x00008000U /*!< DMA reception requests enable */
+#define FMPI2C_CR1_SBC 0x00010000U /*!< Slave byte control */
+#define FMPI2C_CR1_NOSTRETCH 0x00020000U /*!< Clock stretching disable */
+#define FMPI2C_CR1_GCEN 0x00080000U /*!< General call enable */
+#define FMPI2C_CR1_SMBHEN 0x00100000U /*!< SMBus host address enable */
+#define FMPI2C_CR1_SMBDEN 0x00200000U /*!< SMBus device default address enable */
+#define FMPI2C_CR1_ALERTEN 0x00400000U /*!< SMBus alert enable */
+#define FMPI2C_CR1_PECEN 0x00800000U /*!< PEC enable */
+
+/****************** Bit definition for I2C_CR2 register ********************/
+#define FMPI2C_CR2_SADD 0x000003FFU /*!< Slave address (master mode) */
+#define FMPI2C_CR2_RD_WRN 0x00000400U /*!< Transfer direction (master mode) */
+#define FMPI2C_CR2_ADD10 0x00000800U /*!< 10-bit addressing mode (master mode) */
+#define FMPI2C_CR2_HEAD10R 0x00001000U /*!< 10-bit address header only read direction (master mode) */
+#define FMPI2C_CR2_START 0x00002000U /*!< START generation */
+#define FMPI2C_CR2_STOP 0x00004000U /*!< STOP generation (master mode) */
+#define FMPI2C_CR2_NACK 0x00008000U /*!< NACK generation (slave mode) */
+#define FMPI2C_CR2_NBYTES 0x00FF0000U /*!< Number of bytes */
+#define FMPI2C_CR2_RELOAD 0x01000000U /*!< NBYTES reload mode */
+#define FMPI2C_CR2_AUTOEND 0x02000000U /*!< Automatic end mode (master mode) */
+#define FMPI2C_CR2_PECBYTE 0x04000000U /*!< Packet error checking byte */
+
+/******************* Bit definition for I2C_OAR1 register ******************/
+#define FMPI2C_OAR1_OA1 0x000003FFU /*!< Interface own address 1 */
+#define FMPI2C_OAR1_OA1MODE 0x00000400U /*!< Own address 1 10-bit mode */
+#define FMPI2C_OAR1_OA1EN 0x00008000U /*!< Own address 1 enable */
+
+/******************* Bit definition for I2C_OAR2 register ******************/
+#define FMPI2C_OAR2_OA2 0x000000FEU /*!< Interface own address 2 */
+#define FMPI2C_OAR2_OA2MSK 0x00000700U /*!< Own address 2 masks */
+#define FMPI2C_OAR2_OA2EN 0x00008000U /*!< Own address 2 enable */
+
+/******************* Bit definition for I2C_TIMINGR register *******************/
+#define FMPI2C_TIMINGR_SCLL 0x000000FFU /*!< SCL low period (master mode) */
+#define FMPI2C_TIMINGR_SCLH 0x0000FF00U /*!< SCL high period (master mode) */
+#define FMPI2C_TIMINGR_SDADEL 0x000F0000U /*!< Data hold time */
+#define FMPI2C_TIMINGR_SCLDEL 0x00F00000U /*!< Data setup time */
+#define FMPI2C_TIMINGR_PRESC 0xF0000000U /*!< Timings prescaler */
+
+/******************* Bit definition for I2C_TIMEOUTR register *******************/
+#define FMPI2C_TIMEOUTR_TIMEOUTA 0x00000FFFU /*!< Bus timeout A */
+#define FMPI2C_TIMEOUTR_TIDLE 0x00001000U /*!< Idle clock timeout detection */
+#define FMPI2C_TIMEOUTR_TIMOUTEN 0x00008000U /*!< Clock timeout enable */
+#define FMPI2C_TIMEOUTR_TIMEOUTB 0x0FFF0000U /*!< Bus timeout B */
+#define FMPI2C_TIMEOUTR_TEXTEN 0x80000000U /*!< Extended clock timeout enable */
+
+/****************** Bit definition for I2C_ISR register *********************/
+#define FMPI2C_ISR_TXE 0x00000001U /*!< Transmit data register empty */
+#define FMPI2C_ISR_TXIS 0x00000002U /*!< Transmit interrupt status */
+#define FMPI2C_ISR_RXNE 0x00000004U /*!< Receive data register not empty */
+#define FMPI2C_ISR_ADDR 0x00000008U /*!< Address matched (slave mode) */
+#define FMPI2C_ISR_NACKF 0x00000010U /*!< NACK received flag */
+#define FMPI2C_ISR_STOPF 0x00000020U /*!< STOP detection flag */
+#define FMPI2C_ISR_TC 0x00000040U /*!< Transfer complete (master mode) */
+#define FMPI2C_ISR_TCR 0x00000080U /*!< Transfer complete reload */
+#define FMPI2C_ISR_BERR 0x00000100U /*!< Bus error */
+#define FMPI2C_ISR_ARLO 0x00000200U /*!< Arbitration lost */
+#define FMPI2C_ISR_OVR 0x00000400U /*!< Overrun/Underrun */
+#define FMPI2C_ISR_PECERR 0x00000800U /*!< PEC error in reception */
+#define FMPI2C_ISR_TIMEOUT 0x00001000U /*!< Timeout or Tlow detection flag */
+#define FMPI2C_ISR_ALERT 0x00002000U /*!< SMBus alert */
+#define FMPI2C_ISR_BUSY 0x00008000U /*!< Bus busy */
+#define FMPI2C_ISR_DIR 0x00010000U /*!< Transfer direction (slave mode) */
+#define FMPI2C_ISR_ADDCODE 0x00FE0000U /*!< Address match code (slave mode) */
+
+/****************** Bit definition for I2C_ICR register *********************/
+#define FMPI2C_ICR_ADDRCF 0x00000008U /*!< Address matched clear flag */
+#define FMPI2C_ICR_NACKCF 0x00000010U /*!< NACK clear flag */
+#define FMPI2C_ICR_STOPCF 0x00000020U /*!< STOP detection clear flag */
+#define FMPI2C_ICR_BERRCF 0x00000100U /*!< Bus error clear flag */
+#define FMPI2C_ICR_ARLOCF 0x00000200U /*!< Arbitration lost clear flag */
+#define FMPI2C_ICR_OVRCF 0x00000400U /*!< Overrun/Underrun clear flag */
+#define FMPI2C_ICR_PECCF 0x00000800U /*!< PAC error clear flag */
+#define FMPI2C_ICR_TIMOUTCF 0x00001000U /*!< Timeout clear flag */
+#define FMPI2C_ICR_ALERTCF 0x00002000U /*!< Alert clear flag */
+
+/****************** Bit definition for I2C_PECR register *********************/
+#define FMPI2C_PECR_PEC 0x000000FFU /*!< PEC register */
+
+/****************** Bit definition for I2C_RXDR register *********************/
+#define FMPI2C_RXDR_RXDATA 0x000000FFU /*!< 8-bit receive data */
+
+/****************** Bit definition for I2C_TXDR register *********************/
+#define FMPI2C_TXDR_TXDATA 0x000000FFU /*!< 8-bit transmit data */
+
+/******************************************************************************/
+/* */
+/* Independent WATCHDOG */
+/* */
+/******************************************************************************/
+/******************* Bit definition for IWDG_KR register ********************/
+#define IWDG_KR_KEY 0xFFFFU /*!<Key value (write only, read 0000h) */
+
+/******************* Bit definition for IWDG_PR register ********************/
+#define IWDG_PR_PR 0x07U /*!<PR[2:0] (Prescaler divider) */
+#define IWDG_PR_PR_0 0x01U /*!<Bit 0 */
+#define IWDG_PR_PR_1 0x02U /*!<Bit 1 */
+#define IWDG_PR_PR_2 0x04U /*!<Bit 2 */
+
+/******************* Bit definition for IWDG_RLR register *******************/
+#define IWDG_RLR_RL 0x0FFFU /*!<Watchdog counter reload value */
+
+/******************* Bit definition for IWDG_SR register ********************/
+#define IWDG_SR_PVU 0x01U /*!<Watchdog prescaler value update */
+#define IWDG_SR_RVU 0x02U /*!<Watchdog counter reload value update */
+
+
+/******************************************************************************/
+/* */
+/* Power Control */
+/* */
+/******************************************************************************/
+/******************** Bit definition for PWR_CR register ********************/
+#define PWR_CR_LPDS 0x00000001U /*!< Low-Power Deepsleep */
+#define PWR_CR_PDDS 0x00000002U /*!< Power Down Deepsleep */
+#define PWR_CR_CWUF 0x00000004U /*!< Clear Wakeup Flag */
+#define PWR_CR_CSBF 0x00000008U /*!< Clear Standby Flag */
+#define PWR_CR_PVDE 0x00000010U /*!< Power Voltage Detector Enable */
+
+#define PWR_CR_PLS 0x000000E0U /*!< PLS[2:0] bits (PVD Level Selection) */
+#define PWR_CR_PLS_0 0x00000020U /*!< Bit 0 */
+#define PWR_CR_PLS_1 0x00000040U /*!< Bit 1 */
+#define PWR_CR_PLS_2 0x00000080U /*!< Bit 2 */
+
+/*!< PVD level configuration */
+#define PWR_CR_PLS_LEV0 0x00000000U /*!< PVD level 0 */
+#define PWR_CR_PLS_LEV1 0x00000020U /*!< PVD level 1 */
+#define PWR_CR_PLS_LEV2 0x00000040U /*!< PVD level 2 */
+#define PWR_CR_PLS_LEV3 0x00000060U /*!< PVD level 3 */
+#define PWR_CR_PLS_LEV4 0x00000080U /*!< PVD level 4 */
+#define PWR_CR_PLS_LEV5 0x000000A0U /*!< PVD level 5 */
+#define PWR_CR_PLS_LEV6 0x000000C0U /*!< PVD level 6 */
+#define PWR_CR_PLS_LEV7 0x000000E0U /*!< PVD level 7 */
+
+#define PWR_CR_DBP 0x00000100U /*!< Disable Backup Domain write protection */
+#define PWR_CR_FPDS 0x00000200U /*!< Flash power down in Stop mode */
+#define PWR_CR_LPLVDS 0x00000400U /*!< Low Power Regulator Low Voltage in Deep Sleep mode */
+#define PWR_CR_MRLVDS 0x00000800U /*!< Main Regulator Low Voltage in Deep Sleep mode */
+#define PWR_CR_ADCDC1 0x00002000U /*!< Refer to AN4073 on how to use this bit */
+
+#define PWR_CR_VOS 0x0000C000U /*!< VOS[1:0] bits (Regulator voltage scaling output selection) */
+#define PWR_CR_VOS_0 0x00004000U /*!< Bit 0 */
+#define PWR_CR_VOS_1 0x00008000U /*!< Bit 1 */
+
+#define PWR_CR_FMSSR 0x00100000U /*!< Flash Memory Sleep System Run */
+#define PWR_CR_FISSR 0x00200000U /*!< Flash Interface Stop while System Run */
+
+/******************* Bit definition for PWR_CSR register ********************/
+#define PWR_CSR_WUF 0x00000001U /*!< Wakeup Flag */
+#define PWR_CSR_SBF 0x00000002U /*!< Standby Flag */
+#define PWR_CSR_PVDO 0x00000004U /*!< PVD Output */
+#define PWR_CSR_BRR 0x00000008U /*!< Backup regulator ready */
+#define PWR_CSR_EWUP 0x00000100U /*!< Enable WKUP pin */
+#define PWR_CSR_BRE 0x00000200U /*!< Backup regulator enable */
+#define PWR_CSR_VOSRDY 0x00004000U /*!< Regulator voltage scaling output selection ready */
+/******************************************************************************/
+/* */
+/* QUADSPI */
+/* */
+/******************************************************************************/
+/***************** Bit definition for QUADSPI_CR register *******************/
+#define QUADSPI_CR_EN 0x00000001U /*!< Enable */
+#define QUADSPI_CR_ABORT 0x00000002U /*!< Abort request */
+#define QUADSPI_CR_DMAEN 0x00000004U /*!< DMA Enable */
+#define QUADSPI_CR_TCEN 0x00000008U /*!< Timeout Counter Enable */
+#define QUADSPI_CR_SSHIFT 0x00000010U /*!< SSHIFT Sample Shift */
+#define QUADSPI_CR_DFM 0x00000040U /*!< Dual Flash Mode */
+#define QUADSPI_CR_FSEL 0x00000080U /*!< Flash Select */
+#define QUADSPI_CR_FTHRES 0x00001F00U /*!< FTHRES[3:0] FIFO Level */
+#define QUADSPI_CR_FTHRES_0 0x00000100U /*!< Bit 0 */
+#define QUADSPI_CR_FTHRES_1 0x00000200U /*!< Bit 1 */
+#define QUADSPI_CR_FTHRES_2 0x00000400U /*!< Bit 2 */
+#define QUADSPI_CR_FTHRES_3 0x00000800U /*!< Bit 3 */
+#define QUADSPI_CR_FTHRES_4 0x00001000U /*!< Bit 4 */
+#define QUADSPI_CR_TEIE 0x00010000U /*!< Transfer Error Interrupt Enable */
+#define QUADSPI_CR_TCIE 0x00020000U /*!< Transfer Complete Interrupt Enable */
+#define QUADSPI_CR_FTIE 0x00040000U /*!< FIFO Threshold Interrupt Enable */
+#define QUADSPI_CR_SMIE 0x00080000U /*!< Status Match Interrupt Enable */
+#define QUADSPI_CR_TOIE 0x00100000U /*!< TimeOut Interrupt Enable */
+#define QUADSPI_CR_APMS 0x00400000U /*!< Bit 1 */
+#define QUADSPI_CR_PMM 0x00800000U /*!< Polling Match Mode */
+#define QUADSPI_CR_PRESCALER 0xFF000000U /*!< PRESCALER[7:0] Clock prescaler */
+#define QUADSPI_CR_PRESCALER_0 0x01000000U /*!< Bit 0 */
+#define QUADSPI_CR_PRESCALER_1 0x02000000U /*!< Bit 1 */
+#define QUADSPI_CR_PRESCALER_2 0x04000000U /*!< Bit 2 */
+#define QUADSPI_CR_PRESCALER_3 0x08000000U /*!< Bit 3 */
+#define QUADSPI_CR_PRESCALER_4 0x10000000U /*!< Bit 4 */
+#define QUADSPI_CR_PRESCALER_5 0x20000000U /*!< Bit 5 */
+#define QUADSPI_CR_PRESCALER_6 0x40000000U /*!< Bit 6 */
+#define QUADSPI_CR_PRESCALER_7 0x80000000U /*!< Bit 7 */
+
+/***************** Bit definition for QUADSPI_DCR register ******************/
+#define QUADSPI_DCR_CKMODE 0x00000001U /*!< Mode 0 / Mode 3 */
+#define QUADSPI_DCR_CSHT 0x00000700U /*!< CSHT[2:0]: ChipSelect High Time */
+#define QUADSPI_DCR_CSHT_0 0x00000100U /*!< Bit 0 */
+#define QUADSPI_DCR_CSHT_1 0x00000200U /*!< Bit 1 */
+#define QUADSPI_DCR_CSHT_2 0x00000400U /*!< Bit 2 */
+#define QUADSPI_DCR_FSIZE 0x001F0000U /*!< FSIZE[4:0]: Flash Size */
+#define QUADSPI_DCR_FSIZE_0 0x00010000U /*!< Bit 0 */
+#define QUADSPI_DCR_FSIZE_1 0x00020000U /*!< Bit 1 */
+#define QUADSPI_DCR_FSIZE_2 0x00040000U /*!< Bit 2 */
+#define QUADSPI_DCR_FSIZE_3 0x00080000U /*!< Bit 3 */
+#define QUADSPI_DCR_FSIZE_4 0x00100000U /*!< Bit 4 */
+
+/****************** Bit definition for QUADSPI_SR register *******************/
+#define QUADSPI_SR_TEF 0x00000001U /*!< Transfer Error Flag */
+#define QUADSPI_SR_TCF 0x00000002U /*!< Transfer Complete Flag */
+#define QUADSPI_SR_FTF 0x00000004U /*!< FIFO Threshlod Flag */
+#define QUADSPI_SR_SMF 0x00000008U /*!< Status Match Flag */
+#define QUADSPI_SR_TOF 0x00000010U /*!< Timeout Flag */
+#define QUADSPI_SR_BUSY 0x00000020U /*!< Busy */
+#define QUADSPI_SR_FLEVEL 0x00003F00U /*!< FIFO Threshlod Flag */
+#define QUADSPI_SR_FLEVEL_0 0x00000100U /*!< Bit 0 */
+#define QUADSPI_SR_FLEVEL_1 0x00000200U /*!< Bit 1 */
+#define QUADSPI_SR_FLEVEL_2 0x00000400U /*!< Bit 2 */
+#define QUADSPI_SR_FLEVEL_3 0x00000800U /*!< Bit 3 */
+#define QUADSPI_SR_FLEVEL_4 0x00001000U /*!< Bit 4 */
+#define QUADSPI_SR_FLEVEL_5 0x00002000U /*!< Bit 5 */
+
+/****************** Bit definition for QUADSPI_FCR register ******************/
+#define QUADSPI_FCR_CTEF 0x00000001U /*!< Clear Transfer Error Flag */
+#define QUADSPI_FCR_CTCF 0x00000002U /*!< Clear Transfer Complete Flag */
+#define QUADSPI_FCR_CSMF 0x00000008U /*!< Clear Status Match Flag */
+#define QUADSPI_FCR_CTOF 0x00000010U /*!< Clear Timeout Flag */
+
+/****************** Bit definition for QUADSPI_DLR register ******************/
+#define QUADSPI_DLR_DL 0xFFFFFFFFU /*!< DL[31:0]: Data Length */
+
+/****************** Bit definition for QUADSPI_CCR register ******************/
+#define QUADSPI_CCR_INSTRUCTION 0x000000FFU /*!< INSTRUCTION[7:0]: Instruction */
+#define QUADSPI_CCR_INSTRUCTION_0 0x00000001U /*!< Bit 0 */
+#define QUADSPI_CCR_INSTRUCTION_1 0x00000002U /*!< Bit 1 */
+#define QUADSPI_CCR_INSTRUCTION_2 0x00000004U /*!< Bit 2 */
+#define QUADSPI_CCR_INSTRUCTION_3 0x00000008U /*!< Bit 3 */
+#define QUADSPI_CCR_INSTRUCTION_4 0x00000010U /*!< Bit 4 */
+#define QUADSPI_CCR_INSTRUCTION_5 0x00000020U /*!< Bit 5 */
+#define QUADSPI_CCR_INSTRUCTION_6 0x00000040U /*!< Bit 6 */
+#define QUADSPI_CCR_INSTRUCTION_7 0x00000080U /*!< Bit 7 */
+#define QUADSPI_CCR_IMODE 0x00000300U /*!< IMODE[1:0]: Instruction Mode */
+#define QUADSPI_CCR_IMODE_0 0x00000100U /*!< Bit 0 */
+#define QUADSPI_CCR_IMODE_1 0x00000200U /*!< Bit 1 */
+#define QUADSPI_CCR_ADMODE 0x00000C00U /*!< ADMODE[1:0]: Address Mode */
+#define QUADSPI_CCR_ADMODE_0 0x00000400U /*!< Bit 0 */
+#define QUADSPI_CCR_ADMODE_1 0x00000800U /*!< Bit 1 */
+#define QUADSPI_CCR_ADSIZE 0x00003000U /*!< ADSIZE[1:0]: Address Size */
+#define QUADSPI_CCR_ADSIZE_0 0x00001000U /*!< Bit 0 */
+#define QUADSPI_CCR_ADSIZE_1 0x00002000U /*!< Bit 1 */
+#define QUADSPI_CCR_ABMODE 0x0000C000U /*!< ABMODE[1:0]: Alternate Bytes Mode */
+#define QUADSPI_CCR_ABMODE_0 0x00004000U /*!< Bit 0 */
+#define QUADSPI_CCR_ABMODE_1 0x00008000U /*!< Bit 1 */
+#define QUADSPI_CCR_ABSIZE 0x00030000U /*!< ABSIZE[1:0]: Instruction Mode */
+#define QUADSPI_CCR_ABSIZE_0 0x00010000U /*!< Bit 0 */
+#define QUADSPI_CCR_ABSIZE_1 0x00020000U /*!< Bit 1 */
+#define QUADSPI_CCR_DCYC 0x007C0000U /*!< DCYC[4:0]: Dummy Cycles */
+#define QUADSPI_CCR_DCYC_0 0x00040000U /*!< Bit 0 */
+#define QUADSPI_CCR_DCYC_1 0x00080000U /*!< Bit 1 */
+#define QUADSPI_CCR_DCYC_2 0x00100000U /*!< Bit 2 */
+#define QUADSPI_CCR_DCYC_3 0x00200000U /*!< Bit 3 */
+#define QUADSPI_CCR_DCYC_4 0x00400000U /*!< Bit 4 */
+#define QUADSPI_CCR_DMODE 0x03000000U /*!< DMODE[1:0]: Data Mode */
+#define QUADSPI_CCR_DMODE_0 0x01000000U /*!< Bit 0 */
+#define QUADSPI_CCR_DMODE_1 0x02000000U /*!< Bit 1 */
+#define QUADSPI_CCR_FMODE 0x0C000000U /*!< FMODE[1:0]: Functional Mode */
+#define QUADSPI_CCR_FMODE_0 0x04000000U /*!< Bit 0 */
+#define QUADSPI_CCR_FMODE_1 0x08000000U /*!< Bit 1 */
+#define QUADSPI_CCR_SIOO 0x10000000U /*!< SIOO: Send Instruction Only Once Mode */
+#define QUADSPI_CCR_DHHC 0x40000000U /*!< DHHC: Delay Half Hclk Cycle */
+#define QUADSPI_CCR_DDRM 0x80000000U /*!< DDRM: Double Data Rate Mode */
+/****************** Bit definition for QUADSPI_AR register *******************/
+#define QUADSPI_AR_ADDRESS 0xFFFFFFFFU /*!< ADDRESS[31:0]: Address */
+
+/****************** Bit definition for QUADSPI_ABR register ******************/
+#define QUADSPI_ABR_ALTERNATE 0xFFFFFFFFU /*!< ALTERNATE[31:0]: Alternate Bytes */
+
+/****************** Bit definition for QUADSPI_DR register *******************/
+#define QUADSPI_DR_DATA 0xFFFFFFFFU /*!< DATA[31:0]: Data */
+
+/****************** Bit definition for QUADSPI_PSMKR register ****************/
+#define QUADSPI_PSMKR_MASK 0xFFFFFFFFU /*!< MASK[31:0]: Status Mask */
+
+/****************** Bit definition for QUADSPI_PSMAR register ****************/
+#define QUADSPI_PSMAR_MATCH 0xFFFFFFFFU /*!< MATCH[31:0]: Status Match */
+
+/****************** Bit definition for QUADSPI_PIR register *****************/
+#define QUADSPI_PIR_INTERVAL 0x0000FFFFU /*!< INTERVAL[15:0]: Polling Interval */
+
+/****************** Bit definition for QUADSPI_LPTR register *****************/
+#define QUADSPI_LPTR_TIMEOUT 0x0000FFFFU /*!< TIMEOUT[15:0]: Timeout period */
+
+/******************************************************************************/
+/* */
+/* Reset and Clock Control */
+/* */
+/******************************************************************************/
+/******************** Bit definition for RCC_CR register ********************/
+#define RCC_CR_HSION 0x00000001U
+#define RCC_CR_HSIRDY 0x00000002U
+
+#define RCC_CR_HSITRIM 0x000000F8U
+#define RCC_CR_HSITRIM_0 0x00000008U/*!<Bit 0 */
+#define RCC_CR_HSITRIM_1 0x00000010U/*!<Bit 1 */
+#define RCC_CR_HSITRIM_2 0x00000020U/*!<Bit 2 */
+#define RCC_CR_HSITRIM_3 0x00000040U/*!<Bit 3 */
+#define RCC_CR_HSITRIM_4 0x00000080U/*!<Bit 4 */
+
+#define RCC_CR_HSICAL 0x0000FF00U
+#define RCC_CR_HSICAL_0 0x00000100U/*!<Bit 0 */
+#define RCC_CR_HSICAL_1 0x00000200U/*!<Bit 1 */
+#define RCC_CR_HSICAL_2 0x00000400U/*!<Bit 2 */
+#define RCC_CR_HSICAL_3 0x00000800U/*!<Bit 3 */
+#define RCC_CR_HSICAL_4 0x00001000U/*!<Bit 4 */
+#define RCC_CR_HSICAL_5 0x00002000U/*!<Bit 5 */
+#define RCC_CR_HSICAL_6 0x00004000U/*!<Bit 6 */
+#define RCC_CR_HSICAL_7 0x00008000U/*!<Bit 7 */
+
+#define RCC_CR_HSEON 0x00010000U
+#define RCC_CR_HSERDY 0x00020000U
+#define RCC_CR_HSEBYP 0x00040000U
+#define RCC_CR_CSSON 0x00080000U
+#define RCC_CR_PLLON 0x01000000U
+#define RCC_CR_PLLRDY 0x02000000U
+#define RCC_CR_PLLI2SON 0x04000000U
+#define RCC_CR_PLLI2SRDY 0x08000000U
+
+/******************** Bit definition for RCC_PLLCFGR register ***************/
+#define RCC_PLLCFGR_PLLM 0x0000003FU
+#define RCC_PLLCFGR_PLLM_0 0x00000001U
+#define RCC_PLLCFGR_PLLM_1 0x00000002U
+#define RCC_PLLCFGR_PLLM_2 0x00000004U
+#define RCC_PLLCFGR_PLLM_3 0x00000008U
+#define RCC_PLLCFGR_PLLM_4 0x00000010U
+#define RCC_PLLCFGR_PLLM_5 0x00000020U
+
+#define RCC_PLLCFGR_PLLN 0x00007FC0U
+#define RCC_PLLCFGR_PLLN_0 0x00000040U
+#define RCC_PLLCFGR_PLLN_1 0x00000080U
+#define RCC_PLLCFGR_PLLN_2 0x00000100U
+#define RCC_PLLCFGR_PLLN_3 0x00000200U
+#define RCC_PLLCFGR_PLLN_4 0x00000400U
+#define RCC_PLLCFGR_PLLN_5 0x00000800U
+#define RCC_PLLCFGR_PLLN_6 0x00001000U
+#define RCC_PLLCFGR_PLLN_7 0x00002000U
+#define RCC_PLLCFGR_PLLN_8 0x00004000U
+
+#define RCC_PLLCFGR_PLLP 0x00030000U
+#define RCC_PLLCFGR_PLLP_0 0x00010000U
+#define RCC_PLLCFGR_PLLP_1 0x00020000U
+
+#define RCC_PLLCFGR_PLLSRC 0x00400000U
+#define RCC_PLLCFGR_PLLSRC_HSE 0x00400000U
+#define RCC_PLLCFGR_PLLSRC_HSI 0x00000000U
+
+#define RCC_PLLCFGR_PLLQ 0x0F000000U
+#define RCC_PLLCFGR_PLLQ_0 0x01000000U
+#define RCC_PLLCFGR_PLLQ_1 0x02000000U
+#define RCC_PLLCFGR_PLLQ_2 0x04000000U
+#define RCC_PLLCFGR_PLLQ_3 0x08000000U
+
+#define RCC_PLLCFGR_PLLR 0x70000000U
+#define RCC_PLLCFGR_PLLR_0 0x10000000U
+#define RCC_PLLCFGR_PLLR_1 0x20000000U
+#define RCC_PLLCFGR_PLLR_2 0x40000000U
+
+/******************** Bit definition for RCC_CFGR register ******************/
+/*!< SW configuration */
+#define RCC_CFGR_SW 0x00000003U /*!< SW[1:0] bits (System clock Switch) */
+#define RCC_CFGR_SW_0 0x00000001U /*!< Bit 0 */
+#define RCC_CFGR_SW_1 0x00000002U /*!< Bit 1 */
+
+#define RCC_CFGR_SW_HSI 0x00000000U /*!< HSI selected as system clock */
+#define RCC_CFGR_SW_HSE 0x00000001U /*!< HSE selected as system clock */
+#define RCC_CFGR_SW_PLL 0x00000002U /*!< PLL/PLLP selected as system clock */
+#define RCC_CFGR_SW_PLLR 0x00000003U /*!< PLL/PLLR selected as system clock */
+
+/*!< SWS configuration */
+#define RCC_CFGR_SWS 0x0000000CU /*!< SWS[1:0] bits (System Clock Switch Status) */
+#define RCC_CFGR_SWS_0 0x00000004U /*!< Bit 0 */
+#define RCC_CFGR_SWS_1 0x00000008U /*!< Bit 1 */
+
+#define RCC_CFGR_SWS_HSI 0x00000000U /*!< HSI oscillator used as system clock */
+#define RCC_CFGR_SWS_HSE 0x00000004U /*!< HSE oscillator used as system clock */
+#define RCC_CFGR_SWS_PLL 0x00000008U /*!< PLL/PLLP used as system clock */
+#define RCC_CFGR_SWS_PLLR 0x0000000CU /*!< PLL/PLLR used as system clock */
+
+/*!< HPRE configuration */
+#define RCC_CFGR_HPRE 0x000000F0U /*!< HPRE[3:0] bits (AHB prescaler) */
+#define RCC_CFGR_HPRE_0 0x00000010U /*!< Bit 0 */
+#define RCC_CFGR_HPRE_1 0x00000020U /*!< Bit 1 */
+#define RCC_CFGR_HPRE_2 0x00000040U /*!< Bit 2 */
+#define RCC_CFGR_HPRE_3 0x00000080U /*!< Bit 3 */
+
+#define RCC_CFGR_HPRE_DIV1 0x00000000U /*!< SYSCLK not divided */
+#define RCC_CFGR_HPRE_DIV2 0x00000080U /*!< SYSCLK divided by 2 */
+#define RCC_CFGR_HPRE_DIV4 0x00000090U /*!< SYSCLK divided by 4 */
+#define RCC_CFGR_HPRE_DIV8 0x000000A0U /*!< SYSCLK divided by 8 */
+#define RCC_CFGR_HPRE_DIV16 0x000000B0U /*!< SYSCLK divided by 16 */
+#define RCC_CFGR_HPRE_DIV64 0x000000C0U /*!< SYSCLK divided by 64 */
+#define RCC_CFGR_HPRE_DIV128 0x000000D0U /*!< SYSCLK divided by 128 */
+#define RCC_CFGR_HPRE_DIV256 0x000000E0U /*!< SYSCLK divided by 256 */
+#define RCC_CFGR_HPRE_DIV512 0x000000F0U /*!< SYSCLK divided by 512 */
+
+/*!< PPRE1 configuration */
+#define RCC_CFGR_PPRE1 0x00001C00U /*!< PRE1[2:0] bits (APB1 prescaler) */
+#define RCC_CFGR_PPRE1_0 0x00000400U /*!< Bit 0 */
+#define RCC_CFGR_PPRE1_1 0x00000800U /*!< Bit 1 */
+#define RCC_CFGR_PPRE1_2 0x00001000U /*!< Bit 2 */
+
+#define RCC_CFGR_PPRE1_DIV1 0x00000000U /*!< HCLK not divided */
+#define RCC_CFGR_PPRE1_DIV2 0x00001000U /*!< HCLK divided by 2 */
+#define RCC_CFGR_PPRE1_DIV4 0x00001400U /*!< HCLK divided by 4 */
+#define RCC_CFGR_PPRE1_DIV8 0x00001800U /*!< HCLK divided by 8 */
+#define RCC_CFGR_PPRE1_DIV16 0x00001C00U /*!< HCLK divided by 16 */
+
+/*!< PPRE2 configuration */
+#define RCC_CFGR_PPRE2 0x0000E000U /*!< PRE2[2:0] bits (APB2 prescaler) */
+#define RCC_CFGR_PPRE2_0 0x00002000U /*!< Bit 0 */
+#define RCC_CFGR_PPRE2_1 0x00004000U /*!< Bit 1 */
+#define RCC_CFGR_PPRE2_2 0x00008000U /*!< Bit 2 */
+
+#define RCC_CFGR_PPRE2_DIV1 0x00000000U /*!< HCLK not divided */
+#define RCC_CFGR_PPRE2_DIV2 0x00008000U /*!< HCLK divided by 2 */
+#define RCC_CFGR_PPRE2_DIV4 0x0000A000U /*!< HCLK divided by 4 */
+#define RCC_CFGR_PPRE2_DIV8 0x0000C000U /*!< HCLK divided by 8 */
+#define RCC_CFGR_PPRE2_DIV16 0x0000E000U /*!< HCLK divided by 16 */
+
+/*!< RTCPRE configuration */
+#define RCC_CFGR_RTCPRE 0x001F0000U
+#define RCC_CFGR_RTCPRE_0 0x00010000U
+#define RCC_CFGR_RTCPRE_1 0x00020000U
+#define RCC_CFGR_RTCPRE_2 0x00040000U
+#define RCC_CFGR_RTCPRE_3 0x00080000U
+#define RCC_CFGR_RTCPRE_4 0x00100000U
+
+/*!< MCO1 configuration */
+#define RCC_CFGR_MCO1 0x00600000U
+#define RCC_CFGR_MCO1_0 0x00200000U
+#define RCC_CFGR_MCO1_1 0x00400000U
+
+#define RCC_CFGR_MCO1PRE 0x07000000U
+#define RCC_CFGR_MCO1PRE_0 0x01000000U
+#define RCC_CFGR_MCO1PRE_1 0x02000000U
+#define RCC_CFGR_MCO1PRE_2 0x04000000U
+
+#define RCC_CFGR_MCO2PRE 0x38000000U
+#define RCC_CFGR_MCO2PRE_0 0x08000000U
+#define RCC_CFGR_MCO2PRE_1 0x10000000U
+#define RCC_CFGR_MCO2PRE_2 0x20000000U
+
+#define RCC_CFGR_MCO2 0xC0000000U
+#define RCC_CFGR_MCO2_0 0x40000000U
+#define RCC_CFGR_MCO2_1 0x80000000U
+
+/******************** Bit definition for RCC_CIR register *******************/
+#define RCC_CIR_LSIRDYF 0x00000001U
+#define RCC_CIR_LSERDYF 0x00000002U
+#define RCC_CIR_HSIRDYF 0x00000004U
+#define RCC_CIR_HSERDYF 0x00000008U
+#define RCC_CIR_PLLRDYF 0x00000010U
+#define RCC_CIR_PLLI2SRDYF 0x00000020U
+
+#define RCC_CIR_CSSF 0x00000080U
+#define RCC_CIR_LSIRDYIE 0x00000100U
+#define RCC_CIR_LSERDYIE 0x00000200U
+#define RCC_CIR_HSIRDYIE 0x00000400U
+#define RCC_CIR_HSERDYIE 0x00000800U
+#define RCC_CIR_PLLRDYIE 0x00001000U
+#define RCC_CIR_PLLI2SRDYIE 0x00002000U
+
+#define RCC_CIR_LSIRDYC 0x00010000U
+#define RCC_CIR_LSERDYC 0x00020000U
+#define RCC_CIR_HSIRDYC 0x00040000U
+#define RCC_CIR_HSERDYC 0x00080000U
+#define RCC_CIR_PLLRDYC 0x00100000U
+#define RCC_CIR_PLLI2SRDYC 0x00200000U
+
+#define RCC_CIR_CSSC 0x00800000U
+
+/******************** Bit definition for RCC_AHB1RSTR register **************/
+#define RCC_AHB1RSTR_GPIOARST 0x00000001U
+#define RCC_AHB1RSTR_GPIOBRST 0x00000002U
+#define RCC_AHB1RSTR_GPIOCRST 0x00000004U
+#define RCC_AHB1RSTR_GPIODRST 0x00000008U
+#define RCC_AHB1RSTR_GPIOERST 0x00000010U
+#define RCC_AHB1RSTR_GPIOFRST 0x00000020U
+#define RCC_AHB1RSTR_GPIOGRST 0x00000040U
+#define RCC_AHB1RSTR_GPIOHRST 0x00000080U
+#define RCC_AHB1RSTR_CRCRST 0x00001000U
+#define RCC_AHB1RSTR_DMA1RST 0x00200000U
+#define RCC_AHB1RSTR_DMA2RST 0x00400000U
+
+/******************** Bit definition for RCC_AHB2RSTR register **************/
+#define RCC_AHB2RSTR_RNGRST 0x00000040U
+#define RCC_AHB2RSTR_OTGFSRST 0x00000080U
+
+/******************** Bit definition for RCC_AHB3RSTR register **************/
+#define RCC_AHB3RSTR_FSMCRST 0x00000001U
+#define RCC_AHB3RSTR_QSPIRST 0x00000002U
+
+/******************** Bit definition for RCC_APB1RSTR register **************/
+#define RCC_APB1RSTR_TIM2RST 0x00000001U
+#define RCC_APB1RSTR_TIM3RST 0x00000002U
+#define RCC_APB1RSTR_TIM4RST 0x00000004U
+#define RCC_APB1RSTR_TIM5RST 0x00000008U
+#define RCC_APB1RSTR_TIM6RST 0x00000010U
+#define RCC_APB1RSTR_TIM7RST 0x00000020U
+#define RCC_APB1RSTR_TIM12RST 0x00000040U
+#define RCC_APB1RSTR_TIM13RST 0x00000080U
+#define RCC_APB1RSTR_TIM14RST 0x00000100U
+#define RCC_APB1RSTR_WWDGRST 0x00000800U
+#define RCC_APB1RSTR_SPI2RST 0x00004000U
+#define RCC_APB1RSTR_SPI3RST 0x00008000U
+#define RCC_APB1RSTR_USART2RST 0x00020000U
+#define RCC_APB1RSTR_USART3RST 0x00040000U
+#define RCC_APB1RSTR_I2C1RST 0x00200000U
+#define RCC_APB1RSTR_I2C2RST 0x00400000U
+#define RCC_APB1RSTR_I2C3RST 0x00800000U
+#define RCC_APB1RSTR_FMPI2C1RST 0x01000000U
+#define RCC_APB1RSTR_CAN1RST 0x02000000U
+#define RCC_APB1RSTR_CAN2RST 0x04000000U
+#define RCC_APB1RSTR_PWRRST 0x10000000U
+
+/******************** Bit definition for RCC_APB2RSTR register **************/
+#define RCC_APB2RSTR_TIM1RST 0x00000001U
+#define RCC_APB2RSTR_TIM8RST 0x00000002U
+#define RCC_APB2RSTR_USART1RST 0x00000010U
+#define RCC_APB2RSTR_USART6RST 0x00000020U
+#define RCC_APB2RSTR_ADCRST 0x00000100U
+#define RCC_APB2RSTR_SDIORST 0x00000800U
+#define RCC_APB2RSTR_SPI1RST 0x00001000U
+#define RCC_APB2RSTR_SPI4RST 0x00002000U
+#define RCC_APB2RSTR_SYSCFGRST 0x00004000U
+#define RCC_APB2RSTR_TIM9RST 0x00010000U
+#define RCC_APB2RSTR_TIM10RST 0x00020000U
+#define RCC_APB2RSTR_TIM11RST 0x00040000U
+#define RCC_APB2RSTR_SPI5RST 0x00100000U
+#define RCC_APB2RSTR_DFSDM1RST 0x01000000U
+
+/******************** Bit definition for RCC_AHB1ENR register ***************/
+#define RCC_AHB1ENR_GPIOAEN 0x00000001U
+#define RCC_AHB1ENR_GPIOBEN 0x00000002U
+#define RCC_AHB1ENR_GPIOCEN 0x00000004U
+#define RCC_AHB1ENR_GPIODEN 0x00000008U
+#define RCC_AHB1ENR_GPIOEEN 0x00000010U
+#define RCC_AHB1ENR_GPIOFEN 0x00000020U
+#define RCC_AHB1ENR_GPIOGEN 0x00000040U
+#define RCC_AHB1ENR_GPIOHEN 0x00000080U
+#define RCC_AHB1ENR_CRCEN 0x00001000U
+#define RCC_AHB1ENR_DMA1EN 0x00200000U
+#define RCC_AHB1ENR_DMA2EN 0x00400000U
+
+/******************** Bit definition for RCC_AHB2ENR register ***************/
+#define RCC_AHB2ENR_RNGEN 0x00000040U
+#define RCC_AHB2ENR_OTGFSEN 0x00000080U
+
+/******************** Bit definition for RCC_AHB3ENR register ***************/
+#define RCC_AHB3ENR_FSMCEN 0x00000001U
+#define RCC_AHB3ENR_QSPIEN 0x00000002U
+
+/******************** Bit definition for RCC_APB1ENR register ***************/
+#define RCC_APB1ENR_TIM2EN 0x00000001U
+#define RCC_APB1ENR_TIM3EN 0x00000002U
+#define RCC_APB1ENR_TIM4EN 0x00000004U
+#define RCC_APB1ENR_TIM5EN 0x00000008U
+#define RCC_APB1ENR_TIM6EN 0x00000010U
+#define RCC_APB1ENR_TIM7EN 0x00000020U
+#define RCC_APB1ENR_TIM12EN 0x00000040U
+#define RCC_APB1ENR_TIM13EN 0x00000080U
+#define RCC_APB1ENR_TIM14EN 0x00000100U
+#define RCC_APB1ENR_RTCAPBEN 0x00000400U
+#define RCC_APB1ENR_WWDGEN 0x00000800U
+#define RCC_APB1ENR_SPI2EN 0x00004000U
+#define RCC_APB1ENR_SPI3EN 0x00008000U
+#define RCC_APB1ENR_USART2EN 0x00020000U
+#define RCC_APB1ENR_USART3EN 0x00040000U
+#define RCC_APB1ENR_I2C1EN 0x00200000U
+#define RCC_APB1ENR_I2C2EN 0x00400000U
+#define RCC_APB1ENR_I2C3EN 0x00800000U
+#define RCC_APB1ENR_FMPI2C1EN 0x01000000U
+#define RCC_APB1ENR_CAN1EN 0x02000000U
+#define RCC_APB1ENR_CAN2EN 0x04000000U
+#define RCC_APB1ENR_PWREN 0x10000000U
+
+/******************** Bit definition for RCC_APB2ENR register ***************/
+#define RCC_APB2ENR_TIM1EN 0x00000001U
+#define RCC_APB2ENR_TIM8EN 0x00000002U
+#define RCC_APB2ENR_USART1EN 0x00000010U
+#define RCC_APB2ENR_USART6EN 0x00000020U
+#define RCC_APB2ENR_ADC1EN 0x00000100U
+#define RCC_APB2ENR_SDIOEN 0x00000800U
+#define RCC_APB2ENR_SPI1EN 0x00001000U
+#define RCC_APB2ENR_SPI4EN 0x00002000U
+#define RCC_APB2ENR_SYSCFGEN 0x00004000U
+#define RCC_APB2ENR_EXTITEN 0x00008000U
+#define RCC_APB2ENR_TIM9EN 0x00010000U
+#define RCC_APB2ENR_TIM10EN 0x00020000U
+#define RCC_APB2ENR_TIM11EN 0x00040000U
+#define RCC_APB2ENR_SPI5EN 0x00100000U
+#define RCC_APB2ENR_DFSDM1EN 0x01000000U
+/******************** Bit definition for RCC_AHB1LPENR register *************/
+#define RCC_AHB1LPENR_GPIOALPEN 0x00000001U
+#define RCC_AHB1LPENR_GPIOBLPEN 0x00000002U
+#define RCC_AHB1LPENR_GPIOCLPEN 0x00000004U
+#define RCC_AHB1LPENR_GPIODLPEN 0x00000008U
+#define RCC_AHB1LPENR_GPIOELPEN 0x00000010U
+#define RCC_AHB1LPENR_GPIOFLPEN 0x00000020U
+#define RCC_AHB1LPENR_GPIOGLPEN 0x00000040U
+#define RCC_AHB1LPENR_GPIOHLPEN 0x00000080U
+#define RCC_AHB1LPENR_CRCLPEN 0x00001000U
+#define RCC_AHB1LPENR_FLITFLPEN 0x00008000U
+#define RCC_AHB1LPENR_SRAM1LPEN 0x00010000U
+#define RCC_AHB1LPENR_DMA1LPEN 0x00200000U
+#define RCC_AHB1LPENR_DMA2LPEN 0x00400000U
+
+/******************** Bit definition for RCC_AHB2LPENR register *************/
+#define RCC_AHB2LPENR_RNGLPEN 0x00000040U
+#define RCC_AHB2LPENR_OTGFSLPEN 0x00000080U
+
+/******************** Bit definition for RCC_AHB3LPENR register *************/
+#define RCC_AHB3LPENR_FSMCLPEN 0x00000001U
+#define RCC_AHB3LPENR_QSPILPEN 0x00000002U
+
+/******************** Bit definition for RCC_APB1LPENR register *************/
+#define RCC_APB1LPENR_TIM2LPEN 0x00000001U
+#define RCC_APB1LPENR_TIM3LPEN 0x00000002U
+#define RCC_APB1LPENR_TIM4LPEN 0x00000004U
+#define RCC_APB1LPENR_TIM5LPEN 0x00000008U
+#define RCC_APB1LPENR_TIM6LPEN 0x00000010U
+#define RCC_APB1LPENR_TIM7LPEN 0x00000020U
+#define RCC_APB1LPENR_TIM12LPEN 0x00000040U
+#define RCC_APB1LPENR_TIM13LPEN 0x00000080U
+#define RCC_APB1LPENR_TIM14LPEN 0x00000100U
+#define RCC_APB1LPENR_RTCAPBLPEN 0x00000400U
+#define RCC_APB1LPENR_WWDGLPEN 0x00000800U
+#define RCC_APB1LPENR_SPI2LPEN 0x00004000U
+#define RCC_APB1LPENR_SPI3LPEN 0x00008000U
+#define RCC_APB1LPENR_USART2LPEN 0x00020000U
+#define RCC_APB1LPENR_USART3LPEN 0x00040000U
+#define RCC_APB1LPENR_I2C1LPEN 0x00200000U
+#define RCC_APB1LPENR_I2C2LPEN 0x00400000U
+#define RCC_APB1LPENR_I2C3LPEN 0x00800000U
+#define RCC_APB1LPENR_FMPI2C1LPEN 0x01000000U
+#define RCC_APB1LPENR_CAN1LPEN 0x02000000U
+#define RCC_APB1LPENR_CAN2LPEN 0x04000000U
+#define RCC_APB1LPENR_PWRLPEN 0x10000000U
+
+/******************** Bit definition for RCC_APB2LPENR register *************/
+#define RCC_APB2LPENR_TIM1LPEN 0x00000001U
+#define RCC_APB2LPENR_TIM8LPEN 0x00000002U
+#define RCC_APB2LPENR_USART1LPEN 0x00000010U
+#define RCC_APB2LPENR_USART6LPEN 0x00000020U
+#define RCC_APB2LPENR_ADC1LPEN 0x00000100U
+#define RCC_APB2LPENR_SDIOLPEN 0x00000800U
+#define RCC_APB2LPENR_SPI1LPEN 0x00001000U
+#define RCC_APB2LPENR_SPI4LPEN 0x00002000U
+#define RCC_APB2LPENR_SYSCFGLPEN 0x00004000U
+#define RCC_APB2LPENR_EXTITLPEN 0x00008000U
+#define RCC_APB2LPENR_TIM9LPEN 0x00010000U
+#define RCC_APB2LPENR_TIM10LPEN 0x00020000U
+#define RCC_APB2LPENR_TIM11LPEN 0x00040000U
+#define RCC_APB2LPENR_SPI5LPEN 0x00100000U
+#define RCC_APB2LPENR_DFSDM1LPEN 0x01000000U
+
+/******************** Bit definition for RCC_BDCR register ******************/
+#define RCC_BDCR_LSEON 0x00000001U
+#define RCC_BDCR_LSERDY 0x00000002U
+#define RCC_BDCR_LSEBYP 0x00000004U
+#define RCC_BDCR_LSEMOD 0x00000008U
+
+#define RCC_BDCR_RTCSEL 0x00000300U
+#define RCC_BDCR_RTCSEL_0 0x00000100U
+#define RCC_BDCR_RTCSEL_1 0x00000200U
+
+#define RCC_BDCR_RTCEN 0x00008000U
+#define RCC_BDCR_BDRST 0x00010000U
+
+/******************** Bit definition for RCC_CSR register *******************/
+#define RCC_CSR_LSION 0x00000001U
+#define RCC_CSR_LSIRDY 0x00000002U
+#define RCC_CSR_RMVF 0x01000000U
+#define RCC_CSR_PADRSTF 0x04000000U
+#define RCC_CSR_PORRSTF 0x08000000U
+#define RCC_CSR_SFTRSTF 0x10000000U
+#define RCC_CSR_WDGRSTF 0x20000000U
+#define RCC_CSR_WWDGRSTF 0x40000000U
+#define RCC_CSR_LPWRRSTF 0x80000000U
+
+/******************** Bit definition for RCC_SSCGR register *****************/
+#define RCC_SSCGR_MODPER 0x00001FFFU
+#define RCC_SSCGR_INCSTEP 0x0FFFE000U
+#define RCC_SSCGR_SPREADSEL 0x40000000U
+#define RCC_SSCGR_SSCGEN 0x80000000U
+
+/******************** Bit definition for RCC_PLLI2SCFGR register ************/
+#define RCC_PLLI2SCFGR_PLLI2SM 0x0000003FU
+#define RCC_PLLI2SCFGR_PLLI2SM_0 0x00000001U
+#define RCC_PLLI2SCFGR_PLLI2SM_1 0x00000002U
+#define RCC_PLLI2SCFGR_PLLI2SM_2 0x00000004U
+#define RCC_PLLI2SCFGR_PLLI2SM_3 0x00000008U
+#define RCC_PLLI2SCFGR_PLLI2SM_4 0x00000010U
+#define RCC_PLLI2SCFGR_PLLI2SM_5 0x00000020U
+
+#define RCC_PLLI2SCFGR_PLLI2SN 0x00007FC0U
+#define RCC_PLLI2SCFGR_PLLI2SN_0 0x00000040U
+#define RCC_PLLI2SCFGR_PLLI2SN_1 0x00000080U
+#define RCC_PLLI2SCFGR_PLLI2SN_2 0x00000100U
+#define RCC_PLLI2SCFGR_PLLI2SN_3 0x00000200U
+#define RCC_PLLI2SCFGR_PLLI2SN_4 0x00000400U
+#define RCC_PLLI2SCFGR_PLLI2SN_5 0x00000800U
+#define RCC_PLLI2SCFGR_PLLI2SN_6 0x00001000U
+#define RCC_PLLI2SCFGR_PLLI2SN_7 0x00002000U
+#define RCC_PLLI2SCFGR_PLLI2SN_8 0x00004000U
+
+#define RCC_PLLI2SCFGR_PLLI2SSRC 0x00400000U
+
+#define RCC_PLLI2SCFGR_PLLI2SQ 0x0F000000U
+#define RCC_PLLI2SCFGR_PLLI2SQ_0 0x01000000U
+#define RCC_PLLI2SCFGR_PLLI2SQ_1 0x02000000U
+#define RCC_PLLI2SCFGR_PLLI2SQ_2 0x04000000U
+#define RCC_PLLI2SCFGR_PLLI2SQ_3 0x08000000U
+
+#define RCC_PLLI2SCFGR_PLLI2SR 0x70000000U
+#define RCC_PLLI2SCFGR_PLLI2SR_0 0x10000000U
+#define RCC_PLLI2SCFGR_PLLI2SR_1 0x20000000U
+#define RCC_PLLI2SCFGR_PLLI2SR_2 0x40000000U
+
+/******************** Bit definition for RCC_DCKCFGR register ****************/
+#define RCC_DCKCFGR_CKDFSDM1ASEL 0x00008000U
+#define RCC_DCKCFGR_TIMPRE 0x01000000U
+
+#define RCC_DCKCFGR_I2S1SRC 0x06000000U
+#define RCC_DCKCFGR_I2S1SRC_0 0x02000000U
+#define RCC_DCKCFGR_I2S1SRC_1 0x04000000U
+
+#define RCC_DCKCFGR_I2S2SRC 0x18000000U
+#define RCC_DCKCFGR_I2S2SRC_0 0x08000000U
+#define RCC_DCKCFGR_I2S2SRC_1 0x10000000U
+
+#define RCC_DCKCFGR_CKDFSDM1SEL 0x80000000U
+
+/******************** Bit definition for RCC_CKGATENR register ***************/
+#define RCC_CKGATENR_AHB2APB1_CKEN 0x00000001U
+#define RCC_CKGATENR_AHB2APB2_CKEN 0x00000002U
+#define RCC_CKGATENR_CM4DBG_CKEN 0x00000004U
+#define RCC_CKGATENR_SPARE_CKEN 0x00000008U
+#define RCC_CKGATENR_SRAM_CKEN 0x00000010U
+#define RCC_CKGATENR_FLITF_CKEN 0x00000020U
+#define RCC_CKGATENR_RCC_CKEN 0x00000040U
+#define RCC_CKGATENR_RCC_EVTCTL 0x00000080U
+
+/******************** Bit definition for RCC_DCKCFGR2 register ***************/
+#define RCC_DCKCFGR2_FMPI2C1SEL 0x00C00000U
+#define RCC_DCKCFGR2_FMPI2C1SEL_0 0x00400000U
+#define RCC_DCKCFGR2_FMPI2C1SEL_1 0x00800000U
+
+#define RCC_DCKCFGR2_CK48MSEL 0x08000000U
+#define RCC_DCKCFGR2_SDIOSEL 0x10000000U
+
+/******************************************************************************/
+/* */
+/* RNG */
+/* */
+/******************************************************************************/
+/******************** Bits definition for RNG_CR register *******************/
+#define RNG_CR_RNGEN 0x00000004U
+#define RNG_CR_IE 0x00000008U
+
+/******************** Bits definition for RNG_SR register *******************/
+#define RNG_SR_DRDY 0x00000001U
+#define RNG_SR_CECS 0x00000002U
+#define RNG_SR_SECS 0x00000004U
+#define RNG_SR_CEIS 0x00000020U
+#define RNG_SR_SEIS 0x00000040U
+
+/******************************************************************************/
+/* */
+/* Real-Time Clock (RTC) */
+/* */
+/******************************************************************************/
+/******************** Bits definition for RTC_TR register *******************/
+#define RTC_TR_PM 0x00400000U
+#define RTC_TR_HT 0x00300000U
+#define RTC_TR_HT_0 0x00100000U
+#define RTC_TR_HT_1 0x00200000U
+#define RTC_TR_HU 0x000F0000U
+#define RTC_TR_HU_0 0x00010000U
+#define RTC_TR_HU_1 0x00020000U
+#define RTC_TR_HU_2 0x00040000U
+#define RTC_TR_HU_3 0x00080000U
+#define RTC_TR_MNT 0x00007000U
+#define RTC_TR_MNT_0 0x00001000U
+#define RTC_TR_MNT_1 0x00002000U
+#define RTC_TR_MNT_2 0x00004000U
+#define RTC_TR_MNU 0x00000F00U
+#define RTC_TR_MNU_0 0x00000100U
+#define RTC_TR_MNU_1 0x00000200U
+#define RTC_TR_MNU_2 0x00000400U
+#define RTC_TR_MNU_3 0x00000800U
+#define RTC_TR_ST 0x00000070U
+#define RTC_TR_ST_0 0x00000010U
+#define RTC_TR_ST_1 0x00000020U
+#define RTC_TR_ST_2 0x00000040U
+#define RTC_TR_SU 0x0000000FU
+#define RTC_TR_SU_0 0x00000001U
+#define RTC_TR_SU_1 0x00000002U
+#define RTC_TR_SU_2 0x00000004U
+#define RTC_TR_SU_3 0x00000008U
+
+/******************** Bits definition for RTC_DR register *******************/
+#define RTC_DR_YT 0x00F00000U
+#define RTC_DR_YT_0 0x00100000U
+#define RTC_DR_YT_1 0x00200000U
+#define RTC_DR_YT_2 0x00400000U
+#define RTC_DR_YT_3 0x00800000U
+#define RTC_DR_YU 0x000F0000U
+#define RTC_DR_YU_0 0x00010000U
+#define RTC_DR_YU_1 0x00020000U
+#define RTC_DR_YU_2 0x00040000U
+#define RTC_DR_YU_3 0x00080000U
+#define RTC_DR_WDU 0x0000E000U
+#define RTC_DR_WDU_0 0x00002000U
+#define RTC_DR_WDU_1 0x00004000U
+#define RTC_DR_WDU_2 0x00008000U
+#define RTC_DR_MT 0x00001000U
+#define RTC_DR_MU 0x00000F00U
+#define RTC_DR_MU_0 0x00000100U
+#define RTC_DR_MU_1 0x00000200U
+#define RTC_DR_MU_2 0x00000400U
+#define RTC_DR_MU_3 0x00000800U
+#define RTC_DR_DT 0x00000030U
+#define RTC_DR_DT_0 0x00000010U
+#define RTC_DR_DT_1 0x00000020U
+#define RTC_DR_DU 0x0000000FU
+#define RTC_DR_DU_0 0x00000001U
+#define RTC_DR_DU_1 0x00000002U
+#define RTC_DR_DU_2 0x00000004U
+#define RTC_DR_DU_3 0x00000008U
+
+/******************** Bits definition for RTC_CR register *******************/
+#define RTC_CR_COE 0x00800000U
+#define RTC_CR_OSEL 0x00600000U
+#define RTC_CR_OSEL_0 0x00200000U
+#define RTC_CR_OSEL_1 0x00400000U
+#define RTC_CR_POL 0x00100000U
+#define RTC_CR_COSEL 0x00080000U
+#define RTC_CR_BCK 0x00040000U
+#define RTC_CR_SUB1H 0x00020000U
+#define RTC_CR_ADD1H 0x00010000U
+#define RTC_CR_TSIE 0x00008000U
+#define RTC_CR_WUTIE 0x00004000U
+#define RTC_CR_ALRBIE 0x00002000U
+#define RTC_CR_ALRAIE 0x00001000U
+#define RTC_CR_TSE 0x00000800U
+#define RTC_CR_WUTE 0x00000400U
+#define RTC_CR_ALRBE 0x00000200U
+#define RTC_CR_ALRAE 0x00000100U
+#define RTC_CR_DCE 0x00000080U
+#define RTC_CR_FMT 0x00000040U
+#define RTC_CR_BYPSHAD 0x00000020U
+#define RTC_CR_REFCKON 0x00000010U
+#define RTC_CR_TSEDGE 0x00000008U
+#define RTC_CR_WUCKSEL 0x00000007U
+#define RTC_CR_WUCKSEL_0 0x00000001U
+#define RTC_CR_WUCKSEL_1 0x00000002U
+#define RTC_CR_WUCKSEL_2 0x00000004U
+
+/******************** Bits definition for RTC_ISR register ******************/
+#define RTC_ISR_RECALPF 0x00010000U
+#define RTC_ISR_TAMP1F 0x00002000U
+#define RTC_ISR_TAMP2F 0x00004000U
+#define RTC_ISR_TSOVF 0x00001000U
+#define RTC_ISR_TSF 0x00000800U
+#define RTC_ISR_WUTF 0x00000400U
+#define RTC_ISR_ALRBF 0x00000200U
+#define RTC_ISR_ALRAF 0x00000100U
+#define RTC_ISR_INIT 0x00000080U
+#define RTC_ISR_INITF 0x00000040U
+#define RTC_ISR_RSF 0x00000020U
+#define RTC_ISR_INITS 0x00000010U
+#define RTC_ISR_SHPF 0x00000008U
+#define RTC_ISR_WUTWF 0x00000004U
+#define RTC_ISR_ALRBWF 0x00000002U
+#define RTC_ISR_ALRAWF 0x00000001U
+
+/******************** Bits definition for RTC_PRER register *****************/
+#define RTC_PRER_PREDIV_A 0x007F0000U
+#define RTC_PRER_PREDIV_S 0x00007FFFU
+
+/******************** Bits definition for RTC_WUTR register *****************/
+#define RTC_WUTR_WUT 0x0000FFFFU
+
+/******************** Bits definition for RTC_CALIBR register ***************/
+#define RTC_CALIBR_DCS 0x00000080U
+#define RTC_CALIBR_DC 0x0000001FU
+
+/******************** Bits definition for RTC_ALRMAR register ***************/
+#define RTC_ALRMAR_MSK4 0x80000000U
+#define RTC_ALRMAR_WDSEL 0x40000000U
+#define RTC_ALRMAR_DT 0x30000000U
+#define RTC_ALRMAR_DT_0 0x10000000U
+#define RTC_ALRMAR_DT_1 0x20000000U
+#define RTC_ALRMAR_DU 0x0F000000U
+#define RTC_ALRMAR_DU_0 0x01000000U
+#define RTC_ALRMAR_DU_1 0x02000000U
+#define RTC_ALRMAR_DU_2 0x04000000U
+#define RTC_ALRMAR_DU_3 0x08000000U
+#define RTC_ALRMAR_MSK3 0x00800000U
+#define RTC_ALRMAR_PM 0x00400000U
+#define RTC_ALRMAR_HT 0x00300000U
+#define RTC_ALRMAR_HT_0 0x00100000U
+#define RTC_ALRMAR_HT_1 0x00200000U
+#define RTC_ALRMAR_HU 0x000F0000U
+#define RTC_ALRMAR_HU_0 0x00010000U
+#define RTC_ALRMAR_HU_1 0x00020000U
+#define RTC_ALRMAR_HU_2 0x00040000U
+#define RTC_ALRMAR_HU_3 0x00080000U
+#define RTC_ALRMAR_MSK2 0x00008000U
+#define RTC_ALRMAR_MNT 0x00007000U
+#define RTC_ALRMAR_MNT_0 0x00001000U
+#define RTC_ALRMAR_MNT_1 0x00002000U
+#define RTC_ALRMAR_MNT_2 0x00004000U
+#define RTC_ALRMAR_MNU 0x00000F00U
+#define RTC_ALRMAR_MNU_0 0x00000100U
+#define RTC_ALRMAR_MNU_1 0x00000200U
+#define RTC_ALRMAR_MNU_2 0x00000400U
+#define RTC_ALRMAR_MNU_3 0x00000800U
+#define RTC_ALRMAR_MSK1 0x00000080U
+#define RTC_ALRMAR_ST 0x00000070U
+#define RTC_ALRMAR_ST_0 0x00000010U
+#define RTC_ALRMAR_ST_1 0x00000020U
+#define RTC_ALRMAR_ST_2 0x00000040U
+#define RTC_ALRMAR_SU 0x0000000FU
+#define RTC_ALRMAR_SU_0 0x00000001U
+#define RTC_ALRMAR_SU_1 0x00000002U
+#define RTC_ALRMAR_SU_2 0x00000004U
+#define RTC_ALRMAR_SU_3 0x00000008U
+
+/******************** Bits definition for RTC_ALRMBR register ***************/
+#define RTC_ALRMBR_MSK4 0x80000000U
+#define RTC_ALRMBR_WDSEL 0x40000000U
+#define RTC_ALRMBR_DT 0x30000000U
+#define RTC_ALRMBR_DT_0 0x10000000U
+#define RTC_ALRMBR_DT_1 0x20000000U
+#define RTC_ALRMBR_DU 0x0F000000U
+#define RTC_ALRMBR_DU_0 0x01000000U
+#define RTC_ALRMBR_DU_1 0x02000000U
+#define RTC_ALRMBR_DU_2 0x04000000U
+#define RTC_ALRMBR_DU_3 0x08000000U
+#define RTC_ALRMBR_MSK3 0x00800000U
+#define RTC_ALRMBR_PM 0x00400000U
+#define RTC_ALRMBR_HT 0x00300000U
+#define RTC_ALRMBR_HT_0 0x00100000U
+#define RTC_ALRMBR_HT_1 0x00200000U
+#define RTC_ALRMBR_HU 0x000F0000U
+#define RTC_ALRMBR_HU_0 0x00010000U
+#define RTC_ALRMBR_HU_1 0x00020000U
+#define RTC_ALRMBR_HU_2 0x00040000U
+#define RTC_ALRMBR_HU_3 0x00080000U
+#define RTC_ALRMBR_MSK2 0x00008000U
+#define RTC_ALRMBR_MNT 0x00007000U
+#define RTC_ALRMBR_MNT_0 0x00001000U
+#define RTC_ALRMBR_MNT_1 0x00002000U
+#define RTC_ALRMBR_MNT_2 0x00004000U
+#define RTC_ALRMBR_MNU 0x00000F00U
+#define RTC_ALRMBR_MNU_0 0x00000100U
+#define RTC_ALRMBR_MNU_1 0x00000200U
+#define RTC_ALRMBR_MNU_2 0x00000400U
+#define RTC_ALRMBR_MNU_3 0x00000800U
+#define RTC_ALRMBR_MSK1 0x00000080U
+#define RTC_ALRMBR_ST 0x00000070U
+#define RTC_ALRMBR_ST_0 0x00000010U
+#define RTC_ALRMBR_ST_1 0x00000020U
+#define RTC_ALRMBR_ST_2 0x00000040U
+#define RTC_ALRMBR_SU 0x0000000FU
+#define RTC_ALRMBR_SU_0 0x00000001U
+#define RTC_ALRMBR_SU_1 0x00000002U
+#define RTC_ALRMBR_SU_2 0x00000004U
+#define RTC_ALRMBR_SU_3 0x00000008U
+
+/******************** Bits definition for RTC_WPR register ******************/
+#define RTC_WPR_KEY 0x000000FFU
+
+/******************** Bits definition for RTC_SSR register ******************/
+#define RTC_SSR_SS 0x0000FFFFU
+
+/******************** Bits definition for RTC_SHIFTR register ***************/
+#define RTC_SHIFTR_SUBFS 0x00007FFFU
+#define RTC_SHIFTR_ADD1S 0x80000000U
+
+/******************** Bits definition for RTC_TSTR register *****************/
+#define RTC_TSTR_PM 0x00400000U
+#define RTC_TSTR_HT 0x00300000U
+#define RTC_TSTR_HT_0 0x00100000U
+#define RTC_TSTR_HT_1 0x00200000U
+#define RTC_TSTR_HU 0x000F0000U
+#define RTC_TSTR_HU_0 0x00010000U
+#define RTC_TSTR_HU_1 0x00020000U
+#define RTC_TSTR_HU_2 0x00040000U
+#define RTC_TSTR_HU_3 0x00080000U
+#define RTC_TSTR_MNT 0x00007000U
+#define RTC_TSTR_MNT_0 0x00001000U
+#define RTC_TSTR_MNT_1 0x00002000U
+#define RTC_TSTR_MNT_2 0x00004000U
+#define RTC_TSTR_MNU 0x00000F00U
+#define RTC_TSTR_MNU_0 0x00000100U
+#define RTC_TSTR_MNU_1 0x00000200U
+#define RTC_TSTR_MNU_2 0x00000400U
+#define RTC_TSTR_MNU_3 0x00000800U
+#define RTC_TSTR_ST 0x00000070U
+#define RTC_TSTR_ST_0 0x00000010U
+#define RTC_TSTR_ST_1 0x00000020U
+#define RTC_TSTR_ST_2 0x00000040U
+#define RTC_TSTR_SU 0x0000000FU
+#define RTC_TSTR_SU_0 0x00000001U
+#define RTC_TSTR_SU_1 0x00000002U
+#define RTC_TSTR_SU_2 0x00000004U
+#define RTC_TSTR_SU_3 0x00000008U
+
+/******************** Bits definition for RTC_TSDR register *****************/
+#define RTC_TSDR_WDU 0x0000E000U
+#define RTC_TSDR_WDU_0 0x00002000U
+#define RTC_TSDR_WDU_1 0x00004000U
+#define RTC_TSDR_WDU_2 0x00008000U
+#define RTC_TSDR_MT 0x00001000U
+#define RTC_TSDR_MU 0x00000F00U
+#define RTC_TSDR_MU_0 0x00000100U
+#define RTC_TSDR_MU_1 0x00000200U
+#define RTC_TSDR_MU_2 0x00000400U
+#define RTC_TSDR_MU_3 0x00000800U
+#define RTC_TSDR_DT 0x00000030U
+#define RTC_TSDR_DT_0 0x00000010U
+#define RTC_TSDR_DT_1 0x00000020U
+#define RTC_TSDR_DU 0x0000000FU
+#define RTC_TSDR_DU_0 0x00000001U
+#define RTC_TSDR_DU_1 0x00000002U
+#define RTC_TSDR_DU_2 0x00000004U
+#define RTC_TSDR_DU_3 0x00000008U
+
+/******************** Bits definition for RTC_TSSSR register ****************/
+#define RTC_TSSSR_SS 0x0000FFFFU
+
+/******************** Bits definition for RTC_CAL register *****************/
+#define RTC_CALR_CALP 0x00008000U
+#define RTC_CALR_CALW8 0x00004000U
+#define RTC_CALR_CALW16 0x00002000U
+#define RTC_CALR_CALM 0x000001FFU
+#define RTC_CALR_CALM_0 0x00000001U
+#define RTC_CALR_CALM_1 0x00000002U
+#define RTC_CALR_CALM_2 0x00000004U
+#define RTC_CALR_CALM_3 0x00000008U
+#define RTC_CALR_CALM_4 0x00000010U
+#define RTC_CALR_CALM_5 0x00000020U
+#define RTC_CALR_CALM_6 0x00000040U
+#define RTC_CALR_CALM_7 0x00000080U
+#define RTC_CALR_CALM_8 0x00000100U
+
+/******************** Bits definition for RTC_TAFCR register ****************/
+#define RTC_TAFCR_ALARMOUTTYPE 0x00040000U
+#define RTC_TAFCR_TSINSEL 0x00020000U
+#define RTC_TAFCR_TAMPINSEL 0x00010000U
+#define RTC_TAFCR_TAMPPUDIS 0x00008000U
+#define RTC_TAFCR_TAMPPRCH 0x00006000U
+#define RTC_TAFCR_TAMPPRCH_0 0x00002000U
+#define RTC_TAFCR_TAMPPRCH_1 0x00004000U
+#define RTC_TAFCR_TAMPFLT 0x00001800U
+#define RTC_TAFCR_TAMPFLT_0 0x00000800U
+#define RTC_TAFCR_TAMPFLT_1 0x00001000U
+#define RTC_TAFCR_TAMPFREQ 0x00000700U
+#define RTC_TAFCR_TAMPFREQ_0 0x00000100U
+#define RTC_TAFCR_TAMPFREQ_1 0x00000200U
+#define RTC_TAFCR_TAMPFREQ_2 0x00000400U
+#define RTC_TAFCR_TAMPTS 0x00000080U
+#define RTC_TAFCR_TAMP2TRG 0x00000010U
+#define RTC_TAFCR_TAMP2E 0x00000008U
+#define RTC_TAFCR_TAMPIE 0x00000004U
+#define RTC_TAFCR_TAMP1TRG 0x00000002U
+#define RTC_TAFCR_TAMP1E 0x00000001U
+
+/******************** Bits definition for RTC_ALRMASSR register *************/
+#define RTC_ALRMASSR_MASKSS 0x0F000000U
+#define RTC_ALRMASSR_MASKSS_0 0x01000000U
+#define RTC_ALRMASSR_MASKSS_1 0x02000000U
+#define RTC_ALRMASSR_MASKSS_2 0x04000000U
+#define RTC_ALRMASSR_MASKSS_3 0x08000000U
+#define RTC_ALRMASSR_SS 0x00007FFFU
+
+/******************** Bits definition for RTC_ALRMBSSR register *************/
+#define RTC_ALRMBSSR_MASKSS 0x0F000000U
+#define RTC_ALRMBSSR_MASKSS_0 0x01000000U
+#define RTC_ALRMBSSR_MASKSS_1 0x02000000U
+#define RTC_ALRMBSSR_MASKSS_2 0x04000000U
+#define RTC_ALRMBSSR_MASKSS_3 0x08000000U
+#define RTC_ALRMBSSR_SS 0x00007FFFU
+
+/******************** Bits definition for RTC_BKP0R register ****************/
+#define RTC_BKP0R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP1R register ****************/
+#define RTC_BKP1R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP2R register ****************/
+#define RTC_BKP2R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP3R register ****************/
+#define RTC_BKP3R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP4R register ****************/
+#define RTC_BKP4R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP5R register ****************/
+#define RTC_BKP5R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP6R register ****************/
+#define RTC_BKP6R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP7R register ****************/
+#define RTC_BKP7R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP8R register ****************/
+#define RTC_BKP8R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP9R register ****************/
+#define RTC_BKP9R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP10R register ***************/
+#define RTC_BKP10R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP11R register ***************/
+#define RTC_BKP11R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP12R register ***************/
+#define RTC_BKP12R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP13R register ***************/
+#define RTC_BKP13R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP14R register ***************/
+#define RTC_BKP14R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP15R register ***************/
+#define RTC_BKP15R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP16R register ***************/
+#define RTC_BKP16R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP17R register ***************/
+#define RTC_BKP17R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP18R register ***************/
+#define RTC_BKP18R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP19R register ***************/
+#define RTC_BKP19R 0xFFFFFFFFU
+
+
+
+/******************************************************************************/
+/* */
+/* SD host Interface */
+/* */
+/******************************************************************************/
+/****************** Bit definition for SDIO_POWER register ******************/
+#define SDIO_POWER_PWRCTRL 0x03U /*!<PWRCTRL[1:0] bits (Power supply control bits) */
+#define SDIO_POWER_PWRCTRL_0 0x01U /*!<Bit 0 */
+#define SDIO_POWER_PWRCTRL_1 0x02U /*!<Bit 1 */
+
+/****************** Bit definition for SDIO_CLKCR register ******************/
+#define SDIO_CLKCR_CLKDIV 0x00FFU /*!<Clock divide factor */
+#define SDIO_CLKCR_CLKEN 0x0100U /*!<Clock enable bit */
+#define SDIO_CLKCR_PWRSAV 0x0200U /*!<Power saving configuration bit */
+#define SDIO_CLKCR_BYPASS 0x0400U /*!<Clock divider bypass enable bit */
+
+#define SDIO_CLKCR_WIDBUS 0x1800U /*!<WIDBUS[1:0] bits (Wide bus mode enable bit) */
+#define SDIO_CLKCR_WIDBUS_0 0x0800U /*!<Bit 0 */
+#define SDIO_CLKCR_WIDBUS_1 0x1000U /*!<Bit 1 */
+
+#define SDIO_CLKCR_NEGEDGE 0x2000U /*!<SDIO_CK dephasing selection bit */
+#define SDIO_CLKCR_HWFC_EN 0x4000U /*!<HW Flow Control enable */
+
+/******************* Bit definition for SDIO_ARG register *******************/
+#define SDIO_ARG_CMDARG 0xFFFFFFFFU /*!<Command argument */
+
+/******************* Bit definition for SDIO_CMD register *******************/
+#define SDIO_CMD_CMDINDEX 0x003FU /*!<Command Index */
+
+#define SDIO_CMD_WAITRESP 0x00C0U /*!<WAITRESP[1:0] bits (Wait for response bits) */
+#define SDIO_CMD_WAITRESP_0 0x0040U /*!< Bit 0 */
+#define SDIO_CMD_WAITRESP_1 0x0080U /*!< Bit 1 */
+
+#define SDIO_CMD_WAITINT 0x0100U /*!<CPSM Waits for Interrupt Request */
+#define SDIO_CMD_WAITPEND 0x0200U /*!<CPSM Waits for ends of data transfer (CmdPend internal signal) */
+#define SDIO_CMD_CPSMEN 0x0400U /*!<Command path state machine (CPSM) Enable bit */
+#define SDIO_CMD_SDIOSUSPEND 0x0800U /*!<SD I/O suspend command */
+#define SDIO_CMD_ENCMDCOMPL 0x1000U /*!<Enable CMD completion */
+#define SDIO_CMD_NIEN 0x2000U /*!<Not Interrupt Enable */
+#define SDIO_CMD_CEATACMD 0x4000U /*!<CE-ATA command */
+
+/***************** Bit definition for SDIO_RESPCMD register *****************/
+#define SDIO_RESPCMD_RESPCMD 0x3FU /*!<Response command index */
+
+/****************** Bit definition for SDIO_RESP0 register ******************/
+#define SDIO_RESP0_CARDSTATUS0 0xFFFFFFFFU /*!<Card Status */
+
+/****************** Bit definition for SDIO_RESP1 register ******************/
+#define SDIO_RESP1_CARDSTATUS1 0xFFFFFFFFU /*!<Card Status */
+
+/****************** Bit definition for SDIO_RESP2 register ******************/
+#define SDIO_RESP2_CARDSTATUS2 0xFFFFFFFFU /*!<Card Status */
+
+/****************** Bit definition for SDIO_RESP3 register ******************/
+#define SDIO_RESP3_CARDSTATUS3 0xFFFFFFFFU /*!<Card Status */
+
+/****************** Bit definition for SDIO_RESP4 register ******************/
+#define SDIO_RESP4_CARDSTATUS4 0xFFFFFFFFU /*!<Card Status */
+
+/****************** Bit definition for SDIO_DTIMER register *****************/
+#define SDIO_DTIMER_DATATIME 0xFFFFFFFFU /*!<Data timeout period. */
+
+/****************** Bit definition for SDIO_DLEN register *******************/
+#define SDIO_DLEN_DATALENGTH 0x01FFFFFFU /*!<Data length value */
+
+/****************** Bit definition for SDIO_DCTRL register ******************/
+#define SDIO_DCTRL_DTEN 0x0001U /*!<Data transfer enabled bit */
+#define SDIO_DCTRL_DTDIR 0x0002U /*!<Data transfer direction selection */
+#define SDIO_DCTRL_DTMODE 0x0004U /*!<Data transfer mode selection */
+#define SDIO_DCTRL_DMAEN 0x0008U /*!<DMA enabled bit */
+
+#define SDIO_DCTRL_DBLOCKSIZE 0x00F0U /*!<DBLOCKSIZE[3:0] bits (Data block size) */
+#define SDIO_DCTRL_DBLOCKSIZE_0 0x0010U /*!<Bit 0 */
+#define SDIO_DCTRL_DBLOCKSIZE_1 0x0020U /*!<Bit 1 */
+#define SDIO_DCTRL_DBLOCKSIZE_2 0x0040U /*!<Bit 2 */
+#define SDIO_DCTRL_DBLOCKSIZE_3 0x0080U /*!<Bit 3 */
+
+#define SDIO_DCTRL_RWSTART 0x0100U /*!<Read wait start */
+#define SDIO_DCTRL_RWSTOP 0x0200U /*!<Read wait stop */
+#define SDIO_DCTRL_RWMOD 0x0400U /*!<Read wait mode */
+#define SDIO_DCTRL_SDIOEN 0x0800U /*!<SD I/O enable functions */
+
+/****************** Bit definition for SDIO_DCOUNT register *****************/
+#define SDIO_DCOUNT_DATACOUNT 0x01FFFFFFU /*!<Data count value */
+
+/****************** Bit definition for SDIO_STA register ********************/
+#define SDIO_STA_CCRCFAIL 0x00000001U /*!<Command response received (CRC check failed) */
+#define SDIO_STA_DCRCFAIL 0x00000002U /*!<Data block sent/received (CRC check failed) */
+#define SDIO_STA_CTIMEOUT 0x00000004U /*!<Command response timeout */
+#define SDIO_STA_DTIMEOUT 0x00000008U /*!<Data timeout */
+#define SDIO_STA_TXUNDERR 0x00000010U /*!<Transmit FIFO underrun error */
+#define SDIO_STA_RXOVERR 0x00000020U /*!<Received FIFO overrun error */
+#define SDIO_STA_CMDREND 0x00000040U /*!<Command response received (CRC check passed) */
+#define SDIO_STA_CMDSENT 0x00000080U /*!<Command sent (no response required) */
+#define SDIO_STA_DATAEND 0x00000100U /*!<Data end (data counter, SDIDCOUNT, is zero) */
+#define SDIO_STA_STBITERR 0x00000200U /*!<Start bit not detected on all data signals in wide bus mode */
+#define SDIO_STA_DBCKEND 0x00000400U /*!<Data block sent/received (CRC check passed) */
+#define SDIO_STA_CMDACT 0x00000800U /*!<Command transfer in progress */
+#define SDIO_STA_TXACT 0x00001000U /*!<Data transmit in progress */
+#define SDIO_STA_RXACT 0x00002000U /*!<Data receive in progress */
+#define SDIO_STA_TXFIFOHE 0x00004000U /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
+#define SDIO_STA_RXFIFOHF 0x00008000U /*!<Receive FIFO Half Full: there are at least 8 words in the FIFO */
+#define SDIO_STA_TXFIFOF 0x00010000U /*!<Transmit FIFO full */
+#define SDIO_STA_RXFIFOF 0x00020000U /*!<Receive FIFO full */
+#define SDIO_STA_TXFIFOE 0x00040000U /*!<Transmit FIFO empty */
+#define SDIO_STA_RXFIFOE 0x00080000U /*!<Receive FIFO empty */
+#define SDIO_STA_TXDAVL 0x00100000U /*!<Data available in transmit FIFO */
+#define SDIO_STA_RXDAVL 0x00200000U /*!<Data available in receive FIFO */
+#define SDIO_STA_SDIOIT 0x00400000U /*!<SDIO interrupt received */
+#define SDIO_STA_CEATAEND 0x00800000U /*!<CE-ATA command completion signal received for CMD61 */
+
+/******************* Bit definition for SDIO_ICR register *******************/
+#define SDIO_ICR_CCRCFAILC 0x00000001U /*!<CCRCFAIL flag clear bit */
+#define SDIO_ICR_DCRCFAILC 0x00000002U /*!<DCRCFAIL flag clear bit */
+#define SDIO_ICR_CTIMEOUTC 0x00000004U /*!<CTIMEOUT flag clear bit */
+#define SDIO_ICR_DTIMEOUTC 0x00000008U /*!<DTIMEOUT flag clear bit */
+#define SDIO_ICR_TXUNDERRC 0x00000010U /*!<TXUNDERR flag clear bit */
+#define SDIO_ICR_RXOVERRC 0x00000020U /*!<RXOVERR flag clear bit */
+#define SDIO_ICR_CMDRENDC 0x00000040U /*!<CMDREND flag clear bit */
+#define SDIO_ICR_CMDSENTC 0x00000080U /*!<CMDSENT flag clear bit */
+#define SDIO_ICR_DATAENDC 0x00000100U /*!<DATAEND flag clear bit */
+#define SDIO_ICR_STBITERRC 0x00000200U /*!<STBITERR flag clear bit */
+#define SDIO_ICR_DBCKENDC 0x00000400U /*!<DBCKEND flag clear bit */
+#define SDIO_ICR_SDIOITC 0x00400000U /*!<SDIOIT flag clear bit */
+#define SDIO_ICR_CEATAENDC 0x00800000U /*!<CEATAEND flag clear bit */
+
+/****************** Bit definition for SDIO_MASK register *******************/
+#define SDIO_MASK_CCRCFAILIE 0x00000001U /*!<Command CRC Fail Interrupt Enable */
+#define SDIO_MASK_DCRCFAILIE 0x00000002U /*!<Data CRC Fail Interrupt Enable */
+#define SDIO_MASK_CTIMEOUTIE 0x00000004U /*!<Command TimeOut Interrupt Enable */
+#define SDIO_MASK_DTIMEOUTIE 0x00000008U /*!<Data TimeOut Interrupt Enable */
+#define SDIO_MASK_TXUNDERRIE 0x00000010U /*!<Tx FIFO UnderRun Error Interrupt Enable */
+#define SDIO_MASK_RXOVERRIE 0x00000020U /*!<Rx FIFO OverRun Error Interrupt Enable */
+#define SDIO_MASK_CMDRENDIE 0x00000040U /*!<Command Response Received Interrupt Enable */
+#define SDIO_MASK_CMDSENTIE 0x00000080U /*!<Command Sent Interrupt Enable */
+#define SDIO_MASK_DATAENDIE 0x00000100U /*!<Data End Interrupt Enable */
+#define SDIO_MASK_STBITERRIE 0x00000200U /*!<Start Bit Error Interrupt Enable */
+#define SDIO_MASK_DBCKENDIE 0x00000400U /*!<Data Block End Interrupt Enable */
+#define SDIO_MASK_CMDACTIE 0x00000800U /*!<CCommand Acting Interrupt Enable */
+#define SDIO_MASK_TXACTIE 0x00001000U /*!<Data Transmit Acting Interrupt Enable */
+#define SDIO_MASK_RXACTIE 0x00002000U /*!<Data receive acting interrupt enabled */
+#define SDIO_MASK_TXFIFOHEIE 0x00004000U /*!<Tx FIFO Half Empty interrupt Enable */
+#define SDIO_MASK_RXFIFOHFIE 0x00008000U /*!<Rx FIFO Half Full interrupt Enable */
+#define SDIO_MASK_TXFIFOFIE 0x00010000U /*!<Tx FIFO Full interrupt Enable */
+#define SDIO_MASK_RXFIFOFIE 0x00020000U /*!<Rx FIFO Full interrupt Enable */
+#define SDIO_MASK_TXFIFOEIE 0x00040000U /*!<Tx FIFO Empty interrupt Enable */
+#define SDIO_MASK_RXFIFOEIE 0x00080000U /*!<Rx FIFO Empty interrupt Enable */
+#define SDIO_MASK_TXDAVLIE 0x00100000U /*!<Data available in Tx FIFO interrupt Enable */
+#define SDIO_MASK_RXDAVLIE 0x00200000U /*!<Data available in Rx FIFO interrupt Enable */
+#define SDIO_MASK_SDIOITIE 0x00400000U /*!<SDIO Mode Interrupt Received interrupt Enable */
+#define SDIO_MASK_CEATAENDIE 0x00800000U /*!<CE-ATA command completion signal received Interrupt Enable */
+
+/***************** Bit definition for SDIO_FIFOCNT register *****************/
+#define SDIO_FIFOCNT_FIFOCOUNT 0x00FFFFFFU /*!<Remaining number of words to be written to or read from the FIFO */
+
+/****************** Bit definition for SDIO_FIFO register *******************/
+#define SDIO_FIFO_FIFODATA 0xFFFFFFFFU /*!<Receive and transmit FIFO data */
+
+/******************************************************************************/
+/* */
+/* Serial Peripheral Interface */
+/* */
+/******************************************************************************/
+/******************* Bit definition for SPI_CR1 register ********************/
+#define SPI_CR1_CPHA 0x00000001U /*!<Clock Phase */
+#define SPI_CR1_CPOL 0x00000002U /*!<Clock Polarity */
+#define SPI_CR1_MSTR 0x00000004U /*!<Master Selection */
+
+#define SPI_CR1_BR 0x00000038U /*!<BR[2:0] bits (Baud Rate Control) */
+#define SPI_CR1_BR_0 0x00000008U /*!<Bit 0 */
+#define SPI_CR1_BR_1 0x00000010U /*!<Bit 1 */
+#define SPI_CR1_BR_2 0x00000020U /*!<Bit 2 */
+
+#define SPI_CR1_SPE 0x00000040U /*!<SPI Enable */
+#define SPI_CR1_LSBFIRST 0x00000080U /*!<Frame Format */
+#define SPI_CR1_SSI 0x00000100U /*!<Internal slave select */
+#define SPI_CR1_SSM 0x00000200U /*!<Software slave management */
+#define SPI_CR1_RXONLY 0x00000400U /*!<Receive only */
+#define SPI_CR1_DFF 0x00000800U /*!<Data Frame Format */
+#define SPI_CR1_CRCNEXT 0x00001000U /*!<Transmit CRC next */
+#define SPI_CR1_CRCEN 0x00002000U /*!<Hardware CRC calculation enable */
+#define SPI_CR1_BIDIOE 0x00004000U /*!<Output enable in bidirectional mode */
+#define SPI_CR1_BIDIMODE 0x00008000U /*!<Bidirectional data mode enable */
+
+/******************* Bit definition for SPI_CR2 register ********************/
+#define SPI_CR2_RXDMAEN 0x00000001U /*!<Rx Buffer DMA Enable */
+#define SPI_CR2_TXDMAEN 0x00000002U /*!<Tx Buffer DMA Enable */
+#define SPI_CR2_SSOE 0x00000004U /*!<SS Output Enable */
+#define SPI_CR2_FRF 0x00000010U /*!<Frame Format */
+#define SPI_CR2_ERRIE 0x00000020U /*!<Error Interrupt Enable */
+#define SPI_CR2_RXNEIE 0x00000040U /*!<RX buffer Not Empty Interrupt Enable */
+#define SPI_CR2_TXEIE 0x00000080U /*!<Tx buffer Empty Interrupt Enable */
+
+/******************** Bit definition for SPI_SR register ********************/
+#define SPI_SR_RXNE 0x00000001U /*!<Receive buffer Not Empty */
+#define SPI_SR_TXE 0x00000002U /*!<Transmit buffer Empty */
+#define SPI_SR_CHSIDE 0x00000004U /*!<Channel side */
+#define SPI_SR_UDR 0x00000008U /*!<Underrun flag */
+#define SPI_SR_CRCERR 0x00000010U /*!<CRC Error flag */
+#define SPI_SR_MODF 0x00000020U /*!<Mode fault */
+#define SPI_SR_OVR 0x00000040U /*!<Overrun flag */
+#define SPI_SR_BSY 0x00000080U /*!<Busy flag */
+#define SPI_SR_FRE 0x00000100U /*!<Frame format error flag */
+
+/******************** Bit definition for SPI_DR register ********************/
+#define SPI_DR_DR 0x0000FFFFU /*!<Data Register */
+
+/******************* Bit definition for SPI_CRCPR register ******************/
+#define SPI_CRCPR_CRCPOLY 0x0000FFFFU /*!<CRC polynomial register */
+
+/****************** Bit definition for SPI_RXCRCR register ******************/
+#define SPI_RXCRCR_RXCRC 0x0000FFFFU /*!<Rx CRC Register */
+
+/****************** Bit definition for SPI_TXCRCR register ******************/
+#define SPI_TXCRCR_TXCRC 0x0000FFFFU /*!<Tx CRC Register */
+
+/****************** Bit definition for SPI_I2SCFGR register *****************/
+#define SPI_I2SCFGR_CHLEN 0x00000001U /*!<Channel length (number of bits per audio channel) */
+
+#define SPI_I2SCFGR_DATLEN 0x00000006U /*!<DATLEN[1:0] bits (Data length to be transferred) */
+#define SPI_I2SCFGR_DATLEN_0 0x00000002U /*!<Bit 0 */
+#define SPI_I2SCFGR_DATLEN_1 0x00000004U /*!<Bit 1 */
+
+#define SPI_I2SCFGR_CKPOL 0x00000008U /*!<steady state clock polarity */
+
+#define SPI_I2SCFGR_I2SSTD 0x00000030U /*!<I2SSTD[1:0] bits (I2S standard selection) */
+#define SPI_I2SCFGR_I2SSTD_0 0x00000010U /*!<Bit 0 */
+#define SPI_I2SCFGR_I2SSTD_1 0x00000020U /*!<Bit 1 */
+
+#define SPI_I2SCFGR_PCMSYNC 0x00000080U /*!<PCM frame synchronization */
+
+#define SPI_I2SCFGR_I2SCFG 0x00000300U /*!<I2SCFG[1:0] bits (I2S configuration mode) */
+#define SPI_I2SCFGR_I2SCFG_0 0x00000100U /*!<Bit 0 */
+#define SPI_I2SCFGR_I2SCFG_1 0x00000200U /*!<Bit 1 */
+
+#define SPI_I2SCFGR_I2SE 0x00000400U /*!<I2S Enable */
+#define SPI_I2SCFGR_I2SMOD 0x00000800U /*!<I2S mode selection */
+
+/****************** Bit definition for SPI_I2SPR register *******************/
+#define SPI_I2SPR_I2SDIV 0x000000FFU /*!<I2S Linear prescaler */
+#define SPI_I2SPR_ODD 0x00000100U /*!<Odd factor for the prescaler */
+#define SPI_I2SPR_MCKOE 0x00000200U /*!<Master Clock Output Enable */
+
+/******************************************************************************/
+/* */
+/* SYSCFG */
+/* */
+/******************************************************************************/
+/****************** Bit definition for SYSCFG_MEMRMP register ***************/
+#define SYSCFG_MEMRMP_MEM_MODE 0x00000007U /*!< SYSCFG_Memory Remap Config */
+#define SYSCFG_MEMRMP_MEM_MODE_0 0x00000001U
+#define SYSCFG_MEMRMP_MEM_MODE_1 0x00000002U
+#define SYSCFG_MEMRMP_MEM_MODE_2 0x00000004U
+
+#define SYSCFG_SWP_FSMC 0x00000C00U /*!< FSMC memory mapping swap */
+/****************** Bit definition for SYSCFG_PMC register ******************/
+#define SYSCFG_PMC_ADC1DC2 0x00010000U /*!< Refer to AN4073 on how to use this bit */
+
+/***************** Bit definition for SYSCFG_EXTICR1 register ***************/
+#define SYSCFG_EXTICR1_EXTI0 0x000FU /*!<EXTI 0 configuration */
+#define SYSCFG_EXTICR1_EXTI1 0x00F0U /*!<EXTI 1 configuration */
+#define SYSCFG_EXTICR1_EXTI2 0x0F00U /*!<EXTI 2 configuration */
+#define SYSCFG_EXTICR1_EXTI3 0xF000U /*!<EXTI 3 configuration */
+/**
+ * @brief EXTI0 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI0_PA 0x0000U /*!<PA[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PB 0x0001U /*!<PB[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PC 0x0002U /*!<PC[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PD 0x0003U /*!<PD[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PE 0x0004U /*!<PE[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PF 0x0005U /*!<PE[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PG 0x0006U /*!<PE[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PH 0x0007U /*!<PH[0] pin */
+
+/**
+ * @brief EXTI1 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI1_PA 0x0000U /*!<PA[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PB 0x0010U /*!<PB[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PC 0x0020U /*!<PC[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PD 0x0030U /*!<PD[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PE 0x0040U /*!<PE[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PF 0x0050U /*!<PD[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PG 0x0060U /*!<PE[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PH 0x0070U /*!<PH[1] pin */
+
+/**
+ * @brief EXTI2 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI2_PA 0x0000U /*!<PA[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PB 0x0100U /*!<PB[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PC 0x0200U /*!<PC[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PD 0x0300U /*!<PD[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PE 0x0400U /*!<PE[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PF 0x0500U /*!<PE[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PG 0x0600U /*!<PE[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PH 0x0700U /*!<PH[2] pin */
+
+/**
+ * @brief EXTI3 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI3_PA 0x0000U /*!<PA[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PB 0x1000U /*!<PB[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PC 0x2000U /*!<PC[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PD 0x3000U /*!<PD[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PE 0x4000U /*!<PE[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PF 0x5000U /*!<PE[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PG 0x6000U /*!<PE[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PH 0x7000U /*!<PH[3] pin */
+
+/***************** Bit definition for SYSCFG_EXTICR2 register ***************/
+#define SYSCFG_EXTICR2_EXTI4 0x000FU /*!<EXTI 4 configuration */
+#define SYSCFG_EXTICR2_EXTI5 0x00F0U /*!<EXTI 5 configuration */
+#define SYSCFG_EXTICR2_EXTI6 0x0F00U /*!<EXTI 6 configuration */
+#define SYSCFG_EXTICR2_EXTI7 0xF000U /*!<EXTI 7 configuration */
+/**
+ * @brief EXTI4 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI4_PA 0x0000U /*!<PA[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PB 0x0001U /*!<PB[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PC 0x0002U /*!<PC[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PD 0x0003U /*!<PD[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PE 0x0004U /*!<PE[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PF 0x0005U /*!<PE[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PG 0x0006U /*!<PE[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PH 0x0007U /*!<PH[4] pin */
+
+/**
+ * @brief EXTI5 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI5_PA 0x0000U /*!<PA[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PB 0x0010U /*!<PB[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PC 0x0020U /*!<PC[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PD 0x0030U /*!<PD[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PE 0x0040U /*!<PE[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PF 0x0050U /*!<PE[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PG 0x0060U /*!<PE[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PH 0x0070U /*!<PH[5] pin */
+
+/**
+ * @brief EXTI6 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI6_PA 0x0000U /*!<PA[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PB 0x0100U /*!<PB[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PC 0x0200U /*!<PC[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PD 0x0300U /*!<PD[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PE 0x0400U /*!<PE[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PF 0x0500U /*!<PE[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PG 0x0600U /*!<PE[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PH 0x0700U /*!<PH[6] pin */
+
+/**
+ * @brief EXTI7 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI7_PA 0x0000U /*!<PA[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PB 0x1000U /*!<PB[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PC 0x2000U /*!<PC[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PD 0x3000U /*!<PD[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PE 0x4000U /*!<PE[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PF 0x5000U /*!<PE[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PG 0x6000U /*!<PE[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PH 0x7000U /*!<PH[7] pin */
+
+
+/***************** Bit definition for SYSCFG_EXTICR3 register ***************/
+#define SYSCFG_EXTICR3_EXTI8 0x000FU /*!<EXTI 8 configuration */
+#define SYSCFG_EXTICR3_EXTI9 0x00F0U /*!<EXTI 9 configuration */
+#define SYSCFG_EXTICR3_EXTI10 0x0F00U /*!<EXTI 10 configuration */
+#define SYSCFG_EXTICR3_EXTI11 0xF000U /*!<EXTI 11 configuration */
+
+/**
+ * @brief EXTI8 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI8_PA 0x0000U /*!<PA[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PB 0x0001U /*!<PB[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PC 0x0002U /*!<PC[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PD 0x0003U /*!<PD[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PE 0x0004U /*!<PE[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PF 0x0005U /*!<PE[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PG 0x0006U /*!<PE[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PH 0x0007U /*!<PH[8] pin */
+
+/**
+ * @brief EXTI9 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI9_PA 0x0000U /*!<PA[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PB 0x0010U /*!<PB[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PC 0x0020U /*!<PC[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PD 0x0030U /*!<PD[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PE 0x0040U /*!<PE[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PF 0x0050U /*!<PE[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PG 0x0060U /*!<PE[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PH 0x0070U /*!<PH[9] pin */
+
+/**
+ * @brief EXTI10 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI10_PA 0x0000U /*!<PA[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PB 0x0100U /*!<PB[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PC 0x0200U /*!<PC[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PD 0x0300U /*!<PD[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PE 0x0400U /*!<PE[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PF 0x0500U /*!<PE[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PG 0x0600U /*!<PE[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PH 0x0700U /*!<PH[10] pin */
+
+/**
+ * @brief EXTI11 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI11_PA 0x0000U /*!<PA[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PB 0x1000U /*!<PB[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PC 0x2000U /*!<PC[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PD 0x3000U /*!<PD[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PE 0x4000U /*!<PE[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PF 0x5000U /*!<PE[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PG 0x6000U /*!<PE[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PH 0x7000U /*!<PH[11] pin */
+
+/***************** Bit definition for SYSCFG_EXTICR4 register ***************/
+#define SYSCFG_EXTICR4_EXTI12 0x000FU /*!<EXTI 12 configuration */
+#define SYSCFG_EXTICR4_EXTI13 0x00F0U /*!<EXTI 13 configuration */
+#define SYSCFG_EXTICR4_EXTI14 0x0F00U /*!<EXTI 14 configuration */
+#define SYSCFG_EXTICR4_EXTI15 0xF000U /*!<EXTI 15 configuration */
+/**
+ * @brief EXTI12 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI12_PA 0x0000U /*!<PA[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PB 0x0001U /*!<PB[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PC 0x0002U /*!<PC[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PD 0x0003U /*!<PD[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PE 0x0004U /*!<PE[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PF 0x0005U /*!<PE[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PG 0x0006U /*!<PE[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PH 0x0007U /*!<PH[12] pin */
+
+/**
+ * @brief EXTI13 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI13_PA 0x0000U /*!<PA[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PB 0x0010U /*!<PB[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PC 0x0020U /*!<PC[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PD 0x0030U /*!<PD[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PE 0x0040U /*!<PE[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PF 0x0050U /*!<PE[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PG 0x0060U /*!<PE[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PH 0x0070U /*!<PH[13] pin */
+
+/**
+ * @brief EXTI14 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI14_PA 0x0000U /*!<PA[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PB 0x0100U /*!<PB[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PC 0x0200U /*!<PC[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PD 0x0300U /*!<PD[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PE 0x0400U /*!<PE[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PF 0x0500U /*!<PE[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PG 0x0600U /*!<PE[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PH 0x0700U /*!<PH[14] pin */
+
+/**
+ * @brief EXTI15 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI15_PA 0x0000U /*!<PA[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PB 0x1000U /*!<PB[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PC 0x2000U /*!<PC[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PD 0x3000U /*!<PD[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PE 0x4000U /*!<PE[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PF 0x5000U /*!<PF[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PG 0x6000U /*!<PG[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PH 0x7000U /*!<PH[15] pin */
+
+/****************** Bit definition for SYSCFG_CMPCR register ****************/
+#define SYSCFG_CMPCR_CMP_PD 0x00000001U /*!<Compensation cell ready flag */
+#define SYSCFG_CMPCR_READY 0x00000100U /*!<Compensation cell power-down */
+
+/****************** Bit definition for SYSCFG_CFGR register *****************/
+#define SYSCFG_CFGR_FMPI2C1_SCL 0x00000001U /*!<FM+ drive capability for FMPI2C1_SCL pin */
+#define SYSCFG_CFGR_FMPI2C1_SDA 0x00000002U /*!<FM+ drive capability for FMPI2C1_SDA pin */
+
+/******************************************************************************/
+/* */
+/* TIM */
+/* */
+/******************************************************************************/
+/******************* Bit definition for TIM_CR1 register ********************/
+#define TIM_CR1_CEN 0x0001U /*!<Counter enable */
+#define TIM_CR1_UDIS 0x0002U /*!<Update disable */
+#define TIM_CR1_URS 0x0004U /*!<Update request source */
+#define TIM_CR1_OPM 0x0008U /*!<One pulse mode */
+#define TIM_CR1_DIR 0x0010U /*!<Direction */
+
+#define TIM_CR1_CMS 0x0060U /*!<CMS[1:0] bits (Center-aligned mode selection) */
+#define TIM_CR1_CMS_0 0x0020U /*!<Bit 0 */
+#define TIM_CR1_CMS_1 0x0040U /*!<Bit 1 */
+
+#define TIM_CR1_ARPE 0x0080U /*!<Auto-reload preload enable */
+
+#define TIM_CR1_CKD 0x0300U /*!<CKD[1:0] bits (clock division) */
+#define TIM_CR1_CKD_0 0x0100U /*!<Bit 0 */
+#define TIM_CR1_CKD_1 0x0200U /*!<Bit 1 */
+
+/******************* Bit definition for TIM_CR2 register ********************/
+#define TIM_CR2_CCPC 0x0001U /*!<Capture/Compare Preloaded Control */
+#define TIM_CR2_CCUS 0x0004U /*!<Capture/Compare Control Update Selection */
+#define TIM_CR2_CCDS 0x0008U /*!<Capture/Compare DMA Selection */
+
+#define TIM_CR2_MMS 0x0070U /*!<MMS[2:0] bits (Master Mode Selection) */
+#define TIM_CR2_MMS_0 0x0010U /*!<Bit 0 */
+#define TIM_CR2_MMS_1 0x0020U /*!<Bit 1 */
+#define TIM_CR2_MMS_2 0x0040U /*!<Bit 2 */
+
+#define TIM_CR2_TI1S 0x0080U /*!<TI1 Selection */
+#define TIM_CR2_OIS1 0x0100U /*!<Output Idle state 1 (OC1 output) */
+#define TIM_CR2_OIS1N 0x0200U /*!<Output Idle state 1 (OC1N output) */
+#define TIM_CR2_OIS2 0x0400U /*!<Output Idle state 2 (OC2 output) */
+#define TIM_CR2_OIS2N 0x0800U /*!<Output Idle state 2 (OC2N output) */
+#define TIM_CR2_OIS3 0x1000U /*!<Output Idle state 3 (OC3 output) */
+#define TIM_CR2_OIS3N 0x2000U /*!<Output Idle state 3 (OC3N output) */
+#define TIM_CR2_OIS4 0x4000U /*!<Output Idle state 4 (OC4 output) */
+
+/******************* Bit definition for TIM_SMCR register *******************/
+#define TIM_SMCR_SMS 0x0007U /*!<SMS[2:0] bits (Slave mode selection) */
+#define TIM_SMCR_SMS_0 0x0001U /*!<Bit 0 */
+#define TIM_SMCR_SMS_1 0x0002U /*!<Bit 1 */
+#define TIM_SMCR_SMS_2 0x0004U /*!<Bit 2 */
+
+#define TIM_SMCR_TS 0x0070U /*!<TS[2:0] bits (Trigger selection) */
+#define TIM_SMCR_TS_0 0x0010U /*!<Bit 0 */
+#define TIM_SMCR_TS_1 0x0020U /*!<Bit 1 */
+#define TIM_SMCR_TS_2 0x0040U /*!<Bit 2 */
+
+#define TIM_SMCR_MSM 0x0080U /*!<Master/slave mode */
+
+#define TIM_SMCR_ETF 0x0F00U /*!<ETF[3:0] bits (External trigger filter) */
+#define TIM_SMCR_ETF_0 0x0100U /*!<Bit 0 */
+#define TIM_SMCR_ETF_1 0x0200U /*!<Bit 1 */
+#define TIM_SMCR_ETF_2 0x0400U /*!<Bit 2 */
+#define TIM_SMCR_ETF_3 0x0800U /*!<Bit 3 */
+
+#define TIM_SMCR_ETPS 0x3000U /*!<ETPS[1:0] bits (External trigger prescaler) */
+#define TIM_SMCR_ETPS_0 0x1000U /*!<Bit 0 */
+#define TIM_SMCR_ETPS_1 0x2000U /*!<Bit 1 */
+
+#define TIM_SMCR_ECE 0x4000U /*!<External clock enable */
+#define TIM_SMCR_ETP 0x8000U /*!<External trigger polarity */
+
+/******************* Bit definition for TIM_DIER register *******************/
+#define TIM_DIER_UIE 0x0001U /*!<Update interrupt enable */
+#define TIM_DIER_CC1IE 0x0002U /*!<Capture/Compare 1 interrupt enable */
+#define TIM_DIER_CC2IE 0x0004U /*!<Capture/Compare 2 interrupt enable */
+#define TIM_DIER_CC3IE 0x0008U /*!<Capture/Compare 3 interrupt enable */
+#define TIM_DIER_CC4IE 0x0010U /*!<Capture/Compare 4 interrupt enable */
+#define TIM_DIER_COMIE 0x0020U /*!<COM interrupt enable */
+#define TIM_DIER_TIE 0x0040U /*!<Trigger interrupt enable */
+#define TIM_DIER_BIE 0x0080U /*!<Break interrupt enable */
+#define TIM_DIER_UDE 0x0100U /*!<Update DMA request enable */
+#define TIM_DIER_CC1DE 0x0200U /*!<Capture/Compare 1 DMA request enable */
+#define TIM_DIER_CC2DE 0x0400U /*!<Capture/Compare 2 DMA request enable */
+#define TIM_DIER_CC3DE 0x0800U /*!<Capture/Compare 3 DMA request enable */
+#define TIM_DIER_CC4DE 0x1000U /*!<Capture/Compare 4 DMA request enable */
+#define TIM_DIER_COMDE 0x2000U /*!<COM DMA request enable */
+#define TIM_DIER_TDE 0x4000U /*!<Trigger DMA request enable */
+
+/******************** Bit definition for TIM_SR register ********************/
+#define TIM_SR_UIF 0x0001U /*!<Update interrupt Flag */
+#define TIM_SR_CC1IF 0x0002U /*!<Capture/Compare 1 interrupt Flag */
+#define TIM_SR_CC2IF 0x0004U /*!<Capture/Compare 2 interrupt Flag */
+#define TIM_SR_CC3IF 0x0008U /*!<Capture/Compare 3 interrupt Flag */
+#define TIM_SR_CC4IF 0x0010U /*!<Capture/Compare 4 interrupt Flag */
+#define TIM_SR_COMIF 0x0020U /*!<COM interrupt Flag */
+#define TIM_SR_TIF 0x0040U /*!<Trigger interrupt Flag */
+#define TIM_SR_BIF 0x0080U /*!<Break interrupt Flag */
+#define TIM_SR_CC1OF 0x0200U /*!<Capture/Compare 1 Overcapture Flag */
+#define TIM_SR_CC2OF 0x0400U /*!<Capture/Compare 2 Overcapture Flag */
+#define TIM_SR_CC3OF 0x0800U /*!<Capture/Compare 3 Overcapture Flag */
+#define TIM_SR_CC4OF 0x1000U /*!<Capture/Compare 4 Overcapture Flag */
+
+/******************* Bit definition for TIM_EGR register ********************/
+#define TIM_EGR_UG 0x01U /*!<Update Generation */
+#define TIM_EGR_CC1G 0x02U /*!<Capture/Compare 1 Generation */
+#define TIM_EGR_CC2G 0x04U /*!<Capture/Compare 2 Generation */
+#define TIM_EGR_CC3G 0x08U /*!<Capture/Compare 3 Generation */
+#define TIM_EGR_CC4G 0x10U /*!<Capture/Compare 4 Generation */
+#define TIM_EGR_COMG 0x20U /*!<Capture/Compare Control Update Generation */
+#define TIM_EGR_TG 0x40U /*!<Trigger Generation */
+#define TIM_EGR_BG 0x80U /*!<Break Generation */
+
+/****************** Bit definition for TIM_CCMR1 register *******************/
+#define TIM_CCMR1_CC1S 0x0003U /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
+#define TIM_CCMR1_CC1S_0 0x0001U /*!<Bit 0 */
+#define TIM_CCMR1_CC1S_1 0x0002U /*!<Bit 1 */
+
+#define TIM_CCMR1_OC1FE 0x0004U /*!<Output Compare 1 Fast enable */
+#define TIM_CCMR1_OC1PE 0x0008U /*!<Output Compare 1 Preload enable */
+
+#define TIM_CCMR1_OC1M 0x0070U /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
+#define TIM_CCMR1_OC1M_0 0x0010U /*!<Bit 0 */
+#define TIM_CCMR1_OC1M_1 0x0020U /*!<Bit 1 */
+#define TIM_CCMR1_OC1M_2 0x0040U /*!<Bit 2 */
+
+#define TIM_CCMR1_OC1CE 0x0080U /*!<Output Compare 1Clear Enable */
+
+#define TIM_CCMR1_CC2S 0x0300U /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
+#define TIM_CCMR1_CC2S_0 0x0100U /*!<Bit 0 */
+#define TIM_CCMR1_CC2S_1 0x0200U /*!<Bit 1 */
+
+#define TIM_CCMR1_OC2FE 0x0400U /*!<Output Compare 2 Fast enable */
+#define TIM_CCMR1_OC2PE 0x0800U /*!<Output Compare 2 Preload enable */
+
+#define TIM_CCMR1_OC2M 0x7000U /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
+#define TIM_CCMR1_OC2M_0 0x1000U /*!<Bit 0 */
+#define TIM_CCMR1_OC2M_1 0x2000U /*!<Bit 1 */
+#define TIM_CCMR1_OC2M_2 0x4000U /*!<Bit 2 */
+
+#define TIM_CCMR1_OC2CE 0x8000U /*!<Output Compare 2 Clear Enable */
+
+/*----------------------------------------------------------------------------*/
+
+#define TIM_CCMR1_IC1PSC 0x000CU /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
+#define TIM_CCMR1_IC1PSC_0 0x0004U /*!<Bit 0 */
+#define TIM_CCMR1_IC1PSC_1 0x0008U /*!<Bit 1 */
+
+#define TIM_CCMR1_IC1F 0x00F0U /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
+#define TIM_CCMR1_IC1F_0 0x0010U /*!<Bit 0 */
+#define TIM_CCMR1_IC1F_1 0x0020U /*!<Bit 1 */
+#define TIM_CCMR1_IC1F_2 0x0040U /*!<Bit 2 */
+#define TIM_CCMR1_IC1F_3 0x0080U /*!<Bit 3 */
+
+#define TIM_CCMR1_IC2PSC 0x0C00U /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
+#define TIM_CCMR1_IC2PSC_0 0x0400U /*!<Bit 0 */
+#define TIM_CCMR1_IC2PSC_1 0x0800U /*!<Bit 1 */
+
+#define TIM_CCMR1_IC2F 0xF000U /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
+#define TIM_CCMR1_IC2F_0 0x1000U /*!<Bit 0 */
+#define TIM_CCMR1_IC2F_1 0x2000U /*!<Bit 1 */
+#define TIM_CCMR1_IC2F_2 0x4000U /*!<Bit 2 */
+#define TIM_CCMR1_IC2F_3 0x8000U /*!<Bit 3 */
+
+/****************** Bit definition for TIM_CCMR2 register *******************/
+#define TIM_CCMR2_CC3S 0x0003U /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
+#define TIM_CCMR2_CC3S_0 0x0001U /*!<Bit 0 */
+#define TIM_CCMR2_CC3S_1 0x0002U /*!<Bit 1 */
+
+#define TIM_CCMR2_OC3FE 0x0004U /*!<Output Compare 3 Fast enable */
+#define TIM_CCMR2_OC3PE 0x0008U /*!<Output Compare 3 Preload enable */
+
+#define TIM_CCMR2_OC3M 0x0070U /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
+#define TIM_CCMR2_OC3M_0 0x0010U /*!<Bit 0 */
+#define TIM_CCMR2_OC3M_1 0x0020U /*!<Bit 1 */
+#define TIM_CCMR2_OC3M_2 0x0040U /*!<Bit 2 */
+
+#define TIM_CCMR2_OC3CE 0x0080U /*!<Output Compare 3 Clear Enable */
+
+#define TIM_CCMR2_CC4S 0x0300U /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
+#define TIM_CCMR2_CC4S_0 0x0100U /*!<Bit 0 */
+#define TIM_CCMR2_CC4S_1 0x0200U /*!<Bit 1 */
+
+#define TIM_CCMR2_OC4FE 0x0400U /*!<Output Compare 4 Fast enable */
+#define TIM_CCMR2_OC4PE 0x0800U /*!<Output Compare 4 Preload enable */
+
+#define TIM_CCMR2_OC4M 0x7000U /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
+#define TIM_CCMR2_OC4M_0 0x1000U /*!<Bit 0 */
+#define TIM_CCMR2_OC4M_1 0x2000U /*!<Bit 1 */
+#define TIM_CCMR2_OC4M_2 0x4000U /*!<Bit 2 */
+
+#define TIM_CCMR2_OC4CE 0x8000U /*!<Output Compare 4 Clear Enable */
+
+/*----------------------------------------------------------------------------*/
+
+#define TIM_CCMR2_IC3PSC 0x000CU /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
+#define TIM_CCMR2_IC3PSC_0 0x0004U /*!<Bit 0 */
+#define TIM_CCMR2_IC3PSC_1 0x0008U /*!<Bit 1 */
+
+#define TIM_CCMR2_IC3F 0x00F0U /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
+#define TIM_CCMR2_IC3F_0 0x0010U /*!<Bit 0 */
+#define TIM_CCMR2_IC3F_1 0x0020U /*!<Bit 1 */
+#define TIM_CCMR2_IC3F_2 0x0040U /*!<Bit 2 */
+#define TIM_CCMR2_IC3F_3 0x0080U /*!<Bit 3 */
+
+#define TIM_CCMR2_IC4PSC 0x0C00U /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
+#define TIM_CCMR2_IC4PSC_0 0x0400U /*!<Bit 0 */
+#define TIM_CCMR2_IC4PSC_1 0x0800U /*!<Bit 1 */
+
+#define TIM_CCMR2_IC4F 0xF000U /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
+#define TIM_CCMR2_IC4F_0 0x1000U /*!<Bit 0 */
+#define TIM_CCMR2_IC4F_1 0x2000U /*!<Bit 1 */
+#define TIM_CCMR2_IC4F_2 0x4000U /*!<Bit 2 */
+#define TIM_CCMR2_IC4F_3 0x8000U /*!<Bit 3 */
+
+/******************* Bit definition for TIM_CCER register *******************/
+#define TIM_CCER_CC1E 0x0001U /*!<Capture/Compare 1 output enable */
+#define TIM_CCER_CC1P 0x0002U /*!<Capture/Compare 1 output Polarity */
+#define TIM_CCER_CC1NE 0x0004U /*!<Capture/Compare 1 Complementary output enable */
+#define TIM_CCER_CC1NP 0x0008U /*!<Capture/Compare 1 Complementary output Polarity */
+#define TIM_CCER_CC2E 0x0010U /*!<Capture/Compare 2 output enable */
+#define TIM_CCER_CC2P 0x0020U /*!<Capture/Compare 2 output Polarity */
+#define TIM_CCER_CC2NE 0x0040U /*!<Capture/Compare 2 Complementary output enable */
+#define TIM_CCER_CC2NP 0x0080U /*!<Capture/Compare 2 Complementary output Polarity */
+#define TIM_CCER_CC3E 0x0100U /*!<Capture/Compare 3 output enable */
+#define TIM_CCER_CC3P 0x0200U /*!<Capture/Compare 3 output Polarity */
+#define TIM_CCER_CC3NE 0x0400U /*!<Capture/Compare 3 Complementary output enable */
+#define TIM_CCER_CC3NP 0x0800U /*!<Capture/Compare 3 Complementary output Polarity */
+#define TIM_CCER_CC4E 0x1000U /*!<Capture/Compare 4 output enable */
+#define TIM_CCER_CC4P 0x2000U /*!<Capture/Compare 4 output Polarity */
+#define TIM_CCER_CC4NP 0x8000U /*!<Capture/Compare 4 Complementary output Polarity */
+
+/******************* Bit definition for TIM_CNT register ********************/
+#define TIM_CNT_CNT 0xFFFFU /*!<Counter Value */
+
+/******************* Bit definition for TIM_PSC register ********************/
+#define TIM_PSC_PSC 0xFFFFU /*!<Prescaler Value */
+
+/******************* Bit definition for TIM_ARR register ********************/
+#define TIM_ARR_ARR 0xFFFFU /*!<actual auto-reload Value */
+
+/******************* Bit definition for TIM_RCR register ********************/
+#define TIM_RCR_REP 0xFFU /*!<Repetition Counter Value */
+
+/******************* Bit definition for TIM_CCR1 register *******************/
+#define TIM_CCR1_CCR1 0xFFFFU /*!<Capture/Compare 1 Value */
+
+/******************* Bit definition for TIM_CCR2 register *******************/
+#define TIM_CCR2_CCR2 0xFFFFU /*!<Capture/Compare 2 Value */
+
+/******************* Bit definition for TIM_CCR3 register *******************/
+#define TIM_CCR3_CCR3 0xFFFFU /*!<Capture/Compare 3 Value */
+
+/******************* Bit definition for TIM_CCR4 register *******************/
+#define TIM_CCR4_CCR4 0xFFFFU /*!<Capture/Compare 4 Value */
+
+/******************* Bit definition for TIM_BDTR register *******************/
+#define TIM_BDTR_DTG 0x00FFU /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
+#define TIM_BDTR_DTG_0 0x0001U /*!<Bit 0 */
+#define TIM_BDTR_DTG_1 0x0002U /*!<Bit 1 */
+#define TIM_BDTR_DTG_2 0x0004U /*!<Bit 2 */
+#define TIM_BDTR_DTG_3 0x0008U /*!<Bit 3 */
+#define TIM_BDTR_DTG_4 0x0010U /*!<Bit 4 */
+#define TIM_BDTR_DTG_5 0x0020U /*!<Bit 5 */
+#define TIM_BDTR_DTG_6 0x0040U /*!<Bit 6 */
+#define TIM_BDTR_DTG_7 0x0080U /*!<Bit 7 */
+
+#define TIM_BDTR_LOCK 0x0300U /*!<LOCK[1:0] bits (Lock Configuration) */
+#define TIM_BDTR_LOCK_0 0x0100U /*!<Bit 0 */
+#define TIM_BDTR_LOCK_1 0x0200U /*!<Bit 1 */
+
+#define TIM_BDTR_OSSI 0x0400U /*!<Off-State Selection for Idle mode */
+#define TIM_BDTR_OSSR 0x0800U /*!<Off-State Selection for Run mode */
+#define TIM_BDTR_BKE 0x1000U /*!<Break enable */
+#define TIM_BDTR_BKP 0x2000U /*!<Break Polarity */
+#define TIM_BDTR_AOE 0x4000U /*!<Automatic Output enable */
+#define TIM_BDTR_MOE 0x8000U /*!<Main Output enable */
+
+/******************* Bit definition for TIM_DCR register ********************/
+#define TIM_DCR_DBA 0x001FU /*!<DBA[4:0] bits (DMA Base Address) */
+#define TIM_DCR_DBA_0 0x0001U /*!<Bit 0 */
+#define TIM_DCR_DBA_1 0x0002U /*!<Bit 1 */
+#define TIM_DCR_DBA_2 0x0004U /*!<Bit 2 */
+#define TIM_DCR_DBA_3 0x0008U /*!<Bit 3 */
+#define TIM_DCR_DBA_4 0x0010U /*!<Bit 4 */
+
+#define TIM_DCR_DBL 0x1F00U /*!<DBL[4:0] bits (DMA Burst Length) */
+#define TIM_DCR_DBL_0 0x0100U /*!<Bit 0 */
+#define TIM_DCR_DBL_1 0x0200U /*!<Bit 1 */
+#define TIM_DCR_DBL_2 0x0400U /*!<Bit 2 */
+#define TIM_DCR_DBL_3 0x0800U /*!<Bit 3 */
+#define TIM_DCR_DBL_4 0x1000U /*!<Bit 4 */
+
+/******************* Bit definition for TIM_DMAR register *******************/
+#define TIM_DMAR_DMAB 0xFFFFU /*!<DMA register for burst accesses */
+
+/******************* Bit definition for TIM_OR register *********************/
+#define TIM_OR_TI4_RMP 0x00C0U /*!<TI4_RMP[1:0] bits (TIM5 Input 4 remap) */
+#define TIM_OR_TI4_RMP_0 0x0040U /*!<Bit 0 */
+#define TIM_OR_TI4_RMP_1 0x0080U /*!<Bit 1 */
+#define TIM_OR_ITR1_RMP 0x0C00U /*!<ITR1_RMP[1:0] bits (TIM2 Internal trigger 1 remap) */
+#define TIM_OR_ITR1_RMP_0 0x0400U /*!<Bit 0 */
+#define TIM_OR_ITR1_RMP_1 0x0800U /*!<Bit 1 */
+
+
+/******************************************************************************/
+/* */
+/* Universal Synchronous Asynchronous Receiver Transmitter */
+/* */
+/******************************************************************************/
+/******************* Bit definition for USART_SR register *******************/
+#define USART_SR_PE 0x0001U /*!<Parity Error */
+#define USART_SR_FE 0x0002U /*!<Framing Error */
+#define USART_SR_NE 0x0004U /*!<Noise Error Flag */
+#define USART_SR_ORE 0x0008U /*!<OverRun Error */
+#define USART_SR_IDLE 0x0010U /*!<IDLE line detected */
+#define USART_SR_RXNE 0x0020U /*!<Read Data Register Not Empty */
+#define USART_SR_TC 0x0040U /*!<Transmission Complete */
+#define USART_SR_TXE 0x0080U /*!<Transmit Data Register Empty */
+#define USART_SR_LBD 0x0100U /*!<LIN Break Detection Flag */
+#define USART_SR_CTS 0x0200U /*!<CTS Flag */
+
+/******************* Bit definition for USART_DR register *******************/
+#define USART_DR_DR 0x01FFU /*!<Data value */
+
+/****************** Bit definition for USART_BRR register *******************/
+#define USART_BRR_DIV_Fraction 0x000FU /*!<Fraction of USARTDIV */
+#define USART_BRR_DIV_Mantissa 0xFFF0U /*!<Mantissa of USARTDIV */
+
+/****************** Bit definition for USART_CR1 register *******************/
+#define USART_CR1_SBK 0x0001U /*!<Send Break */
+#define USART_CR1_RWU 0x0002U /*!<Receiver wakeup */
+#define USART_CR1_RE 0x0004U /*!<Receiver Enable */
+#define USART_CR1_TE 0x0008U /*!<Transmitter Enable */
+#define USART_CR1_IDLEIE 0x0010U /*!<IDLE Interrupt Enable */
+#define USART_CR1_RXNEIE 0x0020U /*!<RXNE Interrupt Enable */
+#define USART_CR1_TCIE 0x0040U /*!<Transmission Complete Interrupt Enable */
+#define USART_CR1_TXEIE 0x0080U /*!<PE Interrupt Enable */
+#define USART_CR1_PEIE 0x0100U /*!<PE Interrupt Enable */
+#define USART_CR1_PS 0x0200U /*!<Parity Selection */
+#define USART_CR1_PCE 0x0400U /*!<Parity Control Enable */
+#define USART_CR1_WAKE 0x0800U /*!<Wakeup method */
+#define USART_CR1_M 0x1000U /*!<Word length */
+#define USART_CR1_UE 0x2000U /*!<USART Enable */
+#define USART_CR1_OVER8 0x8000U /*!<USART Oversampling by 8 enable */
+
+/****************** Bit definition for USART_CR2 register *******************/
+#define USART_CR2_ADD 0x000FU /*!<Address of the USART node */
+#define USART_CR2_LBDL 0x0020U /*!<LIN Break Detection Length */
+#define USART_CR2_LBDIE 0x0040U /*!<LIN Break Detection Interrupt Enable */
+#define USART_CR2_LBCL 0x0100U /*!<Last Bit Clock pulse */
+#define USART_CR2_CPHA 0x0200U /*!<Clock Phase */
+#define USART_CR2_CPOL 0x0400U /*!<Clock Polarity */
+#define USART_CR2_CLKEN 0x0800U /*!<Clock Enable */
+
+#define USART_CR2_STOP 0x3000U /*!<STOP[1:0] bits (STOP bits) */
+#define USART_CR2_STOP_0 0x1000U /*!<Bit 0 */
+#define USART_CR2_STOP_1 0x2000U /*!<Bit 1 */
+
+#define USART_CR2_LINEN 0x4000U /*!<LIN mode enable */
+
+/****************** Bit definition for USART_CR3 register *******************/
+#define USART_CR3_EIE 0x0001U /*!<Error Interrupt Enable */
+#define USART_CR3_IREN 0x0002U /*!<IrDA mode Enable */
+#define USART_CR3_IRLP 0x0004U /*!<IrDA Low-Power */
+#define USART_CR3_HDSEL 0x0008U /*!<Half-Duplex Selection */
+#define USART_CR3_NACK 0x0010U /*!<Smartcard NACK enable */
+#define USART_CR3_SCEN 0x0020U /*!<Smartcard mode enable */
+#define USART_CR3_DMAR 0x0040U /*!<DMA Enable Receiver */
+#define USART_CR3_DMAT 0x0080U /*!<DMA Enable Transmitter */
+#define USART_CR3_RTSE 0x0100U /*!<RTS Enable */
+#define USART_CR3_CTSE 0x0200U /*!<CTS Enable */
+#define USART_CR3_CTSIE 0x0400U /*!<CTS Interrupt Enable */
+#define USART_CR3_ONEBIT 0x0800U /*!<USART One bit method enable */
+
+/****************** Bit definition for USART_GTPR register ******************/
+#define USART_GTPR_PSC 0x00FFU /*!<PSC[7:0] bits (Prescaler value) */
+#define USART_GTPR_PSC_0 0x0001U /*!<Bit 0 */
+#define USART_GTPR_PSC_1 0x0002U /*!<Bit 1 */
+#define USART_GTPR_PSC_2 0x0004U /*!<Bit 2 */
+#define USART_GTPR_PSC_3 0x0008U /*!<Bit 3 */
+#define USART_GTPR_PSC_4 0x0010U /*!<Bit 4 */
+#define USART_GTPR_PSC_5 0x0020U /*!<Bit 5 */
+#define USART_GTPR_PSC_6 0x0040U /*!<Bit 6 */
+#define USART_GTPR_PSC_7 0x0080U /*!<Bit 7 */
+
+#define USART_GTPR_GT 0xFF00U /*!<Guard time value */
+
+/******************************************************************************/
+/* */
+/* Window WATCHDOG */
+/* */
+/******************************************************************************/
+/******************* Bit definition for WWDG_CR register ********************/
+#define WWDG_CR_T 0x7FU /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
+#define WWDG_CR_T_0 0x01U /*!<Bit 0 */
+#define WWDG_CR_T_1 0x02U /*!<Bit 1 */
+#define WWDG_CR_T_2 0x04U /*!<Bit 2 */
+#define WWDG_CR_T_3 0x08U /*!<Bit 3 */
+#define WWDG_CR_T_4 0x10U /*!<Bit 4 */
+#define WWDG_CR_T_5 0x20U /*!<Bit 5 */
+#define WWDG_CR_T_6 0x40U /*!<Bit 6 */
+/* Legacy defines */
+#define WWDG_CR_T0 WWDG_CR_T_0
+#define WWDG_CR_T1 WWDG_CR_T_1
+#define WWDG_CR_T2 WWDG_CR_T_2
+#define WWDG_CR_T3 WWDG_CR_T_3
+#define WWDG_CR_T4 WWDG_CR_T_4
+#define WWDG_CR_T5 WWDG_CR_T_5
+#define WWDG_CR_T6 WWDG_CR_T_6
+
+#define WWDG_CR_WDGA 0x80U /*!<Activation bit */
+
+/******************* Bit definition for WWDG_CFR register *******************/
+#define WWDG_CFR_W 0x007FU /*!<W[6:0] bits (7-bit window value) */
+#define WWDG_CFR_W_0 0x0001U /*!<Bit 0 */
+#define WWDG_CFR_W_1 0x0002U /*!<Bit 1 */
+#define WWDG_CFR_W_2 0x0004U /*!<Bit 2 */
+#define WWDG_CFR_W_3 0x0008U /*!<Bit 3 */
+#define WWDG_CFR_W_4 0x0010U /*!<Bit 4 */
+#define WWDG_CFR_W_5 0x0020U /*!<Bit 5 */
+#define WWDG_CFR_W_6 0x0040U /*!<Bit 6 */
+/* Legacy defines */
+#define WWDG_CFR_W0 WWDG_CFR_W_0
+#define WWDG_CFR_W1 WWDG_CFR_W_1
+#define WWDG_CFR_W2 WWDG_CFR_W_2
+#define WWDG_CFR_W3 WWDG_CFR_W_3
+#define WWDG_CFR_W4 WWDG_CFR_W_4
+#define WWDG_CFR_W5 WWDG_CFR_W_5
+#define WWDG_CFR_W6 WWDG_CFR_W_6
+
+#define WWDG_CFR_WDGTB 0x0180U /*!<WDGTB[1:0] bits (Timer Base) */
+#define WWDG_CFR_WDGTB_0 0x0080U /*!<Bit 0 */
+#define WWDG_CFR_WDGTB_1 0x0100U /*!<Bit 1 */
+/* Legacy defines */
+#define WWDG_CFR_WDGTB0 WWDG_CFR_WDGTB_0
+#define WWDG_CFR_WDGTB1 WWDG_CFR_WDGTB_1
+
+#define WWDG_CFR_EWI 0x0200U /*!<Early Wakeup Interrupt */
+
+/******************* Bit definition for WWDG_SR register ********************/
+#define WWDG_SR_EWIF 0x01U /*!<Early Wakeup Interrupt Flag */
+
+
+/******************************************************************************/
+/* */
+/* DBG */
+/* */
+/******************************************************************************/
+/******************** Bit definition for DBGMCU_IDCODE register *************/
+#define DBGMCU_IDCODE_DEV_ID 0x00000FFFU
+#define DBGMCU_IDCODE_REV_ID 0xFFFF0000U
+
+/******************** Bit definition for DBGMCU_CR register *****************/
+#define DBGMCU_CR_DBG_SLEEP 0x00000001U
+#define DBGMCU_CR_DBG_STOP 0x00000002U
+#define DBGMCU_CR_DBG_STANDBY 0x00000004U
+#define DBGMCU_CR_TRACE_IOEN 0x00000020U
+
+#define DBGMCU_CR_TRACE_MODE 0x000000C0U
+#define DBGMCU_CR_TRACE_MODE_0 0x00000040U/*!<Bit 0 */
+#define DBGMCU_CR_TRACE_MODE_1 0x00000080U/*!<Bit 1 */
+
+/******************** Bit definition for DBGMCU_APB1_FZ register ************/
+#define DBGMCU_APB1_FZ_DBG_TIM2_STOP 0x00000001U
+#define DBGMCU_APB1_FZ_DBG_TIM3_STOP 0x00000002U
+#define DBGMCU_APB1_FZ_DBG_TIM4_STOP 0x00000004U
+#define DBGMCU_APB1_FZ_DBG_TIM5_STOP 0x00000008U
+#define DBGMCU_APB1_FZ_DBG_TIM6_STOP 0x00000010U
+#define DBGMCU_APB1_FZ_DBG_TIM7_STOP 0x00000020U
+#define DBGMCU_APB1_FZ_DBG_TIM12_STOP 0x00000040U
+#define DBGMCU_APB1_FZ_DBG_TIM13_STOP 0x00000080U
+#define DBGMCU_APB1_FZ_DBG_TIM14_STOP 0x00000100U
+#define DBGMCU_APB1_FZ_DBG_RTC_STOP 0x00000400U
+#define DBGMCU_APB1_FZ_DBG_WWDG_STOP 0x00000800U
+#define DBGMCU_APB1_FZ_DBG_IWDG_STOP 0x00001000U
+#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT 0x00200000U
+#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT 0x00400000U
+#define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT 0x00800000U
+#define DBGMCU_APB1_FZ_DBG_CAN1_STOP 0x02000000U
+#define DBGMCU_APB1_FZ_DBG_CAN2_STOP 0x04000000U
+
+/******************** Bit definition for DBGMCU_APB2_FZ register ************/
+#define DBGMCU_APB2_FZ_DBG_TIM1_STOP 0x00000001U
+#define DBGMCU_APB2_FZ_DBG_TIM8_STOP 0x00000002U
+#define DBGMCU_APB2_FZ_DBG_TIM9_STOP 0x00010000U
+#define DBGMCU_APB2_FZ_DBG_TIM10_STOP 0x00020000U
+#define DBGMCU_APB2_FZ_DBG_TIM11_STOP 0x00040000U
+
+/******************************************************************************/
+/* */
+/* USB_OTG */
+/* */
+/******************************************************************************/
+/******************** Bit definition for USB_OTG_GOTGCTL register ***********/
+#define USB_OTG_GOTGCTL_SRQSCS 0x00000001U /*!< Session request success */
+#define USB_OTG_GOTGCTL_SRQ 0x00000002U /*!< Session request */
+#define USB_OTG_GOTGCTL_VBVALOEN 0x00000004U /*!< VBUS valid override enable */
+#define USB_OTG_GOTGCTL_VBVALOVAL 0x00000008U /*!< VBUS valid override value */
+#define USB_OTG_GOTGCTL_AVALOEN 0x00000010U /*!< A-peripheral session valid override enable */
+#define USB_OTG_GOTGCTL_AVALOVAL 0x00000020U /*!< A-peripheral session valid override value */
+#define USB_OTG_GOTGCTL_BVALOEN 0x00000040U /*!< B-peripheral session valid override enable */
+#define USB_OTG_GOTGCTL_BVALOVAL 0x00000080U /*!< B-peripheral session valid override value */
+#define USB_OTG_GOTGCTL_HNGSCS 0x00000100U /*!< Host set HNP enable */
+#define USB_OTG_GOTGCTL_HNPRQ 0x00000200U /*!< HNP request */
+#define USB_OTG_GOTGCTL_HSHNPEN 0x00000400U /*!< Host set HNP enable */
+#define USB_OTG_GOTGCTL_DHNPEN 0x00000800U /*!< Device HNP enabled */
+#define USB_OTG_GOTGCTL_EHEN 0x00001000U /*!< Embedded host enable */
+#define USB_OTG_GOTGCTL_CIDSTS 0x00010000U /*!< Connector ID status */
+#define USB_OTG_GOTGCTL_DBCT 0x00020000U /*!< Long/short debounce time */
+#define USB_OTG_GOTGCTL_ASVLD 0x00040000U /*!< A-session valid */
+#define USB_OTG_GOTGCTL_BSESVLD 0x00080000U /*!< B-session valid */
+#define USB_OTG_GOTGCTL_OTGVER 0x00100000U /*!< OTG version */
+
+/******************** Bit definition for USB_OTG_HCFG register **************/
+
+#define USB_OTG_HCFG_FSLSPCS 0x00000003U /*!< FS/LS PHY clock select */
+#define USB_OTG_HCFG_FSLSPCS_0 0x00000001U /*!<Bit 0 */
+#define USB_OTG_HCFG_FSLSPCS_1 0x00000002U /*!<Bit 1 */
+#define USB_OTG_HCFG_FSLSS 0x00000004U /*!< FS- and LS-only support */
+
+/******************** Bit definition for USB_OTG_DCFG register **************/
+
+#define USB_OTG_DCFG_DSPD 0x00000003U /*!< Device speed */
+#define USB_OTG_DCFG_DSPD_0 0x00000001U /*!<Bit 0 */
+#define USB_OTG_DCFG_DSPD_1 0x00000002U /*!<Bit 1 */
+#define USB_OTG_DCFG_NZLSOHSK 0x00000004U /*!< Nonzero-length status OUT handshake */
+
+#define USB_OTG_DCFG_DAD 0x000007F0U /*!< Device address */
+#define USB_OTG_DCFG_DAD_0 0x00000010U /*!<Bit 0 */
+#define USB_OTG_DCFG_DAD_1 0x00000020U /*!<Bit 1 */
+#define USB_OTG_DCFG_DAD_2 0x00000040U /*!<Bit 2 */
+#define USB_OTG_DCFG_DAD_3 0x00000080U /*!<Bit 3 */
+#define USB_OTG_DCFG_DAD_4 0x00000100U /*!<Bit 4 */
+#define USB_OTG_DCFG_DAD_5 0x00000200U /*!<Bit 5 */
+#define USB_OTG_DCFG_DAD_6 0x00000400U /*!<Bit 6 */
+
+#define USB_OTG_DCFG_PFIVL 0x00001800U /*!< Periodic (micro)frame interval */
+#define USB_OTG_DCFG_PFIVL_0 0x00000800U /*!<Bit 0 */
+#define USB_OTG_DCFG_PFIVL_1 0x00001000U /*!<Bit 1 */
+
+#define USB_OTG_DCFG_PERSCHIVL 0x03000000U /*!< Periodic scheduling interval */
+#define USB_OTG_DCFG_PERSCHIVL_0 0x01000000U /*!<Bit 0 */
+#define USB_OTG_DCFG_PERSCHIVL_1 0x02000000U /*!<Bit 1 */
+
+/******************** Bit definition for USB_OTG_PCGCR register *************/
+#define USB_OTG_PCGCR_STPPCLK 0x00000001U /*!< Stop PHY clock */
+#define USB_OTG_PCGCR_GATEHCLK 0x00000002U /*!< Gate HCLK */
+#define USB_OTG_PCGCR_PHYSUSP 0x00000010U /*!< PHY suspended */
+
+/******************** Bit definition for USB_OTG_GOTGINT register ***********/
+#define USB_OTG_GOTGINT_SEDET 0x00000004U /*!< Session end detected */
+#define USB_OTG_GOTGINT_SRSSCHG 0x00000100U /*!< Session request success status change */
+#define USB_OTG_GOTGINT_HNSSCHG 0x00000200U /*!< Host negotiation success status change */
+#define USB_OTG_GOTGINT_HNGDET 0x00020000U /*!< Host negotiation detected */
+#define USB_OTG_GOTGINT_ADTOCHG 0x00040000U /*!< A-device timeout change */
+#define USB_OTG_GOTGINT_DBCDNE 0x00080000U /*!< Debounce done */
+#define USB_OTG_GOTGINT_IDCHNG 0x00100000U /*!< Change in ID pin input value */
+
+/******************** Bit definition for USB_OTG_DCTL register **************/
+#define USB_OTG_DCTL_RWUSIG 0x00000001U /*!< Remote wakeup signaling */
+#define USB_OTG_DCTL_SDIS 0x00000002U /*!< Soft disconnect */
+#define USB_OTG_DCTL_GINSTS 0x00000004U /*!< Global IN NAK status */
+#define USB_OTG_DCTL_GONSTS 0x00000008U /*!< Global OUT NAK status */
+#define USB_OTG_DCTL_TCTL 0x00000070U /*!< Test control */
+#define USB_OTG_DCTL_TCTL_0 0x00000010U /*!<Bit 0 */
+#define USB_OTG_DCTL_TCTL_1 0x00000020U /*!<Bit 1 */
+#define USB_OTG_DCTL_TCTL_2 0x00000040U /*!<Bit 2 */
+#define USB_OTG_DCTL_SGINAK 0x00000080U /*!< Set global IN NAK */
+#define USB_OTG_DCTL_CGINAK 0x00000100U /*!< Clear global IN NAK */
+#define USB_OTG_DCTL_SGONAK 0x00000200U /*!< Set global OUT NAK */
+#define USB_OTG_DCTL_CGONAK 0x00000400U /*!< Clear global OUT NAK */
+#define USB_OTG_DCTL_POPRGDNE 0x00000800U /*!< Power-on programming done */
+
+/******************** Bit definition for USB_OTG_HFIR register **************/
+#define USB_OTG_HFIR_FRIVL 0x0000FFFFU /*!< Frame interval */
+
+/******************** Bit definition for USB_OTG_HFNUM register *************/
+#define USB_OTG_HFNUM_FRNUM 0x0000FFFFU /*!< Frame number */
+#define USB_OTG_HFNUM_FTREM 0xFFFF0000U /*!< Frame time remaining */
+
+/******************** Bit definition for USB_OTG_DSTS register **************/
+#define USB_OTG_DSTS_SUSPSTS 0x00000001U /*!< Suspend status */
+
+#define USB_OTG_DSTS_ENUMSPD 0x00000006U /*!< Enumerated speed */
+#define USB_OTG_DSTS_ENUMSPD_0 0x00000002U /*!<Bit 0 */
+#define USB_OTG_DSTS_ENUMSPD_1 0x00000004U /*!<Bit 1 */
+#define USB_OTG_DSTS_EERR 0x00000008U /*!< Erratic error */
+#define USB_OTG_DSTS_FNSOF 0x003FFF00U /*!< Frame number of the received SOF */
+
+/******************** Bit definition for USB_OTG_GAHBCFG register ***********/
+#define USB_OTG_GAHBCFG_GINT 0x00000001U /*!< Global interrupt mask */
+#define USB_OTG_GAHBCFG_HBSTLEN 0x0000001EU /*!< Burst length/type */
+#define USB_OTG_GAHBCFG_HBSTLEN_0 0x00000002U /*!<Bit 0 */
+#define USB_OTG_GAHBCFG_HBSTLEN_1 0x00000004U /*!<Bit 1 */
+#define USB_OTG_GAHBCFG_HBSTLEN_2 0x00000008U /*!<Bit 2 */
+#define USB_OTG_GAHBCFG_HBSTLEN_3 0x00000010U /*!<Bit 3 */
+#define USB_OTG_GAHBCFG_DMAEN 0x00000020U /*!< DMA enable */
+#define USB_OTG_GAHBCFG_TXFELVL 0x00000080U /*!< TxFIFO empty level */
+#define USB_OTG_GAHBCFG_PTXFELVL 0x00000100U /*!< Periodic TxFIFO empty level */
+
+/******************** Bit definition for USB_OTG_GUSBCFG register ***********/
+#define USB_OTG_GUSBCFG_TOCAL 0x00000007U /*!< FS timeout calibration */
+#define USB_OTG_GUSBCFG_TOCAL_0 0x00000001U /*!<Bit 0 */
+#define USB_OTG_GUSBCFG_TOCAL_1 0x00000002U /*!<Bit 1 */
+#define USB_OTG_GUSBCFG_TOCAL_2 0x00000004U /*!<Bit 2 */
+#define USB_OTG_GUSBCFG_PHYSEL 0x00000040U /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */
+#define USB_OTG_GUSBCFG_SRPCAP 0x00000100U /*!< SRP-capable */
+#define USB_OTG_GUSBCFG_HNPCAP 0x00000200U /*!< HNP-capable */
+
+#define USB_OTG_GUSBCFG_TRDT 0x00003C00U /*!< USB turnaround time */
+#define USB_OTG_GUSBCFG_TRDT_0 0x00000400U /*!<Bit 0 */
+#define USB_OTG_GUSBCFG_TRDT_1 0x00000800U /*!<Bit 1 */
+#define USB_OTG_GUSBCFG_TRDT_2 0x00001000U /*!<Bit 2 */
+#define USB_OTG_GUSBCFG_TRDT_3 0x00002000U /*!<Bit 3 */
+#define USB_OTG_GUSBCFG_PHYLPCS 0x00008000U /*!< PHY Low-power clock select */
+#define USB_OTG_GUSBCFG_ULPIFSLS 0x00020000U /*!< ULPI FS/LS select */
+#define USB_OTG_GUSBCFG_ULPIAR 0x00040000U /*!< ULPI Auto-resume */
+#define USB_OTG_GUSBCFG_ULPICSM 0x00080000U /*!< ULPI Clock SuspendM */
+#define USB_OTG_GUSBCFG_ULPIEVBUSD 0x00100000U /*!< ULPI External VBUS Drive */
+#define USB_OTG_GUSBCFG_ULPIEVBUSI 0x00200000U /*!< ULPI external VBUS indicator */
+#define USB_OTG_GUSBCFG_TSDPS 0x00400000U /*!< TermSel DLine pulsing selection */
+#define USB_OTG_GUSBCFG_PCCI 0x00800000U /*!< Indicator complement */
+#define USB_OTG_GUSBCFG_PTCI 0x01000000U /*!< Indicator pass through */
+#define USB_OTG_GUSBCFG_ULPIIPD 0x02000000U /*!< ULPI interface protect disable */
+#define USB_OTG_GUSBCFG_FHMOD 0x20000000U /*!< Forced host mode */
+#define USB_OTG_GUSBCFG_FDMOD 0x40000000U /*!< Forced peripheral mode */
+#define USB_OTG_GUSBCFG_CTXPKT 0x80000000U /*!< Corrupt Tx packet */
+
+/******************** Bit definition for USB_OTG_GRSTCTL register ***********/
+#define USB_OTG_GRSTCTL_CSRST 0x00000001U /*!< Core soft reset */
+#define USB_OTG_GRSTCTL_HSRST 0x00000002U /*!< HCLK soft reset */
+#define USB_OTG_GRSTCTL_FCRST 0x00000004U /*!< Host frame counter reset */
+#define USB_OTG_GRSTCTL_RXFFLSH 0x00000010U /*!< RxFIFO flush */
+#define USB_OTG_GRSTCTL_TXFFLSH 0x00000020U /*!< TxFIFO flush */
+
+#define USB_OTG_GRSTCTL_TXFNUM 0x000007C0U /*!< TxFIFO number */
+#define USB_OTG_GRSTCTL_TXFNUM_0 0x00000040U /*!<Bit 0 */
+#define USB_OTG_GRSTCTL_TXFNUM_1 0x00000080U /*!<Bit 1 */
+#define USB_OTG_GRSTCTL_TXFNUM_2 0x00000100U /*!<Bit 2 */
+#define USB_OTG_GRSTCTL_TXFNUM_3 0x00000200U /*!<Bit 3 */
+#define USB_OTG_GRSTCTL_TXFNUM_4 0x00000400U /*!<Bit 4 */
+#define USB_OTG_GRSTCTL_DMAREQ 0x40000000U /*!< DMA request signal */
+#define USB_OTG_GRSTCTL_AHBIDL 0x80000000U /*!< AHB master idle */
+
+/******************** Bit definition for USB_OTG_DIEPMSK register ***********/
+#define USB_OTG_DIEPMSK_XFRCM 0x00000001U /*!< Transfer completed interrupt mask */
+#define USB_OTG_DIEPMSK_EPDM 0x00000002U /*!< Endpoint disabled interrupt mask */
+#define USB_OTG_DIEPMSK_TOM 0x00000008U /*!< Timeout condition mask (nonisochronous endpoints) */
+#define USB_OTG_DIEPMSK_ITTXFEMSK 0x00000010U /*!< IN token received when TxFIFO empty mask */
+#define USB_OTG_DIEPMSK_INEPNMM 0x00000020U /*!< IN token received with EP mismatch mask */
+#define USB_OTG_DIEPMSK_INEPNEM 0x00000040U /*!< IN endpoint NAK effective mask */
+#define USB_OTG_DIEPMSK_TXFURM 0x00000100U /*!< FIFO underrun mask */
+#define USB_OTG_DIEPMSK_BIM 0x00000200U /*!< BNA interrupt mask */
+
+/******************** Bit definition for USB_OTG_HPTXSTS register ***********/
+#define USB_OTG_HPTXSTS_PTXFSAVL 0x0000FFFFU /*!< Periodic transmit data FIFO space available */
+
+#define USB_OTG_HPTXSTS_PTXQSAV 0x00FF0000U /*!< Periodic transmit request queue space available */
+#define USB_OTG_HPTXSTS_PTXQSAV_0 0x00010000U /*!<Bit 0 */
+#define USB_OTG_HPTXSTS_PTXQSAV_1 0x00020000U /*!<Bit 1 */
+#define USB_OTG_HPTXSTS_PTXQSAV_2 0x00040000U /*!<Bit 2 */
+#define USB_OTG_HPTXSTS_PTXQSAV_3 0x00080000U /*!<Bit 3 */
+#define USB_OTG_HPTXSTS_PTXQSAV_4 0x00100000U /*!<Bit 4 */
+#define USB_OTG_HPTXSTS_PTXQSAV_5 0x00200000U /*!<Bit 5 */
+#define USB_OTG_HPTXSTS_PTXQSAV_6 0x00400000U /*!<Bit 6 */
+#define USB_OTG_HPTXSTS_PTXQSAV_7 0x00800000U /*!<Bit 7 */
+
+#define USB_OTG_HPTXSTS_PTXQTOP 0xFF000000U /*!< Top of the periodic transmit request queue */
+#define USB_OTG_HPTXSTS_PTXQTOP_0 0x01000000U /*!<Bit 0 */
+#define USB_OTG_HPTXSTS_PTXQTOP_1 0x02000000U /*!<Bit 1 */
+#define USB_OTG_HPTXSTS_PTXQTOP_2 0x04000000U /*!<Bit 2 */
+#define USB_OTG_HPTXSTS_PTXQTOP_3 0x08000000U /*!<Bit 3 */
+#define USB_OTG_HPTXSTS_PTXQTOP_4 0x10000000U /*!<Bit 4 */
+#define USB_OTG_HPTXSTS_PTXQTOP_5 0x20000000U /*!<Bit 5 */
+#define USB_OTG_HPTXSTS_PTXQTOP_6 0x40000000U /*!<Bit 6 */
+#define USB_OTG_HPTXSTS_PTXQTOP_7 0x80000000U /*!<Bit 7 */
+
+/******************** Bit definition for USB_OTG_HAINT register *************/
+#define USB_OTG_HAINT_HAINT 0x0000FFFFU /*!< Channel interrupts */
+
+/******************** Bit definition for USB_OTG_DOEPMSK register ***********/
+#define USB_OTG_DOEPMSK_XFRCM 0x00000001U /*!< Transfer completed interrupt mask */
+#define USB_OTG_DOEPMSK_EPDM 0x00000002U /*!< Endpoint disabled interrupt mask */
+#define USB_OTG_DOEPMSK_STUPM 0x00000008U /*!< SETUP phase done mask */
+#define USB_OTG_DOEPMSK_OTEPDM 0x00000010U /*!< OUT token received when endpoint disabled mask */
+#define USB_OTG_DOEPMSK_OTEPSPRM 0x00000020U /*!< Status Phase Received mask */
+#define USB_OTG_DOEPMSK_B2BSTUP 0x00000040U /*!< Back-to-back SETUP packets received mask */
+#define USB_OTG_DOEPMSK_OPEM 0x00000100U /*!< OUT packet error mask */
+#define USB_OTG_DOEPMSK_BOIM 0x00000200U /*!< BNA interrupt mask */
+
+/******************** Bit definition for USB_OTG_GINTSTS register ***********/
+#define USB_OTG_GINTSTS_CMOD 0x00000001U /*!< Current mode of operation */
+#define USB_OTG_GINTSTS_MMIS 0x00000002U /*!< Mode mismatch interrupt */
+#define USB_OTG_GINTSTS_OTGINT 0x00000004U /*!< OTG interrupt */
+#define USB_OTG_GINTSTS_SOF 0x00000008U /*!< Start of frame */
+#define USB_OTG_GINTSTS_RXFLVL 0x00000010U /*!< RxFIFO nonempty */
+#define USB_OTG_GINTSTS_NPTXFE 0x00000020U /*!< Nonperiodic TxFIFO empty */
+#define USB_OTG_GINTSTS_GINAKEFF 0x00000040U /*!< Global IN nonperiodic NAK effective */
+#define USB_OTG_GINTSTS_BOUTNAKEFF 0x00000080U /*!< Global OUT NAK effective */
+#define USB_OTG_GINTSTS_ESUSP 0x00000400U /*!< Early suspend */
+#define USB_OTG_GINTSTS_USBSUSP 0x00000800U /*!< USB suspend */
+#define USB_OTG_GINTSTS_USBRST 0x00001000U /*!< USB reset */
+#define USB_OTG_GINTSTS_ENUMDNE 0x00002000U /*!< Enumeration done */
+#define USB_OTG_GINTSTS_ISOODRP 0x00004000U /*!< Isochronous OUT packet dropped interrupt */
+#define USB_OTG_GINTSTS_EOPF 0x00008000U /*!< End of periodic frame interrupt */
+#define USB_OTG_GINTSTS_IEPINT 0x00040000U /*!< IN endpoint interrupt */
+#define USB_OTG_GINTSTS_OEPINT 0x00080000U /*!< OUT endpoint interrupt */
+#define USB_OTG_GINTSTS_IISOIXFR 0x00100000U /*!< Incomplete isochronous IN transfer */
+#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT 0x00200000U /*!< Incomplete periodic transfer */
+#define USB_OTG_GINTSTS_DATAFSUSP 0x00400000U /*!< Data fetch suspended */
+#define USB_OTG_GINTSTS_RSTDET 0x00800000U /*!< Reset detected interrupt */
+#define USB_OTG_GINTSTS_HPRTINT 0x01000000U /*!< Host port interrupt */
+#define USB_OTG_GINTSTS_HCINT 0x02000000U /*!< Host channels interrupt */
+#define USB_OTG_GINTSTS_PTXFE 0x04000000U /*!< Periodic TxFIFO empty */
+#define USB_OTG_GINTSTS_LPMINT 0x08000000U /*!< LPM interrupt */
+#define USB_OTG_GINTSTS_CIDSCHG 0x10000000U /*!< Connector ID status change */
+#define USB_OTG_GINTSTS_DISCINT 0x20000000U /*!< Disconnect detected interrupt */
+#define USB_OTG_GINTSTS_SRQINT 0x40000000U /*!< Session request/new session detected interrupt */
+#define USB_OTG_GINTSTS_WKUINT 0x80000000U /*!< Resume/remote wakeup detected interrupt */
+
+/******************** Bit definition for USB_OTG_GINTMSK register ***********/
+#define USB_OTG_GINTMSK_MMISM 0x00000002U /*!< Mode mismatch interrupt mask */
+#define USB_OTG_GINTMSK_OTGINT 0x00000004U /*!< OTG interrupt mask */
+#define USB_OTG_GINTMSK_SOFM 0x00000008U /*!< Start of frame mask */
+#define USB_OTG_GINTMSK_RXFLVLM 0x00000010U /*!< Receive FIFO nonempty mask */
+#define USB_OTG_GINTMSK_NPTXFEM 0x00000020U /*!< Nonperiodic TxFIFO empty mask */
+#define USB_OTG_GINTMSK_GINAKEFFM 0x00000040U /*!< Global nonperiodic IN NAK effective mask */
+#define USB_OTG_GINTMSK_GONAKEFFM 0x00000080U /*!< Global OUT NAK effective mask */
+#define USB_OTG_GINTMSK_ESUSPM 0x00000400U /*!< Early suspend mask */
+#define USB_OTG_GINTMSK_USBSUSPM 0x00000800U /*!< USB suspend mask */
+#define USB_OTG_GINTMSK_USBRST 0x00001000U /*!< USB reset mask */
+#define USB_OTG_GINTMSK_ENUMDNEM 0x00002000U /*!< Enumeration done mask */
+#define USB_OTG_GINTMSK_ISOODRPM 0x00004000U /*!< Isochronous OUT packet dropped interrupt mask */
+#define USB_OTG_GINTMSK_EOPFM 0x00008000U /*!< End of periodic frame interrupt mask */
+#define USB_OTG_GINTMSK_EPMISM 0x00020000U /*!< Endpoint mismatch interrupt mask */
+#define USB_OTG_GINTMSK_IEPINT 0x00040000U /*!< IN endpoints interrupt mask */
+#define USB_OTG_GINTMSK_OEPINT 0x00080000U /*!< OUT endpoints interrupt mask */
+#define USB_OTG_GINTMSK_IISOIXFRM 0x00100000U /*!< Incomplete isochronous IN transfer mask */
+#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM 0x00200000U /*!< Incomplete periodic transfer mask */
+#define USB_OTG_GINTMSK_FSUSPM 0x00400000U /*!< Data fetch suspended mask */
+#define USB_OTG_GINTMSK_RSTDETM 0x00800000U /*!< Reset detected interrupt mask */
+#define USB_OTG_GINTMSK_PRTIM 0x01000000U /*!< Host port interrupt mask */
+#define USB_OTG_GINTMSK_HCIM 0x02000000U /*!< Host channels interrupt mask */
+#define USB_OTG_GINTMSK_PTXFEM 0x04000000U /*!< Periodic TxFIFO empty mask */
+#define USB_OTG_GINTMSK_LPMINTM 0x08000000U /*!< LPM interrupt Mask */
+#define USB_OTG_GINTMSK_CIDSCHGM 0x10000000U /*!< Connector ID status change mask */
+#define USB_OTG_GINTMSK_DISCINT 0x20000000U /*!< Disconnect detected interrupt mask */
+#define USB_OTG_GINTMSK_SRQIM 0x40000000U /*!< Session request/new session detected interrupt mask */
+#define USB_OTG_GINTMSK_WUIM 0x80000000U /*!< Resume/remote wakeup detected interrupt mask */
+
+/******************** Bit definition for USB_OTG_DAINT register *************/
+#define USB_OTG_DAINT_IEPINT 0x0000FFFFU /*!< IN endpoint interrupt bits */
+#define USB_OTG_DAINT_OEPINT 0xFFFF0000U /*!< OUT endpoint interrupt bits */
+
+/******************** Bit definition for USB_OTG_HAINTMSK register **********/
+#define USB_OTG_HAINTMSK_HAINTM 0x0000FFFFU /*!< Channel interrupt mask */
+
+/******************** Bit definition for USB_OTG_GRXSTSP register ***********/
+#define USB_OTG_GRXSTSP_EPNUM 0x0000000FU /*!< IN EP interrupt mask bits */
+#define USB_OTG_GRXSTSP_BCNT 0x00007FF0U /*!< OUT EP interrupt mask bits */
+#define USB_OTG_GRXSTSP_DPID 0x00018000U /*!< OUT EP interrupt mask bits */
+#define USB_OTG_GRXSTSP_PKTSTS 0x001E0000U /*!< OUT EP interrupt mask bits */
+
+/******************** Bit definition for USB_OTG_DAINTMSK register **********/
+#define USB_OTG_DAINTMSK_IEPM 0x0000FFFFU /*!< IN EP interrupt mask bits */
+#define USB_OTG_DAINTMSK_OEPM 0xFFFF0000U /*!< OUT EP interrupt mask bits */
+
+/******************** Bit definition for OTG register ***********************/
+
+#define USB_OTG_CHNUM 0x0000000FU /*!< Channel number */
+#define USB_OTG_CHNUM_0 0x00000001U /*!<Bit 0 */
+#define USB_OTG_CHNUM_1 0x00000002U /*!<Bit 1 */
+#define USB_OTG_CHNUM_2 0x00000004U /*!<Bit 2 */
+#define USB_OTG_CHNUM_3 0x00000008U /*!<Bit 3 */
+#define USB_OTG_BCNT 0x00007FF0U /*!< Byte count */
+
+#define USB_OTG_DPID 0x00018000U /*!< Data PID */
+#define USB_OTG_DPID_0 0x00008000U /*!<Bit 0 */
+#define USB_OTG_DPID_1 0x00010000U /*!<Bit 1 */
+
+#define USB_OTG_PKTSTS 0x001E0000U /*!< Packet status */
+#define USB_OTG_PKTSTS_0 0x00020000U /*!<Bit 0 */
+#define USB_OTG_PKTSTS_1 0x00040000U /*!<Bit 1 */
+#define USB_OTG_PKTSTS_2 0x00080000U /*!<Bit 2 */
+#define USB_OTG_PKTSTS_3 0x00100000U /*!<Bit 3 */
+
+#define USB_OTG_EPNUM 0x0000000FU /*!< Endpoint number */
+#define USB_OTG_EPNUM_0 0x00000001U /*!<Bit 0 */
+#define USB_OTG_EPNUM_1 0x00000002U /*!<Bit 1 */
+#define USB_OTG_EPNUM_2 0x00000004U /*!<Bit 2 */
+#define USB_OTG_EPNUM_3 0x00000008U /*!<Bit 3 */
+
+#define USB_OTG_FRMNUM 0x01E00000U /*!< Frame number */
+#define USB_OTG_FRMNUM_0 0x00200000U /*!<Bit 0 */
+#define USB_OTG_FRMNUM_1 0x00400000U /*!<Bit 1 */
+#define USB_OTG_FRMNUM_2 0x00800000U /*!<Bit 2 */
+#define USB_OTG_FRMNUM_3 0x01000000U /*!<Bit 3 */
+
+/******************** Bit definition for OTG register ***********************/
+#define USB_OTG_CHNUM 0x0000000FU /*!< Channel number */
+#define USB_OTG_CHNUM_0 0x00000001U /*!<Bit 0 */
+#define USB_OTG_CHNUM_1 0x00000002U /*!<Bit 1 */
+#define USB_OTG_CHNUM_2 0x00000004U /*!<Bit 2 */
+#define USB_OTG_CHNUM_3 0x00000008U /*!<Bit 3 */
+#define USB_OTG_BCNT 0x00007FF0U /*!< Byte count */
+
+#define USB_OTG_DPID 0x00018000U /*!< Data PID */
+#define USB_OTG_DPID_0 0x00008000U /*!<Bit 0 */
+#define USB_OTG_DPID_1 0x00010000U /*!<Bit 1 */
+
+#define USB_OTG_PKTSTS 0x001E0000U /*!< Packet status */
+#define USB_OTG_PKTSTS_0 0x00020000U /*!<Bit 0 */
+#define USB_OTG_PKTSTS_1 0x00040000U /*!<Bit 1 */
+#define USB_OTG_PKTSTS_2 0x00080000U /*!<Bit 2 */
+#define USB_OTG_PKTSTS_3 0x00100000U /*!<Bit 3 */
+
+#define USB_OTG_EPNUM 0x0000000FU /*!< Endpoint number */
+#define USB_OTG_EPNUM_0 0x00000001U /*!<Bit 0 */
+#define USB_OTG_EPNUM_1 0x00000002U /*!<Bit 1 */
+#define USB_OTG_EPNUM_2 0x00000004U /*!<Bit 2 */
+#define USB_OTG_EPNUM_3 0x00000008U /*!<Bit 3 */
+
+#define USB_OTG_FRMNUM 0x01E00000U /*!< Frame number */
+#define USB_OTG_FRMNUM_0 0x00200000U /*!<Bit 0 */
+#define USB_OTG_FRMNUM_1 0x00400000U /*!<Bit 1 */
+#define USB_OTG_FRMNUM_2 0x00800000U /*!<Bit 2 */
+#define USB_OTG_FRMNUM_3 0x01000000U /*!<Bit 3 */
+
+/******************** Bit definition for USB_OTG_GRXFSIZ register ***********/
+#define USB_OTG_GRXFSIZ_RXFD 0x0000FFFFU /*!< RxFIFO depth */
+
+/******************** Bit definition for USB_OTG_DVBUSDIS register **********/
+#define USB_OTG_DVBUSDIS_VBUSDT 0x0000FFFFU /*!< Device VBUS discharge time */
+
+/******************** Bit definition for OTG register ***********************/
+#define USB_OTG_NPTXFSA 0x0000FFFFU /*!< Nonperiodic transmit RAM start address */
+#define USB_OTG_NPTXFD 0xFFFF0000U /*!< Nonperiodic TxFIFO depth */
+#define USB_OTG_TX0FSA 0x0000FFFFU /*!< Endpoint 0 transmit RAM start address */
+#define USB_OTG_TX0FD 0xFFFF0000U /*!< Endpoint 0 TxFIFO depth */
+
+/******************** Bit definition for USB_OTG_DVBUSPULSE register ********/
+#define USB_OTG_DVBUSPULSE_DVBUSP 0x00000FFFU /*!< Device VBUS pulsing time */
+
+/******************** Bit definition for USB_OTG_GNPTXSTS register **********/
+#define USB_OTG_GNPTXSTS_NPTXFSAV 0x0000FFFFU /*!< Nonperiodic TxFIFO space available */
+
+#define USB_OTG_GNPTXSTS_NPTQXSAV 0x00FF0000U /*!< Nonperiodic transmit request queue space available */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_0 0x00010000U /*!<Bit 0 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_1 0x00020000U /*!<Bit 1 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_2 0x00040000U /*!<Bit 2 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_3 0x00080000U /*!<Bit 3 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_4 0x00100000U /*!<Bit 4 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_5 0x00200000U /*!<Bit 5 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_6 0x00400000U /*!<Bit 6 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_7 0x00800000U /*!<Bit 7 */
+
+#define USB_OTG_GNPTXSTS_NPTXQTOP 0x7F000000U /*!< Top of the nonperiodic transmit request queue */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_0 0x01000000U /*!<Bit 0 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_1 0x02000000U /*!<Bit 1 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_2 0x04000000U /*!<Bit 2 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_3 0x08000000U /*!<Bit 3 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_4 0x10000000U /*!<Bit 4 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_5 0x20000000U /*!<Bit 5 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_6 0x40000000U /*!<Bit 6 */
+
+/******************** Bit definition for USB_OTG_DTHRCTL register ***********/
+#define USB_OTG_DTHRCTL_NONISOTHREN 0x00000001U /*!< Nonisochronous IN endpoints threshold enable */
+#define USB_OTG_DTHRCTL_ISOTHREN 0x00000002U /*!< ISO IN endpoint threshold enable */
+
+#define USB_OTG_DTHRCTL_TXTHRLEN 0x000007FCU /*!< Transmit threshold length */
+#define USB_OTG_DTHRCTL_TXTHRLEN_0 0x00000004U /*!<Bit 0 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_1 0x00000008U /*!<Bit 1 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_2 0x00000010U /*!<Bit 2 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_3 0x00000020U /*!<Bit 3 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_4 0x00000040U /*!<Bit 4 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_5 0x00000080U /*!<Bit 5 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_6 0x00000100U /*!<Bit 6 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_7 0x00000200U /*!<Bit 7 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_8 0x00000400U /*!<Bit 8 */
+#define USB_OTG_DTHRCTL_RXTHREN 0x00010000U /*!< Receive threshold enable */
+
+#define USB_OTG_DTHRCTL_RXTHRLEN 0x03FE0000U /*!< Receive threshold length */
+#define USB_OTG_DTHRCTL_RXTHRLEN_0 0x00020000U /*!<Bit 0 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_1 0x00040000U /*!<Bit 1 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_2 0x00080000U /*!<Bit 2 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_3 0x00100000U /*!<Bit 3 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_4 0x00200000U /*!<Bit 4 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_5 0x00400000U /*!<Bit 5 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_6 0x00800000U /*!<Bit 6 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_7 0x01000000U /*!<Bit 7 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_8 0x02000000U /*!<Bit 8 */
+#define USB_OTG_DTHRCTL_ARPEN 0x08000000U /*!< Arbiter parking enable */
+
+/******************** Bit definition for USB_OTG_DIEPEMPMSK register ********/
+#define USB_OTG_DIEPEMPMSK_INEPTXFEM 0x0000FFFFU /*!< IN EP Tx FIFO empty interrupt mask bits */
+
+/******************** Bit definition for USB_OTG_DEACHINT register **********/
+#define USB_OTG_DEACHINT_IEP1INT 0x00000002U /*!< IN endpoint 1interrupt bit */
+#define USB_OTG_DEACHINT_OEP1INT 0x00020000U /*!< OUT endpoint 1 interrupt bit */
+
+/******************** Bit definition for USB_OTG_GCCFG register *************/
+#define USB_OTG_GCCFG_DCDET 0x00000001U /*!< Data contact detection (DCD) status */
+#define USB_OTG_GCCFG_PDET 0x00000002U /*!< Primary detection (PD) status */
+#define USB_OTG_GCCFG_SDET 0x00000004U /*!< Secondary detection (SD) status */
+#define USB_OTG_GCCFG_PS2DET 0x00000008U /*!< DM pull-up detection status */
+#define USB_OTG_GCCFG_PWRDWN 0x00010000U /*!< Power down */
+#define USB_OTG_GCCFG_BCDEN 0x00020000U /*!< Battery charging detector (BCD) enable */
+#define USB_OTG_GCCFG_DCDEN 0x00040000U /*!< Data contact detection (DCD) mode enable*/
+#define USB_OTG_GCCFG_PDEN 0x00080000U /*!< Primary detection (PD) mode enable*/
+#define USB_OTG_GCCFG_SDEN 0x00100000U /*!< Secondary detection (SD) mode enable */
+#define USB_OTG_GCCFG_VBDEN 0x00200000U /*!< USB VBUS Detection Enable */
+
+/******************** Bit definition for USB_OTG_DEACHINTMSK register *******/
+#define USB_OTG_DEACHINTMSK_IEP1INTM 0x00000002U /*!< IN Endpoint 1 interrupt mask bit */
+#define USB_OTG_DEACHINTMSK_OEP1INTM 0x00020000U /*!< OUT Endpoint 1 interrupt mask bit */
+
+/******************** Bit definition for USB_OTG_CID register ***************/
+#define USB_OTG_CID_PRODUCT_ID 0xFFFFFFFFU /*!< Product ID field */
+
+/******************** Bit definition for USB_OTG_GLPMCFG register ***********/
+#define USB_OTG_GLPMCFG_LPMEN 0x00000001U /*!< LPM support enable */
+#define USB_OTG_GLPMCFG_LPMACK 0x00000002U /*!< LPM Token acknowledge enable */
+#define USB_OTG_GLPMCFG_BESL 0x0000003CU /*!< BESL value received with last ACKed LPM Token */
+#define USB_OTG_GLPMCFG_REMWAKE 0x00000040U /*!< bRemoteWake value received with last ACKed LPM Token */
+#define USB_OTG_GLPMCFG_L1SSEN 0x00000080U /*!< L1 shallow sleep enable */
+#define USB_OTG_GLPMCFG_BESLTHRS 0x00000F00U /*!< BESL threshold */
+#define USB_OTG_GLPMCFG_L1DSEN 0x00001000U /*!< L1 deep sleep enable */
+#define USB_OTG_GLPMCFG_LPMRSP 0x00006000U /*!< LPM response */
+#define USB_OTG_GLPMCFG_SLPSTS 0x00008000U /*!< Port sleep status */
+#define USB_OTG_GLPMCFG_L1RSMOK 0x00010000U /*!< Sleep State Resume OK */
+#define USB_OTG_GLPMCFG_LPMCHIDX 0x001E0000U /*!< LPM Channel Index */
+#define USB_OTG_GLPMCFG_LPMRCNT 0x00E00000U /*!< LPM retry count */
+#define USB_OTG_GLPMCFG_SNDLPM 0x01000000U /*!< Send LPM transaction */
+#define USB_OTG_GLPMCFG_LPMRCNTSTS 0x0E000000U /*!< LPM retry count status */
+#define USB_OTG_GLPMCFG_ENBESL 0x10000000U /*!< Enable best effort service latency */
+
+/******************** Bit definition for USB_OTG_DIEPEACHMSK1 register ******/
+#define USB_OTG_DIEPEACHMSK1_XFRCM 0x00000001U /*!< Transfer completed interrupt mask */
+#define USB_OTG_DIEPEACHMSK1_EPDM 0x00000002U /*!< Endpoint disabled interrupt mask */
+#define USB_OTG_DIEPEACHMSK1_TOM 0x00000008U /*!< Timeout condition mask (nonisochronous endpoints) */
+#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK 0x00000010U /*!< IN token received when TxFIFO empty mask */
+#define USB_OTG_DIEPEACHMSK1_INEPNMM 0x00000020U /*!< IN token received with EP mismatch mask */
+#define USB_OTG_DIEPEACHMSK1_INEPNEM 0x00000040U /*!< IN endpoint NAK effective mask */
+#define USB_OTG_DIEPEACHMSK1_TXFURM 0x00000100U /*!< FIFO underrun mask */
+#define USB_OTG_DIEPEACHMSK1_BIM 0x00000200U /*!< BNA interrupt mask */
+#define USB_OTG_DIEPEACHMSK1_NAKM 0x00002000U /*!< NAK interrupt mask */
+
+/******************** Bit definition for USB_OTG_HPRT register **************/
+#define USB_OTG_HPRT_PCSTS 0x00000001U /*!< Port connect status */
+#define USB_OTG_HPRT_PCDET 0x00000002U /*!< Port connect detected */
+#define USB_OTG_HPRT_PENA 0x00000004U /*!< Port enable */
+#define USB_OTG_HPRT_PENCHNG 0x00000008U /*!< Port enable/disable change */
+#define USB_OTG_HPRT_POCA 0x00000010U /*!< Port overcurrent active */
+#define USB_OTG_HPRT_POCCHNG 0x00000020U /*!< Port overcurrent change */
+#define USB_OTG_HPRT_PRES 0x00000040U /*!< Port resume */
+#define USB_OTG_HPRT_PSUSP 0x00000080U /*!< Port suspend */
+#define USB_OTG_HPRT_PRST 0x00000100U /*!< Port reset */
+
+#define USB_OTG_HPRT_PLSTS 0x00000C00U /*!< Port line status */
+#define USB_OTG_HPRT_PLSTS_0 0x00000400U /*!<Bit 0 */
+#define USB_OTG_HPRT_PLSTS_1 0x00000800U /*!<Bit 1 */
+#define USB_OTG_HPRT_PPWR 0x00001000U /*!< Port power */
+
+#define USB_OTG_HPRT_PTCTL 0x0001E000U /*!< Port test control */
+#define USB_OTG_HPRT_PTCTL_0 0x00002000U /*!<Bit 0 */
+#define USB_OTG_HPRT_PTCTL_1 0x00004000U /*!<Bit 1 */
+#define USB_OTG_HPRT_PTCTL_2 0x00008000U /*!<Bit 2 */
+#define USB_OTG_HPRT_PTCTL_3 0x00010000U /*!<Bit 3 */
+
+#define USB_OTG_HPRT_PSPD 0x00060000U /*!< Port speed */
+#define USB_OTG_HPRT_PSPD_0 0x00020000U /*!<Bit 0 */
+#define USB_OTG_HPRT_PSPD_1 0x00040000U /*!<Bit 1 */
+
+/******************** Bit definition for USB_OTG_DOEPEACHMSK1 register ******/
+#define USB_OTG_DOEPEACHMSK1_XFRCM 0x00000001U /*!< Transfer completed interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_EPDM 0x00000002U /*!< Endpoint disabled interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_TOM 0x00000008U /*!< Timeout condition mask */
+#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK 0x00000010U /*!< IN token received when TxFIFO empty mask */
+#define USB_OTG_DOEPEACHMSK1_INEPNMM 0x00000020U /*!< IN token received with EP mismatch mask */
+#define USB_OTG_DOEPEACHMSK1_INEPNEM 0x00000040U /*!< IN endpoint NAK effective mask */
+#define USB_OTG_DOEPEACHMSK1_TXFURM 0x00000100U /*!< OUT packet error mask */
+#define USB_OTG_DOEPEACHMSK1_BIM 0x00000200U /*!< BNA interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_BERRM 0x00001000U /*!< Bubble error interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_NAKM 0x00002000U /*!< NAK interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_NYETM 0x00004000U /*!< NYET interrupt mask */
+
+/******************** Bit definition for USB_OTG_HPTXFSIZ register **********/
+#define USB_OTG_HPTXFSIZ_PTXSA 0x0000FFFFU /*!< Host periodic TxFIFO start address */
+#define USB_OTG_HPTXFSIZ_PTXFD 0xFFFF0000U /*!< Host periodic TxFIFO depth */
+
+/******************** Bit definition for USB_OTG_DIEPCTL register ***********/
+#define USB_OTG_DIEPCTL_MPSIZ 0x000007FFU /*!< Maximum packet size */
+#define USB_OTG_DIEPCTL_USBAEP 0x00008000U /*!< USB active endpoint */
+#define USB_OTG_DIEPCTL_EONUM_DPID 0x00010000U /*!< Even/odd frame */
+#define USB_OTG_DIEPCTL_NAKSTS 0x00020000U /*!< NAK status */
+
+#define USB_OTG_DIEPCTL_EPTYP 0x000C0000U /*!< Endpoint type */
+#define USB_OTG_DIEPCTL_EPTYP_0 0x00040000U /*!<Bit 0 */
+#define USB_OTG_DIEPCTL_EPTYP_1 0x00080000U /*!<Bit 1 */
+#define USB_OTG_DIEPCTL_STALL 0x00200000U /*!< STALL handshake */
+
+#define USB_OTG_DIEPCTL_TXFNUM 0x03C00000U /*!< TxFIFO number */
+#define USB_OTG_DIEPCTL_TXFNUM_0 0x00400000U /*!<Bit 0 */
+#define USB_OTG_DIEPCTL_TXFNUM_1 0x00800000U /*!<Bit 1 */
+#define USB_OTG_DIEPCTL_TXFNUM_2 0x01000000U /*!<Bit 2 */
+#define USB_OTG_DIEPCTL_TXFNUM_3 0x02000000U /*!<Bit 3 */
+#define USB_OTG_DIEPCTL_CNAK 0x04000000U /*!< Clear NAK */
+#define USB_OTG_DIEPCTL_SNAK 0x08000000U /*!< Set NAK */
+#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM 0x10000000U /*!< Set DATA0 PID */
+#define USB_OTG_DIEPCTL_SODDFRM 0x20000000U /*!< Set odd frame */
+#define USB_OTG_DIEPCTL_EPDIS 0x40000000U /*!< Endpoint disable */
+#define USB_OTG_DIEPCTL_EPENA 0x80000000U /*!< Endpoint enable */
+
+/******************** Bit definition for USB_OTG_HCCHAR register ************/
+#define USB_OTG_HCCHAR_MPSIZ 0x000007FFU /*!< Maximum packet size */
+
+#define USB_OTG_HCCHAR_EPNUM 0x00007800U /*!< Endpoint number */
+#define USB_OTG_HCCHAR_EPNUM_0 0x00000800U /*!<Bit 0 */
+#define USB_OTG_HCCHAR_EPNUM_1 0x00001000U /*!<Bit 1 */
+#define USB_OTG_HCCHAR_EPNUM_2 0x00002000U /*!<Bit 2 */
+#define USB_OTG_HCCHAR_EPNUM_3 0x00004000U /*!<Bit 3 */
+#define USB_OTG_HCCHAR_EPDIR 0x00008000U /*!< Endpoint direction */
+#define USB_OTG_HCCHAR_LSDEV 0x00020000U /*!< Low-speed device */
+
+#define USB_OTG_HCCHAR_EPTYP 0x000C0000U /*!< Endpoint type */
+#define USB_OTG_HCCHAR_EPTYP_0 0x00040000U /*!<Bit 0 */
+#define USB_OTG_HCCHAR_EPTYP_1 0x00080000U /*!<Bit 1 */
+
+#define USB_OTG_HCCHAR_MC 0x00300000U /*!< Multi Count (MC) / Error Count (EC) */
+#define USB_OTG_HCCHAR_MC_0 0x00100000U /*!<Bit 0 */
+#define USB_OTG_HCCHAR_MC_1 0x00200000U /*!<Bit 1 */
+
+#define USB_OTG_HCCHAR_DAD 0x1FC00000U /*!< Device address */
+#define USB_OTG_HCCHAR_DAD_0 0x00400000U /*!<Bit 0 */
+#define USB_OTG_HCCHAR_DAD_1 0x00800000U /*!<Bit 1 */
+#define USB_OTG_HCCHAR_DAD_2 0x01000000U /*!<Bit 2 */
+#define USB_OTG_HCCHAR_DAD_3 0x02000000U /*!<Bit 3 */
+#define USB_OTG_HCCHAR_DAD_4 0x04000000U /*!<Bit 4 */
+#define USB_OTG_HCCHAR_DAD_5 0x08000000U /*!<Bit 5 */
+#define USB_OTG_HCCHAR_DAD_6 0x10000000U /*!<Bit 6 */
+#define USB_OTG_HCCHAR_ODDFRM 0x20000000U /*!< Odd frame */
+#define USB_OTG_HCCHAR_CHDIS 0x40000000U /*!< Channel disable */
+#define USB_OTG_HCCHAR_CHENA 0x80000000U /*!< Channel enable */
+
+/******************** Bit definition for USB_OTG_HCSPLT register ************/
+
+#define USB_OTG_HCSPLT_PRTADDR 0x0000007FU /*!< Port address */
+#define USB_OTG_HCSPLT_PRTADDR_0 0x00000001U /*!<Bit 0 */
+#define USB_OTG_HCSPLT_PRTADDR_1 0x00000002U /*!<Bit 1 */
+#define USB_OTG_HCSPLT_PRTADDR_2 0x00000004U /*!<Bit 2 */
+#define USB_OTG_HCSPLT_PRTADDR_3 0x00000008U /*!<Bit 3 */
+#define USB_OTG_HCSPLT_PRTADDR_4 0x00000010U /*!<Bit 4 */
+#define USB_OTG_HCSPLT_PRTADDR_5 0x00000020U /*!<Bit 5 */
+#define USB_OTG_HCSPLT_PRTADDR_6 0x00000040U /*!<Bit 6 */
+
+#define USB_OTG_HCSPLT_HUBADDR 0x00003F80U /*!< Hub address */
+#define USB_OTG_HCSPLT_HUBADDR_0 0x00000080U /*!<Bit 0 */
+#define USB_OTG_HCSPLT_HUBADDR_1 0x00000100U /*!<Bit 1 */
+#define USB_OTG_HCSPLT_HUBADDR_2 0x00000200U /*!<Bit 2 */
+#define USB_OTG_HCSPLT_HUBADDR_3 0x00000400U /*!<Bit 3 */
+#define USB_OTG_HCSPLT_HUBADDR_4 0x00000800U /*!<Bit 4 */
+#define USB_OTG_HCSPLT_HUBADDR_5 0x00001000U /*!<Bit 5 */
+#define USB_OTG_HCSPLT_HUBADDR_6 0x00002000U /*!<Bit 6 */
+
+#define USB_OTG_HCSPLT_XACTPOS 0x0000C000U /*!< XACTPOS */
+#define USB_OTG_HCSPLT_XACTPOS_0 0x00004000U /*!<Bit 0 */
+#define USB_OTG_HCSPLT_XACTPOS_1 0x00008000U /*!<Bit 1 */
+#define USB_OTG_HCSPLT_COMPLSPLT 0x00010000U /*!< Do complete split */
+#define USB_OTG_HCSPLT_SPLITEN 0x80000000U /*!< Split enable */
+
+/******************** Bit definition for USB_OTG_HCINT register *************/
+#define USB_OTG_HCINT_XFRC 0x00000001U /*!< Transfer completed */
+#define USB_OTG_HCINT_CHH 0x00000002U /*!< Channel halted */
+#define USB_OTG_HCINT_AHBERR 0x00000004U /*!< AHB error */
+#define USB_OTG_HCINT_STALL 0x00000008U /*!< STALL response received interrupt */
+#define USB_OTG_HCINT_NAK 0x00000010U /*!< NAK response received interrupt */
+#define USB_OTG_HCINT_ACK 0x00000020U /*!< ACK response received/transmitted interrupt */
+#define USB_OTG_HCINT_NYET 0x00000040U /*!< Response received interrupt */
+#define USB_OTG_HCINT_TXERR 0x00000080U /*!< Transaction error */
+#define USB_OTG_HCINT_BBERR 0x00000100U /*!< Babble error */
+#define USB_OTG_HCINT_FRMOR 0x00000200U /*!< Frame overrun */
+#define USB_OTG_HCINT_DTERR 0x00000400U /*!< Data toggle error */
+
+/******************** Bit definition for USB_OTG_DIEPINT register ***********/
+#define USB_OTG_DIEPINT_XFRC 0x00000001U /*!< Transfer completed interrupt */
+#define USB_OTG_DIEPINT_EPDISD 0x00000002U /*!< Endpoint disabled interrupt */
+#define USB_OTG_DIEPINT_TOC 0x00000008U /*!< Timeout condition */
+#define USB_OTG_DIEPINT_ITTXFE 0x00000010U /*!< IN token received when TxFIFO is empty */
+#define USB_OTG_DIEPINT_INEPNE 0x00000040U /*!< IN endpoint NAK effective */
+#define USB_OTG_DIEPINT_TXFE 0x00000080U /*!< Transmit FIFO empty */
+#define USB_OTG_DIEPINT_TXFIFOUDRN 0x00000100U /*!< Transmit Fifo Underrun */
+#define USB_OTG_DIEPINT_BNA 0x00000200U /*!< Buffer not available interrupt */
+#define USB_OTG_DIEPINT_PKTDRPSTS 0x00000800U /*!< Packet dropped status */
+#define USB_OTG_DIEPINT_BERR 0x00001000U /*!< Babble error interrupt */
+#define USB_OTG_DIEPINT_NAK 0x00002000U /*!< NAK interrupt */
+
+/******************** Bit definition for USB_OTG_HCINTMSK register **********/
+#define USB_OTG_HCINTMSK_XFRCM 0x00000001U /*!< Transfer completed mask */
+#define USB_OTG_HCINTMSK_CHHM 0x00000002U /*!< Channel halted mask */
+#define USB_OTG_HCINTMSK_AHBERR 0x00000004U /*!< AHB error */
+#define USB_OTG_HCINTMSK_STALLM 0x00000008U /*!< STALL response received interrupt mask */
+#define USB_OTG_HCINTMSK_NAKM 0x00000010U /*!< NAK response received interrupt mask */
+#define USB_OTG_HCINTMSK_ACKM 0x00000020U /*!< ACK response received/transmitted interrupt mask */
+#define USB_OTG_HCINTMSK_NYET 0x00000040U /*!< response received interrupt mask */
+#define USB_OTG_HCINTMSK_TXERRM 0x00000080U /*!< Transaction error mask */
+#define USB_OTG_HCINTMSK_BBERRM 0x00000100U /*!< Babble error mask */
+#define USB_OTG_HCINTMSK_FRMORM 0x00000200U /*!< Frame overrun mask */
+#define USB_OTG_HCINTMSK_DTERRM 0x00000400U /*!< Data toggle error mask */
+
+/******************** Bit definition for USB_OTG_DIEPTSIZ register **********/
+
+#define USB_OTG_DIEPTSIZ_XFRSIZ 0x0007FFFFU /*!< Transfer size */
+#define USB_OTG_DIEPTSIZ_PKTCNT 0x1FF80000U /*!< Packet count */
+#define USB_OTG_DIEPTSIZ_MULCNT 0x60000000U /*!< Packet count */
+/******************** Bit definition for USB_OTG_HCTSIZ register ************/
+#define USB_OTG_HCTSIZ_XFRSIZ 0x0007FFFFU /*!< Transfer size */
+#define USB_OTG_HCTSIZ_PKTCNT 0x1FF80000U /*!< Packet count */
+#define USB_OTG_HCTSIZ_DOPING 0x80000000U /*!< Do PING */
+#define USB_OTG_HCTSIZ_DPID 0x60000000U /*!< Data PID */
+#define USB_OTG_HCTSIZ_DPID_0 0x20000000U /*!<Bit 0 */
+#define USB_OTG_HCTSIZ_DPID_1 0x40000000U /*!<Bit 1 */
+
+/******************** Bit definition for USB_OTG_DIEPDMA register ***********/
+#define USB_OTG_DIEPDMA_DMAADDR 0xFFFFFFFFU /*!< DMA address */
+
+/******************** Bit definition for USB_OTG_HCDMA register *************/
+#define USB_OTG_HCDMA_DMAADDR 0xFFFFFFFFU /*!< DMA address */
+
+/******************** Bit definition for USB_OTG_DTXFSTS register ***********/
+#define USB_OTG_DTXFSTS_INEPTFSAV 0x0000FFFFU /*!< IN endpoint TxFIFO space available */
+
+/******************** Bit definition for USB_OTG_DIEPTXF register ***********/
+#define USB_OTG_DIEPTXF_INEPTXSA 0x0000FFFFU /*!< IN endpoint FIFOx transmit RAM start address */
+#define USB_OTG_DIEPTXF_INEPTXFD 0xFFFF0000U /*!< IN endpoint TxFIFO depth */
+
+/******************** Bit definition for USB_OTG_DOEPCTL register ***********/
+
+#define USB_OTG_DOEPCTL_MPSIZ 0x000007FFU /*!< Maximum packet size */ /*!<Bit 1 */
+#define USB_OTG_DOEPCTL_USBAEP 0x00008000U /*!< USB active endpoint */
+#define USB_OTG_DOEPCTL_NAKSTS 0x00020000U /*!< NAK status */
+#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM 0x10000000U /*!< Set DATA0 PID */
+#define USB_OTG_DOEPCTL_SODDFRM 0x20000000U /*!< Set odd frame */
+#define USB_OTG_DOEPCTL_EPTYP 0x000C0000U /*!< Endpoint type */
+#define USB_OTG_DOEPCTL_EPTYP_0 0x00040000U /*!<Bit 0 */
+#define USB_OTG_DOEPCTL_EPTYP_1 0x00080000U /*!<Bit 1 */
+#define USB_OTG_DOEPCTL_SNPM 0x00100000U /*!< Snoop mode */
+#define USB_OTG_DOEPCTL_STALL 0x00200000U /*!< STALL handshake */
+#define USB_OTG_DOEPCTL_CNAK 0x04000000U /*!< Clear NAK */
+#define USB_OTG_DOEPCTL_SNAK 0x08000000U /*!< Set NAK */
+#define USB_OTG_DOEPCTL_EPDIS 0x40000000U /*!< Endpoint disable */
+#define USB_OTG_DOEPCTL_EPENA 0x80000000U /*!< Endpoint enable */
+
+/******************** Bit definition for USB_OTG_DOEPINT register ***********/
+#define USB_OTG_DOEPINT_XFRC 0x00000001U /*!< Transfer completed interrupt */
+#define USB_OTG_DOEPINT_EPDISD 0x00000002U /*!< Endpoint disabled interrupt */
+#define USB_OTG_DOEPINT_STUP 0x00000008U /*!< SETUP phase done */
+#define USB_OTG_DOEPINT_OTEPDIS 0x00000010U /*!< OUT token received when endpoint disabled */
+#define USB_OTG_DOEPINT_OTEPSPR 0x00000020U /*!< Status Phase Received For Control Write */
+#define USB_OTG_DOEPINT_B2BSTUP 0x00000040U /*!< Back-to-back SETUP packets received */
+#define USB_OTG_DOEPINT_NYET 0x00004000U /*!< NYET interrupt */
+
+/******************** Bit definition for USB_OTG_DOEPTSIZ register **********/
+
+#define USB_OTG_DOEPTSIZ_XFRSIZ 0x0007FFFFU /*!< Transfer size */
+#define USB_OTG_DOEPTSIZ_PKTCNT 0x1FF80000U /*!< Packet count */
+
+#define USB_OTG_DOEPTSIZ_STUPCNT 0x60000000U /*!< SETUP packet count */
+#define USB_OTG_DOEPTSIZ_STUPCNT_0 0x20000000U /*!<Bit 0 */
+#define USB_OTG_DOEPTSIZ_STUPCNT_1 0x40000000U /*!<Bit 1 */
+
+/******************** Bit definition for PCGCCTL register *******************/
+#define USB_OTG_PCGCCTL_STOPCLK 0x00000001U /*!< SETUP packet count */
+#define USB_OTG_PCGCCTL_GATECLK 0x00000002U /*!<Bit 0 */
+#define USB_OTG_PCGCCTL_PHYSUSP 0x00000010U /*!<Bit 1 */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup Exported_macros
+ * @{
+ */
+
+/******************************* ADC Instances ********************************/
+#define IS_ADC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
+
+/******************************* CAN Instances ********************************/
+#define IS_CAN_ALL_INSTANCE(INSTANCE) (((INSTANCE) == CAN1) || \
+ ((INSTANCE) == CAN2))
+/****************************** DFSDM Instances *******************************/
+#define IS_DFSDM_FILTER_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DFSDM1_Filter0) || \
+ ((INSTANCE) == DFSDM1_Filter1))
+
+#define IS_DFSDM_CHANNEL_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DFSDM1_Channel0) || \
+ ((INSTANCE) == DFSDM1_Channel1) || \
+ ((INSTANCE) == DFSDM1_Channel2) || \
+ ((INSTANCE) == DFSDM1_Channel3))
+
+/******************************* CRC Instances ********************************/
+#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
+
+/******************************** DMA Instances *******************************/
+#define IS_DMA_STREAM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0) || \
+ ((INSTANCE) == DMA1_Stream1) || \
+ ((INSTANCE) == DMA1_Stream2) || \
+ ((INSTANCE) == DMA1_Stream3) || \
+ ((INSTANCE) == DMA1_Stream4) || \
+ ((INSTANCE) == DMA1_Stream5) || \
+ ((INSTANCE) == DMA1_Stream6) || \
+ ((INSTANCE) == DMA1_Stream7) || \
+ ((INSTANCE) == DMA2_Stream0) || \
+ ((INSTANCE) == DMA2_Stream1) || \
+ ((INSTANCE) == DMA2_Stream2) || \
+ ((INSTANCE) == DMA2_Stream3) || \
+ ((INSTANCE) == DMA2_Stream4) || \
+ ((INSTANCE) == DMA2_Stream5) || \
+ ((INSTANCE) == DMA2_Stream6) || \
+ ((INSTANCE) == DMA2_Stream7))
+
+/******************************* GPIO Instances *******************************/
+#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
+ ((INSTANCE) == GPIOB) || \
+ ((INSTANCE) == GPIOC) || \
+ ((INSTANCE) == GPIOD) || \
+ ((INSTANCE) == GPIOE) || \
+ ((INSTANCE) == GPIOF) || \
+ ((INSTANCE) == GPIOG) || \
+ ((INSTANCE) == GPIOH))
+
+/******************************** I2C Instances *******************************/
+#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
+ ((INSTANCE) == I2C2) || \
+ ((INSTANCE) == I2C3))
+
+/******************************** I2S Instances *******************************/
+#define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
+ ((INSTANCE) == SPI2) || \
+ ((INSTANCE) == SPI3) || \
+ ((INSTANCE) == SPI4) || \
+ ((INSTANCE) == SPI5))
+
+/*************************** I2S Extended Instances ***************************/
+#define IS_I2S_ALL_INSTANCE_EXT(PERIPH) (((INSTANCE) == SPI2) || \
+ ((INSTANCE) == SPI3) || \
+ ((INSTANCE) == I2S2ext) || \
+ ((INSTANCE) == I2S3ext))
+
+/******************************* RNG Instances ********************************/
+#define IS_RNG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RNG)
+
+/****************************** RTC Instances *********************************/
+#define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
+
+/******************************** SPI Instances *******************************/
+#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
+ ((INSTANCE) == SPI2) || \
+ ((INSTANCE) == SPI3) || \
+ ((INSTANCE) == SPI4) || \
+ ((INSTANCE) == SPI5))
+/*************************** SPI Extended Instances ***************************/
+#define IS_SPI_ALL_INSTANCE_EXT(INSTANCE) (((INSTANCE) == SPI1) || \
+ ((INSTANCE) == SPI2) || \
+ ((INSTANCE) == SPI3) || \
+ ((INSTANCE) == SPI4) || \
+ ((INSTANCE) == SPI5) || \
+ ((INSTANCE) == I2S2ext) || \
+ ((INSTANCE) == I2S3ext))
+
+/****************** TIM Instances : All supported instances *******************/
+#define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM6) || \
+ ((INSTANCE) == TIM7) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM9) || \
+ ((INSTANCE) == TIM10) || \
+ ((INSTANCE) == TIM11) || \
+ ((INSTANCE) == TIM12) || \
+ ((INSTANCE) == TIM13) || \
+ ((INSTANCE) == TIM14))
+
+/************* TIM Instances : at least 1 capture/compare channel *************/
+#define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM9) || \
+ ((INSTANCE) == TIM10) || \
+ ((INSTANCE) == TIM11) || \
+ ((INSTANCE) == TIM12) || \
+ ((INSTANCE) == TIM13) || \
+ ((INSTANCE) == TIM14))
+
+/************ TIM Instances : at least 2 capture/compare channels *************/
+#define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM9) || \
+ ((INSTANCE) == TIM12))
+
+/************ TIM Instances : at least 3 capture/compare channels *************/
+#define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8))
+
+/************ TIM Instances : at least 4 capture/compare channels *************/
+#define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8))
+
+/******************** TIM Instances : Advanced-control timers *****************/
+#define IS_TIM_ADVANCED_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM8))
+
+/******************* TIM Instances : Timer input XOR function *****************/
+#define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8))
+
+/****************** TIM Instances : DMA requests generation (UDE) *************/
+#define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM6) || \
+ ((INSTANCE) == TIM7) || \
+ ((INSTANCE) == TIM8))
+
+/************ TIM Instances : DMA requests generation (CCxDE) *****************/
+#define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8))
+
+/************ TIM Instances : DMA requests generation (COMDE) *****************/
+#define IS_TIM_CCDMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8))
+
+/******************** TIM Instances : DMA burst feature ***********************/
+#define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8))
+
+/****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/
+#define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM6) || \
+ ((INSTANCE) == TIM7) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM9) || \
+ ((INSTANCE) == TIM12))
+
+/*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
+#define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM9) || \
+ ((INSTANCE) == TIM12))
+
+/********************** TIM Instances : 32 bit Counter ************************/
+#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)(((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM5))
+
+/***************** TIM Instances : external trigger input available ************/
+#define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8))
+
+/****************** TIM Instances : remapping capability **********************/
+#define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM11))
+
+/******************* TIM Instances : output(s) available **********************/
+#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
+ ((((INSTANCE) == TIM1) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM2) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM3) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM4) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM5) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM8) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM9) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2))) \
+ || \
+ (((INSTANCE) == TIM10) && \
+ (((CHANNEL) == TIM_CHANNEL_1))) \
+ || \
+ (((INSTANCE) == TIM11) && \
+ (((CHANNEL) == TIM_CHANNEL_1))) \
+ || \
+ (((INSTANCE) == TIM12) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2))) \
+ || \
+ (((INSTANCE) == TIM13) && \
+ (((CHANNEL) == TIM_CHANNEL_1))) \
+ || \
+ (((INSTANCE) == TIM14) && \
+ (((CHANNEL) == TIM_CHANNEL_1))))
+
+/************ TIM Instances : complementary output(s) available ***************/
+#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
+ ((((INSTANCE) == TIM1) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3))) \
+ || \
+ (((INSTANCE) == TIM8) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3))))
+
+/******************** USART Instances : Synchronous mode **********************/
+#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3) || \
+ ((INSTANCE) == USART6))
+
+/******************** UART Instances : Asynchronous mode **********************/
+#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3) || \
+ ((INSTANCE) == USART6))
+
+/****************** UART Instances : Hardware Flow control ********************/
+#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3) || \
+ ((INSTANCE) == USART6))
+
+/********************* UART Instances : Smart card mode ***********************/
+#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3) || \
+ ((INSTANCE) == USART6))
+
+/*********************** UART Instances : IRDA mode ***************************/
+#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3) || \
+ ((INSTANCE) == USART6))
+
+/*********************** PCD Instances ****************************************/
+#define IS_PCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS))
+
+/*********************** HCD Instances ****************************************/
+#define IS_HCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS))
+
+/****************************** IWDG Instances ********************************/
+#define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
+
+/****************************** WWDG Instances ********************************/
+#define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
+
+/****************************** QSPI Instances ********************************/
+#define IS_QSPI_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == QUADSPI)
+
+/***************************** FMPI2C Instances *******************************/
+#define IS_FMPI2C_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == FMPI2C1)
+
+/****************************** SDIO Instances ********************************/
+#define IS_SDIO_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SDIO)
+
+/****************************** USB Instances ********************************/
+#define IS_USB_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB_OTG_FS)
+
+/****************************** USB Exported Constants ************************/
+#define USB_OTG_FS_HOST_MAX_CHANNEL_NBR 12U
+#define USB_OTG_FS_MAX_IN_ENDPOINTS 6U /* Including EP0 */
+#define USB_OTG_FS_MAX_OUT_ENDPOINTS 6U /* Including EP0 */
+#define USB_OTG_FS_TOTAL_FIFO_SIZE 1280U /* in Bytes */
+
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* __STM32F412Zx_H */
+
+
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Device/ST/STM32F4xx/Include/stm32f415xx.h b/Device/ST/STM32F4xx/Include/stm32f415xx.h
new file mode 100644
index 0000000..3de878d
--- /dev/null
+++ b/Device/ST/STM32F4xx/Include/stm32f415xx.h
@@ -0,0 +1,7684 @@
+/**
+ ******************************************************************************
+ * @file stm32f415xx.h
+ * @author MCD Application Team
+ * @version V2.5.0
+ * @date 22-April-2016
+ * @brief CMSIS STM32F415xx Device Peripheral Access Layer Header File.
+ *
+ * This file contains:
+ * - Data structures and the address mapping for all peripherals
+ * - peripherals registers declarations and bits definition
+ * - Macros to access peripheral’s registers hardware
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/** @addtogroup CMSIS
+ * @{
+ */
+
+/** @addtogroup stm32f415xx
+ * @{
+ */
+
+#ifndef __STM32F415xx_H
+#define __STM32F415xx_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif /* __cplusplus */
+
+
+/** @addtogroup Configuration_section_for_CMSIS
+ * @{
+ */
+
+/**
+ * @brief Configuration of the Cortex-M4 Processor and Core Peripherals
+ */
+#define __CM4_REV 0x0001U /*!< Core revision r0p1 */
+#define __MPU_PRESENT 1U /*!< STM32F4XX provides an MPU */
+#define __NVIC_PRIO_BITS 4U /*!< STM32F4XX uses 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */
+#define __FPU_PRESENT 1U /*!< FPU present */
+
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_interrupt_number_definition
+ * @{
+ */
+
+/**
+ * @brief STM32F4XX Interrupt Number Definition, according to the selected device
+ * in @ref Library_configuration_section
+ */
+typedef enum
+{
+/****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/
+ NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
+ MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */
+ BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */
+ UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */
+ SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */
+ DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */
+ PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */
+ SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */
+/****** STM32 specific Interrupt Numbers **********************************************************************/
+ WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
+ PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */
+ TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */
+ RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */
+ FLASH_IRQn = 4, /*!< FLASH global Interrupt */
+ RCC_IRQn = 5, /*!< RCC global Interrupt */
+ EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */
+ EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */
+ EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */
+ EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */
+ EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */
+ DMA1_Stream0_IRQn = 11, /*!< DMA1 Stream 0 global Interrupt */
+ DMA1_Stream1_IRQn = 12, /*!< DMA1 Stream 1 global Interrupt */
+ DMA1_Stream2_IRQn = 13, /*!< DMA1 Stream 2 global Interrupt */
+ DMA1_Stream3_IRQn = 14, /*!< DMA1 Stream 3 global Interrupt */
+ DMA1_Stream4_IRQn = 15, /*!< DMA1 Stream 4 global Interrupt */
+ DMA1_Stream5_IRQn = 16, /*!< DMA1 Stream 5 global Interrupt */
+ DMA1_Stream6_IRQn = 17, /*!< DMA1 Stream 6 global Interrupt */
+ ADC_IRQn = 18, /*!< ADC1, ADC2 and ADC3 global Interrupts */
+ CAN1_TX_IRQn = 19, /*!< CAN1 TX Interrupt */
+ CAN1_RX0_IRQn = 20, /*!< CAN1 RX0 Interrupt */
+ CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */
+ CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */
+ EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
+ TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break interrupt and TIM9 global interrupt */
+ TIM1_UP_TIM10_IRQn = 25, /*!< TIM1 Update Interrupt and TIM10 global interrupt */
+ TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */
+ TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
+ TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
+ TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
+ TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
+ I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
+ I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
+ I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
+ I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
+ SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
+ SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
+ USART1_IRQn = 37, /*!< USART1 global Interrupt */
+ USART2_IRQn = 38, /*!< USART2 global Interrupt */
+ USART3_IRQn = 39, /*!< USART3 global Interrupt */
+ EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
+ RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */
+ OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS Wakeup through EXTI line interrupt */
+ TIM8_BRK_TIM12_IRQn = 43, /*!< TIM8 Break Interrupt and TIM12 global interrupt */
+ TIM8_UP_TIM13_IRQn = 44, /*!< TIM8 Update Interrupt and TIM13 global interrupt */
+ TIM8_TRG_COM_TIM14_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */
+ TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */
+ DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */
+ FSMC_IRQn = 48, /*!< FSMC global Interrupt */
+ SDIO_IRQn = 49, /*!< SDIO global Interrupt */
+ TIM5_IRQn = 50, /*!< TIM5 global Interrupt */
+ SPI3_IRQn = 51, /*!< SPI3 global Interrupt */
+ UART4_IRQn = 52, /*!< UART4 global Interrupt */
+ UART5_IRQn = 53, /*!< UART5 global Interrupt */
+ TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC1&2 underrun error interrupts */
+ TIM7_IRQn = 55, /*!< TIM7 global interrupt */
+ DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */
+ DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */
+ DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */
+ DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */
+ DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */
+ CAN2_TX_IRQn = 63, /*!< CAN2 TX Interrupt */
+ CAN2_RX0_IRQn = 64, /*!< CAN2 RX0 Interrupt */
+ CAN2_RX1_IRQn = 65, /*!< CAN2 RX1 Interrupt */
+ CAN2_SCE_IRQn = 66, /*!< CAN2 SCE Interrupt */
+ OTG_FS_IRQn = 67, /*!< USB OTG FS global Interrupt */
+ DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */
+ DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */
+ DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */
+ USART6_IRQn = 71, /*!< USART6 global interrupt */
+ I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */
+ I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */
+ OTG_HS_EP1_OUT_IRQn = 74, /*!< USB OTG HS End Point 1 Out global interrupt */
+ OTG_HS_EP1_IN_IRQn = 75, /*!< USB OTG HS End Point 1 In global interrupt */
+ OTG_HS_WKUP_IRQn = 76, /*!< USB OTG HS Wakeup through EXTI interrupt */
+ OTG_HS_IRQn = 77, /*!< USB OTG HS global interrupt */
+ CRYP_IRQn = 79, /*!< CRYP crypto global interrupt */
+ HASH_RNG_IRQn = 80, /*!< Hash and Rng global interrupt */
+ FPU_IRQn = 81 /*!< FPU global interrupt */
+} IRQn_Type;
+
+/**
+ * @}
+ */
+
+#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
+#include "system_stm32f4xx.h"
+#include <stdint.h>
+
+/** @addtogroup Peripheral_registers_structures
+ * @{
+ */
+
+/**
+ * @brief Analog to Digital Converter
+ */
+
+typedef struct
+{
+ __IO uint32_t SR; /*!< ADC status register, Address offset: 0x00 */
+ __IO uint32_t CR1; /*!< ADC control register 1, Address offset: 0x04 */
+ __IO uint32_t CR2; /*!< ADC control register 2, Address offset: 0x08 */
+ __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x0C */
+ __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x10 */
+ __IO uint32_t JOFR1; /*!< ADC injected channel data offset register 1, Address offset: 0x14 */
+ __IO uint32_t JOFR2; /*!< ADC injected channel data offset register 2, Address offset: 0x18 */
+ __IO uint32_t JOFR3; /*!< ADC injected channel data offset register 3, Address offset: 0x1C */
+ __IO uint32_t JOFR4; /*!< ADC injected channel data offset register 4, Address offset: 0x20 */
+ __IO uint32_t HTR; /*!< ADC watchdog higher threshold register, Address offset: 0x24 */
+ __IO uint32_t LTR; /*!< ADC watchdog lower threshold register, Address offset: 0x28 */
+ __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x2C */
+ __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x30 */
+ __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x34 */
+ __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x38*/
+ __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x3C */
+ __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x40 */
+ __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x44 */
+ __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x48 */
+ __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x4C */
+} ADC_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1 base address + 0x300 */
+ __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1 base address + 0x304 */
+ __IO uint32_t CDR; /*!< ADC common regular data register for dual
+ AND triple modes, Address offset: ADC1 base address + 0x308 */
+} ADC_Common_TypeDef;
+
+
+/**
+ * @brief Controller Area Network TxMailBox
+ */
+
+typedef struct
+{
+ __IO uint32_t TIR; /*!< CAN TX mailbox identifier register */
+ __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */
+ __IO uint32_t TDLR; /*!< CAN mailbox data low register */
+ __IO uint32_t TDHR; /*!< CAN mailbox data high register */
+} CAN_TxMailBox_TypeDef;
+
+/**
+ * @brief Controller Area Network FIFOMailBox
+ */
+
+typedef struct
+{
+ __IO uint32_t RIR; /*!< CAN receive FIFO mailbox identifier register */
+ __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */
+ __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */
+ __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */
+} CAN_FIFOMailBox_TypeDef;
+
+/**
+ * @brief Controller Area Network FilterRegister
+ */
+
+typedef struct
+{
+ __IO uint32_t FR1; /*!< CAN Filter bank register 1 */
+ __IO uint32_t FR2; /*!< CAN Filter bank register 1 */
+} CAN_FilterRegister_TypeDef;
+
+/**
+ * @brief Controller Area Network
+ */
+
+typedef struct
+{
+ __IO uint32_t MCR; /*!< CAN master control register, Address offset: 0x00 */
+ __IO uint32_t MSR; /*!< CAN master status register, Address offset: 0x04 */
+ __IO uint32_t TSR; /*!< CAN transmit status register, Address offset: 0x08 */
+ __IO uint32_t RF0R; /*!< CAN receive FIFO 0 register, Address offset: 0x0C */
+ __IO uint32_t RF1R; /*!< CAN receive FIFO 1 register, Address offset: 0x10 */
+ __IO uint32_t IER; /*!< CAN interrupt enable register, Address offset: 0x14 */
+ __IO uint32_t ESR; /*!< CAN error status register, Address offset: 0x18 */
+ __IO uint32_t BTR; /*!< CAN bit timing register, Address offset: 0x1C */
+ uint32_t RESERVED0[88]; /*!< Reserved, 0x020 - 0x17F */
+ CAN_TxMailBox_TypeDef sTxMailBox[3]; /*!< CAN Tx MailBox, Address offset: 0x180 - 0x1AC */
+ CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; /*!< CAN FIFO MailBox, Address offset: 0x1B0 - 0x1CC */
+ uint32_t RESERVED1[12]; /*!< Reserved, 0x1D0 - 0x1FF */
+ __IO uint32_t FMR; /*!< CAN filter master register, Address offset: 0x200 */
+ __IO uint32_t FM1R; /*!< CAN filter mode register, Address offset: 0x204 */
+ uint32_t RESERVED2; /*!< Reserved, 0x208 */
+ __IO uint32_t FS1R; /*!< CAN filter scale register, Address offset: 0x20C */
+ uint32_t RESERVED3; /*!< Reserved, 0x210 */
+ __IO uint32_t FFA1R; /*!< CAN filter FIFO assignment register, Address offset: 0x214 */
+ uint32_t RESERVED4; /*!< Reserved, 0x218 */
+ __IO uint32_t FA1R; /*!< CAN filter activation register, Address offset: 0x21C */
+ uint32_t RESERVED5[8]; /*!< Reserved, 0x220-0x23F */
+ CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register, Address offset: 0x240-0x31C */
+} CAN_TypeDef;
+
+/**
+ * @brief CRC calculation unit
+ */
+
+typedef struct
+{
+ __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
+ __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
+ uint8_t RESERVED0; /*!< Reserved, 0x05 */
+ uint16_t RESERVED1; /*!< Reserved, 0x06 */
+ __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
+} CRC_TypeDef;
+
+/**
+ * @brief Digital to Analog Converter
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */
+ __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */
+ __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
+ __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */
+ __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */
+ __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
+ __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */
+ __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */
+ __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */
+ __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */
+ __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */
+ __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */
+ __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */
+ __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */
+} DAC_TypeDef;
+
+/**
+ * @brief Debug MCU
+ */
+
+typedef struct
+{
+ __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
+ __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
+ __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */
+ __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */
+}DBGMCU_TypeDef;
+
+
+/**
+ * @brief DMA Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< DMA stream x configuration register */
+ __IO uint32_t NDTR; /*!< DMA stream x number of data register */
+ __IO uint32_t PAR; /*!< DMA stream x peripheral address register */
+ __IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */
+ __IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */
+ __IO uint32_t FCR; /*!< DMA stream x FIFO control register */
+} DMA_Stream_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t LISR; /*!< DMA low interrupt status register, Address offset: 0x00 */
+ __IO uint32_t HISR; /*!< DMA high interrupt status register, Address offset: 0x04 */
+ __IO uint32_t LIFCR; /*!< DMA low interrupt flag clear register, Address offset: 0x08 */
+ __IO uint32_t HIFCR; /*!< DMA high interrupt flag clear register, Address offset: 0x0C */
+} DMA_TypeDef;
+
+
+/**
+ * @brief External Interrupt/Event Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t IMR; /*!< EXTI Interrupt mask register, Address offset: 0x00 */
+ __IO uint32_t EMR; /*!< EXTI Event mask register, Address offset: 0x04 */
+ __IO uint32_t RTSR; /*!< EXTI Rising trigger selection register, Address offset: 0x08 */
+ __IO uint32_t FTSR; /*!< EXTI Falling trigger selection register, Address offset: 0x0C */
+ __IO uint32_t SWIER; /*!< EXTI Software interrupt event register, Address offset: 0x10 */
+ __IO uint32_t PR; /*!< EXTI Pending register, Address offset: 0x14 */
+} EXTI_TypeDef;
+
+/**
+ * @brief FLASH Registers
+ */
+
+typedef struct
+{
+ __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */
+ __IO uint32_t KEYR; /*!< FLASH key register, Address offset: 0x04 */
+ __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x08 */
+ __IO uint32_t SR; /*!< FLASH status register, Address offset: 0x0C */
+ __IO uint32_t CR; /*!< FLASH control register, Address offset: 0x10 */
+ __IO uint32_t OPTCR; /*!< FLASH option control register , Address offset: 0x14 */
+ __IO uint32_t OPTCR1; /*!< FLASH option control register 1, Address offset: 0x18 */
+} FLASH_TypeDef;
+
+
+/**
+ * @brief Flexible Static Memory Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */
+} FSMC_Bank1_TypeDef;
+
+/**
+ * @brief Flexible Static Memory Controller Bank1E
+ */
+
+typedef struct
+{
+ __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */
+} FSMC_Bank1E_TypeDef;
+
+/**
+ * @brief Flexible Static Memory Controller Bank2
+ */
+
+typedef struct
+{
+ __IO uint32_t PCR2; /*!< NAND Flash control register 2, Address offset: 0x60 */
+ __IO uint32_t SR2; /*!< NAND Flash FIFO status and interrupt register 2, Address offset: 0x64 */
+ __IO uint32_t PMEM2; /*!< NAND Flash Common memory space timing register 2, Address offset: 0x68 */
+ __IO uint32_t PATT2; /*!< NAND Flash Attribute memory space timing register 2, Address offset: 0x6C */
+ uint32_t RESERVED0; /*!< Reserved, 0x70 */
+ __IO uint32_t ECCR2; /*!< NAND Flash ECC result registers 2, Address offset: 0x74 */
+ uint32_t RESERVED1; /*!< Reserved, 0x78 */
+ uint32_t RESERVED2; /*!< Reserved, 0x7C */
+ __IO uint32_t PCR3; /*!< NAND Flash control register 3, Address offset: 0x80 */
+ __IO uint32_t SR3; /*!< NAND Flash FIFO status and interrupt register 3, Address offset: 0x84 */
+ __IO uint32_t PMEM3; /*!< NAND Flash Common memory space timing register 3, Address offset: 0x88 */
+ __IO uint32_t PATT3; /*!< NAND Flash Attribute memory space timing register 3, Address offset: 0x8C */
+ uint32_t RESERVED3; /*!< Reserved, 0x90 */
+ __IO uint32_t ECCR3; /*!< NAND Flash ECC result registers 3, Address offset: 0x94 */
+} FSMC_Bank2_3_TypeDef;
+
+/**
+ * @brief Flexible Static Memory Controller Bank4
+ */
+
+typedef struct
+{
+ __IO uint32_t PCR4; /*!< PC Card control register 4, Address offset: 0xA0 */
+ __IO uint32_t SR4; /*!< PC Card FIFO status and interrupt register 4, Address offset: 0xA4 */
+ __IO uint32_t PMEM4; /*!< PC Card Common memory space timing register 4, Address offset: 0xA8 */
+ __IO uint32_t PATT4; /*!< PC Card Attribute memory space timing register 4, Address offset: 0xAC */
+ __IO uint32_t PIO4; /*!< PC Card I/O space timing register 4, Address offset: 0xB0 */
+} FSMC_Bank4_TypeDef;
+
+
+/**
+ * @brief General Purpose I/O
+ */
+
+typedef struct
+{
+ __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
+ __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */
+ __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */
+ __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
+ __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
+ __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
+ __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */
+ __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
+ __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */
+} GPIO_TypeDef;
+
+/**
+ * @brief System configuration controller
+ */
+
+typedef struct
+{
+ __IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */
+ __IO uint32_t PMC; /*!< SYSCFG peripheral mode configuration register, Address offset: 0x04 */
+ __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
+ uint32_t RESERVED[2]; /*!< Reserved, 0x18-0x1C */
+ __IO uint32_t CMPCR; /*!< SYSCFG Compensation cell control register, Address offset: 0x20 */
+} SYSCFG_TypeDef;
+
+/**
+ * @brief Inter-integrated Circuit Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */
+ __IO uint32_t OAR1; /*!< I2C Own address register 1, Address offset: 0x08 */
+ __IO uint32_t OAR2; /*!< I2C Own address register 2, Address offset: 0x0C */
+ __IO uint32_t DR; /*!< I2C Data register, Address offset: 0x10 */
+ __IO uint32_t SR1; /*!< I2C Status register 1, Address offset: 0x14 */
+ __IO uint32_t SR2; /*!< I2C Status register 2, Address offset: 0x18 */
+ __IO uint32_t CCR; /*!< I2C Clock control register, Address offset: 0x1C */
+ __IO uint32_t TRISE; /*!< I2C TRISE register, Address offset: 0x20 */
+ __IO uint32_t FLTR; /*!< I2C FLTR register, Address offset: 0x24 */
+} I2C_TypeDef;
+
+/**
+ * @brief Independent WATCHDOG
+ */
+
+typedef struct
+{
+ __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */
+ __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */
+ __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */
+ __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */
+} IWDG_TypeDef;
+
+/**
+ * @brief Power Control
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */
+ __IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */
+} PWR_TypeDef;
+
+/**
+ * @brief Reset and Clock Control
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */
+ __IO uint32_t PLLCFGR; /*!< RCC PLL configuration register, Address offset: 0x04 */
+ __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x08 */
+ __IO uint32_t CIR; /*!< RCC clock interrupt register, Address offset: 0x0C */
+ __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x10 */
+ __IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x14 */
+ __IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0x18 */
+ uint32_t RESERVED0; /*!< Reserved, 0x1C */
+ __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x20 */
+ __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x24 */
+ uint32_t RESERVED1[2]; /*!< Reserved, 0x28-0x2C */
+ __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clock register, Address offset: 0x30 */
+ __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clock register, Address offset: 0x34 */
+ __IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clock register, Address offset: 0x38 */
+ uint32_t RESERVED2; /*!< Reserved, 0x3C */
+ __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x40 */
+ __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x44 */
+ uint32_t RESERVED3[2]; /*!< Reserved, 0x48-0x4C */
+ __IO uint32_t AHB1LPENR; /*!< RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 */
+ __IO uint32_t AHB2LPENR; /*!< RCC AHB2 peripheral clock enable in low power mode register, Address offset: 0x54 */
+ __IO uint32_t AHB3LPENR; /*!< RCC AHB3 peripheral clock enable in low power mode register, Address offset: 0x58 */
+ uint32_t RESERVED4; /*!< Reserved, 0x5C */
+ __IO uint32_t APB1LPENR; /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 */
+ __IO uint32_t APB2LPENR; /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 */
+ uint32_t RESERVED5[2]; /*!< Reserved, 0x68-0x6C */
+ __IO uint32_t BDCR; /*!< RCC Backup domain control register, Address offset: 0x70 */
+ __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x74 */
+ uint32_t RESERVED6[2]; /*!< Reserved, 0x78-0x7C */
+ __IO uint32_t SSCGR; /*!< RCC spread spectrum clock generation register, Address offset: 0x80 */
+ __IO uint32_t PLLI2SCFGR; /*!< RCC PLLI2S configuration register, Address offset: 0x84 */
+
+} RCC_TypeDef;
+
+/**
+ * @brief Real-Time Clock
+ */
+
+typedef struct
+{
+ __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
+ __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */
+ __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */
+ __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */
+ __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */
+ __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */
+ __IO uint32_t CALIBR; /*!< RTC calibration register, Address offset: 0x18 */
+ __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */
+ __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */
+ __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */
+ __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */
+ __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */
+ __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */
+ __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */
+ __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */
+ __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */
+ __IO uint32_t TAFCR; /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */
+ __IO uint32_t ALRMASSR;/*!< RTC alarm A sub second register, Address offset: 0x44 */
+ __IO uint32_t ALRMBSSR;/*!< RTC alarm B sub second register, Address offset: 0x48 */
+ uint32_t RESERVED7; /*!< Reserved, 0x4C */
+ __IO uint32_t BKP0R; /*!< RTC backup register 1, Address offset: 0x50 */
+ __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */
+ __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */
+ __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */
+ __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */
+ __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */
+ __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */
+ __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */
+ __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */
+ __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */
+ __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */
+ __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */
+ __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */
+ __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */
+ __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */
+ __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */
+ __IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */
+ __IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */
+ __IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */
+ __IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */
+} RTC_TypeDef;
+
+
+/**
+ * @brief SD host Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t POWER; /*!< SDIO power control register, Address offset: 0x00 */
+ __IO uint32_t CLKCR; /*!< SDI clock control register, Address offset: 0x04 */
+ __IO uint32_t ARG; /*!< SDIO argument register, Address offset: 0x08 */
+ __IO uint32_t CMD; /*!< SDIO command register, Address offset: 0x0C */
+ __I uint32_t RESPCMD; /*!< SDIO command response register, Address offset: 0x10 */
+ __I uint32_t RESP1; /*!< SDIO response 1 register, Address offset: 0x14 */
+ __I uint32_t RESP2; /*!< SDIO response 2 register, Address offset: 0x18 */
+ __I uint32_t RESP3; /*!< SDIO response 3 register, Address offset: 0x1C */
+ __I uint32_t RESP4; /*!< SDIO response 4 register, Address offset: 0x20 */
+ __IO uint32_t DTIMER; /*!< SDIO data timer register, Address offset: 0x24 */
+ __IO uint32_t DLEN; /*!< SDIO data length register, Address offset: 0x28 */
+ __IO uint32_t DCTRL; /*!< SDIO data control register, Address offset: 0x2C */
+ __I uint32_t DCOUNT; /*!< SDIO data counter register, Address offset: 0x30 */
+ __I uint32_t STA; /*!< SDIO status register, Address offset: 0x34 */
+ __IO uint32_t ICR; /*!< SDIO interrupt clear register, Address offset: 0x38 */
+ __IO uint32_t MASK; /*!< SDIO mask register, Address offset: 0x3C */
+ uint32_t RESERVED0[2]; /*!< Reserved, 0x40-0x44 */
+ __I uint32_t FIFOCNT; /*!< SDIO FIFO counter register, Address offset: 0x48 */
+ uint32_t RESERVED1[13]; /*!< Reserved, 0x4C-0x7C */
+ __IO uint32_t FIFO; /*!< SDIO data FIFO register, Address offset: 0x80 */
+} SDIO_TypeDef;
+
+/**
+ * @brief Serial Peripheral Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t CR1; /*!< SPI control register 1 (not used in I2S mode), Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< SPI control register 2, Address offset: 0x04 */
+ __IO uint32_t SR; /*!< SPI status register, Address offset: 0x08 */
+ __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */
+ __IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
+ __IO uint32_t RXCRCR; /*!< SPI RX CRC register (not used in I2S mode), Address offset: 0x14 */
+ __IO uint32_t TXCRCR; /*!< SPI TX CRC register (not used in I2S mode), Address offset: 0x18 */
+ __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */
+ __IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */
+} SPI_TypeDef;
+
+/**
+ * @brief TIM
+ */
+
+typedef struct
+{
+ __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
+ __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */
+ __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
+ __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
+ __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
+ __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
+ __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
+ __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
+ __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
+ __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */
+ __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
+ __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */
+ __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
+ __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
+ __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
+ __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
+ __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
+ __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
+ __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */
+ __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */
+} TIM_TypeDef;
+
+/**
+ * @brief Universal Synchronous Asynchronous Receiver Transmitter
+ */
+
+typedef struct
+{
+ __IO uint32_t SR; /*!< USART Status register, Address offset: 0x00 */
+ __IO uint32_t DR; /*!< USART Data register, Address offset: 0x04 */
+ __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x08 */
+ __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x0C */
+ __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x10 */
+ __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x14 */
+ __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x18 */
+} USART_TypeDef;
+
+/**
+ * @brief Window WATCHDOG
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
+ __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
+ __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
+} WWDG_TypeDef;
+
+/**
+ * @brief Crypto Processor
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< CRYP control register, Address offset: 0x00 */
+ __IO uint32_t SR; /*!< CRYP status register, Address offset: 0x04 */
+ __IO uint32_t DR; /*!< CRYP data input register, Address offset: 0x08 */
+ __IO uint32_t DOUT; /*!< CRYP data output register, Address offset: 0x0C */
+ __IO uint32_t DMACR; /*!< CRYP DMA control register, Address offset: 0x10 */
+ __IO uint32_t IMSCR; /*!< CRYP interrupt mask set/clear register, Address offset: 0x14 */
+ __IO uint32_t RISR; /*!< CRYP raw interrupt status register, Address offset: 0x18 */
+ __IO uint32_t MISR; /*!< CRYP masked interrupt status register, Address offset: 0x1C */
+ __IO uint32_t K0LR; /*!< CRYP key left register 0, Address offset: 0x20 */
+ __IO uint32_t K0RR; /*!< CRYP key right register 0, Address offset: 0x24 */
+ __IO uint32_t K1LR; /*!< CRYP key left register 1, Address offset: 0x28 */
+ __IO uint32_t K1RR; /*!< CRYP key right register 1, Address offset: 0x2C */
+ __IO uint32_t K2LR; /*!< CRYP key left register 2, Address offset: 0x30 */
+ __IO uint32_t K2RR; /*!< CRYP key right register 2, Address offset: 0x34 */
+ __IO uint32_t K3LR; /*!< CRYP key left register 3, Address offset: 0x38 */
+ __IO uint32_t K3RR; /*!< CRYP key right register 3, Address offset: 0x3C */
+ __IO uint32_t IV0LR; /*!< CRYP initialization vector left-word register 0, Address offset: 0x40 */
+ __IO uint32_t IV0RR; /*!< CRYP initialization vector right-word register 0, Address offset: 0x44 */
+ __IO uint32_t IV1LR; /*!< CRYP initialization vector left-word register 1, Address offset: 0x48 */
+ __IO uint32_t IV1RR; /*!< CRYP initialization vector right-word register 1, Address offset: 0x4C */
+ __IO uint32_t CSGCMCCM0R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 0, Address offset: 0x50 */
+ __IO uint32_t CSGCMCCM1R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 1, Address offset: 0x54 */
+ __IO uint32_t CSGCMCCM2R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 2, Address offset: 0x58 */
+ __IO uint32_t CSGCMCCM3R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 3, Address offset: 0x5C */
+ __IO uint32_t CSGCMCCM4R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 4, Address offset: 0x60 */
+ __IO uint32_t CSGCMCCM5R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 5, Address offset: 0x64 */
+ __IO uint32_t CSGCMCCM6R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 6, Address offset: 0x68 */
+ __IO uint32_t CSGCMCCM7R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 7, Address offset: 0x6C */
+ __IO uint32_t CSGCM0R; /*!< CRYP GCM/GMAC context swap register 0, Address offset: 0x70 */
+ __IO uint32_t CSGCM1R; /*!< CRYP GCM/GMAC context swap register 1, Address offset: 0x74 */
+ __IO uint32_t CSGCM2R; /*!< CRYP GCM/GMAC context swap register 2, Address offset: 0x78 */
+ __IO uint32_t CSGCM3R; /*!< CRYP GCM/GMAC context swap register 3, Address offset: 0x7C */
+ __IO uint32_t CSGCM4R; /*!< CRYP GCM/GMAC context swap register 4, Address offset: 0x80 */
+ __IO uint32_t CSGCM5R; /*!< CRYP GCM/GMAC context swap register 5, Address offset: 0x84 */
+ __IO uint32_t CSGCM6R; /*!< CRYP GCM/GMAC context swap register 6, Address offset: 0x88 */
+ __IO uint32_t CSGCM7R; /*!< CRYP GCM/GMAC context swap register 7, Address offset: 0x8C */
+} CRYP_TypeDef;
+
+/**
+ * @brief HASH
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< HASH control register, Address offset: 0x00 */
+ __IO uint32_t DIN; /*!< HASH data input register, Address offset: 0x04 */
+ __IO uint32_t STR; /*!< HASH start register, Address offset: 0x08 */
+ __IO uint32_t HR[5]; /*!< HASH digest registers, Address offset: 0x0C-0x1C */
+ __IO uint32_t IMR; /*!< HASH interrupt enable register, Address offset: 0x20 */
+ __IO uint32_t SR; /*!< HASH status register, Address offset: 0x24 */
+ uint32_t RESERVED[52]; /*!< Reserved, 0x28-0xF4 */
+ __IO uint32_t CSR[54]; /*!< HASH context swap registers, Address offset: 0x0F8-0x1CC */
+} HASH_TypeDef;
+
+/**
+ * @brief HASH_DIGEST
+ */
+
+typedef struct
+{
+ __IO uint32_t HR[8]; /*!< HASH digest registers, Address offset: 0x310-0x32C */
+} HASH_DIGEST_TypeDef;
+
+/**
+ * @brief RNG
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */
+ __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */
+ __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */
+} RNG_TypeDef;
+
+
+
+/**
+ * @brief __USB_OTG_Core_register
+ */
+typedef struct
+{
+ __IO uint32_t GOTGCTL; /*!< USB_OTG Control and Status Register Address offset : 0x00 */
+ __IO uint32_t GOTGINT; /*!< USB_OTG Interrupt Register Address offset : 0x04 */
+ __IO uint32_t GAHBCFG; /*!< Core AHB Configuration Register Address offset : 0x08 */
+ __IO uint32_t GUSBCFG; /*!< Core USB Configuration Register Address offset : 0x0C */
+ __IO uint32_t GRSTCTL; /*!< Core Reset Register Address offset : 0x10 */
+ __IO uint32_t GINTSTS; /*!< Core Interrupt Register Address offset : 0x14 */
+ __IO uint32_t GINTMSK; /*!< Core Interrupt Mask Register Address offset : 0x18 */
+ __IO uint32_t GRXSTSR; /*!< Receive Sts Q Read Register Address offset : 0x1C */
+ __IO uint32_t GRXSTSP; /*!< Receive Sts Q Read & POP Register Address offset : 0x20 */
+ __IO uint32_t GRXFSIZ; /* Receive FIFO Size Register Address offset : 0x24 */
+ __IO uint32_t DIEPTXF0_HNPTXFSIZ; /*!< EP0 / Non Periodic Tx FIFO Size Register Address offset : 0x28 */
+ __IO uint32_t HNPTXSTS; /*!< Non Periodic Tx FIFO/Queue Sts reg Address offset : 0x2C */
+ uint32_t Reserved30[2]; /* Reserved Address offset : 0x30 */
+ __IO uint32_t GCCFG; /*!< General Purpose IO Register Address offset : 0x38 */
+ __IO uint32_t CID; /*!< User ID Register Address offset : 0x3C */
+ uint32_t Reserved40[48]; /*!< Reserved Address offset : 0x40-0xFF */
+ __IO uint32_t HPTXFSIZ; /*!< Host Periodic Tx FIFO Size Reg Address offset : 0x100 */
+ __IO uint32_t DIEPTXF[0x0F]; /*!< dev Periodic Transmit FIFO */
+}
+USB_OTG_GlobalTypeDef;
+
+
+
+/**
+ * @brief __device_Registers
+ */
+typedef struct
+{
+ __IO uint32_t DCFG; /*!< dev Configuration Register Address offset : 0x800 */
+ __IO uint32_t DCTL; /*!< dev Control Register Address offset : 0x804 */
+ __IO uint32_t DSTS; /*!< dev Status Register (RO) Address offset : 0x808 */
+ uint32_t Reserved0C; /*!< Reserved Address offset : 0x80C */
+ __IO uint32_t DIEPMSK; /* !< dev IN Endpoint Mask Address offset : 0x810 */
+ __IO uint32_t DOEPMSK; /*!< dev OUT Endpoint Mask Address offset : 0x814 */
+ __IO uint32_t DAINT; /*!< dev All Endpoints Itr Reg Address offset : 0x818 */
+ __IO uint32_t DAINTMSK; /*!< dev All Endpoints Itr Mask Address offset : 0x81C */
+ uint32_t Reserved20; /*!< Reserved Address offset : 0x820 */
+ uint32_t Reserved9; /*!< Reserved Address offset : 0x824 */
+ __IO uint32_t DVBUSDIS; /*!< dev VBUS discharge Register Address offset : 0x828 */
+ __IO uint32_t DVBUSPULSE; /*!< dev VBUS Pulse Register Address offset : 0x82C */
+ __IO uint32_t DTHRCTL; /*!< dev thr Address offset : 0x830 */
+ __IO uint32_t DIEPEMPMSK; /*!< dev empty msk Address offset : 0x834 */
+ __IO uint32_t DEACHINT; /*!< dedicated EP interrupt Address offset : 0x838 */
+ __IO uint32_t DEACHMSK; /*!< dedicated EP msk Address offset : 0x83C */
+ uint32_t Reserved40; /*!< dedicated EP mask Address offset : 0x840 */
+ __IO uint32_t DINEP1MSK; /*!< dedicated EP mask Address offset : 0x844 */
+ uint32_t Reserved44[15]; /*!< Reserved Address offset : 0x844-0x87C */
+ __IO uint32_t DOUTEP1MSK; /*!< dedicated EP msk Address offset : 0x884 */
+}
+USB_OTG_DeviceTypeDef;
+
+
+/**
+ * @brief __IN_Endpoint-Specific_Register
+ */
+typedef struct
+{
+ __IO uint32_t DIEPCTL; /* dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h */
+ uint32_t Reserved04; /* Reserved 900h + (ep_num * 20h) + 04h */
+ __IO uint32_t DIEPINT; /* dev IN Endpoint Itr Reg 900h + (ep_num * 20h) + 08h */
+ uint32_t Reserved0C; /* Reserved 900h + (ep_num * 20h) + 0Ch */
+ __IO uint32_t DIEPTSIZ; /* IN Endpoint Txfer Size 900h + (ep_num * 20h) + 10h */
+ __IO uint32_t DIEPDMA; /* IN Endpoint DMA Address Reg 900h + (ep_num * 20h) + 14h */
+ __IO uint32_t DTXFSTS; /*IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h */
+ uint32_t Reserved18; /* Reserved 900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch */
+}
+USB_OTG_INEndpointTypeDef;
+
+
+/**
+ * @brief __OUT_Endpoint-Specific_Registers
+ */
+typedef struct
+{
+ __IO uint32_t DOEPCTL; /* dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h*/
+ uint32_t Reserved04; /* Reserved B00h + (ep_num * 20h) + 04h*/
+ __IO uint32_t DOEPINT; /* dev OUT Endpoint Itr Reg B00h + (ep_num * 20h) + 08h*/
+ uint32_t Reserved0C; /* Reserved B00h + (ep_num * 20h) + 0Ch*/
+ __IO uint32_t DOEPTSIZ; /* dev OUT Endpoint Txfer Size B00h + (ep_num * 20h) + 10h*/
+ __IO uint32_t DOEPDMA; /* dev OUT Endpoint DMA Address B00h + (ep_num * 20h) + 14h*/
+ uint32_t Reserved18[2]; /* Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch*/
+}
+USB_OTG_OUTEndpointTypeDef;
+
+
+/**
+ * @brief __Host_Mode_Register_Structures
+ */
+typedef struct
+{
+ __IO uint32_t HCFG; /* Host Configuration Register 400h*/
+ __IO uint32_t HFIR; /* Host Frame Interval Register 404h*/
+ __IO uint32_t HFNUM; /* Host Frame Nbr/Frame Remaining 408h*/
+ uint32_t Reserved40C; /* Reserved 40Ch*/
+ __IO uint32_t HPTXSTS; /* Host Periodic Tx FIFO/ Queue Status 410h*/
+ __IO uint32_t HAINT; /* Host All Channels Interrupt Register 414h*/
+ __IO uint32_t HAINTMSK; /* Host All Channels Interrupt Mask 418h*/
+}
+USB_OTG_HostTypeDef;
+
+
+/**
+ * @brief __Host_Channel_Specific_Registers
+ */
+typedef struct
+{
+ __IO uint32_t HCCHAR;
+ __IO uint32_t HCSPLT;
+ __IO uint32_t HCINT;
+ __IO uint32_t HCINTMSK;
+ __IO uint32_t HCTSIZ;
+ __IO uint32_t HCDMA;
+ uint32_t Reserved[2];
+}
+USB_OTG_HostChannelTypeDef;
+
+
+/**
+ * @brief Peripheral_memory_map
+ */
+#define FLASH_BASE 0x08000000U /*!< FLASH(up to 1 MB) base address in the alias region */
+#define CCMDATARAM_BASE 0x10000000U /*!< CCM(core coupled memory) data RAM(64 KB) base address in the alias region */
+#define SRAM1_BASE 0x20000000U /*!< SRAM1(112 KB) base address in the alias region */
+#define SRAM2_BASE 0x2001C000U /*!< SRAM2(16 KB) base address in the alias region */
+#define PERIPH_BASE 0x40000000U /*!< Peripheral base address in the alias region */
+#define BKPSRAM_BASE 0x40024000U /*!< Backup SRAM(4 KB) base address in the alias region */
+#define FSMC_R_BASE 0xA0000000U /*!< FSMC registers base address */
+#define SRAM1_BB_BASE 0x22000000U /*!< SRAM1(112 KB) base address in the bit-band region */
+#define SRAM2_BB_BASE 0x22380000U /*!< SRAM2(16 KB) base address in the bit-band region */
+#define PERIPH_BB_BASE 0x42000000U /*!< Peripheral base address in the bit-band region */
+#define BKPSRAM_BB_BASE 0x42480000U /*!< Backup SRAM(4 KB) base address in the bit-band region */
+#define FLASH_END 0x080FFFFFU /*!< FLASH end address */
+#define CCMDATARAM_END 0x1000FFFFU /*!< CCM data RAM end address */
+
+/* Legacy defines */
+#define SRAM_BASE SRAM1_BASE
+#define SRAM_BB_BASE SRAM1_BB_BASE
+
+
+/*!< Peripheral memory map */
+#define APB1PERIPH_BASE PERIPH_BASE
+#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000U)
+#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000U)
+#define AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000U)
+
+/*!< APB1 peripherals */
+#define TIM2_BASE (APB1PERIPH_BASE + 0x0000U)
+#define TIM3_BASE (APB1PERIPH_BASE + 0x0400U)
+#define TIM4_BASE (APB1PERIPH_BASE + 0x0800U)
+#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00U)
+#define TIM6_BASE (APB1PERIPH_BASE + 0x1000U)
+#define TIM7_BASE (APB1PERIPH_BASE + 0x1400U)
+#define TIM12_BASE (APB1PERIPH_BASE + 0x1800U)
+#define TIM13_BASE (APB1PERIPH_BASE + 0x1C00U)
+#define TIM14_BASE (APB1PERIPH_BASE + 0x2000U)
+#define RTC_BASE (APB1PERIPH_BASE + 0x2800U)
+#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00U)
+#define IWDG_BASE (APB1PERIPH_BASE + 0x3000U)
+#define I2S2ext_BASE (APB1PERIPH_BASE + 0x3400U)
+#define SPI2_BASE (APB1PERIPH_BASE + 0x3800U)
+#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00U)
+#define I2S3ext_BASE (APB1PERIPH_BASE + 0x4000U)
+#define USART2_BASE (APB1PERIPH_BASE + 0x4400U)
+#define USART3_BASE (APB1PERIPH_BASE + 0x4800U)
+#define UART4_BASE (APB1PERIPH_BASE + 0x4C00U)
+#define UART5_BASE (APB1PERIPH_BASE + 0x5000U)
+#define I2C1_BASE (APB1PERIPH_BASE + 0x5400U)
+#define I2C2_BASE (APB1PERIPH_BASE + 0x5800U)
+#define I2C3_BASE (APB1PERIPH_BASE + 0x5C00U)
+#define CAN1_BASE (APB1PERIPH_BASE + 0x6400U)
+#define CAN2_BASE (APB1PERIPH_BASE + 0x6800U)
+#define PWR_BASE (APB1PERIPH_BASE + 0x7000U)
+#define DAC_BASE (APB1PERIPH_BASE + 0x7400U)
+
+/*!< APB2 peripherals */
+#define TIM1_BASE (APB2PERIPH_BASE + 0x0000U)
+#define TIM8_BASE (APB2PERIPH_BASE + 0x0400U)
+#define USART1_BASE (APB2PERIPH_BASE + 0x1000U)
+#define USART6_BASE (APB2PERIPH_BASE + 0x1400U)
+#define ADC1_BASE (APB2PERIPH_BASE + 0x2000U)
+#define ADC2_BASE (APB2PERIPH_BASE + 0x2100U)
+#define ADC3_BASE (APB2PERIPH_BASE + 0x2200U)
+#define ADC_BASE (APB2PERIPH_BASE + 0x2300U)
+#define SDIO_BASE (APB2PERIPH_BASE + 0x2C00U)
+#define SPI1_BASE (APB2PERIPH_BASE + 0x3000U)
+#define SYSCFG_BASE (APB2PERIPH_BASE + 0x3800U)
+#define EXTI_BASE (APB2PERIPH_BASE + 0x3C00U)
+#define TIM9_BASE (APB2PERIPH_BASE + 0x4000U)
+#define TIM10_BASE (APB2PERIPH_BASE + 0x4400U)
+#define TIM11_BASE (APB2PERIPH_BASE + 0x4800U)
+
+/*!< AHB1 peripherals */
+#define GPIOA_BASE (AHB1PERIPH_BASE + 0x0000U)
+#define GPIOB_BASE (AHB1PERIPH_BASE + 0x0400U)
+#define GPIOC_BASE (AHB1PERIPH_BASE + 0x0800U)
+#define GPIOD_BASE (AHB1PERIPH_BASE + 0x0C00U)
+#define GPIOE_BASE (AHB1PERIPH_BASE + 0x1000U)
+#define GPIOF_BASE (AHB1PERIPH_BASE + 0x1400U)
+#define GPIOG_BASE (AHB1PERIPH_BASE + 0x1800U)
+#define GPIOH_BASE (AHB1PERIPH_BASE + 0x1C00U)
+#define GPIOI_BASE (AHB1PERIPH_BASE + 0x2000U)
+#define CRC_BASE (AHB1PERIPH_BASE + 0x3000U)
+#define RCC_BASE (AHB1PERIPH_BASE + 0x3800U)
+#define FLASH_R_BASE (AHB1PERIPH_BASE + 0x3C00U)
+#define DMA1_BASE (AHB1PERIPH_BASE + 0x6000U)
+#define DMA1_Stream0_BASE (DMA1_BASE + 0x010U)
+#define DMA1_Stream1_BASE (DMA1_BASE + 0x028U)
+#define DMA1_Stream2_BASE (DMA1_BASE + 0x040U)
+#define DMA1_Stream3_BASE (DMA1_BASE + 0x058U)
+#define DMA1_Stream4_BASE (DMA1_BASE + 0x070U)
+#define DMA1_Stream5_BASE (DMA1_BASE + 0x088U)
+#define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0U)
+#define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8U)
+#define DMA2_BASE (AHB1PERIPH_BASE + 0x6400U)
+#define DMA2_Stream0_BASE (DMA2_BASE + 0x010U)
+#define DMA2_Stream1_BASE (DMA2_BASE + 0x028U)
+#define DMA2_Stream2_BASE (DMA2_BASE + 0x040U)
+#define DMA2_Stream3_BASE (DMA2_BASE + 0x058U)
+#define DMA2_Stream4_BASE (DMA2_BASE + 0x070U)
+#define DMA2_Stream5_BASE (DMA2_BASE + 0x088U)
+#define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0U)
+#define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8U)
+
+/*!< AHB2 peripherals */
+#define CRYP_BASE (AHB2PERIPH_BASE + 0x60000U)
+#define HASH_BASE (AHB2PERIPH_BASE + 0x60400U)
+#define HASH_DIGEST_BASE (AHB2PERIPH_BASE + 0x60710U)
+#define RNG_BASE (AHB2PERIPH_BASE + 0x60800U)
+
+/*!< FSMC Bankx registers base address */
+#define FSMC_Bank1_R_BASE (FSMC_R_BASE + 0x0000U)
+#define FSMC_Bank1E_R_BASE (FSMC_R_BASE + 0x0104U)
+#define FSMC_Bank2_3_R_BASE (FSMC_R_BASE + 0x0060U)
+#define FSMC_Bank4_R_BASE (FSMC_R_BASE + 0x00A0U)
+
+/* Debug MCU registers base address */
+#define DBGMCU_BASE 0xE0042000U
+
+/*!< USB registers base address */
+#define USB_OTG_HS_PERIPH_BASE 0x40040000U
+#define USB_OTG_FS_PERIPH_BASE 0x50000000U
+
+#define USB_OTG_GLOBAL_BASE 0x000U
+#define USB_OTG_DEVICE_BASE 0x800U
+#define USB_OTG_IN_ENDPOINT_BASE 0x900U
+#define USB_OTG_OUT_ENDPOINT_BASE 0xB00U
+#define USB_OTG_EP_REG_SIZE 0x20U
+#define USB_OTG_HOST_BASE 0x400U
+#define USB_OTG_HOST_PORT_BASE 0x440U
+#define USB_OTG_HOST_CHANNEL_BASE 0x500U
+#define USB_OTG_HOST_CHANNEL_SIZE 0x20U
+#define USB_OTG_PCGCCTL_BASE 0xE00U
+#define USB_OTG_FIFO_BASE 0x1000U
+#define USB_OTG_FIFO_SIZE 0x1000U
+
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_declaration
+ * @{
+ */
+#define TIM2 ((TIM_TypeDef *) TIM2_BASE)
+#define TIM3 ((TIM_TypeDef *) TIM3_BASE)
+#define TIM4 ((TIM_TypeDef *) TIM4_BASE)
+#define TIM5 ((TIM_TypeDef *) TIM5_BASE)
+#define TIM6 ((TIM_TypeDef *) TIM6_BASE)
+#define TIM7 ((TIM_TypeDef *) TIM7_BASE)
+#define TIM12 ((TIM_TypeDef *) TIM12_BASE)
+#define TIM13 ((TIM_TypeDef *) TIM13_BASE)
+#define TIM14 ((TIM_TypeDef *) TIM14_BASE)
+#define RTC ((RTC_TypeDef *) RTC_BASE)
+#define WWDG ((WWDG_TypeDef *) WWDG_BASE)
+#define IWDG ((IWDG_TypeDef *) IWDG_BASE)
+#define I2S2ext ((SPI_TypeDef *) I2S2ext_BASE)
+#define SPI2 ((SPI_TypeDef *) SPI2_BASE)
+#define SPI3 ((SPI_TypeDef *) SPI3_BASE)
+#define I2S3ext ((SPI_TypeDef *) I2S3ext_BASE)
+#define USART2 ((USART_TypeDef *) USART2_BASE)
+#define USART3 ((USART_TypeDef *) USART3_BASE)
+#define UART4 ((USART_TypeDef *) UART4_BASE)
+#define UART5 ((USART_TypeDef *) UART5_BASE)
+#define I2C1 ((I2C_TypeDef *) I2C1_BASE)
+#define I2C2 ((I2C_TypeDef *) I2C2_BASE)
+#define I2C3 ((I2C_TypeDef *) I2C3_BASE)
+#define CAN1 ((CAN_TypeDef *) CAN1_BASE)
+#define CAN2 ((CAN_TypeDef *) CAN2_BASE)
+#define PWR ((PWR_TypeDef *) PWR_BASE)
+#define DAC ((DAC_TypeDef *) DAC_BASE)
+#define TIM1 ((TIM_TypeDef *) TIM1_BASE)
+#define TIM8 ((TIM_TypeDef *) TIM8_BASE)
+#define USART1 ((USART_TypeDef *) USART1_BASE)
+#define USART6 ((USART_TypeDef *) USART6_BASE)
+#define ADC ((ADC_Common_TypeDef *) ADC_BASE)
+#define ADC1 ((ADC_TypeDef *) ADC1_BASE)
+#define ADC2 ((ADC_TypeDef *) ADC2_BASE)
+#define ADC3 ((ADC_TypeDef *) ADC3_BASE)
+#define SDIO ((SDIO_TypeDef *) SDIO_BASE)
+#define SPI1 ((SPI_TypeDef *) SPI1_BASE)
+#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
+#define EXTI ((EXTI_TypeDef *) EXTI_BASE)
+#define TIM9 ((TIM_TypeDef *) TIM9_BASE)
+#define TIM10 ((TIM_TypeDef *) TIM10_BASE)
+#define TIM11 ((TIM_TypeDef *) TIM11_BASE)
+#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
+#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
+#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
+#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
+#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
+#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
+#define GPIOG ((GPIO_TypeDef *) GPIOG_BASE)
+#define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
+#define GPIOI ((GPIO_TypeDef *) GPIOI_BASE)
+#define CRC ((CRC_TypeDef *) CRC_BASE)
+#define RCC ((RCC_TypeDef *) RCC_BASE)
+#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
+#define DMA1 ((DMA_TypeDef *) DMA1_BASE)
+#define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)
+#define DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)
+#define DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)
+#define DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)
+#define DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)
+#define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)
+#define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)
+#define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)
+#define DMA2 ((DMA_TypeDef *) DMA2_BASE)
+#define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)
+#define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
+#define DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)
+#define DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)
+#define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)
+#define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)
+#define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)
+#define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)
+#define CRYP ((CRYP_TypeDef *) CRYP_BASE)
+#define HASH ((HASH_TypeDef *) HASH_BASE)
+#define HASH_DIGEST ((HASH_DIGEST_TypeDef *) HASH_DIGEST_BASE)
+#define RNG ((RNG_TypeDef *) RNG_BASE)
+#define FSMC_Bank1 ((FSMC_Bank1_TypeDef *) FSMC_Bank1_R_BASE)
+#define FSMC_Bank1E ((FSMC_Bank1E_TypeDef *) FSMC_Bank1E_R_BASE)
+#define FSMC_Bank2_3 ((FSMC_Bank2_3_TypeDef *) FSMC_Bank2_3_R_BASE)
+#define FSMC_Bank4 ((FSMC_Bank4_TypeDef *) FSMC_Bank4_R_BASE)
+
+#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
+
+#define USB_OTG_FS ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE)
+#define USB_OTG_HS ((USB_OTG_GlobalTypeDef *) USB_OTG_HS_PERIPH_BASE)
+
+/**
+ * @}
+ */
+
+/** @addtogroup Exported_constants
+ * @{
+ */
+
+ /** @addtogroup Peripheral_Registers_Bits_Definition
+ * @{
+ */
+
+/******************************************************************************/
+/* Peripheral Registers_Bits_Definition */
+/******************************************************************************/
+
+/******************************************************************************/
+/* */
+/* Analog to Digital Converter */
+/* */
+/******************************************************************************/
+/******************** Bit definition for ADC_SR register ********************/
+#define ADC_SR_AWD 0x00000001U /*!<Analog watchdog flag */
+#define ADC_SR_EOC 0x00000002U /*!<End of conversion */
+#define ADC_SR_JEOC 0x00000004U /*!<Injected channel end of conversion */
+#define ADC_SR_JSTRT 0x00000008U /*!<Injected channel Start flag */
+#define ADC_SR_STRT 0x00000010U /*!<Regular channel Start flag */
+#define ADC_SR_OVR 0x00000020U /*!<Overrun flag */
+
+/******************* Bit definition for ADC_CR1 register ********************/
+#define ADC_CR1_AWDCH 0x0000001FU /*!<AWDCH[4:0] bits (Analog watchdog channel select bits) */
+#define ADC_CR1_AWDCH_0 0x00000001U /*!<Bit 0 */
+#define ADC_CR1_AWDCH_1 0x00000002U /*!<Bit 1 */
+#define ADC_CR1_AWDCH_2 0x00000004U /*!<Bit 2 */
+#define ADC_CR1_AWDCH_3 0x00000008U /*!<Bit 3 */
+#define ADC_CR1_AWDCH_4 0x00000010U /*!<Bit 4 */
+#define ADC_CR1_EOCIE 0x00000020U /*!<Interrupt enable for EOC */
+#define ADC_CR1_AWDIE 0x00000040U /*!<AAnalog Watchdog interrupt enable */
+#define ADC_CR1_JEOCIE 0x00000080U /*!<Interrupt enable for injected channels */
+#define ADC_CR1_SCAN 0x00000100U /*!<Scan mode */
+#define ADC_CR1_AWDSGL 0x00000200U /*!<Enable the watchdog on a single channel in scan mode */
+#define ADC_CR1_JAUTO 0x00000400U /*!<Automatic injected group conversion */
+#define ADC_CR1_DISCEN 0x00000800U /*!<Discontinuous mode on regular channels */
+#define ADC_CR1_JDISCEN 0x00001000U /*!<Discontinuous mode on injected channels */
+#define ADC_CR1_DISCNUM 0x0000E000U /*!<DISCNUM[2:0] bits (Discontinuous mode channel count) */
+#define ADC_CR1_DISCNUM_0 0x00002000U /*!<Bit 0 */
+#define ADC_CR1_DISCNUM_1 0x00004000U /*!<Bit 1 */
+#define ADC_CR1_DISCNUM_2 0x00008000U /*!<Bit 2 */
+#define ADC_CR1_JAWDEN 0x00400000U /*!<Analog watchdog enable on injected channels */
+#define ADC_CR1_AWDEN 0x00800000U /*!<Analog watchdog enable on regular channels */
+#define ADC_CR1_RES 0x03000000U /*!<RES[2:0] bits (Resolution) */
+#define ADC_CR1_RES_0 0x01000000U /*!<Bit 0 */
+#define ADC_CR1_RES_1 0x02000000U /*!<Bit 1 */
+#define ADC_CR1_OVRIE 0x04000000U /*!<overrun interrupt enable */
+
+/******************* Bit definition for ADC_CR2 register ********************/
+#define ADC_CR2_ADON 0x00000001U /*!<A/D Converter ON / OFF */
+#define ADC_CR2_CONT 0x00000002U /*!<Continuous Conversion */
+#define ADC_CR2_DMA 0x00000100U /*!<Direct Memory access mode */
+#define ADC_CR2_DDS 0x00000200U /*!<DMA disable selection (Single ADC) */
+#define ADC_CR2_EOCS 0x00000400U /*!<End of conversion selection */
+#define ADC_CR2_ALIGN 0x00000800U /*!<Data Alignment */
+#define ADC_CR2_JEXTSEL 0x000F0000U /*!<JEXTSEL[3:0] bits (External event select for injected group) */
+#define ADC_CR2_JEXTSEL_0 0x00010000U /*!<Bit 0 */
+#define ADC_CR2_JEXTSEL_1 0x00020000U /*!<Bit 1 */
+#define ADC_CR2_JEXTSEL_2 0x00040000U /*!<Bit 2 */
+#define ADC_CR2_JEXTSEL_3 0x00080000U /*!<Bit 3 */
+#define ADC_CR2_JEXTEN 0x00300000U /*!<JEXTEN[1:0] bits (External Trigger Conversion mode for injected channelsp) */
+#define ADC_CR2_JEXTEN_0 0x00100000U /*!<Bit 0 */
+#define ADC_CR2_JEXTEN_1 0x00200000U /*!<Bit 1 */
+#define ADC_CR2_JSWSTART 0x00400000U /*!<Start Conversion of injected channels */
+#define ADC_CR2_EXTSEL 0x0F000000U /*!<EXTSEL[3:0] bits (External Event Select for regular group) */
+#define ADC_CR2_EXTSEL_0 0x01000000U /*!<Bit 0 */
+#define ADC_CR2_EXTSEL_1 0x02000000U /*!<Bit 1 */
+#define ADC_CR2_EXTSEL_2 0x04000000U /*!<Bit 2 */
+#define ADC_CR2_EXTSEL_3 0x08000000U /*!<Bit 3 */
+#define ADC_CR2_EXTEN 0x30000000U /*!<EXTEN[1:0] bits (External Trigger Conversion mode for regular channelsp) */
+#define ADC_CR2_EXTEN_0 0x10000000U /*!<Bit 0 */
+#define ADC_CR2_EXTEN_1 0x20000000U /*!<Bit 1 */
+#define ADC_CR2_SWSTART 0x40000000U /*!<Start Conversion of regular channels */
+
+/****************** Bit definition for ADC_SMPR1 register *******************/
+#define ADC_SMPR1_SMP10 0x00000007U /*!<SMP10[2:0] bits (Channel 10 Sample time selection) */
+#define ADC_SMPR1_SMP10_0 0x00000001U /*!<Bit 0 */
+#define ADC_SMPR1_SMP10_1 0x00000002U /*!<Bit 1 */
+#define ADC_SMPR1_SMP10_2 0x00000004U /*!<Bit 2 */
+#define ADC_SMPR1_SMP11 0x00000038U /*!<SMP11[2:0] bits (Channel 11 Sample time selection) */
+#define ADC_SMPR1_SMP11_0 0x00000008U /*!<Bit 0 */
+#define ADC_SMPR1_SMP11_1 0x00000010U /*!<Bit 1 */
+#define ADC_SMPR1_SMP11_2 0x00000020U /*!<Bit 2 */
+#define ADC_SMPR1_SMP12 0x000001C0U /*!<SMP12[2:0] bits (Channel 12 Sample time selection) */
+#define ADC_SMPR1_SMP12_0 0x00000040U /*!<Bit 0 */
+#define ADC_SMPR1_SMP12_1 0x00000080U /*!<Bit 1 */
+#define ADC_SMPR1_SMP12_2 0x00000100U /*!<Bit 2 */
+#define ADC_SMPR1_SMP13 0x00000E00U /*!<SMP13[2:0] bits (Channel 13 Sample time selection) */
+#define ADC_SMPR1_SMP13_0 0x00000200U /*!<Bit 0 */
+#define ADC_SMPR1_SMP13_1 0x00000400U /*!<Bit 1 */
+#define ADC_SMPR1_SMP13_2 0x00000800U /*!<Bit 2 */
+#define ADC_SMPR1_SMP14 0x00007000U /*!<SMP14[2:0] bits (Channel 14 Sample time selection) */
+#define ADC_SMPR1_SMP14_0 0x00001000U /*!<Bit 0 */
+#define ADC_SMPR1_SMP14_1 0x00002000U /*!<Bit 1 */
+#define ADC_SMPR1_SMP14_2 0x00004000U /*!<Bit 2 */
+#define ADC_SMPR1_SMP15 0x00038000U /*!<SMP15[2:0] bits (Channel 15 Sample time selection) */
+#define ADC_SMPR1_SMP15_0 0x00008000U /*!<Bit 0 */
+#define ADC_SMPR1_SMP15_1 0x00010000U /*!<Bit 1 */
+#define ADC_SMPR1_SMP15_2 0x00020000U /*!<Bit 2 */
+#define ADC_SMPR1_SMP16 0x001C0000U /*!<SMP16[2:0] bits (Channel 16 Sample time selection) */
+#define ADC_SMPR1_SMP16_0 0x00040000U /*!<Bit 0 */
+#define ADC_SMPR1_SMP16_1 0x00080000U /*!<Bit 1 */
+#define ADC_SMPR1_SMP16_2 0x00100000U /*!<Bit 2 */
+#define ADC_SMPR1_SMP17 0x00E00000U /*!<SMP17[2:0] bits (Channel 17 Sample time selection) */
+#define ADC_SMPR1_SMP17_0 0x00200000U /*!<Bit 0 */
+#define ADC_SMPR1_SMP17_1 0x00400000U /*!<Bit 1 */
+#define ADC_SMPR1_SMP17_2 0x00800000U /*!<Bit 2 */
+#define ADC_SMPR1_SMP18 0x07000000U /*!<SMP18[2:0] bits (Channel 18 Sample time selection) */
+#define ADC_SMPR1_SMP18_0 0x01000000U /*!<Bit 0 */
+#define ADC_SMPR1_SMP18_1 0x02000000U /*!<Bit 1 */
+#define ADC_SMPR1_SMP18_2 0x04000000U /*!<Bit 2 */
+
+/****************** Bit definition for ADC_SMPR2 register *******************/
+#define ADC_SMPR2_SMP0 0x00000007U /*!<SMP0[2:0] bits (Channel 0 Sample time selection) */
+#define ADC_SMPR2_SMP0_0 0x00000001U /*!<Bit 0 */
+#define ADC_SMPR2_SMP0_1 0x00000002U /*!<Bit 1 */
+#define ADC_SMPR2_SMP0_2 0x00000004U /*!<Bit 2 */
+#define ADC_SMPR2_SMP1 0x00000038U /*!<SMP1[2:0] bits (Channel 1 Sample time selection) */
+#define ADC_SMPR2_SMP1_0 0x00000008U /*!<Bit 0 */
+#define ADC_SMPR2_SMP1_1 0x00000010U /*!<Bit 1 */
+#define ADC_SMPR2_SMP1_2 0x00000020U /*!<Bit 2 */
+#define ADC_SMPR2_SMP2 0x000001C0U /*!<SMP2[2:0] bits (Channel 2 Sample time selection) */
+#define ADC_SMPR2_SMP2_0 0x00000040U /*!<Bit 0 */
+#define ADC_SMPR2_SMP2_1 0x00000080U /*!<Bit 1 */
+#define ADC_SMPR2_SMP2_2 0x00000100U /*!<Bit 2 */
+#define ADC_SMPR2_SMP3 0x00000E00U /*!<SMP3[2:0] bits (Channel 3 Sample time selection) */
+#define ADC_SMPR2_SMP3_0 0x00000200U /*!<Bit 0 */
+#define ADC_SMPR2_SMP3_1 0x00000400U /*!<Bit 1 */
+#define ADC_SMPR2_SMP3_2 0x00000800U /*!<Bit 2 */
+#define ADC_SMPR2_SMP4 0x00007000U /*!<SMP4[2:0] bits (Channel 4 Sample time selection) */
+#define ADC_SMPR2_SMP4_0 0x00001000U /*!<Bit 0 */
+#define ADC_SMPR2_SMP4_1 0x00002000U /*!<Bit 1 */
+#define ADC_SMPR2_SMP4_2 0x00004000U /*!<Bit 2 */
+#define ADC_SMPR2_SMP5 0x00038000U /*!<SMP5[2:0] bits (Channel 5 Sample time selection) */
+#define ADC_SMPR2_SMP5_0 0x00008000U /*!<Bit 0 */
+#define ADC_SMPR2_SMP5_1 0x00010000U /*!<Bit 1 */
+#define ADC_SMPR2_SMP5_2 0x00020000U /*!<Bit 2 */
+#define ADC_SMPR2_SMP6 0x001C0000U /*!<SMP6[2:0] bits (Channel 6 Sample time selection) */
+#define ADC_SMPR2_SMP6_0 0x00040000U /*!<Bit 0 */
+#define ADC_SMPR2_SMP6_1 0x00080000U /*!<Bit 1 */
+#define ADC_SMPR2_SMP6_2 0x00100000U /*!<Bit 2 */
+#define ADC_SMPR2_SMP7 0x00E00000U /*!<SMP7[2:0] bits (Channel 7 Sample time selection) */
+#define ADC_SMPR2_SMP7_0 0x00200000U /*!<Bit 0 */
+#define ADC_SMPR2_SMP7_1 0x00400000U /*!<Bit 1 */
+#define ADC_SMPR2_SMP7_2 0x00800000U /*!<Bit 2 */
+#define ADC_SMPR2_SMP8 0x07000000U /*!<SMP8[2:0] bits (Channel 8 Sample time selection) */
+#define ADC_SMPR2_SMP8_0 0x01000000U /*!<Bit 0 */
+#define ADC_SMPR2_SMP8_1 0x02000000U /*!<Bit 1 */
+#define ADC_SMPR2_SMP8_2 0x04000000U /*!<Bit 2 */
+#define ADC_SMPR2_SMP9 0x38000000U /*!<SMP9[2:0] bits (Channel 9 Sample time selection) */
+#define ADC_SMPR2_SMP9_0 0x08000000U /*!<Bit 0 */
+#define ADC_SMPR2_SMP9_1 0x10000000U /*!<Bit 1 */
+#define ADC_SMPR2_SMP9_2 0x20000000U /*!<Bit 2 */
+
+/****************** Bit definition for ADC_JOFR1 register *******************/
+#define ADC_JOFR1_JOFFSET1 0x0FFFU /*!<Data offset for injected channel 1 */
+
+/****************** Bit definition for ADC_JOFR2 register *******************/
+#define ADC_JOFR2_JOFFSET2 0x0FFFU /*!<Data offset for injected channel 2 */
+
+/****************** Bit definition for ADC_JOFR3 register *******************/
+#define ADC_JOFR3_JOFFSET3 0x0FFFU /*!<Data offset for injected channel 3 */
+
+/****************** Bit definition for ADC_JOFR4 register *******************/
+#define ADC_JOFR4_JOFFSET4 0x0FFFU /*!<Data offset for injected channel 4 */
+
+/******************* Bit definition for ADC_HTR register ********************/
+#define ADC_HTR_HT 0x0FFFU /*!<Analog watchdog high threshold */
+
+/******************* Bit definition for ADC_LTR register ********************/
+#define ADC_LTR_LT 0x0FFFU /*!<Analog watchdog low threshold */
+
+/******************* Bit definition for ADC_SQR1 register *******************/
+#define ADC_SQR1_SQ13 0x0000001FU /*!<SQ13[4:0] bits (13th conversion in regular sequence) */
+#define ADC_SQR1_SQ13_0 0x00000001U /*!<Bit 0 */
+#define ADC_SQR1_SQ13_1 0x00000002U /*!<Bit 1 */
+#define ADC_SQR1_SQ13_2 0x00000004U /*!<Bit 2 */
+#define ADC_SQR1_SQ13_3 0x00000008U /*!<Bit 3 */
+#define ADC_SQR1_SQ13_4 0x00000010U /*!<Bit 4 */
+#define ADC_SQR1_SQ14 0x000003E0U /*!<SQ14[4:0] bits (14th conversion in regular sequence) */
+#define ADC_SQR1_SQ14_0 0x00000020U /*!<Bit 0 */
+#define ADC_SQR1_SQ14_1 0x00000040U /*!<Bit 1 */
+#define ADC_SQR1_SQ14_2 0x00000080U /*!<Bit 2 */
+#define ADC_SQR1_SQ14_3 0x00000100U /*!<Bit 3 */
+#define ADC_SQR1_SQ14_4 0x00000200U /*!<Bit 4 */
+#define ADC_SQR1_SQ15 0x00007C00U /*!<SQ15[4:0] bits (15th conversion in regular sequence) */
+#define ADC_SQR1_SQ15_0 0x00000400U /*!<Bit 0 */
+#define ADC_SQR1_SQ15_1 0x00000800U /*!<Bit 1 */
+#define ADC_SQR1_SQ15_2 0x00001000U /*!<Bit 2 */
+#define ADC_SQR1_SQ15_3 0x00002000U /*!<Bit 3 */
+#define ADC_SQR1_SQ15_4 0x00004000U /*!<Bit 4 */
+#define ADC_SQR1_SQ16 0x000F8000U /*!<SQ16[4:0] bits (16th conversion in regular sequence) */
+#define ADC_SQR1_SQ16_0 0x00008000U /*!<Bit 0 */
+#define ADC_SQR1_SQ16_1 0x00010000U /*!<Bit 1 */
+#define ADC_SQR1_SQ16_2 0x00020000U /*!<Bit 2 */
+#define ADC_SQR1_SQ16_3 0x00040000U /*!<Bit 3 */
+#define ADC_SQR1_SQ16_4 0x00080000U /*!<Bit 4 */
+#define ADC_SQR1_L 0x00F00000U /*!<L[3:0] bits (Regular channel sequence length) */
+#define ADC_SQR1_L_0 0x00100000U /*!<Bit 0 */
+#define ADC_SQR1_L_1 0x00200000U /*!<Bit 1 */
+#define ADC_SQR1_L_2 0x00400000U /*!<Bit 2 */
+#define ADC_SQR1_L_3 0x00800000U /*!<Bit 3 */
+
+/******************* Bit definition for ADC_SQR2 register *******************/
+#define ADC_SQR2_SQ7 0x0000001FU /*!<SQ7[4:0] bits (7th conversion in regular sequence) */
+#define ADC_SQR2_SQ7_0 0x00000001U /*!<Bit 0 */
+#define ADC_SQR2_SQ7_1 0x00000002U /*!<Bit 1 */
+#define ADC_SQR2_SQ7_2 0x00000004U /*!<Bit 2 */
+#define ADC_SQR2_SQ7_3 0x00000008U /*!<Bit 3 */
+#define ADC_SQR2_SQ7_4 0x00000010U /*!<Bit 4 */
+#define ADC_SQR2_SQ8 0x000003E0U /*!<SQ8[4:0] bits (8th conversion in regular sequence) */
+#define ADC_SQR2_SQ8_0 0x00000020U /*!<Bit 0 */
+#define ADC_SQR2_SQ8_1 0x00000040U /*!<Bit 1 */
+#define ADC_SQR2_SQ8_2 0x00000080U /*!<Bit 2 */
+#define ADC_SQR2_SQ8_3 0x00000100U /*!<Bit 3 */
+#define ADC_SQR2_SQ8_4 0x00000200U /*!<Bit 4 */
+#define ADC_SQR2_SQ9 0x00007C00U /*!<SQ9[4:0] bits (9th conversion in regular sequence) */
+#define ADC_SQR2_SQ9_0 0x00000400U /*!<Bit 0 */
+#define ADC_SQR2_SQ9_1 0x00000800U /*!<Bit 1 */
+#define ADC_SQR2_SQ9_2 0x00001000U /*!<Bit 2 */
+#define ADC_SQR2_SQ9_3 0x00002000U /*!<Bit 3 */
+#define ADC_SQR2_SQ9_4 0x00004000U /*!<Bit 4 */
+#define ADC_SQR2_SQ10 0x000F8000U /*!<SQ10[4:0] bits (10th conversion in regular sequence) */
+#define ADC_SQR2_SQ10_0 0x00008000U /*!<Bit 0 */
+#define ADC_SQR2_SQ10_1 0x00010000U /*!<Bit 1 */
+#define ADC_SQR2_SQ10_2 0x00020000U /*!<Bit 2 */
+#define ADC_SQR2_SQ10_3 0x00040000U /*!<Bit 3 */
+#define ADC_SQR2_SQ10_4 0x00080000U /*!<Bit 4 */
+#define ADC_SQR2_SQ11 0x01F00000U /*!<SQ11[4:0] bits (11th conversion in regular sequence) */
+#define ADC_SQR2_SQ11_0 0x00100000U /*!<Bit 0 */
+#define ADC_SQR2_SQ11_1 0x00200000U /*!<Bit 1 */
+#define ADC_SQR2_SQ11_2 0x00400000U /*!<Bit 2 */
+#define ADC_SQR2_SQ11_3 0x00800000U /*!<Bit 3 */
+#define ADC_SQR2_SQ11_4 0x01000000U /*!<Bit 4 */
+#define ADC_SQR2_SQ12 0x3E000000U /*!<SQ12[4:0] bits (12th conversion in regular sequence) */
+#define ADC_SQR2_SQ12_0 0x02000000U /*!<Bit 0 */
+#define ADC_SQR2_SQ12_1 0x04000000U /*!<Bit 1 */
+#define ADC_SQR2_SQ12_2 0x08000000U /*!<Bit 2 */
+#define ADC_SQR2_SQ12_3 0x10000000U /*!<Bit 3 */
+#define ADC_SQR2_SQ12_4 0x20000000U /*!<Bit 4 */
+
+/******************* Bit definition for ADC_SQR3 register *******************/
+#define ADC_SQR3_SQ1 0x0000001FU /*!<SQ1[4:0] bits (1st conversion in regular sequence) */
+#define ADC_SQR3_SQ1_0 0x00000001U /*!<Bit 0 */
+#define ADC_SQR3_SQ1_1 0x00000002U /*!<Bit 1 */
+#define ADC_SQR3_SQ1_2 0x00000004U /*!<Bit 2 */
+#define ADC_SQR3_SQ1_3 0x00000008U /*!<Bit 3 */
+#define ADC_SQR3_SQ1_4 0x00000010U /*!<Bit 4 */
+#define ADC_SQR3_SQ2 0x000003E0U /*!<SQ2[4:0] bits (2nd conversion in regular sequence) */
+#define ADC_SQR3_SQ2_0 0x00000020U /*!<Bit 0 */
+#define ADC_SQR3_SQ2_1 0x00000040U /*!<Bit 1 */
+#define ADC_SQR3_SQ2_2 0x00000080U /*!<Bit 2 */
+#define ADC_SQR3_SQ2_3 0x00000100U /*!<Bit 3 */
+#define ADC_SQR3_SQ2_4 0x00000200U /*!<Bit 4 */
+#define ADC_SQR3_SQ3 0x00007C00U /*!<SQ3[4:0] bits (3rd conversion in regular sequence) */
+#define ADC_SQR3_SQ3_0 0x00000400U /*!<Bit 0 */
+#define ADC_SQR3_SQ3_1 0x00000800U /*!<Bit 1 */
+#define ADC_SQR3_SQ3_2 0x00001000U /*!<Bit 2 */
+#define ADC_SQR3_SQ3_3 0x00002000U /*!<Bit 3 */
+#define ADC_SQR3_SQ3_4 0x00004000U /*!<Bit 4 */
+#define ADC_SQR3_SQ4 0x000F8000U /*!<SQ4[4:0] bits (4th conversion in regular sequence) */
+#define ADC_SQR3_SQ4_0 0x00008000U /*!<Bit 0 */
+#define ADC_SQR3_SQ4_1 0x00010000U /*!<Bit 1 */
+#define ADC_SQR3_SQ4_2 0x00020000U /*!<Bit 2 */
+#define ADC_SQR3_SQ4_3 0x00040000U /*!<Bit 3 */
+#define ADC_SQR3_SQ4_4 0x00080000U /*!<Bit 4 */
+#define ADC_SQR3_SQ5 0x01F00000U /*!<SQ5[4:0] bits (5th conversion in regular sequence) */
+#define ADC_SQR3_SQ5_0 0x00100000U /*!<Bit 0 */
+#define ADC_SQR3_SQ5_1 0x00200000U /*!<Bit 1 */
+#define ADC_SQR3_SQ5_2 0x00400000U /*!<Bit 2 */
+#define ADC_SQR3_SQ5_3 0x00800000U /*!<Bit 3 */
+#define ADC_SQR3_SQ5_4 0x01000000U /*!<Bit 4 */
+#define ADC_SQR3_SQ6 0x3E000000U /*!<SQ6[4:0] bits (6th conversion in regular sequence) */
+#define ADC_SQR3_SQ6_0 0x02000000U /*!<Bit 0 */
+#define ADC_SQR3_SQ6_1 0x04000000U /*!<Bit 1 */
+#define ADC_SQR3_SQ6_2 0x08000000U /*!<Bit 2 */
+#define ADC_SQR3_SQ6_3 0x10000000U /*!<Bit 3 */
+#define ADC_SQR3_SQ6_4 0x20000000U /*!<Bit 4 */
+
+/******************* Bit definition for ADC_JSQR register *******************/
+#define ADC_JSQR_JSQ1 0x0000001FU /*!<JSQ1[4:0] bits (1st conversion in injected sequence) */
+#define ADC_JSQR_JSQ1_0 0x00000001U /*!<Bit 0 */
+#define ADC_JSQR_JSQ1_1 0x00000002U /*!<Bit 1 */
+#define ADC_JSQR_JSQ1_2 0x00000004U /*!<Bit 2 */
+#define ADC_JSQR_JSQ1_3 0x00000008U /*!<Bit 3 */
+#define ADC_JSQR_JSQ1_4 0x00000010U /*!<Bit 4 */
+#define ADC_JSQR_JSQ2 0x000003E0U /*!<JSQ2[4:0] bits (2nd conversion in injected sequence) */
+#define ADC_JSQR_JSQ2_0 0x00000020U /*!<Bit 0 */
+#define ADC_JSQR_JSQ2_1 0x00000040U /*!<Bit 1 */
+#define ADC_JSQR_JSQ2_2 0x00000080U /*!<Bit 2 */
+#define ADC_JSQR_JSQ2_3 0x00000100U /*!<Bit 3 */
+#define ADC_JSQR_JSQ2_4 0x00000200U /*!<Bit 4 */
+#define ADC_JSQR_JSQ3 0x00007C00U /*!<JSQ3[4:0] bits (3rd conversion in injected sequence) */
+#define ADC_JSQR_JSQ3_0 0x00000400U /*!<Bit 0 */
+#define ADC_JSQR_JSQ3_1 0x00000800U /*!<Bit 1 */
+#define ADC_JSQR_JSQ3_2 0x00001000U /*!<Bit 2 */
+#define ADC_JSQR_JSQ3_3 0x00002000U /*!<Bit 3 */
+#define ADC_JSQR_JSQ3_4 0x00004000U /*!<Bit 4 */
+#define ADC_JSQR_JSQ4 0x000F8000U /*!<JSQ4[4:0] bits (4th conversion in injected sequence) */
+#define ADC_JSQR_JSQ4_0 0x00008000U /*!<Bit 0 */
+#define ADC_JSQR_JSQ4_1 0x00010000U /*!<Bit 1 */
+#define ADC_JSQR_JSQ4_2 0x00020000U /*!<Bit 2 */
+#define ADC_JSQR_JSQ4_3 0x00040000U /*!<Bit 3 */
+#define ADC_JSQR_JSQ4_4 0x00080000U /*!<Bit 4 */
+#define ADC_JSQR_JL 0x00300000U /*!<JL[1:0] bits (Injected Sequence length) */
+#define ADC_JSQR_JL_0 0x00100000U /*!<Bit 0 */
+#define ADC_JSQR_JL_1 0x00200000U /*!<Bit 1 */
+
+/******************* Bit definition for ADC_JDR1 register *******************/
+#define ADC_JDR1_JDATA 0xFFFFU /*!<Injected data */
+
+/******************* Bit definition for ADC_JDR2 register *******************/
+#define ADC_JDR2_JDATA 0xFFFFU /*!<Injected data */
+
+/******************* Bit definition for ADC_JDR3 register *******************/
+#define ADC_JDR3_JDATA 0xFFFFU /*!<Injected data */
+
+/******************* Bit definition for ADC_JDR4 register *******************/
+#define ADC_JDR4_JDATA 0xFFFFU /*!<Injected data */
+
+/******************** Bit definition for ADC_DR register ********************/
+#define ADC_DR_DATA 0x0000FFFFU /*!<Regular data */
+#define ADC_DR_ADC2DATA 0xFFFF0000U /*!<ADC2 data */
+
+/******************* Bit definition for ADC_CSR register ********************/
+#define ADC_CSR_AWD1 0x00000001U /*!<ADC1 Analog watchdog flag */
+#define ADC_CSR_EOC1 0x00000002U /*!<ADC1 End of conversion */
+#define ADC_CSR_JEOC1 0x00000004U /*!<ADC1 Injected channel end of conversion */
+#define ADC_CSR_JSTRT1 0x00000008U /*!<ADC1 Injected channel Start flag */
+#define ADC_CSR_STRT1 0x00000010U /*!<ADC1 Regular channel Start flag */
+#define ADC_CSR_OVR1 0x00000020U /*!<ADC1 DMA overrun flag */
+#define ADC_CSR_AWD2 0x00000100U /*!<ADC2 Analog watchdog flag */
+#define ADC_CSR_EOC2 0x00000200U /*!<ADC2 End of conversion */
+#define ADC_CSR_JEOC2 0x00000400U /*!<ADC2 Injected channel end of conversion */
+#define ADC_CSR_JSTRT2 0x00000800U /*!<ADC2 Injected channel Start flag */
+#define ADC_CSR_STRT2 0x00001000U /*!<ADC2 Regular channel Start flag */
+#define ADC_CSR_OVR2 0x00002000U /*!<ADC2 DMA overrun flag */
+#define ADC_CSR_AWD3 0x00010000U /*!<ADC3 Analog watchdog flag */
+#define ADC_CSR_EOC3 0x00020000U /*!<ADC3 End of conversion */
+#define ADC_CSR_JEOC3 0x00040000U /*!<ADC3 Injected channel end of conversion */
+#define ADC_CSR_JSTRT3 0x00080000U /*!<ADC3 Injected channel Start flag */
+#define ADC_CSR_STRT3 0x00100000U /*!<ADC3 Regular channel Start flag */
+#define ADC_CSR_OVR3 0x00200000U /*!<ADC3 DMA overrun flag */
+
+/* Legacy defines */
+#define ADC_CSR_DOVR1 ADC_CSR_OVR1
+#define ADC_CSR_DOVR2 ADC_CSR_OVR2
+#define ADC_CSR_DOVR3 ADC_CSR_OVR3
+
+/******************* Bit definition for ADC_CCR register ********************/
+#define ADC_CCR_MULTI 0x0000001FU /*!<MULTI[4:0] bits (Multi-ADC mode selection) */
+#define ADC_CCR_MULTI_0 0x00000001U /*!<Bit 0 */
+#define ADC_CCR_MULTI_1 0x00000002U /*!<Bit 1 */
+#define ADC_CCR_MULTI_2 0x00000004U /*!<Bit 2 */
+#define ADC_CCR_MULTI_3 0x00000008U /*!<Bit 3 */
+#define ADC_CCR_MULTI_4 0x00000010U /*!<Bit 4 */
+#define ADC_CCR_DELAY 0x00000F00U /*!<DELAY[3:0] bits (Delay between 2 sampling phases) */
+#define ADC_CCR_DELAY_0 0x00000100U /*!<Bit 0 */
+#define ADC_CCR_DELAY_1 0x00000200U /*!<Bit 1 */
+#define ADC_CCR_DELAY_2 0x00000400U /*!<Bit 2 */
+#define ADC_CCR_DELAY_3 0x00000800U /*!<Bit 3 */
+#define ADC_CCR_DDS 0x00002000U /*!<DMA disable selection (Multi-ADC mode) */
+#define ADC_CCR_DMA 0x0000C000U /*!<DMA[1:0] bits (Direct Memory Access mode for multimode) */
+#define ADC_CCR_DMA_0 0x00004000U /*!<Bit 0 */
+#define ADC_CCR_DMA_1 0x00008000U /*!<Bit 1 */
+#define ADC_CCR_ADCPRE 0x00030000U /*!<ADCPRE[1:0] bits (ADC prescaler) */
+#define ADC_CCR_ADCPRE_0 0x00010000U /*!<Bit 0 */
+#define ADC_CCR_ADCPRE_1 0x00020000U /*!<Bit 1 */
+#define ADC_CCR_VBATE 0x00400000U /*!<VBAT Enable */
+#define ADC_CCR_TSVREFE 0x00800000U /*!<Temperature Sensor and VREFINT Enable */
+
+/******************* Bit definition for ADC_CDR register ********************/
+#define ADC_CDR_DATA1 0x0000FFFFU /*!<1st data of a pair of regular conversions */
+#define ADC_CDR_DATA2 0xFFFF0000U /*!<2nd data of a pair of regular conversions */
+
+/******************************************************************************/
+/* */
+/* Controller Area Network */
+/* */
+/******************************************************************************/
+/*!<CAN control and status registers */
+/******************* Bit definition for CAN_MCR register ********************/
+#define CAN_MCR_INRQ 0x00000001U /*!<Initialization Request */
+#define CAN_MCR_SLEEP 0x00000002U /*!<Sleep Mode Request */
+#define CAN_MCR_TXFP 0x00000004U /*!<Transmit FIFO Priority */
+#define CAN_MCR_RFLM 0x00000008U /*!<Receive FIFO Locked Mode */
+#define CAN_MCR_NART 0x00000010U /*!<No Automatic Retransmission */
+#define CAN_MCR_AWUM 0x00000020U /*!<Automatic Wakeup Mode */
+#define CAN_MCR_ABOM 0x00000040U /*!<Automatic Bus-Off Management */
+#define CAN_MCR_TTCM 0x00000080U /*!<Time Triggered Communication Mode */
+#define CAN_MCR_RESET 0x00008000U /*!<bxCAN software master reset */
+#define CAN_MCR_DBF 0x00010000U /*!<bxCAN Debug freeze */
+/******************* Bit definition for CAN_MSR register ********************/
+#define CAN_MSR_INAK 0x0001U /*!<Initialization Acknowledge */
+#define CAN_MSR_SLAK 0x0002U /*!<Sleep Acknowledge */
+#define CAN_MSR_ERRI 0x0004U /*!<Error Interrupt */
+#define CAN_MSR_WKUI 0x0008U /*!<Wakeup Interrupt */
+#define CAN_MSR_SLAKI 0x0010U /*!<Sleep Acknowledge Interrupt */
+#define CAN_MSR_TXM 0x0100U /*!<Transmit Mode */
+#define CAN_MSR_RXM 0x0200U /*!<Receive Mode */
+#define CAN_MSR_SAMP 0x0400U /*!<Last Sample Point */
+#define CAN_MSR_RX 0x0800U /*!<CAN Rx Signal */
+
+/******************* Bit definition for CAN_TSR register ********************/
+#define CAN_TSR_RQCP0 0x00000001U /*!<Request Completed Mailbox0 */
+#define CAN_TSR_TXOK0 0x00000002U /*!<Transmission OK of Mailbox0 */
+#define CAN_TSR_ALST0 0x00000004U /*!<Arbitration Lost for Mailbox0 */
+#define CAN_TSR_TERR0 0x00000008U /*!<Transmission Error of Mailbox0 */
+#define CAN_TSR_ABRQ0 0x00000080U /*!<Abort Request for Mailbox0 */
+#define CAN_TSR_RQCP1 0x00000100U /*!<Request Completed Mailbox1 */
+#define CAN_TSR_TXOK1 0x00000200U /*!<Transmission OK of Mailbox1 */
+#define CAN_TSR_ALST1 0x00000400U /*!<Arbitration Lost for Mailbox1 */
+#define CAN_TSR_TERR1 0x00000800U /*!<Transmission Error of Mailbox1 */
+#define CAN_TSR_ABRQ1 0x00008000U /*!<Abort Request for Mailbox 1 */
+#define CAN_TSR_RQCP2 0x00010000U /*!<Request Completed Mailbox2 */
+#define CAN_TSR_TXOK2 0x00020000U /*!<Transmission OK of Mailbox 2 */
+#define CAN_TSR_ALST2 0x00040000U /*!<Arbitration Lost for mailbox 2 */
+#define CAN_TSR_TERR2 0x00080000U /*!<Transmission Error of Mailbox 2 */
+#define CAN_TSR_ABRQ2 0x00800000U /*!<Abort Request for Mailbox 2 */
+#define CAN_TSR_CODE 0x03000000U /*!<Mailbox Code */
+
+#define CAN_TSR_TME 0x1C000000U /*!<TME[2:0] bits */
+#define CAN_TSR_TME0 0x04000000U /*!<Transmit Mailbox 0 Empty */
+#define CAN_TSR_TME1 0x08000000U /*!<Transmit Mailbox 1 Empty */
+#define CAN_TSR_TME2 0x10000000U /*!<Transmit Mailbox 2 Empty */
+
+#define CAN_TSR_LOW 0xE0000000U /*!<LOW[2:0] bits */
+#define CAN_TSR_LOW0 0x20000000U /*!<Lowest Priority Flag for Mailbox 0 */
+#define CAN_TSR_LOW1 0x40000000U /*!<Lowest Priority Flag for Mailbox 1 */
+#define CAN_TSR_LOW2 0x80000000U /*!<Lowest Priority Flag for Mailbox 2 */
+
+/******************* Bit definition for CAN_RF0R register *******************/
+#define CAN_RF0R_FMP0 0x03U /*!<FIFO 0 Message Pending */
+#define CAN_RF0R_FULL0 0x08U /*!<FIFO 0 Full */
+#define CAN_RF0R_FOVR0 0x10U /*!<FIFO 0 Overrun */
+#define CAN_RF0R_RFOM0 0x20U /*!<Release FIFO 0 Output Mailbox */
+
+/******************* Bit definition for CAN_RF1R register *******************/
+#define CAN_RF1R_FMP1 0x03U /*!<FIFO 1 Message Pending */
+#define CAN_RF1R_FULL1 0x08U /*!<FIFO 1 Full */
+#define CAN_RF1R_FOVR1 0x10U /*!<FIFO 1 Overrun */
+#define CAN_RF1R_RFOM1 0x20U /*!<Release FIFO 1 Output Mailbox */
+
+/******************** Bit definition for CAN_IER register *******************/
+#define CAN_IER_TMEIE 0x00000001U /*!<Transmit Mailbox Empty Interrupt Enable */
+#define CAN_IER_FMPIE0 0x00000002U /*!<FIFO Message Pending Interrupt Enable */
+#define CAN_IER_FFIE0 0x00000004U /*!<FIFO Full Interrupt Enable */
+#define CAN_IER_FOVIE0 0x00000008U /*!<FIFO Overrun Interrupt Enable */
+#define CAN_IER_FMPIE1 0x00000010U /*!<FIFO Message Pending Interrupt Enable */
+#define CAN_IER_FFIE1 0x00000020U /*!<FIFO Full Interrupt Enable */
+#define CAN_IER_FOVIE1 0x00000040U /*!<FIFO Overrun Interrupt Enable */
+#define CAN_IER_EWGIE 0x00000100U /*!<Error Warning Interrupt Enable */
+#define CAN_IER_EPVIE 0x00000200U /*!<Error Passive Interrupt Enable */
+#define CAN_IER_BOFIE 0x00000400U /*!<Bus-Off Interrupt Enable */
+#define CAN_IER_LECIE 0x00000800U /*!<Last Error Code Interrupt Enable */
+#define CAN_IER_ERRIE 0x00008000U /*!<Error Interrupt Enable */
+#define CAN_IER_WKUIE 0x00010000U /*!<Wakeup Interrupt Enable */
+#define CAN_IER_SLKIE 0x00020000U /*!<Sleep Interrupt Enable */
+#define CAN_IER_EWGIE 0x00000100U /*!<Error warning interrupt enable */
+#define CAN_IER_EPVIE 0x00000200U /*!<Error passive interrupt enable */
+#define CAN_IER_BOFIE 0x00000400U /*!<Bus-off interrupt enable */
+#define CAN_IER_LECIE 0x00000800U /*!<Last error code interrupt enable */
+#define CAN_IER_ERRIE 0x00008000U /*!<Error interrupt enable */
+
+
+/******************** Bit definition for CAN_ESR register *******************/
+#define CAN_ESR_EWGF 0x00000001U /*!<Error Warning Flag */
+#define CAN_ESR_EPVF 0x00000002U /*!<Error Passive Flag */
+#define CAN_ESR_BOFF 0x00000004U /*!<Bus-Off Flag */
+
+#define CAN_ESR_LEC 0x00000070U /*!<LEC[2:0] bits (Last Error Code) */
+#define CAN_ESR_LEC_0 0x00000010U /*!<Bit 0 */
+#define CAN_ESR_LEC_1 0x00000020U /*!<Bit 1 */
+#define CAN_ESR_LEC_2 0x00000040U /*!<Bit 2 */
+
+#define CAN_ESR_TEC 0x00FF0000U /*!<Least significant byte of the 9-bit Transmit Error Counter */
+#define CAN_ESR_REC 0xFF000000U /*!<Receive Error Counter */
+
+/******************* Bit definition for CAN_BTR register ********************/
+#define CAN_BTR_BRP 0x000003FFU /*!<Baud Rate Prescaler */
+#define CAN_BTR_TS1 0x000F0000U /*!<Time Segment 1 */
+#define CAN_BTR_TS1_0 0x00010000U /*!<Bit 0 */
+#define CAN_BTR_TS1_1 0x00020000U /*!<Bit 1 */
+#define CAN_BTR_TS1_2 0x00040000U /*!<Bit 2 */
+#define CAN_BTR_TS1_3 0x00080000U /*!<Bit 3 */
+#define CAN_BTR_TS2 0x00700000U /*!<Time Segment 2 */
+#define CAN_BTR_TS2_0 0x00100000U /*!<Bit 0 */
+#define CAN_BTR_TS2_1 0x00200000U /*!<Bit 1 */
+#define CAN_BTR_TS2_2 0x00400000U /*!<Bit 2 */
+#define CAN_BTR_SJW 0x03000000U /*!<Resynchronization Jump Width */
+#define CAN_BTR_SJW_0 0x01000000U /*!<Bit 0 */
+#define CAN_BTR_SJW_1 0x02000000U /*!<Bit 1 */
+#define CAN_BTR_LBKM 0x40000000U /*!<Loop Back Mode (Debug) */
+#define CAN_BTR_SILM 0x80000000U /*!<Silent Mode */
+
+
+/*!<Mailbox registers */
+/****************** Bit definition for CAN_TI0R register ********************/
+#define CAN_TI0R_TXRQ 0x00000001U /*!<Transmit Mailbox Request */
+#define CAN_TI0R_RTR 0x00000002U /*!<Remote Transmission Request */
+#define CAN_TI0R_IDE 0x00000004U /*!<Identifier Extension */
+#define CAN_TI0R_EXID 0x001FFFF8U /*!<Extended Identifier */
+#define CAN_TI0R_STID 0xFFE00000U /*!<Standard Identifier or Extended Identifier */
+
+/****************** Bit definition for CAN_TDT0R register *******************/
+#define CAN_TDT0R_DLC 0x0000000FU /*!<Data Length Code */
+#define CAN_TDT0R_TGT 0x00000100U /*!<Transmit Global Time */
+#define CAN_TDT0R_TIME 0xFFFF0000U /*!<Message Time Stamp */
+
+/****************** Bit definition for CAN_TDL0R register *******************/
+#define CAN_TDL0R_DATA0 0x000000FFU /*!<Data byte 0 */
+#define CAN_TDL0R_DATA1 0x0000FF00U /*!<Data byte 1 */
+#define CAN_TDL0R_DATA2 0x00FF0000U /*!<Data byte 2 */
+#define CAN_TDL0R_DATA3 0xFF000000U /*!<Data byte 3 */
+
+/****************** Bit definition for CAN_TDH0R register *******************/
+#define CAN_TDH0R_DATA4 0x000000FFU /*!<Data byte 4 */
+#define CAN_TDH0R_DATA5 0x0000FF00U /*!<Data byte 5 */
+#define CAN_TDH0R_DATA6 0x00FF0000U /*!<Data byte 6 */
+#define CAN_TDH0R_DATA7 0xFF000000U /*!<Data byte 7 */
+
+/******************* Bit definition for CAN_TI1R register *******************/
+#define CAN_TI1R_TXRQ 0x00000001U /*!<Transmit Mailbox Request */
+#define CAN_TI1R_RTR 0x00000002U /*!<Remote Transmission Request */
+#define CAN_TI1R_IDE 0x00000004U /*!<Identifier Extension */
+#define CAN_TI1R_EXID 0x001FFFF8U /*!<Extended Identifier */
+#define CAN_TI1R_STID 0xFFE00000U /*!<Standard Identifier or Extended Identifier */
+
+/******************* Bit definition for CAN_TDT1R register ******************/
+#define CAN_TDT1R_DLC 0x0000000FU /*!<Data Length Code */
+#define CAN_TDT1R_TGT 0x00000100U /*!<Transmit Global Time */
+#define CAN_TDT1R_TIME 0xFFFF0000U /*!<Message Time Stamp */
+
+/******************* Bit definition for CAN_TDL1R register ******************/
+#define CAN_TDL1R_DATA0 0x000000FFU /*!<Data byte 0 */
+#define CAN_TDL1R_DATA1 0x0000FF00U /*!<Data byte 1 */
+#define CAN_TDL1R_DATA2 0x00FF0000U /*!<Data byte 2 */
+#define CAN_TDL1R_DATA3 0xFF000000U /*!<Data byte 3 */
+
+/******************* Bit definition for CAN_TDH1R register ******************/
+#define CAN_TDH1R_DATA4 0x000000FFU /*!<Data byte 4 */
+#define CAN_TDH1R_DATA5 0x0000FF00U /*!<Data byte 5 */
+#define CAN_TDH1R_DATA6 0x00FF0000U /*!<Data byte 6 */
+#define CAN_TDH1R_DATA7 0xFF000000U /*!<Data byte 7 */
+
+/******************* Bit definition for CAN_TI2R register *******************/
+#define CAN_TI2R_TXRQ 0x00000001U /*!<Transmit Mailbox Request */
+#define CAN_TI2R_RTR 0x00000002U /*!<Remote Transmission Request */
+#define CAN_TI2R_IDE 0x00000004U /*!<Identifier Extension */
+#define CAN_TI2R_EXID 0x001FFFF8U /*!<Extended identifier */
+#define CAN_TI2R_STID 0xFFE00000U /*!<Standard Identifier or Extended Identifier */
+
+/******************* Bit definition for CAN_TDT2R register ******************/
+#define CAN_TDT2R_DLC 0x0000000FU /*!<Data Length Code */
+#define CAN_TDT2R_TGT 0x00000100U /*!<Transmit Global Time */
+#define CAN_TDT2R_TIME 0xFFFF0000U /*!<Message Time Stamp */
+
+/******************* Bit definition for CAN_TDL2R register ******************/
+#define CAN_TDL2R_DATA0 0x000000FFU /*!<Data byte 0 */
+#define CAN_TDL2R_DATA1 0x0000FF00U /*!<Data byte 1 */
+#define CAN_TDL2R_DATA2 0x00FF0000U /*!<Data byte 2 */
+#define CAN_TDL2R_DATA3 0xFF000000U /*!<Data byte 3 */
+
+/******************* Bit definition for CAN_TDH2R register ******************/
+#define CAN_TDH2R_DATA4 0x000000FFU /*!<Data byte 4 */
+#define CAN_TDH2R_DATA5 0x0000FF00U /*!<Data byte 5 */
+#define CAN_TDH2R_DATA6 0x00FF0000U /*!<Data byte 6 */
+#define CAN_TDH2R_DATA7 0xFF000000U /*!<Data byte 7 */
+
+/******************* Bit definition for CAN_RI0R register *******************/
+#define CAN_RI0R_RTR 0x00000002U /*!<Remote Transmission Request */
+#define CAN_RI0R_IDE 0x00000004U /*!<Identifier Extension */
+#define CAN_RI0R_EXID 0x001FFFF8U /*!<Extended Identifier */
+#define CAN_RI0R_STID 0xFFE00000U /*!<Standard Identifier or Extended Identifier */
+
+/******************* Bit definition for CAN_RDT0R register ******************/
+#define CAN_RDT0R_DLC 0x0000000FU /*!<Data Length Code */
+#define CAN_RDT0R_FMI 0x0000FF00U /*!<Filter Match Index */
+#define CAN_RDT0R_TIME 0xFFFF0000U /*!<Message Time Stamp */
+
+/******************* Bit definition for CAN_RDL0R register ******************/
+#define CAN_RDL0R_DATA0 0x000000FFU /*!<Data byte 0 */
+#define CAN_RDL0R_DATA1 0x0000FF00U /*!<Data byte 1 */
+#define CAN_RDL0R_DATA2 0x00FF0000U /*!<Data byte 2 */
+#define CAN_RDL0R_DATA3 0xFF000000U /*!<Data byte 3 */
+
+/******************* Bit definition for CAN_RDH0R register ******************/
+#define CAN_RDH0R_DATA4 0x000000FFU /*!<Data byte 4 */
+#define CAN_RDH0R_DATA5 0x0000FF00U /*!<Data byte 5 */
+#define CAN_RDH0R_DATA6 0x00FF0000U /*!<Data byte 6 */
+#define CAN_RDH0R_DATA7 0xFF000000U /*!<Data byte 7 */
+
+/******************* Bit definition for CAN_RI1R register *******************/
+#define CAN_RI1R_RTR 0x00000002U /*!<Remote Transmission Request */
+#define CAN_RI1R_IDE 0x00000004U /*!<Identifier Extension */
+#define CAN_RI1R_EXID 0x001FFFF8U /*!<Extended identifier */
+#define CAN_RI1R_STID 0xFFE00000U /*!<Standard Identifier or Extended Identifier */
+
+/******************* Bit definition for CAN_RDT1R register ******************/
+#define CAN_RDT1R_DLC 0x0000000FU /*!<Data Length Code */
+#define CAN_RDT1R_FMI 0x0000FF00U /*!<Filter Match Index */
+#define CAN_RDT1R_TIME 0xFFFF0000U /*!<Message Time Stamp */
+
+/******************* Bit definition for CAN_RDL1R register ******************/
+#define CAN_RDL1R_DATA0 0x000000FFU /*!<Data byte 0 */
+#define CAN_RDL1R_DATA1 0x0000FF00U /*!<Data byte 1 */
+#define CAN_RDL1R_DATA2 0x00FF0000U /*!<Data byte 2 */
+#define CAN_RDL1R_DATA3 0xFF000000U /*!<Data byte 3 */
+
+/******************* Bit definition for CAN_RDH1R register ******************/
+#define CAN_RDH1R_DATA4 0x000000FFU /*!<Data byte 4 */
+#define CAN_RDH1R_DATA5 0x0000FF00U /*!<Data byte 5 */
+#define CAN_RDH1R_DATA6 0x00FF0000U /*!<Data byte 6 */
+#define CAN_RDH1R_DATA7 0xFF000000U /*!<Data byte 7 */
+
+/*!<CAN filter registers */
+/******************* Bit definition for CAN_FMR register ********************/
+#define CAN_FMR_FINIT 0x01U /*!<Filter Init Mode */
+#define CAN_FMR_CAN2SB 0x00003F00U /*!<CAN2 start bank */
+
+/******************* Bit definition for CAN_FM1R register *******************/
+#define CAN_FM1R_FBM 0x0FFFFFFFU /*!<Filter Mode */
+#define CAN_FM1R_FBM0 0x00000001U /*!<Filter Init Mode bit 0 */
+#define CAN_FM1R_FBM1 0x00000002U /*!<Filter Init Mode bit 1 */
+#define CAN_FM1R_FBM2 0x00000004U /*!<Filter Init Mode bit 2 */
+#define CAN_FM1R_FBM3 0x00000008U /*!<Filter Init Mode bit 3 */
+#define CAN_FM1R_FBM4 0x00000010U /*!<Filter Init Mode bit 4 */
+#define CAN_FM1R_FBM5 0x00000020U /*!<Filter Init Mode bit 5 */
+#define CAN_FM1R_FBM6 0x00000040U /*!<Filter Init Mode bit 6 */
+#define CAN_FM1R_FBM7 0x00000080U /*!<Filter Init Mode bit 7 */
+#define CAN_FM1R_FBM8 0x00000100U /*!<Filter Init Mode bit 8 */
+#define CAN_FM1R_FBM9 0x00000200U /*!<Filter Init Mode bit 9 */
+#define CAN_FM1R_FBM10 0x00000400U /*!<Filter Init Mode bit 10 */
+#define CAN_FM1R_FBM11 0x00000800U /*!<Filter Init Mode bit 11 */
+#define CAN_FM1R_FBM12 0x00001000U /*!<Filter Init Mode bit 12 */
+#define CAN_FM1R_FBM13 0x00002000U /*!<Filter Init Mode bit 13 */
+#define CAN_FM1R_FBM14 0x00004000U /*!<Filter Init Mode bit 14 */
+#define CAN_FM1R_FBM15 0x00008000U /*!<Filter Init Mode bit 15 */
+#define CAN_FM1R_FBM16 0x00010000U /*!<Filter Init Mode bit 16 */
+#define CAN_FM1R_FBM17 0x00020000U /*!<Filter Init Mode bit 17 */
+#define CAN_FM1R_FBM18 0x00040000U /*!<Filter Init Mode bit 18 */
+#define CAN_FM1R_FBM19 0x00080000U /*!<Filter Init Mode bit 19 */
+#define CAN_FM1R_FBM20 0x00100000U /*!<Filter Init Mode bit 20 */
+#define CAN_FM1R_FBM21 0x00200000U /*!<Filter Init Mode bit 21 */
+#define CAN_FM1R_FBM22 0x00400000U /*!<Filter Init Mode bit 22 */
+#define CAN_FM1R_FBM23 0x00800000U /*!<Filter Init Mode bit 23 */
+#define CAN_FM1R_FBM24 0x01000000U /*!<Filter Init Mode bit 24 */
+#define CAN_FM1R_FBM25 0x02000000U /*!<Filter Init Mode bit 25 */
+#define CAN_FM1R_FBM26 0x04000000U /*!<Filter Init Mode bit 26 */
+#define CAN_FM1R_FBM27 0x08000000U /*!<Filter Init Mode bit 27 */
+
+/******************* Bit definition for CAN_FS1R register *******************/
+#define CAN_FS1R_FSC 0x0FFFFFFFU /*!<Filter Scale Configuration */
+#define CAN_FS1R_FSC0 0x00000001U /*!<Filter Scale Configuration bit 0 */
+#define CAN_FS1R_FSC1 0x00000002U /*!<Filter Scale Configuration bit 1 */
+#define CAN_FS1R_FSC2 0x00000004U /*!<Filter Scale Configuration bit 2 */
+#define CAN_FS1R_FSC3 0x00000008U /*!<Filter Scale Configuration bit 3 */
+#define CAN_FS1R_FSC4 0x00000010U /*!<Filter Scale Configuration bit 4 */
+#define CAN_FS1R_FSC5 0x00000020U /*!<Filter Scale Configuration bit 5 */
+#define CAN_FS1R_FSC6 0x00000040U /*!<Filter Scale Configuration bit 6 */
+#define CAN_FS1R_FSC7 0x00000080U /*!<Filter Scale Configuration bit 7 */
+#define CAN_FS1R_FSC8 0x00000100U /*!<Filter Scale Configuration bit 8 */
+#define CAN_FS1R_FSC9 0x00000200U /*!<Filter Scale Configuration bit 9 */
+#define CAN_FS1R_FSC10 0x00000400U /*!<Filter Scale Configuration bit 10 */
+#define CAN_FS1R_FSC11 0x00000800U /*!<Filter Scale Configuration bit 11 */
+#define CAN_FS1R_FSC12 0x00001000U /*!<Filter Scale Configuration bit 12 */
+#define CAN_FS1R_FSC13 0x00002000U /*!<Filter Scale Configuration bit 13 */
+#define CAN_FS1R_FSC14 0x00004000U /*!<Filter Scale Configuration bit 14 */
+#define CAN_FS1R_FSC15 0x00008000U /*!<Filter Scale Configuration bit 15 */
+#define CAN_FS1R_FSC16 0x00010000U /*!<Filter Scale Configuration bit 16 */
+#define CAN_FS1R_FSC17 0x00020000U /*!<Filter Scale Configuration bit 17 */
+#define CAN_FS1R_FSC18 0x00040000U /*!<Filter Scale Configuration bit 18 */
+#define CAN_FS1R_FSC19 0x00080000U /*!<Filter Scale Configuration bit 19 */
+#define CAN_FS1R_FSC20 0x00100000U /*!<Filter Scale Configuration bit 20 */
+#define CAN_FS1R_FSC21 0x00200000U /*!<Filter Scale Configuration bit 21 */
+#define CAN_FS1R_FSC22 0x00400000U /*!<Filter Scale Configuration bit 22 */
+#define CAN_FS1R_FSC23 0x00800000U /*!<Filter Scale Configuration bit 23 */
+#define CAN_FS1R_FSC24 0x01000000U /*!<Filter Scale Configuration bit 24 */
+#define CAN_FS1R_FSC25 0x02000000U /*!<Filter Scale Configuration bit 25 */
+#define CAN_FS1R_FSC26 0x04000000U /*!<Filter Scale Configuration bit 26 */
+#define CAN_FS1R_FSC27 0x08000000U /*!<Filter Scale Configuration bit 27 */
+
+/****************** Bit definition for CAN_FFA1R register *******************/
+#define CAN_FFA1R_FFA 0x0FFFFFFFU /*!<Filter FIFO Assignment */
+#define CAN_FFA1R_FFA0 0x00000001U /*!<Filter FIFO Assignment bit 0 */
+#define CAN_FFA1R_FFA1 0x00000002U /*!<Filter FIFO Assignment bit 1 */
+#define CAN_FFA1R_FFA2 0x00000004U /*!<Filter FIFO Assignment bit 2 */
+#define CAN_FFA1R_FFA3 0x00000008U /*!<Filter FIFO Assignment bit 3 */
+#define CAN_FFA1R_FFA4 0x00000010U /*!<Filter FIFO Assignment bit 4 */
+#define CAN_FFA1R_FFA5 0x00000020U /*!<Filter FIFO Assignment bit 5 */
+#define CAN_FFA1R_FFA6 0x00000040U /*!<Filter FIFO Assignment bit 6 */
+#define CAN_FFA1R_FFA7 0x00000080U /*!<Filter FIFO Assignment bit 7 */
+#define CAN_FFA1R_FFA8 0x00000100U /*!<Filter FIFO Assignment bit 8 */
+#define CAN_FFA1R_FFA9 0x00000200U /*!<Filter FIFO Assignment bit 9 */
+#define CAN_FFA1R_FFA10 0x00000400U /*!<Filter FIFO Assignment bit 10 */
+#define CAN_FFA1R_FFA11 0x00000800U /*!<Filter FIFO Assignment bit 11 */
+#define CAN_FFA1R_FFA12 0x00001000U /*!<Filter FIFO Assignment bit 12 */
+#define CAN_FFA1R_FFA13 0x00002000U /*!<Filter FIFO Assignment bit 13 */
+#define CAN_FFA1R_FFA14 0x00004000U /*!<Filter FIFO Assignment bit 14 */
+#define CAN_FFA1R_FFA15 0x00008000U /*!<Filter FIFO Assignment bit 15 */
+#define CAN_FFA1R_FFA16 0x00010000U /*!<Filter FIFO Assignment bit 16 */
+#define CAN_FFA1R_FFA17 0x00020000U /*!<Filter FIFO Assignment bit 17 */
+#define CAN_FFA1R_FFA18 0x00040000U /*!<Filter FIFO Assignment bit 18 */
+#define CAN_FFA1R_FFA19 0x00080000U /*!<Filter FIFO Assignment bit 19 */
+#define CAN_FFA1R_FFA20 0x00100000U /*!<Filter FIFO Assignment bit 20 */
+#define CAN_FFA1R_FFA21 0x00200000U /*!<Filter FIFO Assignment bit 21 */
+#define CAN_FFA1R_FFA22 0x00400000U /*!<Filter FIFO Assignment bit 22 */
+#define CAN_FFA1R_FFA23 0x00800000U /*!<Filter FIFO Assignment bit 23 */
+#define CAN_FFA1R_FFA24 0x01000000U /*!<Filter FIFO Assignment bit 24 */
+#define CAN_FFA1R_FFA25 0x02000000U /*!<Filter FIFO Assignment bit 25 */
+#define CAN_FFA1R_FFA26 0x04000000U /*!<Filter FIFO Assignment bit 26 */
+#define CAN_FFA1R_FFA27 0x08000000U /*!<Filter FIFO Assignment bit 27 */
+
+/******************* Bit definition for CAN_FA1R register *******************/
+#define CAN_FA1R_FACT 0x0FFFFFFFU /*!<Filter Active */
+#define CAN_FA1R_FACT0 0x00000001U /*!<Filter Active bit 0 */
+#define CAN_FA1R_FACT1 0x00000002U /*!<Filter Active bit 1 */
+#define CAN_FA1R_FACT2 0x00000004U /*!<Filter Active bit 2 */
+#define CAN_FA1R_FACT3 0x00000008U /*!<Filter Active bit 3 */
+#define CAN_FA1R_FACT4 0x00000010U /*!<Filter Active bit 4 */
+#define CAN_FA1R_FACT5 0x00000020U /*!<Filter Active bit 5 */
+#define CAN_FA1R_FACT6 0x00000040U /*!<Filter Active bit 6 */
+#define CAN_FA1R_FACT7 0x00000080U /*!<Filter Active bit 7 */
+#define CAN_FA1R_FACT8 0x00000100U /*!<Filter Active bit 8 */
+#define CAN_FA1R_FACT9 0x00000200U /*!<Filter Active bit 9 */
+#define CAN_FA1R_FACT10 0x00000400U /*!<Filter Active bit 10 */
+#define CAN_FA1R_FACT11 0x00000800U /*!<Filter Active bit 11 */
+#define CAN_FA1R_FACT12 0x00001000U /*!<Filter Active bit 12 */
+#define CAN_FA1R_FACT13 0x00002000U /*!<Filter Active bit 13 */
+#define CAN_FA1R_FACT14 0x00004000U /*!<Filter Active bit 14 */
+#define CAN_FA1R_FACT15 0x00008000U /*!<Filter Active bit 15 */
+#define CAN_FA1R_FACT16 0x00010000U /*!<Filter Active bit 16 */
+#define CAN_FA1R_FACT17 0x00020000U /*!<Filter Active bit 17 */
+#define CAN_FA1R_FACT18 0x00040000U /*!<Filter Active bit 18 */
+#define CAN_FA1R_FACT19 0x00080000U /*!<Filter Active bit 19 */
+#define CAN_FA1R_FACT20 0x00100000U /*!<Filter Active bit 20 */
+#define CAN_FA1R_FACT21 0x00200000U /*!<Filter Active bit 21 */
+#define CAN_FA1R_FACT22 0x00400000U /*!<Filter Active bit 22 */
+#define CAN_FA1R_FACT23 0x00800000U /*!<Filter Active bit 23 */
+#define CAN_FA1R_FACT24 0x01000000U /*!<Filter Active bit 24 */
+#define CAN_FA1R_FACT25 0x02000000U /*!<Filter Active bit 25 */
+#define CAN_FA1R_FACT26 0x04000000U /*!<Filter Active bit 26 */
+#define CAN_FA1R_FACT27 0x08000000U /*!<Filter Active bit 27 */
+
+/******************* Bit definition for CAN_F0R1 register *******************/
+#define CAN_F0R1_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F0R1_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F0R1_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F0R1_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F0R1_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F0R1_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F0R1_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F0R1_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F0R1_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F0R1_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F0R1_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F0R1_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F0R1_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F0R1_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F0R1_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F0R1_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F0R1_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F0R1_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F0R1_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F0R1_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F0R1_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F0R1_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F0R1_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F0R1_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F0R1_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F0R1_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F0R1_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F0R1_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F0R1_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F0R1_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F0R1_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F0R1_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F1R1 register *******************/
+#define CAN_F1R1_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F1R1_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F1R1_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F1R1_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F1R1_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F1R1_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F1R1_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F1R1_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F1R1_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F1R1_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F1R1_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F1R1_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F1R1_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F1R1_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F1R1_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F1R1_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F1R1_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F1R1_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F1R1_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F1R1_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F1R1_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F1R1_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F1R1_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F1R1_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F1R1_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F1R1_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F1R1_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F1R1_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F1R1_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F1R1_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F1R1_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F1R1_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F2R1 register *******************/
+#define CAN_F2R1_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F2R1_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F2R1_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F2R1_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F2R1_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F2R1_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F2R1_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F2R1_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F2R1_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F2R1_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F2R1_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F2R1_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F2R1_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F2R1_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F2R1_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F2R1_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F2R1_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F2R1_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F2R1_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F2R1_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F2R1_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F2R1_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F2R1_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F2R1_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F2R1_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F2R1_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F2R1_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F2R1_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F2R1_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F2R1_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F2R1_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F2R1_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F3R1 register *******************/
+#define CAN_F3R1_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F3R1_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F3R1_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F3R1_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F3R1_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F3R1_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F3R1_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F3R1_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F3R1_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F3R1_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F3R1_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F3R1_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F3R1_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F3R1_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F3R1_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F3R1_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F3R1_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F3R1_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F3R1_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F3R1_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F3R1_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F3R1_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F3R1_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F3R1_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F3R1_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F3R1_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F3R1_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F3R1_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F3R1_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F3R1_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F3R1_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F3R1_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F4R1 register *******************/
+#define CAN_F4R1_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F4R1_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F4R1_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F4R1_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F4R1_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F4R1_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F4R1_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F4R1_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F4R1_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F4R1_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F4R1_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F4R1_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F4R1_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F4R1_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F4R1_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F4R1_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F4R1_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F4R1_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F4R1_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F4R1_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F4R1_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F4R1_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F4R1_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F4R1_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F4R1_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F4R1_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F4R1_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F4R1_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F4R1_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F4R1_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F4R1_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F4R1_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F5R1 register *******************/
+#define CAN_F5R1_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F5R1_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F5R1_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F5R1_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F5R1_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F5R1_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F5R1_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F5R1_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F5R1_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F5R1_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F5R1_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F5R1_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F5R1_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F5R1_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F5R1_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F5R1_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F5R1_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F5R1_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F5R1_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F5R1_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F5R1_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F5R1_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F5R1_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F5R1_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F5R1_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F5R1_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F5R1_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F5R1_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F5R1_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F5R1_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F5R1_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F5R1_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F6R1 register *******************/
+#define CAN_F6R1_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F6R1_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F6R1_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F6R1_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F6R1_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F6R1_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F6R1_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F6R1_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F6R1_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F6R1_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F6R1_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F6R1_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F6R1_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F6R1_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F6R1_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F6R1_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F6R1_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F6R1_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F6R1_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F6R1_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F6R1_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F6R1_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F6R1_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F6R1_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F6R1_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F6R1_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F6R1_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F6R1_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F6R1_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F6R1_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F6R1_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F6R1_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F7R1 register *******************/
+#define CAN_F7R1_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F7R1_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F7R1_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F7R1_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F7R1_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F7R1_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F7R1_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F7R1_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F7R1_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F7R1_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F7R1_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F7R1_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F7R1_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F7R1_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F7R1_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F7R1_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F7R1_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F7R1_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F7R1_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F7R1_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F7R1_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F7R1_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F7R1_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F7R1_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F7R1_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F7R1_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F7R1_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F7R1_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F7R1_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F7R1_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F7R1_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F7R1_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F8R1 register *******************/
+#define CAN_F8R1_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F8R1_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F8R1_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F8R1_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F8R1_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F8R1_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F8R1_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F8R1_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F8R1_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F8R1_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F8R1_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F8R1_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F8R1_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F8R1_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F8R1_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F8R1_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F8R1_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F8R1_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F8R1_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F8R1_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F8R1_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F8R1_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F8R1_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F8R1_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F8R1_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F8R1_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F8R1_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F8R1_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F8R1_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F8R1_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F8R1_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F8R1_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F9R1 register *******************/
+#define CAN_F9R1_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F9R1_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F9R1_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F9R1_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F9R1_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F9R1_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F9R1_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F9R1_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F9R1_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F9R1_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F9R1_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F9R1_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F9R1_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F9R1_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F9R1_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F9R1_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F9R1_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F9R1_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F9R1_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F9R1_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F9R1_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F9R1_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F9R1_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F9R1_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F9R1_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F9R1_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F9R1_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F9R1_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F9R1_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F9R1_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F9R1_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F9R1_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F10R1 register ******************/
+#define CAN_F10R1_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F10R1_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F10R1_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F10R1_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F10R1_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F10R1_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F10R1_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F10R1_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F10R1_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F10R1_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F10R1_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F10R1_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F10R1_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F10R1_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F10R1_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F10R1_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F10R1_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F10R1_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F10R1_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F10R1_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F10R1_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F10R1_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F10R1_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F10R1_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F10R1_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F10R1_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F10R1_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F10R1_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F10R1_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F10R1_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F10R1_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F10R1_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F11R1 register ******************/
+#define CAN_F11R1_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F11R1_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F11R1_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F11R1_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F11R1_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F11R1_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F11R1_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F11R1_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F11R1_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F11R1_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F11R1_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F11R1_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F11R1_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F11R1_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F11R1_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F11R1_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F11R1_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F11R1_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F11R1_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F11R1_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F11R1_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F11R1_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F11R1_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F11R1_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F11R1_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F11R1_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F11R1_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F11R1_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F11R1_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F11R1_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F11R1_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F11R1_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F12R1 register ******************/
+#define CAN_F12R1_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F12R1_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F12R1_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F12R1_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F12R1_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F12R1_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F12R1_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F12R1_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F12R1_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F12R1_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F12R1_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F12R1_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F12R1_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F12R1_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F12R1_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F12R1_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F12R1_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F12R1_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F12R1_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F12R1_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F12R1_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F12R1_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F12R1_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F12R1_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F12R1_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F12R1_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F12R1_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F12R1_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F12R1_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F12R1_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F12R1_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F12R1_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F13R1 register ******************/
+#define CAN_F13R1_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F13R1_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F13R1_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F13R1_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F13R1_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F13R1_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F13R1_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F13R1_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F13R1_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F13R1_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F13R1_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F13R1_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F13R1_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F13R1_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F13R1_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F13R1_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F13R1_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F13R1_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F13R1_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F13R1_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F13R1_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F13R1_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F13R1_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F13R1_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F13R1_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F13R1_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F13R1_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F13R1_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F13R1_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F13R1_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F13R1_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F13R1_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F0R2 register *******************/
+#define CAN_F0R2_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F0R2_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F0R2_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F0R2_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F0R2_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F0R2_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F0R2_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F0R2_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F0R2_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F0R2_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F0R2_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F0R2_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F0R2_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F0R2_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F0R2_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F0R2_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F0R2_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F0R2_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F0R2_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F0R2_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F0R2_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F0R2_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F0R2_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F0R2_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F0R2_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F0R2_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F0R2_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F0R2_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F0R2_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F0R2_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F0R2_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F0R2_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F1R2 register *******************/
+#define CAN_F1R2_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F1R2_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F1R2_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F1R2_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F1R2_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F1R2_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F1R2_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F1R2_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F1R2_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F1R2_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F1R2_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F1R2_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F1R2_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F1R2_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F1R2_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F1R2_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F1R2_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F1R2_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F1R2_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F1R2_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F1R2_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F1R2_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F1R2_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F1R2_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F1R2_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F1R2_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F1R2_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F1R2_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F1R2_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F1R2_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F1R2_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F1R2_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F2R2 register *******************/
+#define CAN_F2R2_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F2R2_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F2R2_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F2R2_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F2R2_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F2R2_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F2R2_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F2R2_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F2R2_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F2R2_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F2R2_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F2R2_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F2R2_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F2R2_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F2R2_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F2R2_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F2R2_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F2R2_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F2R2_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F2R2_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F2R2_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F2R2_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F2R2_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F2R2_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F2R2_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F2R2_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F2R2_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F2R2_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F2R2_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F2R2_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F2R2_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F2R2_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F3R2 register *******************/
+#define CAN_F3R2_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F3R2_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F3R2_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F3R2_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F3R2_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F3R2_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F3R2_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F3R2_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F3R2_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F3R2_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F3R2_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F3R2_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F3R2_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F3R2_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F3R2_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F3R2_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F3R2_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F3R2_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F3R2_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F3R2_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F3R2_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F3R2_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F3R2_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F3R2_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F3R2_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F3R2_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F3R2_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F3R2_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F3R2_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F3R2_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F3R2_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F3R2_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F4R2 register *******************/
+#define CAN_F4R2_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F4R2_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F4R2_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F4R2_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F4R2_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F4R2_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F4R2_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F4R2_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F4R2_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F4R2_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F4R2_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F4R2_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F4R2_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F4R2_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F4R2_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F4R2_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F4R2_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F4R2_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F4R2_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F4R2_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F4R2_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F4R2_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F4R2_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F4R2_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F4R2_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F4R2_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F4R2_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F4R2_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F4R2_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F4R2_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F4R2_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F4R2_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F5R2 register *******************/
+#define CAN_F5R2_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F5R2_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F5R2_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F5R2_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F5R2_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F5R2_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F5R2_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F5R2_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F5R2_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F5R2_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F5R2_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F5R2_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F5R2_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F5R2_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F5R2_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F5R2_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F5R2_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F5R2_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F5R2_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F5R2_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F5R2_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F5R2_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F5R2_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F5R2_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F5R2_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F5R2_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F5R2_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F5R2_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F5R2_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F5R2_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F5R2_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F5R2_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F6R2 register *******************/
+#define CAN_F6R2_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F6R2_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F6R2_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F6R2_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F6R2_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F6R2_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F6R2_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F6R2_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F6R2_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F6R2_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F6R2_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F6R2_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F6R2_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F6R2_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F6R2_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F6R2_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F6R2_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F6R2_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F6R2_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F6R2_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F6R2_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F6R2_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F6R2_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F6R2_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F6R2_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F6R2_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F6R2_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F6R2_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F6R2_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F6R2_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F6R2_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F6R2_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F7R2 register *******************/
+#define CAN_F7R2_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F7R2_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F7R2_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F7R2_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F7R2_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F7R2_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F7R2_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F7R2_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F7R2_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F7R2_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F7R2_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F7R2_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F7R2_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F7R2_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F7R2_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F7R2_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F7R2_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F7R2_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F7R2_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F7R2_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F7R2_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F7R2_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F7R2_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F7R2_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F7R2_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F7R2_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F7R2_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F7R2_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F7R2_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F7R2_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F7R2_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F7R2_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F8R2 register *******************/
+#define CAN_F8R2_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F8R2_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F8R2_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F8R2_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F8R2_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F8R2_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F8R2_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F8R2_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F8R2_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F8R2_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F8R2_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F8R2_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F8R2_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F8R2_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F8R2_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F8R2_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F8R2_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F8R2_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F8R2_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F8R2_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F8R2_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F8R2_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F8R2_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F8R2_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F8R2_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F8R2_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F8R2_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F8R2_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F8R2_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F8R2_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F8R2_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F8R2_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F9R2 register *******************/
+#define CAN_F9R2_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F9R2_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F9R2_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F9R2_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F9R2_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F9R2_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F9R2_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F9R2_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F9R2_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F9R2_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F9R2_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F9R2_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F9R2_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F9R2_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F9R2_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F9R2_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F9R2_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F9R2_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F9R2_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F9R2_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F9R2_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F9R2_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F9R2_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F9R2_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F9R2_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F9R2_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F9R2_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F9R2_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F9R2_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F9R2_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F9R2_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F9R2_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F10R2 register ******************/
+#define CAN_F10R2_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F10R2_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F10R2_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F10R2_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F10R2_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F10R2_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F10R2_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F10R2_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F10R2_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F10R2_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F10R2_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F10R2_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F10R2_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F10R2_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F10R2_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F10R2_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F10R2_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F10R2_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F10R2_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F10R2_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F10R2_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F10R2_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F10R2_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F10R2_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F10R2_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F10R2_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F10R2_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F10R2_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F10R2_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F10R2_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F10R2_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F10R2_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F11R2 register ******************/
+#define CAN_F11R2_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F11R2_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F11R2_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F11R2_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F11R2_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F11R2_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F11R2_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F11R2_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F11R2_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F11R2_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F11R2_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F11R2_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F11R2_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F11R2_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F11R2_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F11R2_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F11R2_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F11R2_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F11R2_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F11R2_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F11R2_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F11R2_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F11R2_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F11R2_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F11R2_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F11R2_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F11R2_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F11R2_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F11R2_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F11R2_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F11R2_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F11R2_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F12R2 register ******************/
+#define CAN_F12R2_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F12R2_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F12R2_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F12R2_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F12R2_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F12R2_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F12R2_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F12R2_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F12R2_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F12R2_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F12R2_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F12R2_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F12R2_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F12R2_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F12R2_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F12R2_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F12R2_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F12R2_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F12R2_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F12R2_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F12R2_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F12R2_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F12R2_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F12R2_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F12R2_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F12R2_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F12R2_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F12R2_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F12R2_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F12R2_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F12R2_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F12R2_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F13R2 register ******************/
+#define CAN_F13R2_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F13R2_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F13R2_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F13R2_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F13R2_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F13R2_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F13R2_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F13R2_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F13R2_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F13R2_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F13R2_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F13R2_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F13R2_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F13R2_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F13R2_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F13R2_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F13R2_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F13R2_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F13R2_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F13R2_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F13R2_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F13R2_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F13R2_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F13R2_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F13R2_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F13R2_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F13R2_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F13R2_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F13R2_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F13R2_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F13R2_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F13R2_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************************************************************************/
+/* */
+/* CRC calculation unit */
+/* */
+/******************************************************************************/
+/******************* Bit definition for CRC_DR register *********************/
+#define CRC_DR_DR 0xFFFFFFFFU /*!< Data register bits */
+
+
+/******************* Bit definition for CRC_IDR register ********************/
+#define CRC_IDR_IDR 0xFFU /*!< General-purpose 8-bit data register bits */
+
+
+/******************** Bit definition for CRC_CR register ********************/
+#define CRC_CR_RESET 0x01U /*!< RESET bit */
+
+/******************************************************************************/
+/* */
+/* Crypto Processor */
+/* */
+/******************************************************************************/
+/******************* Bits definition for CRYP_CR register ********************/
+#define CRYP_CR_ALGODIR 0x00000004U
+
+#define CRYP_CR_ALGOMODE 0x00080038U
+#define CRYP_CR_ALGOMODE_0 0x00000008U
+#define CRYP_CR_ALGOMODE_1 0x00000010U
+#define CRYP_CR_ALGOMODE_2 0x00000020U
+#define CRYP_CR_ALGOMODE_TDES_ECB 0x00000000U
+#define CRYP_CR_ALGOMODE_TDES_CBC 0x00000008U
+#define CRYP_CR_ALGOMODE_DES_ECB 0x00000010U
+#define CRYP_CR_ALGOMODE_DES_CBC 0x00000018U
+#define CRYP_CR_ALGOMODE_AES_ECB 0x00000020U
+#define CRYP_CR_ALGOMODE_AES_CBC 0x00000028U
+#define CRYP_CR_ALGOMODE_AES_CTR 0x00000030U
+#define CRYP_CR_ALGOMODE_AES_KEY 0x00000038U
+
+#define CRYP_CR_DATATYPE 0x000000C0U
+#define CRYP_CR_DATATYPE_0 0x00000040U
+#define CRYP_CR_DATATYPE_1 0x00000080U
+#define CRYP_CR_KEYSIZE 0x00000300U
+#define CRYP_CR_KEYSIZE_0 0x00000100U
+#define CRYP_CR_KEYSIZE_1 0x00000200U
+#define CRYP_CR_FFLUSH 0x00004000U
+#define CRYP_CR_CRYPEN 0x00008000U
+
+#define CRYP_CR_GCM_CCMPH 0x00030000U
+#define CRYP_CR_GCM_CCMPH_0 0x00010000U
+#define CRYP_CR_GCM_CCMPH_1 0x00020000U
+#define CRYP_CR_ALGOMODE_3 0x00080000U
+
+/****************** Bits definition for CRYP_SR register *********************/
+#define CRYP_SR_IFEM 0x00000001U
+#define CRYP_SR_IFNF 0x00000002U
+#define CRYP_SR_OFNE 0x00000004U
+#define CRYP_SR_OFFU 0x00000008U
+#define CRYP_SR_BUSY 0x00000010U
+/****************** Bits definition for CRYP_DMACR register ******************/
+#define CRYP_DMACR_DIEN 0x00000001U
+#define CRYP_DMACR_DOEN 0x00000002U
+/***************** Bits definition for CRYP_IMSCR register ******************/
+#define CRYP_IMSCR_INIM 0x00000001U
+#define CRYP_IMSCR_OUTIM 0x00000002U
+/****************** Bits definition for CRYP_RISR register *******************/
+#define CRYP_RISR_OUTRIS 0x00000001U
+#define CRYP_RISR_INRIS 0x00000002U
+/****************** Bits definition for CRYP_MISR register *******************/
+#define CRYP_MISR_INMIS 0x00000001U
+#define CRYP_MISR_OUTMIS 0x00000002U
+
+/******************************************************************************/
+/* */
+/* Digital to Analog Converter */
+/* */
+/******************************************************************************/
+/******************** Bit definition for DAC_CR register ********************/
+#define DAC_CR_EN1 0x00000001U /*!<DAC channel1 enable */
+#define DAC_CR_BOFF1 0x00000002U /*!<DAC channel1 output buffer disable */
+#define DAC_CR_TEN1 0x00000004U /*!<DAC channel1 Trigger enable */
+
+#define DAC_CR_TSEL1 0x00000038U /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */
+#define DAC_CR_TSEL1_0 0x00000008U /*!<Bit 0 */
+#define DAC_CR_TSEL1_1 0x00000010U /*!<Bit 1 */
+#define DAC_CR_TSEL1_2 0x00000020U /*!<Bit 2 */
+
+#define DAC_CR_WAVE1 0x000000C0U /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
+#define DAC_CR_WAVE1_0 0x00000040U /*!<Bit 0 */
+#define DAC_CR_WAVE1_1 0x00000080U /*!<Bit 1 */
+
+#define DAC_CR_MAMP1 0x00000F00U /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
+#define DAC_CR_MAMP1_0 0x00000100U /*!<Bit 0 */
+#define DAC_CR_MAMP1_1 0x00000200U /*!<Bit 1 */
+#define DAC_CR_MAMP1_2 0x00000400U /*!<Bit 2 */
+#define DAC_CR_MAMP1_3 0x00000800U /*!<Bit 3 */
+
+#define DAC_CR_DMAEN1 0x00001000U /*!<DAC channel1 DMA enable */
+#define DAC_CR_DMAUDRIE1 0x00002000U /*!<DAC channel1 DMA underrun interrupt enable*/
+#define DAC_CR_EN2 0x00010000U /*!<DAC channel2 enable */
+#define DAC_CR_BOFF2 0x00020000U /*!<DAC channel2 output buffer disable */
+#define DAC_CR_TEN2 0x00040000U /*!<DAC channel2 Trigger enable */
+
+#define DAC_CR_TSEL2 0x00380000U /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */
+#define DAC_CR_TSEL2_0 0x00080000U /*!<Bit 0 */
+#define DAC_CR_TSEL2_1 0x00100000U /*!<Bit 1 */
+#define DAC_CR_TSEL2_2 0x00200000U /*!<Bit 2 */
+
+#define DAC_CR_WAVE2 0x00C00000U /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
+#define DAC_CR_WAVE2_0 0x00400000U /*!<Bit 0 */
+#define DAC_CR_WAVE2_1 0x00800000U /*!<Bit 1 */
+
+#define DAC_CR_MAMP2 0x0F000000U /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
+#define DAC_CR_MAMP2_0 0x01000000U /*!<Bit 0 */
+#define DAC_CR_MAMP2_1 0x02000000U /*!<Bit 1 */
+#define DAC_CR_MAMP2_2 0x04000000U /*!<Bit 2 */
+#define DAC_CR_MAMP2_3 0x08000000U /*!<Bit 3 */
+
+#define DAC_CR_DMAEN2 0x10000000U /*!<DAC channel2 DMA enabled */
+#define DAC_CR_DMAUDRIE2 0x20000000U /*!<DAC channel2 DMA underrun interrupt enable*/
+
+/***************** Bit definition for DAC_SWTRIGR register ******************/
+#define DAC_SWTRIGR_SWTRIG1 0x01U /*!<DAC channel1 software trigger */
+#define DAC_SWTRIGR_SWTRIG2 0x02U /*!<DAC channel2 software trigger */
+
+/***************** Bit definition for DAC_DHR12R1 register ******************/
+#define DAC_DHR12R1_DACC1DHR 0x0FFFU /*!<DAC channel1 12-bit Right aligned data */
+
+/***************** Bit definition for DAC_DHR12L1 register ******************/
+#define DAC_DHR12L1_DACC1DHR 0xFFF0U /*!<DAC channel1 12-bit Left aligned data */
+
+/****************** Bit definition for DAC_DHR8R1 register ******************/
+#define DAC_DHR8R1_DACC1DHR 0xFFU /*!<DAC channel1 8-bit Right aligned data */
+
+/***************** Bit definition for DAC_DHR12R2 register ******************/
+#define DAC_DHR12R2_DACC2DHR 0x0FFFU /*!<DAC channel2 12-bit Right aligned data */
+
+/***************** Bit definition for DAC_DHR12L2 register ******************/
+#define DAC_DHR12L2_DACC2DHR 0xFFF0U /*!<DAC channel2 12-bit Left aligned data */
+
+/****************** Bit definition for DAC_DHR8R2 register ******************/
+#define DAC_DHR8R2_DACC2DHR 0xFFU /*!<DAC channel2 8-bit Right aligned data */
+
+/***************** Bit definition for DAC_DHR12RD register ******************/
+#define DAC_DHR12RD_DACC1DHR 0x00000FFFU /*!<DAC channel1 12-bit Right aligned data */
+#define DAC_DHR12RD_DACC2DHR 0x0FFF0000U /*!<DAC channel2 12-bit Right aligned data */
+
+/***************** Bit definition for DAC_DHR12LD register ******************/
+#define DAC_DHR12LD_DACC1DHR 0x0000FFF0U /*!<DAC channel1 12-bit Left aligned data */
+#define DAC_DHR12LD_DACC2DHR 0xFFF00000U /*!<DAC channel2 12-bit Left aligned data */
+
+/****************** Bit definition for DAC_DHR8RD register ******************/
+#define DAC_DHR8RD_DACC1DHR 0x00FFU /*!<DAC channel1 8-bit Right aligned data */
+#define DAC_DHR8RD_DACC2DHR 0xFF00U /*!<DAC channel2 8-bit Right aligned data */
+
+/******************* Bit definition for DAC_DOR1 register *******************/
+#define DAC_DOR1_DACC1DOR 0x0FFFU /*!<DAC channel1 data output */
+
+/******************* Bit definition for DAC_DOR2 register *******************/
+#define DAC_DOR2_DACC2DOR 0x0FFFU /*!<DAC channel2 data output */
+
+/******************** Bit definition for DAC_SR register ********************/
+#define DAC_SR_DMAUDR1 0x00002000U /*!<DAC channel1 DMA underrun flag */
+#define DAC_SR_DMAUDR2 0x20000000U /*!<DAC channel2 DMA underrun flag */
+
+/******************************************************************************/
+/* */
+/* Debug MCU */
+/* */
+/******************************************************************************/
+
+/******************************************************************************/
+/* */
+/* DMA Controller */
+/* */
+/******************************************************************************/
+/******************** Bits definition for DMA_SxCR register *****************/
+#define DMA_SxCR_CHSEL 0x0E000000U
+#define DMA_SxCR_CHSEL_0 0x02000000U
+#define DMA_SxCR_CHSEL_1 0x04000000U
+#define DMA_SxCR_CHSEL_2 0x08000000U
+#define DMA_SxCR_MBURST 0x01800000U
+#define DMA_SxCR_MBURST_0 0x00800000U
+#define DMA_SxCR_MBURST_1 0x01000000U
+#define DMA_SxCR_PBURST 0x00600000U
+#define DMA_SxCR_PBURST_0 0x00200000U
+#define DMA_SxCR_PBURST_1 0x00400000U
+#define DMA_SxCR_CT 0x00080000U
+#define DMA_SxCR_DBM 0x00040000U
+#define DMA_SxCR_PL 0x00030000U
+#define DMA_SxCR_PL_0 0x00010000U
+#define DMA_SxCR_PL_1 0x00020000U
+#define DMA_SxCR_PINCOS 0x00008000U
+#define DMA_SxCR_MSIZE 0x00006000U
+#define DMA_SxCR_MSIZE_0 0x00002000U
+#define DMA_SxCR_MSIZE_1 0x00004000U
+#define DMA_SxCR_PSIZE 0x00001800U
+#define DMA_SxCR_PSIZE_0 0x00000800U
+#define DMA_SxCR_PSIZE_1 0x00001000U
+#define DMA_SxCR_MINC 0x00000400U
+#define DMA_SxCR_PINC 0x00000200U
+#define DMA_SxCR_CIRC 0x00000100U
+#define DMA_SxCR_DIR 0x000000C0U
+#define DMA_SxCR_DIR_0 0x00000040U
+#define DMA_SxCR_DIR_1 0x00000080U
+#define DMA_SxCR_PFCTRL 0x00000020U
+#define DMA_SxCR_TCIE 0x00000010U
+#define DMA_SxCR_HTIE 0x00000008U
+#define DMA_SxCR_TEIE 0x00000004U
+#define DMA_SxCR_DMEIE 0x00000002U
+#define DMA_SxCR_EN 0x00000001U
+
+/* Legacy defines */
+#define DMA_SxCR_ACK 0x00100000U
+
+/******************** Bits definition for DMA_SxCNDTR register **************/
+#define DMA_SxNDT 0x0000FFFFU
+#define DMA_SxNDT_0 0x00000001U
+#define DMA_SxNDT_1 0x00000002U
+#define DMA_SxNDT_2 0x00000004U
+#define DMA_SxNDT_3 0x00000008U
+#define DMA_SxNDT_4 0x00000010U
+#define DMA_SxNDT_5 0x00000020U
+#define DMA_SxNDT_6 0x00000040U
+#define DMA_SxNDT_7 0x00000080U
+#define DMA_SxNDT_8 0x00000100U
+#define DMA_SxNDT_9 0x00000200U
+#define DMA_SxNDT_10 0x00000400U
+#define DMA_SxNDT_11 0x00000800U
+#define DMA_SxNDT_12 0x00001000U
+#define DMA_SxNDT_13 0x00002000U
+#define DMA_SxNDT_14 0x00004000U
+#define DMA_SxNDT_15 0x00008000U
+
+/******************** Bits definition for DMA_SxFCR register ****************/
+#define DMA_SxFCR_FEIE 0x00000080U
+#define DMA_SxFCR_FS 0x00000038U
+#define DMA_SxFCR_FS_0 0x00000008U
+#define DMA_SxFCR_FS_1 0x00000010U
+#define DMA_SxFCR_FS_2 0x00000020U
+#define DMA_SxFCR_DMDIS 0x00000004U
+#define DMA_SxFCR_FTH 0x00000003U
+#define DMA_SxFCR_FTH_0 0x00000001U
+#define DMA_SxFCR_FTH_1 0x00000002U
+
+/******************** Bits definition for DMA_LISR register *****************/
+#define DMA_LISR_TCIF3 0x08000000U
+#define DMA_LISR_HTIF3 0x04000000U
+#define DMA_LISR_TEIF3 0x02000000U
+#define DMA_LISR_DMEIF3 0x01000000U
+#define DMA_LISR_FEIF3 0x00400000U
+#define DMA_LISR_TCIF2 0x00200000U
+#define DMA_LISR_HTIF2 0x00100000U
+#define DMA_LISR_TEIF2 0x00080000U
+#define DMA_LISR_DMEIF2 0x00040000U
+#define DMA_LISR_FEIF2 0x00010000U
+#define DMA_LISR_TCIF1 0x00000800U
+#define DMA_LISR_HTIF1 0x00000400U
+#define DMA_LISR_TEIF1 0x00000200U
+#define DMA_LISR_DMEIF1 0x00000100U
+#define DMA_LISR_FEIF1 0x00000040U
+#define DMA_LISR_TCIF0 0x00000020U
+#define DMA_LISR_HTIF0 0x00000010U
+#define DMA_LISR_TEIF0 0x00000008U
+#define DMA_LISR_DMEIF0 0x00000004U
+#define DMA_LISR_FEIF0 0x00000001U
+
+/******************** Bits definition for DMA_HISR register *****************/
+#define DMA_HISR_TCIF7 0x08000000U
+#define DMA_HISR_HTIF7 0x04000000U
+#define DMA_HISR_TEIF7 0x02000000U
+#define DMA_HISR_DMEIF7 0x01000000U
+#define DMA_HISR_FEIF7 0x00400000U
+#define DMA_HISR_TCIF6 0x00200000U
+#define DMA_HISR_HTIF6 0x00100000U
+#define DMA_HISR_TEIF6 0x00080000U
+#define DMA_HISR_DMEIF6 0x00040000U
+#define DMA_HISR_FEIF6 0x00010000U
+#define DMA_HISR_TCIF5 0x00000800U
+#define DMA_HISR_HTIF5 0x00000400U
+#define DMA_HISR_TEIF5 0x00000200U
+#define DMA_HISR_DMEIF5 0x00000100U
+#define DMA_HISR_FEIF5 0x00000040U
+#define DMA_HISR_TCIF4 0x00000020U
+#define DMA_HISR_HTIF4 0x00000010U
+#define DMA_HISR_TEIF4 0x00000008U
+#define DMA_HISR_DMEIF4 0x00000004U
+#define DMA_HISR_FEIF4 0x00000001U
+
+/******************** Bits definition for DMA_LIFCR register ****************/
+#define DMA_LIFCR_CTCIF3 0x08000000U
+#define DMA_LIFCR_CHTIF3 0x04000000U
+#define DMA_LIFCR_CTEIF3 0x02000000U
+#define DMA_LIFCR_CDMEIF3 0x01000000U
+#define DMA_LIFCR_CFEIF3 0x00400000U
+#define DMA_LIFCR_CTCIF2 0x00200000U
+#define DMA_LIFCR_CHTIF2 0x00100000U
+#define DMA_LIFCR_CTEIF2 0x00080000U
+#define DMA_LIFCR_CDMEIF2 0x00040000U
+#define DMA_LIFCR_CFEIF2 0x00010000U
+#define DMA_LIFCR_CTCIF1 0x00000800U
+#define DMA_LIFCR_CHTIF1 0x00000400U
+#define DMA_LIFCR_CTEIF1 0x00000200U
+#define DMA_LIFCR_CDMEIF1 0x00000100U
+#define DMA_LIFCR_CFEIF1 0x00000040U
+#define DMA_LIFCR_CTCIF0 0x00000020U
+#define DMA_LIFCR_CHTIF0 0x00000010U
+#define DMA_LIFCR_CTEIF0 0x00000008U
+#define DMA_LIFCR_CDMEIF0 0x00000004U
+#define DMA_LIFCR_CFEIF0 0x00000001U
+
+/******************** Bits definition for DMA_HIFCR register ****************/
+#define DMA_HIFCR_CTCIF7 0x08000000U
+#define DMA_HIFCR_CHTIF7 0x04000000U
+#define DMA_HIFCR_CTEIF7 0x02000000U
+#define DMA_HIFCR_CDMEIF7 0x01000000U
+#define DMA_HIFCR_CFEIF7 0x00400000U
+#define DMA_HIFCR_CTCIF6 0x00200000U
+#define DMA_HIFCR_CHTIF6 0x00100000U
+#define DMA_HIFCR_CTEIF6 0x00080000U
+#define DMA_HIFCR_CDMEIF6 0x00040000U
+#define DMA_HIFCR_CFEIF6 0x00010000U
+#define DMA_HIFCR_CTCIF5 0x00000800U
+#define DMA_HIFCR_CHTIF5 0x00000400U
+#define DMA_HIFCR_CTEIF5 0x00000200U
+#define DMA_HIFCR_CDMEIF5 0x00000100U
+#define DMA_HIFCR_CFEIF5 0x00000040U
+#define DMA_HIFCR_CTCIF4 0x00000020U
+#define DMA_HIFCR_CHTIF4 0x00000010U
+#define DMA_HIFCR_CTEIF4 0x00000008U
+#define DMA_HIFCR_CDMEIF4 0x00000004U
+#define DMA_HIFCR_CFEIF4 0x00000001U
+
+
+/******************************************************************************/
+/* */
+/* External Interrupt/Event Controller */
+/* */
+/******************************************************************************/
+/******************* Bit definition for EXTI_IMR register *******************/
+#define EXTI_IMR_MR0 0x00000001U /*!< Interrupt Mask on line 0 */
+#define EXTI_IMR_MR1 0x00000002U /*!< Interrupt Mask on line 1 */
+#define EXTI_IMR_MR2 0x00000004U /*!< Interrupt Mask on line 2 */
+#define EXTI_IMR_MR3 0x00000008U /*!< Interrupt Mask on line 3 */
+#define EXTI_IMR_MR4 0x00000010U /*!< Interrupt Mask on line 4 */
+#define EXTI_IMR_MR5 0x00000020U /*!< Interrupt Mask on line 5 */
+#define EXTI_IMR_MR6 0x00000040U /*!< Interrupt Mask on line 6 */
+#define EXTI_IMR_MR7 0x00000080U /*!< Interrupt Mask on line 7 */
+#define EXTI_IMR_MR8 0x00000100U /*!< Interrupt Mask on line 8 */
+#define EXTI_IMR_MR9 0x00000200U /*!< Interrupt Mask on line 9 */
+#define EXTI_IMR_MR10 0x00000400U /*!< Interrupt Mask on line 10 */
+#define EXTI_IMR_MR11 0x00000800U /*!< Interrupt Mask on line 11 */
+#define EXTI_IMR_MR12 0x00001000U /*!< Interrupt Mask on line 12 */
+#define EXTI_IMR_MR13 0x00002000U /*!< Interrupt Mask on line 13 */
+#define EXTI_IMR_MR14 0x00004000U /*!< Interrupt Mask on line 14 */
+#define EXTI_IMR_MR15 0x00008000U /*!< Interrupt Mask on line 15 */
+#define EXTI_IMR_MR16 0x00010000U /*!< Interrupt Mask on line 16 */
+#define EXTI_IMR_MR17 0x00020000U /*!< Interrupt Mask on line 17 */
+#define EXTI_IMR_MR18 0x00040000U /*!< Interrupt Mask on line 18 */
+#define EXTI_IMR_MR19 0x00080000U /*!< Interrupt Mask on line 19 */
+#define EXTI_IMR_MR20 0x00100000U /*!< Interrupt Mask on line 20 */
+#define EXTI_IMR_MR21 0x00200000U /*!< Interrupt Mask on line 21 */
+#define EXTI_IMR_MR22 0x00400000U /*!< Interrupt Mask on line 22 */
+
+/******************* Bit definition for EXTI_EMR register *******************/
+#define EXTI_EMR_MR0 0x00000001U /*!< Event Mask on line 0 */
+#define EXTI_EMR_MR1 0x00000002U /*!< Event Mask on line 1 */
+#define EXTI_EMR_MR2 0x00000004U /*!< Event Mask on line 2 */
+#define EXTI_EMR_MR3 0x00000008U /*!< Event Mask on line 3 */
+#define EXTI_EMR_MR4 0x00000010U /*!< Event Mask on line 4 */
+#define EXTI_EMR_MR5 0x00000020U /*!< Event Mask on line 5 */
+#define EXTI_EMR_MR6 0x00000040U /*!< Event Mask on line 6 */
+#define EXTI_EMR_MR7 0x00000080U /*!< Event Mask on line 7 */
+#define EXTI_EMR_MR8 0x00000100U /*!< Event Mask on line 8 */
+#define EXTI_EMR_MR9 0x00000200U /*!< Event Mask on line 9 */
+#define EXTI_EMR_MR10 0x00000400U /*!< Event Mask on line 10 */
+#define EXTI_EMR_MR11 0x00000800U /*!< Event Mask on line 11 */
+#define EXTI_EMR_MR12 0x00001000U /*!< Event Mask on line 12 */
+#define EXTI_EMR_MR13 0x00002000U /*!< Event Mask on line 13 */
+#define EXTI_EMR_MR14 0x00004000U /*!< Event Mask on line 14 */
+#define EXTI_EMR_MR15 0x00008000U /*!< Event Mask on line 15 */
+#define EXTI_EMR_MR16 0x00010000U /*!< Event Mask on line 16 */
+#define EXTI_EMR_MR17 0x00020000U /*!< Event Mask on line 17 */
+#define EXTI_EMR_MR18 0x00040000U /*!< Event Mask on line 18 */
+#define EXTI_EMR_MR19 0x00080000U /*!< Event Mask on line 19 */
+#define EXTI_EMR_MR20 0x00100000U /*!< Event Mask on line 20 */
+#define EXTI_EMR_MR21 0x00200000U /*!< Event Mask on line 21 */
+#define EXTI_EMR_MR22 0x00400000U /*!< Event Mask on line 22 */
+
+/****************** Bit definition for EXTI_RTSR register *******************/
+#define EXTI_RTSR_TR0 0x00000001U /*!< Rising trigger event configuration bit of line 0 */
+#define EXTI_RTSR_TR1 0x00000002U /*!< Rising trigger event configuration bit of line 1 */
+#define EXTI_RTSR_TR2 0x00000004U /*!< Rising trigger event configuration bit of line 2 */
+#define EXTI_RTSR_TR3 0x00000008U /*!< Rising trigger event configuration bit of line 3 */
+#define EXTI_RTSR_TR4 0x00000010U /*!< Rising trigger event configuration bit of line 4 */
+#define EXTI_RTSR_TR5 0x00000020U /*!< Rising trigger event configuration bit of line 5 */
+#define EXTI_RTSR_TR6 0x00000040U /*!< Rising trigger event configuration bit of line 6 */
+#define EXTI_RTSR_TR7 0x00000080U /*!< Rising trigger event configuration bit of line 7 */
+#define EXTI_RTSR_TR8 0x00000100U /*!< Rising trigger event configuration bit of line 8 */
+#define EXTI_RTSR_TR9 0x00000200U /*!< Rising trigger event configuration bit of line 9 */
+#define EXTI_RTSR_TR10 0x00000400U /*!< Rising trigger event configuration bit of line 10 */
+#define EXTI_RTSR_TR11 0x00000800U /*!< Rising trigger event configuration bit of line 11 */
+#define EXTI_RTSR_TR12 0x00001000U /*!< Rising trigger event configuration bit of line 12 */
+#define EXTI_RTSR_TR13 0x00002000U /*!< Rising trigger event configuration bit of line 13 */
+#define EXTI_RTSR_TR14 0x00004000U /*!< Rising trigger event configuration bit of line 14 */
+#define EXTI_RTSR_TR15 0x00008000U /*!< Rising trigger event configuration bit of line 15 */
+#define EXTI_RTSR_TR16 0x00010000U /*!< Rising trigger event configuration bit of line 16 */
+#define EXTI_RTSR_TR17 0x00020000U /*!< Rising trigger event configuration bit of line 17 */
+#define EXTI_RTSR_TR18 0x00040000U /*!< Rising trigger event configuration bit of line 18 */
+#define EXTI_RTSR_TR19 0x00080000U /*!< Rising trigger event configuration bit of line 19 */
+#define EXTI_RTSR_TR20 0x00100000U /*!< Rising trigger event configuration bit of line 20 */
+#define EXTI_RTSR_TR21 0x00200000U /*!< Rising trigger event configuration bit of line 21 */
+#define EXTI_RTSR_TR22 0x00400000U /*!< Rising trigger event configuration bit of line 22 */
+
+/****************** Bit definition for EXTI_FTSR register *******************/
+#define EXTI_FTSR_TR0 0x00000001U /*!< Falling trigger event configuration bit of line 0 */
+#define EXTI_FTSR_TR1 0x00000002U /*!< Falling trigger event configuration bit of line 1 */
+#define EXTI_FTSR_TR2 0x00000004U /*!< Falling trigger event configuration bit of line 2 */
+#define EXTI_FTSR_TR3 0x00000008U /*!< Falling trigger event configuration bit of line 3 */
+#define EXTI_FTSR_TR4 0x00000010U /*!< Falling trigger event configuration bit of line 4 */
+#define EXTI_FTSR_TR5 0x00000020U /*!< Falling trigger event configuration bit of line 5 */
+#define EXTI_FTSR_TR6 0x00000040U /*!< Falling trigger event configuration bit of line 6 */
+#define EXTI_FTSR_TR7 0x00000080U /*!< Falling trigger event configuration bit of line 7 */
+#define EXTI_FTSR_TR8 0x00000100U /*!< Falling trigger event configuration bit of line 8 */
+#define EXTI_FTSR_TR9 0x00000200U /*!< Falling trigger event configuration bit of line 9 */
+#define EXTI_FTSR_TR10 0x00000400U /*!< Falling trigger event configuration bit of line 10 */
+#define EXTI_FTSR_TR11 0x00000800U /*!< Falling trigger event configuration bit of line 11 */
+#define EXTI_FTSR_TR12 0x00001000U /*!< Falling trigger event configuration bit of line 12 */
+#define EXTI_FTSR_TR13 0x00002000U /*!< Falling trigger event configuration bit of line 13 */
+#define EXTI_FTSR_TR14 0x00004000U /*!< Falling trigger event configuration bit of line 14 */
+#define EXTI_FTSR_TR15 0x00008000U /*!< Falling trigger event configuration bit of line 15 */
+#define EXTI_FTSR_TR16 0x00010000U /*!< Falling trigger event configuration bit of line 16 */
+#define EXTI_FTSR_TR17 0x00020000U /*!< Falling trigger event configuration bit of line 17 */
+#define EXTI_FTSR_TR18 0x00040000U /*!< Falling trigger event configuration bit of line 18 */
+#define EXTI_FTSR_TR19 0x00080000U /*!< Falling trigger event configuration bit of line 19 */
+#define EXTI_FTSR_TR20 0x00100000U /*!< Falling trigger event configuration bit of line 20 */
+#define EXTI_FTSR_TR21 0x00200000U /*!< Falling trigger event configuration bit of line 21 */
+#define EXTI_FTSR_TR22 0x00400000U /*!< Falling trigger event configuration bit of line 22 */
+
+/****************** Bit definition for EXTI_SWIER register ******************/
+#define EXTI_SWIER_SWIER0 0x00000001U /*!< Software Interrupt on line 0 */
+#define EXTI_SWIER_SWIER1 0x00000002U /*!< Software Interrupt on line 1 */
+#define EXTI_SWIER_SWIER2 0x00000004U /*!< Software Interrupt on line 2 */
+#define EXTI_SWIER_SWIER3 0x00000008U /*!< Software Interrupt on line 3 */
+#define EXTI_SWIER_SWIER4 0x00000010U /*!< Software Interrupt on line 4 */
+#define EXTI_SWIER_SWIER5 0x00000020U /*!< Software Interrupt on line 5 */
+#define EXTI_SWIER_SWIER6 0x00000040U /*!< Software Interrupt on line 6 */
+#define EXTI_SWIER_SWIER7 0x00000080U /*!< Software Interrupt on line 7 */
+#define EXTI_SWIER_SWIER8 0x00000100U /*!< Software Interrupt on line 8 */
+#define EXTI_SWIER_SWIER9 0x00000200U /*!< Software Interrupt on line 9 */
+#define EXTI_SWIER_SWIER10 0x00000400U /*!< Software Interrupt on line 10 */
+#define EXTI_SWIER_SWIER11 0x00000800U /*!< Software Interrupt on line 11 */
+#define EXTI_SWIER_SWIER12 0x00001000U /*!< Software Interrupt on line 12 */
+#define EXTI_SWIER_SWIER13 0x00002000U /*!< Software Interrupt on line 13 */
+#define EXTI_SWIER_SWIER14 0x00004000U /*!< Software Interrupt on line 14 */
+#define EXTI_SWIER_SWIER15 0x00008000U /*!< Software Interrupt on line 15 */
+#define EXTI_SWIER_SWIER16 0x00010000U /*!< Software Interrupt on line 16 */
+#define EXTI_SWIER_SWIER17 0x00020000U /*!< Software Interrupt on line 17 */
+#define EXTI_SWIER_SWIER18 0x00040000U /*!< Software Interrupt on line 18 */
+#define EXTI_SWIER_SWIER19 0x00080000U /*!< Software Interrupt on line 19 */
+#define EXTI_SWIER_SWIER20 0x00100000U /*!< Software Interrupt on line 20 */
+#define EXTI_SWIER_SWIER21 0x00200000U /*!< Software Interrupt on line 21 */
+#define EXTI_SWIER_SWIER22 0x00400000U /*!< Software Interrupt on line 22 */
+
+/******************* Bit definition for EXTI_PR register ********************/
+#define EXTI_PR_PR0 0x00000001U /*!< Pending bit for line 0 */
+#define EXTI_PR_PR1 0x00000002U /*!< Pending bit for line 1 */
+#define EXTI_PR_PR2 0x00000004U /*!< Pending bit for line 2 */
+#define EXTI_PR_PR3 0x00000008U /*!< Pending bit for line 3 */
+#define EXTI_PR_PR4 0x00000010U /*!< Pending bit for line 4 */
+#define EXTI_PR_PR5 0x00000020U /*!< Pending bit for line 5 */
+#define EXTI_PR_PR6 0x00000040U /*!< Pending bit for line 6 */
+#define EXTI_PR_PR7 0x00000080U /*!< Pending bit for line 7 */
+#define EXTI_PR_PR8 0x00000100U /*!< Pending bit for line 8 */
+#define EXTI_PR_PR9 0x00000200U /*!< Pending bit for line 9 */
+#define EXTI_PR_PR10 0x00000400U /*!< Pending bit for line 10 */
+#define EXTI_PR_PR11 0x00000800U /*!< Pending bit for line 11 */
+#define EXTI_PR_PR12 0x00001000U /*!< Pending bit for line 12 */
+#define EXTI_PR_PR13 0x00002000U /*!< Pending bit for line 13 */
+#define EXTI_PR_PR14 0x00004000U /*!< Pending bit for line 14 */
+#define EXTI_PR_PR15 0x00008000U /*!< Pending bit for line 15 */
+#define EXTI_PR_PR16 0x00010000U /*!< Pending bit for line 16 */
+#define EXTI_PR_PR17 0x00020000U /*!< Pending bit for line 17 */
+#define EXTI_PR_PR18 0x00040000U /*!< Pending bit for line 18 */
+#define EXTI_PR_PR19 0x00080000U /*!< Pending bit for line 19 */
+#define EXTI_PR_PR20 0x00100000U /*!< Pending bit for line 20 */
+#define EXTI_PR_PR21 0x00200000U /*!< Pending bit for line 21 */
+#define EXTI_PR_PR22 0x00400000U /*!< Pending bit for line 22 */
+
+/******************************************************************************/
+/* */
+/* FLASH */
+/* */
+/******************************************************************************/
+/******************* Bits definition for FLASH_ACR register *****************/
+#define FLASH_ACR_LATENCY 0x0000000FU
+#define FLASH_ACR_LATENCY_0WS 0x00000000U
+#define FLASH_ACR_LATENCY_1WS 0x00000001U
+#define FLASH_ACR_LATENCY_2WS 0x00000002U
+#define FLASH_ACR_LATENCY_3WS 0x00000003U
+#define FLASH_ACR_LATENCY_4WS 0x00000004U
+#define FLASH_ACR_LATENCY_5WS 0x00000005U
+#define FLASH_ACR_LATENCY_6WS 0x00000006U
+#define FLASH_ACR_LATENCY_7WS 0x00000007U
+
+#define FLASH_ACR_PRFTEN 0x00000100U
+#define FLASH_ACR_ICEN 0x00000200U
+#define FLASH_ACR_DCEN 0x00000400U
+#define FLASH_ACR_ICRST 0x00000800U
+#define FLASH_ACR_DCRST 0x00001000U
+#define FLASH_ACR_BYTE0_ADDRESS 0x40023C00U
+#define FLASH_ACR_BYTE2_ADDRESS 0x40023C03U
+
+/******************* Bits definition for FLASH_SR register ******************/
+#define FLASH_SR_EOP 0x00000001U
+#define FLASH_SR_SOP 0x00000002U
+#define FLASH_SR_WRPERR 0x00000010U
+#define FLASH_SR_PGAERR 0x00000020U
+#define FLASH_SR_PGPERR 0x00000040U
+#define FLASH_SR_PGSERR 0x00000080U
+#define FLASH_SR_BSY 0x00010000U
+
+/******************* Bits definition for FLASH_CR register ******************/
+#define FLASH_CR_PG 0x00000001U
+#define FLASH_CR_SER 0x00000002U
+#define FLASH_CR_MER 0x00000004U
+#define FLASH_CR_SNB 0x000000F8U
+#define FLASH_CR_SNB_0 0x00000008U
+#define FLASH_CR_SNB_1 0x00000010U
+#define FLASH_CR_SNB_2 0x00000020U
+#define FLASH_CR_SNB_3 0x00000040U
+#define FLASH_CR_SNB_4 0x00000080U
+#define FLASH_CR_PSIZE 0x00000300U
+#define FLASH_CR_PSIZE_0 0x00000100U
+#define FLASH_CR_PSIZE_1 0x00000200U
+#define FLASH_CR_STRT 0x00010000U
+#define FLASH_CR_EOPIE 0x01000000U
+#define FLASH_CR_LOCK 0x80000000U
+
+/******************* Bits definition for FLASH_OPTCR register ***************/
+#define FLASH_OPTCR_OPTLOCK 0x00000001U
+#define FLASH_OPTCR_OPTSTRT 0x00000002U
+#define FLASH_OPTCR_BOR_LEV_0 0x00000004U
+#define FLASH_OPTCR_BOR_LEV_1 0x00000008U
+#define FLASH_OPTCR_BOR_LEV 0x0000000CU
+
+#define FLASH_OPTCR_WDG_SW 0x00000020U
+#define FLASH_OPTCR_nRST_STOP 0x00000040U
+#define FLASH_OPTCR_nRST_STDBY 0x00000080U
+#define FLASH_OPTCR_RDP 0x0000FF00U
+#define FLASH_OPTCR_RDP_0 0x00000100U
+#define FLASH_OPTCR_RDP_1 0x00000200U
+#define FLASH_OPTCR_RDP_2 0x00000400U
+#define FLASH_OPTCR_RDP_3 0x00000800U
+#define FLASH_OPTCR_RDP_4 0x00001000U
+#define FLASH_OPTCR_RDP_5 0x00002000U
+#define FLASH_OPTCR_RDP_6 0x00004000U
+#define FLASH_OPTCR_RDP_7 0x00008000U
+#define FLASH_OPTCR_nWRP 0x0FFF0000U
+#define FLASH_OPTCR_nWRP_0 0x00010000U
+#define FLASH_OPTCR_nWRP_1 0x00020000U
+#define FLASH_OPTCR_nWRP_2 0x00040000U
+#define FLASH_OPTCR_nWRP_3 0x00080000U
+#define FLASH_OPTCR_nWRP_4 0x00100000U
+#define FLASH_OPTCR_nWRP_5 0x00200000U
+#define FLASH_OPTCR_nWRP_6 0x00400000U
+#define FLASH_OPTCR_nWRP_7 0x00800000U
+#define FLASH_OPTCR_nWRP_8 0x01000000U
+#define FLASH_OPTCR_nWRP_9 0x02000000U
+#define FLASH_OPTCR_nWRP_10 0x04000000U
+#define FLASH_OPTCR_nWRP_11 0x08000000U
+
+/****************** Bits definition for FLASH_OPTCR1 register ***************/
+#define FLASH_OPTCR1_nWRP 0x0FFF0000U
+#define FLASH_OPTCR1_nWRP_0 0x00010000U
+#define FLASH_OPTCR1_nWRP_1 0x00020000U
+#define FLASH_OPTCR1_nWRP_2 0x00040000U
+#define FLASH_OPTCR1_nWRP_3 0x00080000U
+#define FLASH_OPTCR1_nWRP_4 0x00100000U
+#define FLASH_OPTCR1_nWRP_5 0x00200000U
+#define FLASH_OPTCR1_nWRP_6 0x00400000U
+#define FLASH_OPTCR1_nWRP_7 0x00800000U
+#define FLASH_OPTCR1_nWRP_8 0x01000000U
+#define FLASH_OPTCR1_nWRP_9 0x02000000U
+#define FLASH_OPTCR1_nWRP_10 0x04000000U
+#define FLASH_OPTCR1_nWRP_11 0x08000000U
+
+/******************************************************************************/
+/* */
+/* Flexible Static Memory Controller */
+/* */
+/******************************************************************************/
+/****************** Bit definition for FSMC_BCR1 register *******************/
+#define FSMC_BCR1_MBKEN 0x00000001U /*!<Memory bank enable bit */
+#define FSMC_BCR1_MUXEN 0x00000002U /*!<Address/data multiplexing enable bit */
+
+#define FSMC_BCR1_MTYP 0x0000000CU /*!<MTYP[1:0] bits (Memory type) */
+#define FSMC_BCR1_MTYP_0 0x00000004U /*!<Bit 0 */
+#define FSMC_BCR1_MTYP_1 0x00000008U /*!<Bit 1 */
+
+#define FSMC_BCR1_MWID 0x00000030U /*!<MWID[1:0] bits (Memory data bus width) */
+#define FSMC_BCR1_MWID_0 0x00000010U /*!<Bit 0 */
+#define FSMC_BCR1_MWID_1 0x00000020U /*!<Bit 1 */
+
+#define FSMC_BCR1_FACCEN 0x00000040U /*!<Flash access enable */
+#define FSMC_BCR1_BURSTEN 0x00000100U /*!<Burst enable bit */
+#define FSMC_BCR1_WAITPOL 0x00000200U /*!<Wait signal polarity bit */
+#define FSMC_BCR1_WRAPMOD 0x00000400U /*!<Wrapped burst mode support */
+#define FSMC_BCR1_WAITCFG 0x00000800U /*!<Wait timing configuration */
+#define FSMC_BCR1_WREN 0x00001000U /*!<Write enable bit */
+#define FSMC_BCR1_WAITEN 0x00002000U /*!<Wait enable bit */
+#define FSMC_BCR1_EXTMOD 0x00004000U /*!<Extended mode enable */
+#define FSMC_BCR1_ASYNCWAIT 0x00008000U /*!<Asynchronous wait */
+#define FSMC_BCR1_CPSIZE 0x00070000U /*!<CRAM page size */
+#define FSMC_BCR1_CPSIZE_0 0x00010000U /*!<Bit 0 */
+#define FSMC_BCR1_CPSIZE_1 0x00020000U /*!<Bit 1 */
+#define FSMC_BCR1_CPSIZE_2 0x00040000U /*!<Bit 2 */
+#define FSMC_BCR1_CBURSTRW 0x00080000U /*!<Write burst enable */
+
+/****************** Bit definition for FSMC_BCR2 register *******************/
+#define FSMC_BCR2_MBKEN 0x00000001U /*!<Memory bank enable bit */
+#define FSMC_BCR2_MUXEN 0x00000002U /*!<Address/data multiplexing enable bit */
+
+#define FSMC_BCR2_MTYP 0x0000000CU /*!<MTYP[1:0] bits (Memory type) */
+#define FSMC_BCR2_MTYP_0 0x00000004U /*!<Bit 0 */
+#define FSMC_BCR2_MTYP_1 0x00000008U /*!<Bit 1 */
+
+#define FSMC_BCR2_MWID 0x00000030U /*!<MWID[1:0] bits (Memory data bus width) */
+#define FSMC_BCR2_MWID_0 0x00000010U /*!<Bit 0 */
+#define FSMC_BCR2_MWID_1 0x00000020U /*!<Bit 1 */
+
+#define FSMC_BCR2_FACCEN 0x00000040U /*!<Flash access enable */
+#define FSMC_BCR2_BURSTEN 0x00000100U /*!<Burst enable bit */
+#define FSMC_BCR2_WAITPOL 0x00000200U /*!<Wait signal polarity bit */
+#define FSMC_BCR2_WRAPMOD 0x00000400U /*!<Wrapped burst mode support */
+#define FSMC_BCR2_WAITCFG 0x00000800U /*!<Wait timing configuration */
+#define FSMC_BCR2_WREN 0x00001000U /*!<Write enable bit */
+#define FSMC_BCR2_WAITEN 0x00002000U /*!<Wait enable bit */
+#define FSMC_BCR2_EXTMOD 0x00004000U /*!<Extended mode enable */
+#define FSMC_BCR2_ASYNCWAIT 0x00008000U /*!<Asynchronous wait */
+#define FSMC_BCR2_CPSIZE 0x00070000U /*!<CRAM page size */
+#define FSMC_BCR2_CPSIZE_0 0x00010000U /*!<Bit 0 */
+#define FSMC_BCR2_CPSIZE_1 0x00020000U /*!<Bit 1 */
+#define FSMC_BCR2_CPSIZE_2 0x00040000U /*!<Bit 2 */
+#define FSMC_BCR2_CBURSTRW 0x00080000U /*!<Write burst enable */
+
+/****************** Bit definition for FSMC_BCR3 register *******************/
+#define FSMC_BCR3_MBKEN 0x00000001U /*!<Memory bank enable bit */
+#define FSMC_BCR3_MUXEN 0x00000002U /*!<Address/data multiplexing enable bit */
+
+#define FSMC_BCR3_MTYP 0x0000000CU /*!<MTYP[1:0] bits (Memory type) */
+#define FSMC_BCR3_MTYP_0 0x00000004U /*!<Bit 0 */
+#define FSMC_BCR3_MTYP_1 0x00000008U /*!<Bit 1 */
+
+#define FSMC_BCR3_MWID 0x00000030U /*!<MWID[1:0] bits (Memory data bus width) */
+#define FSMC_BCR3_MWID_0 0x00000010U /*!<Bit 0 */
+#define FSMC_BCR3_MWID_1 0x00000020U /*!<Bit 1 */
+
+#define FSMC_BCR3_FACCEN 0x00000040U /*!<Flash access enable */
+#define FSMC_BCR3_BURSTEN 0x00000100U /*!<Burst enable bit */
+#define FSMC_BCR3_WAITPOL 0x00000200U /*!<Wait signal polarity bit */
+#define FSMC_BCR3_WRAPMOD 0x00000400U /*!<Wrapped burst mode support */
+#define FSMC_BCR3_WAITCFG 0x00000800U /*!<Wait timing configuration */
+#define FSMC_BCR3_WREN 0x00001000U /*!<Write enable bit */
+#define FSMC_BCR3_WAITEN 0x00002000U /*!<Wait enable bit */
+#define FSMC_BCR3_EXTMOD 0x00004000U /*!<Extended mode enable */
+#define FSMC_BCR3_ASYNCWAIT 0x00008000U /*!<Asynchronous wait */
+#define FSMC_BCR3_CPSIZE 0x00070000U /*!<CRAM page size */
+#define FSMC_BCR3_CPSIZE_0 0x00010000U /*!<Bit 0 */
+#define FSMC_BCR3_CPSIZE_1 0x00020000U /*!<Bit 1 */
+#define FSMC_BCR3_CPSIZE_2 0x00040000U /*!<Bit 2 */
+#define FSMC_BCR3_CBURSTRW 0x00080000U /*!<Write burst enable */
+
+/****************** Bit definition for FSMC_BCR4 register *******************/
+#define FSMC_BCR4_MBKEN 0x00000001U /*!<Memory bank enable bit */
+#define FSMC_BCR4_MUXEN 0x00000002U /*!<Address/data multiplexing enable bit */
+
+#define FSMC_BCR4_MTYP 0x0000000CU /*!<MTYP[1:0] bits (Memory type) */
+#define FSMC_BCR4_MTYP_0 0x00000004U /*!<Bit 0 */
+#define FSMC_BCR4_MTYP_1 0x00000008U /*!<Bit 1 */
+
+#define FSMC_BCR4_MWID 0x00000030U /*!<MWID[1:0] bits (Memory data bus width) */
+#define FSMC_BCR4_MWID_0 0x00000010U /*!<Bit 0 */
+#define FSMC_BCR4_MWID_1 0x00000020U /*!<Bit 1 */
+
+#define FSMC_BCR4_FACCEN 0x00000040U /*!<Flash access enable */
+#define FSMC_BCR4_BURSTEN 0x00000100U /*!<Burst enable bit */
+#define FSMC_BCR4_WAITPOL 0x00000200U /*!<Wait signal polarity bit */
+#define FSMC_BCR4_WRAPMOD 0x00000400U /*!<Wrapped burst mode support */
+#define FSMC_BCR4_WAITCFG 0x00000800U /*!<Wait timing configuration */
+#define FSMC_BCR4_WREN 0x00001000U /*!<Write enable bit */
+#define FSMC_BCR4_WAITEN 0x00002000U /*!<Wait enable bit */
+#define FSMC_BCR4_EXTMOD 0x00004000U /*!<Extended mode enable */
+#define FSMC_BCR4_ASYNCWAIT 0x00008000U /*!<Asynchronous wait */
+#define FSMC_BCR4_CPSIZE 0x00070000U /*!<CRAM page size */
+#define FSMC_BCR4_CPSIZE_0 0x00010000U /*!<Bit 0 */
+#define FSMC_BCR4_CPSIZE_1 0x00020000U /*!<Bit 1 */
+#define FSMC_BCR4_CPSIZE_2 0x00040000U /*!<Bit 2 */
+#define FSMC_BCR4_CBURSTRW 0x00080000U /*!<Write burst enable */
+
+/****************** Bit definition for FSMC_BTR1 register ******************/
+#define FSMC_BTR1_ADDSET 0x0000000FU /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FSMC_BTR1_ADDSET_0 0x00000001U /*!<Bit 0 */
+#define FSMC_BTR1_ADDSET_1 0x00000002U /*!<Bit 1 */
+#define FSMC_BTR1_ADDSET_2 0x00000004U /*!<Bit 2 */
+#define FSMC_BTR1_ADDSET_3 0x00000008U /*!<Bit 3 */
+
+#define FSMC_BTR1_ADDHLD 0x000000F0U /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FSMC_BTR1_ADDHLD_0 0x00000010U /*!<Bit 0 */
+#define FSMC_BTR1_ADDHLD_1 0x00000020U /*!<Bit 1 */
+#define FSMC_BTR1_ADDHLD_2 0x00000040U /*!<Bit 2 */
+#define FSMC_BTR1_ADDHLD_3 0x00000080U /*!<Bit 3 */
+
+#define FSMC_BTR1_DATAST 0x0000FF00U /*!<DATAST [7:0] bits (Data-phase duration) */
+#define FSMC_BTR1_DATAST_0 0x00000100U /*!<Bit 0 */
+#define FSMC_BTR1_DATAST_1 0x00000200U /*!<Bit 1 */
+#define FSMC_BTR1_DATAST_2 0x00000400U /*!<Bit 2 */
+#define FSMC_BTR1_DATAST_3 0x00000800U /*!<Bit 3 */
+#define FSMC_BTR1_DATAST_4 0x00001000U /*!<Bit 4 */
+#define FSMC_BTR1_DATAST_5 0x00002000U /*!<Bit 5 */
+#define FSMC_BTR1_DATAST_6 0x00004000U /*!<Bit 6 */
+#define FSMC_BTR1_DATAST_7 0x00008000U /*!<Bit 7 */
+
+#define FSMC_BTR1_BUSTURN 0x000F0000U /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define FSMC_BTR1_BUSTURN_0 0x00010000U /*!<Bit 0 */
+#define FSMC_BTR1_BUSTURN_1 0x00020000U /*!<Bit 1 */
+#define FSMC_BTR1_BUSTURN_2 0x00040000U /*!<Bit 2 */
+#define FSMC_BTR1_BUSTURN_3 0x00080000U /*!<Bit 3 */
+
+#define FSMC_BTR1_CLKDIV 0x00F00000U /*!<CLKDIV[3:0] bits (Clock divide ratio) */
+#define FSMC_BTR1_CLKDIV_0 0x00100000U /*!<Bit 0 */
+#define FSMC_BTR1_CLKDIV_1 0x00200000U /*!<Bit 1 */
+#define FSMC_BTR1_CLKDIV_2 0x00400000U /*!<Bit 2 */
+#define FSMC_BTR1_CLKDIV_3 0x00800000U /*!<Bit 3 */
+
+#define FSMC_BTR1_DATLAT 0x0F000000U /*!<DATLA[3:0] bits (Data latency) */
+#define FSMC_BTR1_DATLAT_0 0x01000000U /*!<Bit 0 */
+#define FSMC_BTR1_DATLAT_1 0x02000000U /*!<Bit 1 */
+#define FSMC_BTR1_DATLAT_2 0x04000000U /*!<Bit 2 */
+#define FSMC_BTR1_DATLAT_3 0x08000000U /*!<Bit 3 */
+
+#define FSMC_BTR1_ACCMOD 0x30000000U /*!<ACCMOD[1:0] bits (Access mode) */
+#define FSMC_BTR1_ACCMOD_0 0x10000000U /*!<Bit 0 */
+#define FSMC_BTR1_ACCMOD_1 0x20000000U /*!<Bit 1 */
+
+/****************** Bit definition for FSMC_BTR2 register *******************/
+#define FSMC_BTR2_ADDSET 0x0000000FU /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FSMC_BTR2_ADDSET_0 0x00000001U /*!<Bit 0 */
+#define FSMC_BTR2_ADDSET_1 0x00000002U /*!<Bit 1 */
+#define FSMC_BTR2_ADDSET_2 0x00000004U /*!<Bit 2 */
+#define FSMC_BTR2_ADDSET_3 0x00000008U /*!<Bit 3 */
+
+#define FSMC_BTR2_ADDHLD 0x000000F0U /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FSMC_BTR2_ADDHLD_0 0x00000010U /*!<Bit 0 */
+#define FSMC_BTR2_ADDHLD_1 0x00000020U /*!<Bit 1 */
+#define FSMC_BTR2_ADDHLD_2 0x00000040U /*!<Bit 2 */
+#define FSMC_BTR2_ADDHLD_3 0x00000080U /*!<Bit 3 */
+
+#define FSMC_BTR2_DATAST 0x0000FF00U /*!<DATAST [7:0] bits (Data-phase duration) */
+#define FSMC_BTR2_DATAST_0 0x00000100U /*!<Bit 0 */
+#define FSMC_BTR2_DATAST_1 0x00000200U /*!<Bit 1 */
+#define FSMC_BTR2_DATAST_2 0x00000400U /*!<Bit 2 */
+#define FSMC_BTR2_DATAST_3 0x00000800U /*!<Bit 3 */
+#define FSMC_BTR2_DATAST_4 0x00001000U /*!<Bit 4 */
+#define FSMC_BTR2_DATAST_5 0x00002000U /*!<Bit 5 */
+#define FSMC_BTR2_DATAST_6 0x00004000U /*!<Bit 6 */
+#define FSMC_BTR2_DATAST_7 0x00008000U /*!<Bit 7 */
+
+#define FSMC_BTR2_BUSTURN 0x000F0000U /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define FSMC_BTR2_BUSTURN_0 0x00010000U /*!<Bit 0 */
+#define FSMC_BTR2_BUSTURN_1 0x00020000U /*!<Bit 1 */
+#define FSMC_BTR2_BUSTURN_2 0x00040000U /*!<Bit 2 */
+#define FSMC_BTR2_BUSTURN_3 0x00080000U /*!<Bit 3 */
+
+#define FSMC_BTR2_CLKDIV 0x00F00000U /*!<CLKDIV[3:0] bits (Clock divide ratio) */
+#define FSMC_BTR2_CLKDIV_0 0x00100000U /*!<Bit 0 */
+#define FSMC_BTR2_CLKDIV_1 0x00200000U /*!<Bit 1 */
+#define FSMC_BTR2_CLKDIV_2 0x00400000U /*!<Bit 2 */
+#define FSMC_BTR2_CLKDIV_3 0x00800000U /*!<Bit 3 */
+
+#define FSMC_BTR2_DATLAT 0x0F000000U /*!<DATLA[3:0] bits (Data latency) */
+#define FSMC_BTR2_DATLAT_0 0x01000000U /*!<Bit 0 */
+#define FSMC_BTR2_DATLAT_1 0x02000000U /*!<Bit 1 */
+#define FSMC_BTR2_DATLAT_2 0x04000000U /*!<Bit 2 */
+#define FSMC_BTR2_DATLAT_3 0x08000000U /*!<Bit 3 */
+
+#define FSMC_BTR2_ACCMOD 0x30000000U /*!<ACCMOD[1:0] bits (Access mode) */
+#define FSMC_BTR2_ACCMOD_0 0x10000000U /*!<Bit 0 */
+#define FSMC_BTR2_ACCMOD_1 0x20000000U /*!<Bit 1 */
+
+/******************* Bit definition for FSMC_BTR3 register *******************/
+#define FSMC_BTR3_ADDSET 0x0000000FU /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FSMC_BTR3_ADDSET_0 0x00000001U /*!<Bit 0 */
+#define FSMC_BTR3_ADDSET_1 0x00000002U /*!<Bit 1 */
+#define FSMC_BTR3_ADDSET_2 0x00000004U /*!<Bit 2 */
+#define FSMC_BTR3_ADDSET_3 0x00000008U /*!<Bit 3 */
+
+#define FSMC_BTR3_ADDHLD 0x000000F0U /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FSMC_BTR3_ADDHLD_0 0x00000010U /*!<Bit 0 */
+#define FSMC_BTR3_ADDHLD_1 0x00000020U /*!<Bit 1 */
+#define FSMC_BTR3_ADDHLD_2 0x00000040U /*!<Bit 2 */
+#define FSMC_BTR3_ADDHLD_3 0x00000080U /*!<Bit 3 */
+
+#define FSMC_BTR3_DATAST 0x0000FF00U /*!<DATAST [7:0] bits (Data-phase duration) */
+#define FSMC_BTR3_DATAST_0 0x00000100U /*!<Bit 0 */
+#define FSMC_BTR3_DATAST_1 0x00000200U /*!<Bit 1 */
+#define FSMC_BTR3_DATAST_2 0x00000400U /*!<Bit 2 */
+#define FSMC_BTR3_DATAST_3 0x00000800U /*!<Bit 3 */
+#define FSMC_BTR3_DATAST_4 0x00001000U /*!<Bit 4 */
+#define FSMC_BTR3_DATAST_5 0x00002000U /*!<Bit 5 */
+#define FSMC_BTR3_DATAST_6 0x00004000U /*!<Bit 6 */
+#define FSMC_BTR3_DATAST_7 0x00008000U /*!<Bit 7 */
+
+#define FSMC_BTR3_BUSTURN 0x000F0000U /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define FSMC_BTR3_BUSTURN_0 0x00010000U /*!<Bit 0 */
+#define FSMC_BTR3_BUSTURN_1 0x00020000U /*!<Bit 1 */
+#define FSMC_BTR3_BUSTURN_2 0x00040000U /*!<Bit 2 */
+#define FSMC_BTR3_BUSTURN_3 0x00080000U /*!<Bit 3 */
+
+#define FSMC_BTR3_CLKDIV 0x00F00000U /*!<CLKDIV[3:0] bits (Clock divide ratio) */
+#define FSMC_BTR3_CLKDIV_0 0x00100000U /*!<Bit 0 */
+#define FSMC_BTR3_CLKDIV_1 0x00200000U /*!<Bit 1 */
+#define FSMC_BTR3_CLKDIV_2 0x00400000U /*!<Bit 2 */
+#define FSMC_BTR3_CLKDIV_3 0x00800000U /*!<Bit 3 */
+
+#define FSMC_BTR3_DATLAT 0x0F000000U /*!<DATLA[3:0] bits (Data latency) */
+#define FSMC_BTR3_DATLAT_0 0x01000000U /*!<Bit 0 */
+#define FSMC_BTR3_DATLAT_1 0x02000000U /*!<Bit 1 */
+#define FSMC_BTR3_DATLAT_2 0x04000000U /*!<Bit 2 */
+#define FSMC_BTR3_DATLAT_3 0x08000000U /*!<Bit 3 */
+
+#define FSMC_BTR3_ACCMOD 0x30000000U /*!<ACCMOD[1:0] bits (Access mode) */
+#define FSMC_BTR3_ACCMOD_0 0x10000000U /*!<Bit 0 */
+#define FSMC_BTR3_ACCMOD_1 0x20000000U /*!<Bit 1 */
+
+/****************** Bit definition for FSMC_BTR4 register *******************/
+#define FSMC_BTR4_ADDSET 0x0000000FU /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FSMC_BTR4_ADDSET_0 0x00000001U /*!<Bit 0 */
+#define FSMC_BTR4_ADDSET_1 0x00000002U /*!<Bit 1 */
+#define FSMC_BTR4_ADDSET_2 0x00000004U /*!<Bit 2 */
+#define FSMC_BTR4_ADDSET_3 0x00000008U /*!<Bit 3 */
+
+#define FSMC_BTR4_ADDHLD 0x000000F0U /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FSMC_BTR4_ADDHLD_0 0x00000010U /*!<Bit 0 */
+#define FSMC_BTR4_ADDHLD_1 0x00000020U /*!<Bit 1 */
+#define FSMC_BTR4_ADDHLD_2 0x00000040U /*!<Bit 2 */
+#define FSMC_BTR4_ADDHLD_3 0x00000080U /*!<Bit 3 */
+
+#define FSMC_BTR4_DATAST 0x0000FF00U /*!<DATAST [7:0] bits (Data-phase duration) */
+#define FSMC_BTR4_DATAST_0 0x00000100U /*!<Bit 0 */
+#define FSMC_BTR4_DATAST_1 0x00000200U /*!<Bit 1 */
+#define FSMC_BTR4_DATAST_2 0x00000400U /*!<Bit 2 */
+#define FSMC_BTR4_DATAST_3 0x00000800U /*!<Bit 3 */
+#define FSMC_BTR4_DATAST_4 0x00001000U /*!<Bit 4 */
+#define FSMC_BTR4_DATAST_5 0x00002000U /*!<Bit 5 */
+#define FSMC_BTR4_DATAST_6 0x00004000U /*!<Bit 6 */
+#define FSMC_BTR4_DATAST_7 0x00008000U /*!<Bit 7 */
+
+#define FSMC_BTR4_BUSTURN 0x000F0000U /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define FSMC_BTR4_BUSTURN_0 0x00010000U /*!<Bit 0 */
+#define FSMC_BTR4_BUSTURN_1 0x00020000U /*!<Bit 1 */
+#define FSMC_BTR4_BUSTURN_2 0x00040000U /*!<Bit 2 */
+#define FSMC_BTR4_BUSTURN_3 0x00080000U /*!<Bit 3 */
+
+#define FSMC_BTR4_CLKDIV 0x00F00000U /*!<CLKDIV[3:0] bits (Clock divide ratio) */
+#define FSMC_BTR4_CLKDIV_0 0x00100000U /*!<Bit 0 */
+#define FSMC_BTR4_CLKDIV_1 0x00200000U /*!<Bit 1 */
+#define FSMC_BTR4_CLKDIV_2 0x00400000U /*!<Bit 2 */
+#define FSMC_BTR4_CLKDIV_3 0x00800000U /*!<Bit 3 */
+
+#define FSMC_BTR4_DATLAT 0x0F000000U /*!<DATLA[3:0] bits (Data latency) */
+#define FSMC_BTR4_DATLAT_0 0x01000000U /*!<Bit 0 */
+#define FSMC_BTR4_DATLAT_1 0x02000000U /*!<Bit 1 */
+#define FSMC_BTR4_DATLAT_2 0x04000000U /*!<Bit 2 */
+#define FSMC_BTR4_DATLAT_3 0x08000000U /*!<Bit 3 */
+
+#define FSMC_BTR4_ACCMOD 0x30000000U /*!<ACCMOD[1:0] bits (Access mode) */
+#define FSMC_BTR4_ACCMOD_0 0x10000000U /*!<Bit 0 */
+#define FSMC_BTR4_ACCMOD_1 0x20000000U /*!<Bit 1 */
+
+/****************** Bit definition for FSMC_BWTR1 register ******************/
+#define FSMC_BWTR1_ADDSET 0x0000000FU /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FSMC_BWTR1_ADDSET_0 0x00000001U /*!<Bit 0 */
+#define FSMC_BWTR1_ADDSET_1 0x00000002U /*!<Bit 1 */
+#define FSMC_BWTR1_ADDSET_2 0x00000004U /*!<Bit 2 */
+#define FSMC_BWTR1_ADDSET_3 0x00000008U /*!<Bit 3 */
+
+#define FSMC_BWTR1_ADDHLD 0x000000F0U /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FSMC_BWTR1_ADDHLD_0 0x00000010U /*!<Bit 0 */
+#define FSMC_BWTR1_ADDHLD_1 0x00000020U /*!<Bit 1 */
+#define FSMC_BWTR1_ADDHLD_2 0x00000040U /*!<Bit 2 */
+#define FSMC_BWTR1_ADDHLD_3 0x00000080U /*!<Bit 3 */
+
+#define FSMC_BWTR1_DATAST 0x0000FF00U /*!<DATAST [7:0] bits (Data-phase duration) */
+#define FSMC_BWTR1_DATAST_0 0x00000100U /*!<Bit 0 */
+#define FSMC_BWTR1_DATAST_1 0x00000200U /*!<Bit 1 */
+#define FSMC_BWTR1_DATAST_2 0x00000400U /*!<Bit 2 */
+#define FSMC_BWTR1_DATAST_3 0x00000800U /*!<Bit 3 */
+#define FSMC_BWTR1_DATAST_4 0x00001000U /*!<Bit 4 */
+#define FSMC_BWTR1_DATAST_5 0x00002000U /*!<Bit 5 */
+#define FSMC_BWTR1_DATAST_6 0x00004000U /*!<Bit 6 */
+#define FSMC_BWTR1_DATAST_7 0x00008000U /*!<Bit 7 */
+
+#define FSMC_BWTR1_BUSTURN 0x000F0000U /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
+#define FSMC_BWTR1_BUSTURN_0 0x00010000U /*!<Bit 0 */
+#define FSMC_BWTR1_BUSTURN_1 0x00020000U /*!<Bit 1 */
+#define FSMC_BWTR1_BUSTURN_2 0x00040000U /*!<Bit 2 */
+#define FSMC_BWTR1_BUSTURN_3 0x00080000U /*!<Bit 3 */
+
+#define FSMC_BWTR1_ACCMOD 0x30000000U /*!<ACCMOD[1:0] bits (Access mode) */
+#define FSMC_BWTR1_ACCMOD_0 0x10000000U /*!<Bit 0 */
+#define FSMC_BWTR1_ACCMOD_1 0x20000000U /*!<Bit 1 */
+
+/****************** Bit definition for FSMC_BWTR2 register ******************/
+#define FSMC_BWTR2_ADDSET 0x0000000FU /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FSMC_BWTR2_ADDSET_0 0x00000001U /*!<Bit 0 */
+#define FSMC_BWTR2_ADDSET_1 0x00000002U /*!<Bit 1 */
+#define FSMC_BWTR2_ADDSET_2 0x00000004U /*!<Bit 2 */
+#define FSMC_BWTR2_ADDSET_3 0x00000008U /*!<Bit 3 */
+
+#define FSMC_BWTR2_ADDHLD 0x000000F0U /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FSMC_BWTR2_ADDHLD_0 0x00000010U /*!<Bit 0 */
+#define FSMC_BWTR2_ADDHLD_1 0x00000020U /*!<Bit 1 */
+#define FSMC_BWTR2_ADDHLD_2 0x00000040U /*!<Bit 2 */
+#define FSMC_BWTR2_ADDHLD_3 0x00000080U /*!<Bit 3 */
+
+#define FSMC_BWTR2_DATAST 0x0000FF00U /*!<DATAST [7:0] bits (Data-phase duration) */
+#define FSMC_BWTR2_DATAST_0 0x00000100U /*!<Bit 0 */
+#define FSMC_BWTR2_DATAST_1 0x00000200U /*!<Bit 1 */
+#define FSMC_BWTR2_DATAST_2 0x00000400U /*!<Bit 2 */
+#define FSMC_BWTR2_DATAST_3 0x00000800U /*!<Bit 3 */
+#define FSMC_BWTR2_DATAST_4 0x00001000U /*!<Bit 4 */
+#define FSMC_BWTR2_DATAST_5 0x00002000U /*!<Bit 5 */
+#define FSMC_BWTR2_DATAST_6 0x00004000U /*!<Bit 6 */
+#define FSMC_BWTR2_DATAST_7 0x00008000U /*!<Bit 7 */
+
+#define FSMC_BWTR2_BUSTURN 0x000F0000U /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
+#define FSMC_BWTR2_BUSTURN_0 0x00010000U /*!<Bit 0 */
+#define FSMC_BWTR2_BUSTURN_1 0x00020000U /*!<Bit 1 */
+#define FSMC_BWTR2_BUSTURN_2 0x00040000U /*!<Bit 2 */
+#define FSMC_BWTR2_BUSTURN_3 0x00080000U /*!<Bit 3 */
+
+#define FSMC_BWTR2_ACCMOD 0x30000000U /*!<ACCMOD[1:0] bits (Access mode) */
+#define FSMC_BWTR2_ACCMOD_0 0x10000000U /*!<Bit 0 */
+#define FSMC_BWTR2_ACCMOD_1 0x20000000U /*!<Bit 1 */
+
+/****************** Bit definition for FSMC_BWTR3 register ******************/
+#define FSMC_BWTR3_ADDSET 0x0000000FU /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FSMC_BWTR3_ADDSET_0 0x00000001U /*!<Bit 0 */
+#define FSMC_BWTR3_ADDSET_1 0x00000002U /*!<Bit 1 */
+#define FSMC_BWTR3_ADDSET_2 0x00000004U /*!<Bit 2 */
+#define FSMC_BWTR3_ADDSET_3 0x00000008U /*!<Bit 3 */
+
+#define FSMC_BWTR3_ADDHLD 0x000000F0U /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FSMC_BWTR3_ADDHLD_0 0x00000010U /*!<Bit 0 */
+#define FSMC_BWTR3_ADDHLD_1 0x00000020U /*!<Bit 1 */
+#define FSMC_BWTR3_ADDHLD_2 0x00000040U /*!<Bit 2 */
+#define FSMC_BWTR3_ADDHLD_3 0x00000080U /*!<Bit 3 */
+
+#define FSMC_BWTR3_DATAST 0x0000FF00U /*!<DATAST [7:0] bits (Data-phase duration) */
+#define FSMC_BWTR3_DATAST_0 0x00000100U /*!<Bit 0 */
+#define FSMC_BWTR3_DATAST_1 0x00000200U /*!<Bit 1 */
+#define FSMC_BWTR3_DATAST_2 0x00000400U /*!<Bit 2 */
+#define FSMC_BWTR3_DATAST_3 0x00000800U /*!<Bit 3 */
+#define FSMC_BWTR3_DATAST_4 0x00001000U /*!<Bit 4 */
+#define FSMC_BWTR3_DATAST_5 0x00002000U /*!<Bit 5 */
+#define FSMC_BWTR3_DATAST_6 0x00004000U /*!<Bit 6 */
+#define FSMC_BWTR3_DATAST_7 0x00008000U /*!<Bit 7 */
+
+#define FSMC_BWTR3_BUSTURN 0x000F0000U /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
+#define FSMC_BWTR3_BUSTURN_0 0x00010000U /*!<Bit 0 */
+#define FSMC_BWTR3_BUSTURN_1 0x00020000U /*!<Bit 1 */
+#define FSMC_BWTR3_BUSTURN_2 0x00040000U /*!<Bit 2 */
+#define FSMC_BWTR3_BUSTURN_3 0x00080000U /*!<Bit 3 */
+
+#define FSMC_BWTR3_ACCMOD 0x30000000U /*!<ACCMOD[1:0] bits (Access mode) */
+#define FSMC_BWTR3_ACCMOD_0 0x10000000U /*!<Bit 0 */
+#define FSMC_BWTR3_ACCMOD_1 0x20000000U /*!<Bit 1 */
+
+/****************** Bit definition for FSMC_BWTR4 register ******************/
+#define FSMC_BWTR4_ADDSET 0x0000000FU /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FSMC_BWTR4_ADDSET_0 0x00000001U /*!<Bit 0 */
+#define FSMC_BWTR4_ADDSET_1 0x00000002U /*!<Bit 1 */
+#define FSMC_BWTR4_ADDSET_2 0x00000004U /*!<Bit 2 */
+#define FSMC_BWTR4_ADDSET_3 0x00000008U /*!<Bit 3 */
+
+#define FSMC_BWTR4_ADDHLD 0x000000F0U /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FSMC_BWTR4_ADDHLD_0 0x00000010U /*!<Bit 0 */
+#define FSMC_BWTR4_ADDHLD_1 0x00000020U /*!<Bit 1 */
+#define FSMC_BWTR4_ADDHLD_2 0x00000040U /*!<Bit 2 */
+#define FSMC_BWTR4_ADDHLD_3 0x00000080U /*!<Bit 3 */
+
+#define FSMC_BWTR4_DATAST 0x0000FF00U /*!<DATAST [7:0] bits (Data-phase duration) */
+#define FSMC_BWTR4_DATAST_0 0x00000100U /*!<Bit 0 */
+#define FSMC_BWTR4_DATAST_1 0x00000200U /*!<Bit 1 */
+#define FSMC_BWTR4_DATAST_2 0x00000400U /*!<Bit 2 */
+#define FSMC_BWTR4_DATAST_3 0x00000800U /*!<Bit 3 */
+#define FSMC_BWTR4_DATAST_4 0x00001000U /*!<Bit 4 */
+#define FSMC_BWTR4_DATAST_5 0x00002000U /*!<Bit 5 */
+#define FSMC_BWTR4_DATAST_6 0x00004000U /*!<Bit 6 */
+#define FSMC_BWTR4_DATAST_7 0x00008000U /*!<Bit 7 */
+
+#define FSMC_BWTR4_BUSTURN 0x000F0000U /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
+#define FSMC_BWTR4_BUSTURN_0 0x00010000U /*!<Bit 0 */
+#define FSMC_BWTR4_BUSTURN_1 0x00020000U /*!<Bit 1 */
+#define FSMC_BWTR4_BUSTURN_2 0x00040000U /*!<Bit 2 */
+#define FSMC_BWTR4_BUSTURN_3 0x00080000U /*!<Bit 3 */
+
+#define FSMC_BWTR4_ACCMOD 0x30000000U /*!<ACCMOD[1:0] bits (Access mode) */
+#define FSMC_BWTR4_ACCMOD_0 0x10000000U /*!<Bit 0 */
+#define FSMC_BWTR4_ACCMOD_1 0x20000000U /*!<Bit 1 */
+
+/****************** Bit definition for FSMC_PCR2 register *******************/
+#define FSMC_PCR2_PWAITEN 0x00000002U /*!<Wait feature enable bit */
+#define FSMC_PCR2_PBKEN 0x00000004U /*!<PC Card/NAND Flash memory bank enable bit */
+#define FSMC_PCR2_PTYP 0x00000008U /*!<Memory type */
+
+#define FSMC_PCR2_PWID 0x00000030U /*!<PWID[1:0] bits (NAND Flash databus width) */
+#define FSMC_PCR2_PWID_0 0x00000010U /*!<Bit 0 */
+#define FSMC_PCR2_PWID_1 0x00000020U /*!<Bit 1 */
+
+#define FSMC_PCR2_ECCEN 0x00000040U /*!<ECC computation logic enable bit */
+
+#define FSMC_PCR2_TCLR 0x00001E00U /*!<TCLR[3:0] bits (CLE to RE delay) */
+#define FSMC_PCR2_TCLR_0 0x00000200U /*!<Bit 0 */
+#define FSMC_PCR2_TCLR_1 0x00000400U /*!<Bit 1 */
+#define FSMC_PCR2_TCLR_2 0x00000800U /*!<Bit 2 */
+#define FSMC_PCR2_TCLR_3 0x00001000U /*!<Bit 3 */
+
+#define FSMC_PCR2_TAR 0x0001E000U /*!<TAR[3:0] bits (ALE to RE delay) */
+#define FSMC_PCR2_TAR_0 0x00002000U /*!<Bit 0 */
+#define FSMC_PCR2_TAR_1 0x00004000U /*!<Bit 1 */
+#define FSMC_PCR2_TAR_2 0x00008000U /*!<Bit 2 */
+#define FSMC_PCR2_TAR_3 0x00010000U /*!<Bit 3 */
+
+#define FSMC_PCR2_ECCPS 0x000E0000U /*!<ECCPS[1:0] bits (ECC page size) */
+#define FSMC_PCR2_ECCPS_0 0x00020000U /*!<Bit 0 */
+#define FSMC_PCR2_ECCPS_1 0x00040000U /*!<Bit 1 */
+#define FSMC_PCR2_ECCPS_2 0x00080000U /*!<Bit 2 */
+
+/****************** Bit definition for FSMC_PCR3 register *******************/
+#define FSMC_PCR3_PWAITEN 0x00000002U /*!<Wait feature enable bit */
+#define FSMC_PCR3_PBKEN 0x00000004U /*!<PC Card/NAND Flash memory bank enable bit */
+#define FSMC_PCR3_PTYP 0x00000008U /*!<Memory type */
+
+#define FSMC_PCR3_PWID 0x00000030U /*!<PWID[1:0] bits (NAND Flash databus width) */
+#define FSMC_PCR3_PWID_0 0x00000010U /*!<Bit 0 */
+#define FSMC_PCR3_PWID_1 0x00000020U /*!<Bit 1 */
+
+#define FSMC_PCR3_ECCEN 0x00000040U /*!<ECC computation logic enable bit */
+
+#define FSMC_PCR3_TCLR 0x00001E00U /*!<TCLR[3:0] bits (CLE to RE delay) */
+#define FSMC_PCR3_TCLR_0 0x00000200U /*!<Bit 0 */
+#define FSMC_PCR3_TCLR_1 0x00000400U /*!<Bit 1 */
+#define FSMC_PCR3_TCLR_2 0x00000800U /*!<Bit 2 */
+#define FSMC_PCR3_TCLR_3 0x00001000U /*!<Bit 3 */
+
+#define FSMC_PCR3_TAR 0x0001E000U /*!<TAR[3:0] bits (ALE to RE delay) */
+#define FSMC_PCR3_TAR_0 0x00002000U /*!<Bit 0 */
+#define FSMC_PCR3_TAR_1 0x00004000U /*!<Bit 1 */
+#define FSMC_PCR3_TAR_2 0x00008000U /*!<Bit 2 */
+#define FSMC_PCR3_TAR_3 0x00010000U /*!<Bit 3 */
+
+#define FSMC_PCR3_ECCPS 0x000E0000U /*!<ECCPS[2:0] bits (ECC page size) */
+#define FSMC_PCR3_ECCPS_0 0x00020000U /*!<Bit 0 */
+#define FSMC_PCR3_ECCPS_1 0x00040000U /*!<Bit 1 */
+#define FSMC_PCR3_ECCPS_2 0x00080000U /*!<Bit 2 */
+
+/****************** Bit definition for FSMC_PCR4 register *******************/
+#define FSMC_PCR4_PWAITEN 0x00000002U /*!<Wait feature enable bit */
+#define FSMC_PCR4_PBKEN 0x00000004U /*!<PC Card/NAND Flash memory bank enable bit */
+#define FSMC_PCR4_PTYP 0x00000008U /*!<Memory type */
+
+#define FSMC_PCR4_PWID 0x00000030U /*!<PWID[1:0] bits (NAND Flash databus width) */
+#define FSMC_PCR4_PWID_0 0x00000010U /*!<Bit 0 */
+#define FSMC_PCR4_PWID_1 0x00000020U /*!<Bit 1 */
+
+#define FSMC_PCR4_ECCEN 0x00000040U /*!<ECC computation logic enable bit */
+
+#define FSMC_PCR4_TCLR 0x00001E00U /*!<TCLR[3:0] bits (CLE to RE delay) */
+#define FSMC_PCR4_TCLR_0 0x00000200U /*!<Bit 0 */
+#define FSMC_PCR4_TCLR_1 0x00000400U /*!<Bit 1 */
+#define FSMC_PCR4_TCLR_2 0x00000800U /*!<Bit 2 */
+#define FSMC_PCR4_TCLR_3 0x00001000U /*!<Bit 3 */
+
+#define FSMC_PCR4_TAR 0x0001E000U /*!<TAR[3:0] bits (ALE to RE delay) */
+#define FSMC_PCR4_TAR_0 0x00002000U /*!<Bit 0 */
+#define FSMC_PCR4_TAR_1 0x00004000U /*!<Bit 1 */
+#define FSMC_PCR4_TAR_2 0x00008000U /*!<Bit 2 */
+#define FSMC_PCR4_TAR_3 0x00010000U /*!<Bit 3 */
+
+#define FSMC_PCR4_ECCPS 0x000E0000U /*!<ECCPS[2:0] bits (ECC page size) */
+#define FSMC_PCR4_ECCPS_0 0x00020000U /*!<Bit 0 */
+#define FSMC_PCR4_ECCPS_1 0x00040000U /*!<Bit 1 */
+#define FSMC_PCR4_ECCPS_2 0x00080000U /*!<Bit 2 */
+
+/******************* Bit definition for FSMC_SR2 register *******************/
+#define FSMC_SR2_IRS 0x01U /*!<Interrupt Rising Edge status */
+#define FSMC_SR2_ILS 0x02U /*!<Interrupt Level status */
+#define FSMC_SR2_IFS 0x04U /*!<Interrupt Falling Edge status */
+#define FSMC_SR2_IREN 0x08U /*!<Interrupt Rising Edge detection Enable bit */
+#define FSMC_SR2_ILEN 0x10U /*!<Interrupt Level detection Enable bit */
+#define FSMC_SR2_IFEN 0x20U /*!<Interrupt Falling Edge detection Enable bit */
+#define FSMC_SR2_FEMPT 0x40U /*!<FIFO empty */
+
+/******************* Bit definition for FSMC_SR3 register *******************/
+#define FSMC_SR3_IRS 0x01U /*!<Interrupt Rising Edge status */
+#define FSMC_SR3_ILS 0x02U /*!<Interrupt Level status */
+#define FSMC_SR3_IFS 0x04U /*!<Interrupt Falling Edge status */
+#define FSMC_SR3_IREN 0x08U /*!<Interrupt Rising Edge detection Enable bit */
+#define FSMC_SR3_ILEN 0x10U /*!<Interrupt Level detection Enable bit */
+#define FSMC_SR3_IFEN 0x20U /*!<Interrupt Falling Edge detection Enable bit */
+#define FSMC_SR3_FEMPT 0x40U /*!<FIFO empty */
+
+/******************* Bit definition for FSMC_SR4 register *******************/
+#define FSMC_SR4_IRS 0x01U /*!<Interrupt Rising Edge status */
+#define FSMC_SR4_ILS 0x02U /*!<Interrupt Level status */
+#define FSMC_SR4_IFS 0x04U /*!<Interrupt Falling Edge status */
+#define FSMC_SR4_IREN 0x08U /*!<Interrupt Rising Edge detection Enable bit */
+#define FSMC_SR4_ILEN 0x10U /*!<Interrupt Level detection Enable bit */
+#define FSMC_SR4_IFEN 0x20U /*!<Interrupt Falling Edge detection Enable bit */
+#define FSMC_SR4_FEMPT 0x40U /*!<FIFO empty */
+
+/****************** Bit definition for FSMC_PMEM2 register ******************/
+#define FSMC_PMEM2_MEMSET2 0x000000FFU /*!<MEMSET2[7:0] bits (Common memory 2 setup time) */
+#define FSMC_PMEM2_MEMSET2_0 0x00000001U /*!<Bit 0 */
+#define FSMC_PMEM2_MEMSET2_1 0x00000002U /*!<Bit 1 */
+#define FSMC_PMEM2_MEMSET2_2 0x00000004U /*!<Bit 2 */
+#define FSMC_PMEM2_MEMSET2_3 0x00000008U /*!<Bit 3 */
+#define FSMC_PMEM2_MEMSET2_4 0x00000010U /*!<Bit 4 */
+#define FSMC_PMEM2_MEMSET2_5 0x00000020U /*!<Bit 5 */
+#define FSMC_PMEM2_MEMSET2_6 0x00000040U /*!<Bit 6 */
+#define FSMC_PMEM2_MEMSET2_7 0x00000080U /*!<Bit 7 */
+
+#define FSMC_PMEM2_MEMWAIT2 0x0000FF00U /*!<MEMWAIT2[7:0] bits (Common memory 2 wait time) */
+#define FSMC_PMEM2_MEMWAIT2_0 0x00000100U /*!<Bit 0 */
+#define FSMC_PMEM2_MEMWAIT2_1 0x00000200U /*!<Bit 1 */
+#define FSMC_PMEM2_MEMWAIT2_2 0x00000400U /*!<Bit 2 */
+#define FSMC_PMEM2_MEMWAIT2_3 0x00000800U /*!<Bit 3 */
+#define FSMC_PMEM2_MEMWAIT2_4 0x00001000U /*!<Bit 4 */
+#define FSMC_PMEM2_MEMWAIT2_5 0x00002000U /*!<Bit 5 */
+#define FSMC_PMEM2_MEMWAIT2_6 0x00004000U /*!<Bit 6 */
+#define FSMC_PMEM2_MEMWAIT2_7 0x00008000U /*!<Bit 7 */
+
+#define FSMC_PMEM2_MEMHOLD2 0x00FF0000U /*!<MEMHOLD2[7:0] bits (Common memory 2 hold time) */
+#define FSMC_PMEM2_MEMHOLD2_0 0x00010000U /*!<Bit 0 */
+#define FSMC_PMEM2_MEMHOLD2_1 0x00020000U /*!<Bit 1 */
+#define FSMC_PMEM2_MEMHOLD2_2 0x00040000U /*!<Bit 2 */
+#define FSMC_PMEM2_MEMHOLD2_3 0x00080000U /*!<Bit 3 */
+#define FSMC_PMEM2_MEMHOLD2_4 0x00100000U /*!<Bit 4 */
+#define FSMC_PMEM2_MEMHOLD2_5 0x00200000U /*!<Bit 5 */
+#define FSMC_PMEM2_MEMHOLD2_6 0x00400000U /*!<Bit 6 */
+#define FSMC_PMEM2_MEMHOLD2_7 0x00800000U /*!<Bit 7 */
+
+#define FSMC_PMEM2_MEMHIZ2 0xFF000000U /*!<MEMHIZ2[7:0] bits (Common memory 2 databus HiZ time) */
+#define FSMC_PMEM2_MEMHIZ2_0 0x01000000U /*!<Bit 0 */
+#define FSMC_PMEM2_MEMHIZ2_1 0x02000000U /*!<Bit 1 */
+#define FSMC_PMEM2_MEMHIZ2_2 0x04000000U /*!<Bit 2 */
+#define FSMC_PMEM2_MEMHIZ2_3 0x08000000U /*!<Bit 3 */
+#define FSMC_PMEM2_MEMHIZ2_4 0x10000000U /*!<Bit 4 */
+#define FSMC_PMEM2_MEMHIZ2_5 0x20000000U /*!<Bit 5 */
+#define FSMC_PMEM2_MEMHIZ2_6 0x40000000U /*!<Bit 6 */
+#define FSMC_PMEM2_MEMHIZ2_7 0x80000000U /*!<Bit 7 */
+
+/****************** Bit definition for FSMC_PMEM3 register ******************/
+#define FSMC_PMEM3_MEMSET3 0x000000FFU /*!<MEMSET3[7:0] bits (Common memory 3 setup time) */
+#define FSMC_PMEM3_MEMSET3_0 0x00000001U /*!<Bit 0 */
+#define FSMC_PMEM3_MEMSET3_1 0x00000002U /*!<Bit 1 */
+#define FSMC_PMEM3_MEMSET3_2 0x00000004U /*!<Bit 2 */
+#define FSMC_PMEM3_MEMSET3_3 0x00000008U /*!<Bit 3 */
+#define FSMC_PMEM3_MEMSET3_4 0x00000010U /*!<Bit 4 */
+#define FSMC_PMEM3_MEMSET3_5 0x00000020U /*!<Bit 5 */
+#define FSMC_PMEM3_MEMSET3_6 0x00000040U /*!<Bit 6 */
+#define FSMC_PMEM3_MEMSET3_7 0x00000080U /*!<Bit 7 */
+
+#define FSMC_PMEM3_MEMWAIT3 0x0000FF00U /*!<MEMWAIT3[7:0] bits (Common memory 3 wait time) */
+#define FSMC_PMEM3_MEMWAIT3_0 0x00000100U /*!<Bit 0 */
+#define FSMC_PMEM3_MEMWAIT3_1 0x00000200U /*!<Bit 1 */
+#define FSMC_PMEM3_MEMWAIT3_2 0x00000400U /*!<Bit 2 */
+#define FSMC_PMEM3_MEMWAIT3_3 0x00000800U /*!<Bit 3 */
+#define FSMC_PMEM3_MEMWAIT3_4 0x00001000U /*!<Bit 4 */
+#define FSMC_PMEM3_MEMWAIT3_5 0x00002000U /*!<Bit 5 */
+#define FSMC_PMEM3_MEMWAIT3_6 0x00004000U /*!<Bit 6 */
+#define FSMC_PMEM3_MEMWAIT3_7 0x00008000U /*!<Bit 7 */
+
+#define FSMC_PMEM3_MEMHOLD3 0x00FF0000U /*!<MEMHOLD3[7:0] bits (Common memory 3 hold time) */
+#define FSMC_PMEM3_MEMHOLD3_0 0x00010000U /*!<Bit 0 */
+#define FSMC_PMEM3_MEMHOLD3_1 0x00020000U /*!<Bit 1 */
+#define FSMC_PMEM3_MEMHOLD3_2 0x00040000U /*!<Bit 2 */
+#define FSMC_PMEM3_MEMHOLD3_3 0x00080000U /*!<Bit 3 */
+#define FSMC_PMEM3_MEMHOLD3_4 0x00100000U /*!<Bit 4 */
+#define FSMC_PMEM3_MEMHOLD3_5 0x00200000U /*!<Bit 5 */
+#define FSMC_PMEM3_MEMHOLD3_6 0x00400000U /*!<Bit 6 */
+#define FSMC_PMEM3_MEMHOLD3_7 0x00800000U /*!<Bit 7 */
+
+#define FSMC_PMEM3_MEMHIZ3 0xFF000000U /*!<MEMHIZ3[7:0] bits (Common memory 3 databus HiZ time) */
+#define FSMC_PMEM3_MEMHIZ3_0 0x01000000U /*!<Bit 0 */
+#define FSMC_PMEM3_MEMHIZ3_1 0x02000000U /*!<Bit 1 */
+#define FSMC_PMEM3_MEMHIZ3_2 0x04000000U /*!<Bit 2 */
+#define FSMC_PMEM3_MEMHIZ3_3 0x08000000U /*!<Bit 3 */
+#define FSMC_PMEM3_MEMHIZ3_4 0x10000000U /*!<Bit 4 */
+#define FSMC_PMEM3_MEMHIZ3_5 0x20000000U /*!<Bit 5 */
+#define FSMC_PMEM3_MEMHIZ3_6 0x40000000U /*!<Bit 6 */
+#define FSMC_PMEM3_MEMHIZ3_7 0x80000000U /*!<Bit 7 */
+
+/****************** Bit definition for FSMC_PMEM4 register ******************/
+#define FSMC_PMEM4_MEMSET4 0x000000FFU /*!<MEMSET4[7:0] bits (Common memory 4 setup time) */
+#define FSMC_PMEM4_MEMSET4_0 0x00000001U /*!<Bit 0 */
+#define FSMC_PMEM4_MEMSET4_1 0x00000002U /*!<Bit 1 */
+#define FSMC_PMEM4_MEMSET4_2 0x00000004U /*!<Bit 2 */
+#define FSMC_PMEM4_MEMSET4_3 0x00000008U /*!<Bit 3 */
+#define FSMC_PMEM4_MEMSET4_4 0x00000010U /*!<Bit 4 */
+#define FSMC_PMEM4_MEMSET4_5 0x00000020U /*!<Bit 5 */
+#define FSMC_PMEM4_MEMSET4_6 0x00000040U /*!<Bit 6 */
+#define FSMC_PMEM4_MEMSET4_7 0x00000080U /*!<Bit 7 */
+
+#define FSMC_PMEM4_MEMWAIT4 0x0000FF00U /*!<MEMWAIT4[7:0] bits (Common memory 4 wait time) */
+#define FSMC_PMEM4_MEMWAIT4_0 0x00000100U /*!<Bit 0 */
+#define FSMC_PMEM4_MEMWAIT4_1 0x00000200U /*!<Bit 1 */
+#define FSMC_PMEM4_MEMWAIT4_2 0x00000400U /*!<Bit 2 */
+#define FSMC_PMEM4_MEMWAIT4_3 0x00000800U /*!<Bit 3 */
+#define FSMC_PMEM4_MEMWAIT4_4 0x00001000U /*!<Bit 4 */
+#define FSMC_PMEM4_MEMWAIT4_5 0x00002000U /*!<Bit 5 */
+#define FSMC_PMEM4_MEMWAIT4_6 0x00004000U /*!<Bit 6 */
+#define FSMC_PMEM4_MEMWAIT4_7 0x00008000U /*!<Bit 7 */
+
+#define FSMC_PMEM4_MEMHOLD4 0x00FF0000U /*!<MEMHOLD4[7:0] bits (Common memory 4 hold time) */
+#define FSMC_PMEM4_MEMHOLD4_0 0x00010000U /*!<Bit 0 */
+#define FSMC_PMEM4_MEMHOLD4_1 0x00020000U /*!<Bit 1 */
+#define FSMC_PMEM4_MEMHOLD4_2 0x00040000U /*!<Bit 2 */
+#define FSMC_PMEM4_MEMHOLD4_3 0x00080000U /*!<Bit 3 */
+#define FSMC_PMEM4_MEMHOLD4_4 0x00100000U /*!<Bit 4 */
+#define FSMC_PMEM4_MEMHOLD4_5 0x00200000U /*!<Bit 5 */
+#define FSMC_PMEM4_MEMHOLD4_6 0x00400000U /*!<Bit 6 */
+#define FSMC_PMEM4_MEMHOLD4_7 0x00800000U /*!<Bit 7 */
+
+#define FSMC_PMEM4_MEMHIZ4 0xFF000000U /*!<MEMHIZ4[7:0] bits (Common memory 4 databus HiZ time) */
+#define FSMC_PMEM4_MEMHIZ4_0 0x01000000U /*!<Bit 0 */
+#define FSMC_PMEM4_MEMHIZ4_1 0x02000000U /*!<Bit 1 */
+#define FSMC_PMEM4_MEMHIZ4_2 0x04000000U /*!<Bit 2 */
+#define FSMC_PMEM4_MEMHIZ4_3 0x08000000U /*!<Bit 3 */
+#define FSMC_PMEM4_MEMHIZ4_4 0x10000000U /*!<Bit 4 */
+#define FSMC_PMEM4_MEMHIZ4_5 0x20000000U /*!<Bit 5 */
+#define FSMC_PMEM4_MEMHIZ4_6 0x40000000U /*!<Bit 6 */
+#define FSMC_PMEM4_MEMHIZ4_7 0x80000000U /*!<Bit 7 */
+
+/****************** Bit definition for FSMC_PATT2 register ******************/
+#define FSMC_PATT2_ATTSET2 0x000000FFU /*!<ATTSET2[7:0] bits (Attribute memory 2 setup time) */
+#define FSMC_PATT2_ATTSET2_0 0x00000001U /*!<Bit 0 */
+#define FSMC_PATT2_ATTSET2_1 0x00000002U /*!<Bit 1 */
+#define FSMC_PATT2_ATTSET2_2 0x00000004U /*!<Bit 2 */
+#define FSMC_PATT2_ATTSET2_3 0x00000008U /*!<Bit 3 */
+#define FSMC_PATT2_ATTSET2_4 0x00000010U /*!<Bit 4 */
+#define FSMC_PATT2_ATTSET2_5 0x00000020U /*!<Bit 5 */
+#define FSMC_PATT2_ATTSET2_6 0x00000040U /*!<Bit 6 */
+#define FSMC_PATT2_ATTSET2_7 0x00000080U /*!<Bit 7 */
+
+#define FSMC_PATT2_ATTWAIT2 0x0000FF00U /*!<ATTWAIT2[7:0] bits (Attribute memory 2 wait time) */
+#define FSMC_PATT2_ATTWAIT2_0 0x00000100U /*!<Bit 0 */
+#define FSMC_PATT2_ATTWAIT2_1 0x00000200U /*!<Bit 1 */
+#define FSMC_PATT2_ATTWAIT2_2 0x00000400U /*!<Bit 2 */
+#define FSMC_PATT2_ATTWAIT2_3 0x00000800U /*!<Bit 3 */
+#define FSMC_PATT2_ATTWAIT2_4 0x00001000U /*!<Bit 4 */
+#define FSMC_PATT2_ATTWAIT2_5 0x00002000U /*!<Bit 5 */
+#define FSMC_PATT2_ATTWAIT2_6 0x00004000U /*!<Bit 6 */
+#define FSMC_PATT2_ATTWAIT2_7 0x00008000U /*!<Bit 7 */
+
+#define FSMC_PATT2_ATTHOLD2 0x00FF0000U /*!<ATTHOLD2[7:0] bits (Attribute memory 2 hold time) */
+#define FSMC_PATT2_ATTHOLD2_0 0x00010000U /*!<Bit 0 */
+#define FSMC_PATT2_ATTHOLD2_1 0x00020000U /*!<Bit 1 */
+#define FSMC_PATT2_ATTHOLD2_2 0x00040000U /*!<Bit 2 */
+#define FSMC_PATT2_ATTHOLD2_3 0x00080000U /*!<Bit 3 */
+#define FSMC_PATT2_ATTHOLD2_4 0x00100000U /*!<Bit 4 */
+#define FSMC_PATT2_ATTHOLD2_5 0x00200000U /*!<Bit 5 */
+#define FSMC_PATT2_ATTHOLD2_6 0x00400000U /*!<Bit 6 */
+#define FSMC_PATT2_ATTHOLD2_7 0x00800000U /*!<Bit 7 */
+
+#define FSMC_PATT2_ATTHIZ2 0xFF000000U /*!<ATTHIZ2[7:0] bits (Attribute memory 2 databus HiZ time) */
+#define FSMC_PATT2_ATTHIZ2_0 0x01000000U /*!<Bit 0 */
+#define FSMC_PATT2_ATTHIZ2_1 0x02000000U /*!<Bit 1 */
+#define FSMC_PATT2_ATTHIZ2_2 0x04000000U /*!<Bit 2 */
+#define FSMC_PATT2_ATTHIZ2_3 0x08000000U /*!<Bit 3 */
+#define FSMC_PATT2_ATTHIZ2_4 0x10000000U /*!<Bit 4 */
+#define FSMC_PATT2_ATTHIZ2_5 0x20000000U /*!<Bit 5 */
+#define FSMC_PATT2_ATTHIZ2_6 0x40000000U /*!<Bit 6 */
+#define FSMC_PATT2_ATTHIZ2_7 0x80000000U /*!<Bit 7 */
+
+/****************** Bit definition for FSMC_PATT3 register ******************/
+#define FSMC_PATT3_ATTSET3 0x000000FFU /*!<ATTSET3[7:0] bits (Attribute memory 3 setup time) */
+#define FSMC_PATT3_ATTSET3_0 0x00000001U /*!<Bit 0 */
+#define FSMC_PATT3_ATTSET3_1 0x00000002U /*!<Bit 1 */
+#define FSMC_PATT3_ATTSET3_2 0x00000004U /*!<Bit 2 */
+#define FSMC_PATT3_ATTSET3_3 0x00000008U /*!<Bit 3 */
+#define FSMC_PATT3_ATTSET3_4 0x00000010U /*!<Bit 4 */
+#define FSMC_PATT3_ATTSET3_5 0x00000020U /*!<Bit 5 */
+#define FSMC_PATT3_ATTSET3_6 0x00000040U /*!<Bit 6 */
+#define FSMC_PATT3_ATTSET3_7 0x00000080U /*!<Bit 7 */
+
+#define FSMC_PATT3_ATTWAIT3 0x0000FF00U /*!<ATTWAIT3[7:0] bits (Attribute memory 3 wait time) */
+#define FSMC_PATT3_ATTWAIT3_0 0x00000100U /*!<Bit 0 */
+#define FSMC_PATT3_ATTWAIT3_1 0x00000200U /*!<Bit 1 */
+#define FSMC_PATT3_ATTWAIT3_2 0x00000400U /*!<Bit 2 */
+#define FSMC_PATT3_ATTWAIT3_3 0x00000800U /*!<Bit 3 */
+#define FSMC_PATT3_ATTWAIT3_4 0x00001000U /*!<Bit 4 */
+#define FSMC_PATT3_ATTWAIT3_5 0x00002000U /*!<Bit 5 */
+#define FSMC_PATT3_ATTWAIT3_6 0x00004000U /*!<Bit 6 */
+#define FSMC_PATT3_ATTWAIT3_7 0x00008000U /*!<Bit 7 */
+
+#define FSMC_PATT3_ATTHOLD3 0x00FF0000U /*!<ATTHOLD3[7:0] bits (Attribute memory 3 hold time) */
+#define FSMC_PATT3_ATTHOLD3_0 0x00010000U /*!<Bit 0 */
+#define FSMC_PATT3_ATTHOLD3_1 0x00020000U /*!<Bit 1 */
+#define FSMC_PATT3_ATTHOLD3_2 0x00040000U /*!<Bit 2 */
+#define FSMC_PATT3_ATTHOLD3_3 0x00080000U /*!<Bit 3 */
+#define FSMC_PATT3_ATTHOLD3_4 0x00100000U /*!<Bit 4 */
+#define FSMC_PATT3_ATTHOLD3_5 0x00200000U /*!<Bit 5 */
+#define FSMC_PATT3_ATTHOLD3_6 0x00400000U /*!<Bit 6 */
+#define FSMC_PATT3_ATTHOLD3_7 0x00800000U /*!<Bit 7 */
+
+#define FSMC_PATT3_ATTHIZ3 0xFF000000U /*!<ATTHIZ3[7:0] bits (Attribute memory 3 databus HiZ time) */
+#define FSMC_PATT3_ATTHIZ3_0 0x01000000U /*!<Bit 0 */
+#define FSMC_PATT3_ATTHIZ3_1 0x02000000U /*!<Bit 1 */
+#define FSMC_PATT3_ATTHIZ3_2 0x04000000U /*!<Bit 2 */
+#define FSMC_PATT3_ATTHIZ3_3 0x08000000U /*!<Bit 3 */
+#define FSMC_PATT3_ATTHIZ3_4 0x10000000U /*!<Bit 4 */
+#define FSMC_PATT3_ATTHIZ3_5 0x20000000U /*!<Bit 5 */
+#define FSMC_PATT3_ATTHIZ3_6 0x40000000U /*!<Bit 6 */
+#define FSMC_PATT3_ATTHIZ3_7 0x80000000U /*!<Bit 7 */
+
+/****************** Bit definition for FSMC_PATT4 register ******************/
+#define FSMC_PATT4_ATTSET4 0x000000FFU /*!<ATTSET4[7:0] bits (Attribute memory 4 setup time) */
+#define FSMC_PATT4_ATTSET4_0 0x00000001U /*!<Bit 0 */
+#define FSMC_PATT4_ATTSET4_1 0x00000002U /*!<Bit 1 */
+#define FSMC_PATT4_ATTSET4_2 0x00000004U /*!<Bit 2 */
+#define FSMC_PATT4_ATTSET4_3 0x00000008U /*!<Bit 3 */
+#define FSMC_PATT4_ATTSET4_4 0x00000010U /*!<Bit 4 */
+#define FSMC_PATT4_ATTSET4_5 0x00000020U /*!<Bit 5 */
+#define FSMC_PATT4_ATTSET4_6 0x00000040U /*!<Bit 6 */
+#define FSMC_PATT4_ATTSET4_7 0x00000080U /*!<Bit 7 */
+
+#define FSMC_PATT4_ATTWAIT4 0x0000FF00U /*!<ATTWAIT4[7:0] bits (Attribute memory 4 wait time) */
+#define FSMC_PATT4_ATTWAIT4_0 0x00000100U /*!<Bit 0 */
+#define FSMC_PATT4_ATTWAIT4_1 0x00000200U /*!<Bit 1 */
+#define FSMC_PATT4_ATTWAIT4_2 0x00000400U /*!<Bit 2 */
+#define FSMC_PATT4_ATTWAIT4_3 0x00000800U /*!<Bit 3 */
+#define FSMC_PATT4_ATTWAIT4_4 0x00001000U /*!<Bit 4 */
+#define FSMC_PATT4_ATTWAIT4_5 0x00002000U /*!<Bit 5 */
+#define FSMC_PATT4_ATTWAIT4_6 0x00004000U /*!<Bit 6 */
+#define FSMC_PATT4_ATTWAIT4_7 0x00008000U /*!<Bit 7 */
+
+#define FSMC_PATT4_ATTHOLD4 0x00FF0000U /*!<ATTHOLD4[7:0] bits (Attribute memory 4 hold time) */
+#define FSMC_PATT4_ATTHOLD4_0 0x00010000U /*!<Bit 0 */
+#define FSMC_PATT4_ATTHOLD4_1 0x00020000U /*!<Bit 1 */
+#define FSMC_PATT4_ATTHOLD4_2 0x00040000U /*!<Bit 2 */
+#define FSMC_PATT4_ATTHOLD4_3 0x00080000U /*!<Bit 3 */
+#define FSMC_PATT4_ATTHOLD4_4 0x00100000U /*!<Bit 4 */
+#define FSMC_PATT4_ATTHOLD4_5 0x00200000U /*!<Bit 5 */
+#define FSMC_PATT4_ATTHOLD4_6 0x00400000U /*!<Bit 6 */
+#define FSMC_PATT4_ATTHOLD4_7 0x00800000U /*!<Bit 7 */
+
+#define FSMC_PATT4_ATTHIZ4 0xFF000000U /*!<ATTHIZ4[7:0] bits (Attribute memory 4 databus HiZ time) */
+#define FSMC_PATT4_ATTHIZ4_0 0x01000000U /*!<Bit 0 */
+#define FSMC_PATT4_ATTHIZ4_1 0x02000000U /*!<Bit 1 */
+#define FSMC_PATT4_ATTHIZ4_2 0x04000000U /*!<Bit 2 */
+#define FSMC_PATT4_ATTHIZ4_3 0x08000000U /*!<Bit 3 */
+#define FSMC_PATT4_ATTHIZ4_4 0x10000000U /*!<Bit 4 */
+#define FSMC_PATT4_ATTHIZ4_5 0x20000000U /*!<Bit 5 */
+#define FSMC_PATT4_ATTHIZ4_6 0x40000000U /*!<Bit 6 */
+#define FSMC_PATT4_ATTHIZ4_7 0x80000000U /*!<Bit 7 */
+
+/****************** Bit definition for FSMC_PIO4 register *******************/
+#define FSMC_PIO4_IOSET4 0x000000FFU /*!<IOSET4[7:0] bits (I/O 4 setup time) */
+#define FSMC_PIO4_IOSET4_0 0x00000001U /*!<Bit 0 */
+#define FSMC_PIO4_IOSET4_1 0x00000002U /*!<Bit 1 */
+#define FSMC_PIO4_IOSET4_2 0x00000004U /*!<Bit 2 */
+#define FSMC_PIO4_IOSET4_3 0x00000008U /*!<Bit 3 */
+#define FSMC_PIO4_IOSET4_4 0x00000010U /*!<Bit 4 */
+#define FSMC_PIO4_IOSET4_5 0x00000020U /*!<Bit 5 */
+#define FSMC_PIO4_IOSET4_6 0x00000040U /*!<Bit 6 */
+#define FSMC_PIO4_IOSET4_7 0x00000080U /*!<Bit 7 */
+
+#define FSMC_PIO4_IOWAIT4 0x0000FF00U /*!<IOWAIT4[7:0] bits (I/O 4 wait time) */
+#define FSMC_PIO4_IOWAIT4_0 0x00000100U /*!<Bit 0 */
+#define FSMC_PIO4_IOWAIT4_1 0x00000200U /*!<Bit 1 */
+#define FSMC_PIO4_IOWAIT4_2 0x00000400U /*!<Bit 2 */
+#define FSMC_PIO4_IOWAIT4_3 0x00000800U /*!<Bit 3 */
+#define FSMC_PIO4_IOWAIT4_4 0x00001000U /*!<Bit 4 */
+#define FSMC_PIO4_IOWAIT4_5 0x00002000U /*!<Bit 5 */
+#define FSMC_PIO4_IOWAIT4_6 0x00004000U /*!<Bit 6 */
+#define FSMC_PIO4_IOWAIT4_7 0x00008000U /*!<Bit 7 */
+
+#define FSMC_PIO4_IOHOLD4 0x00FF0000U /*!<IOHOLD4[7:0] bits (I/O 4 hold time) */
+#define FSMC_PIO4_IOHOLD4_0 0x00010000U /*!<Bit 0 */
+#define FSMC_PIO4_IOHOLD4_1 0x00020000U /*!<Bit 1 */
+#define FSMC_PIO4_IOHOLD4_2 0x00040000U /*!<Bit 2 */
+#define FSMC_PIO4_IOHOLD4_3 0x00080000U /*!<Bit 3 */
+#define FSMC_PIO4_IOHOLD4_4 0x00100000U /*!<Bit 4 */
+#define FSMC_PIO4_IOHOLD4_5 0x00200000U /*!<Bit 5 */
+#define FSMC_PIO4_IOHOLD4_6 0x00400000U /*!<Bit 6 */
+#define FSMC_PIO4_IOHOLD4_7 0x00800000U /*!<Bit 7 */
+
+#define FSMC_PIO4_IOHIZ4 0xFF000000U /*!<IOHIZ4[7:0] bits (I/O 4 databus HiZ time) */
+#define FSMC_PIO4_IOHIZ4_0 0x01000000U /*!<Bit 0 */
+#define FSMC_PIO4_IOHIZ4_1 0x02000000U /*!<Bit 1 */
+#define FSMC_PIO4_IOHIZ4_2 0x04000000U /*!<Bit 2 */
+#define FSMC_PIO4_IOHIZ4_3 0x08000000U /*!<Bit 3 */
+#define FSMC_PIO4_IOHIZ4_4 0x10000000U /*!<Bit 4 */
+#define FSMC_PIO4_IOHIZ4_5 0x20000000U /*!<Bit 5 */
+#define FSMC_PIO4_IOHIZ4_6 0x40000000U /*!<Bit 6 */
+#define FSMC_PIO4_IOHIZ4_7 0x80000000U /*!<Bit 7 */
+
+/****************** Bit definition for FSMC_ECCR2 register ******************/
+#define FSMC_ECCR2_ECC2 0xFFFFFFFFU /*!<ECC result */
+
+/****************** Bit definition for FSMC_ECCR3 register ******************/
+#define FSMC_ECCR3_ECC3 0xFFFFFFFFU /*!<ECC result */
+
+/******************************************************************************/
+/* */
+/* General Purpose I/O */
+/* */
+/******************************************************************************/
+/****************** Bits definition for GPIO_MODER register *****************/
+#define GPIO_MODER_MODER0 0x00000003U
+#define GPIO_MODER_MODER0_0 0x00000001U
+#define GPIO_MODER_MODER0_1 0x00000002U
+
+#define GPIO_MODER_MODER1 0x0000000CU
+#define GPIO_MODER_MODER1_0 0x00000004U
+#define GPIO_MODER_MODER1_1 0x00000008U
+
+#define GPIO_MODER_MODER2 0x00000030U
+#define GPIO_MODER_MODER2_0 0x00000010U
+#define GPIO_MODER_MODER2_1 0x00000020U
+
+#define GPIO_MODER_MODER3 0x000000C0U
+#define GPIO_MODER_MODER3_0 0x00000040U
+#define GPIO_MODER_MODER3_1 0x00000080U
+
+#define GPIO_MODER_MODER4 0x00000300U
+#define GPIO_MODER_MODER4_0 0x00000100U
+#define GPIO_MODER_MODER4_1 0x00000200U
+
+#define GPIO_MODER_MODER5 0x00000C00U
+#define GPIO_MODER_MODER5_0 0x00000400U
+#define GPIO_MODER_MODER5_1 0x00000800U
+
+#define GPIO_MODER_MODER6 0x00003000U
+#define GPIO_MODER_MODER6_0 0x00001000U
+#define GPIO_MODER_MODER6_1 0x00002000U
+
+#define GPIO_MODER_MODER7 0x0000C000U
+#define GPIO_MODER_MODER7_0 0x00004000U
+#define GPIO_MODER_MODER7_1 0x00008000U
+
+#define GPIO_MODER_MODER8 0x00030000U
+#define GPIO_MODER_MODER8_0 0x00010000U
+#define GPIO_MODER_MODER8_1 0x00020000U
+
+#define GPIO_MODER_MODER9 0x000C0000U
+#define GPIO_MODER_MODER9_0 0x00040000U
+#define GPIO_MODER_MODER9_1 0x00080000U
+
+#define GPIO_MODER_MODER10 0x00300000U
+#define GPIO_MODER_MODER10_0 0x00100000U
+#define GPIO_MODER_MODER10_1 0x00200000U
+
+#define GPIO_MODER_MODER11 0x00C00000U
+#define GPIO_MODER_MODER11_0 0x00400000U
+#define GPIO_MODER_MODER11_1 0x00800000U
+
+#define GPIO_MODER_MODER12 0x03000000U
+#define GPIO_MODER_MODER12_0 0x01000000U
+#define GPIO_MODER_MODER12_1 0x02000000U
+
+#define GPIO_MODER_MODER13 0x0C000000U
+#define GPIO_MODER_MODER13_0 0x04000000U
+#define GPIO_MODER_MODER13_1 0x08000000U
+
+#define GPIO_MODER_MODER14 0x30000000U
+#define GPIO_MODER_MODER14_0 0x10000000U
+#define GPIO_MODER_MODER14_1 0x20000000U
+
+#define GPIO_MODER_MODER15 0xC0000000U
+#define GPIO_MODER_MODER15_0 0x40000000U
+#define GPIO_MODER_MODER15_1 0x80000000U
+
+/****************** Bits definition for GPIO_OTYPER register ****************/
+#define GPIO_OTYPER_OT_0 0x00000001U
+#define GPIO_OTYPER_OT_1 0x00000002U
+#define GPIO_OTYPER_OT_2 0x00000004U
+#define GPIO_OTYPER_OT_3 0x00000008U
+#define GPIO_OTYPER_OT_4 0x00000010U
+#define GPIO_OTYPER_OT_5 0x00000020U
+#define GPIO_OTYPER_OT_6 0x00000040U
+#define GPIO_OTYPER_OT_7 0x00000080U
+#define GPIO_OTYPER_OT_8 0x00000100U
+#define GPIO_OTYPER_OT_9 0x00000200U
+#define GPIO_OTYPER_OT_10 0x00000400U
+#define GPIO_OTYPER_OT_11 0x00000800U
+#define GPIO_OTYPER_OT_12 0x00001000U
+#define GPIO_OTYPER_OT_13 0x00002000U
+#define GPIO_OTYPER_OT_14 0x00004000U
+#define GPIO_OTYPER_OT_15 0x00008000U
+
+/****************** Bits definition for GPIO_OSPEEDR register ***************/
+#define GPIO_OSPEEDER_OSPEEDR0 0x00000003U
+#define GPIO_OSPEEDER_OSPEEDR0_0 0x00000001U
+#define GPIO_OSPEEDER_OSPEEDR0_1 0x00000002U
+
+#define GPIO_OSPEEDER_OSPEEDR1 0x0000000CU
+#define GPIO_OSPEEDER_OSPEEDR1_0 0x00000004U
+#define GPIO_OSPEEDER_OSPEEDR1_1 0x00000008U
+
+#define GPIO_OSPEEDER_OSPEEDR2 0x00000030U
+#define GPIO_OSPEEDER_OSPEEDR2_0 0x00000010U
+#define GPIO_OSPEEDER_OSPEEDR2_1 0x00000020U
+
+#define GPIO_OSPEEDER_OSPEEDR3 0x000000C0U
+#define GPIO_OSPEEDER_OSPEEDR3_0 0x00000040U
+#define GPIO_OSPEEDER_OSPEEDR3_1 0x00000080U
+
+#define GPIO_OSPEEDER_OSPEEDR4 0x00000300U
+#define GPIO_OSPEEDER_OSPEEDR4_0 0x00000100U
+#define GPIO_OSPEEDER_OSPEEDR4_1 0x00000200U
+
+#define GPIO_OSPEEDER_OSPEEDR5 0x00000C00U
+#define GPIO_OSPEEDER_OSPEEDR5_0 0x00000400U
+#define GPIO_OSPEEDER_OSPEEDR5_1 0x00000800U
+
+#define GPIO_OSPEEDER_OSPEEDR6 0x00003000U
+#define GPIO_OSPEEDER_OSPEEDR6_0 0x00001000U
+#define GPIO_OSPEEDER_OSPEEDR6_1 0x00002000U
+
+#define GPIO_OSPEEDER_OSPEEDR7 0x0000C000U
+#define GPIO_OSPEEDER_OSPEEDR7_0 0x00004000U
+#define GPIO_OSPEEDER_OSPEEDR7_1 0x00008000U
+
+#define GPIO_OSPEEDER_OSPEEDR8 0x00030000U
+#define GPIO_OSPEEDER_OSPEEDR8_0 0x00010000U
+#define GPIO_OSPEEDER_OSPEEDR8_1 0x00020000U
+
+#define GPIO_OSPEEDER_OSPEEDR9 0x000C0000U
+#define GPIO_OSPEEDER_OSPEEDR9_0 0x00040000U
+#define GPIO_OSPEEDER_OSPEEDR9_1 0x00080000U
+
+#define GPIO_OSPEEDER_OSPEEDR10 0x00300000U
+#define GPIO_OSPEEDER_OSPEEDR10_0 0x00100000U
+#define GPIO_OSPEEDER_OSPEEDR10_1 0x00200000U
+
+#define GPIO_OSPEEDER_OSPEEDR11 0x00C00000U
+#define GPIO_OSPEEDER_OSPEEDR11_0 0x00400000U
+#define GPIO_OSPEEDER_OSPEEDR11_1 0x00800000U
+
+#define GPIO_OSPEEDER_OSPEEDR12 0x03000000U
+#define GPIO_OSPEEDER_OSPEEDR12_0 0x01000000U
+#define GPIO_OSPEEDER_OSPEEDR12_1 0x02000000U
+
+#define GPIO_OSPEEDER_OSPEEDR13 0x0C000000U
+#define GPIO_OSPEEDER_OSPEEDR13_0 0x04000000U
+#define GPIO_OSPEEDER_OSPEEDR13_1 0x08000000U
+
+#define GPIO_OSPEEDER_OSPEEDR14 0x30000000U
+#define GPIO_OSPEEDER_OSPEEDR14_0 0x10000000U
+#define GPIO_OSPEEDER_OSPEEDR14_1 0x20000000U
+
+#define GPIO_OSPEEDER_OSPEEDR15 0xC0000000U
+#define GPIO_OSPEEDER_OSPEEDR15_0 0x40000000U
+#define GPIO_OSPEEDER_OSPEEDR15_1 0x80000000U
+
+/****************** Bits definition for GPIO_PUPDR register *****************/
+#define GPIO_PUPDR_PUPDR0 0x00000003U
+#define GPIO_PUPDR_PUPDR0_0 0x00000001U
+#define GPIO_PUPDR_PUPDR0_1 0x00000002U
+
+#define GPIO_PUPDR_PUPDR1 0x0000000CU
+#define GPIO_PUPDR_PUPDR1_0 0x00000004U
+#define GPIO_PUPDR_PUPDR1_1 0x00000008U
+
+#define GPIO_PUPDR_PUPDR2 0x00000030U
+#define GPIO_PUPDR_PUPDR2_0 0x00000010U
+#define GPIO_PUPDR_PUPDR2_1 0x00000020U
+
+#define GPIO_PUPDR_PUPDR3 0x000000C0U
+#define GPIO_PUPDR_PUPDR3_0 0x00000040U
+#define GPIO_PUPDR_PUPDR3_1 0x00000080U
+
+#define GPIO_PUPDR_PUPDR4 0x00000300U
+#define GPIO_PUPDR_PUPDR4_0 0x00000100U
+#define GPIO_PUPDR_PUPDR4_1 0x00000200U
+
+#define GPIO_PUPDR_PUPDR5 0x00000C00U
+#define GPIO_PUPDR_PUPDR5_0 0x00000400U
+#define GPIO_PUPDR_PUPDR5_1 0x00000800U
+
+#define GPIO_PUPDR_PUPDR6 0x00003000U
+#define GPIO_PUPDR_PUPDR6_0 0x00001000U
+#define GPIO_PUPDR_PUPDR6_1 0x00002000U
+
+#define GPIO_PUPDR_PUPDR7 0x0000C000U
+#define GPIO_PUPDR_PUPDR7_0 0x00004000U
+#define GPIO_PUPDR_PUPDR7_1 0x00008000U
+
+#define GPIO_PUPDR_PUPDR8 0x00030000U
+#define GPIO_PUPDR_PUPDR8_0 0x00010000U
+#define GPIO_PUPDR_PUPDR8_1 0x00020000U
+
+#define GPIO_PUPDR_PUPDR9 0x000C0000U
+#define GPIO_PUPDR_PUPDR9_0 0x00040000U
+#define GPIO_PUPDR_PUPDR9_1 0x00080000U
+
+#define GPIO_PUPDR_PUPDR10 0x00300000U
+#define GPIO_PUPDR_PUPDR10_0 0x00100000U
+#define GPIO_PUPDR_PUPDR10_1 0x00200000U
+
+#define GPIO_PUPDR_PUPDR11 0x00C00000U
+#define GPIO_PUPDR_PUPDR11_0 0x00400000U
+#define GPIO_PUPDR_PUPDR11_1 0x00800000U
+
+#define GPIO_PUPDR_PUPDR12 0x03000000U
+#define GPIO_PUPDR_PUPDR12_0 0x01000000U
+#define GPIO_PUPDR_PUPDR12_1 0x02000000U
+
+#define GPIO_PUPDR_PUPDR13 0x0C000000U
+#define GPIO_PUPDR_PUPDR13_0 0x04000000U
+#define GPIO_PUPDR_PUPDR13_1 0x08000000U
+
+#define GPIO_PUPDR_PUPDR14 0x30000000U
+#define GPIO_PUPDR_PUPDR14_0 0x10000000U
+#define GPIO_PUPDR_PUPDR14_1 0x20000000U
+
+#define GPIO_PUPDR_PUPDR15 0xC0000000U
+#define GPIO_PUPDR_PUPDR15_0 0x40000000U
+#define GPIO_PUPDR_PUPDR15_1 0x80000000U
+
+/****************** Bits definition for GPIO_IDR register *******************/
+#define GPIO_IDR_IDR_0 0x00000001U
+#define GPIO_IDR_IDR_1 0x00000002U
+#define GPIO_IDR_IDR_2 0x00000004U
+#define GPIO_IDR_IDR_3 0x00000008U
+#define GPIO_IDR_IDR_4 0x00000010U
+#define GPIO_IDR_IDR_5 0x00000020U
+#define GPIO_IDR_IDR_6 0x00000040U
+#define GPIO_IDR_IDR_7 0x00000080U
+#define GPIO_IDR_IDR_8 0x00000100U
+#define GPIO_IDR_IDR_9 0x00000200U
+#define GPIO_IDR_IDR_10 0x00000400U
+#define GPIO_IDR_IDR_11 0x00000800U
+#define GPIO_IDR_IDR_12 0x00001000U
+#define GPIO_IDR_IDR_13 0x00002000U
+#define GPIO_IDR_IDR_14 0x00004000U
+#define GPIO_IDR_IDR_15 0x00008000U
+/* Old GPIO_IDR register bits definition, maintained for legacy purpose */
+#define GPIO_OTYPER_IDR_0 GPIO_IDR_IDR_0
+#define GPIO_OTYPER_IDR_1 GPIO_IDR_IDR_1
+#define GPIO_OTYPER_IDR_2 GPIO_IDR_IDR_2
+#define GPIO_OTYPER_IDR_3 GPIO_IDR_IDR_3
+#define GPIO_OTYPER_IDR_4 GPIO_IDR_IDR_4
+#define GPIO_OTYPER_IDR_5 GPIO_IDR_IDR_5
+#define GPIO_OTYPER_IDR_6 GPIO_IDR_IDR_6
+#define GPIO_OTYPER_IDR_7 GPIO_IDR_IDR_7
+#define GPIO_OTYPER_IDR_8 GPIO_IDR_IDR_8
+#define GPIO_OTYPER_IDR_9 GPIO_IDR_IDR_9
+#define GPIO_OTYPER_IDR_10 GPIO_IDR_IDR_10
+#define GPIO_OTYPER_IDR_11 GPIO_IDR_IDR_11
+#define GPIO_OTYPER_IDR_12 GPIO_IDR_IDR_12
+#define GPIO_OTYPER_IDR_13 GPIO_IDR_IDR_13
+#define GPIO_OTYPER_IDR_14 GPIO_IDR_IDR_14
+#define GPIO_OTYPER_IDR_15 GPIO_IDR_IDR_15
+
+/****************** Bits definition for GPIO_ODR register *******************/
+#define GPIO_ODR_ODR_0 0x00000001U
+#define GPIO_ODR_ODR_1 0x00000002U
+#define GPIO_ODR_ODR_2 0x00000004U
+#define GPIO_ODR_ODR_3 0x00000008U
+#define GPIO_ODR_ODR_4 0x00000010U
+#define GPIO_ODR_ODR_5 0x00000020U
+#define GPIO_ODR_ODR_6 0x00000040U
+#define GPIO_ODR_ODR_7 0x00000080U
+#define GPIO_ODR_ODR_8 0x00000100U
+#define GPIO_ODR_ODR_9 0x00000200U
+#define GPIO_ODR_ODR_10 0x00000400U
+#define GPIO_ODR_ODR_11 0x00000800U
+#define GPIO_ODR_ODR_12 0x00001000U
+#define GPIO_ODR_ODR_13 0x00002000U
+#define GPIO_ODR_ODR_14 0x00004000U
+#define GPIO_ODR_ODR_15 0x00008000U
+/* Old GPIO_ODR register bits definition, maintained for legacy purpose */
+#define GPIO_OTYPER_ODR_0 GPIO_ODR_ODR_0
+#define GPIO_OTYPER_ODR_1 GPIO_ODR_ODR_1
+#define GPIO_OTYPER_ODR_2 GPIO_ODR_ODR_2
+#define GPIO_OTYPER_ODR_3 GPIO_ODR_ODR_3
+#define GPIO_OTYPER_ODR_4 GPIO_ODR_ODR_4
+#define GPIO_OTYPER_ODR_5 GPIO_ODR_ODR_5
+#define GPIO_OTYPER_ODR_6 GPIO_ODR_ODR_6
+#define GPIO_OTYPER_ODR_7 GPIO_ODR_ODR_7
+#define GPIO_OTYPER_ODR_8 GPIO_ODR_ODR_8
+#define GPIO_OTYPER_ODR_9 GPIO_ODR_ODR_9
+#define GPIO_OTYPER_ODR_10 GPIO_ODR_ODR_10
+#define GPIO_OTYPER_ODR_11 GPIO_ODR_ODR_11
+#define GPIO_OTYPER_ODR_12 GPIO_ODR_ODR_12
+#define GPIO_OTYPER_ODR_13 GPIO_ODR_ODR_13
+#define GPIO_OTYPER_ODR_14 GPIO_ODR_ODR_14
+#define GPIO_OTYPER_ODR_15 GPIO_ODR_ODR_15
+
+/****************** Bits definition for GPIO_BSRR register ******************/
+#define GPIO_BSRR_BS_0 0x00000001U
+#define GPIO_BSRR_BS_1 0x00000002U
+#define GPIO_BSRR_BS_2 0x00000004U
+#define GPIO_BSRR_BS_3 0x00000008U
+#define GPIO_BSRR_BS_4 0x00000010U
+#define GPIO_BSRR_BS_5 0x00000020U
+#define GPIO_BSRR_BS_6 0x00000040U
+#define GPIO_BSRR_BS_7 0x00000080U
+#define GPIO_BSRR_BS_8 0x00000100U
+#define GPIO_BSRR_BS_9 0x00000200U
+#define GPIO_BSRR_BS_10 0x00000400U
+#define GPIO_BSRR_BS_11 0x00000800U
+#define GPIO_BSRR_BS_12 0x00001000U
+#define GPIO_BSRR_BS_13 0x00002000U
+#define GPIO_BSRR_BS_14 0x00004000U
+#define GPIO_BSRR_BS_15 0x00008000U
+#define GPIO_BSRR_BR_0 0x00010000U
+#define GPIO_BSRR_BR_1 0x00020000U
+#define GPIO_BSRR_BR_2 0x00040000U
+#define GPIO_BSRR_BR_3 0x00080000U
+#define GPIO_BSRR_BR_4 0x00100000U
+#define GPIO_BSRR_BR_5 0x00200000U
+#define GPIO_BSRR_BR_6 0x00400000U
+#define GPIO_BSRR_BR_7 0x00800000U
+#define GPIO_BSRR_BR_8 0x01000000U
+#define GPIO_BSRR_BR_9 0x02000000U
+#define GPIO_BSRR_BR_10 0x04000000U
+#define GPIO_BSRR_BR_11 0x08000000U
+#define GPIO_BSRR_BR_12 0x10000000U
+#define GPIO_BSRR_BR_13 0x20000000U
+#define GPIO_BSRR_BR_14 0x40000000U
+#define GPIO_BSRR_BR_15 0x80000000U
+
+/****************** Bit definition for GPIO_LCKR register *********************/
+#define GPIO_LCKR_LCK0 0x00000001U
+#define GPIO_LCKR_LCK1 0x00000002U
+#define GPIO_LCKR_LCK2 0x00000004U
+#define GPIO_LCKR_LCK3 0x00000008U
+#define GPIO_LCKR_LCK4 0x00000010U
+#define GPIO_LCKR_LCK5 0x00000020U
+#define GPIO_LCKR_LCK6 0x00000040U
+#define GPIO_LCKR_LCK7 0x00000080U
+#define GPIO_LCKR_LCK8 0x00000100U
+#define GPIO_LCKR_LCK9 0x00000200U
+#define GPIO_LCKR_LCK10 0x00000400U
+#define GPIO_LCKR_LCK11 0x00000800U
+#define GPIO_LCKR_LCK12 0x00001000U
+#define GPIO_LCKR_LCK13 0x00002000U
+#define GPIO_LCKR_LCK14 0x00004000U
+#define GPIO_LCKR_LCK15 0x00008000U
+#define GPIO_LCKR_LCKK 0x00010000U
+
+/******************************************************************************/
+/* */
+/* HASH */
+/* */
+/******************************************************************************/
+/****************** Bits definition for HASH_CR register ********************/
+#define HASH_CR_INIT 0x00000004U
+#define HASH_CR_DMAE 0x00000008U
+#define HASH_CR_DATATYPE 0x00000030U
+#define HASH_CR_DATATYPE_0 0x00000010U
+#define HASH_CR_DATATYPE_1 0x00000020U
+#define HASH_CR_MODE 0x00000040U
+#define HASH_CR_ALGO 0x00040080U
+#define HASH_CR_ALGO_0 0x00000080U
+#define HASH_CR_ALGO_1 0x00040000U
+#define HASH_CR_NBW 0x00000F00U
+#define HASH_CR_NBW_0 0x00000100U
+#define HASH_CR_NBW_1 0x00000200U
+#define HASH_CR_NBW_2 0x00000400U
+#define HASH_CR_NBW_3 0x00000800U
+#define HASH_CR_DINNE 0x00001000U
+#define HASH_CR_MDMAT 0x00002000U
+#define HASH_CR_LKEY 0x00010000U
+
+/****************** Bits definition for HASH_STR register *******************/
+#define HASH_STR_NBLW 0x0000001FU
+#define HASH_STR_NBLW_0 0x00000001U
+#define HASH_STR_NBLW_1 0x00000002U
+#define HASH_STR_NBLW_2 0x00000004U
+#define HASH_STR_NBLW_3 0x00000008U
+#define HASH_STR_NBLW_4 0x00000010U
+#define HASH_STR_DCAL 0x00000100U
+/* Aliases for HASH_STR register */
+#define HASH_STR_NBW HASH_STR_NBLW
+#define HASH_STR_NBW_0 HASH_STR_NBLW_0
+#define HASH_STR_NBW_1 HASH_STR_NBLW_1
+#define HASH_STR_NBW_2 HASH_STR_NBLW_2
+#define HASH_STR_NBW_3 HASH_STR_NBLW_3
+#define HASH_STR_NBW_4 HASH_STR_NBLW_4
+
+/****************** Bits definition for HASH_IMR register *******************/
+#define HASH_IMR_DINIE 0x00000001U
+#define HASH_IMR_DCIE 0x00000002U
+/* Aliases for HASH_IMR register */
+#define HASH_IMR_DINIM HASH_IMR_DINIE
+#define HASH_IMR_DCIM HASH_IMR_DCIE
+
+/****************** Bits definition for HASH_SR register ********************/
+#define HASH_SR_DINIS 0x00000001U
+#define HASH_SR_DCIS 0x00000002U
+#define HASH_SR_DMAS 0x00000004U
+#define HASH_SR_BUSY 0x00000008U
+
+/******************************************************************************/
+/* */
+/* Inter-integrated Circuit Interface */
+/* */
+/******************************************************************************/
+/******************* Bit definition for I2C_CR1 register ********************/
+#define I2C_CR1_PE 0x00000001U /*!<Peripheral Enable */
+#define I2C_CR1_SMBUS 0x00000002U /*!<SMBus Mode */
+#define I2C_CR1_SMBTYPE 0x00000008U /*!<SMBus Type */
+#define I2C_CR1_ENARP 0x00000010U /*!<ARP Enable */
+#define I2C_CR1_ENPEC 0x00000020U /*!<PEC Enable */
+#define I2C_CR1_ENGC 0x00000040U /*!<General Call Enable */
+#define I2C_CR1_NOSTRETCH 0x00000080U /*!<Clock Stretching Disable (Slave mode) */
+#define I2C_CR1_START 0x00000100U /*!<Start Generation */
+#define I2C_CR1_STOP 0x00000200U /*!<Stop Generation */
+#define I2C_CR1_ACK 0x00000400U /*!<Acknowledge Enable */
+#define I2C_CR1_POS 0x00000800U /*!<Acknowledge/PEC Position (for data reception) */
+#define I2C_CR1_PEC 0x00001000U /*!<Packet Error Checking */
+#define I2C_CR1_ALERT 0x00002000U /*!<SMBus Alert */
+#define I2C_CR1_SWRST 0x00008000U /*!<Software Reset */
+
+/******************* Bit definition for I2C_CR2 register ********************/
+#define I2C_CR2_FREQ 0x0000003FU /*!<FREQ[5:0] bits (Peripheral Clock Frequency) */
+#define I2C_CR2_FREQ_0 0x00000001U /*!<Bit 0 */
+#define I2C_CR2_FREQ_1 0x00000002U /*!<Bit 1 */
+#define I2C_CR2_FREQ_2 0x00000004U /*!<Bit 2 */
+#define I2C_CR2_FREQ_3 0x00000008U /*!<Bit 3 */
+#define I2C_CR2_FREQ_4 0x00000010U /*!<Bit 4 */
+#define I2C_CR2_FREQ_5 0x00000020U /*!<Bit 5 */
+
+#define I2C_CR2_ITERREN 0x00000100U /*!<Error Interrupt Enable */
+#define I2C_CR2_ITEVTEN 0x00000200U /*!<Event Interrupt Enable */
+#define I2C_CR2_ITBUFEN 0x00000400U /*!<Buffer Interrupt Enable */
+#define I2C_CR2_DMAEN 0x00000800U /*!<DMA Requests Enable */
+#define I2C_CR2_LAST 0x00001000U /*!<DMA Last Transfer */
+
+/******************* Bit definition for I2C_OAR1 register *******************/
+#define I2C_OAR1_ADD1_7 0x000000FEU /*!<Interface Address */
+#define I2C_OAR1_ADD8_9 0x00000300U /*!<Interface Address */
+
+#define I2C_OAR1_ADD0 0x00000001U /*!<Bit 0 */
+#define I2C_OAR1_ADD1 0x00000002U /*!<Bit 1 */
+#define I2C_OAR1_ADD2 0x00000004U /*!<Bit 2 */
+#define I2C_OAR1_ADD3 0x00000008U /*!<Bit 3 */
+#define I2C_OAR1_ADD4 0x00000010U /*!<Bit 4 */
+#define I2C_OAR1_ADD5 0x00000020U /*!<Bit 5 */
+#define I2C_OAR1_ADD6 0x00000040U /*!<Bit 6 */
+#define I2C_OAR1_ADD7 0x00000080U /*!<Bit 7 */
+#define I2C_OAR1_ADD8 0x00000100U /*!<Bit 8 */
+#define I2C_OAR1_ADD9 0x00000200U /*!<Bit 9 */
+
+#define I2C_OAR1_ADDMODE 0x00008000U /*!<Addressing Mode (Slave mode) */
+
+/******************* Bit definition for I2C_OAR2 register *******************/
+#define I2C_OAR2_ENDUAL 0x00000001U /*!<Dual addressing mode enable */
+#define I2C_OAR2_ADD2 0x000000FEU /*!<Interface address */
+
+/******************** Bit definition for I2C_DR register ********************/
+#define I2C_DR_DR 0x000000FFU /*!<8-bit Data Register */
+
+/******************* Bit definition for I2C_SR1 register ********************/
+#define I2C_SR1_SB 0x00000001U /*!<Start Bit (Master mode) */
+#define I2C_SR1_ADDR 0x00000002U /*!<Address sent (master mode)/matched (slave mode) */
+#define I2C_SR1_BTF 0x00000004U /*!<Byte Transfer Finished */
+#define I2C_SR1_ADD10 0x00000008U /*!<10-bit header sent (Master mode) */
+#define I2C_SR1_STOPF 0x00000010U /*!<Stop detection (Slave mode) */
+#define I2C_SR1_RXNE 0x00000040U /*!<Data Register not Empty (receivers) */
+#define I2C_SR1_TXE 0x00000080U /*!<Data Register Empty (transmitters) */
+#define I2C_SR1_BERR 0x00000100U /*!<Bus Error */
+#define I2C_SR1_ARLO 0x00000200U /*!<Arbitration Lost (master mode) */
+#define I2C_SR1_AF 0x00000400U /*!<Acknowledge Failure */
+#define I2C_SR1_OVR 0x00000800U /*!<Overrun/Underrun */
+#define I2C_SR1_PECERR 0x00001000U /*!<PEC Error in reception */
+#define I2C_SR1_TIMEOUT 0x00004000U /*!<Timeout or Tlow Error */
+#define I2C_SR1_SMBALERT 0x00008000U /*!<SMBus Alert */
+
+/******************* Bit definition for I2C_SR2 register ********************/
+#define I2C_SR2_MSL 0x00000001U /*!<Master/Slave */
+#define I2C_SR2_BUSY 0x00000002U /*!<Bus Busy */
+#define I2C_SR2_TRA 0x00000004U /*!<Transmitter/Receiver */
+#define I2C_SR2_GENCALL 0x00000010U /*!<General Call Address (Slave mode) */
+#define I2C_SR2_SMBDEFAULT 0x00000020U /*!<SMBus Device Default Address (Slave mode) */
+#define I2C_SR2_SMBHOST 0x00000040U /*!<SMBus Host Header (Slave mode) */
+#define I2C_SR2_DUALF 0x00000080U /*!<Dual Flag (Slave mode) */
+#define I2C_SR2_PEC 0x0000FF00U /*!<Packet Error Checking Register */
+
+/******************* Bit definition for I2C_CCR register ********************/
+#define I2C_CCR_CCR 0x00000FFFU /*!<Clock Control Register in Fast/Standard mode (Master mode) */
+#define I2C_CCR_DUTY 0x00004000U /*!<Fast Mode Duty Cycle */
+#define I2C_CCR_FS 0x00008000U /*!<I2C Master Mode Selection */
+
+/****************** Bit definition for I2C_TRISE register *******************/
+#define I2C_TRISE_TRISE 0x0000003FU /*!<Maximum Rise Time in Fast/Standard mode (Master mode) */
+
+/****************** Bit definition for I2C_FLTR register *******************/
+#define I2C_FLTR_DNF 0x0000000FU /*!<Digital Noise Filter */
+#define I2C_FLTR_ANOFF 0x00000010U /*!<Analog Noise Filter OFF */
+
+/******************************************************************************/
+/* */
+/* Independent WATCHDOG */
+/* */
+/******************************************************************************/
+/******************* Bit definition for IWDG_KR register ********************/
+#define IWDG_KR_KEY 0xFFFFU /*!<Key value (write only, read 0000h) */
+
+/******************* Bit definition for IWDG_PR register ********************/
+#define IWDG_PR_PR 0x07U /*!<PR[2:0] (Prescaler divider) */
+#define IWDG_PR_PR_0 0x01U /*!<Bit 0 */
+#define IWDG_PR_PR_1 0x02U /*!<Bit 1 */
+#define IWDG_PR_PR_2 0x04U /*!<Bit 2 */
+
+/******************* Bit definition for IWDG_RLR register *******************/
+#define IWDG_RLR_RL 0x0FFFU /*!<Watchdog counter reload value */
+
+/******************* Bit definition for IWDG_SR register ********************/
+#define IWDG_SR_PVU 0x01U /*!<Watchdog prescaler value update */
+#define IWDG_SR_RVU 0x02U /*!<Watchdog counter reload value update */
+
+
+/******************************************************************************/
+/* */
+/* Power Control */
+/* */
+/******************************************************************************/
+/******************** Bit definition for PWR_CR register ********************/
+#define PWR_CR_LPDS 0x00000001U /*!< Low-Power Deepsleep */
+#define PWR_CR_PDDS 0x00000002U /*!< Power Down Deepsleep */
+#define PWR_CR_CWUF 0x00000004U /*!< Clear Wakeup Flag */
+#define PWR_CR_CSBF 0x00000008U /*!< Clear Standby Flag */
+#define PWR_CR_PVDE 0x00000010U /*!< Power Voltage Detector Enable */
+
+#define PWR_CR_PLS 0x000000E0U /*!< PLS[2:0] bits (PVD Level Selection) */
+#define PWR_CR_PLS_0 0x00000020U /*!< Bit 0 */
+#define PWR_CR_PLS_1 0x00000040U /*!< Bit 1 */
+#define PWR_CR_PLS_2 0x00000080U /*!< Bit 2 */
+
+/*!< PVD level configuration */
+#define PWR_CR_PLS_LEV0 0x00000000U /*!< PVD level 0 */
+#define PWR_CR_PLS_LEV1 0x00000020U /*!< PVD level 1 */
+#define PWR_CR_PLS_LEV2 0x00000040U /*!< PVD level 2 */
+#define PWR_CR_PLS_LEV3 0x00000060U /*!< PVD level 3 */
+#define PWR_CR_PLS_LEV4 0x00000080U /*!< PVD level 4 */
+#define PWR_CR_PLS_LEV5 0x000000A0U /*!< PVD level 5 */
+#define PWR_CR_PLS_LEV6 0x000000C0U /*!< PVD level 6 */
+#define PWR_CR_PLS_LEV7 0x000000E0U /*!< PVD level 7 */
+
+#define PWR_CR_DBP 0x00000100U /*!< Disable Backup Domain write protection */
+#define PWR_CR_FPDS 0x00000200U /*!< Flash power down in Stop mode */
+#define PWR_CR_VOS 0x00004000U /*!< VOS bit (Regulator voltage scaling output selection) */
+
+/* Legacy define */
+#define PWR_CR_PMODE PWR_CR_VOS
+
+/******************* Bit definition for PWR_CSR register ********************/
+#define PWR_CSR_WUF 0x00000001U /*!< Wakeup Flag */
+#define PWR_CSR_SBF 0x00000002U /*!< Standby Flag */
+#define PWR_CSR_PVDO 0x00000004U /*!< PVD Output */
+#define PWR_CSR_BRR 0x00000008U /*!< Backup regulator ready */
+#define PWR_CSR_EWUP 0x00000100U /*!< Enable WKUP pin */
+#define PWR_CSR_BRE 0x00000200U /*!< Backup regulator enable */
+#define PWR_CSR_VOSRDY 0x00004000U /*!< Regulator voltage scaling output selection ready */
+
+/* Legacy define */
+#define PWR_CSR_REGRDY PWR_CSR_VOSRDY
+
+/******************************************************************************/
+/* */
+/* Reset and Clock Control */
+/* */
+/******************************************************************************/
+/******************** Bit definition for RCC_CR register ********************/
+#define RCC_CR_HSION 0x00000001U
+#define RCC_CR_HSIRDY 0x00000002U
+
+#define RCC_CR_HSITRIM 0x000000F8U
+#define RCC_CR_HSITRIM_0 0x00000008U/*!<Bit 0 */
+#define RCC_CR_HSITRIM_1 0x00000010U/*!<Bit 1 */
+#define RCC_CR_HSITRIM_2 0x00000020U/*!<Bit 2 */
+#define RCC_CR_HSITRIM_3 0x00000040U/*!<Bit 3 */
+#define RCC_CR_HSITRIM_4 0x00000080U/*!<Bit 4 */
+
+#define RCC_CR_HSICAL 0x0000FF00U
+#define RCC_CR_HSICAL_0 0x00000100U/*!<Bit 0 */
+#define RCC_CR_HSICAL_1 0x00000200U/*!<Bit 1 */
+#define RCC_CR_HSICAL_2 0x00000400U/*!<Bit 2 */
+#define RCC_CR_HSICAL_3 0x00000800U/*!<Bit 3 */
+#define RCC_CR_HSICAL_4 0x00001000U/*!<Bit 4 */
+#define RCC_CR_HSICAL_5 0x00002000U/*!<Bit 5 */
+#define RCC_CR_HSICAL_6 0x00004000U/*!<Bit 6 */
+#define RCC_CR_HSICAL_7 0x00008000U/*!<Bit 7 */
+
+#define RCC_CR_HSEON 0x00010000U
+#define RCC_CR_HSERDY 0x00020000U
+#define RCC_CR_HSEBYP 0x00040000U
+#define RCC_CR_CSSON 0x00080000U
+#define RCC_CR_PLLON 0x01000000U
+#define RCC_CR_PLLRDY 0x02000000U
+#define RCC_CR_PLLI2SON 0x04000000U
+#define RCC_CR_PLLI2SRDY 0x08000000U
+
+/******************** Bit definition for RCC_PLLCFGR register ***************/
+#define RCC_PLLCFGR_PLLM 0x0000003FU
+#define RCC_PLLCFGR_PLLM_0 0x00000001U
+#define RCC_PLLCFGR_PLLM_1 0x00000002U
+#define RCC_PLLCFGR_PLLM_2 0x00000004U
+#define RCC_PLLCFGR_PLLM_3 0x00000008U
+#define RCC_PLLCFGR_PLLM_4 0x00000010U
+#define RCC_PLLCFGR_PLLM_5 0x00000020U
+
+#define RCC_PLLCFGR_PLLN 0x00007FC0U
+#define RCC_PLLCFGR_PLLN_0 0x00000040U
+#define RCC_PLLCFGR_PLLN_1 0x00000080U
+#define RCC_PLLCFGR_PLLN_2 0x00000100U
+#define RCC_PLLCFGR_PLLN_3 0x00000200U
+#define RCC_PLLCFGR_PLLN_4 0x00000400U
+#define RCC_PLLCFGR_PLLN_5 0x00000800U
+#define RCC_PLLCFGR_PLLN_6 0x00001000U
+#define RCC_PLLCFGR_PLLN_7 0x00002000U
+#define RCC_PLLCFGR_PLLN_8 0x00004000U
+
+#define RCC_PLLCFGR_PLLP 0x00030000U
+#define RCC_PLLCFGR_PLLP_0 0x00010000U
+#define RCC_PLLCFGR_PLLP_1 0x00020000U
+
+#define RCC_PLLCFGR_PLLSRC 0x00400000U
+#define RCC_PLLCFGR_PLLSRC_HSE 0x00400000U
+#define RCC_PLLCFGR_PLLSRC_HSI 0x00000000U
+
+#define RCC_PLLCFGR_PLLQ 0x0F000000U
+#define RCC_PLLCFGR_PLLQ_0 0x01000000U
+#define RCC_PLLCFGR_PLLQ_1 0x02000000U
+#define RCC_PLLCFGR_PLLQ_2 0x04000000U
+#define RCC_PLLCFGR_PLLQ_3 0x08000000U
+
+/******************** Bit definition for RCC_CFGR register ******************/
+/*!< SW configuration */
+#define RCC_CFGR_SW 0x00000003U /*!< SW[1:0] bits (System clock Switch) */
+#define RCC_CFGR_SW_0 0x00000001U /*!< Bit 0 */
+#define RCC_CFGR_SW_1 0x00000002U /*!< Bit 1 */
+
+#define RCC_CFGR_SW_HSI 0x00000000U /*!< HSI selected as system clock */
+#define RCC_CFGR_SW_HSE 0x00000001U /*!< HSE selected as system clock */
+#define RCC_CFGR_SW_PLL 0x00000002U /*!< PLL selected as system clock */
+
+/*!< SWS configuration */
+#define RCC_CFGR_SWS 0x0000000CU /*!< SWS[1:0] bits (System Clock Switch Status) */
+#define RCC_CFGR_SWS_0 0x00000004U /*!< Bit 0 */
+#define RCC_CFGR_SWS_1 0x00000008U /*!< Bit 1 */
+
+#define RCC_CFGR_SWS_HSI 0x00000000U /*!< HSI oscillator used as system clock */
+#define RCC_CFGR_SWS_HSE 0x00000004U /*!< HSE oscillator used as system clock */
+#define RCC_CFGR_SWS_PLL 0x00000008U /*!< PLL used as system clock */
+
+/*!< HPRE configuration */
+#define RCC_CFGR_HPRE 0x000000F0U /*!< HPRE[3:0] bits (AHB prescaler) */
+#define RCC_CFGR_HPRE_0 0x00000010U /*!< Bit 0 */
+#define RCC_CFGR_HPRE_1 0x00000020U /*!< Bit 1 */
+#define RCC_CFGR_HPRE_2 0x00000040U /*!< Bit 2 */
+#define RCC_CFGR_HPRE_3 0x00000080U /*!< Bit 3 */
+
+#define RCC_CFGR_HPRE_DIV1 0x00000000U /*!< SYSCLK not divided */
+#define RCC_CFGR_HPRE_DIV2 0x00000080U /*!< SYSCLK divided by 2 */
+#define RCC_CFGR_HPRE_DIV4 0x00000090U /*!< SYSCLK divided by 4 */
+#define RCC_CFGR_HPRE_DIV8 0x000000A0U /*!< SYSCLK divided by 8 */
+#define RCC_CFGR_HPRE_DIV16 0x000000B0U /*!< SYSCLK divided by 16 */
+#define RCC_CFGR_HPRE_DIV64 0x000000C0U /*!< SYSCLK divided by 64 */
+#define RCC_CFGR_HPRE_DIV128 0x000000D0U /*!< SYSCLK divided by 128 */
+#define RCC_CFGR_HPRE_DIV256 0x000000E0U /*!< SYSCLK divided by 256 */
+#define RCC_CFGR_HPRE_DIV512 0x000000F0U /*!< SYSCLK divided by 512 */
+
+/*!< PPRE1 configuration */
+#define RCC_CFGR_PPRE1 0x00001C00U /*!< PRE1[2:0] bits (APB1 prescaler) */
+#define RCC_CFGR_PPRE1_0 0x00000400U /*!< Bit 0 */
+#define RCC_CFGR_PPRE1_1 0x00000800U /*!< Bit 1 */
+#define RCC_CFGR_PPRE1_2 0x00001000U /*!< Bit 2 */
+
+#define RCC_CFGR_PPRE1_DIV1 0x00000000U /*!< HCLK not divided */
+#define RCC_CFGR_PPRE1_DIV2 0x00001000U /*!< HCLK divided by 2 */
+#define RCC_CFGR_PPRE1_DIV4 0x00001400U /*!< HCLK divided by 4 */
+#define RCC_CFGR_PPRE1_DIV8 0x00001800U /*!< HCLK divided by 8 */
+#define RCC_CFGR_PPRE1_DIV16 0x00001C00U /*!< HCLK divided by 16 */
+
+/*!< PPRE2 configuration */
+#define RCC_CFGR_PPRE2 0x0000E000U /*!< PRE2[2:0] bits (APB2 prescaler) */
+#define RCC_CFGR_PPRE2_0 0x00002000U /*!< Bit 0 */
+#define RCC_CFGR_PPRE2_1 0x00004000U /*!< Bit 1 */
+#define RCC_CFGR_PPRE2_2 0x00008000U /*!< Bit 2 */
+
+#define RCC_CFGR_PPRE2_DIV1 0x00000000U /*!< HCLK not divided */
+#define RCC_CFGR_PPRE2_DIV2 0x00008000U /*!< HCLK divided by 2 */
+#define RCC_CFGR_PPRE2_DIV4 0x0000A000U /*!< HCLK divided by 4 */
+#define RCC_CFGR_PPRE2_DIV8 0x0000C000U /*!< HCLK divided by 8 */
+#define RCC_CFGR_PPRE2_DIV16 0x0000E000U /*!< HCLK divided by 16 */
+
+/*!< RTCPRE configuration */
+#define RCC_CFGR_RTCPRE 0x001F0000U
+#define RCC_CFGR_RTCPRE_0 0x00010000U
+#define RCC_CFGR_RTCPRE_1 0x00020000U
+#define RCC_CFGR_RTCPRE_2 0x00040000U
+#define RCC_CFGR_RTCPRE_3 0x00080000U
+#define RCC_CFGR_RTCPRE_4 0x00100000U
+
+/*!< MCO1 configuration */
+#define RCC_CFGR_MCO1 0x00600000U
+#define RCC_CFGR_MCO1_0 0x00200000U
+#define RCC_CFGR_MCO1_1 0x00400000U
+
+#define RCC_CFGR_I2SSRC 0x00800000U
+
+#define RCC_CFGR_MCO1PRE 0x07000000U
+#define RCC_CFGR_MCO1PRE_0 0x01000000U
+#define RCC_CFGR_MCO1PRE_1 0x02000000U
+#define RCC_CFGR_MCO1PRE_2 0x04000000U
+
+#define RCC_CFGR_MCO2PRE 0x38000000U
+#define RCC_CFGR_MCO2PRE_0 0x08000000U
+#define RCC_CFGR_MCO2PRE_1 0x10000000U
+#define RCC_CFGR_MCO2PRE_2 0x20000000U
+
+#define RCC_CFGR_MCO2 0xC0000000U
+#define RCC_CFGR_MCO2_0 0x40000000U
+#define RCC_CFGR_MCO2_1 0x80000000U
+
+/******************** Bit definition for RCC_CIR register *******************/
+#define RCC_CIR_LSIRDYF 0x00000001U
+#define RCC_CIR_LSERDYF 0x00000002U
+#define RCC_CIR_HSIRDYF 0x00000004U
+#define RCC_CIR_HSERDYF 0x00000008U
+#define RCC_CIR_PLLRDYF 0x00000010U
+#define RCC_CIR_PLLI2SRDYF 0x00000020U
+
+#define RCC_CIR_CSSF 0x00000080U
+#define RCC_CIR_LSIRDYIE 0x00000100U
+#define RCC_CIR_LSERDYIE 0x00000200U
+#define RCC_CIR_HSIRDYIE 0x00000400U
+#define RCC_CIR_HSERDYIE 0x00000800U
+#define RCC_CIR_PLLRDYIE 0x00001000U
+#define RCC_CIR_PLLI2SRDYIE 0x00002000U
+
+#define RCC_CIR_LSIRDYC 0x00010000U
+#define RCC_CIR_LSERDYC 0x00020000U
+#define RCC_CIR_HSIRDYC 0x00040000U
+#define RCC_CIR_HSERDYC 0x00080000U
+#define RCC_CIR_PLLRDYC 0x00100000U
+#define RCC_CIR_PLLI2SRDYC 0x00200000U
+
+#define RCC_CIR_CSSC 0x00800000U
+
+/******************** Bit definition for RCC_AHB1RSTR register **************/
+#define RCC_AHB1RSTR_GPIOARST 0x00000001U
+#define RCC_AHB1RSTR_GPIOBRST 0x00000002U
+#define RCC_AHB1RSTR_GPIOCRST 0x00000004U
+#define RCC_AHB1RSTR_GPIODRST 0x00000008U
+#define RCC_AHB1RSTR_GPIOERST 0x00000010U
+#define RCC_AHB1RSTR_GPIOFRST 0x00000020U
+#define RCC_AHB1RSTR_GPIOGRST 0x00000040U
+#define RCC_AHB1RSTR_GPIOHRST 0x00000080U
+#define RCC_AHB1RSTR_GPIOIRST 0x00000100U
+#define RCC_AHB1RSTR_CRCRST 0x00001000U
+#define RCC_AHB1RSTR_DMA1RST 0x00200000U
+#define RCC_AHB1RSTR_DMA2RST 0x00400000U
+#define RCC_AHB1RSTR_OTGHRST 0x20000000U
+
+/******************** Bit definition for RCC_AHB2RSTR register **************/
+#define RCC_AHB2RSTR_CRYPRST 0x00000010U
+#define RCC_AHB2RSTR_HASHRST 0x00000020U
+ /* maintained for legacy purpose */
+ #define RCC_AHB2RSTR_HSAHRST RCC_AHB2RSTR_HASHRST
+#define RCC_AHB2RSTR_RNGRST 0x00000040U
+#define RCC_AHB2RSTR_OTGFSRST 0x00000080U
+
+/******************** Bit definition for RCC_AHB3RSTR register **************/
+
+#define RCC_AHB3RSTR_FSMCRST 0x00000001U
+
+/******************** Bit definition for RCC_APB1RSTR register **************/
+#define RCC_APB1RSTR_TIM2RST 0x00000001U
+#define RCC_APB1RSTR_TIM3RST 0x00000002U
+#define RCC_APB1RSTR_TIM4RST 0x00000004U
+#define RCC_APB1RSTR_TIM5RST 0x00000008U
+#define RCC_APB1RSTR_TIM6RST 0x00000010U
+#define RCC_APB1RSTR_TIM7RST 0x00000020U
+#define RCC_APB1RSTR_TIM12RST 0x00000040U
+#define RCC_APB1RSTR_TIM13RST 0x00000080U
+#define RCC_APB1RSTR_TIM14RST 0x00000100U
+#define RCC_APB1RSTR_WWDGRST 0x00000800U
+#define RCC_APB1RSTR_SPI2RST 0x00004000U
+#define RCC_APB1RSTR_SPI3RST 0x00008000U
+#define RCC_APB1RSTR_USART2RST 0x00020000U
+#define RCC_APB1RSTR_USART3RST 0x00040000U
+#define RCC_APB1RSTR_UART4RST 0x00080000U
+#define RCC_APB1RSTR_UART5RST 0x00100000U
+#define RCC_APB1RSTR_I2C1RST 0x00200000U
+#define RCC_APB1RSTR_I2C2RST 0x00400000U
+#define RCC_APB1RSTR_I2C3RST 0x00800000U
+#define RCC_APB1RSTR_CAN1RST 0x02000000U
+#define RCC_APB1RSTR_CAN2RST 0x04000000U
+#define RCC_APB1RSTR_PWRRST 0x10000000U
+#define RCC_APB1RSTR_DACRST 0x20000000U
+
+/******************** Bit definition for RCC_APB2RSTR register **************/
+#define RCC_APB2RSTR_TIM1RST 0x00000001U
+#define RCC_APB2RSTR_TIM8RST 0x00000002U
+#define RCC_APB2RSTR_USART1RST 0x00000010U
+#define RCC_APB2RSTR_USART6RST 0x00000020U
+#define RCC_APB2RSTR_ADCRST 0x00000100U
+#define RCC_APB2RSTR_SDIORST 0x00000800U
+#define RCC_APB2RSTR_SPI1RST 0x00001000U
+#define RCC_APB2RSTR_SYSCFGRST 0x00004000U
+#define RCC_APB2RSTR_TIM9RST 0x00010000U
+#define RCC_APB2RSTR_TIM10RST 0x00020000U
+#define RCC_APB2RSTR_TIM11RST 0x00040000U
+
+/* Old SPI1RST bit definition, maintained for legacy purpose */
+#define RCC_APB2RSTR_SPI1 RCC_APB2RSTR_SPI1RST
+
+/******************** Bit definition for RCC_AHB1ENR register ***************/
+#define RCC_AHB1ENR_GPIOAEN 0x00000001U
+#define RCC_AHB1ENR_GPIOBEN 0x00000002U
+#define RCC_AHB1ENR_GPIOCEN 0x00000004U
+#define RCC_AHB1ENR_GPIODEN 0x00000008U
+#define RCC_AHB1ENR_GPIOEEN 0x00000010U
+#define RCC_AHB1ENR_GPIOFEN 0x00000020U
+#define RCC_AHB1ENR_GPIOGEN 0x00000040U
+#define RCC_AHB1ENR_GPIOHEN 0x00000080U
+#define RCC_AHB1ENR_GPIOIEN 0x00000100U
+#define RCC_AHB1ENR_CRCEN 0x00001000U
+#define RCC_AHB1ENR_BKPSRAMEN 0x00040000U
+#define RCC_AHB1ENR_CCMDATARAMEN 0x00100000U
+#define RCC_AHB1ENR_DMA1EN 0x00200000U
+#define RCC_AHB1ENR_DMA2EN 0x00400000U
+
+#define RCC_AHB1ENR_OTGHSEN 0x20000000U
+#define RCC_AHB1ENR_OTGHSULPIEN 0x40000000U
+
+/******************** Bit definition for RCC_AHB2ENR register ***************/
+#define RCC_AHB2ENR_CRYPEN 0x00000010U
+#define RCC_AHB2ENR_HASHEN 0x00000020U
+#define RCC_AHB2ENR_RNGEN 0x00000040U
+#define RCC_AHB2ENR_OTGFSEN 0x00000080U
+
+/******************** Bit definition for RCC_AHB3ENR register ***************/
+
+#define RCC_AHB3ENR_FSMCEN 0x00000001U
+
+/******************** Bit definition for RCC_APB1ENR register ***************/
+#define RCC_APB1ENR_TIM2EN 0x00000001U
+#define RCC_APB1ENR_TIM3EN 0x00000002U
+#define RCC_APB1ENR_TIM4EN 0x00000004U
+#define RCC_APB1ENR_TIM5EN 0x00000008U
+#define RCC_APB1ENR_TIM6EN 0x00000010U
+#define RCC_APB1ENR_TIM7EN 0x00000020U
+#define RCC_APB1ENR_TIM12EN 0x00000040U
+#define RCC_APB1ENR_TIM13EN 0x00000080U
+#define RCC_APB1ENR_TIM14EN 0x00000100U
+#define RCC_APB1ENR_WWDGEN 0x00000800U
+#define RCC_APB1ENR_SPI2EN 0x00004000U
+#define RCC_APB1ENR_SPI3EN 0x00008000U
+#define RCC_APB1ENR_USART2EN 0x00020000U
+#define RCC_APB1ENR_USART3EN 0x00040000U
+#define RCC_APB1ENR_UART4EN 0x00080000U
+#define RCC_APB1ENR_UART5EN 0x00100000U
+#define RCC_APB1ENR_I2C1EN 0x00200000U
+#define RCC_APB1ENR_I2C2EN 0x00400000U
+#define RCC_APB1ENR_I2C3EN 0x00800000U
+#define RCC_APB1ENR_CAN1EN 0x02000000U
+#define RCC_APB1ENR_CAN2EN 0x04000000U
+#define RCC_APB1ENR_PWREN 0x10000000U
+#define RCC_APB1ENR_DACEN 0x20000000U
+
+/******************** Bit definition for RCC_APB2ENR register ***************/
+#define RCC_APB2ENR_TIM1EN 0x00000001U
+#define RCC_APB2ENR_TIM8EN 0x00000002U
+#define RCC_APB2ENR_USART1EN 0x00000010U
+#define RCC_APB2ENR_USART6EN 0x00000020U
+#define RCC_APB2ENR_ADC1EN 0x00000100U
+#define RCC_APB2ENR_ADC2EN 0x00000200U
+#define RCC_APB2ENR_ADC3EN 0x00000400U
+#define RCC_APB2ENR_SDIOEN 0x00000800U
+#define RCC_APB2ENR_SPI1EN 0x00001000U
+#define RCC_APB2ENR_SYSCFGEN 0x00004000U
+#define RCC_APB2ENR_TIM9EN 0x00010000U
+#define RCC_APB2ENR_TIM10EN 0x00020000U
+#define RCC_APB2ENR_TIM11EN 0x00040000U
+#define RCC_APB2ENR_SPI5EN 0x00100000U
+#define RCC_APB2ENR_SPI6EN 0x00200000U
+
+/******************** Bit definition for RCC_AHB1LPENR register *************/
+#define RCC_AHB1LPENR_GPIOALPEN 0x00000001U
+#define RCC_AHB1LPENR_GPIOBLPEN 0x00000002U
+#define RCC_AHB1LPENR_GPIOCLPEN 0x00000004U
+#define RCC_AHB1LPENR_GPIODLPEN 0x00000008U
+#define RCC_AHB1LPENR_GPIOELPEN 0x00000010U
+#define RCC_AHB1LPENR_GPIOFLPEN 0x00000020U
+#define RCC_AHB1LPENR_GPIOGLPEN 0x00000040U
+#define RCC_AHB1LPENR_GPIOHLPEN 0x00000080U
+#define RCC_AHB1LPENR_GPIOILPEN 0x00000100U
+#define RCC_AHB1LPENR_CRCLPEN 0x00001000U
+#define RCC_AHB1LPENR_FLITFLPEN 0x00008000U
+#define RCC_AHB1LPENR_SRAM1LPEN 0x00010000U
+#define RCC_AHB1LPENR_SRAM2LPEN 0x00020000U
+#define RCC_AHB1LPENR_BKPSRAMLPEN 0x00040000U
+#define RCC_AHB1LPENR_DMA1LPEN 0x00200000U
+#define RCC_AHB1LPENR_DMA2LPEN 0x00400000U
+#define RCC_AHB1LPENR_OTGHSLPEN 0x20000000U
+#define RCC_AHB1LPENR_OTGHSULPILPEN 0x40000000U
+
+/******************** Bit definition for RCC_AHB2LPENR register *************/
+#define RCC_AHB2LPENR_CRYPLPEN 0x00000010U
+#define RCC_AHB2LPENR_HASHLPEN 0x00000020U
+#define RCC_AHB2LPENR_RNGLPEN 0x00000040U
+#define RCC_AHB2LPENR_OTGFSLPEN 0x00000080U
+
+/******************** Bit definition for RCC_AHB3LPENR register *************/
+
+#define RCC_AHB3LPENR_FSMCLPEN 0x00000001U
+
+/******************** Bit definition for RCC_APB1LPENR register *************/
+#define RCC_APB1LPENR_TIM2LPEN 0x00000001U
+#define RCC_APB1LPENR_TIM3LPEN 0x00000002U
+#define RCC_APB1LPENR_TIM4LPEN 0x00000004U
+#define RCC_APB1LPENR_TIM5LPEN 0x00000008U
+#define RCC_APB1LPENR_TIM6LPEN 0x00000010U
+#define RCC_APB1LPENR_TIM7LPEN 0x00000020U
+#define RCC_APB1LPENR_TIM12LPEN 0x00000040U
+#define RCC_APB1LPENR_TIM13LPEN 0x00000080U
+#define RCC_APB1LPENR_TIM14LPEN 0x00000100U
+#define RCC_APB1LPENR_WWDGLPEN 0x00000800U
+#define RCC_APB1LPENR_SPI2LPEN 0x00004000U
+#define RCC_APB1LPENR_SPI3LPEN 0x00008000U
+#define RCC_APB1LPENR_USART2LPEN 0x00020000U
+#define RCC_APB1LPENR_USART3LPEN 0x00040000U
+#define RCC_APB1LPENR_UART4LPEN 0x00080000U
+#define RCC_APB1LPENR_UART5LPEN 0x00100000U
+#define RCC_APB1LPENR_I2C1LPEN 0x00200000U
+#define RCC_APB1LPENR_I2C2LPEN 0x00400000U
+#define RCC_APB1LPENR_I2C3LPEN 0x00800000U
+#define RCC_APB1LPENR_CAN1LPEN 0x02000000U
+#define RCC_APB1LPENR_CAN2LPEN 0x04000000U
+#define RCC_APB1LPENR_PWRLPEN 0x10000000U
+#define RCC_APB1LPENR_DACLPEN 0x20000000U
+
+/******************** Bit definition for RCC_APB2LPENR register *************/
+#define RCC_APB2LPENR_TIM1LPEN 0x00000001U
+#define RCC_APB2LPENR_TIM8LPEN 0x00000002U
+#define RCC_APB2LPENR_USART1LPEN 0x00000010U
+#define RCC_APB2LPENR_USART6LPEN 0x00000020U
+#define RCC_APB2LPENR_ADC1LPEN 0x00000100U
+#define RCC_APB2LPENR_ADC2LPEN 0x00000200U
+#define RCC_APB2LPENR_ADC3LPEN 0x00000400U
+#define RCC_APB2LPENR_SDIOLPEN 0x00000800U
+#define RCC_APB2LPENR_SPI1LPEN 0x00001000U
+#define RCC_APB2LPENR_SYSCFGLPEN 0x00004000U
+#define RCC_APB2LPENR_TIM9LPEN 0x00010000U
+#define RCC_APB2LPENR_TIM10LPEN 0x00020000U
+#define RCC_APB2LPENR_TIM11LPEN 0x00040000U
+
+/******************** Bit definition for RCC_BDCR register ******************/
+#define RCC_BDCR_LSEON 0x00000001U
+#define RCC_BDCR_LSERDY 0x00000002U
+#define RCC_BDCR_LSEBYP 0x00000004U
+
+#define RCC_BDCR_RTCSEL 0x00000300U
+#define RCC_BDCR_RTCSEL_0 0x00000100U
+#define RCC_BDCR_RTCSEL_1 0x00000200U
+
+#define RCC_BDCR_RTCEN 0x00008000U
+#define RCC_BDCR_BDRST 0x00010000U
+
+/******************** Bit definition for RCC_CSR register *******************/
+#define RCC_CSR_LSION 0x00000001U
+#define RCC_CSR_LSIRDY 0x00000002U
+#define RCC_CSR_RMVF 0x01000000U
+#define RCC_CSR_BORRSTF 0x02000000U
+#define RCC_CSR_PADRSTF 0x04000000U
+#define RCC_CSR_PORRSTF 0x08000000U
+#define RCC_CSR_SFTRSTF 0x10000000U
+#define RCC_CSR_WDGRSTF 0x20000000U
+#define RCC_CSR_WWDGRSTF 0x40000000U
+#define RCC_CSR_LPWRRSTF 0x80000000U
+
+/******************** Bit definition for RCC_SSCGR register *****************/
+#define RCC_SSCGR_MODPER 0x00001FFFU
+#define RCC_SSCGR_INCSTEP 0x0FFFE000U
+#define RCC_SSCGR_SPREADSEL 0x40000000U
+#define RCC_SSCGR_SSCGEN 0x80000000U
+
+/******************** Bit definition for RCC_PLLI2SCFGR register ************/
+#define RCC_PLLI2SCFGR_PLLI2SN 0x00007FC0U
+#define RCC_PLLI2SCFGR_PLLI2SN_0 0x00000040U
+#define RCC_PLLI2SCFGR_PLLI2SN_1 0x00000080U
+#define RCC_PLLI2SCFGR_PLLI2SN_2 0x00000100U
+#define RCC_PLLI2SCFGR_PLLI2SN_3 0x00000200U
+#define RCC_PLLI2SCFGR_PLLI2SN_4 0x00000400U
+#define RCC_PLLI2SCFGR_PLLI2SN_5 0x00000800U
+#define RCC_PLLI2SCFGR_PLLI2SN_6 0x00001000U
+#define RCC_PLLI2SCFGR_PLLI2SN_7 0x00002000U
+#define RCC_PLLI2SCFGR_PLLI2SN_8 0x00004000U
+
+#define RCC_PLLI2SCFGR_PLLI2SR 0x70000000U
+#define RCC_PLLI2SCFGR_PLLI2SR_0 0x10000000U
+#define RCC_PLLI2SCFGR_PLLI2SR_1 0x20000000U
+#define RCC_PLLI2SCFGR_PLLI2SR_2 0x40000000U
+
+/******************************************************************************/
+/* */
+/* RNG */
+/* */
+/******************************************************************************/
+/******************** Bits definition for RNG_CR register *******************/
+#define RNG_CR_RNGEN 0x00000004U
+#define RNG_CR_IE 0x00000008U
+
+/******************** Bits definition for RNG_SR register *******************/
+#define RNG_SR_DRDY 0x00000001U
+#define RNG_SR_CECS 0x00000002U
+#define RNG_SR_SECS 0x00000004U
+#define RNG_SR_CEIS 0x00000020U
+#define RNG_SR_SEIS 0x00000040U
+
+/******************************************************************************/
+/* */
+/* Real-Time Clock (RTC) */
+/* */
+/******************************************************************************/
+/******************** Bits definition for RTC_TR register *******************/
+#define RTC_TR_PM 0x00400000U
+#define RTC_TR_HT 0x00300000U
+#define RTC_TR_HT_0 0x00100000U
+#define RTC_TR_HT_1 0x00200000U
+#define RTC_TR_HU 0x000F0000U
+#define RTC_TR_HU_0 0x00010000U
+#define RTC_TR_HU_1 0x00020000U
+#define RTC_TR_HU_2 0x00040000U
+#define RTC_TR_HU_3 0x00080000U
+#define RTC_TR_MNT 0x00007000U
+#define RTC_TR_MNT_0 0x00001000U
+#define RTC_TR_MNT_1 0x00002000U
+#define RTC_TR_MNT_2 0x00004000U
+#define RTC_TR_MNU 0x00000F00U
+#define RTC_TR_MNU_0 0x00000100U
+#define RTC_TR_MNU_1 0x00000200U
+#define RTC_TR_MNU_2 0x00000400U
+#define RTC_TR_MNU_3 0x00000800U
+#define RTC_TR_ST 0x00000070U
+#define RTC_TR_ST_0 0x00000010U
+#define RTC_TR_ST_1 0x00000020U
+#define RTC_TR_ST_2 0x00000040U
+#define RTC_TR_SU 0x0000000FU
+#define RTC_TR_SU_0 0x00000001U
+#define RTC_TR_SU_1 0x00000002U
+#define RTC_TR_SU_2 0x00000004U
+#define RTC_TR_SU_3 0x00000008U
+
+/******************** Bits definition for RTC_DR register *******************/
+#define RTC_DR_YT 0x00F00000U
+#define RTC_DR_YT_0 0x00100000U
+#define RTC_DR_YT_1 0x00200000U
+#define RTC_DR_YT_2 0x00400000U
+#define RTC_DR_YT_3 0x00800000U
+#define RTC_DR_YU 0x000F0000U
+#define RTC_DR_YU_0 0x00010000U
+#define RTC_DR_YU_1 0x00020000U
+#define RTC_DR_YU_2 0x00040000U
+#define RTC_DR_YU_3 0x00080000U
+#define RTC_DR_WDU 0x0000E000U
+#define RTC_DR_WDU_0 0x00002000U
+#define RTC_DR_WDU_1 0x00004000U
+#define RTC_DR_WDU_2 0x00008000U
+#define RTC_DR_MT 0x00001000U
+#define RTC_DR_MU 0x00000F00U
+#define RTC_DR_MU_0 0x00000100U
+#define RTC_DR_MU_1 0x00000200U
+#define RTC_DR_MU_2 0x00000400U
+#define RTC_DR_MU_3 0x00000800U
+#define RTC_DR_DT 0x00000030U
+#define RTC_DR_DT_0 0x00000010U
+#define RTC_DR_DT_1 0x00000020U
+#define RTC_DR_DU 0x0000000FU
+#define RTC_DR_DU_0 0x00000001U
+#define RTC_DR_DU_1 0x00000002U
+#define RTC_DR_DU_2 0x00000004U
+#define RTC_DR_DU_3 0x00000008U
+
+/******************** Bits definition for RTC_CR register *******************/
+#define RTC_CR_COE 0x00800000U
+#define RTC_CR_OSEL 0x00600000U
+#define RTC_CR_OSEL_0 0x00200000U
+#define RTC_CR_OSEL_1 0x00400000U
+#define RTC_CR_POL 0x00100000U
+#define RTC_CR_COSEL 0x00080000U
+#define RTC_CR_BCK 0x00040000U
+#define RTC_CR_SUB1H 0x00020000U
+#define RTC_CR_ADD1H 0x00010000U
+#define RTC_CR_TSIE 0x00008000U
+#define RTC_CR_WUTIE 0x00004000U
+#define RTC_CR_ALRBIE 0x00002000U
+#define RTC_CR_ALRAIE 0x00001000U
+#define RTC_CR_TSE 0x00000800U
+#define RTC_CR_WUTE 0x00000400U
+#define RTC_CR_ALRBE 0x00000200U
+#define RTC_CR_ALRAE 0x00000100U
+#define RTC_CR_DCE 0x00000080U
+#define RTC_CR_FMT 0x00000040U
+#define RTC_CR_BYPSHAD 0x00000020U
+#define RTC_CR_REFCKON 0x00000010U
+#define RTC_CR_TSEDGE 0x00000008U
+#define RTC_CR_WUCKSEL 0x00000007U
+#define RTC_CR_WUCKSEL_0 0x00000001U
+#define RTC_CR_WUCKSEL_1 0x00000002U
+#define RTC_CR_WUCKSEL_2 0x00000004U
+
+/******************** Bits definition for RTC_ISR register ******************/
+#define RTC_ISR_RECALPF 0x00010000U
+#define RTC_ISR_TAMP1F 0x00002000U
+#define RTC_ISR_TAMP2F 0x00004000U
+#define RTC_ISR_TSOVF 0x00001000U
+#define RTC_ISR_TSF 0x00000800U
+#define RTC_ISR_WUTF 0x00000400U
+#define RTC_ISR_ALRBF 0x00000200U
+#define RTC_ISR_ALRAF 0x00000100U
+#define RTC_ISR_INIT 0x00000080U
+#define RTC_ISR_INITF 0x00000040U
+#define RTC_ISR_RSF 0x00000020U
+#define RTC_ISR_INITS 0x00000010U
+#define RTC_ISR_SHPF 0x00000008U
+#define RTC_ISR_WUTWF 0x00000004U
+#define RTC_ISR_ALRBWF 0x00000002U
+#define RTC_ISR_ALRAWF 0x00000001U
+
+/******************** Bits definition for RTC_PRER register *****************/
+#define RTC_PRER_PREDIV_A 0x007F0000U
+#define RTC_PRER_PREDIV_S 0x00007FFFU
+
+/******************** Bits definition for RTC_WUTR register *****************/
+#define RTC_WUTR_WUT 0x0000FFFFU
+
+/******************** Bits definition for RTC_CALIBR register ***************/
+#define RTC_CALIBR_DCS 0x00000080U
+#define RTC_CALIBR_DC 0x0000001FU
+
+/******************** Bits definition for RTC_ALRMAR register ***************/
+#define RTC_ALRMAR_MSK4 0x80000000U
+#define RTC_ALRMAR_WDSEL 0x40000000U
+#define RTC_ALRMAR_DT 0x30000000U
+#define RTC_ALRMAR_DT_0 0x10000000U
+#define RTC_ALRMAR_DT_1 0x20000000U
+#define RTC_ALRMAR_DU 0x0F000000U
+#define RTC_ALRMAR_DU_0 0x01000000U
+#define RTC_ALRMAR_DU_1 0x02000000U
+#define RTC_ALRMAR_DU_2 0x04000000U
+#define RTC_ALRMAR_DU_3 0x08000000U
+#define RTC_ALRMAR_MSK3 0x00800000U
+#define RTC_ALRMAR_PM 0x00400000U
+#define RTC_ALRMAR_HT 0x00300000U
+#define RTC_ALRMAR_HT_0 0x00100000U
+#define RTC_ALRMAR_HT_1 0x00200000U
+#define RTC_ALRMAR_HU 0x000F0000U
+#define RTC_ALRMAR_HU_0 0x00010000U
+#define RTC_ALRMAR_HU_1 0x00020000U
+#define RTC_ALRMAR_HU_2 0x00040000U
+#define RTC_ALRMAR_HU_3 0x00080000U
+#define RTC_ALRMAR_MSK2 0x00008000U
+#define RTC_ALRMAR_MNT 0x00007000U
+#define RTC_ALRMAR_MNT_0 0x00001000U
+#define RTC_ALRMAR_MNT_1 0x00002000U
+#define RTC_ALRMAR_MNT_2 0x00004000U
+#define RTC_ALRMAR_MNU 0x00000F00U
+#define RTC_ALRMAR_MNU_0 0x00000100U
+#define RTC_ALRMAR_MNU_1 0x00000200U
+#define RTC_ALRMAR_MNU_2 0x00000400U
+#define RTC_ALRMAR_MNU_3 0x00000800U
+#define RTC_ALRMAR_MSK1 0x00000080U
+#define RTC_ALRMAR_ST 0x00000070U
+#define RTC_ALRMAR_ST_0 0x00000010U
+#define RTC_ALRMAR_ST_1 0x00000020U
+#define RTC_ALRMAR_ST_2 0x00000040U
+#define RTC_ALRMAR_SU 0x0000000FU
+#define RTC_ALRMAR_SU_0 0x00000001U
+#define RTC_ALRMAR_SU_1 0x00000002U
+#define RTC_ALRMAR_SU_2 0x00000004U
+#define RTC_ALRMAR_SU_3 0x00000008U
+
+/******************** Bits definition for RTC_ALRMBR register ***************/
+#define RTC_ALRMBR_MSK4 0x80000000U
+#define RTC_ALRMBR_WDSEL 0x40000000U
+#define RTC_ALRMBR_DT 0x30000000U
+#define RTC_ALRMBR_DT_0 0x10000000U
+#define RTC_ALRMBR_DT_1 0x20000000U
+#define RTC_ALRMBR_DU 0x0F000000U
+#define RTC_ALRMBR_DU_0 0x01000000U
+#define RTC_ALRMBR_DU_1 0x02000000U
+#define RTC_ALRMBR_DU_2 0x04000000U
+#define RTC_ALRMBR_DU_3 0x08000000U
+#define RTC_ALRMBR_MSK3 0x00800000U
+#define RTC_ALRMBR_PM 0x00400000U
+#define RTC_ALRMBR_HT 0x00300000U
+#define RTC_ALRMBR_HT_0 0x00100000U
+#define RTC_ALRMBR_HT_1 0x00200000U
+#define RTC_ALRMBR_HU 0x000F0000U
+#define RTC_ALRMBR_HU_0 0x00010000U
+#define RTC_ALRMBR_HU_1 0x00020000U
+#define RTC_ALRMBR_HU_2 0x00040000U
+#define RTC_ALRMBR_HU_3 0x00080000U
+#define RTC_ALRMBR_MSK2 0x00008000U
+#define RTC_ALRMBR_MNT 0x00007000U
+#define RTC_ALRMBR_MNT_0 0x00001000U
+#define RTC_ALRMBR_MNT_1 0x00002000U
+#define RTC_ALRMBR_MNT_2 0x00004000U
+#define RTC_ALRMBR_MNU 0x00000F00U
+#define RTC_ALRMBR_MNU_0 0x00000100U
+#define RTC_ALRMBR_MNU_1 0x00000200U
+#define RTC_ALRMBR_MNU_2 0x00000400U
+#define RTC_ALRMBR_MNU_3 0x00000800U
+#define RTC_ALRMBR_MSK1 0x00000080U
+#define RTC_ALRMBR_ST 0x00000070U
+#define RTC_ALRMBR_ST_0 0x00000010U
+#define RTC_ALRMBR_ST_1 0x00000020U
+#define RTC_ALRMBR_ST_2 0x00000040U
+#define RTC_ALRMBR_SU 0x0000000FU
+#define RTC_ALRMBR_SU_0 0x00000001U
+#define RTC_ALRMBR_SU_1 0x00000002U
+#define RTC_ALRMBR_SU_2 0x00000004U
+#define RTC_ALRMBR_SU_3 0x00000008U
+
+/******************** Bits definition for RTC_WPR register ******************/
+#define RTC_WPR_KEY 0x000000FFU
+
+/******************** Bits definition for RTC_SSR register ******************/
+#define RTC_SSR_SS 0x0000FFFFU
+
+/******************** Bits definition for RTC_SHIFTR register ***************/
+#define RTC_SHIFTR_SUBFS 0x00007FFFU
+#define RTC_SHIFTR_ADD1S 0x80000000U
+
+/******************** Bits definition for RTC_TSTR register *****************/
+#define RTC_TSTR_PM 0x00400000U
+#define RTC_TSTR_HT 0x00300000U
+#define RTC_TSTR_HT_0 0x00100000U
+#define RTC_TSTR_HT_1 0x00200000U
+#define RTC_TSTR_HU 0x000F0000U
+#define RTC_TSTR_HU_0 0x00010000U
+#define RTC_TSTR_HU_1 0x00020000U
+#define RTC_TSTR_HU_2 0x00040000U
+#define RTC_TSTR_HU_3 0x00080000U
+#define RTC_TSTR_MNT 0x00007000U
+#define RTC_TSTR_MNT_0 0x00001000U
+#define RTC_TSTR_MNT_1 0x00002000U
+#define RTC_TSTR_MNT_2 0x00004000U
+#define RTC_TSTR_MNU 0x00000F00U
+#define RTC_TSTR_MNU_0 0x00000100U
+#define RTC_TSTR_MNU_1 0x00000200U
+#define RTC_TSTR_MNU_2 0x00000400U
+#define RTC_TSTR_MNU_3 0x00000800U
+#define RTC_TSTR_ST 0x00000070U
+#define RTC_TSTR_ST_0 0x00000010U
+#define RTC_TSTR_ST_1 0x00000020U
+#define RTC_TSTR_ST_2 0x00000040U
+#define RTC_TSTR_SU 0x0000000FU
+#define RTC_TSTR_SU_0 0x00000001U
+#define RTC_TSTR_SU_1 0x00000002U
+#define RTC_TSTR_SU_2 0x00000004U
+#define RTC_TSTR_SU_3 0x00000008U
+
+/******************** Bits definition for RTC_TSDR register *****************/
+#define RTC_TSDR_WDU 0x0000E000U
+#define RTC_TSDR_WDU_0 0x00002000U
+#define RTC_TSDR_WDU_1 0x00004000U
+#define RTC_TSDR_WDU_2 0x00008000U
+#define RTC_TSDR_MT 0x00001000U
+#define RTC_TSDR_MU 0x00000F00U
+#define RTC_TSDR_MU_0 0x00000100U
+#define RTC_TSDR_MU_1 0x00000200U
+#define RTC_TSDR_MU_2 0x00000400U
+#define RTC_TSDR_MU_3 0x00000800U
+#define RTC_TSDR_DT 0x00000030U
+#define RTC_TSDR_DT_0 0x00000010U
+#define RTC_TSDR_DT_1 0x00000020U
+#define RTC_TSDR_DU 0x0000000FU
+#define RTC_TSDR_DU_0 0x00000001U
+#define RTC_TSDR_DU_1 0x00000002U
+#define RTC_TSDR_DU_2 0x00000004U
+#define RTC_TSDR_DU_3 0x00000008U
+
+/******************** Bits definition for RTC_TSSSR register ****************/
+#define RTC_TSSSR_SS 0x0000FFFFU
+
+/******************** Bits definition for RTC_CAL register *****************/
+#define RTC_CALR_CALP 0x00008000U
+#define RTC_CALR_CALW8 0x00004000U
+#define RTC_CALR_CALW16 0x00002000U
+#define RTC_CALR_CALM 0x000001FFU
+#define RTC_CALR_CALM_0 0x00000001U
+#define RTC_CALR_CALM_1 0x00000002U
+#define RTC_CALR_CALM_2 0x00000004U
+#define RTC_CALR_CALM_3 0x00000008U
+#define RTC_CALR_CALM_4 0x00000010U
+#define RTC_CALR_CALM_5 0x00000020U
+#define RTC_CALR_CALM_6 0x00000040U
+#define RTC_CALR_CALM_7 0x00000080U
+#define RTC_CALR_CALM_8 0x00000100U
+
+/******************** Bits definition for RTC_TAFCR register ****************/
+#define RTC_TAFCR_ALARMOUTTYPE 0x00040000U
+#define RTC_TAFCR_TSINSEL 0x00020000U
+#define RTC_TAFCR_TAMPINSEL 0x00010000U
+#define RTC_TAFCR_TAMPPUDIS 0x00008000U
+#define RTC_TAFCR_TAMPPRCH 0x00006000U
+#define RTC_TAFCR_TAMPPRCH_0 0x00002000U
+#define RTC_TAFCR_TAMPPRCH_1 0x00004000U
+#define RTC_TAFCR_TAMPFLT 0x00001800U
+#define RTC_TAFCR_TAMPFLT_0 0x00000800U
+#define RTC_TAFCR_TAMPFLT_1 0x00001000U
+#define RTC_TAFCR_TAMPFREQ 0x00000700U
+#define RTC_TAFCR_TAMPFREQ_0 0x00000100U
+#define RTC_TAFCR_TAMPFREQ_1 0x00000200U
+#define RTC_TAFCR_TAMPFREQ_2 0x00000400U
+#define RTC_TAFCR_TAMPTS 0x00000080U
+#define RTC_TAFCR_TAMP2TRG 0x00000010U
+#define RTC_TAFCR_TAMP2E 0x00000008U
+#define RTC_TAFCR_TAMPIE 0x00000004U
+#define RTC_TAFCR_TAMP1TRG 0x00000002U
+#define RTC_TAFCR_TAMP1E 0x00000001U
+
+/******************** Bits definition for RTC_ALRMASSR register *************/
+#define RTC_ALRMASSR_MASKSS 0x0F000000U
+#define RTC_ALRMASSR_MASKSS_0 0x01000000U
+#define RTC_ALRMASSR_MASKSS_1 0x02000000U
+#define RTC_ALRMASSR_MASKSS_2 0x04000000U
+#define RTC_ALRMASSR_MASKSS_3 0x08000000U
+#define RTC_ALRMASSR_SS 0x00007FFFU
+
+/******************** Bits definition for RTC_ALRMBSSR register *************/
+#define RTC_ALRMBSSR_MASKSS 0x0F000000U
+#define RTC_ALRMBSSR_MASKSS_0 0x01000000U
+#define RTC_ALRMBSSR_MASKSS_1 0x02000000U
+#define RTC_ALRMBSSR_MASKSS_2 0x04000000U
+#define RTC_ALRMBSSR_MASKSS_3 0x08000000U
+#define RTC_ALRMBSSR_SS 0x00007FFFU
+
+/******************** Bits definition for RTC_BKP0R register ****************/
+#define RTC_BKP0R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP1R register ****************/
+#define RTC_BKP1R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP2R register ****************/
+#define RTC_BKP2R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP3R register ****************/
+#define RTC_BKP3R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP4R register ****************/
+#define RTC_BKP4R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP5R register ****************/
+#define RTC_BKP5R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP6R register ****************/
+#define RTC_BKP6R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP7R register ****************/
+#define RTC_BKP7R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP8R register ****************/
+#define RTC_BKP8R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP9R register ****************/
+#define RTC_BKP9R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP10R register ***************/
+#define RTC_BKP10R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP11R register ***************/
+#define RTC_BKP11R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP12R register ***************/
+#define RTC_BKP12R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP13R register ***************/
+#define RTC_BKP13R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP14R register ***************/
+#define RTC_BKP14R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP15R register ***************/
+#define RTC_BKP15R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP16R register ***************/
+#define RTC_BKP16R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP17R register ***************/
+#define RTC_BKP17R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP18R register ***************/
+#define RTC_BKP18R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP19R register ***************/
+#define RTC_BKP19R 0xFFFFFFFFU
+
+
+
+/******************************************************************************/
+/* */
+/* SD host Interface */
+/* */
+/******************************************************************************/
+/****************** Bit definition for SDIO_POWER register ******************/
+#define SDIO_POWER_PWRCTRL 0x03U /*!<PWRCTRL[1:0] bits (Power supply control bits) */
+#define SDIO_POWER_PWRCTRL_0 0x01U /*!<Bit 0 */
+#define SDIO_POWER_PWRCTRL_1 0x02U /*!<Bit 1 */
+
+/****************** Bit definition for SDIO_CLKCR register ******************/
+#define SDIO_CLKCR_CLKDIV 0x00FFU /*!<Clock divide factor */
+#define SDIO_CLKCR_CLKEN 0x0100U /*!<Clock enable bit */
+#define SDIO_CLKCR_PWRSAV 0x0200U /*!<Power saving configuration bit */
+#define SDIO_CLKCR_BYPASS 0x0400U /*!<Clock divider bypass enable bit */
+
+#define SDIO_CLKCR_WIDBUS 0x1800U /*!<WIDBUS[1:0] bits (Wide bus mode enable bit) */
+#define SDIO_CLKCR_WIDBUS_0 0x0800U /*!<Bit 0 */
+#define SDIO_CLKCR_WIDBUS_1 0x1000U /*!<Bit 1 */
+
+#define SDIO_CLKCR_NEGEDGE 0x2000U /*!<SDIO_CK dephasing selection bit */
+#define SDIO_CLKCR_HWFC_EN 0x4000U /*!<HW Flow Control enable */
+
+/******************* Bit definition for SDIO_ARG register *******************/
+#define SDIO_ARG_CMDARG 0xFFFFFFFFU /*!<Command argument */
+
+/******************* Bit definition for SDIO_CMD register *******************/
+#define SDIO_CMD_CMDINDEX 0x003FU /*!<Command Index */
+
+#define SDIO_CMD_WAITRESP 0x00C0U /*!<WAITRESP[1:0] bits (Wait for response bits) */
+#define SDIO_CMD_WAITRESP_0 0x0040U /*!< Bit 0 */
+#define SDIO_CMD_WAITRESP_1 0x0080U /*!< Bit 1 */
+
+#define SDIO_CMD_WAITINT 0x0100U /*!<CPSM Waits for Interrupt Request */
+#define SDIO_CMD_WAITPEND 0x0200U /*!<CPSM Waits for ends of data transfer (CmdPend internal signal) */
+#define SDIO_CMD_CPSMEN 0x0400U /*!<Command path state machine (CPSM) Enable bit */
+#define SDIO_CMD_SDIOSUSPEND 0x0800U /*!<SD I/O suspend command */
+#define SDIO_CMD_ENCMDCOMPL 0x1000U /*!<Enable CMD completion */
+#define SDIO_CMD_NIEN 0x2000U /*!<Not Interrupt Enable */
+#define SDIO_CMD_CEATACMD 0x4000U /*!<CE-ATA command */
+
+/***************** Bit definition for SDIO_RESPCMD register *****************/
+#define SDIO_RESPCMD_RESPCMD 0x3FU /*!<Response command index */
+
+/****************** Bit definition for SDIO_RESP0 register ******************/
+#define SDIO_RESP0_CARDSTATUS0 0xFFFFFFFFU /*!<Card Status */
+
+/****************** Bit definition for SDIO_RESP1 register ******************/
+#define SDIO_RESP1_CARDSTATUS1 0xFFFFFFFFU /*!<Card Status */
+
+/****************** Bit definition for SDIO_RESP2 register ******************/
+#define SDIO_RESP2_CARDSTATUS2 0xFFFFFFFFU /*!<Card Status */
+
+/****************** Bit definition for SDIO_RESP3 register ******************/
+#define SDIO_RESP3_CARDSTATUS3 0xFFFFFFFFU /*!<Card Status */
+
+/****************** Bit definition for SDIO_RESP4 register ******************/
+#define SDIO_RESP4_CARDSTATUS4 0xFFFFFFFFU /*!<Card Status */
+
+/****************** Bit definition for SDIO_DTIMER register *****************/
+#define SDIO_DTIMER_DATATIME 0xFFFFFFFFU /*!<Data timeout period. */
+
+/****************** Bit definition for SDIO_DLEN register *******************/
+#define SDIO_DLEN_DATALENGTH 0x01FFFFFFU /*!<Data length value */
+
+/****************** Bit definition for SDIO_DCTRL register ******************/
+#define SDIO_DCTRL_DTEN 0x0001U /*!<Data transfer enabled bit */
+#define SDIO_DCTRL_DTDIR 0x0002U /*!<Data transfer direction selection */
+#define SDIO_DCTRL_DTMODE 0x0004U /*!<Data transfer mode selection */
+#define SDIO_DCTRL_DMAEN 0x0008U /*!<DMA enabled bit */
+
+#define SDIO_DCTRL_DBLOCKSIZE 0x00F0U /*!<DBLOCKSIZE[3:0] bits (Data block size) */
+#define SDIO_DCTRL_DBLOCKSIZE_0 0x0010U /*!<Bit 0 */
+#define SDIO_DCTRL_DBLOCKSIZE_1 0x0020U /*!<Bit 1 */
+#define SDIO_DCTRL_DBLOCKSIZE_2 0x0040U /*!<Bit 2 */
+#define SDIO_DCTRL_DBLOCKSIZE_3 0x0080U /*!<Bit 3 */
+
+#define SDIO_DCTRL_RWSTART 0x0100U /*!<Read wait start */
+#define SDIO_DCTRL_RWSTOP 0x0200U /*!<Read wait stop */
+#define SDIO_DCTRL_RWMOD 0x0400U /*!<Read wait mode */
+#define SDIO_DCTRL_SDIOEN 0x0800U /*!<SD I/O enable functions */
+
+/****************** Bit definition for SDIO_DCOUNT register *****************/
+#define SDIO_DCOUNT_DATACOUNT 0x01FFFFFFU /*!<Data count value */
+
+/****************** Bit definition for SDIO_STA register ********************/
+#define SDIO_STA_CCRCFAIL 0x00000001U /*!<Command response received (CRC check failed) */
+#define SDIO_STA_DCRCFAIL 0x00000002U /*!<Data block sent/received (CRC check failed) */
+#define SDIO_STA_CTIMEOUT 0x00000004U /*!<Command response timeout */
+#define SDIO_STA_DTIMEOUT 0x00000008U /*!<Data timeout */
+#define SDIO_STA_TXUNDERR 0x00000010U /*!<Transmit FIFO underrun error */
+#define SDIO_STA_RXOVERR 0x00000020U /*!<Received FIFO overrun error */
+#define SDIO_STA_CMDREND 0x00000040U /*!<Command response received (CRC check passed) */
+#define SDIO_STA_CMDSENT 0x00000080U /*!<Command sent (no response required) */
+#define SDIO_STA_DATAEND 0x00000100U /*!<Data end (data counter, SDIDCOUNT, is zero) */
+#define SDIO_STA_STBITERR 0x00000200U /*!<Start bit not detected on all data signals in wide bus mode */
+#define SDIO_STA_DBCKEND 0x00000400U /*!<Data block sent/received (CRC check passed) */
+#define SDIO_STA_CMDACT 0x00000800U /*!<Command transfer in progress */
+#define SDIO_STA_TXACT 0x00001000U /*!<Data transmit in progress */
+#define SDIO_STA_RXACT 0x00002000U /*!<Data receive in progress */
+#define SDIO_STA_TXFIFOHE 0x00004000U /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
+#define SDIO_STA_RXFIFOHF 0x00008000U /*!<Receive FIFO Half Full: there are at least 8 words in the FIFO */
+#define SDIO_STA_TXFIFOF 0x00010000U /*!<Transmit FIFO full */
+#define SDIO_STA_RXFIFOF 0x00020000U /*!<Receive FIFO full */
+#define SDIO_STA_TXFIFOE 0x00040000U /*!<Transmit FIFO empty */
+#define SDIO_STA_RXFIFOE 0x00080000U /*!<Receive FIFO empty */
+#define SDIO_STA_TXDAVL 0x00100000U /*!<Data available in transmit FIFO */
+#define SDIO_STA_RXDAVL 0x00200000U /*!<Data available in receive FIFO */
+#define SDIO_STA_SDIOIT 0x00400000U /*!<SDIO interrupt received */
+#define SDIO_STA_CEATAEND 0x00800000U /*!<CE-ATA command completion signal received for CMD61 */
+
+/******************* Bit definition for SDIO_ICR register *******************/
+#define SDIO_ICR_CCRCFAILC 0x00000001U /*!<CCRCFAIL flag clear bit */
+#define SDIO_ICR_DCRCFAILC 0x00000002U /*!<DCRCFAIL flag clear bit */
+#define SDIO_ICR_CTIMEOUTC 0x00000004U /*!<CTIMEOUT flag clear bit */
+#define SDIO_ICR_DTIMEOUTC 0x00000008U /*!<DTIMEOUT flag clear bit */
+#define SDIO_ICR_TXUNDERRC 0x00000010U /*!<TXUNDERR flag clear bit */
+#define SDIO_ICR_RXOVERRC 0x00000020U /*!<RXOVERR flag clear bit */
+#define SDIO_ICR_CMDRENDC 0x00000040U /*!<CMDREND flag clear bit */
+#define SDIO_ICR_CMDSENTC 0x00000080U /*!<CMDSENT flag clear bit */
+#define SDIO_ICR_DATAENDC 0x00000100U /*!<DATAEND flag clear bit */
+#define SDIO_ICR_STBITERRC 0x00000200U /*!<STBITERR flag clear bit */
+#define SDIO_ICR_DBCKENDC 0x00000400U /*!<DBCKEND flag clear bit */
+#define SDIO_ICR_SDIOITC 0x00400000U /*!<SDIOIT flag clear bit */
+#define SDIO_ICR_CEATAENDC 0x00800000U /*!<CEATAEND flag clear bit */
+
+/****************** Bit definition for SDIO_MASK register *******************/
+#define SDIO_MASK_CCRCFAILIE 0x00000001U /*!<Command CRC Fail Interrupt Enable */
+#define SDIO_MASK_DCRCFAILIE 0x00000002U /*!<Data CRC Fail Interrupt Enable */
+#define SDIO_MASK_CTIMEOUTIE 0x00000004U /*!<Command TimeOut Interrupt Enable */
+#define SDIO_MASK_DTIMEOUTIE 0x00000008U /*!<Data TimeOut Interrupt Enable */
+#define SDIO_MASK_TXUNDERRIE 0x00000010U /*!<Tx FIFO UnderRun Error Interrupt Enable */
+#define SDIO_MASK_RXOVERRIE 0x00000020U /*!<Rx FIFO OverRun Error Interrupt Enable */
+#define SDIO_MASK_CMDRENDIE 0x00000040U /*!<Command Response Received Interrupt Enable */
+#define SDIO_MASK_CMDSENTIE 0x00000080U /*!<Command Sent Interrupt Enable */
+#define SDIO_MASK_DATAENDIE 0x00000100U /*!<Data End Interrupt Enable */
+#define SDIO_MASK_STBITERRIE 0x00000200U /*!<Start Bit Error Interrupt Enable */
+#define SDIO_MASK_DBCKENDIE 0x00000400U /*!<Data Block End Interrupt Enable */
+#define SDIO_MASK_CMDACTIE 0x00000800U /*!<CCommand Acting Interrupt Enable */
+#define SDIO_MASK_TXACTIE 0x00001000U /*!<Data Transmit Acting Interrupt Enable */
+#define SDIO_MASK_RXACTIE 0x00002000U /*!<Data receive acting interrupt enabled */
+#define SDIO_MASK_TXFIFOHEIE 0x00004000U /*!<Tx FIFO Half Empty interrupt Enable */
+#define SDIO_MASK_RXFIFOHFIE 0x00008000U /*!<Rx FIFO Half Full interrupt Enable */
+#define SDIO_MASK_TXFIFOFIE 0x00010000U /*!<Tx FIFO Full interrupt Enable */
+#define SDIO_MASK_RXFIFOFIE 0x00020000U /*!<Rx FIFO Full interrupt Enable */
+#define SDIO_MASK_TXFIFOEIE 0x00040000U /*!<Tx FIFO Empty interrupt Enable */
+#define SDIO_MASK_RXFIFOEIE 0x00080000U /*!<Rx FIFO Empty interrupt Enable */
+#define SDIO_MASK_TXDAVLIE 0x00100000U /*!<Data available in Tx FIFO interrupt Enable */
+#define SDIO_MASK_RXDAVLIE 0x00200000U /*!<Data available in Rx FIFO interrupt Enable */
+#define SDIO_MASK_SDIOITIE 0x00400000U /*!<SDIO Mode Interrupt Received interrupt Enable */
+#define SDIO_MASK_CEATAENDIE 0x00800000U /*!<CE-ATA command completion signal received Interrupt Enable */
+
+/***************** Bit definition for SDIO_FIFOCNT register *****************/
+#define SDIO_FIFOCNT_FIFOCOUNT 0x00FFFFFFU /*!<Remaining number of words to be written to or read from the FIFO */
+
+/****************** Bit definition for SDIO_FIFO register *******************/
+#define SDIO_FIFO_FIFODATA 0xFFFFFFFFU /*!<Receive and transmit FIFO data */
+
+/******************************************************************************/
+/* */
+/* Serial Peripheral Interface */
+/* */
+/******************************************************************************/
+/******************* Bit definition for SPI_CR1 register ********************/
+#define SPI_CR1_CPHA 0x00000001U /*!<Clock Phase */
+#define SPI_CR1_CPOL 0x00000002U /*!<Clock Polarity */
+#define SPI_CR1_MSTR 0x00000004U /*!<Master Selection */
+
+#define SPI_CR1_BR 0x00000038U /*!<BR[2:0] bits (Baud Rate Control) */
+#define SPI_CR1_BR_0 0x00000008U /*!<Bit 0 */
+#define SPI_CR1_BR_1 0x00000010U /*!<Bit 1 */
+#define SPI_CR1_BR_2 0x00000020U /*!<Bit 2 */
+
+#define SPI_CR1_SPE 0x00000040U /*!<SPI Enable */
+#define SPI_CR1_LSBFIRST 0x00000080U /*!<Frame Format */
+#define SPI_CR1_SSI 0x00000100U /*!<Internal slave select */
+#define SPI_CR1_SSM 0x00000200U /*!<Software slave management */
+#define SPI_CR1_RXONLY 0x00000400U /*!<Receive only */
+#define SPI_CR1_DFF 0x00000800U /*!<Data Frame Format */
+#define SPI_CR1_CRCNEXT 0x00001000U /*!<Transmit CRC next */
+#define SPI_CR1_CRCEN 0x00002000U /*!<Hardware CRC calculation enable */
+#define SPI_CR1_BIDIOE 0x00004000U /*!<Output enable in bidirectional mode */
+#define SPI_CR1_BIDIMODE 0x00008000U /*!<Bidirectional data mode enable */
+
+/******************* Bit definition for SPI_CR2 register ********************/
+#define SPI_CR2_RXDMAEN 0x00000001U /*!<Rx Buffer DMA Enable */
+#define SPI_CR2_TXDMAEN 0x00000002U /*!<Tx Buffer DMA Enable */
+#define SPI_CR2_SSOE 0x00000004U /*!<SS Output Enable */
+#define SPI_CR2_FRF 0x00000010U /*!<Frame Format */
+#define SPI_CR2_ERRIE 0x00000020U /*!<Error Interrupt Enable */
+#define SPI_CR2_RXNEIE 0x00000040U /*!<RX buffer Not Empty Interrupt Enable */
+#define SPI_CR2_TXEIE 0x00000080U /*!<Tx buffer Empty Interrupt Enable */
+
+/******************** Bit definition for SPI_SR register ********************/
+#define SPI_SR_RXNE 0x00000001U /*!<Receive buffer Not Empty */
+#define SPI_SR_TXE 0x00000002U /*!<Transmit buffer Empty */
+#define SPI_SR_CHSIDE 0x00000004U /*!<Channel side */
+#define SPI_SR_UDR 0x00000008U /*!<Underrun flag */
+#define SPI_SR_CRCERR 0x00000010U /*!<CRC Error flag */
+#define SPI_SR_MODF 0x00000020U /*!<Mode fault */
+#define SPI_SR_OVR 0x00000040U /*!<Overrun flag */
+#define SPI_SR_BSY 0x00000080U /*!<Busy flag */
+#define SPI_SR_FRE 0x00000100U /*!<Frame format error flag */
+
+/******************** Bit definition for SPI_DR register ********************/
+#define SPI_DR_DR 0x0000FFFFU /*!<Data Register */
+
+/******************* Bit definition for SPI_CRCPR register ******************/
+#define SPI_CRCPR_CRCPOLY 0x0000FFFFU /*!<CRC polynomial register */
+
+/****************** Bit definition for SPI_RXCRCR register ******************/
+#define SPI_RXCRCR_RXCRC 0x0000FFFFU /*!<Rx CRC Register */
+
+/****************** Bit definition for SPI_TXCRCR register ******************/
+#define SPI_TXCRCR_TXCRC 0x0000FFFFU /*!<Tx CRC Register */
+
+/****************** Bit definition for SPI_I2SCFGR register *****************/
+#define SPI_I2SCFGR_CHLEN 0x00000001U /*!<Channel length (number of bits per audio channel) */
+
+#define SPI_I2SCFGR_DATLEN 0x00000006U /*!<DATLEN[1:0] bits (Data length to be transferred) */
+#define SPI_I2SCFGR_DATLEN_0 0x00000002U /*!<Bit 0 */
+#define SPI_I2SCFGR_DATLEN_1 0x00000004U /*!<Bit 1 */
+
+#define SPI_I2SCFGR_CKPOL 0x00000008U /*!<steady state clock polarity */
+
+#define SPI_I2SCFGR_I2SSTD 0x00000030U /*!<I2SSTD[1:0] bits (I2S standard selection) */
+#define SPI_I2SCFGR_I2SSTD_0 0x00000010U /*!<Bit 0 */
+#define SPI_I2SCFGR_I2SSTD_1 0x00000020U /*!<Bit 1 */
+
+#define SPI_I2SCFGR_PCMSYNC 0x00000080U /*!<PCM frame synchronization */
+
+#define SPI_I2SCFGR_I2SCFG 0x00000300U /*!<I2SCFG[1:0] bits (I2S configuration mode) */
+#define SPI_I2SCFGR_I2SCFG_0 0x00000100U /*!<Bit 0 */
+#define SPI_I2SCFGR_I2SCFG_1 0x00000200U /*!<Bit 1 */
+
+#define SPI_I2SCFGR_I2SE 0x00000400U /*!<I2S Enable */
+#define SPI_I2SCFGR_I2SMOD 0x00000800U /*!<I2S mode selection */
+
+/****************** Bit definition for SPI_I2SPR register *******************/
+#define SPI_I2SPR_I2SDIV 0x000000FFU /*!<I2S Linear prescaler */
+#define SPI_I2SPR_ODD 0x00000100U /*!<Odd factor for the prescaler */
+#define SPI_I2SPR_MCKOE 0x00000200U /*!<Master Clock Output Enable */
+
+/******************************************************************************/
+/* */
+/* SYSCFG */
+/* */
+/******************************************************************************/
+/****************** Bit definition for SYSCFG_MEMRMP register ***************/
+#define SYSCFG_MEMRMP_MEM_MODE 0x00000007U /*!< SYSCFG_Memory Remap Config */
+#define SYSCFG_MEMRMP_MEM_MODE_0 0x00000001U
+#define SYSCFG_MEMRMP_MEM_MODE_1 0x00000002U
+#define SYSCFG_MEMRMP_MEM_MODE_2 0x00000004U
+
+/****************** Bit definition for SYSCFG_PMC register ******************/
+#define SYSCFG_PMC_MII_RMII_SEL 0x00800000U /*!<Ethernet PHY interface selection */
+/* Old MII_RMII_SEL bit definition, maintained for legacy purpose */
+#define SYSCFG_PMC_MII_RMII SYSCFG_PMC_MII_RMII_SEL
+
+/***************** Bit definition for SYSCFG_EXTICR1 register ***************/
+#define SYSCFG_EXTICR1_EXTI0 0x000FU /*!<EXTI 0 configuration */
+#define SYSCFG_EXTICR1_EXTI1 0x00F0U /*!<EXTI 1 configuration */
+#define SYSCFG_EXTICR1_EXTI2 0x0F00U /*!<EXTI 2 configuration */
+#define SYSCFG_EXTICR1_EXTI3 0xF000U /*!<EXTI 3 configuration */
+/**
+ * @brief EXTI0 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI0_PA 0x0000U /*!<PA[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PB 0x0001U /*!<PB[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PC 0x0002U /*!<PC[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PD 0x0003U /*!<PD[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PE 0x0004U /*!<PE[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PF 0x0005U /*!<PF[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PG 0x0006U /*!<PG[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PH 0x0007U /*!<PH[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PI 0x0008U /*!<PI[0] pin */
+
+/**
+ * @brief EXTI1 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI1_PA 0x0000U /*!<PA[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PB 0x0010U /*!<PB[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PC 0x0020U /*!<PC[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PD 0x0030U /*!<PD[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PE 0x0040U /*!<PE[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PF 0x0050U /*!<PF[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PG 0x0060U /*!<PG[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PH 0x0070U /*!<PH[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PI 0x0080U /*!<PI[1] pin */
+
+/**
+ * @brief EXTI2 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI2_PA 0x0000U /*!<PA[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PB 0x0100U /*!<PB[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PC 0x0200U /*!<PC[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PD 0x0300U /*!<PD[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PE 0x0400U /*!<PE[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PF 0x0500U /*!<PF[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PG 0x0600U /*!<PG[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PH 0x0700U /*!<PH[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PI 0x0800U /*!<PI[2] pin */
+
+/**
+ * @brief EXTI3 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI3_PA 0x0000U /*!<PA[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PB 0x1000U /*!<PB[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PC 0x2000U /*!<PC[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PD 0x3000U /*!<PD[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PE 0x4000U /*!<PE[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PF 0x5000U /*!<PF[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PG 0x6000U /*!<PG[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PH 0x7000U /*!<PH[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PI 0x8000U /*!<PI[3] pin */
+
+/***************** Bit definition for SYSCFG_EXTICR2 register ***************/
+#define SYSCFG_EXTICR2_EXTI4 0x000FU /*!<EXTI 4 configuration */
+#define SYSCFG_EXTICR2_EXTI5 0x00F0U /*!<EXTI 5 configuration */
+#define SYSCFG_EXTICR2_EXTI6 0x0F00U /*!<EXTI 6 configuration */
+#define SYSCFG_EXTICR2_EXTI7 0xF000U /*!<EXTI 7 configuration */
+/**
+ * @brief EXTI4 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI4_PA 0x0000U /*!<PA[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PB 0x0001U /*!<PB[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PC 0x0002U /*!<PC[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PD 0x0003U /*!<PD[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PE 0x0004U /*!<PE[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PF 0x0005U /*!<PF[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PG 0x0006U /*!<PG[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PH 0x0007U /*!<PH[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PI 0x0008U /*!<PI[4] pin */
+
+/**
+ * @brief EXTI5 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI5_PA 0x0000U /*!<PA[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PB 0x0010U /*!<PB[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PC 0x0020U /*!<PC[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PD 0x0030U /*!<PD[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PE 0x0040U /*!<PE[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PF 0x0050U /*!<PF[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PG 0x0060U /*!<PG[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PH 0x0070U /*!<PH[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PI 0x0080U /*!<PI[5] pin */
+
+/**
+ * @brief EXTI6 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI6_PA 0x0000U /*!<PA[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PB 0x0100U /*!<PB[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PC 0x0200U /*!<PC[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PD 0x0300U /*!<PD[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PE 0x0400U /*!<PE[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PF 0x0500U /*!<PF[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PG 0x0600U /*!<PG[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PH 0x0700U /*!<PH[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PI 0x0800U /*!<PI[6] pin */
+
+/**
+ * @brief EXTI7 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI7_PA 0x0000U /*!<PA[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PB 0x1000U /*!<PB[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PC 0x2000U /*!<PC[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PD 0x3000U /*!<PD[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PE 0x4000U /*!<PE[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PF 0x5000U /*!<PF[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PG 0x6000U /*!<PG[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PH 0x7000U /*!<PH[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PI 0x8000U /*!<PI[7] pin */
+
+
+/***************** Bit definition for SYSCFG_EXTICR3 register ***************/
+#define SYSCFG_EXTICR3_EXTI8 0x000FU /*!<EXTI 8 configuration */
+#define SYSCFG_EXTICR3_EXTI9 0x00F0U /*!<EXTI 9 configuration */
+#define SYSCFG_EXTICR3_EXTI10 0x0F00U /*!<EXTI 10 configuration */
+#define SYSCFG_EXTICR3_EXTI11 0xF000U /*!<EXTI 11 configuration */
+
+/**
+ * @brief EXTI8 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI8_PA 0x0000U /*!<PA[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PB 0x0001U /*!<PB[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PC 0x0002U /*!<PC[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PD 0x0003U /*!<PD[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PE 0x0004U /*!<PE[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PF 0x0005U /*!<PF[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PG 0x0006U /*!<PG[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PH 0x0007U /*!<PH[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PI 0x0008U /*!<PI[8] pin */
+
+/**
+ * @brief EXTI9 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI9_PA 0x0000U /*!<PA[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PB 0x0010U /*!<PB[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PC 0x0020U /*!<PC[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PD 0x0030U /*!<PD[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PE 0x0040U /*!<PE[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PF 0x0050U /*!<PF[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PG 0x0060U /*!<PG[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PH 0x0070U /*!<PH[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PI 0x0080U /*!<PI[9] pin */
+
+/**
+ * @brief EXTI10 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI10_PA 0x0000U /*!<PA[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PB 0x0100U /*!<PB[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PC 0x0200U /*!<PC[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PD 0x0300U /*!<PD[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PE 0x0400U /*!<PE[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PF 0x0500U /*!<PF[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PG 0x0600U /*!<PG[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PH 0x0700U /*!<PH[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PI 0x0800U /*!<PI[10] pin */
+
+/**
+ * @brief EXTI11 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI11_PA 0x0000U /*!<PA[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PB 0x1000U /*!<PB[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PC 0x2000U /*!<PC[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PD 0x3000U /*!<PD[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PE 0x4000U /*!<PE[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PF 0x5000U /*!<PF[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PG 0x6000U /*!<PG[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PH 0x7000U /*!<PH[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PI 0x8000U /*!<PI[11] pin */
+
+/***************** Bit definition for SYSCFG_EXTICR4 register ***************/
+#define SYSCFG_EXTICR4_EXTI12 0x000FU /*!<EXTI 12 configuration */
+#define SYSCFG_EXTICR4_EXTI13 0x00F0U /*!<EXTI 13 configuration */
+#define SYSCFG_EXTICR4_EXTI14 0x0F00U /*!<EXTI 14 configuration */
+#define SYSCFG_EXTICR4_EXTI15 0xF000U /*!<EXTI 15 configuration */
+/**
+ * @brief EXTI12 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI12_PA 0x0000U /*!<PA[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PB 0x0001U /*!<PB[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PC 0x0002U /*!<PC[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PD 0x0003U /*!<PD[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PE 0x0004U /*!<PE[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PF 0x0005U /*!<PF[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PG 0x0006U /*!<PG[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PH 0x0007U /*!<PH[12] pin */
+
+/**
+ * @brief EXTI13 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI13_PA 0x0000U /*!<PA[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PB 0x0010U /*!<PB[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PC 0x0020U /*!<PC[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PD 0x0030U /*!<PD[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PE 0x0040U /*!<PE[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PF 0x0050U /*!<PF[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PG 0x0060U /*!<PG[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PH 0x0070U /*!<PH[13] pin */
+
+/**
+ * @brief EXTI14 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI14_PA 0x0000U /*!<PA[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PB 0x0100U /*!<PB[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PC 0x0200U /*!<PC[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PD 0x0300U /*!<PD[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PE 0x0400U /*!<PE[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PF 0x0500U /*!<PF[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PG 0x0600U /*!<PG[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PH 0x0700U /*!<PH[14] pin */
+
+/**
+ * @brief EXTI15 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI15_PA 0x0000U /*!<PA[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PB 0x1000U /*!<PB[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PC 0x2000U /*!<PC[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PD 0x3000U /*!<PD[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PE 0x4000U /*!<PE[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PF 0x5000U /*!<PF[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PG 0x6000U /*!<PG[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PH 0x7000U /*!<PH[15] pin */
+
+/****************** Bit definition for SYSCFG_CMPCR register ****************/
+#define SYSCFG_CMPCR_CMP_PD 0x00000001U /*!<Compensation cell ready flag */
+#define SYSCFG_CMPCR_READY 0x00000100U /*!<Compensation cell power-down */
+
+/******************************************************************************/
+/* */
+/* TIM */
+/* */
+/******************************************************************************/
+/******************* Bit definition for TIM_CR1 register ********************/
+#define TIM_CR1_CEN 0x0001U /*!<Counter enable */
+#define TIM_CR1_UDIS 0x0002U /*!<Update disable */
+#define TIM_CR1_URS 0x0004U /*!<Update request source */
+#define TIM_CR1_OPM 0x0008U /*!<One pulse mode */
+#define TIM_CR1_DIR 0x0010U /*!<Direction */
+
+#define TIM_CR1_CMS 0x0060U /*!<CMS[1:0] bits (Center-aligned mode selection) */
+#define TIM_CR1_CMS_0 0x0020U /*!<Bit 0 */
+#define TIM_CR1_CMS_1 0x0040U /*!<Bit 1 */
+
+#define TIM_CR1_ARPE 0x0080U /*!<Auto-reload preload enable */
+
+#define TIM_CR1_CKD 0x0300U /*!<CKD[1:0] bits (clock division) */
+#define TIM_CR1_CKD_0 0x0100U /*!<Bit 0 */
+#define TIM_CR1_CKD_1 0x0200U /*!<Bit 1 */
+
+/******************* Bit definition for TIM_CR2 register ********************/
+#define TIM_CR2_CCPC 0x0001U /*!<Capture/Compare Preloaded Control */
+#define TIM_CR2_CCUS 0x0004U /*!<Capture/Compare Control Update Selection */
+#define TIM_CR2_CCDS 0x0008U /*!<Capture/Compare DMA Selection */
+
+#define TIM_CR2_MMS 0x0070U /*!<MMS[2:0] bits (Master Mode Selection) */
+#define TIM_CR2_MMS_0 0x0010U /*!<Bit 0 */
+#define TIM_CR2_MMS_1 0x0020U /*!<Bit 1 */
+#define TIM_CR2_MMS_2 0x0040U /*!<Bit 2 */
+
+#define TIM_CR2_TI1S 0x0080U /*!<TI1 Selection */
+#define TIM_CR2_OIS1 0x0100U /*!<Output Idle state 1 (OC1 output) */
+#define TIM_CR2_OIS1N 0x0200U /*!<Output Idle state 1 (OC1N output) */
+#define TIM_CR2_OIS2 0x0400U /*!<Output Idle state 2 (OC2 output) */
+#define TIM_CR2_OIS2N 0x0800U /*!<Output Idle state 2 (OC2N output) */
+#define TIM_CR2_OIS3 0x1000U /*!<Output Idle state 3 (OC3 output) */
+#define TIM_CR2_OIS3N 0x2000U /*!<Output Idle state 3 (OC3N output) */
+#define TIM_CR2_OIS4 0x4000U /*!<Output Idle state 4 (OC4 output) */
+
+/******************* Bit definition for TIM_SMCR register *******************/
+#define TIM_SMCR_SMS 0x0007U /*!<SMS[2:0] bits (Slave mode selection) */
+#define TIM_SMCR_SMS_0 0x0001U /*!<Bit 0 */
+#define TIM_SMCR_SMS_1 0x0002U /*!<Bit 1 */
+#define TIM_SMCR_SMS_2 0x0004U /*!<Bit 2 */
+
+#define TIM_SMCR_TS 0x0070U /*!<TS[2:0] bits (Trigger selection) */
+#define TIM_SMCR_TS_0 0x0010U /*!<Bit 0 */
+#define TIM_SMCR_TS_1 0x0020U /*!<Bit 1 */
+#define TIM_SMCR_TS_2 0x0040U /*!<Bit 2 */
+
+#define TIM_SMCR_MSM 0x0080U /*!<Master/slave mode */
+
+#define TIM_SMCR_ETF 0x0F00U /*!<ETF[3:0] bits (External trigger filter) */
+#define TIM_SMCR_ETF_0 0x0100U /*!<Bit 0 */
+#define TIM_SMCR_ETF_1 0x0200U /*!<Bit 1 */
+#define TIM_SMCR_ETF_2 0x0400U /*!<Bit 2 */
+#define TIM_SMCR_ETF_3 0x0800U /*!<Bit 3 */
+
+#define TIM_SMCR_ETPS 0x3000U /*!<ETPS[1:0] bits (External trigger prescaler) */
+#define TIM_SMCR_ETPS_0 0x1000U /*!<Bit 0 */
+#define TIM_SMCR_ETPS_1 0x2000U /*!<Bit 1 */
+
+#define TIM_SMCR_ECE 0x4000U /*!<External clock enable */
+#define TIM_SMCR_ETP 0x8000U /*!<External trigger polarity */
+
+/******************* Bit definition for TIM_DIER register *******************/
+#define TIM_DIER_UIE 0x0001U /*!<Update interrupt enable */
+#define TIM_DIER_CC1IE 0x0002U /*!<Capture/Compare 1 interrupt enable */
+#define TIM_DIER_CC2IE 0x0004U /*!<Capture/Compare 2 interrupt enable */
+#define TIM_DIER_CC3IE 0x0008U /*!<Capture/Compare 3 interrupt enable */
+#define TIM_DIER_CC4IE 0x0010U /*!<Capture/Compare 4 interrupt enable */
+#define TIM_DIER_COMIE 0x0020U /*!<COM interrupt enable */
+#define TIM_DIER_TIE 0x0040U /*!<Trigger interrupt enable */
+#define TIM_DIER_BIE 0x0080U /*!<Break interrupt enable */
+#define TIM_DIER_UDE 0x0100U /*!<Update DMA request enable */
+#define TIM_DIER_CC1DE 0x0200U /*!<Capture/Compare 1 DMA request enable */
+#define TIM_DIER_CC2DE 0x0400U /*!<Capture/Compare 2 DMA request enable */
+#define TIM_DIER_CC3DE 0x0800U /*!<Capture/Compare 3 DMA request enable */
+#define TIM_DIER_CC4DE 0x1000U /*!<Capture/Compare 4 DMA request enable */
+#define TIM_DIER_COMDE 0x2000U /*!<COM DMA request enable */
+#define TIM_DIER_TDE 0x4000U /*!<Trigger DMA request enable */
+
+/******************** Bit definition for TIM_SR register ********************/
+#define TIM_SR_UIF 0x0001U /*!<Update interrupt Flag */
+#define TIM_SR_CC1IF 0x0002U /*!<Capture/Compare 1 interrupt Flag */
+#define TIM_SR_CC2IF 0x0004U /*!<Capture/Compare 2 interrupt Flag */
+#define TIM_SR_CC3IF 0x0008U /*!<Capture/Compare 3 interrupt Flag */
+#define TIM_SR_CC4IF 0x0010U /*!<Capture/Compare 4 interrupt Flag */
+#define TIM_SR_COMIF 0x0020U /*!<COM interrupt Flag */
+#define TIM_SR_TIF 0x0040U /*!<Trigger interrupt Flag */
+#define TIM_SR_BIF 0x0080U /*!<Break interrupt Flag */
+#define TIM_SR_CC1OF 0x0200U /*!<Capture/Compare 1 Overcapture Flag */
+#define TIM_SR_CC2OF 0x0400U /*!<Capture/Compare 2 Overcapture Flag */
+#define TIM_SR_CC3OF 0x0800U /*!<Capture/Compare 3 Overcapture Flag */
+#define TIM_SR_CC4OF 0x1000U /*!<Capture/Compare 4 Overcapture Flag */
+
+/******************* Bit definition for TIM_EGR register ********************/
+#define TIM_EGR_UG 0x01U /*!<Update Generation */
+#define TIM_EGR_CC1G 0x02U /*!<Capture/Compare 1 Generation */
+#define TIM_EGR_CC2G 0x04U /*!<Capture/Compare 2 Generation */
+#define TIM_EGR_CC3G 0x08U /*!<Capture/Compare 3 Generation */
+#define TIM_EGR_CC4G 0x10U /*!<Capture/Compare 4 Generation */
+#define TIM_EGR_COMG 0x20U /*!<Capture/Compare Control Update Generation */
+#define TIM_EGR_TG 0x40U /*!<Trigger Generation */
+#define TIM_EGR_BG 0x80U /*!<Break Generation */
+
+/****************** Bit definition for TIM_CCMR1 register *******************/
+#define TIM_CCMR1_CC1S 0x0003U /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
+#define TIM_CCMR1_CC1S_0 0x0001U /*!<Bit 0 */
+#define TIM_CCMR1_CC1S_1 0x0002U /*!<Bit 1 */
+
+#define TIM_CCMR1_OC1FE 0x0004U /*!<Output Compare 1 Fast enable */
+#define TIM_CCMR1_OC1PE 0x0008U /*!<Output Compare 1 Preload enable */
+
+#define TIM_CCMR1_OC1M 0x0070U /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
+#define TIM_CCMR1_OC1M_0 0x0010U /*!<Bit 0 */
+#define TIM_CCMR1_OC1M_1 0x0020U /*!<Bit 1 */
+#define TIM_CCMR1_OC1M_2 0x0040U /*!<Bit 2 */
+
+#define TIM_CCMR1_OC1CE 0x0080U /*!<Output Compare 1Clear Enable */
+
+#define TIM_CCMR1_CC2S 0x0300U /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
+#define TIM_CCMR1_CC2S_0 0x0100U /*!<Bit 0 */
+#define TIM_CCMR1_CC2S_1 0x0200U /*!<Bit 1 */
+
+#define TIM_CCMR1_OC2FE 0x0400U /*!<Output Compare 2 Fast enable */
+#define TIM_CCMR1_OC2PE 0x0800U /*!<Output Compare 2 Preload enable */
+
+#define TIM_CCMR1_OC2M 0x7000U /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
+#define TIM_CCMR1_OC2M_0 0x1000U /*!<Bit 0 */
+#define TIM_CCMR1_OC2M_1 0x2000U /*!<Bit 1 */
+#define TIM_CCMR1_OC2M_2 0x4000U /*!<Bit 2 */
+
+#define TIM_CCMR1_OC2CE 0x8000U /*!<Output Compare 2 Clear Enable */
+
+/*----------------------------------------------------------------------------*/
+
+#define TIM_CCMR1_IC1PSC 0x000CU /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
+#define TIM_CCMR1_IC1PSC_0 0x0004U /*!<Bit 0 */
+#define TIM_CCMR1_IC1PSC_1 0x0008U /*!<Bit 1 */
+
+#define TIM_CCMR1_IC1F 0x00F0U /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
+#define TIM_CCMR1_IC1F_0 0x0010U /*!<Bit 0 */
+#define TIM_CCMR1_IC1F_1 0x0020U /*!<Bit 1 */
+#define TIM_CCMR1_IC1F_2 0x0040U /*!<Bit 2 */
+#define TIM_CCMR1_IC1F_3 0x0080U /*!<Bit 3 */
+
+#define TIM_CCMR1_IC2PSC 0x0C00U /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
+#define TIM_CCMR1_IC2PSC_0 0x0400U /*!<Bit 0 */
+#define TIM_CCMR1_IC2PSC_1 0x0800U /*!<Bit 1 */
+
+#define TIM_CCMR1_IC2F 0xF000U /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
+#define TIM_CCMR1_IC2F_0 0x1000U /*!<Bit 0 */
+#define TIM_CCMR1_IC2F_1 0x2000U /*!<Bit 1 */
+#define TIM_CCMR1_IC2F_2 0x4000U /*!<Bit 2 */
+#define TIM_CCMR1_IC2F_3 0x8000U /*!<Bit 3 */
+
+/****************** Bit definition for TIM_CCMR2 register *******************/
+#define TIM_CCMR2_CC3S 0x0003U /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
+#define TIM_CCMR2_CC3S_0 0x0001U /*!<Bit 0 */
+#define TIM_CCMR2_CC3S_1 0x0002U /*!<Bit 1 */
+
+#define TIM_CCMR2_OC3FE 0x0004U /*!<Output Compare 3 Fast enable */
+#define TIM_CCMR2_OC3PE 0x0008U /*!<Output Compare 3 Preload enable */
+
+#define TIM_CCMR2_OC3M 0x0070U /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
+#define TIM_CCMR2_OC3M_0 0x0010U /*!<Bit 0 */
+#define TIM_CCMR2_OC3M_1 0x0020U /*!<Bit 1 */
+#define TIM_CCMR2_OC3M_2 0x0040U /*!<Bit 2 */
+
+#define TIM_CCMR2_OC3CE 0x0080U /*!<Output Compare 3 Clear Enable */
+
+#define TIM_CCMR2_CC4S 0x0300U /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
+#define TIM_CCMR2_CC4S_0 0x0100U /*!<Bit 0 */
+#define TIM_CCMR2_CC4S_1 0x0200U /*!<Bit 1 */
+
+#define TIM_CCMR2_OC4FE 0x0400U /*!<Output Compare 4 Fast enable */
+#define TIM_CCMR2_OC4PE 0x0800U /*!<Output Compare 4 Preload enable */
+
+#define TIM_CCMR2_OC4M 0x7000U /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
+#define TIM_CCMR2_OC4M_0 0x1000U /*!<Bit 0 */
+#define TIM_CCMR2_OC4M_1 0x2000U /*!<Bit 1 */
+#define TIM_CCMR2_OC4M_2 0x4000U /*!<Bit 2 */
+
+#define TIM_CCMR2_OC4CE 0x8000U /*!<Output Compare 4 Clear Enable */
+
+/*----------------------------------------------------------------------------*/
+
+#define TIM_CCMR2_IC3PSC 0x000CU /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
+#define TIM_CCMR2_IC3PSC_0 0x0004U /*!<Bit 0 */
+#define TIM_CCMR2_IC3PSC_1 0x0008U /*!<Bit 1 */
+
+#define TIM_CCMR2_IC3F 0x00F0U /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
+#define TIM_CCMR2_IC3F_0 0x0010U /*!<Bit 0 */
+#define TIM_CCMR2_IC3F_1 0x0020U /*!<Bit 1 */
+#define TIM_CCMR2_IC3F_2 0x0040U /*!<Bit 2 */
+#define TIM_CCMR2_IC3F_3 0x0080U /*!<Bit 3 */
+
+#define TIM_CCMR2_IC4PSC 0x0C00U /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
+#define TIM_CCMR2_IC4PSC_0 0x0400U /*!<Bit 0 */
+#define TIM_CCMR2_IC4PSC_1 0x0800U /*!<Bit 1 */
+
+#define TIM_CCMR2_IC4F 0xF000U /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
+#define TIM_CCMR2_IC4F_0 0x1000U /*!<Bit 0 */
+#define TIM_CCMR2_IC4F_1 0x2000U /*!<Bit 1 */
+#define TIM_CCMR2_IC4F_2 0x4000U /*!<Bit 2 */
+#define TIM_CCMR2_IC4F_3 0x8000U /*!<Bit 3 */
+
+/******************* Bit definition for TIM_CCER register *******************/
+#define TIM_CCER_CC1E 0x0001U /*!<Capture/Compare 1 output enable */
+#define TIM_CCER_CC1P 0x0002U /*!<Capture/Compare 1 output Polarity */
+#define TIM_CCER_CC1NE 0x0004U /*!<Capture/Compare 1 Complementary output enable */
+#define TIM_CCER_CC1NP 0x0008U /*!<Capture/Compare 1 Complementary output Polarity */
+#define TIM_CCER_CC2E 0x0010U /*!<Capture/Compare 2 output enable */
+#define TIM_CCER_CC2P 0x0020U /*!<Capture/Compare 2 output Polarity */
+#define TIM_CCER_CC2NE 0x0040U /*!<Capture/Compare 2 Complementary output enable */
+#define TIM_CCER_CC2NP 0x0080U /*!<Capture/Compare 2 Complementary output Polarity */
+#define TIM_CCER_CC3E 0x0100U /*!<Capture/Compare 3 output enable */
+#define TIM_CCER_CC3P 0x0200U /*!<Capture/Compare 3 output Polarity */
+#define TIM_CCER_CC3NE 0x0400U /*!<Capture/Compare 3 Complementary output enable */
+#define TIM_CCER_CC3NP 0x0800U /*!<Capture/Compare 3 Complementary output Polarity */
+#define TIM_CCER_CC4E 0x1000U /*!<Capture/Compare 4 output enable */
+#define TIM_CCER_CC4P 0x2000U /*!<Capture/Compare 4 output Polarity */
+#define TIM_CCER_CC4NP 0x8000U /*!<Capture/Compare 4 Complementary output Polarity */
+
+/******************* Bit definition for TIM_CNT register ********************/
+#define TIM_CNT_CNT 0xFFFFU /*!<Counter Value */
+
+/******************* Bit definition for TIM_PSC register ********************/
+#define TIM_PSC_PSC 0xFFFFU /*!<Prescaler Value */
+
+/******************* Bit definition for TIM_ARR register ********************/
+#define TIM_ARR_ARR 0xFFFFU /*!<actual auto-reload Value */
+
+/******************* Bit definition for TIM_RCR register ********************/
+#define TIM_RCR_REP 0xFFU /*!<Repetition Counter Value */
+
+/******************* Bit definition for TIM_CCR1 register *******************/
+#define TIM_CCR1_CCR1 0xFFFFU /*!<Capture/Compare 1 Value */
+
+/******************* Bit definition for TIM_CCR2 register *******************/
+#define TIM_CCR2_CCR2 0xFFFFU /*!<Capture/Compare 2 Value */
+
+/******************* Bit definition for TIM_CCR3 register *******************/
+#define TIM_CCR3_CCR3 0xFFFFU /*!<Capture/Compare 3 Value */
+
+/******************* Bit definition for TIM_CCR4 register *******************/
+#define TIM_CCR4_CCR4 0xFFFFU /*!<Capture/Compare 4 Value */
+
+/******************* Bit definition for TIM_BDTR register *******************/
+#define TIM_BDTR_DTG 0x00FFU /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
+#define TIM_BDTR_DTG_0 0x0001U /*!<Bit 0 */
+#define TIM_BDTR_DTG_1 0x0002U /*!<Bit 1 */
+#define TIM_BDTR_DTG_2 0x0004U /*!<Bit 2 */
+#define TIM_BDTR_DTG_3 0x0008U /*!<Bit 3 */
+#define TIM_BDTR_DTG_4 0x0010U /*!<Bit 4 */
+#define TIM_BDTR_DTG_5 0x0020U /*!<Bit 5 */
+#define TIM_BDTR_DTG_6 0x0040U /*!<Bit 6 */
+#define TIM_BDTR_DTG_7 0x0080U /*!<Bit 7 */
+
+#define TIM_BDTR_LOCK 0x0300U /*!<LOCK[1:0] bits (Lock Configuration) */
+#define TIM_BDTR_LOCK_0 0x0100U /*!<Bit 0 */
+#define TIM_BDTR_LOCK_1 0x0200U /*!<Bit 1 */
+
+#define TIM_BDTR_OSSI 0x0400U /*!<Off-State Selection for Idle mode */
+#define TIM_BDTR_OSSR 0x0800U /*!<Off-State Selection for Run mode */
+#define TIM_BDTR_BKE 0x1000U /*!<Break enable */
+#define TIM_BDTR_BKP 0x2000U /*!<Break Polarity */
+#define TIM_BDTR_AOE 0x4000U /*!<Automatic Output enable */
+#define TIM_BDTR_MOE 0x8000U /*!<Main Output enable */
+
+/******************* Bit definition for TIM_DCR register ********************/
+#define TIM_DCR_DBA 0x001FU /*!<DBA[4:0] bits (DMA Base Address) */
+#define TIM_DCR_DBA_0 0x0001U /*!<Bit 0 */
+#define TIM_DCR_DBA_1 0x0002U /*!<Bit 1 */
+#define TIM_DCR_DBA_2 0x0004U /*!<Bit 2 */
+#define TIM_DCR_DBA_3 0x0008U /*!<Bit 3 */
+#define TIM_DCR_DBA_4 0x0010U /*!<Bit 4 */
+
+#define TIM_DCR_DBL 0x1F00U /*!<DBL[4:0] bits (DMA Burst Length) */
+#define TIM_DCR_DBL_0 0x0100U /*!<Bit 0 */
+#define TIM_DCR_DBL_1 0x0200U /*!<Bit 1 */
+#define TIM_DCR_DBL_2 0x0400U /*!<Bit 2 */
+#define TIM_DCR_DBL_3 0x0800U /*!<Bit 3 */
+#define TIM_DCR_DBL_4 0x1000U /*!<Bit 4 */
+
+/******************* Bit definition for TIM_DMAR register *******************/
+#define TIM_DMAR_DMAB 0xFFFFU /*!<DMA register for burst accesses */
+
+/******************* Bit definition for TIM_OR register *********************/
+#define TIM_OR_TI4_RMP 0x00C0U /*!<TI4_RMP[1:0] bits (TIM5 Input 4 remap) */
+#define TIM_OR_TI4_RMP_0 0x0040U /*!<Bit 0 */
+#define TIM_OR_TI4_RMP_1 0x0080U /*!<Bit 1 */
+#define TIM_OR_ITR1_RMP 0x0C00U /*!<ITR1_RMP[1:0] bits (TIM2 Internal trigger 1 remap) */
+#define TIM_OR_ITR1_RMP_0 0x0400U /*!<Bit 0 */
+#define TIM_OR_ITR1_RMP_1 0x0800U /*!<Bit 1 */
+
+
+/******************************************************************************/
+/* */
+/* Universal Synchronous Asynchronous Receiver Transmitter */
+/* */
+/******************************************************************************/
+/******************* Bit definition for USART_SR register *******************/
+#define USART_SR_PE 0x0001U /*!<Parity Error */
+#define USART_SR_FE 0x0002U /*!<Framing Error */
+#define USART_SR_NE 0x0004U /*!<Noise Error Flag */
+#define USART_SR_ORE 0x0008U /*!<OverRun Error */
+#define USART_SR_IDLE 0x0010U /*!<IDLE line detected */
+#define USART_SR_RXNE 0x0020U /*!<Read Data Register Not Empty */
+#define USART_SR_TC 0x0040U /*!<Transmission Complete */
+#define USART_SR_TXE 0x0080U /*!<Transmit Data Register Empty */
+#define USART_SR_LBD 0x0100U /*!<LIN Break Detection Flag */
+#define USART_SR_CTS 0x0200U /*!<CTS Flag */
+
+/******************* Bit definition for USART_DR register *******************/
+#define USART_DR_DR 0x01FFU /*!<Data value */
+
+/****************** Bit definition for USART_BRR register *******************/
+#define USART_BRR_DIV_Fraction 0x000FU /*!<Fraction of USARTDIV */
+#define USART_BRR_DIV_Mantissa 0xFFF0U /*!<Mantissa of USARTDIV */
+
+/****************** Bit definition for USART_CR1 register *******************/
+#define USART_CR1_SBK 0x0001U /*!<Send Break */
+#define USART_CR1_RWU 0x0002U /*!<Receiver wakeup */
+#define USART_CR1_RE 0x0004U /*!<Receiver Enable */
+#define USART_CR1_TE 0x0008U /*!<Transmitter Enable */
+#define USART_CR1_IDLEIE 0x0010U /*!<IDLE Interrupt Enable */
+#define USART_CR1_RXNEIE 0x0020U /*!<RXNE Interrupt Enable */
+#define USART_CR1_TCIE 0x0040U /*!<Transmission Complete Interrupt Enable */
+#define USART_CR1_TXEIE 0x0080U /*!<PE Interrupt Enable */
+#define USART_CR1_PEIE 0x0100U /*!<PE Interrupt Enable */
+#define USART_CR1_PS 0x0200U /*!<Parity Selection */
+#define USART_CR1_PCE 0x0400U /*!<Parity Control Enable */
+#define USART_CR1_WAKE 0x0800U /*!<Wakeup method */
+#define USART_CR1_M 0x1000U /*!<Word length */
+#define USART_CR1_UE 0x2000U /*!<USART Enable */
+#define USART_CR1_OVER8 0x8000U /*!<USART Oversampling by 8 enable */
+
+/****************** Bit definition for USART_CR2 register *******************/
+#define USART_CR2_ADD 0x000FU /*!<Address of the USART node */
+#define USART_CR2_LBDL 0x0020U /*!<LIN Break Detection Length */
+#define USART_CR2_LBDIE 0x0040U /*!<LIN Break Detection Interrupt Enable */
+#define USART_CR2_LBCL 0x0100U /*!<Last Bit Clock pulse */
+#define USART_CR2_CPHA 0x0200U /*!<Clock Phase */
+#define USART_CR2_CPOL 0x0400U /*!<Clock Polarity */
+#define USART_CR2_CLKEN 0x0800U /*!<Clock Enable */
+
+#define USART_CR2_STOP 0x3000U /*!<STOP[1:0] bits (STOP bits) */
+#define USART_CR2_STOP_0 0x1000U /*!<Bit 0 */
+#define USART_CR2_STOP_1 0x2000U /*!<Bit 1 */
+
+#define USART_CR2_LINEN 0x4000U /*!<LIN mode enable */
+
+/****************** Bit definition for USART_CR3 register *******************/
+#define USART_CR3_EIE 0x0001U /*!<Error Interrupt Enable */
+#define USART_CR3_IREN 0x0002U /*!<IrDA mode Enable */
+#define USART_CR3_IRLP 0x0004U /*!<IrDA Low-Power */
+#define USART_CR3_HDSEL 0x0008U /*!<Half-Duplex Selection */
+#define USART_CR3_NACK 0x0010U /*!<Smartcard NACK enable */
+#define USART_CR3_SCEN 0x0020U /*!<Smartcard mode enable */
+#define USART_CR3_DMAR 0x0040U /*!<DMA Enable Receiver */
+#define USART_CR3_DMAT 0x0080U /*!<DMA Enable Transmitter */
+#define USART_CR3_RTSE 0x0100U /*!<RTS Enable */
+#define USART_CR3_CTSE 0x0200U /*!<CTS Enable */
+#define USART_CR3_CTSIE 0x0400U /*!<CTS Interrupt Enable */
+#define USART_CR3_ONEBIT 0x0800U /*!<USART One bit method enable */
+
+/****************** Bit definition for USART_GTPR register ******************/
+#define USART_GTPR_PSC 0x00FFU /*!<PSC[7:0] bits (Prescaler value) */
+#define USART_GTPR_PSC_0 0x0001U /*!<Bit 0 */
+#define USART_GTPR_PSC_1 0x0002U /*!<Bit 1 */
+#define USART_GTPR_PSC_2 0x0004U /*!<Bit 2 */
+#define USART_GTPR_PSC_3 0x0008U /*!<Bit 3 */
+#define USART_GTPR_PSC_4 0x0010U /*!<Bit 4 */
+#define USART_GTPR_PSC_5 0x0020U /*!<Bit 5 */
+#define USART_GTPR_PSC_6 0x0040U /*!<Bit 6 */
+#define USART_GTPR_PSC_7 0x0080U /*!<Bit 7 */
+
+#define USART_GTPR_GT 0xFF00U /*!<Guard time value */
+
+/******************************************************************************/
+/* */
+/* Window WATCHDOG */
+/* */
+/******************************************************************************/
+/******************* Bit definition for WWDG_CR register ********************/
+#define WWDG_CR_T 0x7FU /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
+#define WWDG_CR_T_0 0x01U /*!<Bit 0 */
+#define WWDG_CR_T_1 0x02U /*!<Bit 1 */
+#define WWDG_CR_T_2 0x04U /*!<Bit 2 */
+#define WWDG_CR_T_3 0x08U /*!<Bit 3 */
+#define WWDG_CR_T_4 0x10U /*!<Bit 4 */
+#define WWDG_CR_T_5 0x20U /*!<Bit 5 */
+#define WWDG_CR_T_6 0x40U /*!<Bit 6 */
+/* Legacy defines */
+#define WWDG_CR_T0 WWDG_CR_T_0
+#define WWDG_CR_T1 WWDG_CR_T_1
+#define WWDG_CR_T2 WWDG_CR_T_2
+#define WWDG_CR_T3 WWDG_CR_T_3
+#define WWDG_CR_T4 WWDG_CR_T_4
+#define WWDG_CR_T5 WWDG_CR_T_5
+#define WWDG_CR_T6 WWDG_CR_T_6
+
+#define WWDG_CR_WDGA 0x80U /*!<Activation bit */
+
+/******************* Bit definition for WWDG_CFR register *******************/
+#define WWDG_CFR_W 0x007FU /*!<W[6:0] bits (7-bit window value) */
+#define WWDG_CFR_W_0 0x0001U /*!<Bit 0 */
+#define WWDG_CFR_W_1 0x0002U /*!<Bit 1 */
+#define WWDG_CFR_W_2 0x0004U /*!<Bit 2 */
+#define WWDG_CFR_W_3 0x0008U /*!<Bit 3 */
+#define WWDG_CFR_W_4 0x0010U /*!<Bit 4 */
+#define WWDG_CFR_W_5 0x0020U /*!<Bit 5 */
+#define WWDG_CFR_W_6 0x0040U /*!<Bit 6 */
+/* Legacy defines */
+#define WWDG_CFR_W0 WWDG_CFR_W_0
+#define WWDG_CFR_W1 WWDG_CFR_W_1
+#define WWDG_CFR_W2 WWDG_CFR_W_2
+#define WWDG_CFR_W3 WWDG_CFR_W_3
+#define WWDG_CFR_W4 WWDG_CFR_W_4
+#define WWDG_CFR_W5 WWDG_CFR_W_5
+#define WWDG_CFR_W6 WWDG_CFR_W_6
+
+#define WWDG_CFR_WDGTB 0x0180U /*!<WDGTB[1:0] bits (Timer Base) */
+#define WWDG_CFR_WDGTB_0 0x0080U /*!<Bit 0 */
+#define WWDG_CFR_WDGTB_1 0x0100U /*!<Bit 1 */
+/* Legacy defines */
+#define WWDG_CFR_WDGTB0 WWDG_CFR_WDGTB_0
+#define WWDG_CFR_WDGTB1 WWDG_CFR_WDGTB_1
+
+#define WWDG_CFR_EWI 0x0200U /*!<Early Wakeup Interrupt */
+
+/******************* Bit definition for WWDG_SR register ********************/
+#define WWDG_SR_EWIF 0x01U /*!<Early Wakeup Interrupt Flag */
+
+
+/******************************************************************************/
+/* */
+/* DBG */
+/* */
+/******************************************************************************/
+/******************** Bit definition for DBGMCU_IDCODE register *************/
+#define DBGMCU_IDCODE_DEV_ID 0x00000FFFU
+#define DBGMCU_IDCODE_REV_ID 0xFFFF0000U
+
+/******************** Bit definition for DBGMCU_CR register *****************/
+#define DBGMCU_CR_DBG_SLEEP 0x00000001U
+#define DBGMCU_CR_DBG_STOP 0x00000002U
+#define DBGMCU_CR_DBG_STANDBY 0x00000004U
+#define DBGMCU_CR_TRACE_IOEN 0x00000020U
+
+#define DBGMCU_CR_TRACE_MODE 0x000000C0U
+#define DBGMCU_CR_TRACE_MODE_0 0x00000040U/*!<Bit 0 */
+#define DBGMCU_CR_TRACE_MODE_1 0x00000080U/*!<Bit 1 */
+
+/******************** Bit definition for DBGMCU_APB1_FZ register ************/
+#define DBGMCU_APB1_FZ_DBG_TIM2_STOP 0x00000001U
+#define DBGMCU_APB1_FZ_DBG_TIM3_STOP 0x00000002U
+#define DBGMCU_APB1_FZ_DBG_TIM4_STOP 0x00000004U
+#define DBGMCU_APB1_FZ_DBG_TIM5_STOP 0x00000008U
+#define DBGMCU_APB1_FZ_DBG_TIM6_STOP 0x00000010U
+#define DBGMCU_APB1_FZ_DBG_TIM7_STOP 0x00000020U
+#define DBGMCU_APB1_FZ_DBG_TIM12_STOP 0x00000040U
+#define DBGMCU_APB1_FZ_DBG_TIM13_STOP 0x00000080U
+#define DBGMCU_APB1_FZ_DBG_TIM14_STOP 0x00000100U
+#define DBGMCU_APB1_FZ_DBG_RTC_STOP 0x00000400U
+#define DBGMCU_APB1_FZ_DBG_WWDG_STOP 0x00000800U
+#define DBGMCU_APB1_FZ_DBG_IWDG_STOP 0x00001000U
+#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT 0x00200000U
+#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT 0x00400000U
+#define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT 0x00800000U
+#define DBGMCU_APB1_FZ_DBG_CAN1_STOP 0x02000000U
+#define DBGMCU_APB1_FZ_DBG_CAN2_STOP 0x04000000U
+/* Old IWDGSTOP bit definition, maintained for legacy purpose */
+#define DBGMCU_APB1_FZ_DBG_IWDEG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP
+
+/******************** Bit definition for DBGMCU_APB2_FZ register ************/
+#define DBGMCU_APB2_FZ_DBG_TIM1_STOP 0x00000001U
+#define DBGMCU_APB2_FZ_DBG_TIM8_STOP 0x00000002U
+#define DBGMCU_APB2_FZ_DBG_TIM9_STOP 0x00010000U
+#define DBGMCU_APB2_FZ_DBG_TIM10_STOP 0x00020000U
+#define DBGMCU_APB2_FZ_DBG_TIM11_STOP 0x00040000U
+
+/******************************************************************************/
+/* */
+/* USB_OTG */
+/* */
+/******************************************************************************/
+/******************** Bit definition forUSB_OTG_GOTGCTL register ********************/
+#define USB_OTG_GOTGCTL_SRQSCS 0x00000001U /*!< Session request success */
+#define USB_OTG_GOTGCTL_SRQ 0x00000002U /*!< Session request */
+#define USB_OTG_GOTGCTL_HNGSCS 0x00000100U /*!< Host negotiation success */
+#define USB_OTG_GOTGCTL_HNPRQ 0x00000200U /*!< HNP request */
+#define USB_OTG_GOTGCTL_HSHNPEN 0x00000400U /*!< Host set HNP enable */
+#define USB_OTG_GOTGCTL_DHNPEN 0x00000800U /*!< Device HNP enabled */
+#define USB_OTG_GOTGCTL_CIDSTS 0x00010000U /*!< Connector ID status */
+#define USB_OTG_GOTGCTL_DBCT 0x00020000U /*!< Long/short debounce time */
+#define USB_OTG_GOTGCTL_ASVLD 0x00040000U /*!< A-session valid */
+#define USB_OTG_GOTGCTL_BSVLD 0x00080000U /*!< B-session valid */
+
+/******************** Bit definition forUSB_OTG_HCFG register ********************/
+
+#define USB_OTG_HCFG_FSLSPCS 0x00000003U /*!< FS/LS PHY clock select */
+#define USB_OTG_HCFG_FSLSPCS_0 0x00000001U /*!<Bit 0 */
+#define USB_OTG_HCFG_FSLSPCS_1 0x00000002U /*!<Bit 1 */
+#define USB_OTG_HCFG_FSLSS 0x00000004U /*!< FS- and LS-only support */
+
+/******************** Bit definition forUSB_OTG_DCFG register ********************/
+
+#define USB_OTG_DCFG_DSPD 0x00000003U /*!< Device speed */
+#define USB_OTG_DCFG_DSPD_0 0x00000001U /*!<Bit 0 */
+#define USB_OTG_DCFG_DSPD_1 0x00000002U /*!<Bit 1 */
+#define USB_OTG_DCFG_NZLSOHSK 0x00000004U /*!< Nonzero-length status OUT handshake */
+
+#define USB_OTG_DCFG_DAD 0x000007F0U /*!< Device address */
+#define USB_OTG_DCFG_DAD_0 0x00000010U /*!<Bit 0 */
+#define USB_OTG_DCFG_DAD_1 0x00000020U /*!<Bit 1 */
+#define USB_OTG_DCFG_DAD_2 0x00000040U /*!<Bit 2 */
+#define USB_OTG_DCFG_DAD_3 0x00000080U /*!<Bit 3 */
+#define USB_OTG_DCFG_DAD_4 0x00000100U /*!<Bit 4 */
+#define USB_OTG_DCFG_DAD_5 0x00000200U /*!<Bit 5 */
+#define USB_OTG_DCFG_DAD_6 0x00000400U /*!<Bit 6 */
+
+#define USB_OTG_DCFG_PFIVL 0x00001800U /*!< Periodic (micro)frame interval */
+#define USB_OTG_DCFG_PFIVL_0 0x00000800U /*!<Bit 0 */
+#define USB_OTG_DCFG_PFIVL_1 0x00001000U /*!<Bit 1 */
+
+#define USB_OTG_DCFG_PERSCHIVL 0x03000000U /*!< Periodic scheduling interval */
+#define USB_OTG_DCFG_PERSCHIVL_0 0x01000000U /*!<Bit 0 */
+#define USB_OTG_DCFG_PERSCHIVL_1 0x02000000U /*!<Bit 1 */
+
+/******************** Bit definition forUSB_OTG_PCGCR register ********************/
+#define USB_OTG_PCGCR_STPPCLK 0x00000001U /*!< Stop PHY clock */
+#define USB_OTG_PCGCR_GATEHCLK 0x00000002U /*!< Gate HCLK */
+#define USB_OTG_PCGCR_PHYSUSP 0x00000010U /*!< PHY suspended */
+
+/******************** Bit definition forUSB_OTG_GOTGINT register ********************/
+#define USB_OTG_GOTGINT_SEDET 0x00000004U /*!< Session end detected */
+#define USB_OTG_GOTGINT_SRSSCHG 0x00000100U /*!< Session request success status change */
+#define USB_OTG_GOTGINT_HNSSCHG 0x00000200U /*!< Host negotiation success status change */
+#define USB_OTG_GOTGINT_HNGDET 0x00020000U /*!< Host negotiation detected */
+#define USB_OTG_GOTGINT_ADTOCHG 0x00040000U /*!< A-device timeout change */
+#define USB_OTG_GOTGINT_DBCDNE 0x00080000U /*!< Debounce done */
+
+/******************** Bit definition forUSB_OTG_DCTL register ********************/
+#define USB_OTG_DCTL_RWUSIG 0x00000001U /*!< Remote wakeup signaling */
+#define USB_OTG_DCTL_SDIS 0x00000002U /*!< Soft disconnect */
+#define USB_OTG_DCTL_GINSTS 0x00000004U /*!< Global IN NAK status */
+#define USB_OTG_DCTL_GONSTS 0x00000008U /*!< Global OUT NAK status */
+
+#define USB_OTG_DCTL_TCTL 0x00000070U /*!< Test control */
+#define USB_OTG_DCTL_TCTL_0 0x00000010U /*!<Bit 0 */
+#define USB_OTG_DCTL_TCTL_1 0x00000020U /*!<Bit 1 */
+#define USB_OTG_DCTL_TCTL_2 0x00000040U /*!<Bit 2 */
+#define USB_OTG_DCTL_SGINAK 0x00000080U /*!< Set global IN NAK */
+#define USB_OTG_DCTL_CGINAK 0x00000100U /*!< Clear global IN NAK */
+#define USB_OTG_DCTL_SGONAK 0x00000200U /*!< Set global OUT NAK */
+#define USB_OTG_DCTL_CGONAK 0x00000400U /*!< Clear global OUT NAK */
+#define USB_OTG_DCTL_POPRGDNE 0x00000800U /*!< Power-on programming done */
+
+/******************** Bit definition forUSB_OTG_HFIR register ********************/
+#define USB_OTG_HFIR_FRIVL 0x0000FFFFU /*!< Frame interval */
+
+/******************** Bit definition forUSB_OTG_HFNUM register ********************/
+#define USB_OTG_HFNUM_FRNUM 0x0000FFFFU /*!< Frame number */
+#define USB_OTG_HFNUM_FTREM 0xFFFF0000U /*!< Frame time remaining */
+
+/******************** Bit definition forUSB_OTG_DSTS register ********************/
+#define USB_OTG_DSTS_SUSPSTS 0x00000001U /*!< Suspend status */
+
+#define USB_OTG_DSTS_ENUMSPD 0x00000006U /*!< Enumerated speed */
+#define USB_OTG_DSTS_ENUMSPD_0 0x00000002U /*!<Bit 0 */
+#define USB_OTG_DSTS_ENUMSPD_1 0x00000004U /*!<Bit 1 */
+#define USB_OTG_DSTS_EERR 0x00000008U /*!< Erratic error */
+#define USB_OTG_DSTS_FNSOF 0x003FFF00U /*!< Frame number of the received SOF */
+
+/******************** Bit definition forUSB_OTG_GAHBCFG register ********************/
+#define USB_OTG_GAHBCFG_GINT 0x00000001U /*!< Global interrupt mask */
+
+#define USB_OTG_GAHBCFG_HBSTLEN 0x0000001EU /*!< Burst length/type */
+#define USB_OTG_GAHBCFG_HBSTLEN_0 0x00000002U /*!<Bit 0 */
+#define USB_OTG_GAHBCFG_HBSTLEN_1 0x00000004U /*!<Bit 1 */
+#define USB_OTG_GAHBCFG_HBSTLEN_2 0x00000008U /*!<Bit 2 */
+#define USB_OTG_GAHBCFG_HBSTLEN_3 0x00000010U /*!<Bit 3 */
+#define USB_OTG_GAHBCFG_DMAEN 0x00000020U /*!< DMA enable */
+#define USB_OTG_GAHBCFG_TXFELVL 0x00000080U /*!< TxFIFO empty level */
+#define USB_OTG_GAHBCFG_PTXFELVL 0x00000100U /*!< Periodic TxFIFO empty level */
+
+/******************** Bit definition forUSB_OTG_GUSBCFG register ********************/
+
+#define USB_OTG_GUSBCFG_TOCAL 0x00000007U /*!< FS timeout calibration */
+#define USB_OTG_GUSBCFG_TOCAL_0 0x00000001U /*!<Bit 0 */
+#define USB_OTG_GUSBCFG_TOCAL_1 0x00000002U /*!<Bit 1 */
+#define USB_OTG_GUSBCFG_TOCAL_2 0x00000004U /*!<Bit 2 */
+#define USB_OTG_GUSBCFG_PHYSEL 0x00000040U /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */
+#define USB_OTG_GUSBCFG_SRPCAP 0x00000100U /*!< SRP-capable */
+#define USB_OTG_GUSBCFG_HNPCAP 0x00000200U /*!< HNP-capable */
+
+#define USB_OTG_GUSBCFG_TRDT 0x00003C00U /*!< USB turnaround time */
+#define USB_OTG_GUSBCFG_TRDT_0 0x00000400U /*!<Bit 0 */
+#define USB_OTG_GUSBCFG_TRDT_1 0x00000800U /*!<Bit 1 */
+#define USB_OTG_GUSBCFG_TRDT_2 0x00001000U /*!<Bit 2 */
+#define USB_OTG_GUSBCFG_TRDT_3 0x00002000U /*!<Bit 3 */
+#define USB_OTG_GUSBCFG_PHYLPCS 0x00008000U /*!< PHY Low-power clock select */
+#define USB_OTG_GUSBCFG_ULPIFSLS 0x00020000U /*!< ULPI FS/LS select */
+#define USB_OTG_GUSBCFG_ULPIAR 0x00040000U /*!< ULPI Auto-resume */
+#define USB_OTG_GUSBCFG_ULPICSM 0x00080000U /*!< ULPI Clock SuspendM */
+#define USB_OTG_GUSBCFG_ULPIEVBUSD 0x00100000U /*!< ULPI External VBUS Drive */
+#define USB_OTG_GUSBCFG_ULPIEVBUSI 0x00200000U /*!< ULPI external VBUS indicator */
+#define USB_OTG_GUSBCFG_TSDPS 0x00400000U /*!< TermSel DLine pulsing selection */
+#define USB_OTG_GUSBCFG_PCCI 0x00800000U /*!< Indicator complement */
+#define USB_OTG_GUSBCFG_PTCI 0x01000000U /*!< Indicator pass through */
+#define USB_OTG_GUSBCFG_ULPIIPD 0x02000000U /*!< ULPI interface protect disable */
+#define USB_OTG_GUSBCFG_FHMOD 0x20000000U /*!< Forced host mode */
+#define USB_OTG_GUSBCFG_FDMOD 0x40000000U /*!< Forced peripheral mode */
+#define USB_OTG_GUSBCFG_CTXPKT 0x80000000U /*!< Corrupt Tx packet */
+
+/******************** Bit definition forUSB_OTG_GRSTCTL register ********************/
+#define USB_OTG_GRSTCTL_CSRST 0x00000001U /*!< Core soft reset */
+#define USB_OTG_GRSTCTL_HSRST 0x00000002U /*!< HCLK soft reset */
+#define USB_OTG_GRSTCTL_FCRST 0x00000004U /*!< Host frame counter reset */
+#define USB_OTG_GRSTCTL_RXFFLSH 0x00000010U /*!< RxFIFO flush */
+#define USB_OTG_GRSTCTL_TXFFLSH 0x00000020U /*!< TxFIFO flush */
+
+#define USB_OTG_GRSTCTL_TXFNUM 0x000007C0U /*!< TxFIFO number */
+#define USB_OTG_GRSTCTL_TXFNUM_0 0x00000040U /*!<Bit 0 */
+#define USB_OTG_GRSTCTL_TXFNUM_1 0x00000080U /*!<Bit 1 */
+#define USB_OTG_GRSTCTL_TXFNUM_2 0x00000100U /*!<Bit 2 */
+#define USB_OTG_GRSTCTL_TXFNUM_3 0x00000200U /*!<Bit 3 */
+#define USB_OTG_GRSTCTL_TXFNUM_4 0x00000400U /*!<Bit 4 */
+#define USB_OTG_GRSTCTL_DMAREQ 0x40000000U /*!< DMA request signal */
+#define USB_OTG_GRSTCTL_AHBIDL 0x80000000U /*!< AHB master idle */
+
+/******************** Bit definition forUSB_OTG_DIEPMSK register ********************/
+#define USB_OTG_DIEPMSK_XFRCM 0x00000001U /*!< Transfer completed interrupt mask */
+#define USB_OTG_DIEPMSK_EPDM 0x00000002U /*!< Endpoint disabled interrupt mask */
+#define USB_OTG_DIEPMSK_TOM 0x00000008U /*!< Timeout condition mask (nonisochronous endpoints) */
+#define USB_OTG_DIEPMSK_ITTXFEMSK 0x00000010U /*!< IN token received when TxFIFO empty mask */
+#define USB_OTG_DIEPMSK_INEPNMM 0x00000020U /*!< IN token received with EP mismatch mask */
+#define USB_OTG_DIEPMSK_INEPNEM 0x00000040U /*!< IN endpoint NAK effective mask */
+#define USB_OTG_DIEPMSK_TXFURM 0x00000100U /*!< FIFO underrun mask */
+#define USB_OTG_DIEPMSK_BIM 0x00000200U /*!< BNA interrupt mask */
+
+/******************** Bit definition forUSB_OTG_HPTXSTS register ********************/
+#define USB_OTG_HPTXSTS_PTXFSAVL 0x0000FFFFU /*!< Periodic transmit data FIFO space available */
+
+#define USB_OTG_HPTXSTS_PTXQSAV 0x00FF0000U /*!< Periodic transmit request queue space available */
+#define USB_OTG_HPTXSTS_PTXQSAV_0 0x00010000U /*!<Bit 0 */
+#define USB_OTG_HPTXSTS_PTXQSAV_1 0x00020000U /*!<Bit 1 */
+#define USB_OTG_HPTXSTS_PTXQSAV_2 0x00040000U /*!<Bit 2 */
+#define USB_OTG_HPTXSTS_PTXQSAV_3 0x00080000U /*!<Bit 3 */
+#define USB_OTG_HPTXSTS_PTXQSAV_4 0x00100000U /*!<Bit 4 */
+#define USB_OTG_HPTXSTS_PTXQSAV_5 0x00200000U /*!<Bit 5 */
+#define USB_OTG_HPTXSTS_PTXQSAV_6 0x00400000U /*!<Bit 6 */
+#define USB_OTG_HPTXSTS_PTXQSAV_7 0x00800000U /*!<Bit 7 */
+
+#define USB_OTG_HPTXSTS_PTXQTOP 0xFF000000U /*!< Top of the periodic transmit request queue */
+#define USB_OTG_HPTXSTS_PTXQTOP_0 0x01000000U /*!<Bit 0 */
+#define USB_OTG_HPTXSTS_PTXQTOP_1 0x02000000U /*!<Bit 1 */
+#define USB_OTG_HPTXSTS_PTXQTOP_2 0x04000000U /*!<Bit 2 */
+#define USB_OTG_HPTXSTS_PTXQTOP_3 0x08000000U /*!<Bit 3 */
+#define USB_OTG_HPTXSTS_PTXQTOP_4 0x10000000U /*!<Bit 4 */
+#define USB_OTG_HPTXSTS_PTXQTOP_5 0x20000000U /*!<Bit 5 */
+#define USB_OTG_HPTXSTS_PTXQTOP_6 0x40000000U /*!<Bit 6 */
+#define USB_OTG_HPTXSTS_PTXQTOP_7 0x80000000U /*!<Bit 7 */
+
+/******************** Bit definition forUSB_OTG_HAINT register ********************/
+#define USB_OTG_HAINT_HAINT 0x0000FFFFU /*!< Channel interrupts */
+
+/******************** Bit definition forUSB_OTG_DOEPMSK register ********************/
+#define USB_OTG_DOEPMSK_XFRCM 0x00000001U /*!< Transfer completed interrupt mask */
+#define USB_OTG_DOEPMSK_EPDM 0x00000002U /*!< Endpoint disabled interrupt mask */
+#define USB_OTG_DOEPMSK_STUPM 0x00000008U /*!< SETUP phase done mask */
+#define USB_OTG_DOEPMSK_OTEPDM 0x00000010U /*!< OUT token received when endpoint disabled mask */
+#define USB_OTG_DOEPMSK_B2BSTUP 0x00000040U /*!< Back-to-back SETUP packets received mask */
+#define USB_OTG_DOEPMSK_OPEM 0x00000100U /*!< OUT packet error mask */
+#define USB_OTG_DOEPMSK_BOIM 0x00000200U /*!< BNA interrupt mask */
+
+/******************** Bit definition forUSB_OTG_GINTSTS register ********************/
+#define USB_OTG_GINTSTS_CMOD 0x00000001U /*!< Current mode of operation */
+#define USB_OTG_GINTSTS_MMIS 0x00000002U /*!< Mode mismatch interrupt */
+#define USB_OTG_GINTSTS_OTGINT 0x00000004U /*!< OTG interrupt */
+#define USB_OTG_GINTSTS_SOF 0x00000008U /*!< Start of frame */
+#define USB_OTG_GINTSTS_RXFLVL 0x00000010U /*!< RxFIFO nonempty */
+#define USB_OTG_GINTSTS_NPTXFE 0x00000020U /*!< Nonperiodic TxFIFO empty */
+#define USB_OTG_GINTSTS_GINAKEFF 0x00000040U /*!< Global IN nonperiodic NAK effective */
+#define USB_OTG_GINTSTS_BOUTNAKEFF 0x00000080U /*!< Global OUT NAK effective */
+#define USB_OTG_GINTSTS_ESUSP 0x00000400U /*!< Early suspend */
+#define USB_OTG_GINTSTS_USBSUSP 0x00000800U /*!< USB suspend */
+#define USB_OTG_GINTSTS_USBRST 0x00001000U /*!< USB reset */
+#define USB_OTG_GINTSTS_ENUMDNE 0x00002000U /*!< Enumeration done */
+#define USB_OTG_GINTSTS_ISOODRP 0x00004000U /*!< Isochronous OUT packet dropped interrupt */
+#define USB_OTG_GINTSTS_EOPF 0x00008000U /*!< End of periodic frame interrupt */
+#define USB_OTG_GINTSTS_IEPINT 0x00040000U /*!< IN endpoint interrupt */
+#define USB_OTG_GINTSTS_OEPINT 0x00080000U /*!< OUT endpoint interrupt */
+#define USB_OTG_GINTSTS_IISOIXFR 0x00100000U /*!< Incomplete isochronous IN transfer */
+#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT 0x00200000U /*!< Incomplete periodic transfer */
+#define USB_OTG_GINTSTS_DATAFSUSP 0x00400000U /*!< Data fetch suspended */
+#define USB_OTG_GINTSTS_HPRTINT 0x01000000U /*!< Host port interrupt */
+#define USB_OTG_GINTSTS_HCINT 0x02000000U /*!< Host channels interrupt */
+#define USB_OTG_GINTSTS_PTXFE 0x04000000U /*!< Periodic TxFIFO empty */
+#define USB_OTG_GINTSTS_CIDSCHG 0x10000000U /*!< Connector ID status change */
+#define USB_OTG_GINTSTS_DISCINT 0x20000000U /*!< Disconnect detected interrupt */
+#define USB_OTG_GINTSTS_SRQINT 0x40000000U /*!< Session request/new session detected interrupt */
+#define USB_OTG_GINTSTS_WKUINT 0x80000000U /*!< Resume/remote wakeup detected interrupt */
+
+/******************** Bit definition forUSB_OTG_GINTMSK register ********************/
+#define USB_OTG_GINTMSK_MMISM 0x00000002U /*!< Mode mismatch interrupt mask */
+#define USB_OTG_GINTMSK_OTGINT 0x00000004U /*!< OTG interrupt mask */
+#define USB_OTG_GINTMSK_SOFM 0x00000008U /*!< Start of frame mask */
+#define USB_OTG_GINTMSK_RXFLVLM 0x00000010U /*!< Receive FIFO nonempty mask */
+#define USB_OTG_GINTMSK_NPTXFEM 0x00000020U /*!< Nonperiodic TxFIFO empty mask */
+#define USB_OTG_GINTMSK_GINAKEFFM 0x00000040U /*!< Global nonperiodic IN NAK effective mask */
+#define USB_OTG_GINTMSK_GONAKEFFM 0x00000080U /*!< Global OUT NAK effective mask */
+#define USB_OTG_GINTMSK_ESUSPM 0x00000400U /*!< Early suspend mask */
+#define USB_OTG_GINTMSK_USBSUSPM 0x00000800U /*!< USB suspend mask */
+#define USB_OTG_GINTMSK_USBRST 0x00001000U /*!< USB reset mask */
+#define USB_OTG_GINTMSK_ENUMDNEM 0x00002000U /*!< Enumeration done mask */
+#define USB_OTG_GINTMSK_ISOODRPM 0x00004000U /*!< Isochronous OUT packet dropped interrupt mask */
+#define USB_OTG_GINTMSK_EOPFM 0x00008000U /*!< End of periodic frame interrupt mask */
+#define USB_OTG_GINTMSK_EPMISM 0x00020000U /*!< Endpoint mismatch interrupt mask */
+#define USB_OTG_GINTMSK_IEPINT 0x00040000U /*!< IN endpoints interrupt mask */
+#define USB_OTG_GINTMSK_OEPINT 0x00080000U /*!< OUT endpoints interrupt mask */
+#define USB_OTG_GINTMSK_IISOIXFRM 0x00100000U /*!< Incomplete isochronous IN transfer mask */
+#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM 0x00200000U /*!< Incomplete periodic transfer mask */
+#define USB_OTG_GINTMSK_FSUSPM 0x00400000U /*!< Data fetch suspended mask */
+#define USB_OTG_GINTMSK_PRTIM 0x01000000U /*!< Host port interrupt mask */
+#define USB_OTG_GINTMSK_HCIM 0x02000000U /*!< Host channels interrupt mask */
+#define USB_OTG_GINTMSK_PTXFEM 0x04000000U /*!< Periodic TxFIFO empty mask */
+#define USB_OTG_GINTMSK_CIDSCHGM 0x10000000U /*!< Connector ID status change mask */
+#define USB_OTG_GINTMSK_DISCINT 0x20000000U /*!< Disconnect detected interrupt mask */
+#define USB_OTG_GINTMSK_SRQIM 0x40000000U /*!< Session request/new session detected interrupt mask */
+#define USB_OTG_GINTMSK_WUIM 0x80000000U /*!< Resume/remote wakeup detected interrupt mask */
+
+/******************** Bit definition forUSB_OTG_DAINT register ********************/
+#define USB_OTG_DAINT_IEPINT 0x0000FFFFU /*!< IN endpoint interrupt bits */
+#define USB_OTG_DAINT_OEPINT 0xFFFF0000U /*!< OUT endpoint interrupt bits */
+
+/******************** Bit definition forUSB_OTG_HAINTMSK register ********************/
+#define USB_OTG_HAINTMSK_HAINTM 0x0000FFFFU /*!< Channel interrupt mask */
+
+/******************** Bit definition for USB_OTG_GRXSTSP register ********************/
+#define USB_OTG_GRXSTSP_EPNUM 0x0000000FU /*!< IN EP interrupt mask bits */
+#define USB_OTG_GRXSTSP_BCNT 0x00007FF0U /*!< OUT EP interrupt mask bits */
+#define USB_OTG_GRXSTSP_DPID 0x00018000U /*!< OUT EP interrupt mask bits */
+#define USB_OTG_GRXSTSP_PKTSTS 0x001E0000U /*!< OUT EP interrupt mask bits */
+
+/******************** Bit definition forUSB_OTG_DAINTMSK register ********************/
+#define USB_OTG_DAINTMSK_IEPM 0x0000FFFFU /*!< IN EP interrupt mask bits */
+#define USB_OTG_DAINTMSK_OEPM 0xFFFF0000U /*!< OUT EP interrupt mask bits */
+
+/******************** Bit definition for OTG register ********************/
+
+#define USB_OTG_CHNUM 0x0000000FU /*!< Channel number */
+#define USB_OTG_CHNUM_0 0x00000001U /*!<Bit 0 */
+#define USB_OTG_CHNUM_1 0x00000002U /*!<Bit 1 */
+#define USB_OTG_CHNUM_2 0x00000004U /*!<Bit 2 */
+#define USB_OTG_CHNUM_3 0x00000008U /*!<Bit 3 */
+#define USB_OTG_BCNT 0x00007FF0U /*!< Byte count */
+
+#define USB_OTG_DPID 0x00018000U /*!< Data PID */
+#define USB_OTG_DPID_0 0x00008000U /*!<Bit 0 */
+#define USB_OTG_DPID_1 0x00010000U /*!<Bit 1 */
+
+#define USB_OTG_PKTSTS 0x001E0000U /*!< Packet status */
+#define USB_OTG_PKTSTS_0 0x00020000U /*!<Bit 0 */
+#define USB_OTG_PKTSTS_1 0x00040000U /*!<Bit 1 */
+#define USB_OTG_PKTSTS_2 0x00080000U /*!<Bit 2 */
+#define USB_OTG_PKTSTS_3 0x00100000U /*!<Bit 3 */
+
+#define USB_OTG_EPNUM 0x0000000FU /*!< Endpoint number */
+#define USB_OTG_EPNUM_0 0x00000001U /*!<Bit 0 */
+#define USB_OTG_EPNUM_1 0x00000002U /*!<Bit 1 */
+#define USB_OTG_EPNUM_2 0x00000004U /*!<Bit 2 */
+#define USB_OTG_EPNUM_3 0x00000008U /*!<Bit 3 */
+
+#define USB_OTG_FRMNUM 0x01E00000U /*!< Frame number */
+#define USB_OTG_FRMNUM_0 0x00200000U /*!<Bit 0 */
+#define USB_OTG_FRMNUM_1 0x00400000U /*!<Bit 1 */
+#define USB_OTG_FRMNUM_2 0x00800000U /*!<Bit 2 */
+#define USB_OTG_FRMNUM_3 0x01000000U /*!<Bit 3 */
+
+/******************** Bit definition for OTG register ********************/
+
+#define USB_OTG_CHNUM 0x0000000FU /*!< Channel number */
+#define USB_OTG_CHNUM_0 0x00000001U /*!<Bit 0 */
+#define USB_OTG_CHNUM_1 0x00000002U /*!<Bit 1 */
+#define USB_OTG_CHNUM_2 0x00000004U /*!<Bit 2 */
+#define USB_OTG_CHNUM_3 0x00000008U /*!<Bit 3 */
+#define USB_OTG_BCNT 0x00007FF0U /*!< Byte count */
+
+#define USB_OTG_DPID 0x00018000U /*!< Data PID */
+#define USB_OTG_DPID_0 0x00008000U /*!<Bit 0 */
+#define USB_OTG_DPID_1 0x00010000U /*!<Bit 1 */
+
+#define USB_OTG_PKTSTS 0x001E0000U /*!< Packet status */
+#define USB_OTG_PKTSTS_0 0x00020000U /*!<Bit 0 */
+#define USB_OTG_PKTSTS_1 0x00040000U /*!<Bit 1 */
+#define USB_OTG_PKTSTS_2 0x00080000U /*!<Bit 2 */
+#define USB_OTG_PKTSTS_3 0x00100000U /*!<Bit 3 */
+
+#define USB_OTG_EPNUM 0x0000000FU /*!< Endpoint number */
+#define USB_OTG_EPNUM_0 0x00000001U /*!<Bit 0 */
+#define USB_OTG_EPNUM_1 0x00000002U /*!<Bit 1 */
+#define USB_OTG_EPNUM_2 0x00000004U /*!<Bit 2 */
+#define USB_OTG_EPNUM_3 0x00000008U /*!<Bit 3 */
+
+#define USB_OTG_FRMNUM 0x01E00000U /*!< Frame number */
+#define USB_OTG_FRMNUM_0 0x00200000U /*!<Bit 0 */
+#define USB_OTG_FRMNUM_1 0x00400000U /*!<Bit 1 */
+#define USB_OTG_FRMNUM_2 0x00800000U /*!<Bit 2 */
+#define USB_OTG_FRMNUM_3 0x01000000U /*!<Bit 3 */
+
+/******************** Bit definition forUSB_OTG_GRXFSIZ register ********************/
+#define USB_OTG_GRXFSIZ_RXFD 0x0000FFFFU /*!< RxFIFO depth */
+
+/******************** Bit definition forUSB_OTG_DVBUSDIS register ********************/
+#define USB_OTG_DVBUSDIS_VBUSDT 0x0000FFFFU /*!< Device VBUS discharge time */
+
+/******************** Bit definition for OTG register ********************/
+#define USB_OTG_NPTXFSA 0x0000FFFFU /*!< Nonperiodic transmit RAM start address */
+#define USB_OTG_NPTXFD 0xFFFF0000U /*!< Nonperiodic TxFIFO depth */
+#define USB_OTG_TX0FSA 0x0000FFFFU /*!< Endpoint 0 transmit RAM start address */
+#define USB_OTG_TX0FD 0xFFFF0000U /*!< Endpoint 0 TxFIFO depth */
+
+/******************** Bit definition forUSB_OTG_DVBUSPULSE register ********************/
+#define USB_OTG_DVBUSPULSE_DVBUSP 0x00000FFFU /*!< Device VBUS pulsing time */
+
+/******************** Bit definition forUSB_OTG_GNPTXSTS register ********************/
+#define USB_OTG_GNPTXSTS_NPTXFSAV 0x0000FFFFU /*!< Nonperiodic TxFIFO space available */
+
+#define USB_OTG_GNPTXSTS_NPTQXSAV 0x00FF0000U /*!< Nonperiodic transmit request queue space available */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_0 0x00010000U /*!<Bit 0 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_1 0x00020000U /*!<Bit 1 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_2 0x00040000U /*!<Bit 2 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_3 0x00080000U /*!<Bit 3 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_4 0x00100000U /*!<Bit 4 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_5 0x00200000U /*!<Bit 5 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_6 0x00400000U /*!<Bit 6 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_7 0x00800000U /*!<Bit 7 */
+
+#define USB_OTG_GNPTXSTS_NPTXQTOP 0x7F000000U /*!< Top of the nonperiodic transmit request queue */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_0 0x01000000U /*!<Bit 0 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_1 0x02000000U /*!<Bit 1 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_2 0x04000000U /*!<Bit 2 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_3 0x08000000U /*!<Bit 3 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_4 0x10000000U /*!<Bit 4 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_5 0x20000000U /*!<Bit 5 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_6 0x40000000U /*!<Bit 6 */
+
+/******************** Bit definition forUSB_OTG_DTHRCTL register ********************/
+#define USB_OTG_DTHRCTL_NONISOTHREN 0x00000001U /*!< Nonisochronous IN endpoints threshold enable */
+#define USB_OTG_DTHRCTL_ISOTHREN 0x00000002U /*!< ISO IN endpoint threshold enable */
+
+#define USB_OTG_DTHRCTL_TXTHRLEN 0x000007FCU /*!< Transmit threshold length */
+#define USB_OTG_DTHRCTL_TXTHRLEN_0 0x00000004U /*!<Bit 0 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_1 0x00000008U /*!<Bit 1 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_2 0x00000010U /*!<Bit 2 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_3 0x00000020U /*!<Bit 3 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_4 0x00000040U /*!<Bit 4 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_5 0x00000080U /*!<Bit 5 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_6 0x00000100U /*!<Bit 6 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_7 0x00000200U /*!<Bit 7 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_8 0x00000400U /*!<Bit 8 */
+#define USB_OTG_DTHRCTL_RXTHREN 0x00010000U /*!< Receive threshold enable */
+
+#define USB_OTG_DTHRCTL_RXTHRLEN 0x03FE0000U /*!< Receive threshold length */
+#define USB_OTG_DTHRCTL_RXTHRLEN_0 0x00020000U /*!<Bit 0 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_1 0x00040000U /*!<Bit 1 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_2 0x00080000U /*!<Bit 2 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_3 0x00100000U /*!<Bit 3 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_4 0x00200000U /*!<Bit 4 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_5 0x00400000U /*!<Bit 5 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_6 0x00800000U /*!<Bit 6 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_7 0x01000000U /*!<Bit 7 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_8 0x02000000U /*!<Bit 8 */
+#define USB_OTG_DTHRCTL_ARPEN 0x08000000U /*!< Arbiter parking enable */
+
+/******************** Bit definition forUSB_OTG_DIEPEMPMSK register ********************/
+#define USB_OTG_DIEPEMPMSK_INEPTXFEM 0x0000FFFFU /*!< IN EP Tx FIFO empty interrupt mask bits */
+
+/******************** Bit definition forUSB_OTG_DEACHINT register ********************/
+#define USB_OTG_DEACHINT_IEP1INT 0x00000002U /*!< IN endpoint 1interrupt bit */
+#define USB_OTG_DEACHINT_OEP1INT 0x00020000U /*!< OUT endpoint 1 interrupt bit */
+
+/******************** Bit definition forUSB_OTG_GCCFG register ********************/
+#define USB_OTG_GCCFG_PWRDWN 0x00010000U /*!< Power down */
+#define USB_OTG_GCCFG_I2CPADEN 0x00020000U /*!< Enable I2C bus connection for the external I2C PHY interface */
+#define USB_OTG_GCCFG_VBUSASEN 0x00040000U /*!< Enable the VBUS sensing device */
+#define USB_OTG_GCCFG_VBUSBSEN 0x00080000U /*!< Enable the VBUS sensing device */
+#define USB_OTG_GCCFG_SOFOUTEN 0x00100000U /*!< SOF output enable */
+#define USB_OTG_GCCFG_NOVBUSSENS 0x00200000U /*!< VBUS sensing disable option */
+
+/******************** Bit definition forUSB_OTG_DEACHINTMSK register ********************/
+#define USB_OTG_DEACHINTMSK_IEP1INTM 0x00000002U /*!< IN Endpoint 1 interrupt mask bit */
+#define USB_OTG_DEACHINTMSK_OEP1INTM 0x00020000U /*!< OUT Endpoint 1 interrupt mask bit */
+
+/******************** Bit definition forUSB_OTG_CID register ********************/
+#define USB_OTG_CID_PRODUCT_ID 0xFFFFFFFFU /*!< Product ID field */
+
+/******************** Bit definition forUSB_OTG_DIEPEACHMSK1 register ********************/
+#define USB_OTG_DIEPEACHMSK1_XFRCM 0x00000001U /*!< Transfer completed interrupt mask */
+#define USB_OTG_DIEPEACHMSK1_EPDM 0x00000002U /*!< Endpoint disabled interrupt mask */
+#define USB_OTG_DIEPEACHMSK1_TOM 0x00000008U /*!< Timeout condition mask (nonisochronous endpoints) */
+#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK 0x00000010U /*!< IN token received when TxFIFO empty mask */
+#define USB_OTG_DIEPEACHMSK1_INEPNMM 0x00000020U /*!< IN token received with EP mismatch mask */
+#define USB_OTG_DIEPEACHMSK1_INEPNEM 0x00000040U /*!< IN endpoint NAK effective mask */
+#define USB_OTG_DIEPEACHMSK1_TXFURM 0x00000100U /*!< FIFO underrun mask */
+#define USB_OTG_DIEPEACHMSK1_BIM 0x00000200U /*!< BNA interrupt mask */
+#define USB_OTG_DIEPEACHMSK1_NAKM 0x00002000U /*!< NAK interrupt mask */
+
+/******************** Bit definition forUSB_OTG_HPRT register ********************/
+#define USB_OTG_HPRT_PCSTS 0x00000001U /*!< Port connect status */
+#define USB_OTG_HPRT_PCDET 0x00000002U /*!< Port connect detected */
+#define USB_OTG_HPRT_PENA 0x00000004U /*!< Port enable */
+#define USB_OTG_HPRT_PENCHNG 0x00000008U /*!< Port enable/disable change */
+#define USB_OTG_HPRT_POCA 0x00000010U /*!< Port overcurrent active */
+#define USB_OTG_HPRT_POCCHNG 0x00000020U /*!< Port overcurrent change */
+#define USB_OTG_HPRT_PRES 0x00000040U /*!< Port resume */
+#define USB_OTG_HPRT_PSUSP 0x00000080U /*!< Port suspend */
+#define USB_OTG_HPRT_PRST 0x00000100U /*!< Port reset */
+
+#define USB_OTG_HPRT_PLSTS 0x00000C00U /*!< Port line status */
+#define USB_OTG_HPRT_PLSTS_0 0x00000400U /*!<Bit 0 */
+#define USB_OTG_HPRT_PLSTS_1 0x00000800U /*!<Bit 1 */
+#define USB_OTG_HPRT_PPWR 0x00001000U /*!< Port power */
+
+#define USB_OTG_HPRT_PTCTL 0x0001E000U /*!< Port test control */
+#define USB_OTG_HPRT_PTCTL_0 0x00002000U /*!<Bit 0 */
+#define USB_OTG_HPRT_PTCTL_1 0x00004000U /*!<Bit 1 */
+#define USB_OTG_HPRT_PTCTL_2 0x00008000U /*!<Bit 2 */
+#define USB_OTG_HPRT_PTCTL_3 0x00010000U /*!<Bit 3 */
+
+#define USB_OTG_HPRT_PSPD 0x00060000U /*!< Port speed */
+#define USB_OTG_HPRT_PSPD_0 0x00020000U /*!<Bit 0 */
+#define USB_OTG_HPRT_PSPD_1 0x00040000U /*!<Bit 1 */
+
+/******************** Bit definition forUSB_OTG_DOEPEACHMSK1 register ********************/
+#define USB_OTG_DOEPEACHMSK1_XFRCM 0x00000001U /*!< Transfer completed interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_EPDM 0x00000002U /*!< Endpoint disabled interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_TOM 0x00000008U /*!< Timeout condition mask */
+#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK 0x00000010U /*!< IN token received when TxFIFO empty mask */
+#define USB_OTG_DOEPEACHMSK1_INEPNMM 0x00000020U /*!< IN token received with EP mismatch mask */
+#define USB_OTG_DOEPEACHMSK1_INEPNEM 0x00000040U /*!< IN endpoint NAK effective mask */
+#define USB_OTG_DOEPEACHMSK1_TXFURM 0x00000100U /*!< OUT packet error mask */
+#define USB_OTG_DOEPEACHMSK1_BIM 0x00000200U /*!< BNA interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_BERRM 0x00001000U /*!< Bubble error interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_NAKM 0x00002000U /*!< NAK interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_NYETM 0x00004000U /*!< NYET interrupt mask */
+
+/******************** Bit definition forUSB_OTG_HPTXFSIZ register ********************/
+#define USB_OTG_HPTXFSIZ_PTXSA 0x0000FFFFU /*!< Host periodic TxFIFO start address */
+#define USB_OTG_HPTXFSIZ_PTXFD 0xFFFF0000U /*!< Host periodic TxFIFO depth */
+
+/******************** Bit definition forUSB_OTG_DIEPCTL register ********************/
+#define USB_OTG_DIEPCTL_MPSIZ 0x000007FFU /*!< Maximum packet size */
+#define USB_OTG_DIEPCTL_USBAEP 0x00008000U /*!< USB active endpoint */
+#define USB_OTG_DIEPCTL_EONUM_DPID 0x00010000U /*!< Even/odd frame */
+#define USB_OTG_DIEPCTL_NAKSTS 0x00020000U /*!< NAK status */
+
+#define USB_OTG_DIEPCTL_EPTYP 0x000C0000U /*!< Endpoint type */
+#define USB_OTG_DIEPCTL_EPTYP_0 0x00040000U /*!<Bit 0 */
+#define USB_OTG_DIEPCTL_EPTYP_1 0x00080000U /*!<Bit 1 */
+#define USB_OTG_DIEPCTL_STALL 0x00200000U /*!< STALL handshake */
+
+#define USB_OTG_DIEPCTL_TXFNUM 0x03C00000U /*!< TxFIFO number */
+#define USB_OTG_DIEPCTL_TXFNUM_0 0x00400000U /*!<Bit 0 */
+#define USB_OTG_DIEPCTL_TXFNUM_1 0x00800000U /*!<Bit 1 */
+#define USB_OTG_DIEPCTL_TXFNUM_2 0x01000000U /*!<Bit 2 */
+#define USB_OTG_DIEPCTL_TXFNUM_3 0x02000000U /*!<Bit 3 */
+#define USB_OTG_DIEPCTL_CNAK 0x04000000U /*!< Clear NAK */
+#define USB_OTG_DIEPCTL_SNAK 0x08000000U /*!< Set NAK */
+#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM 0x10000000U /*!< Set DATA0 PID */
+#define USB_OTG_DIEPCTL_SODDFRM 0x20000000U /*!< Set odd frame */
+#define USB_OTG_DIEPCTL_EPDIS 0x40000000U /*!< Endpoint disable */
+#define USB_OTG_DIEPCTL_EPENA 0x80000000U /*!< Endpoint enable */
+
+/******************** Bit definition forUSB_OTG_HCCHAR register ********************/
+#define USB_OTG_HCCHAR_MPSIZ 0x000007FFU /*!< Maximum packet size */
+
+#define USB_OTG_HCCHAR_EPNUM 0x00007800U /*!< Endpoint number */
+#define USB_OTG_HCCHAR_EPNUM_0 0x00000800U /*!<Bit 0 */
+#define USB_OTG_HCCHAR_EPNUM_1 0x00001000U /*!<Bit 1 */
+#define USB_OTG_HCCHAR_EPNUM_2 0x00002000U /*!<Bit 2 */
+#define USB_OTG_HCCHAR_EPNUM_3 0x00004000U /*!<Bit 3 */
+#define USB_OTG_HCCHAR_EPDIR 0x00008000U /*!< Endpoint direction */
+#define USB_OTG_HCCHAR_LSDEV 0x00020000U /*!< Low-speed device */
+
+#define USB_OTG_HCCHAR_EPTYP 0x000C0000U /*!< Endpoint type */
+#define USB_OTG_HCCHAR_EPTYP_0 0x00040000U /*!<Bit 0 */
+#define USB_OTG_HCCHAR_EPTYP_1 0x00080000U /*!<Bit 1 */
+
+#define USB_OTG_HCCHAR_MC 0x00300000U /*!< Multi Count (MC) / Error Count (EC) */
+#define USB_OTG_HCCHAR_MC_0 0x00100000U /*!<Bit 0 */
+#define USB_OTG_HCCHAR_MC_1 0x00200000U /*!<Bit 1 */
+
+#define USB_OTG_HCCHAR_DAD 0x1FC00000U /*!< Device address */
+#define USB_OTG_HCCHAR_DAD_0 0x00400000U /*!<Bit 0 */
+#define USB_OTG_HCCHAR_DAD_1 0x00800000U /*!<Bit 1 */
+#define USB_OTG_HCCHAR_DAD_2 0x01000000U /*!<Bit 2 */
+#define USB_OTG_HCCHAR_DAD_3 0x02000000U /*!<Bit 3 */
+#define USB_OTG_HCCHAR_DAD_4 0x04000000U /*!<Bit 4 */
+#define USB_OTG_HCCHAR_DAD_5 0x08000000U /*!<Bit 5 */
+#define USB_OTG_HCCHAR_DAD_6 0x10000000U /*!<Bit 6 */
+#define USB_OTG_HCCHAR_ODDFRM 0x20000000U /*!< Odd frame */
+#define USB_OTG_HCCHAR_CHDIS 0x40000000U /*!< Channel disable */
+#define USB_OTG_HCCHAR_CHENA 0x80000000U /*!< Channel enable */
+
+/******************** Bit definition forUSB_OTG_HCSPLT register ********************/
+
+#define USB_OTG_HCSPLT_PRTADDR 0x0000007FU /*!< Port address */
+#define USB_OTG_HCSPLT_PRTADDR_0 0x00000001U /*!<Bit 0 */
+#define USB_OTG_HCSPLT_PRTADDR_1 0x00000002U /*!<Bit 1 */
+#define USB_OTG_HCSPLT_PRTADDR_2 0x00000004U /*!<Bit 2 */
+#define USB_OTG_HCSPLT_PRTADDR_3 0x00000008U /*!<Bit 3 */
+#define USB_OTG_HCSPLT_PRTADDR_4 0x00000010U /*!<Bit 4 */
+#define USB_OTG_HCSPLT_PRTADDR_5 0x00000020U /*!<Bit 5 */
+#define USB_OTG_HCSPLT_PRTADDR_6 0x00000040U /*!<Bit 6 */
+
+#define USB_OTG_HCSPLT_HUBADDR 0x00003F80U /*!< Hub address */
+#define USB_OTG_HCSPLT_HUBADDR_0 0x00000080U /*!<Bit 0 */
+#define USB_OTG_HCSPLT_HUBADDR_1 0x00000100U /*!<Bit 1 */
+#define USB_OTG_HCSPLT_HUBADDR_2 0x00000200U /*!<Bit 2 */
+#define USB_OTG_HCSPLT_HUBADDR_3 0x00000400U /*!<Bit 3 */
+#define USB_OTG_HCSPLT_HUBADDR_4 0x00000800U /*!<Bit 4 */
+#define USB_OTG_HCSPLT_HUBADDR_5 0x00001000U /*!<Bit 5 */
+#define USB_OTG_HCSPLT_HUBADDR_6 0x00002000U /*!<Bit 6 */
+
+#define USB_OTG_HCSPLT_XACTPOS 0x0000C000U /*!< XACTPOS */
+#define USB_OTG_HCSPLT_XACTPOS_0 0x00004000U /*!<Bit 0 */
+#define USB_OTG_HCSPLT_XACTPOS_1 0x00008000U /*!<Bit 1 */
+#define USB_OTG_HCSPLT_COMPLSPLT 0x00010000U /*!< Do complete split */
+#define USB_OTG_HCSPLT_SPLITEN 0x80000000U /*!< Split enable */
+
+/******************** Bit definition forUSB_OTG_HCINT register ********************/
+#define USB_OTG_HCINT_XFRC 0x00000001U /*!< Transfer completed */
+#define USB_OTG_HCINT_CHH 0x00000002U /*!< Channel halted */
+#define USB_OTG_HCINT_AHBERR 0x00000004U /*!< AHB error */
+#define USB_OTG_HCINT_STALL 0x00000008U /*!< STALL response received interrupt */
+#define USB_OTG_HCINT_NAK 0x00000010U /*!< NAK response received interrupt */
+#define USB_OTG_HCINT_ACK 0x00000020U /*!< ACK response received/transmitted interrupt */
+#define USB_OTG_HCINT_NYET 0x00000040U /*!< Response received interrupt */
+#define USB_OTG_HCINT_TXERR 0x00000080U /*!< Transaction error */
+#define USB_OTG_HCINT_BBERR 0x00000100U /*!< Babble error */
+#define USB_OTG_HCINT_FRMOR 0x00000200U /*!< Frame overrun */
+#define USB_OTG_HCINT_DTERR 0x00000400U /*!< Data toggle error */
+
+/******************** Bit definition forUSB_OTG_DIEPINT register ********************/
+#define USB_OTG_DIEPINT_XFRC 0x00000001U /*!< Transfer completed interrupt */
+#define USB_OTG_DIEPINT_EPDISD 0x00000002U /*!< Endpoint disabled interrupt */
+#define USB_OTG_DIEPINT_TOC 0x00000008U /*!< Timeout condition */
+#define USB_OTG_DIEPINT_ITTXFE 0x00000010U /*!< IN token received when TxFIFO is empty */
+#define USB_OTG_DIEPINT_INEPNE 0x00000040U /*!< IN endpoint NAK effective */
+#define USB_OTG_DIEPINT_TXFE 0x00000080U /*!< Transmit FIFO empty */
+#define USB_OTG_DIEPINT_TXFIFOUDRN 0x00000100U /*!< Transmit Fifo Underrun */
+#define USB_OTG_DIEPINT_BNA 0x00000200U /*!< Buffer not available interrupt */
+#define USB_OTG_DIEPINT_PKTDRPSTS 0x00000800U /*!< Packet dropped status */
+#define USB_OTG_DIEPINT_BERR 0x00001000U /*!< Babble error interrupt */
+#define USB_OTG_DIEPINT_NAK 0x00002000U /*!< NAK interrupt */
+
+/******************** Bit definition forUSB_OTG_HCINTMSK register ********************/
+#define USB_OTG_HCINTMSK_XFRCM 0x00000001U /*!< Transfer completed mask */
+#define USB_OTG_HCINTMSK_CHHM 0x00000002U /*!< Channel halted mask */
+#define USB_OTG_HCINTMSK_AHBERR 0x00000004U /*!< AHB error */
+#define USB_OTG_HCINTMSK_STALLM 0x00000008U /*!< STALL response received interrupt mask */
+#define USB_OTG_HCINTMSK_NAKM 0x00000010U /*!< NAK response received interrupt mask */
+#define USB_OTG_HCINTMSK_ACKM 0x00000020U /*!< ACK response received/transmitted interrupt mask */
+#define USB_OTG_HCINTMSK_NYET 0x00000040U /*!< response received interrupt mask */
+#define USB_OTG_HCINTMSK_TXERRM 0x00000080U /*!< Transaction error mask */
+#define USB_OTG_HCINTMSK_BBERRM 0x00000100U /*!< Babble error mask */
+#define USB_OTG_HCINTMSK_FRMORM 0x00000200U /*!< Frame overrun mask */
+#define USB_OTG_HCINTMSK_DTERRM 0x00000400U /*!< Data toggle error mask */
+
+/******************** Bit definition for USB_OTG_DIEPTSIZ register ********************/
+
+#define USB_OTG_DIEPTSIZ_XFRSIZ 0x0007FFFFU /*!< Transfer size */
+#define USB_OTG_DIEPTSIZ_PKTCNT 0x1FF80000U /*!< Packet count */
+#define USB_OTG_DIEPTSIZ_MULCNT 0x60000000U /*!< Packet count */
+/******************** Bit definition forUSB_OTG_HCTSIZ register ********************/
+#define USB_OTG_HCTSIZ_XFRSIZ 0x0007FFFFU /*!< Transfer size */
+#define USB_OTG_HCTSIZ_PKTCNT 0x1FF80000U /*!< Packet count */
+#define USB_OTG_HCTSIZ_DOPING 0x80000000U /*!< Do PING */
+#define USB_OTG_HCTSIZ_DPID 0x60000000U /*!< Data PID */
+#define USB_OTG_HCTSIZ_DPID_0 0x20000000U /*!<Bit 0 */
+#define USB_OTG_HCTSIZ_DPID_1 0x40000000U /*!<Bit 1 */
+
+/******************** Bit definition forUSB_OTG_DIEPDMA register ********************/
+#define USB_OTG_DIEPDMA_DMAADDR 0xFFFFFFFFU /*!< DMA address */
+
+/******************** Bit definition forUSB_OTG_HCDMA register ********************/
+#define USB_OTG_HCDMA_DMAADDR 0xFFFFFFFFU /*!< DMA address */
+
+/******************** Bit definition forUSB_OTG_DTXFSTS register ********************/
+#define USB_OTG_DTXFSTS_INEPTFSAV 0x0000FFFFU /*!< IN endpoint TxFIFO space avail */
+
+/******************** Bit definition forUSB_OTG_DIEPTXF register ********************/
+#define USB_OTG_DIEPTXF_INEPTXSA 0x0000FFFFU /*!< IN endpoint FIFOx transmit RAM start address */
+#define USB_OTG_DIEPTXF_INEPTXFD 0xFFFF0000U /*!< IN endpoint TxFIFO depth */
+
+/******************** Bit definition forUSB_OTG_DOEPCTL register ********************/
+
+#define USB_OTG_DOEPCTL_MPSIZ 0x000007FFU /*!< Maximum packet size */ /*!<Bit 1 */
+#define USB_OTG_DOEPCTL_USBAEP 0x00008000U /*!< USB active endpoint */
+#define USB_OTG_DOEPCTL_NAKSTS 0x00020000U /*!< NAK status */
+#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM 0x10000000U /*!< Set DATA0 PID */
+#define USB_OTG_DOEPCTL_SODDFRM 0x20000000U /*!< Set odd frame */
+#define USB_OTG_DOEPCTL_EPTYP 0x000C0000U /*!< Endpoint type */
+#define USB_OTG_DOEPCTL_EPTYP_0 0x00040000U /*!<Bit 0 */
+#define USB_OTG_DOEPCTL_EPTYP_1 0x00080000U /*!<Bit 1 */
+#define USB_OTG_DOEPCTL_SNPM 0x00100000U /*!< Snoop mode */
+#define USB_OTG_DOEPCTL_STALL 0x00200000U /*!< STALL handshake */
+#define USB_OTG_DOEPCTL_CNAK 0x04000000U /*!< Clear NAK */
+#define USB_OTG_DOEPCTL_SNAK 0x08000000U /*!< Set NAK */
+#define USB_OTG_DOEPCTL_EPDIS 0x40000000U /*!< Endpoint disable */
+#define USB_OTG_DOEPCTL_EPENA 0x80000000U /*!< Endpoint enable */
+
+/******************** Bit definition forUSB_OTG_DOEPINT register ********************/
+#define USB_OTG_DOEPINT_XFRC 0x00000001U /*!< Transfer completed interrupt */
+#define USB_OTG_DOEPINT_EPDISD 0x00000002U /*!< Endpoint disabled interrupt */
+#define USB_OTG_DOEPINT_STUP 0x00000008U /*!< SETUP phase done */
+#define USB_OTG_DOEPINT_OTEPDIS 0x00000010U /*!< OUT token received when endpoint disabled */
+#define USB_OTG_DOEPINT_B2BSTUP 0x00000040U /*!< Back-to-back SETUP packets received */
+#define USB_OTG_DOEPINT_NYET 0x00004000U /*!< NYET interrupt */
+
+/******************** Bit definition forUSB_OTG_DOEPTSIZ register ********************/
+
+#define USB_OTG_DOEPTSIZ_XFRSIZ 0x0007FFFFU /*!< Transfer size */
+#define USB_OTG_DOEPTSIZ_PKTCNT 0x1FF80000U /*!< Packet count */
+
+#define USB_OTG_DOEPTSIZ_STUPCNT 0x60000000U /*!< SETUP packet count */
+#define USB_OTG_DOEPTSIZ_STUPCNT_0 0x20000000U /*!<Bit 0 */
+#define USB_OTG_DOEPTSIZ_STUPCNT_1 0x40000000U /*!<Bit 1 */
+
+/******************** Bit definition for PCGCCTL register ********************/
+#define USB_OTG_PCGCCTL_STOPCLK 0x00000001U /*!< SETUP packet count */
+#define USB_OTG_PCGCCTL_GATECLK 0x00000002U /*!<Bit 0 */
+#define USB_OTG_PCGCCTL_PHYSUSP 0x00000010U /*!<Bit 1 */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup Exported_macros
+ * @{
+ */
+
+/******************************* ADC Instances ********************************/
+#define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) || \
+ ((INSTANCE) == ADC2) || \
+ ((INSTANCE) == ADC3))
+
+/******************************* CAN Instances ********************************/
+#define IS_CAN_ALL_INSTANCE(INSTANCE) (((INSTANCE) == CAN1) || \
+ ((INSTANCE) == CAN2))
+
+/******************************* CRC Instances ********************************/
+#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
+
+/******************************* DAC Instances ********************************/
+#define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC)
+
+/******************************** DMA Instances *******************************/
+#define IS_DMA_STREAM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0) || \
+ ((INSTANCE) == DMA1_Stream1) || \
+ ((INSTANCE) == DMA1_Stream2) || \
+ ((INSTANCE) == DMA1_Stream3) || \
+ ((INSTANCE) == DMA1_Stream4) || \
+ ((INSTANCE) == DMA1_Stream5) || \
+ ((INSTANCE) == DMA1_Stream6) || \
+ ((INSTANCE) == DMA1_Stream7) || \
+ ((INSTANCE) == DMA2_Stream0) || \
+ ((INSTANCE) == DMA2_Stream1) || \
+ ((INSTANCE) == DMA2_Stream2) || \
+ ((INSTANCE) == DMA2_Stream3) || \
+ ((INSTANCE) == DMA2_Stream4) || \
+ ((INSTANCE) == DMA2_Stream5) || \
+ ((INSTANCE) == DMA2_Stream6) || \
+ ((INSTANCE) == DMA2_Stream7))
+
+/******************************* GPIO Instances *******************************/
+#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
+ ((INSTANCE) == GPIOB) || \
+ ((INSTANCE) == GPIOC) || \
+ ((INSTANCE) == GPIOD) || \
+ ((INSTANCE) == GPIOE) || \
+ ((INSTANCE) == GPIOF) || \
+ ((INSTANCE) == GPIOG) || \
+ ((INSTANCE) == GPIOH) || \
+ ((INSTANCE) == GPIOI))
+
+/******************************** I2C Instances *******************************/
+#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
+ ((INSTANCE) == I2C2) || \
+ ((INSTANCE) == I2C3))
+
+/******************************** I2S Instances *******************************/
+#define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI2) || \
+ ((INSTANCE) == SPI3))
+
+/*************************** I2S Extended Instances ***************************/
+#define IS_I2S_ALL_INSTANCE_EXT(PERIPH) (((INSTANCE) == SPI2) || \
+ ((INSTANCE) == SPI3) || \
+ ((INSTANCE) == I2S2ext) || \
+ ((INSTANCE) == I2S3ext))
+
+/******************************* RNG Instances ********************************/
+#define IS_RNG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RNG)
+
+/****************************** RTC Instances *********************************/
+#define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
+
+/******************************** SPI Instances *******************************/
+#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
+ ((INSTANCE) == SPI2) || \
+ ((INSTANCE) == SPI3))
+
+/*************************** SPI Extended Instances ***************************/
+#define IS_SPI_ALL_INSTANCE_EXT(INSTANCE) (((INSTANCE) == SPI1) || \
+ ((INSTANCE) == SPI2) || \
+ ((INSTANCE) == SPI3) || \
+ ((INSTANCE) == I2S2ext) || \
+ ((INSTANCE) == I2S3ext))
+
+/****************** TIM Instances : All supported instances *******************/
+#define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM6) || \
+ ((INSTANCE) == TIM7) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM9) || \
+ ((INSTANCE) == TIM10) || \
+ ((INSTANCE) == TIM11) || \
+ ((INSTANCE) == TIM12) || \
+ ((INSTANCE) == TIM13) || \
+ ((INSTANCE) == TIM14))
+
+/************* TIM Instances : at least 1 capture/compare channel *************/
+#define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM9) || \
+ ((INSTANCE) == TIM10) || \
+ ((INSTANCE) == TIM11) || \
+ ((INSTANCE) == TIM12) || \
+ ((INSTANCE) == TIM13) || \
+ ((INSTANCE) == TIM14))
+
+/************ TIM Instances : at least 2 capture/compare channels *************/
+#define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM9) || \
+ ((INSTANCE) == TIM12))
+
+/************ TIM Instances : at least 3 capture/compare channels *************/
+#define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8))
+
+/************ TIM Instances : at least 4 capture/compare channels *************/
+#define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8))
+
+/******************** TIM Instances : Advanced-control timers *****************/
+#define IS_TIM_ADVANCED_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM8))
+
+/******************* TIM Instances : Timer input XOR function *****************/
+#define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8))
+
+/****************** TIM Instances : DMA requests generation (UDE) *************/
+#define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM6) || \
+ ((INSTANCE) == TIM7) || \
+ ((INSTANCE) == TIM8))
+
+/************ TIM Instances : DMA requests generation (CCxDE) *****************/
+#define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8))
+
+/************ TIM Instances : DMA requests generation (COMDE) *****************/
+#define IS_TIM_CCDMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8))
+
+/******************** TIM Instances : DMA burst feature ***********************/
+#define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8))
+
+/****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/
+#define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM6) || \
+ ((INSTANCE) == TIM7) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM9) || \
+ ((INSTANCE) == TIM12))
+
+/*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
+#define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM9) || \
+ ((INSTANCE) == TIM12))
+
+/********************** TIM Instances : 32 bit Counter ************************/
+#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)(((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM5))
+
+/***************** TIM Instances : external trigger input availabe ************/
+#define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8))
+
+/****************** TIM Instances : remapping capability **********************/
+#define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM11))
+
+/******************* TIM Instances : output(s) available **********************/
+#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
+ ((((INSTANCE) == TIM1) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM2) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM3) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM4) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM5) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM8) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM9) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2))) \
+ || \
+ (((INSTANCE) == TIM10) && \
+ (((CHANNEL) == TIM_CHANNEL_1))) \
+ || \
+ (((INSTANCE) == TIM11) && \
+ (((CHANNEL) == TIM_CHANNEL_1))) \
+ || \
+ (((INSTANCE) == TIM12) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2))) \
+ || \
+ (((INSTANCE) == TIM13) && \
+ (((CHANNEL) == TIM_CHANNEL_1))) \
+ || \
+ (((INSTANCE) == TIM14) && \
+ (((CHANNEL) == TIM_CHANNEL_1))))
+
+/************ TIM Instances : complementary output(s) available ***************/
+#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
+ ((((INSTANCE) == TIM1) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3))) \
+ || \
+ (((INSTANCE) == TIM8) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3))))
+
+/******************** USART Instances : Synchronous mode **********************/
+#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3) || \
+ ((INSTANCE) == USART6))
+
+/******************** UART Instances : Asynchronous mode **********************/
+#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3) || \
+ ((INSTANCE) == UART4) || \
+ ((INSTANCE) == UART5) || \
+ ((INSTANCE) == USART6))
+
+/****************** UART Instances : Hardware Flow control ********************/
+#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3) || \
+ ((INSTANCE) == USART6))
+
+/********************* UART Instances : Smard card mode ***********************/
+#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3) || \
+ ((INSTANCE) == USART6))
+
+/*********************** UART Instances : IRDA mode ***************************/
+#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3) || \
+ ((INSTANCE) == UART4) || \
+ ((INSTANCE) == UART5) || \
+ ((INSTANCE) == USART6))
+
+/*********************** PCD Instances ****************************************/
+/*********************** PCD Instances ****************************************/
+#define IS_PCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS) || \
+ ((INSTANCE) == USB_OTG_HS))
+
+/*********************** HCD Instances ****************************************/
+#define IS_HCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS) || \
+ ((INSTANCE) == USB_OTG_HS))
+
+/*********************** HCD Instances ****************************************/
+#define IS_HCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS) || \
+ ((INSTANCE) == USB_OTG_HS))
+
+/****************************** IWDG Instances ********************************/
+#define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
+
+/****************************** WWDG Instances ********************************/
+#define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
+
+/****************************** SDIO Instances ********************************/
+#define IS_SDIO_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SDIO)
+
+/****************************** USB Exported Constants ************************/
+#define USB_OTG_FS_HOST_MAX_CHANNEL_NBR 8U
+#define USB_OTG_FS_MAX_IN_ENDPOINTS 4U /* Including EP0 */
+#define USB_OTG_FS_MAX_OUT_ENDPOINTS 4U /* Including EP0 */
+#define USB_OTG_FS_TOTAL_FIFO_SIZE 1280U /* in Bytes */
+
+#define USB_OTG_HS_HOST_MAX_CHANNEL_NBR 12U
+#define USB_OTG_HS_MAX_IN_ENDPOINTS 6U /* Including EP0 */
+#define USB_OTG_HS_MAX_OUT_ENDPOINTS 6U /* Including EP0 */
+#define USB_OTG_HS_TOTAL_FIFO_SIZE 4096U /* in Bytes */
+
+/******************************************************************************/
+/* For a painless codes migration between the STM32F4xx device product */
+/* lines, the aliases defined below are put in place to overcome the */
+/* differences in the interrupt handlers and IRQn definitions. */
+/* No need to update developed interrupt code when moving across */
+/* product lines within the same STM32F4 Family */
+/******************************************************************************/
+
+/* Aliases for __IRQn */
+#define FMC_IRQn FSMC_IRQn
+
+/* Aliases for __IRQHandler */
+#define FMC_IRQHandler FSMC_IRQHandler
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* __STM32F415xx_H */
+
+
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Device/ST/STM32F4xx/Include/stm32f417xx.h b/Device/ST/STM32F4xx/Include/stm32f417xx.h
new file mode 100644
index 0000000..6af37d1
--- /dev/null
+++ b/Device/ST/STM32F4xx/Include/stm32f417xx.h
@@ -0,0 +1,8328 @@
+/**
+ ******************************************************************************
+ * @file stm32f417xx.h
+ * @author MCD Application Team
+ * @version V2.5.0
+ * @date 22-April-2016
+ * @brief CMSIS STM32F417xx Device Peripheral Access Layer Header File.
+ *
+ * This file contains:
+ * - Data structures and the address mapping for all peripherals
+ * - peripherals registers declarations and bits definition
+ * - Macros to access peripheral’s registers hardware
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/** @addtogroup CMSIS
+ * @{
+ */
+
+/** @addtogroup stm32f417xx
+ * @{
+ */
+
+#ifndef __STM32F417xx_H
+#define __STM32F417xx_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif /* __cplusplus */
+
+
+/** @addtogroup Configuration_section_for_CMSIS
+ * @{
+ */
+
+/**
+ * @brief Configuration of the Cortex-M4 Processor and Core Peripherals
+ */
+#define __CM4_REV 0x0001U /*!< Core revision r0p1 */
+#define __MPU_PRESENT 1U /*!< STM32F4XX provides an MPU */
+#define __NVIC_PRIO_BITS 4U /*!< STM32F4XX uses 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */
+#define __FPU_PRESENT 1U /*!< FPU present */
+
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_interrupt_number_definition
+ * @{
+ */
+
+/**
+ * @brief STM32F4XX Interrupt Number Definition, according to the selected device
+ * in @ref Library_configuration_section
+ */
+typedef enum
+{
+/****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/
+ NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
+ MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */
+ BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */
+ UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */
+ SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */
+ DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */
+ PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */
+ SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */
+/****** STM32 specific Interrupt Numbers **********************************************************************/
+ WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
+ PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */
+ TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */
+ RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */
+ FLASH_IRQn = 4, /*!< FLASH global Interrupt */
+ RCC_IRQn = 5, /*!< RCC global Interrupt */
+ EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */
+ EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */
+ EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */
+ EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */
+ EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */
+ DMA1_Stream0_IRQn = 11, /*!< DMA1 Stream 0 global Interrupt */
+ DMA1_Stream1_IRQn = 12, /*!< DMA1 Stream 1 global Interrupt */
+ DMA1_Stream2_IRQn = 13, /*!< DMA1 Stream 2 global Interrupt */
+ DMA1_Stream3_IRQn = 14, /*!< DMA1 Stream 3 global Interrupt */
+ DMA1_Stream4_IRQn = 15, /*!< DMA1 Stream 4 global Interrupt */
+ DMA1_Stream5_IRQn = 16, /*!< DMA1 Stream 5 global Interrupt */
+ DMA1_Stream6_IRQn = 17, /*!< DMA1 Stream 6 global Interrupt */
+ ADC_IRQn = 18, /*!< ADC1, ADC2 and ADC3 global Interrupts */
+ CAN1_TX_IRQn = 19, /*!< CAN1 TX Interrupt */
+ CAN1_RX0_IRQn = 20, /*!< CAN1 RX0 Interrupt */
+ CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */
+ CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */
+ EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
+ TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break interrupt and TIM9 global interrupt */
+ TIM1_UP_TIM10_IRQn = 25, /*!< TIM1 Update Interrupt and TIM10 global interrupt */
+ TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */
+ TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
+ TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
+ TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
+ TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
+ I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
+ I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
+ I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
+ I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
+ SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
+ SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
+ USART1_IRQn = 37, /*!< USART1 global Interrupt */
+ USART2_IRQn = 38, /*!< USART2 global Interrupt */
+ USART3_IRQn = 39, /*!< USART3 global Interrupt */
+ EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
+ RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */
+ OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS Wakeup through EXTI line interrupt */
+ TIM8_BRK_TIM12_IRQn = 43, /*!< TIM8 Break Interrupt and TIM12 global interrupt */
+ TIM8_UP_TIM13_IRQn = 44, /*!< TIM8 Update Interrupt and TIM13 global interrupt */
+ TIM8_TRG_COM_TIM14_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */
+ TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */
+ DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */
+ FSMC_IRQn = 48, /*!< FSMC global Interrupt */
+ SDIO_IRQn = 49, /*!< SDIO global Interrupt */
+ TIM5_IRQn = 50, /*!< TIM5 global Interrupt */
+ SPI3_IRQn = 51, /*!< SPI3 global Interrupt */
+ UART4_IRQn = 52, /*!< UART4 global Interrupt */
+ UART5_IRQn = 53, /*!< UART5 global Interrupt */
+ TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC1&2 underrun error interrupts */
+ TIM7_IRQn = 55, /*!< TIM7 global interrupt */
+ DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */
+ DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */
+ DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */
+ DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */
+ DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */
+ ETH_IRQn = 61, /*!< Ethernet global Interrupt */
+ ETH_WKUP_IRQn = 62, /*!< Ethernet Wakeup through EXTI line Interrupt */
+ CAN2_TX_IRQn = 63, /*!< CAN2 TX Interrupt */
+ CAN2_RX0_IRQn = 64, /*!< CAN2 RX0 Interrupt */
+ CAN2_RX1_IRQn = 65, /*!< CAN2 RX1 Interrupt */
+ CAN2_SCE_IRQn = 66, /*!< CAN2 SCE Interrupt */
+ OTG_FS_IRQn = 67, /*!< USB OTG FS global Interrupt */
+ DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */
+ DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */
+ DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */
+ USART6_IRQn = 71, /*!< USART6 global interrupt */
+ I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */
+ I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */
+ OTG_HS_EP1_OUT_IRQn = 74, /*!< USB OTG HS End Point 1 Out global interrupt */
+ OTG_HS_EP1_IN_IRQn = 75, /*!< USB OTG HS End Point 1 In global interrupt */
+ OTG_HS_WKUP_IRQn = 76, /*!< USB OTG HS Wakeup through EXTI interrupt */
+ OTG_HS_IRQn = 77, /*!< USB OTG HS global interrupt */
+ DCMI_IRQn = 78, /*!< DCMI global interrupt */
+ CRYP_IRQn = 79, /*!< CRYP crypto global interrupt */
+ HASH_RNG_IRQn = 80, /*!< Hash and Rng global interrupt */
+ FPU_IRQn = 81 /*!< FPU global interrupt */
+} IRQn_Type;
+
+/**
+ * @}
+ */
+
+#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
+#include "system_stm32f4xx.h"
+#include <stdint.h>
+
+/** @addtogroup Peripheral_registers_structures
+ * @{
+ */
+
+/**
+ * @brief Analog to Digital Converter
+ */
+
+typedef struct
+{
+ __IO uint32_t SR; /*!< ADC status register, Address offset: 0x00 */
+ __IO uint32_t CR1; /*!< ADC control register 1, Address offset: 0x04 */
+ __IO uint32_t CR2; /*!< ADC control register 2, Address offset: 0x08 */
+ __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x0C */
+ __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x10 */
+ __IO uint32_t JOFR1; /*!< ADC injected channel data offset register 1, Address offset: 0x14 */
+ __IO uint32_t JOFR2; /*!< ADC injected channel data offset register 2, Address offset: 0x18 */
+ __IO uint32_t JOFR3; /*!< ADC injected channel data offset register 3, Address offset: 0x1C */
+ __IO uint32_t JOFR4; /*!< ADC injected channel data offset register 4, Address offset: 0x20 */
+ __IO uint32_t HTR; /*!< ADC watchdog higher threshold register, Address offset: 0x24 */
+ __IO uint32_t LTR; /*!< ADC watchdog lower threshold register, Address offset: 0x28 */
+ __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x2C */
+ __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x30 */
+ __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x34 */
+ __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x38*/
+ __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x3C */
+ __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x40 */
+ __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x44 */
+ __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x48 */
+ __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x4C */
+} ADC_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1 base address + 0x300 */
+ __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1 base address + 0x304 */
+ __IO uint32_t CDR; /*!< ADC common regular data register for dual
+ AND triple modes, Address offset: ADC1 base address + 0x308 */
+} ADC_Common_TypeDef;
+
+
+/**
+ * @brief Controller Area Network TxMailBox
+ */
+
+typedef struct
+{
+ __IO uint32_t TIR; /*!< CAN TX mailbox identifier register */
+ __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */
+ __IO uint32_t TDLR; /*!< CAN mailbox data low register */
+ __IO uint32_t TDHR; /*!< CAN mailbox data high register */
+} CAN_TxMailBox_TypeDef;
+
+/**
+ * @brief Controller Area Network FIFOMailBox
+ */
+
+typedef struct
+{
+ __IO uint32_t RIR; /*!< CAN receive FIFO mailbox identifier register */
+ __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */
+ __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */
+ __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */
+} CAN_FIFOMailBox_TypeDef;
+
+/**
+ * @brief Controller Area Network FilterRegister
+ */
+
+typedef struct
+{
+ __IO uint32_t FR1; /*!< CAN Filter bank register 1 */
+ __IO uint32_t FR2; /*!< CAN Filter bank register 1 */
+} CAN_FilterRegister_TypeDef;
+
+/**
+ * @brief Controller Area Network
+ */
+
+typedef struct
+{
+ __IO uint32_t MCR; /*!< CAN master control register, Address offset: 0x00 */
+ __IO uint32_t MSR; /*!< CAN master status register, Address offset: 0x04 */
+ __IO uint32_t TSR; /*!< CAN transmit status register, Address offset: 0x08 */
+ __IO uint32_t RF0R; /*!< CAN receive FIFO 0 register, Address offset: 0x0C */
+ __IO uint32_t RF1R; /*!< CAN receive FIFO 1 register, Address offset: 0x10 */
+ __IO uint32_t IER; /*!< CAN interrupt enable register, Address offset: 0x14 */
+ __IO uint32_t ESR; /*!< CAN error status register, Address offset: 0x18 */
+ __IO uint32_t BTR; /*!< CAN bit timing register, Address offset: 0x1C */
+ uint32_t RESERVED0[88]; /*!< Reserved, 0x020 - 0x17F */
+ CAN_TxMailBox_TypeDef sTxMailBox[3]; /*!< CAN Tx MailBox, Address offset: 0x180 - 0x1AC */
+ CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; /*!< CAN FIFO MailBox, Address offset: 0x1B0 - 0x1CC */
+ uint32_t RESERVED1[12]; /*!< Reserved, 0x1D0 - 0x1FF */
+ __IO uint32_t FMR; /*!< CAN filter master register, Address offset: 0x200 */
+ __IO uint32_t FM1R; /*!< CAN filter mode register, Address offset: 0x204 */
+ uint32_t RESERVED2; /*!< Reserved, 0x208 */
+ __IO uint32_t FS1R; /*!< CAN filter scale register, Address offset: 0x20C */
+ uint32_t RESERVED3; /*!< Reserved, 0x210 */
+ __IO uint32_t FFA1R; /*!< CAN filter FIFO assignment register, Address offset: 0x214 */
+ uint32_t RESERVED4; /*!< Reserved, 0x218 */
+ __IO uint32_t FA1R; /*!< CAN filter activation register, Address offset: 0x21C */
+ uint32_t RESERVED5[8]; /*!< Reserved, 0x220-0x23F */
+ CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register, Address offset: 0x240-0x31C */
+} CAN_TypeDef;
+
+/**
+ * @brief CRC calculation unit
+ */
+
+typedef struct
+{
+ __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
+ __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
+ uint8_t RESERVED0; /*!< Reserved, 0x05 */
+ uint16_t RESERVED1; /*!< Reserved, 0x06 */
+ __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
+} CRC_TypeDef;
+
+/**
+ * @brief Digital to Analog Converter
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */
+ __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */
+ __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
+ __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */
+ __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */
+ __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
+ __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */
+ __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */
+ __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */
+ __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */
+ __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */
+ __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */
+ __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */
+ __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */
+} DAC_TypeDef;
+
+/**
+ * @brief Debug MCU
+ */
+
+typedef struct
+{
+ __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
+ __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
+ __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */
+ __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */
+}DBGMCU_TypeDef;
+
+/**
+ * @brief DCMI
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< DCMI control register 1, Address offset: 0x00 */
+ __IO uint32_t SR; /*!< DCMI status register, Address offset: 0x04 */
+ __IO uint32_t RISR; /*!< DCMI raw interrupt status register, Address offset: 0x08 */
+ __IO uint32_t IER; /*!< DCMI interrupt enable register, Address offset: 0x0C */
+ __IO uint32_t MISR; /*!< DCMI masked interrupt status register, Address offset: 0x10 */
+ __IO uint32_t ICR; /*!< DCMI interrupt clear register, Address offset: 0x14 */
+ __IO uint32_t ESCR; /*!< DCMI embedded synchronization code register, Address offset: 0x18 */
+ __IO uint32_t ESUR; /*!< DCMI embedded synchronization unmask register, Address offset: 0x1C */
+ __IO uint32_t CWSTRTR; /*!< DCMI crop window start, Address offset: 0x20 */
+ __IO uint32_t CWSIZER; /*!< DCMI crop window size, Address offset: 0x24 */
+ __IO uint32_t DR; /*!< DCMI data register, Address offset: 0x28 */
+} DCMI_TypeDef;
+
+/**
+ * @brief DMA Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< DMA stream x configuration register */
+ __IO uint32_t NDTR; /*!< DMA stream x number of data register */
+ __IO uint32_t PAR; /*!< DMA stream x peripheral address register */
+ __IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */
+ __IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */
+ __IO uint32_t FCR; /*!< DMA stream x FIFO control register */
+} DMA_Stream_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t LISR; /*!< DMA low interrupt status register, Address offset: 0x00 */
+ __IO uint32_t HISR; /*!< DMA high interrupt status register, Address offset: 0x04 */
+ __IO uint32_t LIFCR; /*!< DMA low interrupt flag clear register, Address offset: 0x08 */
+ __IO uint32_t HIFCR; /*!< DMA high interrupt flag clear register, Address offset: 0x0C */
+} DMA_TypeDef;
+
+
+/**
+ * @brief Ethernet MAC
+ */
+
+typedef struct
+{
+ __IO uint32_t MACCR;
+ __IO uint32_t MACFFR;
+ __IO uint32_t MACHTHR;
+ __IO uint32_t MACHTLR;
+ __IO uint32_t MACMIIAR;
+ __IO uint32_t MACMIIDR;
+ __IO uint32_t MACFCR;
+ __IO uint32_t MACVLANTR; /* 8 */
+ uint32_t RESERVED0[2];
+ __IO uint32_t MACRWUFFR; /* 11 */
+ __IO uint32_t MACPMTCSR;
+ uint32_t RESERVED1[2];
+ __IO uint32_t MACSR; /* 15 */
+ __IO uint32_t MACIMR;
+ __IO uint32_t MACA0HR;
+ __IO uint32_t MACA0LR;
+ __IO uint32_t MACA1HR;
+ __IO uint32_t MACA1LR;
+ __IO uint32_t MACA2HR;
+ __IO uint32_t MACA2LR;
+ __IO uint32_t MACA3HR;
+ __IO uint32_t MACA3LR; /* 24 */
+ uint32_t RESERVED2[40];
+ __IO uint32_t MMCCR; /* 65 */
+ __IO uint32_t MMCRIR;
+ __IO uint32_t MMCTIR;
+ __IO uint32_t MMCRIMR;
+ __IO uint32_t MMCTIMR; /* 69 */
+ uint32_t RESERVED3[14];
+ __IO uint32_t MMCTGFSCCR; /* 84 */
+ __IO uint32_t MMCTGFMSCCR;
+ uint32_t RESERVED4[5];
+ __IO uint32_t MMCTGFCR;
+ uint32_t RESERVED5[10];
+ __IO uint32_t MMCRFCECR;
+ __IO uint32_t MMCRFAECR;
+ uint32_t RESERVED6[10];
+ __IO uint32_t MMCRGUFCR;
+ uint32_t RESERVED7[334];
+ __IO uint32_t PTPTSCR;
+ __IO uint32_t PTPSSIR;
+ __IO uint32_t PTPTSHR;
+ __IO uint32_t PTPTSLR;
+ __IO uint32_t PTPTSHUR;
+ __IO uint32_t PTPTSLUR;
+ __IO uint32_t PTPTSAR;
+ __IO uint32_t PTPTTHR;
+ __IO uint32_t PTPTTLR;
+ __IO uint32_t RESERVED8;
+ __IO uint32_t PTPTSSR;
+ uint32_t RESERVED9[565];
+ __IO uint32_t DMABMR;
+ __IO uint32_t DMATPDR;
+ __IO uint32_t DMARPDR;
+ __IO uint32_t DMARDLAR;
+ __IO uint32_t DMATDLAR;
+ __IO uint32_t DMASR;
+ __IO uint32_t DMAOMR;
+ __IO uint32_t DMAIER;
+ __IO uint32_t DMAMFBOCR;
+ __IO uint32_t DMARSWTR;
+ uint32_t RESERVED10[8];
+ __IO uint32_t DMACHTDR;
+ __IO uint32_t DMACHRDR;
+ __IO uint32_t DMACHTBAR;
+ __IO uint32_t DMACHRBAR;
+} ETH_TypeDef;
+
+/**
+ * @brief External Interrupt/Event Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t IMR; /*!< EXTI Interrupt mask register, Address offset: 0x00 */
+ __IO uint32_t EMR; /*!< EXTI Event mask register, Address offset: 0x04 */
+ __IO uint32_t RTSR; /*!< EXTI Rising trigger selection register, Address offset: 0x08 */
+ __IO uint32_t FTSR; /*!< EXTI Falling trigger selection register, Address offset: 0x0C */
+ __IO uint32_t SWIER; /*!< EXTI Software interrupt event register, Address offset: 0x10 */
+ __IO uint32_t PR; /*!< EXTI Pending register, Address offset: 0x14 */
+} EXTI_TypeDef;
+
+/**
+ * @brief FLASH Registers
+ */
+
+typedef struct
+{
+ __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */
+ __IO uint32_t KEYR; /*!< FLASH key register, Address offset: 0x04 */
+ __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x08 */
+ __IO uint32_t SR; /*!< FLASH status register, Address offset: 0x0C */
+ __IO uint32_t CR; /*!< FLASH control register, Address offset: 0x10 */
+ __IO uint32_t OPTCR; /*!< FLASH option control register , Address offset: 0x14 */
+ __IO uint32_t OPTCR1; /*!< FLASH option control register 1, Address offset: 0x18 */
+} FLASH_TypeDef;
+
+
+/**
+ * @brief Flexible Static Memory Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */
+} FSMC_Bank1_TypeDef;
+
+/**
+ * @brief Flexible Static Memory Controller Bank1E
+ */
+
+typedef struct
+{
+ __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */
+} FSMC_Bank1E_TypeDef;
+
+/**
+ * @brief Flexible Static Memory Controller Bank2
+ */
+
+typedef struct
+{
+ __IO uint32_t PCR2; /*!< NAND Flash control register 2, Address offset: 0x60 */
+ __IO uint32_t SR2; /*!< NAND Flash FIFO status and interrupt register 2, Address offset: 0x64 */
+ __IO uint32_t PMEM2; /*!< NAND Flash Common memory space timing register 2, Address offset: 0x68 */
+ __IO uint32_t PATT2; /*!< NAND Flash Attribute memory space timing register 2, Address offset: 0x6C */
+ uint32_t RESERVED0; /*!< Reserved, 0x70 */
+ __IO uint32_t ECCR2; /*!< NAND Flash ECC result registers 2, Address offset: 0x74 */
+ uint32_t RESERVED1; /*!< Reserved, 0x78 */
+ uint32_t RESERVED2; /*!< Reserved, 0x7C */
+ __IO uint32_t PCR3; /*!< NAND Flash control register 3, Address offset: 0x80 */
+ __IO uint32_t SR3; /*!< NAND Flash FIFO status and interrupt register 3, Address offset: 0x84 */
+ __IO uint32_t PMEM3; /*!< NAND Flash Common memory space timing register 3, Address offset: 0x88 */
+ __IO uint32_t PATT3; /*!< NAND Flash Attribute memory space timing register 3, Address offset: 0x8C */
+ uint32_t RESERVED3; /*!< Reserved, 0x90 */
+ __IO uint32_t ECCR3; /*!< NAND Flash ECC result registers 3, Address offset: 0x94 */
+} FSMC_Bank2_3_TypeDef;
+
+/**
+ * @brief Flexible Static Memory Controller Bank4
+ */
+
+typedef struct
+{
+ __IO uint32_t PCR4; /*!< PC Card control register 4, Address offset: 0xA0 */
+ __IO uint32_t SR4; /*!< PC Card FIFO status and interrupt register 4, Address offset: 0xA4 */
+ __IO uint32_t PMEM4; /*!< PC Card Common memory space timing register 4, Address offset: 0xA8 */
+ __IO uint32_t PATT4; /*!< PC Card Attribute memory space timing register 4, Address offset: 0xAC */
+ __IO uint32_t PIO4; /*!< PC Card I/O space timing register 4, Address offset: 0xB0 */
+} FSMC_Bank4_TypeDef;
+
+
+/**
+ * @brief General Purpose I/O
+ */
+
+typedef struct
+{
+ __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
+ __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */
+ __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */
+ __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
+ __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
+ __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
+ __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */
+ __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
+ __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */
+} GPIO_TypeDef;
+
+/**
+ * @brief System configuration controller
+ */
+
+typedef struct
+{
+ __IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */
+ __IO uint32_t PMC; /*!< SYSCFG peripheral mode configuration register, Address offset: 0x04 */
+ __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
+ uint32_t RESERVED[2]; /*!< Reserved, 0x18-0x1C */
+ __IO uint32_t CMPCR; /*!< SYSCFG Compensation cell control register, Address offset: 0x20 */
+} SYSCFG_TypeDef;
+
+/**
+ * @brief Inter-integrated Circuit Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */
+ __IO uint32_t OAR1; /*!< I2C Own address register 1, Address offset: 0x08 */
+ __IO uint32_t OAR2; /*!< I2C Own address register 2, Address offset: 0x0C */
+ __IO uint32_t DR; /*!< I2C Data register, Address offset: 0x10 */
+ __IO uint32_t SR1; /*!< I2C Status register 1, Address offset: 0x14 */
+ __IO uint32_t SR2; /*!< I2C Status register 2, Address offset: 0x18 */
+ __IO uint32_t CCR; /*!< I2C Clock control register, Address offset: 0x1C */
+ __IO uint32_t TRISE; /*!< I2C TRISE register, Address offset: 0x20 */
+ __IO uint32_t FLTR; /*!< I2C FLTR register, Address offset: 0x24 */
+} I2C_TypeDef;
+
+/**
+ * @brief Independent WATCHDOG
+ */
+
+typedef struct
+{
+ __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */
+ __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */
+ __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */
+ __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */
+} IWDG_TypeDef;
+
+/**
+ * @brief Power Control
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */
+ __IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */
+} PWR_TypeDef;
+
+/**
+ * @brief Reset and Clock Control
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */
+ __IO uint32_t PLLCFGR; /*!< RCC PLL configuration register, Address offset: 0x04 */
+ __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x08 */
+ __IO uint32_t CIR; /*!< RCC clock interrupt register, Address offset: 0x0C */
+ __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x10 */
+ __IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x14 */
+ __IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0x18 */
+ uint32_t RESERVED0; /*!< Reserved, 0x1C */
+ __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x20 */
+ __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x24 */
+ uint32_t RESERVED1[2]; /*!< Reserved, 0x28-0x2C */
+ __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clock register, Address offset: 0x30 */
+ __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clock register, Address offset: 0x34 */
+ __IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clock register, Address offset: 0x38 */
+ uint32_t RESERVED2; /*!< Reserved, 0x3C */
+ __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x40 */
+ __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x44 */
+ uint32_t RESERVED3[2]; /*!< Reserved, 0x48-0x4C */
+ __IO uint32_t AHB1LPENR; /*!< RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 */
+ __IO uint32_t AHB2LPENR; /*!< RCC AHB2 peripheral clock enable in low power mode register, Address offset: 0x54 */
+ __IO uint32_t AHB3LPENR; /*!< RCC AHB3 peripheral clock enable in low power mode register, Address offset: 0x58 */
+ uint32_t RESERVED4; /*!< Reserved, 0x5C */
+ __IO uint32_t APB1LPENR; /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 */
+ __IO uint32_t APB2LPENR; /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 */
+ uint32_t RESERVED5[2]; /*!< Reserved, 0x68-0x6C */
+ __IO uint32_t BDCR; /*!< RCC Backup domain control register, Address offset: 0x70 */
+ __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x74 */
+ uint32_t RESERVED6[2]; /*!< Reserved, 0x78-0x7C */
+ __IO uint32_t SSCGR; /*!< RCC spread spectrum clock generation register, Address offset: 0x80 */
+ __IO uint32_t PLLI2SCFGR; /*!< RCC PLLI2S configuration register, Address offset: 0x84 */
+
+} RCC_TypeDef;
+
+/**
+ * @brief Real-Time Clock
+ */
+
+typedef struct
+{
+ __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
+ __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */
+ __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */
+ __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */
+ __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */
+ __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */
+ __IO uint32_t CALIBR; /*!< RTC calibration register, Address offset: 0x18 */
+ __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */
+ __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */
+ __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */
+ __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */
+ __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */
+ __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */
+ __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */
+ __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */
+ __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */
+ __IO uint32_t TAFCR; /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */
+ __IO uint32_t ALRMASSR;/*!< RTC alarm A sub second register, Address offset: 0x44 */
+ __IO uint32_t ALRMBSSR;/*!< RTC alarm B sub second register, Address offset: 0x48 */
+ uint32_t RESERVED7; /*!< Reserved, 0x4C */
+ __IO uint32_t BKP0R; /*!< RTC backup register 1, Address offset: 0x50 */
+ __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */
+ __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */
+ __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */
+ __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */
+ __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */
+ __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */
+ __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */
+ __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */
+ __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */
+ __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */
+ __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */
+ __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */
+ __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */
+ __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */
+ __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */
+ __IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */
+ __IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */
+ __IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */
+ __IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */
+} RTC_TypeDef;
+
+
+/**
+ * @brief SD host Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t POWER; /*!< SDIO power control register, Address offset: 0x00 */
+ __IO uint32_t CLKCR; /*!< SDI clock control register, Address offset: 0x04 */
+ __IO uint32_t ARG; /*!< SDIO argument register, Address offset: 0x08 */
+ __IO uint32_t CMD; /*!< SDIO command register, Address offset: 0x0C */
+ __I uint32_t RESPCMD; /*!< SDIO command response register, Address offset: 0x10 */
+ __I uint32_t RESP1; /*!< SDIO response 1 register, Address offset: 0x14 */
+ __I uint32_t RESP2; /*!< SDIO response 2 register, Address offset: 0x18 */
+ __I uint32_t RESP3; /*!< SDIO response 3 register, Address offset: 0x1C */
+ __I uint32_t RESP4; /*!< SDIO response 4 register, Address offset: 0x20 */
+ __IO uint32_t DTIMER; /*!< SDIO data timer register, Address offset: 0x24 */
+ __IO uint32_t DLEN; /*!< SDIO data length register, Address offset: 0x28 */
+ __IO uint32_t DCTRL; /*!< SDIO data control register, Address offset: 0x2C */
+ __I uint32_t DCOUNT; /*!< SDIO data counter register, Address offset: 0x30 */
+ __I uint32_t STA; /*!< SDIO status register, Address offset: 0x34 */
+ __IO uint32_t ICR; /*!< SDIO interrupt clear register, Address offset: 0x38 */
+ __IO uint32_t MASK; /*!< SDIO mask register, Address offset: 0x3C */
+ uint32_t RESERVED0[2]; /*!< Reserved, 0x40-0x44 */
+ __I uint32_t FIFOCNT; /*!< SDIO FIFO counter register, Address offset: 0x48 */
+ uint32_t RESERVED1[13]; /*!< Reserved, 0x4C-0x7C */
+ __IO uint32_t FIFO; /*!< SDIO data FIFO register, Address offset: 0x80 */
+} SDIO_TypeDef;
+
+/**
+ * @brief Serial Peripheral Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t CR1; /*!< SPI control register 1 (not used in I2S mode), Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< SPI control register 2, Address offset: 0x04 */
+ __IO uint32_t SR; /*!< SPI status register, Address offset: 0x08 */
+ __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */
+ __IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
+ __IO uint32_t RXCRCR; /*!< SPI RX CRC register (not used in I2S mode), Address offset: 0x14 */
+ __IO uint32_t TXCRCR; /*!< SPI TX CRC register (not used in I2S mode), Address offset: 0x18 */
+ __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */
+ __IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */
+} SPI_TypeDef;
+
+/**
+ * @brief TIM
+ */
+
+typedef struct
+{
+ __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
+ __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */
+ __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
+ __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
+ __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
+ __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
+ __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
+ __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
+ __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
+ __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */
+ __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
+ __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */
+ __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
+ __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
+ __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
+ __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
+ __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
+ __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
+ __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */
+ __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */
+} TIM_TypeDef;
+
+/**
+ * @brief Universal Synchronous Asynchronous Receiver Transmitter
+ */
+
+typedef struct
+{
+ __IO uint32_t SR; /*!< USART Status register, Address offset: 0x00 */
+ __IO uint32_t DR; /*!< USART Data register, Address offset: 0x04 */
+ __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x08 */
+ __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x0C */
+ __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x10 */
+ __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x14 */
+ __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x18 */
+} USART_TypeDef;
+
+/**
+ * @brief Window WATCHDOG
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
+ __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
+ __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
+} WWDG_TypeDef;
+
+/**
+ * @brief Crypto Processor
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< CRYP control register, Address offset: 0x00 */
+ __IO uint32_t SR; /*!< CRYP status register, Address offset: 0x04 */
+ __IO uint32_t DR; /*!< CRYP data input register, Address offset: 0x08 */
+ __IO uint32_t DOUT; /*!< CRYP data output register, Address offset: 0x0C */
+ __IO uint32_t DMACR; /*!< CRYP DMA control register, Address offset: 0x10 */
+ __IO uint32_t IMSCR; /*!< CRYP interrupt mask set/clear register, Address offset: 0x14 */
+ __IO uint32_t RISR; /*!< CRYP raw interrupt status register, Address offset: 0x18 */
+ __IO uint32_t MISR; /*!< CRYP masked interrupt status register, Address offset: 0x1C */
+ __IO uint32_t K0LR; /*!< CRYP key left register 0, Address offset: 0x20 */
+ __IO uint32_t K0RR; /*!< CRYP key right register 0, Address offset: 0x24 */
+ __IO uint32_t K1LR; /*!< CRYP key left register 1, Address offset: 0x28 */
+ __IO uint32_t K1RR; /*!< CRYP key right register 1, Address offset: 0x2C */
+ __IO uint32_t K2LR; /*!< CRYP key left register 2, Address offset: 0x30 */
+ __IO uint32_t K2RR; /*!< CRYP key right register 2, Address offset: 0x34 */
+ __IO uint32_t K3LR; /*!< CRYP key left register 3, Address offset: 0x38 */
+ __IO uint32_t K3RR; /*!< CRYP key right register 3, Address offset: 0x3C */
+ __IO uint32_t IV0LR; /*!< CRYP initialization vector left-word register 0, Address offset: 0x40 */
+ __IO uint32_t IV0RR; /*!< CRYP initialization vector right-word register 0, Address offset: 0x44 */
+ __IO uint32_t IV1LR; /*!< CRYP initialization vector left-word register 1, Address offset: 0x48 */
+ __IO uint32_t IV1RR; /*!< CRYP initialization vector right-word register 1, Address offset: 0x4C */
+ __IO uint32_t CSGCMCCM0R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 0, Address offset: 0x50 */
+ __IO uint32_t CSGCMCCM1R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 1, Address offset: 0x54 */
+ __IO uint32_t CSGCMCCM2R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 2, Address offset: 0x58 */
+ __IO uint32_t CSGCMCCM3R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 3, Address offset: 0x5C */
+ __IO uint32_t CSGCMCCM4R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 4, Address offset: 0x60 */
+ __IO uint32_t CSGCMCCM5R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 5, Address offset: 0x64 */
+ __IO uint32_t CSGCMCCM6R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 6, Address offset: 0x68 */
+ __IO uint32_t CSGCMCCM7R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 7, Address offset: 0x6C */
+ __IO uint32_t CSGCM0R; /*!< CRYP GCM/GMAC context swap register 0, Address offset: 0x70 */
+ __IO uint32_t CSGCM1R; /*!< CRYP GCM/GMAC context swap register 1, Address offset: 0x74 */
+ __IO uint32_t CSGCM2R; /*!< CRYP GCM/GMAC context swap register 2, Address offset: 0x78 */
+ __IO uint32_t CSGCM3R; /*!< CRYP GCM/GMAC context swap register 3, Address offset: 0x7C */
+ __IO uint32_t CSGCM4R; /*!< CRYP GCM/GMAC context swap register 4, Address offset: 0x80 */
+ __IO uint32_t CSGCM5R; /*!< CRYP GCM/GMAC context swap register 5, Address offset: 0x84 */
+ __IO uint32_t CSGCM6R; /*!< CRYP GCM/GMAC context swap register 6, Address offset: 0x88 */
+ __IO uint32_t CSGCM7R; /*!< CRYP GCM/GMAC context swap register 7, Address offset: 0x8C */
+} CRYP_TypeDef;
+
+/**
+ * @brief HASH
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< HASH control register, Address offset: 0x00 */
+ __IO uint32_t DIN; /*!< HASH data input register, Address offset: 0x04 */
+ __IO uint32_t STR; /*!< HASH start register, Address offset: 0x08 */
+ __IO uint32_t HR[5]; /*!< HASH digest registers, Address offset: 0x0C-0x1C */
+ __IO uint32_t IMR; /*!< HASH interrupt enable register, Address offset: 0x20 */
+ __IO uint32_t SR; /*!< HASH status register, Address offset: 0x24 */
+ uint32_t RESERVED[52]; /*!< Reserved, 0x28-0xF4 */
+ __IO uint32_t CSR[54]; /*!< HASH context swap registers, Address offset: 0x0F8-0x1CC */
+} HASH_TypeDef;
+
+/**
+ * @brief HASH_DIGEST
+ */
+
+typedef struct
+{
+ __IO uint32_t HR[8]; /*!< HASH digest registers, Address offset: 0x310-0x32C */
+} HASH_DIGEST_TypeDef;
+
+/**
+ * @brief RNG
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */
+ __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */
+ __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */
+} RNG_TypeDef;
+
+
+
+/**
+ * @brief __USB_OTG_Core_register
+ */
+typedef struct
+{
+ __IO uint32_t GOTGCTL; /*!< USB_OTG Control and Status Register 000h*/
+ __IO uint32_t GOTGINT; /*!< USB_OTG Interrupt Register 004h*/
+ __IO uint32_t GAHBCFG; /*!< Core AHB Configuration Register 008h*/
+ __IO uint32_t GUSBCFG; /*!< Core USB Configuration Register 00Ch*/
+ __IO uint32_t GRSTCTL; /*!< Core Reset Register 010h*/
+ __IO uint32_t GINTSTS; /*!< Core Interrupt Register 014h*/
+ __IO uint32_t GINTMSK; /*!< Core Interrupt Mask Register 018h*/
+ __IO uint32_t GRXSTSR; /*!< Receive Sts Q Read Register 01Ch*/
+ __IO uint32_t GRXSTSP; /*!< Receive Sts Q Read & POP Register 020h*/
+ __IO uint32_t GRXFSIZ; /* Receive FIFO Size Register 024h*/
+ __IO uint32_t DIEPTXF0_HNPTXFSIZ; /*!< EP0 / Non Periodic Tx FIFO Size Register 028h*/
+ __IO uint32_t HNPTXSTS; /*!< Non Periodic Tx FIFO/Queue Sts reg 02Ch*/
+ uint32_t Reserved30[2]; /* Reserved 030h*/
+ __IO uint32_t GCCFG; /* General Purpose IO Register 038h*/
+ __IO uint32_t CID; /* User ID Register 03Ch*/
+ uint32_t Reserved40[48]; /* Reserved 040h-0FFh*/
+ __IO uint32_t HPTXFSIZ; /* Host Periodic Tx FIFO Size Reg 100h*/
+ __IO uint32_t DIEPTXF[0x0F];/* dev Periodic Transmit FIFO */
+}
+USB_OTG_GlobalTypeDef;
+
+
+
+/**
+ * @brief __device_Registers
+ */
+typedef struct
+{
+ __IO uint32_t DCFG; /* dev Configuration Register 800h*/
+ __IO uint32_t DCTL; /* dev Control Register 804h*/
+ __IO uint32_t DSTS; /* dev Status Register (RO) 808h*/
+ uint32_t Reserved0C; /* Reserved 80Ch*/
+ __IO uint32_t DIEPMSK; /* dev IN Endpoint Mask 810h*/
+ __IO uint32_t DOEPMSK; /* dev OUT Endpoint Mask 814h*/
+ __IO uint32_t DAINT; /* dev All Endpoints Itr Reg 818h*/
+ __IO uint32_t DAINTMSK; /* dev All Endpoints Itr Mask 81Ch*/
+ uint32_t Reserved20; /* Reserved 820h*/
+ uint32_t Reserved9; /* Reserved 824h*/
+ __IO uint32_t DVBUSDIS; /* dev VBUS discharge Register 828h*/
+ __IO uint32_t DVBUSPULSE; /* dev VBUS Pulse Register 82Ch*/
+ __IO uint32_t DTHRCTL; /* dev thr 830h*/
+ __IO uint32_t DIEPEMPMSK; /* dev empty msk 834h*/
+ __IO uint32_t DEACHINT; /* dedicated EP interrupt 838h*/
+ __IO uint32_t DEACHMSK; /* dedicated EP msk 83Ch*/
+ uint32_t Reserved40; /* dedicated EP mask 840h*/
+ __IO uint32_t DINEP1MSK; /* dedicated EP mask 844h*/
+ uint32_t Reserved44[15]; /* Reserved 844-87Ch*/
+ __IO uint32_t DOUTEP1MSK; /* dedicated EP msk 884h*/
+}
+USB_OTG_DeviceTypeDef;
+
+
+/**
+ * @brief __IN_Endpoint-Specific_Register
+ */
+typedef struct
+{
+ __IO uint32_t DIEPCTL; /* dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h*/
+ uint32_t Reserved04; /* Reserved 900h + (ep_num * 20h) + 04h*/
+ __IO uint32_t DIEPINT; /* dev IN Endpoint Itr Reg 900h + (ep_num * 20h) + 08h*/
+ uint32_t Reserved0C; /* Reserved 900h + (ep_num * 20h) + 0Ch*/
+ __IO uint32_t DIEPTSIZ; /* IN Endpoint Txfer Size 900h + (ep_num * 20h) + 10h*/
+ __IO uint32_t DIEPDMA; /* IN Endpoint DMA Address Reg 900h + (ep_num * 20h) + 14h*/
+ __IO uint32_t DTXFSTS;/*IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h*/
+ uint32_t Reserved18; /* Reserved 900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch*/
+}
+USB_OTG_INEndpointTypeDef;
+
+
+/**
+ * @brief __OUT_Endpoint-Specific_Registers
+ */
+typedef struct
+{
+ __IO uint32_t DOEPCTL; /* dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h*/
+ uint32_t Reserved04; /* Reserved B00h + (ep_num * 20h) + 04h*/
+ __IO uint32_t DOEPINT; /* dev OUT Endpoint Itr Reg B00h + (ep_num * 20h) + 08h*/
+ uint32_t Reserved0C; /* Reserved B00h + (ep_num * 20h) + 0Ch*/
+ __IO uint32_t DOEPTSIZ; /* dev OUT Endpoint Txfer Size B00h + (ep_num * 20h) + 10h*/
+ __IO uint32_t DOEPDMA; /* dev OUT Endpoint DMA Address B00h + (ep_num * 20h) + 14h*/
+ uint32_t Reserved18[2]; /* Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch*/
+}
+USB_OTG_OUTEndpointTypeDef;
+
+
+/**
+ * @brief __Host_Mode_Register_Structures
+ */
+typedef struct
+{
+ __IO uint32_t HCFG; /* Host Configuration Register 400h*/
+ __IO uint32_t HFIR; /* Host Frame Interval Register 404h*/
+ __IO uint32_t HFNUM; /* Host Frame Nbr/Frame Remaining 408h*/
+ uint32_t Reserved40C; /* Reserved 40Ch*/
+ __IO uint32_t HPTXSTS; /* Host Periodic Tx FIFO/ Queue Status 410h*/
+ __IO uint32_t HAINT; /* Host All Channels Interrupt Register 414h*/
+ __IO uint32_t HAINTMSK; /* Host All Channels Interrupt Mask 418h*/
+}
+USB_OTG_HostTypeDef;
+
+
+/**
+ * @brief __Host_Channel_Specific_Registers
+ */
+typedef struct
+{
+ __IO uint32_t HCCHAR;
+ __IO uint32_t HCSPLT;
+ __IO uint32_t HCINT;
+ __IO uint32_t HCINTMSK;
+ __IO uint32_t HCTSIZ;
+ __IO uint32_t HCDMA;
+ uint32_t Reserved[2];
+}
+USB_OTG_HostChannelTypeDef;
+
+
+/**
+ * @brief Peripheral_memory_map
+ */
+#define FLASH_BASE 0x08000000U /*!< FLASH(up to 1 MB) base address in the alias region */
+#define CCMDATARAM_BASE 0x10000000U /*!< CCM(core coupled memory) data RAM(64 KB) base address in the alias region */
+#define SRAM1_BASE 0x20000000U /*!< SRAM1(112 KB) base address in the alias region */
+#define SRAM2_BASE 0x2001C000U /*!< SRAM2(16 KB) base address in the alias region */
+#define PERIPH_BASE 0x40000000U /*!< Peripheral base address in the alias region */
+#define BKPSRAM_BASE 0x40024000U /*!< Backup SRAM(4 KB) base address in the alias region */
+#define FSMC_R_BASE 0xA0000000U /*!< FSMC registers base address */
+#define SRAM1_BB_BASE 0x22000000U /*!< SRAM1(112 KB) base address in the bit-band region */
+#define SRAM2_BB_BASE 0x22380000U /*!< SRAM2(16 KB) base address in the bit-band region */
+#define PERIPH_BB_BASE 0x42000000U /*!< Peripheral base address in the bit-band region */
+#define BKPSRAM_BB_BASE 0x42480000U /*!< Backup SRAM(4 KB) base address in the bit-band region */
+#define FLASH_END 0x080FFFFFU /*!< FLASH end address */
+#define CCMDATARAM_END 0x1000FFFFU /*!< CCM data RAM end address */
+
+/* Legacy defines */
+#define SRAM_BASE SRAM1_BASE
+#define SRAM_BB_BASE SRAM1_BB_BASE
+
+
+/*!< Peripheral memory map */
+#define APB1PERIPH_BASE PERIPH_BASE
+#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000U)
+#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000U)
+#define AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000U)
+
+/*!< APB1 peripherals */
+#define TIM2_BASE (APB1PERIPH_BASE + 0x0000U)
+#define TIM3_BASE (APB1PERIPH_BASE + 0x0400U)
+#define TIM4_BASE (APB1PERIPH_BASE + 0x0800U)
+#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00U)
+#define TIM6_BASE (APB1PERIPH_BASE + 0x1000U)
+#define TIM7_BASE (APB1PERIPH_BASE + 0x1400U)
+#define TIM12_BASE (APB1PERIPH_BASE + 0x1800U)
+#define TIM13_BASE (APB1PERIPH_BASE + 0x1C00U)
+#define TIM14_BASE (APB1PERIPH_BASE + 0x2000U)
+#define RTC_BASE (APB1PERIPH_BASE + 0x2800U)
+#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00U)
+#define IWDG_BASE (APB1PERIPH_BASE + 0x3000U)
+#define I2S2ext_BASE (APB1PERIPH_BASE + 0x3400U)
+#define SPI2_BASE (APB1PERIPH_BASE + 0x3800U)
+#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00U)
+#define I2S3ext_BASE (APB1PERIPH_BASE + 0x4000U)
+#define USART2_BASE (APB1PERIPH_BASE + 0x4400U)
+#define USART3_BASE (APB1PERIPH_BASE + 0x4800U)
+#define UART4_BASE (APB1PERIPH_BASE + 0x4C00U)
+#define UART5_BASE (APB1PERIPH_BASE + 0x5000U)
+#define I2C1_BASE (APB1PERIPH_BASE + 0x5400U)
+#define I2C2_BASE (APB1PERIPH_BASE + 0x5800U)
+#define I2C3_BASE (APB1PERIPH_BASE + 0x5C00U)
+#define CAN1_BASE (APB1PERIPH_BASE + 0x6400U)
+#define CAN2_BASE (APB1PERIPH_BASE + 0x6800U)
+#define PWR_BASE (APB1PERIPH_BASE + 0x7000U)
+#define DAC_BASE (APB1PERIPH_BASE + 0x7400U)
+
+/*!< APB2 peripherals */
+#define TIM1_BASE (APB2PERIPH_BASE + 0x0000U)
+#define TIM8_BASE (APB2PERIPH_BASE + 0x0400U)
+#define USART1_BASE (APB2PERIPH_BASE + 0x1000U)
+#define USART6_BASE (APB2PERIPH_BASE + 0x1400U)
+#define ADC1_BASE (APB2PERIPH_BASE + 0x2000U)
+#define ADC2_BASE (APB2PERIPH_BASE + 0x2100U)
+#define ADC3_BASE (APB2PERIPH_BASE + 0x2200U)
+#define ADC_BASE (APB2PERIPH_BASE + 0x2300U)
+#define SDIO_BASE (APB2PERIPH_BASE + 0x2C00U)
+#define SPI1_BASE (APB2PERIPH_BASE + 0x3000U)
+#define SYSCFG_BASE (APB2PERIPH_BASE + 0x3800U)
+#define EXTI_BASE (APB2PERIPH_BASE + 0x3C00U)
+#define TIM9_BASE (APB2PERIPH_BASE + 0x4000U)
+#define TIM10_BASE (APB2PERIPH_BASE + 0x4400U)
+#define TIM11_BASE (APB2PERIPH_BASE + 0x4800U)
+
+/*!< AHB1 peripherals */
+#define GPIOA_BASE (AHB1PERIPH_BASE + 0x0000U)
+#define GPIOB_BASE (AHB1PERIPH_BASE + 0x0400U)
+#define GPIOC_BASE (AHB1PERIPH_BASE + 0x0800U)
+#define GPIOD_BASE (AHB1PERIPH_BASE + 0x0C00U)
+#define GPIOE_BASE (AHB1PERIPH_BASE + 0x1000U)
+#define GPIOF_BASE (AHB1PERIPH_BASE + 0x1400U)
+#define GPIOG_BASE (AHB1PERIPH_BASE + 0x1800U)
+#define GPIOH_BASE (AHB1PERIPH_BASE + 0x1C00U)
+#define GPIOI_BASE (AHB1PERIPH_BASE + 0x2000U)
+#define CRC_BASE (AHB1PERIPH_BASE + 0x3000U)
+#define RCC_BASE (AHB1PERIPH_BASE + 0x3800U)
+#define FLASH_R_BASE (AHB1PERIPH_BASE + 0x3C00U)
+#define DMA1_BASE (AHB1PERIPH_BASE + 0x6000U)
+#define DMA1_Stream0_BASE (DMA1_BASE + 0x010U)
+#define DMA1_Stream1_BASE (DMA1_BASE + 0x028U)
+#define DMA1_Stream2_BASE (DMA1_BASE + 0x040U)
+#define DMA1_Stream3_BASE (DMA1_BASE + 0x058U)
+#define DMA1_Stream4_BASE (DMA1_BASE + 0x070U)
+#define DMA1_Stream5_BASE (DMA1_BASE + 0x088U)
+#define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0U)
+#define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8U)
+#define DMA2_BASE (AHB1PERIPH_BASE + 0x6400U)
+#define DMA2_Stream0_BASE (DMA2_BASE + 0x010U)
+#define DMA2_Stream1_BASE (DMA2_BASE + 0x028U)
+#define DMA2_Stream2_BASE (DMA2_BASE + 0x040U)
+#define DMA2_Stream3_BASE (DMA2_BASE + 0x058U)
+#define DMA2_Stream4_BASE (DMA2_BASE + 0x070U)
+#define DMA2_Stream5_BASE (DMA2_BASE + 0x088U)
+#define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0U)
+#define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8U)
+#define ETH_BASE (AHB1PERIPH_BASE + 0x8000U)
+#define ETH_MAC_BASE (ETH_BASE)
+#define ETH_MMC_BASE (ETH_BASE + 0x0100U)
+#define ETH_PTP_BASE (ETH_BASE + 0x0700U)
+#define ETH_DMA_BASE (ETH_BASE + 0x1000U)
+
+/*!< AHB2 peripherals */
+#define DCMI_BASE (AHB2PERIPH_BASE + 0x50000U)
+#define CRYP_BASE (AHB2PERIPH_BASE + 0x60000U)
+#define HASH_BASE (AHB2PERIPH_BASE + 0x60400U)
+#define HASH_DIGEST_BASE (AHB2PERIPH_BASE + 0x60710U)
+#define RNG_BASE (AHB2PERIPH_BASE + 0x60800U)
+
+/*!< FSMC Bankx registers base address */
+#define FSMC_Bank1_R_BASE (FSMC_R_BASE + 0x0000U)
+#define FSMC_Bank1E_R_BASE (FSMC_R_BASE + 0x0104U)
+#define FSMC_Bank2_3_R_BASE (FSMC_R_BASE + 0x0060U)
+#define FSMC_Bank4_R_BASE (FSMC_R_BASE + 0x00A0U)
+
+/* Debug MCU registers base address */
+#define DBGMCU_BASE 0xE0042000U
+
+/*!< USB registers base address */
+#define USB_OTG_HS_PERIPH_BASE 0x40040000U
+#define USB_OTG_FS_PERIPH_BASE 0x50000000U
+
+#define USB_OTG_GLOBAL_BASE 0x000U
+#define USB_OTG_DEVICE_BASE 0x800U
+#define USB_OTG_IN_ENDPOINT_BASE 0x900U
+#define USB_OTG_OUT_ENDPOINT_BASE 0xB00U
+#define USB_OTG_EP_REG_SIZE 0x20U
+#define USB_OTG_HOST_BASE 0x400U
+#define USB_OTG_HOST_PORT_BASE 0x440U
+#define USB_OTG_HOST_CHANNEL_BASE 0x500U
+#define USB_OTG_HOST_CHANNEL_SIZE 0x20U
+#define USB_OTG_PCGCCTL_BASE 0xE00U
+#define USB_OTG_FIFO_BASE 0x1000U
+#define USB_OTG_FIFO_SIZE 0x1000U
+
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_declaration
+ * @{
+ */
+#define TIM2 ((TIM_TypeDef *) TIM2_BASE)
+#define TIM3 ((TIM_TypeDef *) TIM3_BASE)
+#define TIM4 ((TIM_TypeDef *) TIM4_BASE)
+#define TIM5 ((TIM_TypeDef *) TIM5_BASE)
+#define TIM6 ((TIM_TypeDef *) TIM6_BASE)
+#define TIM7 ((TIM_TypeDef *) TIM7_BASE)
+#define TIM12 ((TIM_TypeDef *) TIM12_BASE)
+#define TIM13 ((TIM_TypeDef *) TIM13_BASE)
+#define TIM14 ((TIM_TypeDef *) TIM14_BASE)
+#define RTC ((RTC_TypeDef *) RTC_BASE)
+#define WWDG ((WWDG_TypeDef *) WWDG_BASE)
+#define IWDG ((IWDG_TypeDef *) IWDG_BASE)
+#define I2S2ext ((SPI_TypeDef *) I2S2ext_BASE)
+#define SPI2 ((SPI_TypeDef *) SPI2_BASE)
+#define SPI3 ((SPI_TypeDef *) SPI3_BASE)
+#define I2S3ext ((SPI_TypeDef *) I2S3ext_BASE)
+#define USART2 ((USART_TypeDef *) USART2_BASE)
+#define USART3 ((USART_TypeDef *) USART3_BASE)
+#define UART4 ((USART_TypeDef *) UART4_BASE)
+#define UART5 ((USART_TypeDef *) UART5_BASE)
+#define I2C1 ((I2C_TypeDef *) I2C1_BASE)
+#define I2C2 ((I2C_TypeDef *) I2C2_BASE)
+#define I2C3 ((I2C_TypeDef *) I2C3_BASE)
+#define CAN1 ((CAN_TypeDef *) CAN1_BASE)
+#define CAN2 ((CAN_TypeDef *) CAN2_BASE)
+#define PWR ((PWR_TypeDef *) PWR_BASE)
+#define DAC ((DAC_TypeDef *) DAC_BASE)
+#define TIM1 ((TIM_TypeDef *) TIM1_BASE)
+#define TIM8 ((TIM_TypeDef *) TIM8_BASE)
+#define USART1 ((USART_TypeDef *) USART1_BASE)
+#define USART6 ((USART_TypeDef *) USART6_BASE)
+#define ADC ((ADC_Common_TypeDef *) ADC_BASE)
+#define ADC1 ((ADC_TypeDef *) ADC1_BASE)
+#define ADC2 ((ADC_TypeDef *) ADC2_BASE)
+#define ADC3 ((ADC_TypeDef *) ADC3_BASE)
+#define SDIO ((SDIO_TypeDef *) SDIO_BASE)
+#define SPI1 ((SPI_TypeDef *) SPI1_BASE)
+#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
+#define EXTI ((EXTI_TypeDef *) EXTI_BASE)
+#define TIM9 ((TIM_TypeDef *) TIM9_BASE)
+#define TIM10 ((TIM_TypeDef *) TIM10_BASE)
+#define TIM11 ((TIM_TypeDef *) TIM11_BASE)
+#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
+#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
+#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
+#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
+#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
+#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
+#define GPIOG ((GPIO_TypeDef *) GPIOG_BASE)
+#define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
+#define GPIOI ((GPIO_TypeDef *) GPIOI_BASE)
+#define CRC ((CRC_TypeDef *) CRC_BASE)
+#define RCC ((RCC_TypeDef *) RCC_BASE)
+#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
+#define DMA1 ((DMA_TypeDef *) DMA1_BASE)
+#define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)
+#define DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)
+#define DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)
+#define DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)
+#define DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)
+#define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)
+#define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)
+#define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)
+#define DMA2 ((DMA_TypeDef *) DMA2_BASE)
+#define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)
+#define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
+#define DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)
+#define DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)
+#define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)
+#define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)
+#define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)
+#define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)
+#define ETH ((ETH_TypeDef *) ETH_BASE)
+#define DCMI ((DCMI_TypeDef *) DCMI_BASE)
+#define CRYP ((CRYP_TypeDef *) CRYP_BASE)
+#define HASH ((HASH_TypeDef *) HASH_BASE)
+#define HASH_DIGEST ((HASH_DIGEST_TypeDef *) HASH_DIGEST_BASE)
+#define RNG ((RNG_TypeDef *) RNG_BASE)
+#define FSMC_Bank1 ((FSMC_Bank1_TypeDef *) FSMC_Bank1_R_BASE)
+#define FSMC_Bank1E ((FSMC_Bank1E_TypeDef *) FSMC_Bank1E_R_BASE)
+#define FSMC_Bank2_3 ((FSMC_Bank2_3_TypeDef *) FSMC_Bank2_3_R_BASE)
+#define FSMC_Bank4 ((FSMC_Bank4_TypeDef *) FSMC_Bank4_R_BASE)
+
+#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
+
+#define USB_OTG_FS ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE)
+#define USB_OTG_HS ((USB_OTG_GlobalTypeDef *) USB_OTG_HS_PERIPH_BASE)
+
+/**
+ * @}
+ */
+
+/** @addtogroup Exported_constants
+ * @{
+ */
+
+ /** @addtogroup Peripheral_Registers_Bits_Definition
+ * @{
+ */
+
+/******************************************************************************/
+/* Peripheral Registers_Bits_Definition */
+/******************************************************************************/
+
+/******************************************************************************/
+/* */
+/* Analog to Digital Converter */
+/* */
+/******************************************************************************/
+/******************** Bit definition for ADC_SR register ********************/
+#define ADC_SR_AWD 0x00000001U /*!<Analog watchdog flag */
+#define ADC_SR_EOC 0x00000002U /*!<End of conversion */
+#define ADC_SR_JEOC 0x00000004U /*!<Injected channel end of conversion */
+#define ADC_SR_JSTRT 0x00000008U /*!<Injected channel Start flag */
+#define ADC_SR_STRT 0x00000010U /*!<Regular channel Start flag */
+#define ADC_SR_OVR 0x00000020U /*!<Overrun flag */
+
+/******************* Bit definition for ADC_CR1 register ********************/
+#define ADC_CR1_AWDCH 0x0000001FU /*!<AWDCH[4:0] bits (Analog watchdog channel select bits) */
+#define ADC_CR1_AWDCH_0 0x00000001U /*!<Bit 0 */
+#define ADC_CR1_AWDCH_1 0x00000002U /*!<Bit 1 */
+#define ADC_CR1_AWDCH_2 0x00000004U /*!<Bit 2 */
+#define ADC_CR1_AWDCH_3 0x00000008U /*!<Bit 3 */
+#define ADC_CR1_AWDCH_4 0x00000010U /*!<Bit 4 */
+#define ADC_CR1_EOCIE 0x00000020U /*!<Interrupt enable for EOC */
+#define ADC_CR1_AWDIE 0x00000040U /*!<AAnalog Watchdog interrupt enable */
+#define ADC_CR1_JEOCIE 0x00000080U /*!<Interrupt enable for injected channels */
+#define ADC_CR1_SCAN 0x00000100U /*!<Scan mode */
+#define ADC_CR1_AWDSGL 0x00000200U /*!<Enable the watchdog on a single channel in scan mode */
+#define ADC_CR1_JAUTO 0x00000400U /*!<Automatic injected group conversion */
+#define ADC_CR1_DISCEN 0x00000800U /*!<Discontinuous mode on regular channels */
+#define ADC_CR1_JDISCEN 0x00001000U /*!<Discontinuous mode on injected channels */
+#define ADC_CR1_DISCNUM 0x0000E000U /*!<DISCNUM[2:0] bits (Discontinuous mode channel count) */
+#define ADC_CR1_DISCNUM_0 0x00002000U /*!<Bit 0 */
+#define ADC_CR1_DISCNUM_1 0x00004000U /*!<Bit 1 */
+#define ADC_CR1_DISCNUM_2 0x00008000U /*!<Bit 2 */
+#define ADC_CR1_JAWDEN 0x00400000U /*!<Analog watchdog enable on injected channels */
+#define ADC_CR1_AWDEN 0x00800000U /*!<Analog watchdog enable on regular channels */
+#define ADC_CR1_RES 0x03000000U /*!<RES[2:0] bits (Resolution) */
+#define ADC_CR1_RES_0 0x01000000U /*!<Bit 0 */
+#define ADC_CR1_RES_1 0x02000000U /*!<Bit 1 */
+#define ADC_CR1_OVRIE 0x04000000U /*!<overrun interrupt enable */
+
+/******************* Bit definition for ADC_CR2 register ********************/
+#define ADC_CR2_ADON 0x00000001U /*!<A/D Converter ON / OFF */
+#define ADC_CR2_CONT 0x00000002U /*!<Continuous Conversion */
+#define ADC_CR2_DMA 0x00000100U /*!<Direct Memory access mode */
+#define ADC_CR2_DDS 0x00000200U /*!<DMA disable selection (Single ADC) */
+#define ADC_CR2_EOCS 0x00000400U /*!<End of conversion selection */
+#define ADC_CR2_ALIGN 0x00000800U /*!<Data Alignment */
+#define ADC_CR2_JEXTSEL 0x000F0000U /*!<JEXTSEL[3:0] bits (External event select for injected group) */
+#define ADC_CR2_JEXTSEL_0 0x00010000U /*!<Bit 0 */
+#define ADC_CR2_JEXTSEL_1 0x00020000U /*!<Bit 1 */
+#define ADC_CR2_JEXTSEL_2 0x00040000U /*!<Bit 2 */
+#define ADC_CR2_JEXTSEL_3 0x00080000U /*!<Bit 3 */
+#define ADC_CR2_JEXTEN 0x00300000U /*!<JEXTEN[1:0] bits (External Trigger Conversion mode for injected channelsp) */
+#define ADC_CR2_JEXTEN_0 0x00100000U /*!<Bit 0 */
+#define ADC_CR2_JEXTEN_1 0x00200000U /*!<Bit 1 */
+#define ADC_CR2_JSWSTART 0x00400000U /*!<Start Conversion of injected channels */
+#define ADC_CR2_EXTSEL 0x0F000000U /*!<EXTSEL[3:0] bits (External Event Select for regular group) */
+#define ADC_CR2_EXTSEL_0 0x01000000U /*!<Bit 0 */
+#define ADC_CR2_EXTSEL_1 0x02000000U /*!<Bit 1 */
+#define ADC_CR2_EXTSEL_2 0x04000000U /*!<Bit 2 */
+#define ADC_CR2_EXTSEL_3 0x08000000U /*!<Bit 3 */
+#define ADC_CR2_EXTEN 0x30000000U /*!<EXTEN[1:0] bits (External Trigger Conversion mode for regular channelsp) */
+#define ADC_CR2_EXTEN_0 0x10000000U /*!<Bit 0 */
+#define ADC_CR2_EXTEN_1 0x20000000U /*!<Bit 1 */
+#define ADC_CR2_SWSTART 0x40000000U /*!<Start Conversion of regular channels */
+
+/****************** Bit definition for ADC_SMPR1 register *******************/
+#define ADC_SMPR1_SMP10 0x00000007U /*!<SMP10[2:0] bits (Channel 10 Sample time selection) */
+#define ADC_SMPR1_SMP10_0 0x00000001U /*!<Bit 0 */
+#define ADC_SMPR1_SMP10_1 0x00000002U /*!<Bit 1 */
+#define ADC_SMPR1_SMP10_2 0x00000004U /*!<Bit 2 */
+#define ADC_SMPR1_SMP11 0x00000038U /*!<SMP11[2:0] bits (Channel 11 Sample time selection) */
+#define ADC_SMPR1_SMP11_0 0x00000008U /*!<Bit 0 */
+#define ADC_SMPR1_SMP11_1 0x00000010U /*!<Bit 1 */
+#define ADC_SMPR1_SMP11_2 0x00000020U /*!<Bit 2 */
+#define ADC_SMPR1_SMP12 0x000001C0U /*!<SMP12[2:0] bits (Channel 12 Sample time selection) */
+#define ADC_SMPR1_SMP12_0 0x00000040U /*!<Bit 0 */
+#define ADC_SMPR1_SMP12_1 0x00000080U /*!<Bit 1 */
+#define ADC_SMPR1_SMP12_2 0x00000100U /*!<Bit 2 */
+#define ADC_SMPR1_SMP13 0x00000E00U /*!<SMP13[2:0] bits (Channel 13 Sample time selection) */
+#define ADC_SMPR1_SMP13_0 0x00000200U /*!<Bit 0 */
+#define ADC_SMPR1_SMP13_1 0x00000400U /*!<Bit 1 */
+#define ADC_SMPR1_SMP13_2 0x00000800U /*!<Bit 2 */
+#define ADC_SMPR1_SMP14 0x00007000U /*!<SMP14[2:0] bits (Channel 14 Sample time selection) */
+#define ADC_SMPR1_SMP14_0 0x00001000U /*!<Bit 0 */
+#define ADC_SMPR1_SMP14_1 0x00002000U /*!<Bit 1 */
+#define ADC_SMPR1_SMP14_2 0x00004000U /*!<Bit 2 */
+#define ADC_SMPR1_SMP15 0x00038000U /*!<SMP15[2:0] bits (Channel 15 Sample time selection) */
+#define ADC_SMPR1_SMP15_0 0x00008000U /*!<Bit 0 */
+#define ADC_SMPR1_SMP15_1 0x00010000U /*!<Bit 1 */
+#define ADC_SMPR1_SMP15_2 0x00020000U /*!<Bit 2 */
+#define ADC_SMPR1_SMP16 0x001C0000U /*!<SMP16[2:0] bits (Channel 16 Sample time selection) */
+#define ADC_SMPR1_SMP16_0 0x00040000U /*!<Bit 0 */
+#define ADC_SMPR1_SMP16_1 0x00080000U /*!<Bit 1 */
+#define ADC_SMPR1_SMP16_2 0x00100000U /*!<Bit 2 */
+#define ADC_SMPR1_SMP17 0x00E00000U /*!<SMP17[2:0] bits (Channel 17 Sample time selection) */
+#define ADC_SMPR1_SMP17_0 0x00200000U /*!<Bit 0 */
+#define ADC_SMPR1_SMP17_1 0x00400000U /*!<Bit 1 */
+#define ADC_SMPR1_SMP17_2 0x00800000U /*!<Bit 2 */
+#define ADC_SMPR1_SMP18 0x07000000U /*!<SMP18[2:0] bits (Channel 18 Sample time selection) */
+#define ADC_SMPR1_SMP18_0 0x01000000U /*!<Bit 0 */
+#define ADC_SMPR1_SMP18_1 0x02000000U /*!<Bit 1 */
+#define ADC_SMPR1_SMP18_2 0x04000000U /*!<Bit 2 */
+
+/****************** Bit definition for ADC_SMPR2 register *******************/
+#define ADC_SMPR2_SMP0 0x00000007U /*!<SMP0[2:0] bits (Channel 0 Sample time selection) */
+#define ADC_SMPR2_SMP0_0 0x00000001U /*!<Bit 0 */
+#define ADC_SMPR2_SMP0_1 0x00000002U /*!<Bit 1 */
+#define ADC_SMPR2_SMP0_2 0x00000004U /*!<Bit 2 */
+#define ADC_SMPR2_SMP1 0x00000038U /*!<SMP1[2:0] bits (Channel 1 Sample time selection) */
+#define ADC_SMPR2_SMP1_0 0x00000008U /*!<Bit 0 */
+#define ADC_SMPR2_SMP1_1 0x00000010U /*!<Bit 1 */
+#define ADC_SMPR2_SMP1_2 0x00000020U /*!<Bit 2 */
+#define ADC_SMPR2_SMP2 0x000001C0U /*!<SMP2[2:0] bits (Channel 2 Sample time selection) */
+#define ADC_SMPR2_SMP2_0 0x00000040U /*!<Bit 0 */
+#define ADC_SMPR2_SMP2_1 0x00000080U /*!<Bit 1 */
+#define ADC_SMPR2_SMP2_2 0x00000100U /*!<Bit 2 */
+#define ADC_SMPR2_SMP3 0x00000E00U /*!<SMP3[2:0] bits (Channel 3 Sample time selection) */
+#define ADC_SMPR2_SMP3_0 0x00000200U /*!<Bit 0 */
+#define ADC_SMPR2_SMP3_1 0x00000400U /*!<Bit 1 */
+#define ADC_SMPR2_SMP3_2 0x00000800U /*!<Bit 2 */
+#define ADC_SMPR2_SMP4 0x00007000U /*!<SMP4[2:0] bits (Channel 4 Sample time selection) */
+#define ADC_SMPR2_SMP4_0 0x00001000U /*!<Bit 0 */
+#define ADC_SMPR2_SMP4_1 0x00002000U /*!<Bit 1 */
+#define ADC_SMPR2_SMP4_2 0x00004000U /*!<Bit 2 */
+#define ADC_SMPR2_SMP5 0x00038000U /*!<SMP5[2:0] bits (Channel 5 Sample time selection) */
+#define ADC_SMPR2_SMP5_0 0x00008000U /*!<Bit 0 */
+#define ADC_SMPR2_SMP5_1 0x00010000U /*!<Bit 1 */
+#define ADC_SMPR2_SMP5_2 0x00020000U /*!<Bit 2 */
+#define ADC_SMPR2_SMP6 0x001C0000U /*!<SMP6[2:0] bits (Channel 6 Sample time selection) */
+#define ADC_SMPR2_SMP6_0 0x00040000U /*!<Bit 0 */
+#define ADC_SMPR2_SMP6_1 0x00080000U /*!<Bit 1 */
+#define ADC_SMPR2_SMP6_2 0x00100000U /*!<Bit 2 */
+#define ADC_SMPR2_SMP7 0x00E00000U /*!<SMP7[2:0] bits (Channel 7 Sample time selection) */
+#define ADC_SMPR2_SMP7_0 0x00200000U /*!<Bit 0 */
+#define ADC_SMPR2_SMP7_1 0x00400000U /*!<Bit 1 */
+#define ADC_SMPR2_SMP7_2 0x00800000U /*!<Bit 2 */
+#define ADC_SMPR2_SMP8 0x07000000U /*!<SMP8[2:0] bits (Channel 8 Sample time selection) */
+#define ADC_SMPR2_SMP8_0 0x01000000U /*!<Bit 0 */
+#define ADC_SMPR2_SMP8_1 0x02000000U /*!<Bit 1 */
+#define ADC_SMPR2_SMP8_2 0x04000000U /*!<Bit 2 */
+#define ADC_SMPR2_SMP9 0x38000000U /*!<SMP9[2:0] bits (Channel 9 Sample time selection) */
+#define ADC_SMPR2_SMP9_0 0x08000000U /*!<Bit 0 */
+#define ADC_SMPR2_SMP9_1 0x10000000U /*!<Bit 1 */
+#define ADC_SMPR2_SMP9_2 0x20000000U /*!<Bit 2 */
+
+/****************** Bit definition for ADC_JOFR1 register *******************/
+#define ADC_JOFR1_JOFFSET1 0x0FFFU /*!<Data offset for injected channel 1 */
+
+/****************** Bit definition for ADC_JOFR2 register *******************/
+#define ADC_JOFR2_JOFFSET2 0x0FFFU /*!<Data offset for injected channel 2 */
+
+/****************** Bit definition for ADC_JOFR3 register *******************/
+#define ADC_JOFR3_JOFFSET3 0x0FFFU /*!<Data offset for injected channel 3 */
+
+/****************** Bit definition for ADC_JOFR4 register *******************/
+#define ADC_JOFR4_JOFFSET4 0x0FFFU /*!<Data offset for injected channel 4 */
+
+/******************* Bit definition for ADC_HTR register ********************/
+#define ADC_HTR_HT 0x0FFFU /*!<Analog watchdog high threshold */
+
+/******************* Bit definition for ADC_LTR register ********************/
+#define ADC_LTR_LT 0x0FFFU /*!<Analog watchdog low threshold */
+
+/******************* Bit definition for ADC_SQR1 register *******************/
+#define ADC_SQR1_SQ13 0x0000001FU /*!<SQ13[4:0] bits (13th conversion in regular sequence) */
+#define ADC_SQR1_SQ13_0 0x00000001U /*!<Bit 0 */
+#define ADC_SQR1_SQ13_1 0x00000002U /*!<Bit 1 */
+#define ADC_SQR1_SQ13_2 0x00000004U /*!<Bit 2 */
+#define ADC_SQR1_SQ13_3 0x00000008U /*!<Bit 3 */
+#define ADC_SQR1_SQ13_4 0x00000010U /*!<Bit 4 */
+#define ADC_SQR1_SQ14 0x000003E0U /*!<SQ14[4:0] bits (14th conversion in regular sequence) */
+#define ADC_SQR1_SQ14_0 0x00000020U /*!<Bit 0 */
+#define ADC_SQR1_SQ14_1 0x00000040U /*!<Bit 1 */
+#define ADC_SQR1_SQ14_2 0x00000080U /*!<Bit 2 */
+#define ADC_SQR1_SQ14_3 0x00000100U /*!<Bit 3 */
+#define ADC_SQR1_SQ14_4 0x00000200U /*!<Bit 4 */
+#define ADC_SQR1_SQ15 0x00007C00U /*!<SQ15[4:0] bits (15th conversion in regular sequence) */
+#define ADC_SQR1_SQ15_0 0x00000400U /*!<Bit 0 */
+#define ADC_SQR1_SQ15_1 0x00000800U /*!<Bit 1 */
+#define ADC_SQR1_SQ15_2 0x00001000U /*!<Bit 2 */
+#define ADC_SQR1_SQ15_3 0x00002000U /*!<Bit 3 */
+#define ADC_SQR1_SQ15_4 0x00004000U /*!<Bit 4 */
+#define ADC_SQR1_SQ16 0x000F8000U /*!<SQ16[4:0] bits (16th conversion in regular sequence) */
+#define ADC_SQR1_SQ16_0 0x00008000U /*!<Bit 0 */
+#define ADC_SQR1_SQ16_1 0x00010000U /*!<Bit 1 */
+#define ADC_SQR1_SQ16_2 0x00020000U /*!<Bit 2 */
+#define ADC_SQR1_SQ16_3 0x00040000U /*!<Bit 3 */
+#define ADC_SQR1_SQ16_4 0x00080000U /*!<Bit 4 */
+#define ADC_SQR1_L 0x00F00000U /*!<L[3:0] bits (Regular channel sequence length) */
+#define ADC_SQR1_L_0 0x00100000U /*!<Bit 0 */
+#define ADC_SQR1_L_1 0x00200000U /*!<Bit 1 */
+#define ADC_SQR1_L_2 0x00400000U /*!<Bit 2 */
+#define ADC_SQR1_L_3 0x00800000U /*!<Bit 3 */
+
+/******************* Bit definition for ADC_SQR2 register *******************/
+#define ADC_SQR2_SQ7 0x0000001FU /*!<SQ7[4:0] bits (7th conversion in regular sequence) */
+#define ADC_SQR2_SQ7_0 0x00000001U /*!<Bit 0 */
+#define ADC_SQR2_SQ7_1 0x00000002U /*!<Bit 1 */
+#define ADC_SQR2_SQ7_2 0x00000004U /*!<Bit 2 */
+#define ADC_SQR2_SQ7_3 0x00000008U /*!<Bit 3 */
+#define ADC_SQR2_SQ7_4 0x00000010U /*!<Bit 4 */
+#define ADC_SQR2_SQ8 0x000003E0U /*!<SQ8[4:0] bits (8th conversion in regular sequence) */
+#define ADC_SQR2_SQ8_0 0x00000020U /*!<Bit 0 */
+#define ADC_SQR2_SQ8_1 0x00000040U /*!<Bit 1 */
+#define ADC_SQR2_SQ8_2 0x00000080U /*!<Bit 2 */
+#define ADC_SQR2_SQ8_3 0x00000100U /*!<Bit 3 */
+#define ADC_SQR2_SQ8_4 0x00000200U /*!<Bit 4 */
+#define ADC_SQR2_SQ9 0x00007C00U /*!<SQ9[4:0] bits (9th conversion in regular sequence) */
+#define ADC_SQR2_SQ9_0 0x00000400U /*!<Bit 0 */
+#define ADC_SQR2_SQ9_1 0x00000800U /*!<Bit 1 */
+#define ADC_SQR2_SQ9_2 0x00001000U /*!<Bit 2 */
+#define ADC_SQR2_SQ9_3 0x00002000U /*!<Bit 3 */
+#define ADC_SQR2_SQ9_4 0x00004000U /*!<Bit 4 */
+#define ADC_SQR2_SQ10 0x000F8000U /*!<SQ10[4:0] bits (10th conversion in regular sequence) */
+#define ADC_SQR2_SQ10_0 0x00008000U /*!<Bit 0 */
+#define ADC_SQR2_SQ10_1 0x00010000U /*!<Bit 1 */
+#define ADC_SQR2_SQ10_2 0x00020000U /*!<Bit 2 */
+#define ADC_SQR2_SQ10_3 0x00040000U /*!<Bit 3 */
+#define ADC_SQR2_SQ10_4 0x00080000U /*!<Bit 4 */
+#define ADC_SQR2_SQ11 0x01F00000U /*!<SQ11[4:0] bits (11th conversion in regular sequence) */
+#define ADC_SQR2_SQ11_0 0x00100000U /*!<Bit 0 */
+#define ADC_SQR2_SQ11_1 0x00200000U /*!<Bit 1 */
+#define ADC_SQR2_SQ11_2 0x00400000U /*!<Bit 2 */
+#define ADC_SQR2_SQ11_3 0x00800000U /*!<Bit 3 */
+#define ADC_SQR2_SQ11_4 0x01000000U /*!<Bit 4 */
+#define ADC_SQR2_SQ12 0x3E000000U /*!<SQ12[4:0] bits (12th conversion in regular sequence) */
+#define ADC_SQR2_SQ12_0 0x02000000U /*!<Bit 0 */
+#define ADC_SQR2_SQ12_1 0x04000000U /*!<Bit 1 */
+#define ADC_SQR2_SQ12_2 0x08000000U /*!<Bit 2 */
+#define ADC_SQR2_SQ12_3 0x10000000U /*!<Bit 3 */
+#define ADC_SQR2_SQ12_4 0x20000000U /*!<Bit 4 */
+
+/******************* Bit definition for ADC_SQR3 register *******************/
+#define ADC_SQR3_SQ1 0x0000001FU /*!<SQ1[4:0] bits (1st conversion in regular sequence) */
+#define ADC_SQR3_SQ1_0 0x00000001U /*!<Bit 0 */
+#define ADC_SQR3_SQ1_1 0x00000002U /*!<Bit 1 */
+#define ADC_SQR3_SQ1_2 0x00000004U /*!<Bit 2 */
+#define ADC_SQR3_SQ1_3 0x00000008U /*!<Bit 3 */
+#define ADC_SQR3_SQ1_4 0x00000010U /*!<Bit 4 */
+#define ADC_SQR3_SQ2 0x000003E0U /*!<SQ2[4:0] bits (2nd conversion in regular sequence) */
+#define ADC_SQR3_SQ2_0 0x00000020U /*!<Bit 0 */
+#define ADC_SQR3_SQ2_1 0x00000040U /*!<Bit 1 */
+#define ADC_SQR3_SQ2_2 0x00000080U /*!<Bit 2 */
+#define ADC_SQR3_SQ2_3 0x00000100U /*!<Bit 3 */
+#define ADC_SQR3_SQ2_4 0x00000200U /*!<Bit 4 */
+#define ADC_SQR3_SQ3 0x00007C00U /*!<SQ3[4:0] bits (3rd conversion in regular sequence) */
+#define ADC_SQR3_SQ3_0 0x00000400U /*!<Bit 0 */
+#define ADC_SQR3_SQ3_1 0x00000800U /*!<Bit 1 */
+#define ADC_SQR3_SQ3_2 0x00001000U /*!<Bit 2 */
+#define ADC_SQR3_SQ3_3 0x00002000U /*!<Bit 3 */
+#define ADC_SQR3_SQ3_4 0x00004000U /*!<Bit 4 */
+#define ADC_SQR3_SQ4 0x000F8000U /*!<SQ4[4:0] bits (4th conversion in regular sequence) */
+#define ADC_SQR3_SQ4_0 0x00008000U /*!<Bit 0 */
+#define ADC_SQR3_SQ4_1 0x00010000U /*!<Bit 1 */
+#define ADC_SQR3_SQ4_2 0x00020000U /*!<Bit 2 */
+#define ADC_SQR3_SQ4_3 0x00040000U /*!<Bit 3 */
+#define ADC_SQR3_SQ4_4 0x00080000U /*!<Bit 4 */
+#define ADC_SQR3_SQ5 0x01F00000U /*!<SQ5[4:0] bits (5th conversion in regular sequence) */
+#define ADC_SQR3_SQ5_0 0x00100000U /*!<Bit 0 */
+#define ADC_SQR3_SQ5_1 0x00200000U /*!<Bit 1 */
+#define ADC_SQR3_SQ5_2 0x00400000U /*!<Bit 2 */
+#define ADC_SQR3_SQ5_3 0x00800000U /*!<Bit 3 */
+#define ADC_SQR3_SQ5_4 0x01000000U /*!<Bit 4 */
+#define ADC_SQR3_SQ6 0x3E000000U /*!<SQ6[4:0] bits (6th conversion in regular sequence) */
+#define ADC_SQR3_SQ6_0 0x02000000U /*!<Bit 0 */
+#define ADC_SQR3_SQ6_1 0x04000000U /*!<Bit 1 */
+#define ADC_SQR3_SQ6_2 0x08000000U /*!<Bit 2 */
+#define ADC_SQR3_SQ6_3 0x10000000U /*!<Bit 3 */
+#define ADC_SQR3_SQ6_4 0x20000000U /*!<Bit 4 */
+
+/******************* Bit definition for ADC_JSQR register *******************/
+#define ADC_JSQR_JSQ1 0x0000001FU /*!<JSQ1[4:0] bits (1st conversion in injected sequence) */
+#define ADC_JSQR_JSQ1_0 0x00000001U /*!<Bit 0 */
+#define ADC_JSQR_JSQ1_1 0x00000002U /*!<Bit 1 */
+#define ADC_JSQR_JSQ1_2 0x00000004U /*!<Bit 2 */
+#define ADC_JSQR_JSQ1_3 0x00000008U /*!<Bit 3 */
+#define ADC_JSQR_JSQ1_4 0x00000010U /*!<Bit 4 */
+#define ADC_JSQR_JSQ2 0x000003E0U /*!<JSQ2[4:0] bits (2nd conversion in injected sequence) */
+#define ADC_JSQR_JSQ2_0 0x00000020U /*!<Bit 0 */
+#define ADC_JSQR_JSQ2_1 0x00000040U /*!<Bit 1 */
+#define ADC_JSQR_JSQ2_2 0x00000080U /*!<Bit 2 */
+#define ADC_JSQR_JSQ2_3 0x00000100U /*!<Bit 3 */
+#define ADC_JSQR_JSQ2_4 0x00000200U /*!<Bit 4 */
+#define ADC_JSQR_JSQ3 0x00007C00U /*!<JSQ3[4:0] bits (3rd conversion in injected sequence) */
+#define ADC_JSQR_JSQ3_0 0x00000400U /*!<Bit 0 */
+#define ADC_JSQR_JSQ3_1 0x00000800U /*!<Bit 1 */
+#define ADC_JSQR_JSQ3_2 0x00001000U /*!<Bit 2 */
+#define ADC_JSQR_JSQ3_3 0x00002000U /*!<Bit 3 */
+#define ADC_JSQR_JSQ3_4 0x00004000U /*!<Bit 4 */
+#define ADC_JSQR_JSQ4 0x000F8000U /*!<JSQ4[4:0] bits (4th conversion in injected sequence) */
+#define ADC_JSQR_JSQ4_0 0x00008000U /*!<Bit 0 */
+#define ADC_JSQR_JSQ4_1 0x00010000U /*!<Bit 1 */
+#define ADC_JSQR_JSQ4_2 0x00020000U /*!<Bit 2 */
+#define ADC_JSQR_JSQ4_3 0x00040000U /*!<Bit 3 */
+#define ADC_JSQR_JSQ4_4 0x00080000U /*!<Bit 4 */
+#define ADC_JSQR_JL 0x00300000U /*!<JL[1:0] bits (Injected Sequence length) */
+#define ADC_JSQR_JL_0 0x00100000U /*!<Bit 0 */
+#define ADC_JSQR_JL_1 0x00200000U /*!<Bit 1 */
+
+/******************* Bit definition for ADC_JDR1 register *******************/
+#define ADC_JDR1_JDATA 0xFFFFU /*!<Injected data */
+
+/******************* Bit definition for ADC_JDR2 register *******************/
+#define ADC_JDR2_JDATA 0xFFFFU /*!<Injected data */
+
+/******************* Bit definition for ADC_JDR3 register *******************/
+#define ADC_JDR3_JDATA 0xFFFFU /*!<Injected data */
+
+/******************* Bit definition for ADC_JDR4 register *******************/
+#define ADC_JDR4_JDATA 0xFFFFU /*!<Injected data */
+
+/******************** Bit definition for ADC_DR register ********************/
+#define ADC_DR_DATA 0x0000FFFFU /*!<Regular data */
+#define ADC_DR_ADC2DATA 0xFFFF0000U /*!<ADC2 data */
+
+/******************* Bit definition for ADC_CSR register ********************/
+#define ADC_CSR_AWD1 0x00000001U /*!<ADC1 Analog watchdog flag */
+#define ADC_CSR_EOC1 0x00000002U /*!<ADC1 End of conversion */
+#define ADC_CSR_JEOC1 0x00000004U /*!<ADC1 Injected channel end of conversion */
+#define ADC_CSR_JSTRT1 0x00000008U /*!<ADC1 Injected channel Start flag */
+#define ADC_CSR_STRT1 0x00000010U /*!<ADC1 Regular channel Start flag */
+#define ADC_CSR_OVR1 0x00000020U /*!<ADC1 DMA overrun flag */
+#define ADC_CSR_AWD2 0x00000100U /*!<ADC2 Analog watchdog flag */
+#define ADC_CSR_EOC2 0x00000200U /*!<ADC2 End of conversion */
+#define ADC_CSR_JEOC2 0x00000400U /*!<ADC2 Injected channel end of conversion */
+#define ADC_CSR_JSTRT2 0x00000800U /*!<ADC2 Injected channel Start flag */
+#define ADC_CSR_STRT2 0x00001000U /*!<ADC2 Regular channel Start flag */
+#define ADC_CSR_OVR2 0x00002000U /*!<ADC2 DMA overrun flag */
+#define ADC_CSR_AWD3 0x00010000U /*!<ADC3 Analog watchdog flag */
+#define ADC_CSR_EOC3 0x00020000U /*!<ADC3 End of conversion */
+#define ADC_CSR_JEOC3 0x00040000U /*!<ADC3 Injected channel end of conversion */
+#define ADC_CSR_JSTRT3 0x00080000U /*!<ADC3 Injected channel Start flag */
+#define ADC_CSR_STRT3 0x00100000U /*!<ADC3 Regular channel Start flag */
+#define ADC_CSR_OVR3 0x00200000U /*!<ADC3 DMA overrun flag */
+
+/* Legacy defines */
+#define ADC_CSR_DOVR1 ADC_CSR_OVR1
+#define ADC_CSR_DOVR2 ADC_CSR_OVR2
+#define ADC_CSR_DOVR3 ADC_CSR_OVR3
+
+/******************* Bit definition for ADC_CCR register ********************/
+#define ADC_CCR_MULTI 0x0000001FU /*!<MULTI[4:0] bits (Multi-ADC mode selection) */
+#define ADC_CCR_MULTI_0 0x00000001U /*!<Bit 0 */
+#define ADC_CCR_MULTI_1 0x00000002U /*!<Bit 1 */
+#define ADC_CCR_MULTI_2 0x00000004U /*!<Bit 2 */
+#define ADC_CCR_MULTI_3 0x00000008U /*!<Bit 3 */
+#define ADC_CCR_MULTI_4 0x00000010U /*!<Bit 4 */
+#define ADC_CCR_DELAY 0x00000F00U /*!<DELAY[3:0] bits (Delay between 2 sampling phases) */
+#define ADC_CCR_DELAY_0 0x00000100U /*!<Bit 0 */
+#define ADC_CCR_DELAY_1 0x00000200U /*!<Bit 1 */
+#define ADC_CCR_DELAY_2 0x00000400U /*!<Bit 2 */
+#define ADC_CCR_DELAY_3 0x00000800U /*!<Bit 3 */
+#define ADC_CCR_DDS 0x00002000U /*!<DMA disable selection (Multi-ADC mode) */
+#define ADC_CCR_DMA 0x0000C000U /*!<DMA[1:0] bits (Direct Memory Access mode for multimode) */
+#define ADC_CCR_DMA_0 0x00004000U /*!<Bit 0 */
+#define ADC_CCR_DMA_1 0x00008000U /*!<Bit 1 */
+#define ADC_CCR_ADCPRE 0x00030000U /*!<ADCPRE[1:0] bits (ADC prescaler) */
+#define ADC_CCR_ADCPRE_0 0x00010000U /*!<Bit 0 */
+#define ADC_CCR_ADCPRE_1 0x00020000U /*!<Bit 1 */
+#define ADC_CCR_VBATE 0x00400000U /*!<VBAT Enable */
+#define ADC_CCR_TSVREFE 0x00800000U /*!<Temperature Sensor and VREFINT Enable */
+
+/******************* Bit definition for ADC_CDR register ********************/
+#define ADC_CDR_DATA1 0x0000FFFFU /*!<1st data of a pair of regular conversions */
+#define ADC_CDR_DATA2 0xFFFF0000U /*!<2nd data of a pair of regular conversions */
+
+/******************************************************************************/
+/* */
+/* Controller Area Network */
+/* */
+/******************************************************************************/
+/*!<CAN control and status registers */
+/******************* Bit definition for CAN_MCR register ********************/
+#define CAN_MCR_INRQ 0x00000001U /*!<Initialization Request */
+#define CAN_MCR_SLEEP 0x00000002U /*!<Sleep Mode Request */
+#define CAN_MCR_TXFP 0x00000004U /*!<Transmit FIFO Priority */
+#define CAN_MCR_RFLM 0x00000008U /*!<Receive FIFO Locked Mode */
+#define CAN_MCR_NART 0x00000010U /*!<No Automatic Retransmission */
+#define CAN_MCR_AWUM 0x00000020U /*!<Automatic Wakeup Mode */
+#define CAN_MCR_ABOM 0x00000040U /*!<Automatic Bus-Off Management */
+#define CAN_MCR_TTCM 0x00000080U /*!<Time Triggered Communication Mode */
+#define CAN_MCR_RESET 0x00008000U /*!<bxCAN software master reset */
+#define CAN_MCR_DBF 0x00010000U /*!<bxCAN Debug freeze */
+/******************* Bit definition for CAN_MSR register ********************/
+#define CAN_MSR_INAK 0x0001U /*!<Initialization Acknowledge */
+#define CAN_MSR_SLAK 0x0002U /*!<Sleep Acknowledge */
+#define CAN_MSR_ERRI 0x0004U /*!<Error Interrupt */
+#define CAN_MSR_WKUI 0x0008U /*!<Wakeup Interrupt */
+#define CAN_MSR_SLAKI 0x0010U /*!<Sleep Acknowledge Interrupt */
+#define CAN_MSR_TXM 0x0100U /*!<Transmit Mode */
+#define CAN_MSR_RXM 0x0200U /*!<Receive Mode */
+#define CAN_MSR_SAMP 0x0400U /*!<Last Sample Point */
+#define CAN_MSR_RX 0x0800U /*!<CAN Rx Signal */
+
+/******************* Bit definition for CAN_TSR register ********************/
+#define CAN_TSR_RQCP0 0x00000001U /*!<Request Completed Mailbox0 */
+#define CAN_TSR_TXOK0 0x00000002U /*!<Transmission OK of Mailbox0 */
+#define CAN_TSR_ALST0 0x00000004U /*!<Arbitration Lost for Mailbox0 */
+#define CAN_TSR_TERR0 0x00000008U /*!<Transmission Error of Mailbox0 */
+#define CAN_TSR_ABRQ0 0x00000080U /*!<Abort Request for Mailbox0 */
+#define CAN_TSR_RQCP1 0x00000100U /*!<Request Completed Mailbox1 */
+#define CAN_TSR_TXOK1 0x00000200U /*!<Transmission OK of Mailbox1 */
+#define CAN_TSR_ALST1 0x00000400U /*!<Arbitration Lost for Mailbox1 */
+#define CAN_TSR_TERR1 0x00000800U /*!<Transmission Error of Mailbox1 */
+#define CAN_TSR_ABRQ1 0x00008000U /*!<Abort Request for Mailbox 1 */
+#define CAN_TSR_RQCP2 0x00010000U /*!<Request Completed Mailbox2 */
+#define CAN_TSR_TXOK2 0x00020000U /*!<Transmission OK of Mailbox 2 */
+#define CAN_TSR_ALST2 0x00040000U /*!<Arbitration Lost for mailbox 2 */
+#define CAN_TSR_TERR2 0x00080000U /*!<Transmission Error of Mailbox 2 */
+#define CAN_TSR_ABRQ2 0x00800000U /*!<Abort Request for Mailbox 2 */
+#define CAN_TSR_CODE 0x03000000U /*!<Mailbox Code */
+
+#define CAN_TSR_TME 0x1C000000U /*!<TME[2:0] bits */
+#define CAN_TSR_TME0 0x04000000U /*!<Transmit Mailbox 0 Empty */
+#define CAN_TSR_TME1 0x08000000U /*!<Transmit Mailbox 1 Empty */
+#define CAN_TSR_TME2 0x10000000U /*!<Transmit Mailbox 2 Empty */
+
+#define CAN_TSR_LOW 0xE0000000U /*!<LOW[2:0] bits */
+#define CAN_TSR_LOW0 0x20000000U /*!<Lowest Priority Flag for Mailbox 0 */
+#define CAN_TSR_LOW1 0x40000000U /*!<Lowest Priority Flag for Mailbox 1 */
+#define CAN_TSR_LOW2 0x80000000U /*!<Lowest Priority Flag for Mailbox 2 */
+
+/******************* Bit definition for CAN_RF0R register *******************/
+#define CAN_RF0R_FMP0 0x03U /*!<FIFO 0 Message Pending */
+#define CAN_RF0R_FULL0 0x08U /*!<FIFO 0 Full */
+#define CAN_RF0R_FOVR0 0x10U /*!<FIFO 0 Overrun */
+#define CAN_RF0R_RFOM0 0x20U /*!<Release FIFO 0 Output Mailbox */
+
+/******************* Bit definition for CAN_RF1R register *******************/
+#define CAN_RF1R_FMP1 0x03U /*!<FIFO 1 Message Pending */
+#define CAN_RF1R_FULL1 0x08U /*!<FIFO 1 Full */
+#define CAN_RF1R_FOVR1 0x10U /*!<FIFO 1 Overrun */
+#define CAN_RF1R_RFOM1 0x20U /*!<Release FIFO 1 Output Mailbox */
+
+/******************** Bit definition for CAN_IER register *******************/
+#define CAN_IER_TMEIE 0x00000001U /*!<Transmit Mailbox Empty Interrupt Enable */
+#define CAN_IER_FMPIE0 0x00000002U /*!<FIFO Message Pending Interrupt Enable */
+#define CAN_IER_FFIE0 0x00000004U /*!<FIFO Full Interrupt Enable */
+#define CAN_IER_FOVIE0 0x00000008U /*!<FIFO Overrun Interrupt Enable */
+#define CAN_IER_FMPIE1 0x00000010U /*!<FIFO Message Pending Interrupt Enable */
+#define CAN_IER_FFIE1 0x00000020U /*!<FIFO Full Interrupt Enable */
+#define CAN_IER_FOVIE1 0x00000040U /*!<FIFO Overrun Interrupt Enable */
+#define CAN_IER_EWGIE 0x00000100U /*!<Error Warning Interrupt Enable */
+#define CAN_IER_EPVIE 0x00000200U /*!<Error Passive Interrupt Enable */
+#define CAN_IER_BOFIE 0x00000400U /*!<Bus-Off Interrupt Enable */
+#define CAN_IER_LECIE 0x00000800U /*!<Last Error Code Interrupt Enable */
+#define CAN_IER_ERRIE 0x00008000U /*!<Error Interrupt Enable */
+#define CAN_IER_WKUIE 0x00010000U /*!<Wakeup Interrupt Enable */
+#define CAN_IER_SLKIE 0x00020000U /*!<Sleep Interrupt Enable */
+#define CAN_IER_EWGIE 0x00000100U /*!<Error warning interrupt enable */
+#define CAN_IER_EPVIE 0x00000200U /*!<Error passive interrupt enable */
+#define CAN_IER_BOFIE 0x00000400U /*!<Bus-off interrupt enable */
+#define CAN_IER_LECIE 0x00000800U /*!<Last error code interrupt enable */
+#define CAN_IER_ERRIE 0x00008000U /*!<Error interrupt enable */
+
+
+/******************** Bit definition for CAN_ESR register *******************/
+#define CAN_ESR_EWGF 0x00000001U /*!<Error Warning Flag */
+#define CAN_ESR_EPVF 0x00000002U /*!<Error Passive Flag */
+#define CAN_ESR_BOFF 0x00000004U /*!<Bus-Off Flag */
+
+#define CAN_ESR_LEC 0x00000070U /*!<LEC[2:0] bits (Last Error Code) */
+#define CAN_ESR_LEC_0 0x00000010U /*!<Bit 0 */
+#define CAN_ESR_LEC_1 0x00000020U /*!<Bit 1 */
+#define CAN_ESR_LEC_2 0x00000040U /*!<Bit 2 */
+
+#define CAN_ESR_TEC 0x00FF0000U /*!<Least significant byte of the 9-bit Transmit Error Counter */
+#define CAN_ESR_REC 0xFF000000U /*!<Receive Error Counter */
+
+/******************* Bit definition for CAN_BTR register ********************/
+#define CAN_BTR_BRP 0x000003FFU /*!<Baud Rate Prescaler */
+#define CAN_BTR_TS1 0x000F0000U /*!<Time Segment 1 */
+#define CAN_BTR_TS1_0 0x00010000U /*!<Bit 0 */
+#define CAN_BTR_TS1_1 0x00020000U /*!<Bit 1 */
+#define CAN_BTR_TS1_2 0x00040000U /*!<Bit 2 */
+#define CAN_BTR_TS1_3 0x00080000U /*!<Bit 3 */
+#define CAN_BTR_TS2 0x00700000U /*!<Time Segment 2 */
+#define CAN_BTR_TS2_0 0x00100000U /*!<Bit 0 */
+#define CAN_BTR_TS2_1 0x00200000U /*!<Bit 1 */
+#define CAN_BTR_TS2_2 0x00400000U /*!<Bit 2 */
+#define CAN_BTR_SJW 0x03000000U /*!<Resynchronization Jump Width */
+#define CAN_BTR_SJW_0 0x01000000U /*!<Bit 0 */
+#define CAN_BTR_SJW_1 0x02000000U /*!<Bit 1 */
+#define CAN_BTR_LBKM 0x40000000U /*!<Loop Back Mode (Debug) */
+#define CAN_BTR_SILM 0x80000000U /*!<Silent Mode */
+
+
+/*!<Mailbox registers */
+/****************** Bit definition for CAN_TI0R register ********************/
+#define CAN_TI0R_TXRQ 0x00000001U /*!<Transmit Mailbox Request */
+#define CAN_TI0R_RTR 0x00000002U /*!<Remote Transmission Request */
+#define CAN_TI0R_IDE 0x00000004U /*!<Identifier Extension */
+#define CAN_TI0R_EXID 0x001FFFF8U /*!<Extended Identifier */
+#define CAN_TI0R_STID 0xFFE00000U /*!<Standard Identifier or Extended Identifier */
+
+/****************** Bit definition for CAN_TDT0R register *******************/
+#define CAN_TDT0R_DLC 0x0000000FU /*!<Data Length Code */
+#define CAN_TDT0R_TGT 0x00000100U /*!<Transmit Global Time */
+#define CAN_TDT0R_TIME 0xFFFF0000U /*!<Message Time Stamp */
+
+/****************** Bit definition for CAN_TDL0R register *******************/
+#define CAN_TDL0R_DATA0 0x000000FFU /*!<Data byte 0 */
+#define CAN_TDL0R_DATA1 0x0000FF00U /*!<Data byte 1 */
+#define CAN_TDL0R_DATA2 0x00FF0000U /*!<Data byte 2 */
+#define CAN_TDL0R_DATA3 0xFF000000U /*!<Data byte 3 */
+
+/****************** Bit definition for CAN_TDH0R register *******************/
+#define CAN_TDH0R_DATA4 0x000000FFU /*!<Data byte 4 */
+#define CAN_TDH0R_DATA5 0x0000FF00U /*!<Data byte 5 */
+#define CAN_TDH0R_DATA6 0x00FF0000U /*!<Data byte 6 */
+#define CAN_TDH0R_DATA7 0xFF000000U /*!<Data byte 7 */
+
+/******************* Bit definition for CAN_TI1R register *******************/
+#define CAN_TI1R_TXRQ 0x00000001U /*!<Transmit Mailbox Request */
+#define CAN_TI1R_RTR 0x00000002U /*!<Remote Transmission Request */
+#define CAN_TI1R_IDE 0x00000004U /*!<Identifier Extension */
+#define CAN_TI1R_EXID 0x001FFFF8U /*!<Extended Identifier */
+#define CAN_TI1R_STID 0xFFE00000U /*!<Standard Identifier or Extended Identifier */
+
+/******************* Bit definition for CAN_TDT1R register ******************/
+#define CAN_TDT1R_DLC 0x0000000FU /*!<Data Length Code */
+#define CAN_TDT1R_TGT 0x00000100U /*!<Transmit Global Time */
+#define CAN_TDT1R_TIME 0xFFFF0000U /*!<Message Time Stamp */
+
+/******************* Bit definition for CAN_TDL1R register ******************/
+#define CAN_TDL1R_DATA0 0x000000FFU /*!<Data byte 0 */
+#define CAN_TDL1R_DATA1 0x0000FF00U /*!<Data byte 1 */
+#define CAN_TDL1R_DATA2 0x00FF0000U /*!<Data byte 2 */
+#define CAN_TDL1R_DATA3 0xFF000000U /*!<Data byte 3 */
+
+/******************* Bit definition for CAN_TDH1R register ******************/
+#define CAN_TDH1R_DATA4 0x000000FFU /*!<Data byte 4 */
+#define CAN_TDH1R_DATA5 0x0000FF00U /*!<Data byte 5 */
+#define CAN_TDH1R_DATA6 0x00FF0000U /*!<Data byte 6 */
+#define CAN_TDH1R_DATA7 0xFF000000U /*!<Data byte 7 */
+
+/******************* Bit definition for CAN_TI2R register *******************/
+#define CAN_TI2R_TXRQ 0x00000001U /*!<Transmit Mailbox Request */
+#define CAN_TI2R_RTR 0x00000002U /*!<Remote Transmission Request */
+#define CAN_TI2R_IDE 0x00000004U /*!<Identifier Extension */
+#define CAN_TI2R_EXID 0x001FFFF8U /*!<Extended identifier */
+#define CAN_TI2R_STID 0xFFE00000U /*!<Standard Identifier or Extended Identifier */
+
+/******************* Bit definition for CAN_TDT2R register ******************/
+#define CAN_TDT2R_DLC 0x0000000FU /*!<Data Length Code */
+#define CAN_TDT2R_TGT 0x00000100U /*!<Transmit Global Time */
+#define CAN_TDT2R_TIME 0xFFFF0000U /*!<Message Time Stamp */
+
+/******************* Bit definition for CAN_TDL2R register ******************/
+#define CAN_TDL2R_DATA0 0x000000FFU /*!<Data byte 0 */
+#define CAN_TDL2R_DATA1 0x0000FF00U /*!<Data byte 1 */
+#define CAN_TDL2R_DATA2 0x00FF0000U /*!<Data byte 2 */
+#define CAN_TDL2R_DATA3 0xFF000000U /*!<Data byte 3 */
+
+/******************* Bit definition for CAN_TDH2R register ******************/
+#define CAN_TDH2R_DATA4 0x000000FFU /*!<Data byte 4 */
+#define CAN_TDH2R_DATA5 0x0000FF00U /*!<Data byte 5 */
+#define CAN_TDH2R_DATA6 0x00FF0000U /*!<Data byte 6 */
+#define CAN_TDH2R_DATA7 0xFF000000U /*!<Data byte 7 */
+
+/******************* Bit definition for CAN_RI0R register *******************/
+#define CAN_RI0R_RTR 0x00000002U /*!<Remote Transmission Request */
+#define CAN_RI0R_IDE 0x00000004U /*!<Identifier Extension */
+#define CAN_RI0R_EXID 0x001FFFF8U /*!<Extended Identifier */
+#define CAN_RI0R_STID 0xFFE00000U /*!<Standard Identifier or Extended Identifier */
+
+/******************* Bit definition for CAN_RDT0R register ******************/
+#define CAN_RDT0R_DLC 0x0000000FU /*!<Data Length Code */
+#define CAN_RDT0R_FMI 0x0000FF00U /*!<Filter Match Index */
+#define CAN_RDT0R_TIME 0xFFFF0000U /*!<Message Time Stamp */
+
+/******************* Bit definition for CAN_RDL0R register ******************/
+#define CAN_RDL0R_DATA0 0x000000FFU /*!<Data byte 0 */
+#define CAN_RDL0R_DATA1 0x0000FF00U /*!<Data byte 1 */
+#define CAN_RDL0R_DATA2 0x00FF0000U /*!<Data byte 2 */
+#define CAN_RDL0R_DATA3 0xFF000000U /*!<Data byte 3 */
+
+/******************* Bit definition for CAN_RDH0R register ******************/
+#define CAN_RDH0R_DATA4 0x000000FFU /*!<Data byte 4 */
+#define CAN_RDH0R_DATA5 0x0000FF00U /*!<Data byte 5 */
+#define CAN_RDH0R_DATA6 0x00FF0000U /*!<Data byte 6 */
+#define CAN_RDH0R_DATA7 0xFF000000U /*!<Data byte 7 */
+
+/******************* Bit definition for CAN_RI1R register *******************/
+#define CAN_RI1R_RTR 0x00000002U /*!<Remote Transmission Request */
+#define CAN_RI1R_IDE 0x00000004U /*!<Identifier Extension */
+#define CAN_RI1R_EXID 0x001FFFF8U /*!<Extended identifier */
+#define CAN_RI1R_STID 0xFFE00000U /*!<Standard Identifier or Extended Identifier */
+
+/******************* Bit definition for CAN_RDT1R register ******************/
+#define CAN_RDT1R_DLC 0x0000000FU /*!<Data Length Code */
+#define CAN_RDT1R_FMI 0x0000FF00U /*!<Filter Match Index */
+#define CAN_RDT1R_TIME 0xFFFF0000U /*!<Message Time Stamp */
+
+/******************* Bit definition for CAN_RDL1R register ******************/
+#define CAN_RDL1R_DATA0 0x000000FFU /*!<Data byte 0 */
+#define CAN_RDL1R_DATA1 0x0000FF00U /*!<Data byte 1 */
+#define CAN_RDL1R_DATA2 0x00FF0000U /*!<Data byte 2 */
+#define CAN_RDL1R_DATA3 0xFF000000U /*!<Data byte 3 */
+
+/******************* Bit definition for CAN_RDH1R register ******************/
+#define CAN_RDH1R_DATA4 0x000000FFU /*!<Data byte 4 */
+#define CAN_RDH1R_DATA5 0x0000FF00U /*!<Data byte 5 */
+#define CAN_RDH1R_DATA6 0x00FF0000U /*!<Data byte 6 */
+#define CAN_RDH1R_DATA7 0xFF000000U /*!<Data byte 7 */
+
+/*!<CAN filter registers */
+/******************* Bit definition for CAN_FMR register ********************/
+#define CAN_FMR_FINIT 0x01U /*!<Filter Init Mode */
+#define CAN_FMR_CAN2SB 0x00003F00U /*!<CAN2 start bank */
+
+/******************* Bit definition for CAN_FM1R register *******************/
+#define CAN_FM1R_FBM 0x0FFFFFFFU /*!<Filter Mode */
+#define CAN_FM1R_FBM0 0x00000001U /*!<Filter Init Mode bit 0 */
+#define CAN_FM1R_FBM1 0x00000002U /*!<Filter Init Mode bit 1 */
+#define CAN_FM1R_FBM2 0x00000004U /*!<Filter Init Mode bit 2 */
+#define CAN_FM1R_FBM3 0x00000008U /*!<Filter Init Mode bit 3 */
+#define CAN_FM1R_FBM4 0x00000010U /*!<Filter Init Mode bit 4 */
+#define CAN_FM1R_FBM5 0x00000020U /*!<Filter Init Mode bit 5 */
+#define CAN_FM1R_FBM6 0x00000040U /*!<Filter Init Mode bit 6 */
+#define CAN_FM1R_FBM7 0x00000080U /*!<Filter Init Mode bit 7 */
+#define CAN_FM1R_FBM8 0x00000100U /*!<Filter Init Mode bit 8 */
+#define CAN_FM1R_FBM9 0x00000200U /*!<Filter Init Mode bit 9 */
+#define CAN_FM1R_FBM10 0x00000400U /*!<Filter Init Mode bit 10 */
+#define CAN_FM1R_FBM11 0x00000800U /*!<Filter Init Mode bit 11 */
+#define CAN_FM1R_FBM12 0x00001000U /*!<Filter Init Mode bit 12 */
+#define CAN_FM1R_FBM13 0x00002000U /*!<Filter Init Mode bit 13 */
+#define CAN_FM1R_FBM14 0x00004000U /*!<Filter Init Mode bit 14 */
+#define CAN_FM1R_FBM15 0x00008000U /*!<Filter Init Mode bit 15 */
+#define CAN_FM1R_FBM16 0x00010000U /*!<Filter Init Mode bit 16 */
+#define CAN_FM1R_FBM17 0x00020000U /*!<Filter Init Mode bit 17 */
+#define CAN_FM1R_FBM18 0x00040000U /*!<Filter Init Mode bit 18 */
+#define CAN_FM1R_FBM19 0x00080000U /*!<Filter Init Mode bit 19 */
+#define CAN_FM1R_FBM20 0x00100000U /*!<Filter Init Mode bit 20 */
+#define CAN_FM1R_FBM21 0x00200000U /*!<Filter Init Mode bit 21 */
+#define CAN_FM1R_FBM22 0x00400000U /*!<Filter Init Mode bit 22 */
+#define CAN_FM1R_FBM23 0x00800000U /*!<Filter Init Mode bit 23 */
+#define CAN_FM1R_FBM24 0x01000000U /*!<Filter Init Mode bit 24 */
+#define CAN_FM1R_FBM25 0x02000000U /*!<Filter Init Mode bit 25 */
+#define CAN_FM1R_FBM26 0x04000000U /*!<Filter Init Mode bit 26 */
+#define CAN_FM1R_FBM27 0x08000000U /*!<Filter Init Mode bit 27 */
+
+/******************* Bit definition for CAN_FS1R register *******************/
+#define CAN_FS1R_FSC 0x0FFFFFFFU /*!<Filter Scale Configuration */
+#define CAN_FS1R_FSC0 0x00000001U /*!<Filter Scale Configuration bit 0 */
+#define CAN_FS1R_FSC1 0x00000002U /*!<Filter Scale Configuration bit 1 */
+#define CAN_FS1R_FSC2 0x00000004U /*!<Filter Scale Configuration bit 2 */
+#define CAN_FS1R_FSC3 0x00000008U /*!<Filter Scale Configuration bit 3 */
+#define CAN_FS1R_FSC4 0x00000010U /*!<Filter Scale Configuration bit 4 */
+#define CAN_FS1R_FSC5 0x00000020U /*!<Filter Scale Configuration bit 5 */
+#define CAN_FS1R_FSC6 0x00000040U /*!<Filter Scale Configuration bit 6 */
+#define CAN_FS1R_FSC7 0x00000080U /*!<Filter Scale Configuration bit 7 */
+#define CAN_FS1R_FSC8 0x00000100U /*!<Filter Scale Configuration bit 8 */
+#define CAN_FS1R_FSC9 0x00000200U /*!<Filter Scale Configuration bit 9 */
+#define CAN_FS1R_FSC10 0x00000400U /*!<Filter Scale Configuration bit 10 */
+#define CAN_FS1R_FSC11 0x00000800U /*!<Filter Scale Configuration bit 11 */
+#define CAN_FS1R_FSC12 0x00001000U /*!<Filter Scale Configuration bit 12 */
+#define CAN_FS1R_FSC13 0x00002000U /*!<Filter Scale Configuration bit 13 */
+#define CAN_FS1R_FSC14 0x00004000U /*!<Filter Scale Configuration bit 14 */
+#define CAN_FS1R_FSC15 0x00008000U /*!<Filter Scale Configuration bit 15 */
+#define CAN_FS1R_FSC16 0x00010000U /*!<Filter Scale Configuration bit 16 */
+#define CAN_FS1R_FSC17 0x00020000U /*!<Filter Scale Configuration bit 17 */
+#define CAN_FS1R_FSC18 0x00040000U /*!<Filter Scale Configuration bit 18 */
+#define CAN_FS1R_FSC19 0x00080000U /*!<Filter Scale Configuration bit 19 */
+#define CAN_FS1R_FSC20 0x00100000U /*!<Filter Scale Configuration bit 20 */
+#define CAN_FS1R_FSC21 0x00200000U /*!<Filter Scale Configuration bit 21 */
+#define CAN_FS1R_FSC22 0x00400000U /*!<Filter Scale Configuration bit 22 */
+#define CAN_FS1R_FSC23 0x00800000U /*!<Filter Scale Configuration bit 23 */
+#define CAN_FS1R_FSC24 0x01000000U /*!<Filter Scale Configuration bit 24 */
+#define CAN_FS1R_FSC25 0x02000000U /*!<Filter Scale Configuration bit 25 */
+#define CAN_FS1R_FSC26 0x04000000U /*!<Filter Scale Configuration bit 26 */
+#define CAN_FS1R_FSC27 0x08000000U /*!<Filter Scale Configuration bit 27 */
+
+/****************** Bit definition for CAN_FFA1R register *******************/
+#define CAN_FFA1R_FFA 0x0FFFFFFFU /*!<Filter FIFO Assignment */
+#define CAN_FFA1R_FFA0 0x00000001U /*!<Filter FIFO Assignment bit 0 */
+#define CAN_FFA1R_FFA1 0x00000002U /*!<Filter FIFO Assignment bit 1 */
+#define CAN_FFA1R_FFA2 0x00000004U /*!<Filter FIFO Assignment bit 2 */
+#define CAN_FFA1R_FFA3 0x00000008U /*!<Filter FIFO Assignment bit 3 */
+#define CAN_FFA1R_FFA4 0x00000010U /*!<Filter FIFO Assignment bit 4 */
+#define CAN_FFA1R_FFA5 0x00000020U /*!<Filter FIFO Assignment bit 5 */
+#define CAN_FFA1R_FFA6 0x00000040U /*!<Filter FIFO Assignment bit 6 */
+#define CAN_FFA1R_FFA7 0x00000080U /*!<Filter FIFO Assignment bit 7 */
+#define CAN_FFA1R_FFA8 0x00000100U /*!<Filter FIFO Assignment bit 8 */
+#define CAN_FFA1R_FFA9 0x00000200U /*!<Filter FIFO Assignment bit 9 */
+#define CAN_FFA1R_FFA10 0x00000400U /*!<Filter FIFO Assignment bit 10 */
+#define CAN_FFA1R_FFA11 0x00000800U /*!<Filter FIFO Assignment bit 11 */
+#define CAN_FFA1R_FFA12 0x00001000U /*!<Filter FIFO Assignment bit 12 */
+#define CAN_FFA1R_FFA13 0x00002000U /*!<Filter FIFO Assignment bit 13 */
+#define CAN_FFA1R_FFA14 0x00004000U /*!<Filter FIFO Assignment bit 14 */
+#define CAN_FFA1R_FFA15 0x00008000U /*!<Filter FIFO Assignment bit 15 */
+#define CAN_FFA1R_FFA16 0x00010000U /*!<Filter FIFO Assignment bit 16 */
+#define CAN_FFA1R_FFA17 0x00020000U /*!<Filter FIFO Assignment bit 17 */
+#define CAN_FFA1R_FFA18 0x00040000U /*!<Filter FIFO Assignment bit 18 */
+#define CAN_FFA1R_FFA19 0x00080000U /*!<Filter FIFO Assignment bit 19 */
+#define CAN_FFA1R_FFA20 0x00100000U /*!<Filter FIFO Assignment bit 20 */
+#define CAN_FFA1R_FFA21 0x00200000U /*!<Filter FIFO Assignment bit 21 */
+#define CAN_FFA1R_FFA22 0x00400000U /*!<Filter FIFO Assignment bit 22 */
+#define CAN_FFA1R_FFA23 0x00800000U /*!<Filter FIFO Assignment bit 23 */
+#define CAN_FFA1R_FFA24 0x01000000U /*!<Filter FIFO Assignment bit 24 */
+#define CAN_FFA1R_FFA25 0x02000000U /*!<Filter FIFO Assignment bit 25 */
+#define CAN_FFA1R_FFA26 0x04000000U /*!<Filter FIFO Assignment bit 26 */
+#define CAN_FFA1R_FFA27 0x08000000U /*!<Filter FIFO Assignment bit 27 */
+
+/******************* Bit definition for CAN_FA1R register *******************/
+#define CAN_FA1R_FACT 0x0FFFFFFFU /*!<Filter Active */
+#define CAN_FA1R_FACT0 0x00000001U /*!<Filter Active bit 0 */
+#define CAN_FA1R_FACT1 0x00000002U /*!<Filter Active bit 1 */
+#define CAN_FA1R_FACT2 0x00000004U /*!<Filter Active bit 2 */
+#define CAN_FA1R_FACT3 0x00000008U /*!<Filter Active bit 3 */
+#define CAN_FA1R_FACT4 0x00000010U /*!<Filter Active bit 4 */
+#define CAN_FA1R_FACT5 0x00000020U /*!<Filter Active bit 5 */
+#define CAN_FA1R_FACT6 0x00000040U /*!<Filter Active bit 6 */
+#define CAN_FA1R_FACT7 0x00000080U /*!<Filter Active bit 7 */
+#define CAN_FA1R_FACT8 0x00000100U /*!<Filter Active bit 8 */
+#define CAN_FA1R_FACT9 0x00000200U /*!<Filter Active bit 9 */
+#define CAN_FA1R_FACT10 0x00000400U /*!<Filter Active bit 10 */
+#define CAN_FA1R_FACT11 0x00000800U /*!<Filter Active bit 11 */
+#define CAN_FA1R_FACT12 0x00001000U /*!<Filter Active bit 12 */
+#define CAN_FA1R_FACT13 0x00002000U /*!<Filter Active bit 13 */
+#define CAN_FA1R_FACT14 0x00004000U /*!<Filter Active bit 14 */
+#define CAN_FA1R_FACT15 0x00008000U /*!<Filter Active bit 15 */
+#define CAN_FA1R_FACT16 0x00010000U /*!<Filter Active bit 16 */
+#define CAN_FA1R_FACT17 0x00020000U /*!<Filter Active bit 17 */
+#define CAN_FA1R_FACT18 0x00040000U /*!<Filter Active bit 18 */
+#define CAN_FA1R_FACT19 0x00080000U /*!<Filter Active bit 19 */
+#define CAN_FA1R_FACT20 0x00100000U /*!<Filter Active bit 20 */
+#define CAN_FA1R_FACT21 0x00200000U /*!<Filter Active bit 21 */
+#define CAN_FA1R_FACT22 0x00400000U /*!<Filter Active bit 22 */
+#define CAN_FA1R_FACT23 0x00800000U /*!<Filter Active bit 23 */
+#define CAN_FA1R_FACT24 0x01000000U /*!<Filter Active bit 24 */
+#define CAN_FA1R_FACT25 0x02000000U /*!<Filter Active bit 25 */
+#define CAN_FA1R_FACT26 0x04000000U /*!<Filter Active bit 26 */
+#define CAN_FA1R_FACT27 0x08000000U /*!<Filter Active bit 27 */
+
+/******************* Bit definition for CAN_F0R1 register *******************/
+#define CAN_F0R1_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F0R1_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F0R1_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F0R1_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F0R1_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F0R1_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F0R1_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F0R1_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F0R1_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F0R1_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F0R1_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F0R1_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F0R1_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F0R1_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F0R1_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F0R1_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F0R1_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F0R1_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F0R1_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F0R1_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F0R1_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F0R1_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F0R1_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F0R1_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F0R1_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F0R1_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F0R1_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F0R1_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F0R1_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F0R1_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F0R1_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F0R1_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F1R1 register *******************/
+#define CAN_F1R1_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F1R1_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F1R1_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F1R1_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F1R1_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F1R1_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F1R1_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F1R1_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F1R1_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F1R1_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F1R1_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F1R1_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F1R1_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F1R1_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F1R1_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F1R1_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F1R1_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F1R1_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F1R1_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F1R1_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F1R1_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F1R1_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F1R1_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F1R1_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F1R1_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F1R1_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F1R1_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F1R1_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F1R1_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F1R1_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F1R1_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F1R1_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F2R1 register *******************/
+#define CAN_F2R1_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F2R1_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F2R1_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F2R1_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F2R1_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F2R1_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F2R1_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F2R1_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F2R1_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F2R1_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F2R1_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F2R1_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F2R1_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F2R1_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F2R1_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F2R1_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F2R1_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F2R1_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F2R1_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F2R1_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F2R1_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F2R1_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F2R1_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F2R1_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F2R1_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F2R1_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F2R1_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F2R1_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F2R1_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F2R1_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F2R1_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F2R1_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F3R1 register *******************/
+#define CAN_F3R1_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F3R1_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F3R1_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F3R1_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F3R1_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F3R1_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F3R1_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F3R1_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F3R1_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F3R1_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F3R1_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F3R1_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F3R1_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F3R1_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F3R1_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F3R1_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F3R1_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F3R1_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F3R1_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F3R1_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F3R1_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F3R1_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F3R1_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F3R1_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F3R1_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F3R1_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F3R1_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F3R1_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F3R1_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F3R1_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F3R1_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F3R1_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F4R1 register *******************/
+#define CAN_F4R1_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F4R1_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F4R1_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F4R1_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F4R1_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F4R1_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F4R1_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F4R1_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F4R1_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F4R1_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F4R1_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F4R1_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F4R1_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F4R1_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F4R1_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F4R1_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F4R1_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F4R1_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F4R1_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F4R1_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F4R1_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F4R1_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F4R1_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F4R1_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F4R1_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F4R1_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F4R1_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F4R1_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F4R1_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F4R1_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F4R1_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F4R1_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F5R1 register *******************/
+#define CAN_F5R1_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F5R1_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F5R1_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F5R1_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F5R1_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F5R1_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F5R1_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F5R1_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F5R1_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F5R1_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F5R1_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F5R1_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F5R1_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F5R1_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F5R1_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F5R1_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F5R1_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F5R1_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F5R1_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F5R1_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F5R1_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F5R1_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F5R1_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F5R1_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F5R1_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F5R1_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F5R1_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F5R1_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F5R1_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F5R1_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F5R1_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F5R1_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F6R1 register *******************/
+#define CAN_F6R1_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F6R1_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F6R1_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F6R1_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F6R1_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F6R1_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F6R1_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F6R1_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F6R1_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F6R1_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F6R1_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F6R1_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F6R1_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F6R1_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F6R1_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F6R1_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F6R1_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F6R1_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F6R1_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F6R1_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F6R1_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F6R1_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F6R1_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F6R1_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F6R1_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F6R1_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F6R1_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F6R1_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F6R1_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F6R1_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F6R1_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F6R1_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F7R1 register *******************/
+#define CAN_F7R1_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F7R1_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F7R1_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F7R1_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F7R1_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F7R1_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F7R1_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F7R1_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F7R1_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F7R1_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F7R1_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F7R1_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F7R1_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F7R1_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F7R1_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F7R1_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F7R1_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F7R1_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F7R1_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F7R1_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F7R1_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F7R1_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F7R1_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F7R1_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F7R1_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F7R1_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F7R1_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F7R1_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F7R1_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F7R1_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F7R1_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F7R1_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F8R1 register *******************/
+#define CAN_F8R1_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F8R1_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F8R1_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F8R1_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F8R1_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F8R1_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F8R1_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F8R1_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F8R1_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F8R1_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F8R1_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F8R1_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F8R1_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F8R1_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F8R1_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F8R1_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F8R1_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F8R1_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F8R1_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F8R1_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F8R1_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F8R1_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F8R1_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F8R1_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F8R1_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F8R1_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F8R1_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F8R1_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F8R1_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F8R1_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F8R1_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F8R1_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F9R1 register *******************/
+#define CAN_F9R1_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F9R1_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F9R1_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F9R1_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F9R1_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F9R1_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F9R1_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F9R1_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F9R1_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F9R1_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F9R1_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F9R1_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F9R1_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F9R1_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F9R1_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F9R1_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F9R1_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F9R1_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F9R1_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F9R1_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F9R1_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F9R1_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F9R1_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F9R1_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F9R1_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F9R1_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F9R1_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F9R1_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F9R1_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F9R1_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F9R1_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F9R1_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F10R1 register ******************/
+#define CAN_F10R1_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F10R1_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F10R1_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F10R1_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F10R1_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F10R1_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F10R1_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F10R1_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F10R1_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F10R1_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F10R1_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F10R1_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F10R1_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F10R1_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F10R1_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F10R1_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F10R1_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F10R1_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F10R1_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F10R1_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F10R1_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F10R1_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F10R1_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F10R1_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F10R1_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F10R1_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F10R1_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F10R1_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F10R1_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F10R1_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F10R1_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F10R1_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F11R1 register ******************/
+#define CAN_F11R1_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F11R1_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F11R1_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F11R1_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F11R1_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F11R1_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F11R1_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F11R1_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F11R1_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F11R1_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F11R1_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F11R1_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F11R1_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F11R1_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F11R1_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F11R1_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F11R1_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F11R1_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F11R1_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F11R1_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F11R1_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F11R1_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F11R1_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F11R1_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F11R1_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F11R1_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F11R1_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F11R1_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F11R1_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F11R1_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F11R1_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F11R1_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F12R1 register ******************/
+#define CAN_F12R1_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F12R1_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F12R1_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F12R1_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F12R1_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F12R1_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F12R1_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F12R1_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F12R1_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F12R1_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F12R1_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F12R1_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F12R1_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F12R1_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F12R1_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F12R1_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F12R1_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F12R1_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F12R1_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F12R1_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F12R1_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F12R1_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F12R1_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F12R1_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F12R1_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F12R1_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F12R1_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F12R1_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F12R1_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F12R1_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F12R1_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F12R1_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F13R1 register ******************/
+#define CAN_F13R1_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F13R1_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F13R1_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F13R1_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F13R1_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F13R1_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F13R1_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F13R1_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F13R1_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F13R1_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F13R1_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F13R1_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F13R1_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F13R1_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F13R1_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F13R1_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F13R1_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F13R1_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F13R1_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F13R1_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F13R1_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F13R1_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F13R1_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F13R1_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F13R1_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F13R1_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F13R1_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F13R1_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F13R1_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F13R1_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F13R1_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F13R1_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F0R2 register *******************/
+#define CAN_F0R2_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F0R2_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F0R2_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F0R2_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F0R2_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F0R2_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F0R2_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F0R2_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F0R2_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F0R2_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F0R2_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F0R2_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F0R2_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F0R2_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F0R2_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F0R2_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F0R2_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F0R2_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F0R2_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F0R2_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F0R2_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F0R2_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F0R2_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F0R2_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F0R2_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F0R2_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F0R2_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F0R2_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F0R2_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F0R2_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F0R2_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F0R2_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F1R2 register *******************/
+#define CAN_F1R2_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F1R2_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F1R2_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F1R2_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F1R2_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F1R2_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F1R2_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F1R2_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F1R2_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F1R2_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F1R2_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F1R2_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F1R2_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F1R2_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F1R2_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F1R2_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F1R2_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F1R2_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F1R2_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F1R2_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F1R2_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F1R2_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F1R2_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F1R2_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F1R2_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F1R2_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F1R2_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F1R2_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F1R2_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F1R2_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F1R2_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F1R2_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F2R2 register *******************/
+#define CAN_F2R2_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F2R2_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F2R2_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F2R2_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F2R2_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F2R2_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F2R2_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F2R2_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F2R2_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F2R2_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F2R2_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F2R2_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F2R2_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F2R2_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F2R2_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F2R2_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F2R2_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F2R2_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F2R2_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F2R2_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F2R2_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F2R2_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F2R2_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F2R2_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F2R2_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F2R2_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F2R2_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F2R2_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F2R2_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F2R2_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F2R2_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F2R2_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F3R2 register *******************/
+#define CAN_F3R2_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F3R2_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F3R2_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F3R2_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F3R2_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F3R2_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F3R2_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F3R2_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F3R2_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F3R2_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F3R2_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F3R2_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F3R2_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F3R2_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F3R2_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F3R2_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F3R2_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F3R2_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F3R2_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F3R2_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F3R2_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F3R2_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F3R2_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F3R2_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F3R2_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F3R2_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F3R2_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F3R2_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F3R2_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F3R2_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F3R2_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F3R2_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F4R2 register *******************/
+#define CAN_F4R2_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F4R2_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F4R2_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F4R2_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F4R2_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F4R2_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F4R2_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F4R2_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F4R2_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F4R2_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F4R2_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F4R2_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F4R2_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F4R2_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F4R2_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F4R2_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F4R2_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F4R2_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F4R2_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F4R2_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F4R2_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F4R2_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F4R2_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F4R2_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F4R2_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F4R2_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F4R2_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F4R2_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F4R2_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F4R2_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F4R2_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F4R2_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F5R2 register *******************/
+#define CAN_F5R2_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F5R2_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F5R2_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F5R2_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F5R2_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F5R2_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F5R2_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F5R2_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F5R2_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F5R2_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F5R2_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F5R2_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F5R2_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F5R2_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F5R2_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F5R2_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F5R2_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F5R2_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F5R2_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F5R2_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F5R2_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F5R2_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F5R2_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F5R2_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F5R2_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F5R2_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F5R2_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F5R2_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F5R2_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F5R2_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F5R2_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F5R2_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F6R2 register *******************/
+#define CAN_F6R2_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F6R2_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F6R2_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F6R2_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F6R2_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F6R2_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F6R2_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F6R2_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F6R2_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F6R2_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F6R2_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F6R2_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F6R2_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F6R2_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F6R2_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F6R2_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F6R2_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F6R2_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F6R2_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F6R2_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F6R2_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F6R2_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F6R2_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F6R2_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F6R2_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F6R2_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F6R2_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F6R2_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F6R2_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F6R2_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F6R2_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F6R2_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F7R2 register *******************/
+#define CAN_F7R2_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F7R2_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F7R2_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F7R2_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F7R2_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F7R2_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F7R2_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F7R2_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F7R2_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F7R2_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F7R2_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F7R2_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F7R2_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F7R2_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F7R2_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F7R2_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F7R2_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F7R2_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F7R2_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F7R2_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F7R2_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F7R2_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F7R2_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F7R2_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F7R2_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F7R2_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F7R2_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F7R2_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F7R2_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F7R2_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F7R2_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F7R2_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F8R2 register *******************/
+#define CAN_F8R2_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F8R2_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F8R2_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F8R2_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F8R2_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F8R2_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F8R2_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F8R2_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F8R2_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F8R2_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F8R2_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F8R2_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F8R2_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F8R2_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F8R2_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F8R2_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F8R2_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F8R2_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F8R2_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F8R2_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F8R2_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F8R2_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F8R2_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F8R2_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F8R2_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F8R2_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F8R2_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F8R2_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F8R2_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F8R2_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F8R2_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F8R2_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F9R2 register *******************/
+#define CAN_F9R2_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F9R2_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F9R2_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F9R2_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F9R2_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F9R2_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F9R2_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F9R2_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F9R2_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F9R2_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F9R2_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F9R2_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F9R2_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F9R2_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F9R2_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F9R2_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F9R2_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F9R2_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F9R2_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F9R2_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F9R2_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F9R2_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F9R2_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F9R2_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F9R2_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F9R2_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F9R2_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F9R2_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F9R2_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F9R2_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F9R2_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F9R2_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F10R2 register ******************/
+#define CAN_F10R2_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F10R2_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F10R2_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F10R2_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F10R2_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F10R2_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F10R2_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F10R2_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F10R2_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F10R2_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F10R2_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F10R2_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F10R2_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F10R2_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F10R2_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F10R2_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F10R2_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F10R2_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F10R2_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F10R2_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F10R2_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F10R2_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F10R2_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F10R2_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F10R2_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F10R2_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F10R2_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F10R2_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F10R2_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F10R2_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F10R2_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F10R2_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F11R2 register ******************/
+#define CAN_F11R2_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F11R2_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F11R2_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F11R2_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F11R2_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F11R2_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F11R2_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F11R2_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F11R2_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F11R2_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F11R2_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F11R2_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F11R2_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F11R2_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F11R2_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F11R2_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F11R2_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F11R2_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F11R2_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F11R2_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F11R2_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F11R2_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F11R2_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F11R2_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F11R2_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F11R2_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F11R2_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F11R2_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F11R2_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F11R2_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F11R2_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F11R2_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F12R2 register ******************/
+#define CAN_F12R2_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F12R2_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F12R2_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F12R2_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F12R2_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F12R2_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F12R2_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F12R2_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F12R2_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F12R2_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F12R2_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F12R2_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F12R2_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F12R2_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F12R2_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F12R2_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F12R2_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F12R2_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F12R2_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F12R2_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F12R2_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F12R2_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F12R2_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F12R2_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F12R2_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F12R2_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F12R2_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F12R2_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F12R2_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F12R2_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F12R2_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F12R2_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F13R2 register ******************/
+#define CAN_F13R2_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F13R2_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F13R2_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F13R2_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F13R2_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F13R2_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F13R2_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F13R2_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F13R2_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F13R2_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F13R2_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F13R2_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F13R2_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F13R2_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F13R2_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F13R2_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F13R2_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F13R2_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F13R2_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F13R2_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F13R2_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F13R2_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F13R2_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F13R2_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F13R2_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F13R2_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F13R2_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F13R2_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F13R2_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F13R2_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F13R2_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F13R2_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************************************************************************/
+/* */
+/* CRC calculation unit */
+/* */
+/******************************************************************************/
+/******************* Bit definition for CRC_DR register *********************/
+#define CRC_DR_DR 0xFFFFFFFFU /*!< Data register bits */
+
+
+/******************* Bit definition for CRC_IDR register ********************/
+#define CRC_IDR_IDR 0xFFU /*!< General-purpose 8-bit data register bits */
+
+
+/******************** Bit definition for CRC_CR register ********************/
+#define CRC_CR_RESET 0x01U /*!< RESET bit */
+
+/******************************************************************************/
+/* */
+/* Crypto Processor */
+/* */
+/******************************************************************************/
+/******************* Bits definition for CRYP_CR register ********************/
+#define CRYP_CR_ALGODIR 0x00000004U
+
+#define CRYP_CR_ALGOMODE 0x00080038U
+#define CRYP_CR_ALGOMODE_0 0x00000008U
+#define CRYP_CR_ALGOMODE_1 0x00000010U
+#define CRYP_CR_ALGOMODE_2 0x00000020U
+#define CRYP_CR_ALGOMODE_TDES_ECB 0x00000000U
+#define CRYP_CR_ALGOMODE_TDES_CBC 0x00000008U
+#define CRYP_CR_ALGOMODE_DES_ECB 0x00000010U
+#define CRYP_CR_ALGOMODE_DES_CBC 0x00000018U
+#define CRYP_CR_ALGOMODE_AES_ECB 0x00000020U
+#define CRYP_CR_ALGOMODE_AES_CBC 0x00000028U
+#define CRYP_CR_ALGOMODE_AES_CTR 0x00000030U
+#define CRYP_CR_ALGOMODE_AES_KEY 0x00000038U
+
+#define CRYP_CR_DATATYPE 0x000000C0U
+#define CRYP_CR_DATATYPE_0 0x00000040U
+#define CRYP_CR_DATATYPE_1 0x00000080U
+#define CRYP_CR_KEYSIZE 0x00000300U
+#define CRYP_CR_KEYSIZE_0 0x00000100U
+#define CRYP_CR_KEYSIZE_1 0x00000200U
+#define CRYP_CR_FFLUSH 0x00004000U
+#define CRYP_CR_CRYPEN 0x00008000U
+
+#define CRYP_CR_GCM_CCMPH 0x00030000U
+#define CRYP_CR_GCM_CCMPH_0 0x00010000U
+#define CRYP_CR_GCM_CCMPH_1 0x00020000U
+#define CRYP_CR_ALGOMODE_3 0x00080000U
+
+/****************** Bits definition for CRYP_SR register *********************/
+#define CRYP_SR_IFEM 0x00000001U
+#define CRYP_SR_IFNF 0x00000002U
+#define CRYP_SR_OFNE 0x00000004U
+#define CRYP_SR_OFFU 0x00000008U
+#define CRYP_SR_BUSY 0x00000010U
+/****************** Bits definition for CRYP_DMACR register ******************/
+#define CRYP_DMACR_DIEN 0x00000001U
+#define CRYP_DMACR_DOEN 0x00000002U
+/***************** Bits definition for CRYP_IMSCR register ******************/
+#define CRYP_IMSCR_INIM 0x00000001U
+#define CRYP_IMSCR_OUTIM 0x00000002U
+/****************** Bits definition for CRYP_RISR register *******************/
+#define CRYP_RISR_OUTRIS 0x00000001U
+#define CRYP_RISR_INRIS 0x00000002U
+/****************** Bits definition for CRYP_MISR register *******************/
+#define CRYP_MISR_INMIS 0x00000001U
+#define CRYP_MISR_OUTMIS 0x00000002U
+
+/******************************************************************************/
+/* */
+/* Digital to Analog Converter */
+/* */
+/******************************************************************************/
+/******************** Bit definition for DAC_CR register ********************/
+#define DAC_CR_EN1 0x00000001U /*!<DAC channel1 enable */
+#define DAC_CR_BOFF1 0x00000002U /*!<DAC channel1 output buffer disable */
+#define DAC_CR_TEN1 0x00000004U /*!<DAC channel1 Trigger enable */
+
+#define DAC_CR_TSEL1 0x00000038U /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */
+#define DAC_CR_TSEL1_0 0x00000008U /*!<Bit 0 */
+#define DAC_CR_TSEL1_1 0x00000010U /*!<Bit 1 */
+#define DAC_CR_TSEL1_2 0x00000020U /*!<Bit 2 */
+
+#define DAC_CR_WAVE1 0x000000C0U /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
+#define DAC_CR_WAVE1_0 0x00000040U /*!<Bit 0 */
+#define DAC_CR_WAVE1_1 0x00000080U /*!<Bit 1 */
+
+#define DAC_CR_MAMP1 0x00000F00U /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
+#define DAC_CR_MAMP1_0 0x00000100U /*!<Bit 0 */
+#define DAC_CR_MAMP1_1 0x00000200U /*!<Bit 1 */
+#define DAC_CR_MAMP1_2 0x00000400U /*!<Bit 2 */
+#define DAC_CR_MAMP1_3 0x00000800U /*!<Bit 3 */
+
+#define DAC_CR_DMAEN1 0x00001000U /*!<DAC channel1 DMA enable */
+#define DAC_CR_DMAUDRIE1 0x00002000U /*!<DAC channel1 DMA underrun interrupt enable*/
+#define DAC_CR_EN2 0x00010000U /*!<DAC channel2 enable */
+#define DAC_CR_BOFF2 0x00020000U /*!<DAC channel2 output buffer disable */
+#define DAC_CR_TEN2 0x00040000U /*!<DAC channel2 Trigger enable */
+
+#define DAC_CR_TSEL2 0x00380000U /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */
+#define DAC_CR_TSEL2_0 0x00080000U /*!<Bit 0 */
+#define DAC_CR_TSEL2_1 0x00100000U /*!<Bit 1 */
+#define DAC_CR_TSEL2_2 0x00200000U /*!<Bit 2 */
+
+#define DAC_CR_WAVE2 0x00C00000U /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
+#define DAC_CR_WAVE2_0 0x00400000U /*!<Bit 0 */
+#define DAC_CR_WAVE2_1 0x00800000U /*!<Bit 1 */
+
+#define DAC_CR_MAMP2 0x0F000000U /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
+#define DAC_CR_MAMP2_0 0x01000000U /*!<Bit 0 */
+#define DAC_CR_MAMP2_1 0x02000000U /*!<Bit 1 */
+#define DAC_CR_MAMP2_2 0x04000000U /*!<Bit 2 */
+#define DAC_CR_MAMP2_3 0x08000000U /*!<Bit 3 */
+
+#define DAC_CR_DMAEN2 0x10000000U /*!<DAC channel2 DMA enabled */
+#define DAC_CR_DMAUDRIE2 0x20000000U /*!<DAC channel2 DMA underrun interrupt enable*/
+
+/***************** Bit definition for DAC_SWTRIGR register ******************/
+#define DAC_SWTRIGR_SWTRIG1 0x01U /*!<DAC channel1 software trigger */
+#define DAC_SWTRIGR_SWTRIG2 0x02U /*!<DAC channel2 software trigger */
+
+/***************** Bit definition for DAC_DHR12R1 register ******************/
+#define DAC_DHR12R1_DACC1DHR 0x0FFFU /*!<DAC channel1 12-bit Right aligned data */
+
+/***************** Bit definition for DAC_DHR12L1 register ******************/
+#define DAC_DHR12L1_DACC1DHR 0xFFF0U /*!<DAC channel1 12-bit Left aligned data */
+
+/****************** Bit definition for DAC_DHR8R1 register ******************/
+#define DAC_DHR8R1_DACC1DHR 0xFFU /*!<DAC channel1 8-bit Right aligned data */
+
+/***************** Bit definition for DAC_DHR12R2 register ******************/
+#define DAC_DHR12R2_DACC2DHR 0x0FFFU /*!<DAC channel2 12-bit Right aligned data */
+
+/***************** Bit definition for DAC_DHR12L2 register ******************/
+#define DAC_DHR12L2_DACC2DHR 0xFFF0U /*!<DAC channel2 12-bit Left aligned data */
+
+/****************** Bit definition for DAC_DHR8R2 register ******************/
+#define DAC_DHR8R2_DACC2DHR 0xFFU /*!<DAC channel2 8-bit Right aligned data */
+
+/***************** Bit definition for DAC_DHR12RD register ******************/
+#define DAC_DHR12RD_DACC1DHR 0x00000FFFU /*!<DAC channel1 12-bit Right aligned data */
+#define DAC_DHR12RD_DACC2DHR 0x0FFF0000U /*!<DAC channel2 12-bit Right aligned data */
+
+/***************** Bit definition for DAC_DHR12LD register ******************/
+#define DAC_DHR12LD_DACC1DHR 0x0000FFF0U /*!<DAC channel1 12-bit Left aligned data */
+#define DAC_DHR12LD_DACC2DHR 0xFFF00000U /*!<DAC channel2 12-bit Left aligned data */
+
+/****************** Bit definition for DAC_DHR8RD register ******************/
+#define DAC_DHR8RD_DACC1DHR 0x00FFU /*!<DAC channel1 8-bit Right aligned data */
+#define DAC_DHR8RD_DACC2DHR 0xFF00U /*!<DAC channel2 8-bit Right aligned data */
+
+/******************* Bit definition for DAC_DOR1 register *******************/
+#define DAC_DOR1_DACC1DOR 0x0FFFU /*!<DAC channel1 data output */
+
+/******************* Bit definition for DAC_DOR2 register *******************/
+#define DAC_DOR2_DACC2DOR 0x0FFFU /*!<DAC channel2 data output */
+
+/******************** Bit definition for DAC_SR register ********************/
+#define DAC_SR_DMAUDR1 0x00002000U /*!<DAC channel1 DMA underrun flag */
+#define DAC_SR_DMAUDR2 0x20000000U /*!<DAC channel2 DMA underrun flag */
+
+/******************************************************************************/
+/* */
+/* Debug MCU */
+/* */
+/******************************************************************************/
+
+/******************************************************************************/
+/* */
+/* DCMI */
+/* */
+/******************************************************************************/
+/******************** Bits definition for DCMI_CR register ******************/
+#define DCMI_CR_CAPTURE 0x00000001U
+#define DCMI_CR_CM 0x00000002U
+#define DCMI_CR_CROP 0x00000004U
+#define DCMI_CR_JPEG 0x00000008U
+#define DCMI_CR_ESS 0x00000010U
+#define DCMI_CR_PCKPOL 0x00000020U
+#define DCMI_CR_HSPOL 0x00000040U
+#define DCMI_CR_VSPOL 0x00000080U
+#define DCMI_CR_FCRC_0 0x00000100U
+#define DCMI_CR_FCRC_1 0x00000200U
+#define DCMI_CR_EDM_0 0x00000400U
+#define DCMI_CR_EDM_1 0x00000800U
+#define DCMI_CR_CRE 0x00001000U
+#define DCMI_CR_ENABLE 0x00004000U
+
+/******************** Bits definition for DCMI_SR register ******************/
+#define DCMI_SR_HSYNC 0x00000001U
+#define DCMI_SR_VSYNC 0x00000002U
+#define DCMI_SR_FNE 0x00000004U
+
+/******************** Bits definition for DCMI_RIS register *****************/
+#define DCMI_RIS_FRAME_RIS 0x00000001U
+#define DCMI_RIS_OVR_RIS 0x00000002U
+#define DCMI_RIS_ERR_RIS 0x00000004U
+#define DCMI_RIS_VSYNC_RIS 0x00000008U
+#define DCMI_RIS_LINE_RIS 0x00000010U
+/* Legacy defines */
+#define DCMI_RISR_FRAME_RIS DCMI_RIS_FRAME_RIS
+#define DCMI_RISR_OVR_RIS DCMI_RIS_OVR_RIS
+#define DCMI_RISR_ERR_RIS DCMI_RIS_ERR_RIS
+#define DCMI_RISR_VSYNC_RIS DCMI_RIS_VSYNC_RIS
+#define DCMI_RISR_LINE_RIS DCMI_RIS_LINE_RIS
+#define DCMI_RISR_OVF_RIS DCMI_RIS_OVR_RIS
+
+/******************** Bits definition for DCMI_IER register *****************/
+#define DCMI_IER_FRAME_IE 0x00000001U
+#define DCMI_IER_OVR_IE 0x00000002U
+#define DCMI_IER_ERR_IE 0x00000004U
+#define DCMI_IER_VSYNC_IE 0x00000008U
+#define DCMI_IER_LINE_IE 0x00000010U
+/* Legacy defines */
+#define DCMI_IER_OVF_IE DCMI_IER_OVR_IE
+
+/******************** Bits definition for DCMI_MIS register *****************/
+#define DCMI_MIS_FRAME_MIS 0x00000001U
+#define DCMI_MIS_OVR_MIS 0x00000002U
+#define DCMI_MIS_ERR_MIS 0x00000004U
+#define DCMI_MIS_VSYNC_MIS 0x00000008U
+#define DCMI_MIS_LINE_MIS 0x00000010U
+
+/* Legacy defines */
+#define DCMI_MISR_FRAME_MIS DCMI_MIS_FRAME_MIS
+#define DCMI_MISR_OVF_MIS DCMI_MIS_OVR_MIS
+#define DCMI_MISR_ERR_MIS DCMI_MIS_ERR_MIS
+#define DCMI_MISR_VSYNC_MIS DCMI_MIS_VSYNC_MIS
+#define DCMI_MISR_LINE_MIS DCMI_MIS_LINE_MIS
+
+/******************** Bits definition for DCMI_ICR register *****************/
+#define DCMI_ICR_FRAME_ISC 0x00000001U
+#define DCMI_ICR_OVR_ISC 0x00000002U
+#define DCMI_ICR_ERR_ISC 0x00000004U
+#define DCMI_ICR_VSYNC_ISC 0x00000008U
+#define DCMI_ICR_LINE_ISC 0x00000010U
+
+/* Legacy defines */
+#define DCMI_ICR_OVF_ISC DCMI_ICR_OVR_ISC
+
+/******************** Bits definition for DCMI_ESCR register ******************/
+#define DCMI_ESCR_FSC 0x000000FFU
+#define DCMI_ESCR_LSC 0x0000FF00U
+#define DCMI_ESCR_LEC 0x00FF0000U
+#define DCMI_ESCR_FEC 0xFF000000U
+
+/******************** Bits definition for DCMI_ESUR register ******************/
+#define DCMI_ESUR_FSU 0x000000FFU
+#define DCMI_ESUR_LSU 0x0000FF00U
+#define DCMI_ESUR_LEU 0x00FF0000U
+#define DCMI_ESUR_FEU 0xFF000000U
+
+/******************** Bits definition for DCMI_CWSTRT register ******************/
+#define DCMI_CWSTRT_HOFFCNT 0x00003FFFU
+#define DCMI_CWSTRT_VST 0x1FFF0000U
+
+/******************** Bits definition for DCMI_CWSIZE register ******************/
+#define DCMI_CWSIZE_CAPCNT 0x00003FFFU
+#define DCMI_CWSIZE_VLINE 0x3FFF0000U
+
+/******************** Bits definition for DCMI_DR register ******************/
+#define DCMI_DR_BYTE0 0x000000FFU
+#define DCMI_DR_BYTE1 0x0000FF00U
+#define DCMI_DR_BYTE2 0x00FF0000U
+#define DCMI_DR_BYTE3 0xFF000000U
+
+/******************************************************************************/
+/* */
+/* DMA Controller */
+/* */
+/******************************************************************************/
+/******************** Bits definition for DMA_SxCR register *****************/
+#define DMA_SxCR_CHSEL 0x0E000000U
+#define DMA_SxCR_CHSEL_0 0x02000000U
+#define DMA_SxCR_CHSEL_1 0x04000000U
+#define DMA_SxCR_CHSEL_2 0x08000000U
+#define DMA_SxCR_MBURST 0x01800000U
+#define DMA_SxCR_MBURST_0 0x00800000U
+#define DMA_SxCR_MBURST_1 0x01000000U
+#define DMA_SxCR_PBURST 0x00600000U
+#define DMA_SxCR_PBURST_0 0x00200000U
+#define DMA_SxCR_PBURST_1 0x00400000U
+#define DMA_SxCR_CT 0x00080000U
+#define DMA_SxCR_DBM 0x00040000U
+#define DMA_SxCR_PL 0x00030000U
+#define DMA_SxCR_PL_0 0x00010000U
+#define DMA_SxCR_PL_1 0x00020000U
+#define DMA_SxCR_PINCOS 0x00008000U
+#define DMA_SxCR_MSIZE 0x00006000U
+#define DMA_SxCR_MSIZE_0 0x00002000U
+#define DMA_SxCR_MSIZE_1 0x00004000U
+#define DMA_SxCR_PSIZE 0x00001800U
+#define DMA_SxCR_PSIZE_0 0x00000800U
+#define DMA_SxCR_PSIZE_1 0x00001000U
+#define DMA_SxCR_MINC 0x00000400U
+#define DMA_SxCR_PINC 0x00000200U
+#define DMA_SxCR_CIRC 0x00000100U
+#define DMA_SxCR_DIR 0x000000C0U
+#define DMA_SxCR_DIR_0 0x00000040U
+#define DMA_SxCR_DIR_1 0x00000080U
+#define DMA_SxCR_PFCTRL 0x00000020U
+#define DMA_SxCR_TCIE 0x00000010U
+#define DMA_SxCR_HTIE 0x00000008U
+#define DMA_SxCR_TEIE 0x00000004U
+#define DMA_SxCR_DMEIE 0x00000002U
+#define DMA_SxCR_EN 0x00000001U
+
+/* Legacy defines */
+#define DMA_SxCR_ACK 0x00100000U
+
+/******************** Bits definition for DMA_SxCNDTR register **************/
+#define DMA_SxNDT 0x0000FFFFU
+#define DMA_SxNDT_0 0x00000001U
+#define DMA_SxNDT_1 0x00000002U
+#define DMA_SxNDT_2 0x00000004U
+#define DMA_SxNDT_3 0x00000008U
+#define DMA_SxNDT_4 0x00000010U
+#define DMA_SxNDT_5 0x00000020U
+#define DMA_SxNDT_6 0x00000040U
+#define DMA_SxNDT_7 0x00000080U
+#define DMA_SxNDT_8 0x00000100U
+#define DMA_SxNDT_9 0x00000200U
+#define DMA_SxNDT_10 0x00000400U
+#define DMA_SxNDT_11 0x00000800U
+#define DMA_SxNDT_12 0x00001000U
+#define DMA_SxNDT_13 0x00002000U
+#define DMA_SxNDT_14 0x00004000U
+#define DMA_SxNDT_15 0x00008000U
+
+/******************** Bits definition for DMA_SxFCR register ****************/
+#define DMA_SxFCR_FEIE 0x00000080U
+#define DMA_SxFCR_FS 0x00000038U
+#define DMA_SxFCR_FS_0 0x00000008U
+#define DMA_SxFCR_FS_1 0x00000010U
+#define DMA_SxFCR_FS_2 0x00000020U
+#define DMA_SxFCR_DMDIS 0x00000004U
+#define DMA_SxFCR_FTH 0x00000003U
+#define DMA_SxFCR_FTH_0 0x00000001U
+#define DMA_SxFCR_FTH_1 0x00000002U
+
+/******************** Bits definition for DMA_LISR register *****************/
+#define DMA_LISR_TCIF3 0x08000000U
+#define DMA_LISR_HTIF3 0x04000000U
+#define DMA_LISR_TEIF3 0x02000000U
+#define DMA_LISR_DMEIF3 0x01000000U
+#define DMA_LISR_FEIF3 0x00400000U
+#define DMA_LISR_TCIF2 0x00200000U
+#define DMA_LISR_HTIF2 0x00100000U
+#define DMA_LISR_TEIF2 0x00080000U
+#define DMA_LISR_DMEIF2 0x00040000U
+#define DMA_LISR_FEIF2 0x00010000U
+#define DMA_LISR_TCIF1 0x00000800U
+#define DMA_LISR_HTIF1 0x00000400U
+#define DMA_LISR_TEIF1 0x00000200U
+#define DMA_LISR_DMEIF1 0x00000100U
+#define DMA_LISR_FEIF1 0x00000040U
+#define DMA_LISR_TCIF0 0x00000020U
+#define DMA_LISR_HTIF0 0x00000010U
+#define DMA_LISR_TEIF0 0x00000008U
+#define DMA_LISR_DMEIF0 0x00000004U
+#define DMA_LISR_FEIF0 0x00000001U
+
+/******************** Bits definition for DMA_HISR register *****************/
+#define DMA_HISR_TCIF7 0x08000000U
+#define DMA_HISR_HTIF7 0x04000000U
+#define DMA_HISR_TEIF7 0x02000000U
+#define DMA_HISR_DMEIF7 0x01000000U
+#define DMA_HISR_FEIF7 0x00400000U
+#define DMA_HISR_TCIF6 0x00200000U
+#define DMA_HISR_HTIF6 0x00100000U
+#define DMA_HISR_TEIF6 0x00080000U
+#define DMA_HISR_DMEIF6 0x00040000U
+#define DMA_HISR_FEIF6 0x00010000U
+#define DMA_HISR_TCIF5 0x00000800U
+#define DMA_HISR_HTIF5 0x00000400U
+#define DMA_HISR_TEIF5 0x00000200U
+#define DMA_HISR_DMEIF5 0x00000100U
+#define DMA_HISR_FEIF5 0x00000040U
+#define DMA_HISR_TCIF4 0x00000020U
+#define DMA_HISR_HTIF4 0x00000010U
+#define DMA_HISR_TEIF4 0x00000008U
+#define DMA_HISR_DMEIF4 0x00000004U
+#define DMA_HISR_FEIF4 0x00000001U
+
+/******************** Bits definition for DMA_LIFCR register ****************/
+#define DMA_LIFCR_CTCIF3 0x08000000U
+#define DMA_LIFCR_CHTIF3 0x04000000U
+#define DMA_LIFCR_CTEIF3 0x02000000U
+#define DMA_LIFCR_CDMEIF3 0x01000000U
+#define DMA_LIFCR_CFEIF3 0x00400000U
+#define DMA_LIFCR_CTCIF2 0x00200000U
+#define DMA_LIFCR_CHTIF2 0x00100000U
+#define DMA_LIFCR_CTEIF2 0x00080000U
+#define DMA_LIFCR_CDMEIF2 0x00040000U
+#define DMA_LIFCR_CFEIF2 0x00010000U
+#define DMA_LIFCR_CTCIF1 0x00000800U
+#define DMA_LIFCR_CHTIF1 0x00000400U
+#define DMA_LIFCR_CTEIF1 0x00000200U
+#define DMA_LIFCR_CDMEIF1 0x00000100U
+#define DMA_LIFCR_CFEIF1 0x00000040U
+#define DMA_LIFCR_CTCIF0 0x00000020U
+#define DMA_LIFCR_CHTIF0 0x00000010U
+#define DMA_LIFCR_CTEIF0 0x00000008U
+#define DMA_LIFCR_CDMEIF0 0x00000004U
+#define DMA_LIFCR_CFEIF0 0x00000001U
+
+/******************** Bits definition for DMA_HIFCR register ****************/
+#define DMA_HIFCR_CTCIF7 0x08000000U
+#define DMA_HIFCR_CHTIF7 0x04000000U
+#define DMA_HIFCR_CTEIF7 0x02000000U
+#define DMA_HIFCR_CDMEIF7 0x01000000U
+#define DMA_HIFCR_CFEIF7 0x00400000U
+#define DMA_HIFCR_CTCIF6 0x00200000U
+#define DMA_HIFCR_CHTIF6 0x00100000U
+#define DMA_HIFCR_CTEIF6 0x00080000U
+#define DMA_HIFCR_CDMEIF6 0x00040000U
+#define DMA_HIFCR_CFEIF6 0x00010000U
+#define DMA_HIFCR_CTCIF5 0x00000800U
+#define DMA_HIFCR_CHTIF5 0x00000400U
+#define DMA_HIFCR_CTEIF5 0x00000200U
+#define DMA_HIFCR_CDMEIF5 0x00000100U
+#define DMA_HIFCR_CFEIF5 0x00000040U
+#define DMA_HIFCR_CTCIF4 0x00000020U
+#define DMA_HIFCR_CHTIF4 0x00000010U
+#define DMA_HIFCR_CTEIF4 0x00000008U
+#define DMA_HIFCR_CDMEIF4 0x00000004U
+#define DMA_HIFCR_CFEIF4 0x00000001U
+
+
+/******************************************************************************/
+/* */
+/* External Interrupt/Event Controller */
+/* */
+/******************************************************************************/
+/******************* Bit definition for EXTI_IMR register *******************/
+#define EXTI_IMR_MR0 0x00000001U /*!< Interrupt Mask on line 0 */
+#define EXTI_IMR_MR1 0x00000002U /*!< Interrupt Mask on line 1 */
+#define EXTI_IMR_MR2 0x00000004U /*!< Interrupt Mask on line 2 */
+#define EXTI_IMR_MR3 0x00000008U /*!< Interrupt Mask on line 3 */
+#define EXTI_IMR_MR4 0x00000010U /*!< Interrupt Mask on line 4 */
+#define EXTI_IMR_MR5 0x00000020U /*!< Interrupt Mask on line 5 */
+#define EXTI_IMR_MR6 0x00000040U /*!< Interrupt Mask on line 6 */
+#define EXTI_IMR_MR7 0x00000080U /*!< Interrupt Mask on line 7 */
+#define EXTI_IMR_MR8 0x00000100U /*!< Interrupt Mask on line 8 */
+#define EXTI_IMR_MR9 0x00000200U /*!< Interrupt Mask on line 9 */
+#define EXTI_IMR_MR10 0x00000400U /*!< Interrupt Mask on line 10 */
+#define EXTI_IMR_MR11 0x00000800U /*!< Interrupt Mask on line 11 */
+#define EXTI_IMR_MR12 0x00001000U /*!< Interrupt Mask on line 12 */
+#define EXTI_IMR_MR13 0x00002000U /*!< Interrupt Mask on line 13 */
+#define EXTI_IMR_MR14 0x00004000U /*!< Interrupt Mask on line 14 */
+#define EXTI_IMR_MR15 0x00008000U /*!< Interrupt Mask on line 15 */
+#define EXTI_IMR_MR16 0x00010000U /*!< Interrupt Mask on line 16 */
+#define EXTI_IMR_MR17 0x00020000U /*!< Interrupt Mask on line 17 */
+#define EXTI_IMR_MR18 0x00040000U /*!< Interrupt Mask on line 18 */
+#define EXTI_IMR_MR19 0x00080000U /*!< Interrupt Mask on line 19 */
+#define EXTI_IMR_MR20 0x00100000U /*!< Interrupt Mask on line 20 */
+#define EXTI_IMR_MR21 0x00200000U /*!< Interrupt Mask on line 21 */
+#define EXTI_IMR_MR22 0x00400000U /*!< Interrupt Mask on line 22 */
+
+/******************* Bit definition for EXTI_EMR register *******************/
+#define EXTI_EMR_MR0 0x00000001U /*!< Event Mask on line 0 */
+#define EXTI_EMR_MR1 0x00000002U /*!< Event Mask on line 1 */
+#define EXTI_EMR_MR2 0x00000004U /*!< Event Mask on line 2 */
+#define EXTI_EMR_MR3 0x00000008U /*!< Event Mask on line 3 */
+#define EXTI_EMR_MR4 0x00000010U /*!< Event Mask on line 4 */
+#define EXTI_EMR_MR5 0x00000020U /*!< Event Mask on line 5 */
+#define EXTI_EMR_MR6 0x00000040U /*!< Event Mask on line 6 */
+#define EXTI_EMR_MR7 0x00000080U /*!< Event Mask on line 7 */
+#define EXTI_EMR_MR8 0x00000100U /*!< Event Mask on line 8 */
+#define EXTI_EMR_MR9 0x00000200U /*!< Event Mask on line 9 */
+#define EXTI_EMR_MR10 0x00000400U /*!< Event Mask on line 10 */
+#define EXTI_EMR_MR11 0x00000800U /*!< Event Mask on line 11 */
+#define EXTI_EMR_MR12 0x00001000U /*!< Event Mask on line 12 */
+#define EXTI_EMR_MR13 0x00002000U /*!< Event Mask on line 13 */
+#define EXTI_EMR_MR14 0x00004000U /*!< Event Mask on line 14 */
+#define EXTI_EMR_MR15 0x00008000U /*!< Event Mask on line 15 */
+#define EXTI_EMR_MR16 0x00010000U /*!< Event Mask on line 16 */
+#define EXTI_EMR_MR17 0x00020000U /*!< Event Mask on line 17 */
+#define EXTI_EMR_MR18 0x00040000U /*!< Event Mask on line 18 */
+#define EXTI_EMR_MR19 0x00080000U /*!< Event Mask on line 19 */
+#define EXTI_EMR_MR20 0x00100000U /*!< Event Mask on line 20 */
+#define EXTI_EMR_MR21 0x00200000U /*!< Event Mask on line 21 */
+#define EXTI_EMR_MR22 0x00400000U /*!< Event Mask on line 22 */
+
+/****************** Bit definition for EXTI_RTSR register *******************/
+#define EXTI_RTSR_TR0 0x00000001U /*!< Rising trigger event configuration bit of line 0 */
+#define EXTI_RTSR_TR1 0x00000002U /*!< Rising trigger event configuration bit of line 1 */
+#define EXTI_RTSR_TR2 0x00000004U /*!< Rising trigger event configuration bit of line 2 */
+#define EXTI_RTSR_TR3 0x00000008U /*!< Rising trigger event configuration bit of line 3 */
+#define EXTI_RTSR_TR4 0x00000010U /*!< Rising trigger event configuration bit of line 4 */
+#define EXTI_RTSR_TR5 0x00000020U /*!< Rising trigger event configuration bit of line 5 */
+#define EXTI_RTSR_TR6 0x00000040U /*!< Rising trigger event configuration bit of line 6 */
+#define EXTI_RTSR_TR7 0x00000080U /*!< Rising trigger event configuration bit of line 7 */
+#define EXTI_RTSR_TR8 0x00000100U /*!< Rising trigger event configuration bit of line 8 */
+#define EXTI_RTSR_TR9 0x00000200U /*!< Rising trigger event configuration bit of line 9 */
+#define EXTI_RTSR_TR10 0x00000400U /*!< Rising trigger event configuration bit of line 10 */
+#define EXTI_RTSR_TR11 0x00000800U /*!< Rising trigger event configuration bit of line 11 */
+#define EXTI_RTSR_TR12 0x00001000U /*!< Rising trigger event configuration bit of line 12 */
+#define EXTI_RTSR_TR13 0x00002000U /*!< Rising trigger event configuration bit of line 13 */
+#define EXTI_RTSR_TR14 0x00004000U /*!< Rising trigger event configuration bit of line 14 */
+#define EXTI_RTSR_TR15 0x00008000U /*!< Rising trigger event configuration bit of line 15 */
+#define EXTI_RTSR_TR16 0x00010000U /*!< Rising trigger event configuration bit of line 16 */
+#define EXTI_RTSR_TR17 0x00020000U /*!< Rising trigger event configuration bit of line 17 */
+#define EXTI_RTSR_TR18 0x00040000U /*!< Rising trigger event configuration bit of line 18 */
+#define EXTI_RTSR_TR19 0x00080000U /*!< Rising trigger event configuration bit of line 19 */
+#define EXTI_RTSR_TR20 0x00100000U /*!< Rising trigger event configuration bit of line 20 */
+#define EXTI_RTSR_TR21 0x00200000U /*!< Rising trigger event configuration bit of line 21 */
+#define EXTI_RTSR_TR22 0x00400000U /*!< Rising trigger event configuration bit of line 22 */
+
+/****************** Bit definition for EXTI_FTSR register *******************/
+#define EXTI_FTSR_TR0 0x00000001U /*!< Falling trigger event configuration bit of line 0 */
+#define EXTI_FTSR_TR1 0x00000002U /*!< Falling trigger event configuration bit of line 1 */
+#define EXTI_FTSR_TR2 0x00000004U /*!< Falling trigger event configuration bit of line 2 */
+#define EXTI_FTSR_TR3 0x00000008U /*!< Falling trigger event configuration bit of line 3 */
+#define EXTI_FTSR_TR4 0x00000010U /*!< Falling trigger event configuration bit of line 4 */
+#define EXTI_FTSR_TR5 0x00000020U /*!< Falling trigger event configuration bit of line 5 */
+#define EXTI_FTSR_TR6 0x00000040U /*!< Falling trigger event configuration bit of line 6 */
+#define EXTI_FTSR_TR7 0x00000080U /*!< Falling trigger event configuration bit of line 7 */
+#define EXTI_FTSR_TR8 0x00000100U /*!< Falling trigger event configuration bit of line 8 */
+#define EXTI_FTSR_TR9 0x00000200U /*!< Falling trigger event configuration bit of line 9 */
+#define EXTI_FTSR_TR10 0x00000400U /*!< Falling trigger event configuration bit of line 10 */
+#define EXTI_FTSR_TR11 0x00000800U /*!< Falling trigger event configuration bit of line 11 */
+#define EXTI_FTSR_TR12 0x00001000U /*!< Falling trigger event configuration bit of line 12 */
+#define EXTI_FTSR_TR13 0x00002000U /*!< Falling trigger event configuration bit of line 13 */
+#define EXTI_FTSR_TR14 0x00004000U /*!< Falling trigger event configuration bit of line 14 */
+#define EXTI_FTSR_TR15 0x00008000U /*!< Falling trigger event configuration bit of line 15 */
+#define EXTI_FTSR_TR16 0x00010000U /*!< Falling trigger event configuration bit of line 16 */
+#define EXTI_FTSR_TR17 0x00020000U /*!< Falling trigger event configuration bit of line 17 */
+#define EXTI_FTSR_TR18 0x00040000U /*!< Falling trigger event configuration bit of line 18 */
+#define EXTI_FTSR_TR19 0x00080000U /*!< Falling trigger event configuration bit of line 19 */
+#define EXTI_FTSR_TR20 0x00100000U /*!< Falling trigger event configuration bit of line 20 */
+#define EXTI_FTSR_TR21 0x00200000U /*!< Falling trigger event configuration bit of line 21 */
+#define EXTI_FTSR_TR22 0x00400000U /*!< Falling trigger event configuration bit of line 22 */
+
+/****************** Bit definition for EXTI_SWIER register ******************/
+#define EXTI_SWIER_SWIER0 0x00000001U /*!< Software Interrupt on line 0 */
+#define EXTI_SWIER_SWIER1 0x00000002U /*!< Software Interrupt on line 1 */
+#define EXTI_SWIER_SWIER2 0x00000004U /*!< Software Interrupt on line 2 */
+#define EXTI_SWIER_SWIER3 0x00000008U /*!< Software Interrupt on line 3 */
+#define EXTI_SWIER_SWIER4 0x00000010U /*!< Software Interrupt on line 4 */
+#define EXTI_SWIER_SWIER5 0x00000020U /*!< Software Interrupt on line 5 */
+#define EXTI_SWIER_SWIER6 0x00000040U /*!< Software Interrupt on line 6 */
+#define EXTI_SWIER_SWIER7 0x00000080U /*!< Software Interrupt on line 7 */
+#define EXTI_SWIER_SWIER8 0x00000100U /*!< Software Interrupt on line 8 */
+#define EXTI_SWIER_SWIER9 0x00000200U /*!< Software Interrupt on line 9 */
+#define EXTI_SWIER_SWIER10 0x00000400U /*!< Software Interrupt on line 10 */
+#define EXTI_SWIER_SWIER11 0x00000800U /*!< Software Interrupt on line 11 */
+#define EXTI_SWIER_SWIER12 0x00001000U /*!< Software Interrupt on line 12 */
+#define EXTI_SWIER_SWIER13 0x00002000U /*!< Software Interrupt on line 13 */
+#define EXTI_SWIER_SWIER14 0x00004000U /*!< Software Interrupt on line 14 */
+#define EXTI_SWIER_SWIER15 0x00008000U /*!< Software Interrupt on line 15 */
+#define EXTI_SWIER_SWIER16 0x00010000U /*!< Software Interrupt on line 16 */
+#define EXTI_SWIER_SWIER17 0x00020000U /*!< Software Interrupt on line 17 */
+#define EXTI_SWIER_SWIER18 0x00040000U /*!< Software Interrupt on line 18 */
+#define EXTI_SWIER_SWIER19 0x00080000U /*!< Software Interrupt on line 19 */
+#define EXTI_SWIER_SWIER20 0x00100000U /*!< Software Interrupt on line 20 */
+#define EXTI_SWIER_SWIER21 0x00200000U /*!< Software Interrupt on line 21 */
+#define EXTI_SWIER_SWIER22 0x00400000U /*!< Software Interrupt on line 22 */
+
+/******************* Bit definition for EXTI_PR register ********************/
+#define EXTI_PR_PR0 0x00000001U /*!< Pending bit for line 0 */
+#define EXTI_PR_PR1 0x00000002U /*!< Pending bit for line 1 */
+#define EXTI_PR_PR2 0x00000004U /*!< Pending bit for line 2 */
+#define EXTI_PR_PR3 0x00000008U /*!< Pending bit for line 3 */
+#define EXTI_PR_PR4 0x00000010U /*!< Pending bit for line 4 */
+#define EXTI_PR_PR5 0x00000020U /*!< Pending bit for line 5 */
+#define EXTI_PR_PR6 0x00000040U /*!< Pending bit for line 6 */
+#define EXTI_PR_PR7 0x00000080U /*!< Pending bit for line 7 */
+#define EXTI_PR_PR8 0x00000100U /*!< Pending bit for line 8 */
+#define EXTI_PR_PR9 0x00000200U /*!< Pending bit for line 9 */
+#define EXTI_PR_PR10 0x00000400U /*!< Pending bit for line 10 */
+#define EXTI_PR_PR11 0x00000800U /*!< Pending bit for line 11 */
+#define EXTI_PR_PR12 0x00001000U /*!< Pending bit for line 12 */
+#define EXTI_PR_PR13 0x00002000U /*!< Pending bit for line 13 */
+#define EXTI_PR_PR14 0x00004000U /*!< Pending bit for line 14 */
+#define EXTI_PR_PR15 0x00008000U /*!< Pending bit for line 15 */
+#define EXTI_PR_PR16 0x00010000U /*!< Pending bit for line 16 */
+#define EXTI_PR_PR17 0x00020000U /*!< Pending bit for line 17 */
+#define EXTI_PR_PR18 0x00040000U /*!< Pending bit for line 18 */
+#define EXTI_PR_PR19 0x00080000U /*!< Pending bit for line 19 */
+#define EXTI_PR_PR20 0x00100000U /*!< Pending bit for line 20 */
+#define EXTI_PR_PR21 0x00200000U /*!< Pending bit for line 21 */
+#define EXTI_PR_PR22 0x00400000U /*!< Pending bit for line 22 */
+
+/******************************************************************************/
+/* */
+/* FLASH */
+/* */
+/******************************************************************************/
+/******************* Bits definition for FLASH_ACR register *****************/
+#define FLASH_ACR_LATENCY 0x0000000FU
+#define FLASH_ACR_LATENCY_0WS 0x00000000U
+#define FLASH_ACR_LATENCY_1WS 0x00000001U
+#define FLASH_ACR_LATENCY_2WS 0x00000002U
+#define FLASH_ACR_LATENCY_3WS 0x00000003U
+#define FLASH_ACR_LATENCY_4WS 0x00000004U
+#define FLASH_ACR_LATENCY_5WS 0x00000005U
+#define FLASH_ACR_LATENCY_6WS 0x00000006U
+#define FLASH_ACR_LATENCY_7WS 0x00000007U
+
+#define FLASH_ACR_PRFTEN 0x00000100U
+#define FLASH_ACR_ICEN 0x00000200U
+#define FLASH_ACR_DCEN 0x00000400U
+#define FLASH_ACR_ICRST 0x00000800U
+#define FLASH_ACR_DCRST 0x00001000U
+#define FLASH_ACR_BYTE0_ADDRESS 0x40023C00U
+#define FLASH_ACR_BYTE2_ADDRESS 0x40023C03U
+
+/******************* Bits definition for FLASH_SR register ******************/
+#define FLASH_SR_EOP 0x00000001U
+#define FLASH_SR_SOP 0x00000002U
+#define FLASH_SR_WRPERR 0x00000010U
+#define FLASH_SR_PGAERR 0x00000020U
+#define FLASH_SR_PGPERR 0x00000040U
+#define FLASH_SR_PGSERR 0x00000080U
+#define FLASH_SR_BSY 0x00010000U
+
+/******************* Bits definition for FLASH_CR register ******************/
+#define FLASH_CR_PG 0x00000001U
+#define FLASH_CR_SER 0x00000002U
+#define FLASH_CR_MER 0x00000004U
+#define FLASH_CR_SNB 0x000000F8U
+#define FLASH_CR_SNB_0 0x00000008U
+#define FLASH_CR_SNB_1 0x00000010U
+#define FLASH_CR_SNB_2 0x00000020U
+#define FLASH_CR_SNB_3 0x00000040U
+#define FLASH_CR_SNB_4 0x00000080U
+#define FLASH_CR_PSIZE 0x00000300U
+#define FLASH_CR_PSIZE_0 0x00000100U
+#define FLASH_CR_PSIZE_1 0x00000200U
+#define FLASH_CR_STRT 0x00010000U
+#define FLASH_CR_EOPIE 0x01000000U
+#define FLASH_CR_LOCK 0x80000000U
+
+/******************* Bits definition for FLASH_OPTCR register ***************/
+#define FLASH_OPTCR_OPTLOCK 0x00000001U
+#define FLASH_OPTCR_OPTSTRT 0x00000002U
+#define FLASH_OPTCR_BOR_LEV_0 0x00000004U
+#define FLASH_OPTCR_BOR_LEV_1 0x00000008U
+#define FLASH_OPTCR_BOR_LEV 0x0000000CU
+
+#define FLASH_OPTCR_WDG_SW 0x00000020U
+#define FLASH_OPTCR_nRST_STOP 0x00000040U
+#define FLASH_OPTCR_nRST_STDBY 0x00000080U
+#define FLASH_OPTCR_RDP 0x0000FF00U
+#define FLASH_OPTCR_RDP_0 0x00000100U
+#define FLASH_OPTCR_RDP_1 0x00000200U
+#define FLASH_OPTCR_RDP_2 0x00000400U
+#define FLASH_OPTCR_RDP_3 0x00000800U
+#define FLASH_OPTCR_RDP_4 0x00001000U
+#define FLASH_OPTCR_RDP_5 0x00002000U
+#define FLASH_OPTCR_RDP_6 0x00004000U
+#define FLASH_OPTCR_RDP_7 0x00008000U
+#define FLASH_OPTCR_nWRP 0x0FFF0000U
+#define FLASH_OPTCR_nWRP_0 0x00010000U
+#define FLASH_OPTCR_nWRP_1 0x00020000U
+#define FLASH_OPTCR_nWRP_2 0x00040000U
+#define FLASH_OPTCR_nWRP_3 0x00080000U
+#define FLASH_OPTCR_nWRP_4 0x00100000U
+#define FLASH_OPTCR_nWRP_5 0x00200000U
+#define FLASH_OPTCR_nWRP_6 0x00400000U
+#define FLASH_OPTCR_nWRP_7 0x00800000U
+#define FLASH_OPTCR_nWRP_8 0x01000000U
+#define FLASH_OPTCR_nWRP_9 0x02000000U
+#define FLASH_OPTCR_nWRP_10 0x04000000U
+#define FLASH_OPTCR_nWRP_11 0x08000000U
+
+/****************** Bits definition for FLASH_OPTCR1 register ***************/
+#define FLASH_OPTCR1_nWRP 0x0FFF0000U
+#define FLASH_OPTCR1_nWRP_0 0x00010000U
+#define FLASH_OPTCR1_nWRP_1 0x00020000U
+#define FLASH_OPTCR1_nWRP_2 0x00040000U
+#define FLASH_OPTCR1_nWRP_3 0x00080000U
+#define FLASH_OPTCR1_nWRP_4 0x00100000U
+#define FLASH_OPTCR1_nWRP_5 0x00200000U
+#define FLASH_OPTCR1_nWRP_6 0x00400000U
+#define FLASH_OPTCR1_nWRP_7 0x00800000U
+#define FLASH_OPTCR1_nWRP_8 0x01000000U
+#define FLASH_OPTCR1_nWRP_9 0x02000000U
+#define FLASH_OPTCR1_nWRP_10 0x04000000U
+#define FLASH_OPTCR1_nWRP_11 0x08000000U
+
+/******************************************************************************/
+/* */
+/* Flexible Static Memory Controller */
+/* */
+/******************************************************************************/
+/****************** Bit definition for FSMC_BCR1 register *******************/
+#define FSMC_BCR1_MBKEN 0x00000001U /*!<Memory bank enable bit */
+#define FSMC_BCR1_MUXEN 0x00000002U /*!<Address/data multiplexing enable bit */
+
+#define FSMC_BCR1_MTYP 0x0000000CU /*!<MTYP[1:0] bits (Memory type) */
+#define FSMC_BCR1_MTYP_0 0x00000004U /*!<Bit 0 */
+#define FSMC_BCR1_MTYP_1 0x00000008U /*!<Bit 1 */
+
+#define FSMC_BCR1_MWID 0x00000030U /*!<MWID[1:0] bits (Memory data bus width) */
+#define FSMC_BCR1_MWID_0 0x00000010U /*!<Bit 0 */
+#define FSMC_BCR1_MWID_1 0x00000020U /*!<Bit 1 */
+
+#define FSMC_BCR1_FACCEN 0x00000040U /*!<Flash access enable */
+#define FSMC_BCR1_BURSTEN 0x00000100U /*!<Burst enable bit */
+#define FSMC_BCR1_WAITPOL 0x00000200U /*!<Wait signal polarity bit */
+#define FSMC_BCR1_WRAPMOD 0x00000400U /*!<Wrapped burst mode support */
+#define FSMC_BCR1_WAITCFG 0x00000800U /*!<Wait timing configuration */
+#define FSMC_BCR1_WREN 0x00001000U /*!<Write enable bit */
+#define FSMC_BCR1_WAITEN 0x00002000U /*!<Wait enable bit */
+#define FSMC_BCR1_EXTMOD 0x00004000U /*!<Extended mode enable */
+#define FSMC_BCR1_ASYNCWAIT 0x00008000U /*!<Asynchronous wait */
+#define FSMC_BCR1_CPSIZE 0x00070000U /*!<CRAM page size */
+#define FSMC_BCR1_CPSIZE_0 0x00010000U /*!<Bit 0 */
+#define FSMC_BCR1_CPSIZE_1 0x00020000U /*!<Bit 1 */
+#define FSMC_BCR1_CPSIZE_2 0x00040000U /*!<Bit 2 */
+#define FSMC_BCR1_CBURSTRW 0x00080000U /*!<Write burst enable */
+
+/****************** Bit definition for FSMC_BCR2 register *******************/
+#define FSMC_BCR2_MBKEN 0x00000001U /*!<Memory bank enable bit */
+#define FSMC_BCR2_MUXEN 0x00000002U /*!<Address/data multiplexing enable bit */
+
+#define FSMC_BCR2_MTYP 0x0000000CU /*!<MTYP[1:0] bits (Memory type) */
+#define FSMC_BCR2_MTYP_0 0x00000004U /*!<Bit 0 */
+#define FSMC_BCR2_MTYP_1 0x00000008U /*!<Bit 1 */
+
+#define FSMC_BCR2_MWID 0x00000030U /*!<MWID[1:0] bits (Memory data bus width) */
+#define FSMC_BCR2_MWID_0 0x00000010U /*!<Bit 0 */
+#define FSMC_BCR2_MWID_1 0x00000020U /*!<Bit 1 */
+
+#define FSMC_BCR2_FACCEN 0x00000040U /*!<Flash access enable */
+#define FSMC_BCR2_BURSTEN 0x00000100U /*!<Burst enable bit */
+#define FSMC_BCR2_WAITPOL 0x00000200U /*!<Wait signal polarity bit */
+#define FSMC_BCR2_WRAPMOD 0x00000400U /*!<Wrapped burst mode support */
+#define FSMC_BCR2_WAITCFG 0x00000800U /*!<Wait timing configuration */
+#define FSMC_BCR2_WREN 0x00001000U /*!<Write enable bit */
+#define FSMC_BCR2_WAITEN 0x00002000U /*!<Wait enable bit */
+#define FSMC_BCR2_EXTMOD 0x00004000U /*!<Extended mode enable */
+#define FSMC_BCR2_ASYNCWAIT 0x00008000U /*!<Asynchronous wait */
+#define FSMC_BCR2_CPSIZE 0x00070000U /*!<CRAM page size */
+#define FSMC_BCR2_CPSIZE_0 0x00010000U /*!<Bit 0 */
+#define FSMC_BCR2_CPSIZE_1 0x00020000U /*!<Bit 1 */
+#define FSMC_BCR2_CPSIZE_2 0x00040000U /*!<Bit 2 */
+#define FSMC_BCR2_CBURSTRW 0x00080000U /*!<Write burst enable */
+
+/****************** Bit definition for FSMC_BCR3 register *******************/
+#define FSMC_BCR3_MBKEN 0x00000001U /*!<Memory bank enable bit */
+#define FSMC_BCR3_MUXEN 0x00000002U /*!<Address/data multiplexing enable bit */
+
+#define FSMC_BCR3_MTYP 0x0000000CU /*!<MTYP[1:0] bits (Memory type) */
+#define FSMC_BCR3_MTYP_0 0x00000004U /*!<Bit 0 */
+#define FSMC_BCR3_MTYP_1 0x00000008U /*!<Bit 1 */
+
+#define FSMC_BCR3_MWID 0x00000030U /*!<MWID[1:0] bits (Memory data bus width) */
+#define FSMC_BCR3_MWID_0 0x00000010U /*!<Bit 0 */
+#define FSMC_BCR3_MWID_1 0x00000020U /*!<Bit 1 */
+
+#define FSMC_BCR3_FACCEN 0x00000040U /*!<Flash access enable */
+#define FSMC_BCR3_BURSTEN 0x00000100U /*!<Burst enable bit */
+#define FSMC_BCR3_WAITPOL 0x00000200U /*!<Wait signal polarity bit */
+#define FSMC_BCR3_WRAPMOD 0x00000400U /*!<Wrapped burst mode support */
+#define FSMC_BCR3_WAITCFG 0x00000800U /*!<Wait timing configuration */
+#define FSMC_BCR3_WREN 0x00001000U /*!<Write enable bit */
+#define FSMC_BCR3_WAITEN 0x00002000U /*!<Wait enable bit */
+#define FSMC_BCR3_EXTMOD 0x00004000U /*!<Extended mode enable */
+#define FSMC_BCR3_ASYNCWAIT 0x00008000U /*!<Asynchronous wait */
+#define FSMC_BCR3_CPSIZE 0x00070000U /*!<CRAM page size */
+#define FSMC_BCR3_CPSIZE_0 0x00010000U /*!<Bit 0 */
+#define FSMC_BCR3_CPSIZE_1 0x00020000U /*!<Bit 1 */
+#define FSMC_BCR3_CPSIZE_2 0x00040000U /*!<Bit 2 */
+#define FSMC_BCR3_CBURSTRW 0x00080000U /*!<Write burst enable */
+
+/****************** Bit definition for FSMC_BCR4 register *******************/
+#define FSMC_BCR4_MBKEN 0x00000001U /*!<Memory bank enable bit */
+#define FSMC_BCR4_MUXEN 0x00000002U /*!<Address/data multiplexing enable bit */
+
+#define FSMC_BCR4_MTYP 0x0000000CU /*!<MTYP[1:0] bits (Memory type) */
+#define FSMC_BCR4_MTYP_0 0x00000004U /*!<Bit 0 */
+#define FSMC_BCR4_MTYP_1 0x00000008U /*!<Bit 1 */
+
+#define FSMC_BCR4_MWID 0x00000030U /*!<MWID[1:0] bits (Memory data bus width) */
+#define FSMC_BCR4_MWID_0 0x00000010U /*!<Bit 0 */
+#define FSMC_BCR4_MWID_1 0x00000020U /*!<Bit 1 */
+
+#define FSMC_BCR4_FACCEN 0x00000040U /*!<Flash access enable */
+#define FSMC_BCR4_BURSTEN 0x00000100U /*!<Burst enable bit */
+#define FSMC_BCR4_WAITPOL 0x00000200U /*!<Wait signal polarity bit */
+#define FSMC_BCR4_WRAPMOD 0x00000400U /*!<Wrapped burst mode support */
+#define FSMC_BCR4_WAITCFG 0x00000800U /*!<Wait timing configuration */
+#define FSMC_BCR4_WREN 0x00001000U /*!<Write enable bit */
+#define FSMC_BCR4_WAITEN 0x00002000U /*!<Wait enable bit */
+#define FSMC_BCR4_EXTMOD 0x00004000U /*!<Extended mode enable */
+#define FSMC_BCR4_ASYNCWAIT 0x00008000U /*!<Asynchronous wait */
+#define FSMC_BCR4_CPSIZE 0x00070000U /*!<CRAM page size */
+#define FSMC_BCR4_CPSIZE_0 0x00010000U /*!<Bit 0 */
+#define FSMC_BCR4_CPSIZE_1 0x00020000U /*!<Bit 1 */
+#define FSMC_BCR4_CPSIZE_2 0x00040000U /*!<Bit 2 */
+#define FSMC_BCR4_CBURSTRW 0x00080000U /*!<Write burst enable */
+
+/****************** Bit definition for FSMC_BTR1 register ******************/
+#define FSMC_BTR1_ADDSET 0x0000000FU /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FSMC_BTR1_ADDSET_0 0x00000001U /*!<Bit 0 */
+#define FSMC_BTR1_ADDSET_1 0x00000002U /*!<Bit 1 */
+#define FSMC_BTR1_ADDSET_2 0x00000004U /*!<Bit 2 */
+#define FSMC_BTR1_ADDSET_3 0x00000008U /*!<Bit 3 */
+
+#define FSMC_BTR1_ADDHLD 0x000000F0U /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FSMC_BTR1_ADDHLD_0 0x00000010U /*!<Bit 0 */
+#define FSMC_BTR1_ADDHLD_1 0x00000020U /*!<Bit 1 */
+#define FSMC_BTR1_ADDHLD_2 0x00000040U /*!<Bit 2 */
+#define FSMC_BTR1_ADDHLD_3 0x00000080U /*!<Bit 3 */
+
+#define FSMC_BTR1_DATAST 0x0000FF00U /*!<DATAST [7:0] bits (Data-phase duration) */
+#define FSMC_BTR1_DATAST_0 0x00000100U /*!<Bit 0 */
+#define FSMC_BTR1_DATAST_1 0x00000200U /*!<Bit 1 */
+#define FSMC_BTR1_DATAST_2 0x00000400U /*!<Bit 2 */
+#define FSMC_BTR1_DATAST_3 0x00000800U /*!<Bit 3 */
+#define FSMC_BTR1_DATAST_4 0x00001000U /*!<Bit 4 */
+#define FSMC_BTR1_DATAST_5 0x00002000U /*!<Bit 5 */
+#define FSMC_BTR1_DATAST_6 0x00004000U /*!<Bit 6 */
+#define FSMC_BTR1_DATAST_7 0x00008000U /*!<Bit 7 */
+
+#define FSMC_BTR1_BUSTURN 0x000F0000U /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define FSMC_BTR1_BUSTURN_0 0x00010000U /*!<Bit 0 */
+#define FSMC_BTR1_BUSTURN_1 0x00020000U /*!<Bit 1 */
+#define FSMC_BTR1_BUSTURN_2 0x00040000U /*!<Bit 2 */
+#define FSMC_BTR1_BUSTURN_3 0x00080000U /*!<Bit 3 */
+
+#define FSMC_BTR1_CLKDIV 0x00F00000U /*!<CLKDIV[3:0] bits (Clock divide ratio) */
+#define FSMC_BTR1_CLKDIV_0 0x00100000U /*!<Bit 0 */
+#define FSMC_BTR1_CLKDIV_1 0x00200000U /*!<Bit 1 */
+#define FSMC_BTR1_CLKDIV_2 0x00400000U /*!<Bit 2 */
+#define FSMC_BTR1_CLKDIV_3 0x00800000U /*!<Bit 3 */
+
+#define FSMC_BTR1_DATLAT 0x0F000000U /*!<DATLA[3:0] bits (Data latency) */
+#define FSMC_BTR1_DATLAT_0 0x01000000U /*!<Bit 0 */
+#define FSMC_BTR1_DATLAT_1 0x02000000U /*!<Bit 1 */
+#define FSMC_BTR1_DATLAT_2 0x04000000U /*!<Bit 2 */
+#define FSMC_BTR1_DATLAT_3 0x08000000U /*!<Bit 3 */
+
+#define FSMC_BTR1_ACCMOD 0x30000000U /*!<ACCMOD[1:0] bits (Access mode) */
+#define FSMC_BTR1_ACCMOD_0 0x10000000U /*!<Bit 0 */
+#define FSMC_BTR1_ACCMOD_1 0x20000000U /*!<Bit 1 */
+
+/****************** Bit definition for FSMC_BTR2 register *******************/
+#define FSMC_BTR2_ADDSET 0x0000000FU /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FSMC_BTR2_ADDSET_0 0x00000001U /*!<Bit 0 */
+#define FSMC_BTR2_ADDSET_1 0x00000002U /*!<Bit 1 */
+#define FSMC_BTR2_ADDSET_2 0x00000004U /*!<Bit 2 */
+#define FSMC_BTR2_ADDSET_3 0x00000008U /*!<Bit 3 */
+
+#define FSMC_BTR2_ADDHLD 0x000000F0U /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FSMC_BTR2_ADDHLD_0 0x00000010U /*!<Bit 0 */
+#define FSMC_BTR2_ADDHLD_1 0x00000020U /*!<Bit 1 */
+#define FSMC_BTR2_ADDHLD_2 0x00000040U /*!<Bit 2 */
+#define FSMC_BTR2_ADDHLD_3 0x00000080U /*!<Bit 3 */
+
+#define FSMC_BTR2_DATAST 0x0000FF00U /*!<DATAST [7:0] bits (Data-phase duration) */
+#define FSMC_BTR2_DATAST_0 0x00000100U /*!<Bit 0 */
+#define FSMC_BTR2_DATAST_1 0x00000200U /*!<Bit 1 */
+#define FSMC_BTR2_DATAST_2 0x00000400U /*!<Bit 2 */
+#define FSMC_BTR2_DATAST_3 0x00000800U /*!<Bit 3 */
+#define FSMC_BTR2_DATAST_4 0x00001000U /*!<Bit 4 */
+#define FSMC_BTR2_DATAST_5 0x00002000U /*!<Bit 5 */
+#define FSMC_BTR2_DATAST_6 0x00004000U /*!<Bit 6 */
+#define FSMC_BTR2_DATAST_7 0x00008000U /*!<Bit 7 */
+
+#define FSMC_BTR2_BUSTURN 0x000F0000U /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define FSMC_BTR2_BUSTURN_0 0x00010000U /*!<Bit 0 */
+#define FSMC_BTR2_BUSTURN_1 0x00020000U /*!<Bit 1 */
+#define FSMC_BTR2_BUSTURN_2 0x00040000U /*!<Bit 2 */
+#define FSMC_BTR2_BUSTURN_3 0x00080000U /*!<Bit 3 */
+
+#define FSMC_BTR2_CLKDIV 0x00F00000U /*!<CLKDIV[3:0] bits (Clock divide ratio) */
+#define FSMC_BTR2_CLKDIV_0 0x00100000U /*!<Bit 0 */
+#define FSMC_BTR2_CLKDIV_1 0x00200000U /*!<Bit 1 */
+#define FSMC_BTR2_CLKDIV_2 0x00400000U /*!<Bit 2 */
+#define FSMC_BTR2_CLKDIV_3 0x00800000U /*!<Bit 3 */
+
+#define FSMC_BTR2_DATLAT 0x0F000000U /*!<DATLA[3:0] bits (Data latency) */
+#define FSMC_BTR2_DATLAT_0 0x01000000U /*!<Bit 0 */
+#define FSMC_BTR2_DATLAT_1 0x02000000U /*!<Bit 1 */
+#define FSMC_BTR2_DATLAT_2 0x04000000U /*!<Bit 2 */
+#define FSMC_BTR2_DATLAT_3 0x08000000U /*!<Bit 3 */
+
+#define FSMC_BTR2_ACCMOD 0x30000000U /*!<ACCMOD[1:0] bits (Access mode) */
+#define FSMC_BTR2_ACCMOD_0 0x10000000U /*!<Bit 0 */
+#define FSMC_BTR2_ACCMOD_1 0x20000000U /*!<Bit 1 */
+
+/******************* Bit definition for FSMC_BTR3 register *******************/
+#define FSMC_BTR3_ADDSET 0x0000000FU /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FSMC_BTR3_ADDSET_0 0x00000001U /*!<Bit 0 */
+#define FSMC_BTR3_ADDSET_1 0x00000002U /*!<Bit 1 */
+#define FSMC_BTR3_ADDSET_2 0x00000004U /*!<Bit 2 */
+#define FSMC_BTR3_ADDSET_3 0x00000008U /*!<Bit 3 */
+
+#define FSMC_BTR3_ADDHLD 0x000000F0U /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FSMC_BTR3_ADDHLD_0 0x00000010U /*!<Bit 0 */
+#define FSMC_BTR3_ADDHLD_1 0x00000020U /*!<Bit 1 */
+#define FSMC_BTR3_ADDHLD_2 0x00000040U /*!<Bit 2 */
+#define FSMC_BTR3_ADDHLD_3 0x00000080U /*!<Bit 3 */
+
+#define FSMC_BTR3_DATAST 0x0000FF00U /*!<DATAST [7:0] bits (Data-phase duration) */
+#define FSMC_BTR3_DATAST_0 0x00000100U /*!<Bit 0 */
+#define FSMC_BTR3_DATAST_1 0x00000200U /*!<Bit 1 */
+#define FSMC_BTR3_DATAST_2 0x00000400U /*!<Bit 2 */
+#define FSMC_BTR3_DATAST_3 0x00000800U /*!<Bit 3 */
+#define FSMC_BTR3_DATAST_4 0x00001000U /*!<Bit 4 */
+#define FSMC_BTR3_DATAST_5 0x00002000U /*!<Bit 5 */
+#define FSMC_BTR3_DATAST_6 0x00004000U /*!<Bit 6 */
+#define FSMC_BTR3_DATAST_7 0x00008000U /*!<Bit 7 */
+
+#define FSMC_BTR3_BUSTURN 0x000F0000U /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define FSMC_BTR3_BUSTURN_0 0x00010000U /*!<Bit 0 */
+#define FSMC_BTR3_BUSTURN_1 0x00020000U /*!<Bit 1 */
+#define FSMC_BTR3_BUSTURN_2 0x00040000U /*!<Bit 2 */
+#define FSMC_BTR3_BUSTURN_3 0x00080000U /*!<Bit 3 */
+
+#define FSMC_BTR3_CLKDIV 0x00F00000U /*!<CLKDIV[3:0] bits (Clock divide ratio) */
+#define FSMC_BTR3_CLKDIV_0 0x00100000U /*!<Bit 0 */
+#define FSMC_BTR3_CLKDIV_1 0x00200000U /*!<Bit 1 */
+#define FSMC_BTR3_CLKDIV_2 0x00400000U /*!<Bit 2 */
+#define FSMC_BTR3_CLKDIV_3 0x00800000U /*!<Bit 3 */
+
+#define FSMC_BTR3_DATLAT 0x0F000000U /*!<DATLA[3:0] bits (Data latency) */
+#define FSMC_BTR3_DATLAT_0 0x01000000U /*!<Bit 0 */
+#define FSMC_BTR3_DATLAT_1 0x02000000U /*!<Bit 1 */
+#define FSMC_BTR3_DATLAT_2 0x04000000U /*!<Bit 2 */
+#define FSMC_BTR3_DATLAT_3 0x08000000U /*!<Bit 3 */
+
+#define FSMC_BTR3_ACCMOD 0x30000000U /*!<ACCMOD[1:0] bits (Access mode) */
+#define FSMC_BTR3_ACCMOD_0 0x10000000U /*!<Bit 0 */
+#define FSMC_BTR3_ACCMOD_1 0x20000000U /*!<Bit 1 */
+
+/****************** Bit definition for FSMC_BTR4 register *******************/
+#define FSMC_BTR4_ADDSET 0x0000000FU /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FSMC_BTR4_ADDSET_0 0x00000001U /*!<Bit 0 */
+#define FSMC_BTR4_ADDSET_1 0x00000002U /*!<Bit 1 */
+#define FSMC_BTR4_ADDSET_2 0x00000004U /*!<Bit 2 */
+#define FSMC_BTR4_ADDSET_3 0x00000008U /*!<Bit 3 */
+
+#define FSMC_BTR4_ADDHLD 0x000000F0U /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FSMC_BTR4_ADDHLD_0 0x00000010U /*!<Bit 0 */
+#define FSMC_BTR4_ADDHLD_1 0x00000020U /*!<Bit 1 */
+#define FSMC_BTR4_ADDHLD_2 0x00000040U /*!<Bit 2 */
+#define FSMC_BTR4_ADDHLD_3 0x00000080U /*!<Bit 3 */
+
+#define FSMC_BTR4_DATAST 0x0000FF00U /*!<DATAST [7:0] bits (Data-phase duration) */
+#define FSMC_BTR4_DATAST_0 0x00000100U /*!<Bit 0 */
+#define FSMC_BTR4_DATAST_1 0x00000200U /*!<Bit 1 */
+#define FSMC_BTR4_DATAST_2 0x00000400U /*!<Bit 2 */
+#define FSMC_BTR4_DATAST_3 0x00000800U /*!<Bit 3 */
+#define FSMC_BTR4_DATAST_4 0x00001000U /*!<Bit 4 */
+#define FSMC_BTR4_DATAST_5 0x00002000U /*!<Bit 5 */
+#define FSMC_BTR4_DATAST_6 0x00004000U /*!<Bit 6 */
+#define FSMC_BTR4_DATAST_7 0x00008000U /*!<Bit 7 */
+
+#define FSMC_BTR4_BUSTURN 0x000F0000U /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define FSMC_BTR4_BUSTURN_0 0x00010000U /*!<Bit 0 */
+#define FSMC_BTR4_BUSTURN_1 0x00020000U /*!<Bit 1 */
+#define FSMC_BTR4_BUSTURN_2 0x00040000U /*!<Bit 2 */
+#define FSMC_BTR4_BUSTURN_3 0x00080000U /*!<Bit 3 */
+
+#define FSMC_BTR4_CLKDIV 0x00F00000U /*!<CLKDIV[3:0] bits (Clock divide ratio) */
+#define FSMC_BTR4_CLKDIV_0 0x00100000U /*!<Bit 0 */
+#define FSMC_BTR4_CLKDIV_1 0x00200000U /*!<Bit 1 */
+#define FSMC_BTR4_CLKDIV_2 0x00400000U /*!<Bit 2 */
+#define FSMC_BTR4_CLKDIV_3 0x00800000U /*!<Bit 3 */
+
+#define FSMC_BTR4_DATLAT 0x0F000000U /*!<DATLA[3:0] bits (Data latency) */
+#define FSMC_BTR4_DATLAT_0 0x01000000U /*!<Bit 0 */
+#define FSMC_BTR4_DATLAT_1 0x02000000U /*!<Bit 1 */
+#define FSMC_BTR4_DATLAT_2 0x04000000U /*!<Bit 2 */
+#define FSMC_BTR4_DATLAT_3 0x08000000U /*!<Bit 3 */
+
+#define FSMC_BTR4_ACCMOD 0x30000000U /*!<ACCMOD[1:0] bits (Access mode) */
+#define FSMC_BTR4_ACCMOD_0 0x10000000U /*!<Bit 0 */
+#define FSMC_BTR4_ACCMOD_1 0x20000000U /*!<Bit 1 */
+
+/****************** Bit definition for FSMC_BWTR1 register ******************/
+#define FSMC_BWTR1_ADDSET 0x0000000FU /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FSMC_BWTR1_ADDSET_0 0x00000001U /*!<Bit 0 */
+#define FSMC_BWTR1_ADDSET_1 0x00000002U /*!<Bit 1 */
+#define FSMC_BWTR1_ADDSET_2 0x00000004U /*!<Bit 2 */
+#define FSMC_BWTR1_ADDSET_3 0x00000008U /*!<Bit 3 */
+
+#define FSMC_BWTR1_ADDHLD 0x000000F0U /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FSMC_BWTR1_ADDHLD_0 0x00000010U /*!<Bit 0 */
+#define FSMC_BWTR1_ADDHLD_1 0x00000020U /*!<Bit 1 */
+#define FSMC_BWTR1_ADDHLD_2 0x00000040U /*!<Bit 2 */
+#define FSMC_BWTR1_ADDHLD_3 0x00000080U /*!<Bit 3 */
+
+#define FSMC_BWTR1_DATAST 0x0000FF00U /*!<DATAST [7:0] bits (Data-phase duration) */
+#define FSMC_BWTR1_DATAST_0 0x00000100U /*!<Bit 0 */
+#define FSMC_BWTR1_DATAST_1 0x00000200U /*!<Bit 1 */
+#define FSMC_BWTR1_DATAST_2 0x00000400U /*!<Bit 2 */
+#define FSMC_BWTR1_DATAST_3 0x00000800U /*!<Bit 3 */
+#define FSMC_BWTR1_DATAST_4 0x00001000U /*!<Bit 4 */
+#define FSMC_BWTR1_DATAST_5 0x00002000U /*!<Bit 5 */
+#define FSMC_BWTR1_DATAST_6 0x00004000U /*!<Bit 6 */
+#define FSMC_BWTR1_DATAST_7 0x00008000U /*!<Bit 7 */
+
+#define FSMC_BWTR1_BUSTURN 0x000F0000U /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
+#define FSMC_BWTR1_BUSTURN_0 0x00010000U /*!<Bit 0 */
+#define FSMC_BWTR1_BUSTURN_1 0x00020000U /*!<Bit 1 */
+#define FSMC_BWTR1_BUSTURN_2 0x00040000U /*!<Bit 2 */
+#define FSMC_BWTR1_BUSTURN_3 0x00080000U /*!<Bit 3 */
+
+#define FSMC_BWTR1_ACCMOD 0x30000000U /*!<ACCMOD[1:0] bits (Access mode) */
+#define FSMC_BWTR1_ACCMOD_0 0x10000000U /*!<Bit 0 */
+#define FSMC_BWTR1_ACCMOD_1 0x20000000U /*!<Bit 1 */
+
+/****************** Bit definition for FSMC_BWTR2 register ******************/
+#define FSMC_BWTR2_ADDSET 0x0000000FU /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FSMC_BWTR2_ADDSET_0 0x00000001U /*!<Bit 0 */
+#define FSMC_BWTR2_ADDSET_1 0x00000002U /*!<Bit 1 */
+#define FSMC_BWTR2_ADDSET_2 0x00000004U /*!<Bit 2 */
+#define FSMC_BWTR2_ADDSET_3 0x00000008U /*!<Bit 3 */
+
+#define FSMC_BWTR2_ADDHLD 0x000000F0U /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FSMC_BWTR2_ADDHLD_0 0x00000010U /*!<Bit 0 */
+#define FSMC_BWTR2_ADDHLD_1 0x00000020U /*!<Bit 1 */
+#define FSMC_BWTR2_ADDHLD_2 0x00000040U /*!<Bit 2 */
+#define FSMC_BWTR2_ADDHLD_3 0x00000080U /*!<Bit 3 */
+
+#define FSMC_BWTR2_DATAST 0x0000FF00U /*!<DATAST [7:0] bits (Data-phase duration) */
+#define FSMC_BWTR2_DATAST_0 0x00000100U /*!<Bit 0 */
+#define FSMC_BWTR2_DATAST_1 0x00000200U /*!<Bit 1 */
+#define FSMC_BWTR2_DATAST_2 0x00000400U /*!<Bit 2 */
+#define FSMC_BWTR2_DATAST_3 0x00000800U /*!<Bit 3 */
+#define FSMC_BWTR2_DATAST_4 0x00001000U /*!<Bit 4 */
+#define FSMC_BWTR2_DATAST_5 0x00002000U /*!<Bit 5 */
+#define FSMC_BWTR2_DATAST_6 0x00004000U /*!<Bit 6 */
+#define FSMC_BWTR2_DATAST_7 0x00008000U /*!<Bit 7 */
+
+#define FSMC_BWTR2_BUSTURN 0x000F0000U /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
+#define FSMC_BWTR2_BUSTURN_0 0x00010000U /*!<Bit 0 */
+#define FSMC_BWTR2_BUSTURN_1 0x00020000U /*!<Bit 1 */
+#define FSMC_BWTR2_BUSTURN_2 0x00040000U /*!<Bit 2 */
+#define FSMC_BWTR2_BUSTURN_3 0x00080000U /*!<Bit 3 */
+
+#define FSMC_BWTR2_ACCMOD 0x30000000U /*!<ACCMOD[1:0] bits (Access mode) */
+#define FSMC_BWTR2_ACCMOD_0 0x10000000U /*!<Bit 0 */
+#define FSMC_BWTR2_ACCMOD_1 0x20000000U /*!<Bit 1 */
+
+/****************** Bit definition for FSMC_BWTR3 register ******************/
+#define FSMC_BWTR3_ADDSET 0x0000000FU /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FSMC_BWTR3_ADDSET_0 0x00000001U /*!<Bit 0 */
+#define FSMC_BWTR3_ADDSET_1 0x00000002U /*!<Bit 1 */
+#define FSMC_BWTR3_ADDSET_2 0x00000004U /*!<Bit 2 */
+#define FSMC_BWTR3_ADDSET_3 0x00000008U /*!<Bit 3 */
+
+#define FSMC_BWTR3_ADDHLD 0x000000F0U /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FSMC_BWTR3_ADDHLD_0 0x00000010U /*!<Bit 0 */
+#define FSMC_BWTR3_ADDHLD_1 0x00000020U /*!<Bit 1 */
+#define FSMC_BWTR3_ADDHLD_2 0x00000040U /*!<Bit 2 */
+#define FSMC_BWTR3_ADDHLD_3 0x00000080U /*!<Bit 3 */
+
+#define FSMC_BWTR3_DATAST 0x0000FF00U /*!<DATAST [7:0] bits (Data-phase duration) */
+#define FSMC_BWTR3_DATAST_0 0x00000100U /*!<Bit 0 */
+#define FSMC_BWTR3_DATAST_1 0x00000200U /*!<Bit 1 */
+#define FSMC_BWTR3_DATAST_2 0x00000400U /*!<Bit 2 */
+#define FSMC_BWTR3_DATAST_3 0x00000800U /*!<Bit 3 */
+#define FSMC_BWTR3_DATAST_4 0x00001000U /*!<Bit 4 */
+#define FSMC_BWTR3_DATAST_5 0x00002000U /*!<Bit 5 */
+#define FSMC_BWTR3_DATAST_6 0x00004000U /*!<Bit 6 */
+#define FSMC_BWTR3_DATAST_7 0x00008000U /*!<Bit 7 */
+
+#define FSMC_BWTR3_BUSTURN 0x000F0000U /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
+#define FSMC_BWTR3_BUSTURN_0 0x00010000U /*!<Bit 0 */
+#define FSMC_BWTR3_BUSTURN_1 0x00020000U /*!<Bit 1 */
+#define FSMC_BWTR3_BUSTURN_2 0x00040000U /*!<Bit 2 */
+#define FSMC_BWTR3_BUSTURN_3 0x00080000U /*!<Bit 3 */
+
+#define FSMC_BWTR3_ACCMOD 0x30000000U /*!<ACCMOD[1:0] bits (Access mode) */
+#define FSMC_BWTR3_ACCMOD_0 0x10000000U /*!<Bit 0 */
+#define FSMC_BWTR3_ACCMOD_1 0x20000000U /*!<Bit 1 */
+
+/****************** Bit definition for FSMC_BWTR4 register ******************/
+#define FSMC_BWTR4_ADDSET 0x0000000FU /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FSMC_BWTR4_ADDSET_0 0x00000001U /*!<Bit 0 */
+#define FSMC_BWTR4_ADDSET_1 0x00000002U /*!<Bit 1 */
+#define FSMC_BWTR4_ADDSET_2 0x00000004U /*!<Bit 2 */
+#define FSMC_BWTR4_ADDSET_3 0x00000008U /*!<Bit 3 */
+
+#define FSMC_BWTR4_ADDHLD 0x000000F0U /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FSMC_BWTR4_ADDHLD_0 0x00000010U /*!<Bit 0 */
+#define FSMC_BWTR4_ADDHLD_1 0x00000020U /*!<Bit 1 */
+#define FSMC_BWTR4_ADDHLD_2 0x00000040U /*!<Bit 2 */
+#define FSMC_BWTR4_ADDHLD_3 0x00000080U /*!<Bit 3 */
+
+#define FSMC_BWTR4_DATAST 0x0000FF00U /*!<DATAST [7:0] bits (Data-phase duration) */
+#define FSMC_BWTR4_DATAST_0 0x00000100U /*!<Bit 0 */
+#define FSMC_BWTR4_DATAST_1 0x00000200U /*!<Bit 1 */
+#define FSMC_BWTR4_DATAST_2 0x00000400U /*!<Bit 2 */
+#define FSMC_BWTR4_DATAST_3 0x00000800U /*!<Bit 3 */
+#define FSMC_BWTR4_DATAST_4 0x00001000U /*!<Bit 4 */
+#define FSMC_BWTR4_DATAST_5 0x00002000U /*!<Bit 5 */
+#define FSMC_BWTR4_DATAST_6 0x00004000U /*!<Bit 6 */
+#define FSMC_BWTR4_DATAST_7 0x00008000U /*!<Bit 7 */
+
+#define FSMC_BWTR4_BUSTURN 0x000F0000U /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
+#define FSMC_BWTR4_BUSTURN_0 0x00010000U /*!<Bit 0 */
+#define FSMC_BWTR4_BUSTURN_1 0x00020000U /*!<Bit 1 */
+#define FSMC_BWTR4_BUSTURN_2 0x00040000U /*!<Bit 2 */
+#define FSMC_BWTR4_BUSTURN_3 0x00080000U /*!<Bit 3 */
+
+#define FSMC_BWTR4_ACCMOD 0x30000000U /*!<ACCMOD[1:0] bits (Access mode) */
+#define FSMC_BWTR4_ACCMOD_0 0x10000000U /*!<Bit 0 */
+#define FSMC_BWTR4_ACCMOD_1 0x20000000U /*!<Bit 1 */
+
+/****************** Bit definition for FSMC_PCR2 register *******************/
+#define FSMC_PCR2_PWAITEN 0x00000002U /*!<Wait feature enable bit */
+#define FSMC_PCR2_PBKEN 0x00000004U /*!<PC Card/NAND Flash memory bank enable bit */
+#define FSMC_PCR2_PTYP 0x00000008U /*!<Memory type */
+
+#define FSMC_PCR2_PWID 0x00000030U /*!<PWID[1:0] bits (NAND Flash databus width) */
+#define FSMC_PCR2_PWID_0 0x00000010U /*!<Bit 0 */
+#define FSMC_PCR2_PWID_1 0x00000020U /*!<Bit 1 */
+
+#define FSMC_PCR2_ECCEN 0x00000040U /*!<ECC computation logic enable bit */
+
+#define FSMC_PCR2_TCLR 0x00001E00U /*!<TCLR[3:0] bits (CLE to RE delay) */
+#define FSMC_PCR2_TCLR_0 0x00000200U /*!<Bit 0 */
+#define FSMC_PCR2_TCLR_1 0x00000400U /*!<Bit 1 */
+#define FSMC_PCR2_TCLR_2 0x00000800U /*!<Bit 2 */
+#define FSMC_PCR2_TCLR_3 0x00001000U /*!<Bit 3 */
+
+#define FSMC_PCR2_TAR 0x0001E000U /*!<TAR[3:0] bits (ALE to RE delay) */
+#define FSMC_PCR2_TAR_0 0x00002000U /*!<Bit 0 */
+#define FSMC_PCR2_TAR_1 0x00004000U /*!<Bit 1 */
+#define FSMC_PCR2_TAR_2 0x00008000U /*!<Bit 2 */
+#define FSMC_PCR2_TAR_3 0x00010000U /*!<Bit 3 */
+
+#define FSMC_PCR2_ECCPS 0x000E0000U /*!<ECCPS[1:0] bits (ECC page size) */
+#define FSMC_PCR2_ECCPS_0 0x00020000U /*!<Bit 0 */
+#define FSMC_PCR2_ECCPS_1 0x00040000U /*!<Bit 1 */
+#define FSMC_PCR2_ECCPS_2 0x00080000U /*!<Bit 2 */
+
+/****************** Bit definition for FSMC_PCR3 register *******************/
+#define FSMC_PCR3_PWAITEN 0x00000002U /*!<Wait feature enable bit */
+#define FSMC_PCR3_PBKEN 0x00000004U /*!<PC Card/NAND Flash memory bank enable bit */
+#define FSMC_PCR3_PTYP 0x00000008U /*!<Memory type */
+
+#define FSMC_PCR3_PWID 0x00000030U /*!<PWID[1:0] bits (NAND Flash databus width) */
+#define FSMC_PCR3_PWID_0 0x00000010U /*!<Bit 0 */
+#define FSMC_PCR3_PWID_1 0x00000020U /*!<Bit 1 */
+
+#define FSMC_PCR3_ECCEN 0x00000040U /*!<ECC computation logic enable bit */
+
+#define FSMC_PCR3_TCLR 0x00001E00U /*!<TCLR[3:0] bits (CLE to RE delay) */
+#define FSMC_PCR3_TCLR_0 0x00000200U /*!<Bit 0 */
+#define FSMC_PCR3_TCLR_1 0x00000400U /*!<Bit 1 */
+#define FSMC_PCR3_TCLR_2 0x00000800U /*!<Bit 2 */
+#define FSMC_PCR3_TCLR_3 0x00001000U /*!<Bit 3 */
+
+#define FSMC_PCR3_TAR 0x0001E000U /*!<TAR[3:0] bits (ALE to RE delay) */
+#define FSMC_PCR3_TAR_0 0x00002000U /*!<Bit 0 */
+#define FSMC_PCR3_TAR_1 0x00004000U /*!<Bit 1 */
+#define FSMC_PCR3_TAR_2 0x00008000U /*!<Bit 2 */
+#define FSMC_PCR3_TAR_3 0x00010000U /*!<Bit 3 */
+
+#define FSMC_PCR3_ECCPS 0x000E0000U /*!<ECCPS[2:0] bits (ECC page size) */
+#define FSMC_PCR3_ECCPS_0 0x00020000U /*!<Bit 0 */
+#define FSMC_PCR3_ECCPS_1 0x00040000U /*!<Bit 1 */
+#define FSMC_PCR3_ECCPS_2 0x00080000U /*!<Bit 2 */
+
+/****************** Bit definition for FSMC_PCR4 register *******************/
+#define FSMC_PCR4_PWAITEN 0x00000002U /*!<Wait feature enable bit */
+#define FSMC_PCR4_PBKEN 0x00000004U /*!<PC Card/NAND Flash memory bank enable bit */
+#define FSMC_PCR4_PTYP 0x00000008U /*!<Memory type */
+
+#define FSMC_PCR4_PWID 0x00000030U /*!<PWID[1:0] bits (NAND Flash databus width) */
+#define FSMC_PCR4_PWID_0 0x00000010U /*!<Bit 0 */
+#define FSMC_PCR4_PWID_1 0x00000020U /*!<Bit 1 */
+
+#define FSMC_PCR4_ECCEN 0x00000040U /*!<ECC computation logic enable bit */
+
+#define FSMC_PCR4_TCLR 0x00001E00U /*!<TCLR[3:0] bits (CLE to RE delay) */
+#define FSMC_PCR4_TCLR_0 0x00000200U /*!<Bit 0 */
+#define FSMC_PCR4_TCLR_1 0x00000400U /*!<Bit 1 */
+#define FSMC_PCR4_TCLR_2 0x00000800U /*!<Bit 2 */
+#define FSMC_PCR4_TCLR_3 0x00001000U /*!<Bit 3 */
+
+#define FSMC_PCR4_TAR 0x0001E000U /*!<TAR[3:0] bits (ALE to RE delay) */
+#define FSMC_PCR4_TAR_0 0x00002000U /*!<Bit 0 */
+#define FSMC_PCR4_TAR_1 0x00004000U /*!<Bit 1 */
+#define FSMC_PCR4_TAR_2 0x00008000U /*!<Bit 2 */
+#define FSMC_PCR4_TAR_3 0x00010000U /*!<Bit 3 */
+
+#define FSMC_PCR4_ECCPS 0x000E0000U /*!<ECCPS[2:0] bits (ECC page size) */
+#define FSMC_PCR4_ECCPS_0 0x00020000U /*!<Bit 0 */
+#define FSMC_PCR4_ECCPS_1 0x00040000U /*!<Bit 1 */
+#define FSMC_PCR4_ECCPS_2 0x00080000U /*!<Bit 2 */
+
+/******************* Bit definition for FSMC_SR2 register *******************/
+#define FSMC_SR2_IRS 0x01U /*!<Interrupt Rising Edge status */
+#define FSMC_SR2_ILS 0x02U /*!<Interrupt Level status */
+#define FSMC_SR2_IFS 0x04U /*!<Interrupt Falling Edge status */
+#define FSMC_SR2_IREN 0x08U /*!<Interrupt Rising Edge detection Enable bit */
+#define FSMC_SR2_ILEN 0x10U /*!<Interrupt Level detection Enable bit */
+#define FSMC_SR2_IFEN 0x20U /*!<Interrupt Falling Edge detection Enable bit */
+#define FSMC_SR2_FEMPT 0x40U /*!<FIFO empty */
+
+/******************* Bit definition for FSMC_SR3 register *******************/
+#define FSMC_SR3_IRS 0x01U /*!<Interrupt Rising Edge status */
+#define FSMC_SR3_ILS 0x02U /*!<Interrupt Level status */
+#define FSMC_SR3_IFS 0x04U /*!<Interrupt Falling Edge status */
+#define FSMC_SR3_IREN 0x08U /*!<Interrupt Rising Edge detection Enable bit */
+#define FSMC_SR3_ILEN 0x10U /*!<Interrupt Level detection Enable bit */
+#define FSMC_SR3_IFEN 0x20U /*!<Interrupt Falling Edge detection Enable bit */
+#define FSMC_SR3_FEMPT 0x40U /*!<FIFO empty */
+
+/******************* Bit definition for FSMC_SR4 register *******************/
+#define FSMC_SR4_IRS 0x01U /*!<Interrupt Rising Edge status */
+#define FSMC_SR4_ILS 0x02U /*!<Interrupt Level status */
+#define FSMC_SR4_IFS 0x04U /*!<Interrupt Falling Edge status */
+#define FSMC_SR4_IREN 0x08U /*!<Interrupt Rising Edge detection Enable bit */
+#define FSMC_SR4_ILEN 0x10U /*!<Interrupt Level detection Enable bit */
+#define FSMC_SR4_IFEN 0x20U /*!<Interrupt Falling Edge detection Enable bit */
+#define FSMC_SR4_FEMPT 0x40U /*!<FIFO empty */
+
+/****************** Bit definition for FSMC_PMEM2 register ******************/
+#define FSMC_PMEM2_MEMSET2 0x000000FFU /*!<MEMSET2[7:0] bits (Common memory 2 setup time) */
+#define FSMC_PMEM2_MEMSET2_0 0x00000001U /*!<Bit 0 */
+#define FSMC_PMEM2_MEMSET2_1 0x00000002U /*!<Bit 1 */
+#define FSMC_PMEM2_MEMSET2_2 0x00000004U /*!<Bit 2 */
+#define FSMC_PMEM2_MEMSET2_3 0x00000008U /*!<Bit 3 */
+#define FSMC_PMEM2_MEMSET2_4 0x00000010U /*!<Bit 4 */
+#define FSMC_PMEM2_MEMSET2_5 0x00000020U /*!<Bit 5 */
+#define FSMC_PMEM2_MEMSET2_6 0x00000040U /*!<Bit 6 */
+#define FSMC_PMEM2_MEMSET2_7 0x00000080U /*!<Bit 7 */
+
+#define FSMC_PMEM2_MEMWAIT2 0x0000FF00U /*!<MEMWAIT2[7:0] bits (Common memory 2 wait time) */
+#define FSMC_PMEM2_MEMWAIT2_0 0x00000100U /*!<Bit 0 */
+#define FSMC_PMEM2_MEMWAIT2_1 0x00000200U /*!<Bit 1 */
+#define FSMC_PMEM2_MEMWAIT2_2 0x00000400U /*!<Bit 2 */
+#define FSMC_PMEM2_MEMWAIT2_3 0x00000800U /*!<Bit 3 */
+#define FSMC_PMEM2_MEMWAIT2_4 0x00001000U /*!<Bit 4 */
+#define FSMC_PMEM2_MEMWAIT2_5 0x00002000U /*!<Bit 5 */
+#define FSMC_PMEM2_MEMWAIT2_6 0x00004000U /*!<Bit 6 */
+#define FSMC_PMEM2_MEMWAIT2_7 0x00008000U /*!<Bit 7 */
+
+#define FSMC_PMEM2_MEMHOLD2 0x00FF0000U /*!<MEMHOLD2[7:0] bits (Common memory 2 hold time) */
+#define FSMC_PMEM2_MEMHOLD2_0 0x00010000U /*!<Bit 0 */
+#define FSMC_PMEM2_MEMHOLD2_1 0x00020000U /*!<Bit 1 */
+#define FSMC_PMEM2_MEMHOLD2_2 0x00040000U /*!<Bit 2 */
+#define FSMC_PMEM2_MEMHOLD2_3 0x00080000U /*!<Bit 3 */
+#define FSMC_PMEM2_MEMHOLD2_4 0x00100000U /*!<Bit 4 */
+#define FSMC_PMEM2_MEMHOLD2_5 0x00200000U /*!<Bit 5 */
+#define FSMC_PMEM2_MEMHOLD2_6 0x00400000U /*!<Bit 6 */
+#define FSMC_PMEM2_MEMHOLD2_7 0x00800000U /*!<Bit 7 */
+
+#define FSMC_PMEM2_MEMHIZ2 0xFF000000U /*!<MEMHIZ2[7:0] bits (Common memory 2 databus HiZ time) */
+#define FSMC_PMEM2_MEMHIZ2_0 0x01000000U /*!<Bit 0 */
+#define FSMC_PMEM2_MEMHIZ2_1 0x02000000U /*!<Bit 1 */
+#define FSMC_PMEM2_MEMHIZ2_2 0x04000000U /*!<Bit 2 */
+#define FSMC_PMEM2_MEMHIZ2_3 0x08000000U /*!<Bit 3 */
+#define FSMC_PMEM2_MEMHIZ2_4 0x10000000U /*!<Bit 4 */
+#define FSMC_PMEM2_MEMHIZ2_5 0x20000000U /*!<Bit 5 */
+#define FSMC_PMEM2_MEMHIZ2_6 0x40000000U /*!<Bit 6 */
+#define FSMC_PMEM2_MEMHIZ2_7 0x80000000U /*!<Bit 7 */
+
+/****************** Bit definition for FSMC_PMEM3 register ******************/
+#define FSMC_PMEM3_MEMSET3 0x000000FFU /*!<MEMSET3[7:0] bits (Common memory 3 setup time) */
+#define FSMC_PMEM3_MEMSET3_0 0x00000001U /*!<Bit 0 */
+#define FSMC_PMEM3_MEMSET3_1 0x00000002U /*!<Bit 1 */
+#define FSMC_PMEM3_MEMSET3_2 0x00000004U /*!<Bit 2 */
+#define FSMC_PMEM3_MEMSET3_3 0x00000008U /*!<Bit 3 */
+#define FSMC_PMEM3_MEMSET3_4 0x00000010U /*!<Bit 4 */
+#define FSMC_PMEM3_MEMSET3_5 0x00000020U /*!<Bit 5 */
+#define FSMC_PMEM3_MEMSET3_6 0x00000040U /*!<Bit 6 */
+#define FSMC_PMEM3_MEMSET3_7 0x00000080U /*!<Bit 7 */
+
+#define FSMC_PMEM3_MEMWAIT3 0x0000FF00U /*!<MEMWAIT3[7:0] bits (Common memory 3 wait time) */
+#define FSMC_PMEM3_MEMWAIT3_0 0x00000100U /*!<Bit 0 */
+#define FSMC_PMEM3_MEMWAIT3_1 0x00000200U /*!<Bit 1 */
+#define FSMC_PMEM3_MEMWAIT3_2 0x00000400U /*!<Bit 2 */
+#define FSMC_PMEM3_MEMWAIT3_3 0x00000800U /*!<Bit 3 */
+#define FSMC_PMEM3_MEMWAIT3_4 0x00001000U /*!<Bit 4 */
+#define FSMC_PMEM3_MEMWAIT3_5 0x00002000U /*!<Bit 5 */
+#define FSMC_PMEM3_MEMWAIT3_6 0x00004000U /*!<Bit 6 */
+#define FSMC_PMEM3_MEMWAIT3_7 0x00008000U /*!<Bit 7 */
+
+#define FSMC_PMEM3_MEMHOLD3 0x00FF0000U /*!<MEMHOLD3[7:0] bits (Common memory 3 hold time) */
+#define FSMC_PMEM3_MEMHOLD3_0 0x00010000U /*!<Bit 0 */
+#define FSMC_PMEM3_MEMHOLD3_1 0x00020000U /*!<Bit 1 */
+#define FSMC_PMEM3_MEMHOLD3_2 0x00040000U /*!<Bit 2 */
+#define FSMC_PMEM3_MEMHOLD3_3 0x00080000U /*!<Bit 3 */
+#define FSMC_PMEM3_MEMHOLD3_4 0x00100000U /*!<Bit 4 */
+#define FSMC_PMEM3_MEMHOLD3_5 0x00200000U /*!<Bit 5 */
+#define FSMC_PMEM3_MEMHOLD3_6 0x00400000U /*!<Bit 6 */
+#define FSMC_PMEM3_MEMHOLD3_7 0x00800000U /*!<Bit 7 */
+
+#define FSMC_PMEM3_MEMHIZ3 0xFF000000U /*!<MEMHIZ3[7:0] bits (Common memory 3 databus HiZ time) */
+#define FSMC_PMEM3_MEMHIZ3_0 0x01000000U /*!<Bit 0 */
+#define FSMC_PMEM3_MEMHIZ3_1 0x02000000U /*!<Bit 1 */
+#define FSMC_PMEM3_MEMHIZ3_2 0x04000000U /*!<Bit 2 */
+#define FSMC_PMEM3_MEMHIZ3_3 0x08000000U /*!<Bit 3 */
+#define FSMC_PMEM3_MEMHIZ3_4 0x10000000U /*!<Bit 4 */
+#define FSMC_PMEM3_MEMHIZ3_5 0x20000000U /*!<Bit 5 */
+#define FSMC_PMEM3_MEMHIZ3_6 0x40000000U /*!<Bit 6 */
+#define FSMC_PMEM3_MEMHIZ3_7 0x80000000U /*!<Bit 7 */
+
+/****************** Bit definition for FSMC_PMEM4 register ******************/
+#define FSMC_PMEM4_MEMSET4 0x000000FFU /*!<MEMSET4[7:0] bits (Common memory 4 setup time) */
+#define FSMC_PMEM4_MEMSET4_0 0x00000001U /*!<Bit 0 */
+#define FSMC_PMEM4_MEMSET4_1 0x00000002U /*!<Bit 1 */
+#define FSMC_PMEM4_MEMSET4_2 0x00000004U /*!<Bit 2 */
+#define FSMC_PMEM4_MEMSET4_3 0x00000008U /*!<Bit 3 */
+#define FSMC_PMEM4_MEMSET4_4 0x00000010U /*!<Bit 4 */
+#define FSMC_PMEM4_MEMSET4_5 0x00000020U /*!<Bit 5 */
+#define FSMC_PMEM4_MEMSET4_6 0x00000040U /*!<Bit 6 */
+#define FSMC_PMEM4_MEMSET4_7 0x00000080U /*!<Bit 7 */
+
+#define FSMC_PMEM4_MEMWAIT4 0x0000FF00U /*!<MEMWAIT4[7:0] bits (Common memory 4 wait time) */
+#define FSMC_PMEM4_MEMWAIT4_0 0x00000100U /*!<Bit 0 */
+#define FSMC_PMEM4_MEMWAIT4_1 0x00000200U /*!<Bit 1 */
+#define FSMC_PMEM4_MEMWAIT4_2 0x00000400U /*!<Bit 2 */
+#define FSMC_PMEM4_MEMWAIT4_3 0x00000800U /*!<Bit 3 */
+#define FSMC_PMEM4_MEMWAIT4_4 0x00001000U /*!<Bit 4 */
+#define FSMC_PMEM4_MEMWAIT4_5 0x00002000U /*!<Bit 5 */
+#define FSMC_PMEM4_MEMWAIT4_6 0x00004000U /*!<Bit 6 */
+#define FSMC_PMEM4_MEMWAIT4_7 0x00008000U /*!<Bit 7 */
+
+#define FSMC_PMEM4_MEMHOLD4 0x00FF0000U /*!<MEMHOLD4[7:0] bits (Common memory 4 hold time) */
+#define FSMC_PMEM4_MEMHOLD4_0 0x00010000U /*!<Bit 0 */
+#define FSMC_PMEM4_MEMHOLD4_1 0x00020000U /*!<Bit 1 */
+#define FSMC_PMEM4_MEMHOLD4_2 0x00040000U /*!<Bit 2 */
+#define FSMC_PMEM4_MEMHOLD4_3 0x00080000U /*!<Bit 3 */
+#define FSMC_PMEM4_MEMHOLD4_4 0x00100000U /*!<Bit 4 */
+#define FSMC_PMEM4_MEMHOLD4_5 0x00200000U /*!<Bit 5 */
+#define FSMC_PMEM4_MEMHOLD4_6 0x00400000U /*!<Bit 6 */
+#define FSMC_PMEM4_MEMHOLD4_7 0x00800000U /*!<Bit 7 */
+
+#define FSMC_PMEM4_MEMHIZ4 0xFF000000U /*!<MEMHIZ4[7:0] bits (Common memory 4 databus HiZ time) */
+#define FSMC_PMEM4_MEMHIZ4_0 0x01000000U /*!<Bit 0 */
+#define FSMC_PMEM4_MEMHIZ4_1 0x02000000U /*!<Bit 1 */
+#define FSMC_PMEM4_MEMHIZ4_2 0x04000000U /*!<Bit 2 */
+#define FSMC_PMEM4_MEMHIZ4_3 0x08000000U /*!<Bit 3 */
+#define FSMC_PMEM4_MEMHIZ4_4 0x10000000U /*!<Bit 4 */
+#define FSMC_PMEM4_MEMHIZ4_5 0x20000000U /*!<Bit 5 */
+#define FSMC_PMEM4_MEMHIZ4_6 0x40000000U /*!<Bit 6 */
+#define FSMC_PMEM4_MEMHIZ4_7 0x80000000U /*!<Bit 7 */
+
+/****************** Bit definition for FSMC_PATT2 register ******************/
+#define FSMC_PATT2_ATTSET2 0x000000FFU /*!<ATTSET2[7:0] bits (Attribute memory 2 setup time) */
+#define FSMC_PATT2_ATTSET2_0 0x00000001U /*!<Bit 0 */
+#define FSMC_PATT2_ATTSET2_1 0x00000002U /*!<Bit 1 */
+#define FSMC_PATT2_ATTSET2_2 0x00000004U /*!<Bit 2 */
+#define FSMC_PATT2_ATTSET2_3 0x00000008U /*!<Bit 3 */
+#define FSMC_PATT2_ATTSET2_4 0x00000010U /*!<Bit 4 */
+#define FSMC_PATT2_ATTSET2_5 0x00000020U /*!<Bit 5 */
+#define FSMC_PATT2_ATTSET2_6 0x00000040U /*!<Bit 6 */
+#define FSMC_PATT2_ATTSET2_7 0x00000080U /*!<Bit 7 */
+
+#define FSMC_PATT2_ATTWAIT2 0x0000FF00U /*!<ATTWAIT2[7:0] bits (Attribute memory 2 wait time) */
+#define FSMC_PATT2_ATTWAIT2_0 0x00000100U /*!<Bit 0 */
+#define FSMC_PATT2_ATTWAIT2_1 0x00000200U /*!<Bit 1 */
+#define FSMC_PATT2_ATTWAIT2_2 0x00000400U /*!<Bit 2 */
+#define FSMC_PATT2_ATTWAIT2_3 0x00000800U /*!<Bit 3 */
+#define FSMC_PATT2_ATTWAIT2_4 0x00001000U /*!<Bit 4 */
+#define FSMC_PATT2_ATTWAIT2_5 0x00002000U /*!<Bit 5 */
+#define FSMC_PATT2_ATTWAIT2_6 0x00004000U /*!<Bit 6 */
+#define FSMC_PATT2_ATTWAIT2_7 0x00008000U /*!<Bit 7 */
+
+#define FSMC_PATT2_ATTHOLD2 0x00FF0000U /*!<ATTHOLD2[7:0] bits (Attribute memory 2 hold time) */
+#define FSMC_PATT2_ATTHOLD2_0 0x00010000U /*!<Bit 0 */
+#define FSMC_PATT2_ATTHOLD2_1 0x00020000U /*!<Bit 1 */
+#define FSMC_PATT2_ATTHOLD2_2 0x00040000U /*!<Bit 2 */
+#define FSMC_PATT2_ATTHOLD2_3 0x00080000U /*!<Bit 3 */
+#define FSMC_PATT2_ATTHOLD2_4 0x00100000U /*!<Bit 4 */
+#define FSMC_PATT2_ATTHOLD2_5 0x00200000U /*!<Bit 5 */
+#define FSMC_PATT2_ATTHOLD2_6 0x00400000U /*!<Bit 6 */
+#define FSMC_PATT2_ATTHOLD2_7 0x00800000U /*!<Bit 7 */
+
+#define FSMC_PATT2_ATTHIZ2 0xFF000000U /*!<ATTHIZ2[7:0] bits (Attribute memory 2 databus HiZ time) */
+#define FSMC_PATT2_ATTHIZ2_0 0x01000000U /*!<Bit 0 */
+#define FSMC_PATT2_ATTHIZ2_1 0x02000000U /*!<Bit 1 */
+#define FSMC_PATT2_ATTHIZ2_2 0x04000000U /*!<Bit 2 */
+#define FSMC_PATT2_ATTHIZ2_3 0x08000000U /*!<Bit 3 */
+#define FSMC_PATT2_ATTHIZ2_4 0x10000000U /*!<Bit 4 */
+#define FSMC_PATT2_ATTHIZ2_5 0x20000000U /*!<Bit 5 */
+#define FSMC_PATT2_ATTHIZ2_6 0x40000000U /*!<Bit 6 */
+#define FSMC_PATT2_ATTHIZ2_7 0x80000000U /*!<Bit 7 */
+
+/****************** Bit definition for FSMC_PATT3 register ******************/
+#define FSMC_PATT3_ATTSET3 0x000000FFU /*!<ATTSET3[7:0] bits (Attribute memory 3 setup time) */
+#define FSMC_PATT3_ATTSET3_0 0x00000001U /*!<Bit 0 */
+#define FSMC_PATT3_ATTSET3_1 0x00000002U /*!<Bit 1 */
+#define FSMC_PATT3_ATTSET3_2 0x00000004U /*!<Bit 2 */
+#define FSMC_PATT3_ATTSET3_3 0x00000008U /*!<Bit 3 */
+#define FSMC_PATT3_ATTSET3_4 0x00000010U /*!<Bit 4 */
+#define FSMC_PATT3_ATTSET3_5 0x00000020U /*!<Bit 5 */
+#define FSMC_PATT3_ATTSET3_6 0x00000040U /*!<Bit 6 */
+#define FSMC_PATT3_ATTSET3_7 0x00000080U /*!<Bit 7 */
+
+#define FSMC_PATT3_ATTWAIT3 0x0000FF00U /*!<ATTWAIT3[7:0] bits (Attribute memory 3 wait time) */
+#define FSMC_PATT3_ATTWAIT3_0 0x00000100U /*!<Bit 0 */
+#define FSMC_PATT3_ATTWAIT3_1 0x00000200U /*!<Bit 1 */
+#define FSMC_PATT3_ATTWAIT3_2 0x00000400U /*!<Bit 2 */
+#define FSMC_PATT3_ATTWAIT3_3 0x00000800U /*!<Bit 3 */
+#define FSMC_PATT3_ATTWAIT3_4 0x00001000U /*!<Bit 4 */
+#define FSMC_PATT3_ATTWAIT3_5 0x00002000U /*!<Bit 5 */
+#define FSMC_PATT3_ATTWAIT3_6 0x00004000U /*!<Bit 6 */
+#define FSMC_PATT3_ATTWAIT3_7 0x00008000U /*!<Bit 7 */
+
+#define FSMC_PATT3_ATTHOLD3 0x00FF0000U /*!<ATTHOLD3[7:0] bits (Attribute memory 3 hold time) */
+#define FSMC_PATT3_ATTHOLD3_0 0x00010000U /*!<Bit 0 */
+#define FSMC_PATT3_ATTHOLD3_1 0x00020000U /*!<Bit 1 */
+#define FSMC_PATT3_ATTHOLD3_2 0x00040000U /*!<Bit 2 */
+#define FSMC_PATT3_ATTHOLD3_3 0x00080000U /*!<Bit 3 */
+#define FSMC_PATT3_ATTHOLD3_4 0x00100000U /*!<Bit 4 */
+#define FSMC_PATT3_ATTHOLD3_5 0x00200000U /*!<Bit 5 */
+#define FSMC_PATT3_ATTHOLD3_6 0x00400000U /*!<Bit 6 */
+#define FSMC_PATT3_ATTHOLD3_7 0x00800000U /*!<Bit 7 */
+
+#define FSMC_PATT3_ATTHIZ3 0xFF000000U /*!<ATTHIZ3[7:0] bits (Attribute memory 3 databus HiZ time) */
+#define FSMC_PATT3_ATTHIZ3_0 0x01000000U /*!<Bit 0 */
+#define FSMC_PATT3_ATTHIZ3_1 0x02000000U /*!<Bit 1 */
+#define FSMC_PATT3_ATTHIZ3_2 0x04000000U /*!<Bit 2 */
+#define FSMC_PATT3_ATTHIZ3_3 0x08000000U /*!<Bit 3 */
+#define FSMC_PATT3_ATTHIZ3_4 0x10000000U /*!<Bit 4 */
+#define FSMC_PATT3_ATTHIZ3_5 0x20000000U /*!<Bit 5 */
+#define FSMC_PATT3_ATTHIZ3_6 0x40000000U /*!<Bit 6 */
+#define FSMC_PATT3_ATTHIZ3_7 0x80000000U /*!<Bit 7 */
+
+/****************** Bit definition for FSMC_PATT4 register ******************/
+#define FSMC_PATT4_ATTSET4 0x000000FFU /*!<ATTSET4[7:0] bits (Attribute memory 4 setup time) */
+#define FSMC_PATT4_ATTSET4_0 0x00000001U /*!<Bit 0 */
+#define FSMC_PATT4_ATTSET4_1 0x00000002U /*!<Bit 1 */
+#define FSMC_PATT4_ATTSET4_2 0x00000004U /*!<Bit 2 */
+#define FSMC_PATT4_ATTSET4_3 0x00000008U /*!<Bit 3 */
+#define FSMC_PATT4_ATTSET4_4 0x00000010U /*!<Bit 4 */
+#define FSMC_PATT4_ATTSET4_5 0x00000020U /*!<Bit 5 */
+#define FSMC_PATT4_ATTSET4_6 0x00000040U /*!<Bit 6 */
+#define FSMC_PATT4_ATTSET4_7 0x00000080U /*!<Bit 7 */
+
+#define FSMC_PATT4_ATTWAIT4 0x0000FF00U /*!<ATTWAIT4[7:0] bits (Attribute memory 4 wait time) */
+#define FSMC_PATT4_ATTWAIT4_0 0x00000100U /*!<Bit 0 */
+#define FSMC_PATT4_ATTWAIT4_1 0x00000200U /*!<Bit 1 */
+#define FSMC_PATT4_ATTWAIT4_2 0x00000400U /*!<Bit 2 */
+#define FSMC_PATT4_ATTWAIT4_3 0x00000800U /*!<Bit 3 */
+#define FSMC_PATT4_ATTWAIT4_4 0x00001000U /*!<Bit 4 */
+#define FSMC_PATT4_ATTWAIT4_5 0x00002000U /*!<Bit 5 */
+#define FSMC_PATT4_ATTWAIT4_6 0x00004000U /*!<Bit 6 */
+#define FSMC_PATT4_ATTWAIT4_7 0x00008000U /*!<Bit 7 */
+
+#define FSMC_PATT4_ATTHOLD4 0x00FF0000U /*!<ATTHOLD4[7:0] bits (Attribute memory 4 hold time) */
+#define FSMC_PATT4_ATTHOLD4_0 0x00010000U /*!<Bit 0 */
+#define FSMC_PATT4_ATTHOLD4_1 0x00020000U /*!<Bit 1 */
+#define FSMC_PATT4_ATTHOLD4_2 0x00040000U /*!<Bit 2 */
+#define FSMC_PATT4_ATTHOLD4_3 0x00080000U /*!<Bit 3 */
+#define FSMC_PATT4_ATTHOLD4_4 0x00100000U /*!<Bit 4 */
+#define FSMC_PATT4_ATTHOLD4_5 0x00200000U /*!<Bit 5 */
+#define FSMC_PATT4_ATTHOLD4_6 0x00400000U /*!<Bit 6 */
+#define FSMC_PATT4_ATTHOLD4_7 0x00800000U /*!<Bit 7 */
+
+#define FSMC_PATT4_ATTHIZ4 0xFF000000U /*!<ATTHIZ4[7:0] bits (Attribute memory 4 databus HiZ time) */
+#define FSMC_PATT4_ATTHIZ4_0 0x01000000U /*!<Bit 0 */
+#define FSMC_PATT4_ATTHIZ4_1 0x02000000U /*!<Bit 1 */
+#define FSMC_PATT4_ATTHIZ4_2 0x04000000U /*!<Bit 2 */
+#define FSMC_PATT4_ATTHIZ4_3 0x08000000U /*!<Bit 3 */
+#define FSMC_PATT4_ATTHIZ4_4 0x10000000U /*!<Bit 4 */
+#define FSMC_PATT4_ATTHIZ4_5 0x20000000U /*!<Bit 5 */
+#define FSMC_PATT4_ATTHIZ4_6 0x40000000U /*!<Bit 6 */
+#define FSMC_PATT4_ATTHIZ4_7 0x80000000U /*!<Bit 7 */
+
+/****************** Bit definition for FSMC_PIO4 register *******************/
+#define FSMC_PIO4_IOSET4 0x000000FFU /*!<IOSET4[7:0] bits (I/O 4 setup time) */
+#define FSMC_PIO4_IOSET4_0 0x00000001U /*!<Bit 0 */
+#define FSMC_PIO4_IOSET4_1 0x00000002U /*!<Bit 1 */
+#define FSMC_PIO4_IOSET4_2 0x00000004U /*!<Bit 2 */
+#define FSMC_PIO4_IOSET4_3 0x00000008U /*!<Bit 3 */
+#define FSMC_PIO4_IOSET4_4 0x00000010U /*!<Bit 4 */
+#define FSMC_PIO4_IOSET4_5 0x00000020U /*!<Bit 5 */
+#define FSMC_PIO4_IOSET4_6 0x00000040U /*!<Bit 6 */
+#define FSMC_PIO4_IOSET4_7 0x00000080U /*!<Bit 7 */
+
+#define FSMC_PIO4_IOWAIT4 0x0000FF00U /*!<IOWAIT4[7:0] bits (I/O 4 wait time) */
+#define FSMC_PIO4_IOWAIT4_0 0x00000100U /*!<Bit 0 */
+#define FSMC_PIO4_IOWAIT4_1 0x00000200U /*!<Bit 1 */
+#define FSMC_PIO4_IOWAIT4_2 0x00000400U /*!<Bit 2 */
+#define FSMC_PIO4_IOWAIT4_3 0x00000800U /*!<Bit 3 */
+#define FSMC_PIO4_IOWAIT4_4 0x00001000U /*!<Bit 4 */
+#define FSMC_PIO4_IOWAIT4_5 0x00002000U /*!<Bit 5 */
+#define FSMC_PIO4_IOWAIT4_6 0x00004000U /*!<Bit 6 */
+#define FSMC_PIO4_IOWAIT4_7 0x00008000U /*!<Bit 7 */
+
+#define FSMC_PIO4_IOHOLD4 0x00FF0000U /*!<IOHOLD4[7:0] bits (I/O 4 hold time) */
+#define FSMC_PIO4_IOHOLD4_0 0x00010000U /*!<Bit 0 */
+#define FSMC_PIO4_IOHOLD4_1 0x00020000U /*!<Bit 1 */
+#define FSMC_PIO4_IOHOLD4_2 0x00040000U /*!<Bit 2 */
+#define FSMC_PIO4_IOHOLD4_3 0x00080000U /*!<Bit 3 */
+#define FSMC_PIO4_IOHOLD4_4 0x00100000U /*!<Bit 4 */
+#define FSMC_PIO4_IOHOLD4_5 0x00200000U /*!<Bit 5 */
+#define FSMC_PIO4_IOHOLD4_6 0x00400000U /*!<Bit 6 */
+#define FSMC_PIO4_IOHOLD4_7 0x00800000U /*!<Bit 7 */
+
+#define FSMC_PIO4_IOHIZ4 0xFF000000U /*!<IOHIZ4[7:0] bits (I/O 4 databus HiZ time) */
+#define FSMC_PIO4_IOHIZ4_0 0x01000000U /*!<Bit 0 */
+#define FSMC_PIO4_IOHIZ4_1 0x02000000U /*!<Bit 1 */
+#define FSMC_PIO4_IOHIZ4_2 0x04000000U /*!<Bit 2 */
+#define FSMC_PIO4_IOHIZ4_3 0x08000000U /*!<Bit 3 */
+#define FSMC_PIO4_IOHIZ4_4 0x10000000U /*!<Bit 4 */
+#define FSMC_PIO4_IOHIZ4_5 0x20000000U /*!<Bit 5 */
+#define FSMC_PIO4_IOHIZ4_6 0x40000000U /*!<Bit 6 */
+#define FSMC_PIO4_IOHIZ4_7 0x80000000U /*!<Bit 7 */
+
+/****************** Bit definition for FSMC_ECCR2 register ******************/
+#define FSMC_ECCR2_ECC2 0xFFFFFFFFU /*!<ECC result */
+
+/****************** Bit definition for FSMC_ECCR3 register ******************/
+#define FSMC_ECCR3_ECC3 0xFFFFFFFFU /*!<ECC result */
+
+/******************************************************************************/
+/* */
+/* General Purpose I/O */
+/* */
+/******************************************************************************/
+/****************** Bits definition for GPIO_MODER register *****************/
+#define GPIO_MODER_MODER0 0x00000003U
+#define GPIO_MODER_MODER0_0 0x00000001U
+#define GPIO_MODER_MODER0_1 0x00000002U
+
+#define GPIO_MODER_MODER1 0x0000000CU
+#define GPIO_MODER_MODER1_0 0x00000004U
+#define GPIO_MODER_MODER1_1 0x00000008U
+
+#define GPIO_MODER_MODER2 0x00000030U
+#define GPIO_MODER_MODER2_0 0x00000010U
+#define GPIO_MODER_MODER2_1 0x00000020U
+
+#define GPIO_MODER_MODER3 0x000000C0U
+#define GPIO_MODER_MODER3_0 0x00000040U
+#define GPIO_MODER_MODER3_1 0x00000080U
+
+#define GPIO_MODER_MODER4 0x00000300U
+#define GPIO_MODER_MODER4_0 0x00000100U
+#define GPIO_MODER_MODER4_1 0x00000200U
+
+#define GPIO_MODER_MODER5 0x00000C00U
+#define GPIO_MODER_MODER5_0 0x00000400U
+#define GPIO_MODER_MODER5_1 0x00000800U
+
+#define GPIO_MODER_MODER6 0x00003000U
+#define GPIO_MODER_MODER6_0 0x00001000U
+#define GPIO_MODER_MODER6_1 0x00002000U
+
+#define GPIO_MODER_MODER7 0x0000C000U
+#define GPIO_MODER_MODER7_0 0x00004000U
+#define GPIO_MODER_MODER7_1 0x00008000U
+
+#define GPIO_MODER_MODER8 0x00030000U
+#define GPIO_MODER_MODER8_0 0x00010000U
+#define GPIO_MODER_MODER8_1 0x00020000U
+
+#define GPIO_MODER_MODER9 0x000C0000U
+#define GPIO_MODER_MODER9_0 0x00040000U
+#define GPIO_MODER_MODER9_1 0x00080000U
+
+#define GPIO_MODER_MODER10 0x00300000U
+#define GPIO_MODER_MODER10_0 0x00100000U
+#define GPIO_MODER_MODER10_1 0x00200000U
+
+#define GPIO_MODER_MODER11 0x00C00000U
+#define GPIO_MODER_MODER11_0 0x00400000U
+#define GPIO_MODER_MODER11_1 0x00800000U
+
+#define GPIO_MODER_MODER12 0x03000000U
+#define GPIO_MODER_MODER12_0 0x01000000U
+#define GPIO_MODER_MODER12_1 0x02000000U
+
+#define GPIO_MODER_MODER13 0x0C000000U
+#define GPIO_MODER_MODER13_0 0x04000000U
+#define GPIO_MODER_MODER13_1 0x08000000U
+
+#define GPIO_MODER_MODER14 0x30000000U
+#define GPIO_MODER_MODER14_0 0x10000000U
+#define GPIO_MODER_MODER14_1 0x20000000U
+
+#define GPIO_MODER_MODER15 0xC0000000U
+#define GPIO_MODER_MODER15_0 0x40000000U
+#define GPIO_MODER_MODER15_1 0x80000000U
+
+/****************** Bits definition for GPIO_OTYPER register ****************/
+#define GPIO_OTYPER_OT_0 0x00000001U
+#define GPIO_OTYPER_OT_1 0x00000002U
+#define GPIO_OTYPER_OT_2 0x00000004U
+#define GPIO_OTYPER_OT_3 0x00000008U
+#define GPIO_OTYPER_OT_4 0x00000010U
+#define GPIO_OTYPER_OT_5 0x00000020U
+#define GPIO_OTYPER_OT_6 0x00000040U
+#define GPIO_OTYPER_OT_7 0x00000080U
+#define GPIO_OTYPER_OT_8 0x00000100U
+#define GPIO_OTYPER_OT_9 0x00000200U
+#define GPIO_OTYPER_OT_10 0x00000400U
+#define GPIO_OTYPER_OT_11 0x00000800U
+#define GPIO_OTYPER_OT_12 0x00001000U
+#define GPIO_OTYPER_OT_13 0x00002000U
+#define GPIO_OTYPER_OT_14 0x00004000U
+#define GPIO_OTYPER_OT_15 0x00008000U
+
+/****************** Bits definition for GPIO_OSPEEDR register ***************/
+#define GPIO_OSPEEDER_OSPEEDR0 0x00000003U
+#define GPIO_OSPEEDER_OSPEEDR0_0 0x00000001U
+#define GPIO_OSPEEDER_OSPEEDR0_1 0x00000002U
+
+#define GPIO_OSPEEDER_OSPEEDR1 0x0000000CU
+#define GPIO_OSPEEDER_OSPEEDR1_0 0x00000004U
+#define GPIO_OSPEEDER_OSPEEDR1_1 0x00000008U
+
+#define GPIO_OSPEEDER_OSPEEDR2 0x00000030U
+#define GPIO_OSPEEDER_OSPEEDR2_0 0x00000010U
+#define GPIO_OSPEEDER_OSPEEDR2_1 0x00000020U
+
+#define GPIO_OSPEEDER_OSPEEDR3 0x000000C0U
+#define GPIO_OSPEEDER_OSPEEDR3_0 0x00000040U
+#define GPIO_OSPEEDER_OSPEEDR3_1 0x00000080U
+
+#define GPIO_OSPEEDER_OSPEEDR4 0x00000300U
+#define GPIO_OSPEEDER_OSPEEDR4_0 0x00000100U
+#define GPIO_OSPEEDER_OSPEEDR4_1 0x00000200U
+
+#define GPIO_OSPEEDER_OSPEEDR5 0x00000C00U
+#define GPIO_OSPEEDER_OSPEEDR5_0 0x00000400U
+#define GPIO_OSPEEDER_OSPEEDR5_1 0x00000800U
+
+#define GPIO_OSPEEDER_OSPEEDR6 0x00003000U
+#define GPIO_OSPEEDER_OSPEEDR6_0 0x00001000U
+#define GPIO_OSPEEDER_OSPEEDR6_1 0x00002000U
+
+#define GPIO_OSPEEDER_OSPEEDR7 0x0000C000U
+#define GPIO_OSPEEDER_OSPEEDR7_0 0x00004000U
+#define GPIO_OSPEEDER_OSPEEDR7_1 0x00008000U
+
+#define GPIO_OSPEEDER_OSPEEDR8 0x00030000U
+#define GPIO_OSPEEDER_OSPEEDR8_0 0x00010000U
+#define GPIO_OSPEEDER_OSPEEDR8_1 0x00020000U
+
+#define GPIO_OSPEEDER_OSPEEDR9 0x000C0000U
+#define GPIO_OSPEEDER_OSPEEDR9_0 0x00040000U
+#define GPIO_OSPEEDER_OSPEEDR9_1 0x00080000U
+
+#define GPIO_OSPEEDER_OSPEEDR10 0x00300000U
+#define GPIO_OSPEEDER_OSPEEDR10_0 0x00100000U
+#define GPIO_OSPEEDER_OSPEEDR10_1 0x00200000U
+
+#define GPIO_OSPEEDER_OSPEEDR11 0x00C00000U
+#define GPIO_OSPEEDER_OSPEEDR11_0 0x00400000U
+#define GPIO_OSPEEDER_OSPEEDR11_1 0x00800000U
+
+#define GPIO_OSPEEDER_OSPEEDR12 0x03000000U
+#define GPIO_OSPEEDER_OSPEEDR12_0 0x01000000U
+#define GPIO_OSPEEDER_OSPEEDR12_1 0x02000000U
+
+#define GPIO_OSPEEDER_OSPEEDR13 0x0C000000U
+#define GPIO_OSPEEDER_OSPEEDR13_0 0x04000000U
+#define GPIO_OSPEEDER_OSPEEDR13_1 0x08000000U
+
+#define GPIO_OSPEEDER_OSPEEDR14 0x30000000U
+#define GPIO_OSPEEDER_OSPEEDR14_0 0x10000000U
+#define GPIO_OSPEEDER_OSPEEDR14_1 0x20000000U
+
+#define GPIO_OSPEEDER_OSPEEDR15 0xC0000000U
+#define GPIO_OSPEEDER_OSPEEDR15_0 0x40000000U
+#define GPIO_OSPEEDER_OSPEEDR15_1 0x80000000U
+
+/****************** Bits definition for GPIO_PUPDR register *****************/
+#define GPIO_PUPDR_PUPDR0 0x00000003U
+#define GPIO_PUPDR_PUPDR0_0 0x00000001U
+#define GPIO_PUPDR_PUPDR0_1 0x00000002U
+
+#define GPIO_PUPDR_PUPDR1 0x0000000CU
+#define GPIO_PUPDR_PUPDR1_0 0x00000004U
+#define GPIO_PUPDR_PUPDR1_1 0x00000008U
+
+#define GPIO_PUPDR_PUPDR2 0x00000030U
+#define GPIO_PUPDR_PUPDR2_0 0x00000010U
+#define GPIO_PUPDR_PUPDR2_1 0x00000020U
+
+#define GPIO_PUPDR_PUPDR3 0x000000C0U
+#define GPIO_PUPDR_PUPDR3_0 0x00000040U
+#define GPIO_PUPDR_PUPDR3_1 0x00000080U
+
+#define GPIO_PUPDR_PUPDR4 0x00000300U
+#define GPIO_PUPDR_PUPDR4_0 0x00000100U
+#define GPIO_PUPDR_PUPDR4_1 0x00000200U
+
+#define GPIO_PUPDR_PUPDR5 0x00000C00U
+#define GPIO_PUPDR_PUPDR5_0 0x00000400U
+#define GPIO_PUPDR_PUPDR5_1 0x00000800U
+
+#define GPIO_PUPDR_PUPDR6 0x00003000U
+#define GPIO_PUPDR_PUPDR6_0 0x00001000U
+#define GPIO_PUPDR_PUPDR6_1 0x00002000U
+
+#define GPIO_PUPDR_PUPDR7 0x0000C000U
+#define GPIO_PUPDR_PUPDR7_0 0x00004000U
+#define GPIO_PUPDR_PUPDR7_1 0x00008000U
+
+#define GPIO_PUPDR_PUPDR8 0x00030000U
+#define GPIO_PUPDR_PUPDR8_0 0x00010000U
+#define GPIO_PUPDR_PUPDR8_1 0x00020000U
+
+#define GPIO_PUPDR_PUPDR9 0x000C0000U
+#define GPIO_PUPDR_PUPDR9_0 0x00040000U
+#define GPIO_PUPDR_PUPDR9_1 0x00080000U
+
+#define GPIO_PUPDR_PUPDR10 0x00300000U
+#define GPIO_PUPDR_PUPDR10_0 0x00100000U
+#define GPIO_PUPDR_PUPDR10_1 0x00200000U
+
+#define GPIO_PUPDR_PUPDR11 0x00C00000U
+#define GPIO_PUPDR_PUPDR11_0 0x00400000U
+#define GPIO_PUPDR_PUPDR11_1 0x00800000U
+
+#define GPIO_PUPDR_PUPDR12 0x03000000U
+#define GPIO_PUPDR_PUPDR12_0 0x01000000U
+#define GPIO_PUPDR_PUPDR12_1 0x02000000U
+
+#define GPIO_PUPDR_PUPDR13 0x0C000000U
+#define GPIO_PUPDR_PUPDR13_0 0x04000000U
+#define GPIO_PUPDR_PUPDR13_1 0x08000000U
+
+#define GPIO_PUPDR_PUPDR14 0x30000000U
+#define GPIO_PUPDR_PUPDR14_0 0x10000000U
+#define GPIO_PUPDR_PUPDR14_1 0x20000000U
+
+#define GPIO_PUPDR_PUPDR15 0xC0000000U
+#define GPIO_PUPDR_PUPDR15_0 0x40000000U
+#define GPIO_PUPDR_PUPDR15_1 0x80000000U
+
+/****************** Bits definition for GPIO_IDR register *******************/
+#define GPIO_IDR_IDR_0 0x00000001U
+#define GPIO_IDR_IDR_1 0x00000002U
+#define GPIO_IDR_IDR_2 0x00000004U
+#define GPIO_IDR_IDR_3 0x00000008U
+#define GPIO_IDR_IDR_4 0x00000010U
+#define GPIO_IDR_IDR_5 0x00000020U
+#define GPIO_IDR_IDR_6 0x00000040U
+#define GPIO_IDR_IDR_7 0x00000080U
+#define GPIO_IDR_IDR_8 0x00000100U
+#define GPIO_IDR_IDR_9 0x00000200U
+#define GPIO_IDR_IDR_10 0x00000400U
+#define GPIO_IDR_IDR_11 0x00000800U
+#define GPIO_IDR_IDR_12 0x00001000U
+#define GPIO_IDR_IDR_13 0x00002000U
+#define GPIO_IDR_IDR_14 0x00004000U
+#define GPIO_IDR_IDR_15 0x00008000U
+/* Old GPIO_IDR register bits definition, maintained for legacy purpose */
+#define GPIO_OTYPER_IDR_0 GPIO_IDR_IDR_0
+#define GPIO_OTYPER_IDR_1 GPIO_IDR_IDR_1
+#define GPIO_OTYPER_IDR_2 GPIO_IDR_IDR_2
+#define GPIO_OTYPER_IDR_3 GPIO_IDR_IDR_3
+#define GPIO_OTYPER_IDR_4 GPIO_IDR_IDR_4
+#define GPIO_OTYPER_IDR_5 GPIO_IDR_IDR_5
+#define GPIO_OTYPER_IDR_6 GPIO_IDR_IDR_6
+#define GPIO_OTYPER_IDR_7 GPIO_IDR_IDR_7
+#define GPIO_OTYPER_IDR_8 GPIO_IDR_IDR_8
+#define GPIO_OTYPER_IDR_9 GPIO_IDR_IDR_9
+#define GPIO_OTYPER_IDR_10 GPIO_IDR_IDR_10
+#define GPIO_OTYPER_IDR_11 GPIO_IDR_IDR_11
+#define GPIO_OTYPER_IDR_12 GPIO_IDR_IDR_12
+#define GPIO_OTYPER_IDR_13 GPIO_IDR_IDR_13
+#define GPIO_OTYPER_IDR_14 GPIO_IDR_IDR_14
+#define GPIO_OTYPER_IDR_15 GPIO_IDR_IDR_15
+
+/****************** Bits definition for GPIO_ODR register *******************/
+#define GPIO_ODR_ODR_0 0x00000001U
+#define GPIO_ODR_ODR_1 0x00000002U
+#define GPIO_ODR_ODR_2 0x00000004U
+#define GPIO_ODR_ODR_3 0x00000008U
+#define GPIO_ODR_ODR_4 0x00000010U
+#define GPIO_ODR_ODR_5 0x00000020U
+#define GPIO_ODR_ODR_6 0x00000040U
+#define GPIO_ODR_ODR_7 0x00000080U
+#define GPIO_ODR_ODR_8 0x00000100U
+#define GPIO_ODR_ODR_9 0x00000200U
+#define GPIO_ODR_ODR_10 0x00000400U
+#define GPIO_ODR_ODR_11 0x00000800U
+#define GPIO_ODR_ODR_12 0x00001000U
+#define GPIO_ODR_ODR_13 0x00002000U
+#define GPIO_ODR_ODR_14 0x00004000U
+#define GPIO_ODR_ODR_15 0x00008000U
+/* Old GPIO_ODR register bits definition, maintained for legacy purpose */
+#define GPIO_OTYPER_ODR_0 GPIO_ODR_ODR_0
+#define GPIO_OTYPER_ODR_1 GPIO_ODR_ODR_1
+#define GPIO_OTYPER_ODR_2 GPIO_ODR_ODR_2
+#define GPIO_OTYPER_ODR_3 GPIO_ODR_ODR_3
+#define GPIO_OTYPER_ODR_4 GPIO_ODR_ODR_4
+#define GPIO_OTYPER_ODR_5 GPIO_ODR_ODR_5
+#define GPIO_OTYPER_ODR_6 GPIO_ODR_ODR_6
+#define GPIO_OTYPER_ODR_7 GPIO_ODR_ODR_7
+#define GPIO_OTYPER_ODR_8 GPIO_ODR_ODR_8
+#define GPIO_OTYPER_ODR_9 GPIO_ODR_ODR_9
+#define GPIO_OTYPER_ODR_10 GPIO_ODR_ODR_10
+#define GPIO_OTYPER_ODR_11 GPIO_ODR_ODR_11
+#define GPIO_OTYPER_ODR_12 GPIO_ODR_ODR_12
+#define GPIO_OTYPER_ODR_13 GPIO_ODR_ODR_13
+#define GPIO_OTYPER_ODR_14 GPIO_ODR_ODR_14
+#define GPIO_OTYPER_ODR_15 GPIO_ODR_ODR_15
+
+/****************** Bits definition for GPIO_BSRR register ******************/
+#define GPIO_BSRR_BS_0 0x00000001U
+#define GPIO_BSRR_BS_1 0x00000002U
+#define GPIO_BSRR_BS_2 0x00000004U
+#define GPIO_BSRR_BS_3 0x00000008U
+#define GPIO_BSRR_BS_4 0x00000010U
+#define GPIO_BSRR_BS_5 0x00000020U
+#define GPIO_BSRR_BS_6 0x00000040U
+#define GPIO_BSRR_BS_7 0x00000080U
+#define GPIO_BSRR_BS_8 0x00000100U
+#define GPIO_BSRR_BS_9 0x00000200U
+#define GPIO_BSRR_BS_10 0x00000400U
+#define GPIO_BSRR_BS_11 0x00000800U
+#define GPIO_BSRR_BS_12 0x00001000U
+#define GPIO_BSRR_BS_13 0x00002000U
+#define GPIO_BSRR_BS_14 0x00004000U
+#define GPIO_BSRR_BS_15 0x00008000U
+#define GPIO_BSRR_BR_0 0x00010000U
+#define GPIO_BSRR_BR_1 0x00020000U
+#define GPIO_BSRR_BR_2 0x00040000U
+#define GPIO_BSRR_BR_3 0x00080000U
+#define GPIO_BSRR_BR_4 0x00100000U
+#define GPIO_BSRR_BR_5 0x00200000U
+#define GPIO_BSRR_BR_6 0x00400000U
+#define GPIO_BSRR_BR_7 0x00800000U
+#define GPIO_BSRR_BR_8 0x01000000U
+#define GPIO_BSRR_BR_9 0x02000000U
+#define GPIO_BSRR_BR_10 0x04000000U
+#define GPIO_BSRR_BR_11 0x08000000U
+#define GPIO_BSRR_BR_12 0x10000000U
+#define GPIO_BSRR_BR_13 0x20000000U
+#define GPIO_BSRR_BR_14 0x40000000U
+#define GPIO_BSRR_BR_15 0x80000000U
+
+/****************** Bit definition for GPIO_LCKR register *********************/
+#define GPIO_LCKR_LCK0 0x00000001U
+#define GPIO_LCKR_LCK1 0x00000002U
+#define GPIO_LCKR_LCK2 0x00000004U
+#define GPIO_LCKR_LCK3 0x00000008U
+#define GPIO_LCKR_LCK4 0x00000010U
+#define GPIO_LCKR_LCK5 0x00000020U
+#define GPIO_LCKR_LCK6 0x00000040U
+#define GPIO_LCKR_LCK7 0x00000080U
+#define GPIO_LCKR_LCK8 0x00000100U
+#define GPIO_LCKR_LCK9 0x00000200U
+#define GPIO_LCKR_LCK10 0x00000400U
+#define GPIO_LCKR_LCK11 0x00000800U
+#define GPIO_LCKR_LCK12 0x00001000U
+#define GPIO_LCKR_LCK13 0x00002000U
+#define GPIO_LCKR_LCK14 0x00004000U
+#define GPIO_LCKR_LCK15 0x00008000U
+#define GPIO_LCKR_LCKK 0x00010000U
+
+/******************************************************************************/
+/* */
+/* HASH */
+/* */
+/******************************************************************************/
+/****************** Bits definition for HASH_CR register ********************/
+#define HASH_CR_INIT 0x00000004U
+#define HASH_CR_DMAE 0x00000008U
+#define HASH_CR_DATATYPE 0x00000030U
+#define HASH_CR_DATATYPE_0 0x00000010U
+#define HASH_CR_DATATYPE_1 0x00000020U
+#define HASH_CR_MODE 0x00000040U
+#define HASH_CR_ALGO 0x00040080U
+#define HASH_CR_ALGO_0 0x00000080U
+#define HASH_CR_ALGO_1 0x00040000U
+#define HASH_CR_NBW 0x00000F00U
+#define HASH_CR_NBW_0 0x00000100U
+#define HASH_CR_NBW_1 0x00000200U
+#define HASH_CR_NBW_2 0x00000400U
+#define HASH_CR_NBW_3 0x00000800U
+#define HASH_CR_DINNE 0x00001000U
+#define HASH_CR_MDMAT 0x00002000U
+#define HASH_CR_LKEY 0x00010000U
+
+/****************** Bits definition for HASH_STR register *******************/
+#define HASH_STR_NBLW 0x0000001FU
+#define HASH_STR_NBLW_0 0x00000001U
+#define HASH_STR_NBLW_1 0x00000002U
+#define HASH_STR_NBLW_2 0x00000004U
+#define HASH_STR_NBLW_3 0x00000008U
+#define HASH_STR_NBLW_4 0x00000010U
+#define HASH_STR_DCAL 0x00000100U
+/* Aliases for HASH_STR register */
+#define HASH_STR_NBW HASH_STR_NBLW
+#define HASH_STR_NBW_0 HASH_STR_NBLW_0
+#define HASH_STR_NBW_1 HASH_STR_NBLW_1
+#define HASH_STR_NBW_2 HASH_STR_NBLW_2
+#define HASH_STR_NBW_3 HASH_STR_NBLW_3
+#define HASH_STR_NBW_4 HASH_STR_NBLW_4
+
+/****************** Bits definition for HASH_IMR register *******************/
+#define HASH_IMR_DINIE 0x00000001U
+#define HASH_IMR_DCIE 0x00000002U
+/* Aliases for HASH_IMR register */
+#define HASH_IMR_DINIM HASH_IMR_DINIE
+#define HASH_IMR_DCIM HASH_IMR_DCIE
+
+/****************** Bits definition for HASH_SR register ********************/
+#define HASH_SR_DINIS 0x00000001U
+#define HASH_SR_DCIS 0x00000002U
+#define HASH_SR_DMAS 0x00000004U
+#define HASH_SR_BUSY 0x00000008U
+
+/******************************************************************************/
+/* */
+/* Inter-integrated Circuit Interface */
+/* */
+/******************************************************************************/
+/******************* Bit definition for I2C_CR1 register ********************/
+#define I2C_CR1_PE 0x00000001U /*!<Peripheral Enable */
+#define I2C_CR1_SMBUS 0x00000002U /*!<SMBus Mode */
+#define I2C_CR1_SMBTYPE 0x00000008U /*!<SMBus Type */
+#define I2C_CR1_ENARP 0x00000010U /*!<ARP Enable */
+#define I2C_CR1_ENPEC 0x00000020U /*!<PEC Enable */
+#define I2C_CR1_ENGC 0x00000040U /*!<General Call Enable */
+#define I2C_CR1_NOSTRETCH 0x00000080U /*!<Clock Stretching Disable (Slave mode) */
+#define I2C_CR1_START 0x00000100U /*!<Start Generation */
+#define I2C_CR1_STOP 0x00000200U /*!<Stop Generation */
+#define I2C_CR1_ACK 0x00000400U /*!<Acknowledge Enable */
+#define I2C_CR1_POS 0x00000800U /*!<Acknowledge/PEC Position (for data reception) */
+#define I2C_CR1_PEC 0x00001000U /*!<Packet Error Checking */
+#define I2C_CR1_ALERT 0x00002000U /*!<SMBus Alert */
+#define I2C_CR1_SWRST 0x00008000U /*!<Software Reset */
+
+/******************* Bit definition for I2C_CR2 register ********************/
+#define I2C_CR2_FREQ 0x0000003FU /*!<FREQ[5:0] bits (Peripheral Clock Frequency) */
+#define I2C_CR2_FREQ_0 0x00000001U /*!<Bit 0 */
+#define I2C_CR2_FREQ_1 0x00000002U /*!<Bit 1 */
+#define I2C_CR2_FREQ_2 0x00000004U /*!<Bit 2 */
+#define I2C_CR2_FREQ_3 0x00000008U /*!<Bit 3 */
+#define I2C_CR2_FREQ_4 0x00000010U /*!<Bit 4 */
+#define I2C_CR2_FREQ_5 0x00000020U /*!<Bit 5 */
+
+#define I2C_CR2_ITERREN 0x00000100U /*!<Error Interrupt Enable */
+#define I2C_CR2_ITEVTEN 0x00000200U /*!<Event Interrupt Enable */
+#define I2C_CR2_ITBUFEN 0x00000400U /*!<Buffer Interrupt Enable */
+#define I2C_CR2_DMAEN 0x00000800U /*!<DMA Requests Enable */
+#define I2C_CR2_LAST 0x00001000U /*!<DMA Last Transfer */
+
+/******************* Bit definition for I2C_OAR1 register *******************/
+#define I2C_OAR1_ADD1_7 0x000000FEU /*!<Interface Address */
+#define I2C_OAR1_ADD8_9 0x00000300U /*!<Interface Address */
+
+#define I2C_OAR1_ADD0 0x00000001U /*!<Bit 0 */
+#define I2C_OAR1_ADD1 0x00000002U /*!<Bit 1 */
+#define I2C_OAR1_ADD2 0x00000004U /*!<Bit 2 */
+#define I2C_OAR1_ADD3 0x00000008U /*!<Bit 3 */
+#define I2C_OAR1_ADD4 0x00000010U /*!<Bit 4 */
+#define I2C_OAR1_ADD5 0x00000020U /*!<Bit 5 */
+#define I2C_OAR1_ADD6 0x00000040U /*!<Bit 6 */
+#define I2C_OAR1_ADD7 0x00000080U /*!<Bit 7 */
+#define I2C_OAR1_ADD8 0x00000100U /*!<Bit 8 */
+#define I2C_OAR1_ADD9 0x00000200U /*!<Bit 9 */
+
+#define I2C_OAR1_ADDMODE 0x00008000U /*!<Addressing Mode (Slave mode) */
+
+/******************* Bit definition for I2C_OAR2 register *******************/
+#define I2C_OAR2_ENDUAL 0x00000001U /*!<Dual addressing mode enable */
+#define I2C_OAR2_ADD2 0x000000FEU /*!<Interface address */
+
+/******************** Bit definition for I2C_DR register ********************/
+#define I2C_DR_DR 0x000000FFU /*!<8-bit Data Register */
+
+/******************* Bit definition for I2C_SR1 register ********************/
+#define I2C_SR1_SB 0x00000001U /*!<Start Bit (Master mode) */
+#define I2C_SR1_ADDR 0x00000002U /*!<Address sent (master mode)/matched (slave mode) */
+#define I2C_SR1_BTF 0x00000004U /*!<Byte Transfer Finished */
+#define I2C_SR1_ADD10 0x00000008U /*!<10-bit header sent (Master mode) */
+#define I2C_SR1_STOPF 0x00000010U /*!<Stop detection (Slave mode) */
+#define I2C_SR1_RXNE 0x00000040U /*!<Data Register not Empty (receivers) */
+#define I2C_SR1_TXE 0x00000080U /*!<Data Register Empty (transmitters) */
+#define I2C_SR1_BERR 0x00000100U /*!<Bus Error */
+#define I2C_SR1_ARLO 0x00000200U /*!<Arbitration Lost (master mode) */
+#define I2C_SR1_AF 0x00000400U /*!<Acknowledge Failure */
+#define I2C_SR1_OVR 0x00000800U /*!<Overrun/Underrun */
+#define I2C_SR1_PECERR 0x00001000U /*!<PEC Error in reception */
+#define I2C_SR1_TIMEOUT 0x00004000U /*!<Timeout or Tlow Error */
+#define I2C_SR1_SMBALERT 0x00008000U /*!<SMBus Alert */
+
+/******************* Bit definition for I2C_SR2 register ********************/
+#define I2C_SR2_MSL 0x00000001U /*!<Master/Slave */
+#define I2C_SR2_BUSY 0x00000002U /*!<Bus Busy */
+#define I2C_SR2_TRA 0x00000004U /*!<Transmitter/Receiver */
+#define I2C_SR2_GENCALL 0x00000010U /*!<General Call Address (Slave mode) */
+#define I2C_SR2_SMBDEFAULT 0x00000020U /*!<SMBus Device Default Address (Slave mode) */
+#define I2C_SR2_SMBHOST 0x00000040U /*!<SMBus Host Header (Slave mode) */
+#define I2C_SR2_DUALF 0x00000080U /*!<Dual Flag (Slave mode) */
+#define I2C_SR2_PEC 0x0000FF00U /*!<Packet Error Checking Register */
+
+/******************* Bit definition for I2C_CCR register ********************/
+#define I2C_CCR_CCR 0x00000FFFU /*!<Clock Control Register in Fast/Standard mode (Master mode) */
+#define I2C_CCR_DUTY 0x00004000U /*!<Fast Mode Duty Cycle */
+#define I2C_CCR_FS 0x00008000U /*!<I2C Master Mode Selection */
+
+/****************** Bit definition for I2C_TRISE register *******************/
+#define I2C_TRISE_TRISE 0x0000003FU /*!<Maximum Rise Time in Fast/Standard mode (Master mode) */
+
+/****************** Bit definition for I2C_FLTR register *******************/
+#define I2C_FLTR_DNF 0x0000000FU /*!<Digital Noise Filter */
+#define I2C_FLTR_ANOFF 0x00000010U /*!<Analog Noise Filter OFF */
+
+/******************************************************************************/
+/* */
+/* Independent WATCHDOG */
+/* */
+/******************************************************************************/
+/******************* Bit definition for IWDG_KR register ********************/
+#define IWDG_KR_KEY 0xFFFFU /*!<Key value (write only, read 0000h) */
+
+/******************* Bit definition for IWDG_PR register ********************/
+#define IWDG_PR_PR 0x07U /*!<PR[2:0] (Prescaler divider) */
+#define IWDG_PR_PR_0 0x01U /*!<Bit 0 */
+#define IWDG_PR_PR_1 0x02U /*!<Bit 1 */
+#define IWDG_PR_PR_2 0x04U /*!<Bit 2 */
+
+/******************* Bit definition for IWDG_RLR register *******************/
+#define IWDG_RLR_RL 0x0FFFU /*!<Watchdog counter reload value */
+
+/******************* Bit definition for IWDG_SR register ********************/
+#define IWDG_SR_PVU 0x01U /*!<Watchdog prescaler value update */
+#define IWDG_SR_RVU 0x02U /*!<Watchdog counter reload value update */
+
+
+/******************************************************************************/
+/* */
+/* Power Control */
+/* */
+/******************************************************************************/
+/******************** Bit definition for PWR_CR register ********************/
+#define PWR_CR_LPDS 0x00000001U /*!< Low-Power Deepsleep */
+#define PWR_CR_PDDS 0x00000002U /*!< Power Down Deepsleep */
+#define PWR_CR_CWUF 0x00000004U /*!< Clear Wakeup Flag */
+#define PWR_CR_CSBF 0x00000008U /*!< Clear Standby Flag */
+#define PWR_CR_PVDE 0x00000010U /*!< Power Voltage Detector Enable */
+
+#define PWR_CR_PLS 0x000000E0U /*!< PLS[2:0] bits (PVD Level Selection) */
+#define PWR_CR_PLS_0 0x00000020U /*!< Bit 0 */
+#define PWR_CR_PLS_1 0x00000040U /*!< Bit 1 */
+#define PWR_CR_PLS_2 0x00000080U /*!< Bit 2 */
+
+/*!< PVD level configuration */
+#define PWR_CR_PLS_LEV0 0x00000000U /*!< PVD level 0 */
+#define PWR_CR_PLS_LEV1 0x00000020U /*!< PVD level 1 */
+#define PWR_CR_PLS_LEV2 0x00000040U /*!< PVD level 2 */
+#define PWR_CR_PLS_LEV3 0x00000060U /*!< PVD level 3 */
+#define PWR_CR_PLS_LEV4 0x00000080U /*!< PVD level 4 */
+#define PWR_CR_PLS_LEV5 0x000000A0U /*!< PVD level 5 */
+#define PWR_CR_PLS_LEV6 0x000000C0U /*!< PVD level 6 */
+#define PWR_CR_PLS_LEV7 0x000000E0U /*!< PVD level 7 */
+
+#define PWR_CR_DBP 0x00000100U /*!< Disable Backup Domain write protection */
+#define PWR_CR_FPDS 0x00000200U /*!< Flash power down in Stop mode */
+#define PWR_CR_VOS 0x00004000U /*!< VOS bit (Regulator voltage scaling output selection) */
+
+/* Legacy define */
+#define PWR_CR_PMODE PWR_CR_VOS
+
+/******************* Bit definition for PWR_CSR register ********************/
+#define PWR_CSR_WUF 0x00000001U /*!< Wakeup Flag */
+#define PWR_CSR_SBF 0x00000002U /*!< Standby Flag */
+#define PWR_CSR_PVDO 0x00000004U /*!< PVD Output */
+#define PWR_CSR_BRR 0x00000008U /*!< Backup regulator ready */
+#define PWR_CSR_EWUP 0x00000100U /*!< Enable WKUP pin */
+#define PWR_CSR_BRE 0x00000200U /*!< Backup regulator enable */
+#define PWR_CSR_VOSRDY 0x00004000U /*!< Regulator voltage scaling output selection ready */
+
+/* Legacy define */
+#define PWR_CSR_REGRDY PWR_CSR_VOSRDY
+
+/******************************************************************************/
+/* */
+/* Reset and Clock Control */
+/* */
+/******************************************************************************/
+/******************** Bit definition for RCC_CR register ********************/
+#define RCC_CR_HSION 0x00000001U
+#define RCC_CR_HSIRDY 0x00000002U
+
+#define RCC_CR_HSITRIM 0x000000F8U
+#define RCC_CR_HSITRIM_0 0x00000008U/*!<Bit 0 */
+#define RCC_CR_HSITRIM_1 0x00000010U/*!<Bit 1 */
+#define RCC_CR_HSITRIM_2 0x00000020U/*!<Bit 2 */
+#define RCC_CR_HSITRIM_3 0x00000040U/*!<Bit 3 */
+#define RCC_CR_HSITRIM_4 0x00000080U/*!<Bit 4 */
+
+#define RCC_CR_HSICAL 0x0000FF00U
+#define RCC_CR_HSICAL_0 0x00000100U/*!<Bit 0 */
+#define RCC_CR_HSICAL_1 0x00000200U/*!<Bit 1 */
+#define RCC_CR_HSICAL_2 0x00000400U/*!<Bit 2 */
+#define RCC_CR_HSICAL_3 0x00000800U/*!<Bit 3 */
+#define RCC_CR_HSICAL_4 0x00001000U/*!<Bit 4 */
+#define RCC_CR_HSICAL_5 0x00002000U/*!<Bit 5 */
+#define RCC_CR_HSICAL_6 0x00004000U/*!<Bit 6 */
+#define RCC_CR_HSICAL_7 0x00008000U/*!<Bit 7 */
+
+#define RCC_CR_HSEON 0x00010000U
+#define RCC_CR_HSERDY 0x00020000U
+#define RCC_CR_HSEBYP 0x00040000U
+#define RCC_CR_CSSON 0x00080000U
+#define RCC_CR_PLLON 0x01000000U
+#define RCC_CR_PLLRDY 0x02000000U
+#define RCC_CR_PLLI2SON 0x04000000U
+#define RCC_CR_PLLI2SRDY 0x08000000U
+
+/******************** Bit definition for RCC_PLLCFGR register ***************/
+#define RCC_PLLCFGR_PLLM 0x0000003FU
+#define RCC_PLLCFGR_PLLM_0 0x00000001U
+#define RCC_PLLCFGR_PLLM_1 0x00000002U
+#define RCC_PLLCFGR_PLLM_2 0x00000004U
+#define RCC_PLLCFGR_PLLM_3 0x00000008U
+#define RCC_PLLCFGR_PLLM_4 0x00000010U
+#define RCC_PLLCFGR_PLLM_5 0x00000020U
+
+#define RCC_PLLCFGR_PLLN 0x00007FC0U
+#define RCC_PLLCFGR_PLLN_0 0x00000040U
+#define RCC_PLLCFGR_PLLN_1 0x00000080U
+#define RCC_PLLCFGR_PLLN_2 0x00000100U
+#define RCC_PLLCFGR_PLLN_3 0x00000200U
+#define RCC_PLLCFGR_PLLN_4 0x00000400U
+#define RCC_PLLCFGR_PLLN_5 0x00000800U
+#define RCC_PLLCFGR_PLLN_6 0x00001000U
+#define RCC_PLLCFGR_PLLN_7 0x00002000U
+#define RCC_PLLCFGR_PLLN_8 0x00004000U
+
+#define RCC_PLLCFGR_PLLP 0x00030000U
+#define RCC_PLLCFGR_PLLP_0 0x00010000U
+#define RCC_PLLCFGR_PLLP_1 0x00020000U
+
+#define RCC_PLLCFGR_PLLSRC 0x00400000U
+#define RCC_PLLCFGR_PLLSRC_HSE 0x00400000U
+#define RCC_PLLCFGR_PLLSRC_HSI 0x00000000U
+
+#define RCC_PLLCFGR_PLLQ 0x0F000000U
+#define RCC_PLLCFGR_PLLQ_0 0x01000000U
+#define RCC_PLLCFGR_PLLQ_1 0x02000000U
+#define RCC_PLLCFGR_PLLQ_2 0x04000000U
+#define RCC_PLLCFGR_PLLQ_3 0x08000000U
+
+/******************** Bit definition for RCC_CFGR register ******************/
+/*!< SW configuration */
+#define RCC_CFGR_SW 0x00000003U /*!< SW[1:0] bits (System clock Switch) */
+#define RCC_CFGR_SW_0 0x00000001U /*!< Bit 0 */
+#define RCC_CFGR_SW_1 0x00000002U /*!< Bit 1 */
+
+#define RCC_CFGR_SW_HSI 0x00000000U /*!< HSI selected as system clock */
+#define RCC_CFGR_SW_HSE 0x00000001U /*!< HSE selected as system clock */
+#define RCC_CFGR_SW_PLL 0x00000002U /*!< PLL selected as system clock */
+
+/*!< SWS configuration */
+#define RCC_CFGR_SWS 0x0000000CU /*!< SWS[1:0] bits (System Clock Switch Status) */
+#define RCC_CFGR_SWS_0 0x00000004U /*!< Bit 0 */
+#define RCC_CFGR_SWS_1 0x00000008U /*!< Bit 1 */
+
+#define RCC_CFGR_SWS_HSI 0x00000000U /*!< HSI oscillator used as system clock */
+#define RCC_CFGR_SWS_HSE 0x00000004U /*!< HSE oscillator used as system clock */
+#define RCC_CFGR_SWS_PLL 0x00000008U /*!< PLL used as system clock */
+
+/*!< HPRE configuration */
+#define RCC_CFGR_HPRE 0x000000F0U /*!< HPRE[3:0] bits (AHB prescaler) */
+#define RCC_CFGR_HPRE_0 0x00000010U /*!< Bit 0 */
+#define RCC_CFGR_HPRE_1 0x00000020U /*!< Bit 1 */
+#define RCC_CFGR_HPRE_2 0x00000040U /*!< Bit 2 */
+#define RCC_CFGR_HPRE_3 0x00000080U /*!< Bit 3 */
+
+#define RCC_CFGR_HPRE_DIV1 0x00000000U /*!< SYSCLK not divided */
+#define RCC_CFGR_HPRE_DIV2 0x00000080U /*!< SYSCLK divided by 2 */
+#define RCC_CFGR_HPRE_DIV4 0x00000090U /*!< SYSCLK divided by 4 */
+#define RCC_CFGR_HPRE_DIV8 0x000000A0U /*!< SYSCLK divided by 8 */
+#define RCC_CFGR_HPRE_DIV16 0x000000B0U /*!< SYSCLK divided by 16 */
+#define RCC_CFGR_HPRE_DIV64 0x000000C0U /*!< SYSCLK divided by 64 */
+#define RCC_CFGR_HPRE_DIV128 0x000000D0U /*!< SYSCLK divided by 128 */
+#define RCC_CFGR_HPRE_DIV256 0x000000E0U /*!< SYSCLK divided by 256 */
+#define RCC_CFGR_HPRE_DIV512 0x000000F0U /*!< SYSCLK divided by 512 */
+
+/*!< PPRE1 configuration */
+#define RCC_CFGR_PPRE1 0x00001C00U /*!< PRE1[2:0] bits (APB1 prescaler) */
+#define RCC_CFGR_PPRE1_0 0x00000400U /*!< Bit 0 */
+#define RCC_CFGR_PPRE1_1 0x00000800U /*!< Bit 1 */
+#define RCC_CFGR_PPRE1_2 0x00001000U /*!< Bit 2 */
+
+#define RCC_CFGR_PPRE1_DIV1 0x00000000U /*!< HCLK not divided */
+#define RCC_CFGR_PPRE1_DIV2 0x00001000U /*!< HCLK divided by 2 */
+#define RCC_CFGR_PPRE1_DIV4 0x00001400U /*!< HCLK divided by 4 */
+#define RCC_CFGR_PPRE1_DIV8 0x00001800U /*!< HCLK divided by 8 */
+#define RCC_CFGR_PPRE1_DIV16 0x00001C00U /*!< HCLK divided by 16 */
+
+/*!< PPRE2 configuration */
+#define RCC_CFGR_PPRE2 0x0000E000U /*!< PRE2[2:0] bits (APB2 prescaler) */
+#define RCC_CFGR_PPRE2_0 0x00002000U /*!< Bit 0 */
+#define RCC_CFGR_PPRE2_1 0x00004000U /*!< Bit 1 */
+#define RCC_CFGR_PPRE2_2 0x00008000U /*!< Bit 2 */
+
+#define RCC_CFGR_PPRE2_DIV1 0x00000000U /*!< HCLK not divided */
+#define RCC_CFGR_PPRE2_DIV2 0x00008000U /*!< HCLK divided by 2 */
+#define RCC_CFGR_PPRE2_DIV4 0x0000A000U /*!< HCLK divided by 4 */
+#define RCC_CFGR_PPRE2_DIV8 0x0000C000U /*!< HCLK divided by 8 */
+#define RCC_CFGR_PPRE2_DIV16 0x0000E000U /*!< HCLK divided by 16 */
+
+/*!< RTCPRE configuration */
+#define RCC_CFGR_RTCPRE 0x001F0000U
+#define RCC_CFGR_RTCPRE_0 0x00010000U
+#define RCC_CFGR_RTCPRE_1 0x00020000U
+#define RCC_CFGR_RTCPRE_2 0x00040000U
+#define RCC_CFGR_RTCPRE_3 0x00080000U
+#define RCC_CFGR_RTCPRE_4 0x00100000U
+
+/*!< MCO1 configuration */
+#define RCC_CFGR_MCO1 0x00600000U
+#define RCC_CFGR_MCO1_0 0x00200000U
+#define RCC_CFGR_MCO1_1 0x00400000U
+
+#define RCC_CFGR_I2SSRC 0x00800000U
+
+#define RCC_CFGR_MCO1PRE 0x07000000U
+#define RCC_CFGR_MCO1PRE_0 0x01000000U
+#define RCC_CFGR_MCO1PRE_1 0x02000000U
+#define RCC_CFGR_MCO1PRE_2 0x04000000U
+
+#define RCC_CFGR_MCO2PRE 0x38000000U
+#define RCC_CFGR_MCO2PRE_0 0x08000000U
+#define RCC_CFGR_MCO2PRE_1 0x10000000U
+#define RCC_CFGR_MCO2PRE_2 0x20000000U
+
+#define RCC_CFGR_MCO2 0xC0000000U
+#define RCC_CFGR_MCO2_0 0x40000000U
+#define RCC_CFGR_MCO2_1 0x80000000U
+
+/******************** Bit definition for RCC_CIR register *******************/
+#define RCC_CIR_LSIRDYF 0x00000001U
+#define RCC_CIR_LSERDYF 0x00000002U
+#define RCC_CIR_HSIRDYF 0x00000004U
+#define RCC_CIR_HSERDYF 0x00000008U
+#define RCC_CIR_PLLRDYF 0x00000010U
+#define RCC_CIR_PLLI2SRDYF 0x00000020U
+
+#define RCC_CIR_CSSF 0x00000080U
+#define RCC_CIR_LSIRDYIE 0x00000100U
+#define RCC_CIR_LSERDYIE 0x00000200U
+#define RCC_CIR_HSIRDYIE 0x00000400U
+#define RCC_CIR_HSERDYIE 0x00000800U
+#define RCC_CIR_PLLRDYIE 0x00001000U
+#define RCC_CIR_PLLI2SRDYIE 0x00002000U
+
+#define RCC_CIR_LSIRDYC 0x00010000U
+#define RCC_CIR_LSERDYC 0x00020000U
+#define RCC_CIR_HSIRDYC 0x00040000U
+#define RCC_CIR_HSERDYC 0x00080000U
+#define RCC_CIR_PLLRDYC 0x00100000U
+#define RCC_CIR_PLLI2SRDYC 0x00200000U
+
+#define RCC_CIR_CSSC 0x00800000U
+
+/******************** Bit definition for RCC_AHB1RSTR register **************/
+#define RCC_AHB1RSTR_GPIOARST 0x00000001U
+#define RCC_AHB1RSTR_GPIOBRST 0x00000002U
+#define RCC_AHB1RSTR_GPIOCRST 0x00000004U
+#define RCC_AHB1RSTR_GPIODRST 0x00000008U
+#define RCC_AHB1RSTR_GPIOERST 0x00000010U
+#define RCC_AHB1RSTR_GPIOFRST 0x00000020U
+#define RCC_AHB1RSTR_GPIOGRST 0x00000040U
+#define RCC_AHB1RSTR_GPIOHRST 0x00000080U
+#define RCC_AHB1RSTR_GPIOIRST 0x00000100U
+#define RCC_AHB1RSTR_CRCRST 0x00001000U
+#define RCC_AHB1RSTR_DMA1RST 0x00200000U
+#define RCC_AHB1RSTR_DMA2RST 0x00400000U
+#define RCC_AHB1RSTR_ETHMACRST 0x02000000U
+#define RCC_AHB1RSTR_OTGHRST 0x20000000U
+
+/******************** Bit definition for RCC_AHB2RSTR register **************/
+#define RCC_AHB2RSTR_DCMIRST 0x00000001U
+#define RCC_AHB2RSTR_CRYPRST 0x00000010U
+#define RCC_AHB2RSTR_HASHRST 0x00000020U
+ /* maintained for legacy purpose */
+ #define RCC_AHB2RSTR_HSAHRST RCC_AHB2RSTR_HASHRST
+#define RCC_AHB2RSTR_RNGRST 0x00000040U
+#define RCC_AHB2RSTR_OTGFSRST 0x00000080U
+
+/******************** Bit definition for RCC_AHB3RSTR register **************/
+
+#define RCC_AHB3RSTR_FSMCRST 0x00000001U
+
+/******************** Bit definition for RCC_APB1RSTR register **************/
+#define RCC_APB1RSTR_TIM2RST 0x00000001U
+#define RCC_APB1RSTR_TIM3RST 0x00000002U
+#define RCC_APB1RSTR_TIM4RST 0x00000004U
+#define RCC_APB1RSTR_TIM5RST 0x00000008U
+#define RCC_APB1RSTR_TIM6RST 0x00000010U
+#define RCC_APB1RSTR_TIM7RST 0x00000020U
+#define RCC_APB1RSTR_TIM12RST 0x00000040U
+#define RCC_APB1RSTR_TIM13RST 0x00000080U
+#define RCC_APB1RSTR_TIM14RST 0x00000100U
+#define RCC_APB1RSTR_WWDGRST 0x00000800U
+#define RCC_APB1RSTR_SPI2RST 0x00004000U
+#define RCC_APB1RSTR_SPI3RST 0x00008000U
+#define RCC_APB1RSTR_USART2RST 0x00020000U
+#define RCC_APB1RSTR_USART3RST 0x00040000U
+#define RCC_APB1RSTR_UART4RST 0x00080000U
+#define RCC_APB1RSTR_UART5RST 0x00100000U
+#define RCC_APB1RSTR_I2C1RST 0x00200000U
+#define RCC_APB1RSTR_I2C2RST 0x00400000U
+#define RCC_APB1RSTR_I2C3RST 0x00800000U
+#define RCC_APB1RSTR_CAN1RST 0x02000000U
+#define RCC_APB1RSTR_CAN2RST 0x04000000U
+#define RCC_APB1RSTR_PWRRST 0x10000000U
+#define RCC_APB1RSTR_DACRST 0x20000000U
+
+/******************** Bit definition for RCC_APB2RSTR register **************/
+#define RCC_APB2RSTR_TIM1RST 0x00000001U
+#define RCC_APB2RSTR_TIM8RST 0x00000002U
+#define RCC_APB2RSTR_USART1RST 0x00000010U
+#define RCC_APB2RSTR_USART6RST 0x00000020U
+#define RCC_APB2RSTR_ADCRST 0x00000100U
+#define RCC_APB2RSTR_SDIORST 0x00000800U
+#define RCC_APB2RSTR_SPI1RST 0x00001000U
+#define RCC_APB2RSTR_SYSCFGRST 0x00004000U
+#define RCC_APB2RSTR_TIM9RST 0x00010000U
+#define RCC_APB2RSTR_TIM10RST 0x00020000U
+#define RCC_APB2RSTR_TIM11RST 0x00040000U
+
+/* Old SPI1RST bit definition, maintained for legacy purpose */
+#define RCC_APB2RSTR_SPI1 RCC_APB2RSTR_SPI1RST
+
+/******************** Bit definition for RCC_AHB1ENR register ***************/
+#define RCC_AHB1ENR_GPIOAEN 0x00000001U
+#define RCC_AHB1ENR_GPIOBEN 0x00000002U
+#define RCC_AHB1ENR_GPIOCEN 0x00000004U
+#define RCC_AHB1ENR_GPIODEN 0x00000008U
+#define RCC_AHB1ENR_GPIOEEN 0x00000010U
+#define RCC_AHB1ENR_GPIOFEN 0x00000020U
+#define RCC_AHB1ENR_GPIOGEN 0x00000040U
+#define RCC_AHB1ENR_GPIOHEN 0x00000080U
+#define RCC_AHB1ENR_GPIOIEN 0x00000100U
+#define RCC_AHB1ENR_CRCEN 0x00001000U
+#define RCC_AHB1ENR_BKPSRAMEN 0x00040000U
+#define RCC_AHB1ENR_CCMDATARAMEN 0x00100000U
+#define RCC_AHB1ENR_DMA1EN 0x00200000U
+#define RCC_AHB1ENR_DMA2EN 0x00400000U
+
+#define RCC_AHB1ENR_ETHMACEN 0x02000000U
+#define RCC_AHB1ENR_ETHMACTXEN 0x04000000U
+#define RCC_AHB1ENR_ETHMACRXEN 0x08000000U
+#define RCC_AHB1ENR_ETHMACPTPEN 0x10000000U
+#define RCC_AHB1ENR_OTGHSEN 0x20000000U
+#define RCC_AHB1ENR_OTGHSULPIEN 0x40000000U
+
+/******************** Bit definition for RCC_AHB2ENR register ***************/
+#define RCC_AHB2ENR_DCMIEN 0x00000001U
+#define RCC_AHB2ENR_CRYPEN 0x00000010U
+#define RCC_AHB2ENR_HASHEN 0x00000020U
+#define RCC_AHB2ENR_RNGEN 0x00000040U
+#define RCC_AHB2ENR_OTGFSEN 0x00000080U
+
+/******************** Bit definition for RCC_AHB3ENR register ***************/
+
+#define RCC_AHB3ENR_FSMCEN 0x00000001U
+
+/******************** Bit definition for RCC_APB1ENR register ***************/
+#define RCC_APB1ENR_TIM2EN 0x00000001U
+#define RCC_APB1ENR_TIM3EN 0x00000002U
+#define RCC_APB1ENR_TIM4EN 0x00000004U
+#define RCC_APB1ENR_TIM5EN 0x00000008U
+#define RCC_APB1ENR_TIM6EN 0x00000010U
+#define RCC_APB1ENR_TIM7EN 0x00000020U
+#define RCC_APB1ENR_TIM12EN 0x00000040U
+#define RCC_APB1ENR_TIM13EN 0x00000080U
+#define RCC_APB1ENR_TIM14EN 0x00000100U
+#define RCC_APB1ENR_WWDGEN 0x00000800U
+#define RCC_APB1ENR_SPI2EN 0x00004000U
+#define RCC_APB1ENR_SPI3EN 0x00008000U
+#define RCC_APB1ENR_USART2EN 0x00020000U
+#define RCC_APB1ENR_USART3EN 0x00040000U
+#define RCC_APB1ENR_UART4EN 0x00080000U
+#define RCC_APB1ENR_UART5EN 0x00100000U
+#define RCC_APB1ENR_I2C1EN 0x00200000U
+#define RCC_APB1ENR_I2C2EN 0x00400000U
+#define RCC_APB1ENR_I2C3EN 0x00800000U
+#define RCC_APB1ENR_CAN1EN 0x02000000U
+#define RCC_APB1ENR_CAN2EN 0x04000000U
+#define RCC_APB1ENR_PWREN 0x10000000U
+#define RCC_APB1ENR_DACEN 0x20000000U
+
+/******************** Bit definition for RCC_APB2ENR register ***************/
+#define RCC_APB2ENR_TIM1EN 0x00000001U
+#define RCC_APB2ENR_TIM8EN 0x00000002U
+#define RCC_APB2ENR_USART1EN 0x00000010U
+#define RCC_APB2ENR_USART6EN 0x00000020U
+#define RCC_APB2ENR_ADC1EN 0x00000100U
+#define RCC_APB2ENR_ADC2EN 0x00000200U
+#define RCC_APB2ENR_ADC3EN 0x00000400U
+#define RCC_APB2ENR_SDIOEN 0x00000800U
+#define RCC_APB2ENR_SPI1EN 0x00001000U
+#define RCC_APB2ENR_SYSCFGEN 0x00004000U
+#define RCC_APB2ENR_TIM9EN 0x00010000U
+#define RCC_APB2ENR_TIM10EN 0x00020000U
+#define RCC_APB2ENR_TIM11EN 0x00040000U
+#define RCC_APB2ENR_SPI5EN 0x00100000U
+#define RCC_APB2ENR_SPI6EN 0x00200000U
+
+/******************** Bit definition for RCC_AHB1LPENR register *************/
+#define RCC_AHB1LPENR_GPIOALPEN 0x00000001U
+#define RCC_AHB1LPENR_GPIOBLPEN 0x00000002U
+#define RCC_AHB1LPENR_GPIOCLPEN 0x00000004U
+#define RCC_AHB1LPENR_GPIODLPEN 0x00000008U
+#define RCC_AHB1LPENR_GPIOELPEN 0x00000010U
+#define RCC_AHB1LPENR_GPIOFLPEN 0x00000020U
+#define RCC_AHB1LPENR_GPIOGLPEN 0x00000040U
+#define RCC_AHB1LPENR_GPIOHLPEN 0x00000080U
+#define RCC_AHB1LPENR_GPIOILPEN 0x00000100U
+#define RCC_AHB1LPENR_CRCLPEN 0x00001000U
+#define RCC_AHB1LPENR_FLITFLPEN 0x00008000U
+#define RCC_AHB1LPENR_SRAM1LPEN 0x00010000U
+#define RCC_AHB1LPENR_SRAM2LPEN 0x00020000U
+#define RCC_AHB1LPENR_BKPSRAMLPEN 0x00040000U
+#define RCC_AHB1LPENR_DMA1LPEN 0x00200000U
+#define RCC_AHB1LPENR_DMA2LPEN 0x00400000U
+#define RCC_AHB1LPENR_ETHMACLPEN 0x02000000U
+#define RCC_AHB1LPENR_ETHMACTXLPEN 0x04000000U
+#define RCC_AHB1LPENR_ETHMACRXLPEN 0x08000000U
+#define RCC_AHB1LPENR_ETHMACPTPLPEN 0x10000000U
+#define RCC_AHB1LPENR_OTGHSLPEN 0x20000000U
+#define RCC_AHB1LPENR_OTGHSULPILPEN 0x40000000U
+
+/******************** Bit definition for RCC_AHB2LPENR register *************/
+#define RCC_AHB2LPENR_DCMILPEN 0x00000001U
+#define RCC_AHB2LPENR_CRYPLPEN 0x00000010U
+#define RCC_AHB2LPENR_HASHLPEN 0x00000020U
+#define RCC_AHB2LPENR_RNGLPEN 0x00000040U
+#define RCC_AHB2LPENR_OTGFSLPEN 0x00000080U
+
+/******************** Bit definition for RCC_AHB3LPENR register *************/
+
+#define RCC_AHB3LPENR_FSMCLPEN 0x00000001U
+
+/******************** Bit definition for RCC_APB1LPENR register *************/
+#define RCC_APB1LPENR_TIM2LPEN 0x00000001U
+#define RCC_APB1LPENR_TIM3LPEN 0x00000002U
+#define RCC_APB1LPENR_TIM4LPEN 0x00000004U
+#define RCC_APB1LPENR_TIM5LPEN 0x00000008U
+#define RCC_APB1LPENR_TIM6LPEN 0x00000010U
+#define RCC_APB1LPENR_TIM7LPEN 0x00000020U
+#define RCC_APB1LPENR_TIM12LPEN 0x00000040U
+#define RCC_APB1LPENR_TIM13LPEN 0x00000080U
+#define RCC_APB1LPENR_TIM14LPEN 0x00000100U
+#define RCC_APB1LPENR_WWDGLPEN 0x00000800U
+#define RCC_APB1LPENR_SPI2LPEN 0x00004000U
+#define RCC_APB1LPENR_SPI3LPEN 0x00008000U
+#define RCC_APB1LPENR_USART2LPEN 0x00020000U
+#define RCC_APB1LPENR_USART3LPEN 0x00040000U
+#define RCC_APB1LPENR_UART4LPEN 0x00080000U
+#define RCC_APB1LPENR_UART5LPEN 0x00100000U
+#define RCC_APB1LPENR_I2C1LPEN 0x00200000U
+#define RCC_APB1LPENR_I2C2LPEN 0x00400000U
+#define RCC_APB1LPENR_I2C3LPEN 0x00800000U
+#define RCC_APB1LPENR_CAN1LPEN 0x02000000U
+#define RCC_APB1LPENR_CAN2LPEN 0x04000000U
+#define RCC_APB1LPENR_PWRLPEN 0x10000000U
+#define RCC_APB1LPENR_DACLPEN 0x20000000U
+
+/******************** Bit definition for RCC_APB2LPENR register *************/
+#define RCC_APB2LPENR_TIM1LPEN 0x00000001U
+#define RCC_APB2LPENR_TIM8LPEN 0x00000002U
+#define RCC_APB2LPENR_USART1LPEN 0x00000010U
+#define RCC_APB2LPENR_USART6LPEN 0x00000020U
+#define RCC_APB2LPENR_ADC1LPEN 0x00000100U
+#define RCC_APB2LPENR_ADC2LPEN 0x00000200U
+#define RCC_APB2LPENR_ADC3LPEN 0x00000400U
+#define RCC_APB2LPENR_SDIOLPEN 0x00000800U
+#define RCC_APB2LPENR_SPI1LPEN 0x00001000U
+#define RCC_APB2LPENR_SYSCFGLPEN 0x00004000U
+#define RCC_APB2LPENR_TIM9LPEN 0x00010000U
+#define RCC_APB2LPENR_TIM10LPEN 0x00020000U
+#define RCC_APB2LPENR_TIM11LPEN 0x00040000U
+
+/******************** Bit definition for RCC_BDCR register ******************/
+#define RCC_BDCR_LSEON 0x00000001U
+#define RCC_BDCR_LSERDY 0x00000002U
+#define RCC_BDCR_LSEBYP 0x00000004U
+
+#define RCC_BDCR_RTCSEL 0x00000300U
+#define RCC_BDCR_RTCSEL_0 0x00000100U
+#define RCC_BDCR_RTCSEL_1 0x00000200U
+
+#define RCC_BDCR_RTCEN 0x00008000U
+#define RCC_BDCR_BDRST 0x00010000U
+
+/******************** Bit definition for RCC_CSR register *******************/
+#define RCC_CSR_LSION 0x00000001U
+#define RCC_CSR_LSIRDY 0x00000002U
+#define RCC_CSR_RMVF 0x01000000U
+#define RCC_CSR_BORRSTF 0x02000000U
+#define RCC_CSR_PADRSTF 0x04000000U
+#define RCC_CSR_PORRSTF 0x08000000U
+#define RCC_CSR_SFTRSTF 0x10000000U
+#define RCC_CSR_WDGRSTF 0x20000000U
+#define RCC_CSR_WWDGRSTF 0x40000000U
+#define RCC_CSR_LPWRRSTF 0x80000000U
+
+/******************** Bit definition for RCC_SSCGR register *****************/
+#define RCC_SSCGR_MODPER 0x00001FFFU
+#define RCC_SSCGR_INCSTEP 0x0FFFE000U
+#define RCC_SSCGR_SPREADSEL 0x40000000U
+#define RCC_SSCGR_SSCGEN 0x80000000U
+
+/******************** Bit definition for RCC_PLLI2SCFGR register ************/
+#define RCC_PLLI2SCFGR_PLLI2SN 0x00007FC0U
+#define RCC_PLLI2SCFGR_PLLI2SN_0 0x00000040U
+#define RCC_PLLI2SCFGR_PLLI2SN_1 0x00000080U
+#define RCC_PLLI2SCFGR_PLLI2SN_2 0x00000100U
+#define RCC_PLLI2SCFGR_PLLI2SN_3 0x00000200U
+#define RCC_PLLI2SCFGR_PLLI2SN_4 0x00000400U
+#define RCC_PLLI2SCFGR_PLLI2SN_5 0x00000800U
+#define RCC_PLLI2SCFGR_PLLI2SN_6 0x00001000U
+#define RCC_PLLI2SCFGR_PLLI2SN_7 0x00002000U
+#define RCC_PLLI2SCFGR_PLLI2SN_8 0x00004000U
+
+#define RCC_PLLI2SCFGR_PLLI2SR 0x70000000U
+#define RCC_PLLI2SCFGR_PLLI2SR_0 0x10000000U
+#define RCC_PLLI2SCFGR_PLLI2SR_1 0x20000000U
+#define RCC_PLLI2SCFGR_PLLI2SR_2 0x40000000U
+
+/******************************************************************************/
+/* */
+/* RNG */
+/* */
+/******************************************************************************/
+/******************** Bits definition for RNG_CR register *******************/
+#define RNG_CR_RNGEN 0x00000004U
+#define RNG_CR_IE 0x00000008U
+
+/******************** Bits definition for RNG_SR register *******************/
+#define RNG_SR_DRDY 0x00000001U
+#define RNG_SR_CECS 0x00000002U
+#define RNG_SR_SECS 0x00000004U
+#define RNG_SR_CEIS 0x00000020U
+#define RNG_SR_SEIS 0x00000040U
+
+/******************************************************************************/
+/* */
+/* Real-Time Clock (RTC) */
+/* */
+/******************************************************************************/
+/******************** Bits definition for RTC_TR register *******************/
+#define RTC_TR_PM 0x00400000U
+#define RTC_TR_HT 0x00300000U
+#define RTC_TR_HT_0 0x00100000U
+#define RTC_TR_HT_1 0x00200000U
+#define RTC_TR_HU 0x000F0000U
+#define RTC_TR_HU_0 0x00010000U
+#define RTC_TR_HU_1 0x00020000U
+#define RTC_TR_HU_2 0x00040000U
+#define RTC_TR_HU_3 0x00080000U
+#define RTC_TR_MNT 0x00007000U
+#define RTC_TR_MNT_0 0x00001000U
+#define RTC_TR_MNT_1 0x00002000U
+#define RTC_TR_MNT_2 0x00004000U
+#define RTC_TR_MNU 0x00000F00U
+#define RTC_TR_MNU_0 0x00000100U
+#define RTC_TR_MNU_1 0x00000200U
+#define RTC_TR_MNU_2 0x00000400U
+#define RTC_TR_MNU_3 0x00000800U
+#define RTC_TR_ST 0x00000070U
+#define RTC_TR_ST_0 0x00000010U
+#define RTC_TR_ST_1 0x00000020U
+#define RTC_TR_ST_2 0x00000040U
+#define RTC_TR_SU 0x0000000FU
+#define RTC_TR_SU_0 0x00000001U
+#define RTC_TR_SU_1 0x00000002U
+#define RTC_TR_SU_2 0x00000004U
+#define RTC_TR_SU_3 0x00000008U
+
+/******************** Bits definition for RTC_DR register *******************/
+#define RTC_DR_YT 0x00F00000U
+#define RTC_DR_YT_0 0x00100000U
+#define RTC_DR_YT_1 0x00200000U
+#define RTC_DR_YT_2 0x00400000U
+#define RTC_DR_YT_3 0x00800000U
+#define RTC_DR_YU 0x000F0000U
+#define RTC_DR_YU_0 0x00010000U
+#define RTC_DR_YU_1 0x00020000U
+#define RTC_DR_YU_2 0x00040000U
+#define RTC_DR_YU_3 0x00080000U
+#define RTC_DR_WDU 0x0000E000U
+#define RTC_DR_WDU_0 0x00002000U
+#define RTC_DR_WDU_1 0x00004000U
+#define RTC_DR_WDU_2 0x00008000U
+#define RTC_DR_MT 0x00001000U
+#define RTC_DR_MU 0x00000F00U
+#define RTC_DR_MU_0 0x00000100U
+#define RTC_DR_MU_1 0x00000200U
+#define RTC_DR_MU_2 0x00000400U
+#define RTC_DR_MU_3 0x00000800U
+#define RTC_DR_DT 0x00000030U
+#define RTC_DR_DT_0 0x00000010U
+#define RTC_DR_DT_1 0x00000020U
+#define RTC_DR_DU 0x0000000FU
+#define RTC_DR_DU_0 0x00000001U
+#define RTC_DR_DU_1 0x00000002U
+#define RTC_DR_DU_2 0x00000004U
+#define RTC_DR_DU_3 0x00000008U
+
+/******************** Bits definition for RTC_CR register *******************/
+#define RTC_CR_COE 0x00800000U
+#define RTC_CR_OSEL 0x00600000U
+#define RTC_CR_OSEL_0 0x00200000U
+#define RTC_CR_OSEL_1 0x00400000U
+#define RTC_CR_POL 0x00100000U
+#define RTC_CR_COSEL 0x00080000U
+#define RTC_CR_BCK 0x00040000U
+#define RTC_CR_SUB1H 0x00020000U
+#define RTC_CR_ADD1H 0x00010000U
+#define RTC_CR_TSIE 0x00008000U
+#define RTC_CR_WUTIE 0x00004000U
+#define RTC_CR_ALRBIE 0x00002000U
+#define RTC_CR_ALRAIE 0x00001000U
+#define RTC_CR_TSE 0x00000800U
+#define RTC_CR_WUTE 0x00000400U
+#define RTC_CR_ALRBE 0x00000200U
+#define RTC_CR_ALRAE 0x00000100U
+#define RTC_CR_DCE 0x00000080U
+#define RTC_CR_FMT 0x00000040U
+#define RTC_CR_BYPSHAD 0x00000020U
+#define RTC_CR_REFCKON 0x00000010U
+#define RTC_CR_TSEDGE 0x00000008U
+#define RTC_CR_WUCKSEL 0x00000007U
+#define RTC_CR_WUCKSEL_0 0x00000001U
+#define RTC_CR_WUCKSEL_1 0x00000002U
+#define RTC_CR_WUCKSEL_2 0x00000004U
+
+/******************** Bits definition for RTC_ISR register ******************/
+#define RTC_ISR_RECALPF 0x00010000U
+#define RTC_ISR_TAMP1F 0x00002000U
+#define RTC_ISR_TAMP2F 0x00004000U
+#define RTC_ISR_TSOVF 0x00001000U
+#define RTC_ISR_TSF 0x00000800U
+#define RTC_ISR_WUTF 0x00000400U
+#define RTC_ISR_ALRBF 0x00000200U
+#define RTC_ISR_ALRAF 0x00000100U
+#define RTC_ISR_INIT 0x00000080U
+#define RTC_ISR_INITF 0x00000040U
+#define RTC_ISR_RSF 0x00000020U
+#define RTC_ISR_INITS 0x00000010U
+#define RTC_ISR_SHPF 0x00000008U
+#define RTC_ISR_WUTWF 0x00000004U
+#define RTC_ISR_ALRBWF 0x00000002U
+#define RTC_ISR_ALRAWF 0x00000001U
+
+/******************** Bits definition for RTC_PRER register *****************/
+#define RTC_PRER_PREDIV_A 0x007F0000U
+#define RTC_PRER_PREDIV_S 0x00007FFFU
+
+/******************** Bits definition for RTC_WUTR register *****************/
+#define RTC_WUTR_WUT 0x0000FFFFU
+
+/******************** Bits definition for RTC_CALIBR register ***************/
+#define RTC_CALIBR_DCS 0x00000080U
+#define RTC_CALIBR_DC 0x0000001FU
+
+/******************** Bits definition for RTC_ALRMAR register ***************/
+#define RTC_ALRMAR_MSK4 0x80000000U
+#define RTC_ALRMAR_WDSEL 0x40000000U
+#define RTC_ALRMAR_DT 0x30000000U
+#define RTC_ALRMAR_DT_0 0x10000000U
+#define RTC_ALRMAR_DT_1 0x20000000U
+#define RTC_ALRMAR_DU 0x0F000000U
+#define RTC_ALRMAR_DU_0 0x01000000U
+#define RTC_ALRMAR_DU_1 0x02000000U
+#define RTC_ALRMAR_DU_2 0x04000000U
+#define RTC_ALRMAR_DU_3 0x08000000U
+#define RTC_ALRMAR_MSK3 0x00800000U
+#define RTC_ALRMAR_PM 0x00400000U
+#define RTC_ALRMAR_HT 0x00300000U
+#define RTC_ALRMAR_HT_0 0x00100000U
+#define RTC_ALRMAR_HT_1 0x00200000U
+#define RTC_ALRMAR_HU 0x000F0000U
+#define RTC_ALRMAR_HU_0 0x00010000U
+#define RTC_ALRMAR_HU_1 0x00020000U
+#define RTC_ALRMAR_HU_2 0x00040000U
+#define RTC_ALRMAR_HU_3 0x00080000U
+#define RTC_ALRMAR_MSK2 0x00008000U
+#define RTC_ALRMAR_MNT 0x00007000U
+#define RTC_ALRMAR_MNT_0 0x00001000U
+#define RTC_ALRMAR_MNT_1 0x00002000U
+#define RTC_ALRMAR_MNT_2 0x00004000U
+#define RTC_ALRMAR_MNU 0x00000F00U
+#define RTC_ALRMAR_MNU_0 0x00000100U
+#define RTC_ALRMAR_MNU_1 0x00000200U
+#define RTC_ALRMAR_MNU_2 0x00000400U
+#define RTC_ALRMAR_MNU_3 0x00000800U
+#define RTC_ALRMAR_MSK1 0x00000080U
+#define RTC_ALRMAR_ST 0x00000070U
+#define RTC_ALRMAR_ST_0 0x00000010U
+#define RTC_ALRMAR_ST_1 0x00000020U
+#define RTC_ALRMAR_ST_2 0x00000040U
+#define RTC_ALRMAR_SU 0x0000000FU
+#define RTC_ALRMAR_SU_0 0x00000001U
+#define RTC_ALRMAR_SU_1 0x00000002U
+#define RTC_ALRMAR_SU_2 0x00000004U
+#define RTC_ALRMAR_SU_3 0x00000008U
+
+/******************** Bits definition for RTC_ALRMBR register ***************/
+#define RTC_ALRMBR_MSK4 0x80000000U
+#define RTC_ALRMBR_WDSEL 0x40000000U
+#define RTC_ALRMBR_DT 0x30000000U
+#define RTC_ALRMBR_DT_0 0x10000000U
+#define RTC_ALRMBR_DT_1 0x20000000U
+#define RTC_ALRMBR_DU 0x0F000000U
+#define RTC_ALRMBR_DU_0 0x01000000U
+#define RTC_ALRMBR_DU_1 0x02000000U
+#define RTC_ALRMBR_DU_2 0x04000000U
+#define RTC_ALRMBR_DU_3 0x08000000U
+#define RTC_ALRMBR_MSK3 0x00800000U
+#define RTC_ALRMBR_PM 0x00400000U
+#define RTC_ALRMBR_HT 0x00300000U
+#define RTC_ALRMBR_HT_0 0x00100000U
+#define RTC_ALRMBR_HT_1 0x00200000U
+#define RTC_ALRMBR_HU 0x000F0000U
+#define RTC_ALRMBR_HU_0 0x00010000U
+#define RTC_ALRMBR_HU_1 0x00020000U
+#define RTC_ALRMBR_HU_2 0x00040000U
+#define RTC_ALRMBR_HU_3 0x00080000U
+#define RTC_ALRMBR_MSK2 0x00008000U
+#define RTC_ALRMBR_MNT 0x00007000U
+#define RTC_ALRMBR_MNT_0 0x00001000U
+#define RTC_ALRMBR_MNT_1 0x00002000U
+#define RTC_ALRMBR_MNT_2 0x00004000U
+#define RTC_ALRMBR_MNU 0x00000F00U
+#define RTC_ALRMBR_MNU_0 0x00000100U
+#define RTC_ALRMBR_MNU_1 0x00000200U
+#define RTC_ALRMBR_MNU_2 0x00000400U
+#define RTC_ALRMBR_MNU_3 0x00000800U
+#define RTC_ALRMBR_MSK1 0x00000080U
+#define RTC_ALRMBR_ST 0x00000070U
+#define RTC_ALRMBR_ST_0 0x00000010U
+#define RTC_ALRMBR_ST_1 0x00000020U
+#define RTC_ALRMBR_ST_2 0x00000040U
+#define RTC_ALRMBR_SU 0x0000000FU
+#define RTC_ALRMBR_SU_0 0x00000001U
+#define RTC_ALRMBR_SU_1 0x00000002U
+#define RTC_ALRMBR_SU_2 0x00000004U
+#define RTC_ALRMBR_SU_3 0x00000008U
+
+/******************** Bits definition for RTC_WPR register ******************/
+#define RTC_WPR_KEY 0x000000FFU
+
+/******************** Bits definition for RTC_SSR register ******************/
+#define RTC_SSR_SS 0x0000FFFFU
+
+/******************** Bits definition for RTC_SHIFTR register ***************/
+#define RTC_SHIFTR_SUBFS 0x00007FFFU
+#define RTC_SHIFTR_ADD1S 0x80000000U
+
+/******************** Bits definition for RTC_TSTR register *****************/
+#define RTC_TSTR_PM 0x00400000U
+#define RTC_TSTR_HT 0x00300000U
+#define RTC_TSTR_HT_0 0x00100000U
+#define RTC_TSTR_HT_1 0x00200000U
+#define RTC_TSTR_HU 0x000F0000U
+#define RTC_TSTR_HU_0 0x00010000U
+#define RTC_TSTR_HU_1 0x00020000U
+#define RTC_TSTR_HU_2 0x00040000U
+#define RTC_TSTR_HU_3 0x00080000U
+#define RTC_TSTR_MNT 0x00007000U
+#define RTC_TSTR_MNT_0 0x00001000U
+#define RTC_TSTR_MNT_1 0x00002000U
+#define RTC_TSTR_MNT_2 0x00004000U
+#define RTC_TSTR_MNU 0x00000F00U
+#define RTC_TSTR_MNU_0 0x00000100U
+#define RTC_TSTR_MNU_1 0x00000200U
+#define RTC_TSTR_MNU_2 0x00000400U
+#define RTC_TSTR_MNU_3 0x00000800U
+#define RTC_TSTR_ST 0x00000070U
+#define RTC_TSTR_ST_0 0x00000010U
+#define RTC_TSTR_ST_1 0x00000020U
+#define RTC_TSTR_ST_2 0x00000040U
+#define RTC_TSTR_SU 0x0000000FU
+#define RTC_TSTR_SU_0 0x00000001U
+#define RTC_TSTR_SU_1 0x00000002U
+#define RTC_TSTR_SU_2 0x00000004U
+#define RTC_TSTR_SU_3 0x00000008U
+
+/******************** Bits definition for RTC_TSDR register *****************/
+#define RTC_TSDR_WDU 0x0000E000U
+#define RTC_TSDR_WDU_0 0x00002000U
+#define RTC_TSDR_WDU_1 0x00004000U
+#define RTC_TSDR_WDU_2 0x00008000U
+#define RTC_TSDR_MT 0x00001000U
+#define RTC_TSDR_MU 0x00000F00U
+#define RTC_TSDR_MU_0 0x00000100U
+#define RTC_TSDR_MU_1 0x00000200U
+#define RTC_TSDR_MU_2 0x00000400U
+#define RTC_TSDR_MU_3 0x00000800U
+#define RTC_TSDR_DT 0x00000030U
+#define RTC_TSDR_DT_0 0x00000010U
+#define RTC_TSDR_DT_1 0x00000020U
+#define RTC_TSDR_DU 0x0000000FU
+#define RTC_TSDR_DU_0 0x00000001U
+#define RTC_TSDR_DU_1 0x00000002U
+#define RTC_TSDR_DU_2 0x00000004U
+#define RTC_TSDR_DU_3 0x00000008U
+
+/******************** Bits definition for RTC_TSSSR register ****************/
+#define RTC_TSSSR_SS 0x0000FFFFU
+
+/******************** Bits definition for RTC_CAL register *****************/
+#define RTC_CALR_CALP 0x00008000U
+#define RTC_CALR_CALW8 0x00004000U
+#define RTC_CALR_CALW16 0x00002000U
+#define RTC_CALR_CALM 0x000001FFU
+#define RTC_CALR_CALM_0 0x00000001U
+#define RTC_CALR_CALM_1 0x00000002U
+#define RTC_CALR_CALM_2 0x00000004U
+#define RTC_CALR_CALM_3 0x00000008U
+#define RTC_CALR_CALM_4 0x00000010U
+#define RTC_CALR_CALM_5 0x00000020U
+#define RTC_CALR_CALM_6 0x00000040U
+#define RTC_CALR_CALM_7 0x00000080U
+#define RTC_CALR_CALM_8 0x00000100U
+
+/******************** Bits definition for RTC_TAFCR register ****************/
+#define RTC_TAFCR_ALARMOUTTYPE 0x00040000U
+#define RTC_TAFCR_TSINSEL 0x00020000U
+#define RTC_TAFCR_TAMPINSEL 0x00010000U
+#define RTC_TAFCR_TAMPPUDIS 0x00008000U
+#define RTC_TAFCR_TAMPPRCH 0x00006000U
+#define RTC_TAFCR_TAMPPRCH_0 0x00002000U
+#define RTC_TAFCR_TAMPPRCH_1 0x00004000U
+#define RTC_TAFCR_TAMPFLT 0x00001800U
+#define RTC_TAFCR_TAMPFLT_0 0x00000800U
+#define RTC_TAFCR_TAMPFLT_1 0x00001000U
+#define RTC_TAFCR_TAMPFREQ 0x00000700U
+#define RTC_TAFCR_TAMPFREQ_0 0x00000100U
+#define RTC_TAFCR_TAMPFREQ_1 0x00000200U
+#define RTC_TAFCR_TAMPFREQ_2 0x00000400U
+#define RTC_TAFCR_TAMPTS 0x00000080U
+#define RTC_TAFCR_TAMP2TRG 0x00000010U
+#define RTC_TAFCR_TAMP2E 0x00000008U
+#define RTC_TAFCR_TAMPIE 0x00000004U
+#define RTC_TAFCR_TAMP1TRG 0x00000002U
+#define RTC_TAFCR_TAMP1E 0x00000001U
+
+/******************** Bits definition for RTC_ALRMASSR register *************/
+#define RTC_ALRMASSR_MASKSS 0x0F000000U
+#define RTC_ALRMASSR_MASKSS_0 0x01000000U
+#define RTC_ALRMASSR_MASKSS_1 0x02000000U
+#define RTC_ALRMASSR_MASKSS_2 0x04000000U
+#define RTC_ALRMASSR_MASKSS_3 0x08000000U
+#define RTC_ALRMASSR_SS 0x00007FFFU
+
+/******************** Bits definition for RTC_ALRMBSSR register *************/
+#define RTC_ALRMBSSR_MASKSS 0x0F000000U
+#define RTC_ALRMBSSR_MASKSS_0 0x01000000U
+#define RTC_ALRMBSSR_MASKSS_1 0x02000000U
+#define RTC_ALRMBSSR_MASKSS_2 0x04000000U
+#define RTC_ALRMBSSR_MASKSS_3 0x08000000U
+#define RTC_ALRMBSSR_SS 0x00007FFFU
+
+/******************** Bits definition for RTC_BKP0R register ****************/
+#define RTC_BKP0R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP1R register ****************/
+#define RTC_BKP1R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP2R register ****************/
+#define RTC_BKP2R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP3R register ****************/
+#define RTC_BKP3R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP4R register ****************/
+#define RTC_BKP4R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP5R register ****************/
+#define RTC_BKP5R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP6R register ****************/
+#define RTC_BKP6R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP7R register ****************/
+#define RTC_BKP7R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP8R register ****************/
+#define RTC_BKP8R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP9R register ****************/
+#define RTC_BKP9R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP10R register ***************/
+#define RTC_BKP10R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP11R register ***************/
+#define RTC_BKP11R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP12R register ***************/
+#define RTC_BKP12R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP13R register ***************/
+#define RTC_BKP13R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP14R register ***************/
+#define RTC_BKP14R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP15R register ***************/
+#define RTC_BKP15R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP16R register ***************/
+#define RTC_BKP16R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP17R register ***************/
+#define RTC_BKP17R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP18R register ***************/
+#define RTC_BKP18R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP19R register ***************/
+#define RTC_BKP19R 0xFFFFFFFFU
+
+
+
+/******************************************************************************/
+/* */
+/* SD host Interface */
+/* */
+/******************************************************************************/
+/****************** Bit definition for SDIO_POWER register ******************/
+#define SDIO_POWER_PWRCTRL 0x03U /*!<PWRCTRL[1:0] bits (Power supply control bits) */
+#define SDIO_POWER_PWRCTRL_0 0x01U /*!<Bit 0 */
+#define SDIO_POWER_PWRCTRL_1 0x02U /*!<Bit 1 */
+
+/****************** Bit definition for SDIO_CLKCR register ******************/
+#define SDIO_CLKCR_CLKDIV 0x00FFU /*!<Clock divide factor */
+#define SDIO_CLKCR_CLKEN 0x0100U /*!<Clock enable bit */
+#define SDIO_CLKCR_PWRSAV 0x0200U /*!<Power saving configuration bit */
+#define SDIO_CLKCR_BYPASS 0x0400U /*!<Clock divider bypass enable bit */
+
+#define SDIO_CLKCR_WIDBUS 0x1800U /*!<WIDBUS[1:0] bits (Wide bus mode enable bit) */
+#define SDIO_CLKCR_WIDBUS_0 0x0800U /*!<Bit 0 */
+#define SDIO_CLKCR_WIDBUS_1 0x1000U /*!<Bit 1 */
+
+#define SDIO_CLKCR_NEGEDGE 0x2000U /*!<SDIO_CK dephasing selection bit */
+#define SDIO_CLKCR_HWFC_EN 0x4000U /*!<HW Flow Control enable */
+
+/******************* Bit definition for SDIO_ARG register *******************/
+#define SDIO_ARG_CMDARG 0xFFFFFFFFU /*!<Command argument */
+
+/******************* Bit definition for SDIO_CMD register *******************/
+#define SDIO_CMD_CMDINDEX 0x003FU /*!<Command Index */
+
+#define SDIO_CMD_WAITRESP 0x00C0U /*!<WAITRESP[1:0] bits (Wait for response bits) */
+#define SDIO_CMD_WAITRESP_0 0x0040U /*!< Bit 0 */
+#define SDIO_CMD_WAITRESP_1 0x0080U /*!< Bit 1 */
+
+#define SDIO_CMD_WAITINT 0x0100U /*!<CPSM Waits for Interrupt Request */
+#define SDIO_CMD_WAITPEND 0x0200U /*!<CPSM Waits for ends of data transfer (CmdPend internal signal) */
+#define SDIO_CMD_CPSMEN 0x0400U /*!<Command path state machine (CPSM) Enable bit */
+#define SDIO_CMD_SDIOSUSPEND 0x0800U /*!<SD I/O suspend command */
+#define SDIO_CMD_ENCMDCOMPL 0x1000U /*!<Enable CMD completion */
+#define SDIO_CMD_NIEN 0x2000U /*!<Not Interrupt Enable */
+#define SDIO_CMD_CEATACMD 0x4000U /*!<CE-ATA command */
+
+/***************** Bit definition for SDIO_RESPCMD register *****************/
+#define SDIO_RESPCMD_RESPCMD 0x3FU /*!<Response command index */
+
+/****************** Bit definition for SDIO_RESP0 register ******************/
+#define SDIO_RESP0_CARDSTATUS0 0xFFFFFFFFU /*!<Card Status */
+
+/****************** Bit definition for SDIO_RESP1 register ******************/
+#define SDIO_RESP1_CARDSTATUS1 0xFFFFFFFFU /*!<Card Status */
+
+/****************** Bit definition for SDIO_RESP2 register ******************/
+#define SDIO_RESP2_CARDSTATUS2 0xFFFFFFFFU /*!<Card Status */
+
+/****************** Bit definition for SDIO_RESP3 register ******************/
+#define SDIO_RESP3_CARDSTATUS3 0xFFFFFFFFU /*!<Card Status */
+
+/****************** Bit definition for SDIO_RESP4 register ******************/
+#define SDIO_RESP4_CARDSTATUS4 0xFFFFFFFFU /*!<Card Status */
+
+/****************** Bit definition for SDIO_DTIMER register *****************/
+#define SDIO_DTIMER_DATATIME 0xFFFFFFFFU /*!<Data timeout period. */
+
+/****************** Bit definition for SDIO_DLEN register *******************/
+#define SDIO_DLEN_DATALENGTH 0x01FFFFFFU /*!<Data length value */
+
+/****************** Bit definition for SDIO_DCTRL register ******************/
+#define SDIO_DCTRL_DTEN 0x0001U /*!<Data transfer enabled bit */
+#define SDIO_DCTRL_DTDIR 0x0002U /*!<Data transfer direction selection */
+#define SDIO_DCTRL_DTMODE 0x0004U /*!<Data transfer mode selection */
+#define SDIO_DCTRL_DMAEN 0x0008U /*!<DMA enabled bit */
+
+#define SDIO_DCTRL_DBLOCKSIZE 0x00F0U /*!<DBLOCKSIZE[3:0] bits (Data block size) */
+#define SDIO_DCTRL_DBLOCKSIZE_0 0x0010U /*!<Bit 0 */
+#define SDIO_DCTRL_DBLOCKSIZE_1 0x0020U /*!<Bit 1 */
+#define SDIO_DCTRL_DBLOCKSIZE_2 0x0040U /*!<Bit 2 */
+#define SDIO_DCTRL_DBLOCKSIZE_3 0x0080U /*!<Bit 3 */
+
+#define SDIO_DCTRL_RWSTART 0x0100U /*!<Read wait start */
+#define SDIO_DCTRL_RWSTOP 0x0200U /*!<Read wait stop */
+#define SDIO_DCTRL_RWMOD 0x0400U /*!<Read wait mode */
+#define SDIO_DCTRL_SDIOEN 0x0800U /*!<SD I/O enable functions */
+
+/****************** Bit definition for SDIO_DCOUNT register *****************/
+#define SDIO_DCOUNT_DATACOUNT 0x01FFFFFFU /*!<Data count value */
+
+/****************** Bit definition for SDIO_STA register ********************/
+#define SDIO_STA_CCRCFAIL 0x00000001U /*!<Command response received (CRC check failed) */
+#define SDIO_STA_DCRCFAIL 0x00000002U /*!<Data block sent/received (CRC check failed) */
+#define SDIO_STA_CTIMEOUT 0x00000004U /*!<Command response timeout */
+#define SDIO_STA_DTIMEOUT 0x00000008U /*!<Data timeout */
+#define SDIO_STA_TXUNDERR 0x00000010U /*!<Transmit FIFO underrun error */
+#define SDIO_STA_RXOVERR 0x00000020U /*!<Received FIFO overrun error */
+#define SDIO_STA_CMDREND 0x00000040U /*!<Command response received (CRC check passed) */
+#define SDIO_STA_CMDSENT 0x00000080U /*!<Command sent (no response required) */
+#define SDIO_STA_DATAEND 0x00000100U /*!<Data end (data counter, SDIDCOUNT, is zero) */
+#define SDIO_STA_STBITERR 0x00000200U /*!<Start bit not detected on all data signals in wide bus mode */
+#define SDIO_STA_DBCKEND 0x00000400U /*!<Data block sent/received (CRC check passed) */
+#define SDIO_STA_CMDACT 0x00000800U /*!<Command transfer in progress */
+#define SDIO_STA_TXACT 0x00001000U /*!<Data transmit in progress */
+#define SDIO_STA_RXACT 0x00002000U /*!<Data receive in progress */
+#define SDIO_STA_TXFIFOHE 0x00004000U /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
+#define SDIO_STA_RXFIFOHF 0x00008000U /*!<Receive FIFO Half Full: there are at least 8 words in the FIFO */
+#define SDIO_STA_TXFIFOF 0x00010000U /*!<Transmit FIFO full */
+#define SDIO_STA_RXFIFOF 0x00020000U /*!<Receive FIFO full */
+#define SDIO_STA_TXFIFOE 0x00040000U /*!<Transmit FIFO empty */
+#define SDIO_STA_RXFIFOE 0x00080000U /*!<Receive FIFO empty */
+#define SDIO_STA_TXDAVL 0x00100000U /*!<Data available in transmit FIFO */
+#define SDIO_STA_RXDAVL 0x00200000U /*!<Data available in receive FIFO */
+#define SDIO_STA_SDIOIT 0x00400000U /*!<SDIO interrupt received */
+#define SDIO_STA_CEATAEND 0x00800000U /*!<CE-ATA command completion signal received for CMD61 */
+
+/******************* Bit definition for SDIO_ICR register *******************/
+#define SDIO_ICR_CCRCFAILC 0x00000001U /*!<CCRCFAIL flag clear bit */
+#define SDIO_ICR_DCRCFAILC 0x00000002U /*!<DCRCFAIL flag clear bit */
+#define SDIO_ICR_CTIMEOUTC 0x00000004U /*!<CTIMEOUT flag clear bit */
+#define SDIO_ICR_DTIMEOUTC 0x00000008U /*!<DTIMEOUT flag clear bit */
+#define SDIO_ICR_TXUNDERRC 0x00000010U /*!<TXUNDERR flag clear bit */
+#define SDIO_ICR_RXOVERRC 0x00000020U /*!<RXOVERR flag clear bit */
+#define SDIO_ICR_CMDRENDC 0x00000040U /*!<CMDREND flag clear bit */
+#define SDIO_ICR_CMDSENTC 0x00000080U /*!<CMDSENT flag clear bit */
+#define SDIO_ICR_DATAENDC 0x00000100U /*!<DATAEND flag clear bit */
+#define SDIO_ICR_STBITERRC 0x00000200U /*!<STBITERR flag clear bit */
+#define SDIO_ICR_DBCKENDC 0x00000400U /*!<DBCKEND flag clear bit */
+#define SDIO_ICR_SDIOITC 0x00400000U /*!<SDIOIT flag clear bit */
+#define SDIO_ICR_CEATAENDC 0x00800000U /*!<CEATAEND flag clear bit */
+
+/****************** Bit definition for SDIO_MASK register *******************/
+#define SDIO_MASK_CCRCFAILIE 0x00000001U /*!<Command CRC Fail Interrupt Enable */
+#define SDIO_MASK_DCRCFAILIE 0x00000002U /*!<Data CRC Fail Interrupt Enable */
+#define SDIO_MASK_CTIMEOUTIE 0x00000004U /*!<Command TimeOut Interrupt Enable */
+#define SDIO_MASK_DTIMEOUTIE 0x00000008U /*!<Data TimeOut Interrupt Enable */
+#define SDIO_MASK_TXUNDERRIE 0x00000010U /*!<Tx FIFO UnderRun Error Interrupt Enable */
+#define SDIO_MASK_RXOVERRIE 0x00000020U /*!<Rx FIFO OverRun Error Interrupt Enable */
+#define SDIO_MASK_CMDRENDIE 0x00000040U /*!<Command Response Received Interrupt Enable */
+#define SDIO_MASK_CMDSENTIE 0x00000080U /*!<Command Sent Interrupt Enable */
+#define SDIO_MASK_DATAENDIE 0x00000100U /*!<Data End Interrupt Enable */
+#define SDIO_MASK_STBITERRIE 0x00000200U /*!<Start Bit Error Interrupt Enable */
+#define SDIO_MASK_DBCKENDIE 0x00000400U /*!<Data Block End Interrupt Enable */
+#define SDIO_MASK_CMDACTIE 0x00000800U /*!<CCommand Acting Interrupt Enable */
+#define SDIO_MASK_TXACTIE 0x00001000U /*!<Data Transmit Acting Interrupt Enable */
+#define SDIO_MASK_RXACTIE 0x00002000U /*!<Data receive acting interrupt enabled */
+#define SDIO_MASK_TXFIFOHEIE 0x00004000U /*!<Tx FIFO Half Empty interrupt Enable */
+#define SDIO_MASK_RXFIFOHFIE 0x00008000U /*!<Rx FIFO Half Full interrupt Enable */
+#define SDIO_MASK_TXFIFOFIE 0x00010000U /*!<Tx FIFO Full interrupt Enable */
+#define SDIO_MASK_RXFIFOFIE 0x00020000U /*!<Rx FIFO Full interrupt Enable */
+#define SDIO_MASK_TXFIFOEIE 0x00040000U /*!<Tx FIFO Empty interrupt Enable */
+#define SDIO_MASK_RXFIFOEIE 0x00080000U /*!<Rx FIFO Empty interrupt Enable */
+#define SDIO_MASK_TXDAVLIE 0x00100000U /*!<Data available in Tx FIFO interrupt Enable */
+#define SDIO_MASK_RXDAVLIE 0x00200000U /*!<Data available in Rx FIFO interrupt Enable */
+#define SDIO_MASK_SDIOITIE 0x00400000U /*!<SDIO Mode Interrupt Received interrupt Enable */
+#define SDIO_MASK_CEATAENDIE 0x00800000U /*!<CE-ATA command completion signal received Interrupt Enable */
+
+/***************** Bit definition for SDIO_FIFOCNT register *****************/
+#define SDIO_FIFOCNT_FIFOCOUNT 0x00FFFFFFU /*!<Remaining number of words to be written to or read from the FIFO */
+
+/****************** Bit definition for SDIO_FIFO register *******************/
+#define SDIO_FIFO_FIFODATA 0xFFFFFFFFU /*!<Receive and transmit FIFO data */
+
+/******************************************************************************/
+/* */
+/* Serial Peripheral Interface */
+/* */
+/******************************************************************************/
+/******************* Bit definition for SPI_CR1 register ********************/
+#define SPI_CR1_CPHA 0x00000001U /*!<Clock Phase */
+#define SPI_CR1_CPOL 0x00000002U /*!<Clock Polarity */
+#define SPI_CR1_MSTR 0x00000004U /*!<Master Selection */
+
+#define SPI_CR1_BR 0x00000038U /*!<BR[2:0] bits (Baud Rate Control) */
+#define SPI_CR1_BR_0 0x00000008U /*!<Bit 0 */
+#define SPI_CR1_BR_1 0x00000010U /*!<Bit 1 */
+#define SPI_CR1_BR_2 0x00000020U /*!<Bit 2 */
+
+#define SPI_CR1_SPE 0x00000040U /*!<SPI Enable */
+#define SPI_CR1_LSBFIRST 0x00000080U /*!<Frame Format */
+#define SPI_CR1_SSI 0x00000100U /*!<Internal slave select */
+#define SPI_CR1_SSM 0x00000200U /*!<Software slave management */
+#define SPI_CR1_RXONLY 0x00000400U /*!<Receive only */
+#define SPI_CR1_DFF 0x00000800U /*!<Data Frame Format */
+#define SPI_CR1_CRCNEXT 0x00001000U /*!<Transmit CRC next */
+#define SPI_CR1_CRCEN 0x00002000U /*!<Hardware CRC calculation enable */
+#define SPI_CR1_BIDIOE 0x00004000U /*!<Output enable in bidirectional mode */
+#define SPI_CR1_BIDIMODE 0x00008000U /*!<Bidirectional data mode enable */
+
+/******************* Bit definition for SPI_CR2 register ********************/
+#define SPI_CR2_RXDMAEN 0x00000001U /*!<Rx Buffer DMA Enable */
+#define SPI_CR2_TXDMAEN 0x00000002U /*!<Tx Buffer DMA Enable */
+#define SPI_CR2_SSOE 0x00000004U /*!<SS Output Enable */
+#define SPI_CR2_FRF 0x00000010U /*!<Frame Format */
+#define SPI_CR2_ERRIE 0x00000020U /*!<Error Interrupt Enable */
+#define SPI_CR2_RXNEIE 0x00000040U /*!<RX buffer Not Empty Interrupt Enable */
+#define SPI_CR2_TXEIE 0x00000080U /*!<Tx buffer Empty Interrupt Enable */
+
+/******************** Bit definition for SPI_SR register ********************/
+#define SPI_SR_RXNE 0x00000001U /*!<Receive buffer Not Empty */
+#define SPI_SR_TXE 0x00000002U /*!<Transmit buffer Empty */
+#define SPI_SR_CHSIDE 0x00000004U /*!<Channel side */
+#define SPI_SR_UDR 0x00000008U /*!<Underrun flag */
+#define SPI_SR_CRCERR 0x00000010U /*!<CRC Error flag */
+#define SPI_SR_MODF 0x00000020U /*!<Mode fault */
+#define SPI_SR_OVR 0x00000040U /*!<Overrun flag */
+#define SPI_SR_BSY 0x00000080U /*!<Busy flag */
+#define SPI_SR_FRE 0x00000100U /*!<Frame format error flag */
+
+/******************** Bit definition for SPI_DR register ********************/
+#define SPI_DR_DR 0x0000FFFFU /*!<Data Register */
+
+/******************* Bit definition for SPI_CRCPR register ******************/
+#define SPI_CRCPR_CRCPOLY 0x0000FFFFU /*!<CRC polynomial register */
+
+/****************** Bit definition for SPI_RXCRCR register ******************/
+#define SPI_RXCRCR_RXCRC 0x0000FFFFU /*!<Rx CRC Register */
+
+/****************** Bit definition for SPI_TXCRCR register ******************/
+#define SPI_TXCRCR_TXCRC 0x0000FFFFU /*!<Tx CRC Register */
+
+/****************** Bit definition for SPI_I2SCFGR register *****************/
+#define SPI_I2SCFGR_CHLEN 0x00000001U /*!<Channel length (number of bits per audio channel) */
+
+#define SPI_I2SCFGR_DATLEN 0x00000006U /*!<DATLEN[1:0] bits (Data length to be transferred) */
+#define SPI_I2SCFGR_DATLEN_0 0x00000002U /*!<Bit 0 */
+#define SPI_I2SCFGR_DATLEN_1 0x00000004U /*!<Bit 1 */
+
+#define SPI_I2SCFGR_CKPOL 0x00000008U /*!<steady state clock polarity */
+
+#define SPI_I2SCFGR_I2SSTD 0x00000030U /*!<I2SSTD[1:0] bits (I2S standard selection) */
+#define SPI_I2SCFGR_I2SSTD_0 0x00000010U /*!<Bit 0 */
+#define SPI_I2SCFGR_I2SSTD_1 0x00000020U /*!<Bit 1 */
+
+#define SPI_I2SCFGR_PCMSYNC 0x00000080U /*!<PCM frame synchronization */
+
+#define SPI_I2SCFGR_I2SCFG 0x00000300U /*!<I2SCFG[1:0] bits (I2S configuration mode) */
+#define SPI_I2SCFGR_I2SCFG_0 0x00000100U /*!<Bit 0 */
+#define SPI_I2SCFGR_I2SCFG_1 0x00000200U /*!<Bit 1 */
+
+#define SPI_I2SCFGR_I2SE 0x00000400U /*!<I2S Enable */
+#define SPI_I2SCFGR_I2SMOD 0x00000800U /*!<I2S mode selection */
+
+/****************** Bit definition for SPI_I2SPR register *******************/
+#define SPI_I2SPR_I2SDIV 0x000000FFU /*!<I2S Linear prescaler */
+#define SPI_I2SPR_ODD 0x00000100U /*!<Odd factor for the prescaler */
+#define SPI_I2SPR_MCKOE 0x00000200U /*!<Master Clock Output Enable */
+
+/******************************************************************************/
+/* */
+/* SYSCFG */
+/* */
+/******************************************************************************/
+/****************** Bit definition for SYSCFG_MEMRMP register ***************/
+#define SYSCFG_MEMRMP_MEM_MODE 0x00000007U /*!< SYSCFG_Memory Remap Config */
+#define SYSCFG_MEMRMP_MEM_MODE_0 0x00000001U
+#define SYSCFG_MEMRMP_MEM_MODE_1 0x00000002U
+#define SYSCFG_MEMRMP_MEM_MODE_2 0x00000004U
+
+/****************** Bit definition for SYSCFG_PMC register ******************/
+#define SYSCFG_PMC_MII_RMII_SEL 0x00800000U /*!<Ethernet PHY interface selection */
+
+/***************** Bit definition for SYSCFG_EXTICR1 register ***************/
+#define SYSCFG_EXTICR1_EXTI0 0x000FU /*!<EXTI 0 configuration */
+#define SYSCFG_EXTICR1_EXTI1 0x00F0U /*!<EXTI 1 configuration */
+#define SYSCFG_EXTICR1_EXTI2 0x0F00U /*!<EXTI 2 configuration */
+#define SYSCFG_EXTICR1_EXTI3 0xF000U /*!<EXTI 3 configuration */
+/**
+ * @brief EXTI0 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI0_PA 0x0000U /*!<PA[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PB 0x0001U /*!<PB[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PC 0x0002U /*!<PC[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PD 0x0003U /*!<PD[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PE 0x0004U /*!<PE[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PF 0x0005U /*!<PF[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PG 0x0006U /*!<PG[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PH 0x0007U /*!<PH[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PI 0x0008U /*!<PI[0] pin */
+
+/**
+ * @brief EXTI1 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI1_PA 0x0000U /*!<PA[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PB 0x0010U /*!<PB[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PC 0x0020U /*!<PC[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PD 0x0030U /*!<PD[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PE 0x0040U /*!<PE[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PF 0x0050U /*!<PF[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PG 0x0060U /*!<PG[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PH 0x0070U /*!<PH[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PI 0x0080U /*!<PI[1] pin */
+
+/**
+ * @brief EXTI2 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI2_PA 0x0000U /*!<PA[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PB 0x0100U /*!<PB[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PC 0x0200U /*!<PC[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PD 0x0300U /*!<PD[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PE 0x0400U /*!<PE[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PF 0x0500U /*!<PF[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PG 0x0600U /*!<PG[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PH 0x0700U /*!<PH[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PI 0x0800U /*!<PI[2] pin */
+
+/**
+ * @brief EXTI3 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI3_PA 0x0000U /*!<PA[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PB 0x1000U /*!<PB[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PC 0x2000U /*!<PC[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PD 0x3000U /*!<PD[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PE 0x4000U /*!<PE[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PF 0x5000U /*!<PF[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PG 0x6000U /*!<PG[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PH 0x7000U /*!<PH[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PI 0x8000U /*!<PI[3] pin */
+
+/***************** Bit definition for SYSCFG_EXTICR2 register ***************/
+#define SYSCFG_EXTICR2_EXTI4 0x000FU /*!<EXTI 4 configuration */
+#define SYSCFG_EXTICR2_EXTI5 0x00F0U /*!<EXTI 5 configuration */
+#define SYSCFG_EXTICR2_EXTI6 0x0F00U /*!<EXTI 6 configuration */
+#define SYSCFG_EXTICR2_EXTI7 0xF000U /*!<EXTI 7 configuration */
+/**
+ * @brief EXTI4 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI4_PA 0x0000U /*!<PA[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PB 0x0001U /*!<PB[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PC 0x0002U /*!<PC[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PD 0x0003U /*!<PD[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PE 0x0004U /*!<PE[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PF 0x0005U /*!<PF[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PG 0x0006U /*!<PG[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PH 0x0007U /*!<PH[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PI 0x0008U /*!<PI[4] pin */
+
+/**
+ * @brief EXTI5 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI5_PA 0x0000U /*!<PA[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PB 0x0010U /*!<PB[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PC 0x0020U /*!<PC[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PD 0x0030U /*!<PD[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PE 0x0040U /*!<PE[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PF 0x0050U /*!<PF[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PG 0x0060U /*!<PG[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PH 0x0070U /*!<PH[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PI 0x0080U /*!<PI[5] pin */
+
+/**
+ * @brief EXTI6 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI6_PA 0x0000U /*!<PA[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PB 0x0100U /*!<PB[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PC 0x0200U /*!<PC[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PD 0x0300U /*!<PD[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PE 0x0400U /*!<PE[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PF 0x0500U /*!<PF[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PG 0x0600U /*!<PG[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PH 0x0700U /*!<PH[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PI 0x0800U /*!<PI[6] pin */
+
+/**
+ * @brief EXTI7 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI7_PA 0x0000U /*!<PA[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PB 0x1000U /*!<PB[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PC 0x2000U /*!<PC[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PD 0x3000U /*!<PD[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PE 0x4000U /*!<PE[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PF 0x5000U /*!<PF[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PG 0x6000U /*!<PG[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PH 0x7000U /*!<PH[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PI 0x8000U /*!<PI[7] pin */
+
+
+/***************** Bit definition for SYSCFG_EXTICR3 register ***************/
+#define SYSCFG_EXTICR3_EXTI8 0x000FU /*!<EXTI 8 configuration */
+#define SYSCFG_EXTICR3_EXTI9 0x00F0U /*!<EXTI 9 configuration */
+#define SYSCFG_EXTICR3_EXTI10 0x0F00U /*!<EXTI 10 configuration */
+#define SYSCFG_EXTICR3_EXTI11 0xF000U /*!<EXTI 11 configuration */
+
+/**
+ * @brief EXTI8 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI8_PA 0x0000U /*!<PA[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PB 0x0001U /*!<PB[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PC 0x0002U /*!<PC[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PD 0x0003U /*!<PD[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PE 0x0004U /*!<PE[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PF 0x0005U /*!<PF[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PG 0x0006U /*!<PG[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PH 0x0007U /*!<PH[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PI 0x0008U /*!<PI[8] pin */
+
+/**
+ * @brief EXTI9 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI9_PA 0x0000U /*!<PA[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PB 0x0010U /*!<PB[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PC 0x0020U /*!<PC[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PD 0x0030U /*!<PD[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PE 0x0040U /*!<PE[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PF 0x0050U /*!<PF[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PG 0x0060U /*!<PG[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PH 0x0070U /*!<PH[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PI 0x0080U /*!<PI[9] pin */
+
+/**
+ * @brief EXTI10 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI10_PA 0x0000U /*!<PA[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PB 0x0100U /*!<PB[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PC 0x0200U /*!<PC[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PD 0x0300U /*!<PD[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PE 0x0400U /*!<PE[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PF 0x0500U /*!<PF[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PG 0x0600U /*!<PG[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PH 0x0700U /*!<PH[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PI 0x0800U /*!<PI[10] pin */
+
+/**
+ * @brief EXTI11 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI11_PA 0x0000U /*!<PA[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PB 0x1000U /*!<PB[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PC 0x2000U /*!<PC[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PD 0x3000U /*!<PD[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PE 0x4000U /*!<PE[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PF 0x5000U /*!<PF[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PG 0x6000U /*!<PG[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PH 0x7000U /*!<PH[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PI 0x8000U /*!<PI[11] pin */
+
+/***************** Bit definition for SYSCFG_EXTICR4 register ***************/
+#define SYSCFG_EXTICR4_EXTI12 0x000FU /*!<EXTI 12 configuration */
+#define SYSCFG_EXTICR4_EXTI13 0x00F0U /*!<EXTI 13 configuration */
+#define SYSCFG_EXTICR4_EXTI14 0x0F00U /*!<EXTI 14 configuration */
+#define SYSCFG_EXTICR4_EXTI15 0xF000U /*!<EXTI 15 configuration */
+/**
+ * @brief EXTI12 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI12_PA 0x0000U /*!<PA[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PB 0x0001U /*!<PB[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PC 0x0002U /*!<PC[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PD 0x0003U /*!<PD[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PE 0x0004U /*!<PE[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PF 0x0005U /*!<PF[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PG 0x0006U /*!<PG[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PH 0x0007U /*!<PH[12] pin */
+
+/**
+ * @brief EXTI13 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI13_PA 0x0000U /*!<PA[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PB 0x0010U /*!<PB[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PC 0x0020U /*!<PC[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PD 0x0030U /*!<PD[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PE 0x0040U /*!<PE[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PF 0x0050U /*!<PF[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PG 0x0060U /*!<PG[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PH 0x0070U /*!<PH[13] pin */
+
+/**
+ * @brief EXTI14 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI14_PA 0x0000U /*!<PA[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PB 0x0100U /*!<PB[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PC 0x0200U /*!<PC[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PD 0x0300U /*!<PD[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PE 0x0400U /*!<PE[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PF 0x0500U /*!<PF[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PG 0x0600U /*!<PG[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PH 0x0700U /*!<PH[14] pin */
+
+/**
+ * @brief EXTI15 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI15_PA 0x0000U /*!<PA[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PB 0x1000U /*!<PB[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PC 0x2000U /*!<PC[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PD 0x3000U /*!<PD[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PE 0x4000U /*!<PE[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PF 0x5000U /*!<PF[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PG 0x6000U /*!<PG[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PH 0x7000U /*!<PH[15] pin */
+
+/****************** Bit definition for SYSCFG_CMPCR register ****************/
+#define SYSCFG_CMPCR_CMP_PD 0x00000001U /*!<Compensation cell ready flag */
+#define SYSCFG_CMPCR_READY 0x00000100U /*!<Compensation cell power-down */
+
+/******************************************************************************/
+/* */
+/* TIM */
+/* */
+/******************************************************************************/
+/******************* Bit definition for TIM_CR1 register ********************/
+#define TIM_CR1_CEN 0x0001U /*!<Counter enable */
+#define TIM_CR1_UDIS 0x0002U /*!<Update disable */
+#define TIM_CR1_URS 0x0004U /*!<Update request source */
+#define TIM_CR1_OPM 0x0008U /*!<One pulse mode */
+#define TIM_CR1_DIR 0x0010U /*!<Direction */
+
+#define TIM_CR1_CMS 0x0060U /*!<CMS[1:0] bits (Center-aligned mode selection) */
+#define TIM_CR1_CMS_0 0x0020U /*!<Bit 0 */
+#define TIM_CR1_CMS_1 0x0040U /*!<Bit 1 */
+
+#define TIM_CR1_ARPE 0x0080U /*!<Auto-reload preload enable */
+
+#define TIM_CR1_CKD 0x0300U /*!<CKD[1:0] bits (clock division) */
+#define TIM_CR1_CKD_0 0x0100U /*!<Bit 0 */
+#define TIM_CR1_CKD_1 0x0200U /*!<Bit 1 */
+
+/******************* Bit definition for TIM_CR2 register ********************/
+#define TIM_CR2_CCPC 0x0001U /*!<Capture/Compare Preloaded Control */
+#define TIM_CR2_CCUS 0x0004U /*!<Capture/Compare Control Update Selection */
+#define TIM_CR2_CCDS 0x0008U /*!<Capture/Compare DMA Selection */
+
+#define TIM_CR2_MMS 0x0070U /*!<MMS[2:0] bits (Master Mode Selection) */
+#define TIM_CR2_MMS_0 0x0010U /*!<Bit 0 */
+#define TIM_CR2_MMS_1 0x0020U /*!<Bit 1 */
+#define TIM_CR2_MMS_2 0x0040U /*!<Bit 2 */
+
+#define TIM_CR2_TI1S 0x0080U /*!<TI1 Selection */
+#define TIM_CR2_OIS1 0x0100U /*!<Output Idle state 1 (OC1 output) */
+#define TIM_CR2_OIS1N 0x0200U /*!<Output Idle state 1 (OC1N output) */
+#define TIM_CR2_OIS2 0x0400U /*!<Output Idle state 2 (OC2 output) */
+#define TIM_CR2_OIS2N 0x0800U /*!<Output Idle state 2 (OC2N output) */
+#define TIM_CR2_OIS3 0x1000U /*!<Output Idle state 3 (OC3 output) */
+#define TIM_CR2_OIS3N 0x2000U /*!<Output Idle state 3 (OC3N output) */
+#define TIM_CR2_OIS4 0x4000U /*!<Output Idle state 4 (OC4 output) */
+
+/******************* Bit definition for TIM_SMCR register *******************/
+#define TIM_SMCR_SMS 0x0007U /*!<SMS[2:0] bits (Slave mode selection) */
+#define TIM_SMCR_SMS_0 0x0001U /*!<Bit 0 */
+#define TIM_SMCR_SMS_1 0x0002U /*!<Bit 1 */
+#define TIM_SMCR_SMS_2 0x0004U /*!<Bit 2 */
+
+#define TIM_SMCR_TS 0x0070U /*!<TS[2:0] bits (Trigger selection) */
+#define TIM_SMCR_TS_0 0x0010U /*!<Bit 0 */
+#define TIM_SMCR_TS_1 0x0020U /*!<Bit 1 */
+#define TIM_SMCR_TS_2 0x0040U /*!<Bit 2 */
+
+#define TIM_SMCR_MSM 0x0080U /*!<Master/slave mode */
+
+#define TIM_SMCR_ETF 0x0F00U /*!<ETF[3:0] bits (External trigger filter) */
+#define TIM_SMCR_ETF_0 0x0100U /*!<Bit 0 */
+#define TIM_SMCR_ETF_1 0x0200U /*!<Bit 1 */
+#define TIM_SMCR_ETF_2 0x0400U /*!<Bit 2 */
+#define TIM_SMCR_ETF_3 0x0800U /*!<Bit 3 */
+
+#define TIM_SMCR_ETPS 0x3000U /*!<ETPS[1:0] bits (External trigger prescaler) */
+#define TIM_SMCR_ETPS_0 0x1000U /*!<Bit 0 */
+#define TIM_SMCR_ETPS_1 0x2000U /*!<Bit 1 */
+
+#define TIM_SMCR_ECE 0x4000U /*!<External clock enable */
+#define TIM_SMCR_ETP 0x8000U /*!<External trigger polarity */
+
+/******************* Bit definition for TIM_DIER register *******************/
+#define TIM_DIER_UIE 0x0001U /*!<Update interrupt enable */
+#define TIM_DIER_CC1IE 0x0002U /*!<Capture/Compare 1 interrupt enable */
+#define TIM_DIER_CC2IE 0x0004U /*!<Capture/Compare 2 interrupt enable */
+#define TIM_DIER_CC3IE 0x0008U /*!<Capture/Compare 3 interrupt enable */
+#define TIM_DIER_CC4IE 0x0010U /*!<Capture/Compare 4 interrupt enable */
+#define TIM_DIER_COMIE 0x0020U /*!<COM interrupt enable */
+#define TIM_DIER_TIE 0x0040U /*!<Trigger interrupt enable */
+#define TIM_DIER_BIE 0x0080U /*!<Break interrupt enable */
+#define TIM_DIER_UDE 0x0100U /*!<Update DMA request enable */
+#define TIM_DIER_CC1DE 0x0200U /*!<Capture/Compare 1 DMA request enable */
+#define TIM_DIER_CC2DE 0x0400U /*!<Capture/Compare 2 DMA request enable */
+#define TIM_DIER_CC3DE 0x0800U /*!<Capture/Compare 3 DMA request enable */
+#define TIM_DIER_CC4DE 0x1000U /*!<Capture/Compare 4 DMA request enable */
+#define TIM_DIER_COMDE 0x2000U /*!<COM DMA request enable */
+#define TIM_DIER_TDE 0x4000U /*!<Trigger DMA request enable */
+
+/******************** Bit definition for TIM_SR register ********************/
+#define TIM_SR_UIF 0x0001U /*!<Update interrupt Flag */
+#define TIM_SR_CC1IF 0x0002U /*!<Capture/Compare 1 interrupt Flag */
+#define TIM_SR_CC2IF 0x0004U /*!<Capture/Compare 2 interrupt Flag */
+#define TIM_SR_CC3IF 0x0008U /*!<Capture/Compare 3 interrupt Flag */
+#define TIM_SR_CC4IF 0x0010U /*!<Capture/Compare 4 interrupt Flag */
+#define TIM_SR_COMIF 0x0020U /*!<COM interrupt Flag */
+#define TIM_SR_TIF 0x0040U /*!<Trigger interrupt Flag */
+#define TIM_SR_BIF 0x0080U /*!<Break interrupt Flag */
+#define TIM_SR_CC1OF 0x0200U /*!<Capture/Compare 1 Overcapture Flag */
+#define TIM_SR_CC2OF 0x0400U /*!<Capture/Compare 2 Overcapture Flag */
+#define TIM_SR_CC3OF 0x0800U /*!<Capture/Compare 3 Overcapture Flag */
+#define TIM_SR_CC4OF 0x1000U /*!<Capture/Compare 4 Overcapture Flag */
+
+/******************* Bit definition for TIM_EGR register ********************/
+#define TIM_EGR_UG 0x01U /*!<Update Generation */
+#define TIM_EGR_CC1G 0x02U /*!<Capture/Compare 1 Generation */
+#define TIM_EGR_CC2G 0x04U /*!<Capture/Compare 2 Generation */
+#define TIM_EGR_CC3G 0x08U /*!<Capture/Compare 3 Generation */
+#define TIM_EGR_CC4G 0x10U /*!<Capture/Compare 4 Generation */
+#define TIM_EGR_COMG 0x20U /*!<Capture/Compare Control Update Generation */
+#define TIM_EGR_TG 0x40U /*!<Trigger Generation */
+#define TIM_EGR_BG 0x80U /*!<Break Generation */
+
+/****************** Bit definition for TIM_CCMR1 register *******************/
+#define TIM_CCMR1_CC1S 0x0003U /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
+#define TIM_CCMR1_CC1S_0 0x0001U /*!<Bit 0 */
+#define TIM_CCMR1_CC1S_1 0x0002U /*!<Bit 1 */
+
+#define TIM_CCMR1_OC1FE 0x0004U /*!<Output Compare 1 Fast enable */
+#define TIM_CCMR1_OC1PE 0x0008U /*!<Output Compare 1 Preload enable */
+
+#define TIM_CCMR1_OC1M 0x0070U /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
+#define TIM_CCMR1_OC1M_0 0x0010U /*!<Bit 0 */
+#define TIM_CCMR1_OC1M_1 0x0020U /*!<Bit 1 */
+#define TIM_CCMR1_OC1M_2 0x0040U /*!<Bit 2 */
+
+#define TIM_CCMR1_OC1CE 0x0080U /*!<Output Compare 1Clear Enable */
+
+#define TIM_CCMR1_CC2S 0x0300U /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
+#define TIM_CCMR1_CC2S_0 0x0100U /*!<Bit 0 */
+#define TIM_CCMR1_CC2S_1 0x0200U /*!<Bit 1 */
+
+#define TIM_CCMR1_OC2FE 0x0400U /*!<Output Compare 2 Fast enable */
+#define TIM_CCMR1_OC2PE 0x0800U /*!<Output Compare 2 Preload enable */
+
+#define TIM_CCMR1_OC2M 0x7000U /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
+#define TIM_CCMR1_OC2M_0 0x1000U /*!<Bit 0 */
+#define TIM_CCMR1_OC2M_1 0x2000U /*!<Bit 1 */
+#define TIM_CCMR1_OC2M_2 0x4000U /*!<Bit 2 */
+
+#define TIM_CCMR1_OC2CE 0x8000U /*!<Output Compare 2 Clear Enable */
+
+/*----------------------------------------------------------------------------*/
+
+#define TIM_CCMR1_IC1PSC 0x000CU /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
+#define TIM_CCMR1_IC1PSC_0 0x0004U /*!<Bit 0 */
+#define TIM_CCMR1_IC1PSC_1 0x0008U /*!<Bit 1 */
+
+#define TIM_CCMR1_IC1F 0x00F0U /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
+#define TIM_CCMR1_IC1F_0 0x0010U /*!<Bit 0 */
+#define TIM_CCMR1_IC1F_1 0x0020U /*!<Bit 1 */
+#define TIM_CCMR1_IC1F_2 0x0040U /*!<Bit 2 */
+#define TIM_CCMR1_IC1F_3 0x0080U /*!<Bit 3 */
+
+#define TIM_CCMR1_IC2PSC 0x0C00U /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
+#define TIM_CCMR1_IC2PSC_0 0x0400U /*!<Bit 0 */
+#define TIM_CCMR1_IC2PSC_1 0x0800U /*!<Bit 1 */
+
+#define TIM_CCMR1_IC2F 0xF000U /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
+#define TIM_CCMR1_IC2F_0 0x1000U /*!<Bit 0 */
+#define TIM_CCMR1_IC2F_1 0x2000U /*!<Bit 1 */
+#define TIM_CCMR1_IC2F_2 0x4000U /*!<Bit 2 */
+#define TIM_CCMR1_IC2F_3 0x8000U /*!<Bit 3 */
+
+/****************** Bit definition for TIM_CCMR2 register *******************/
+#define TIM_CCMR2_CC3S 0x0003U /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
+#define TIM_CCMR2_CC3S_0 0x0001U /*!<Bit 0 */
+#define TIM_CCMR2_CC3S_1 0x0002U /*!<Bit 1 */
+
+#define TIM_CCMR2_OC3FE 0x0004U /*!<Output Compare 3 Fast enable */
+#define TIM_CCMR2_OC3PE 0x0008U /*!<Output Compare 3 Preload enable */
+
+#define TIM_CCMR2_OC3M 0x0070U /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
+#define TIM_CCMR2_OC3M_0 0x0010U /*!<Bit 0 */
+#define TIM_CCMR2_OC3M_1 0x0020U /*!<Bit 1 */
+#define TIM_CCMR2_OC3M_2 0x0040U /*!<Bit 2 */
+
+#define TIM_CCMR2_OC3CE 0x0080U /*!<Output Compare 3 Clear Enable */
+
+#define TIM_CCMR2_CC4S 0x0300U /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
+#define TIM_CCMR2_CC4S_0 0x0100U /*!<Bit 0 */
+#define TIM_CCMR2_CC4S_1 0x0200U /*!<Bit 1 */
+
+#define TIM_CCMR2_OC4FE 0x0400U /*!<Output Compare 4 Fast enable */
+#define TIM_CCMR2_OC4PE 0x0800U /*!<Output Compare 4 Preload enable */
+
+#define TIM_CCMR2_OC4M 0x7000U /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
+#define TIM_CCMR2_OC4M_0 0x1000U /*!<Bit 0 */
+#define TIM_CCMR2_OC4M_1 0x2000U /*!<Bit 1 */
+#define TIM_CCMR2_OC4M_2 0x4000U /*!<Bit 2 */
+
+#define TIM_CCMR2_OC4CE 0x8000U /*!<Output Compare 4 Clear Enable */
+
+/*----------------------------------------------------------------------------*/
+
+#define TIM_CCMR2_IC3PSC 0x000CU /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
+#define TIM_CCMR2_IC3PSC_0 0x0004U /*!<Bit 0 */
+#define TIM_CCMR2_IC3PSC_1 0x0008U /*!<Bit 1 */
+
+#define TIM_CCMR2_IC3F 0x00F0U /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
+#define TIM_CCMR2_IC3F_0 0x0010U /*!<Bit 0 */
+#define TIM_CCMR2_IC3F_1 0x0020U /*!<Bit 1 */
+#define TIM_CCMR2_IC3F_2 0x0040U /*!<Bit 2 */
+#define TIM_CCMR2_IC3F_3 0x0080U /*!<Bit 3 */
+
+#define TIM_CCMR2_IC4PSC 0x0C00U /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
+#define TIM_CCMR2_IC4PSC_0 0x0400U /*!<Bit 0 */
+#define TIM_CCMR2_IC4PSC_1 0x0800U /*!<Bit 1 */
+
+#define TIM_CCMR2_IC4F 0xF000U /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
+#define TIM_CCMR2_IC4F_0 0x1000U /*!<Bit 0 */
+#define TIM_CCMR2_IC4F_1 0x2000U /*!<Bit 1 */
+#define TIM_CCMR2_IC4F_2 0x4000U /*!<Bit 2 */
+#define TIM_CCMR2_IC4F_3 0x8000U /*!<Bit 3 */
+
+/******************* Bit definition for TIM_CCER register *******************/
+#define TIM_CCER_CC1E 0x0001U /*!<Capture/Compare 1 output enable */
+#define TIM_CCER_CC1P 0x0002U /*!<Capture/Compare 1 output Polarity */
+#define TIM_CCER_CC1NE 0x0004U /*!<Capture/Compare 1 Complementary output enable */
+#define TIM_CCER_CC1NP 0x0008U /*!<Capture/Compare 1 Complementary output Polarity */
+#define TIM_CCER_CC2E 0x0010U /*!<Capture/Compare 2 output enable */
+#define TIM_CCER_CC2P 0x0020U /*!<Capture/Compare 2 output Polarity */
+#define TIM_CCER_CC2NE 0x0040U /*!<Capture/Compare 2 Complementary output enable */
+#define TIM_CCER_CC2NP 0x0080U /*!<Capture/Compare 2 Complementary output Polarity */
+#define TIM_CCER_CC3E 0x0100U /*!<Capture/Compare 3 output enable */
+#define TIM_CCER_CC3P 0x0200U /*!<Capture/Compare 3 output Polarity */
+#define TIM_CCER_CC3NE 0x0400U /*!<Capture/Compare 3 Complementary output enable */
+#define TIM_CCER_CC3NP 0x0800U /*!<Capture/Compare 3 Complementary output Polarity */
+#define TIM_CCER_CC4E 0x1000U /*!<Capture/Compare 4 output enable */
+#define TIM_CCER_CC4P 0x2000U /*!<Capture/Compare 4 output Polarity */
+#define TIM_CCER_CC4NP 0x8000U /*!<Capture/Compare 4 Complementary output Polarity */
+
+/******************* Bit definition for TIM_CNT register ********************/
+#define TIM_CNT_CNT 0xFFFFU /*!<Counter Value */
+
+/******************* Bit definition for TIM_PSC register ********************/
+#define TIM_PSC_PSC 0xFFFFU /*!<Prescaler Value */
+
+/******************* Bit definition for TIM_ARR register ********************/
+#define TIM_ARR_ARR 0xFFFFU /*!<actual auto-reload Value */
+
+/******************* Bit definition for TIM_RCR register ********************/
+#define TIM_RCR_REP 0xFFU /*!<Repetition Counter Value */
+
+/******************* Bit definition for TIM_CCR1 register *******************/
+#define TIM_CCR1_CCR1 0xFFFFU /*!<Capture/Compare 1 Value */
+
+/******************* Bit definition for TIM_CCR2 register *******************/
+#define TIM_CCR2_CCR2 0xFFFFU /*!<Capture/Compare 2 Value */
+
+/******************* Bit definition for TIM_CCR3 register *******************/
+#define TIM_CCR3_CCR3 0xFFFFU /*!<Capture/Compare 3 Value */
+
+/******************* Bit definition for TIM_CCR4 register *******************/
+#define TIM_CCR4_CCR4 0xFFFFU /*!<Capture/Compare 4 Value */
+
+/******************* Bit definition for TIM_BDTR register *******************/
+#define TIM_BDTR_DTG 0x00FFU /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
+#define TIM_BDTR_DTG_0 0x0001U /*!<Bit 0 */
+#define TIM_BDTR_DTG_1 0x0002U /*!<Bit 1 */
+#define TIM_BDTR_DTG_2 0x0004U /*!<Bit 2 */
+#define TIM_BDTR_DTG_3 0x0008U /*!<Bit 3 */
+#define TIM_BDTR_DTG_4 0x0010U /*!<Bit 4 */
+#define TIM_BDTR_DTG_5 0x0020U /*!<Bit 5 */
+#define TIM_BDTR_DTG_6 0x0040U /*!<Bit 6 */
+#define TIM_BDTR_DTG_7 0x0080U /*!<Bit 7 */
+
+#define TIM_BDTR_LOCK 0x0300U /*!<LOCK[1:0] bits (Lock Configuration) */
+#define TIM_BDTR_LOCK_0 0x0100U /*!<Bit 0 */
+#define TIM_BDTR_LOCK_1 0x0200U /*!<Bit 1 */
+
+#define TIM_BDTR_OSSI 0x0400U /*!<Off-State Selection for Idle mode */
+#define TIM_BDTR_OSSR 0x0800U /*!<Off-State Selection for Run mode */
+#define TIM_BDTR_BKE 0x1000U /*!<Break enable */
+#define TIM_BDTR_BKP 0x2000U /*!<Break Polarity */
+#define TIM_BDTR_AOE 0x4000U /*!<Automatic Output enable */
+#define TIM_BDTR_MOE 0x8000U /*!<Main Output enable */
+
+/******************* Bit definition for TIM_DCR register ********************/
+#define TIM_DCR_DBA 0x001FU /*!<DBA[4:0] bits (DMA Base Address) */
+#define TIM_DCR_DBA_0 0x0001U /*!<Bit 0 */
+#define TIM_DCR_DBA_1 0x0002U /*!<Bit 1 */
+#define TIM_DCR_DBA_2 0x0004U /*!<Bit 2 */
+#define TIM_DCR_DBA_3 0x0008U /*!<Bit 3 */
+#define TIM_DCR_DBA_4 0x0010U /*!<Bit 4 */
+
+#define TIM_DCR_DBL 0x1F00U /*!<DBL[4:0] bits (DMA Burst Length) */
+#define TIM_DCR_DBL_0 0x0100U /*!<Bit 0 */
+#define TIM_DCR_DBL_1 0x0200U /*!<Bit 1 */
+#define TIM_DCR_DBL_2 0x0400U /*!<Bit 2 */
+#define TIM_DCR_DBL_3 0x0800U /*!<Bit 3 */
+#define TIM_DCR_DBL_4 0x1000U /*!<Bit 4 */
+
+/******************* Bit definition for TIM_DMAR register *******************/
+#define TIM_DMAR_DMAB 0xFFFFU /*!<DMA register for burst accesses */
+
+/******************* Bit definition for TIM_OR register *********************/
+#define TIM_OR_TI4_RMP 0x00C0U /*!<TI4_RMP[1:0] bits (TIM5 Input 4 remap) */
+#define TIM_OR_TI4_RMP_0 0x0040U /*!<Bit 0 */
+#define TIM_OR_TI4_RMP_1 0x0080U /*!<Bit 1 */
+#define TIM_OR_ITR1_RMP 0x0C00U /*!<ITR1_RMP[1:0] bits (TIM2 Internal trigger 1 remap) */
+#define TIM_OR_ITR1_RMP_0 0x0400U /*!<Bit 0 */
+#define TIM_OR_ITR1_RMP_1 0x0800U /*!<Bit 1 */
+
+
+/******************************************************************************/
+/* */
+/* Universal Synchronous Asynchronous Receiver Transmitter */
+/* */
+/******************************************************************************/
+/******************* Bit definition for USART_SR register *******************/
+#define USART_SR_PE 0x0001U /*!<Parity Error */
+#define USART_SR_FE 0x0002U /*!<Framing Error */
+#define USART_SR_NE 0x0004U /*!<Noise Error Flag */
+#define USART_SR_ORE 0x0008U /*!<OverRun Error */
+#define USART_SR_IDLE 0x0010U /*!<IDLE line detected */
+#define USART_SR_RXNE 0x0020U /*!<Read Data Register Not Empty */
+#define USART_SR_TC 0x0040U /*!<Transmission Complete */
+#define USART_SR_TXE 0x0080U /*!<Transmit Data Register Empty */
+#define USART_SR_LBD 0x0100U /*!<LIN Break Detection Flag */
+#define USART_SR_CTS 0x0200U /*!<CTS Flag */
+
+/******************* Bit definition for USART_DR register *******************/
+#define USART_DR_DR 0x01FFU /*!<Data value */
+
+/****************** Bit definition for USART_BRR register *******************/
+#define USART_BRR_DIV_Fraction 0x000FU /*!<Fraction of USARTDIV */
+#define USART_BRR_DIV_Mantissa 0xFFF0U /*!<Mantissa of USARTDIV */
+
+/****************** Bit definition for USART_CR1 register *******************/
+#define USART_CR1_SBK 0x0001U /*!<Send Break */
+#define USART_CR1_RWU 0x0002U /*!<Receiver wakeup */
+#define USART_CR1_RE 0x0004U /*!<Receiver Enable */
+#define USART_CR1_TE 0x0008U /*!<Transmitter Enable */
+#define USART_CR1_IDLEIE 0x0010U /*!<IDLE Interrupt Enable */
+#define USART_CR1_RXNEIE 0x0020U /*!<RXNE Interrupt Enable */
+#define USART_CR1_TCIE 0x0040U /*!<Transmission Complete Interrupt Enable */
+#define USART_CR1_TXEIE 0x0080U /*!<PE Interrupt Enable */
+#define USART_CR1_PEIE 0x0100U /*!<PE Interrupt Enable */
+#define USART_CR1_PS 0x0200U /*!<Parity Selection */
+#define USART_CR1_PCE 0x0400U /*!<Parity Control Enable */
+#define USART_CR1_WAKE 0x0800U /*!<Wakeup method */
+#define USART_CR1_M 0x1000U /*!<Word length */
+#define USART_CR1_UE 0x2000U /*!<USART Enable */
+#define USART_CR1_OVER8 0x8000U /*!<USART Oversampling by 8 enable */
+
+/****************** Bit definition for USART_CR2 register *******************/
+#define USART_CR2_ADD 0x000FU /*!<Address of the USART node */
+#define USART_CR2_LBDL 0x0020U /*!<LIN Break Detection Length */
+#define USART_CR2_LBDIE 0x0040U /*!<LIN Break Detection Interrupt Enable */
+#define USART_CR2_LBCL 0x0100U /*!<Last Bit Clock pulse */
+#define USART_CR2_CPHA 0x0200U /*!<Clock Phase */
+#define USART_CR2_CPOL 0x0400U /*!<Clock Polarity */
+#define USART_CR2_CLKEN 0x0800U /*!<Clock Enable */
+
+#define USART_CR2_STOP 0x3000U /*!<STOP[1:0] bits (STOP bits) */
+#define USART_CR2_STOP_0 0x1000U /*!<Bit 0 */
+#define USART_CR2_STOP_1 0x2000U /*!<Bit 1 */
+
+#define USART_CR2_LINEN 0x4000U /*!<LIN mode enable */
+
+/****************** Bit definition for USART_CR3 register *******************/
+#define USART_CR3_EIE 0x0001U /*!<Error Interrupt Enable */
+#define USART_CR3_IREN 0x0002U /*!<IrDA mode Enable */
+#define USART_CR3_IRLP 0x0004U /*!<IrDA Low-Power */
+#define USART_CR3_HDSEL 0x0008U /*!<Half-Duplex Selection */
+#define USART_CR3_NACK 0x0010U /*!<Smartcard NACK enable */
+#define USART_CR3_SCEN 0x0020U /*!<Smartcard mode enable */
+#define USART_CR3_DMAR 0x0040U /*!<DMA Enable Receiver */
+#define USART_CR3_DMAT 0x0080U /*!<DMA Enable Transmitter */
+#define USART_CR3_RTSE 0x0100U /*!<RTS Enable */
+#define USART_CR3_CTSE 0x0200U /*!<CTS Enable */
+#define USART_CR3_CTSIE 0x0400U /*!<CTS Interrupt Enable */
+#define USART_CR3_ONEBIT 0x0800U /*!<USART One bit method enable */
+
+/****************** Bit definition for USART_GTPR register ******************/
+#define USART_GTPR_PSC 0x00FFU /*!<PSC[7:0] bits (Prescaler value) */
+#define USART_GTPR_PSC_0 0x0001U /*!<Bit 0 */
+#define USART_GTPR_PSC_1 0x0002U /*!<Bit 1 */
+#define USART_GTPR_PSC_2 0x0004U /*!<Bit 2 */
+#define USART_GTPR_PSC_3 0x0008U /*!<Bit 3 */
+#define USART_GTPR_PSC_4 0x0010U /*!<Bit 4 */
+#define USART_GTPR_PSC_5 0x0020U /*!<Bit 5 */
+#define USART_GTPR_PSC_6 0x0040U /*!<Bit 6 */
+#define USART_GTPR_PSC_7 0x0080U /*!<Bit 7 */
+
+#define USART_GTPR_GT 0xFF00U /*!<Guard time value */
+
+/******************************************************************************/
+/* */
+/* Window WATCHDOG */
+/* */
+/******************************************************************************/
+/******************* Bit definition for WWDG_CR register ********************/
+#define WWDG_CR_T 0x7FU /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
+#define WWDG_CR_T_0 0x01U /*!<Bit 0 */
+#define WWDG_CR_T_1 0x02U /*!<Bit 1 */
+#define WWDG_CR_T_2 0x04U /*!<Bit 2 */
+#define WWDG_CR_T_3 0x08U /*!<Bit 3 */
+#define WWDG_CR_T_4 0x10U /*!<Bit 4 */
+#define WWDG_CR_T_5 0x20U /*!<Bit 5 */
+#define WWDG_CR_T_6 0x40U /*!<Bit 6 */
+/* Legacy defines */
+#define WWDG_CR_T0 WWDG_CR_T_0
+#define WWDG_CR_T1 WWDG_CR_T_1
+#define WWDG_CR_T2 WWDG_CR_T_2
+#define WWDG_CR_T3 WWDG_CR_T_3
+#define WWDG_CR_T4 WWDG_CR_T_4
+#define WWDG_CR_T5 WWDG_CR_T_5
+#define WWDG_CR_T6 WWDG_CR_T_6
+
+#define WWDG_CR_WDGA 0x80U /*!<Activation bit */
+
+/******************* Bit definition for WWDG_CFR register *******************/
+#define WWDG_CFR_W 0x007FU /*!<W[6:0] bits (7-bit window value) */
+#define WWDG_CFR_W_0 0x0001U /*!<Bit 0 */
+#define WWDG_CFR_W_1 0x0002U /*!<Bit 1 */
+#define WWDG_CFR_W_2 0x0004U /*!<Bit 2 */
+#define WWDG_CFR_W_3 0x0008U /*!<Bit 3 */
+#define WWDG_CFR_W_4 0x0010U /*!<Bit 4 */
+#define WWDG_CFR_W_5 0x0020U /*!<Bit 5 */
+#define WWDG_CFR_W_6 0x0040U /*!<Bit 6 */
+/* Legacy defines */
+#define WWDG_CFR_W0 WWDG_CFR_W_0
+#define WWDG_CFR_W1 WWDG_CFR_W_1
+#define WWDG_CFR_W2 WWDG_CFR_W_2
+#define WWDG_CFR_W3 WWDG_CFR_W_3
+#define WWDG_CFR_W4 WWDG_CFR_W_4
+#define WWDG_CFR_W5 WWDG_CFR_W_5
+#define WWDG_CFR_W6 WWDG_CFR_W_6
+
+#define WWDG_CFR_WDGTB 0x0180U /*!<WDGTB[1:0] bits (Timer Base) */
+#define WWDG_CFR_WDGTB_0 0x0080U /*!<Bit 0 */
+#define WWDG_CFR_WDGTB_1 0x0100U /*!<Bit 1 */
+/* Legacy defines */
+#define WWDG_CFR_WDGTB0 WWDG_CFR_WDGTB_0
+#define WWDG_CFR_WDGTB1 WWDG_CFR_WDGTB_1
+
+#define WWDG_CFR_EWI 0x0200U /*!<Early Wakeup Interrupt */
+
+/******************* Bit definition for WWDG_SR register ********************/
+#define WWDG_SR_EWIF 0x01U /*!<Early Wakeup Interrupt Flag */
+
+
+/******************************************************************************/
+/* */
+/* DBG */
+/* */
+/******************************************************************************/
+/******************** Bit definition for DBGMCU_IDCODE register *************/
+#define DBGMCU_IDCODE_DEV_ID 0x00000FFFU
+#define DBGMCU_IDCODE_REV_ID 0xFFFF0000U
+
+/******************** Bit definition for DBGMCU_CR register *****************/
+#define DBGMCU_CR_DBG_SLEEP 0x00000001U
+#define DBGMCU_CR_DBG_STOP 0x00000002U
+#define DBGMCU_CR_DBG_STANDBY 0x00000004U
+#define DBGMCU_CR_TRACE_IOEN 0x00000020U
+
+#define DBGMCU_CR_TRACE_MODE 0x000000C0U
+#define DBGMCU_CR_TRACE_MODE_0 0x00000040U/*!<Bit 0 */
+#define DBGMCU_CR_TRACE_MODE_1 0x00000080U/*!<Bit 1 */
+
+/******************** Bit definition for DBGMCU_APB1_FZ register ************/
+#define DBGMCU_APB1_FZ_DBG_TIM2_STOP 0x00000001U
+#define DBGMCU_APB1_FZ_DBG_TIM3_STOP 0x00000002U
+#define DBGMCU_APB1_FZ_DBG_TIM4_STOP 0x00000004U
+#define DBGMCU_APB1_FZ_DBG_TIM5_STOP 0x00000008U
+#define DBGMCU_APB1_FZ_DBG_TIM6_STOP 0x00000010U
+#define DBGMCU_APB1_FZ_DBG_TIM7_STOP 0x00000020U
+#define DBGMCU_APB1_FZ_DBG_TIM12_STOP 0x00000040U
+#define DBGMCU_APB1_FZ_DBG_TIM13_STOP 0x00000080U
+#define DBGMCU_APB1_FZ_DBG_TIM14_STOP 0x00000100U
+#define DBGMCU_APB1_FZ_DBG_RTC_STOP 0x00000400U
+#define DBGMCU_APB1_FZ_DBG_WWDG_STOP 0x00000800U
+#define DBGMCU_APB1_FZ_DBG_IWDG_STOP 0x00001000U
+#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT 0x00200000U
+#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT 0x00400000U
+#define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT 0x00800000U
+#define DBGMCU_APB1_FZ_DBG_CAN1_STOP 0x02000000U
+#define DBGMCU_APB1_FZ_DBG_CAN2_STOP 0x04000000U
+/* Old IWDGSTOP bit definition, maintained for legacy purpose */
+#define DBGMCU_APB1_FZ_DBG_IWDEG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP
+
+/******************** Bit definition for DBGMCU_APB2_FZ register ************/
+#define DBGMCU_APB2_FZ_DBG_TIM1_STOP 0x00000001U
+#define DBGMCU_APB2_FZ_DBG_TIM8_STOP 0x00000002U
+#define DBGMCU_APB2_FZ_DBG_TIM9_STOP 0x00010000U
+#define DBGMCU_APB2_FZ_DBG_TIM10_STOP 0x00020000U
+#define DBGMCU_APB2_FZ_DBG_TIM11_STOP 0x00040000U
+
+/******************************************************************************/
+/* */
+/* Ethernet MAC Registers bits definitions */
+/* */
+/******************************************************************************/
+/* Bit definition for Ethernet MAC Control Register register */
+#define ETH_MACCR_WD 0x00800000U /* Watchdog disable */
+#define ETH_MACCR_JD 0x00400000U /* Jabber disable */
+#define ETH_MACCR_IFG 0x000E0000U /* Inter-frame gap */
+#define ETH_MACCR_IFG_96Bit 0x00000000U /* Minimum IFG between frames during transmission is 96Bit */
+ #define ETH_MACCR_IFG_88Bit 0x00020000U /* Minimum IFG between frames during transmission is 88Bit */
+ #define ETH_MACCR_IFG_80Bit 0x00040000U /* Minimum IFG between frames during transmission is 80Bit */
+ #define ETH_MACCR_IFG_72Bit 0x00060000U /* Minimum IFG between frames during transmission is 72Bit */
+ #define ETH_MACCR_IFG_64Bit 0x00080000U /* Minimum IFG between frames during transmission is 64Bit */
+ #define ETH_MACCR_IFG_56Bit 0x000A0000U /* Minimum IFG between frames during transmission is 56Bit */
+ #define ETH_MACCR_IFG_48Bit 0x000C0000U /* Minimum IFG between frames during transmission is 48Bit */
+ #define ETH_MACCR_IFG_40Bit 0x000E0000U /* Minimum IFG between frames during transmission is 40Bit */
+#define ETH_MACCR_CSD 0x00010000U /* Carrier sense disable (during transmission) */
+#define ETH_MACCR_FES 0x00004000U /* Fast ethernet speed */
+#define ETH_MACCR_ROD 0x00002000U /* Receive own disable */
+#define ETH_MACCR_LM 0x00001000U /* loopback mode */
+#define ETH_MACCR_DM 0x00000800U /* Duplex mode */
+#define ETH_MACCR_IPCO 0x00000400U /* IP Checksum offload */
+#define ETH_MACCR_RD 0x00000200U /* Retry disable */
+#define ETH_MACCR_APCS 0x00000080U /* Automatic Pad/CRC stripping */
+#define ETH_MACCR_BL 0x00000060U /* Back-off limit: random integer number (r) of slot time delays before rescheduling
+ a transmission attempt during retries after a collision: 0 =< r <2^k */
+ #define ETH_MACCR_BL_10 0x00000000U /* k = min (n, 10) */
+ #define ETH_MACCR_BL_8 0x00000020U /* k = min (n, 8) */
+ #define ETH_MACCR_BL_4 0x00000040U /* k = min (n, 4) */
+ #define ETH_MACCR_BL_1 0x00000060U /* k = min (n, 1) */
+#define ETH_MACCR_DC 0x00000010U /* Defferal check */
+#define ETH_MACCR_TE 0x00000008U /* Transmitter enable */
+#define ETH_MACCR_RE 0x00000004U /* Receiver enable */
+
+/* Bit definition for Ethernet MAC Frame Filter Register */
+#define ETH_MACFFR_RA 0x80000000U /* Receive all */
+#define ETH_MACFFR_HPF 0x00000400U /* Hash or perfect filter */
+#define ETH_MACFFR_SAF 0x00000200U /* Source address filter enable */
+#define ETH_MACFFR_SAIF 0x00000100U /* SA inverse filtering */
+#define ETH_MACFFR_PCF 0x000000C0U /* Pass control frames: 3 cases */
+ #define ETH_MACFFR_PCF_BlockAll 0x00000040U /* MAC filters all control frames from reaching the application */
+ #define ETH_MACFFR_PCF_ForwardAll 0x00000080U /* MAC forwards all control frames to application even if they fail the Address Filter */
+ #define ETH_MACFFR_PCF_ForwardPassedAddrFilter 0x000000C0U /* MAC forwards control frames that pass the Address Filter. */
+#define ETH_MACFFR_BFD 0x00000020U /* Broadcast frame disable */
+#define ETH_MACFFR_PAM 0x00000010U /* Pass all mutlicast */
+#define ETH_MACFFR_DAIF 0x00000008U /* DA Inverse filtering */
+#define ETH_MACFFR_HM 0x00000004U /* Hash multicast */
+#define ETH_MACFFR_HU 0x00000002U /* Hash unicast */
+#define ETH_MACFFR_PM 0x00000001U /* Promiscuous mode */
+
+/* Bit definition for Ethernet MAC Hash Table High Register */
+#define ETH_MACHTHR_HTH 0xFFFFFFFFU /* Hash table high */
+
+/* Bit definition for Ethernet MAC Hash Table Low Register */
+#define ETH_MACHTLR_HTL 0xFFFFFFFFU /* Hash table low */
+
+/* Bit definition for Ethernet MAC MII Address Register */
+#define ETH_MACMIIAR_PA 0x0000F800U /* Physical layer address */
+#define ETH_MACMIIAR_MR 0x000007C0U /* MII register in the selected PHY */
+#define ETH_MACMIIAR_CR 0x0000001CU /* CR clock range: 6 cases */
+ #define ETH_MACMIIAR_CR_Div42 0x00000000U /* HCLK:60-100 MHz; MDC clock= HCLK/42 */
+ #define ETH_MACMIIAR_CR_Div62 0x00000004U /* HCLK:100-150 MHz; MDC clock= HCLK/62 */
+ #define ETH_MACMIIAR_CR_Div16 0x00000008U /* HCLK:20-35 MHz; MDC clock= HCLK/16 */
+ #define ETH_MACMIIAR_CR_Div26 0x0000000CU /* HCLK:35-60 MHz; MDC clock= HCLK/26 */
+ #define ETH_MACMIIAR_CR_Div102 0x00000010U /* HCLK:150-168 MHz; MDC clock= HCLK/102 */
+#define ETH_MACMIIAR_MW 0x00000002U /* MII write */
+#define ETH_MACMIIAR_MB 0x00000001U /* MII busy */
+
+/* Bit definition for Ethernet MAC MII Data Register */
+#define ETH_MACMIIDR_MD 0x0000FFFFU /* MII data: read/write data from/to PHY */
+
+/* Bit definition for Ethernet MAC Flow Control Register */
+#define ETH_MACFCR_PT 0xFFFF0000U /* Pause time */
+#define ETH_MACFCR_ZQPD 0x00000080U /* Zero-quanta pause disable */
+#define ETH_MACFCR_PLT 0x00000030U /* Pause low threshold: 4 cases */
+ #define ETH_MACFCR_PLT_Minus4 0x00000000U /* Pause time minus 4 slot times */
+ #define ETH_MACFCR_PLT_Minus28 0x00000010U /* Pause time minus 28 slot times */
+ #define ETH_MACFCR_PLT_Minus144 0x00000020U /* Pause time minus 144 slot times */
+ #define ETH_MACFCR_PLT_Minus256 0x00000030U /* Pause time minus 256 slot times */
+#define ETH_MACFCR_UPFD 0x00000008U /* Unicast pause frame detect */
+#define ETH_MACFCR_RFCE 0x00000004U /* Receive flow control enable */
+#define ETH_MACFCR_TFCE 0x00000002U /* Transmit flow control enable */
+#define ETH_MACFCR_FCBBPA 0x00000001U /* Flow control busy/backpressure activate */
+
+/* Bit definition for Ethernet MAC VLAN Tag Register */
+#define ETH_MACVLANTR_VLANTC 0x00010000U /* 12-bit VLAN tag comparison */
+#define ETH_MACVLANTR_VLANTI 0x0000FFFFU /* VLAN tag identifier (for receive frames) */
+
+/* Bit definition for Ethernet MAC Remote Wake-UpFrame Filter Register */
+#define ETH_MACRWUFFR_D 0xFFFFFFFFU /* Wake-up frame filter register data */
+/* Eight sequential Writes to this address (offset 0x28) will write all Wake-UpFrame Filter Registers.
+ Eight sequential Reads from this address (offset 0x28) will read all Wake-UpFrame Filter Registers. */
+/* Wake-UpFrame Filter Reg0 : Filter 0 Byte Mask
+ Wake-UpFrame Filter Reg1 : Filter 1 Byte Mask
+ Wake-UpFrame Filter Reg2 : Filter 2 Byte Mask
+ Wake-UpFrame Filter Reg3 : Filter 3 Byte Mask
+ Wake-UpFrame Filter Reg4 : RSVD - Filter3 Command - RSVD - Filter2 Command -
+ RSVD - Filter1 Command - RSVD - Filter0 Command
+ Wake-UpFrame Filter Re5 : Filter3 Offset - Filter2 Offset - Filter1 Offset - Filter0 Offset
+ Wake-UpFrame Filter Re6 : Filter1 CRC16 - Filter0 CRC16
+ Wake-UpFrame Filter Re7 : Filter3 CRC16 - Filter2 CRC16 */
+
+/* Bit definition for Ethernet MAC PMT Control and Status Register */
+#define ETH_MACPMTCSR_WFFRPR 0x80000000U /* Wake-Up Frame Filter Register Pointer Reset */
+#define ETH_MACPMTCSR_GU 0x00000200U /* Global Unicast */
+#define ETH_MACPMTCSR_WFR 0x00000040U /* Wake-Up Frame Received */
+#define ETH_MACPMTCSR_MPR 0x00000020U /* Magic Packet Received */
+#define ETH_MACPMTCSR_WFE 0x00000004U /* Wake-Up Frame Enable */
+#define ETH_MACPMTCSR_MPE 0x00000002U /* Magic Packet Enable */
+#define ETH_MACPMTCSR_PD 0x00000001U /* Power Down */
+
+/* Bit definition for Ethernet MAC Status Register */
+#define ETH_MACSR_TSTS 0x00000200U /* Time stamp trigger status */
+#define ETH_MACSR_MMCTS 0x00000040U /* MMC transmit status */
+#define ETH_MACSR_MMMCRS 0x00000020U /* MMC receive status */
+#define ETH_MACSR_MMCS 0x00000010U /* MMC status */
+#define ETH_MACSR_PMTS 0x00000008U /* PMT status */
+
+/* Bit definition for Ethernet MAC Interrupt Mask Register */
+#define ETH_MACIMR_TSTIM 0x00000200U /* Time stamp trigger interrupt mask */
+#define ETH_MACIMR_PMTIM 0x00000008U /* PMT interrupt mask */
+
+/* Bit definition for Ethernet MAC Address0 High Register */
+#define ETH_MACA0HR_MACA0H 0x0000FFFFU /* MAC address0 high */
+
+/* Bit definition for Ethernet MAC Address0 Low Register */
+#define ETH_MACA0LR_MACA0L 0xFFFFFFFFU /* MAC address0 low */
+
+/* Bit definition for Ethernet MAC Address1 High Register */
+#define ETH_MACA1HR_AE 0x80000000U /* Address enable */
+#define ETH_MACA1HR_SA 0x40000000U /* Source address */
+#define ETH_MACA1HR_MBC 0x3F000000U /* Mask byte control: bits to mask for comparison of the MAC Address bytes */
+ #define ETH_MACA1HR_MBC_HBits15_8 0x20000000U /* Mask MAC Address high reg bits [15:8] */
+ #define ETH_MACA1HR_MBC_HBits7_0 0x10000000U /* Mask MAC Address high reg bits [7:0] */
+ #define ETH_MACA1HR_MBC_LBits31_24 0x08000000U /* Mask MAC Address low reg bits [31:24] */
+ #define ETH_MACA1HR_MBC_LBits23_16 0x04000000U /* Mask MAC Address low reg bits [23:16] */
+ #define ETH_MACA1HR_MBC_LBits15_8 0x02000000U /* Mask MAC Address low reg bits [15:8] */
+ #define ETH_MACA1HR_MBC_LBits7_0 0x01000000U /* Mask MAC Address low reg bits [7:0] */
+#define ETH_MACA1HR_MACA1H 0x0000FFFFU /* MAC address1 high */
+
+/* Bit definition for Ethernet MAC Address1 Low Register */
+#define ETH_MACA1LR_MACA1L 0xFFFFFFFFU /* MAC address1 low */
+
+/* Bit definition for Ethernet MAC Address2 High Register */
+#define ETH_MACA2HR_AE 0x80000000U /* Address enable */
+#define ETH_MACA2HR_SA 0x40000000U /* Source address */
+#define ETH_MACA2HR_MBC 0x3F000000U /* Mask byte control */
+ #define ETH_MACA2HR_MBC_HBits15_8 0x20000000U /* Mask MAC Address high reg bits [15:8] */
+ #define ETH_MACA2HR_MBC_HBits7_0 0x10000000U /* Mask MAC Address high reg bits [7:0] */
+ #define ETH_MACA2HR_MBC_LBits31_24 0x08000000U /* Mask MAC Address low reg bits [31:24] */
+ #define ETH_MACA2HR_MBC_LBits23_16 0x04000000U /* Mask MAC Address low reg bits [23:16] */
+ #define ETH_MACA2HR_MBC_LBits15_8 0x02000000U /* Mask MAC Address low reg bits [15:8] */
+ #define ETH_MACA2HR_MBC_LBits7_0 0x01000000U /* Mask MAC Address low reg bits [70] */
+#define ETH_MACA2HR_MACA2H 0x0000FFFFU /* MAC address1 high */
+
+/* Bit definition for Ethernet MAC Address2 Low Register */
+#define ETH_MACA2LR_MACA2L 0xFFFFFFFFU /* MAC address2 low */
+
+/* Bit definition for Ethernet MAC Address3 High Register */
+#define ETH_MACA3HR_AE 0x80000000U /* Address enable */
+#define ETH_MACA3HR_SA 0x40000000U /* Source address */
+#define ETH_MACA3HR_MBC 0x3F000000U /* Mask byte control */
+ #define ETH_MACA3HR_MBC_HBits15_8 0x20000000U /* Mask MAC Address high reg bits [15:8] */
+ #define ETH_MACA3HR_MBC_HBits7_0 0x10000000U /* Mask MAC Address high reg bits [7:0] */
+ #define ETH_MACA3HR_MBC_LBits31_24 0x08000000U /* Mask MAC Address low reg bits [31:24] */
+ #define ETH_MACA3HR_MBC_LBits23_16 0x04000000U /* Mask MAC Address low reg bits [23:16] */
+ #define ETH_MACA3HR_MBC_LBits15_8 0x02000000U /* Mask MAC Address low reg bits [15:8] */
+ #define ETH_MACA3HR_MBC_LBits7_0 0x01000000U /* Mask MAC Address low reg bits [70] */
+#define ETH_MACA3HR_MACA3H 0x0000FFFFU /* MAC address3 high */
+
+/* Bit definition for Ethernet MAC Address3 Low Register */
+#define ETH_MACA3LR_MACA3L 0xFFFFFFFFU /* MAC address3 low */
+
+/******************************************************************************/
+/* Ethernet MMC Registers bits definition */
+/******************************************************************************/
+
+/* Bit definition for Ethernet MMC Contol Register */
+#define ETH_MMCCR_MCFHP 0x00000020U /* MMC counter Full-Half preset */
+#define ETH_MMCCR_MCP 0x00000010U /* MMC counter preset */
+#define ETH_MMCCR_MCF 0x00000008U /* MMC Counter Freeze */
+#define ETH_MMCCR_ROR 0x00000004U /* Reset on Read */
+#define ETH_MMCCR_CSR 0x00000002U /* Counter Stop Rollover */
+#define ETH_MMCCR_CR 0x00000001U /* Counters Reset */
+
+/* Bit definition for Ethernet MMC Receive Interrupt Register */
+#define ETH_MMCRIR_RGUFS 0x00020000U /* Set when Rx good unicast frames counter reaches half the maximum value */
+#define ETH_MMCRIR_RFAES 0x00000040U /* Set when Rx alignment error counter reaches half the maximum value */
+#define ETH_MMCRIR_RFCES 0x00000020U /* Set when Rx crc error counter reaches half the maximum value */
+
+/* Bit definition for Ethernet MMC Transmit Interrupt Register */
+#define ETH_MMCTIR_TGFS 0x00200000U /* Set when Tx good frame count counter reaches half the maximum value */
+#define ETH_MMCTIR_TGFMSCS 0x00008000U /* Set when Tx good multi col counter reaches half the maximum value */
+#define ETH_MMCTIR_TGFSCS 0x00004000U /* Set when Tx good single col counter reaches half the maximum value */
+
+/* Bit definition for Ethernet MMC Receive Interrupt Mask Register */
+#define ETH_MMCRIMR_RGUFM 0x00020000U /* Mask the interrupt when Rx good unicast frames counter reaches half the maximum value */
+#define ETH_MMCRIMR_RFAEM 0x00000040U /* Mask the interrupt when when Rx alignment error counter reaches half the maximum value */
+#define ETH_MMCRIMR_RFCEM 0x00000020U /* Mask the interrupt when Rx crc error counter reaches half the maximum value */
+
+/* Bit definition for Ethernet MMC Transmit Interrupt Mask Register */
+#define ETH_MMCTIMR_TGFM 0x00200000U /* Mask the interrupt when Tx good frame count counter reaches half the maximum value */
+#define ETH_MMCTIMR_TGFMSCM 0x00008000U /* Mask the interrupt when Tx good multi col counter reaches half the maximum value */
+#define ETH_MMCTIMR_TGFSCM 0x00004000U /* Mask the interrupt when Tx good single col counter reaches half the maximum value */
+
+/* Bit definition for Ethernet MMC Transmitted Good Frames after Single Collision Counter Register */
+#define ETH_MMCTGFSCCR_TGFSCC 0xFFFFFFFFU /* Number of successfully transmitted frames after a single collision in Half-duplex mode. */
+
+/* Bit definition for Ethernet MMC Transmitted Good Frames after More than a Single Collision Counter Register */
+#define ETH_MMCTGFMSCCR_TGFMSCC 0xFFFFFFFFU /* Number of successfully transmitted frames after more than a single collision in Half-duplex mode. */
+
+/* Bit definition for Ethernet MMC Transmitted Good Frames Counter Register */
+#define ETH_MMCTGFCR_TGFC 0xFFFFFFFFU /* Number of good frames transmitted. */
+
+/* Bit definition for Ethernet MMC Received Frames with CRC Error Counter Register */
+#define ETH_MMCRFCECR_RFCEC 0xFFFFFFFFU /* Number of frames received with CRC error. */
+
+/* Bit definition for Ethernet MMC Received Frames with Alignement Error Counter Register */
+#define ETH_MMCRFAECR_RFAEC 0xFFFFFFFFU /* Number of frames received with alignment (dribble) error */
+
+/* Bit definition for Ethernet MMC Received Good Unicast Frames Counter Register */
+#define ETH_MMCRGUFCR_RGUFC 0xFFFFFFFFU /* Number of good unicast frames received. */
+
+/******************************************************************************/
+/* Ethernet PTP Registers bits definition */
+/******************************************************************************/
+
+/* Bit definition for Ethernet PTP Time Stamp Contol Register */
+#define ETH_PTPTSCR_TSCNT 0x00030000U /* Time stamp clock node type */
+#define ETH_PTPTSSR_TSSMRME 0x00008000U /* Time stamp snapshot for message relevant to master enable */
+#define ETH_PTPTSSR_TSSEME 0x00004000U /* Time stamp snapshot for event message enable */
+#define ETH_PTPTSSR_TSSIPV4FE 0x00002000U /* Time stamp snapshot for IPv4 frames enable */
+#define ETH_PTPTSSR_TSSIPV6FE 0x00001000U /* Time stamp snapshot for IPv6 frames enable */
+#define ETH_PTPTSSR_TSSPTPOEFE 0x00000800U /* Time stamp snapshot for PTP over ethernet frames enable */
+#define ETH_PTPTSSR_TSPTPPSV2E 0x00000400U /* Time stamp PTP packet snooping for version2 format enable */
+#define ETH_PTPTSSR_TSSSR 0x00000200U /* Time stamp Sub-seconds rollover */
+#define ETH_PTPTSSR_TSSARFE 0x00000100U /* Time stamp snapshot for all received frames enable */
+
+#define ETH_PTPTSCR_TSARU 0x00000020U /* Addend register update */
+#define ETH_PTPTSCR_TSITE 0x00000010U /* Time stamp interrupt trigger enable */
+#define ETH_PTPTSCR_TSSTU 0x00000008U /* Time stamp update */
+#define ETH_PTPTSCR_TSSTI 0x00000004U /* Time stamp initialize */
+#define ETH_PTPTSCR_TSFCU 0x00000002U /* Time stamp fine or coarse update */
+#define ETH_PTPTSCR_TSE 0x00000001U /* Time stamp enable */
+
+/* Bit definition for Ethernet PTP Sub-Second Increment Register */
+#define ETH_PTPSSIR_STSSI 0x000000FFU /* System time Sub-second increment value */
+
+/* Bit definition for Ethernet PTP Time Stamp High Register */
+#define ETH_PTPTSHR_STS 0xFFFFFFFFU /* System Time second */
+
+/* Bit definition for Ethernet PTP Time Stamp Low Register */
+#define ETH_PTPTSLR_STPNS 0x80000000U /* System Time Positive or negative time */
+#define ETH_PTPTSLR_STSS 0x7FFFFFFFU /* System Time sub-seconds */
+
+/* Bit definition for Ethernet PTP Time Stamp High Update Register */
+#define ETH_PTPTSHUR_TSUS 0xFFFFFFFFU /* Time stamp update seconds */
+
+/* Bit definition for Ethernet PTP Time Stamp Low Update Register */
+#define ETH_PTPTSLUR_TSUPNS 0x80000000U /* Time stamp update Positive or negative time */
+#define ETH_PTPTSLUR_TSUSS 0x7FFFFFFFU /* Time stamp update sub-seconds */
+
+/* Bit definition for Ethernet PTP Time Stamp Addend Register */
+#define ETH_PTPTSAR_TSA 0xFFFFFFFFU /* Time stamp addend */
+
+/* Bit definition for Ethernet PTP Target Time High Register */
+#define ETH_PTPTTHR_TTSH 0xFFFFFFFFU /* Target time stamp high */
+
+/* Bit definition for Ethernet PTP Target Time Low Register */
+#define ETH_PTPTTLR_TTSL 0xFFFFFFFFU /* Target time stamp low */
+
+/* Bit definition for Ethernet PTP Time Stamp Status Register */
+#define ETH_PTPTSSR_TSTTR 0x00000020U /* Time stamp target time reached */
+#define ETH_PTPTSSR_TSSO 0x00000010U /* Time stamp seconds overflow */
+
+/******************************************************************************/
+/* Ethernet DMA Registers bits definition */
+/******************************************************************************/
+
+/* Bit definition for Ethernet DMA Bus Mode Register */
+#define ETH_DMABMR_AAB 0x02000000U /* Address-Aligned beats */
+#define ETH_DMABMR_FPM 0x01000000U /* 4xPBL mode */
+#define ETH_DMABMR_USP 0x00800000U /* Use separate PBL */
+#define ETH_DMABMR_RDP 0x007E0000U /* RxDMA PBL */
+ #define ETH_DMABMR_RDP_1Beat 0x00020000U /* maximum number of beats to be transferred in one RxDMA transaction is 1 */
+ #define ETH_DMABMR_RDP_2Beat 0x00040000U /* maximum number of beats to be transferred in one RxDMA transaction is 2 */
+ #define ETH_DMABMR_RDP_4Beat 0x00080000U /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
+ #define ETH_DMABMR_RDP_8Beat 0x00100000U /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
+ #define ETH_DMABMR_RDP_16Beat 0x00200000U /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
+ #define ETH_DMABMR_RDP_32Beat 0x00400000U /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
+ #define ETH_DMABMR_RDP_4xPBL_4Beat 0x01020000U /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
+ #define ETH_DMABMR_RDP_4xPBL_8Beat 0x01040000U /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
+ #define ETH_DMABMR_RDP_4xPBL_16Beat 0x01080000U /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
+ #define ETH_DMABMR_RDP_4xPBL_32Beat 0x01100000U /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
+ #define ETH_DMABMR_RDP_4xPBL_64Beat 0x01200000U /* maximum number of beats to be transferred in one RxDMA transaction is 64 */
+ #define ETH_DMABMR_RDP_4xPBL_128Beat 0x01400000U /* maximum number of beats to be transferred in one RxDMA transaction is 128 */
+#define ETH_DMABMR_FB 0x00010000U /* Fixed Burst */
+#define ETH_DMABMR_RTPR 0x0000C000U /* Rx Tx priority ratio */
+ #define ETH_DMABMR_RTPR_1_1 0x00000000U /* Rx Tx priority ratio */
+ #define ETH_DMABMR_RTPR_2_1 0x00004000U /* Rx Tx priority ratio */
+ #define ETH_DMABMR_RTPR_3_1 0x00008000U /* Rx Tx priority ratio */
+ #define ETH_DMABMR_RTPR_4_1 0x0000C000U /* Rx Tx priority ratio */
+#define ETH_DMABMR_PBL 0x00003F00U /* Programmable burst length */
+ #define ETH_DMABMR_PBL_1Beat 0x00000100U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */
+ #define ETH_DMABMR_PBL_2Beat 0x00000200U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */
+ #define ETH_DMABMR_PBL_4Beat 0x00000400U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
+ #define ETH_DMABMR_PBL_8Beat 0x00000800U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
+ #define ETH_DMABMR_PBL_16Beat 0x00001000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
+ #define ETH_DMABMR_PBL_32Beat 0x00002000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
+ #define ETH_DMABMR_PBL_4xPBL_4Beat 0x01000100U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
+ #define ETH_DMABMR_PBL_4xPBL_8Beat 0x01000200U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
+ #define ETH_DMABMR_PBL_4xPBL_16Beat 0x01000400U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
+ #define ETH_DMABMR_PBL_4xPBL_32Beat 0x01000800U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
+ #define ETH_DMABMR_PBL_4xPBL_64Beat 0x01001000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */
+ #define ETH_DMABMR_PBL_4xPBL_128Beat 0x01002000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */
+#define ETH_DMABMR_EDE 0x00000080U /* Enhanced Descriptor Enable */
+#define ETH_DMABMR_DSL 0x0000007CU /* Descriptor Skip Length */
+#define ETH_DMABMR_DA 0x00000002U /* DMA arbitration scheme */
+#define ETH_DMABMR_SR 0x00000001U /* Software reset */
+
+/* Bit definition for Ethernet DMA Transmit Poll Demand Register */
+#define ETH_DMATPDR_TPD 0xFFFFFFFFU /* Transmit poll demand */
+
+/* Bit definition for Ethernet DMA Receive Poll Demand Register */
+#define ETH_DMARPDR_RPD 0xFFFFFFFFU /* Receive poll demand */
+
+/* Bit definition for Ethernet DMA Receive Descriptor List Address Register */
+#define ETH_DMARDLAR_SRL 0xFFFFFFFFU /* Start of receive list */
+
+/* Bit definition for Ethernet DMA Transmit Descriptor List Address Register */
+#define ETH_DMATDLAR_STL 0xFFFFFFFFU /* Start of transmit list */
+
+/* Bit definition for Ethernet DMA Status Register */
+#define ETH_DMASR_TSTS 0x20000000U /* Time-stamp trigger status */
+#define ETH_DMASR_PMTS 0x10000000U /* PMT status */
+#define ETH_DMASR_MMCS 0x08000000U /* MMC status */
+#define ETH_DMASR_EBS 0x03800000U /* Error bits status */
+ /* combination with EBS[2:0] for GetFlagStatus function */
+ #define ETH_DMASR_EBS_DescAccess 0x02000000U /* Error bits 0-data buffer, 1-desc. access */
+ #define ETH_DMASR_EBS_ReadTransf 0x01000000U /* Error bits 0-write trnsf, 1-read transfr */
+ #define ETH_DMASR_EBS_DataTransfTx 0x00800000U /* Error bits 0-Rx DMA, 1-Tx DMA */
+#define ETH_DMASR_TPS 0x00700000U /* Transmit process state */
+ #define ETH_DMASR_TPS_Stopped 0x00000000U /* Stopped - Reset or Stop Tx Command issued */
+ #define ETH_DMASR_TPS_Fetching 0x00100000U /* Running - fetching the Tx descriptor */
+ #define ETH_DMASR_TPS_Waiting 0x00200000U /* Running - waiting for status */
+ #define ETH_DMASR_TPS_Reading 0x00300000U /* Running - reading the data from host memory */
+ #define ETH_DMASR_TPS_Suspended 0x00600000U /* Suspended - Tx Descriptor unavailabe */
+ #define ETH_DMASR_TPS_Closing 0x00700000U /* Running - closing Rx descriptor */
+#define ETH_DMASR_RPS 0x000E0000U /* Receive process state */
+ #define ETH_DMASR_RPS_Stopped 0x00000000U /* Stopped - Reset or Stop Rx Command issued */
+ #define ETH_DMASR_RPS_Fetching 0x00020000U /* Running - fetching the Rx descriptor */
+ #define ETH_DMASR_RPS_Waiting 0x00060000U /* Running - waiting for packet */
+ #define ETH_DMASR_RPS_Suspended 0x00080000U /* Suspended - Rx Descriptor unavailable */
+ #define ETH_DMASR_RPS_Closing 0x000A0000U /* Running - closing descriptor */
+ #define ETH_DMASR_RPS_Queuing 0x000E0000U /* Running - queuing the recieve frame into host memory */
+#define ETH_DMASR_NIS 0x00010000U /* Normal interrupt summary */
+#define ETH_DMASR_AIS 0x00008000U /* Abnormal interrupt summary */
+#define ETH_DMASR_ERS 0x00004000U /* Early receive status */
+#define ETH_DMASR_FBES 0x00002000U /* Fatal bus error status */
+#define ETH_DMASR_ETS 0x00000400U /* Early transmit status */
+#define ETH_DMASR_RWTS 0x00000200U /* Receive watchdog timeout status */
+#define ETH_DMASR_RPSS 0x00000100U /* Receive process stopped status */
+#define ETH_DMASR_RBUS 0x00000080U /* Receive buffer unavailable status */
+#define ETH_DMASR_RS 0x00000040U /* Receive status */
+#define ETH_DMASR_TUS 0x00000020U /* Transmit underflow status */
+#define ETH_DMASR_ROS 0x00000010U /* Receive overflow status */
+#define ETH_DMASR_TJTS 0x00000008U /* Transmit jabber timeout status */
+#define ETH_DMASR_TBUS 0x00000004U /* Transmit buffer unavailable status */
+#define ETH_DMASR_TPSS 0x00000002U /* Transmit process stopped status */
+#define ETH_DMASR_TS 0x00000001U /* Transmit status */
+
+/* Bit definition for Ethernet DMA Operation Mode Register */
+#define ETH_DMAOMR_DTCEFD 0x04000000U /* Disable Dropping of TCP/IP checksum error frames */
+#define ETH_DMAOMR_RSF 0x02000000U /* Receive store and forward */
+#define ETH_DMAOMR_DFRF 0x01000000U /* Disable flushing of received frames */
+#define ETH_DMAOMR_TSF 0x00200000U /* Transmit store and forward */
+#define ETH_DMAOMR_FTF 0x00100000U /* Flush transmit FIFO */
+#define ETH_DMAOMR_TTC 0x0001C000U /* Transmit threshold control */
+ #define ETH_DMAOMR_TTC_64Bytes 0x00000000U /* threshold level of the MTL Transmit FIFO is 64 Bytes */
+ #define ETH_DMAOMR_TTC_128Bytes 0x00004000U /* threshold level of the MTL Transmit FIFO is 128 Bytes */
+ #define ETH_DMAOMR_TTC_192Bytes 0x00008000U /* threshold level of the MTL Transmit FIFO is 192 Bytes */
+ #define ETH_DMAOMR_TTC_256Bytes 0x0000C000U /* threshold level of the MTL Transmit FIFO is 256 Bytes */
+ #define ETH_DMAOMR_TTC_40Bytes 0x00010000U /* threshold level of the MTL Transmit FIFO is 40 Bytes */
+ #define ETH_DMAOMR_TTC_32Bytes 0x00014000U /* threshold level of the MTL Transmit FIFO is 32 Bytes */
+ #define ETH_DMAOMR_TTC_24Bytes 0x00018000U /* threshold level of the MTL Transmit FIFO is 24 Bytes */
+ #define ETH_DMAOMR_TTC_16Bytes 0x0001C000U /* threshold level of the MTL Transmit FIFO is 16 Bytes */
+#define ETH_DMAOMR_ST 0x00002000U /* Start/stop transmission command */
+#define ETH_DMAOMR_FEF 0x00000080U /* Forward error frames */
+#define ETH_DMAOMR_FUGF 0x00000040U /* Forward undersized good frames */
+#define ETH_DMAOMR_RTC 0x00000018U /* receive threshold control */
+ #define ETH_DMAOMR_RTC_64Bytes 0x00000000U /* threshold level of the MTL Receive FIFO is 64 Bytes */
+ #define ETH_DMAOMR_RTC_32Bytes 0x00000008U /* threshold level of the MTL Receive FIFO is 32 Bytes */
+ #define ETH_DMAOMR_RTC_96Bytes 0x00000010U /* threshold level of the MTL Receive FIFO is 96 Bytes */
+ #define ETH_DMAOMR_RTC_128Bytes 0x00000018U /* threshold level of the MTL Receive FIFO is 128 Bytes */
+#define ETH_DMAOMR_OSF 0x00000004U /* operate on second frame */
+#define ETH_DMAOMR_SR 0x00000002U /* Start/stop receive */
+
+/* Bit definition for Ethernet DMA Interrupt Enable Register */
+#define ETH_DMAIER_NISE 0x00010000U /* Normal interrupt summary enable */
+#define ETH_DMAIER_AISE 0x00008000U /* Abnormal interrupt summary enable */
+#define ETH_DMAIER_ERIE 0x00004000U /* Early receive interrupt enable */
+#define ETH_DMAIER_FBEIE 0x00002000U /* Fatal bus error interrupt enable */
+#define ETH_DMAIER_ETIE 0x00000400U /* Early transmit interrupt enable */
+#define ETH_DMAIER_RWTIE 0x00000200U /* Receive watchdog timeout interrupt enable */
+#define ETH_DMAIER_RPSIE 0x00000100U /* Receive process stopped interrupt enable */
+#define ETH_DMAIER_RBUIE 0x00000080U /* Receive buffer unavailable interrupt enable */
+#define ETH_DMAIER_RIE 0x00000040U /* Receive interrupt enable */
+#define ETH_DMAIER_TUIE 0x00000020U /* Transmit Underflow interrupt enable */
+#define ETH_DMAIER_ROIE 0x00000010U /* Receive Overflow interrupt enable */
+#define ETH_DMAIER_TJTIE 0x00000008U /* Transmit jabber timeout interrupt enable */
+#define ETH_DMAIER_TBUIE 0x00000004U /* Transmit buffer unavailable interrupt enable */
+#define ETH_DMAIER_TPSIE 0x00000002U /* Transmit process stopped interrupt enable */
+#define ETH_DMAIER_TIE 0x00000001U /* Transmit interrupt enable */
+
+/* Bit definition for Ethernet DMA Missed Frame and Buffer Overflow Counter Register */
+#define ETH_DMAMFBOCR_OFOC 0x10000000U /* Overflow bit for FIFO overflow counter */
+#define ETH_DMAMFBOCR_MFA 0x0FFE0000U /* Number of frames missed by the application */
+#define ETH_DMAMFBOCR_OMFC 0x00010000U /* Overflow bit for missed frame counter */
+#define ETH_DMAMFBOCR_MFC 0x0000FFFFU /* Number of frames missed by the controller */
+
+/* Bit definition for Ethernet DMA Current Host Transmit Descriptor Register */
+#define ETH_DMACHTDR_HTDAP 0xFFFFFFFFU /* Host transmit descriptor address pointer */
+
+/* Bit definition for Ethernet DMA Current Host Receive Descriptor Register */
+#define ETH_DMACHRDR_HRDAP 0xFFFFFFFFU /* Host receive descriptor address pointer */
+
+/* Bit definition for Ethernet DMA Current Host Transmit Buffer Address Register */
+#define ETH_DMACHTBAR_HTBAP 0xFFFFFFFFU /* Host transmit buffer address pointer */
+
+/* Bit definition for Ethernet DMA Current Host Receive Buffer Address Register */
+#define ETH_DMACHRBAR_HRBAP 0xFFFFFFFFU /* Host receive buffer address pointer */
+
+/******************************************************************************/
+/* */
+/* USB_OTG */
+/* */
+/******************************************************************************/
+/******************** Bit definition forUSB_OTG_GOTGCTL register ********************/
+#define USB_OTG_GOTGCTL_SRQSCS 0x00000001U /*!< Session request success */
+#define USB_OTG_GOTGCTL_SRQ 0x00000002U /*!< Session request */
+#define USB_OTG_GOTGCTL_HNGSCS 0x00000100U /*!< Host negotiation success */
+#define USB_OTG_GOTGCTL_HNPRQ 0x00000200U /*!< HNP request */
+#define USB_OTG_GOTGCTL_HSHNPEN 0x00000400U /*!< Host set HNP enable */
+#define USB_OTG_GOTGCTL_DHNPEN 0x00000800U /*!< Device HNP enabled */
+#define USB_OTG_GOTGCTL_CIDSTS 0x00010000U /*!< Connector ID status */
+#define USB_OTG_GOTGCTL_DBCT 0x00020000U /*!< Long/short debounce time */
+#define USB_OTG_GOTGCTL_ASVLD 0x00040000U /*!< A-session valid */
+#define USB_OTG_GOTGCTL_BSVLD 0x00080000U /*!< B-session valid */
+
+/******************** Bit definition forUSB_OTG_HCFG register ********************/
+
+#define USB_OTG_HCFG_FSLSPCS 0x00000003U /*!< FS/LS PHY clock select */
+#define USB_OTG_HCFG_FSLSPCS_0 0x00000001U /*!<Bit 0 */
+#define USB_OTG_HCFG_FSLSPCS_1 0x00000002U /*!<Bit 1 */
+#define USB_OTG_HCFG_FSLSS 0x00000004U /*!< FS- and LS-only support */
+
+/******************** Bit definition forUSB_OTG_DCFG register ********************/
+
+#define USB_OTG_DCFG_DSPD 0x00000003U /*!< Device speed */
+#define USB_OTG_DCFG_DSPD_0 0x00000001U /*!<Bit 0 */
+#define USB_OTG_DCFG_DSPD_1 0x00000002U /*!<Bit 1 */
+#define USB_OTG_DCFG_NZLSOHSK 0x00000004U /*!< Nonzero-length status OUT handshake */
+
+#define USB_OTG_DCFG_DAD 0x000007F0U /*!< Device address */
+#define USB_OTG_DCFG_DAD_0 0x00000010U /*!<Bit 0 */
+#define USB_OTG_DCFG_DAD_1 0x00000020U /*!<Bit 1 */
+#define USB_OTG_DCFG_DAD_2 0x00000040U /*!<Bit 2 */
+#define USB_OTG_DCFG_DAD_3 0x00000080U /*!<Bit 3 */
+#define USB_OTG_DCFG_DAD_4 0x00000100U /*!<Bit 4 */
+#define USB_OTG_DCFG_DAD_5 0x00000200U /*!<Bit 5 */
+#define USB_OTG_DCFG_DAD_6 0x00000400U /*!<Bit 6 */
+
+#define USB_OTG_DCFG_PFIVL 0x00001800U /*!< Periodic (micro)frame interval */
+#define USB_OTG_DCFG_PFIVL_0 0x00000800U /*!<Bit 0 */
+#define USB_OTG_DCFG_PFIVL_1 0x00001000U /*!<Bit 1 */
+
+#define USB_OTG_DCFG_PERSCHIVL 0x03000000U /*!< Periodic scheduling interval */
+#define USB_OTG_DCFG_PERSCHIVL_0 0x01000000U /*!<Bit 0 */
+#define USB_OTG_DCFG_PERSCHIVL_1 0x02000000U /*!<Bit 1 */
+
+/******************** Bit definition forUSB_OTG_PCGCR register ********************/
+#define USB_OTG_PCGCR_STPPCLK 0x00000001U /*!< Stop PHY clock */
+#define USB_OTG_PCGCR_GATEHCLK 0x00000002U /*!< Gate HCLK */
+#define USB_OTG_PCGCR_PHYSUSP 0x00000010U /*!< PHY suspended */
+
+/******************** Bit definition forUSB_OTG_GOTGINT register ********************/
+#define USB_OTG_GOTGINT_SEDET 0x00000004U /*!< Session end detected */
+#define USB_OTG_GOTGINT_SRSSCHG 0x00000100U /*!< Session request success status change */
+#define USB_OTG_GOTGINT_HNSSCHG 0x00000200U /*!< Host negotiation success status change */
+#define USB_OTG_GOTGINT_HNGDET 0x00020000U /*!< Host negotiation detected */
+#define USB_OTG_GOTGINT_ADTOCHG 0x00040000U /*!< A-device timeout change */
+#define USB_OTG_GOTGINT_DBCDNE 0x00080000U /*!< Debounce done */
+
+/******************** Bit definition forUSB_OTG_DCTL register ********************/
+#define USB_OTG_DCTL_RWUSIG 0x00000001U /*!< Remote wakeup signaling */
+#define USB_OTG_DCTL_SDIS 0x00000002U /*!< Soft disconnect */
+#define USB_OTG_DCTL_GINSTS 0x00000004U /*!< Global IN NAK status */
+#define USB_OTG_DCTL_GONSTS 0x00000008U /*!< Global OUT NAK status */
+
+#define USB_OTG_DCTL_TCTL 0x00000070U /*!< Test control */
+#define USB_OTG_DCTL_TCTL_0 0x00000010U /*!<Bit 0 */
+#define USB_OTG_DCTL_TCTL_1 0x00000020U /*!<Bit 1 */
+#define USB_OTG_DCTL_TCTL_2 0x00000040U /*!<Bit 2 */
+#define USB_OTG_DCTL_SGINAK 0x00000080U /*!< Set global IN NAK */
+#define USB_OTG_DCTL_CGINAK 0x00000100U /*!< Clear global IN NAK */
+#define USB_OTG_DCTL_SGONAK 0x00000200U /*!< Set global OUT NAK */
+#define USB_OTG_DCTL_CGONAK 0x00000400U /*!< Clear global OUT NAK */
+#define USB_OTG_DCTL_POPRGDNE 0x00000800U /*!< Power-on programming done */
+
+/******************** Bit definition forUSB_OTG_HFIR register ********************/
+#define USB_OTG_HFIR_FRIVL 0x0000FFFFU /*!< Frame interval */
+
+/******************** Bit definition forUSB_OTG_HFNUM register ********************/
+#define USB_OTG_HFNUM_FRNUM 0x0000FFFFU /*!< Frame number */
+#define USB_OTG_HFNUM_FTREM 0xFFFF0000U /*!< Frame time remaining */
+
+/******************** Bit definition forUSB_OTG_DSTS register ********************/
+#define USB_OTG_DSTS_SUSPSTS 0x00000001U /*!< Suspend status */
+
+#define USB_OTG_DSTS_ENUMSPD 0x00000006U /*!< Enumerated speed */
+#define USB_OTG_DSTS_ENUMSPD_0 0x00000002U /*!<Bit 0 */
+#define USB_OTG_DSTS_ENUMSPD_1 0x00000004U /*!<Bit 1 */
+#define USB_OTG_DSTS_EERR 0x00000008U /*!< Erratic error */
+#define USB_OTG_DSTS_FNSOF 0x003FFF00U /*!< Frame number of the received SOF */
+
+/******************** Bit definition forUSB_OTG_GAHBCFG register ********************/
+#define USB_OTG_GAHBCFG_GINT 0x00000001U /*!< Global interrupt mask */
+
+#define USB_OTG_GAHBCFG_HBSTLEN 0x0000001EU /*!< Burst length/type */
+#define USB_OTG_GAHBCFG_HBSTLEN_0 0x00000002U /*!<Bit 0 */
+#define USB_OTG_GAHBCFG_HBSTLEN_1 0x00000004U /*!<Bit 1 */
+#define USB_OTG_GAHBCFG_HBSTLEN_2 0x00000008U /*!<Bit 2 */
+#define USB_OTG_GAHBCFG_HBSTLEN_3 0x00000010U /*!<Bit 3 */
+#define USB_OTG_GAHBCFG_DMAEN 0x00000020U /*!< DMA enable */
+#define USB_OTG_GAHBCFG_TXFELVL 0x00000080U /*!< TxFIFO empty level */
+#define USB_OTG_GAHBCFG_PTXFELVL 0x00000100U /*!< Periodic TxFIFO empty level */
+
+/******************** Bit definition forUSB_OTG_GUSBCFG register ********************/
+
+#define USB_OTG_GUSBCFG_TOCAL 0x00000007U /*!< FS timeout calibration */
+#define USB_OTG_GUSBCFG_TOCAL_0 0x00000001U /*!<Bit 0 */
+#define USB_OTG_GUSBCFG_TOCAL_1 0x00000002U /*!<Bit 1 */
+#define USB_OTG_GUSBCFG_TOCAL_2 0x00000004U /*!<Bit 2 */
+#define USB_OTG_GUSBCFG_PHYSEL 0x00000040U /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */
+#define USB_OTG_GUSBCFG_SRPCAP 0x00000100U /*!< SRP-capable */
+#define USB_OTG_GUSBCFG_HNPCAP 0x00000200U /*!< HNP-capable */
+
+#define USB_OTG_GUSBCFG_TRDT 0x00003C00U /*!< USB turnaround time */
+#define USB_OTG_GUSBCFG_TRDT_0 0x00000400U /*!<Bit 0 */
+#define USB_OTG_GUSBCFG_TRDT_1 0x00000800U /*!<Bit 1 */
+#define USB_OTG_GUSBCFG_TRDT_2 0x00001000U /*!<Bit 2 */
+#define USB_OTG_GUSBCFG_TRDT_3 0x00002000U /*!<Bit 3 */
+#define USB_OTG_GUSBCFG_PHYLPCS 0x00008000U /*!< PHY Low-power clock select */
+#define USB_OTG_GUSBCFG_ULPIFSLS 0x00020000U /*!< ULPI FS/LS select */
+#define USB_OTG_GUSBCFG_ULPIAR 0x00040000U /*!< ULPI Auto-resume */
+#define USB_OTG_GUSBCFG_ULPICSM 0x00080000U /*!< ULPI Clock SuspendM */
+#define USB_OTG_GUSBCFG_ULPIEVBUSD 0x00100000U /*!< ULPI External VBUS Drive */
+#define USB_OTG_GUSBCFG_ULPIEVBUSI 0x00200000U /*!< ULPI external VBUS indicator */
+#define USB_OTG_GUSBCFG_TSDPS 0x00400000U /*!< TermSel DLine pulsing selection */
+#define USB_OTG_GUSBCFG_PCCI 0x00800000U /*!< Indicator complement */
+#define USB_OTG_GUSBCFG_PTCI 0x01000000U /*!< Indicator pass through */
+#define USB_OTG_GUSBCFG_ULPIIPD 0x02000000U /*!< ULPI interface protect disable */
+#define USB_OTG_GUSBCFG_FHMOD 0x20000000U /*!< Forced host mode */
+#define USB_OTG_GUSBCFG_FDMOD 0x40000000U /*!< Forced peripheral mode */
+#define USB_OTG_GUSBCFG_CTXPKT 0x80000000U /*!< Corrupt Tx packet */
+
+/******************** Bit definition forUSB_OTG_GRSTCTL register ********************/
+#define USB_OTG_GRSTCTL_CSRST 0x00000001U /*!< Core soft reset */
+#define USB_OTG_GRSTCTL_HSRST 0x00000002U /*!< HCLK soft reset */
+#define USB_OTG_GRSTCTL_FCRST 0x00000004U /*!< Host frame counter reset */
+#define USB_OTG_GRSTCTL_RXFFLSH 0x00000010U /*!< RxFIFO flush */
+#define USB_OTG_GRSTCTL_TXFFLSH 0x00000020U /*!< TxFIFO flush */
+
+#define USB_OTG_GRSTCTL_TXFNUM 0x000007C0U /*!< TxFIFO number */
+#define USB_OTG_GRSTCTL_TXFNUM_0 0x00000040U /*!<Bit 0 */
+#define USB_OTG_GRSTCTL_TXFNUM_1 0x00000080U /*!<Bit 1 */
+#define USB_OTG_GRSTCTL_TXFNUM_2 0x00000100U /*!<Bit 2 */
+#define USB_OTG_GRSTCTL_TXFNUM_3 0x00000200U /*!<Bit 3 */
+#define USB_OTG_GRSTCTL_TXFNUM_4 0x00000400U /*!<Bit 4 */
+#define USB_OTG_GRSTCTL_DMAREQ 0x40000000U /*!< DMA request signal */
+#define USB_OTG_GRSTCTL_AHBIDL 0x80000000U /*!< AHB master idle */
+
+/******************** Bit definition forUSB_OTG_DIEPMSK register ********************/
+#define USB_OTG_DIEPMSK_XFRCM 0x00000001U /*!< Transfer completed interrupt mask */
+#define USB_OTG_DIEPMSK_EPDM 0x00000002U /*!< Endpoint disabled interrupt mask */
+#define USB_OTG_DIEPMSK_TOM 0x00000008U /*!< Timeout condition mask (nonisochronous endpoints) */
+#define USB_OTG_DIEPMSK_ITTXFEMSK 0x00000010U /*!< IN token received when TxFIFO empty mask */
+#define USB_OTG_DIEPMSK_INEPNMM 0x00000020U /*!< IN token received with EP mismatch mask */
+#define USB_OTG_DIEPMSK_INEPNEM 0x00000040U /*!< IN endpoint NAK effective mask */
+#define USB_OTG_DIEPMSK_TXFURM 0x00000100U /*!< FIFO underrun mask */
+#define USB_OTG_DIEPMSK_BIM 0x00000200U /*!< BNA interrupt mask */
+
+/******************** Bit definition forUSB_OTG_HPTXSTS register ********************/
+#define USB_OTG_HPTXSTS_PTXFSAVL 0x0000FFFFU /*!< Periodic transmit data FIFO space available */
+
+#define USB_OTG_HPTXSTS_PTXQSAV 0x00FF0000U /*!< Periodic transmit request queue space available */
+#define USB_OTG_HPTXSTS_PTXQSAV_0 0x00010000U /*!<Bit 0 */
+#define USB_OTG_HPTXSTS_PTXQSAV_1 0x00020000U /*!<Bit 1 */
+#define USB_OTG_HPTXSTS_PTXQSAV_2 0x00040000U /*!<Bit 2 */
+#define USB_OTG_HPTXSTS_PTXQSAV_3 0x00080000U /*!<Bit 3 */
+#define USB_OTG_HPTXSTS_PTXQSAV_4 0x00100000U /*!<Bit 4 */
+#define USB_OTG_HPTXSTS_PTXQSAV_5 0x00200000U /*!<Bit 5 */
+#define USB_OTG_HPTXSTS_PTXQSAV_6 0x00400000U /*!<Bit 6 */
+#define USB_OTG_HPTXSTS_PTXQSAV_7 0x00800000U /*!<Bit 7 */
+
+#define USB_OTG_HPTXSTS_PTXQTOP 0xFF000000U /*!< Top of the periodic transmit request queue */
+#define USB_OTG_HPTXSTS_PTXQTOP_0 0x01000000U /*!<Bit 0 */
+#define USB_OTG_HPTXSTS_PTXQTOP_1 0x02000000U /*!<Bit 1 */
+#define USB_OTG_HPTXSTS_PTXQTOP_2 0x04000000U /*!<Bit 2 */
+#define USB_OTG_HPTXSTS_PTXQTOP_3 0x08000000U /*!<Bit 3 */
+#define USB_OTG_HPTXSTS_PTXQTOP_4 0x10000000U /*!<Bit 4 */
+#define USB_OTG_HPTXSTS_PTXQTOP_5 0x20000000U /*!<Bit 5 */
+#define USB_OTG_HPTXSTS_PTXQTOP_6 0x40000000U /*!<Bit 6 */
+#define USB_OTG_HPTXSTS_PTXQTOP_7 0x80000000U /*!<Bit 7 */
+
+/******************** Bit definition forUSB_OTG_HAINT register ********************/
+#define USB_OTG_HAINT_HAINT 0x0000FFFFU /*!< Channel interrupts */
+
+/******************** Bit definition forUSB_OTG_DOEPMSK register ********************/
+#define USB_OTG_DOEPMSK_XFRCM 0x00000001U /*!< Transfer completed interrupt mask */
+#define USB_OTG_DOEPMSK_EPDM 0x00000002U /*!< Endpoint disabled interrupt mask */
+#define USB_OTG_DOEPMSK_STUPM 0x00000008U /*!< SETUP phase done mask */
+#define USB_OTG_DOEPMSK_OTEPDM 0x00000010U /*!< OUT token received when endpoint disabled mask */
+#define USB_OTG_DOEPMSK_B2BSTUP 0x00000040U /*!< Back-to-back SETUP packets received mask */
+#define USB_OTG_DOEPMSK_OPEM 0x00000100U /*!< OUT packet error mask */
+#define USB_OTG_DOEPMSK_BOIM 0x00000200U /*!< BNA interrupt mask */
+
+/******************** Bit definition forUSB_OTG_GINTSTS register ********************/
+#define USB_OTG_GINTSTS_CMOD 0x00000001U /*!< Current mode of operation */
+#define USB_OTG_GINTSTS_MMIS 0x00000002U /*!< Mode mismatch interrupt */
+#define USB_OTG_GINTSTS_OTGINT 0x00000004U /*!< OTG interrupt */
+#define USB_OTG_GINTSTS_SOF 0x00000008U /*!< Start of frame */
+#define USB_OTG_GINTSTS_RXFLVL 0x00000010U /*!< RxFIFO nonempty */
+#define USB_OTG_GINTSTS_NPTXFE 0x00000020U /*!< Nonperiodic TxFIFO empty */
+#define USB_OTG_GINTSTS_GINAKEFF 0x00000040U /*!< Global IN nonperiodic NAK effective */
+#define USB_OTG_GINTSTS_BOUTNAKEFF 0x00000080U /*!< Global OUT NAK effective */
+#define USB_OTG_GINTSTS_ESUSP 0x00000400U /*!< Early suspend */
+#define USB_OTG_GINTSTS_USBSUSP 0x00000800U /*!< USB suspend */
+#define USB_OTG_GINTSTS_USBRST 0x00001000U /*!< USB reset */
+#define USB_OTG_GINTSTS_ENUMDNE 0x00002000U /*!< Enumeration done */
+#define USB_OTG_GINTSTS_ISOODRP 0x00004000U /*!< Isochronous OUT packet dropped interrupt */
+#define USB_OTG_GINTSTS_EOPF 0x00008000U /*!< End of periodic frame interrupt */
+#define USB_OTG_GINTSTS_IEPINT 0x00040000U /*!< IN endpoint interrupt */
+#define USB_OTG_GINTSTS_OEPINT 0x00080000U /*!< OUT endpoint interrupt */
+#define USB_OTG_GINTSTS_IISOIXFR 0x00100000U /*!< Incomplete isochronous IN transfer */
+#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT 0x00200000U /*!< Incomplete periodic transfer */
+#define USB_OTG_GINTSTS_DATAFSUSP 0x00400000U /*!< Data fetch suspended */
+#define USB_OTG_GINTSTS_HPRTINT 0x01000000U /*!< Host port interrupt */
+#define USB_OTG_GINTSTS_HCINT 0x02000000U /*!< Host channels interrupt */
+#define USB_OTG_GINTSTS_PTXFE 0x04000000U /*!< Periodic TxFIFO empty */
+#define USB_OTG_GINTSTS_CIDSCHG 0x10000000U /*!< Connector ID status change */
+#define USB_OTG_GINTSTS_DISCINT 0x20000000U /*!< Disconnect detected interrupt */
+#define USB_OTG_GINTSTS_SRQINT 0x40000000U /*!< Session request/new session detected interrupt */
+#define USB_OTG_GINTSTS_WKUINT 0x80000000U /*!< Resume/remote wakeup detected interrupt */
+
+/******************** Bit definition forUSB_OTG_GINTMSK register ********************/
+#define USB_OTG_GINTMSK_MMISM 0x00000002U /*!< Mode mismatch interrupt mask */
+#define USB_OTG_GINTMSK_OTGINT 0x00000004U /*!< OTG interrupt mask */
+#define USB_OTG_GINTMSK_SOFM 0x00000008U /*!< Start of frame mask */
+#define USB_OTG_GINTMSK_RXFLVLM 0x00000010U /*!< Receive FIFO nonempty mask */
+#define USB_OTG_GINTMSK_NPTXFEM 0x00000020U /*!< Nonperiodic TxFIFO empty mask */
+#define USB_OTG_GINTMSK_GINAKEFFM 0x00000040U /*!< Global nonperiodic IN NAK effective mask */
+#define USB_OTG_GINTMSK_GONAKEFFM 0x00000080U /*!< Global OUT NAK effective mask */
+#define USB_OTG_GINTMSK_ESUSPM 0x00000400U /*!< Early suspend mask */
+#define USB_OTG_GINTMSK_USBSUSPM 0x00000800U /*!< USB suspend mask */
+#define USB_OTG_GINTMSK_USBRST 0x00001000U /*!< USB reset mask */
+#define USB_OTG_GINTMSK_ENUMDNEM 0x00002000U /*!< Enumeration done mask */
+#define USB_OTG_GINTMSK_ISOODRPM 0x00004000U /*!< Isochronous OUT packet dropped interrupt mask */
+#define USB_OTG_GINTMSK_EOPFM 0x00008000U /*!< End of periodic frame interrupt mask */
+#define USB_OTG_GINTMSK_EPMISM 0x00020000U /*!< Endpoint mismatch interrupt mask */
+#define USB_OTG_GINTMSK_IEPINT 0x00040000U /*!< IN endpoints interrupt mask */
+#define USB_OTG_GINTMSK_OEPINT 0x00080000U /*!< OUT endpoints interrupt mask */
+#define USB_OTG_GINTMSK_IISOIXFRM 0x00100000U /*!< Incomplete isochronous IN transfer mask */
+#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM 0x00200000U /*!< Incomplete periodic transfer mask */
+#define USB_OTG_GINTMSK_FSUSPM 0x00400000U /*!< Data fetch suspended mask */
+#define USB_OTG_GINTMSK_PRTIM 0x01000000U /*!< Host port interrupt mask */
+#define USB_OTG_GINTMSK_HCIM 0x02000000U /*!< Host channels interrupt mask */
+#define USB_OTG_GINTMSK_PTXFEM 0x04000000U /*!< Periodic TxFIFO empty mask */
+#define USB_OTG_GINTMSK_CIDSCHGM 0x10000000U /*!< Connector ID status change mask */
+#define USB_OTG_GINTMSK_DISCINT 0x20000000U /*!< Disconnect detected interrupt mask */
+#define USB_OTG_GINTMSK_SRQIM 0x40000000U /*!< Session request/new session detected interrupt mask */
+#define USB_OTG_GINTMSK_WUIM 0x80000000U /*!< Resume/remote wakeup detected interrupt mask */
+
+/******************** Bit definition forUSB_OTG_DAINT register ********************/
+#define USB_OTG_DAINT_IEPINT 0x0000FFFFU /*!< IN endpoint interrupt bits */
+#define USB_OTG_DAINT_OEPINT 0xFFFF0000U /*!< OUT endpoint interrupt bits */
+
+/******************** Bit definition forUSB_OTG_HAINTMSK register ********************/
+#define USB_OTG_HAINTMSK_HAINTM 0x0000FFFFU /*!< Channel interrupt mask */
+
+/******************** Bit definition for USB_OTG_GRXSTSP register ********************/
+#define USB_OTG_GRXSTSP_EPNUM 0x0000000FU /*!< IN EP interrupt mask bits */
+#define USB_OTG_GRXSTSP_BCNT 0x00007FF0U /*!< OUT EP interrupt mask bits */
+#define USB_OTG_GRXSTSP_DPID 0x00018000U /*!< OUT EP interrupt mask bits */
+#define USB_OTG_GRXSTSP_PKTSTS 0x001E0000U /*!< OUT EP interrupt mask bits */
+
+/******************** Bit definition forUSB_OTG_DAINTMSK register ********************/
+#define USB_OTG_DAINTMSK_IEPM 0x0000FFFFU /*!< IN EP interrupt mask bits */
+#define USB_OTG_DAINTMSK_OEPM 0xFFFF0000U /*!< OUT EP interrupt mask bits */
+
+/******************** Bit definition for OTG register ********************/
+
+#define USB_OTG_CHNUM 0x0000000FU /*!< Channel number */
+#define USB_OTG_CHNUM_0 0x00000001U /*!<Bit 0 */
+#define USB_OTG_CHNUM_1 0x00000002U /*!<Bit 1 */
+#define USB_OTG_CHNUM_2 0x00000004U /*!<Bit 2 */
+#define USB_OTG_CHNUM_3 0x00000008U /*!<Bit 3 */
+#define USB_OTG_BCNT 0x00007FF0U /*!< Byte count */
+
+#define USB_OTG_DPID 0x00018000U /*!< Data PID */
+#define USB_OTG_DPID_0 0x00008000U /*!<Bit 0 */
+#define USB_OTG_DPID_1 0x00010000U /*!<Bit 1 */
+
+#define USB_OTG_PKTSTS 0x001E0000U /*!< Packet status */
+#define USB_OTG_PKTSTS_0 0x00020000U /*!<Bit 0 */
+#define USB_OTG_PKTSTS_1 0x00040000U /*!<Bit 1 */
+#define USB_OTG_PKTSTS_2 0x00080000U /*!<Bit 2 */
+#define USB_OTG_PKTSTS_3 0x00100000U /*!<Bit 3 */
+
+#define USB_OTG_EPNUM 0x0000000FU /*!< Endpoint number */
+#define USB_OTG_EPNUM_0 0x00000001U /*!<Bit 0 */
+#define USB_OTG_EPNUM_1 0x00000002U /*!<Bit 1 */
+#define USB_OTG_EPNUM_2 0x00000004U /*!<Bit 2 */
+#define USB_OTG_EPNUM_3 0x00000008U /*!<Bit 3 */
+
+#define USB_OTG_FRMNUM 0x01E00000U /*!< Frame number */
+#define USB_OTG_FRMNUM_0 0x00200000U /*!<Bit 0 */
+#define USB_OTG_FRMNUM_1 0x00400000U /*!<Bit 1 */
+#define USB_OTG_FRMNUM_2 0x00800000U /*!<Bit 2 */
+#define USB_OTG_FRMNUM_3 0x01000000U /*!<Bit 3 */
+
+/******************** Bit definition for OTG register ********************/
+
+#define USB_OTG_CHNUM 0x0000000FU /*!< Channel number */
+#define USB_OTG_CHNUM_0 0x00000001U /*!<Bit 0 */
+#define USB_OTG_CHNUM_1 0x00000002U /*!<Bit 1 */
+#define USB_OTG_CHNUM_2 0x00000004U /*!<Bit 2 */
+#define USB_OTG_CHNUM_3 0x00000008U /*!<Bit 3 */
+#define USB_OTG_BCNT 0x00007FF0U /*!< Byte count */
+
+#define USB_OTG_DPID 0x00018000U /*!< Data PID */
+#define USB_OTG_DPID_0 0x00008000U /*!<Bit 0 */
+#define USB_OTG_DPID_1 0x00010000U /*!<Bit 1 */
+
+#define USB_OTG_PKTSTS 0x001E0000U /*!< Packet status */
+#define USB_OTG_PKTSTS_0 0x00020000U /*!<Bit 0 */
+#define USB_OTG_PKTSTS_1 0x00040000U /*!<Bit 1 */
+#define USB_OTG_PKTSTS_2 0x00080000U /*!<Bit 2 */
+#define USB_OTG_PKTSTS_3 0x00100000U /*!<Bit 3 */
+
+#define USB_OTG_EPNUM 0x0000000FU /*!< Endpoint number */
+#define USB_OTG_EPNUM_0 0x00000001U /*!<Bit 0 */
+#define USB_OTG_EPNUM_1 0x00000002U /*!<Bit 1 */
+#define USB_OTG_EPNUM_2 0x00000004U /*!<Bit 2 */
+#define USB_OTG_EPNUM_3 0x00000008U /*!<Bit 3 */
+
+#define USB_OTG_FRMNUM 0x01E00000U /*!< Frame number */
+#define USB_OTG_FRMNUM_0 0x00200000U /*!<Bit 0 */
+#define USB_OTG_FRMNUM_1 0x00400000U /*!<Bit 1 */
+#define USB_OTG_FRMNUM_2 0x00800000U /*!<Bit 2 */
+#define USB_OTG_FRMNUM_3 0x01000000U /*!<Bit 3 */
+
+/******************** Bit definition forUSB_OTG_GRXFSIZ register ********************/
+#define USB_OTG_GRXFSIZ_RXFD 0x0000FFFFU /*!< RxFIFO depth */
+
+/******************** Bit definition forUSB_OTG_DVBUSDIS register ********************/
+#define USB_OTG_DVBUSDIS_VBUSDT 0x0000FFFFU /*!< Device VBUS discharge time */
+
+/******************** Bit definition for OTG register ********************/
+#define USB_OTG_NPTXFSA 0x0000FFFFU /*!< Nonperiodic transmit RAM start address */
+#define USB_OTG_NPTXFD 0xFFFF0000U /*!< Nonperiodic TxFIFO depth */
+#define USB_OTG_TX0FSA 0x0000FFFFU /*!< Endpoint 0 transmit RAM start address */
+#define USB_OTG_TX0FD 0xFFFF0000U /*!< Endpoint 0 TxFIFO depth */
+
+/******************** Bit definition forUSB_OTG_DVBUSPULSE register ********************/
+#define USB_OTG_DVBUSPULSE_DVBUSP 0x00000FFFU /*!< Device VBUS pulsing time */
+
+/******************** Bit definition forUSB_OTG_GNPTXSTS register ********************/
+#define USB_OTG_GNPTXSTS_NPTXFSAV 0x0000FFFFU /*!< Nonperiodic TxFIFO space available */
+
+#define USB_OTG_GNPTXSTS_NPTQXSAV 0x00FF0000U /*!< Nonperiodic transmit request queue space available */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_0 0x00010000U /*!<Bit 0 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_1 0x00020000U /*!<Bit 1 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_2 0x00040000U /*!<Bit 2 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_3 0x00080000U /*!<Bit 3 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_4 0x00100000U /*!<Bit 4 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_5 0x00200000U /*!<Bit 5 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_6 0x00400000U /*!<Bit 6 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_7 0x00800000U /*!<Bit 7 */
+
+#define USB_OTG_GNPTXSTS_NPTXQTOP 0x7F000000U /*!< Top of the nonperiodic transmit request queue */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_0 0x01000000U /*!<Bit 0 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_1 0x02000000U /*!<Bit 1 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_2 0x04000000U /*!<Bit 2 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_3 0x08000000U /*!<Bit 3 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_4 0x10000000U /*!<Bit 4 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_5 0x20000000U /*!<Bit 5 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_6 0x40000000U /*!<Bit 6 */
+
+/******************** Bit definition forUSB_OTG_DTHRCTL register ********************/
+#define USB_OTG_DTHRCTL_NONISOTHREN 0x00000001U /*!< Nonisochronous IN endpoints threshold enable */
+#define USB_OTG_DTHRCTL_ISOTHREN 0x00000002U /*!< ISO IN endpoint threshold enable */
+
+#define USB_OTG_DTHRCTL_TXTHRLEN 0x000007FCU /*!< Transmit threshold length */
+#define USB_OTG_DTHRCTL_TXTHRLEN_0 0x00000004U /*!<Bit 0 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_1 0x00000008U /*!<Bit 1 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_2 0x00000010U /*!<Bit 2 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_3 0x00000020U /*!<Bit 3 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_4 0x00000040U /*!<Bit 4 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_5 0x00000080U /*!<Bit 5 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_6 0x00000100U /*!<Bit 6 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_7 0x00000200U /*!<Bit 7 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_8 0x00000400U /*!<Bit 8 */
+#define USB_OTG_DTHRCTL_RXTHREN 0x00010000U /*!< Receive threshold enable */
+
+#define USB_OTG_DTHRCTL_RXTHRLEN 0x03FE0000U /*!< Receive threshold length */
+#define USB_OTG_DTHRCTL_RXTHRLEN_0 0x00020000U /*!<Bit 0 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_1 0x00040000U /*!<Bit 1 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_2 0x00080000U /*!<Bit 2 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_3 0x00100000U /*!<Bit 3 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_4 0x00200000U /*!<Bit 4 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_5 0x00400000U /*!<Bit 5 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_6 0x00800000U /*!<Bit 6 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_7 0x01000000U /*!<Bit 7 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_8 0x02000000U /*!<Bit 8 */
+#define USB_OTG_DTHRCTL_ARPEN 0x08000000U /*!< Arbiter parking enable */
+
+/******************** Bit definition forUSB_OTG_DIEPEMPMSK register ********************/
+#define USB_OTG_DIEPEMPMSK_INEPTXFEM 0x0000FFFFU /*!< IN EP Tx FIFO empty interrupt mask bits */
+
+/******************** Bit definition forUSB_OTG_DEACHINT register ********************/
+#define USB_OTG_DEACHINT_IEP1INT 0x00000002U /*!< IN endpoint 1interrupt bit */
+#define USB_OTG_DEACHINT_OEP1INT 0x00020000U /*!< OUT endpoint 1 interrupt bit */
+
+/******************** Bit definition forUSB_OTG_GCCFG register ********************/
+#define USB_OTG_GCCFG_PWRDWN 0x00010000U /*!< Power down */
+#define USB_OTG_GCCFG_I2CPADEN 0x00020000U /*!< Enable I2C bus connection for the external I2C PHY interface */
+#define USB_OTG_GCCFG_VBUSASEN 0x00040000U /*!< Enable the VBUS sensing device */
+#define USB_OTG_GCCFG_VBUSBSEN 0x00080000U /*!< Enable the VBUS sensing device */
+#define USB_OTG_GCCFG_SOFOUTEN 0x00100000U /*!< SOF output enable */
+#define USB_OTG_GCCFG_NOVBUSSENS 0x00200000U /*!< VBUS sensing disable option */
+
+/******************** Bit definition forUSB_OTG_DEACHINTMSK register ********************/
+#define USB_OTG_DEACHINTMSK_IEP1INTM 0x00000002U /*!< IN Endpoint 1 interrupt mask bit */
+#define USB_OTG_DEACHINTMSK_OEP1INTM 0x00020000U /*!< OUT Endpoint 1 interrupt mask bit */
+
+/******************** Bit definition forUSB_OTG_CID register ********************/
+#define USB_OTG_CID_PRODUCT_ID 0xFFFFFFFFU /*!< Product ID field */
+
+/******************** Bit definition forUSB_OTG_DIEPEACHMSK1 register ********************/
+#define USB_OTG_DIEPEACHMSK1_XFRCM 0x00000001U /*!< Transfer completed interrupt mask */
+#define USB_OTG_DIEPEACHMSK1_EPDM 0x00000002U /*!< Endpoint disabled interrupt mask */
+#define USB_OTG_DIEPEACHMSK1_TOM 0x00000008U /*!< Timeout condition mask (nonisochronous endpoints) */
+#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK 0x00000010U /*!< IN token received when TxFIFO empty mask */
+#define USB_OTG_DIEPEACHMSK1_INEPNMM 0x00000020U /*!< IN token received with EP mismatch mask */
+#define USB_OTG_DIEPEACHMSK1_INEPNEM 0x00000040U /*!< IN endpoint NAK effective mask */
+#define USB_OTG_DIEPEACHMSK1_TXFURM 0x00000100U /*!< FIFO underrun mask */
+#define USB_OTG_DIEPEACHMSK1_BIM 0x00000200U /*!< BNA interrupt mask */
+#define USB_OTG_DIEPEACHMSK1_NAKM 0x00002000U /*!< NAK interrupt mask */
+
+/******************** Bit definition forUSB_OTG_HPRT register ********************/
+#define USB_OTG_HPRT_PCSTS 0x00000001U /*!< Port connect status */
+#define USB_OTG_HPRT_PCDET 0x00000002U /*!< Port connect detected */
+#define USB_OTG_HPRT_PENA 0x00000004U /*!< Port enable */
+#define USB_OTG_HPRT_PENCHNG 0x00000008U /*!< Port enable/disable change */
+#define USB_OTG_HPRT_POCA 0x00000010U /*!< Port overcurrent active */
+#define USB_OTG_HPRT_POCCHNG 0x00000020U /*!< Port overcurrent change */
+#define USB_OTG_HPRT_PRES 0x00000040U /*!< Port resume */
+#define USB_OTG_HPRT_PSUSP 0x00000080U /*!< Port suspend */
+#define USB_OTG_HPRT_PRST 0x00000100U /*!< Port reset */
+
+#define USB_OTG_HPRT_PLSTS 0x00000C00U /*!< Port line status */
+#define USB_OTG_HPRT_PLSTS_0 0x00000400U /*!<Bit 0 */
+#define USB_OTG_HPRT_PLSTS_1 0x00000800U /*!<Bit 1 */
+#define USB_OTG_HPRT_PPWR 0x00001000U /*!< Port power */
+
+#define USB_OTG_HPRT_PTCTL 0x0001E000U /*!< Port test control */
+#define USB_OTG_HPRT_PTCTL_0 0x00002000U /*!<Bit 0 */
+#define USB_OTG_HPRT_PTCTL_1 0x00004000U /*!<Bit 1 */
+#define USB_OTG_HPRT_PTCTL_2 0x00008000U /*!<Bit 2 */
+#define USB_OTG_HPRT_PTCTL_3 0x00010000U /*!<Bit 3 */
+
+#define USB_OTG_HPRT_PSPD 0x00060000U /*!< Port speed */
+#define USB_OTG_HPRT_PSPD_0 0x00020000U /*!<Bit 0 */
+#define USB_OTG_HPRT_PSPD_1 0x00040000U /*!<Bit 1 */
+
+/******************** Bit definition forUSB_OTG_DOEPEACHMSK1 register ********************/
+#define USB_OTG_DOEPEACHMSK1_XFRCM 0x00000001U /*!< Transfer completed interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_EPDM 0x00000002U /*!< Endpoint disabled interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_TOM 0x00000008U /*!< Timeout condition mask */
+#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK 0x00000010U /*!< IN token received when TxFIFO empty mask */
+#define USB_OTG_DOEPEACHMSK1_INEPNMM 0x00000020U /*!< IN token received with EP mismatch mask */
+#define USB_OTG_DOEPEACHMSK1_INEPNEM 0x00000040U /*!< IN endpoint NAK effective mask */
+#define USB_OTG_DOEPEACHMSK1_TXFURM 0x00000100U /*!< OUT packet error mask */
+#define USB_OTG_DOEPEACHMSK1_BIM 0x00000200U /*!< BNA interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_BERRM 0x00001000U /*!< Bubble error interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_NAKM 0x00002000U /*!< NAK interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_NYETM 0x00004000U /*!< NYET interrupt mask */
+
+/******************** Bit definition forUSB_OTG_HPTXFSIZ register ********************/
+#define USB_OTG_HPTXFSIZ_PTXSA 0x0000FFFFU /*!< Host periodic TxFIFO start address */
+#define USB_OTG_HPTXFSIZ_PTXFD 0xFFFF0000U /*!< Host periodic TxFIFO depth */
+
+/******************** Bit definition forUSB_OTG_DIEPCTL register ********************/
+#define USB_OTG_DIEPCTL_MPSIZ 0x000007FFU /*!< Maximum packet size */
+#define USB_OTG_DIEPCTL_USBAEP 0x00008000U /*!< USB active endpoint */
+#define USB_OTG_DIEPCTL_EONUM_DPID 0x00010000U /*!< Even/odd frame */
+#define USB_OTG_DIEPCTL_NAKSTS 0x00020000U /*!< NAK status */
+
+#define USB_OTG_DIEPCTL_EPTYP 0x000C0000U /*!< Endpoint type */
+#define USB_OTG_DIEPCTL_EPTYP_0 0x00040000U /*!<Bit 0 */
+#define USB_OTG_DIEPCTL_EPTYP_1 0x00080000U /*!<Bit 1 */
+#define USB_OTG_DIEPCTL_STALL 0x00200000U /*!< STALL handshake */
+
+#define USB_OTG_DIEPCTL_TXFNUM 0x03C00000U /*!< TxFIFO number */
+#define USB_OTG_DIEPCTL_TXFNUM_0 0x00400000U /*!<Bit 0 */
+#define USB_OTG_DIEPCTL_TXFNUM_1 0x00800000U /*!<Bit 1 */
+#define USB_OTG_DIEPCTL_TXFNUM_2 0x01000000U /*!<Bit 2 */
+#define USB_OTG_DIEPCTL_TXFNUM_3 0x02000000U /*!<Bit 3 */
+#define USB_OTG_DIEPCTL_CNAK 0x04000000U /*!< Clear NAK */
+#define USB_OTG_DIEPCTL_SNAK 0x08000000U /*!< Set NAK */
+#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM 0x10000000U /*!< Set DATA0 PID */
+#define USB_OTG_DIEPCTL_SODDFRM 0x20000000U /*!< Set odd frame */
+#define USB_OTG_DIEPCTL_EPDIS 0x40000000U /*!< Endpoint disable */
+#define USB_OTG_DIEPCTL_EPENA 0x80000000U /*!< Endpoint enable */
+
+/******************** Bit definition forUSB_OTG_HCCHAR register ********************/
+#define USB_OTG_HCCHAR_MPSIZ 0x000007FFU /*!< Maximum packet size */
+
+#define USB_OTG_HCCHAR_EPNUM 0x00007800U /*!< Endpoint number */
+#define USB_OTG_HCCHAR_EPNUM_0 0x00000800U /*!<Bit 0 */
+#define USB_OTG_HCCHAR_EPNUM_1 0x00001000U /*!<Bit 1 */
+#define USB_OTG_HCCHAR_EPNUM_2 0x00002000U /*!<Bit 2 */
+#define USB_OTG_HCCHAR_EPNUM_3 0x00004000U /*!<Bit 3 */
+#define USB_OTG_HCCHAR_EPDIR 0x00008000U /*!< Endpoint direction */
+#define USB_OTG_HCCHAR_LSDEV 0x00020000U /*!< Low-speed device */
+
+#define USB_OTG_HCCHAR_EPTYP 0x000C0000U /*!< Endpoint type */
+#define USB_OTG_HCCHAR_EPTYP_0 0x00040000U /*!<Bit 0 */
+#define USB_OTG_HCCHAR_EPTYP_1 0x00080000U /*!<Bit 1 */
+
+#define USB_OTG_HCCHAR_MC 0x00300000U /*!< Multi Count (MC) / Error Count (EC) */
+#define USB_OTG_HCCHAR_MC_0 0x00100000U /*!<Bit 0 */
+#define USB_OTG_HCCHAR_MC_1 0x00200000U /*!<Bit 1 */
+
+#define USB_OTG_HCCHAR_DAD 0x1FC00000U /*!< Device address */
+#define USB_OTG_HCCHAR_DAD_0 0x00400000U /*!<Bit 0 */
+#define USB_OTG_HCCHAR_DAD_1 0x00800000U /*!<Bit 1 */
+#define USB_OTG_HCCHAR_DAD_2 0x01000000U /*!<Bit 2 */
+#define USB_OTG_HCCHAR_DAD_3 0x02000000U /*!<Bit 3 */
+#define USB_OTG_HCCHAR_DAD_4 0x04000000U /*!<Bit 4 */
+#define USB_OTG_HCCHAR_DAD_5 0x08000000U /*!<Bit 5 */
+#define USB_OTG_HCCHAR_DAD_6 0x10000000U /*!<Bit 6 */
+#define USB_OTG_HCCHAR_ODDFRM 0x20000000U /*!< Odd frame */
+#define USB_OTG_HCCHAR_CHDIS 0x40000000U /*!< Channel disable */
+#define USB_OTG_HCCHAR_CHENA 0x80000000U /*!< Channel enable */
+
+/******************** Bit definition forUSB_OTG_HCSPLT register ********************/
+
+#define USB_OTG_HCSPLT_PRTADDR 0x0000007FU /*!< Port address */
+#define USB_OTG_HCSPLT_PRTADDR_0 0x00000001U /*!<Bit 0 */
+#define USB_OTG_HCSPLT_PRTADDR_1 0x00000002U /*!<Bit 1 */
+#define USB_OTG_HCSPLT_PRTADDR_2 0x00000004U /*!<Bit 2 */
+#define USB_OTG_HCSPLT_PRTADDR_3 0x00000008U /*!<Bit 3 */
+#define USB_OTG_HCSPLT_PRTADDR_4 0x00000010U /*!<Bit 4 */
+#define USB_OTG_HCSPLT_PRTADDR_5 0x00000020U /*!<Bit 5 */
+#define USB_OTG_HCSPLT_PRTADDR_6 0x00000040U /*!<Bit 6 */
+
+#define USB_OTG_HCSPLT_HUBADDR 0x00003F80U /*!< Hub address */
+#define USB_OTG_HCSPLT_HUBADDR_0 0x00000080U /*!<Bit 0 */
+#define USB_OTG_HCSPLT_HUBADDR_1 0x00000100U /*!<Bit 1 */
+#define USB_OTG_HCSPLT_HUBADDR_2 0x00000200U /*!<Bit 2 */
+#define USB_OTG_HCSPLT_HUBADDR_3 0x00000400U /*!<Bit 3 */
+#define USB_OTG_HCSPLT_HUBADDR_4 0x00000800U /*!<Bit 4 */
+#define USB_OTG_HCSPLT_HUBADDR_5 0x00001000U /*!<Bit 5 */
+#define USB_OTG_HCSPLT_HUBADDR_6 0x00002000U /*!<Bit 6 */
+
+#define USB_OTG_HCSPLT_XACTPOS 0x0000C000U /*!< XACTPOS */
+#define USB_OTG_HCSPLT_XACTPOS_0 0x00004000U /*!<Bit 0 */
+#define USB_OTG_HCSPLT_XACTPOS_1 0x00008000U /*!<Bit 1 */
+#define USB_OTG_HCSPLT_COMPLSPLT 0x00010000U /*!< Do complete split */
+#define USB_OTG_HCSPLT_SPLITEN 0x80000000U /*!< Split enable */
+
+/******************** Bit definition forUSB_OTG_HCINT register ********************/
+#define USB_OTG_HCINT_XFRC 0x00000001U /*!< Transfer completed */
+#define USB_OTG_HCINT_CHH 0x00000002U /*!< Channel halted */
+#define USB_OTG_HCINT_AHBERR 0x00000004U /*!< AHB error */
+#define USB_OTG_HCINT_STALL 0x00000008U /*!< STALL response received interrupt */
+#define USB_OTG_HCINT_NAK 0x00000010U /*!< NAK response received interrupt */
+#define USB_OTG_HCINT_ACK 0x00000020U /*!< ACK response received/transmitted interrupt */
+#define USB_OTG_HCINT_NYET 0x00000040U /*!< Response received interrupt */
+#define USB_OTG_HCINT_TXERR 0x00000080U /*!< Transaction error */
+#define USB_OTG_HCINT_BBERR 0x00000100U /*!< Babble error */
+#define USB_OTG_HCINT_FRMOR 0x00000200U /*!< Frame overrun */
+#define USB_OTG_HCINT_DTERR 0x00000400U /*!< Data toggle error */
+
+/******************** Bit definition forUSB_OTG_DIEPINT register ********************/
+#define USB_OTG_DIEPINT_XFRC 0x00000001U /*!< Transfer completed interrupt */
+#define USB_OTG_DIEPINT_EPDISD 0x00000002U /*!< Endpoint disabled interrupt */
+#define USB_OTG_DIEPINT_TOC 0x00000008U /*!< Timeout condition */
+#define USB_OTG_DIEPINT_ITTXFE 0x00000010U /*!< IN token received when TxFIFO is empty */
+#define USB_OTG_DIEPINT_INEPNE 0x00000040U /*!< IN endpoint NAK effective */
+#define USB_OTG_DIEPINT_TXFE 0x00000080U /*!< Transmit FIFO empty */
+#define USB_OTG_DIEPINT_TXFIFOUDRN 0x00000100U /*!< Transmit Fifo Underrun */
+#define USB_OTG_DIEPINT_BNA 0x00000200U /*!< Buffer not available interrupt */
+#define USB_OTG_DIEPINT_PKTDRPSTS 0x00000800U /*!< Packet dropped status */
+#define USB_OTG_DIEPINT_BERR 0x00001000U /*!< Babble error interrupt */
+#define USB_OTG_DIEPINT_NAK 0x00002000U /*!< NAK interrupt */
+
+/******************** Bit definition forUSB_OTG_HCINTMSK register ********************/
+#define USB_OTG_HCINTMSK_XFRCM 0x00000001U /*!< Transfer completed mask */
+#define USB_OTG_HCINTMSK_CHHM 0x00000002U /*!< Channel halted mask */
+#define USB_OTG_HCINTMSK_AHBERR 0x00000004U /*!< AHB error */
+#define USB_OTG_HCINTMSK_STALLM 0x00000008U /*!< STALL response received interrupt mask */
+#define USB_OTG_HCINTMSK_NAKM 0x00000010U /*!< NAK response received interrupt mask */
+#define USB_OTG_HCINTMSK_ACKM 0x00000020U /*!< ACK response received/transmitted interrupt mask */
+#define USB_OTG_HCINTMSK_NYET 0x00000040U /*!< response received interrupt mask */
+#define USB_OTG_HCINTMSK_TXERRM 0x00000080U /*!< Transaction error mask */
+#define USB_OTG_HCINTMSK_BBERRM 0x00000100U /*!< Babble error mask */
+#define USB_OTG_HCINTMSK_FRMORM 0x00000200U /*!< Frame overrun mask */
+#define USB_OTG_HCINTMSK_DTERRM 0x00000400U /*!< Data toggle error mask */
+
+/******************** Bit definition for USB_OTG_DIEPTSIZ register ********************/
+
+#define USB_OTG_DIEPTSIZ_XFRSIZ 0x0007FFFFU /*!< Transfer size */
+#define USB_OTG_DIEPTSIZ_PKTCNT 0x1FF80000U /*!< Packet count */
+#define USB_OTG_DIEPTSIZ_MULCNT 0x60000000U /*!< Packet count */
+/******************** Bit definition forUSB_OTG_HCTSIZ register ********************/
+#define USB_OTG_HCTSIZ_XFRSIZ 0x0007FFFFU /*!< Transfer size */
+#define USB_OTG_HCTSIZ_PKTCNT 0x1FF80000U /*!< Packet count */
+#define USB_OTG_HCTSIZ_DOPING 0x80000000U /*!< Do PING */
+#define USB_OTG_HCTSIZ_DPID 0x60000000U /*!< Data PID */
+#define USB_OTG_HCTSIZ_DPID_0 0x20000000U /*!<Bit 0 */
+#define USB_OTG_HCTSIZ_DPID_1 0x40000000U /*!<Bit 1 */
+
+/******************** Bit definition forUSB_OTG_DIEPDMA register ********************/
+#define USB_OTG_DIEPDMA_DMAADDR 0xFFFFFFFFU /*!< DMA address */
+
+/******************** Bit definition forUSB_OTG_HCDMA register ********************/
+#define USB_OTG_HCDMA_DMAADDR 0xFFFFFFFFU /*!< DMA address */
+
+/******************** Bit definition forUSB_OTG_DTXFSTS register ********************/
+#define USB_OTG_DTXFSTS_INEPTFSAV 0x0000FFFFU /*!< IN endpoint TxFIFO space avail */
+
+/******************** Bit definition forUSB_OTG_DIEPTXF register ********************/
+#define USB_OTG_DIEPTXF_INEPTXSA 0x0000FFFFU /*!< IN endpoint FIFOx transmit RAM start address */
+#define USB_OTG_DIEPTXF_INEPTXFD 0xFFFF0000U /*!< IN endpoint TxFIFO depth */
+
+/******************** Bit definition forUSB_OTG_DOEPCTL register ********************/
+
+#define USB_OTG_DOEPCTL_MPSIZ 0x000007FFU /*!< Maximum packet size */ /*!<Bit 1 */
+#define USB_OTG_DOEPCTL_USBAEP 0x00008000U /*!< USB active endpoint */
+#define USB_OTG_DOEPCTL_NAKSTS 0x00020000U /*!< NAK status */
+#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM 0x10000000U /*!< Set DATA0 PID */
+#define USB_OTG_DOEPCTL_SODDFRM 0x20000000U /*!< Set odd frame */
+#define USB_OTG_DOEPCTL_EPTYP 0x000C0000U /*!< Endpoint type */
+#define USB_OTG_DOEPCTL_EPTYP_0 0x00040000U /*!<Bit 0 */
+#define USB_OTG_DOEPCTL_EPTYP_1 0x00080000U /*!<Bit 1 */
+#define USB_OTG_DOEPCTL_SNPM 0x00100000U /*!< Snoop mode */
+#define USB_OTG_DOEPCTL_STALL 0x00200000U /*!< STALL handshake */
+#define USB_OTG_DOEPCTL_CNAK 0x04000000U /*!< Clear NAK */
+#define USB_OTG_DOEPCTL_SNAK 0x08000000U /*!< Set NAK */
+#define USB_OTG_DOEPCTL_EPDIS 0x40000000U /*!< Endpoint disable */
+#define USB_OTG_DOEPCTL_EPENA 0x80000000U /*!< Endpoint enable */
+
+/******************** Bit definition forUSB_OTG_DOEPINT register ********************/
+#define USB_OTG_DOEPINT_XFRC 0x00000001U /*!< Transfer completed interrupt */
+#define USB_OTG_DOEPINT_EPDISD 0x00000002U /*!< Endpoint disabled interrupt */
+#define USB_OTG_DOEPINT_STUP 0x00000008U /*!< SETUP phase done */
+#define USB_OTG_DOEPINT_OTEPDIS 0x00000010U /*!< OUT token received when endpoint disabled */
+#define USB_OTG_DOEPINT_B2BSTUP 0x00000040U /*!< Back-to-back SETUP packets received */
+#define USB_OTG_DOEPINT_NYET 0x00004000U /*!< NYET interrupt */
+
+/******************** Bit definition forUSB_OTG_DOEPTSIZ register ********************/
+
+#define USB_OTG_DOEPTSIZ_XFRSIZ 0x0007FFFFU /*!< Transfer size */
+#define USB_OTG_DOEPTSIZ_PKTCNT 0x1FF80000U /*!< Packet count */
+
+#define USB_OTG_DOEPTSIZ_STUPCNT 0x60000000U /*!< SETUP packet count */
+#define USB_OTG_DOEPTSIZ_STUPCNT_0 0x20000000U /*!<Bit 0 */
+#define USB_OTG_DOEPTSIZ_STUPCNT_1 0x40000000U /*!<Bit 1 */
+
+/******************** Bit definition for PCGCCTL register ********************/
+#define USB_OTG_PCGCCTL_STOPCLK 0x00000001U /*!< SETUP packet count */
+#define USB_OTG_PCGCCTL_GATECLK 0x00000002U /*!<Bit 0 */
+#define USB_OTG_PCGCCTL_PHYSUSP 0x00000010U /*!<Bit 1 */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup Exported_macros
+ * @{
+ */
+
+/******************************* ADC Instances ********************************/
+#define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) || \
+ ((INSTANCE) == ADC2) || \
+ ((INSTANCE) == ADC3))
+
+/******************************* CAN Instances ********************************/
+#define IS_CAN_ALL_INSTANCE(INSTANCE) (((INSTANCE) == CAN1) || \
+ ((INSTANCE) == CAN2))
+
+/******************************* CRC Instances ********************************/
+#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
+
+/******************************* DAC Instances ********************************/
+#define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC)
+
+/******************************* DCMI Instances *******************************/
+#define IS_DCMI_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DCMI)
+
+/******************************** DMA Instances *******************************/
+#define IS_DMA_STREAM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0) || \
+ ((INSTANCE) == DMA1_Stream1) || \
+ ((INSTANCE) == DMA1_Stream2) || \
+ ((INSTANCE) == DMA1_Stream3) || \
+ ((INSTANCE) == DMA1_Stream4) || \
+ ((INSTANCE) == DMA1_Stream5) || \
+ ((INSTANCE) == DMA1_Stream6) || \
+ ((INSTANCE) == DMA1_Stream7) || \
+ ((INSTANCE) == DMA2_Stream0) || \
+ ((INSTANCE) == DMA2_Stream1) || \
+ ((INSTANCE) == DMA2_Stream2) || \
+ ((INSTANCE) == DMA2_Stream3) || \
+ ((INSTANCE) == DMA2_Stream4) || \
+ ((INSTANCE) == DMA2_Stream5) || \
+ ((INSTANCE) == DMA2_Stream6) || \
+ ((INSTANCE) == DMA2_Stream7))
+
+/******************************* GPIO Instances *******************************/
+#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
+ ((INSTANCE) == GPIOB) || \
+ ((INSTANCE) == GPIOC) || \
+ ((INSTANCE) == GPIOD) || \
+ ((INSTANCE) == GPIOE) || \
+ ((INSTANCE) == GPIOF) || \
+ ((INSTANCE) == GPIOG) || \
+ ((INSTANCE) == GPIOH) || \
+ ((INSTANCE) == GPIOI))
+
+/******************************** I2C Instances *******************************/
+#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
+ ((INSTANCE) == I2C2) || \
+ ((INSTANCE) == I2C3))
+
+/******************************** I2S Instances *******************************/
+#define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI2) || \
+ ((INSTANCE) == SPI3))
+
+/*************************** I2S Extended Instances ***************************/
+#define IS_I2S_ALL_INSTANCE_EXT(PERIPH) (((INSTANCE) == SPI2) || \
+ ((INSTANCE) == SPI3) || \
+ ((INSTANCE) == I2S2ext) || \
+ ((INSTANCE) == I2S3ext))
+
+/******************************* RNG Instances ********************************/
+#define IS_RNG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RNG)
+
+/****************************** RTC Instances *********************************/
+#define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
+
+/******************************** SPI Instances *******************************/
+#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
+ ((INSTANCE) == SPI2) || \
+ ((INSTANCE) == SPI3))
+
+/*************************** SPI Extended Instances ***************************/
+#define IS_SPI_ALL_INSTANCE_EXT(INSTANCE) (((INSTANCE) == SPI1) || \
+ ((INSTANCE) == SPI2) || \
+ ((INSTANCE) == SPI3) || \
+ ((INSTANCE) == I2S2ext) || \
+ ((INSTANCE) == I2S3ext))
+
+/****************** TIM Instances : All supported instances *******************/
+#define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM6) || \
+ ((INSTANCE) == TIM7) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM9) || \
+ ((INSTANCE) == TIM10) || \
+ ((INSTANCE) == TIM11) || \
+ ((INSTANCE) == TIM12) || \
+ ((INSTANCE) == TIM13) || \
+ ((INSTANCE) == TIM14))
+
+/************* TIM Instances : at least 1 capture/compare channel *************/
+#define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM9) || \
+ ((INSTANCE) == TIM10) || \
+ ((INSTANCE) == TIM11) || \
+ ((INSTANCE) == TIM12) || \
+ ((INSTANCE) == TIM13) || \
+ ((INSTANCE) == TIM14))
+
+/************ TIM Instances : at least 2 capture/compare channels *************/
+#define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM9) || \
+ ((INSTANCE) == TIM12))
+
+/************ TIM Instances : at least 3 capture/compare channels *************/
+#define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8))
+
+/************ TIM Instances : at least 4 capture/compare channels *************/
+#define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8))
+
+/******************** TIM Instances : Advanced-control timers *****************/
+#define IS_TIM_ADVANCED_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM8))
+
+/******************* TIM Instances : Timer input XOR function *****************/
+#define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8))
+
+/****************** TIM Instances : DMA requests generation (UDE) *************/
+#define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM6) || \
+ ((INSTANCE) == TIM7) || \
+ ((INSTANCE) == TIM8))
+
+/************ TIM Instances : DMA requests generation (CCxDE) *****************/
+#define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8))
+
+/************ TIM Instances : DMA requests generation (COMDE) *****************/
+#define IS_TIM_CCDMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8))
+
+/******************** TIM Instances : DMA burst feature ***********************/
+#define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8))
+
+/****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/
+#define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM6) || \
+ ((INSTANCE) == TIM7) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM9) || \
+ ((INSTANCE) == TIM12))
+
+/*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
+#define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM9) || \
+ ((INSTANCE) == TIM12))
+
+/********************** TIM Instances : 32 bit Counter ************************/
+#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)(((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM5))
+
+/***************** TIM Instances : external trigger input availabe ************/
+#define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8))
+
+/****************** TIM Instances : remapping capability **********************/
+#define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM11))
+
+/******************* TIM Instances : output(s) available **********************/
+#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
+ ((((INSTANCE) == TIM1) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM2) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM3) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM4) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM5) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM8) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM9) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2))) \
+ || \
+ (((INSTANCE) == TIM10) && \
+ (((CHANNEL) == TIM_CHANNEL_1))) \
+ || \
+ (((INSTANCE) == TIM11) && \
+ (((CHANNEL) == TIM_CHANNEL_1))) \
+ || \
+ (((INSTANCE) == TIM12) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2))) \
+ || \
+ (((INSTANCE) == TIM13) && \
+ (((CHANNEL) == TIM_CHANNEL_1))) \
+ || \
+ (((INSTANCE) == TIM14) && \
+ (((CHANNEL) == TIM_CHANNEL_1))))
+
+/************ TIM Instances : complementary output(s) available ***************/
+#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
+ ((((INSTANCE) == TIM1) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3))) \
+ || \
+ (((INSTANCE) == TIM8) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3))))
+
+/******************** USART Instances : Synchronous mode **********************/
+#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3) || \
+ ((INSTANCE) == USART6))
+
+/******************** UART Instances : Asynchronous mode **********************/
+#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3) || \
+ ((INSTANCE) == UART4) || \
+ ((INSTANCE) == UART5) || \
+ ((INSTANCE) == USART6))
+
+/****************** UART Instances : Hardware Flow control ********************/
+#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3) || \
+ ((INSTANCE) == USART6))
+
+/********************* UART Instances : Smard card mode ***********************/
+#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3) || \
+ ((INSTANCE) == USART6))
+
+/*********************** UART Instances : IRDA mode ***************************/
+#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3) || \
+ ((INSTANCE) == UART4) || \
+ ((INSTANCE) == UART5) || \
+ ((INSTANCE) == USART6))
+
+/*********************** PCD Instances ****************************************/
+/*********************** PCD Instances ****************************************/
+#define IS_PCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS) || \
+ ((INSTANCE) == USB_OTG_HS))
+
+/*********************** HCD Instances ****************************************/
+#define IS_HCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS) || \
+ ((INSTANCE) == USB_OTG_HS))
+
+/****************************** IWDG Instances ********************************/
+#define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
+
+/****************************** WWDG Instances ********************************/
+#define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
+
+/****************************** SDIO Instances ********************************/
+#define IS_SDIO_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SDIO)
+
+/****************************** USB Exported Constants ************************/
+#define USB_OTG_FS_HOST_MAX_CHANNEL_NBR 8U
+#define USB_OTG_FS_MAX_IN_ENDPOINTS 4U /* Including EP0 */
+#define USB_OTG_FS_MAX_OUT_ENDPOINTS 4U /* Including EP0 */
+#define USB_OTG_FS_TOTAL_FIFO_SIZE 1280U /* in Bytes */
+
+#define USB_OTG_HS_HOST_MAX_CHANNEL_NBR 12U
+#define USB_OTG_HS_MAX_IN_ENDPOINTS 6U /* Including EP0 */
+#define USB_OTG_HS_MAX_OUT_ENDPOINTS 6U /* Including EP0 */
+#define USB_OTG_HS_TOTAL_FIFO_SIZE 4096U /* in Bytes */
+
+/******************************************************************************/
+/* For a painless codes migration between the STM32F4xx device product */
+/* lines, the aliases defined below are put in place to overcome the */
+/* differences in the interrupt handlers and IRQn definitions. */
+/* No need to update developed interrupt code when moving across */
+/* product lines within the same STM32F4 Family */
+/******************************************************************************/
+
+/* Aliases for __IRQn */
+#define FMC_IRQn FSMC_IRQn
+
+/* Aliases for __IRQHandler */
+#define FMC_IRQHandler FSMC_IRQHandler
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* __STM32F4xx_H */
+
+
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Device/ST/STM32F4xx/Include/stm32f427xx.h b/Device/ST/STM32F4xx/Include/stm32f427xx.h
new file mode 100644
index 0000000..164adfa
--- /dev/null
+++ b/Device/ST/STM32F4xx/Include/stm32f427xx.h
@@ -0,0 +1,8901 @@
+/**
+ ******************************************************************************
+ * @file stm32f427xx.h
+ * @author MCD Application Team
+ * @version V2.5.0
+ * @date 22-April-2016
+ * @brief CMSIS STM32F427xx Device Peripheral Access Layer Header File.
+ *
+ * This file contains:
+ * - Data structures and the address mapping for all peripherals
+ * - peripherals registers declarations and bits definition
+ * - Macros to access peripheral’s registers hardware
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/** @addtogroup CMSIS_Device
+ * @{
+ */
+
+/** @addtogroup stm32f427xx
+ * @{
+ */
+
+#ifndef __stm32f427xx_H
+#define __stm32f427xx_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif /* __cplusplus */
+
+/** @addtogroup Configuration_section_for_CMSIS
+ * @{
+ */
+
+/**
+ * @brief Configuration of the Cortex-M4 Processor and Core Peripherals
+ */
+#define __CM4_REV 0x0001U /*!< Core revision r0p1 */
+#define __MPU_PRESENT 1U /*!< STM32F4XX provides an MPU */
+#define __NVIC_PRIO_BITS 4U /*!< STM32F4XX uses 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */
+#define __FPU_PRESENT 1U /*!< FPU present */
+
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_interrupt_number_definition
+ * @{
+ */
+
+/**
+ * @brief STM32F4XX Interrupt Number Definition, according to the selected device
+ * in @ref Library_configuration_section
+ */
+typedef enum
+{
+/****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/
+ NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
+ MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */
+ BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */
+ UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */
+ SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */
+ DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */
+ PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */
+ SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */
+/****** STM32 specific Interrupt Numbers **********************************************************************/
+ WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
+ PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */
+ TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */
+ RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */
+ FLASH_IRQn = 4, /*!< FLASH global Interrupt */
+ RCC_IRQn = 5, /*!< RCC global Interrupt */
+ EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */
+ EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */
+ EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */
+ EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */
+ EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */
+ DMA1_Stream0_IRQn = 11, /*!< DMA1 Stream 0 global Interrupt */
+ DMA1_Stream1_IRQn = 12, /*!< DMA1 Stream 1 global Interrupt */
+ DMA1_Stream2_IRQn = 13, /*!< DMA1 Stream 2 global Interrupt */
+ DMA1_Stream3_IRQn = 14, /*!< DMA1 Stream 3 global Interrupt */
+ DMA1_Stream4_IRQn = 15, /*!< DMA1 Stream 4 global Interrupt */
+ DMA1_Stream5_IRQn = 16, /*!< DMA1 Stream 5 global Interrupt */
+ DMA1_Stream6_IRQn = 17, /*!< DMA1 Stream 6 global Interrupt */
+ ADC_IRQn = 18, /*!< ADC1, ADC2 and ADC3 global Interrupts */
+ CAN1_TX_IRQn = 19, /*!< CAN1 TX Interrupt */
+ CAN1_RX0_IRQn = 20, /*!< CAN1 RX0 Interrupt */
+ CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */
+ CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */
+ EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
+ TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break interrupt and TIM9 global interrupt */
+ TIM1_UP_TIM10_IRQn = 25, /*!< TIM1 Update Interrupt and TIM10 global interrupt */
+ TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */
+ TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
+ TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
+ TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
+ TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
+ I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
+ I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
+ I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
+ I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
+ SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
+ SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
+ USART1_IRQn = 37, /*!< USART1 global Interrupt */
+ USART2_IRQn = 38, /*!< USART2 global Interrupt */
+ USART3_IRQn = 39, /*!< USART3 global Interrupt */
+ EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
+ RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */
+ OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS Wakeup through EXTI line interrupt */
+ TIM8_BRK_TIM12_IRQn = 43, /*!< TIM8 Break Interrupt and TIM12 global interrupt */
+ TIM8_UP_TIM13_IRQn = 44, /*!< TIM8 Update Interrupt and TIM13 global interrupt */
+ TIM8_TRG_COM_TIM14_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */
+ TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */
+ DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */
+ FMC_IRQn = 48, /*!< FMC global Interrupt */
+ SDIO_IRQn = 49, /*!< SDIO global Interrupt */
+ TIM5_IRQn = 50, /*!< TIM5 global Interrupt */
+ SPI3_IRQn = 51, /*!< SPI3 global Interrupt */
+ UART4_IRQn = 52, /*!< UART4 global Interrupt */
+ UART5_IRQn = 53, /*!< UART5 global Interrupt */
+ TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC1&2 underrun error interrupts */
+ TIM7_IRQn = 55, /*!< TIM7 global interrupt */
+ DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */
+ DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */
+ DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */
+ DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */
+ DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */
+ ETH_IRQn = 61, /*!< Ethernet global Interrupt */
+ ETH_WKUP_IRQn = 62, /*!< Ethernet Wakeup through EXTI line Interrupt */
+ CAN2_TX_IRQn = 63, /*!< CAN2 TX Interrupt */
+ CAN2_RX0_IRQn = 64, /*!< CAN2 RX0 Interrupt */
+ CAN2_RX1_IRQn = 65, /*!< CAN2 RX1 Interrupt */
+ CAN2_SCE_IRQn = 66, /*!< CAN2 SCE Interrupt */
+ OTG_FS_IRQn = 67, /*!< USB OTG FS global Interrupt */
+ DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */
+ DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */
+ DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */
+ USART6_IRQn = 71, /*!< USART6 global interrupt */
+ I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */
+ I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */
+ OTG_HS_EP1_OUT_IRQn = 74, /*!< USB OTG HS End Point 1 Out global interrupt */
+ OTG_HS_EP1_IN_IRQn = 75, /*!< USB OTG HS End Point 1 In global interrupt */
+ OTG_HS_WKUP_IRQn = 76, /*!< USB OTG HS Wakeup through EXTI interrupt */
+ OTG_HS_IRQn = 77, /*!< USB OTG HS global interrupt */
+ DCMI_IRQn = 78, /*!< DCMI global interrupt */
+ HASH_RNG_IRQn = 80, /*!< Hash and RNG global interrupt */
+ FPU_IRQn = 81, /*!< FPU global interrupt */
+ UART7_IRQn = 82, /*!< UART7 global interrupt */
+ UART8_IRQn = 83, /*!< UART8 global interrupt */
+ SPI4_IRQn = 84, /*!< SPI4 global Interrupt */
+ SPI5_IRQn = 85, /*!< SPI5 global Interrupt */
+ SPI6_IRQn = 86, /*!< SPI6 global Interrupt */
+ SAI1_IRQn = 87, /*!< SAI1 global Interrupt */
+ DMA2D_IRQn = 90 /*!< DMA2D global Interrupt */
+} IRQn_Type;
+
+/**
+ * @}
+ */
+
+#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
+#include "system_stm32f4xx.h"
+#include <stdint.h>
+
+/** @addtogroup Peripheral_registers_structures
+ * @{
+ */
+
+/**
+ * @brief Analog to Digital Converter
+ */
+
+typedef struct
+{
+ __IO uint32_t SR; /*!< ADC status register, Address offset: 0x00 */
+ __IO uint32_t CR1; /*!< ADC control register 1, Address offset: 0x04 */
+ __IO uint32_t CR2; /*!< ADC control register 2, Address offset: 0x08 */
+ __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x0C */
+ __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x10 */
+ __IO uint32_t JOFR1; /*!< ADC injected channel data offset register 1, Address offset: 0x14 */
+ __IO uint32_t JOFR2; /*!< ADC injected channel data offset register 2, Address offset: 0x18 */
+ __IO uint32_t JOFR3; /*!< ADC injected channel data offset register 3, Address offset: 0x1C */
+ __IO uint32_t JOFR4; /*!< ADC injected channel data offset register 4, Address offset: 0x20 */
+ __IO uint32_t HTR; /*!< ADC watchdog higher threshold register, Address offset: 0x24 */
+ __IO uint32_t LTR; /*!< ADC watchdog lower threshold register, Address offset: 0x28 */
+ __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x2C */
+ __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x30 */
+ __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x34 */
+ __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x38*/
+ __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x3C */
+ __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x40 */
+ __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x44 */
+ __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x48 */
+ __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x4C */
+} ADC_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1 base address + 0x300 */
+ __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1 base address + 0x304 */
+ __IO uint32_t CDR; /*!< ADC common regular data register for dual
+ AND triple modes, Address offset: ADC1 base address + 0x308 */
+} ADC_Common_TypeDef;
+
+
+/**
+ * @brief Controller Area Network TxMailBox
+ */
+
+typedef struct
+{
+ __IO uint32_t TIR; /*!< CAN TX mailbox identifier register */
+ __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */
+ __IO uint32_t TDLR; /*!< CAN mailbox data low register */
+ __IO uint32_t TDHR; /*!< CAN mailbox data high register */
+} CAN_TxMailBox_TypeDef;
+
+/**
+ * @brief Controller Area Network FIFOMailBox
+ */
+
+typedef struct
+{
+ __IO uint32_t RIR; /*!< CAN receive FIFO mailbox identifier register */
+ __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */
+ __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */
+ __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */
+} CAN_FIFOMailBox_TypeDef;
+
+/**
+ * @brief Controller Area Network FilterRegister
+ */
+
+typedef struct
+{
+ __IO uint32_t FR1; /*!< CAN Filter bank register 1 */
+ __IO uint32_t FR2; /*!< CAN Filter bank register 1 */
+} CAN_FilterRegister_TypeDef;
+
+/**
+ * @brief Controller Area Network
+ */
+
+typedef struct
+{
+ __IO uint32_t MCR; /*!< CAN master control register, Address offset: 0x00 */
+ __IO uint32_t MSR; /*!< CAN master status register, Address offset: 0x04 */
+ __IO uint32_t TSR; /*!< CAN transmit status register, Address offset: 0x08 */
+ __IO uint32_t RF0R; /*!< CAN receive FIFO 0 register, Address offset: 0x0C */
+ __IO uint32_t RF1R; /*!< CAN receive FIFO 1 register, Address offset: 0x10 */
+ __IO uint32_t IER; /*!< CAN interrupt enable register, Address offset: 0x14 */
+ __IO uint32_t ESR; /*!< CAN error status register, Address offset: 0x18 */
+ __IO uint32_t BTR; /*!< CAN bit timing register, Address offset: 0x1C */
+ uint32_t RESERVED0[88]; /*!< Reserved, 0x020 - 0x17F */
+ CAN_TxMailBox_TypeDef sTxMailBox[3]; /*!< CAN Tx MailBox, Address offset: 0x180 - 0x1AC */
+ CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; /*!< CAN FIFO MailBox, Address offset: 0x1B0 - 0x1CC */
+ uint32_t RESERVED1[12]; /*!< Reserved, 0x1D0 - 0x1FF */
+ __IO uint32_t FMR; /*!< CAN filter master register, Address offset: 0x200 */
+ __IO uint32_t FM1R; /*!< CAN filter mode register, Address offset: 0x204 */
+ uint32_t RESERVED2; /*!< Reserved, 0x208 */
+ __IO uint32_t FS1R; /*!< CAN filter scale register, Address offset: 0x20C */
+ uint32_t RESERVED3; /*!< Reserved, 0x210 */
+ __IO uint32_t FFA1R; /*!< CAN filter FIFO assignment register, Address offset: 0x214 */
+ uint32_t RESERVED4; /*!< Reserved, 0x218 */
+ __IO uint32_t FA1R; /*!< CAN filter activation register, Address offset: 0x21C */
+ uint32_t RESERVED5[8]; /*!< Reserved, 0x220-0x23F */
+ CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register, Address offset: 0x240-0x31C */
+} CAN_TypeDef;
+
+/**
+ * @brief CRC calculation unit
+ */
+
+typedef struct
+{
+ __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
+ __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
+ uint8_t RESERVED0; /*!< Reserved, 0x05 */
+ uint16_t RESERVED1; /*!< Reserved, 0x06 */
+ __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
+} CRC_TypeDef;
+
+/**
+ * @brief Digital to Analog Converter
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */
+ __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */
+ __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
+ __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */
+ __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */
+ __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
+ __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */
+ __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */
+ __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */
+ __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */
+ __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */
+ __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */
+ __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */
+ __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */
+} DAC_TypeDef;
+
+/**
+ * @brief Debug MCU
+ */
+
+typedef struct
+{
+ __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
+ __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
+ __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */
+ __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */
+}DBGMCU_TypeDef;
+
+/**
+ * @brief DCMI
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< DCMI control register 1, Address offset: 0x00 */
+ __IO uint32_t SR; /*!< DCMI status register, Address offset: 0x04 */
+ __IO uint32_t RISR; /*!< DCMI raw interrupt status register, Address offset: 0x08 */
+ __IO uint32_t IER; /*!< DCMI interrupt enable register, Address offset: 0x0C */
+ __IO uint32_t MISR; /*!< DCMI masked interrupt status register, Address offset: 0x10 */
+ __IO uint32_t ICR; /*!< DCMI interrupt clear register, Address offset: 0x14 */
+ __IO uint32_t ESCR; /*!< DCMI embedded synchronization code register, Address offset: 0x18 */
+ __IO uint32_t ESUR; /*!< DCMI embedded synchronization unmask register, Address offset: 0x1C */
+ __IO uint32_t CWSTRTR; /*!< DCMI crop window start, Address offset: 0x20 */
+ __IO uint32_t CWSIZER; /*!< DCMI crop window size, Address offset: 0x24 */
+ __IO uint32_t DR; /*!< DCMI data register, Address offset: 0x28 */
+} DCMI_TypeDef;
+
+/**
+ * @brief DMA Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< DMA stream x configuration register */
+ __IO uint32_t NDTR; /*!< DMA stream x number of data register */
+ __IO uint32_t PAR; /*!< DMA stream x peripheral address register */
+ __IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */
+ __IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */
+ __IO uint32_t FCR; /*!< DMA stream x FIFO control register */
+} DMA_Stream_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t LISR; /*!< DMA low interrupt status register, Address offset: 0x00 */
+ __IO uint32_t HISR; /*!< DMA high interrupt status register, Address offset: 0x04 */
+ __IO uint32_t LIFCR; /*!< DMA low interrupt flag clear register, Address offset: 0x08 */
+ __IO uint32_t HIFCR; /*!< DMA high interrupt flag clear register, Address offset: 0x0C */
+} DMA_TypeDef;
+
+/**
+ * @brief DMA2D Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< DMA2D Control Register, Address offset: 0x00 */
+ __IO uint32_t ISR; /*!< DMA2D Interrupt Status Register, Address offset: 0x04 */
+ __IO uint32_t IFCR; /*!< DMA2D Interrupt Flag Clear Register, Address offset: 0x08 */
+ __IO uint32_t FGMAR; /*!< DMA2D Foreground Memory Address Register, Address offset: 0x0C */
+ __IO uint32_t FGOR; /*!< DMA2D Foreground Offset Register, Address offset: 0x10 */
+ __IO uint32_t BGMAR; /*!< DMA2D Background Memory Address Register, Address offset: 0x14 */
+ __IO uint32_t BGOR; /*!< DMA2D Background Offset Register, Address offset: 0x18 */
+ __IO uint32_t FGPFCCR; /*!< DMA2D Foreground PFC Control Register, Address offset: 0x1C */
+ __IO uint32_t FGCOLR; /*!< DMA2D Foreground Color Register, Address offset: 0x20 */
+ __IO uint32_t BGPFCCR; /*!< DMA2D Background PFC Control Register, Address offset: 0x24 */
+ __IO uint32_t BGCOLR; /*!< DMA2D Background Color Register, Address offset: 0x28 */
+ __IO uint32_t FGCMAR; /*!< DMA2D Foreground CLUT Memory Address Register, Address offset: 0x2C */
+ __IO uint32_t BGCMAR; /*!< DMA2D Background CLUT Memory Address Register, Address offset: 0x30 */
+ __IO uint32_t OPFCCR; /*!< DMA2D Output PFC Control Register, Address offset: 0x34 */
+ __IO uint32_t OCOLR; /*!< DMA2D Output Color Register, Address offset: 0x38 */
+ __IO uint32_t OMAR; /*!< DMA2D Output Memory Address Register, Address offset: 0x3C */
+ __IO uint32_t OOR; /*!< DMA2D Output Offset Register, Address offset: 0x40 */
+ __IO uint32_t NLR; /*!< DMA2D Number of Line Register, Address offset: 0x44 */
+ __IO uint32_t LWR; /*!< DMA2D Line Watermark Register, Address offset: 0x48 */
+ __IO uint32_t AMTCR; /*!< DMA2D AHB Master Timer Configuration Register, Address offset: 0x4C */
+ uint32_t RESERVED[236]; /*!< Reserved, 0x50-0x3FF */
+ __IO uint32_t FGCLUT[256]; /*!< DMA2D Foreground CLUT, Address offset:400-7FF */
+ __IO uint32_t BGCLUT[256]; /*!< DMA2D Background CLUT, Address offset:800-BFF */
+} DMA2D_TypeDef;
+
+/**
+ * @brief Ethernet MAC
+ */
+
+typedef struct
+{
+ __IO uint32_t MACCR;
+ __IO uint32_t MACFFR;
+ __IO uint32_t MACHTHR;
+ __IO uint32_t MACHTLR;
+ __IO uint32_t MACMIIAR;
+ __IO uint32_t MACMIIDR;
+ __IO uint32_t MACFCR;
+ __IO uint32_t MACVLANTR; /* 8 */
+ uint32_t RESERVED0[2];
+ __IO uint32_t MACRWUFFR; /* 11 */
+ __IO uint32_t MACPMTCSR;
+ uint32_t RESERVED1[2];
+ __IO uint32_t MACSR; /* 15 */
+ __IO uint32_t MACIMR;
+ __IO uint32_t MACA0HR;
+ __IO uint32_t MACA0LR;
+ __IO uint32_t MACA1HR;
+ __IO uint32_t MACA1LR;
+ __IO uint32_t MACA2HR;
+ __IO uint32_t MACA2LR;
+ __IO uint32_t MACA3HR;
+ __IO uint32_t MACA3LR; /* 24 */
+ uint32_t RESERVED2[40];
+ __IO uint32_t MMCCR; /* 65 */
+ __IO uint32_t MMCRIR;
+ __IO uint32_t MMCTIR;
+ __IO uint32_t MMCRIMR;
+ __IO uint32_t MMCTIMR; /* 69 */
+ uint32_t RESERVED3[14];
+ __IO uint32_t MMCTGFSCCR; /* 84 */
+ __IO uint32_t MMCTGFMSCCR;
+ uint32_t RESERVED4[5];
+ __IO uint32_t MMCTGFCR;
+ uint32_t RESERVED5[10];
+ __IO uint32_t MMCRFCECR;
+ __IO uint32_t MMCRFAECR;
+ uint32_t RESERVED6[10];
+ __IO uint32_t MMCRGUFCR;
+ uint32_t RESERVED7[334];
+ __IO uint32_t PTPTSCR;
+ __IO uint32_t PTPSSIR;
+ __IO uint32_t PTPTSHR;
+ __IO uint32_t PTPTSLR;
+ __IO uint32_t PTPTSHUR;
+ __IO uint32_t PTPTSLUR;
+ __IO uint32_t PTPTSAR;
+ __IO uint32_t PTPTTHR;
+ __IO uint32_t PTPTTLR;
+ __IO uint32_t RESERVED8;
+ __IO uint32_t PTPTSSR;
+ uint32_t RESERVED9[565];
+ __IO uint32_t DMABMR;
+ __IO uint32_t DMATPDR;
+ __IO uint32_t DMARPDR;
+ __IO uint32_t DMARDLAR;
+ __IO uint32_t DMATDLAR;
+ __IO uint32_t DMASR;
+ __IO uint32_t DMAOMR;
+ __IO uint32_t DMAIER;
+ __IO uint32_t DMAMFBOCR;
+ __IO uint32_t DMARSWTR;
+ uint32_t RESERVED10[8];
+ __IO uint32_t DMACHTDR;
+ __IO uint32_t DMACHRDR;
+ __IO uint32_t DMACHTBAR;
+ __IO uint32_t DMACHRBAR;
+} ETH_TypeDef;
+
+/**
+ * @brief External Interrupt/Event Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t IMR; /*!< EXTI Interrupt mask register, Address offset: 0x00 */
+ __IO uint32_t EMR; /*!< EXTI Event mask register, Address offset: 0x04 */
+ __IO uint32_t RTSR; /*!< EXTI Rising trigger selection register, Address offset: 0x08 */
+ __IO uint32_t FTSR; /*!< EXTI Falling trigger selection register, Address offset: 0x0C */
+ __IO uint32_t SWIER; /*!< EXTI Software interrupt event register, Address offset: 0x10 */
+ __IO uint32_t PR; /*!< EXTI Pending register, Address offset: 0x14 */
+} EXTI_TypeDef;
+
+/**
+ * @brief FLASH Registers
+ */
+
+typedef struct
+{
+ __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */
+ __IO uint32_t KEYR; /*!< FLASH key register, Address offset: 0x04 */
+ __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x08 */
+ __IO uint32_t SR; /*!< FLASH status register, Address offset: 0x0C */
+ __IO uint32_t CR; /*!< FLASH control register, Address offset: 0x10 */
+ __IO uint32_t OPTCR; /*!< FLASH option control register , Address offset: 0x14 */
+ __IO uint32_t OPTCR1; /*!< FLASH option control register 1, Address offset: 0x18 */
+} FLASH_TypeDef;
+
+/**
+ * @brief Flexible Memory Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */
+} FMC_Bank1_TypeDef;
+
+/**
+ * @brief Flexible Memory Controller Bank1E
+ */
+
+typedef struct
+{
+ __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */
+} FMC_Bank1E_TypeDef;
+
+/**
+ * @brief Flexible Memory Controller Bank2
+ */
+
+typedef struct
+{
+ __IO uint32_t PCR2; /*!< NAND Flash control register 2, Address offset: 0x60 */
+ __IO uint32_t SR2; /*!< NAND Flash FIFO status and interrupt register 2, Address offset: 0x64 */
+ __IO uint32_t PMEM2; /*!< NAND Flash Common memory space timing register 2, Address offset: 0x68 */
+ __IO uint32_t PATT2; /*!< NAND Flash Attribute memory space timing register 2, Address offset: 0x6C */
+ uint32_t RESERVED0; /*!< Reserved, 0x70 */
+ __IO uint32_t ECCR2; /*!< NAND Flash ECC result registers 2, Address offset: 0x74 */
+ uint32_t RESERVED1; /*!< Reserved, 0x78 */
+ uint32_t RESERVED2; /*!< Reserved, 0x7C */
+ __IO uint32_t PCR3; /*!< NAND Flash control register 3, Address offset: 0x80 */
+ __IO uint32_t SR3; /*!< NAND Flash FIFO status and interrupt register 3, Address offset: 0x84 */
+ __IO uint32_t PMEM3; /*!< NAND Flash Common memory space timing register 3, Address offset: 0x88 */
+ __IO uint32_t PATT3; /*!< NAND Flash Attribute memory space timing register 3, Address offset: 0x8C */
+ uint32_t RESERVED3; /*!< Reserved, 0x90 */
+ __IO uint32_t ECCR3; /*!< NAND Flash ECC result registers 3, Address offset: 0x94 */
+} FMC_Bank2_3_TypeDef;
+
+/**
+ * @brief Flexible Memory Controller Bank4
+ */
+
+typedef struct
+{
+ __IO uint32_t PCR4; /*!< PC Card control register 4, Address offset: 0xA0 */
+ __IO uint32_t SR4; /*!< PC Card FIFO status and interrupt register 4, Address offset: 0xA4 */
+ __IO uint32_t PMEM4; /*!< PC Card Common memory space timing register 4, Address offset: 0xA8 */
+ __IO uint32_t PATT4; /*!< PC Card Attribute memory space timing register 4, Address offset: 0xAC */
+ __IO uint32_t PIO4; /*!< PC Card I/O space timing register 4, Address offset: 0xB0 */
+} FMC_Bank4_TypeDef;
+
+/**
+ * @brief Flexible Memory Controller Bank5_6
+ */
+
+typedef struct
+{
+ __IO uint32_t SDCR[2]; /*!< SDRAM Control registers , Address offset: 0x140-0x144 */
+ __IO uint32_t SDTR[2]; /*!< SDRAM Timing registers , Address offset: 0x148-0x14C */
+ __IO uint32_t SDCMR; /*!< SDRAM Command Mode register, Address offset: 0x150 */
+ __IO uint32_t SDRTR; /*!< SDRAM Refresh Timer register, Address offset: 0x154 */
+ __IO uint32_t SDSR; /*!< SDRAM Status register, Address offset: 0x158 */
+} FMC_Bank5_6_TypeDef;
+
+/**
+ * @brief General Purpose I/O
+ */
+
+typedef struct
+{
+ __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
+ __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */
+ __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */
+ __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
+ __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
+ __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
+ __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */
+ __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
+ __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */
+} GPIO_TypeDef;
+
+/**
+ * @brief System configuration controller
+ */
+
+typedef struct
+{
+ __IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */
+ __IO uint32_t PMC; /*!< SYSCFG peripheral mode configuration register, Address offset: 0x04 */
+ __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
+ uint32_t RESERVED[2]; /*!< Reserved, 0x18-0x1C */
+ __IO uint32_t CMPCR; /*!< SYSCFG Compensation cell control register, Address offset: 0x20 */
+} SYSCFG_TypeDef;
+
+/**
+ * @brief Inter-integrated Circuit Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */
+ __IO uint32_t OAR1; /*!< I2C Own address register 1, Address offset: 0x08 */
+ __IO uint32_t OAR2; /*!< I2C Own address register 2, Address offset: 0x0C */
+ __IO uint32_t DR; /*!< I2C Data register, Address offset: 0x10 */
+ __IO uint32_t SR1; /*!< I2C Status register 1, Address offset: 0x14 */
+ __IO uint32_t SR2; /*!< I2C Status register 2, Address offset: 0x18 */
+ __IO uint32_t CCR; /*!< I2C Clock control register, Address offset: 0x1C */
+ __IO uint32_t TRISE; /*!< I2C TRISE register, Address offset: 0x20 */
+ __IO uint32_t FLTR; /*!< I2C FLTR register, Address offset: 0x24 */
+} I2C_TypeDef;
+
+/**
+ * @brief Independent WATCHDOG
+ */
+
+typedef struct
+{
+ __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */
+ __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */
+ __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */
+ __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */
+} IWDG_TypeDef;
+
+/**
+ * @brief Power Control
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */
+ __IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */
+} PWR_TypeDef;
+
+/**
+ * @brief Reset and Clock Control
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */
+ __IO uint32_t PLLCFGR; /*!< RCC PLL configuration register, Address offset: 0x04 */
+ __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x08 */
+ __IO uint32_t CIR; /*!< RCC clock interrupt register, Address offset: 0x0C */
+ __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x10 */
+ __IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x14 */
+ __IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0x18 */
+ uint32_t RESERVED0; /*!< Reserved, 0x1C */
+ __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x20 */
+ __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x24 */
+ uint32_t RESERVED1[2]; /*!< Reserved, 0x28-0x2C */
+ __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clock register, Address offset: 0x30 */
+ __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clock register, Address offset: 0x34 */
+ __IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clock register, Address offset: 0x38 */
+ uint32_t RESERVED2; /*!< Reserved, 0x3C */
+ __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x40 */
+ __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x44 */
+ uint32_t RESERVED3[2]; /*!< Reserved, 0x48-0x4C */
+ __IO uint32_t AHB1LPENR; /*!< RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 */
+ __IO uint32_t AHB2LPENR; /*!< RCC AHB2 peripheral clock enable in low power mode register, Address offset: 0x54 */
+ __IO uint32_t AHB3LPENR; /*!< RCC AHB3 peripheral clock enable in low power mode register, Address offset: 0x58 */
+ uint32_t RESERVED4; /*!< Reserved, 0x5C */
+ __IO uint32_t APB1LPENR; /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 */
+ __IO uint32_t APB2LPENR; /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 */
+ uint32_t RESERVED5[2]; /*!< Reserved, 0x68-0x6C */
+ __IO uint32_t BDCR; /*!< RCC Backup domain control register, Address offset: 0x70 */
+ __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x74 */
+ uint32_t RESERVED6[2]; /*!< Reserved, 0x78-0x7C */
+ __IO uint32_t SSCGR; /*!< RCC spread spectrum clock generation register, Address offset: 0x80 */
+ __IO uint32_t PLLI2SCFGR; /*!< RCC PLLI2S configuration register, Address offset: 0x84 */
+ __IO uint32_t PLLSAICFGR; /*!< RCC PLLSAI configuration register, Address offset: 0x88 */
+ __IO uint32_t DCKCFGR; /*!< RCC Dedicated Clocks configuration register, Address offset: 0x8C */
+
+} RCC_TypeDef;
+
+/**
+ * @brief Real-Time Clock
+ */
+
+typedef struct
+{
+ __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
+ __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */
+ __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */
+ __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */
+ __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */
+ __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */
+ __IO uint32_t CALIBR; /*!< RTC calibration register, Address offset: 0x18 */
+ __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */
+ __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */
+ __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */
+ __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */
+ __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */
+ __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */
+ __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */
+ __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */
+ __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */
+ __IO uint32_t TAFCR; /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */
+ __IO uint32_t ALRMASSR;/*!< RTC alarm A sub second register, Address offset: 0x44 */
+ __IO uint32_t ALRMBSSR;/*!< RTC alarm B sub second register, Address offset: 0x48 */
+ uint32_t RESERVED7; /*!< Reserved, 0x4C */
+ __IO uint32_t BKP0R; /*!< RTC backup register 1, Address offset: 0x50 */
+ __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */
+ __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */
+ __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */
+ __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */
+ __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */
+ __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */
+ __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */
+ __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */
+ __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */
+ __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */
+ __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */
+ __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */
+ __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */
+ __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */
+ __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */
+ __IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */
+ __IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */
+ __IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */
+ __IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */
+} RTC_TypeDef;
+
+/**
+ * @brief Serial Audio Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t GCR; /*!< SAI global configuration register, Address offset: 0x00 */
+} SAI_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t CR1; /*!< SAI block x configuration register 1, Address offset: 0x04 */
+ __IO uint32_t CR2; /*!< SAI block x configuration register 2, Address offset: 0x08 */
+ __IO uint32_t FRCR; /*!< SAI block x frame configuration register, Address offset: 0x0C */
+ __IO uint32_t SLOTR; /*!< SAI block x slot register, Address offset: 0x10 */
+ __IO uint32_t IMR; /*!< SAI block x interrupt mask register, Address offset: 0x14 */
+ __IO uint32_t SR; /*!< SAI block x status register, Address offset: 0x18 */
+ __IO uint32_t CLRFR; /*!< SAI block x clear flag register, Address offset: 0x1C */
+ __IO uint32_t DR; /*!< SAI block x data register, Address offset: 0x20 */
+} SAI_Block_TypeDef;
+
+/**
+ * @brief SD host Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t POWER; /*!< SDIO power control register, Address offset: 0x00 */
+ __IO uint32_t CLKCR; /*!< SDI clock control register, Address offset: 0x04 */
+ __IO uint32_t ARG; /*!< SDIO argument register, Address offset: 0x08 */
+ __IO uint32_t CMD; /*!< SDIO command register, Address offset: 0x0C */
+ __I uint32_t RESPCMD; /*!< SDIO command response register, Address offset: 0x10 */
+ __I uint32_t RESP1; /*!< SDIO response 1 register, Address offset: 0x14 */
+ __I uint32_t RESP2; /*!< SDIO response 2 register, Address offset: 0x18 */
+ __I uint32_t RESP3; /*!< SDIO response 3 register, Address offset: 0x1C */
+ __I uint32_t RESP4; /*!< SDIO response 4 register, Address offset: 0x20 */
+ __IO uint32_t DTIMER; /*!< SDIO data timer register, Address offset: 0x24 */
+ __IO uint32_t DLEN; /*!< SDIO data length register, Address offset: 0x28 */
+ __IO uint32_t DCTRL; /*!< SDIO data control register, Address offset: 0x2C */
+ __I uint32_t DCOUNT; /*!< SDIO data counter register, Address offset: 0x30 */
+ __I uint32_t STA; /*!< SDIO status register, Address offset: 0x34 */
+ __IO uint32_t ICR; /*!< SDIO interrupt clear register, Address offset: 0x38 */
+ __IO uint32_t MASK; /*!< SDIO mask register, Address offset: 0x3C */
+ uint32_t RESERVED0[2]; /*!< Reserved, 0x40-0x44 */
+ __I uint32_t FIFOCNT; /*!< SDIO FIFO counter register, Address offset: 0x48 */
+ uint32_t RESERVED1[13]; /*!< Reserved, 0x4C-0x7C */
+ __IO uint32_t FIFO; /*!< SDIO data FIFO register, Address offset: 0x80 */
+} SDIO_TypeDef;
+
+/**
+ * @brief Serial Peripheral Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t CR1; /*!< SPI control register 1 (not used in I2S mode), Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< SPI control register 2, Address offset: 0x04 */
+ __IO uint32_t SR; /*!< SPI status register, Address offset: 0x08 */
+ __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */
+ __IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
+ __IO uint32_t RXCRCR; /*!< SPI RX CRC register (not used in I2S mode), Address offset: 0x14 */
+ __IO uint32_t TXCRCR; /*!< SPI TX CRC register (not used in I2S mode), Address offset: 0x18 */
+ __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */
+ __IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */
+} SPI_TypeDef;
+
+/**
+ * @brief TIM
+ */
+
+typedef struct
+{
+ __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
+ __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */
+ __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
+ __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
+ __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
+ __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
+ __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
+ __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
+ __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
+ __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */
+ __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
+ __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */
+ __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
+ __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
+ __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
+ __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
+ __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
+ __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
+ __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */
+ __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */
+} TIM_TypeDef;
+
+/**
+ * @brief Universal Synchronous Asynchronous Receiver Transmitter
+ */
+
+typedef struct
+{
+ __IO uint32_t SR; /*!< USART Status register, Address offset: 0x00 */
+ __IO uint32_t DR; /*!< USART Data register, Address offset: 0x04 */
+ __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x08 */
+ __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x0C */
+ __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x10 */
+ __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x14 */
+ __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x18 */
+} USART_TypeDef;
+
+/**
+ * @brief Window WATCHDOG
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
+ __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
+ __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
+} WWDG_TypeDef;
+
+
+/**
+ * @brief RNG
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */
+ __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */
+ __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */
+} RNG_TypeDef;
+
+
+/**
+ * @brief __USB_OTG_Core_register
+ */
+typedef struct
+{
+ __IO uint32_t GOTGCTL; /*!< USB_OTG Control and Status Register 000h */
+ __IO uint32_t GOTGINT; /*!< USB_OTG Interrupt Register 004h */
+ __IO uint32_t GAHBCFG; /*!< Core AHB Configuration Register 008h */
+ __IO uint32_t GUSBCFG; /*!< Core USB Configuration Register 00Ch */
+ __IO uint32_t GRSTCTL; /*!< Core Reset Register 010h */
+ __IO uint32_t GINTSTS; /*!< Core Interrupt Register 014h */
+ __IO uint32_t GINTMSK; /*!< Core Interrupt Mask Register 018h */
+ __IO uint32_t GRXSTSR; /*!< Receive Sts Q Read Register 01Ch */
+ __IO uint32_t GRXSTSP; /*!< Receive Sts Q Read & POP Register 020h */
+ __IO uint32_t GRXFSIZ; /* Receive FIFO Size Register 024h */
+ __IO uint32_t DIEPTXF0_HNPTXFSIZ; /*!< EP0 / Non Periodic Tx FIFO Size Register 028h*/
+ __IO uint32_t HNPTXSTS; /*!< Non Periodic Tx FIFO/Queue Sts reg 02Ch */
+ uint32_t Reserved30[2]; /* Reserved 030h*/
+ __IO uint32_t GCCFG; /* General Purpose IO Register 038h*/
+ __IO uint32_t CID; /* User ID Register 03Ch*/
+ uint32_t Reserved40[48]; /* Reserved 040h-0FFh*/
+ __IO uint32_t HPTXFSIZ; /* Host Periodic Tx FIFO Size Reg 100h*/
+ __IO uint32_t DIEPTXF[0x0F];/* dev Periodic Transmit FIFO */
+}
+USB_OTG_GlobalTypeDef;
+
+
+/**
+ * @brief __device_Registers
+ */
+typedef struct
+{
+ __IO uint32_t DCFG; /* dev Configuration Register 800h*/
+ __IO uint32_t DCTL; /* dev Control Register 804h*/
+ __IO uint32_t DSTS; /* dev Status Register (RO) 808h*/
+ uint32_t Reserved0C; /* Reserved 80Ch*/
+ __IO uint32_t DIEPMSK; /* dev IN Endpoint Mask 810h*/
+ __IO uint32_t DOEPMSK; /* dev OUT Endpoint Mask 814h*/
+ __IO uint32_t DAINT; /* dev All Endpoints Itr Reg 818h*/
+ __IO uint32_t DAINTMSK; /* dev All Endpoints Itr Mask 81Ch*/
+ uint32_t Reserved20; /* Reserved 820h*/
+ uint32_t Reserved9; /* Reserved 824h*/
+ __IO uint32_t DVBUSDIS; /* dev VBUS discharge Register 828h*/
+ __IO uint32_t DVBUSPULSE; /* dev VBUS Pulse Register 82Ch*/
+ __IO uint32_t DTHRCTL; /* dev thr 830h*/
+ __IO uint32_t DIEPEMPMSK; /* dev empty msk 834h*/
+ __IO uint32_t DEACHINT; /* dedicated EP interrupt 838h*/
+ __IO uint32_t DEACHMSK; /* dedicated EP msk 83Ch*/
+ uint32_t Reserved40; /* dedicated EP mask 840h*/
+ __IO uint32_t DINEP1MSK; /* dedicated EP mask 844h*/
+ uint32_t Reserved44[15]; /* Reserved 844-87Ch*/
+ __IO uint32_t DOUTEP1MSK; /* dedicated EP msk 884h*/
+}
+USB_OTG_DeviceTypeDef;
+
+
+/**
+ * @brief __IN_Endpoint-Specific_Register
+ */
+typedef struct
+{
+ __IO uint32_t DIEPCTL; /* dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h*/
+ uint32_t Reserved04; /* Reserved 900h + (ep_num * 20h) + 04h*/
+ __IO uint32_t DIEPINT; /* dev IN Endpoint Itr Reg 900h + (ep_num * 20h) + 08h*/
+ uint32_t Reserved0C; /* Reserved 900h + (ep_num * 20h) + 0Ch*/
+ __IO uint32_t DIEPTSIZ; /* IN Endpoint Txfer Size 900h + (ep_num * 20h) + 10h*/
+ __IO uint32_t DIEPDMA; /* IN Endpoint DMA Address Reg 900h + (ep_num * 20h) + 14h*/
+ __IO uint32_t DTXFSTS;/*IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h*/
+ uint32_t Reserved18; /* Reserved 900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch*/
+}
+USB_OTG_INEndpointTypeDef;
+
+
+/**
+ * @brief __OUT_Endpoint-Specific_Registers
+ */
+typedef struct
+{
+ __IO uint32_t DOEPCTL; /* dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h*/
+ uint32_t Reserved04; /* Reserved B00h + (ep_num * 20h) + 04h*/
+ __IO uint32_t DOEPINT; /* dev OUT Endpoint Itr Reg B00h + (ep_num * 20h) + 08h*/
+ uint32_t Reserved0C; /* Reserved B00h + (ep_num * 20h) + 0Ch*/
+ __IO uint32_t DOEPTSIZ; /* dev OUT Endpoint Txfer Size B00h + (ep_num * 20h) + 10h*/
+ __IO uint32_t DOEPDMA; /* dev OUT Endpoint DMA Address B00h + (ep_num * 20h) + 14h*/
+ uint32_t Reserved18[2]; /* Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch*/
+}
+USB_OTG_OUTEndpointTypeDef;
+
+
+/**
+ * @brief __Host_Mode_Register_Structures
+ */
+typedef struct
+{
+ __IO uint32_t HCFG; /* Host Configuration Register 400h*/
+ __IO uint32_t HFIR; /* Host Frame Interval Register 404h*/
+ __IO uint32_t HFNUM; /* Host Frame Nbr/Frame Remaining 408h*/
+ uint32_t Reserved40C; /* Reserved 40Ch*/
+ __IO uint32_t HPTXSTS; /* Host Periodic Tx FIFO/ Queue Status 410h*/
+ __IO uint32_t HAINT; /* Host All Channels Interrupt Register 414h*/
+ __IO uint32_t HAINTMSK; /* Host All Channels Interrupt Mask 418h*/
+}
+USB_OTG_HostTypeDef;
+
+/**
+ * @brief __Host_Channel_Specific_Registers
+ */
+typedef struct
+{
+ __IO uint32_t HCCHAR;
+ __IO uint32_t HCSPLT;
+ __IO uint32_t HCINT;
+ __IO uint32_t HCINTMSK;
+ __IO uint32_t HCTSIZ;
+ __IO uint32_t HCDMA;
+ uint32_t Reserved[2];
+}
+USB_OTG_HostChannelTypeDef;
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_memory_map
+ * @{
+ */
+#define FLASH_BASE 0x08000000U /*!< FLASH(up to 2 MB) base address in the alias region */
+#define CCMDATARAM_BASE 0x10000000U /*!< CCM(core coupled memory) data RAM(64 KB) base address in the alias region */
+#define SRAM1_BASE 0x20000000U /*!< SRAM1(112 KB) base address in the alias region */
+#define SRAM2_BASE 0x2001C000U /*!< SRAM2(16 KB) base address in the alias region */
+#define PERIPH_BASE 0x40000000U /*!< Peripheral base address in the alias region */
+#define BKPSRAM_BASE 0x40024000U /*!< Backup SRAM(4 KB) base address in the alias region */
+#define FMC_R_BASE 0xA0000000U /*!< FMC registers base address */
+#define SRAM1_BB_BASE 0x22000000U /*!< SRAM1(112 KB) base address in the bit-band region */
+#define SRAM2_BB_BASE 0x22380000U /*!< SRAM2(16 KB) base address in the bit-band region */
+#define PERIPH_BB_BASE 0x42000000U /*!< Peripheral base address in the bit-band region */
+#define BKPSRAM_BB_BASE 0x42480000U /*!< Backup SRAM(4 KB) base address in the bit-band region */
+#define FLASH_END 0x081FFFFFU /*!< FLASH end address */
+#define CCMDATARAM_END 0x1000FFFFU /*!< CCM data RAM end address */
+
+/* Legacy defines */
+#define SRAM_BASE SRAM1_BASE
+#define SRAM_BB_BASE SRAM1_BB_BASE
+
+
+/*!< Peripheral memory map */
+#define APB1PERIPH_BASE PERIPH_BASE
+#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000U)
+#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000U)
+#define AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000U)
+
+/*!< APB1 peripherals */
+#define TIM2_BASE (APB1PERIPH_BASE + 0x0000U)
+#define TIM3_BASE (APB1PERIPH_BASE + 0x0400U)
+#define TIM4_BASE (APB1PERIPH_BASE + 0x0800U)
+#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00U)
+#define TIM6_BASE (APB1PERIPH_BASE + 0x1000U)
+#define TIM7_BASE (APB1PERIPH_BASE + 0x1400U)
+#define TIM12_BASE (APB1PERIPH_BASE + 0x1800U)
+#define TIM13_BASE (APB1PERIPH_BASE + 0x1C00U)
+#define TIM14_BASE (APB1PERIPH_BASE + 0x2000U)
+#define RTC_BASE (APB1PERIPH_BASE + 0x2800U)
+#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00U)
+#define IWDG_BASE (APB1PERIPH_BASE + 0x3000U)
+#define I2S2ext_BASE (APB1PERIPH_BASE + 0x3400U)
+#define SPI2_BASE (APB1PERIPH_BASE + 0x3800U)
+#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00U)
+#define I2S3ext_BASE (APB1PERIPH_BASE + 0x4000U)
+#define USART2_BASE (APB1PERIPH_BASE + 0x4400U)
+#define USART3_BASE (APB1PERIPH_BASE + 0x4800U)
+#define UART4_BASE (APB1PERIPH_BASE + 0x4C00U)
+#define UART5_BASE (APB1PERIPH_BASE + 0x5000U)
+#define I2C1_BASE (APB1PERIPH_BASE + 0x5400U)
+#define I2C2_BASE (APB1PERIPH_BASE + 0x5800U)
+#define I2C3_BASE (APB1PERIPH_BASE + 0x5C00U)
+#define CAN1_BASE (APB1PERIPH_BASE + 0x6400U)
+#define CAN2_BASE (APB1PERIPH_BASE + 0x6800U)
+#define PWR_BASE (APB1PERIPH_BASE + 0x7000U)
+#define DAC_BASE (APB1PERIPH_BASE + 0x7400U)
+#define UART7_BASE (APB1PERIPH_BASE + 0x7800U)
+#define UART8_BASE (APB1PERIPH_BASE + 0x7C00U)
+
+/*!< APB2 peripherals */
+#define TIM1_BASE (APB2PERIPH_BASE + 0x0000U)
+#define TIM8_BASE (APB2PERIPH_BASE + 0x0400U)
+#define USART1_BASE (APB2PERIPH_BASE + 0x1000U)
+#define USART6_BASE (APB2PERIPH_BASE + 0x1400U)
+#define ADC1_BASE (APB2PERIPH_BASE + 0x2000U)
+#define ADC2_BASE (APB2PERIPH_BASE + 0x2100U)
+#define ADC3_BASE (APB2PERIPH_BASE + 0x2200U)
+#define ADC_BASE (APB2PERIPH_BASE + 0x2300U)
+#define SDIO_BASE (APB2PERIPH_BASE + 0x2C00U)
+#define SPI1_BASE (APB2PERIPH_BASE + 0x3000U)
+#define SPI4_BASE (APB2PERIPH_BASE + 0x3400U)
+#define SYSCFG_BASE (APB2PERIPH_BASE + 0x3800U)
+#define EXTI_BASE (APB2PERIPH_BASE + 0x3C00U)
+#define TIM9_BASE (APB2PERIPH_BASE + 0x4000U)
+#define TIM10_BASE (APB2PERIPH_BASE + 0x4400U)
+#define TIM11_BASE (APB2PERIPH_BASE + 0x4800U)
+#define SPI5_BASE (APB2PERIPH_BASE + 0x5000U)
+#define SPI6_BASE (APB2PERIPH_BASE + 0x5400U)
+#define SAI1_BASE (APB2PERIPH_BASE + 0x5800U)
+#define SAI1_Block_A_BASE (SAI1_BASE + 0x004U)
+#define SAI1_Block_B_BASE (SAI1_BASE + 0x024U)
+
+/*!< AHB1 peripherals */
+#define GPIOA_BASE (AHB1PERIPH_BASE + 0x0000U)
+#define GPIOB_BASE (AHB1PERIPH_BASE + 0x0400U)
+#define GPIOC_BASE (AHB1PERIPH_BASE + 0x0800U)
+#define GPIOD_BASE (AHB1PERIPH_BASE + 0x0C00U)
+#define GPIOE_BASE (AHB1PERIPH_BASE + 0x1000U)
+#define GPIOF_BASE (AHB1PERIPH_BASE + 0x1400U)
+#define GPIOG_BASE (AHB1PERIPH_BASE + 0x1800U)
+#define GPIOH_BASE (AHB1PERIPH_BASE + 0x1C00U)
+#define GPIOI_BASE (AHB1PERIPH_BASE + 0x2000U)
+#define GPIOJ_BASE (AHB1PERIPH_BASE + 0x2400U)
+#define GPIOK_BASE (AHB1PERIPH_BASE + 0x2800U)
+#define CRC_BASE (AHB1PERIPH_BASE + 0x3000U)
+#define RCC_BASE (AHB1PERIPH_BASE + 0x3800U)
+#define FLASH_R_BASE (AHB1PERIPH_BASE + 0x3C00U)
+#define DMA1_BASE (AHB1PERIPH_BASE + 0x6000U)
+#define DMA1_Stream0_BASE (DMA1_BASE + 0x010U)
+#define DMA1_Stream1_BASE (DMA1_BASE + 0x028U)
+#define DMA1_Stream2_BASE (DMA1_BASE + 0x040U)
+#define DMA1_Stream3_BASE (DMA1_BASE + 0x058U)
+#define DMA1_Stream4_BASE (DMA1_BASE + 0x070U)
+#define DMA1_Stream5_BASE (DMA1_BASE + 0x088U)
+#define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0U)
+#define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8U)
+#define DMA2_BASE (AHB1PERIPH_BASE + 0x6400U)
+#define DMA2_Stream0_BASE (DMA2_BASE + 0x010U)
+#define DMA2_Stream1_BASE (DMA2_BASE + 0x028U)
+#define DMA2_Stream2_BASE (DMA2_BASE + 0x040U)
+#define DMA2_Stream3_BASE (DMA2_BASE + 0x058U)
+#define DMA2_Stream4_BASE (DMA2_BASE + 0x070U)
+#define DMA2_Stream5_BASE (DMA2_BASE + 0x088U)
+#define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0U)
+#define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8U)
+#define ETH_BASE (AHB1PERIPH_BASE + 0x8000U)
+#define ETH_MAC_BASE (ETH_BASE)
+#define ETH_MMC_BASE (ETH_BASE + 0x0100U)
+#define ETH_PTP_BASE (ETH_BASE + 0x0700U)
+#define ETH_DMA_BASE (ETH_BASE + 0x1000U)
+#define DMA2D_BASE (AHB1PERIPH_BASE + 0xB000U)
+
+/*!< AHB2 peripherals */
+#define DCMI_BASE (AHB2PERIPH_BASE + 0x50000U)
+#define RNG_BASE (AHB2PERIPH_BASE + 0x60800U)
+
+/*!< FMC Bankx registers base address */
+#define FMC_Bank1_R_BASE (FMC_R_BASE + 0x0000U)
+#define FMC_Bank1E_R_BASE (FMC_R_BASE + 0x0104U)
+#define FMC_Bank2_3_R_BASE (FMC_R_BASE + 0x0060U)
+#define FMC_Bank4_R_BASE (FMC_R_BASE + 0x00A0U)
+#define FMC_Bank5_6_R_BASE (FMC_R_BASE + 0x0140U)
+
+/* Debug MCU registers base address */
+#define DBGMCU_BASE 0xE0042000U
+
+/*!< USB registers base address */
+#define USB_OTG_HS_PERIPH_BASE 0x40040000U
+#define USB_OTG_FS_PERIPH_BASE 0x50000000U
+
+#define USB_OTG_GLOBAL_BASE 0x000U
+#define USB_OTG_DEVICE_BASE 0x800U
+#define USB_OTG_IN_ENDPOINT_BASE 0x900U
+#define USB_OTG_OUT_ENDPOINT_BASE 0xB00U
+#define USB_OTG_EP_REG_SIZE 0x20U
+#define USB_OTG_HOST_BASE 0x400U
+#define USB_OTG_HOST_PORT_BASE 0x440U
+#define USB_OTG_HOST_CHANNEL_BASE 0x500U
+#define USB_OTG_HOST_CHANNEL_SIZE 0x20U
+#define USB_OTG_PCGCCTL_BASE 0xE00U
+#define USB_OTG_FIFO_BASE 0x1000U
+#define USB_OTG_FIFO_SIZE 0x1000U
+
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_declaration
+ * @{
+ */
+#define TIM2 ((TIM_TypeDef *) TIM2_BASE)
+#define TIM3 ((TIM_TypeDef *) TIM3_BASE)
+#define TIM4 ((TIM_TypeDef *) TIM4_BASE)
+#define TIM5 ((TIM_TypeDef *) TIM5_BASE)
+#define TIM6 ((TIM_TypeDef *) TIM6_BASE)
+#define TIM7 ((TIM_TypeDef *) TIM7_BASE)
+#define TIM12 ((TIM_TypeDef *) TIM12_BASE)
+#define TIM13 ((TIM_TypeDef *) TIM13_BASE)
+#define TIM14 ((TIM_TypeDef *) TIM14_BASE)
+#define RTC ((RTC_TypeDef *) RTC_BASE)
+#define WWDG ((WWDG_TypeDef *) WWDG_BASE)
+#define IWDG ((IWDG_TypeDef *) IWDG_BASE)
+#define I2S2ext ((SPI_TypeDef *) I2S2ext_BASE)
+#define SPI2 ((SPI_TypeDef *) SPI2_BASE)
+#define SPI3 ((SPI_TypeDef *) SPI3_BASE)
+#define I2S3ext ((SPI_TypeDef *) I2S3ext_BASE)
+#define USART2 ((USART_TypeDef *) USART2_BASE)
+#define USART3 ((USART_TypeDef *) USART3_BASE)
+#define UART4 ((USART_TypeDef *) UART4_BASE)
+#define UART5 ((USART_TypeDef *) UART5_BASE)
+#define I2C1 ((I2C_TypeDef *) I2C1_BASE)
+#define I2C2 ((I2C_TypeDef *) I2C2_BASE)
+#define I2C3 ((I2C_TypeDef *) I2C3_BASE)
+#define CAN1 ((CAN_TypeDef *) CAN1_BASE)
+#define CAN2 ((CAN_TypeDef *) CAN2_BASE)
+#define PWR ((PWR_TypeDef *) PWR_BASE)
+#define DAC ((DAC_TypeDef *) DAC_BASE)
+#define UART7 ((USART_TypeDef *) UART7_BASE)
+#define UART8 ((USART_TypeDef *) UART8_BASE)
+#define TIM1 ((TIM_TypeDef *) TIM1_BASE)
+#define TIM8 ((TIM_TypeDef *) TIM8_BASE)
+#define USART1 ((USART_TypeDef *) USART1_BASE)
+#define USART6 ((USART_TypeDef *) USART6_BASE)
+#define ADC ((ADC_Common_TypeDef *) ADC_BASE)
+#define ADC1 ((ADC_TypeDef *) ADC1_BASE)
+#define ADC2 ((ADC_TypeDef *) ADC2_BASE)
+#define ADC3 ((ADC_TypeDef *) ADC3_BASE)
+#define SDIO ((SDIO_TypeDef *) SDIO_BASE)
+#define SPI1 ((SPI_TypeDef *) SPI1_BASE)
+#define SPI4 ((SPI_TypeDef *) SPI4_BASE)
+#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
+#define EXTI ((EXTI_TypeDef *) EXTI_BASE)
+#define TIM9 ((TIM_TypeDef *) TIM9_BASE)
+#define TIM10 ((TIM_TypeDef *) TIM10_BASE)
+#define TIM11 ((TIM_TypeDef *) TIM11_BASE)
+#define SPI5 ((SPI_TypeDef *) SPI5_BASE)
+#define SPI6 ((SPI_TypeDef *) SPI6_BASE)
+#define SAI1 ((SAI_TypeDef *) SAI1_BASE)
+#define SAI1_Block_A ((SAI_Block_TypeDef *)SAI1_Block_A_BASE)
+#define SAI1_Block_B ((SAI_Block_TypeDef *)SAI1_Block_B_BASE)
+
+#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
+#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
+#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
+#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
+#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
+#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
+#define GPIOG ((GPIO_TypeDef *) GPIOG_BASE)
+#define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
+#define GPIOI ((GPIO_TypeDef *) GPIOI_BASE)
+#define GPIOJ ((GPIO_TypeDef *) GPIOJ_BASE)
+#define GPIOK ((GPIO_TypeDef *) GPIOK_BASE)
+#define CRC ((CRC_TypeDef *) CRC_BASE)
+#define RCC ((RCC_TypeDef *) RCC_BASE)
+#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
+#define DMA1 ((DMA_TypeDef *) DMA1_BASE)
+#define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)
+#define DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)
+#define DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)
+#define DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)
+#define DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)
+#define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)
+#define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)
+#define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)
+#define DMA2 ((DMA_TypeDef *) DMA2_BASE)
+#define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)
+#define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
+#define DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)
+#define DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)
+#define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)
+#define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)
+#define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)
+#define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)
+#define ETH ((ETH_TypeDef *) ETH_BASE)
+#define DMA2D ((DMA2D_TypeDef *)DMA2D_BASE)
+#define DCMI ((DCMI_TypeDef *) DCMI_BASE)
+#define RNG ((RNG_TypeDef *) RNG_BASE)
+#define FMC_Bank1 ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE)
+#define FMC_Bank1E ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE)
+#define FMC_Bank2_3 ((FMC_Bank2_3_TypeDef *) FMC_Bank2_3_R_BASE)
+#define FMC_Bank4 ((FMC_Bank4_TypeDef *) FMC_Bank4_R_BASE)
+#define FMC_Bank5_6 ((FMC_Bank5_6_TypeDef *) FMC_Bank5_6_R_BASE)
+
+#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
+
+#define USB_OTG_FS ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE)
+#define USB_OTG_HS ((USB_OTG_GlobalTypeDef *) USB_OTG_HS_PERIPH_BASE)
+
+/**
+ * @}
+ */
+
+/** @addtogroup Exported_constants
+ * @{
+ */
+
+ /** @addtogroup Peripheral_Registers_Bits_Definition
+ * @{
+ */
+
+/******************************************************************************/
+/* Peripheral Registers_Bits_Definition */
+/******************************************************************************/
+
+/******************************************************************************/
+/* */
+/* Analog to Digital Converter */
+/* */
+/******************************************************************************/
+/******************** Bit definition for ADC_SR register ********************/
+#define ADC_SR_AWD 0x00000001U /*!<Analog watchdog flag */
+#define ADC_SR_EOC 0x00000002U /*!<End of conversion */
+#define ADC_SR_JEOC 0x00000004U /*!<Injected channel end of conversion */
+#define ADC_SR_JSTRT 0x00000008U /*!<Injected channel Start flag */
+#define ADC_SR_STRT 0x00000010U /*!<Regular channel Start flag */
+#define ADC_SR_OVR 0x00000020U /*!<Overrun flag */
+
+/******************* Bit definition for ADC_CR1 register ********************/
+#define ADC_CR1_AWDCH 0x0000001FU /*!<AWDCH[4:0] bits (Analog watchdog channel select bits) */
+#define ADC_CR1_AWDCH_0 0x00000001U /*!<Bit 0 */
+#define ADC_CR1_AWDCH_1 0x00000002U /*!<Bit 1 */
+#define ADC_CR1_AWDCH_2 0x00000004U /*!<Bit 2 */
+#define ADC_CR1_AWDCH_3 0x00000008U /*!<Bit 3 */
+#define ADC_CR1_AWDCH_4 0x00000010U /*!<Bit 4 */
+#define ADC_CR1_EOCIE 0x00000020U /*!<Interrupt enable for EOC */
+#define ADC_CR1_AWDIE 0x00000040U /*!<AAnalog Watchdog interrupt enable */
+#define ADC_CR1_JEOCIE 0x00000080U /*!<Interrupt enable for injected channels */
+#define ADC_CR1_SCAN 0x00000100U /*!<Scan mode */
+#define ADC_CR1_AWDSGL 0x00000200U /*!<Enable the watchdog on a single channel in scan mode */
+#define ADC_CR1_JAUTO 0x00000400U /*!<Automatic injected group conversion */
+#define ADC_CR1_DISCEN 0x00000800U /*!<Discontinuous mode on regular channels */
+#define ADC_CR1_JDISCEN 0x00001000U /*!<Discontinuous mode on injected channels */
+#define ADC_CR1_DISCNUM 0x0000E000U /*!<DISCNUM[2:0] bits (Discontinuous mode channel count) */
+#define ADC_CR1_DISCNUM_0 0x00002000U /*!<Bit 0 */
+#define ADC_CR1_DISCNUM_1 0x00004000U /*!<Bit 1 */
+#define ADC_CR1_DISCNUM_2 0x00008000U /*!<Bit 2 */
+#define ADC_CR1_JAWDEN 0x00400000U /*!<Analog watchdog enable on injected channels */
+#define ADC_CR1_AWDEN 0x00800000U /*!<Analog watchdog enable on regular channels */
+#define ADC_CR1_RES 0x03000000U /*!<RES[2:0] bits (Resolution) */
+#define ADC_CR1_RES_0 0x01000000U /*!<Bit 0 */
+#define ADC_CR1_RES_1 0x02000000U /*!<Bit 1 */
+#define ADC_CR1_OVRIE 0x04000000U /*!<overrun interrupt enable */
+
+/******************* Bit definition for ADC_CR2 register ********************/
+#define ADC_CR2_ADON 0x00000001U /*!<A/D Converter ON / OFF */
+#define ADC_CR2_CONT 0x00000002U /*!<Continuous Conversion */
+#define ADC_CR2_DMA 0x00000100U /*!<Direct Memory access mode */
+#define ADC_CR2_DDS 0x00000200U /*!<DMA disable selection (Single ADC) */
+#define ADC_CR2_EOCS 0x00000400U /*!<End of conversion selection */
+#define ADC_CR2_ALIGN 0x00000800U /*!<Data Alignment */
+#define ADC_CR2_JEXTSEL 0x000F0000U /*!<JEXTSEL[3:0] bits (External event select for injected group) */
+#define ADC_CR2_JEXTSEL_0 0x00010000U /*!<Bit 0 */
+#define ADC_CR2_JEXTSEL_1 0x00020000U /*!<Bit 1 */
+#define ADC_CR2_JEXTSEL_2 0x00040000U /*!<Bit 2 */
+#define ADC_CR2_JEXTSEL_3 0x00080000U /*!<Bit 3 */
+#define ADC_CR2_JEXTEN 0x00300000U /*!<JEXTEN[1:0] bits (External Trigger Conversion mode for injected channelsp) */
+#define ADC_CR2_JEXTEN_0 0x00100000U /*!<Bit 0 */
+#define ADC_CR2_JEXTEN_1 0x00200000U /*!<Bit 1 */
+#define ADC_CR2_JSWSTART 0x00400000U /*!<Start Conversion of injected channels */
+#define ADC_CR2_EXTSEL 0x0F000000U /*!<EXTSEL[3:0] bits (External Event Select for regular group) */
+#define ADC_CR2_EXTSEL_0 0x01000000U /*!<Bit 0 */
+#define ADC_CR2_EXTSEL_1 0x02000000U /*!<Bit 1 */
+#define ADC_CR2_EXTSEL_2 0x04000000U /*!<Bit 2 */
+#define ADC_CR2_EXTSEL_3 0x08000000U /*!<Bit 3 */
+#define ADC_CR2_EXTEN 0x30000000U /*!<EXTEN[1:0] bits (External Trigger Conversion mode for regular channelsp) */
+#define ADC_CR2_EXTEN_0 0x10000000U /*!<Bit 0 */
+#define ADC_CR2_EXTEN_1 0x20000000U /*!<Bit 1 */
+#define ADC_CR2_SWSTART 0x40000000U /*!<Start Conversion of regular channels */
+
+/****************** Bit definition for ADC_SMPR1 register *******************/
+#define ADC_SMPR1_SMP10 0x00000007U /*!<SMP10[2:0] bits (Channel 10 Sample time selection) */
+#define ADC_SMPR1_SMP10_0 0x00000001U /*!<Bit 0 */
+#define ADC_SMPR1_SMP10_1 0x00000002U /*!<Bit 1 */
+#define ADC_SMPR1_SMP10_2 0x00000004U /*!<Bit 2 */
+#define ADC_SMPR1_SMP11 0x00000038U /*!<SMP11[2:0] bits (Channel 11 Sample time selection) */
+#define ADC_SMPR1_SMP11_0 0x00000008U /*!<Bit 0 */
+#define ADC_SMPR1_SMP11_1 0x00000010U /*!<Bit 1 */
+#define ADC_SMPR1_SMP11_2 0x00000020U /*!<Bit 2 */
+#define ADC_SMPR1_SMP12 0x000001C0U /*!<SMP12[2:0] bits (Channel 12 Sample time selection) */
+#define ADC_SMPR1_SMP12_0 0x00000040U /*!<Bit 0 */
+#define ADC_SMPR1_SMP12_1 0x00000080U /*!<Bit 1 */
+#define ADC_SMPR1_SMP12_2 0x00000100U /*!<Bit 2 */
+#define ADC_SMPR1_SMP13 0x00000E00U /*!<SMP13[2:0] bits (Channel 13 Sample time selection) */
+#define ADC_SMPR1_SMP13_0 0x00000200U /*!<Bit 0 */
+#define ADC_SMPR1_SMP13_1 0x00000400U /*!<Bit 1 */
+#define ADC_SMPR1_SMP13_2 0x00000800U /*!<Bit 2 */
+#define ADC_SMPR1_SMP14 0x00007000U /*!<SMP14[2:0] bits (Channel 14 Sample time selection) */
+#define ADC_SMPR1_SMP14_0 0x00001000U /*!<Bit 0 */
+#define ADC_SMPR1_SMP14_1 0x00002000U /*!<Bit 1 */
+#define ADC_SMPR1_SMP14_2 0x00004000U /*!<Bit 2 */
+#define ADC_SMPR1_SMP15 0x00038000U /*!<SMP15[2:0] bits (Channel 15 Sample time selection) */
+#define ADC_SMPR1_SMP15_0 0x00008000U /*!<Bit 0 */
+#define ADC_SMPR1_SMP15_1 0x00010000U /*!<Bit 1 */
+#define ADC_SMPR1_SMP15_2 0x00020000U /*!<Bit 2 */
+#define ADC_SMPR1_SMP16 0x001C0000U /*!<SMP16[2:0] bits (Channel 16 Sample time selection) */
+#define ADC_SMPR1_SMP16_0 0x00040000U /*!<Bit 0 */
+#define ADC_SMPR1_SMP16_1 0x00080000U /*!<Bit 1 */
+#define ADC_SMPR1_SMP16_2 0x00100000U /*!<Bit 2 */
+#define ADC_SMPR1_SMP17 0x00E00000U /*!<SMP17[2:0] bits (Channel 17 Sample time selection) */
+#define ADC_SMPR1_SMP17_0 0x00200000U /*!<Bit 0 */
+#define ADC_SMPR1_SMP17_1 0x00400000U /*!<Bit 1 */
+#define ADC_SMPR1_SMP17_2 0x00800000U /*!<Bit 2 */
+#define ADC_SMPR1_SMP18 0x07000000U /*!<SMP18[2:0] bits (Channel 18 Sample time selection) */
+#define ADC_SMPR1_SMP18_0 0x01000000U /*!<Bit 0 */
+#define ADC_SMPR1_SMP18_1 0x02000000U /*!<Bit 1 */
+#define ADC_SMPR1_SMP18_2 0x04000000U /*!<Bit 2 */
+
+/****************** Bit definition for ADC_SMPR2 register *******************/
+#define ADC_SMPR2_SMP0 0x00000007U /*!<SMP0[2:0] bits (Channel 0 Sample time selection) */
+#define ADC_SMPR2_SMP0_0 0x00000001U /*!<Bit 0 */
+#define ADC_SMPR2_SMP0_1 0x00000002U /*!<Bit 1 */
+#define ADC_SMPR2_SMP0_2 0x00000004U /*!<Bit 2 */
+#define ADC_SMPR2_SMP1 0x00000038U /*!<SMP1[2:0] bits (Channel 1 Sample time selection) */
+#define ADC_SMPR2_SMP1_0 0x00000008U /*!<Bit 0 */
+#define ADC_SMPR2_SMP1_1 0x00000010U /*!<Bit 1 */
+#define ADC_SMPR2_SMP1_2 0x00000020U /*!<Bit 2 */
+#define ADC_SMPR2_SMP2 0x000001C0U /*!<SMP2[2:0] bits (Channel 2 Sample time selection) */
+#define ADC_SMPR2_SMP2_0 0x00000040U /*!<Bit 0 */
+#define ADC_SMPR2_SMP2_1 0x00000080U /*!<Bit 1 */
+#define ADC_SMPR2_SMP2_2 0x00000100U /*!<Bit 2 */
+#define ADC_SMPR2_SMP3 0x00000E00U /*!<SMP3[2:0] bits (Channel 3 Sample time selection) */
+#define ADC_SMPR2_SMP3_0 0x00000200U /*!<Bit 0 */
+#define ADC_SMPR2_SMP3_1 0x00000400U /*!<Bit 1 */
+#define ADC_SMPR2_SMP3_2 0x00000800U /*!<Bit 2 */
+#define ADC_SMPR2_SMP4 0x00007000U /*!<SMP4[2:0] bits (Channel 4 Sample time selection) */
+#define ADC_SMPR2_SMP4_0 0x00001000U /*!<Bit 0 */
+#define ADC_SMPR2_SMP4_1 0x00002000U /*!<Bit 1 */
+#define ADC_SMPR2_SMP4_2 0x00004000U /*!<Bit 2 */
+#define ADC_SMPR2_SMP5 0x00038000U /*!<SMP5[2:0] bits (Channel 5 Sample time selection) */
+#define ADC_SMPR2_SMP5_0 0x00008000U /*!<Bit 0 */
+#define ADC_SMPR2_SMP5_1 0x00010000U /*!<Bit 1 */
+#define ADC_SMPR2_SMP5_2 0x00020000U /*!<Bit 2 */
+#define ADC_SMPR2_SMP6 0x001C0000U /*!<SMP6[2:0] bits (Channel 6 Sample time selection) */
+#define ADC_SMPR2_SMP6_0 0x00040000U /*!<Bit 0 */
+#define ADC_SMPR2_SMP6_1 0x00080000U /*!<Bit 1 */
+#define ADC_SMPR2_SMP6_2 0x00100000U /*!<Bit 2 */
+#define ADC_SMPR2_SMP7 0x00E00000U /*!<SMP7[2:0] bits (Channel 7 Sample time selection) */
+#define ADC_SMPR2_SMP7_0 0x00200000U /*!<Bit 0 */
+#define ADC_SMPR2_SMP7_1 0x00400000U /*!<Bit 1 */
+#define ADC_SMPR2_SMP7_2 0x00800000U /*!<Bit 2 */
+#define ADC_SMPR2_SMP8 0x07000000U /*!<SMP8[2:0] bits (Channel 8 Sample time selection) */
+#define ADC_SMPR2_SMP8_0 0x01000000U /*!<Bit 0 */
+#define ADC_SMPR2_SMP8_1 0x02000000U /*!<Bit 1 */
+#define ADC_SMPR2_SMP8_2 0x04000000U /*!<Bit 2 */
+#define ADC_SMPR2_SMP9 0x38000000U /*!<SMP9[2:0] bits (Channel 9 Sample time selection) */
+#define ADC_SMPR2_SMP9_0 0x08000000U /*!<Bit 0 */
+#define ADC_SMPR2_SMP9_1 0x10000000U /*!<Bit 1 */
+#define ADC_SMPR2_SMP9_2 0x20000000U /*!<Bit 2 */
+
+/****************** Bit definition for ADC_JOFR1 register *******************/
+#define ADC_JOFR1_JOFFSET1 0x0FFFU /*!<Data offset for injected channel 1 */
+
+/****************** Bit definition for ADC_JOFR2 register *******************/
+#define ADC_JOFR2_JOFFSET2 0x0FFFU /*!<Data offset for injected channel 2 */
+
+/****************** Bit definition for ADC_JOFR3 register *******************/
+#define ADC_JOFR3_JOFFSET3 0x0FFFU /*!<Data offset for injected channel 3 */
+
+/****************** Bit definition for ADC_JOFR4 register *******************/
+#define ADC_JOFR4_JOFFSET4 0x0FFFU /*!<Data offset for injected channel 4 */
+
+/******************* Bit definition for ADC_HTR register ********************/
+#define ADC_HTR_HT 0x0FFFU /*!<Analog watchdog high threshold */
+
+/******************* Bit definition for ADC_LTR register ********************/
+#define ADC_LTR_LT 0x0FFFU /*!<Analog watchdog low threshold */
+
+/******************* Bit definition for ADC_SQR1 register *******************/
+#define ADC_SQR1_SQ13 0x0000001FU /*!<SQ13[4:0] bits (13th conversion in regular sequence) */
+#define ADC_SQR1_SQ13_0 0x00000001U /*!<Bit 0 */
+#define ADC_SQR1_SQ13_1 0x00000002U /*!<Bit 1 */
+#define ADC_SQR1_SQ13_2 0x00000004U /*!<Bit 2 */
+#define ADC_SQR1_SQ13_3 0x00000008U /*!<Bit 3 */
+#define ADC_SQR1_SQ13_4 0x00000010U /*!<Bit 4 */
+#define ADC_SQR1_SQ14 0x000003E0U /*!<SQ14[4:0] bits (14th conversion in regular sequence) */
+#define ADC_SQR1_SQ14_0 0x00000020U /*!<Bit 0 */
+#define ADC_SQR1_SQ14_1 0x00000040U /*!<Bit 1 */
+#define ADC_SQR1_SQ14_2 0x00000080U /*!<Bit 2 */
+#define ADC_SQR1_SQ14_3 0x00000100U /*!<Bit 3 */
+#define ADC_SQR1_SQ14_4 0x00000200U /*!<Bit 4 */
+#define ADC_SQR1_SQ15 0x00007C00U /*!<SQ15[4:0] bits (15th conversion in regular sequence) */
+#define ADC_SQR1_SQ15_0 0x00000400U /*!<Bit 0 */
+#define ADC_SQR1_SQ15_1 0x00000800U /*!<Bit 1 */
+#define ADC_SQR1_SQ15_2 0x00001000U /*!<Bit 2 */
+#define ADC_SQR1_SQ15_3 0x00002000U /*!<Bit 3 */
+#define ADC_SQR1_SQ15_4 0x00004000U /*!<Bit 4 */
+#define ADC_SQR1_SQ16 0x000F8000U /*!<SQ16[4:0] bits (16th conversion in regular sequence) */
+#define ADC_SQR1_SQ16_0 0x00008000U /*!<Bit 0 */
+#define ADC_SQR1_SQ16_1 0x00010000U /*!<Bit 1 */
+#define ADC_SQR1_SQ16_2 0x00020000U /*!<Bit 2 */
+#define ADC_SQR1_SQ16_3 0x00040000U /*!<Bit 3 */
+#define ADC_SQR1_SQ16_4 0x00080000U /*!<Bit 4 */
+#define ADC_SQR1_L 0x00F00000U /*!<L[3:0] bits (Regular channel sequence length) */
+#define ADC_SQR1_L_0 0x00100000U /*!<Bit 0 */
+#define ADC_SQR1_L_1 0x00200000U /*!<Bit 1 */
+#define ADC_SQR1_L_2 0x00400000U /*!<Bit 2 */
+#define ADC_SQR1_L_3 0x00800000U /*!<Bit 3 */
+
+/******************* Bit definition for ADC_SQR2 register *******************/
+#define ADC_SQR2_SQ7 0x0000001FU /*!<SQ7[4:0] bits (7th conversion in regular sequence) */
+#define ADC_SQR2_SQ7_0 0x00000001U /*!<Bit 0 */
+#define ADC_SQR2_SQ7_1 0x00000002U /*!<Bit 1 */
+#define ADC_SQR2_SQ7_2 0x00000004U /*!<Bit 2 */
+#define ADC_SQR2_SQ7_3 0x00000008U /*!<Bit 3 */
+#define ADC_SQR2_SQ7_4 0x00000010U /*!<Bit 4 */
+#define ADC_SQR2_SQ8 0x000003E0U /*!<SQ8[4:0] bits (8th conversion in regular sequence) */
+#define ADC_SQR2_SQ8_0 0x00000020U /*!<Bit 0 */
+#define ADC_SQR2_SQ8_1 0x00000040U /*!<Bit 1 */
+#define ADC_SQR2_SQ8_2 0x00000080U /*!<Bit 2 */
+#define ADC_SQR2_SQ8_3 0x00000100U /*!<Bit 3 */
+#define ADC_SQR2_SQ8_4 0x00000200U /*!<Bit 4 */
+#define ADC_SQR2_SQ9 0x00007C00U /*!<SQ9[4:0] bits (9th conversion in regular sequence) */
+#define ADC_SQR2_SQ9_0 0x00000400U /*!<Bit 0 */
+#define ADC_SQR2_SQ9_1 0x00000800U /*!<Bit 1 */
+#define ADC_SQR2_SQ9_2 0x00001000U /*!<Bit 2 */
+#define ADC_SQR2_SQ9_3 0x00002000U /*!<Bit 3 */
+#define ADC_SQR2_SQ9_4 0x00004000U /*!<Bit 4 */
+#define ADC_SQR2_SQ10 0x000F8000U /*!<SQ10[4:0] bits (10th conversion in regular sequence) */
+#define ADC_SQR2_SQ10_0 0x00008000U /*!<Bit 0 */
+#define ADC_SQR2_SQ10_1 0x00010000U /*!<Bit 1 */
+#define ADC_SQR2_SQ10_2 0x00020000U /*!<Bit 2 */
+#define ADC_SQR2_SQ10_3 0x00040000U /*!<Bit 3 */
+#define ADC_SQR2_SQ10_4 0x00080000U /*!<Bit 4 */
+#define ADC_SQR2_SQ11 0x01F00000U /*!<SQ11[4:0] bits (11th conversion in regular sequence) */
+#define ADC_SQR2_SQ11_0 0x00100000U /*!<Bit 0 */
+#define ADC_SQR2_SQ11_1 0x00200000U /*!<Bit 1 */
+#define ADC_SQR2_SQ11_2 0x00400000U /*!<Bit 2 */
+#define ADC_SQR2_SQ11_3 0x00800000U /*!<Bit 3 */
+#define ADC_SQR2_SQ11_4 0x01000000U /*!<Bit 4 */
+#define ADC_SQR2_SQ12 0x3E000000U /*!<SQ12[4:0] bits (12th conversion in regular sequence) */
+#define ADC_SQR2_SQ12_0 0x02000000U /*!<Bit 0 */
+#define ADC_SQR2_SQ12_1 0x04000000U /*!<Bit 1 */
+#define ADC_SQR2_SQ12_2 0x08000000U /*!<Bit 2 */
+#define ADC_SQR2_SQ12_3 0x10000000U /*!<Bit 3 */
+#define ADC_SQR2_SQ12_4 0x20000000U /*!<Bit 4 */
+
+/******************* Bit definition for ADC_SQR3 register *******************/
+#define ADC_SQR3_SQ1 0x0000001FU /*!<SQ1[4:0] bits (1st conversion in regular sequence) */
+#define ADC_SQR3_SQ1_0 0x00000001U /*!<Bit 0 */
+#define ADC_SQR3_SQ1_1 0x00000002U /*!<Bit 1 */
+#define ADC_SQR3_SQ1_2 0x00000004U /*!<Bit 2 */
+#define ADC_SQR3_SQ1_3 0x00000008U /*!<Bit 3 */
+#define ADC_SQR3_SQ1_4 0x00000010U /*!<Bit 4 */
+#define ADC_SQR3_SQ2 0x000003E0U /*!<SQ2[4:0] bits (2nd conversion in regular sequence) */
+#define ADC_SQR3_SQ2_0 0x00000020U /*!<Bit 0 */
+#define ADC_SQR3_SQ2_1 0x00000040U /*!<Bit 1 */
+#define ADC_SQR3_SQ2_2 0x00000080U /*!<Bit 2 */
+#define ADC_SQR3_SQ2_3 0x00000100U /*!<Bit 3 */
+#define ADC_SQR3_SQ2_4 0x00000200U /*!<Bit 4 */
+#define ADC_SQR3_SQ3 0x00007C00U /*!<SQ3[4:0] bits (3rd conversion in regular sequence) */
+#define ADC_SQR3_SQ3_0 0x00000400U /*!<Bit 0 */
+#define ADC_SQR3_SQ3_1 0x00000800U /*!<Bit 1 */
+#define ADC_SQR3_SQ3_2 0x00001000U /*!<Bit 2 */
+#define ADC_SQR3_SQ3_3 0x00002000U /*!<Bit 3 */
+#define ADC_SQR3_SQ3_4 0x00004000U /*!<Bit 4 */
+#define ADC_SQR3_SQ4 0x000F8000U /*!<SQ4[4:0] bits (4th conversion in regular sequence) */
+#define ADC_SQR3_SQ4_0 0x00008000U /*!<Bit 0 */
+#define ADC_SQR3_SQ4_1 0x00010000U /*!<Bit 1 */
+#define ADC_SQR3_SQ4_2 0x00020000U /*!<Bit 2 */
+#define ADC_SQR3_SQ4_3 0x00040000U /*!<Bit 3 */
+#define ADC_SQR3_SQ4_4 0x00080000U /*!<Bit 4 */
+#define ADC_SQR3_SQ5 0x01F00000U /*!<SQ5[4:0] bits (5th conversion in regular sequence) */
+#define ADC_SQR3_SQ5_0 0x00100000U /*!<Bit 0 */
+#define ADC_SQR3_SQ5_1 0x00200000U /*!<Bit 1 */
+#define ADC_SQR3_SQ5_2 0x00400000U /*!<Bit 2 */
+#define ADC_SQR3_SQ5_3 0x00800000U /*!<Bit 3 */
+#define ADC_SQR3_SQ5_4 0x01000000U /*!<Bit 4 */
+#define ADC_SQR3_SQ6 0x3E000000U /*!<SQ6[4:0] bits (6th conversion in regular sequence) */
+#define ADC_SQR3_SQ6_0 0x02000000U /*!<Bit 0 */
+#define ADC_SQR3_SQ6_1 0x04000000U /*!<Bit 1 */
+#define ADC_SQR3_SQ6_2 0x08000000U /*!<Bit 2 */
+#define ADC_SQR3_SQ6_3 0x10000000U /*!<Bit 3 */
+#define ADC_SQR3_SQ6_4 0x20000000U /*!<Bit 4 */
+
+/******************* Bit definition for ADC_JSQR register *******************/
+#define ADC_JSQR_JSQ1 0x0000001FU /*!<JSQ1[4:0] bits (1st conversion in injected sequence) */
+#define ADC_JSQR_JSQ1_0 0x00000001U /*!<Bit 0 */
+#define ADC_JSQR_JSQ1_1 0x00000002U /*!<Bit 1 */
+#define ADC_JSQR_JSQ1_2 0x00000004U /*!<Bit 2 */
+#define ADC_JSQR_JSQ1_3 0x00000008U /*!<Bit 3 */
+#define ADC_JSQR_JSQ1_4 0x00000010U /*!<Bit 4 */
+#define ADC_JSQR_JSQ2 0x000003E0U /*!<JSQ2[4:0] bits (2nd conversion in injected sequence) */
+#define ADC_JSQR_JSQ2_0 0x00000020U /*!<Bit 0 */
+#define ADC_JSQR_JSQ2_1 0x00000040U /*!<Bit 1 */
+#define ADC_JSQR_JSQ2_2 0x00000080U /*!<Bit 2 */
+#define ADC_JSQR_JSQ2_3 0x00000100U /*!<Bit 3 */
+#define ADC_JSQR_JSQ2_4 0x00000200U /*!<Bit 4 */
+#define ADC_JSQR_JSQ3 0x00007C00U /*!<JSQ3[4:0] bits (3rd conversion in injected sequence) */
+#define ADC_JSQR_JSQ3_0 0x00000400U /*!<Bit 0 */
+#define ADC_JSQR_JSQ3_1 0x00000800U /*!<Bit 1 */
+#define ADC_JSQR_JSQ3_2 0x00001000U /*!<Bit 2 */
+#define ADC_JSQR_JSQ3_3 0x00002000U /*!<Bit 3 */
+#define ADC_JSQR_JSQ3_4 0x00004000U /*!<Bit 4 */
+#define ADC_JSQR_JSQ4 0x000F8000U /*!<JSQ4[4:0] bits (4th conversion in injected sequence) */
+#define ADC_JSQR_JSQ4_0 0x00008000U /*!<Bit 0 */
+#define ADC_JSQR_JSQ4_1 0x00010000U /*!<Bit 1 */
+#define ADC_JSQR_JSQ4_2 0x00020000U /*!<Bit 2 */
+#define ADC_JSQR_JSQ4_3 0x00040000U /*!<Bit 3 */
+#define ADC_JSQR_JSQ4_4 0x00080000U /*!<Bit 4 */
+#define ADC_JSQR_JL 0x00300000U /*!<JL[1:0] bits (Injected Sequence length) */
+#define ADC_JSQR_JL_0 0x00100000U /*!<Bit 0 */
+#define ADC_JSQR_JL_1 0x00200000U /*!<Bit 1 */
+
+/******************* Bit definition for ADC_JDR1 register *******************/
+#define ADC_JDR1_JDATA 0xFFFFU /*!<Injected data */
+
+/******************* Bit definition for ADC_JDR2 register *******************/
+#define ADC_JDR2_JDATA 0xFFFFU /*!<Injected data */
+
+/******************* Bit definition for ADC_JDR3 register *******************/
+#define ADC_JDR3_JDATA 0xFFFFU /*!<Injected data */
+
+/******************* Bit definition for ADC_JDR4 register *******************/
+#define ADC_JDR4_JDATA 0xFFFFU /*!<Injected data */
+
+/******************** Bit definition for ADC_DR register ********************/
+#define ADC_DR_DATA 0x0000FFFFU /*!<Regular data */
+#define ADC_DR_ADC2DATA 0xFFFF0000U /*!<ADC2 data */
+
+/******************* Bit definition for ADC_CSR register ********************/
+#define ADC_CSR_AWD1 0x00000001U /*!<ADC1 Analog watchdog flag */
+#define ADC_CSR_EOC1 0x00000002U /*!<ADC1 End of conversion */
+#define ADC_CSR_JEOC1 0x00000004U /*!<ADC1 Injected channel end of conversion */
+#define ADC_CSR_JSTRT1 0x00000008U /*!<ADC1 Injected channel Start flag */
+#define ADC_CSR_STRT1 0x00000010U /*!<ADC1 Regular channel Start flag */
+#define ADC_CSR_OVR1 0x00000020U /*!<ADC1 DMA overrun flag */
+#define ADC_CSR_AWD2 0x00000100U /*!<ADC2 Analog watchdog flag */
+#define ADC_CSR_EOC2 0x00000200U /*!<ADC2 End of conversion */
+#define ADC_CSR_JEOC2 0x00000400U /*!<ADC2 Injected channel end of conversion */
+#define ADC_CSR_JSTRT2 0x00000800U /*!<ADC2 Injected channel Start flag */
+#define ADC_CSR_STRT2 0x00001000U /*!<ADC2 Regular channel Start flag */
+#define ADC_CSR_OVR2 0x00002000U /*!<ADC2 DMA overrun flag */
+#define ADC_CSR_AWD3 0x00010000U /*!<ADC3 Analog watchdog flag */
+#define ADC_CSR_EOC3 0x00020000U /*!<ADC3 End of conversion */
+#define ADC_CSR_JEOC3 0x00040000U /*!<ADC3 Injected channel end of conversion */
+#define ADC_CSR_JSTRT3 0x00080000U /*!<ADC3 Injected channel Start flag */
+#define ADC_CSR_STRT3 0x00100000U /*!<ADC3 Regular channel Start flag */
+#define ADC_CSR_OVR3 0x00200000U /*!<ADC3 DMA overrun flag */
+
+/* Legacy defines */
+#define ADC_CSR_DOVR1 ADC_CSR_OVR1
+#define ADC_CSR_DOVR2 ADC_CSR_OVR2
+#define ADC_CSR_DOVR3 ADC_CSR_OVR3
+
+/******************* Bit definition for ADC_CCR register ********************/
+#define ADC_CCR_MULTI 0x0000001FU /*!<MULTI[4:0] bits (Multi-ADC mode selection) */
+#define ADC_CCR_MULTI_0 0x00000001U /*!<Bit 0 */
+#define ADC_CCR_MULTI_1 0x00000002U /*!<Bit 1 */
+#define ADC_CCR_MULTI_2 0x00000004U /*!<Bit 2 */
+#define ADC_CCR_MULTI_3 0x00000008U /*!<Bit 3 */
+#define ADC_CCR_MULTI_4 0x00000010U /*!<Bit 4 */
+#define ADC_CCR_DELAY 0x00000F00U /*!<DELAY[3:0] bits (Delay between 2 sampling phases) */
+#define ADC_CCR_DELAY_0 0x00000100U /*!<Bit 0 */
+#define ADC_CCR_DELAY_1 0x00000200U /*!<Bit 1 */
+#define ADC_CCR_DELAY_2 0x00000400U /*!<Bit 2 */
+#define ADC_CCR_DELAY_3 0x00000800U /*!<Bit 3 */
+#define ADC_CCR_DDS 0x00002000U /*!<DMA disable selection (Multi-ADC mode) */
+#define ADC_CCR_DMA 0x0000C000U /*!<DMA[1:0] bits (Direct Memory Access mode for multimode) */
+#define ADC_CCR_DMA_0 0x00004000U /*!<Bit 0 */
+#define ADC_CCR_DMA_1 0x00008000U /*!<Bit 1 */
+#define ADC_CCR_ADCPRE 0x00030000U /*!<ADCPRE[1:0] bits (ADC prescaler) */
+#define ADC_CCR_ADCPRE_0 0x00010000U /*!<Bit 0 */
+#define ADC_CCR_ADCPRE_1 0x00020000U /*!<Bit 1 */
+#define ADC_CCR_VBATE 0x00400000U /*!<VBAT Enable */
+#define ADC_CCR_TSVREFE 0x00800000U /*!<Temperature Sensor and VREFINT Enable */
+
+/******************* Bit definition for ADC_CDR register ********************/
+#define ADC_CDR_DATA1 0x0000FFFFU /*!<1st data of a pair of regular conversions */
+#define ADC_CDR_DATA2 0xFFFF0000U /*!<2nd data of a pair of regular conversions */
+
+/******************************************************************************/
+/* */
+/* Controller Area Network */
+/* */
+/******************************************************************************/
+/*!<CAN control and status registers */
+/******************* Bit definition for CAN_MCR register ********************/
+#define CAN_MCR_INRQ 0x00000001U /*!<Initialization Request */
+#define CAN_MCR_SLEEP 0x00000002U /*!<Sleep Mode Request */
+#define CAN_MCR_TXFP 0x00000004U /*!<Transmit FIFO Priority */
+#define CAN_MCR_RFLM 0x00000008U /*!<Receive FIFO Locked Mode */
+#define CAN_MCR_NART 0x00000010U /*!<No Automatic Retransmission */
+#define CAN_MCR_AWUM 0x00000020U /*!<Automatic Wakeup Mode */
+#define CAN_MCR_ABOM 0x00000040U /*!<Automatic Bus-Off Management */
+#define CAN_MCR_TTCM 0x00000080U /*!<Time Triggered Communication Mode */
+#define CAN_MCR_RESET 0x00008000U /*!<bxCAN software master reset */
+#define CAN_MCR_DBF 0x00010000U /*!<bxCAN Debug freeze */
+/******************* Bit definition for CAN_MSR register ********************/
+#define CAN_MSR_INAK 0x0001U /*!<Initialization Acknowledge */
+#define CAN_MSR_SLAK 0x0002U /*!<Sleep Acknowledge */
+#define CAN_MSR_ERRI 0x0004U /*!<Error Interrupt */
+#define CAN_MSR_WKUI 0x0008U /*!<Wakeup Interrupt */
+#define CAN_MSR_SLAKI 0x0010U /*!<Sleep Acknowledge Interrupt */
+#define CAN_MSR_TXM 0x0100U /*!<Transmit Mode */
+#define CAN_MSR_RXM 0x0200U /*!<Receive Mode */
+#define CAN_MSR_SAMP 0x0400U /*!<Last Sample Point */
+#define CAN_MSR_RX 0x0800U /*!<CAN Rx Signal */
+
+/******************* Bit definition for CAN_TSR register ********************/
+#define CAN_TSR_RQCP0 0x00000001U /*!<Request Completed Mailbox0 */
+#define CAN_TSR_TXOK0 0x00000002U /*!<Transmission OK of Mailbox0 */
+#define CAN_TSR_ALST0 0x00000004U /*!<Arbitration Lost for Mailbox0 */
+#define CAN_TSR_TERR0 0x00000008U /*!<Transmission Error of Mailbox0 */
+#define CAN_TSR_ABRQ0 0x00000080U /*!<Abort Request for Mailbox0 */
+#define CAN_TSR_RQCP1 0x00000100U /*!<Request Completed Mailbox1 */
+#define CAN_TSR_TXOK1 0x00000200U /*!<Transmission OK of Mailbox1 */
+#define CAN_TSR_ALST1 0x00000400U /*!<Arbitration Lost for Mailbox1 */
+#define CAN_TSR_TERR1 0x00000800U /*!<Transmission Error of Mailbox1 */
+#define CAN_TSR_ABRQ1 0x00008000U /*!<Abort Request for Mailbox 1 */
+#define CAN_TSR_RQCP2 0x00010000U /*!<Request Completed Mailbox2 */
+#define CAN_TSR_TXOK2 0x00020000U /*!<Transmission OK of Mailbox 2 */
+#define CAN_TSR_ALST2 0x00040000U /*!<Arbitration Lost for mailbox 2 */
+#define CAN_TSR_TERR2 0x00080000U /*!<Transmission Error of Mailbox 2 */
+#define CAN_TSR_ABRQ2 0x00800000U /*!<Abort Request for Mailbox 2 */
+#define CAN_TSR_CODE 0x03000000U /*!<Mailbox Code */
+
+#define CAN_TSR_TME 0x1C000000U /*!<TME[2:0] bits */
+#define CAN_TSR_TME0 0x04000000U /*!<Transmit Mailbox 0 Empty */
+#define CAN_TSR_TME1 0x08000000U /*!<Transmit Mailbox 1 Empty */
+#define CAN_TSR_TME2 0x10000000U /*!<Transmit Mailbox 2 Empty */
+
+#define CAN_TSR_LOW 0xE0000000U /*!<LOW[2:0] bits */
+#define CAN_TSR_LOW0 0x20000000U /*!<Lowest Priority Flag for Mailbox 0 */
+#define CAN_TSR_LOW1 0x40000000U /*!<Lowest Priority Flag for Mailbox 1 */
+#define CAN_TSR_LOW2 0x80000000U /*!<Lowest Priority Flag for Mailbox 2 */
+
+/******************* Bit definition for CAN_RF0R register *******************/
+#define CAN_RF0R_FMP0 0x03U /*!<FIFO 0 Message Pending */
+#define CAN_RF0R_FULL0 0x08U /*!<FIFO 0 Full */
+#define CAN_RF0R_FOVR0 0x10U /*!<FIFO 0 Overrun */
+#define CAN_RF0R_RFOM0 0x20U /*!<Release FIFO 0 Output Mailbox */
+
+/******************* Bit definition for CAN_RF1R register *******************/
+#define CAN_RF1R_FMP1 0x03U /*!<FIFO 1 Message Pending */
+#define CAN_RF1R_FULL1 0x08U /*!<FIFO 1 Full */
+#define CAN_RF1R_FOVR1 0x10U /*!<FIFO 1 Overrun */
+#define CAN_RF1R_RFOM1 0x20U /*!<Release FIFO 1 Output Mailbox */
+
+/******************** Bit definition for CAN_IER register *******************/
+#define CAN_IER_TMEIE 0x00000001U /*!<Transmit Mailbox Empty Interrupt Enable */
+#define CAN_IER_FMPIE0 0x00000002U /*!<FIFO Message Pending Interrupt Enable */
+#define CAN_IER_FFIE0 0x00000004U /*!<FIFO Full Interrupt Enable */
+#define CAN_IER_FOVIE0 0x00000008U /*!<FIFO Overrun Interrupt Enable */
+#define CAN_IER_FMPIE1 0x00000010U /*!<FIFO Message Pending Interrupt Enable */
+#define CAN_IER_FFIE1 0x00000020U /*!<FIFO Full Interrupt Enable */
+#define CAN_IER_FOVIE1 0x00000040U /*!<FIFO Overrun Interrupt Enable */
+#define CAN_IER_EWGIE 0x00000100U /*!<Error Warning Interrupt Enable */
+#define CAN_IER_EPVIE 0x00000200U /*!<Error Passive Interrupt Enable */
+#define CAN_IER_BOFIE 0x00000400U /*!<Bus-Off Interrupt Enable */
+#define CAN_IER_LECIE 0x00000800U /*!<Last Error Code Interrupt Enable */
+#define CAN_IER_ERRIE 0x00008000U /*!<Error Interrupt Enable */
+#define CAN_IER_WKUIE 0x00010000U /*!<Wakeup Interrupt Enable */
+#define CAN_IER_SLKIE 0x00020000U /*!<Sleep Interrupt Enable */
+#define CAN_IER_EWGIE 0x00000100U /*!<Error warning interrupt enable */
+#define CAN_IER_EPVIE 0x00000200U /*!<Error passive interrupt enable */
+#define CAN_IER_BOFIE 0x00000400U /*!<Bus-off interrupt enable */
+#define CAN_IER_LECIE 0x00000800U /*!<Last error code interrupt enable */
+#define CAN_IER_ERRIE 0x00008000U /*!<Error interrupt enable */
+
+
+/******************** Bit definition for CAN_ESR register *******************/
+#define CAN_ESR_EWGF 0x00000001U /*!<Error Warning Flag */
+#define CAN_ESR_EPVF 0x00000002U /*!<Error Passive Flag */
+#define CAN_ESR_BOFF 0x00000004U /*!<Bus-Off Flag */
+
+#define CAN_ESR_LEC 0x00000070U /*!<LEC[2:0] bits (Last Error Code) */
+#define CAN_ESR_LEC_0 0x00000010U /*!<Bit 0 */
+#define CAN_ESR_LEC_1 0x00000020U /*!<Bit 1 */
+#define CAN_ESR_LEC_2 0x00000040U /*!<Bit 2 */
+
+#define CAN_ESR_TEC 0x00FF0000U /*!<Least significant byte of the 9-bit Transmit Error Counter */
+#define CAN_ESR_REC 0xFF000000U /*!<Receive Error Counter */
+
+/******************* Bit definition for CAN_BTR register ********************/
+#define CAN_BTR_BRP 0x000003FFU /*!<Baud Rate Prescaler */
+#define CAN_BTR_TS1 0x000F0000U /*!<Time Segment 1 */
+#define CAN_BTR_TS1_0 0x00010000U /*!<Bit 0 */
+#define CAN_BTR_TS1_1 0x00020000U /*!<Bit 1 */
+#define CAN_BTR_TS1_2 0x00040000U /*!<Bit 2 */
+#define CAN_BTR_TS1_3 0x00080000U /*!<Bit 3 */
+#define CAN_BTR_TS2 0x00700000U /*!<Time Segment 2 */
+#define CAN_BTR_TS2_0 0x00100000U /*!<Bit 0 */
+#define CAN_BTR_TS2_1 0x00200000U /*!<Bit 1 */
+#define CAN_BTR_TS2_2 0x00400000U /*!<Bit 2 */
+#define CAN_BTR_SJW 0x03000000U /*!<Resynchronization Jump Width */
+#define CAN_BTR_SJW_0 0x01000000U /*!<Bit 0 */
+#define CAN_BTR_SJW_1 0x02000000U /*!<Bit 1 */
+#define CAN_BTR_LBKM 0x40000000U /*!<Loop Back Mode (Debug) */
+#define CAN_BTR_SILM 0x80000000U /*!<Silent Mode */
+
+
+/*!<Mailbox registers */
+/****************** Bit definition for CAN_TI0R register ********************/
+#define CAN_TI0R_TXRQ 0x00000001U /*!<Transmit Mailbox Request */
+#define CAN_TI0R_RTR 0x00000002U /*!<Remote Transmission Request */
+#define CAN_TI0R_IDE 0x00000004U /*!<Identifier Extension */
+#define CAN_TI0R_EXID 0x001FFFF8U /*!<Extended Identifier */
+#define CAN_TI0R_STID 0xFFE00000U /*!<Standard Identifier or Extended Identifier */
+
+/****************** Bit definition for CAN_TDT0R register *******************/
+#define CAN_TDT0R_DLC 0x0000000FU /*!<Data Length Code */
+#define CAN_TDT0R_TGT 0x00000100U /*!<Transmit Global Time */
+#define CAN_TDT0R_TIME 0xFFFF0000U /*!<Message Time Stamp */
+
+/****************** Bit definition for CAN_TDL0R register *******************/
+#define CAN_TDL0R_DATA0 0x000000FFU /*!<Data byte 0 */
+#define CAN_TDL0R_DATA1 0x0000FF00U /*!<Data byte 1 */
+#define CAN_TDL0R_DATA2 0x00FF0000U /*!<Data byte 2 */
+#define CAN_TDL0R_DATA3 0xFF000000U /*!<Data byte 3 */
+
+/****************** Bit definition for CAN_TDH0R register *******************/
+#define CAN_TDH0R_DATA4 0x000000FFU /*!<Data byte 4 */
+#define CAN_TDH0R_DATA5 0x0000FF00U /*!<Data byte 5 */
+#define CAN_TDH0R_DATA6 0x00FF0000U /*!<Data byte 6 */
+#define CAN_TDH0R_DATA7 0xFF000000U /*!<Data byte 7 */
+
+/******************* Bit definition for CAN_TI1R register *******************/
+#define CAN_TI1R_TXRQ 0x00000001U /*!<Transmit Mailbox Request */
+#define CAN_TI1R_RTR 0x00000002U /*!<Remote Transmission Request */
+#define CAN_TI1R_IDE 0x00000004U /*!<Identifier Extension */
+#define CAN_TI1R_EXID 0x001FFFF8U /*!<Extended Identifier */
+#define CAN_TI1R_STID 0xFFE00000U /*!<Standard Identifier or Extended Identifier */
+
+/******************* Bit definition for CAN_TDT1R register ******************/
+#define CAN_TDT1R_DLC 0x0000000FU /*!<Data Length Code */
+#define CAN_TDT1R_TGT 0x00000100U /*!<Transmit Global Time */
+#define CAN_TDT1R_TIME 0xFFFF0000U /*!<Message Time Stamp */
+
+/******************* Bit definition for CAN_TDL1R register ******************/
+#define CAN_TDL1R_DATA0 0x000000FFU /*!<Data byte 0 */
+#define CAN_TDL1R_DATA1 0x0000FF00U /*!<Data byte 1 */
+#define CAN_TDL1R_DATA2 0x00FF0000U /*!<Data byte 2 */
+#define CAN_TDL1R_DATA3 0xFF000000U /*!<Data byte 3 */
+
+/******************* Bit definition for CAN_TDH1R register ******************/
+#define CAN_TDH1R_DATA4 0x000000FFU /*!<Data byte 4 */
+#define CAN_TDH1R_DATA5 0x0000FF00U /*!<Data byte 5 */
+#define CAN_TDH1R_DATA6 0x00FF0000U /*!<Data byte 6 */
+#define CAN_TDH1R_DATA7 0xFF000000U /*!<Data byte 7 */
+
+/******************* Bit definition for CAN_TI2R register *******************/
+#define CAN_TI2R_TXRQ 0x00000001U /*!<Transmit Mailbox Request */
+#define CAN_TI2R_RTR 0x00000002U /*!<Remote Transmission Request */
+#define CAN_TI2R_IDE 0x00000004U /*!<Identifier Extension */
+#define CAN_TI2R_EXID 0x001FFFF8U /*!<Extended identifier */
+#define CAN_TI2R_STID 0xFFE00000U /*!<Standard Identifier or Extended Identifier */
+
+/******************* Bit definition for CAN_TDT2R register ******************/
+#define CAN_TDT2R_DLC 0x0000000FU /*!<Data Length Code */
+#define CAN_TDT2R_TGT 0x00000100U /*!<Transmit Global Time */
+#define CAN_TDT2R_TIME 0xFFFF0000U /*!<Message Time Stamp */
+
+/******************* Bit definition for CAN_TDL2R register ******************/
+#define CAN_TDL2R_DATA0 0x000000FFU /*!<Data byte 0 */
+#define CAN_TDL2R_DATA1 0x0000FF00U /*!<Data byte 1 */
+#define CAN_TDL2R_DATA2 0x00FF0000U /*!<Data byte 2 */
+#define CAN_TDL2R_DATA3 0xFF000000U /*!<Data byte 3 */
+
+/******************* Bit definition for CAN_TDH2R register ******************/
+#define CAN_TDH2R_DATA4 0x000000FFU /*!<Data byte 4 */
+#define CAN_TDH2R_DATA5 0x0000FF00U /*!<Data byte 5 */
+#define CAN_TDH2R_DATA6 0x00FF0000U /*!<Data byte 6 */
+#define CAN_TDH2R_DATA7 0xFF000000U /*!<Data byte 7 */
+
+/******************* Bit definition for CAN_RI0R register *******************/
+#define CAN_RI0R_RTR 0x00000002U /*!<Remote Transmission Request */
+#define CAN_RI0R_IDE 0x00000004U /*!<Identifier Extension */
+#define CAN_RI0R_EXID 0x001FFFF8U /*!<Extended Identifier */
+#define CAN_RI0R_STID 0xFFE00000U /*!<Standard Identifier or Extended Identifier */
+
+/******************* Bit definition for CAN_RDT0R register ******************/
+#define CAN_RDT0R_DLC 0x0000000FU /*!<Data Length Code */
+#define CAN_RDT0R_FMI 0x0000FF00U /*!<Filter Match Index */
+#define CAN_RDT0R_TIME 0xFFFF0000U /*!<Message Time Stamp */
+
+/******************* Bit definition for CAN_RDL0R register ******************/
+#define CAN_RDL0R_DATA0 0x000000FFU /*!<Data byte 0 */
+#define CAN_RDL0R_DATA1 0x0000FF00U /*!<Data byte 1 */
+#define CAN_RDL0R_DATA2 0x00FF0000U /*!<Data byte 2 */
+#define CAN_RDL0R_DATA3 0xFF000000U /*!<Data byte 3 */
+
+/******************* Bit definition for CAN_RDH0R register ******************/
+#define CAN_RDH0R_DATA4 0x000000FFU /*!<Data byte 4 */
+#define CAN_RDH0R_DATA5 0x0000FF00U /*!<Data byte 5 */
+#define CAN_RDH0R_DATA6 0x00FF0000U /*!<Data byte 6 */
+#define CAN_RDH0R_DATA7 0xFF000000U /*!<Data byte 7 */
+
+/******************* Bit definition for CAN_RI1R register *******************/
+#define CAN_RI1R_RTR 0x00000002U /*!<Remote Transmission Request */
+#define CAN_RI1R_IDE 0x00000004U /*!<Identifier Extension */
+#define CAN_RI1R_EXID 0x001FFFF8U /*!<Extended identifier */
+#define CAN_RI1R_STID 0xFFE00000U /*!<Standard Identifier or Extended Identifier */
+
+/******************* Bit definition for CAN_RDT1R register ******************/
+#define CAN_RDT1R_DLC 0x0000000FU /*!<Data Length Code */
+#define CAN_RDT1R_FMI 0x0000FF00U /*!<Filter Match Index */
+#define CAN_RDT1R_TIME 0xFFFF0000U /*!<Message Time Stamp */
+
+/******************* Bit definition for CAN_RDL1R register ******************/
+#define CAN_RDL1R_DATA0 0x000000FFU /*!<Data byte 0 */
+#define CAN_RDL1R_DATA1 0x0000FF00U /*!<Data byte 1 */
+#define CAN_RDL1R_DATA2 0x00FF0000U /*!<Data byte 2 */
+#define CAN_RDL1R_DATA3 0xFF000000U /*!<Data byte 3 */
+
+/******************* Bit definition for CAN_RDH1R register ******************/
+#define CAN_RDH1R_DATA4 0x000000FFU /*!<Data byte 4 */
+#define CAN_RDH1R_DATA5 0x0000FF00U /*!<Data byte 5 */
+#define CAN_RDH1R_DATA6 0x00FF0000U /*!<Data byte 6 */
+#define CAN_RDH1R_DATA7 0xFF000000U /*!<Data byte 7 */
+
+/*!<CAN filter registers */
+/******************* Bit definition for CAN_FMR register ********************/
+#define CAN_FMR_FINIT 0x01U /*!<Filter Init Mode */
+#define CAN_FMR_CAN2SB 0x00003F00U /*!<CAN2 start bank */
+
+/******************* Bit definition for CAN_FM1R register *******************/
+#define CAN_FM1R_FBM 0x0FFFFFFFU /*!<Filter Mode */
+#define CAN_FM1R_FBM0 0x00000001U /*!<Filter Init Mode bit 0 */
+#define CAN_FM1R_FBM1 0x00000002U /*!<Filter Init Mode bit 1 */
+#define CAN_FM1R_FBM2 0x00000004U /*!<Filter Init Mode bit 2 */
+#define CAN_FM1R_FBM3 0x00000008U /*!<Filter Init Mode bit 3 */
+#define CAN_FM1R_FBM4 0x00000010U /*!<Filter Init Mode bit 4 */
+#define CAN_FM1R_FBM5 0x00000020U /*!<Filter Init Mode bit 5 */
+#define CAN_FM1R_FBM6 0x00000040U /*!<Filter Init Mode bit 6 */
+#define CAN_FM1R_FBM7 0x00000080U /*!<Filter Init Mode bit 7 */
+#define CAN_FM1R_FBM8 0x00000100U /*!<Filter Init Mode bit 8 */
+#define CAN_FM1R_FBM9 0x00000200U /*!<Filter Init Mode bit 9 */
+#define CAN_FM1R_FBM10 0x00000400U /*!<Filter Init Mode bit 10 */
+#define CAN_FM1R_FBM11 0x00000800U /*!<Filter Init Mode bit 11 */
+#define CAN_FM1R_FBM12 0x00001000U /*!<Filter Init Mode bit 12 */
+#define CAN_FM1R_FBM13 0x00002000U /*!<Filter Init Mode bit 13 */
+#define CAN_FM1R_FBM14 0x00004000U /*!<Filter Init Mode bit 14 */
+#define CAN_FM1R_FBM15 0x00008000U /*!<Filter Init Mode bit 15 */
+#define CAN_FM1R_FBM16 0x00010000U /*!<Filter Init Mode bit 16 */
+#define CAN_FM1R_FBM17 0x00020000U /*!<Filter Init Mode bit 17 */
+#define CAN_FM1R_FBM18 0x00040000U /*!<Filter Init Mode bit 18 */
+#define CAN_FM1R_FBM19 0x00080000U /*!<Filter Init Mode bit 19 */
+#define CAN_FM1R_FBM20 0x00100000U /*!<Filter Init Mode bit 20 */
+#define CAN_FM1R_FBM21 0x00200000U /*!<Filter Init Mode bit 21 */
+#define CAN_FM1R_FBM22 0x00400000U /*!<Filter Init Mode bit 22 */
+#define CAN_FM1R_FBM23 0x00800000U /*!<Filter Init Mode bit 23 */
+#define CAN_FM1R_FBM24 0x01000000U /*!<Filter Init Mode bit 24 */
+#define CAN_FM1R_FBM25 0x02000000U /*!<Filter Init Mode bit 25 */
+#define CAN_FM1R_FBM26 0x04000000U /*!<Filter Init Mode bit 26 */
+#define CAN_FM1R_FBM27 0x08000000U /*!<Filter Init Mode bit 27 */
+
+/******************* Bit definition for CAN_FS1R register *******************/
+#define CAN_FS1R_FSC 0x0FFFFFFFU /*!<Filter Scale Configuration */
+#define CAN_FS1R_FSC0 0x00000001U /*!<Filter Scale Configuration bit 0 */
+#define CAN_FS1R_FSC1 0x00000002U /*!<Filter Scale Configuration bit 1 */
+#define CAN_FS1R_FSC2 0x00000004U /*!<Filter Scale Configuration bit 2 */
+#define CAN_FS1R_FSC3 0x00000008U /*!<Filter Scale Configuration bit 3 */
+#define CAN_FS1R_FSC4 0x00000010U /*!<Filter Scale Configuration bit 4 */
+#define CAN_FS1R_FSC5 0x00000020U /*!<Filter Scale Configuration bit 5 */
+#define CAN_FS1R_FSC6 0x00000040U /*!<Filter Scale Configuration bit 6 */
+#define CAN_FS1R_FSC7 0x00000080U /*!<Filter Scale Configuration bit 7 */
+#define CAN_FS1R_FSC8 0x00000100U /*!<Filter Scale Configuration bit 8 */
+#define CAN_FS1R_FSC9 0x00000200U /*!<Filter Scale Configuration bit 9 */
+#define CAN_FS1R_FSC10 0x00000400U /*!<Filter Scale Configuration bit 10 */
+#define CAN_FS1R_FSC11 0x00000800U /*!<Filter Scale Configuration bit 11 */
+#define CAN_FS1R_FSC12 0x00001000U /*!<Filter Scale Configuration bit 12 */
+#define CAN_FS1R_FSC13 0x00002000U /*!<Filter Scale Configuration bit 13 */
+#define CAN_FS1R_FSC14 0x00004000U /*!<Filter Scale Configuration bit 14 */
+#define CAN_FS1R_FSC15 0x00008000U /*!<Filter Scale Configuration bit 15 */
+#define CAN_FS1R_FSC16 0x00010000U /*!<Filter Scale Configuration bit 16 */
+#define CAN_FS1R_FSC17 0x00020000U /*!<Filter Scale Configuration bit 17 */
+#define CAN_FS1R_FSC18 0x00040000U /*!<Filter Scale Configuration bit 18 */
+#define CAN_FS1R_FSC19 0x00080000U /*!<Filter Scale Configuration bit 19 */
+#define CAN_FS1R_FSC20 0x00100000U /*!<Filter Scale Configuration bit 20 */
+#define CAN_FS1R_FSC21 0x00200000U /*!<Filter Scale Configuration bit 21 */
+#define CAN_FS1R_FSC22 0x00400000U /*!<Filter Scale Configuration bit 22 */
+#define CAN_FS1R_FSC23 0x00800000U /*!<Filter Scale Configuration bit 23 */
+#define CAN_FS1R_FSC24 0x01000000U /*!<Filter Scale Configuration bit 24 */
+#define CAN_FS1R_FSC25 0x02000000U /*!<Filter Scale Configuration bit 25 */
+#define CAN_FS1R_FSC26 0x04000000U /*!<Filter Scale Configuration bit 26 */
+#define CAN_FS1R_FSC27 0x08000000U /*!<Filter Scale Configuration bit 27 */
+
+/****************** Bit definition for CAN_FFA1R register *******************/
+#define CAN_FFA1R_FFA 0x0FFFFFFFU /*!<Filter FIFO Assignment */
+#define CAN_FFA1R_FFA0 0x00000001U /*!<Filter FIFO Assignment bit 0 */
+#define CAN_FFA1R_FFA1 0x00000002U /*!<Filter FIFO Assignment bit 1 */
+#define CAN_FFA1R_FFA2 0x00000004U /*!<Filter FIFO Assignment bit 2 */
+#define CAN_FFA1R_FFA3 0x00000008U /*!<Filter FIFO Assignment bit 3 */
+#define CAN_FFA1R_FFA4 0x00000010U /*!<Filter FIFO Assignment bit 4 */
+#define CAN_FFA1R_FFA5 0x00000020U /*!<Filter FIFO Assignment bit 5 */
+#define CAN_FFA1R_FFA6 0x00000040U /*!<Filter FIFO Assignment bit 6 */
+#define CAN_FFA1R_FFA7 0x00000080U /*!<Filter FIFO Assignment bit 7 */
+#define CAN_FFA1R_FFA8 0x00000100U /*!<Filter FIFO Assignment bit 8 */
+#define CAN_FFA1R_FFA9 0x00000200U /*!<Filter FIFO Assignment bit 9 */
+#define CAN_FFA1R_FFA10 0x00000400U /*!<Filter FIFO Assignment bit 10 */
+#define CAN_FFA1R_FFA11 0x00000800U /*!<Filter FIFO Assignment bit 11 */
+#define CAN_FFA1R_FFA12 0x00001000U /*!<Filter FIFO Assignment bit 12 */
+#define CAN_FFA1R_FFA13 0x00002000U /*!<Filter FIFO Assignment bit 13 */
+#define CAN_FFA1R_FFA14 0x00004000U /*!<Filter FIFO Assignment bit 14 */
+#define CAN_FFA1R_FFA15 0x00008000U /*!<Filter FIFO Assignment bit 15 */
+#define CAN_FFA1R_FFA16 0x00010000U /*!<Filter FIFO Assignment bit 16 */
+#define CAN_FFA1R_FFA17 0x00020000U /*!<Filter FIFO Assignment bit 17 */
+#define CAN_FFA1R_FFA18 0x00040000U /*!<Filter FIFO Assignment bit 18 */
+#define CAN_FFA1R_FFA19 0x00080000U /*!<Filter FIFO Assignment bit 19 */
+#define CAN_FFA1R_FFA20 0x00100000U /*!<Filter FIFO Assignment bit 20 */
+#define CAN_FFA1R_FFA21 0x00200000U /*!<Filter FIFO Assignment bit 21 */
+#define CAN_FFA1R_FFA22 0x00400000U /*!<Filter FIFO Assignment bit 22 */
+#define CAN_FFA1R_FFA23 0x00800000U /*!<Filter FIFO Assignment bit 23 */
+#define CAN_FFA1R_FFA24 0x01000000U /*!<Filter FIFO Assignment bit 24 */
+#define CAN_FFA1R_FFA25 0x02000000U /*!<Filter FIFO Assignment bit 25 */
+#define CAN_FFA1R_FFA26 0x04000000U /*!<Filter FIFO Assignment bit 26 */
+#define CAN_FFA1R_FFA27 0x08000000U /*!<Filter FIFO Assignment bit 27 */
+
+/******************* Bit definition for CAN_FA1R register *******************/
+#define CAN_FA1R_FACT 0x0FFFFFFFU /*!<Filter Active */
+#define CAN_FA1R_FACT0 0x00000001U /*!<Filter Active bit 0 */
+#define CAN_FA1R_FACT1 0x00000002U /*!<Filter Active bit 1 */
+#define CAN_FA1R_FACT2 0x00000004U /*!<Filter Active bit 2 */
+#define CAN_FA1R_FACT3 0x00000008U /*!<Filter Active bit 3 */
+#define CAN_FA1R_FACT4 0x00000010U /*!<Filter Active bit 4 */
+#define CAN_FA1R_FACT5 0x00000020U /*!<Filter Active bit 5 */
+#define CAN_FA1R_FACT6 0x00000040U /*!<Filter Active bit 6 */
+#define CAN_FA1R_FACT7 0x00000080U /*!<Filter Active bit 7 */
+#define CAN_FA1R_FACT8 0x00000100U /*!<Filter Active bit 8 */
+#define CAN_FA1R_FACT9 0x00000200U /*!<Filter Active bit 9 */
+#define CAN_FA1R_FACT10 0x00000400U /*!<Filter Active bit 10 */
+#define CAN_FA1R_FACT11 0x00000800U /*!<Filter Active bit 11 */
+#define CAN_FA1R_FACT12 0x00001000U /*!<Filter Active bit 12 */
+#define CAN_FA1R_FACT13 0x00002000U /*!<Filter Active bit 13 */
+#define CAN_FA1R_FACT14 0x00004000U /*!<Filter Active bit 14 */
+#define CAN_FA1R_FACT15 0x00008000U /*!<Filter Active bit 15 */
+#define CAN_FA1R_FACT16 0x00010000U /*!<Filter Active bit 16 */
+#define CAN_FA1R_FACT17 0x00020000U /*!<Filter Active bit 17 */
+#define CAN_FA1R_FACT18 0x00040000U /*!<Filter Active bit 18 */
+#define CAN_FA1R_FACT19 0x00080000U /*!<Filter Active bit 19 */
+#define CAN_FA1R_FACT20 0x00100000U /*!<Filter Active bit 20 */
+#define CAN_FA1R_FACT21 0x00200000U /*!<Filter Active bit 21 */
+#define CAN_FA1R_FACT22 0x00400000U /*!<Filter Active bit 22 */
+#define CAN_FA1R_FACT23 0x00800000U /*!<Filter Active bit 23 */
+#define CAN_FA1R_FACT24 0x01000000U /*!<Filter Active bit 24 */
+#define CAN_FA1R_FACT25 0x02000000U /*!<Filter Active bit 25 */
+#define CAN_FA1R_FACT26 0x04000000U /*!<Filter Active bit 26 */
+#define CAN_FA1R_FACT27 0x08000000U /*!<Filter Active bit 27 */
+
+/******************* Bit definition for CAN_F0R1 register *******************/
+#define CAN_F0R1_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F0R1_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F0R1_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F0R1_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F0R1_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F0R1_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F0R1_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F0R1_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F0R1_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F0R1_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F0R1_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F0R1_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F0R1_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F0R1_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F0R1_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F0R1_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F0R1_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F0R1_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F0R1_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F0R1_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F0R1_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F0R1_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F0R1_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F0R1_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F0R1_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F0R1_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F0R1_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F0R1_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F0R1_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F0R1_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F0R1_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F0R1_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F1R1 register *******************/
+#define CAN_F1R1_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F1R1_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F1R1_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F1R1_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F1R1_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F1R1_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F1R1_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F1R1_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F1R1_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F1R1_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F1R1_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F1R1_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F1R1_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F1R1_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F1R1_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F1R1_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F1R1_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F1R1_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F1R1_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F1R1_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F1R1_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F1R1_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F1R1_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F1R1_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F1R1_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F1R1_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F1R1_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F1R1_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F1R1_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F1R1_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F1R1_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F1R1_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F2R1 register *******************/
+#define CAN_F2R1_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F2R1_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F2R1_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F2R1_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F2R1_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F2R1_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F2R1_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F2R1_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F2R1_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F2R1_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F2R1_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F2R1_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F2R1_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F2R1_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F2R1_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F2R1_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F2R1_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F2R1_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F2R1_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F2R1_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F2R1_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F2R1_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F2R1_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F2R1_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F2R1_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F2R1_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F2R1_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F2R1_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F2R1_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F2R1_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F2R1_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F2R1_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F3R1 register *******************/
+#define CAN_F3R1_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F3R1_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F3R1_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F3R1_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F3R1_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F3R1_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F3R1_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F3R1_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F3R1_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F3R1_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F3R1_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F3R1_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F3R1_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F3R1_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F3R1_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F3R1_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F3R1_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F3R1_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F3R1_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F3R1_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F3R1_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F3R1_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F3R1_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F3R1_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F3R1_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F3R1_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F3R1_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F3R1_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F3R1_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F3R1_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F3R1_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F3R1_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F4R1 register *******************/
+#define CAN_F4R1_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F4R1_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F4R1_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F4R1_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F4R1_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F4R1_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F4R1_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F4R1_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F4R1_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F4R1_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F4R1_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F4R1_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F4R1_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F4R1_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F4R1_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F4R1_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F4R1_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F4R1_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F4R1_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F4R1_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F4R1_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F4R1_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F4R1_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F4R1_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F4R1_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F4R1_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F4R1_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F4R1_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F4R1_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F4R1_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F4R1_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F4R1_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F5R1 register *******************/
+#define CAN_F5R1_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F5R1_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F5R1_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F5R1_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F5R1_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F5R1_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F5R1_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F5R1_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F5R1_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F5R1_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F5R1_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F5R1_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F5R1_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F5R1_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F5R1_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F5R1_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F5R1_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F5R1_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F5R1_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F5R1_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F5R1_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F5R1_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F5R1_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F5R1_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F5R1_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F5R1_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F5R1_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F5R1_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F5R1_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F5R1_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F5R1_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F5R1_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F6R1 register *******************/
+#define CAN_F6R1_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F6R1_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F6R1_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F6R1_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F6R1_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F6R1_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F6R1_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F6R1_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F6R1_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F6R1_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F6R1_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F6R1_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F6R1_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F6R1_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F6R1_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F6R1_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F6R1_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F6R1_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F6R1_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F6R1_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F6R1_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F6R1_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F6R1_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F6R1_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F6R1_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F6R1_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F6R1_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F6R1_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F6R1_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F6R1_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F6R1_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F6R1_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F7R1 register *******************/
+#define CAN_F7R1_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F7R1_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F7R1_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F7R1_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F7R1_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F7R1_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F7R1_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F7R1_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F7R1_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F7R1_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F7R1_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F7R1_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F7R1_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F7R1_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F7R1_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F7R1_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F7R1_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F7R1_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F7R1_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F7R1_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F7R1_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F7R1_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F7R1_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F7R1_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F7R1_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F7R1_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F7R1_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F7R1_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F7R1_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F7R1_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F7R1_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F7R1_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F8R1 register *******************/
+#define CAN_F8R1_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F8R1_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F8R1_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F8R1_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F8R1_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F8R1_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F8R1_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F8R1_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F8R1_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F8R1_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F8R1_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F8R1_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F8R1_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F8R1_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F8R1_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F8R1_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F8R1_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F8R1_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F8R1_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F8R1_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F8R1_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F8R1_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F8R1_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F8R1_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F8R1_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F8R1_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F8R1_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F8R1_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F8R1_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F8R1_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F8R1_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F8R1_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F9R1 register *******************/
+#define CAN_F9R1_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F9R1_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F9R1_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F9R1_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F9R1_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F9R1_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F9R1_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F9R1_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F9R1_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F9R1_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F9R1_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F9R1_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F9R1_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F9R1_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F9R1_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F9R1_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F9R1_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F9R1_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F9R1_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F9R1_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F9R1_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F9R1_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F9R1_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F9R1_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F9R1_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F9R1_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F9R1_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F9R1_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F9R1_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F9R1_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F9R1_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F9R1_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F10R1 register ******************/
+#define CAN_F10R1_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F10R1_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F10R1_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F10R1_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F10R1_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F10R1_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F10R1_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F10R1_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F10R1_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F10R1_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F10R1_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F10R1_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F10R1_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F10R1_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F10R1_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F10R1_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F10R1_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F10R1_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F10R1_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F10R1_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F10R1_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F10R1_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F10R1_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F10R1_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F10R1_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F10R1_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F10R1_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F10R1_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F10R1_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F10R1_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F10R1_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F10R1_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F11R1 register ******************/
+#define CAN_F11R1_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F11R1_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F11R1_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F11R1_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F11R1_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F11R1_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F11R1_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F11R1_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F11R1_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F11R1_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F11R1_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F11R1_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F11R1_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F11R1_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F11R1_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F11R1_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F11R1_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F11R1_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F11R1_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F11R1_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F11R1_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F11R1_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F11R1_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F11R1_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F11R1_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F11R1_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F11R1_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F11R1_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F11R1_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F11R1_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F11R1_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F11R1_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F12R1 register ******************/
+#define CAN_F12R1_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F12R1_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F12R1_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F12R1_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F12R1_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F12R1_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F12R1_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F12R1_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F12R1_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F12R1_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F12R1_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F12R1_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F12R1_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F12R1_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F12R1_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F12R1_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F12R1_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F12R1_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F12R1_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F12R1_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F12R1_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F12R1_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F12R1_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F12R1_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F12R1_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F12R1_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F12R1_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F12R1_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F12R1_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F12R1_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F12R1_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F12R1_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F13R1 register ******************/
+#define CAN_F13R1_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F13R1_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F13R1_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F13R1_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F13R1_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F13R1_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F13R1_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F13R1_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F13R1_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F13R1_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F13R1_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F13R1_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F13R1_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F13R1_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F13R1_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F13R1_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F13R1_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F13R1_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F13R1_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F13R1_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F13R1_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F13R1_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F13R1_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F13R1_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F13R1_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F13R1_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F13R1_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F13R1_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F13R1_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F13R1_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F13R1_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F13R1_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F0R2 register *******************/
+#define CAN_F0R2_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F0R2_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F0R2_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F0R2_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F0R2_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F0R2_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F0R2_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F0R2_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F0R2_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F0R2_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F0R2_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F0R2_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F0R2_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F0R2_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F0R2_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F0R2_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F0R2_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F0R2_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F0R2_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F0R2_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F0R2_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F0R2_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F0R2_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F0R2_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F0R2_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F0R2_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F0R2_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F0R2_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F0R2_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F0R2_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F0R2_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F0R2_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F1R2 register *******************/
+#define CAN_F1R2_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F1R2_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F1R2_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F1R2_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F1R2_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F1R2_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F1R2_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F1R2_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F1R2_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F1R2_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F1R2_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F1R2_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F1R2_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F1R2_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F1R2_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F1R2_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F1R2_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F1R2_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F1R2_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F1R2_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F1R2_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F1R2_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F1R2_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F1R2_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F1R2_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F1R2_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F1R2_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F1R2_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F1R2_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F1R2_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F1R2_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F1R2_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F2R2 register *******************/
+#define CAN_F2R2_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F2R2_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F2R2_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F2R2_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F2R2_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F2R2_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F2R2_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F2R2_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F2R2_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F2R2_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F2R2_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F2R2_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F2R2_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F2R2_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F2R2_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F2R2_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F2R2_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F2R2_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F2R2_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F2R2_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F2R2_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F2R2_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F2R2_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F2R2_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F2R2_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F2R2_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F2R2_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F2R2_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F2R2_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F2R2_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F2R2_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F2R2_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F3R2 register *******************/
+#define CAN_F3R2_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F3R2_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F3R2_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F3R2_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F3R2_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F3R2_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F3R2_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F3R2_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F3R2_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F3R2_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F3R2_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F3R2_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F3R2_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F3R2_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F3R2_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F3R2_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F3R2_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F3R2_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F3R2_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F3R2_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F3R2_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F3R2_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F3R2_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F3R2_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F3R2_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F3R2_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F3R2_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F3R2_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F3R2_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F3R2_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F3R2_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F3R2_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F4R2 register *******************/
+#define CAN_F4R2_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F4R2_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F4R2_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F4R2_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F4R2_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F4R2_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F4R2_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F4R2_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F4R2_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F4R2_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F4R2_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F4R2_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F4R2_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F4R2_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F4R2_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F4R2_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F4R2_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F4R2_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F4R2_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F4R2_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F4R2_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F4R2_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F4R2_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F4R2_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F4R2_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F4R2_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F4R2_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F4R2_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F4R2_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F4R2_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F4R2_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F4R2_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F5R2 register *******************/
+#define CAN_F5R2_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F5R2_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F5R2_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F5R2_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F5R2_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F5R2_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F5R2_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F5R2_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F5R2_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F5R2_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F5R2_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F5R2_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F5R2_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F5R2_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F5R2_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F5R2_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F5R2_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F5R2_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F5R2_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F5R2_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F5R2_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F5R2_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F5R2_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F5R2_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F5R2_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F5R2_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F5R2_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F5R2_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F5R2_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F5R2_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F5R2_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F5R2_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F6R2 register *******************/
+#define CAN_F6R2_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F6R2_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F6R2_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F6R2_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F6R2_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F6R2_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F6R2_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F6R2_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F6R2_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F6R2_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F6R2_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F6R2_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F6R2_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F6R2_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F6R2_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F6R2_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F6R2_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F6R2_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F6R2_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F6R2_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F6R2_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F6R2_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F6R2_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F6R2_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F6R2_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F6R2_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F6R2_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F6R2_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F6R2_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F6R2_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F6R2_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F6R2_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F7R2 register *******************/
+#define CAN_F7R2_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F7R2_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F7R2_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F7R2_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F7R2_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F7R2_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F7R2_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F7R2_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F7R2_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F7R2_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F7R2_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F7R2_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F7R2_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F7R2_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F7R2_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F7R2_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F7R2_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F7R2_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F7R2_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F7R2_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F7R2_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F7R2_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F7R2_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F7R2_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F7R2_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F7R2_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F7R2_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F7R2_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F7R2_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F7R2_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F7R2_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F7R2_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F8R2 register *******************/
+#define CAN_F8R2_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F8R2_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F8R2_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F8R2_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F8R2_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F8R2_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F8R2_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F8R2_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F8R2_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F8R2_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F8R2_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F8R2_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F8R2_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F8R2_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F8R2_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F8R2_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F8R2_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F8R2_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F8R2_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F8R2_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F8R2_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F8R2_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F8R2_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F8R2_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F8R2_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F8R2_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F8R2_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F8R2_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F8R2_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F8R2_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F8R2_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F8R2_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F9R2 register *******************/
+#define CAN_F9R2_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F9R2_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F9R2_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F9R2_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F9R2_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F9R2_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F9R2_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F9R2_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F9R2_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F9R2_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F9R2_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F9R2_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F9R2_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F9R2_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F9R2_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F9R2_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F9R2_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F9R2_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F9R2_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F9R2_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F9R2_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F9R2_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F9R2_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F9R2_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F9R2_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F9R2_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F9R2_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F9R2_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F9R2_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F9R2_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F9R2_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F9R2_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F10R2 register ******************/
+#define CAN_F10R2_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F10R2_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F10R2_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F10R2_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F10R2_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F10R2_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F10R2_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F10R2_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F10R2_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F10R2_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F10R2_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F10R2_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F10R2_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F10R2_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F10R2_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F10R2_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F10R2_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F10R2_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F10R2_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F10R2_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F10R2_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F10R2_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F10R2_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F10R2_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F10R2_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F10R2_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F10R2_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F10R2_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F10R2_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F10R2_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F10R2_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F10R2_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F11R2 register ******************/
+#define CAN_F11R2_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F11R2_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F11R2_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F11R2_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F11R2_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F11R2_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F11R2_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F11R2_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F11R2_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F11R2_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F11R2_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F11R2_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F11R2_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F11R2_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F11R2_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F11R2_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F11R2_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F11R2_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F11R2_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F11R2_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F11R2_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F11R2_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F11R2_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F11R2_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F11R2_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F11R2_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F11R2_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F11R2_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F11R2_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F11R2_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F11R2_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F11R2_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F12R2 register ******************/
+#define CAN_F12R2_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F12R2_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F12R2_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F12R2_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F12R2_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F12R2_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F12R2_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F12R2_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F12R2_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F12R2_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F12R2_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F12R2_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F12R2_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F12R2_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F12R2_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F12R2_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F12R2_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F12R2_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F12R2_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F12R2_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F12R2_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F12R2_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F12R2_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F12R2_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F12R2_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F12R2_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F12R2_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F12R2_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F12R2_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F12R2_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F12R2_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F12R2_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F13R2 register ******************/
+#define CAN_F13R2_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F13R2_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F13R2_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F13R2_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F13R2_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F13R2_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F13R2_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F13R2_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F13R2_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F13R2_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F13R2_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F13R2_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F13R2_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F13R2_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F13R2_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F13R2_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F13R2_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F13R2_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F13R2_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F13R2_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F13R2_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F13R2_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F13R2_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F13R2_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F13R2_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F13R2_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F13R2_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F13R2_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F13R2_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F13R2_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F13R2_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F13R2_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************************************************************************/
+/* */
+/* CRC calculation unit */
+/* */
+/******************************************************************************/
+/******************* Bit definition for CRC_DR register *********************/
+#define CRC_DR_DR 0xFFFFFFFFU /*!< Data register bits */
+
+
+/******************* Bit definition for CRC_IDR register ********************/
+#define CRC_IDR_IDR 0xFFU /*!< General-purpose 8-bit data register bits */
+
+
+/******************** Bit definition for CRC_CR register ********************/
+#define CRC_CR_RESET 0x01U /*!< RESET bit */
+
+/******************************************************************************/
+/* */
+/* Digital to Analog Converter */
+/* */
+/******************************************************************************/
+/******************** Bit definition for DAC_CR register ********************/
+#define DAC_CR_EN1 0x00000001U /*!<DAC channel1 enable */
+#define DAC_CR_BOFF1 0x00000002U /*!<DAC channel1 output buffer disable */
+#define DAC_CR_TEN1 0x00000004U /*!<DAC channel1 Trigger enable */
+
+#define DAC_CR_TSEL1 0x00000038U /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */
+#define DAC_CR_TSEL1_0 0x00000008U /*!<Bit 0 */
+#define DAC_CR_TSEL1_1 0x00000010U /*!<Bit 1 */
+#define DAC_CR_TSEL1_2 0x00000020U /*!<Bit 2 */
+
+#define DAC_CR_WAVE1 0x000000C0U /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
+#define DAC_CR_WAVE1_0 0x00000040U /*!<Bit 0 */
+#define DAC_CR_WAVE1_1 0x00000080U /*!<Bit 1 */
+
+#define DAC_CR_MAMP1 0x00000F00U /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
+#define DAC_CR_MAMP1_0 0x00000100U /*!<Bit 0 */
+#define DAC_CR_MAMP1_1 0x00000200U /*!<Bit 1 */
+#define DAC_CR_MAMP1_2 0x00000400U /*!<Bit 2 */
+#define DAC_CR_MAMP1_3 0x00000800U /*!<Bit 3 */
+
+#define DAC_CR_DMAEN1 0x00001000U /*!<DAC channel1 DMA enable */
+#define DAC_CR_DMAUDRIE1 0x00002000U /*!<DAC channel1 DMA underrun interrupt enable*/
+#define DAC_CR_EN2 0x00010000U /*!<DAC channel2 enable */
+#define DAC_CR_BOFF2 0x00020000U /*!<DAC channel2 output buffer disable */
+#define DAC_CR_TEN2 0x00040000U /*!<DAC channel2 Trigger enable */
+
+#define DAC_CR_TSEL2 0x00380000U /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */
+#define DAC_CR_TSEL2_0 0x00080000U /*!<Bit 0 */
+#define DAC_CR_TSEL2_1 0x00100000U /*!<Bit 1 */
+#define DAC_CR_TSEL2_2 0x00200000U /*!<Bit 2 */
+
+#define DAC_CR_WAVE2 0x00C00000U /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
+#define DAC_CR_WAVE2_0 0x00400000U /*!<Bit 0 */
+#define DAC_CR_WAVE2_1 0x00800000U /*!<Bit 1 */
+
+#define DAC_CR_MAMP2 0x0F000000U /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
+#define DAC_CR_MAMP2_0 0x01000000U /*!<Bit 0 */
+#define DAC_CR_MAMP2_1 0x02000000U /*!<Bit 1 */
+#define DAC_CR_MAMP2_2 0x04000000U /*!<Bit 2 */
+#define DAC_CR_MAMP2_3 0x08000000U /*!<Bit 3 */
+
+#define DAC_CR_DMAEN2 0x10000000U /*!<DAC channel2 DMA enabled */
+#define DAC_CR_DMAUDRIE2 0x20000000U /*!<DAC channel2 DMA underrun interrupt enable*/
+
+/***************** Bit definition for DAC_SWTRIGR register ******************/
+#define DAC_SWTRIGR_SWTRIG1 0x01U /*!<DAC channel1 software trigger */
+#define DAC_SWTRIGR_SWTRIG2 0x02U /*!<DAC channel2 software trigger */
+
+/***************** Bit definition for DAC_DHR12R1 register ******************/
+#define DAC_DHR12R1_DACC1DHR 0x0FFFU /*!<DAC channel1 12-bit Right aligned data */
+
+/***************** Bit definition for DAC_DHR12L1 register ******************/
+#define DAC_DHR12L1_DACC1DHR 0xFFF0U /*!<DAC channel1 12-bit Left aligned data */
+
+/****************** Bit definition for DAC_DHR8R1 register ******************/
+#define DAC_DHR8R1_DACC1DHR 0xFFU /*!<DAC channel1 8-bit Right aligned data */
+
+/***************** Bit definition for DAC_DHR12R2 register ******************/
+#define DAC_DHR12R2_DACC2DHR 0x0FFFU /*!<DAC channel2 12-bit Right aligned data */
+
+/***************** Bit definition for DAC_DHR12L2 register ******************/
+#define DAC_DHR12L2_DACC2DHR 0xFFF0U /*!<DAC channel2 12-bit Left aligned data */
+
+/****************** Bit definition for DAC_DHR8R2 register ******************/
+#define DAC_DHR8R2_DACC2DHR 0xFFU /*!<DAC channel2 8-bit Right aligned data */
+
+/***************** Bit definition for DAC_DHR12RD register ******************/
+#define DAC_DHR12RD_DACC1DHR 0x00000FFFU /*!<DAC channel1 12-bit Right aligned data */
+#define DAC_DHR12RD_DACC2DHR 0x0FFF0000U /*!<DAC channel2 12-bit Right aligned data */
+
+/***************** Bit definition for DAC_DHR12LD register ******************/
+#define DAC_DHR12LD_DACC1DHR 0x0000FFF0U /*!<DAC channel1 12-bit Left aligned data */
+#define DAC_DHR12LD_DACC2DHR 0xFFF00000U /*!<DAC channel2 12-bit Left aligned data */
+
+/****************** Bit definition for DAC_DHR8RD register ******************/
+#define DAC_DHR8RD_DACC1DHR 0x00FFU /*!<DAC channel1 8-bit Right aligned data */
+#define DAC_DHR8RD_DACC2DHR 0xFF00U /*!<DAC channel2 8-bit Right aligned data */
+
+/******************* Bit definition for DAC_DOR1 register *******************/
+#define DAC_DOR1_DACC1DOR 0x0FFFU /*!<DAC channel1 data output */
+
+/******************* Bit definition for DAC_DOR2 register *******************/
+#define DAC_DOR2_DACC2DOR 0x0FFFU /*!<DAC channel2 data output */
+
+/******************** Bit definition for DAC_SR register ********************/
+#define DAC_SR_DMAUDR1 0x00002000U /*!<DAC channel1 DMA underrun flag */
+#define DAC_SR_DMAUDR2 0x20000000U /*!<DAC channel2 DMA underrun flag */
+
+/******************************************************************************/
+/* */
+/* Debug MCU */
+/* */
+/******************************************************************************/
+
+/******************************************************************************/
+/* */
+/* DCMI */
+/* */
+/******************************************************************************/
+/******************** Bits definition for DCMI_CR register ******************/
+#define DCMI_CR_CAPTURE 0x00000001U
+#define DCMI_CR_CM 0x00000002U
+#define DCMI_CR_CROP 0x00000004U
+#define DCMI_CR_JPEG 0x00000008U
+#define DCMI_CR_ESS 0x00000010U
+#define DCMI_CR_PCKPOL 0x00000020U
+#define DCMI_CR_HSPOL 0x00000040U
+#define DCMI_CR_VSPOL 0x00000080U
+#define DCMI_CR_FCRC_0 0x00000100U
+#define DCMI_CR_FCRC_1 0x00000200U
+#define DCMI_CR_EDM_0 0x00000400U
+#define DCMI_CR_EDM_1 0x00000800U
+#define DCMI_CR_CRE 0x00001000U
+#define DCMI_CR_ENABLE 0x00004000U
+
+/******************** Bits definition for DCMI_SR register ******************/
+#define DCMI_SR_HSYNC 0x00000001U
+#define DCMI_SR_VSYNC 0x00000002U
+#define DCMI_SR_FNE 0x00000004U
+
+/******************** Bits definition for DCMI_RIS register *****************/
+#define DCMI_RIS_FRAME_RIS 0x00000001U
+#define DCMI_RIS_OVR_RIS 0x00000002U
+#define DCMI_RIS_ERR_RIS 0x00000004U
+#define DCMI_RIS_VSYNC_RIS 0x00000008U
+#define DCMI_RIS_LINE_RIS 0x00000010U
+/* Legacy defines */
+#define DCMI_RISR_FRAME_RIS DCMI_RIS_FRAME_RIS
+#define DCMI_RISR_OVR_RIS DCMI_RIS_OVR_RIS
+#define DCMI_RISR_ERR_RIS DCMI_RIS_ERR_RIS
+#define DCMI_RISR_VSYNC_RIS DCMI_RIS_VSYNC_RIS
+#define DCMI_RISR_LINE_RIS DCMI_RIS_LINE_RIS
+#define DCMI_RISR_OVF_RIS DCMI_RIS_OVR_RIS
+
+/******************** Bits definition for DCMI_IER register *****************/
+#define DCMI_IER_FRAME_IE 0x00000001U
+#define DCMI_IER_OVR_IE 0x00000002U
+#define DCMI_IER_ERR_IE 0x00000004U
+#define DCMI_IER_VSYNC_IE 0x00000008U
+#define DCMI_IER_LINE_IE 0x00000010U
+/* Legacy defines */
+#define DCMI_IER_OVF_IE DCMI_IER_OVR_IE
+
+/******************** Bits definition for DCMI_MIS register *****************/
+#define DCMI_MIS_FRAME_MIS 0x00000001U
+#define DCMI_MIS_OVR_MIS 0x00000002U
+#define DCMI_MIS_ERR_MIS 0x00000004U
+#define DCMI_MIS_VSYNC_MIS 0x00000008U
+#define DCMI_MIS_LINE_MIS 0x00000010U
+
+/* Legacy defines */
+#define DCMI_MISR_FRAME_MIS DCMI_MIS_FRAME_MIS
+#define DCMI_MISR_OVF_MIS DCMI_MIS_OVR_MIS
+#define DCMI_MISR_ERR_MIS DCMI_MIS_ERR_MIS
+#define DCMI_MISR_VSYNC_MIS DCMI_MIS_VSYNC_MIS
+#define DCMI_MISR_LINE_MIS DCMI_MIS_LINE_MIS
+
+/******************** Bits definition for DCMI_ICR register *****************/
+#define DCMI_ICR_FRAME_ISC 0x00000001U
+#define DCMI_ICR_OVR_ISC 0x00000002U
+#define DCMI_ICR_ERR_ISC 0x00000004U
+#define DCMI_ICR_VSYNC_ISC 0x00000008U
+#define DCMI_ICR_LINE_ISC 0x00000010U
+
+/* Legacy defines */
+#define DCMI_ICR_OVF_ISC DCMI_ICR_OVR_ISC
+
+/******************** Bits definition for DCMI_ESCR register ******************/
+#define DCMI_ESCR_FSC 0x000000FFU
+#define DCMI_ESCR_LSC 0x0000FF00U
+#define DCMI_ESCR_LEC 0x00FF0000U
+#define DCMI_ESCR_FEC 0xFF000000U
+
+/******************** Bits definition for DCMI_ESUR register ******************/
+#define DCMI_ESUR_FSU 0x000000FFU
+#define DCMI_ESUR_LSU 0x0000FF00U
+#define DCMI_ESUR_LEU 0x00FF0000U
+#define DCMI_ESUR_FEU 0xFF000000U
+
+/******************** Bits definition for DCMI_CWSTRT register ******************/
+#define DCMI_CWSTRT_HOFFCNT 0x00003FFFU
+#define DCMI_CWSTRT_VST 0x1FFF0000U
+
+/******************** Bits definition for DCMI_CWSIZE register ******************/
+#define DCMI_CWSIZE_CAPCNT 0x00003FFFU
+#define DCMI_CWSIZE_VLINE 0x3FFF0000U
+
+/******************** Bits definition for DCMI_DR register ******************/
+#define DCMI_DR_BYTE0 0x000000FFU
+#define DCMI_DR_BYTE1 0x0000FF00U
+#define DCMI_DR_BYTE2 0x00FF0000U
+#define DCMI_DR_BYTE3 0xFF000000U
+
+/******************************************************************************/
+/* */
+/* DMA Controller */
+/* */
+/******************************************************************************/
+/******************** Bits definition for DMA_SxCR register *****************/
+#define DMA_SxCR_CHSEL 0x0E000000U
+#define DMA_SxCR_CHSEL_0 0x02000000U
+#define DMA_SxCR_CHSEL_1 0x04000000U
+#define DMA_SxCR_CHSEL_2 0x08000000U
+#define DMA_SxCR_MBURST 0x01800000U
+#define DMA_SxCR_MBURST_0 0x00800000U
+#define DMA_SxCR_MBURST_1 0x01000000U
+#define DMA_SxCR_PBURST 0x00600000U
+#define DMA_SxCR_PBURST_0 0x00200000U
+#define DMA_SxCR_PBURST_1 0x00400000U
+#define DMA_SxCR_CT 0x00080000U
+#define DMA_SxCR_DBM 0x00040000U
+#define DMA_SxCR_PL 0x00030000U
+#define DMA_SxCR_PL_0 0x00010000U
+#define DMA_SxCR_PL_1 0x00020000U
+#define DMA_SxCR_PINCOS 0x00008000U
+#define DMA_SxCR_MSIZE 0x00006000U
+#define DMA_SxCR_MSIZE_0 0x00002000U
+#define DMA_SxCR_MSIZE_1 0x00004000U
+#define DMA_SxCR_PSIZE 0x00001800U
+#define DMA_SxCR_PSIZE_0 0x00000800U
+#define DMA_SxCR_PSIZE_1 0x00001000U
+#define DMA_SxCR_MINC 0x00000400U
+#define DMA_SxCR_PINC 0x00000200U
+#define DMA_SxCR_CIRC 0x00000100U
+#define DMA_SxCR_DIR 0x000000C0U
+#define DMA_SxCR_DIR_0 0x00000040U
+#define DMA_SxCR_DIR_1 0x00000080U
+#define DMA_SxCR_PFCTRL 0x00000020U
+#define DMA_SxCR_TCIE 0x00000010U
+#define DMA_SxCR_HTIE 0x00000008U
+#define DMA_SxCR_TEIE 0x00000004U
+#define DMA_SxCR_DMEIE 0x00000002U
+#define DMA_SxCR_EN 0x00000001U
+
+/* Legacy defines */
+#define DMA_SxCR_ACK 0x00100000U
+
+/******************** Bits definition for DMA_SxCNDTR register **************/
+#define DMA_SxNDT 0x0000FFFFU
+#define DMA_SxNDT_0 0x00000001U
+#define DMA_SxNDT_1 0x00000002U
+#define DMA_SxNDT_2 0x00000004U
+#define DMA_SxNDT_3 0x00000008U
+#define DMA_SxNDT_4 0x00000010U
+#define DMA_SxNDT_5 0x00000020U
+#define DMA_SxNDT_6 0x00000040U
+#define DMA_SxNDT_7 0x00000080U
+#define DMA_SxNDT_8 0x00000100U
+#define DMA_SxNDT_9 0x00000200U
+#define DMA_SxNDT_10 0x00000400U
+#define DMA_SxNDT_11 0x00000800U
+#define DMA_SxNDT_12 0x00001000U
+#define DMA_SxNDT_13 0x00002000U
+#define DMA_SxNDT_14 0x00004000U
+#define DMA_SxNDT_15 0x00008000U
+
+/******************** Bits definition for DMA_SxFCR register ****************/
+#define DMA_SxFCR_FEIE 0x00000080U
+#define DMA_SxFCR_FS 0x00000038U
+#define DMA_SxFCR_FS_0 0x00000008U
+#define DMA_SxFCR_FS_1 0x00000010U
+#define DMA_SxFCR_FS_2 0x00000020U
+#define DMA_SxFCR_DMDIS 0x00000004U
+#define DMA_SxFCR_FTH 0x00000003U
+#define DMA_SxFCR_FTH_0 0x00000001U
+#define DMA_SxFCR_FTH_1 0x00000002U
+
+/******************** Bits definition for DMA_LISR register *****************/
+#define DMA_LISR_TCIF3 0x08000000U
+#define DMA_LISR_HTIF3 0x04000000U
+#define DMA_LISR_TEIF3 0x02000000U
+#define DMA_LISR_DMEIF3 0x01000000U
+#define DMA_LISR_FEIF3 0x00400000U
+#define DMA_LISR_TCIF2 0x00200000U
+#define DMA_LISR_HTIF2 0x00100000U
+#define DMA_LISR_TEIF2 0x00080000U
+#define DMA_LISR_DMEIF2 0x00040000U
+#define DMA_LISR_FEIF2 0x00010000U
+#define DMA_LISR_TCIF1 0x00000800U
+#define DMA_LISR_HTIF1 0x00000400U
+#define DMA_LISR_TEIF1 0x00000200U
+#define DMA_LISR_DMEIF1 0x00000100U
+#define DMA_LISR_FEIF1 0x00000040U
+#define DMA_LISR_TCIF0 0x00000020U
+#define DMA_LISR_HTIF0 0x00000010U
+#define DMA_LISR_TEIF0 0x00000008U
+#define DMA_LISR_DMEIF0 0x00000004U
+#define DMA_LISR_FEIF0 0x00000001U
+
+/******************** Bits definition for DMA_HISR register *****************/
+#define DMA_HISR_TCIF7 0x08000000U
+#define DMA_HISR_HTIF7 0x04000000U
+#define DMA_HISR_TEIF7 0x02000000U
+#define DMA_HISR_DMEIF7 0x01000000U
+#define DMA_HISR_FEIF7 0x00400000U
+#define DMA_HISR_TCIF6 0x00200000U
+#define DMA_HISR_HTIF6 0x00100000U
+#define DMA_HISR_TEIF6 0x00080000U
+#define DMA_HISR_DMEIF6 0x00040000U
+#define DMA_HISR_FEIF6 0x00010000U
+#define DMA_HISR_TCIF5 0x00000800U
+#define DMA_HISR_HTIF5 0x00000400U
+#define DMA_HISR_TEIF5 0x00000200U
+#define DMA_HISR_DMEIF5 0x00000100U
+#define DMA_HISR_FEIF5 0x00000040U
+#define DMA_HISR_TCIF4 0x00000020U
+#define DMA_HISR_HTIF4 0x00000010U
+#define DMA_HISR_TEIF4 0x00000008U
+#define DMA_HISR_DMEIF4 0x00000004U
+#define DMA_HISR_FEIF4 0x00000001U
+
+/******************** Bits definition for DMA_LIFCR register ****************/
+#define DMA_LIFCR_CTCIF3 0x08000000U
+#define DMA_LIFCR_CHTIF3 0x04000000U
+#define DMA_LIFCR_CTEIF3 0x02000000U
+#define DMA_LIFCR_CDMEIF3 0x01000000U
+#define DMA_LIFCR_CFEIF3 0x00400000U
+#define DMA_LIFCR_CTCIF2 0x00200000U
+#define DMA_LIFCR_CHTIF2 0x00100000U
+#define DMA_LIFCR_CTEIF2 0x00080000U
+#define DMA_LIFCR_CDMEIF2 0x00040000U
+#define DMA_LIFCR_CFEIF2 0x00010000U
+#define DMA_LIFCR_CTCIF1 0x00000800U
+#define DMA_LIFCR_CHTIF1 0x00000400U
+#define DMA_LIFCR_CTEIF1 0x00000200U
+#define DMA_LIFCR_CDMEIF1 0x00000100U
+#define DMA_LIFCR_CFEIF1 0x00000040U
+#define DMA_LIFCR_CTCIF0 0x00000020U
+#define DMA_LIFCR_CHTIF0 0x00000010U
+#define DMA_LIFCR_CTEIF0 0x00000008U
+#define DMA_LIFCR_CDMEIF0 0x00000004U
+#define DMA_LIFCR_CFEIF0 0x00000001U
+
+/******************** Bits definition for DMA_HIFCR register ****************/
+#define DMA_HIFCR_CTCIF7 0x08000000U
+#define DMA_HIFCR_CHTIF7 0x04000000U
+#define DMA_HIFCR_CTEIF7 0x02000000U
+#define DMA_HIFCR_CDMEIF7 0x01000000U
+#define DMA_HIFCR_CFEIF7 0x00400000U
+#define DMA_HIFCR_CTCIF6 0x00200000U
+#define DMA_HIFCR_CHTIF6 0x00100000U
+#define DMA_HIFCR_CTEIF6 0x00080000U
+#define DMA_HIFCR_CDMEIF6 0x00040000U
+#define DMA_HIFCR_CFEIF6 0x00010000U
+#define DMA_HIFCR_CTCIF5 0x00000800U
+#define DMA_HIFCR_CHTIF5 0x00000400U
+#define DMA_HIFCR_CTEIF5 0x00000200U
+#define DMA_HIFCR_CDMEIF5 0x00000100U
+#define DMA_HIFCR_CFEIF5 0x00000040U
+#define DMA_HIFCR_CTCIF4 0x00000020U
+#define DMA_HIFCR_CHTIF4 0x00000010U
+#define DMA_HIFCR_CTEIF4 0x00000008U
+#define DMA_HIFCR_CDMEIF4 0x00000004U
+#define DMA_HIFCR_CFEIF4 0x00000001U
+
+
+/******************************************************************************/
+/* */
+/* AHB Master DMA2D Controller (DMA2D) */
+/* */
+/******************************************************************************/
+
+/******************** Bit definition for DMA2D_CR register ******************/
+
+#define DMA2D_CR_START 0x00000001U /*!< Start transfer */
+#define DMA2D_CR_SUSP 0x00000002U /*!< Suspend transfer */
+#define DMA2D_CR_ABORT 0x00000004U /*!< Abort transfer */
+#define DMA2D_CR_TEIE 0x00000100U /*!< Transfer Error Interrupt Enable */
+#define DMA2D_CR_TCIE 0x00000200U /*!< Transfer Complete Interrupt Enable */
+#define DMA2D_CR_TWIE 0x00000400U /*!< Transfer Watermark Interrupt Enable */
+#define DMA2D_CR_CAEIE 0x00000800U /*!< CLUT Access Error Interrupt Enable */
+#define DMA2D_CR_CTCIE 0x00001000U /*!< CLUT Transfer Complete Interrupt Enable */
+#define DMA2D_CR_CEIE 0x00002000U /*!< Configuration Error Interrupt Enable */
+#define DMA2D_CR_MODE 0x00030000U /*!< DMA2D Mode[1:0] */
+#define DMA2D_CR_MODE_0 0x00010000U /*!< DMA2D Mode bit 0 */
+#define DMA2D_CR_MODE_1 0x00020000U /*!< DMA2D Mode bit 1 */
+
+/******************** Bit definition for DMA2D_ISR register *****************/
+
+#define DMA2D_ISR_TEIF 0x00000001U /*!< Transfer Error Interrupt Flag */
+#define DMA2D_ISR_TCIF 0x00000002U /*!< Transfer Complete Interrupt Flag */
+#define DMA2D_ISR_TWIF 0x00000004U /*!< Transfer Watermark Interrupt Flag */
+#define DMA2D_ISR_CAEIF 0x00000008U /*!< CLUT Access Error Interrupt Flag */
+#define DMA2D_ISR_CTCIF 0x00000010U /*!< CLUT Transfer Complete Interrupt Flag */
+#define DMA2D_ISR_CEIF 0x00000020U /*!< Configuration Error Interrupt Flag */
+
+/******************** Bit definition for DMA2D_IFCR register ****************/
+
+#define DMA2D_IFCR_CTEIF 0x00000001U /*!< Clears Transfer Error Interrupt Flag */
+#define DMA2D_IFCR_CTCIF 0x00000002U /*!< Clears Transfer Complete Interrupt Flag */
+#define DMA2D_IFCR_CTWIF 0x00000004U /*!< Clears Transfer Watermark Interrupt Flag */
+#define DMA2D_IFCR_CAECIF 0x00000008U /*!< Clears CLUT Access Error Interrupt Flag */
+#define DMA2D_IFCR_CCTCIF 0x00000010U /*!< Clears CLUT Transfer Complete Interrupt Flag */
+#define DMA2D_IFCR_CCEIF 0x00000020U /*!< Clears Configuration Error Interrupt Flag */
+
+/* Legacy defines */
+#define DMA2D_IFSR_CTEIF DMA2D_IFCR_CTEIF /*!< Clears Transfer Error Interrupt Flag */
+#define DMA2D_IFSR_CTCIF DMA2D_IFCR_CTCIF /*!< Clears Transfer Complete Interrupt Flag */
+#define DMA2D_IFSR_CTWIF DMA2D_IFCR_CTWIF /*!< Clears Transfer Watermark Interrupt Flag */
+#define DMA2D_IFSR_CCAEIF DMA2D_IFCR_CAECIF /*!< Clears CLUT Access Error Interrupt Flag */
+#define DMA2D_IFSR_CCTCIF DMA2D_IFCR_CCTCIF /*!< Clears CLUT Transfer Complete Interrupt Flag */
+#define DMA2D_IFSR_CCEIF DMA2D_IFCR_CCEIF /*!< Clears Configuration Error Interrupt Flag */
+
+/******************** Bit definition for DMA2D_FGMAR register ***************/
+
+#define DMA2D_FGMAR_MA 0xFFFFFFFFU /*!< Memory Address */
+
+/******************** Bit definition for DMA2D_FGOR register ****************/
+
+#define DMA2D_FGOR_LO 0x00003FFFU /*!< Line Offset */
+
+/******************** Bit definition for DMA2D_BGMAR register ***************/
+
+#define DMA2D_BGMAR_MA 0xFFFFFFFFU /*!< Memory Address */
+
+/******************** Bit definition for DMA2D_BGOR register ****************/
+
+#define DMA2D_BGOR_LO 0x00003FFFU /*!< Line Offset */
+
+/******************** Bit definition for DMA2D_FGPFCCR register *************/
+
+#define DMA2D_FGPFCCR_CM 0x0000000FU /*!< Input color mode CM[3:0] */
+#define DMA2D_FGPFCCR_CM_0 0x00000001U /*!< Input color mode CM bit 0 */
+#define DMA2D_FGPFCCR_CM_1 0x00000002U /*!< Input color mode CM bit 1 */
+#define DMA2D_FGPFCCR_CM_2 0x00000004U /*!< Input color mode CM bit 2 */
+#define DMA2D_FGPFCCR_CM_3 0x00000008U /*!< Input color mode CM bit 3 */
+#define DMA2D_FGPFCCR_CCM 0x00000010U /*!< CLUT Color mode */
+#define DMA2D_FGPFCCR_START 0x00000020U /*!< Start */
+#define DMA2D_FGPFCCR_CS 0x0000FF00U /*!< CLUT size */
+#define DMA2D_FGPFCCR_AM 0x00030000U /*!< Alpha mode AM[1:0] */
+#define DMA2D_FGPFCCR_AM_0 0x00010000U /*!< Alpha mode AM bit 0 */
+#define DMA2D_FGPFCCR_AM_1 0x00020000U /*!< Alpha mode AM bit 1 */
+#define DMA2D_FGPFCCR_ALPHA 0xFF000000U /*!< Alpha value */
+
+/******************** Bit definition for DMA2D_FGCOLR register **************/
+
+#define DMA2D_FGCOLR_BLUE 0x000000FFU /*!< Blue Value */
+#define DMA2D_FGCOLR_GREEN 0x0000FF00U /*!< Green Value */
+#define DMA2D_FGCOLR_RED 0x00FF0000U /*!< Red Value */
+
+/******************** Bit definition for DMA2D_BGPFCCR register *************/
+
+#define DMA2D_BGPFCCR_CM 0x0000000FU /*!< Input color mode CM[3:0] */
+#define DMA2D_BGPFCCR_CM_0 0x00000001U /*!< Input color mode CM bit 0 */
+#define DMA2D_BGPFCCR_CM_1 0x00000002U /*!< Input color mode CM bit 1 */
+#define DMA2D_BGPFCCR_CM_2 0x00000004U /*!< Input color mode CM bit 2 */
+#define DMA2D_FGPFCCR_CM_3 0x00000008U /*!< Input color mode CM bit 3 */
+#define DMA2D_BGPFCCR_CCM 0x00000010U /*!< CLUT Color mode */
+#define DMA2D_BGPFCCR_START 0x00000020U /*!< Start */
+#define DMA2D_BGPFCCR_CS 0x0000FF00U /*!< CLUT size */
+#define DMA2D_BGPFCCR_AM 0x00030000U /*!< Alpha mode AM[1:0] */
+#define DMA2D_BGPFCCR_AM_0 0x00010000U /*!< Alpha mode AM bit 0 */
+#define DMA2D_BGPFCCR_AM_1 0x00020000U /*!< Alpha mode AM bit 1 */
+#define DMA2D_BGPFCCR_ALPHA 0xFF000000U /*!< background Input Alpha value */
+
+/******************** Bit definition for DMA2D_BGCOLR register **************/
+
+#define DMA2D_BGCOLR_BLUE 0x000000FFU /*!< Blue Value */
+#define DMA2D_BGCOLR_GREEN 0x0000FF00U /*!< Green Value */
+#define DMA2D_BGCOLR_RED 0x00FF0000U /*!< Red Value */
+
+/******************** Bit definition for DMA2D_FGCMAR register **************/
+
+#define DMA2D_FGCMAR_MA 0xFFFFFFFFU /*!< Memory Address */
+
+/******************** Bit definition for DMA2D_BGCMAR register **************/
+
+#define DMA2D_BGCMAR_MA 0xFFFFFFFFU /*!< Memory Address */
+
+/******************** Bit definition for DMA2D_OPFCCR register **************/
+
+#define DMA2D_OPFCCR_CM 0x00000007U /*!< Color mode CM[2:0] */
+#define DMA2D_OPFCCR_CM_0 0x00000001U /*!< Color mode CM bit 0 */
+#define DMA2D_OPFCCR_CM_1 0x00000002U /*!< Color mode CM bit 1 */
+#define DMA2D_OPFCCR_CM_2 0x00000004U /*!< Color mode CM bit 2 */
+
+/******************** Bit definition for DMA2D_OCOLR register ***************/
+
+/*!<Mode_ARGB8888/RGB888 */
+
+#define DMA2D_OCOLR_BLUE_1 0x000000FFU /*!< BLUE Value */
+#define DMA2D_OCOLR_GREEN_1 0x0000FF00U /*!< GREEN Value */
+#define DMA2D_OCOLR_RED_1 0x00FF0000U /*!< Red Value */
+#define DMA2D_OCOLR_ALPHA_1 0xFF000000U /*!< Alpha Channel Value */
+
+/*!<Mode_RGB565 */
+#define DMA2D_OCOLR_BLUE_2 0x0000001FU /*!< BLUE Value */
+#define DMA2D_OCOLR_GREEN_2 0x000007E0U /*!< GREEN Value */
+#define DMA2D_OCOLR_RED_2 0x0000F800U /*!< Red Value */
+
+/*!<Mode_ARGB1555 */
+#define DMA2D_OCOLR_BLUE_3 0x0000001FU /*!< BLUE Value */
+#define DMA2D_OCOLR_GREEN_3 0x000003E0U /*!< GREEN Value */
+#define DMA2D_OCOLR_RED_3 0x00007C00U /*!< Red Value */
+#define DMA2D_OCOLR_ALPHA_3 0x00008000U /*!< Alpha Channel Value */
+
+/*!<Mode_ARGB4444 */
+#define DMA2D_OCOLR_BLUE_4 0x0000000FU /*!< BLUE Value */
+#define DMA2D_OCOLR_GREEN_4 0x000000F0U /*!< GREEN Value */
+#define DMA2D_OCOLR_RED_4 0x00000F00U /*!< Red Value */
+#define DMA2D_OCOLR_ALPHA_4 0x0000F000U /*!< Alpha Channel Value */
+
+/******************** Bit definition for DMA2D_OMAR register ****************/
+
+#define DMA2D_OMAR_MA 0xFFFFFFFFU /*!< Memory Address */
+
+/******************** Bit definition for DMA2D_OOR register *****************/
+
+#define DMA2D_OOR_LO 0x00003FFFU /*!< Line Offset */
+
+/******************** Bit definition for DMA2D_NLR register *****************/
+
+#define DMA2D_NLR_NL 0x0000FFFFU /*!< Number of Lines */
+#define DMA2D_NLR_PL 0x3FFF0000U /*!< Pixel per Lines */
+
+/******************** Bit definition for DMA2D_LWR register *****************/
+
+#define DMA2D_LWR_LW 0x0000FFFFU /*!< Line Watermark */
+
+/******************** Bit definition for DMA2D_AMTCR register ***************/
+
+#define DMA2D_AMTCR_EN 0x00000001U /*!< Enable */
+#define DMA2D_AMTCR_DT 0x0000FF00U /*!< Dead Time */
+
+/******************** Bit definition for DMA2D_FGCLUT register **************/
+
+/******************** Bit definition for DMA2D_BGCLUT register **************/
+
+
+
+/******************************************************************************/
+/* */
+/* External Interrupt/Event Controller */
+/* */
+/******************************************************************************/
+/******************* Bit definition for EXTI_IMR register *******************/
+#define EXTI_IMR_MR0 0x00000001U /*!< Interrupt Mask on line 0 */
+#define EXTI_IMR_MR1 0x00000002U /*!< Interrupt Mask on line 1 */
+#define EXTI_IMR_MR2 0x00000004U /*!< Interrupt Mask on line 2 */
+#define EXTI_IMR_MR3 0x00000008U /*!< Interrupt Mask on line 3 */
+#define EXTI_IMR_MR4 0x00000010U /*!< Interrupt Mask on line 4 */
+#define EXTI_IMR_MR5 0x00000020U /*!< Interrupt Mask on line 5 */
+#define EXTI_IMR_MR6 0x00000040U /*!< Interrupt Mask on line 6 */
+#define EXTI_IMR_MR7 0x00000080U /*!< Interrupt Mask on line 7 */
+#define EXTI_IMR_MR8 0x00000100U /*!< Interrupt Mask on line 8 */
+#define EXTI_IMR_MR9 0x00000200U /*!< Interrupt Mask on line 9 */
+#define EXTI_IMR_MR10 0x00000400U /*!< Interrupt Mask on line 10 */
+#define EXTI_IMR_MR11 0x00000800U /*!< Interrupt Mask on line 11 */
+#define EXTI_IMR_MR12 0x00001000U /*!< Interrupt Mask on line 12 */
+#define EXTI_IMR_MR13 0x00002000U /*!< Interrupt Mask on line 13 */
+#define EXTI_IMR_MR14 0x00004000U /*!< Interrupt Mask on line 14 */
+#define EXTI_IMR_MR15 0x00008000U /*!< Interrupt Mask on line 15 */
+#define EXTI_IMR_MR16 0x00010000U /*!< Interrupt Mask on line 16 */
+#define EXTI_IMR_MR17 0x00020000U /*!< Interrupt Mask on line 17 */
+#define EXTI_IMR_MR18 0x00040000U /*!< Interrupt Mask on line 18 */
+#define EXTI_IMR_MR19 0x00080000U /*!< Interrupt Mask on line 19 */
+#define EXTI_IMR_MR20 0x00100000U /*!< Interrupt Mask on line 20 */
+#define EXTI_IMR_MR21 0x00200000U /*!< Interrupt Mask on line 21 */
+#define EXTI_IMR_MR22 0x00400000U /*!< Interrupt Mask on line 22 */
+
+/******************* Bit definition for EXTI_EMR register *******************/
+#define EXTI_EMR_MR0 0x00000001U /*!< Event Mask on line 0 */
+#define EXTI_EMR_MR1 0x00000002U /*!< Event Mask on line 1 */
+#define EXTI_EMR_MR2 0x00000004U /*!< Event Mask on line 2 */
+#define EXTI_EMR_MR3 0x00000008U /*!< Event Mask on line 3 */
+#define EXTI_EMR_MR4 0x00000010U /*!< Event Mask on line 4 */
+#define EXTI_EMR_MR5 0x00000020U /*!< Event Mask on line 5 */
+#define EXTI_EMR_MR6 0x00000040U /*!< Event Mask on line 6 */
+#define EXTI_EMR_MR7 0x00000080U /*!< Event Mask on line 7 */
+#define EXTI_EMR_MR8 0x00000100U /*!< Event Mask on line 8 */
+#define EXTI_EMR_MR9 0x00000200U /*!< Event Mask on line 9 */
+#define EXTI_EMR_MR10 0x00000400U /*!< Event Mask on line 10 */
+#define EXTI_EMR_MR11 0x00000800U /*!< Event Mask on line 11 */
+#define EXTI_EMR_MR12 0x00001000U /*!< Event Mask on line 12 */
+#define EXTI_EMR_MR13 0x00002000U /*!< Event Mask on line 13 */
+#define EXTI_EMR_MR14 0x00004000U /*!< Event Mask on line 14 */
+#define EXTI_EMR_MR15 0x00008000U /*!< Event Mask on line 15 */
+#define EXTI_EMR_MR16 0x00010000U /*!< Event Mask on line 16 */
+#define EXTI_EMR_MR17 0x00020000U /*!< Event Mask on line 17 */
+#define EXTI_EMR_MR18 0x00040000U /*!< Event Mask on line 18 */
+#define EXTI_EMR_MR19 0x00080000U /*!< Event Mask on line 19 */
+#define EXTI_EMR_MR20 0x00100000U /*!< Event Mask on line 20 */
+#define EXTI_EMR_MR21 0x00200000U /*!< Event Mask on line 21 */
+#define EXTI_EMR_MR22 0x00400000U /*!< Event Mask on line 22 */
+
+/****************** Bit definition for EXTI_RTSR register *******************/
+#define EXTI_RTSR_TR0 0x00000001U /*!< Rising trigger event configuration bit of line 0 */
+#define EXTI_RTSR_TR1 0x00000002U /*!< Rising trigger event configuration bit of line 1 */
+#define EXTI_RTSR_TR2 0x00000004U /*!< Rising trigger event configuration bit of line 2 */
+#define EXTI_RTSR_TR3 0x00000008U /*!< Rising trigger event configuration bit of line 3 */
+#define EXTI_RTSR_TR4 0x00000010U /*!< Rising trigger event configuration bit of line 4 */
+#define EXTI_RTSR_TR5 0x00000020U /*!< Rising trigger event configuration bit of line 5 */
+#define EXTI_RTSR_TR6 0x00000040U /*!< Rising trigger event configuration bit of line 6 */
+#define EXTI_RTSR_TR7 0x00000080U /*!< Rising trigger event configuration bit of line 7 */
+#define EXTI_RTSR_TR8 0x00000100U /*!< Rising trigger event configuration bit of line 8 */
+#define EXTI_RTSR_TR9 0x00000200U /*!< Rising trigger event configuration bit of line 9 */
+#define EXTI_RTSR_TR10 0x00000400U /*!< Rising trigger event configuration bit of line 10 */
+#define EXTI_RTSR_TR11 0x00000800U /*!< Rising trigger event configuration bit of line 11 */
+#define EXTI_RTSR_TR12 0x00001000U /*!< Rising trigger event configuration bit of line 12 */
+#define EXTI_RTSR_TR13 0x00002000U /*!< Rising trigger event configuration bit of line 13 */
+#define EXTI_RTSR_TR14 0x00004000U /*!< Rising trigger event configuration bit of line 14 */
+#define EXTI_RTSR_TR15 0x00008000U /*!< Rising trigger event configuration bit of line 15 */
+#define EXTI_RTSR_TR16 0x00010000U /*!< Rising trigger event configuration bit of line 16 */
+#define EXTI_RTSR_TR17 0x00020000U /*!< Rising trigger event configuration bit of line 17 */
+#define EXTI_RTSR_TR18 0x00040000U /*!< Rising trigger event configuration bit of line 18 */
+#define EXTI_RTSR_TR19 0x00080000U /*!< Rising trigger event configuration bit of line 19 */
+#define EXTI_RTSR_TR20 0x00100000U /*!< Rising trigger event configuration bit of line 20 */
+#define EXTI_RTSR_TR21 0x00200000U /*!< Rising trigger event configuration bit of line 21 */
+#define EXTI_RTSR_TR22 0x00400000U /*!< Rising trigger event configuration bit of line 22 */
+
+/****************** Bit definition for EXTI_FTSR register *******************/
+#define EXTI_FTSR_TR0 0x00000001U /*!< Falling trigger event configuration bit of line 0 */
+#define EXTI_FTSR_TR1 0x00000002U /*!< Falling trigger event configuration bit of line 1 */
+#define EXTI_FTSR_TR2 0x00000004U /*!< Falling trigger event configuration bit of line 2 */
+#define EXTI_FTSR_TR3 0x00000008U /*!< Falling trigger event configuration bit of line 3 */
+#define EXTI_FTSR_TR4 0x00000010U /*!< Falling trigger event configuration bit of line 4 */
+#define EXTI_FTSR_TR5 0x00000020U /*!< Falling trigger event configuration bit of line 5 */
+#define EXTI_FTSR_TR6 0x00000040U /*!< Falling trigger event configuration bit of line 6 */
+#define EXTI_FTSR_TR7 0x00000080U /*!< Falling trigger event configuration bit of line 7 */
+#define EXTI_FTSR_TR8 0x00000100U /*!< Falling trigger event configuration bit of line 8 */
+#define EXTI_FTSR_TR9 0x00000200U /*!< Falling trigger event configuration bit of line 9 */
+#define EXTI_FTSR_TR10 0x00000400U /*!< Falling trigger event configuration bit of line 10 */
+#define EXTI_FTSR_TR11 0x00000800U /*!< Falling trigger event configuration bit of line 11 */
+#define EXTI_FTSR_TR12 0x00001000U /*!< Falling trigger event configuration bit of line 12 */
+#define EXTI_FTSR_TR13 0x00002000U /*!< Falling trigger event configuration bit of line 13 */
+#define EXTI_FTSR_TR14 0x00004000U /*!< Falling trigger event configuration bit of line 14 */
+#define EXTI_FTSR_TR15 0x00008000U /*!< Falling trigger event configuration bit of line 15 */
+#define EXTI_FTSR_TR16 0x00010000U /*!< Falling trigger event configuration bit of line 16 */
+#define EXTI_FTSR_TR17 0x00020000U /*!< Falling trigger event configuration bit of line 17 */
+#define EXTI_FTSR_TR18 0x00040000U /*!< Falling trigger event configuration bit of line 18 */
+#define EXTI_FTSR_TR19 0x00080000U /*!< Falling trigger event configuration bit of line 19 */
+#define EXTI_FTSR_TR20 0x00100000U /*!< Falling trigger event configuration bit of line 20 */
+#define EXTI_FTSR_TR21 0x00200000U /*!< Falling trigger event configuration bit of line 21 */
+#define EXTI_FTSR_TR22 0x00400000U /*!< Falling trigger event configuration bit of line 22 */
+
+/****************** Bit definition for EXTI_SWIER register ******************/
+#define EXTI_SWIER_SWIER0 0x00000001U /*!< Software Interrupt on line 0 */
+#define EXTI_SWIER_SWIER1 0x00000002U /*!< Software Interrupt on line 1 */
+#define EXTI_SWIER_SWIER2 0x00000004U /*!< Software Interrupt on line 2 */
+#define EXTI_SWIER_SWIER3 0x00000008U /*!< Software Interrupt on line 3 */
+#define EXTI_SWIER_SWIER4 0x00000010U /*!< Software Interrupt on line 4 */
+#define EXTI_SWIER_SWIER5 0x00000020U /*!< Software Interrupt on line 5 */
+#define EXTI_SWIER_SWIER6 0x00000040U /*!< Software Interrupt on line 6 */
+#define EXTI_SWIER_SWIER7 0x00000080U /*!< Software Interrupt on line 7 */
+#define EXTI_SWIER_SWIER8 0x00000100U /*!< Software Interrupt on line 8 */
+#define EXTI_SWIER_SWIER9 0x00000200U /*!< Software Interrupt on line 9 */
+#define EXTI_SWIER_SWIER10 0x00000400U /*!< Software Interrupt on line 10 */
+#define EXTI_SWIER_SWIER11 0x00000800U /*!< Software Interrupt on line 11 */
+#define EXTI_SWIER_SWIER12 0x00001000U /*!< Software Interrupt on line 12 */
+#define EXTI_SWIER_SWIER13 0x00002000U /*!< Software Interrupt on line 13 */
+#define EXTI_SWIER_SWIER14 0x00004000U /*!< Software Interrupt on line 14 */
+#define EXTI_SWIER_SWIER15 0x00008000U /*!< Software Interrupt on line 15 */
+#define EXTI_SWIER_SWIER16 0x00010000U /*!< Software Interrupt on line 16 */
+#define EXTI_SWIER_SWIER17 0x00020000U /*!< Software Interrupt on line 17 */
+#define EXTI_SWIER_SWIER18 0x00040000U /*!< Software Interrupt on line 18 */
+#define EXTI_SWIER_SWIER19 0x00080000U /*!< Software Interrupt on line 19 */
+#define EXTI_SWIER_SWIER20 0x00100000U /*!< Software Interrupt on line 20 */
+#define EXTI_SWIER_SWIER21 0x00200000U /*!< Software Interrupt on line 21 */
+#define EXTI_SWIER_SWIER22 0x00400000U /*!< Software Interrupt on line 22 */
+
+/******************* Bit definition for EXTI_PR register ********************/
+#define EXTI_PR_PR0 0x00000001U /*!< Pending bit for line 0 */
+#define EXTI_PR_PR1 0x00000002U /*!< Pending bit for line 1 */
+#define EXTI_PR_PR2 0x00000004U /*!< Pending bit for line 2 */
+#define EXTI_PR_PR3 0x00000008U /*!< Pending bit for line 3 */
+#define EXTI_PR_PR4 0x00000010U /*!< Pending bit for line 4 */
+#define EXTI_PR_PR5 0x00000020U /*!< Pending bit for line 5 */
+#define EXTI_PR_PR6 0x00000040U /*!< Pending bit for line 6 */
+#define EXTI_PR_PR7 0x00000080U /*!< Pending bit for line 7 */
+#define EXTI_PR_PR8 0x00000100U /*!< Pending bit for line 8 */
+#define EXTI_PR_PR9 0x00000200U /*!< Pending bit for line 9 */
+#define EXTI_PR_PR10 0x00000400U /*!< Pending bit for line 10 */
+#define EXTI_PR_PR11 0x00000800U /*!< Pending bit for line 11 */
+#define EXTI_PR_PR12 0x00001000U /*!< Pending bit for line 12 */
+#define EXTI_PR_PR13 0x00002000U /*!< Pending bit for line 13 */
+#define EXTI_PR_PR14 0x00004000U /*!< Pending bit for line 14 */
+#define EXTI_PR_PR15 0x00008000U /*!< Pending bit for line 15 */
+#define EXTI_PR_PR16 0x00010000U /*!< Pending bit for line 16 */
+#define EXTI_PR_PR17 0x00020000U /*!< Pending bit for line 17 */
+#define EXTI_PR_PR18 0x00040000U /*!< Pending bit for line 18 */
+#define EXTI_PR_PR19 0x00080000U /*!< Pending bit for line 19 */
+#define EXTI_PR_PR20 0x00100000U /*!< Pending bit for line 20 */
+#define EXTI_PR_PR21 0x00200000U /*!< Pending bit for line 21 */
+#define EXTI_PR_PR22 0x00400000U /*!< Pending bit for line 22 */
+
+/******************************************************************************/
+/* */
+/* FLASH */
+/* */
+/******************************************************************************/
+/******************* Bits definition for FLASH_ACR register *****************/
+#define FLASH_ACR_LATENCY 0x0000000FU
+#define FLASH_ACR_LATENCY_0WS 0x00000000U
+#define FLASH_ACR_LATENCY_1WS 0x00000001U
+#define FLASH_ACR_LATENCY_2WS 0x00000002U
+#define FLASH_ACR_LATENCY_3WS 0x00000003U
+#define FLASH_ACR_LATENCY_4WS 0x00000004U
+#define FLASH_ACR_LATENCY_5WS 0x00000005U
+#define FLASH_ACR_LATENCY_6WS 0x00000006U
+#define FLASH_ACR_LATENCY_7WS 0x00000007U
+#define FLASH_ACR_LATENCY_8WS 0x00000008U
+#define FLASH_ACR_LATENCY_9WS 0x00000009U
+#define FLASH_ACR_LATENCY_10WS 0x0000000AU
+#define FLASH_ACR_LATENCY_11WS 0x0000000BU
+#define FLASH_ACR_LATENCY_12WS 0x0000000CU
+#define FLASH_ACR_LATENCY_13WS 0x0000000DU
+#define FLASH_ACR_LATENCY_14WS 0x0000000EU
+#define FLASH_ACR_LATENCY_15WS 0x0000000FU
+#define FLASH_ACR_PRFTEN 0x00000100U
+#define FLASH_ACR_ICEN 0x00000200U
+#define FLASH_ACR_DCEN 0x00000400U
+#define FLASH_ACR_ICRST 0x00000800U
+#define FLASH_ACR_DCRST 0x00001000U
+#define FLASH_ACR_BYTE0_ADDRESS 0x40023C00U
+#define FLASH_ACR_BYTE2_ADDRESS 0x40023C03U
+
+/******************* Bits definition for FLASH_SR register ******************/
+#define FLASH_SR_EOP 0x00000001U
+#define FLASH_SR_SOP 0x00000002U
+#define FLASH_SR_WRPERR 0x00000010U
+#define FLASH_SR_PGAERR 0x00000020U
+#define FLASH_SR_PGPERR 0x00000040U
+#define FLASH_SR_PGSERR 0x00000080U
+#define FLASH_SR_BSY 0x00010000U
+
+/******************* Bits definition for FLASH_CR register ******************/
+#define FLASH_CR_PG 0x00000001U
+#define FLASH_CR_SER 0x00000002U
+#define FLASH_CR_MER 0x00000004U
+#define FLASH_CR_MER1 FLASH_CR_MER
+#define FLASH_CR_SNB 0x000000F8U
+#define FLASH_CR_SNB_0 0x00000008U
+#define FLASH_CR_SNB_1 0x00000010U
+#define FLASH_CR_SNB_2 0x00000020U
+#define FLASH_CR_SNB_3 0x00000040U
+#define FLASH_CR_SNB_4 0x00000080U
+#define FLASH_CR_PSIZE 0x00000300U
+#define FLASH_CR_PSIZE_0 0x00000100U
+#define FLASH_CR_PSIZE_1 0x00000200U
+#define FLASH_CR_MER2 0x00008000U
+#define FLASH_CR_STRT 0x00010000U
+#define FLASH_CR_EOPIE 0x01000000U
+#define FLASH_CR_LOCK 0x80000000U
+
+/******************* Bits definition for FLASH_OPTCR register ***************/
+#define FLASH_OPTCR_OPTLOCK 0x00000001U
+#define FLASH_OPTCR_OPTSTRT 0x00000002U
+#define FLASH_OPTCR_BOR_LEV_0 0x00000004U
+#define FLASH_OPTCR_BOR_LEV_1 0x00000008U
+#define FLASH_OPTCR_BOR_LEV 0x0000000CU
+#define FLASH_OPTCR_BFB2 0x00000010U
+#define FLASH_OPTCR_WDG_SW 0x00000020U
+#define FLASH_OPTCR_nRST_STOP 0x00000040U
+#define FLASH_OPTCR_nRST_STDBY 0x00000080U
+#define FLASH_OPTCR_RDP 0x0000FF00U
+#define FLASH_OPTCR_RDP_0 0x00000100U
+#define FLASH_OPTCR_RDP_1 0x00000200U
+#define FLASH_OPTCR_RDP_2 0x00000400U
+#define FLASH_OPTCR_RDP_3 0x00000800U
+#define FLASH_OPTCR_RDP_4 0x00001000U
+#define FLASH_OPTCR_RDP_5 0x00002000U
+#define FLASH_OPTCR_RDP_6 0x00004000U
+#define FLASH_OPTCR_RDP_7 0x00008000U
+#define FLASH_OPTCR_nWRP 0x0FFF0000U
+#define FLASH_OPTCR_nWRP_0 0x00010000U
+#define FLASH_OPTCR_nWRP_1 0x00020000U
+#define FLASH_OPTCR_nWRP_2 0x00040000U
+#define FLASH_OPTCR_nWRP_3 0x00080000U
+#define FLASH_OPTCR_nWRP_4 0x00100000U
+#define FLASH_OPTCR_nWRP_5 0x00200000U
+#define FLASH_OPTCR_nWRP_6 0x00400000U
+#define FLASH_OPTCR_nWRP_7 0x00800000U
+#define FLASH_OPTCR_nWRP_8 0x01000000U
+#define FLASH_OPTCR_nWRP_9 0x02000000U
+#define FLASH_OPTCR_nWRP_10 0x04000000U
+#define FLASH_OPTCR_nWRP_11 0x08000000U
+#define FLASH_OPTCR_DB1M 0x40000000U
+#define FLASH_OPTCR_SPRMOD 0x80000000U
+
+/****************** Bits definition for FLASH_OPTCR1 register ***************/
+#define FLASH_OPTCR1_nWRP 0x0FFF0000U
+#define FLASH_OPTCR1_nWRP_0 0x00010000U
+#define FLASH_OPTCR1_nWRP_1 0x00020000U
+#define FLASH_OPTCR1_nWRP_2 0x00040000U
+#define FLASH_OPTCR1_nWRP_3 0x00080000U
+#define FLASH_OPTCR1_nWRP_4 0x00100000U
+#define FLASH_OPTCR1_nWRP_5 0x00200000U
+#define FLASH_OPTCR1_nWRP_6 0x00400000U
+#define FLASH_OPTCR1_nWRP_7 0x00800000U
+#define FLASH_OPTCR1_nWRP_8 0x01000000U
+#define FLASH_OPTCR1_nWRP_9 0x02000000U
+#define FLASH_OPTCR1_nWRP_10 0x04000000U
+#define FLASH_OPTCR1_nWRP_11 0x08000000U
+
+/******************************************************************************/
+/* */
+/* Flexible Memory Controller */
+/* */
+/******************************************************************************/
+/****************** Bit definition for FMC_BCR1 register *******************/
+#define FMC_BCR1_MBKEN 0x00000001U /*!<Memory bank enable bit */
+#define FMC_BCR1_MUXEN 0x00000002U /*!<Address/data multiplexing enable bit */
+
+#define FMC_BCR1_MTYP 0x0000000CU /*!<MTYP[1:0] bits (Memory type) */
+#define FMC_BCR1_MTYP_0 0x00000004U /*!<Bit 0 */
+#define FMC_BCR1_MTYP_1 0x00000008U /*!<Bit 1 */
+
+#define FMC_BCR1_MWID 0x00000030U /*!<MWID[1:0] bits (Memory data bus width) */
+#define FMC_BCR1_MWID_0 0x00000010U /*!<Bit 0 */
+#define FMC_BCR1_MWID_1 0x00000020U /*!<Bit 1 */
+
+#define FMC_BCR1_FACCEN 0x00000040U /*!<Flash access enable */
+#define FMC_BCR1_BURSTEN 0x00000100U /*!<Burst enable bit */
+#define FMC_BCR1_WAITPOL 0x00000200U /*!<Wait signal polarity bit */
+#define FMC_BCR1_WRAPMOD 0x00000400U /*!<Wrapped burst mode support */
+#define FMC_BCR1_WAITCFG 0x00000800U /*!<Wait timing configuration */
+#define FMC_BCR1_WREN 0x00001000U /*!<Write enable bit */
+#define FMC_BCR1_WAITEN 0x00002000U /*!<Wait enable bit */
+#define FMC_BCR1_EXTMOD 0x00004000U /*!<Extended mode enable */
+#define FMC_BCR1_ASYNCWAIT 0x00008000U /*!<Asynchronous wait */
+#define FMC_BCR1_CPSIZE 0x00070000U /*!<CRAM page size */
+#define FMC_BCR1_CPSIZE_0 0x00010000U /*!<Bit 0 */
+#define FMC_BCR1_CPSIZE_1 0x00020000U /*!<Bit 1 */
+#define FMC_BCR1_CPSIZE_2 0x00040000U /*!<Bit 2 */
+#define FMC_BCR1_CBURSTRW 0x00080000U /*!<Write burst enable */
+#define FMC_BCR1_CCLKEN 0x00100000U /*!<Continous clock enable */
+
+/****************** Bit definition for FMC_BCR2 register *******************/
+#define FMC_BCR2_MBKEN 0x00000001U /*!<Memory bank enable bit */
+#define FMC_BCR2_MUXEN 0x00000002U /*!<Address/data multiplexing enable bit */
+
+#define FMC_BCR2_MTYP 0x0000000CU /*!<MTYP[1:0] bits (Memory type) */
+#define FMC_BCR2_MTYP_0 0x00000004U /*!<Bit 0 */
+#define FMC_BCR2_MTYP_1 0x00000008U /*!<Bit 1 */
+
+#define FMC_BCR2_MWID 0x00000030U /*!<MWID[1:0] bits (Memory data bus width) */
+#define FMC_BCR2_MWID_0 0x00000010U /*!<Bit 0 */
+#define FMC_BCR2_MWID_1 0x00000020U /*!<Bit 1 */
+
+#define FMC_BCR2_FACCEN 0x00000040U /*!<Flash access enable */
+#define FMC_BCR2_BURSTEN 0x00000100U /*!<Burst enable bit */
+#define FMC_BCR2_WAITPOL 0x00000200U /*!<Wait signal polarity bit */
+#define FMC_BCR2_WRAPMOD 0x00000400U /*!<Wrapped burst mode support */
+#define FMC_BCR2_WAITCFG 0x00000800U /*!<Wait timing configuration */
+#define FMC_BCR2_WREN 0x00001000U /*!<Write enable bit */
+#define FMC_BCR2_WAITEN 0x00002000U /*!<Wait enable bit */
+#define FMC_BCR2_EXTMOD 0x00004000U /*!<Extended mode enable */
+#define FMC_BCR2_ASYNCWAIT 0x00008000U /*!<Asynchronous wait */
+#define FMC_BCR2_CPSIZE 0x00070000U /*!<CRAM page size */
+#define FMC_BCR2_CPSIZE_0 0x00010000U /*!<Bit 0 */
+#define FMC_BCR2_CPSIZE_1 0x00020000U /*!<Bit 1 */
+#define FMC_BCR2_CPSIZE_2 0x00040000U /*!<Bit 2 */
+#define FMC_BCR2_CBURSTRW 0x00080000U /*!<Write burst enable */
+
+/****************** Bit definition for FMC_BCR3 register *******************/
+#define FMC_BCR3_MBKEN 0x00000001U /*!<Memory bank enable bit */
+#define FMC_BCR3_MUXEN 0x00000002U /*!<Address/data multiplexing enable bit */
+
+#define FMC_BCR3_MTYP 0x0000000CU /*!<MTYP[1:0] bits (Memory type) */
+#define FMC_BCR3_MTYP_0 0x00000004U /*!<Bit 0 */
+#define FMC_BCR3_MTYP_1 0x00000008U /*!<Bit 1 */
+
+#define FMC_BCR3_MWID 0x00000030U /*!<MWID[1:0] bits (Memory data bus width) */
+#define FMC_BCR3_MWID_0 0x00000010U /*!<Bit 0 */
+#define FMC_BCR3_MWID_1 0x00000020U /*!<Bit 1 */
+
+#define FMC_BCR3_FACCEN 0x00000040U /*!<Flash access enable */
+#define FMC_BCR3_BURSTEN 0x00000100U /*!<Burst enable bit */
+#define FMC_BCR3_WAITPOL 0x00000200U /*!<Wait signal polarity bit */
+#define FMC_BCR3_WRAPMOD 0x00000400U /*!<Wrapped burst mode support */
+#define FMC_BCR3_WAITCFG 0x00000800U /*!<Wait timing configuration */
+#define FMC_BCR3_WREN 0x00001000U /*!<Write enable bit */
+#define FMC_BCR3_WAITEN 0x00002000U /*!<Wait enable bit */
+#define FMC_BCR3_EXTMOD 0x00004000U /*!<Extended mode enable */
+#define FMC_BCR3_ASYNCWAIT 0x00008000U /*!<Asynchronous wait */
+#define FMC_BCR3_CPSIZE 0x00070000U /*!<CRAM page size */
+#define FMC_BCR3_CPSIZE_0 0x00010000U /*!<Bit 0 */
+#define FMC_BCR3_CPSIZE_1 0x00020000U /*!<Bit 1 */
+#define FMC_BCR3_CPSIZE_2 0x00040000U /*!<Bit 2 */
+#define FMC_BCR3_CBURSTRW 0x00080000U /*!<Write burst enable */
+
+/****************** Bit definition for FMC_BCR4 register *******************/
+#define FMC_BCR4_MBKEN 0x00000001U /*!<Memory bank enable bit */
+#define FMC_BCR4_MUXEN 0x00000002U /*!<Address/data multiplexing enable bit */
+
+#define FMC_BCR4_MTYP 0x0000000CU /*!<MTYP[1:0] bits (Memory type) */
+#define FMC_BCR4_MTYP_0 0x00000004U /*!<Bit 0 */
+#define FMC_BCR4_MTYP_1 0x00000008U /*!<Bit 1 */
+
+#define FMC_BCR4_MWID 0x00000030U /*!<MWID[1:0] bits (Memory data bus width) */
+#define FMC_BCR4_MWID_0 0x00000010U /*!<Bit 0 */
+#define FMC_BCR4_MWID_1 0x00000020U /*!<Bit 1 */
+
+#define FMC_BCR4_FACCEN 0x00000040U /*!<Flash access enable */
+#define FMC_BCR4_BURSTEN 0x00000100U /*!<Burst enable bit */
+#define FMC_BCR4_WAITPOL 0x00000200U /*!<Wait signal polarity bit */
+#define FMC_BCR4_WRAPMOD 0x00000400U /*!<Wrapped burst mode support */
+#define FMC_BCR4_WAITCFG 0x00000800U /*!<Wait timing configuration */
+#define FMC_BCR4_WREN 0x00001000U /*!<Write enable bit */
+#define FMC_BCR4_WAITEN 0x00002000U /*!<Wait enable bit */
+#define FMC_BCR4_EXTMOD 0x00004000U /*!<Extended mode enable */
+#define FMC_BCR4_ASYNCWAIT 0x00008000U /*!<Asynchronous wait */
+#define FMC_BCR4_CPSIZE 0x00070000U /*!<CRAM page size */
+#define FMC_BCR4_CPSIZE_0 0x00010000U /*!<Bit 0 */
+#define FMC_BCR4_CPSIZE_1 0x00020000U /*!<Bit 1 */
+#define FMC_BCR4_CPSIZE_2 0x00040000U /*!<Bit 2 */
+#define FMC_BCR4_CBURSTRW 0x00080000U /*!<Write burst enable */
+
+/****************** Bit definition for FMC_BTR1 register ******************/
+#define FMC_BTR1_ADDSET 0x0000000FU /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FMC_BTR1_ADDSET_0 0x00000001U /*!<Bit 0 */
+#define FMC_BTR1_ADDSET_1 0x00000002U /*!<Bit 1 */
+#define FMC_BTR1_ADDSET_2 0x00000004U /*!<Bit 2 */
+#define FMC_BTR1_ADDSET_3 0x00000008U /*!<Bit 3 */
+
+#define FMC_BTR1_ADDHLD 0x000000F0U /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FMC_BTR1_ADDHLD_0 0x00000010U /*!<Bit 0 */
+#define FMC_BTR1_ADDHLD_1 0x00000020U /*!<Bit 1 */
+#define FMC_BTR1_ADDHLD_2 0x00000040U /*!<Bit 2 */
+#define FMC_BTR1_ADDHLD_3 0x00000080U /*!<Bit 3 */
+
+#define FMC_BTR1_DATAST 0x0000FF00U /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FMC_BTR1_DATAST_0 0x00000100U /*!<Bit 0 */
+#define FMC_BTR1_DATAST_1 0x00000200U /*!<Bit 1 */
+#define FMC_BTR1_DATAST_2 0x00000400U /*!<Bit 2 */
+#define FMC_BTR1_DATAST_3 0x00000800U /*!<Bit 3 */
+#define FMC_BTR1_DATAST_4 0x00001000U /*!<Bit 4 */
+#define FMC_BTR1_DATAST_5 0x00002000U /*!<Bit 5 */
+#define FMC_BTR1_DATAST_6 0x00004000U /*!<Bit 6 */
+#define FMC_BTR1_DATAST_7 0x00008000U /*!<Bit 7 */
+
+#define FMC_BTR1_BUSTURN 0x000F0000U /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define FMC_BTR1_BUSTURN_0 0x00010000U /*!<Bit 0 */
+#define FMC_BTR1_BUSTURN_1 0x00020000U /*!<Bit 1 */
+#define FMC_BTR1_BUSTURN_2 0x00040000U /*!<Bit 2 */
+#define FMC_BTR1_BUSTURN_3 0x00080000U /*!<Bit 3 */
+
+#define FMC_BTR1_CLKDIV 0x00F00000U /*!<CLKDIV[3:0] bits (Clock divide ratio) */
+#define FMC_BTR1_CLKDIV_0 0x00100000U /*!<Bit 0 */
+#define FMC_BTR1_CLKDIV_1 0x00200000U /*!<Bit 1 */
+#define FMC_BTR1_CLKDIV_2 0x00400000U /*!<Bit 2 */
+#define FMC_BTR1_CLKDIV_3 0x00800000U /*!<Bit 3 */
+
+#define FMC_BTR1_DATLAT 0x0F000000U /*!<DATLA[3:0] bits (Data latency) */
+#define FMC_BTR1_DATLAT_0 0x01000000U /*!<Bit 0 */
+#define FMC_BTR1_DATLAT_1 0x02000000U /*!<Bit 1 */
+#define FMC_BTR1_DATLAT_2 0x04000000U /*!<Bit 2 */
+#define FMC_BTR1_DATLAT_3 0x08000000U /*!<Bit 3 */
+
+#define FMC_BTR1_ACCMOD 0x30000000U /*!<ACCMOD[1:0] bits (Access mode) */
+#define FMC_BTR1_ACCMOD_0 0x10000000U /*!<Bit 0 */
+#define FMC_BTR1_ACCMOD_1 0x20000000U /*!<Bit 1 */
+
+/****************** Bit definition for FMC_BTR2 register *******************/
+#define FMC_BTR2_ADDSET 0x0000000FU /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FMC_BTR2_ADDSET_0 0x00000001U /*!<Bit 0 */
+#define FMC_BTR2_ADDSET_1 0x00000002U /*!<Bit 1 */
+#define FMC_BTR2_ADDSET_2 0x00000004U /*!<Bit 2 */
+#define FMC_BTR2_ADDSET_3 0x00000008U /*!<Bit 3 */
+
+#define FMC_BTR2_ADDHLD 0x000000F0U /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FMC_BTR2_ADDHLD_0 0x00000010U /*!<Bit 0 */
+#define FMC_BTR2_ADDHLD_1 0x00000020U /*!<Bit 1 */
+#define FMC_BTR2_ADDHLD_2 0x00000040U /*!<Bit 2 */
+#define FMC_BTR2_ADDHLD_3 0x00000080U /*!<Bit 3 */
+
+#define FMC_BTR2_DATAST 0x0000FF00U /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FMC_BTR2_DATAST_0 0x00000100U /*!<Bit 0 */
+#define FMC_BTR2_DATAST_1 0x00000200U /*!<Bit 1 */
+#define FMC_BTR2_DATAST_2 0x00000400U /*!<Bit 2 */
+#define FMC_BTR2_DATAST_3 0x00000800U /*!<Bit 3 */
+#define FMC_BTR2_DATAST_4 0x00001000U /*!<Bit 4 */
+#define FMC_BTR2_DATAST_5 0x00002000U /*!<Bit 5 */
+#define FMC_BTR2_DATAST_6 0x00004000U /*!<Bit 6 */
+#define FMC_BTR2_DATAST_7 0x00008000U /*!<Bit 7 */
+
+#define FMC_BTR2_BUSTURN 0x000F0000U /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define FMC_BTR2_BUSTURN_0 0x00010000U /*!<Bit 0 */
+#define FMC_BTR2_BUSTURN_1 0x00020000U /*!<Bit 1 */
+#define FMC_BTR2_BUSTURN_2 0x00040000U /*!<Bit 2 */
+#define FMC_BTR2_BUSTURN_3 0x00080000U /*!<Bit 3 */
+
+#define FMC_BTR2_CLKDIV 0x00F00000U /*!<CLKDIV[3:0] bits (Clock divide ratio) */
+#define FMC_BTR2_CLKDIV_0 0x00100000U /*!<Bit 0 */
+#define FMC_BTR2_CLKDIV_1 0x00200000U /*!<Bit 1 */
+#define FMC_BTR2_CLKDIV_2 0x00400000U /*!<Bit 2 */
+#define FMC_BTR2_CLKDIV_3 0x00800000U /*!<Bit 3 */
+
+#define FMC_BTR2_DATLAT 0x0F000000U /*!<DATLA[3:0] bits (Data latency) */
+#define FMC_BTR2_DATLAT_0 0x01000000U /*!<Bit 0 */
+#define FMC_BTR2_DATLAT_1 0x02000000U /*!<Bit 1 */
+#define FMC_BTR2_DATLAT_2 0x04000000U /*!<Bit 2 */
+#define FMC_BTR2_DATLAT_3 0x08000000U /*!<Bit 3 */
+
+#define FMC_BTR2_ACCMOD 0x30000000U /*!<ACCMOD[1:0] bits (Access mode) */
+#define FMC_BTR2_ACCMOD_0 0x10000000U /*!<Bit 0 */
+#define FMC_BTR2_ACCMOD_1 0x20000000U /*!<Bit 1 */
+
+/******************* Bit definition for FMC_BTR3 register *******************/
+#define FMC_BTR3_ADDSET 0x0000000FU /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FMC_BTR3_ADDSET_0 0x00000001U /*!<Bit 0 */
+#define FMC_BTR3_ADDSET_1 0x00000002U /*!<Bit 1 */
+#define FMC_BTR3_ADDSET_2 0x00000004U /*!<Bit 2 */
+#define FMC_BTR3_ADDSET_3 0x00000008U /*!<Bit 3 */
+
+#define FMC_BTR3_ADDHLD 0x000000F0U /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FMC_BTR3_ADDHLD_0 0x00000010U /*!<Bit 0 */
+#define FMC_BTR3_ADDHLD_1 0x00000020U /*!<Bit 1 */
+#define FMC_BTR3_ADDHLD_2 0x00000040U /*!<Bit 2 */
+#define FMC_BTR3_ADDHLD_3 0x00000080U /*!<Bit 3 */
+
+#define FMC_BTR3_DATAST 0x0000FF00U /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FMC_BTR3_DATAST_0 0x00000100U /*!<Bit 0 */
+#define FMC_BTR3_DATAST_1 0x00000200U /*!<Bit 1 */
+#define FMC_BTR3_DATAST_2 0x00000400U /*!<Bit 2 */
+#define FMC_BTR3_DATAST_3 0x00000800U /*!<Bit 3 */
+#define FMC_BTR3_DATAST_4 0x00001000U /*!<Bit 4 */
+#define FMC_BTR3_DATAST_5 0x00002000U /*!<Bit 5 */
+#define FMC_BTR3_DATAST_6 0x00004000U /*!<Bit 6 */
+#define FMC_BTR3_DATAST_7 0x00008000U /*!<Bit 7 */
+
+#define FMC_BTR3_BUSTURN 0x000F0000U /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define FMC_BTR3_BUSTURN_0 0x00010000U /*!<Bit 0 */
+#define FMC_BTR3_BUSTURN_1 0x00020000U /*!<Bit 1 */
+#define FMC_BTR3_BUSTURN_2 0x00040000U /*!<Bit 2 */
+#define FMC_BTR3_BUSTURN_3 0x00080000U /*!<Bit 3 */
+
+#define FMC_BTR3_CLKDIV 0x00F00000U /*!<CLKDIV[3:0] bits (Clock divide ratio) */
+#define FMC_BTR3_CLKDIV_0 0x00100000U /*!<Bit 0 */
+#define FMC_BTR3_CLKDIV_1 0x00200000U /*!<Bit 1 */
+#define FMC_BTR3_CLKDIV_2 0x00400000U /*!<Bit 2 */
+#define FMC_BTR3_CLKDIV_3 0x00800000U /*!<Bit 3 */
+
+#define FMC_BTR3_DATLAT 0x0F000000U /*!<DATLA[3:0] bits (Data latency) */
+#define FMC_BTR3_DATLAT_0 0x01000000U /*!<Bit 0 */
+#define FMC_BTR3_DATLAT_1 0x02000000U /*!<Bit 1 */
+#define FMC_BTR3_DATLAT_2 0x04000000U /*!<Bit 2 */
+#define FMC_BTR3_DATLAT_3 0x08000000U /*!<Bit 3 */
+
+#define FMC_BTR3_ACCMOD 0x30000000U /*!<ACCMOD[1:0] bits (Access mode) */
+#define FMC_BTR3_ACCMOD_0 0x10000000U /*!<Bit 0 */
+#define FMC_BTR3_ACCMOD_1 0x20000000U /*!<Bit 1 */
+
+/****************** Bit definition for FMC_BTR4 register *******************/
+#define FMC_BTR4_ADDSET 0x0000000FU /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FMC_BTR4_ADDSET_0 0x00000001U /*!<Bit 0 */
+#define FMC_BTR4_ADDSET_1 0x00000002U /*!<Bit 1 */
+#define FMC_BTR4_ADDSET_2 0x00000004U /*!<Bit 2 */
+#define FMC_BTR4_ADDSET_3 0x00000008U /*!<Bit 3 */
+
+#define FMC_BTR4_ADDHLD 0x000000F0U /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FMC_BTR4_ADDHLD_0 0x00000010U /*!<Bit 0 */
+#define FMC_BTR4_ADDHLD_1 0x00000020U /*!<Bit 1 */
+#define FMC_BTR4_ADDHLD_2 0x00000040U /*!<Bit 2 */
+#define FMC_BTR4_ADDHLD_3 0x00000080U /*!<Bit 3 */
+
+#define FMC_BTR4_DATAST 0x0000FF00U /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FMC_BTR4_DATAST_0 0x00000100U /*!<Bit 0 */
+#define FMC_BTR4_DATAST_1 0x00000200U /*!<Bit 1 */
+#define FMC_BTR4_DATAST_2 0x00000400U /*!<Bit 2 */
+#define FMC_BTR4_DATAST_3 0x00000800U /*!<Bit 3 */
+#define FMC_BTR4_DATAST_4 0x00001000U /*!<Bit 4 */
+#define FMC_BTR4_DATAST_5 0x00002000U /*!<Bit 5 */
+#define FMC_BTR4_DATAST_6 0x00004000U /*!<Bit 6 */
+#define FMC_BTR4_DATAST_7 0x00008000U /*!<Bit 7 */
+
+#define FMC_BTR4_BUSTURN 0x000F0000U /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define FMC_BTR4_BUSTURN_0 0x00010000U /*!<Bit 0 */
+#define FMC_BTR4_BUSTURN_1 0x00020000U /*!<Bit 1 */
+#define FMC_BTR4_BUSTURN_2 0x00040000U /*!<Bit 2 */
+#define FMC_BTR4_BUSTURN_3 0x00080000U /*!<Bit 3 */
+
+#define FMC_BTR4_CLKDIV 0x00F00000U /*!<CLKDIV[3:0] bits (Clock divide ratio) */
+#define FMC_BTR4_CLKDIV_0 0x00100000U /*!<Bit 0 */
+#define FMC_BTR4_CLKDIV_1 0x00200000U /*!<Bit 1 */
+#define FMC_BTR4_CLKDIV_2 0x00400000U /*!<Bit 2 */
+#define FMC_BTR4_CLKDIV_3 0x00800000U /*!<Bit 3 */
+
+#define FMC_BTR4_DATLAT 0x0F000000U /*!<DATLA[3:0] bits (Data latency) */
+#define FMC_BTR4_DATLAT_0 0x01000000U /*!<Bit 0 */
+#define FMC_BTR4_DATLAT_1 0x02000000U /*!<Bit 1 */
+#define FMC_BTR4_DATLAT_2 0x04000000U /*!<Bit 2 */
+#define FMC_BTR4_DATLAT_3 0x08000000U /*!<Bit 3 */
+
+#define FMC_BTR4_ACCMOD 0x30000000U /*!<ACCMOD[1:0] bits (Access mode) */
+#define FMC_BTR4_ACCMOD_0 0x10000000U /*!<Bit 0 */
+#define FMC_BTR4_ACCMOD_1 0x20000000U /*!<Bit 1 */
+
+/****************** Bit definition for FMC_BWTR1 register ******************/
+#define FMC_BWTR1_ADDSET 0x0000000FU /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FMC_BWTR1_ADDSET_0 0x00000001U /*!<Bit 0 */
+#define FMC_BWTR1_ADDSET_1 0x00000002U /*!<Bit 1 */
+#define FMC_BWTR1_ADDSET_2 0x00000004U /*!<Bit 2 */
+#define FMC_BWTR1_ADDSET_3 0x00000008U /*!<Bit 3 */
+
+#define FMC_BWTR1_ADDHLD 0x000000F0U /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FMC_BWTR1_ADDHLD_0 0x00000010U /*!<Bit 0 */
+#define FMC_BWTR1_ADDHLD_1 0x00000020U /*!<Bit 1 */
+#define FMC_BWTR1_ADDHLD_2 0x00000040U /*!<Bit 2 */
+#define FMC_BWTR1_ADDHLD_3 0x00000080U /*!<Bit 3 */
+
+#define FMC_BWTR1_DATAST 0x0000FF00U /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FMC_BWTR1_DATAST_0 0x00000100U /*!<Bit 0 */
+#define FMC_BWTR1_DATAST_1 0x00000200U /*!<Bit 1 */
+#define FMC_BWTR1_DATAST_2 0x00000400U /*!<Bit 2 */
+#define FMC_BWTR1_DATAST_3 0x00000800U /*!<Bit 3 */
+#define FMC_BWTR1_DATAST_4 0x00001000U /*!<Bit 4 */
+#define FMC_BWTR1_DATAST_5 0x00002000U /*!<Bit 5 */
+#define FMC_BWTR1_DATAST_6 0x00004000U /*!<Bit 6 */
+#define FMC_BWTR1_DATAST_7 0x00008000U /*!<Bit 7 */
+
+#define FMC_BWTR1_BUSTURN 0x000F0000U /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
+#define FMC_BWTR1_BUSTURN_0 0x00010000U /*!<Bit 0 */
+#define FMC_BWTR1_BUSTURN_1 0x00020000U /*!<Bit 1 */
+#define FMC_BWTR1_BUSTURN_2 0x00040000U /*!<Bit 2 */
+#define FMC_BWTR1_BUSTURN_3 0x00080000U /*!<Bit 3 */
+
+#define FMC_BWTR1_ACCMOD 0x30000000U /*!<ACCMOD[1:0] bits (Access mode) */
+#define FMC_BWTR1_ACCMOD_0 0x10000000U /*!<Bit 0 */
+#define FMC_BWTR1_ACCMOD_1 0x20000000U /*!<Bit 1 */
+
+/****************** Bit definition for FMC_BWTR2 register ******************/
+#define FMC_BWTR2_ADDSET 0x0000000FU /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FMC_BWTR2_ADDSET_0 0x00000001U /*!<Bit 0 */
+#define FMC_BWTR2_ADDSET_1 0x00000002U /*!<Bit 1 */
+#define FMC_BWTR2_ADDSET_2 0x00000004U /*!<Bit 2 */
+#define FMC_BWTR2_ADDSET_3 0x00000008U /*!<Bit 3 */
+
+#define FMC_BWTR2_ADDHLD 0x000000F0U /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FMC_BWTR2_ADDHLD_0 0x00000010U /*!<Bit 0 */
+#define FMC_BWTR2_ADDHLD_1 0x00000020U /*!<Bit 1 */
+#define FMC_BWTR2_ADDHLD_2 0x00000040U /*!<Bit 2 */
+#define FMC_BWTR2_ADDHLD_3 0x00000080U /*!<Bit 3 */
+
+#define FMC_BWTR2_DATAST 0x0000FF00U /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FMC_BWTR2_DATAST_0 0x00000100U /*!<Bit 0 */
+#define FMC_BWTR2_DATAST_1 0x00000200U /*!<Bit 1 */
+#define FMC_BWTR2_DATAST_2 0x00000400U /*!<Bit 2 */
+#define FMC_BWTR2_DATAST_3 0x00000800U /*!<Bit 3 */
+#define FMC_BWTR2_DATAST_4 0x00001000U /*!<Bit 4 */
+#define FMC_BWTR2_DATAST_5 0x00002000U /*!<Bit 5 */
+#define FMC_BWTR2_DATAST_6 0x00004000U /*!<Bit 6 */
+#define FMC_BWTR2_DATAST_7 0x00008000U /*!<Bit 7 */
+
+#define FMC_BWTR2_BUSTURN 0x000F0000U /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
+#define FMC_BWTR2_BUSTURN_0 0x00010000U /*!<Bit 0 */
+#define FMC_BWTR2_BUSTURN_1 0x00020000U /*!<Bit 1 */
+#define FMC_BWTR2_BUSTURN_2 0x00040000U /*!<Bit 2 */
+#define FMC_BWTR2_BUSTURN_3 0x00080000U /*!<Bit 3 */
+
+#define FMC_BWTR2_ACCMOD 0x30000000U /*!<ACCMOD[1:0] bits (Access mode) */
+#define FMC_BWTR2_ACCMOD_0 0x10000000U /*!<Bit 0 */
+#define FMC_BWTR2_ACCMOD_1 0x20000000U /*!<Bit 1 */
+
+/****************** Bit definition for FMC_BWTR3 register ******************/
+#define FMC_BWTR3_ADDSET 0x0000000FU /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FMC_BWTR3_ADDSET_0 0x00000001U /*!<Bit 0 */
+#define FMC_BWTR3_ADDSET_1 0x00000002U /*!<Bit 1 */
+#define FMC_BWTR3_ADDSET_2 0x00000004U /*!<Bit 2 */
+#define FMC_BWTR3_ADDSET_3 0x00000008U /*!<Bit 3 */
+
+#define FMC_BWTR3_ADDHLD 0x000000F0U /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FMC_BWTR3_ADDHLD_0 0x00000010U /*!<Bit 0 */
+#define FMC_BWTR3_ADDHLD_1 0x00000020U /*!<Bit 1 */
+#define FMC_BWTR3_ADDHLD_2 0x00000040U /*!<Bit 2 */
+#define FMC_BWTR3_ADDHLD_3 0x00000080U /*!<Bit 3 */
+
+#define FMC_BWTR3_DATAST 0x0000FF00U /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FMC_BWTR3_DATAST_0 0x00000100U /*!<Bit 0 */
+#define FMC_BWTR3_DATAST_1 0x00000200U /*!<Bit 1 */
+#define FMC_BWTR3_DATAST_2 0x00000400U /*!<Bit 2 */
+#define FMC_BWTR3_DATAST_3 0x00000800U /*!<Bit 3 */
+#define FMC_BWTR3_DATAST_4 0x00001000U /*!<Bit 4 */
+#define FMC_BWTR3_DATAST_5 0x00002000U /*!<Bit 5 */
+#define FMC_BWTR3_DATAST_6 0x00004000U /*!<Bit 6 */
+#define FMC_BWTR3_DATAST_7 0x00008000U /*!<Bit 7 */
+
+#define FMC_BWTR3_BUSTURN 0x000F0000U /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
+#define FMC_BWTR3_BUSTURN_0 0x00010000U /*!<Bit 0 */
+#define FMC_BWTR3_BUSTURN_1 0x00020000U /*!<Bit 1 */
+#define FMC_BWTR3_BUSTURN_2 0x00040000U /*!<Bit 2 */
+#define FMC_BWTR3_BUSTURN_3 0x00080000U /*!<Bit 3 */
+
+#define FMC_BWTR3_ACCMOD 0x30000000U /*!<ACCMOD[1:0] bits (Access mode) */
+#define FMC_BWTR3_ACCMOD_0 0x10000000U /*!<Bit 0 */
+#define FMC_BWTR3_ACCMOD_1 0x20000000U /*!<Bit 1 */
+
+/****************** Bit definition for FMC_BWTR4 register ******************/
+#define FMC_BWTR4_ADDSET 0x0000000FU /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FMC_BWTR4_ADDSET_0 0x00000001U /*!<Bit 0 */
+#define FMC_BWTR4_ADDSET_1 0x00000002U /*!<Bit 1 */
+#define FMC_BWTR4_ADDSET_2 0x00000004U /*!<Bit 2 */
+#define FMC_BWTR4_ADDSET_3 0x00000008U /*!<Bit 3 */
+
+#define FMC_BWTR4_ADDHLD 0x000000F0U /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FMC_BWTR4_ADDHLD_0 0x00000010U /*!<Bit 0 */
+#define FMC_BWTR4_ADDHLD_1 0x00000020U /*!<Bit 1 */
+#define FMC_BWTR4_ADDHLD_2 0x00000040U /*!<Bit 2 */
+#define FMC_BWTR4_ADDHLD_3 0x00000080U /*!<Bit 3 */
+
+#define FMC_BWTR4_DATAST 0x0000FF00U /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FMC_BWTR4_DATAST_0 0x00000100U /*!<Bit 0 */
+#define FMC_BWTR4_DATAST_1 0x00000200U /*!<Bit 1 */
+#define FMC_BWTR4_DATAST_2 0x00000400U /*!<Bit 2 */
+#define FMC_BWTR4_DATAST_3 0x00000800U /*!<Bit 3 */
+#define FMC_BWTR4_DATAST_4 0x00001000U /*!<Bit 4 */
+#define FMC_BWTR4_DATAST_5 0x00002000U /*!<Bit 5 */
+#define FMC_BWTR4_DATAST_6 0x00004000U /*!<Bit 6 */
+#define FMC_BWTR4_DATAST_7 0x00008000U /*!<Bit 7 */
+
+#define FMC_BWTR4_BUSTURN 0x000F0000U /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
+#define FMC_BWTR4_BUSTURN_0 0x00010000U /*!<Bit 0 */
+#define FMC_BWTR4_BUSTURN_1 0x00020000U /*!<Bit 1 */
+#define FMC_BWTR4_BUSTURN_2 0x00040000U /*!<Bit 2 */
+#define FMC_BWTR4_BUSTURN_3 0x00080000U /*!<Bit 3 */
+
+#define FMC_BWTR4_ACCMOD 0x30000000U /*!<ACCMOD[1:0] bits (Access mode) */
+#define FMC_BWTR4_ACCMOD_0 0x10000000U /*!<Bit 0 */
+#define FMC_BWTR4_ACCMOD_1 0x20000000U /*!<Bit 1 */
+
+/****************** Bit definition for FMC_PCR2 register *******************/
+#define FMC_PCR2_PWAITEN 0x00000002U /*!<Wait feature enable bit */
+#define FMC_PCR2_PBKEN 0x00000004U /*!<PC Card/NAND Flash memory bank enable bit */
+#define FMC_PCR2_PTYP 0x00000008U /*!<Memory type */
+
+#define FMC_PCR2_PWID 0x00000030U /*!<PWID[1:0] bits (NAND Flash databus width) */
+#define FMC_PCR2_PWID_0 0x00000010U /*!<Bit 0 */
+#define FMC_PCR2_PWID_1 0x00000020U /*!<Bit 1 */
+
+#define FMC_PCR2_ECCEN 0x00000040U /*!<ECC computation logic enable bit */
+
+#define FMC_PCR2_TCLR 0x00001E00U /*!<TCLR[3:0] bits (CLE to RE delay) */
+#define FMC_PCR2_TCLR_0 0x00000200U /*!<Bit 0 */
+#define FMC_PCR2_TCLR_1 0x00000400U /*!<Bit 1 */
+#define FMC_PCR2_TCLR_2 0x00000800U /*!<Bit 2 */
+#define FMC_PCR2_TCLR_3 0x00001000U /*!<Bit 3 */
+
+#define FMC_PCR2_TAR 0x0001E000U /*!<TAR[3:0] bits (ALE to RE delay) */
+#define FMC_PCR2_TAR_0 0x00002000U /*!<Bit 0 */
+#define FMC_PCR2_TAR_1 0x00004000U /*!<Bit 1 */
+#define FMC_PCR2_TAR_2 0x00008000U /*!<Bit 2 */
+#define FMC_PCR2_TAR_3 0x00010000U /*!<Bit 3 */
+
+#define FMC_PCR2_ECCPS 0x000E0000U /*!<ECCPS[1:0] bits (ECC page size) */
+#define FMC_PCR2_ECCPS_0 0x00020000U /*!<Bit 0 */
+#define FMC_PCR2_ECCPS_1 0x00040000U /*!<Bit 1 */
+#define FMC_PCR2_ECCPS_2 0x00080000U /*!<Bit 2 */
+
+/****************** Bit definition for FMC_PCR3 register *******************/
+#define FMC_PCR3_PWAITEN 0x00000002U /*!<Wait feature enable bit */
+#define FMC_PCR3_PBKEN 0x00000004U /*!<PC Card/NAND Flash memory bank enable bit */
+#define FMC_PCR3_PTYP 0x00000008U /*!<Memory type */
+
+#define FMC_PCR3_PWID 0x00000030U /*!<PWID[1:0] bits (NAND Flash databus width) */
+#define FMC_PCR3_PWID_0 0x00000010U /*!<Bit 0 */
+#define FMC_PCR3_PWID_1 0x00000020U /*!<Bit 1 */
+
+#define FMC_PCR3_ECCEN 0x00000040U /*!<ECC computation logic enable bit */
+
+#define FMC_PCR3_TCLR 0x00001E00U /*!<TCLR[3:0] bits (CLE to RE delay) */
+#define FMC_PCR3_TCLR_0 0x00000200U /*!<Bit 0 */
+#define FMC_PCR3_TCLR_1 0x00000400U /*!<Bit 1 */
+#define FMC_PCR3_TCLR_2 0x00000800U /*!<Bit 2 */
+#define FMC_PCR3_TCLR_3 0x00001000U /*!<Bit 3 */
+
+#define FMC_PCR3_TAR 0x0001E000U /*!<TAR[3:0] bits (ALE to RE delay) */
+#define FMC_PCR3_TAR_0 0x00002000U /*!<Bit 0 */
+#define FMC_PCR3_TAR_1 0x00004000U /*!<Bit 1 */
+#define FMC_PCR3_TAR_2 0x00008000U /*!<Bit 2 */
+#define FMC_PCR3_TAR_3 0x00010000U /*!<Bit 3 */
+
+#define FMC_PCR3_ECCPS 0x000E0000U /*!<ECCPS[2:0] bits (ECC page size) */
+#define FMC_PCR3_ECCPS_0 0x00020000U /*!<Bit 0 */
+#define FMC_PCR3_ECCPS_1 0x00040000U /*!<Bit 1 */
+#define FMC_PCR3_ECCPS_2 0x00080000U /*!<Bit 2 */
+
+/****************** Bit definition for FMC_PCR4 register *******************/
+#define FMC_PCR4_PWAITEN 0x00000002U /*!<Wait feature enable bit */
+#define FMC_PCR4_PBKEN 0x00000004U /*!<PC Card/NAND Flash memory bank enable bit */
+#define FMC_PCR4_PTYP 0x00000008U /*!<Memory type */
+
+#define FMC_PCR4_PWID 0x00000030U /*!<PWID[1:0] bits (NAND Flash databus width) */
+#define FMC_PCR4_PWID_0 0x00000010U /*!<Bit 0 */
+#define FMC_PCR4_PWID_1 0x00000020U /*!<Bit 1 */
+
+#define FMC_PCR4_ECCEN 0x00000040U /*!<ECC computation logic enable bit */
+
+#define FMC_PCR4_TCLR 0x00001E00U /*!<TCLR[3:0] bits (CLE to RE delay) */
+#define FMC_PCR4_TCLR_0 0x00000200U /*!<Bit 0 */
+#define FMC_PCR4_TCLR_1 0x00000400U /*!<Bit 1 */
+#define FMC_PCR4_TCLR_2 0x00000800U /*!<Bit 2 */
+#define FMC_PCR4_TCLR_3 0x00001000U /*!<Bit 3 */
+
+#define FMC_PCR4_TAR 0x0001E000U /*!<TAR[3:0] bits (ALE to RE delay) */
+#define FMC_PCR4_TAR_0 0x00002000U /*!<Bit 0 */
+#define FMC_PCR4_TAR_1 0x00004000U /*!<Bit 1 */
+#define FMC_PCR4_TAR_2 0x00008000U /*!<Bit 2 */
+#define FMC_PCR4_TAR_3 0x00010000U /*!<Bit 3 */
+
+#define FMC_PCR4_ECCPS 0x000E0000U /*!<ECCPS[2:0] bits (ECC page size) */
+#define FMC_PCR4_ECCPS_0 0x00020000U /*!<Bit 0 */
+#define FMC_PCR4_ECCPS_1 0x00040000U /*!<Bit 1 */
+#define FMC_PCR4_ECCPS_2 0x00080000U /*!<Bit 2 */
+
+/******************* Bit definition for FMC_SR2 register *******************/
+#define FMC_SR2_IRS 0x01U /*!<Interrupt Rising Edge status */
+#define FMC_SR2_ILS 0x02U /*!<Interrupt Level status */
+#define FMC_SR2_IFS 0x04U /*!<Interrupt Falling Edge status */
+#define FMC_SR2_IREN 0x08U /*!<Interrupt Rising Edge detection Enable bit */
+#define FMC_SR2_ILEN 0x10U /*!<Interrupt Level detection Enable bit */
+#define FMC_SR2_IFEN 0x20U /*!<Interrupt Falling Edge detection Enable bit */
+#define FMC_SR2_FEMPT 0x40U /*!<FIFO empty */
+
+/******************* Bit definition for FMC_SR3 register *******************/
+#define FMC_SR3_IRS 0x01U /*!<Interrupt Rising Edge status */
+#define FMC_SR3_ILS 0x02U /*!<Interrupt Level status */
+#define FMC_SR3_IFS 0x04U /*!<Interrupt Falling Edge status */
+#define FMC_SR3_IREN 0x08U /*!<Interrupt Rising Edge detection Enable bit */
+#define FMC_SR3_ILEN 0x10U /*!<Interrupt Level detection Enable bit */
+#define FMC_SR3_IFEN 0x20U /*!<Interrupt Falling Edge detection Enable bit */
+#define FMC_SR3_FEMPT 0x40U /*!<FIFO empty */
+
+/******************* Bit definition for FMC_SR4 register *******************/
+#define FMC_SR4_IRS 0x01U /*!<Interrupt Rising Edge status */
+#define FMC_SR4_ILS 0x02U /*!<Interrupt Level status */
+#define FMC_SR4_IFS 0x04U /*!<Interrupt Falling Edge status */
+#define FMC_SR4_IREN 0x08U /*!<Interrupt Rising Edge detection Enable bit */
+#define FMC_SR4_ILEN 0x10U /*!<Interrupt Level detection Enable bit */
+#define FMC_SR4_IFEN 0x20U /*!<Interrupt Falling Edge detection Enable bit */
+#define FMC_SR4_FEMPT 0x40U /*!<FIFO empty */
+
+/****************** Bit definition for FMC_PMEM2 register ******************/
+#define FMC_PMEM2_MEMSET2 0x000000FFU /*!<MEMSET2[7:0] bits (Common memory 2 setup time) */
+#define FMC_PMEM2_MEMSET2_0 0x00000001U /*!<Bit 0 */
+#define FMC_PMEM2_MEMSET2_1 0x00000002U /*!<Bit 1 */
+#define FMC_PMEM2_MEMSET2_2 0x00000004U /*!<Bit 2 */
+#define FMC_PMEM2_MEMSET2_3 0x00000008U /*!<Bit 3 */
+#define FMC_PMEM2_MEMSET2_4 0x00000010U /*!<Bit 4 */
+#define FMC_PMEM2_MEMSET2_5 0x00000020U /*!<Bit 5 */
+#define FMC_PMEM2_MEMSET2_6 0x00000040U /*!<Bit 6 */
+#define FMC_PMEM2_MEMSET2_7 0x00000080U /*!<Bit 7 */
+
+#define FMC_PMEM2_MEMWAIT2 0x0000FF00U /*!<MEMWAIT2[7:0] bits (Common memory 2 wait time) */
+#define FMC_PMEM2_MEMWAIT2_0 0x00000100U /*!<Bit 0 */
+#define FMC_PMEM2_MEMWAIT2_1 0x00000200U /*!<Bit 1 */
+#define FMC_PMEM2_MEMWAIT2_2 0x00000400U /*!<Bit 2 */
+#define FMC_PMEM2_MEMWAIT2_3 0x00000800U /*!<Bit 3 */
+#define FMC_PMEM2_MEMWAIT2_4 0x00001000U /*!<Bit 4 */
+#define FMC_PMEM2_MEMWAIT2_5 0x00002000U /*!<Bit 5 */
+#define FMC_PMEM2_MEMWAIT2_6 0x00004000U /*!<Bit 6 */
+#define FMC_PMEM2_MEMWAIT2_7 0x00008000U /*!<Bit 7 */
+
+#define FMC_PMEM2_MEMHOLD2 0x00FF0000U /*!<MEMHOLD2[7:0] bits (Common memory 2 hold time) */
+#define FMC_PMEM2_MEMHOLD2_0 0x00010000U /*!<Bit 0 */
+#define FMC_PMEM2_MEMHOLD2_1 0x00020000U /*!<Bit 1 */
+#define FMC_PMEM2_MEMHOLD2_2 0x00040000U /*!<Bit 2 */
+#define FMC_PMEM2_MEMHOLD2_3 0x00080000U /*!<Bit 3 */
+#define FMC_PMEM2_MEMHOLD2_4 0x00100000U /*!<Bit 4 */
+#define FMC_PMEM2_MEMHOLD2_5 0x00200000U /*!<Bit 5 */
+#define FMC_PMEM2_MEMHOLD2_6 0x00400000U /*!<Bit 6 */
+#define FMC_PMEM2_MEMHOLD2_7 0x00800000U /*!<Bit 7 */
+
+#define FMC_PMEM2_MEMHIZ2 0xFF000000U /*!<MEMHIZ2[7:0] bits (Common memory 2 databus HiZ time) */
+#define FMC_PMEM2_MEMHIZ2_0 0x01000000U /*!<Bit 0 */
+#define FMC_PMEM2_MEMHIZ2_1 0x02000000U /*!<Bit 1 */
+#define FMC_PMEM2_MEMHIZ2_2 0x04000000U /*!<Bit 2 */
+#define FMC_PMEM2_MEMHIZ2_3 0x08000000U /*!<Bit 3 */
+#define FMC_PMEM2_MEMHIZ2_4 0x10000000U /*!<Bit 4 */
+#define FMC_PMEM2_MEMHIZ2_5 0x20000000U /*!<Bit 5 */
+#define FMC_PMEM2_MEMHIZ2_6 0x40000000U /*!<Bit 6 */
+#define FMC_PMEM2_MEMHIZ2_7 0x80000000U /*!<Bit 7 */
+
+/****************** Bit definition for FMC_PMEM3 register ******************/
+#define FMC_PMEM3_MEMSET3 0x000000FFU /*!<MEMSET3[7:0] bits (Common memory 3 setup time) */
+#define FMC_PMEM3_MEMSET3_0 0x00000001U /*!<Bit 0 */
+#define FMC_PMEM3_MEMSET3_1 0x00000002U /*!<Bit 1 */
+#define FMC_PMEM3_MEMSET3_2 0x00000004U /*!<Bit 2 */
+#define FMC_PMEM3_MEMSET3_3 0x00000008U /*!<Bit 3 */
+#define FMC_PMEM3_MEMSET3_4 0x00000010U /*!<Bit 4 */
+#define FMC_PMEM3_MEMSET3_5 0x00000020U /*!<Bit 5 */
+#define FMC_PMEM3_MEMSET3_6 0x00000040U /*!<Bit 6 */
+#define FMC_PMEM3_MEMSET3_7 0x00000080U /*!<Bit 7 */
+
+#define FMC_PMEM3_MEMWAIT3 0x0000FF00U /*!<MEMWAIT3[7:0] bits (Common memory 3 wait time) */
+#define FMC_PMEM3_MEMWAIT3_0 0x00000100U /*!<Bit 0 */
+#define FMC_PMEM3_MEMWAIT3_1 0x00000200U /*!<Bit 1 */
+#define FMC_PMEM3_MEMWAIT3_2 0x00000400U /*!<Bit 2 */
+#define FMC_PMEM3_MEMWAIT3_3 0x00000800U /*!<Bit 3 */
+#define FMC_PMEM3_MEMWAIT3_4 0x00001000U /*!<Bit 4 */
+#define FMC_PMEM3_MEMWAIT3_5 0x00002000U /*!<Bit 5 */
+#define FMC_PMEM3_MEMWAIT3_6 0x00004000U /*!<Bit 6 */
+#define FMC_PMEM3_MEMWAIT3_7 0x00008000U /*!<Bit 7 */
+
+#define FMC_PMEM3_MEMHOLD3 0x00FF0000U /*!<MEMHOLD3[7:0] bits (Common memory 3 hold time) */
+#define FMC_PMEM3_MEMHOLD3_0 0x00010000U /*!<Bit 0 */
+#define FMC_PMEM3_MEMHOLD3_1 0x00020000U /*!<Bit 1 */
+#define FMC_PMEM3_MEMHOLD3_2 0x00040000U /*!<Bit 2 */
+#define FMC_PMEM3_MEMHOLD3_3 0x00080000U /*!<Bit 3 */
+#define FMC_PMEM3_MEMHOLD3_4 0x00100000U /*!<Bit 4 */
+#define FMC_PMEM3_MEMHOLD3_5 0x00200000U /*!<Bit 5 */
+#define FMC_PMEM3_MEMHOLD3_6 0x00400000U /*!<Bit 6 */
+#define FMC_PMEM3_MEMHOLD3_7 0x00800000U /*!<Bit 7 */
+
+#define FMC_PMEM3_MEMHIZ3 0xFF000000U /*!<MEMHIZ3[7:0] bits (Common memory 3 databus HiZ time) */
+#define FMC_PMEM3_MEMHIZ3_0 0x01000000U /*!<Bit 0 */
+#define FMC_PMEM3_MEMHIZ3_1 0x02000000U /*!<Bit 1 */
+#define FMC_PMEM3_MEMHIZ3_2 0x04000000U /*!<Bit 2 */
+#define FMC_PMEM3_MEMHIZ3_3 0x08000000U /*!<Bit 3 */
+#define FMC_PMEM3_MEMHIZ3_4 0x10000000U /*!<Bit 4 */
+#define FMC_PMEM3_MEMHIZ3_5 0x20000000U /*!<Bit 5 */
+#define FMC_PMEM3_MEMHIZ3_6 0x40000000U /*!<Bit 6 */
+#define FMC_PMEM3_MEMHIZ3_7 0x80000000U /*!<Bit 7 */
+
+/****************** Bit definition for FMC_PMEM4 register ******************/
+#define FMC_PMEM4_MEMSET4 0x000000FFU /*!<MEMSET4[7:0] bits (Common memory 4 setup time) */
+#define FMC_PMEM4_MEMSET4_0 0x00000001U /*!<Bit 0 */
+#define FMC_PMEM4_MEMSET4_1 0x00000002U /*!<Bit 1 */
+#define FMC_PMEM4_MEMSET4_2 0x00000004U /*!<Bit 2 */
+#define FMC_PMEM4_MEMSET4_3 0x00000008U /*!<Bit 3 */
+#define FMC_PMEM4_MEMSET4_4 0x00000010U /*!<Bit 4 */
+#define FMC_PMEM4_MEMSET4_5 0x00000020U /*!<Bit 5 */
+#define FMC_PMEM4_MEMSET4_6 0x00000040U /*!<Bit 6 */
+#define FMC_PMEM4_MEMSET4_7 0x00000080U /*!<Bit 7 */
+
+#define FMC_PMEM4_MEMWAIT4 0x0000FF00U /*!<MEMWAIT4[7:0] bits (Common memory 4 wait time) */
+#define FMC_PMEM4_MEMWAIT4_0 0x00000100U /*!<Bit 0 */
+#define FMC_PMEM4_MEMWAIT4_1 0x00000200U /*!<Bit 1 */
+#define FMC_PMEM4_MEMWAIT4_2 0x00000400U /*!<Bit 2 */
+#define FMC_PMEM4_MEMWAIT4_3 0x00000800U /*!<Bit 3 */
+#define FMC_PMEM4_MEMWAIT4_4 0x00001000U /*!<Bit 4 */
+#define FMC_PMEM4_MEMWAIT4_5 0x00002000U /*!<Bit 5 */
+#define FMC_PMEM4_MEMWAIT4_6 0x00004000U /*!<Bit 6 */
+#define FMC_PMEM4_MEMWAIT4_7 0x00008000U /*!<Bit 7 */
+
+#define FMC_PMEM4_MEMHOLD4 0x00FF0000U /*!<MEMHOLD4[7:0] bits (Common memory 4 hold time) */
+#define FMC_PMEM4_MEMHOLD4_0 0x00010000U /*!<Bit 0 */
+#define FMC_PMEM4_MEMHOLD4_1 0x00020000U /*!<Bit 1 */
+#define FMC_PMEM4_MEMHOLD4_2 0x00040000U /*!<Bit 2 */
+#define FMC_PMEM4_MEMHOLD4_3 0x00080000U /*!<Bit 3 */
+#define FMC_PMEM4_MEMHOLD4_4 0x00100000U /*!<Bit 4 */
+#define FMC_PMEM4_MEMHOLD4_5 0x00200000U /*!<Bit 5 */
+#define FMC_PMEM4_MEMHOLD4_6 0x00400000U /*!<Bit 6 */
+#define FMC_PMEM4_MEMHOLD4_7 0x00800000U /*!<Bit 7 */
+
+#define FMC_PMEM4_MEMHIZ4 0xFF000000U /*!<MEMHIZ4[7:0] bits (Common memory 4 databus HiZ time) */
+#define FMC_PMEM4_MEMHIZ4_0 0x01000000U /*!<Bit 0 */
+#define FMC_PMEM4_MEMHIZ4_1 0x02000000U /*!<Bit 1 */
+#define FMC_PMEM4_MEMHIZ4_2 0x04000000U /*!<Bit 2 */
+#define FMC_PMEM4_MEMHIZ4_3 0x08000000U /*!<Bit 3 */
+#define FMC_PMEM4_MEMHIZ4_4 0x10000000U /*!<Bit 4 */
+#define FMC_PMEM4_MEMHIZ4_5 0x20000000U /*!<Bit 5 */
+#define FMC_PMEM4_MEMHIZ4_6 0x40000000U /*!<Bit 6 */
+#define FMC_PMEM4_MEMHIZ4_7 0x80000000U /*!<Bit 7 */
+
+/****************** Bit definition for FMC_PATT2 register ******************/
+#define FMC_PATT2_ATTSET2 0x000000FFU /*!<ATTSET2[7:0] bits (Attribute memory 2 setup time) */
+#define FMC_PATT2_ATTSET2_0 0x00000001U /*!<Bit 0 */
+#define FMC_PATT2_ATTSET2_1 0x00000002U /*!<Bit 1 */
+#define FMC_PATT2_ATTSET2_2 0x00000004U /*!<Bit 2 */
+#define FMC_PATT2_ATTSET2_3 0x00000008U /*!<Bit 3 */
+#define FMC_PATT2_ATTSET2_4 0x00000010U /*!<Bit 4 */
+#define FMC_PATT2_ATTSET2_5 0x00000020U /*!<Bit 5 */
+#define FMC_PATT2_ATTSET2_6 0x00000040U /*!<Bit 6 */
+#define FMC_PATT2_ATTSET2_7 0x00000080U /*!<Bit 7 */
+
+#define FMC_PATT2_ATTWAIT2 0x0000FF00U /*!<ATTWAIT2[7:0] bits (Attribute memory 2 wait time) */
+#define FMC_PATT2_ATTWAIT2_0 0x00000100U /*!<Bit 0 */
+#define FMC_PATT2_ATTWAIT2_1 0x00000200U /*!<Bit 1 */
+#define FMC_PATT2_ATTWAIT2_2 0x00000400U /*!<Bit 2 */
+#define FMC_PATT2_ATTWAIT2_3 0x00000800U /*!<Bit 3 */
+#define FMC_PATT2_ATTWAIT2_4 0x00001000U /*!<Bit 4 */
+#define FMC_PATT2_ATTWAIT2_5 0x00002000U /*!<Bit 5 */
+#define FMC_PATT2_ATTWAIT2_6 0x00004000U /*!<Bit 6 */
+#define FMC_PATT2_ATTWAIT2_7 0x00008000U /*!<Bit 7 */
+
+#define FMC_PATT2_ATTHOLD2 0x00FF0000U /*!<ATTHOLD2[7:0] bits (Attribute memory 2 hold time) */
+#define FMC_PATT2_ATTHOLD2_0 0x00010000U /*!<Bit 0 */
+#define FMC_PATT2_ATTHOLD2_1 0x00020000U /*!<Bit 1 */
+#define FMC_PATT2_ATTHOLD2_2 0x00040000U /*!<Bit 2 */
+#define FMC_PATT2_ATTHOLD2_3 0x00080000U /*!<Bit 3 */
+#define FMC_PATT2_ATTHOLD2_4 0x00100000U /*!<Bit 4 */
+#define FMC_PATT2_ATTHOLD2_5 0x00200000U /*!<Bit 5 */
+#define FMC_PATT2_ATTHOLD2_6 0x00400000U /*!<Bit 6 */
+#define FMC_PATT2_ATTHOLD2_7 0x00800000U /*!<Bit 7 */
+
+#define FMC_PATT2_ATTHIZ2 0xFF000000U /*!<ATTHIZ2[7:0] bits (Attribute memory 2 databus HiZ time) */
+#define FMC_PATT2_ATTHIZ2_0 0x01000000U /*!<Bit 0 */
+#define FMC_PATT2_ATTHIZ2_1 0x02000000U /*!<Bit 1 */
+#define FMC_PATT2_ATTHIZ2_2 0x04000000U /*!<Bit 2 */
+#define FMC_PATT2_ATTHIZ2_3 0x08000000U /*!<Bit 3 */
+#define FMC_PATT2_ATTHIZ2_4 0x10000000U /*!<Bit 4 */
+#define FMC_PATT2_ATTHIZ2_5 0x20000000U /*!<Bit 5 */
+#define FMC_PATT2_ATTHIZ2_6 0x40000000U /*!<Bit 6 */
+#define FMC_PATT2_ATTHIZ2_7 0x80000000U /*!<Bit 7 */
+
+/****************** Bit definition for FMC_PATT3 register ******************/
+#define FMC_PATT3_ATTSET3 0x000000FFU /*!<ATTSET3[7:0] bits (Attribute memory 3 setup time) */
+#define FMC_PATT3_ATTSET3_0 0x00000001U /*!<Bit 0 */
+#define FMC_PATT3_ATTSET3_1 0x00000002U /*!<Bit 1 */
+#define FMC_PATT3_ATTSET3_2 0x00000004U /*!<Bit 2 */
+#define FMC_PATT3_ATTSET3_3 0x00000008U /*!<Bit 3 */
+#define FMC_PATT3_ATTSET3_4 0x00000010U /*!<Bit 4 */
+#define FMC_PATT3_ATTSET3_5 0x00000020U /*!<Bit 5 */
+#define FMC_PATT3_ATTSET3_6 0x00000040U /*!<Bit 6 */
+#define FMC_PATT3_ATTSET3_7 0x00000080U /*!<Bit 7 */
+
+#define FMC_PATT3_ATTWAIT3 0x0000FF00U /*!<ATTWAIT3[7:0] bits (Attribute memory 3 wait time) */
+#define FMC_PATT3_ATTWAIT3_0 0x00000100U /*!<Bit 0 */
+#define FMC_PATT3_ATTWAIT3_1 0x00000200U /*!<Bit 1 */
+#define FMC_PATT3_ATTWAIT3_2 0x00000400U /*!<Bit 2 */
+#define FMC_PATT3_ATTWAIT3_3 0x00000800U /*!<Bit 3 */
+#define FMC_PATT3_ATTWAIT3_4 0x00001000U /*!<Bit 4 */
+#define FMC_PATT3_ATTWAIT3_5 0x00002000U /*!<Bit 5 */
+#define FMC_PATT3_ATTWAIT3_6 0x00004000U /*!<Bit 6 */
+#define FMC_PATT3_ATTWAIT3_7 0x00008000U /*!<Bit 7 */
+
+#define FMC_PATT3_ATTHOLD3 0x00FF0000U /*!<ATTHOLD3[7:0] bits (Attribute memory 3 hold time) */
+#define FMC_PATT3_ATTHOLD3_0 0x00010000U /*!<Bit 0 */
+#define FMC_PATT3_ATTHOLD3_1 0x00020000U /*!<Bit 1 */
+#define FMC_PATT3_ATTHOLD3_2 0x00040000U /*!<Bit 2 */
+#define FMC_PATT3_ATTHOLD3_3 0x00080000U /*!<Bit 3 */
+#define FMC_PATT3_ATTHOLD3_4 0x00100000U /*!<Bit 4 */
+#define FMC_PATT3_ATTHOLD3_5 0x00200000U /*!<Bit 5 */
+#define FMC_PATT3_ATTHOLD3_6 0x00400000U /*!<Bit 6 */
+#define FMC_PATT3_ATTHOLD3_7 0x00800000U /*!<Bit 7 */
+
+#define FMC_PATT3_ATTHIZ3 0xFF000000U /*!<ATTHIZ3[7:0] bits (Attribute memory 3 databus HiZ time) */
+#define FMC_PATT3_ATTHIZ3_0 0x01000000U /*!<Bit 0 */
+#define FMC_PATT3_ATTHIZ3_1 0x02000000U /*!<Bit 1 */
+#define FMC_PATT3_ATTHIZ3_2 0x04000000U /*!<Bit 2 */
+#define FMC_PATT3_ATTHIZ3_3 0x08000000U /*!<Bit 3 */
+#define FMC_PATT3_ATTHIZ3_4 0x10000000U /*!<Bit 4 */
+#define FMC_PATT3_ATTHIZ3_5 0x20000000U /*!<Bit 5 */
+#define FMC_PATT3_ATTHIZ3_6 0x40000000U /*!<Bit 6 */
+#define FMC_PATT3_ATTHIZ3_7 0x80000000U /*!<Bit 7 */
+
+/****************** Bit definition for FMC_PATT4 register ******************/
+#define FMC_PATT4_ATTSET4 0x000000FFU /*!<ATTSET4[7:0] bits (Attribute memory 4 setup time) */
+#define FMC_PATT4_ATTSET4_0 0x00000001U /*!<Bit 0 */
+#define FMC_PATT4_ATTSET4_1 0x00000002U /*!<Bit 1 */
+#define FMC_PATT4_ATTSET4_2 0x00000004U /*!<Bit 2 */
+#define FMC_PATT4_ATTSET4_3 0x00000008U /*!<Bit 3 */
+#define FMC_PATT4_ATTSET4_4 0x00000010U /*!<Bit 4 */
+#define FMC_PATT4_ATTSET4_5 0x00000020U /*!<Bit 5 */
+#define FMC_PATT4_ATTSET4_6 0x00000040U /*!<Bit 6 */
+#define FMC_PATT4_ATTSET4_7 0x00000080U /*!<Bit 7 */
+
+#define FMC_PATT4_ATTWAIT4 0x0000FF00U /*!<ATTWAIT4[7:0] bits (Attribute memory 4 wait time) */
+#define FMC_PATT4_ATTWAIT4_0 0x00000100U /*!<Bit 0 */
+#define FMC_PATT4_ATTWAIT4_1 0x00000200U /*!<Bit 1 */
+#define FMC_PATT4_ATTWAIT4_2 0x00000400U /*!<Bit 2 */
+#define FMC_PATT4_ATTWAIT4_3 0x00000800U /*!<Bit 3 */
+#define FMC_PATT4_ATTWAIT4_4 0x00001000U /*!<Bit 4 */
+#define FMC_PATT4_ATTWAIT4_5 0x00002000U /*!<Bit 5 */
+#define FMC_PATT4_ATTWAIT4_6 0x00004000U /*!<Bit 6 */
+#define FMC_PATT4_ATTWAIT4_7 0x00008000U /*!<Bit 7 */
+
+#define FMC_PATT4_ATTHOLD4 0x00FF0000U /*!<ATTHOLD4[7:0] bits (Attribute memory 4 hold time) */
+#define FMC_PATT4_ATTHOLD4_0 0x00010000U /*!<Bit 0 */
+#define FMC_PATT4_ATTHOLD4_1 0x00020000U /*!<Bit 1 */
+#define FMC_PATT4_ATTHOLD4_2 0x00040000U /*!<Bit 2 */
+#define FMC_PATT4_ATTHOLD4_3 0x00080000U /*!<Bit 3 */
+#define FMC_PATT4_ATTHOLD4_4 0x00100000U /*!<Bit 4 */
+#define FMC_PATT4_ATTHOLD4_5 0x00200000U /*!<Bit 5 */
+#define FMC_PATT4_ATTHOLD4_6 0x00400000U /*!<Bit 6 */
+#define FMC_PATT4_ATTHOLD4_7 0x00800000U /*!<Bit 7 */
+
+#define FMC_PATT4_ATTHIZ4 0xFF000000U /*!<ATTHIZ4[7:0] bits (Attribute memory 4 databus HiZ time) */
+#define FMC_PATT4_ATTHIZ4_0 0x01000000U /*!<Bit 0 */
+#define FMC_PATT4_ATTHIZ4_1 0x02000000U /*!<Bit 1 */
+#define FMC_PATT4_ATTHIZ4_2 0x04000000U /*!<Bit 2 */
+#define FMC_PATT4_ATTHIZ4_3 0x08000000U /*!<Bit 3 */
+#define FMC_PATT4_ATTHIZ4_4 0x10000000U /*!<Bit 4 */
+#define FMC_PATT4_ATTHIZ4_5 0x20000000U /*!<Bit 5 */
+#define FMC_PATT4_ATTHIZ4_6 0x40000000U /*!<Bit 6 */
+#define FMC_PATT4_ATTHIZ4_7 0x80000000U /*!<Bit 7 */
+
+/****************** Bit definition for FMC_PIO4 register *******************/
+#define FMC_PIO4_IOSET4 0x000000FFU /*!<IOSET4[7:0] bits (I/O 4 setup time) */
+#define FMC_PIO4_IOSET4_0 0x00000001U /*!<Bit 0 */
+#define FMC_PIO4_IOSET4_1 0x00000002U /*!<Bit 1 */
+#define FMC_PIO4_IOSET4_2 0x00000004U /*!<Bit 2 */
+#define FMC_PIO4_IOSET4_3 0x00000008U /*!<Bit 3 */
+#define FMC_PIO4_IOSET4_4 0x00000010U /*!<Bit 4 */
+#define FMC_PIO4_IOSET4_5 0x00000020U /*!<Bit 5 */
+#define FMC_PIO4_IOSET4_6 0x00000040U /*!<Bit 6 */
+#define FMC_PIO4_IOSET4_7 0x00000080U /*!<Bit 7 */
+
+#define FMC_PIO4_IOWAIT4 0x0000FF00U /*!<IOWAIT4[7:0] bits (I/O 4 wait time) */
+#define FMC_PIO4_IOWAIT4_0 0x00000100U /*!<Bit 0 */
+#define FMC_PIO4_IOWAIT4_1 0x00000200U /*!<Bit 1 */
+#define FMC_PIO4_IOWAIT4_2 0x00000400U /*!<Bit 2 */
+#define FMC_PIO4_IOWAIT4_3 0x00000800U /*!<Bit 3 */
+#define FMC_PIO4_IOWAIT4_4 0x00001000U /*!<Bit 4 */
+#define FMC_PIO4_IOWAIT4_5 0x00002000U /*!<Bit 5 */
+#define FMC_PIO4_IOWAIT4_6 0x00004000U /*!<Bit 6 */
+#define FMC_PIO4_IOWAIT4_7 0x00008000U /*!<Bit 7 */
+
+#define FMC_PIO4_IOHOLD4 0x00FF0000U /*!<IOHOLD4[7:0] bits (I/O 4 hold time) */
+#define FMC_PIO4_IOHOLD4_0 0x00010000U /*!<Bit 0 */
+#define FMC_PIO4_IOHOLD4_1 0x00020000U /*!<Bit 1 */
+#define FMC_PIO4_IOHOLD4_2 0x00040000U /*!<Bit 2 */
+#define FMC_PIO4_IOHOLD4_3 0x00080000U /*!<Bit 3 */
+#define FMC_PIO4_IOHOLD4_4 0x00100000U /*!<Bit 4 */
+#define FMC_PIO4_IOHOLD4_5 0x00200000U /*!<Bit 5 */
+#define FMC_PIO4_IOHOLD4_6 0x00400000U /*!<Bit 6 */
+#define FMC_PIO4_IOHOLD4_7 0x00800000U /*!<Bit 7 */
+
+#define FMC_PIO4_IOHIZ4 0xFF000000U /*!<IOHIZ4[7:0] bits (I/O 4 databus HiZ time) */
+#define FMC_PIO4_IOHIZ4_0 0x01000000U /*!<Bit 0 */
+#define FMC_PIO4_IOHIZ4_1 0x02000000U /*!<Bit 1 */
+#define FMC_PIO4_IOHIZ4_2 0x04000000U /*!<Bit 2 */
+#define FMC_PIO4_IOHIZ4_3 0x08000000U /*!<Bit 3 */
+#define FMC_PIO4_IOHIZ4_4 0x10000000U /*!<Bit 4 */
+#define FMC_PIO4_IOHIZ4_5 0x20000000U /*!<Bit 5 */
+#define FMC_PIO4_IOHIZ4_6 0x40000000U /*!<Bit 6 */
+#define FMC_PIO4_IOHIZ4_7 0x80000000U /*!<Bit 7 */
+
+/****************** Bit definition for FMC_ECCR2 register ******************/
+#define FMC_ECCR2_ECC2 0xFFFFFFFFU /*!<ECC result */
+
+/****************** Bit definition for FMC_ECCR3 register ******************/
+#define FMC_ECCR3_ECC3 0xFFFFFFFFU /*!<ECC result */
+
+/****************** Bit definition for FMC_SDCR1 register ******************/
+#define FMC_SDCR1_NC 0x00000003U /*!<NC[1:0] bits (Number of column bits) */
+#define FMC_SDCR1_NC_0 0x00000001U /*!<Bit 0 */
+#define FMC_SDCR1_NC_1 0x00000002U /*!<Bit 1 */
+
+#define FMC_SDCR1_NR 0x0000000CU /*!<NR[1:0] bits (Number of row bits) */
+#define FMC_SDCR1_NR_0 0x00000004U /*!<Bit 0 */
+#define FMC_SDCR1_NR_1 0x00000008U /*!<Bit 1 */
+
+#define FMC_SDCR1_MWID 0x00000030U /*!<NR[1:0] bits (Number of row bits) */
+#define FMC_SDCR1_MWID_0 0x00000010U /*!<Bit 0 */
+#define FMC_SDCR1_MWID_1 0x00000020U /*!<Bit 1 */
+
+#define FMC_SDCR1_NB 0x00000040U /*!<Number of internal bank */
+
+#define FMC_SDCR1_CAS 0x00000180U /*!<CAS[1:0] bits (CAS latency) */
+#define FMC_SDCR1_CAS_0 0x00000080U /*!<Bit 0 */
+#define FMC_SDCR1_CAS_1 0x00000100U /*!<Bit 1 */
+
+#define FMC_SDCR1_WP 0x00000200U /*!<Write protection */
+
+#define FMC_SDCR1_SDCLK 0x00000C00U /*!<SDRAM clock configuration */
+#define FMC_SDCR1_SDCLK_0 0x00000400U /*!<Bit 0 */
+#define FMC_SDCR1_SDCLK_1 0x00000800U /*!<Bit 1 */
+
+#define FMC_SDCR1_RBURST 0x00001000U /*!<Read burst */
+
+#define FMC_SDCR1_RPIPE 0x00006000U /*!<Write protection */
+#define FMC_SDCR1_RPIPE_0 0x00002000U /*!<Bit 0 */
+#define FMC_SDCR1_RPIPE_1 0x00004000U /*!<Bit 1 */
+
+/****************** Bit definition for FMC_SDCR2 register ******************/
+#define FMC_SDCR2_NC 0x00000003U /*!<NC[1:0] bits (Number of column bits) */
+#define FMC_SDCR2_NC_0 0x00000001U /*!<Bit 0 */
+#define FMC_SDCR2_NC_1 0x00000002U /*!<Bit 1 */
+
+#define FMC_SDCR2_NR 0x0000000CU /*!<NR[1:0] bits (Number of row bits) */
+#define FMC_SDCR2_NR_0 0x00000004U /*!<Bit 0 */
+#define FMC_SDCR2_NR_1 0x00000008U /*!<Bit 1 */
+
+#define FMC_SDCR2_MWID 0x00000030U /*!<NR[1:0] bits (Number of row bits) */
+#define FMC_SDCR2_MWID_0 0x00000010U /*!<Bit 0 */
+#define FMC_SDCR2_MWID_1 0x00000020U /*!<Bit 1 */
+
+#define FMC_SDCR2_NB 0x00000040U /*!<Number of internal bank */
+
+#define FMC_SDCR2_CAS 0x00000180U /*!<CAS[1:0] bits (CAS latency) */
+#define FMC_SDCR2_CAS_0 0x00000080U /*!<Bit 0 */
+#define FMC_SDCR2_CAS_1 0x00000100U /*!<Bit 1 */
+
+#define FMC_SDCR2_WP 0x00000200U /*!<Write protection */
+
+#define FMC_SDCR2_SDCLK 0x00000C00U /*!<SDCLK[1:0] (SDRAM clock configuration) */
+#define FMC_SDCR2_SDCLK_0 0x00000400U /*!<Bit 0 */
+#define FMC_SDCR2_SDCLK_1 0x00000800U /*!<Bit 1 */
+
+#define FMC_SDCR2_RBURST 0x00001000U /*!<Read burst */
+
+#define FMC_SDCR2_RPIPE 0x00006000U /*!<RPIPE[1:0](Read pipe) */
+#define FMC_SDCR2_RPIPE_0 0x00002000U /*!<Bit 0 */
+#define FMC_SDCR2_RPIPE_1 0x00004000U /*!<Bit 1 */
+
+/****************** Bit definition for FMC_SDTR1 register ******************/
+#define FMC_SDTR1_TMRD 0x0000000FU /*!<TMRD[3:0] bits (Load mode register to active) */
+#define FMC_SDTR1_TMRD_0 0x00000001U /*!<Bit 0 */
+#define FMC_SDTR1_TMRD_1 0x00000002U /*!<Bit 1 */
+#define FMC_SDTR1_TMRD_2 0x00000004U /*!<Bit 2 */
+#define FMC_SDTR1_TMRD_3 0x00000008U /*!<Bit 3 */
+
+#define FMC_SDTR1_TXSR 0x000000F0U /*!<TXSR[3:0] bits (Exit self refresh) */
+#define FMC_SDTR1_TXSR_0 0x00000010U /*!<Bit 0 */
+#define FMC_SDTR1_TXSR_1 0x00000020U /*!<Bit 1 */
+#define FMC_SDTR1_TXSR_2 0x00000040U /*!<Bit 2 */
+#define FMC_SDTR1_TXSR_3 0x00000080U /*!<Bit 3 */
+
+#define FMC_SDTR1_TRAS 0x00000F00U /*!<TRAS[3:0] bits (Self refresh time) */
+#define FMC_SDTR1_TRAS_0 0x00000100U /*!<Bit 0 */
+#define FMC_SDTR1_TRAS_1 0x00000200U /*!<Bit 1 */
+#define FMC_SDTR1_TRAS_2 0x00000400U /*!<Bit 2 */
+#define FMC_SDTR1_TRAS_3 0x00000800U /*!<Bit 3 */
+
+#define FMC_SDTR1_TRC 0x0000F000U /*!<TRC[2:0] bits (Row cycle delay) */
+#define FMC_SDTR1_TRC_0 0x00001000U /*!<Bit 0 */
+#define FMC_SDTR1_TRC_1 0x00002000U /*!<Bit 1 */
+#define FMC_SDTR1_TRC_2 0x00004000U /*!<Bit 2 */
+
+#define FMC_SDTR1_TWR 0x000F0000U /*!<TRC[2:0] bits (Write recovery delay) */
+#define FMC_SDTR1_TWR_0 0x00010000U /*!<Bit 0 */
+#define FMC_SDTR1_TWR_1 0x00020000U /*!<Bit 1 */
+#define FMC_SDTR1_TWR_2 0x00040000U /*!<Bit 2 */
+
+#define FMC_SDTR1_TRP 0x00F00000U /*!<TRP[2:0] bits (Row precharge delay) */
+#define FMC_SDTR1_TRP_0 0x00100000U /*!<Bit 0 */
+#define FMC_SDTR1_TRP_1 0x00200000U /*!<Bit 1 */
+#define FMC_SDTR1_TRP_2 0x00400000U /*!<Bit 2 */
+
+#define FMC_SDTR1_TRCD 0x0F000000U /*!<TRP[2:0] bits (Row to column delay) */
+#define FMC_SDTR1_TRCD_0 0x01000000U /*!<Bit 0 */
+#define FMC_SDTR1_TRCD_1 0x02000000U /*!<Bit 1 */
+#define FMC_SDTR1_TRCD_2 0x04000000U /*!<Bit 2 */
+
+/****************** Bit definition for FMC_SDTR2 register ******************/
+#define FMC_SDTR2_TMRD 0x0000000FU /*!<TMRD[3:0] bits (Load mode register to active) */
+#define FMC_SDTR2_TMRD_0 0x00000001U /*!<Bit 0 */
+#define FMC_SDTR2_TMRD_1 0x00000002U /*!<Bit 1 */
+#define FMC_SDTR2_TMRD_2 0x00000004U /*!<Bit 2 */
+#define FMC_SDTR2_TMRD_3 0x00000008U /*!<Bit 3 */
+
+#define FMC_SDTR2_TXSR 0x000000F0U /*!<TXSR[3:0] bits (Exit self refresh) */
+#define FMC_SDTR2_TXSR_0 0x00000010U /*!<Bit 0 */
+#define FMC_SDTR2_TXSR_1 0x00000020U /*!<Bit 1 */
+#define FMC_SDTR2_TXSR_2 0x00000040U /*!<Bit 2 */
+#define FMC_SDTR2_TXSR_3 0x00000080U /*!<Bit 3 */
+
+#define FMC_SDTR2_TRAS 0x00000F00U /*!<TRAS[3:0] bits (Self refresh time) */
+#define FMC_SDTR2_TRAS_0 0x00000100U /*!<Bit 0 */
+#define FMC_SDTR2_TRAS_1 0x00000200U /*!<Bit 1 */
+#define FMC_SDTR2_TRAS_2 0x00000400U /*!<Bit 2 */
+#define FMC_SDTR2_TRAS_3 0x00000800U /*!<Bit 3 */
+
+#define FMC_SDTR2_TRC 0x0000F000U /*!<TRC[2:0] bits (Row cycle delay) */
+#define FMC_SDTR2_TRC_0 0x00001000U /*!<Bit 0 */
+#define FMC_SDTR2_TRC_1 0x00002000U /*!<Bit 1 */
+#define FMC_SDTR2_TRC_2 0x00004000U /*!<Bit 2 */
+
+#define FMC_SDTR2_TWR 0x000F0000U /*!<TRC[2:0] bits (Write recovery delay) */
+#define FMC_SDTR2_TWR_0 0x00010000U /*!<Bit 0 */
+#define FMC_SDTR2_TWR_1 0x00020000U /*!<Bit 1 */
+#define FMC_SDTR2_TWR_2 0x00040000U /*!<Bit 2 */
+
+#define FMC_SDTR2_TRP 0x00F00000U /*!<TRP[2:0] bits (Row precharge delay) */
+#define FMC_SDTR2_TRP_0 0x00100000U /*!<Bit 0 */
+#define FMC_SDTR2_TRP_1 0x00200000U /*!<Bit 1 */
+#define FMC_SDTR2_TRP_2 0x00400000U /*!<Bit 2 */
+
+#define FMC_SDTR2_TRCD 0x0F000000U /*!<TRP[2:0] bits (Row to column delay) */
+#define FMC_SDTR2_TRCD_0 0x01000000U /*!<Bit 0 */
+#define FMC_SDTR2_TRCD_1 0x02000000U /*!<Bit 1 */
+#define FMC_SDTR2_TRCD_2 0x04000000U /*!<Bit 2 */
+
+/****************** Bit definition for FMC_SDCMR register ******************/
+#define FMC_SDCMR_MODE 0x00000007U /*!<MODE[2:0] bits (Command mode) */
+#define FMC_SDCMR_MODE_0 0x00000001U /*!<Bit 0 */
+#define FMC_SDCMR_MODE_1 0x00000002U /*!<Bit 1 */
+#define FMC_SDCMR_MODE_2 0x00000004U /*!<Bit 2 */
+
+#define FMC_SDCMR_CTB2 0x00000008U /*!<Command target 2 */
+
+#define FMC_SDCMR_CTB1 0x00000010U /*!<Command target 1 */
+
+#define FMC_SDCMR_NRFS 0x000001E0U /*!<NRFS[3:0] bits (Number of auto-refresh) */
+#define FMC_SDCMR_NRFS_0 0x00000020U /*!<Bit 0 */
+#define FMC_SDCMR_NRFS_1 0x00000040U /*!<Bit 1 */
+#define FMC_SDCMR_NRFS_2 0x00000080U /*!<Bit 2 */
+#define FMC_SDCMR_NRFS_3 0x00000100U /*!<Bit 3 */
+
+#define FMC_SDCMR_MRD 0x003FFE00U /*!<MRD[12:0] bits (Mode register definition) */
+
+/****************** Bit definition for FMC_SDRTR register ******************/
+#define FMC_SDRTR_CRE 0x00000001U /*!<Clear refresh error flag */
+
+#define FMC_SDRTR_COUNT 0x00003FFEU /*!<COUNT[12:0] bits (Refresh timer count) */
+
+#define FMC_SDRTR_REIE 0x00004000U /*!<RES interupt enable */
+
+/****************** Bit definition for FMC_SDSR register ******************/
+#define FMC_SDSR_RE 0x00000001U /*!<Refresh error flag */
+
+#define FMC_SDSR_MODES1 0x00000006U /*!<MODES1[1:0]bits (Status mode for bank 1) */
+#define FMC_SDSR_MODES1_0 0x00000002U /*!<Bit 0 */
+#define FMC_SDSR_MODES1_1 0x00000004U /*!<Bit 1 */
+
+#define FMC_SDSR_MODES2 0x00000018U /*!<MODES2[1:0]bits (Status mode for bank 2) */
+#define FMC_SDSR_MODES2_0 0x00000008U /*!<Bit 0 */
+#define FMC_SDSR_MODES2_1 0x00000010U /*!<Bit 1 */
+#define FMC_SDSR_BUSY 0x00000020U /*!<Busy status */
+
+
+
+/******************************************************************************/
+/* */
+/* General Purpose I/O */
+/* */
+/******************************************************************************/
+/****************** Bits definition for GPIO_MODER register *****************/
+#define GPIO_MODER_MODER0 0x00000003U
+#define GPIO_MODER_MODER0_0 0x00000001U
+#define GPIO_MODER_MODER0_1 0x00000002U
+
+#define GPIO_MODER_MODER1 0x0000000CU
+#define GPIO_MODER_MODER1_0 0x00000004U
+#define GPIO_MODER_MODER1_1 0x00000008U
+
+#define GPIO_MODER_MODER2 0x00000030U
+#define GPIO_MODER_MODER2_0 0x00000010U
+#define GPIO_MODER_MODER2_1 0x00000020U
+
+#define GPIO_MODER_MODER3 0x000000C0U
+#define GPIO_MODER_MODER3_0 0x00000040U
+#define GPIO_MODER_MODER3_1 0x00000080U
+
+#define GPIO_MODER_MODER4 0x00000300U
+#define GPIO_MODER_MODER4_0 0x00000100U
+#define GPIO_MODER_MODER4_1 0x00000200U
+
+#define GPIO_MODER_MODER5 0x00000C00U
+#define GPIO_MODER_MODER5_0 0x00000400U
+#define GPIO_MODER_MODER5_1 0x00000800U
+
+#define GPIO_MODER_MODER6 0x00003000U
+#define GPIO_MODER_MODER6_0 0x00001000U
+#define GPIO_MODER_MODER6_1 0x00002000U
+
+#define GPIO_MODER_MODER7 0x0000C000U
+#define GPIO_MODER_MODER7_0 0x00004000U
+#define GPIO_MODER_MODER7_1 0x00008000U
+
+#define GPIO_MODER_MODER8 0x00030000U
+#define GPIO_MODER_MODER8_0 0x00010000U
+#define GPIO_MODER_MODER8_1 0x00020000U
+
+#define GPIO_MODER_MODER9 0x000C0000U
+#define GPIO_MODER_MODER9_0 0x00040000U
+#define GPIO_MODER_MODER9_1 0x00080000U
+
+#define GPIO_MODER_MODER10 0x00300000U
+#define GPIO_MODER_MODER10_0 0x00100000U
+#define GPIO_MODER_MODER10_1 0x00200000U
+
+#define GPIO_MODER_MODER11 0x00C00000U
+#define GPIO_MODER_MODER11_0 0x00400000U
+#define GPIO_MODER_MODER11_1 0x00800000U
+
+#define GPIO_MODER_MODER12 0x03000000U
+#define GPIO_MODER_MODER12_0 0x01000000U
+#define GPIO_MODER_MODER12_1 0x02000000U
+
+#define GPIO_MODER_MODER13 0x0C000000U
+#define GPIO_MODER_MODER13_0 0x04000000U
+#define GPIO_MODER_MODER13_1 0x08000000U
+
+#define GPIO_MODER_MODER14 0x30000000U
+#define GPIO_MODER_MODER14_0 0x10000000U
+#define GPIO_MODER_MODER14_1 0x20000000U
+
+#define GPIO_MODER_MODER15 0xC0000000U
+#define GPIO_MODER_MODER15_0 0x40000000U
+#define GPIO_MODER_MODER15_1 0x80000000U
+
+/****************** Bits definition for GPIO_OTYPER register ****************/
+#define GPIO_OTYPER_OT_0 0x00000001U
+#define GPIO_OTYPER_OT_1 0x00000002U
+#define GPIO_OTYPER_OT_2 0x00000004U
+#define GPIO_OTYPER_OT_3 0x00000008U
+#define GPIO_OTYPER_OT_4 0x00000010U
+#define GPIO_OTYPER_OT_5 0x00000020U
+#define GPIO_OTYPER_OT_6 0x00000040U
+#define GPIO_OTYPER_OT_7 0x00000080U
+#define GPIO_OTYPER_OT_8 0x00000100U
+#define GPIO_OTYPER_OT_9 0x00000200U
+#define GPIO_OTYPER_OT_10 0x00000400U
+#define GPIO_OTYPER_OT_11 0x00000800U
+#define GPIO_OTYPER_OT_12 0x00001000U
+#define GPIO_OTYPER_OT_13 0x00002000U
+#define GPIO_OTYPER_OT_14 0x00004000U
+#define GPIO_OTYPER_OT_15 0x00008000U
+
+/****************** Bits definition for GPIO_OSPEEDR register ***************/
+#define GPIO_OSPEEDER_OSPEEDR0 0x00000003U
+#define GPIO_OSPEEDER_OSPEEDR0_0 0x00000001U
+#define GPIO_OSPEEDER_OSPEEDR0_1 0x00000002U
+
+#define GPIO_OSPEEDER_OSPEEDR1 0x0000000CU
+#define GPIO_OSPEEDER_OSPEEDR1_0 0x00000004U
+#define GPIO_OSPEEDER_OSPEEDR1_1 0x00000008U
+
+#define GPIO_OSPEEDER_OSPEEDR2 0x00000030U
+#define GPIO_OSPEEDER_OSPEEDR2_0 0x00000010U
+#define GPIO_OSPEEDER_OSPEEDR2_1 0x00000020U
+
+#define GPIO_OSPEEDER_OSPEEDR3 0x000000C0U
+#define GPIO_OSPEEDER_OSPEEDR3_0 0x00000040U
+#define GPIO_OSPEEDER_OSPEEDR3_1 0x00000080U
+
+#define GPIO_OSPEEDER_OSPEEDR4 0x00000300U
+#define GPIO_OSPEEDER_OSPEEDR4_0 0x00000100U
+#define GPIO_OSPEEDER_OSPEEDR4_1 0x00000200U
+
+#define GPIO_OSPEEDER_OSPEEDR5 0x00000C00U
+#define GPIO_OSPEEDER_OSPEEDR5_0 0x00000400U
+#define GPIO_OSPEEDER_OSPEEDR5_1 0x00000800U
+
+#define GPIO_OSPEEDER_OSPEEDR6 0x00003000U
+#define GPIO_OSPEEDER_OSPEEDR6_0 0x00001000U
+#define GPIO_OSPEEDER_OSPEEDR6_1 0x00002000U
+
+#define GPIO_OSPEEDER_OSPEEDR7 0x0000C000U
+#define GPIO_OSPEEDER_OSPEEDR7_0 0x00004000U
+#define GPIO_OSPEEDER_OSPEEDR7_1 0x00008000U
+
+#define GPIO_OSPEEDER_OSPEEDR8 0x00030000U
+#define GPIO_OSPEEDER_OSPEEDR8_0 0x00010000U
+#define GPIO_OSPEEDER_OSPEEDR8_1 0x00020000U
+
+#define GPIO_OSPEEDER_OSPEEDR9 0x000C0000U
+#define GPIO_OSPEEDER_OSPEEDR9_0 0x00040000U
+#define GPIO_OSPEEDER_OSPEEDR9_1 0x00080000U
+
+#define GPIO_OSPEEDER_OSPEEDR10 0x00300000U
+#define GPIO_OSPEEDER_OSPEEDR10_0 0x00100000U
+#define GPIO_OSPEEDER_OSPEEDR10_1 0x00200000U
+
+#define GPIO_OSPEEDER_OSPEEDR11 0x00C00000U
+#define GPIO_OSPEEDER_OSPEEDR11_0 0x00400000U
+#define GPIO_OSPEEDER_OSPEEDR11_1 0x00800000U
+
+#define GPIO_OSPEEDER_OSPEEDR12 0x03000000U
+#define GPIO_OSPEEDER_OSPEEDR12_0 0x01000000U
+#define GPIO_OSPEEDER_OSPEEDR12_1 0x02000000U
+
+#define GPIO_OSPEEDER_OSPEEDR13 0x0C000000U
+#define GPIO_OSPEEDER_OSPEEDR13_0 0x04000000U
+#define GPIO_OSPEEDER_OSPEEDR13_1 0x08000000U
+
+#define GPIO_OSPEEDER_OSPEEDR14 0x30000000U
+#define GPIO_OSPEEDER_OSPEEDR14_0 0x10000000U
+#define GPIO_OSPEEDER_OSPEEDR14_1 0x20000000U
+
+#define GPIO_OSPEEDER_OSPEEDR15 0xC0000000U
+#define GPIO_OSPEEDER_OSPEEDR15_0 0x40000000U
+#define GPIO_OSPEEDER_OSPEEDR15_1 0x80000000U
+
+/****************** Bits definition for GPIO_PUPDR register *****************/
+#define GPIO_PUPDR_PUPDR0 0x00000003U
+#define GPIO_PUPDR_PUPDR0_0 0x00000001U
+#define GPIO_PUPDR_PUPDR0_1 0x00000002U
+
+#define GPIO_PUPDR_PUPDR1 0x0000000CU
+#define GPIO_PUPDR_PUPDR1_0 0x00000004U
+#define GPIO_PUPDR_PUPDR1_1 0x00000008U
+
+#define GPIO_PUPDR_PUPDR2 0x00000030U
+#define GPIO_PUPDR_PUPDR2_0 0x00000010U
+#define GPIO_PUPDR_PUPDR2_1 0x00000020U
+
+#define GPIO_PUPDR_PUPDR3 0x000000C0U
+#define GPIO_PUPDR_PUPDR3_0 0x00000040U
+#define GPIO_PUPDR_PUPDR3_1 0x00000080U
+
+#define GPIO_PUPDR_PUPDR4 0x00000300U
+#define GPIO_PUPDR_PUPDR4_0 0x00000100U
+#define GPIO_PUPDR_PUPDR4_1 0x00000200U
+
+#define GPIO_PUPDR_PUPDR5 0x00000C00U
+#define GPIO_PUPDR_PUPDR5_0 0x00000400U
+#define GPIO_PUPDR_PUPDR5_1 0x00000800U
+
+#define GPIO_PUPDR_PUPDR6 0x00003000U
+#define GPIO_PUPDR_PUPDR6_0 0x00001000U
+#define GPIO_PUPDR_PUPDR6_1 0x00002000U
+
+#define GPIO_PUPDR_PUPDR7 0x0000C000U
+#define GPIO_PUPDR_PUPDR7_0 0x00004000U
+#define GPIO_PUPDR_PUPDR7_1 0x00008000U
+
+#define GPIO_PUPDR_PUPDR8 0x00030000U
+#define GPIO_PUPDR_PUPDR8_0 0x00010000U
+#define GPIO_PUPDR_PUPDR8_1 0x00020000U
+
+#define GPIO_PUPDR_PUPDR9 0x000C0000U
+#define GPIO_PUPDR_PUPDR9_0 0x00040000U
+#define GPIO_PUPDR_PUPDR9_1 0x00080000U
+
+#define GPIO_PUPDR_PUPDR10 0x00300000U
+#define GPIO_PUPDR_PUPDR10_0 0x00100000U
+#define GPIO_PUPDR_PUPDR10_1 0x00200000U
+
+#define GPIO_PUPDR_PUPDR11 0x00C00000U
+#define GPIO_PUPDR_PUPDR11_0 0x00400000U
+#define GPIO_PUPDR_PUPDR11_1 0x00800000U
+
+#define GPIO_PUPDR_PUPDR12 0x03000000U
+#define GPIO_PUPDR_PUPDR12_0 0x01000000U
+#define GPIO_PUPDR_PUPDR12_1 0x02000000U
+
+#define GPIO_PUPDR_PUPDR13 0x0C000000U
+#define GPIO_PUPDR_PUPDR13_0 0x04000000U
+#define GPIO_PUPDR_PUPDR13_1 0x08000000U
+
+#define GPIO_PUPDR_PUPDR14 0x30000000U
+#define GPIO_PUPDR_PUPDR14_0 0x10000000U
+#define GPIO_PUPDR_PUPDR14_1 0x20000000U
+
+#define GPIO_PUPDR_PUPDR15 0xC0000000U
+#define GPIO_PUPDR_PUPDR15_0 0x40000000U
+#define GPIO_PUPDR_PUPDR15_1 0x80000000U
+
+/****************** Bits definition for GPIO_IDR register *******************/
+#define GPIO_IDR_IDR_0 0x00000001U
+#define GPIO_IDR_IDR_1 0x00000002U
+#define GPIO_IDR_IDR_2 0x00000004U
+#define GPIO_IDR_IDR_3 0x00000008U
+#define GPIO_IDR_IDR_4 0x00000010U
+#define GPIO_IDR_IDR_5 0x00000020U
+#define GPIO_IDR_IDR_6 0x00000040U
+#define GPIO_IDR_IDR_7 0x00000080U
+#define GPIO_IDR_IDR_8 0x00000100U
+#define GPIO_IDR_IDR_9 0x00000200U
+#define GPIO_IDR_IDR_10 0x00000400U
+#define GPIO_IDR_IDR_11 0x00000800U
+#define GPIO_IDR_IDR_12 0x00001000U
+#define GPIO_IDR_IDR_13 0x00002000U
+#define GPIO_IDR_IDR_14 0x00004000U
+#define GPIO_IDR_IDR_15 0x00008000U
+/* Old GPIO_IDR register bits definition, maintained for legacy purpose */
+#define GPIO_OTYPER_IDR_0 GPIO_IDR_IDR_0
+#define GPIO_OTYPER_IDR_1 GPIO_IDR_IDR_1
+#define GPIO_OTYPER_IDR_2 GPIO_IDR_IDR_2
+#define GPIO_OTYPER_IDR_3 GPIO_IDR_IDR_3
+#define GPIO_OTYPER_IDR_4 GPIO_IDR_IDR_4
+#define GPIO_OTYPER_IDR_5 GPIO_IDR_IDR_5
+#define GPIO_OTYPER_IDR_6 GPIO_IDR_IDR_6
+#define GPIO_OTYPER_IDR_7 GPIO_IDR_IDR_7
+#define GPIO_OTYPER_IDR_8 GPIO_IDR_IDR_8
+#define GPIO_OTYPER_IDR_9 GPIO_IDR_IDR_9
+#define GPIO_OTYPER_IDR_10 GPIO_IDR_IDR_10
+#define GPIO_OTYPER_IDR_11 GPIO_IDR_IDR_11
+#define GPIO_OTYPER_IDR_12 GPIO_IDR_IDR_12
+#define GPIO_OTYPER_IDR_13 GPIO_IDR_IDR_13
+#define GPIO_OTYPER_IDR_14 GPIO_IDR_IDR_14
+#define GPIO_OTYPER_IDR_15 GPIO_IDR_IDR_15
+
+/****************** Bits definition for GPIO_ODR register *******************/
+#define GPIO_ODR_ODR_0 0x00000001U
+#define GPIO_ODR_ODR_1 0x00000002U
+#define GPIO_ODR_ODR_2 0x00000004U
+#define GPIO_ODR_ODR_3 0x00000008U
+#define GPIO_ODR_ODR_4 0x00000010U
+#define GPIO_ODR_ODR_5 0x00000020U
+#define GPIO_ODR_ODR_6 0x00000040U
+#define GPIO_ODR_ODR_7 0x00000080U
+#define GPIO_ODR_ODR_8 0x00000100U
+#define GPIO_ODR_ODR_9 0x00000200U
+#define GPIO_ODR_ODR_10 0x00000400U
+#define GPIO_ODR_ODR_11 0x00000800U
+#define GPIO_ODR_ODR_12 0x00001000U
+#define GPIO_ODR_ODR_13 0x00002000U
+#define GPIO_ODR_ODR_14 0x00004000U
+#define GPIO_ODR_ODR_15 0x00008000U
+/* Old GPIO_ODR register bits definition, maintained for legacy purpose */
+#define GPIO_OTYPER_ODR_0 GPIO_ODR_ODR_0
+#define GPIO_OTYPER_ODR_1 GPIO_ODR_ODR_1
+#define GPIO_OTYPER_ODR_2 GPIO_ODR_ODR_2
+#define GPIO_OTYPER_ODR_3 GPIO_ODR_ODR_3
+#define GPIO_OTYPER_ODR_4 GPIO_ODR_ODR_4
+#define GPIO_OTYPER_ODR_5 GPIO_ODR_ODR_5
+#define GPIO_OTYPER_ODR_6 GPIO_ODR_ODR_6
+#define GPIO_OTYPER_ODR_7 GPIO_ODR_ODR_7
+#define GPIO_OTYPER_ODR_8 GPIO_ODR_ODR_8
+#define GPIO_OTYPER_ODR_9 GPIO_ODR_ODR_9
+#define GPIO_OTYPER_ODR_10 GPIO_ODR_ODR_10
+#define GPIO_OTYPER_ODR_11 GPIO_ODR_ODR_11
+#define GPIO_OTYPER_ODR_12 GPIO_ODR_ODR_12
+#define GPIO_OTYPER_ODR_13 GPIO_ODR_ODR_13
+#define GPIO_OTYPER_ODR_14 GPIO_ODR_ODR_14
+#define GPIO_OTYPER_ODR_15 GPIO_ODR_ODR_15
+
+/****************** Bits definition for GPIO_BSRR register ******************/
+#define GPIO_BSRR_BS_0 0x00000001U
+#define GPIO_BSRR_BS_1 0x00000002U
+#define GPIO_BSRR_BS_2 0x00000004U
+#define GPIO_BSRR_BS_3 0x00000008U
+#define GPIO_BSRR_BS_4 0x00000010U
+#define GPIO_BSRR_BS_5 0x00000020U
+#define GPIO_BSRR_BS_6 0x00000040U
+#define GPIO_BSRR_BS_7 0x00000080U
+#define GPIO_BSRR_BS_8 0x00000100U
+#define GPIO_BSRR_BS_9 0x00000200U
+#define GPIO_BSRR_BS_10 0x00000400U
+#define GPIO_BSRR_BS_11 0x00000800U
+#define GPIO_BSRR_BS_12 0x00001000U
+#define GPIO_BSRR_BS_13 0x00002000U
+#define GPIO_BSRR_BS_14 0x00004000U
+#define GPIO_BSRR_BS_15 0x00008000U
+#define GPIO_BSRR_BR_0 0x00010000U
+#define GPIO_BSRR_BR_1 0x00020000U
+#define GPIO_BSRR_BR_2 0x00040000U
+#define GPIO_BSRR_BR_3 0x00080000U
+#define GPIO_BSRR_BR_4 0x00100000U
+#define GPIO_BSRR_BR_5 0x00200000U
+#define GPIO_BSRR_BR_6 0x00400000U
+#define GPIO_BSRR_BR_7 0x00800000U
+#define GPIO_BSRR_BR_8 0x01000000U
+#define GPIO_BSRR_BR_9 0x02000000U
+#define GPIO_BSRR_BR_10 0x04000000U
+#define GPIO_BSRR_BR_11 0x08000000U
+#define GPIO_BSRR_BR_12 0x10000000U
+#define GPIO_BSRR_BR_13 0x20000000U
+#define GPIO_BSRR_BR_14 0x40000000U
+#define GPIO_BSRR_BR_15 0x80000000U
+
+/****************** Bit definition for GPIO_LCKR register *********************/
+#define GPIO_LCKR_LCK0 0x00000001U
+#define GPIO_LCKR_LCK1 0x00000002U
+#define GPIO_LCKR_LCK2 0x00000004U
+#define GPIO_LCKR_LCK3 0x00000008U
+#define GPIO_LCKR_LCK4 0x00000010U
+#define GPIO_LCKR_LCK5 0x00000020U
+#define GPIO_LCKR_LCK6 0x00000040U
+#define GPIO_LCKR_LCK7 0x00000080U
+#define GPIO_LCKR_LCK8 0x00000100U
+#define GPIO_LCKR_LCK9 0x00000200U
+#define GPIO_LCKR_LCK10 0x00000400U
+#define GPIO_LCKR_LCK11 0x00000800U
+#define GPIO_LCKR_LCK12 0x00001000U
+#define GPIO_LCKR_LCK13 0x00002000U
+#define GPIO_LCKR_LCK14 0x00004000U
+#define GPIO_LCKR_LCK15 0x00008000U
+#define GPIO_LCKR_LCKK 0x00010000U
+
+/******************************************************************************/
+/* */
+/* Inter-integrated Circuit Interface */
+/* */
+/******************************************************************************/
+/******************* Bit definition for I2C_CR1 register ********************/
+#define I2C_CR1_PE 0x00000001U /*!<Peripheral Enable */
+#define I2C_CR1_SMBUS 0x00000002U /*!<SMBus Mode */
+#define I2C_CR1_SMBTYPE 0x00000008U /*!<SMBus Type */
+#define I2C_CR1_ENARP 0x00000010U /*!<ARP Enable */
+#define I2C_CR1_ENPEC 0x00000020U /*!<PEC Enable */
+#define I2C_CR1_ENGC 0x00000040U /*!<General Call Enable */
+#define I2C_CR1_NOSTRETCH 0x00000080U /*!<Clock Stretching Disable (Slave mode) */
+#define I2C_CR1_START 0x00000100U /*!<Start Generation */
+#define I2C_CR1_STOP 0x00000200U /*!<Stop Generation */
+#define I2C_CR1_ACK 0x00000400U /*!<Acknowledge Enable */
+#define I2C_CR1_POS 0x00000800U /*!<Acknowledge/PEC Position (for data reception) */
+#define I2C_CR1_PEC 0x00001000U /*!<Packet Error Checking */
+#define I2C_CR1_ALERT 0x00002000U /*!<SMBus Alert */
+#define I2C_CR1_SWRST 0x00008000U /*!<Software Reset */
+
+/******************* Bit definition for I2C_CR2 register ********************/
+#define I2C_CR2_FREQ 0x0000003FU /*!<FREQ[5:0] bits (Peripheral Clock Frequency) */
+#define I2C_CR2_FREQ_0 0x00000001U /*!<Bit 0 */
+#define I2C_CR2_FREQ_1 0x00000002U /*!<Bit 1 */
+#define I2C_CR2_FREQ_2 0x00000004U /*!<Bit 2 */
+#define I2C_CR2_FREQ_3 0x00000008U /*!<Bit 3 */
+#define I2C_CR2_FREQ_4 0x00000010U /*!<Bit 4 */
+#define I2C_CR2_FREQ_5 0x00000020U /*!<Bit 5 */
+
+#define I2C_CR2_ITERREN 0x00000100U /*!<Error Interrupt Enable */
+#define I2C_CR2_ITEVTEN 0x00000200U /*!<Event Interrupt Enable */
+#define I2C_CR2_ITBUFEN 0x00000400U /*!<Buffer Interrupt Enable */
+#define I2C_CR2_DMAEN 0x00000800U /*!<DMA Requests Enable */
+#define I2C_CR2_LAST 0x00001000U /*!<DMA Last Transfer */
+
+/******************* Bit definition for I2C_OAR1 register *******************/
+#define I2C_OAR1_ADD1_7 0x000000FEU /*!<Interface Address */
+#define I2C_OAR1_ADD8_9 0x00000300U /*!<Interface Address */
+
+#define I2C_OAR1_ADD0 0x00000001U /*!<Bit 0 */
+#define I2C_OAR1_ADD1 0x00000002U /*!<Bit 1 */
+#define I2C_OAR1_ADD2 0x00000004U /*!<Bit 2 */
+#define I2C_OAR1_ADD3 0x00000008U /*!<Bit 3 */
+#define I2C_OAR1_ADD4 0x00000010U /*!<Bit 4 */
+#define I2C_OAR1_ADD5 0x00000020U /*!<Bit 5 */
+#define I2C_OAR1_ADD6 0x00000040U /*!<Bit 6 */
+#define I2C_OAR1_ADD7 0x00000080U /*!<Bit 7 */
+#define I2C_OAR1_ADD8 0x00000100U /*!<Bit 8 */
+#define I2C_OAR1_ADD9 0x00000200U /*!<Bit 9 */
+
+#define I2C_OAR1_ADDMODE 0x00008000U /*!<Addressing Mode (Slave mode) */
+
+/******************* Bit definition for I2C_OAR2 register *******************/
+#define I2C_OAR2_ENDUAL 0x00000001U /*!<Dual addressing mode enable */
+#define I2C_OAR2_ADD2 0x000000FEU /*!<Interface address */
+
+/******************** Bit definition for I2C_DR register ********************/
+#define I2C_DR_DR 0x000000FFU /*!<8-bit Data Register */
+
+/******************* Bit definition for I2C_SR1 register ********************/
+#define I2C_SR1_SB 0x00000001U /*!<Start Bit (Master mode) */
+#define I2C_SR1_ADDR 0x00000002U /*!<Address sent (master mode)/matched (slave mode) */
+#define I2C_SR1_BTF 0x00000004U /*!<Byte Transfer Finished */
+#define I2C_SR1_ADD10 0x00000008U /*!<10-bit header sent (Master mode) */
+#define I2C_SR1_STOPF 0x00000010U /*!<Stop detection (Slave mode) */
+#define I2C_SR1_RXNE 0x00000040U /*!<Data Register not Empty (receivers) */
+#define I2C_SR1_TXE 0x00000080U /*!<Data Register Empty (transmitters) */
+#define I2C_SR1_BERR 0x00000100U /*!<Bus Error */
+#define I2C_SR1_ARLO 0x00000200U /*!<Arbitration Lost (master mode) */
+#define I2C_SR1_AF 0x00000400U /*!<Acknowledge Failure */
+#define I2C_SR1_OVR 0x00000800U /*!<Overrun/Underrun */
+#define I2C_SR1_PECERR 0x00001000U /*!<PEC Error in reception */
+#define I2C_SR1_TIMEOUT 0x00004000U /*!<Timeout or Tlow Error */
+#define I2C_SR1_SMBALERT 0x00008000U /*!<SMBus Alert */
+
+/******************* Bit definition for I2C_SR2 register ********************/
+#define I2C_SR2_MSL 0x00000001U /*!<Master/Slave */
+#define I2C_SR2_BUSY 0x00000002U /*!<Bus Busy */
+#define I2C_SR2_TRA 0x00000004U /*!<Transmitter/Receiver */
+#define I2C_SR2_GENCALL 0x00000010U /*!<General Call Address (Slave mode) */
+#define I2C_SR2_SMBDEFAULT 0x00000020U /*!<SMBus Device Default Address (Slave mode) */
+#define I2C_SR2_SMBHOST 0x00000040U /*!<SMBus Host Header (Slave mode) */
+#define I2C_SR2_DUALF 0x00000080U /*!<Dual Flag (Slave mode) */
+#define I2C_SR2_PEC 0x0000FF00U /*!<Packet Error Checking Register */
+
+/******************* Bit definition for I2C_CCR register ********************/
+#define I2C_CCR_CCR 0x00000FFFU /*!<Clock Control Register in Fast/Standard mode (Master mode) */
+#define I2C_CCR_DUTY 0x00004000U /*!<Fast Mode Duty Cycle */
+#define I2C_CCR_FS 0x00008000U /*!<I2C Master Mode Selection */
+
+/****************** Bit definition for I2C_TRISE register *******************/
+#define I2C_TRISE_TRISE 0x0000003FU /*!<Maximum Rise Time in Fast/Standard mode (Master mode) */
+
+/****************** Bit definition for I2C_FLTR register *******************/
+#define I2C_FLTR_DNF 0x0000000FU /*!<Digital Noise Filter */
+#define I2C_FLTR_ANOFF 0x00000010U /*!<Analog Noise Filter OFF */
+
+/******************************************************************************/
+/* */
+/* Independent WATCHDOG */
+/* */
+/******************************************************************************/
+/******************* Bit definition for IWDG_KR register ********************/
+#define IWDG_KR_KEY 0xFFFFU /*!<Key value (write only, read 0000h) */
+
+/******************* Bit definition for IWDG_PR register ********************/
+#define IWDG_PR_PR 0x07U /*!<PR[2:0] (Prescaler divider) */
+#define IWDG_PR_PR_0 0x01U /*!<Bit 0 */
+#define IWDG_PR_PR_1 0x02U /*!<Bit 1 */
+#define IWDG_PR_PR_2 0x04U /*!<Bit 2 */
+
+/******************* Bit definition for IWDG_RLR register *******************/
+#define IWDG_RLR_RL 0x0FFFU /*!<Watchdog counter reload value */
+
+/******************* Bit definition for IWDG_SR register ********************/
+#define IWDG_SR_PVU 0x01U /*!<Watchdog prescaler value update */
+#define IWDG_SR_RVU 0x02U /*!<Watchdog counter reload value update */
+
+
+/******************************************************************************/
+/* */
+/* Power Control */
+/* */
+/******************************************************************************/
+/******************** Bit definition for PWR_CR register ********************/
+#define PWR_CR_LPDS 0x00000001U /*!< Low-Power Deepsleep */
+#define PWR_CR_PDDS 0x00000002U /*!< Power Down Deepsleep */
+#define PWR_CR_CWUF 0x00000004U /*!< Clear Wakeup Flag */
+#define PWR_CR_CSBF 0x00000008U /*!< Clear Standby Flag */
+#define PWR_CR_PVDE 0x00000010U /*!< Power Voltage Detector Enable */
+
+#define PWR_CR_PLS 0x000000E0U /*!< PLS[2:0] bits (PVD Level Selection) */
+#define PWR_CR_PLS_0 0x00000020U /*!< Bit 0 */
+#define PWR_CR_PLS_1 0x00000040U /*!< Bit 1 */
+#define PWR_CR_PLS_2 0x00000080U /*!< Bit 2 */
+
+/*!< PVD level configuration */
+#define PWR_CR_PLS_LEV0 0x00000000U /*!< PVD level 0 */
+#define PWR_CR_PLS_LEV1 0x00000020U /*!< PVD level 1 */
+#define PWR_CR_PLS_LEV2 0x00000040U /*!< PVD level 2 */
+#define PWR_CR_PLS_LEV3 0x00000060U /*!< PVD level 3 */
+#define PWR_CR_PLS_LEV4 0x00000080U /*!< PVD level 4 */
+#define PWR_CR_PLS_LEV5 0x000000A0U /*!< PVD level 5 */
+#define PWR_CR_PLS_LEV6 0x000000C0U /*!< PVD level 6 */
+#define PWR_CR_PLS_LEV7 0x000000E0U /*!< PVD level 7 */
+#define PWR_CR_DBP 0x00000100U /*!< Disable Backup Domain write protection */
+#define PWR_CR_FPDS 0x00000200U /*!< Flash power down in Stop mode */
+#define PWR_CR_LPLVDS 0x00000400U /*!< Low-Power Regulator Low Voltage Scaling in Stop mode */
+#define PWR_CR_MRLVDS 0x00000800U /*!< Main regulator Low Voltage Scaling in Stop mode */
+#define PWR_CR_ADCDC1 0x00002000U /*!< Refer to AN4073 on how to use this bit */
+#define PWR_CR_VOS 0x0000C000U /*!< VOS[1:0] bits (Regulator voltage scaling output selection) */
+#define PWR_CR_VOS_0 0x00004000U /*!< Bit 0 */
+#define PWR_CR_VOS_1 0x00008000U /*!< Bit 1 */
+#define PWR_CR_ODEN 0x00010000U /*!< Over Drive enable */
+#define PWR_CR_ODSWEN 0x00020000U /*!< Over Drive switch enabled */
+#define PWR_CR_UDEN 0x000C0000U /*!< Under Drive enable in stop mode */
+#define PWR_CR_UDEN_0 0x00040000U /*!< Bit 0 */
+#define PWR_CR_UDEN_1 0x00080000U /*!< Bit 1 */
+
+/* Legacy define */
+#define PWR_CR_PMODE PWR_CR_VOS
+#define PWR_CR_LPUDS PWR_CR_LPLVDS /*!< Low-Power Regulator in deepsleep under-drive mode */
+#define PWR_CR_MRUDS PWR_CR_MRLVDS /*!< Main regulator in deepsleep under-drive mode */
+
+/******************* Bit definition for PWR_CSR register ********************/
+#define PWR_CSR_WUF 0x00000001U /*!< Wakeup Flag */
+#define PWR_CSR_SBF 0x00000002U /*!< Standby Flag */
+#define PWR_CSR_PVDO 0x00000004U /*!< PVD Output */
+#define PWR_CSR_BRR 0x00000008U /*!< Backup regulator ready */
+#define PWR_CSR_EWUP 0x00000100U /*!< Enable WKUP pin */
+#define PWR_CSR_BRE 0x00000200U /*!< Backup regulator enable */
+#define PWR_CSR_VOSRDY 0x00004000U /*!< Regulator voltage scaling output selection ready */
+#define PWR_CSR_ODRDY 0x00010000U /*!< Over Drive generator ready */
+#define PWR_CSR_ODSWRDY 0x00020000U /*!< Over Drive Switch ready */
+#define PWR_CSR_UDSWRDY 0x000C0000U /*!< Under Drive ready */
+
+/* Legacy define */
+#define PWR_CSR_REGRDY PWR_CSR_VOSRDY
+
+/******************************************************************************/
+/* */
+/* Reset and Clock Control */
+/* */
+/******************************************************************************/
+/******************** Bit definition for RCC_CR register ********************/
+#define RCC_CR_HSION 0x00000001U
+#define RCC_CR_HSIRDY 0x00000002U
+
+#define RCC_CR_HSITRIM 0x000000F8U
+#define RCC_CR_HSITRIM_0 0x00000008U/*!<Bit 0 */
+#define RCC_CR_HSITRIM_1 0x00000010U/*!<Bit 1 */
+#define RCC_CR_HSITRIM_2 0x00000020U/*!<Bit 2 */
+#define RCC_CR_HSITRIM_3 0x00000040U/*!<Bit 3 */
+#define RCC_CR_HSITRIM_4 0x00000080U/*!<Bit 4 */
+
+#define RCC_CR_HSICAL 0x0000FF00U
+#define RCC_CR_HSICAL_0 0x00000100U/*!<Bit 0 */
+#define RCC_CR_HSICAL_1 0x00000200U/*!<Bit 1 */
+#define RCC_CR_HSICAL_2 0x00000400U/*!<Bit 2 */
+#define RCC_CR_HSICAL_3 0x00000800U/*!<Bit 3 */
+#define RCC_CR_HSICAL_4 0x00001000U/*!<Bit 4 */
+#define RCC_CR_HSICAL_5 0x00002000U/*!<Bit 5 */
+#define RCC_CR_HSICAL_6 0x00004000U/*!<Bit 6 */
+#define RCC_CR_HSICAL_7 0x00008000U/*!<Bit 7 */
+
+#define RCC_CR_HSEON 0x00010000U
+#define RCC_CR_HSERDY 0x00020000U
+#define RCC_CR_HSEBYP 0x00040000U
+#define RCC_CR_CSSON 0x00080000U
+#define RCC_CR_PLLON 0x01000000U
+#define RCC_CR_PLLRDY 0x02000000U
+#define RCC_CR_PLLI2SON 0x04000000U
+#define RCC_CR_PLLI2SRDY 0x08000000U
+#define RCC_CR_PLLSAION 0x10000000U
+#define RCC_CR_PLLSAIRDY 0x20000000U
+
+/******************** Bit definition for RCC_PLLCFGR register ***************/
+#define RCC_PLLCFGR_PLLM 0x0000003FU
+#define RCC_PLLCFGR_PLLM_0 0x00000001U
+#define RCC_PLLCFGR_PLLM_1 0x00000002U
+#define RCC_PLLCFGR_PLLM_2 0x00000004U
+#define RCC_PLLCFGR_PLLM_3 0x00000008U
+#define RCC_PLLCFGR_PLLM_4 0x00000010U
+#define RCC_PLLCFGR_PLLM_5 0x00000020U
+
+#define RCC_PLLCFGR_PLLN 0x00007FC0U
+#define RCC_PLLCFGR_PLLN_0 0x00000040U
+#define RCC_PLLCFGR_PLLN_1 0x00000080U
+#define RCC_PLLCFGR_PLLN_2 0x00000100U
+#define RCC_PLLCFGR_PLLN_3 0x00000200U
+#define RCC_PLLCFGR_PLLN_4 0x00000400U
+#define RCC_PLLCFGR_PLLN_5 0x00000800U
+#define RCC_PLLCFGR_PLLN_6 0x00001000U
+#define RCC_PLLCFGR_PLLN_7 0x00002000U
+#define RCC_PLLCFGR_PLLN_8 0x00004000U
+
+#define RCC_PLLCFGR_PLLP 0x00030000U
+#define RCC_PLLCFGR_PLLP_0 0x00010000U
+#define RCC_PLLCFGR_PLLP_1 0x00020000U
+
+#define RCC_PLLCFGR_PLLSRC 0x00400000U
+#define RCC_PLLCFGR_PLLSRC_HSE 0x00400000U
+#define RCC_PLLCFGR_PLLSRC_HSI 0x00000000U
+
+#define RCC_PLLCFGR_PLLQ 0x0F000000U
+#define RCC_PLLCFGR_PLLQ_0 0x01000000U
+#define RCC_PLLCFGR_PLLQ_1 0x02000000U
+#define RCC_PLLCFGR_PLLQ_2 0x04000000U
+#define RCC_PLLCFGR_PLLQ_3 0x08000000U
+
+/******************** Bit definition for RCC_CFGR register ******************/
+/*!< SW configuration */
+#define RCC_CFGR_SW 0x00000003U /*!< SW[1:0] bits (System clock Switch) */
+#define RCC_CFGR_SW_0 0x00000001U /*!< Bit 0 */
+#define RCC_CFGR_SW_1 0x00000002U /*!< Bit 1 */
+
+#define RCC_CFGR_SW_HSI 0x00000000U /*!< HSI selected as system clock */
+#define RCC_CFGR_SW_HSE 0x00000001U /*!< HSE selected as system clock */
+#define RCC_CFGR_SW_PLL 0x00000002U /*!< PLL selected as system clock */
+
+/*!< SWS configuration */
+#define RCC_CFGR_SWS 0x0000000CU /*!< SWS[1:0] bits (System Clock Switch Status) */
+#define RCC_CFGR_SWS_0 0x00000004U /*!< Bit 0 */
+#define RCC_CFGR_SWS_1 0x00000008U /*!< Bit 1 */
+
+#define RCC_CFGR_SWS_HSI 0x00000000U /*!< HSI oscillator used as system clock */
+#define RCC_CFGR_SWS_HSE 0x00000004U /*!< HSE oscillator used as system clock */
+#define RCC_CFGR_SWS_PLL 0x00000008U /*!< PLL used as system clock */
+
+/*!< HPRE configuration */
+#define RCC_CFGR_HPRE 0x000000F0U /*!< HPRE[3:0] bits (AHB prescaler) */
+#define RCC_CFGR_HPRE_0 0x00000010U /*!< Bit 0 */
+#define RCC_CFGR_HPRE_1 0x00000020U /*!< Bit 1 */
+#define RCC_CFGR_HPRE_2 0x00000040U /*!< Bit 2 */
+#define RCC_CFGR_HPRE_3 0x00000080U /*!< Bit 3 */
+
+#define RCC_CFGR_HPRE_DIV1 0x00000000U /*!< SYSCLK not divided */
+#define RCC_CFGR_HPRE_DIV2 0x00000080U /*!< SYSCLK divided by 2 */
+#define RCC_CFGR_HPRE_DIV4 0x00000090U /*!< SYSCLK divided by 4 */
+#define RCC_CFGR_HPRE_DIV8 0x000000A0U /*!< SYSCLK divided by 8 */
+#define RCC_CFGR_HPRE_DIV16 0x000000B0U /*!< SYSCLK divided by 16 */
+#define RCC_CFGR_HPRE_DIV64 0x000000C0U /*!< SYSCLK divided by 64 */
+#define RCC_CFGR_HPRE_DIV128 0x000000D0U /*!< SYSCLK divided by 128 */
+#define RCC_CFGR_HPRE_DIV256 0x000000E0U /*!< SYSCLK divided by 256 */
+#define RCC_CFGR_HPRE_DIV512 0x000000F0U /*!< SYSCLK divided by 512 */
+
+/*!< PPRE1 configuration */
+#define RCC_CFGR_PPRE1 0x00001C00U /*!< PRE1[2:0] bits (APB1 prescaler) */
+#define RCC_CFGR_PPRE1_0 0x00000400U /*!< Bit 0 */
+#define RCC_CFGR_PPRE1_1 0x00000800U /*!< Bit 1 */
+#define RCC_CFGR_PPRE1_2 0x00001000U /*!< Bit 2 */
+
+#define RCC_CFGR_PPRE1_DIV1 0x00000000U /*!< HCLK not divided */
+#define RCC_CFGR_PPRE1_DIV2 0x00001000U /*!< HCLK divided by 2 */
+#define RCC_CFGR_PPRE1_DIV4 0x00001400U /*!< HCLK divided by 4 */
+#define RCC_CFGR_PPRE1_DIV8 0x00001800U /*!< HCLK divided by 8 */
+#define RCC_CFGR_PPRE1_DIV16 0x00001C00U /*!< HCLK divided by 16 */
+
+/*!< PPRE2 configuration */
+#define RCC_CFGR_PPRE2 0x0000E000U /*!< PRE2[2:0] bits (APB2 prescaler) */
+#define RCC_CFGR_PPRE2_0 0x00002000U /*!< Bit 0 */
+#define RCC_CFGR_PPRE2_1 0x00004000U /*!< Bit 1 */
+#define RCC_CFGR_PPRE2_2 0x00008000U /*!< Bit 2 */
+
+#define RCC_CFGR_PPRE2_DIV1 0x00000000U /*!< HCLK not divided */
+#define RCC_CFGR_PPRE2_DIV2 0x00008000U /*!< HCLK divided by 2 */
+#define RCC_CFGR_PPRE2_DIV4 0x0000A000U /*!< HCLK divided by 4 */
+#define RCC_CFGR_PPRE2_DIV8 0x0000C000U /*!< HCLK divided by 8 */
+#define RCC_CFGR_PPRE2_DIV16 0x0000E000U /*!< HCLK divided by 16 */
+
+/*!< RTCPRE configuration */
+#define RCC_CFGR_RTCPRE 0x001F0000U
+#define RCC_CFGR_RTCPRE_0 0x00010000U
+#define RCC_CFGR_RTCPRE_1 0x00020000U
+#define RCC_CFGR_RTCPRE_2 0x00040000U
+#define RCC_CFGR_RTCPRE_3 0x00080000U
+#define RCC_CFGR_RTCPRE_4 0x00100000U
+
+/*!< MCO1 configuration */
+#define RCC_CFGR_MCO1 0x00600000U
+#define RCC_CFGR_MCO1_0 0x00200000U
+#define RCC_CFGR_MCO1_1 0x00400000U
+
+#define RCC_CFGR_I2SSRC 0x00800000U
+
+#define RCC_CFGR_MCO1PRE 0x07000000U
+#define RCC_CFGR_MCO1PRE_0 0x01000000U
+#define RCC_CFGR_MCO1PRE_1 0x02000000U
+#define RCC_CFGR_MCO1PRE_2 0x04000000U
+
+#define RCC_CFGR_MCO2PRE 0x38000000U
+#define RCC_CFGR_MCO2PRE_0 0x08000000U
+#define RCC_CFGR_MCO2PRE_1 0x10000000U
+#define RCC_CFGR_MCO2PRE_2 0x20000000U
+
+#define RCC_CFGR_MCO2 0xC0000000U
+#define RCC_CFGR_MCO2_0 0x40000000U
+#define RCC_CFGR_MCO2_1 0x80000000U
+
+/******************** Bit definition for RCC_CIR register *******************/
+#define RCC_CIR_LSIRDYF 0x00000001U
+#define RCC_CIR_LSERDYF 0x00000002U
+#define RCC_CIR_HSIRDYF 0x00000004U
+#define RCC_CIR_HSERDYF 0x00000008U
+#define RCC_CIR_PLLRDYF 0x00000010U
+#define RCC_CIR_PLLI2SRDYF 0x00000020U
+#define RCC_CIR_PLLSAIRDYF 0x00000040U
+#define RCC_CIR_CSSF 0x00000080U
+#define RCC_CIR_LSIRDYIE 0x00000100U
+#define RCC_CIR_LSERDYIE 0x00000200U
+#define RCC_CIR_HSIRDYIE 0x00000400U
+#define RCC_CIR_HSERDYIE 0x00000800U
+#define RCC_CIR_PLLRDYIE 0x00001000U
+#define RCC_CIR_PLLI2SRDYIE 0x00002000U
+#define RCC_CIR_PLLSAIRDYIE 0x00004000U
+#define RCC_CIR_LSIRDYC 0x00010000U
+#define RCC_CIR_LSERDYC 0x00020000U
+#define RCC_CIR_HSIRDYC 0x00040000U
+#define RCC_CIR_HSERDYC 0x00080000U
+#define RCC_CIR_PLLRDYC 0x00100000U
+#define RCC_CIR_PLLI2SRDYC 0x00200000U
+#define RCC_CIR_PLLSAIRDYC 0x00400000U
+#define RCC_CIR_CSSC 0x00800000U
+
+/******************** Bit definition for RCC_AHB1RSTR register **************/
+#define RCC_AHB1RSTR_GPIOARST 0x00000001U
+#define RCC_AHB1RSTR_GPIOBRST 0x00000002U
+#define RCC_AHB1RSTR_GPIOCRST 0x00000004U
+#define RCC_AHB1RSTR_GPIODRST 0x00000008U
+#define RCC_AHB1RSTR_GPIOERST 0x00000010U
+#define RCC_AHB1RSTR_GPIOFRST 0x00000020U
+#define RCC_AHB1RSTR_GPIOGRST 0x00000040U
+#define RCC_AHB1RSTR_GPIOHRST 0x00000080U
+#define RCC_AHB1RSTR_GPIOIRST 0x00000100U
+#define RCC_AHB1RSTR_GPIOJRST 0x00000200U
+#define RCC_AHB1RSTR_GPIOKRST 0x00000400U
+#define RCC_AHB1RSTR_CRCRST 0x00001000U
+#define RCC_AHB1RSTR_DMA1RST 0x00200000U
+#define RCC_AHB1RSTR_DMA2RST 0x00400000U
+#define RCC_AHB1RSTR_DMA2DRST 0x00800000U
+#define RCC_AHB1RSTR_ETHMACRST 0x02000000U
+#define RCC_AHB1RSTR_OTGHRST 0x20000000U
+
+/******************** Bit definition for RCC_AHB2RSTR register **************/
+#define RCC_AHB2RSTR_DCMIRST 0x00000001U
+#define RCC_AHB2RSTR_RNGRST 0x00000040U
+#define RCC_AHB2RSTR_OTGFSRST 0x00000080U
+
+/******************** Bit definition for RCC_AHB3RSTR register **************/
+#define RCC_AHB3RSTR_FMCRST 0x00000001U
+
+/******************** Bit definition for RCC_APB1RSTR register **************/
+#define RCC_APB1RSTR_TIM2RST 0x00000001U
+#define RCC_APB1RSTR_TIM3RST 0x00000002U
+#define RCC_APB1RSTR_TIM4RST 0x00000004U
+#define RCC_APB1RSTR_TIM5RST 0x00000008U
+#define RCC_APB1RSTR_TIM6RST 0x00000010U
+#define RCC_APB1RSTR_TIM7RST 0x00000020U
+#define RCC_APB1RSTR_TIM12RST 0x00000040U
+#define RCC_APB1RSTR_TIM13RST 0x00000080U
+#define RCC_APB1RSTR_TIM14RST 0x00000100U
+#define RCC_APB1RSTR_WWDGRST 0x00000800U
+#define RCC_APB1RSTR_SPI2RST 0x00004000U
+#define RCC_APB1RSTR_SPI3RST 0x00008000U
+#define RCC_APB1RSTR_USART2RST 0x00020000U
+#define RCC_APB1RSTR_USART3RST 0x00040000U
+#define RCC_APB1RSTR_UART4RST 0x00080000U
+#define RCC_APB1RSTR_UART5RST 0x00100000U
+#define RCC_APB1RSTR_I2C1RST 0x00200000U
+#define RCC_APB1RSTR_I2C2RST 0x00400000U
+#define RCC_APB1RSTR_I2C3RST 0x00800000U
+#define RCC_APB1RSTR_CAN1RST 0x02000000U
+#define RCC_APB1RSTR_CAN2RST 0x04000000U
+#define RCC_APB1RSTR_PWRRST 0x10000000U
+#define RCC_APB1RSTR_DACRST 0x20000000U
+#define RCC_APB1RSTR_UART7RST 0x40000000U
+#define RCC_APB1RSTR_UART8RST 0x80000000U
+
+/******************** Bit definition for RCC_APB2RSTR register **************/
+#define RCC_APB2RSTR_TIM1RST 0x00000001U
+#define RCC_APB2RSTR_TIM8RST 0x00000002U
+#define RCC_APB2RSTR_USART1RST 0x00000010U
+#define RCC_APB2RSTR_USART6RST 0x00000020U
+#define RCC_APB2RSTR_ADCRST 0x00000100U
+#define RCC_APB2RSTR_SDIORST 0x00000800U
+#define RCC_APB2RSTR_SPI1RST 0x00001000U
+#define RCC_APB2RSTR_SPI4RST 0x00002000U
+#define RCC_APB2RSTR_SYSCFGRST 0x00004000U
+#define RCC_APB2RSTR_TIM9RST 0x00010000U
+#define RCC_APB2RSTR_TIM10RST 0x00020000U
+#define RCC_APB2RSTR_TIM11RST 0x00040000U
+#define RCC_APB2RSTR_SPI5RST 0x00100000U
+#define RCC_APB2RSTR_SPI6RST 0x00200000U
+#define RCC_APB2RSTR_SAI1RST 0x00400000U
+
+/* Old SPI1RST bit definition, maintained for legacy purpose */
+#define RCC_APB2RSTR_SPI1 RCC_APB2RSTR_SPI1RST
+
+/******************** Bit definition for RCC_AHB1ENR register ***************/
+#define RCC_AHB1ENR_GPIOAEN 0x00000001U
+#define RCC_AHB1ENR_GPIOBEN 0x00000002U
+#define RCC_AHB1ENR_GPIOCEN 0x00000004U
+#define RCC_AHB1ENR_GPIODEN 0x00000008U
+#define RCC_AHB1ENR_GPIOEEN 0x00000010U
+#define RCC_AHB1ENR_GPIOFEN 0x00000020U
+#define RCC_AHB1ENR_GPIOGEN 0x00000040U
+#define RCC_AHB1ENR_GPIOHEN 0x00000080U
+#define RCC_AHB1ENR_GPIOIEN 0x00000100U
+#define RCC_AHB1ENR_GPIOJEN 0x00000200U
+#define RCC_AHB1ENR_GPIOKEN 0x00000400U
+
+#define RCC_AHB1ENR_CRCEN 0x00001000U
+#define RCC_AHB1ENR_BKPSRAMEN 0x00040000U
+#define RCC_AHB1ENR_CCMDATARAMEN 0x00100000U
+#define RCC_AHB1ENR_DMA1EN 0x00200000U
+#define RCC_AHB1ENR_DMA2EN 0x00400000U
+#define RCC_AHB1ENR_DMA2DEN 0x00800000U
+
+#define RCC_AHB1ENR_ETHMACEN 0x02000000U
+#define RCC_AHB1ENR_ETHMACTXEN 0x04000000U
+#define RCC_AHB1ENR_ETHMACRXEN 0x08000000U
+#define RCC_AHB1ENR_ETHMACPTPEN 0x10000000U
+#define RCC_AHB1ENR_OTGHSEN 0x20000000U
+#define RCC_AHB1ENR_OTGHSULPIEN 0x40000000U
+
+/******************** Bit definition for RCC_AHB2ENR register ***************/
+#define RCC_AHB2ENR_DCMIEN 0x00000001U
+#define RCC_AHB2ENR_RNGEN 0x00000040U
+#define RCC_AHB2ENR_OTGFSEN 0x00000080U
+
+/******************** Bit definition for RCC_AHB3ENR register ***************/
+#define RCC_AHB3ENR_FMCEN 0x00000001U
+
+/******************** Bit definition for RCC_APB1ENR register ***************/
+#define RCC_APB1ENR_TIM2EN 0x00000001U
+#define RCC_APB1ENR_TIM3EN 0x00000002U
+#define RCC_APB1ENR_TIM4EN 0x00000004U
+#define RCC_APB1ENR_TIM5EN 0x00000008U
+#define RCC_APB1ENR_TIM6EN 0x00000010U
+#define RCC_APB1ENR_TIM7EN 0x00000020U
+#define RCC_APB1ENR_TIM12EN 0x00000040U
+#define RCC_APB1ENR_TIM13EN 0x00000080U
+#define RCC_APB1ENR_TIM14EN 0x00000100U
+#define RCC_APB1ENR_WWDGEN 0x00000800U
+#define RCC_APB1ENR_SPI2EN 0x00004000U
+#define RCC_APB1ENR_SPI3EN 0x00008000U
+#define RCC_APB1ENR_USART2EN 0x00020000U
+#define RCC_APB1ENR_USART3EN 0x00040000U
+#define RCC_APB1ENR_UART4EN 0x00080000U
+#define RCC_APB1ENR_UART5EN 0x00100000U
+#define RCC_APB1ENR_I2C1EN 0x00200000U
+#define RCC_APB1ENR_I2C2EN 0x00400000U
+#define RCC_APB1ENR_I2C3EN 0x00800000U
+#define RCC_APB1ENR_CAN1EN 0x02000000U
+#define RCC_APB1ENR_CAN2EN 0x04000000U
+#define RCC_APB1ENR_PWREN 0x10000000U
+#define RCC_APB1ENR_DACEN 0x20000000U
+#define RCC_APB1ENR_UART7EN 0x40000000U
+#define RCC_APB1ENR_UART8EN 0x80000000U
+
+/******************** Bit definition for RCC_APB2ENR register ***************/
+#define RCC_APB2ENR_TIM1EN 0x00000001U
+#define RCC_APB2ENR_TIM8EN 0x00000002U
+#define RCC_APB2ENR_USART1EN 0x00000010U
+#define RCC_APB2ENR_USART6EN 0x00000020U
+#define RCC_APB2ENR_ADC1EN 0x00000100U
+#define RCC_APB2ENR_ADC2EN 0x00000200U
+#define RCC_APB2ENR_ADC3EN 0x00000400U
+#define RCC_APB2ENR_SDIOEN 0x00000800U
+#define RCC_APB2ENR_SPI1EN 0x00001000U
+#define RCC_APB2ENR_SPI4EN 0x00002000U
+#define RCC_APB2ENR_SYSCFGEN 0x00004000U
+#define RCC_APB2ENR_TIM9EN 0x00010000U
+#define RCC_APB2ENR_TIM10EN 0x00020000U
+#define RCC_APB2ENR_TIM11EN 0x00040000U
+#define RCC_APB2ENR_SPI5EN 0x00100000U
+#define RCC_APB2ENR_SPI6EN 0x00200000U
+#define RCC_APB2ENR_SAI1EN 0x00400000U
+
+/******************** Bit definition for RCC_AHB1LPENR register *************/
+#define RCC_AHB1LPENR_GPIOALPEN 0x00000001U
+#define RCC_AHB1LPENR_GPIOBLPEN 0x00000002U
+#define RCC_AHB1LPENR_GPIOCLPEN 0x00000004U
+#define RCC_AHB1LPENR_GPIODLPEN 0x00000008U
+#define RCC_AHB1LPENR_GPIOELPEN 0x00000010U
+#define RCC_AHB1LPENR_GPIOFLPEN 0x00000020U
+#define RCC_AHB1LPENR_GPIOGLPEN 0x00000040U
+#define RCC_AHB1LPENR_GPIOHLPEN 0x00000080U
+#define RCC_AHB1LPENR_GPIOILPEN 0x00000100U
+#define RCC_AHB1LPENR_GPIOJLPEN 0x00000200U
+#define RCC_AHB1LPENR_GPIOKLPEN 0x00000400U
+
+#define RCC_AHB1LPENR_CRCLPEN 0x00001000U
+#define RCC_AHB1LPENR_FLITFLPEN 0x00008000U
+#define RCC_AHB1LPENR_SRAM1LPEN 0x00010000U
+#define RCC_AHB1LPENR_SRAM2LPEN 0x00020000U
+#define RCC_AHB1LPENR_BKPSRAMLPEN 0x00040000U
+#define RCC_AHB1LPENR_DMA1LPEN 0x00200000U
+#define RCC_AHB1LPENR_DMA2LPEN 0x00400000U
+#define RCC_AHB1LPENR_DMA2DLPEN 0x00800000U
+
+#define RCC_AHB1LPENR_ETHMACLPEN 0x02000000U
+#define RCC_AHB1LPENR_ETHMACTXLPEN 0x04000000U
+#define RCC_AHB1LPENR_ETHMACRXLPEN 0x08000000U
+#define RCC_AHB1LPENR_ETHMACPTPLPEN 0x10000000U
+#define RCC_AHB1LPENR_OTGHSLPEN 0x20000000U
+#define RCC_AHB1LPENR_OTGHSULPILPEN 0x40000000U
+
+/******************** Bit definition for RCC_AHB2LPENR register *************/
+#define RCC_AHB2LPENR_DCMILPEN 0x00000001U
+#define RCC_AHB2LPENR_RNGLPEN 0x00000040U
+#define RCC_AHB2LPENR_OTGFSLPEN 0x00000080U
+
+/******************** Bit definition for RCC_AHB3LPENR register *************/
+#define RCC_AHB3LPENR_FMCLPEN 0x00000001U
+
+/******************** Bit definition for RCC_APB1LPENR register *************/
+#define RCC_APB1LPENR_TIM2LPEN 0x00000001U
+#define RCC_APB1LPENR_TIM3LPEN 0x00000002U
+#define RCC_APB1LPENR_TIM4LPEN 0x00000004U
+#define RCC_APB1LPENR_TIM5LPEN 0x00000008U
+#define RCC_APB1LPENR_TIM6LPEN 0x00000010U
+#define RCC_APB1LPENR_TIM7LPEN 0x00000020U
+#define RCC_APB1LPENR_TIM12LPEN 0x00000040U
+#define RCC_APB1LPENR_TIM13LPEN 0x00000080U
+#define RCC_APB1LPENR_TIM14LPEN 0x00000100U
+#define RCC_APB1LPENR_WWDGLPEN 0x00000800U
+#define RCC_APB1LPENR_SPI2LPEN 0x00004000U
+#define RCC_APB1LPENR_SPI3LPEN 0x00008000U
+#define RCC_APB1LPENR_USART2LPEN 0x00020000U
+#define RCC_APB1LPENR_USART3LPEN 0x00040000U
+#define RCC_APB1LPENR_UART4LPEN 0x00080000U
+#define RCC_APB1LPENR_UART5LPEN 0x00100000U
+#define RCC_APB1LPENR_I2C1LPEN 0x00200000U
+#define RCC_APB1LPENR_I2C2LPEN 0x00400000U
+#define RCC_APB1LPENR_I2C3LPEN 0x00800000U
+#define RCC_APB1LPENR_CAN1LPEN 0x02000000U
+#define RCC_APB1LPENR_CAN2LPEN 0x04000000U
+#define RCC_APB1LPENR_PWRLPEN 0x10000000U
+#define RCC_APB1LPENR_DACLPEN 0x20000000U
+#define RCC_APB1LPENR_UART7LPEN 0x40000000U
+#define RCC_APB1LPENR_UART8LPEN 0x80000000U
+
+/******************** Bit definition for RCC_APB2LPENR register *************/
+#define RCC_APB2LPENR_TIM1LPEN 0x00000001U
+#define RCC_APB2LPENR_TIM8LPEN 0x00000002U
+#define RCC_APB2LPENR_USART1LPEN 0x00000010U
+#define RCC_APB2LPENR_USART6LPEN 0x00000020U
+#define RCC_APB2LPENR_ADC1LPEN 0x00000100U
+#define RCC_APB2LPENR_ADC2LPEN 0x00000200U
+#define RCC_APB2LPENR_ADC3LPEN 0x00000400U
+#define RCC_APB2LPENR_SDIOLPEN 0x00000800U
+#define RCC_APB2LPENR_SPI1LPEN 0x00001000U
+#define RCC_APB2LPENR_SPI4LPEN 0x00002000U
+#define RCC_APB2LPENR_SYSCFGLPEN 0x00004000U
+#define RCC_APB2LPENR_TIM9LPEN 0x00010000U
+#define RCC_APB2LPENR_TIM10LPEN 0x00020000U
+#define RCC_APB2LPENR_TIM11LPEN 0x00040000U
+#define RCC_APB2LPENR_SPI5LPEN 0x00100000U
+#define RCC_APB2LPENR_SPI6LPEN 0x00200000U
+#define RCC_APB2LPENR_SAI1LPEN 0x00400000U
+
+/******************** Bit definition for RCC_BDCR register ******************/
+#define RCC_BDCR_LSEON 0x00000001U
+#define RCC_BDCR_LSERDY 0x00000002U
+#define RCC_BDCR_LSEBYP 0x00000004U
+
+#define RCC_BDCR_RTCSEL 0x00000300U
+#define RCC_BDCR_RTCSEL_0 0x00000100U
+#define RCC_BDCR_RTCSEL_1 0x00000200U
+
+#define RCC_BDCR_RTCEN 0x00008000U
+#define RCC_BDCR_BDRST 0x00010000U
+
+/******************** Bit definition for RCC_CSR register *******************/
+#define RCC_CSR_LSION 0x00000001U
+#define RCC_CSR_LSIRDY 0x00000002U
+#define RCC_CSR_RMVF 0x01000000U
+#define RCC_CSR_BORRSTF 0x02000000U
+#define RCC_CSR_PADRSTF 0x04000000U
+#define RCC_CSR_PORRSTF 0x08000000U
+#define RCC_CSR_SFTRSTF 0x10000000U
+#define RCC_CSR_WDGRSTF 0x20000000U
+#define RCC_CSR_WWDGRSTF 0x40000000U
+#define RCC_CSR_LPWRRSTF 0x80000000U
+
+/******************** Bit definition for RCC_SSCGR register *****************/
+#define RCC_SSCGR_MODPER 0x00001FFFU
+#define RCC_SSCGR_INCSTEP 0x0FFFE000U
+#define RCC_SSCGR_SPREADSEL 0x40000000U
+#define RCC_SSCGR_SSCGEN 0x80000000U
+
+/******************** Bit definition for RCC_PLLI2SCFGR register ************/
+#define RCC_PLLI2SCFGR_PLLI2SN 0x00007FC0U
+#define RCC_PLLI2SCFGR_PLLI2SN_0 0x00000040U
+#define RCC_PLLI2SCFGR_PLLI2SN_1 0x00000080U
+#define RCC_PLLI2SCFGR_PLLI2SN_2 0x00000100U
+#define RCC_PLLI2SCFGR_PLLI2SN_3 0x00000200U
+#define RCC_PLLI2SCFGR_PLLI2SN_4 0x00000400U
+#define RCC_PLLI2SCFGR_PLLI2SN_5 0x00000800U
+#define RCC_PLLI2SCFGR_PLLI2SN_6 0x00001000U
+#define RCC_PLLI2SCFGR_PLLI2SN_7 0x00002000U
+#define RCC_PLLI2SCFGR_PLLI2SN_8 0x00004000U
+
+#define RCC_PLLI2SCFGR_PLLI2SQ 0x0F000000U
+#define RCC_PLLI2SCFGR_PLLI2SQ_0 0x01000000U
+#define RCC_PLLI2SCFGR_PLLI2SQ_1 0x02000000U
+#define RCC_PLLI2SCFGR_PLLI2SQ_2 0x04000000U
+#define RCC_PLLI2SCFGR_PLLI2SQ_3 0x08000000U
+
+#define RCC_PLLI2SCFGR_PLLI2SR 0x70000000U
+#define RCC_PLLI2SCFGR_PLLI2SR_0 0x10000000U
+#define RCC_PLLI2SCFGR_PLLI2SR_1 0x20000000U
+#define RCC_PLLI2SCFGR_PLLI2SR_2 0x40000000U
+
+
+/******************** Bit definition for RCC_PLLSAICFGR register ************/
+#define RCC_PLLSAICFGR_PLLSAIN 0x00007FC0U
+#define RCC_PLLSAICFGR_PLLSAIN_0 0x00000040U
+#define RCC_PLLSAICFGR_PLLSAIN_1 0x00000080U
+#define RCC_PLLSAICFGR_PLLSAIN_2 0x00000100U
+#define RCC_PLLSAICFGR_PLLSAIN_3 0x00000200U
+#define RCC_PLLSAICFGR_PLLSAIN_4 0x00000400U
+#define RCC_PLLSAICFGR_PLLSAIN_5 0x00000800U
+#define RCC_PLLSAICFGR_PLLSAIN_6 0x00001000U
+#define RCC_PLLSAICFGR_PLLSAIN_7 0x00002000U
+#define RCC_PLLSAICFGR_PLLSAIN_8 0x00004000U
+
+#define RCC_PLLSAICFGR_PLLSAIQ 0x0F000000U
+#define RCC_PLLSAICFGR_PLLSAIQ_0 0x01000000U
+#define RCC_PLLSAICFGR_PLLSAIQ_1 0x02000000U
+#define RCC_PLLSAICFGR_PLLSAIQ_2 0x04000000U
+#define RCC_PLLSAICFGR_PLLSAIQ_3 0x08000000U
+
+#define RCC_PLLSAICFGR_PLLSAIR 0x70000000U
+#define RCC_PLLSAICFGR_PLLSAIR_0 0x10000000U
+#define RCC_PLLSAICFGR_PLLSAIR_1 0x20000000U
+#define RCC_PLLSAICFGR_PLLSAIR_2 0x40000000U
+
+/******************** Bit definition for RCC_DCKCFGR register ***************/
+#define RCC_DCKCFGR_PLLI2SDIVQ 0x0000001FU
+#define RCC_DCKCFGR_PLLSAIDIVQ 0x00001F00U
+#define RCC_DCKCFGR_PLLSAIDIVR 0x00030000U
+#define RCC_DCKCFGR_SAI1ASRC 0x00300000U
+#define RCC_DCKCFGR_SAI1ASRC_0 0x00100000U
+#define RCC_DCKCFGR_SAI1ASRC_1 0x00200000U
+#define RCC_DCKCFGR_SAI1BSRC 0x00C00000U
+#define RCC_DCKCFGR_SAI1BSRC_0 0x00400000U
+#define RCC_DCKCFGR_SAI1BSRC_1 0x00800000U
+#define RCC_DCKCFGR_TIMPRE 0x01000000U
+
+
+/******************************************************************************/
+/* */
+/* RNG */
+/* */
+/******************************************************************************/
+/******************** Bits definition for RNG_CR register *******************/
+#define RNG_CR_RNGEN 0x00000004U
+#define RNG_CR_IE 0x00000008U
+
+/******************** Bits definition for RNG_SR register *******************/
+#define RNG_SR_DRDY 0x00000001U
+#define RNG_SR_CECS 0x00000002U
+#define RNG_SR_SECS 0x00000004U
+#define RNG_SR_CEIS 0x00000020U
+#define RNG_SR_SEIS 0x00000040U
+
+/******************************************************************************/
+/* */
+/* Real-Time Clock (RTC) */
+/* */
+/******************************************************************************/
+/******************** Bits definition for RTC_TR register *******************/
+#define RTC_TR_PM 0x00400000U
+#define RTC_TR_HT 0x00300000U
+#define RTC_TR_HT_0 0x00100000U
+#define RTC_TR_HT_1 0x00200000U
+#define RTC_TR_HU 0x000F0000U
+#define RTC_TR_HU_0 0x00010000U
+#define RTC_TR_HU_1 0x00020000U
+#define RTC_TR_HU_2 0x00040000U
+#define RTC_TR_HU_3 0x00080000U
+#define RTC_TR_MNT 0x00007000U
+#define RTC_TR_MNT_0 0x00001000U
+#define RTC_TR_MNT_1 0x00002000U
+#define RTC_TR_MNT_2 0x00004000U
+#define RTC_TR_MNU 0x00000F00U
+#define RTC_TR_MNU_0 0x00000100U
+#define RTC_TR_MNU_1 0x00000200U
+#define RTC_TR_MNU_2 0x00000400U
+#define RTC_TR_MNU_3 0x00000800U
+#define RTC_TR_ST 0x00000070U
+#define RTC_TR_ST_0 0x00000010U
+#define RTC_TR_ST_1 0x00000020U
+#define RTC_TR_ST_2 0x00000040U
+#define RTC_TR_SU 0x0000000FU
+#define RTC_TR_SU_0 0x00000001U
+#define RTC_TR_SU_1 0x00000002U
+#define RTC_TR_SU_2 0x00000004U
+#define RTC_TR_SU_3 0x00000008U
+
+/******************** Bits definition for RTC_DR register *******************/
+#define RTC_DR_YT 0x00F00000U
+#define RTC_DR_YT_0 0x00100000U
+#define RTC_DR_YT_1 0x00200000U
+#define RTC_DR_YT_2 0x00400000U
+#define RTC_DR_YT_3 0x00800000U
+#define RTC_DR_YU 0x000F0000U
+#define RTC_DR_YU_0 0x00010000U
+#define RTC_DR_YU_1 0x00020000U
+#define RTC_DR_YU_2 0x00040000U
+#define RTC_DR_YU_3 0x00080000U
+#define RTC_DR_WDU 0x0000E000U
+#define RTC_DR_WDU_0 0x00002000U
+#define RTC_DR_WDU_1 0x00004000U
+#define RTC_DR_WDU_2 0x00008000U
+#define RTC_DR_MT 0x00001000U
+#define RTC_DR_MU 0x00000F00U
+#define RTC_DR_MU_0 0x00000100U
+#define RTC_DR_MU_1 0x00000200U
+#define RTC_DR_MU_2 0x00000400U
+#define RTC_DR_MU_3 0x00000800U
+#define RTC_DR_DT 0x00000030U
+#define RTC_DR_DT_0 0x00000010U
+#define RTC_DR_DT_1 0x00000020U
+#define RTC_DR_DU 0x0000000FU
+#define RTC_DR_DU_0 0x00000001U
+#define RTC_DR_DU_1 0x00000002U
+#define RTC_DR_DU_2 0x00000004U
+#define RTC_DR_DU_3 0x00000008U
+
+/******************** Bits definition for RTC_CR register *******************/
+#define RTC_CR_COE 0x00800000U
+#define RTC_CR_OSEL 0x00600000U
+#define RTC_CR_OSEL_0 0x00200000U
+#define RTC_CR_OSEL_1 0x00400000U
+#define RTC_CR_POL 0x00100000U
+#define RTC_CR_COSEL 0x00080000U
+#define RTC_CR_BCK 0x00040000U
+#define RTC_CR_SUB1H 0x00020000U
+#define RTC_CR_ADD1H 0x00010000U
+#define RTC_CR_TSIE 0x00008000U
+#define RTC_CR_WUTIE 0x00004000U
+#define RTC_CR_ALRBIE 0x00002000U
+#define RTC_CR_ALRAIE 0x00001000U
+#define RTC_CR_TSE 0x00000800U
+#define RTC_CR_WUTE 0x00000400U
+#define RTC_CR_ALRBE 0x00000200U
+#define RTC_CR_ALRAE 0x00000100U
+#define RTC_CR_DCE 0x00000080U
+#define RTC_CR_FMT 0x00000040U
+#define RTC_CR_BYPSHAD 0x00000020U
+#define RTC_CR_REFCKON 0x00000010U
+#define RTC_CR_TSEDGE 0x00000008U
+#define RTC_CR_WUCKSEL 0x00000007U
+#define RTC_CR_WUCKSEL_0 0x00000001U
+#define RTC_CR_WUCKSEL_1 0x00000002U
+#define RTC_CR_WUCKSEL_2 0x00000004U
+
+/******************** Bits definition for RTC_ISR register ******************/
+#define RTC_ISR_RECALPF 0x00010000U
+#define RTC_ISR_TAMP1F 0x00002000U
+#define RTC_ISR_TAMP2F 0x00004000U
+#define RTC_ISR_TSOVF 0x00001000U
+#define RTC_ISR_TSF 0x00000800U
+#define RTC_ISR_WUTF 0x00000400U
+#define RTC_ISR_ALRBF 0x00000200U
+#define RTC_ISR_ALRAF 0x00000100U
+#define RTC_ISR_INIT 0x00000080U
+#define RTC_ISR_INITF 0x00000040U
+#define RTC_ISR_RSF 0x00000020U
+#define RTC_ISR_INITS 0x00000010U
+#define RTC_ISR_SHPF 0x00000008U
+#define RTC_ISR_WUTWF 0x00000004U
+#define RTC_ISR_ALRBWF 0x00000002U
+#define RTC_ISR_ALRAWF 0x00000001U
+
+/******************** Bits definition for RTC_PRER register *****************/
+#define RTC_PRER_PREDIV_A 0x007F0000U
+#define RTC_PRER_PREDIV_S 0x00007FFFU
+
+/******************** Bits definition for RTC_WUTR register *****************/
+#define RTC_WUTR_WUT 0x0000FFFFU
+
+/******************** Bits definition for RTC_CALIBR register ***************/
+#define RTC_CALIBR_DCS 0x00000080U
+#define RTC_CALIBR_DC 0x0000001FU
+
+/******************** Bits definition for RTC_ALRMAR register ***************/
+#define RTC_ALRMAR_MSK4 0x80000000U
+#define RTC_ALRMAR_WDSEL 0x40000000U
+#define RTC_ALRMAR_DT 0x30000000U
+#define RTC_ALRMAR_DT_0 0x10000000U
+#define RTC_ALRMAR_DT_1 0x20000000U
+#define RTC_ALRMAR_DU 0x0F000000U
+#define RTC_ALRMAR_DU_0 0x01000000U
+#define RTC_ALRMAR_DU_1 0x02000000U
+#define RTC_ALRMAR_DU_2 0x04000000U
+#define RTC_ALRMAR_DU_3 0x08000000U
+#define RTC_ALRMAR_MSK3 0x00800000U
+#define RTC_ALRMAR_PM 0x00400000U
+#define RTC_ALRMAR_HT 0x00300000U
+#define RTC_ALRMAR_HT_0 0x00100000U
+#define RTC_ALRMAR_HT_1 0x00200000U
+#define RTC_ALRMAR_HU 0x000F0000U
+#define RTC_ALRMAR_HU_0 0x00010000U
+#define RTC_ALRMAR_HU_1 0x00020000U
+#define RTC_ALRMAR_HU_2 0x00040000U
+#define RTC_ALRMAR_HU_3 0x00080000U
+#define RTC_ALRMAR_MSK2 0x00008000U
+#define RTC_ALRMAR_MNT 0x00007000U
+#define RTC_ALRMAR_MNT_0 0x00001000U
+#define RTC_ALRMAR_MNT_1 0x00002000U
+#define RTC_ALRMAR_MNT_2 0x00004000U
+#define RTC_ALRMAR_MNU 0x00000F00U
+#define RTC_ALRMAR_MNU_0 0x00000100U
+#define RTC_ALRMAR_MNU_1 0x00000200U
+#define RTC_ALRMAR_MNU_2 0x00000400U
+#define RTC_ALRMAR_MNU_3 0x00000800U
+#define RTC_ALRMAR_MSK1 0x00000080U
+#define RTC_ALRMAR_ST 0x00000070U
+#define RTC_ALRMAR_ST_0 0x00000010U
+#define RTC_ALRMAR_ST_1 0x00000020U
+#define RTC_ALRMAR_ST_2 0x00000040U
+#define RTC_ALRMAR_SU 0x0000000FU
+#define RTC_ALRMAR_SU_0 0x00000001U
+#define RTC_ALRMAR_SU_1 0x00000002U
+#define RTC_ALRMAR_SU_2 0x00000004U
+#define RTC_ALRMAR_SU_3 0x00000008U
+
+/******************** Bits definition for RTC_ALRMBR register ***************/
+#define RTC_ALRMBR_MSK4 0x80000000U
+#define RTC_ALRMBR_WDSEL 0x40000000U
+#define RTC_ALRMBR_DT 0x30000000U
+#define RTC_ALRMBR_DT_0 0x10000000U
+#define RTC_ALRMBR_DT_1 0x20000000U
+#define RTC_ALRMBR_DU 0x0F000000U
+#define RTC_ALRMBR_DU_0 0x01000000U
+#define RTC_ALRMBR_DU_1 0x02000000U
+#define RTC_ALRMBR_DU_2 0x04000000U
+#define RTC_ALRMBR_DU_3 0x08000000U
+#define RTC_ALRMBR_MSK3 0x00800000U
+#define RTC_ALRMBR_PM 0x00400000U
+#define RTC_ALRMBR_HT 0x00300000U
+#define RTC_ALRMBR_HT_0 0x00100000U
+#define RTC_ALRMBR_HT_1 0x00200000U
+#define RTC_ALRMBR_HU 0x000F0000U
+#define RTC_ALRMBR_HU_0 0x00010000U
+#define RTC_ALRMBR_HU_1 0x00020000U
+#define RTC_ALRMBR_HU_2 0x00040000U
+#define RTC_ALRMBR_HU_3 0x00080000U
+#define RTC_ALRMBR_MSK2 0x00008000U
+#define RTC_ALRMBR_MNT 0x00007000U
+#define RTC_ALRMBR_MNT_0 0x00001000U
+#define RTC_ALRMBR_MNT_1 0x00002000U
+#define RTC_ALRMBR_MNT_2 0x00004000U
+#define RTC_ALRMBR_MNU 0x00000F00U
+#define RTC_ALRMBR_MNU_0 0x00000100U
+#define RTC_ALRMBR_MNU_1 0x00000200U
+#define RTC_ALRMBR_MNU_2 0x00000400U
+#define RTC_ALRMBR_MNU_3 0x00000800U
+#define RTC_ALRMBR_MSK1 0x00000080U
+#define RTC_ALRMBR_ST 0x00000070U
+#define RTC_ALRMBR_ST_0 0x00000010U
+#define RTC_ALRMBR_ST_1 0x00000020U
+#define RTC_ALRMBR_ST_2 0x00000040U
+#define RTC_ALRMBR_SU 0x0000000FU
+#define RTC_ALRMBR_SU_0 0x00000001U
+#define RTC_ALRMBR_SU_1 0x00000002U
+#define RTC_ALRMBR_SU_2 0x00000004U
+#define RTC_ALRMBR_SU_3 0x00000008U
+
+/******************** Bits definition for RTC_WPR register ******************/
+#define RTC_WPR_KEY 0x000000FFU
+
+/******************** Bits definition for RTC_SSR register ******************/
+#define RTC_SSR_SS 0x0000FFFFU
+
+/******************** Bits definition for RTC_SHIFTR register ***************/
+#define RTC_SHIFTR_SUBFS 0x00007FFFU
+#define RTC_SHIFTR_ADD1S 0x80000000U
+
+/******************** Bits definition for RTC_TSTR register *****************/
+#define RTC_TSTR_PM 0x00400000U
+#define RTC_TSTR_HT 0x00300000U
+#define RTC_TSTR_HT_0 0x00100000U
+#define RTC_TSTR_HT_1 0x00200000U
+#define RTC_TSTR_HU 0x000F0000U
+#define RTC_TSTR_HU_0 0x00010000U
+#define RTC_TSTR_HU_1 0x00020000U
+#define RTC_TSTR_HU_2 0x00040000U
+#define RTC_TSTR_HU_3 0x00080000U
+#define RTC_TSTR_MNT 0x00007000U
+#define RTC_TSTR_MNT_0 0x00001000U
+#define RTC_TSTR_MNT_1 0x00002000U
+#define RTC_TSTR_MNT_2 0x00004000U
+#define RTC_TSTR_MNU 0x00000F00U
+#define RTC_TSTR_MNU_0 0x00000100U
+#define RTC_TSTR_MNU_1 0x00000200U
+#define RTC_TSTR_MNU_2 0x00000400U
+#define RTC_TSTR_MNU_3 0x00000800U
+#define RTC_TSTR_ST 0x00000070U
+#define RTC_TSTR_ST_0 0x00000010U
+#define RTC_TSTR_ST_1 0x00000020U
+#define RTC_TSTR_ST_2 0x00000040U
+#define RTC_TSTR_SU 0x0000000FU
+#define RTC_TSTR_SU_0 0x00000001U
+#define RTC_TSTR_SU_1 0x00000002U
+#define RTC_TSTR_SU_2 0x00000004U
+#define RTC_TSTR_SU_3 0x00000008U
+
+/******************** Bits definition for RTC_TSDR register *****************/
+#define RTC_TSDR_WDU 0x0000E000U
+#define RTC_TSDR_WDU_0 0x00002000U
+#define RTC_TSDR_WDU_1 0x00004000U
+#define RTC_TSDR_WDU_2 0x00008000U
+#define RTC_TSDR_MT 0x00001000U
+#define RTC_TSDR_MU 0x00000F00U
+#define RTC_TSDR_MU_0 0x00000100U
+#define RTC_TSDR_MU_1 0x00000200U
+#define RTC_TSDR_MU_2 0x00000400U
+#define RTC_TSDR_MU_3 0x00000800U
+#define RTC_TSDR_DT 0x00000030U
+#define RTC_TSDR_DT_0 0x00000010U
+#define RTC_TSDR_DT_1 0x00000020U
+#define RTC_TSDR_DU 0x0000000FU
+#define RTC_TSDR_DU_0 0x00000001U
+#define RTC_TSDR_DU_1 0x00000002U
+#define RTC_TSDR_DU_2 0x00000004U
+#define RTC_TSDR_DU_3 0x00000008U
+
+/******************** Bits definition for RTC_TSSSR register ****************/
+#define RTC_TSSSR_SS 0x0000FFFFU
+
+/******************** Bits definition for RTC_CAL register *****************/
+#define RTC_CALR_CALP 0x00008000U
+#define RTC_CALR_CALW8 0x00004000U
+#define RTC_CALR_CALW16 0x00002000U
+#define RTC_CALR_CALM 0x000001FFU
+#define RTC_CALR_CALM_0 0x00000001U
+#define RTC_CALR_CALM_1 0x00000002U
+#define RTC_CALR_CALM_2 0x00000004U
+#define RTC_CALR_CALM_3 0x00000008U
+#define RTC_CALR_CALM_4 0x00000010U
+#define RTC_CALR_CALM_5 0x00000020U
+#define RTC_CALR_CALM_6 0x00000040U
+#define RTC_CALR_CALM_7 0x00000080U
+#define RTC_CALR_CALM_8 0x00000100U
+
+/******************** Bits definition for RTC_TAFCR register ****************/
+#define RTC_TAFCR_ALARMOUTTYPE 0x00040000U
+#define RTC_TAFCR_TSINSEL 0x00020000U
+#define RTC_TAFCR_TAMPINSEL 0x00010000U
+#define RTC_TAFCR_TAMPPUDIS 0x00008000U
+#define RTC_TAFCR_TAMPPRCH 0x00006000U
+#define RTC_TAFCR_TAMPPRCH_0 0x00002000U
+#define RTC_TAFCR_TAMPPRCH_1 0x00004000U
+#define RTC_TAFCR_TAMPFLT 0x00001800U
+#define RTC_TAFCR_TAMPFLT_0 0x00000800U
+#define RTC_TAFCR_TAMPFLT_1 0x00001000U
+#define RTC_TAFCR_TAMPFREQ 0x00000700U
+#define RTC_TAFCR_TAMPFREQ_0 0x00000100U
+#define RTC_TAFCR_TAMPFREQ_1 0x00000200U
+#define RTC_TAFCR_TAMPFREQ_2 0x00000400U
+#define RTC_TAFCR_TAMPTS 0x00000080U
+#define RTC_TAFCR_TAMP2TRG 0x00000010U
+#define RTC_TAFCR_TAMP2E 0x00000008U
+#define RTC_TAFCR_TAMPIE 0x00000004U
+#define RTC_TAFCR_TAMP1TRG 0x00000002U
+#define RTC_TAFCR_TAMP1E 0x00000001U
+
+/******************** Bits definition for RTC_ALRMASSR register *************/
+#define RTC_ALRMASSR_MASKSS 0x0F000000U
+#define RTC_ALRMASSR_MASKSS_0 0x01000000U
+#define RTC_ALRMASSR_MASKSS_1 0x02000000U
+#define RTC_ALRMASSR_MASKSS_2 0x04000000U
+#define RTC_ALRMASSR_MASKSS_3 0x08000000U
+#define RTC_ALRMASSR_SS 0x00007FFFU
+
+/******************** Bits definition for RTC_ALRMBSSR register *************/
+#define RTC_ALRMBSSR_MASKSS 0x0F000000U
+#define RTC_ALRMBSSR_MASKSS_0 0x01000000U
+#define RTC_ALRMBSSR_MASKSS_1 0x02000000U
+#define RTC_ALRMBSSR_MASKSS_2 0x04000000U
+#define RTC_ALRMBSSR_MASKSS_3 0x08000000U
+#define RTC_ALRMBSSR_SS 0x00007FFFU
+
+/******************** Bits definition for RTC_BKP0R register ****************/
+#define RTC_BKP0R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP1R register ****************/
+#define RTC_BKP1R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP2R register ****************/
+#define RTC_BKP2R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP3R register ****************/
+#define RTC_BKP3R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP4R register ****************/
+#define RTC_BKP4R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP5R register ****************/
+#define RTC_BKP5R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP6R register ****************/
+#define RTC_BKP6R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP7R register ****************/
+#define RTC_BKP7R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP8R register ****************/
+#define RTC_BKP8R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP9R register ****************/
+#define RTC_BKP9R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP10R register ***************/
+#define RTC_BKP10R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP11R register ***************/
+#define RTC_BKP11R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP12R register ***************/
+#define RTC_BKP12R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP13R register ***************/
+#define RTC_BKP13R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP14R register ***************/
+#define RTC_BKP14R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP15R register ***************/
+#define RTC_BKP15R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP16R register ***************/
+#define RTC_BKP16R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP17R register ***************/
+#define RTC_BKP17R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP18R register ***************/
+#define RTC_BKP18R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP19R register ***************/
+#define RTC_BKP19R 0xFFFFFFFFU
+
+/******************************************************************************/
+/* */
+/* Serial Audio Interface */
+/* */
+/******************************************************************************/
+/******************** Bit definition for SAI_GCR register *******************/
+#define SAI_GCR_SYNCIN 0x00000003U /*!<SYNCIN[1:0] bits (Synchronization Inputs) */
+#define SAI_GCR_SYNCIN_0 0x00000001U /*!<Bit 0 */
+#define SAI_GCR_SYNCIN_1 0x00000002U /*!<Bit 1 */
+
+#define SAI_GCR_SYNCOUT 0x00000030U /*!<SYNCOUT[1:0] bits (Synchronization Outputs) */
+#define SAI_GCR_SYNCOUT_0 0x00000010U /*!<Bit 0 */
+#define SAI_GCR_SYNCOUT_1 0x00000020U /*!<Bit 1 */
+
+/******************* Bit definition for SAI_xCR1 register *******************/
+#define SAI_xCR1_MODE 0x00000003U /*!<MODE[1:0] bits (Audio Block Mode) */
+#define SAI_xCR1_MODE_0 0x00000001U /*!<Bit 0 */
+#define SAI_xCR1_MODE_1 0x00000002U /*!<Bit 1 */
+
+#define SAI_xCR1_PRTCFG 0x0000000CU /*!<PRTCFG[1:0] bits (Protocol Configuration) */
+#define SAI_xCR1_PRTCFG_0 0x00000004U /*!<Bit 0 */
+#define SAI_xCR1_PRTCFG_1 0x00000008U /*!<Bit 1 */
+
+#define SAI_xCR1_DS 0x000000E0U /*!<DS[1:0] bits (Data Size) */
+#define SAI_xCR1_DS_0 0x00000020U /*!<Bit 0 */
+#define SAI_xCR1_DS_1 0x00000040U /*!<Bit 1 */
+#define SAI_xCR1_DS_2 0x00000080U /*!<Bit 2 */
+
+#define SAI_xCR1_LSBFIRST 0x00000100U /*!<LSB First Configuration */
+#define SAI_xCR1_CKSTR 0x00000200U /*!<ClocK STRobing edge */
+
+#define SAI_xCR1_SYNCEN 0x00000C00U /*!<SYNCEN[1:0](SYNChronization ENable) */
+#define SAI_xCR1_SYNCEN_0 0x00000400U /*!<Bit 0 */
+#define SAI_xCR1_SYNCEN_1 0x00000800U /*!<Bit 1 */
+
+#define SAI_xCR1_MONO 0x00001000U /*!<Mono mode */
+#define SAI_xCR1_OUTDRIV 0x00002000U /*!<Output Drive */
+#define SAI_xCR1_SAIEN 0x00010000U /*!<Audio Block enable */
+#define SAI_xCR1_DMAEN 0x00020000U /*!<DMA enable */
+#define SAI_xCR1_NODIV 0x00080000U /*!<No Divider Configuration */
+
+#define SAI_xCR1_MCKDIV 0x00F00000U /*!<MCKDIV[3:0] (Master ClocK Divider) */
+#define SAI_xCR1_MCKDIV_0 0x00100000U /*!<Bit 0 */
+#define SAI_xCR1_MCKDIV_1 0x00200000U /*!<Bit 1 */
+#define SAI_xCR1_MCKDIV_2 0x00400000U /*!<Bit 2 */
+#define SAI_xCR1_MCKDIV_3 0x00800000U /*!<Bit 3 */
+
+/******************* Bit definition for SAI_xCR2 register *******************/
+#define SAI_xCR2_FTH 0x00000007U /*!<FTH[2:0](Fifo THreshold) */
+#define SAI_xCR2_FTH_0 0x00000001U /*!<Bit 0 */
+#define SAI_xCR2_FTH_1 0x00000002U /*!<Bit 1 */
+#define SAI_xCR2_FTH_2 0x00000004U /*!<Bit 2 */
+
+#define SAI_xCR2_FFLUSH 0x00000008U /*!<Fifo FLUSH */
+#define SAI_xCR2_TRIS 0x00000010U /*!<TRIState Management on data line */
+#define SAI_xCR2_MUTE 0x00000020U /*!<Mute mode */
+#define SAI_xCR2_MUTEVAL 0x00000040U /*!<Muate value */
+
+#define SAI_xCR2_MUTECNT 0x00001F80U /*!<MUTECNT[5:0] (MUTE counter) */
+#define SAI_xCR2_MUTECNT_0 0x00000080U /*!<Bit 0 */
+#define SAI_xCR2_MUTECNT_1 0x00000100U /*!<Bit 1 */
+#define SAI_xCR2_MUTECNT_2 0x00000200U /*!<Bit 2 */
+#define SAI_xCR2_MUTECNT_3 0x00000400U /*!<Bit 3 */
+#define SAI_xCR2_MUTECNT_4 0x00000800U /*!<Bit 4 */
+#define SAI_xCR2_MUTECNT_5 0x00001000U /*!<Bit 5 */
+
+#define SAI_xCR2_CPL 0x00002000U /*!< Complement Bit */
+
+#define SAI_xCR2_COMP 0x0000C000U /*!<COMP[1:0] (Companding mode) */
+#define SAI_xCR2_COMP_0 0x00004000U /*!<Bit 0 */
+#define SAI_xCR2_COMP_1 0x00008000U /*!<Bit 1 */
+
+/****************** Bit definition for SAI_xFRCR register *******************/
+#define SAI_xFRCR_FRL 0x000000FFU /*!<FRL[1:0](Frame length) */
+#define SAI_xFRCR_FRL_0 0x00000001U /*!<Bit 0 */
+#define SAI_xFRCR_FRL_1 0x00000002U /*!<Bit 1 */
+#define SAI_xFRCR_FRL_2 0x00000004U /*!<Bit 2 */
+#define SAI_xFRCR_FRL_3 0x00000008U /*!<Bit 3 */
+#define SAI_xFRCR_FRL_4 0x00000010U /*!<Bit 4 */
+#define SAI_xFRCR_FRL_5 0x00000020U /*!<Bit 5 */
+#define SAI_xFRCR_FRL_6 0x00000040U /*!<Bit 6 */
+#define SAI_xFRCR_FRL_7 0x00000080U /*!<Bit 7 */
+
+#define SAI_xFRCR_FSALL 0x00007F00U /*!<FRL[1:0] (Frame synchronization active level length) */
+#define SAI_xFRCR_FSALL_0 0x00000100U /*!<Bit 0 */
+#define SAI_xFRCR_FSALL_1 0x00000200U /*!<Bit 1 */
+#define SAI_xFRCR_FSALL_2 0x00000400U /*!<Bit 2 */
+#define SAI_xFRCR_FSALL_3 0x00000800U /*!<Bit 3 */
+#define SAI_xFRCR_FSALL_4 0x00001000U /*!<Bit 4 */
+#define SAI_xFRCR_FSALL_5 0x00002000U /*!<Bit 5 */
+#define SAI_xFRCR_FSALL_6 0x00004000U /*!<Bit 6 */
+
+#define SAI_xFRCR_FSDEF 0x00010000U /*!< Frame Synchronization Definition */
+#define SAI_xFRCR_FSPOL 0x00020000U /*!<Frame Synchronization POLarity */
+#define SAI_xFRCR_FSOFF 0x00040000U /*!<Frame Synchronization OFFset */
+/* Legacy defines */
+#define SAI_xFRCR_FSPO SAI_xFRCR_FSPOL
+
+/****************** Bit definition for SAI_xSLOTR register *******************/
+#define SAI_xSLOTR_FBOFF 0x0000001FU /*!<FRL[4:0](First Bit Offset) */
+#define SAI_xSLOTR_FBOFF_0 0x00000001U /*!<Bit 0 */
+#define SAI_xSLOTR_FBOFF_1 0x00000002U /*!<Bit 1 */
+#define SAI_xSLOTR_FBOFF_2 0x00000004U /*!<Bit 2 */
+#define SAI_xSLOTR_FBOFF_3 0x00000008U /*!<Bit 3 */
+#define SAI_xSLOTR_FBOFF_4 0x00000010U /*!<Bit 4 */
+
+#define SAI_xSLOTR_SLOTSZ 0x000000C0U /*!<SLOTSZ[1:0] (Slot size) */
+#define SAI_xSLOTR_SLOTSZ_0 0x00000040U /*!<Bit 0 */
+#define SAI_xSLOTR_SLOTSZ_1 0x00000080U /*!<Bit 1 */
+
+#define SAI_xSLOTR_NBSLOT 0x00000F00U /*!<NBSLOT[3:0] (Number of Slot in audio Frame) */
+#define SAI_xSLOTR_NBSLOT_0 0x00000100U /*!<Bit 0 */
+#define SAI_xSLOTR_NBSLOT_1 0x00000200U /*!<Bit 1 */
+#define SAI_xSLOTR_NBSLOT_2 0x00000400U /*!<Bit 2 */
+#define SAI_xSLOTR_NBSLOT_3 0x00000800U /*!<Bit 3 */
+
+#define SAI_xSLOTR_SLOTEN 0xFFFF0000U /*!<SLOTEN[15:0] (Slot Enable) */
+
+/******************* Bit definition for SAI_xIMR register *******************/
+#define SAI_xIMR_OVRUDRIE 0x00000001U /*!<Overrun underrun interrupt enable */
+#define SAI_xIMR_MUTEDETIE 0x00000002U /*!<Mute detection interrupt enable */
+#define SAI_xIMR_WCKCFGIE 0x00000004U /*!<Wrong Clock Configuration interrupt enable */
+#define SAI_xIMR_FREQIE 0x00000008U /*!<FIFO request interrupt enable */
+#define SAI_xIMR_CNRDYIE 0x00000010U /*!<Codec not ready interrupt enable */
+#define SAI_xIMR_AFSDETIE 0x00000020U /*!<Anticipated frame synchronization detection interrupt enable */
+#define SAI_xIMR_LFSDETIE 0x00000040U /*!<Late frame synchronization detection interrupt enable */
+
+/******************** Bit definition for SAI_xSR register *******************/
+#define SAI_xSR_OVRUDR 0x00000001U /*!<Overrun underrun */
+#define SAI_xSR_MUTEDET 0x00000002U /*!<Mute detection */
+#define SAI_xSR_WCKCFG 0x00000004U /*!<Wrong Clock Configuration */
+#define SAI_xSR_FREQ 0x00000008U /*!<FIFO request */
+#define SAI_xSR_CNRDY 0x00000010U /*!<Codec not ready */
+#define SAI_xSR_AFSDET 0x00000020U /*!<Anticipated frame synchronization detection */
+#define SAI_xSR_LFSDET 0x00000040U /*!<Late frame synchronization detection */
+
+#define SAI_xSR_FLVL 0x00070000U /*!<FLVL[2:0] (FIFO Level Threshold) */
+#define SAI_xSR_FLVL_0 0x00010000U /*!<Bit 0 */
+#define SAI_xSR_FLVL_1 0x00020000U /*!<Bit 1 */
+#define SAI_xSR_FLVL_2 0x00040000U /*!<Bit 2 */
+
+/****************** Bit definition for SAI_xCLRFR register ******************/
+#define SAI_xCLRFR_COVRUDR 0x00000001U /*!<Clear Overrun underrun */
+#define SAI_xCLRFR_CMUTEDET 0x00000002U /*!<Clear Mute detection */
+#define SAI_xCLRFR_CWCKCFG 0x00000004U /*!<Clear Wrong Clock Configuration */
+#define SAI_xCLRFR_CFREQ 0x00000008U /*!<Clear FIFO request */
+#define SAI_xCLRFR_CCNRDY 0x00000010U /*!<Clear Codec not ready */
+#define SAI_xCLRFR_CAFSDET 0x00000020U /*!<Clear Anticipated frame synchronization detection */
+#define SAI_xCLRFR_CLFSDET 0x00000040U /*!<Clear Late frame synchronization detection */
+
+/****************** Bit definition for SAI_xDR register ******************/
+#define SAI_xDR_DATA 0xFFFFFFFFU
+
+
+/******************************************************************************/
+/* */
+/* SD host Interface */
+/* */
+/******************************************************************************/
+/****************** Bit definition for SDIO_POWER register ******************/
+#define SDIO_POWER_PWRCTRL 0x03U /*!<PWRCTRL[1:0] bits (Power supply control bits) */
+#define SDIO_POWER_PWRCTRL_0 0x01U /*!<Bit 0 */
+#define SDIO_POWER_PWRCTRL_1 0x02U /*!<Bit 1 */
+
+/****************** Bit definition for SDIO_CLKCR register ******************/
+#define SDIO_CLKCR_CLKDIV 0x00FFU /*!<Clock divide factor */
+#define SDIO_CLKCR_CLKEN 0x0100U /*!<Clock enable bit */
+#define SDIO_CLKCR_PWRSAV 0x0200U /*!<Power saving configuration bit */
+#define SDIO_CLKCR_BYPASS 0x0400U /*!<Clock divider bypass enable bit */
+
+#define SDIO_CLKCR_WIDBUS 0x1800U /*!<WIDBUS[1:0] bits (Wide bus mode enable bit) */
+#define SDIO_CLKCR_WIDBUS_0 0x0800U /*!<Bit 0 */
+#define SDIO_CLKCR_WIDBUS_1 0x1000U /*!<Bit 1 */
+
+#define SDIO_CLKCR_NEGEDGE 0x2000U /*!<SDIO_CK dephasing selection bit */
+#define SDIO_CLKCR_HWFC_EN 0x4000U /*!<HW Flow Control enable */
+
+/******************* Bit definition for SDIO_ARG register *******************/
+#define SDIO_ARG_CMDARG 0xFFFFFFFFU /*!<Command argument */
+
+/******************* Bit definition for SDIO_CMD register *******************/
+#define SDIO_CMD_CMDINDEX 0x003FU /*!<Command Index */
+
+#define SDIO_CMD_WAITRESP 0x00C0U /*!<WAITRESP[1:0] bits (Wait for response bits) */
+#define SDIO_CMD_WAITRESP_0 0x0040U /*!< Bit 0 */
+#define SDIO_CMD_WAITRESP_1 0x0080U /*!< Bit 1 */
+
+#define SDIO_CMD_WAITINT 0x0100U /*!<CPSM Waits for Interrupt Request */
+#define SDIO_CMD_WAITPEND 0x0200U /*!<CPSM Waits for ends of data transfer (CmdPend internal signal) */
+#define SDIO_CMD_CPSMEN 0x0400U /*!<Command path state machine (CPSM) Enable bit */
+#define SDIO_CMD_SDIOSUSPEND 0x0800U /*!<SD I/O suspend command */
+#define SDIO_CMD_ENCMDCOMPL 0x1000U /*!<Enable CMD completion */
+#define SDIO_CMD_NIEN 0x2000U /*!<Not Interrupt Enable */
+#define SDIO_CMD_CEATACMD 0x4000U /*!<CE-ATA command */
+
+/***************** Bit definition for SDIO_RESPCMD register *****************/
+#define SDIO_RESPCMD_RESPCMD 0x3FU /*!<Response command index */
+
+/****************** Bit definition for SDIO_RESP0 register ******************/
+#define SDIO_RESP0_CARDSTATUS0 0xFFFFFFFFU /*!<Card Status */
+
+/****************** Bit definition for SDIO_RESP1 register ******************/
+#define SDIO_RESP1_CARDSTATUS1 0xFFFFFFFFU /*!<Card Status */
+
+/****************** Bit definition for SDIO_RESP2 register ******************/
+#define SDIO_RESP2_CARDSTATUS2 0xFFFFFFFFU /*!<Card Status */
+
+/****************** Bit definition for SDIO_RESP3 register ******************/
+#define SDIO_RESP3_CARDSTATUS3 0xFFFFFFFFU /*!<Card Status */
+
+/****************** Bit definition for SDIO_RESP4 register ******************/
+#define SDIO_RESP4_CARDSTATUS4 0xFFFFFFFFU /*!<Card Status */
+
+/****************** Bit definition for SDIO_DTIMER register *****************/
+#define SDIO_DTIMER_DATATIME 0xFFFFFFFFU /*!<Data timeout period. */
+
+/****************** Bit definition for SDIO_DLEN register *******************/
+#define SDIO_DLEN_DATALENGTH 0x01FFFFFFU /*!<Data length value */
+
+/****************** Bit definition for SDIO_DCTRL register ******************/
+#define SDIO_DCTRL_DTEN 0x0001U /*!<Data transfer enabled bit */
+#define SDIO_DCTRL_DTDIR 0x0002U /*!<Data transfer direction selection */
+#define SDIO_DCTRL_DTMODE 0x0004U /*!<Data transfer mode selection */
+#define SDIO_DCTRL_DMAEN 0x0008U /*!<DMA enabled bit */
+
+#define SDIO_DCTRL_DBLOCKSIZE 0x00F0U /*!<DBLOCKSIZE[3:0] bits (Data block size) */
+#define SDIO_DCTRL_DBLOCKSIZE_0 0x0010U /*!<Bit 0 */
+#define SDIO_DCTRL_DBLOCKSIZE_1 0x0020U /*!<Bit 1 */
+#define SDIO_DCTRL_DBLOCKSIZE_2 0x0040U /*!<Bit 2 */
+#define SDIO_DCTRL_DBLOCKSIZE_3 0x0080U /*!<Bit 3 */
+
+#define SDIO_DCTRL_RWSTART 0x0100U /*!<Read wait start */
+#define SDIO_DCTRL_RWSTOP 0x0200U /*!<Read wait stop */
+#define SDIO_DCTRL_RWMOD 0x0400U /*!<Read wait mode */
+#define SDIO_DCTRL_SDIOEN 0x0800U /*!<SD I/O enable functions */
+
+/****************** Bit definition for SDIO_DCOUNT register *****************/
+#define SDIO_DCOUNT_DATACOUNT 0x01FFFFFFU /*!<Data count value */
+
+/****************** Bit definition for SDIO_STA register ********************/
+#define SDIO_STA_CCRCFAIL 0x00000001U /*!<Command response received (CRC check failed) */
+#define SDIO_STA_DCRCFAIL 0x00000002U /*!<Data block sent/received (CRC check failed) */
+#define SDIO_STA_CTIMEOUT 0x00000004U /*!<Command response timeout */
+#define SDIO_STA_DTIMEOUT 0x00000008U /*!<Data timeout */
+#define SDIO_STA_TXUNDERR 0x00000010U /*!<Transmit FIFO underrun error */
+#define SDIO_STA_RXOVERR 0x00000020U /*!<Received FIFO overrun error */
+#define SDIO_STA_CMDREND 0x00000040U /*!<Command response received (CRC check passed) */
+#define SDIO_STA_CMDSENT 0x00000080U /*!<Command sent (no response required) */
+#define SDIO_STA_DATAEND 0x00000100U /*!<Data end (data counter, SDIDCOUNT, is zero) */
+#define SDIO_STA_STBITERR 0x00000200U /*!<Start bit not detected on all data signals in wide bus mode */
+#define SDIO_STA_DBCKEND 0x00000400U /*!<Data block sent/received (CRC check passed) */
+#define SDIO_STA_CMDACT 0x00000800U /*!<Command transfer in progress */
+#define SDIO_STA_TXACT 0x00001000U /*!<Data transmit in progress */
+#define SDIO_STA_RXACT 0x00002000U /*!<Data receive in progress */
+#define SDIO_STA_TXFIFOHE 0x00004000U /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
+#define SDIO_STA_RXFIFOHF 0x00008000U /*!<Receive FIFO Half Full: there are at least 8 words in the FIFO */
+#define SDIO_STA_TXFIFOF 0x00010000U /*!<Transmit FIFO full */
+#define SDIO_STA_RXFIFOF 0x00020000U /*!<Receive FIFO full */
+#define SDIO_STA_TXFIFOE 0x00040000U /*!<Transmit FIFO empty */
+#define SDIO_STA_RXFIFOE 0x00080000U /*!<Receive FIFO empty */
+#define SDIO_STA_TXDAVL 0x00100000U /*!<Data available in transmit FIFO */
+#define SDIO_STA_RXDAVL 0x00200000U /*!<Data available in receive FIFO */
+#define SDIO_STA_SDIOIT 0x00400000U /*!<SDIO interrupt received */
+#define SDIO_STA_CEATAEND 0x00800000U /*!<CE-ATA command completion signal received for CMD61 */
+
+/******************* Bit definition for SDIO_ICR register *******************/
+#define SDIO_ICR_CCRCFAILC 0x00000001U /*!<CCRCFAIL flag clear bit */
+#define SDIO_ICR_DCRCFAILC 0x00000002U /*!<DCRCFAIL flag clear bit */
+#define SDIO_ICR_CTIMEOUTC 0x00000004U /*!<CTIMEOUT flag clear bit */
+#define SDIO_ICR_DTIMEOUTC 0x00000008U /*!<DTIMEOUT flag clear bit */
+#define SDIO_ICR_TXUNDERRC 0x00000010U /*!<TXUNDERR flag clear bit */
+#define SDIO_ICR_RXOVERRC 0x00000020U /*!<RXOVERR flag clear bit */
+#define SDIO_ICR_CMDRENDC 0x00000040U /*!<CMDREND flag clear bit */
+#define SDIO_ICR_CMDSENTC 0x00000080U /*!<CMDSENT flag clear bit */
+#define SDIO_ICR_DATAENDC 0x00000100U /*!<DATAEND flag clear bit */
+#define SDIO_ICR_STBITERRC 0x00000200U /*!<STBITERR flag clear bit */
+#define SDIO_ICR_DBCKENDC 0x00000400U /*!<DBCKEND flag clear bit */
+#define SDIO_ICR_SDIOITC 0x00400000U /*!<SDIOIT flag clear bit */
+#define SDIO_ICR_CEATAENDC 0x00800000U /*!<CEATAEND flag clear bit */
+
+/****************** Bit definition for SDIO_MASK register *******************/
+#define SDIO_MASK_CCRCFAILIE 0x00000001U /*!<Command CRC Fail Interrupt Enable */
+#define SDIO_MASK_DCRCFAILIE 0x00000002U /*!<Data CRC Fail Interrupt Enable */
+#define SDIO_MASK_CTIMEOUTIE 0x00000004U /*!<Command TimeOut Interrupt Enable */
+#define SDIO_MASK_DTIMEOUTIE 0x00000008U /*!<Data TimeOut Interrupt Enable */
+#define SDIO_MASK_TXUNDERRIE 0x00000010U /*!<Tx FIFO UnderRun Error Interrupt Enable */
+#define SDIO_MASK_RXOVERRIE 0x00000020U /*!<Rx FIFO OverRun Error Interrupt Enable */
+#define SDIO_MASK_CMDRENDIE 0x00000040U /*!<Command Response Received Interrupt Enable */
+#define SDIO_MASK_CMDSENTIE 0x00000080U /*!<Command Sent Interrupt Enable */
+#define SDIO_MASK_DATAENDIE 0x00000100U /*!<Data End Interrupt Enable */
+#define SDIO_MASK_STBITERRIE 0x00000200U /*!<Start Bit Error Interrupt Enable */
+#define SDIO_MASK_DBCKENDIE 0x00000400U /*!<Data Block End Interrupt Enable */
+#define SDIO_MASK_CMDACTIE 0x00000800U /*!<CCommand Acting Interrupt Enable */
+#define SDIO_MASK_TXACTIE 0x00001000U /*!<Data Transmit Acting Interrupt Enable */
+#define SDIO_MASK_RXACTIE 0x00002000U /*!<Data receive acting interrupt enabled */
+#define SDIO_MASK_TXFIFOHEIE 0x00004000U /*!<Tx FIFO Half Empty interrupt Enable */
+#define SDIO_MASK_RXFIFOHFIE 0x00008000U /*!<Rx FIFO Half Full interrupt Enable */
+#define SDIO_MASK_TXFIFOFIE 0x00010000U /*!<Tx FIFO Full interrupt Enable */
+#define SDIO_MASK_RXFIFOFIE 0x00020000U /*!<Rx FIFO Full interrupt Enable */
+#define SDIO_MASK_TXFIFOEIE 0x00040000U /*!<Tx FIFO Empty interrupt Enable */
+#define SDIO_MASK_RXFIFOEIE 0x00080000U /*!<Rx FIFO Empty interrupt Enable */
+#define SDIO_MASK_TXDAVLIE 0x00100000U /*!<Data available in Tx FIFO interrupt Enable */
+#define SDIO_MASK_RXDAVLIE 0x00200000U /*!<Data available in Rx FIFO interrupt Enable */
+#define SDIO_MASK_SDIOITIE 0x00400000U /*!<SDIO Mode Interrupt Received interrupt Enable */
+#define SDIO_MASK_CEATAENDIE 0x00800000U /*!<CE-ATA command completion signal received Interrupt Enable */
+
+/***************** Bit definition for SDIO_FIFOCNT register *****************/
+#define SDIO_FIFOCNT_FIFOCOUNT 0x00FFFFFFU /*!<Remaining number of words to be written to or read from the FIFO */
+
+/****************** Bit definition for SDIO_FIFO register *******************/
+#define SDIO_FIFO_FIFODATA 0xFFFFFFFFU /*!<Receive and transmit FIFO data */
+
+/******************************************************************************/
+/* */
+/* Serial Peripheral Interface */
+/* */
+/******************************************************************************/
+/******************* Bit definition for SPI_CR1 register ********************/
+#define SPI_CR1_CPHA 0x00000001U /*!<Clock Phase */
+#define SPI_CR1_CPOL 0x00000002U /*!<Clock Polarity */
+#define SPI_CR1_MSTR 0x00000004U /*!<Master Selection */
+
+#define SPI_CR1_BR 0x00000038U /*!<BR[2:0] bits (Baud Rate Control) */
+#define SPI_CR1_BR_0 0x00000008U /*!<Bit 0 */
+#define SPI_CR1_BR_1 0x00000010U /*!<Bit 1 */
+#define SPI_CR1_BR_2 0x00000020U /*!<Bit 2 */
+
+#define SPI_CR1_SPE 0x00000040U /*!<SPI Enable */
+#define SPI_CR1_LSBFIRST 0x00000080U /*!<Frame Format */
+#define SPI_CR1_SSI 0x00000100U /*!<Internal slave select */
+#define SPI_CR1_SSM 0x00000200U /*!<Software slave management */
+#define SPI_CR1_RXONLY 0x00000400U /*!<Receive only */
+#define SPI_CR1_DFF 0x00000800U /*!<Data Frame Format */
+#define SPI_CR1_CRCNEXT 0x00001000U /*!<Transmit CRC next */
+#define SPI_CR1_CRCEN 0x00002000U /*!<Hardware CRC calculation enable */
+#define SPI_CR1_BIDIOE 0x00004000U /*!<Output enable in bidirectional mode */
+#define SPI_CR1_BIDIMODE 0x00008000U /*!<Bidirectional data mode enable */
+
+/******************* Bit definition for SPI_CR2 register ********************/
+#define SPI_CR2_RXDMAEN 0x00000001U /*!<Rx Buffer DMA Enable */
+#define SPI_CR2_TXDMAEN 0x00000002U /*!<Tx Buffer DMA Enable */
+#define SPI_CR2_SSOE 0x00000004U /*!<SS Output Enable */
+#define SPI_CR2_FRF 0x00000010U /*!<Frame Format */
+#define SPI_CR2_ERRIE 0x00000020U /*!<Error Interrupt Enable */
+#define SPI_CR2_RXNEIE 0x00000040U /*!<RX buffer Not Empty Interrupt Enable */
+#define SPI_CR2_TXEIE 0x00000080U /*!<Tx buffer Empty Interrupt Enable */
+
+/******************** Bit definition for SPI_SR register ********************/
+#define SPI_SR_RXNE 0x00000001U /*!<Receive buffer Not Empty */
+#define SPI_SR_TXE 0x00000002U /*!<Transmit buffer Empty */
+#define SPI_SR_CHSIDE 0x00000004U /*!<Channel side */
+#define SPI_SR_UDR 0x00000008U /*!<Underrun flag */
+#define SPI_SR_CRCERR 0x00000010U /*!<CRC Error flag */
+#define SPI_SR_MODF 0x00000020U /*!<Mode fault */
+#define SPI_SR_OVR 0x00000040U /*!<Overrun flag */
+#define SPI_SR_BSY 0x00000080U /*!<Busy flag */
+#define SPI_SR_FRE 0x00000100U /*!<Frame format error flag */
+
+/******************** Bit definition for SPI_DR register ********************/
+#define SPI_DR_DR 0x0000FFFFU /*!<Data Register */
+
+/******************* Bit definition for SPI_CRCPR register ******************/
+#define SPI_CRCPR_CRCPOLY 0x0000FFFFU /*!<CRC polynomial register */
+
+/****************** Bit definition for SPI_RXCRCR register ******************/
+#define SPI_RXCRCR_RXCRC 0x0000FFFFU /*!<Rx CRC Register */
+
+/****************** Bit definition for SPI_TXCRCR register ******************/
+#define SPI_TXCRCR_TXCRC 0x0000FFFFU /*!<Tx CRC Register */
+
+/****************** Bit definition for SPI_I2SCFGR register *****************/
+#define SPI_I2SCFGR_CHLEN 0x00000001U /*!<Channel length (number of bits per audio channel) */
+
+#define SPI_I2SCFGR_DATLEN 0x00000006U /*!<DATLEN[1:0] bits (Data length to be transferred) */
+#define SPI_I2SCFGR_DATLEN_0 0x00000002U /*!<Bit 0 */
+#define SPI_I2SCFGR_DATLEN_1 0x00000004U /*!<Bit 1 */
+
+#define SPI_I2SCFGR_CKPOL 0x00000008U /*!<steady state clock polarity */
+
+#define SPI_I2SCFGR_I2SSTD 0x00000030U /*!<I2SSTD[1:0] bits (I2S standard selection) */
+#define SPI_I2SCFGR_I2SSTD_0 0x00000010U /*!<Bit 0 */
+#define SPI_I2SCFGR_I2SSTD_1 0x00000020U /*!<Bit 1 */
+
+#define SPI_I2SCFGR_PCMSYNC 0x00000080U /*!<PCM frame synchronization */
+
+#define SPI_I2SCFGR_I2SCFG 0x00000300U /*!<I2SCFG[1:0] bits (I2S configuration mode) */
+#define SPI_I2SCFGR_I2SCFG_0 0x00000100U /*!<Bit 0 */
+#define SPI_I2SCFGR_I2SCFG_1 0x00000200U /*!<Bit 1 */
+
+#define SPI_I2SCFGR_I2SE 0x00000400U /*!<I2S Enable */
+#define SPI_I2SCFGR_I2SMOD 0x00000800U /*!<I2S mode selection */
+
+/****************** Bit definition for SPI_I2SPR register *******************/
+#define SPI_I2SPR_I2SDIV 0x000000FFU /*!<I2S Linear prescaler */
+#define SPI_I2SPR_ODD 0x00000100U /*!<Odd factor for the prescaler */
+#define SPI_I2SPR_MCKOE 0x00000200U /*!<Master Clock Output Enable */
+
+/******************************************************************************/
+/* */
+/* SYSCFG */
+/* */
+/******************************************************************************/
+/****************** Bit definition for SYSCFG_MEMRMP register ***************/
+#define SYSCFG_MEMRMP_MEM_MODE 0x00000007U /*!< SYSCFG_Memory Remap Config */
+#define SYSCFG_MEMRMP_MEM_MODE_0 0x00000001U
+#define SYSCFG_MEMRMP_MEM_MODE_1 0x00000002U
+#define SYSCFG_MEMRMP_MEM_MODE_2 0x00000004U
+
+#define SYSCFG_MEMRMP_UFB_MODE 0x00000100U /*!< User Flash Bank mode */
+#define SYSCFG_SWP_FMC 0x00000C00U /*!< FMC memory mapping swap */
+
+/****************** Bit definition for SYSCFG_PMC register ******************/
+#define SYSCFG_PMC_ADCxDC2 0x00070000U /*!< Refer to AN4073 on how to use this bit */
+#define SYSCFG_PMC_ADC1DC2 0x00010000U /*!< Refer to AN4073 on how to use this bit */
+#define SYSCFG_PMC_ADC2DC2 0x00020000U /*!< Refer to AN4073 on how to use this bit */
+#define SYSCFG_PMC_ADC3DC2 0x00040000U /*!< Refer to AN4073 on how to use this bit */
+
+#define SYSCFG_PMC_MII_RMII_SEL 0x00800000U /*!<Ethernet PHY interface selection */
+/* Old MII_RMII_SEL bit definition, maintained for legacy purpose */
+#define SYSCFG_PMC_MII_RMII SYSCFG_PMC_MII_RMII_SEL
+
+/***************** Bit definition for SYSCFG_EXTICR1 register ***************/
+#define SYSCFG_EXTICR1_EXTI0 0x000FU /*!<EXTI 0 configuration */
+#define SYSCFG_EXTICR1_EXTI1 0x00F0U /*!<EXTI 1 configuration */
+#define SYSCFG_EXTICR1_EXTI2 0x0F00U /*!<EXTI 2 configuration */
+#define SYSCFG_EXTICR1_EXTI3 0xF000U /*!<EXTI 3 configuration */
+/**
+ * @brief EXTI0 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI0_PA 0x0000U /*!<PA[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PB 0x0001U /*!<PB[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PC 0x0002U /*!<PC[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PD 0x0003U /*!<PD[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PE 0x0004U /*!<PE[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PF 0x0005U /*!<PF[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PG 0x0006U /*!<PG[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PH 0x0007U /*!<PH[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PI 0x0008U /*!<PI[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PJ 0x0009U /*!<PJ[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PK 0x000AU /*!<PK[0] pin */
+
+/**
+ * @brief EXTI1 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI1_PA 0x0000U /*!<PA[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PB 0x0010U /*!<PB[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PC 0x0020U /*!<PC[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PD 0x0030U /*!<PD[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PE 0x0040U /*!<PE[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PF 0x0050U /*!<PF[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PG 0x0060U /*!<PG[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PH 0x0070U /*!<PH[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PI 0x0080U /*!<PI[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PJ 0x0090U /*!<PJ[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PK 0x00A0U /*!<PK[1] pin */
+
+
+/**
+ * @brief EXTI2 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI2_PA 0x0000U /*!<PA[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PB 0x0100U /*!<PB[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PC 0x0200U /*!<PC[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PD 0x0300U /*!<PD[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PE 0x0400U /*!<PE[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PF 0x0500U /*!<PF[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PG 0x0600U /*!<PG[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PH 0x0700U /*!<PH[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PI 0x0800U /*!<PI[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PJ 0x0900U /*!<PJ[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PK 0x0A00U /*!<PK[2] pin */
+
+
+/**
+ * @brief EXTI3 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI3_PA 0x0000U /*!<PA[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PB 0x1000U /*!<PB[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PC 0x2000U /*!<PC[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PD 0x3000U /*!<PD[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PE 0x4000U /*!<PE[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PF 0x5000U /*!<PF[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PG 0x6000U /*!<PG[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PH 0x7000U /*!<PH[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PI 0x8000U /*!<PI[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PJ 0x9000U /*!<PJ[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PK 0xA000U /*!<PK[3] pin */
+
+
+/***************** Bit definition for SYSCFG_EXTICR2 register ***************/
+#define SYSCFG_EXTICR2_EXTI4 0x000FU /*!<EXTI 4 configuration */
+#define SYSCFG_EXTICR2_EXTI5 0x00F0U /*!<EXTI 5 configuration */
+#define SYSCFG_EXTICR2_EXTI6 0x0F00U /*!<EXTI 6 configuration */
+#define SYSCFG_EXTICR2_EXTI7 0xF000U /*!<EXTI 7 configuration */
+/**
+ * @brief EXTI4 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI4_PA 0x0000U /*!<PA[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PB 0x0001U /*!<PB[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PC 0x0002U /*!<PC[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PD 0x0003U /*!<PD[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PE 0x0004U /*!<PE[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PF 0x0005U /*!<PF[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PG 0x0006U /*!<PG[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PH 0x0007U /*!<PH[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PI 0x0008U /*!<PI[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PJ 0x0009U /*!<PJ[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PK 0x000AU /*!<PK[4] pin */
+
+/**
+ * @brief EXTI5 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI5_PA 0x0000U /*!<PA[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PB 0x0010U /*!<PB[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PC 0x0020U /*!<PC[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PD 0x0030U /*!<PD[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PE 0x0040U /*!<PE[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PF 0x0050U /*!<PF[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PG 0x0060U /*!<PG[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PH 0x0070U /*!<PH[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PI 0x0080U /*!<PI[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PJ 0x0090U /*!<PJ[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PK 0x00A0U /*!<PK[5] pin */
+
+/**
+ * @brief EXTI6 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI6_PA 0x0000U /*!<PA[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PB 0x0100U /*!<PB[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PC 0x0200U /*!<PC[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PD 0x0300U /*!<PD[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PE 0x0400U /*!<PE[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PF 0x0500U /*!<PF[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PG 0x0600U /*!<PG[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PH 0x0700U /*!<PH[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PI 0x0800U /*!<PI[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PJ 0x0900U /*!<PJ[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PK 0x0A00U /*!<PK[6] pin */
+
+
+/**
+ * @brief EXTI7 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI7_PA 0x0000U /*!<PA[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PB 0x1000U /*!<PB[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PC 0x2000U /*!<PC[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PD 0x3000U /*!<PD[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PE 0x4000U /*!<PE[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PF 0x5000U /*!<PF[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PG 0x6000U /*!<PG[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PH 0x7000U /*!<PH[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PI 0x8000U /*!<PI[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PJ 0x9000U /*!<PJ[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PK 0xA000U /*!<PK[7] pin */
+
+/***************** Bit definition for SYSCFG_EXTICR3 register ***************/
+#define SYSCFG_EXTICR3_EXTI8 0x000FU /*!<EXTI 8 configuration */
+#define SYSCFG_EXTICR3_EXTI9 0x00F0U /*!<EXTI 9 configuration */
+#define SYSCFG_EXTICR3_EXTI10 0x0F00U /*!<EXTI 10 configuration */
+#define SYSCFG_EXTICR3_EXTI11 0xF000U /*!<EXTI 11 configuration */
+
+/**
+ * @brief EXTI8 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI8_PA 0x0000U /*!<PA[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PB 0x0001U /*!<PB[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PC 0x0002U /*!<PC[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PD 0x0003U /*!<PD[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PE 0x0004U /*!<PE[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PF 0x0005U /*!<PF[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PG 0x0006U /*!<PG[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PH 0x0007U /*!<PH[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PI 0x0008U /*!<PI[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PJ 0x0009U /*!<PJ[8] pin */
+
+/**
+ * @brief EXTI9 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI9_PA 0x0000U /*!<PA[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PB 0x0010U /*!<PB[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PC 0x0020U /*!<PC[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PD 0x0030U /*!<PD[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PE 0x0040U /*!<PE[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PF 0x0050U /*!<PF[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PG 0x0060U /*!<PG[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PH 0x0070U /*!<PH[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PI 0x0080U /*!<PI[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PJ 0x0090U /*!<PJ[9] pin */
+
+
+/**
+ * @brief EXTI10 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI10_PA 0x0000U /*!<PA[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PB 0x0100U /*!<PB[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PC 0x0200U /*!<PC[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PD 0x0300U /*!<PD[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PE 0x0400U /*!<PE[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PF 0x0500U /*!<PF[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PG 0x0600U /*!<PG[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PH 0x0700U /*!<PH[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PI 0x0800U /*!<PI[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PJ 0x0900U /*!<PJ[10] pin */
+
+
+/**
+ * @brief EXTI11 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI11_PA 0x0000U /*!<PA[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PB 0x1000U /*!<PB[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PC 0x2000U /*!<PC[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PD 0x3000U /*!<PD[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PE 0x4000U /*!<PE[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PF 0x5000U /*!<PF[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PG 0x6000U /*!<PG[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PH 0x7000U /*!<PH[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PI 0x8000U /*!<PI[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PJ 0x9000U /*!<PJ[11] pin */
+
+
+/***************** Bit definition for SYSCFG_EXTICR4 register ***************/
+#define SYSCFG_EXTICR4_EXTI12 0x000FU /*!<EXTI 12 configuration */
+#define SYSCFG_EXTICR4_EXTI13 0x00F0U /*!<EXTI 13 configuration */
+#define SYSCFG_EXTICR4_EXTI14 0x0F00U /*!<EXTI 14 configuration */
+#define SYSCFG_EXTICR4_EXTI15 0xF000U /*!<EXTI 15 configuration */
+/**
+ * @brief EXTI12 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI12_PA 0x0000U /*!<PA[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PB 0x0001U /*!<PB[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PC 0x0002U /*!<PC[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PD 0x0003U /*!<PD[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PE 0x0004U /*!<PE[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PF 0x0005U /*!<PF[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PG 0x0006U /*!<PG[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PH 0x0007U /*!<PH[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PI 0x0008U /*!<PI[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PJ 0x0009U /*!<PJ[12] pin */
+
+
+/**
+ * @brief EXTI13 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI13_PA 0x0000U /*!<PA[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PB 0x0010U /*!<PB[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PC 0x0020U /*!<PC[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PD 0x0030U /*!<PD[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PE 0x0040U /*!<PE[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PF 0x0050U /*!<PF[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PG 0x0060U /*!<PG[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PH 0x0070U /*!<PH[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PI 0x0008U /*!<PI[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PJ 0x0009U /*!<PJ[13] pin */
+
+
+/**
+ * @brief EXTI14 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI14_PA 0x0000U /*!<PA[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PB 0x0100U /*!<PB[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PC 0x0200U /*!<PC[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PD 0x0300U /*!<PD[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PE 0x0400U /*!<PE[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PF 0x0500U /*!<PF[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PG 0x0600U /*!<PG[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PH 0x0700U /*!<PH[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PI 0x0800U /*!<PI[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PJ 0x0900U /*!<PJ[14] pin */
+
+
+/**
+ * @brief EXTI15 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI15_PA 0x0000U /*!<PA[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PB 0x1000U /*!<PB[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PC 0x2000U /*!<PC[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PD 0x3000U /*!<PD[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PE 0x4000U /*!<PE[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PF 0x5000U /*!<PF[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PG 0x6000U /*!<PG[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PH 0x7000U /*!<PH[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PI 0x8000U /*!<PI[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PJ 0x9000U /*!<PJ[15] pin */
+
+/****************** Bit definition for SYSCFG_CMPCR register ****************/
+#define SYSCFG_CMPCR_CMP_PD 0x00000001U /*!<Compensation cell ready flag */
+#define SYSCFG_CMPCR_READY 0x00000100U /*!<Compensation cell power-down */
+
+/******************************************************************************/
+/* */
+/* TIM */
+/* */
+/******************************************************************************/
+/******************* Bit definition for TIM_CR1 register ********************/
+#define TIM_CR1_CEN 0x0001U /*!<Counter enable */
+#define TIM_CR1_UDIS 0x0002U /*!<Update disable */
+#define TIM_CR1_URS 0x0004U /*!<Update request source */
+#define TIM_CR1_OPM 0x0008U /*!<One pulse mode */
+#define TIM_CR1_DIR 0x0010U /*!<Direction */
+
+#define TIM_CR1_CMS 0x0060U /*!<CMS[1:0] bits (Center-aligned mode selection) */
+#define TIM_CR1_CMS_0 0x0020U /*!<Bit 0 */
+#define TIM_CR1_CMS_1 0x0040U /*!<Bit 1 */
+
+#define TIM_CR1_ARPE 0x0080U /*!<Auto-reload preload enable */
+
+#define TIM_CR1_CKD 0x0300U /*!<CKD[1:0] bits (clock division) */
+#define TIM_CR1_CKD_0 0x0100U /*!<Bit 0 */
+#define TIM_CR1_CKD_1 0x0200U /*!<Bit 1 */
+
+/******************* Bit definition for TIM_CR2 register ********************/
+#define TIM_CR2_CCPC 0x0001U /*!<Capture/Compare Preloaded Control */
+#define TIM_CR2_CCUS 0x0004U /*!<Capture/Compare Control Update Selection */
+#define TIM_CR2_CCDS 0x0008U /*!<Capture/Compare DMA Selection */
+
+#define TIM_CR2_MMS 0x0070U /*!<MMS[2:0] bits (Master Mode Selection) */
+#define TIM_CR2_MMS_0 0x0010U /*!<Bit 0 */
+#define TIM_CR2_MMS_1 0x0020U /*!<Bit 1 */
+#define TIM_CR2_MMS_2 0x0040U /*!<Bit 2 */
+
+#define TIM_CR2_TI1S 0x0080U /*!<TI1 Selection */
+#define TIM_CR2_OIS1 0x0100U /*!<Output Idle state 1 (OC1 output) */
+#define TIM_CR2_OIS1N 0x0200U /*!<Output Idle state 1 (OC1N output) */
+#define TIM_CR2_OIS2 0x0400U /*!<Output Idle state 2 (OC2 output) */
+#define TIM_CR2_OIS2N 0x0800U /*!<Output Idle state 2 (OC2N output) */
+#define TIM_CR2_OIS3 0x1000U /*!<Output Idle state 3 (OC3 output) */
+#define TIM_CR2_OIS3N 0x2000U /*!<Output Idle state 3 (OC3N output) */
+#define TIM_CR2_OIS4 0x4000U /*!<Output Idle state 4 (OC4 output) */
+
+/******************* Bit definition for TIM_SMCR register *******************/
+#define TIM_SMCR_SMS 0x0007U /*!<SMS[2:0] bits (Slave mode selection) */
+#define TIM_SMCR_SMS_0 0x0001U /*!<Bit 0 */
+#define TIM_SMCR_SMS_1 0x0002U /*!<Bit 1 */
+#define TIM_SMCR_SMS_2 0x0004U /*!<Bit 2 */
+
+#define TIM_SMCR_TS 0x0070U /*!<TS[2:0] bits (Trigger selection) */
+#define TIM_SMCR_TS_0 0x0010U /*!<Bit 0 */
+#define TIM_SMCR_TS_1 0x0020U /*!<Bit 1 */
+#define TIM_SMCR_TS_2 0x0040U /*!<Bit 2 */
+
+#define TIM_SMCR_MSM 0x0080U /*!<Master/slave mode */
+
+#define TIM_SMCR_ETF 0x0F00U /*!<ETF[3:0] bits (External trigger filter) */
+#define TIM_SMCR_ETF_0 0x0100U /*!<Bit 0 */
+#define TIM_SMCR_ETF_1 0x0200U /*!<Bit 1 */
+#define TIM_SMCR_ETF_2 0x0400U /*!<Bit 2 */
+#define TIM_SMCR_ETF_3 0x0800U /*!<Bit 3 */
+
+#define TIM_SMCR_ETPS 0x3000U /*!<ETPS[1:0] bits (External trigger prescaler) */
+#define TIM_SMCR_ETPS_0 0x1000U /*!<Bit 0 */
+#define TIM_SMCR_ETPS_1 0x2000U /*!<Bit 1 */
+
+#define TIM_SMCR_ECE 0x4000U /*!<External clock enable */
+#define TIM_SMCR_ETP 0x8000U /*!<External trigger polarity */
+
+/******************* Bit definition for TIM_DIER register *******************/
+#define TIM_DIER_UIE 0x0001U /*!<Update interrupt enable */
+#define TIM_DIER_CC1IE 0x0002U /*!<Capture/Compare 1 interrupt enable */
+#define TIM_DIER_CC2IE 0x0004U /*!<Capture/Compare 2 interrupt enable */
+#define TIM_DIER_CC3IE 0x0008U /*!<Capture/Compare 3 interrupt enable */
+#define TIM_DIER_CC4IE 0x0010U /*!<Capture/Compare 4 interrupt enable */
+#define TIM_DIER_COMIE 0x0020U /*!<COM interrupt enable */
+#define TIM_DIER_TIE 0x0040U /*!<Trigger interrupt enable */
+#define TIM_DIER_BIE 0x0080U /*!<Break interrupt enable */
+#define TIM_DIER_UDE 0x0100U /*!<Update DMA request enable */
+#define TIM_DIER_CC1DE 0x0200U /*!<Capture/Compare 1 DMA request enable */
+#define TIM_DIER_CC2DE 0x0400U /*!<Capture/Compare 2 DMA request enable */
+#define TIM_DIER_CC3DE 0x0800U /*!<Capture/Compare 3 DMA request enable */
+#define TIM_DIER_CC4DE 0x1000U /*!<Capture/Compare 4 DMA request enable */
+#define TIM_DIER_COMDE 0x2000U /*!<COM DMA request enable */
+#define TIM_DIER_TDE 0x4000U /*!<Trigger DMA request enable */
+
+/******************** Bit definition for TIM_SR register ********************/
+#define TIM_SR_UIF 0x0001U /*!<Update interrupt Flag */
+#define TIM_SR_CC1IF 0x0002U /*!<Capture/Compare 1 interrupt Flag */
+#define TIM_SR_CC2IF 0x0004U /*!<Capture/Compare 2 interrupt Flag */
+#define TIM_SR_CC3IF 0x0008U /*!<Capture/Compare 3 interrupt Flag */
+#define TIM_SR_CC4IF 0x0010U /*!<Capture/Compare 4 interrupt Flag */
+#define TIM_SR_COMIF 0x0020U /*!<COM interrupt Flag */
+#define TIM_SR_TIF 0x0040U /*!<Trigger interrupt Flag */
+#define TIM_SR_BIF 0x0080U /*!<Break interrupt Flag */
+#define TIM_SR_CC1OF 0x0200U /*!<Capture/Compare 1 Overcapture Flag */
+#define TIM_SR_CC2OF 0x0400U /*!<Capture/Compare 2 Overcapture Flag */
+#define TIM_SR_CC3OF 0x0800U /*!<Capture/Compare 3 Overcapture Flag */
+#define TIM_SR_CC4OF 0x1000U /*!<Capture/Compare 4 Overcapture Flag */
+
+/******************* Bit definition for TIM_EGR register ********************/
+#define TIM_EGR_UG 0x01U /*!<Update Generation */
+#define TIM_EGR_CC1G 0x02U /*!<Capture/Compare 1 Generation */
+#define TIM_EGR_CC2G 0x04U /*!<Capture/Compare 2 Generation */
+#define TIM_EGR_CC3G 0x08U /*!<Capture/Compare 3 Generation */
+#define TIM_EGR_CC4G 0x10U /*!<Capture/Compare 4 Generation */
+#define TIM_EGR_COMG 0x20U /*!<Capture/Compare Control Update Generation */
+#define TIM_EGR_TG 0x40U /*!<Trigger Generation */
+#define TIM_EGR_BG 0x80U /*!<Break Generation */
+
+/****************** Bit definition for TIM_CCMR1 register *******************/
+#define TIM_CCMR1_CC1S 0x0003U /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
+#define TIM_CCMR1_CC1S_0 0x0001U /*!<Bit 0 */
+#define TIM_CCMR1_CC1S_1 0x0002U /*!<Bit 1 */
+
+#define TIM_CCMR1_OC1FE 0x0004U /*!<Output Compare 1 Fast enable */
+#define TIM_CCMR1_OC1PE 0x0008U /*!<Output Compare 1 Preload enable */
+
+#define TIM_CCMR1_OC1M 0x0070U /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
+#define TIM_CCMR1_OC1M_0 0x0010U /*!<Bit 0 */
+#define TIM_CCMR1_OC1M_1 0x0020U /*!<Bit 1 */
+#define TIM_CCMR1_OC1M_2 0x0040U /*!<Bit 2 */
+
+#define TIM_CCMR1_OC1CE 0x0080U /*!<Output Compare 1Clear Enable */
+
+#define TIM_CCMR1_CC2S 0x0300U /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
+#define TIM_CCMR1_CC2S_0 0x0100U /*!<Bit 0 */
+#define TIM_CCMR1_CC2S_1 0x0200U /*!<Bit 1 */
+
+#define TIM_CCMR1_OC2FE 0x0400U /*!<Output Compare 2 Fast enable */
+#define TIM_CCMR1_OC2PE 0x0800U /*!<Output Compare 2 Preload enable */
+
+#define TIM_CCMR1_OC2M 0x7000U /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
+#define TIM_CCMR1_OC2M_0 0x1000U /*!<Bit 0 */
+#define TIM_CCMR1_OC2M_1 0x2000U /*!<Bit 1 */
+#define TIM_CCMR1_OC2M_2 0x4000U /*!<Bit 2 */
+
+#define TIM_CCMR1_OC2CE 0x8000U /*!<Output Compare 2 Clear Enable */
+
+/*----------------------------------------------------------------------------*/
+
+#define TIM_CCMR1_IC1PSC 0x000CU /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
+#define TIM_CCMR1_IC1PSC_0 0x0004U /*!<Bit 0 */
+#define TIM_CCMR1_IC1PSC_1 0x0008U /*!<Bit 1 */
+
+#define TIM_CCMR1_IC1F 0x00F0U /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
+#define TIM_CCMR1_IC1F_0 0x0010U /*!<Bit 0 */
+#define TIM_CCMR1_IC1F_1 0x0020U /*!<Bit 1 */
+#define TIM_CCMR1_IC1F_2 0x0040U /*!<Bit 2 */
+#define TIM_CCMR1_IC1F_3 0x0080U /*!<Bit 3 */
+
+#define TIM_CCMR1_IC2PSC 0x0C00U /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
+#define TIM_CCMR1_IC2PSC_0 0x0400U /*!<Bit 0 */
+#define TIM_CCMR1_IC2PSC_1 0x0800U /*!<Bit 1 */
+
+#define TIM_CCMR1_IC2F 0xF000U /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
+#define TIM_CCMR1_IC2F_0 0x1000U /*!<Bit 0 */
+#define TIM_CCMR1_IC2F_1 0x2000U /*!<Bit 1 */
+#define TIM_CCMR1_IC2F_2 0x4000U /*!<Bit 2 */
+#define TIM_CCMR1_IC2F_3 0x8000U /*!<Bit 3 */
+
+/****************** Bit definition for TIM_CCMR2 register *******************/
+#define TIM_CCMR2_CC3S 0x0003U /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
+#define TIM_CCMR2_CC3S_0 0x0001U /*!<Bit 0 */
+#define TIM_CCMR2_CC3S_1 0x0002U /*!<Bit 1 */
+
+#define TIM_CCMR2_OC3FE 0x0004U /*!<Output Compare 3 Fast enable */
+#define TIM_CCMR2_OC3PE 0x0008U /*!<Output Compare 3 Preload enable */
+
+#define TIM_CCMR2_OC3M 0x0070U /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
+#define TIM_CCMR2_OC3M_0 0x0010U /*!<Bit 0 */
+#define TIM_CCMR2_OC3M_1 0x0020U /*!<Bit 1 */
+#define TIM_CCMR2_OC3M_2 0x0040U /*!<Bit 2 */
+
+#define TIM_CCMR2_OC3CE 0x0080U /*!<Output Compare 3 Clear Enable */
+
+#define TIM_CCMR2_CC4S 0x0300U /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
+#define TIM_CCMR2_CC4S_0 0x0100U /*!<Bit 0 */
+#define TIM_CCMR2_CC4S_1 0x0200U /*!<Bit 1 */
+
+#define TIM_CCMR2_OC4FE 0x0400U /*!<Output Compare 4 Fast enable */
+#define TIM_CCMR2_OC4PE 0x0800U /*!<Output Compare 4 Preload enable */
+
+#define TIM_CCMR2_OC4M 0x7000U /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
+#define TIM_CCMR2_OC4M_0 0x1000U /*!<Bit 0 */
+#define TIM_CCMR2_OC4M_1 0x2000U /*!<Bit 1 */
+#define TIM_CCMR2_OC4M_2 0x4000U /*!<Bit 2 */
+
+#define TIM_CCMR2_OC4CE 0x8000U /*!<Output Compare 4 Clear Enable */
+
+/*----------------------------------------------------------------------------*/
+
+#define TIM_CCMR2_IC3PSC 0x000CU /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
+#define TIM_CCMR2_IC3PSC_0 0x0004U /*!<Bit 0 */
+#define TIM_CCMR2_IC3PSC_1 0x0008U /*!<Bit 1 */
+
+#define TIM_CCMR2_IC3F 0x00F0U /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
+#define TIM_CCMR2_IC3F_0 0x0010U /*!<Bit 0 */
+#define TIM_CCMR2_IC3F_1 0x0020U /*!<Bit 1 */
+#define TIM_CCMR2_IC3F_2 0x0040U /*!<Bit 2 */
+#define TIM_CCMR2_IC3F_3 0x0080U /*!<Bit 3 */
+
+#define TIM_CCMR2_IC4PSC 0x0C00U /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
+#define TIM_CCMR2_IC4PSC_0 0x0400U /*!<Bit 0 */
+#define TIM_CCMR2_IC4PSC_1 0x0800U /*!<Bit 1 */
+
+#define TIM_CCMR2_IC4F 0xF000U /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
+#define TIM_CCMR2_IC4F_0 0x1000U /*!<Bit 0 */
+#define TIM_CCMR2_IC4F_1 0x2000U /*!<Bit 1 */
+#define TIM_CCMR2_IC4F_2 0x4000U /*!<Bit 2 */
+#define TIM_CCMR2_IC4F_3 0x8000U /*!<Bit 3 */
+
+/******************* Bit definition for TIM_CCER register *******************/
+#define TIM_CCER_CC1E 0x0001U /*!<Capture/Compare 1 output enable */
+#define TIM_CCER_CC1P 0x0002U /*!<Capture/Compare 1 output Polarity */
+#define TIM_CCER_CC1NE 0x0004U /*!<Capture/Compare 1 Complementary output enable */
+#define TIM_CCER_CC1NP 0x0008U /*!<Capture/Compare 1 Complementary output Polarity */
+#define TIM_CCER_CC2E 0x0010U /*!<Capture/Compare 2 output enable */
+#define TIM_CCER_CC2P 0x0020U /*!<Capture/Compare 2 output Polarity */
+#define TIM_CCER_CC2NE 0x0040U /*!<Capture/Compare 2 Complementary output enable */
+#define TIM_CCER_CC2NP 0x0080U /*!<Capture/Compare 2 Complementary output Polarity */
+#define TIM_CCER_CC3E 0x0100U /*!<Capture/Compare 3 output enable */
+#define TIM_CCER_CC3P 0x0200U /*!<Capture/Compare 3 output Polarity */
+#define TIM_CCER_CC3NE 0x0400U /*!<Capture/Compare 3 Complementary output enable */
+#define TIM_CCER_CC3NP 0x0800U /*!<Capture/Compare 3 Complementary output Polarity */
+#define TIM_CCER_CC4E 0x1000U /*!<Capture/Compare 4 output enable */
+#define TIM_CCER_CC4P 0x2000U /*!<Capture/Compare 4 output Polarity */
+#define TIM_CCER_CC4NP 0x8000U /*!<Capture/Compare 4 Complementary output Polarity */
+
+/******************* Bit definition for TIM_CNT register ********************/
+#define TIM_CNT_CNT 0xFFFFU /*!<Counter Value */
+
+/******************* Bit definition for TIM_PSC register ********************/
+#define TIM_PSC_PSC 0xFFFFU /*!<Prescaler Value */
+
+/******************* Bit definition for TIM_ARR register ********************/
+#define TIM_ARR_ARR 0xFFFFU /*!<actual auto-reload Value */
+
+/******************* Bit definition for TIM_RCR register ********************/
+#define TIM_RCR_REP 0xFFU /*!<Repetition Counter Value */
+
+/******************* Bit definition for TIM_CCR1 register *******************/
+#define TIM_CCR1_CCR1 0xFFFFU /*!<Capture/Compare 1 Value */
+
+/******************* Bit definition for TIM_CCR2 register *******************/
+#define TIM_CCR2_CCR2 0xFFFFU /*!<Capture/Compare 2 Value */
+
+/******************* Bit definition for TIM_CCR3 register *******************/
+#define TIM_CCR3_CCR3 0xFFFFU /*!<Capture/Compare 3 Value */
+
+/******************* Bit definition for TIM_CCR4 register *******************/
+#define TIM_CCR4_CCR4 0xFFFFU /*!<Capture/Compare 4 Value */
+
+/******************* Bit definition for TIM_BDTR register *******************/
+#define TIM_BDTR_DTG 0x00FFU /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
+#define TIM_BDTR_DTG_0 0x0001U /*!<Bit 0 */
+#define TIM_BDTR_DTG_1 0x0002U /*!<Bit 1 */
+#define TIM_BDTR_DTG_2 0x0004U /*!<Bit 2 */
+#define TIM_BDTR_DTG_3 0x0008U /*!<Bit 3 */
+#define TIM_BDTR_DTG_4 0x0010U /*!<Bit 4 */
+#define TIM_BDTR_DTG_5 0x0020U /*!<Bit 5 */
+#define TIM_BDTR_DTG_6 0x0040U /*!<Bit 6 */
+#define TIM_BDTR_DTG_7 0x0080U /*!<Bit 7 */
+
+#define TIM_BDTR_LOCK 0x0300U /*!<LOCK[1:0] bits (Lock Configuration) */
+#define TIM_BDTR_LOCK_0 0x0100U /*!<Bit 0 */
+#define TIM_BDTR_LOCK_1 0x0200U /*!<Bit 1 */
+
+#define TIM_BDTR_OSSI 0x0400U /*!<Off-State Selection for Idle mode */
+#define TIM_BDTR_OSSR 0x0800U /*!<Off-State Selection for Run mode */
+#define TIM_BDTR_BKE 0x1000U /*!<Break enable */
+#define TIM_BDTR_BKP 0x2000U /*!<Break Polarity */
+#define TIM_BDTR_AOE 0x4000U /*!<Automatic Output enable */
+#define TIM_BDTR_MOE 0x8000U /*!<Main Output enable */
+
+/******************* Bit definition for TIM_DCR register ********************/
+#define TIM_DCR_DBA 0x001FU /*!<DBA[4:0] bits (DMA Base Address) */
+#define TIM_DCR_DBA_0 0x0001U /*!<Bit 0 */
+#define TIM_DCR_DBA_1 0x0002U /*!<Bit 1 */
+#define TIM_DCR_DBA_2 0x0004U /*!<Bit 2 */
+#define TIM_DCR_DBA_3 0x0008U /*!<Bit 3 */
+#define TIM_DCR_DBA_4 0x0010U /*!<Bit 4 */
+
+#define TIM_DCR_DBL 0x1F00U /*!<DBL[4:0] bits (DMA Burst Length) */
+#define TIM_DCR_DBL_0 0x0100U /*!<Bit 0 */
+#define TIM_DCR_DBL_1 0x0200U /*!<Bit 1 */
+#define TIM_DCR_DBL_2 0x0400U /*!<Bit 2 */
+#define TIM_DCR_DBL_3 0x0800U /*!<Bit 3 */
+#define TIM_DCR_DBL_4 0x1000U /*!<Bit 4 */
+
+/******************* Bit definition for TIM_DMAR register *******************/
+#define TIM_DMAR_DMAB 0xFFFFU /*!<DMA register for burst accesses */
+
+/******************* Bit definition for TIM_OR register *********************/
+#define TIM_OR_TI4_RMP 0x00C0U /*!<TI4_RMP[1:0] bits (TIM5 Input 4 remap) */
+#define TIM_OR_TI4_RMP_0 0x0040U /*!<Bit 0 */
+#define TIM_OR_TI4_RMP_1 0x0080U /*!<Bit 1 */
+#define TIM_OR_ITR1_RMP 0x0C00U /*!<ITR1_RMP[1:0] bits (TIM2 Internal trigger 1 remap) */
+#define TIM_OR_ITR1_RMP_0 0x0400U /*!<Bit 0 */
+#define TIM_OR_ITR1_RMP_1 0x0800U /*!<Bit 1 */
+
+
+/******************************************************************************/
+/* */
+/* Universal Synchronous Asynchronous Receiver Transmitter */
+/* */
+/******************************************************************************/
+/******************* Bit definition for USART_SR register *******************/
+#define USART_SR_PE 0x0001U /*!<Parity Error */
+#define USART_SR_FE 0x0002U /*!<Framing Error */
+#define USART_SR_NE 0x0004U /*!<Noise Error Flag */
+#define USART_SR_ORE 0x0008U /*!<OverRun Error */
+#define USART_SR_IDLE 0x0010U /*!<IDLE line detected */
+#define USART_SR_RXNE 0x0020U /*!<Read Data Register Not Empty */
+#define USART_SR_TC 0x0040U /*!<Transmission Complete */
+#define USART_SR_TXE 0x0080U /*!<Transmit Data Register Empty */
+#define USART_SR_LBD 0x0100U /*!<LIN Break Detection Flag */
+#define USART_SR_CTS 0x0200U /*!<CTS Flag */
+
+/******************* Bit definition for USART_DR register *******************/
+#define USART_DR_DR 0x01FFU /*!<Data value */
+
+/****************** Bit definition for USART_BRR register *******************/
+#define USART_BRR_DIV_Fraction 0x000FU /*!<Fraction of USARTDIV */
+#define USART_BRR_DIV_Mantissa 0xFFF0U /*!<Mantissa of USARTDIV */
+
+/****************** Bit definition for USART_CR1 register *******************/
+#define USART_CR1_SBK 0x0001U /*!<Send Break */
+#define USART_CR1_RWU 0x0002U /*!<Receiver wakeup */
+#define USART_CR1_RE 0x0004U /*!<Receiver Enable */
+#define USART_CR1_TE 0x0008U /*!<Transmitter Enable */
+#define USART_CR1_IDLEIE 0x0010U /*!<IDLE Interrupt Enable */
+#define USART_CR1_RXNEIE 0x0020U /*!<RXNE Interrupt Enable */
+#define USART_CR1_TCIE 0x0040U /*!<Transmission Complete Interrupt Enable */
+#define USART_CR1_TXEIE 0x0080U /*!<PE Interrupt Enable */
+#define USART_CR1_PEIE 0x0100U /*!<PE Interrupt Enable */
+#define USART_CR1_PS 0x0200U /*!<Parity Selection */
+#define USART_CR1_PCE 0x0400U /*!<Parity Control Enable */
+#define USART_CR1_WAKE 0x0800U /*!<Wakeup method */
+#define USART_CR1_M 0x1000U /*!<Word length */
+#define USART_CR1_UE 0x2000U /*!<USART Enable */
+#define USART_CR1_OVER8 0x8000U /*!<USART Oversampling by 8 enable */
+
+/****************** Bit definition for USART_CR2 register *******************/
+#define USART_CR2_ADD 0x000FU /*!<Address of the USART node */
+#define USART_CR2_LBDL 0x0020U /*!<LIN Break Detection Length */
+#define USART_CR2_LBDIE 0x0040U /*!<LIN Break Detection Interrupt Enable */
+#define USART_CR2_LBCL 0x0100U /*!<Last Bit Clock pulse */
+#define USART_CR2_CPHA 0x0200U /*!<Clock Phase */
+#define USART_CR2_CPOL 0x0400U /*!<Clock Polarity */
+#define USART_CR2_CLKEN 0x0800U /*!<Clock Enable */
+
+#define USART_CR2_STOP 0x3000U /*!<STOP[1:0] bits (STOP bits) */
+#define USART_CR2_STOP_0 0x1000U /*!<Bit 0 */
+#define USART_CR2_STOP_1 0x2000U /*!<Bit 1 */
+
+#define USART_CR2_LINEN 0x4000U /*!<LIN mode enable */
+
+/****************** Bit definition for USART_CR3 register *******************/
+#define USART_CR3_EIE 0x0001U /*!<Error Interrupt Enable */
+#define USART_CR3_IREN 0x0002U /*!<IrDA mode Enable */
+#define USART_CR3_IRLP 0x0004U /*!<IrDA Low-Power */
+#define USART_CR3_HDSEL 0x0008U /*!<Half-Duplex Selection */
+#define USART_CR3_NACK 0x0010U /*!<Smartcard NACK enable */
+#define USART_CR3_SCEN 0x0020U /*!<Smartcard mode enable */
+#define USART_CR3_DMAR 0x0040U /*!<DMA Enable Receiver */
+#define USART_CR3_DMAT 0x0080U /*!<DMA Enable Transmitter */
+#define USART_CR3_RTSE 0x0100U /*!<RTS Enable */
+#define USART_CR3_CTSE 0x0200U /*!<CTS Enable */
+#define USART_CR3_CTSIE 0x0400U /*!<CTS Interrupt Enable */
+#define USART_CR3_ONEBIT 0x0800U /*!<USART One bit method enable */
+
+/****************** Bit definition for USART_GTPR register ******************/
+#define USART_GTPR_PSC 0x00FFU /*!<PSC[7:0] bits (Prescaler value) */
+#define USART_GTPR_PSC_0 0x0001U /*!<Bit 0 */
+#define USART_GTPR_PSC_1 0x0002U /*!<Bit 1 */
+#define USART_GTPR_PSC_2 0x0004U /*!<Bit 2 */
+#define USART_GTPR_PSC_3 0x0008U /*!<Bit 3 */
+#define USART_GTPR_PSC_4 0x0010U /*!<Bit 4 */
+#define USART_GTPR_PSC_5 0x0020U /*!<Bit 5 */
+#define USART_GTPR_PSC_6 0x0040U /*!<Bit 6 */
+#define USART_GTPR_PSC_7 0x0080U /*!<Bit 7 */
+
+#define USART_GTPR_GT 0xFF00U /*!<Guard time value */
+
+/******************************************************************************/
+/* */
+/* Window WATCHDOG */
+/* */
+/******************************************************************************/
+/******************* Bit definition for WWDG_CR register ********************/
+#define WWDG_CR_T 0x7FU /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
+#define WWDG_CR_T_0 0x01U /*!<Bit 0 */
+#define WWDG_CR_T_1 0x02U /*!<Bit 1 */
+#define WWDG_CR_T_2 0x04U /*!<Bit 2 */
+#define WWDG_CR_T_3 0x08U /*!<Bit 3 */
+#define WWDG_CR_T_4 0x10U /*!<Bit 4 */
+#define WWDG_CR_T_5 0x20U /*!<Bit 5 */
+#define WWDG_CR_T_6 0x40U /*!<Bit 6 */
+/* Legacy defines */
+#define WWDG_CR_T0 WWDG_CR_T_0
+#define WWDG_CR_T1 WWDG_CR_T_1
+#define WWDG_CR_T2 WWDG_CR_T_2
+#define WWDG_CR_T3 WWDG_CR_T_3
+#define WWDG_CR_T4 WWDG_CR_T_4
+#define WWDG_CR_T5 WWDG_CR_T_5
+#define WWDG_CR_T6 WWDG_CR_T_6
+
+#define WWDG_CR_WDGA 0x80U /*!<Activation bit */
+
+/******************* Bit definition for WWDG_CFR register *******************/
+#define WWDG_CFR_W 0x007FU /*!<W[6:0] bits (7-bit window value) */
+#define WWDG_CFR_W_0 0x0001U /*!<Bit 0 */
+#define WWDG_CFR_W_1 0x0002U /*!<Bit 1 */
+#define WWDG_CFR_W_2 0x0004U /*!<Bit 2 */
+#define WWDG_CFR_W_3 0x0008U /*!<Bit 3 */
+#define WWDG_CFR_W_4 0x0010U /*!<Bit 4 */
+#define WWDG_CFR_W_5 0x0020U /*!<Bit 5 */
+#define WWDG_CFR_W_6 0x0040U /*!<Bit 6 */
+/* Legacy defines */
+#define WWDG_CFR_W0 WWDG_CFR_W_0
+#define WWDG_CFR_W1 WWDG_CFR_W_1
+#define WWDG_CFR_W2 WWDG_CFR_W_2
+#define WWDG_CFR_W3 WWDG_CFR_W_3
+#define WWDG_CFR_W4 WWDG_CFR_W_4
+#define WWDG_CFR_W5 WWDG_CFR_W_5
+#define WWDG_CFR_W6 WWDG_CFR_W_6
+
+#define WWDG_CFR_WDGTB 0x0180U /*!<WDGTB[1:0] bits (Timer Base) */
+#define WWDG_CFR_WDGTB_0 0x0080U /*!<Bit 0 */
+#define WWDG_CFR_WDGTB_1 0x0100U /*!<Bit 1 */
+/* Legacy defines */
+#define WWDG_CFR_WDGTB0 WWDG_CFR_WDGTB_0
+#define WWDG_CFR_WDGTB1 WWDG_CFR_WDGTB_1
+
+#define WWDG_CFR_EWI 0x0200U /*!<Early Wakeup Interrupt */
+
+/******************* Bit definition for WWDG_SR register ********************/
+#define WWDG_SR_EWIF 0x01U /*!<Early Wakeup Interrupt Flag */
+
+
+/******************************************************************************/
+/* */
+/* DBG */
+/* */
+/******************************************************************************/
+/******************** Bit definition for DBGMCU_IDCODE register *************/
+#define DBGMCU_IDCODE_DEV_ID 0x00000FFFU
+#define DBGMCU_IDCODE_REV_ID 0xFFFF0000U
+
+/******************** Bit definition for DBGMCU_CR register *****************/
+#define DBGMCU_CR_DBG_SLEEP 0x00000001U
+#define DBGMCU_CR_DBG_STOP 0x00000002U
+#define DBGMCU_CR_DBG_STANDBY 0x00000004U
+#define DBGMCU_CR_TRACE_IOEN 0x00000020U
+
+#define DBGMCU_CR_TRACE_MODE 0x000000C0U
+#define DBGMCU_CR_TRACE_MODE_0 0x00000040U/*!<Bit 0 */
+#define DBGMCU_CR_TRACE_MODE_1 0x00000080U/*!<Bit 1 */
+
+/******************** Bit definition for DBGMCU_APB1_FZ register ************/
+#define DBGMCU_APB1_FZ_DBG_TIM2_STOP 0x00000001U
+#define DBGMCU_APB1_FZ_DBG_TIM3_STOP 0x00000002U
+#define DBGMCU_APB1_FZ_DBG_TIM4_STOP 0x00000004U
+#define DBGMCU_APB1_FZ_DBG_TIM5_STOP 0x00000008U
+#define DBGMCU_APB1_FZ_DBG_TIM6_STOP 0x00000010U
+#define DBGMCU_APB1_FZ_DBG_TIM7_STOP 0x00000020U
+#define DBGMCU_APB1_FZ_DBG_TIM12_STOP 0x00000040U
+#define DBGMCU_APB1_FZ_DBG_TIM13_STOP 0x00000080U
+#define DBGMCU_APB1_FZ_DBG_TIM14_STOP 0x00000100U
+#define DBGMCU_APB1_FZ_DBG_RTC_STOP 0x00000400U
+#define DBGMCU_APB1_FZ_DBG_WWDG_STOP 0x00000800U
+#define DBGMCU_APB1_FZ_DBG_IWDG_STOP 0x00001000U
+#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT 0x00200000U
+#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT 0x00400000U
+#define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT 0x00800000U
+#define DBGMCU_APB1_FZ_DBG_CAN1_STOP 0x02000000U
+#define DBGMCU_APB1_FZ_DBG_CAN2_STOP 0x04000000U
+/* Old IWDGSTOP bit definition, maintained for legacy purpose */
+#define DBGMCU_APB1_FZ_DBG_IWDEG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP
+
+/******************** Bit definition for DBGMCU_APB2_FZ register ************/
+#define DBGMCU_APB2_FZ_DBG_TIM1_STOP 0x00000001U
+#define DBGMCU_APB2_FZ_DBG_TIM8_STOP 0x00000002U
+#define DBGMCU_APB2_FZ_DBG_TIM9_STOP 0x00010000U
+#define DBGMCU_APB2_FZ_DBG_TIM10_STOP 0x00020000U
+#define DBGMCU_APB2_FZ_DBG_TIM11_STOP 0x00040000U
+
+/******************************************************************************/
+/* */
+/* Ethernet MAC Registers bits definitions */
+/* */
+/******************************************************************************/
+/* Bit definition for Ethernet MAC Control Register register */
+#define ETH_MACCR_WD 0x00800000U /* Watchdog disable */
+#define ETH_MACCR_JD 0x00400000U /* Jabber disable */
+#define ETH_MACCR_IFG 0x000E0000U /* Inter-frame gap */
+#define ETH_MACCR_IFG_96Bit 0x00000000U /* Minimum IFG between frames during transmission is 96Bit */
+ #define ETH_MACCR_IFG_88Bit 0x00020000U /* Minimum IFG between frames during transmission is 88Bit */
+ #define ETH_MACCR_IFG_80Bit 0x00040000U /* Minimum IFG between frames during transmission is 80Bit */
+ #define ETH_MACCR_IFG_72Bit 0x00060000U /* Minimum IFG between frames during transmission is 72Bit */
+ #define ETH_MACCR_IFG_64Bit 0x00080000U /* Minimum IFG between frames during transmission is 64Bit */
+ #define ETH_MACCR_IFG_56Bit 0x000A0000U /* Minimum IFG between frames during transmission is 56Bit */
+ #define ETH_MACCR_IFG_48Bit 0x000C0000U /* Minimum IFG between frames during transmission is 48Bit */
+ #define ETH_MACCR_IFG_40Bit 0x000E0000U /* Minimum IFG between frames during transmission is 40Bit */
+#define ETH_MACCR_CSD 0x00010000U /* Carrier sense disable (during transmission) */
+#define ETH_MACCR_FES 0x00004000U /* Fast ethernet speed */
+#define ETH_MACCR_ROD 0x00002000U /* Receive own disable */
+#define ETH_MACCR_LM 0x00001000U /* loopback mode */
+#define ETH_MACCR_DM 0x00000800U /* Duplex mode */
+#define ETH_MACCR_IPCO 0x00000400U /* IP Checksum offload */
+#define ETH_MACCR_RD 0x00000200U /* Retry disable */
+#define ETH_MACCR_APCS 0x00000080U /* Automatic Pad/CRC stripping */
+#define ETH_MACCR_BL 0x00000060U /* Back-off limit: random integer number (r) of slot time delays before rescheduling
+ a transmission attempt during retries after a collision: 0 =< r <2^k */
+ #define ETH_MACCR_BL_10 0x00000000U /* k = min (n, 10) */
+ #define ETH_MACCR_BL_8 0x00000020U /* k = min (n, 8) */
+ #define ETH_MACCR_BL_4 0x00000040U /* k = min (n, 4) */
+ #define ETH_MACCR_BL_1 0x00000060U /* k = min (n, 1) */
+#define ETH_MACCR_DC 0x00000010U /* Defferal check */
+#define ETH_MACCR_TE 0x00000008U /* Transmitter enable */
+#define ETH_MACCR_RE 0x00000004U /* Receiver enable */
+
+/* Bit definition for Ethernet MAC Frame Filter Register */
+#define ETH_MACFFR_RA 0x80000000U /* Receive all */
+#define ETH_MACFFR_HPF 0x00000400U /* Hash or perfect filter */
+#define ETH_MACFFR_SAF 0x00000200U /* Source address filter enable */
+#define ETH_MACFFR_SAIF 0x00000100U /* SA inverse filtering */
+#define ETH_MACFFR_PCF 0x000000C0U /* Pass control frames: 3 cases */
+ #define ETH_MACFFR_PCF_BlockAll 0x00000040U /* MAC filters all control frames from reaching the application */
+ #define ETH_MACFFR_PCF_ForwardAll 0x00000080U /* MAC forwards all control frames to application even if they fail the Address Filter */
+ #define ETH_MACFFR_PCF_ForwardPassedAddrFilter 0x000000C0U /* MAC forwards control frames that pass the Address Filter. */
+#define ETH_MACFFR_BFD 0x00000020U /* Broadcast frame disable */
+#define ETH_MACFFR_PAM 0x00000010U /* Pass all mutlicast */
+#define ETH_MACFFR_DAIF 0x00000008U /* DA Inverse filtering */
+#define ETH_MACFFR_HM 0x00000004U /* Hash multicast */
+#define ETH_MACFFR_HU 0x00000002U /* Hash unicast */
+#define ETH_MACFFR_PM 0x00000001U /* Promiscuous mode */
+
+/* Bit definition for Ethernet MAC Hash Table High Register */
+#define ETH_MACHTHR_HTH 0xFFFFFFFFU /* Hash table high */
+
+/* Bit definition for Ethernet MAC Hash Table Low Register */
+#define ETH_MACHTLR_HTL 0xFFFFFFFFU /* Hash table low */
+
+/* Bit definition for Ethernet MAC MII Address Register */
+#define ETH_MACMIIAR_PA 0x0000F800U /* Physical layer address */
+#define ETH_MACMIIAR_MR 0x000007C0U /* MII register in the selected PHY */
+#define ETH_MACMIIAR_CR 0x0000001CU /* CR clock range: 6 cases */
+ #define ETH_MACMIIAR_CR_Div42 0x00000000U /* HCLK:60-100 MHz; MDC clock= HCLK/42 */
+ #define ETH_MACMIIAR_CR_Div62 0x00000004U /* HCLK:100-150 MHz; MDC clock= HCLK/62 */
+ #define ETH_MACMIIAR_CR_Div16 0x00000008U /* HCLK:20-35 MHz; MDC clock= HCLK/16 */
+ #define ETH_MACMIIAR_CR_Div26 0x0000000CU /* HCLK:35-60 MHz; MDC clock= HCLK/26 */
+ #define ETH_MACMIIAR_CR_Div102 0x00000010U /* HCLK:150-168 MHz; MDC clock= HCLK/102 */
+#define ETH_MACMIIAR_MW 0x00000002U /* MII write */
+#define ETH_MACMIIAR_MB 0x00000001U /* MII busy */
+
+/* Bit definition for Ethernet MAC MII Data Register */
+#define ETH_MACMIIDR_MD 0x0000FFFFU /* MII data: read/write data from/to PHY */
+
+/* Bit definition for Ethernet MAC Flow Control Register */
+#define ETH_MACFCR_PT 0xFFFF0000U /* Pause time */
+#define ETH_MACFCR_ZQPD 0x00000080U /* Zero-quanta pause disable */
+#define ETH_MACFCR_PLT 0x00000030U /* Pause low threshold: 4 cases */
+ #define ETH_MACFCR_PLT_Minus4 0x00000000U /* Pause time minus 4 slot times */
+ #define ETH_MACFCR_PLT_Minus28 0x00000010U /* Pause time minus 28 slot times */
+ #define ETH_MACFCR_PLT_Minus144 0x00000020U /* Pause time minus 144 slot times */
+ #define ETH_MACFCR_PLT_Minus256 0x00000030U /* Pause time minus 256 slot times */
+#define ETH_MACFCR_UPFD 0x00000008U /* Unicast pause frame detect */
+#define ETH_MACFCR_RFCE 0x00000004U /* Receive flow control enable */
+#define ETH_MACFCR_TFCE 0x00000002U /* Transmit flow control enable */
+#define ETH_MACFCR_FCBBPA 0x00000001U /* Flow control busy/backpressure activate */
+
+/* Bit definition for Ethernet MAC VLAN Tag Register */
+#define ETH_MACVLANTR_VLANTC 0x00010000U /* 12-bit VLAN tag comparison */
+#define ETH_MACVLANTR_VLANTI 0x0000FFFFU /* VLAN tag identifier (for receive frames) */
+
+/* Bit definition for Ethernet MAC Remote Wake-UpFrame Filter Register */
+#define ETH_MACRWUFFR_D 0xFFFFFFFFU /* Wake-up frame filter register data */
+/* Eight sequential Writes to this address (offset 0x28) will write all Wake-UpFrame Filter Registers.
+ Eight sequential Reads from this address (offset 0x28) will read all Wake-UpFrame Filter Registers. */
+/* Wake-UpFrame Filter Reg0 : Filter 0 Byte Mask
+ Wake-UpFrame Filter Reg1 : Filter 1 Byte Mask
+ Wake-UpFrame Filter Reg2 : Filter 2 Byte Mask
+ Wake-UpFrame Filter Reg3 : Filter 3 Byte Mask
+ Wake-UpFrame Filter Reg4 : RSVD - Filter3 Command - RSVD - Filter2 Command -
+ RSVD - Filter1 Command - RSVD - Filter0 Command
+ Wake-UpFrame Filter Re5 : Filter3 Offset - Filter2 Offset - Filter1 Offset - Filter0 Offset
+ Wake-UpFrame Filter Re6 : Filter1 CRC16 - Filter0 CRC16
+ Wake-UpFrame Filter Re7 : Filter3 CRC16 - Filter2 CRC16 */
+
+/* Bit definition for Ethernet MAC PMT Control and Status Register */
+#define ETH_MACPMTCSR_WFFRPR 0x80000000U /* Wake-Up Frame Filter Register Pointer Reset */
+#define ETH_MACPMTCSR_GU 0x00000200U /* Global Unicast */
+#define ETH_MACPMTCSR_WFR 0x00000040U /* Wake-Up Frame Received */
+#define ETH_MACPMTCSR_MPR 0x00000020U /* Magic Packet Received */
+#define ETH_MACPMTCSR_WFE 0x00000004U /* Wake-Up Frame Enable */
+#define ETH_MACPMTCSR_MPE 0x00000002U /* Magic Packet Enable */
+#define ETH_MACPMTCSR_PD 0x00000001U /* Power Down */
+
+/* Bit definition for Ethernet MAC Status Register */
+#define ETH_MACSR_TSTS 0x00000200U /* Time stamp trigger status */
+#define ETH_MACSR_MMCTS 0x00000040U /* MMC transmit status */
+#define ETH_MACSR_MMMCRS 0x00000020U /* MMC receive status */
+#define ETH_MACSR_MMCS 0x00000010U /* MMC status */
+#define ETH_MACSR_PMTS 0x00000008U /* PMT status */
+
+/* Bit definition for Ethernet MAC Interrupt Mask Register */
+#define ETH_MACIMR_TSTIM 0x00000200U /* Time stamp trigger interrupt mask */
+#define ETH_MACIMR_PMTIM 0x00000008U /* PMT interrupt mask */
+
+/* Bit definition for Ethernet MAC Address0 High Register */
+#define ETH_MACA0HR_MACA0H 0x0000FFFFU /* MAC address0 high */
+
+/* Bit definition for Ethernet MAC Address0 Low Register */
+#define ETH_MACA0LR_MACA0L 0xFFFFFFFFU /* MAC address0 low */
+
+/* Bit definition for Ethernet MAC Address1 High Register */
+#define ETH_MACA1HR_AE 0x80000000U /* Address enable */
+#define ETH_MACA1HR_SA 0x40000000U /* Source address */
+#define ETH_MACA1HR_MBC 0x3F000000U /* Mask byte control: bits to mask for comparison of the MAC Address bytes */
+ #define ETH_MACA1HR_MBC_HBits15_8 0x20000000U /* Mask MAC Address high reg bits [15:8] */
+ #define ETH_MACA1HR_MBC_HBits7_0 0x10000000U /* Mask MAC Address high reg bits [7:0] */
+ #define ETH_MACA1HR_MBC_LBits31_24 0x08000000U /* Mask MAC Address low reg bits [31:24] */
+ #define ETH_MACA1HR_MBC_LBits23_16 0x04000000U /* Mask MAC Address low reg bits [23:16] */
+ #define ETH_MACA1HR_MBC_LBits15_8 0x02000000U /* Mask MAC Address low reg bits [15:8] */
+ #define ETH_MACA1HR_MBC_LBits7_0 0x01000000U /* Mask MAC Address low reg bits [7:0] */
+#define ETH_MACA1HR_MACA1H 0x0000FFFFU /* MAC address1 high */
+
+/* Bit definition for Ethernet MAC Address1 Low Register */
+#define ETH_MACA1LR_MACA1L 0xFFFFFFFFU /* MAC address1 low */
+
+/* Bit definition for Ethernet MAC Address2 High Register */
+#define ETH_MACA2HR_AE 0x80000000U /* Address enable */
+#define ETH_MACA2HR_SA 0x40000000U /* Source address */
+#define ETH_MACA2HR_MBC 0x3F000000U /* Mask byte control */
+ #define ETH_MACA2HR_MBC_HBits15_8 0x20000000U /* Mask MAC Address high reg bits [15:8] */
+ #define ETH_MACA2HR_MBC_HBits7_0 0x10000000U /* Mask MAC Address high reg bits [7:0] */
+ #define ETH_MACA2HR_MBC_LBits31_24 0x08000000U /* Mask MAC Address low reg bits [31:24] */
+ #define ETH_MACA2HR_MBC_LBits23_16 0x04000000U /* Mask MAC Address low reg bits [23:16] */
+ #define ETH_MACA2HR_MBC_LBits15_8 0x02000000U /* Mask MAC Address low reg bits [15:8] */
+ #define ETH_MACA2HR_MBC_LBits7_0 0x01000000U /* Mask MAC Address low reg bits [70] */
+#define ETH_MACA2HR_MACA2H 0x0000FFFFU /* MAC address1 high */
+
+/* Bit definition for Ethernet MAC Address2 Low Register */
+#define ETH_MACA2LR_MACA2L 0xFFFFFFFFU /* MAC address2 low */
+
+/* Bit definition for Ethernet MAC Address3 High Register */
+#define ETH_MACA3HR_AE 0x80000000U /* Address enable */
+#define ETH_MACA3HR_SA 0x40000000U /* Source address */
+#define ETH_MACA3HR_MBC 0x3F000000U /* Mask byte control */
+ #define ETH_MACA3HR_MBC_HBits15_8 0x20000000U /* Mask MAC Address high reg bits [15:8] */
+ #define ETH_MACA3HR_MBC_HBits7_0 0x10000000U /* Mask MAC Address high reg bits [7:0] */
+ #define ETH_MACA3HR_MBC_LBits31_24 0x08000000U /* Mask MAC Address low reg bits [31:24] */
+ #define ETH_MACA3HR_MBC_LBits23_16 0x04000000U /* Mask MAC Address low reg bits [23:16] */
+ #define ETH_MACA3HR_MBC_LBits15_8 0x02000000U /* Mask MAC Address low reg bits [15:8] */
+ #define ETH_MACA3HR_MBC_LBits7_0 0x01000000U /* Mask MAC Address low reg bits [70] */
+#define ETH_MACA3HR_MACA3H 0x0000FFFFU /* MAC address3 high */
+
+/* Bit definition for Ethernet MAC Address3 Low Register */
+#define ETH_MACA3LR_MACA3L 0xFFFFFFFFU /* MAC address3 low */
+
+/******************************************************************************/
+/* Ethernet MMC Registers bits definition */
+/******************************************************************************/
+
+/* Bit definition for Ethernet MMC Contol Register */
+#define ETH_MMCCR_MCFHP 0x00000020U /* MMC counter Full-Half preset */
+#define ETH_MMCCR_MCP 0x00000010U /* MMC counter preset */
+#define ETH_MMCCR_MCF 0x00000008U /* MMC Counter Freeze */
+#define ETH_MMCCR_ROR 0x00000004U /* Reset on Read */
+#define ETH_MMCCR_CSR 0x00000002U /* Counter Stop Rollover */
+#define ETH_MMCCR_CR 0x00000001U /* Counters Reset */
+
+/* Bit definition for Ethernet MMC Receive Interrupt Register */
+#define ETH_MMCRIR_RGUFS 0x00020000U /* Set when Rx good unicast frames counter reaches half the maximum value */
+#define ETH_MMCRIR_RFAES 0x00000040U /* Set when Rx alignment error counter reaches half the maximum value */
+#define ETH_MMCRIR_RFCES 0x00000020U /* Set when Rx crc error counter reaches half the maximum value */
+
+/* Bit definition for Ethernet MMC Transmit Interrupt Register */
+#define ETH_MMCTIR_TGFS 0x00200000U /* Set when Tx good frame count counter reaches half the maximum value */
+#define ETH_MMCTIR_TGFMSCS 0x00008000U /* Set when Tx good multi col counter reaches half the maximum value */
+#define ETH_MMCTIR_TGFSCS 0x00004000U /* Set when Tx good single col counter reaches half the maximum value */
+
+/* Bit definition for Ethernet MMC Receive Interrupt Mask Register */
+#define ETH_MMCRIMR_RGUFM 0x00020000U /* Mask the interrupt when Rx good unicast frames counter reaches half the maximum value */
+#define ETH_MMCRIMR_RFAEM 0x00000040U /* Mask the interrupt when when Rx alignment error counter reaches half the maximum value */
+#define ETH_MMCRIMR_RFCEM 0x00000020U /* Mask the interrupt when Rx crc error counter reaches half the maximum value */
+
+/* Bit definition for Ethernet MMC Transmit Interrupt Mask Register */
+#define ETH_MMCTIMR_TGFM 0x00200000U /* Mask the interrupt when Tx good frame count counter reaches half the maximum value */
+#define ETH_MMCTIMR_TGFMSCM 0x00008000U /* Mask the interrupt when Tx good multi col counter reaches half the maximum value */
+#define ETH_MMCTIMR_TGFSCM 0x00004000U /* Mask the interrupt when Tx good single col counter reaches half the maximum value */
+
+/* Bit definition for Ethernet MMC Transmitted Good Frames after Single Collision Counter Register */
+#define ETH_MMCTGFSCCR_TGFSCC 0xFFFFFFFFU /* Number of successfully transmitted frames after a single collision in Half-duplex mode. */
+
+/* Bit definition for Ethernet MMC Transmitted Good Frames after More than a Single Collision Counter Register */
+#define ETH_MMCTGFMSCCR_TGFMSCC 0xFFFFFFFFU /* Number of successfully transmitted frames after more than a single collision in Half-duplex mode. */
+
+/* Bit definition for Ethernet MMC Transmitted Good Frames Counter Register */
+#define ETH_MMCTGFCR_TGFC 0xFFFFFFFFU /* Number of good frames transmitted. */
+
+/* Bit definition for Ethernet MMC Received Frames with CRC Error Counter Register */
+#define ETH_MMCRFCECR_RFCEC 0xFFFFFFFFU /* Number of frames received with CRC error. */
+
+/* Bit definition for Ethernet MMC Received Frames with Alignement Error Counter Register */
+#define ETH_MMCRFAECR_RFAEC 0xFFFFFFFFU /* Number of frames received with alignment (dribble) error */
+
+/* Bit definition for Ethernet MMC Received Good Unicast Frames Counter Register */
+#define ETH_MMCRGUFCR_RGUFC 0xFFFFFFFFU /* Number of good unicast frames received. */
+
+/******************************************************************************/
+/* Ethernet PTP Registers bits definition */
+/******************************************************************************/
+
+/* Bit definition for Ethernet PTP Time Stamp Contol Register */
+#define ETH_PTPTSCR_TSCNT 0x00030000U /* Time stamp clock node type */
+#define ETH_PTPTSSR_TSSMRME 0x00008000U /* Time stamp snapshot for message relevant to master enable */
+#define ETH_PTPTSSR_TSSEME 0x00004000U /* Time stamp snapshot for event message enable */
+#define ETH_PTPTSSR_TSSIPV4FE 0x00002000U /* Time stamp snapshot for IPv4 frames enable */
+#define ETH_PTPTSSR_TSSIPV6FE 0x00001000U /* Time stamp snapshot for IPv6 frames enable */
+#define ETH_PTPTSSR_TSSPTPOEFE 0x00000800U /* Time stamp snapshot for PTP over ethernet frames enable */
+#define ETH_PTPTSSR_TSPTPPSV2E 0x00000400U /* Time stamp PTP packet snooping for version2 format enable */
+#define ETH_PTPTSSR_TSSSR 0x00000200U /* Time stamp Sub-seconds rollover */
+#define ETH_PTPTSSR_TSSARFE 0x00000100U /* Time stamp snapshot for all received frames enable */
+
+#define ETH_PTPTSCR_TSARU 0x00000020U /* Addend register update */
+#define ETH_PTPTSCR_TSITE 0x00000010U /* Time stamp interrupt trigger enable */
+#define ETH_PTPTSCR_TSSTU 0x00000008U /* Time stamp update */
+#define ETH_PTPTSCR_TSSTI 0x00000004U /* Time stamp initialize */
+#define ETH_PTPTSCR_TSFCU 0x00000002U /* Time stamp fine or coarse update */
+#define ETH_PTPTSCR_TSE 0x00000001U /* Time stamp enable */
+
+/* Bit definition for Ethernet PTP Sub-Second Increment Register */
+#define ETH_PTPSSIR_STSSI 0x000000FFU /* System time Sub-second increment value */
+
+/* Bit definition for Ethernet PTP Time Stamp High Register */
+#define ETH_PTPTSHR_STS 0xFFFFFFFFU /* System Time second */
+
+/* Bit definition for Ethernet PTP Time Stamp Low Register */
+#define ETH_PTPTSLR_STPNS 0x80000000U /* System Time Positive or negative time */
+#define ETH_PTPTSLR_STSS 0x7FFFFFFFU /* System Time sub-seconds */
+
+/* Bit definition for Ethernet PTP Time Stamp High Update Register */
+#define ETH_PTPTSHUR_TSUS 0xFFFFFFFFU /* Time stamp update seconds */
+
+/* Bit definition for Ethernet PTP Time Stamp Low Update Register */
+#define ETH_PTPTSLUR_TSUPNS 0x80000000U /* Time stamp update Positive or negative time */
+#define ETH_PTPTSLUR_TSUSS 0x7FFFFFFFU /* Time stamp update sub-seconds */
+
+/* Bit definition for Ethernet PTP Time Stamp Addend Register */
+#define ETH_PTPTSAR_TSA 0xFFFFFFFFU /* Time stamp addend */
+
+/* Bit definition for Ethernet PTP Target Time High Register */
+#define ETH_PTPTTHR_TTSH 0xFFFFFFFFU /* Target time stamp high */
+
+/* Bit definition for Ethernet PTP Target Time Low Register */
+#define ETH_PTPTTLR_TTSL 0xFFFFFFFFU /* Target time stamp low */
+
+/* Bit definition for Ethernet PTP Time Stamp Status Register */
+#define ETH_PTPTSSR_TSTTR 0x00000020U /* Time stamp target time reached */
+#define ETH_PTPTSSR_TSSO 0x00000010U /* Time stamp seconds overflow */
+
+/******************************************************************************/
+/* Ethernet DMA Registers bits definition */
+/******************************************************************************/
+
+/* Bit definition for Ethernet DMA Bus Mode Register */
+#define ETH_DMABMR_AAB 0x02000000U /* Address-Aligned beats */
+#define ETH_DMABMR_FPM 0x01000000U /* 4xPBL mode */
+#define ETH_DMABMR_USP 0x00800000U /* Use separate PBL */
+#define ETH_DMABMR_RDP 0x007E0000U /* RxDMA PBL */
+ #define ETH_DMABMR_RDP_1Beat 0x00020000U /* maximum number of beats to be transferred in one RxDMA transaction is 1 */
+ #define ETH_DMABMR_RDP_2Beat 0x00040000U /* maximum number of beats to be transferred in one RxDMA transaction is 2 */
+ #define ETH_DMABMR_RDP_4Beat 0x00080000U /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
+ #define ETH_DMABMR_RDP_8Beat 0x00100000U /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
+ #define ETH_DMABMR_RDP_16Beat 0x00200000U /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
+ #define ETH_DMABMR_RDP_32Beat 0x00400000U /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
+ #define ETH_DMABMR_RDP_4xPBL_4Beat 0x01020000U /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
+ #define ETH_DMABMR_RDP_4xPBL_8Beat 0x01040000U /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
+ #define ETH_DMABMR_RDP_4xPBL_16Beat 0x01080000U /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
+ #define ETH_DMABMR_RDP_4xPBL_32Beat 0x01100000U /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
+ #define ETH_DMABMR_RDP_4xPBL_64Beat 0x01200000U /* maximum number of beats to be transferred in one RxDMA transaction is 64 */
+ #define ETH_DMABMR_RDP_4xPBL_128Beat 0x01400000U /* maximum number of beats to be transferred in one RxDMA transaction is 128 */
+#define ETH_DMABMR_FB 0x00010000U /* Fixed Burst */
+#define ETH_DMABMR_RTPR 0x0000C000U /* Rx Tx priority ratio */
+ #define ETH_DMABMR_RTPR_1_1 0x00000000U /* Rx Tx priority ratio */
+ #define ETH_DMABMR_RTPR_2_1 0x00004000U /* Rx Tx priority ratio */
+ #define ETH_DMABMR_RTPR_3_1 0x00008000U /* Rx Tx priority ratio */
+ #define ETH_DMABMR_RTPR_4_1 0x0000C000U /* Rx Tx priority ratio */
+#define ETH_DMABMR_PBL 0x00003F00U /* Programmable burst length */
+ #define ETH_DMABMR_PBL_1Beat 0x00000100U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */
+ #define ETH_DMABMR_PBL_2Beat 0x00000200U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */
+ #define ETH_DMABMR_PBL_4Beat 0x00000400U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
+ #define ETH_DMABMR_PBL_8Beat 0x00000800U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
+ #define ETH_DMABMR_PBL_16Beat 0x00001000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
+ #define ETH_DMABMR_PBL_32Beat 0x00002000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
+ #define ETH_DMABMR_PBL_4xPBL_4Beat 0x01000100U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
+ #define ETH_DMABMR_PBL_4xPBL_8Beat 0x01000200U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
+ #define ETH_DMABMR_PBL_4xPBL_16Beat 0x01000400U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
+ #define ETH_DMABMR_PBL_4xPBL_32Beat 0x01000800U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
+ #define ETH_DMABMR_PBL_4xPBL_64Beat 0x01001000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */
+ #define ETH_DMABMR_PBL_4xPBL_128Beat 0x01002000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */
+#define ETH_DMABMR_EDE 0x00000080U /* Enhanced Descriptor Enable */
+#define ETH_DMABMR_DSL 0x0000007CU /* Descriptor Skip Length */
+#define ETH_DMABMR_DA 0x00000002U /* DMA arbitration scheme */
+#define ETH_DMABMR_SR 0x00000001U /* Software reset */
+
+/* Bit definition for Ethernet DMA Transmit Poll Demand Register */
+#define ETH_DMATPDR_TPD 0xFFFFFFFFU /* Transmit poll demand */
+
+/* Bit definition for Ethernet DMA Receive Poll Demand Register */
+#define ETH_DMARPDR_RPD 0xFFFFFFFFU /* Receive poll demand */
+
+/* Bit definition for Ethernet DMA Receive Descriptor List Address Register */
+#define ETH_DMARDLAR_SRL 0xFFFFFFFFU /* Start of receive list */
+
+/* Bit definition for Ethernet DMA Transmit Descriptor List Address Register */
+#define ETH_DMATDLAR_STL 0xFFFFFFFFU /* Start of transmit list */
+
+/* Bit definition for Ethernet DMA Status Register */
+#define ETH_DMASR_TSTS 0x20000000U /* Time-stamp trigger status */
+#define ETH_DMASR_PMTS 0x10000000U /* PMT status */
+#define ETH_DMASR_MMCS 0x08000000U /* MMC status */
+#define ETH_DMASR_EBS 0x03800000U /* Error bits status */
+ /* combination with EBS[2:0] for GetFlagStatus function */
+ #define ETH_DMASR_EBS_DescAccess 0x02000000U /* Error bits 0-data buffer, 1-desc. access */
+ #define ETH_DMASR_EBS_ReadTransf 0x01000000U /* Error bits 0-write trnsf, 1-read transfr */
+ #define ETH_DMASR_EBS_DataTransfTx 0x00800000U /* Error bits 0-Rx DMA, 1-Tx DMA */
+#define ETH_DMASR_TPS 0x00700000U /* Transmit process state */
+ #define ETH_DMASR_TPS_Stopped 0x00000000U /* Stopped - Reset or Stop Tx Command issued */
+ #define ETH_DMASR_TPS_Fetching 0x00100000U /* Running - fetching the Tx descriptor */
+ #define ETH_DMASR_TPS_Waiting 0x00200000U /* Running - waiting for status */
+ #define ETH_DMASR_TPS_Reading 0x00300000U /* Running - reading the data from host memory */
+ #define ETH_DMASR_TPS_Suspended 0x00600000U /* Suspended - Tx Descriptor unavailabe */
+ #define ETH_DMASR_TPS_Closing 0x00700000U /* Running - closing Rx descriptor */
+#define ETH_DMASR_RPS 0x000E0000U /* Receive process state */
+ #define ETH_DMASR_RPS_Stopped 0x00000000U /* Stopped - Reset or Stop Rx Command issued */
+ #define ETH_DMASR_RPS_Fetching 0x00020000U /* Running - fetching the Rx descriptor */
+ #define ETH_DMASR_RPS_Waiting 0x00060000U /* Running - waiting for packet */
+ #define ETH_DMASR_RPS_Suspended 0x00080000U /* Suspended - Rx Descriptor unavailable */
+ #define ETH_DMASR_RPS_Closing 0x000A0000U /* Running - closing descriptor */
+ #define ETH_DMASR_RPS_Queuing 0x000E0000U /* Running - queuing the recieve frame into host memory */
+#define ETH_DMASR_NIS 0x00010000U /* Normal interrupt summary */
+#define ETH_DMASR_AIS 0x00008000U /* Abnormal interrupt summary */
+#define ETH_DMASR_ERS 0x00004000U /* Early receive status */
+#define ETH_DMASR_FBES 0x00002000U /* Fatal bus error status */
+#define ETH_DMASR_ETS 0x00000400U /* Early transmit status */
+#define ETH_DMASR_RWTS 0x00000200U /* Receive watchdog timeout status */
+#define ETH_DMASR_RPSS 0x00000100U /* Receive process stopped status */
+#define ETH_DMASR_RBUS 0x00000080U /* Receive buffer unavailable status */
+#define ETH_DMASR_RS 0x00000040U /* Receive status */
+#define ETH_DMASR_TUS 0x00000020U /* Transmit underflow status */
+#define ETH_DMASR_ROS 0x00000010U /* Receive overflow status */
+#define ETH_DMASR_TJTS 0x00000008U /* Transmit jabber timeout status */
+#define ETH_DMASR_TBUS 0x00000004U /* Transmit buffer unavailable status */
+#define ETH_DMASR_TPSS 0x00000002U /* Transmit process stopped status */
+#define ETH_DMASR_TS 0x00000001U /* Transmit status */
+
+/* Bit definition for Ethernet DMA Operation Mode Register */
+#define ETH_DMAOMR_DTCEFD 0x04000000U /* Disable Dropping of TCP/IP checksum error frames */
+#define ETH_DMAOMR_RSF 0x02000000U /* Receive store and forward */
+#define ETH_DMAOMR_DFRF 0x01000000U /* Disable flushing of received frames */
+#define ETH_DMAOMR_TSF 0x00200000U /* Transmit store and forward */
+#define ETH_DMAOMR_FTF 0x00100000U /* Flush transmit FIFO */
+#define ETH_DMAOMR_TTC 0x0001C000U /* Transmit threshold control */
+ #define ETH_DMAOMR_TTC_64Bytes 0x00000000U /* threshold level of the MTL Transmit FIFO is 64 Bytes */
+ #define ETH_DMAOMR_TTC_128Bytes 0x00004000U /* threshold level of the MTL Transmit FIFO is 128 Bytes */
+ #define ETH_DMAOMR_TTC_192Bytes 0x00008000U /* threshold level of the MTL Transmit FIFO is 192 Bytes */
+ #define ETH_DMAOMR_TTC_256Bytes 0x0000C000U /* threshold level of the MTL Transmit FIFO is 256 Bytes */
+ #define ETH_DMAOMR_TTC_40Bytes 0x00010000U /* threshold level of the MTL Transmit FIFO is 40 Bytes */
+ #define ETH_DMAOMR_TTC_32Bytes 0x00014000U /* threshold level of the MTL Transmit FIFO is 32 Bytes */
+ #define ETH_DMAOMR_TTC_24Bytes 0x00018000U /* threshold level of the MTL Transmit FIFO is 24 Bytes */
+ #define ETH_DMAOMR_TTC_16Bytes 0x0001C000U /* threshold level of the MTL Transmit FIFO is 16 Bytes */
+#define ETH_DMAOMR_ST 0x00002000U /* Start/stop transmission command */
+#define ETH_DMAOMR_FEF 0x00000080U /* Forward error frames */
+#define ETH_DMAOMR_FUGF 0x00000040U /* Forward undersized good frames */
+#define ETH_DMAOMR_RTC 0x00000018U /* receive threshold control */
+ #define ETH_DMAOMR_RTC_64Bytes 0x00000000U /* threshold level of the MTL Receive FIFO is 64 Bytes */
+ #define ETH_DMAOMR_RTC_32Bytes 0x00000008U /* threshold level of the MTL Receive FIFO is 32 Bytes */
+ #define ETH_DMAOMR_RTC_96Bytes 0x00000010U /* threshold level of the MTL Receive FIFO is 96 Bytes */
+ #define ETH_DMAOMR_RTC_128Bytes 0x00000018U /* threshold level of the MTL Receive FIFO is 128 Bytes */
+#define ETH_DMAOMR_OSF 0x00000004U /* operate on second frame */
+#define ETH_DMAOMR_SR 0x00000002U /* Start/stop receive */
+
+/* Bit definition for Ethernet DMA Interrupt Enable Register */
+#define ETH_DMAIER_NISE 0x00010000U /* Normal interrupt summary enable */
+#define ETH_DMAIER_AISE 0x00008000U /* Abnormal interrupt summary enable */
+#define ETH_DMAIER_ERIE 0x00004000U /* Early receive interrupt enable */
+#define ETH_DMAIER_FBEIE 0x00002000U /* Fatal bus error interrupt enable */
+#define ETH_DMAIER_ETIE 0x00000400U /* Early transmit interrupt enable */
+#define ETH_DMAIER_RWTIE 0x00000200U /* Receive watchdog timeout interrupt enable */
+#define ETH_DMAIER_RPSIE 0x00000100U /* Receive process stopped interrupt enable */
+#define ETH_DMAIER_RBUIE 0x00000080U /* Receive buffer unavailable interrupt enable */
+#define ETH_DMAIER_RIE 0x00000040U /* Receive interrupt enable */
+#define ETH_DMAIER_TUIE 0x00000020U /* Transmit Underflow interrupt enable */
+#define ETH_DMAIER_ROIE 0x00000010U /* Receive Overflow interrupt enable */
+#define ETH_DMAIER_TJTIE 0x00000008U /* Transmit jabber timeout interrupt enable */
+#define ETH_DMAIER_TBUIE 0x00000004U /* Transmit buffer unavailable interrupt enable */
+#define ETH_DMAIER_TPSIE 0x00000002U /* Transmit process stopped interrupt enable */
+#define ETH_DMAIER_TIE 0x00000001U /* Transmit interrupt enable */
+
+/* Bit definition for Ethernet DMA Missed Frame and Buffer Overflow Counter Register */
+#define ETH_DMAMFBOCR_OFOC 0x10000000U /* Overflow bit for FIFO overflow counter */
+#define ETH_DMAMFBOCR_MFA 0x0FFE0000U /* Number of frames missed by the application */
+#define ETH_DMAMFBOCR_OMFC 0x00010000U /* Overflow bit for missed frame counter */
+#define ETH_DMAMFBOCR_MFC 0x0000FFFFU /* Number of frames missed by the controller */
+
+/* Bit definition for Ethernet DMA Current Host Transmit Descriptor Register */
+#define ETH_DMACHTDR_HTDAP 0xFFFFFFFFU /* Host transmit descriptor address pointer */
+
+/* Bit definition for Ethernet DMA Current Host Receive Descriptor Register */
+#define ETH_DMACHRDR_HRDAP 0xFFFFFFFFU /* Host receive descriptor address pointer */
+
+/* Bit definition for Ethernet DMA Current Host Transmit Buffer Address Register */
+#define ETH_DMACHTBAR_HTBAP 0xFFFFFFFFU /* Host transmit buffer address pointer */
+
+/* Bit definition for Ethernet DMA Current Host Receive Buffer Address Register */
+#define ETH_DMACHRBAR_HRBAP 0xFFFFFFFFU /* Host receive buffer address pointer */
+
+/******************************************************************************/
+/* */
+/* USB_OTG */
+/* */
+/******************************************************************************/
+/******************** Bit definition forUSB_OTG_GOTGCTL register ********************/
+#define USB_OTG_GOTGCTL_SRQSCS 0x00000001U /*!< Session request success */
+#define USB_OTG_GOTGCTL_SRQ 0x00000002U /*!< Session request */
+#define USB_OTG_GOTGCTL_HNGSCS 0x00000100U /*!< Host negotiation success */
+#define USB_OTG_GOTGCTL_HNPRQ 0x00000200U /*!< HNP request */
+#define USB_OTG_GOTGCTL_HSHNPEN 0x00000400U /*!< Host set HNP enable */
+#define USB_OTG_GOTGCTL_DHNPEN 0x00000800U /*!< Device HNP enabled */
+#define USB_OTG_GOTGCTL_CIDSTS 0x00010000U /*!< Connector ID status */
+#define USB_OTG_GOTGCTL_DBCT 0x00020000U /*!< Long/short debounce time */
+#define USB_OTG_GOTGCTL_ASVLD 0x00040000U /*!< A-session valid */
+#define USB_OTG_GOTGCTL_BSVLD 0x00080000U /*!< B-session valid */
+
+/******************** Bit definition forUSB_OTG_HCFG register ********************/
+
+#define USB_OTG_HCFG_FSLSPCS 0x00000003U /*!< FS/LS PHY clock select */
+#define USB_OTG_HCFG_FSLSPCS_0 0x00000001U /*!<Bit 0 */
+#define USB_OTG_HCFG_FSLSPCS_1 0x00000002U /*!<Bit 1 */
+#define USB_OTG_HCFG_FSLSS 0x00000004U /*!< FS- and LS-only support */
+
+/******************** Bit definition forUSB_OTG_DCFG register ********************/
+
+#define USB_OTG_DCFG_DSPD 0x00000003U /*!< Device speed */
+#define USB_OTG_DCFG_DSPD_0 0x00000001U /*!<Bit 0 */
+#define USB_OTG_DCFG_DSPD_1 0x00000002U /*!<Bit 1 */
+#define USB_OTG_DCFG_NZLSOHSK 0x00000004U /*!< Nonzero-length status OUT handshake */
+
+#define USB_OTG_DCFG_DAD 0x000007F0U /*!< Device address */
+#define USB_OTG_DCFG_DAD_0 0x00000010U /*!<Bit 0 */
+#define USB_OTG_DCFG_DAD_1 0x00000020U /*!<Bit 1 */
+#define USB_OTG_DCFG_DAD_2 0x00000040U /*!<Bit 2 */
+#define USB_OTG_DCFG_DAD_3 0x00000080U /*!<Bit 3 */
+#define USB_OTG_DCFG_DAD_4 0x00000100U /*!<Bit 4 */
+#define USB_OTG_DCFG_DAD_5 0x00000200U /*!<Bit 5 */
+#define USB_OTG_DCFG_DAD_6 0x00000400U /*!<Bit 6 */
+
+#define USB_OTG_DCFG_PFIVL 0x00001800U /*!< Periodic (micro)frame interval */
+#define USB_OTG_DCFG_PFIVL_0 0x00000800U /*!<Bit 0 */
+#define USB_OTG_DCFG_PFIVL_1 0x00001000U /*!<Bit 1 */
+
+#define USB_OTG_DCFG_PERSCHIVL 0x03000000U /*!< Periodic scheduling interval */
+#define USB_OTG_DCFG_PERSCHIVL_0 0x01000000U /*!<Bit 0 */
+#define USB_OTG_DCFG_PERSCHIVL_1 0x02000000U /*!<Bit 1 */
+
+/******************** Bit definition forUSB_OTG_PCGCR register ********************/
+#define USB_OTG_PCGCR_STPPCLK 0x00000001U /*!< Stop PHY clock */
+#define USB_OTG_PCGCR_GATEHCLK 0x00000002U /*!< Gate HCLK */
+#define USB_OTG_PCGCR_PHYSUSP 0x00000010U /*!< PHY suspended */
+
+/******************** Bit definition forUSB_OTG_GOTGINT register ********************/
+#define USB_OTG_GOTGINT_SEDET 0x00000004U /*!< Session end detected */
+#define USB_OTG_GOTGINT_SRSSCHG 0x00000100U /*!< Session request success status change */
+#define USB_OTG_GOTGINT_HNSSCHG 0x00000200U /*!< Host negotiation success status change */
+#define USB_OTG_GOTGINT_HNGDET 0x00020000U /*!< Host negotiation detected */
+#define USB_OTG_GOTGINT_ADTOCHG 0x00040000U /*!< A-device timeout change */
+#define USB_OTG_GOTGINT_DBCDNE 0x00080000U /*!< Debounce done */
+
+/******************** Bit definition forUSB_OTG_DCTL register ********************/
+#define USB_OTG_DCTL_RWUSIG 0x00000001U /*!< Remote wakeup signaling */
+#define USB_OTG_DCTL_SDIS 0x00000002U /*!< Soft disconnect */
+#define USB_OTG_DCTL_GINSTS 0x00000004U /*!< Global IN NAK status */
+#define USB_OTG_DCTL_GONSTS 0x00000008U /*!< Global OUT NAK status */
+
+#define USB_OTG_DCTL_TCTL 0x00000070U /*!< Test control */
+#define USB_OTG_DCTL_TCTL_0 0x00000010U /*!<Bit 0 */
+#define USB_OTG_DCTL_TCTL_1 0x00000020U /*!<Bit 1 */
+#define USB_OTG_DCTL_TCTL_2 0x00000040U /*!<Bit 2 */
+#define USB_OTG_DCTL_SGINAK 0x00000080U /*!< Set global IN NAK */
+#define USB_OTG_DCTL_CGINAK 0x00000100U /*!< Clear global IN NAK */
+#define USB_OTG_DCTL_SGONAK 0x00000200U /*!< Set global OUT NAK */
+#define USB_OTG_DCTL_CGONAK 0x00000400U /*!< Clear global OUT NAK */
+#define USB_OTG_DCTL_POPRGDNE 0x00000800U /*!< Power-on programming done */
+
+/******************** Bit definition forUSB_OTG_HFIR register ********************/
+#define USB_OTG_HFIR_FRIVL 0x0000FFFFU /*!< Frame interval */
+
+/******************** Bit definition forUSB_OTG_HFNUM register ********************/
+#define USB_OTG_HFNUM_FRNUM 0x0000FFFFU /*!< Frame number */
+#define USB_OTG_HFNUM_FTREM 0xFFFF0000U /*!< Frame time remaining */
+
+/******************** Bit definition forUSB_OTG_DSTS register ********************/
+#define USB_OTG_DSTS_SUSPSTS 0x00000001U /*!< Suspend status */
+
+#define USB_OTG_DSTS_ENUMSPD 0x00000006U /*!< Enumerated speed */
+#define USB_OTG_DSTS_ENUMSPD_0 0x00000002U /*!<Bit 0 */
+#define USB_OTG_DSTS_ENUMSPD_1 0x00000004U /*!<Bit 1 */
+#define USB_OTG_DSTS_EERR 0x00000008U /*!< Erratic error */
+#define USB_OTG_DSTS_FNSOF 0x003FFF00U /*!< Frame number of the received SOF */
+
+/******************** Bit definition forUSB_OTG_GAHBCFG register ********************/
+#define USB_OTG_GAHBCFG_GINT 0x00000001U /*!< Global interrupt mask */
+
+#define USB_OTG_GAHBCFG_HBSTLEN 0x0000001EU /*!< Burst length/type */
+#define USB_OTG_GAHBCFG_HBSTLEN_0 0x00000002U /*!<Bit 0 */
+#define USB_OTG_GAHBCFG_HBSTLEN_1 0x00000004U /*!<Bit 1 */
+#define USB_OTG_GAHBCFG_HBSTLEN_2 0x00000008U /*!<Bit 2 */
+#define USB_OTG_GAHBCFG_HBSTLEN_3 0x00000010U /*!<Bit 3 */
+#define USB_OTG_GAHBCFG_DMAEN 0x00000020U /*!< DMA enable */
+#define USB_OTG_GAHBCFG_TXFELVL 0x00000080U /*!< TxFIFO empty level */
+#define USB_OTG_GAHBCFG_PTXFELVL 0x00000100U /*!< Periodic TxFIFO empty level */
+
+/******************** Bit definition forUSB_OTG_GUSBCFG register ********************/
+
+#define USB_OTG_GUSBCFG_TOCAL 0x00000007U /*!< FS timeout calibration */
+#define USB_OTG_GUSBCFG_TOCAL_0 0x00000001U /*!<Bit 0 */
+#define USB_OTG_GUSBCFG_TOCAL_1 0x00000002U /*!<Bit 1 */
+#define USB_OTG_GUSBCFG_TOCAL_2 0x00000004U /*!<Bit 2 */
+#define USB_OTG_GUSBCFG_PHYSEL 0x00000040U /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */
+#define USB_OTG_GUSBCFG_SRPCAP 0x00000100U /*!< SRP-capable */
+#define USB_OTG_GUSBCFG_HNPCAP 0x00000200U /*!< HNP-capable */
+
+#define USB_OTG_GUSBCFG_TRDT 0x00003C00U /*!< USB turnaround time */
+#define USB_OTG_GUSBCFG_TRDT_0 0x00000400U /*!<Bit 0 */
+#define USB_OTG_GUSBCFG_TRDT_1 0x00000800U /*!<Bit 1 */
+#define USB_OTG_GUSBCFG_TRDT_2 0x00001000U /*!<Bit 2 */
+#define USB_OTG_GUSBCFG_TRDT_3 0x00002000U /*!<Bit 3 */
+#define USB_OTG_GUSBCFG_PHYLPCS 0x00008000U /*!< PHY Low-power clock select */
+#define USB_OTG_GUSBCFG_ULPIFSLS 0x00020000U /*!< ULPI FS/LS select */
+#define USB_OTG_GUSBCFG_ULPIAR 0x00040000U /*!< ULPI Auto-resume */
+#define USB_OTG_GUSBCFG_ULPICSM 0x00080000U /*!< ULPI Clock SuspendM */
+#define USB_OTG_GUSBCFG_ULPIEVBUSD 0x00100000U /*!< ULPI External VBUS Drive */
+#define USB_OTG_GUSBCFG_ULPIEVBUSI 0x00200000U /*!< ULPI external VBUS indicator */
+#define USB_OTG_GUSBCFG_TSDPS 0x00400000U /*!< TermSel DLine pulsing selection */
+#define USB_OTG_GUSBCFG_PCCI 0x00800000U /*!< Indicator complement */
+#define USB_OTG_GUSBCFG_PTCI 0x01000000U /*!< Indicator pass through */
+#define USB_OTG_GUSBCFG_ULPIIPD 0x02000000U /*!< ULPI interface protect disable */
+#define USB_OTG_GUSBCFG_FHMOD 0x20000000U /*!< Forced host mode */
+#define USB_OTG_GUSBCFG_FDMOD 0x40000000U /*!< Forced peripheral mode */
+#define USB_OTG_GUSBCFG_CTXPKT 0x80000000U /*!< Corrupt Tx packet */
+
+/******************** Bit definition forUSB_OTG_GRSTCTL register ********************/
+#define USB_OTG_GRSTCTL_CSRST 0x00000001U /*!< Core soft reset */
+#define USB_OTG_GRSTCTL_HSRST 0x00000002U /*!< HCLK soft reset */
+#define USB_OTG_GRSTCTL_FCRST 0x00000004U /*!< Host frame counter reset */
+#define USB_OTG_GRSTCTL_RXFFLSH 0x00000010U /*!< RxFIFO flush */
+#define USB_OTG_GRSTCTL_TXFFLSH 0x00000020U /*!< TxFIFO flush */
+
+#define USB_OTG_GRSTCTL_TXFNUM 0x000007C0U /*!< TxFIFO number */
+#define USB_OTG_GRSTCTL_TXFNUM_0 0x00000040U /*!<Bit 0 */
+#define USB_OTG_GRSTCTL_TXFNUM_1 0x00000080U /*!<Bit 1 */
+#define USB_OTG_GRSTCTL_TXFNUM_2 0x00000100U /*!<Bit 2 */
+#define USB_OTG_GRSTCTL_TXFNUM_3 0x00000200U /*!<Bit 3 */
+#define USB_OTG_GRSTCTL_TXFNUM_4 0x00000400U /*!<Bit 4 */
+#define USB_OTG_GRSTCTL_DMAREQ 0x40000000U /*!< DMA request signal */
+#define USB_OTG_GRSTCTL_AHBIDL 0x80000000U /*!< AHB master idle */
+
+/******************** Bit definition forUSB_OTG_DIEPMSK register ********************/
+#define USB_OTG_DIEPMSK_XFRCM 0x00000001U /*!< Transfer completed interrupt mask */
+#define USB_OTG_DIEPMSK_EPDM 0x00000002U /*!< Endpoint disabled interrupt mask */
+#define USB_OTG_DIEPMSK_TOM 0x00000008U /*!< Timeout condition mask (nonisochronous endpoints) */
+#define USB_OTG_DIEPMSK_ITTXFEMSK 0x00000010U /*!< IN token received when TxFIFO empty mask */
+#define USB_OTG_DIEPMSK_INEPNMM 0x00000020U /*!< IN token received with EP mismatch mask */
+#define USB_OTG_DIEPMSK_INEPNEM 0x00000040U /*!< IN endpoint NAK effective mask */
+#define USB_OTG_DIEPMSK_TXFURM 0x00000100U /*!< FIFO underrun mask */
+#define USB_OTG_DIEPMSK_BIM 0x00000200U /*!< BNA interrupt mask */
+
+/******************** Bit definition forUSB_OTG_HPTXSTS register ********************/
+#define USB_OTG_HPTXSTS_PTXFSAVL 0x0000FFFFU /*!< Periodic transmit data FIFO space available */
+
+#define USB_OTG_HPTXSTS_PTXQSAV 0x00FF0000U /*!< Periodic transmit request queue space available */
+#define USB_OTG_HPTXSTS_PTXQSAV_0 0x00010000U /*!<Bit 0 */
+#define USB_OTG_HPTXSTS_PTXQSAV_1 0x00020000U /*!<Bit 1 */
+#define USB_OTG_HPTXSTS_PTXQSAV_2 0x00040000U /*!<Bit 2 */
+#define USB_OTG_HPTXSTS_PTXQSAV_3 0x00080000U /*!<Bit 3 */
+#define USB_OTG_HPTXSTS_PTXQSAV_4 0x00100000U /*!<Bit 4 */
+#define USB_OTG_HPTXSTS_PTXQSAV_5 0x00200000U /*!<Bit 5 */
+#define USB_OTG_HPTXSTS_PTXQSAV_6 0x00400000U /*!<Bit 6 */
+#define USB_OTG_HPTXSTS_PTXQSAV_7 0x00800000U /*!<Bit 7 */
+
+#define USB_OTG_HPTXSTS_PTXQTOP 0xFF000000U /*!< Top of the periodic transmit request queue */
+#define USB_OTG_HPTXSTS_PTXQTOP_0 0x01000000U /*!<Bit 0 */
+#define USB_OTG_HPTXSTS_PTXQTOP_1 0x02000000U /*!<Bit 1 */
+#define USB_OTG_HPTXSTS_PTXQTOP_2 0x04000000U /*!<Bit 2 */
+#define USB_OTG_HPTXSTS_PTXQTOP_3 0x08000000U /*!<Bit 3 */
+#define USB_OTG_HPTXSTS_PTXQTOP_4 0x10000000U /*!<Bit 4 */
+#define USB_OTG_HPTXSTS_PTXQTOP_5 0x20000000U /*!<Bit 5 */
+#define USB_OTG_HPTXSTS_PTXQTOP_6 0x40000000U /*!<Bit 6 */
+#define USB_OTG_HPTXSTS_PTXQTOP_7 0x80000000U /*!<Bit 7 */
+
+/******************** Bit definition forUSB_OTG_HAINT register ********************/
+#define USB_OTG_HAINT_HAINT 0x0000FFFFU /*!< Channel interrupts */
+
+/******************** Bit definition forUSB_OTG_DOEPMSK register ********************/
+#define USB_OTG_DOEPMSK_XFRCM 0x00000001U /*!< Transfer completed interrupt mask */
+#define USB_OTG_DOEPMSK_EPDM 0x00000002U /*!< Endpoint disabled interrupt mask */
+#define USB_OTG_DOEPMSK_STUPM 0x00000008U /*!< SETUP phase done mask */
+#define USB_OTG_DOEPMSK_OTEPDM 0x00000010U /*!< OUT token received when endpoint disabled mask */
+#define USB_OTG_DOEPMSK_B2BSTUP 0x00000040U /*!< Back-to-back SETUP packets received mask */
+#define USB_OTG_DOEPMSK_OPEM 0x00000100U /*!< OUT packet error mask */
+#define USB_OTG_DOEPMSK_BOIM 0x00000200U /*!< BNA interrupt mask */
+
+/******************** Bit definition forUSB_OTG_GINTSTS register ********************/
+#define USB_OTG_GINTSTS_CMOD 0x00000001U /*!< Current mode of operation */
+#define USB_OTG_GINTSTS_MMIS 0x00000002U /*!< Mode mismatch interrupt */
+#define USB_OTG_GINTSTS_OTGINT 0x00000004U /*!< OTG interrupt */
+#define USB_OTG_GINTSTS_SOF 0x00000008U /*!< Start of frame */
+#define USB_OTG_GINTSTS_RXFLVL 0x00000010U /*!< RxFIFO nonempty */
+#define USB_OTG_GINTSTS_NPTXFE 0x00000020U /*!< Nonperiodic TxFIFO empty */
+#define USB_OTG_GINTSTS_GINAKEFF 0x00000040U /*!< Global IN nonperiodic NAK effective */
+#define USB_OTG_GINTSTS_BOUTNAKEFF 0x00000080U /*!< Global OUT NAK effective */
+#define USB_OTG_GINTSTS_ESUSP 0x00000400U /*!< Early suspend */
+#define USB_OTG_GINTSTS_USBSUSP 0x00000800U /*!< USB suspend */
+#define USB_OTG_GINTSTS_USBRST 0x00001000U /*!< USB reset */
+#define USB_OTG_GINTSTS_ENUMDNE 0x00002000U /*!< Enumeration done */
+#define USB_OTG_GINTSTS_ISOODRP 0x00004000U /*!< Isochronous OUT packet dropped interrupt */
+#define USB_OTG_GINTSTS_EOPF 0x00008000U /*!< End of periodic frame interrupt */
+#define USB_OTG_GINTSTS_IEPINT 0x00040000U /*!< IN endpoint interrupt */
+#define USB_OTG_GINTSTS_OEPINT 0x00080000U /*!< OUT endpoint interrupt */
+#define USB_OTG_GINTSTS_IISOIXFR 0x00100000U /*!< Incomplete isochronous IN transfer */
+#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT 0x00200000U /*!< Incomplete periodic transfer */
+#define USB_OTG_GINTSTS_DATAFSUSP 0x00400000U /*!< Data fetch suspended */
+#define USB_OTG_GINTSTS_HPRTINT 0x01000000U /*!< Host port interrupt */
+#define USB_OTG_GINTSTS_HCINT 0x02000000U /*!< Host channels interrupt */
+#define USB_OTG_GINTSTS_PTXFE 0x04000000U /*!< Periodic TxFIFO empty */
+#define USB_OTG_GINTSTS_CIDSCHG 0x10000000U /*!< Connector ID status change */
+#define USB_OTG_GINTSTS_DISCINT 0x20000000U /*!< Disconnect detected interrupt */
+#define USB_OTG_GINTSTS_SRQINT 0x40000000U /*!< Session request/new session detected interrupt */
+#define USB_OTG_GINTSTS_WKUINT 0x80000000U /*!< Resume/remote wakeup detected interrupt */
+
+/******************** Bit definition forUSB_OTG_GINTMSK register ********************/
+#define USB_OTG_GINTMSK_MMISM 0x00000002U /*!< Mode mismatch interrupt mask */
+#define USB_OTG_GINTMSK_OTGINT 0x00000004U /*!< OTG interrupt mask */
+#define USB_OTG_GINTMSK_SOFM 0x00000008U /*!< Start of frame mask */
+#define USB_OTG_GINTMSK_RXFLVLM 0x00000010U /*!< Receive FIFO nonempty mask */
+#define USB_OTG_GINTMSK_NPTXFEM 0x00000020U /*!< Nonperiodic TxFIFO empty mask */
+#define USB_OTG_GINTMSK_GINAKEFFM 0x00000040U /*!< Global nonperiodic IN NAK effective mask */
+#define USB_OTG_GINTMSK_GONAKEFFM 0x00000080U /*!< Global OUT NAK effective mask */
+#define USB_OTG_GINTMSK_ESUSPM 0x00000400U /*!< Early suspend mask */
+#define USB_OTG_GINTMSK_USBSUSPM 0x00000800U /*!< USB suspend mask */
+#define USB_OTG_GINTMSK_USBRST 0x00001000U /*!< USB reset mask */
+#define USB_OTG_GINTMSK_ENUMDNEM 0x00002000U /*!< Enumeration done mask */
+#define USB_OTG_GINTMSK_ISOODRPM 0x00004000U /*!< Isochronous OUT packet dropped interrupt mask */
+#define USB_OTG_GINTMSK_EOPFM 0x00008000U /*!< End of periodic frame interrupt mask */
+#define USB_OTG_GINTMSK_EPMISM 0x00020000U /*!< Endpoint mismatch interrupt mask */
+#define USB_OTG_GINTMSK_IEPINT 0x00040000U /*!< IN endpoints interrupt mask */
+#define USB_OTG_GINTMSK_OEPINT 0x00080000U /*!< OUT endpoints interrupt mask */
+#define USB_OTG_GINTMSK_IISOIXFRM 0x00100000U /*!< Incomplete isochronous IN transfer mask */
+#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM 0x00200000U /*!< Incomplete periodic transfer mask */
+#define USB_OTG_GINTMSK_FSUSPM 0x00400000U /*!< Data fetch suspended mask */
+#define USB_OTG_GINTMSK_PRTIM 0x01000000U /*!< Host port interrupt mask */
+#define USB_OTG_GINTMSK_HCIM 0x02000000U /*!< Host channels interrupt mask */
+#define USB_OTG_GINTMSK_PTXFEM 0x04000000U /*!< Periodic TxFIFO empty mask */
+#define USB_OTG_GINTMSK_CIDSCHGM 0x10000000U /*!< Connector ID status change mask */
+#define USB_OTG_GINTMSK_DISCINT 0x20000000U /*!< Disconnect detected interrupt mask */
+#define USB_OTG_GINTMSK_SRQIM 0x40000000U /*!< Session request/new session detected interrupt mask */
+#define USB_OTG_GINTMSK_WUIM 0x80000000U /*!< Resume/remote wakeup detected interrupt mask */
+
+/******************** Bit definition forUSB_OTG_DAINT register ********************/
+#define USB_OTG_DAINT_IEPINT 0x0000FFFFU /*!< IN endpoint interrupt bits */
+#define USB_OTG_DAINT_OEPINT 0xFFFF0000U /*!< OUT endpoint interrupt bits */
+
+/******************** Bit definition forUSB_OTG_HAINTMSK register ********************/
+#define USB_OTG_HAINTMSK_HAINTM 0x0000FFFFU /*!< Channel interrupt mask */
+
+/******************** Bit definition for USB_OTG_GRXSTSP register ********************/
+#define USB_OTG_GRXSTSP_EPNUM 0x0000000FU /*!< IN EP interrupt mask bits */
+#define USB_OTG_GRXSTSP_BCNT 0x00007FF0U /*!< OUT EP interrupt mask bits */
+#define USB_OTG_GRXSTSP_DPID 0x00018000U /*!< OUT EP interrupt mask bits */
+#define USB_OTG_GRXSTSP_PKTSTS 0x001E0000U /*!< OUT EP interrupt mask bits */
+
+/******************** Bit definition forUSB_OTG_DAINTMSK register ********************/
+#define USB_OTG_DAINTMSK_IEPM 0x0000FFFFU /*!< IN EP interrupt mask bits */
+#define USB_OTG_DAINTMSK_OEPM 0xFFFF0000U /*!< OUT EP interrupt mask bits */
+
+/******************** Bit definition for OTG register ********************/
+
+#define USB_OTG_CHNUM 0x0000000FU /*!< Channel number */
+#define USB_OTG_CHNUM_0 0x00000001U /*!<Bit 0 */
+#define USB_OTG_CHNUM_1 0x00000002U /*!<Bit 1 */
+#define USB_OTG_CHNUM_2 0x00000004U /*!<Bit 2 */
+#define USB_OTG_CHNUM_3 0x00000008U /*!<Bit 3 */
+#define USB_OTG_BCNT 0x00007FF0U /*!< Byte count */
+
+#define USB_OTG_DPID 0x00018000U /*!< Data PID */
+#define USB_OTG_DPID_0 0x00008000U /*!<Bit 0 */
+#define USB_OTG_DPID_1 0x00010000U /*!<Bit 1 */
+
+#define USB_OTG_PKTSTS 0x001E0000U /*!< Packet status */
+#define USB_OTG_PKTSTS_0 0x00020000U /*!<Bit 0 */
+#define USB_OTG_PKTSTS_1 0x00040000U /*!<Bit 1 */
+#define USB_OTG_PKTSTS_2 0x00080000U /*!<Bit 2 */
+#define USB_OTG_PKTSTS_3 0x00100000U /*!<Bit 3 */
+
+#define USB_OTG_EPNUM 0x0000000FU /*!< Endpoint number */
+#define USB_OTG_EPNUM_0 0x00000001U /*!<Bit 0 */
+#define USB_OTG_EPNUM_1 0x00000002U /*!<Bit 1 */
+#define USB_OTG_EPNUM_2 0x00000004U /*!<Bit 2 */
+#define USB_OTG_EPNUM_3 0x00000008U /*!<Bit 3 */
+
+#define USB_OTG_FRMNUM 0x01E00000U /*!< Frame number */
+#define USB_OTG_FRMNUM_0 0x00200000U /*!<Bit 0 */
+#define USB_OTG_FRMNUM_1 0x00400000U /*!<Bit 1 */
+#define USB_OTG_FRMNUM_2 0x00800000U /*!<Bit 2 */
+#define USB_OTG_FRMNUM_3 0x01000000U /*!<Bit 3 */
+
+/******************** Bit definition for OTG register ********************/
+
+#define USB_OTG_CHNUM 0x0000000FU /*!< Channel number */
+#define USB_OTG_CHNUM_0 0x00000001U /*!<Bit 0 */
+#define USB_OTG_CHNUM_1 0x00000002U /*!<Bit 1 */
+#define USB_OTG_CHNUM_2 0x00000004U /*!<Bit 2 */
+#define USB_OTG_CHNUM_3 0x00000008U /*!<Bit 3 */
+#define USB_OTG_BCNT 0x00007FF0U /*!< Byte count */
+
+#define USB_OTG_DPID 0x00018000U /*!< Data PID */
+#define USB_OTG_DPID_0 0x00008000U /*!<Bit 0 */
+#define USB_OTG_DPID_1 0x00010000U /*!<Bit 1 */
+
+#define USB_OTG_PKTSTS 0x001E0000U /*!< Packet status */
+#define USB_OTG_PKTSTS_0 0x00020000U /*!<Bit 0 */
+#define USB_OTG_PKTSTS_1 0x00040000U /*!<Bit 1 */
+#define USB_OTG_PKTSTS_2 0x00080000U /*!<Bit 2 */
+#define USB_OTG_PKTSTS_3 0x00100000U /*!<Bit 3 */
+
+#define USB_OTG_EPNUM 0x0000000FU /*!< Endpoint number */
+#define USB_OTG_EPNUM_0 0x00000001U /*!<Bit 0 */
+#define USB_OTG_EPNUM_1 0x00000002U /*!<Bit 1 */
+#define USB_OTG_EPNUM_2 0x00000004U /*!<Bit 2 */
+#define USB_OTG_EPNUM_3 0x00000008U /*!<Bit 3 */
+
+#define USB_OTG_FRMNUM 0x01E00000U /*!< Frame number */
+#define USB_OTG_FRMNUM_0 0x00200000U /*!<Bit 0 */
+#define USB_OTG_FRMNUM_1 0x00400000U /*!<Bit 1 */
+#define USB_OTG_FRMNUM_2 0x00800000U /*!<Bit 2 */
+#define USB_OTG_FRMNUM_3 0x01000000U /*!<Bit 3 */
+
+/******************** Bit definition forUSB_OTG_GRXFSIZ register ********************/
+#define USB_OTG_GRXFSIZ_RXFD 0x0000FFFFU /*!< RxFIFO depth */
+
+/******************** Bit definition forUSB_OTG_DVBUSDIS register ********************/
+#define USB_OTG_DVBUSDIS_VBUSDT 0x0000FFFFU /*!< Device VBUS discharge time */
+
+/******************** Bit definition for OTG register ********************/
+#define USB_OTG_NPTXFSA 0x0000FFFFU /*!< Nonperiodic transmit RAM start address */
+#define USB_OTG_NPTXFD 0xFFFF0000U /*!< Nonperiodic TxFIFO depth */
+#define USB_OTG_TX0FSA 0x0000FFFFU /*!< Endpoint 0 transmit RAM start address */
+#define USB_OTG_TX0FD 0xFFFF0000U /*!< Endpoint 0 TxFIFO depth */
+
+/******************** Bit definition forUSB_OTG_DVBUSPULSE register ********************/
+#define USB_OTG_DVBUSPULSE_DVBUSP 0x00000FFFU /*!< Device VBUS pulsing time */
+
+/******************** Bit definition forUSB_OTG_GNPTXSTS register ********************/
+#define USB_OTG_GNPTXSTS_NPTXFSAV 0x0000FFFFU /*!< Nonperiodic TxFIFO space available */
+
+#define USB_OTG_GNPTXSTS_NPTQXSAV 0x00FF0000U /*!< Nonperiodic transmit request queue space available */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_0 0x00010000U /*!<Bit 0 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_1 0x00020000U /*!<Bit 1 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_2 0x00040000U /*!<Bit 2 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_3 0x00080000U /*!<Bit 3 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_4 0x00100000U /*!<Bit 4 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_5 0x00200000U /*!<Bit 5 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_6 0x00400000U /*!<Bit 6 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_7 0x00800000U /*!<Bit 7 */
+
+#define USB_OTG_GNPTXSTS_NPTXQTOP 0x7F000000U /*!< Top of the nonperiodic transmit request queue */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_0 0x01000000U /*!<Bit 0 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_1 0x02000000U /*!<Bit 1 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_2 0x04000000U /*!<Bit 2 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_3 0x08000000U /*!<Bit 3 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_4 0x10000000U /*!<Bit 4 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_5 0x20000000U /*!<Bit 5 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_6 0x40000000U /*!<Bit 6 */
+
+/******************** Bit definition forUSB_OTG_DTHRCTL register ********************/
+#define USB_OTG_DTHRCTL_NONISOTHREN 0x00000001U /*!< Nonisochronous IN endpoints threshold enable */
+#define USB_OTG_DTHRCTL_ISOTHREN 0x00000002U /*!< ISO IN endpoint threshold enable */
+
+#define USB_OTG_DTHRCTL_TXTHRLEN 0x000007FCU /*!< Transmit threshold length */
+#define USB_OTG_DTHRCTL_TXTHRLEN_0 0x00000004U /*!<Bit 0 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_1 0x00000008U /*!<Bit 1 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_2 0x00000010U /*!<Bit 2 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_3 0x00000020U /*!<Bit 3 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_4 0x00000040U /*!<Bit 4 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_5 0x00000080U /*!<Bit 5 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_6 0x00000100U /*!<Bit 6 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_7 0x00000200U /*!<Bit 7 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_8 0x00000400U /*!<Bit 8 */
+#define USB_OTG_DTHRCTL_RXTHREN 0x00010000U /*!< Receive threshold enable */
+
+#define USB_OTG_DTHRCTL_RXTHRLEN 0x03FE0000U /*!< Receive threshold length */
+#define USB_OTG_DTHRCTL_RXTHRLEN_0 0x00020000U /*!<Bit 0 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_1 0x00040000U /*!<Bit 1 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_2 0x00080000U /*!<Bit 2 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_3 0x00100000U /*!<Bit 3 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_4 0x00200000U /*!<Bit 4 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_5 0x00400000U /*!<Bit 5 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_6 0x00800000U /*!<Bit 6 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_7 0x01000000U /*!<Bit 7 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_8 0x02000000U /*!<Bit 8 */
+#define USB_OTG_DTHRCTL_ARPEN 0x08000000U /*!< Arbiter parking enable */
+
+/******************** Bit definition forUSB_OTG_DIEPEMPMSK register ********************/
+#define USB_OTG_DIEPEMPMSK_INEPTXFEM 0x0000FFFFU /*!< IN EP Tx FIFO empty interrupt mask bits */
+
+/******************** Bit definition forUSB_OTG_DEACHINT register ********************/
+#define USB_OTG_DEACHINT_IEP1INT 0x00000002U /*!< IN endpoint 1interrupt bit */
+#define USB_OTG_DEACHINT_OEP1INT 0x00020000U /*!< OUT endpoint 1 interrupt bit */
+
+/******************** Bit definition forUSB_OTG_GCCFG register ********************/
+#define USB_OTG_GCCFG_PWRDWN 0x00010000U /*!< Power down */
+#define USB_OTG_GCCFG_I2CPADEN 0x00020000U /*!< Enable I2C bus connection for the external I2C PHY interface */
+#define USB_OTG_GCCFG_VBUSASEN 0x00040000U /*!< Enable the VBUS sensing device */
+#define USB_OTG_GCCFG_VBUSBSEN 0x00080000U /*!< Enable the VBUS sensing device */
+#define USB_OTG_GCCFG_SOFOUTEN 0x00100000U /*!< SOF output enable */
+#define USB_OTG_GCCFG_NOVBUSSENS 0x00200000U /*!< VBUS sensing disable option */
+
+/******************** Bit definition forUSB_OTG_DEACHINTMSK register ********************/
+#define USB_OTG_DEACHINTMSK_IEP1INTM 0x00000002U /*!< IN Endpoint 1 interrupt mask bit */
+#define USB_OTG_DEACHINTMSK_OEP1INTM 0x00020000U /*!< OUT Endpoint 1 interrupt mask bit */
+
+/******************** Bit definition forUSB_OTG_CID register ********************/
+#define USB_OTG_CID_PRODUCT_ID 0xFFFFFFFFU /*!< Product ID field */
+
+/******************** Bit definition forUSB_OTG_DIEPEACHMSK1 register ********************/
+#define USB_OTG_DIEPEACHMSK1_XFRCM 0x00000001U /*!< Transfer completed interrupt mask */
+#define USB_OTG_DIEPEACHMSK1_EPDM 0x00000002U /*!< Endpoint disabled interrupt mask */
+#define USB_OTG_DIEPEACHMSK1_TOM 0x00000008U /*!< Timeout condition mask (nonisochronous endpoints) */
+#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK 0x00000010U /*!< IN token received when TxFIFO empty mask */
+#define USB_OTG_DIEPEACHMSK1_INEPNMM 0x00000020U /*!< IN token received with EP mismatch mask */
+#define USB_OTG_DIEPEACHMSK1_INEPNEM 0x00000040U /*!< IN endpoint NAK effective mask */
+#define USB_OTG_DIEPEACHMSK1_TXFURM 0x00000100U /*!< FIFO underrun mask */
+#define USB_OTG_DIEPEACHMSK1_BIM 0x00000200U /*!< BNA interrupt mask */
+#define USB_OTG_DIEPEACHMSK1_NAKM 0x00002000U /*!< NAK interrupt mask */
+
+/******************** Bit definition forUSB_OTG_HPRT register ********************/
+#define USB_OTG_HPRT_PCSTS 0x00000001U /*!< Port connect status */
+#define USB_OTG_HPRT_PCDET 0x00000002U /*!< Port connect detected */
+#define USB_OTG_HPRT_PENA 0x00000004U /*!< Port enable */
+#define USB_OTG_HPRT_PENCHNG 0x00000008U /*!< Port enable/disable change */
+#define USB_OTG_HPRT_POCA 0x00000010U /*!< Port overcurrent active */
+#define USB_OTG_HPRT_POCCHNG 0x00000020U /*!< Port overcurrent change */
+#define USB_OTG_HPRT_PRES 0x00000040U /*!< Port resume */
+#define USB_OTG_HPRT_PSUSP 0x00000080U /*!< Port suspend */
+#define USB_OTG_HPRT_PRST 0x00000100U /*!< Port reset */
+
+#define USB_OTG_HPRT_PLSTS 0x00000C00U /*!< Port line status */
+#define USB_OTG_HPRT_PLSTS_0 0x00000400U /*!<Bit 0 */
+#define USB_OTG_HPRT_PLSTS_1 0x00000800U /*!<Bit 1 */
+#define USB_OTG_HPRT_PPWR 0x00001000U /*!< Port power */
+
+#define USB_OTG_HPRT_PTCTL 0x0001E000U /*!< Port test control */
+#define USB_OTG_HPRT_PTCTL_0 0x00002000U /*!<Bit 0 */
+#define USB_OTG_HPRT_PTCTL_1 0x00004000U /*!<Bit 1 */
+#define USB_OTG_HPRT_PTCTL_2 0x00008000U /*!<Bit 2 */
+#define USB_OTG_HPRT_PTCTL_3 0x00010000U /*!<Bit 3 */
+
+#define USB_OTG_HPRT_PSPD 0x00060000U /*!< Port speed */
+#define USB_OTG_HPRT_PSPD_0 0x00020000U /*!<Bit 0 */
+#define USB_OTG_HPRT_PSPD_1 0x00040000U /*!<Bit 1 */
+
+/******************** Bit definition forUSB_OTG_DOEPEACHMSK1 register ********************/
+#define USB_OTG_DOEPEACHMSK1_XFRCM 0x00000001U /*!< Transfer completed interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_EPDM 0x00000002U /*!< Endpoint disabled interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_TOM 0x00000008U /*!< Timeout condition mask */
+#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK 0x00000010U /*!< IN token received when TxFIFO empty mask */
+#define USB_OTG_DOEPEACHMSK1_INEPNMM 0x00000020U /*!< IN token received with EP mismatch mask */
+#define USB_OTG_DOEPEACHMSK1_INEPNEM 0x00000040U /*!< IN endpoint NAK effective mask */
+#define USB_OTG_DOEPEACHMSK1_TXFURM 0x00000100U /*!< OUT packet error mask */
+#define USB_OTG_DOEPEACHMSK1_BIM 0x00000200U /*!< BNA interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_BERRM 0x00001000U /*!< Bubble error interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_NAKM 0x00002000U /*!< NAK interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_NYETM 0x00004000U /*!< NYET interrupt mask */
+
+/******************** Bit definition forUSB_OTG_HPTXFSIZ register ********************/
+#define USB_OTG_HPTXFSIZ_PTXSA 0x0000FFFFU /*!< Host periodic TxFIFO start address */
+#define USB_OTG_HPTXFSIZ_PTXFD 0xFFFF0000U /*!< Host periodic TxFIFO depth */
+
+/******************** Bit definition forUSB_OTG_DIEPCTL register ********************/
+#define USB_OTG_DIEPCTL_MPSIZ 0x000007FFU /*!< Maximum packet size */
+#define USB_OTG_DIEPCTL_USBAEP 0x00008000U /*!< USB active endpoint */
+#define USB_OTG_DIEPCTL_EONUM_DPID 0x00010000U /*!< Even/odd frame */
+#define USB_OTG_DIEPCTL_NAKSTS 0x00020000U /*!< NAK status */
+
+#define USB_OTG_DIEPCTL_EPTYP 0x000C0000U /*!< Endpoint type */
+#define USB_OTG_DIEPCTL_EPTYP_0 0x00040000U /*!<Bit 0 */
+#define USB_OTG_DIEPCTL_EPTYP_1 0x00080000U /*!<Bit 1 */
+#define USB_OTG_DIEPCTL_STALL 0x00200000U /*!< STALL handshake */
+
+#define USB_OTG_DIEPCTL_TXFNUM 0x03C00000U /*!< TxFIFO number */
+#define USB_OTG_DIEPCTL_TXFNUM_0 0x00400000U /*!<Bit 0 */
+#define USB_OTG_DIEPCTL_TXFNUM_1 0x00800000U /*!<Bit 1 */
+#define USB_OTG_DIEPCTL_TXFNUM_2 0x01000000U /*!<Bit 2 */
+#define USB_OTG_DIEPCTL_TXFNUM_3 0x02000000U /*!<Bit 3 */
+#define USB_OTG_DIEPCTL_CNAK 0x04000000U /*!< Clear NAK */
+#define USB_OTG_DIEPCTL_SNAK 0x08000000U /*!< Set NAK */
+#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM 0x10000000U /*!< Set DATA0 PID */
+#define USB_OTG_DIEPCTL_SODDFRM 0x20000000U /*!< Set odd frame */
+#define USB_OTG_DIEPCTL_EPDIS 0x40000000U /*!< Endpoint disable */
+#define USB_OTG_DIEPCTL_EPENA 0x80000000U /*!< Endpoint enable */
+
+/******************** Bit definition forUSB_OTG_HCCHAR register ********************/
+#define USB_OTG_HCCHAR_MPSIZ 0x000007FFU /*!< Maximum packet size */
+
+#define USB_OTG_HCCHAR_EPNUM 0x00007800U /*!< Endpoint number */
+#define USB_OTG_HCCHAR_EPNUM_0 0x00000800U /*!<Bit 0 */
+#define USB_OTG_HCCHAR_EPNUM_1 0x00001000U /*!<Bit 1 */
+#define USB_OTG_HCCHAR_EPNUM_2 0x00002000U /*!<Bit 2 */
+#define USB_OTG_HCCHAR_EPNUM_3 0x00004000U /*!<Bit 3 */
+#define USB_OTG_HCCHAR_EPDIR 0x00008000U /*!< Endpoint direction */
+#define USB_OTG_HCCHAR_LSDEV 0x00020000U /*!< Low-speed device */
+
+#define USB_OTG_HCCHAR_EPTYP 0x000C0000U /*!< Endpoint type */
+#define USB_OTG_HCCHAR_EPTYP_0 0x00040000U /*!<Bit 0 */
+#define USB_OTG_HCCHAR_EPTYP_1 0x00080000U /*!<Bit 1 */
+
+#define USB_OTG_HCCHAR_MC 0x00300000U /*!< Multi Count (MC) / Error Count (EC) */
+#define USB_OTG_HCCHAR_MC_0 0x00100000U /*!<Bit 0 */
+#define USB_OTG_HCCHAR_MC_1 0x00200000U /*!<Bit 1 */
+
+#define USB_OTG_HCCHAR_DAD 0x1FC00000U /*!< Device address */
+#define USB_OTG_HCCHAR_DAD_0 0x00400000U /*!<Bit 0 */
+#define USB_OTG_HCCHAR_DAD_1 0x00800000U /*!<Bit 1 */
+#define USB_OTG_HCCHAR_DAD_2 0x01000000U /*!<Bit 2 */
+#define USB_OTG_HCCHAR_DAD_3 0x02000000U /*!<Bit 3 */
+#define USB_OTG_HCCHAR_DAD_4 0x04000000U /*!<Bit 4 */
+#define USB_OTG_HCCHAR_DAD_5 0x08000000U /*!<Bit 5 */
+#define USB_OTG_HCCHAR_DAD_6 0x10000000U /*!<Bit 6 */
+#define USB_OTG_HCCHAR_ODDFRM 0x20000000U /*!< Odd frame */
+#define USB_OTG_HCCHAR_CHDIS 0x40000000U /*!< Channel disable */
+#define USB_OTG_HCCHAR_CHENA 0x80000000U /*!< Channel enable */
+
+/******************** Bit definition forUSB_OTG_HCSPLT register ********************/
+
+#define USB_OTG_HCSPLT_PRTADDR 0x0000007FU /*!< Port address */
+#define USB_OTG_HCSPLT_PRTADDR_0 0x00000001U /*!<Bit 0 */
+#define USB_OTG_HCSPLT_PRTADDR_1 0x00000002U /*!<Bit 1 */
+#define USB_OTG_HCSPLT_PRTADDR_2 0x00000004U /*!<Bit 2 */
+#define USB_OTG_HCSPLT_PRTADDR_3 0x00000008U /*!<Bit 3 */
+#define USB_OTG_HCSPLT_PRTADDR_4 0x00000010U /*!<Bit 4 */
+#define USB_OTG_HCSPLT_PRTADDR_5 0x00000020U /*!<Bit 5 */
+#define USB_OTG_HCSPLT_PRTADDR_6 0x00000040U /*!<Bit 6 */
+
+#define USB_OTG_HCSPLT_HUBADDR 0x00003F80U /*!< Hub address */
+#define USB_OTG_HCSPLT_HUBADDR_0 0x00000080U /*!<Bit 0 */
+#define USB_OTG_HCSPLT_HUBADDR_1 0x00000100U /*!<Bit 1 */
+#define USB_OTG_HCSPLT_HUBADDR_2 0x00000200U /*!<Bit 2 */
+#define USB_OTG_HCSPLT_HUBADDR_3 0x00000400U /*!<Bit 3 */
+#define USB_OTG_HCSPLT_HUBADDR_4 0x00000800U /*!<Bit 4 */
+#define USB_OTG_HCSPLT_HUBADDR_5 0x00001000U /*!<Bit 5 */
+#define USB_OTG_HCSPLT_HUBADDR_6 0x00002000U /*!<Bit 6 */
+
+#define USB_OTG_HCSPLT_XACTPOS 0x0000C000U /*!< XACTPOS */
+#define USB_OTG_HCSPLT_XACTPOS_0 0x00004000U /*!<Bit 0 */
+#define USB_OTG_HCSPLT_XACTPOS_1 0x00008000U /*!<Bit 1 */
+#define USB_OTG_HCSPLT_COMPLSPLT 0x00010000U /*!< Do complete split */
+#define USB_OTG_HCSPLT_SPLITEN 0x80000000U /*!< Split enable */
+
+/******************** Bit definition forUSB_OTG_HCINT register ********************/
+#define USB_OTG_HCINT_XFRC 0x00000001U /*!< Transfer completed */
+#define USB_OTG_HCINT_CHH 0x00000002U /*!< Channel halted */
+#define USB_OTG_HCINT_AHBERR 0x00000004U /*!< AHB error */
+#define USB_OTG_HCINT_STALL 0x00000008U /*!< STALL response received interrupt */
+#define USB_OTG_HCINT_NAK 0x00000010U /*!< NAK response received interrupt */
+#define USB_OTG_HCINT_ACK 0x00000020U /*!< ACK response received/transmitted interrupt */
+#define USB_OTG_HCINT_NYET 0x00000040U /*!< Response received interrupt */
+#define USB_OTG_HCINT_TXERR 0x00000080U /*!< Transaction error */
+#define USB_OTG_HCINT_BBERR 0x00000100U /*!< Babble error */
+#define USB_OTG_HCINT_FRMOR 0x00000200U /*!< Frame overrun */
+#define USB_OTG_HCINT_DTERR 0x00000400U /*!< Data toggle error */
+
+/******************** Bit definition forUSB_OTG_DIEPINT register ********************/
+#define USB_OTG_DIEPINT_XFRC 0x00000001U /*!< Transfer completed interrupt */
+#define USB_OTG_DIEPINT_EPDISD 0x00000002U /*!< Endpoint disabled interrupt */
+#define USB_OTG_DIEPINT_TOC 0x00000008U /*!< Timeout condition */
+#define USB_OTG_DIEPINT_ITTXFE 0x00000010U /*!< IN token received when TxFIFO is empty */
+#define USB_OTG_DIEPINT_INEPNE 0x00000040U /*!< IN endpoint NAK effective */
+#define USB_OTG_DIEPINT_TXFE 0x00000080U /*!< Transmit FIFO empty */
+#define USB_OTG_DIEPINT_TXFIFOUDRN 0x00000100U /*!< Transmit Fifo Underrun */
+#define USB_OTG_DIEPINT_BNA 0x00000200U /*!< Buffer not available interrupt */
+#define USB_OTG_DIEPINT_PKTDRPSTS 0x00000800U /*!< Packet dropped status */
+#define USB_OTG_DIEPINT_BERR 0x00001000U /*!< Babble error interrupt */
+#define USB_OTG_DIEPINT_NAK 0x00002000U /*!< NAK interrupt */
+
+/******************** Bit definition forUSB_OTG_HCINTMSK register ********************/
+#define USB_OTG_HCINTMSK_XFRCM 0x00000001U /*!< Transfer completed mask */
+#define USB_OTG_HCINTMSK_CHHM 0x00000002U /*!< Channel halted mask */
+#define USB_OTG_HCINTMSK_AHBERR 0x00000004U /*!< AHB error */
+#define USB_OTG_HCINTMSK_STALLM 0x00000008U /*!< STALL response received interrupt mask */
+#define USB_OTG_HCINTMSK_NAKM 0x00000010U /*!< NAK response received interrupt mask */
+#define USB_OTG_HCINTMSK_ACKM 0x00000020U /*!< ACK response received/transmitted interrupt mask */
+#define USB_OTG_HCINTMSK_NYET 0x00000040U /*!< response received interrupt mask */
+#define USB_OTG_HCINTMSK_TXERRM 0x00000080U /*!< Transaction error mask */
+#define USB_OTG_HCINTMSK_BBERRM 0x00000100U /*!< Babble error mask */
+#define USB_OTG_HCINTMSK_FRMORM 0x00000200U /*!< Frame overrun mask */
+#define USB_OTG_HCINTMSK_DTERRM 0x00000400U /*!< Data toggle error mask */
+
+/******************** Bit definition for USB_OTG_DIEPTSIZ register ********************/
+
+#define USB_OTG_DIEPTSIZ_XFRSIZ 0x0007FFFFU /*!< Transfer size */
+#define USB_OTG_DIEPTSIZ_PKTCNT 0x1FF80000U /*!< Packet count */
+#define USB_OTG_DIEPTSIZ_MULCNT 0x60000000U /*!< Packet count */
+/******************** Bit definition forUSB_OTG_HCTSIZ register ********************/
+#define USB_OTG_HCTSIZ_XFRSIZ 0x0007FFFFU /*!< Transfer size */
+#define USB_OTG_HCTSIZ_PKTCNT 0x1FF80000U /*!< Packet count */
+#define USB_OTG_HCTSIZ_DOPING 0x80000000U /*!< Do PING */
+#define USB_OTG_HCTSIZ_DPID 0x60000000U /*!< Data PID */
+#define USB_OTG_HCTSIZ_DPID_0 0x20000000U /*!<Bit 0 */
+#define USB_OTG_HCTSIZ_DPID_1 0x40000000U /*!<Bit 1 */
+
+/******************** Bit definition forUSB_OTG_DIEPDMA register ********************/
+#define USB_OTG_DIEPDMA_DMAADDR 0xFFFFFFFFU /*!< DMA address */
+
+/******************** Bit definition forUSB_OTG_HCDMA register ********************/
+#define USB_OTG_HCDMA_DMAADDR 0xFFFFFFFFU /*!< DMA address */
+
+/******************** Bit definition forUSB_OTG_DTXFSTS register ********************/
+#define USB_OTG_DTXFSTS_INEPTFSAV 0x0000FFFFU /*!< IN endpoint TxFIFO space available */
+
+/******************** Bit definition forUSB_OTG_DIEPTXF register ********************/
+#define USB_OTG_DIEPTXF_INEPTXSA 0x0000FFFFU /*!< IN endpoint FIFOx transmit RAM start address */
+#define USB_OTG_DIEPTXF_INEPTXFD 0xFFFF0000U /*!< IN endpoint TxFIFO depth */
+
+/******************** Bit definition forUSB_OTG_DOEPCTL register ********************/
+
+#define USB_OTG_DOEPCTL_MPSIZ 0x000007FFU /*!< Maximum packet size */ /*!<Bit 1 */
+#define USB_OTG_DOEPCTL_USBAEP 0x00008000U /*!< USB active endpoint */
+#define USB_OTG_DOEPCTL_NAKSTS 0x00020000U /*!< NAK status */
+#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM 0x10000000U /*!< Set DATA0 PID */
+#define USB_OTG_DOEPCTL_SODDFRM 0x20000000U /*!< Set odd frame */
+#define USB_OTG_DOEPCTL_EPTYP 0x000C0000U /*!< Endpoint type */
+#define USB_OTG_DOEPCTL_EPTYP_0 0x00040000U /*!<Bit 0 */
+#define USB_OTG_DOEPCTL_EPTYP_1 0x00080000U /*!<Bit 1 */
+#define USB_OTG_DOEPCTL_SNPM 0x00100000U /*!< Snoop mode */
+#define USB_OTG_DOEPCTL_STALL 0x00200000U /*!< STALL handshake */
+#define USB_OTG_DOEPCTL_CNAK 0x04000000U /*!< Clear NAK */
+#define USB_OTG_DOEPCTL_SNAK 0x08000000U /*!< Set NAK */
+#define USB_OTG_DOEPCTL_EPDIS 0x40000000U /*!< Endpoint disable */
+#define USB_OTG_DOEPCTL_EPENA 0x80000000U /*!< Endpoint enable */
+
+/******************** Bit definition forUSB_OTG_DOEPINT register ********************/
+#define USB_OTG_DOEPINT_XFRC 0x00000001U /*!< Transfer completed interrupt */
+#define USB_OTG_DOEPINT_EPDISD 0x00000002U /*!< Endpoint disabled interrupt */
+#define USB_OTG_DOEPINT_STUP 0x00000008U /*!< SETUP phase done */
+#define USB_OTG_DOEPINT_OTEPDIS 0x00000010U /*!< OUT token received when endpoint disabled */
+#define USB_OTG_DOEPINT_B2BSTUP 0x00000040U /*!< Back-to-back SETUP packets received */
+#define USB_OTG_DOEPINT_NYET 0x00004000U /*!< NYET interrupt */
+
+/******************** Bit definition forUSB_OTG_DOEPTSIZ register ********************/
+
+#define USB_OTG_DOEPTSIZ_XFRSIZ 0x0007FFFFU /*!< Transfer size */
+#define USB_OTG_DOEPTSIZ_PKTCNT 0x1FF80000U /*!< Packet count */
+
+#define USB_OTG_DOEPTSIZ_STUPCNT 0x60000000U /*!< SETUP packet count */
+#define USB_OTG_DOEPTSIZ_STUPCNT_0 0x20000000U /*!<Bit 0 */
+#define USB_OTG_DOEPTSIZ_STUPCNT_1 0x40000000U /*!<Bit 1 */
+
+/******************** Bit definition for PCGCCTL register ********************/
+#define USB_OTG_PCGCCTL_STOPCLK 0x00000001U /*!< SETUP packet count */
+#define USB_OTG_PCGCCTL_GATECLK 0x00000002U /*!<Bit 0 */
+#define USB_OTG_PCGCCTL_PHYSUSP 0x00000010U /*!<Bit 1 */
+
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup Exported_macros
+ * @{
+ */
+
+/******************************* ADC Instances ********************************/
+#define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) || \
+ ((INSTANCE) == ADC2) || \
+ ((INSTANCE) == ADC3))
+
+/******************************* CAN Instances ********************************/
+#define IS_CAN_ALL_INSTANCE(INSTANCE) (((INSTANCE) == CAN1) || \
+ ((INSTANCE) == CAN2))
+
+/******************************* CRC Instances ********************************/
+#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
+
+/******************************* DAC Instances ********************************/
+#define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC)
+
+/******************************* DCMI Instances *******************************/
+#define IS_DCMI_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DCMI)
+
+/******************************* DMA2D Instances *******************************/
+#define IS_DMA2D_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DMA2D)
+
+/******************************** DMA Instances *******************************/
+#define IS_DMA_STREAM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0) || \
+ ((INSTANCE) == DMA1_Stream1) || \
+ ((INSTANCE) == DMA1_Stream2) || \
+ ((INSTANCE) == DMA1_Stream3) || \
+ ((INSTANCE) == DMA1_Stream4) || \
+ ((INSTANCE) == DMA1_Stream5) || \
+ ((INSTANCE) == DMA1_Stream6) || \
+ ((INSTANCE) == DMA1_Stream7) || \
+ ((INSTANCE) == DMA2_Stream0) || \
+ ((INSTANCE) == DMA2_Stream1) || \
+ ((INSTANCE) == DMA2_Stream2) || \
+ ((INSTANCE) == DMA2_Stream3) || \
+ ((INSTANCE) == DMA2_Stream4) || \
+ ((INSTANCE) == DMA2_Stream5) || \
+ ((INSTANCE) == DMA2_Stream6) || \
+ ((INSTANCE) == DMA2_Stream7))
+
+/******************************* GPIO Instances *******************************/
+#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
+ ((INSTANCE) == GPIOB) || \
+ ((INSTANCE) == GPIOC) || \
+ ((INSTANCE) == GPIOD) || \
+ ((INSTANCE) == GPIOE) || \
+ ((INSTANCE) == GPIOF) || \
+ ((INSTANCE) == GPIOG) || \
+ ((INSTANCE) == GPIOH) || \
+ ((INSTANCE) == GPIOI) || \
+ ((INSTANCE) == GPIOJ) || \
+ ((INSTANCE) == GPIOK))
+
+/******************************** I2C Instances *******************************/
+#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
+ ((INSTANCE) == I2C2) || \
+ ((INSTANCE) == I2C3))
+
+/******************************** I2S Instances *******************************/
+#define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI2) || \
+ ((INSTANCE) == SPI3))
+
+/*************************** I2S Extended Instances ***************************/
+#define IS_I2S_ALL_INSTANCE_EXT(PERIPH) (((INSTANCE) == SPI2) || \
+ ((INSTANCE) == SPI3) || \
+ ((INSTANCE) == I2S2ext) || \
+ ((INSTANCE) == I2S3ext))
+
+/******************************* RNG Instances ********************************/
+#define IS_RNG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RNG)
+
+/****************************** RTC Instances *********************************/
+#define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
+
+/******************************* SAI Instances ********************************/
+#define IS_SAI_ALL_INSTANCE(PERIPH) (((PERIPH) == SAI1_Block_A) || \
+ ((PERIPH) == SAI1_Block_B))
+/* Legacy define */
+#define IS_SAI_BLOCK_PERIPH IS_SAI_ALL_INSTANCE
+
+/******************************** SPI Instances *******************************/
+#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
+ ((INSTANCE) == SPI2) || \
+ ((INSTANCE) == SPI3) || \
+ ((INSTANCE) == SPI4) || \
+ ((INSTANCE) == SPI5) || \
+ ((INSTANCE) == SPI6))
+
+/*************************** SPI Extended Instances ***************************/
+#define IS_SPI_ALL_INSTANCE_EXT(INSTANCE) (((INSTANCE) == SPI1) || \
+ ((INSTANCE) == SPI2) || \
+ ((INSTANCE) == SPI3) || \
+ ((INSTANCE) == SPI4) || \
+ ((INSTANCE) == SPI5) || \
+ ((INSTANCE) == SPI6) || \
+ ((INSTANCE) == I2S2ext) || \
+ ((INSTANCE) == I2S3ext))
+
+/****************** TIM Instances : All supported instances *******************/
+#define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM6) || \
+ ((INSTANCE) == TIM7) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM9) || \
+ ((INSTANCE) == TIM10) || \
+ ((INSTANCE) == TIM11) || \
+ ((INSTANCE) == TIM12) || \
+ ((INSTANCE) == TIM13) || \
+ ((INSTANCE) == TIM14))
+
+/************* TIM Instances : at least 1 capture/compare channel *************/
+#define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM9) || \
+ ((INSTANCE) == TIM10) || \
+ ((INSTANCE) == TIM11) || \
+ ((INSTANCE) == TIM12) || \
+ ((INSTANCE) == TIM13) || \
+ ((INSTANCE) == TIM14))
+
+/************ TIM Instances : at least 2 capture/compare channels *************/
+#define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM9) || \
+ ((INSTANCE) == TIM12))
+
+/************ TIM Instances : at least 3 capture/compare channels *************/
+#define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8))
+
+/************ TIM Instances : at least 4 capture/compare channels *************/
+#define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8))
+
+/******************** TIM Instances : Advanced-control timers *****************/
+#define IS_TIM_ADVANCED_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM8))
+
+/******************* TIM Instances : Timer input XOR function *****************/
+#define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8))
+
+/****************** TIM Instances : DMA requests generation (UDE) *************/
+#define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM6) || \
+ ((INSTANCE) == TIM7) || \
+ ((INSTANCE) == TIM8))
+
+/************ TIM Instances : DMA requests generation (CCxDE) *****************/
+#define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8))
+
+/************ TIM Instances : DMA requests generation (COMDE) *****************/
+#define IS_TIM_CCDMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8))
+
+/******************** TIM Instances : DMA burst feature ***********************/
+#define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8))
+
+/****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/
+#define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM6) || \
+ ((INSTANCE) == TIM7) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM9) || \
+ ((INSTANCE) == TIM12))
+
+/*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
+#define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM9) || \
+ ((INSTANCE) == TIM12))
+
+/********************** TIM Instances : 32 bit Counter ************************/
+#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)(((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM5))
+
+/***************** TIM Instances : external trigger input availabe ************/
+#define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8))
+
+/****************** TIM Instances : remapping capability **********************/
+#define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM11))
+
+/******************* TIM Instances : output(s) available **********************/
+#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
+ ((((INSTANCE) == TIM1) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM2) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM3) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM4) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM5) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM8) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM9) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2))) \
+ || \
+ (((INSTANCE) == TIM10) && \
+ (((CHANNEL) == TIM_CHANNEL_1))) \
+ || \
+ (((INSTANCE) == TIM11) && \
+ (((CHANNEL) == TIM_CHANNEL_1))) \
+ || \
+ (((INSTANCE) == TIM12) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2))) \
+ || \
+ (((INSTANCE) == TIM13) && \
+ (((CHANNEL) == TIM_CHANNEL_1))) \
+ || \
+ (((INSTANCE) == TIM14) && \
+ (((CHANNEL) == TIM_CHANNEL_1))))
+
+/************ TIM Instances : complementary output(s) available ***************/
+#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
+ ((((INSTANCE) == TIM1) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3))) \
+ || \
+ (((INSTANCE) == TIM8) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3))))
+
+/******************** USART Instances : Synchronous mode **********************/
+#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3) || \
+ ((INSTANCE) == USART6))
+
+/******************** UART Instances : Asynchronous mode **********************/
+#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3) || \
+ ((INSTANCE) == UART4) || \
+ ((INSTANCE) == UART5) || \
+ ((INSTANCE) == USART6) || \
+ ((INSTANCE) == UART7) || \
+ ((INSTANCE) == UART8))
+
+/****************** UART Instances : Hardware Flow control ********************/
+#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3) || \
+ ((INSTANCE) == USART6))
+
+/********************* UART Instances : Smard card mode ***********************/
+#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3) || \
+ ((INSTANCE) == USART6))
+
+/*********************** UART Instances : IRDA mode ***************************/
+#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3) || \
+ ((INSTANCE) == UART4) || \
+ ((INSTANCE) == UART5) || \
+ ((INSTANCE) == USART6) || \
+ ((INSTANCE) == UART7) || \
+ ((INSTANCE) == UART8))
+
+/*********************** PCD Instances ****************************************/
+/*********************** PCD Instances ****************************************/
+#define IS_PCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS) || \
+ ((INSTANCE) == USB_OTG_HS))
+
+/*********************** HCD Instances ****************************************/
+#define IS_HCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS) || \
+ ((INSTANCE) == USB_OTG_HS))
+
+/****************************** IWDG Instances ********************************/
+#define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
+
+/****************************** WWDG Instances ********************************/
+#define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
+
+/****************************** SDIO Instances ********************************/
+#define IS_SDIO_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SDIO)
+
+/****************************** USB Exported Constants ************************/
+#define USB_OTG_FS_HOST_MAX_CHANNEL_NBR 8U
+#define USB_OTG_FS_MAX_IN_ENDPOINTS 4U /* Including EP0 */
+#define USB_OTG_FS_MAX_OUT_ENDPOINTS 4U /* Including EP0 */
+#define USB_OTG_FS_TOTAL_FIFO_SIZE 1280U /* in Bytes */
+
+#define USB_OTG_HS_HOST_MAX_CHANNEL_NBR 12U
+#define USB_OTG_HS_MAX_IN_ENDPOINTS 6U /* Including EP0 */
+#define USB_OTG_HS_MAX_OUT_ENDPOINTS 6U /* Including EP0 */
+#define USB_OTG_HS_TOTAL_FIFO_SIZE 4096U /* in Bytes */
+
+/******************************************************************************/
+/* For a painless codes migration between the STM32F4xx device product */
+/* lines, the aliases defined below are put in place to overcome the */
+/* differences in the interrupt handlers and IRQn definitions. */
+/* No need to update developed interrupt code when moving across */
+/* product lines within the same STM32F4 Family */
+/******************************************************************************/
+
+/* Aliases for __IRQn */
+#define FSMC_IRQn FMC_IRQn
+
+/* Aliases for __IRQHandler */
+#define FSMC_IRQHandler FMC_IRQHandler
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* __stm32f427xx_H */
+
+
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Device/ST/STM32F4xx/Include/stm32f429xx.h b/Device/ST/STM32F4xx/Include/stm32f429xx.h
new file mode 100644
index 0000000..40d3474
--- /dev/null
+++ b/Device/ST/STM32F4xx/Include/stm32f429xx.h
@@ -0,0 +1,9118 @@
+/**
+ ******************************************************************************
+ * @file stm32f429xx.h
+ * @author MCD Application Team
+ * @version V2.5.0
+ * @date 22-April-2016
+ * @brief CMSIS STM32F429xx Device Peripheral Access Layer Header File.
+ *
+ * This file contains:
+ * - Data structures and the address mapping for all peripherals
+ * - peripherals registers declarations and bits definition
+ * - Macros to access peripheral’s registers hardware
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/** @addtogroup CMSIS_Device
+ * @{
+ */
+
+/** @addtogroup stm32f429xx
+ * @{
+ */
+
+#ifndef __STM32F429xx_H
+#define __STM32F429xx_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif /* __cplusplus */
+
+/** @addtogroup Configuration_section_for_CMSIS
+ * @{
+ */
+
+/**
+ * @brief Configuration of the Cortex-M4 Processor and Core Peripherals
+ */
+#define __CM4_REV 0x0001U /*!< Core revision r0p1 */
+#define __MPU_PRESENT 1U /*!< STM32F4XX provides an MPU */
+#define __NVIC_PRIO_BITS 4U /*!< STM32F4XX uses 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */
+#define __FPU_PRESENT 1U /*!< FPU present */
+
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_interrupt_number_definition
+ * @{
+ */
+
+/**
+ * @brief STM32F4XX Interrupt Number Definition, according to the selected device
+ * in @ref Library_configuration_section
+ */
+typedef enum
+{
+/****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/
+ NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
+ MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */
+ BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */
+ UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */
+ SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */
+ DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */
+ PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */
+ SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */
+/****** STM32 specific Interrupt Numbers **********************************************************************/
+ WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
+ PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */
+ TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */
+ RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */
+ FLASH_IRQn = 4, /*!< FLASH global Interrupt */
+ RCC_IRQn = 5, /*!< RCC global Interrupt */
+ EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */
+ EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */
+ EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */
+ EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */
+ EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */
+ DMA1_Stream0_IRQn = 11, /*!< DMA1 Stream 0 global Interrupt */
+ DMA1_Stream1_IRQn = 12, /*!< DMA1 Stream 1 global Interrupt */
+ DMA1_Stream2_IRQn = 13, /*!< DMA1 Stream 2 global Interrupt */
+ DMA1_Stream3_IRQn = 14, /*!< DMA1 Stream 3 global Interrupt */
+ DMA1_Stream4_IRQn = 15, /*!< DMA1 Stream 4 global Interrupt */
+ DMA1_Stream5_IRQn = 16, /*!< DMA1 Stream 5 global Interrupt */
+ DMA1_Stream6_IRQn = 17, /*!< DMA1 Stream 6 global Interrupt */
+ ADC_IRQn = 18, /*!< ADC1, ADC2 and ADC3 global Interrupts */
+ CAN1_TX_IRQn = 19, /*!< CAN1 TX Interrupt */
+ CAN1_RX0_IRQn = 20, /*!< CAN1 RX0 Interrupt */
+ CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */
+ CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */
+ EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
+ TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break interrupt and TIM9 global interrupt */
+ TIM1_UP_TIM10_IRQn = 25, /*!< TIM1 Update Interrupt and TIM10 global interrupt */
+ TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */
+ TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
+ TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
+ TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
+ TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
+ I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
+ I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
+ I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
+ I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
+ SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
+ SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
+ USART1_IRQn = 37, /*!< USART1 global Interrupt */
+ USART2_IRQn = 38, /*!< USART2 global Interrupt */
+ USART3_IRQn = 39, /*!< USART3 global Interrupt */
+ EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
+ RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */
+ OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS Wakeup through EXTI line interrupt */
+ TIM8_BRK_TIM12_IRQn = 43, /*!< TIM8 Break Interrupt and TIM12 global interrupt */
+ TIM8_UP_TIM13_IRQn = 44, /*!< TIM8 Update Interrupt and TIM13 global interrupt */
+ TIM8_TRG_COM_TIM14_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */
+ TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */
+ DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */
+ FMC_IRQn = 48, /*!< FMC global Interrupt */
+ SDIO_IRQn = 49, /*!< SDIO global Interrupt */
+ TIM5_IRQn = 50, /*!< TIM5 global Interrupt */
+ SPI3_IRQn = 51, /*!< SPI3 global Interrupt */
+ UART4_IRQn = 52, /*!< UART4 global Interrupt */
+ UART5_IRQn = 53, /*!< UART5 global Interrupt */
+ TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC1&2 underrun error interrupts */
+ TIM7_IRQn = 55, /*!< TIM7 global interrupt */
+ DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */
+ DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */
+ DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */
+ DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */
+ DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */
+ ETH_IRQn = 61, /*!< Ethernet global Interrupt */
+ ETH_WKUP_IRQn = 62, /*!< Ethernet Wakeup through EXTI line Interrupt */
+ CAN2_TX_IRQn = 63, /*!< CAN2 TX Interrupt */
+ CAN2_RX0_IRQn = 64, /*!< CAN2 RX0 Interrupt */
+ CAN2_RX1_IRQn = 65, /*!< CAN2 RX1 Interrupt */
+ CAN2_SCE_IRQn = 66, /*!< CAN2 SCE Interrupt */
+ OTG_FS_IRQn = 67, /*!< USB OTG FS global Interrupt */
+ DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */
+ DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */
+ DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */
+ USART6_IRQn = 71, /*!< USART6 global interrupt */
+ I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */
+ I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */
+ OTG_HS_EP1_OUT_IRQn = 74, /*!< USB OTG HS End Point 1 Out global interrupt */
+ OTG_HS_EP1_IN_IRQn = 75, /*!< USB OTG HS End Point 1 In global interrupt */
+ OTG_HS_WKUP_IRQn = 76, /*!< USB OTG HS Wakeup through EXTI interrupt */
+ OTG_HS_IRQn = 77, /*!< USB OTG HS global interrupt */
+ DCMI_IRQn = 78, /*!< DCMI global interrupt */
+ HASH_RNG_IRQn = 80, /*!< Hash and RNG global interrupt */
+ FPU_IRQn = 81, /*!< FPU global interrupt */
+ UART7_IRQn = 82, /*!< UART7 global interrupt */
+ UART8_IRQn = 83, /*!< UART8 global interrupt */
+ SPI4_IRQn = 84, /*!< SPI4 global Interrupt */
+ SPI5_IRQn = 85, /*!< SPI5 global Interrupt */
+ SPI6_IRQn = 86, /*!< SPI6 global Interrupt */
+ SAI1_IRQn = 87, /*!< SAI1 global Interrupt */
+ LTDC_IRQn = 88, /*!< LTDC global Interrupt */
+ LTDC_ER_IRQn = 89, /*!< LTDC Error global Interrupt */
+ DMA2D_IRQn = 90 /*!< DMA2D global Interrupt */
+} IRQn_Type;
+
+/**
+ * @}
+ */
+
+#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
+#include "system_stm32f4xx.h"
+#include <stdint.h>
+
+/** @addtogroup Peripheral_registers_structures
+ * @{
+ */
+
+/**
+ * @brief Analog to Digital Converter
+ */
+
+typedef struct
+{
+ __IO uint32_t SR; /*!< ADC status register, Address offset: 0x00 */
+ __IO uint32_t CR1; /*!< ADC control register 1, Address offset: 0x04 */
+ __IO uint32_t CR2; /*!< ADC control register 2, Address offset: 0x08 */
+ __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x0C */
+ __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x10 */
+ __IO uint32_t JOFR1; /*!< ADC injected channel data offset register 1, Address offset: 0x14 */
+ __IO uint32_t JOFR2; /*!< ADC injected channel data offset register 2, Address offset: 0x18 */
+ __IO uint32_t JOFR3; /*!< ADC injected channel data offset register 3, Address offset: 0x1C */
+ __IO uint32_t JOFR4; /*!< ADC injected channel data offset register 4, Address offset: 0x20 */
+ __IO uint32_t HTR; /*!< ADC watchdog higher threshold register, Address offset: 0x24 */
+ __IO uint32_t LTR; /*!< ADC watchdog lower threshold register, Address offset: 0x28 */
+ __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x2C */
+ __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x30 */
+ __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x34 */
+ __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x38*/
+ __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x3C */
+ __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x40 */
+ __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x44 */
+ __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x48 */
+ __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x4C */
+} ADC_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1 base address + 0x300 */
+ __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1 base address + 0x304 */
+ __IO uint32_t CDR; /*!< ADC common regular data register for dual
+ AND triple modes, Address offset: ADC1 base address + 0x308 */
+} ADC_Common_TypeDef;
+
+
+/**
+ * @brief Controller Area Network TxMailBox
+ */
+
+typedef struct
+{
+ __IO uint32_t TIR; /*!< CAN TX mailbox identifier register */
+ __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */
+ __IO uint32_t TDLR; /*!< CAN mailbox data low register */
+ __IO uint32_t TDHR; /*!< CAN mailbox data high register */
+} CAN_TxMailBox_TypeDef;
+
+/**
+ * @brief Controller Area Network FIFOMailBox
+ */
+
+typedef struct
+{
+ __IO uint32_t RIR; /*!< CAN receive FIFO mailbox identifier register */
+ __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */
+ __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */
+ __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */
+} CAN_FIFOMailBox_TypeDef;
+
+/**
+ * @brief Controller Area Network FilterRegister
+ */
+
+typedef struct
+{
+ __IO uint32_t FR1; /*!< CAN Filter bank register 1 */
+ __IO uint32_t FR2; /*!< CAN Filter bank register 1 */
+} CAN_FilterRegister_TypeDef;
+
+/**
+ * @brief Controller Area Network
+ */
+
+typedef struct
+{
+ __IO uint32_t MCR; /*!< CAN master control register, Address offset: 0x00 */
+ __IO uint32_t MSR; /*!< CAN master status register, Address offset: 0x04 */
+ __IO uint32_t TSR; /*!< CAN transmit status register, Address offset: 0x08 */
+ __IO uint32_t RF0R; /*!< CAN receive FIFO 0 register, Address offset: 0x0C */
+ __IO uint32_t RF1R; /*!< CAN receive FIFO 1 register, Address offset: 0x10 */
+ __IO uint32_t IER; /*!< CAN interrupt enable register, Address offset: 0x14 */
+ __IO uint32_t ESR; /*!< CAN error status register, Address offset: 0x18 */
+ __IO uint32_t BTR; /*!< CAN bit timing register, Address offset: 0x1C */
+ uint32_t RESERVED0[88]; /*!< Reserved, 0x020 - 0x17F */
+ CAN_TxMailBox_TypeDef sTxMailBox[3]; /*!< CAN Tx MailBox, Address offset: 0x180 - 0x1AC */
+ CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; /*!< CAN FIFO MailBox, Address offset: 0x1B0 - 0x1CC */
+ uint32_t RESERVED1[12]; /*!< Reserved, 0x1D0 - 0x1FF */
+ __IO uint32_t FMR; /*!< CAN filter master register, Address offset: 0x200 */
+ __IO uint32_t FM1R; /*!< CAN filter mode register, Address offset: 0x204 */
+ uint32_t RESERVED2; /*!< Reserved, 0x208 */
+ __IO uint32_t FS1R; /*!< CAN filter scale register, Address offset: 0x20C */
+ uint32_t RESERVED3; /*!< Reserved, 0x210 */
+ __IO uint32_t FFA1R; /*!< CAN filter FIFO assignment register, Address offset: 0x214 */
+ uint32_t RESERVED4; /*!< Reserved, 0x218 */
+ __IO uint32_t FA1R; /*!< CAN filter activation register, Address offset: 0x21C */
+ uint32_t RESERVED5[8]; /*!< Reserved, 0x220-0x23F */
+ CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register, Address offset: 0x240-0x31C */
+} CAN_TypeDef;
+
+/**
+ * @brief CRC calculation unit
+ */
+
+typedef struct
+{
+ __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
+ __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
+ uint8_t RESERVED0; /*!< Reserved, 0x05 */
+ uint16_t RESERVED1; /*!< Reserved, 0x06 */
+ __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
+} CRC_TypeDef;
+
+/**
+ * @brief Digital to Analog Converter
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */
+ __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */
+ __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
+ __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */
+ __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */
+ __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
+ __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */
+ __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */
+ __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */
+ __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */
+ __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */
+ __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */
+ __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */
+ __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */
+} DAC_TypeDef;
+
+/**
+ * @brief Debug MCU
+ */
+
+typedef struct
+{
+ __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
+ __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
+ __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */
+ __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */
+}DBGMCU_TypeDef;
+
+/**
+ * @brief DCMI
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< DCMI control register 1, Address offset: 0x00 */
+ __IO uint32_t SR; /*!< DCMI status register, Address offset: 0x04 */
+ __IO uint32_t RISR; /*!< DCMI raw interrupt status register, Address offset: 0x08 */
+ __IO uint32_t IER; /*!< DCMI interrupt enable register, Address offset: 0x0C */
+ __IO uint32_t MISR; /*!< DCMI masked interrupt status register, Address offset: 0x10 */
+ __IO uint32_t ICR; /*!< DCMI interrupt clear register, Address offset: 0x14 */
+ __IO uint32_t ESCR; /*!< DCMI embedded synchronization code register, Address offset: 0x18 */
+ __IO uint32_t ESUR; /*!< DCMI embedded synchronization unmask register, Address offset: 0x1C */
+ __IO uint32_t CWSTRTR; /*!< DCMI crop window start, Address offset: 0x20 */
+ __IO uint32_t CWSIZER; /*!< DCMI crop window size, Address offset: 0x24 */
+ __IO uint32_t DR; /*!< DCMI data register, Address offset: 0x28 */
+} DCMI_TypeDef;
+
+/**
+ * @brief DMA Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< DMA stream x configuration register */
+ __IO uint32_t NDTR; /*!< DMA stream x number of data register */
+ __IO uint32_t PAR; /*!< DMA stream x peripheral address register */
+ __IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */
+ __IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */
+ __IO uint32_t FCR; /*!< DMA stream x FIFO control register */
+} DMA_Stream_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t LISR; /*!< DMA low interrupt status register, Address offset: 0x00 */
+ __IO uint32_t HISR; /*!< DMA high interrupt status register, Address offset: 0x04 */
+ __IO uint32_t LIFCR; /*!< DMA low interrupt flag clear register, Address offset: 0x08 */
+ __IO uint32_t HIFCR; /*!< DMA high interrupt flag clear register, Address offset: 0x0C */
+} DMA_TypeDef;
+
+/**
+ * @brief DMA2D Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< DMA2D Control Register, Address offset: 0x00 */
+ __IO uint32_t ISR; /*!< DMA2D Interrupt Status Register, Address offset: 0x04 */
+ __IO uint32_t IFCR; /*!< DMA2D Interrupt Flag Clear Register, Address offset: 0x08 */
+ __IO uint32_t FGMAR; /*!< DMA2D Foreground Memory Address Register, Address offset: 0x0C */
+ __IO uint32_t FGOR; /*!< DMA2D Foreground Offset Register, Address offset: 0x10 */
+ __IO uint32_t BGMAR; /*!< DMA2D Background Memory Address Register, Address offset: 0x14 */
+ __IO uint32_t BGOR; /*!< DMA2D Background Offset Register, Address offset: 0x18 */
+ __IO uint32_t FGPFCCR; /*!< DMA2D Foreground PFC Control Register, Address offset: 0x1C */
+ __IO uint32_t FGCOLR; /*!< DMA2D Foreground Color Register, Address offset: 0x20 */
+ __IO uint32_t BGPFCCR; /*!< DMA2D Background PFC Control Register, Address offset: 0x24 */
+ __IO uint32_t BGCOLR; /*!< DMA2D Background Color Register, Address offset: 0x28 */
+ __IO uint32_t FGCMAR; /*!< DMA2D Foreground CLUT Memory Address Register, Address offset: 0x2C */
+ __IO uint32_t BGCMAR; /*!< DMA2D Background CLUT Memory Address Register, Address offset: 0x30 */
+ __IO uint32_t OPFCCR; /*!< DMA2D Output PFC Control Register, Address offset: 0x34 */
+ __IO uint32_t OCOLR; /*!< DMA2D Output Color Register, Address offset: 0x38 */
+ __IO uint32_t OMAR; /*!< DMA2D Output Memory Address Register, Address offset: 0x3C */
+ __IO uint32_t OOR; /*!< DMA2D Output Offset Register, Address offset: 0x40 */
+ __IO uint32_t NLR; /*!< DMA2D Number of Line Register, Address offset: 0x44 */
+ __IO uint32_t LWR; /*!< DMA2D Line Watermark Register, Address offset: 0x48 */
+ __IO uint32_t AMTCR; /*!< DMA2D AHB Master Timer Configuration Register, Address offset: 0x4C */
+ uint32_t RESERVED[236]; /*!< Reserved, 0x50-0x3FF */
+ __IO uint32_t FGCLUT[256]; /*!< DMA2D Foreground CLUT, Address offset:400-7FF */
+ __IO uint32_t BGCLUT[256]; /*!< DMA2D Background CLUT, Address offset:800-BFF */
+} DMA2D_TypeDef;
+
+/**
+ * @brief Ethernet MAC
+ */
+
+typedef struct
+{
+ __IO uint32_t MACCR;
+ __IO uint32_t MACFFR;
+ __IO uint32_t MACHTHR;
+ __IO uint32_t MACHTLR;
+ __IO uint32_t MACMIIAR;
+ __IO uint32_t MACMIIDR;
+ __IO uint32_t MACFCR;
+ __IO uint32_t MACVLANTR; /* 8 */
+ uint32_t RESERVED0[2];
+ __IO uint32_t MACRWUFFR; /* 11 */
+ __IO uint32_t MACPMTCSR;
+ uint32_t RESERVED1[2];
+ __IO uint32_t MACSR; /* 15 */
+ __IO uint32_t MACIMR;
+ __IO uint32_t MACA0HR;
+ __IO uint32_t MACA0LR;
+ __IO uint32_t MACA1HR;
+ __IO uint32_t MACA1LR;
+ __IO uint32_t MACA2HR;
+ __IO uint32_t MACA2LR;
+ __IO uint32_t MACA3HR;
+ __IO uint32_t MACA3LR; /* 24 */
+ uint32_t RESERVED2[40];
+ __IO uint32_t MMCCR; /* 65 */
+ __IO uint32_t MMCRIR;
+ __IO uint32_t MMCTIR;
+ __IO uint32_t MMCRIMR;
+ __IO uint32_t MMCTIMR; /* 69 */
+ uint32_t RESERVED3[14];
+ __IO uint32_t MMCTGFSCCR; /* 84 */
+ __IO uint32_t MMCTGFMSCCR;
+ uint32_t RESERVED4[5];
+ __IO uint32_t MMCTGFCR;
+ uint32_t RESERVED5[10];
+ __IO uint32_t MMCRFCECR;
+ __IO uint32_t MMCRFAECR;
+ uint32_t RESERVED6[10];
+ __IO uint32_t MMCRGUFCR;
+ uint32_t RESERVED7[334];
+ __IO uint32_t PTPTSCR;
+ __IO uint32_t PTPSSIR;
+ __IO uint32_t PTPTSHR;
+ __IO uint32_t PTPTSLR;
+ __IO uint32_t PTPTSHUR;
+ __IO uint32_t PTPTSLUR;
+ __IO uint32_t PTPTSAR;
+ __IO uint32_t PTPTTHR;
+ __IO uint32_t PTPTTLR;
+ __IO uint32_t RESERVED8;
+ __IO uint32_t PTPTSSR;
+ uint32_t RESERVED9[565];
+ __IO uint32_t DMABMR;
+ __IO uint32_t DMATPDR;
+ __IO uint32_t DMARPDR;
+ __IO uint32_t DMARDLAR;
+ __IO uint32_t DMATDLAR;
+ __IO uint32_t DMASR;
+ __IO uint32_t DMAOMR;
+ __IO uint32_t DMAIER;
+ __IO uint32_t DMAMFBOCR;
+ __IO uint32_t DMARSWTR;
+ uint32_t RESERVED10[8];
+ __IO uint32_t DMACHTDR;
+ __IO uint32_t DMACHRDR;
+ __IO uint32_t DMACHTBAR;
+ __IO uint32_t DMACHRBAR;
+} ETH_TypeDef;
+
+/**
+ * @brief External Interrupt/Event Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t IMR; /*!< EXTI Interrupt mask register, Address offset: 0x00 */
+ __IO uint32_t EMR; /*!< EXTI Event mask register, Address offset: 0x04 */
+ __IO uint32_t RTSR; /*!< EXTI Rising trigger selection register, Address offset: 0x08 */
+ __IO uint32_t FTSR; /*!< EXTI Falling trigger selection register, Address offset: 0x0C */
+ __IO uint32_t SWIER; /*!< EXTI Software interrupt event register, Address offset: 0x10 */
+ __IO uint32_t PR; /*!< EXTI Pending register, Address offset: 0x14 */
+} EXTI_TypeDef;
+
+/**
+ * @brief FLASH Registers
+ */
+
+typedef struct
+{
+ __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */
+ __IO uint32_t KEYR; /*!< FLASH key register, Address offset: 0x04 */
+ __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x08 */
+ __IO uint32_t SR; /*!< FLASH status register, Address offset: 0x0C */
+ __IO uint32_t CR; /*!< FLASH control register, Address offset: 0x10 */
+ __IO uint32_t OPTCR; /*!< FLASH option control register , Address offset: 0x14 */
+ __IO uint32_t OPTCR1; /*!< FLASH option control register 1, Address offset: 0x18 */
+} FLASH_TypeDef;
+
+/**
+ * @brief Flexible Memory Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */
+} FMC_Bank1_TypeDef;
+
+/**
+ * @brief Flexible Memory Controller Bank1E
+ */
+
+typedef struct
+{
+ __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */
+} FMC_Bank1E_TypeDef;
+
+/**
+ * @brief Flexible Memory Controller Bank2
+ */
+
+typedef struct
+{
+ __IO uint32_t PCR2; /*!< NAND Flash control register 2, Address offset: 0x60 */
+ __IO uint32_t SR2; /*!< NAND Flash FIFO status and interrupt register 2, Address offset: 0x64 */
+ __IO uint32_t PMEM2; /*!< NAND Flash Common memory space timing register 2, Address offset: 0x68 */
+ __IO uint32_t PATT2; /*!< NAND Flash Attribute memory space timing register 2, Address offset: 0x6C */
+ uint32_t RESERVED0; /*!< Reserved, 0x70 */
+ __IO uint32_t ECCR2; /*!< NAND Flash ECC result registers 2, Address offset: 0x74 */
+ uint32_t RESERVED1; /*!< Reserved, 0x78 */
+ uint32_t RESERVED2; /*!< Reserved, 0x7C */
+ __IO uint32_t PCR3; /*!< NAND Flash control register 3, Address offset: 0x80 */
+ __IO uint32_t SR3; /*!< NAND Flash FIFO status and interrupt register 3, Address offset: 0x84 */
+ __IO uint32_t PMEM3; /*!< NAND Flash Common memory space timing register 3, Address offset: 0x88 */
+ __IO uint32_t PATT3; /*!< NAND Flash Attribute memory space timing register 3, Address offset: 0x8C */
+ uint32_t RESERVED3; /*!< Reserved, 0x90 */
+ __IO uint32_t ECCR3; /*!< NAND Flash ECC result registers 3, Address offset: 0x94 */
+} FMC_Bank2_3_TypeDef;
+
+/**
+ * @brief Flexible Memory Controller Bank4
+ */
+
+typedef struct
+{
+ __IO uint32_t PCR4; /*!< PC Card control register 4, Address offset: 0xA0 */
+ __IO uint32_t SR4; /*!< PC Card FIFO status and interrupt register 4, Address offset: 0xA4 */
+ __IO uint32_t PMEM4; /*!< PC Card Common memory space timing register 4, Address offset: 0xA8 */
+ __IO uint32_t PATT4; /*!< PC Card Attribute memory space timing register 4, Address offset: 0xAC */
+ __IO uint32_t PIO4; /*!< PC Card I/O space timing register 4, Address offset: 0xB0 */
+} FMC_Bank4_TypeDef;
+
+/**
+ * @brief Flexible Memory Controller Bank5_6
+ */
+
+typedef struct
+{
+ __IO uint32_t SDCR[2]; /*!< SDRAM Control registers , Address offset: 0x140-0x144 */
+ __IO uint32_t SDTR[2]; /*!< SDRAM Timing registers , Address offset: 0x148-0x14C */
+ __IO uint32_t SDCMR; /*!< SDRAM Command Mode register, Address offset: 0x150 */
+ __IO uint32_t SDRTR; /*!< SDRAM Refresh Timer register, Address offset: 0x154 */
+ __IO uint32_t SDSR; /*!< SDRAM Status register, Address offset: 0x158 */
+} FMC_Bank5_6_TypeDef;
+
+/**
+ * @brief General Purpose I/O
+ */
+
+typedef struct
+{
+ __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
+ __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */
+ __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */
+ __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
+ __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
+ __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
+ __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */
+ __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
+ __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */
+} GPIO_TypeDef;
+
+/**
+ * @brief System configuration controller
+ */
+
+typedef struct
+{
+ __IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */
+ __IO uint32_t PMC; /*!< SYSCFG peripheral mode configuration register, Address offset: 0x04 */
+ __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
+ uint32_t RESERVED[2]; /*!< Reserved, 0x18-0x1C */
+ __IO uint32_t CMPCR; /*!< SYSCFG Compensation cell control register, Address offset: 0x20 */
+} SYSCFG_TypeDef;
+
+/**
+ * @brief Inter-integrated Circuit Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */
+ __IO uint32_t OAR1; /*!< I2C Own address register 1, Address offset: 0x08 */
+ __IO uint32_t OAR2; /*!< I2C Own address register 2, Address offset: 0x0C */
+ __IO uint32_t DR; /*!< I2C Data register, Address offset: 0x10 */
+ __IO uint32_t SR1; /*!< I2C Status register 1, Address offset: 0x14 */
+ __IO uint32_t SR2; /*!< I2C Status register 2, Address offset: 0x18 */
+ __IO uint32_t CCR; /*!< I2C Clock control register, Address offset: 0x1C */
+ __IO uint32_t TRISE; /*!< I2C TRISE register, Address offset: 0x20 */
+ __IO uint32_t FLTR; /*!< I2C FLTR register, Address offset: 0x24 */
+} I2C_TypeDef;
+
+/**
+ * @brief Independent WATCHDOG
+ */
+
+typedef struct
+{
+ __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */
+ __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */
+ __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */
+ __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */
+} IWDG_TypeDef;
+
+/**
+ * @brief LCD-TFT Display Controller
+ */
+
+typedef struct
+{
+ uint32_t RESERVED0[2]; /*!< Reserved, 0x00-0x04 */
+ __IO uint32_t SSCR; /*!< LTDC Synchronization Size Configuration Register, Address offset: 0x08 */
+ __IO uint32_t BPCR; /*!< LTDC Back Porch Configuration Register, Address offset: 0x0C */
+ __IO uint32_t AWCR; /*!< LTDC Active Width Configuration Register, Address offset: 0x10 */
+ __IO uint32_t TWCR; /*!< LTDC Total Width Configuration Register, Address offset: 0x14 */
+ __IO uint32_t GCR; /*!< LTDC Global Control Register, Address offset: 0x18 */
+ uint32_t RESERVED1[2]; /*!< Reserved, 0x1C-0x20 */
+ __IO uint32_t SRCR; /*!< LTDC Shadow Reload Configuration Register, Address offset: 0x24 */
+ uint32_t RESERVED2[1]; /*!< Reserved, 0x28 */
+ __IO uint32_t BCCR; /*!< LTDC Background Color Configuration Register, Address offset: 0x2C */
+ uint32_t RESERVED3[1]; /*!< Reserved, 0x30 */
+ __IO uint32_t IER; /*!< LTDC Interrupt Enable Register, Address offset: 0x34 */
+ __IO uint32_t ISR; /*!< LTDC Interrupt Status Register, Address offset: 0x38 */
+ __IO uint32_t ICR; /*!< LTDC Interrupt Clear Register, Address offset: 0x3C */
+ __IO uint32_t LIPCR; /*!< LTDC Line Interrupt Position Configuration Register, Address offset: 0x40 */
+ __IO uint32_t CPSR; /*!< LTDC Current Position Status Register, Address offset: 0x44 */
+ __IO uint32_t CDSR; /*!< LTDC Current Display Status Register, Address offset: 0x48 */
+} LTDC_TypeDef;
+
+/**
+ * @brief LCD-TFT Display layer x Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< LTDC Layerx Control Register Address offset: 0x84 */
+ __IO uint32_t WHPCR; /*!< LTDC Layerx Window Horizontal Position Configuration Register Address offset: 0x88 */
+ __IO uint32_t WVPCR; /*!< LTDC Layerx Window Vertical Position Configuration Register Address offset: 0x8C */
+ __IO uint32_t CKCR; /*!< LTDC Layerx Color Keying Configuration Register Address offset: 0x90 */
+ __IO uint32_t PFCR; /*!< LTDC Layerx Pixel Format Configuration Register Address offset: 0x94 */
+ __IO uint32_t CACR; /*!< LTDC Layerx Constant Alpha Configuration Register Address offset: 0x98 */
+ __IO uint32_t DCCR; /*!< LTDC Layerx Default Color Configuration Register Address offset: 0x9C */
+ __IO uint32_t BFCR; /*!< LTDC Layerx Blending Factors Configuration Register Address offset: 0xA0 */
+ uint32_t RESERVED0[2]; /*!< Reserved */
+ __IO uint32_t CFBAR; /*!< LTDC Layerx Color Frame Buffer Address Register Address offset: 0xAC */
+ __IO uint32_t CFBLR; /*!< LTDC Layerx Color Frame Buffer Length Register Address offset: 0xB0 */
+ __IO uint32_t CFBLNR; /*!< LTDC Layerx ColorFrame Buffer Line Number Register Address offset: 0xB4 */
+ uint32_t RESERVED1[3]; /*!< Reserved */
+ __IO uint32_t CLUTWR; /*!< LTDC Layerx CLUT Write Register Address offset: 0x144 */
+
+} LTDC_Layer_TypeDef;
+
+/**
+ * @brief Power Control
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */
+ __IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */
+} PWR_TypeDef;
+
+/**
+ * @brief Reset and Clock Control
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */
+ __IO uint32_t PLLCFGR; /*!< RCC PLL configuration register, Address offset: 0x04 */
+ __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x08 */
+ __IO uint32_t CIR; /*!< RCC clock interrupt register, Address offset: 0x0C */
+ __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x10 */
+ __IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x14 */
+ __IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0x18 */
+ uint32_t RESERVED0; /*!< Reserved, 0x1C */
+ __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x20 */
+ __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x24 */
+ uint32_t RESERVED1[2]; /*!< Reserved, 0x28-0x2C */
+ __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clock register, Address offset: 0x30 */
+ __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clock register, Address offset: 0x34 */
+ __IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clock register, Address offset: 0x38 */
+ uint32_t RESERVED2; /*!< Reserved, 0x3C */
+ __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x40 */
+ __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x44 */
+ uint32_t RESERVED3[2]; /*!< Reserved, 0x48-0x4C */
+ __IO uint32_t AHB1LPENR; /*!< RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 */
+ __IO uint32_t AHB2LPENR; /*!< RCC AHB2 peripheral clock enable in low power mode register, Address offset: 0x54 */
+ __IO uint32_t AHB3LPENR; /*!< RCC AHB3 peripheral clock enable in low power mode register, Address offset: 0x58 */
+ uint32_t RESERVED4; /*!< Reserved, 0x5C */
+ __IO uint32_t APB1LPENR; /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 */
+ __IO uint32_t APB2LPENR; /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 */
+ uint32_t RESERVED5[2]; /*!< Reserved, 0x68-0x6C */
+ __IO uint32_t BDCR; /*!< RCC Backup domain control register, Address offset: 0x70 */
+ __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x74 */
+ uint32_t RESERVED6[2]; /*!< Reserved, 0x78-0x7C */
+ __IO uint32_t SSCGR; /*!< RCC spread spectrum clock generation register, Address offset: 0x80 */
+ __IO uint32_t PLLI2SCFGR; /*!< RCC PLLI2S configuration register, Address offset: 0x84 */
+ __IO uint32_t PLLSAICFGR; /*!< RCC PLLSAI configuration register, Address offset: 0x88 */
+ __IO uint32_t DCKCFGR; /*!< RCC Dedicated Clocks configuration register, Address offset: 0x8C */
+
+} RCC_TypeDef;
+
+/**
+ * @brief Real-Time Clock
+ */
+
+typedef struct
+{
+ __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
+ __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */
+ __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */
+ __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */
+ __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */
+ __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */
+ __IO uint32_t CALIBR; /*!< RTC calibration register, Address offset: 0x18 */
+ __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */
+ __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */
+ __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */
+ __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */
+ __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */
+ __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */
+ __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */
+ __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */
+ __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */
+ __IO uint32_t TAFCR; /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */
+ __IO uint32_t ALRMASSR;/*!< RTC alarm A sub second register, Address offset: 0x44 */
+ __IO uint32_t ALRMBSSR;/*!< RTC alarm B sub second register, Address offset: 0x48 */
+ uint32_t RESERVED7; /*!< Reserved, 0x4C */
+ __IO uint32_t BKP0R; /*!< RTC backup register 1, Address offset: 0x50 */
+ __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */
+ __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */
+ __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */
+ __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */
+ __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */
+ __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */
+ __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */
+ __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */
+ __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */
+ __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */
+ __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */
+ __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */
+ __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */
+ __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */
+ __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */
+ __IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */
+ __IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */
+ __IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */
+ __IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */
+} RTC_TypeDef;
+
+/**
+ * @brief Serial Audio Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t GCR; /*!< SAI global configuration register, Address offset: 0x00 */
+} SAI_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t CR1; /*!< SAI block x configuration register 1, Address offset: 0x04 */
+ __IO uint32_t CR2; /*!< SAI block x configuration register 2, Address offset: 0x08 */
+ __IO uint32_t FRCR; /*!< SAI block x frame configuration register, Address offset: 0x0C */
+ __IO uint32_t SLOTR; /*!< SAI block x slot register, Address offset: 0x10 */
+ __IO uint32_t IMR; /*!< SAI block x interrupt mask register, Address offset: 0x14 */
+ __IO uint32_t SR; /*!< SAI block x status register, Address offset: 0x18 */
+ __IO uint32_t CLRFR; /*!< SAI block x clear flag register, Address offset: 0x1C */
+ __IO uint32_t DR; /*!< SAI block x data register, Address offset: 0x20 */
+} SAI_Block_TypeDef;
+
+/**
+ * @brief SD host Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t POWER; /*!< SDIO power control register, Address offset: 0x00 */
+ __IO uint32_t CLKCR; /*!< SDI clock control register, Address offset: 0x04 */
+ __IO uint32_t ARG; /*!< SDIO argument register, Address offset: 0x08 */
+ __IO uint32_t CMD; /*!< SDIO command register, Address offset: 0x0C */
+ __I uint32_t RESPCMD; /*!< SDIO command response register, Address offset: 0x10 */
+ __I uint32_t RESP1; /*!< SDIO response 1 register, Address offset: 0x14 */
+ __I uint32_t RESP2; /*!< SDIO response 2 register, Address offset: 0x18 */
+ __I uint32_t RESP3; /*!< SDIO response 3 register, Address offset: 0x1C */
+ __I uint32_t RESP4; /*!< SDIO response 4 register, Address offset: 0x20 */
+ __IO uint32_t DTIMER; /*!< SDIO data timer register, Address offset: 0x24 */
+ __IO uint32_t DLEN; /*!< SDIO data length register, Address offset: 0x28 */
+ __IO uint32_t DCTRL; /*!< SDIO data control register, Address offset: 0x2C */
+ __I uint32_t DCOUNT; /*!< SDIO data counter register, Address offset: 0x30 */
+ __I uint32_t STA; /*!< SDIO status register, Address offset: 0x34 */
+ __IO uint32_t ICR; /*!< SDIO interrupt clear register, Address offset: 0x38 */
+ __IO uint32_t MASK; /*!< SDIO mask register, Address offset: 0x3C */
+ uint32_t RESERVED0[2]; /*!< Reserved, 0x40-0x44 */
+ __I uint32_t FIFOCNT; /*!< SDIO FIFO counter register, Address offset: 0x48 */
+ uint32_t RESERVED1[13]; /*!< Reserved, 0x4C-0x7C */
+ __IO uint32_t FIFO; /*!< SDIO data FIFO register, Address offset: 0x80 */
+} SDIO_TypeDef;
+
+/**
+ * @brief Serial Peripheral Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t CR1; /*!< SPI control register 1 (not used in I2S mode), Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< SPI control register 2, Address offset: 0x04 */
+ __IO uint32_t SR; /*!< SPI status register, Address offset: 0x08 */
+ __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */
+ __IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
+ __IO uint32_t RXCRCR; /*!< SPI RX CRC register (not used in I2S mode), Address offset: 0x14 */
+ __IO uint32_t TXCRCR; /*!< SPI TX CRC register (not used in I2S mode), Address offset: 0x18 */
+ __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */
+ __IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */
+} SPI_TypeDef;
+
+/**
+ * @brief TIM
+ */
+
+typedef struct
+{
+ __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
+ __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */
+ __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
+ __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
+ __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
+ __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
+ __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
+ __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
+ __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
+ __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */
+ __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
+ __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */
+ __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
+ __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
+ __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
+ __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
+ __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
+ __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
+ __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */
+ __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */
+} TIM_TypeDef;
+
+/**
+ * @brief Universal Synchronous Asynchronous Receiver Transmitter
+ */
+
+typedef struct
+{
+ __IO uint32_t SR; /*!< USART Status register, Address offset: 0x00 */
+ __IO uint32_t DR; /*!< USART Data register, Address offset: 0x04 */
+ __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x08 */
+ __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x0C */
+ __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x10 */
+ __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x14 */
+ __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x18 */
+} USART_TypeDef;
+
+/**
+ * @brief Window WATCHDOG
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
+ __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
+ __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
+} WWDG_TypeDef;
+
+
+/**
+ * @brief RNG
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */
+ __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */
+ __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */
+} RNG_TypeDef;
+
+
+/**
+ * @brief __USB_OTG_Core_register
+ */
+typedef struct
+{
+ __IO uint32_t GOTGCTL; /*!< USB_OTG Control and Status Register 000h */
+ __IO uint32_t GOTGINT; /*!< USB_OTG Interrupt Register 004h */
+ __IO uint32_t GAHBCFG; /*!< Core AHB Configuration Register 008h */
+ __IO uint32_t GUSBCFG; /*!< Core USB Configuration Register 00Ch */
+ __IO uint32_t GRSTCTL; /*!< Core Reset Register 010h */
+ __IO uint32_t GINTSTS; /*!< Core Interrupt Register 014h */
+ __IO uint32_t GINTMSK; /*!< Core Interrupt Mask Register 018h */
+ __IO uint32_t GRXSTSR; /*!< Receive Sts Q Read Register 01Ch */
+ __IO uint32_t GRXSTSP; /*!< Receive Sts Q Read & POP Register 020h */
+ __IO uint32_t GRXFSIZ; /* Receive FIFO Size Register 024h */
+ __IO uint32_t DIEPTXF0_HNPTXFSIZ; /*!< EP0 / Non Periodic Tx FIFO Size Register 028h*/
+ __IO uint32_t HNPTXSTS; /*!< Non Periodic Tx FIFO/Queue Sts reg 02Ch */
+ uint32_t Reserved30[2]; /* Reserved 030h*/
+ __IO uint32_t GCCFG; /* General Purpose IO Register 038h*/
+ __IO uint32_t CID; /* User ID Register 03Ch*/
+ uint32_t Reserved40[48]; /* Reserved 040h-0FFh*/
+ __IO uint32_t HPTXFSIZ; /* Host Periodic Tx FIFO Size Reg 100h*/
+ __IO uint32_t DIEPTXF[0x0F];/* dev Periodic Transmit FIFO */
+}
+USB_OTG_GlobalTypeDef;
+
+
+/**
+ * @brief __device_Registers
+ */
+typedef struct
+{
+ __IO uint32_t DCFG; /* dev Configuration Register 800h*/
+ __IO uint32_t DCTL; /* dev Control Register 804h*/
+ __IO uint32_t DSTS; /* dev Status Register (RO) 808h*/
+ uint32_t Reserved0C; /* Reserved 80Ch*/
+ __IO uint32_t DIEPMSK; /* dev IN Endpoint Mask 810h*/
+ __IO uint32_t DOEPMSK; /* dev OUT Endpoint Mask 814h*/
+ __IO uint32_t DAINT; /* dev All Endpoints Itr Reg 818h*/
+ __IO uint32_t DAINTMSK; /* dev All Endpoints Itr Mask 81Ch*/
+ uint32_t Reserved20; /* Reserved 820h*/
+ uint32_t Reserved9; /* Reserved 824h*/
+ __IO uint32_t DVBUSDIS; /* dev VBUS discharge Register 828h*/
+ __IO uint32_t DVBUSPULSE; /* dev VBUS Pulse Register 82Ch*/
+ __IO uint32_t DTHRCTL; /* dev thr 830h*/
+ __IO uint32_t DIEPEMPMSK; /* dev empty msk 834h*/
+ __IO uint32_t DEACHINT; /* dedicated EP interrupt 838h*/
+ __IO uint32_t DEACHMSK; /* dedicated EP msk 83Ch*/
+ uint32_t Reserved40; /* dedicated EP mask 840h*/
+ __IO uint32_t DINEP1MSK; /* dedicated EP mask 844h*/
+ uint32_t Reserved44[15]; /* Reserved 844-87Ch*/
+ __IO uint32_t DOUTEP1MSK; /* dedicated EP msk 884h*/
+}
+USB_OTG_DeviceTypeDef;
+
+
+/**
+ * @brief __IN_Endpoint-Specific_Register
+ */
+typedef struct
+{
+ __IO uint32_t DIEPCTL; /* dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h*/
+ uint32_t Reserved04; /* Reserved 900h + (ep_num * 20h) + 04h*/
+ __IO uint32_t DIEPINT; /* dev IN Endpoint Itr Reg 900h + (ep_num * 20h) + 08h*/
+ uint32_t Reserved0C; /* Reserved 900h + (ep_num * 20h) + 0Ch*/
+ __IO uint32_t DIEPTSIZ; /* IN Endpoint Txfer Size 900h + (ep_num * 20h) + 10h*/
+ __IO uint32_t DIEPDMA; /* IN Endpoint DMA Address Reg 900h + (ep_num * 20h) + 14h*/
+ __IO uint32_t DTXFSTS;/*IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h*/
+ uint32_t Reserved18; /* Reserved 900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch*/
+}
+USB_OTG_INEndpointTypeDef;
+
+
+/**
+ * @brief __OUT_Endpoint-Specific_Registers
+ */
+typedef struct
+{
+ __IO uint32_t DOEPCTL; /* dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h*/
+ uint32_t Reserved04; /* Reserved B00h + (ep_num * 20h) + 04h*/
+ __IO uint32_t DOEPINT; /* dev OUT Endpoint Itr Reg B00h + (ep_num * 20h) + 08h*/
+ uint32_t Reserved0C; /* Reserved B00h + (ep_num * 20h) + 0Ch*/
+ __IO uint32_t DOEPTSIZ; /* dev OUT Endpoint Txfer Size B00h + (ep_num * 20h) + 10h*/
+ __IO uint32_t DOEPDMA; /* dev OUT Endpoint DMA Address B00h + (ep_num * 20h) + 14h*/
+ uint32_t Reserved18[2]; /* Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch*/
+}
+USB_OTG_OUTEndpointTypeDef;
+
+
+/**
+ * @brief __Host_Mode_Register_Structures
+ */
+typedef struct
+{
+ __IO uint32_t HCFG; /* Host Configuration Register 400h*/
+ __IO uint32_t HFIR; /* Host Frame Interval Register 404h*/
+ __IO uint32_t HFNUM; /* Host Frame Nbr/Frame Remaining 408h*/
+ uint32_t Reserved40C; /* Reserved 40Ch*/
+ __IO uint32_t HPTXSTS; /* Host Periodic Tx FIFO/ Queue Status 410h*/
+ __IO uint32_t HAINT; /* Host All Channels Interrupt Register 414h*/
+ __IO uint32_t HAINTMSK; /* Host All Channels Interrupt Mask 418h*/
+}
+USB_OTG_HostTypeDef;
+
+/**
+ * @brief __Host_Channel_Specific_Registers
+ */
+typedef struct
+{
+ __IO uint32_t HCCHAR;
+ __IO uint32_t HCSPLT;
+ __IO uint32_t HCINT;
+ __IO uint32_t HCINTMSK;
+ __IO uint32_t HCTSIZ;
+ __IO uint32_t HCDMA;
+ uint32_t Reserved[2];
+}
+USB_OTG_HostChannelTypeDef;
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_memory_map
+ * @{
+ */
+#define FLASH_BASE 0x08000000U /*!< FLASH(up to 2 MB) base address in the alias region */
+#define CCMDATARAM_BASE 0x10000000U /*!< CCM(core coupled memory) data RAM(64 KB) base address in the alias region */
+#define SRAM1_BASE 0x20000000U /*!< SRAM1(112 KB) base address in the alias region */
+#define SRAM2_BASE 0x2001C000U /*!< SRAM2(16 KB) base address in the alias region */
+#define SRAM3_BASE 0x20020000U /*!< SRAM3(64 KB) base address in the alias region */
+#define PERIPH_BASE 0x40000000U /*!< Peripheral base address in the alias region */
+#define BKPSRAM_BASE 0x40024000U /*!< Backup SRAM(4 KB) base address in the alias region */
+#define FMC_R_BASE 0xA0000000U /*!< FMC registers base address */
+#define SRAM1_BB_BASE 0x22000000U /*!< SRAM1(112 KB) base address in the bit-band region */
+#define SRAM2_BB_BASE 0x22380000U /*!< SRAM2(16 KB) base address in the bit-band region */
+#define SRAM3_BB_BASE 0x22400000U /*!< SRAM3(64 KB) base address in the bit-band region */
+#define PERIPH_BB_BASE 0x42000000U /*!< Peripheral base address in the bit-band region */
+#define BKPSRAM_BB_BASE 0x42480000U /*!< Backup SRAM(4 KB) base address in the bit-band region */
+#define FLASH_END 0x081FFFFFU /*!< FLASH end address */
+#define CCMDATARAM_END 0x1000FFFFU /*!< CCM data RAM end address */
+
+/* Legacy defines */
+#define SRAM_BASE SRAM1_BASE
+#define SRAM_BB_BASE SRAM1_BB_BASE
+
+
+/*!< Peripheral memory map */
+#define APB1PERIPH_BASE PERIPH_BASE
+#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000U)
+#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000U)
+#define AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000U)
+
+/*!< APB1 peripherals */
+#define TIM2_BASE (APB1PERIPH_BASE + 0x0000U)
+#define TIM3_BASE (APB1PERIPH_BASE + 0x0400U)
+#define TIM4_BASE (APB1PERIPH_BASE + 0x0800U)
+#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00U)
+#define TIM6_BASE (APB1PERIPH_BASE + 0x1000U)
+#define TIM7_BASE (APB1PERIPH_BASE + 0x1400U)
+#define TIM12_BASE (APB1PERIPH_BASE + 0x1800U)
+#define TIM13_BASE (APB1PERIPH_BASE + 0x1C00U)
+#define TIM14_BASE (APB1PERIPH_BASE + 0x2000U)
+#define RTC_BASE (APB1PERIPH_BASE + 0x2800U)
+#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00U)
+#define IWDG_BASE (APB1PERIPH_BASE + 0x3000U)
+#define I2S2ext_BASE (APB1PERIPH_BASE + 0x3400U)
+#define SPI2_BASE (APB1PERIPH_BASE + 0x3800U)
+#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00U)
+#define I2S3ext_BASE (APB1PERIPH_BASE + 0x4000U)
+#define USART2_BASE (APB1PERIPH_BASE + 0x4400U)
+#define USART3_BASE (APB1PERIPH_BASE + 0x4800U)
+#define UART4_BASE (APB1PERIPH_BASE + 0x4C00U)
+#define UART5_BASE (APB1PERIPH_BASE + 0x5000U)
+#define I2C1_BASE (APB1PERIPH_BASE + 0x5400U)
+#define I2C2_BASE (APB1PERIPH_BASE + 0x5800U)
+#define I2C3_BASE (APB1PERIPH_BASE + 0x5C00U)
+#define CAN1_BASE (APB1PERIPH_BASE + 0x6400U)
+#define CAN2_BASE (APB1PERIPH_BASE + 0x6800U)
+#define PWR_BASE (APB1PERIPH_BASE + 0x7000U)
+#define DAC_BASE (APB1PERIPH_BASE + 0x7400U)
+#define UART7_BASE (APB1PERIPH_BASE + 0x7800U)
+#define UART8_BASE (APB1PERIPH_BASE + 0x7C00U)
+
+/*!< APB2 peripherals */
+#define TIM1_BASE (APB2PERIPH_BASE + 0x0000U)
+#define TIM8_BASE (APB2PERIPH_BASE + 0x0400U)
+#define USART1_BASE (APB2PERIPH_BASE + 0x1000U)
+#define USART6_BASE (APB2PERIPH_BASE + 0x1400U)
+#define ADC1_BASE (APB2PERIPH_BASE + 0x2000U)
+#define ADC2_BASE (APB2PERIPH_BASE + 0x2100U)
+#define ADC3_BASE (APB2PERIPH_BASE + 0x2200U)
+#define ADC_BASE (APB2PERIPH_BASE + 0x2300U)
+#define SDIO_BASE (APB2PERIPH_BASE + 0x2C00U)
+#define SPI1_BASE (APB2PERIPH_BASE + 0x3000U)
+#define SPI4_BASE (APB2PERIPH_BASE + 0x3400U)
+#define SYSCFG_BASE (APB2PERIPH_BASE + 0x3800U)
+#define EXTI_BASE (APB2PERIPH_BASE + 0x3C00U)
+#define TIM9_BASE (APB2PERIPH_BASE + 0x4000U)
+#define TIM10_BASE (APB2PERIPH_BASE + 0x4400U)
+#define TIM11_BASE (APB2PERIPH_BASE + 0x4800U)
+#define SPI5_BASE (APB2PERIPH_BASE + 0x5000U)
+#define SPI6_BASE (APB2PERIPH_BASE + 0x5400U)
+#define SAI1_BASE (APB2PERIPH_BASE + 0x5800U)
+#define SAI1_Block_A_BASE (SAI1_BASE + 0x004U)
+#define SAI1_Block_B_BASE (SAI1_BASE + 0x024U)
+#define LTDC_BASE (APB2PERIPH_BASE + 0x6800U)
+#define LTDC_Layer1_BASE (LTDC_BASE + 0x84U)
+#define LTDC_Layer2_BASE (LTDC_BASE + 0x104U)
+
+/*!< AHB1 peripherals */
+#define GPIOA_BASE (AHB1PERIPH_BASE + 0x0000U)
+#define GPIOB_BASE (AHB1PERIPH_BASE + 0x0400U)
+#define GPIOC_BASE (AHB1PERIPH_BASE + 0x0800U)
+#define GPIOD_BASE (AHB1PERIPH_BASE + 0x0C00U)
+#define GPIOE_BASE (AHB1PERIPH_BASE + 0x1000U)
+#define GPIOF_BASE (AHB1PERIPH_BASE + 0x1400U)
+#define GPIOG_BASE (AHB1PERIPH_BASE + 0x1800U)
+#define GPIOH_BASE (AHB1PERIPH_BASE + 0x1C00U)
+#define GPIOI_BASE (AHB1PERIPH_BASE + 0x2000U)
+#define GPIOJ_BASE (AHB1PERIPH_BASE + 0x2400U)
+#define GPIOK_BASE (AHB1PERIPH_BASE + 0x2800U)
+#define CRC_BASE (AHB1PERIPH_BASE + 0x3000U)
+#define RCC_BASE (AHB1PERIPH_BASE + 0x3800U)
+#define FLASH_R_BASE (AHB1PERIPH_BASE + 0x3C00U)
+#define DMA1_BASE (AHB1PERIPH_BASE + 0x6000U)
+#define DMA1_Stream0_BASE (DMA1_BASE + 0x010U)
+#define DMA1_Stream1_BASE (DMA1_BASE + 0x028U)
+#define DMA1_Stream2_BASE (DMA1_BASE + 0x040U)
+#define DMA1_Stream3_BASE (DMA1_BASE + 0x058U)
+#define DMA1_Stream4_BASE (DMA1_BASE + 0x070U)
+#define DMA1_Stream5_BASE (DMA1_BASE + 0x088U)
+#define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0U)
+#define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8U)
+#define DMA2_BASE (AHB1PERIPH_BASE + 0x6400U)
+#define DMA2_Stream0_BASE (DMA2_BASE + 0x010U)
+#define DMA2_Stream1_BASE (DMA2_BASE + 0x028U)
+#define DMA2_Stream2_BASE (DMA2_BASE + 0x040U)
+#define DMA2_Stream3_BASE (DMA2_BASE + 0x058U)
+#define DMA2_Stream4_BASE (DMA2_BASE + 0x070U)
+#define DMA2_Stream5_BASE (DMA2_BASE + 0x088U)
+#define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0U)
+#define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8U)
+#define ETH_BASE (AHB1PERIPH_BASE + 0x8000U)
+#define ETH_MAC_BASE (ETH_BASE)
+#define ETH_MMC_BASE (ETH_BASE + 0x0100U)
+#define ETH_PTP_BASE (ETH_BASE + 0x0700U)
+#define ETH_DMA_BASE (ETH_BASE + 0x1000U)
+#define DMA2D_BASE (AHB1PERIPH_BASE + 0xB000U)
+
+/*!< AHB2 peripherals */
+#define DCMI_BASE (AHB2PERIPH_BASE + 0x50000U)
+#define RNG_BASE (AHB2PERIPH_BASE + 0x60800U)
+
+/*!< FMC Bankx registers base address */
+#define FMC_Bank1_R_BASE (FMC_R_BASE + 0x0000U)
+#define FMC_Bank1E_R_BASE (FMC_R_BASE + 0x0104U)
+#define FMC_Bank2_3_R_BASE (FMC_R_BASE + 0x0060U)
+#define FMC_Bank4_R_BASE (FMC_R_BASE + 0x00A0U)
+#define FMC_Bank5_6_R_BASE (FMC_R_BASE + 0x0140U)
+
+/* Debug MCU registers base address */
+#define DBGMCU_BASE 0xE0042000U
+
+/*!< USB registers base address */
+#define USB_OTG_HS_PERIPH_BASE 0x40040000U
+#define USB_OTG_FS_PERIPH_BASE 0x50000000U
+
+#define USB_OTG_GLOBAL_BASE 0x000U
+#define USB_OTG_DEVICE_BASE 0x800U
+#define USB_OTG_IN_ENDPOINT_BASE 0x900U
+#define USB_OTG_OUT_ENDPOINT_BASE 0xB00U
+#define USB_OTG_EP_REG_SIZE 0x20U
+#define USB_OTG_HOST_BASE 0x400U
+#define USB_OTG_HOST_PORT_BASE 0x440U
+#define USB_OTG_HOST_CHANNEL_BASE 0x500U
+#define USB_OTG_HOST_CHANNEL_SIZE 0x20U
+#define USB_OTG_PCGCCTL_BASE 0xE00U
+#define USB_OTG_FIFO_BASE 0x1000U
+#define USB_OTG_FIFO_SIZE 0x1000U
+
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_declaration
+ * @{
+ */
+#define TIM2 ((TIM_TypeDef *) TIM2_BASE)
+#define TIM3 ((TIM_TypeDef *) TIM3_BASE)
+#define TIM4 ((TIM_TypeDef *) TIM4_BASE)
+#define TIM5 ((TIM_TypeDef *) TIM5_BASE)
+#define TIM6 ((TIM_TypeDef *) TIM6_BASE)
+#define TIM7 ((TIM_TypeDef *) TIM7_BASE)
+#define TIM12 ((TIM_TypeDef *) TIM12_BASE)
+#define TIM13 ((TIM_TypeDef *) TIM13_BASE)
+#define TIM14 ((TIM_TypeDef *) TIM14_BASE)
+#define RTC ((RTC_TypeDef *) RTC_BASE)
+#define WWDG ((WWDG_TypeDef *) WWDG_BASE)
+#define IWDG ((IWDG_TypeDef *) IWDG_BASE)
+#define I2S2ext ((SPI_TypeDef *) I2S2ext_BASE)
+#define SPI2 ((SPI_TypeDef *) SPI2_BASE)
+#define SPI3 ((SPI_TypeDef *) SPI3_BASE)
+#define I2S3ext ((SPI_TypeDef *) I2S3ext_BASE)
+#define USART2 ((USART_TypeDef *) USART2_BASE)
+#define USART3 ((USART_TypeDef *) USART3_BASE)
+#define UART4 ((USART_TypeDef *) UART4_BASE)
+#define UART5 ((USART_TypeDef *) UART5_BASE)
+#define I2C1 ((I2C_TypeDef *) I2C1_BASE)
+#define I2C2 ((I2C_TypeDef *) I2C2_BASE)
+#define I2C3 ((I2C_TypeDef *) I2C3_BASE)
+#define CAN1 ((CAN_TypeDef *) CAN1_BASE)
+#define CAN2 ((CAN_TypeDef *) CAN2_BASE)
+#define PWR ((PWR_TypeDef *) PWR_BASE)
+#define DAC ((DAC_TypeDef *) DAC_BASE)
+#define UART7 ((USART_TypeDef *) UART7_BASE)
+#define UART8 ((USART_TypeDef *) UART8_BASE)
+#define TIM1 ((TIM_TypeDef *) TIM1_BASE)
+#define TIM8 ((TIM_TypeDef *) TIM8_BASE)
+#define USART1 ((USART_TypeDef *) USART1_BASE)
+#define USART6 ((USART_TypeDef *) USART6_BASE)
+#define ADC ((ADC_Common_TypeDef *) ADC_BASE)
+#define ADC1 ((ADC_TypeDef *) ADC1_BASE)
+#define ADC2 ((ADC_TypeDef *) ADC2_BASE)
+#define ADC3 ((ADC_TypeDef *) ADC3_BASE)
+#define SDIO ((SDIO_TypeDef *) SDIO_BASE)
+#define SPI1 ((SPI_TypeDef *) SPI1_BASE)
+#define SPI4 ((SPI_TypeDef *) SPI4_BASE)
+#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
+#define EXTI ((EXTI_TypeDef *) EXTI_BASE)
+#define TIM9 ((TIM_TypeDef *) TIM9_BASE)
+#define TIM10 ((TIM_TypeDef *) TIM10_BASE)
+#define TIM11 ((TIM_TypeDef *) TIM11_BASE)
+#define SPI5 ((SPI_TypeDef *) SPI5_BASE)
+#define SPI6 ((SPI_TypeDef *) SPI6_BASE)
+#define SAI1 ((SAI_TypeDef *) SAI1_BASE)
+#define SAI1_Block_A ((SAI_Block_TypeDef *)SAI1_Block_A_BASE)
+#define SAI1_Block_B ((SAI_Block_TypeDef *)SAI1_Block_B_BASE)
+#define LTDC ((LTDC_TypeDef *)LTDC_BASE)
+#define LTDC_Layer1 ((LTDC_Layer_TypeDef *)LTDC_Layer1_BASE)
+#define LTDC_Layer2 ((LTDC_Layer_TypeDef *)LTDC_Layer2_BASE)
+
+#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
+#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
+#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
+#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
+#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
+#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
+#define GPIOG ((GPIO_TypeDef *) GPIOG_BASE)
+#define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
+#define GPIOI ((GPIO_TypeDef *) GPIOI_BASE)
+#define GPIOJ ((GPIO_TypeDef *) GPIOJ_BASE)
+#define GPIOK ((GPIO_TypeDef *) GPIOK_BASE)
+#define CRC ((CRC_TypeDef *) CRC_BASE)
+#define RCC ((RCC_TypeDef *) RCC_BASE)
+#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
+#define DMA1 ((DMA_TypeDef *) DMA1_BASE)
+#define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)
+#define DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)
+#define DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)
+#define DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)
+#define DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)
+#define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)
+#define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)
+#define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)
+#define DMA2 ((DMA_TypeDef *) DMA2_BASE)
+#define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)
+#define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
+#define DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)
+#define DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)
+#define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)
+#define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)
+#define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)
+#define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)
+#define ETH ((ETH_TypeDef *) ETH_BASE)
+#define DMA2D ((DMA2D_TypeDef *)DMA2D_BASE)
+#define DCMI ((DCMI_TypeDef *) DCMI_BASE)
+#define RNG ((RNG_TypeDef *) RNG_BASE)
+#define FMC_Bank1 ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE)
+#define FMC_Bank1E ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE)
+#define FMC_Bank2_3 ((FMC_Bank2_3_TypeDef *) FMC_Bank2_3_R_BASE)
+#define FMC_Bank4 ((FMC_Bank4_TypeDef *) FMC_Bank4_R_BASE)
+#define FMC_Bank5_6 ((FMC_Bank5_6_TypeDef *) FMC_Bank5_6_R_BASE)
+
+#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
+
+#define USB_OTG_FS ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE)
+#define USB_OTG_HS ((USB_OTG_GlobalTypeDef *) USB_OTG_HS_PERIPH_BASE)
+
+/**
+ * @}
+ */
+
+/** @addtogroup Exported_constants
+ * @{
+ */
+
+ /** @addtogroup Peripheral_Registers_Bits_Definition
+ * @{
+ */
+
+/******************************************************************************/
+/* Peripheral Registers_Bits_Definition */
+/******************************************************************************/
+
+/******************************************************************************/
+/* */
+/* Analog to Digital Converter */
+/* */
+/******************************************************************************/
+/******************** Bit definition for ADC_SR register ********************/
+#define ADC_SR_AWD 0x00000001U /*!<Analog watchdog flag */
+#define ADC_SR_EOC 0x00000002U /*!<End of conversion */
+#define ADC_SR_JEOC 0x00000004U /*!<Injected channel end of conversion */
+#define ADC_SR_JSTRT 0x00000008U /*!<Injected channel Start flag */
+#define ADC_SR_STRT 0x00000010U /*!<Regular channel Start flag */
+#define ADC_SR_OVR 0x00000020U /*!<Overrun flag */
+
+/******************* Bit definition for ADC_CR1 register ********************/
+#define ADC_CR1_AWDCH 0x0000001FU /*!<AWDCH[4:0] bits (Analog watchdog channel select bits) */
+#define ADC_CR1_AWDCH_0 0x00000001U /*!<Bit 0 */
+#define ADC_CR1_AWDCH_1 0x00000002U /*!<Bit 1 */
+#define ADC_CR1_AWDCH_2 0x00000004U /*!<Bit 2 */
+#define ADC_CR1_AWDCH_3 0x00000008U /*!<Bit 3 */
+#define ADC_CR1_AWDCH_4 0x00000010U /*!<Bit 4 */
+#define ADC_CR1_EOCIE 0x00000020U /*!<Interrupt enable for EOC */
+#define ADC_CR1_AWDIE 0x00000040U /*!<AAnalog Watchdog interrupt enable */
+#define ADC_CR1_JEOCIE 0x00000080U /*!<Interrupt enable for injected channels */
+#define ADC_CR1_SCAN 0x00000100U /*!<Scan mode */
+#define ADC_CR1_AWDSGL 0x00000200U /*!<Enable the watchdog on a single channel in scan mode */
+#define ADC_CR1_JAUTO 0x00000400U /*!<Automatic injected group conversion */
+#define ADC_CR1_DISCEN 0x00000800U /*!<Discontinuous mode on regular channels */
+#define ADC_CR1_JDISCEN 0x00001000U /*!<Discontinuous mode on injected channels */
+#define ADC_CR1_DISCNUM 0x0000E000U /*!<DISCNUM[2:0] bits (Discontinuous mode channel count) */
+#define ADC_CR1_DISCNUM_0 0x00002000U /*!<Bit 0 */
+#define ADC_CR1_DISCNUM_1 0x00004000U /*!<Bit 1 */
+#define ADC_CR1_DISCNUM_2 0x00008000U /*!<Bit 2 */
+#define ADC_CR1_JAWDEN 0x00400000U /*!<Analog watchdog enable on injected channels */
+#define ADC_CR1_AWDEN 0x00800000U /*!<Analog watchdog enable on regular channels */
+#define ADC_CR1_RES 0x03000000U /*!<RES[2:0] bits (Resolution) */
+#define ADC_CR1_RES_0 0x01000000U /*!<Bit 0 */
+#define ADC_CR1_RES_1 0x02000000U /*!<Bit 1 */
+#define ADC_CR1_OVRIE 0x04000000U /*!<overrun interrupt enable */
+
+/******************* Bit definition for ADC_CR2 register ********************/
+#define ADC_CR2_ADON 0x00000001U /*!<A/D Converter ON / OFF */
+#define ADC_CR2_CONT 0x00000002U /*!<Continuous Conversion */
+#define ADC_CR2_DMA 0x00000100U /*!<Direct Memory access mode */
+#define ADC_CR2_DDS 0x00000200U /*!<DMA disable selection (Single ADC) */
+#define ADC_CR2_EOCS 0x00000400U /*!<End of conversion selection */
+#define ADC_CR2_ALIGN 0x00000800U /*!<Data Alignment */
+#define ADC_CR2_JEXTSEL 0x000F0000U /*!<JEXTSEL[3:0] bits (External event select for injected group) */
+#define ADC_CR2_JEXTSEL_0 0x00010000U /*!<Bit 0 */
+#define ADC_CR2_JEXTSEL_1 0x00020000U /*!<Bit 1 */
+#define ADC_CR2_JEXTSEL_2 0x00040000U /*!<Bit 2 */
+#define ADC_CR2_JEXTSEL_3 0x00080000U /*!<Bit 3 */
+#define ADC_CR2_JEXTEN 0x00300000U /*!<JEXTEN[1:0] bits (External Trigger Conversion mode for injected channelsp) */
+#define ADC_CR2_JEXTEN_0 0x00100000U /*!<Bit 0 */
+#define ADC_CR2_JEXTEN_1 0x00200000U /*!<Bit 1 */
+#define ADC_CR2_JSWSTART 0x00400000U /*!<Start Conversion of injected channels */
+#define ADC_CR2_EXTSEL 0x0F000000U /*!<EXTSEL[3:0] bits (External Event Select for regular group) */
+#define ADC_CR2_EXTSEL_0 0x01000000U /*!<Bit 0 */
+#define ADC_CR2_EXTSEL_1 0x02000000U /*!<Bit 1 */
+#define ADC_CR2_EXTSEL_2 0x04000000U /*!<Bit 2 */
+#define ADC_CR2_EXTSEL_3 0x08000000U /*!<Bit 3 */
+#define ADC_CR2_EXTEN 0x30000000U /*!<EXTEN[1:0] bits (External Trigger Conversion mode for regular channelsp) */
+#define ADC_CR2_EXTEN_0 0x10000000U /*!<Bit 0 */
+#define ADC_CR2_EXTEN_1 0x20000000U /*!<Bit 1 */
+#define ADC_CR2_SWSTART 0x40000000U /*!<Start Conversion of regular channels */
+
+/****************** Bit definition for ADC_SMPR1 register *******************/
+#define ADC_SMPR1_SMP10 0x00000007U /*!<SMP10[2:0] bits (Channel 10 Sample time selection) */
+#define ADC_SMPR1_SMP10_0 0x00000001U /*!<Bit 0 */
+#define ADC_SMPR1_SMP10_1 0x00000002U /*!<Bit 1 */
+#define ADC_SMPR1_SMP10_2 0x00000004U /*!<Bit 2 */
+#define ADC_SMPR1_SMP11 0x00000038U /*!<SMP11[2:0] bits (Channel 11 Sample time selection) */
+#define ADC_SMPR1_SMP11_0 0x00000008U /*!<Bit 0 */
+#define ADC_SMPR1_SMP11_1 0x00000010U /*!<Bit 1 */
+#define ADC_SMPR1_SMP11_2 0x00000020U /*!<Bit 2 */
+#define ADC_SMPR1_SMP12 0x000001C0U /*!<SMP12[2:0] bits (Channel 12 Sample time selection) */
+#define ADC_SMPR1_SMP12_0 0x00000040U /*!<Bit 0 */
+#define ADC_SMPR1_SMP12_1 0x00000080U /*!<Bit 1 */
+#define ADC_SMPR1_SMP12_2 0x00000100U /*!<Bit 2 */
+#define ADC_SMPR1_SMP13 0x00000E00U /*!<SMP13[2:0] bits (Channel 13 Sample time selection) */
+#define ADC_SMPR1_SMP13_0 0x00000200U /*!<Bit 0 */
+#define ADC_SMPR1_SMP13_1 0x00000400U /*!<Bit 1 */
+#define ADC_SMPR1_SMP13_2 0x00000800U /*!<Bit 2 */
+#define ADC_SMPR1_SMP14 0x00007000U /*!<SMP14[2:0] bits (Channel 14 Sample time selection) */
+#define ADC_SMPR1_SMP14_0 0x00001000U /*!<Bit 0 */
+#define ADC_SMPR1_SMP14_1 0x00002000U /*!<Bit 1 */
+#define ADC_SMPR1_SMP14_2 0x00004000U /*!<Bit 2 */
+#define ADC_SMPR1_SMP15 0x00038000U /*!<SMP15[2:0] bits (Channel 15 Sample time selection) */
+#define ADC_SMPR1_SMP15_0 0x00008000U /*!<Bit 0 */
+#define ADC_SMPR1_SMP15_1 0x00010000U /*!<Bit 1 */
+#define ADC_SMPR1_SMP15_2 0x00020000U /*!<Bit 2 */
+#define ADC_SMPR1_SMP16 0x001C0000U /*!<SMP16[2:0] bits (Channel 16 Sample time selection) */
+#define ADC_SMPR1_SMP16_0 0x00040000U /*!<Bit 0 */
+#define ADC_SMPR1_SMP16_1 0x00080000U /*!<Bit 1 */
+#define ADC_SMPR1_SMP16_2 0x00100000U /*!<Bit 2 */
+#define ADC_SMPR1_SMP17 0x00E00000U /*!<SMP17[2:0] bits (Channel 17 Sample time selection) */
+#define ADC_SMPR1_SMP17_0 0x00200000U /*!<Bit 0 */
+#define ADC_SMPR1_SMP17_1 0x00400000U /*!<Bit 1 */
+#define ADC_SMPR1_SMP17_2 0x00800000U /*!<Bit 2 */
+#define ADC_SMPR1_SMP18 0x07000000U /*!<SMP18[2:0] bits (Channel 18 Sample time selection) */
+#define ADC_SMPR1_SMP18_0 0x01000000U /*!<Bit 0 */
+#define ADC_SMPR1_SMP18_1 0x02000000U /*!<Bit 1 */
+#define ADC_SMPR1_SMP18_2 0x04000000U /*!<Bit 2 */
+
+/****************** Bit definition for ADC_SMPR2 register *******************/
+#define ADC_SMPR2_SMP0 0x00000007U /*!<SMP0[2:0] bits (Channel 0 Sample time selection) */
+#define ADC_SMPR2_SMP0_0 0x00000001U /*!<Bit 0 */
+#define ADC_SMPR2_SMP0_1 0x00000002U /*!<Bit 1 */
+#define ADC_SMPR2_SMP0_2 0x00000004U /*!<Bit 2 */
+#define ADC_SMPR2_SMP1 0x00000038U /*!<SMP1[2:0] bits (Channel 1 Sample time selection) */
+#define ADC_SMPR2_SMP1_0 0x00000008U /*!<Bit 0 */
+#define ADC_SMPR2_SMP1_1 0x00000010U /*!<Bit 1 */
+#define ADC_SMPR2_SMP1_2 0x00000020U /*!<Bit 2 */
+#define ADC_SMPR2_SMP2 0x000001C0U /*!<SMP2[2:0] bits (Channel 2 Sample time selection) */
+#define ADC_SMPR2_SMP2_0 0x00000040U /*!<Bit 0 */
+#define ADC_SMPR2_SMP2_1 0x00000080U /*!<Bit 1 */
+#define ADC_SMPR2_SMP2_2 0x00000100U /*!<Bit 2 */
+#define ADC_SMPR2_SMP3 0x00000E00U /*!<SMP3[2:0] bits (Channel 3 Sample time selection) */
+#define ADC_SMPR2_SMP3_0 0x00000200U /*!<Bit 0 */
+#define ADC_SMPR2_SMP3_1 0x00000400U /*!<Bit 1 */
+#define ADC_SMPR2_SMP3_2 0x00000800U /*!<Bit 2 */
+#define ADC_SMPR2_SMP4 0x00007000U /*!<SMP4[2:0] bits (Channel 4 Sample time selection) */
+#define ADC_SMPR2_SMP4_0 0x00001000U /*!<Bit 0 */
+#define ADC_SMPR2_SMP4_1 0x00002000U /*!<Bit 1 */
+#define ADC_SMPR2_SMP4_2 0x00004000U /*!<Bit 2 */
+#define ADC_SMPR2_SMP5 0x00038000U /*!<SMP5[2:0] bits (Channel 5 Sample time selection) */
+#define ADC_SMPR2_SMP5_0 0x00008000U /*!<Bit 0 */
+#define ADC_SMPR2_SMP5_1 0x00010000U /*!<Bit 1 */
+#define ADC_SMPR2_SMP5_2 0x00020000U /*!<Bit 2 */
+#define ADC_SMPR2_SMP6 0x001C0000U /*!<SMP6[2:0] bits (Channel 6 Sample time selection) */
+#define ADC_SMPR2_SMP6_0 0x00040000U /*!<Bit 0 */
+#define ADC_SMPR2_SMP6_1 0x00080000U /*!<Bit 1 */
+#define ADC_SMPR2_SMP6_2 0x00100000U /*!<Bit 2 */
+#define ADC_SMPR2_SMP7 0x00E00000U /*!<SMP7[2:0] bits (Channel 7 Sample time selection) */
+#define ADC_SMPR2_SMP7_0 0x00200000U /*!<Bit 0 */
+#define ADC_SMPR2_SMP7_1 0x00400000U /*!<Bit 1 */
+#define ADC_SMPR2_SMP7_2 0x00800000U /*!<Bit 2 */
+#define ADC_SMPR2_SMP8 0x07000000U /*!<SMP8[2:0] bits (Channel 8 Sample time selection) */
+#define ADC_SMPR2_SMP8_0 0x01000000U /*!<Bit 0 */
+#define ADC_SMPR2_SMP8_1 0x02000000U /*!<Bit 1 */
+#define ADC_SMPR2_SMP8_2 0x04000000U /*!<Bit 2 */
+#define ADC_SMPR2_SMP9 0x38000000U /*!<SMP9[2:0] bits (Channel 9 Sample time selection) */
+#define ADC_SMPR2_SMP9_0 0x08000000U /*!<Bit 0 */
+#define ADC_SMPR2_SMP9_1 0x10000000U /*!<Bit 1 */
+#define ADC_SMPR2_SMP9_2 0x20000000U /*!<Bit 2 */
+
+/****************** Bit definition for ADC_JOFR1 register *******************/
+#define ADC_JOFR1_JOFFSET1 0x0FFFU /*!<Data offset for injected channel 1 */
+
+/****************** Bit definition for ADC_JOFR2 register *******************/
+#define ADC_JOFR2_JOFFSET2 0x0FFFU /*!<Data offset for injected channel 2 */
+
+/****************** Bit definition for ADC_JOFR3 register *******************/
+#define ADC_JOFR3_JOFFSET3 0x0FFFU /*!<Data offset for injected channel 3 */
+
+/****************** Bit definition for ADC_JOFR4 register *******************/
+#define ADC_JOFR4_JOFFSET4 0x0FFFU /*!<Data offset for injected channel 4 */
+
+/******************* Bit definition for ADC_HTR register ********************/
+#define ADC_HTR_HT 0x0FFFU /*!<Analog watchdog high threshold */
+
+/******************* Bit definition for ADC_LTR register ********************/
+#define ADC_LTR_LT 0x0FFFU /*!<Analog watchdog low threshold */
+
+/******************* Bit definition for ADC_SQR1 register *******************/
+#define ADC_SQR1_SQ13 0x0000001FU /*!<SQ13[4:0] bits (13th conversion in regular sequence) */
+#define ADC_SQR1_SQ13_0 0x00000001U /*!<Bit 0 */
+#define ADC_SQR1_SQ13_1 0x00000002U /*!<Bit 1 */
+#define ADC_SQR1_SQ13_2 0x00000004U /*!<Bit 2 */
+#define ADC_SQR1_SQ13_3 0x00000008U /*!<Bit 3 */
+#define ADC_SQR1_SQ13_4 0x00000010U /*!<Bit 4 */
+#define ADC_SQR1_SQ14 0x000003E0U /*!<SQ14[4:0] bits (14th conversion in regular sequence) */
+#define ADC_SQR1_SQ14_0 0x00000020U /*!<Bit 0 */
+#define ADC_SQR1_SQ14_1 0x00000040U /*!<Bit 1 */
+#define ADC_SQR1_SQ14_2 0x00000080U /*!<Bit 2 */
+#define ADC_SQR1_SQ14_3 0x00000100U /*!<Bit 3 */
+#define ADC_SQR1_SQ14_4 0x00000200U /*!<Bit 4 */
+#define ADC_SQR1_SQ15 0x00007C00U /*!<SQ15[4:0] bits (15th conversion in regular sequence) */
+#define ADC_SQR1_SQ15_0 0x00000400U /*!<Bit 0 */
+#define ADC_SQR1_SQ15_1 0x00000800U /*!<Bit 1 */
+#define ADC_SQR1_SQ15_2 0x00001000U /*!<Bit 2 */
+#define ADC_SQR1_SQ15_3 0x00002000U /*!<Bit 3 */
+#define ADC_SQR1_SQ15_4 0x00004000U /*!<Bit 4 */
+#define ADC_SQR1_SQ16 0x000F8000U /*!<SQ16[4:0] bits (16th conversion in regular sequence) */
+#define ADC_SQR1_SQ16_0 0x00008000U /*!<Bit 0 */
+#define ADC_SQR1_SQ16_1 0x00010000U /*!<Bit 1 */
+#define ADC_SQR1_SQ16_2 0x00020000U /*!<Bit 2 */
+#define ADC_SQR1_SQ16_3 0x00040000U /*!<Bit 3 */
+#define ADC_SQR1_SQ16_4 0x00080000U /*!<Bit 4 */
+#define ADC_SQR1_L 0x00F00000U /*!<L[3:0] bits (Regular channel sequence length) */
+#define ADC_SQR1_L_0 0x00100000U /*!<Bit 0 */
+#define ADC_SQR1_L_1 0x00200000U /*!<Bit 1 */
+#define ADC_SQR1_L_2 0x00400000U /*!<Bit 2 */
+#define ADC_SQR1_L_3 0x00800000U /*!<Bit 3 */
+
+/******************* Bit definition for ADC_SQR2 register *******************/
+#define ADC_SQR2_SQ7 0x0000001FU /*!<SQ7[4:0] bits (7th conversion in regular sequence) */
+#define ADC_SQR2_SQ7_0 0x00000001U /*!<Bit 0 */
+#define ADC_SQR2_SQ7_1 0x00000002U /*!<Bit 1 */
+#define ADC_SQR2_SQ7_2 0x00000004U /*!<Bit 2 */
+#define ADC_SQR2_SQ7_3 0x00000008U /*!<Bit 3 */
+#define ADC_SQR2_SQ7_4 0x00000010U /*!<Bit 4 */
+#define ADC_SQR2_SQ8 0x000003E0U /*!<SQ8[4:0] bits (8th conversion in regular sequence) */
+#define ADC_SQR2_SQ8_0 0x00000020U /*!<Bit 0 */
+#define ADC_SQR2_SQ8_1 0x00000040U /*!<Bit 1 */
+#define ADC_SQR2_SQ8_2 0x00000080U /*!<Bit 2 */
+#define ADC_SQR2_SQ8_3 0x00000100U /*!<Bit 3 */
+#define ADC_SQR2_SQ8_4 0x00000200U /*!<Bit 4 */
+#define ADC_SQR2_SQ9 0x00007C00U /*!<SQ9[4:0] bits (9th conversion in regular sequence) */
+#define ADC_SQR2_SQ9_0 0x00000400U /*!<Bit 0 */
+#define ADC_SQR2_SQ9_1 0x00000800U /*!<Bit 1 */
+#define ADC_SQR2_SQ9_2 0x00001000U /*!<Bit 2 */
+#define ADC_SQR2_SQ9_3 0x00002000U /*!<Bit 3 */
+#define ADC_SQR2_SQ9_4 0x00004000U /*!<Bit 4 */
+#define ADC_SQR2_SQ10 0x000F8000U /*!<SQ10[4:0] bits (10th conversion in regular sequence) */
+#define ADC_SQR2_SQ10_0 0x00008000U /*!<Bit 0 */
+#define ADC_SQR2_SQ10_1 0x00010000U /*!<Bit 1 */
+#define ADC_SQR2_SQ10_2 0x00020000U /*!<Bit 2 */
+#define ADC_SQR2_SQ10_3 0x00040000U /*!<Bit 3 */
+#define ADC_SQR2_SQ10_4 0x00080000U /*!<Bit 4 */
+#define ADC_SQR2_SQ11 0x01F00000U /*!<SQ11[4:0] bits (11th conversion in regular sequence) */
+#define ADC_SQR2_SQ11_0 0x00100000U /*!<Bit 0 */
+#define ADC_SQR2_SQ11_1 0x00200000U /*!<Bit 1 */
+#define ADC_SQR2_SQ11_2 0x00400000U /*!<Bit 2 */
+#define ADC_SQR2_SQ11_3 0x00800000U /*!<Bit 3 */
+#define ADC_SQR2_SQ11_4 0x01000000U /*!<Bit 4 */
+#define ADC_SQR2_SQ12 0x3E000000U /*!<SQ12[4:0] bits (12th conversion in regular sequence) */
+#define ADC_SQR2_SQ12_0 0x02000000U /*!<Bit 0 */
+#define ADC_SQR2_SQ12_1 0x04000000U /*!<Bit 1 */
+#define ADC_SQR2_SQ12_2 0x08000000U /*!<Bit 2 */
+#define ADC_SQR2_SQ12_3 0x10000000U /*!<Bit 3 */
+#define ADC_SQR2_SQ12_4 0x20000000U /*!<Bit 4 */
+
+/******************* Bit definition for ADC_SQR3 register *******************/
+#define ADC_SQR3_SQ1 0x0000001FU /*!<SQ1[4:0] bits (1st conversion in regular sequence) */
+#define ADC_SQR3_SQ1_0 0x00000001U /*!<Bit 0 */
+#define ADC_SQR3_SQ1_1 0x00000002U /*!<Bit 1 */
+#define ADC_SQR3_SQ1_2 0x00000004U /*!<Bit 2 */
+#define ADC_SQR3_SQ1_3 0x00000008U /*!<Bit 3 */
+#define ADC_SQR3_SQ1_4 0x00000010U /*!<Bit 4 */
+#define ADC_SQR3_SQ2 0x000003E0U /*!<SQ2[4:0] bits (2nd conversion in regular sequence) */
+#define ADC_SQR3_SQ2_0 0x00000020U /*!<Bit 0 */
+#define ADC_SQR3_SQ2_1 0x00000040U /*!<Bit 1 */
+#define ADC_SQR3_SQ2_2 0x00000080U /*!<Bit 2 */
+#define ADC_SQR3_SQ2_3 0x00000100U /*!<Bit 3 */
+#define ADC_SQR3_SQ2_4 0x00000200U /*!<Bit 4 */
+#define ADC_SQR3_SQ3 0x00007C00U /*!<SQ3[4:0] bits (3rd conversion in regular sequence) */
+#define ADC_SQR3_SQ3_0 0x00000400U /*!<Bit 0 */
+#define ADC_SQR3_SQ3_1 0x00000800U /*!<Bit 1 */
+#define ADC_SQR3_SQ3_2 0x00001000U /*!<Bit 2 */
+#define ADC_SQR3_SQ3_3 0x00002000U /*!<Bit 3 */
+#define ADC_SQR3_SQ3_4 0x00004000U /*!<Bit 4 */
+#define ADC_SQR3_SQ4 0x000F8000U /*!<SQ4[4:0] bits (4th conversion in regular sequence) */
+#define ADC_SQR3_SQ4_0 0x00008000U /*!<Bit 0 */
+#define ADC_SQR3_SQ4_1 0x00010000U /*!<Bit 1 */
+#define ADC_SQR3_SQ4_2 0x00020000U /*!<Bit 2 */
+#define ADC_SQR3_SQ4_3 0x00040000U /*!<Bit 3 */
+#define ADC_SQR3_SQ4_4 0x00080000U /*!<Bit 4 */
+#define ADC_SQR3_SQ5 0x01F00000U /*!<SQ5[4:0] bits (5th conversion in regular sequence) */
+#define ADC_SQR3_SQ5_0 0x00100000U /*!<Bit 0 */
+#define ADC_SQR3_SQ5_1 0x00200000U /*!<Bit 1 */
+#define ADC_SQR3_SQ5_2 0x00400000U /*!<Bit 2 */
+#define ADC_SQR3_SQ5_3 0x00800000U /*!<Bit 3 */
+#define ADC_SQR3_SQ5_4 0x01000000U /*!<Bit 4 */
+#define ADC_SQR3_SQ6 0x3E000000U /*!<SQ6[4:0] bits (6th conversion in regular sequence) */
+#define ADC_SQR3_SQ6_0 0x02000000U /*!<Bit 0 */
+#define ADC_SQR3_SQ6_1 0x04000000U /*!<Bit 1 */
+#define ADC_SQR3_SQ6_2 0x08000000U /*!<Bit 2 */
+#define ADC_SQR3_SQ6_3 0x10000000U /*!<Bit 3 */
+#define ADC_SQR3_SQ6_4 0x20000000U /*!<Bit 4 */
+
+/******************* Bit definition for ADC_JSQR register *******************/
+#define ADC_JSQR_JSQ1 0x0000001FU /*!<JSQ1[4:0] bits (1st conversion in injected sequence) */
+#define ADC_JSQR_JSQ1_0 0x00000001U /*!<Bit 0 */
+#define ADC_JSQR_JSQ1_1 0x00000002U /*!<Bit 1 */
+#define ADC_JSQR_JSQ1_2 0x00000004U /*!<Bit 2 */
+#define ADC_JSQR_JSQ1_3 0x00000008U /*!<Bit 3 */
+#define ADC_JSQR_JSQ1_4 0x00000010U /*!<Bit 4 */
+#define ADC_JSQR_JSQ2 0x000003E0U /*!<JSQ2[4:0] bits (2nd conversion in injected sequence) */
+#define ADC_JSQR_JSQ2_0 0x00000020U /*!<Bit 0 */
+#define ADC_JSQR_JSQ2_1 0x00000040U /*!<Bit 1 */
+#define ADC_JSQR_JSQ2_2 0x00000080U /*!<Bit 2 */
+#define ADC_JSQR_JSQ2_3 0x00000100U /*!<Bit 3 */
+#define ADC_JSQR_JSQ2_4 0x00000200U /*!<Bit 4 */
+#define ADC_JSQR_JSQ3 0x00007C00U /*!<JSQ3[4:0] bits (3rd conversion in injected sequence) */
+#define ADC_JSQR_JSQ3_0 0x00000400U /*!<Bit 0 */
+#define ADC_JSQR_JSQ3_1 0x00000800U /*!<Bit 1 */
+#define ADC_JSQR_JSQ3_2 0x00001000U /*!<Bit 2 */
+#define ADC_JSQR_JSQ3_3 0x00002000U /*!<Bit 3 */
+#define ADC_JSQR_JSQ3_4 0x00004000U /*!<Bit 4 */
+#define ADC_JSQR_JSQ4 0x000F8000U /*!<JSQ4[4:0] bits (4th conversion in injected sequence) */
+#define ADC_JSQR_JSQ4_0 0x00008000U /*!<Bit 0 */
+#define ADC_JSQR_JSQ4_1 0x00010000U /*!<Bit 1 */
+#define ADC_JSQR_JSQ4_2 0x00020000U /*!<Bit 2 */
+#define ADC_JSQR_JSQ4_3 0x00040000U /*!<Bit 3 */
+#define ADC_JSQR_JSQ4_4 0x00080000U /*!<Bit 4 */
+#define ADC_JSQR_JL 0x00300000U /*!<JL[1:0] bits (Injected Sequence length) */
+#define ADC_JSQR_JL_0 0x00100000U /*!<Bit 0 */
+#define ADC_JSQR_JL_1 0x00200000U /*!<Bit 1 */
+
+/******************* Bit definition for ADC_JDR1 register *******************/
+#define ADC_JDR1_JDATA 0xFFFFU /*!<Injected data */
+
+/******************* Bit definition for ADC_JDR2 register *******************/
+#define ADC_JDR2_JDATA 0xFFFFU /*!<Injected data */
+
+/******************* Bit definition for ADC_JDR3 register *******************/
+#define ADC_JDR3_JDATA 0xFFFFU /*!<Injected data */
+
+/******************* Bit definition for ADC_JDR4 register *******************/
+#define ADC_JDR4_JDATA 0xFFFFU /*!<Injected data */
+
+/******************** Bit definition for ADC_DR register ********************/
+#define ADC_DR_DATA 0x0000FFFFU /*!<Regular data */
+#define ADC_DR_ADC2DATA 0xFFFF0000U /*!<ADC2 data */
+
+/******************* Bit definition for ADC_CSR register ********************/
+#define ADC_CSR_AWD1 0x00000001U /*!<ADC1 Analog watchdog flag */
+#define ADC_CSR_EOC1 0x00000002U /*!<ADC1 End of conversion */
+#define ADC_CSR_JEOC1 0x00000004U /*!<ADC1 Injected channel end of conversion */
+#define ADC_CSR_JSTRT1 0x00000008U /*!<ADC1 Injected channel Start flag */
+#define ADC_CSR_STRT1 0x00000010U /*!<ADC1 Regular channel Start flag */
+#define ADC_CSR_OVR1 0x00000020U /*!<ADC1 DMA overrun flag */
+#define ADC_CSR_AWD2 0x00000100U /*!<ADC2 Analog watchdog flag */
+#define ADC_CSR_EOC2 0x00000200U /*!<ADC2 End of conversion */
+#define ADC_CSR_JEOC2 0x00000400U /*!<ADC2 Injected channel end of conversion */
+#define ADC_CSR_JSTRT2 0x00000800U /*!<ADC2 Injected channel Start flag */
+#define ADC_CSR_STRT2 0x00001000U /*!<ADC2 Regular channel Start flag */
+#define ADC_CSR_OVR2 0x00002000U /*!<ADC2 DMA overrun flag */
+#define ADC_CSR_AWD3 0x00010000U /*!<ADC3 Analog watchdog flag */
+#define ADC_CSR_EOC3 0x00020000U /*!<ADC3 End of conversion */
+#define ADC_CSR_JEOC3 0x00040000U /*!<ADC3 Injected channel end of conversion */
+#define ADC_CSR_JSTRT3 0x00080000U /*!<ADC3 Injected channel Start flag */
+#define ADC_CSR_STRT3 0x00100000U /*!<ADC3 Regular channel Start flag */
+#define ADC_CSR_OVR3 0x00200000U /*!<ADC3 DMA overrun flag */
+
+/* Legacy defines */
+#define ADC_CSR_DOVR1 ADC_CSR_OVR1
+#define ADC_CSR_DOVR2 ADC_CSR_OVR2
+#define ADC_CSR_DOVR3 ADC_CSR_OVR3
+
+/******************* Bit definition for ADC_CCR register ********************/
+#define ADC_CCR_MULTI 0x0000001FU /*!<MULTI[4:0] bits (Multi-ADC mode selection) */
+#define ADC_CCR_MULTI_0 0x00000001U /*!<Bit 0 */
+#define ADC_CCR_MULTI_1 0x00000002U /*!<Bit 1 */
+#define ADC_CCR_MULTI_2 0x00000004U /*!<Bit 2 */
+#define ADC_CCR_MULTI_3 0x00000008U /*!<Bit 3 */
+#define ADC_CCR_MULTI_4 0x00000010U /*!<Bit 4 */
+#define ADC_CCR_DELAY 0x00000F00U /*!<DELAY[3:0] bits (Delay between 2 sampling phases) */
+#define ADC_CCR_DELAY_0 0x00000100U /*!<Bit 0 */
+#define ADC_CCR_DELAY_1 0x00000200U /*!<Bit 1 */
+#define ADC_CCR_DELAY_2 0x00000400U /*!<Bit 2 */
+#define ADC_CCR_DELAY_3 0x00000800U /*!<Bit 3 */
+#define ADC_CCR_DDS 0x00002000U /*!<DMA disable selection (Multi-ADC mode) */
+#define ADC_CCR_DMA 0x0000C000U /*!<DMA[1:0] bits (Direct Memory Access mode for multimode) */
+#define ADC_CCR_DMA_0 0x00004000U /*!<Bit 0 */
+#define ADC_CCR_DMA_1 0x00008000U /*!<Bit 1 */
+#define ADC_CCR_ADCPRE 0x00030000U /*!<ADCPRE[1:0] bits (ADC prescaler) */
+#define ADC_CCR_ADCPRE_0 0x00010000U /*!<Bit 0 */
+#define ADC_CCR_ADCPRE_1 0x00020000U /*!<Bit 1 */
+#define ADC_CCR_VBATE 0x00400000U /*!<VBAT Enable */
+#define ADC_CCR_TSVREFE 0x00800000U /*!<Temperature Sensor and VREFINT Enable */
+
+/******************* Bit definition for ADC_CDR register ********************/
+#define ADC_CDR_DATA1 0x0000FFFFU /*!<1st data of a pair of regular conversions */
+#define ADC_CDR_DATA2 0xFFFF0000U /*!<2nd data of a pair of regular conversions */
+
+/******************************************************************************/
+/* */
+/* Controller Area Network */
+/* */
+/******************************************************************************/
+/*!<CAN control and status registers */
+/******************* Bit definition for CAN_MCR register ********************/
+#define CAN_MCR_INRQ 0x00000001U /*!<Initialization Request */
+#define CAN_MCR_SLEEP 0x00000002U /*!<Sleep Mode Request */
+#define CAN_MCR_TXFP 0x00000004U /*!<Transmit FIFO Priority */
+#define CAN_MCR_RFLM 0x00000008U /*!<Receive FIFO Locked Mode */
+#define CAN_MCR_NART 0x00000010U /*!<No Automatic Retransmission */
+#define CAN_MCR_AWUM 0x00000020U /*!<Automatic Wakeup Mode */
+#define CAN_MCR_ABOM 0x00000040U /*!<Automatic Bus-Off Management */
+#define CAN_MCR_TTCM 0x00000080U /*!<Time Triggered Communication Mode */
+#define CAN_MCR_RESET 0x00008000U /*!<bxCAN software master reset */
+#define CAN_MCR_DBF 0x00010000U /*!<bxCAN Debug freeze */
+/******************* Bit definition for CAN_MSR register ********************/
+#define CAN_MSR_INAK 0x0001U /*!<Initialization Acknowledge */
+#define CAN_MSR_SLAK 0x0002U /*!<Sleep Acknowledge */
+#define CAN_MSR_ERRI 0x0004U /*!<Error Interrupt */
+#define CAN_MSR_WKUI 0x0008U /*!<Wakeup Interrupt */
+#define CAN_MSR_SLAKI 0x0010U /*!<Sleep Acknowledge Interrupt */
+#define CAN_MSR_TXM 0x0100U /*!<Transmit Mode */
+#define CAN_MSR_RXM 0x0200U /*!<Receive Mode */
+#define CAN_MSR_SAMP 0x0400U /*!<Last Sample Point */
+#define CAN_MSR_RX 0x0800U /*!<CAN Rx Signal */
+
+/******************* Bit definition for CAN_TSR register ********************/
+#define CAN_TSR_RQCP0 0x00000001U /*!<Request Completed Mailbox0 */
+#define CAN_TSR_TXOK0 0x00000002U /*!<Transmission OK of Mailbox0 */
+#define CAN_TSR_ALST0 0x00000004U /*!<Arbitration Lost for Mailbox0 */
+#define CAN_TSR_TERR0 0x00000008U /*!<Transmission Error of Mailbox0 */
+#define CAN_TSR_ABRQ0 0x00000080U /*!<Abort Request for Mailbox0 */
+#define CAN_TSR_RQCP1 0x00000100U /*!<Request Completed Mailbox1 */
+#define CAN_TSR_TXOK1 0x00000200U /*!<Transmission OK of Mailbox1 */
+#define CAN_TSR_ALST1 0x00000400U /*!<Arbitration Lost for Mailbox1 */
+#define CAN_TSR_TERR1 0x00000800U /*!<Transmission Error of Mailbox1 */
+#define CAN_TSR_ABRQ1 0x00008000U /*!<Abort Request for Mailbox 1 */
+#define CAN_TSR_RQCP2 0x00010000U /*!<Request Completed Mailbox2 */
+#define CAN_TSR_TXOK2 0x00020000U /*!<Transmission OK of Mailbox 2 */
+#define CAN_TSR_ALST2 0x00040000U /*!<Arbitration Lost for mailbox 2 */
+#define CAN_TSR_TERR2 0x00080000U /*!<Transmission Error of Mailbox 2 */
+#define CAN_TSR_ABRQ2 0x00800000U /*!<Abort Request for Mailbox 2 */
+#define CAN_TSR_CODE 0x03000000U /*!<Mailbox Code */
+
+#define CAN_TSR_TME 0x1C000000U /*!<TME[2:0] bits */
+#define CAN_TSR_TME0 0x04000000U /*!<Transmit Mailbox 0 Empty */
+#define CAN_TSR_TME1 0x08000000U /*!<Transmit Mailbox 1 Empty */
+#define CAN_TSR_TME2 0x10000000U /*!<Transmit Mailbox 2 Empty */
+
+#define CAN_TSR_LOW 0xE0000000U /*!<LOW[2:0] bits */
+#define CAN_TSR_LOW0 0x20000000U /*!<Lowest Priority Flag for Mailbox 0 */
+#define CAN_TSR_LOW1 0x40000000U /*!<Lowest Priority Flag for Mailbox 1 */
+#define CAN_TSR_LOW2 0x80000000U /*!<Lowest Priority Flag for Mailbox 2 */
+
+/******************* Bit definition for CAN_RF0R register *******************/
+#define CAN_RF0R_FMP0 0x03U /*!<FIFO 0 Message Pending */
+#define CAN_RF0R_FULL0 0x08U /*!<FIFO 0 Full */
+#define CAN_RF0R_FOVR0 0x10U /*!<FIFO 0 Overrun */
+#define CAN_RF0R_RFOM0 0x20U /*!<Release FIFO 0 Output Mailbox */
+
+/******************* Bit definition for CAN_RF1R register *******************/
+#define CAN_RF1R_FMP1 0x03U /*!<FIFO 1 Message Pending */
+#define CAN_RF1R_FULL1 0x08U /*!<FIFO 1 Full */
+#define CAN_RF1R_FOVR1 0x10U /*!<FIFO 1 Overrun */
+#define CAN_RF1R_RFOM1 0x20U /*!<Release FIFO 1 Output Mailbox */
+
+/******************** Bit definition for CAN_IER register *******************/
+#define CAN_IER_TMEIE 0x00000001U /*!<Transmit Mailbox Empty Interrupt Enable */
+#define CAN_IER_FMPIE0 0x00000002U /*!<FIFO Message Pending Interrupt Enable */
+#define CAN_IER_FFIE0 0x00000004U /*!<FIFO Full Interrupt Enable */
+#define CAN_IER_FOVIE0 0x00000008U /*!<FIFO Overrun Interrupt Enable */
+#define CAN_IER_FMPIE1 0x00000010U /*!<FIFO Message Pending Interrupt Enable */
+#define CAN_IER_FFIE1 0x00000020U /*!<FIFO Full Interrupt Enable */
+#define CAN_IER_FOVIE1 0x00000040U /*!<FIFO Overrun Interrupt Enable */
+#define CAN_IER_EWGIE 0x00000100U /*!<Error Warning Interrupt Enable */
+#define CAN_IER_EPVIE 0x00000200U /*!<Error Passive Interrupt Enable */
+#define CAN_IER_BOFIE 0x00000400U /*!<Bus-Off Interrupt Enable */
+#define CAN_IER_LECIE 0x00000800U /*!<Last Error Code Interrupt Enable */
+#define CAN_IER_ERRIE 0x00008000U /*!<Error Interrupt Enable */
+#define CAN_IER_WKUIE 0x00010000U /*!<Wakeup Interrupt Enable */
+#define CAN_IER_SLKIE 0x00020000U /*!<Sleep Interrupt Enable */
+#define CAN_IER_EWGIE 0x00000100U /*!<Error warning interrupt enable */
+#define CAN_IER_EPVIE 0x00000200U /*!<Error passive interrupt enable */
+#define CAN_IER_BOFIE 0x00000400U /*!<Bus-off interrupt enable */
+#define CAN_IER_LECIE 0x00000800U /*!<Last error code interrupt enable */
+#define CAN_IER_ERRIE 0x00008000U /*!<Error interrupt enable */
+
+
+/******************** Bit definition for CAN_ESR register *******************/
+#define CAN_ESR_EWGF 0x00000001U /*!<Error Warning Flag */
+#define CAN_ESR_EPVF 0x00000002U /*!<Error Passive Flag */
+#define CAN_ESR_BOFF 0x00000004U /*!<Bus-Off Flag */
+
+#define CAN_ESR_LEC 0x00000070U /*!<LEC[2:0] bits (Last Error Code) */
+#define CAN_ESR_LEC_0 0x00000010U /*!<Bit 0 */
+#define CAN_ESR_LEC_1 0x00000020U /*!<Bit 1 */
+#define CAN_ESR_LEC_2 0x00000040U /*!<Bit 2 */
+
+#define CAN_ESR_TEC 0x00FF0000U /*!<Least significant byte of the 9-bit Transmit Error Counter */
+#define CAN_ESR_REC 0xFF000000U /*!<Receive Error Counter */
+
+/******************* Bit definition for CAN_BTR register ********************/
+#define CAN_BTR_BRP 0x000003FFU /*!<Baud Rate Prescaler */
+#define CAN_BTR_TS1 0x000F0000U /*!<Time Segment 1 */
+#define CAN_BTR_TS1_0 0x00010000U /*!<Bit 0 */
+#define CAN_BTR_TS1_1 0x00020000U /*!<Bit 1 */
+#define CAN_BTR_TS1_2 0x00040000U /*!<Bit 2 */
+#define CAN_BTR_TS1_3 0x00080000U /*!<Bit 3 */
+#define CAN_BTR_TS2 0x00700000U /*!<Time Segment 2 */
+#define CAN_BTR_TS2_0 0x00100000U /*!<Bit 0 */
+#define CAN_BTR_TS2_1 0x00200000U /*!<Bit 1 */
+#define CAN_BTR_TS2_2 0x00400000U /*!<Bit 2 */
+#define CAN_BTR_SJW 0x03000000U /*!<Resynchronization Jump Width */
+#define CAN_BTR_SJW_0 0x01000000U /*!<Bit 0 */
+#define CAN_BTR_SJW_1 0x02000000U /*!<Bit 1 */
+#define CAN_BTR_LBKM 0x40000000U /*!<Loop Back Mode (Debug) */
+#define CAN_BTR_SILM 0x80000000U /*!<Silent Mode */
+
+
+/*!<Mailbox registers */
+/****************** Bit definition for CAN_TI0R register ********************/
+#define CAN_TI0R_TXRQ 0x00000001U /*!<Transmit Mailbox Request */
+#define CAN_TI0R_RTR 0x00000002U /*!<Remote Transmission Request */
+#define CAN_TI0R_IDE 0x00000004U /*!<Identifier Extension */
+#define CAN_TI0R_EXID 0x001FFFF8U /*!<Extended Identifier */
+#define CAN_TI0R_STID 0xFFE00000U /*!<Standard Identifier or Extended Identifier */
+
+/****************** Bit definition for CAN_TDT0R register *******************/
+#define CAN_TDT0R_DLC 0x0000000FU /*!<Data Length Code */
+#define CAN_TDT0R_TGT 0x00000100U /*!<Transmit Global Time */
+#define CAN_TDT0R_TIME 0xFFFF0000U /*!<Message Time Stamp */
+
+/****************** Bit definition for CAN_TDL0R register *******************/
+#define CAN_TDL0R_DATA0 0x000000FFU /*!<Data byte 0 */
+#define CAN_TDL0R_DATA1 0x0000FF00U /*!<Data byte 1 */
+#define CAN_TDL0R_DATA2 0x00FF0000U /*!<Data byte 2 */
+#define CAN_TDL0R_DATA3 0xFF000000U /*!<Data byte 3 */
+
+/****************** Bit definition for CAN_TDH0R register *******************/
+#define CAN_TDH0R_DATA4 0x000000FFU /*!<Data byte 4 */
+#define CAN_TDH0R_DATA5 0x0000FF00U /*!<Data byte 5 */
+#define CAN_TDH0R_DATA6 0x00FF0000U /*!<Data byte 6 */
+#define CAN_TDH0R_DATA7 0xFF000000U /*!<Data byte 7 */
+
+/******************* Bit definition for CAN_TI1R register *******************/
+#define CAN_TI1R_TXRQ 0x00000001U /*!<Transmit Mailbox Request */
+#define CAN_TI1R_RTR 0x00000002U /*!<Remote Transmission Request */
+#define CAN_TI1R_IDE 0x00000004U /*!<Identifier Extension */
+#define CAN_TI1R_EXID 0x001FFFF8U /*!<Extended Identifier */
+#define CAN_TI1R_STID 0xFFE00000U /*!<Standard Identifier or Extended Identifier */
+
+/******************* Bit definition for CAN_TDT1R register ******************/
+#define CAN_TDT1R_DLC 0x0000000FU /*!<Data Length Code */
+#define CAN_TDT1R_TGT 0x00000100U /*!<Transmit Global Time */
+#define CAN_TDT1R_TIME 0xFFFF0000U /*!<Message Time Stamp */
+
+/******************* Bit definition for CAN_TDL1R register ******************/
+#define CAN_TDL1R_DATA0 0x000000FFU /*!<Data byte 0 */
+#define CAN_TDL1R_DATA1 0x0000FF00U /*!<Data byte 1 */
+#define CAN_TDL1R_DATA2 0x00FF0000U /*!<Data byte 2 */
+#define CAN_TDL1R_DATA3 0xFF000000U /*!<Data byte 3 */
+
+/******************* Bit definition for CAN_TDH1R register ******************/
+#define CAN_TDH1R_DATA4 0x000000FFU /*!<Data byte 4 */
+#define CAN_TDH1R_DATA5 0x0000FF00U /*!<Data byte 5 */
+#define CAN_TDH1R_DATA6 0x00FF0000U /*!<Data byte 6 */
+#define CAN_TDH1R_DATA7 0xFF000000U /*!<Data byte 7 */
+
+/******************* Bit definition for CAN_TI2R register *******************/
+#define CAN_TI2R_TXRQ 0x00000001U /*!<Transmit Mailbox Request */
+#define CAN_TI2R_RTR 0x00000002U /*!<Remote Transmission Request */
+#define CAN_TI2R_IDE 0x00000004U /*!<Identifier Extension */
+#define CAN_TI2R_EXID 0x001FFFF8U /*!<Extended identifier */
+#define CAN_TI2R_STID 0xFFE00000U /*!<Standard Identifier or Extended Identifier */
+
+/******************* Bit definition for CAN_TDT2R register ******************/
+#define CAN_TDT2R_DLC 0x0000000FU /*!<Data Length Code */
+#define CAN_TDT2R_TGT 0x00000100U /*!<Transmit Global Time */
+#define CAN_TDT2R_TIME 0xFFFF0000U /*!<Message Time Stamp */
+
+/******************* Bit definition for CAN_TDL2R register ******************/
+#define CAN_TDL2R_DATA0 0x000000FFU /*!<Data byte 0 */
+#define CAN_TDL2R_DATA1 0x0000FF00U /*!<Data byte 1 */
+#define CAN_TDL2R_DATA2 0x00FF0000U /*!<Data byte 2 */
+#define CAN_TDL2R_DATA3 0xFF000000U /*!<Data byte 3 */
+
+/******************* Bit definition for CAN_TDH2R register ******************/
+#define CAN_TDH2R_DATA4 0x000000FFU /*!<Data byte 4 */
+#define CAN_TDH2R_DATA5 0x0000FF00U /*!<Data byte 5 */
+#define CAN_TDH2R_DATA6 0x00FF0000U /*!<Data byte 6 */
+#define CAN_TDH2R_DATA7 0xFF000000U /*!<Data byte 7 */
+
+/******************* Bit definition for CAN_RI0R register *******************/
+#define CAN_RI0R_RTR 0x00000002U /*!<Remote Transmission Request */
+#define CAN_RI0R_IDE 0x00000004U /*!<Identifier Extension */
+#define CAN_RI0R_EXID 0x001FFFF8U /*!<Extended Identifier */
+#define CAN_RI0R_STID 0xFFE00000U /*!<Standard Identifier or Extended Identifier */
+
+/******************* Bit definition for CAN_RDT0R register ******************/
+#define CAN_RDT0R_DLC 0x0000000FU /*!<Data Length Code */
+#define CAN_RDT0R_FMI 0x0000FF00U /*!<Filter Match Index */
+#define CAN_RDT0R_TIME 0xFFFF0000U /*!<Message Time Stamp */
+
+/******************* Bit definition for CAN_RDL0R register ******************/
+#define CAN_RDL0R_DATA0 0x000000FFU /*!<Data byte 0 */
+#define CAN_RDL0R_DATA1 0x0000FF00U /*!<Data byte 1 */
+#define CAN_RDL0R_DATA2 0x00FF0000U /*!<Data byte 2 */
+#define CAN_RDL0R_DATA3 0xFF000000U /*!<Data byte 3 */
+
+/******************* Bit definition for CAN_RDH0R register ******************/
+#define CAN_RDH0R_DATA4 0x000000FFU /*!<Data byte 4 */
+#define CAN_RDH0R_DATA5 0x0000FF00U /*!<Data byte 5 */
+#define CAN_RDH0R_DATA6 0x00FF0000U /*!<Data byte 6 */
+#define CAN_RDH0R_DATA7 0xFF000000U /*!<Data byte 7 */
+
+/******************* Bit definition for CAN_RI1R register *******************/
+#define CAN_RI1R_RTR 0x00000002U /*!<Remote Transmission Request */
+#define CAN_RI1R_IDE 0x00000004U /*!<Identifier Extension */
+#define CAN_RI1R_EXID 0x001FFFF8U /*!<Extended identifier */
+#define CAN_RI1R_STID 0xFFE00000U /*!<Standard Identifier or Extended Identifier */
+
+/******************* Bit definition for CAN_RDT1R register ******************/
+#define CAN_RDT1R_DLC 0x0000000FU /*!<Data Length Code */
+#define CAN_RDT1R_FMI 0x0000FF00U /*!<Filter Match Index */
+#define CAN_RDT1R_TIME 0xFFFF0000U /*!<Message Time Stamp */
+
+/******************* Bit definition for CAN_RDL1R register ******************/
+#define CAN_RDL1R_DATA0 0x000000FFU /*!<Data byte 0 */
+#define CAN_RDL1R_DATA1 0x0000FF00U /*!<Data byte 1 */
+#define CAN_RDL1R_DATA2 0x00FF0000U /*!<Data byte 2 */
+#define CAN_RDL1R_DATA3 0xFF000000U /*!<Data byte 3 */
+
+/******************* Bit definition for CAN_RDH1R register ******************/
+#define CAN_RDH1R_DATA4 0x000000FFU /*!<Data byte 4 */
+#define CAN_RDH1R_DATA5 0x0000FF00U /*!<Data byte 5 */
+#define CAN_RDH1R_DATA6 0x00FF0000U /*!<Data byte 6 */
+#define CAN_RDH1R_DATA7 0xFF000000U /*!<Data byte 7 */
+
+/*!<CAN filter registers */
+/******************* Bit definition for CAN_FMR register ********************/
+#define CAN_FMR_FINIT 0x01U /*!<Filter Init Mode */
+#define CAN_FMR_CAN2SB 0x00003F00U /*!<CAN2 start bank */
+
+/******************* Bit definition for CAN_FM1R register *******************/
+#define CAN_FM1R_FBM 0x0FFFFFFFU /*!<Filter Mode */
+#define CAN_FM1R_FBM0 0x00000001U /*!<Filter Init Mode bit 0 */
+#define CAN_FM1R_FBM1 0x00000002U /*!<Filter Init Mode bit 1 */
+#define CAN_FM1R_FBM2 0x00000004U /*!<Filter Init Mode bit 2 */
+#define CAN_FM1R_FBM3 0x00000008U /*!<Filter Init Mode bit 3 */
+#define CAN_FM1R_FBM4 0x00000010U /*!<Filter Init Mode bit 4 */
+#define CAN_FM1R_FBM5 0x00000020U /*!<Filter Init Mode bit 5 */
+#define CAN_FM1R_FBM6 0x00000040U /*!<Filter Init Mode bit 6 */
+#define CAN_FM1R_FBM7 0x00000080U /*!<Filter Init Mode bit 7 */
+#define CAN_FM1R_FBM8 0x00000100U /*!<Filter Init Mode bit 8 */
+#define CAN_FM1R_FBM9 0x00000200U /*!<Filter Init Mode bit 9 */
+#define CAN_FM1R_FBM10 0x00000400U /*!<Filter Init Mode bit 10 */
+#define CAN_FM1R_FBM11 0x00000800U /*!<Filter Init Mode bit 11 */
+#define CAN_FM1R_FBM12 0x00001000U /*!<Filter Init Mode bit 12 */
+#define CAN_FM1R_FBM13 0x00002000U /*!<Filter Init Mode bit 13 */
+#define CAN_FM1R_FBM14 0x00004000U /*!<Filter Init Mode bit 14 */
+#define CAN_FM1R_FBM15 0x00008000U /*!<Filter Init Mode bit 15 */
+#define CAN_FM1R_FBM16 0x00010000U /*!<Filter Init Mode bit 16 */
+#define CAN_FM1R_FBM17 0x00020000U /*!<Filter Init Mode bit 17 */
+#define CAN_FM1R_FBM18 0x00040000U /*!<Filter Init Mode bit 18 */
+#define CAN_FM1R_FBM19 0x00080000U /*!<Filter Init Mode bit 19 */
+#define CAN_FM1R_FBM20 0x00100000U /*!<Filter Init Mode bit 20 */
+#define CAN_FM1R_FBM21 0x00200000U /*!<Filter Init Mode bit 21 */
+#define CAN_FM1R_FBM22 0x00400000U /*!<Filter Init Mode bit 22 */
+#define CAN_FM1R_FBM23 0x00800000U /*!<Filter Init Mode bit 23 */
+#define CAN_FM1R_FBM24 0x01000000U /*!<Filter Init Mode bit 24 */
+#define CAN_FM1R_FBM25 0x02000000U /*!<Filter Init Mode bit 25 */
+#define CAN_FM1R_FBM26 0x04000000U /*!<Filter Init Mode bit 26 */
+#define CAN_FM1R_FBM27 0x08000000U /*!<Filter Init Mode bit 27 */
+
+/******************* Bit definition for CAN_FS1R register *******************/
+#define CAN_FS1R_FSC 0x0FFFFFFFU /*!<Filter Scale Configuration */
+#define CAN_FS1R_FSC0 0x00000001U /*!<Filter Scale Configuration bit 0 */
+#define CAN_FS1R_FSC1 0x00000002U /*!<Filter Scale Configuration bit 1 */
+#define CAN_FS1R_FSC2 0x00000004U /*!<Filter Scale Configuration bit 2 */
+#define CAN_FS1R_FSC3 0x00000008U /*!<Filter Scale Configuration bit 3 */
+#define CAN_FS1R_FSC4 0x00000010U /*!<Filter Scale Configuration bit 4 */
+#define CAN_FS1R_FSC5 0x00000020U /*!<Filter Scale Configuration bit 5 */
+#define CAN_FS1R_FSC6 0x00000040U /*!<Filter Scale Configuration bit 6 */
+#define CAN_FS1R_FSC7 0x00000080U /*!<Filter Scale Configuration bit 7 */
+#define CAN_FS1R_FSC8 0x00000100U /*!<Filter Scale Configuration bit 8 */
+#define CAN_FS1R_FSC9 0x00000200U /*!<Filter Scale Configuration bit 9 */
+#define CAN_FS1R_FSC10 0x00000400U /*!<Filter Scale Configuration bit 10 */
+#define CAN_FS1R_FSC11 0x00000800U /*!<Filter Scale Configuration bit 11 */
+#define CAN_FS1R_FSC12 0x00001000U /*!<Filter Scale Configuration bit 12 */
+#define CAN_FS1R_FSC13 0x00002000U /*!<Filter Scale Configuration bit 13 */
+#define CAN_FS1R_FSC14 0x00004000U /*!<Filter Scale Configuration bit 14 */
+#define CAN_FS1R_FSC15 0x00008000U /*!<Filter Scale Configuration bit 15 */
+#define CAN_FS1R_FSC16 0x00010000U /*!<Filter Scale Configuration bit 16 */
+#define CAN_FS1R_FSC17 0x00020000U /*!<Filter Scale Configuration bit 17 */
+#define CAN_FS1R_FSC18 0x00040000U /*!<Filter Scale Configuration bit 18 */
+#define CAN_FS1R_FSC19 0x00080000U /*!<Filter Scale Configuration bit 19 */
+#define CAN_FS1R_FSC20 0x00100000U /*!<Filter Scale Configuration bit 20 */
+#define CAN_FS1R_FSC21 0x00200000U /*!<Filter Scale Configuration bit 21 */
+#define CAN_FS1R_FSC22 0x00400000U /*!<Filter Scale Configuration bit 22 */
+#define CAN_FS1R_FSC23 0x00800000U /*!<Filter Scale Configuration bit 23 */
+#define CAN_FS1R_FSC24 0x01000000U /*!<Filter Scale Configuration bit 24 */
+#define CAN_FS1R_FSC25 0x02000000U /*!<Filter Scale Configuration bit 25 */
+#define CAN_FS1R_FSC26 0x04000000U /*!<Filter Scale Configuration bit 26 */
+#define CAN_FS1R_FSC27 0x08000000U /*!<Filter Scale Configuration bit 27 */
+
+/****************** Bit definition for CAN_FFA1R register *******************/
+#define CAN_FFA1R_FFA 0x0FFFFFFFU /*!<Filter FIFO Assignment */
+#define CAN_FFA1R_FFA0 0x00000001U /*!<Filter FIFO Assignment bit 0 */
+#define CAN_FFA1R_FFA1 0x00000002U /*!<Filter FIFO Assignment bit 1 */
+#define CAN_FFA1R_FFA2 0x00000004U /*!<Filter FIFO Assignment bit 2 */
+#define CAN_FFA1R_FFA3 0x00000008U /*!<Filter FIFO Assignment bit 3 */
+#define CAN_FFA1R_FFA4 0x00000010U /*!<Filter FIFO Assignment bit 4 */
+#define CAN_FFA1R_FFA5 0x00000020U /*!<Filter FIFO Assignment bit 5 */
+#define CAN_FFA1R_FFA6 0x00000040U /*!<Filter FIFO Assignment bit 6 */
+#define CAN_FFA1R_FFA7 0x00000080U /*!<Filter FIFO Assignment bit 7 */
+#define CAN_FFA1R_FFA8 0x00000100U /*!<Filter FIFO Assignment bit 8 */
+#define CAN_FFA1R_FFA9 0x00000200U /*!<Filter FIFO Assignment bit 9 */
+#define CAN_FFA1R_FFA10 0x00000400U /*!<Filter FIFO Assignment bit 10 */
+#define CAN_FFA1R_FFA11 0x00000800U /*!<Filter FIFO Assignment bit 11 */
+#define CAN_FFA1R_FFA12 0x00001000U /*!<Filter FIFO Assignment bit 12 */
+#define CAN_FFA1R_FFA13 0x00002000U /*!<Filter FIFO Assignment bit 13 */
+#define CAN_FFA1R_FFA14 0x00004000U /*!<Filter FIFO Assignment bit 14 */
+#define CAN_FFA1R_FFA15 0x00008000U /*!<Filter FIFO Assignment bit 15 */
+#define CAN_FFA1R_FFA16 0x00010000U /*!<Filter FIFO Assignment bit 16 */
+#define CAN_FFA1R_FFA17 0x00020000U /*!<Filter FIFO Assignment bit 17 */
+#define CAN_FFA1R_FFA18 0x00040000U /*!<Filter FIFO Assignment bit 18 */
+#define CAN_FFA1R_FFA19 0x00080000U /*!<Filter FIFO Assignment bit 19 */
+#define CAN_FFA1R_FFA20 0x00100000U /*!<Filter FIFO Assignment bit 20 */
+#define CAN_FFA1R_FFA21 0x00200000U /*!<Filter FIFO Assignment bit 21 */
+#define CAN_FFA1R_FFA22 0x00400000U /*!<Filter FIFO Assignment bit 22 */
+#define CAN_FFA1R_FFA23 0x00800000U /*!<Filter FIFO Assignment bit 23 */
+#define CAN_FFA1R_FFA24 0x01000000U /*!<Filter FIFO Assignment bit 24 */
+#define CAN_FFA1R_FFA25 0x02000000U /*!<Filter FIFO Assignment bit 25 */
+#define CAN_FFA1R_FFA26 0x04000000U /*!<Filter FIFO Assignment bit 26 */
+#define CAN_FFA1R_FFA27 0x08000000U /*!<Filter FIFO Assignment bit 27 */
+
+/******************* Bit definition for CAN_FA1R register *******************/
+#define CAN_FA1R_FACT 0x0FFFFFFFU /*!<Filter Active */
+#define CAN_FA1R_FACT0 0x00000001U /*!<Filter Active bit 0 */
+#define CAN_FA1R_FACT1 0x00000002U /*!<Filter Active bit 1 */
+#define CAN_FA1R_FACT2 0x00000004U /*!<Filter Active bit 2 */
+#define CAN_FA1R_FACT3 0x00000008U /*!<Filter Active bit 3 */
+#define CAN_FA1R_FACT4 0x00000010U /*!<Filter Active bit 4 */
+#define CAN_FA1R_FACT5 0x00000020U /*!<Filter Active bit 5 */
+#define CAN_FA1R_FACT6 0x00000040U /*!<Filter Active bit 6 */
+#define CAN_FA1R_FACT7 0x00000080U /*!<Filter Active bit 7 */
+#define CAN_FA1R_FACT8 0x00000100U /*!<Filter Active bit 8 */
+#define CAN_FA1R_FACT9 0x00000200U /*!<Filter Active bit 9 */
+#define CAN_FA1R_FACT10 0x00000400U /*!<Filter Active bit 10 */
+#define CAN_FA1R_FACT11 0x00000800U /*!<Filter Active bit 11 */
+#define CAN_FA1R_FACT12 0x00001000U /*!<Filter Active bit 12 */
+#define CAN_FA1R_FACT13 0x00002000U /*!<Filter Active bit 13 */
+#define CAN_FA1R_FACT14 0x00004000U /*!<Filter Active bit 14 */
+#define CAN_FA1R_FACT15 0x00008000U /*!<Filter Active bit 15 */
+#define CAN_FA1R_FACT16 0x00010000U /*!<Filter Active bit 16 */
+#define CAN_FA1R_FACT17 0x00020000U /*!<Filter Active bit 17 */
+#define CAN_FA1R_FACT18 0x00040000U /*!<Filter Active bit 18 */
+#define CAN_FA1R_FACT19 0x00080000U /*!<Filter Active bit 19 */
+#define CAN_FA1R_FACT20 0x00100000U /*!<Filter Active bit 20 */
+#define CAN_FA1R_FACT21 0x00200000U /*!<Filter Active bit 21 */
+#define CAN_FA1R_FACT22 0x00400000U /*!<Filter Active bit 22 */
+#define CAN_FA1R_FACT23 0x00800000U /*!<Filter Active bit 23 */
+#define CAN_FA1R_FACT24 0x01000000U /*!<Filter Active bit 24 */
+#define CAN_FA1R_FACT25 0x02000000U /*!<Filter Active bit 25 */
+#define CAN_FA1R_FACT26 0x04000000U /*!<Filter Active bit 26 */
+#define CAN_FA1R_FACT27 0x08000000U /*!<Filter Active bit 27 */
+
+/******************* Bit definition for CAN_F0R1 register *******************/
+#define CAN_F0R1_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F0R1_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F0R1_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F0R1_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F0R1_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F0R1_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F0R1_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F0R1_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F0R1_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F0R1_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F0R1_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F0R1_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F0R1_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F0R1_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F0R1_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F0R1_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F0R1_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F0R1_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F0R1_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F0R1_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F0R1_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F0R1_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F0R1_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F0R1_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F0R1_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F0R1_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F0R1_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F0R1_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F0R1_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F0R1_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F0R1_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F0R1_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F1R1 register *******************/
+#define CAN_F1R1_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F1R1_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F1R1_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F1R1_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F1R1_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F1R1_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F1R1_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F1R1_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F1R1_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F1R1_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F1R1_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F1R1_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F1R1_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F1R1_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F1R1_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F1R1_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F1R1_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F1R1_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F1R1_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F1R1_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F1R1_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F1R1_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F1R1_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F1R1_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F1R1_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F1R1_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F1R1_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F1R1_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F1R1_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F1R1_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F1R1_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F1R1_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F2R1 register *******************/
+#define CAN_F2R1_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F2R1_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F2R1_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F2R1_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F2R1_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F2R1_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F2R1_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F2R1_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F2R1_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F2R1_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F2R1_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F2R1_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F2R1_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F2R1_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F2R1_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F2R1_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F2R1_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F2R1_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F2R1_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F2R1_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F2R1_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F2R1_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F2R1_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F2R1_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F2R1_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F2R1_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F2R1_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F2R1_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F2R1_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F2R1_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F2R1_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F2R1_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F3R1 register *******************/
+#define CAN_F3R1_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F3R1_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F3R1_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F3R1_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F3R1_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F3R1_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F3R1_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F3R1_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F3R1_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F3R1_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F3R1_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F3R1_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F3R1_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F3R1_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F3R1_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F3R1_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F3R1_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F3R1_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F3R1_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F3R1_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F3R1_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F3R1_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F3R1_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F3R1_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F3R1_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F3R1_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F3R1_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F3R1_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F3R1_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F3R1_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F3R1_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F3R1_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F4R1 register *******************/
+#define CAN_F4R1_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F4R1_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F4R1_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F4R1_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F4R1_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F4R1_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F4R1_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F4R1_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F4R1_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F4R1_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F4R1_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F4R1_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F4R1_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F4R1_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F4R1_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F4R1_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F4R1_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F4R1_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F4R1_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F4R1_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F4R1_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F4R1_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F4R1_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F4R1_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F4R1_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F4R1_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F4R1_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F4R1_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F4R1_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F4R1_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F4R1_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F4R1_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F5R1 register *******************/
+#define CAN_F5R1_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F5R1_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F5R1_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F5R1_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F5R1_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F5R1_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F5R1_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F5R1_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F5R1_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F5R1_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F5R1_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F5R1_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F5R1_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F5R1_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F5R1_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F5R1_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F5R1_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F5R1_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F5R1_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F5R1_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F5R1_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F5R1_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F5R1_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F5R1_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F5R1_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F5R1_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F5R1_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F5R1_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F5R1_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F5R1_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F5R1_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F5R1_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F6R1 register *******************/
+#define CAN_F6R1_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F6R1_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F6R1_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F6R1_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F6R1_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F6R1_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F6R1_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F6R1_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F6R1_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F6R1_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F6R1_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F6R1_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F6R1_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F6R1_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F6R1_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F6R1_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F6R1_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F6R1_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F6R1_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F6R1_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F6R1_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F6R1_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F6R1_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F6R1_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F6R1_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F6R1_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F6R1_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F6R1_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F6R1_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F6R1_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F6R1_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F6R1_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F7R1 register *******************/
+#define CAN_F7R1_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F7R1_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F7R1_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F7R1_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F7R1_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F7R1_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F7R1_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F7R1_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F7R1_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F7R1_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F7R1_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F7R1_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F7R1_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F7R1_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F7R1_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F7R1_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F7R1_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F7R1_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F7R1_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F7R1_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F7R1_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F7R1_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F7R1_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F7R1_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F7R1_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F7R1_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F7R1_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F7R1_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F7R1_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F7R1_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F7R1_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F7R1_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F8R1 register *******************/
+#define CAN_F8R1_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F8R1_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F8R1_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F8R1_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F8R1_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F8R1_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F8R1_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F8R1_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F8R1_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F8R1_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F8R1_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F8R1_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F8R1_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F8R1_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F8R1_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F8R1_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F8R1_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F8R1_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F8R1_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F8R1_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F8R1_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F8R1_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F8R1_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F8R1_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F8R1_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F8R1_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F8R1_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F8R1_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F8R1_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F8R1_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F8R1_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F8R1_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F9R1 register *******************/
+#define CAN_F9R1_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F9R1_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F9R1_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F9R1_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F9R1_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F9R1_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F9R1_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F9R1_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F9R1_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F9R1_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F9R1_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F9R1_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F9R1_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F9R1_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F9R1_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F9R1_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F9R1_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F9R1_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F9R1_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F9R1_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F9R1_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F9R1_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F9R1_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F9R1_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F9R1_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F9R1_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F9R1_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F9R1_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F9R1_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F9R1_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F9R1_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F9R1_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F10R1 register ******************/
+#define CAN_F10R1_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F10R1_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F10R1_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F10R1_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F10R1_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F10R1_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F10R1_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F10R1_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F10R1_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F10R1_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F10R1_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F10R1_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F10R1_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F10R1_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F10R1_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F10R1_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F10R1_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F10R1_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F10R1_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F10R1_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F10R1_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F10R1_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F10R1_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F10R1_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F10R1_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F10R1_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F10R1_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F10R1_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F10R1_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F10R1_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F10R1_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F10R1_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F11R1 register ******************/
+#define CAN_F11R1_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F11R1_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F11R1_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F11R1_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F11R1_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F11R1_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F11R1_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F11R1_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F11R1_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F11R1_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F11R1_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F11R1_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F11R1_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F11R1_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F11R1_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F11R1_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F11R1_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F11R1_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F11R1_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F11R1_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F11R1_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F11R1_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F11R1_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F11R1_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F11R1_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F11R1_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F11R1_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F11R1_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F11R1_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F11R1_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F11R1_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F11R1_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F12R1 register ******************/
+#define CAN_F12R1_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F12R1_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F12R1_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F12R1_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F12R1_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F12R1_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F12R1_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F12R1_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F12R1_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F12R1_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F12R1_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F12R1_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F12R1_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F12R1_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F12R1_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F12R1_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F12R1_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F12R1_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F12R1_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F12R1_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F12R1_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F12R1_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F12R1_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F12R1_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F12R1_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F12R1_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F12R1_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F12R1_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F12R1_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F12R1_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F12R1_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F12R1_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F13R1 register ******************/
+#define CAN_F13R1_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F13R1_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F13R1_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F13R1_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F13R1_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F13R1_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F13R1_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F13R1_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F13R1_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F13R1_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F13R1_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F13R1_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F13R1_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F13R1_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F13R1_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F13R1_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F13R1_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F13R1_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F13R1_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F13R1_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F13R1_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F13R1_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F13R1_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F13R1_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F13R1_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F13R1_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F13R1_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F13R1_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F13R1_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F13R1_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F13R1_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F13R1_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F0R2 register *******************/
+#define CAN_F0R2_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F0R2_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F0R2_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F0R2_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F0R2_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F0R2_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F0R2_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F0R2_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F0R2_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F0R2_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F0R2_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F0R2_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F0R2_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F0R2_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F0R2_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F0R2_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F0R2_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F0R2_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F0R2_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F0R2_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F0R2_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F0R2_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F0R2_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F0R2_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F0R2_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F0R2_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F0R2_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F0R2_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F0R2_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F0R2_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F0R2_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F0R2_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F1R2 register *******************/
+#define CAN_F1R2_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F1R2_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F1R2_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F1R2_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F1R2_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F1R2_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F1R2_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F1R2_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F1R2_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F1R2_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F1R2_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F1R2_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F1R2_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F1R2_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F1R2_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F1R2_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F1R2_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F1R2_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F1R2_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F1R2_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F1R2_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F1R2_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F1R2_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F1R2_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F1R2_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F1R2_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F1R2_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F1R2_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F1R2_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F1R2_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F1R2_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F1R2_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F2R2 register *******************/
+#define CAN_F2R2_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F2R2_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F2R2_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F2R2_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F2R2_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F2R2_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F2R2_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F2R2_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F2R2_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F2R2_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F2R2_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F2R2_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F2R2_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F2R2_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F2R2_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F2R2_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F2R2_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F2R2_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F2R2_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F2R2_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F2R2_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F2R2_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F2R2_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F2R2_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F2R2_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F2R2_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F2R2_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F2R2_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F2R2_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F2R2_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F2R2_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F2R2_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F3R2 register *******************/
+#define CAN_F3R2_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F3R2_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F3R2_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F3R2_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F3R2_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F3R2_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F3R2_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F3R2_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F3R2_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F3R2_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F3R2_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F3R2_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F3R2_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F3R2_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F3R2_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F3R2_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F3R2_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F3R2_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F3R2_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F3R2_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F3R2_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F3R2_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F3R2_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F3R2_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F3R2_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F3R2_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F3R2_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F3R2_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F3R2_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F3R2_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F3R2_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F3R2_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F4R2 register *******************/
+#define CAN_F4R2_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F4R2_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F4R2_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F4R2_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F4R2_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F4R2_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F4R2_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F4R2_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F4R2_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F4R2_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F4R2_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F4R2_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F4R2_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F4R2_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F4R2_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F4R2_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F4R2_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F4R2_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F4R2_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F4R2_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F4R2_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F4R2_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F4R2_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F4R2_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F4R2_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F4R2_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F4R2_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F4R2_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F4R2_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F4R2_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F4R2_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F4R2_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F5R2 register *******************/
+#define CAN_F5R2_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F5R2_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F5R2_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F5R2_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F5R2_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F5R2_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F5R2_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F5R2_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F5R2_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F5R2_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F5R2_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F5R2_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F5R2_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F5R2_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F5R2_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F5R2_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F5R2_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F5R2_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F5R2_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F5R2_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F5R2_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F5R2_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F5R2_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F5R2_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F5R2_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F5R2_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F5R2_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F5R2_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F5R2_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F5R2_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F5R2_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F5R2_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F6R2 register *******************/
+#define CAN_F6R2_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F6R2_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F6R2_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F6R2_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F6R2_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F6R2_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F6R2_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F6R2_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F6R2_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F6R2_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F6R2_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F6R2_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F6R2_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F6R2_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F6R2_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F6R2_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F6R2_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F6R2_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F6R2_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F6R2_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F6R2_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F6R2_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F6R2_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F6R2_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F6R2_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F6R2_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F6R2_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F6R2_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F6R2_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F6R2_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F6R2_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F6R2_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F7R2 register *******************/
+#define CAN_F7R2_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F7R2_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F7R2_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F7R2_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F7R2_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F7R2_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F7R2_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F7R2_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F7R2_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F7R2_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F7R2_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F7R2_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F7R2_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F7R2_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F7R2_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F7R2_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F7R2_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F7R2_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F7R2_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F7R2_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F7R2_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F7R2_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F7R2_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F7R2_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F7R2_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F7R2_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F7R2_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F7R2_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F7R2_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F7R2_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F7R2_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F7R2_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F8R2 register *******************/
+#define CAN_F8R2_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F8R2_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F8R2_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F8R2_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F8R2_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F8R2_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F8R2_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F8R2_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F8R2_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F8R2_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F8R2_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F8R2_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F8R2_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F8R2_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F8R2_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F8R2_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F8R2_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F8R2_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F8R2_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F8R2_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F8R2_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F8R2_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F8R2_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F8R2_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F8R2_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F8R2_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F8R2_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F8R2_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F8R2_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F8R2_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F8R2_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F8R2_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F9R2 register *******************/
+#define CAN_F9R2_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F9R2_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F9R2_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F9R2_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F9R2_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F9R2_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F9R2_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F9R2_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F9R2_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F9R2_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F9R2_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F9R2_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F9R2_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F9R2_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F9R2_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F9R2_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F9R2_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F9R2_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F9R2_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F9R2_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F9R2_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F9R2_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F9R2_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F9R2_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F9R2_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F9R2_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F9R2_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F9R2_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F9R2_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F9R2_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F9R2_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F9R2_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F10R2 register ******************/
+#define CAN_F10R2_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F10R2_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F10R2_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F10R2_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F10R2_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F10R2_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F10R2_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F10R2_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F10R2_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F10R2_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F10R2_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F10R2_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F10R2_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F10R2_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F10R2_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F10R2_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F10R2_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F10R2_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F10R2_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F10R2_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F10R2_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F10R2_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F10R2_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F10R2_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F10R2_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F10R2_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F10R2_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F10R2_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F10R2_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F10R2_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F10R2_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F10R2_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F11R2 register ******************/
+#define CAN_F11R2_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F11R2_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F11R2_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F11R2_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F11R2_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F11R2_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F11R2_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F11R2_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F11R2_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F11R2_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F11R2_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F11R2_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F11R2_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F11R2_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F11R2_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F11R2_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F11R2_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F11R2_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F11R2_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F11R2_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F11R2_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F11R2_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F11R2_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F11R2_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F11R2_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F11R2_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F11R2_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F11R2_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F11R2_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F11R2_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F11R2_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F11R2_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F12R2 register ******************/
+#define CAN_F12R2_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F12R2_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F12R2_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F12R2_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F12R2_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F12R2_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F12R2_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F12R2_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F12R2_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F12R2_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F12R2_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F12R2_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F12R2_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F12R2_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F12R2_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F12R2_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F12R2_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F12R2_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F12R2_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F12R2_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F12R2_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F12R2_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F12R2_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F12R2_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F12R2_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F12R2_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F12R2_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F12R2_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F12R2_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F12R2_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F12R2_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F12R2_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F13R2 register ******************/
+#define CAN_F13R2_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F13R2_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F13R2_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F13R2_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F13R2_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F13R2_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F13R2_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F13R2_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F13R2_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F13R2_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F13R2_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F13R2_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F13R2_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F13R2_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F13R2_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F13R2_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F13R2_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F13R2_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F13R2_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F13R2_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F13R2_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F13R2_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F13R2_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F13R2_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F13R2_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F13R2_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F13R2_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F13R2_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F13R2_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F13R2_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F13R2_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F13R2_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************************************************************************/
+/* */
+/* CRC calculation unit */
+/* */
+/******************************************************************************/
+/******************* Bit definition for CRC_DR register *********************/
+#define CRC_DR_DR 0xFFFFFFFFU /*!< Data register bits */
+
+
+/******************* Bit definition for CRC_IDR register ********************/
+#define CRC_IDR_IDR 0xFFU /*!< General-purpose 8-bit data register bits */
+
+
+/******************** Bit definition for CRC_CR register ********************/
+#define CRC_CR_RESET 0x01U /*!< RESET bit */
+
+/******************************************************************************/
+/* */
+/* Digital to Analog Converter */
+/* */
+/******************************************************************************/
+/******************** Bit definition for DAC_CR register ********************/
+#define DAC_CR_EN1 0x00000001U /*!<DAC channel1 enable */
+#define DAC_CR_BOFF1 0x00000002U /*!<DAC channel1 output buffer disable */
+#define DAC_CR_TEN1 0x00000004U /*!<DAC channel1 Trigger enable */
+
+#define DAC_CR_TSEL1 0x00000038U /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */
+#define DAC_CR_TSEL1_0 0x00000008U /*!<Bit 0 */
+#define DAC_CR_TSEL1_1 0x00000010U /*!<Bit 1 */
+#define DAC_CR_TSEL1_2 0x00000020U /*!<Bit 2 */
+
+#define DAC_CR_WAVE1 0x000000C0U /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
+#define DAC_CR_WAVE1_0 0x00000040U /*!<Bit 0 */
+#define DAC_CR_WAVE1_1 0x00000080U /*!<Bit 1 */
+
+#define DAC_CR_MAMP1 0x00000F00U /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
+#define DAC_CR_MAMP1_0 0x00000100U /*!<Bit 0 */
+#define DAC_CR_MAMP1_1 0x00000200U /*!<Bit 1 */
+#define DAC_CR_MAMP1_2 0x00000400U /*!<Bit 2 */
+#define DAC_CR_MAMP1_3 0x00000800U /*!<Bit 3 */
+
+#define DAC_CR_DMAEN1 0x00001000U /*!<DAC channel1 DMA enable */
+#define DAC_CR_DMAUDRIE1 0x00002000U /*!<DAC channel1 DMA underrun interrupt enable*/
+#define DAC_CR_EN2 0x00010000U /*!<DAC channel2 enable */
+#define DAC_CR_BOFF2 0x00020000U /*!<DAC channel2 output buffer disable */
+#define DAC_CR_TEN2 0x00040000U /*!<DAC channel2 Trigger enable */
+
+#define DAC_CR_TSEL2 0x00380000U /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */
+#define DAC_CR_TSEL2_0 0x00080000U /*!<Bit 0 */
+#define DAC_CR_TSEL2_1 0x00100000U /*!<Bit 1 */
+#define DAC_CR_TSEL2_2 0x00200000U /*!<Bit 2 */
+
+#define DAC_CR_WAVE2 0x00C00000U /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
+#define DAC_CR_WAVE2_0 0x00400000U /*!<Bit 0 */
+#define DAC_CR_WAVE2_1 0x00800000U /*!<Bit 1 */
+
+#define DAC_CR_MAMP2 0x0F000000U /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
+#define DAC_CR_MAMP2_0 0x01000000U /*!<Bit 0 */
+#define DAC_CR_MAMP2_1 0x02000000U /*!<Bit 1 */
+#define DAC_CR_MAMP2_2 0x04000000U /*!<Bit 2 */
+#define DAC_CR_MAMP2_3 0x08000000U /*!<Bit 3 */
+
+#define DAC_CR_DMAEN2 0x10000000U /*!<DAC channel2 DMA enabled */
+#define DAC_CR_DMAUDRIE2 0x20000000U /*!<DAC channel2 DMA underrun interrupt enable*/
+
+/***************** Bit definition for DAC_SWTRIGR register ******************/
+#define DAC_SWTRIGR_SWTRIG1 0x01U /*!<DAC channel1 software trigger */
+#define DAC_SWTRIGR_SWTRIG2 0x02U /*!<DAC channel2 software trigger */
+
+/***************** Bit definition for DAC_DHR12R1 register ******************/
+#define DAC_DHR12R1_DACC1DHR 0x0FFFU /*!<DAC channel1 12-bit Right aligned data */
+
+/***************** Bit definition for DAC_DHR12L1 register ******************/
+#define DAC_DHR12L1_DACC1DHR 0xFFF0U /*!<DAC channel1 12-bit Left aligned data */
+
+/****************** Bit definition for DAC_DHR8R1 register ******************/
+#define DAC_DHR8R1_DACC1DHR 0xFFU /*!<DAC channel1 8-bit Right aligned data */
+
+/***************** Bit definition for DAC_DHR12R2 register ******************/
+#define DAC_DHR12R2_DACC2DHR 0x0FFFU /*!<DAC channel2 12-bit Right aligned data */
+
+/***************** Bit definition for DAC_DHR12L2 register ******************/
+#define DAC_DHR12L2_DACC2DHR 0xFFF0U /*!<DAC channel2 12-bit Left aligned data */
+
+/****************** Bit definition for DAC_DHR8R2 register ******************/
+#define DAC_DHR8R2_DACC2DHR 0xFFU /*!<DAC channel2 8-bit Right aligned data */
+
+/***************** Bit definition for DAC_DHR12RD register ******************/
+#define DAC_DHR12RD_DACC1DHR 0x00000FFFU /*!<DAC channel1 12-bit Right aligned data */
+#define DAC_DHR12RD_DACC2DHR 0x0FFF0000U /*!<DAC channel2 12-bit Right aligned data */
+
+/***************** Bit definition for DAC_DHR12LD register ******************/
+#define DAC_DHR12LD_DACC1DHR 0x0000FFF0U /*!<DAC channel1 12-bit Left aligned data */
+#define DAC_DHR12LD_DACC2DHR 0xFFF00000U /*!<DAC channel2 12-bit Left aligned data */
+
+/****************** Bit definition for DAC_DHR8RD register ******************/
+#define DAC_DHR8RD_DACC1DHR 0x00FFU /*!<DAC channel1 8-bit Right aligned data */
+#define DAC_DHR8RD_DACC2DHR 0xFF00U /*!<DAC channel2 8-bit Right aligned data */
+
+/******************* Bit definition for DAC_DOR1 register *******************/
+#define DAC_DOR1_DACC1DOR 0x0FFFU /*!<DAC channel1 data output */
+
+/******************* Bit definition for DAC_DOR2 register *******************/
+#define DAC_DOR2_DACC2DOR 0x0FFFU /*!<DAC channel2 data output */
+
+/******************** Bit definition for DAC_SR register ********************/
+#define DAC_SR_DMAUDR1 0x00002000U /*!<DAC channel1 DMA underrun flag */
+#define DAC_SR_DMAUDR2 0x20000000U /*!<DAC channel2 DMA underrun flag */
+
+/******************************************************************************/
+/* */
+/* Debug MCU */
+/* */
+/******************************************************************************/
+
+/******************************************************************************/
+/* */
+/* DCMI */
+/* */
+/******************************************************************************/
+/******************** Bits definition for DCMI_CR register ******************/
+#define DCMI_CR_CAPTURE 0x00000001U
+#define DCMI_CR_CM 0x00000002U
+#define DCMI_CR_CROP 0x00000004U
+#define DCMI_CR_JPEG 0x00000008U
+#define DCMI_CR_ESS 0x00000010U
+#define DCMI_CR_PCKPOL 0x00000020U
+#define DCMI_CR_HSPOL 0x00000040U
+#define DCMI_CR_VSPOL 0x00000080U
+#define DCMI_CR_FCRC_0 0x00000100U
+#define DCMI_CR_FCRC_1 0x00000200U
+#define DCMI_CR_EDM_0 0x00000400U
+#define DCMI_CR_EDM_1 0x00000800U
+#define DCMI_CR_CRE 0x00001000U
+#define DCMI_CR_ENABLE 0x00004000U
+
+/******************** Bits definition for DCMI_SR register ******************/
+#define DCMI_SR_HSYNC 0x00000001U
+#define DCMI_SR_VSYNC 0x00000002U
+#define DCMI_SR_FNE 0x00000004U
+
+/******************** Bits definition for DCMI_RIS register *****************/
+#define DCMI_RIS_FRAME_RIS 0x00000001U
+#define DCMI_RIS_OVR_RIS 0x00000002U
+#define DCMI_RIS_ERR_RIS 0x00000004U
+#define DCMI_RIS_VSYNC_RIS 0x00000008U
+#define DCMI_RIS_LINE_RIS 0x00000010U
+/* Legacy defines */
+#define DCMI_RISR_FRAME_RIS DCMI_RIS_FRAME_RIS
+#define DCMI_RISR_OVR_RIS DCMI_RIS_OVR_RIS
+#define DCMI_RISR_ERR_RIS DCMI_RIS_ERR_RIS
+#define DCMI_RISR_VSYNC_RIS DCMI_RIS_VSYNC_RIS
+#define DCMI_RISR_LINE_RIS DCMI_RIS_LINE_RIS
+#define DCMI_RISR_OVF_RIS DCMI_RIS_OVR_RIS
+
+/******************** Bits definition for DCMI_IER register *****************/
+#define DCMI_IER_FRAME_IE 0x00000001U
+#define DCMI_IER_OVR_IE 0x00000002U
+#define DCMI_IER_ERR_IE 0x00000004U
+#define DCMI_IER_VSYNC_IE 0x00000008U
+#define DCMI_IER_LINE_IE 0x00000010U
+/* Legacy defines */
+#define DCMI_IER_OVF_IE DCMI_IER_OVR_IE
+
+/******************** Bits definition for DCMI_MIS register *****************/
+#define DCMI_MIS_FRAME_MIS 0x00000001U
+#define DCMI_MIS_OVR_MIS 0x00000002U
+#define DCMI_MIS_ERR_MIS 0x00000004U
+#define DCMI_MIS_VSYNC_MIS 0x00000008U
+#define DCMI_MIS_LINE_MIS 0x00000010U
+
+/* Legacy defines */
+#define DCMI_MISR_FRAME_MIS DCMI_MIS_FRAME_MIS
+#define DCMI_MISR_OVF_MIS DCMI_MIS_OVR_MIS
+#define DCMI_MISR_ERR_MIS DCMI_MIS_ERR_MIS
+#define DCMI_MISR_VSYNC_MIS DCMI_MIS_VSYNC_MIS
+#define DCMI_MISR_LINE_MIS DCMI_MIS_LINE_MIS
+
+/******************** Bits definition for DCMI_ICR register *****************/
+#define DCMI_ICR_FRAME_ISC 0x00000001U
+#define DCMI_ICR_OVR_ISC 0x00000002U
+#define DCMI_ICR_ERR_ISC 0x00000004U
+#define DCMI_ICR_VSYNC_ISC 0x00000008U
+#define DCMI_ICR_LINE_ISC 0x00000010U
+
+/* Legacy defines */
+#define DCMI_ICR_OVF_ISC DCMI_ICR_OVR_ISC
+
+/******************** Bits definition for DCMI_ESCR register ******************/
+#define DCMI_ESCR_FSC 0x000000FFU
+#define DCMI_ESCR_LSC 0x0000FF00U
+#define DCMI_ESCR_LEC 0x00FF0000U
+#define DCMI_ESCR_FEC 0xFF000000U
+
+/******************** Bits definition for DCMI_ESUR register ******************/
+#define DCMI_ESUR_FSU 0x000000FFU
+#define DCMI_ESUR_LSU 0x0000FF00U
+#define DCMI_ESUR_LEU 0x00FF0000U
+#define DCMI_ESUR_FEU 0xFF000000U
+
+/******************** Bits definition for DCMI_CWSTRT register ******************/
+#define DCMI_CWSTRT_HOFFCNT 0x00003FFFU
+#define DCMI_CWSTRT_VST 0x1FFF0000U
+
+/******************** Bits definition for DCMI_CWSIZE register ******************/
+#define DCMI_CWSIZE_CAPCNT 0x00003FFFU
+#define DCMI_CWSIZE_VLINE 0x3FFF0000U
+
+/******************** Bits definition for DCMI_DR register ******************/
+#define DCMI_DR_BYTE0 0x000000FFU
+#define DCMI_DR_BYTE1 0x0000FF00U
+#define DCMI_DR_BYTE2 0x00FF0000U
+#define DCMI_DR_BYTE3 0xFF000000U
+
+/******************************************************************************/
+/* */
+/* DMA Controller */
+/* */
+/******************************************************************************/
+/******************** Bits definition for DMA_SxCR register *****************/
+#define DMA_SxCR_CHSEL 0x0E000000U
+#define DMA_SxCR_CHSEL_0 0x02000000U
+#define DMA_SxCR_CHSEL_1 0x04000000U
+#define DMA_SxCR_CHSEL_2 0x08000000U
+#define DMA_SxCR_MBURST 0x01800000U
+#define DMA_SxCR_MBURST_0 0x00800000U
+#define DMA_SxCR_MBURST_1 0x01000000U
+#define DMA_SxCR_PBURST 0x00600000U
+#define DMA_SxCR_PBURST_0 0x00200000U
+#define DMA_SxCR_PBURST_1 0x00400000U
+#define DMA_SxCR_CT 0x00080000U
+#define DMA_SxCR_DBM 0x00040000U
+#define DMA_SxCR_PL 0x00030000U
+#define DMA_SxCR_PL_0 0x00010000U
+#define DMA_SxCR_PL_1 0x00020000U
+#define DMA_SxCR_PINCOS 0x00008000U
+#define DMA_SxCR_MSIZE 0x00006000U
+#define DMA_SxCR_MSIZE_0 0x00002000U
+#define DMA_SxCR_MSIZE_1 0x00004000U
+#define DMA_SxCR_PSIZE 0x00001800U
+#define DMA_SxCR_PSIZE_0 0x00000800U
+#define DMA_SxCR_PSIZE_1 0x00001000U
+#define DMA_SxCR_MINC 0x00000400U
+#define DMA_SxCR_PINC 0x00000200U
+#define DMA_SxCR_CIRC 0x00000100U
+#define DMA_SxCR_DIR 0x000000C0U
+#define DMA_SxCR_DIR_0 0x00000040U
+#define DMA_SxCR_DIR_1 0x00000080U
+#define DMA_SxCR_PFCTRL 0x00000020U
+#define DMA_SxCR_TCIE 0x00000010U
+#define DMA_SxCR_HTIE 0x00000008U
+#define DMA_SxCR_TEIE 0x00000004U
+#define DMA_SxCR_DMEIE 0x00000002U
+#define DMA_SxCR_EN 0x00000001U
+
+/* Legacy defines */
+#define DMA_SxCR_ACK 0x00100000U
+
+/******************** Bits definition for DMA_SxCNDTR register **************/
+#define DMA_SxNDT 0x0000FFFFU
+#define DMA_SxNDT_0 0x00000001U
+#define DMA_SxNDT_1 0x00000002U
+#define DMA_SxNDT_2 0x00000004U
+#define DMA_SxNDT_3 0x00000008U
+#define DMA_SxNDT_4 0x00000010U
+#define DMA_SxNDT_5 0x00000020U
+#define DMA_SxNDT_6 0x00000040U
+#define DMA_SxNDT_7 0x00000080U
+#define DMA_SxNDT_8 0x00000100U
+#define DMA_SxNDT_9 0x00000200U
+#define DMA_SxNDT_10 0x00000400U
+#define DMA_SxNDT_11 0x00000800U
+#define DMA_SxNDT_12 0x00001000U
+#define DMA_SxNDT_13 0x00002000U
+#define DMA_SxNDT_14 0x00004000U
+#define DMA_SxNDT_15 0x00008000U
+
+/******************** Bits definition for DMA_SxFCR register ****************/
+#define DMA_SxFCR_FEIE 0x00000080U
+#define DMA_SxFCR_FS 0x00000038U
+#define DMA_SxFCR_FS_0 0x00000008U
+#define DMA_SxFCR_FS_1 0x00000010U
+#define DMA_SxFCR_FS_2 0x00000020U
+#define DMA_SxFCR_DMDIS 0x00000004U
+#define DMA_SxFCR_FTH 0x00000003U
+#define DMA_SxFCR_FTH_0 0x00000001U
+#define DMA_SxFCR_FTH_1 0x00000002U
+
+/******************** Bits definition for DMA_LISR register *****************/
+#define DMA_LISR_TCIF3 0x08000000U
+#define DMA_LISR_HTIF3 0x04000000U
+#define DMA_LISR_TEIF3 0x02000000U
+#define DMA_LISR_DMEIF3 0x01000000U
+#define DMA_LISR_FEIF3 0x00400000U
+#define DMA_LISR_TCIF2 0x00200000U
+#define DMA_LISR_HTIF2 0x00100000U
+#define DMA_LISR_TEIF2 0x00080000U
+#define DMA_LISR_DMEIF2 0x00040000U
+#define DMA_LISR_FEIF2 0x00010000U
+#define DMA_LISR_TCIF1 0x00000800U
+#define DMA_LISR_HTIF1 0x00000400U
+#define DMA_LISR_TEIF1 0x00000200U
+#define DMA_LISR_DMEIF1 0x00000100U
+#define DMA_LISR_FEIF1 0x00000040U
+#define DMA_LISR_TCIF0 0x00000020U
+#define DMA_LISR_HTIF0 0x00000010U
+#define DMA_LISR_TEIF0 0x00000008U
+#define DMA_LISR_DMEIF0 0x00000004U
+#define DMA_LISR_FEIF0 0x00000001U
+
+/******************** Bits definition for DMA_HISR register *****************/
+#define DMA_HISR_TCIF7 0x08000000U
+#define DMA_HISR_HTIF7 0x04000000U
+#define DMA_HISR_TEIF7 0x02000000U
+#define DMA_HISR_DMEIF7 0x01000000U
+#define DMA_HISR_FEIF7 0x00400000U
+#define DMA_HISR_TCIF6 0x00200000U
+#define DMA_HISR_HTIF6 0x00100000U
+#define DMA_HISR_TEIF6 0x00080000U
+#define DMA_HISR_DMEIF6 0x00040000U
+#define DMA_HISR_FEIF6 0x00010000U
+#define DMA_HISR_TCIF5 0x00000800U
+#define DMA_HISR_HTIF5 0x00000400U
+#define DMA_HISR_TEIF5 0x00000200U
+#define DMA_HISR_DMEIF5 0x00000100U
+#define DMA_HISR_FEIF5 0x00000040U
+#define DMA_HISR_TCIF4 0x00000020U
+#define DMA_HISR_HTIF4 0x00000010U
+#define DMA_HISR_TEIF4 0x00000008U
+#define DMA_HISR_DMEIF4 0x00000004U
+#define DMA_HISR_FEIF4 0x00000001U
+
+/******************** Bits definition for DMA_LIFCR register ****************/
+#define DMA_LIFCR_CTCIF3 0x08000000U
+#define DMA_LIFCR_CHTIF3 0x04000000U
+#define DMA_LIFCR_CTEIF3 0x02000000U
+#define DMA_LIFCR_CDMEIF3 0x01000000U
+#define DMA_LIFCR_CFEIF3 0x00400000U
+#define DMA_LIFCR_CTCIF2 0x00200000U
+#define DMA_LIFCR_CHTIF2 0x00100000U
+#define DMA_LIFCR_CTEIF2 0x00080000U
+#define DMA_LIFCR_CDMEIF2 0x00040000U
+#define DMA_LIFCR_CFEIF2 0x00010000U
+#define DMA_LIFCR_CTCIF1 0x00000800U
+#define DMA_LIFCR_CHTIF1 0x00000400U
+#define DMA_LIFCR_CTEIF1 0x00000200U
+#define DMA_LIFCR_CDMEIF1 0x00000100U
+#define DMA_LIFCR_CFEIF1 0x00000040U
+#define DMA_LIFCR_CTCIF0 0x00000020U
+#define DMA_LIFCR_CHTIF0 0x00000010U
+#define DMA_LIFCR_CTEIF0 0x00000008U
+#define DMA_LIFCR_CDMEIF0 0x00000004U
+#define DMA_LIFCR_CFEIF0 0x00000001U
+
+/******************** Bits definition for DMA_HIFCR register ****************/
+#define DMA_HIFCR_CTCIF7 0x08000000U
+#define DMA_HIFCR_CHTIF7 0x04000000U
+#define DMA_HIFCR_CTEIF7 0x02000000U
+#define DMA_HIFCR_CDMEIF7 0x01000000U
+#define DMA_HIFCR_CFEIF7 0x00400000U
+#define DMA_HIFCR_CTCIF6 0x00200000U
+#define DMA_HIFCR_CHTIF6 0x00100000U
+#define DMA_HIFCR_CTEIF6 0x00080000U
+#define DMA_HIFCR_CDMEIF6 0x00040000U
+#define DMA_HIFCR_CFEIF6 0x00010000U
+#define DMA_HIFCR_CTCIF5 0x00000800U
+#define DMA_HIFCR_CHTIF5 0x00000400U
+#define DMA_HIFCR_CTEIF5 0x00000200U
+#define DMA_HIFCR_CDMEIF5 0x00000100U
+#define DMA_HIFCR_CFEIF5 0x00000040U
+#define DMA_HIFCR_CTCIF4 0x00000020U
+#define DMA_HIFCR_CHTIF4 0x00000010U
+#define DMA_HIFCR_CTEIF4 0x00000008U
+#define DMA_HIFCR_CDMEIF4 0x00000004U
+#define DMA_HIFCR_CFEIF4 0x00000001U
+
+
+/******************************************************************************/
+/* */
+/* AHB Master DMA2D Controller (DMA2D) */
+/* */
+/******************************************************************************/
+
+/******************** Bit definition for DMA2D_CR register ******************/
+
+#define DMA2D_CR_START 0x00000001U /*!< Start transfer */
+#define DMA2D_CR_SUSP 0x00000002U /*!< Suspend transfer */
+#define DMA2D_CR_ABORT 0x00000004U /*!< Abort transfer */
+#define DMA2D_CR_TEIE 0x00000100U /*!< Transfer Error Interrupt Enable */
+#define DMA2D_CR_TCIE 0x00000200U /*!< Transfer Complete Interrupt Enable */
+#define DMA2D_CR_TWIE 0x00000400U /*!< Transfer Watermark Interrupt Enable */
+#define DMA2D_CR_CAEIE 0x00000800U /*!< CLUT Access Error Interrupt Enable */
+#define DMA2D_CR_CTCIE 0x00001000U /*!< CLUT Transfer Complete Interrupt Enable */
+#define DMA2D_CR_CEIE 0x00002000U /*!< Configuration Error Interrupt Enable */
+#define DMA2D_CR_MODE 0x00030000U /*!< DMA2D Mode[1:0] */
+#define DMA2D_CR_MODE_0 0x00010000U /*!< DMA2D Mode bit 0 */
+#define DMA2D_CR_MODE_1 0x00020000U /*!< DMA2D Mode bit 1 */
+
+/******************** Bit definition for DMA2D_ISR register *****************/
+
+#define DMA2D_ISR_TEIF 0x00000001U /*!< Transfer Error Interrupt Flag */
+#define DMA2D_ISR_TCIF 0x00000002U /*!< Transfer Complete Interrupt Flag */
+#define DMA2D_ISR_TWIF 0x00000004U /*!< Transfer Watermark Interrupt Flag */
+#define DMA2D_ISR_CAEIF 0x00000008U /*!< CLUT Access Error Interrupt Flag */
+#define DMA2D_ISR_CTCIF 0x00000010U /*!< CLUT Transfer Complete Interrupt Flag */
+#define DMA2D_ISR_CEIF 0x00000020U /*!< Configuration Error Interrupt Flag */
+
+/******************** Bit definition for DMA2D_IFCR register ****************/
+
+#define DMA2D_IFCR_CTEIF 0x00000001U /*!< Clears Transfer Error Interrupt Flag */
+#define DMA2D_IFCR_CTCIF 0x00000002U /*!< Clears Transfer Complete Interrupt Flag */
+#define DMA2D_IFCR_CTWIF 0x00000004U /*!< Clears Transfer Watermark Interrupt Flag */
+#define DMA2D_IFCR_CAECIF 0x00000008U /*!< Clears CLUT Access Error Interrupt Flag */
+#define DMA2D_IFCR_CCTCIF 0x00000010U /*!< Clears CLUT Transfer Complete Interrupt Flag */
+#define DMA2D_IFCR_CCEIF 0x00000020U /*!< Clears Configuration Error Interrupt Flag */
+
+/* Legacy defines */
+#define DMA2D_IFSR_CTEIF DMA2D_IFCR_CTEIF /*!< Clears Transfer Error Interrupt Flag */
+#define DMA2D_IFSR_CTCIF DMA2D_IFCR_CTCIF /*!< Clears Transfer Complete Interrupt Flag */
+#define DMA2D_IFSR_CTWIF DMA2D_IFCR_CTWIF /*!< Clears Transfer Watermark Interrupt Flag */
+#define DMA2D_IFSR_CCAEIF DMA2D_IFCR_CAECIF /*!< Clears CLUT Access Error Interrupt Flag */
+#define DMA2D_IFSR_CCTCIF DMA2D_IFCR_CCTCIF /*!< Clears CLUT Transfer Complete Interrupt Flag */
+#define DMA2D_IFSR_CCEIF DMA2D_IFCR_CCEIF /*!< Clears Configuration Error Interrupt Flag */
+
+/******************** Bit definition for DMA2D_FGMAR register ***************/
+
+#define DMA2D_FGMAR_MA 0xFFFFFFFFU /*!< Memory Address */
+
+/******************** Bit definition for DMA2D_FGOR register ****************/
+
+#define DMA2D_FGOR_LO 0x00003FFFU /*!< Line Offset */
+
+/******************** Bit definition for DMA2D_BGMAR register ***************/
+
+#define DMA2D_BGMAR_MA 0xFFFFFFFFU /*!< Memory Address */
+
+/******************** Bit definition for DMA2D_BGOR register ****************/
+
+#define DMA2D_BGOR_LO 0x00003FFFU /*!< Line Offset */
+
+/******************** Bit definition for DMA2D_FGPFCCR register *************/
+
+#define DMA2D_FGPFCCR_CM 0x0000000FU /*!< Input color mode CM[3:0] */
+#define DMA2D_FGPFCCR_CM_0 0x00000001U /*!< Input color mode CM bit 0 */
+#define DMA2D_FGPFCCR_CM_1 0x00000002U /*!< Input color mode CM bit 1 */
+#define DMA2D_FGPFCCR_CM_2 0x00000004U /*!< Input color mode CM bit 2 */
+#define DMA2D_FGPFCCR_CM_3 0x00000008U /*!< Input color mode CM bit 3 */
+#define DMA2D_FGPFCCR_CCM 0x00000010U /*!< CLUT Color mode */
+#define DMA2D_FGPFCCR_START 0x00000020U /*!< Start */
+#define DMA2D_FGPFCCR_CS 0x0000FF00U /*!< CLUT size */
+#define DMA2D_FGPFCCR_AM 0x00030000U /*!< Alpha mode AM[1:0] */
+#define DMA2D_FGPFCCR_AM_0 0x00010000U /*!< Alpha mode AM bit 0 */
+#define DMA2D_FGPFCCR_AM_1 0x00020000U /*!< Alpha mode AM bit 1 */
+#define DMA2D_FGPFCCR_ALPHA 0xFF000000U /*!< Alpha value */
+
+/******************** Bit definition for DMA2D_FGCOLR register **************/
+
+#define DMA2D_FGCOLR_BLUE 0x000000FFU /*!< Blue Value */
+#define DMA2D_FGCOLR_GREEN 0x0000FF00U /*!< Green Value */
+#define DMA2D_FGCOLR_RED 0x00FF0000U /*!< Red Value */
+
+/******************** Bit definition for DMA2D_BGPFCCR register *************/
+
+#define DMA2D_BGPFCCR_CM 0x0000000FU /*!< Input color mode CM[3:0] */
+#define DMA2D_BGPFCCR_CM_0 0x00000001U /*!< Input color mode CM bit 0 */
+#define DMA2D_BGPFCCR_CM_1 0x00000002U /*!< Input color mode CM bit 1 */
+#define DMA2D_BGPFCCR_CM_2 0x00000004U /*!< Input color mode CM bit 2 */
+#define DMA2D_FGPFCCR_CM_3 0x00000008U /*!< Input color mode CM bit 3 */
+#define DMA2D_BGPFCCR_CCM 0x00000010U /*!< CLUT Color mode */
+#define DMA2D_BGPFCCR_START 0x00000020U /*!< Start */
+#define DMA2D_BGPFCCR_CS 0x0000FF00U /*!< CLUT size */
+#define DMA2D_BGPFCCR_AM 0x00030000U /*!< Alpha mode AM[1:0] */
+#define DMA2D_BGPFCCR_AM_0 0x00010000U /*!< Alpha mode AM bit 0 */
+#define DMA2D_BGPFCCR_AM_1 0x00020000U /*!< Alpha mode AM bit 1 */
+#define DMA2D_BGPFCCR_ALPHA 0xFF000000U /*!< background Input Alpha value */
+
+/******************** Bit definition for DMA2D_BGCOLR register **************/
+
+#define DMA2D_BGCOLR_BLUE 0x000000FFU /*!< Blue Value */
+#define DMA2D_BGCOLR_GREEN 0x0000FF00U /*!< Green Value */
+#define DMA2D_BGCOLR_RED 0x00FF0000U /*!< Red Value */
+
+/******************** Bit definition for DMA2D_FGCMAR register **************/
+
+#define DMA2D_FGCMAR_MA 0xFFFFFFFFU /*!< Memory Address */
+
+/******************** Bit definition for DMA2D_BGCMAR register **************/
+
+#define DMA2D_BGCMAR_MA 0xFFFFFFFFU /*!< Memory Address */
+
+/******************** Bit definition for DMA2D_OPFCCR register **************/
+
+#define DMA2D_OPFCCR_CM 0x00000007U /*!< Color mode CM[2:0] */
+#define DMA2D_OPFCCR_CM_0 0x00000001U /*!< Color mode CM bit 0 */
+#define DMA2D_OPFCCR_CM_1 0x00000002U /*!< Color mode CM bit 1 */
+#define DMA2D_OPFCCR_CM_2 0x00000004U /*!< Color mode CM bit 2 */
+
+/******************** Bit definition for DMA2D_OCOLR register ***************/
+
+/*!<Mode_ARGB8888/RGB888 */
+
+#define DMA2D_OCOLR_BLUE_1 0x000000FFU /*!< BLUE Value */
+#define DMA2D_OCOLR_GREEN_1 0x0000FF00U /*!< GREEN Value */
+#define DMA2D_OCOLR_RED_1 0x00FF0000U /*!< Red Value */
+#define DMA2D_OCOLR_ALPHA_1 0xFF000000U /*!< Alpha Channel Value */
+
+/*!<Mode_RGB565 */
+#define DMA2D_OCOLR_BLUE_2 0x0000001FU /*!< BLUE Value */
+#define DMA2D_OCOLR_GREEN_2 0x000007E0U /*!< GREEN Value */
+#define DMA2D_OCOLR_RED_2 0x0000F800U /*!< Red Value */
+
+/*!<Mode_ARGB1555 */
+#define DMA2D_OCOLR_BLUE_3 0x0000001FU /*!< BLUE Value */
+#define DMA2D_OCOLR_GREEN_3 0x000003E0U /*!< GREEN Value */
+#define DMA2D_OCOLR_RED_3 0x00007C00U /*!< Red Value */
+#define DMA2D_OCOLR_ALPHA_3 0x00008000U /*!< Alpha Channel Value */
+
+/*!<Mode_ARGB4444 */
+#define DMA2D_OCOLR_BLUE_4 0x0000000FU /*!< BLUE Value */
+#define DMA2D_OCOLR_GREEN_4 0x000000F0U /*!< GREEN Value */
+#define DMA2D_OCOLR_RED_4 0x00000F00U /*!< Red Value */
+#define DMA2D_OCOLR_ALPHA_4 0x0000F000U /*!< Alpha Channel Value */
+
+/******************** Bit definition for DMA2D_OMAR register ****************/
+
+#define DMA2D_OMAR_MA 0xFFFFFFFFU /*!< Memory Address */
+
+/******************** Bit definition for DMA2D_OOR register *****************/
+
+#define DMA2D_OOR_LO 0x00003FFFU /*!< Line Offset */
+
+/******************** Bit definition for DMA2D_NLR register *****************/
+
+#define DMA2D_NLR_NL 0x0000FFFFU /*!< Number of Lines */
+#define DMA2D_NLR_PL 0x3FFF0000U /*!< Pixel per Lines */
+
+/******************** Bit definition for DMA2D_LWR register *****************/
+
+#define DMA2D_LWR_LW 0x0000FFFFU /*!< Line Watermark */
+
+/******************** Bit definition for DMA2D_AMTCR register ***************/
+
+#define DMA2D_AMTCR_EN 0x00000001U /*!< Enable */
+#define DMA2D_AMTCR_DT 0x0000FF00U /*!< Dead Time */
+
+/******************** Bit definition for DMA2D_FGCLUT register **************/
+
+/******************** Bit definition for DMA2D_BGCLUT register **************/
+
+
+
+/******************************************************************************/
+/* */
+/* External Interrupt/Event Controller */
+/* */
+/******************************************************************************/
+/******************* Bit definition for EXTI_IMR register *******************/
+#define EXTI_IMR_MR0 0x00000001U /*!< Interrupt Mask on line 0 */
+#define EXTI_IMR_MR1 0x00000002U /*!< Interrupt Mask on line 1 */
+#define EXTI_IMR_MR2 0x00000004U /*!< Interrupt Mask on line 2 */
+#define EXTI_IMR_MR3 0x00000008U /*!< Interrupt Mask on line 3 */
+#define EXTI_IMR_MR4 0x00000010U /*!< Interrupt Mask on line 4 */
+#define EXTI_IMR_MR5 0x00000020U /*!< Interrupt Mask on line 5 */
+#define EXTI_IMR_MR6 0x00000040U /*!< Interrupt Mask on line 6 */
+#define EXTI_IMR_MR7 0x00000080U /*!< Interrupt Mask on line 7 */
+#define EXTI_IMR_MR8 0x00000100U /*!< Interrupt Mask on line 8 */
+#define EXTI_IMR_MR9 0x00000200U /*!< Interrupt Mask on line 9 */
+#define EXTI_IMR_MR10 0x00000400U /*!< Interrupt Mask on line 10 */
+#define EXTI_IMR_MR11 0x00000800U /*!< Interrupt Mask on line 11 */
+#define EXTI_IMR_MR12 0x00001000U /*!< Interrupt Mask on line 12 */
+#define EXTI_IMR_MR13 0x00002000U /*!< Interrupt Mask on line 13 */
+#define EXTI_IMR_MR14 0x00004000U /*!< Interrupt Mask on line 14 */
+#define EXTI_IMR_MR15 0x00008000U /*!< Interrupt Mask on line 15 */
+#define EXTI_IMR_MR16 0x00010000U /*!< Interrupt Mask on line 16 */
+#define EXTI_IMR_MR17 0x00020000U /*!< Interrupt Mask on line 17 */
+#define EXTI_IMR_MR18 0x00040000U /*!< Interrupt Mask on line 18 */
+#define EXTI_IMR_MR19 0x00080000U /*!< Interrupt Mask on line 19 */
+#define EXTI_IMR_MR20 0x00100000U /*!< Interrupt Mask on line 20 */
+#define EXTI_IMR_MR21 0x00200000U /*!< Interrupt Mask on line 21 */
+#define EXTI_IMR_MR22 0x00400000U /*!< Interrupt Mask on line 22 */
+
+/******************* Bit definition for EXTI_EMR register *******************/
+#define EXTI_EMR_MR0 0x00000001U /*!< Event Mask on line 0 */
+#define EXTI_EMR_MR1 0x00000002U /*!< Event Mask on line 1 */
+#define EXTI_EMR_MR2 0x00000004U /*!< Event Mask on line 2 */
+#define EXTI_EMR_MR3 0x00000008U /*!< Event Mask on line 3 */
+#define EXTI_EMR_MR4 0x00000010U /*!< Event Mask on line 4 */
+#define EXTI_EMR_MR5 0x00000020U /*!< Event Mask on line 5 */
+#define EXTI_EMR_MR6 0x00000040U /*!< Event Mask on line 6 */
+#define EXTI_EMR_MR7 0x00000080U /*!< Event Mask on line 7 */
+#define EXTI_EMR_MR8 0x00000100U /*!< Event Mask on line 8 */
+#define EXTI_EMR_MR9 0x00000200U /*!< Event Mask on line 9 */
+#define EXTI_EMR_MR10 0x00000400U /*!< Event Mask on line 10 */
+#define EXTI_EMR_MR11 0x00000800U /*!< Event Mask on line 11 */
+#define EXTI_EMR_MR12 0x00001000U /*!< Event Mask on line 12 */
+#define EXTI_EMR_MR13 0x00002000U /*!< Event Mask on line 13 */
+#define EXTI_EMR_MR14 0x00004000U /*!< Event Mask on line 14 */
+#define EXTI_EMR_MR15 0x00008000U /*!< Event Mask on line 15 */
+#define EXTI_EMR_MR16 0x00010000U /*!< Event Mask on line 16 */
+#define EXTI_EMR_MR17 0x00020000U /*!< Event Mask on line 17 */
+#define EXTI_EMR_MR18 0x00040000U /*!< Event Mask on line 18 */
+#define EXTI_EMR_MR19 0x00080000U /*!< Event Mask on line 19 */
+#define EXTI_EMR_MR20 0x00100000U /*!< Event Mask on line 20 */
+#define EXTI_EMR_MR21 0x00200000U /*!< Event Mask on line 21 */
+#define EXTI_EMR_MR22 0x00400000U /*!< Event Mask on line 22 */
+
+/****************** Bit definition for EXTI_RTSR register *******************/
+#define EXTI_RTSR_TR0 0x00000001U /*!< Rising trigger event configuration bit of line 0 */
+#define EXTI_RTSR_TR1 0x00000002U /*!< Rising trigger event configuration bit of line 1 */
+#define EXTI_RTSR_TR2 0x00000004U /*!< Rising trigger event configuration bit of line 2 */
+#define EXTI_RTSR_TR3 0x00000008U /*!< Rising trigger event configuration bit of line 3 */
+#define EXTI_RTSR_TR4 0x00000010U /*!< Rising trigger event configuration bit of line 4 */
+#define EXTI_RTSR_TR5 0x00000020U /*!< Rising trigger event configuration bit of line 5 */
+#define EXTI_RTSR_TR6 0x00000040U /*!< Rising trigger event configuration bit of line 6 */
+#define EXTI_RTSR_TR7 0x00000080U /*!< Rising trigger event configuration bit of line 7 */
+#define EXTI_RTSR_TR8 0x00000100U /*!< Rising trigger event configuration bit of line 8 */
+#define EXTI_RTSR_TR9 0x00000200U /*!< Rising trigger event configuration bit of line 9 */
+#define EXTI_RTSR_TR10 0x00000400U /*!< Rising trigger event configuration bit of line 10 */
+#define EXTI_RTSR_TR11 0x00000800U /*!< Rising trigger event configuration bit of line 11 */
+#define EXTI_RTSR_TR12 0x00001000U /*!< Rising trigger event configuration bit of line 12 */
+#define EXTI_RTSR_TR13 0x00002000U /*!< Rising trigger event configuration bit of line 13 */
+#define EXTI_RTSR_TR14 0x00004000U /*!< Rising trigger event configuration bit of line 14 */
+#define EXTI_RTSR_TR15 0x00008000U /*!< Rising trigger event configuration bit of line 15 */
+#define EXTI_RTSR_TR16 0x00010000U /*!< Rising trigger event configuration bit of line 16 */
+#define EXTI_RTSR_TR17 0x00020000U /*!< Rising trigger event configuration bit of line 17 */
+#define EXTI_RTSR_TR18 0x00040000U /*!< Rising trigger event configuration bit of line 18 */
+#define EXTI_RTSR_TR19 0x00080000U /*!< Rising trigger event configuration bit of line 19 */
+#define EXTI_RTSR_TR20 0x00100000U /*!< Rising trigger event configuration bit of line 20 */
+#define EXTI_RTSR_TR21 0x00200000U /*!< Rising trigger event configuration bit of line 21 */
+#define EXTI_RTSR_TR22 0x00400000U /*!< Rising trigger event configuration bit of line 22 */
+
+/****************** Bit definition for EXTI_FTSR register *******************/
+#define EXTI_FTSR_TR0 0x00000001U /*!< Falling trigger event configuration bit of line 0 */
+#define EXTI_FTSR_TR1 0x00000002U /*!< Falling trigger event configuration bit of line 1 */
+#define EXTI_FTSR_TR2 0x00000004U /*!< Falling trigger event configuration bit of line 2 */
+#define EXTI_FTSR_TR3 0x00000008U /*!< Falling trigger event configuration bit of line 3 */
+#define EXTI_FTSR_TR4 0x00000010U /*!< Falling trigger event configuration bit of line 4 */
+#define EXTI_FTSR_TR5 0x00000020U /*!< Falling trigger event configuration bit of line 5 */
+#define EXTI_FTSR_TR6 0x00000040U /*!< Falling trigger event configuration bit of line 6 */
+#define EXTI_FTSR_TR7 0x00000080U /*!< Falling trigger event configuration bit of line 7 */
+#define EXTI_FTSR_TR8 0x00000100U /*!< Falling trigger event configuration bit of line 8 */
+#define EXTI_FTSR_TR9 0x00000200U /*!< Falling trigger event configuration bit of line 9 */
+#define EXTI_FTSR_TR10 0x00000400U /*!< Falling trigger event configuration bit of line 10 */
+#define EXTI_FTSR_TR11 0x00000800U /*!< Falling trigger event configuration bit of line 11 */
+#define EXTI_FTSR_TR12 0x00001000U /*!< Falling trigger event configuration bit of line 12 */
+#define EXTI_FTSR_TR13 0x00002000U /*!< Falling trigger event configuration bit of line 13 */
+#define EXTI_FTSR_TR14 0x00004000U /*!< Falling trigger event configuration bit of line 14 */
+#define EXTI_FTSR_TR15 0x00008000U /*!< Falling trigger event configuration bit of line 15 */
+#define EXTI_FTSR_TR16 0x00010000U /*!< Falling trigger event configuration bit of line 16 */
+#define EXTI_FTSR_TR17 0x00020000U /*!< Falling trigger event configuration bit of line 17 */
+#define EXTI_FTSR_TR18 0x00040000U /*!< Falling trigger event configuration bit of line 18 */
+#define EXTI_FTSR_TR19 0x00080000U /*!< Falling trigger event configuration bit of line 19 */
+#define EXTI_FTSR_TR20 0x00100000U /*!< Falling trigger event configuration bit of line 20 */
+#define EXTI_FTSR_TR21 0x00200000U /*!< Falling trigger event configuration bit of line 21 */
+#define EXTI_FTSR_TR22 0x00400000U /*!< Falling trigger event configuration bit of line 22 */
+
+/****************** Bit definition for EXTI_SWIER register ******************/
+#define EXTI_SWIER_SWIER0 0x00000001U /*!< Software Interrupt on line 0 */
+#define EXTI_SWIER_SWIER1 0x00000002U /*!< Software Interrupt on line 1 */
+#define EXTI_SWIER_SWIER2 0x00000004U /*!< Software Interrupt on line 2 */
+#define EXTI_SWIER_SWIER3 0x00000008U /*!< Software Interrupt on line 3 */
+#define EXTI_SWIER_SWIER4 0x00000010U /*!< Software Interrupt on line 4 */
+#define EXTI_SWIER_SWIER5 0x00000020U /*!< Software Interrupt on line 5 */
+#define EXTI_SWIER_SWIER6 0x00000040U /*!< Software Interrupt on line 6 */
+#define EXTI_SWIER_SWIER7 0x00000080U /*!< Software Interrupt on line 7 */
+#define EXTI_SWIER_SWIER8 0x00000100U /*!< Software Interrupt on line 8 */
+#define EXTI_SWIER_SWIER9 0x00000200U /*!< Software Interrupt on line 9 */
+#define EXTI_SWIER_SWIER10 0x00000400U /*!< Software Interrupt on line 10 */
+#define EXTI_SWIER_SWIER11 0x00000800U /*!< Software Interrupt on line 11 */
+#define EXTI_SWIER_SWIER12 0x00001000U /*!< Software Interrupt on line 12 */
+#define EXTI_SWIER_SWIER13 0x00002000U /*!< Software Interrupt on line 13 */
+#define EXTI_SWIER_SWIER14 0x00004000U /*!< Software Interrupt on line 14 */
+#define EXTI_SWIER_SWIER15 0x00008000U /*!< Software Interrupt on line 15 */
+#define EXTI_SWIER_SWIER16 0x00010000U /*!< Software Interrupt on line 16 */
+#define EXTI_SWIER_SWIER17 0x00020000U /*!< Software Interrupt on line 17 */
+#define EXTI_SWIER_SWIER18 0x00040000U /*!< Software Interrupt on line 18 */
+#define EXTI_SWIER_SWIER19 0x00080000U /*!< Software Interrupt on line 19 */
+#define EXTI_SWIER_SWIER20 0x00100000U /*!< Software Interrupt on line 20 */
+#define EXTI_SWIER_SWIER21 0x00200000U /*!< Software Interrupt on line 21 */
+#define EXTI_SWIER_SWIER22 0x00400000U /*!< Software Interrupt on line 22 */
+
+/******************* Bit definition for EXTI_PR register ********************/
+#define EXTI_PR_PR0 0x00000001U /*!< Pending bit for line 0 */
+#define EXTI_PR_PR1 0x00000002U /*!< Pending bit for line 1 */
+#define EXTI_PR_PR2 0x00000004U /*!< Pending bit for line 2 */
+#define EXTI_PR_PR3 0x00000008U /*!< Pending bit for line 3 */
+#define EXTI_PR_PR4 0x00000010U /*!< Pending bit for line 4 */
+#define EXTI_PR_PR5 0x00000020U /*!< Pending bit for line 5 */
+#define EXTI_PR_PR6 0x00000040U /*!< Pending bit for line 6 */
+#define EXTI_PR_PR7 0x00000080U /*!< Pending bit for line 7 */
+#define EXTI_PR_PR8 0x00000100U /*!< Pending bit for line 8 */
+#define EXTI_PR_PR9 0x00000200U /*!< Pending bit for line 9 */
+#define EXTI_PR_PR10 0x00000400U /*!< Pending bit for line 10 */
+#define EXTI_PR_PR11 0x00000800U /*!< Pending bit for line 11 */
+#define EXTI_PR_PR12 0x00001000U /*!< Pending bit for line 12 */
+#define EXTI_PR_PR13 0x00002000U /*!< Pending bit for line 13 */
+#define EXTI_PR_PR14 0x00004000U /*!< Pending bit for line 14 */
+#define EXTI_PR_PR15 0x00008000U /*!< Pending bit for line 15 */
+#define EXTI_PR_PR16 0x00010000U /*!< Pending bit for line 16 */
+#define EXTI_PR_PR17 0x00020000U /*!< Pending bit for line 17 */
+#define EXTI_PR_PR18 0x00040000U /*!< Pending bit for line 18 */
+#define EXTI_PR_PR19 0x00080000U /*!< Pending bit for line 19 */
+#define EXTI_PR_PR20 0x00100000U /*!< Pending bit for line 20 */
+#define EXTI_PR_PR21 0x00200000U /*!< Pending bit for line 21 */
+#define EXTI_PR_PR22 0x00400000U /*!< Pending bit for line 22 */
+
+/******************************************************************************/
+/* */
+/* FLASH */
+/* */
+/******************************************************************************/
+/******************* Bits definition for FLASH_ACR register *****************/
+#define FLASH_ACR_LATENCY 0x0000000FU
+#define FLASH_ACR_LATENCY_0WS 0x00000000U
+#define FLASH_ACR_LATENCY_1WS 0x00000001U
+#define FLASH_ACR_LATENCY_2WS 0x00000002U
+#define FLASH_ACR_LATENCY_3WS 0x00000003U
+#define FLASH_ACR_LATENCY_4WS 0x00000004U
+#define FLASH_ACR_LATENCY_5WS 0x00000005U
+#define FLASH_ACR_LATENCY_6WS 0x00000006U
+#define FLASH_ACR_LATENCY_7WS 0x00000007U
+#define FLASH_ACR_LATENCY_8WS 0x00000008U
+#define FLASH_ACR_LATENCY_9WS 0x00000009U
+#define FLASH_ACR_LATENCY_10WS 0x0000000AU
+#define FLASH_ACR_LATENCY_11WS 0x0000000BU
+#define FLASH_ACR_LATENCY_12WS 0x0000000CU
+#define FLASH_ACR_LATENCY_13WS 0x0000000DU
+#define FLASH_ACR_LATENCY_14WS 0x0000000EU
+#define FLASH_ACR_LATENCY_15WS 0x0000000FU
+#define FLASH_ACR_PRFTEN 0x00000100U
+#define FLASH_ACR_ICEN 0x00000200U
+#define FLASH_ACR_DCEN 0x00000400U
+#define FLASH_ACR_ICRST 0x00000800U
+#define FLASH_ACR_DCRST 0x00001000U
+#define FLASH_ACR_BYTE0_ADDRESS 0x40023C00U
+#define FLASH_ACR_BYTE2_ADDRESS 0x40023C03U
+
+/******************* Bits definition for FLASH_SR register ******************/
+#define FLASH_SR_EOP 0x00000001U
+#define FLASH_SR_SOP 0x00000002U
+#define FLASH_SR_WRPERR 0x00000010U
+#define FLASH_SR_PGAERR 0x00000020U
+#define FLASH_SR_PGPERR 0x00000040U
+#define FLASH_SR_PGSERR 0x00000080U
+#define FLASH_SR_BSY 0x00010000U
+
+/******************* Bits definition for FLASH_CR register ******************/
+#define FLASH_CR_PG 0x00000001U
+#define FLASH_CR_SER 0x00000002U
+#define FLASH_CR_MER 0x00000004U
+#define FLASH_CR_MER1 FLASH_CR_MER
+#define FLASH_CR_SNB 0x000000F8U
+#define FLASH_CR_SNB_0 0x00000008U
+#define FLASH_CR_SNB_1 0x00000010U
+#define FLASH_CR_SNB_2 0x00000020U
+#define FLASH_CR_SNB_3 0x00000040U
+#define FLASH_CR_SNB_4 0x00000080U
+#define FLASH_CR_PSIZE 0x00000300U
+#define FLASH_CR_PSIZE_0 0x00000100U
+#define FLASH_CR_PSIZE_1 0x00000200U
+#define FLASH_CR_MER2 0x00008000U
+#define FLASH_CR_STRT 0x00010000U
+#define FLASH_CR_EOPIE 0x01000000U
+#define FLASH_CR_LOCK 0x80000000U
+
+/******************* Bits definition for FLASH_OPTCR register ***************/
+#define FLASH_OPTCR_OPTLOCK 0x00000001U
+#define FLASH_OPTCR_OPTSTRT 0x00000002U
+#define FLASH_OPTCR_BOR_LEV_0 0x00000004U
+#define FLASH_OPTCR_BOR_LEV_1 0x00000008U
+#define FLASH_OPTCR_BOR_LEV 0x0000000CU
+#define FLASH_OPTCR_BFB2 0x00000010U
+#define FLASH_OPTCR_WDG_SW 0x00000020U
+#define FLASH_OPTCR_nRST_STOP 0x00000040U
+#define FLASH_OPTCR_nRST_STDBY 0x00000080U
+#define FLASH_OPTCR_RDP 0x0000FF00U
+#define FLASH_OPTCR_RDP_0 0x00000100U
+#define FLASH_OPTCR_RDP_1 0x00000200U
+#define FLASH_OPTCR_RDP_2 0x00000400U
+#define FLASH_OPTCR_RDP_3 0x00000800U
+#define FLASH_OPTCR_RDP_4 0x00001000U
+#define FLASH_OPTCR_RDP_5 0x00002000U
+#define FLASH_OPTCR_RDP_6 0x00004000U
+#define FLASH_OPTCR_RDP_7 0x00008000U
+#define FLASH_OPTCR_nWRP 0x0FFF0000U
+#define FLASH_OPTCR_nWRP_0 0x00010000U
+#define FLASH_OPTCR_nWRP_1 0x00020000U
+#define FLASH_OPTCR_nWRP_2 0x00040000U
+#define FLASH_OPTCR_nWRP_3 0x00080000U
+#define FLASH_OPTCR_nWRP_4 0x00100000U
+#define FLASH_OPTCR_nWRP_5 0x00200000U
+#define FLASH_OPTCR_nWRP_6 0x00400000U
+#define FLASH_OPTCR_nWRP_7 0x00800000U
+#define FLASH_OPTCR_nWRP_8 0x01000000U
+#define FLASH_OPTCR_nWRP_9 0x02000000U
+#define FLASH_OPTCR_nWRP_10 0x04000000U
+#define FLASH_OPTCR_nWRP_11 0x08000000U
+#define FLASH_OPTCR_DB1M 0x40000000U
+#define FLASH_OPTCR_SPRMOD 0x80000000U
+
+/****************** Bits definition for FLASH_OPTCR1 register ***************/
+#define FLASH_OPTCR1_nWRP 0x0FFF0000U
+#define FLASH_OPTCR1_nWRP_0 0x00010000U
+#define FLASH_OPTCR1_nWRP_1 0x00020000U
+#define FLASH_OPTCR1_nWRP_2 0x00040000U
+#define FLASH_OPTCR1_nWRP_3 0x00080000U
+#define FLASH_OPTCR1_nWRP_4 0x00100000U
+#define FLASH_OPTCR1_nWRP_5 0x00200000U
+#define FLASH_OPTCR1_nWRP_6 0x00400000U
+#define FLASH_OPTCR1_nWRP_7 0x00800000U
+#define FLASH_OPTCR1_nWRP_8 0x01000000U
+#define FLASH_OPTCR1_nWRP_9 0x02000000U
+#define FLASH_OPTCR1_nWRP_10 0x04000000U
+#define FLASH_OPTCR1_nWRP_11 0x08000000U
+
+/******************************************************************************/
+/* */
+/* Flexible Memory Controller */
+/* */
+/******************************************************************************/
+/****************** Bit definition for FMC_BCR1 register *******************/
+#define FMC_BCR1_MBKEN 0x00000001U /*!<Memory bank enable bit */
+#define FMC_BCR1_MUXEN 0x00000002U /*!<Address/data multiplexing enable bit */
+
+#define FMC_BCR1_MTYP 0x0000000CU /*!<MTYP[1:0] bits (Memory type) */
+#define FMC_BCR1_MTYP_0 0x00000004U /*!<Bit 0 */
+#define FMC_BCR1_MTYP_1 0x00000008U /*!<Bit 1 */
+
+#define FMC_BCR1_MWID 0x00000030U /*!<MWID[1:0] bits (Memory data bus width) */
+#define FMC_BCR1_MWID_0 0x00000010U /*!<Bit 0 */
+#define FMC_BCR1_MWID_1 0x00000020U /*!<Bit 1 */
+
+#define FMC_BCR1_FACCEN 0x00000040U /*!<Flash access enable */
+#define FMC_BCR1_BURSTEN 0x00000100U /*!<Burst enable bit */
+#define FMC_BCR1_WAITPOL 0x00000200U /*!<Wait signal polarity bit */
+#define FMC_BCR1_WRAPMOD 0x00000400U /*!<Wrapped burst mode support */
+#define FMC_BCR1_WAITCFG 0x00000800U /*!<Wait timing configuration */
+#define FMC_BCR1_WREN 0x00001000U /*!<Write enable bit */
+#define FMC_BCR1_WAITEN 0x00002000U /*!<Wait enable bit */
+#define FMC_BCR1_EXTMOD 0x00004000U /*!<Extended mode enable */
+#define FMC_BCR1_ASYNCWAIT 0x00008000U /*!<Asynchronous wait */
+#define FMC_BCR1_CPSIZE 0x00070000U /*!<CRAM page size */
+#define FMC_BCR1_CPSIZE_0 0x00010000U /*!<Bit 0 */
+#define FMC_BCR1_CPSIZE_1 0x00020000U /*!<Bit 1 */
+#define FMC_BCR1_CPSIZE_2 0x00040000U /*!<Bit 2 */
+#define FMC_BCR1_CBURSTRW 0x00080000U /*!<Write burst enable */
+#define FMC_BCR1_CCLKEN 0x00100000U /*!<Continous clock enable */
+
+/****************** Bit definition for FMC_BCR2 register *******************/
+#define FMC_BCR2_MBKEN 0x00000001U /*!<Memory bank enable bit */
+#define FMC_BCR2_MUXEN 0x00000002U /*!<Address/data multiplexing enable bit */
+
+#define FMC_BCR2_MTYP 0x0000000CU /*!<MTYP[1:0] bits (Memory type) */
+#define FMC_BCR2_MTYP_0 0x00000004U /*!<Bit 0 */
+#define FMC_BCR2_MTYP_1 0x00000008U /*!<Bit 1 */
+
+#define FMC_BCR2_MWID 0x00000030U /*!<MWID[1:0] bits (Memory data bus width) */
+#define FMC_BCR2_MWID_0 0x00000010U /*!<Bit 0 */
+#define FMC_BCR2_MWID_1 0x00000020U /*!<Bit 1 */
+
+#define FMC_BCR2_FACCEN 0x00000040U /*!<Flash access enable */
+#define FMC_BCR2_BURSTEN 0x00000100U /*!<Burst enable bit */
+#define FMC_BCR2_WAITPOL 0x00000200U /*!<Wait signal polarity bit */
+#define FMC_BCR2_WRAPMOD 0x00000400U /*!<Wrapped burst mode support */
+#define FMC_BCR2_WAITCFG 0x00000800U /*!<Wait timing configuration */
+#define FMC_BCR2_WREN 0x00001000U /*!<Write enable bit */
+#define FMC_BCR2_WAITEN 0x00002000U /*!<Wait enable bit */
+#define FMC_BCR2_EXTMOD 0x00004000U /*!<Extended mode enable */
+#define FMC_BCR2_ASYNCWAIT 0x00008000U /*!<Asynchronous wait */
+#define FMC_BCR2_CPSIZE 0x00070000U /*!<CRAM page size */
+#define FMC_BCR2_CPSIZE_0 0x00010000U /*!<Bit 0 */
+#define FMC_BCR2_CPSIZE_1 0x00020000U /*!<Bit 1 */
+#define FMC_BCR2_CPSIZE_2 0x00040000U /*!<Bit 2 */
+#define FMC_BCR2_CBURSTRW 0x00080000U /*!<Write burst enable */
+
+/****************** Bit definition for FMC_BCR3 register *******************/
+#define FMC_BCR3_MBKEN 0x00000001U /*!<Memory bank enable bit */
+#define FMC_BCR3_MUXEN 0x00000002U /*!<Address/data multiplexing enable bit */
+
+#define FMC_BCR3_MTYP 0x0000000CU /*!<MTYP[1:0] bits (Memory type) */
+#define FMC_BCR3_MTYP_0 0x00000004U /*!<Bit 0 */
+#define FMC_BCR3_MTYP_1 0x00000008U /*!<Bit 1 */
+
+#define FMC_BCR3_MWID 0x00000030U /*!<MWID[1:0] bits (Memory data bus width) */
+#define FMC_BCR3_MWID_0 0x00000010U /*!<Bit 0 */
+#define FMC_BCR3_MWID_1 0x00000020U /*!<Bit 1 */
+
+#define FMC_BCR3_FACCEN 0x00000040U /*!<Flash access enable */
+#define FMC_BCR3_BURSTEN 0x00000100U /*!<Burst enable bit */
+#define FMC_BCR3_WAITPOL 0x00000200U /*!<Wait signal polarity bit */
+#define FMC_BCR3_WRAPMOD 0x00000400U /*!<Wrapped burst mode support */
+#define FMC_BCR3_WAITCFG 0x00000800U /*!<Wait timing configuration */
+#define FMC_BCR3_WREN 0x00001000U /*!<Write enable bit */
+#define FMC_BCR3_WAITEN 0x00002000U /*!<Wait enable bit */
+#define FMC_BCR3_EXTMOD 0x00004000U /*!<Extended mode enable */
+#define FMC_BCR3_ASYNCWAIT 0x00008000U /*!<Asynchronous wait */
+#define FMC_BCR3_CPSIZE 0x00070000U /*!<CRAM page size */
+#define FMC_BCR3_CPSIZE_0 0x00010000U /*!<Bit 0 */
+#define FMC_BCR3_CPSIZE_1 0x00020000U /*!<Bit 1 */
+#define FMC_BCR3_CPSIZE_2 0x00040000U /*!<Bit 2 */
+#define FMC_BCR3_CBURSTRW 0x00080000U /*!<Write burst enable */
+
+/****************** Bit definition for FMC_BCR4 register *******************/
+#define FMC_BCR4_MBKEN 0x00000001U /*!<Memory bank enable bit */
+#define FMC_BCR4_MUXEN 0x00000002U /*!<Address/data multiplexing enable bit */
+
+#define FMC_BCR4_MTYP 0x0000000CU /*!<MTYP[1:0] bits (Memory type) */
+#define FMC_BCR4_MTYP_0 0x00000004U /*!<Bit 0 */
+#define FMC_BCR4_MTYP_1 0x00000008U /*!<Bit 1 */
+
+#define FMC_BCR4_MWID 0x00000030U /*!<MWID[1:0] bits (Memory data bus width) */
+#define FMC_BCR4_MWID_0 0x00000010U /*!<Bit 0 */
+#define FMC_BCR4_MWID_1 0x00000020U /*!<Bit 1 */
+
+#define FMC_BCR4_FACCEN 0x00000040U /*!<Flash access enable */
+#define FMC_BCR4_BURSTEN 0x00000100U /*!<Burst enable bit */
+#define FMC_BCR4_WAITPOL 0x00000200U /*!<Wait signal polarity bit */
+#define FMC_BCR4_WRAPMOD 0x00000400U /*!<Wrapped burst mode support */
+#define FMC_BCR4_WAITCFG 0x00000800U /*!<Wait timing configuration */
+#define FMC_BCR4_WREN 0x00001000U /*!<Write enable bit */
+#define FMC_BCR4_WAITEN 0x00002000U /*!<Wait enable bit */
+#define FMC_BCR4_EXTMOD 0x00004000U /*!<Extended mode enable */
+#define FMC_BCR4_ASYNCWAIT 0x00008000U /*!<Asynchronous wait */
+#define FMC_BCR4_CPSIZE 0x00070000U /*!<CRAM page size */
+#define FMC_BCR4_CPSIZE_0 0x00010000U /*!<Bit 0 */
+#define FMC_BCR4_CPSIZE_1 0x00020000U /*!<Bit 1 */
+#define FMC_BCR4_CPSIZE_2 0x00040000U /*!<Bit 2 */
+#define FMC_BCR4_CBURSTRW 0x00080000U /*!<Write burst enable */
+
+/****************** Bit definition for FMC_BTR1 register ******************/
+#define FMC_BTR1_ADDSET 0x0000000FU /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FMC_BTR1_ADDSET_0 0x00000001U /*!<Bit 0 */
+#define FMC_BTR1_ADDSET_1 0x00000002U /*!<Bit 1 */
+#define FMC_BTR1_ADDSET_2 0x00000004U /*!<Bit 2 */
+#define FMC_BTR1_ADDSET_3 0x00000008U /*!<Bit 3 */
+
+#define FMC_BTR1_ADDHLD 0x000000F0U /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FMC_BTR1_ADDHLD_0 0x00000010U /*!<Bit 0 */
+#define FMC_BTR1_ADDHLD_1 0x00000020U /*!<Bit 1 */
+#define FMC_BTR1_ADDHLD_2 0x00000040U /*!<Bit 2 */
+#define FMC_BTR1_ADDHLD_3 0x00000080U /*!<Bit 3 */
+
+#define FMC_BTR1_DATAST 0x0000FF00U /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FMC_BTR1_DATAST_0 0x00000100U /*!<Bit 0 */
+#define FMC_BTR1_DATAST_1 0x00000200U /*!<Bit 1 */
+#define FMC_BTR1_DATAST_2 0x00000400U /*!<Bit 2 */
+#define FMC_BTR1_DATAST_3 0x00000800U /*!<Bit 3 */
+#define FMC_BTR1_DATAST_4 0x00001000U /*!<Bit 4 */
+#define FMC_BTR1_DATAST_5 0x00002000U /*!<Bit 5 */
+#define FMC_BTR1_DATAST_6 0x00004000U /*!<Bit 6 */
+#define FMC_BTR1_DATAST_7 0x00008000U /*!<Bit 7 */
+
+#define FMC_BTR1_BUSTURN 0x000F0000U /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define FMC_BTR1_BUSTURN_0 0x00010000U /*!<Bit 0 */
+#define FMC_BTR1_BUSTURN_1 0x00020000U /*!<Bit 1 */
+#define FMC_BTR1_BUSTURN_2 0x00040000U /*!<Bit 2 */
+#define FMC_BTR1_BUSTURN_3 0x00080000U /*!<Bit 3 */
+
+#define FMC_BTR1_CLKDIV 0x00F00000U /*!<CLKDIV[3:0] bits (Clock divide ratio) */
+#define FMC_BTR1_CLKDIV_0 0x00100000U /*!<Bit 0 */
+#define FMC_BTR1_CLKDIV_1 0x00200000U /*!<Bit 1 */
+#define FMC_BTR1_CLKDIV_2 0x00400000U /*!<Bit 2 */
+#define FMC_BTR1_CLKDIV_3 0x00800000U /*!<Bit 3 */
+
+#define FMC_BTR1_DATLAT 0x0F000000U /*!<DATLA[3:0] bits (Data latency) */
+#define FMC_BTR1_DATLAT_0 0x01000000U /*!<Bit 0 */
+#define FMC_BTR1_DATLAT_1 0x02000000U /*!<Bit 1 */
+#define FMC_BTR1_DATLAT_2 0x04000000U /*!<Bit 2 */
+#define FMC_BTR1_DATLAT_3 0x08000000U /*!<Bit 3 */
+
+#define FMC_BTR1_ACCMOD 0x30000000U /*!<ACCMOD[1:0] bits (Access mode) */
+#define FMC_BTR1_ACCMOD_0 0x10000000U /*!<Bit 0 */
+#define FMC_BTR1_ACCMOD_1 0x20000000U /*!<Bit 1 */
+
+/****************** Bit definition for FMC_BTR2 register *******************/
+#define FMC_BTR2_ADDSET 0x0000000FU /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FMC_BTR2_ADDSET_0 0x00000001U /*!<Bit 0 */
+#define FMC_BTR2_ADDSET_1 0x00000002U /*!<Bit 1 */
+#define FMC_BTR2_ADDSET_2 0x00000004U /*!<Bit 2 */
+#define FMC_BTR2_ADDSET_3 0x00000008U /*!<Bit 3 */
+
+#define FMC_BTR2_ADDHLD 0x000000F0U /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FMC_BTR2_ADDHLD_0 0x00000010U /*!<Bit 0 */
+#define FMC_BTR2_ADDHLD_1 0x00000020U /*!<Bit 1 */
+#define FMC_BTR2_ADDHLD_2 0x00000040U /*!<Bit 2 */
+#define FMC_BTR2_ADDHLD_3 0x00000080U /*!<Bit 3 */
+
+#define FMC_BTR2_DATAST 0x0000FF00U /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FMC_BTR2_DATAST_0 0x00000100U /*!<Bit 0 */
+#define FMC_BTR2_DATAST_1 0x00000200U /*!<Bit 1 */
+#define FMC_BTR2_DATAST_2 0x00000400U /*!<Bit 2 */
+#define FMC_BTR2_DATAST_3 0x00000800U /*!<Bit 3 */
+#define FMC_BTR2_DATAST_4 0x00001000U /*!<Bit 4 */
+#define FMC_BTR2_DATAST_5 0x00002000U /*!<Bit 5 */
+#define FMC_BTR2_DATAST_6 0x00004000U /*!<Bit 6 */
+#define FMC_BTR2_DATAST_7 0x00008000U /*!<Bit 7 */
+
+#define FMC_BTR2_BUSTURN 0x000F0000U /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define FMC_BTR2_BUSTURN_0 0x00010000U /*!<Bit 0 */
+#define FMC_BTR2_BUSTURN_1 0x00020000U /*!<Bit 1 */
+#define FMC_BTR2_BUSTURN_2 0x00040000U /*!<Bit 2 */
+#define FMC_BTR2_BUSTURN_3 0x00080000U /*!<Bit 3 */
+
+#define FMC_BTR2_CLKDIV 0x00F00000U /*!<CLKDIV[3:0] bits (Clock divide ratio) */
+#define FMC_BTR2_CLKDIV_0 0x00100000U /*!<Bit 0 */
+#define FMC_BTR2_CLKDIV_1 0x00200000U /*!<Bit 1 */
+#define FMC_BTR2_CLKDIV_2 0x00400000U /*!<Bit 2 */
+#define FMC_BTR2_CLKDIV_3 0x00800000U /*!<Bit 3 */
+
+#define FMC_BTR2_DATLAT 0x0F000000U /*!<DATLA[3:0] bits (Data latency) */
+#define FMC_BTR2_DATLAT_0 0x01000000U /*!<Bit 0 */
+#define FMC_BTR2_DATLAT_1 0x02000000U /*!<Bit 1 */
+#define FMC_BTR2_DATLAT_2 0x04000000U /*!<Bit 2 */
+#define FMC_BTR2_DATLAT_3 0x08000000U /*!<Bit 3 */
+
+#define FMC_BTR2_ACCMOD 0x30000000U /*!<ACCMOD[1:0] bits (Access mode) */
+#define FMC_BTR2_ACCMOD_0 0x10000000U /*!<Bit 0 */
+#define FMC_BTR2_ACCMOD_1 0x20000000U /*!<Bit 1 */
+
+/******************* Bit definition for FMC_BTR3 register *******************/
+#define FMC_BTR3_ADDSET 0x0000000FU /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FMC_BTR3_ADDSET_0 0x00000001U /*!<Bit 0 */
+#define FMC_BTR3_ADDSET_1 0x00000002U /*!<Bit 1 */
+#define FMC_BTR3_ADDSET_2 0x00000004U /*!<Bit 2 */
+#define FMC_BTR3_ADDSET_3 0x00000008U /*!<Bit 3 */
+
+#define FMC_BTR3_ADDHLD 0x000000F0U /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FMC_BTR3_ADDHLD_0 0x00000010U /*!<Bit 0 */
+#define FMC_BTR3_ADDHLD_1 0x00000020U /*!<Bit 1 */
+#define FMC_BTR3_ADDHLD_2 0x00000040U /*!<Bit 2 */
+#define FMC_BTR3_ADDHLD_3 0x00000080U /*!<Bit 3 */
+
+#define FMC_BTR3_DATAST 0x0000FF00U /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FMC_BTR3_DATAST_0 0x00000100U /*!<Bit 0 */
+#define FMC_BTR3_DATAST_1 0x00000200U /*!<Bit 1 */
+#define FMC_BTR3_DATAST_2 0x00000400U /*!<Bit 2 */
+#define FMC_BTR3_DATAST_3 0x00000800U /*!<Bit 3 */
+#define FMC_BTR3_DATAST_4 0x00001000U /*!<Bit 4 */
+#define FMC_BTR3_DATAST_5 0x00002000U /*!<Bit 5 */
+#define FMC_BTR3_DATAST_6 0x00004000U /*!<Bit 6 */
+#define FMC_BTR3_DATAST_7 0x00008000U /*!<Bit 7 */
+
+#define FMC_BTR3_BUSTURN 0x000F0000U /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define FMC_BTR3_BUSTURN_0 0x00010000U /*!<Bit 0 */
+#define FMC_BTR3_BUSTURN_1 0x00020000U /*!<Bit 1 */
+#define FMC_BTR3_BUSTURN_2 0x00040000U /*!<Bit 2 */
+#define FMC_BTR3_BUSTURN_3 0x00080000U /*!<Bit 3 */
+
+#define FMC_BTR3_CLKDIV 0x00F00000U /*!<CLKDIV[3:0] bits (Clock divide ratio) */
+#define FMC_BTR3_CLKDIV_0 0x00100000U /*!<Bit 0 */
+#define FMC_BTR3_CLKDIV_1 0x00200000U /*!<Bit 1 */
+#define FMC_BTR3_CLKDIV_2 0x00400000U /*!<Bit 2 */
+#define FMC_BTR3_CLKDIV_3 0x00800000U /*!<Bit 3 */
+
+#define FMC_BTR3_DATLAT 0x0F000000U /*!<DATLA[3:0] bits (Data latency) */
+#define FMC_BTR3_DATLAT_0 0x01000000U /*!<Bit 0 */
+#define FMC_BTR3_DATLAT_1 0x02000000U /*!<Bit 1 */
+#define FMC_BTR3_DATLAT_2 0x04000000U /*!<Bit 2 */
+#define FMC_BTR3_DATLAT_3 0x08000000U /*!<Bit 3 */
+
+#define FMC_BTR3_ACCMOD 0x30000000U /*!<ACCMOD[1:0] bits (Access mode) */
+#define FMC_BTR3_ACCMOD_0 0x10000000U /*!<Bit 0 */
+#define FMC_BTR3_ACCMOD_1 0x20000000U /*!<Bit 1 */
+
+/****************** Bit definition for FMC_BTR4 register *******************/
+#define FMC_BTR4_ADDSET 0x0000000FU /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FMC_BTR4_ADDSET_0 0x00000001U /*!<Bit 0 */
+#define FMC_BTR4_ADDSET_1 0x00000002U /*!<Bit 1 */
+#define FMC_BTR4_ADDSET_2 0x00000004U /*!<Bit 2 */
+#define FMC_BTR4_ADDSET_3 0x00000008U /*!<Bit 3 */
+
+#define FMC_BTR4_ADDHLD 0x000000F0U /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FMC_BTR4_ADDHLD_0 0x00000010U /*!<Bit 0 */
+#define FMC_BTR4_ADDHLD_1 0x00000020U /*!<Bit 1 */
+#define FMC_BTR4_ADDHLD_2 0x00000040U /*!<Bit 2 */
+#define FMC_BTR4_ADDHLD_3 0x00000080U /*!<Bit 3 */
+
+#define FMC_BTR4_DATAST 0x0000FF00U /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FMC_BTR4_DATAST_0 0x00000100U /*!<Bit 0 */
+#define FMC_BTR4_DATAST_1 0x00000200U /*!<Bit 1 */
+#define FMC_BTR4_DATAST_2 0x00000400U /*!<Bit 2 */
+#define FMC_BTR4_DATAST_3 0x00000800U /*!<Bit 3 */
+#define FMC_BTR4_DATAST_4 0x00001000U /*!<Bit 4 */
+#define FMC_BTR4_DATAST_5 0x00002000U /*!<Bit 5 */
+#define FMC_BTR4_DATAST_6 0x00004000U /*!<Bit 6 */
+#define FMC_BTR4_DATAST_7 0x00008000U /*!<Bit 7 */
+
+#define FMC_BTR4_BUSTURN 0x000F0000U /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define FMC_BTR4_BUSTURN_0 0x00010000U /*!<Bit 0 */
+#define FMC_BTR4_BUSTURN_1 0x00020000U /*!<Bit 1 */
+#define FMC_BTR4_BUSTURN_2 0x00040000U /*!<Bit 2 */
+#define FMC_BTR4_BUSTURN_3 0x00080000U /*!<Bit 3 */
+
+#define FMC_BTR4_CLKDIV 0x00F00000U /*!<CLKDIV[3:0] bits (Clock divide ratio) */
+#define FMC_BTR4_CLKDIV_0 0x00100000U /*!<Bit 0 */
+#define FMC_BTR4_CLKDIV_1 0x00200000U /*!<Bit 1 */
+#define FMC_BTR4_CLKDIV_2 0x00400000U /*!<Bit 2 */
+#define FMC_BTR4_CLKDIV_3 0x00800000U /*!<Bit 3 */
+
+#define FMC_BTR4_DATLAT 0x0F000000U /*!<DATLA[3:0] bits (Data latency) */
+#define FMC_BTR4_DATLAT_0 0x01000000U /*!<Bit 0 */
+#define FMC_BTR4_DATLAT_1 0x02000000U /*!<Bit 1 */
+#define FMC_BTR4_DATLAT_2 0x04000000U /*!<Bit 2 */
+#define FMC_BTR4_DATLAT_3 0x08000000U /*!<Bit 3 */
+
+#define FMC_BTR4_ACCMOD 0x30000000U /*!<ACCMOD[1:0] bits (Access mode) */
+#define FMC_BTR4_ACCMOD_0 0x10000000U /*!<Bit 0 */
+#define FMC_BTR4_ACCMOD_1 0x20000000U /*!<Bit 1 */
+
+/****************** Bit definition for FMC_BWTR1 register ******************/
+#define FMC_BWTR1_ADDSET 0x0000000FU /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FMC_BWTR1_ADDSET_0 0x00000001U /*!<Bit 0 */
+#define FMC_BWTR1_ADDSET_1 0x00000002U /*!<Bit 1 */
+#define FMC_BWTR1_ADDSET_2 0x00000004U /*!<Bit 2 */
+#define FMC_BWTR1_ADDSET_3 0x00000008U /*!<Bit 3 */
+
+#define FMC_BWTR1_ADDHLD 0x000000F0U /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FMC_BWTR1_ADDHLD_0 0x00000010U /*!<Bit 0 */
+#define FMC_BWTR1_ADDHLD_1 0x00000020U /*!<Bit 1 */
+#define FMC_BWTR1_ADDHLD_2 0x00000040U /*!<Bit 2 */
+#define FMC_BWTR1_ADDHLD_3 0x00000080U /*!<Bit 3 */
+
+#define FMC_BWTR1_DATAST 0x0000FF00U /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FMC_BWTR1_DATAST_0 0x00000100U /*!<Bit 0 */
+#define FMC_BWTR1_DATAST_1 0x00000200U /*!<Bit 1 */
+#define FMC_BWTR1_DATAST_2 0x00000400U /*!<Bit 2 */
+#define FMC_BWTR1_DATAST_3 0x00000800U /*!<Bit 3 */
+#define FMC_BWTR1_DATAST_4 0x00001000U /*!<Bit 4 */
+#define FMC_BWTR1_DATAST_5 0x00002000U /*!<Bit 5 */
+#define FMC_BWTR1_DATAST_6 0x00004000U /*!<Bit 6 */
+#define FMC_BWTR1_DATAST_7 0x00008000U /*!<Bit 7 */
+
+#define FMC_BWTR1_BUSTURN 0x000F0000U /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
+#define FMC_BWTR1_BUSTURN_0 0x00010000U /*!<Bit 0 */
+#define FMC_BWTR1_BUSTURN_1 0x00020000U /*!<Bit 1 */
+#define FMC_BWTR1_BUSTURN_2 0x00040000U /*!<Bit 2 */
+#define FMC_BWTR1_BUSTURN_3 0x00080000U /*!<Bit 3 */
+
+#define FMC_BWTR1_ACCMOD 0x30000000U /*!<ACCMOD[1:0] bits (Access mode) */
+#define FMC_BWTR1_ACCMOD_0 0x10000000U /*!<Bit 0 */
+#define FMC_BWTR1_ACCMOD_1 0x20000000U /*!<Bit 1 */
+
+/****************** Bit definition for FMC_BWTR2 register ******************/
+#define FMC_BWTR2_ADDSET 0x0000000FU /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FMC_BWTR2_ADDSET_0 0x00000001U /*!<Bit 0 */
+#define FMC_BWTR2_ADDSET_1 0x00000002U /*!<Bit 1 */
+#define FMC_BWTR2_ADDSET_2 0x00000004U /*!<Bit 2 */
+#define FMC_BWTR2_ADDSET_3 0x00000008U /*!<Bit 3 */
+
+#define FMC_BWTR2_ADDHLD 0x000000F0U /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FMC_BWTR2_ADDHLD_0 0x00000010U /*!<Bit 0 */
+#define FMC_BWTR2_ADDHLD_1 0x00000020U /*!<Bit 1 */
+#define FMC_BWTR2_ADDHLD_2 0x00000040U /*!<Bit 2 */
+#define FMC_BWTR2_ADDHLD_3 0x00000080U /*!<Bit 3 */
+
+#define FMC_BWTR2_DATAST 0x0000FF00U /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FMC_BWTR2_DATAST_0 0x00000100U /*!<Bit 0 */
+#define FMC_BWTR2_DATAST_1 0x00000200U /*!<Bit 1 */
+#define FMC_BWTR2_DATAST_2 0x00000400U /*!<Bit 2 */
+#define FMC_BWTR2_DATAST_3 0x00000800U /*!<Bit 3 */
+#define FMC_BWTR2_DATAST_4 0x00001000U /*!<Bit 4 */
+#define FMC_BWTR2_DATAST_5 0x00002000U /*!<Bit 5 */
+#define FMC_BWTR2_DATAST_6 0x00004000U /*!<Bit 6 */
+#define FMC_BWTR2_DATAST_7 0x00008000U /*!<Bit 7 */
+
+#define FMC_BWTR2_BUSTURN 0x000F0000U /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
+#define FMC_BWTR2_BUSTURN_0 0x00010000U /*!<Bit 0 */
+#define FMC_BWTR2_BUSTURN_1 0x00020000U /*!<Bit 1 */
+#define FMC_BWTR2_BUSTURN_2 0x00040000U /*!<Bit 2 */
+#define FMC_BWTR2_BUSTURN_3 0x00080000U /*!<Bit 3 */
+
+#define FMC_BWTR2_ACCMOD 0x30000000U /*!<ACCMOD[1:0] bits (Access mode) */
+#define FMC_BWTR2_ACCMOD_0 0x10000000U /*!<Bit 0 */
+#define FMC_BWTR2_ACCMOD_1 0x20000000U /*!<Bit 1 */
+
+/****************** Bit definition for FMC_BWTR3 register ******************/
+#define FMC_BWTR3_ADDSET 0x0000000FU /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FMC_BWTR3_ADDSET_0 0x00000001U /*!<Bit 0 */
+#define FMC_BWTR3_ADDSET_1 0x00000002U /*!<Bit 1 */
+#define FMC_BWTR3_ADDSET_2 0x00000004U /*!<Bit 2 */
+#define FMC_BWTR3_ADDSET_3 0x00000008U /*!<Bit 3 */
+
+#define FMC_BWTR3_ADDHLD 0x000000F0U /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FMC_BWTR3_ADDHLD_0 0x00000010U /*!<Bit 0 */
+#define FMC_BWTR3_ADDHLD_1 0x00000020U /*!<Bit 1 */
+#define FMC_BWTR3_ADDHLD_2 0x00000040U /*!<Bit 2 */
+#define FMC_BWTR3_ADDHLD_3 0x00000080U /*!<Bit 3 */
+
+#define FMC_BWTR3_DATAST 0x0000FF00U /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FMC_BWTR3_DATAST_0 0x00000100U /*!<Bit 0 */
+#define FMC_BWTR3_DATAST_1 0x00000200U /*!<Bit 1 */
+#define FMC_BWTR3_DATAST_2 0x00000400U /*!<Bit 2 */
+#define FMC_BWTR3_DATAST_3 0x00000800U /*!<Bit 3 */
+#define FMC_BWTR3_DATAST_4 0x00001000U /*!<Bit 4 */
+#define FMC_BWTR3_DATAST_5 0x00002000U /*!<Bit 5 */
+#define FMC_BWTR3_DATAST_6 0x00004000U /*!<Bit 6 */
+#define FMC_BWTR3_DATAST_7 0x00008000U /*!<Bit 7 */
+
+#define FMC_BWTR3_BUSTURN 0x000F0000U /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
+#define FMC_BWTR3_BUSTURN_0 0x00010000U /*!<Bit 0 */
+#define FMC_BWTR3_BUSTURN_1 0x00020000U /*!<Bit 1 */
+#define FMC_BWTR3_BUSTURN_2 0x00040000U /*!<Bit 2 */
+#define FMC_BWTR3_BUSTURN_3 0x00080000U /*!<Bit 3 */
+
+#define FMC_BWTR3_ACCMOD 0x30000000U /*!<ACCMOD[1:0] bits (Access mode) */
+#define FMC_BWTR3_ACCMOD_0 0x10000000U /*!<Bit 0 */
+#define FMC_BWTR3_ACCMOD_1 0x20000000U /*!<Bit 1 */
+
+/****************** Bit definition for FMC_BWTR4 register ******************/
+#define FMC_BWTR4_ADDSET 0x0000000FU /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FMC_BWTR4_ADDSET_0 0x00000001U /*!<Bit 0 */
+#define FMC_BWTR4_ADDSET_1 0x00000002U /*!<Bit 1 */
+#define FMC_BWTR4_ADDSET_2 0x00000004U /*!<Bit 2 */
+#define FMC_BWTR4_ADDSET_3 0x00000008U /*!<Bit 3 */
+
+#define FMC_BWTR4_ADDHLD 0x000000F0U /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FMC_BWTR4_ADDHLD_0 0x00000010U /*!<Bit 0 */
+#define FMC_BWTR4_ADDHLD_1 0x00000020U /*!<Bit 1 */
+#define FMC_BWTR4_ADDHLD_2 0x00000040U /*!<Bit 2 */
+#define FMC_BWTR4_ADDHLD_3 0x00000080U /*!<Bit 3 */
+
+#define FMC_BWTR4_DATAST 0x0000FF00U /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FMC_BWTR4_DATAST_0 0x00000100U /*!<Bit 0 */
+#define FMC_BWTR4_DATAST_1 0x00000200U /*!<Bit 1 */
+#define FMC_BWTR4_DATAST_2 0x00000400U /*!<Bit 2 */
+#define FMC_BWTR4_DATAST_3 0x00000800U /*!<Bit 3 */
+#define FMC_BWTR4_DATAST_4 0x00001000U /*!<Bit 4 */
+#define FMC_BWTR4_DATAST_5 0x00002000U /*!<Bit 5 */
+#define FMC_BWTR4_DATAST_6 0x00004000U /*!<Bit 6 */
+#define FMC_BWTR4_DATAST_7 0x00008000U /*!<Bit 7 */
+
+#define FMC_BWTR4_BUSTURN 0x000F0000U /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
+#define FMC_BWTR4_BUSTURN_0 0x00010000U /*!<Bit 0 */
+#define FMC_BWTR4_BUSTURN_1 0x00020000U /*!<Bit 1 */
+#define FMC_BWTR4_BUSTURN_2 0x00040000U /*!<Bit 2 */
+#define FMC_BWTR4_BUSTURN_3 0x00080000U /*!<Bit 3 */
+
+#define FMC_BWTR4_ACCMOD 0x30000000U /*!<ACCMOD[1:0] bits (Access mode) */
+#define FMC_BWTR4_ACCMOD_0 0x10000000U /*!<Bit 0 */
+#define FMC_BWTR4_ACCMOD_1 0x20000000U /*!<Bit 1 */
+
+/****************** Bit definition for FMC_PCR2 register *******************/
+#define FMC_PCR2_PWAITEN 0x00000002U /*!<Wait feature enable bit */
+#define FMC_PCR2_PBKEN 0x00000004U /*!<PC Card/NAND Flash memory bank enable bit */
+#define FMC_PCR2_PTYP 0x00000008U /*!<Memory type */
+
+#define FMC_PCR2_PWID 0x00000030U /*!<PWID[1:0] bits (NAND Flash databus width) */
+#define FMC_PCR2_PWID_0 0x00000010U /*!<Bit 0 */
+#define FMC_PCR2_PWID_1 0x00000020U /*!<Bit 1 */
+
+#define FMC_PCR2_ECCEN 0x00000040U /*!<ECC computation logic enable bit */
+
+#define FMC_PCR2_TCLR 0x00001E00U /*!<TCLR[3:0] bits (CLE to RE delay) */
+#define FMC_PCR2_TCLR_0 0x00000200U /*!<Bit 0 */
+#define FMC_PCR2_TCLR_1 0x00000400U /*!<Bit 1 */
+#define FMC_PCR2_TCLR_2 0x00000800U /*!<Bit 2 */
+#define FMC_PCR2_TCLR_3 0x00001000U /*!<Bit 3 */
+
+#define FMC_PCR2_TAR 0x0001E000U /*!<TAR[3:0] bits (ALE to RE delay) */
+#define FMC_PCR2_TAR_0 0x00002000U /*!<Bit 0 */
+#define FMC_PCR2_TAR_1 0x00004000U /*!<Bit 1 */
+#define FMC_PCR2_TAR_2 0x00008000U /*!<Bit 2 */
+#define FMC_PCR2_TAR_3 0x00010000U /*!<Bit 3 */
+
+#define FMC_PCR2_ECCPS 0x000E0000U /*!<ECCPS[1:0] bits (ECC page size) */
+#define FMC_PCR2_ECCPS_0 0x00020000U /*!<Bit 0 */
+#define FMC_PCR2_ECCPS_1 0x00040000U /*!<Bit 1 */
+#define FMC_PCR2_ECCPS_2 0x00080000U /*!<Bit 2 */
+
+/****************** Bit definition for FMC_PCR3 register *******************/
+#define FMC_PCR3_PWAITEN 0x00000002U /*!<Wait feature enable bit */
+#define FMC_PCR3_PBKEN 0x00000004U /*!<PC Card/NAND Flash memory bank enable bit */
+#define FMC_PCR3_PTYP 0x00000008U /*!<Memory type */
+
+#define FMC_PCR3_PWID 0x00000030U /*!<PWID[1:0] bits (NAND Flash databus width) */
+#define FMC_PCR3_PWID_0 0x00000010U /*!<Bit 0 */
+#define FMC_PCR3_PWID_1 0x00000020U /*!<Bit 1 */
+
+#define FMC_PCR3_ECCEN 0x00000040U /*!<ECC computation logic enable bit */
+
+#define FMC_PCR3_TCLR 0x00001E00U /*!<TCLR[3:0] bits (CLE to RE delay) */
+#define FMC_PCR3_TCLR_0 0x00000200U /*!<Bit 0 */
+#define FMC_PCR3_TCLR_1 0x00000400U /*!<Bit 1 */
+#define FMC_PCR3_TCLR_2 0x00000800U /*!<Bit 2 */
+#define FMC_PCR3_TCLR_3 0x00001000U /*!<Bit 3 */
+
+#define FMC_PCR3_TAR 0x0001E000U /*!<TAR[3:0] bits (ALE to RE delay) */
+#define FMC_PCR3_TAR_0 0x00002000U /*!<Bit 0 */
+#define FMC_PCR3_TAR_1 0x00004000U /*!<Bit 1 */
+#define FMC_PCR3_TAR_2 0x00008000U /*!<Bit 2 */
+#define FMC_PCR3_TAR_3 0x00010000U /*!<Bit 3 */
+
+#define FMC_PCR3_ECCPS 0x000E0000U /*!<ECCPS[2:0] bits (ECC page size) */
+#define FMC_PCR3_ECCPS_0 0x00020000U /*!<Bit 0 */
+#define FMC_PCR3_ECCPS_1 0x00040000U /*!<Bit 1 */
+#define FMC_PCR3_ECCPS_2 0x00080000U /*!<Bit 2 */
+
+/****************** Bit definition for FMC_PCR4 register *******************/
+#define FMC_PCR4_PWAITEN 0x00000002U /*!<Wait feature enable bit */
+#define FMC_PCR4_PBKEN 0x00000004U /*!<PC Card/NAND Flash memory bank enable bit */
+#define FMC_PCR4_PTYP 0x00000008U /*!<Memory type */
+
+#define FMC_PCR4_PWID 0x00000030U /*!<PWID[1:0] bits (NAND Flash databus width) */
+#define FMC_PCR4_PWID_0 0x00000010U /*!<Bit 0 */
+#define FMC_PCR4_PWID_1 0x00000020U /*!<Bit 1 */
+
+#define FMC_PCR4_ECCEN 0x00000040U /*!<ECC computation logic enable bit */
+
+#define FMC_PCR4_TCLR 0x00001E00U /*!<TCLR[3:0] bits (CLE to RE delay) */
+#define FMC_PCR4_TCLR_0 0x00000200U /*!<Bit 0 */
+#define FMC_PCR4_TCLR_1 0x00000400U /*!<Bit 1 */
+#define FMC_PCR4_TCLR_2 0x00000800U /*!<Bit 2 */
+#define FMC_PCR4_TCLR_3 0x00001000U /*!<Bit 3 */
+
+#define FMC_PCR4_TAR 0x0001E000U /*!<TAR[3:0] bits (ALE to RE delay) */
+#define FMC_PCR4_TAR_0 0x00002000U /*!<Bit 0 */
+#define FMC_PCR4_TAR_1 0x00004000U /*!<Bit 1 */
+#define FMC_PCR4_TAR_2 0x00008000U /*!<Bit 2 */
+#define FMC_PCR4_TAR_3 0x00010000U /*!<Bit 3 */
+
+#define FMC_PCR4_ECCPS 0x000E0000U /*!<ECCPS[2:0] bits (ECC page size) */
+#define FMC_PCR4_ECCPS_0 0x00020000U /*!<Bit 0 */
+#define FMC_PCR4_ECCPS_1 0x00040000U /*!<Bit 1 */
+#define FMC_PCR4_ECCPS_2 0x00080000U /*!<Bit 2 */
+
+/******************* Bit definition for FMC_SR2 register *******************/
+#define FMC_SR2_IRS 0x01U /*!<Interrupt Rising Edge status */
+#define FMC_SR2_ILS 0x02U /*!<Interrupt Level status */
+#define FMC_SR2_IFS 0x04U /*!<Interrupt Falling Edge status */
+#define FMC_SR2_IREN 0x08U /*!<Interrupt Rising Edge detection Enable bit */
+#define FMC_SR2_ILEN 0x10U /*!<Interrupt Level detection Enable bit */
+#define FMC_SR2_IFEN 0x20U /*!<Interrupt Falling Edge detection Enable bit */
+#define FMC_SR2_FEMPT 0x40U /*!<FIFO empty */
+
+/******************* Bit definition for FMC_SR3 register *******************/
+#define FMC_SR3_IRS 0x01U /*!<Interrupt Rising Edge status */
+#define FMC_SR3_ILS 0x02U /*!<Interrupt Level status */
+#define FMC_SR3_IFS 0x04U /*!<Interrupt Falling Edge status */
+#define FMC_SR3_IREN 0x08U /*!<Interrupt Rising Edge detection Enable bit */
+#define FMC_SR3_ILEN 0x10U /*!<Interrupt Level detection Enable bit */
+#define FMC_SR3_IFEN 0x20U /*!<Interrupt Falling Edge detection Enable bit */
+#define FMC_SR3_FEMPT 0x40U /*!<FIFO empty */
+
+/******************* Bit definition for FMC_SR4 register *******************/
+#define FMC_SR4_IRS 0x01U /*!<Interrupt Rising Edge status */
+#define FMC_SR4_ILS 0x02U /*!<Interrupt Level status */
+#define FMC_SR4_IFS 0x04U /*!<Interrupt Falling Edge status */
+#define FMC_SR4_IREN 0x08U /*!<Interrupt Rising Edge detection Enable bit */
+#define FMC_SR4_ILEN 0x10U /*!<Interrupt Level detection Enable bit */
+#define FMC_SR4_IFEN 0x20U /*!<Interrupt Falling Edge detection Enable bit */
+#define FMC_SR4_FEMPT 0x40U /*!<FIFO empty */
+
+/****************** Bit definition for FMC_PMEM2 register ******************/
+#define FMC_PMEM2_MEMSET2 0x000000FFU /*!<MEMSET2[7:0] bits (Common memory 2 setup time) */
+#define FMC_PMEM2_MEMSET2_0 0x00000001U /*!<Bit 0 */
+#define FMC_PMEM2_MEMSET2_1 0x00000002U /*!<Bit 1 */
+#define FMC_PMEM2_MEMSET2_2 0x00000004U /*!<Bit 2 */
+#define FMC_PMEM2_MEMSET2_3 0x00000008U /*!<Bit 3 */
+#define FMC_PMEM2_MEMSET2_4 0x00000010U /*!<Bit 4 */
+#define FMC_PMEM2_MEMSET2_5 0x00000020U /*!<Bit 5 */
+#define FMC_PMEM2_MEMSET2_6 0x00000040U /*!<Bit 6 */
+#define FMC_PMEM2_MEMSET2_7 0x00000080U /*!<Bit 7 */
+
+#define FMC_PMEM2_MEMWAIT2 0x0000FF00U /*!<MEMWAIT2[7:0] bits (Common memory 2 wait time) */
+#define FMC_PMEM2_MEMWAIT2_0 0x00000100U /*!<Bit 0 */
+#define FMC_PMEM2_MEMWAIT2_1 0x00000200U /*!<Bit 1 */
+#define FMC_PMEM2_MEMWAIT2_2 0x00000400U /*!<Bit 2 */
+#define FMC_PMEM2_MEMWAIT2_3 0x00000800U /*!<Bit 3 */
+#define FMC_PMEM2_MEMWAIT2_4 0x00001000U /*!<Bit 4 */
+#define FMC_PMEM2_MEMWAIT2_5 0x00002000U /*!<Bit 5 */
+#define FMC_PMEM2_MEMWAIT2_6 0x00004000U /*!<Bit 6 */
+#define FMC_PMEM2_MEMWAIT2_7 0x00008000U /*!<Bit 7 */
+
+#define FMC_PMEM2_MEMHOLD2 0x00FF0000U /*!<MEMHOLD2[7:0] bits (Common memory 2 hold time) */
+#define FMC_PMEM2_MEMHOLD2_0 0x00010000U /*!<Bit 0 */
+#define FMC_PMEM2_MEMHOLD2_1 0x00020000U /*!<Bit 1 */
+#define FMC_PMEM2_MEMHOLD2_2 0x00040000U /*!<Bit 2 */
+#define FMC_PMEM2_MEMHOLD2_3 0x00080000U /*!<Bit 3 */
+#define FMC_PMEM2_MEMHOLD2_4 0x00100000U /*!<Bit 4 */
+#define FMC_PMEM2_MEMHOLD2_5 0x00200000U /*!<Bit 5 */
+#define FMC_PMEM2_MEMHOLD2_6 0x00400000U /*!<Bit 6 */
+#define FMC_PMEM2_MEMHOLD2_7 0x00800000U /*!<Bit 7 */
+
+#define FMC_PMEM2_MEMHIZ2 0xFF000000U /*!<MEMHIZ2[7:0] bits (Common memory 2 databus HiZ time) */
+#define FMC_PMEM2_MEMHIZ2_0 0x01000000U /*!<Bit 0 */
+#define FMC_PMEM2_MEMHIZ2_1 0x02000000U /*!<Bit 1 */
+#define FMC_PMEM2_MEMHIZ2_2 0x04000000U /*!<Bit 2 */
+#define FMC_PMEM2_MEMHIZ2_3 0x08000000U /*!<Bit 3 */
+#define FMC_PMEM2_MEMHIZ2_4 0x10000000U /*!<Bit 4 */
+#define FMC_PMEM2_MEMHIZ2_5 0x20000000U /*!<Bit 5 */
+#define FMC_PMEM2_MEMHIZ2_6 0x40000000U /*!<Bit 6 */
+#define FMC_PMEM2_MEMHIZ2_7 0x80000000U /*!<Bit 7 */
+
+/****************** Bit definition for FMC_PMEM3 register ******************/
+#define FMC_PMEM3_MEMSET3 0x000000FFU /*!<MEMSET3[7:0] bits (Common memory 3 setup time) */
+#define FMC_PMEM3_MEMSET3_0 0x00000001U /*!<Bit 0 */
+#define FMC_PMEM3_MEMSET3_1 0x00000002U /*!<Bit 1 */
+#define FMC_PMEM3_MEMSET3_2 0x00000004U /*!<Bit 2 */
+#define FMC_PMEM3_MEMSET3_3 0x00000008U /*!<Bit 3 */
+#define FMC_PMEM3_MEMSET3_4 0x00000010U /*!<Bit 4 */
+#define FMC_PMEM3_MEMSET3_5 0x00000020U /*!<Bit 5 */
+#define FMC_PMEM3_MEMSET3_6 0x00000040U /*!<Bit 6 */
+#define FMC_PMEM3_MEMSET3_7 0x00000080U /*!<Bit 7 */
+
+#define FMC_PMEM3_MEMWAIT3 0x0000FF00U /*!<MEMWAIT3[7:0] bits (Common memory 3 wait time) */
+#define FMC_PMEM3_MEMWAIT3_0 0x00000100U /*!<Bit 0 */
+#define FMC_PMEM3_MEMWAIT3_1 0x00000200U /*!<Bit 1 */
+#define FMC_PMEM3_MEMWAIT3_2 0x00000400U /*!<Bit 2 */
+#define FMC_PMEM3_MEMWAIT3_3 0x00000800U /*!<Bit 3 */
+#define FMC_PMEM3_MEMWAIT3_4 0x00001000U /*!<Bit 4 */
+#define FMC_PMEM3_MEMWAIT3_5 0x00002000U /*!<Bit 5 */
+#define FMC_PMEM3_MEMWAIT3_6 0x00004000U /*!<Bit 6 */
+#define FMC_PMEM3_MEMWAIT3_7 0x00008000U /*!<Bit 7 */
+
+#define FMC_PMEM3_MEMHOLD3 0x00FF0000U /*!<MEMHOLD3[7:0] bits (Common memory 3 hold time) */
+#define FMC_PMEM3_MEMHOLD3_0 0x00010000U /*!<Bit 0 */
+#define FMC_PMEM3_MEMHOLD3_1 0x00020000U /*!<Bit 1 */
+#define FMC_PMEM3_MEMHOLD3_2 0x00040000U /*!<Bit 2 */
+#define FMC_PMEM3_MEMHOLD3_3 0x00080000U /*!<Bit 3 */
+#define FMC_PMEM3_MEMHOLD3_4 0x00100000U /*!<Bit 4 */
+#define FMC_PMEM3_MEMHOLD3_5 0x00200000U /*!<Bit 5 */
+#define FMC_PMEM3_MEMHOLD3_6 0x00400000U /*!<Bit 6 */
+#define FMC_PMEM3_MEMHOLD3_7 0x00800000U /*!<Bit 7 */
+
+#define FMC_PMEM3_MEMHIZ3 0xFF000000U /*!<MEMHIZ3[7:0] bits (Common memory 3 databus HiZ time) */
+#define FMC_PMEM3_MEMHIZ3_0 0x01000000U /*!<Bit 0 */
+#define FMC_PMEM3_MEMHIZ3_1 0x02000000U /*!<Bit 1 */
+#define FMC_PMEM3_MEMHIZ3_2 0x04000000U /*!<Bit 2 */
+#define FMC_PMEM3_MEMHIZ3_3 0x08000000U /*!<Bit 3 */
+#define FMC_PMEM3_MEMHIZ3_4 0x10000000U /*!<Bit 4 */
+#define FMC_PMEM3_MEMHIZ3_5 0x20000000U /*!<Bit 5 */
+#define FMC_PMEM3_MEMHIZ3_6 0x40000000U /*!<Bit 6 */
+#define FMC_PMEM3_MEMHIZ3_7 0x80000000U /*!<Bit 7 */
+
+/****************** Bit definition for FMC_PMEM4 register ******************/
+#define FMC_PMEM4_MEMSET4 0x000000FFU /*!<MEMSET4[7:0] bits (Common memory 4 setup time) */
+#define FMC_PMEM4_MEMSET4_0 0x00000001U /*!<Bit 0 */
+#define FMC_PMEM4_MEMSET4_1 0x00000002U /*!<Bit 1 */
+#define FMC_PMEM4_MEMSET4_2 0x00000004U /*!<Bit 2 */
+#define FMC_PMEM4_MEMSET4_3 0x00000008U /*!<Bit 3 */
+#define FMC_PMEM4_MEMSET4_4 0x00000010U /*!<Bit 4 */
+#define FMC_PMEM4_MEMSET4_5 0x00000020U /*!<Bit 5 */
+#define FMC_PMEM4_MEMSET4_6 0x00000040U /*!<Bit 6 */
+#define FMC_PMEM4_MEMSET4_7 0x00000080U /*!<Bit 7 */
+
+#define FMC_PMEM4_MEMWAIT4 0x0000FF00U /*!<MEMWAIT4[7:0] bits (Common memory 4 wait time) */
+#define FMC_PMEM4_MEMWAIT4_0 0x00000100U /*!<Bit 0 */
+#define FMC_PMEM4_MEMWAIT4_1 0x00000200U /*!<Bit 1 */
+#define FMC_PMEM4_MEMWAIT4_2 0x00000400U /*!<Bit 2 */
+#define FMC_PMEM4_MEMWAIT4_3 0x00000800U /*!<Bit 3 */
+#define FMC_PMEM4_MEMWAIT4_4 0x00001000U /*!<Bit 4 */
+#define FMC_PMEM4_MEMWAIT4_5 0x00002000U /*!<Bit 5 */
+#define FMC_PMEM4_MEMWAIT4_6 0x00004000U /*!<Bit 6 */
+#define FMC_PMEM4_MEMWAIT4_7 0x00008000U /*!<Bit 7 */
+
+#define FMC_PMEM4_MEMHOLD4 0x00FF0000U /*!<MEMHOLD4[7:0] bits (Common memory 4 hold time) */
+#define FMC_PMEM4_MEMHOLD4_0 0x00010000U /*!<Bit 0 */
+#define FMC_PMEM4_MEMHOLD4_1 0x00020000U /*!<Bit 1 */
+#define FMC_PMEM4_MEMHOLD4_2 0x00040000U /*!<Bit 2 */
+#define FMC_PMEM4_MEMHOLD4_3 0x00080000U /*!<Bit 3 */
+#define FMC_PMEM4_MEMHOLD4_4 0x00100000U /*!<Bit 4 */
+#define FMC_PMEM4_MEMHOLD4_5 0x00200000U /*!<Bit 5 */
+#define FMC_PMEM4_MEMHOLD4_6 0x00400000U /*!<Bit 6 */
+#define FMC_PMEM4_MEMHOLD4_7 0x00800000U /*!<Bit 7 */
+
+#define FMC_PMEM4_MEMHIZ4 0xFF000000U /*!<MEMHIZ4[7:0] bits (Common memory 4 databus HiZ time) */
+#define FMC_PMEM4_MEMHIZ4_0 0x01000000U /*!<Bit 0 */
+#define FMC_PMEM4_MEMHIZ4_1 0x02000000U /*!<Bit 1 */
+#define FMC_PMEM4_MEMHIZ4_2 0x04000000U /*!<Bit 2 */
+#define FMC_PMEM4_MEMHIZ4_3 0x08000000U /*!<Bit 3 */
+#define FMC_PMEM4_MEMHIZ4_4 0x10000000U /*!<Bit 4 */
+#define FMC_PMEM4_MEMHIZ4_5 0x20000000U /*!<Bit 5 */
+#define FMC_PMEM4_MEMHIZ4_6 0x40000000U /*!<Bit 6 */
+#define FMC_PMEM4_MEMHIZ4_7 0x80000000U /*!<Bit 7 */
+
+/****************** Bit definition for FMC_PATT2 register ******************/
+#define FMC_PATT2_ATTSET2 0x000000FFU /*!<ATTSET2[7:0] bits (Attribute memory 2 setup time) */
+#define FMC_PATT2_ATTSET2_0 0x00000001U /*!<Bit 0 */
+#define FMC_PATT2_ATTSET2_1 0x00000002U /*!<Bit 1 */
+#define FMC_PATT2_ATTSET2_2 0x00000004U /*!<Bit 2 */
+#define FMC_PATT2_ATTSET2_3 0x00000008U /*!<Bit 3 */
+#define FMC_PATT2_ATTSET2_4 0x00000010U /*!<Bit 4 */
+#define FMC_PATT2_ATTSET2_5 0x00000020U /*!<Bit 5 */
+#define FMC_PATT2_ATTSET2_6 0x00000040U /*!<Bit 6 */
+#define FMC_PATT2_ATTSET2_7 0x00000080U /*!<Bit 7 */
+
+#define FMC_PATT2_ATTWAIT2 0x0000FF00U /*!<ATTWAIT2[7:0] bits (Attribute memory 2 wait time) */
+#define FMC_PATT2_ATTWAIT2_0 0x00000100U /*!<Bit 0 */
+#define FMC_PATT2_ATTWAIT2_1 0x00000200U /*!<Bit 1 */
+#define FMC_PATT2_ATTWAIT2_2 0x00000400U /*!<Bit 2 */
+#define FMC_PATT2_ATTWAIT2_3 0x00000800U /*!<Bit 3 */
+#define FMC_PATT2_ATTWAIT2_4 0x00001000U /*!<Bit 4 */
+#define FMC_PATT2_ATTWAIT2_5 0x00002000U /*!<Bit 5 */
+#define FMC_PATT2_ATTWAIT2_6 0x00004000U /*!<Bit 6 */
+#define FMC_PATT2_ATTWAIT2_7 0x00008000U /*!<Bit 7 */
+
+#define FMC_PATT2_ATTHOLD2 0x00FF0000U /*!<ATTHOLD2[7:0] bits (Attribute memory 2 hold time) */
+#define FMC_PATT2_ATTHOLD2_0 0x00010000U /*!<Bit 0 */
+#define FMC_PATT2_ATTHOLD2_1 0x00020000U /*!<Bit 1 */
+#define FMC_PATT2_ATTHOLD2_2 0x00040000U /*!<Bit 2 */
+#define FMC_PATT2_ATTHOLD2_3 0x00080000U /*!<Bit 3 */
+#define FMC_PATT2_ATTHOLD2_4 0x00100000U /*!<Bit 4 */
+#define FMC_PATT2_ATTHOLD2_5 0x00200000U /*!<Bit 5 */
+#define FMC_PATT2_ATTHOLD2_6 0x00400000U /*!<Bit 6 */
+#define FMC_PATT2_ATTHOLD2_7 0x00800000U /*!<Bit 7 */
+
+#define FMC_PATT2_ATTHIZ2 0xFF000000U /*!<ATTHIZ2[7:0] bits (Attribute memory 2 databus HiZ time) */
+#define FMC_PATT2_ATTHIZ2_0 0x01000000U /*!<Bit 0 */
+#define FMC_PATT2_ATTHIZ2_1 0x02000000U /*!<Bit 1 */
+#define FMC_PATT2_ATTHIZ2_2 0x04000000U /*!<Bit 2 */
+#define FMC_PATT2_ATTHIZ2_3 0x08000000U /*!<Bit 3 */
+#define FMC_PATT2_ATTHIZ2_4 0x10000000U /*!<Bit 4 */
+#define FMC_PATT2_ATTHIZ2_5 0x20000000U /*!<Bit 5 */
+#define FMC_PATT2_ATTHIZ2_6 0x40000000U /*!<Bit 6 */
+#define FMC_PATT2_ATTHIZ2_7 0x80000000U /*!<Bit 7 */
+
+/****************** Bit definition for FMC_PATT3 register ******************/
+#define FMC_PATT3_ATTSET3 0x000000FFU /*!<ATTSET3[7:0] bits (Attribute memory 3 setup time) */
+#define FMC_PATT3_ATTSET3_0 0x00000001U /*!<Bit 0 */
+#define FMC_PATT3_ATTSET3_1 0x00000002U /*!<Bit 1 */
+#define FMC_PATT3_ATTSET3_2 0x00000004U /*!<Bit 2 */
+#define FMC_PATT3_ATTSET3_3 0x00000008U /*!<Bit 3 */
+#define FMC_PATT3_ATTSET3_4 0x00000010U /*!<Bit 4 */
+#define FMC_PATT3_ATTSET3_5 0x00000020U /*!<Bit 5 */
+#define FMC_PATT3_ATTSET3_6 0x00000040U /*!<Bit 6 */
+#define FMC_PATT3_ATTSET3_7 0x00000080U /*!<Bit 7 */
+
+#define FMC_PATT3_ATTWAIT3 0x0000FF00U /*!<ATTWAIT3[7:0] bits (Attribute memory 3 wait time) */
+#define FMC_PATT3_ATTWAIT3_0 0x00000100U /*!<Bit 0 */
+#define FMC_PATT3_ATTWAIT3_1 0x00000200U /*!<Bit 1 */
+#define FMC_PATT3_ATTWAIT3_2 0x00000400U /*!<Bit 2 */
+#define FMC_PATT3_ATTWAIT3_3 0x00000800U /*!<Bit 3 */
+#define FMC_PATT3_ATTWAIT3_4 0x00001000U /*!<Bit 4 */
+#define FMC_PATT3_ATTWAIT3_5 0x00002000U /*!<Bit 5 */
+#define FMC_PATT3_ATTWAIT3_6 0x00004000U /*!<Bit 6 */
+#define FMC_PATT3_ATTWAIT3_7 0x00008000U /*!<Bit 7 */
+
+#define FMC_PATT3_ATTHOLD3 0x00FF0000U /*!<ATTHOLD3[7:0] bits (Attribute memory 3 hold time) */
+#define FMC_PATT3_ATTHOLD3_0 0x00010000U /*!<Bit 0 */
+#define FMC_PATT3_ATTHOLD3_1 0x00020000U /*!<Bit 1 */
+#define FMC_PATT3_ATTHOLD3_2 0x00040000U /*!<Bit 2 */
+#define FMC_PATT3_ATTHOLD3_3 0x00080000U /*!<Bit 3 */
+#define FMC_PATT3_ATTHOLD3_4 0x00100000U /*!<Bit 4 */
+#define FMC_PATT3_ATTHOLD3_5 0x00200000U /*!<Bit 5 */
+#define FMC_PATT3_ATTHOLD3_6 0x00400000U /*!<Bit 6 */
+#define FMC_PATT3_ATTHOLD3_7 0x00800000U /*!<Bit 7 */
+
+#define FMC_PATT3_ATTHIZ3 0xFF000000U /*!<ATTHIZ3[7:0] bits (Attribute memory 3 databus HiZ time) */
+#define FMC_PATT3_ATTHIZ3_0 0x01000000U /*!<Bit 0 */
+#define FMC_PATT3_ATTHIZ3_1 0x02000000U /*!<Bit 1 */
+#define FMC_PATT3_ATTHIZ3_2 0x04000000U /*!<Bit 2 */
+#define FMC_PATT3_ATTHIZ3_3 0x08000000U /*!<Bit 3 */
+#define FMC_PATT3_ATTHIZ3_4 0x10000000U /*!<Bit 4 */
+#define FMC_PATT3_ATTHIZ3_5 0x20000000U /*!<Bit 5 */
+#define FMC_PATT3_ATTHIZ3_6 0x40000000U /*!<Bit 6 */
+#define FMC_PATT3_ATTHIZ3_7 0x80000000U /*!<Bit 7 */
+
+/****************** Bit definition for FMC_PATT4 register ******************/
+#define FMC_PATT4_ATTSET4 0x000000FFU /*!<ATTSET4[7:0] bits (Attribute memory 4 setup time) */
+#define FMC_PATT4_ATTSET4_0 0x00000001U /*!<Bit 0 */
+#define FMC_PATT4_ATTSET4_1 0x00000002U /*!<Bit 1 */
+#define FMC_PATT4_ATTSET4_2 0x00000004U /*!<Bit 2 */
+#define FMC_PATT4_ATTSET4_3 0x00000008U /*!<Bit 3 */
+#define FMC_PATT4_ATTSET4_4 0x00000010U /*!<Bit 4 */
+#define FMC_PATT4_ATTSET4_5 0x00000020U /*!<Bit 5 */
+#define FMC_PATT4_ATTSET4_6 0x00000040U /*!<Bit 6 */
+#define FMC_PATT4_ATTSET4_7 0x00000080U /*!<Bit 7 */
+
+#define FMC_PATT4_ATTWAIT4 0x0000FF00U /*!<ATTWAIT4[7:0] bits (Attribute memory 4 wait time) */
+#define FMC_PATT4_ATTWAIT4_0 0x00000100U /*!<Bit 0 */
+#define FMC_PATT4_ATTWAIT4_1 0x00000200U /*!<Bit 1 */
+#define FMC_PATT4_ATTWAIT4_2 0x00000400U /*!<Bit 2 */
+#define FMC_PATT4_ATTWAIT4_3 0x00000800U /*!<Bit 3 */
+#define FMC_PATT4_ATTWAIT4_4 0x00001000U /*!<Bit 4 */
+#define FMC_PATT4_ATTWAIT4_5 0x00002000U /*!<Bit 5 */
+#define FMC_PATT4_ATTWAIT4_6 0x00004000U /*!<Bit 6 */
+#define FMC_PATT4_ATTWAIT4_7 0x00008000U /*!<Bit 7 */
+
+#define FMC_PATT4_ATTHOLD4 0x00FF0000U /*!<ATTHOLD4[7:0] bits (Attribute memory 4 hold time) */
+#define FMC_PATT4_ATTHOLD4_0 0x00010000U /*!<Bit 0 */
+#define FMC_PATT4_ATTHOLD4_1 0x00020000U /*!<Bit 1 */
+#define FMC_PATT4_ATTHOLD4_2 0x00040000U /*!<Bit 2 */
+#define FMC_PATT4_ATTHOLD4_3 0x00080000U /*!<Bit 3 */
+#define FMC_PATT4_ATTHOLD4_4 0x00100000U /*!<Bit 4 */
+#define FMC_PATT4_ATTHOLD4_5 0x00200000U /*!<Bit 5 */
+#define FMC_PATT4_ATTHOLD4_6 0x00400000U /*!<Bit 6 */
+#define FMC_PATT4_ATTHOLD4_7 0x00800000U /*!<Bit 7 */
+
+#define FMC_PATT4_ATTHIZ4 0xFF000000U /*!<ATTHIZ4[7:0] bits (Attribute memory 4 databus HiZ time) */
+#define FMC_PATT4_ATTHIZ4_0 0x01000000U /*!<Bit 0 */
+#define FMC_PATT4_ATTHIZ4_1 0x02000000U /*!<Bit 1 */
+#define FMC_PATT4_ATTHIZ4_2 0x04000000U /*!<Bit 2 */
+#define FMC_PATT4_ATTHIZ4_3 0x08000000U /*!<Bit 3 */
+#define FMC_PATT4_ATTHIZ4_4 0x10000000U /*!<Bit 4 */
+#define FMC_PATT4_ATTHIZ4_5 0x20000000U /*!<Bit 5 */
+#define FMC_PATT4_ATTHIZ4_6 0x40000000U /*!<Bit 6 */
+#define FMC_PATT4_ATTHIZ4_7 0x80000000U /*!<Bit 7 */
+
+/****************** Bit definition for FMC_PIO4 register *******************/
+#define FMC_PIO4_IOSET4 0x000000FFU /*!<IOSET4[7:0] bits (I/O 4 setup time) */
+#define FMC_PIO4_IOSET4_0 0x00000001U /*!<Bit 0 */
+#define FMC_PIO4_IOSET4_1 0x00000002U /*!<Bit 1 */
+#define FMC_PIO4_IOSET4_2 0x00000004U /*!<Bit 2 */
+#define FMC_PIO4_IOSET4_3 0x00000008U /*!<Bit 3 */
+#define FMC_PIO4_IOSET4_4 0x00000010U /*!<Bit 4 */
+#define FMC_PIO4_IOSET4_5 0x00000020U /*!<Bit 5 */
+#define FMC_PIO4_IOSET4_6 0x00000040U /*!<Bit 6 */
+#define FMC_PIO4_IOSET4_7 0x00000080U /*!<Bit 7 */
+
+#define FMC_PIO4_IOWAIT4 0x0000FF00U /*!<IOWAIT4[7:0] bits (I/O 4 wait time) */
+#define FMC_PIO4_IOWAIT4_0 0x00000100U /*!<Bit 0 */
+#define FMC_PIO4_IOWAIT4_1 0x00000200U /*!<Bit 1 */
+#define FMC_PIO4_IOWAIT4_2 0x00000400U /*!<Bit 2 */
+#define FMC_PIO4_IOWAIT4_3 0x00000800U /*!<Bit 3 */
+#define FMC_PIO4_IOWAIT4_4 0x00001000U /*!<Bit 4 */
+#define FMC_PIO4_IOWAIT4_5 0x00002000U /*!<Bit 5 */
+#define FMC_PIO4_IOWAIT4_6 0x00004000U /*!<Bit 6 */
+#define FMC_PIO4_IOWAIT4_7 0x00008000U /*!<Bit 7 */
+
+#define FMC_PIO4_IOHOLD4 0x00FF0000U /*!<IOHOLD4[7:0] bits (I/O 4 hold time) */
+#define FMC_PIO4_IOHOLD4_0 0x00010000U /*!<Bit 0 */
+#define FMC_PIO4_IOHOLD4_1 0x00020000U /*!<Bit 1 */
+#define FMC_PIO4_IOHOLD4_2 0x00040000U /*!<Bit 2 */
+#define FMC_PIO4_IOHOLD4_3 0x00080000U /*!<Bit 3 */
+#define FMC_PIO4_IOHOLD4_4 0x00100000U /*!<Bit 4 */
+#define FMC_PIO4_IOHOLD4_5 0x00200000U /*!<Bit 5 */
+#define FMC_PIO4_IOHOLD4_6 0x00400000U /*!<Bit 6 */
+#define FMC_PIO4_IOHOLD4_7 0x00800000U /*!<Bit 7 */
+
+#define FMC_PIO4_IOHIZ4 0xFF000000U /*!<IOHIZ4[7:0] bits (I/O 4 databus HiZ time) */
+#define FMC_PIO4_IOHIZ4_0 0x01000000U /*!<Bit 0 */
+#define FMC_PIO4_IOHIZ4_1 0x02000000U /*!<Bit 1 */
+#define FMC_PIO4_IOHIZ4_2 0x04000000U /*!<Bit 2 */
+#define FMC_PIO4_IOHIZ4_3 0x08000000U /*!<Bit 3 */
+#define FMC_PIO4_IOHIZ4_4 0x10000000U /*!<Bit 4 */
+#define FMC_PIO4_IOHIZ4_5 0x20000000U /*!<Bit 5 */
+#define FMC_PIO4_IOHIZ4_6 0x40000000U /*!<Bit 6 */
+#define FMC_PIO4_IOHIZ4_7 0x80000000U /*!<Bit 7 */
+
+/****************** Bit definition for FMC_ECCR2 register ******************/
+#define FMC_ECCR2_ECC2 0xFFFFFFFFU /*!<ECC result */
+
+/****************** Bit definition for FMC_ECCR3 register ******************/
+#define FMC_ECCR3_ECC3 0xFFFFFFFFU /*!<ECC result */
+
+/****************** Bit definition for FMC_SDCR1 register ******************/
+#define FMC_SDCR1_NC 0x00000003U /*!<NC[1:0] bits (Number of column bits) */
+#define FMC_SDCR1_NC_0 0x00000001U /*!<Bit 0 */
+#define FMC_SDCR1_NC_1 0x00000002U /*!<Bit 1 */
+
+#define FMC_SDCR1_NR 0x0000000CU /*!<NR[1:0] bits (Number of row bits) */
+#define FMC_SDCR1_NR_0 0x00000004U /*!<Bit 0 */
+#define FMC_SDCR1_NR_1 0x00000008U /*!<Bit 1 */
+
+#define FMC_SDCR1_MWID 0x00000030U /*!<NR[1:0] bits (Number of row bits) */
+#define FMC_SDCR1_MWID_0 0x00000010U /*!<Bit 0 */
+#define FMC_SDCR1_MWID_1 0x00000020U /*!<Bit 1 */
+
+#define FMC_SDCR1_NB 0x00000040U /*!<Number of internal bank */
+
+#define FMC_SDCR1_CAS 0x00000180U /*!<CAS[1:0] bits (CAS latency) */
+#define FMC_SDCR1_CAS_0 0x00000080U /*!<Bit 0 */
+#define FMC_SDCR1_CAS_1 0x00000100U /*!<Bit 1 */
+
+#define FMC_SDCR1_WP 0x00000200U /*!<Write protection */
+
+#define FMC_SDCR1_SDCLK 0x00000C00U /*!<SDRAM clock configuration */
+#define FMC_SDCR1_SDCLK_0 0x00000400U /*!<Bit 0 */
+#define FMC_SDCR1_SDCLK_1 0x00000800U /*!<Bit 1 */
+
+#define FMC_SDCR1_RBURST 0x00001000U /*!<Read burst */
+
+#define FMC_SDCR1_RPIPE 0x00006000U /*!<Write protection */
+#define FMC_SDCR1_RPIPE_0 0x00002000U /*!<Bit 0 */
+#define FMC_SDCR1_RPIPE_1 0x00004000U /*!<Bit 1 */
+
+/****************** Bit definition for FMC_SDCR2 register ******************/
+#define FMC_SDCR2_NC 0x00000003U /*!<NC[1:0] bits (Number of column bits) */
+#define FMC_SDCR2_NC_0 0x00000001U /*!<Bit 0 */
+#define FMC_SDCR2_NC_1 0x00000002U /*!<Bit 1 */
+
+#define FMC_SDCR2_NR 0x0000000CU /*!<NR[1:0] bits (Number of row bits) */
+#define FMC_SDCR2_NR_0 0x00000004U /*!<Bit 0 */
+#define FMC_SDCR2_NR_1 0x00000008U /*!<Bit 1 */
+
+#define FMC_SDCR2_MWID 0x00000030U /*!<NR[1:0] bits (Number of row bits) */
+#define FMC_SDCR2_MWID_0 0x00000010U /*!<Bit 0 */
+#define FMC_SDCR2_MWID_1 0x00000020U /*!<Bit 1 */
+
+#define FMC_SDCR2_NB 0x00000040U /*!<Number of internal bank */
+
+#define FMC_SDCR2_CAS 0x00000180U /*!<CAS[1:0] bits (CAS latency) */
+#define FMC_SDCR2_CAS_0 0x00000080U /*!<Bit 0 */
+#define FMC_SDCR2_CAS_1 0x00000100U /*!<Bit 1 */
+
+#define FMC_SDCR2_WP 0x00000200U /*!<Write protection */
+
+#define FMC_SDCR2_SDCLK 0x00000C00U /*!<SDCLK[1:0] (SDRAM clock configuration) */
+#define FMC_SDCR2_SDCLK_0 0x00000400U /*!<Bit 0 */
+#define FMC_SDCR2_SDCLK_1 0x00000800U /*!<Bit 1 */
+
+#define FMC_SDCR2_RBURST 0x00001000U /*!<Read burst */
+
+#define FMC_SDCR2_RPIPE 0x00006000U /*!<RPIPE[1:0](Read pipe) */
+#define FMC_SDCR2_RPIPE_0 0x00002000U /*!<Bit 0 */
+#define FMC_SDCR2_RPIPE_1 0x00004000U /*!<Bit 1 */
+
+/****************** Bit definition for FMC_SDTR1 register ******************/
+#define FMC_SDTR1_TMRD 0x0000000FU /*!<TMRD[3:0] bits (Load mode register to active) */
+#define FMC_SDTR1_TMRD_0 0x00000001U /*!<Bit 0 */
+#define FMC_SDTR1_TMRD_1 0x00000002U /*!<Bit 1 */
+#define FMC_SDTR1_TMRD_2 0x00000004U /*!<Bit 2 */
+#define FMC_SDTR1_TMRD_3 0x00000008U /*!<Bit 3 */
+
+#define FMC_SDTR1_TXSR 0x000000F0U /*!<TXSR[3:0] bits (Exit self refresh) */
+#define FMC_SDTR1_TXSR_0 0x00000010U /*!<Bit 0 */
+#define FMC_SDTR1_TXSR_1 0x00000020U /*!<Bit 1 */
+#define FMC_SDTR1_TXSR_2 0x00000040U /*!<Bit 2 */
+#define FMC_SDTR1_TXSR_3 0x00000080U /*!<Bit 3 */
+
+#define FMC_SDTR1_TRAS 0x00000F00U /*!<TRAS[3:0] bits (Self refresh time) */
+#define FMC_SDTR1_TRAS_0 0x00000100U /*!<Bit 0 */
+#define FMC_SDTR1_TRAS_1 0x00000200U /*!<Bit 1 */
+#define FMC_SDTR1_TRAS_2 0x00000400U /*!<Bit 2 */
+#define FMC_SDTR1_TRAS_3 0x00000800U /*!<Bit 3 */
+
+#define FMC_SDTR1_TRC 0x0000F000U /*!<TRC[2:0] bits (Row cycle delay) */
+#define FMC_SDTR1_TRC_0 0x00001000U /*!<Bit 0 */
+#define FMC_SDTR1_TRC_1 0x00002000U /*!<Bit 1 */
+#define FMC_SDTR1_TRC_2 0x00004000U /*!<Bit 2 */
+
+#define FMC_SDTR1_TWR 0x000F0000U /*!<TRC[2:0] bits (Write recovery delay) */
+#define FMC_SDTR1_TWR_0 0x00010000U /*!<Bit 0 */
+#define FMC_SDTR1_TWR_1 0x00020000U /*!<Bit 1 */
+#define FMC_SDTR1_TWR_2 0x00040000U /*!<Bit 2 */
+
+#define FMC_SDTR1_TRP 0x00F00000U /*!<TRP[2:0] bits (Row precharge delay) */
+#define FMC_SDTR1_TRP_0 0x00100000U /*!<Bit 0 */
+#define FMC_SDTR1_TRP_1 0x00200000U /*!<Bit 1 */
+#define FMC_SDTR1_TRP_2 0x00400000U /*!<Bit 2 */
+
+#define FMC_SDTR1_TRCD 0x0F000000U /*!<TRP[2:0] bits (Row to column delay) */
+#define FMC_SDTR1_TRCD_0 0x01000000U /*!<Bit 0 */
+#define FMC_SDTR1_TRCD_1 0x02000000U /*!<Bit 1 */
+#define FMC_SDTR1_TRCD_2 0x04000000U /*!<Bit 2 */
+
+/****************** Bit definition for FMC_SDTR2 register ******************/
+#define FMC_SDTR2_TMRD 0x0000000FU /*!<TMRD[3:0] bits (Load mode register to active) */
+#define FMC_SDTR2_TMRD_0 0x00000001U /*!<Bit 0 */
+#define FMC_SDTR2_TMRD_1 0x00000002U /*!<Bit 1 */
+#define FMC_SDTR2_TMRD_2 0x00000004U /*!<Bit 2 */
+#define FMC_SDTR2_TMRD_3 0x00000008U /*!<Bit 3 */
+
+#define FMC_SDTR2_TXSR 0x000000F0U /*!<TXSR[3:0] bits (Exit self refresh) */
+#define FMC_SDTR2_TXSR_0 0x00000010U /*!<Bit 0 */
+#define FMC_SDTR2_TXSR_1 0x00000020U /*!<Bit 1 */
+#define FMC_SDTR2_TXSR_2 0x00000040U /*!<Bit 2 */
+#define FMC_SDTR2_TXSR_3 0x00000080U /*!<Bit 3 */
+
+#define FMC_SDTR2_TRAS 0x00000F00U /*!<TRAS[3:0] bits (Self refresh time) */
+#define FMC_SDTR2_TRAS_0 0x00000100U /*!<Bit 0 */
+#define FMC_SDTR2_TRAS_1 0x00000200U /*!<Bit 1 */
+#define FMC_SDTR2_TRAS_2 0x00000400U /*!<Bit 2 */
+#define FMC_SDTR2_TRAS_3 0x00000800U /*!<Bit 3 */
+
+#define FMC_SDTR2_TRC 0x0000F000U /*!<TRC[2:0] bits (Row cycle delay) */
+#define FMC_SDTR2_TRC_0 0x00001000U /*!<Bit 0 */
+#define FMC_SDTR2_TRC_1 0x00002000U /*!<Bit 1 */
+#define FMC_SDTR2_TRC_2 0x00004000U /*!<Bit 2 */
+
+#define FMC_SDTR2_TWR 0x000F0000U /*!<TRC[2:0] bits (Write recovery delay) */
+#define FMC_SDTR2_TWR_0 0x00010000U /*!<Bit 0 */
+#define FMC_SDTR2_TWR_1 0x00020000U /*!<Bit 1 */
+#define FMC_SDTR2_TWR_2 0x00040000U /*!<Bit 2 */
+
+#define FMC_SDTR2_TRP 0x00F00000U /*!<TRP[2:0] bits (Row precharge delay) */
+#define FMC_SDTR2_TRP_0 0x00100000U /*!<Bit 0 */
+#define FMC_SDTR2_TRP_1 0x00200000U /*!<Bit 1 */
+#define FMC_SDTR2_TRP_2 0x00400000U /*!<Bit 2 */
+
+#define FMC_SDTR2_TRCD 0x0F000000U /*!<TRP[2:0] bits (Row to column delay) */
+#define FMC_SDTR2_TRCD_0 0x01000000U /*!<Bit 0 */
+#define FMC_SDTR2_TRCD_1 0x02000000U /*!<Bit 1 */
+#define FMC_SDTR2_TRCD_2 0x04000000U /*!<Bit 2 */
+
+/****************** Bit definition for FMC_SDCMR register ******************/
+#define FMC_SDCMR_MODE 0x00000007U /*!<MODE[2:0] bits (Command mode) */
+#define FMC_SDCMR_MODE_0 0x00000001U /*!<Bit 0 */
+#define FMC_SDCMR_MODE_1 0x00000002U /*!<Bit 1 */
+#define FMC_SDCMR_MODE_2 0x00000004U /*!<Bit 2 */
+
+#define FMC_SDCMR_CTB2 0x00000008U /*!<Command target 2 */
+
+#define FMC_SDCMR_CTB1 0x00000010U /*!<Command target 1 */
+
+#define FMC_SDCMR_NRFS 0x000001E0U /*!<NRFS[3:0] bits (Number of auto-refresh) */
+#define FMC_SDCMR_NRFS_0 0x00000020U /*!<Bit 0 */
+#define FMC_SDCMR_NRFS_1 0x00000040U /*!<Bit 1 */
+#define FMC_SDCMR_NRFS_2 0x00000080U /*!<Bit 2 */
+#define FMC_SDCMR_NRFS_3 0x00000100U /*!<Bit 3 */
+
+#define FMC_SDCMR_MRD 0x003FFE00U /*!<MRD[12:0] bits (Mode register definition) */
+
+/****************** Bit definition for FMC_SDRTR register ******************/
+#define FMC_SDRTR_CRE 0x00000001U /*!<Clear refresh error flag */
+
+#define FMC_SDRTR_COUNT 0x00003FFEU /*!<COUNT[12:0] bits (Refresh timer count) */
+
+#define FMC_SDRTR_REIE 0x00004000U /*!<RES interupt enable */
+
+/****************** Bit definition for FMC_SDSR register ******************/
+#define FMC_SDSR_RE 0x00000001U /*!<Refresh error flag */
+
+#define FMC_SDSR_MODES1 0x00000006U /*!<MODES1[1:0]bits (Status mode for bank 1) */
+#define FMC_SDSR_MODES1_0 0x00000002U /*!<Bit 0 */
+#define FMC_SDSR_MODES1_1 0x00000004U /*!<Bit 1 */
+
+#define FMC_SDSR_MODES2 0x00000018U /*!<MODES2[1:0]bits (Status mode for bank 2) */
+#define FMC_SDSR_MODES2_0 0x00000008U /*!<Bit 0 */
+#define FMC_SDSR_MODES2_1 0x00000010U /*!<Bit 1 */
+#define FMC_SDSR_BUSY 0x00000020U /*!<Busy status */
+
+
+
+/******************************************************************************/
+/* */
+/* General Purpose I/O */
+/* */
+/******************************************************************************/
+/****************** Bits definition for GPIO_MODER register *****************/
+#define GPIO_MODER_MODER0 0x00000003U
+#define GPIO_MODER_MODER0_0 0x00000001U
+#define GPIO_MODER_MODER0_1 0x00000002U
+
+#define GPIO_MODER_MODER1 0x0000000CU
+#define GPIO_MODER_MODER1_0 0x00000004U
+#define GPIO_MODER_MODER1_1 0x00000008U
+
+#define GPIO_MODER_MODER2 0x00000030U
+#define GPIO_MODER_MODER2_0 0x00000010U
+#define GPIO_MODER_MODER2_1 0x00000020U
+
+#define GPIO_MODER_MODER3 0x000000C0U
+#define GPIO_MODER_MODER3_0 0x00000040U
+#define GPIO_MODER_MODER3_1 0x00000080U
+
+#define GPIO_MODER_MODER4 0x00000300U
+#define GPIO_MODER_MODER4_0 0x00000100U
+#define GPIO_MODER_MODER4_1 0x00000200U
+
+#define GPIO_MODER_MODER5 0x00000C00U
+#define GPIO_MODER_MODER5_0 0x00000400U
+#define GPIO_MODER_MODER5_1 0x00000800U
+
+#define GPIO_MODER_MODER6 0x00003000U
+#define GPIO_MODER_MODER6_0 0x00001000U
+#define GPIO_MODER_MODER6_1 0x00002000U
+
+#define GPIO_MODER_MODER7 0x0000C000U
+#define GPIO_MODER_MODER7_0 0x00004000U
+#define GPIO_MODER_MODER7_1 0x00008000U
+
+#define GPIO_MODER_MODER8 0x00030000U
+#define GPIO_MODER_MODER8_0 0x00010000U
+#define GPIO_MODER_MODER8_1 0x00020000U
+
+#define GPIO_MODER_MODER9 0x000C0000U
+#define GPIO_MODER_MODER9_0 0x00040000U
+#define GPIO_MODER_MODER9_1 0x00080000U
+
+#define GPIO_MODER_MODER10 0x00300000U
+#define GPIO_MODER_MODER10_0 0x00100000U
+#define GPIO_MODER_MODER10_1 0x00200000U
+
+#define GPIO_MODER_MODER11 0x00C00000U
+#define GPIO_MODER_MODER11_0 0x00400000U
+#define GPIO_MODER_MODER11_1 0x00800000U
+
+#define GPIO_MODER_MODER12 0x03000000U
+#define GPIO_MODER_MODER12_0 0x01000000U
+#define GPIO_MODER_MODER12_1 0x02000000U
+
+#define GPIO_MODER_MODER13 0x0C000000U
+#define GPIO_MODER_MODER13_0 0x04000000U
+#define GPIO_MODER_MODER13_1 0x08000000U
+
+#define GPIO_MODER_MODER14 0x30000000U
+#define GPIO_MODER_MODER14_0 0x10000000U
+#define GPIO_MODER_MODER14_1 0x20000000U
+
+#define GPIO_MODER_MODER15 0xC0000000U
+#define GPIO_MODER_MODER15_0 0x40000000U
+#define GPIO_MODER_MODER15_1 0x80000000U
+
+/****************** Bits definition for GPIO_OTYPER register ****************/
+#define GPIO_OTYPER_OT_0 0x00000001U
+#define GPIO_OTYPER_OT_1 0x00000002U
+#define GPIO_OTYPER_OT_2 0x00000004U
+#define GPIO_OTYPER_OT_3 0x00000008U
+#define GPIO_OTYPER_OT_4 0x00000010U
+#define GPIO_OTYPER_OT_5 0x00000020U
+#define GPIO_OTYPER_OT_6 0x00000040U
+#define GPIO_OTYPER_OT_7 0x00000080U
+#define GPIO_OTYPER_OT_8 0x00000100U
+#define GPIO_OTYPER_OT_9 0x00000200U
+#define GPIO_OTYPER_OT_10 0x00000400U
+#define GPIO_OTYPER_OT_11 0x00000800U
+#define GPIO_OTYPER_OT_12 0x00001000U
+#define GPIO_OTYPER_OT_13 0x00002000U
+#define GPIO_OTYPER_OT_14 0x00004000U
+#define GPIO_OTYPER_OT_15 0x00008000U
+
+/****************** Bits definition for GPIO_OSPEEDR register ***************/
+#define GPIO_OSPEEDER_OSPEEDR0 0x00000003U
+#define GPIO_OSPEEDER_OSPEEDR0_0 0x00000001U
+#define GPIO_OSPEEDER_OSPEEDR0_1 0x00000002U
+
+#define GPIO_OSPEEDER_OSPEEDR1 0x0000000CU
+#define GPIO_OSPEEDER_OSPEEDR1_0 0x00000004U
+#define GPIO_OSPEEDER_OSPEEDR1_1 0x00000008U
+
+#define GPIO_OSPEEDER_OSPEEDR2 0x00000030U
+#define GPIO_OSPEEDER_OSPEEDR2_0 0x00000010U
+#define GPIO_OSPEEDER_OSPEEDR2_1 0x00000020U
+
+#define GPIO_OSPEEDER_OSPEEDR3 0x000000C0U
+#define GPIO_OSPEEDER_OSPEEDR3_0 0x00000040U
+#define GPIO_OSPEEDER_OSPEEDR3_1 0x00000080U
+
+#define GPIO_OSPEEDER_OSPEEDR4 0x00000300U
+#define GPIO_OSPEEDER_OSPEEDR4_0 0x00000100U
+#define GPIO_OSPEEDER_OSPEEDR4_1 0x00000200U
+
+#define GPIO_OSPEEDER_OSPEEDR5 0x00000C00U
+#define GPIO_OSPEEDER_OSPEEDR5_0 0x00000400U
+#define GPIO_OSPEEDER_OSPEEDR5_1 0x00000800U
+
+#define GPIO_OSPEEDER_OSPEEDR6 0x00003000U
+#define GPIO_OSPEEDER_OSPEEDR6_0 0x00001000U
+#define GPIO_OSPEEDER_OSPEEDR6_1 0x00002000U
+
+#define GPIO_OSPEEDER_OSPEEDR7 0x0000C000U
+#define GPIO_OSPEEDER_OSPEEDR7_0 0x00004000U
+#define GPIO_OSPEEDER_OSPEEDR7_1 0x00008000U
+
+#define GPIO_OSPEEDER_OSPEEDR8 0x00030000U
+#define GPIO_OSPEEDER_OSPEEDR8_0 0x00010000U
+#define GPIO_OSPEEDER_OSPEEDR8_1 0x00020000U
+
+#define GPIO_OSPEEDER_OSPEEDR9 0x000C0000U
+#define GPIO_OSPEEDER_OSPEEDR9_0 0x00040000U
+#define GPIO_OSPEEDER_OSPEEDR9_1 0x00080000U
+
+#define GPIO_OSPEEDER_OSPEEDR10 0x00300000U
+#define GPIO_OSPEEDER_OSPEEDR10_0 0x00100000U
+#define GPIO_OSPEEDER_OSPEEDR10_1 0x00200000U
+
+#define GPIO_OSPEEDER_OSPEEDR11 0x00C00000U
+#define GPIO_OSPEEDER_OSPEEDR11_0 0x00400000U
+#define GPIO_OSPEEDER_OSPEEDR11_1 0x00800000U
+
+#define GPIO_OSPEEDER_OSPEEDR12 0x03000000U
+#define GPIO_OSPEEDER_OSPEEDR12_0 0x01000000U
+#define GPIO_OSPEEDER_OSPEEDR12_1 0x02000000U
+
+#define GPIO_OSPEEDER_OSPEEDR13 0x0C000000U
+#define GPIO_OSPEEDER_OSPEEDR13_0 0x04000000U
+#define GPIO_OSPEEDER_OSPEEDR13_1 0x08000000U
+
+#define GPIO_OSPEEDER_OSPEEDR14 0x30000000U
+#define GPIO_OSPEEDER_OSPEEDR14_0 0x10000000U
+#define GPIO_OSPEEDER_OSPEEDR14_1 0x20000000U
+
+#define GPIO_OSPEEDER_OSPEEDR15 0xC0000000U
+#define GPIO_OSPEEDER_OSPEEDR15_0 0x40000000U
+#define GPIO_OSPEEDER_OSPEEDR15_1 0x80000000U
+
+/****************** Bits definition for GPIO_PUPDR register *****************/
+#define GPIO_PUPDR_PUPDR0 0x00000003U
+#define GPIO_PUPDR_PUPDR0_0 0x00000001U
+#define GPIO_PUPDR_PUPDR0_1 0x00000002U
+
+#define GPIO_PUPDR_PUPDR1 0x0000000CU
+#define GPIO_PUPDR_PUPDR1_0 0x00000004U
+#define GPIO_PUPDR_PUPDR1_1 0x00000008U
+
+#define GPIO_PUPDR_PUPDR2 0x00000030U
+#define GPIO_PUPDR_PUPDR2_0 0x00000010U
+#define GPIO_PUPDR_PUPDR2_1 0x00000020U
+
+#define GPIO_PUPDR_PUPDR3 0x000000C0U
+#define GPIO_PUPDR_PUPDR3_0 0x00000040U
+#define GPIO_PUPDR_PUPDR3_1 0x00000080U
+
+#define GPIO_PUPDR_PUPDR4 0x00000300U
+#define GPIO_PUPDR_PUPDR4_0 0x00000100U
+#define GPIO_PUPDR_PUPDR4_1 0x00000200U
+
+#define GPIO_PUPDR_PUPDR5 0x00000C00U
+#define GPIO_PUPDR_PUPDR5_0 0x00000400U
+#define GPIO_PUPDR_PUPDR5_1 0x00000800U
+
+#define GPIO_PUPDR_PUPDR6 0x00003000U
+#define GPIO_PUPDR_PUPDR6_0 0x00001000U
+#define GPIO_PUPDR_PUPDR6_1 0x00002000U
+
+#define GPIO_PUPDR_PUPDR7 0x0000C000U
+#define GPIO_PUPDR_PUPDR7_0 0x00004000U
+#define GPIO_PUPDR_PUPDR7_1 0x00008000U
+
+#define GPIO_PUPDR_PUPDR8 0x00030000U
+#define GPIO_PUPDR_PUPDR8_0 0x00010000U
+#define GPIO_PUPDR_PUPDR8_1 0x00020000U
+
+#define GPIO_PUPDR_PUPDR9 0x000C0000U
+#define GPIO_PUPDR_PUPDR9_0 0x00040000U
+#define GPIO_PUPDR_PUPDR9_1 0x00080000U
+
+#define GPIO_PUPDR_PUPDR10 0x00300000U
+#define GPIO_PUPDR_PUPDR10_0 0x00100000U
+#define GPIO_PUPDR_PUPDR10_1 0x00200000U
+
+#define GPIO_PUPDR_PUPDR11 0x00C00000U
+#define GPIO_PUPDR_PUPDR11_0 0x00400000U
+#define GPIO_PUPDR_PUPDR11_1 0x00800000U
+
+#define GPIO_PUPDR_PUPDR12 0x03000000U
+#define GPIO_PUPDR_PUPDR12_0 0x01000000U
+#define GPIO_PUPDR_PUPDR12_1 0x02000000U
+
+#define GPIO_PUPDR_PUPDR13 0x0C000000U
+#define GPIO_PUPDR_PUPDR13_0 0x04000000U
+#define GPIO_PUPDR_PUPDR13_1 0x08000000U
+
+#define GPIO_PUPDR_PUPDR14 0x30000000U
+#define GPIO_PUPDR_PUPDR14_0 0x10000000U
+#define GPIO_PUPDR_PUPDR14_1 0x20000000U
+
+#define GPIO_PUPDR_PUPDR15 0xC0000000U
+#define GPIO_PUPDR_PUPDR15_0 0x40000000U
+#define GPIO_PUPDR_PUPDR15_1 0x80000000U
+
+/****************** Bits definition for GPIO_IDR register *******************/
+#define GPIO_IDR_IDR_0 0x00000001U
+#define GPIO_IDR_IDR_1 0x00000002U
+#define GPIO_IDR_IDR_2 0x00000004U
+#define GPIO_IDR_IDR_3 0x00000008U
+#define GPIO_IDR_IDR_4 0x00000010U
+#define GPIO_IDR_IDR_5 0x00000020U
+#define GPIO_IDR_IDR_6 0x00000040U
+#define GPIO_IDR_IDR_7 0x00000080U
+#define GPIO_IDR_IDR_8 0x00000100U
+#define GPIO_IDR_IDR_9 0x00000200U
+#define GPIO_IDR_IDR_10 0x00000400U
+#define GPIO_IDR_IDR_11 0x00000800U
+#define GPIO_IDR_IDR_12 0x00001000U
+#define GPIO_IDR_IDR_13 0x00002000U
+#define GPIO_IDR_IDR_14 0x00004000U
+#define GPIO_IDR_IDR_15 0x00008000U
+/* Old GPIO_IDR register bits definition, maintained for legacy purpose */
+#define GPIO_OTYPER_IDR_0 GPIO_IDR_IDR_0
+#define GPIO_OTYPER_IDR_1 GPIO_IDR_IDR_1
+#define GPIO_OTYPER_IDR_2 GPIO_IDR_IDR_2
+#define GPIO_OTYPER_IDR_3 GPIO_IDR_IDR_3
+#define GPIO_OTYPER_IDR_4 GPIO_IDR_IDR_4
+#define GPIO_OTYPER_IDR_5 GPIO_IDR_IDR_5
+#define GPIO_OTYPER_IDR_6 GPIO_IDR_IDR_6
+#define GPIO_OTYPER_IDR_7 GPIO_IDR_IDR_7
+#define GPIO_OTYPER_IDR_8 GPIO_IDR_IDR_8
+#define GPIO_OTYPER_IDR_9 GPIO_IDR_IDR_9
+#define GPIO_OTYPER_IDR_10 GPIO_IDR_IDR_10
+#define GPIO_OTYPER_IDR_11 GPIO_IDR_IDR_11
+#define GPIO_OTYPER_IDR_12 GPIO_IDR_IDR_12
+#define GPIO_OTYPER_IDR_13 GPIO_IDR_IDR_13
+#define GPIO_OTYPER_IDR_14 GPIO_IDR_IDR_14
+#define GPIO_OTYPER_IDR_15 GPIO_IDR_IDR_15
+
+/****************** Bits definition for GPIO_ODR register *******************/
+#define GPIO_ODR_ODR_0 0x00000001U
+#define GPIO_ODR_ODR_1 0x00000002U
+#define GPIO_ODR_ODR_2 0x00000004U
+#define GPIO_ODR_ODR_3 0x00000008U
+#define GPIO_ODR_ODR_4 0x00000010U
+#define GPIO_ODR_ODR_5 0x00000020U
+#define GPIO_ODR_ODR_6 0x00000040U
+#define GPIO_ODR_ODR_7 0x00000080U
+#define GPIO_ODR_ODR_8 0x00000100U
+#define GPIO_ODR_ODR_9 0x00000200U
+#define GPIO_ODR_ODR_10 0x00000400U
+#define GPIO_ODR_ODR_11 0x00000800U
+#define GPIO_ODR_ODR_12 0x00001000U
+#define GPIO_ODR_ODR_13 0x00002000U
+#define GPIO_ODR_ODR_14 0x00004000U
+#define GPIO_ODR_ODR_15 0x00008000U
+/* Old GPIO_ODR register bits definition, maintained for legacy purpose */
+#define GPIO_OTYPER_ODR_0 GPIO_ODR_ODR_0
+#define GPIO_OTYPER_ODR_1 GPIO_ODR_ODR_1
+#define GPIO_OTYPER_ODR_2 GPIO_ODR_ODR_2
+#define GPIO_OTYPER_ODR_3 GPIO_ODR_ODR_3
+#define GPIO_OTYPER_ODR_4 GPIO_ODR_ODR_4
+#define GPIO_OTYPER_ODR_5 GPIO_ODR_ODR_5
+#define GPIO_OTYPER_ODR_6 GPIO_ODR_ODR_6
+#define GPIO_OTYPER_ODR_7 GPIO_ODR_ODR_7
+#define GPIO_OTYPER_ODR_8 GPIO_ODR_ODR_8
+#define GPIO_OTYPER_ODR_9 GPIO_ODR_ODR_9
+#define GPIO_OTYPER_ODR_10 GPIO_ODR_ODR_10
+#define GPIO_OTYPER_ODR_11 GPIO_ODR_ODR_11
+#define GPIO_OTYPER_ODR_12 GPIO_ODR_ODR_12
+#define GPIO_OTYPER_ODR_13 GPIO_ODR_ODR_13
+#define GPIO_OTYPER_ODR_14 GPIO_ODR_ODR_14
+#define GPIO_OTYPER_ODR_15 GPIO_ODR_ODR_15
+
+/****************** Bits definition for GPIO_BSRR register ******************/
+#define GPIO_BSRR_BS_0 0x00000001U
+#define GPIO_BSRR_BS_1 0x00000002U
+#define GPIO_BSRR_BS_2 0x00000004U
+#define GPIO_BSRR_BS_3 0x00000008U
+#define GPIO_BSRR_BS_4 0x00000010U
+#define GPIO_BSRR_BS_5 0x00000020U
+#define GPIO_BSRR_BS_6 0x00000040U
+#define GPIO_BSRR_BS_7 0x00000080U
+#define GPIO_BSRR_BS_8 0x00000100U
+#define GPIO_BSRR_BS_9 0x00000200U
+#define GPIO_BSRR_BS_10 0x00000400U
+#define GPIO_BSRR_BS_11 0x00000800U
+#define GPIO_BSRR_BS_12 0x00001000U
+#define GPIO_BSRR_BS_13 0x00002000U
+#define GPIO_BSRR_BS_14 0x00004000U
+#define GPIO_BSRR_BS_15 0x00008000U
+#define GPIO_BSRR_BR_0 0x00010000U
+#define GPIO_BSRR_BR_1 0x00020000U
+#define GPIO_BSRR_BR_2 0x00040000U
+#define GPIO_BSRR_BR_3 0x00080000U
+#define GPIO_BSRR_BR_4 0x00100000U
+#define GPIO_BSRR_BR_5 0x00200000U
+#define GPIO_BSRR_BR_6 0x00400000U
+#define GPIO_BSRR_BR_7 0x00800000U
+#define GPIO_BSRR_BR_8 0x01000000U
+#define GPIO_BSRR_BR_9 0x02000000U
+#define GPIO_BSRR_BR_10 0x04000000U
+#define GPIO_BSRR_BR_11 0x08000000U
+#define GPIO_BSRR_BR_12 0x10000000U
+#define GPIO_BSRR_BR_13 0x20000000U
+#define GPIO_BSRR_BR_14 0x40000000U
+#define GPIO_BSRR_BR_15 0x80000000U
+
+/****************** Bit definition for GPIO_LCKR register *********************/
+#define GPIO_LCKR_LCK0 0x00000001U
+#define GPIO_LCKR_LCK1 0x00000002U
+#define GPIO_LCKR_LCK2 0x00000004U
+#define GPIO_LCKR_LCK3 0x00000008U
+#define GPIO_LCKR_LCK4 0x00000010U
+#define GPIO_LCKR_LCK5 0x00000020U
+#define GPIO_LCKR_LCK6 0x00000040U
+#define GPIO_LCKR_LCK7 0x00000080U
+#define GPIO_LCKR_LCK8 0x00000100U
+#define GPIO_LCKR_LCK9 0x00000200U
+#define GPIO_LCKR_LCK10 0x00000400U
+#define GPIO_LCKR_LCK11 0x00000800U
+#define GPIO_LCKR_LCK12 0x00001000U
+#define GPIO_LCKR_LCK13 0x00002000U
+#define GPIO_LCKR_LCK14 0x00004000U
+#define GPIO_LCKR_LCK15 0x00008000U
+#define GPIO_LCKR_LCKK 0x00010000U
+
+/******************************************************************************/
+/* */
+/* Inter-integrated Circuit Interface */
+/* */
+/******************************************************************************/
+/******************* Bit definition for I2C_CR1 register ********************/
+#define I2C_CR1_PE 0x00000001U /*!<Peripheral Enable */
+#define I2C_CR1_SMBUS 0x00000002U /*!<SMBus Mode */
+#define I2C_CR1_SMBTYPE 0x00000008U /*!<SMBus Type */
+#define I2C_CR1_ENARP 0x00000010U /*!<ARP Enable */
+#define I2C_CR1_ENPEC 0x00000020U /*!<PEC Enable */
+#define I2C_CR1_ENGC 0x00000040U /*!<General Call Enable */
+#define I2C_CR1_NOSTRETCH 0x00000080U /*!<Clock Stretching Disable (Slave mode) */
+#define I2C_CR1_START 0x00000100U /*!<Start Generation */
+#define I2C_CR1_STOP 0x00000200U /*!<Stop Generation */
+#define I2C_CR1_ACK 0x00000400U /*!<Acknowledge Enable */
+#define I2C_CR1_POS 0x00000800U /*!<Acknowledge/PEC Position (for data reception) */
+#define I2C_CR1_PEC 0x00001000U /*!<Packet Error Checking */
+#define I2C_CR1_ALERT 0x00002000U /*!<SMBus Alert */
+#define I2C_CR1_SWRST 0x00008000U /*!<Software Reset */
+
+/******************* Bit definition for I2C_CR2 register ********************/
+#define I2C_CR2_FREQ 0x0000003FU /*!<FREQ[5:0] bits (Peripheral Clock Frequency) */
+#define I2C_CR2_FREQ_0 0x00000001U /*!<Bit 0 */
+#define I2C_CR2_FREQ_1 0x00000002U /*!<Bit 1 */
+#define I2C_CR2_FREQ_2 0x00000004U /*!<Bit 2 */
+#define I2C_CR2_FREQ_3 0x00000008U /*!<Bit 3 */
+#define I2C_CR2_FREQ_4 0x00000010U /*!<Bit 4 */
+#define I2C_CR2_FREQ_5 0x00000020U /*!<Bit 5 */
+
+#define I2C_CR2_ITERREN 0x00000100U /*!<Error Interrupt Enable */
+#define I2C_CR2_ITEVTEN 0x00000200U /*!<Event Interrupt Enable */
+#define I2C_CR2_ITBUFEN 0x00000400U /*!<Buffer Interrupt Enable */
+#define I2C_CR2_DMAEN 0x00000800U /*!<DMA Requests Enable */
+#define I2C_CR2_LAST 0x00001000U /*!<DMA Last Transfer */
+
+/******************* Bit definition for I2C_OAR1 register *******************/
+#define I2C_OAR1_ADD1_7 0x000000FEU /*!<Interface Address */
+#define I2C_OAR1_ADD8_9 0x00000300U /*!<Interface Address */
+
+#define I2C_OAR1_ADD0 0x00000001U /*!<Bit 0 */
+#define I2C_OAR1_ADD1 0x00000002U /*!<Bit 1 */
+#define I2C_OAR1_ADD2 0x00000004U /*!<Bit 2 */
+#define I2C_OAR1_ADD3 0x00000008U /*!<Bit 3 */
+#define I2C_OAR1_ADD4 0x00000010U /*!<Bit 4 */
+#define I2C_OAR1_ADD5 0x00000020U /*!<Bit 5 */
+#define I2C_OAR1_ADD6 0x00000040U /*!<Bit 6 */
+#define I2C_OAR1_ADD7 0x00000080U /*!<Bit 7 */
+#define I2C_OAR1_ADD8 0x00000100U /*!<Bit 8 */
+#define I2C_OAR1_ADD9 0x00000200U /*!<Bit 9 */
+
+#define I2C_OAR1_ADDMODE 0x00008000U /*!<Addressing Mode (Slave mode) */
+
+/******************* Bit definition for I2C_OAR2 register *******************/
+#define I2C_OAR2_ENDUAL 0x00000001U /*!<Dual addressing mode enable */
+#define I2C_OAR2_ADD2 0x000000FEU /*!<Interface address */
+
+/******************** Bit definition for I2C_DR register ********************/
+#define I2C_DR_DR 0x000000FFU /*!<8-bit Data Register */
+
+/******************* Bit definition for I2C_SR1 register ********************/
+#define I2C_SR1_SB 0x00000001U /*!<Start Bit (Master mode) */
+#define I2C_SR1_ADDR 0x00000002U /*!<Address sent (master mode)/matched (slave mode) */
+#define I2C_SR1_BTF 0x00000004U /*!<Byte Transfer Finished */
+#define I2C_SR1_ADD10 0x00000008U /*!<10-bit header sent (Master mode) */
+#define I2C_SR1_STOPF 0x00000010U /*!<Stop detection (Slave mode) */
+#define I2C_SR1_RXNE 0x00000040U /*!<Data Register not Empty (receivers) */
+#define I2C_SR1_TXE 0x00000080U /*!<Data Register Empty (transmitters) */
+#define I2C_SR1_BERR 0x00000100U /*!<Bus Error */
+#define I2C_SR1_ARLO 0x00000200U /*!<Arbitration Lost (master mode) */
+#define I2C_SR1_AF 0x00000400U /*!<Acknowledge Failure */
+#define I2C_SR1_OVR 0x00000800U /*!<Overrun/Underrun */
+#define I2C_SR1_PECERR 0x00001000U /*!<PEC Error in reception */
+#define I2C_SR1_TIMEOUT 0x00004000U /*!<Timeout or Tlow Error */
+#define I2C_SR1_SMBALERT 0x00008000U /*!<SMBus Alert */
+
+/******************* Bit definition for I2C_SR2 register ********************/
+#define I2C_SR2_MSL 0x00000001U /*!<Master/Slave */
+#define I2C_SR2_BUSY 0x00000002U /*!<Bus Busy */
+#define I2C_SR2_TRA 0x00000004U /*!<Transmitter/Receiver */
+#define I2C_SR2_GENCALL 0x00000010U /*!<General Call Address (Slave mode) */
+#define I2C_SR2_SMBDEFAULT 0x00000020U /*!<SMBus Device Default Address (Slave mode) */
+#define I2C_SR2_SMBHOST 0x00000040U /*!<SMBus Host Header (Slave mode) */
+#define I2C_SR2_DUALF 0x00000080U /*!<Dual Flag (Slave mode) */
+#define I2C_SR2_PEC 0x0000FF00U /*!<Packet Error Checking Register */
+
+/******************* Bit definition for I2C_CCR register ********************/
+#define I2C_CCR_CCR 0x00000FFFU /*!<Clock Control Register in Fast/Standard mode (Master mode) */
+#define I2C_CCR_DUTY 0x00004000U /*!<Fast Mode Duty Cycle */
+#define I2C_CCR_FS 0x00008000U /*!<I2C Master Mode Selection */
+
+/****************** Bit definition for I2C_TRISE register *******************/
+#define I2C_TRISE_TRISE 0x0000003FU /*!<Maximum Rise Time in Fast/Standard mode (Master mode) */
+
+/****************** Bit definition for I2C_FLTR register *******************/
+#define I2C_FLTR_DNF 0x0000000FU /*!<Digital Noise Filter */
+#define I2C_FLTR_ANOFF 0x00000010U /*!<Analog Noise Filter OFF */
+
+/******************************************************************************/
+/* */
+/* Independent WATCHDOG */
+/* */
+/******************************************************************************/
+/******************* Bit definition for IWDG_KR register ********************/
+#define IWDG_KR_KEY 0xFFFFU /*!<Key value (write only, read 0000h) */
+
+/******************* Bit definition for IWDG_PR register ********************/
+#define IWDG_PR_PR 0x07U /*!<PR[2:0] (Prescaler divider) */
+#define IWDG_PR_PR_0 0x01U /*!<Bit 0 */
+#define IWDG_PR_PR_1 0x02U /*!<Bit 1 */
+#define IWDG_PR_PR_2 0x04U /*!<Bit 2 */
+
+/******************* Bit definition for IWDG_RLR register *******************/
+#define IWDG_RLR_RL 0x0FFFU /*!<Watchdog counter reload value */
+
+/******************* Bit definition for IWDG_SR register ********************/
+#define IWDG_SR_PVU 0x01U /*!<Watchdog prescaler value update */
+#define IWDG_SR_RVU 0x02U /*!<Watchdog counter reload value update */
+
+
+/******************************************************************************/
+/* */
+/* LCD-TFT Display Controller (LTDC) */
+/* */
+/******************************************************************************/
+
+/******************** Bit definition for LTDC_SSCR register *****************/
+
+#define LTDC_SSCR_VSH 0x000007FFU /*!< Vertical Synchronization Height */
+#define LTDC_SSCR_HSW 0x0FFF0000U /*!< Horizontal Synchronization Width */
+
+/******************** Bit definition for LTDC_BPCR register *****************/
+
+#define LTDC_BPCR_AVBP 0x000007FFU /*!< Accumulated Vertical Back Porch */
+#define LTDC_BPCR_AHBP 0x0FFF0000U /*!< Accumulated Horizontal Back Porch */
+
+/******************** Bit definition for LTDC_AWCR register *****************/
+
+#define LTDC_AWCR_AAH 0x000007FFU /*!< Accumulated Active heigh */
+#define LTDC_AWCR_AAW 0x0FFF0000U /*!< Accumulated Active Width */
+
+/******************** Bit definition for LTDC_TWCR register *****************/
+
+#define LTDC_TWCR_TOTALH 0x000007FFU /*!< Total Heigh */
+#define LTDC_TWCR_TOTALW 0x0FFF0000U /*!< Total Width */
+
+/******************** Bit definition for LTDC_GCR register ******************/
+
+#define LTDC_GCR_LTDCEN 0x00000001U /*!< LCD-TFT controller enable bit */
+#define LTDC_GCR_DBW 0x00000070U /*!< Dither Blue Width */
+#define LTDC_GCR_DGW 0x00000700U /*!< Dither Green Width */
+#define LTDC_GCR_DRW 0x00007000U /*!< Dither Red Width */
+#define LTDC_GCR_DEN 0x00010000U /*!< Dither Enable */
+#define LTDC_GCR_PCPOL 0x10000000U /*!< Pixel Clock Polarity */
+#define LTDC_GCR_DEPOL 0x20000000U /*!< Data Enable Polarity */
+#define LTDC_GCR_VSPOL 0x40000000U /*!< Vertical Synchronization Polarity */
+#define LTDC_GCR_HSPOL 0x80000000U /*!< Horizontal Synchronization Polarity */
+
+/* Legacy defines */
+#define LTDC_GCR_DTEN LTDC_GCR_DEN
+
+/******************** Bit definition for LTDC_SRCR register *****************/
+
+#define LTDC_SRCR_IMR 0x00000001U /*!< Immediate Reload */
+#define LTDC_SRCR_VBR 0x00000002U /*!< Vertical Blanking Reload */
+
+/******************** Bit definition for LTDC_BCCR register *****************/
+
+#define LTDC_BCCR_BCBLUE 0x000000FFU /*!< Background Blue value */
+#define LTDC_BCCR_BCGREEN 0x0000FF00U /*!< Background Green value */
+#define LTDC_BCCR_BCRED 0x00FF0000U /*!< Background Red value */
+
+/******************** Bit definition for LTDC_IER register ******************/
+
+#define LTDC_IER_LIE 0x00000001U /*!< Line Interrupt Enable */
+#define LTDC_IER_FUIE 0x00000002U /*!< FIFO Underrun Interrupt Enable */
+#define LTDC_IER_TERRIE 0x00000004U /*!< Transfer Error Interrupt Enable */
+#define LTDC_IER_RRIE 0x00000008U /*!< Register Reload interrupt enable */
+
+/******************** Bit definition for LTDC_ISR register ******************/
+
+#define LTDC_ISR_LIF 0x00000001U /*!< Line Interrupt Flag */
+#define LTDC_ISR_FUIF 0x00000002U /*!< FIFO Underrun Interrupt Flag */
+#define LTDC_ISR_TERRIF 0x00000004U /*!< Transfer Error Interrupt Flag */
+#define LTDC_ISR_RRIF 0x00000008U /*!< Register Reload interrupt Flag */
+
+/******************** Bit definition for LTDC_ICR register ******************/
+
+#define LTDC_ICR_CLIF 0x00000001U /*!< Clears the Line Interrupt Flag */
+#define LTDC_ICR_CFUIF 0x00000002U /*!< Clears the FIFO Underrun Interrupt Flag */
+#define LTDC_ICR_CTERRIF 0x00000004U /*!< Clears the Transfer Error Interrupt Flag */
+#define LTDC_ICR_CRRIF 0x00000008U /*!< Clears Register Reload interrupt Flag */
+
+/******************** Bit definition for LTDC_LIPCR register ****************/
+
+#define LTDC_LIPCR_LIPOS 0x000007FFU /*!< Line Interrupt Position */
+
+/******************** Bit definition for LTDC_CPSR register *****************/
+
+#define LTDC_CPSR_CYPOS 0x0000FFFFU /*!< Current Y Position */
+#define LTDC_CPSR_CXPOS 0xFFFF0000U /*!< Current X Position */
+
+/******************** Bit definition for LTDC_CDSR register *****************/
+
+#define LTDC_CDSR_VDES 0x00000001U /*!< Vertical Data Enable Status */
+#define LTDC_CDSR_HDES 0x00000002U /*!< Horizontal Data Enable Status */
+#define LTDC_CDSR_VSYNCS 0x00000004U /*!< Vertical Synchronization Status */
+#define LTDC_CDSR_HSYNCS 0x00000008U /*!< Horizontal Synchronization Status */
+
+/******************** Bit definition for LTDC_LxCR register *****************/
+
+#define LTDC_LxCR_LEN 0x00000001U /*!< Layer Enable */
+#define LTDC_LxCR_COLKEN 0x00000002U /*!< Color Keying Enable */
+#define LTDC_LxCR_CLUTEN 0x00000010U /*!< Color Lockup Table Enable */
+
+/******************** Bit definition for LTDC_LxWHPCR register **************/
+
+#define LTDC_LxWHPCR_WHSTPOS 0x00000FFFU /*!< Window Horizontal Start Position */
+#define LTDC_LxWHPCR_WHSPPOS 0xFFFF0000U /*!< Window Horizontal Stop Position */
+
+/******************** Bit definition for LTDC_LxWVPCR register **************/
+
+#define LTDC_LxWVPCR_WVSTPOS 0x00000FFFU /*!< Window Vertical Start Position */
+#define LTDC_LxWVPCR_WVSPPOS 0xFFFF0000U /*!< Window Vertical Stop Position */
+
+/******************** Bit definition for LTDC_LxCKCR register ***************/
+
+#define LTDC_LxCKCR_CKBLUE 0x000000FFU /*!< Color Key Blue value */
+#define LTDC_LxCKCR_CKGREEN 0x0000FF00U /*!< Color Key Green value */
+#define LTDC_LxCKCR_CKRED 0x00FF0000U /*!< Color Key Red value */
+
+/******************** Bit definition for LTDC_LxPFCR register ***************/
+
+#define LTDC_LxPFCR_PF 0x00000007U /*!< Pixel Format */
+
+/******************** Bit definition for LTDC_LxCACR register ***************/
+
+#define LTDC_LxCACR_CONSTA 0x000000FFU /*!< Constant Alpha */
+
+/******************** Bit definition for LTDC_LxDCCR register ***************/
+
+#define LTDC_LxDCCR_DCBLUE 0x000000FFU /*!< Default Color Blue */
+#define LTDC_LxDCCR_DCGREEN 0x0000FF00U /*!< Default Color Green */
+#define LTDC_LxDCCR_DCRED 0x00FF0000U /*!< Default Color Red */
+#define LTDC_LxDCCR_DCALPHA 0xFF000000U /*!< Default Color Alpha */
+
+/******************** Bit definition for LTDC_LxBFCR register ***************/
+
+#define LTDC_LxBFCR_BF2 0x00000007U /*!< Blending Factor 2 */
+#define LTDC_LxBFCR_BF1 0x00000700U /*!< Blending Factor 1 */
+
+/******************** Bit definition for LTDC_LxCFBAR register **************/
+
+#define LTDC_LxCFBAR_CFBADD 0xFFFFFFFFU /*!< Color Frame Buffer Start Address */
+
+/******************** Bit definition for LTDC_LxCFBLR register **************/
+
+#define LTDC_LxCFBLR_CFBLL 0x00001FFFU /*!< Color Frame Buffer Line Length */
+#define LTDC_LxCFBLR_CFBP 0x1FFF0000U /*!< Color Frame Buffer Pitch in bytes */
+
+/******************** Bit definition for LTDC_LxCFBLNR register *************/
+
+#define LTDC_LxCFBLNR_CFBLNBR 0x000007FFU /*!< Frame Buffer Line Number */
+
+/******************** Bit definition for LTDC_LxCLUTWR register *************/
+
+#define LTDC_LxCLUTWR_BLUE 0x000000FFU /*!< Blue value */
+#define LTDC_LxCLUTWR_GREEN 0x0000FF00U /*!< Green value */
+#define LTDC_LxCLUTWR_RED 0x00FF0000U /*!< Red value */
+#define LTDC_LxCLUTWR_CLUTADD 0xFF000000U /*!< CLUT address */
+
+
+/******************************************************************************/
+/* */
+/* Power Control */
+/* */
+/******************************************************************************/
+/******************** Bit definition for PWR_CR register ********************/
+#define PWR_CR_LPDS 0x00000001U /*!< Low-Power Deepsleep */
+#define PWR_CR_PDDS 0x00000002U /*!< Power Down Deepsleep */
+#define PWR_CR_CWUF 0x00000004U /*!< Clear Wakeup Flag */
+#define PWR_CR_CSBF 0x00000008U /*!< Clear Standby Flag */
+#define PWR_CR_PVDE 0x00000010U /*!< Power Voltage Detector Enable */
+
+#define PWR_CR_PLS 0x000000E0U /*!< PLS[2:0] bits (PVD Level Selection) */
+#define PWR_CR_PLS_0 0x00000020U /*!< Bit 0 */
+#define PWR_CR_PLS_1 0x00000040U /*!< Bit 1 */
+#define PWR_CR_PLS_2 0x00000080U /*!< Bit 2 */
+
+/*!< PVD level configuration */
+#define PWR_CR_PLS_LEV0 0x00000000U /*!< PVD level 0 */
+#define PWR_CR_PLS_LEV1 0x00000020U /*!< PVD level 1 */
+#define PWR_CR_PLS_LEV2 0x00000040U /*!< PVD level 2 */
+#define PWR_CR_PLS_LEV3 0x00000060U /*!< PVD level 3 */
+#define PWR_CR_PLS_LEV4 0x00000080U /*!< PVD level 4 */
+#define PWR_CR_PLS_LEV5 0x000000A0U /*!< PVD level 5 */
+#define PWR_CR_PLS_LEV6 0x000000C0U /*!< PVD level 6 */
+#define PWR_CR_PLS_LEV7 0x000000E0U /*!< PVD level 7 */
+#define PWR_CR_DBP 0x00000100U /*!< Disable Backup Domain write protection */
+#define PWR_CR_FPDS 0x00000200U /*!< Flash power down in Stop mode */
+#define PWR_CR_LPLVDS 0x00000400U /*!< Low-Power Regulator Low Voltage Scaling in Stop mode */
+#define PWR_CR_MRLVDS 0x00000800U /*!< Main regulator Low Voltage Scaling in Stop mode */
+#define PWR_CR_ADCDC1 0x00002000U /*!< Refer to AN4073 on how to use this bit */
+#define PWR_CR_VOS 0x0000C000U /*!< VOS[1:0] bits (Regulator voltage scaling output selection) */
+#define PWR_CR_VOS_0 0x00004000U /*!< Bit 0 */
+#define PWR_CR_VOS_1 0x00008000U /*!< Bit 1 */
+#define PWR_CR_ODEN 0x00010000U /*!< Over Drive enable */
+#define PWR_CR_ODSWEN 0x00020000U /*!< Over Drive switch enabled */
+#define PWR_CR_UDEN 0x000C0000U /*!< Under Drive enable in stop mode */
+#define PWR_CR_UDEN_0 0x00040000U /*!< Bit 0 */
+#define PWR_CR_UDEN_1 0x00080000U /*!< Bit 1 */
+
+/* Legacy define */
+#define PWR_CR_PMODE PWR_CR_VOS
+#define PWR_CR_LPUDS PWR_CR_LPLVDS /*!< Low-Power Regulator in deepsleep under-drive mode */
+#define PWR_CR_MRUDS PWR_CR_MRLVDS /*!< Main regulator in deepsleep under-drive mode */
+
+/******************* Bit definition for PWR_CSR register ********************/
+#define PWR_CSR_WUF 0x00000001U /*!< Wakeup Flag */
+#define PWR_CSR_SBF 0x00000002U /*!< Standby Flag */
+#define PWR_CSR_PVDO 0x00000004U /*!< PVD Output */
+#define PWR_CSR_BRR 0x00000008U /*!< Backup regulator ready */
+#define PWR_CSR_EWUP 0x00000100U /*!< Enable WKUP pin */
+#define PWR_CSR_BRE 0x00000200U /*!< Backup regulator enable */
+#define PWR_CSR_VOSRDY 0x00004000U /*!< Regulator voltage scaling output selection ready */
+#define PWR_CSR_ODRDY 0x00010000U /*!< Over Drive generator ready */
+#define PWR_CSR_ODSWRDY 0x00020000U /*!< Over Drive Switch ready */
+#define PWR_CSR_UDSWRDY 0x000C0000U /*!< Under Drive ready */
+
+/* Legacy define */
+#define PWR_CSR_REGRDY PWR_CSR_VOSRDY
+
+/******************************************************************************/
+/* */
+/* Reset and Clock Control */
+/* */
+/******************************************************************************/
+/******************** Bit definition for RCC_CR register ********************/
+#define RCC_CR_HSION 0x00000001U
+#define RCC_CR_HSIRDY 0x00000002U
+
+#define RCC_CR_HSITRIM 0x000000F8U
+#define RCC_CR_HSITRIM_0 0x00000008U/*!<Bit 0 */
+#define RCC_CR_HSITRIM_1 0x00000010U/*!<Bit 1 */
+#define RCC_CR_HSITRIM_2 0x00000020U/*!<Bit 2 */
+#define RCC_CR_HSITRIM_3 0x00000040U/*!<Bit 3 */
+#define RCC_CR_HSITRIM_4 0x00000080U/*!<Bit 4 */
+
+#define RCC_CR_HSICAL 0x0000FF00U
+#define RCC_CR_HSICAL_0 0x00000100U/*!<Bit 0 */
+#define RCC_CR_HSICAL_1 0x00000200U/*!<Bit 1 */
+#define RCC_CR_HSICAL_2 0x00000400U/*!<Bit 2 */
+#define RCC_CR_HSICAL_3 0x00000800U/*!<Bit 3 */
+#define RCC_CR_HSICAL_4 0x00001000U/*!<Bit 4 */
+#define RCC_CR_HSICAL_5 0x00002000U/*!<Bit 5 */
+#define RCC_CR_HSICAL_6 0x00004000U/*!<Bit 6 */
+#define RCC_CR_HSICAL_7 0x00008000U/*!<Bit 7 */
+
+#define RCC_CR_HSEON 0x00010000U
+#define RCC_CR_HSERDY 0x00020000U
+#define RCC_CR_HSEBYP 0x00040000U
+#define RCC_CR_CSSON 0x00080000U
+#define RCC_CR_PLLON 0x01000000U
+#define RCC_CR_PLLRDY 0x02000000U
+#define RCC_CR_PLLI2SON 0x04000000U
+#define RCC_CR_PLLI2SRDY 0x08000000U
+#define RCC_CR_PLLSAION 0x10000000U
+#define RCC_CR_PLLSAIRDY 0x20000000U
+
+/******************** Bit definition for RCC_PLLCFGR register ***************/
+#define RCC_PLLCFGR_PLLM 0x0000003FU
+#define RCC_PLLCFGR_PLLM_0 0x00000001U
+#define RCC_PLLCFGR_PLLM_1 0x00000002U
+#define RCC_PLLCFGR_PLLM_2 0x00000004U
+#define RCC_PLLCFGR_PLLM_3 0x00000008U
+#define RCC_PLLCFGR_PLLM_4 0x00000010U
+#define RCC_PLLCFGR_PLLM_5 0x00000020U
+
+#define RCC_PLLCFGR_PLLN 0x00007FC0U
+#define RCC_PLLCFGR_PLLN_0 0x00000040U
+#define RCC_PLLCFGR_PLLN_1 0x00000080U
+#define RCC_PLLCFGR_PLLN_2 0x00000100U
+#define RCC_PLLCFGR_PLLN_3 0x00000200U
+#define RCC_PLLCFGR_PLLN_4 0x00000400U
+#define RCC_PLLCFGR_PLLN_5 0x00000800U
+#define RCC_PLLCFGR_PLLN_6 0x00001000U
+#define RCC_PLLCFGR_PLLN_7 0x00002000U
+#define RCC_PLLCFGR_PLLN_8 0x00004000U
+
+#define RCC_PLLCFGR_PLLP 0x00030000U
+#define RCC_PLLCFGR_PLLP_0 0x00010000U
+#define RCC_PLLCFGR_PLLP_1 0x00020000U
+
+#define RCC_PLLCFGR_PLLSRC 0x00400000U
+#define RCC_PLLCFGR_PLLSRC_HSE 0x00400000U
+#define RCC_PLLCFGR_PLLSRC_HSI 0x00000000U
+
+#define RCC_PLLCFGR_PLLQ 0x0F000000U
+#define RCC_PLLCFGR_PLLQ_0 0x01000000U
+#define RCC_PLLCFGR_PLLQ_1 0x02000000U
+#define RCC_PLLCFGR_PLLQ_2 0x04000000U
+#define RCC_PLLCFGR_PLLQ_3 0x08000000U
+
+/******************** Bit definition for RCC_CFGR register ******************/
+/*!< SW configuration */
+#define RCC_CFGR_SW 0x00000003U /*!< SW[1:0] bits (System clock Switch) */
+#define RCC_CFGR_SW_0 0x00000001U /*!< Bit 0 */
+#define RCC_CFGR_SW_1 0x00000002U /*!< Bit 1 */
+
+#define RCC_CFGR_SW_HSI 0x00000000U /*!< HSI selected as system clock */
+#define RCC_CFGR_SW_HSE 0x00000001U /*!< HSE selected as system clock */
+#define RCC_CFGR_SW_PLL 0x00000002U /*!< PLL selected as system clock */
+
+/*!< SWS configuration */
+#define RCC_CFGR_SWS 0x0000000CU /*!< SWS[1:0] bits (System Clock Switch Status) */
+#define RCC_CFGR_SWS_0 0x00000004U /*!< Bit 0 */
+#define RCC_CFGR_SWS_1 0x00000008U /*!< Bit 1 */
+
+#define RCC_CFGR_SWS_HSI 0x00000000U /*!< HSI oscillator used as system clock */
+#define RCC_CFGR_SWS_HSE 0x00000004U /*!< HSE oscillator used as system clock */
+#define RCC_CFGR_SWS_PLL 0x00000008U /*!< PLL used as system clock */
+
+/*!< HPRE configuration */
+#define RCC_CFGR_HPRE 0x000000F0U /*!< HPRE[3:0] bits (AHB prescaler) */
+#define RCC_CFGR_HPRE_0 0x00000010U /*!< Bit 0 */
+#define RCC_CFGR_HPRE_1 0x00000020U /*!< Bit 1 */
+#define RCC_CFGR_HPRE_2 0x00000040U /*!< Bit 2 */
+#define RCC_CFGR_HPRE_3 0x00000080U /*!< Bit 3 */
+
+#define RCC_CFGR_HPRE_DIV1 0x00000000U /*!< SYSCLK not divided */
+#define RCC_CFGR_HPRE_DIV2 0x00000080U /*!< SYSCLK divided by 2 */
+#define RCC_CFGR_HPRE_DIV4 0x00000090U /*!< SYSCLK divided by 4 */
+#define RCC_CFGR_HPRE_DIV8 0x000000A0U /*!< SYSCLK divided by 8 */
+#define RCC_CFGR_HPRE_DIV16 0x000000B0U /*!< SYSCLK divided by 16 */
+#define RCC_CFGR_HPRE_DIV64 0x000000C0U /*!< SYSCLK divided by 64 */
+#define RCC_CFGR_HPRE_DIV128 0x000000D0U /*!< SYSCLK divided by 128 */
+#define RCC_CFGR_HPRE_DIV256 0x000000E0U /*!< SYSCLK divided by 256 */
+#define RCC_CFGR_HPRE_DIV512 0x000000F0U /*!< SYSCLK divided by 512 */
+
+/*!< PPRE1 configuration */
+#define RCC_CFGR_PPRE1 0x00001C00U /*!< PRE1[2:0] bits (APB1 prescaler) */
+#define RCC_CFGR_PPRE1_0 0x00000400U /*!< Bit 0 */
+#define RCC_CFGR_PPRE1_1 0x00000800U /*!< Bit 1 */
+#define RCC_CFGR_PPRE1_2 0x00001000U /*!< Bit 2 */
+
+#define RCC_CFGR_PPRE1_DIV1 0x00000000U /*!< HCLK not divided */
+#define RCC_CFGR_PPRE1_DIV2 0x00001000U /*!< HCLK divided by 2 */
+#define RCC_CFGR_PPRE1_DIV4 0x00001400U /*!< HCLK divided by 4 */
+#define RCC_CFGR_PPRE1_DIV8 0x00001800U /*!< HCLK divided by 8 */
+#define RCC_CFGR_PPRE1_DIV16 0x00001C00U /*!< HCLK divided by 16 */
+
+/*!< PPRE2 configuration */
+#define RCC_CFGR_PPRE2 0x0000E000U /*!< PRE2[2:0] bits (APB2 prescaler) */
+#define RCC_CFGR_PPRE2_0 0x00002000U /*!< Bit 0 */
+#define RCC_CFGR_PPRE2_1 0x00004000U /*!< Bit 1 */
+#define RCC_CFGR_PPRE2_2 0x00008000U /*!< Bit 2 */
+
+#define RCC_CFGR_PPRE2_DIV1 0x00000000U /*!< HCLK not divided */
+#define RCC_CFGR_PPRE2_DIV2 0x00008000U /*!< HCLK divided by 2 */
+#define RCC_CFGR_PPRE2_DIV4 0x0000A000U /*!< HCLK divided by 4 */
+#define RCC_CFGR_PPRE2_DIV8 0x0000C000U /*!< HCLK divided by 8 */
+#define RCC_CFGR_PPRE2_DIV16 0x0000E000U /*!< HCLK divided by 16 */
+
+/*!< RTCPRE configuration */
+#define RCC_CFGR_RTCPRE 0x001F0000U
+#define RCC_CFGR_RTCPRE_0 0x00010000U
+#define RCC_CFGR_RTCPRE_1 0x00020000U
+#define RCC_CFGR_RTCPRE_2 0x00040000U
+#define RCC_CFGR_RTCPRE_3 0x00080000U
+#define RCC_CFGR_RTCPRE_4 0x00100000U
+
+/*!< MCO1 configuration */
+#define RCC_CFGR_MCO1 0x00600000U
+#define RCC_CFGR_MCO1_0 0x00200000U
+#define RCC_CFGR_MCO1_1 0x00400000U
+
+#define RCC_CFGR_I2SSRC 0x00800000U
+
+#define RCC_CFGR_MCO1PRE 0x07000000U
+#define RCC_CFGR_MCO1PRE_0 0x01000000U
+#define RCC_CFGR_MCO1PRE_1 0x02000000U
+#define RCC_CFGR_MCO1PRE_2 0x04000000U
+
+#define RCC_CFGR_MCO2PRE 0x38000000U
+#define RCC_CFGR_MCO2PRE_0 0x08000000U
+#define RCC_CFGR_MCO2PRE_1 0x10000000U
+#define RCC_CFGR_MCO2PRE_2 0x20000000U
+
+#define RCC_CFGR_MCO2 0xC0000000U
+#define RCC_CFGR_MCO2_0 0x40000000U
+#define RCC_CFGR_MCO2_1 0x80000000U
+
+/******************** Bit definition for RCC_CIR register *******************/
+#define RCC_CIR_LSIRDYF 0x00000001U
+#define RCC_CIR_LSERDYF 0x00000002U
+#define RCC_CIR_HSIRDYF 0x00000004U
+#define RCC_CIR_HSERDYF 0x00000008U
+#define RCC_CIR_PLLRDYF 0x00000010U
+#define RCC_CIR_PLLI2SRDYF 0x00000020U
+#define RCC_CIR_PLLSAIRDYF 0x00000040U
+#define RCC_CIR_CSSF 0x00000080U
+#define RCC_CIR_LSIRDYIE 0x00000100U
+#define RCC_CIR_LSERDYIE 0x00000200U
+#define RCC_CIR_HSIRDYIE 0x00000400U
+#define RCC_CIR_HSERDYIE 0x00000800U
+#define RCC_CIR_PLLRDYIE 0x00001000U
+#define RCC_CIR_PLLI2SRDYIE 0x00002000U
+#define RCC_CIR_PLLSAIRDYIE 0x00004000U
+#define RCC_CIR_LSIRDYC 0x00010000U
+#define RCC_CIR_LSERDYC 0x00020000U
+#define RCC_CIR_HSIRDYC 0x00040000U
+#define RCC_CIR_HSERDYC 0x00080000U
+#define RCC_CIR_PLLRDYC 0x00100000U
+#define RCC_CIR_PLLI2SRDYC 0x00200000U
+#define RCC_CIR_PLLSAIRDYC 0x00400000U
+#define RCC_CIR_CSSC 0x00800000U
+
+/******************** Bit definition for RCC_AHB1RSTR register **************/
+#define RCC_AHB1RSTR_GPIOARST 0x00000001U
+#define RCC_AHB1RSTR_GPIOBRST 0x00000002U
+#define RCC_AHB1RSTR_GPIOCRST 0x00000004U
+#define RCC_AHB1RSTR_GPIODRST 0x00000008U
+#define RCC_AHB1RSTR_GPIOERST 0x00000010U
+#define RCC_AHB1RSTR_GPIOFRST 0x00000020U
+#define RCC_AHB1RSTR_GPIOGRST 0x00000040U
+#define RCC_AHB1RSTR_GPIOHRST 0x00000080U
+#define RCC_AHB1RSTR_GPIOIRST 0x00000100U
+#define RCC_AHB1RSTR_GPIOJRST 0x00000200U
+#define RCC_AHB1RSTR_GPIOKRST 0x00000400U
+#define RCC_AHB1RSTR_CRCRST 0x00001000U
+#define RCC_AHB1RSTR_DMA1RST 0x00200000U
+#define RCC_AHB1RSTR_DMA2RST 0x00400000U
+#define RCC_AHB1RSTR_DMA2DRST 0x00800000U
+#define RCC_AHB1RSTR_ETHMACRST 0x02000000U
+#define RCC_AHB1RSTR_OTGHRST 0x20000000U
+
+/******************** Bit definition for RCC_AHB2RSTR register **************/
+#define RCC_AHB2RSTR_DCMIRST 0x00000001U
+#define RCC_AHB2RSTR_RNGRST 0x00000040U
+#define RCC_AHB2RSTR_OTGFSRST 0x00000080U
+
+/******************** Bit definition for RCC_AHB3RSTR register **************/
+#define RCC_AHB3RSTR_FMCRST 0x00000001U
+
+/******************** Bit definition for RCC_APB1RSTR register **************/
+#define RCC_APB1RSTR_TIM2RST 0x00000001U
+#define RCC_APB1RSTR_TIM3RST 0x00000002U
+#define RCC_APB1RSTR_TIM4RST 0x00000004U
+#define RCC_APB1RSTR_TIM5RST 0x00000008U
+#define RCC_APB1RSTR_TIM6RST 0x00000010U
+#define RCC_APB1RSTR_TIM7RST 0x00000020U
+#define RCC_APB1RSTR_TIM12RST 0x00000040U
+#define RCC_APB1RSTR_TIM13RST 0x00000080U
+#define RCC_APB1RSTR_TIM14RST 0x00000100U
+#define RCC_APB1RSTR_WWDGRST 0x00000800U
+#define RCC_APB1RSTR_SPI2RST 0x00004000U
+#define RCC_APB1RSTR_SPI3RST 0x00008000U
+#define RCC_APB1RSTR_USART2RST 0x00020000U
+#define RCC_APB1RSTR_USART3RST 0x00040000U
+#define RCC_APB1RSTR_UART4RST 0x00080000U
+#define RCC_APB1RSTR_UART5RST 0x00100000U
+#define RCC_APB1RSTR_I2C1RST 0x00200000U
+#define RCC_APB1RSTR_I2C2RST 0x00400000U
+#define RCC_APB1RSTR_I2C3RST 0x00800000U
+#define RCC_APB1RSTR_CAN1RST 0x02000000U
+#define RCC_APB1RSTR_CAN2RST 0x04000000U
+#define RCC_APB1RSTR_PWRRST 0x10000000U
+#define RCC_APB1RSTR_DACRST 0x20000000U
+#define RCC_APB1RSTR_UART7RST 0x40000000U
+#define RCC_APB1RSTR_UART8RST 0x80000000U
+
+/******************** Bit definition for RCC_APB2RSTR register **************/
+#define RCC_APB2RSTR_TIM1RST 0x00000001U
+#define RCC_APB2RSTR_TIM8RST 0x00000002U
+#define RCC_APB2RSTR_USART1RST 0x00000010U
+#define RCC_APB2RSTR_USART6RST 0x00000020U
+#define RCC_APB2RSTR_ADCRST 0x00000100U
+#define RCC_APB2RSTR_SDIORST 0x00000800U
+#define RCC_APB2RSTR_SPI1RST 0x00001000U
+#define RCC_APB2RSTR_SPI4RST 0x00002000U
+#define RCC_APB2RSTR_SYSCFGRST 0x00004000U
+#define RCC_APB2RSTR_TIM9RST 0x00010000U
+#define RCC_APB2RSTR_TIM10RST 0x00020000U
+#define RCC_APB2RSTR_TIM11RST 0x00040000U
+#define RCC_APB2RSTR_SPI5RST 0x00100000U
+#define RCC_APB2RSTR_SPI6RST 0x00200000U
+#define RCC_APB2RSTR_SAI1RST 0x00400000U
+#define RCC_APB2RSTR_LTDCRST 0x04000000U
+
+/* Old SPI1RST bit definition, maintained for legacy purpose */
+#define RCC_APB2RSTR_SPI1 RCC_APB2RSTR_SPI1RST
+
+/******************** Bit definition for RCC_AHB1ENR register ***************/
+#define RCC_AHB1ENR_GPIOAEN 0x00000001U
+#define RCC_AHB1ENR_GPIOBEN 0x00000002U
+#define RCC_AHB1ENR_GPIOCEN 0x00000004U
+#define RCC_AHB1ENR_GPIODEN 0x00000008U
+#define RCC_AHB1ENR_GPIOEEN 0x00000010U
+#define RCC_AHB1ENR_GPIOFEN 0x00000020U
+#define RCC_AHB1ENR_GPIOGEN 0x00000040U
+#define RCC_AHB1ENR_GPIOHEN 0x00000080U
+#define RCC_AHB1ENR_GPIOIEN 0x00000100U
+#define RCC_AHB1ENR_GPIOJEN 0x00000200U
+#define RCC_AHB1ENR_GPIOKEN 0x00000400U
+
+#define RCC_AHB1ENR_CRCEN 0x00001000U
+#define RCC_AHB1ENR_BKPSRAMEN 0x00040000U
+#define RCC_AHB1ENR_CCMDATARAMEN 0x00100000U
+#define RCC_AHB1ENR_DMA1EN 0x00200000U
+#define RCC_AHB1ENR_DMA2EN 0x00400000U
+#define RCC_AHB1ENR_DMA2DEN 0x00800000U
+
+#define RCC_AHB1ENR_ETHMACEN 0x02000000U
+#define RCC_AHB1ENR_ETHMACTXEN 0x04000000U
+#define RCC_AHB1ENR_ETHMACRXEN 0x08000000U
+#define RCC_AHB1ENR_ETHMACPTPEN 0x10000000U
+#define RCC_AHB1ENR_OTGHSEN 0x20000000U
+#define RCC_AHB1ENR_OTGHSULPIEN 0x40000000U
+
+/******************** Bit definition for RCC_AHB2ENR register ***************/
+#define RCC_AHB2ENR_DCMIEN 0x00000001U
+#define RCC_AHB2ENR_RNGEN 0x00000040U
+#define RCC_AHB2ENR_OTGFSEN 0x00000080U
+
+/******************** Bit definition for RCC_AHB3ENR register ***************/
+#define RCC_AHB3ENR_FMCEN 0x00000001U
+
+/******************** Bit definition for RCC_APB1ENR register ***************/
+#define RCC_APB1ENR_TIM2EN 0x00000001U
+#define RCC_APB1ENR_TIM3EN 0x00000002U
+#define RCC_APB1ENR_TIM4EN 0x00000004U
+#define RCC_APB1ENR_TIM5EN 0x00000008U
+#define RCC_APB1ENR_TIM6EN 0x00000010U
+#define RCC_APB1ENR_TIM7EN 0x00000020U
+#define RCC_APB1ENR_TIM12EN 0x00000040U
+#define RCC_APB1ENR_TIM13EN 0x00000080U
+#define RCC_APB1ENR_TIM14EN 0x00000100U
+#define RCC_APB1ENR_WWDGEN 0x00000800U
+#define RCC_APB1ENR_SPI2EN 0x00004000U
+#define RCC_APB1ENR_SPI3EN 0x00008000U
+#define RCC_APB1ENR_USART2EN 0x00020000U
+#define RCC_APB1ENR_USART3EN 0x00040000U
+#define RCC_APB1ENR_UART4EN 0x00080000U
+#define RCC_APB1ENR_UART5EN 0x00100000U
+#define RCC_APB1ENR_I2C1EN 0x00200000U
+#define RCC_APB1ENR_I2C2EN 0x00400000U
+#define RCC_APB1ENR_I2C3EN 0x00800000U
+#define RCC_APB1ENR_CAN1EN 0x02000000U
+#define RCC_APB1ENR_CAN2EN 0x04000000U
+#define RCC_APB1ENR_PWREN 0x10000000U
+#define RCC_APB1ENR_DACEN 0x20000000U
+#define RCC_APB1ENR_UART7EN 0x40000000U
+#define RCC_APB1ENR_UART8EN 0x80000000U
+
+/******************** Bit definition for RCC_APB2ENR register ***************/
+#define RCC_APB2ENR_TIM1EN 0x00000001U
+#define RCC_APB2ENR_TIM8EN 0x00000002U
+#define RCC_APB2ENR_USART1EN 0x00000010U
+#define RCC_APB2ENR_USART6EN 0x00000020U
+#define RCC_APB2ENR_ADC1EN 0x00000100U
+#define RCC_APB2ENR_ADC2EN 0x00000200U
+#define RCC_APB2ENR_ADC3EN 0x00000400U
+#define RCC_APB2ENR_SDIOEN 0x00000800U
+#define RCC_APB2ENR_SPI1EN 0x00001000U
+#define RCC_APB2ENR_SPI4EN 0x00002000U
+#define RCC_APB2ENR_SYSCFGEN 0x00004000U
+#define RCC_APB2ENR_TIM9EN 0x00010000U
+#define RCC_APB2ENR_TIM10EN 0x00020000U
+#define RCC_APB2ENR_TIM11EN 0x00040000U
+#define RCC_APB2ENR_SPI5EN 0x00100000U
+#define RCC_APB2ENR_SPI6EN 0x00200000U
+#define RCC_APB2ENR_SAI1EN 0x00400000U
+#define RCC_APB2ENR_LTDCEN 0x04000000U
+
+/******************** Bit definition for RCC_AHB1LPENR register *************/
+#define RCC_AHB1LPENR_GPIOALPEN 0x00000001U
+#define RCC_AHB1LPENR_GPIOBLPEN 0x00000002U
+#define RCC_AHB1LPENR_GPIOCLPEN 0x00000004U
+#define RCC_AHB1LPENR_GPIODLPEN 0x00000008U
+#define RCC_AHB1LPENR_GPIOELPEN 0x00000010U
+#define RCC_AHB1LPENR_GPIOFLPEN 0x00000020U
+#define RCC_AHB1LPENR_GPIOGLPEN 0x00000040U
+#define RCC_AHB1LPENR_GPIOHLPEN 0x00000080U
+#define RCC_AHB1LPENR_GPIOILPEN 0x00000100U
+#define RCC_AHB1LPENR_GPIOJLPEN 0x00000200U
+#define RCC_AHB1LPENR_GPIOKLPEN 0x00000400U
+
+#define RCC_AHB1LPENR_CRCLPEN 0x00001000U
+#define RCC_AHB1LPENR_FLITFLPEN 0x00008000U
+#define RCC_AHB1LPENR_SRAM1LPEN 0x00010000U
+#define RCC_AHB1LPENR_SRAM2LPEN 0x00020000U
+#define RCC_AHB1LPENR_BKPSRAMLPEN 0x00040000U
+#define RCC_AHB1LPENR_SRAM3LPEN 0x00080000U
+#define RCC_AHB1LPENR_DMA1LPEN 0x00200000U
+#define RCC_AHB1LPENR_DMA2LPEN 0x00400000U
+#define RCC_AHB1LPENR_DMA2DLPEN 0x00800000U
+
+#define RCC_AHB1LPENR_ETHMACLPEN 0x02000000U
+#define RCC_AHB1LPENR_ETHMACTXLPEN 0x04000000U
+#define RCC_AHB1LPENR_ETHMACRXLPEN 0x08000000U
+#define RCC_AHB1LPENR_ETHMACPTPLPEN 0x10000000U
+#define RCC_AHB1LPENR_OTGHSLPEN 0x20000000U
+#define RCC_AHB1LPENR_OTGHSULPILPEN 0x40000000U
+
+/******************** Bit definition for RCC_AHB2LPENR register *************/
+#define RCC_AHB2LPENR_DCMILPEN 0x00000001U
+#define RCC_AHB2LPENR_RNGLPEN 0x00000040U
+#define RCC_AHB2LPENR_OTGFSLPEN 0x00000080U
+
+/******************** Bit definition for RCC_AHB3LPENR register *************/
+#define RCC_AHB3LPENR_FMCLPEN 0x00000001U
+
+/******************** Bit definition for RCC_APB1LPENR register *************/
+#define RCC_APB1LPENR_TIM2LPEN 0x00000001U
+#define RCC_APB1LPENR_TIM3LPEN 0x00000002U
+#define RCC_APB1LPENR_TIM4LPEN 0x00000004U
+#define RCC_APB1LPENR_TIM5LPEN 0x00000008U
+#define RCC_APB1LPENR_TIM6LPEN 0x00000010U
+#define RCC_APB1LPENR_TIM7LPEN 0x00000020U
+#define RCC_APB1LPENR_TIM12LPEN 0x00000040U
+#define RCC_APB1LPENR_TIM13LPEN 0x00000080U
+#define RCC_APB1LPENR_TIM14LPEN 0x00000100U
+#define RCC_APB1LPENR_WWDGLPEN 0x00000800U
+#define RCC_APB1LPENR_SPI2LPEN 0x00004000U
+#define RCC_APB1LPENR_SPI3LPEN 0x00008000U
+#define RCC_APB1LPENR_USART2LPEN 0x00020000U
+#define RCC_APB1LPENR_USART3LPEN 0x00040000U
+#define RCC_APB1LPENR_UART4LPEN 0x00080000U
+#define RCC_APB1LPENR_UART5LPEN 0x00100000U
+#define RCC_APB1LPENR_I2C1LPEN 0x00200000U
+#define RCC_APB1LPENR_I2C2LPEN 0x00400000U
+#define RCC_APB1LPENR_I2C3LPEN 0x00800000U
+#define RCC_APB1LPENR_CAN1LPEN 0x02000000U
+#define RCC_APB1LPENR_CAN2LPEN 0x04000000U
+#define RCC_APB1LPENR_PWRLPEN 0x10000000U
+#define RCC_APB1LPENR_DACLPEN 0x20000000U
+#define RCC_APB1LPENR_UART7LPEN 0x40000000U
+#define RCC_APB1LPENR_UART8LPEN 0x80000000U
+
+/******************** Bit definition for RCC_APB2LPENR register *************/
+#define RCC_APB2LPENR_TIM1LPEN 0x00000001U
+#define RCC_APB2LPENR_TIM8LPEN 0x00000002U
+#define RCC_APB2LPENR_USART1LPEN 0x00000010U
+#define RCC_APB2LPENR_USART6LPEN 0x00000020U
+#define RCC_APB2LPENR_ADC1LPEN 0x00000100U
+#define RCC_APB2LPENR_ADC2LPEN 0x00000200U
+#define RCC_APB2LPENR_ADC3LPEN 0x00000400U
+#define RCC_APB2LPENR_SDIOLPEN 0x00000800U
+#define RCC_APB2LPENR_SPI1LPEN 0x00001000U
+#define RCC_APB2LPENR_SPI4LPEN 0x00002000U
+#define RCC_APB2LPENR_SYSCFGLPEN 0x00004000U
+#define RCC_APB2LPENR_TIM9LPEN 0x00010000U
+#define RCC_APB2LPENR_TIM10LPEN 0x00020000U
+#define RCC_APB2LPENR_TIM11LPEN 0x00040000U
+#define RCC_APB2LPENR_SPI5LPEN 0x00100000U
+#define RCC_APB2LPENR_SPI6LPEN 0x00200000U
+#define RCC_APB2LPENR_SAI1LPEN 0x00400000U
+#define RCC_APB2LPENR_LTDCLPEN 0x04000000U
+
+/******************** Bit definition for RCC_BDCR register ******************/
+#define RCC_BDCR_LSEON 0x00000001U
+#define RCC_BDCR_LSERDY 0x00000002U
+#define RCC_BDCR_LSEBYP 0x00000004U
+
+#define RCC_BDCR_RTCSEL 0x00000300U
+#define RCC_BDCR_RTCSEL_0 0x00000100U
+#define RCC_BDCR_RTCSEL_1 0x00000200U
+
+#define RCC_BDCR_RTCEN 0x00008000U
+#define RCC_BDCR_BDRST 0x00010000U
+
+/******************** Bit definition for RCC_CSR register *******************/
+#define RCC_CSR_LSION 0x00000001U
+#define RCC_CSR_LSIRDY 0x00000002U
+#define RCC_CSR_RMVF 0x01000000U
+#define RCC_CSR_BORRSTF 0x02000000U
+#define RCC_CSR_PADRSTF 0x04000000U
+#define RCC_CSR_PORRSTF 0x08000000U
+#define RCC_CSR_SFTRSTF 0x10000000U
+#define RCC_CSR_WDGRSTF 0x20000000U
+#define RCC_CSR_WWDGRSTF 0x40000000U
+#define RCC_CSR_LPWRRSTF 0x80000000U
+
+/******************** Bit definition for RCC_SSCGR register *****************/
+#define RCC_SSCGR_MODPER 0x00001FFFU
+#define RCC_SSCGR_INCSTEP 0x0FFFE000U
+#define RCC_SSCGR_SPREADSEL 0x40000000U
+#define RCC_SSCGR_SSCGEN 0x80000000U
+
+/******************** Bit definition for RCC_PLLI2SCFGR register ************/
+#define RCC_PLLI2SCFGR_PLLI2SN 0x00007FC0U
+#define RCC_PLLI2SCFGR_PLLI2SN_0 0x00000040U
+#define RCC_PLLI2SCFGR_PLLI2SN_1 0x00000080U
+#define RCC_PLLI2SCFGR_PLLI2SN_2 0x00000100U
+#define RCC_PLLI2SCFGR_PLLI2SN_3 0x00000200U
+#define RCC_PLLI2SCFGR_PLLI2SN_4 0x00000400U
+#define RCC_PLLI2SCFGR_PLLI2SN_5 0x00000800U
+#define RCC_PLLI2SCFGR_PLLI2SN_6 0x00001000U
+#define RCC_PLLI2SCFGR_PLLI2SN_7 0x00002000U
+#define RCC_PLLI2SCFGR_PLLI2SN_8 0x00004000U
+
+#define RCC_PLLI2SCFGR_PLLI2SQ 0x0F000000U
+#define RCC_PLLI2SCFGR_PLLI2SQ_0 0x01000000U
+#define RCC_PLLI2SCFGR_PLLI2SQ_1 0x02000000U
+#define RCC_PLLI2SCFGR_PLLI2SQ_2 0x04000000U
+#define RCC_PLLI2SCFGR_PLLI2SQ_3 0x08000000U
+
+#define RCC_PLLI2SCFGR_PLLI2SR 0x70000000U
+#define RCC_PLLI2SCFGR_PLLI2SR_0 0x10000000U
+#define RCC_PLLI2SCFGR_PLLI2SR_1 0x20000000U
+#define RCC_PLLI2SCFGR_PLLI2SR_2 0x40000000U
+
+
+/******************** Bit definition for RCC_PLLSAICFGR register ************/
+#define RCC_PLLSAICFGR_PLLSAIN 0x00007FC0U
+#define RCC_PLLSAICFGR_PLLSAIN_0 0x00000040U
+#define RCC_PLLSAICFGR_PLLSAIN_1 0x00000080U
+#define RCC_PLLSAICFGR_PLLSAIN_2 0x00000100U
+#define RCC_PLLSAICFGR_PLLSAIN_3 0x00000200U
+#define RCC_PLLSAICFGR_PLLSAIN_4 0x00000400U
+#define RCC_PLLSAICFGR_PLLSAIN_5 0x00000800U
+#define RCC_PLLSAICFGR_PLLSAIN_6 0x00001000U
+#define RCC_PLLSAICFGR_PLLSAIN_7 0x00002000U
+#define RCC_PLLSAICFGR_PLLSAIN_8 0x00004000U
+
+#define RCC_PLLSAICFGR_PLLSAIQ 0x0F000000U
+#define RCC_PLLSAICFGR_PLLSAIQ_0 0x01000000U
+#define RCC_PLLSAICFGR_PLLSAIQ_1 0x02000000U
+#define RCC_PLLSAICFGR_PLLSAIQ_2 0x04000000U
+#define RCC_PLLSAICFGR_PLLSAIQ_3 0x08000000U
+
+#define RCC_PLLSAICFGR_PLLSAIR 0x70000000U
+#define RCC_PLLSAICFGR_PLLSAIR_0 0x10000000U
+#define RCC_PLLSAICFGR_PLLSAIR_1 0x20000000U
+#define RCC_PLLSAICFGR_PLLSAIR_2 0x40000000U
+
+/******************** Bit definition for RCC_DCKCFGR register ***************/
+#define RCC_DCKCFGR_PLLI2SDIVQ 0x0000001FU
+#define RCC_DCKCFGR_PLLSAIDIVQ 0x00001F00U
+#define RCC_DCKCFGR_PLLSAIDIVR 0x00030000U
+#define RCC_DCKCFGR_SAI1ASRC 0x00300000U
+#define RCC_DCKCFGR_SAI1ASRC_0 0x00100000U
+#define RCC_DCKCFGR_SAI1ASRC_1 0x00200000U
+#define RCC_DCKCFGR_SAI1BSRC 0x00C00000U
+#define RCC_DCKCFGR_SAI1BSRC_0 0x00400000U
+#define RCC_DCKCFGR_SAI1BSRC_1 0x00800000U
+#define RCC_DCKCFGR_TIMPRE 0x01000000U
+
+
+/******************************************************************************/
+/* */
+/* RNG */
+/* */
+/******************************************************************************/
+/******************** Bits definition for RNG_CR register *******************/
+#define RNG_CR_RNGEN 0x00000004U
+#define RNG_CR_IE 0x00000008U
+
+/******************** Bits definition for RNG_SR register *******************/
+#define RNG_SR_DRDY 0x00000001U
+#define RNG_SR_CECS 0x00000002U
+#define RNG_SR_SECS 0x00000004U
+#define RNG_SR_CEIS 0x00000020U
+#define RNG_SR_SEIS 0x00000040U
+
+/******************************************************************************/
+/* */
+/* Real-Time Clock (RTC) */
+/* */
+/******************************************************************************/
+/******************** Bits definition for RTC_TR register *******************/
+#define RTC_TR_PM 0x00400000U
+#define RTC_TR_HT 0x00300000U
+#define RTC_TR_HT_0 0x00100000U
+#define RTC_TR_HT_1 0x00200000U
+#define RTC_TR_HU 0x000F0000U
+#define RTC_TR_HU_0 0x00010000U
+#define RTC_TR_HU_1 0x00020000U
+#define RTC_TR_HU_2 0x00040000U
+#define RTC_TR_HU_3 0x00080000U
+#define RTC_TR_MNT 0x00007000U
+#define RTC_TR_MNT_0 0x00001000U
+#define RTC_TR_MNT_1 0x00002000U
+#define RTC_TR_MNT_2 0x00004000U
+#define RTC_TR_MNU 0x00000F00U
+#define RTC_TR_MNU_0 0x00000100U
+#define RTC_TR_MNU_1 0x00000200U
+#define RTC_TR_MNU_2 0x00000400U
+#define RTC_TR_MNU_3 0x00000800U
+#define RTC_TR_ST 0x00000070U
+#define RTC_TR_ST_0 0x00000010U
+#define RTC_TR_ST_1 0x00000020U
+#define RTC_TR_ST_2 0x00000040U
+#define RTC_TR_SU 0x0000000FU
+#define RTC_TR_SU_0 0x00000001U
+#define RTC_TR_SU_1 0x00000002U
+#define RTC_TR_SU_2 0x00000004U
+#define RTC_TR_SU_3 0x00000008U
+
+/******************** Bits definition for RTC_DR register *******************/
+#define RTC_DR_YT 0x00F00000U
+#define RTC_DR_YT_0 0x00100000U
+#define RTC_DR_YT_1 0x00200000U
+#define RTC_DR_YT_2 0x00400000U
+#define RTC_DR_YT_3 0x00800000U
+#define RTC_DR_YU 0x000F0000U
+#define RTC_DR_YU_0 0x00010000U
+#define RTC_DR_YU_1 0x00020000U
+#define RTC_DR_YU_2 0x00040000U
+#define RTC_DR_YU_3 0x00080000U
+#define RTC_DR_WDU 0x0000E000U
+#define RTC_DR_WDU_0 0x00002000U
+#define RTC_DR_WDU_1 0x00004000U
+#define RTC_DR_WDU_2 0x00008000U
+#define RTC_DR_MT 0x00001000U
+#define RTC_DR_MU 0x00000F00U
+#define RTC_DR_MU_0 0x00000100U
+#define RTC_DR_MU_1 0x00000200U
+#define RTC_DR_MU_2 0x00000400U
+#define RTC_DR_MU_3 0x00000800U
+#define RTC_DR_DT 0x00000030U
+#define RTC_DR_DT_0 0x00000010U
+#define RTC_DR_DT_1 0x00000020U
+#define RTC_DR_DU 0x0000000FU
+#define RTC_DR_DU_0 0x00000001U
+#define RTC_DR_DU_1 0x00000002U
+#define RTC_DR_DU_2 0x00000004U
+#define RTC_DR_DU_3 0x00000008U
+
+/******************** Bits definition for RTC_CR register *******************/
+#define RTC_CR_COE 0x00800000U
+#define RTC_CR_OSEL 0x00600000U
+#define RTC_CR_OSEL_0 0x00200000U
+#define RTC_CR_OSEL_1 0x00400000U
+#define RTC_CR_POL 0x00100000U
+#define RTC_CR_COSEL 0x00080000U
+#define RTC_CR_BCK 0x00040000U
+#define RTC_CR_SUB1H 0x00020000U
+#define RTC_CR_ADD1H 0x00010000U
+#define RTC_CR_TSIE 0x00008000U
+#define RTC_CR_WUTIE 0x00004000U
+#define RTC_CR_ALRBIE 0x00002000U
+#define RTC_CR_ALRAIE 0x00001000U
+#define RTC_CR_TSE 0x00000800U
+#define RTC_CR_WUTE 0x00000400U
+#define RTC_CR_ALRBE 0x00000200U
+#define RTC_CR_ALRAE 0x00000100U
+#define RTC_CR_DCE 0x00000080U
+#define RTC_CR_FMT 0x00000040U
+#define RTC_CR_BYPSHAD 0x00000020U
+#define RTC_CR_REFCKON 0x00000010U
+#define RTC_CR_TSEDGE 0x00000008U
+#define RTC_CR_WUCKSEL 0x00000007U
+#define RTC_CR_WUCKSEL_0 0x00000001U
+#define RTC_CR_WUCKSEL_1 0x00000002U
+#define RTC_CR_WUCKSEL_2 0x00000004U
+
+/******************** Bits definition for RTC_ISR register ******************/
+#define RTC_ISR_RECALPF 0x00010000U
+#define RTC_ISR_TAMP1F 0x00002000U
+#define RTC_ISR_TAMP2F 0x00004000U
+#define RTC_ISR_TSOVF 0x00001000U
+#define RTC_ISR_TSF 0x00000800U
+#define RTC_ISR_WUTF 0x00000400U
+#define RTC_ISR_ALRBF 0x00000200U
+#define RTC_ISR_ALRAF 0x00000100U
+#define RTC_ISR_INIT 0x00000080U
+#define RTC_ISR_INITF 0x00000040U
+#define RTC_ISR_RSF 0x00000020U
+#define RTC_ISR_INITS 0x00000010U
+#define RTC_ISR_SHPF 0x00000008U
+#define RTC_ISR_WUTWF 0x00000004U
+#define RTC_ISR_ALRBWF 0x00000002U
+#define RTC_ISR_ALRAWF 0x00000001U
+
+/******************** Bits definition for RTC_PRER register *****************/
+#define RTC_PRER_PREDIV_A 0x007F0000U
+#define RTC_PRER_PREDIV_S 0x00007FFFU
+
+/******************** Bits definition for RTC_WUTR register *****************/
+#define RTC_WUTR_WUT 0x0000FFFFU
+
+/******************** Bits definition for RTC_CALIBR register ***************/
+#define RTC_CALIBR_DCS 0x00000080U
+#define RTC_CALIBR_DC 0x0000001FU
+
+/******************** Bits definition for RTC_ALRMAR register ***************/
+#define RTC_ALRMAR_MSK4 0x80000000U
+#define RTC_ALRMAR_WDSEL 0x40000000U
+#define RTC_ALRMAR_DT 0x30000000U
+#define RTC_ALRMAR_DT_0 0x10000000U
+#define RTC_ALRMAR_DT_1 0x20000000U
+#define RTC_ALRMAR_DU 0x0F000000U
+#define RTC_ALRMAR_DU_0 0x01000000U
+#define RTC_ALRMAR_DU_1 0x02000000U
+#define RTC_ALRMAR_DU_2 0x04000000U
+#define RTC_ALRMAR_DU_3 0x08000000U
+#define RTC_ALRMAR_MSK3 0x00800000U
+#define RTC_ALRMAR_PM 0x00400000U
+#define RTC_ALRMAR_HT 0x00300000U
+#define RTC_ALRMAR_HT_0 0x00100000U
+#define RTC_ALRMAR_HT_1 0x00200000U
+#define RTC_ALRMAR_HU 0x000F0000U
+#define RTC_ALRMAR_HU_0 0x00010000U
+#define RTC_ALRMAR_HU_1 0x00020000U
+#define RTC_ALRMAR_HU_2 0x00040000U
+#define RTC_ALRMAR_HU_3 0x00080000U
+#define RTC_ALRMAR_MSK2 0x00008000U
+#define RTC_ALRMAR_MNT 0x00007000U
+#define RTC_ALRMAR_MNT_0 0x00001000U
+#define RTC_ALRMAR_MNT_1 0x00002000U
+#define RTC_ALRMAR_MNT_2 0x00004000U
+#define RTC_ALRMAR_MNU 0x00000F00U
+#define RTC_ALRMAR_MNU_0 0x00000100U
+#define RTC_ALRMAR_MNU_1 0x00000200U
+#define RTC_ALRMAR_MNU_2 0x00000400U
+#define RTC_ALRMAR_MNU_3 0x00000800U
+#define RTC_ALRMAR_MSK1 0x00000080U
+#define RTC_ALRMAR_ST 0x00000070U
+#define RTC_ALRMAR_ST_0 0x00000010U
+#define RTC_ALRMAR_ST_1 0x00000020U
+#define RTC_ALRMAR_ST_2 0x00000040U
+#define RTC_ALRMAR_SU 0x0000000FU
+#define RTC_ALRMAR_SU_0 0x00000001U
+#define RTC_ALRMAR_SU_1 0x00000002U
+#define RTC_ALRMAR_SU_2 0x00000004U
+#define RTC_ALRMAR_SU_3 0x00000008U
+
+/******************** Bits definition for RTC_ALRMBR register ***************/
+#define RTC_ALRMBR_MSK4 0x80000000U
+#define RTC_ALRMBR_WDSEL 0x40000000U
+#define RTC_ALRMBR_DT 0x30000000U
+#define RTC_ALRMBR_DT_0 0x10000000U
+#define RTC_ALRMBR_DT_1 0x20000000U
+#define RTC_ALRMBR_DU 0x0F000000U
+#define RTC_ALRMBR_DU_0 0x01000000U
+#define RTC_ALRMBR_DU_1 0x02000000U
+#define RTC_ALRMBR_DU_2 0x04000000U
+#define RTC_ALRMBR_DU_3 0x08000000U
+#define RTC_ALRMBR_MSK3 0x00800000U
+#define RTC_ALRMBR_PM 0x00400000U
+#define RTC_ALRMBR_HT 0x00300000U
+#define RTC_ALRMBR_HT_0 0x00100000U
+#define RTC_ALRMBR_HT_1 0x00200000U
+#define RTC_ALRMBR_HU 0x000F0000U
+#define RTC_ALRMBR_HU_0 0x00010000U
+#define RTC_ALRMBR_HU_1 0x00020000U
+#define RTC_ALRMBR_HU_2 0x00040000U
+#define RTC_ALRMBR_HU_3 0x00080000U
+#define RTC_ALRMBR_MSK2 0x00008000U
+#define RTC_ALRMBR_MNT 0x00007000U
+#define RTC_ALRMBR_MNT_0 0x00001000U
+#define RTC_ALRMBR_MNT_1 0x00002000U
+#define RTC_ALRMBR_MNT_2 0x00004000U
+#define RTC_ALRMBR_MNU 0x00000F00U
+#define RTC_ALRMBR_MNU_0 0x00000100U
+#define RTC_ALRMBR_MNU_1 0x00000200U
+#define RTC_ALRMBR_MNU_2 0x00000400U
+#define RTC_ALRMBR_MNU_3 0x00000800U
+#define RTC_ALRMBR_MSK1 0x00000080U
+#define RTC_ALRMBR_ST 0x00000070U
+#define RTC_ALRMBR_ST_0 0x00000010U
+#define RTC_ALRMBR_ST_1 0x00000020U
+#define RTC_ALRMBR_ST_2 0x00000040U
+#define RTC_ALRMBR_SU 0x0000000FU
+#define RTC_ALRMBR_SU_0 0x00000001U
+#define RTC_ALRMBR_SU_1 0x00000002U
+#define RTC_ALRMBR_SU_2 0x00000004U
+#define RTC_ALRMBR_SU_3 0x00000008U
+
+/******************** Bits definition for RTC_WPR register ******************/
+#define RTC_WPR_KEY 0x000000FFU
+
+/******************** Bits definition for RTC_SSR register ******************/
+#define RTC_SSR_SS 0x0000FFFFU
+
+/******************** Bits definition for RTC_SHIFTR register ***************/
+#define RTC_SHIFTR_SUBFS 0x00007FFFU
+#define RTC_SHIFTR_ADD1S 0x80000000U
+
+/******************** Bits definition for RTC_TSTR register *****************/
+#define RTC_TSTR_PM 0x00400000U
+#define RTC_TSTR_HT 0x00300000U
+#define RTC_TSTR_HT_0 0x00100000U
+#define RTC_TSTR_HT_1 0x00200000U
+#define RTC_TSTR_HU 0x000F0000U
+#define RTC_TSTR_HU_0 0x00010000U
+#define RTC_TSTR_HU_1 0x00020000U
+#define RTC_TSTR_HU_2 0x00040000U
+#define RTC_TSTR_HU_3 0x00080000U
+#define RTC_TSTR_MNT 0x00007000U
+#define RTC_TSTR_MNT_0 0x00001000U
+#define RTC_TSTR_MNT_1 0x00002000U
+#define RTC_TSTR_MNT_2 0x00004000U
+#define RTC_TSTR_MNU 0x00000F00U
+#define RTC_TSTR_MNU_0 0x00000100U
+#define RTC_TSTR_MNU_1 0x00000200U
+#define RTC_TSTR_MNU_2 0x00000400U
+#define RTC_TSTR_MNU_3 0x00000800U
+#define RTC_TSTR_ST 0x00000070U
+#define RTC_TSTR_ST_0 0x00000010U
+#define RTC_TSTR_ST_1 0x00000020U
+#define RTC_TSTR_ST_2 0x00000040U
+#define RTC_TSTR_SU 0x0000000FU
+#define RTC_TSTR_SU_0 0x00000001U
+#define RTC_TSTR_SU_1 0x00000002U
+#define RTC_TSTR_SU_2 0x00000004U
+#define RTC_TSTR_SU_3 0x00000008U
+
+/******************** Bits definition for RTC_TSDR register *****************/
+#define RTC_TSDR_WDU 0x0000E000U
+#define RTC_TSDR_WDU_0 0x00002000U
+#define RTC_TSDR_WDU_1 0x00004000U
+#define RTC_TSDR_WDU_2 0x00008000U
+#define RTC_TSDR_MT 0x00001000U
+#define RTC_TSDR_MU 0x00000F00U
+#define RTC_TSDR_MU_0 0x00000100U
+#define RTC_TSDR_MU_1 0x00000200U
+#define RTC_TSDR_MU_2 0x00000400U
+#define RTC_TSDR_MU_3 0x00000800U
+#define RTC_TSDR_DT 0x00000030U
+#define RTC_TSDR_DT_0 0x00000010U
+#define RTC_TSDR_DT_1 0x00000020U
+#define RTC_TSDR_DU 0x0000000FU
+#define RTC_TSDR_DU_0 0x00000001U
+#define RTC_TSDR_DU_1 0x00000002U
+#define RTC_TSDR_DU_2 0x00000004U
+#define RTC_TSDR_DU_3 0x00000008U
+
+/******************** Bits definition for RTC_TSSSR register ****************/
+#define RTC_TSSSR_SS 0x0000FFFFU
+
+/******************** Bits definition for RTC_CAL register *****************/
+#define RTC_CALR_CALP 0x00008000U
+#define RTC_CALR_CALW8 0x00004000U
+#define RTC_CALR_CALW16 0x00002000U
+#define RTC_CALR_CALM 0x000001FFU
+#define RTC_CALR_CALM_0 0x00000001U
+#define RTC_CALR_CALM_1 0x00000002U
+#define RTC_CALR_CALM_2 0x00000004U
+#define RTC_CALR_CALM_3 0x00000008U
+#define RTC_CALR_CALM_4 0x00000010U
+#define RTC_CALR_CALM_5 0x00000020U
+#define RTC_CALR_CALM_6 0x00000040U
+#define RTC_CALR_CALM_7 0x00000080U
+#define RTC_CALR_CALM_8 0x00000100U
+
+/******************** Bits definition for RTC_TAFCR register ****************/
+#define RTC_TAFCR_ALARMOUTTYPE 0x00040000U
+#define RTC_TAFCR_TSINSEL 0x00020000U
+#define RTC_TAFCR_TAMPINSEL 0x00010000U
+#define RTC_TAFCR_TAMPPUDIS 0x00008000U
+#define RTC_TAFCR_TAMPPRCH 0x00006000U
+#define RTC_TAFCR_TAMPPRCH_0 0x00002000U
+#define RTC_TAFCR_TAMPPRCH_1 0x00004000U
+#define RTC_TAFCR_TAMPFLT 0x00001800U
+#define RTC_TAFCR_TAMPFLT_0 0x00000800U
+#define RTC_TAFCR_TAMPFLT_1 0x00001000U
+#define RTC_TAFCR_TAMPFREQ 0x00000700U
+#define RTC_TAFCR_TAMPFREQ_0 0x00000100U
+#define RTC_TAFCR_TAMPFREQ_1 0x00000200U
+#define RTC_TAFCR_TAMPFREQ_2 0x00000400U
+#define RTC_TAFCR_TAMPTS 0x00000080U
+#define RTC_TAFCR_TAMP2TRG 0x00000010U
+#define RTC_TAFCR_TAMP2E 0x00000008U
+#define RTC_TAFCR_TAMPIE 0x00000004U
+#define RTC_TAFCR_TAMP1TRG 0x00000002U
+#define RTC_TAFCR_TAMP1E 0x00000001U
+
+/******************** Bits definition for RTC_ALRMASSR register *************/
+#define RTC_ALRMASSR_MASKSS 0x0F000000U
+#define RTC_ALRMASSR_MASKSS_0 0x01000000U
+#define RTC_ALRMASSR_MASKSS_1 0x02000000U
+#define RTC_ALRMASSR_MASKSS_2 0x04000000U
+#define RTC_ALRMASSR_MASKSS_3 0x08000000U
+#define RTC_ALRMASSR_SS 0x00007FFFU
+
+/******************** Bits definition for RTC_ALRMBSSR register *************/
+#define RTC_ALRMBSSR_MASKSS 0x0F000000U
+#define RTC_ALRMBSSR_MASKSS_0 0x01000000U
+#define RTC_ALRMBSSR_MASKSS_1 0x02000000U
+#define RTC_ALRMBSSR_MASKSS_2 0x04000000U
+#define RTC_ALRMBSSR_MASKSS_3 0x08000000U
+#define RTC_ALRMBSSR_SS 0x00007FFFU
+
+/******************** Bits definition for RTC_BKP0R register ****************/
+#define RTC_BKP0R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP1R register ****************/
+#define RTC_BKP1R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP2R register ****************/
+#define RTC_BKP2R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP3R register ****************/
+#define RTC_BKP3R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP4R register ****************/
+#define RTC_BKP4R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP5R register ****************/
+#define RTC_BKP5R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP6R register ****************/
+#define RTC_BKP6R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP7R register ****************/
+#define RTC_BKP7R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP8R register ****************/
+#define RTC_BKP8R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP9R register ****************/
+#define RTC_BKP9R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP10R register ***************/
+#define RTC_BKP10R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP11R register ***************/
+#define RTC_BKP11R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP12R register ***************/
+#define RTC_BKP12R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP13R register ***************/
+#define RTC_BKP13R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP14R register ***************/
+#define RTC_BKP14R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP15R register ***************/
+#define RTC_BKP15R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP16R register ***************/
+#define RTC_BKP16R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP17R register ***************/
+#define RTC_BKP17R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP18R register ***************/
+#define RTC_BKP18R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP19R register ***************/
+#define RTC_BKP19R 0xFFFFFFFFU
+
+/******************************************************************************/
+/* */
+/* Serial Audio Interface */
+/* */
+/******************************************************************************/
+/******************** Bit definition for SAI_GCR register *******************/
+#define SAI_GCR_SYNCIN 0x00000003U /*!<SYNCIN[1:0] bits (Synchronization Inputs) */
+#define SAI_GCR_SYNCIN_0 0x00000001U /*!<Bit 0 */
+#define SAI_GCR_SYNCIN_1 0x00000002U /*!<Bit 1 */
+
+#define SAI_GCR_SYNCOUT 0x00000030U /*!<SYNCOUT[1:0] bits (Synchronization Outputs) */
+#define SAI_GCR_SYNCOUT_0 0x00000010U /*!<Bit 0 */
+#define SAI_GCR_SYNCOUT_1 0x00000020U /*!<Bit 1 */
+
+/******************* Bit definition for SAI_xCR1 register *******************/
+#define SAI_xCR1_MODE 0x00000003U /*!<MODE[1:0] bits (Audio Block Mode) */
+#define SAI_xCR1_MODE_0 0x00000001U /*!<Bit 0 */
+#define SAI_xCR1_MODE_1 0x00000002U /*!<Bit 1 */
+
+#define SAI_xCR1_PRTCFG 0x0000000CU /*!<PRTCFG[1:0] bits (Protocol Configuration) */
+#define SAI_xCR1_PRTCFG_0 0x00000004U /*!<Bit 0 */
+#define SAI_xCR1_PRTCFG_1 0x00000008U /*!<Bit 1 */
+
+#define SAI_xCR1_DS 0x000000E0U /*!<DS[1:0] bits (Data Size) */
+#define SAI_xCR1_DS_0 0x00000020U /*!<Bit 0 */
+#define SAI_xCR1_DS_1 0x00000040U /*!<Bit 1 */
+#define SAI_xCR1_DS_2 0x00000080U /*!<Bit 2 */
+
+#define SAI_xCR1_LSBFIRST 0x00000100U /*!<LSB First Configuration */
+#define SAI_xCR1_CKSTR 0x00000200U /*!<ClocK STRobing edge */
+
+#define SAI_xCR1_SYNCEN 0x00000C00U /*!<SYNCEN[1:0](SYNChronization ENable) */
+#define SAI_xCR1_SYNCEN_0 0x00000400U /*!<Bit 0 */
+#define SAI_xCR1_SYNCEN_1 0x00000800U /*!<Bit 1 */
+
+#define SAI_xCR1_MONO 0x00001000U /*!<Mono mode */
+#define SAI_xCR1_OUTDRIV 0x00002000U /*!<Output Drive */
+#define SAI_xCR1_SAIEN 0x00010000U /*!<Audio Block enable */
+#define SAI_xCR1_DMAEN 0x00020000U /*!<DMA enable */
+#define SAI_xCR1_NODIV 0x00080000U /*!<No Divider Configuration */
+
+#define SAI_xCR1_MCKDIV 0x00F00000U /*!<MCKDIV[3:0] (Master ClocK Divider) */
+#define SAI_xCR1_MCKDIV_0 0x00100000U /*!<Bit 0 */
+#define SAI_xCR1_MCKDIV_1 0x00200000U /*!<Bit 1 */
+#define SAI_xCR1_MCKDIV_2 0x00400000U /*!<Bit 2 */
+#define SAI_xCR1_MCKDIV_3 0x00800000U /*!<Bit 3 */
+
+/******************* Bit definition for SAI_xCR2 register *******************/
+#define SAI_xCR2_FTH 0x00000007U /*!<FTH[2:0](Fifo THreshold) */
+#define SAI_xCR2_FTH_0 0x00000001U /*!<Bit 0 */
+#define SAI_xCR2_FTH_1 0x00000002U /*!<Bit 1 */
+#define SAI_xCR2_FTH_2 0x00000004U /*!<Bit 2 */
+
+#define SAI_xCR2_FFLUSH 0x00000008U /*!<Fifo FLUSH */
+#define SAI_xCR2_TRIS 0x00000010U /*!<TRIState Management on data line */
+#define SAI_xCR2_MUTE 0x00000020U /*!<Mute mode */
+#define SAI_xCR2_MUTEVAL 0x00000040U /*!<Muate value */
+
+#define SAI_xCR2_MUTECNT 0x00001F80U /*!<MUTECNT[5:0] (MUTE counter) */
+#define SAI_xCR2_MUTECNT_0 0x00000080U /*!<Bit 0 */
+#define SAI_xCR2_MUTECNT_1 0x00000100U /*!<Bit 1 */
+#define SAI_xCR2_MUTECNT_2 0x00000200U /*!<Bit 2 */
+#define SAI_xCR2_MUTECNT_3 0x00000400U /*!<Bit 3 */
+#define SAI_xCR2_MUTECNT_4 0x00000800U /*!<Bit 4 */
+#define SAI_xCR2_MUTECNT_5 0x00001000U /*!<Bit 5 */
+
+#define SAI_xCR2_CPL 0x00002000U /*!< Complement Bit */
+
+#define SAI_xCR2_COMP 0x0000C000U /*!<COMP[1:0] (Companding mode) */
+#define SAI_xCR2_COMP_0 0x00004000U /*!<Bit 0 */
+#define SAI_xCR2_COMP_1 0x00008000U /*!<Bit 1 */
+
+/****************** Bit definition for SAI_xFRCR register *******************/
+#define SAI_xFRCR_FRL 0x000000FFU /*!<FRL[1:0](Frame length) */
+#define SAI_xFRCR_FRL_0 0x00000001U /*!<Bit 0 */
+#define SAI_xFRCR_FRL_1 0x00000002U /*!<Bit 1 */
+#define SAI_xFRCR_FRL_2 0x00000004U /*!<Bit 2 */
+#define SAI_xFRCR_FRL_3 0x00000008U /*!<Bit 3 */
+#define SAI_xFRCR_FRL_4 0x00000010U /*!<Bit 4 */
+#define SAI_xFRCR_FRL_5 0x00000020U /*!<Bit 5 */
+#define SAI_xFRCR_FRL_6 0x00000040U /*!<Bit 6 */
+#define SAI_xFRCR_FRL_7 0x00000080U /*!<Bit 7 */
+
+#define SAI_xFRCR_FSALL 0x00007F00U /*!<FRL[1:0] (Frame synchronization active level length) */
+#define SAI_xFRCR_FSALL_0 0x00000100U /*!<Bit 0 */
+#define SAI_xFRCR_FSALL_1 0x00000200U /*!<Bit 1 */
+#define SAI_xFRCR_FSALL_2 0x00000400U /*!<Bit 2 */
+#define SAI_xFRCR_FSALL_3 0x00000800U /*!<Bit 3 */
+#define SAI_xFRCR_FSALL_4 0x00001000U /*!<Bit 4 */
+#define SAI_xFRCR_FSALL_5 0x00002000U /*!<Bit 5 */
+#define SAI_xFRCR_FSALL_6 0x00004000U /*!<Bit 6 */
+
+#define SAI_xFRCR_FSDEF 0x00010000U /*!< Frame Synchronization Definition */
+#define SAI_xFRCR_FSPOL 0x00020000U /*!<Frame Synchronization POLarity */
+#define SAI_xFRCR_FSOFF 0x00040000U /*!<Frame Synchronization OFFset */
+/* Legacy defines */
+#define SAI_xFRCR_FSPO SAI_xFRCR_FSPOL
+
+/****************** Bit definition for SAI_xSLOTR register *******************/
+#define SAI_xSLOTR_FBOFF 0x0000001FU /*!<FRL[4:0](First Bit Offset) */
+#define SAI_xSLOTR_FBOFF_0 0x00000001U /*!<Bit 0 */
+#define SAI_xSLOTR_FBOFF_1 0x00000002U /*!<Bit 1 */
+#define SAI_xSLOTR_FBOFF_2 0x00000004U /*!<Bit 2 */
+#define SAI_xSLOTR_FBOFF_3 0x00000008U /*!<Bit 3 */
+#define SAI_xSLOTR_FBOFF_4 0x00000010U /*!<Bit 4 */
+
+#define SAI_xSLOTR_SLOTSZ 0x000000C0U /*!<SLOTSZ[1:0] (Slot size) */
+#define SAI_xSLOTR_SLOTSZ_0 0x00000040U /*!<Bit 0 */
+#define SAI_xSLOTR_SLOTSZ_1 0x00000080U /*!<Bit 1 */
+
+#define SAI_xSLOTR_NBSLOT 0x00000F00U /*!<NBSLOT[3:0] (Number of Slot in audio Frame) */
+#define SAI_xSLOTR_NBSLOT_0 0x00000100U /*!<Bit 0 */
+#define SAI_xSLOTR_NBSLOT_1 0x00000200U /*!<Bit 1 */
+#define SAI_xSLOTR_NBSLOT_2 0x00000400U /*!<Bit 2 */
+#define SAI_xSLOTR_NBSLOT_3 0x00000800U /*!<Bit 3 */
+
+#define SAI_xSLOTR_SLOTEN 0xFFFF0000U /*!<SLOTEN[15:0] (Slot Enable) */
+
+/******************* Bit definition for SAI_xIMR register *******************/
+#define SAI_xIMR_OVRUDRIE 0x00000001U /*!<Overrun underrun interrupt enable */
+#define SAI_xIMR_MUTEDETIE 0x00000002U /*!<Mute detection interrupt enable */
+#define SAI_xIMR_WCKCFGIE 0x00000004U /*!<Wrong Clock Configuration interrupt enable */
+#define SAI_xIMR_FREQIE 0x00000008U /*!<FIFO request interrupt enable */
+#define SAI_xIMR_CNRDYIE 0x00000010U /*!<Codec not ready interrupt enable */
+#define SAI_xIMR_AFSDETIE 0x00000020U /*!<Anticipated frame synchronization detection interrupt enable */
+#define SAI_xIMR_LFSDETIE 0x00000040U /*!<Late frame synchronization detection interrupt enable */
+
+/******************** Bit definition for SAI_xSR register *******************/
+#define SAI_xSR_OVRUDR 0x00000001U /*!<Overrun underrun */
+#define SAI_xSR_MUTEDET 0x00000002U /*!<Mute detection */
+#define SAI_xSR_WCKCFG 0x00000004U /*!<Wrong Clock Configuration */
+#define SAI_xSR_FREQ 0x00000008U /*!<FIFO request */
+#define SAI_xSR_CNRDY 0x00000010U /*!<Codec not ready */
+#define SAI_xSR_AFSDET 0x00000020U /*!<Anticipated frame synchronization detection */
+#define SAI_xSR_LFSDET 0x00000040U /*!<Late frame synchronization detection */
+
+#define SAI_xSR_FLVL 0x00070000U /*!<FLVL[2:0] (FIFO Level Threshold) */
+#define SAI_xSR_FLVL_0 0x00010000U /*!<Bit 0 */
+#define SAI_xSR_FLVL_1 0x00020000U /*!<Bit 1 */
+#define SAI_xSR_FLVL_2 0x00040000U /*!<Bit 2 */
+
+/****************** Bit definition for SAI_xCLRFR register ******************/
+#define SAI_xCLRFR_COVRUDR 0x00000001U /*!<Clear Overrun underrun */
+#define SAI_xCLRFR_CMUTEDET 0x00000002U /*!<Clear Mute detection */
+#define SAI_xCLRFR_CWCKCFG 0x00000004U /*!<Clear Wrong Clock Configuration */
+#define SAI_xCLRFR_CFREQ 0x00000008U /*!<Clear FIFO request */
+#define SAI_xCLRFR_CCNRDY 0x00000010U /*!<Clear Codec not ready */
+#define SAI_xCLRFR_CAFSDET 0x00000020U /*!<Clear Anticipated frame synchronization detection */
+#define SAI_xCLRFR_CLFSDET 0x00000040U /*!<Clear Late frame synchronization detection */
+
+/****************** Bit definition for SAI_xDR register ******************/
+#define SAI_xDR_DATA 0xFFFFFFFFU
+
+
+/******************************************************************************/
+/* */
+/* SD host Interface */
+/* */
+/******************************************************************************/
+/****************** Bit definition for SDIO_POWER register ******************/
+#define SDIO_POWER_PWRCTRL 0x03U /*!<PWRCTRL[1:0] bits (Power supply control bits) */
+#define SDIO_POWER_PWRCTRL_0 0x01U /*!<Bit 0 */
+#define SDIO_POWER_PWRCTRL_1 0x02U /*!<Bit 1 */
+
+/****************** Bit definition for SDIO_CLKCR register ******************/
+#define SDIO_CLKCR_CLKDIV 0x00FFU /*!<Clock divide factor */
+#define SDIO_CLKCR_CLKEN 0x0100U /*!<Clock enable bit */
+#define SDIO_CLKCR_PWRSAV 0x0200U /*!<Power saving configuration bit */
+#define SDIO_CLKCR_BYPASS 0x0400U /*!<Clock divider bypass enable bit */
+
+#define SDIO_CLKCR_WIDBUS 0x1800U /*!<WIDBUS[1:0] bits (Wide bus mode enable bit) */
+#define SDIO_CLKCR_WIDBUS_0 0x0800U /*!<Bit 0 */
+#define SDIO_CLKCR_WIDBUS_1 0x1000U /*!<Bit 1 */
+
+#define SDIO_CLKCR_NEGEDGE 0x2000U /*!<SDIO_CK dephasing selection bit */
+#define SDIO_CLKCR_HWFC_EN 0x4000U /*!<HW Flow Control enable */
+
+/******************* Bit definition for SDIO_ARG register *******************/
+#define SDIO_ARG_CMDARG 0xFFFFFFFFU /*!<Command argument */
+
+/******************* Bit definition for SDIO_CMD register *******************/
+#define SDIO_CMD_CMDINDEX 0x003FU /*!<Command Index */
+
+#define SDIO_CMD_WAITRESP 0x00C0U /*!<WAITRESP[1:0] bits (Wait for response bits) */
+#define SDIO_CMD_WAITRESP_0 0x0040U /*!< Bit 0 */
+#define SDIO_CMD_WAITRESP_1 0x0080U /*!< Bit 1 */
+
+#define SDIO_CMD_WAITINT 0x0100U /*!<CPSM Waits for Interrupt Request */
+#define SDIO_CMD_WAITPEND 0x0200U /*!<CPSM Waits for ends of data transfer (CmdPend internal signal) */
+#define SDIO_CMD_CPSMEN 0x0400U /*!<Command path state machine (CPSM) Enable bit */
+#define SDIO_CMD_SDIOSUSPEND 0x0800U /*!<SD I/O suspend command */
+#define SDIO_CMD_ENCMDCOMPL 0x1000U /*!<Enable CMD completion */
+#define SDIO_CMD_NIEN 0x2000U /*!<Not Interrupt Enable */
+#define SDIO_CMD_CEATACMD 0x4000U /*!<CE-ATA command */
+
+/***************** Bit definition for SDIO_RESPCMD register *****************/
+#define SDIO_RESPCMD_RESPCMD 0x3FU /*!<Response command index */
+
+/****************** Bit definition for SDIO_RESP0 register ******************/
+#define SDIO_RESP0_CARDSTATUS0 0xFFFFFFFFU /*!<Card Status */
+
+/****************** Bit definition for SDIO_RESP1 register ******************/
+#define SDIO_RESP1_CARDSTATUS1 0xFFFFFFFFU /*!<Card Status */
+
+/****************** Bit definition for SDIO_RESP2 register ******************/
+#define SDIO_RESP2_CARDSTATUS2 0xFFFFFFFFU /*!<Card Status */
+
+/****************** Bit definition for SDIO_RESP3 register ******************/
+#define SDIO_RESP3_CARDSTATUS3 0xFFFFFFFFU /*!<Card Status */
+
+/****************** Bit definition for SDIO_RESP4 register ******************/
+#define SDIO_RESP4_CARDSTATUS4 0xFFFFFFFFU /*!<Card Status */
+
+/****************** Bit definition for SDIO_DTIMER register *****************/
+#define SDIO_DTIMER_DATATIME 0xFFFFFFFFU /*!<Data timeout period. */
+
+/****************** Bit definition for SDIO_DLEN register *******************/
+#define SDIO_DLEN_DATALENGTH 0x01FFFFFFU /*!<Data length value */
+
+/****************** Bit definition for SDIO_DCTRL register ******************/
+#define SDIO_DCTRL_DTEN 0x0001U /*!<Data transfer enabled bit */
+#define SDIO_DCTRL_DTDIR 0x0002U /*!<Data transfer direction selection */
+#define SDIO_DCTRL_DTMODE 0x0004U /*!<Data transfer mode selection */
+#define SDIO_DCTRL_DMAEN 0x0008U /*!<DMA enabled bit */
+
+#define SDIO_DCTRL_DBLOCKSIZE 0x00F0U /*!<DBLOCKSIZE[3:0] bits (Data block size) */
+#define SDIO_DCTRL_DBLOCKSIZE_0 0x0010U /*!<Bit 0 */
+#define SDIO_DCTRL_DBLOCKSIZE_1 0x0020U /*!<Bit 1 */
+#define SDIO_DCTRL_DBLOCKSIZE_2 0x0040U /*!<Bit 2 */
+#define SDIO_DCTRL_DBLOCKSIZE_3 0x0080U /*!<Bit 3 */
+
+#define SDIO_DCTRL_RWSTART 0x0100U /*!<Read wait start */
+#define SDIO_DCTRL_RWSTOP 0x0200U /*!<Read wait stop */
+#define SDIO_DCTRL_RWMOD 0x0400U /*!<Read wait mode */
+#define SDIO_DCTRL_SDIOEN 0x0800U /*!<SD I/O enable functions */
+
+/****************** Bit definition for SDIO_DCOUNT register *****************/
+#define SDIO_DCOUNT_DATACOUNT 0x01FFFFFFU /*!<Data count value */
+
+/****************** Bit definition for SDIO_STA register ********************/
+#define SDIO_STA_CCRCFAIL 0x00000001U /*!<Command response received (CRC check failed) */
+#define SDIO_STA_DCRCFAIL 0x00000002U /*!<Data block sent/received (CRC check failed) */
+#define SDIO_STA_CTIMEOUT 0x00000004U /*!<Command response timeout */
+#define SDIO_STA_DTIMEOUT 0x00000008U /*!<Data timeout */
+#define SDIO_STA_TXUNDERR 0x00000010U /*!<Transmit FIFO underrun error */
+#define SDIO_STA_RXOVERR 0x00000020U /*!<Received FIFO overrun error */
+#define SDIO_STA_CMDREND 0x00000040U /*!<Command response received (CRC check passed) */
+#define SDIO_STA_CMDSENT 0x00000080U /*!<Command sent (no response required) */
+#define SDIO_STA_DATAEND 0x00000100U /*!<Data end (data counter, SDIDCOUNT, is zero) */
+#define SDIO_STA_STBITERR 0x00000200U /*!<Start bit not detected on all data signals in wide bus mode */
+#define SDIO_STA_DBCKEND 0x00000400U /*!<Data block sent/received (CRC check passed) */
+#define SDIO_STA_CMDACT 0x00000800U /*!<Command transfer in progress */
+#define SDIO_STA_TXACT 0x00001000U /*!<Data transmit in progress */
+#define SDIO_STA_RXACT 0x00002000U /*!<Data receive in progress */
+#define SDIO_STA_TXFIFOHE 0x00004000U /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
+#define SDIO_STA_RXFIFOHF 0x00008000U /*!<Receive FIFO Half Full: there are at least 8 words in the FIFO */
+#define SDIO_STA_TXFIFOF 0x00010000U /*!<Transmit FIFO full */
+#define SDIO_STA_RXFIFOF 0x00020000U /*!<Receive FIFO full */
+#define SDIO_STA_TXFIFOE 0x00040000U /*!<Transmit FIFO empty */
+#define SDIO_STA_RXFIFOE 0x00080000U /*!<Receive FIFO empty */
+#define SDIO_STA_TXDAVL 0x00100000U /*!<Data available in transmit FIFO */
+#define SDIO_STA_RXDAVL 0x00200000U /*!<Data available in receive FIFO */
+#define SDIO_STA_SDIOIT 0x00400000U /*!<SDIO interrupt received */
+#define SDIO_STA_CEATAEND 0x00800000U /*!<CE-ATA command completion signal received for CMD61 */
+
+/******************* Bit definition for SDIO_ICR register *******************/
+#define SDIO_ICR_CCRCFAILC 0x00000001U /*!<CCRCFAIL flag clear bit */
+#define SDIO_ICR_DCRCFAILC 0x00000002U /*!<DCRCFAIL flag clear bit */
+#define SDIO_ICR_CTIMEOUTC 0x00000004U /*!<CTIMEOUT flag clear bit */
+#define SDIO_ICR_DTIMEOUTC 0x00000008U /*!<DTIMEOUT flag clear bit */
+#define SDIO_ICR_TXUNDERRC 0x00000010U /*!<TXUNDERR flag clear bit */
+#define SDIO_ICR_RXOVERRC 0x00000020U /*!<RXOVERR flag clear bit */
+#define SDIO_ICR_CMDRENDC 0x00000040U /*!<CMDREND flag clear bit */
+#define SDIO_ICR_CMDSENTC 0x00000080U /*!<CMDSENT flag clear bit */
+#define SDIO_ICR_DATAENDC 0x00000100U /*!<DATAEND flag clear bit */
+#define SDIO_ICR_STBITERRC 0x00000200U /*!<STBITERR flag clear bit */
+#define SDIO_ICR_DBCKENDC 0x00000400U /*!<DBCKEND flag clear bit */
+#define SDIO_ICR_SDIOITC 0x00400000U /*!<SDIOIT flag clear bit */
+#define SDIO_ICR_CEATAENDC 0x00800000U /*!<CEATAEND flag clear bit */
+
+/****************** Bit definition for SDIO_MASK register *******************/
+#define SDIO_MASK_CCRCFAILIE 0x00000001U /*!<Command CRC Fail Interrupt Enable */
+#define SDIO_MASK_DCRCFAILIE 0x00000002U /*!<Data CRC Fail Interrupt Enable */
+#define SDIO_MASK_CTIMEOUTIE 0x00000004U /*!<Command TimeOut Interrupt Enable */
+#define SDIO_MASK_DTIMEOUTIE 0x00000008U /*!<Data TimeOut Interrupt Enable */
+#define SDIO_MASK_TXUNDERRIE 0x00000010U /*!<Tx FIFO UnderRun Error Interrupt Enable */
+#define SDIO_MASK_RXOVERRIE 0x00000020U /*!<Rx FIFO OverRun Error Interrupt Enable */
+#define SDIO_MASK_CMDRENDIE 0x00000040U /*!<Command Response Received Interrupt Enable */
+#define SDIO_MASK_CMDSENTIE 0x00000080U /*!<Command Sent Interrupt Enable */
+#define SDIO_MASK_DATAENDIE 0x00000100U /*!<Data End Interrupt Enable */
+#define SDIO_MASK_STBITERRIE 0x00000200U /*!<Start Bit Error Interrupt Enable */
+#define SDIO_MASK_DBCKENDIE 0x00000400U /*!<Data Block End Interrupt Enable */
+#define SDIO_MASK_CMDACTIE 0x00000800U /*!<CCommand Acting Interrupt Enable */
+#define SDIO_MASK_TXACTIE 0x00001000U /*!<Data Transmit Acting Interrupt Enable */
+#define SDIO_MASK_RXACTIE 0x00002000U /*!<Data receive acting interrupt enabled */
+#define SDIO_MASK_TXFIFOHEIE 0x00004000U /*!<Tx FIFO Half Empty interrupt Enable */
+#define SDIO_MASK_RXFIFOHFIE 0x00008000U /*!<Rx FIFO Half Full interrupt Enable */
+#define SDIO_MASK_TXFIFOFIE 0x00010000U /*!<Tx FIFO Full interrupt Enable */
+#define SDIO_MASK_RXFIFOFIE 0x00020000U /*!<Rx FIFO Full interrupt Enable */
+#define SDIO_MASK_TXFIFOEIE 0x00040000U /*!<Tx FIFO Empty interrupt Enable */
+#define SDIO_MASK_RXFIFOEIE 0x00080000U /*!<Rx FIFO Empty interrupt Enable */
+#define SDIO_MASK_TXDAVLIE 0x00100000U /*!<Data available in Tx FIFO interrupt Enable */
+#define SDIO_MASK_RXDAVLIE 0x00200000U /*!<Data available in Rx FIFO interrupt Enable */
+#define SDIO_MASK_SDIOITIE 0x00400000U /*!<SDIO Mode Interrupt Received interrupt Enable */
+#define SDIO_MASK_CEATAENDIE 0x00800000U /*!<CE-ATA command completion signal received Interrupt Enable */
+
+/***************** Bit definition for SDIO_FIFOCNT register *****************/
+#define SDIO_FIFOCNT_FIFOCOUNT 0x00FFFFFFU /*!<Remaining number of words to be written to or read from the FIFO */
+
+/****************** Bit definition for SDIO_FIFO register *******************/
+#define SDIO_FIFO_FIFODATA 0xFFFFFFFFU /*!<Receive and transmit FIFO data */
+
+/******************************************************************************/
+/* */
+/* Serial Peripheral Interface */
+/* */
+/******************************************************************************/
+/******************* Bit definition for SPI_CR1 register ********************/
+#define SPI_CR1_CPHA 0x00000001U /*!<Clock Phase */
+#define SPI_CR1_CPOL 0x00000002U /*!<Clock Polarity */
+#define SPI_CR1_MSTR 0x00000004U /*!<Master Selection */
+
+#define SPI_CR1_BR 0x00000038U /*!<BR[2:0] bits (Baud Rate Control) */
+#define SPI_CR1_BR_0 0x00000008U /*!<Bit 0 */
+#define SPI_CR1_BR_1 0x00000010U /*!<Bit 1 */
+#define SPI_CR1_BR_2 0x00000020U /*!<Bit 2 */
+
+#define SPI_CR1_SPE 0x00000040U /*!<SPI Enable */
+#define SPI_CR1_LSBFIRST 0x00000080U /*!<Frame Format */
+#define SPI_CR1_SSI 0x00000100U /*!<Internal slave select */
+#define SPI_CR1_SSM 0x00000200U /*!<Software slave management */
+#define SPI_CR1_RXONLY 0x00000400U /*!<Receive only */
+#define SPI_CR1_DFF 0x00000800U /*!<Data Frame Format */
+#define SPI_CR1_CRCNEXT 0x00001000U /*!<Transmit CRC next */
+#define SPI_CR1_CRCEN 0x00002000U /*!<Hardware CRC calculation enable */
+#define SPI_CR1_BIDIOE 0x00004000U /*!<Output enable in bidirectional mode */
+#define SPI_CR1_BIDIMODE 0x00008000U /*!<Bidirectional data mode enable */
+
+/******************* Bit definition for SPI_CR2 register ********************/
+#define SPI_CR2_RXDMAEN 0x00000001U /*!<Rx Buffer DMA Enable */
+#define SPI_CR2_TXDMAEN 0x00000002U /*!<Tx Buffer DMA Enable */
+#define SPI_CR2_SSOE 0x00000004U /*!<SS Output Enable */
+#define SPI_CR2_FRF 0x00000010U /*!<Frame Format */
+#define SPI_CR2_ERRIE 0x00000020U /*!<Error Interrupt Enable */
+#define SPI_CR2_RXNEIE 0x00000040U /*!<RX buffer Not Empty Interrupt Enable */
+#define SPI_CR2_TXEIE 0x00000080U /*!<Tx buffer Empty Interrupt Enable */
+
+/******************** Bit definition for SPI_SR register ********************/
+#define SPI_SR_RXNE 0x00000001U /*!<Receive buffer Not Empty */
+#define SPI_SR_TXE 0x00000002U /*!<Transmit buffer Empty */
+#define SPI_SR_CHSIDE 0x00000004U /*!<Channel side */
+#define SPI_SR_UDR 0x00000008U /*!<Underrun flag */
+#define SPI_SR_CRCERR 0x00000010U /*!<CRC Error flag */
+#define SPI_SR_MODF 0x00000020U /*!<Mode fault */
+#define SPI_SR_OVR 0x00000040U /*!<Overrun flag */
+#define SPI_SR_BSY 0x00000080U /*!<Busy flag */
+#define SPI_SR_FRE 0x00000100U /*!<Frame format error flag */
+
+/******************** Bit definition for SPI_DR register ********************/
+#define SPI_DR_DR 0x0000FFFFU /*!<Data Register */
+
+/******************* Bit definition for SPI_CRCPR register ******************/
+#define SPI_CRCPR_CRCPOLY 0x0000FFFFU /*!<CRC polynomial register */
+
+/****************** Bit definition for SPI_RXCRCR register ******************/
+#define SPI_RXCRCR_RXCRC 0x0000FFFFU /*!<Rx CRC Register */
+
+/****************** Bit definition for SPI_TXCRCR register ******************/
+#define SPI_TXCRCR_TXCRC 0x0000FFFFU /*!<Tx CRC Register */
+
+/****************** Bit definition for SPI_I2SCFGR register *****************/
+#define SPI_I2SCFGR_CHLEN 0x00000001U /*!<Channel length (number of bits per audio channel) */
+
+#define SPI_I2SCFGR_DATLEN 0x00000006U /*!<DATLEN[1:0] bits (Data length to be transferred) */
+#define SPI_I2SCFGR_DATLEN_0 0x00000002U /*!<Bit 0 */
+#define SPI_I2SCFGR_DATLEN_1 0x00000004U /*!<Bit 1 */
+
+#define SPI_I2SCFGR_CKPOL 0x00000008U /*!<steady state clock polarity */
+
+#define SPI_I2SCFGR_I2SSTD 0x00000030U /*!<I2SSTD[1:0] bits (I2S standard selection) */
+#define SPI_I2SCFGR_I2SSTD_0 0x00000010U /*!<Bit 0 */
+#define SPI_I2SCFGR_I2SSTD_1 0x00000020U /*!<Bit 1 */
+
+#define SPI_I2SCFGR_PCMSYNC 0x00000080U /*!<PCM frame synchronization */
+
+#define SPI_I2SCFGR_I2SCFG 0x00000300U /*!<I2SCFG[1:0] bits (I2S configuration mode) */
+#define SPI_I2SCFGR_I2SCFG_0 0x00000100U /*!<Bit 0 */
+#define SPI_I2SCFGR_I2SCFG_1 0x00000200U /*!<Bit 1 */
+
+#define SPI_I2SCFGR_I2SE 0x00000400U /*!<I2S Enable */
+#define SPI_I2SCFGR_I2SMOD 0x00000800U /*!<I2S mode selection */
+
+/****************** Bit definition for SPI_I2SPR register *******************/
+#define SPI_I2SPR_I2SDIV 0x000000FFU /*!<I2S Linear prescaler */
+#define SPI_I2SPR_ODD 0x00000100U /*!<Odd factor for the prescaler */
+#define SPI_I2SPR_MCKOE 0x00000200U /*!<Master Clock Output Enable */
+
+/******************************************************************************/
+/* */
+/* SYSCFG */
+/* */
+/******************************************************************************/
+/****************** Bit definition for SYSCFG_MEMRMP register ***************/
+#define SYSCFG_MEMRMP_MEM_MODE 0x00000007U /*!< SYSCFG_Memory Remap Config */
+#define SYSCFG_MEMRMP_MEM_MODE_0 0x00000001U
+#define SYSCFG_MEMRMP_MEM_MODE_1 0x00000002U
+#define SYSCFG_MEMRMP_MEM_MODE_2 0x00000004U
+
+#define SYSCFG_MEMRMP_UFB_MODE 0x00000100U /*!< User Flash Bank mode */
+#define SYSCFG_SWP_FMC 0x00000C00U /*!< FMC memory mapping swap */
+
+/****************** Bit definition for SYSCFG_PMC register ******************/
+#define SYSCFG_PMC_ADCxDC2 0x00070000U /*!< Refer to AN4073 on how to use this bit */
+#define SYSCFG_PMC_ADC1DC2 0x00010000U /*!< Refer to AN4073 on how to use this bit */
+#define SYSCFG_PMC_ADC2DC2 0x00020000U /*!< Refer to AN4073 on how to use this bit */
+#define SYSCFG_PMC_ADC3DC2 0x00040000U /*!< Refer to AN4073 on how to use this bit */
+
+#define SYSCFG_PMC_MII_RMII_SEL 0x00800000U /*!<Ethernet PHY interface selection */
+/* Old MII_RMII_SEL bit definition, maintained for legacy purpose */
+#define SYSCFG_PMC_MII_RMII SYSCFG_PMC_MII_RMII_SEL
+
+/***************** Bit definition for SYSCFG_EXTICR1 register ***************/
+#define SYSCFG_EXTICR1_EXTI0 0x000FU /*!<EXTI 0 configuration */
+#define SYSCFG_EXTICR1_EXTI1 0x00F0U /*!<EXTI 1 configuration */
+#define SYSCFG_EXTICR1_EXTI2 0x0F00U /*!<EXTI 2 configuration */
+#define SYSCFG_EXTICR1_EXTI3 0xF000U /*!<EXTI 3 configuration */
+/**
+ * @brief EXTI0 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI0_PA 0x0000U /*!<PA[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PB 0x0001U /*!<PB[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PC 0x0002U /*!<PC[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PD 0x0003U /*!<PD[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PE 0x0004U /*!<PE[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PF 0x0005U /*!<PF[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PG 0x0006U /*!<PG[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PH 0x0007U /*!<PH[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PI 0x0008U /*!<PI[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PJ 0x0009U /*!<PJ[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PK 0x000AU /*!<PK[0] pin */
+
+/**
+ * @brief EXTI1 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI1_PA 0x0000U /*!<PA[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PB 0x0010U /*!<PB[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PC 0x0020U /*!<PC[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PD 0x0030U /*!<PD[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PE 0x0040U /*!<PE[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PF 0x0050U /*!<PF[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PG 0x0060U /*!<PG[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PH 0x0070U /*!<PH[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PI 0x0080U /*!<PI[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PJ 0x0090U /*!<PJ[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PK 0x00A0U /*!<PK[1] pin */
+
+
+/**
+ * @brief EXTI2 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI2_PA 0x0000U /*!<PA[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PB 0x0100U /*!<PB[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PC 0x0200U /*!<PC[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PD 0x0300U /*!<PD[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PE 0x0400U /*!<PE[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PF 0x0500U /*!<PF[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PG 0x0600U /*!<PG[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PH 0x0700U /*!<PH[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PI 0x0800U /*!<PI[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PJ 0x0900U /*!<PJ[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PK 0x0A00U /*!<PK[2] pin */
+
+
+/**
+ * @brief EXTI3 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI3_PA 0x0000U /*!<PA[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PB 0x1000U /*!<PB[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PC 0x2000U /*!<PC[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PD 0x3000U /*!<PD[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PE 0x4000U /*!<PE[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PF 0x5000U /*!<PF[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PG 0x6000U /*!<PG[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PH 0x7000U /*!<PH[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PI 0x8000U /*!<PI[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PJ 0x9000U /*!<PJ[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PK 0xA000U /*!<PK[3] pin */
+
+
+/***************** Bit definition for SYSCFG_EXTICR2 register ***************/
+#define SYSCFG_EXTICR2_EXTI4 0x000FU /*!<EXTI 4 configuration */
+#define SYSCFG_EXTICR2_EXTI5 0x00F0U /*!<EXTI 5 configuration */
+#define SYSCFG_EXTICR2_EXTI6 0x0F00U /*!<EXTI 6 configuration */
+#define SYSCFG_EXTICR2_EXTI7 0xF000U /*!<EXTI 7 configuration */
+/**
+ * @brief EXTI4 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI4_PA 0x0000U /*!<PA[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PB 0x0001U /*!<PB[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PC 0x0002U /*!<PC[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PD 0x0003U /*!<PD[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PE 0x0004U /*!<PE[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PF 0x0005U /*!<PF[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PG 0x0006U /*!<PG[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PH 0x0007U /*!<PH[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PI 0x0008U /*!<PI[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PJ 0x0009U /*!<PJ[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PK 0x000AU /*!<PK[4] pin */
+
+/**
+ * @brief EXTI5 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI5_PA 0x0000U /*!<PA[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PB 0x0010U /*!<PB[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PC 0x0020U /*!<PC[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PD 0x0030U /*!<PD[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PE 0x0040U /*!<PE[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PF 0x0050U /*!<PF[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PG 0x0060U /*!<PG[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PH 0x0070U /*!<PH[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PI 0x0080U /*!<PI[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PJ 0x0090U /*!<PJ[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PK 0x00A0U /*!<PK[5] pin */
+
+/**
+ * @brief EXTI6 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI6_PA 0x0000U /*!<PA[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PB 0x0100U /*!<PB[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PC 0x0200U /*!<PC[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PD 0x0300U /*!<PD[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PE 0x0400U /*!<PE[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PF 0x0500U /*!<PF[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PG 0x0600U /*!<PG[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PH 0x0700U /*!<PH[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PI 0x0800U /*!<PI[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PJ 0x0900U /*!<PJ[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PK 0x0A00U /*!<PK[6] pin */
+
+
+/**
+ * @brief EXTI7 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI7_PA 0x0000U /*!<PA[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PB 0x1000U /*!<PB[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PC 0x2000U /*!<PC[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PD 0x3000U /*!<PD[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PE 0x4000U /*!<PE[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PF 0x5000U /*!<PF[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PG 0x6000U /*!<PG[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PH 0x7000U /*!<PH[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PI 0x8000U /*!<PI[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PJ 0x9000U /*!<PJ[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PK 0xA000U /*!<PK[7] pin */
+
+/***************** Bit definition for SYSCFG_EXTICR3 register ***************/
+#define SYSCFG_EXTICR3_EXTI8 0x000FU /*!<EXTI 8 configuration */
+#define SYSCFG_EXTICR3_EXTI9 0x00F0U /*!<EXTI 9 configuration */
+#define SYSCFG_EXTICR3_EXTI10 0x0F00U /*!<EXTI 10 configuration */
+#define SYSCFG_EXTICR3_EXTI11 0xF000U /*!<EXTI 11 configuration */
+
+/**
+ * @brief EXTI8 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI8_PA 0x0000U /*!<PA[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PB 0x0001U /*!<PB[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PC 0x0002U /*!<PC[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PD 0x0003U /*!<PD[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PE 0x0004U /*!<PE[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PF 0x0005U /*!<PF[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PG 0x0006U /*!<PG[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PH 0x0007U /*!<PH[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PI 0x0008U /*!<PI[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PJ 0x0009U /*!<PJ[8] pin */
+
+/**
+ * @brief EXTI9 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI9_PA 0x0000U /*!<PA[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PB 0x0010U /*!<PB[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PC 0x0020U /*!<PC[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PD 0x0030U /*!<PD[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PE 0x0040U /*!<PE[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PF 0x0050U /*!<PF[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PG 0x0060U /*!<PG[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PH 0x0070U /*!<PH[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PI 0x0080U /*!<PI[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PJ 0x0090U /*!<PJ[9] pin */
+
+
+/**
+ * @brief EXTI10 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI10_PA 0x0000U /*!<PA[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PB 0x0100U /*!<PB[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PC 0x0200U /*!<PC[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PD 0x0300U /*!<PD[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PE 0x0400U /*!<PE[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PF 0x0500U /*!<PF[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PG 0x0600U /*!<PG[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PH 0x0700U /*!<PH[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PI 0x0800U /*!<PI[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PJ 0x0900U /*!<PJ[10] pin */
+
+
+/**
+ * @brief EXTI11 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI11_PA 0x0000U /*!<PA[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PB 0x1000U /*!<PB[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PC 0x2000U /*!<PC[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PD 0x3000U /*!<PD[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PE 0x4000U /*!<PE[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PF 0x5000U /*!<PF[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PG 0x6000U /*!<PG[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PH 0x7000U /*!<PH[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PI 0x8000U /*!<PI[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PJ 0x9000U /*!<PJ[11] pin */
+
+
+/***************** Bit definition for SYSCFG_EXTICR4 register ***************/
+#define SYSCFG_EXTICR4_EXTI12 0x000FU /*!<EXTI 12 configuration */
+#define SYSCFG_EXTICR4_EXTI13 0x00F0U /*!<EXTI 13 configuration */
+#define SYSCFG_EXTICR4_EXTI14 0x0F00U /*!<EXTI 14 configuration */
+#define SYSCFG_EXTICR4_EXTI15 0xF000U /*!<EXTI 15 configuration */
+/**
+ * @brief EXTI12 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI12_PA 0x0000U /*!<PA[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PB 0x0001U /*!<PB[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PC 0x0002U /*!<PC[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PD 0x0003U /*!<PD[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PE 0x0004U /*!<PE[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PF 0x0005U /*!<PF[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PG 0x0006U /*!<PG[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PH 0x0007U /*!<PH[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PI 0x0008U /*!<PI[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PJ 0x0009U /*!<PJ[12] pin */
+
+
+/**
+ * @brief EXTI13 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI13_PA 0x0000U /*!<PA[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PB 0x0010U /*!<PB[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PC 0x0020U /*!<PC[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PD 0x0030U /*!<PD[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PE 0x0040U /*!<PE[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PF 0x0050U /*!<PF[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PG 0x0060U /*!<PG[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PH 0x0070U /*!<PH[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PI 0x0008U /*!<PI[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PJ 0x0009U /*!<PJ[13] pin */
+
+
+/**
+ * @brief EXTI14 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI14_PA 0x0000U /*!<PA[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PB 0x0100U /*!<PB[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PC 0x0200U /*!<PC[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PD 0x0300U /*!<PD[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PE 0x0400U /*!<PE[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PF 0x0500U /*!<PF[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PG 0x0600U /*!<PG[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PH 0x0700U /*!<PH[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PI 0x0800U /*!<PI[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PJ 0x0900U /*!<PJ[14] pin */
+
+
+/**
+ * @brief EXTI15 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI15_PA 0x0000U /*!<PA[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PB 0x1000U /*!<PB[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PC 0x2000U /*!<PC[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PD 0x3000U /*!<PD[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PE 0x4000U /*!<PE[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PF 0x5000U /*!<PF[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PG 0x6000U /*!<PG[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PH 0x7000U /*!<PH[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PI 0x8000U /*!<PI[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PJ 0x9000U /*!<PJ[15] pin */
+
+/****************** Bit definition for SYSCFG_CMPCR register ****************/
+#define SYSCFG_CMPCR_CMP_PD 0x00000001U /*!<Compensation cell ready flag */
+#define SYSCFG_CMPCR_READY 0x00000100U /*!<Compensation cell power-down */
+
+/******************************************************************************/
+/* */
+/* TIM */
+/* */
+/******************************************************************************/
+/******************* Bit definition for TIM_CR1 register ********************/
+#define TIM_CR1_CEN 0x0001U /*!<Counter enable */
+#define TIM_CR1_UDIS 0x0002U /*!<Update disable */
+#define TIM_CR1_URS 0x0004U /*!<Update request source */
+#define TIM_CR1_OPM 0x0008U /*!<One pulse mode */
+#define TIM_CR1_DIR 0x0010U /*!<Direction */
+
+#define TIM_CR1_CMS 0x0060U /*!<CMS[1:0] bits (Center-aligned mode selection) */
+#define TIM_CR1_CMS_0 0x0020U /*!<Bit 0 */
+#define TIM_CR1_CMS_1 0x0040U /*!<Bit 1 */
+
+#define TIM_CR1_ARPE 0x0080U /*!<Auto-reload preload enable */
+
+#define TIM_CR1_CKD 0x0300U /*!<CKD[1:0] bits (clock division) */
+#define TIM_CR1_CKD_0 0x0100U /*!<Bit 0 */
+#define TIM_CR1_CKD_1 0x0200U /*!<Bit 1 */
+
+/******************* Bit definition for TIM_CR2 register ********************/
+#define TIM_CR2_CCPC 0x0001U /*!<Capture/Compare Preloaded Control */
+#define TIM_CR2_CCUS 0x0004U /*!<Capture/Compare Control Update Selection */
+#define TIM_CR2_CCDS 0x0008U /*!<Capture/Compare DMA Selection */
+
+#define TIM_CR2_MMS 0x0070U /*!<MMS[2:0] bits (Master Mode Selection) */
+#define TIM_CR2_MMS_0 0x0010U /*!<Bit 0 */
+#define TIM_CR2_MMS_1 0x0020U /*!<Bit 1 */
+#define TIM_CR2_MMS_2 0x0040U /*!<Bit 2 */
+
+#define TIM_CR2_TI1S 0x0080U /*!<TI1 Selection */
+#define TIM_CR2_OIS1 0x0100U /*!<Output Idle state 1 (OC1 output) */
+#define TIM_CR2_OIS1N 0x0200U /*!<Output Idle state 1 (OC1N output) */
+#define TIM_CR2_OIS2 0x0400U /*!<Output Idle state 2 (OC2 output) */
+#define TIM_CR2_OIS2N 0x0800U /*!<Output Idle state 2 (OC2N output) */
+#define TIM_CR2_OIS3 0x1000U /*!<Output Idle state 3 (OC3 output) */
+#define TIM_CR2_OIS3N 0x2000U /*!<Output Idle state 3 (OC3N output) */
+#define TIM_CR2_OIS4 0x4000U /*!<Output Idle state 4 (OC4 output) */
+
+/******************* Bit definition for TIM_SMCR register *******************/
+#define TIM_SMCR_SMS 0x0007U /*!<SMS[2:0] bits (Slave mode selection) */
+#define TIM_SMCR_SMS_0 0x0001U /*!<Bit 0 */
+#define TIM_SMCR_SMS_1 0x0002U /*!<Bit 1 */
+#define TIM_SMCR_SMS_2 0x0004U /*!<Bit 2 */
+
+#define TIM_SMCR_TS 0x0070U /*!<TS[2:0] bits (Trigger selection) */
+#define TIM_SMCR_TS_0 0x0010U /*!<Bit 0 */
+#define TIM_SMCR_TS_1 0x0020U /*!<Bit 1 */
+#define TIM_SMCR_TS_2 0x0040U /*!<Bit 2 */
+
+#define TIM_SMCR_MSM 0x0080U /*!<Master/slave mode */
+
+#define TIM_SMCR_ETF 0x0F00U /*!<ETF[3:0] bits (External trigger filter) */
+#define TIM_SMCR_ETF_0 0x0100U /*!<Bit 0 */
+#define TIM_SMCR_ETF_1 0x0200U /*!<Bit 1 */
+#define TIM_SMCR_ETF_2 0x0400U /*!<Bit 2 */
+#define TIM_SMCR_ETF_3 0x0800U /*!<Bit 3 */
+
+#define TIM_SMCR_ETPS 0x3000U /*!<ETPS[1:0] bits (External trigger prescaler) */
+#define TIM_SMCR_ETPS_0 0x1000U /*!<Bit 0 */
+#define TIM_SMCR_ETPS_1 0x2000U /*!<Bit 1 */
+
+#define TIM_SMCR_ECE 0x4000U /*!<External clock enable */
+#define TIM_SMCR_ETP 0x8000U /*!<External trigger polarity */
+
+/******************* Bit definition for TIM_DIER register *******************/
+#define TIM_DIER_UIE 0x0001U /*!<Update interrupt enable */
+#define TIM_DIER_CC1IE 0x0002U /*!<Capture/Compare 1 interrupt enable */
+#define TIM_DIER_CC2IE 0x0004U /*!<Capture/Compare 2 interrupt enable */
+#define TIM_DIER_CC3IE 0x0008U /*!<Capture/Compare 3 interrupt enable */
+#define TIM_DIER_CC4IE 0x0010U /*!<Capture/Compare 4 interrupt enable */
+#define TIM_DIER_COMIE 0x0020U /*!<COM interrupt enable */
+#define TIM_DIER_TIE 0x0040U /*!<Trigger interrupt enable */
+#define TIM_DIER_BIE 0x0080U /*!<Break interrupt enable */
+#define TIM_DIER_UDE 0x0100U /*!<Update DMA request enable */
+#define TIM_DIER_CC1DE 0x0200U /*!<Capture/Compare 1 DMA request enable */
+#define TIM_DIER_CC2DE 0x0400U /*!<Capture/Compare 2 DMA request enable */
+#define TIM_DIER_CC3DE 0x0800U /*!<Capture/Compare 3 DMA request enable */
+#define TIM_DIER_CC4DE 0x1000U /*!<Capture/Compare 4 DMA request enable */
+#define TIM_DIER_COMDE 0x2000U /*!<COM DMA request enable */
+#define TIM_DIER_TDE 0x4000U /*!<Trigger DMA request enable */
+
+/******************** Bit definition for TIM_SR register ********************/
+#define TIM_SR_UIF 0x0001U /*!<Update interrupt Flag */
+#define TIM_SR_CC1IF 0x0002U /*!<Capture/Compare 1 interrupt Flag */
+#define TIM_SR_CC2IF 0x0004U /*!<Capture/Compare 2 interrupt Flag */
+#define TIM_SR_CC3IF 0x0008U /*!<Capture/Compare 3 interrupt Flag */
+#define TIM_SR_CC4IF 0x0010U /*!<Capture/Compare 4 interrupt Flag */
+#define TIM_SR_COMIF 0x0020U /*!<COM interrupt Flag */
+#define TIM_SR_TIF 0x0040U /*!<Trigger interrupt Flag */
+#define TIM_SR_BIF 0x0080U /*!<Break interrupt Flag */
+#define TIM_SR_CC1OF 0x0200U /*!<Capture/Compare 1 Overcapture Flag */
+#define TIM_SR_CC2OF 0x0400U /*!<Capture/Compare 2 Overcapture Flag */
+#define TIM_SR_CC3OF 0x0800U /*!<Capture/Compare 3 Overcapture Flag */
+#define TIM_SR_CC4OF 0x1000U /*!<Capture/Compare 4 Overcapture Flag */
+
+/******************* Bit definition for TIM_EGR register ********************/
+#define TIM_EGR_UG 0x01U /*!<Update Generation */
+#define TIM_EGR_CC1G 0x02U /*!<Capture/Compare 1 Generation */
+#define TIM_EGR_CC2G 0x04U /*!<Capture/Compare 2 Generation */
+#define TIM_EGR_CC3G 0x08U /*!<Capture/Compare 3 Generation */
+#define TIM_EGR_CC4G 0x10U /*!<Capture/Compare 4 Generation */
+#define TIM_EGR_COMG 0x20U /*!<Capture/Compare Control Update Generation */
+#define TIM_EGR_TG 0x40U /*!<Trigger Generation */
+#define TIM_EGR_BG 0x80U /*!<Break Generation */
+
+/****************** Bit definition for TIM_CCMR1 register *******************/
+#define TIM_CCMR1_CC1S 0x0003U /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
+#define TIM_CCMR1_CC1S_0 0x0001U /*!<Bit 0 */
+#define TIM_CCMR1_CC1S_1 0x0002U /*!<Bit 1 */
+
+#define TIM_CCMR1_OC1FE 0x0004U /*!<Output Compare 1 Fast enable */
+#define TIM_CCMR1_OC1PE 0x0008U /*!<Output Compare 1 Preload enable */
+
+#define TIM_CCMR1_OC1M 0x0070U /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
+#define TIM_CCMR1_OC1M_0 0x0010U /*!<Bit 0 */
+#define TIM_CCMR1_OC1M_1 0x0020U /*!<Bit 1 */
+#define TIM_CCMR1_OC1M_2 0x0040U /*!<Bit 2 */
+
+#define TIM_CCMR1_OC1CE 0x0080U /*!<Output Compare 1Clear Enable */
+
+#define TIM_CCMR1_CC2S 0x0300U /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
+#define TIM_CCMR1_CC2S_0 0x0100U /*!<Bit 0 */
+#define TIM_CCMR1_CC2S_1 0x0200U /*!<Bit 1 */
+
+#define TIM_CCMR1_OC2FE 0x0400U /*!<Output Compare 2 Fast enable */
+#define TIM_CCMR1_OC2PE 0x0800U /*!<Output Compare 2 Preload enable */
+
+#define TIM_CCMR1_OC2M 0x7000U /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
+#define TIM_CCMR1_OC2M_0 0x1000U /*!<Bit 0 */
+#define TIM_CCMR1_OC2M_1 0x2000U /*!<Bit 1 */
+#define TIM_CCMR1_OC2M_2 0x4000U /*!<Bit 2 */
+
+#define TIM_CCMR1_OC2CE 0x8000U /*!<Output Compare 2 Clear Enable */
+
+/*----------------------------------------------------------------------------*/
+
+#define TIM_CCMR1_IC1PSC 0x000CU /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
+#define TIM_CCMR1_IC1PSC_0 0x0004U /*!<Bit 0 */
+#define TIM_CCMR1_IC1PSC_1 0x0008U /*!<Bit 1 */
+
+#define TIM_CCMR1_IC1F 0x00F0U /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
+#define TIM_CCMR1_IC1F_0 0x0010U /*!<Bit 0 */
+#define TIM_CCMR1_IC1F_1 0x0020U /*!<Bit 1 */
+#define TIM_CCMR1_IC1F_2 0x0040U /*!<Bit 2 */
+#define TIM_CCMR1_IC1F_3 0x0080U /*!<Bit 3 */
+
+#define TIM_CCMR1_IC2PSC 0x0C00U /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
+#define TIM_CCMR1_IC2PSC_0 0x0400U /*!<Bit 0 */
+#define TIM_CCMR1_IC2PSC_1 0x0800U /*!<Bit 1 */
+
+#define TIM_CCMR1_IC2F 0xF000U /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
+#define TIM_CCMR1_IC2F_0 0x1000U /*!<Bit 0 */
+#define TIM_CCMR1_IC2F_1 0x2000U /*!<Bit 1 */
+#define TIM_CCMR1_IC2F_2 0x4000U /*!<Bit 2 */
+#define TIM_CCMR1_IC2F_3 0x8000U /*!<Bit 3 */
+
+/****************** Bit definition for TIM_CCMR2 register *******************/
+#define TIM_CCMR2_CC3S 0x0003U /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
+#define TIM_CCMR2_CC3S_0 0x0001U /*!<Bit 0 */
+#define TIM_CCMR2_CC3S_1 0x0002U /*!<Bit 1 */
+
+#define TIM_CCMR2_OC3FE 0x0004U /*!<Output Compare 3 Fast enable */
+#define TIM_CCMR2_OC3PE 0x0008U /*!<Output Compare 3 Preload enable */
+
+#define TIM_CCMR2_OC3M 0x0070U /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
+#define TIM_CCMR2_OC3M_0 0x0010U /*!<Bit 0 */
+#define TIM_CCMR2_OC3M_1 0x0020U /*!<Bit 1 */
+#define TIM_CCMR2_OC3M_2 0x0040U /*!<Bit 2 */
+
+#define TIM_CCMR2_OC3CE 0x0080U /*!<Output Compare 3 Clear Enable */
+
+#define TIM_CCMR2_CC4S 0x0300U /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
+#define TIM_CCMR2_CC4S_0 0x0100U /*!<Bit 0 */
+#define TIM_CCMR2_CC4S_1 0x0200U /*!<Bit 1 */
+
+#define TIM_CCMR2_OC4FE 0x0400U /*!<Output Compare 4 Fast enable */
+#define TIM_CCMR2_OC4PE 0x0800U /*!<Output Compare 4 Preload enable */
+
+#define TIM_CCMR2_OC4M 0x7000U /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
+#define TIM_CCMR2_OC4M_0 0x1000U /*!<Bit 0 */
+#define TIM_CCMR2_OC4M_1 0x2000U /*!<Bit 1 */
+#define TIM_CCMR2_OC4M_2 0x4000U /*!<Bit 2 */
+
+#define TIM_CCMR2_OC4CE 0x8000U /*!<Output Compare 4 Clear Enable */
+
+/*----------------------------------------------------------------------------*/
+
+#define TIM_CCMR2_IC3PSC 0x000CU /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
+#define TIM_CCMR2_IC3PSC_0 0x0004U /*!<Bit 0 */
+#define TIM_CCMR2_IC3PSC_1 0x0008U /*!<Bit 1 */
+
+#define TIM_CCMR2_IC3F 0x00F0U /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
+#define TIM_CCMR2_IC3F_0 0x0010U /*!<Bit 0 */
+#define TIM_CCMR2_IC3F_1 0x0020U /*!<Bit 1 */
+#define TIM_CCMR2_IC3F_2 0x0040U /*!<Bit 2 */
+#define TIM_CCMR2_IC3F_3 0x0080U /*!<Bit 3 */
+
+#define TIM_CCMR2_IC4PSC 0x0C00U /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
+#define TIM_CCMR2_IC4PSC_0 0x0400U /*!<Bit 0 */
+#define TIM_CCMR2_IC4PSC_1 0x0800U /*!<Bit 1 */
+
+#define TIM_CCMR2_IC4F 0xF000U /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
+#define TIM_CCMR2_IC4F_0 0x1000U /*!<Bit 0 */
+#define TIM_CCMR2_IC4F_1 0x2000U /*!<Bit 1 */
+#define TIM_CCMR2_IC4F_2 0x4000U /*!<Bit 2 */
+#define TIM_CCMR2_IC4F_3 0x8000U /*!<Bit 3 */
+
+/******************* Bit definition for TIM_CCER register *******************/
+#define TIM_CCER_CC1E 0x0001U /*!<Capture/Compare 1 output enable */
+#define TIM_CCER_CC1P 0x0002U /*!<Capture/Compare 1 output Polarity */
+#define TIM_CCER_CC1NE 0x0004U /*!<Capture/Compare 1 Complementary output enable */
+#define TIM_CCER_CC1NP 0x0008U /*!<Capture/Compare 1 Complementary output Polarity */
+#define TIM_CCER_CC2E 0x0010U /*!<Capture/Compare 2 output enable */
+#define TIM_CCER_CC2P 0x0020U /*!<Capture/Compare 2 output Polarity */
+#define TIM_CCER_CC2NE 0x0040U /*!<Capture/Compare 2 Complementary output enable */
+#define TIM_CCER_CC2NP 0x0080U /*!<Capture/Compare 2 Complementary output Polarity */
+#define TIM_CCER_CC3E 0x0100U /*!<Capture/Compare 3 output enable */
+#define TIM_CCER_CC3P 0x0200U /*!<Capture/Compare 3 output Polarity */
+#define TIM_CCER_CC3NE 0x0400U /*!<Capture/Compare 3 Complementary output enable */
+#define TIM_CCER_CC3NP 0x0800U /*!<Capture/Compare 3 Complementary output Polarity */
+#define TIM_CCER_CC4E 0x1000U /*!<Capture/Compare 4 output enable */
+#define TIM_CCER_CC4P 0x2000U /*!<Capture/Compare 4 output Polarity */
+#define TIM_CCER_CC4NP 0x8000U /*!<Capture/Compare 4 Complementary output Polarity */
+
+/******************* Bit definition for TIM_CNT register ********************/
+#define TIM_CNT_CNT 0xFFFFU /*!<Counter Value */
+
+/******************* Bit definition for TIM_PSC register ********************/
+#define TIM_PSC_PSC 0xFFFFU /*!<Prescaler Value */
+
+/******************* Bit definition for TIM_ARR register ********************/
+#define TIM_ARR_ARR 0xFFFFU /*!<actual auto-reload Value */
+
+/******************* Bit definition for TIM_RCR register ********************/
+#define TIM_RCR_REP 0xFFU /*!<Repetition Counter Value */
+
+/******************* Bit definition for TIM_CCR1 register *******************/
+#define TIM_CCR1_CCR1 0xFFFFU /*!<Capture/Compare 1 Value */
+
+/******************* Bit definition for TIM_CCR2 register *******************/
+#define TIM_CCR2_CCR2 0xFFFFU /*!<Capture/Compare 2 Value */
+
+/******************* Bit definition for TIM_CCR3 register *******************/
+#define TIM_CCR3_CCR3 0xFFFFU /*!<Capture/Compare 3 Value */
+
+/******************* Bit definition for TIM_CCR4 register *******************/
+#define TIM_CCR4_CCR4 0xFFFFU /*!<Capture/Compare 4 Value */
+
+/******************* Bit definition for TIM_BDTR register *******************/
+#define TIM_BDTR_DTG 0x00FFU /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
+#define TIM_BDTR_DTG_0 0x0001U /*!<Bit 0 */
+#define TIM_BDTR_DTG_1 0x0002U /*!<Bit 1 */
+#define TIM_BDTR_DTG_2 0x0004U /*!<Bit 2 */
+#define TIM_BDTR_DTG_3 0x0008U /*!<Bit 3 */
+#define TIM_BDTR_DTG_4 0x0010U /*!<Bit 4 */
+#define TIM_BDTR_DTG_5 0x0020U /*!<Bit 5 */
+#define TIM_BDTR_DTG_6 0x0040U /*!<Bit 6 */
+#define TIM_BDTR_DTG_7 0x0080U /*!<Bit 7 */
+
+#define TIM_BDTR_LOCK 0x0300U /*!<LOCK[1:0] bits (Lock Configuration) */
+#define TIM_BDTR_LOCK_0 0x0100U /*!<Bit 0 */
+#define TIM_BDTR_LOCK_1 0x0200U /*!<Bit 1 */
+
+#define TIM_BDTR_OSSI 0x0400U /*!<Off-State Selection for Idle mode */
+#define TIM_BDTR_OSSR 0x0800U /*!<Off-State Selection for Run mode */
+#define TIM_BDTR_BKE 0x1000U /*!<Break enable */
+#define TIM_BDTR_BKP 0x2000U /*!<Break Polarity */
+#define TIM_BDTR_AOE 0x4000U /*!<Automatic Output enable */
+#define TIM_BDTR_MOE 0x8000U /*!<Main Output enable */
+
+/******************* Bit definition for TIM_DCR register ********************/
+#define TIM_DCR_DBA 0x001FU /*!<DBA[4:0] bits (DMA Base Address) */
+#define TIM_DCR_DBA_0 0x0001U /*!<Bit 0 */
+#define TIM_DCR_DBA_1 0x0002U /*!<Bit 1 */
+#define TIM_DCR_DBA_2 0x0004U /*!<Bit 2 */
+#define TIM_DCR_DBA_3 0x0008U /*!<Bit 3 */
+#define TIM_DCR_DBA_4 0x0010U /*!<Bit 4 */
+
+#define TIM_DCR_DBL 0x1F00U /*!<DBL[4:0] bits (DMA Burst Length) */
+#define TIM_DCR_DBL_0 0x0100U /*!<Bit 0 */
+#define TIM_DCR_DBL_1 0x0200U /*!<Bit 1 */
+#define TIM_DCR_DBL_2 0x0400U /*!<Bit 2 */
+#define TIM_DCR_DBL_3 0x0800U /*!<Bit 3 */
+#define TIM_DCR_DBL_4 0x1000U /*!<Bit 4 */
+
+/******************* Bit definition for TIM_DMAR register *******************/
+#define TIM_DMAR_DMAB 0xFFFFU /*!<DMA register for burst accesses */
+
+/******************* Bit definition for TIM_OR register *********************/
+#define TIM_OR_TI4_RMP 0x00C0U /*!<TI4_RMP[1:0] bits (TIM5 Input 4 remap) */
+#define TIM_OR_TI4_RMP_0 0x0040U /*!<Bit 0 */
+#define TIM_OR_TI4_RMP_1 0x0080U /*!<Bit 1 */
+#define TIM_OR_ITR1_RMP 0x0C00U /*!<ITR1_RMP[1:0] bits (TIM2 Internal trigger 1 remap) */
+#define TIM_OR_ITR1_RMP_0 0x0400U /*!<Bit 0 */
+#define TIM_OR_ITR1_RMP_1 0x0800U /*!<Bit 1 */
+
+
+/******************************************************************************/
+/* */
+/* Universal Synchronous Asynchronous Receiver Transmitter */
+/* */
+/******************************************************************************/
+/******************* Bit definition for USART_SR register *******************/
+#define USART_SR_PE 0x0001U /*!<Parity Error */
+#define USART_SR_FE 0x0002U /*!<Framing Error */
+#define USART_SR_NE 0x0004U /*!<Noise Error Flag */
+#define USART_SR_ORE 0x0008U /*!<OverRun Error */
+#define USART_SR_IDLE 0x0010U /*!<IDLE line detected */
+#define USART_SR_RXNE 0x0020U /*!<Read Data Register Not Empty */
+#define USART_SR_TC 0x0040U /*!<Transmission Complete */
+#define USART_SR_TXE 0x0080U /*!<Transmit Data Register Empty */
+#define USART_SR_LBD 0x0100U /*!<LIN Break Detection Flag */
+#define USART_SR_CTS 0x0200U /*!<CTS Flag */
+
+/******************* Bit definition for USART_DR register *******************/
+#define USART_DR_DR 0x01FFU /*!<Data value */
+
+/****************** Bit definition for USART_BRR register *******************/
+#define USART_BRR_DIV_Fraction 0x000FU /*!<Fraction of USARTDIV */
+#define USART_BRR_DIV_Mantissa 0xFFF0U /*!<Mantissa of USARTDIV */
+
+/****************** Bit definition for USART_CR1 register *******************/
+#define USART_CR1_SBK 0x0001U /*!<Send Break */
+#define USART_CR1_RWU 0x0002U /*!<Receiver wakeup */
+#define USART_CR1_RE 0x0004U /*!<Receiver Enable */
+#define USART_CR1_TE 0x0008U /*!<Transmitter Enable */
+#define USART_CR1_IDLEIE 0x0010U /*!<IDLE Interrupt Enable */
+#define USART_CR1_RXNEIE 0x0020U /*!<RXNE Interrupt Enable */
+#define USART_CR1_TCIE 0x0040U /*!<Transmission Complete Interrupt Enable */
+#define USART_CR1_TXEIE 0x0080U /*!<PE Interrupt Enable */
+#define USART_CR1_PEIE 0x0100U /*!<PE Interrupt Enable */
+#define USART_CR1_PS 0x0200U /*!<Parity Selection */
+#define USART_CR1_PCE 0x0400U /*!<Parity Control Enable */
+#define USART_CR1_WAKE 0x0800U /*!<Wakeup method */
+#define USART_CR1_M 0x1000U /*!<Word length */
+#define USART_CR1_UE 0x2000U /*!<USART Enable */
+#define USART_CR1_OVER8 0x8000U /*!<USART Oversampling by 8 enable */
+
+/****************** Bit definition for USART_CR2 register *******************/
+#define USART_CR2_ADD 0x000FU /*!<Address of the USART node */
+#define USART_CR2_LBDL 0x0020U /*!<LIN Break Detection Length */
+#define USART_CR2_LBDIE 0x0040U /*!<LIN Break Detection Interrupt Enable */
+#define USART_CR2_LBCL 0x0100U /*!<Last Bit Clock pulse */
+#define USART_CR2_CPHA 0x0200U /*!<Clock Phase */
+#define USART_CR2_CPOL 0x0400U /*!<Clock Polarity */
+#define USART_CR2_CLKEN 0x0800U /*!<Clock Enable */
+
+#define USART_CR2_STOP 0x3000U /*!<STOP[1:0] bits (STOP bits) */
+#define USART_CR2_STOP_0 0x1000U /*!<Bit 0 */
+#define USART_CR2_STOP_1 0x2000U /*!<Bit 1 */
+
+#define USART_CR2_LINEN 0x4000U /*!<LIN mode enable */
+
+/****************** Bit definition for USART_CR3 register *******************/
+#define USART_CR3_EIE 0x0001U /*!<Error Interrupt Enable */
+#define USART_CR3_IREN 0x0002U /*!<IrDA mode Enable */
+#define USART_CR3_IRLP 0x0004U /*!<IrDA Low-Power */
+#define USART_CR3_HDSEL 0x0008U /*!<Half-Duplex Selection */
+#define USART_CR3_NACK 0x0010U /*!<Smartcard NACK enable */
+#define USART_CR3_SCEN 0x0020U /*!<Smartcard mode enable */
+#define USART_CR3_DMAR 0x0040U /*!<DMA Enable Receiver */
+#define USART_CR3_DMAT 0x0080U /*!<DMA Enable Transmitter */
+#define USART_CR3_RTSE 0x0100U /*!<RTS Enable */
+#define USART_CR3_CTSE 0x0200U /*!<CTS Enable */
+#define USART_CR3_CTSIE 0x0400U /*!<CTS Interrupt Enable */
+#define USART_CR3_ONEBIT 0x0800U /*!<USART One bit method enable */
+
+/****************** Bit definition for USART_GTPR register ******************/
+#define USART_GTPR_PSC 0x00FFU /*!<PSC[7:0] bits (Prescaler value) */
+#define USART_GTPR_PSC_0 0x0001U /*!<Bit 0 */
+#define USART_GTPR_PSC_1 0x0002U /*!<Bit 1 */
+#define USART_GTPR_PSC_2 0x0004U /*!<Bit 2 */
+#define USART_GTPR_PSC_3 0x0008U /*!<Bit 3 */
+#define USART_GTPR_PSC_4 0x0010U /*!<Bit 4 */
+#define USART_GTPR_PSC_5 0x0020U /*!<Bit 5 */
+#define USART_GTPR_PSC_6 0x0040U /*!<Bit 6 */
+#define USART_GTPR_PSC_7 0x0080U /*!<Bit 7 */
+
+#define USART_GTPR_GT 0xFF00U /*!<Guard time value */
+
+/******************************************************************************/
+/* */
+/* Window WATCHDOG */
+/* */
+/******************************************************************************/
+/******************* Bit definition for WWDG_CR register ********************/
+#define WWDG_CR_T 0x7FU /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
+#define WWDG_CR_T_0 0x01U /*!<Bit 0 */
+#define WWDG_CR_T_1 0x02U /*!<Bit 1 */
+#define WWDG_CR_T_2 0x04U /*!<Bit 2 */
+#define WWDG_CR_T_3 0x08U /*!<Bit 3 */
+#define WWDG_CR_T_4 0x10U /*!<Bit 4 */
+#define WWDG_CR_T_5 0x20U /*!<Bit 5 */
+#define WWDG_CR_T_6 0x40U /*!<Bit 6 */
+/* Legacy defines */
+#define WWDG_CR_T0 WWDG_CR_T_0
+#define WWDG_CR_T1 WWDG_CR_T_1
+#define WWDG_CR_T2 WWDG_CR_T_2
+#define WWDG_CR_T3 WWDG_CR_T_3
+#define WWDG_CR_T4 WWDG_CR_T_4
+#define WWDG_CR_T5 WWDG_CR_T_5
+#define WWDG_CR_T6 WWDG_CR_T_6
+
+#define WWDG_CR_WDGA 0x80U /*!<Activation bit */
+
+/******************* Bit definition for WWDG_CFR register *******************/
+#define WWDG_CFR_W 0x007FU /*!<W[6:0] bits (7-bit window value) */
+#define WWDG_CFR_W_0 0x0001U /*!<Bit 0 */
+#define WWDG_CFR_W_1 0x0002U /*!<Bit 1 */
+#define WWDG_CFR_W_2 0x0004U /*!<Bit 2 */
+#define WWDG_CFR_W_3 0x0008U /*!<Bit 3 */
+#define WWDG_CFR_W_4 0x0010U /*!<Bit 4 */
+#define WWDG_CFR_W_5 0x0020U /*!<Bit 5 */
+#define WWDG_CFR_W_6 0x0040U /*!<Bit 6 */
+/* Legacy defines */
+#define WWDG_CFR_W0 WWDG_CFR_W_0
+#define WWDG_CFR_W1 WWDG_CFR_W_1
+#define WWDG_CFR_W2 WWDG_CFR_W_2
+#define WWDG_CFR_W3 WWDG_CFR_W_3
+#define WWDG_CFR_W4 WWDG_CFR_W_4
+#define WWDG_CFR_W5 WWDG_CFR_W_5
+#define WWDG_CFR_W6 WWDG_CFR_W_6
+
+#define WWDG_CFR_WDGTB 0x0180U /*!<WDGTB[1:0] bits (Timer Base) */
+#define WWDG_CFR_WDGTB_0 0x0080U /*!<Bit 0 */
+#define WWDG_CFR_WDGTB_1 0x0100U /*!<Bit 1 */
+/* Legacy defines */
+#define WWDG_CFR_WDGTB0 WWDG_CFR_WDGTB_0
+#define WWDG_CFR_WDGTB1 WWDG_CFR_WDGTB_1
+
+#define WWDG_CFR_EWI 0x0200U /*!<Early Wakeup Interrupt */
+
+/******************* Bit definition for WWDG_SR register ********************/
+#define WWDG_SR_EWIF 0x01U /*!<Early Wakeup Interrupt Flag */
+
+
+/******************************************************************************/
+/* */
+/* DBG */
+/* */
+/******************************************************************************/
+/******************** Bit definition for DBGMCU_IDCODE register *************/
+#define DBGMCU_IDCODE_DEV_ID 0x00000FFFU
+#define DBGMCU_IDCODE_REV_ID 0xFFFF0000U
+
+/******************** Bit definition for DBGMCU_CR register *****************/
+#define DBGMCU_CR_DBG_SLEEP 0x00000001U
+#define DBGMCU_CR_DBG_STOP 0x00000002U
+#define DBGMCU_CR_DBG_STANDBY 0x00000004U
+#define DBGMCU_CR_TRACE_IOEN 0x00000020U
+
+#define DBGMCU_CR_TRACE_MODE 0x000000C0U
+#define DBGMCU_CR_TRACE_MODE_0 0x00000040U/*!<Bit 0 */
+#define DBGMCU_CR_TRACE_MODE_1 0x00000080U/*!<Bit 1 */
+
+/******************** Bit definition for DBGMCU_APB1_FZ register ************/
+#define DBGMCU_APB1_FZ_DBG_TIM2_STOP 0x00000001U
+#define DBGMCU_APB1_FZ_DBG_TIM3_STOP 0x00000002U
+#define DBGMCU_APB1_FZ_DBG_TIM4_STOP 0x00000004U
+#define DBGMCU_APB1_FZ_DBG_TIM5_STOP 0x00000008U
+#define DBGMCU_APB1_FZ_DBG_TIM6_STOP 0x00000010U
+#define DBGMCU_APB1_FZ_DBG_TIM7_STOP 0x00000020U
+#define DBGMCU_APB1_FZ_DBG_TIM12_STOP 0x00000040U
+#define DBGMCU_APB1_FZ_DBG_TIM13_STOP 0x00000080U
+#define DBGMCU_APB1_FZ_DBG_TIM14_STOP 0x00000100U
+#define DBGMCU_APB1_FZ_DBG_RTC_STOP 0x00000400U
+#define DBGMCU_APB1_FZ_DBG_WWDG_STOP 0x00000800U
+#define DBGMCU_APB1_FZ_DBG_IWDG_STOP 0x00001000U
+#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT 0x00200000U
+#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT 0x00400000U
+#define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT 0x00800000U
+#define DBGMCU_APB1_FZ_DBG_CAN1_STOP 0x02000000U
+#define DBGMCU_APB1_FZ_DBG_CAN2_STOP 0x04000000U
+/* Old IWDGSTOP bit definition, maintained for legacy purpose */
+#define DBGMCU_APB1_FZ_DBG_IWDEG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP
+
+/******************** Bit definition for DBGMCU_APB2_FZ register ************/
+#define DBGMCU_APB2_FZ_DBG_TIM1_STOP 0x00000001U
+#define DBGMCU_APB2_FZ_DBG_TIM8_STOP 0x00000002U
+#define DBGMCU_APB2_FZ_DBG_TIM9_STOP 0x00010000U
+#define DBGMCU_APB2_FZ_DBG_TIM10_STOP 0x00020000U
+#define DBGMCU_APB2_FZ_DBG_TIM11_STOP 0x00040000U
+
+/******************************************************************************/
+/* */
+/* Ethernet MAC Registers bits definitions */
+/* */
+/******************************************************************************/
+/* Bit definition for Ethernet MAC Control Register register */
+#define ETH_MACCR_WD 0x00800000U /* Watchdog disable */
+#define ETH_MACCR_JD 0x00400000U /* Jabber disable */
+#define ETH_MACCR_IFG 0x000E0000U /* Inter-frame gap */
+#define ETH_MACCR_IFG_96Bit 0x00000000U /* Minimum IFG between frames during transmission is 96Bit */
+ #define ETH_MACCR_IFG_88Bit 0x00020000U /* Minimum IFG between frames during transmission is 88Bit */
+ #define ETH_MACCR_IFG_80Bit 0x00040000U /* Minimum IFG between frames during transmission is 80Bit */
+ #define ETH_MACCR_IFG_72Bit 0x00060000U /* Minimum IFG between frames during transmission is 72Bit */
+ #define ETH_MACCR_IFG_64Bit 0x00080000U /* Minimum IFG between frames during transmission is 64Bit */
+ #define ETH_MACCR_IFG_56Bit 0x000A0000U /* Minimum IFG between frames during transmission is 56Bit */
+ #define ETH_MACCR_IFG_48Bit 0x000C0000U /* Minimum IFG between frames during transmission is 48Bit */
+ #define ETH_MACCR_IFG_40Bit 0x000E0000U /* Minimum IFG between frames during transmission is 40Bit */
+#define ETH_MACCR_CSD 0x00010000U /* Carrier sense disable (during transmission) */
+#define ETH_MACCR_FES 0x00004000U /* Fast ethernet speed */
+#define ETH_MACCR_ROD 0x00002000U /* Receive own disable */
+#define ETH_MACCR_LM 0x00001000U /* loopback mode */
+#define ETH_MACCR_DM 0x00000800U /* Duplex mode */
+#define ETH_MACCR_IPCO 0x00000400U /* IP Checksum offload */
+#define ETH_MACCR_RD 0x00000200U /* Retry disable */
+#define ETH_MACCR_APCS 0x00000080U /* Automatic Pad/CRC stripping */
+#define ETH_MACCR_BL 0x00000060U /* Back-off limit: random integer number (r) of slot time delays before rescheduling
+ a transmission attempt during retries after a collision: 0 =< r <2^k */
+ #define ETH_MACCR_BL_10 0x00000000U /* k = min (n, 10) */
+ #define ETH_MACCR_BL_8 0x00000020U /* k = min (n, 8) */
+ #define ETH_MACCR_BL_4 0x00000040U /* k = min (n, 4) */
+ #define ETH_MACCR_BL_1 0x00000060U /* k = min (n, 1) */
+#define ETH_MACCR_DC 0x00000010U /* Defferal check */
+#define ETH_MACCR_TE 0x00000008U /* Transmitter enable */
+#define ETH_MACCR_RE 0x00000004U /* Receiver enable */
+
+/* Bit definition for Ethernet MAC Frame Filter Register */
+#define ETH_MACFFR_RA 0x80000000U /* Receive all */
+#define ETH_MACFFR_HPF 0x00000400U /* Hash or perfect filter */
+#define ETH_MACFFR_SAF 0x00000200U /* Source address filter enable */
+#define ETH_MACFFR_SAIF 0x00000100U /* SA inverse filtering */
+#define ETH_MACFFR_PCF 0x000000C0U /* Pass control frames: 3 cases */
+ #define ETH_MACFFR_PCF_BlockAll 0x00000040U /* MAC filters all control frames from reaching the application */
+ #define ETH_MACFFR_PCF_ForwardAll 0x00000080U /* MAC forwards all control frames to application even if they fail the Address Filter */
+ #define ETH_MACFFR_PCF_ForwardPassedAddrFilter 0x000000C0U /* MAC forwards control frames that pass the Address Filter. */
+#define ETH_MACFFR_BFD 0x00000020U /* Broadcast frame disable */
+#define ETH_MACFFR_PAM 0x00000010U /* Pass all mutlicast */
+#define ETH_MACFFR_DAIF 0x00000008U /* DA Inverse filtering */
+#define ETH_MACFFR_HM 0x00000004U /* Hash multicast */
+#define ETH_MACFFR_HU 0x00000002U /* Hash unicast */
+#define ETH_MACFFR_PM 0x00000001U /* Promiscuous mode */
+
+/* Bit definition for Ethernet MAC Hash Table High Register */
+#define ETH_MACHTHR_HTH 0xFFFFFFFFU /* Hash table high */
+
+/* Bit definition for Ethernet MAC Hash Table Low Register */
+#define ETH_MACHTLR_HTL 0xFFFFFFFFU /* Hash table low */
+
+/* Bit definition for Ethernet MAC MII Address Register */
+#define ETH_MACMIIAR_PA 0x0000F800U /* Physical layer address */
+#define ETH_MACMIIAR_MR 0x000007C0U /* MII register in the selected PHY */
+#define ETH_MACMIIAR_CR 0x0000001CU /* CR clock range: 6 cases */
+ #define ETH_MACMIIAR_CR_Div42 0x00000000U /* HCLK:60-100 MHz; MDC clock= HCLK/42 */
+ #define ETH_MACMIIAR_CR_Div62 0x00000004U /* HCLK:100-150 MHz; MDC clock= HCLK/62 */
+ #define ETH_MACMIIAR_CR_Div16 0x00000008U /* HCLK:20-35 MHz; MDC clock= HCLK/16 */
+ #define ETH_MACMIIAR_CR_Div26 0x0000000CU /* HCLK:35-60 MHz; MDC clock= HCLK/26 */
+ #define ETH_MACMIIAR_CR_Div102 0x00000010U /* HCLK:150-168 MHz; MDC clock= HCLK/102 */
+#define ETH_MACMIIAR_MW 0x00000002U /* MII write */
+#define ETH_MACMIIAR_MB 0x00000001U /* MII busy */
+
+/* Bit definition for Ethernet MAC MII Data Register */
+#define ETH_MACMIIDR_MD 0x0000FFFFU /* MII data: read/write data from/to PHY */
+
+/* Bit definition for Ethernet MAC Flow Control Register */
+#define ETH_MACFCR_PT 0xFFFF0000U /* Pause time */
+#define ETH_MACFCR_ZQPD 0x00000080U /* Zero-quanta pause disable */
+#define ETH_MACFCR_PLT 0x00000030U /* Pause low threshold: 4 cases */
+ #define ETH_MACFCR_PLT_Minus4 0x00000000U /* Pause time minus 4 slot times */
+ #define ETH_MACFCR_PLT_Minus28 0x00000010U /* Pause time minus 28 slot times */
+ #define ETH_MACFCR_PLT_Minus144 0x00000020U /* Pause time minus 144 slot times */
+ #define ETH_MACFCR_PLT_Minus256 0x00000030U /* Pause time minus 256 slot times */
+#define ETH_MACFCR_UPFD 0x00000008U /* Unicast pause frame detect */
+#define ETH_MACFCR_RFCE 0x00000004U /* Receive flow control enable */
+#define ETH_MACFCR_TFCE 0x00000002U /* Transmit flow control enable */
+#define ETH_MACFCR_FCBBPA 0x00000001U /* Flow control busy/backpressure activate */
+
+/* Bit definition for Ethernet MAC VLAN Tag Register */
+#define ETH_MACVLANTR_VLANTC 0x00010000U /* 12-bit VLAN tag comparison */
+#define ETH_MACVLANTR_VLANTI 0x0000FFFFU /* VLAN tag identifier (for receive frames) */
+
+/* Bit definition for Ethernet MAC Remote Wake-UpFrame Filter Register */
+#define ETH_MACRWUFFR_D 0xFFFFFFFFU /* Wake-up frame filter register data */
+/* Eight sequential Writes to this address (offset 0x28) will write all Wake-UpFrame Filter Registers.
+ Eight sequential Reads from this address (offset 0x28) will read all Wake-UpFrame Filter Registers. */
+/* Wake-UpFrame Filter Reg0 : Filter 0 Byte Mask
+ Wake-UpFrame Filter Reg1 : Filter 1 Byte Mask
+ Wake-UpFrame Filter Reg2 : Filter 2 Byte Mask
+ Wake-UpFrame Filter Reg3 : Filter 3 Byte Mask
+ Wake-UpFrame Filter Reg4 : RSVD - Filter3 Command - RSVD - Filter2 Command -
+ RSVD - Filter1 Command - RSVD - Filter0 Command
+ Wake-UpFrame Filter Re5 : Filter3 Offset - Filter2 Offset - Filter1 Offset - Filter0 Offset
+ Wake-UpFrame Filter Re6 : Filter1 CRC16 - Filter0 CRC16
+ Wake-UpFrame Filter Re7 : Filter3 CRC16 - Filter2 CRC16 */
+
+/* Bit definition for Ethernet MAC PMT Control and Status Register */
+#define ETH_MACPMTCSR_WFFRPR 0x80000000U /* Wake-Up Frame Filter Register Pointer Reset */
+#define ETH_MACPMTCSR_GU 0x00000200U /* Global Unicast */
+#define ETH_MACPMTCSR_WFR 0x00000040U /* Wake-Up Frame Received */
+#define ETH_MACPMTCSR_MPR 0x00000020U /* Magic Packet Received */
+#define ETH_MACPMTCSR_WFE 0x00000004U /* Wake-Up Frame Enable */
+#define ETH_MACPMTCSR_MPE 0x00000002U /* Magic Packet Enable */
+#define ETH_MACPMTCSR_PD 0x00000001U /* Power Down */
+
+/* Bit definition for Ethernet MAC Status Register */
+#define ETH_MACSR_TSTS 0x00000200U /* Time stamp trigger status */
+#define ETH_MACSR_MMCTS 0x00000040U /* MMC transmit status */
+#define ETH_MACSR_MMMCRS 0x00000020U /* MMC receive status */
+#define ETH_MACSR_MMCS 0x00000010U /* MMC status */
+#define ETH_MACSR_PMTS 0x00000008U /* PMT status */
+
+/* Bit definition for Ethernet MAC Interrupt Mask Register */
+#define ETH_MACIMR_TSTIM 0x00000200U /* Time stamp trigger interrupt mask */
+#define ETH_MACIMR_PMTIM 0x00000008U /* PMT interrupt mask */
+
+/* Bit definition for Ethernet MAC Address0 High Register */
+#define ETH_MACA0HR_MACA0H 0x0000FFFFU /* MAC address0 high */
+
+/* Bit definition for Ethernet MAC Address0 Low Register */
+#define ETH_MACA0LR_MACA0L 0xFFFFFFFFU /* MAC address0 low */
+
+/* Bit definition for Ethernet MAC Address1 High Register */
+#define ETH_MACA1HR_AE 0x80000000U /* Address enable */
+#define ETH_MACA1HR_SA 0x40000000U /* Source address */
+#define ETH_MACA1HR_MBC 0x3F000000U /* Mask byte control: bits to mask for comparison of the MAC Address bytes */
+ #define ETH_MACA1HR_MBC_HBits15_8 0x20000000U /* Mask MAC Address high reg bits [15:8] */
+ #define ETH_MACA1HR_MBC_HBits7_0 0x10000000U /* Mask MAC Address high reg bits [7:0] */
+ #define ETH_MACA1HR_MBC_LBits31_24 0x08000000U /* Mask MAC Address low reg bits [31:24] */
+ #define ETH_MACA1HR_MBC_LBits23_16 0x04000000U /* Mask MAC Address low reg bits [23:16] */
+ #define ETH_MACA1HR_MBC_LBits15_8 0x02000000U /* Mask MAC Address low reg bits [15:8] */
+ #define ETH_MACA1HR_MBC_LBits7_0 0x01000000U /* Mask MAC Address low reg bits [7:0] */
+#define ETH_MACA1HR_MACA1H 0x0000FFFFU /* MAC address1 high */
+
+/* Bit definition for Ethernet MAC Address1 Low Register */
+#define ETH_MACA1LR_MACA1L 0xFFFFFFFFU /* MAC address1 low */
+
+/* Bit definition for Ethernet MAC Address2 High Register */
+#define ETH_MACA2HR_AE 0x80000000U /* Address enable */
+#define ETH_MACA2HR_SA 0x40000000U /* Source address */
+#define ETH_MACA2HR_MBC 0x3F000000U /* Mask byte control */
+ #define ETH_MACA2HR_MBC_HBits15_8 0x20000000U /* Mask MAC Address high reg bits [15:8] */
+ #define ETH_MACA2HR_MBC_HBits7_0 0x10000000U /* Mask MAC Address high reg bits [7:0] */
+ #define ETH_MACA2HR_MBC_LBits31_24 0x08000000U /* Mask MAC Address low reg bits [31:24] */
+ #define ETH_MACA2HR_MBC_LBits23_16 0x04000000U /* Mask MAC Address low reg bits [23:16] */
+ #define ETH_MACA2HR_MBC_LBits15_8 0x02000000U /* Mask MAC Address low reg bits [15:8] */
+ #define ETH_MACA2HR_MBC_LBits7_0 0x01000000U /* Mask MAC Address low reg bits [70] */
+#define ETH_MACA2HR_MACA2H 0x0000FFFFU /* MAC address1 high */
+
+/* Bit definition for Ethernet MAC Address2 Low Register */
+#define ETH_MACA2LR_MACA2L 0xFFFFFFFFU /* MAC address2 low */
+
+/* Bit definition for Ethernet MAC Address3 High Register */
+#define ETH_MACA3HR_AE 0x80000000U /* Address enable */
+#define ETH_MACA3HR_SA 0x40000000U /* Source address */
+#define ETH_MACA3HR_MBC 0x3F000000U /* Mask byte control */
+ #define ETH_MACA3HR_MBC_HBits15_8 0x20000000U /* Mask MAC Address high reg bits [15:8] */
+ #define ETH_MACA3HR_MBC_HBits7_0 0x10000000U /* Mask MAC Address high reg bits [7:0] */
+ #define ETH_MACA3HR_MBC_LBits31_24 0x08000000U /* Mask MAC Address low reg bits [31:24] */
+ #define ETH_MACA3HR_MBC_LBits23_16 0x04000000U /* Mask MAC Address low reg bits [23:16] */
+ #define ETH_MACA3HR_MBC_LBits15_8 0x02000000U /* Mask MAC Address low reg bits [15:8] */
+ #define ETH_MACA3HR_MBC_LBits7_0 0x01000000U /* Mask MAC Address low reg bits [70] */
+#define ETH_MACA3HR_MACA3H 0x0000FFFFU /* MAC address3 high */
+
+/* Bit definition for Ethernet MAC Address3 Low Register */
+#define ETH_MACA3LR_MACA3L 0xFFFFFFFFU /* MAC address3 low */
+
+/******************************************************************************/
+/* Ethernet MMC Registers bits definition */
+/******************************************************************************/
+
+/* Bit definition for Ethernet MMC Contol Register */
+#define ETH_MMCCR_MCFHP 0x00000020U /* MMC counter Full-Half preset */
+#define ETH_MMCCR_MCP 0x00000010U /* MMC counter preset */
+#define ETH_MMCCR_MCF 0x00000008U /* MMC Counter Freeze */
+#define ETH_MMCCR_ROR 0x00000004U /* Reset on Read */
+#define ETH_MMCCR_CSR 0x00000002U /* Counter Stop Rollover */
+#define ETH_MMCCR_CR 0x00000001U /* Counters Reset */
+
+/* Bit definition for Ethernet MMC Receive Interrupt Register */
+#define ETH_MMCRIR_RGUFS 0x00020000U /* Set when Rx good unicast frames counter reaches half the maximum value */
+#define ETH_MMCRIR_RFAES 0x00000040U /* Set when Rx alignment error counter reaches half the maximum value */
+#define ETH_MMCRIR_RFCES 0x00000020U /* Set when Rx crc error counter reaches half the maximum value */
+
+/* Bit definition for Ethernet MMC Transmit Interrupt Register */
+#define ETH_MMCTIR_TGFS 0x00200000U /* Set when Tx good frame count counter reaches half the maximum value */
+#define ETH_MMCTIR_TGFMSCS 0x00008000U /* Set when Tx good multi col counter reaches half the maximum value */
+#define ETH_MMCTIR_TGFSCS 0x00004000U /* Set when Tx good single col counter reaches half the maximum value */
+
+/* Bit definition for Ethernet MMC Receive Interrupt Mask Register */
+#define ETH_MMCRIMR_RGUFM 0x00020000U /* Mask the interrupt when Rx good unicast frames counter reaches half the maximum value */
+#define ETH_MMCRIMR_RFAEM 0x00000040U /* Mask the interrupt when when Rx alignment error counter reaches half the maximum value */
+#define ETH_MMCRIMR_RFCEM 0x00000020U /* Mask the interrupt when Rx crc error counter reaches half the maximum value */
+
+/* Bit definition for Ethernet MMC Transmit Interrupt Mask Register */
+#define ETH_MMCTIMR_TGFM 0x00200000U /* Mask the interrupt when Tx good frame count counter reaches half the maximum value */
+#define ETH_MMCTIMR_TGFMSCM 0x00008000U /* Mask the interrupt when Tx good multi col counter reaches half the maximum value */
+#define ETH_MMCTIMR_TGFSCM 0x00004000U /* Mask the interrupt when Tx good single col counter reaches half the maximum value */
+
+/* Bit definition for Ethernet MMC Transmitted Good Frames after Single Collision Counter Register */
+#define ETH_MMCTGFSCCR_TGFSCC 0xFFFFFFFFU /* Number of successfully transmitted frames after a single collision in Half-duplex mode. */
+
+/* Bit definition for Ethernet MMC Transmitted Good Frames after More than a Single Collision Counter Register */
+#define ETH_MMCTGFMSCCR_TGFMSCC 0xFFFFFFFFU /* Number of successfully transmitted frames after more than a single collision in Half-duplex mode. */
+
+/* Bit definition for Ethernet MMC Transmitted Good Frames Counter Register */
+#define ETH_MMCTGFCR_TGFC 0xFFFFFFFFU /* Number of good frames transmitted. */
+
+/* Bit definition for Ethernet MMC Received Frames with CRC Error Counter Register */
+#define ETH_MMCRFCECR_RFCEC 0xFFFFFFFFU /* Number of frames received with CRC error. */
+
+/* Bit definition for Ethernet MMC Received Frames with Alignement Error Counter Register */
+#define ETH_MMCRFAECR_RFAEC 0xFFFFFFFFU /* Number of frames received with alignment (dribble) error */
+
+/* Bit definition for Ethernet MMC Received Good Unicast Frames Counter Register */
+#define ETH_MMCRGUFCR_RGUFC 0xFFFFFFFFU /* Number of good unicast frames received. */
+
+/******************************************************************************/
+/* Ethernet PTP Registers bits definition */
+/******************************************************************************/
+
+/* Bit definition for Ethernet PTP Time Stamp Contol Register */
+#define ETH_PTPTSCR_TSCNT 0x00030000U /* Time stamp clock node type */
+#define ETH_PTPTSSR_TSSMRME 0x00008000U /* Time stamp snapshot for message relevant to master enable */
+#define ETH_PTPTSSR_TSSEME 0x00004000U /* Time stamp snapshot for event message enable */
+#define ETH_PTPTSSR_TSSIPV4FE 0x00002000U /* Time stamp snapshot for IPv4 frames enable */
+#define ETH_PTPTSSR_TSSIPV6FE 0x00001000U /* Time stamp snapshot for IPv6 frames enable */
+#define ETH_PTPTSSR_TSSPTPOEFE 0x00000800U /* Time stamp snapshot for PTP over ethernet frames enable */
+#define ETH_PTPTSSR_TSPTPPSV2E 0x00000400U /* Time stamp PTP packet snooping for version2 format enable */
+#define ETH_PTPTSSR_TSSSR 0x00000200U /* Time stamp Sub-seconds rollover */
+#define ETH_PTPTSSR_TSSARFE 0x00000100U /* Time stamp snapshot for all received frames enable */
+
+#define ETH_PTPTSCR_TSARU 0x00000020U /* Addend register update */
+#define ETH_PTPTSCR_TSITE 0x00000010U /* Time stamp interrupt trigger enable */
+#define ETH_PTPTSCR_TSSTU 0x00000008U /* Time stamp update */
+#define ETH_PTPTSCR_TSSTI 0x00000004U /* Time stamp initialize */
+#define ETH_PTPTSCR_TSFCU 0x00000002U /* Time stamp fine or coarse update */
+#define ETH_PTPTSCR_TSE 0x00000001U /* Time stamp enable */
+
+/* Bit definition for Ethernet PTP Sub-Second Increment Register */
+#define ETH_PTPSSIR_STSSI 0x000000FFU /* System time Sub-second increment value */
+
+/* Bit definition for Ethernet PTP Time Stamp High Register */
+#define ETH_PTPTSHR_STS 0xFFFFFFFFU /* System Time second */
+
+/* Bit definition for Ethernet PTP Time Stamp Low Register */
+#define ETH_PTPTSLR_STPNS 0x80000000U /* System Time Positive or negative time */
+#define ETH_PTPTSLR_STSS 0x7FFFFFFFU /* System Time sub-seconds */
+
+/* Bit definition for Ethernet PTP Time Stamp High Update Register */
+#define ETH_PTPTSHUR_TSUS 0xFFFFFFFFU /* Time stamp update seconds */
+
+/* Bit definition for Ethernet PTP Time Stamp Low Update Register */
+#define ETH_PTPTSLUR_TSUPNS 0x80000000U /* Time stamp update Positive or negative time */
+#define ETH_PTPTSLUR_TSUSS 0x7FFFFFFFU /* Time stamp update sub-seconds */
+
+/* Bit definition for Ethernet PTP Time Stamp Addend Register */
+#define ETH_PTPTSAR_TSA 0xFFFFFFFFU /* Time stamp addend */
+
+/* Bit definition for Ethernet PTP Target Time High Register */
+#define ETH_PTPTTHR_TTSH 0xFFFFFFFFU /* Target time stamp high */
+
+/* Bit definition for Ethernet PTP Target Time Low Register */
+#define ETH_PTPTTLR_TTSL 0xFFFFFFFFU /* Target time stamp low */
+
+/* Bit definition for Ethernet PTP Time Stamp Status Register */
+#define ETH_PTPTSSR_TSTTR 0x00000020U /* Time stamp target time reached */
+#define ETH_PTPTSSR_TSSO 0x00000010U /* Time stamp seconds overflow */
+
+/******************************************************************************/
+/* Ethernet DMA Registers bits definition */
+/******************************************************************************/
+
+/* Bit definition for Ethernet DMA Bus Mode Register */
+#define ETH_DMABMR_AAB 0x02000000U /* Address-Aligned beats */
+#define ETH_DMABMR_FPM 0x01000000U /* 4xPBL mode */
+#define ETH_DMABMR_USP 0x00800000U /* Use separate PBL */
+#define ETH_DMABMR_RDP 0x007E0000U /* RxDMA PBL */
+ #define ETH_DMABMR_RDP_1Beat 0x00020000U /* maximum number of beats to be transferred in one RxDMA transaction is 1 */
+ #define ETH_DMABMR_RDP_2Beat 0x00040000U /* maximum number of beats to be transferred in one RxDMA transaction is 2 */
+ #define ETH_DMABMR_RDP_4Beat 0x00080000U /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
+ #define ETH_DMABMR_RDP_8Beat 0x00100000U /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
+ #define ETH_DMABMR_RDP_16Beat 0x00200000U /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
+ #define ETH_DMABMR_RDP_32Beat 0x00400000U /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
+ #define ETH_DMABMR_RDP_4xPBL_4Beat 0x01020000U /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
+ #define ETH_DMABMR_RDP_4xPBL_8Beat 0x01040000U /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
+ #define ETH_DMABMR_RDP_4xPBL_16Beat 0x01080000U /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
+ #define ETH_DMABMR_RDP_4xPBL_32Beat 0x01100000U /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
+ #define ETH_DMABMR_RDP_4xPBL_64Beat 0x01200000U /* maximum number of beats to be transferred in one RxDMA transaction is 64 */
+ #define ETH_DMABMR_RDP_4xPBL_128Beat 0x01400000U /* maximum number of beats to be transferred in one RxDMA transaction is 128 */
+#define ETH_DMABMR_FB 0x00010000U /* Fixed Burst */
+#define ETH_DMABMR_RTPR 0x0000C000U /* Rx Tx priority ratio */
+ #define ETH_DMABMR_RTPR_1_1 0x00000000U /* Rx Tx priority ratio */
+ #define ETH_DMABMR_RTPR_2_1 0x00004000U /* Rx Tx priority ratio */
+ #define ETH_DMABMR_RTPR_3_1 0x00008000U /* Rx Tx priority ratio */
+ #define ETH_DMABMR_RTPR_4_1 0x0000C000U /* Rx Tx priority ratio */
+#define ETH_DMABMR_PBL 0x00003F00U /* Programmable burst length */
+ #define ETH_DMABMR_PBL_1Beat 0x00000100U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */
+ #define ETH_DMABMR_PBL_2Beat 0x00000200U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */
+ #define ETH_DMABMR_PBL_4Beat 0x00000400U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
+ #define ETH_DMABMR_PBL_8Beat 0x00000800U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
+ #define ETH_DMABMR_PBL_16Beat 0x00001000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
+ #define ETH_DMABMR_PBL_32Beat 0x00002000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
+ #define ETH_DMABMR_PBL_4xPBL_4Beat 0x01000100U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
+ #define ETH_DMABMR_PBL_4xPBL_8Beat 0x01000200U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
+ #define ETH_DMABMR_PBL_4xPBL_16Beat 0x01000400U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
+ #define ETH_DMABMR_PBL_4xPBL_32Beat 0x01000800U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
+ #define ETH_DMABMR_PBL_4xPBL_64Beat 0x01001000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */
+ #define ETH_DMABMR_PBL_4xPBL_128Beat 0x01002000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */
+#define ETH_DMABMR_EDE 0x00000080U /* Enhanced Descriptor Enable */
+#define ETH_DMABMR_DSL 0x0000007CU /* Descriptor Skip Length */
+#define ETH_DMABMR_DA 0x00000002U /* DMA arbitration scheme */
+#define ETH_DMABMR_SR 0x00000001U /* Software reset */
+
+/* Bit definition for Ethernet DMA Transmit Poll Demand Register */
+#define ETH_DMATPDR_TPD 0xFFFFFFFFU /* Transmit poll demand */
+
+/* Bit definition for Ethernet DMA Receive Poll Demand Register */
+#define ETH_DMARPDR_RPD 0xFFFFFFFFU /* Receive poll demand */
+
+/* Bit definition for Ethernet DMA Receive Descriptor List Address Register */
+#define ETH_DMARDLAR_SRL 0xFFFFFFFFU /* Start of receive list */
+
+/* Bit definition for Ethernet DMA Transmit Descriptor List Address Register */
+#define ETH_DMATDLAR_STL 0xFFFFFFFFU /* Start of transmit list */
+
+/* Bit definition for Ethernet DMA Status Register */
+#define ETH_DMASR_TSTS 0x20000000U /* Time-stamp trigger status */
+#define ETH_DMASR_PMTS 0x10000000U /* PMT status */
+#define ETH_DMASR_MMCS 0x08000000U /* MMC status */
+#define ETH_DMASR_EBS 0x03800000U /* Error bits status */
+ /* combination with EBS[2:0] for GetFlagStatus function */
+ #define ETH_DMASR_EBS_DescAccess 0x02000000U /* Error bits 0-data buffer, 1-desc. access */
+ #define ETH_DMASR_EBS_ReadTransf 0x01000000U /* Error bits 0-write trnsf, 1-read transfr */
+ #define ETH_DMASR_EBS_DataTransfTx 0x00800000U /* Error bits 0-Rx DMA, 1-Tx DMA */
+#define ETH_DMASR_TPS 0x00700000U /* Transmit process state */
+ #define ETH_DMASR_TPS_Stopped 0x00000000U /* Stopped - Reset or Stop Tx Command issued */
+ #define ETH_DMASR_TPS_Fetching 0x00100000U /* Running - fetching the Tx descriptor */
+ #define ETH_DMASR_TPS_Waiting 0x00200000U /* Running - waiting for status */
+ #define ETH_DMASR_TPS_Reading 0x00300000U /* Running - reading the data from host memory */
+ #define ETH_DMASR_TPS_Suspended 0x00600000U /* Suspended - Tx Descriptor unavailabe */
+ #define ETH_DMASR_TPS_Closing 0x00700000U /* Running - closing Rx descriptor */
+#define ETH_DMASR_RPS 0x000E0000U /* Receive process state */
+ #define ETH_DMASR_RPS_Stopped 0x00000000U /* Stopped - Reset or Stop Rx Command issued */
+ #define ETH_DMASR_RPS_Fetching 0x00020000U /* Running - fetching the Rx descriptor */
+ #define ETH_DMASR_RPS_Waiting 0x00060000U /* Running - waiting for packet */
+ #define ETH_DMASR_RPS_Suspended 0x00080000U /* Suspended - Rx Descriptor unavailable */
+ #define ETH_DMASR_RPS_Closing 0x000A0000U /* Running - closing descriptor */
+ #define ETH_DMASR_RPS_Queuing 0x000E0000U /* Running - queuing the recieve frame into host memory */
+#define ETH_DMASR_NIS 0x00010000U /* Normal interrupt summary */
+#define ETH_DMASR_AIS 0x00008000U /* Abnormal interrupt summary */
+#define ETH_DMASR_ERS 0x00004000U /* Early receive status */
+#define ETH_DMASR_FBES 0x00002000U /* Fatal bus error status */
+#define ETH_DMASR_ETS 0x00000400U /* Early transmit status */
+#define ETH_DMASR_RWTS 0x00000200U /* Receive watchdog timeout status */
+#define ETH_DMASR_RPSS 0x00000100U /* Receive process stopped status */
+#define ETH_DMASR_RBUS 0x00000080U /* Receive buffer unavailable status */
+#define ETH_DMASR_RS 0x00000040U /* Receive status */
+#define ETH_DMASR_TUS 0x00000020U /* Transmit underflow status */
+#define ETH_DMASR_ROS 0x00000010U /* Receive overflow status */
+#define ETH_DMASR_TJTS 0x00000008U /* Transmit jabber timeout status */
+#define ETH_DMASR_TBUS 0x00000004U /* Transmit buffer unavailable status */
+#define ETH_DMASR_TPSS 0x00000002U /* Transmit process stopped status */
+#define ETH_DMASR_TS 0x00000001U /* Transmit status */
+
+/* Bit definition for Ethernet DMA Operation Mode Register */
+#define ETH_DMAOMR_DTCEFD 0x04000000U /* Disable Dropping of TCP/IP checksum error frames */
+#define ETH_DMAOMR_RSF 0x02000000U /* Receive store and forward */
+#define ETH_DMAOMR_DFRF 0x01000000U /* Disable flushing of received frames */
+#define ETH_DMAOMR_TSF 0x00200000U /* Transmit store and forward */
+#define ETH_DMAOMR_FTF 0x00100000U /* Flush transmit FIFO */
+#define ETH_DMAOMR_TTC 0x0001C000U /* Transmit threshold control */
+ #define ETH_DMAOMR_TTC_64Bytes 0x00000000U /* threshold level of the MTL Transmit FIFO is 64 Bytes */
+ #define ETH_DMAOMR_TTC_128Bytes 0x00004000U /* threshold level of the MTL Transmit FIFO is 128 Bytes */
+ #define ETH_DMAOMR_TTC_192Bytes 0x00008000U /* threshold level of the MTL Transmit FIFO is 192 Bytes */
+ #define ETH_DMAOMR_TTC_256Bytes 0x0000C000U /* threshold level of the MTL Transmit FIFO is 256 Bytes */
+ #define ETH_DMAOMR_TTC_40Bytes 0x00010000U /* threshold level of the MTL Transmit FIFO is 40 Bytes */
+ #define ETH_DMAOMR_TTC_32Bytes 0x00014000U /* threshold level of the MTL Transmit FIFO is 32 Bytes */
+ #define ETH_DMAOMR_TTC_24Bytes 0x00018000U /* threshold level of the MTL Transmit FIFO is 24 Bytes */
+ #define ETH_DMAOMR_TTC_16Bytes 0x0001C000U /* threshold level of the MTL Transmit FIFO is 16 Bytes */
+#define ETH_DMAOMR_ST 0x00002000U /* Start/stop transmission command */
+#define ETH_DMAOMR_FEF 0x00000080U /* Forward error frames */
+#define ETH_DMAOMR_FUGF 0x00000040U /* Forward undersized good frames */
+#define ETH_DMAOMR_RTC 0x00000018U /* receive threshold control */
+ #define ETH_DMAOMR_RTC_64Bytes 0x00000000U /* threshold level of the MTL Receive FIFO is 64 Bytes */
+ #define ETH_DMAOMR_RTC_32Bytes 0x00000008U /* threshold level of the MTL Receive FIFO is 32 Bytes */
+ #define ETH_DMAOMR_RTC_96Bytes 0x00000010U /* threshold level of the MTL Receive FIFO is 96 Bytes */
+ #define ETH_DMAOMR_RTC_128Bytes 0x00000018U /* threshold level of the MTL Receive FIFO is 128 Bytes */
+#define ETH_DMAOMR_OSF 0x00000004U /* operate on second frame */
+#define ETH_DMAOMR_SR 0x00000002U /* Start/stop receive */
+
+/* Bit definition for Ethernet DMA Interrupt Enable Register */
+#define ETH_DMAIER_NISE 0x00010000U /* Normal interrupt summary enable */
+#define ETH_DMAIER_AISE 0x00008000U /* Abnormal interrupt summary enable */
+#define ETH_DMAIER_ERIE 0x00004000U /* Early receive interrupt enable */
+#define ETH_DMAIER_FBEIE 0x00002000U /* Fatal bus error interrupt enable */
+#define ETH_DMAIER_ETIE 0x00000400U /* Early transmit interrupt enable */
+#define ETH_DMAIER_RWTIE 0x00000200U /* Receive watchdog timeout interrupt enable */
+#define ETH_DMAIER_RPSIE 0x00000100U /* Receive process stopped interrupt enable */
+#define ETH_DMAIER_RBUIE 0x00000080U /* Receive buffer unavailable interrupt enable */
+#define ETH_DMAIER_RIE 0x00000040U /* Receive interrupt enable */
+#define ETH_DMAIER_TUIE 0x00000020U /* Transmit Underflow interrupt enable */
+#define ETH_DMAIER_ROIE 0x00000010U /* Receive Overflow interrupt enable */
+#define ETH_DMAIER_TJTIE 0x00000008U /* Transmit jabber timeout interrupt enable */
+#define ETH_DMAIER_TBUIE 0x00000004U /* Transmit buffer unavailable interrupt enable */
+#define ETH_DMAIER_TPSIE 0x00000002U /* Transmit process stopped interrupt enable */
+#define ETH_DMAIER_TIE 0x00000001U /* Transmit interrupt enable */
+
+/* Bit definition for Ethernet DMA Missed Frame and Buffer Overflow Counter Register */
+#define ETH_DMAMFBOCR_OFOC 0x10000000U /* Overflow bit for FIFO overflow counter */
+#define ETH_DMAMFBOCR_MFA 0x0FFE0000U /* Number of frames missed by the application */
+#define ETH_DMAMFBOCR_OMFC 0x00010000U /* Overflow bit for missed frame counter */
+#define ETH_DMAMFBOCR_MFC 0x0000FFFFU /* Number of frames missed by the controller */
+
+/* Bit definition for Ethernet DMA Current Host Transmit Descriptor Register */
+#define ETH_DMACHTDR_HTDAP 0xFFFFFFFFU /* Host transmit descriptor address pointer */
+
+/* Bit definition for Ethernet DMA Current Host Receive Descriptor Register */
+#define ETH_DMACHRDR_HRDAP 0xFFFFFFFFU /* Host receive descriptor address pointer */
+
+/* Bit definition for Ethernet DMA Current Host Transmit Buffer Address Register */
+#define ETH_DMACHTBAR_HTBAP 0xFFFFFFFFU /* Host transmit buffer address pointer */
+
+/* Bit definition for Ethernet DMA Current Host Receive Buffer Address Register */
+#define ETH_DMACHRBAR_HRBAP 0xFFFFFFFFU /* Host receive buffer address pointer */
+
+/******************************************************************************/
+/* */
+/* USB_OTG */
+/* */
+/******************************************************************************/
+/******************** Bit definition forUSB_OTG_GOTGCTL register ********************/
+#define USB_OTG_GOTGCTL_SRQSCS 0x00000001U /*!< Session request success */
+#define USB_OTG_GOTGCTL_SRQ 0x00000002U /*!< Session request */
+#define USB_OTG_GOTGCTL_HNGSCS 0x00000100U /*!< Host negotiation success */
+#define USB_OTG_GOTGCTL_HNPRQ 0x00000200U /*!< HNP request */
+#define USB_OTG_GOTGCTL_HSHNPEN 0x00000400U /*!< Host set HNP enable */
+#define USB_OTG_GOTGCTL_DHNPEN 0x00000800U /*!< Device HNP enabled */
+#define USB_OTG_GOTGCTL_CIDSTS 0x00010000U /*!< Connector ID status */
+#define USB_OTG_GOTGCTL_DBCT 0x00020000U /*!< Long/short debounce time */
+#define USB_OTG_GOTGCTL_ASVLD 0x00040000U /*!< A-session valid */
+#define USB_OTG_GOTGCTL_BSVLD 0x00080000U /*!< B-session valid */
+
+/******************** Bit definition forUSB_OTG_HCFG register ********************/
+
+#define USB_OTG_HCFG_FSLSPCS 0x00000003U /*!< FS/LS PHY clock select */
+#define USB_OTG_HCFG_FSLSPCS_0 0x00000001U /*!<Bit 0 */
+#define USB_OTG_HCFG_FSLSPCS_1 0x00000002U /*!<Bit 1 */
+#define USB_OTG_HCFG_FSLSS 0x00000004U /*!< FS- and LS-only support */
+
+/******************** Bit definition forUSB_OTG_DCFG register ********************/
+
+#define USB_OTG_DCFG_DSPD 0x00000003U /*!< Device speed */
+#define USB_OTG_DCFG_DSPD_0 0x00000001U /*!<Bit 0 */
+#define USB_OTG_DCFG_DSPD_1 0x00000002U /*!<Bit 1 */
+#define USB_OTG_DCFG_NZLSOHSK 0x00000004U /*!< Nonzero-length status OUT handshake */
+
+#define USB_OTG_DCFG_DAD 0x000007F0U /*!< Device address */
+#define USB_OTG_DCFG_DAD_0 0x00000010U /*!<Bit 0 */
+#define USB_OTG_DCFG_DAD_1 0x00000020U /*!<Bit 1 */
+#define USB_OTG_DCFG_DAD_2 0x00000040U /*!<Bit 2 */
+#define USB_OTG_DCFG_DAD_3 0x00000080U /*!<Bit 3 */
+#define USB_OTG_DCFG_DAD_4 0x00000100U /*!<Bit 4 */
+#define USB_OTG_DCFG_DAD_5 0x00000200U /*!<Bit 5 */
+#define USB_OTG_DCFG_DAD_6 0x00000400U /*!<Bit 6 */
+
+#define USB_OTG_DCFG_PFIVL 0x00001800U /*!< Periodic (micro)frame interval */
+#define USB_OTG_DCFG_PFIVL_0 0x00000800U /*!<Bit 0 */
+#define USB_OTG_DCFG_PFIVL_1 0x00001000U /*!<Bit 1 */
+
+#define USB_OTG_DCFG_PERSCHIVL 0x03000000U /*!< Periodic scheduling interval */
+#define USB_OTG_DCFG_PERSCHIVL_0 0x01000000U /*!<Bit 0 */
+#define USB_OTG_DCFG_PERSCHIVL_1 0x02000000U /*!<Bit 1 */
+
+/******************** Bit definition forUSB_OTG_PCGCR register ********************/
+#define USB_OTG_PCGCR_STPPCLK 0x00000001U /*!< Stop PHY clock */
+#define USB_OTG_PCGCR_GATEHCLK 0x00000002U /*!< Gate HCLK */
+#define USB_OTG_PCGCR_PHYSUSP 0x00000010U /*!< PHY suspended */
+
+/******************** Bit definition forUSB_OTG_GOTGINT register ********************/
+#define USB_OTG_GOTGINT_SEDET 0x00000004U /*!< Session end detected */
+#define USB_OTG_GOTGINT_SRSSCHG 0x00000100U /*!< Session request success status change */
+#define USB_OTG_GOTGINT_HNSSCHG 0x00000200U /*!< Host negotiation success status change */
+#define USB_OTG_GOTGINT_HNGDET 0x00020000U /*!< Host negotiation detected */
+#define USB_OTG_GOTGINT_ADTOCHG 0x00040000U /*!< A-device timeout change */
+#define USB_OTG_GOTGINT_DBCDNE 0x00080000U /*!< Debounce done */
+
+/******************** Bit definition forUSB_OTG_DCTL register ********************/
+#define USB_OTG_DCTL_RWUSIG 0x00000001U /*!< Remote wakeup signaling */
+#define USB_OTG_DCTL_SDIS 0x00000002U /*!< Soft disconnect */
+#define USB_OTG_DCTL_GINSTS 0x00000004U /*!< Global IN NAK status */
+#define USB_OTG_DCTL_GONSTS 0x00000008U /*!< Global OUT NAK status */
+
+#define USB_OTG_DCTL_TCTL 0x00000070U /*!< Test control */
+#define USB_OTG_DCTL_TCTL_0 0x00000010U /*!<Bit 0 */
+#define USB_OTG_DCTL_TCTL_1 0x00000020U /*!<Bit 1 */
+#define USB_OTG_DCTL_TCTL_2 0x00000040U /*!<Bit 2 */
+#define USB_OTG_DCTL_SGINAK 0x00000080U /*!< Set global IN NAK */
+#define USB_OTG_DCTL_CGINAK 0x00000100U /*!< Clear global IN NAK */
+#define USB_OTG_DCTL_SGONAK 0x00000200U /*!< Set global OUT NAK */
+#define USB_OTG_DCTL_CGONAK 0x00000400U /*!< Clear global OUT NAK */
+#define USB_OTG_DCTL_POPRGDNE 0x00000800U /*!< Power-on programming done */
+
+/******************** Bit definition forUSB_OTG_HFIR register ********************/
+#define USB_OTG_HFIR_FRIVL 0x0000FFFFU /*!< Frame interval */
+
+/******************** Bit definition forUSB_OTG_HFNUM register ********************/
+#define USB_OTG_HFNUM_FRNUM 0x0000FFFFU /*!< Frame number */
+#define USB_OTG_HFNUM_FTREM 0xFFFF0000U /*!< Frame time remaining */
+
+/******************** Bit definition forUSB_OTG_DSTS register ********************/
+#define USB_OTG_DSTS_SUSPSTS 0x00000001U /*!< Suspend status */
+
+#define USB_OTG_DSTS_ENUMSPD 0x00000006U /*!< Enumerated speed */
+#define USB_OTG_DSTS_ENUMSPD_0 0x00000002U /*!<Bit 0 */
+#define USB_OTG_DSTS_ENUMSPD_1 0x00000004U /*!<Bit 1 */
+#define USB_OTG_DSTS_EERR 0x00000008U /*!< Erratic error */
+#define USB_OTG_DSTS_FNSOF 0x003FFF00U /*!< Frame number of the received SOF */
+
+/******************** Bit definition forUSB_OTG_GAHBCFG register ********************/
+#define USB_OTG_GAHBCFG_GINT 0x00000001U /*!< Global interrupt mask */
+
+#define USB_OTG_GAHBCFG_HBSTLEN 0x0000001EU /*!< Burst length/type */
+#define USB_OTG_GAHBCFG_HBSTLEN_0 0x00000002U /*!<Bit 0 */
+#define USB_OTG_GAHBCFG_HBSTLEN_1 0x00000004U /*!<Bit 1 */
+#define USB_OTG_GAHBCFG_HBSTLEN_2 0x00000008U /*!<Bit 2 */
+#define USB_OTG_GAHBCFG_HBSTLEN_3 0x00000010U /*!<Bit 3 */
+#define USB_OTG_GAHBCFG_DMAEN 0x00000020U /*!< DMA enable */
+#define USB_OTG_GAHBCFG_TXFELVL 0x00000080U /*!< TxFIFO empty level */
+#define USB_OTG_GAHBCFG_PTXFELVL 0x00000100U /*!< Periodic TxFIFO empty level */
+
+/******************** Bit definition forUSB_OTG_GUSBCFG register ********************/
+
+#define USB_OTG_GUSBCFG_TOCAL 0x00000007U /*!< FS timeout calibration */
+#define USB_OTG_GUSBCFG_TOCAL_0 0x00000001U /*!<Bit 0 */
+#define USB_OTG_GUSBCFG_TOCAL_1 0x00000002U /*!<Bit 1 */
+#define USB_OTG_GUSBCFG_TOCAL_2 0x00000004U /*!<Bit 2 */
+#define USB_OTG_GUSBCFG_PHYSEL 0x00000040U /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */
+#define USB_OTG_GUSBCFG_SRPCAP 0x00000100U /*!< SRP-capable */
+#define USB_OTG_GUSBCFG_HNPCAP 0x00000200U /*!< HNP-capable */
+
+#define USB_OTG_GUSBCFG_TRDT 0x00003C00U /*!< USB turnaround time */
+#define USB_OTG_GUSBCFG_TRDT_0 0x00000400U /*!<Bit 0 */
+#define USB_OTG_GUSBCFG_TRDT_1 0x00000800U /*!<Bit 1 */
+#define USB_OTG_GUSBCFG_TRDT_2 0x00001000U /*!<Bit 2 */
+#define USB_OTG_GUSBCFG_TRDT_3 0x00002000U /*!<Bit 3 */
+#define USB_OTG_GUSBCFG_PHYLPCS 0x00008000U /*!< PHY Low-power clock select */
+#define USB_OTG_GUSBCFG_ULPIFSLS 0x00020000U /*!< ULPI FS/LS select */
+#define USB_OTG_GUSBCFG_ULPIAR 0x00040000U /*!< ULPI Auto-resume */
+#define USB_OTG_GUSBCFG_ULPICSM 0x00080000U /*!< ULPI Clock SuspendM */
+#define USB_OTG_GUSBCFG_ULPIEVBUSD 0x00100000U /*!< ULPI External VBUS Drive */
+#define USB_OTG_GUSBCFG_ULPIEVBUSI 0x00200000U /*!< ULPI external VBUS indicator */
+#define USB_OTG_GUSBCFG_TSDPS 0x00400000U /*!< TermSel DLine pulsing selection */
+#define USB_OTG_GUSBCFG_PCCI 0x00800000U /*!< Indicator complement */
+#define USB_OTG_GUSBCFG_PTCI 0x01000000U /*!< Indicator pass through */
+#define USB_OTG_GUSBCFG_ULPIIPD 0x02000000U /*!< ULPI interface protect disable */
+#define USB_OTG_GUSBCFG_FHMOD 0x20000000U /*!< Forced host mode */
+#define USB_OTG_GUSBCFG_FDMOD 0x40000000U /*!< Forced peripheral mode */
+#define USB_OTG_GUSBCFG_CTXPKT 0x80000000U /*!< Corrupt Tx packet */
+
+/******************** Bit definition forUSB_OTG_GRSTCTL register ********************/
+#define USB_OTG_GRSTCTL_CSRST 0x00000001U /*!< Core soft reset */
+#define USB_OTG_GRSTCTL_HSRST 0x00000002U /*!< HCLK soft reset */
+#define USB_OTG_GRSTCTL_FCRST 0x00000004U /*!< Host frame counter reset */
+#define USB_OTG_GRSTCTL_RXFFLSH 0x00000010U /*!< RxFIFO flush */
+#define USB_OTG_GRSTCTL_TXFFLSH 0x00000020U /*!< TxFIFO flush */
+
+#define USB_OTG_GRSTCTL_TXFNUM 0x000007C0U /*!< TxFIFO number */
+#define USB_OTG_GRSTCTL_TXFNUM_0 0x00000040U /*!<Bit 0 */
+#define USB_OTG_GRSTCTL_TXFNUM_1 0x00000080U /*!<Bit 1 */
+#define USB_OTG_GRSTCTL_TXFNUM_2 0x00000100U /*!<Bit 2 */
+#define USB_OTG_GRSTCTL_TXFNUM_3 0x00000200U /*!<Bit 3 */
+#define USB_OTG_GRSTCTL_TXFNUM_4 0x00000400U /*!<Bit 4 */
+#define USB_OTG_GRSTCTL_DMAREQ 0x40000000U /*!< DMA request signal */
+#define USB_OTG_GRSTCTL_AHBIDL 0x80000000U /*!< AHB master idle */
+
+/******************** Bit definition forUSB_OTG_DIEPMSK register ********************/
+#define USB_OTG_DIEPMSK_XFRCM 0x00000001U /*!< Transfer completed interrupt mask */
+#define USB_OTG_DIEPMSK_EPDM 0x00000002U /*!< Endpoint disabled interrupt mask */
+#define USB_OTG_DIEPMSK_TOM 0x00000008U /*!< Timeout condition mask (nonisochronous endpoints) */
+#define USB_OTG_DIEPMSK_ITTXFEMSK 0x00000010U /*!< IN token received when TxFIFO empty mask */
+#define USB_OTG_DIEPMSK_INEPNMM 0x00000020U /*!< IN token received with EP mismatch mask */
+#define USB_OTG_DIEPMSK_INEPNEM 0x00000040U /*!< IN endpoint NAK effective mask */
+#define USB_OTG_DIEPMSK_TXFURM 0x00000100U /*!< FIFO underrun mask */
+#define USB_OTG_DIEPMSK_BIM 0x00000200U /*!< BNA interrupt mask */
+
+/******************** Bit definition forUSB_OTG_HPTXSTS register ********************/
+#define USB_OTG_HPTXSTS_PTXFSAVL 0x0000FFFFU /*!< Periodic transmit data FIFO space available */
+
+#define USB_OTG_HPTXSTS_PTXQSAV 0x00FF0000U /*!< Periodic transmit request queue space available */
+#define USB_OTG_HPTXSTS_PTXQSAV_0 0x00010000U /*!<Bit 0 */
+#define USB_OTG_HPTXSTS_PTXQSAV_1 0x00020000U /*!<Bit 1 */
+#define USB_OTG_HPTXSTS_PTXQSAV_2 0x00040000U /*!<Bit 2 */
+#define USB_OTG_HPTXSTS_PTXQSAV_3 0x00080000U /*!<Bit 3 */
+#define USB_OTG_HPTXSTS_PTXQSAV_4 0x00100000U /*!<Bit 4 */
+#define USB_OTG_HPTXSTS_PTXQSAV_5 0x00200000U /*!<Bit 5 */
+#define USB_OTG_HPTXSTS_PTXQSAV_6 0x00400000U /*!<Bit 6 */
+#define USB_OTG_HPTXSTS_PTXQSAV_7 0x00800000U /*!<Bit 7 */
+
+#define USB_OTG_HPTXSTS_PTXQTOP 0xFF000000U /*!< Top of the periodic transmit request queue */
+#define USB_OTG_HPTXSTS_PTXQTOP_0 0x01000000U /*!<Bit 0 */
+#define USB_OTG_HPTXSTS_PTXQTOP_1 0x02000000U /*!<Bit 1 */
+#define USB_OTG_HPTXSTS_PTXQTOP_2 0x04000000U /*!<Bit 2 */
+#define USB_OTG_HPTXSTS_PTXQTOP_3 0x08000000U /*!<Bit 3 */
+#define USB_OTG_HPTXSTS_PTXQTOP_4 0x10000000U /*!<Bit 4 */
+#define USB_OTG_HPTXSTS_PTXQTOP_5 0x20000000U /*!<Bit 5 */
+#define USB_OTG_HPTXSTS_PTXQTOP_6 0x40000000U /*!<Bit 6 */
+#define USB_OTG_HPTXSTS_PTXQTOP_7 0x80000000U /*!<Bit 7 */
+
+/******************** Bit definition forUSB_OTG_HAINT register ********************/
+#define USB_OTG_HAINT_HAINT 0x0000FFFFU /*!< Channel interrupts */
+
+/******************** Bit definition forUSB_OTG_DOEPMSK register ********************/
+#define USB_OTG_DOEPMSK_XFRCM 0x00000001U /*!< Transfer completed interrupt mask */
+#define USB_OTG_DOEPMSK_EPDM 0x00000002U /*!< Endpoint disabled interrupt mask */
+#define USB_OTG_DOEPMSK_STUPM 0x00000008U /*!< SETUP phase done mask */
+#define USB_OTG_DOEPMSK_OTEPDM 0x00000010U /*!< OUT token received when endpoint disabled mask */
+#define USB_OTG_DOEPMSK_B2BSTUP 0x00000040U /*!< Back-to-back SETUP packets received mask */
+#define USB_OTG_DOEPMSK_OPEM 0x00000100U /*!< OUT packet error mask */
+#define USB_OTG_DOEPMSK_BOIM 0x00000200U /*!< BNA interrupt mask */
+
+/******************** Bit definition forUSB_OTG_GINTSTS register ********************/
+#define USB_OTG_GINTSTS_CMOD 0x00000001U /*!< Current mode of operation */
+#define USB_OTG_GINTSTS_MMIS 0x00000002U /*!< Mode mismatch interrupt */
+#define USB_OTG_GINTSTS_OTGINT 0x00000004U /*!< OTG interrupt */
+#define USB_OTG_GINTSTS_SOF 0x00000008U /*!< Start of frame */
+#define USB_OTG_GINTSTS_RXFLVL 0x00000010U /*!< RxFIFO nonempty */
+#define USB_OTG_GINTSTS_NPTXFE 0x00000020U /*!< Nonperiodic TxFIFO empty */
+#define USB_OTG_GINTSTS_GINAKEFF 0x00000040U /*!< Global IN nonperiodic NAK effective */
+#define USB_OTG_GINTSTS_BOUTNAKEFF 0x00000080U /*!< Global OUT NAK effective */
+#define USB_OTG_GINTSTS_ESUSP 0x00000400U /*!< Early suspend */
+#define USB_OTG_GINTSTS_USBSUSP 0x00000800U /*!< USB suspend */
+#define USB_OTG_GINTSTS_USBRST 0x00001000U /*!< USB reset */
+#define USB_OTG_GINTSTS_ENUMDNE 0x00002000U /*!< Enumeration done */
+#define USB_OTG_GINTSTS_ISOODRP 0x00004000U /*!< Isochronous OUT packet dropped interrupt */
+#define USB_OTG_GINTSTS_EOPF 0x00008000U /*!< End of periodic frame interrupt */
+#define USB_OTG_GINTSTS_IEPINT 0x00040000U /*!< IN endpoint interrupt */
+#define USB_OTG_GINTSTS_OEPINT 0x00080000U /*!< OUT endpoint interrupt */
+#define USB_OTG_GINTSTS_IISOIXFR 0x00100000U /*!< Incomplete isochronous IN transfer */
+#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT 0x00200000U /*!< Incomplete periodic transfer */
+#define USB_OTG_GINTSTS_DATAFSUSP 0x00400000U /*!< Data fetch suspended */
+#define USB_OTG_GINTSTS_HPRTINT 0x01000000U /*!< Host port interrupt */
+#define USB_OTG_GINTSTS_HCINT 0x02000000U /*!< Host channels interrupt */
+#define USB_OTG_GINTSTS_PTXFE 0x04000000U /*!< Periodic TxFIFO empty */
+#define USB_OTG_GINTSTS_CIDSCHG 0x10000000U /*!< Connector ID status change */
+#define USB_OTG_GINTSTS_DISCINT 0x20000000U /*!< Disconnect detected interrupt */
+#define USB_OTG_GINTSTS_SRQINT 0x40000000U /*!< Session request/new session detected interrupt */
+#define USB_OTG_GINTSTS_WKUINT 0x80000000U /*!< Resume/remote wakeup detected interrupt */
+
+/******************** Bit definition forUSB_OTG_GINTMSK register ********************/
+#define USB_OTG_GINTMSK_MMISM 0x00000002U /*!< Mode mismatch interrupt mask */
+#define USB_OTG_GINTMSK_OTGINT 0x00000004U /*!< OTG interrupt mask */
+#define USB_OTG_GINTMSK_SOFM 0x00000008U /*!< Start of frame mask */
+#define USB_OTG_GINTMSK_RXFLVLM 0x00000010U /*!< Receive FIFO nonempty mask */
+#define USB_OTG_GINTMSK_NPTXFEM 0x00000020U /*!< Nonperiodic TxFIFO empty mask */
+#define USB_OTG_GINTMSK_GINAKEFFM 0x00000040U /*!< Global nonperiodic IN NAK effective mask */
+#define USB_OTG_GINTMSK_GONAKEFFM 0x00000080U /*!< Global OUT NAK effective mask */
+#define USB_OTG_GINTMSK_ESUSPM 0x00000400U /*!< Early suspend mask */
+#define USB_OTG_GINTMSK_USBSUSPM 0x00000800U /*!< USB suspend mask */
+#define USB_OTG_GINTMSK_USBRST 0x00001000U /*!< USB reset mask */
+#define USB_OTG_GINTMSK_ENUMDNEM 0x00002000U /*!< Enumeration done mask */
+#define USB_OTG_GINTMSK_ISOODRPM 0x00004000U /*!< Isochronous OUT packet dropped interrupt mask */
+#define USB_OTG_GINTMSK_EOPFM 0x00008000U /*!< End of periodic frame interrupt mask */
+#define USB_OTG_GINTMSK_EPMISM 0x00020000U /*!< Endpoint mismatch interrupt mask */
+#define USB_OTG_GINTMSK_IEPINT 0x00040000U /*!< IN endpoints interrupt mask */
+#define USB_OTG_GINTMSK_OEPINT 0x00080000U /*!< OUT endpoints interrupt mask */
+#define USB_OTG_GINTMSK_IISOIXFRM 0x00100000U /*!< Incomplete isochronous IN transfer mask */
+#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM 0x00200000U /*!< Incomplete periodic transfer mask */
+#define USB_OTG_GINTMSK_FSUSPM 0x00400000U /*!< Data fetch suspended mask */
+#define USB_OTG_GINTMSK_PRTIM 0x01000000U /*!< Host port interrupt mask */
+#define USB_OTG_GINTMSK_HCIM 0x02000000U /*!< Host channels interrupt mask */
+#define USB_OTG_GINTMSK_PTXFEM 0x04000000U /*!< Periodic TxFIFO empty mask */
+#define USB_OTG_GINTMSK_CIDSCHGM 0x10000000U /*!< Connector ID status change mask */
+#define USB_OTG_GINTMSK_DISCINT 0x20000000U /*!< Disconnect detected interrupt mask */
+#define USB_OTG_GINTMSK_SRQIM 0x40000000U /*!< Session request/new session detected interrupt mask */
+#define USB_OTG_GINTMSK_WUIM 0x80000000U /*!< Resume/remote wakeup detected interrupt mask */
+
+/******************** Bit definition forUSB_OTG_DAINT register ********************/
+#define USB_OTG_DAINT_IEPINT 0x0000FFFFU /*!< IN endpoint interrupt bits */
+#define USB_OTG_DAINT_OEPINT 0xFFFF0000U /*!< OUT endpoint interrupt bits */
+
+/******************** Bit definition forUSB_OTG_HAINTMSK register ********************/
+#define USB_OTG_HAINTMSK_HAINTM 0x0000FFFFU /*!< Channel interrupt mask */
+
+/******************** Bit definition for USB_OTG_GRXSTSP register ********************/
+#define USB_OTG_GRXSTSP_EPNUM 0x0000000FU /*!< IN EP interrupt mask bits */
+#define USB_OTG_GRXSTSP_BCNT 0x00007FF0U /*!< OUT EP interrupt mask bits */
+#define USB_OTG_GRXSTSP_DPID 0x00018000U /*!< OUT EP interrupt mask bits */
+#define USB_OTG_GRXSTSP_PKTSTS 0x001E0000U /*!< OUT EP interrupt mask bits */
+
+/******************** Bit definition forUSB_OTG_DAINTMSK register ********************/
+#define USB_OTG_DAINTMSK_IEPM 0x0000FFFFU /*!< IN EP interrupt mask bits */
+#define USB_OTG_DAINTMSK_OEPM 0xFFFF0000U /*!< OUT EP interrupt mask bits */
+
+/******************** Bit definition for OTG register ********************/
+
+#define USB_OTG_CHNUM 0x0000000FU /*!< Channel number */
+#define USB_OTG_CHNUM_0 0x00000001U /*!<Bit 0 */
+#define USB_OTG_CHNUM_1 0x00000002U /*!<Bit 1 */
+#define USB_OTG_CHNUM_2 0x00000004U /*!<Bit 2 */
+#define USB_OTG_CHNUM_3 0x00000008U /*!<Bit 3 */
+#define USB_OTG_BCNT 0x00007FF0U /*!< Byte count */
+
+#define USB_OTG_DPID 0x00018000U /*!< Data PID */
+#define USB_OTG_DPID_0 0x00008000U /*!<Bit 0 */
+#define USB_OTG_DPID_1 0x00010000U /*!<Bit 1 */
+
+#define USB_OTG_PKTSTS 0x001E0000U /*!< Packet status */
+#define USB_OTG_PKTSTS_0 0x00020000U /*!<Bit 0 */
+#define USB_OTG_PKTSTS_1 0x00040000U /*!<Bit 1 */
+#define USB_OTG_PKTSTS_2 0x00080000U /*!<Bit 2 */
+#define USB_OTG_PKTSTS_3 0x00100000U /*!<Bit 3 */
+
+#define USB_OTG_EPNUM 0x0000000FU /*!< Endpoint number */
+#define USB_OTG_EPNUM_0 0x00000001U /*!<Bit 0 */
+#define USB_OTG_EPNUM_1 0x00000002U /*!<Bit 1 */
+#define USB_OTG_EPNUM_2 0x00000004U /*!<Bit 2 */
+#define USB_OTG_EPNUM_3 0x00000008U /*!<Bit 3 */
+
+#define USB_OTG_FRMNUM 0x01E00000U /*!< Frame number */
+#define USB_OTG_FRMNUM_0 0x00200000U /*!<Bit 0 */
+#define USB_OTG_FRMNUM_1 0x00400000U /*!<Bit 1 */
+#define USB_OTG_FRMNUM_2 0x00800000U /*!<Bit 2 */
+#define USB_OTG_FRMNUM_3 0x01000000U /*!<Bit 3 */
+
+/******************** Bit definition for OTG register ********************/
+
+#define USB_OTG_CHNUM 0x0000000FU /*!< Channel number */
+#define USB_OTG_CHNUM_0 0x00000001U /*!<Bit 0 */
+#define USB_OTG_CHNUM_1 0x00000002U /*!<Bit 1 */
+#define USB_OTG_CHNUM_2 0x00000004U /*!<Bit 2 */
+#define USB_OTG_CHNUM_3 0x00000008U /*!<Bit 3 */
+#define USB_OTG_BCNT 0x00007FF0U /*!< Byte count */
+
+#define USB_OTG_DPID 0x00018000U /*!< Data PID */
+#define USB_OTG_DPID_0 0x00008000U /*!<Bit 0 */
+#define USB_OTG_DPID_1 0x00010000U /*!<Bit 1 */
+
+#define USB_OTG_PKTSTS 0x001E0000U /*!< Packet status */
+#define USB_OTG_PKTSTS_0 0x00020000U /*!<Bit 0 */
+#define USB_OTG_PKTSTS_1 0x00040000U /*!<Bit 1 */
+#define USB_OTG_PKTSTS_2 0x00080000U /*!<Bit 2 */
+#define USB_OTG_PKTSTS_3 0x00100000U /*!<Bit 3 */
+
+#define USB_OTG_EPNUM 0x0000000FU /*!< Endpoint number */
+#define USB_OTG_EPNUM_0 0x00000001U /*!<Bit 0 */
+#define USB_OTG_EPNUM_1 0x00000002U /*!<Bit 1 */
+#define USB_OTG_EPNUM_2 0x00000004U /*!<Bit 2 */
+#define USB_OTG_EPNUM_3 0x00000008U /*!<Bit 3 */
+
+#define USB_OTG_FRMNUM 0x01E00000U /*!< Frame number */
+#define USB_OTG_FRMNUM_0 0x00200000U /*!<Bit 0 */
+#define USB_OTG_FRMNUM_1 0x00400000U /*!<Bit 1 */
+#define USB_OTG_FRMNUM_2 0x00800000U /*!<Bit 2 */
+#define USB_OTG_FRMNUM_3 0x01000000U /*!<Bit 3 */
+
+/******************** Bit definition forUSB_OTG_GRXFSIZ register ********************/
+#define USB_OTG_GRXFSIZ_RXFD 0x0000FFFFU /*!< RxFIFO depth */
+
+/******************** Bit definition forUSB_OTG_DVBUSDIS register ********************/
+#define USB_OTG_DVBUSDIS_VBUSDT 0x0000FFFFU /*!< Device VBUS discharge time */
+
+/******************** Bit definition for OTG register ********************/
+#define USB_OTG_NPTXFSA 0x0000FFFFU /*!< Nonperiodic transmit RAM start address */
+#define USB_OTG_NPTXFD 0xFFFF0000U /*!< Nonperiodic TxFIFO depth */
+#define USB_OTG_TX0FSA 0x0000FFFFU /*!< Endpoint 0 transmit RAM start address */
+#define USB_OTG_TX0FD 0xFFFF0000U /*!< Endpoint 0 TxFIFO depth */
+
+/******************** Bit definition forUSB_OTG_DVBUSPULSE register ********************/
+#define USB_OTG_DVBUSPULSE_DVBUSP 0x00000FFFU /*!< Device VBUS pulsing time */
+
+/******************** Bit definition forUSB_OTG_GNPTXSTS register ********************/
+#define USB_OTG_GNPTXSTS_NPTXFSAV 0x0000FFFFU /*!< Nonperiodic TxFIFO space available */
+
+#define USB_OTG_GNPTXSTS_NPTQXSAV 0x00FF0000U /*!< Nonperiodic transmit request queue space available */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_0 0x00010000U /*!<Bit 0 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_1 0x00020000U /*!<Bit 1 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_2 0x00040000U /*!<Bit 2 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_3 0x00080000U /*!<Bit 3 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_4 0x00100000U /*!<Bit 4 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_5 0x00200000U /*!<Bit 5 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_6 0x00400000U /*!<Bit 6 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_7 0x00800000U /*!<Bit 7 */
+
+#define USB_OTG_GNPTXSTS_NPTXQTOP 0x7F000000U /*!< Top of the nonperiodic transmit request queue */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_0 0x01000000U /*!<Bit 0 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_1 0x02000000U /*!<Bit 1 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_2 0x04000000U /*!<Bit 2 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_3 0x08000000U /*!<Bit 3 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_4 0x10000000U /*!<Bit 4 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_5 0x20000000U /*!<Bit 5 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_6 0x40000000U /*!<Bit 6 */
+
+/******************** Bit definition forUSB_OTG_DTHRCTL register ********************/
+#define USB_OTG_DTHRCTL_NONISOTHREN 0x00000001U /*!< Nonisochronous IN endpoints threshold enable */
+#define USB_OTG_DTHRCTL_ISOTHREN 0x00000002U /*!< ISO IN endpoint threshold enable */
+
+#define USB_OTG_DTHRCTL_TXTHRLEN 0x000007FCU /*!< Transmit threshold length */
+#define USB_OTG_DTHRCTL_TXTHRLEN_0 0x00000004U /*!<Bit 0 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_1 0x00000008U /*!<Bit 1 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_2 0x00000010U /*!<Bit 2 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_3 0x00000020U /*!<Bit 3 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_4 0x00000040U /*!<Bit 4 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_5 0x00000080U /*!<Bit 5 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_6 0x00000100U /*!<Bit 6 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_7 0x00000200U /*!<Bit 7 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_8 0x00000400U /*!<Bit 8 */
+#define USB_OTG_DTHRCTL_RXTHREN 0x00010000U /*!< Receive threshold enable */
+
+#define USB_OTG_DTHRCTL_RXTHRLEN 0x03FE0000U /*!< Receive threshold length */
+#define USB_OTG_DTHRCTL_RXTHRLEN_0 0x00020000U /*!<Bit 0 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_1 0x00040000U /*!<Bit 1 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_2 0x00080000U /*!<Bit 2 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_3 0x00100000U /*!<Bit 3 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_4 0x00200000U /*!<Bit 4 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_5 0x00400000U /*!<Bit 5 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_6 0x00800000U /*!<Bit 6 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_7 0x01000000U /*!<Bit 7 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_8 0x02000000U /*!<Bit 8 */
+#define USB_OTG_DTHRCTL_ARPEN 0x08000000U /*!< Arbiter parking enable */
+
+/******************** Bit definition forUSB_OTG_DIEPEMPMSK register ********************/
+#define USB_OTG_DIEPEMPMSK_INEPTXFEM 0x0000FFFFU /*!< IN EP Tx FIFO empty interrupt mask bits */
+
+/******************** Bit definition forUSB_OTG_DEACHINT register ********************/
+#define USB_OTG_DEACHINT_IEP1INT 0x00000002U /*!< IN endpoint 1interrupt bit */
+#define USB_OTG_DEACHINT_OEP1INT 0x00020000U /*!< OUT endpoint 1 interrupt bit */
+
+/******************** Bit definition forUSB_OTG_GCCFG register ********************/
+#define USB_OTG_GCCFG_PWRDWN 0x00010000U /*!< Power down */
+#define USB_OTG_GCCFG_I2CPADEN 0x00020000U /*!< Enable I2C bus connection for the external I2C PHY interface */
+#define USB_OTG_GCCFG_VBUSASEN 0x00040000U /*!< Enable the VBUS sensing device */
+#define USB_OTG_GCCFG_VBUSBSEN 0x00080000U /*!< Enable the VBUS sensing device */
+#define USB_OTG_GCCFG_SOFOUTEN 0x00100000U /*!< SOF output enable */
+#define USB_OTG_GCCFG_NOVBUSSENS 0x00200000U /*!< VBUS sensing disable option */
+
+/******************** Bit definition forUSB_OTG_DEACHINTMSK register ********************/
+#define USB_OTG_DEACHINTMSK_IEP1INTM 0x00000002U /*!< IN Endpoint 1 interrupt mask bit */
+#define USB_OTG_DEACHINTMSK_OEP1INTM 0x00020000U /*!< OUT Endpoint 1 interrupt mask bit */
+
+/******************** Bit definition forUSB_OTG_CID register ********************/
+#define USB_OTG_CID_PRODUCT_ID 0xFFFFFFFFU /*!< Product ID field */
+
+/******************** Bit definition forUSB_OTG_DIEPEACHMSK1 register ********************/
+#define USB_OTG_DIEPEACHMSK1_XFRCM 0x00000001U /*!< Transfer completed interrupt mask */
+#define USB_OTG_DIEPEACHMSK1_EPDM 0x00000002U /*!< Endpoint disabled interrupt mask */
+#define USB_OTG_DIEPEACHMSK1_TOM 0x00000008U /*!< Timeout condition mask (nonisochronous endpoints) */
+#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK 0x00000010U /*!< IN token received when TxFIFO empty mask */
+#define USB_OTG_DIEPEACHMSK1_INEPNMM 0x00000020U /*!< IN token received with EP mismatch mask */
+#define USB_OTG_DIEPEACHMSK1_INEPNEM 0x00000040U /*!< IN endpoint NAK effective mask */
+#define USB_OTG_DIEPEACHMSK1_TXFURM 0x00000100U /*!< FIFO underrun mask */
+#define USB_OTG_DIEPEACHMSK1_BIM 0x00000200U /*!< BNA interrupt mask */
+#define USB_OTG_DIEPEACHMSK1_NAKM 0x00002000U /*!< NAK interrupt mask */
+
+/******************** Bit definition forUSB_OTG_HPRT register ********************/
+#define USB_OTG_HPRT_PCSTS 0x00000001U /*!< Port connect status */
+#define USB_OTG_HPRT_PCDET 0x00000002U /*!< Port connect detected */
+#define USB_OTG_HPRT_PENA 0x00000004U /*!< Port enable */
+#define USB_OTG_HPRT_PENCHNG 0x00000008U /*!< Port enable/disable change */
+#define USB_OTG_HPRT_POCA 0x00000010U /*!< Port overcurrent active */
+#define USB_OTG_HPRT_POCCHNG 0x00000020U /*!< Port overcurrent change */
+#define USB_OTG_HPRT_PRES 0x00000040U /*!< Port resume */
+#define USB_OTG_HPRT_PSUSP 0x00000080U /*!< Port suspend */
+#define USB_OTG_HPRT_PRST 0x00000100U /*!< Port reset */
+
+#define USB_OTG_HPRT_PLSTS 0x00000C00U /*!< Port line status */
+#define USB_OTG_HPRT_PLSTS_0 0x00000400U /*!<Bit 0 */
+#define USB_OTG_HPRT_PLSTS_1 0x00000800U /*!<Bit 1 */
+#define USB_OTG_HPRT_PPWR 0x00001000U /*!< Port power */
+
+#define USB_OTG_HPRT_PTCTL 0x0001E000U /*!< Port test control */
+#define USB_OTG_HPRT_PTCTL_0 0x00002000U /*!<Bit 0 */
+#define USB_OTG_HPRT_PTCTL_1 0x00004000U /*!<Bit 1 */
+#define USB_OTG_HPRT_PTCTL_2 0x00008000U /*!<Bit 2 */
+#define USB_OTG_HPRT_PTCTL_3 0x00010000U /*!<Bit 3 */
+
+#define USB_OTG_HPRT_PSPD 0x00060000U /*!< Port speed */
+#define USB_OTG_HPRT_PSPD_0 0x00020000U /*!<Bit 0 */
+#define USB_OTG_HPRT_PSPD_1 0x00040000U /*!<Bit 1 */
+
+/******************** Bit definition forUSB_OTG_DOEPEACHMSK1 register ********************/
+#define USB_OTG_DOEPEACHMSK1_XFRCM 0x00000001U /*!< Transfer completed interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_EPDM 0x00000002U /*!< Endpoint disabled interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_TOM 0x00000008U /*!< Timeout condition mask */
+#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK 0x00000010U /*!< IN token received when TxFIFO empty mask */
+#define USB_OTG_DOEPEACHMSK1_INEPNMM 0x00000020U /*!< IN token received with EP mismatch mask */
+#define USB_OTG_DOEPEACHMSK1_INEPNEM 0x00000040U /*!< IN endpoint NAK effective mask */
+#define USB_OTG_DOEPEACHMSK1_TXFURM 0x00000100U /*!< OUT packet error mask */
+#define USB_OTG_DOEPEACHMSK1_BIM 0x00000200U /*!< BNA interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_BERRM 0x00001000U /*!< Bubble error interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_NAKM 0x00002000U /*!< NAK interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_NYETM 0x00004000U /*!< NYET interrupt mask */
+
+/******************** Bit definition forUSB_OTG_HPTXFSIZ register ********************/
+#define USB_OTG_HPTXFSIZ_PTXSA 0x0000FFFFU /*!< Host periodic TxFIFO start address */
+#define USB_OTG_HPTXFSIZ_PTXFD 0xFFFF0000U /*!< Host periodic TxFIFO depth */
+
+/******************** Bit definition forUSB_OTG_DIEPCTL register ********************/
+#define USB_OTG_DIEPCTL_MPSIZ 0x000007FFU /*!< Maximum packet size */
+#define USB_OTG_DIEPCTL_USBAEP 0x00008000U /*!< USB active endpoint */
+#define USB_OTG_DIEPCTL_EONUM_DPID 0x00010000U /*!< Even/odd frame */
+#define USB_OTG_DIEPCTL_NAKSTS 0x00020000U /*!< NAK status */
+
+#define USB_OTG_DIEPCTL_EPTYP 0x000C0000U /*!< Endpoint type */
+#define USB_OTG_DIEPCTL_EPTYP_0 0x00040000U /*!<Bit 0 */
+#define USB_OTG_DIEPCTL_EPTYP_1 0x00080000U /*!<Bit 1 */
+#define USB_OTG_DIEPCTL_STALL 0x00200000U /*!< STALL handshake */
+
+#define USB_OTG_DIEPCTL_TXFNUM 0x03C00000U /*!< TxFIFO number */
+#define USB_OTG_DIEPCTL_TXFNUM_0 0x00400000U /*!<Bit 0 */
+#define USB_OTG_DIEPCTL_TXFNUM_1 0x00800000U /*!<Bit 1 */
+#define USB_OTG_DIEPCTL_TXFNUM_2 0x01000000U /*!<Bit 2 */
+#define USB_OTG_DIEPCTL_TXFNUM_3 0x02000000U /*!<Bit 3 */
+#define USB_OTG_DIEPCTL_CNAK 0x04000000U /*!< Clear NAK */
+#define USB_OTG_DIEPCTL_SNAK 0x08000000U /*!< Set NAK */
+#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM 0x10000000U /*!< Set DATA0 PID */
+#define USB_OTG_DIEPCTL_SODDFRM 0x20000000U /*!< Set odd frame */
+#define USB_OTG_DIEPCTL_EPDIS 0x40000000U /*!< Endpoint disable */
+#define USB_OTG_DIEPCTL_EPENA 0x80000000U /*!< Endpoint enable */
+
+/******************** Bit definition forUSB_OTG_HCCHAR register ********************/
+#define USB_OTG_HCCHAR_MPSIZ 0x000007FFU /*!< Maximum packet size */
+
+#define USB_OTG_HCCHAR_EPNUM 0x00007800U /*!< Endpoint number */
+#define USB_OTG_HCCHAR_EPNUM_0 0x00000800U /*!<Bit 0 */
+#define USB_OTG_HCCHAR_EPNUM_1 0x00001000U /*!<Bit 1 */
+#define USB_OTG_HCCHAR_EPNUM_2 0x00002000U /*!<Bit 2 */
+#define USB_OTG_HCCHAR_EPNUM_3 0x00004000U /*!<Bit 3 */
+#define USB_OTG_HCCHAR_EPDIR 0x00008000U /*!< Endpoint direction */
+#define USB_OTG_HCCHAR_LSDEV 0x00020000U /*!< Low-speed device */
+
+#define USB_OTG_HCCHAR_EPTYP 0x000C0000U /*!< Endpoint type */
+#define USB_OTG_HCCHAR_EPTYP_0 0x00040000U /*!<Bit 0 */
+#define USB_OTG_HCCHAR_EPTYP_1 0x00080000U /*!<Bit 1 */
+
+#define USB_OTG_HCCHAR_MC 0x00300000U /*!< Multi Count (MC) / Error Count (EC) */
+#define USB_OTG_HCCHAR_MC_0 0x00100000U /*!<Bit 0 */
+#define USB_OTG_HCCHAR_MC_1 0x00200000U /*!<Bit 1 */
+
+#define USB_OTG_HCCHAR_DAD 0x1FC00000U /*!< Device address */
+#define USB_OTG_HCCHAR_DAD_0 0x00400000U /*!<Bit 0 */
+#define USB_OTG_HCCHAR_DAD_1 0x00800000U /*!<Bit 1 */
+#define USB_OTG_HCCHAR_DAD_2 0x01000000U /*!<Bit 2 */
+#define USB_OTG_HCCHAR_DAD_3 0x02000000U /*!<Bit 3 */
+#define USB_OTG_HCCHAR_DAD_4 0x04000000U /*!<Bit 4 */
+#define USB_OTG_HCCHAR_DAD_5 0x08000000U /*!<Bit 5 */
+#define USB_OTG_HCCHAR_DAD_6 0x10000000U /*!<Bit 6 */
+#define USB_OTG_HCCHAR_ODDFRM 0x20000000U /*!< Odd frame */
+#define USB_OTG_HCCHAR_CHDIS 0x40000000U /*!< Channel disable */
+#define USB_OTG_HCCHAR_CHENA 0x80000000U /*!< Channel enable */
+
+/******************** Bit definition forUSB_OTG_HCSPLT register ********************/
+
+#define USB_OTG_HCSPLT_PRTADDR 0x0000007FU /*!< Port address */
+#define USB_OTG_HCSPLT_PRTADDR_0 0x00000001U /*!<Bit 0 */
+#define USB_OTG_HCSPLT_PRTADDR_1 0x00000002U /*!<Bit 1 */
+#define USB_OTG_HCSPLT_PRTADDR_2 0x00000004U /*!<Bit 2 */
+#define USB_OTG_HCSPLT_PRTADDR_3 0x00000008U /*!<Bit 3 */
+#define USB_OTG_HCSPLT_PRTADDR_4 0x00000010U /*!<Bit 4 */
+#define USB_OTG_HCSPLT_PRTADDR_5 0x00000020U /*!<Bit 5 */
+#define USB_OTG_HCSPLT_PRTADDR_6 0x00000040U /*!<Bit 6 */
+
+#define USB_OTG_HCSPLT_HUBADDR 0x00003F80U /*!< Hub address */
+#define USB_OTG_HCSPLT_HUBADDR_0 0x00000080U /*!<Bit 0 */
+#define USB_OTG_HCSPLT_HUBADDR_1 0x00000100U /*!<Bit 1 */
+#define USB_OTG_HCSPLT_HUBADDR_2 0x00000200U /*!<Bit 2 */
+#define USB_OTG_HCSPLT_HUBADDR_3 0x00000400U /*!<Bit 3 */
+#define USB_OTG_HCSPLT_HUBADDR_4 0x00000800U /*!<Bit 4 */
+#define USB_OTG_HCSPLT_HUBADDR_5 0x00001000U /*!<Bit 5 */
+#define USB_OTG_HCSPLT_HUBADDR_6 0x00002000U /*!<Bit 6 */
+
+#define USB_OTG_HCSPLT_XACTPOS 0x0000C000U /*!< XACTPOS */
+#define USB_OTG_HCSPLT_XACTPOS_0 0x00004000U /*!<Bit 0 */
+#define USB_OTG_HCSPLT_XACTPOS_1 0x00008000U /*!<Bit 1 */
+#define USB_OTG_HCSPLT_COMPLSPLT 0x00010000U /*!< Do complete split */
+#define USB_OTG_HCSPLT_SPLITEN 0x80000000U /*!< Split enable */
+
+/******************** Bit definition forUSB_OTG_HCINT register ********************/
+#define USB_OTG_HCINT_XFRC 0x00000001U /*!< Transfer completed */
+#define USB_OTG_HCINT_CHH 0x00000002U /*!< Channel halted */
+#define USB_OTG_HCINT_AHBERR 0x00000004U /*!< AHB error */
+#define USB_OTG_HCINT_STALL 0x00000008U /*!< STALL response received interrupt */
+#define USB_OTG_HCINT_NAK 0x00000010U /*!< NAK response received interrupt */
+#define USB_OTG_HCINT_ACK 0x00000020U /*!< ACK response received/transmitted interrupt */
+#define USB_OTG_HCINT_NYET 0x00000040U /*!< Response received interrupt */
+#define USB_OTG_HCINT_TXERR 0x00000080U /*!< Transaction error */
+#define USB_OTG_HCINT_BBERR 0x00000100U /*!< Babble error */
+#define USB_OTG_HCINT_FRMOR 0x00000200U /*!< Frame overrun */
+#define USB_OTG_HCINT_DTERR 0x00000400U /*!< Data toggle error */
+
+/******************** Bit definition forUSB_OTG_DIEPINT register ********************/
+#define USB_OTG_DIEPINT_XFRC 0x00000001U /*!< Transfer completed interrupt */
+#define USB_OTG_DIEPINT_EPDISD 0x00000002U /*!< Endpoint disabled interrupt */
+#define USB_OTG_DIEPINT_TOC 0x00000008U /*!< Timeout condition */
+#define USB_OTG_DIEPINT_ITTXFE 0x00000010U /*!< IN token received when TxFIFO is empty */
+#define USB_OTG_DIEPINT_INEPNE 0x00000040U /*!< IN endpoint NAK effective */
+#define USB_OTG_DIEPINT_TXFE 0x00000080U /*!< Transmit FIFO empty */
+#define USB_OTG_DIEPINT_TXFIFOUDRN 0x00000100U /*!< Transmit Fifo Underrun */
+#define USB_OTG_DIEPINT_BNA 0x00000200U /*!< Buffer not available interrupt */
+#define USB_OTG_DIEPINT_PKTDRPSTS 0x00000800U /*!< Packet dropped status */
+#define USB_OTG_DIEPINT_BERR 0x00001000U /*!< Babble error interrupt */
+#define USB_OTG_DIEPINT_NAK 0x00002000U /*!< NAK interrupt */
+
+/******************** Bit definition forUSB_OTG_HCINTMSK register ********************/
+#define USB_OTG_HCINTMSK_XFRCM 0x00000001U /*!< Transfer completed mask */
+#define USB_OTG_HCINTMSK_CHHM 0x00000002U /*!< Channel halted mask */
+#define USB_OTG_HCINTMSK_AHBERR 0x00000004U /*!< AHB error */
+#define USB_OTG_HCINTMSK_STALLM 0x00000008U /*!< STALL response received interrupt mask */
+#define USB_OTG_HCINTMSK_NAKM 0x00000010U /*!< NAK response received interrupt mask */
+#define USB_OTG_HCINTMSK_ACKM 0x00000020U /*!< ACK response received/transmitted interrupt mask */
+#define USB_OTG_HCINTMSK_NYET 0x00000040U /*!< response received interrupt mask */
+#define USB_OTG_HCINTMSK_TXERRM 0x00000080U /*!< Transaction error mask */
+#define USB_OTG_HCINTMSK_BBERRM 0x00000100U /*!< Babble error mask */
+#define USB_OTG_HCINTMSK_FRMORM 0x00000200U /*!< Frame overrun mask */
+#define USB_OTG_HCINTMSK_DTERRM 0x00000400U /*!< Data toggle error mask */
+
+/******************** Bit definition for USB_OTG_DIEPTSIZ register ********************/
+
+#define USB_OTG_DIEPTSIZ_XFRSIZ 0x0007FFFFU /*!< Transfer size */
+#define USB_OTG_DIEPTSIZ_PKTCNT 0x1FF80000U /*!< Packet count */
+#define USB_OTG_DIEPTSIZ_MULCNT 0x60000000U /*!< Packet count */
+/******************** Bit definition forUSB_OTG_HCTSIZ register ********************/
+#define USB_OTG_HCTSIZ_XFRSIZ 0x0007FFFFU /*!< Transfer size */
+#define USB_OTG_HCTSIZ_PKTCNT 0x1FF80000U /*!< Packet count */
+#define USB_OTG_HCTSIZ_DOPING 0x80000000U /*!< Do PING */
+#define USB_OTG_HCTSIZ_DPID 0x60000000U /*!< Data PID */
+#define USB_OTG_HCTSIZ_DPID_0 0x20000000U /*!<Bit 0 */
+#define USB_OTG_HCTSIZ_DPID_1 0x40000000U /*!<Bit 1 */
+
+/******************** Bit definition forUSB_OTG_DIEPDMA register ********************/
+#define USB_OTG_DIEPDMA_DMAADDR 0xFFFFFFFFU /*!< DMA address */
+
+/******************** Bit definition forUSB_OTG_HCDMA register ********************/
+#define USB_OTG_HCDMA_DMAADDR 0xFFFFFFFFU /*!< DMA address */
+
+/******************** Bit definition forUSB_OTG_DTXFSTS register ********************/
+#define USB_OTG_DTXFSTS_INEPTFSAV 0x0000FFFFU /*!< IN endpoint TxFIFO space available */
+
+/******************** Bit definition forUSB_OTG_DIEPTXF register ********************/
+#define USB_OTG_DIEPTXF_INEPTXSA 0x0000FFFFU /*!< IN endpoint FIFOx transmit RAM start address */
+#define USB_OTG_DIEPTXF_INEPTXFD 0xFFFF0000U /*!< IN endpoint TxFIFO depth */
+
+/******************** Bit definition forUSB_OTG_DOEPCTL register ********************/
+
+#define USB_OTG_DOEPCTL_MPSIZ 0x000007FFU /*!< Maximum packet size */ /*!<Bit 1 */
+#define USB_OTG_DOEPCTL_USBAEP 0x00008000U /*!< USB active endpoint */
+#define USB_OTG_DOEPCTL_NAKSTS 0x00020000U /*!< NAK status */
+#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM 0x10000000U /*!< Set DATA0 PID */
+#define USB_OTG_DOEPCTL_SODDFRM 0x20000000U /*!< Set odd frame */
+#define USB_OTG_DOEPCTL_EPTYP 0x000C0000U /*!< Endpoint type */
+#define USB_OTG_DOEPCTL_EPTYP_0 0x00040000U /*!<Bit 0 */
+#define USB_OTG_DOEPCTL_EPTYP_1 0x00080000U /*!<Bit 1 */
+#define USB_OTG_DOEPCTL_SNPM 0x00100000U /*!< Snoop mode */
+#define USB_OTG_DOEPCTL_STALL 0x00200000U /*!< STALL handshake */
+#define USB_OTG_DOEPCTL_CNAK 0x04000000U /*!< Clear NAK */
+#define USB_OTG_DOEPCTL_SNAK 0x08000000U /*!< Set NAK */
+#define USB_OTG_DOEPCTL_EPDIS 0x40000000U /*!< Endpoint disable */
+#define USB_OTG_DOEPCTL_EPENA 0x80000000U /*!< Endpoint enable */
+
+/******************** Bit definition forUSB_OTG_DOEPINT register ********************/
+#define USB_OTG_DOEPINT_XFRC 0x00000001U /*!< Transfer completed interrupt */
+#define USB_OTG_DOEPINT_EPDISD 0x00000002U /*!< Endpoint disabled interrupt */
+#define USB_OTG_DOEPINT_STUP 0x00000008U /*!< SETUP phase done */
+#define USB_OTG_DOEPINT_OTEPDIS 0x00000010U /*!< OUT token received when endpoint disabled */
+#define USB_OTG_DOEPINT_B2BSTUP 0x00000040U /*!< Back-to-back SETUP packets received */
+#define USB_OTG_DOEPINT_NYET 0x00004000U /*!< NYET interrupt */
+
+/******************** Bit definition forUSB_OTG_DOEPTSIZ register ********************/
+
+#define USB_OTG_DOEPTSIZ_XFRSIZ 0x0007FFFFU /*!< Transfer size */
+#define USB_OTG_DOEPTSIZ_PKTCNT 0x1FF80000U /*!< Packet count */
+
+#define USB_OTG_DOEPTSIZ_STUPCNT 0x60000000U /*!< SETUP packet count */
+#define USB_OTG_DOEPTSIZ_STUPCNT_0 0x20000000U /*!<Bit 0 */
+#define USB_OTG_DOEPTSIZ_STUPCNT_1 0x40000000U /*!<Bit 1 */
+
+/******************** Bit definition for PCGCCTL register ********************/
+#define USB_OTG_PCGCCTL_STOPCLK 0x00000001U /*!< SETUP packet count */
+#define USB_OTG_PCGCCTL_GATECLK 0x00000002U /*!<Bit 0 */
+#define USB_OTG_PCGCCTL_PHYSUSP 0x00000010U /*!<Bit 1 */
+
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup Exported_macros
+ * @{
+ */
+
+/******************************* ADC Instances ********************************/
+#define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) || \
+ ((INSTANCE) == ADC2) || \
+ ((INSTANCE) == ADC3))
+
+/******************************* CAN Instances ********************************/
+#define IS_CAN_ALL_INSTANCE(INSTANCE) (((INSTANCE) == CAN1) || \
+ ((INSTANCE) == CAN2))
+
+/******************************* CRC Instances ********************************/
+#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
+
+/******************************* DAC Instances ********************************/
+#define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC)
+
+/******************************* DCMI Instances *******************************/
+#define IS_DCMI_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DCMI)
+
+/******************************* DMA2D Instances *******************************/
+#define IS_DMA2D_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DMA2D)
+
+/******************************** DMA Instances *******************************/
+#define IS_DMA_STREAM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0) || \
+ ((INSTANCE) == DMA1_Stream1) || \
+ ((INSTANCE) == DMA1_Stream2) || \
+ ((INSTANCE) == DMA1_Stream3) || \
+ ((INSTANCE) == DMA1_Stream4) || \
+ ((INSTANCE) == DMA1_Stream5) || \
+ ((INSTANCE) == DMA1_Stream6) || \
+ ((INSTANCE) == DMA1_Stream7) || \
+ ((INSTANCE) == DMA2_Stream0) || \
+ ((INSTANCE) == DMA2_Stream1) || \
+ ((INSTANCE) == DMA2_Stream2) || \
+ ((INSTANCE) == DMA2_Stream3) || \
+ ((INSTANCE) == DMA2_Stream4) || \
+ ((INSTANCE) == DMA2_Stream5) || \
+ ((INSTANCE) == DMA2_Stream6) || \
+ ((INSTANCE) == DMA2_Stream7))
+
+/******************************* GPIO Instances *******************************/
+#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
+ ((INSTANCE) == GPIOB) || \
+ ((INSTANCE) == GPIOC) || \
+ ((INSTANCE) == GPIOD) || \
+ ((INSTANCE) == GPIOE) || \
+ ((INSTANCE) == GPIOF) || \
+ ((INSTANCE) == GPIOG) || \
+ ((INSTANCE) == GPIOH) || \
+ ((INSTANCE) == GPIOI) || \
+ ((INSTANCE) == GPIOJ) || \
+ ((INSTANCE) == GPIOK))
+
+/******************************** I2C Instances *******************************/
+#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
+ ((INSTANCE) == I2C2) || \
+ ((INSTANCE) == I2C3))
+
+/******************************** I2S Instances *******************************/
+#define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI2) || \
+ ((INSTANCE) == SPI3))
+
+/*************************** I2S Extended Instances ***************************/
+#define IS_I2S_ALL_INSTANCE_EXT(PERIPH) (((INSTANCE) == SPI2) || \
+ ((INSTANCE) == SPI3) || \
+ ((INSTANCE) == I2S2ext) || \
+ ((INSTANCE) == I2S3ext))
+
+/****************************** LTDC Instances ********************************/
+#define IS_LTDC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == LTDC)
+
+/******************************* RNG Instances ********************************/
+#define IS_RNG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RNG)
+
+/****************************** RTC Instances *********************************/
+#define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
+
+/******************************* SAI Instances ********************************/
+#define IS_SAI_ALL_INSTANCE(PERIPH) (((PERIPH) == SAI1_Block_A) || \
+ ((PERIPH) == SAI1_Block_B))
+/* Legacy define */
+#define IS_SAI_BLOCK_PERIPH IS_SAI_ALL_INSTANCE
+
+/******************************** SPI Instances *******************************/
+#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
+ ((INSTANCE) == SPI2) || \
+ ((INSTANCE) == SPI3) || \
+ ((INSTANCE) == SPI4) || \
+ ((INSTANCE) == SPI5) || \
+ ((INSTANCE) == SPI6))
+
+/*************************** SPI Extended Instances ***************************/
+#define IS_SPI_ALL_INSTANCE_EXT(INSTANCE) (((INSTANCE) == SPI1) || \
+ ((INSTANCE) == SPI2) || \
+ ((INSTANCE) == SPI3) || \
+ ((INSTANCE) == SPI4) || \
+ ((INSTANCE) == SPI5) || \
+ ((INSTANCE) == SPI6) || \
+ ((INSTANCE) == I2S2ext) || \
+ ((INSTANCE) == I2S3ext))
+
+/****************** TIM Instances : All supported instances *******************/
+#define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM6) || \
+ ((INSTANCE) == TIM7) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM9) || \
+ ((INSTANCE) == TIM10) || \
+ ((INSTANCE) == TIM11) || \
+ ((INSTANCE) == TIM12) || \
+ ((INSTANCE) == TIM13) || \
+ ((INSTANCE) == TIM14))
+
+/************* TIM Instances : at least 1 capture/compare channel *************/
+#define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM9) || \
+ ((INSTANCE) == TIM10) || \
+ ((INSTANCE) == TIM11) || \
+ ((INSTANCE) == TIM12) || \
+ ((INSTANCE) == TIM13) || \
+ ((INSTANCE) == TIM14))
+
+/************ TIM Instances : at least 2 capture/compare channels *************/
+#define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM9) || \
+ ((INSTANCE) == TIM12))
+
+/************ TIM Instances : at least 3 capture/compare channels *************/
+#define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8))
+
+/************ TIM Instances : at least 4 capture/compare channels *************/
+#define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8))
+
+/******************** TIM Instances : Advanced-control timers *****************/
+#define IS_TIM_ADVANCED_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM8))
+
+/******************* TIM Instances : Timer input XOR function *****************/
+#define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8))
+
+/****************** TIM Instances : DMA requests generation (UDE) *************/
+#define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM6) || \
+ ((INSTANCE) == TIM7) || \
+ ((INSTANCE) == TIM8))
+
+/************ TIM Instances : DMA requests generation (CCxDE) *****************/
+#define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8))
+
+/************ TIM Instances : DMA requests generation (COMDE) *****************/
+#define IS_TIM_CCDMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8))
+
+/******************** TIM Instances : DMA burst feature ***********************/
+#define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8))
+
+/****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/
+#define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM6) || \
+ ((INSTANCE) == TIM7) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM9) || \
+ ((INSTANCE) == TIM12))
+
+/*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
+#define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM9) || \
+ ((INSTANCE) == TIM12))
+
+/********************** TIM Instances : 32 bit Counter ************************/
+#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)(((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM5))
+
+/***************** TIM Instances : external trigger input availabe ************/
+#define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8))
+
+/****************** TIM Instances : remapping capability **********************/
+#define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM11))
+
+/******************* TIM Instances : output(s) available **********************/
+#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
+ ((((INSTANCE) == TIM1) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM2) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM3) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM4) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM5) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM8) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM9) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2))) \
+ || \
+ (((INSTANCE) == TIM10) && \
+ (((CHANNEL) == TIM_CHANNEL_1))) \
+ || \
+ (((INSTANCE) == TIM11) && \
+ (((CHANNEL) == TIM_CHANNEL_1))) \
+ || \
+ (((INSTANCE) == TIM12) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2))) \
+ || \
+ (((INSTANCE) == TIM13) && \
+ (((CHANNEL) == TIM_CHANNEL_1))) \
+ || \
+ (((INSTANCE) == TIM14) && \
+ (((CHANNEL) == TIM_CHANNEL_1))))
+
+/************ TIM Instances : complementary output(s) available ***************/
+#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
+ ((((INSTANCE) == TIM1) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3))) \
+ || \
+ (((INSTANCE) == TIM8) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3))))
+
+/******************** USART Instances : Synchronous mode **********************/
+#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3) || \
+ ((INSTANCE) == USART6))
+
+/******************** UART Instances : Asynchronous mode **********************/
+#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3) || \
+ ((INSTANCE) == UART4) || \
+ ((INSTANCE) == UART5) || \
+ ((INSTANCE) == USART6) || \
+ ((INSTANCE) == UART7) || \
+ ((INSTANCE) == UART8))
+
+/****************** UART Instances : Hardware Flow control ********************/
+#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3) || \
+ ((INSTANCE) == USART6))
+
+/********************* UART Instances : Smard card mode ***********************/
+#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3) || \
+ ((INSTANCE) == USART6))
+
+/*********************** UART Instances : IRDA mode ***************************/
+#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3) || \
+ ((INSTANCE) == UART4) || \
+ ((INSTANCE) == UART5) || \
+ ((INSTANCE) == USART6) || \
+ ((INSTANCE) == UART7) || \
+ ((INSTANCE) == UART8))
+
+/*********************** PCD Instances ****************************************/
+#define IS_PCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS) || \
+ ((INSTANCE) == USB_OTG_HS))
+
+/*********************** HCD Instances ****************************************/
+#define IS_HCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS) || \
+ ((INSTANCE) == USB_OTG_HS))
+
+
+/****************************** IWDG Instances ********************************/
+#define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
+
+/****************************** WWDG Instances ********************************/
+#define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
+
+/****************************** SDIO Instances ********************************/
+#define IS_SDIO_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SDIO)
+
+/****************************** USB Exported Constants ************************/
+#define USB_OTG_FS_HOST_MAX_CHANNEL_NBR 8U
+#define USB_OTG_FS_MAX_IN_ENDPOINTS 4U /* Including EP0 */
+#define USB_OTG_FS_MAX_OUT_ENDPOINTS 4U /* Including EP0 */
+#define USB_OTG_FS_TOTAL_FIFO_SIZE 1280U /* in Bytes */
+
+#define USB_OTG_HS_HOST_MAX_CHANNEL_NBR 12U
+#define USB_OTG_HS_MAX_IN_ENDPOINTS 6U /* Including EP0 */
+#define USB_OTG_HS_MAX_OUT_ENDPOINTS 6U /* Including EP0 */
+#define USB_OTG_HS_TOTAL_FIFO_SIZE 4096U /* in Bytes */
+
+/******************************************************************************/
+/* For a painless codes migration between the STM32F4xx device product */
+/* lines, the aliases defined below are put in place to overcome the */
+/* differences in the interrupt handlers and IRQn definitions. */
+/* No need to update developed interrupt code when moving across */
+/* product lines within the same STM32F4 Family */
+/******************************************************************************/
+
+/* Aliases for __IRQn */
+#define FSMC_IRQn FMC_IRQn
+
+/* Aliases for __IRQHandler */
+#define FSMC_IRQHandler FMC_IRQHandler
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* __STM32F429xx_H */
+
+
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Device/ST/STM32F4xx/Include/stm32f437xx.h b/Device/ST/STM32F4xx/Include/stm32f437xx.h
new file mode 100644
index 0000000..3538c8b
--- /dev/null
+++ b/Device/ST/STM32F4xx/Include/stm32f437xx.h
@@ -0,0 +1,9093 @@
+/**
+ ******************************************************************************
+ * @file stm32f437xx.h
+ * @author MCD Application Team
+ * @version V2.5.0
+ * @date 22-April-2016
+ * @brief CMSIS STM32F437xx Device Peripheral Access Layer Header File.
+ *
+ * This file contains:
+ * - Data structures and the address mapping for all peripherals
+ * - peripherals registers declarations and bits definition
+ * - Macros to access peripheral’s registers hardware
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/** @addtogroup CMSIS_Device
+ * @{
+ */
+
+/** @addtogroup stm32f437xx
+ * @{
+ */
+
+#ifndef __STM32F437xx_H
+#define __STM32F437xx_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif /* __cplusplus */
+
+/** @addtogroup Configuration_section_for_CMSIS
+ * @{
+ */
+
+/**
+ * @brief Configuration of the Cortex-M4 Processor and Core Peripherals
+ */
+#define __CM4_REV 0x0001U /*!< Core revision r0p1 */
+#define __MPU_PRESENT 1U /*!< STM32F4XX provides an MPU */
+#define __NVIC_PRIO_BITS 4U /*!< STM32F4XX uses 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */
+#define __FPU_PRESENT 1U /*!< FPU present */
+
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_interrupt_number_definition
+ * @{
+ */
+
+/**
+ * @brief STM32F4XX Interrupt Number Definition, according to the selected device
+ * in @ref Library_configuration_section
+ */
+typedef enum
+{
+/****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/
+ NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
+ MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */
+ BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */
+ UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */
+ SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */
+ DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */
+ PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */
+ SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */
+/****** STM32 specific Interrupt Numbers **********************************************************************/
+ WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
+ PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */
+ TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */
+ RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */
+ FLASH_IRQn = 4, /*!< FLASH global Interrupt */
+ RCC_IRQn = 5, /*!< RCC global Interrupt */
+ EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */
+ EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */
+ EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */
+ EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */
+ EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */
+ DMA1_Stream0_IRQn = 11, /*!< DMA1 Stream 0 global Interrupt */
+ DMA1_Stream1_IRQn = 12, /*!< DMA1 Stream 1 global Interrupt */
+ DMA1_Stream2_IRQn = 13, /*!< DMA1 Stream 2 global Interrupt */
+ DMA1_Stream3_IRQn = 14, /*!< DMA1 Stream 3 global Interrupt */
+ DMA1_Stream4_IRQn = 15, /*!< DMA1 Stream 4 global Interrupt */
+ DMA1_Stream5_IRQn = 16, /*!< DMA1 Stream 5 global Interrupt */
+ DMA1_Stream6_IRQn = 17, /*!< DMA1 Stream 6 global Interrupt */
+ ADC_IRQn = 18, /*!< ADC1, ADC2 and ADC3 global Interrupts */
+ CAN1_TX_IRQn = 19, /*!< CAN1 TX Interrupt */
+ CAN1_RX0_IRQn = 20, /*!< CAN1 RX0 Interrupt */
+ CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */
+ CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */
+ EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
+ TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break interrupt and TIM9 global interrupt */
+ TIM1_UP_TIM10_IRQn = 25, /*!< TIM1 Update Interrupt and TIM10 global interrupt */
+ TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */
+ TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
+ TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
+ TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
+ TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
+ I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
+ I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
+ I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
+ I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
+ SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
+ SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
+ USART1_IRQn = 37, /*!< USART1 global Interrupt */
+ USART2_IRQn = 38, /*!< USART2 global Interrupt */
+ USART3_IRQn = 39, /*!< USART3 global Interrupt */
+ EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
+ RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */
+ OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS Wakeup through EXTI line interrupt */
+ TIM8_BRK_TIM12_IRQn = 43, /*!< TIM8 Break Interrupt and TIM12 global interrupt */
+ TIM8_UP_TIM13_IRQn = 44, /*!< TIM8 Update Interrupt and TIM13 global interrupt */
+ TIM8_TRG_COM_TIM14_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */
+ TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */
+ DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */
+ FMC_IRQn = 48, /*!< FMC global Interrupt */
+ SDIO_IRQn = 49, /*!< SDIO global Interrupt */
+ TIM5_IRQn = 50, /*!< TIM5 global Interrupt */
+ SPI3_IRQn = 51, /*!< SPI3 global Interrupt */
+ UART4_IRQn = 52, /*!< UART4 global Interrupt */
+ UART5_IRQn = 53, /*!< UART5 global Interrupt */
+ TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC1&2 underrun error interrupts */
+ TIM7_IRQn = 55, /*!< TIM7 global interrupt */
+ DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */
+ DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */
+ DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */
+ DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */
+ DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */
+ ETH_IRQn = 61, /*!< Ethernet global Interrupt */
+ ETH_WKUP_IRQn = 62, /*!< Ethernet Wakeup through EXTI line Interrupt */
+ CAN2_TX_IRQn = 63, /*!< CAN2 TX Interrupt */
+ CAN2_RX0_IRQn = 64, /*!< CAN2 RX0 Interrupt */
+ CAN2_RX1_IRQn = 65, /*!< CAN2 RX1 Interrupt */
+ CAN2_SCE_IRQn = 66, /*!< CAN2 SCE Interrupt */
+ OTG_FS_IRQn = 67, /*!< USB OTG FS global Interrupt */
+ DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */
+ DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */
+ DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */
+ USART6_IRQn = 71, /*!< USART6 global interrupt */
+ I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */
+ I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */
+ OTG_HS_EP1_OUT_IRQn = 74, /*!< USB OTG HS End Point 1 Out global interrupt */
+ OTG_HS_EP1_IN_IRQn = 75, /*!< USB OTG HS End Point 1 In global interrupt */
+ OTG_HS_WKUP_IRQn = 76, /*!< USB OTG HS Wakeup through EXTI interrupt */
+ OTG_HS_IRQn = 77, /*!< USB OTG HS global interrupt */
+ DCMI_IRQn = 78, /*!< DCMI global interrupt */
+ CRYP_IRQn = 79, /*!< CRYP crypto global interrupt */
+ HASH_RNG_IRQn = 80, /*!< Hash and Rng global interrupt */
+ FPU_IRQn = 81, /*!< FPU global interrupt */
+ UART7_IRQn = 82, /*!< UART7 global interrupt */
+ UART8_IRQn = 83, /*!< UART8 global interrupt */
+ SPI4_IRQn = 84, /*!< SPI4 global Interrupt */
+ SPI5_IRQn = 85, /*!< SPI5 global Interrupt */
+ SPI6_IRQn = 86, /*!< SPI6 global Interrupt */
+ SAI1_IRQn = 87, /*!< SAI1 global Interrupt */
+ DMA2D_IRQn = 90 /*!< DMA2D global Interrupt */
+} IRQn_Type;
+
+/**
+ * @}
+ */
+
+#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
+#include "system_stm32f4xx.h"
+#include <stdint.h>
+
+/** @addtogroup Peripheral_registers_structures
+ * @{
+ */
+
+/**
+ * @brief Analog to Digital Converter
+ */
+
+typedef struct
+{
+ __IO uint32_t SR; /*!< ADC status register, Address offset: 0x00 */
+ __IO uint32_t CR1; /*!< ADC control register 1, Address offset: 0x04 */
+ __IO uint32_t CR2; /*!< ADC control register 2, Address offset: 0x08 */
+ __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x0C */
+ __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x10 */
+ __IO uint32_t JOFR1; /*!< ADC injected channel data offset register 1, Address offset: 0x14 */
+ __IO uint32_t JOFR2; /*!< ADC injected channel data offset register 2, Address offset: 0x18 */
+ __IO uint32_t JOFR3; /*!< ADC injected channel data offset register 3, Address offset: 0x1C */
+ __IO uint32_t JOFR4; /*!< ADC injected channel data offset register 4, Address offset: 0x20 */
+ __IO uint32_t HTR; /*!< ADC watchdog higher threshold register, Address offset: 0x24 */
+ __IO uint32_t LTR; /*!< ADC watchdog lower threshold register, Address offset: 0x28 */
+ __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x2C */
+ __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x30 */
+ __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x34 */
+ __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x38*/
+ __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x3C */
+ __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x40 */
+ __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x44 */
+ __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x48 */
+ __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x4C */
+} ADC_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1 base address + 0x300 */
+ __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1 base address + 0x304 */
+ __IO uint32_t CDR; /*!< ADC common regular data register for dual
+ AND triple modes, Address offset: ADC1 base address + 0x308 */
+} ADC_Common_TypeDef;
+
+
+/**
+ * @brief Controller Area Network TxMailBox
+ */
+
+typedef struct
+{
+ __IO uint32_t TIR; /*!< CAN TX mailbox identifier register */
+ __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */
+ __IO uint32_t TDLR; /*!< CAN mailbox data low register */
+ __IO uint32_t TDHR; /*!< CAN mailbox data high register */
+} CAN_TxMailBox_TypeDef;
+
+/**
+ * @brief Controller Area Network FIFOMailBox
+ */
+
+typedef struct
+{
+ __IO uint32_t RIR; /*!< CAN receive FIFO mailbox identifier register */
+ __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */
+ __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */
+ __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */
+} CAN_FIFOMailBox_TypeDef;
+
+/**
+ * @brief Controller Area Network FilterRegister
+ */
+
+typedef struct
+{
+ __IO uint32_t FR1; /*!< CAN Filter bank register 1 */
+ __IO uint32_t FR2; /*!< CAN Filter bank register 1 */
+} CAN_FilterRegister_TypeDef;
+
+/**
+ * @brief Controller Area Network
+ */
+
+typedef struct
+{
+ __IO uint32_t MCR; /*!< CAN master control register, Address offset: 0x00 */
+ __IO uint32_t MSR; /*!< CAN master status register, Address offset: 0x04 */
+ __IO uint32_t TSR; /*!< CAN transmit status register, Address offset: 0x08 */
+ __IO uint32_t RF0R; /*!< CAN receive FIFO 0 register, Address offset: 0x0C */
+ __IO uint32_t RF1R; /*!< CAN receive FIFO 1 register, Address offset: 0x10 */
+ __IO uint32_t IER; /*!< CAN interrupt enable register, Address offset: 0x14 */
+ __IO uint32_t ESR; /*!< CAN error status register, Address offset: 0x18 */
+ __IO uint32_t BTR; /*!< CAN bit timing register, Address offset: 0x1C */
+ uint32_t RESERVED0[88]; /*!< Reserved, 0x020 - 0x17F */
+ CAN_TxMailBox_TypeDef sTxMailBox[3]; /*!< CAN Tx MailBox, Address offset: 0x180 - 0x1AC */
+ CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; /*!< CAN FIFO MailBox, Address offset: 0x1B0 - 0x1CC */
+ uint32_t RESERVED1[12]; /*!< Reserved, 0x1D0 - 0x1FF */
+ __IO uint32_t FMR; /*!< CAN filter master register, Address offset: 0x200 */
+ __IO uint32_t FM1R; /*!< CAN filter mode register, Address offset: 0x204 */
+ uint32_t RESERVED2; /*!< Reserved, 0x208 */
+ __IO uint32_t FS1R; /*!< CAN filter scale register, Address offset: 0x20C */
+ uint32_t RESERVED3; /*!< Reserved, 0x210 */
+ __IO uint32_t FFA1R; /*!< CAN filter FIFO assignment register, Address offset: 0x214 */
+ uint32_t RESERVED4; /*!< Reserved, 0x218 */
+ __IO uint32_t FA1R; /*!< CAN filter activation register, Address offset: 0x21C */
+ uint32_t RESERVED5[8]; /*!< Reserved, 0x220-0x23F */
+ CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register, Address offset: 0x240-0x31C */
+} CAN_TypeDef;
+
+/**
+ * @brief CRC calculation unit
+ */
+
+typedef struct
+{
+ __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
+ __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
+ uint8_t RESERVED0; /*!< Reserved, 0x05 */
+ uint16_t RESERVED1; /*!< Reserved, 0x06 */
+ __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
+} CRC_TypeDef;
+
+/**
+ * @brief Digital to Analog Converter
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */
+ __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */
+ __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
+ __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */
+ __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */
+ __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
+ __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */
+ __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */
+ __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */
+ __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */
+ __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */
+ __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */
+ __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */
+ __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */
+} DAC_TypeDef;
+
+/**
+ * @brief Debug MCU
+ */
+
+typedef struct
+{
+ __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
+ __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
+ __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */
+ __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */
+}DBGMCU_TypeDef;
+
+/**
+ * @brief DCMI
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< DCMI control register 1, Address offset: 0x00 */
+ __IO uint32_t SR; /*!< DCMI status register, Address offset: 0x04 */
+ __IO uint32_t RISR; /*!< DCMI raw interrupt status register, Address offset: 0x08 */
+ __IO uint32_t IER; /*!< DCMI interrupt enable register, Address offset: 0x0C */
+ __IO uint32_t MISR; /*!< DCMI masked interrupt status register, Address offset: 0x10 */
+ __IO uint32_t ICR; /*!< DCMI interrupt clear register, Address offset: 0x14 */
+ __IO uint32_t ESCR; /*!< DCMI embedded synchronization code register, Address offset: 0x18 */
+ __IO uint32_t ESUR; /*!< DCMI embedded synchronization unmask register, Address offset: 0x1C */
+ __IO uint32_t CWSTRTR; /*!< DCMI crop window start, Address offset: 0x20 */
+ __IO uint32_t CWSIZER; /*!< DCMI crop window size, Address offset: 0x24 */
+ __IO uint32_t DR; /*!< DCMI data register, Address offset: 0x28 */
+} DCMI_TypeDef;
+
+/**
+ * @brief DMA Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< DMA stream x configuration register */
+ __IO uint32_t NDTR; /*!< DMA stream x number of data register */
+ __IO uint32_t PAR; /*!< DMA stream x peripheral address register */
+ __IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */
+ __IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */
+ __IO uint32_t FCR; /*!< DMA stream x FIFO control register */
+} DMA_Stream_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t LISR; /*!< DMA low interrupt status register, Address offset: 0x00 */
+ __IO uint32_t HISR; /*!< DMA high interrupt status register, Address offset: 0x04 */
+ __IO uint32_t LIFCR; /*!< DMA low interrupt flag clear register, Address offset: 0x08 */
+ __IO uint32_t HIFCR; /*!< DMA high interrupt flag clear register, Address offset: 0x0C */
+} DMA_TypeDef;
+
+/**
+ * @brief DMA2D Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< DMA2D Control Register, Address offset: 0x00 */
+ __IO uint32_t ISR; /*!< DMA2D Interrupt Status Register, Address offset: 0x04 */
+ __IO uint32_t IFCR; /*!< DMA2D Interrupt Flag Clear Register, Address offset: 0x08 */
+ __IO uint32_t FGMAR; /*!< DMA2D Foreground Memory Address Register, Address offset: 0x0C */
+ __IO uint32_t FGOR; /*!< DMA2D Foreground Offset Register, Address offset: 0x10 */
+ __IO uint32_t BGMAR; /*!< DMA2D Background Memory Address Register, Address offset: 0x14 */
+ __IO uint32_t BGOR; /*!< DMA2D Background Offset Register, Address offset: 0x18 */
+ __IO uint32_t FGPFCCR; /*!< DMA2D Foreground PFC Control Register, Address offset: 0x1C */
+ __IO uint32_t FGCOLR; /*!< DMA2D Foreground Color Register, Address offset: 0x20 */
+ __IO uint32_t BGPFCCR; /*!< DMA2D Background PFC Control Register, Address offset: 0x24 */
+ __IO uint32_t BGCOLR; /*!< DMA2D Background Color Register, Address offset: 0x28 */
+ __IO uint32_t FGCMAR; /*!< DMA2D Foreground CLUT Memory Address Register, Address offset: 0x2C */
+ __IO uint32_t BGCMAR; /*!< DMA2D Background CLUT Memory Address Register, Address offset: 0x30 */
+ __IO uint32_t OPFCCR; /*!< DMA2D Output PFC Control Register, Address offset: 0x34 */
+ __IO uint32_t OCOLR; /*!< DMA2D Output Color Register, Address offset: 0x38 */
+ __IO uint32_t OMAR; /*!< DMA2D Output Memory Address Register, Address offset: 0x3C */
+ __IO uint32_t OOR; /*!< DMA2D Output Offset Register, Address offset: 0x40 */
+ __IO uint32_t NLR; /*!< DMA2D Number of Line Register, Address offset: 0x44 */
+ __IO uint32_t LWR; /*!< DMA2D Line Watermark Register, Address offset: 0x48 */
+ __IO uint32_t AMTCR; /*!< DMA2D AHB Master Timer Configuration Register, Address offset: 0x4C */
+ uint32_t RESERVED[236]; /*!< Reserved, 0x50-0x3FF */
+ __IO uint32_t FGCLUT[256]; /*!< DMA2D Foreground CLUT, Address offset:400-7FF */
+ __IO uint32_t BGCLUT[256]; /*!< DMA2D Background CLUT, Address offset:800-BFF */
+} DMA2D_TypeDef;
+
+/**
+ * @brief Ethernet MAC
+ */
+
+typedef struct
+{
+ __IO uint32_t MACCR;
+ __IO uint32_t MACFFR;
+ __IO uint32_t MACHTHR;
+ __IO uint32_t MACHTLR;
+ __IO uint32_t MACMIIAR;
+ __IO uint32_t MACMIIDR;
+ __IO uint32_t MACFCR;
+ __IO uint32_t MACVLANTR; /* 8 */
+ uint32_t RESERVED0[2];
+ __IO uint32_t MACRWUFFR; /* 11 */
+ __IO uint32_t MACPMTCSR;
+ uint32_t RESERVED1[2];
+ __IO uint32_t MACSR; /* 15 */
+ __IO uint32_t MACIMR;
+ __IO uint32_t MACA0HR;
+ __IO uint32_t MACA0LR;
+ __IO uint32_t MACA1HR;
+ __IO uint32_t MACA1LR;
+ __IO uint32_t MACA2HR;
+ __IO uint32_t MACA2LR;
+ __IO uint32_t MACA3HR;
+ __IO uint32_t MACA3LR; /* 24 */
+ uint32_t RESERVED2[40];
+ __IO uint32_t MMCCR; /* 65 */
+ __IO uint32_t MMCRIR;
+ __IO uint32_t MMCTIR;
+ __IO uint32_t MMCRIMR;
+ __IO uint32_t MMCTIMR; /* 69 */
+ uint32_t RESERVED3[14];
+ __IO uint32_t MMCTGFSCCR; /* 84 */
+ __IO uint32_t MMCTGFMSCCR;
+ uint32_t RESERVED4[5];
+ __IO uint32_t MMCTGFCR;
+ uint32_t RESERVED5[10];
+ __IO uint32_t MMCRFCECR;
+ __IO uint32_t MMCRFAECR;
+ uint32_t RESERVED6[10];
+ __IO uint32_t MMCRGUFCR;
+ uint32_t RESERVED7[334];
+ __IO uint32_t PTPTSCR;
+ __IO uint32_t PTPSSIR;
+ __IO uint32_t PTPTSHR;
+ __IO uint32_t PTPTSLR;
+ __IO uint32_t PTPTSHUR;
+ __IO uint32_t PTPTSLUR;
+ __IO uint32_t PTPTSAR;
+ __IO uint32_t PTPTTHR;
+ __IO uint32_t PTPTTLR;
+ __IO uint32_t RESERVED8;
+ __IO uint32_t PTPTSSR;
+ uint32_t RESERVED9[565];
+ __IO uint32_t DMABMR;
+ __IO uint32_t DMATPDR;
+ __IO uint32_t DMARPDR;
+ __IO uint32_t DMARDLAR;
+ __IO uint32_t DMATDLAR;
+ __IO uint32_t DMASR;
+ __IO uint32_t DMAOMR;
+ __IO uint32_t DMAIER;
+ __IO uint32_t DMAMFBOCR;
+ __IO uint32_t DMARSWTR;
+ uint32_t RESERVED10[8];
+ __IO uint32_t DMACHTDR;
+ __IO uint32_t DMACHRDR;
+ __IO uint32_t DMACHTBAR;
+ __IO uint32_t DMACHRBAR;
+} ETH_TypeDef;
+
+/**
+ * @brief External Interrupt/Event Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t IMR; /*!< EXTI Interrupt mask register, Address offset: 0x00 */
+ __IO uint32_t EMR; /*!< EXTI Event mask register, Address offset: 0x04 */
+ __IO uint32_t RTSR; /*!< EXTI Rising trigger selection register, Address offset: 0x08 */
+ __IO uint32_t FTSR; /*!< EXTI Falling trigger selection register, Address offset: 0x0C */
+ __IO uint32_t SWIER; /*!< EXTI Software interrupt event register, Address offset: 0x10 */
+ __IO uint32_t PR; /*!< EXTI Pending register, Address offset: 0x14 */
+} EXTI_TypeDef;
+
+/**
+ * @brief FLASH Registers
+ */
+
+typedef struct
+{
+ __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */
+ __IO uint32_t KEYR; /*!< FLASH key register, Address offset: 0x04 */
+ __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x08 */
+ __IO uint32_t SR; /*!< FLASH status register, Address offset: 0x0C */
+ __IO uint32_t CR; /*!< FLASH control register, Address offset: 0x10 */
+ __IO uint32_t OPTCR; /*!< FLASH option control register , Address offset: 0x14 */
+ __IO uint32_t OPTCR1; /*!< FLASH option control register 1, Address offset: 0x18 */
+} FLASH_TypeDef;
+
+/**
+ * @brief Flexible Memory Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */
+} FMC_Bank1_TypeDef;
+
+/**
+ * @brief Flexible Memory Controller Bank1E
+ */
+
+typedef struct
+{
+ __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */
+} FMC_Bank1E_TypeDef;
+
+/**
+ * @brief Flexible Memory Controller Bank2
+ */
+
+typedef struct
+{
+ __IO uint32_t PCR2; /*!< NAND Flash control register 2, Address offset: 0x60 */
+ __IO uint32_t SR2; /*!< NAND Flash FIFO status and interrupt register 2, Address offset: 0x64 */
+ __IO uint32_t PMEM2; /*!< NAND Flash Common memory space timing register 2, Address offset: 0x68 */
+ __IO uint32_t PATT2; /*!< NAND Flash Attribute memory space timing register 2, Address offset: 0x6C */
+ uint32_t RESERVED0; /*!< Reserved, 0x70 */
+ __IO uint32_t ECCR2; /*!< NAND Flash ECC result registers 2, Address offset: 0x74 */
+ uint32_t RESERVED1; /*!< Reserved, 0x78 */
+ uint32_t RESERVED2; /*!< Reserved, 0x7C */
+ __IO uint32_t PCR3; /*!< NAND Flash control register 3, Address offset: 0x80 */
+ __IO uint32_t SR3; /*!< NAND Flash FIFO status and interrupt register 3, Address offset: 0x84 */
+ __IO uint32_t PMEM3; /*!< NAND Flash Common memory space timing register 3, Address offset: 0x88 */
+ __IO uint32_t PATT3; /*!< NAND Flash Attribute memory space timing register 3, Address offset: 0x8C */
+ uint32_t RESERVED3; /*!< Reserved, 0x90 */
+ __IO uint32_t ECCR3; /*!< NAND Flash ECC result registers 3, Address offset: 0x94 */
+} FMC_Bank2_3_TypeDef;
+
+/**
+ * @brief Flexible Memory Controller Bank4
+ */
+
+typedef struct
+{
+ __IO uint32_t PCR4; /*!< PC Card control register 4, Address offset: 0xA0 */
+ __IO uint32_t SR4; /*!< PC Card FIFO status and interrupt register 4, Address offset: 0xA4 */
+ __IO uint32_t PMEM4; /*!< PC Card Common memory space timing register 4, Address offset: 0xA8 */
+ __IO uint32_t PATT4; /*!< PC Card Attribute memory space timing register 4, Address offset: 0xAC */
+ __IO uint32_t PIO4; /*!< PC Card I/O space timing register 4, Address offset: 0xB0 */
+} FMC_Bank4_TypeDef;
+
+/**
+ * @brief Flexible Memory Controller Bank5_6
+ */
+
+typedef struct
+{
+ __IO uint32_t SDCR[2]; /*!< SDRAM Control registers , Address offset: 0x140-0x144 */
+ __IO uint32_t SDTR[2]; /*!< SDRAM Timing registers , Address offset: 0x148-0x14C */
+ __IO uint32_t SDCMR; /*!< SDRAM Command Mode register, Address offset: 0x150 */
+ __IO uint32_t SDRTR; /*!< SDRAM Refresh Timer register, Address offset: 0x154 */
+ __IO uint32_t SDSR; /*!< SDRAM Status register, Address offset: 0x158 */
+} FMC_Bank5_6_TypeDef;
+
+/**
+ * @brief General Purpose I/O
+ */
+
+typedef struct
+{
+ __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
+ __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */
+ __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */
+ __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
+ __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
+ __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
+ __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */
+ __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
+ __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */
+} GPIO_TypeDef;
+
+/**
+ * @brief System configuration controller
+ */
+
+typedef struct
+{
+ __IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */
+ __IO uint32_t PMC; /*!< SYSCFG peripheral mode configuration register, Address offset: 0x04 */
+ __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
+ uint32_t RESERVED[2]; /*!< Reserved, 0x18-0x1C */
+ __IO uint32_t CMPCR; /*!< SYSCFG Compensation cell control register, Address offset: 0x20 */
+} SYSCFG_TypeDef;
+
+/**
+ * @brief Inter-integrated Circuit Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */
+ __IO uint32_t OAR1; /*!< I2C Own address register 1, Address offset: 0x08 */
+ __IO uint32_t OAR2; /*!< I2C Own address register 2, Address offset: 0x0C */
+ __IO uint32_t DR; /*!< I2C Data register, Address offset: 0x10 */
+ __IO uint32_t SR1; /*!< I2C Status register 1, Address offset: 0x14 */
+ __IO uint32_t SR2; /*!< I2C Status register 2, Address offset: 0x18 */
+ __IO uint32_t CCR; /*!< I2C Clock control register, Address offset: 0x1C */
+ __IO uint32_t TRISE; /*!< I2C TRISE register, Address offset: 0x20 */
+ __IO uint32_t FLTR; /*!< I2C FLTR register, Address offset: 0x24 */
+} I2C_TypeDef;
+
+/**
+ * @brief Independent WATCHDOG
+ */
+
+typedef struct
+{
+ __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */
+ __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */
+ __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */
+ __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */
+} IWDG_TypeDef;
+
+
+/**
+ * @brief Power Control
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */
+ __IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */
+} PWR_TypeDef;
+
+/**
+ * @brief Reset and Clock Control
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */
+ __IO uint32_t PLLCFGR; /*!< RCC PLL configuration register, Address offset: 0x04 */
+ __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x08 */
+ __IO uint32_t CIR; /*!< RCC clock interrupt register, Address offset: 0x0C */
+ __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x10 */
+ __IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x14 */
+ __IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0x18 */
+ uint32_t RESERVED0; /*!< Reserved, 0x1C */
+ __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x20 */
+ __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x24 */
+ uint32_t RESERVED1[2]; /*!< Reserved, 0x28-0x2C */
+ __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clock register, Address offset: 0x30 */
+ __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clock register, Address offset: 0x34 */
+ __IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clock register, Address offset: 0x38 */
+ uint32_t RESERVED2; /*!< Reserved, 0x3C */
+ __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x40 */
+ __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x44 */
+ uint32_t RESERVED3[2]; /*!< Reserved, 0x48-0x4C */
+ __IO uint32_t AHB1LPENR; /*!< RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 */
+ __IO uint32_t AHB2LPENR; /*!< RCC AHB2 peripheral clock enable in low power mode register, Address offset: 0x54 */
+ __IO uint32_t AHB3LPENR; /*!< RCC AHB3 peripheral clock enable in low power mode register, Address offset: 0x58 */
+ uint32_t RESERVED4; /*!< Reserved, 0x5C */
+ __IO uint32_t APB1LPENR; /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 */
+ __IO uint32_t APB2LPENR; /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 */
+ uint32_t RESERVED5[2]; /*!< Reserved, 0x68-0x6C */
+ __IO uint32_t BDCR; /*!< RCC Backup domain control register, Address offset: 0x70 */
+ __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x74 */
+ uint32_t RESERVED6[2]; /*!< Reserved, 0x78-0x7C */
+ __IO uint32_t SSCGR; /*!< RCC spread spectrum clock generation register, Address offset: 0x80 */
+ __IO uint32_t PLLI2SCFGR; /*!< RCC PLLI2S configuration register, Address offset: 0x84 */
+ __IO uint32_t PLLSAICFGR; /*!< RCC PLLSAI configuration register, Address offset: 0x88 */
+ __IO uint32_t DCKCFGR; /*!< RCC Dedicated Clocks configuration register, Address offset: 0x8C */
+
+} RCC_TypeDef;
+
+/**
+ * @brief Real-Time Clock
+ */
+
+typedef struct
+{
+ __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
+ __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */
+ __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */
+ __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */
+ __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */
+ __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */
+ __IO uint32_t CALIBR; /*!< RTC calibration register, Address offset: 0x18 */
+ __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */
+ __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */
+ __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */
+ __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */
+ __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */
+ __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */
+ __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */
+ __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */
+ __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */
+ __IO uint32_t TAFCR; /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */
+ __IO uint32_t ALRMASSR;/*!< RTC alarm A sub second register, Address offset: 0x44 */
+ __IO uint32_t ALRMBSSR;/*!< RTC alarm B sub second register, Address offset: 0x48 */
+ uint32_t RESERVED7; /*!< Reserved, 0x4C */
+ __IO uint32_t BKP0R; /*!< RTC backup register 1, Address offset: 0x50 */
+ __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */
+ __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */
+ __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */
+ __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */
+ __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */
+ __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */
+ __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */
+ __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */
+ __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */
+ __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */
+ __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */
+ __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */
+ __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */
+ __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */
+ __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */
+ __IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */
+ __IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */
+ __IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */
+ __IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */
+} RTC_TypeDef;
+
+/**
+ * @brief Serial Audio Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t GCR; /*!< SAI global configuration register, Address offset: 0x00 */
+} SAI_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t CR1; /*!< SAI block x configuration register 1, Address offset: 0x04 */
+ __IO uint32_t CR2; /*!< SAI block x configuration register 2, Address offset: 0x08 */
+ __IO uint32_t FRCR; /*!< SAI block x frame configuration register, Address offset: 0x0C */
+ __IO uint32_t SLOTR; /*!< SAI block x slot register, Address offset: 0x10 */
+ __IO uint32_t IMR; /*!< SAI block x interrupt mask register, Address offset: 0x14 */
+ __IO uint32_t SR; /*!< SAI block x status register, Address offset: 0x18 */
+ __IO uint32_t CLRFR; /*!< SAI block x clear flag register, Address offset: 0x1C */
+ __IO uint32_t DR; /*!< SAI block x data register, Address offset: 0x20 */
+} SAI_Block_TypeDef;
+
+/**
+ * @brief SD host Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t POWER; /*!< SDIO power control register, Address offset: 0x00 */
+ __IO uint32_t CLKCR; /*!< SDI clock control register, Address offset: 0x04 */
+ __IO uint32_t ARG; /*!< SDIO argument register, Address offset: 0x08 */
+ __IO uint32_t CMD; /*!< SDIO command register, Address offset: 0x0C */
+ __I uint32_t RESPCMD; /*!< SDIO command response register, Address offset: 0x10 */
+ __I uint32_t RESP1; /*!< SDIO response 1 register, Address offset: 0x14 */
+ __I uint32_t RESP2; /*!< SDIO response 2 register, Address offset: 0x18 */
+ __I uint32_t RESP3; /*!< SDIO response 3 register, Address offset: 0x1C */
+ __I uint32_t RESP4; /*!< SDIO response 4 register, Address offset: 0x20 */
+ __IO uint32_t DTIMER; /*!< SDIO data timer register, Address offset: 0x24 */
+ __IO uint32_t DLEN; /*!< SDIO data length register, Address offset: 0x28 */
+ __IO uint32_t DCTRL; /*!< SDIO data control register, Address offset: 0x2C */
+ __I uint32_t DCOUNT; /*!< SDIO data counter register, Address offset: 0x30 */
+ __I uint32_t STA; /*!< SDIO status register, Address offset: 0x34 */
+ __IO uint32_t ICR; /*!< SDIO interrupt clear register, Address offset: 0x38 */
+ __IO uint32_t MASK; /*!< SDIO mask register, Address offset: 0x3C */
+ uint32_t RESERVED0[2]; /*!< Reserved, 0x40-0x44 */
+ __I uint32_t FIFOCNT; /*!< SDIO FIFO counter register, Address offset: 0x48 */
+ uint32_t RESERVED1[13]; /*!< Reserved, 0x4C-0x7C */
+ __IO uint32_t FIFO; /*!< SDIO data FIFO register, Address offset: 0x80 */
+} SDIO_TypeDef;
+
+/**
+ * @brief Serial Peripheral Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t CR1; /*!< SPI control register 1 (not used in I2S mode), Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< SPI control register 2, Address offset: 0x04 */
+ __IO uint32_t SR; /*!< SPI status register, Address offset: 0x08 */
+ __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */
+ __IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
+ __IO uint32_t RXCRCR; /*!< SPI RX CRC register (not used in I2S mode), Address offset: 0x14 */
+ __IO uint32_t TXCRCR; /*!< SPI TX CRC register (not used in I2S mode), Address offset: 0x18 */
+ __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */
+ __IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */
+} SPI_TypeDef;
+
+/**
+ * @brief TIM
+ */
+
+typedef struct
+{
+ __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
+ __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */
+ __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
+ __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
+ __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
+ __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
+ __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
+ __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
+ __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
+ __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */
+ __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
+ __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */
+ __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
+ __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
+ __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
+ __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
+ __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
+ __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
+ __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */
+ __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */
+} TIM_TypeDef;
+
+/**
+ * @brief Universal Synchronous Asynchronous Receiver Transmitter
+ */
+
+typedef struct
+{
+ __IO uint32_t SR; /*!< USART Status register, Address offset: 0x00 */
+ __IO uint32_t DR; /*!< USART Data register, Address offset: 0x04 */
+ __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x08 */
+ __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x0C */
+ __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x10 */
+ __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x14 */
+ __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x18 */
+} USART_TypeDef;
+
+/**
+ * @brief Window WATCHDOG
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
+ __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
+ __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
+} WWDG_TypeDef;
+
+/**
+ * @brief Crypto Processor
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< CRYP control register, Address offset: 0x00 */
+ __IO uint32_t SR; /*!< CRYP status register, Address offset: 0x04 */
+ __IO uint32_t DR; /*!< CRYP data input register, Address offset: 0x08 */
+ __IO uint32_t DOUT; /*!< CRYP data output register, Address offset: 0x0C */
+ __IO uint32_t DMACR; /*!< CRYP DMA control register, Address offset: 0x10 */
+ __IO uint32_t IMSCR; /*!< CRYP interrupt mask set/clear register, Address offset: 0x14 */
+ __IO uint32_t RISR; /*!< CRYP raw interrupt status register, Address offset: 0x18 */
+ __IO uint32_t MISR; /*!< CRYP masked interrupt status register, Address offset: 0x1C */
+ __IO uint32_t K0LR; /*!< CRYP key left register 0, Address offset: 0x20 */
+ __IO uint32_t K0RR; /*!< CRYP key right register 0, Address offset: 0x24 */
+ __IO uint32_t K1LR; /*!< CRYP key left register 1, Address offset: 0x28 */
+ __IO uint32_t K1RR; /*!< CRYP key right register 1, Address offset: 0x2C */
+ __IO uint32_t K2LR; /*!< CRYP key left register 2, Address offset: 0x30 */
+ __IO uint32_t K2RR; /*!< CRYP key right register 2, Address offset: 0x34 */
+ __IO uint32_t K3LR; /*!< CRYP key left register 3, Address offset: 0x38 */
+ __IO uint32_t K3RR; /*!< CRYP key right register 3, Address offset: 0x3C */
+ __IO uint32_t IV0LR; /*!< CRYP initialization vector left-word register 0, Address offset: 0x40 */
+ __IO uint32_t IV0RR; /*!< CRYP initialization vector right-word register 0, Address offset: 0x44 */
+ __IO uint32_t IV1LR; /*!< CRYP initialization vector left-word register 1, Address offset: 0x48 */
+ __IO uint32_t IV1RR; /*!< CRYP initialization vector right-word register 1, Address offset: 0x4C */
+ __IO uint32_t CSGCMCCM0R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 0, Address offset: 0x50 */
+ __IO uint32_t CSGCMCCM1R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 1, Address offset: 0x54 */
+ __IO uint32_t CSGCMCCM2R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 2, Address offset: 0x58 */
+ __IO uint32_t CSGCMCCM3R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 3, Address offset: 0x5C */
+ __IO uint32_t CSGCMCCM4R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 4, Address offset: 0x60 */
+ __IO uint32_t CSGCMCCM5R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 5, Address offset: 0x64 */
+ __IO uint32_t CSGCMCCM6R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 6, Address offset: 0x68 */
+ __IO uint32_t CSGCMCCM7R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 7, Address offset: 0x6C */
+ __IO uint32_t CSGCM0R; /*!< CRYP GCM/GMAC context swap register 0, Address offset: 0x70 */
+ __IO uint32_t CSGCM1R; /*!< CRYP GCM/GMAC context swap register 1, Address offset: 0x74 */
+ __IO uint32_t CSGCM2R; /*!< CRYP GCM/GMAC context swap register 2, Address offset: 0x78 */
+ __IO uint32_t CSGCM3R; /*!< CRYP GCM/GMAC context swap register 3, Address offset: 0x7C */
+ __IO uint32_t CSGCM4R; /*!< CRYP GCM/GMAC context swap register 4, Address offset: 0x80 */
+ __IO uint32_t CSGCM5R; /*!< CRYP GCM/GMAC context swap register 5, Address offset: 0x84 */
+ __IO uint32_t CSGCM6R; /*!< CRYP GCM/GMAC context swap register 6, Address offset: 0x88 */
+ __IO uint32_t CSGCM7R; /*!< CRYP GCM/GMAC context swap register 7, Address offset: 0x8C */
+} CRYP_TypeDef;
+
+/**
+ * @brief HASH
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< HASH control register, Address offset: 0x00 */
+ __IO uint32_t DIN; /*!< HASH data input register, Address offset: 0x04 */
+ __IO uint32_t STR; /*!< HASH start register, Address offset: 0x08 */
+ __IO uint32_t HR[5]; /*!< HASH digest registers, Address offset: 0x0C-0x1C */
+ __IO uint32_t IMR; /*!< HASH interrupt enable register, Address offset: 0x20 */
+ __IO uint32_t SR; /*!< HASH status register, Address offset: 0x24 */
+ uint32_t RESERVED[52]; /*!< Reserved, 0x28-0xF4 */
+ __IO uint32_t CSR[54]; /*!< HASH context swap registers, Address offset: 0x0F8-0x1CC */
+} HASH_TypeDef;
+
+/**
+ * @brief HASH_DIGEST
+ */
+
+typedef struct
+{
+ __IO uint32_t HR[8]; /*!< HASH digest registers, Address offset: 0x310-0x32C */
+} HASH_DIGEST_TypeDef;
+
+/**
+ * @brief RNG
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */
+ __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */
+ __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */
+} RNG_TypeDef;
+
+
+/**
+ * @brief __USB_OTG_Core_register
+ */
+typedef struct
+{
+ __IO uint32_t GOTGCTL; /*!< USB_OTG Control and Status Register 000h */
+ __IO uint32_t GOTGINT; /*!< USB_OTG Interrupt Register 004h */
+ __IO uint32_t GAHBCFG; /*!< Core AHB Configuration Register 008h */
+ __IO uint32_t GUSBCFG; /*!< Core USB Configuration Register 00Ch */
+ __IO uint32_t GRSTCTL; /*!< Core Reset Register 010h */
+ __IO uint32_t GINTSTS; /*!< Core Interrupt Register 014h */
+ __IO uint32_t GINTMSK; /*!< Core Interrupt Mask Register 018h */
+ __IO uint32_t GRXSTSR; /*!< Receive Sts Q Read Register 01Ch */
+ __IO uint32_t GRXSTSP; /*!< Receive Sts Q Read & POP Register 020h */
+ __IO uint32_t GRXFSIZ; /* Receive FIFO Size Register 024h */
+ __IO uint32_t DIEPTXF0_HNPTXFSIZ; /*!< EP0 / Non Periodic Tx FIFO Size Register 028h*/
+ __IO uint32_t HNPTXSTS; /*!< Non Periodic Tx FIFO/Queue Sts reg 02Ch */
+ uint32_t Reserved30[2]; /* Reserved 030h*/
+ __IO uint32_t GCCFG; /* General Purpose IO Register 038h*/
+ __IO uint32_t CID; /* User ID Register 03Ch*/
+ uint32_t Reserved40[48]; /* Reserved 040h-0FFh*/
+ __IO uint32_t HPTXFSIZ; /* Host Periodic Tx FIFO Size Reg 100h*/
+ __IO uint32_t DIEPTXF[0x0F];/* dev Periodic Transmit FIFO */
+}
+USB_OTG_GlobalTypeDef;
+
+
+/**
+ * @brief __device_Registers
+ */
+typedef struct
+{
+ __IO uint32_t DCFG; /* dev Configuration Register 800h*/
+ __IO uint32_t DCTL; /* dev Control Register 804h*/
+ __IO uint32_t DSTS; /* dev Status Register (RO) 808h*/
+ uint32_t Reserved0C; /* Reserved 80Ch*/
+ __IO uint32_t DIEPMSK; /* dev IN Endpoint Mask 810h*/
+ __IO uint32_t DOEPMSK; /* dev OUT Endpoint Mask 814h*/
+ __IO uint32_t DAINT; /* dev All Endpoints Itr Reg 818h*/
+ __IO uint32_t DAINTMSK; /* dev All Endpoints Itr Mask 81Ch*/
+ uint32_t Reserved20; /* Reserved 820h*/
+ uint32_t Reserved9; /* Reserved 824h*/
+ __IO uint32_t DVBUSDIS; /* dev VBUS discharge Register 828h*/
+ __IO uint32_t DVBUSPULSE; /* dev VBUS Pulse Register 82Ch*/
+ __IO uint32_t DTHRCTL; /* dev thr 830h*/
+ __IO uint32_t DIEPEMPMSK; /* dev empty msk 834h*/
+ __IO uint32_t DEACHINT; /* dedicated EP interrupt 838h*/
+ __IO uint32_t DEACHMSK; /* dedicated EP msk 83Ch*/
+ uint32_t Reserved40; /* dedicated EP mask 840h*/
+ __IO uint32_t DINEP1MSK; /* dedicated EP mask 844h*/
+ uint32_t Reserved44[15]; /* Reserved 844-87Ch*/
+ __IO uint32_t DOUTEP1MSK; /* dedicated EP msk 884h*/
+}
+USB_OTG_DeviceTypeDef;
+
+
+/**
+ * @brief __IN_Endpoint-Specific_Register
+ */
+typedef struct
+{
+ __IO uint32_t DIEPCTL; /* dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h*/
+ uint32_t Reserved04; /* Reserved 900h + (ep_num * 20h) + 04h*/
+ __IO uint32_t DIEPINT; /* dev IN Endpoint Itr Reg 900h + (ep_num * 20h) + 08h*/
+ uint32_t Reserved0C; /* Reserved 900h + (ep_num * 20h) + 0Ch*/
+ __IO uint32_t DIEPTSIZ; /* IN Endpoint Txfer Size 900h + (ep_num * 20h) + 10h*/
+ __IO uint32_t DIEPDMA; /* IN Endpoint DMA Address Reg 900h + (ep_num * 20h) + 14h*/
+ __IO uint32_t DTXFSTS;/*IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h*/
+ uint32_t Reserved18; /* Reserved 900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch*/
+}
+USB_OTG_INEndpointTypeDef;
+
+
+/**
+ * @brief __OUT_Endpoint-Specific_Registers
+ */
+typedef struct
+{
+ __IO uint32_t DOEPCTL; /* dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h*/
+ uint32_t Reserved04; /* Reserved B00h + (ep_num * 20h) + 04h*/
+ __IO uint32_t DOEPINT; /* dev OUT Endpoint Itr Reg B00h + (ep_num * 20h) + 08h*/
+ uint32_t Reserved0C; /* Reserved B00h + (ep_num * 20h) + 0Ch*/
+ __IO uint32_t DOEPTSIZ; /* dev OUT Endpoint Txfer Size B00h + (ep_num * 20h) + 10h*/
+ __IO uint32_t DOEPDMA; /* dev OUT Endpoint DMA Address B00h + (ep_num * 20h) + 14h*/
+ uint32_t Reserved18[2]; /* Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch*/
+}
+USB_OTG_OUTEndpointTypeDef;
+
+
+/**
+ * @brief __Host_Mode_Register_Structures
+ */
+typedef struct
+{
+ __IO uint32_t HCFG; /* Host Configuration Register 400h*/
+ __IO uint32_t HFIR; /* Host Frame Interval Register 404h*/
+ __IO uint32_t HFNUM; /* Host Frame Nbr/Frame Remaining 408h*/
+ uint32_t Reserved40C; /* Reserved 40Ch*/
+ __IO uint32_t HPTXSTS; /* Host Periodic Tx FIFO/ Queue Status 410h*/
+ __IO uint32_t HAINT; /* Host All Channels Interrupt Register 414h*/
+ __IO uint32_t HAINTMSK; /* Host All Channels Interrupt Mask 418h*/
+}
+USB_OTG_HostTypeDef;
+
+/**
+ * @brief __Host_Channel_Specific_Registers
+ */
+typedef struct
+{
+ __IO uint32_t HCCHAR;
+ __IO uint32_t HCSPLT;
+ __IO uint32_t HCINT;
+ __IO uint32_t HCINTMSK;
+ __IO uint32_t HCTSIZ;
+ __IO uint32_t HCDMA;
+ uint32_t Reserved[2];
+}
+USB_OTG_HostChannelTypeDef;
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_memory_map
+ * @{
+ */
+#define FLASH_BASE 0x08000000U /*!< FLASH(up to 2 MB) base address in the alias region */
+#define CCMDATARAM_BASE 0x10000000U /*!< CCM(core coupled memory) data RAM(64 KB) base address in the alias region */
+#define SRAM1_BASE 0x20000000U /*!< SRAM1(112 KB) base address in the alias region */
+#define SRAM2_BASE 0x2001C000U /*!< SRAM2(16 KB) base address in the alias region */
+#define SRAM3_BASE 0x20020000U /*!< SRAM3(64 KB) base address in the alias region */
+#define PERIPH_BASE 0x40000000U /*!< Peripheral base address in the alias region */
+#define BKPSRAM_BASE 0x40024000U /*!< Backup SRAM(4 KB) base address in the alias region */
+#define FMC_R_BASE 0xA0000000U /*!< FMC registers base address */
+#define SRAM1_BB_BASE 0x22000000U /*!< SRAM1(112 KB) base address in the bit-band region */
+#define SRAM2_BB_BASE 0x22380000U /*!< SRAM2(16 KB) base address in the bit-band region */
+#define SRAM3_BB_BASE 0x22400000U /*!< SRAM3(64 KB) base address in the bit-band region */
+#define PERIPH_BB_BASE 0x42000000U /*!< Peripheral base address in the bit-band region */
+#define BKPSRAM_BB_BASE 0x42480000U /*!< Backup SRAM(4 KB) base address in the bit-band region */
+#define FLASH_END 0x081FFFFFU /*!< FLASH end address */
+#define CCMDATARAM_END 0x1000FFFFU /*!< CCM data RAM end address */
+
+/* Legacy defines */
+#define SRAM_BASE SRAM1_BASE
+#define SRAM_BB_BASE SRAM1_BB_BASE
+
+
+/*!< Peripheral memory map */
+#define APB1PERIPH_BASE PERIPH_BASE
+#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000U)
+#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000U)
+#define AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000U)
+
+/*!< APB1 peripherals */
+#define TIM2_BASE (APB1PERIPH_BASE + 0x0000U)
+#define TIM3_BASE (APB1PERIPH_BASE + 0x0400U)
+#define TIM4_BASE (APB1PERIPH_BASE + 0x0800U)
+#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00U)
+#define TIM6_BASE (APB1PERIPH_BASE + 0x1000U)
+#define TIM7_BASE (APB1PERIPH_BASE + 0x1400U)
+#define TIM12_BASE (APB1PERIPH_BASE + 0x1800U)
+#define TIM13_BASE (APB1PERIPH_BASE + 0x1C00U)
+#define TIM14_BASE (APB1PERIPH_BASE + 0x2000U)
+#define RTC_BASE (APB1PERIPH_BASE + 0x2800U)
+#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00U)
+#define IWDG_BASE (APB1PERIPH_BASE + 0x3000U)
+#define I2S2ext_BASE (APB1PERIPH_BASE + 0x3400U)
+#define SPI2_BASE (APB1PERIPH_BASE + 0x3800U)
+#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00U)
+#define I2S3ext_BASE (APB1PERIPH_BASE + 0x4000U)
+#define USART2_BASE (APB1PERIPH_BASE + 0x4400U)
+#define USART3_BASE (APB1PERIPH_BASE + 0x4800U)
+#define UART4_BASE (APB1PERIPH_BASE + 0x4C00U)
+#define UART5_BASE (APB1PERIPH_BASE + 0x5000U)
+#define I2C1_BASE (APB1PERIPH_BASE + 0x5400U)
+#define I2C2_BASE (APB1PERIPH_BASE + 0x5800U)
+#define I2C3_BASE (APB1PERIPH_BASE + 0x5C00U)
+#define CAN1_BASE (APB1PERIPH_BASE + 0x6400U)
+#define CAN2_BASE (APB1PERIPH_BASE + 0x6800U)
+#define PWR_BASE (APB1PERIPH_BASE + 0x7000U)
+#define DAC_BASE (APB1PERIPH_BASE + 0x7400U)
+#define UART7_BASE (APB1PERIPH_BASE + 0x7800U)
+#define UART8_BASE (APB1PERIPH_BASE + 0x7C00U)
+
+/*!< APB2 peripherals */
+#define TIM1_BASE (APB2PERIPH_BASE + 0x0000U)
+#define TIM8_BASE (APB2PERIPH_BASE + 0x0400U)
+#define USART1_BASE (APB2PERIPH_BASE + 0x1000U)
+#define USART6_BASE (APB2PERIPH_BASE + 0x1400U)
+#define ADC1_BASE (APB2PERIPH_BASE + 0x2000U)
+#define ADC2_BASE (APB2PERIPH_BASE + 0x2100U)
+#define ADC3_BASE (APB2PERIPH_BASE + 0x2200U)
+#define ADC_BASE (APB2PERIPH_BASE + 0x2300U)
+#define SDIO_BASE (APB2PERIPH_BASE + 0x2C00U)
+#define SPI1_BASE (APB2PERIPH_BASE + 0x3000U)
+#define SPI4_BASE (APB2PERIPH_BASE + 0x3400U)
+#define SYSCFG_BASE (APB2PERIPH_BASE + 0x3800U)
+#define EXTI_BASE (APB2PERIPH_BASE + 0x3C00U)
+#define TIM9_BASE (APB2PERIPH_BASE + 0x4000U)
+#define TIM10_BASE (APB2PERIPH_BASE + 0x4400U)
+#define TIM11_BASE (APB2PERIPH_BASE + 0x4800U)
+#define SPI5_BASE (APB2PERIPH_BASE + 0x5000U)
+#define SPI6_BASE (APB2PERIPH_BASE + 0x5400U)
+#define SAI1_BASE (APB2PERIPH_BASE + 0x5800U)
+#define SAI1_Block_A_BASE (SAI1_BASE + 0x004U)
+#define SAI1_Block_B_BASE (SAI1_BASE + 0x024U)
+
+/*!< AHB1 peripherals */
+#define GPIOA_BASE (AHB1PERIPH_BASE + 0x0000U)
+#define GPIOB_BASE (AHB1PERIPH_BASE + 0x0400U)
+#define GPIOC_BASE (AHB1PERIPH_BASE + 0x0800U)
+#define GPIOD_BASE (AHB1PERIPH_BASE + 0x0C00U)
+#define GPIOE_BASE (AHB1PERIPH_BASE + 0x1000U)
+#define GPIOF_BASE (AHB1PERIPH_BASE + 0x1400U)
+#define GPIOG_BASE (AHB1PERIPH_BASE + 0x1800U)
+#define GPIOH_BASE (AHB1PERIPH_BASE + 0x1C00U)
+#define GPIOI_BASE (AHB1PERIPH_BASE + 0x2000U)
+#define GPIOJ_BASE (AHB1PERIPH_BASE + 0x2400U)
+#define GPIOK_BASE (AHB1PERIPH_BASE + 0x2800U)
+#define CRC_BASE (AHB1PERIPH_BASE + 0x3000U)
+#define RCC_BASE (AHB1PERIPH_BASE + 0x3800U)
+#define FLASH_R_BASE (AHB1PERIPH_BASE + 0x3C00U)
+#define DMA1_BASE (AHB1PERIPH_BASE + 0x6000U)
+#define DMA1_Stream0_BASE (DMA1_BASE + 0x010U)
+#define DMA1_Stream1_BASE (DMA1_BASE + 0x028U)
+#define DMA1_Stream2_BASE (DMA1_BASE + 0x040U)
+#define DMA1_Stream3_BASE (DMA1_BASE + 0x058U)
+#define DMA1_Stream4_BASE (DMA1_BASE + 0x070U)
+#define DMA1_Stream5_BASE (DMA1_BASE + 0x088U)
+#define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0U)
+#define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8U)
+#define DMA2_BASE (AHB1PERIPH_BASE + 0x6400U)
+#define DMA2_Stream0_BASE (DMA2_BASE + 0x010U)
+#define DMA2_Stream1_BASE (DMA2_BASE + 0x028U)
+#define DMA2_Stream2_BASE (DMA2_BASE + 0x040U)
+#define DMA2_Stream3_BASE (DMA2_BASE + 0x058U)
+#define DMA2_Stream4_BASE (DMA2_BASE + 0x070U)
+#define DMA2_Stream5_BASE (DMA2_BASE + 0x088U)
+#define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0U)
+#define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8U)
+#define ETH_BASE (AHB1PERIPH_BASE + 0x8000U)
+#define ETH_MAC_BASE (ETH_BASE)
+#define ETH_MMC_BASE (ETH_BASE + 0x0100U)
+#define ETH_PTP_BASE (ETH_BASE + 0x0700U)
+#define ETH_DMA_BASE (ETH_BASE + 0x1000U)
+#define DMA2D_BASE (AHB1PERIPH_BASE + 0xB000U)
+
+/*!< AHB2 peripherals */
+#define DCMI_BASE (AHB2PERIPH_BASE + 0x50000U)
+#define CRYP_BASE (AHB2PERIPH_BASE + 0x60000U)
+#define HASH_BASE (AHB2PERIPH_BASE + 0x60400U)
+#define HASH_DIGEST_BASE (AHB2PERIPH_BASE + 0x60710U)
+#define RNG_BASE (AHB2PERIPH_BASE + 0x60800U)
+
+/*!< FMC Bankx registers base address */
+#define FMC_Bank1_R_BASE (FMC_R_BASE + 0x0000U)
+#define FMC_Bank1E_R_BASE (FMC_R_BASE + 0x0104U)
+#define FMC_Bank2_3_R_BASE (FMC_R_BASE + 0x0060U)
+#define FMC_Bank4_R_BASE (FMC_R_BASE + 0x00A0U)
+#define FMC_Bank5_6_R_BASE (FMC_R_BASE + 0x0140U)
+
+/* Debug MCU registers base address */
+#define DBGMCU_BASE 0xE0042000U
+
+/*!< USB registers base address */
+#define USB_OTG_HS_PERIPH_BASE 0x40040000U
+#define USB_OTG_FS_PERIPH_BASE 0x50000000U
+
+#define USB_OTG_GLOBAL_BASE 0x000U
+#define USB_OTG_DEVICE_BASE 0x800U
+#define USB_OTG_IN_ENDPOINT_BASE 0x900U
+#define USB_OTG_OUT_ENDPOINT_BASE 0xB00U
+#define USB_OTG_EP_REG_SIZE 0x20U
+#define USB_OTG_HOST_BASE 0x400U
+#define USB_OTG_HOST_PORT_BASE 0x440U
+#define USB_OTG_HOST_CHANNEL_BASE 0x500U
+#define USB_OTG_HOST_CHANNEL_SIZE 0x20U
+#define USB_OTG_PCGCCTL_BASE 0xE00U
+#define USB_OTG_FIFO_BASE 0x1000U
+#define USB_OTG_FIFO_SIZE 0x1000U
+
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_declaration
+ * @{
+ */
+#define TIM2 ((TIM_TypeDef *) TIM2_BASE)
+#define TIM3 ((TIM_TypeDef *) TIM3_BASE)
+#define TIM4 ((TIM_TypeDef *) TIM4_BASE)
+#define TIM5 ((TIM_TypeDef *) TIM5_BASE)
+#define TIM6 ((TIM_TypeDef *) TIM6_BASE)
+#define TIM7 ((TIM_TypeDef *) TIM7_BASE)
+#define TIM12 ((TIM_TypeDef *) TIM12_BASE)
+#define TIM13 ((TIM_TypeDef *) TIM13_BASE)
+#define TIM14 ((TIM_TypeDef *) TIM14_BASE)
+#define RTC ((RTC_TypeDef *) RTC_BASE)
+#define WWDG ((WWDG_TypeDef *) WWDG_BASE)
+#define IWDG ((IWDG_TypeDef *) IWDG_BASE)
+#define I2S2ext ((SPI_TypeDef *) I2S2ext_BASE)
+#define SPI2 ((SPI_TypeDef *) SPI2_BASE)
+#define SPI3 ((SPI_TypeDef *) SPI3_BASE)
+#define I2S3ext ((SPI_TypeDef *) I2S3ext_BASE)
+#define USART2 ((USART_TypeDef *) USART2_BASE)
+#define USART3 ((USART_TypeDef *) USART3_BASE)
+#define UART4 ((USART_TypeDef *) UART4_BASE)
+#define UART5 ((USART_TypeDef *) UART5_BASE)
+#define I2C1 ((I2C_TypeDef *) I2C1_BASE)
+#define I2C2 ((I2C_TypeDef *) I2C2_BASE)
+#define I2C3 ((I2C_TypeDef *) I2C3_BASE)
+#define CAN1 ((CAN_TypeDef *) CAN1_BASE)
+#define CAN2 ((CAN_TypeDef *) CAN2_BASE)
+#define PWR ((PWR_TypeDef *) PWR_BASE)
+#define DAC ((DAC_TypeDef *) DAC_BASE)
+#define UART7 ((USART_TypeDef *) UART7_BASE)
+#define UART8 ((USART_TypeDef *) UART8_BASE)
+#define TIM1 ((TIM_TypeDef *) TIM1_BASE)
+#define TIM8 ((TIM_TypeDef *) TIM8_BASE)
+#define USART1 ((USART_TypeDef *) USART1_BASE)
+#define USART6 ((USART_TypeDef *) USART6_BASE)
+#define ADC ((ADC_Common_TypeDef *) ADC_BASE)
+#define ADC1 ((ADC_TypeDef *) ADC1_BASE)
+#define ADC2 ((ADC_TypeDef *) ADC2_BASE)
+#define ADC3 ((ADC_TypeDef *) ADC3_BASE)
+#define SDIO ((SDIO_TypeDef *) SDIO_BASE)
+#define SPI1 ((SPI_TypeDef *) SPI1_BASE)
+#define SPI4 ((SPI_TypeDef *) SPI4_BASE)
+#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
+#define EXTI ((EXTI_TypeDef *) EXTI_BASE)
+#define TIM9 ((TIM_TypeDef *) TIM9_BASE)
+#define TIM10 ((TIM_TypeDef *) TIM10_BASE)
+#define TIM11 ((TIM_TypeDef *) TIM11_BASE)
+#define SPI5 ((SPI_TypeDef *) SPI5_BASE)
+#define SPI6 ((SPI_TypeDef *) SPI6_BASE)
+#define SAI1 ((SAI_TypeDef *) SAI1_BASE)
+#define SAI1_Block_A ((SAI_Block_TypeDef *)SAI1_Block_A_BASE)
+#define SAI1_Block_B ((SAI_Block_TypeDef *)SAI1_Block_B_BASE)
+
+#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
+#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
+#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
+#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
+#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
+#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
+#define GPIOG ((GPIO_TypeDef *) GPIOG_BASE)
+#define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
+#define GPIOI ((GPIO_TypeDef *) GPIOI_BASE)
+#define GPIOJ ((GPIO_TypeDef *) GPIOJ_BASE)
+#define GPIOK ((GPIO_TypeDef *) GPIOK_BASE)
+#define CRC ((CRC_TypeDef *) CRC_BASE)
+#define RCC ((RCC_TypeDef *) RCC_BASE)
+#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
+#define DMA1 ((DMA_TypeDef *) DMA1_BASE)
+#define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)
+#define DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)
+#define DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)
+#define DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)
+#define DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)
+#define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)
+#define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)
+#define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)
+#define DMA2 ((DMA_TypeDef *) DMA2_BASE)
+#define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)
+#define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
+#define DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)
+#define DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)
+#define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)
+#define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)
+#define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)
+#define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)
+#define ETH ((ETH_TypeDef *) ETH_BASE)
+#define DMA2D ((DMA2D_TypeDef *)DMA2D_BASE)
+#define DCMI ((DCMI_TypeDef *) DCMI_BASE)
+#define CRYP ((CRYP_TypeDef *) CRYP_BASE)
+#define HASH ((HASH_TypeDef *) HASH_BASE)
+#define HASH_DIGEST ((HASH_DIGEST_TypeDef *) HASH_DIGEST_BASE)
+#define RNG ((RNG_TypeDef *) RNG_BASE)
+#define FMC_Bank1 ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE)
+#define FMC_Bank1E ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE)
+#define FMC_Bank2_3 ((FMC_Bank2_3_TypeDef *) FMC_Bank2_3_R_BASE)
+#define FMC_Bank4 ((FMC_Bank4_TypeDef *) FMC_Bank4_R_BASE)
+#define FMC_Bank5_6 ((FMC_Bank5_6_TypeDef *) FMC_Bank5_6_R_BASE)
+
+#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
+
+#define USB_OTG_FS ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE)
+#define USB_OTG_HS ((USB_OTG_GlobalTypeDef *) USB_OTG_HS_PERIPH_BASE)
+
+/**
+ * @}
+ */
+
+/** @addtogroup Exported_constants
+ * @{
+ */
+
+ /** @addtogroup Peripheral_Registers_Bits_Definition
+ * @{
+ */
+
+/******************************************************************************/
+/* Peripheral Registers_Bits_Definition */
+/******************************************************************************/
+
+/******************************************************************************/
+/* */
+/* Analog to Digital Converter */
+/* */
+/******************************************************************************/
+/******************** Bit definition for ADC_SR register ********************/
+#define ADC_SR_AWD 0x00000001U /*!<Analog watchdog flag */
+#define ADC_SR_EOC 0x00000002U /*!<End of conversion */
+#define ADC_SR_JEOC 0x00000004U /*!<Injected channel end of conversion */
+#define ADC_SR_JSTRT 0x00000008U /*!<Injected channel Start flag */
+#define ADC_SR_STRT 0x00000010U /*!<Regular channel Start flag */
+#define ADC_SR_OVR 0x00000020U /*!<Overrun flag */
+
+/******************* Bit definition for ADC_CR1 register ********************/
+#define ADC_CR1_AWDCH 0x0000001FU /*!<AWDCH[4:0] bits (Analog watchdog channel select bits) */
+#define ADC_CR1_AWDCH_0 0x00000001U /*!<Bit 0 */
+#define ADC_CR1_AWDCH_1 0x00000002U /*!<Bit 1 */
+#define ADC_CR1_AWDCH_2 0x00000004U /*!<Bit 2 */
+#define ADC_CR1_AWDCH_3 0x00000008U /*!<Bit 3 */
+#define ADC_CR1_AWDCH_4 0x00000010U /*!<Bit 4 */
+#define ADC_CR1_EOCIE 0x00000020U /*!<Interrupt enable for EOC */
+#define ADC_CR1_AWDIE 0x00000040U /*!<AAnalog Watchdog interrupt enable */
+#define ADC_CR1_JEOCIE 0x00000080U /*!<Interrupt enable for injected channels */
+#define ADC_CR1_SCAN 0x00000100U /*!<Scan mode */
+#define ADC_CR1_AWDSGL 0x00000200U /*!<Enable the watchdog on a single channel in scan mode */
+#define ADC_CR1_JAUTO 0x00000400U /*!<Automatic injected group conversion */
+#define ADC_CR1_DISCEN 0x00000800U /*!<Discontinuous mode on regular channels */
+#define ADC_CR1_JDISCEN 0x00001000U /*!<Discontinuous mode on injected channels */
+#define ADC_CR1_DISCNUM 0x0000E000U /*!<DISCNUM[2:0] bits (Discontinuous mode channel count) */
+#define ADC_CR1_DISCNUM_0 0x00002000U /*!<Bit 0 */
+#define ADC_CR1_DISCNUM_1 0x00004000U /*!<Bit 1 */
+#define ADC_CR1_DISCNUM_2 0x00008000U /*!<Bit 2 */
+#define ADC_CR1_JAWDEN 0x00400000U /*!<Analog watchdog enable on injected channels */
+#define ADC_CR1_AWDEN 0x00800000U /*!<Analog watchdog enable on regular channels */
+#define ADC_CR1_RES 0x03000000U /*!<RES[2:0] bits (Resolution) */
+#define ADC_CR1_RES_0 0x01000000U /*!<Bit 0 */
+#define ADC_CR1_RES_1 0x02000000U /*!<Bit 1 */
+#define ADC_CR1_OVRIE 0x04000000U /*!<overrun interrupt enable */
+
+/******************* Bit definition for ADC_CR2 register ********************/
+#define ADC_CR2_ADON 0x00000001U /*!<A/D Converter ON / OFF */
+#define ADC_CR2_CONT 0x00000002U /*!<Continuous Conversion */
+#define ADC_CR2_DMA 0x00000100U /*!<Direct Memory access mode */
+#define ADC_CR2_DDS 0x00000200U /*!<DMA disable selection (Single ADC) */
+#define ADC_CR2_EOCS 0x00000400U /*!<End of conversion selection */
+#define ADC_CR2_ALIGN 0x00000800U /*!<Data Alignment */
+#define ADC_CR2_JEXTSEL 0x000F0000U /*!<JEXTSEL[3:0] bits (External event select for injected group) */
+#define ADC_CR2_JEXTSEL_0 0x00010000U /*!<Bit 0 */
+#define ADC_CR2_JEXTSEL_1 0x00020000U /*!<Bit 1 */
+#define ADC_CR2_JEXTSEL_2 0x00040000U /*!<Bit 2 */
+#define ADC_CR2_JEXTSEL_3 0x00080000U /*!<Bit 3 */
+#define ADC_CR2_JEXTEN 0x00300000U /*!<JEXTEN[1:0] bits (External Trigger Conversion mode for injected channelsp) */
+#define ADC_CR2_JEXTEN_0 0x00100000U /*!<Bit 0 */
+#define ADC_CR2_JEXTEN_1 0x00200000U /*!<Bit 1 */
+#define ADC_CR2_JSWSTART 0x00400000U /*!<Start Conversion of injected channels */
+#define ADC_CR2_EXTSEL 0x0F000000U /*!<EXTSEL[3:0] bits (External Event Select for regular group) */
+#define ADC_CR2_EXTSEL_0 0x01000000U /*!<Bit 0 */
+#define ADC_CR2_EXTSEL_1 0x02000000U /*!<Bit 1 */
+#define ADC_CR2_EXTSEL_2 0x04000000U /*!<Bit 2 */
+#define ADC_CR2_EXTSEL_3 0x08000000U /*!<Bit 3 */
+#define ADC_CR2_EXTEN 0x30000000U /*!<EXTEN[1:0] bits (External Trigger Conversion mode for regular channelsp) */
+#define ADC_CR2_EXTEN_0 0x10000000U /*!<Bit 0 */
+#define ADC_CR2_EXTEN_1 0x20000000U /*!<Bit 1 */
+#define ADC_CR2_SWSTART 0x40000000U /*!<Start Conversion of regular channels */
+
+/****************** Bit definition for ADC_SMPR1 register *******************/
+#define ADC_SMPR1_SMP10 0x00000007U /*!<SMP10[2:0] bits (Channel 10 Sample time selection) */
+#define ADC_SMPR1_SMP10_0 0x00000001U /*!<Bit 0 */
+#define ADC_SMPR1_SMP10_1 0x00000002U /*!<Bit 1 */
+#define ADC_SMPR1_SMP10_2 0x00000004U /*!<Bit 2 */
+#define ADC_SMPR1_SMP11 0x00000038U /*!<SMP11[2:0] bits (Channel 11 Sample time selection) */
+#define ADC_SMPR1_SMP11_0 0x00000008U /*!<Bit 0 */
+#define ADC_SMPR1_SMP11_1 0x00000010U /*!<Bit 1 */
+#define ADC_SMPR1_SMP11_2 0x00000020U /*!<Bit 2 */
+#define ADC_SMPR1_SMP12 0x000001C0U /*!<SMP12[2:0] bits (Channel 12 Sample time selection) */
+#define ADC_SMPR1_SMP12_0 0x00000040U /*!<Bit 0 */
+#define ADC_SMPR1_SMP12_1 0x00000080U /*!<Bit 1 */
+#define ADC_SMPR1_SMP12_2 0x00000100U /*!<Bit 2 */
+#define ADC_SMPR1_SMP13 0x00000E00U /*!<SMP13[2:0] bits (Channel 13 Sample time selection) */
+#define ADC_SMPR1_SMP13_0 0x00000200U /*!<Bit 0 */
+#define ADC_SMPR1_SMP13_1 0x00000400U /*!<Bit 1 */
+#define ADC_SMPR1_SMP13_2 0x00000800U /*!<Bit 2 */
+#define ADC_SMPR1_SMP14 0x00007000U /*!<SMP14[2:0] bits (Channel 14 Sample time selection) */
+#define ADC_SMPR1_SMP14_0 0x00001000U /*!<Bit 0 */
+#define ADC_SMPR1_SMP14_1 0x00002000U /*!<Bit 1 */
+#define ADC_SMPR1_SMP14_2 0x00004000U /*!<Bit 2 */
+#define ADC_SMPR1_SMP15 0x00038000U /*!<SMP15[2:0] bits (Channel 15 Sample time selection) */
+#define ADC_SMPR1_SMP15_0 0x00008000U /*!<Bit 0 */
+#define ADC_SMPR1_SMP15_1 0x00010000U /*!<Bit 1 */
+#define ADC_SMPR1_SMP15_2 0x00020000U /*!<Bit 2 */
+#define ADC_SMPR1_SMP16 0x001C0000U /*!<SMP16[2:0] bits (Channel 16 Sample time selection) */
+#define ADC_SMPR1_SMP16_0 0x00040000U /*!<Bit 0 */
+#define ADC_SMPR1_SMP16_1 0x00080000U /*!<Bit 1 */
+#define ADC_SMPR1_SMP16_2 0x00100000U /*!<Bit 2 */
+#define ADC_SMPR1_SMP17 0x00E00000U /*!<SMP17[2:0] bits (Channel 17 Sample time selection) */
+#define ADC_SMPR1_SMP17_0 0x00200000U /*!<Bit 0 */
+#define ADC_SMPR1_SMP17_1 0x00400000U /*!<Bit 1 */
+#define ADC_SMPR1_SMP17_2 0x00800000U /*!<Bit 2 */
+#define ADC_SMPR1_SMP18 0x07000000U /*!<SMP18[2:0] bits (Channel 18 Sample time selection) */
+#define ADC_SMPR1_SMP18_0 0x01000000U /*!<Bit 0 */
+#define ADC_SMPR1_SMP18_1 0x02000000U /*!<Bit 1 */
+#define ADC_SMPR1_SMP18_2 0x04000000U /*!<Bit 2 */
+
+/****************** Bit definition for ADC_SMPR2 register *******************/
+#define ADC_SMPR2_SMP0 0x00000007U /*!<SMP0[2:0] bits (Channel 0 Sample time selection) */
+#define ADC_SMPR2_SMP0_0 0x00000001U /*!<Bit 0 */
+#define ADC_SMPR2_SMP0_1 0x00000002U /*!<Bit 1 */
+#define ADC_SMPR2_SMP0_2 0x00000004U /*!<Bit 2 */
+#define ADC_SMPR2_SMP1 0x00000038U /*!<SMP1[2:0] bits (Channel 1 Sample time selection) */
+#define ADC_SMPR2_SMP1_0 0x00000008U /*!<Bit 0 */
+#define ADC_SMPR2_SMP1_1 0x00000010U /*!<Bit 1 */
+#define ADC_SMPR2_SMP1_2 0x00000020U /*!<Bit 2 */
+#define ADC_SMPR2_SMP2 0x000001C0U /*!<SMP2[2:0] bits (Channel 2 Sample time selection) */
+#define ADC_SMPR2_SMP2_0 0x00000040U /*!<Bit 0 */
+#define ADC_SMPR2_SMP2_1 0x00000080U /*!<Bit 1 */
+#define ADC_SMPR2_SMP2_2 0x00000100U /*!<Bit 2 */
+#define ADC_SMPR2_SMP3 0x00000E00U /*!<SMP3[2:0] bits (Channel 3 Sample time selection) */
+#define ADC_SMPR2_SMP3_0 0x00000200U /*!<Bit 0 */
+#define ADC_SMPR2_SMP3_1 0x00000400U /*!<Bit 1 */
+#define ADC_SMPR2_SMP3_2 0x00000800U /*!<Bit 2 */
+#define ADC_SMPR2_SMP4 0x00007000U /*!<SMP4[2:0] bits (Channel 4 Sample time selection) */
+#define ADC_SMPR2_SMP4_0 0x00001000U /*!<Bit 0 */
+#define ADC_SMPR2_SMP4_1 0x00002000U /*!<Bit 1 */
+#define ADC_SMPR2_SMP4_2 0x00004000U /*!<Bit 2 */
+#define ADC_SMPR2_SMP5 0x00038000U /*!<SMP5[2:0] bits (Channel 5 Sample time selection) */
+#define ADC_SMPR2_SMP5_0 0x00008000U /*!<Bit 0 */
+#define ADC_SMPR2_SMP5_1 0x00010000U /*!<Bit 1 */
+#define ADC_SMPR2_SMP5_2 0x00020000U /*!<Bit 2 */
+#define ADC_SMPR2_SMP6 0x001C0000U /*!<SMP6[2:0] bits (Channel 6 Sample time selection) */
+#define ADC_SMPR2_SMP6_0 0x00040000U /*!<Bit 0 */
+#define ADC_SMPR2_SMP6_1 0x00080000U /*!<Bit 1 */
+#define ADC_SMPR2_SMP6_2 0x00100000U /*!<Bit 2 */
+#define ADC_SMPR2_SMP7 0x00E00000U /*!<SMP7[2:0] bits (Channel 7 Sample time selection) */
+#define ADC_SMPR2_SMP7_0 0x00200000U /*!<Bit 0 */
+#define ADC_SMPR2_SMP7_1 0x00400000U /*!<Bit 1 */
+#define ADC_SMPR2_SMP7_2 0x00800000U /*!<Bit 2 */
+#define ADC_SMPR2_SMP8 0x07000000U /*!<SMP8[2:0] bits (Channel 8 Sample time selection) */
+#define ADC_SMPR2_SMP8_0 0x01000000U /*!<Bit 0 */
+#define ADC_SMPR2_SMP8_1 0x02000000U /*!<Bit 1 */
+#define ADC_SMPR2_SMP8_2 0x04000000U /*!<Bit 2 */
+#define ADC_SMPR2_SMP9 0x38000000U /*!<SMP9[2:0] bits (Channel 9 Sample time selection) */
+#define ADC_SMPR2_SMP9_0 0x08000000U /*!<Bit 0 */
+#define ADC_SMPR2_SMP9_1 0x10000000U /*!<Bit 1 */
+#define ADC_SMPR2_SMP9_2 0x20000000U /*!<Bit 2 */
+
+/****************** Bit definition for ADC_JOFR1 register *******************/
+#define ADC_JOFR1_JOFFSET1 0x0FFFU /*!<Data offset for injected channel 1 */
+
+/****************** Bit definition for ADC_JOFR2 register *******************/
+#define ADC_JOFR2_JOFFSET2 0x0FFFU /*!<Data offset for injected channel 2 */
+
+/****************** Bit definition for ADC_JOFR3 register *******************/
+#define ADC_JOFR3_JOFFSET3 0x0FFFU /*!<Data offset for injected channel 3 */
+
+/****************** Bit definition for ADC_JOFR4 register *******************/
+#define ADC_JOFR4_JOFFSET4 0x0FFFU /*!<Data offset for injected channel 4 */
+
+/******************* Bit definition for ADC_HTR register ********************/
+#define ADC_HTR_HT 0x0FFFU /*!<Analog watchdog high threshold */
+
+/******************* Bit definition for ADC_LTR register ********************/
+#define ADC_LTR_LT 0x0FFFU /*!<Analog watchdog low threshold */
+
+/******************* Bit definition for ADC_SQR1 register *******************/
+#define ADC_SQR1_SQ13 0x0000001FU /*!<SQ13[4:0] bits (13th conversion in regular sequence) */
+#define ADC_SQR1_SQ13_0 0x00000001U /*!<Bit 0 */
+#define ADC_SQR1_SQ13_1 0x00000002U /*!<Bit 1 */
+#define ADC_SQR1_SQ13_2 0x00000004U /*!<Bit 2 */
+#define ADC_SQR1_SQ13_3 0x00000008U /*!<Bit 3 */
+#define ADC_SQR1_SQ13_4 0x00000010U /*!<Bit 4 */
+#define ADC_SQR1_SQ14 0x000003E0U /*!<SQ14[4:0] bits (14th conversion in regular sequence) */
+#define ADC_SQR1_SQ14_0 0x00000020U /*!<Bit 0 */
+#define ADC_SQR1_SQ14_1 0x00000040U /*!<Bit 1 */
+#define ADC_SQR1_SQ14_2 0x00000080U /*!<Bit 2 */
+#define ADC_SQR1_SQ14_3 0x00000100U /*!<Bit 3 */
+#define ADC_SQR1_SQ14_4 0x00000200U /*!<Bit 4 */
+#define ADC_SQR1_SQ15 0x00007C00U /*!<SQ15[4:0] bits (15th conversion in regular sequence) */
+#define ADC_SQR1_SQ15_0 0x00000400U /*!<Bit 0 */
+#define ADC_SQR1_SQ15_1 0x00000800U /*!<Bit 1 */
+#define ADC_SQR1_SQ15_2 0x00001000U /*!<Bit 2 */
+#define ADC_SQR1_SQ15_3 0x00002000U /*!<Bit 3 */
+#define ADC_SQR1_SQ15_4 0x00004000U /*!<Bit 4 */
+#define ADC_SQR1_SQ16 0x000F8000U /*!<SQ16[4:0] bits (16th conversion in regular sequence) */
+#define ADC_SQR1_SQ16_0 0x00008000U /*!<Bit 0 */
+#define ADC_SQR1_SQ16_1 0x00010000U /*!<Bit 1 */
+#define ADC_SQR1_SQ16_2 0x00020000U /*!<Bit 2 */
+#define ADC_SQR1_SQ16_3 0x00040000U /*!<Bit 3 */
+#define ADC_SQR1_SQ16_4 0x00080000U /*!<Bit 4 */
+#define ADC_SQR1_L 0x00F00000U /*!<L[3:0] bits (Regular channel sequence length) */
+#define ADC_SQR1_L_0 0x00100000U /*!<Bit 0 */
+#define ADC_SQR1_L_1 0x00200000U /*!<Bit 1 */
+#define ADC_SQR1_L_2 0x00400000U /*!<Bit 2 */
+#define ADC_SQR1_L_3 0x00800000U /*!<Bit 3 */
+
+/******************* Bit definition for ADC_SQR2 register *******************/
+#define ADC_SQR2_SQ7 0x0000001FU /*!<SQ7[4:0] bits (7th conversion in regular sequence) */
+#define ADC_SQR2_SQ7_0 0x00000001U /*!<Bit 0 */
+#define ADC_SQR2_SQ7_1 0x00000002U /*!<Bit 1 */
+#define ADC_SQR2_SQ7_2 0x00000004U /*!<Bit 2 */
+#define ADC_SQR2_SQ7_3 0x00000008U /*!<Bit 3 */
+#define ADC_SQR2_SQ7_4 0x00000010U /*!<Bit 4 */
+#define ADC_SQR2_SQ8 0x000003E0U /*!<SQ8[4:0] bits (8th conversion in regular sequence) */
+#define ADC_SQR2_SQ8_0 0x00000020U /*!<Bit 0 */
+#define ADC_SQR2_SQ8_1 0x00000040U /*!<Bit 1 */
+#define ADC_SQR2_SQ8_2 0x00000080U /*!<Bit 2 */
+#define ADC_SQR2_SQ8_3 0x00000100U /*!<Bit 3 */
+#define ADC_SQR2_SQ8_4 0x00000200U /*!<Bit 4 */
+#define ADC_SQR2_SQ9 0x00007C00U /*!<SQ9[4:0] bits (9th conversion in regular sequence) */
+#define ADC_SQR2_SQ9_0 0x00000400U /*!<Bit 0 */
+#define ADC_SQR2_SQ9_1 0x00000800U /*!<Bit 1 */
+#define ADC_SQR2_SQ9_2 0x00001000U /*!<Bit 2 */
+#define ADC_SQR2_SQ9_3 0x00002000U /*!<Bit 3 */
+#define ADC_SQR2_SQ9_4 0x00004000U /*!<Bit 4 */
+#define ADC_SQR2_SQ10 0x000F8000U /*!<SQ10[4:0] bits (10th conversion in regular sequence) */
+#define ADC_SQR2_SQ10_0 0x00008000U /*!<Bit 0 */
+#define ADC_SQR2_SQ10_1 0x00010000U /*!<Bit 1 */
+#define ADC_SQR2_SQ10_2 0x00020000U /*!<Bit 2 */
+#define ADC_SQR2_SQ10_3 0x00040000U /*!<Bit 3 */
+#define ADC_SQR2_SQ10_4 0x00080000U /*!<Bit 4 */
+#define ADC_SQR2_SQ11 0x01F00000U /*!<SQ11[4:0] bits (11th conversion in regular sequence) */
+#define ADC_SQR2_SQ11_0 0x00100000U /*!<Bit 0 */
+#define ADC_SQR2_SQ11_1 0x00200000U /*!<Bit 1 */
+#define ADC_SQR2_SQ11_2 0x00400000U /*!<Bit 2 */
+#define ADC_SQR2_SQ11_3 0x00800000U /*!<Bit 3 */
+#define ADC_SQR2_SQ11_4 0x01000000U /*!<Bit 4 */
+#define ADC_SQR2_SQ12 0x3E000000U /*!<SQ12[4:0] bits (12th conversion in regular sequence) */
+#define ADC_SQR2_SQ12_0 0x02000000U /*!<Bit 0 */
+#define ADC_SQR2_SQ12_1 0x04000000U /*!<Bit 1 */
+#define ADC_SQR2_SQ12_2 0x08000000U /*!<Bit 2 */
+#define ADC_SQR2_SQ12_3 0x10000000U /*!<Bit 3 */
+#define ADC_SQR2_SQ12_4 0x20000000U /*!<Bit 4 */
+
+/******************* Bit definition for ADC_SQR3 register *******************/
+#define ADC_SQR3_SQ1 0x0000001FU /*!<SQ1[4:0] bits (1st conversion in regular sequence) */
+#define ADC_SQR3_SQ1_0 0x00000001U /*!<Bit 0 */
+#define ADC_SQR3_SQ1_1 0x00000002U /*!<Bit 1 */
+#define ADC_SQR3_SQ1_2 0x00000004U /*!<Bit 2 */
+#define ADC_SQR3_SQ1_3 0x00000008U /*!<Bit 3 */
+#define ADC_SQR3_SQ1_4 0x00000010U /*!<Bit 4 */
+#define ADC_SQR3_SQ2 0x000003E0U /*!<SQ2[4:0] bits (2nd conversion in regular sequence) */
+#define ADC_SQR3_SQ2_0 0x00000020U /*!<Bit 0 */
+#define ADC_SQR3_SQ2_1 0x00000040U /*!<Bit 1 */
+#define ADC_SQR3_SQ2_2 0x00000080U /*!<Bit 2 */
+#define ADC_SQR3_SQ2_3 0x00000100U /*!<Bit 3 */
+#define ADC_SQR3_SQ2_4 0x00000200U /*!<Bit 4 */
+#define ADC_SQR3_SQ3 0x00007C00U /*!<SQ3[4:0] bits (3rd conversion in regular sequence) */
+#define ADC_SQR3_SQ3_0 0x00000400U /*!<Bit 0 */
+#define ADC_SQR3_SQ3_1 0x00000800U /*!<Bit 1 */
+#define ADC_SQR3_SQ3_2 0x00001000U /*!<Bit 2 */
+#define ADC_SQR3_SQ3_3 0x00002000U /*!<Bit 3 */
+#define ADC_SQR3_SQ3_4 0x00004000U /*!<Bit 4 */
+#define ADC_SQR3_SQ4 0x000F8000U /*!<SQ4[4:0] bits (4th conversion in regular sequence) */
+#define ADC_SQR3_SQ4_0 0x00008000U /*!<Bit 0 */
+#define ADC_SQR3_SQ4_1 0x00010000U /*!<Bit 1 */
+#define ADC_SQR3_SQ4_2 0x00020000U /*!<Bit 2 */
+#define ADC_SQR3_SQ4_3 0x00040000U /*!<Bit 3 */
+#define ADC_SQR3_SQ4_4 0x00080000U /*!<Bit 4 */
+#define ADC_SQR3_SQ5 0x01F00000U /*!<SQ5[4:0] bits (5th conversion in regular sequence) */
+#define ADC_SQR3_SQ5_0 0x00100000U /*!<Bit 0 */
+#define ADC_SQR3_SQ5_1 0x00200000U /*!<Bit 1 */
+#define ADC_SQR3_SQ5_2 0x00400000U /*!<Bit 2 */
+#define ADC_SQR3_SQ5_3 0x00800000U /*!<Bit 3 */
+#define ADC_SQR3_SQ5_4 0x01000000U /*!<Bit 4 */
+#define ADC_SQR3_SQ6 0x3E000000U /*!<SQ6[4:0] bits (6th conversion in regular sequence) */
+#define ADC_SQR3_SQ6_0 0x02000000U /*!<Bit 0 */
+#define ADC_SQR3_SQ6_1 0x04000000U /*!<Bit 1 */
+#define ADC_SQR3_SQ6_2 0x08000000U /*!<Bit 2 */
+#define ADC_SQR3_SQ6_3 0x10000000U /*!<Bit 3 */
+#define ADC_SQR3_SQ6_4 0x20000000U /*!<Bit 4 */
+
+/******************* Bit definition for ADC_JSQR register *******************/
+#define ADC_JSQR_JSQ1 0x0000001FU /*!<JSQ1[4:0] bits (1st conversion in injected sequence) */
+#define ADC_JSQR_JSQ1_0 0x00000001U /*!<Bit 0 */
+#define ADC_JSQR_JSQ1_1 0x00000002U /*!<Bit 1 */
+#define ADC_JSQR_JSQ1_2 0x00000004U /*!<Bit 2 */
+#define ADC_JSQR_JSQ1_3 0x00000008U /*!<Bit 3 */
+#define ADC_JSQR_JSQ1_4 0x00000010U /*!<Bit 4 */
+#define ADC_JSQR_JSQ2 0x000003E0U /*!<JSQ2[4:0] bits (2nd conversion in injected sequence) */
+#define ADC_JSQR_JSQ2_0 0x00000020U /*!<Bit 0 */
+#define ADC_JSQR_JSQ2_1 0x00000040U /*!<Bit 1 */
+#define ADC_JSQR_JSQ2_2 0x00000080U /*!<Bit 2 */
+#define ADC_JSQR_JSQ2_3 0x00000100U /*!<Bit 3 */
+#define ADC_JSQR_JSQ2_4 0x00000200U /*!<Bit 4 */
+#define ADC_JSQR_JSQ3 0x00007C00U /*!<JSQ3[4:0] bits (3rd conversion in injected sequence) */
+#define ADC_JSQR_JSQ3_0 0x00000400U /*!<Bit 0 */
+#define ADC_JSQR_JSQ3_1 0x00000800U /*!<Bit 1 */
+#define ADC_JSQR_JSQ3_2 0x00001000U /*!<Bit 2 */
+#define ADC_JSQR_JSQ3_3 0x00002000U /*!<Bit 3 */
+#define ADC_JSQR_JSQ3_4 0x00004000U /*!<Bit 4 */
+#define ADC_JSQR_JSQ4 0x000F8000U /*!<JSQ4[4:0] bits (4th conversion in injected sequence) */
+#define ADC_JSQR_JSQ4_0 0x00008000U /*!<Bit 0 */
+#define ADC_JSQR_JSQ4_1 0x00010000U /*!<Bit 1 */
+#define ADC_JSQR_JSQ4_2 0x00020000U /*!<Bit 2 */
+#define ADC_JSQR_JSQ4_3 0x00040000U /*!<Bit 3 */
+#define ADC_JSQR_JSQ4_4 0x00080000U /*!<Bit 4 */
+#define ADC_JSQR_JL 0x00300000U /*!<JL[1:0] bits (Injected Sequence length) */
+#define ADC_JSQR_JL_0 0x00100000U /*!<Bit 0 */
+#define ADC_JSQR_JL_1 0x00200000U /*!<Bit 1 */
+
+/******************* Bit definition for ADC_JDR1 register *******************/
+#define ADC_JDR1_JDATA 0xFFFFU /*!<Injected data */
+
+/******************* Bit definition for ADC_JDR2 register *******************/
+#define ADC_JDR2_JDATA 0xFFFFU /*!<Injected data */
+
+/******************* Bit definition for ADC_JDR3 register *******************/
+#define ADC_JDR3_JDATA 0xFFFFU /*!<Injected data */
+
+/******************* Bit definition for ADC_JDR4 register *******************/
+#define ADC_JDR4_JDATA 0xFFFFU /*!<Injected data */
+
+/******************** Bit definition for ADC_DR register ********************/
+#define ADC_DR_DATA 0x0000FFFFU /*!<Regular data */
+#define ADC_DR_ADC2DATA 0xFFFF0000U /*!<ADC2 data */
+
+/******************* Bit definition for ADC_CSR register ********************/
+#define ADC_CSR_AWD1 0x00000001U /*!<ADC1 Analog watchdog flag */
+#define ADC_CSR_EOC1 0x00000002U /*!<ADC1 End of conversion */
+#define ADC_CSR_JEOC1 0x00000004U /*!<ADC1 Injected channel end of conversion */
+#define ADC_CSR_JSTRT1 0x00000008U /*!<ADC1 Injected channel Start flag */
+#define ADC_CSR_STRT1 0x00000010U /*!<ADC1 Regular channel Start flag */
+#define ADC_CSR_OVR1 0x00000020U /*!<ADC1 DMA overrun flag */
+#define ADC_CSR_AWD2 0x00000100U /*!<ADC2 Analog watchdog flag */
+#define ADC_CSR_EOC2 0x00000200U /*!<ADC2 End of conversion */
+#define ADC_CSR_JEOC2 0x00000400U /*!<ADC2 Injected channel end of conversion */
+#define ADC_CSR_JSTRT2 0x00000800U /*!<ADC2 Injected channel Start flag */
+#define ADC_CSR_STRT2 0x00001000U /*!<ADC2 Regular channel Start flag */
+#define ADC_CSR_OVR2 0x00002000U /*!<ADC2 DMA overrun flag */
+#define ADC_CSR_AWD3 0x00010000U /*!<ADC3 Analog watchdog flag */
+#define ADC_CSR_EOC3 0x00020000U /*!<ADC3 End of conversion */
+#define ADC_CSR_JEOC3 0x00040000U /*!<ADC3 Injected channel end of conversion */
+#define ADC_CSR_JSTRT3 0x00080000U /*!<ADC3 Injected channel Start flag */
+#define ADC_CSR_STRT3 0x00100000U /*!<ADC3 Regular channel Start flag */
+#define ADC_CSR_OVR3 0x00200000U /*!<ADC3 DMA overrun flag */
+
+/* Legacy defines */
+#define ADC_CSR_DOVR1 ADC_CSR_OVR1
+#define ADC_CSR_DOVR2 ADC_CSR_OVR2
+#define ADC_CSR_DOVR3 ADC_CSR_OVR3
+
+/******************* Bit definition for ADC_CCR register ********************/
+#define ADC_CCR_MULTI 0x0000001FU /*!<MULTI[4:0] bits (Multi-ADC mode selection) */
+#define ADC_CCR_MULTI_0 0x00000001U /*!<Bit 0 */
+#define ADC_CCR_MULTI_1 0x00000002U /*!<Bit 1 */
+#define ADC_CCR_MULTI_2 0x00000004U /*!<Bit 2 */
+#define ADC_CCR_MULTI_3 0x00000008U /*!<Bit 3 */
+#define ADC_CCR_MULTI_4 0x00000010U /*!<Bit 4 */
+#define ADC_CCR_DELAY 0x00000F00U /*!<DELAY[3:0] bits (Delay between 2 sampling phases) */
+#define ADC_CCR_DELAY_0 0x00000100U /*!<Bit 0 */
+#define ADC_CCR_DELAY_1 0x00000200U /*!<Bit 1 */
+#define ADC_CCR_DELAY_2 0x00000400U /*!<Bit 2 */
+#define ADC_CCR_DELAY_3 0x00000800U /*!<Bit 3 */
+#define ADC_CCR_DDS 0x00002000U /*!<DMA disable selection (Multi-ADC mode) */
+#define ADC_CCR_DMA 0x0000C000U /*!<DMA[1:0] bits (Direct Memory Access mode for multimode) */
+#define ADC_CCR_DMA_0 0x00004000U /*!<Bit 0 */
+#define ADC_CCR_DMA_1 0x00008000U /*!<Bit 1 */
+#define ADC_CCR_ADCPRE 0x00030000U /*!<ADCPRE[1:0] bits (ADC prescaler) */
+#define ADC_CCR_ADCPRE_0 0x00010000U /*!<Bit 0 */
+#define ADC_CCR_ADCPRE_1 0x00020000U /*!<Bit 1 */
+#define ADC_CCR_VBATE 0x00400000U /*!<VBAT Enable */
+#define ADC_CCR_TSVREFE 0x00800000U /*!<Temperature Sensor and VREFINT Enable */
+
+/******************* Bit definition for ADC_CDR register ********************/
+#define ADC_CDR_DATA1 0x0000FFFFU /*!<1st data of a pair of regular conversions */
+#define ADC_CDR_DATA2 0xFFFF0000U /*!<2nd data of a pair of regular conversions */
+
+/******************************************************************************/
+/* */
+/* Controller Area Network */
+/* */
+/******************************************************************************/
+/*!<CAN control and status registers */
+/******************* Bit definition for CAN_MCR register ********************/
+#define CAN_MCR_INRQ 0x00000001U /*!<Initialization Request */
+#define CAN_MCR_SLEEP 0x00000002U /*!<Sleep Mode Request */
+#define CAN_MCR_TXFP 0x00000004U /*!<Transmit FIFO Priority */
+#define CAN_MCR_RFLM 0x00000008U /*!<Receive FIFO Locked Mode */
+#define CAN_MCR_NART 0x00000010U /*!<No Automatic Retransmission */
+#define CAN_MCR_AWUM 0x00000020U /*!<Automatic Wakeup Mode */
+#define CAN_MCR_ABOM 0x00000040U /*!<Automatic Bus-Off Management */
+#define CAN_MCR_TTCM 0x00000080U /*!<Time Triggered Communication Mode */
+#define CAN_MCR_RESET 0x00008000U /*!<bxCAN software master reset */
+#define CAN_MCR_DBF 0x00010000U /*!<bxCAN Debug freeze */
+/******************* Bit definition for CAN_MSR register ********************/
+#define CAN_MSR_INAK 0x0001U /*!<Initialization Acknowledge */
+#define CAN_MSR_SLAK 0x0002U /*!<Sleep Acknowledge */
+#define CAN_MSR_ERRI 0x0004U /*!<Error Interrupt */
+#define CAN_MSR_WKUI 0x0008U /*!<Wakeup Interrupt */
+#define CAN_MSR_SLAKI 0x0010U /*!<Sleep Acknowledge Interrupt */
+#define CAN_MSR_TXM 0x0100U /*!<Transmit Mode */
+#define CAN_MSR_RXM 0x0200U /*!<Receive Mode */
+#define CAN_MSR_SAMP 0x0400U /*!<Last Sample Point */
+#define CAN_MSR_RX 0x0800U /*!<CAN Rx Signal */
+
+/******************* Bit definition for CAN_TSR register ********************/
+#define CAN_TSR_RQCP0 0x00000001U /*!<Request Completed Mailbox0 */
+#define CAN_TSR_TXOK0 0x00000002U /*!<Transmission OK of Mailbox0 */
+#define CAN_TSR_ALST0 0x00000004U /*!<Arbitration Lost for Mailbox0 */
+#define CAN_TSR_TERR0 0x00000008U /*!<Transmission Error of Mailbox0 */
+#define CAN_TSR_ABRQ0 0x00000080U /*!<Abort Request for Mailbox0 */
+#define CAN_TSR_RQCP1 0x00000100U /*!<Request Completed Mailbox1 */
+#define CAN_TSR_TXOK1 0x00000200U /*!<Transmission OK of Mailbox1 */
+#define CAN_TSR_ALST1 0x00000400U /*!<Arbitration Lost for Mailbox1 */
+#define CAN_TSR_TERR1 0x00000800U /*!<Transmission Error of Mailbox1 */
+#define CAN_TSR_ABRQ1 0x00008000U /*!<Abort Request for Mailbox 1 */
+#define CAN_TSR_RQCP2 0x00010000U /*!<Request Completed Mailbox2 */
+#define CAN_TSR_TXOK2 0x00020000U /*!<Transmission OK of Mailbox 2 */
+#define CAN_TSR_ALST2 0x00040000U /*!<Arbitration Lost for mailbox 2 */
+#define CAN_TSR_TERR2 0x00080000U /*!<Transmission Error of Mailbox 2 */
+#define CAN_TSR_ABRQ2 0x00800000U /*!<Abort Request for Mailbox 2 */
+#define CAN_TSR_CODE 0x03000000U /*!<Mailbox Code */
+
+#define CAN_TSR_TME 0x1C000000U /*!<TME[2:0] bits */
+#define CAN_TSR_TME0 0x04000000U /*!<Transmit Mailbox 0 Empty */
+#define CAN_TSR_TME1 0x08000000U /*!<Transmit Mailbox 1 Empty */
+#define CAN_TSR_TME2 0x10000000U /*!<Transmit Mailbox 2 Empty */
+
+#define CAN_TSR_LOW 0xE0000000U /*!<LOW[2:0] bits */
+#define CAN_TSR_LOW0 0x20000000U /*!<Lowest Priority Flag for Mailbox 0 */
+#define CAN_TSR_LOW1 0x40000000U /*!<Lowest Priority Flag for Mailbox 1 */
+#define CAN_TSR_LOW2 0x80000000U /*!<Lowest Priority Flag for Mailbox 2 */
+
+/******************* Bit definition for CAN_RF0R register *******************/
+#define CAN_RF0R_FMP0 0x03U /*!<FIFO 0 Message Pending */
+#define CAN_RF0R_FULL0 0x08U /*!<FIFO 0 Full */
+#define CAN_RF0R_FOVR0 0x10U /*!<FIFO 0 Overrun */
+#define CAN_RF0R_RFOM0 0x20U /*!<Release FIFO 0 Output Mailbox */
+
+/******************* Bit definition for CAN_RF1R register *******************/
+#define CAN_RF1R_FMP1 0x03U /*!<FIFO 1 Message Pending */
+#define CAN_RF1R_FULL1 0x08U /*!<FIFO 1 Full */
+#define CAN_RF1R_FOVR1 0x10U /*!<FIFO 1 Overrun */
+#define CAN_RF1R_RFOM1 0x20U /*!<Release FIFO 1 Output Mailbox */
+
+/******************** Bit definition for CAN_IER register *******************/
+#define CAN_IER_TMEIE 0x00000001U /*!<Transmit Mailbox Empty Interrupt Enable */
+#define CAN_IER_FMPIE0 0x00000002U /*!<FIFO Message Pending Interrupt Enable */
+#define CAN_IER_FFIE0 0x00000004U /*!<FIFO Full Interrupt Enable */
+#define CAN_IER_FOVIE0 0x00000008U /*!<FIFO Overrun Interrupt Enable */
+#define CAN_IER_FMPIE1 0x00000010U /*!<FIFO Message Pending Interrupt Enable */
+#define CAN_IER_FFIE1 0x00000020U /*!<FIFO Full Interrupt Enable */
+#define CAN_IER_FOVIE1 0x00000040U /*!<FIFO Overrun Interrupt Enable */
+#define CAN_IER_EWGIE 0x00000100U /*!<Error Warning Interrupt Enable */
+#define CAN_IER_EPVIE 0x00000200U /*!<Error Passive Interrupt Enable */
+#define CAN_IER_BOFIE 0x00000400U /*!<Bus-Off Interrupt Enable */
+#define CAN_IER_LECIE 0x00000800U /*!<Last Error Code Interrupt Enable */
+#define CAN_IER_ERRIE 0x00008000U /*!<Error Interrupt Enable */
+#define CAN_IER_WKUIE 0x00010000U /*!<Wakeup Interrupt Enable */
+#define CAN_IER_SLKIE 0x00020000U /*!<Sleep Interrupt Enable */
+#define CAN_IER_EWGIE 0x00000100U /*!<Error warning interrupt enable */
+#define CAN_IER_EPVIE 0x00000200U /*!<Error passive interrupt enable */
+#define CAN_IER_BOFIE 0x00000400U /*!<Bus-off interrupt enable */
+#define CAN_IER_LECIE 0x00000800U /*!<Last error code interrupt enable */
+#define CAN_IER_ERRIE 0x00008000U /*!<Error interrupt enable */
+
+
+/******************** Bit definition for CAN_ESR register *******************/
+#define CAN_ESR_EWGF 0x00000001U /*!<Error Warning Flag */
+#define CAN_ESR_EPVF 0x00000002U /*!<Error Passive Flag */
+#define CAN_ESR_BOFF 0x00000004U /*!<Bus-Off Flag */
+
+#define CAN_ESR_LEC 0x00000070U /*!<LEC[2:0] bits (Last Error Code) */
+#define CAN_ESR_LEC_0 0x00000010U /*!<Bit 0 */
+#define CAN_ESR_LEC_1 0x00000020U /*!<Bit 1 */
+#define CAN_ESR_LEC_2 0x00000040U /*!<Bit 2 */
+
+#define CAN_ESR_TEC 0x00FF0000U /*!<Least significant byte of the 9-bit Transmit Error Counter */
+#define CAN_ESR_REC 0xFF000000U /*!<Receive Error Counter */
+
+/******************* Bit definition for CAN_BTR register ********************/
+#define CAN_BTR_BRP 0x000003FFU /*!<Baud Rate Prescaler */
+#define CAN_BTR_TS1 0x000F0000U /*!<Time Segment 1 */
+#define CAN_BTR_TS1_0 0x00010000U /*!<Bit 0 */
+#define CAN_BTR_TS1_1 0x00020000U /*!<Bit 1 */
+#define CAN_BTR_TS1_2 0x00040000U /*!<Bit 2 */
+#define CAN_BTR_TS1_3 0x00080000U /*!<Bit 3 */
+#define CAN_BTR_TS2 0x00700000U /*!<Time Segment 2 */
+#define CAN_BTR_TS2_0 0x00100000U /*!<Bit 0 */
+#define CAN_BTR_TS2_1 0x00200000U /*!<Bit 1 */
+#define CAN_BTR_TS2_2 0x00400000U /*!<Bit 2 */
+#define CAN_BTR_SJW 0x03000000U /*!<Resynchronization Jump Width */
+#define CAN_BTR_SJW_0 0x01000000U /*!<Bit 0 */
+#define CAN_BTR_SJW_1 0x02000000U /*!<Bit 1 */
+#define CAN_BTR_LBKM 0x40000000U /*!<Loop Back Mode (Debug) */
+#define CAN_BTR_SILM 0x80000000U /*!<Silent Mode */
+
+
+/*!<Mailbox registers */
+/****************** Bit definition for CAN_TI0R register ********************/
+#define CAN_TI0R_TXRQ 0x00000001U /*!<Transmit Mailbox Request */
+#define CAN_TI0R_RTR 0x00000002U /*!<Remote Transmission Request */
+#define CAN_TI0R_IDE 0x00000004U /*!<Identifier Extension */
+#define CAN_TI0R_EXID 0x001FFFF8U /*!<Extended Identifier */
+#define CAN_TI0R_STID 0xFFE00000U /*!<Standard Identifier or Extended Identifier */
+
+/****************** Bit definition for CAN_TDT0R register *******************/
+#define CAN_TDT0R_DLC 0x0000000FU /*!<Data Length Code */
+#define CAN_TDT0R_TGT 0x00000100U /*!<Transmit Global Time */
+#define CAN_TDT0R_TIME 0xFFFF0000U /*!<Message Time Stamp */
+
+/****************** Bit definition for CAN_TDL0R register *******************/
+#define CAN_TDL0R_DATA0 0x000000FFU /*!<Data byte 0 */
+#define CAN_TDL0R_DATA1 0x0000FF00U /*!<Data byte 1 */
+#define CAN_TDL0R_DATA2 0x00FF0000U /*!<Data byte 2 */
+#define CAN_TDL0R_DATA3 0xFF000000U /*!<Data byte 3 */
+
+/****************** Bit definition for CAN_TDH0R register *******************/
+#define CAN_TDH0R_DATA4 0x000000FFU /*!<Data byte 4 */
+#define CAN_TDH0R_DATA5 0x0000FF00U /*!<Data byte 5 */
+#define CAN_TDH0R_DATA6 0x00FF0000U /*!<Data byte 6 */
+#define CAN_TDH0R_DATA7 0xFF000000U /*!<Data byte 7 */
+
+/******************* Bit definition for CAN_TI1R register *******************/
+#define CAN_TI1R_TXRQ 0x00000001U /*!<Transmit Mailbox Request */
+#define CAN_TI1R_RTR 0x00000002U /*!<Remote Transmission Request */
+#define CAN_TI1R_IDE 0x00000004U /*!<Identifier Extension */
+#define CAN_TI1R_EXID 0x001FFFF8U /*!<Extended Identifier */
+#define CAN_TI1R_STID 0xFFE00000U /*!<Standard Identifier or Extended Identifier */
+
+/******************* Bit definition for CAN_TDT1R register ******************/
+#define CAN_TDT1R_DLC 0x0000000FU /*!<Data Length Code */
+#define CAN_TDT1R_TGT 0x00000100U /*!<Transmit Global Time */
+#define CAN_TDT1R_TIME 0xFFFF0000U /*!<Message Time Stamp */
+
+/******************* Bit definition for CAN_TDL1R register ******************/
+#define CAN_TDL1R_DATA0 0x000000FFU /*!<Data byte 0 */
+#define CAN_TDL1R_DATA1 0x0000FF00U /*!<Data byte 1 */
+#define CAN_TDL1R_DATA2 0x00FF0000U /*!<Data byte 2 */
+#define CAN_TDL1R_DATA3 0xFF000000U /*!<Data byte 3 */
+
+/******************* Bit definition for CAN_TDH1R register ******************/
+#define CAN_TDH1R_DATA4 0x000000FFU /*!<Data byte 4 */
+#define CAN_TDH1R_DATA5 0x0000FF00U /*!<Data byte 5 */
+#define CAN_TDH1R_DATA6 0x00FF0000U /*!<Data byte 6 */
+#define CAN_TDH1R_DATA7 0xFF000000U /*!<Data byte 7 */
+
+/******************* Bit definition for CAN_TI2R register *******************/
+#define CAN_TI2R_TXRQ 0x00000001U /*!<Transmit Mailbox Request */
+#define CAN_TI2R_RTR 0x00000002U /*!<Remote Transmission Request */
+#define CAN_TI2R_IDE 0x00000004U /*!<Identifier Extension */
+#define CAN_TI2R_EXID 0x001FFFF8U /*!<Extended identifier */
+#define CAN_TI2R_STID 0xFFE00000U /*!<Standard Identifier or Extended Identifier */
+
+/******************* Bit definition for CAN_TDT2R register ******************/
+#define CAN_TDT2R_DLC 0x0000000FU /*!<Data Length Code */
+#define CAN_TDT2R_TGT 0x00000100U /*!<Transmit Global Time */
+#define CAN_TDT2R_TIME 0xFFFF0000U /*!<Message Time Stamp */
+
+/******************* Bit definition for CAN_TDL2R register ******************/
+#define CAN_TDL2R_DATA0 0x000000FFU /*!<Data byte 0 */
+#define CAN_TDL2R_DATA1 0x0000FF00U /*!<Data byte 1 */
+#define CAN_TDL2R_DATA2 0x00FF0000U /*!<Data byte 2 */
+#define CAN_TDL2R_DATA3 0xFF000000U /*!<Data byte 3 */
+
+/******************* Bit definition for CAN_TDH2R register ******************/
+#define CAN_TDH2R_DATA4 0x000000FFU /*!<Data byte 4 */
+#define CAN_TDH2R_DATA5 0x0000FF00U /*!<Data byte 5 */
+#define CAN_TDH2R_DATA6 0x00FF0000U /*!<Data byte 6 */
+#define CAN_TDH2R_DATA7 0xFF000000U /*!<Data byte 7 */
+
+/******************* Bit definition for CAN_RI0R register *******************/
+#define CAN_RI0R_RTR 0x00000002U /*!<Remote Transmission Request */
+#define CAN_RI0R_IDE 0x00000004U /*!<Identifier Extension */
+#define CAN_RI0R_EXID 0x001FFFF8U /*!<Extended Identifier */
+#define CAN_RI0R_STID 0xFFE00000U /*!<Standard Identifier or Extended Identifier */
+
+/******************* Bit definition for CAN_RDT0R register ******************/
+#define CAN_RDT0R_DLC 0x0000000FU /*!<Data Length Code */
+#define CAN_RDT0R_FMI 0x0000FF00U /*!<Filter Match Index */
+#define CAN_RDT0R_TIME 0xFFFF0000U /*!<Message Time Stamp */
+
+/******************* Bit definition for CAN_RDL0R register ******************/
+#define CAN_RDL0R_DATA0 0x000000FFU /*!<Data byte 0 */
+#define CAN_RDL0R_DATA1 0x0000FF00U /*!<Data byte 1 */
+#define CAN_RDL0R_DATA2 0x00FF0000U /*!<Data byte 2 */
+#define CAN_RDL0R_DATA3 0xFF000000U /*!<Data byte 3 */
+
+/******************* Bit definition for CAN_RDH0R register ******************/
+#define CAN_RDH0R_DATA4 0x000000FFU /*!<Data byte 4 */
+#define CAN_RDH0R_DATA5 0x0000FF00U /*!<Data byte 5 */
+#define CAN_RDH0R_DATA6 0x00FF0000U /*!<Data byte 6 */
+#define CAN_RDH0R_DATA7 0xFF000000U /*!<Data byte 7 */
+
+/******************* Bit definition for CAN_RI1R register *******************/
+#define CAN_RI1R_RTR 0x00000002U /*!<Remote Transmission Request */
+#define CAN_RI1R_IDE 0x00000004U /*!<Identifier Extension */
+#define CAN_RI1R_EXID 0x001FFFF8U /*!<Extended identifier */
+#define CAN_RI1R_STID 0xFFE00000U /*!<Standard Identifier or Extended Identifier */
+
+/******************* Bit definition for CAN_RDT1R register ******************/
+#define CAN_RDT1R_DLC 0x0000000FU /*!<Data Length Code */
+#define CAN_RDT1R_FMI 0x0000FF00U /*!<Filter Match Index */
+#define CAN_RDT1R_TIME 0xFFFF0000U /*!<Message Time Stamp */
+
+/******************* Bit definition for CAN_RDL1R register ******************/
+#define CAN_RDL1R_DATA0 0x000000FFU /*!<Data byte 0 */
+#define CAN_RDL1R_DATA1 0x0000FF00U /*!<Data byte 1 */
+#define CAN_RDL1R_DATA2 0x00FF0000U /*!<Data byte 2 */
+#define CAN_RDL1R_DATA3 0xFF000000U /*!<Data byte 3 */
+
+/******************* Bit definition for CAN_RDH1R register ******************/
+#define CAN_RDH1R_DATA4 0x000000FFU /*!<Data byte 4 */
+#define CAN_RDH1R_DATA5 0x0000FF00U /*!<Data byte 5 */
+#define CAN_RDH1R_DATA6 0x00FF0000U /*!<Data byte 6 */
+#define CAN_RDH1R_DATA7 0xFF000000U /*!<Data byte 7 */
+
+/*!<CAN filter registers */
+/******************* Bit definition for CAN_FMR register ********************/
+#define CAN_FMR_FINIT 0x01U /*!<Filter Init Mode */
+#define CAN_FMR_CAN2SB 0x00003F00U /*!<CAN2 start bank */
+
+/******************* Bit definition for CAN_FM1R register *******************/
+#define CAN_FM1R_FBM 0x0FFFFFFFU /*!<Filter Mode */
+#define CAN_FM1R_FBM0 0x00000001U /*!<Filter Init Mode bit 0 */
+#define CAN_FM1R_FBM1 0x00000002U /*!<Filter Init Mode bit 1 */
+#define CAN_FM1R_FBM2 0x00000004U /*!<Filter Init Mode bit 2 */
+#define CAN_FM1R_FBM3 0x00000008U /*!<Filter Init Mode bit 3 */
+#define CAN_FM1R_FBM4 0x00000010U /*!<Filter Init Mode bit 4 */
+#define CAN_FM1R_FBM5 0x00000020U /*!<Filter Init Mode bit 5 */
+#define CAN_FM1R_FBM6 0x00000040U /*!<Filter Init Mode bit 6 */
+#define CAN_FM1R_FBM7 0x00000080U /*!<Filter Init Mode bit 7 */
+#define CAN_FM1R_FBM8 0x00000100U /*!<Filter Init Mode bit 8 */
+#define CAN_FM1R_FBM9 0x00000200U /*!<Filter Init Mode bit 9 */
+#define CAN_FM1R_FBM10 0x00000400U /*!<Filter Init Mode bit 10 */
+#define CAN_FM1R_FBM11 0x00000800U /*!<Filter Init Mode bit 11 */
+#define CAN_FM1R_FBM12 0x00001000U /*!<Filter Init Mode bit 12 */
+#define CAN_FM1R_FBM13 0x00002000U /*!<Filter Init Mode bit 13 */
+#define CAN_FM1R_FBM14 0x00004000U /*!<Filter Init Mode bit 14 */
+#define CAN_FM1R_FBM15 0x00008000U /*!<Filter Init Mode bit 15 */
+#define CAN_FM1R_FBM16 0x00010000U /*!<Filter Init Mode bit 16 */
+#define CAN_FM1R_FBM17 0x00020000U /*!<Filter Init Mode bit 17 */
+#define CAN_FM1R_FBM18 0x00040000U /*!<Filter Init Mode bit 18 */
+#define CAN_FM1R_FBM19 0x00080000U /*!<Filter Init Mode bit 19 */
+#define CAN_FM1R_FBM20 0x00100000U /*!<Filter Init Mode bit 20 */
+#define CAN_FM1R_FBM21 0x00200000U /*!<Filter Init Mode bit 21 */
+#define CAN_FM1R_FBM22 0x00400000U /*!<Filter Init Mode bit 22 */
+#define CAN_FM1R_FBM23 0x00800000U /*!<Filter Init Mode bit 23 */
+#define CAN_FM1R_FBM24 0x01000000U /*!<Filter Init Mode bit 24 */
+#define CAN_FM1R_FBM25 0x02000000U /*!<Filter Init Mode bit 25 */
+#define CAN_FM1R_FBM26 0x04000000U /*!<Filter Init Mode bit 26 */
+#define CAN_FM1R_FBM27 0x08000000U /*!<Filter Init Mode bit 27 */
+
+/******************* Bit definition for CAN_FS1R register *******************/
+#define CAN_FS1R_FSC 0x0FFFFFFFU /*!<Filter Scale Configuration */
+#define CAN_FS1R_FSC0 0x00000001U /*!<Filter Scale Configuration bit 0 */
+#define CAN_FS1R_FSC1 0x00000002U /*!<Filter Scale Configuration bit 1 */
+#define CAN_FS1R_FSC2 0x00000004U /*!<Filter Scale Configuration bit 2 */
+#define CAN_FS1R_FSC3 0x00000008U /*!<Filter Scale Configuration bit 3 */
+#define CAN_FS1R_FSC4 0x00000010U /*!<Filter Scale Configuration bit 4 */
+#define CAN_FS1R_FSC5 0x00000020U /*!<Filter Scale Configuration bit 5 */
+#define CAN_FS1R_FSC6 0x00000040U /*!<Filter Scale Configuration bit 6 */
+#define CAN_FS1R_FSC7 0x00000080U /*!<Filter Scale Configuration bit 7 */
+#define CAN_FS1R_FSC8 0x00000100U /*!<Filter Scale Configuration bit 8 */
+#define CAN_FS1R_FSC9 0x00000200U /*!<Filter Scale Configuration bit 9 */
+#define CAN_FS1R_FSC10 0x00000400U /*!<Filter Scale Configuration bit 10 */
+#define CAN_FS1R_FSC11 0x00000800U /*!<Filter Scale Configuration bit 11 */
+#define CAN_FS1R_FSC12 0x00001000U /*!<Filter Scale Configuration bit 12 */
+#define CAN_FS1R_FSC13 0x00002000U /*!<Filter Scale Configuration bit 13 */
+#define CAN_FS1R_FSC14 0x00004000U /*!<Filter Scale Configuration bit 14 */
+#define CAN_FS1R_FSC15 0x00008000U /*!<Filter Scale Configuration bit 15 */
+#define CAN_FS1R_FSC16 0x00010000U /*!<Filter Scale Configuration bit 16 */
+#define CAN_FS1R_FSC17 0x00020000U /*!<Filter Scale Configuration bit 17 */
+#define CAN_FS1R_FSC18 0x00040000U /*!<Filter Scale Configuration bit 18 */
+#define CAN_FS1R_FSC19 0x00080000U /*!<Filter Scale Configuration bit 19 */
+#define CAN_FS1R_FSC20 0x00100000U /*!<Filter Scale Configuration bit 20 */
+#define CAN_FS1R_FSC21 0x00200000U /*!<Filter Scale Configuration bit 21 */
+#define CAN_FS1R_FSC22 0x00400000U /*!<Filter Scale Configuration bit 22 */
+#define CAN_FS1R_FSC23 0x00800000U /*!<Filter Scale Configuration bit 23 */
+#define CAN_FS1R_FSC24 0x01000000U /*!<Filter Scale Configuration bit 24 */
+#define CAN_FS1R_FSC25 0x02000000U /*!<Filter Scale Configuration bit 25 */
+#define CAN_FS1R_FSC26 0x04000000U /*!<Filter Scale Configuration bit 26 */
+#define CAN_FS1R_FSC27 0x08000000U /*!<Filter Scale Configuration bit 27 */
+
+/****************** Bit definition for CAN_FFA1R register *******************/
+#define CAN_FFA1R_FFA 0x0FFFFFFFU /*!<Filter FIFO Assignment */
+#define CAN_FFA1R_FFA0 0x00000001U /*!<Filter FIFO Assignment bit 0 */
+#define CAN_FFA1R_FFA1 0x00000002U /*!<Filter FIFO Assignment bit 1 */
+#define CAN_FFA1R_FFA2 0x00000004U /*!<Filter FIFO Assignment bit 2 */
+#define CAN_FFA1R_FFA3 0x00000008U /*!<Filter FIFO Assignment bit 3 */
+#define CAN_FFA1R_FFA4 0x00000010U /*!<Filter FIFO Assignment bit 4 */
+#define CAN_FFA1R_FFA5 0x00000020U /*!<Filter FIFO Assignment bit 5 */
+#define CAN_FFA1R_FFA6 0x00000040U /*!<Filter FIFO Assignment bit 6 */
+#define CAN_FFA1R_FFA7 0x00000080U /*!<Filter FIFO Assignment bit 7 */
+#define CAN_FFA1R_FFA8 0x00000100U /*!<Filter FIFO Assignment bit 8 */
+#define CAN_FFA1R_FFA9 0x00000200U /*!<Filter FIFO Assignment bit 9 */
+#define CAN_FFA1R_FFA10 0x00000400U /*!<Filter FIFO Assignment bit 10 */
+#define CAN_FFA1R_FFA11 0x00000800U /*!<Filter FIFO Assignment bit 11 */
+#define CAN_FFA1R_FFA12 0x00001000U /*!<Filter FIFO Assignment bit 12 */
+#define CAN_FFA1R_FFA13 0x00002000U /*!<Filter FIFO Assignment bit 13 */
+#define CAN_FFA1R_FFA14 0x00004000U /*!<Filter FIFO Assignment bit 14 */
+#define CAN_FFA1R_FFA15 0x00008000U /*!<Filter FIFO Assignment bit 15 */
+#define CAN_FFA1R_FFA16 0x00010000U /*!<Filter FIFO Assignment bit 16 */
+#define CAN_FFA1R_FFA17 0x00020000U /*!<Filter FIFO Assignment bit 17 */
+#define CAN_FFA1R_FFA18 0x00040000U /*!<Filter FIFO Assignment bit 18 */
+#define CAN_FFA1R_FFA19 0x00080000U /*!<Filter FIFO Assignment bit 19 */
+#define CAN_FFA1R_FFA20 0x00100000U /*!<Filter FIFO Assignment bit 20 */
+#define CAN_FFA1R_FFA21 0x00200000U /*!<Filter FIFO Assignment bit 21 */
+#define CAN_FFA1R_FFA22 0x00400000U /*!<Filter FIFO Assignment bit 22 */
+#define CAN_FFA1R_FFA23 0x00800000U /*!<Filter FIFO Assignment bit 23 */
+#define CAN_FFA1R_FFA24 0x01000000U /*!<Filter FIFO Assignment bit 24 */
+#define CAN_FFA1R_FFA25 0x02000000U /*!<Filter FIFO Assignment bit 25 */
+#define CAN_FFA1R_FFA26 0x04000000U /*!<Filter FIFO Assignment bit 26 */
+#define CAN_FFA1R_FFA27 0x08000000U /*!<Filter FIFO Assignment bit 27 */
+
+/******************* Bit definition for CAN_FA1R register *******************/
+#define CAN_FA1R_FACT 0x0FFFFFFFU /*!<Filter Active */
+#define CAN_FA1R_FACT0 0x00000001U /*!<Filter Active bit 0 */
+#define CAN_FA1R_FACT1 0x00000002U /*!<Filter Active bit 1 */
+#define CAN_FA1R_FACT2 0x00000004U /*!<Filter Active bit 2 */
+#define CAN_FA1R_FACT3 0x00000008U /*!<Filter Active bit 3 */
+#define CAN_FA1R_FACT4 0x00000010U /*!<Filter Active bit 4 */
+#define CAN_FA1R_FACT5 0x00000020U /*!<Filter Active bit 5 */
+#define CAN_FA1R_FACT6 0x00000040U /*!<Filter Active bit 6 */
+#define CAN_FA1R_FACT7 0x00000080U /*!<Filter Active bit 7 */
+#define CAN_FA1R_FACT8 0x00000100U /*!<Filter Active bit 8 */
+#define CAN_FA1R_FACT9 0x00000200U /*!<Filter Active bit 9 */
+#define CAN_FA1R_FACT10 0x00000400U /*!<Filter Active bit 10 */
+#define CAN_FA1R_FACT11 0x00000800U /*!<Filter Active bit 11 */
+#define CAN_FA1R_FACT12 0x00001000U /*!<Filter Active bit 12 */
+#define CAN_FA1R_FACT13 0x00002000U /*!<Filter Active bit 13 */
+#define CAN_FA1R_FACT14 0x00004000U /*!<Filter Active bit 14 */
+#define CAN_FA1R_FACT15 0x00008000U /*!<Filter Active bit 15 */
+#define CAN_FA1R_FACT16 0x00010000U /*!<Filter Active bit 16 */
+#define CAN_FA1R_FACT17 0x00020000U /*!<Filter Active bit 17 */
+#define CAN_FA1R_FACT18 0x00040000U /*!<Filter Active bit 18 */
+#define CAN_FA1R_FACT19 0x00080000U /*!<Filter Active bit 19 */
+#define CAN_FA1R_FACT20 0x00100000U /*!<Filter Active bit 20 */
+#define CAN_FA1R_FACT21 0x00200000U /*!<Filter Active bit 21 */
+#define CAN_FA1R_FACT22 0x00400000U /*!<Filter Active bit 22 */
+#define CAN_FA1R_FACT23 0x00800000U /*!<Filter Active bit 23 */
+#define CAN_FA1R_FACT24 0x01000000U /*!<Filter Active bit 24 */
+#define CAN_FA1R_FACT25 0x02000000U /*!<Filter Active bit 25 */
+#define CAN_FA1R_FACT26 0x04000000U /*!<Filter Active bit 26 */
+#define CAN_FA1R_FACT27 0x08000000U /*!<Filter Active bit 27 */
+
+/******************* Bit definition for CAN_F0R1 register *******************/
+#define CAN_F0R1_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F0R1_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F0R1_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F0R1_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F0R1_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F0R1_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F0R1_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F0R1_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F0R1_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F0R1_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F0R1_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F0R1_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F0R1_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F0R1_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F0R1_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F0R1_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F0R1_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F0R1_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F0R1_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F0R1_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F0R1_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F0R1_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F0R1_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F0R1_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F0R1_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F0R1_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F0R1_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F0R1_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F0R1_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F0R1_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F0R1_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F0R1_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F1R1 register *******************/
+#define CAN_F1R1_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F1R1_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F1R1_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F1R1_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F1R1_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F1R1_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F1R1_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F1R1_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F1R1_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F1R1_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F1R1_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F1R1_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F1R1_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F1R1_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F1R1_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F1R1_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F1R1_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F1R1_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F1R1_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F1R1_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F1R1_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F1R1_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F1R1_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F1R1_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F1R1_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F1R1_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F1R1_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F1R1_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F1R1_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F1R1_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F1R1_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F1R1_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F2R1 register *******************/
+#define CAN_F2R1_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F2R1_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F2R1_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F2R1_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F2R1_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F2R1_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F2R1_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F2R1_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F2R1_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F2R1_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F2R1_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F2R1_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F2R1_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F2R1_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F2R1_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F2R1_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F2R1_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F2R1_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F2R1_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F2R1_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F2R1_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F2R1_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F2R1_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F2R1_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F2R1_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F2R1_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F2R1_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F2R1_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F2R1_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F2R1_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F2R1_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F2R1_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F3R1 register *******************/
+#define CAN_F3R1_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F3R1_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F3R1_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F3R1_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F3R1_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F3R1_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F3R1_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F3R1_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F3R1_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F3R1_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F3R1_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F3R1_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F3R1_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F3R1_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F3R1_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F3R1_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F3R1_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F3R1_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F3R1_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F3R1_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F3R1_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F3R1_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F3R1_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F3R1_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F3R1_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F3R1_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F3R1_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F3R1_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F3R1_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F3R1_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F3R1_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F3R1_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F4R1 register *******************/
+#define CAN_F4R1_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F4R1_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F4R1_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F4R1_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F4R1_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F4R1_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F4R1_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F4R1_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F4R1_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F4R1_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F4R1_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F4R1_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F4R1_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F4R1_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F4R1_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F4R1_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F4R1_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F4R1_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F4R1_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F4R1_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F4R1_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F4R1_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F4R1_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F4R1_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F4R1_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F4R1_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F4R1_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F4R1_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F4R1_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F4R1_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F4R1_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F4R1_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F5R1 register *******************/
+#define CAN_F5R1_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F5R1_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F5R1_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F5R1_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F5R1_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F5R1_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F5R1_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F5R1_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F5R1_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F5R1_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F5R1_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F5R1_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F5R1_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F5R1_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F5R1_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F5R1_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F5R1_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F5R1_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F5R1_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F5R1_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F5R1_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F5R1_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F5R1_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F5R1_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F5R1_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F5R1_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F5R1_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F5R1_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F5R1_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F5R1_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F5R1_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F5R1_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F6R1 register *******************/
+#define CAN_F6R1_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F6R1_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F6R1_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F6R1_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F6R1_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F6R1_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F6R1_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F6R1_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F6R1_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F6R1_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F6R1_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F6R1_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F6R1_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F6R1_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F6R1_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F6R1_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F6R1_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F6R1_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F6R1_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F6R1_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F6R1_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F6R1_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F6R1_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F6R1_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F6R1_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F6R1_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F6R1_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F6R1_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F6R1_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F6R1_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F6R1_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F6R1_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F7R1 register *******************/
+#define CAN_F7R1_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F7R1_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F7R1_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F7R1_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F7R1_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F7R1_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F7R1_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F7R1_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F7R1_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F7R1_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F7R1_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F7R1_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F7R1_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F7R1_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F7R1_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F7R1_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F7R1_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F7R1_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F7R1_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F7R1_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F7R1_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F7R1_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F7R1_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F7R1_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F7R1_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F7R1_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F7R1_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F7R1_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F7R1_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F7R1_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F7R1_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F7R1_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F8R1 register *******************/
+#define CAN_F8R1_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F8R1_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F8R1_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F8R1_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F8R1_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F8R1_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F8R1_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F8R1_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F8R1_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F8R1_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F8R1_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F8R1_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F8R1_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F8R1_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F8R1_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F8R1_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F8R1_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F8R1_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F8R1_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F8R1_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F8R1_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F8R1_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F8R1_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F8R1_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F8R1_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F8R1_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F8R1_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F8R1_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F8R1_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F8R1_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F8R1_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F8R1_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F9R1 register *******************/
+#define CAN_F9R1_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F9R1_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F9R1_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F9R1_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F9R1_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F9R1_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F9R1_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F9R1_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F9R1_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F9R1_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F9R1_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F9R1_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F9R1_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F9R1_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F9R1_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F9R1_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F9R1_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F9R1_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F9R1_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F9R1_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F9R1_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F9R1_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F9R1_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F9R1_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F9R1_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F9R1_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F9R1_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F9R1_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F9R1_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F9R1_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F9R1_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F9R1_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F10R1 register ******************/
+#define CAN_F10R1_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F10R1_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F10R1_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F10R1_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F10R1_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F10R1_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F10R1_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F10R1_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F10R1_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F10R1_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F10R1_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F10R1_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F10R1_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F10R1_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F10R1_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F10R1_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F10R1_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F10R1_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F10R1_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F10R1_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F10R1_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F10R1_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F10R1_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F10R1_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F10R1_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F10R1_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F10R1_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F10R1_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F10R1_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F10R1_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F10R1_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F10R1_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F11R1 register ******************/
+#define CAN_F11R1_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F11R1_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F11R1_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F11R1_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F11R1_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F11R1_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F11R1_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F11R1_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F11R1_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F11R1_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F11R1_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F11R1_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F11R1_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F11R1_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F11R1_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F11R1_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F11R1_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F11R1_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F11R1_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F11R1_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F11R1_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F11R1_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F11R1_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F11R1_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F11R1_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F11R1_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F11R1_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F11R1_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F11R1_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F11R1_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F11R1_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F11R1_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F12R1 register ******************/
+#define CAN_F12R1_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F12R1_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F12R1_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F12R1_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F12R1_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F12R1_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F12R1_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F12R1_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F12R1_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F12R1_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F12R1_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F12R1_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F12R1_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F12R1_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F12R1_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F12R1_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F12R1_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F12R1_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F12R1_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F12R1_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F12R1_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F12R1_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F12R1_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F12R1_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F12R1_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F12R1_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F12R1_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F12R1_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F12R1_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F12R1_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F12R1_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F12R1_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F13R1 register ******************/
+#define CAN_F13R1_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F13R1_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F13R1_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F13R1_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F13R1_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F13R1_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F13R1_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F13R1_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F13R1_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F13R1_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F13R1_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F13R1_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F13R1_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F13R1_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F13R1_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F13R1_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F13R1_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F13R1_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F13R1_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F13R1_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F13R1_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F13R1_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F13R1_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F13R1_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F13R1_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F13R1_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F13R1_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F13R1_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F13R1_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F13R1_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F13R1_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F13R1_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F0R2 register *******************/
+#define CAN_F0R2_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F0R2_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F0R2_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F0R2_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F0R2_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F0R2_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F0R2_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F0R2_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F0R2_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F0R2_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F0R2_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F0R2_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F0R2_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F0R2_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F0R2_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F0R2_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F0R2_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F0R2_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F0R2_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F0R2_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F0R2_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F0R2_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F0R2_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F0R2_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F0R2_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F0R2_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F0R2_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F0R2_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F0R2_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F0R2_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F0R2_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F0R2_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F1R2 register *******************/
+#define CAN_F1R2_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F1R2_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F1R2_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F1R2_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F1R2_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F1R2_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F1R2_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F1R2_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F1R2_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F1R2_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F1R2_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F1R2_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F1R2_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F1R2_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F1R2_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F1R2_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F1R2_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F1R2_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F1R2_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F1R2_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F1R2_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F1R2_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F1R2_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F1R2_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F1R2_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F1R2_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F1R2_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F1R2_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F1R2_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F1R2_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F1R2_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F1R2_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F2R2 register *******************/
+#define CAN_F2R2_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F2R2_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F2R2_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F2R2_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F2R2_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F2R2_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F2R2_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F2R2_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F2R2_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F2R2_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F2R2_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F2R2_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F2R2_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F2R2_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F2R2_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F2R2_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F2R2_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F2R2_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F2R2_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F2R2_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F2R2_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F2R2_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F2R2_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F2R2_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F2R2_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F2R2_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F2R2_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F2R2_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F2R2_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F2R2_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F2R2_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F2R2_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F3R2 register *******************/
+#define CAN_F3R2_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F3R2_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F3R2_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F3R2_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F3R2_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F3R2_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F3R2_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F3R2_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F3R2_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F3R2_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F3R2_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F3R2_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F3R2_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F3R2_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F3R2_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F3R2_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F3R2_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F3R2_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F3R2_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F3R2_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F3R2_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F3R2_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F3R2_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F3R2_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F3R2_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F3R2_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F3R2_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F3R2_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F3R2_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F3R2_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F3R2_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F3R2_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F4R2 register *******************/
+#define CAN_F4R2_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F4R2_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F4R2_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F4R2_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F4R2_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F4R2_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F4R2_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F4R2_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F4R2_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F4R2_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F4R2_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F4R2_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F4R2_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F4R2_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F4R2_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F4R2_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F4R2_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F4R2_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F4R2_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F4R2_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F4R2_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F4R2_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F4R2_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F4R2_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F4R2_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F4R2_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F4R2_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F4R2_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F4R2_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F4R2_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F4R2_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F4R2_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F5R2 register *******************/
+#define CAN_F5R2_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F5R2_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F5R2_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F5R2_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F5R2_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F5R2_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F5R2_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F5R2_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F5R2_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F5R2_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F5R2_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F5R2_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F5R2_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F5R2_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F5R2_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F5R2_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F5R2_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F5R2_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F5R2_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F5R2_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F5R2_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F5R2_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F5R2_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F5R2_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F5R2_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F5R2_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F5R2_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F5R2_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F5R2_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F5R2_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F5R2_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F5R2_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F6R2 register *******************/
+#define CAN_F6R2_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F6R2_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F6R2_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F6R2_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F6R2_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F6R2_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F6R2_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F6R2_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F6R2_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F6R2_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F6R2_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F6R2_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F6R2_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F6R2_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F6R2_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F6R2_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F6R2_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F6R2_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F6R2_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F6R2_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F6R2_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F6R2_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F6R2_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F6R2_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F6R2_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F6R2_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F6R2_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F6R2_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F6R2_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F6R2_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F6R2_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F6R2_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F7R2 register *******************/
+#define CAN_F7R2_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F7R2_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F7R2_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F7R2_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F7R2_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F7R2_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F7R2_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F7R2_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F7R2_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F7R2_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F7R2_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F7R2_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F7R2_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F7R2_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F7R2_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F7R2_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F7R2_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F7R2_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F7R2_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F7R2_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F7R2_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F7R2_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F7R2_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F7R2_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F7R2_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F7R2_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F7R2_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F7R2_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F7R2_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F7R2_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F7R2_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F7R2_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F8R2 register *******************/
+#define CAN_F8R2_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F8R2_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F8R2_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F8R2_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F8R2_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F8R2_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F8R2_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F8R2_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F8R2_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F8R2_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F8R2_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F8R2_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F8R2_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F8R2_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F8R2_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F8R2_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F8R2_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F8R2_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F8R2_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F8R2_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F8R2_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F8R2_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F8R2_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F8R2_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F8R2_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F8R2_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F8R2_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F8R2_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F8R2_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F8R2_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F8R2_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F8R2_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F9R2 register *******************/
+#define CAN_F9R2_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F9R2_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F9R2_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F9R2_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F9R2_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F9R2_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F9R2_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F9R2_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F9R2_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F9R2_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F9R2_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F9R2_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F9R2_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F9R2_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F9R2_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F9R2_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F9R2_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F9R2_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F9R2_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F9R2_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F9R2_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F9R2_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F9R2_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F9R2_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F9R2_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F9R2_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F9R2_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F9R2_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F9R2_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F9R2_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F9R2_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F9R2_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F10R2 register ******************/
+#define CAN_F10R2_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F10R2_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F10R2_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F10R2_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F10R2_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F10R2_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F10R2_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F10R2_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F10R2_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F10R2_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F10R2_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F10R2_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F10R2_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F10R2_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F10R2_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F10R2_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F10R2_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F10R2_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F10R2_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F10R2_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F10R2_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F10R2_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F10R2_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F10R2_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F10R2_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F10R2_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F10R2_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F10R2_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F10R2_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F10R2_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F10R2_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F10R2_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F11R2 register ******************/
+#define CAN_F11R2_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F11R2_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F11R2_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F11R2_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F11R2_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F11R2_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F11R2_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F11R2_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F11R2_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F11R2_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F11R2_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F11R2_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F11R2_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F11R2_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F11R2_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F11R2_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F11R2_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F11R2_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F11R2_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F11R2_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F11R2_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F11R2_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F11R2_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F11R2_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F11R2_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F11R2_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F11R2_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F11R2_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F11R2_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F11R2_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F11R2_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F11R2_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F12R2 register ******************/
+#define CAN_F12R2_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F12R2_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F12R2_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F12R2_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F12R2_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F12R2_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F12R2_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F12R2_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F12R2_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F12R2_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F12R2_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F12R2_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F12R2_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F12R2_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F12R2_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F12R2_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F12R2_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F12R2_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F12R2_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F12R2_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F12R2_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F12R2_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F12R2_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F12R2_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F12R2_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F12R2_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F12R2_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F12R2_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F12R2_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F12R2_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F12R2_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F12R2_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F13R2 register ******************/
+#define CAN_F13R2_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F13R2_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F13R2_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F13R2_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F13R2_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F13R2_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F13R2_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F13R2_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F13R2_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F13R2_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F13R2_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F13R2_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F13R2_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F13R2_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F13R2_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F13R2_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F13R2_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F13R2_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F13R2_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F13R2_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F13R2_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F13R2_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F13R2_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F13R2_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F13R2_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F13R2_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F13R2_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F13R2_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F13R2_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F13R2_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F13R2_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F13R2_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************************************************************************/
+/* */
+/* CRC calculation unit */
+/* */
+/******************************************************************************/
+/******************* Bit definition for CRC_DR register *********************/
+#define CRC_DR_DR 0xFFFFFFFFU /*!< Data register bits */
+
+
+/******************* Bit definition for CRC_IDR register ********************/
+#define CRC_IDR_IDR 0xFFU /*!< General-purpose 8-bit data register bits */
+
+
+/******************** Bit definition for CRC_CR register ********************/
+#define CRC_CR_RESET 0x01U /*!< RESET bit */
+
+/******************************************************************************/
+/* */
+/* Crypto Processor */
+/* */
+/******************************************************************************/
+/******************* Bits definition for CRYP_CR register ********************/
+#define CRYP_CR_ALGODIR 0x00000004U
+
+#define CRYP_CR_ALGOMODE 0x00080038U
+#define CRYP_CR_ALGOMODE_0 0x00000008U
+#define CRYP_CR_ALGOMODE_1 0x00000010U
+#define CRYP_CR_ALGOMODE_2 0x00000020U
+#define CRYP_CR_ALGOMODE_TDES_ECB 0x00000000U
+#define CRYP_CR_ALGOMODE_TDES_CBC 0x00000008U
+#define CRYP_CR_ALGOMODE_DES_ECB 0x00000010U
+#define CRYP_CR_ALGOMODE_DES_CBC 0x00000018U
+#define CRYP_CR_ALGOMODE_AES_ECB 0x00000020U
+#define CRYP_CR_ALGOMODE_AES_CBC 0x00000028U
+#define CRYP_CR_ALGOMODE_AES_CTR 0x00000030U
+#define CRYP_CR_ALGOMODE_AES_KEY 0x00000038U
+
+#define CRYP_CR_DATATYPE 0x000000C0U
+#define CRYP_CR_DATATYPE_0 0x00000040U
+#define CRYP_CR_DATATYPE_1 0x00000080U
+#define CRYP_CR_KEYSIZE 0x00000300U
+#define CRYP_CR_KEYSIZE_0 0x00000100U
+#define CRYP_CR_KEYSIZE_1 0x00000200U
+#define CRYP_CR_FFLUSH 0x00004000U
+#define CRYP_CR_CRYPEN 0x00008000U
+
+#define CRYP_CR_GCM_CCMPH 0x00030000U
+#define CRYP_CR_GCM_CCMPH_0 0x00010000U
+#define CRYP_CR_GCM_CCMPH_1 0x00020000U
+#define CRYP_CR_ALGOMODE_3 0x00080000U
+
+/****************** Bits definition for CRYP_SR register *********************/
+#define CRYP_SR_IFEM 0x00000001U
+#define CRYP_SR_IFNF 0x00000002U
+#define CRYP_SR_OFNE 0x00000004U
+#define CRYP_SR_OFFU 0x00000008U
+#define CRYP_SR_BUSY 0x00000010U
+/****************** Bits definition for CRYP_DMACR register ******************/
+#define CRYP_DMACR_DIEN 0x00000001U
+#define CRYP_DMACR_DOEN 0x00000002U
+/***************** Bits definition for CRYP_IMSCR register ******************/
+#define CRYP_IMSCR_INIM 0x00000001U
+#define CRYP_IMSCR_OUTIM 0x00000002U
+/****************** Bits definition for CRYP_RISR register *******************/
+#define CRYP_RISR_OUTRIS 0x00000001U
+#define CRYP_RISR_INRIS 0x00000002U
+/****************** Bits definition for CRYP_MISR register *******************/
+#define CRYP_MISR_INMIS 0x00000001U
+#define CRYP_MISR_OUTMIS 0x00000002U
+
+/******************************************************************************/
+/* */
+/* Digital to Analog Converter */
+/* */
+/******************************************************************************/
+/******************** Bit definition for DAC_CR register ********************/
+#define DAC_CR_EN1 0x00000001U /*!<DAC channel1 enable */
+#define DAC_CR_BOFF1 0x00000002U /*!<DAC channel1 output buffer disable */
+#define DAC_CR_TEN1 0x00000004U /*!<DAC channel1 Trigger enable */
+
+#define DAC_CR_TSEL1 0x00000038U /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */
+#define DAC_CR_TSEL1_0 0x00000008U /*!<Bit 0 */
+#define DAC_CR_TSEL1_1 0x00000010U /*!<Bit 1 */
+#define DAC_CR_TSEL1_2 0x00000020U /*!<Bit 2 */
+
+#define DAC_CR_WAVE1 0x000000C0U /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
+#define DAC_CR_WAVE1_0 0x00000040U /*!<Bit 0 */
+#define DAC_CR_WAVE1_1 0x00000080U /*!<Bit 1 */
+
+#define DAC_CR_MAMP1 0x00000F00U /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
+#define DAC_CR_MAMP1_0 0x00000100U /*!<Bit 0 */
+#define DAC_CR_MAMP1_1 0x00000200U /*!<Bit 1 */
+#define DAC_CR_MAMP1_2 0x00000400U /*!<Bit 2 */
+#define DAC_CR_MAMP1_3 0x00000800U /*!<Bit 3 */
+
+#define DAC_CR_DMAEN1 0x00001000U /*!<DAC channel1 DMA enable */
+#define DAC_CR_DMAUDRIE1 0x00002000U /*!<DAC channel1 DMA underrun interrupt enable*/
+#define DAC_CR_EN2 0x00010000U /*!<DAC channel2 enable */
+#define DAC_CR_BOFF2 0x00020000U /*!<DAC channel2 output buffer disable */
+#define DAC_CR_TEN2 0x00040000U /*!<DAC channel2 Trigger enable */
+
+#define DAC_CR_TSEL2 0x00380000U /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */
+#define DAC_CR_TSEL2_0 0x00080000U /*!<Bit 0 */
+#define DAC_CR_TSEL2_1 0x00100000U /*!<Bit 1 */
+#define DAC_CR_TSEL2_2 0x00200000U /*!<Bit 2 */
+
+#define DAC_CR_WAVE2 0x00C00000U /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
+#define DAC_CR_WAVE2_0 0x00400000U /*!<Bit 0 */
+#define DAC_CR_WAVE2_1 0x00800000U /*!<Bit 1 */
+
+#define DAC_CR_MAMP2 0x0F000000U /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
+#define DAC_CR_MAMP2_0 0x01000000U /*!<Bit 0 */
+#define DAC_CR_MAMP2_1 0x02000000U /*!<Bit 1 */
+#define DAC_CR_MAMP2_2 0x04000000U /*!<Bit 2 */
+#define DAC_CR_MAMP2_3 0x08000000U /*!<Bit 3 */
+
+#define DAC_CR_DMAEN2 0x10000000U /*!<DAC channel2 DMA enabled */
+#define DAC_CR_DMAUDRIE2 0x20000000U /*!<DAC channel2 DMA underrun interrupt enable*/
+
+/***************** Bit definition for DAC_SWTRIGR register ******************/
+#define DAC_SWTRIGR_SWTRIG1 0x01U /*!<DAC channel1 software trigger */
+#define DAC_SWTRIGR_SWTRIG2 0x02U /*!<DAC channel2 software trigger */
+
+/***************** Bit definition for DAC_DHR12R1 register ******************/
+#define DAC_DHR12R1_DACC1DHR 0x0FFFU /*!<DAC channel1 12-bit Right aligned data */
+
+/***************** Bit definition for DAC_DHR12L1 register ******************/
+#define DAC_DHR12L1_DACC1DHR 0xFFF0U /*!<DAC channel1 12-bit Left aligned data */
+
+/****************** Bit definition for DAC_DHR8R1 register ******************/
+#define DAC_DHR8R1_DACC1DHR 0xFFU /*!<DAC channel1 8-bit Right aligned data */
+
+/***************** Bit definition for DAC_DHR12R2 register ******************/
+#define DAC_DHR12R2_DACC2DHR 0x0FFFU /*!<DAC channel2 12-bit Right aligned data */
+
+/***************** Bit definition for DAC_DHR12L2 register ******************/
+#define DAC_DHR12L2_DACC2DHR 0xFFF0U /*!<DAC channel2 12-bit Left aligned data */
+
+/****************** Bit definition for DAC_DHR8R2 register ******************/
+#define DAC_DHR8R2_DACC2DHR 0xFFU /*!<DAC channel2 8-bit Right aligned data */
+
+/***************** Bit definition for DAC_DHR12RD register ******************/
+#define DAC_DHR12RD_DACC1DHR 0x00000FFFU /*!<DAC channel1 12-bit Right aligned data */
+#define DAC_DHR12RD_DACC2DHR 0x0FFF0000U /*!<DAC channel2 12-bit Right aligned data */
+
+/***************** Bit definition for DAC_DHR12LD register ******************/
+#define DAC_DHR12LD_DACC1DHR 0x0000FFF0U /*!<DAC channel1 12-bit Left aligned data */
+#define DAC_DHR12LD_DACC2DHR 0xFFF00000U /*!<DAC channel2 12-bit Left aligned data */
+
+/****************** Bit definition for DAC_DHR8RD register ******************/
+#define DAC_DHR8RD_DACC1DHR 0x00FFU /*!<DAC channel1 8-bit Right aligned data */
+#define DAC_DHR8RD_DACC2DHR 0xFF00U /*!<DAC channel2 8-bit Right aligned data */
+
+/******************* Bit definition for DAC_DOR1 register *******************/
+#define DAC_DOR1_DACC1DOR 0x0FFFU /*!<DAC channel1 data output */
+
+/******************* Bit definition for DAC_DOR2 register *******************/
+#define DAC_DOR2_DACC2DOR 0x0FFFU /*!<DAC channel2 data output */
+
+/******************** Bit definition for DAC_SR register ********************/
+#define DAC_SR_DMAUDR1 0x00002000U /*!<DAC channel1 DMA underrun flag */
+#define DAC_SR_DMAUDR2 0x20000000U /*!<DAC channel2 DMA underrun flag */
+
+/******************************************************************************/
+/* */
+/* Debug MCU */
+/* */
+/******************************************************************************/
+
+/******************************************************************************/
+/* */
+/* DCMI */
+/* */
+/******************************************************************************/
+/******************** Bits definition for DCMI_CR register ******************/
+#define DCMI_CR_CAPTURE 0x00000001U
+#define DCMI_CR_CM 0x00000002U
+#define DCMI_CR_CROP 0x00000004U
+#define DCMI_CR_JPEG 0x00000008U
+#define DCMI_CR_ESS 0x00000010U
+#define DCMI_CR_PCKPOL 0x00000020U
+#define DCMI_CR_HSPOL 0x00000040U
+#define DCMI_CR_VSPOL 0x00000080U
+#define DCMI_CR_FCRC_0 0x00000100U
+#define DCMI_CR_FCRC_1 0x00000200U
+#define DCMI_CR_EDM_0 0x00000400U
+#define DCMI_CR_EDM_1 0x00000800U
+#define DCMI_CR_CRE 0x00001000U
+#define DCMI_CR_ENABLE 0x00004000U
+
+/******************** Bits definition for DCMI_SR register ******************/
+#define DCMI_SR_HSYNC 0x00000001U
+#define DCMI_SR_VSYNC 0x00000002U
+#define DCMI_SR_FNE 0x00000004U
+
+/******************** Bits definition for DCMI_RIS register *****************/
+#define DCMI_RIS_FRAME_RIS 0x00000001U
+#define DCMI_RIS_OVR_RIS 0x00000002U
+#define DCMI_RIS_ERR_RIS 0x00000004U
+#define DCMI_RIS_VSYNC_RIS 0x00000008U
+#define DCMI_RIS_LINE_RIS 0x00000010U
+/* Legacy defines */
+#define DCMI_RISR_FRAME_RIS DCMI_RIS_FRAME_RIS
+#define DCMI_RISR_OVR_RIS DCMI_RIS_OVR_RIS
+#define DCMI_RISR_ERR_RIS DCMI_RIS_ERR_RIS
+#define DCMI_RISR_VSYNC_RIS DCMI_RIS_VSYNC_RIS
+#define DCMI_RISR_LINE_RIS DCMI_RIS_LINE_RIS
+#define DCMI_RISR_OVF_RIS DCMI_RIS_OVR_RIS
+
+/******************** Bits definition for DCMI_IER register *****************/
+#define DCMI_IER_FRAME_IE 0x00000001U
+#define DCMI_IER_OVR_IE 0x00000002U
+#define DCMI_IER_ERR_IE 0x00000004U
+#define DCMI_IER_VSYNC_IE 0x00000008U
+#define DCMI_IER_LINE_IE 0x00000010U
+/* Legacy defines */
+#define DCMI_IER_OVF_IE DCMI_IER_OVR_IE
+
+/******************** Bits definition for DCMI_MIS register *****************/
+#define DCMI_MIS_FRAME_MIS 0x00000001U
+#define DCMI_MIS_OVR_MIS 0x00000002U
+#define DCMI_MIS_ERR_MIS 0x00000004U
+#define DCMI_MIS_VSYNC_MIS 0x00000008U
+#define DCMI_MIS_LINE_MIS 0x00000010U
+
+/* Legacy defines */
+#define DCMI_MISR_FRAME_MIS DCMI_MIS_FRAME_MIS
+#define DCMI_MISR_OVF_MIS DCMI_MIS_OVR_MIS
+#define DCMI_MISR_ERR_MIS DCMI_MIS_ERR_MIS
+#define DCMI_MISR_VSYNC_MIS DCMI_MIS_VSYNC_MIS
+#define DCMI_MISR_LINE_MIS DCMI_MIS_LINE_MIS
+
+/******************** Bits definition for DCMI_ICR register *****************/
+#define DCMI_ICR_FRAME_ISC 0x00000001U
+#define DCMI_ICR_OVR_ISC 0x00000002U
+#define DCMI_ICR_ERR_ISC 0x00000004U
+#define DCMI_ICR_VSYNC_ISC 0x00000008U
+#define DCMI_ICR_LINE_ISC 0x00000010U
+
+/* Legacy defines */
+#define DCMI_ICR_OVF_ISC DCMI_ICR_OVR_ISC
+
+/******************** Bits definition for DCMI_ESCR register ******************/
+#define DCMI_ESCR_FSC 0x000000FFU
+#define DCMI_ESCR_LSC 0x0000FF00U
+#define DCMI_ESCR_LEC 0x00FF0000U
+#define DCMI_ESCR_FEC 0xFF000000U
+
+/******************** Bits definition for DCMI_ESUR register ******************/
+#define DCMI_ESUR_FSU 0x000000FFU
+#define DCMI_ESUR_LSU 0x0000FF00U
+#define DCMI_ESUR_LEU 0x00FF0000U
+#define DCMI_ESUR_FEU 0xFF000000U
+
+/******************** Bits definition for DCMI_CWSTRT register ******************/
+#define DCMI_CWSTRT_HOFFCNT 0x00003FFFU
+#define DCMI_CWSTRT_VST 0x1FFF0000U
+
+/******************** Bits definition for DCMI_CWSIZE register ******************/
+#define DCMI_CWSIZE_CAPCNT 0x00003FFFU
+#define DCMI_CWSIZE_VLINE 0x3FFF0000U
+
+/******************** Bits definition for DCMI_DR register ******************/
+#define DCMI_DR_BYTE0 0x000000FFU
+#define DCMI_DR_BYTE1 0x0000FF00U
+#define DCMI_DR_BYTE2 0x00FF0000U
+#define DCMI_DR_BYTE3 0xFF000000U
+
+/******************************************************************************/
+/* */
+/* DMA Controller */
+/* */
+/******************************************************************************/
+/******************** Bits definition for DMA_SxCR register *****************/
+#define DMA_SxCR_CHSEL 0x0E000000U
+#define DMA_SxCR_CHSEL_0 0x02000000U
+#define DMA_SxCR_CHSEL_1 0x04000000U
+#define DMA_SxCR_CHSEL_2 0x08000000U
+#define DMA_SxCR_MBURST 0x01800000U
+#define DMA_SxCR_MBURST_0 0x00800000U
+#define DMA_SxCR_MBURST_1 0x01000000U
+#define DMA_SxCR_PBURST 0x00600000U
+#define DMA_SxCR_PBURST_0 0x00200000U
+#define DMA_SxCR_PBURST_1 0x00400000U
+#define DMA_SxCR_CT 0x00080000U
+#define DMA_SxCR_DBM 0x00040000U
+#define DMA_SxCR_PL 0x00030000U
+#define DMA_SxCR_PL_0 0x00010000U
+#define DMA_SxCR_PL_1 0x00020000U
+#define DMA_SxCR_PINCOS 0x00008000U
+#define DMA_SxCR_MSIZE 0x00006000U
+#define DMA_SxCR_MSIZE_0 0x00002000U
+#define DMA_SxCR_MSIZE_1 0x00004000U
+#define DMA_SxCR_PSIZE 0x00001800U
+#define DMA_SxCR_PSIZE_0 0x00000800U
+#define DMA_SxCR_PSIZE_1 0x00001000U
+#define DMA_SxCR_MINC 0x00000400U
+#define DMA_SxCR_PINC 0x00000200U
+#define DMA_SxCR_CIRC 0x00000100U
+#define DMA_SxCR_DIR 0x000000C0U
+#define DMA_SxCR_DIR_0 0x00000040U
+#define DMA_SxCR_DIR_1 0x00000080U
+#define DMA_SxCR_PFCTRL 0x00000020U
+#define DMA_SxCR_TCIE 0x00000010U
+#define DMA_SxCR_HTIE 0x00000008U
+#define DMA_SxCR_TEIE 0x00000004U
+#define DMA_SxCR_DMEIE 0x00000002U
+#define DMA_SxCR_EN 0x00000001U
+
+/* Legacy defines */
+#define DMA_SxCR_ACK 0x00100000U
+
+/******************** Bits definition for DMA_SxCNDTR register **************/
+#define DMA_SxNDT 0x0000FFFFU
+#define DMA_SxNDT_0 0x00000001U
+#define DMA_SxNDT_1 0x00000002U
+#define DMA_SxNDT_2 0x00000004U
+#define DMA_SxNDT_3 0x00000008U
+#define DMA_SxNDT_4 0x00000010U
+#define DMA_SxNDT_5 0x00000020U
+#define DMA_SxNDT_6 0x00000040U
+#define DMA_SxNDT_7 0x00000080U
+#define DMA_SxNDT_8 0x00000100U
+#define DMA_SxNDT_9 0x00000200U
+#define DMA_SxNDT_10 0x00000400U
+#define DMA_SxNDT_11 0x00000800U
+#define DMA_SxNDT_12 0x00001000U
+#define DMA_SxNDT_13 0x00002000U
+#define DMA_SxNDT_14 0x00004000U
+#define DMA_SxNDT_15 0x00008000U
+
+/******************** Bits definition for DMA_SxFCR register ****************/
+#define DMA_SxFCR_FEIE 0x00000080U
+#define DMA_SxFCR_FS 0x00000038U
+#define DMA_SxFCR_FS_0 0x00000008U
+#define DMA_SxFCR_FS_1 0x00000010U
+#define DMA_SxFCR_FS_2 0x00000020U
+#define DMA_SxFCR_DMDIS 0x00000004U
+#define DMA_SxFCR_FTH 0x00000003U
+#define DMA_SxFCR_FTH_0 0x00000001U
+#define DMA_SxFCR_FTH_1 0x00000002U
+
+/******************** Bits definition for DMA_LISR register *****************/
+#define DMA_LISR_TCIF3 0x08000000U
+#define DMA_LISR_HTIF3 0x04000000U
+#define DMA_LISR_TEIF3 0x02000000U
+#define DMA_LISR_DMEIF3 0x01000000U
+#define DMA_LISR_FEIF3 0x00400000U
+#define DMA_LISR_TCIF2 0x00200000U
+#define DMA_LISR_HTIF2 0x00100000U
+#define DMA_LISR_TEIF2 0x00080000U
+#define DMA_LISR_DMEIF2 0x00040000U
+#define DMA_LISR_FEIF2 0x00010000U
+#define DMA_LISR_TCIF1 0x00000800U
+#define DMA_LISR_HTIF1 0x00000400U
+#define DMA_LISR_TEIF1 0x00000200U
+#define DMA_LISR_DMEIF1 0x00000100U
+#define DMA_LISR_FEIF1 0x00000040U
+#define DMA_LISR_TCIF0 0x00000020U
+#define DMA_LISR_HTIF0 0x00000010U
+#define DMA_LISR_TEIF0 0x00000008U
+#define DMA_LISR_DMEIF0 0x00000004U
+#define DMA_LISR_FEIF0 0x00000001U
+
+/******************** Bits definition for DMA_HISR register *****************/
+#define DMA_HISR_TCIF7 0x08000000U
+#define DMA_HISR_HTIF7 0x04000000U
+#define DMA_HISR_TEIF7 0x02000000U
+#define DMA_HISR_DMEIF7 0x01000000U
+#define DMA_HISR_FEIF7 0x00400000U
+#define DMA_HISR_TCIF6 0x00200000U
+#define DMA_HISR_HTIF6 0x00100000U
+#define DMA_HISR_TEIF6 0x00080000U
+#define DMA_HISR_DMEIF6 0x00040000U
+#define DMA_HISR_FEIF6 0x00010000U
+#define DMA_HISR_TCIF5 0x00000800U
+#define DMA_HISR_HTIF5 0x00000400U
+#define DMA_HISR_TEIF5 0x00000200U
+#define DMA_HISR_DMEIF5 0x00000100U
+#define DMA_HISR_FEIF5 0x00000040U
+#define DMA_HISR_TCIF4 0x00000020U
+#define DMA_HISR_HTIF4 0x00000010U
+#define DMA_HISR_TEIF4 0x00000008U
+#define DMA_HISR_DMEIF4 0x00000004U
+#define DMA_HISR_FEIF4 0x00000001U
+
+/******************** Bits definition for DMA_LIFCR register ****************/
+#define DMA_LIFCR_CTCIF3 0x08000000U
+#define DMA_LIFCR_CHTIF3 0x04000000U
+#define DMA_LIFCR_CTEIF3 0x02000000U
+#define DMA_LIFCR_CDMEIF3 0x01000000U
+#define DMA_LIFCR_CFEIF3 0x00400000U
+#define DMA_LIFCR_CTCIF2 0x00200000U
+#define DMA_LIFCR_CHTIF2 0x00100000U
+#define DMA_LIFCR_CTEIF2 0x00080000U
+#define DMA_LIFCR_CDMEIF2 0x00040000U
+#define DMA_LIFCR_CFEIF2 0x00010000U
+#define DMA_LIFCR_CTCIF1 0x00000800U
+#define DMA_LIFCR_CHTIF1 0x00000400U
+#define DMA_LIFCR_CTEIF1 0x00000200U
+#define DMA_LIFCR_CDMEIF1 0x00000100U
+#define DMA_LIFCR_CFEIF1 0x00000040U
+#define DMA_LIFCR_CTCIF0 0x00000020U
+#define DMA_LIFCR_CHTIF0 0x00000010U
+#define DMA_LIFCR_CTEIF0 0x00000008U
+#define DMA_LIFCR_CDMEIF0 0x00000004U
+#define DMA_LIFCR_CFEIF0 0x00000001U
+
+/******************** Bits definition for DMA_HIFCR register ****************/
+#define DMA_HIFCR_CTCIF7 0x08000000U
+#define DMA_HIFCR_CHTIF7 0x04000000U
+#define DMA_HIFCR_CTEIF7 0x02000000U
+#define DMA_HIFCR_CDMEIF7 0x01000000U
+#define DMA_HIFCR_CFEIF7 0x00400000U
+#define DMA_HIFCR_CTCIF6 0x00200000U
+#define DMA_HIFCR_CHTIF6 0x00100000U
+#define DMA_HIFCR_CTEIF6 0x00080000U
+#define DMA_HIFCR_CDMEIF6 0x00040000U
+#define DMA_HIFCR_CFEIF6 0x00010000U
+#define DMA_HIFCR_CTCIF5 0x00000800U
+#define DMA_HIFCR_CHTIF5 0x00000400U
+#define DMA_HIFCR_CTEIF5 0x00000200U
+#define DMA_HIFCR_CDMEIF5 0x00000100U
+#define DMA_HIFCR_CFEIF5 0x00000040U
+#define DMA_HIFCR_CTCIF4 0x00000020U
+#define DMA_HIFCR_CHTIF4 0x00000010U
+#define DMA_HIFCR_CTEIF4 0x00000008U
+#define DMA_HIFCR_CDMEIF4 0x00000004U
+#define DMA_HIFCR_CFEIF4 0x00000001U
+
+
+/******************************************************************************/
+/* */
+/* AHB Master DMA2D Controller (DMA2D) */
+/* */
+/******************************************************************************/
+
+/******************** Bit definition for DMA2D_CR register ******************/
+
+#define DMA2D_CR_START 0x00000001U /*!< Start transfer */
+#define DMA2D_CR_SUSP 0x00000002U /*!< Suspend transfer */
+#define DMA2D_CR_ABORT 0x00000004U /*!< Abort transfer */
+#define DMA2D_CR_TEIE 0x00000100U /*!< Transfer Error Interrupt Enable */
+#define DMA2D_CR_TCIE 0x00000200U /*!< Transfer Complete Interrupt Enable */
+#define DMA2D_CR_TWIE 0x00000400U /*!< Transfer Watermark Interrupt Enable */
+#define DMA2D_CR_CAEIE 0x00000800U /*!< CLUT Access Error Interrupt Enable */
+#define DMA2D_CR_CTCIE 0x00001000U /*!< CLUT Transfer Complete Interrupt Enable */
+#define DMA2D_CR_CEIE 0x00002000U /*!< Configuration Error Interrupt Enable */
+#define DMA2D_CR_MODE 0x00030000U /*!< DMA2D Mode[1:0] */
+#define DMA2D_CR_MODE_0 0x00010000U /*!< DMA2D Mode bit 0 */
+#define DMA2D_CR_MODE_1 0x00020000U /*!< DMA2D Mode bit 1 */
+
+/******************** Bit definition for DMA2D_ISR register *****************/
+
+#define DMA2D_ISR_TEIF 0x00000001U /*!< Transfer Error Interrupt Flag */
+#define DMA2D_ISR_TCIF 0x00000002U /*!< Transfer Complete Interrupt Flag */
+#define DMA2D_ISR_TWIF 0x00000004U /*!< Transfer Watermark Interrupt Flag */
+#define DMA2D_ISR_CAEIF 0x00000008U /*!< CLUT Access Error Interrupt Flag */
+#define DMA2D_ISR_CTCIF 0x00000010U /*!< CLUT Transfer Complete Interrupt Flag */
+#define DMA2D_ISR_CEIF 0x00000020U /*!< Configuration Error Interrupt Flag */
+
+/******************** Bit definition for DMA2D_IFCR register ****************/
+
+#define DMA2D_IFCR_CTEIF 0x00000001U /*!< Clears Transfer Error Interrupt Flag */
+#define DMA2D_IFCR_CTCIF 0x00000002U /*!< Clears Transfer Complete Interrupt Flag */
+#define DMA2D_IFCR_CTWIF 0x00000004U /*!< Clears Transfer Watermark Interrupt Flag */
+#define DMA2D_IFCR_CAECIF 0x00000008U /*!< Clears CLUT Access Error Interrupt Flag */
+#define DMA2D_IFCR_CCTCIF 0x00000010U /*!< Clears CLUT Transfer Complete Interrupt Flag */
+#define DMA2D_IFCR_CCEIF 0x00000020U /*!< Clears Configuration Error Interrupt Flag */
+
+/* Legacy defines */
+#define DMA2D_IFSR_CTEIF DMA2D_IFCR_CTEIF /*!< Clears Transfer Error Interrupt Flag */
+#define DMA2D_IFSR_CTCIF DMA2D_IFCR_CTCIF /*!< Clears Transfer Complete Interrupt Flag */
+#define DMA2D_IFSR_CTWIF DMA2D_IFCR_CTWIF /*!< Clears Transfer Watermark Interrupt Flag */
+#define DMA2D_IFSR_CCAEIF DMA2D_IFCR_CAECIF /*!< Clears CLUT Access Error Interrupt Flag */
+#define DMA2D_IFSR_CCTCIF DMA2D_IFCR_CCTCIF /*!< Clears CLUT Transfer Complete Interrupt Flag */
+#define DMA2D_IFSR_CCEIF DMA2D_IFCR_CCEIF /*!< Clears Configuration Error Interrupt Flag */
+
+/******************** Bit definition for DMA2D_FGMAR register ***************/
+
+#define DMA2D_FGMAR_MA 0xFFFFFFFFU /*!< Memory Address */
+
+/******************** Bit definition for DMA2D_FGOR register ****************/
+
+#define DMA2D_FGOR_LO 0x00003FFFU /*!< Line Offset */
+
+/******************** Bit definition for DMA2D_BGMAR register ***************/
+
+#define DMA2D_BGMAR_MA 0xFFFFFFFFU /*!< Memory Address */
+
+/******************** Bit definition for DMA2D_BGOR register ****************/
+
+#define DMA2D_BGOR_LO 0x00003FFFU /*!< Line Offset */
+
+/******************** Bit definition for DMA2D_FGPFCCR register *************/
+
+#define DMA2D_FGPFCCR_CM 0x0000000FU /*!< Input color mode CM[3:0] */
+#define DMA2D_FGPFCCR_CM_0 0x00000001U /*!< Input color mode CM bit 0 */
+#define DMA2D_FGPFCCR_CM_1 0x00000002U /*!< Input color mode CM bit 1 */
+#define DMA2D_FGPFCCR_CM_2 0x00000004U /*!< Input color mode CM bit 2 */
+#define DMA2D_FGPFCCR_CM_3 0x00000008U /*!< Input color mode CM bit 3 */
+#define DMA2D_FGPFCCR_CCM 0x00000010U /*!< CLUT Color mode */
+#define DMA2D_FGPFCCR_START 0x00000020U /*!< Start */
+#define DMA2D_FGPFCCR_CS 0x0000FF00U /*!< CLUT size */
+#define DMA2D_FGPFCCR_AM 0x00030000U /*!< Alpha mode AM[1:0] */
+#define DMA2D_FGPFCCR_AM_0 0x00010000U /*!< Alpha mode AM bit 0 */
+#define DMA2D_FGPFCCR_AM_1 0x00020000U /*!< Alpha mode AM bit 1 */
+#define DMA2D_FGPFCCR_ALPHA 0xFF000000U /*!< Alpha value */
+
+/******************** Bit definition for DMA2D_FGCOLR register **************/
+
+#define DMA2D_FGCOLR_BLUE 0x000000FFU /*!< Blue Value */
+#define DMA2D_FGCOLR_GREEN 0x0000FF00U /*!< Green Value */
+#define DMA2D_FGCOLR_RED 0x00FF0000U /*!< Red Value */
+
+/******************** Bit definition for DMA2D_BGPFCCR register *************/
+
+#define DMA2D_BGPFCCR_CM 0x0000000FU /*!< Input color mode CM[3:0] */
+#define DMA2D_BGPFCCR_CM_0 0x00000001U /*!< Input color mode CM bit 0 */
+#define DMA2D_BGPFCCR_CM_1 0x00000002U /*!< Input color mode CM bit 1 */
+#define DMA2D_BGPFCCR_CM_2 0x00000004U /*!< Input color mode CM bit 2 */
+#define DMA2D_FGPFCCR_CM_3 0x00000008U /*!< Input color mode CM bit 3 */
+#define DMA2D_BGPFCCR_CCM 0x00000010U /*!< CLUT Color mode */
+#define DMA2D_BGPFCCR_START 0x00000020U /*!< Start */
+#define DMA2D_BGPFCCR_CS 0x0000FF00U /*!< CLUT size */
+#define DMA2D_BGPFCCR_AM 0x00030000U /*!< Alpha mode AM[1:0] */
+#define DMA2D_BGPFCCR_AM_0 0x00010000U /*!< Alpha mode AM bit 0 */
+#define DMA2D_BGPFCCR_AM_1 0x00020000U /*!< Alpha mode AM bit 1 */
+#define DMA2D_BGPFCCR_ALPHA 0xFF000000U /*!< background Input Alpha value */
+
+/******************** Bit definition for DMA2D_BGCOLR register **************/
+
+#define DMA2D_BGCOLR_BLUE 0x000000FFU /*!< Blue Value */
+#define DMA2D_BGCOLR_GREEN 0x0000FF00U /*!< Green Value */
+#define DMA2D_BGCOLR_RED 0x00FF0000U /*!< Red Value */
+
+/******************** Bit definition for DMA2D_FGCMAR register **************/
+
+#define DMA2D_FGCMAR_MA 0xFFFFFFFFU /*!< Memory Address */
+
+/******************** Bit definition for DMA2D_BGCMAR register **************/
+
+#define DMA2D_BGCMAR_MA 0xFFFFFFFFU /*!< Memory Address */
+
+/******************** Bit definition for DMA2D_OPFCCR register **************/
+
+#define DMA2D_OPFCCR_CM 0x00000007U /*!< Color mode CM[2:0] */
+#define DMA2D_OPFCCR_CM_0 0x00000001U /*!< Color mode CM bit 0 */
+#define DMA2D_OPFCCR_CM_1 0x00000002U /*!< Color mode CM bit 1 */
+#define DMA2D_OPFCCR_CM_2 0x00000004U /*!< Color mode CM bit 2 */
+
+/******************** Bit definition for DMA2D_OCOLR register ***************/
+
+/*!<Mode_ARGB8888/RGB888 */
+
+#define DMA2D_OCOLR_BLUE_1 0x000000FFU /*!< BLUE Value */
+#define DMA2D_OCOLR_GREEN_1 0x0000FF00U /*!< GREEN Value */
+#define DMA2D_OCOLR_RED_1 0x00FF0000U /*!< Red Value */
+#define DMA2D_OCOLR_ALPHA_1 0xFF000000U /*!< Alpha Channel Value */
+
+/*!<Mode_RGB565 */
+#define DMA2D_OCOLR_BLUE_2 0x0000001FU /*!< BLUE Value */
+#define DMA2D_OCOLR_GREEN_2 0x000007E0U /*!< GREEN Value */
+#define DMA2D_OCOLR_RED_2 0x0000F800U /*!< Red Value */
+
+/*!<Mode_ARGB1555 */
+#define DMA2D_OCOLR_BLUE_3 0x0000001FU /*!< BLUE Value */
+#define DMA2D_OCOLR_GREEN_3 0x000003E0U /*!< GREEN Value */
+#define DMA2D_OCOLR_RED_3 0x00007C00U /*!< Red Value */
+#define DMA2D_OCOLR_ALPHA_3 0x00008000U /*!< Alpha Channel Value */
+
+/*!<Mode_ARGB4444 */
+#define DMA2D_OCOLR_BLUE_4 0x0000000FU /*!< BLUE Value */
+#define DMA2D_OCOLR_GREEN_4 0x000000F0U /*!< GREEN Value */
+#define DMA2D_OCOLR_RED_4 0x00000F00U /*!< Red Value */
+#define DMA2D_OCOLR_ALPHA_4 0x0000F000U /*!< Alpha Channel Value */
+
+/******************** Bit definition for DMA2D_OMAR register ****************/
+
+#define DMA2D_OMAR_MA 0xFFFFFFFFU /*!< Memory Address */
+
+/******************** Bit definition for DMA2D_OOR register *****************/
+
+#define DMA2D_OOR_LO 0x00003FFFU /*!< Line Offset */
+
+/******************** Bit definition for DMA2D_NLR register *****************/
+
+#define DMA2D_NLR_NL 0x0000FFFFU /*!< Number of Lines */
+#define DMA2D_NLR_PL 0x3FFF0000U /*!< Pixel per Lines */
+
+/******************** Bit definition for DMA2D_LWR register *****************/
+
+#define DMA2D_LWR_LW 0x0000FFFFU /*!< Line Watermark */
+
+/******************** Bit definition for DMA2D_AMTCR register ***************/
+
+#define DMA2D_AMTCR_EN 0x00000001U /*!< Enable */
+#define DMA2D_AMTCR_DT 0x0000FF00U /*!< Dead Time */
+
+/******************** Bit definition for DMA2D_FGCLUT register **************/
+
+/******************** Bit definition for DMA2D_BGCLUT register **************/
+
+
+
+/******************************************************************************/
+/* */
+/* External Interrupt/Event Controller */
+/* */
+/******************************************************************************/
+/******************* Bit definition for EXTI_IMR register *******************/
+#define EXTI_IMR_MR0 0x00000001U /*!< Interrupt Mask on line 0 */
+#define EXTI_IMR_MR1 0x00000002U /*!< Interrupt Mask on line 1 */
+#define EXTI_IMR_MR2 0x00000004U /*!< Interrupt Mask on line 2 */
+#define EXTI_IMR_MR3 0x00000008U /*!< Interrupt Mask on line 3 */
+#define EXTI_IMR_MR4 0x00000010U /*!< Interrupt Mask on line 4 */
+#define EXTI_IMR_MR5 0x00000020U /*!< Interrupt Mask on line 5 */
+#define EXTI_IMR_MR6 0x00000040U /*!< Interrupt Mask on line 6 */
+#define EXTI_IMR_MR7 0x00000080U /*!< Interrupt Mask on line 7 */
+#define EXTI_IMR_MR8 0x00000100U /*!< Interrupt Mask on line 8 */
+#define EXTI_IMR_MR9 0x00000200U /*!< Interrupt Mask on line 9 */
+#define EXTI_IMR_MR10 0x00000400U /*!< Interrupt Mask on line 10 */
+#define EXTI_IMR_MR11 0x00000800U /*!< Interrupt Mask on line 11 */
+#define EXTI_IMR_MR12 0x00001000U /*!< Interrupt Mask on line 12 */
+#define EXTI_IMR_MR13 0x00002000U /*!< Interrupt Mask on line 13 */
+#define EXTI_IMR_MR14 0x00004000U /*!< Interrupt Mask on line 14 */
+#define EXTI_IMR_MR15 0x00008000U /*!< Interrupt Mask on line 15 */
+#define EXTI_IMR_MR16 0x00010000U /*!< Interrupt Mask on line 16 */
+#define EXTI_IMR_MR17 0x00020000U /*!< Interrupt Mask on line 17 */
+#define EXTI_IMR_MR18 0x00040000U /*!< Interrupt Mask on line 18 */
+#define EXTI_IMR_MR19 0x00080000U /*!< Interrupt Mask on line 19 */
+#define EXTI_IMR_MR20 0x00100000U /*!< Interrupt Mask on line 20 */
+#define EXTI_IMR_MR21 0x00200000U /*!< Interrupt Mask on line 21 */
+#define EXTI_IMR_MR22 0x00400000U /*!< Interrupt Mask on line 22 */
+
+/******************* Bit definition for EXTI_EMR register *******************/
+#define EXTI_EMR_MR0 0x00000001U /*!< Event Mask on line 0 */
+#define EXTI_EMR_MR1 0x00000002U /*!< Event Mask on line 1 */
+#define EXTI_EMR_MR2 0x00000004U /*!< Event Mask on line 2 */
+#define EXTI_EMR_MR3 0x00000008U /*!< Event Mask on line 3 */
+#define EXTI_EMR_MR4 0x00000010U /*!< Event Mask on line 4 */
+#define EXTI_EMR_MR5 0x00000020U /*!< Event Mask on line 5 */
+#define EXTI_EMR_MR6 0x00000040U /*!< Event Mask on line 6 */
+#define EXTI_EMR_MR7 0x00000080U /*!< Event Mask on line 7 */
+#define EXTI_EMR_MR8 0x00000100U /*!< Event Mask on line 8 */
+#define EXTI_EMR_MR9 0x00000200U /*!< Event Mask on line 9 */
+#define EXTI_EMR_MR10 0x00000400U /*!< Event Mask on line 10 */
+#define EXTI_EMR_MR11 0x00000800U /*!< Event Mask on line 11 */
+#define EXTI_EMR_MR12 0x00001000U /*!< Event Mask on line 12 */
+#define EXTI_EMR_MR13 0x00002000U /*!< Event Mask on line 13 */
+#define EXTI_EMR_MR14 0x00004000U /*!< Event Mask on line 14 */
+#define EXTI_EMR_MR15 0x00008000U /*!< Event Mask on line 15 */
+#define EXTI_EMR_MR16 0x00010000U /*!< Event Mask on line 16 */
+#define EXTI_EMR_MR17 0x00020000U /*!< Event Mask on line 17 */
+#define EXTI_EMR_MR18 0x00040000U /*!< Event Mask on line 18 */
+#define EXTI_EMR_MR19 0x00080000U /*!< Event Mask on line 19 */
+#define EXTI_EMR_MR20 0x00100000U /*!< Event Mask on line 20 */
+#define EXTI_EMR_MR21 0x00200000U /*!< Event Mask on line 21 */
+#define EXTI_EMR_MR22 0x00400000U /*!< Event Mask on line 22 */
+
+/****************** Bit definition for EXTI_RTSR register *******************/
+#define EXTI_RTSR_TR0 0x00000001U /*!< Rising trigger event configuration bit of line 0 */
+#define EXTI_RTSR_TR1 0x00000002U /*!< Rising trigger event configuration bit of line 1 */
+#define EXTI_RTSR_TR2 0x00000004U /*!< Rising trigger event configuration bit of line 2 */
+#define EXTI_RTSR_TR3 0x00000008U /*!< Rising trigger event configuration bit of line 3 */
+#define EXTI_RTSR_TR4 0x00000010U /*!< Rising trigger event configuration bit of line 4 */
+#define EXTI_RTSR_TR5 0x00000020U /*!< Rising trigger event configuration bit of line 5 */
+#define EXTI_RTSR_TR6 0x00000040U /*!< Rising trigger event configuration bit of line 6 */
+#define EXTI_RTSR_TR7 0x00000080U /*!< Rising trigger event configuration bit of line 7 */
+#define EXTI_RTSR_TR8 0x00000100U /*!< Rising trigger event configuration bit of line 8 */
+#define EXTI_RTSR_TR9 0x00000200U /*!< Rising trigger event configuration bit of line 9 */
+#define EXTI_RTSR_TR10 0x00000400U /*!< Rising trigger event configuration bit of line 10 */
+#define EXTI_RTSR_TR11 0x00000800U /*!< Rising trigger event configuration bit of line 11 */
+#define EXTI_RTSR_TR12 0x00001000U /*!< Rising trigger event configuration bit of line 12 */
+#define EXTI_RTSR_TR13 0x00002000U /*!< Rising trigger event configuration bit of line 13 */
+#define EXTI_RTSR_TR14 0x00004000U /*!< Rising trigger event configuration bit of line 14 */
+#define EXTI_RTSR_TR15 0x00008000U /*!< Rising trigger event configuration bit of line 15 */
+#define EXTI_RTSR_TR16 0x00010000U /*!< Rising trigger event configuration bit of line 16 */
+#define EXTI_RTSR_TR17 0x00020000U /*!< Rising trigger event configuration bit of line 17 */
+#define EXTI_RTSR_TR18 0x00040000U /*!< Rising trigger event configuration bit of line 18 */
+#define EXTI_RTSR_TR19 0x00080000U /*!< Rising trigger event configuration bit of line 19 */
+#define EXTI_RTSR_TR20 0x00100000U /*!< Rising trigger event configuration bit of line 20 */
+#define EXTI_RTSR_TR21 0x00200000U /*!< Rising trigger event configuration bit of line 21 */
+#define EXTI_RTSR_TR22 0x00400000U /*!< Rising trigger event configuration bit of line 22 */
+
+/****************** Bit definition for EXTI_FTSR register *******************/
+#define EXTI_FTSR_TR0 0x00000001U /*!< Falling trigger event configuration bit of line 0 */
+#define EXTI_FTSR_TR1 0x00000002U /*!< Falling trigger event configuration bit of line 1 */
+#define EXTI_FTSR_TR2 0x00000004U /*!< Falling trigger event configuration bit of line 2 */
+#define EXTI_FTSR_TR3 0x00000008U /*!< Falling trigger event configuration bit of line 3 */
+#define EXTI_FTSR_TR4 0x00000010U /*!< Falling trigger event configuration bit of line 4 */
+#define EXTI_FTSR_TR5 0x00000020U /*!< Falling trigger event configuration bit of line 5 */
+#define EXTI_FTSR_TR6 0x00000040U /*!< Falling trigger event configuration bit of line 6 */
+#define EXTI_FTSR_TR7 0x00000080U /*!< Falling trigger event configuration bit of line 7 */
+#define EXTI_FTSR_TR8 0x00000100U /*!< Falling trigger event configuration bit of line 8 */
+#define EXTI_FTSR_TR9 0x00000200U /*!< Falling trigger event configuration bit of line 9 */
+#define EXTI_FTSR_TR10 0x00000400U /*!< Falling trigger event configuration bit of line 10 */
+#define EXTI_FTSR_TR11 0x00000800U /*!< Falling trigger event configuration bit of line 11 */
+#define EXTI_FTSR_TR12 0x00001000U /*!< Falling trigger event configuration bit of line 12 */
+#define EXTI_FTSR_TR13 0x00002000U /*!< Falling trigger event configuration bit of line 13 */
+#define EXTI_FTSR_TR14 0x00004000U /*!< Falling trigger event configuration bit of line 14 */
+#define EXTI_FTSR_TR15 0x00008000U /*!< Falling trigger event configuration bit of line 15 */
+#define EXTI_FTSR_TR16 0x00010000U /*!< Falling trigger event configuration bit of line 16 */
+#define EXTI_FTSR_TR17 0x00020000U /*!< Falling trigger event configuration bit of line 17 */
+#define EXTI_FTSR_TR18 0x00040000U /*!< Falling trigger event configuration bit of line 18 */
+#define EXTI_FTSR_TR19 0x00080000U /*!< Falling trigger event configuration bit of line 19 */
+#define EXTI_FTSR_TR20 0x00100000U /*!< Falling trigger event configuration bit of line 20 */
+#define EXTI_FTSR_TR21 0x00200000U /*!< Falling trigger event configuration bit of line 21 */
+#define EXTI_FTSR_TR22 0x00400000U /*!< Falling trigger event configuration bit of line 22 */
+
+/****************** Bit definition for EXTI_SWIER register ******************/
+#define EXTI_SWIER_SWIER0 0x00000001U /*!< Software Interrupt on line 0 */
+#define EXTI_SWIER_SWIER1 0x00000002U /*!< Software Interrupt on line 1 */
+#define EXTI_SWIER_SWIER2 0x00000004U /*!< Software Interrupt on line 2 */
+#define EXTI_SWIER_SWIER3 0x00000008U /*!< Software Interrupt on line 3 */
+#define EXTI_SWIER_SWIER4 0x00000010U /*!< Software Interrupt on line 4 */
+#define EXTI_SWIER_SWIER5 0x00000020U /*!< Software Interrupt on line 5 */
+#define EXTI_SWIER_SWIER6 0x00000040U /*!< Software Interrupt on line 6 */
+#define EXTI_SWIER_SWIER7 0x00000080U /*!< Software Interrupt on line 7 */
+#define EXTI_SWIER_SWIER8 0x00000100U /*!< Software Interrupt on line 8 */
+#define EXTI_SWIER_SWIER9 0x00000200U /*!< Software Interrupt on line 9 */
+#define EXTI_SWIER_SWIER10 0x00000400U /*!< Software Interrupt on line 10 */
+#define EXTI_SWIER_SWIER11 0x00000800U /*!< Software Interrupt on line 11 */
+#define EXTI_SWIER_SWIER12 0x00001000U /*!< Software Interrupt on line 12 */
+#define EXTI_SWIER_SWIER13 0x00002000U /*!< Software Interrupt on line 13 */
+#define EXTI_SWIER_SWIER14 0x00004000U /*!< Software Interrupt on line 14 */
+#define EXTI_SWIER_SWIER15 0x00008000U /*!< Software Interrupt on line 15 */
+#define EXTI_SWIER_SWIER16 0x00010000U /*!< Software Interrupt on line 16 */
+#define EXTI_SWIER_SWIER17 0x00020000U /*!< Software Interrupt on line 17 */
+#define EXTI_SWIER_SWIER18 0x00040000U /*!< Software Interrupt on line 18 */
+#define EXTI_SWIER_SWIER19 0x00080000U /*!< Software Interrupt on line 19 */
+#define EXTI_SWIER_SWIER20 0x00100000U /*!< Software Interrupt on line 20 */
+#define EXTI_SWIER_SWIER21 0x00200000U /*!< Software Interrupt on line 21 */
+#define EXTI_SWIER_SWIER22 0x00400000U /*!< Software Interrupt on line 22 */
+
+/******************* Bit definition for EXTI_PR register ********************/
+#define EXTI_PR_PR0 0x00000001U /*!< Pending bit for line 0 */
+#define EXTI_PR_PR1 0x00000002U /*!< Pending bit for line 1 */
+#define EXTI_PR_PR2 0x00000004U /*!< Pending bit for line 2 */
+#define EXTI_PR_PR3 0x00000008U /*!< Pending bit for line 3 */
+#define EXTI_PR_PR4 0x00000010U /*!< Pending bit for line 4 */
+#define EXTI_PR_PR5 0x00000020U /*!< Pending bit for line 5 */
+#define EXTI_PR_PR6 0x00000040U /*!< Pending bit for line 6 */
+#define EXTI_PR_PR7 0x00000080U /*!< Pending bit for line 7 */
+#define EXTI_PR_PR8 0x00000100U /*!< Pending bit for line 8 */
+#define EXTI_PR_PR9 0x00000200U /*!< Pending bit for line 9 */
+#define EXTI_PR_PR10 0x00000400U /*!< Pending bit for line 10 */
+#define EXTI_PR_PR11 0x00000800U /*!< Pending bit for line 11 */
+#define EXTI_PR_PR12 0x00001000U /*!< Pending bit for line 12 */
+#define EXTI_PR_PR13 0x00002000U /*!< Pending bit for line 13 */
+#define EXTI_PR_PR14 0x00004000U /*!< Pending bit for line 14 */
+#define EXTI_PR_PR15 0x00008000U /*!< Pending bit for line 15 */
+#define EXTI_PR_PR16 0x00010000U /*!< Pending bit for line 16 */
+#define EXTI_PR_PR17 0x00020000U /*!< Pending bit for line 17 */
+#define EXTI_PR_PR18 0x00040000U /*!< Pending bit for line 18 */
+#define EXTI_PR_PR19 0x00080000U /*!< Pending bit for line 19 */
+#define EXTI_PR_PR20 0x00100000U /*!< Pending bit for line 20 */
+#define EXTI_PR_PR21 0x00200000U /*!< Pending bit for line 21 */
+#define EXTI_PR_PR22 0x00400000U /*!< Pending bit for line 22 */
+
+/******************************************************************************/
+/* */
+/* FLASH */
+/* */
+/******************************************************************************/
+/******************* Bits definition for FLASH_ACR register *****************/
+#define FLASH_ACR_LATENCY 0x0000000FU
+#define FLASH_ACR_LATENCY_0WS 0x00000000U
+#define FLASH_ACR_LATENCY_1WS 0x00000001U
+#define FLASH_ACR_LATENCY_2WS 0x00000002U
+#define FLASH_ACR_LATENCY_3WS 0x00000003U
+#define FLASH_ACR_LATENCY_4WS 0x00000004U
+#define FLASH_ACR_LATENCY_5WS 0x00000005U
+#define FLASH_ACR_LATENCY_6WS 0x00000006U
+#define FLASH_ACR_LATENCY_7WS 0x00000007U
+#define FLASH_ACR_LATENCY_8WS 0x00000008U
+#define FLASH_ACR_LATENCY_9WS 0x00000009U
+#define FLASH_ACR_LATENCY_10WS 0x0000000AU
+#define FLASH_ACR_LATENCY_11WS 0x0000000BU
+#define FLASH_ACR_LATENCY_12WS 0x0000000CU
+#define FLASH_ACR_LATENCY_13WS 0x0000000DU
+#define FLASH_ACR_LATENCY_14WS 0x0000000EU
+#define FLASH_ACR_LATENCY_15WS 0x0000000FU
+#define FLASH_ACR_PRFTEN 0x00000100U
+#define FLASH_ACR_ICEN 0x00000200U
+#define FLASH_ACR_DCEN 0x00000400U
+#define FLASH_ACR_ICRST 0x00000800U
+#define FLASH_ACR_DCRST 0x00001000U
+#define FLASH_ACR_BYTE0_ADDRESS 0x40023C00U
+#define FLASH_ACR_BYTE2_ADDRESS 0x40023C03U
+
+/******************* Bits definition for FLASH_SR register ******************/
+#define FLASH_SR_EOP 0x00000001U
+#define FLASH_SR_SOP 0x00000002U
+#define FLASH_SR_WRPERR 0x00000010U
+#define FLASH_SR_PGAERR 0x00000020U
+#define FLASH_SR_PGPERR 0x00000040U
+#define FLASH_SR_PGSERR 0x00000080U
+#define FLASH_SR_BSY 0x00010000U
+
+/******************* Bits definition for FLASH_CR register ******************/
+#define FLASH_CR_PG 0x00000001U
+#define FLASH_CR_SER 0x00000002U
+#define FLASH_CR_MER 0x00000004U
+#define FLASH_CR_MER1 FLASH_CR_MER
+#define FLASH_CR_SNB 0x000000F8U
+#define FLASH_CR_SNB_0 0x00000008U
+#define FLASH_CR_SNB_1 0x00000010U
+#define FLASH_CR_SNB_2 0x00000020U
+#define FLASH_CR_SNB_3 0x00000040U
+#define FLASH_CR_SNB_4 0x00000080U
+#define FLASH_CR_PSIZE 0x00000300U
+#define FLASH_CR_PSIZE_0 0x00000100U
+#define FLASH_CR_PSIZE_1 0x00000200U
+#define FLASH_CR_MER2 0x00008000U
+#define FLASH_CR_STRT 0x00010000U
+#define FLASH_CR_EOPIE 0x01000000U
+#define FLASH_CR_LOCK 0x80000000U
+
+/******************* Bits definition for FLASH_OPTCR register ***************/
+#define FLASH_OPTCR_OPTLOCK 0x00000001U
+#define FLASH_OPTCR_OPTSTRT 0x00000002U
+#define FLASH_OPTCR_BOR_LEV_0 0x00000004U
+#define FLASH_OPTCR_BOR_LEV_1 0x00000008U
+#define FLASH_OPTCR_BOR_LEV 0x0000000CU
+#define FLASH_OPTCR_BFB2 0x00000010U
+#define FLASH_OPTCR_WDG_SW 0x00000020U
+#define FLASH_OPTCR_nRST_STOP 0x00000040U
+#define FLASH_OPTCR_nRST_STDBY 0x00000080U
+#define FLASH_OPTCR_RDP 0x0000FF00U
+#define FLASH_OPTCR_RDP_0 0x00000100U
+#define FLASH_OPTCR_RDP_1 0x00000200U
+#define FLASH_OPTCR_RDP_2 0x00000400U
+#define FLASH_OPTCR_RDP_3 0x00000800U
+#define FLASH_OPTCR_RDP_4 0x00001000U
+#define FLASH_OPTCR_RDP_5 0x00002000U
+#define FLASH_OPTCR_RDP_6 0x00004000U
+#define FLASH_OPTCR_RDP_7 0x00008000U
+#define FLASH_OPTCR_nWRP 0x0FFF0000U
+#define FLASH_OPTCR_nWRP_0 0x00010000U
+#define FLASH_OPTCR_nWRP_1 0x00020000U
+#define FLASH_OPTCR_nWRP_2 0x00040000U
+#define FLASH_OPTCR_nWRP_3 0x00080000U
+#define FLASH_OPTCR_nWRP_4 0x00100000U
+#define FLASH_OPTCR_nWRP_5 0x00200000U
+#define FLASH_OPTCR_nWRP_6 0x00400000U
+#define FLASH_OPTCR_nWRP_7 0x00800000U
+#define FLASH_OPTCR_nWRP_8 0x01000000U
+#define FLASH_OPTCR_nWRP_9 0x02000000U
+#define FLASH_OPTCR_nWRP_10 0x04000000U
+#define FLASH_OPTCR_nWRP_11 0x08000000U
+#define FLASH_OPTCR_DB1M 0x40000000U
+#define FLASH_OPTCR_SPRMOD 0x80000000U
+
+/****************** Bits definition for FLASH_OPTCR1 register ***************/
+#define FLASH_OPTCR1_nWRP 0x0FFF0000U
+#define FLASH_OPTCR1_nWRP_0 0x00010000U
+#define FLASH_OPTCR1_nWRP_1 0x00020000U
+#define FLASH_OPTCR1_nWRP_2 0x00040000U
+#define FLASH_OPTCR1_nWRP_3 0x00080000U
+#define FLASH_OPTCR1_nWRP_4 0x00100000U
+#define FLASH_OPTCR1_nWRP_5 0x00200000U
+#define FLASH_OPTCR1_nWRP_6 0x00400000U
+#define FLASH_OPTCR1_nWRP_7 0x00800000U
+#define FLASH_OPTCR1_nWRP_8 0x01000000U
+#define FLASH_OPTCR1_nWRP_9 0x02000000U
+#define FLASH_OPTCR1_nWRP_10 0x04000000U
+#define FLASH_OPTCR1_nWRP_11 0x08000000U
+
+/******************************************************************************/
+/* */
+/* Flexible Memory Controller */
+/* */
+/******************************************************************************/
+/****************** Bit definition for FMC_BCR1 register *******************/
+#define FMC_BCR1_MBKEN 0x00000001U /*!<Memory bank enable bit */
+#define FMC_BCR1_MUXEN 0x00000002U /*!<Address/data multiplexing enable bit */
+
+#define FMC_BCR1_MTYP 0x0000000CU /*!<MTYP[1:0] bits (Memory type) */
+#define FMC_BCR1_MTYP_0 0x00000004U /*!<Bit 0 */
+#define FMC_BCR1_MTYP_1 0x00000008U /*!<Bit 1 */
+
+#define FMC_BCR1_MWID 0x00000030U /*!<MWID[1:0] bits (Memory data bus width) */
+#define FMC_BCR1_MWID_0 0x00000010U /*!<Bit 0 */
+#define FMC_BCR1_MWID_1 0x00000020U /*!<Bit 1 */
+
+#define FMC_BCR1_FACCEN 0x00000040U /*!<Flash access enable */
+#define FMC_BCR1_BURSTEN 0x00000100U /*!<Burst enable bit */
+#define FMC_BCR1_WAITPOL 0x00000200U /*!<Wait signal polarity bit */
+#define FMC_BCR1_WRAPMOD 0x00000400U /*!<Wrapped burst mode support */
+#define FMC_BCR1_WAITCFG 0x00000800U /*!<Wait timing configuration */
+#define FMC_BCR1_WREN 0x00001000U /*!<Write enable bit */
+#define FMC_BCR1_WAITEN 0x00002000U /*!<Wait enable bit */
+#define FMC_BCR1_EXTMOD 0x00004000U /*!<Extended mode enable */
+#define FMC_BCR1_ASYNCWAIT 0x00008000U /*!<Asynchronous wait */
+#define FMC_BCR1_CPSIZE 0x00070000U /*!<CRAM page size */
+#define FMC_BCR1_CPSIZE_0 0x00010000U /*!<Bit 0 */
+#define FMC_BCR1_CPSIZE_1 0x00020000U /*!<Bit 1 */
+#define FMC_BCR1_CPSIZE_2 0x00040000U /*!<Bit 2 */
+#define FMC_BCR1_CBURSTRW 0x00080000U /*!<Write burst enable */
+#define FMC_BCR1_CCLKEN 0x00100000U /*!<Continous clock enable */
+
+/****************** Bit definition for FMC_BCR2 register *******************/
+#define FMC_BCR2_MBKEN 0x00000001U /*!<Memory bank enable bit */
+#define FMC_BCR2_MUXEN 0x00000002U /*!<Address/data multiplexing enable bit */
+
+#define FMC_BCR2_MTYP 0x0000000CU /*!<MTYP[1:0] bits (Memory type) */
+#define FMC_BCR2_MTYP_0 0x00000004U /*!<Bit 0 */
+#define FMC_BCR2_MTYP_1 0x00000008U /*!<Bit 1 */
+
+#define FMC_BCR2_MWID 0x00000030U /*!<MWID[1:0] bits (Memory data bus width) */
+#define FMC_BCR2_MWID_0 0x00000010U /*!<Bit 0 */
+#define FMC_BCR2_MWID_1 0x00000020U /*!<Bit 1 */
+
+#define FMC_BCR2_FACCEN 0x00000040U /*!<Flash access enable */
+#define FMC_BCR2_BURSTEN 0x00000100U /*!<Burst enable bit */
+#define FMC_BCR2_WAITPOL 0x00000200U /*!<Wait signal polarity bit */
+#define FMC_BCR2_WRAPMOD 0x00000400U /*!<Wrapped burst mode support */
+#define FMC_BCR2_WAITCFG 0x00000800U /*!<Wait timing configuration */
+#define FMC_BCR2_WREN 0x00001000U /*!<Write enable bit */
+#define FMC_BCR2_WAITEN 0x00002000U /*!<Wait enable bit */
+#define FMC_BCR2_EXTMOD 0x00004000U /*!<Extended mode enable */
+#define FMC_BCR2_ASYNCWAIT 0x00008000U /*!<Asynchronous wait */
+#define FMC_BCR2_CPSIZE 0x00070000U /*!<CRAM page size */
+#define FMC_BCR2_CPSIZE_0 0x00010000U /*!<Bit 0 */
+#define FMC_BCR2_CPSIZE_1 0x00020000U /*!<Bit 1 */
+#define FMC_BCR2_CPSIZE_2 0x00040000U /*!<Bit 2 */
+#define FMC_BCR2_CBURSTRW 0x00080000U /*!<Write burst enable */
+
+/****************** Bit definition for FMC_BCR3 register *******************/
+#define FMC_BCR3_MBKEN 0x00000001U /*!<Memory bank enable bit */
+#define FMC_BCR3_MUXEN 0x00000002U /*!<Address/data multiplexing enable bit */
+
+#define FMC_BCR3_MTYP 0x0000000CU /*!<MTYP[1:0] bits (Memory type) */
+#define FMC_BCR3_MTYP_0 0x00000004U /*!<Bit 0 */
+#define FMC_BCR3_MTYP_1 0x00000008U /*!<Bit 1 */
+
+#define FMC_BCR3_MWID 0x00000030U /*!<MWID[1:0] bits (Memory data bus width) */
+#define FMC_BCR3_MWID_0 0x00000010U /*!<Bit 0 */
+#define FMC_BCR3_MWID_1 0x00000020U /*!<Bit 1 */
+
+#define FMC_BCR3_FACCEN 0x00000040U /*!<Flash access enable */
+#define FMC_BCR3_BURSTEN 0x00000100U /*!<Burst enable bit */
+#define FMC_BCR3_WAITPOL 0x00000200U /*!<Wait signal polarity bit */
+#define FMC_BCR3_WRAPMOD 0x00000400U /*!<Wrapped burst mode support */
+#define FMC_BCR3_WAITCFG 0x00000800U /*!<Wait timing configuration */
+#define FMC_BCR3_WREN 0x00001000U /*!<Write enable bit */
+#define FMC_BCR3_WAITEN 0x00002000U /*!<Wait enable bit */
+#define FMC_BCR3_EXTMOD 0x00004000U /*!<Extended mode enable */
+#define FMC_BCR3_ASYNCWAIT 0x00008000U /*!<Asynchronous wait */
+#define FMC_BCR3_CPSIZE 0x00070000U /*!<CRAM page size */
+#define FMC_BCR3_CPSIZE_0 0x00010000U /*!<Bit 0 */
+#define FMC_BCR3_CPSIZE_1 0x00020000U /*!<Bit 1 */
+#define FMC_BCR3_CPSIZE_2 0x00040000U /*!<Bit 2 */
+#define FMC_BCR3_CBURSTRW 0x00080000U /*!<Write burst enable */
+
+/****************** Bit definition for FMC_BCR4 register *******************/
+#define FMC_BCR4_MBKEN 0x00000001U /*!<Memory bank enable bit */
+#define FMC_BCR4_MUXEN 0x00000002U /*!<Address/data multiplexing enable bit */
+
+#define FMC_BCR4_MTYP 0x0000000CU /*!<MTYP[1:0] bits (Memory type) */
+#define FMC_BCR4_MTYP_0 0x00000004U /*!<Bit 0 */
+#define FMC_BCR4_MTYP_1 0x00000008U /*!<Bit 1 */
+
+#define FMC_BCR4_MWID 0x00000030U /*!<MWID[1:0] bits (Memory data bus width) */
+#define FMC_BCR4_MWID_0 0x00000010U /*!<Bit 0 */
+#define FMC_BCR4_MWID_1 0x00000020U /*!<Bit 1 */
+
+#define FMC_BCR4_FACCEN 0x00000040U /*!<Flash access enable */
+#define FMC_BCR4_BURSTEN 0x00000100U /*!<Burst enable bit */
+#define FMC_BCR4_WAITPOL 0x00000200U /*!<Wait signal polarity bit */
+#define FMC_BCR4_WRAPMOD 0x00000400U /*!<Wrapped burst mode support */
+#define FMC_BCR4_WAITCFG 0x00000800U /*!<Wait timing configuration */
+#define FMC_BCR4_WREN 0x00001000U /*!<Write enable bit */
+#define FMC_BCR4_WAITEN 0x00002000U /*!<Wait enable bit */
+#define FMC_BCR4_EXTMOD 0x00004000U /*!<Extended mode enable */
+#define FMC_BCR4_ASYNCWAIT 0x00008000U /*!<Asynchronous wait */
+#define FMC_BCR4_CPSIZE 0x00070000U /*!<CRAM page size */
+#define FMC_BCR4_CPSIZE_0 0x00010000U /*!<Bit 0 */
+#define FMC_BCR4_CPSIZE_1 0x00020000U /*!<Bit 1 */
+#define FMC_BCR4_CPSIZE_2 0x00040000U /*!<Bit 2 */
+#define FMC_BCR4_CBURSTRW 0x00080000U /*!<Write burst enable */
+
+/****************** Bit definition for FMC_BTR1 register ******************/
+#define FMC_BTR1_ADDSET 0x0000000FU /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FMC_BTR1_ADDSET_0 0x00000001U /*!<Bit 0 */
+#define FMC_BTR1_ADDSET_1 0x00000002U /*!<Bit 1 */
+#define FMC_BTR1_ADDSET_2 0x00000004U /*!<Bit 2 */
+#define FMC_BTR1_ADDSET_3 0x00000008U /*!<Bit 3 */
+
+#define FMC_BTR1_ADDHLD 0x000000F0U /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FMC_BTR1_ADDHLD_0 0x00000010U /*!<Bit 0 */
+#define FMC_BTR1_ADDHLD_1 0x00000020U /*!<Bit 1 */
+#define FMC_BTR1_ADDHLD_2 0x00000040U /*!<Bit 2 */
+#define FMC_BTR1_ADDHLD_3 0x00000080U /*!<Bit 3 */
+
+#define FMC_BTR1_DATAST 0x0000FF00U /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FMC_BTR1_DATAST_0 0x00000100U /*!<Bit 0 */
+#define FMC_BTR1_DATAST_1 0x00000200U /*!<Bit 1 */
+#define FMC_BTR1_DATAST_2 0x00000400U /*!<Bit 2 */
+#define FMC_BTR1_DATAST_3 0x00000800U /*!<Bit 3 */
+#define FMC_BTR1_DATAST_4 0x00001000U /*!<Bit 4 */
+#define FMC_BTR1_DATAST_5 0x00002000U /*!<Bit 5 */
+#define FMC_BTR1_DATAST_6 0x00004000U /*!<Bit 6 */
+#define FMC_BTR1_DATAST_7 0x00008000U /*!<Bit 7 */
+
+#define FMC_BTR1_BUSTURN 0x000F0000U /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define FMC_BTR1_BUSTURN_0 0x00010000U /*!<Bit 0 */
+#define FMC_BTR1_BUSTURN_1 0x00020000U /*!<Bit 1 */
+#define FMC_BTR1_BUSTURN_2 0x00040000U /*!<Bit 2 */
+#define FMC_BTR1_BUSTURN_3 0x00080000U /*!<Bit 3 */
+
+#define FMC_BTR1_CLKDIV 0x00F00000U /*!<CLKDIV[3:0] bits (Clock divide ratio) */
+#define FMC_BTR1_CLKDIV_0 0x00100000U /*!<Bit 0 */
+#define FMC_BTR1_CLKDIV_1 0x00200000U /*!<Bit 1 */
+#define FMC_BTR1_CLKDIV_2 0x00400000U /*!<Bit 2 */
+#define FMC_BTR1_CLKDIV_3 0x00800000U /*!<Bit 3 */
+
+#define FMC_BTR1_DATLAT 0x0F000000U /*!<DATLA[3:0] bits (Data latency) */
+#define FMC_BTR1_DATLAT_0 0x01000000U /*!<Bit 0 */
+#define FMC_BTR1_DATLAT_1 0x02000000U /*!<Bit 1 */
+#define FMC_BTR1_DATLAT_2 0x04000000U /*!<Bit 2 */
+#define FMC_BTR1_DATLAT_3 0x08000000U /*!<Bit 3 */
+
+#define FMC_BTR1_ACCMOD 0x30000000U /*!<ACCMOD[1:0] bits (Access mode) */
+#define FMC_BTR1_ACCMOD_0 0x10000000U /*!<Bit 0 */
+#define FMC_BTR1_ACCMOD_1 0x20000000U /*!<Bit 1 */
+
+/****************** Bit definition for FMC_BTR2 register *******************/
+#define FMC_BTR2_ADDSET 0x0000000FU /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FMC_BTR2_ADDSET_0 0x00000001U /*!<Bit 0 */
+#define FMC_BTR2_ADDSET_1 0x00000002U /*!<Bit 1 */
+#define FMC_BTR2_ADDSET_2 0x00000004U /*!<Bit 2 */
+#define FMC_BTR2_ADDSET_3 0x00000008U /*!<Bit 3 */
+
+#define FMC_BTR2_ADDHLD 0x000000F0U /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FMC_BTR2_ADDHLD_0 0x00000010U /*!<Bit 0 */
+#define FMC_BTR2_ADDHLD_1 0x00000020U /*!<Bit 1 */
+#define FMC_BTR2_ADDHLD_2 0x00000040U /*!<Bit 2 */
+#define FMC_BTR2_ADDHLD_3 0x00000080U /*!<Bit 3 */
+
+#define FMC_BTR2_DATAST 0x0000FF00U /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FMC_BTR2_DATAST_0 0x00000100U /*!<Bit 0 */
+#define FMC_BTR2_DATAST_1 0x00000200U /*!<Bit 1 */
+#define FMC_BTR2_DATAST_2 0x00000400U /*!<Bit 2 */
+#define FMC_BTR2_DATAST_3 0x00000800U /*!<Bit 3 */
+#define FMC_BTR2_DATAST_4 0x00001000U /*!<Bit 4 */
+#define FMC_BTR2_DATAST_5 0x00002000U /*!<Bit 5 */
+#define FMC_BTR2_DATAST_6 0x00004000U /*!<Bit 6 */
+#define FMC_BTR2_DATAST_7 0x00008000U /*!<Bit 7 */
+
+#define FMC_BTR2_BUSTURN 0x000F0000U /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define FMC_BTR2_BUSTURN_0 0x00010000U /*!<Bit 0 */
+#define FMC_BTR2_BUSTURN_1 0x00020000U /*!<Bit 1 */
+#define FMC_BTR2_BUSTURN_2 0x00040000U /*!<Bit 2 */
+#define FMC_BTR2_BUSTURN_3 0x00080000U /*!<Bit 3 */
+
+#define FMC_BTR2_CLKDIV 0x00F00000U /*!<CLKDIV[3:0] bits (Clock divide ratio) */
+#define FMC_BTR2_CLKDIV_0 0x00100000U /*!<Bit 0 */
+#define FMC_BTR2_CLKDIV_1 0x00200000U /*!<Bit 1 */
+#define FMC_BTR2_CLKDIV_2 0x00400000U /*!<Bit 2 */
+#define FMC_BTR2_CLKDIV_3 0x00800000U /*!<Bit 3 */
+
+#define FMC_BTR2_DATLAT 0x0F000000U /*!<DATLA[3:0] bits (Data latency) */
+#define FMC_BTR2_DATLAT_0 0x01000000U /*!<Bit 0 */
+#define FMC_BTR2_DATLAT_1 0x02000000U /*!<Bit 1 */
+#define FMC_BTR2_DATLAT_2 0x04000000U /*!<Bit 2 */
+#define FMC_BTR2_DATLAT_3 0x08000000U /*!<Bit 3 */
+
+#define FMC_BTR2_ACCMOD 0x30000000U /*!<ACCMOD[1:0] bits (Access mode) */
+#define FMC_BTR2_ACCMOD_0 0x10000000U /*!<Bit 0 */
+#define FMC_BTR2_ACCMOD_1 0x20000000U /*!<Bit 1 */
+
+/******************* Bit definition for FMC_BTR3 register *******************/
+#define FMC_BTR3_ADDSET 0x0000000FU /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FMC_BTR3_ADDSET_0 0x00000001U /*!<Bit 0 */
+#define FMC_BTR3_ADDSET_1 0x00000002U /*!<Bit 1 */
+#define FMC_BTR3_ADDSET_2 0x00000004U /*!<Bit 2 */
+#define FMC_BTR3_ADDSET_3 0x00000008U /*!<Bit 3 */
+
+#define FMC_BTR3_ADDHLD 0x000000F0U /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FMC_BTR3_ADDHLD_0 0x00000010U /*!<Bit 0 */
+#define FMC_BTR3_ADDHLD_1 0x00000020U /*!<Bit 1 */
+#define FMC_BTR3_ADDHLD_2 0x00000040U /*!<Bit 2 */
+#define FMC_BTR3_ADDHLD_3 0x00000080U /*!<Bit 3 */
+
+#define FMC_BTR3_DATAST 0x0000FF00U /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FMC_BTR3_DATAST_0 0x00000100U /*!<Bit 0 */
+#define FMC_BTR3_DATAST_1 0x00000200U /*!<Bit 1 */
+#define FMC_BTR3_DATAST_2 0x00000400U /*!<Bit 2 */
+#define FMC_BTR3_DATAST_3 0x00000800U /*!<Bit 3 */
+#define FMC_BTR3_DATAST_4 0x00001000U /*!<Bit 4 */
+#define FMC_BTR3_DATAST_5 0x00002000U /*!<Bit 5 */
+#define FMC_BTR3_DATAST_6 0x00004000U /*!<Bit 6 */
+#define FMC_BTR3_DATAST_7 0x00008000U /*!<Bit 7 */
+
+#define FMC_BTR3_BUSTURN 0x000F0000U /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define FMC_BTR3_BUSTURN_0 0x00010000U /*!<Bit 0 */
+#define FMC_BTR3_BUSTURN_1 0x00020000U /*!<Bit 1 */
+#define FMC_BTR3_BUSTURN_2 0x00040000U /*!<Bit 2 */
+#define FMC_BTR3_BUSTURN_3 0x00080000U /*!<Bit 3 */
+
+#define FMC_BTR3_CLKDIV 0x00F00000U /*!<CLKDIV[3:0] bits (Clock divide ratio) */
+#define FMC_BTR3_CLKDIV_0 0x00100000U /*!<Bit 0 */
+#define FMC_BTR3_CLKDIV_1 0x00200000U /*!<Bit 1 */
+#define FMC_BTR3_CLKDIV_2 0x00400000U /*!<Bit 2 */
+#define FMC_BTR3_CLKDIV_3 0x00800000U /*!<Bit 3 */
+
+#define FMC_BTR3_DATLAT 0x0F000000U /*!<DATLA[3:0] bits (Data latency) */
+#define FMC_BTR3_DATLAT_0 0x01000000U /*!<Bit 0 */
+#define FMC_BTR3_DATLAT_1 0x02000000U /*!<Bit 1 */
+#define FMC_BTR3_DATLAT_2 0x04000000U /*!<Bit 2 */
+#define FMC_BTR3_DATLAT_3 0x08000000U /*!<Bit 3 */
+
+#define FMC_BTR3_ACCMOD 0x30000000U /*!<ACCMOD[1:0] bits (Access mode) */
+#define FMC_BTR3_ACCMOD_0 0x10000000U /*!<Bit 0 */
+#define FMC_BTR3_ACCMOD_1 0x20000000U /*!<Bit 1 */
+
+/****************** Bit definition for FMC_BTR4 register *******************/
+#define FMC_BTR4_ADDSET 0x0000000FU /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FMC_BTR4_ADDSET_0 0x00000001U /*!<Bit 0 */
+#define FMC_BTR4_ADDSET_1 0x00000002U /*!<Bit 1 */
+#define FMC_BTR4_ADDSET_2 0x00000004U /*!<Bit 2 */
+#define FMC_BTR4_ADDSET_3 0x00000008U /*!<Bit 3 */
+
+#define FMC_BTR4_ADDHLD 0x000000F0U /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FMC_BTR4_ADDHLD_0 0x00000010U /*!<Bit 0 */
+#define FMC_BTR4_ADDHLD_1 0x00000020U /*!<Bit 1 */
+#define FMC_BTR4_ADDHLD_2 0x00000040U /*!<Bit 2 */
+#define FMC_BTR4_ADDHLD_3 0x00000080U /*!<Bit 3 */
+
+#define FMC_BTR4_DATAST 0x0000FF00U /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FMC_BTR4_DATAST_0 0x00000100U /*!<Bit 0 */
+#define FMC_BTR4_DATAST_1 0x00000200U /*!<Bit 1 */
+#define FMC_BTR4_DATAST_2 0x00000400U /*!<Bit 2 */
+#define FMC_BTR4_DATAST_3 0x00000800U /*!<Bit 3 */
+#define FMC_BTR4_DATAST_4 0x00001000U /*!<Bit 4 */
+#define FMC_BTR4_DATAST_5 0x00002000U /*!<Bit 5 */
+#define FMC_BTR4_DATAST_6 0x00004000U /*!<Bit 6 */
+#define FMC_BTR4_DATAST_7 0x00008000U /*!<Bit 7 */
+
+#define FMC_BTR4_BUSTURN 0x000F0000U /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define FMC_BTR4_BUSTURN_0 0x00010000U /*!<Bit 0 */
+#define FMC_BTR4_BUSTURN_1 0x00020000U /*!<Bit 1 */
+#define FMC_BTR4_BUSTURN_2 0x00040000U /*!<Bit 2 */
+#define FMC_BTR4_BUSTURN_3 0x00080000U /*!<Bit 3 */
+
+#define FMC_BTR4_CLKDIV 0x00F00000U /*!<CLKDIV[3:0] bits (Clock divide ratio) */
+#define FMC_BTR4_CLKDIV_0 0x00100000U /*!<Bit 0 */
+#define FMC_BTR4_CLKDIV_1 0x00200000U /*!<Bit 1 */
+#define FMC_BTR4_CLKDIV_2 0x00400000U /*!<Bit 2 */
+#define FMC_BTR4_CLKDIV_3 0x00800000U /*!<Bit 3 */
+
+#define FMC_BTR4_DATLAT 0x0F000000U /*!<DATLA[3:0] bits (Data latency) */
+#define FMC_BTR4_DATLAT_0 0x01000000U /*!<Bit 0 */
+#define FMC_BTR4_DATLAT_1 0x02000000U /*!<Bit 1 */
+#define FMC_BTR4_DATLAT_2 0x04000000U /*!<Bit 2 */
+#define FMC_BTR4_DATLAT_3 0x08000000U /*!<Bit 3 */
+
+#define FMC_BTR4_ACCMOD 0x30000000U /*!<ACCMOD[1:0] bits (Access mode) */
+#define FMC_BTR4_ACCMOD_0 0x10000000U /*!<Bit 0 */
+#define FMC_BTR4_ACCMOD_1 0x20000000U /*!<Bit 1 */
+
+/****************** Bit definition for FMC_BWTR1 register ******************/
+#define FMC_BWTR1_ADDSET 0x0000000FU /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FMC_BWTR1_ADDSET_0 0x00000001U /*!<Bit 0 */
+#define FMC_BWTR1_ADDSET_1 0x00000002U /*!<Bit 1 */
+#define FMC_BWTR1_ADDSET_2 0x00000004U /*!<Bit 2 */
+#define FMC_BWTR1_ADDSET_3 0x00000008U /*!<Bit 3 */
+
+#define FMC_BWTR1_ADDHLD 0x000000F0U /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FMC_BWTR1_ADDHLD_0 0x00000010U /*!<Bit 0 */
+#define FMC_BWTR1_ADDHLD_1 0x00000020U /*!<Bit 1 */
+#define FMC_BWTR1_ADDHLD_2 0x00000040U /*!<Bit 2 */
+#define FMC_BWTR1_ADDHLD_3 0x00000080U /*!<Bit 3 */
+
+#define FMC_BWTR1_DATAST 0x0000FF00U /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FMC_BWTR1_DATAST_0 0x00000100U /*!<Bit 0 */
+#define FMC_BWTR1_DATAST_1 0x00000200U /*!<Bit 1 */
+#define FMC_BWTR1_DATAST_2 0x00000400U /*!<Bit 2 */
+#define FMC_BWTR1_DATAST_3 0x00000800U /*!<Bit 3 */
+#define FMC_BWTR1_DATAST_4 0x00001000U /*!<Bit 4 */
+#define FMC_BWTR1_DATAST_5 0x00002000U /*!<Bit 5 */
+#define FMC_BWTR1_DATAST_6 0x00004000U /*!<Bit 6 */
+#define FMC_BWTR1_DATAST_7 0x00008000U /*!<Bit 7 */
+
+#define FMC_BWTR1_BUSTURN 0x000F0000U /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
+#define FMC_BWTR1_BUSTURN_0 0x00010000U /*!<Bit 0 */
+#define FMC_BWTR1_BUSTURN_1 0x00020000U /*!<Bit 1 */
+#define FMC_BWTR1_BUSTURN_2 0x00040000U /*!<Bit 2 */
+#define FMC_BWTR1_BUSTURN_3 0x00080000U /*!<Bit 3 */
+
+#define FMC_BWTR1_ACCMOD 0x30000000U /*!<ACCMOD[1:0] bits (Access mode) */
+#define FMC_BWTR1_ACCMOD_0 0x10000000U /*!<Bit 0 */
+#define FMC_BWTR1_ACCMOD_1 0x20000000U /*!<Bit 1 */
+
+/****************** Bit definition for FMC_BWTR2 register ******************/
+#define FMC_BWTR2_ADDSET 0x0000000FU /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FMC_BWTR2_ADDSET_0 0x00000001U /*!<Bit 0 */
+#define FMC_BWTR2_ADDSET_1 0x00000002U /*!<Bit 1 */
+#define FMC_BWTR2_ADDSET_2 0x00000004U /*!<Bit 2 */
+#define FMC_BWTR2_ADDSET_3 0x00000008U /*!<Bit 3 */
+
+#define FMC_BWTR2_ADDHLD 0x000000F0U /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FMC_BWTR2_ADDHLD_0 0x00000010U /*!<Bit 0 */
+#define FMC_BWTR2_ADDHLD_1 0x00000020U /*!<Bit 1 */
+#define FMC_BWTR2_ADDHLD_2 0x00000040U /*!<Bit 2 */
+#define FMC_BWTR2_ADDHLD_3 0x00000080U /*!<Bit 3 */
+
+#define FMC_BWTR2_DATAST 0x0000FF00U /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FMC_BWTR2_DATAST_0 0x00000100U /*!<Bit 0 */
+#define FMC_BWTR2_DATAST_1 0x00000200U /*!<Bit 1 */
+#define FMC_BWTR2_DATAST_2 0x00000400U /*!<Bit 2 */
+#define FMC_BWTR2_DATAST_3 0x00000800U /*!<Bit 3 */
+#define FMC_BWTR2_DATAST_4 0x00001000U /*!<Bit 4 */
+#define FMC_BWTR2_DATAST_5 0x00002000U /*!<Bit 5 */
+#define FMC_BWTR2_DATAST_6 0x00004000U /*!<Bit 6 */
+#define FMC_BWTR2_DATAST_7 0x00008000U /*!<Bit 7 */
+
+#define FMC_BWTR2_BUSTURN 0x000F0000U /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
+#define FMC_BWTR2_BUSTURN_0 0x00010000U /*!<Bit 0 */
+#define FMC_BWTR2_BUSTURN_1 0x00020000U /*!<Bit 1 */
+#define FMC_BWTR2_BUSTURN_2 0x00040000U /*!<Bit 2 */
+#define FMC_BWTR2_BUSTURN_3 0x00080000U /*!<Bit 3 */
+
+#define FMC_BWTR2_ACCMOD 0x30000000U /*!<ACCMOD[1:0] bits (Access mode) */
+#define FMC_BWTR2_ACCMOD_0 0x10000000U /*!<Bit 0 */
+#define FMC_BWTR2_ACCMOD_1 0x20000000U /*!<Bit 1 */
+
+/****************** Bit definition for FMC_BWTR3 register ******************/
+#define FMC_BWTR3_ADDSET 0x0000000FU /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FMC_BWTR3_ADDSET_0 0x00000001U /*!<Bit 0 */
+#define FMC_BWTR3_ADDSET_1 0x00000002U /*!<Bit 1 */
+#define FMC_BWTR3_ADDSET_2 0x00000004U /*!<Bit 2 */
+#define FMC_BWTR3_ADDSET_3 0x00000008U /*!<Bit 3 */
+
+#define FMC_BWTR3_ADDHLD 0x000000F0U /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FMC_BWTR3_ADDHLD_0 0x00000010U /*!<Bit 0 */
+#define FMC_BWTR3_ADDHLD_1 0x00000020U /*!<Bit 1 */
+#define FMC_BWTR3_ADDHLD_2 0x00000040U /*!<Bit 2 */
+#define FMC_BWTR3_ADDHLD_3 0x00000080U /*!<Bit 3 */
+
+#define FMC_BWTR3_DATAST 0x0000FF00U /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FMC_BWTR3_DATAST_0 0x00000100U /*!<Bit 0 */
+#define FMC_BWTR3_DATAST_1 0x00000200U /*!<Bit 1 */
+#define FMC_BWTR3_DATAST_2 0x00000400U /*!<Bit 2 */
+#define FMC_BWTR3_DATAST_3 0x00000800U /*!<Bit 3 */
+#define FMC_BWTR3_DATAST_4 0x00001000U /*!<Bit 4 */
+#define FMC_BWTR3_DATAST_5 0x00002000U /*!<Bit 5 */
+#define FMC_BWTR3_DATAST_6 0x00004000U /*!<Bit 6 */
+#define FMC_BWTR3_DATAST_7 0x00008000U /*!<Bit 7 */
+
+#define FMC_BWTR3_BUSTURN 0x000F0000U /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
+#define FMC_BWTR3_BUSTURN_0 0x00010000U /*!<Bit 0 */
+#define FMC_BWTR3_BUSTURN_1 0x00020000U /*!<Bit 1 */
+#define FMC_BWTR3_BUSTURN_2 0x00040000U /*!<Bit 2 */
+#define FMC_BWTR3_BUSTURN_3 0x00080000U /*!<Bit 3 */
+
+#define FMC_BWTR3_ACCMOD 0x30000000U /*!<ACCMOD[1:0] bits (Access mode) */
+#define FMC_BWTR3_ACCMOD_0 0x10000000U /*!<Bit 0 */
+#define FMC_BWTR3_ACCMOD_1 0x20000000U /*!<Bit 1 */
+
+/****************** Bit definition for FMC_BWTR4 register ******************/
+#define FMC_BWTR4_ADDSET 0x0000000FU /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FMC_BWTR4_ADDSET_0 0x00000001U /*!<Bit 0 */
+#define FMC_BWTR4_ADDSET_1 0x00000002U /*!<Bit 1 */
+#define FMC_BWTR4_ADDSET_2 0x00000004U /*!<Bit 2 */
+#define FMC_BWTR4_ADDSET_3 0x00000008U /*!<Bit 3 */
+
+#define FMC_BWTR4_ADDHLD 0x000000F0U /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FMC_BWTR4_ADDHLD_0 0x00000010U /*!<Bit 0 */
+#define FMC_BWTR4_ADDHLD_1 0x00000020U /*!<Bit 1 */
+#define FMC_BWTR4_ADDHLD_2 0x00000040U /*!<Bit 2 */
+#define FMC_BWTR4_ADDHLD_3 0x00000080U /*!<Bit 3 */
+
+#define FMC_BWTR4_DATAST 0x0000FF00U /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FMC_BWTR4_DATAST_0 0x00000100U /*!<Bit 0 */
+#define FMC_BWTR4_DATAST_1 0x00000200U /*!<Bit 1 */
+#define FMC_BWTR4_DATAST_2 0x00000400U /*!<Bit 2 */
+#define FMC_BWTR4_DATAST_3 0x00000800U /*!<Bit 3 */
+#define FMC_BWTR4_DATAST_4 0x00001000U /*!<Bit 4 */
+#define FMC_BWTR4_DATAST_5 0x00002000U /*!<Bit 5 */
+#define FMC_BWTR4_DATAST_6 0x00004000U /*!<Bit 6 */
+#define FMC_BWTR4_DATAST_7 0x00008000U /*!<Bit 7 */
+
+#define FMC_BWTR4_BUSTURN 0x000F0000U /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
+#define FMC_BWTR4_BUSTURN_0 0x00010000U /*!<Bit 0 */
+#define FMC_BWTR4_BUSTURN_1 0x00020000U /*!<Bit 1 */
+#define FMC_BWTR4_BUSTURN_2 0x00040000U /*!<Bit 2 */
+#define FMC_BWTR4_BUSTURN_3 0x00080000U /*!<Bit 3 */
+
+#define FMC_BWTR4_ACCMOD 0x30000000U /*!<ACCMOD[1:0] bits (Access mode) */
+#define FMC_BWTR4_ACCMOD_0 0x10000000U /*!<Bit 0 */
+#define FMC_BWTR4_ACCMOD_1 0x20000000U /*!<Bit 1 */
+
+/****************** Bit definition for FMC_PCR2 register *******************/
+#define FMC_PCR2_PWAITEN 0x00000002U /*!<Wait feature enable bit */
+#define FMC_PCR2_PBKEN 0x00000004U /*!<PC Card/NAND Flash memory bank enable bit */
+#define FMC_PCR2_PTYP 0x00000008U /*!<Memory type */
+
+#define FMC_PCR2_PWID 0x00000030U /*!<PWID[1:0] bits (NAND Flash databus width) */
+#define FMC_PCR2_PWID_0 0x00000010U /*!<Bit 0 */
+#define FMC_PCR2_PWID_1 0x00000020U /*!<Bit 1 */
+
+#define FMC_PCR2_ECCEN 0x00000040U /*!<ECC computation logic enable bit */
+
+#define FMC_PCR2_TCLR 0x00001E00U /*!<TCLR[3:0] bits (CLE to RE delay) */
+#define FMC_PCR2_TCLR_0 0x00000200U /*!<Bit 0 */
+#define FMC_PCR2_TCLR_1 0x00000400U /*!<Bit 1 */
+#define FMC_PCR2_TCLR_2 0x00000800U /*!<Bit 2 */
+#define FMC_PCR2_TCLR_3 0x00001000U /*!<Bit 3 */
+
+#define FMC_PCR2_TAR 0x0001E000U /*!<TAR[3:0] bits (ALE to RE delay) */
+#define FMC_PCR2_TAR_0 0x00002000U /*!<Bit 0 */
+#define FMC_PCR2_TAR_1 0x00004000U /*!<Bit 1 */
+#define FMC_PCR2_TAR_2 0x00008000U /*!<Bit 2 */
+#define FMC_PCR2_TAR_3 0x00010000U /*!<Bit 3 */
+
+#define FMC_PCR2_ECCPS 0x000E0000U /*!<ECCPS[1:0] bits (ECC page size) */
+#define FMC_PCR2_ECCPS_0 0x00020000U /*!<Bit 0 */
+#define FMC_PCR2_ECCPS_1 0x00040000U /*!<Bit 1 */
+#define FMC_PCR2_ECCPS_2 0x00080000U /*!<Bit 2 */
+
+/****************** Bit definition for FMC_PCR3 register *******************/
+#define FMC_PCR3_PWAITEN 0x00000002U /*!<Wait feature enable bit */
+#define FMC_PCR3_PBKEN 0x00000004U /*!<PC Card/NAND Flash memory bank enable bit */
+#define FMC_PCR3_PTYP 0x00000008U /*!<Memory type */
+
+#define FMC_PCR3_PWID 0x00000030U /*!<PWID[1:0] bits (NAND Flash databus width) */
+#define FMC_PCR3_PWID_0 0x00000010U /*!<Bit 0 */
+#define FMC_PCR3_PWID_1 0x00000020U /*!<Bit 1 */
+
+#define FMC_PCR3_ECCEN 0x00000040U /*!<ECC computation logic enable bit */
+
+#define FMC_PCR3_TCLR 0x00001E00U /*!<TCLR[3:0] bits (CLE to RE delay) */
+#define FMC_PCR3_TCLR_0 0x00000200U /*!<Bit 0 */
+#define FMC_PCR3_TCLR_1 0x00000400U /*!<Bit 1 */
+#define FMC_PCR3_TCLR_2 0x00000800U /*!<Bit 2 */
+#define FMC_PCR3_TCLR_3 0x00001000U /*!<Bit 3 */
+
+#define FMC_PCR3_TAR 0x0001E000U /*!<TAR[3:0] bits (ALE to RE delay) */
+#define FMC_PCR3_TAR_0 0x00002000U /*!<Bit 0 */
+#define FMC_PCR3_TAR_1 0x00004000U /*!<Bit 1 */
+#define FMC_PCR3_TAR_2 0x00008000U /*!<Bit 2 */
+#define FMC_PCR3_TAR_3 0x00010000U /*!<Bit 3 */
+
+#define FMC_PCR3_ECCPS 0x000E0000U /*!<ECCPS[2:0] bits (ECC page size) */
+#define FMC_PCR3_ECCPS_0 0x00020000U /*!<Bit 0 */
+#define FMC_PCR3_ECCPS_1 0x00040000U /*!<Bit 1 */
+#define FMC_PCR3_ECCPS_2 0x00080000U /*!<Bit 2 */
+
+/****************** Bit definition for FMC_PCR4 register *******************/
+#define FMC_PCR4_PWAITEN 0x00000002U /*!<Wait feature enable bit */
+#define FMC_PCR4_PBKEN 0x00000004U /*!<PC Card/NAND Flash memory bank enable bit */
+#define FMC_PCR4_PTYP 0x00000008U /*!<Memory type */
+
+#define FMC_PCR4_PWID 0x00000030U /*!<PWID[1:0] bits (NAND Flash databus width) */
+#define FMC_PCR4_PWID_0 0x00000010U /*!<Bit 0 */
+#define FMC_PCR4_PWID_1 0x00000020U /*!<Bit 1 */
+
+#define FMC_PCR4_ECCEN 0x00000040U /*!<ECC computation logic enable bit */
+
+#define FMC_PCR4_TCLR 0x00001E00U /*!<TCLR[3:0] bits (CLE to RE delay) */
+#define FMC_PCR4_TCLR_0 0x00000200U /*!<Bit 0 */
+#define FMC_PCR4_TCLR_1 0x00000400U /*!<Bit 1 */
+#define FMC_PCR4_TCLR_2 0x00000800U /*!<Bit 2 */
+#define FMC_PCR4_TCLR_3 0x00001000U /*!<Bit 3 */
+
+#define FMC_PCR4_TAR 0x0001E000U /*!<TAR[3:0] bits (ALE to RE delay) */
+#define FMC_PCR4_TAR_0 0x00002000U /*!<Bit 0 */
+#define FMC_PCR4_TAR_1 0x00004000U /*!<Bit 1 */
+#define FMC_PCR4_TAR_2 0x00008000U /*!<Bit 2 */
+#define FMC_PCR4_TAR_3 0x00010000U /*!<Bit 3 */
+
+#define FMC_PCR4_ECCPS 0x000E0000U /*!<ECCPS[2:0] bits (ECC page size) */
+#define FMC_PCR4_ECCPS_0 0x00020000U /*!<Bit 0 */
+#define FMC_PCR4_ECCPS_1 0x00040000U /*!<Bit 1 */
+#define FMC_PCR4_ECCPS_2 0x00080000U /*!<Bit 2 */
+
+/******************* Bit definition for FMC_SR2 register *******************/
+#define FMC_SR2_IRS 0x01U /*!<Interrupt Rising Edge status */
+#define FMC_SR2_ILS 0x02U /*!<Interrupt Level status */
+#define FMC_SR2_IFS 0x04U /*!<Interrupt Falling Edge status */
+#define FMC_SR2_IREN 0x08U /*!<Interrupt Rising Edge detection Enable bit */
+#define FMC_SR2_ILEN 0x10U /*!<Interrupt Level detection Enable bit */
+#define FMC_SR2_IFEN 0x20U /*!<Interrupt Falling Edge detection Enable bit */
+#define FMC_SR2_FEMPT 0x40U /*!<FIFO empty */
+
+/******************* Bit definition for FMC_SR3 register *******************/
+#define FMC_SR3_IRS 0x01U /*!<Interrupt Rising Edge status */
+#define FMC_SR3_ILS 0x02U /*!<Interrupt Level status */
+#define FMC_SR3_IFS 0x04U /*!<Interrupt Falling Edge status */
+#define FMC_SR3_IREN 0x08U /*!<Interrupt Rising Edge detection Enable bit */
+#define FMC_SR3_ILEN 0x10U /*!<Interrupt Level detection Enable bit */
+#define FMC_SR3_IFEN 0x20U /*!<Interrupt Falling Edge detection Enable bit */
+#define FMC_SR3_FEMPT 0x40U /*!<FIFO empty */
+
+/******************* Bit definition for FMC_SR4 register *******************/
+#define FMC_SR4_IRS 0x01U /*!<Interrupt Rising Edge status */
+#define FMC_SR4_ILS 0x02U /*!<Interrupt Level status */
+#define FMC_SR4_IFS 0x04U /*!<Interrupt Falling Edge status */
+#define FMC_SR4_IREN 0x08U /*!<Interrupt Rising Edge detection Enable bit */
+#define FMC_SR4_ILEN 0x10U /*!<Interrupt Level detection Enable bit */
+#define FMC_SR4_IFEN 0x20U /*!<Interrupt Falling Edge detection Enable bit */
+#define FMC_SR4_FEMPT 0x40U /*!<FIFO empty */
+
+/****************** Bit definition for FMC_PMEM2 register ******************/
+#define FMC_PMEM2_MEMSET2 0x000000FFU /*!<MEMSET2[7:0] bits (Common memory 2 setup time) */
+#define FMC_PMEM2_MEMSET2_0 0x00000001U /*!<Bit 0 */
+#define FMC_PMEM2_MEMSET2_1 0x00000002U /*!<Bit 1 */
+#define FMC_PMEM2_MEMSET2_2 0x00000004U /*!<Bit 2 */
+#define FMC_PMEM2_MEMSET2_3 0x00000008U /*!<Bit 3 */
+#define FMC_PMEM2_MEMSET2_4 0x00000010U /*!<Bit 4 */
+#define FMC_PMEM2_MEMSET2_5 0x00000020U /*!<Bit 5 */
+#define FMC_PMEM2_MEMSET2_6 0x00000040U /*!<Bit 6 */
+#define FMC_PMEM2_MEMSET2_7 0x00000080U /*!<Bit 7 */
+
+#define FMC_PMEM2_MEMWAIT2 0x0000FF00U /*!<MEMWAIT2[7:0] bits (Common memory 2 wait time) */
+#define FMC_PMEM2_MEMWAIT2_0 0x00000100U /*!<Bit 0 */
+#define FMC_PMEM2_MEMWAIT2_1 0x00000200U /*!<Bit 1 */
+#define FMC_PMEM2_MEMWAIT2_2 0x00000400U /*!<Bit 2 */
+#define FMC_PMEM2_MEMWAIT2_3 0x00000800U /*!<Bit 3 */
+#define FMC_PMEM2_MEMWAIT2_4 0x00001000U /*!<Bit 4 */
+#define FMC_PMEM2_MEMWAIT2_5 0x00002000U /*!<Bit 5 */
+#define FMC_PMEM2_MEMWAIT2_6 0x00004000U /*!<Bit 6 */
+#define FMC_PMEM2_MEMWAIT2_7 0x00008000U /*!<Bit 7 */
+
+#define FMC_PMEM2_MEMHOLD2 0x00FF0000U /*!<MEMHOLD2[7:0] bits (Common memory 2 hold time) */
+#define FMC_PMEM2_MEMHOLD2_0 0x00010000U /*!<Bit 0 */
+#define FMC_PMEM2_MEMHOLD2_1 0x00020000U /*!<Bit 1 */
+#define FMC_PMEM2_MEMHOLD2_2 0x00040000U /*!<Bit 2 */
+#define FMC_PMEM2_MEMHOLD2_3 0x00080000U /*!<Bit 3 */
+#define FMC_PMEM2_MEMHOLD2_4 0x00100000U /*!<Bit 4 */
+#define FMC_PMEM2_MEMHOLD2_5 0x00200000U /*!<Bit 5 */
+#define FMC_PMEM2_MEMHOLD2_6 0x00400000U /*!<Bit 6 */
+#define FMC_PMEM2_MEMHOLD2_7 0x00800000U /*!<Bit 7 */
+
+#define FMC_PMEM2_MEMHIZ2 0xFF000000U /*!<MEMHIZ2[7:0] bits (Common memory 2 databus HiZ time) */
+#define FMC_PMEM2_MEMHIZ2_0 0x01000000U /*!<Bit 0 */
+#define FMC_PMEM2_MEMHIZ2_1 0x02000000U /*!<Bit 1 */
+#define FMC_PMEM2_MEMHIZ2_2 0x04000000U /*!<Bit 2 */
+#define FMC_PMEM2_MEMHIZ2_3 0x08000000U /*!<Bit 3 */
+#define FMC_PMEM2_MEMHIZ2_4 0x10000000U /*!<Bit 4 */
+#define FMC_PMEM2_MEMHIZ2_5 0x20000000U /*!<Bit 5 */
+#define FMC_PMEM2_MEMHIZ2_6 0x40000000U /*!<Bit 6 */
+#define FMC_PMEM2_MEMHIZ2_7 0x80000000U /*!<Bit 7 */
+
+/****************** Bit definition for FMC_PMEM3 register ******************/
+#define FMC_PMEM3_MEMSET3 0x000000FFU /*!<MEMSET3[7:0] bits (Common memory 3 setup time) */
+#define FMC_PMEM3_MEMSET3_0 0x00000001U /*!<Bit 0 */
+#define FMC_PMEM3_MEMSET3_1 0x00000002U /*!<Bit 1 */
+#define FMC_PMEM3_MEMSET3_2 0x00000004U /*!<Bit 2 */
+#define FMC_PMEM3_MEMSET3_3 0x00000008U /*!<Bit 3 */
+#define FMC_PMEM3_MEMSET3_4 0x00000010U /*!<Bit 4 */
+#define FMC_PMEM3_MEMSET3_5 0x00000020U /*!<Bit 5 */
+#define FMC_PMEM3_MEMSET3_6 0x00000040U /*!<Bit 6 */
+#define FMC_PMEM3_MEMSET3_7 0x00000080U /*!<Bit 7 */
+
+#define FMC_PMEM3_MEMWAIT3 0x0000FF00U /*!<MEMWAIT3[7:0] bits (Common memory 3 wait time) */
+#define FMC_PMEM3_MEMWAIT3_0 0x00000100U /*!<Bit 0 */
+#define FMC_PMEM3_MEMWAIT3_1 0x00000200U /*!<Bit 1 */
+#define FMC_PMEM3_MEMWAIT3_2 0x00000400U /*!<Bit 2 */
+#define FMC_PMEM3_MEMWAIT3_3 0x00000800U /*!<Bit 3 */
+#define FMC_PMEM3_MEMWAIT3_4 0x00001000U /*!<Bit 4 */
+#define FMC_PMEM3_MEMWAIT3_5 0x00002000U /*!<Bit 5 */
+#define FMC_PMEM3_MEMWAIT3_6 0x00004000U /*!<Bit 6 */
+#define FMC_PMEM3_MEMWAIT3_7 0x00008000U /*!<Bit 7 */
+
+#define FMC_PMEM3_MEMHOLD3 0x00FF0000U /*!<MEMHOLD3[7:0] bits (Common memory 3 hold time) */
+#define FMC_PMEM3_MEMHOLD3_0 0x00010000U /*!<Bit 0 */
+#define FMC_PMEM3_MEMHOLD3_1 0x00020000U /*!<Bit 1 */
+#define FMC_PMEM3_MEMHOLD3_2 0x00040000U /*!<Bit 2 */
+#define FMC_PMEM3_MEMHOLD3_3 0x00080000U /*!<Bit 3 */
+#define FMC_PMEM3_MEMHOLD3_4 0x00100000U /*!<Bit 4 */
+#define FMC_PMEM3_MEMHOLD3_5 0x00200000U /*!<Bit 5 */
+#define FMC_PMEM3_MEMHOLD3_6 0x00400000U /*!<Bit 6 */
+#define FMC_PMEM3_MEMHOLD3_7 0x00800000U /*!<Bit 7 */
+
+#define FMC_PMEM3_MEMHIZ3 0xFF000000U /*!<MEMHIZ3[7:0] bits (Common memory 3 databus HiZ time) */
+#define FMC_PMEM3_MEMHIZ3_0 0x01000000U /*!<Bit 0 */
+#define FMC_PMEM3_MEMHIZ3_1 0x02000000U /*!<Bit 1 */
+#define FMC_PMEM3_MEMHIZ3_2 0x04000000U /*!<Bit 2 */
+#define FMC_PMEM3_MEMHIZ3_3 0x08000000U /*!<Bit 3 */
+#define FMC_PMEM3_MEMHIZ3_4 0x10000000U /*!<Bit 4 */
+#define FMC_PMEM3_MEMHIZ3_5 0x20000000U /*!<Bit 5 */
+#define FMC_PMEM3_MEMHIZ3_6 0x40000000U /*!<Bit 6 */
+#define FMC_PMEM3_MEMHIZ3_7 0x80000000U /*!<Bit 7 */
+
+/****************** Bit definition for FMC_PMEM4 register ******************/
+#define FMC_PMEM4_MEMSET4 0x000000FFU /*!<MEMSET4[7:0] bits (Common memory 4 setup time) */
+#define FMC_PMEM4_MEMSET4_0 0x00000001U /*!<Bit 0 */
+#define FMC_PMEM4_MEMSET4_1 0x00000002U /*!<Bit 1 */
+#define FMC_PMEM4_MEMSET4_2 0x00000004U /*!<Bit 2 */
+#define FMC_PMEM4_MEMSET4_3 0x00000008U /*!<Bit 3 */
+#define FMC_PMEM4_MEMSET4_4 0x00000010U /*!<Bit 4 */
+#define FMC_PMEM4_MEMSET4_5 0x00000020U /*!<Bit 5 */
+#define FMC_PMEM4_MEMSET4_6 0x00000040U /*!<Bit 6 */
+#define FMC_PMEM4_MEMSET4_7 0x00000080U /*!<Bit 7 */
+
+#define FMC_PMEM4_MEMWAIT4 0x0000FF00U /*!<MEMWAIT4[7:0] bits (Common memory 4 wait time) */
+#define FMC_PMEM4_MEMWAIT4_0 0x00000100U /*!<Bit 0 */
+#define FMC_PMEM4_MEMWAIT4_1 0x00000200U /*!<Bit 1 */
+#define FMC_PMEM4_MEMWAIT4_2 0x00000400U /*!<Bit 2 */
+#define FMC_PMEM4_MEMWAIT4_3 0x00000800U /*!<Bit 3 */
+#define FMC_PMEM4_MEMWAIT4_4 0x00001000U /*!<Bit 4 */
+#define FMC_PMEM4_MEMWAIT4_5 0x00002000U /*!<Bit 5 */
+#define FMC_PMEM4_MEMWAIT4_6 0x00004000U /*!<Bit 6 */
+#define FMC_PMEM4_MEMWAIT4_7 0x00008000U /*!<Bit 7 */
+
+#define FMC_PMEM4_MEMHOLD4 0x00FF0000U /*!<MEMHOLD4[7:0] bits (Common memory 4 hold time) */
+#define FMC_PMEM4_MEMHOLD4_0 0x00010000U /*!<Bit 0 */
+#define FMC_PMEM4_MEMHOLD4_1 0x00020000U /*!<Bit 1 */
+#define FMC_PMEM4_MEMHOLD4_2 0x00040000U /*!<Bit 2 */
+#define FMC_PMEM4_MEMHOLD4_3 0x00080000U /*!<Bit 3 */
+#define FMC_PMEM4_MEMHOLD4_4 0x00100000U /*!<Bit 4 */
+#define FMC_PMEM4_MEMHOLD4_5 0x00200000U /*!<Bit 5 */
+#define FMC_PMEM4_MEMHOLD4_6 0x00400000U /*!<Bit 6 */
+#define FMC_PMEM4_MEMHOLD4_7 0x00800000U /*!<Bit 7 */
+
+#define FMC_PMEM4_MEMHIZ4 0xFF000000U /*!<MEMHIZ4[7:0] bits (Common memory 4 databus HiZ time) */
+#define FMC_PMEM4_MEMHIZ4_0 0x01000000U /*!<Bit 0 */
+#define FMC_PMEM4_MEMHIZ4_1 0x02000000U /*!<Bit 1 */
+#define FMC_PMEM4_MEMHIZ4_2 0x04000000U /*!<Bit 2 */
+#define FMC_PMEM4_MEMHIZ4_3 0x08000000U /*!<Bit 3 */
+#define FMC_PMEM4_MEMHIZ4_4 0x10000000U /*!<Bit 4 */
+#define FMC_PMEM4_MEMHIZ4_5 0x20000000U /*!<Bit 5 */
+#define FMC_PMEM4_MEMHIZ4_6 0x40000000U /*!<Bit 6 */
+#define FMC_PMEM4_MEMHIZ4_7 0x80000000U /*!<Bit 7 */
+
+/****************** Bit definition for FMC_PATT2 register ******************/
+#define FMC_PATT2_ATTSET2 0x000000FFU /*!<ATTSET2[7:0] bits (Attribute memory 2 setup time) */
+#define FMC_PATT2_ATTSET2_0 0x00000001U /*!<Bit 0 */
+#define FMC_PATT2_ATTSET2_1 0x00000002U /*!<Bit 1 */
+#define FMC_PATT2_ATTSET2_2 0x00000004U /*!<Bit 2 */
+#define FMC_PATT2_ATTSET2_3 0x00000008U /*!<Bit 3 */
+#define FMC_PATT2_ATTSET2_4 0x00000010U /*!<Bit 4 */
+#define FMC_PATT2_ATTSET2_5 0x00000020U /*!<Bit 5 */
+#define FMC_PATT2_ATTSET2_6 0x00000040U /*!<Bit 6 */
+#define FMC_PATT2_ATTSET2_7 0x00000080U /*!<Bit 7 */
+
+#define FMC_PATT2_ATTWAIT2 0x0000FF00U /*!<ATTWAIT2[7:0] bits (Attribute memory 2 wait time) */
+#define FMC_PATT2_ATTWAIT2_0 0x00000100U /*!<Bit 0 */
+#define FMC_PATT2_ATTWAIT2_1 0x00000200U /*!<Bit 1 */
+#define FMC_PATT2_ATTWAIT2_2 0x00000400U /*!<Bit 2 */
+#define FMC_PATT2_ATTWAIT2_3 0x00000800U /*!<Bit 3 */
+#define FMC_PATT2_ATTWAIT2_4 0x00001000U /*!<Bit 4 */
+#define FMC_PATT2_ATTWAIT2_5 0x00002000U /*!<Bit 5 */
+#define FMC_PATT2_ATTWAIT2_6 0x00004000U /*!<Bit 6 */
+#define FMC_PATT2_ATTWAIT2_7 0x00008000U /*!<Bit 7 */
+
+#define FMC_PATT2_ATTHOLD2 0x00FF0000U /*!<ATTHOLD2[7:0] bits (Attribute memory 2 hold time) */
+#define FMC_PATT2_ATTHOLD2_0 0x00010000U /*!<Bit 0 */
+#define FMC_PATT2_ATTHOLD2_1 0x00020000U /*!<Bit 1 */
+#define FMC_PATT2_ATTHOLD2_2 0x00040000U /*!<Bit 2 */
+#define FMC_PATT2_ATTHOLD2_3 0x00080000U /*!<Bit 3 */
+#define FMC_PATT2_ATTHOLD2_4 0x00100000U /*!<Bit 4 */
+#define FMC_PATT2_ATTHOLD2_5 0x00200000U /*!<Bit 5 */
+#define FMC_PATT2_ATTHOLD2_6 0x00400000U /*!<Bit 6 */
+#define FMC_PATT2_ATTHOLD2_7 0x00800000U /*!<Bit 7 */
+
+#define FMC_PATT2_ATTHIZ2 0xFF000000U /*!<ATTHIZ2[7:0] bits (Attribute memory 2 databus HiZ time) */
+#define FMC_PATT2_ATTHIZ2_0 0x01000000U /*!<Bit 0 */
+#define FMC_PATT2_ATTHIZ2_1 0x02000000U /*!<Bit 1 */
+#define FMC_PATT2_ATTHIZ2_2 0x04000000U /*!<Bit 2 */
+#define FMC_PATT2_ATTHIZ2_3 0x08000000U /*!<Bit 3 */
+#define FMC_PATT2_ATTHIZ2_4 0x10000000U /*!<Bit 4 */
+#define FMC_PATT2_ATTHIZ2_5 0x20000000U /*!<Bit 5 */
+#define FMC_PATT2_ATTHIZ2_6 0x40000000U /*!<Bit 6 */
+#define FMC_PATT2_ATTHIZ2_7 0x80000000U /*!<Bit 7 */
+
+/****************** Bit definition for FMC_PATT3 register ******************/
+#define FMC_PATT3_ATTSET3 0x000000FFU /*!<ATTSET3[7:0] bits (Attribute memory 3 setup time) */
+#define FMC_PATT3_ATTSET3_0 0x00000001U /*!<Bit 0 */
+#define FMC_PATT3_ATTSET3_1 0x00000002U /*!<Bit 1 */
+#define FMC_PATT3_ATTSET3_2 0x00000004U /*!<Bit 2 */
+#define FMC_PATT3_ATTSET3_3 0x00000008U /*!<Bit 3 */
+#define FMC_PATT3_ATTSET3_4 0x00000010U /*!<Bit 4 */
+#define FMC_PATT3_ATTSET3_5 0x00000020U /*!<Bit 5 */
+#define FMC_PATT3_ATTSET3_6 0x00000040U /*!<Bit 6 */
+#define FMC_PATT3_ATTSET3_7 0x00000080U /*!<Bit 7 */
+
+#define FMC_PATT3_ATTWAIT3 0x0000FF00U /*!<ATTWAIT3[7:0] bits (Attribute memory 3 wait time) */
+#define FMC_PATT3_ATTWAIT3_0 0x00000100U /*!<Bit 0 */
+#define FMC_PATT3_ATTWAIT3_1 0x00000200U /*!<Bit 1 */
+#define FMC_PATT3_ATTWAIT3_2 0x00000400U /*!<Bit 2 */
+#define FMC_PATT3_ATTWAIT3_3 0x00000800U /*!<Bit 3 */
+#define FMC_PATT3_ATTWAIT3_4 0x00001000U /*!<Bit 4 */
+#define FMC_PATT3_ATTWAIT3_5 0x00002000U /*!<Bit 5 */
+#define FMC_PATT3_ATTWAIT3_6 0x00004000U /*!<Bit 6 */
+#define FMC_PATT3_ATTWAIT3_7 0x00008000U /*!<Bit 7 */
+
+#define FMC_PATT3_ATTHOLD3 0x00FF0000U /*!<ATTHOLD3[7:0] bits (Attribute memory 3 hold time) */
+#define FMC_PATT3_ATTHOLD3_0 0x00010000U /*!<Bit 0 */
+#define FMC_PATT3_ATTHOLD3_1 0x00020000U /*!<Bit 1 */
+#define FMC_PATT3_ATTHOLD3_2 0x00040000U /*!<Bit 2 */
+#define FMC_PATT3_ATTHOLD3_3 0x00080000U /*!<Bit 3 */
+#define FMC_PATT3_ATTHOLD3_4 0x00100000U /*!<Bit 4 */
+#define FMC_PATT3_ATTHOLD3_5 0x00200000U /*!<Bit 5 */
+#define FMC_PATT3_ATTHOLD3_6 0x00400000U /*!<Bit 6 */
+#define FMC_PATT3_ATTHOLD3_7 0x00800000U /*!<Bit 7 */
+
+#define FMC_PATT3_ATTHIZ3 0xFF000000U /*!<ATTHIZ3[7:0] bits (Attribute memory 3 databus HiZ time) */
+#define FMC_PATT3_ATTHIZ3_0 0x01000000U /*!<Bit 0 */
+#define FMC_PATT3_ATTHIZ3_1 0x02000000U /*!<Bit 1 */
+#define FMC_PATT3_ATTHIZ3_2 0x04000000U /*!<Bit 2 */
+#define FMC_PATT3_ATTHIZ3_3 0x08000000U /*!<Bit 3 */
+#define FMC_PATT3_ATTHIZ3_4 0x10000000U /*!<Bit 4 */
+#define FMC_PATT3_ATTHIZ3_5 0x20000000U /*!<Bit 5 */
+#define FMC_PATT3_ATTHIZ3_6 0x40000000U /*!<Bit 6 */
+#define FMC_PATT3_ATTHIZ3_7 0x80000000U /*!<Bit 7 */
+
+/****************** Bit definition for FMC_PATT4 register ******************/
+#define FMC_PATT4_ATTSET4 0x000000FFU /*!<ATTSET4[7:0] bits (Attribute memory 4 setup time) */
+#define FMC_PATT4_ATTSET4_0 0x00000001U /*!<Bit 0 */
+#define FMC_PATT4_ATTSET4_1 0x00000002U /*!<Bit 1 */
+#define FMC_PATT4_ATTSET4_2 0x00000004U /*!<Bit 2 */
+#define FMC_PATT4_ATTSET4_3 0x00000008U /*!<Bit 3 */
+#define FMC_PATT4_ATTSET4_4 0x00000010U /*!<Bit 4 */
+#define FMC_PATT4_ATTSET4_5 0x00000020U /*!<Bit 5 */
+#define FMC_PATT4_ATTSET4_6 0x00000040U /*!<Bit 6 */
+#define FMC_PATT4_ATTSET4_7 0x00000080U /*!<Bit 7 */
+
+#define FMC_PATT4_ATTWAIT4 0x0000FF00U /*!<ATTWAIT4[7:0] bits (Attribute memory 4 wait time) */
+#define FMC_PATT4_ATTWAIT4_0 0x00000100U /*!<Bit 0 */
+#define FMC_PATT4_ATTWAIT4_1 0x00000200U /*!<Bit 1 */
+#define FMC_PATT4_ATTWAIT4_2 0x00000400U /*!<Bit 2 */
+#define FMC_PATT4_ATTWAIT4_3 0x00000800U /*!<Bit 3 */
+#define FMC_PATT4_ATTWAIT4_4 0x00001000U /*!<Bit 4 */
+#define FMC_PATT4_ATTWAIT4_5 0x00002000U /*!<Bit 5 */
+#define FMC_PATT4_ATTWAIT4_6 0x00004000U /*!<Bit 6 */
+#define FMC_PATT4_ATTWAIT4_7 0x00008000U /*!<Bit 7 */
+
+#define FMC_PATT4_ATTHOLD4 0x00FF0000U /*!<ATTHOLD4[7:0] bits (Attribute memory 4 hold time) */
+#define FMC_PATT4_ATTHOLD4_0 0x00010000U /*!<Bit 0 */
+#define FMC_PATT4_ATTHOLD4_1 0x00020000U /*!<Bit 1 */
+#define FMC_PATT4_ATTHOLD4_2 0x00040000U /*!<Bit 2 */
+#define FMC_PATT4_ATTHOLD4_3 0x00080000U /*!<Bit 3 */
+#define FMC_PATT4_ATTHOLD4_4 0x00100000U /*!<Bit 4 */
+#define FMC_PATT4_ATTHOLD4_5 0x00200000U /*!<Bit 5 */
+#define FMC_PATT4_ATTHOLD4_6 0x00400000U /*!<Bit 6 */
+#define FMC_PATT4_ATTHOLD4_7 0x00800000U /*!<Bit 7 */
+
+#define FMC_PATT4_ATTHIZ4 0xFF000000U /*!<ATTHIZ4[7:0] bits (Attribute memory 4 databus HiZ time) */
+#define FMC_PATT4_ATTHIZ4_0 0x01000000U /*!<Bit 0 */
+#define FMC_PATT4_ATTHIZ4_1 0x02000000U /*!<Bit 1 */
+#define FMC_PATT4_ATTHIZ4_2 0x04000000U /*!<Bit 2 */
+#define FMC_PATT4_ATTHIZ4_3 0x08000000U /*!<Bit 3 */
+#define FMC_PATT4_ATTHIZ4_4 0x10000000U /*!<Bit 4 */
+#define FMC_PATT4_ATTHIZ4_5 0x20000000U /*!<Bit 5 */
+#define FMC_PATT4_ATTHIZ4_6 0x40000000U /*!<Bit 6 */
+#define FMC_PATT4_ATTHIZ4_7 0x80000000U /*!<Bit 7 */
+
+/****************** Bit definition for FMC_PIO4 register *******************/
+#define FMC_PIO4_IOSET4 0x000000FFU /*!<IOSET4[7:0] bits (I/O 4 setup time) */
+#define FMC_PIO4_IOSET4_0 0x00000001U /*!<Bit 0 */
+#define FMC_PIO4_IOSET4_1 0x00000002U /*!<Bit 1 */
+#define FMC_PIO4_IOSET4_2 0x00000004U /*!<Bit 2 */
+#define FMC_PIO4_IOSET4_3 0x00000008U /*!<Bit 3 */
+#define FMC_PIO4_IOSET4_4 0x00000010U /*!<Bit 4 */
+#define FMC_PIO4_IOSET4_5 0x00000020U /*!<Bit 5 */
+#define FMC_PIO4_IOSET4_6 0x00000040U /*!<Bit 6 */
+#define FMC_PIO4_IOSET4_7 0x00000080U /*!<Bit 7 */
+
+#define FMC_PIO4_IOWAIT4 0x0000FF00U /*!<IOWAIT4[7:0] bits (I/O 4 wait time) */
+#define FMC_PIO4_IOWAIT4_0 0x00000100U /*!<Bit 0 */
+#define FMC_PIO4_IOWAIT4_1 0x00000200U /*!<Bit 1 */
+#define FMC_PIO4_IOWAIT4_2 0x00000400U /*!<Bit 2 */
+#define FMC_PIO4_IOWAIT4_3 0x00000800U /*!<Bit 3 */
+#define FMC_PIO4_IOWAIT4_4 0x00001000U /*!<Bit 4 */
+#define FMC_PIO4_IOWAIT4_5 0x00002000U /*!<Bit 5 */
+#define FMC_PIO4_IOWAIT4_6 0x00004000U /*!<Bit 6 */
+#define FMC_PIO4_IOWAIT4_7 0x00008000U /*!<Bit 7 */
+
+#define FMC_PIO4_IOHOLD4 0x00FF0000U /*!<IOHOLD4[7:0] bits (I/O 4 hold time) */
+#define FMC_PIO4_IOHOLD4_0 0x00010000U /*!<Bit 0 */
+#define FMC_PIO4_IOHOLD4_1 0x00020000U /*!<Bit 1 */
+#define FMC_PIO4_IOHOLD4_2 0x00040000U /*!<Bit 2 */
+#define FMC_PIO4_IOHOLD4_3 0x00080000U /*!<Bit 3 */
+#define FMC_PIO4_IOHOLD4_4 0x00100000U /*!<Bit 4 */
+#define FMC_PIO4_IOHOLD4_5 0x00200000U /*!<Bit 5 */
+#define FMC_PIO4_IOHOLD4_6 0x00400000U /*!<Bit 6 */
+#define FMC_PIO4_IOHOLD4_7 0x00800000U /*!<Bit 7 */
+
+#define FMC_PIO4_IOHIZ4 0xFF000000U /*!<IOHIZ4[7:0] bits (I/O 4 databus HiZ time) */
+#define FMC_PIO4_IOHIZ4_0 0x01000000U /*!<Bit 0 */
+#define FMC_PIO4_IOHIZ4_1 0x02000000U /*!<Bit 1 */
+#define FMC_PIO4_IOHIZ4_2 0x04000000U /*!<Bit 2 */
+#define FMC_PIO4_IOHIZ4_3 0x08000000U /*!<Bit 3 */
+#define FMC_PIO4_IOHIZ4_4 0x10000000U /*!<Bit 4 */
+#define FMC_PIO4_IOHIZ4_5 0x20000000U /*!<Bit 5 */
+#define FMC_PIO4_IOHIZ4_6 0x40000000U /*!<Bit 6 */
+#define FMC_PIO4_IOHIZ4_7 0x80000000U /*!<Bit 7 */
+
+/****************** Bit definition for FMC_ECCR2 register ******************/
+#define FMC_ECCR2_ECC2 0xFFFFFFFFU /*!<ECC result */
+
+/****************** Bit definition for FMC_ECCR3 register ******************/
+#define FMC_ECCR3_ECC3 0xFFFFFFFFU /*!<ECC result */
+
+/****************** Bit definition for FMC_SDCR1 register ******************/
+#define FMC_SDCR1_NC 0x00000003U /*!<NC[1:0] bits (Number of column bits) */
+#define FMC_SDCR1_NC_0 0x00000001U /*!<Bit 0 */
+#define FMC_SDCR1_NC_1 0x00000002U /*!<Bit 1 */
+
+#define FMC_SDCR1_NR 0x0000000CU /*!<NR[1:0] bits (Number of row bits) */
+#define FMC_SDCR1_NR_0 0x00000004U /*!<Bit 0 */
+#define FMC_SDCR1_NR_1 0x00000008U /*!<Bit 1 */
+
+#define FMC_SDCR1_MWID 0x00000030U /*!<NR[1:0] bits (Number of row bits) */
+#define FMC_SDCR1_MWID_0 0x00000010U /*!<Bit 0 */
+#define FMC_SDCR1_MWID_1 0x00000020U /*!<Bit 1 */
+
+#define FMC_SDCR1_NB 0x00000040U /*!<Number of internal bank */
+
+#define FMC_SDCR1_CAS 0x00000180U /*!<CAS[1:0] bits (CAS latency) */
+#define FMC_SDCR1_CAS_0 0x00000080U /*!<Bit 0 */
+#define FMC_SDCR1_CAS_1 0x00000100U /*!<Bit 1 */
+
+#define FMC_SDCR1_WP 0x00000200U /*!<Write protection */
+
+#define FMC_SDCR1_SDCLK 0x00000C00U /*!<SDRAM clock configuration */
+#define FMC_SDCR1_SDCLK_0 0x00000400U /*!<Bit 0 */
+#define FMC_SDCR1_SDCLK_1 0x00000800U /*!<Bit 1 */
+
+#define FMC_SDCR1_RBURST 0x00001000U /*!<Read burst */
+
+#define FMC_SDCR1_RPIPE 0x00006000U /*!<Write protection */
+#define FMC_SDCR1_RPIPE_0 0x00002000U /*!<Bit 0 */
+#define FMC_SDCR1_RPIPE_1 0x00004000U /*!<Bit 1 */
+
+/****************** Bit definition for FMC_SDCR2 register ******************/
+#define FMC_SDCR2_NC 0x00000003U /*!<NC[1:0] bits (Number of column bits) */
+#define FMC_SDCR2_NC_0 0x00000001U /*!<Bit 0 */
+#define FMC_SDCR2_NC_1 0x00000002U /*!<Bit 1 */
+
+#define FMC_SDCR2_NR 0x0000000CU /*!<NR[1:0] bits (Number of row bits) */
+#define FMC_SDCR2_NR_0 0x00000004U /*!<Bit 0 */
+#define FMC_SDCR2_NR_1 0x00000008U /*!<Bit 1 */
+
+#define FMC_SDCR2_MWID 0x00000030U /*!<NR[1:0] bits (Number of row bits) */
+#define FMC_SDCR2_MWID_0 0x00000010U /*!<Bit 0 */
+#define FMC_SDCR2_MWID_1 0x00000020U /*!<Bit 1 */
+
+#define FMC_SDCR2_NB 0x00000040U /*!<Number of internal bank */
+
+#define FMC_SDCR2_CAS 0x00000180U /*!<CAS[1:0] bits (CAS latency) */
+#define FMC_SDCR2_CAS_0 0x00000080U /*!<Bit 0 */
+#define FMC_SDCR2_CAS_1 0x00000100U /*!<Bit 1 */
+
+#define FMC_SDCR2_WP 0x00000200U /*!<Write protection */
+
+#define FMC_SDCR2_SDCLK 0x00000C00U /*!<SDCLK[1:0] (SDRAM clock configuration) */
+#define FMC_SDCR2_SDCLK_0 0x00000400U /*!<Bit 0 */
+#define FMC_SDCR2_SDCLK_1 0x00000800U /*!<Bit 1 */
+
+#define FMC_SDCR2_RBURST 0x00001000U /*!<Read burst */
+
+#define FMC_SDCR2_RPIPE 0x00006000U /*!<RPIPE[1:0](Read pipe) */
+#define FMC_SDCR2_RPIPE_0 0x00002000U /*!<Bit 0 */
+#define FMC_SDCR2_RPIPE_1 0x00004000U /*!<Bit 1 */
+
+/****************** Bit definition for FMC_SDTR1 register ******************/
+#define FMC_SDTR1_TMRD 0x0000000FU /*!<TMRD[3:0] bits (Load mode register to active) */
+#define FMC_SDTR1_TMRD_0 0x00000001U /*!<Bit 0 */
+#define FMC_SDTR1_TMRD_1 0x00000002U /*!<Bit 1 */
+#define FMC_SDTR1_TMRD_2 0x00000004U /*!<Bit 2 */
+#define FMC_SDTR1_TMRD_3 0x00000008U /*!<Bit 3 */
+
+#define FMC_SDTR1_TXSR 0x000000F0U /*!<TXSR[3:0] bits (Exit self refresh) */
+#define FMC_SDTR1_TXSR_0 0x00000010U /*!<Bit 0 */
+#define FMC_SDTR1_TXSR_1 0x00000020U /*!<Bit 1 */
+#define FMC_SDTR1_TXSR_2 0x00000040U /*!<Bit 2 */
+#define FMC_SDTR1_TXSR_3 0x00000080U /*!<Bit 3 */
+
+#define FMC_SDTR1_TRAS 0x00000F00U /*!<TRAS[3:0] bits (Self refresh time) */
+#define FMC_SDTR1_TRAS_0 0x00000100U /*!<Bit 0 */
+#define FMC_SDTR1_TRAS_1 0x00000200U /*!<Bit 1 */
+#define FMC_SDTR1_TRAS_2 0x00000400U /*!<Bit 2 */
+#define FMC_SDTR1_TRAS_3 0x00000800U /*!<Bit 3 */
+
+#define FMC_SDTR1_TRC 0x0000F000U /*!<TRC[2:0] bits (Row cycle delay) */
+#define FMC_SDTR1_TRC_0 0x00001000U /*!<Bit 0 */
+#define FMC_SDTR1_TRC_1 0x00002000U /*!<Bit 1 */
+#define FMC_SDTR1_TRC_2 0x00004000U /*!<Bit 2 */
+
+#define FMC_SDTR1_TWR 0x000F0000U /*!<TRC[2:0] bits (Write recovery delay) */
+#define FMC_SDTR1_TWR_0 0x00010000U /*!<Bit 0 */
+#define FMC_SDTR1_TWR_1 0x00020000U /*!<Bit 1 */
+#define FMC_SDTR1_TWR_2 0x00040000U /*!<Bit 2 */
+
+#define FMC_SDTR1_TRP 0x00F00000U /*!<TRP[2:0] bits (Row precharge delay) */
+#define FMC_SDTR1_TRP_0 0x00100000U /*!<Bit 0 */
+#define FMC_SDTR1_TRP_1 0x00200000U /*!<Bit 1 */
+#define FMC_SDTR1_TRP_2 0x00400000U /*!<Bit 2 */
+
+#define FMC_SDTR1_TRCD 0x0F000000U /*!<TRP[2:0] bits (Row to column delay) */
+#define FMC_SDTR1_TRCD_0 0x01000000U /*!<Bit 0 */
+#define FMC_SDTR1_TRCD_1 0x02000000U /*!<Bit 1 */
+#define FMC_SDTR1_TRCD_2 0x04000000U /*!<Bit 2 */
+
+/****************** Bit definition for FMC_SDTR2 register ******************/
+#define FMC_SDTR2_TMRD 0x0000000FU /*!<TMRD[3:0] bits (Load mode register to active) */
+#define FMC_SDTR2_TMRD_0 0x00000001U /*!<Bit 0 */
+#define FMC_SDTR2_TMRD_1 0x00000002U /*!<Bit 1 */
+#define FMC_SDTR2_TMRD_2 0x00000004U /*!<Bit 2 */
+#define FMC_SDTR2_TMRD_3 0x00000008U /*!<Bit 3 */
+
+#define FMC_SDTR2_TXSR 0x000000F0U /*!<TXSR[3:0] bits (Exit self refresh) */
+#define FMC_SDTR2_TXSR_0 0x00000010U /*!<Bit 0 */
+#define FMC_SDTR2_TXSR_1 0x00000020U /*!<Bit 1 */
+#define FMC_SDTR2_TXSR_2 0x00000040U /*!<Bit 2 */
+#define FMC_SDTR2_TXSR_3 0x00000080U /*!<Bit 3 */
+
+#define FMC_SDTR2_TRAS 0x00000F00U /*!<TRAS[3:0] bits (Self refresh time) */
+#define FMC_SDTR2_TRAS_0 0x00000100U /*!<Bit 0 */
+#define FMC_SDTR2_TRAS_1 0x00000200U /*!<Bit 1 */
+#define FMC_SDTR2_TRAS_2 0x00000400U /*!<Bit 2 */
+#define FMC_SDTR2_TRAS_3 0x00000800U /*!<Bit 3 */
+
+#define FMC_SDTR2_TRC 0x0000F000U /*!<TRC[2:0] bits (Row cycle delay) */
+#define FMC_SDTR2_TRC_0 0x00001000U /*!<Bit 0 */
+#define FMC_SDTR2_TRC_1 0x00002000U /*!<Bit 1 */
+#define FMC_SDTR2_TRC_2 0x00004000U /*!<Bit 2 */
+
+#define FMC_SDTR2_TWR 0x000F0000U /*!<TRC[2:0] bits (Write recovery delay) */
+#define FMC_SDTR2_TWR_0 0x00010000U /*!<Bit 0 */
+#define FMC_SDTR2_TWR_1 0x00020000U /*!<Bit 1 */
+#define FMC_SDTR2_TWR_2 0x00040000U /*!<Bit 2 */
+
+#define FMC_SDTR2_TRP 0x00F00000U /*!<TRP[2:0] bits (Row precharge delay) */
+#define FMC_SDTR2_TRP_0 0x00100000U /*!<Bit 0 */
+#define FMC_SDTR2_TRP_1 0x00200000U /*!<Bit 1 */
+#define FMC_SDTR2_TRP_2 0x00400000U /*!<Bit 2 */
+
+#define FMC_SDTR2_TRCD 0x0F000000U /*!<TRP[2:0] bits (Row to column delay) */
+#define FMC_SDTR2_TRCD_0 0x01000000U /*!<Bit 0 */
+#define FMC_SDTR2_TRCD_1 0x02000000U /*!<Bit 1 */
+#define FMC_SDTR2_TRCD_2 0x04000000U /*!<Bit 2 */
+
+/****************** Bit definition for FMC_SDCMR register ******************/
+#define FMC_SDCMR_MODE 0x00000007U /*!<MODE[2:0] bits (Command mode) */
+#define FMC_SDCMR_MODE_0 0x00000001U /*!<Bit 0 */
+#define FMC_SDCMR_MODE_1 0x00000002U /*!<Bit 1 */
+#define FMC_SDCMR_MODE_2 0x00000004U /*!<Bit 2 */
+
+#define FMC_SDCMR_CTB2 0x00000008U /*!<Command target 2 */
+
+#define FMC_SDCMR_CTB1 0x00000010U /*!<Command target 1 */
+
+#define FMC_SDCMR_NRFS 0x000001E0U /*!<NRFS[3:0] bits (Number of auto-refresh) */
+#define FMC_SDCMR_NRFS_0 0x00000020U /*!<Bit 0 */
+#define FMC_SDCMR_NRFS_1 0x00000040U /*!<Bit 1 */
+#define FMC_SDCMR_NRFS_2 0x00000080U /*!<Bit 2 */
+#define FMC_SDCMR_NRFS_3 0x00000100U /*!<Bit 3 */
+
+#define FMC_SDCMR_MRD 0x003FFE00U /*!<MRD[12:0] bits (Mode register definition) */
+
+/****************** Bit definition for FMC_SDRTR register ******************/
+#define FMC_SDRTR_CRE 0x00000001U /*!<Clear refresh error flag */
+
+#define FMC_SDRTR_COUNT 0x00003FFEU /*!<COUNT[12:0] bits (Refresh timer count) */
+
+#define FMC_SDRTR_REIE 0x00004000U /*!<RES interupt enable */
+
+/****************** Bit definition for FMC_SDSR register ******************/
+#define FMC_SDSR_RE 0x00000001U /*!<Refresh error flag */
+
+#define FMC_SDSR_MODES1 0x00000006U /*!<MODES1[1:0]bits (Status mode for bank 1) */
+#define FMC_SDSR_MODES1_0 0x00000002U /*!<Bit 0 */
+#define FMC_SDSR_MODES1_1 0x00000004U /*!<Bit 1 */
+
+#define FMC_SDSR_MODES2 0x00000018U /*!<MODES2[1:0]bits (Status mode for bank 2) */
+#define FMC_SDSR_MODES2_0 0x00000008U /*!<Bit 0 */
+#define FMC_SDSR_MODES2_1 0x00000010U /*!<Bit 1 */
+#define FMC_SDSR_BUSY 0x00000020U /*!<Busy status */
+
+
+
+/******************************************************************************/
+/* */
+/* General Purpose I/O */
+/* */
+/******************************************************************************/
+/****************** Bits definition for GPIO_MODER register *****************/
+#define GPIO_MODER_MODER0 0x00000003U
+#define GPIO_MODER_MODER0_0 0x00000001U
+#define GPIO_MODER_MODER0_1 0x00000002U
+
+#define GPIO_MODER_MODER1 0x0000000CU
+#define GPIO_MODER_MODER1_0 0x00000004U
+#define GPIO_MODER_MODER1_1 0x00000008U
+
+#define GPIO_MODER_MODER2 0x00000030U
+#define GPIO_MODER_MODER2_0 0x00000010U
+#define GPIO_MODER_MODER2_1 0x00000020U
+
+#define GPIO_MODER_MODER3 0x000000C0U
+#define GPIO_MODER_MODER3_0 0x00000040U
+#define GPIO_MODER_MODER3_1 0x00000080U
+
+#define GPIO_MODER_MODER4 0x00000300U
+#define GPIO_MODER_MODER4_0 0x00000100U
+#define GPIO_MODER_MODER4_1 0x00000200U
+
+#define GPIO_MODER_MODER5 0x00000C00U
+#define GPIO_MODER_MODER5_0 0x00000400U
+#define GPIO_MODER_MODER5_1 0x00000800U
+
+#define GPIO_MODER_MODER6 0x00003000U
+#define GPIO_MODER_MODER6_0 0x00001000U
+#define GPIO_MODER_MODER6_1 0x00002000U
+
+#define GPIO_MODER_MODER7 0x0000C000U
+#define GPIO_MODER_MODER7_0 0x00004000U
+#define GPIO_MODER_MODER7_1 0x00008000U
+
+#define GPIO_MODER_MODER8 0x00030000U
+#define GPIO_MODER_MODER8_0 0x00010000U
+#define GPIO_MODER_MODER8_1 0x00020000U
+
+#define GPIO_MODER_MODER9 0x000C0000U
+#define GPIO_MODER_MODER9_0 0x00040000U
+#define GPIO_MODER_MODER9_1 0x00080000U
+
+#define GPIO_MODER_MODER10 0x00300000U
+#define GPIO_MODER_MODER10_0 0x00100000U
+#define GPIO_MODER_MODER10_1 0x00200000U
+
+#define GPIO_MODER_MODER11 0x00C00000U
+#define GPIO_MODER_MODER11_0 0x00400000U
+#define GPIO_MODER_MODER11_1 0x00800000U
+
+#define GPIO_MODER_MODER12 0x03000000U
+#define GPIO_MODER_MODER12_0 0x01000000U
+#define GPIO_MODER_MODER12_1 0x02000000U
+
+#define GPIO_MODER_MODER13 0x0C000000U
+#define GPIO_MODER_MODER13_0 0x04000000U
+#define GPIO_MODER_MODER13_1 0x08000000U
+
+#define GPIO_MODER_MODER14 0x30000000U
+#define GPIO_MODER_MODER14_0 0x10000000U
+#define GPIO_MODER_MODER14_1 0x20000000U
+
+#define GPIO_MODER_MODER15 0xC0000000U
+#define GPIO_MODER_MODER15_0 0x40000000U
+#define GPIO_MODER_MODER15_1 0x80000000U
+
+/****************** Bits definition for GPIO_OTYPER register ****************/
+#define GPIO_OTYPER_OT_0 0x00000001U
+#define GPIO_OTYPER_OT_1 0x00000002U
+#define GPIO_OTYPER_OT_2 0x00000004U
+#define GPIO_OTYPER_OT_3 0x00000008U
+#define GPIO_OTYPER_OT_4 0x00000010U
+#define GPIO_OTYPER_OT_5 0x00000020U
+#define GPIO_OTYPER_OT_6 0x00000040U
+#define GPIO_OTYPER_OT_7 0x00000080U
+#define GPIO_OTYPER_OT_8 0x00000100U
+#define GPIO_OTYPER_OT_9 0x00000200U
+#define GPIO_OTYPER_OT_10 0x00000400U
+#define GPIO_OTYPER_OT_11 0x00000800U
+#define GPIO_OTYPER_OT_12 0x00001000U
+#define GPIO_OTYPER_OT_13 0x00002000U
+#define GPIO_OTYPER_OT_14 0x00004000U
+#define GPIO_OTYPER_OT_15 0x00008000U
+
+/****************** Bits definition for GPIO_OSPEEDR register ***************/
+#define GPIO_OSPEEDER_OSPEEDR0 0x00000003U
+#define GPIO_OSPEEDER_OSPEEDR0_0 0x00000001U
+#define GPIO_OSPEEDER_OSPEEDR0_1 0x00000002U
+
+#define GPIO_OSPEEDER_OSPEEDR1 0x0000000CU
+#define GPIO_OSPEEDER_OSPEEDR1_0 0x00000004U
+#define GPIO_OSPEEDER_OSPEEDR1_1 0x00000008U
+
+#define GPIO_OSPEEDER_OSPEEDR2 0x00000030U
+#define GPIO_OSPEEDER_OSPEEDR2_0 0x00000010U
+#define GPIO_OSPEEDER_OSPEEDR2_1 0x00000020U
+
+#define GPIO_OSPEEDER_OSPEEDR3 0x000000C0U
+#define GPIO_OSPEEDER_OSPEEDR3_0 0x00000040U
+#define GPIO_OSPEEDER_OSPEEDR3_1 0x00000080U
+
+#define GPIO_OSPEEDER_OSPEEDR4 0x00000300U
+#define GPIO_OSPEEDER_OSPEEDR4_0 0x00000100U
+#define GPIO_OSPEEDER_OSPEEDR4_1 0x00000200U
+
+#define GPIO_OSPEEDER_OSPEEDR5 0x00000C00U
+#define GPIO_OSPEEDER_OSPEEDR5_0 0x00000400U
+#define GPIO_OSPEEDER_OSPEEDR5_1 0x00000800U
+
+#define GPIO_OSPEEDER_OSPEEDR6 0x00003000U
+#define GPIO_OSPEEDER_OSPEEDR6_0 0x00001000U
+#define GPIO_OSPEEDER_OSPEEDR6_1 0x00002000U
+
+#define GPIO_OSPEEDER_OSPEEDR7 0x0000C000U
+#define GPIO_OSPEEDER_OSPEEDR7_0 0x00004000U
+#define GPIO_OSPEEDER_OSPEEDR7_1 0x00008000U
+
+#define GPIO_OSPEEDER_OSPEEDR8 0x00030000U
+#define GPIO_OSPEEDER_OSPEEDR8_0 0x00010000U
+#define GPIO_OSPEEDER_OSPEEDR8_1 0x00020000U
+
+#define GPIO_OSPEEDER_OSPEEDR9 0x000C0000U
+#define GPIO_OSPEEDER_OSPEEDR9_0 0x00040000U
+#define GPIO_OSPEEDER_OSPEEDR9_1 0x00080000U
+
+#define GPIO_OSPEEDER_OSPEEDR10 0x00300000U
+#define GPIO_OSPEEDER_OSPEEDR10_0 0x00100000U
+#define GPIO_OSPEEDER_OSPEEDR10_1 0x00200000U
+
+#define GPIO_OSPEEDER_OSPEEDR11 0x00C00000U
+#define GPIO_OSPEEDER_OSPEEDR11_0 0x00400000U
+#define GPIO_OSPEEDER_OSPEEDR11_1 0x00800000U
+
+#define GPIO_OSPEEDER_OSPEEDR12 0x03000000U
+#define GPIO_OSPEEDER_OSPEEDR12_0 0x01000000U
+#define GPIO_OSPEEDER_OSPEEDR12_1 0x02000000U
+
+#define GPIO_OSPEEDER_OSPEEDR13 0x0C000000U
+#define GPIO_OSPEEDER_OSPEEDR13_0 0x04000000U
+#define GPIO_OSPEEDER_OSPEEDR13_1 0x08000000U
+
+#define GPIO_OSPEEDER_OSPEEDR14 0x30000000U
+#define GPIO_OSPEEDER_OSPEEDR14_0 0x10000000U
+#define GPIO_OSPEEDER_OSPEEDR14_1 0x20000000U
+
+#define GPIO_OSPEEDER_OSPEEDR15 0xC0000000U
+#define GPIO_OSPEEDER_OSPEEDR15_0 0x40000000U
+#define GPIO_OSPEEDER_OSPEEDR15_1 0x80000000U
+
+/****************** Bits definition for GPIO_PUPDR register *****************/
+#define GPIO_PUPDR_PUPDR0 0x00000003U
+#define GPIO_PUPDR_PUPDR0_0 0x00000001U
+#define GPIO_PUPDR_PUPDR0_1 0x00000002U
+
+#define GPIO_PUPDR_PUPDR1 0x0000000CU
+#define GPIO_PUPDR_PUPDR1_0 0x00000004U
+#define GPIO_PUPDR_PUPDR1_1 0x00000008U
+
+#define GPIO_PUPDR_PUPDR2 0x00000030U
+#define GPIO_PUPDR_PUPDR2_0 0x00000010U
+#define GPIO_PUPDR_PUPDR2_1 0x00000020U
+
+#define GPIO_PUPDR_PUPDR3 0x000000C0U
+#define GPIO_PUPDR_PUPDR3_0 0x00000040U
+#define GPIO_PUPDR_PUPDR3_1 0x00000080U
+
+#define GPIO_PUPDR_PUPDR4 0x00000300U
+#define GPIO_PUPDR_PUPDR4_0 0x00000100U
+#define GPIO_PUPDR_PUPDR4_1 0x00000200U
+
+#define GPIO_PUPDR_PUPDR5 0x00000C00U
+#define GPIO_PUPDR_PUPDR5_0 0x00000400U
+#define GPIO_PUPDR_PUPDR5_1 0x00000800U
+
+#define GPIO_PUPDR_PUPDR6 0x00003000U
+#define GPIO_PUPDR_PUPDR6_0 0x00001000U
+#define GPIO_PUPDR_PUPDR6_1 0x00002000U
+
+#define GPIO_PUPDR_PUPDR7 0x0000C000U
+#define GPIO_PUPDR_PUPDR7_0 0x00004000U
+#define GPIO_PUPDR_PUPDR7_1 0x00008000U
+
+#define GPIO_PUPDR_PUPDR8 0x00030000U
+#define GPIO_PUPDR_PUPDR8_0 0x00010000U
+#define GPIO_PUPDR_PUPDR8_1 0x00020000U
+
+#define GPIO_PUPDR_PUPDR9 0x000C0000U
+#define GPIO_PUPDR_PUPDR9_0 0x00040000U
+#define GPIO_PUPDR_PUPDR9_1 0x00080000U
+
+#define GPIO_PUPDR_PUPDR10 0x00300000U
+#define GPIO_PUPDR_PUPDR10_0 0x00100000U
+#define GPIO_PUPDR_PUPDR10_1 0x00200000U
+
+#define GPIO_PUPDR_PUPDR11 0x00C00000U
+#define GPIO_PUPDR_PUPDR11_0 0x00400000U
+#define GPIO_PUPDR_PUPDR11_1 0x00800000U
+
+#define GPIO_PUPDR_PUPDR12 0x03000000U
+#define GPIO_PUPDR_PUPDR12_0 0x01000000U
+#define GPIO_PUPDR_PUPDR12_1 0x02000000U
+
+#define GPIO_PUPDR_PUPDR13 0x0C000000U
+#define GPIO_PUPDR_PUPDR13_0 0x04000000U
+#define GPIO_PUPDR_PUPDR13_1 0x08000000U
+
+#define GPIO_PUPDR_PUPDR14 0x30000000U
+#define GPIO_PUPDR_PUPDR14_0 0x10000000U
+#define GPIO_PUPDR_PUPDR14_1 0x20000000U
+
+#define GPIO_PUPDR_PUPDR15 0xC0000000U
+#define GPIO_PUPDR_PUPDR15_0 0x40000000U
+#define GPIO_PUPDR_PUPDR15_1 0x80000000U
+
+/****************** Bits definition for GPIO_IDR register *******************/
+#define GPIO_IDR_IDR_0 0x00000001U
+#define GPIO_IDR_IDR_1 0x00000002U
+#define GPIO_IDR_IDR_2 0x00000004U
+#define GPIO_IDR_IDR_3 0x00000008U
+#define GPIO_IDR_IDR_4 0x00000010U
+#define GPIO_IDR_IDR_5 0x00000020U
+#define GPIO_IDR_IDR_6 0x00000040U
+#define GPIO_IDR_IDR_7 0x00000080U
+#define GPIO_IDR_IDR_8 0x00000100U
+#define GPIO_IDR_IDR_9 0x00000200U
+#define GPIO_IDR_IDR_10 0x00000400U
+#define GPIO_IDR_IDR_11 0x00000800U
+#define GPIO_IDR_IDR_12 0x00001000U
+#define GPIO_IDR_IDR_13 0x00002000U
+#define GPIO_IDR_IDR_14 0x00004000U
+#define GPIO_IDR_IDR_15 0x00008000U
+/* Old GPIO_IDR register bits definition, maintained for legacy purpose */
+#define GPIO_OTYPER_IDR_0 GPIO_IDR_IDR_0
+#define GPIO_OTYPER_IDR_1 GPIO_IDR_IDR_1
+#define GPIO_OTYPER_IDR_2 GPIO_IDR_IDR_2
+#define GPIO_OTYPER_IDR_3 GPIO_IDR_IDR_3
+#define GPIO_OTYPER_IDR_4 GPIO_IDR_IDR_4
+#define GPIO_OTYPER_IDR_5 GPIO_IDR_IDR_5
+#define GPIO_OTYPER_IDR_6 GPIO_IDR_IDR_6
+#define GPIO_OTYPER_IDR_7 GPIO_IDR_IDR_7
+#define GPIO_OTYPER_IDR_8 GPIO_IDR_IDR_8
+#define GPIO_OTYPER_IDR_9 GPIO_IDR_IDR_9
+#define GPIO_OTYPER_IDR_10 GPIO_IDR_IDR_10
+#define GPIO_OTYPER_IDR_11 GPIO_IDR_IDR_11
+#define GPIO_OTYPER_IDR_12 GPIO_IDR_IDR_12
+#define GPIO_OTYPER_IDR_13 GPIO_IDR_IDR_13
+#define GPIO_OTYPER_IDR_14 GPIO_IDR_IDR_14
+#define GPIO_OTYPER_IDR_15 GPIO_IDR_IDR_15
+
+/****************** Bits definition for GPIO_ODR register *******************/
+#define GPIO_ODR_ODR_0 0x00000001U
+#define GPIO_ODR_ODR_1 0x00000002U
+#define GPIO_ODR_ODR_2 0x00000004U
+#define GPIO_ODR_ODR_3 0x00000008U
+#define GPIO_ODR_ODR_4 0x00000010U
+#define GPIO_ODR_ODR_5 0x00000020U
+#define GPIO_ODR_ODR_6 0x00000040U
+#define GPIO_ODR_ODR_7 0x00000080U
+#define GPIO_ODR_ODR_8 0x00000100U
+#define GPIO_ODR_ODR_9 0x00000200U
+#define GPIO_ODR_ODR_10 0x00000400U
+#define GPIO_ODR_ODR_11 0x00000800U
+#define GPIO_ODR_ODR_12 0x00001000U
+#define GPIO_ODR_ODR_13 0x00002000U
+#define GPIO_ODR_ODR_14 0x00004000U
+#define GPIO_ODR_ODR_15 0x00008000U
+/* Old GPIO_ODR register bits definition, maintained for legacy purpose */
+#define GPIO_OTYPER_ODR_0 GPIO_ODR_ODR_0
+#define GPIO_OTYPER_ODR_1 GPIO_ODR_ODR_1
+#define GPIO_OTYPER_ODR_2 GPIO_ODR_ODR_2
+#define GPIO_OTYPER_ODR_3 GPIO_ODR_ODR_3
+#define GPIO_OTYPER_ODR_4 GPIO_ODR_ODR_4
+#define GPIO_OTYPER_ODR_5 GPIO_ODR_ODR_5
+#define GPIO_OTYPER_ODR_6 GPIO_ODR_ODR_6
+#define GPIO_OTYPER_ODR_7 GPIO_ODR_ODR_7
+#define GPIO_OTYPER_ODR_8 GPIO_ODR_ODR_8
+#define GPIO_OTYPER_ODR_9 GPIO_ODR_ODR_9
+#define GPIO_OTYPER_ODR_10 GPIO_ODR_ODR_10
+#define GPIO_OTYPER_ODR_11 GPIO_ODR_ODR_11
+#define GPIO_OTYPER_ODR_12 GPIO_ODR_ODR_12
+#define GPIO_OTYPER_ODR_13 GPIO_ODR_ODR_13
+#define GPIO_OTYPER_ODR_14 GPIO_ODR_ODR_14
+#define GPIO_OTYPER_ODR_15 GPIO_ODR_ODR_15
+
+/****************** Bits definition for GPIO_BSRR register ******************/
+#define GPIO_BSRR_BS_0 0x00000001U
+#define GPIO_BSRR_BS_1 0x00000002U
+#define GPIO_BSRR_BS_2 0x00000004U
+#define GPIO_BSRR_BS_3 0x00000008U
+#define GPIO_BSRR_BS_4 0x00000010U
+#define GPIO_BSRR_BS_5 0x00000020U
+#define GPIO_BSRR_BS_6 0x00000040U
+#define GPIO_BSRR_BS_7 0x00000080U
+#define GPIO_BSRR_BS_8 0x00000100U
+#define GPIO_BSRR_BS_9 0x00000200U
+#define GPIO_BSRR_BS_10 0x00000400U
+#define GPIO_BSRR_BS_11 0x00000800U
+#define GPIO_BSRR_BS_12 0x00001000U
+#define GPIO_BSRR_BS_13 0x00002000U
+#define GPIO_BSRR_BS_14 0x00004000U
+#define GPIO_BSRR_BS_15 0x00008000U
+#define GPIO_BSRR_BR_0 0x00010000U
+#define GPIO_BSRR_BR_1 0x00020000U
+#define GPIO_BSRR_BR_2 0x00040000U
+#define GPIO_BSRR_BR_3 0x00080000U
+#define GPIO_BSRR_BR_4 0x00100000U
+#define GPIO_BSRR_BR_5 0x00200000U
+#define GPIO_BSRR_BR_6 0x00400000U
+#define GPIO_BSRR_BR_7 0x00800000U
+#define GPIO_BSRR_BR_8 0x01000000U
+#define GPIO_BSRR_BR_9 0x02000000U
+#define GPIO_BSRR_BR_10 0x04000000U
+#define GPIO_BSRR_BR_11 0x08000000U
+#define GPIO_BSRR_BR_12 0x10000000U
+#define GPIO_BSRR_BR_13 0x20000000U
+#define GPIO_BSRR_BR_14 0x40000000U
+#define GPIO_BSRR_BR_15 0x80000000U
+
+/****************** Bit definition for GPIO_LCKR register *********************/
+#define GPIO_LCKR_LCK0 0x00000001U
+#define GPIO_LCKR_LCK1 0x00000002U
+#define GPIO_LCKR_LCK2 0x00000004U
+#define GPIO_LCKR_LCK3 0x00000008U
+#define GPIO_LCKR_LCK4 0x00000010U
+#define GPIO_LCKR_LCK5 0x00000020U
+#define GPIO_LCKR_LCK6 0x00000040U
+#define GPIO_LCKR_LCK7 0x00000080U
+#define GPIO_LCKR_LCK8 0x00000100U
+#define GPIO_LCKR_LCK9 0x00000200U
+#define GPIO_LCKR_LCK10 0x00000400U
+#define GPIO_LCKR_LCK11 0x00000800U
+#define GPIO_LCKR_LCK12 0x00001000U
+#define GPIO_LCKR_LCK13 0x00002000U
+#define GPIO_LCKR_LCK14 0x00004000U
+#define GPIO_LCKR_LCK15 0x00008000U
+#define GPIO_LCKR_LCKK 0x00010000U
+
+/******************************************************************************/
+/* */
+/* HASH */
+/* */
+/******************************************************************************/
+/****************** Bits definition for HASH_CR register ********************/
+#define HASH_CR_INIT 0x00000004U
+#define HASH_CR_DMAE 0x00000008U
+#define HASH_CR_DATATYPE 0x00000030U
+#define HASH_CR_DATATYPE_0 0x00000010U
+#define HASH_CR_DATATYPE_1 0x00000020U
+#define HASH_CR_MODE 0x00000040U
+#define HASH_CR_ALGO 0x00040080U
+#define HASH_CR_ALGO_0 0x00000080U
+#define HASH_CR_ALGO_1 0x00040000U
+#define HASH_CR_NBW 0x00000F00U
+#define HASH_CR_NBW_0 0x00000100U
+#define HASH_CR_NBW_1 0x00000200U
+#define HASH_CR_NBW_2 0x00000400U
+#define HASH_CR_NBW_3 0x00000800U
+#define HASH_CR_DINNE 0x00001000U
+#define HASH_CR_MDMAT 0x00002000U
+#define HASH_CR_LKEY 0x00010000U
+
+/****************** Bits definition for HASH_STR register *******************/
+#define HASH_STR_NBLW 0x0000001FU
+#define HASH_STR_NBLW_0 0x00000001U
+#define HASH_STR_NBLW_1 0x00000002U
+#define HASH_STR_NBLW_2 0x00000004U
+#define HASH_STR_NBLW_3 0x00000008U
+#define HASH_STR_NBLW_4 0x00000010U
+#define HASH_STR_DCAL 0x00000100U
+/* Aliases for HASH_STR register */
+#define HASH_STR_NBW HASH_STR_NBLW
+#define HASH_STR_NBW_0 HASH_STR_NBLW_0
+#define HASH_STR_NBW_1 HASH_STR_NBLW_1
+#define HASH_STR_NBW_2 HASH_STR_NBLW_2
+#define HASH_STR_NBW_3 HASH_STR_NBLW_3
+#define HASH_STR_NBW_4 HASH_STR_NBLW_4
+
+/****************** Bits definition for HASH_IMR register *******************/
+#define HASH_IMR_DINIE 0x00000001U
+#define HASH_IMR_DCIE 0x00000002U
+/* Aliases for HASH_IMR register */
+#define HASH_IMR_DINIM HASH_IMR_DINIE
+#define HASH_IMR_DCIM HASH_IMR_DCIE
+
+/****************** Bits definition for HASH_SR register ********************/
+#define HASH_SR_DINIS 0x00000001U
+#define HASH_SR_DCIS 0x00000002U
+#define HASH_SR_DMAS 0x00000004U
+#define HASH_SR_BUSY 0x00000008U
+
+/******************************************************************************/
+/* */
+/* Inter-integrated Circuit Interface */
+/* */
+/******************************************************************************/
+/******************* Bit definition for I2C_CR1 register ********************/
+#define I2C_CR1_PE 0x00000001U /*!<Peripheral Enable */
+#define I2C_CR1_SMBUS 0x00000002U /*!<SMBus Mode */
+#define I2C_CR1_SMBTYPE 0x00000008U /*!<SMBus Type */
+#define I2C_CR1_ENARP 0x00000010U /*!<ARP Enable */
+#define I2C_CR1_ENPEC 0x00000020U /*!<PEC Enable */
+#define I2C_CR1_ENGC 0x00000040U /*!<General Call Enable */
+#define I2C_CR1_NOSTRETCH 0x00000080U /*!<Clock Stretching Disable (Slave mode) */
+#define I2C_CR1_START 0x00000100U /*!<Start Generation */
+#define I2C_CR1_STOP 0x00000200U /*!<Stop Generation */
+#define I2C_CR1_ACK 0x00000400U /*!<Acknowledge Enable */
+#define I2C_CR1_POS 0x00000800U /*!<Acknowledge/PEC Position (for data reception) */
+#define I2C_CR1_PEC 0x00001000U /*!<Packet Error Checking */
+#define I2C_CR1_ALERT 0x00002000U /*!<SMBus Alert */
+#define I2C_CR1_SWRST 0x00008000U /*!<Software Reset */
+
+/******************* Bit definition for I2C_CR2 register ********************/
+#define I2C_CR2_FREQ 0x0000003FU /*!<FREQ[5:0] bits (Peripheral Clock Frequency) */
+#define I2C_CR2_FREQ_0 0x00000001U /*!<Bit 0 */
+#define I2C_CR2_FREQ_1 0x00000002U /*!<Bit 1 */
+#define I2C_CR2_FREQ_2 0x00000004U /*!<Bit 2 */
+#define I2C_CR2_FREQ_3 0x00000008U /*!<Bit 3 */
+#define I2C_CR2_FREQ_4 0x00000010U /*!<Bit 4 */
+#define I2C_CR2_FREQ_5 0x00000020U /*!<Bit 5 */
+
+#define I2C_CR2_ITERREN 0x00000100U /*!<Error Interrupt Enable */
+#define I2C_CR2_ITEVTEN 0x00000200U /*!<Event Interrupt Enable */
+#define I2C_CR2_ITBUFEN 0x00000400U /*!<Buffer Interrupt Enable */
+#define I2C_CR2_DMAEN 0x00000800U /*!<DMA Requests Enable */
+#define I2C_CR2_LAST 0x00001000U /*!<DMA Last Transfer */
+
+/******************* Bit definition for I2C_OAR1 register *******************/
+#define I2C_OAR1_ADD1_7 0x000000FEU /*!<Interface Address */
+#define I2C_OAR1_ADD8_9 0x00000300U /*!<Interface Address */
+
+#define I2C_OAR1_ADD0 0x00000001U /*!<Bit 0 */
+#define I2C_OAR1_ADD1 0x00000002U /*!<Bit 1 */
+#define I2C_OAR1_ADD2 0x00000004U /*!<Bit 2 */
+#define I2C_OAR1_ADD3 0x00000008U /*!<Bit 3 */
+#define I2C_OAR1_ADD4 0x00000010U /*!<Bit 4 */
+#define I2C_OAR1_ADD5 0x00000020U /*!<Bit 5 */
+#define I2C_OAR1_ADD6 0x00000040U /*!<Bit 6 */
+#define I2C_OAR1_ADD7 0x00000080U /*!<Bit 7 */
+#define I2C_OAR1_ADD8 0x00000100U /*!<Bit 8 */
+#define I2C_OAR1_ADD9 0x00000200U /*!<Bit 9 */
+
+#define I2C_OAR1_ADDMODE 0x00008000U /*!<Addressing Mode (Slave mode) */
+
+/******************* Bit definition for I2C_OAR2 register *******************/
+#define I2C_OAR2_ENDUAL 0x00000001U /*!<Dual addressing mode enable */
+#define I2C_OAR2_ADD2 0x000000FEU /*!<Interface address */
+
+/******************** Bit definition for I2C_DR register ********************/
+#define I2C_DR_DR 0x000000FFU /*!<8-bit Data Register */
+
+/******************* Bit definition for I2C_SR1 register ********************/
+#define I2C_SR1_SB 0x00000001U /*!<Start Bit (Master mode) */
+#define I2C_SR1_ADDR 0x00000002U /*!<Address sent (master mode)/matched (slave mode) */
+#define I2C_SR1_BTF 0x00000004U /*!<Byte Transfer Finished */
+#define I2C_SR1_ADD10 0x00000008U /*!<10-bit header sent (Master mode) */
+#define I2C_SR1_STOPF 0x00000010U /*!<Stop detection (Slave mode) */
+#define I2C_SR1_RXNE 0x00000040U /*!<Data Register not Empty (receivers) */
+#define I2C_SR1_TXE 0x00000080U /*!<Data Register Empty (transmitters) */
+#define I2C_SR1_BERR 0x00000100U /*!<Bus Error */
+#define I2C_SR1_ARLO 0x00000200U /*!<Arbitration Lost (master mode) */
+#define I2C_SR1_AF 0x00000400U /*!<Acknowledge Failure */
+#define I2C_SR1_OVR 0x00000800U /*!<Overrun/Underrun */
+#define I2C_SR1_PECERR 0x00001000U /*!<PEC Error in reception */
+#define I2C_SR1_TIMEOUT 0x00004000U /*!<Timeout or Tlow Error */
+#define I2C_SR1_SMBALERT 0x00008000U /*!<SMBus Alert */
+
+/******************* Bit definition for I2C_SR2 register ********************/
+#define I2C_SR2_MSL 0x00000001U /*!<Master/Slave */
+#define I2C_SR2_BUSY 0x00000002U /*!<Bus Busy */
+#define I2C_SR2_TRA 0x00000004U /*!<Transmitter/Receiver */
+#define I2C_SR2_GENCALL 0x00000010U /*!<General Call Address (Slave mode) */
+#define I2C_SR2_SMBDEFAULT 0x00000020U /*!<SMBus Device Default Address (Slave mode) */
+#define I2C_SR2_SMBHOST 0x00000040U /*!<SMBus Host Header (Slave mode) */
+#define I2C_SR2_DUALF 0x00000080U /*!<Dual Flag (Slave mode) */
+#define I2C_SR2_PEC 0x0000FF00U /*!<Packet Error Checking Register */
+
+/******************* Bit definition for I2C_CCR register ********************/
+#define I2C_CCR_CCR 0x00000FFFU /*!<Clock Control Register in Fast/Standard mode (Master mode) */
+#define I2C_CCR_DUTY 0x00004000U /*!<Fast Mode Duty Cycle */
+#define I2C_CCR_FS 0x00008000U /*!<I2C Master Mode Selection */
+
+/****************** Bit definition for I2C_TRISE register *******************/
+#define I2C_TRISE_TRISE 0x0000003FU /*!<Maximum Rise Time in Fast/Standard mode (Master mode) */
+
+/****************** Bit definition for I2C_FLTR register *******************/
+#define I2C_FLTR_DNF 0x0000000FU /*!<Digital Noise Filter */
+#define I2C_FLTR_ANOFF 0x00000010U /*!<Analog Noise Filter OFF */
+
+/******************************************************************************/
+/* */
+/* Independent WATCHDOG */
+/* */
+/******************************************************************************/
+/******************* Bit definition for IWDG_KR register ********************/
+#define IWDG_KR_KEY 0xFFFFU /*!<Key value (write only, read 0000h) */
+
+/******************* Bit definition for IWDG_PR register ********************/
+#define IWDG_PR_PR 0x07U /*!<PR[2:0] (Prescaler divider) */
+#define IWDG_PR_PR_0 0x01U /*!<Bit 0 */
+#define IWDG_PR_PR_1 0x02U /*!<Bit 1 */
+#define IWDG_PR_PR_2 0x04U /*!<Bit 2 */
+
+/******************* Bit definition for IWDG_RLR register *******************/
+#define IWDG_RLR_RL 0x0FFFU /*!<Watchdog counter reload value */
+
+/******************* Bit definition for IWDG_SR register ********************/
+#define IWDG_SR_PVU 0x01U /*!<Watchdog prescaler value update */
+#define IWDG_SR_RVU 0x02U /*!<Watchdog counter reload value update */
+
+/******************************************************************************/
+/* */
+/* Power Control */
+/* */
+/******************************************************************************/
+/******************** Bit definition for PWR_CR register ********************/
+#define PWR_CR_LPDS 0x00000001U /*!< Low-Power Deepsleep */
+#define PWR_CR_PDDS 0x00000002U /*!< Power Down Deepsleep */
+#define PWR_CR_CWUF 0x00000004U /*!< Clear Wakeup Flag */
+#define PWR_CR_CSBF 0x00000008U /*!< Clear Standby Flag */
+#define PWR_CR_PVDE 0x00000010U /*!< Power Voltage Detector Enable */
+
+#define PWR_CR_PLS 0x000000E0U /*!< PLS[2:0] bits (PVD Level Selection) */
+#define PWR_CR_PLS_0 0x00000020U /*!< Bit 0 */
+#define PWR_CR_PLS_1 0x00000040U /*!< Bit 1 */
+#define PWR_CR_PLS_2 0x00000080U /*!< Bit 2 */
+
+/*!< PVD level configuration */
+#define PWR_CR_PLS_LEV0 0x00000000U /*!< PVD level 0 */
+#define PWR_CR_PLS_LEV1 0x00000020U /*!< PVD level 1 */
+#define PWR_CR_PLS_LEV2 0x00000040U /*!< PVD level 2 */
+#define PWR_CR_PLS_LEV3 0x00000060U /*!< PVD level 3 */
+#define PWR_CR_PLS_LEV4 0x00000080U /*!< PVD level 4 */
+#define PWR_CR_PLS_LEV5 0x000000A0U /*!< PVD level 5 */
+#define PWR_CR_PLS_LEV6 0x000000C0U /*!< PVD level 6 */
+#define PWR_CR_PLS_LEV7 0x000000E0U /*!< PVD level 7 */
+#define PWR_CR_DBP 0x00000100U /*!< Disable Backup Domain write protection */
+#define PWR_CR_FPDS 0x00000200U /*!< Flash power down in Stop mode */
+#define PWR_CR_LPLVDS 0x00000400U /*!< Low-Power Regulator Low Voltage Scaling in Stop mode */
+#define PWR_CR_MRLVDS 0x00000800U /*!< Main regulator Low Voltage Scaling in Stop mode */
+#define PWR_CR_ADCDC1 0x00002000U /*!< Refer to AN4073 on how to use this bit */
+#define PWR_CR_VOS 0x0000C000U /*!< VOS[1:0] bits (Regulator voltage scaling output selection) */
+#define PWR_CR_VOS_0 0x00004000U /*!< Bit 0 */
+#define PWR_CR_VOS_1 0x00008000U /*!< Bit 1 */
+#define PWR_CR_ODEN 0x00010000U /*!< Over Drive enable */
+#define PWR_CR_ODSWEN 0x00020000U /*!< Over Drive switch enabled */
+#define PWR_CR_UDEN 0x000C0000U /*!< Under Drive enable in stop mode */
+#define PWR_CR_UDEN_0 0x00040000U /*!< Bit 0 */
+#define PWR_CR_UDEN_1 0x00080000U /*!< Bit 1 */
+
+/* Legacy define */
+#define PWR_CR_PMODE PWR_CR_VOS
+#define PWR_CR_LPUDS PWR_CR_LPLVDS /*!< Low-Power Regulator in deepsleep under-drive mode */
+#define PWR_CR_MRUDS PWR_CR_MRLVDS /*!< Main regulator in deepsleep under-drive mode */
+
+/******************* Bit definition for PWR_CSR register ********************/
+#define PWR_CSR_WUF 0x00000001U /*!< Wakeup Flag */
+#define PWR_CSR_SBF 0x00000002U /*!< Standby Flag */
+#define PWR_CSR_PVDO 0x00000004U /*!< PVD Output */
+#define PWR_CSR_BRR 0x00000008U /*!< Backup regulator ready */
+#define PWR_CSR_EWUP 0x00000100U /*!< Enable WKUP pin */
+#define PWR_CSR_BRE 0x00000200U /*!< Backup regulator enable */
+#define PWR_CSR_VOSRDY 0x00004000U /*!< Regulator voltage scaling output selection ready */
+#define PWR_CSR_ODRDY 0x00010000U /*!< Over Drive generator ready */
+#define PWR_CSR_ODSWRDY 0x00020000U /*!< Over Drive Switch ready */
+#define PWR_CSR_UDSWRDY 0x000C0000U /*!< Under Drive ready */
+
+/* Legacy define */
+#define PWR_CSR_REGRDY PWR_CSR_VOSRDY
+
+/******************************************************************************/
+/* */
+/* Reset and Clock Control */
+/* */
+/******************************************************************************/
+/******************** Bit definition for RCC_CR register ********************/
+#define RCC_CR_HSION 0x00000001U
+#define RCC_CR_HSIRDY 0x00000002U
+
+#define RCC_CR_HSITRIM 0x000000F8U
+#define RCC_CR_HSITRIM_0 0x00000008U/*!<Bit 0 */
+#define RCC_CR_HSITRIM_1 0x00000010U/*!<Bit 1 */
+#define RCC_CR_HSITRIM_2 0x00000020U/*!<Bit 2 */
+#define RCC_CR_HSITRIM_3 0x00000040U/*!<Bit 3 */
+#define RCC_CR_HSITRIM_4 0x00000080U/*!<Bit 4 */
+
+#define RCC_CR_HSICAL 0x0000FF00U
+#define RCC_CR_HSICAL_0 0x00000100U/*!<Bit 0 */
+#define RCC_CR_HSICAL_1 0x00000200U/*!<Bit 1 */
+#define RCC_CR_HSICAL_2 0x00000400U/*!<Bit 2 */
+#define RCC_CR_HSICAL_3 0x00000800U/*!<Bit 3 */
+#define RCC_CR_HSICAL_4 0x00001000U/*!<Bit 4 */
+#define RCC_CR_HSICAL_5 0x00002000U/*!<Bit 5 */
+#define RCC_CR_HSICAL_6 0x00004000U/*!<Bit 6 */
+#define RCC_CR_HSICAL_7 0x00008000U/*!<Bit 7 */
+
+#define RCC_CR_HSEON 0x00010000U
+#define RCC_CR_HSERDY 0x00020000U
+#define RCC_CR_HSEBYP 0x00040000U
+#define RCC_CR_CSSON 0x00080000U
+#define RCC_CR_PLLON 0x01000000U
+#define RCC_CR_PLLRDY 0x02000000U
+#define RCC_CR_PLLI2SON 0x04000000U
+#define RCC_CR_PLLI2SRDY 0x08000000U
+#define RCC_CR_PLLSAION 0x10000000U
+#define RCC_CR_PLLSAIRDY 0x20000000U
+
+/******************** Bit definition for RCC_PLLCFGR register ***************/
+#define RCC_PLLCFGR_PLLM 0x0000003FU
+#define RCC_PLLCFGR_PLLM_0 0x00000001U
+#define RCC_PLLCFGR_PLLM_1 0x00000002U
+#define RCC_PLLCFGR_PLLM_2 0x00000004U
+#define RCC_PLLCFGR_PLLM_3 0x00000008U
+#define RCC_PLLCFGR_PLLM_4 0x00000010U
+#define RCC_PLLCFGR_PLLM_5 0x00000020U
+
+#define RCC_PLLCFGR_PLLN 0x00007FC0U
+#define RCC_PLLCFGR_PLLN_0 0x00000040U
+#define RCC_PLLCFGR_PLLN_1 0x00000080U
+#define RCC_PLLCFGR_PLLN_2 0x00000100U
+#define RCC_PLLCFGR_PLLN_3 0x00000200U
+#define RCC_PLLCFGR_PLLN_4 0x00000400U
+#define RCC_PLLCFGR_PLLN_5 0x00000800U
+#define RCC_PLLCFGR_PLLN_6 0x00001000U
+#define RCC_PLLCFGR_PLLN_7 0x00002000U
+#define RCC_PLLCFGR_PLLN_8 0x00004000U
+
+#define RCC_PLLCFGR_PLLP 0x00030000U
+#define RCC_PLLCFGR_PLLP_0 0x00010000U
+#define RCC_PLLCFGR_PLLP_1 0x00020000U
+
+#define RCC_PLLCFGR_PLLSRC 0x00400000U
+#define RCC_PLLCFGR_PLLSRC_HSE 0x00400000U
+#define RCC_PLLCFGR_PLLSRC_HSI 0x00000000U
+
+#define RCC_PLLCFGR_PLLQ 0x0F000000U
+#define RCC_PLLCFGR_PLLQ_0 0x01000000U
+#define RCC_PLLCFGR_PLLQ_1 0x02000000U
+#define RCC_PLLCFGR_PLLQ_2 0x04000000U
+#define RCC_PLLCFGR_PLLQ_3 0x08000000U
+
+/******************** Bit definition for RCC_CFGR register ******************/
+/*!< SW configuration */
+#define RCC_CFGR_SW 0x00000003U /*!< SW[1:0] bits (System clock Switch) */
+#define RCC_CFGR_SW_0 0x00000001U /*!< Bit 0 */
+#define RCC_CFGR_SW_1 0x00000002U /*!< Bit 1 */
+
+#define RCC_CFGR_SW_HSI 0x00000000U /*!< HSI selected as system clock */
+#define RCC_CFGR_SW_HSE 0x00000001U /*!< HSE selected as system clock */
+#define RCC_CFGR_SW_PLL 0x00000002U /*!< PLL selected as system clock */
+
+/*!< SWS configuration */
+#define RCC_CFGR_SWS 0x0000000CU /*!< SWS[1:0] bits (System Clock Switch Status) */
+#define RCC_CFGR_SWS_0 0x00000004U /*!< Bit 0 */
+#define RCC_CFGR_SWS_1 0x00000008U /*!< Bit 1 */
+
+#define RCC_CFGR_SWS_HSI 0x00000000U /*!< HSI oscillator used as system clock */
+#define RCC_CFGR_SWS_HSE 0x00000004U /*!< HSE oscillator used as system clock */
+#define RCC_CFGR_SWS_PLL 0x00000008U /*!< PLL used as system clock */
+
+/*!< HPRE configuration */
+#define RCC_CFGR_HPRE 0x000000F0U /*!< HPRE[3:0] bits (AHB prescaler) */
+#define RCC_CFGR_HPRE_0 0x00000010U /*!< Bit 0 */
+#define RCC_CFGR_HPRE_1 0x00000020U /*!< Bit 1 */
+#define RCC_CFGR_HPRE_2 0x00000040U /*!< Bit 2 */
+#define RCC_CFGR_HPRE_3 0x00000080U /*!< Bit 3 */
+
+#define RCC_CFGR_HPRE_DIV1 0x00000000U /*!< SYSCLK not divided */
+#define RCC_CFGR_HPRE_DIV2 0x00000080U /*!< SYSCLK divided by 2 */
+#define RCC_CFGR_HPRE_DIV4 0x00000090U /*!< SYSCLK divided by 4 */
+#define RCC_CFGR_HPRE_DIV8 0x000000A0U /*!< SYSCLK divided by 8 */
+#define RCC_CFGR_HPRE_DIV16 0x000000B0U /*!< SYSCLK divided by 16 */
+#define RCC_CFGR_HPRE_DIV64 0x000000C0U /*!< SYSCLK divided by 64 */
+#define RCC_CFGR_HPRE_DIV128 0x000000D0U /*!< SYSCLK divided by 128 */
+#define RCC_CFGR_HPRE_DIV256 0x000000E0U /*!< SYSCLK divided by 256 */
+#define RCC_CFGR_HPRE_DIV512 0x000000F0U /*!< SYSCLK divided by 512 */
+
+/*!< PPRE1 configuration */
+#define RCC_CFGR_PPRE1 0x00001C00U /*!< PRE1[2:0] bits (APB1 prescaler) */
+#define RCC_CFGR_PPRE1_0 0x00000400U /*!< Bit 0 */
+#define RCC_CFGR_PPRE1_1 0x00000800U /*!< Bit 1 */
+#define RCC_CFGR_PPRE1_2 0x00001000U /*!< Bit 2 */
+
+#define RCC_CFGR_PPRE1_DIV1 0x00000000U /*!< HCLK not divided */
+#define RCC_CFGR_PPRE1_DIV2 0x00001000U /*!< HCLK divided by 2 */
+#define RCC_CFGR_PPRE1_DIV4 0x00001400U /*!< HCLK divided by 4 */
+#define RCC_CFGR_PPRE1_DIV8 0x00001800U /*!< HCLK divided by 8 */
+#define RCC_CFGR_PPRE1_DIV16 0x00001C00U /*!< HCLK divided by 16 */
+
+/*!< PPRE2 configuration */
+#define RCC_CFGR_PPRE2 0x0000E000U /*!< PRE2[2:0] bits (APB2 prescaler) */
+#define RCC_CFGR_PPRE2_0 0x00002000U /*!< Bit 0 */
+#define RCC_CFGR_PPRE2_1 0x00004000U /*!< Bit 1 */
+#define RCC_CFGR_PPRE2_2 0x00008000U /*!< Bit 2 */
+
+#define RCC_CFGR_PPRE2_DIV1 0x00000000U /*!< HCLK not divided */
+#define RCC_CFGR_PPRE2_DIV2 0x00008000U /*!< HCLK divided by 2 */
+#define RCC_CFGR_PPRE2_DIV4 0x0000A000U /*!< HCLK divided by 4 */
+#define RCC_CFGR_PPRE2_DIV8 0x0000C000U /*!< HCLK divided by 8 */
+#define RCC_CFGR_PPRE2_DIV16 0x0000E000U /*!< HCLK divided by 16 */
+
+/*!< RTCPRE configuration */
+#define RCC_CFGR_RTCPRE 0x001F0000U
+#define RCC_CFGR_RTCPRE_0 0x00010000U
+#define RCC_CFGR_RTCPRE_1 0x00020000U
+#define RCC_CFGR_RTCPRE_2 0x00040000U
+#define RCC_CFGR_RTCPRE_3 0x00080000U
+#define RCC_CFGR_RTCPRE_4 0x00100000U
+
+/*!< MCO1 configuration */
+#define RCC_CFGR_MCO1 0x00600000U
+#define RCC_CFGR_MCO1_0 0x00200000U
+#define RCC_CFGR_MCO1_1 0x00400000U
+
+#define RCC_CFGR_I2SSRC 0x00800000U
+
+#define RCC_CFGR_MCO1PRE 0x07000000U
+#define RCC_CFGR_MCO1PRE_0 0x01000000U
+#define RCC_CFGR_MCO1PRE_1 0x02000000U
+#define RCC_CFGR_MCO1PRE_2 0x04000000U
+
+#define RCC_CFGR_MCO2PRE 0x38000000U
+#define RCC_CFGR_MCO2PRE_0 0x08000000U
+#define RCC_CFGR_MCO2PRE_1 0x10000000U
+#define RCC_CFGR_MCO2PRE_2 0x20000000U
+
+#define RCC_CFGR_MCO2 0xC0000000U
+#define RCC_CFGR_MCO2_0 0x40000000U
+#define RCC_CFGR_MCO2_1 0x80000000U
+
+/******************** Bit definition for RCC_CIR register *******************/
+#define RCC_CIR_LSIRDYF 0x00000001U
+#define RCC_CIR_LSERDYF 0x00000002U
+#define RCC_CIR_HSIRDYF 0x00000004U
+#define RCC_CIR_HSERDYF 0x00000008U
+#define RCC_CIR_PLLRDYF 0x00000010U
+#define RCC_CIR_PLLI2SRDYF 0x00000020U
+#define RCC_CIR_PLLSAIRDYF 0x00000040U
+#define RCC_CIR_CSSF 0x00000080U
+#define RCC_CIR_LSIRDYIE 0x00000100U
+#define RCC_CIR_LSERDYIE 0x00000200U
+#define RCC_CIR_HSIRDYIE 0x00000400U
+#define RCC_CIR_HSERDYIE 0x00000800U
+#define RCC_CIR_PLLRDYIE 0x00001000U
+#define RCC_CIR_PLLI2SRDYIE 0x00002000U
+#define RCC_CIR_PLLSAIRDYIE 0x00004000U
+#define RCC_CIR_LSIRDYC 0x00010000U
+#define RCC_CIR_LSERDYC 0x00020000U
+#define RCC_CIR_HSIRDYC 0x00040000U
+#define RCC_CIR_HSERDYC 0x00080000U
+#define RCC_CIR_PLLRDYC 0x00100000U
+#define RCC_CIR_PLLI2SRDYC 0x00200000U
+#define RCC_CIR_PLLSAIRDYC 0x00400000U
+#define RCC_CIR_CSSC 0x00800000U
+
+/******************** Bit definition for RCC_AHB1RSTR register **************/
+#define RCC_AHB1RSTR_GPIOARST 0x00000001U
+#define RCC_AHB1RSTR_GPIOBRST 0x00000002U
+#define RCC_AHB1RSTR_GPIOCRST 0x00000004U
+#define RCC_AHB1RSTR_GPIODRST 0x00000008U
+#define RCC_AHB1RSTR_GPIOERST 0x00000010U
+#define RCC_AHB1RSTR_GPIOFRST 0x00000020U
+#define RCC_AHB1RSTR_GPIOGRST 0x00000040U
+#define RCC_AHB1RSTR_GPIOHRST 0x00000080U
+#define RCC_AHB1RSTR_GPIOIRST 0x00000100U
+#define RCC_AHB1RSTR_GPIOJRST 0x00000200U
+#define RCC_AHB1RSTR_GPIOKRST 0x00000400U
+#define RCC_AHB1RSTR_CRCRST 0x00001000U
+#define RCC_AHB1RSTR_DMA1RST 0x00200000U
+#define RCC_AHB1RSTR_DMA2RST 0x00400000U
+#define RCC_AHB1RSTR_DMA2DRST 0x00800000U
+#define RCC_AHB1RSTR_ETHMACRST 0x02000000U
+#define RCC_AHB1RSTR_OTGHRST 0x20000000U
+
+/******************** Bit definition for RCC_AHB2RSTR register **************/
+#define RCC_AHB2RSTR_DCMIRST 0x00000001U
+#define RCC_AHB2RSTR_CRYPRST 0x00000010U
+#define RCC_AHB2RSTR_HASHRST 0x00000020U
+ /* maintained for legacy purpose */
+ #define RCC_AHB2RSTR_HSAHRST RCC_AHB2RSTR_HASHRST
+#define RCC_AHB2RSTR_RNGRST 0x00000040U
+#define RCC_AHB2RSTR_OTGFSRST 0x00000080U
+
+/******************** Bit definition for RCC_AHB3RSTR register **************/
+#define RCC_AHB3RSTR_FMCRST 0x00000001U
+
+/******************** Bit definition for RCC_APB1RSTR register **************/
+#define RCC_APB1RSTR_TIM2RST 0x00000001U
+#define RCC_APB1RSTR_TIM3RST 0x00000002U
+#define RCC_APB1RSTR_TIM4RST 0x00000004U
+#define RCC_APB1RSTR_TIM5RST 0x00000008U
+#define RCC_APB1RSTR_TIM6RST 0x00000010U
+#define RCC_APB1RSTR_TIM7RST 0x00000020U
+#define RCC_APB1RSTR_TIM12RST 0x00000040U
+#define RCC_APB1RSTR_TIM13RST 0x00000080U
+#define RCC_APB1RSTR_TIM14RST 0x00000100U
+#define RCC_APB1RSTR_WWDGRST 0x00000800U
+#define RCC_APB1RSTR_SPI2RST 0x00004000U
+#define RCC_APB1RSTR_SPI3RST 0x00008000U
+#define RCC_APB1RSTR_USART2RST 0x00020000U
+#define RCC_APB1RSTR_USART3RST 0x00040000U
+#define RCC_APB1RSTR_UART4RST 0x00080000U
+#define RCC_APB1RSTR_UART5RST 0x00100000U
+#define RCC_APB1RSTR_I2C1RST 0x00200000U
+#define RCC_APB1RSTR_I2C2RST 0x00400000U
+#define RCC_APB1RSTR_I2C3RST 0x00800000U
+#define RCC_APB1RSTR_CAN1RST 0x02000000U
+#define RCC_APB1RSTR_CAN2RST 0x04000000U
+#define RCC_APB1RSTR_PWRRST 0x10000000U
+#define RCC_APB1RSTR_DACRST 0x20000000U
+#define RCC_APB1RSTR_UART7RST 0x40000000U
+#define RCC_APB1RSTR_UART8RST 0x80000000U
+
+/******************** Bit definition for RCC_APB2RSTR register **************/
+#define RCC_APB2RSTR_TIM1RST 0x00000001U
+#define RCC_APB2RSTR_TIM8RST 0x00000002U
+#define RCC_APB2RSTR_USART1RST 0x00000010U
+#define RCC_APB2RSTR_USART6RST 0x00000020U
+#define RCC_APB2RSTR_ADCRST 0x00000100U
+#define RCC_APB2RSTR_SDIORST 0x00000800U
+#define RCC_APB2RSTR_SPI1RST 0x00001000U
+#define RCC_APB2RSTR_SPI4RST 0x00002000U
+#define RCC_APB2RSTR_SYSCFGRST 0x00004000U
+#define RCC_APB2RSTR_TIM9RST 0x00010000U
+#define RCC_APB2RSTR_TIM10RST 0x00020000U
+#define RCC_APB2RSTR_TIM11RST 0x00040000U
+#define RCC_APB2RSTR_SPI5RST 0x00100000U
+#define RCC_APB2RSTR_SPI6RST 0x00200000U
+#define RCC_APB2RSTR_SAI1RST 0x00400000U
+
+/* Old SPI1RST bit definition, maintained for legacy purpose */
+#define RCC_APB2RSTR_SPI1 RCC_APB2RSTR_SPI1RST
+
+/******************** Bit definition for RCC_AHB1ENR register ***************/
+#define RCC_AHB1ENR_GPIOAEN 0x00000001U
+#define RCC_AHB1ENR_GPIOBEN 0x00000002U
+#define RCC_AHB1ENR_GPIOCEN 0x00000004U
+#define RCC_AHB1ENR_GPIODEN 0x00000008U
+#define RCC_AHB1ENR_GPIOEEN 0x00000010U
+#define RCC_AHB1ENR_GPIOFEN 0x00000020U
+#define RCC_AHB1ENR_GPIOGEN 0x00000040U
+#define RCC_AHB1ENR_GPIOHEN 0x00000080U
+#define RCC_AHB1ENR_GPIOIEN 0x00000100U
+#define RCC_AHB1ENR_GPIOJEN 0x00000200U
+#define RCC_AHB1ENR_GPIOKEN 0x00000400U
+
+#define RCC_AHB1ENR_CRCEN 0x00001000U
+#define RCC_AHB1ENR_BKPSRAMEN 0x00040000U
+#define RCC_AHB1ENR_CCMDATARAMEN 0x00100000U
+#define RCC_AHB1ENR_DMA1EN 0x00200000U
+#define RCC_AHB1ENR_DMA2EN 0x00400000U
+#define RCC_AHB1ENR_DMA2DEN 0x00800000U
+
+#define RCC_AHB1ENR_ETHMACEN 0x02000000U
+#define RCC_AHB1ENR_ETHMACTXEN 0x04000000U
+#define RCC_AHB1ENR_ETHMACRXEN 0x08000000U
+#define RCC_AHB1ENR_ETHMACPTPEN 0x10000000U
+#define RCC_AHB1ENR_OTGHSEN 0x20000000U
+#define RCC_AHB1ENR_OTGHSULPIEN 0x40000000U
+
+/******************** Bit definition for RCC_AHB2ENR register ***************/
+#define RCC_AHB2ENR_DCMIEN 0x00000001U
+#define RCC_AHB2ENR_CRYPEN 0x00000010U
+#define RCC_AHB2ENR_HASHEN 0x00000020U
+#define RCC_AHB2ENR_RNGEN 0x00000040U
+#define RCC_AHB2ENR_OTGFSEN 0x00000080U
+
+/******************** Bit definition for RCC_AHB3ENR register ***************/
+#define RCC_AHB3ENR_FMCEN 0x00000001U
+
+/******************** Bit definition for RCC_APB1ENR register ***************/
+#define RCC_APB1ENR_TIM2EN 0x00000001U
+#define RCC_APB1ENR_TIM3EN 0x00000002U
+#define RCC_APB1ENR_TIM4EN 0x00000004U
+#define RCC_APB1ENR_TIM5EN 0x00000008U
+#define RCC_APB1ENR_TIM6EN 0x00000010U
+#define RCC_APB1ENR_TIM7EN 0x00000020U
+#define RCC_APB1ENR_TIM12EN 0x00000040U
+#define RCC_APB1ENR_TIM13EN 0x00000080U
+#define RCC_APB1ENR_TIM14EN 0x00000100U
+#define RCC_APB1ENR_WWDGEN 0x00000800U
+#define RCC_APB1ENR_SPI2EN 0x00004000U
+#define RCC_APB1ENR_SPI3EN 0x00008000U
+#define RCC_APB1ENR_USART2EN 0x00020000U
+#define RCC_APB1ENR_USART3EN 0x00040000U
+#define RCC_APB1ENR_UART4EN 0x00080000U
+#define RCC_APB1ENR_UART5EN 0x00100000U
+#define RCC_APB1ENR_I2C1EN 0x00200000U
+#define RCC_APB1ENR_I2C2EN 0x00400000U
+#define RCC_APB1ENR_I2C3EN 0x00800000U
+#define RCC_APB1ENR_CAN1EN 0x02000000U
+#define RCC_APB1ENR_CAN2EN 0x04000000U
+#define RCC_APB1ENR_PWREN 0x10000000U
+#define RCC_APB1ENR_DACEN 0x20000000U
+#define RCC_APB1ENR_UART7EN 0x40000000U
+#define RCC_APB1ENR_UART8EN 0x80000000U
+
+/******************** Bit definition for RCC_APB2ENR register ***************/
+#define RCC_APB2ENR_TIM1EN 0x00000001U
+#define RCC_APB2ENR_TIM8EN 0x00000002U
+#define RCC_APB2ENR_USART1EN 0x00000010U
+#define RCC_APB2ENR_USART6EN 0x00000020U
+#define RCC_APB2ENR_ADC1EN 0x00000100U
+#define RCC_APB2ENR_ADC2EN 0x00000200U
+#define RCC_APB2ENR_ADC3EN 0x00000400U
+#define RCC_APB2ENR_SDIOEN 0x00000800U
+#define RCC_APB2ENR_SPI1EN 0x00001000U
+#define RCC_APB2ENR_SPI4EN 0x00002000U
+#define RCC_APB2ENR_SYSCFGEN 0x00004000U
+#define RCC_APB2ENR_TIM9EN 0x00010000U
+#define RCC_APB2ENR_TIM10EN 0x00020000U
+#define RCC_APB2ENR_TIM11EN 0x00040000U
+#define RCC_APB2ENR_SPI5EN 0x00100000U
+#define RCC_APB2ENR_SPI6EN 0x00200000U
+#define RCC_APB2ENR_SAI1EN 0x00400000U
+
+/******************** Bit definition for RCC_AHB1LPENR register *************/
+#define RCC_AHB1LPENR_GPIOALPEN 0x00000001U
+#define RCC_AHB1LPENR_GPIOBLPEN 0x00000002U
+#define RCC_AHB1LPENR_GPIOCLPEN 0x00000004U
+#define RCC_AHB1LPENR_GPIODLPEN 0x00000008U
+#define RCC_AHB1LPENR_GPIOELPEN 0x00000010U
+#define RCC_AHB1LPENR_GPIOFLPEN 0x00000020U
+#define RCC_AHB1LPENR_GPIOGLPEN 0x00000040U
+#define RCC_AHB1LPENR_GPIOHLPEN 0x00000080U
+#define RCC_AHB1LPENR_GPIOILPEN 0x00000100U
+#define RCC_AHB1LPENR_GPIOJLPEN 0x00000200U
+#define RCC_AHB1LPENR_GPIOKLPEN 0x00000400U
+
+#define RCC_AHB1LPENR_CRCLPEN 0x00001000U
+#define RCC_AHB1LPENR_FLITFLPEN 0x00008000U
+#define RCC_AHB1LPENR_SRAM1LPEN 0x00010000U
+#define RCC_AHB1LPENR_SRAM2LPEN 0x00020000U
+#define RCC_AHB1LPENR_BKPSRAMLPEN 0x00040000U
+#define RCC_AHB1LPENR_SRAM3LPEN 0x00080000U
+#define RCC_AHB1LPENR_DMA1LPEN 0x00200000U
+#define RCC_AHB1LPENR_DMA2LPEN 0x00400000U
+#define RCC_AHB1LPENR_DMA2DLPEN 0x00800000U
+
+#define RCC_AHB1LPENR_ETHMACLPEN 0x02000000U
+#define RCC_AHB1LPENR_ETHMACTXLPEN 0x04000000U
+#define RCC_AHB1LPENR_ETHMACRXLPEN 0x08000000U
+#define RCC_AHB1LPENR_ETHMACPTPLPEN 0x10000000U
+#define RCC_AHB1LPENR_OTGHSLPEN 0x20000000U
+#define RCC_AHB1LPENR_OTGHSULPILPEN 0x40000000U
+
+/******************** Bit definition for RCC_AHB2LPENR register *************/
+#define RCC_AHB2LPENR_DCMILPEN 0x00000001U
+#define RCC_AHB2LPENR_CRYPLPEN 0x00000010U
+#define RCC_AHB2LPENR_HASHLPEN 0x00000020U
+#define RCC_AHB2LPENR_RNGLPEN 0x00000040U
+#define RCC_AHB2LPENR_OTGFSLPEN 0x00000080U
+
+/******************** Bit definition for RCC_AHB3LPENR register *************/
+#define RCC_AHB3LPENR_FMCLPEN 0x00000001U
+
+/******************** Bit definition for RCC_APB1LPENR register *************/
+#define RCC_APB1LPENR_TIM2LPEN 0x00000001U
+#define RCC_APB1LPENR_TIM3LPEN 0x00000002U
+#define RCC_APB1LPENR_TIM4LPEN 0x00000004U
+#define RCC_APB1LPENR_TIM5LPEN 0x00000008U
+#define RCC_APB1LPENR_TIM6LPEN 0x00000010U
+#define RCC_APB1LPENR_TIM7LPEN 0x00000020U
+#define RCC_APB1LPENR_TIM12LPEN 0x00000040U
+#define RCC_APB1LPENR_TIM13LPEN 0x00000080U
+#define RCC_APB1LPENR_TIM14LPEN 0x00000100U
+#define RCC_APB1LPENR_WWDGLPEN 0x00000800U
+#define RCC_APB1LPENR_SPI2LPEN 0x00004000U
+#define RCC_APB1LPENR_SPI3LPEN 0x00008000U
+#define RCC_APB1LPENR_USART2LPEN 0x00020000U
+#define RCC_APB1LPENR_USART3LPEN 0x00040000U
+#define RCC_APB1LPENR_UART4LPEN 0x00080000U
+#define RCC_APB1LPENR_UART5LPEN 0x00100000U
+#define RCC_APB1LPENR_I2C1LPEN 0x00200000U
+#define RCC_APB1LPENR_I2C2LPEN 0x00400000U
+#define RCC_APB1LPENR_I2C3LPEN 0x00800000U
+#define RCC_APB1LPENR_CAN1LPEN 0x02000000U
+#define RCC_APB1LPENR_CAN2LPEN 0x04000000U
+#define RCC_APB1LPENR_PWRLPEN 0x10000000U
+#define RCC_APB1LPENR_DACLPEN 0x20000000U
+#define RCC_APB1LPENR_UART7LPEN 0x40000000U
+#define RCC_APB1LPENR_UART8LPEN 0x80000000U
+
+/******************** Bit definition for RCC_APB2LPENR register *************/
+#define RCC_APB2LPENR_TIM1LPEN 0x00000001U
+#define RCC_APB2LPENR_TIM8LPEN 0x00000002U
+#define RCC_APB2LPENR_USART1LPEN 0x00000010U
+#define RCC_APB2LPENR_USART6LPEN 0x00000020U
+#define RCC_APB2LPENR_ADC1LPEN 0x00000100U
+#define RCC_APB2LPENR_ADC2LPEN 0x00000200U
+#define RCC_APB2LPENR_ADC3LPEN 0x00000400U
+#define RCC_APB2LPENR_SDIOLPEN 0x00000800U
+#define RCC_APB2LPENR_SPI1LPEN 0x00001000U
+#define RCC_APB2LPENR_SPI4LPEN 0x00002000U
+#define RCC_APB2LPENR_SYSCFGLPEN 0x00004000U
+#define RCC_APB2LPENR_TIM9LPEN 0x00010000U
+#define RCC_APB2LPENR_TIM10LPEN 0x00020000U
+#define RCC_APB2LPENR_TIM11LPEN 0x00040000U
+#define RCC_APB2LPENR_SPI5LPEN 0x00100000U
+#define RCC_APB2LPENR_SPI6LPEN 0x00200000U
+#define RCC_APB2LPENR_SAI1LPEN 0x00400000U
+
+/******************** Bit definition for RCC_BDCR register ******************/
+#define RCC_BDCR_LSEON 0x00000001U
+#define RCC_BDCR_LSERDY 0x00000002U
+#define RCC_BDCR_LSEBYP 0x00000004U
+
+#define RCC_BDCR_RTCSEL 0x00000300U
+#define RCC_BDCR_RTCSEL_0 0x00000100U
+#define RCC_BDCR_RTCSEL_1 0x00000200U
+
+#define RCC_BDCR_RTCEN 0x00008000U
+#define RCC_BDCR_BDRST 0x00010000U
+
+/******************** Bit definition for RCC_CSR register *******************/
+#define RCC_CSR_LSION 0x00000001U
+#define RCC_CSR_LSIRDY 0x00000002U
+#define RCC_CSR_RMVF 0x01000000U
+#define RCC_CSR_BORRSTF 0x02000000U
+#define RCC_CSR_PADRSTF 0x04000000U
+#define RCC_CSR_PORRSTF 0x08000000U
+#define RCC_CSR_SFTRSTF 0x10000000U
+#define RCC_CSR_WDGRSTF 0x20000000U
+#define RCC_CSR_WWDGRSTF 0x40000000U
+#define RCC_CSR_LPWRRSTF 0x80000000U
+
+/******************** Bit definition for RCC_SSCGR register *****************/
+#define RCC_SSCGR_MODPER 0x00001FFFU
+#define RCC_SSCGR_INCSTEP 0x0FFFE000U
+#define RCC_SSCGR_SPREADSEL 0x40000000U
+#define RCC_SSCGR_SSCGEN 0x80000000U
+
+/******************** Bit definition for RCC_PLLI2SCFGR register ************/
+#define RCC_PLLI2SCFGR_PLLI2SN 0x00007FC0U
+#define RCC_PLLI2SCFGR_PLLI2SN_0 0x00000040U
+#define RCC_PLLI2SCFGR_PLLI2SN_1 0x00000080U
+#define RCC_PLLI2SCFGR_PLLI2SN_2 0x00000100U
+#define RCC_PLLI2SCFGR_PLLI2SN_3 0x00000200U
+#define RCC_PLLI2SCFGR_PLLI2SN_4 0x00000400U
+#define RCC_PLLI2SCFGR_PLLI2SN_5 0x00000800U
+#define RCC_PLLI2SCFGR_PLLI2SN_6 0x00001000U
+#define RCC_PLLI2SCFGR_PLLI2SN_7 0x00002000U
+#define RCC_PLLI2SCFGR_PLLI2SN_8 0x00004000U
+
+#define RCC_PLLI2SCFGR_PLLI2SQ 0x0F000000U
+#define RCC_PLLI2SCFGR_PLLI2SQ_0 0x01000000U
+#define RCC_PLLI2SCFGR_PLLI2SQ_1 0x02000000U
+#define RCC_PLLI2SCFGR_PLLI2SQ_2 0x04000000U
+#define RCC_PLLI2SCFGR_PLLI2SQ_3 0x08000000U
+
+#define RCC_PLLI2SCFGR_PLLI2SR 0x70000000U
+#define RCC_PLLI2SCFGR_PLLI2SR_0 0x10000000U
+#define RCC_PLLI2SCFGR_PLLI2SR_1 0x20000000U
+#define RCC_PLLI2SCFGR_PLLI2SR_2 0x40000000U
+
+
+/******************** Bit definition for RCC_PLLSAICFGR register ************/
+#define RCC_PLLSAICFGR_PLLSAIN 0x00007FC0U
+#define RCC_PLLSAICFGR_PLLSAIN_0 0x00000040U
+#define RCC_PLLSAICFGR_PLLSAIN_1 0x00000080U
+#define RCC_PLLSAICFGR_PLLSAIN_2 0x00000100U
+#define RCC_PLLSAICFGR_PLLSAIN_3 0x00000200U
+#define RCC_PLLSAICFGR_PLLSAIN_4 0x00000400U
+#define RCC_PLLSAICFGR_PLLSAIN_5 0x00000800U
+#define RCC_PLLSAICFGR_PLLSAIN_6 0x00001000U
+#define RCC_PLLSAICFGR_PLLSAIN_7 0x00002000U
+#define RCC_PLLSAICFGR_PLLSAIN_8 0x00004000U
+
+#define RCC_PLLSAICFGR_PLLSAIQ 0x0F000000U
+#define RCC_PLLSAICFGR_PLLSAIQ_0 0x01000000U
+#define RCC_PLLSAICFGR_PLLSAIQ_1 0x02000000U
+#define RCC_PLLSAICFGR_PLLSAIQ_2 0x04000000U
+#define RCC_PLLSAICFGR_PLLSAIQ_3 0x08000000U
+
+#define RCC_PLLSAICFGR_PLLSAIR 0x70000000U
+#define RCC_PLLSAICFGR_PLLSAIR_0 0x10000000U
+#define RCC_PLLSAICFGR_PLLSAIR_1 0x20000000U
+#define RCC_PLLSAICFGR_PLLSAIR_2 0x40000000U
+
+/******************** Bit definition for RCC_DCKCFGR register ***************/
+#define RCC_DCKCFGR_PLLI2SDIVQ 0x0000001FU
+#define RCC_DCKCFGR_PLLSAIDIVQ 0x00001F00U
+#define RCC_DCKCFGR_PLLSAIDIVR 0x00030000U
+#define RCC_DCKCFGR_SAI1ASRC 0x00300000U
+#define RCC_DCKCFGR_SAI1ASRC_0 0x00100000U
+#define RCC_DCKCFGR_SAI1ASRC_1 0x00200000U
+#define RCC_DCKCFGR_SAI1BSRC 0x00C00000U
+#define RCC_DCKCFGR_SAI1BSRC_0 0x00400000U
+#define RCC_DCKCFGR_SAI1BSRC_1 0x00800000U
+#define RCC_DCKCFGR_TIMPRE 0x01000000U
+
+
+/******************************************************************************/
+/* */
+/* RNG */
+/* */
+/******************************************************************************/
+/******************** Bits definition for RNG_CR register *******************/
+#define RNG_CR_RNGEN 0x00000004U
+#define RNG_CR_IE 0x00000008U
+
+/******************** Bits definition for RNG_SR register *******************/
+#define RNG_SR_DRDY 0x00000001U
+#define RNG_SR_CECS 0x00000002U
+#define RNG_SR_SECS 0x00000004U
+#define RNG_SR_CEIS 0x00000020U
+#define RNG_SR_SEIS 0x00000040U
+
+/******************************************************************************/
+/* */
+/* Real-Time Clock (RTC) */
+/* */
+/******************************************************************************/
+/******************** Bits definition for RTC_TR register *******************/
+#define RTC_TR_PM 0x00400000U
+#define RTC_TR_HT 0x00300000U
+#define RTC_TR_HT_0 0x00100000U
+#define RTC_TR_HT_1 0x00200000U
+#define RTC_TR_HU 0x000F0000U
+#define RTC_TR_HU_0 0x00010000U
+#define RTC_TR_HU_1 0x00020000U
+#define RTC_TR_HU_2 0x00040000U
+#define RTC_TR_HU_3 0x00080000U
+#define RTC_TR_MNT 0x00007000U
+#define RTC_TR_MNT_0 0x00001000U
+#define RTC_TR_MNT_1 0x00002000U
+#define RTC_TR_MNT_2 0x00004000U
+#define RTC_TR_MNU 0x00000F00U
+#define RTC_TR_MNU_0 0x00000100U
+#define RTC_TR_MNU_1 0x00000200U
+#define RTC_TR_MNU_2 0x00000400U
+#define RTC_TR_MNU_3 0x00000800U
+#define RTC_TR_ST 0x00000070U
+#define RTC_TR_ST_0 0x00000010U
+#define RTC_TR_ST_1 0x00000020U
+#define RTC_TR_ST_2 0x00000040U
+#define RTC_TR_SU 0x0000000FU
+#define RTC_TR_SU_0 0x00000001U
+#define RTC_TR_SU_1 0x00000002U
+#define RTC_TR_SU_2 0x00000004U
+#define RTC_TR_SU_3 0x00000008U
+
+/******************** Bits definition for RTC_DR register *******************/
+#define RTC_DR_YT 0x00F00000U
+#define RTC_DR_YT_0 0x00100000U
+#define RTC_DR_YT_1 0x00200000U
+#define RTC_DR_YT_2 0x00400000U
+#define RTC_DR_YT_3 0x00800000U
+#define RTC_DR_YU 0x000F0000U
+#define RTC_DR_YU_0 0x00010000U
+#define RTC_DR_YU_1 0x00020000U
+#define RTC_DR_YU_2 0x00040000U
+#define RTC_DR_YU_3 0x00080000U
+#define RTC_DR_WDU 0x0000E000U
+#define RTC_DR_WDU_0 0x00002000U
+#define RTC_DR_WDU_1 0x00004000U
+#define RTC_DR_WDU_2 0x00008000U
+#define RTC_DR_MT 0x00001000U
+#define RTC_DR_MU 0x00000F00U
+#define RTC_DR_MU_0 0x00000100U
+#define RTC_DR_MU_1 0x00000200U
+#define RTC_DR_MU_2 0x00000400U
+#define RTC_DR_MU_3 0x00000800U
+#define RTC_DR_DT 0x00000030U
+#define RTC_DR_DT_0 0x00000010U
+#define RTC_DR_DT_1 0x00000020U
+#define RTC_DR_DU 0x0000000FU
+#define RTC_DR_DU_0 0x00000001U
+#define RTC_DR_DU_1 0x00000002U
+#define RTC_DR_DU_2 0x00000004U
+#define RTC_DR_DU_3 0x00000008U
+
+/******************** Bits definition for RTC_CR register *******************/
+#define RTC_CR_COE 0x00800000U
+#define RTC_CR_OSEL 0x00600000U
+#define RTC_CR_OSEL_0 0x00200000U
+#define RTC_CR_OSEL_1 0x00400000U
+#define RTC_CR_POL 0x00100000U
+#define RTC_CR_COSEL 0x00080000U
+#define RTC_CR_BCK 0x00040000U
+#define RTC_CR_SUB1H 0x00020000U
+#define RTC_CR_ADD1H 0x00010000U
+#define RTC_CR_TSIE 0x00008000U
+#define RTC_CR_WUTIE 0x00004000U
+#define RTC_CR_ALRBIE 0x00002000U
+#define RTC_CR_ALRAIE 0x00001000U
+#define RTC_CR_TSE 0x00000800U
+#define RTC_CR_WUTE 0x00000400U
+#define RTC_CR_ALRBE 0x00000200U
+#define RTC_CR_ALRAE 0x00000100U
+#define RTC_CR_DCE 0x00000080U
+#define RTC_CR_FMT 0x00000040U
+#define RTC_CR_BYPSHAD 0x00000020U
+#define RTC_CR_REFCKON 0x00000010U
+#define RTC_CR_TSEDGE 0x00000008U
+#define RTC_CR_WUCKSEL 0x00000007U
+#define RTC_CR_WUCKSEL_0 0x00000001U
+#define RTC_CR_WUCKSEL_1 0x00000002U
+#define RTC_CR_WUCKSEL_2 0x00000004U
+
+/******************** Bits definition for RTC_ISR register ******************/
+#define RTC_ISR_RECALPF 0x00010000U
+#define RTC_ISR_TAMP1F 0x00002000U
+#define RTC_ISR_TAMP2F 0x00004000U
+#define RTC_ISR_TSOVF 0x00001000U
+#define RTC_ISR_TSF 0x00000800U
+#define RTC_ISR_WUTF 0x00000400U
+#define RTC_ISR_ALRBF 0x00000200U
+#define RTC_ISR_ALRAF 0x00000100U
+#define RTC_ISR_INIT 0x00000080U
+#define RTC_ISR_INITF 0x00000040U
+#define RTC_ISR_RSF 0x00000020U
+#define RTC_ISR_INITS 0x00000010U
+#define RTC_ISR_SHPF 0x00000008U
+#define RTC_ISR_WUTWF 0x00000004U
+#define RTC_ISR_ALRBWF 0x00000002U
+#define RTC_ISR_ALRAWF 0x00000001U
+
+/******************** Bits definition for RTC_PRER register *****************/
+#define RTC_PRER_PREDIV_A 0x007F0000U
+#define RTC_PRER_PREDIV_S 0x00007FFFU
+
+/******************** Bits definition for RTC_WUTR register *****************/
+#define RTC_WUTR_WUT 0x0000FFFFU
+
+/******************** Bits definition for RTC_CALIBR register ***************/
+#define RTC_CALIBR_DCS 0x00000080U
+#define RTC_CALIBR_DC 0x0000001FU
+
+/******************** Bits definition for RTC_ALRMAR register ***************/
+#define RTC_ALRMAR_MSK4 0x80000000U
+#define RTC_ALRMAR_WDSEL 0x40000000U
+#define RTC_ALRMAR_DT 0x30000000U
+#define RTC_ALRMAR_DT_0 0x10000000U
+#define RTC_ALRMAR_DT_1 0x20000000U
+#define RTC_ALRMAR_DU 0x0F000000U
+#define RTC_ALRMAR_DU_0 0x01000000U
+#define RTC_ALRMAR_DU_1 0x02000000U
+#define RTC_ALRMAR_DU_2 0x04000000U
+#define RTC_ALRMAR_DU_3 0x08000000U
+#define RTC_ALRMAR_MSK3 0x00800000U
+#define RTC_ALRMAR_PM 0x00400000U
+#define RTC_ALRMAR_HT 0x00300000U
+#define RTC_ALRMAR_HT_0 0x00100000U
+#define RTC_ALRMAR_HT_1 0x00200000U
+#define RTC_ALRMAR_HU 0x000F0000U
+#define RTC_ALRMAR_HU_0 0x00010000U
+#define RTC_ALRMAR_HU_1 0x00020000U
+#define RTC_ALRMAR_HU_2 0x00040000U
+#define RTC_ALRMAR_HU_3 0x00080000U
+#define RTC_ALRMAR_MSK2 0x00008000U
+#define RTC_ALRMAR_MNT 0x00007000U
+#define RTC_ALRMAR_MNT_0 0x00001000U
+#define RTC_ALRMAR_MNT_1 0x00002000U
+#define RTC_ALRMAR_MNT_2 0x00004000U
+#define RTC_ALRMAR_MNU 0x00000F00U
+#define RTC_ALRMAR_MNU_0 0x00000100U
+#define RTC_ALRMAR_MNU_1 0x00000200U
+#define RTC_ALRMAR_MNU_2 0x00000400U
+#define RTC_ALRMAR_MNU_3 0x00000800U
+#define RTC_ALRMAR_MSK1 0x00000080U
+#define RTC_ALRMAR_ST 0x00000070U
+#define RTC_ALRMAR_ST_0 0x00000010U
+#define RTC_ALRMAR_ST_1 0x00000020U
+#define RTC_ALRMAR_ST_2 0x00000040U
+#define RTC_ALRMAR_SU 0x0000000FU
+#define RTC_ALRMAR_SU_0 0x00000001U
+#define RTC_ALRMAR_SU_1 0x00000002U
+#define RTC_ALRMAR_SU_2 0x00000004U
+#define RTC_ALRMAR_SU_3 0x00000008U
+
+/******************** Bits definition for RTC_ALRMBR register ***************/
+#define RTC_ALRMBR_MSK4 0x80000000U
+#define RTC_ALRMBR_WDSEL 0x40000000U
+#define RTC_ALRMBR_DT 0x30000000U
+#define RTC_ALRMBR_DT_0 0x10000000U
+#define RTC_ALRMBR_DT_1 0x20000000U
+#define RTC_ALRMBR_DU 0x0F000000U
+#define RTC_ALRMBR_DU_0 0x01000000U
+#define RTC_ALRMBR_DU_1 0x02000000U
+#define RTC_ALRMBR_DU_2 0x04000000U
+#define RTC_ALRMBR_DU_3 0x08000000U
+#define RTC_ALRMBR_MSK3 0x00800000U
+#define RTC_ALRMBR_PM 0x00400000U
+#define RTC_ALRMBR_HT 0x00300000U
+#define RTC_ALRMBR_HT_0 0x00100000U
+#define RTC_ALRMBR_HT_1 0x00200000U
+#define RTC_ALRMBR_HU 0x000F0000U
+#define RTC_ALRMBR_HU_0 0x00010000U
+#define RTC_ALRMBR_HU_1 0x00020000U
+#define RTC_ALRMBR_HU_2 0x00040000U
+#define RTC_ALRMBR_HU_3 0x00080000U
+#define RTC_ALRMBR_MSK2 0x00008000U
+#define RTC_ALRMBR_MNT 0x00007000U
+#define RTC_ALRMBR_MNT_0 0x00001000U
+#define RTC_ALRMBR_MNT_1 0x00002000U
+#define RTC_ALRMBR_MNT_2 0x00004000U
+#define RTC_ALRMBR_MNU 0x00000F00U
+#define RTC_ALRMBR_MNU_0 0x00000100U
+#define RTC_ALRMBR_MNU_1 0x00000200U
+#define RTC_ALRMBR_MNU_2 0x00000400U
+#define RTC_ALRMBR_MNU_3 0x00000800U
+#define RTC_ALRMBR_MSK1 0x00000080U
+#define RTC_ALRMBR_ST 0x00000070U
+#define RTC_ALRMBR_ST_0 0x00000010U
+#define RTC_ALRMBR_ST_1 0x00000020U
+#define RTC_ALRMBR_ST_2 0x00000040U
+#define RTC_ALRMBR_SU 0x0000000FU
+#define RTC_ALRMBR_SU_0 0x00000001U
+#define RTC_ALRMBR_SU_1 0x00000002U
+#define RTC_ALRMBR_SU_2 0x00000004U
+#define RTC_ALRMBR_SU_3 0x00000008U
+
+/******************** Bits definition for RTC_WPR register ******************/
+#define RTC_WPR_KEY 0x000000FFU
+
+/******************** Bits definition for RTC_SSR register ******************/
+#define RTC_SSR_SS 0x0000FFFFU
+
+/******************** Bits definition for RTC_SHIFTR register ***************/
+#define RTC_SHIFTR_SUBFS 0x00007FFFU
+#define RTC_SHIFTR_ADD1S 0x80000000U
+
+/******************** Bits definition for RTC_TSTR register *****************/
+#define RTC_TSTR_PM 0x00400000U
+#define RTC_TSTR_HT 0x00300000U
+#define RTC_TSTR_HT_0 0x00100000U
+#define RTC_TSTR_HT_1 0x00200000U
+#define RTC_TSTR_HU 0x000F0000U
+#define RTC_TSTR_HU_0 0x00010000U
+#define RTC_TSTR_HU_1 0x00020000U
+#define RTC_TSTR_HU_2 0x00040000U
+#define RTC_TSTR_HU_3 0x00080000U
+#define RTC_TSTR_MNT 0x00007000U
+#define RTC_TSTR_MNT_0 0x00001000U
+#define RTC_TSTR_MNT_1 0x00002000U
+#define RTC_TSTR_MNT_2 0x00004000U
+#define RTC_TSTR_MNU 0x00000F00U
+#define RTC_TSTR_MNU_0 0x00000100U
+#define RTC_TSTR_MNU_1 0x00000200U
+#define RTC_TSTR_MNU_2 0x00000400U
+#define RTC_TSTR_MNU_3 0x00000800U
+#define RTC_TSTR_ST 0x00000070U
+#define RTC_TSTR_ST_0 0x00000010U
+#define RTC_TSTR_ST_1 0x00000020U
+#define RTC_TSTR_ST_2 0x00000040U
+#define RTC_TSTR_SU 0x0000000FU
+#define RTC_TSTR_SU_0 0x00000001U
+#define RTC_TSTR_SU_1 0x00000002U
+#define RTC_TSTR_SU_2 0x00000004U
+#define RTC_TSTR_SU_3 0x00000008U
+
+/******************** Bits definition for RTC_TSDR register *****************/
+#define RTC_TSDR_WDU 0x0000E000U
+#define RTC_TSDR_WDU_0 0x00002000U
+#define RTC_TSDR_WDU_1 0x00004000U
+#define RTC_TSDR_WDU_2 0x00008000U
+#define RTC_TSDR_MT 0x00001000U
+#define RTC_TSDR_MU 0x00000F00U
+#define RTC_TSDR_MU_0 0x00000100U
+#define RTC_TSDR_MU_1 0x00000200U
+#define RTC_TSDR_MU_2 0x00000400U
+#define RTC_TSDR_MU_3 0x00000800U
+#define RTC_TSDR_DT 0x00000030U
+#define RTC_TSDR_DT_0 0x00000010U
+#define RTC_TSDR_DT_1 0x00000020U
+#define RTC_TSDR_DU 0x0000000FU
+#define RTC_TSDR_DU_0 0x00000001U
+#define RTC_TSDR_DU_1 0x00000002U
+#define RTC_TSDR_DU_2 0x00000004U
+#define RTC_TSDR_DU_3 0x00000008U
+
+/******************** Bits definition for RTC_TSSSR register ****************/
+#define RTC_TSSSR_SS 0x0000FFFFU
+
+/******************** Bits definition for RTC_CAL register *****************/
+#define RTC_CALR_CALP 0x00008000U
+#define RTC_CALR_CALW8 0x00004000U
+#define RTC_CALR_CALW16 0x00002000U
+#define RTC_CALR_CALM 0x000001FFU
+#define RTC_CALR_CALM_0 0x00000001U
+#define RTC_CALR_CALM_1 0x00000002U
+#define RTC_CALR_CALM_2 0x00000004U
+#define RTC_CALR_CALM_3 0x00000008U
+#define RTC_CALR_CALM_4 0x00000010U
+#define RTC_CALR_CALM_5 0x00000020U
+#define RTC_CALR_CALM_6 0x00000040U
+#define RTC_CALR_CALM_7 0x00000080U
+#define RTC_CALR_CALM_8 0x00000100U
+
+/******************** Bits definition for RTC_TAFCR register ****************/
+#define RTC_TAFCR_ALARMOUTTYPE 0x00040000U
+#define RTC_TAFCR_TSINSEL 0x00020000U
+#define RTC_TAFCR_TAMPINSEL 0x00010000U
+#define RTC_TAFCR_TAMPPUDIS 0x00008000U
+#define RTC_TAFCR_TAMPPRCH 0x00006000U
+#define RTC_TAFCR_TAMPPRCH_0 0x00002000U
+#define RTC_TAFCR_TAMPPRCH_1 0x00004000U
+#define RTC_TAFCR_TAMPFLT 0x00001800U
+#define RTC_TAFCR_TAMPFLT_0 0x00000800U
+#define RTC_TAFCR_TAMPFLT_1 0x00001000U
+#define RTC_TAFCR_TAMPFREQ 0x00000700U
+#define RTC_TAFCR_TAMPFREQ_0 0x00000100U
+#define RTC_TAFCR_TAMPFREQ_1 0x00000200U
+#define RTC_TAFCR_TAMPFREQ_2 0x00000400U
+#define RTC_TAFCR_TAMPTS 0x00000080U
+#define RTC_TAFCR_TAMP2TRG 0x00000010U
+#define RTC_TAFCR_TAMP2E 0x00000008U
+#define RTC_TAFCR_TAMPIE 0x00000004U
+#define RTC_TAFCR_TAMP1TRG 0x00000002U
+#define RTC_TAFCR_TAMP1E 0x00000001U
+
+/******************** Bits definition for RTC_ALRMASSR register *************/
+#define RTC_ALRMASSR_MASKSS 0x0F000000U
+#define RTC_ALRMASSR_MASKSS_0 0x01000000U
+#define RTC_ALRMASSR_MASKSS_1 0x02000000U
+#define RTC_ALRMASSR_MASKSS_2 0x04000000U
+#define RTC_ALRMASSR_MASKSS_3 0x08000000U
+#define RTC_ALRMASSR_SS 0x00007FFFU
+
+/******************** Bits definition for RTC_ALRMBSSR register *************/
+#define RTC_ALRMBSSR_MASKSS 0x0F000000U
+#define RTC_ALRMBSSR_MASKSS_0 0x01000000U
+#define RTC_ALRMBSSR_MASKSS_1 0x02000000U
+#define RTC_ALRMBSSR_MASKSS_2 0x04000000U
+#define RTC_ALRMBSSR_MASKSS_3 0x08000000U
+#define RTC_ALRMBSSR_SS 0x00007FFFU
+
+/******************** Bits definition for RTC_BKP0R register ****************/
+#define RTC_BKP0R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP1R register ****************/
+#define RTC_BKP1R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP2R register ****************/
+#define RTC_BKP2R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP3R register ****************/
+#define RTC_BKP3R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP4R register ****************/
+#define RTC_BKP4R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP5R register ****************/
+#define RTC_BKP5R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP6R register ****************/
+#define RTC_BKP6R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP7R register ****************/
+#define RTC_BKP7R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP8R register ****************/
+#define RTC_BKP8R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP9R register ****************/
+#define RTC_BKP9R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP10R register ***************/
+#define RTC_BKP10R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP11R register ***************/
+#define RTC_BKP11R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP12R register ***************/
+#define RTC_BKP12R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP13R register ***************/
+#define RTC_BKP13R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP14R register ***************/
+#define RTC_BKP14R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP15R register ***************/
+#define RTC_BKP15R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP16R register ***************/
+#define RTC_BKP16R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP17R register ***************/
+#define RTC_BKP17R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP18R register ***************/
+#define RTC_BKP18R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP19R register ***************/
+#define RTC_BKP19R 0xFFFFFFFFU
+
+/******************************************************************************/
+/* */
+/* Serial Audio Interface */
+/* */
+/******************************************************************************/
+/******************** Bit definition for SAI_GCR register *******************/
+#define SAI_GCR_SYNCIN 0x00000003U /*!<SYNCIN[1:0] bits (Synchronization Inputs) */
+#define SAI_GCR_SYNCIN_0 0x00000001U /*!<Bit 0 */
+#define SAI_GCR_SYNCIN_1 0x00000002U /*!<Bit 1 */
+
+#define SAI_GCR_SYNCOUT 0x00000030U /*!<SYNCOUT[1:0] bits (Synchronization Outputs) */
+#define SAI_GCR_SYNCOUT_0 0x00000010U /*!<Bit 0 */
+#define SAI_GCR_SYNCOUT_1 0x00000020U /*!<Bit 1 */
+
+/******************* Bit definition for SAI_xCR1 register *******************/
+#define SAI_xCR1_MODE 0x00000003U /*!<MODE[1:0] bits (Audio Block Mode) */
+#define SAI_xCR1_MODE_0 0x00000001U /*!<Bit 0 */
+#define SAI_xCR1_MODE_1 0x00000002U /*!<Bit 1 */
+
+#define SAI_xCR1_PRTCFG 0x0000000CU /*!<PRTCFG[1:0] bits (Protocol Configuration) */
+#define SAI_xCR1_PRTCFG_0 0x00000004U /*!<Bit 0 */
+#define SAI_xCR1_PRTCFG_1 0x00000008U /*!<Bit 1 */
+
+#define SAI_xCR1_DS 0x000000E0U /*!<DS[1:0] bits (Data Size) */
+#define SAI_xCR1_DS_0 0x00000020U /*!<Bit 0 */
+#define SAI_xCR1_DS_1 0x00000040U /*!<Bit 1 */
+#define SAI_xCR1_DS_2 0x00000080U /*!<Bit 2 */
+
+#define SAI_xCR1_LSBFIRST 0x00000100U /*!<LSB First Configuration */
+#define SAI_xCR1_CKSTR 0x00000200U /*!<ClocK STRobing edge */
+
+#define SAI_xCR1_SYNCEN 0x00000C00U /*!<SYNCEN[1:0](SYNChronization ENable) */
+#define SAI_xCR1_SYNCEN_0 0x00000400U /*!<Bit 0 */
+#define SAI_xCR1_SYNCEN_1 0x00000800U /*!<Bit 1 */
+
+#define SAI_xCR1_MONO 0x00001000U /*!<Mono mode */
+#define SAI_xCR1_OUTDRIV 0x00002000U /*!<Output Drive */
+#define SAI_xCR1_SAIEN 0x00010000U /*!<Audio Block enable */
+#define SAI_xCR1_DMAEN 0x00020000U /*!<DMA enable */
+#define SAI_xCR1_NODIV 0x00080000U /*!<No Divider Configuration */
+
+#define SAI_xCR1_MCKDIV 0x00F00000U /*!<MCKDIV[3:0] (Master ClocK Divider) */
+#define SAI_xCR1_MCKDIV_0 0x00100000U /*!<Bit 0 */
+#define SAI_xCR1_MCKDIV_1 0x00200000U /*!<Bit 1 */
+#define SAI_xCR1_MCKDIV_2 0x00400000U /*!<Bit 2 */
+#define SAI_xCR1_MCKDIV_3 0x00800000U /*!<Bit 3 */
+
+/******************* Bit definition for SAI_xCR2 register *******************/
+#define SAI_xCR2_FTH 0x00000007U /*!<FTH[2:0](Fifo THreshold) */
+#define SAI_xCR2_FTH_0 0x00000001U /*!<Bit 0 */
+#define SAI_xCR2_FTH_1 0x00000002U /*!<Bit 1 */
+#define SAI_xCR2_FTH_2 0x00000004U /*!<Bit 2 */
+
+#define SAI_xCR2_FFLUSH 0x00000008U /*!<Fifo FLUSH */
+#define SAI_xCR2_TRIS 0x00000010U /*!<TRIState Management on data line */
+#define SAI_xCR2_MUTE 0x00000020U /*!<Mute mode */
+#define SAI_xCR2_MUTEVAL 0x00000040U /*!<Muate value */
+
+#define SAI_xCR2_MUTECNT 0x00001F80U /*!<MUTECNT[5:0] (MUTE counter) */
+#define SAI_xCR2_MUTECNT_0 0x00000080U /*!<Bit 0 */
+#define SAI_xCR2_MUTECNT_1 0x00000100U /*!<Bit 1 */
+#define SAI_xCR2_MUTECNT_2 0x00000200U /*!<Bit 2 */
+#define SAI_xCR2_MUTECNT_3 0x00000400U /*!<Bit 3 */
+#define SAI_xCR2_MUTECNT_4 0x00000800U /*!<Bit 4 */
+#define SAI_xCR2_MUTECNT_5 0x00001000U /*!<Bit 5 */
+
+#define SAI_xCR2_CPL 0x00002000U /*!< Complement Bit */
+
+#define SAI_xCR2_COMP 0x0000C000U /*!<COMP[1:0] (Companding mode) */
+#define SAI_xCR2_COMP_0 0x00004000U /*!<Bit 0 */
+#define SAI_xCR2_COMP_1 0x00008000U /*!<Bit 1 */
+
+/****************** Bit definition for SAI_xFRCR register *******************/
+#define SAI_xFRCR_FRL 0x000000FFU /*!<FRL[1:0](Frame length) */
+#define SAI_xFRCR_FRL_0 0x00000001U /*!<Bit 0 */
+#define SAI_xFRCR_FRL_1 0x00000002U /*!<Bit 1 */
+#define SAI_xFRCR_FRL_2 0x00000004U /*!<Bit 2 */
+#define SAI_xFRCR_FRL_3 0x00000008U /*!<Bit 3 */
+#define SAI_xFRCR_FRL_4 0x00000010U /*!<Bit 4 */
+#define SAI_xFRCR_FRL_5 0x00000020U /*!<Bit 5 */
+#define SAI_xFRCR_FRL_6 0x00000040U /*!<Bit 6 */
+#define SAI_xFRCR_FRL_7 0x00000080U /*!<Bit 7 */
+
+#define SAI_xFRCR_FSALL 0x00007F00U /*!<FRL[1:0] (Frame synchronization active level length) */
+#define SAI_xFRCR_FSALL_0 0x00000100U /*!<Bit 0 */
+#define SAI_xFRCR_FSALL_1 0x00000200U /*!<Bit 1 */
+#define SAI_xFRCR_FSALL_2 0x00000400U /*!<Bit 2 */
+#define SAI_xFRCR_FSALL_3 0x00000800U /*!<Bit 3 */
+#define SAI_xFRCR_FSALL_4 0x00001000U /*!<Bit 4 */
+#define SAI_xFRCR_FSALL_5 0x00002000U /*!<Bit 5 */
+#define SAI_xFRCR_FSALL_6 0x00004000U /*!<Bit 6 */
+
+#define SAI_xFRCR_FSDEF 0x00010000U /*!< Frame Synchronization Definition */
+#define SAI_xFRCR_FSPOL 0x00020000U /*!<Frame Synchronization POLarity */
+#define SAI_xFRCR_FSOFF 0x00040000U /*!<Frame Synchronization OFFset */
+/* Legacy defines */
+#define SAI_xFRCR_FSPO SAI_xFRCR_FSPOL
+
+/****************** Bit definition for SAI_xSLOTR register *******************/
+#define SAI_xSLOTR_FBOFF 0x0000001FU /*!<FRL[4:0](First Bit Offset) */
+#define SAI_xSLOTR_FBOFF_0 0x00000001U /*!<Bit 0 */
+#define SAI_xSLOTR_FBOFF_1 0x00000002U /*!<Bit 1 */
+#define SAI_xSLOTR_FBOFF_2 0x00000004U /*!<Bit 2 */
+#define SAI_xSLOTR_FBOFF_3 0x00000008U /*!<Bit 3 */
+#define SAI_xSLOTR_FBOFF_4 0x00000010U /*!<Bit 4 */
+
+#define SAI_xSLOTR_SLOTSZ 0x000000C0U /*!<SLOTSZ[1:0] (Slot size) */
+#define SAI_xSLOTR_SLOTSZ_0 0x00000040U /*!<Bit 0 */
+#define SAI_xSLOTR_SLOTSZ_1 0x00000080U /*!<Bit 1 */
+
+#define SAI_xSLOTR_NBSLOT 0x00000F00U /*!<NBSLOT[3:0] (Number of Slot in audio Frame) */
+#define SAI_xSLOTR_NBSLOT_0 0x00000100U /*!<Bit 0 */
+#define SAI_xSLOTR_NBSLOT_1 0x00000200U /*!<Bit 1 */
+#define SAI_xSLOTR_NBSLOT_2 0x00000400U /*!<Bit 2 */
+#define SAI_xSLOTR_NBSLOT_3 0x00000800U /*!<Bit 3 */
+
+#define SAI_xSLOTR_SLOTEN 0xFFFF0000U /*!<SLOTEN[15:0] (Slot Enable) */
+
+/******************* Bit definition for SAI_xIMR register *******************/
+#define SAI_xIMR_OVRUDRIE 0x00000001U /*!<Overrun underrun interrupt enable */
+#define SAI_xIMR_MUTEDETIE 0x00000002U /*!<Mute detection interrupt enable */
+#define SAI_xIMR_WCKCFGIE 0x00000004U /*!<Wrong Clock Configuration interrupt enable */
+#define SAI_xIMR_FREQIE 0x00000008U /*!<FIFO request interrupt enable */
+#define SAI_xIMR_CNRDYIE 0x00000010U /*!<Codec not ready interrupt enable */
+#define SAI_xIMR_AFSDETIE 0x00000020U /*!<Anticipated frame synchronization detection interrupt enable */
+#define SAI_xIMR_LFSDETIE 0x00000040U /*!<Late frame synchronization detection interrupt enable */
+
+/******************** Bit definition for SAI_xSR register *******************/
+#define SAI_xSR_OVRUDR 0x00000001U /*!<Overrun underrun */
+#define SAI_xSR_MUTEDET 0x00000002U /*!<Mute detection */
+#define SAI_xSR_WCKCFG 0x00000004U /*!<Wrong Clock Configuration */
+#define SAI_xSR_FREQ 0x00000008U /*!<FIFO request */
+#define SAI_xSR_CNRDY 0x00000010U /*!<Codec not ready */
+#define SAI_xSR_AFSDET 0x00000020U /*!<Anticipated frame synchronization detection */
+#define SAI_xSR_LFSDET 0x00000040U /*!<Late frame synchronization detection */
+
+#define SAI_xSR_FLVL 0x00070000U /*!<FLVL[2:0] (FIFO Level Threshold) */
+#define SAI_xSR_FLVL_0 0x00010000U /*!<Bit 0 */
+#define SAI_xSR_FLVL_1 0x00020000U /*!<Bit 1 */
+#define SAI_xSR_FLVL_2 0x00040000U /*!<Bit 2 */
+
+/****************** Bit definition for SAI_xCLRFR register ******************/
+#define SAI_xCLRFR_COVRUDR 0x00000001U /*!<Clear Overrun underrun */
+#define SAI_xCLRFR_CMUTEDET 0x00000002U /*!<Clear Mute detection */
+#define SAI_xCLRFR_CWCKCFG 0x00000004U /*!<Clear Wrong Clock Configuration */
+#define SAI_xCLRFR_CFREQ 0x00000008U /*!<Clear FIFO request */
+#define SAI_xCLRFR_CCNRDY 0x00000010U /*!<Clear Codec not ready */
+#define SAI_xCLRFR_CAFSDET 0x00000020U /*!<Clear Anticipated frame synchronization detection */
+#define SAI_xCLRFR_CLFSDET 0x00000040U /*!<Clear Late frame synchronization detection */
+
+/****************** Bit definition for SAI_xDR register ******************/
+#define SAI_xDR_DATA 0xFFFFFFFFU
+
+
+/******************************************************************************/
+/* */
+/* SD host Interface */
+/* */
+/******************************************************************************/
+/****************** Bit definition for SDIO_POWER register ******************/
+#define SDIO_POWER_PWRCTRL 0x03U /*!<PWRCTRL[1:0] bits (Power supply control bits) */
+#define SDIO_POWER_PWRCTRL_0 0x01U /*!<Bit 0 */
+#define SDIO_POWER_PWRCTRL_1 0x02U /*!<Bit 1 */
+
+/****************** Bit definition for SDIO_CLKCR register ******************/
+#define SDIO_CLKCR_CLKDIV 0x00FFU /*!<Clock divide factor */
+#define SDIO_CLKCR_CLKEN 0x0100U /*!<Clock enable bit */
+#define SDIO_CLKCR_PWRSAV 0x0200U /*!<Power saving configuration bit */
+#define SDIO_CLKCR_BYPASS 0x0400U /*!<Clock divider bypass enable bit */
+
+#define SDIO_CLKCR_WIDBUS 0x1800U /*!<WIDBUS[1:0] bits (Wide bus mode enable bit) */
+#define SDIO_CLKCR_WIDBUS_0 0x0800U /*!<Bit 0 */
+#define SDIO_CLKCR_WIDBUS_1 0x1000U /*!<Bit 1 */
+
+#define SDIO_CLKCR_NEGEDGE 0x2000U /*!<SDIO_CK dephasing selection bit */
+#define SDIO_CLKCR_HWFC_EN 0x4000U /*!<HW Flow Control enable */
+
+/******************* Bit definition for SDIO_ARG register *******************/
+#define SDIO_ARG_CMDARG 0xFFFFFFFFU /*!<Command argument */
+
+/******************* Bit definition for SDIO_CMD register *******************/
+#define SDIO_CMD_CMDINDEX 0x003FU /*!<Command Index */
+
+#define SDIO_CMD_WAITRESP 0x00C0U /*!<WAITRESP[1:0] bits (Wait for response bits) */
+#define SDIO_CMD_WAITRESP_0 0x0040U /*!< Bit 0 */
+#define SDIO_CMD_WAITRESP_1 0x0080U /*!< Bit 1 */
+
+#define SDIO_CMD_WAITINT 0x0100U /*!<CPSM Waits for Interrupt Request */
+#define SDIO_CMD_WAITPEND 0x0200U /*!<CPSM Waits for ends of data transfer (CmdPend internal signal) */
+#define SDIO_CMD_CPSMEN 0x0400U /*!<Command path state machine (CPSM) Enable bit */
+#define SDIO_CMD_SDIOSUSPEND 0x0800U /*!<SD I/O suspend command */
+#define SDIO_CMD_ENCMDCOMPL 0x1000U /*!<Enable CMD completion */
+#define SDIO_CMD_NIEN 0x2000U /*!<Not Interrupt Enable */
+#define SDIO_CMD_CEATACMD 0x4000U /*!<CE-ATA command */
+
+/***************** Bit definition for SDIO_RESPCMD register *****************/
+#define SDIO_RESPCMD_RESPCMD 0x3FU /*!<Response command index */
+
+/****************** Bit definition for SDIO_RESP0 register ******************/
+#define SDIO_RESP0_CARDSTATUS0 0xFFFFFFFFU /*!<Card Status */
+
+/****************** Bit definition for SDIO_RESP1 register ******************/
+#define SDIO_RESP1_CARDSTATUS1 0xFFFFFFFFU /*!<Card Status */
+
+/****************** Bit definition for SDIO_RESP2 register ******************/
+#define SDIO_RESP2_CARDSTATUS2 0xFFFFFFFFU /*!<Card Status */
+
+/****************** Bit definition for SDIO_RESP3 register ******************/
+#define SDIO_RESP3_CARDSTATUS3 0xFFFFFFFFU /*!<Card Status */
+
+/****************** Bit definition for SDIO_RESP4 register ******************/
+#define SDIO_RESP4_CARDSTATUS4 0xFFFFFFFFU /*!<Card Status */
+
+/****************** Bit definition for SDIO_DTIMER register *****************/
+#define SDIO_DTIMER_DATATIME 0xFFFFFFFFU /*!<Data timeout period. */
+
+/****************** Bit definition for SDIO_DLEN register *******************/
+#define SDIO_DLEN_DATALENGTH 0x01FFFFFFU /*!<Data length value */
+
+/****************** Bit definition for SDIO_DCTRL register ******************/
+#define SDIO_DCTRL_DTEN 0x0001U /*!<Data transfer enabled bit */
+#define SDIO_DCTRL_DTDIR 0x0002U /*!<Data transfer direction selection */
+#define SDIO_DCTRL_DTMODE 0x0004U /*!<Data transfer mode selection */
+#define SDIO_DCTRL_DMAEN 0x0008U /*!<DMA enabled bit */
+
+#define SDIO_DCTRL_DBLOCKSIZE 0x00F0U /*!<DBLOCKSIZE[3:0] bits (Data block size) */
+#define SDIO_DCTRL_DBLOCKSIZE_0 0x0010U /*!<Bit 0 */
+#define SDIO_DCTRL_DBLOCKSIZE_1 0x0020U /*!<Bit 1 */
+#define SDIO_DCTRL_DBLOCKSIZE_2 0x0040U /*!<Bit 2 */
+#define SDIO_DCTRL_DBLOCKSIZE_3 0x0080U /*!<Bit 3 */
+
+#define SDIO_DCTRL_RWSTART 0x0100U /*!<Read wait start */
+#define SDIO_DCTRL_RWSTOP 0x0200U /*!<Read wait stop */
+#define SDIO_DCTRL_RWMOD 0x0400U /*!<Read wait mode */
+#define SDIO_DCTRL_SDIOEN 0x0800U /*!<SD I/O enable functions */
+
+/****************** Bit definition for SDIO_DCOUNT register *****************/
+#define SDIO_DCOUNT_DATACOUNT 0x01FFFFFFU /*!<Data count value */
+
+/****************** Bit definition for SDIO_STA register ********************/
+#define SDIO_STA_CCRCFAIL 0x00000001U /*!<Command response received (CRC check failed) */
+#define SDIO_STA_DCRCFAIL 0x00000002U /*!<Data block sent/received (CRC check failed) */
+#define SDIO_STA_CTIMEOUT 0x00000004U /*!<Command response timeout */
+#define SDIO_STA_DTIMEOUT 0x00000008U /*!<Data timeout */
+#define SDIO_STA_TXUNDERR 0x00000010U /*!<Transmit FIFO underrun error */
+#define SDIO_STA_RXOVERR 0x00000020U /*!<Received FIFO overrun error */
+#define SDIO_STA_CMDREND 0x00000040U /*!<Command response received (CRC check passed) */
+#define SDIO_STA_CMDSENT 0x00000080U /*!<Command sent (no response required) */
+#define SDIO_STA_DATAEND 0x00000100U /*!<Data end (data counter, SDIDCOUNT, is zero) */
+#define SDIO_STA_STBITERR 0x00000200U /*!<Start bit not detected on all data signals in wide bus mode */
+#define SDIO_STA_DBCKEND 0x00000400U /*!<Data block sent/received (CRC check passed) */
+#define SDIO_STA_CMDACT 0x00000800U /*!<Command transfer in progress */
+#define SDIO_STA_TXACT 0x00001000U /*!<Data transmit in progress */
+#define SDIO_STA_RXACT 0x00002000U /*!<Data receive in progress */
+#define SDIO_STA_TXFIFOHE 0x00004000U /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
+#define SDIO_STA_RXFIFOHF 0x00008000U /*!<Receive FIFO Half Full: there are at least 8 words in the FIFO */
+#define SDIO_STA_TXFIFOF 0x00010000U /*!<Transmit FIFO full */
+#define SDIO_STA_RXFIFOF 0x00020000U /*!<Receive FIFO full */
+#define SDIO_STA_TXFIFOE 0x00040000U /*!<Transmit FIFO empty */
+#define SDIO_STA_RXFIFOE 0x00080000U /*!<Receive FIFO empty */
+#define SDIO_STA_TXDAVL 0x00100000U /*!<Data available in transmit FIFO */
+#define SDIO_STA_RXDAVL 0x00200000U /*!<Data available in receive FIFO */
+#define SDIO_STA_SDIOIT 0x00400000U /*!<SDIO interrupt received */
+#define SDIO_STA_CEATAEND 0x00800000U /*!<CE-ATA command completion signal received for CMD61 */
+
+/******************* Bit definition for SDIO_ICR register *******************/
+#define SDIO_ICR_CCRCFAILC 0x00000001U /*!<CCRCFAIL flag clear bit */
+#define SDIO_ICR_DCRCFAILC 0x00000002U /*!<DCRCFAIL flag clear bit */
+#define SDIO_ICR_CTIMEOUTC 0x00000004U /*!<CTIMEOUT flag clear bit */
+#define SDIO_ICR_DTIMEOUTC 0x00000008U /*!<DTIMEOUT flag clear bit */
+#define SDIO_ICR_TXUNDERRC 0x00000010U /*!<TXUNDERR flag clear bit */
+#define SDIO_ICR_RXOVERRC 0x00000020U /*!<RXOVERR flag clear bit */
+#define SDIO_ICR_CMDRENDC 0x00000040U /*!<CMDREND flag clear bit */
+#define SDIO_ICR_CMDSENTC 0x00000080U /*!<CMDSENT flag clear bit */
+#define SDIO_ICR_DATAENDC 0x00000100U /*!<DATAEND flag clear bit */
+#define SDIO_ICR_STBITERRC 0x00000200U /*!<STBITERR flag clear bit */
+#define SDIO_ICR_DBCKENDC 0x00000400U /*!<DBCKEND flag clear bit */
+#define SDIO_ICR_SDIOITC 0x00400000U /*!<SDIOIT flag clear bit */
+#define SDIO_ICR_CEATAENDC 0x00800000U /*!<CEATAEND flag clear bit */
+
+/****************** Bit definition for SDIO_MASK register *******************/
+#define SDIO_MASK_CCRCFAILIE 0x00000001U /*!<Command CRC Fail Interrupt Enable */
+#define SDIO_MASK_DCRCFAILIE 0x00000002U /*!<Data CRC Fail Interrupt Enable */
+#define SDIO_MASK_CTIMEOUTIE 0x00000004U /*!<Command TimeOut Interrupt Enable */
+#define SDIO_MASK_DTIMEOUTIE 0x00000008U /*!<Data TimeOut Interrupt Enable */
+#define SDIO_MASK_TXUNDERRIE 0x00000010U /*!<Tx FIFO UnderRun Error Interrupt Enable */
+#define SDIO_MASK_RXOVERRIE 0x00000020U /*!<Rx FIFO OverRun Error Interrupt Enable */
+#define SDIO_MASK_CMDRENDIE 0x00000040U /*!<Command Response Received Interrupt Enable */
+#define SDIO_MASK_CMDSENTIE 0x00000080U /*!<Command Sent Interrupt Enable */
+#define SDIO_MASK_DATAENDIE 0x00000100U /*!<Data End Interrupt Enable */
+#define SDIO_MASK_STBITERRIE 0x00000200U /*!<Start Bit Error Interrupt Enable */
+#define SDIO_MASK_DBCKENDIE 0x00000400U /*!<Data Block End Interrupt Enable */
+#define SDIO_MASK_CMDACTIE 0x00000800U /*!<CCommand Acting Interrupt Enable */
+#define SDIO_MASK_TXACTIE 0x00001000U /*!<Data Transmit Acting Interrupt Enable */
+#define SDIO_MASK_RXACTIE 0x00002000U /*!<Data receive acting interrupt enabled */
+#define SDIO_MASK_TXFIFOHEIE 0x00004000U /*!<Tx FIFO Half Empty interrupt Enable */
+#define SDIO_MASK_RXFIFOHFIE 0x00008000U /*!<Rx FIFO Half Full interrupt Enable */
+#define SDIO_MASK_TXFIFOFIE 0x00010000U /*!<Tx FIFO Full interrupt Enable */
+#define SDIO_MASK_RXFIFOFIE 0x00020000U /*!<Rx FIFO Full interrupt Enable */
+#define SDIO_MASK_TXFIFOEIE 0x00040000U /*!<Tx FIFO Empty interrupt Enable */
+#define SDIO_MASK_RXFIFOEIE 0x00080000U /*!<Rx FIFO Empty interrupt Enable */
+#define SDIO_MASK_TXDAVLIE 0x00100000U /*!<Data available in Tx FIFO interrupt Enable */
+#define SDIO_MASK_RXDAVLIE 0x00200000U /*!<Data available in Rx FIFO interrupt Enable */
+#define SDIO_MASK_SDIOITIE 0x00400000U /*!<SDIO Mode Interrupt Received interrupt Enable */
+#define SDIO_MASK_CEATAENDIE 0x00800000U /*!<CE-ATA command completion signal received Interrupt Enable */
+
+/***************** Bit definition for SDIO_FIFOCNT register *****************/
+#define SDIO_FIFOCNT_FIFOCOUNT 0x00FFFFFFU /*!<Remaining number of words to be written to or read from the FIFO */
+
+/****************** Bit definition for SDIO_FIFO register *******************/
+#define SDIO_FIFO_FIFODATA 0xFFFFFFFFU /*!<Receive and transmit FIFO data */
+
+/******************************************************************************/
+/* */
+/* Serial Peripheral Interface */
+/* */
+/******************************************************************************/
+/******************* Bit definition for SPI_CR1 register ********************/
+#define SPI_CR1_CPHA 0x00000001U /*!<Clock Phase */
+#define SPI_CR1_CPOL 0x00000002U /*!<Clock Polarity */
+#define SPI_CR1_MSTR 0x00000004U /*!<Master Selection */
+
+#define SPI_CR1_BR 0x00000038U /*!<BR[2:0] bits (Baud Rate Control) */
+#define SPI_CR1_BR_0 0x00000008U /*!<Bit 0 */
+#define SPI_CR1_BR_1 0x00000010U /*!<Bit 1 */
+#define SPI_CR1_BR_2 0x00000020U /*!<Bit 2 */
+
+#define SPI_CR1_SPE 0x00000040U /*!<SPI Enable */
+#define SPI_CR1_LSBFIRST 0x00000080U /*!<Frame Format */
+#define SPI_CR1_SSI 0x00000100U /*!<Internal slave select */
+#define SPI_CR1_SSM 0x00000200U /*!<Software slave management */
+#define SPI_CR1_RXONLY 0x00000400U /*!<Receive only */
+#define SPI_CR1_DFF 0x00000800U /*!<Data Frame Format */
+#define SPI_CR1_CRCNEXT 0x00001000U /*!<Transmit CRC next */
+#define SPI_CR1_CRCEN 0x00002000U /*!<Hardware CRC calculation enable */
+#define SPI_CR1_BIDIOE 0x00004000U /*!<Output enable in bidirectional mode */
+#define SPI_CR1_BIDIMODE 0x00008000U /*!<Bidirectional data mode enable */
+
+/******************* Bit definition for SPI_CR2 register ********************/
+#define SPI_CR2_RXDMAEN 0x00000001U /*!<Rx Buffer DMA Enable */
+#define SPI_CR2_TXDMAEN 0x00000002U /*!<Tx Buffer DMA Enable */
+#define SPI_CR2_SSOE 0x00000004U /*!<SS Output Enable */
+#define SPI_CR2_FRF 0x00000010U /*!<Frame Format */
+#define SPI_CR2_ERRIE 0x00000020U /*!<Error Interrupt Enable */
+#define SPI_CR2_RXNEIE 0x00000040U /*!<RX buffer Not Empty Interrupt Enable */
+#define SPI_CR2_TXEIE 0x00000080U /*!<Tx buffer Empty Interrupt Enable */
+
+/******************** Bit definition for SPI_SR register ********************/
+#define SPI_SR_RXNE 0x00000001U /*!<Receive buffer Not Empty */
+#define SPI_SR_TXE 0x00000002U /*!<Transmit buffer Empty */
+#define SPI_SR_CHSIDE 0x00000004U /*!<Channel side */
+#define SPI_SR_UDR 0x00000008U /*!<Underrun flag */
+#define SPI_SR_CRCERR 0x00000010U /*!<CRC Error flag */
+#define SPI_SR_MODF 0x00000020U /*!<Mode fault */
+#define SPI_SR_OVR 0x00000040U /*!<Overrun flag */
+#define SPI_SR_BSY 0x00000080U /*!<Busy flag */
+#define SPI_SR_FRE 0x00000100U /*!<Frame format error flag */
+
+/******************** Bit definition for SPI_DR register ********************/
+#define SPI_DR_DR 0x0000FFFFU /*!<Data Register */
+
+/******************* Bit definition for SPI_CRCPR register ******************/
+#define SPI_CRCPR_CRCPOLY 0x0000FFFFU /*!<CRC polynomial register */
+
+/****************** Bit definition for SPI_RXCRCR register ******************/
+#define SPI_RXCRCR_RXCRC 0x0000FFFFU /*!<Rx CRC Register */
+
+/****************** Bit definition for SPI_TXCRCR register ******************/
+#define SPI_TXCRCR_TXCRC 0x0000FFFFU /*!<Tx CRC Register */
+
+/****************** Bit definition for SPI_I2SCFGR register *****************/
+#define SPI_I2SCFGR_CHLEN 0x00000001U /*!<Channel length (number of bits per audio channel) */
+
+#define SPI_I2SCFGR_DATLEN 0x00000006U /*!<DATLEN[1:0] bits (Data length to be transferred) */
+#define SPI_I2SCFGR_DATLEN_0 0x00000002U /*!<Bit 0 */
+#define SPI_I2SCFGR_DATLEN_1 0x00000004U /*!<Bit 1 */
+
+#define SPI_I2SCFGR_CKPOL 0x00000008U /*!<steady state clock polarity */
+
+#define SPI_I2SCFGR_I2SSTD 0x00000030U /*!<I2SSTD[1:0] bits (I2S standard selection) */
+#define SPI_I2SCFGR_I2SSTD_0 0x00000010U /*!<Bit 0 */
+#define SPI_I2SCFGR_I2SSTD_1 0x00000020U /*!<Bit 1 */
+
+#define SPI_I2SCFGR_PCMSYNC 0x00000080U /*!<PCM frame synchronization */
+
+#define SPI_I2SCFGR_I2SCFG 0x00000300U /*!<I2SCFG[1:0] bits (I2S configuration mode) */
+#define SPI_I2SCFGR_I2SCFG_0 0x00000100U /*!<Bit 0 */
+#define SPI_I2SCFGR_I2SCFG_1 0x00000200U /*!<Bit 1 */
+
+#define SPI_I2SCFGR_I2SE 0x00000400U /*!<I2S Enable */
+#define SPI_I2SCFGR_I2SMOD 0x00000800U /*!<I2S mode selection */
+
+/****************** Bit definition for SPI_I2SPR register *******************/
+#define SPI_I2SPR_I2SDIV 0x000000FFU /*!<I2S Linear prescaler */
+#define SPI_I2SPR_ODD 0x00000100U /*!<Odd factor for the prescaler */
+#define SPI_I2SPR_MCKOE 0x00000200U /*!<Master Clock Output Enable */
+
+/******************************************************************************/
+/* */
+/* SYSCFG */
+/* */
+/******************************************************************************/
+/****************** Bit definition for SYSCFG_MEMRMP register ***************/
+#define SYSCFG_MEMRMP_MEM_MODE 0x00000007U /*!< SYSCFG_Memory Remap Config */
+#define SYSCFG_MEMRMP_MEM_MODE_0 0x00000001U
+#define SYSCFG_MEMRMP_MEM_MODE_1 0x00000002U
+#define SYSCFG_MEMRMP_MEM_MODE_2 0x00000004U
+
+#define SYSCFG_MEMRMP_UFB_MODE 0x00000100U /*!< User Flash Bank mode */
+#define SYSCFG_SWP_FMC 0x00000C00U /*!< FMC memory mapping swap */
+
+/****************** Bit definition for SYSCFG_PMC register ******************/
+#define SYSCFG_PMC_ADCxDC2 0x00070000U /*!< Refer to AN4073 on how to use this bit */
+#define SYSCFG_PMC_ADC1DC2 0x00010000U /*!< Refer to AN4073 on how to use this bit */
+#define SYSCFG_PMC_ADC2DC2 0x00020000U /*!< Refer to AN4073 on how to use this bit */
+#define SYSCFG_PMC_ADC3DC2 0x00040000U /*!< Refer to AN4073 on how to use this bit */
+
+#define SYSCFG_PMC_MII_RMII_SEL 0x00800000U /*!<Ethernet PHY interface selection */
+/* Old MII_RMII_SEL bit definition, maintained for legacy purpose */
+#define SYSCFG_PMC_MII_RMII SYSCFG_PMC_MII_RMII_SEL
+
+/***************** Bit definition for SYSCFG_EXTICR1 register ***************/
+#define SYSCFG_EXTICR1_EXTI0 0x000FU /*!<EXTI 0 configuration */
+#define SYSCFG_EXTICR1_EXTI1 0x00F0U /*!<EXTI 1 configuration */
+#define SYSCFG_EXTICR1_EXTI2 0x0F00U /*!<EXTI 2 configuration */
+#define SYSCFG_EXTICR1_EXTI3 0xF000U /*!<EXTI 3 configuration */
+/**
+ * @brief EXTI0 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI0_PA 0x0000U /*!<PA[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PB 0x0001U /*!<PB[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PC 0x0002U /*!<PC[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PD 0x0003U /*!<PD[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PE 0x0004U /*!<PE[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PF 0x0005U /*!<PF[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PG 0x0006U /*!<PG[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PH 0x0007U /*!<PH[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PI 0x0008U /*!<PI[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PJ 0x0009U /*!<PJ[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PK 0x000AU /*!<PK[0] pin */
+
+/**
+ * @brief EXTI1 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI1_PA 0x0000U /*!<PA[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PB 0x0010U /*!<PB[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PC 0x0020U /*!<PC[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PD 0x0030U /*!<PD[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PE 0x0040U /*!<PE[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PF 0x0050U /*!<PF[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PG 0x0060U /*!<PG[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PH 0x0070U /*!<PH[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PI 0x0080U /*!<PI[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PJ 0x0090U /*!<PJ[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PK 0x00A0U /*!<PK[1] pin */
+
+
+/**
+ * @brief EXTI2 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI2_PA 0x0000U /*!<PA[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PB 0x0100U /*!<PB[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PC 0x0200U /*!<PC[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PD 0x0300U /*!<PD[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PE 0x0400U /*!<PE[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PF 0x0500U /*!<PF[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PG 0x0600U /*!<PG[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PH 0x0700U /*!<PH[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PI 0x0800U /*!<PI[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PJ 0x0900U /*!<PJ[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PK 0x0A00U /*!<PK[2] pin */
+
+
+/**
+ * @brief EXTI3 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI3_PA 0x0000U /*!<PA[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PB 0x1000U /*!<PB[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PC 0x2000U /*!<PC[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PD 0x3000U /*!<PD[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PE 0x4000U /*!<PE[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PF 0x5000U /*!<PF[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PG 0x6000U /*!<PG[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PH 0x7000U /*!<PH[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PI 0x8000U /*!<PI[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PJ 0x9000U /*!<PJ[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PK 0xA000U /*!<PK[3] pin */
+
+
+/***************** Bit definition for SYSCFG_EXTICR2 register ***************/
+#define SYSCFG_EXTICR2_EXTI4 0x000FU /*!<EXTI 4 configuration */
+#define SYSCFG_EXTICR2_EXTI5 0x00F0U /*!<EXTI 5 configuration */
+#define SYSCFG_EXTICR2_EXTI6 0x0F00U /*!<EXTI 6 configuration */
+#define SYSCFG_EXTICR2_EXTI7 0xF000U /*!<EXTI 7 configuration */
+/**
+ * @brief EXTI4 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI4_PA 0x0000U /*!<PA[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PB 0x0001U /*!<PB[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PC 0x0002U /*!<PC[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PD 0x0003U /*!<PD[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PE 0x0004U /*!<PE[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PF 0x0005U /*!<PF[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PG 0x0006U /*!<PG[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PH 0x0007U /*!<PH[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PI 0x0008U /*!<PI[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PJ 0x0009U /*!<PJ[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PK 0x000AU /*!<PK[4] pin */
+
+/**
+ * @brief EXTI5 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI5_PA 0x0000U /*!<PA[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PB 0x0010U /*!<PB[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PC 0x0020U /*!<PC[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PD 0x0030U /*!<PD[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PE 0x0040U /*!<PE[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PF 0x0050U /*!<PF[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PG 0x0060U /*!<PG[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PH 0x0070U /*!<PH[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PI 0x0080U /*!<PI[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PJ 0x0090U /*!<PJ[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PK 0x00A0U /*!<PK[5] pin */
+
+/**
+ * @brief EXTI6 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI6_PA 0x0000U /*!<PA[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PB 0x0100U /*!<PB[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PC 0x0200U /*!<PC[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PD 0x0300U /*!<PD[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PE 0x0400U /*!<PE[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PF 0x0500U /*!<PF[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PG 0x0600U /*!<PG[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PH 0x0700U /*!<PH[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PI 0x0800U /*!<PI[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PJ 0x0900U /*!<PJ[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PK 0x0A00U /*!<PK[6] pin */
+
+
+/**
+ * @brief EXTI7 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI7_PA 0x0000U /*!<PA[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PB 0x1000U /*!<PB[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PC 0x2000U /*!<PC[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PD 0x3000U /*!<PD[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PE 0x4000U /*!<PE[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PF 0x5000U /*!<PF[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PG 0x6000U /*!<PG[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PH 0x7000U /*!<PH[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PI 0x8000U /*!<PI[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PJ 0x9000U /*!<PJ[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PK 0xA000U /*!<PK[7] pin */
+
+/***************** Bit definition for SYSCFG_EXTICR3 register ***************/
+#define SYSCFG_EXTICR3_EXTI8 0x000FU /*!<EXTI 8 configuration */
+#define SYSCFG_EXTICR3_EXTI9 0x00F0U /*!<EXTI 9 configuration */
+#define SYSCFG_EXTICR3_EXTI10 0x0F00U /*!<EXTI 10 configuration */
+#define SYSCFG_EXTICR3_EXTI11 0xF000U /*!<EXTI 11 configuration */
+
+/**
+ * @brief EXTI8 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI8_PA 0x0000U /*!<PA[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PB 0x0001U /*!<PB[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PC 0x0002U /*!<PC[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PD 0x0003U /*!<PD[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PE 0x0004U /*!<PE[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PF 0x0005U /*!<PF[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PG 0x0006U /*!<PG[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PH 0x0007U /*!<PH[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PI 0x0008U /*!<PI[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PJ 0x0009U /*!<PJ[8] pin */
+
+/**
+ * @brief EXTI9 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI9_PA 0x0000U /*!<PA[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PB 0x0010U /*!<PB[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PC 0x0020U /*!<PC[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PD 0x0030U /*!<PD[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PE 0x0040U /*!<PE[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PF 0x0050U /*!<PF[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PG 0x0060U /*!<PG[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PH 0x0070U /*!<PH[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PI 0x0080U /*!<PI[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PJ 0x0090U /*!<PJ[9] pin */
+
+
+/**
+ * @brief EXTI10 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI10_PA 0x0000U /*!<PA[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PB 0x0100U /*!<PB[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PC 0x0200U /*!<PC[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PD 0x0300U /*!<PD[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PE 0x0400U /*!<PE[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PF 0x0500U /*!<PF[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PG 0x0600U /*!<PG[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PH 0x0700U /*!<PH[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PI 0x0800U /*!<PI[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PJ 0x0900U /*!<PJ[10] pin */
+
+
+/**
+ * @brief EXTI11 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI11_PA 0x0000U /*!<PA[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PB 0x1000U /*!<PB[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PC 0x2000U /*!<PC[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PD 0x3000U /*!<PD[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PE 0x4000U /*!<PE[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PF 0x5000U /*!<PF[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PG 0x6000U /*!<PG[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PH 0x7000U /*!<PH[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PI 0x8000U /*!<PI[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PJ 0x9000U /*!<PJ[11] pin */
+
+
+/***************** Bit definition for SYSCFG_EXTICR4 register ***************/
+#define SYSCFG_EXTICR4_EXTI12 0x000FU /*!<EXTI 12 configuration */
+#define SYSCFG_EXTICR4_EXTI13 0x00F0U /*!<EXTI 13 configuration */
+#define SYSCFG_EXTICR4_EXTI14 0x0F00U /*!<EXTI 14 configuration */
+#define SYSCFG_EXTICR4_EXTI15 0xF000U /*!<EXTI 15 configuration */
+/**
+ * @brief EXTI12 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI12_PA 0x0000U /*!<PA[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PB 0x0001U /*!<PB[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PC 0x0002U /*!<PC[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PD 0x0003U /*!<PD[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PE 0x0004U /*!<PE[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PF 0x0005U /*!<PF[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PG 0x0006U /*!<PG[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PH 0x0007U /*!<PH[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PI 0x0008U /*!<PI[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PJ 0x0009U /*!<PJ[12] pin */
+
+
+/**
+ * @brief EXTI13 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI13_PA 0x0000U /*!<PA[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PB 0x0010U /*!<PB[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PC 0x0020U /*!<PC[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PD 0x0030U /*!<PD[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PE 0x0040U /*!<PE[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PF 0x0050U /*!<PF[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PG 0x0060U /*!<PG[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PH 0x0070U /*!<PH[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PI 0x0008U /*!<PI[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PJ 0x0009U /*!<PJ[13] pin */
+
+
+/**
+ * @brief EXTI14 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI14_PA 0x0000U /*!<PA[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PB 0x0100U /*!<PB[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PC 0x0200U /*!<PC[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PD 0x0300U /*!<PD[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PE 0x0400U /*!<PE[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PF 0x0500U /*!<PF[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PG 0x0600U /*!<PG[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PH 0x0700U /*!<PH[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PI 0x0800U /*!<PI[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PJ 0x0900U /*!<PJ[14] pin */
+
+
+/**
+ * @brief EXTI15 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI15_PA 0x0000U /*!<PA[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PB 0x1000U /*!<PB[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PC 0x2000U /*!<PC[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PD 0x3000U /*!<PD[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PE 0x4000U /*!<PE[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PF 0x5000U /*!<PF[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PG 0x6000U /*!<PG[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PH 0x7000U /*!<PH[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PI 0x8000U /*!<PI[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PJ 0x9000U /*!<PJ[15] pin */
+
+/****************** Bit definition for SYSCFG_CMPCR register ****************/
+#define SYSCFG_CMPCR_CMP_PD 0x00000001U /*!<Compensation cell ready flag */
+#define SYSCFG_CMPCR_READY 0x00000100U /*!<Compensation cell power-down */
+
+/******************************************************************************/
+/* */
+/* TIM */
+/* */
+/******************************************************************************/
+/******************* Bit definition for TIM_CR1 register ********************/
+#define TIM_CR1_CEN 0x0001U /*!<Counter enable */
+#define TIM_CR1_UDIS 0x0002U /*!<Update disable */
+#define TIM_CR1_URS 0x0004U /*!<Update request source */
+#define TIM_CR1_OPM 0x0008U /*!<One pulse mode */
+#define TIM_CR1_DIR 0x0010U /*!<Direction */
+
+#define TIM_CR1_CMS 0x0060U /*!<CMS[1:0] bits (Center-aligned mode selection) */
+#define TIM_CR1_CMS_0 0x0020U /*!<Bit 0 */
+#define TIM_CR1_CMS_1 0x0040U /*!<Bit 1 */
+
+#define TIM_CR1_ARPE 0x0080U /*!<Auto-reload preload enable */
+
+#define TIM_CR1_CKD 0x0300U /*!<CKD[1:0] bits (clock division) */
+#define TIM_CR1_CKD_0 0x0100U /*!<Bit 0 */
+#define TIM_CR1_CKD_1 0x0200U /*!<Bit 1 */
+
+/******************* Bit definition for TIM_CR2 register ********************/
+#define TIM_CR2_CCPC 0x0001U /*!<Capture/Compare Preloaded Control */
+#define TIM_CR2_CCUS 0x0004U /*!<Capture/Compare Control Update Selection */
+#define TIM_CR2_CCDS 0x0008U /*!<Capture/Compare DMA Selection */
+
+#define TIM_CR2_MMS 0x0070U /*!<MMS[2:0] bits (Master Mode Selection) */
+#define TIM_CR2_MMS_0 0x0010U /*!<Bit 0 */
+#define TIM_CR2_MMS_1 0x0020U /*!<Bit 1 */
+#define TIM_CR2_MMS_2 0x0040U /*!<Bit 2 */
+
+#define TIM_CR2_TI1S 0x0080U /*!<TI1 Selection */
+#define TIM_CR2_OIS1 0x0100U /*!<Output Idle state 1 (OC1 output) */
+#define TIM_CR2_OIS1N 0x0200U /*!<Output Idle state 1 (OC1N output) */
+#define TIM_CR2_OIS2 0x0400U /*!<Output Idle state 2 (OC2 output) */
+#define TIM_CR2_OIS2N 0x0800U /*!<Output Idle state 2 (OC2N output) */
+#define TIM_CR2_OIS3 0x1000U /*!<Output Idle state 3 (OC3 output) */
+#define TIM_CR2_OIS3N 0x2000U /*!<Output Idle state 3 (OC3N output) */
+#define TIM_CR2_OIS4 0x4000U /*!<Output Idle state 4 (OC4 output) */
+
+/******************* Bit definition for TIM_SMCR register *******************/
+#define TIM_SMCR_SMS 0x0007U /*!<SMS[2:0] bits (Slave mode selection) */
+#define TIM_SMCR_SMS_0 0x0001U /*!<Bit 0 */
+#define TIM_SMCR_SMS_1 0x0002U /*!<Bit 1 */
+#define TIM_SMCR_SMS_2 0x0004U /*!<Bit 2 */
+
+#define TIM_SMCR_TS 0x0070U /*!<TS[2:0] bits (Trigger selection) */
+#define TIM_SMCR_TS_0 0x0010U /*!<Bit 0 */
+#define TIM_SMCR_TS_1 0x0020U /*!<Bit 1 */
+#define TIM_SMCR_TS_2 0x0040U /*!<Bit 2 */
+
+#define TIM_SMCR_MSM 0x0080U /*!<Master/slave mode */
+
+#define TIM_SMCR_ETF 0x0F00U /*!<ETF[3:0] bits (External trigger filter) */
+#define TIM_SMCR_ETF_0 0x0100U /*!<Bit 0 */
+#define TIM_SMCR_ETF_1 0x0200U /*!<Bit 1 */
+#define TIM_SMCR_ETF_2 0x0400U /*!<Bit 2 */
+#define TIM_SMCR_ETF_3 0x0800U /*!<Bit 3 */
+
+#define TIM_SMCR_ETPS 0x3000U /*!<ETPS[1:0] bits (External trigger prescaler) */
+#define TIM_SMCR_ETPS_0 0x1000U /*!<Bit 0 */
+#define TIM_SMCR_ETPS_1 0x2000U /*!<Bit 1 */
+
+#define TIM_SMCR_ECE 0x4000U /*!<External clock enable */
+#define TIM_SMCR_ETP 0x8000U /*!<External trigger polarity */
+
+/******************* Bit definition for TIM_DIER register *******************/
+#define TIM_DIER_UIE 0x0001U /*!<Update interrupt enable */
+#define TIM_DIER_CC1IE 0x0002U /*!<Capture/Compare 1 interrupt enable */
+#define TIM_DIER_CC2IE 0x0004U /*!<Capture/Compare 2 interrupt enable */
+#define TIM_DIER_CC3IE 0x0008U /*!<Capture/Compare 3 interrupt enable */
+#define TIM_DIER_CC4IE 0x0010U /*!<Capture/Compare 4 interrupt enable */
+#define TIM_DIER_COMIE 0x0020U /*!<COM interrupt enable */
+#define TIM_DIER_TIE 0x0040U /*!<Trigger interrupt enable */
+#define TIM_DIER_BIE 0x0080U /*!<Break interrupt enable */
+#define TIM_DIER_UDE 0x0100U /*!<Update DMA request enable */
+#define TIM_DIER_CC1DE 0x0200U /*!<Capture/Compare 1 DMA request enable */
+#define TIM_DIER_CC2DE 0x0400U /*!<Capture/Compare 2 DMA request enable */
+#define TIM_DIER_CC3DE 0x0800U /*!<Capture/Compare 3 DMA request enable */
+#define TIM_DIER_CC4DE 0x1000U /*!<Capture/Compare 4 DMA request enable */
+#define TIM_DIER_COMDE 0x2000U /*!<COM DMA request enable */
+#define TIM_DIER_TDE 0x4000U /*!<Trigger DMA request enable */
+
+/******************** Bit definition for TIM_SR register ********************/
+#define TIM_SR_UIF 0x0001U /*!<Update interrupt Flag */
+#define TIM_SR_CC1IF 0x0002U /*!<Capture/Compare 1 interrupt Flag */
+#define TIM_SR_CC2IF 0x0004U /*!<Capture/Compare 2 interrupt Flag */
+#define TIM_SR_CC3IF 0x0008U /*!<Capture/Compare 3 interrupt Flag */
+#define TIM_SR_CC4IF 0x0010U /*!<Capture/Compare 4 interrupt Flag */
+#define TIM_SR_COMIF 0x0020U /*!<COM interrupt Flag */
+#define TIM_SR_TIF 0x0040U /*!<Trigger interrupt Flag */
+#define TIM_SR_BIF 0x0080U /*!<Break interrupt Flag */
+#define TIM_SR_CC1OF 0x0200U /*!<Capture/Compare 1 Overcapture Flag */
+#define TIM_SR_CC2OF 0x0400U /*!<Capture/Compare 2 Overcapture Flag */
+#define TIM_SR_CC3OF 0x0800U /*!<Capture/Compare 3 Overcapture Flag */
+#define TIM_SR_CC4OF 0x1000U /*!<Capture/Compare 4 Overcapture Flag */
+
+/******************* Bit definition for TIM_EGR register ********************/
+#define TIM_EGR_UG 0x01U /*!<Update Generation */
+#define TIM_EGR_CC1G 0x02U /*!<Capture/Compare 1 Generation */
+#define TIM_EGR_CC2G 0x04U /*!<Capture/Compare 2 Generation */
+#define TIM_EGR_CC3G 0x08U /*!<Capture/Compare 3 Generation */
+#define TIM_EGR_CC4G 0x10U /*!<Capture/Compare 4 Generation */
+#define TIM_EGR_COMG 0x20U /*!<Capture/Compare Control Update Generation */
+#define TIM_EGR_TG 0x40U /*!<Trigger Generation */
+#define TIM_EGR_BG 0x80U /*!<Break Generation */
+
+/****************** Bit definition for TIM_CCMR1 register *******************/
+#define TIM_CCMR1_CC1S 0x0003U /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
+#define TIM_CCMR1_CC1S_0 0x0001U /*!<Bit 0 */
+#define TIM_CCMR1_CC1S_1 0x0002U /*!<Bit 1 */
+
+#define TIM_CCMR1_OC1FE 0x0004U /*!<Output Compare 1 Fast enable */
+#define TIM_CCMR1_OC1PE 0x0008U /*!<Output Compare 1 Preload enable */
+
+#define TIM_CCMR1_OC1M 0x0070U /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
+#define TIM_CCMR1_OC1M_0 0x0010U /*!<Bit 0 */
+#define TIM_CCMR1_OC1M_1 0x0020U /*!<Bit 1 */
+#define TIM_CCMR1_OC1M_2 0x0040U /*!<Bit 2 */
+
+#define TIM_CCMR1_OC1CE 0x0080U /*!<Output Compare 1Clear Enable */
+
+#define TIM_CCMR1_CC2S 0x0300U /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
+#define TIM_CCMR1_CC2S_0 0x0100U /*!<Bit 0 */
+#define TIM_CCMR1_CC2S_1 0x0200U /*!<Bit 1 */
+
+#define TIM_CCMR1_OC2FE 0x0400U /*!<Output Compare 2 Fast enable */
+#define TIM_CCMR1_OC2PE 0x0800U /*!<Output Compare 2 Preload enable */
+
+#define TIM_CCMR1_OC2M 0x7000U /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
+#define TIM_CCMR1_OC2M_0 0x1000U /*!<Bit 0 */
+#define TIM_CCMR1_OC2M_1 0x2000U /*!<Bit 1 */
+#define TIM_CCMR1_OC2M_2 0x4000U /*!<Bit 2 */
+
+#define TIM_CCMR1_OC2CE 0x8000U /*!<Output Compare 2 Clear Enable */
+
+/*----------------------------------------------------------------------------*/
+
+#define TIM_CCMR1_IC1PSC 0x000CU /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
+#define TIM_CCMR1_IC1PSC_0 0x0004U /*!<Bit 0 */
+#define TIM_CCMR1_IC1PSC_1 0x0008U /*!<Bit 1 */
+
+#define TIM_CCMR1_IC1F 0x00F0U /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
+#define TIM_CCMR1_IC1F_0 0x0010U /*!<Bit 0 */
+#define TIM_CCMR1_IC1F_1 0x0020U /*!<Bit 1 */
+#define TIM_CCMR1_IC1F_2 0x0040U /*!<Bit 2 */
+#define TIM_CCMR1_IC1F_3 0x0080U /*!<Bit 3 */
+
+#define TIM_CCMR1_IC2PSC 0x0C00U /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
+#define TIM_CCMR1_IC2PSC_0 0x0400U /*!<Bit 0 */
+#define TIM_CCMR1_IC2PSC_1 0x0800U /*!<Bit 1 */
+
+#define TIM_CCMR1_IC2F 0xF000U /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
+#define TIM_CCMR1_IC2F_0 0x1000U /*!<Bit 0 */
+#define TIM_CCMR1_IC2F_1 0x2000U /*!<Bit 1 */
+#define TIM_CCMR1_IC2F_2 0x4000U /*!<Bit 2 */
+#define TIM_CCMR1_IC2F_3 0x8000U /*!<Bit 3 */
+
+/****************** Bit definition for TIM_CCMR2 register *******************/
+#define TIM_CCMR2_CC3S 0x0003U /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
+#define TIM_CCMR2_CC3S_0 0x0001U /*!<Bit 0 */
+#define TIM_CCMR2_CC3S_1 0x0002U /*!<Bit 1 */
+
+#define TIM_CCMR2_OC3FE 0x0004U /*!<Output Compare 3 Fast enable */
+#define TIM_CCMR2_OC3PE 0x0008U /*!<Output Compare 3 Preload enable */
+
+#define TIM_CCMR2_OC3M 0x0070U /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
+#define TIM_CCMR2_OC3M_0 0x0010U /*!<Bit 0 */
+#define TIM_CCMR2_OC3M_1 0x0020U /*!<Bit 1 */
+#define TIM_CCMR2_OC3M_2 0x0040U /*!<Bit 2 */
+
+#define TIM_CCMR2_OC3CE 0x0080U /*!<Output Compare 3 Clear Enable */
+
+#define TIM_CCMR2_CC4S 0x0300U /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
+#define TIM_CCMR2_CC4S_0 0x0100U /*!<Bit 0 */
+#define TIM_CCMR2_CC4S_1 0x0200U /*!<Bit 1 */
+
+#define TIM_CCMR2_OC4FE 0x0400U /*!<Output Compare 4 Fast enable */
+#define TIM_CCMR2_OC4PE 0x0800U /*!<Output Compare 4 Preload enable */
+
+#define TIM_CCMR2_OC4M 0x7000U /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
+#define TIM_CCMR2_OC4M_0 0x1000U /*!<Bit 0 */
+#define TIM_CCMR2_OC4M_1 0x2000U /*!<Bit 1 */
+#define TIM_CCMR2_OC4M_2 0x4000U /*!<Bit 2 */
+
+#define TIM_CCMR2_OC4CE 0x8000U /*!<Output Compare 4 Clear Enable */
+
+/*----------------------------------------------------------------------------*/
+
+#define TIM_CCMR2_IC3PSC 0x000CU /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
+#define TIM_CCMR2_IC3PSC_0 0x0004U /*!<Bit 0 */
+#define TIM_CCMR2_IC3PSC_1 0x0008U /*!<Bit 1 */
+
+#define TIM_CCMR2_IC3F 0x00F0U /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
+#define TIM_CCMR2_IC3F_0 0x0010U /*!<Bit 0 */
+#define TIM_CCMR2_IC3F_1 0x0020U /*!<Bit 1 */
+#define TIM_CCMR2_IC3F_2 0x0040U /*!<Bit 2 */
+#define TIM_CCMR2_IC3F_3 0x0080U /*!<Bit 3 */
+
+#define TIM_CCMR2_IC4PSC 0x0C00U /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
+#define TIM_CCMR2_IC4PSC_0 0x0400U /*!<Bit 0 */
+#define TIM_CCMR2_IC4PSC_1 0x0800U /*!<Bit 1 */
+
+#define TIM_CCMR2_IC4F 0xF000U /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
+#define TIM_CCMR2_IC4F_0 0x1000U /*!<Bit 0 */
+#define TIM_CCMR2_IC4F_1 0x2000U /*!<Bit 1 */
+#define TIM_CCMR2_IC4F_2 0x4000U /*!<Bit 2 */
+#define TIM_CCMR2_IC4F_3 0x8000U /*!<Bit 3 */
+
+/******************* Bit definition for TIM_CCER register *******************/
+#define TIM_CCER_CC1E 0x0001U /*!<Capture/Compare 1 output enable */
+#define TIM_CCER_CC1P 0x0002U /*!<Capture/Compare 1 output Polarity */
+#define TIM_CCER_CC1NE 0x0004U /*!<Capture/Compare 1 Complementary output enable */
+#define TIM_CCER_CC1NP 0x0008U /*!<Capture/Compare 1 Complementary output Polarity */
+#define TIM_CCER_CC2E 0x0010U /*!<Capture/Compare 2 output enable */
+#define TIM_CCER_CC2P 0x0020U /*!<Capture/Compare 2 output Polarity */
+#define TIM_CCER_CC2NE 0x0040U /*!<Capture/Compare 2 Complementary output enable */
+#define TIM_CCER_CC2NP 0x0080U /*!<Capture/Compare 2 Complementary output Polarity */
+#define TIM_CCER_CC3E 0x0100U /*!<Capture/Compare 3 output enable */
+#define TIM_CCER_CC3P 0x0200U /*!<Capture/Compare 3 output Polarity */
+#define TIM_CCER_CC3NE 0x0400U /*!<Capture/Compare 3 Complementary output enable */
+#define TIM_CCER_CC3NP 0x0800U /*!<Capture/Compare 3 Complementary output Polarity */
+#define TIM_CCER_CC4E 0x1000U /*!<Capture/Compare 4 output enable */
+#define TIM_CCER_CC4P 0x2000U /*!<Capture/Compare 4 output Polarity */
+#define TIM_CCER_CC4NP 0x8000U /*!<Capture/Compare 4 Complementary output Polarity */
+
+/******************* Bit definition for TIM_CNT register ********************/
+#define TIM_CNT_CNT 0xFFFFU /*!<Counter Value */
+
+/******************* Bit definition for TIM_PSC register ********************/
+#define TIM_PSC_PSC 0xFFFFU /*!<Prescaler Value */
+
+/******************* Bit definition for TIM_ARR register ********************/
+#define TIM_ARR_ARR 0xFFFFU /*!<actual auto-reload Value */
+
+/******************* Bit definition for TIM_RCR register ********************/
+#define TIM_RCR_REP 0xFFU /*!<Repetition Counter Value */
+
+/******************* Bit definition for TIM_CCR1 register *******************/
+#define TIM_CCR1_CCR1 0xFFFFU /*!<Capture/Compare 1 Value */
+
+/******************* Bit definition for TIM_CCR2 register *******************/
+#define TIM_CCR2_CCR2 0xFFFFU /*!<Capture/Compare 2 Value */
+
+/******************* Bit definition for TIM_CCR3 register *******************/
+#define TIM_CCR3_CCR3 0xFFFFU /*!<Capture/Compare 3 Value */
+
+/******************* Bit definition for TIM_CCR4 register *******************/
+#define TIM_CCR4_CCR4 0xFFFFU /*!<Capture/Compare 4 Value */
+
+/******************* Bit definition for TIM_BDTR register *******************/
+#define TIM_BDTR_DTG 0x00FFU /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
+#define TIM_BDTR_DTG_0 0x0001U /*!<Bit 0 */
+#define TIM_BDTR_DTG_1 0x0002U /*!<Bit 1 */
+#define TIM_BDTR_DTG_2 0x0004U /*!<Bit 2 */
+#define TIM_BDTR_DTG_3 0x0008U /*!<Bit 3 */
+#define TIM_BDTR_DTG_4 0x0010U /*!<Bit 4 */
+#define TIM_BDTR_DTG_5 0x0020U /*!<Bit 5 */
+#define TIM_BDTR_DTG_6 0x0040U /*!<Bit 6 */
+#define TIM_BDTR_DTG_7 0x0080U /*!<Bit 7 */
+
+#define TIM_BDTR_LOCK 0x0300U /*!<LOCK[1:0] bits (Lock Configuration) */
+#define TIM_BDTR_LOCK_0 0x0100U /*!<Bit 0 */
+#define TIM_BDTR_LOCK_1 0x0200U /*!<Bit 1 */
+
+#define TIM_BDTR_OSSI 0x0400U /*!<Off-State Selection for Idle mode */
+#define TIM_BDTR_OSSR 0x0800U /*!<Off-State Selection for Run mode */
+#define TIM_BDTR_BKE 0x1000U /*!<Break enable */
+#define TIM_BDTR_BKP 0x2000U /*!<Break Polarity */
+#define TIM_BDTR_AOE 0x4000U /*!<Automatic Output enable */
+#define TIM_BDTR_MOE 0x8000U /*!<Main Output enable */
+
+/******************* Bit definition for TIM_DCR register ********************/
+#define TIM_DCR_DBA 0x001FU /*!<DBA[4:0] bits (DMA Base Address) */
+#define TIM_DCR_DBA_0 0x0001U /*!<Bit 0 */
+#define TIM_DCR_DBA_1 0x0002U /*!<Bit 1 */
+#define TIM_DCR_DBA_2 0x0004U /*!<Bit 2 */
+#define TIM_DCR_DBA_3 0x0008U /*!<Bit 3 */
+#define TIM_DCR_DBA_4 0x0010U /*!<Bit 4 */
+
+#define TIM_DCR_DBL 0x1F00U /*!<DBL[4:0] bits (DMA Burst Length) */
+#define TIM_DCR_DBL_0 0x0100U /*!<Bit 0 */
+#define TIM_DCR_DBL_1 0x0200U /*!<Bit 1 */
+#define TIM_DCR_DBL_2 0x0400U /*!<Bit 2 */
+#define TIM_DCR_DBL_3 0x0800U /*!<Bit 3 */
+#define TIM_DCR_DBL_4 0x1000U /*!<Bit 4 */
+
+/******************* Bit definition for TIM_DMAR register *******************/
+#define TIM_DMAR_DMAB 0xFFFFU /*!<DMA register for burst accesses */
+
+/******************* Bit definition for TIM_OR register *********************/
+#define TIM_OR_TI4_RMP 0x00C0U /*!<TI4_RMP[1:0] bits (TIM5 Input 4 remap) */
+#define TIM_OR_TI4_RMP_0 0x0040U /*!<Bit 0 */
+#define TIM_OR_TI4_RMP_1 0x0080U /*!<Bit 1 */
+#define TIM_OR_ITR1_RMP 0x0C00U /*!<ITR1_RMP[1:0] bits (TIM2 Internal trigger 1 remap) */
+#define TIM_OR_ITR1_RMP_0 0x0400U /*!<Bit 0 */
+#define TIM_OR_ITR1_RMP_1 0x0800U /*!<Bit 1 */
+
+
+/******************************************************************************/
+/* */
+/* Universal Synchronous Asynchronous Receiver Transmitter */
+/* */
+/******************************************************************************/
+/******************* Bit definition for USART_SR register *******************/
+#define USART_SR_PE 0x0001U /*!<Parity Error */
+#define USART_SR_FE 0x0002U /*!<Framing Error */
+#define USART_SR_NE 0x0004U /*!<Noise Error Flag */
+#define USART_SR_ORE 0x0008U /*!<OverRun Error */
+#define USART_SR_IDLE 0x0010U /*!<IDLE line detected */
+#define USART_SR_RXNE 0x0020U /*!<Read Data Register Not Empty */
+#define USART_SR_TC 0x0040U /*!<Transmission Complete */
+#define USART_SR_TXE 0x0080U /*!<Transmit Data Register Empty */
+#define USART_SR_LBD 0x0100U /*!<LIN Break Detection Flag */
+#define USART_SR_CTS 0x0200U /*!<CTS Flag */
+
+/******************* Bit definition for USART_DR register *******************/
+#define USART_DR_DR 0x01FFU /*!<Data value */
+
+/****************** Bit definition for USART_BRR register *******************/
+#define USART_BRR_DIV_Fraction 0x000FU /*!<Fraction of USARTDIV */
+#define USART_BRR_DIV_Mantissa 0xFFF0U /*!<Mantissa of USARTDIV */
+
+/****************** Bit definition for USART_CR1 register *******************/
+#define USART_CR1_SBK 0x0001U /*!<Send Break */
+#define USART_CR1_RWU 0x0002U /*!<Receiver wakeup */
+#define USART_CR1_RE 0x0004U /*!<Receiver Enable */
+#define USART_CR1_TE 0x0008U /*!<Transmitter Enable */
+#define USART_CR1_IDLEIE 0x0010U /*!<IDLE Interrupt Enable */
+#define USART_CR1_RXNEIE 0x0020U /*!<RXNE Interrupt Enable */
+#define USART_CR1_TCIE 0x0040U /*!<Transmission Complete Interrupt Enable */
+#define USART_CR1_TXEIE 0x0080U /*!<PE Interrupt Enable */
+#define USART_CR1_PEIE 0x0100U /*!<PE Interrupt Enable */
+#define USART_CR1_PS 0x0200U /*!<Parity Selection */
+#define USART_CR1_PCE 0x0400U /*!<Parity Control Enable */
+#define USART_CR1_WAKE 0x0800U /*!<Wakeup method */
+#define USART_CR1_M 0x1000U /*!<Word length */
+#define USART_CR1_UE 0x2000U /*!<USART Enable */
+#define USART_CR1_OVER8 0x8000U /*!<USART Oversampling by 8 enable */
+
+/****************** Bit definition for USART_CR2 register *******************/
+#define USART_CR2_ADD 0x000FU /*!<Address of the USART node */
+#define USART_CR2_LBDL 0x0020U /*!<LIN Break Detection Length */
+#define USART_CR2_LBDIE 0x0040U /*!<LIN Break Detection Interrupt Enable */
+#define USART_CR2_LBCL 0x0100U /*!<Last Bit Clock pulse */
+#define USART_CR2_CPHA 0x0200U /*!<Clock Phase */
+#define USART_CR2_CPOL 0x0400U /*!<Clock Polarity */
+#define USART_CR2_CLKEN 0x0800U /*!<Clock Enable */
+
+#define USART_CR2_STOP 0x3000U /*!<STOP[1:0] bits (STOP bits) */
+#define USART_CR2_STOP_0 0x1000U /*!<Bit 0 */
+#define USART_CR2_STOP_1 0x2000U /*!<Bit 1 */
+
+#define USART_CR2_LINEN 0x4000U /*!<LIN mode enable */
+
+/****************** Bit definition for USART_CR3 register *******************/
+#define USART_CR3_EIE 0x0001U /*!<Error Interrupt Enable */
+#define USART_CR3_IREN 0x0002U /*!<IrDA mode Enable */
+#define USART_CR3_IRLP 0x0004U /*!<IrDA Low-Power */
+#define USART_CR3_HDSEL 0x0008U /*!<Half-Duplex Selection */
+#define USART_CR3_NACK 0x0010U /*!<Smartcard NACK enable */
+#define USART_CR3_SCEN 0x0020U /*!<Smartcard mode enable */
+#define USART_CR3_DMAR 0x0040U /*!<DMA Enable Receiver */
+#define USART_CR3_DMAT 0x0080U /*!<DMA Enable Transmitter */
+#define USART_CR3_RTSE 0x0100U /*!<RTS Enable */
+#define USART_CR3_CTSE 0x0200U /*!<CTS Enable */
+#define USART_CR3_CTSIE 0x0400U /*!<CTS Interrupt Enable */
+#define USART_CR3_ONEBIT 0x0800U /*!<USART One bit method enable */
+
+/****************** Bit definition for USART_GTPR register ******************/
+#define USART_GTPR_PSC 0x00FFU /*!<PSC[7:0] bits (Prescaler value) */
+#define USART_GTPR_PSC_0 0x0001U /*!<Bit 0 */
+#define USART_GTPR_PSC_1 0x0002U /*!<Bit 1 */
+#define USART_GTPR_PSC_2 0x0004U /*!<Bit 2 */
+#define USART_GTPR_PSC_3 0x0008U /*!<Bit 3 */
+#define USART_GTPR_PSC_4 0x0010U /*!<Bit 4 */
+#define USART_GTPR_PSC_5 0x0020U /*!<Bit 5 */
+#define USART_GTPR_PSC_6 0x0040U /*!<Bit 6 */
+#define USART_GTPR_PSC_7 0x0080U /*!<Bit 7 */
+
+#define USART_GTPR_GT 0xFF00U /*!<Guard time value */
+
+/******************************************************************************/
+/* */
+/* Window WATCHDOG */
+/* */
+/******************************************************************************/
+/******************* Bit definition for WWDG_CR register ********************/
+#define WWDG_CR_T 0x7FU /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
+#define WWDG_CR_T_0 0x01U /*!<Bit 0 */
+#define WWDG_CR_T_1 0x02U /*!<Bit 1 */
+#define WWDG_CR_T_2 0x04U /*!<Bit 2 */
+#define WWDG_CR_T_3 0x08U /*!<Bit 3 */
+#define WWDG_CR_T_4 0x10U /*!<Bit 4 */
+#define WWDG_CR_T_5 0x20U /*!<Bit 5 */
+#define WWDG_CR_T_6 0x40U /*!<Bit 6 */
+/* Legacy defines */
+#define WWDG_CR_T0 WWDG_CR_T_0
+#define WWDG_CR_T1 WWDG_CR_T_1
+#define WWDG_CR_T2 WWDG_CR_T_2
+#define WWDG_CR_T3 WWDG_CR_T_3
+#define WWDG_CR_T4 WWDG_CR_T_4
+#define WWDG_CR_T5 WWDG_CR_T_5
+#define WWDG_CR_T6 WWDG_CR_T_6
+
+#define WWDG_CR_WDGA 0x80U /*!<Activation bit */
+
+/******************* Bit definition for WWDG_CFR register *******************/
+#define WWDG_CFR_W 0x007FU /*!<W[6:0] bits (7-bit window value) */
+#define WWDG_CFR_W_0 0x0001U /*!<Bit 0 */
+#define WWDG_CFR_W_1 0x0002U /*!<Bit 1 */
+#define WWDG_CFR_W_2 0x0004U /*!<Bit 2 */
+#define WWDG_CFR_W_3 0x0008U /*!<Bit 3 */
+#define WWDG_CFR_W_4 0x0010U /*!<Bit 4 */
+#define WWDG_CFR_W_5 0x0020U /*!<Bit 5 */
+#define WWDG_CFR_W_6 0x0040U /*!<Bit 6 */
+/* Legacy defines */
+#define WWDG_CFR_W0 WWDG_CFR_W_0
+#define WWDG_CFR_W1 WWDG_CFR_W_1
+#define WWDG_CFR_W2 WWDG_CFR_W_2
+#define WWDG_CFR_W3 WWDG_CFR_W_3
+#define WWDG_CFR_W4 WWDG_CFR_W_4
+#define WWDG_CFR_W5 WWDG_CFR_W_5
+#define WWDG_CFR_W6 WWDG_CFR_W_6
+
+#define WWDG_CFR_WDGTB 0x0180U /*!<WDGTB[1:0] bits (Timer Base) */
+#define WWDG_CFR_WDGTB_0 0x0080U /*!<Bit 0 */
+#define WWDG_CFR_WDGTB_1 0x0100U /*!<Bit 1 */
+/* Legacy defines */
+#define WWDG_CFR_WDGTB0 WWDG_CFR_WDGTB_0
+#define WWDG_CFR_WDGTB1 WWDG_CFR_WDGTB_1
+
+#define WWDG_CFR_EWI 0x0200U /*!<Early Wakeup Interrupt */
+
+/******************* Bit definition for WWDG_SR register ********************/
+#define WWDG_SR_EWIF 0x01U /*!<Early Wakeup Interrupt Flag */
+
+
+/******************************************************************************/
+/* */
+/* DBG */
+/* */
+/******************************************************************************/
+/******************** Bit definition for DBGMCU_IDCODE register *************/
+#define DBGMCU_IDCODE_DEV_ID 0x00000FFFU
+#define DBGMCU_IDCODE_REV_ID 0xFFFF0000U
+
+/******************** Bit definition for DBGMCU_CR register *****************/
+#define DBGMCU_CR_DBG_SLEEP 0x00000001U
+#define DBGMCU_CR_DBG_STOP 0x00000002U
+#define DBGMCU_CR_DBG_STANDBY 0x00000004U
+#define DBGMCU_CR_TRACE_IOEN 0x00000020U
+
+#define DBGMCU_CR_TRACE_MODE 0x000000C0U
+#define DBGMCU_CR_TRACE_MODE_0 0x00000040U/*!<Bit 0 */
+#define DBGMCU_CR_TRACE_MODE_1 0x00000080U/*!<Bit 1 */
+
+/******************** Bit definition for DBGMCU_APB1_FZ register ************/
+#define DBGMCU_APB1_FZ_DBG_TIM2_STOP 0x00000001U
+#define DBGMCU_APB1_FZ_DBG_TIM3_STOP 0x00000002U
+#define DBGMCU_APB1_FZ_DBG_TIM4_STOP 0x00000004U
+#define DBGMCU_APB1_FZ_DBG_TIM5_STOP 0x00000008U
+#define DBGMCU_APB1_FZ_DBG_TIM6_STOP 0x00000010U
+#define DBGMCU_APB1_FZ_DBG_TIM7_STOP 0x00000020U
+#define DBGMCU_APB1_FZ_DBG_TIM12_STOP 0x00000040U
+#define DBGMCU_APB1_FZ_DBG_TIM13_STOP 0x00000080U
+#define DBGMCU_APB1_FZ_DBG_TIM14_STOP 0x00000100U
+#define DBGMCU_APB1_FZ_DBG_RTC_STOP 0x00000400U
+#define DBGMCU_APB1_FZ_DBG_WWDG_STOP 0x00000800U
+#define DBGMCU_APB1_FZ_DBG_IWDG_STOP 0x00001000U
+#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT 0x00200000U
+#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT 0x00400000U
+#define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT 0x00800000U
+#define DBGMCU_APB1_FZ_DBG_CAN1_STOP 0x02000000U
+#define DBGMCU_APB1_FZ_DBG_CAN2_STOP 0x04000000U
+/* Old IWDGSTOP bit definition, maintained for legacy purpose */
+#define DBGMCU_APB1_FZ_DBG_IWDEG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP
+
+/******************** Bit definition for DBGMCU_APB2_FZ register ************/
+#define DBGMCU_APB2_FZ_DBG_TIM1_STOP 0x00000001U
+#define DBGMCU_APB2_FZ_DBG_TIM8_STOP 0x00000002U
+#define DBGMCU_APB2_FZ_DBG_TIM9_STOP 0x00010000U
+#define DBGMCU_APB2_FZ_DBG_TIM10_STOP 0x00020000U
+#define DBGMCU_APB2_FZ_DBG_TIM11_STOP 0x00040000U
+
+/******************************************************************************/
+/* */
+/* Ethernet MAC Registers bits definitions */
+/* */
+/******************************************************************************/
+/* Bit definition for Ethernet MAC Control Register register */
+#define ETH_MACCR_WD 0x00800000U /* Watchdog disable */
+#define ETH_MACCR_JD 0x00400000U /* Jabber disable */
+#define ETH_MACCR_IFG 0x000E0000U /* Inter-frame gap */
+#define ETH_MACCR_IFG_96Bit 0x00000000U /* Minimum IFG between frames during transmission is 96Bit */
+ #define ETH_MACCR_IFG_88Bit 0x00020000U /* Minimum IFG between frames during transmission is 88Bit */
+ #define ETH_MACCR_IFG_80Bit 0x00040000U /* Minimum IFG between frames during transmission is 80Bit */
+ #define ETH_MACCR_IFG_72Bit 0x00060000U /* Minimum IFG between frames during transmission is 72Bit */
+ #define ETH_MACCR_IFG_64Bit 0x00080000U /* Minimum IFG between frames during transmission is 64Bit */
+ #define ETH_MACCR_IFG_56Bit 0x000A0000U /* Minimum IFG between frames during transmission is 56Bit */
+ #define ETH_MACCR_IFG_48Bit 0x000C0000U /* Minimum IFG between frames during transmission is 48Bit */
+ #define ETH_MACCR_IFG_40Bit 0x000E0000U /* Minimum IFG between frames during transmission is 40Bit */
+#define ETH_MACCR_CSD 0x00010000U /* Carrier sense disable (during transmission) */
+#define ETH_MACCR_FES 0x00004000U /* Fast ethernet speed */
+#define ETH_MACCR_ROD 0x00002000U /* Receive own disable */
+#define ETH_MACCR_LM 0x00001000U /* loopback mode */
+#define ETH_MACCR_DM 0x00000800U /* Duplex mode */
+#define ETH_MACCR_IPCO 0x00000400U /* IP Checksum offload */
+#define ETH_MACCR_RD 0x00000200U /* Retry disable */
+#define ETH_MACCR_APCS 0x00000080U /* Automatic Pad/CRC stripping */
+#define ETH_MACCR_BL 0x00000060U /* Back-off limit: random integer number (r) of slot time delays before rescheduling
+ a transmission attempt during retries after a collision: 0 =< r <2^k */
+ #define ETH_MACCR_BL_10 0x00000000U /* k = min (n, 10) */
+ #define ETH_MACCR_BL_8 0x00000020U /* k = min (n, 8) */
+ #define ETH_MACCR_BL_4 0x00000040U /* k = min (n, 4) */
+ #define ETH_MACCR_BL_1 0x00000060U /* k = min (n, 1) */
+#define ETH_MACCR_DC 0x00000010U /* Defferal check */
+#define ETH_MACCR_TE 0x00000008U /* Transmitter enable */
+#define ETH_MACCR_RE 0x00000004U /* Receiver enable */
+
+/* Bit definition for Ethernet MAC Frame Filter Register */
+#define ETH_MACFFR_RA 0x80000000U /* Receive all */
+#define ETH_MACFFR_HPF 0x00000400U /* Hash or perfect filter */
+#define ETH_MACFFR_SAF 0x00000200U /* Source address filter enable */
+#define ETH_MACFFR_SAIF 0x00000100U /* SA inverse filtering */
+#define ETH_MACFFR_PCF 0x000000C0U /* Pass control frames: 3 cases */
+ #define ETH_MACFFR_PCF_BlockAll 0x00000040U /* MAC filters all control frames from reaching the application */
+ #define ETH_MACFFR_PCF_ForwardAll 0x00000080U /* MAC forwards all control frames to application even if they fail the Address Filter */
+ #define ETH_MACFFR_PCF_ForwardPassedAddrFilter 0x000000C0U /* MAC forwards control frames that pass the Address Filter. */
+#define ETH_MACFFR_BFD 0x00000020U /* Broadcast frame disable */
+#define ETH_MACFFR_PAM 0x00000010U /* Pass all mutlicast */
+#define ETH_MACFFR_DAIF 0x00000008U /* DA Inverse filtering */
+#define ETH_MACFFR_HM 0x00000004U /* Hash multicast */
+#define ETH_MACFFR_HU 0x00000002U /* Hash unicast */
+#define ETH_MACFFR_PM 0x00000001U /* Promiscuous mode */
+
+/* Bit definition for Ethernet MAC Hash Table High Register */
+#define ETH_MACHTHR_HTH 0xFFFFFFFFU /* Hash table high */
+
+/* Bit definition for Ethernet MAC Hash Table Low Register */
+#define ETH_MACHTLR_HTL 0xFFFFFFFFU /* Hash table low */
+
+/* Bit definition for Ethernet MAC MII Address Register */
+#define ETH_MACMIIAR_PA 0x0000F800U /* Physical layer address */
+#define ETH_MACMIIAR_MR 0x000007C0U /* MII register in the selected PHY */
+#define ETH_MACMIIAR_CR 0x0000001CU /* CR clock range: 6 cases */
+ #define ETH_MACMIIAR_CR_Div42 0x00000000U /* HCLK:60-100 MHz; MDC clock= HCLK/42 */
+ #define ETH_MACMIIAR_CR_Div62 0x00000004U /* HCLK:100-150 MHz; MDC clock= HCLK/62 */
+ #define ETH_MACMIIAR_CR_Div16 0x00000008U /* HCLK:20-35 MHz; MDC clock= HCLK/16 */
+ #define ETH_MACMIIAR_CR_Div26 0x0000000CU /* HCLK:35-60 MHz; MDC clock= HCLK/26 */
+ #define ETH_MACMIIAR_CR_Div102 0x00000010U /* HCLK:150-168 MHz; MDC clock= HCLK/102 */
+#define ETH_MACMIIAR_MW 0x00000002U /* MII write */
+#define ETH_MACMIIAR_MB 0x00000001U /* MII busy */
+
+/* Bit definition for Ethernet MAC MII Data Register */
+#define ETH_MACMIIDR_MD 0x0000FFFFU /* MII data: read/write data from/to PHY */
+
+/* Bit definition for Ethernet MAC Flow Control Register */
+#define ETH_MACFCR_PT 0xFFFF0000U /* Pause time */
+#define ETH_MACFCR_ZQPD 0x00000080U /* Zero-quanta pause disable */
+#define ETH_MACFCR_PLT 0x00000030U /* Pause low threshold: 4 cases */
+ #define ETH_MACFCR_PLT_Minus4 0x00000000U /* Pause time minus 4 slot times */
+ #define ETH_MACFCR_PLT_Minus28 0x00000010U /* Pause time minus 28 slot times */
+ #define ETH_MACFCR_PLT_Minus144 0x00000020U /* Pause time minus 144 slot times */
+ #define ETH_MACFCR_PLT_Minus256 0x00000030U /* Pause time minus 256 slot times */
+#define ETH_MACFCR_UPFD 0x00000008U /* Unicast pause frame detect */
+#define ETH_MACFCR_RFCE 0x00000004U /* Receive flow control enable */
+#define ETH_MACFCR_TFCE 0x00000002U /* Transmit flow control enable */
+#define ETH_MACFCR_FCBBPA 0x00000001U /* Flow control busy/backpressure activate */
+
+/* Bit definition for Ethernet MAC VLAN Tag Register */
+#define ETH_MACVLANTR_VLANTC 0x00010000U /* 12-bit VLAN tag comparison */
+#define ETH_MACVLANTR_VLANTI 0x0000FFFFU /* VLAN tag identifier (for receive frames) */
+
+/* Bit definition for Ethernet MAC Remote Wake-UpFrame Filter Register */
+#define ETH_MACRWUFFR_D 0xFFFFFFFFU /* Wake-up frame filter register data */
+/* Eight sequential Writes to this address (offset 0x28) will write all Wake-UpFrame Filter Registers.
+ Eight sequential Reads from this address (offset 0x28) will read all Wake-UpFrame Filter Registers. */
+/* Wake-UpFrame Filter Reg0 : Filter 0 Byte Mask
+ Wake-UpFrame Filter Reg1 : Filter 1 Byte Mask
+ Wake-UpFrame Filter Reg2 : Filter 2 Byte Mask
+ Wake-UpFrame Filter Reg3 : Filter 3 Byte Mask
+ Wake-UpFrame Filter Reg4 : RSVD - Filter3 Command - RSVD - Filter2 Command -
+ RSVD - Filter1 Command - RSVD - Filter0 Command
+ Wake-UpFrame Filter Re5 : Filter3 Offset - Filter2 Offset - Filter1 Offset - Filter0 Offset
+ Wake-UpFrame Filter Re6 : Filter1 CRC16 - Filter0 CRC16
+ Wake-UpFrame Filter Re7 : Filter3 CRC16 - Filter2 CRC16 */
+
+/* Bit definition for Ethernet MAC PMT Control and Status Register */
+#define ETH_MACPMTCSR_WFFRPR 0x80000000U /* Wake-Up Frame Filter Register Pointer Reset */
+#define ETH_MACPMTCSR_GU 0x00000200U /* Global Unicast */
+#define ETH_MACPMTCSR_WFR 0x00000040U /* Wake-Up Frame Received */
+#define ETH_MACPMTCSR_MPR 0x00000020U /* Magic Packet Received */
+#define ETH_MACPMTCSR_WFE 0x00000004U /* Wake-Up Frame Enable */
+#define ETH_MACPMTCSR_MPE 0x00000002U /* Magic Packet Enable */
+#define ETH_MACPMTCSR_PD 0x00000001U /* Power Down */
+
+/* Bit definition for Ethernet MAC Status Register */
+#define ETH_MACSR_TSTS 0x00000200U /* Time stamp trigger status */
+#define ETH_MACSR_MMCTS 0x00000040U /* MMC transmit status */
+#define ETH_MACSR_MMMCRS 0x00000020U /* MMC receive status */
+#define ETH_MACSR_MMCS 0x00000010U /* MMC status */
+#define ETH_MACSR_PMTS 0x00000008U /* PMT status */
+
+/* Bit definition for Ethernet MAC Interrupt Mask Register */
+#define ETH_MACIMR_TSTIM 0x00000200U /* Time stamp trigger interrupt mask */
+#define ETH_MACIMR_PMTIM 0x00000008U /* PMT interrupt mask */
+
+/* Bit definition for Ethernet MAC Address0 High Register */
+#define ETH_MACA0HR_MACA0H 0x0000FFFFU /* MAC address0 high */
+
+/* Bit definition for Ethernet MAC Address0 Low Register */
+#define ETH_MACA0LR_MACA0L 0xFFFFFFFFU /* MAC address0 low */
+
+/* Bit definition for Ethernet MAC Address1 High Register */
+#define ETH_MACA1HR_AE 0x80000000U /* Address enable */
+#define ETH_MACA1HR_SA 0x40000000U /* Source address */
+#define ETH_MACA1HR_MBC 0x3F000000U /* Mask byte control: bits to mask for comparison of the MAC Address bytes */
+ #define ETH_MACA1HR_MBC_HBits15_8 0x20000000U /* Mask MAC Address high reg bits [15:8] */
+ #define ETH_MACA1HR_MBC_HBits7_0 0x10000000U /* Mask MAC Address high reg bits [7:0] */
+ #define ETH_MACA1HR_MBC_LBits31_24 0x08000000U /* Mask MAC Address low reg bits [31:24] */
+ #define ETH_MACA1HR_MBC_LBits23_16 0x04000000U /* Mask MAC Address low reg bits [23:16] */
+ #define ETH_MACA1HR_MBC_LBits15_8 0x02000000U /* Mask MAC Address low reg bits [15:8] */
+ #define ETH_MACA1HR_MBC_LBits7_0 0x01000000U /* Mask MAC Address low reg bits [7:0] */
+#define ETH_MACA1HR_MACA1H 0x0000FFFFU /* MAC address1 high */
+
+/* Bit definition for Ethernet MAC Address1 Low Register */
+#define ETH_MACA1LR_MACA1L 0xFFFFFFFFU /* MAC address1 low */
+
+/* Bit definition for Ethernet MAC Address2 High Register */
+#define ETH_MACA2HR_AE 0x80000000U /* Address enable */
+#define ETH_MACA2HR_SA 0x40000000U /* Source address */
+#define ETH_MACA2HR_MBC 0x3F000000U /* Mask byte control */
+ #define ETH_MACA2HR_MBC_HBits15_8 0x20000000U /* Mask MAC Address high reg bits [15:8] */
+ #define ETH_MACA2HR_MBC_HBits7_0 0x10000000U /* Mask MAC Address high reg bits [7:0] */
+ #define ETH_MACA2HR_MBC_LBits31_24 0x08000000U /* Mask MAC Address low reg bits [31:24] */
+ #define ETH_MACA2HR_MBC_LBits23_16 0x04000000U /* Mask MAC Address low reg bits [23:16] */
+ #define ETH_MACA2HR_MBC_LBits15_8 0x02000000U /* Mask MAC Address low reg bits [15:8] */
+ #define ETH_MACA2HR_MBC_LBits7_0 0x01000000U /* Mask MAC Address low reg bits [70] */
+#define ETH_MACA2HR_MACA2H 0x0000FFFFU /* MAC address1 high */
+
+/* Bit definition for Ethernet MAC Address2 Low Register */
+#define ETH_MACA2LR_MACA2L 0xFFFFFFFFU /* MAC address2 low */
+
+/* Bit definition for Ethernet MAC Address3 High Register */
+#define ETH_MACA3HR_AE 0x80000000U /* Address enable */
+#define ETH_MACA3HR_SA 0x40000000U /* Source address */
+#define ETH_MACA3HR_MBC 0x3F000000U /* Mask byte control */
+ #define ETH_MACA3HR_MBC_HBits15_8 0x20000000U /* Mask MAC Address high reg bits [15:8] */
+ #define ETH_MACA3HR_MBC_HBits7_0 0x10000000U /* Mask MAC Address high reg bits [7:0] */
+ #define ETH_MACA3HR_MBC_LBits31_24 0x08000000U /* Mask MAC Address low reg bits [31:24] */
+ #define ETH_MACA3HR_MBC_LBits23_16 0x04000000U /* Mask MAC Address low reg bits [23:16] */
+ #define ETH_MACA3HR_MBC_LBits15_8 0x02000000U /* Mask MAC Address low reg bits [15:8] */
+ #define ETH_MACA3HR_MBC_LBits7_0 0x01000000U /* Mask MAC Address low reg bits [70] */
+#define ETH_MACA3HR_MACA3H 0x0000FFFFU /* MAC address3 high */
+
+/* Bit definition for Ethernet MAC Address3 Low Register */
+#define ETH_MACA3LR_MACA3L 0xFFFFFFFFU /* MAC address3 low */
+
+/******************************************************************************/
+/* Ethernet MMC Registers bits definition */
+/******************************************************************************/
+
+/* Bit definition for Ethernet MMC Contol Register */
+#define ETH_MMCCR_MCFHP 0x00000020U /* MMC counter Full-Half preset */
+#define ETH_MMCCR_MCP 0x00000010U /* MMC counter preset */
+#define ETH_MMCCR_MCF 0x00000008U /* MMC Counter Freeze */
+#define ETH_MMCCR_ROR 0x00000004U /* Reset on Read */
+#define ETH_MMCCR_CSR 0x00000002U /* Counter Stop Rollover */
+#define ETH_MMCCR_CR 0x00000001U /* Counters Reset */
+
+/* Bit definition for Ethernet MMC Receive Interrupt Register */
+#define ETH_MMCRIR_RGUFS 0x00020000U /* Set when Rx good unicast frames counter reaches half the maximum value */
+#define ETH_MMCRIR_RFAES 0x00000040U /* Set when Rx alignment error counter reaches half the maximum value */
+#define ETH_MMCRIR_RFCES 0x00000020U /* Set when Rx crc error counter reaches half the maximum value */
+
+/* Bit definition for Ethernet MMC Transmit Interrupt Register */
+#define ETH_MMCTIR_TGFS 0x00200000U /* Set when Tx good frame count counter reaches half the maximum value */
+#define ETH_MMCTIR_TGFMSCS 0x00008000U /* Set when Tx good multi col counter reaches half the maximum value */
+#define ETH_MMCTIR_TGFSCS 0x00004000U /* Set when Tx good single col counter reaches half the maximum value */
+
+/* Bit definition for Ethernet MMC Receive Interrupt Mask Register */
+#define ETH_MMCRIMR_RGUFM 0x00020000U /* Mask the interrupt when Rx good unicast frames counter reaches half the maximum value */
+#define ETH_MMCRIMR_RFAEM 0x00000040U /* Mask the interrupt when when Rx alignment error counter reaches half the maximum value */
+#define ETH_MMCRIMR_RFCEM 0x00000020U /* Mask the interrupt when Rx crc error counter reaches half the maximum value */
+
+/* Bit definition for Ethernet MMC Transmit Interrupt Mask Register */
+#define ETH_MMCTIMR_TGFM 0x00200000U /* Mask the interrupt when Tx good frame count counter reaches half the maximum value */
+#define ETH_MMCTIMR_TGFMSCM 0x00008000U /* Mask the interrupt when Tx good multi col counter reaches half the maximum value */
+#define ETH_MMCTIMR_TGFSCM 0x00004000U /* Mask the interrupt when Tx good single col counter reaches half the maximum value */
+
+/* Bit definition for Ethernet MMC Transmitted Good Frames after Single Collision Counter Register */
+#define ETH_MMCTGFSCCR_TGFSCC 0xFFFFFFFFU /* Number of successfully transmitted frames after a single collision in Half-duplex mode. */
+
+/* Bit definition for Ethernet MMC Transmitted Good Frames after More than a Single Collision Counter Register */
+#define ETH_MMCTGFMSCCR_TGFMSCC 0xFFFFFFFFU /* Number of successfully transmitted frames after more than a single collision in Half-duplex mode. */
+
+/* Bit definition for Ethernet MMC Transmitted Good Frames Counter Register */
+#define ETH_MMCTGFCR_TGFC 0xFFFFFFFFU /* Number of good frames transmitted. */
+
+/* Bit definition for Ethernet MMC Received Frames with CRC Error Counter Register */
+#define ETH_MMCRFCECR_RFCEC 0xFFFFFFFFU /* Number of frames received with CRC error. */
+
+/* Bit definition for Ethernet MMC Received Frames with Alignement Error Counter Register */
+#define ETH_MMCRFAECR_RFAEC 0xFFFFFFFFU /* Number of frames received with alignment (dribble) error */
+
+/* Bit definition for Ethernet MMC Received Good Unicast Frames Counter Register */
+#define ETH_MMCRGUFCR_RGUFC 0xFFFFFFFFU /* Number of good unicast frames received. */
+
+/******************************************************************************/
+/* Ethernet PTP Registers bits definition */
+/******************************************************************************/
+
+/* Bit definition for Ethernet PTP Time Stamp Contol Register */
+#define ETH_PTPTSCR_TSCNT 0x00030000U /* Time stamp clock node type */
+#define ETH_PTPTSSR_TSSMRME 0x00008000U /* Time stamp snapshot for message relevant to master enable */
+#define ETH_PTPTSSR_TSSEME 0x00004000U /* Time stamp snapshot for event message enable */
+#define ETH_PTPTSSR_TSSIPV4FE 0x00002000U /* Time stamp snapshot for IPv4 frames enable */
+#define ETH_PTPTSSR_TSSIPV6FE 0x00001000U /* Time stamp snapshot for IPv6 frames enable */
+#define ETH_PTPTSSR_TSSPTPOEFE 0x00000800U /* Time stamp snapshot for PTP over ethernet frames enable */
+#define ETH_PTPTSSR_TSPTPPSV2E 0x00000400U /* Time stamp PTP packet snooping for version2 format enable */
+#define ETH_PTPTSSR_TSSSR 0x00000200U /* Time stamp Sub-seconds rollover */
+#define ETH_PTPTSSR_TSSARFE 0x00000100U /* Time stamp snapshot for all received frames enable */
+
+#define ETH_PTPTSCR_TSARU 0x00000020U /* Addend register update */
+#define ETH_PTPTSCR_TSITE 0x00000010U /* Time stamp interrupt trigger enable */
+#define ETH_PTPTSCR_TSSTU 0x00000008U /* Time stamp update */
+#define ETH_PTPTSCR_TSSTI 0x00000004U /* Time stamp initialize */
+#define ETH_PTPTSCR_TSFCU 0x00000002U /* Time stamp fine or coarse update */
+#define ETH_PTPTSCR_TSE 0x00000001U /* Time stamp enable */
+
+/* Bit definition for Ethernet PTP Sub-Second Increment Register */
+#define ETH_PTPSSIR_STSSI 0x000000FFU /* System time Sub-second increment value */
+
+/* Bit definition for Ethernet PTP Time Stamp High Register */
+#define ETH_PTPTSHR_STS 0xFFFFFFFFU /* System Time second */
+
+/* Bit definition for Ethernet PTP Time Stamp Low Register */
+#define ETH_PTPTSLR_STPNS 0x80000000U /* System Time Positive or negative time */
+#define ETH_PTPTSLR_STSS 0x7FFFFFFFU /* System Time sub-seconds */
+
+/* Bit definition for Ethernet PTP Time Stamp High Update Register */
+#define ETH_PTPTSHUR_TSUS 0xFFFFFFFFU /* Time stamp update seconds */
+
+/* Bit definition for Ethernet PTP Time Stamp Low Update Register */
+#define ETH_PTPTSLUR_TSUPNS 0x80000000U /* Time stamp update Positive or negative time */
+#define ETH_PTPTSLUR_TSUSS 0x7FFFFFFFU /* Time stamp update sub-seconds */
+
+/* Bit definition for Ethernet PTP Time Stamp Addend Register */
+#define ETH_PTPTSAR_TSA 0xFFFFFFFFU /* Time stamp addend */
+
+/* Bit definition for Ethernet PTP Target Time High Register */
+#define ETH_PTPTTHR_TTSH 0xFFFFFFFFU /* Target time stamp high */
+
+/* Bit definition for Ethernet PTP Target Time Low Register */
+#define ETH_PTPTTLR_TTSL 0xFFFFFFFFU /* Target time stamp low */
+
+/* Bit definition for Ethernet PTP Time Stamp Status Register */
+#define ETH_PTPTSSR_TSTTR 0x00000020U /* Time stamp target time reached */
+#define ETH_PTPTSSR_TSSO 0x00000010U /* Time stamp seconds overflow */
+
+/******************************************************************************/
+/* Ethernet DMA Registers bits definition */
+/******************************************************************************/
+
+/* Bit definition for Ethernet DMA Bus Mode Register */
+#define ETH_DMABMR_AAB 0x02000000U /* Address-Aligned beats */
+#define ETH_DMABMR_FPM 0x01000000U /* 4xPBL mode */
+#define ETH_DMABMR_USP 0x00800000U /* Use separate PBL */
+#define ETH_DMABMR_RDP 0x007E0000U /* RxDMA PBL */
+ #define ETH_DMABMR_RDP_1Beat 0x00020000U /* maximum number of beats to be transferred in one RxDMA transaction is 1 */
+ #define ETH_DMABMR_RDP_2Beat 0x00040000U /* maximum number of beats to be transferred in one RxDMA transaction is 2 */
+ #define ETH_DMABMR_RDP_4Beat 0x00080000U /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
+ #define ETH_DMABMR_RDP_8Beat 0x00100000U /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
+ #define ETH_DMABMR_RDP_16Beat 0x00200000U /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
+ #define ETH_DMABMR_RDP_32Beat 0x00400000U /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
+ #define ETH_DMABMR_RDP_4xPBL_4Beat 0x01020000U /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
+ #define ETH_DMABMR_RDP_4xPBL_8Beat 0x01040000U /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
+ #define ETH_DMABMR_RDP_4xPBL_16Beat 0x01080000U /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
+ #define ETH_DMABMR_RDP_4xPBL_32Beat 0x01100000U /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
+ #define ETH_DMABMR_RDP_4xPBL_64Beat 0x01200000U /* maximum number of beats to be transferred in one RxDMA transaction is 64 */
+ #define ETH_DMABMR_RDP_4xPBL_128Beat 0x01400000U /* maximum number of beats to be transferred in one RxDMA transaction is 128 */
+#define ETH_DMABMR_FB 0x00010000U /* Fixed Burst */
+#define ETH_DMABMR_RTPR 0x0000C000U /* Rx Tx priority ratio */
+ #define ETH_DMABMR_RTPR_1_1 0x00000000U /* Rx Tx priority ratio */
+ #define ETH_DMABMR_RTPR_2_1 0x00004000U /* Rx Tx priority ratio */
+ #define ETH_DMABMR_RTPR_3_1 0x00008000U /* Rx Tx priority ratio */
+ #define ETH_DMABMR_RTPR_4_1 0x0000C000U /* Rx Tx priority ratio */
+#define ETH_DMABMR_PBL 0x00003F00U /* Programmable burst length */
+ #define ETH_DMABMR_PBL_1Beat 0x00000100U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */
+ #define ETH_DMABMR_PBL_2Beat 0x00000200U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */
+ #define ETH_DMABMR_PBL_4Beat 0x00000400U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
+ #define ETH_DMABMR_PBL_8Beat 0x00000800U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
+ #define ETH_DMABMR_PBL_16Beat 0x00001000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
+ #define ETH_DMABMR_PBL_32Beat 0x00002000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
+ #define ETH_DMABMR_PBL_4xPBL_4Beat 0x01000100U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
+ #define ETH_DMABMR_PBL_4xPBL_8Beat 0x01000200U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
+ #define ETH_DMABMR_PBL_4xPBL_16Beat 0x01000400U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
+ #define ETH_DMABMR_PBL_4xPBL_32Beat 0x01000800U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
+ #define ETH_DMABMR_PBL_4xPBL_64Beat 0x01001000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */
+ #define ETH_DMABMR_PBL_4xPBL_128Beat 0x01002000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */
+#define ETH_DMABMR_EDE 0x00000080U /* Enhanced Descriptor Enable */
+#define ETH_DMABMR_DSL 0x0000007CU /* Descriptor Skip Length */
+#define ETH_DMABMR_DA 0x00000002U /* DMA arbitration scheme */
+#define ETH_DMABMR_SR 0x00000001U /* Software reset */
+
+/* Bit definition for Ethernet DMA Transmit Poll Demand Register */
+#define ETH_DMATPDR_TPD 0xFFFFFFFFU /* Transmit poll demand */
+
+/* Bit definition for Ethernet DMA Receive Poll Demand Register */
+#define ETH_DMARPDR_RPD 0xFFFFFFFFU /* Receive poll demand */
+
+/* Bit definition for Ethernet DMA Receive Descriptor List Address Register */
+#define ETH_DMARDLAR_SRL 0xFFFFFFFFU /* Start of receive list */
+
+/* Bit definition for Ethernet DMA Transmit Descriptor List Address Register */
+#define ETH_DMATDLAR_STL 0xFFFFFFFFU /* Start of transmit list */
+
+/* Bit definition for Ethernet DMA Status Register */
+#define ETH_DMASR_TSTS 0x20000000U /* Time-stamp trigger status */
+#define ETH_DMASR_PMTS 0x10000000U /* PMT status */
+#define ETH_DMASR_MMCS 0x08000000U /* MMC status */
+#define ETH_DMASR_EBS 0x03800000U /* Error bits status */
+ /* combination with EBS[2:0] for GetFlagStatus function */
+ #define ETH_DMASR_EBS_DescAccess 0x02000000U /* Error bits 0-data buffer, 1-desc. access */
+ #define ETH_DMASR_EBS_ReadTransf 0x01000000U /* Error bits 0-write trnsf, 1-read transfr */
+ #define ETH_DMASR_EBS_DataTransfTx 0x00800000U /* Error bits 0-Rx DMA, 1-Tx DMA */
+#define ETH_DMASR_TPS 0x00700000U /* Transmit process state */
+ #define ETH_DMASR_TPS_Stopped 0x00000000U /* Stopped - Reset or Stop Tx Command issued */
+ #define ETH_DMASR_TPS_Fetching 0x00100000U /* Running - fetching the Tx descriptor */
+ #define ETH_DMASR_TPS_Waiting 0x00200000U /* Running - waiting for status */
+ #define ETH_DMASR_TPS_Reading 0x00300000U /* Running - reading the data from host memory */
+ #define ETH_DMASR_TPS_Suspended 0x00600000U /* Suspended - Tx Descriptor unavailabe */
+ #define ETH_DMASR_TPS_Closing 0x00700000U /* Running - closing Rx descriptor */
+#define ETH_DMASR_RPS 0x000E0000U /* Receive process state */
+ #define ETH_DMASR_RPS_Stopped 0x00000000U /* Stopped - Reset or Stop Rx Command issued */
+ #define ETH_DMASR_RPS_Fetching 0x00020000U /* Running - fetching the Rx descriptor */
+ #define ETH_DMASR_RPS_Waiting 0x00060000U /* Running - waiting for packet */
+ #define ETH_DMASR_RPS_Suspended 0x00080000U /* Suspended - Rx Descriptor unavailable */
+ #define ETH_DMASR_RPS_Closing 0x000A0000U /* Running - closing descriptor */
+ #define ETH_DMASR_RPS_Queuing 0x000E0000U /* Running - queuing the recieve frame into host memory */
+#define ETH_DMASR_NIS 0x00010000U /* Normal interrupt summary */
+#define ETH_DMASR_AIS 0x00008000U /* Abnormal interrupt summary */
+#define ETH_DMASR_ERS 0x00004000U /* Early receive status */
+#define ETH_DMASR_FBES 0x00002000U /* Fatal bus error status */
+#define ETH_DMASR_ETS 0x00000400U /* Early transmit status */
+#define ETH_DMASR_RWTS 0x00000200U /* Receive watchdog timeout status */
+#define ETH_DMASR_RPSS 0x00000100U /* Receive process stopped status */
+#define ETH_DMASR_RBUS 0x00000080U /* Receive buffer unavailable status */
+#define ETH_DMASR_RS 0x00000040U /* Receive status */
+#define ETH_DMASR_TUS 0x00000020U /* Transmit underflow status */
+#define ETH_DMASR_ROS 0x00000010U /* Receive overflow status */
+#define ETH_DMASR_TJTS 0x00000008U /* Transmit jabber timeout status */
+#define ETH_DMASR_TBUS 0x00000004U /* Transmit buffer unavailable status */
+#define ETH_DMASR_TPSS 0x00000002U /* Transmit process stopped status */
+#define ETH_DMASR_TS 0x00000001U /* Transmit status */
+
+/* Bit definition for Ethernet DMA Operation Mode Register */
+#define ETH_DMAOMR_DTCEFD 0x04000000U /* Disable Dropping of TCP/IP checksum error frames */
+#define ETH_DMAOMR_RSF 0x02000000U /* Receive store and forward */
+#define ETH_DMAOMR_DFRF 0x01000000U /* Disable flushing of received frames */
+#define ETH_DMAOMR_TSF 0x00200000U /* Transmit store and forward */
+#define ETH_DMAOMR_FTF 0x00100000U /* Flush transmit FIFO */
+#define ETH_DMAOMR_TTC 0x0001C000U /* Transmit threshold control */
+ #define ETH_DMAOMR_TTC_64Bytes 0x00000000U /* threshold level of the MTL Transmit FIFO is 64 Bytes */
+ #define ETH_DMAOMR_TTC_128Bytes 0x00004000U /* threshold level of the MTL Transmit FIFO is 128 Bytes */
+ #define ETH_DMAOMR_TTC_192Bytes 0x00008000U /* threshold level of the MTL Transmit FIFO is 192 Bytes */
+ #define ETH_DMAOMR_TTC_256Bytes 0x0000C000U /* threshold level of the MTL Transmit FIFO is 256 Bytes */
+ #define ETH_DMAOMR_TTC_40Bytes 0x00010000U /* threshold level of the MTL Transmit FIFO is 40 Bytes */
+ #define ETH_DMAOMR_TTC_32Bytes 0x00014000U /* threshold level of the MTL Transmit FIFO is 32 Bytes */
+ #define ETH_DMAOMR_TTC_24Bytes 0x00018000U /* threshold level of the MTL Transmit FIFO is 24 Bytes */
+ #define ETH_DMAOMR_TTC_16Bytes 0x0001C000U /* threshold level of the MTL Transmit FIFO is 16 Bytes */
+#define ETH_DMAOMR_ST 0x00002000U /* Start/stop transmission command */
+#define ETH_DMAOMR_FEF 0x00000080U /* Forward error frames */
+#define ETH_DMAOMR_FUGF 0x00000040U /* Forward undersized good frames */
+#define ETH_DMAOMR_RTC 0x00000018U /* receive threshold control */
+ #define ETH_DMAOMR_RTC_64Bytes 0x00000000U /* threshold level of the MTL Receive FIFO is 64 Bytes */
+ #define ETH_DMAOMR_RTC_32Bytes 0x00000008U /* threshold level of the MTL Receive FIFO is 32 Bytes */
+ #define ETH_DMAOMR_RTC_96Bytes 0x00000010U /* threshold level of the MTL Receive FIFO is 96 Bytes */
+ #define ETH_DMAOMR_RTC_128Bytes 0x00000018U /* threshold level of the MTL Receive FIFO is 128 Bytes */
+#define ETH_DMAOMR_OSF 0x00000004U /* operate on second frame */
+#define ETH_DMAOMR_SR 0x00000002U /* Start/stop receive */
+
+/* Bit definition for Ethernet DMA Interrupt Enable Register */
+#define ETH_DMAIER_NISE 0x00010000U /* Normal interrupt summary enable */
+#define ETH_DMAIER_AISE 0x00008000U /* Abnormal interrupt summary enable */
+#define ETH_DMAIER_ERIE 0x00004000U /* Early receive interrupt enable */
+#define ETH_DMAIER_FBEIE 0x00002000U /* Fatal bus error interrupt enable */
+#define ETH_DMAIER_ETIE 0x00000400U /* Early transmit interrupt enable */
+#define ETH_DMAIER_RWTIE 0x00000200U /* Receive watchdog timeout interrupt enable */
+#define ETH_DMAIER_RPSIE 0x00000100U /* Receive process stopped interrupt enable */
+#define ETH_DMAIER_RBUIE 0x00000080U /* Receive buffer unavailable interrupt enable */
+#define ETH_DMAIER_RIE 0x00000040U /* Receive interrupt enable */
+#define ETH_DMAIER_TUIE 0x00000020U /* Transmit Underflow interrupt enable */
+#define ETH_DMAIER_ROIE 0x00000010U /* Receive Overflow interrupt enable */
+#define ETH_DMAIER_TJTIE 0x00000008U /* Transmit jabber timeout interrupt enable */
+#define ETH_DMAIER_TBUIE 0x00000004U /* Transmit buffer unavailable interrupt enable */
+#define ETH_DMAIER_TPSIE 0x00000002U /* Transmit process stopped interrupt enable */
+#define ETH_DMAIER_TIE 0x00000001U /* Transmit interrupt enable */
+
+/* Bit definition for Ethernet DMA Missed Frame and Buffer Overflow Counter Register */
+#define ETH_DMAMFBOCR_OFOC 0x10000000U /* Overflow bit for FIFO overflow counter */
+#define ETH_DMAMFBOCR_MFA 0x0FFE0000U /* Number of frames missed by the application */
+#define ETH_DMAMFBOCR_OMFC 0x00010000U /* Overflow bit for missed frame counter */
+#define ETH_DMAMFBOCR_MFC 0x0000FFFFU /* Number of frames missed by the controller */
+
+/* Bit definition for Ethernet DMA Current Host Transmit Descriptor Register */
+#define ETH_DMACHTDR_HTDAP 0xFFFFFFFFU /* Host transmit descriptor address pointer */
+
+/* Bit definition for Ethernet DMA Current Host Receive Descriptor Register */
+#define ETH_DMACHRDR_HRDAP 0xFFFFFFFFU /* Host receive descriptor address pointer */
+
+/* Bit definition for Ethernet DMA Current Host Transmit Buffer Address Register */
+#define ETH_DMACHTBAR_HTBAP 0xFFFFFFFFU /* Host transmit buffer address pointer */
+
+/* Bit definition for Ethernet DMA Current Host Receive Buffer Address Register */
+#define ETH_DMACHRBAR_HRBAP 0xFFFFFFFFU /* Host receive buffer address pointer */
+
+/******************************************************************************/
+/* */
+/* USB_OTG */
+/* */
+/******************************************************************************/
+/******************** Bit definition forUSB_OTG_GOTGCTL register ********************/
+#define USB_OTG_GOTGCTL_SRQSCS 0x00000001U /*!< Session request success */
+#define USB_OTG_GOTGCTL_SRQ 0x00000002U /*!< Session request */
+#define USB_OTG_GOTGCTL_HNGSCS 0x00000100U /*!< Host negotiation success */
+#define USB_OTG_GOTGCTL_HNPRQ 0x00000200U /*!< HNP request */
+#define USB_OTG_GOTGCTL_HSHNPEN 0x00000400U /*!< Host set HNP enable */
+#define USB_OTG_GOTGCTL_DHNPEN 0x00000800U /*!< Device HNP enabled */
+#define USB_OTG_GOTGCTL_CIDSTS 0x00010000U /*!< Connector ID status */
+#define USB_OTG_GOTGCTL_DBCT 0x00020000U /*!< Long/short debounce time */
+#define USB_OTG_GOTGCTL_ASVLD 0x00040000U /*!< A-session valid */
+#define USB_OTG_GOTGCTL_BSVLD 0x00080000U /*!< B-session valid */
+
+/******************** Bit definition forUSB_OTG_HCFG register ********************/
+
+#define USB_OTG_HCFG_FSLSPCS 0x00000003U /*!< FS/LS PHY clock select */
+#define USB_OTG_HCFG_FSLSPCS_0 0x00000001U /*!<Bit 0 */
+#define USB_OTG_HCFG_FSLSPCS_1 0x00000002U /*!<Bit 1 */
+#define USB_OTG_HCFG_FSLSS 0x00000004U /*!< FS- and LS-only support */
+
+/******************** Bit definition forUSB_OTG_DCFG register ********************/
+
+#define USB_OTG_DCFG_DSPD 0x00000003U /*!< Device speed */
+#define USB_OTG_DCFG_DSPD_0 0x00000001U /*!<Bit 0 */
+#define USB_OTG_DCFG_DSPD_1 0x00000002U /*!<Bit 1 */
+#define USB_OTG_DCFG_NZLSOHSK 0x00000004U /*!< Nonzero-length status OUT handshake */
+
+#define USB_OTG_DCFG_DAD 0x000007F0U /*!< Device address */
+#define USB_OTG_DCFG_DAD_0 0x00000010U /*!<Bit 0 */
+#define USB_OTG_DCFG_DAD_1 0x00000020U /*!<Bit 1 */
+#define USB_OTG_DCFG_DAD_2 0x00000040U /*!<Bit 2 */
+#define USB_OTG_DCFG_DAD_3 0x00000080U /*!<Bit 3 */
+#define USB_OTG_DCFG_DAD_4 0x00000100U /*!<Bit 4 */
+#define USB_OTG_DCFG_DAD_5 0x00000200U /*!<Bit 5 */
+#define USB_OTG_DCFG_DAD_6 0x00000400U /*!<Bit 6 */
+
+#define USB_OTG_DCFG_PFIVL 0x00001800U /*!< Periodic (micro)frame interval */
+#define USB_OTG_DCFG_PFIVL_0 0x00000800U /*!<Bit 0 */
+#define USB_OTG_DCFG_PFIVL_1 0x00001000U /*!<Bit 1 */
+
+#define USB_OTG_DCFG_PERSCHIVL 0x03000000U /*!< Periodic scheduling interval */
+#define USB_OTG_DCFG_PERSCHIVL_0 0x01000000U /*!<Bit 0 */
+#define USB_OTG_DCFG_PERSCHIVL_1 0x02000000U /*!<Bit 1 */
+
+/******************** Bit definition forUSB_OTG_PCGCR register ********************/
+#define USB_OTG_PCGCR_STPPCLK 0x00000001U /*!< Stop PHY clock */
+#define USB_OTG_PCGCR_GATEHCLK 0x00000002U /*!< Gate HCLK */
+#define USB_OTG_PCGCR_PHYSUSP 0x00000010U /*!< PHY suspended */
+
+/******************** Bit definition forUSB_OTG_GOTGINT register ********************/
+#define USB_OTG_GOTGINT_SEDET 0x00000004U /*!< Session end detected */
+#define USB_OTG_GOTGINT_SRSSCHG 0x00000100U /*!< Session request success status change */
+#define USB_OTG_GOTGINT_HNSSCHG 0x00000200U /*!< Host negotiation success status change */
+#define USB_OTG_GOTGINT_HNGDET 0x00020000U /*!< Host negotiation detected */
+#define USB_OTG_GOTGINT_ADTOCHG 0x00040000U /*!< A-device timeout change */
+#define USB_OTG_GOTGINT_DBCDNE 0x00080000U /*!< Debounce done */
+
+/******************** Bit definition forUSB_OTG_DCTL register ********************/
+#define USB_OTG_DCTL_RWUSIG 0x00000001U /*!< Remote wakeup signaling */
+#define USB_OTG_DCTL_SDIS 0x00000002U /*!< Soft disconnect */
+#define USB_OTG_DCTL_GINSTS 0x00000004U /*!< Global IN NAK status */
+#define USB_OTG_DCTL_GONSTS 0x00000008U /*!< Global OUT NAK status */
+
+#define USB_OTG_DCTL_TCTL 0x00000070U /*!< Test control */
+#define USB_OTG_DCTL_TCTL_0 0x00000010U /*!<Bit 0 */
+#define USB_OTG_DCTL_TCTL_1 0x00000020U /*!<Bit 1 */
+#define USB_OTG_DCTL_TCTL_2 0x00000040U /*!<Bit 2 */
+#define USB_OTG_DCTL_SGINAK 0x00000080U /*!< Set global IN NAK */
+#define USB_OTG_DCTL_CGINAK 0x00000100U /*!< Clear global IN NAK */
+#define USB_OTG_DCTL_SGONAK 0x00000200U /*!< Set global OUT NAK */
+#define USB_OTG_DCTL_CGONAK 0x00000400U /*!< Clear global OUT NAK */
+#define USB_OTG_DCTL_POPRGDNE 0x00000800U /*!< Power-on programming done */
+
+/******************** Bit definition forUSB_OTG_HFIR register ********************/
+#define USB_OTG_HFIR_FRIVL 0x0000FFFFU /*!< Frame interval */
+
+/******************** Bit definition forUSB_OTG_HFNUM register ********************/
+#define USB_OTG_HFNUM_FRNUM 0x0000FFFFU /*!< Frame number */
+#define USB_OTG_HFNUM_FTREM 0xFFFF0000U /*!< Frame time remaining */
+
+/******************** Bit definition forUSB_OTG_DSTS register ********************/
+#define USB_OTG_DSTS_SUSPSTS 0x00000001U /*!< Suspend status */
+
+#define USB_OTG_DSTS_ENUMSPD 0x00000006U /*!< Enumerated speed */
+#define USB_OTG_DSTS_ENUMSPD_0 0x00000002U /*!<Bit 0 */
+#define USB_OTG_DSTS_ENUMSPD_1 0x00000004U /*!<Bit 1 */
+#define USB_OTG_DSTS_EERR 0x00000008U /*!< Erratic error */
+#define USB_OTG_DSTS_FNSOF 0x003FFF00U /*!< Frame number of the received SOF */
+
+/******************** Bit definition forUSB_OTG_GAHBCFG register ********************/
+#define USB_OTG_GAHBCFG_GINT 0x00000001U /*!< Global interrupt mask */
+
+#define USB_OTG_GAHBCFG_HBSTLEN 0x0000001EU /*!< Burst length/type */
+#define USB_OTG_GAHBCFG_HBSTLEN_0 0x00000002U /*!<Bit 0 */
+#define USB_OTG_GAHBCFG_HBSTLEN_1 0x00000004U /*!<Bit 1 */
+#define USB_OTG_GAHBCFG_HBSTLEN_2 0x00000008U /*!<Bit 2 */
+#define USB_OTG_GAHBCFG_HBSTLEN_3 0x00000010U /*!<Bit 3 */
+#define USB_OTG_GAHBCFG_DMAEN 0x00000020U /*!< DMA enable */
+#define USB_OTG_GAHBCFG_TXFELVL 0x00000080U /*!< TxFIFO empty level */
+#define USB_OTG_GAHBCFG_PTXFELVL 0x00000100U /*!< Periodic TxFIFO empty level */
+
+/******************** Bit definition forUSB_OTG_GUSBCFG register ********************/
+
+#define USB_OTG_GUSBCFG_TOCAL 0x00000007U /*!< FS timeout calibration */
+#define USB_OTG_GUSBCFG_TOCAL_0 0x00000001U /*!<Bit 0 */
+#define USB_OTG_GUSBCFG_TOCAL_1 0x00000002U /*!<Bit 1 */
+#define USB_OTG_GUSBCFG_TOCAL_2 0x00000004U /*!<Bit 2 */
+#define USB_OTG_GUSBCFG_PHYSEL 0x00000040U /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */
+#define USB_OTG_GUSBCFG_SRPCAP 0x00000100U /*!< SRP-capable */
+#define USB_OTG_GUSBCFG_HNPCAP 0x00000200U /*!< HNP-capable */
+
+#define USB_OTG_GUSBCFG_TRDT 0x00003C00U /*!< USB turnaround time */
+#define USB_OTG_GUSBCFG_TRDT_0 0x00000400U /*!<Bit 0 */
+#define USB_OTG_GUSBCFG_TRDT_1 0x00000800U /*!<Bit 1 */
+#define USB_OTG_GUSBCFG_TRDT_2 0x00001000U /*!<Bit 2 */
+#define USB_OTG_GUSBCFG_TRDT_3 0x00002000U /*!<Bit 3 */
+#define USB_OTG_GUSBCFG_PHYLPCS 0x00008000U /*!< PHY Low-power clock select */
+#define USB_OTG_GUSBCFG_ULPIFSLS 0x00020000U /*!< ULPI FS/LS select */
+#define USB_OTG_GUSBCFG_ULPIAR 0x00040000U /*!< ULPI Auto-resume */
+#define USB_OTG_GUSBCFG_ULPICSM 0x00080000U /*!< ULPI Clock SuspendM */
+#define USB_OTG_GUSBCFG_ULPIEVBUSD 0x00100000U /*!< ULPI External VBUS Drive */
+#define USB_OTG_GUSBCFG_ULPIEVBUSI 0x00200000U /*!< ULPI external VBUS indicator */
+#define USB_OTG_GUSBCFG_TSDPS 0x00400000U /*!< TermSel DLine pulsing selection */
+#define USB_OTG_GUSBCFG_PCCI 0x00800000U /*!< Indicator complement */
+#define USB_OTG_GUSBCFG_PTCI 0x01000000U /*!< Indicator pass through */
+#define USB_OTG_GUSBCFG_ULPIIPD 0x02000000U /*!< ULPI interface protect disable */
+#define USB_OTG_GUSBCFG_FHMOD 0x20000000U /*!< Forced host mode */
+#define USB_OTG_GUSBCFG_FDMOD 0x40000000U /*!< Forced peripheral mode */
+#define USB_OTG_GUSBCFG_CTXPKT 0x80000000U /*!< Corrupt Tx packet */
+
+/******************** Bit definition forUSB_OTG_GRSTCTL register ********************/
+#define USB_OTG_GRSTCTL_CSRST 0x00000001U /*!< Core soft reset */
+#define USB_OTG_GRSTCTL_HSRST 0x00000002U /*!< HCLK soft reset */
+#define USB_OTG_GRSTCTL_FCRST 0x00000004U /*!< Host frame counter reset */
+#define USB_OTG_GRSTCTL_RXFFLSH 0x00000010U /*!< RxFIFO flush */
+#define USB_OTG_GRSTCTL_TXFFLSH 0x00000020U /*!< TxFIFO flush */
+
+#define USB_OTG_GRSTCTL_TXFNUM 0x000007C0U /*!< TxFIFO number */
+#define USB_OTG_GRSTCTL_TXFNUM_0 0x00000040U /*!<Bit 0 */
+#define USB_OTG_GRSTCTL_TXFNUM_1 0x00000080U /*!<Bit 1 */
+#define USB_OTG_GRSTCTL_TXFNUM_2 0x00000100U /*!<Bit 2 */
+#define USB_OTG_GRSTCTL_TXFNUM_3 0x00000200U /*!<Bit 3 */
+#define USB_OTG_GRSTCTL_TXFNUM_4 0x00000400U /*!<Bit 4 */
+#define USB_OTG_GRSTCTL_DMAREQ 0x40000000U /*!< DMA request signal */
+#define USB_OTG_GRSTCTL_AHBIDL 0x80000000U /*!< AHB master idle */
+
+/******************** Bit definition forUSB_OTG_DIEPMSK register ********************/
+#define USB_OTG_DIEPMSK_XFRCM 0x00000001U /*!< Transfer completed interrupt mask */
+#define USB_OTG_DIEPMSK_EPDM 0x00000002U /*!< Endpoint disabled interrupt mask */
+#define USB_OTG_DIEPMSK_TOM 0x00000008U /*!< Timeout condition mask (nonisochronous endpoints) */
+#define USB_OTG_DIEPMSK_ITTXFEMSK 0x00000010U /*!< IN token received when TxFIFO empty mask */
+#define USB_OTG_DIEPMSK_INEPNMM 0x00000020U /*!< IN token received with EP mismatch mask */
+#define USB_OTG_DIEPMSK_INEPNEM 0x00000040U /*!< IN endpoint NAK effective mask */
+#define USB_OTG_DIEPMSK_TXFURM 0x00000100U /*!< FIFO underrun mask */
+#define USB_OTG_DIEPMSK_BIM 0x00000200U /*!< BNA interrupt mask */
+
+/******************** Bit definition forUSB_OTG_HPTXSTS register ********************/
+#define USB_OTG_HPTXSTS_PTXFSAVL 0x0000FFFFU /*!< Periodic transmit data FIFO space available */
+
+#define USB_OTG_HPTXSTS_PTXQSAV 0x00FF0000U /*!< Periodic transmit request queue space available */
+#define USB_OTG_HPTXSTS_PTXQSAV_0 0x00010000U /*!<Bit 0 */
+#define USB_OTG_HPTXSTS_PTXQSAV_1 0x00020000U /*!<Bit 1 */
+#define USB_OTG_HPTXSTS_PTXQSAV_2 0x00040000U /*!<Bit 2 */
+#define USB_OTG_HPTXSTS_PTXQSAV_3 0x00080000U /*!<Bit 3 */
+#define USB_OTG_HPTXSTS_PTXQSAV_4 0x00100000U /*!<Bit 4 */
+#define USB_OTG_HPTXSTS_PTXQSAV_5 0x00200000U /*!<Bit 5 */
+#define USB_OTG_HPTXSTS_PTXQSAV_6 0x00400000U /*!<Bit 6 */
+#define USB_OTG_HPTXSTS_PTXQSAV_7 0x00800000U /*!<Bit 7 */
+
+#define USB_OTG_HPTXSTS_PTXQTOP 0xFF000000U /*!< Top of the periodic transmit request queue */
+#define USB_OTG_HPTXSTS_PTXQTOP_0 0x01000000U /*!<Bit 0 */
+#define USB_OTG_HPTXSTS_PTXQTOP_1 0x02000000U /*!<Bit 1 */
+#define USB_OTG_HPTXSTS_PTXQTOP_2 0x04000000U /*!<Bit 2 */
+#define USB_OTG_HPTXSTS_PTXQTOP_3 0x08000000U /*!<Bit 3 */
+#define USB_OTG_HPTXSTS_PTXQTOP_4 0x10000000U /*!<Bit 4 */
+#define USB_OTG_HPTXSTS_PTXQTOP_5 0x20000000U /*!<Bit 5 */
+#define USB_OTG_HPTXSTS_PTXQTOP_6 0x40000000U /*!<Bit 6 */
+#define USB_OTG_HPTXSTS_PTXQTOP_7 0x80000000U /*!<Bit 7 */
+
+/******************** Bit definition forUSB_OTG_HAINT register ********************/
+#define USB_OTG_HAINT_HAINT 0x0000FFFFU /*!< Channel interrupts */
+
+/******************** Bit definition forUSB_OTG_DOEPMSK register ********************/
+#define USB_OTG_DOEPMSK_XFRCM 0x00000001U /*!< Transfer completed interrupt mask */
+#define USB_OTG_DOEPMSK_EPDM 0x00000002U /*!< Endpoint disabled interrupt mask */
+#define USB_OTG_DOEPMSK_STUPM 0x00000008U /*!< SETUP phase done mask */
+#define USB_OTG_DOEPMSK_OTEPDM 0x00000010U /*!< OUT token received when endpoint disabled mask */
+#define USB_OTG_DOEPMSK_B2BSTUP 0x00000040U /*!< Back-to-back SETUP packets received mask */
+#define USB_OTG_DOEPMSK_OPEM 0x00000100U /*!< OUT packet error mask */
+#define USB_OTG_DOEPMSK_BOIM 0x00000200U /*!< BNA interrupt mask */
+
+/******************** Bit definition forUSB_OTG_GINTSTS register ********************/
+#define USB_OTG_GINTSTS_CMOD 0x00000001U /*!< Current mode of operation */
+#define USB_OTG_GINTSTS_MMIS 0x00000002U /*!< Mode mismatch interrupt */
+#define USB_OTG_GINTSTS_OTGINT 0x00000004U /*!< OTG interrupt */
+#define USB_OTG_GINTSTS_SOF 0x00000008U /*!< Start of frame */
+#define USB_OTG_GINTSTS_RXFLVL 0x00000010U /*!< RxFIFO nonempty */
+#define USB_OTG_GINTSTS_NPTXFE 0x00000020U /*!< Nonperiodic TxFIFO empty */
+#define USB_OTG_GINTSTS_GINAKEFF 0x00000040U /*!< Global IN nonperiodic NAK effective */
+#define USB_OTG_GINTSTS_BOUTNAKEFF 0x00000080U /*!< Global OUT NAK effective */
+#define USB_OTG_GINTSTS_ESUSP 0x00000400U /*!< Early suspend */
+#define USB_OTG_GINTSTS_USBSUSP 0x00000800U /*!< USB suspend */
+#define USB_OTG_GINTSTS_USBRST 0x00001000U /*!< USB reset */
+#define USB_OTG_GINTSTS_ENUMDNE 0x00002000U /*!< Enumeration done */
+#define USB_OTG_GINTSTS_ISOODRP 0x00004000U /*!< Isochronous OUT packet dropped interrupt */
+#define USB_OTG_GINTSTS_EOPF 0x00008000U /*!< End of periodic frame interrupt */
+#define USB_OTG_GINTSTS_IEPINT 0x00040000U /*!< IN endpoint interrupt */
+#define USB_OTG_GINTSTS_OEPINT 0x00080000U /*!< OUT endpoint interrupt */
+#define USB_OTG_GINTSTS_IISOIXFR 0x00100000U /*!< Incomplete isochronous IN transfer */
+#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT 0x00200000U /*!< Incomplete periodic transfer */
+#define USB_OTG_GINTSTS_DATAFSUSP 0x00400000U /*!< Data fetch suspended */
+#define USB_OTG_GINTSTS_HPRTINT 0x01000000U /*!< Host port interrupt */
+#define USB_OTG_GINTSTS_HCINT 0x02000000U /*!< Host channels interrupt */
+#define USB_OTG_GINTSTS_PTXFE 0x04000000U /*!< Periodic TxFIFO empty */
+#define USB_OTG_GINTSTS_CIDSCHG 0x10000000U /*!< Connector ID status change */
+#define USB_OTG_GINTSTS_DISCINT 0x20000000U /*!< Disconnect detected interrupt */
+#define USB_OTG_GINTSTS_SRQINT 0x40000000U /*!< Session request/new session detected interrupt */
+#define USB_OTG_GINTSTS_WKUINT 0x80000000U /*!< Resume/remote wakeup detected interrupt */
+
+/******************** Bit definition forUSB_OTG_GINTMSK register ********************/
+#define USB_OTG_GINTMSK_MMISM 0x00000002U /*!< Mode mismatch interrupt mask */
+#define USB_OTG_GINTMSK_OTGINT 0x00000004U /*!< OTG interrupt mask */
+#define USB_OTG_GINTMSK_SOFM 0x00000008U /*!< Start of frame mask */
+#define USB_OTG_GINTMSK_RXFLVLM 0x00000010U /*!< Receive FIFO nonempty mask */
+#define USB_OTG_GINTMSK_NPTXFEM 0x00000020U /*!< Nonperiodic TxFIFO empty mask */
+#define USB_OTG_GINTMSK_GINAKEFFM 0x00000040U /*!< Global nonperiodic IN NAK effective mask */
+#define USB_OTG_GINTMSK_GONAKEFFM 0x00000080U /*!< Global OUT NAK effective mask */
+#define USB_OTG_GINTMSK_ESUSPM 0x00000400U /*!< Early suspend mask */
+#define USB_OTG_GINTMSK_USBSUSPM 0x00000800U /*!< USB suspend mask */
+#define USB_OTG_GINTMSK_USBRST 0x00001000U /*!< USB reset mask */
+#define USB_OTG_GINTMSK_ENUMDNEM 0x00002000U /*!< Enumeration done mask */
+#define USB_OTG_GINTMSK_ISOODRPM 0x00004000U /*!< Isochronous OUT packet dropped interrupt mask */
+#define USB_OTG_GINTMSK_EOPFM 0x00008000U /*!< End of periodic frame interrupt mask */
+#define USB_OTG_GINTMSK_EPMISM 0x00020000U /*!< Endpoint mismatch interrupt mask */
+#define USB_OTG_GINTMSK_IEPINT 0x00040000U /*!< IN endpoints interrupt mask */
+#define USB_OTG_GINTMSK_OEPINT 0x00080000U /*!< OUT endpoints interrupt mask */
+#define USB_OTG_GINTMSK_IISOIXFRM 0x00100000U /*!< Incomplete isochronous IN transfer mask */
+#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM 0x00200000U /*!< Incomplete periodic transfer mask */
+#define USB_OTG_GINTMSK_FSUSPM 0x00400000U /*!< Data fetch suspended mask */
+#define USB_OTG_GINTMSK_PRTIM 0x01000000U /*!< Host port interrupt mask */
+#define USB_OTG_GINTMSK_HCIM 0x02000000U /*!< Host channels interrupt mask */
+#define USB_OTG_GINTMSK_PTXFEM 0x04000000U /*!< Periodic TxFIFO empty mask */
+#define USB_OTG_GINTMSK_CIDSCHGM 0x10000000U /*!< Connector ID status change mask */
+#define USB_OTG_GINTMSK_DISCINT 0x20000000U /*!< Disconnect detected interrupt mask */
+#define USB_OTG_GINTMSK_SRQIM 0x40000000U /*!< Session request/new session detected interrupt mask */
+#define USB_OTG_GINTMSK_WUIM 0x80000000U /*!< Resume/remote wakeup detected interrupt mask */
+
+/******************** Bit definition forUSB_OTG_DAINT register ********************/
+#define USB_OTG_DAINT_IEPINT 0x0000FFFFU /*!< IN endpoint interrupt bits */
+#define USB_OTG_DAINT_OEPINT 0xFFFF0000U /*!< OUT endpoint interrupt bits */
+
+/******************** Bit definition forUSB_OTG_HAINTMSK register ********************/
+#define USB_OTG_HAINTMSK_HAINTM 0x0000FFFFU /*!< Channel interrupt mask */
+
+/******************** Bit definition for USB_OTG_GRXSTSP register ********************/
+#define USB_OTG_GRXSTSP_EPNUM 0x0000000FU /*!< IN EP interrupt mask bits */
+#define USB_OTG_GRXSTSP_BCNT 0x00007FF0U /*!< OUT EP interrupt mask bits */
+#define USB_OTG_GRXSTSP_DPID 0x00018000U /*!< OUT EP interrupt mask bits */
+#define USB_OTG_GRXSTSP_PKTSTS 0x001E0000U /*!< OUT EP interrupt mask bits */
+
+/******************** Bit definition forUSB_OTG_DAINTMSK register ********************/
+#define USB_OTG_DAINTMSK_IEPM 0x0000FFFFU /*!< IN EP interrupt mask bits */
+#define USB_OTG_DAINTMSK_OEPM 0xFFFF0000U /*!< OUT EP interrupt mask bits */
+
+/******************** Bit definition for OTG register ********************/
+
+#define USB_OTG_CHNUM 0x0000000FU /*!< Channel number */
+#define USB_OTG_CHNUM_0 0x00000001U /*!<Bit 0 */
+#define USB_OTG_CHNUM_1 0x00000002U /*!<Bit 1 */
+#define USB_OTG_CHNUM_2 0x00000004U /*!<Bit 2 */
+#define USB_OTG_CHNUM_3 0x00000008U /*!<Bit 3 */
+#define USB_OTG_BCNT 0x00007FF0U /*!< Byte count */
+
+#define USB_OTG_DPID 0x00018000U /*!< Data PID */
+#define USB_OTG_DPID_0 0x00008000U /*!<Bit 0 */
+#define USB_OTG_DPID_1 0x00010000U /*!<Bit 1 */
+
+#define USB_OTG_PKTSTS 0x001E0000U /*!< Packet status */
+#define USB_OTG_PKTSTS_0 0x00020000U /*!<Bit 0 */
+#define USB_OTG_PKTSTS_1 0x00040000U /*!<Bit 1 */
+#define USB_OTG_PKTSTS_2 0x00080000U /*!<Bit 2 */
+#define USB_OTG_PKTSTS_3 0x00100000U /*!<Bit 3 */
+
+#define USB_OTG_EPNUM 0x0000000FU /*!< Endpoint number */
+#define USB_OTG_EPNUM_0 0x00000001U /*!<Bit 0 */
+#define USB_OTG_EPNUM_1 0x00000002U /*!<Bit 1 */
+#define USB_OTG_EPNUM_2 0x00000004U /*!<Bit 2 */
+#define USB_OTG_EPNUM_3 0x00000008U /*!<Bit 3 */
+
+#define USB_OTG_FRMNUM 0x01E00000U /*!< Frame number */
+#define USB_OTG_FRMNUM_0 0x00200000U /*!<Bit 0 */
+#define USB_OTG_FRMNUM_1 0x00400000U /*!<Bit 1 */
+#define USB_OTG_FRMNUM_2 0x00800000U /*!<Bit 2 */
+#define USB_OTG_FRMNUM_3 0x01000000U /*!<Bit 3 */
+
+/******************** Bit definition for OTG register ********************/
+
+#define USB_OTG_CHNUM 0x0000000FU /*!< Channel number */
+#define USB_OTG_CHNUM_0 0x00000001U /*!<Bit 0 */
+#define USB_OTG_CHNUM_1 0x00000002U /*!<Bit 1 */
+#define USB_OTG_CHNUM_2 0x00000004U /*!<Bit 2 */
+#define USB_OTG_CHNUM_3 0x00000008U /*!<Bit 3 */
+#define USB_OTG_BCNT 0x00007FF0U /*!< Byte count */
+
+#define USB_OTG_DPID 0x00018000U /*!< Data PID */
+#define USB_OTG_DPID_0 0x00008000U /*!<Bit 0 */
+#define USB_OTG_DPID_1 0x00010000U /*!<Bit 1 */
+
+#define USB_OTG_PKTSTS 0x001E0000U /*!< Packet status */
+#define USB_OTG_PKTSTS_0 0x00020000U /*!<Bit 0 */
+#define USB_OTG_PKTSTS_1 0x00040000U /*!<Bit 1 */
+#define USB_OTG_PKTSTS_2 0x00080000U /*!<Bit 2 */
+#define USB_OTG_PKTSTS_3 0x00100000U /*!<Bit 3 */
+
+#define USB_OTG_EPNUM 0x0000000FU /*!< Endpoint number */
+#define USB_OTG_EPNUM_0 0x00000001U /*!<Bit 0 */
+#define USB_OTG_EPNUM_1 0x00000002U /*!<Bit 1 */
+#define USB_OTG_EPNUM_2 0x00000004U /*!<Bit 2 */
+#define USB_OTG_EPNUM_3 0x00000008U /*!<Bit 3 */
+
+#define USB_OTG_FRMNUM 0x01E00000U /*!< Frame number */
+#define USB_OTG_FRMNUM_0 0x00200000U /*!<Bit 0 */
+#define USB_OTG_FRMNUM_1 0x00400000U /*!<Bit 1 */
+#define USB_OTG_FRMNUM_2 0x00800000U /*!<Bit 2 */
+#define USB_OTG_FRMNUM_3 0x01000000U /*!<Bit 3 */
+
+/******************** Bit definition forUSB_OTG_GRXFSIZ register ********************/
+#define USB_OTG_GRXFSIZ_RXFD 0x0000FFFFU /*!< RxFIFO depth */
+
+/******************** Bit definition forUSB_OTG_DVBUSDIS register ********************/
+#define USB_OTG_DVBUSDIS_VBUSDT 0x0000FFFFU /*!< Device VBUS discharge time */
+
+/******************** Bit definition for OTG register ********************/
+#define USB_OTG_NPTXFSA 0x0000FFFFU /*!< Nonperiodic transmit RAM start address */
+#define USB_OTG_NPTXFD 0xFFFF0000U /*!< Nonperiodic TxFIFO depth */
+#define USB_OTG_TX0FSA 0x0000FFFFU /*!< Endpoint 0 transmit RAM start address */
+#define USB_OTG_TX0FD 0xFFFF0000U /*!< Endpoint 0 TxFIFO depth */
+
+/******************** Bit definition forUSB_OTG_DVBUSPULSE register ********************/
+#define USB_OTG_DVBUSPULSE_DVBUSP 0x00000FFFU /*!< Device VBUS pulsing time */
+
+/******************** Bit definition forUSB_OTG_GNPTXSTS register ********************/
+#define USB_OTG_GNPTXSTS_NPTXFSAV 0x0000FFFFU /*!< Nonperiodic TxFIFO space available */
+
+#define USB_OTG_GNPTXSTS_NPTQXSAV 0x00FF0000U /*!< Nonperiodic transmit request queue space available */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_0 0x00010000U /*!<Bit 0 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_1 0x00020000U /*!<Bit 1 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_2 0x00040000U /*!<Bit 2 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_3 0x00080000U /*!<Bit 3 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_4 0x00100000U /*!<Bit 4 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_5 0x00200000U /*!<Bit 5 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_6 0x00400000U /*!<Bit 6 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_7 0x00800000U /*!<Bit 7 */
+
+#define USB_OTG_GNPTXSTS_NPTXQTOP 0x7F000000U /*!< Top of the nonperiodic transmit request queue */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_0 0x01000000U /*!<Bit 0 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_1 0x02000000U /*!<Bit 1 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_2 0x04000000U /*!<Bit 2 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_3 0x08000000U /*!<Bit 3 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_4 0x10000000U /*!<Bit 4 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_5 0x20000000U /*!<Bit 5 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_6 0x40000000U /*!<Bit 6 */
+
+/******************** Bit definition forUSB_OTG_DTHRCTL register ********************/
+#define USB_OTG_DTHRCTL_NONISOTHREN 0x00000001U /*!< Nonisochronous IN endpoints threshold enable */
+#define USB_OTG_DTHRCTL_ISOTHREN 0x00000002U /*!< ISO IN endpoint threshold enable */
+
+#define USB_OTG_DTHRCTL_TXTHRLEN 0x000007FCU /*!< Transmit threshold length */
+#define USB_OTG_DTHRCTL_TXTHRLEN_0 0x00000004U /*!<Bit 0 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_1 0x00000008U /*!<Bit 1 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_2 0x00000010U /*!<Bit 2 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_3 0x00000020U /*!<Bit 3 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_4 0x00000040U /*!<Bit 4 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_5 0x00000080U /*!<Bit 5 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_6 0x00000100U /*!<Bit 6 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_7 0x00000200U /*!<Bit 7 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_8 0x00000400U /*!<Bit 8 */
+#define USB_OTG_DTHRCTL_RXTHREN 0x00010000U /*!< Receive threshold enable */
+
+#define USB_OTG_DTHRCTL_RXTHRLEN 0x03FE0000U /*!< Receive threshold length */
+#define USB_OTG_DTHRCTL_RXTHRLEN_0 0x00020000U /*!<Bit 0 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_1 0x00040000U /*!<Bit 1 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_2 0x00080000U /*!<Bit 2 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_3 0x00100000U /*!<Bit 3 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_4 0x00200000U /*!<Bit 4 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_5 0x00400000U /*!<Bit 5 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_6 0x00800000U /*!<Bit 6 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_7 0x01000000U /*!<Bit 7 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_8 0x02000000U /*!<Bit 8 */
+#define USB_OTG_DTHRCTL_ARPEN 0x08000000U /*!< Arbiter parking enable */
+
+/******************** Bit definition forUSB_OTG_DIEPEMPMSK register ********************/
+#define USB_OTG_DIEPEMPMSK_INEPTXFEM 0x0000FFFFU /*!< IN EP Tx FIFO empty interrupt mask bits */
+
+/******************** Bit definition forUSB_OTG_DEACHINT register ********************/
+#define USB_OTG_DEACHINT_IEP1INT 0x00000002U /*!< IN endpoint 1interrupt bit */
+#define USB_OTG_DEACHINT_OEP1INT 0x00020000U /*!< OUT endpoint 1 interrupt bit */
+
+/******************** Bit definition forUSB_OTG_GCCFG register ********************/
+#define USB_OTG_GCCFG_PWRDWN 0x00010000U /*!< Power down */
+#define USB_OTG_GCCFG_I2CPADEN 0x00020000U /*!< Enable I2C bus connection for the external I2C PHY interface */
+#define USB_OTG_GCCFG_VBUSASEN 0x00040000U /*!< Enable the VBUS sensing device */
+#define USB_OTG_GCCFG_VBUSBSEN 0x00080000U /*!< Enable the VBUS sensing device */
+#define USB_OTG_GCCFG_SOFOUTEN 0x00100000U /*!< SOF output enable */
+#define USB_OTG_GCCFG_NOVBUSSENS 0x00200000U /*!< VBUS sensing disable option */
+
+/******************** Bit definition forUSB_OTG_DEACHINTMSK register ********************/
+#define USB_OTG_DEACHINTMSK_IEP1INTM 0x00000002U /*!< IN Endpoint 1 interrupt mask bit */
+#define USB_OTG_DEACHINTMSK_OEP1INTM 0x00020000U /*!< OUT Endpoint 1 interrupt mask bit */
+
+/******************** Bit definition forUSB_OTG_CID register ********************/
+#define USB_OTG_CID_PRODUCT_ID 0xFFFFFFFFU /*!< Product ID field */
+
+/******************** Bit definition forUSB_OTG_DIEPEACHMSK1 register ********************/
+#define USB_OTG_DIEPEACHMSK1_XFRCM 0x00000001U /*!< Transfer completed interrupt mask */
+#define USB_OTG_DIEPEACHMSK1_EPDM 0x00000002U /*!< Endpoint disabled interrupt mask */
+#define USB_OTG_DIEPEACHMSK1_TOM 0x00000008U /*!< Timeout condition mask (nonisochronous endpoints) */
+#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK 0x00000010U /*!< IN token received when TxFIFO empty mask */
+#define USB_OTG_DIEPEACHMSK1_INEPNMM 0x00000020U /*!< IN token received with EP mismatch mask */
+#define USB_OTG_DIEPEACHMSK1_INEPNEM 0x00000040U /*!< IN endpoint NAK effective mask */
+#define USB_OTG_DIEPEACHMSK1_TXFURM 0x00000100U /*!< FIFO underrun mask */
+#define USB_OTG_DIEPEACHMSK1_BIM 0x00000200U /*!< BNA interrupt mask */
+#define USB_OTG_DIEPEACHMSK1_NAKM 0x00002000U /*!< NAK interrupt mask */
+
+/******************** Bit definition forUSB_OTG_HPRT register ********************/
+#define USB_OTG_HPRT_PCSTS 0x00000001U /*!< Port connect status */
+#define USB_OTG_HPRT_PCDET 0x00000002U /*!< Port connect detected */
+#define USB_OTG_HPRT_PENA 0x00000004U /*!< Port enable */
+#define USB_OTG_HPRT_PENCHNG 0x00000008U /*!< Port enable/disable change */
+#define USB_OTG_HPRT_POCA 0x00000010U /*!< Port overcurrent active */
+#define USB_OTG_HPRT_POCCHNG 0x00000020U /*!< Port overcurrent change */
+#define USB_OTG_HPRT_PRES 0x00000040U /*!< Port resume */
+#define USB_OTG_HPRT_PSUSP 0x00000080U /*!< Port suspend */
+#define USB_OTG_HPRT_PRST 0x00000100U /*!< Port reset */
+
+#define USB_OTG_HPRT_PLSTS 0x00000C00U /*!< Port line status */
+#define USB_OTG_HPRT_PLSTS_0 0x00000400U /*!<Bit 0 */
+#define USB_OTG_HPRT_PLSTS_1 0x00000800U /*!<Bit 1 */
+#define USB_OTG_HPRT_PPWR 0x00001000U /*!< Port power */
+
+#define USB_OTG_HPRT_PTCTL 0x0001E000U /*!< Port test control */
+#define USB_OTG_HPRT_PTCTL_0 0x00002000U /*!<Bit 0 */
+#define USB_OTG_HPRT_PTCTL_1 0x00004000U /*!<Bit 1 */
+#define USB_OTG_HPRT_PTCTL_2 0x00008000U /*!<Bit 2 */
+#define USB_OTG_HPRT_PTCTL_3 0x00010000U /*!<Bit 3 */
+
+#define USB_OTG_HPRT_PSPD 0x00060000U /*!< Port speed */
+#define USB_OTG_HPRT_PSPD_0 0x00020000U /*!<Bit 0 */
+#define USB_OTG_HPRT_PSPD_1 0x00040000U /*!<Bit 1 */
+
+/******************** Bit definition forUSB_OTG_DOEPEACHMSK1 register ********************/
+#define USB_OTG_DOEPEACHMSK1_XFRCM 0x00000001U /*!< Transfer completed interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_EPDM 0x00000002U /*!< Endpoint disabled interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_TOM 0x00000008U /*!< Timeout condition mask */
+#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK 0x00000010U /*!< IN token received when TxFIFO empty mask */
+#define USB_OTG_DOEPEACHMSK1_INEPNMM 0x00000020U /*!< IN token received with EP mismatch mask */
+#define USB_OTG_DOEPEACHMSK1_INEPNEM 0x00000040U /*!< IN endpoint NAK effective mask */
+#define USB_OTG_DOEPEACHMSK1_TXFURM 0x00000100U /*!< OUT packet error mask */
+#define USB_OTG_DOEPEACHMSK1_BIM 0x00000200U /*!< BNA interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_BERRM 0x00001000U /*!< Bubble error interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_NAKM 0x00002000U /*!< NAK interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_NYETM 0x00004000U /*!< NYET interrupt mask */
+
+/******************** Bit definition forUSB_OTG_HPTXFSIZ register ********************/
+#define USB_OTG_HPTXFSIZ_PTXSA 0x0000FFFFU /*!< Host periodic TxFIFO start address */
+#define USB_OTG_HPTXFSIZ_PTXFD 0xFFFF0000U /*!< Host periodic TxFIFO depth */
+
+/******************** Bit definition forUSB_OTG_DIEPCTL register ********************/
+#define USB_OTG_DIEPCTL_MPSIZ 0x000007FFU /*!< Maximum packet size */
+#define USB_OTG_DIEPCTL_USBAEP 0x00008000U /*!< USB active endpoint */
+#define USB_OTG_DIEPCTL_EONUM_DPID 0x00010000U /*!< Even/odd frame */
+#define USB_OTG_DIEPCTL_NAKSTS 0x00020000U /*!< NAK status */
+
+#define USB_OTG_DIEPCTL_EPTYP 0x000C0000U /*!< Endpoint type */
+#define USB_OTG_DIEPCTL_EPTYP_0 0x00040000U /*!<Bit 0 */
+#define USB_OTG_DIEPCTL_EPTYP_1 0x00080000U /*!<Bit 1 */
+#define USB_OTG_DIEPCTL_STALL 0x00200000U /*!< STALL handshake */
+
+#define USB_OTG_DIEPCTL_TXFNUM 0x03C00000U /*!< TxFIFO number */
+#define USB_OTG_DIEPCTL_TXFNUM_0 0x00400000U /*!<Bit 0 */
+#define USB_OTG_DIEPCTL_TXFNUM_1 0x00800000U /*!<Bit 1 */
+#define USB_OTG_DIEPCTL_TXFNUM_2 0x01000000U /*!<Bit 2 */
+#define USB_OTG_DIEPCTL_TXFNUM_3 0x02000000U /*!<Bit 3 */
+#define USB_OTG_DIEPCTL_CNAK 0x04000000U /*!< Clear NAK */
+#define USB_OTG_DIEPCTL_SNAK 0x08000000U /*!< Set NAK */
+#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM 0x10000000U /*!< Set DATA0 PID */
+#define USB_OTG_DIEPCTL_SODDFRM 0x20000000U /*!< Set odd frame */
+#define USB_OTG_DIEPCTL_EPDIS 0x40000000U /*!< Endpoint disable */
+#define USB_OTG_DIEPCTL_EPENA 0x80000000U /*!< Endpoint enable */
+
+/******************** Bit definition forUSB_OTG_HCCHAR register ********************/
+#define USB_OTG_HCCHAR_MPSIZ 0x000007FFU /*!< Maximum packet size */
+
+#define USB_OTG_HCCHAR_EPNUM 0x00007800U /*!< Endpoint number */
+#define USB_OTG_HCCHAR_EPNUM_0 0x00000800U /*!<Bit 0 */
+#define USB_OTG_HCCHAR_EPNUM_1 0x00001000U /*!<Bit 1 */
+#define USB_OTG_HCCHAR_EPNUM_2 0x00002000U /*!<Bit 2 */
+#define USB_OTG_HCCHAR_EPNUM_3 0x00004000U /*!<Bit 3 */
+#define USB_OTG_HCCHAR_EPDIR 0x00008000U /*!< Endpoint direction */
+#define USB_OTG_HCCHAR_LSDEV 0x00020000U /*!< Low-speed device */
+
+#define USB_OTG_HCCHAR_EPTYP 0x000C0000U /*!< Endpoint type */
+#define USB_OTG_HCCHAR_EPTYP_0 0x00040000U /*!<Bit 0 */
+#define USB_OTG_HCCHAR_EPTYP_1 0x00080000U /*!<Bit 1 */
+
+#define USB_OTG_HCCHAR_MC 0x00300000U /*!< Multi Count (MC) / Error Count (EC) */
+#define USB_OTG_HCCHAR_MC_0 0x00100000U /*!<Bit 0 */
+#define USB_OTG_HCCHAR_MC_1 0x00200000U /*!<Bit 1 */
+
+#define USB_OTG_HCCHAR_DAD 0x1FC00000U /*!< Device address */
+#define USB_OTG_HCCHAR_DAD_0 0x00400000U /*!<Bit 0 */
+#define USB_OTG_HCCHAR_DAD_1 0x00800000U /*!<Bit 1 */
+#define USB_OTG_HCCHAR_DAD_2 0x01000000U /*!<Bit 2 */
+#define USB_OTG_HCCHAR_DAD_3 0x02000000U /*!<Bit 3 */
+#define USB_OTG_HCCHAR_DAD_4 0x04000000U /*!<Bit 4 */
+#define USB_OTG_HCCHAR_DAD_5 0x08000000U /*!<Bit 5 */
+#define USB_OTG_HCCHAR_DAD_6 0x10000000U /*!<Bit 6 */
+#define USB_OTG_HCCHAR_ODDFRM 0x20000000U /*!< Odd frame */
+#define USB_OTG_HCCHAR_CHDIS 0x40000000U /*!< Channel disable */
+#define USB_OTG_HCCHAR_CHENA 0x80000000U /*!< Channel enable */
+
+/******************** Bit definition forUSB_OTG_HCSPLT register ********************/
+
+#define USB_OTG_HCSPLT_PRTADDR 0x0000007FU /*!< Port address */
+#define USB_OTG_HCSPLT_PRTADDR_0 0x00000001U /*!<Bit 0 */
+#define USB_OTG_HCSPLT_PRTADDR_1 0x00000002U /*!<Bit 1 */
+#define USB_OTG_HCSPLT_PRTADDR_2 0x00000004U /*!<Bit 2 */
+#define USB_OTG_HCSPLT_PRTADDR_3 0x00000008U /*!<Bit 3 */
+#define USB_OTG_HCSPLT_PRTADDR_4 0x00000010U /*!<Bit 4 */
+#define USB_OTG_HCSPLT_PRTADDR_5 0x00000020U /*!<Bit 5 */
+#define USB_OTG_HCSPLT_PRTADDR_6 0x00000040U /*!<Bit 6 */
+
+#define USB_OTG_HCSPLT_HUBADDR 0x00003F80U /*!< Hub address */
+#define USB_OTG_HCSPLT_HUBADDR_0 0x00000080U /*!<Bit 0 */
+#define USB_OTG_HCSPLT_HUBADDR_1 0x00000100U /*!<Bit 1 */
+#define USB_OTG_HCSPLT_HUBADDR_2 0x00000200U /*!<Bit 2 */
+#define USB_OTG_HCSPLT_HUBADDR_3 0x00000400U /*!<Bit 3 */
+#define USB_OTG_HCSPLT_HUBADDR_4 0x00000800U /*!<Bit 4 */
+#define USB_OTG_HCSPLT_HUBADDR_5 0x00001000U /*!<Bit 5 */
+#define USB_OTG_HCSPLT_HUBADDR_6 0x00002000U /*!<Bit 6 */
+
+#define USB_OTG_HCSPLT_XACTPOS 0x0000C000U /*!< XACTPOS */
+#define USB_OTG_HCSPLT_XACTPOS_0 0x00004000U /*!<Bit 0 */
+#define USB_OTG_HCSPLT_XACTPOS_1 0x00008000U /*!<Bit 1 */
+#define USB_OTG_HCSPLT_COMPLSPLT 0x00010000U /*!< Do complete split */
+#define USB_OTG_HCSPLT_SPLITEN 0x80000000U /*!< Split enable */
+
+/******************** Bit definition forUSB_OTG_HCINT register ********************/
+#define USB_OTG_HCINT_XFRC 0x00000001U /*!< Transfer completed */
+#define USB_OTG_HCINT_CHH 0x00000002U /*!< Channel halted */
+#define USB_OTG_HCINT_AHBERR 0x00000004U /*!< AHB error */
+#define USB_OTG_HCINT_STALL 0x00000008U /*!< STALL response received interrupt */
+#define USB_OTG_HCINT_NAK 0x00000010U /*!< NAK response received interrupt */
+#define USB_OTG_HCINT_ACK 0x00000020U /*!< ACK response received/transmitted interrupt */
+#define USB_OTG_HCINT_NYET 0x00000040U /*!< Response received interrupt */
+#define USB_OTG_HCINT_TXERR 0x00000080U /*!< Transaction error */
+#define USB_OTG_HCINT_BBERR 0x00000100U /*!< Babble error */
+#define USB_OTG_HCINT_FRMOR 0x00000200U /*!< Frame overrun */
+#define USB_OTG_HCINT_DTERR 0x00000400U /*!< Data toggle error */
+
+/******************** Bit definition forUSB_OTG_DIEPINT register ********************/
+#define USB_OTG_DIEPINT_XFRC 0x00000001U /*!< Transfer completed interrupt */
+#define USB_OTG_DIEPINT_EPDISD 0x00000002U /*!< Endpoint disabled interrupt */
+#define USB_OTG_DIEPINT_TOC 0x00000008U /*!< Timeout condition */
+#define USB_OTG_DIEPINT_ITTXFE 0x00000010U /*!< IN token received when TxFIFO is empty */
+#define USB_OTG_DIEPINT_INEPNE 0x00000040U /*!< IN endpoint NAK effective */
+#define USB_OTG_DIEPINT_TXFE 0x00000080U /*!< Transmit FIFO empty */
+#define USB_OTG_DIEPINT_TXFIFOUDRN 0x00000100U /*!< Transmit Fifo Underrun */
+#define USB_OTG_DIEPINT_BNA 0x00000200U /*!< Buffer not available interrupt */
+#define USB_OTG_DIEPINT_PKTDRPSTS 0x00000800U /*!< Packet dropped status */
+#define USB_OTG_DIEPINT_BERR 0x00001000U /*!< Babble error interrupt */
+#define USB_OTG_DIEPINT_NAK 0x00002000U /*!< NAK interrupt */
+
+/******************** Bit definition forUSB_OTG_HCINTMSK register ********************/
+#define USB_OTG_HCINTMSK_XFRCM 0x00000001U /*!< Transfer completed mask */
+#define USB_OTG_HCINTMSK_CHHM 0x00000002U /*!< Channel halted mask */
+#define USB_OTG_HCINTMSK_AHBERR 0x00000004U /*!< AHB error */
+#define USB_OTG_HCINTMSK_STALLM 0x00000008U /*!< STALL response received interrupt mask */
+#define USB_OTG_HCINTMSK_NAKM 0x00000010U /*!< NAK response received interrupt mask */
+#define USB_OTG_HCINTMSK_ACKM 0x00000020U /*!< ACK response received/transmitted interrupt mask */
+#define USB_OTG_HCINTMSK_NYET 0x00000040U /*!< response received interrupt mask */
+#define USB_OTG_HCINTMSK_TXERRM 0x00000080U /*!< Transaction error mask */
+#define USB_OTG_HCINTMSK_BBERRM 0x00000100U /*!< Babble error mask */
+#define USB_OTG_HCINTMSK_FRMORM 0x00000200U /*!< Frame overrun mask */
+#define USB_OTG_HCINTMSK_DTERRM 0x00000400U /*!< Data toggle error mask */
+
+/******************** Bit definition for USB_OTG_DIEPTSIZ register ********************/
+
+#define USB_OTG_DIEPTSIZ_XFRSIZ 0x0007FFFFU /*!< Transfer size */
+#define USB_OTG_DIEPTSIZ_PKTCNT 0x1FF80000U /*!< Packet count */
+#define USB_OTG_DIEPTSIZ_MULCNT 0x60000000U /*!< Packet count */
+/******************** Bit definition forUSB_OTG_HCTSIZ register ********************/
+#define USB_OTG_HCTSIZ_XFRSIZ 0x0007FFFFU /*!< Transfer size */
+#define USB_OTG_HCTSIZ_PKTCNT 0x1FF80000U /*!< Packet count */
+#define USB_OTG_HCTSIZ_DOPING 0x80000000U /*!< Do PING */
+#define USB_OTG_HCTSIZ_DPID 0x60000000U /*!< Data PID */
+#define USB_OTG_HCTSIZ_DPID_0 0x20000000U /*!<Bit 0 */
+#define USB_OTG_HCTSIZ_DPID_1 0x40000000U /*!<Bit 1 */
+
+/******************** Bit definition forUSB_OTG_DIEPDMA register ********************/
+#define USB_OTG_DIEPDMA_DMAADDR 0xFFFFFFFFU /*!< DMA address */
+
+/******************** Bit definition forUSB_OTG_HCDMA register ********************/
+#define USB_OTG_HCDMA_DMAADDR 0xFFFFFFFFU /*!< DMA address */
+
+/******************** Bit definition forUSB_OTG_DTXFSTS register ********************/
+#define USB_OTG_DTXFSTS_INEPTFSAV 0x0000FFFFU /*!< IN endpoint TxFIFO space available */
+
+/******************** Bit definition forUSB_OTG_DIEPTXF register ********************/
+#define USB_OTG_DIEPTXF_INEPTXSA 0x0000FFFFU /*!< IN endpoint FIFOx transmit RAM start address */
+#define USB_OTG_DIEPTXF_INEPTXFD 0xFFFF0000U /*!< IN endpoint TxFIFO depth */
+
+/******************** Bit definition forUSB_OTG_DOEPCTL register ********************/
+
+#define USB_OTG_DOEPCTL_MPSIZ 0x000007FFU /*!< Maximum packet size */ /*!<Bit 1 */
+#define USB_OTG_DOEPCTL_USBAEP 0x00008000U /*!< USB active endpoint */
+#define USB_OTG_DOEPCTL_NAKSTS 0x00020000U /*!< NAK status */
+#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM 0x10000000U /*!< Set DATA0 PID */
+#define USB_OTG_DOEPCTL_SODDFRM 0x20000000U /*!< Set odd frame */
+#define USB_OTG_DOEPCTL_EPTYP 0x000C0000U /*!< Endpoint type */
+#define USB_OTG_DOEPCTL_EPTYP_0 0x00040000U /*!<Bit 0 */
+#define USB_OTG_DOEPCTL_EPTYP_1 0x00080000U /*!<Bit 1 */
+#define USB_OTG_DOEPCTL_SNPM 0x00100000U /*!< Snoop mode */
+#define USB_OTG_DOEPCTL_STALL 0x00200000U /*!< STALL handshake */
+#define USB_OTG_DOEPCTL_CNAK 0x04000000U /*!< Clear NAK */
+#define USB_OTG_DOEPCTL_SNAK 0x08000000U /*!< Set NAK */
+#define USB_OTG_DOEPCTL_EPDIS 0x40000000U /*!< Endpoint disable */
+#define USB_OTG_DOEPCTL_EPENA 0x80000000U /*!< Endpoint enable */
+
+/******************** Bit definition forUSB_OTG_DOEPINT register ********************/
+#define USB_OTG_DOEPINT_XFRC 0x00000001U /*!< Transfer completed interrupt */
+#define USB_OTG_DOEPINT_EPDISD 0x00000002U /*!< Endpoint disabled interrupt */
+#define USB_OTG_DOEPINT_STUP 0x00000008U /*!< SETUP phase done */
+#define USB_OTG_DOEPINT_OTEPDIS 0x00000010U /*!< OUT token received when endpoint disabled */
+#define USB_OTG_DOEPINT_B2BSTUP 0x00000040U /*!< Back-to-back SETUP packets received */
+#define USB_OTG_DOEPINT_NYET 0x00004000U /*!< NYET interrupt */
+
+/******************** Bit definition forUSB_OTG_DOEPTSIZ register ********************/
+
+#define USB_OTG_DOEPTSIZ_XFRSIZ 0x0007FFFFU /*!< Transfer size */
+#define USB_OTG_DOEPTSIZ_PKTCNT 0x1FF80000U /*!< Packet count */
+
+#define USB_OTG_DOEPTSIZ_STUPCNT 0x60000000U /*!< SETUP packet count */
+#define USB_OTG_DOEPTSIZ_STUPCNT_0 0x20000000U /*!<Bit 0 */
+#define USB_OTG_DOEPTSIZ_STUPCNT_1 0x40000000U /*!<Bit 1 */
+
+/******************** Bit definition for PCGCCTL register ********************/
+#define USB_OTG_PCGCCTL_STOPCLK 0x00000001U /*!< SETUP packet count */
+#define USB_OTG_PCGCCTL_GATECLK 0x00000002U /*!<Bit 0 */
+#define USB_OTG_PCGCCTL_PHYSUSP 0x00000010U /*!<Bit 1 */
+
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup Exported_macros
+ * @{
+ */
+
+/******************************* ADC Instances ********************************/
+#define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) || \
+ ((INSTANCE) == ADC2) || \
+ ((INSTANCE) == ADC3))
+
+/******************************* CAN Instances ********************************/
+#define IS_CAN_ALL_INSTANCE(INSTANCE) (((INSTANCE) == CAN1) || \
+ ((INSTANCE) == CAN2))
+
+/******************************* CRC Instances ********************************/
+#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
+
+/******************************* DAC Instances ********************************/
+#define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC)
+
+/******************************* DCMI Instances *******************************/
+#define IS_DCMI_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DCMI)
+
+/******************************* DMA2D Instances *******************************/
+#define IS_DMA2D_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DMA2D)
+
+/******************************** DMA Instances *******************************/
+#define IS_DMA_STREAM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0) || \
+ ((INSTANCE) == DMA1_Stream1) || \
+ ((INSTANCE) == DMA1_Stream2) || \
+ ((INSTANCE) == DMA1_Stream3) || \
+ ((INSTANCE) == DMA1_Stream4) || \
+ ((INSTANCE) == DMA1_Stream5) || \
+ ((INSTANCE) == DMA1_Stream6) || \
+ ((INSTANCE) == DMA1_Stream7) || \
+ ((INSTANCE) == DMA2_Stream0) || \
+ ((INSTANCE) == DMA2_Stream1) || \
+ ((INSTANCE) == DMA2_Stream2) || \
+ ((INSTANCE) == DMA2_Stream3) || \
+ ((INSTANCE) == DMA2_Stream4) || \
+ ((INSTANCE) == DMA2_Stream5) || \
+ ((INSTANCE) == DMA2_Stream6) || \
+ ((INSTANCE) == DMA2_Stream7))
+
+/******************************* GPIO Instances *******************************/
+#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
+ ((INSTANCE) == GPIOB) || \
+ ((INSTANCE) == GPIOC) || \
+ ((INSTANCE) == GPIOD) || \
+ ((INSTANCE) == GPIOE) || \
+ ((INSTANCE) == GPIOF) || \
+ ((INSTANCE) == GPIOG) || \
+ ((INSTANCE) == GPIOH) || \
+ ((INSTANCE) == GPIOI) || \
+ ((INSTANCE) == GPIOJ) || \
+ ((INSTANCE) == GPIOK))
+
+/******************************** I2C Instances *******************************/
+#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
+ ((INSTANCE) == I2C2) || \
+ ((INSTANCE) == I2C3))
+
+/******************************** I2S Instances *******************************/
+#define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI2) || \
+ ((INSTANCE) == SPI3))
+
+/*************************** I2S Extended Instances ***************************/
+#define IS_I2S_ALL_INSTANCE_EXT(PERIPH) (((INSTANCE) == SPI2) || \
+ ((INSTANCE) == SPI3) || \
+ ((INSTANCE) == I2S2ext) || \
+ ((INSTANCE) == I2S3ext))
+
+/******************************* RNG Instances ********************************/
+#define IS_RNG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RNG)
+
+/****************************** RTC Instances *********************************/
+#define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
+
+/******************************* SAI Instances ********************************/
+#define IS_SAI_ALL_INSTANCE(PERIPH) (((PERIPH) == SAI1_Block_A) || \
+ ((PERIPH) == SAI1_Block_B))
+/* Legacy define */
+#define IS_SAI_BLOCK_PERIPH IS_SAI_ALL_INSTANCE
+
+/******************************** SPI Instances *******************************/
+#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
+ ((INSTANCE) == SPI2) || \
+ ((INSTANCE) == SPI3) || \
+ ((INSTANCE) == SPI4) || \
+ ((INSTANCE) == SPI5) || \
+ ((INSTANCE) == SPI6))
+
+/*************************** SPI Extended Instances ***************************/
+#define IS_SPI_ALL_INSTANCE_EXT(INSTANCE) (((INSTANCE) == SPI1) || \
+ ((INSTANCE) == SPI2) || \
+ ((INSTANCE) == SPI3) || \
+ ((INSTANCE) == SPI4) || \
+ ((INSTANCE) == SPI5) || \
+ ((INSTANCE) == SPI6) || \
+ ((INSTANCE) == I2S2ext) || \
+ ((INSTANCE) == I2S3ext))
+
+/****************** TIM Instances : All supported instances *******************/
+#define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM6) || \
+ ((INSTANCE) == TIM7) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM9) || \
+ ((INSTANCE) == TIM10) || \
+ ((INSTANCE) == TIM11) || \
+ ((INSTANCE) == TIM12) || \
+ ((INSTANCE) == TIM13) || \
+ ((INSTANCE) == TIM14))
+
+/************* TIM Instances : at least 1 capture/compare channel *************/
+#define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM9) || \
+ ((INSTANCE) == TIM10) || \
+ ((INSTANCE) == TIM11) || \
+ ((INSTANCE) == TIM12) || \
+ ((INSTANCE) == TIM13) || \
+ ((INSTANCE) == TIM14))
+
+/************ TIM Instances : at least 2 capture/compare channels *************/
+#define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM9) || \
+ ((INSTANCE) == TIM12))
+
+/************ TIM Instances : at least 3 capture/compare channels *************/
+#define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8))
+
+/************ TIM Instances : at least 4 capture/compare channels *************/
+#define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8))
+
+/******************** TIM Instances : Advanced-control timers *****************/
+#define IS_TIM_ADVANCED_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM8))
+
+/******************* TIM Instances : Timer input XOR function *****************/
+#define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8))
+
+/****************** TIM Instances : DMA requests generation (UDE) *************/
+#define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM6) || \
+ ((INSTANCE) == TIM7) || \
+ ((INSTANCE) == TIM8))
+
+/************ TIM Instances : DMA requests generation (CCxDE) *****************/
+#define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8))
+
+/************ TIM Instances : DMA requests generation (COMDE) *****************/
+#define IS_TIM_CCDMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8))
+
+/******************** TIM Instances : DMA burst feature ***********************/
+#define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8))
+
+/****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/
+#define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM6) || \
+ ((INSTANCE) == TIM7) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM9) || \
+ ((INSTANCE) == TIM12))
+
+/*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
+#define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM9) || \
+ ((INSTANCE) == TIM12))
+
+/********************** TIM Instances : 32 bit Counter ************************/
+#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)(((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM5))
+
+/***************** TIM Instances : external trigger input availabe ************/
+#define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8))
+
+/****************** TIM Instances : remapping capability **********************/
+#define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM11))
+
+/******************* TIM Instances : output(s) available **********************/
+#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
+ ((((INSTANCE) == TIM1) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM2) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM3) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM4) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM5) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM8) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM9) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2))) \
+ || \
+ (((INSTANCE) == TIM10) && \
+ (((CHANNEL) == TIM_CHANNEL_1))) \
+ || \
+ (((INSTANCE) == TIM11) && \
+ (((CHANNEL) == TIM_CHANNEL_1))) \
+ || \
+ (((INSTANCE) == TIM12) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2))) \
+ || \
+ (((INSTANCE) == TIM13) && \
+ (((CHANNEL) == TIM_CHANNEL_1))) \
+ || \
+ (((INSTANCE) == TIM14) && \
+ (((CHANNEL) == TIM_CHANNEL_1))))
+
+/************ TIM Instances : complementary output(s) available ***************/
+#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
+ ((((INSTANCE) == TIM1) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3))) \
+ || \
+ (((INSTANCE) == TIM8) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3))))
+
+/******************** USART Instances : Synchronous mode **********************/
+#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3) || \
+ ((INSTANCE) == USART6))
+
+/******************** UART Instances : Asynchronous mode **********************/
+#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3) || \
+ ((INSTANCE) == UART4) || \
+ ((INSTANCE) == UART5) || \
+ ((INSTANCE) == USART6) || \
+ ((INSTANCE) == UART7) || \
+ ((INSTANCE) == UART8))
+
+/****************** UART Instances : Hardware Flow control ********************/
+#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3) || \
+ ((INSTANCE) == USART6))
+
+/********************* UART Instances : Smard card mode ***********************/
+#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3) || \
+ ((INSTANCE) == USART6))
+
+/*********************** UART Instances : IRDA mode ***************************/
+#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3) || \
+ ((INSTANCE) == UART4) || \
+ ((INSTANCE) == UART5) || \
+ ((INSTANCE) == USART6) || \
+ ((INSTANCE) == UART7) || \
+ ((INSTANCE) == UART8))
+
+/*********************** PCD Instances ****************************************/
+#define IS_PCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS) || \
+ ((INSTANCE) == USB_OTG_HS))
+
+/*********************** HCD Instances ****************************************/
+#define IS_HCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS) || \
+ ((INSTANCE) == USB_OTG_HS))
+
+/****************************** IWDG Instances ********************************/
+#define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
+
+/****************************** WWDG Instances ********************************/
+#define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
+
+/****************************** SDIO Instances ********************************/
+#define IS_SDIO_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SDIO)
+
+/****************************** USB Exported Constants ************************/
+#define USB_OTG_FS_HOST_MAX_CHANNEL_NBR 8U
+#define USB_OTG_FS_MAX_IN_ENDPOINTS 4U /* Including EP0 */
+#define USB_OTG_FS_MAX_OUT_ENDPOINTS 4U /* Including EP0 */
+#define USB_OTG_FS_TOTAL_FIFO_SIZE 1280U /* in Bytes */
+
+#define USB_OTG_HS_HOST_MAX_CHANNEL_NBR 12U
+#define USB_OTG_HS_MAX_IN_ENDPOINTS 6U /* Including EP0 */
+#define USB_OTG_HS_MAX_OUT_ENDPOINTS 6U /* Including EP0 */
+#define USB_OTG_HS_TOTAL_FIFO_SIZE 4096U /* in Bytes */
+
+/******************************************************************************/
+/* For a painless codes migration between the STM32F4xx device product */
+/* lines, the aliases defined below are put in place to overcome the */
+/* differences in the interrupt handlers and IRQn definitions. */
+/* No need to update developed interrupt code when moving across */
+/* product lines within the same STM32F4 Family */
+/******************************************************************************/
+
+/* Aliases for __IRQn */
+#define FSMC_IRQn FMC_IRQn
+
+/* Aliases for __IRQHandler */
+#define FSMC_IRQHandler FMC_IRQHandler
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* __STM32F437xx_H */
+
+
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Device/ST/STM32F4xx/Include/stm32f439xx.h b/Device/ST/STM32F4xx/Include/stm32f439xx.h
new file mode 100644
index 0000000..956ab86
--- /dev/null
+++ b/Device/ST/STM32F4xx/Include/stm32f439xx.h
@@ -0,0 +1,9306 @@
+/**
+ ******************************************************************************
+ * @file stm32f439xx.h
+ * @author MCD Application Team
+ * @version V2.5.0
+ * @date 22-April-2016
+ * @brief CMSIS STM32F439xx Device Peripheral Access Layer Header File.
+ *
+ * This file contains:
+ * - Data structures and the address mapping for all peripherals
+ * - peripherals registers declarations and bits definition
+ * - Macros to access peripheral’s registers hardware
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/** @addtogroup CMSIS_Device
+ * @{
+ */
+
+/** @addtogroup stm32f439xx
+ * @{
+ */
+
+#ifndef __STM32F439xx_H
+#define __STM32F439xx_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif /* __cplusplus */
+
+/** @addtogroup Configuration_section_for_CMSIS
+ * @{
+ */
+
+/**
+ * @brief Configuration of the Cortex-M4 Processor and Core Peripherals
+ */
+#define __CM4_REV 0x0001U /*!< Core revision r0p1 */
+#define __MPU_PRESENT 1U /*!< STM32F4XX provides an MPU */
+#define __NVIC_PRIO_BITS 4U /*!< STM32F4XX uses 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */
+#define __FPU_PRESENT 1U /*!< FPU present */
+
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_interrupt_number_definition
+ * @{
+ */
+
+/**
+ * @brief STM32F4XX Interrupt Number Definition, according to the selected device
+ * in @ref Library_configuration_section
+ */
+typedef enum
+{
+/****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/
+ NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
+ MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */
+ BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */
+ UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */
+ SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */
+ DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */
+ PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */
+ SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */
+/****** STM32 specific Interrupt Numbers **********************************************************************/
+ WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
+ PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */
+ TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */
+ RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */
+ FLASH_IRQn = 4, /*!< FLASH global Interrupt */
+ RCC_IRQn = 5, /*!< RCC global Interrupt */
+ EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */
+ EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */
+ EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */
+ EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */
+ EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */
+ DMA1_Stream0_IRQn = 11, /*!< DMA1 Stream 0 global Interrupt */
+ DMA1_Stream1_IRQn = 12, /*!< DMA1 Stream 1 global Interrupt */
+ DMA1_Stream2_IRQn = 13, /*!< DMA1 Stream 2 global Interrupt */
+ DMA1_Stream3_IRQn = 14, /*!< DMA1 Stream 3 global Interrupt */
+ DMA1_Stream4_IRQn = 15, /*!< DMA1 Stream 4 global Interrupt */
+ DMA1_Stream5_IRQn = 16, /*!< DMA1 Stream 5 global Interrupt */
+ DMA1_Stream6_IRQn = 17, /*!< DMA1 Stream 6 global Interrupt */
+ ADC_IRQn = 18, /*!< ADC1, ADC2 and ADC3 global Interrupts */
+ CAN1_TX_IRQn = 19, /*!< CAN1 TX Interrupt */
+ CAN1_RX0_IRQn = 20, /*!< CAN1 RX0 Interrupt */
+ CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */
+ CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */
+ EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
+ TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break interrupt and TIM9 global interrupt */
+ TIM1_UP_TIM10_IRQn = 25, /*!< TIM1 Update Interrupt and TIM10 global interrupt */
+ TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */
+ TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
+ TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
+ TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
+ TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
+ I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
+ I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
+ I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
+ I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
+ SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
+ SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
+ USART1_IRQn = 37, /*!< USART1 global Interrupt */
+ USART2_IRQn = 38, /*!< USART2 global Interrupt */
+ USART3_IRQn = 39, /*!< USART3 global Interrupt */
+ EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
+ RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */
+ OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS Wakeup through EXTI line interrupt */
+ TIM8_BRK_TIM12_IRQn = 43, /*!< TIM8 Break Interrupt and TIM12 global interrupt */
+ TIM8_UP_TIM13_IRQn = 44, /*!< TIM8 Update Interrupt and TIM13 global interrupt */
+ TIM8_TRG_COM_TIM14_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */
+ TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */
+ DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */
+ FMC_IRQn = 48, /*!< FMC global Interrupt */
+ SDIO_IRQn = 49, /*!< SDIO global Interrupt */
+ TIM5_IRQn = 50, /*!< TIM5 global Interrupt */
+ SPI3_IRQn = 51, /*!< SPI3 global Interrupt */
+ UART4_IRQn = 52, /*!< UART4 global Interrupt */
+ UART5_IRQn = 53, /*!< UART5 global Interrupt */
+ TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC1&2 underrun error interrupts */
+ TIM7_IRQn = 55, /*!< TIM7 global interrupt */
+ DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */
+ DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */
+ DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */
+ DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */
+ DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */
+ ETH_IRQn = 61, /*!< Ethernet global Interrupt */
+ ETH_WKUP_IRQn = 62, /*!< Ethernet Wakeup through EXTI line Interrupt */
+ CAN2_TX_IRQn = 63, /*!< CAN2 TX Interrupt */
+ CAN2_RX0_IRQn = 64, /*!< CAN2 RX0 Interrupt */
+ CAN2_RX1_IRQn = 65, /*!< CAN2 RX1 Interrupt */
+ CAN2_SCE_IRQn = 66, /*!< CAN2 SCE Interrupt */
+ OTG_FS_IRQn = 67, /*!< USB OTG FS global Interrupt */
+ DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */
+ DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */
+ DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */
+ USART6_IRQn = 71, /*!< USART6 global interrupt */
+ I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */
+ I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */
+ OTG_HS_EP1_OUT_IRQn = 74, /*!< USB OTG HS End Point 1 Out global interrupt */
+ OTG_HS_EP1_IN_IRQn = 75, /*!< USB OTG HS End Point 1 In global interrupt */
+ OTG_HS_WKUP_IRQn = 76, /*!< USB OTG HS Wakeup through EXTI interrupt */
+ OTG_HS_IRQn = 77, /*!< USB OTG HS global interrupt */
+ DCMI_IRQn = 78, /*!< DCMI global interrupt */
+ CRYP_IRQn = 79, /*!< CRYP crypto global interrupt */
+ HASH_RNG_IRQn = 80, /*!< Hash and Rng global interrupt */
+ FPU_IRQn = 81, /*!< FPU global interrupt */
+ UART7_IRQn = 82, /*!< UART7 global interrupt */
+ UART8_IRQn = 83, /*!< UART8 global interrupt */
+ SPI4_IRQn = 84, /*!< SPI4 global Interrupt */
+ SPI5_IRQn = 85, /*!< SPI5 global Interrupt */
+ SPI6_IRQn = 86, /*!< SPI6 global Interrupt */
+ SAI1_IRQn = 87, /*!< SAI1 global Interrupt */
+ LTDC_IRQn = 88, /*!< LTDC global Interrupt */
+ LTDC_ER_IRQn = 89, /*!< LTDC Error global Interrupt */
+ DMA2D_IRQn = 90 /*!< DMA2D global Interrupt */
+} IRQn_Type;
+
+/**
+ * @}
+ */
+
+#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
+#include "system_stm32f4xx.h"
+#include <stdint.h>
+
+/** @addtogroup Peripheral_registers_structures
+ * @{
+ */
+
+/**
+ * @brief Analog to Digital Converter
+ */
+
+typedef struct
+{
+ __IO uint32_t SR; /*!< ADC status register, Address offset: 0x00 */
+ __IO uint32_t CR1; /*!< ADC control register 1, Address offset: 0x04 */
+ __IO uint32_t CR2; /*!< ADC control register 2, Address offset: 0x08 */
+ __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x0C */
+ __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x10 */
+ __IO uint32_t JOFR1; /*!< ADC injected channel data offset register 1, Address offset: 0x14 */
+ __IO uint32_t JOFR2; /*!< ADC injected channel data offset register 2, Address offset: 0x18 */
+ __IO uint32_t JOFR3; /*!< ADC injected channel data offset register 3, Address offset: 0x1C */
+ __IO uint32_t JOFR4; /*!< ADC injected channel data offset register 4, Address offset: 0x20 */
+ __IO uint32_t HTR; /*!< ADC watchdog higher threshold register, Address offset: 0x24 */
+ __IO uint32_t LTR; /*!< ADC watchdog lower threshold register, Address offset: 0x28 */
+ __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x2C */
+ __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x30 */
+ __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x34 */
+ __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x38*/
+ __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x3C */
+ __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x40 */
+ __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x44 */
+ __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x48 */
+ __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x4C */
+} ADC_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1 base address + 0x300 */
+ __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1 base address + 0x304 */
+ __IO uint32_t CDR; /*!< ADC common regular data register for dual
+ AND triple modes, Address offset: ADC1 base address + 0x308 */
+} ADC_Common_TypeDef;
+
+
+/**
+ * @brief Controller Area Network TxMailBox
+ */
+
+typedef struct
+{
+ __IO uint32_t TIR; /*!< CAN TX mailbox identifier register */
+ __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */
+ __IO uint32_t TDLR; /*!< CAN mailbox data low register */
+ __IO uint32_t TDHR; /*!< CAN mailbox data high register */
+} CAN_TxMailBox_TypeDef;
+
+/**
+ * @brief Controller Area Network FIFOMailBox
+ */
+
+typedef struct
+{
+ __IO uint32_t RIR; /*!< CAN receive FIFO mailbox identifier register */
+ __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */
+ __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */
+ __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */
+} CAN_FIFOMailBox_TypeDef;
+
+/**
+ * @brief Controller Area Network FilterRegister
+ */
+
+typedef struct
+{
+ __IO uint32_t FR1; /*!< CAN Filter bank register 1 */
+ __IO uint32_t FR2; /*!< CAN Filter bank register 1 */
+} CAN_FilterRegister_TypeDef;
+
+/**
+ * @brief Controller Area Network
+ */
+
+typedef struct
+{
+ __IO uint32_t MCR; /*!< CAN master control register, Address offset: 0x00 */
+ __IO uint32_t MSR; /*!< CAN master status register, Address offset: 0x04 */
+ __IO uint32_t TSR; /*!< CAN transmit status register, Address offset: 0x08 */
+ __IO uint32_t RF0R; /*!< CAN receive FIFO 0 register, Address offset: 0x0C */
+ __IO uint32_t RF1R; /*!< CAN receive FIFO 1 register, Address offset: 0x10 */
+ __IO uint32_t IER; /*!< CAN interrupt enable register, Address offset: 0x14 */
+ __IO uint32_t ESR; /*!< CAN error status register, Address offset: 0x18 */
+ __IO uint32_t BTR; /*!< CAN bit timing register, Address offset: 0x1C */
+ uint32_t RESERVED0[88]; /*!< Reserved, 0x020 - 0x17F */
+ CAN_TxMailBox_TypeDef sTxMailBox[3]; /*!< CAN Tx MailBox, Address offset: 0x180 - 0x1AC */
+ CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; /*!< CAN FIFO MailBox, Address offset: 0x1B0 - 0x1CC */
+ uint32_t RESERVED1[12]; /*!< Reserved, 0x1D0 - 0x1FF */
+ __IO uint32_t FMR; /*!< CAN filter master register, Address offset: 0x200 */
+ __IO uint32_t FM1R; /*!< CAN filter mode register, Address offset: 0x204 */
+ uint32_t RESERVED2; /*!< Reserved, 0x208 */
+ __IO uint32_t FS1R; /*!< CAN filter scale register, Address offset: 0x20C */
+ uint32_t RESERVED3; /*!< Reserved, 0x210 */
+ __IO uint32_t FFA1R; /*!< CAN filter FIFO assignment register, Address offset: 0x214 */
+ uint32_t RESERVED4; /*!< Reserved, 0x218 */
+ __IO uint32_t FA1R; /*!< CAN filter activation register, Address offset: 0x21C */
+ uint32_t RESERVED5[8]; /*!< Reserved, 0x220-0x23F */
+ CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register, Address offset: 0x240-0x31C */
+} CAN_TypeDef;
+
+/**
+ * @brief CRC calculation unit
+ */
+
+typedef struct
+{
+ __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
+ __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
+ uint8_t RESERVED0; /*!< Reserved, 0x05 */
+ uint16_t RESERVED1; /*!< Reserved, 0x06 */
+ __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
+} CRC_TypeDef;
+
+/**
+ * @brief Digital to Analog Converter
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */
+ __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */
+ __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
+ __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */
+ __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */
+ __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
+ __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */
+ __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */
+ __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */
+ __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */
+ __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */
+ __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */
+ __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */
+ __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */
+} DAC_TypeDef;
+
+/**
+ * @brief Debug MCU
+ */
+
+typedef struct
+{
+ __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
+ __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
+ __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */
+ __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */
+}DBGMCU_TypeDef;
+
+/**
+ * @brief DCMI
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< DCMI control register 1, Address offset: 0x00 */
+ __IO uint32_t SR; /*!< DCMI status register, Address offset: 0x04 */
+ __IO uint32_t RISR; /*!< DCMI raw interrupt status register, Address offset: 0x08 */
+ __IO uint32_t IER; /*!< DCMI interrupt enable register, Address offset: 0x0C */
+ __IO uint32_t MISR; /*!< DCMI masked interrupt status register, Address offset: 0x10 */
+ __IO uint32_t ICR; /*!< DCMI interrupt clear register, Address offset: 0x14 */
+ __IO uint32_t ESCR; /*!< DCMI embedded synchronization code register, Address offset: 0x18 */
+ __IO uint32_t ESUR; /*!< DCMI embedded synchronization unmask register, Address offset: 0x1C */
+ __IO uint32_t CWSTRTR; /*!< DCMI crop window start, Address offset: 0x20 */
+ __IO uint32_t CWSIZER; /*!< DCMI crop window size, Address offset: 0x24 */
+ __IO uint32_t DR; /*!< DCMI data register, Address offset: 0x28 */
+} DCMI_TypeDef;
+
+/**
+ * @brief DMA Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< DMA stream x configuration register */
+ __IO uint32_t NDTR; /*!< DMA stream x number of data register */
+ __IO uint32_t PAR; /*!< DMA stream x peripheral address register */
+ __IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */
+ __IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */
+ __IO uint32_t FCR; /*!< DMA stream x FIFO control register */
+} DMA_Stream_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t LISR; /*!< DMA low interrupt status register, Address offset: 0x00 */
+ __IO uint32_t HISR; /*!< DMA high interrupt status register, Address offset: 0x04 */
+ __IO uint32_t LIFCR; /*!< DMA low interrupt flag clear register, Address offset: 0x08 */
+ __IO uint32_t HIFCR; /*!< DMA high interrupt flag clear register, Address offset: 0x0C */
+} DMA_TypeDef;
+
+/**
+ * @brief DMA2D Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< DMA2D Control Register, Address offset: 0x00 */
+ __IO uint32_t ISR; /*!< DMA2D Interrupt Status Register, Address offset: 0x04 */
+ __IO uint32_t IFCR; /*!< DMA2D Interrupt Flag Clear Register, Address offset: 0x08 */
+ __IO uint32_t FGMAR; /*!< DMA2D Foreground Memory Address Register, Address offset: 0x0C */
+ __IO uint32_t FGOR; /*!< DMA2D Foreground Offset Register, Address offset: 0x10 */
+ __IO uint32_t BGMAR; /*!< DMA2D Background Memory Address Register, Address offset: 0x14 */
+ __IO uint32_t BGOR; /*!< DMA2D Background Offset Register, Address offset: 0x18 */
+ __IO uint32_t FGPFCCR; /*!< DMA2D Foreground PFC Control Register, Address offset: 0x1C */
+ __IO uint32_t FGCOLR; /*!< DMA2D Foreground Color Register, Address offset: 0x20 */
+ __IO uint32_t BGPFCCR; /*!< DMA2D Background PFC Control Register, Address offset: 0x24 */
+ __IO uint32_t BGCOLR; /*!< DMA2D Background Color Register, Address offset: 0x28 */
+ __IO uint32_t FGCMAR; /*!< DMA2D Foreground CLUT Memory Address Register, Address offset: 0x2C */
+ __IO uint32_t BGCMAR; /*!< DMA2D Background CLUT Memory Address Register, Address offset: 0x30 */
+ __IO uint32_t OPFCCR; /*!< DMA2D Output PFC Control Register, Address offset: 0x34 */
+ __IO uint32_t OCOLR; /*!< DMA2D Output Color Register, Address offset: 0x38 */
+ __IO uint32_t OMAR; /*!< DMA2D Output Memory Address Register, Address offset: 0x3C */
+ __IO uint32_t OOR; /*!< DMA2D Output Offset Register, Address offset: 0x40 */
+ __IO uint32_t NLR; /*!< DMA2D Number of Line Register, Address offset: 0x44 */
+ __IO uint32_t LWR; /*!< DMA2D Line Watermark Register, Address offset: 0x48 */
+ __IO uint32_t AMTCR; /*!< DMA2D AHB Master Timer Configuration Register, Address offset: 0x4C */
+ uint32_t RESERVED[236]; /*!< Reserved, 0x50-0x3FF */
+ __IO uint32_t FGCLUT[256]; /*!< DMA2D Foreground CLUT, Address offset:400-7FF */
+ __IO uint32_t BGCLUT[256]; /*!< DMA2D Background CLUT, Address offset:800-BFF */
+} DMA2D_TypeDef;
+
+/**
+ * @brief Ethernet MAC
+ */
+
+typedef struct
+{
+ __IO uint32_t MACCR;
+ __IO uint32_t MACFFR;
+ __IO uint32_t MACHTHR;
+ __IO uint32_t MACHTLR;
+ __IO uint32_t MACMIIAR;
+ __IO uint32_t MACMIIDR;
+ __IO uint32_t MACFCR;
+ __IO uint32_t MACVLANTR; /* 8 */
+ uint32_t RESERVED0[2];
+ __IO uint32_t MACRWUFFR; /* 11 */
+ __IO uint32_t MACPMTCSR;
+ uint32_t RESERVED1[2];
+ __IO uint32_t MACSR; /* 15 */
+ __IO uint32_t MACIMR;
+ __IO uint32_t MACA0HR;
+ __IO uint32_t MACA0LR;
+ __IO uint32_t MACA1HR;
+ __IO uint32_t MACA1LR;
+ __IO uint32_t MACA2HR;
+ __IO uint32_t MACA2LR;
+ __IO uint32_t MACA3HR;
+ __IO uint32_t MACA3LR; /* 24 */
+ uint32_t RESERVED2[40];
+ __IO uint32_t MMCCR; /* 65 */
+ __IO uint32_t MMCRIR;
+ __IO uint32_t MMCTIR;
+ __IO uint32_t MMCRIMR;
+ __IO uint32_t MMCTIMR; /* 69 */
+ uint32_t RESERVED3[14];
+ __IO uint32_t MMCTGFSCCR; /* 84 */
+ __IO uint32_t MMCTGFMSCCR;
+ uint32_t RESERVED4[5];
+ __IO uint32_t MMCTGFCR;
+ uint32_t RESERVED5[10];
+ __IO uint32_t MMCRFCECR;
+ __IO uint32_t MMCRFAECR;
+ uint32_t RESERVED6[10];
+ __IO uint32_t MMCRGUFCR;
+ uint32_t RESERVED7[334];
+ __IO uint32_t PTPTSCR;
+ __IO uint32_t PTPSSIR;
+ __IO uint32_t PTPTSHR;
+ __IO uint32_t PTPTSLR;
+ __IO uint32_t PTPTSHUR;
+ __IO uint32_t PTPTSLUR;
+ __IO uint32_t PTPTSAR;
+ __IO uint32_t PTPTTHR;
+ __IO uint32_t PTPTTLR;
+ __IO uint32_t RESERVED8;
+ __IO uint32_t PTPTSSR;
+ uint32_t RESERVED9[565];
+ __IO uint32_t DMABMR;
+ __IO uint32_t DMATPDR;
+ __IO uint32_t DMARPDR;
+ __IO uint32_t DMARDLAR;
+ __IO uint32_t DMATDLAR;
+ __IO uint32_t DMASR;
+ __IO uint32_t DMAOMR;
+ __IO uint32_t DMAIER;
+ __IO uint32_t DMAMFBOCR;
+ __IO uint32_t DMARSWTR;
+ uint32_t RESERVED10[8];
+ __IO uint32_t DMACHTDR;
+ __IO uint32_t DMACHRDR;
+ __IO uint32_t DMACHTBAR;
+ __IO uint32_t DMACHRBAR;
+} ETH_TypeDef;
+
+/**
+ * @brief External Interrupt/Event Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t IMR; /*!< EXTI Interrupt mask register, Address offset: 0x00 */
+ __IO uint32_t EMR; /*!< EXTI Event mask register, Address offset: 0x04 */
+ __IO uint32_t RTSR; /*!< EXTI Rising trigger selection register, Address offset: 0x08 */
+ __IO uint32_t FTSR; /*!< EXTI Falling trigger selection register, Address offset: 0x0C */
+ __IO uint32_t SWIER; /*!< EXTI Software interrupt event register, Address offset: 0x10 */
+ __IO uint32_t PR; /*!< EXTI Pending register, Address offset: 0x14 */
+} EXTI_TypeDef;
+
+/**
+ * @brief FLASH Registers
+ */
+
+typedef struct
+{
+ __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */
+ __IO uint32_t KEYR; /*!< FLASH key register, Address offset: 0x04 */
+ __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x08 */
+ __IO uint32_t SR; /*!< FLASH status register, Address offset: 0x0C */
+ __IO uint32_t CR; /*!< FLASH control register, Address offset: 0x10 */
+ __IO uint32_t OPTCR; /*!< FLASH option control register , Address offset: 0x14 */
+ __IO uint32_t OPTCR1; /*!< FLASH option control register 1, Address offset: 0x18 */
+} FLASH_TypeDef;
+
+/**
+ * @brief Flexible Memory Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */
+} FMC_Bank1_TypeDef;
+
+/**
+ * @brief Flexible Memory Controller Bank1E
+ */
+
+typedef struct
+{
+ __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */
+} FMC_Bank1E_TypeDef;
+
+/**
+ * @brief Flexible Memory Controller Bank2
+ */
+
+typedef struct
+{
+ __IO uint32_t PCR2; /*!< NAND Flash control register 2, Address offset: 0x60 */
+ __IO uint32_t SR2; /*!< NAND Flash FIFO status and interrupt register 2, Address offset: 0x64 */
+ __IO uint32_t PMEM2; /*!< NAND Flash Common memory space timing register 2, Address offset: 0x68 */
+ __IO uint32_t PATT2; /*!< NAND Flash Attribute memory space timing register 2, Address offset: 0x6C */
+ uint32_t RESERVED0; /*!< Reserved, 0x70 */
+ __IO uint32_t ECCR2; /*!< NAND Flash ECC result registers 2, Address offset: 0x74 */
+ uint32_t RESERVED1; /*!< Reserved, 0x78 */
+ uint32_t RESERVED2; /*!< Reserved, 0x7C */
+ __IO uint32_t PCR3; /*!< NAND Flash control register 3, Address offset: 0x80 */
+ __IO uint32_t SR3; /*!< NAND Flash FIFO status and interrupt register 3, Address offset: 0x84 */
+ __IO uint32_t PMEM3; /*!< NAND Flash Common memory space timing register 3, Address offset: 0x88 */
+ __IO uint32_t PATT3; /*!< NAND Flash Attribute memory space timing register 3, Address offset: 0x8C */
+ uint32_t RESERVED3; /*!< Reserved, 0x90 */
+ __IO uint32_t ECCR3; /*!< NAND Flash ECC result registers 3, Address offset: 0x94 */
+} FMC_Bank2_3_TypeDef;
+
+/**
+ * @brief Flexible Memory Controller Bank4
+ */
+
+typedef struct
+{
+ __IO uint32_t PCR4; /*!< PC Card control register 4, Address offset: 0xA0 */
+ __IO uint32_t SR4; /*!< PC Card FIFO status and interrupt register 4, Address offset: 0xA4 */
+ __IO uint32_t PMEM4; /*!< PC Card Common memory space timing register 4, Address offset: 0xA8 */
+ __IO uint32_t PATT4; /*!< PC Card Attribute memory space timing register 4, Address offset: 0xAC */
+ __IO uint32_t PIO4; /*!< PC Card I/O space timing register 4, Address offset: 0xB0 */
+} FMC_Bank4_TypeDef;
+
+/**
+ * @brief Flexible Memory Controller Bank5_6
+ */
+
+typedef struct
+{
+ __IO uint32_t SDCR[2]; /*!< SDRAM Control registers , Address offset: 0x140-0x144 */
+ __IO uint32_t SDTR[2]; /*!< SDRAM Timing registers , Address offset: 0x148-0x14C */
+ __IO uint32_t SDCMR; /*!< SDRAM Command Mode register, Address offset: 0x150 */
+ __IO uint32_t SDRTR; /*!< SDRAM Refresh Timer register, Address offset: 0x154 */
+ __IO uint32_t SDSR; /*!< SDRAM Status register, Address offset: 0x158 */
+} FMC_Bank5_6_TypeDef;
+
+/**
+ * @brief General Purpose I/O
+ */
+
+typedef struct
+{
+ __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
+ __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */
+ __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */
+ __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
+ __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
+ __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
+ __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */
+ __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
+ __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */
+} GPIO_TypeDef;
+
+/**
+ * @brief System configuration controller
+ */
+
+typedef struct
+{
+ __IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */
+ __IO uint32_t PMC; /*!< SYSCFG peripheral mode configuration register, Address offset: 0x04 */
+ __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
+ uint32_t RESERVED[2]; /*!< Reserved, 0x18-0x1C */
+ __IO uint32_t CMPCR; /*!< SYSCFG Compensation cell control register, Address offset: 0x20 */
+} SYSCFG_TypeDef;
+
+/**
+ * @brief Inter-integrated Circuit Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */
+ __IO uint32_t OAR1; /*!< I2C Own address register 1, Address offset: 0x08 */
+ __IO uint32_t OAR2; /*!< I2C Own address register 2, Address offset: 0x0C */
+ __IO uint32_t DR; /*!< I2C Data register, Address offset: 0x10 */
+ __IO uint32_t SR1; /*!< I2C Status register 1, Address offset: 0x14 */
+ __IO uint32_t SR2; /*!< I2C Status register 2, Address offset: 0x18 */
+ __IO uint32_t CCR; /*!< I2C Clock control register, Address offset: 0x1C */
+ __IO uint32_t TRISE; /*!< I2C TRISE register, Address offset: 0x20 */
+ __IO uint32_t FLTR; /*!< I2C FLTR register, Address offset: 0x24 */
+} I2C_TypeDef;
+
+/**
+ * @brief Independent WATCHDOG
+ */
+
+typedef struct
+{
+ __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */
+ __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */
+ __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */
+ __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */
+} IWDG_TypeDef;
+
+/**
+ * @brief LCD-TFT Display Controller
+ */
+
+typedef struct
+{
+ uint32_t RESERVED0[2]; /*!< Reserved, 0x00-0x04 */
+ __IO uint32_t SSCR; /*!< LTDC Synchronization Size Configuration Register, Address offset: 0x08 */
+ __IO uint32_t BPCR; /*!< LTDC Back Porch Configuration Register, Address offset: 0x0C */
+ __IO uint32_t AWCR; /*!< LTDC Active Width Configuration Register, Address offset: 0x10 */
+ __IO uint32_t TWCR; /*!< LTDC Total Width Configuration Register, Address offset: 0x14 */
+ __IO uint32_t GCR; /*!< LTDC Global Control Register, Address offset: 0x18 */
+ uint32_t RESERVED1[2]; /*!< Reserved, 0x1C-0x20 */
+ __IO uint32_t SRCR; /*!< LTDC Shadow Reload Configuration Register, Address offset: 0x24 */
+ uint32_t RESERVED2[1]; /*!< Reserved, 0x28 */
+ __IO uint32_t BCCR; /*!< LTDC Background Color Configuration Register, Address offset: 0x2C */
+ uint32_t RESERVED3[1]; /*!< Reserved, 0x30 */
+ __IO uint32_t IER; /*!< LTDC Interrupt Enable Register, Address offset: 0x34 */
+ __IO uint32_t ISR; /*!< LTDC Interrupt Status Register, Address offset: 0x38 */
+ __IO uint32_t ICR; /*!< LTDC Interrupt Clear Register, Address offset: 0x3C */
+ __IO uint32_t LIPCR; /*!< LTDC Line Interrupt Position Configuration Register, Address offset: 0x40 */
+ __IO uint32_t CPSR; /*!< LTDC Current Position Status Register, Address offset: 0x44 */
+ __IO uint32_t CDSR; /*!< LTDC Current Display Status Register, Address offset: 0x48 */
+} LTDC_TypeDef;
+
+/**
+ * @brief LCD-TFT Display layer x Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< LTDC Layerx Control Register Address offset: 0x84 */
+ __IO uint32_t WHPCR; /*!< LTDC Layerx Window Horizontal Position Configuration Register Address offset: 0x88 */
+ __IO uint32_t WVPCR; /*!< LTDC Layerx Window Vertical Position Configuration Register Address offset: 0x8C */
+ __IO uint32_t CKCR; /*!< LTDC Layerx Color Keying Configuration Register Address offset: 0x90 */
+ __IO uint32_t PFCR; /*!< LTDC Layerx Pixel Format Configuration Register Address offset: 0x94 */
+ __IO uint32_t CACR; /*!< LTDC Layerx Constant Alpha Configuration Register Address offset: 0x98 */
+ __IO uint32_t DCCR; /*!< LTDC Layerx Default Color Configuration Register Address offset: 0x9C */
+ __IO uint32_t BFCR; /*!< LTDC Layerx Blending Factors Configuration Register Address offset: 0xA0 */
+ uint32_t RESERVED0[2]; /*!< Reserved */
+ __IO uint32_t CFBAR; /*!< LTDC Layerx Color Frame Buffer Address Register Address offset: 0xAC */
+ __IO uint32_t CFBLR; /*!< LTDC Layerx Color Frame Buffer Length Register Address offset: 0xB0 */
+ __IO uint32_t CFBLNR; /*!< LTDC Layerx ColorFrame Buffer Line Number Register Address offset: 0xB4 */
+ uint32_t RESERVED1[3]; /*!< Reserved */
+ __IO uint32_t CLUTWR; /*!< LTDC Layerx CLUT Write Register Address offset: 0x144 */
+
+} LTDC_Layer_TypeDef;
+
+/**
+ * @brief Power Control
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */
+ __IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */
+} PWR_TypeDef;
+
+/**
+ * @brief Reset and Clock Control
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */
+ __IO uint32_t PLLCFGR; /*!< RCC PLL configuration register, Address offset: 0x04 */
+ __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x08 */
+ __IO uint32_t CIR; /*!< RCC clock interrupt register, Address offset: 0x0C */
+ __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x10 */
+ __IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x14 */
+ __IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0x18 */
+ uint32_t RESERVED0; /*!< Reserved, 0x1C */
+ __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x20 */
+ __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x24 */
+ uint32_t RESERVED1[2]; /*!< Reserved, 0x28-0x2C */
+ __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clock register, Address offset: 0x30 */
+ __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clock register, Address offset: 0x34 */
+ __IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clock register, Address offset: 0x38 */
+ uint32_t RESERVED2; /*!< Reserved, 0x3C */
+ __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x40 */
+ __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x44 */
+ uint32_t RESERVED3[2]; /*!< Reserved, 0x48-0x4C */
+ __IO uint32_t AHB1LPENR; /*!< RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 */
+ __IO uint32_t AHB2LPENR; /*!< RCC AHB2 peripheral clock enable in low power mode register, Address offset: 0x54 */
+ __IO uint32_t AHB3LPENR; /*!< RCC AHB3 peripheral clock enable in low power mode register, Address offset: 0x58 */
+ uint32_t RESERVED4; /*!< Reserved, 0x5C */
+ __IO uint32_t APB1LPENR; /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 */
+ __IO uint32_t APB2LPENR; /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 */
+ uint32_t RESERVED5[2]; /*!< Reserved, 0x68-0x6C */
+ __IO uint32_t BDCR; /*!< RCC Backup domain control register, Address offset: 0x70 */
+ __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x74 */
+ uint32_t RESERVED6[2]; /*!< Reserved, 0x78-0x7C */
+ __IO uint32_t SSCGR; /*!< RCC spread spectrum clock generation register, Address offset: 0x80 */
+ __IO uint32_t PLLI2SCFGR; /*!< RCC PLLI2S configuration register, Address offset: 0x84 */
+ __IO uint32_t PLLSAICFGR; /*!< RCC PLLSAI configuration register, Address offset: 0x88 */
+ __IO uint32_t DCKCFGR; /*!< RCC Dedicated Clocks configuration register, Address offset: 0x8C */
+
+} RCC_TypeDef;
+
+/**
+ * @brief Real-Time Clock
+ */
+
+typedef struct
+{
+ __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
+ __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */
+ __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */
+ __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */
+ __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */
+ __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */
+ __IO uint32_t CALIBR; /*!< RTC calibration register, Address offset: 0x18 */
+ __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */
+ __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */
+ __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */
+ __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */
+ __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */
+ __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */
+ __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */
+ __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */
+ __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */
+ __IO uint32_t TAFCR; /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */
+ __IO uint32_t ALRMASSR;/*!< RTC alarm A sub second register, Address offset: 0x44 */
+ __IO uint32_t ALRMBSSR;/*!< RTC alarm B sub second register, Address offset: 0x48 */
+ uint32_t RESERVED7; /*!< Reserved, 0x4C */
+ __IO uint32_t BKP0R; /*!< RTC backup register 1, Address offset: 0x50 */
+ __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */
+ __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */
+ __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */
+ __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */
+ __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */
+ __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */
+ __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */
+ __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */
+ __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */
+ __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */
+ __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */
+ __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */
+ __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */
+ __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */
+ __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */
+ __IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */
+ __IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */
+ __IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */
+ __IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */
+} RTC_TypeDef;
+
+/**
+ * @brief Serial Audio Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t GCR; /*!< SAI global configuration register, Address offset: 0x00 */
+} SAI_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t CR1; /*!< SAI block x configuration register 1, Address offset: 0x04 */
+ __IO uint32_t CR2; /*!< SAI block x configuration register 2, Address offset: 0x08 */
+ __IO uint32_t FRCR; /*!< SAI block x frame configuration register, Address offset: 0x0C */
+ __IO uint32_t SLOTR; /*!< SAI block x slot register, Address offset: 0x10 */
+ __IO uint32_t IMR; /*!< SAI block x interrupt mask register, Address offset: 0x14 */
+ __IO uint32_t SR; /*!< SAI block x status register, Address offset: 0x18 */
+ __IO uint32_t CLRFR; /*!< SAI block x clear flag register, Address offset: 0x1C */
+ __IO uint32_t DR; /*!< SAI block x data register, Address offset: 0x20 */
+} SAI_Block_TypeDef;
+
+/**
+ * @brief SD host Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t POWER; /*!< SDIO power control register, Address offset: 0x00 */
+ __IO uint32_t CLKCR; /*!< SDI clock control register, Address offset: 0x04 */
+ __IO uint32_t ARG; /*!< SDIO argument register, Address offset: 0x08 */
+ __IO uint32_t CMD; /*!< SDIO command register, Address offset: 0x0C */
+ __I uint32_t RESPCMD; /*!< SDIO command response register, Address offset: 0x10 */
+ __I uint32_t RESP1; /*!< SDIO response 1 register, Address offset: 0x14 */
+ __I uint32_t RESP2; /*!< SDIO response 2 register, Address offset: 0x18 */
+ __I uint32_t RESP3; /*!< SDIO response 3 register, Address offset: 0x1C */
+ __I uint32_t RESP4; /*!< SDIO response 4 register, Address offset: 0x20 */
+ __IO uint32_t DTIMER; /*!< SDIO data timer register, Address offset: 0x24 */
+ __IO uint32_t DLEN; /*!< SDIO data length register, Address offset: 0x28 */
+ __IO uint32_t DCTRL; /*!< SDIO data control register, Address offset: 0x2C */
+ __I uint32_t DCOUNT; /*!< SDIO data counter register, Address offset: 0x30 */
+ __I uint32_t STA; /*!< SDIO status register, Address offset: 0x34 */
+ __IO uint32_t ICR; /*!< SDIO interrupt clear register, Address offset: 0x38 */
+ __IO uint32_t MASK; /*!< SDIO mask register, Address offset: 0x3C */
+ uint32_t RESERVED0[2]; /*!< Reserved, 0x40-0x44 */
+ __I uint32_t FIFOCNT; /*!< SDIO FIFO counter register, Address offset: 0x48 */
+ uint32_t RESERVED1[13]; /*!< Reserved, 0x4C-0x7C */
+ __IO uint32_t FIFO; /*!< SDIO data FIFO register, Address offset: 0x80 */
+} SDIO_TypeDef;
+
+/**
+ * @brief Serial Peripheral Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t CR1; /*!< SPI control register 1 (not used in I2S mode), Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< SPI control register 2, Address offset: 0x04 */
+ __IO uint32_t SR; /*!< SPI status register, Address offset: 0x08 */
+ __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */
+ __IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
+ __IO uint32_t RXCRCR; /*!< SPI RX CRC register (not used in I2S mode), Address offset: 0x14 */
+ __IO uint32_t TXCRCR; /*!< SPI TX CRC register (not used in I2S mode), Address offset: 0x18 */
+ __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */
+ __IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */
+} SPI_TypeDef;
+
+/**
+ * @brief TIM
+ */
+
+typedef struct
+{
+ __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
+ __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */
+ __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
+ __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
+ __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
+ __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
+ __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
+ __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
+ __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
+ __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */
+ __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
+ __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */
+ __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
+ __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
+ __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
+ __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
+ __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
+ __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
+ __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */
+ __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */
+} TIM_TypeDef;
+
+/**
+ * @brief Universal Synchronous Asynchronous Receiver Transmitter
+ */
+
+typedef struct
+{
+ __IO uint32_t SR; /*!< USART Status register, Address offset: 0x00 */
+ __IO uint32_t DR; /*!< USART Data register, Address offset: 0x04 */
+ __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x08 */
+ __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x0C */
+ __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x10 */
+ __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x14 */
+ __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x18 */
+} USART_TypeDef;
+
+/**
+ * @brief Window WATCHDOG
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
+ __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
+ __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
+} WWDG_TypeDef;
+
+/**
+ * @brief Crypto Processor
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< CRYP control register, Address offset: 0x00 */
+ __IO uint32_t SR; /*!< CRYP status register, Address offset: 0x04 */
+ __IO uint32_t DR; /*!< CRYP data input register, Address offset: 0x08 */
+ __IO uint32_t DOUT; /*!< CRYP data output register, Address offset: 0x0C */
+ __IO uint32_t DMACR; /*!< CRYP DMA control register, Address offset: 0x10 */
+ __IO uint32_t IMSCR; /*!< CRYP interrupt mask set/clear register, Address offset: 0x14 */
+ __IO uint32_t RISR; /*!< CRYP raw interrupt status register, Address offset: 0x18 */
+ __IO uint32_t MISR; /*!< CRYP masked interrupt status register, Address offset: 0x1C */
+ __IO uint32_t K0LR; /*!< CRYP key left register 0, Address offset: 0x20 */
+ __IO uint32_t K0RR; /*!< CRYP key right register 0, Address offset: 0x24 */
+ __IO uint32_t K1LR; /*!< CRYP key left register 1, Address offset: 0x28 */
+ __IO uint32_t K1RR; /*!< CRYP key right register 1, Address offset: 0x2C */
+ __IO uint32_t K2LR; /*!< CRYP key left register 2, Address offset: 0x30 */
+ __IO uint32_t K2RR; /*!< CRYP key right register 2, Address offset: 0x34 */
+ __IO uint32_t K3LR; /*!< CRYP key left register 3, Address offset: 0x38 */
+ __IO uint32_t K3RR; /*!< CRYP key right register 3, Address offset: 0x3C */
+ __IO uint32_t IV0LR; /*!< CRYP initialization vector left-word register 0, Address offset: 0x40 */
+ __IO uint32_t IV0RR; /*!< CRYP initialization vector right-word register 0, Address offset: 0x44 */
+ __IO uint32_t IV1LR; /*!< CRYP initialization vector left-word register 1, Address offset: 0x48 */
+ __IO uint32_t IV1RR; /*!< CRYP initialization vector right-word register 1, Address offset: 0x4C */
+ __IO uint32_t CSGCMCCM0R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 0, Address offset: 0x50 */
+ __IO uint32_t CSGCMCCM1R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 1, Address offset: 0x54 */
+ __IO uint32_t CSGCMCCM2R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 2, Address offset: 0x58 */
+ __IO uint32_t CSGCMCCM3R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 3, Address offset: 0x5C */
+ __IO uint32_t CSGCMCCM4R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 4, Address offset: 0x60 */
+ __IO uint32_t CSGCMCCM5R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 5, Address offset: 0x64 */
+ __IO uint32_t CSGCMCCM6R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 6, Address offset: 0x68 */
+ __IO uint32_t CSGCMCCM7R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 7, Address offset: 0x6C */
+ __IO uint32_t CSGCM0R; /*!< CRYP GCM/GMAC context swap register 0, Address offset: 0x70 */
+ __IO uint32_t CSGCM1R; /*!< CRYP GCM/GMAC context swap register 1, Address offset: 0x74 */
+ __IO uint32_t CSGCM2R; /*!< CRYP GCM/GMAC context swap register 2, Address offset: 0x78 */
+ __IO uint32_t CSGCM3R; /*!< CRYP GCM/GMAC context swap register 3, Address offset: 0x7C */
+ __IO uint32_t CSGCM4R; /*!< CRYP GCM/GMAC context swap register 4, Address offset: 0x80 */
+ __IO uint32_t CSGCM5R; /*!< CRYP GCM/GMAC context swap register 5, Address offset: 0x84 */
+ __IO uint32_t CSGCM6R; /*!< CRYP GCM/GMAC context swap register 6, Address offset: 0x88 */
+ __IO uint32_t CSGCM7R; /*!< CRYP GCM/GMAC context swap register 7, Address offset: 0x8C */
+} CRYP_TypeDef;
+
+/**
+ * @brief HASH
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< HASH control register, Address offset: 0x00 */
+ __IO uint32_t DIN; /*!< HASH data input register, Address offset: 0x04 */
+ __IO uint32_t STR; /*!< HASH start register, Address offset: 0x08 */
+ __IO uint32_t HR[5]; /*!< HASH digest registers, Address offset: 0x0C-0x1C */
+ __IO uint32_t IMR; /*!< HASH interrupt enable register, Address offset: 0x20 */
+ __IO uint32_t SR; /*!< HASH status register, Address offset: 0x24 */
+ uint32_t RESERVED[52]; /*!< Reserved, 0x28-0xF4 */
+ __IO uint32_t CSR[54]; /*!< HASH context swap registers, Address offset: 0x0F8-0x1CC */
+} HASH_TypeDef;
+
+/**
+ * @brief HASH_DIGEST
+ */
+
+typedef struct
+{
+ __IO uint32_t HR[8]; /*!< HASH digest registers, Address offset: 0x310-0x32C */
+} HASH_DIGEST_TypeDef;
+
+/**
+ * @brief RNG
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */
+ __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */
+ __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */
+} RNG_TypeDef;
+
+
+/**
+ * @brief __USB_OTG_Core_register
+ */
+typedef struct
+{
+ __IO uint32_t GOTGCTL; /*!< USB_OTG Control and Status Register 000h */
+ __IO uint32_t GOTGINT; /*!< USB_OTG Interrupt Register 004h */
+ __IO uint32_t GAHBCFG; /*!< Core AHB Configuration Register 008h */
+ __IO uint32_t GUSBCFG; /*!< Core USB Configuration Register 00Ch */
+ __IO uint32_t GRSTCTL; /*!< Core Reset Register 010h */
+ __IO uint32_t GINTSTS; /*!< Core Interrupt Register 014h */
+ __IO uint32_t GINTMSK; /*!< Core Interrupt Mask Register 018h */
+ __IO uint32_t GRXSTSR; /*!< Receive Sts Q Read Register 01Ch */
+ __IO uint32_t GRXSTSP; /*!< Receive Sts Q Read & POP Register 020h */
+ __IO uint32_t GRXFSIZ; /* Receive FIFO Size Register 024h */
+ __IO uint32_t DIEPTXF0_HNPTXFSIZ; /*!< EP0 / Non Periodic Tx FIFO Size Register 028h*/
+ __IO uint32_t HNPTXSTS; /*!< Non Periodic Tx FIFO/Queue Sts reg 02Ch */
+ uint32_t Reserved30[2]; /* Reserved 030h*/
+ __IO uint32_t GCCFG; /* General Purpose IO Register 038h*/
+ __IO uint32_t CID; /* User ID Register 03Ch*/
+ uint32_t Reserved40[48]; /* Reserved 040h-0FFh*/
+ __IO uint32_t HPTXFSIZ; /* Host Periodic Tx FIFO Size Reg 100h*/
+ __IO uint32_t DIEPTXF[0x0F];/* dev Periodic Transmit FIFO */
+}
+USB_OTG_GlobalTypeDef;
+
+
+/**
+ * @brief __device_Registers
+ */
+typedef struct
+{
+ __IO uint32_t DCFG; /* dev Configuration Register 800h*/
+ __IO uint32_t DCTL; /* dev Control Register 804h*/
+ __IO uint32_t DSTS; /* dev Status Register (RO) 808h*/
+ uint32_t Reserved0C; /* Reserved 80Ch*/
+ __IO uint32_t DIEPMSK; /* dev IN Endpoint Mask 810h*/
+ __IO uint32_t DOEPMSK; /* dev OUT Endpoint Mask 814h*/
+ __IO uint32_t DAINT; /* dev All Endpoints Itr Reg 818h*/
+ __IO uint32_t DAINTMSK; /* dev All Endpoints Itr Mask 81Ch*/
+ uint32_t Reserved20; /* Reserved 820h*/
+ uint32_t Reserved9; /* Reserved 824h*/
+ __IO uint32_t DVBUSDIS; /* dev VBUS discharge Register 828h*/
+ __IO uint32_t DVBUSPULSE; /* dev VBUS Pulse Register 82Ch*/
+ __IO uint32_t DTHRCTL; /* dev thr 830h*/
+ __IO uint32_t DIEPEMPMSK; /* dev empty msk 834h*/
+ __IO uint32_t DEACHINT; /* dedicated EP interrupt 838h*/
+ __IO uint32_t DEACHMSK; /* dedicated EP msk 83Ch*/
+ uint32_t Reserved40; /* dedicated EP mask 840h*/
+ __IO uint32_t DINEP1MSK; /* dedicated EP mask 844h*/
+ uint32_t Reserved44[15]; /* Reserved 844-87Ch*/
+ __IO uint32_t DOUTEP1MSK; /* dedicated EP msk 884h*/
+}
+USB_OTG_DeviceTypeDef;
+
+
+/**
+ * @brief __IN_Endpoint-Specific_Register
+ */
+typedef struct
+{
+ __IO uint32_t DIEPCTL; /* dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h*/
+ uint32_t Reserved04; /* Reserved 900h + (ep_num * 20h) + 04h*/
+ __IO uint32_t DIEPINT; /* dev IN Endpoint Itr Reg 900h + (ep_num * 20h) + 08h*/
+ uint32_t Reserved0C; /* Reserved 900h + (ep_num * 20h) + 0Ch*/
+ __IO uint32_t DIEPTSIZ; /* IN Endpoint Txfer Size 900h + (ep_num * 20h) + 10h*/
+ __IO uint32_t DIEPDMA; /* IN Endpoint DMA Address Reg 900h + (ep_num * 20h) + 14h*/
+ __IO uint32_t DTXFSTS;/*IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h*/
+ uint32_t Reserved18; /* Reserved 900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch*/
+}
+USB_OTG_INEndpointTypeDef;
+
+
+/**
+ * @brief __OUT_Endpoint-Specific_Registers
+ */
+typedef struct
+{
+ __IO uint32_t DOEPCTL; /* dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h*/
+ uint32_t Reserved04; /* Reserved B00h + (ep_num * 20h) + 04h*/
+ __IO uint32_t DOEPINT; /* dev OUT Endpoint Itr Reg B00h + (ep_num * 20h) + 08h*/
+ uint32_t Reserved0C; /* Reserved B00h + (ep_num * 20h) + 0Ch*/
+ __IO uint32_t DOEPTSIZ; /* dev OUT Endpoint Txfer Size B00h + (ep_num * 20h) + 10h*/
+ __IO uint32_t DOEPDMA; /* dev OUT Endpoint DMA Address B00h + (ep_num * 20h) + 14h*/
+ uint32_t Reserved18[2]; /* Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch*/
+}
+USB_OTG_OUTEndpointTypeDef;
+
+
+/**
+ * @brief __Host_Mode_Register_Structures
+ */
+typedef struct
+{
+ __IO uint32_t HCFG; /* Host Configuration Register 400h*/
+ __IO uint32_t HFIR; /* Host Frame Interval Register 404h*/
+ __IO uint32_t HFNUM; /* Host Frame Nbr/Frame Remaining 408h*/
+ uint32_t Reserved40C; /* Reserved 40Ch*/
+ __IO uint32_t HPTXSTS; /* Host Periodic Tx FIFO/ Queue Status 410h*/
+ __IO uint32_t HAINT; /* Host All Channels Interrupt Register 414h*/
+ __IO uint32_t HAINTMSK; /* Host All Channels Interrupt Mask 418h*/
+}
+USB_OTG_HostTypeDef;
+
+/**
+ * @brief __Host_Channel_Specific_Registers
+ */
+typedef struct
+{
+ __IO uint32_t HCCHAR;
+ __IO uint32_t HCSPLT;
+ __IO uint32_t HCINT;
+ __IO uint32_t HCINTMSK;
+ __IO uint32_t HCTSIZ;
+ __IO uint32_t HCDMA;
+ uint32_t Reserved[2];
+}
+USB_OTG_HostChannelTypeDef;
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_memory_map
+ * @{
+ */
+#define FLASH_BASE 0x08000000U /*!< FLASH(up to 2 MB) base address in the alias region */
+#define CCMDATARAM_BASE 0x10000000U /*!< CCM(core coupled memory) data RAM(64 KB) base address in the alias region */
+#define SRAM1_BASE 0x20000000U /*!< SRAM1(112 KB) base address in the alias region */
+#define SRAM2_BASE 0x2001C000U /*!< SRAM2(16 KB) base address in the alias region */
+#define SRAM3_BASE 0x20020000U /*!< SRAM3(64 KB) base address in the alias region */
+#define PERIPH_BASE 0x40000000U /*!< Peripheral base address in the alias region */
+#define BKPSRAM_BASE 0x40024000U /*!< Backup SRAM(4 KB) base address in the alias region */
+#define FMC_R_BASE 0xA0000000U /*!< FMC registers base address */
+#define SRAM1_BB_BASE 0x22000000U /*!< SRAM1(112 KB) base address in the bit-band region */
+#define SRAM2_BB_BASE 0x22380000U /*!< SRAM2(16 KB) base address in the bit-band region */
+#define SRAM3_BB_BASE 0x22400000U /*!< SRAM3(64 KB) base address in the bit-band region */
+#define PERIPH_BB_BASE 0x42000000U /*!< Peripheral base address in the bit-band region */
+#define BKPSRAM_BB_BASE 0x42480000U /*!< Backup SRAM(4 KB) base address in the bit-band region */
+#define FLASH_END 0x081FFFFFU /*!< FLASH end address */
+#define CCMDATARAM_END 0x1000FFFFU /*!< CCM data RAM end address */
+
+/* Legacy defines */
+#define SRAM_BASE SRAM1_BASE
+#define SRAM_BB_BASE SRAM1_BB_BASE
+
+
+/*!< Peripheral memory map */
+#define APB1PERIPH_BASE PERIPH_BASE
+#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000U)
+#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000U)
+#define AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000U)
+
+/*!< APB1 peripherals */
+#define TIM2_BASE (APB1PERIPH_BASE + 0x0000U)
+#define TIM3_BASE (APB1PERIPH_BASE + 0x0400U)
+#define TIM4_BASE (APB1PERIPH_BASE + 0x0800U)
+#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00U)
+#define TIM6_BASE (APB1PERIPH_BASE + 0x1000U)
+#define TIM7_BASE (APB1PERIPH_BASE + 0x1400U)
+#define TIM12_BASE (APB1PERIPH_BASE + 0x1800U)
+#define TIM13_BASE (APB1PERIPH_BASE + 0x1C00U)
+#define TIM14_BASE (APB1PERIPH_BASE + 0x2000U)
+#define RTC_BASE (APB1PERIPH_BASE + 0x2800U)
+#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00U)
+#define IWDG_BASE (APB1PERIPH_BASE + 0x3000U)
+#define I2S2ext_BASE (APB1PERIPH_BASE + 0x3400U)
+#define SPI2_BASE (APB1PERIPH_BASE + 0x3800U)
+#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00U)
+#define I2S3ext_BASE (APB1PERIPH_BASE + 0x4000U)
+#define USART2_BASE (APB1PERIPH_BASE + 0x4400U)
+#define USART3_BASE (APB1PERIPH_BASE + 0x4800U)
+#define UART4_BASE (APB1PERIPH_BASE + 0x4C00U)
+#define UART5_BASE (APB1PERIPH_BASE + 0x5000U)
+#define I2C1_BASE (APB1PERIPH_BASE + 0x5400U)
+#define I2C2_BASE (APB1PERIPH_BASE + 0x5800U)
+#define I2C3_BASE (APB1PERIPH_BASE + 0x5C00U)
+#define CAN1_BASE (APB1PERIPH_BASE + 0x6400U)
+#define CAN2_BASE (APB1PERIPH_BASE + 0x6800U)
+#define PWR_BASE (APB1PERIPH_BASE + 0x7000U)
+#define DAC_BASE (APB1PERIPH_BASE + 0x7400U)
+#define UART7_BASE (APB1PERIPH_BASE + 0x7800U)
+#define UART8_BASE (APB1PERIPH_BASE + 0x7C00U)
+
+/*!< APB2 peripherals */
+#define TIM1_BASE (APB2PERIPH_BASE + 0x0000U)
+#define TIM8_BASE (APB2PERIPH_BASE + 0x0400U)
+#define USART1_BASE (APB2PERIPH_BASE + 0x1000U)
+#define USART6_BASE (APB2PERIPH_BASE + 0x1400U)
+#define ADC1_BASE (APB2PERIPH_BASE + 0x2000U)
+#define ADC2_BASE (APB2PERIPH_BASE + 0x2100U)
+#define ADC3_BASE (APB2PERIPH_BASE + 0x2200U)
+#define ADC_BASE (APB2PERIPH_BASE + 0x2300U)
+#define SDIO_BASE (APB2PERIPH_BASE + 0x2C00U)
+#define SPI1_BASE (APB2PERIPH_BASE + 0x3000U)
+#define SPI4_BASE (APB2PERIPH_BASE + 0x3400U)
+#define SYSCFG_BASE (APB2PERIPH_BASE + 0x3800U)
+#define EXTI_BASE (APB2PERIPH_BASE + 0x3C00U)
+#define TIM9_BASE (APB2PERIPH_BASE + 0x4000U)
+#define TIM10_BASE (APB2PERIPH_BASE + 0x4400U)
+#define TIM11_BASE (APB2PERIPH_BASE + 0x4800U)
+#define SPI5_BASE (APB2PERIPH_BASE + 0x5000U)
+#define SPI6_BASE (APB2PERIPH_BASE + 0x5400U)
+#define SAI1_BASE (APB2PERIPH_BASE + 0x5800U)
+#define SAI1_Block_A_BASE (SAI1_BASE + 0x004U)
+#define SAI1_Block_B_BASE (SAI1_BASE + 0x024U)
+#define LTDC_BASE (APB2PERIPH_BASE + 0x6800U)
+#define LTDC_Layer1_BASE (LTDC_BASE + 0x84U)
+#define LTDC_Layer2_BASE (LTDC_BASE + 0x104U)
+
+/*!< AHB1 peripherals */
+#define GPIOA_BASE (AHB1PERIPH_BASE + 0x0000U)
+#define GPIOB_BASE (AHB1PERIPH_BASE + 0x0400U)
+#define GPIOC_BASE (AHB1PERIPH_BASE + 0x0800U)
+#define GPIOD_BASE (AHB1PERIPH_BASE + 0x0C00U)
+#define GPIOE_BASE (AHB1PERIPH_BASE + 0x1000U)
+#define GPIOF_BASE (AHB1PERIPH_BASE + 0x1400U)
+#define GPIOG_BASE (AHB1PERIPH_BASE + 0x1800U)
+#define GPIOH_BASE (AHB1PERIPH_BASE + 0x1C00U)
+#define GPIOI_BASE (AHB1PERIPH_BASE + 0x2000U)
+#define GPIOJ_BASE (AHB1PERIPH_BASE + 0x2400U)
+#define GPIOK_BASE (AHB1PERIPH_BASE + 0x2800U)
+#define CRC_BASE (AHB1PERIPH_BASE + 0x3000U)
+#define RCC_BASE (AHB1PERIPH_BASE + 0x3800U)
+#define FLASH_R_BASE (AHB1PERIPH_BASE + 0x3C00U)
+#define DMA1_BASE (AHB1PERIPH_BASE + 0x6000U)
+#define DMA1_Stream0_BASE (DMA1_BASE + 0x010U)
+#define DMA1_Stream1_BASE (DMA1_BASE + 0x028U)
+#define DMA1_Stream2_BASE (DMA1_BASE + 0x040U)
+#define DMA1_Stream3_BASE (DMA1_BASE + 0x058U)
+#define DMA1_Stream4_BASE (DMA1_BASE + 0x070U)
+#define DMA1_Stream5_BASE (DMA1_BASE + 0x088U)
+#define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0U)
+#define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8U)
+#define DMA2_BASE (AHB1PERIPH_BASE + 0x6400U)
+#define DMA2_Stream0_BASE (DMA2_BASE + 0x010U)
+#define DMA2_Stream1_BASE (DMA2_BASE + 0x028U)
+#define DMA2_Stream2_BASE (DMA2_BASE + 0x040U)
+#define DMA2_Stream3_BASE (DMA2_BASE + 0x058U)
+#define DMA2_Stream4_BASE (DMA2_BASE + 0x070U)
+#define DMA2_Stream5_BASE (DMA2_BASE + 0x088U)
+#define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0U)
+#define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8U)
+#define ETH_BASE (AHB1PERIPH_BASE + 0x8000U)
+#define ETH_MAC_BASE (ETH_BASE)
+#define ETH_MMC_BASE (ETH_BASE + 0x0100U)
+#define ETH_PTP_BASE (ETH_BASE + 0x0700U)
+#define ETH_DMA_BASE (ETH_BASE + 0x1000U)
+#define DMA2D_BASE (AHB1PERIPH_BASE + 0xB000U)
+
+/*!< AHB2 peripherals */
+#define DCMI_BASE (AHB2PERIPH_BASE + 0x50000U)
+#define CRYP_BASE (AHB2PERIPH_BASE + 0x60000U)
+#define HASH_BASE (AHB2PERIPH_BASE + 0x60400U)
+#define HASH_DIGEST_BASE (AHB2PERIPH_BASE + 0x60710U)
+#define RNG_BASE (AHB2PERIPH_BASE + 0x60800U)
+
+/*!< FMC Bankx registers base address */
+#define FMC_Bank1_R_BASE (FMC_R_BASE + 0x0000U)
+#define FMC_Bank1E_R_BASE (FMC_R_BASE + 0x0104U)
+#define FMC_Bank2_3_R_BASE (FMC_R_BASE + 0x0060U)
+#define FMC_Bank4_R_BASE (FMC_R_BASE + 0x00A0U)
+#define FMC_Bank5_6_R_BASE (FMC_R_BASE + 0x0140U)
+
+/* Debug MCU registers base address */
+#define DBGMCU_BASE 0xE0042000U
+
+/*!< USB registers base address */
+#define USB_OTG_HS_PERIPH_BASE 0x40040000U
+#define USB_OTG_FS_PERIPH_BASE 0x50000000U
+
+#define USB_OTG_GLOBAL_BASE 0x000U
+#define USB_OTG_DEVICE_BASE 0x800U
+#define USB_OTG_IN_ENDPOINT_BASE 0x900U
+#define USB_OTG_OUT_ENDPOINT_BASE 0xB00U
+#define USB_OTG_EP_REG_SIZE 0x20U
+#define USB_OTG_HOST_BASE 0x400U
+#define USB_OTG_HOST_PORT_BASE 0x440U
+#define USB_OTG_HOST_CHANNEL_BASE 0x500U
+#define USB_OTG_HOST_CHANNEL_SIZE 0x20U
+#define USB_OTG_PCGCCTL_BASE 0xE00U
+#define USB_OTG_FIFO_BASE 0x1000U
+#define USB_OTG_FIFO_SIZE 0x1000U
+
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_declaration
+ * @{
+ */
+#define TIM2 ((TIM_TypeDef *) TIM2_BASE)
+#define TIM3 ((TIM_TypeDef *) TIM3_BASE)
+#define TIM4 ((TIM_TypeDef *) TIM4_BASE)
+#define TIM5 ((TIM_TypeDef *) TIM5_BASE)
+#define TIM6 ((TIM_TypeDef *) TIM6_BASE)
+#define TIM7 ((TIM_TypeDef *) TIM7_BASE)
+#define TIM12 ((TIM_TypeDef *) TIM12_BASE)
+#define TIM13 ((TIM_TypeDef *) TIM13_BASE)
+#define TIM14 ((TIM_TypeDef *) TIM14_BASE)
+#define RTC ((RTC_TypeDef *) RTC_BASE)
+#define WWDG ((WWDG_TypeDef *) WWDG_BASE)
+#define IWDG ((IWDG_TypeDef *) IWDG_BASE)
+#define I2S2ext ((SPI_TypeDef *) I2S2ext_BASE)
+#define SPI2 ((SPI_TypeDef *) SPI2_BASE)
+#define SPI3 ((SPI_TypeDef *) SPI3_BASE)
+#define I2S3ext ((SPI_TypeDef *) I2S3ext_BASE)
+#define USART2 ((USART_TypeDef *) USART2_BASE)
+#define USART3 ((USART_TypeDef *) USART3_BASE)
+#define UART4 ((USART_TypeDef *) UART4_BASE)
+#define UART5 ((USART_TypeDef *) UART5_BASE)
+#define I2C1 ((I2C_TypeDef *) I2C1_BASE)
+#define I2C2 ((I2C_TypeDef *) I2C2_BASE)
+#define I2C3 ((I2C_TypeDef *) I2C3_BASE)
+#define CAN1 ((CAN_TypeDef *) CAN1_BASE)
+#define CAN2 ((CAN_TypeDef *) CAN2_BASE)
+#define PWR ((PWR_TypeDef *) PWR_BASE)
+#define DAC ((DAC_TypeDef *) DAC_BASE)
+#define UART7 ((USART_TypeDef *) UART7_BASE)
+#define UART8 ((USART_TypeDef *) UART8_BASE)
+#define TIM1 ((TIM_TypeDef *) TIM1_BASE)
+#define TIM8 ((TIM_TypeDef *) TIM8_BASE)
+#define USART1 ((USART_TypeDef *) USART1_BASE)
+#define USART6 ((USART_TypeDef *) USART6_BASE)
+#define ADC ((ADC_Common_TypeDef *) ADC_BASE)
+#define ADC1 ((ADC_TypeDef *) ADC1_BASE)
+#define ADC2 ((ADC_TypeDef *) ADC2_BASE)
+#define ADC3 ((ADC_TypeDef *) ADC3_BASE)
+#define SDIO ((SDIO_TypeDef *) SDIO_BASE)
+#define SPI1 ((SPI_TypeDef *) SPI1_BASE)
+#define SPI4 ((SPI_TypeDef *) SPI4_BASE)
+#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
+#define EXTI ((EXTI_TypeDef *) EXTI_BASE)
+#define TIM9 ((TIM_TypeDef *) TIM9_BASE)
+#define TIM10 ((TIM_TypeDef *) TIM10_BASE)
+#define TIM11 ((TIM_TypeDef *) TIM11_BASE)
+#define SPI5 ((SPI_TypeDef *) SPI5_BASE)
+#define SPI6 ((SPI_TypeDef *) SPI6_BASE)
+#define SAI1 ((SAI_TypeDef *) SAI1_BASE)
+#define SAI1_Block_A ((SAI_Block_TypeDef *)SAI1_Block_A_BASE)
+#define SAI1_Block_B ((SAI_Block_TypeDef *)SAI1_Block_B_BASE)
+#define LTDC ((LTDC_TypeDef *)LTDC_BASE)
+#define LTDC_Layer1 ((LTDC_Layer_TypeDef *)LTDC_Layer1_BASE)
+#define LTDC_Layer2 ((LTDC_Layer_TypeDef *)LTDC_Layer2_BASE)
+
+#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
+#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
+#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
+#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
+#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
+#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
+#define GPIOG ((GPIO_TypeDef *) GPIOG_BASE)
+#define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
+#define GPIOI ((GPIO_TypeDef *) GPIOI_BASE)
+#define GPIOJ ((GPIO_TypeDef *) GPIOJ_BASE)
+#define GPIOK ((GPIO_TypeDef *) GPIOK_BASE)
+#define CRC ((CRC_TypeDef *) CRC_BASE)
+#define RCC ((RCC_TypeDef *) RCC_BASE)
+#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
+#define DMA1 ((DMA_TypeDef *) DMA1_BASE)
+#define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)
+#define DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)
+#define DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)
+#define DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)
+#define DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)
+#define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)
+#define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)
+#define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)
+#define DMA2 ((DMA_TypeDef *) DMA2_BASE)
+#define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)
+#define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
+#define DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)
+#define DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)
+#define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)
+#define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)
+#define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)
+#define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)
+#define ETH ((ETH_TypeDef *) ETH_BASE)
+#define DMA2D ((DMA2D_TypeDef *)DMA2D_BASE)
+#define DCMI ((DCMI_TypeDef *) DCMI_BASE)
+#define CRYP ((CRYP_TypeDef *) CRYP_BASE)
+#define HASH ((HASH_TypeDef *) HASH_BASE)
+#define HASH_DIGEST ((HASH_DIGEST_TypeDef *) HASH_DIGEST_BASE)
+#define RNG ((RNG_TypeDef *) RNG_BASE)
+#define FMC_Bank1 ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE)
+#define FMC_Bank1E ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE)
+#define FMC_Bank2_3 ((FMC_Bank2_3_TypeDef *) FMC_Bank2_3_R_BASE)
+#define FMC_Bank4 ((FMC_Bank4_TypeDef *) FMC_Bank4_R_BASE)
+#define FMC_Bank5_6 ((FMC_Bank5_6_TypeDef *) FMC_Bank5_6_R_BASE)
+
+#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
+
+#define USB_OTG_FS ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE)
+#define USB_OTG_HS ((USB_OTG_GlobalTypeDef *) USB_OTG_HS_PERIPH_BASE)
+
+/**
+ * @}
+ */
+
+/** @addtogroup Exported_constants
+ * @{
+ */
+
+ /** @addtogroup Peripheral_Registers_Bits_Definition
+ * @{
+ */
+
+/******************************************************************************/
+/* Peripheral Registers_Bits_Definition */
+/******************************************************************************/
+
+/******************************************************************************/
+/* */
+/* Analog to Digital Converter */
+/* */
+/******************************************************************************/
+/******************** Bit definition for ADC_SR register ********************/
+#define ADC_SR_AWD 0x00000001U /*!<Analog watchdog flag */
+#define ADC_SR_EOC 0x00000002U /*!<End of conversion */
+#define ADC_SR_JEOC 0x00000004U /*!<Injected channel end of conversion */
+#define ADC_SR_JSTRT 0x00000008U /*!<Injected channel Start flag */
+#define ADC_SR_STRT 0x00000010U /*!<Regular channel Start flag */
+#define ADC_SR_OVR 0x00000020U /*!<Overrun flag */
+
+/******************* Bit definition for ADC_CR1 register ********************/
+#define ADC_CR1_AWDCH 0x0000001FU /*!<AWDCH[4:0] bits (Analog watchdog channel select bits) */
+#define ADC_CR1_AWDCH_0 0x00000001U /*!<Bit 0 */
+#define ADC_CR1_AWDCH_1 0x00000002U /*!<Bit 1 */
+#define ADC_CR1_AWDCH_2 0x00000004U /*!<Bit 2 */
+#define ADC_CR1_AWDCH_3 0x00000008U /*!<Bit 3 */
+#define ADC_CR1_AWDCH_4 0x00000010U /*!<Bit 4 */
+#define ADC_CR1_EOCIE 0x00000020U /*!<Interrupt enable for EOC */
+#define ADC_CR1_AWDIE 0x00000040U /*!<AAnalog Watchdog interrupt enable */
+#define ADC_CR1_JEOCIE 0x00000080U /*!<Interrupt enable for injected channels */
+#define ADC_CR1_SCAN 0x00000100U /*!<Scan mode */
+#define ADC_CR1_AWDSGL 0x00000200U /*!<Enable the watchdog on a single channel in scan mode */
+#define ADC_CR1_JAUTO 0x00000400U /*!<Automatic injected group conversion */
+#define ADC_CR1_DISCEN 0x00000800U /*!<Discontinuous mode on regular channels */
+#define ADC_CR1_JDISCEN 0x00001000U /*!<Discontinuous mode on injected channels */
+#define ADC_CR1_DISCNUM 0x0000E000U /*!<DISCNUM[2:0] bits (Discontinuous mode channel count) */
+#define ADC_CR1_DISCNUM_0 0x00002000U /*!<Bit 0 */
+#define ADC_CR1_DISCNUM_1 0x00004000U /*!<Bit 1 */
+#define ADC_CR1_DISCNUM_2 0x00008000U /*!<Bit 2 */
+#define ADC_CR1_JAWDEN 0x00400000U /*!<Analog watchdog enable on injected channels */
+#define ADC_CR1_AWDEN 0x00800000U /*!<Analog watchdog enable on regular channels */
+#define ADC_CR1_RES 0x03000000U /*!<RES[2:0] bits (Resolution) */
+#define ADC_CR1_RES_0 0x01000000U /*!<Bit 0 */
+#define ADC_CR1_RES_1 0x02000000U /*!<Bit 1 */
+#define ADC_CR1_OVRIE 0x04000000U /*!<overrun interrupt enable */
+
+/******************* Bit definition for ADC_CR2 register ********************/
+#define ADC_CR2_ADON 0x00000001U /*!<A/D Converter ON / OFF */
+#define ADC_CR2_CONT 0x00000002U /*!<Continuous Conversion */
+#define ADC_CR2_DMA 0x00000100U /*!<Direct Memory access mode */
+#define ADC_CR2_DDS 0x00000200U /*!<DMA disable selection (Single ADC) */
+#define ADC_CR2_EOCS 0x00000400U /*!<End of conversion selection */
+#define ADC_CR2_ALIGN 0x00000800U /*!<Data Alignment */
+#define ADC_CR2_JEXTSEL 0x000F0000U /*!<JEXTSEL[3:0] bits (External event select for injected group) */
+#define ADC_CR2_JEXTSEL_0 0x00010000U /*!<Bit 0 */
+#define ADC_CR2_JEXTSEL_1 0x00020000U /*!<Bit 1 */
+#define ADC_CR2_JEXTSEL_2 0x00040000U /*!<Bit 2 */
+#define ADC_CR2_JEXTSEL_3 0x00080000U /*!<Bit 3 */
+#define ADC_CR2_JEXTEN 0x00300000U /*!<JEXTEN[1:0] bits (External Trigger Conversion mode for injected channelsp) */
+#define ADC_CR2_JEXTEN_0 0x00100000U /*!<Bit 0 */
+#define ADC_CR2_JEXTEN_1 0x00200000U /*!<Bit 1 */
+#define ADC_CR2_JSWSTART 0x00400000U /*!<Start Conversion of injected channels */
+#define ADC_CR2_EXTSEL 0x0F000000U /*!<EXTSEL[3:0] bits (External Event Select for regular group) */
+#define ADC_CR2_EXTSEL_0 0x01000000U /*!<Bit 0 */
+#define ADC_CR2_EXTSEL_1 0x02000000U /*!<Bit 1 */
+#define ADC_CR2_EXTSEL_2 0x04000000U /*!<Bit 2 */
+#define ADC_CR2_EXTSEL_3 0x08000000U /*!<Bit 3 */
+#define ADC_CR2_EXTEN 0x30000000U /*!<EXTEN[1:0] bits (External Trigger Conversion mode for regular channelsp) */
+#define ADC_CR2_EXTEN_0 0x10000000U /*!<Bit 0 */
+#define ADC_CR2_EXTEN_1 0x20000000U /*!<Bit 1 */
+#define ADC_CR2_SWSTART 0x40000000U /*!<Start Conversion of regular channels */
+
+/****************** Bit definition for ADC_SMPR1 register *******************/
+#define ADC_SMPR1_SMP10 0x00000007U /*!<SMP10[2:0] bits (Channel 10 Sample time selection) */
+#define ADC_SMPR1_SMP10_0 0x00000001U /*!<Bit 0 */
+#define ADC_SMPR1_SMP10_1 0x00000002U /*!<Bit 1 */
+#define ADC_SMPR1_SMP10_2 0x00000004U /*!<Bit 2 */
+#define ADC_SMPR1_SMP11 0x00000038U /*!<SMP11[2:0] bits (Channel 11 Sample time selection) */
+#define ADC_SMPR1_SMP11_0 0x00000008U /*!<Bit 0 */
+#define ADC_SMPR1_SMP11_1 0x00000010U /*!<Bit 1 */
+#define ADC_SMPR1_SMP11_2 0x00000020U /*!<Bit 2 */
+#define ADC_SMPR1_SMP12 0x000001C0U /*!<SMP12[2:0] bits (Channel 12 Sample time selection) */
+#define ADC_SMPR1_SMP12_0 0x00000040U /*!<Bit 0 */
+#define ADC_SMPR1_SMP12_1 0x00000080U /*!<Bit 1 */
+#define ADC_SMPR1_SMP12_2 0x00000100U /*!<Bit 2 */
+#define ADC_SMPR1_SMP13 0x00000E00U /*!<SMP13[2:0] bits (Channel 13 Sample time selection) */
+#define ADC_SMPR1_SMP13_0 0x00000200U /*!<Bit 0 */
+#define ADC_SMPR1_SMP13_1 0x00000400U /*!<Bit 1 */
+#define ADC_SMPR1_SMP13_2 0x00000800U /*!<Bit 2 */
+#define ADC_SMPR1_SMP14 0x00007000U /*!<SMP14[2:0] bits (Channel 14 Sample time selection) */
+#define ADC_SMPR1_SMP14_0 0x00001000U /*!<Bit 0 */
+#define ADC_SMPR1_SMP14_1 0x00002000U /*!<Bit 1 */
+#define ADC_SMPR1_SMP14_2 0x00004000U /*!<Bit 2 */
+#define ADC_SMPR1_SMP15 0x00038000U /*!<SMP15[2:0] bits (Channel 15 Sample time selection) */
+#define ADC_SMPR1_SMP15_0 0x00008000U /*!<Bit 0 */
+#define ADC_SMPR1_SMP15_1 0x00010000U /*!<Bit 1 */
+#define ADC_SMPR1_SMP15_2 0x00020000U /*!<Bit 2 */
+#define ADC_SMPR1_SMP16 0x001C0000U /*!<SMP16[2:0] bits (Channel 16 Sample time selection) */
+#define ADC_SMPR1_SMP16_0 0x00040000U /*!<Bit 0 */
+#define ADC_SMPR1_SMP16_1 0x00080000U /*!<Bit 1 */
+#define ADC_SMPR1_SMP16_2 0x00100000U /*!<Bit 2 */
+#define ADC_SMPR1_SMP17 0x00E00000U /*!<SMP17[2:0] bits (Channel 17 Sample time selection) */
+#define ADC_SMPR1_SMP17_0 0x00200000U /*!<Bit 0 */
+#define ADC_SMPR1_SMP17_1 0x00400000U /*!<Bit 1 */
+#define ADC_SMPR1_SMP17_2 0x00800000U /*!<Bit 2 */
+#define ADC_SMPR1_SMP18 0x07000000U /*!<SMP18[2:0] bits (Channel 18 Sample time selection) */
+#define ADC_SMPR1_SMP18_0 0x01000000U /*!<Bit 0 */
+#define ADC_SMPR1_SMP18_1 0x02000000U /*!<Bit 1 */
+#define ADC_SMPR1_SMP18_2 0x04000000U /*!<Bit 2 */
+
+/****************** Bit definition for ADC_SMPR2 register *******************/
+#define ADC_SMPR2_SMP0 0x00000007U /*!<SMP0[2:0] bits (Channel 0 Sample time selection) */
+#define ADC_SMPR2_SMP0_0 0x00000001U /*!<Bit 0 */
+#define ADC_SMPR2_SMP0_1 0x00000002U /*!<Bit 1 */
+#define ADC_SMPR2_SMP0_2 0x00000004U /*!<Bit 2 */
+#define ADC_SMPR2_SMP1 0x00000038U /*!<SMP1[2:0] bits (Channel 1 Sample time selection) */
+#define ADC_SMPR2_SMP1_0 0x00000008U /*!<Bit 0 */
+#define ADC_SMPR2_SMP1_1 0x00000010U /*!<Bit 1 */
+#define ADC_SMPR2_SMP1_2 0x00000020U /*!<Bit 2 */
+#define ADC_SMPR2_SMP2 0x000001C0U /*!<SMP2[2:0] bits (Channel 2 Sample time selection) */
+#define ADC_SMPR2_SMP2_0 0x00000040U /*!<Bit 0 */
+#define ADC_SMPR2_SMP2_1 0x00000080U /*!<Bit 1 */
+#define ADC_SMPR2_SMP2_2 0x00000100U /*!<Bit 2 */
+#define ADC_SMPR2_SMP3 0x00000E00U /*!<SMP3[2:0] bits (Channel 3 Sample time selection) */
+#define ADC_SMPR2_SMP3_0 0x00000200U /*!<Bit 0 */
+#define ADC_SMPR2_SMP3_1 0x00000400U /*!<Bit 1 */
+#define ADC_SMPR2_SMP3_2 0x00000800U /*!<Bit 2 */
+#define ADC_SMPR2_SMP4 0x00007000U /*!<SMP4[2:0] bits (Channel 4 Sample time selection) */
+#define ADC_SMPR2_SMP4_0 0x00001000U /*!<Bit 0 */
+#define ADC_SMPR2_SMP4_1 0x00002000U /*!<Bit 1 */
+#define ADC_SMPR2_SMP4_2 0x00004000U /*!<Bit 2 */
+#define ADC_SMPR2_SMP5 0x00038000U /*!<SMP5[2:0] bits (Channel 5 Sample time selection) */
+#define ADC_SMPR2_SMP5_0 0x00008000U /*!<Bit 0 */
+#define ADC_SMPR2_SMP5_1 0x00010000U /*!<Bit 1 */
+#define ADC_SMPR2_SMP5_2 0x00020000U /*!<Bit 2 */
+#define ADC_SMPR2_SMP6 0x001C0000U /*!<SMP6[2:0] bits (Channel 6 Sample time selection) */
+#define ADC_SMPR2_SMP6_0 0x00040000U /*!<Bit 0 */
+#define ADC_SMPR2_SMP6_1 0x00080000U /*!<Bit 1 */
+#define ADC_SMPR2_SMP6_2 0x00100000U /*!<Bit 2 */
+#define ADC_SMPR2_SMP7 0x00E00000U /*!<SMP7[2:0] bits (Channel 7 Sample time selection) */
+#define ADC_SMPR2_SMP7_0 0x00200000U /*!<Bit 0 */
+#define ADC_SMPR2_SMP7_1 0x00400000U /*!<Bit 1 */
+#define ADC_SMPR2_SMP7_2 0x00800000U /*!<Bit 2 */
+#define ADC_SMPR2_SMP8 0x07000000U /*!<SMP8[2:0] bits (Channel 8 Sample time selection) */
+#define ADC_SMPR2_SMP8_0 0x01000000U /*!<Bit 0 */
+#define ADC_SMPR2_SMP8_1 0x02000000U /*!<Bit 1 */
+#define ADC_SMPR2_SMP8_2 0x04000000U /*!<Bit 2 */
+#define ADC_SMPR2_SMP9 0x38000000U /*!<SMP9[2:0] bits (Channel 9 Sample time selection) */
+#define ADC_SMPR2_SMP9_0 0x08000000U /*!<Bit 0 */
+#define ADC_SMPR2_SMP9_1 0x10000000U /*!<Bit 1 */
+#define ADC_SMPR2_SMP9_2 0x20000000U /*!<Bit 2 */
+
+/****************** Bit definition for ADC_JOFR1 register *******************/
+#define ADC_JOFR1_JOFFSET1 0x0FFFU /*!<Data offset for injected channel 1 */
+
+/****************** Bit definition for ADC_JOFR2 register *******************/
+#define ADC_JOFR2_JOFFSET2 0x0FFFU /*!<Data offset for injected channel 2 */
+
+/****************** Bit definition for ADC_JOFR3 register *******************/
+#define ADC_JOFR3_JOFFSET3 0x0FFFU /*!<Data offset for injected channel 3 */
+
+/****************** Bit definition for ADC_JOFR4 register *******************/
+#define ADC_JOFR4_JOFFSET4 0x0FFFU /*!<Data offset for injected channel 4 */
+
+/******************* Bit definition for ADC_HTR register ********************/
+#define ADC_HTR_HT 0x0FFFU /*!<Analog watchdog high threshold */
+
+/******************* Bit definition for ADC_LTR register ********************/
+#define ADC_LTR_LT 0x0FFFU /*!<Analog watchdog low threshold */
+
+/******************* Bit definition for ADC_SQR1 register *******************/
+#define ADC_SQR1_SQ13 0x0000001FU /*!<SQ13[4:0] bits (13th conversion in regular sequence) */
+#define ADC_SQR1_SQ13_0 0x00000001U /*!<Bit 0 */
+#define ADC_SQR1_SQ13_1 0x00000002U /*!<Bit 1 */
+#define ADC_SQR1_SQ13_2 0x00000004U /*!<Bit 2 */
+#define ADC_SQR1_SQ13_3 0x00000008U /*!<Bit 3 */
+#define ADC_SQR1_SQ13_4 0x00000010U /*!<Bit 4 */
+#define ADC_SQR1_SQ14 0x000003E0U /*!<SQ14[4:0] bits (14th conversion in regular sequence) */
+#define ADC_SQR1_SQ14_0 0x00000020U /*!<Bit 0 */
+#define ADC_SQR1_SQ14_1 0x00000040U /*!<Bit 1 */
+#define ADC_SQR1_SQ14_2 0x00000080U /*!<Bit 2 */
+#define ADC_SQR1_SQ14_3 0x00000100U /*!<Bit 3 */
+#define ADC_SQR1_SQ14_4 0x00000200U /*!<Bit 4 */
+#define ADC_SQR1_SQ15 0x00007C00U /*!<SQ15[4:0] bits (15th conversion in regular sequence) */
+#define ADC_SQR1_SQ15_0 0x00000400U /*!<Bit 0 */
+#define ADC_SQR1_SQ15_1 0x00000800U /*!<Bit 1 */
+#define ADC_SQR1_SQ15_2 0x00001000U /*!<Bit 2 */
+#define ADC_SQR1_SQ15_3 0x00002000U /*!<Bit 3 */
+#define ADC_SQR1_SQ15_4 0x00004000U /*!<Bit 4 */
+#define ADC_SQR1_SQ16 0x000F8000U /*!<SQ16[4:0] bits (16th conversion in regular sequence) */
+#define ADC_SQR1_SQ16_0 0x00008000U /*!<Bit 0 */
+#define ADC_SQR1_SQ16_1 0x00010000U /*!<Bit 1 */
+#define ADC_SQR1_SQ16_2 0x00020000U /*!<Bit 2 */
+#define ADC_SQR1_SQ16_3 0x00040000U /*!<Bit 3 */
+#define ADC_SQR1_SQ16_4 0x00080000U /*!<Bit 4 */
+#define ADC_SQR1_L 0x00F00000U /*!<L[3:0] bits (Regular channel sequence length) */
+#define ADC_SQR1_L_0 0x00100000U /*!<Bit 0 */
+#define ADC_SQR1_L_1 0x00200000U /*!<Bit 1 */
+#define ADC_SQR1_L_2 0x00400000U /*!<Bit 2 */
+#define ADC_SQR1_L_3 0x00800000U /*!<Bit 3 */
+
+/******************* Bit definition for ADC_SQR2 register *******************/
+#define ADC_SQR2_SQ7 0x0000001FU /*!<SQ7[4:0] bits (7th conversion in regular sequence) */
+#define ADC_SQR2_SQ7_0 0x00000001U /*!<Bit 0 */
+#define ADC_SQR2_SQ7_1 0x00000002U /*!<Bit 1 */
+#define ADC_SQR2_SQ7_2 0x00000004U /*!<Bit 2 */
+#define ADC_SQR2_SQ7_3 0x00000008U /*!<Bit 3 */
+#define ADC_SQR2_SQ7_4 0x00000010U /*!<Bit 4 */
+#define ADC_SQR2_SQ8 0x000003E0U /*!<SQ8[4:0] bits (8th conversion in regular sequence) */
+#define ADC_SQR2_SQ8_0 0x00000020U /*!<Bit 0 */
+#define ADC_SQR2_SQ8_1 0x00000040U /*!<Bit 1 */
+#define ADC_SQR2_SQ8_2 0x00000080U /*!<Bit 2 */
+#define ADC_SQR2_SQ8_3 0x00000100U /*!<Bit 3 */
+#define ADC_SQR2_SQ8_4 0x00000200U /*!<Bit 4 */
+#define ADC_SQR2_SQ9 0x00007C00U /*!<SQ9[4:0] bits (9th conversion in regular sequence) */
+#define ADC_SQR2_SQ9_0 0x00000400U /*!<Bit 0 */
+#define ADC_SQR2_SQ9_1 0x00000800U /*!<Bit 1 */
+#define ADC_SQR2_SQ9_2 0x00001000U /*!<Bit 2 */
+#define ADC_SQR2_SQ9_3 0x00002000U /*!<Bit 3 */
+#define ADC_SQR2_SQ9_4 0x00004000U /*!<Bit 4 */
+#define ADC_SQR2_SQ10 0x000F8000U /*!<SQ10[4:0] bits (10th conversion in regular sequence) */
+#define ADC_SQR2_SQ10_0 0x00008000U /*!<Bit 0 */
+#define ADC_SQR2_SQ10_1 0x00010000U /*!<Bit 1 */
+#define ADC_SQR2_SQ10_2 0x00020000U /*!<Bit 2 */
+#define ADC_SQR2_SQ10_3 0x00040000U /*!<Bit 3 */
+#define ADC_SQR2_SQ10_4 0x00080000U /*!<Bit 4 */
+#define ADC_SQR2_SQ11 0x01F00000U /*!<SQ11[4:0] bits (11th conversion in regular sequence) */
+#define ADC_SQR2_SQ11_0 0x00100000U /*!<Bit 0 */
+#define ADC_SQR2_SQ11_1 0x00200000U /*!<Bit 1 */
+#define ADC_SQR2_SQ11_2 0x00400000U /*!<Bit 2 */
+#define ADC_SQR2_SQ11_3 0x00800000U /*!<Bit 3 */
+#define ADC_SQR2_SQ11_4 0x01000000U /*!<Bit 4 */
+#define ADC_SQR2_SQ12 0x3E000000U /*!<SQ12[4:0] bits (12th conversion in regular sequence) */
+#define ADC_SQR2_SQ12_0 0x02000000U /*!<Bit 0 */
+#define ADC_SQR2_SQ12_1 0x04000000U /*!<Bit 1 */
+#define ADC_SQR2_SQ12_2 0x08000000U /*!<Bit 2 */
+#define ADC_SQR2_SQ12_3 0x10000000U /*!<Bit 3 */
+#define ADC_SQR2_SQ12_4 0x20000000U /*!<Bit 4 */
+
+/******************* Bit definition for ADC_SQR3 register *******************/
+#define ADC_SQR3_SQ1 0x0000001FU /*!<SQ1[4:0] bits (1st conversion in regular sequence) */
+#define ADC_SQR3_SQ1_0 0x00000001U /*!<Bit 0 */
+#define ADC_SQR3_SQ1_1 0x00000002U /*!<Bit 1 */
+#define ADC_SQR3_SQ1_2 0x00000004U /*!<Bit 2 */
+#define ADC_SQR3_SQ1_3 0x00000008U /*!<Bit 3 */
+#define ADC_SQR3_SQ1_4 0x00000010U /*!<Bit 4 */
+#define ADC_SQR3_SQ2 0x000003E0U /*!<SQ2[4:0] bits (2nd conversion in regular sequence) */
+#define ADC_SQR3_SQ2_0 0x00000020U /*!<Bit 0 */
+#define ADC_SQR3_SQ2_1 0x00000040U /*!<Bit 1 */
+#define ADC_SQR3_SQ2_2 0x00000080U /*!<Bit 2 */
+#define ADC_SQR3_SQ2_3 0x00000100U /*!<Bit 3 */
+#define ADC_SQR3_SQ2_4 0x00000200U /*!<Bit 4 */
+#define ADC_SQR3_SQ3 0x00007C00U /*!<SQ3[4:0] bits (3rd conversion in regular sequence) */
+#define ADC_SQR3_SQ3_0 0x00000400U /*!<Bit 0 */
+#define ADC_SQR3_SQ3_1 0x00000800U /*!<Bit 1 */
+#define ADC_SQR3_SQ3_2 0x00001000U /*!<Bit 2 */
+#define ADC_SQR3_SQ3_3 0x00002000U /*!<Bit 3 */
+#define ADC_SQR3_SQ3_4 0x00004000U /*!<Bit 4 */
+#define ADC_SQR3_SQ4 0x000F8000U /*!<SQ4[4:0] bits (4th conversion in regular sequence) */
+#define ADC_SQR3_SQ4_0 0x00008000U /*!<Bit 0 */
+#define ADC_SQR3_SQ4_1 0x00010000U /*!<Bit 1 */
+#define ADC_SQR3_SQ4_2 0x00020000U /*!<Bit 2 */
+#define ADC_SQR3_SQ4_3 0x00040000U /*!<Bit 3 */
+#define ADC_SQR3_SQ4_4 0x00080000U /*!<Bit 4 */
+#define ADC_SQR3_SQ5 0x01F00000U /*!<SQ5[4:0] bits (5th conversion in regular sequence) */
+#define ADC_SQR3_SQ5_0 0x00100000U /*!<Bit 0 */
+#define ADC_SQR3_SQ5_1 0x00200000U /*!<Bit 1 */
+#define ADC_SQR3_SQ5_2 0x00400000U /*!<Bit 2 */
+#define ADC_SQR3_SQ5_3 0x00800000U /*!<Bit 3 */
+#define ADC_SQR3_SQ5_4 0x01000000U /*!<Bit 4 */
+#define ADC_SQR3_SQ6 0x3E000000U /*!<SQ6[4:0] bits (6th conversion in regular sequence) */
+#define ADC_SQR3_SQ6_0 0x02000000U /*!<Bit 0 */
+#define ADC_SQR3_SQ6_1 0x04000000U /*!<Bit 1 */
+#define ADC_SQR3_SQ6_2 0x08000000U /*!<Bit 2 */
+#define ADC_SQR3_SQ6_3 0x10000000U /*!<Bit 3 */
+#define ADC_SQR3_SQ6_4 0x20000000U /*!<Bit 4 */
+
+/******************* Bit definition for ADC_JSQR register *******************/
+#define ADC_JSQR_JSQ1 0x0000001FU /*!<JSQ1[4:0] bits (1st conversion in injected sequence) */
+#define ADC_JSQR_JSQ1_0 0x00000001U /*!<Bit 0 */
+#define ADC_JSQR_JSQ1_1 0x00000002U /*!<Bit 1 */
+#define ADC_JSQR_JSQ1_2 0x00000004U /*!<Bit 2 */
+#define ADC_JSQR_JSQ1_3 0x00000008U /*!<Bit 3 */
+#define ADC_JSQR_JSQ1_4 0x00000010U /*!<Bit 4 */
+#define ADC_JSQR_JSQ2 0x000003E0U /*!<JSQ2[4:0] bits (2nd conversion in injected sequence) */
+#define ADC_JSQR_JSQ2_0 0x00000020U /*!<Bit 0 */
+#define ADC_JSQR_JSQ2_1 0x00000040U /*!<Bit 1 */
+#define ADC_JSQR_JSQ2_2 0x00000080U /*!<Bit 2 */
+#define ADC_JSQR_JSQ2_3 0x00000100U /*!<Bit 3 */
+#define ADC_JSQR_JSQ2_4 0x00000200U /*!<Bit 4 */
+#define ADC_JSQR_JSQ3 0x00007C00U /*!<JSQ3[4:0] bits (3rd conversion in injected sequence) */
+#define ADC_JSQR_JSQ3_0 0x00000400U /*!<Bit 0 */
+#define ADC_JSQR_JSQ3_1 0x00000800U /*!<Bit 1 */
+#define ADC_JSQR_JSQ3_2 0x00001000U /*!<Bit 2 */
+#define ADC_JSQR_JSQ3_3 0x00002000U /*!<Bit 3 */
+#define ADC_JSQR_JSQ3_4 0x00004000U /*!<Bit 4 */
+#define ADC_JSQR_JSQ4 0x000F8000U /*!<JSQ4[4:0] bits (4th conversion in injected sequence) */
+#define ADC_JSQR_JSQ4_0 0x00008000U /*!<Bit 0 */
+#define ADC_JSQR_JSQ4_1 0x00010000U /*!<Bit 1 */
+#define ADC_JSQR_JSQ4_2 0x00020000U /*!<Bit 2 */
+#define ADC_JSQR_JSQ4_3 0x00040000U /*!<Bit 3 */
+#define ADC_JSQR_JSQ4_4 0x00080000U /*!<Bit 4 */
+#define ADC_JSQR_JL 0x00300000U /*!<JL[1:0] bits (Injected Sequence length) */
+#define ADC_JSQR_JL_0 0x00100000U /*!<Bit 0 */
+#define ADC_JSQR_JL_1 0x00200000U /*!<Bit 1 */
+
+/******************* Bit definition for ADC_JDR1 register *******************/
+#define ADC_JDR1_JDATA 0xFFFFU /*!<Injected data */
+
+/******************* Bit definition for ADC_JDR2 register *******************/
+#define ADC_JDR2_JDATA 0xFFFFU /*!<Injected data */
+
+/******************* Bit definition for ADC_JDR3 register *******************/
+#define ADC_JDR3_JDATA 0xFFFFU /*!<Injected data */
+
+/******************* Bit definition for ADC_JDR4 register *******************/
+#define ADC_JDR4_JDATA 0xFFFFU /*!<Injected data */
+
+/******************** Bit definition for ADC_DR register ********************/
+#define ADC_DR_DATA 0x0000FFFFU /*!<Regular data */
+#define ADC_DR_ADC2DATA 0xFFFF0000U /*!<ADC2 data */
+
+/******************* Bit definition for ADC_CSR register ********************/
+#define ADC_CSR_AWD1 0x00000001U /*!<ADC1 Analog watchdog flag */
+#define ADC_CSR_EOC1 0x00000002U /*!<ADC1 End of conversion */
+#define ADC_CSR_JEOC1 0x00000004U /*!<ADC1 Injected channel end of conversion */
+#define ADC_CSR_JSTRT1 0x00000008U /*!<ADC1 Injected channel Start flag */
+#define ADC_CSR_STRT1 0x00000010U /*!<ADC1 Regular channel Start flag */
+#define ADC_CSR_OVR1 0x00000020U /*!<ADC1 DMA overrun flag */
+#define ADC_CSR_AWD2 0x00000100U /*!<ADC2 Analog watchdog flag */
+#define ADC_CSR_EOC2 0x00000200U /*!<ADC2 End of conversion */
+#define ADC_CSR_JEOC2 0x00000400U /*!<ADC2 Injected channel end of conversion */
+#define ADC_CSR_JSTRT2 0x00000800U /*!<ADC2 Injected channel Start flag */
+#define ADC_CSR_STRT2 0x00001000U /*!<ADC2 Regular channel Start flag */
+#define ADC_CSR_OVR2 0x00002000U /*!<ADC2 DMA overrun flag */
+#define ADC_CSR_AWD3 0x00010000U /*!<ADC3 Analog watchdog flag */
+#define ADC_CSR_EOC3 0x00020000U /*!<ADC3 End of conversion */
+#define ADC_CSR_JEOC3 0x00040000U /*!<ADC3 Injected channel end of conversion */
+#define ADC_CSR_JSTRT3 0x00080000U /*!<ADC3 Injected channel Start flag */
+#define ADC_CSR_STRT3 0x00100000U /*!<ADC3 Regular channel Start flag */
+#define ADC_CSR_OVR3 0x00200000U /*!<ADC3 DMA overrun flag */
+
+/* Legacy defines */
+#define ADC_CSR_DOVR1 ADC_CSR_OVR1
+#define ADC_CSR_DOVR2 ADC_CSR_OVR2
+#define ADC_CSR_DOVR3 ADC_CSR_OVR3
+
+/******************* Bit definition for ADC_CCR register ********************/
+#define ADC_CCR_MULTI 0x0000001FU /*!<MULTI[4:0] bits (Multi-ADC mode selection) */
+#define ADC_CCR_MULTI_0 0x00000001U /*!<Bit 0 */
+#define ADC_CCR_MULTI_1 0x00000002U /*!<Bit 1 */
+#define ADC_CCR_MULTI_2 0x00000004U /*!<Bit 2 */
+#define ADC_CCR_MULTI_3 0x00000008U /*!<Bit 3 */
+#define ADC_CCR_MULTI_4 0x00000010U /*!<Bit 4 */
+#define ADC_CCR_DELAY 0x00000F00U /*!<DELAY[3:0] bits (Delay between 2 sampling phases) */
+#define ADC_CCR_DELAY_0 0x00000100U /*!<Bit 0 */
+#define ADC_CCR_DELAY_1 0x00000200U /*!<Bit 1 */
+#define ADC_CCR_DELAY_2 0x00000400U /*!<Bit 2 */
+#define ADC_CCR_DELAY_3 0x00000800U /*!<Bit 3 */
+#define ADC_CCR_DDS 0x00002000U /*!<DMA disable selection (Multi-ADC mode) */
+#define ADC_CCR_DMA 0x0000C000U /*!<DMA[1:0] bits (Direct Memory Access mode for multimode) */
+#define ADC_CCR_DMA_0 0x00004000U /*!<Bit 0 */
+#define ADC_CCR_DMA_1 0x00008000U /*!<Bit 1 */
+#define ADC_CCR_ADCPRE 0x00030000U /*!<ADCPRE[1:0] bits (ADC prescaler) */
+#define ADC_CCR_ADCPRE_0 0x00010000U /*!<Bit 0 */
+#define ADC_CCR_ADCPRE_1 0x00020000U /*!<Bit 1 */
+#define ADC_CCR_VBATE 0x00400000U /*!<VBAT Enable */
+#define ADC_CCR_TSVREFE 0x00800000U /*!<Temperature Sensor and VREFINT Enable */
+
+/******************* Bit definition for ADC_CDR register ********************/
+#define ADC_CDR_DATA1 0x0000FFFFU /*!<1st data of a pair of regular conversions */
+#define ADC_CDR_DATA2 0xFFFF0000U /*!<2nd data of a pair of regular conversions */
+
+/******************************************************************************/
+/* */
+/* Controller Area Network */
+/* */
+/******************************************************************************/
+/*!<CAN control and status registers */
+/******************* Bit definition for CAN_MCR register ********************/
+#define CAN_MCR_INRQ 0x00000001U /*!<Initialization Request */
+#define CAN_MCR_SLEEP 0x00000002U /*!<Sleep Mode Request */
+#define CAN_MCR_TXFP 0x00000004U /*!<Transmit FIFO Priority */
+#define CAN_MCR_RFLM 0x00000008U /*!<Receive FIFO Locked Mode */
+#define CAN_MCR_NART 0x00000010U /*!<No Automatic Retransmission */
+#define CAN_MCR_AWUM 0x00000020U /*!<Automatic Wakeup Mode */
+#define CAN_MCR_ABOM 0x00000040U /*!<Automatic Bus-Off Management */
+#define CAN_MCR_TTCM 0x00000080U /*!<Time Triggered Communication Mode */
+#define CAN_MCR_RESET 0x00008000U /*!<bxCAN software master reset */
+#define CAN_MCR_DBF 0x00010000U /*!<bxCAN Debug freeze */
+/******************* Bit definition for CAN_MSR register ********************/
+#define CAN_MSR_INAK 0x0001U /*!<Initialization Acknowledge */
+#define CAN_MSR_SLAK 0x0002U /*!<Sleep Acknowledge */
+#define CAN_MSR_ERRI 0x0004U /*!<Error Interrupt */
+#define CAN_MSR_WKUI 0x0008U /*!<Wakeup Interrupt */
+#define CAN_MSR_SLAKI 0x0010U /*!<Sleep Acknowledge Interrupt */
+#define CAN_MSR_TXM 0x0100U /*!<Transmit Mode */
+#define CAN_MSR_RXM 0x0200U /*!<Receive Mode */
+#define CAN_MSR_SAMP 0x0400U /*!<Last Sample Point */
+#define CAN_MSR_RX 0x0800U /*!<CAN Rx Signal */
+
+/******************* Bit definition for CAN_TSR register ********************/
+#define CAN_TSR_RQCP0 0x00000001U /*!<Request Completed Mailbox0 */
+#define CAN_TSR_TXOK0 0x00000002U /*!<Transmission OK of Mailbox0 */
+#define CAN_TSR_ALST0 0x00000004U /*!<Arbitration Lost for Mailbox0 */
+#define CAN_TSR_TERR0 0x00000008U /*!<Transmission Error of Mailbox0 */
+#define CAN_TSR_ABRQ0 0x00000080U /*!<Abort Request for Mailbox0 */
+#define CAN_TSR_RQCP1 0x00000100U /*!<Request Completed Mailbox1 */
+#define CAN_TSR_TXOK1 0x00000200U /*!<Transmission OK of Mailbox1 */
+#define CAN_TSR_ALST1 0x00000400U /*!<Arbitration Lost for Mailbox1 */
+#define CAN_TSR_TERR1 0x00000800U /*!<Transmission Error of Mailbox1 */
+#define CAN_TSR_ABRQ1 0x00008000U /*!<Abort Request for Mailbox 1 */
+#define CAN_TSR_RQCP2 0x00010000U /*!<Request Completed Mailbox2 */
+#define CAN_TSR_TXOK2 0x00020000U /*!<Transmission OK of Mailbox 2 */
+#define CAN_TSR_ALST2 0x00040000U /*!<Arbitration Lost for mailbox 2 */
+#define CAN_TSR_TERR2 0x00080000U /*!<Transmission Error of Mailbox 2 */
+#define CAN_TSR_ABRQ2 0x00800000U /*!<Abort Request for Mailbox 2 */
+#define CAN_TSR_CODE 0x03000000U /*!<Mailbox Code */
+
+#define CAN_TSR_TME 0x1C000000U /*!<TME[2:0] bits */
+#define CAN_TSR_TME0 0x04000000U /*!<Transmit Mailbox 0 Empty */
+#define CAN_TSR_TME1 0x08000000U /*!<Transmit Mailbox 1 Empty */
+#define CAN_TSR_TME2 0x10000000U /*!<Transmit Mailbox 2 Empty */
+
+#define CAN_TSR_LOW 0xE0000000U /*!<LOW[2:0] bits */
+#define CAN_TSR_LOW0 0x20000000U /*!<Lowest Priority Flag for Mailbox 0 */
+#define CAN_TSR_LOW1 0x40000000U /*!<Lowest Priority Flag for Mailbox 1 */
+#define CAN_TSR_LOW2 0x80000000U /*!<Lowest Priority Flag for Mailbox 2 */
+
+/******************* Bit definition for CAN_RF0R register *******************/
+#define CAN_RF0R_FMP0 0x03U /*!<FIFO 0 Message Pending */
+#define CAN_RF0R_FULL0 0x08U /*!<FIFO 0 Full */
+#define CAN_RF0R_FOVR0 0x10U /*!<FIFO 0 Overrun */
+#define CAN_RF0R_RFOM0 0x20U /*!<Release FIFO 0 Output Mailbox */
+
+/******************* Bit definition for CAN_RF1R register *******************/
+#define CAN_RF1R_FMP1 0x03U /*!<FIFO 1 Message Pending */
+#define CAN_RF1R_FULL1 0x08U /*!<FIFO 1 Full */
+#define CAN_RF1R_FOVR1 0x10U /*!<FIFO 1 Overrun */
+#define CAN_RF1R_RFOM1 0x20U /*!<Release FIFO 1 Output Mailbox */
+
+/******************** Bit definition for CAN_IER register *******************/
+#define CAN_IER_TMEIE 0x00000001U /*!<Transmit Mailbox Empty Interrupt Enable */
+#define CAN_IER_FMPIE0 0x00000002U /*!<FIFO Message Pending Interrupt Enable */
+#define CAN_IER_FFIE0 0x00000004U /*!<FIFO Full Interrupt Enable */
+#define CAN_IER_FOVIE0 0x00000008U /*!<FIFO Overrun Interrupt Enable */
+#define CAN_IER_FMPIE1 0x00000010U /*!<FIFO Message Pending Interrupt Enable */
+#define CAN_IER_FFIE1 0x00000020U /*!<FIFO Full Interrupt Enable */
+#define CAN_IER_FOVIE1 0x00000040U /*!<FIFO Overrun Interrupt Enable */
+#define CAN_IER_EWGIE 0x00000100U /*!<Error Warning Interrupt Enable */
+#define CAN_IER_EPVIE 0x00000200U /*!<Error Passive Interrupt Enable */
+#define CAN_IER_BOFIE 0x00000400U /*!<Bus-Off Interrupt Enable */
+#define CAN_IER_LECIE 0x00000800U /*!<Last Error Code Interrupt Enable */
+#define CAN_IER_ERRIE 0x00008000U /*!<Error Interrupt Enable */
+#define CAN_IER_WKUIE 0x00010000U /*!<Wakeup Interrupt Enable */
+#define CAN_IER_SLKIE 0x00020000U /*!<Sleep Interrupt Enable */
+#define CAN_IER_EWGIE 0x00000100U /*!<Error warning interrupt enable */
+#define CAN_IER_EPVIE 0x00000200U /*!<Error passive interrupt enable */
+#define CAN_IER_BOFIE 0x00000400U /*!<Bus-off interrupt enable */
+#define CAN_IER_LECIE 0x00000800U /*!<Last error code interrupt enable */
+#define CAN_IER_ERRIE 0x00008000U /*!<Error interrupt enable */
+
+
+/******************** Bit definition for CAN_ESR register *******************/
+#define CAN_ESR_EWGF 0x00000001U /*!<Error Warning Flag */
+#define CAN_ESR_EPVF 0x00000002U /*!<Error Passive Flag */
+#define CAN_ESR_BOFF 0x00000004U /*!<Bus-Off Flag */
+
+#define CAN_ESR_LEC 0x00000070U /*!<LEC[2:0] bits (Last Error Code) */
+#define CAN_ESR_LEC_0 0x00000010U /*!<Bit 0 */
+#define CAN_ESR_LEC_1 0x00000020U /*!<Bit 1 */
+#define CAN_ESR_LEC_2 0x00000040U /*!<Bit 2 */
+
+#define CAN_ESR_TEC 0x00FF0000U /*!<Least significant byte of the 9-bit Transmit Error Counter */
+#define CAN_ESR_REC 0xFF000000U /*!<Receive Error Counter */
+
+/******************* Bit definition for CAN_BTR register ********************/
+#define CAN_BTR_BRP 0x000003FFU /*!<Baud Rate Prescaler */
+#define CAN_BTR_TS1 0x000F0000U /*!<Time Segment 1 */
+#define CAN_BTR_TS1_0 0x00010000U /*!<Bit 0 */
+#define CAN_BTR_TS1_1 0x00020000U /*!<Bit 1 */
+#define CAN_BTR_TS1_2 0x00040000U /*!<Bit 2 */
+#define CAN_BTR_TS1_3 0x00080000U /*!<Bit 3 */
+#define CAN_BTR_TS2 0x00700000U /*!<Time Segment 2 */
+#define CAN_BTR_TS2_0 0x00100000U /*!<Bit 0 */
+#define CAN_BTR_TS2_1 0x00200000U /*!<Bit 1 */
+#define CAN_BTR_TS2_2 0x00400000U /*!<Bit 2 */
+#define CAN_BTR_SJW 0x03000000U /*!<Resynchronization Jump Width */
+#define CAN_BTR_SJW_0 0x01000000U /*!<Bit 0 */
+#define CAN_BTR_SJW_1 0x02000000U /*!<Bit 1 */
+#define CAN_BTR_LBKM 0x40000000U /*!<Loop Back Mode (Debug) */
+#define CAN_BTR_SILM 0x80000000U /*!<Silent Mode */
+
+
+/*!<Mailbox registers */
+/****************** Bit definition for CAN_TI0R register ********************/
+#define CAN_TI0R_TXRQ 0x00000001U /*!<Transmit Mailbox Request */
+#define CAN_TI0R_RTR 0x00000002U /*!<Remote Transmission Request */
+#define CAN_TI0R_IDE 0x00000004U /*!<Identifier Extension */
+#define CAN_TI0R_EXID 0x001FFFF8U /*!<Extended Identifier */
+#define CAN_TI0R_STID 0xFFE00000U /*!<Standard Identifier or Extended Identifier */
+
+/****************** Bit definition for CAN_TDT0R register *******************/
+#define CAN_TDT0R_DLC 0x0000000FU /*!<Data Length Code */
+#define CAN_TDT0R_TGT 0x00000100U /*!<Transmit Global Time */
+#define CAN_TDT0R_TIME 0xFFFF0000U /*!<Message Time Stamp */
+
+/****************** Bit definition for CAN_TDL0R register *******************/
+#define CAN_TDL0R_DATA0 0x000000FFU /*!<Data byte 0 */
+#define CAN_TDL0R_DATA1 0x0000FF00U /*!<Data byte 1 */
+#define CAN_TDL0R_DATA2 0x00FF0000U /*!<Data byte 2 */
+#define CAN_TDL0R_DATA3 0xFF000000U /*!<Data byte 3 */
+
+/****************** Bit definition for CAN_TDH0R register *******************/
+#define CAN_TDH0R_DATA4 0x000000FFU /*!<Data byte 4 */
+#define CAN_TDH0R_DATA5 0x0000FF00U /*!<Data byte 5 */
+#define CAN_TDH0R_DATA6 0x00FF0000U /*!<Data byte 6 */
+#define CAN_TDH0R_DATA7 0xFF000000U /*!<Data byte 7 */
+
+/******************* Bit definition for CAN_TI1R register *******************/
+#define CAN_TI1R_TXRQ 0x00000001U /*!<Transmit Mailbox Request */
+#define CAN_TI1R_RTR 0x00000002U /*!<Remote Transmission Request */
+#define CAN_TI1R_IDE 0x00000004U /*!<Identifier Extension */
+#define CAN_TI1R_EXID 0x001FFFF8U /*!<Extended Identifier */
+#define CAN_TI1R_STID 0xFFE00000U /*!<Standard Identifier or Extended Identifier */
+
+/******************* Bit definition for CAN_TDT1R register ******************/
+#define CAN_TDT1R_DLC 0x0000000FU /*!<Data Length Code */
+#define CAN_TDT1R_TGT 0x00000100U /*!<Transmit Global Time */
+#define CAN_TDT1R_TIME 0xFFFF0000U /*!<Message Time Stamp */
+
+/******************* Bit definition for CAN_TDL1R register ******************/
+#define CAN_TDL1R_DATA0 0x000000FFU /*!<Data byte 0 */
+#define CAN_TDL1R_DATA1 0x0000FF00U /*!<Data byte 1 */
+#define CAN_TDL1R_DATA2 0x00FF0000U /*!<Data byte 2 */
+#define CAN_TDL1R_DATA3 0xFF000000U /*!<Data byte 3 */
+
+/******************* Bit definition for CAN_TDH1R register ******************/
+#define CAN_TDH1R_DATA4 0x000000FFU /*!<Data byte 4 */
+#define CAN_TDH1R_DATA5 0x0000FF00U /*!<Data byte 5 */
+#define CAN_TDH1R_DATA6 0x00FF0000U /*!<Data byte 6 */
+#define CAN_TDH1R_DATA7 0xFF000000U /*!<Data byte 7 */
+
+/******************* Bit definition for CAN_TI2R register *******************/
+#define CAN_TI2R_TXRQ 0x00000001U /*!<Transmit Mailbox Request */
+#define CAN_TI2R_RTR 0x00000002U /*!<Remote Transmission Request */
+#define CAN_TI2R_IDE 0x00000004U /*!<Identifier Extension */
+#define CAN_TI2R_EXID 0x001FFFF8U /*!<Extended identifier */
+#define CAN_TI2R_STID 0xFFE00000U /*!<Standard Identifier or Extended Identifier */
+
+/******************* Bit definition for CAN_TDT2R register ******************/
+#define CAN_TDT2R_DLC 0x0000000FU /*!<Data Length Code */
+#define CAN_TDT2R_TGT 0x00000100U /*!<Transmit Global Time */
+#define CAN_TDT2R_TIME 0xFFFF0000U /*!<Message Time Stamp */
+
+/******************* Bit definition for CAN_TDL2R register ******************/
+#define CAN_TDL2R_DATA0 0x000000FFU /*!<Data byte 0 */
+#define CAN_TDL2R_DATA1 0x0000FF00U /*!<Data byte 1 */
+#define CAN_TDL2R_DATA2 0x00FF0000U /*!<Data byte 2 */
+#define CAN_TDL2R_DATA3 0xFF000000U /*!<Data byte 3 */
+
+/******************* Bit definition for CAN_TDH2R register ******************/
+#define CAN_TDH2R_DATA4 0x000000FFU /*!<Data byte 4 */
+#define CAN_TDH2R_DATA5 0x0000FF00U /*!<Data byte 5 */
+#define CAN_TDH2R_DATA6 0x00FF0000U /*!<Data byte 6 */
+#define CAN_TDH2R_DATA7 0xFF000000U /*!<Data byte 7 */
+
+/******************* Bit definition for CAN_RI0R register *******************/
+#define CAN_RI0R_RTR 0x00000002U /*!<Remote Transmission Request */
+#define CAN_RI0R_IDE 0x00000004U /*!<Identifier Extension */
+#define CAN_RI0R_EXID 0x001FFFF8U /*!<Extended Identifier */
+#define CAN_RI0R_STID 0xFFE00000U /*!<Standard Identifier or Extended Identifier */
+
+/******************* Bit definition for CAN_RDT0R register ******************/
+#define CAN_RDT0R_DLC 0x0000000FU /*!<Data Length Code */
+#define CAN_RDT0R_FMI 0x0000FF00U /*!<Filter Match Index */
+#define CAN_RDT0R_TIME 0xFFFF0000U /*!<Message Time Stamp */
+
+/******************* Bit definition for CAN_RDL0R register ******************/
+#define CAN_RDL0R_DATA0 0x000000FFU /*!<Data byte 0 */
+#define CAN_RDL0R_DATA1 0x0000FF00U /*!<Data byte 1 */
+#define CAN_RDL0R_DATA2 0x00FF0000U /*!<Data byte 2 */
+#define CAN_RDL0R_DATA3 0xFF000000U /*!<Data byte 3 */
+
+/******************* Bit definition for CAN_RDH0R register ******************/
+#define CAN_RDH0R_DATA4 0x000000FFU /*!<Data byte 4 */
+#define CAN_RDH0R_DATA5 0x0000FF00U /*!<Data byte 5 */
+#define CAN_RDH0R_DATA6 0x00FF0000U /*!<Data byte 6 */
+#define CAN_RDH0R_DATA7 0xFF000000U /*!<Data byte 7 */
+
+/******************* Bit definition for CAN_RI1R register *******************/
+#define CAN_RI1R_RTR 0x00000002U /*!<Remote Transmission Request */
+#define CAN_RI1R_IDE 0x00000004U /*!<Identifier Extension */
+#define CAN_RI1R_EXID 0x001FFFF8U /*!<Extended identifier */
+#define CAN_RI1R_STID 0xFFE00000U /*!<Standard Identifier or Extended Identifier */
+
+/******************* Bit definition for CAN_RDT1R register ******************/
+#define CAN_RDT1R_DLC 0x0000000FU /*!<Data Length Code */
+#define CAN_RDT1R_FMI 0x0000FF00U /*!<Filter Match Index */
+#define CAN_RDT1R_TIME 0xFFFF0000U /*!<Message Time Stamp */
+
+/******************* Bit definition for CAN_RDL1R register ******************/
+#define CAN_RDL1R_DATA0 0x000000FFU /*!<Data byte 0 */
+#define CAN_RDL1R_DATA1 0x0000FF00U /*!<Data byte 1 */
+#define CAN_RDL1R_DATA2 0x00FF0000U /*!<Data byte 2 */
+#define CAN_RDL1R_DATA3 0xFF000000U /*!<Data byte 3 */
+
+/******************* Bit definition for CAN_RDH1R register ******************/
+#define CAN_RDH1R_DATA4 0x000000FFU /*!<Data byte 4 */
+#define CAN_RDH1R_DATA5 0x0000FF00U /*!<Data byte 5 */
+#define CAN_RDH1R_DATA6 0x00FF0000U /*!<Data byte 6 */
+#define CAN_RDH1R_DATA7 0xFF000000U /*!<Data byte 7 */
+
+/*!<CAN filter registers */
+/******************* Bit definition for CAN_FMR register ********************/
+#define CAN_FMR_FINIT 0x01U /*!<Filter Init Mode */
+#define CAN_FMR_CAN2SB 0x00003F00U /*!<CAN2 start bank */
+
+/******************* Bit definition for CAN_FM1R register *******************/
+#define CAN_FM1R_FBM 0x0FFFFFFFU /*!<Filter Mode */
+#define CAN_FM1R_FBM0 0x00000001U /*!<Filter Init Mode bit 0 */
+#define CAN_FM1R_FBM1 0x00000002U /*!<Filter Init Mode bit 1 */
+#define CAN_FM1R_FBM2 0x00000004U /*!<Filter Init Mode bit 2 */
+#define CAN_FM1R_FBM3 0x00000008U /*!<Filter Init Mode bit 3 */
+#define CAN_FM1R_FBM4 0x00000010U /*!<Filter Init Mode bit 4 */
+#define CAN_FM1R_FBM5 0x00000020U /*!<Filter Init Mode bit 5 */
+#define CAN_FM1R_FBM6 0x00000040U /*!<Filter Init Mode bit 6 */
+#define CAN_FM1R_FBM7 0x00000080U /*!<Filter Init Mode bit 7 */
+#define CAN_FM1R_FBM8 0x00000100U /*!<Filter Init Mode bit 8 */
+#define CAN_FM1R_FBM9 0x00000200U /*!<Filter Init Mode bit 9 */
+#define CAN_FM1R_FBM10 0x00000400U /*!<Filter Init Mode bit 10 */
+#define CAN_FM1R_FBM11 0x00000800U /*!<Filter Init Mode bit 11 */
+#define CAN_FM1R_FBM12 0x00001000U /*!<Filter Init Mode bit 12 */
+#define CAN_FM1R_FBM13 0x00002000U /*!<Filter Init Mode bit 13 */
+#define CAN_FM1R_FBM14 0x00004000U /*!<Filter Init Mode bit 14 */
+#define CAN_FM1R_FBM15 0x00008000U /*!<Filter Init Mode bit 15 */
+#define CAN_FM1R_FBM16 0x00010000U /*!<Filter Init Mode bit 16 */
+#define CAN_FM1R_FBM17 0x00020000U /*!<Filter Init Mode bit 17 */
+#define CAN_FM1R_FBM18 0x00040000U /*!<Filter Init Mode bit 18 */
+#define CAN_FM1R_FBM19 0x00080000U /*!<Filter Init Mode bit 19 */
+#define CAN_FM1R_FBM20 0x00100000U /*!<Filter Init Mode bit 20 */
+#define CAN_FM1R_FBM21 0x00200000U /*!<Filter Init Mode bit 21 */
+#define CAN_FM1R_FBM22 0x00400000U /*!<Filter Init Mode bit 22 */
+#define CAN_FM1R_FBM23 0x00800000U /*!<Filter Init Mode bit 23 */
+#define CAN_FM1R_FBM24 0x01000000U /*!<Filter Init Mode bit 24 */
+#define CAN_FM1R_FBM25 0x02000000U /*!<Filter Init Mode bit 25 */
+#define CAN_FM1R_FBM26 0x04000000U /*!<Filter Init Mode bit 26 */
+#define CAN_FM1R_FBM27 0x08000000U /*!<Filter Init Mode bit 27 */
+
+/******************* Bit definition for CAN_FS1R register *******************/
+#define CAN_FS1R_FSC 0x0FFFFFFFU /*!<Filter Scale Configuration */
+#define CAN_FS1R_FSC0 0x00000001U /*!<Filter Scale Configuration bit 0 */
+#define CAN_FS1R_FSC1 0x00000002U /*!<Filter Scale Configuration bit 1 */
+#define CAN_FS1R_FSC2 0x00000004U /*!<Filter Scale Configuration bit 2 */
+#define CAN_FS1R_FSC3 0x00000008U /*!<Filter Scale Configuration bit 3 */
+#define CAN_FS1R_FSC4 0x00000010U /*!<Filter Scale Configuration bit 4 */
+#define CAN_FS1R_FSC5 0x00000020U /*!<Filter Scale Configuration bit 5 */
+#define CAN_FS1R_FSC6 0x00000040U /*!<Filter Scale Configuration bit 6 */
+#define CAN_FS1R_FSC7 0x00000080U /*!<Filter Scale Configuration bit 7 */
+#define CAN_FS1R_FSC8 0x00000100U /*!<Filter Scale Configuration bit 8 */
+#define CAN_FS1R_FSC9 0x00000200U /*!<Filter Scale Configuration bit 9 */
+#define CAN_FS1R_FSC10 0x00000400U /*!<Filter Scale Configuration bit 10 */
+#define CAN_FS1R_FSC11 0x00000800U /*!<Filter Scale Configuration bit 11 */
+#define CAN_FS1R_FSC12 0x00001000U /*!<Filter Scale Configuration bit 12 */
+#define CAN_FS1R_FSC13 0x00002000U /*!<Filter Scale Configuration bit 13 */
+#define CAN_FS1R_FSC14 0x00004000U /*!<Filter Scale Configuration bit 14 */
+#define CAN_FS1R_FSC15 0x00008000U /*!<Filter Scale Configuration bit 15 */
+#define CAN_FS1R_FSC16 0x00010000U /*!<Filter Scale Configuration bit 16 */
+#define CAN_FS1R_FSC17 0x00020000U /*!<Filter Scale Configuration bit 17 */
+#define CAN_FS1R_FSC18 0x00040000U /*!<Filter Scale Configuration bit 18 */
+#define CAN_FS1R_FSC19 0x00080000U /*!<Filter Scale Configuration bit 19 */
+#define CAN_FS1R_FSC20 0x00100000U /*!<Filter Scale Configuration bit 20 */
+#define CAN_FS1R_FSC21 0x00200000U /*!<Filter Scale Configuration bit 21 */
+#define CAN_FS1R_FSC22 0x00400000U /*!<Filter Scale Configuration bit 22 */
+#define CAN_FS1R_FSC23 0x00800000U /*!<Filter Scale Configuration bit 23 */
+#define CAN_FS1R_FSC24 0x01000000U /*!<Filter Scale Configuration bit 24 */
+#define CAN_FS1R_FSC25 0x02000000U /*!<Filter Scale Configuration bit 25 */
+#define CAN_FS1R_FSC26 0x04000000U /*!<Filter Scale Configuration bit 26 */
+#define CAN_FS1R_FSC27 0x08000000U /*!<Filter Scale Configuration bit 27 */
+
+/****************** Bit definition for CAN_FFA1R register *******************/
+#define CAN_FFA1R_FFA 0x0FFFFFFFU /*!<Filter FIFO Assignment */
+#define CAN_FFA1R_FFA0 0x00000001U /*!<Filter FIFO Assignment bit 0 */
+#define CAN_FFA1R_FFA1 0x00000002U /*!<Filter FIFO Assignment bit 1 */
+#define CAN_FFA1R_FFA2 0x00000004U /*!<Filter FIFO Assignment bit 2 */
+#define CAN_FFA1R_FFA3 0x00000008U /*!<Filter FIFO Assignment bit 3 */
+#define CAN_FFA1R_FFA4 0x00000010U /*!<Filter FIFO Assignment bit 4 */
+#define CAN_FFA1R_FFA5 0x00000020U /*!<Filter FIFO Assignment bit 5 */
+#define CAN_FFA1R_FFA6 0x00000040U /*!<Filter FIFO Assignment bit 6 */
+#define CAN_FFA1R_FFA7 0x00000080U /*!<Filter FIFO Assignment bit 7 */
+#define CAN_FFA1R_FFA8 0x00000100U /*!<Filter FIFO Assignment bit 8 */
+#define CAN_FFA1R_FFA9 0x00000200U /*!<Filter FIFO Assignment bit 9 */
+#define CAN_FFA1R_FFA10 0x00000400U /*!<Filter FIFO Assignment bit 10 */
+#define CAN_FFA1R_FFA11 0x00000800U /*!<Filter FIFO Assignment bit 11 */
+#define CAN_FFA1R_FFA12 0x00001000U /*!<Filter FIFO Assignment bit 12 */
+#define CAN_FFA1R_FFA13 0x00002000U /*!<Filter FIFO Assignment bit 13 */
+#define CAN_FFA1R_FFA14 0x00004000U /*!<Filter FIFO Assignment bit 14 */
+#define CAN_FFA1R_FFA15 0x00008000U /*!<Filter FIFO Assignment bit 15 */
+#define CAN_FFA1R_FFA16 0x00010000U /*!<Filter FIFO Assignment bit 16 */
+#define CAN_FFA1R_FFA17 0x00020000U /*!<Filter FIFO Assignment bit 17 */
+#define CAN_FFA1R_FFA18 0x00040000U /*!<Filter FIFO Assignment bit 18 */
+#define CAN_FFA1R_FFA19 0x00080000U /*!<Filter FIFO Assignment bit 19 */
+#define CAN_FFA1R_FFA20 0x00100000U /*!<Filter FIFO Assignment bit 20 */
+#define CAN_FFA1R_FFA21 0x00200000U /*!<Filter FIFO Assignment bit 21 */
+#define CAN_FFA1R_FFA22 0x00400000U /*!<Filter FIFO Assignment bit 22 */
+#define CAN_FFA1R_FFA23 0x00800000U /*!<Filter FIFO Assignment bit 23 */
+#define CAN_FFA1R_FFA24 0x01000000U /*!<Filter FIFO Assignment bit 24 */
+#define CAN_FFA1R_FFA25 0x02000000U /*!<Filter FIFO Assignment bit 25 */
+#define CAN_FFA1R_FFA26 0x04000000U /*!<Filter FIFO Assignment bit 26 */
+#define CAN_FFA1R_FFA27 0x08000000U /*!<Filter FIFO Assignment bit 27 */
+
+/******************* Bit definition for CAN_FA1R register *******************/
+#define CAN_FA1R_FACT 0x0FFFFFFFU /*!<Filter Active */
+#define CAN_FA1R_FACT0 0x00000001U /*!<Filter Active bit 0 */
+#define CAN_FA1R_FACT1 0x00000002U /*!<Filter Active bit 1 */
+#define CAN_FA1R_FACT2 0x00000004U /*!<Filter Active bit 2 */
+#define CAN_FA1R_FACT3 0x00000008U /*!<Filter Active bit 3 */
+#define CAN_FA1R_FACT4 0x00000010U /*!<Filter Active bit 4 */
+#define CAN_FA1R_FACT5 0x00000020U /*!<Filter Active bit 5 */
+#define CAN_FA1R_FACT6 0x00000040U /*!<Filter Active bit 6 */
+#define CAN_FA1R_FACT7 0x00000080U /*!<Filter Active bit 7 */
+#define CAN_FA1R_FACT8 0x00000100U /*!<Filter Active bit 8 */
+#define CAN_FA1R_FACT9 0x00000200U /*!<Filter Active bit 9 */
+#define CAN_FA1R_FACT10 0x00000400U /*!<Filter Active bit 10 */
+#define CAN_FA1R_FACT11 0x00000800U /*!<Filter Active bit 11 */
+#define CAN_FA1R_FACT12 0x00001000U /*!<Filter Active bit 12 */
+#define CAN_FA1R_FACT13 0x00002000U /*!<Filter Active bit 13 */
+#define CAN_FA1R_FACT14 0x00004000U /*!<Filter Active bit 14 */
+#define CAN_FA1R_FACT15 0x00008000U /*!<Filter Active bit 15 */
+#define CAN_FA1R_FACT16 0x00010000U /*!<Filter Active bit 16 */
+#define CAN_FA1R_FACT17 0x00020000U /*!<Filter Active bit 17 */
+#define CAN_FA1R_FACT18 0x00040000U /*!<Filter Active bit 18 */
+#define CAN_FA1R_FACT19 0x00080000U /*!<Filter Active bit 19 */
+#define CAN_FA1R_FACT20 0x00100000U /*!<Filter Active bit 20 */
+#define CAN_FA1R_FACT21 0x00200000U /*!<Filter Active bit 21 */
+#define CAN_FA1R_FACT22 0x00400000U /*!<Filter Active bit 22 */
+#define CAN_FA1R_FACT23 0x00800000U /*!<Filter Active bit 23 */
+#define CAN_FA1R_FACT24 0x01000000U /*!<Filter Active bit 24 */
+#define CAN_FA1R_FACT25 0x02000000U /*!<Filter Active bit 25 */
+#define CAN_FA1R_FACT26 0x04000000U /*!<Filter Active bit 26 */
+#define CAN_FA1R_FACT27 0x08000000U /*!<Filter Active bit 27 */
+
+/******************* Bit definition for CAN_F0R1 register *******************/
+#define CAN_F0R1_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F0R1_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F0R1_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F0R1_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F0R1_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F0R1_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F0R1_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F0R1_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F0R1_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F0R1_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F0R1_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F0R1_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F0R1_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F0R1_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F0R1_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F0R1_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F0R1_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F0R1_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F0R1_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F0R1_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F0R1_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F0R1_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F0R1_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F0R1_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F0R1_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F0R1_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F0R1_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F0R1_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F0R1_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F0R1_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F0R1_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F0R1_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F1R1 register *******************/
+#define CAN_F1R1_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F1R1_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F1R1_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F1R1_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F1R1_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F1R1_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F1R1_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F1R1_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F1R1_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F1R1_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F1R1_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F1R1_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F1R1_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F1R1_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F1R1_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F1R1_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F1R1_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F1R1_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F1R1_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F1R1_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F1R1_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F1R1_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F1R1_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F1R1_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F1R1_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F1R1_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F1R1_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F1R1_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F1R1_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F1R1_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F1R1_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F1R1_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F2R1 register *******************/
+#define CAN_F2R1_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F2R1_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F2R1_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F2R1_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F2R1_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F2R1_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F2R1_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F2R1_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F2R1_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F2R1_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F2R1_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F2R1_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F2R1_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F2R1_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F2R1_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F2R1_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F2R1_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F2R1_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F2R1_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F2R1_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F2R1_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F2R1_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F2R1_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F2R1_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F2R1_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F2R1_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F2R1_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F2R1_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F2R1_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F2R1_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F2R1_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F2R1_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F3R1 register *******************/
+#define CAN_F3R1_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F3R1_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F3R1_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F3R1_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F3R1_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F3R1_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F3R1_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F3R1_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F3R1_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F3R1_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F3R1_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F3R1_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F3R1_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F3R1_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F3R1_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F3R1_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F3R1_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F3R1_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F3R1_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F3R1_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F3R1_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F3R1_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F3R1_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F3R1_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F3R1_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F3R1_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F3R1_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F3R1_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F3R1_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F3R1_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F3R1_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F3R1_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F4R1 register *******************/
+#define CAN_F4R1_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F4R1_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F4R1_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F4R1_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F4R1_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F4R1_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F4R1_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F4R1_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F4R1_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F4R1_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F4R1_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F4R1_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F4R1_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F4R1_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F4R1_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F4R1_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F4R1_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F4R1_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F4R1_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F4R1_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F4R1_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F4R1_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F4R1_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F4R1_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F4R1_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F4R1_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F4R1_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F4R1_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F4R1_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F4R1_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F4R1_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F4R1_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F5R1 register *******************/
+#define CAN_F5R1_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F5R1_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F5R1_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F5R1_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F5R1_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F5R1_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F5R1_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F5R1_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F5R1_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F5R1_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F5R1_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F5R1_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F5R1_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F5R1_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F5R1_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F5R1_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F5R1_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F5R1_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F5R1_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F5R1_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F5R1_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F5R1_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F5R1_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F5R1_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F5R1_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F5R1_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F5R1_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F5R1_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F5R1_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F5R1_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F5R1_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F5R1_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F6R1 register *******************/
+#define CAN_F6R1_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F6R1_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F6R1_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F6R1_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F6R1_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F6R1_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F6R1_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F6R1_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F6R1_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F6R1_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F6R1_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F6R1_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F6R1_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F6R1_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F6R1_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F6R1_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F6R1_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F6R1_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F6R1_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F6R1_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F6R1_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F6R1_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F6R1_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F6R1_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F6R1_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F6R1_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F6R1_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F6R1_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F6R1_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F6R1_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F6R1_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F6R1_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F7R1 register *******************/
+#define CAN_F7R1_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F7R1_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F7R1_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F7R1_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F7R1_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F7R1_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F7R1_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F7R1_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F7R1_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F7R1_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F7R1_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F7R1_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F7R1_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F7R1_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F7R1_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F7R1_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F7R1_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F7R1_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F7R1_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F7R1_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F7R1_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F7R1_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F7R1_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F7R1_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F7R1_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F7R1_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F7R1_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F7R1_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F7R1_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F7R1_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F7R1_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F7R1_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F8R1 register *******************/
+#define CAN_F8R1_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F8R1_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F8R1_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F8R1_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F8R1_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F8R1_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F8R1_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F8R1_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F8R1_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F8R1_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F8R1_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F8R1_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F8R1_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F8R1_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F8R1_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F8R1_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F8R1_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F8R1_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F8R1_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F8R1_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F8R1_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F8R1_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F8R1_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F8R1_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F8R1_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F8R1_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F8R1_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F8R1_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F8R1_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F8R1_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F8R1_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F8R1_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F9R1 register *******************/
+#define CAN_F9R1_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F9R1_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F9R1_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F9R1_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F9R1_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F9R1_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F9R1_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F9R1_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F9R1_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F9R1_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F9R1_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F9R1_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F9R1_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F9R1_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F9R1_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F9R1_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F9R1_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F9R1_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F9R1_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F9R1_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F9R1_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F9R1_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F9R1_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F9R1_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F9R1_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F9R1_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F9R1_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F9R1_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F9R1_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F9R1_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F9R1_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F9R1_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F10R1 register ******************/
+#define CAN_F10R1_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F10R1_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F10R1_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F10R1_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F10R1_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F10R1_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F10R1_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F10R1_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F10R1_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F10R1_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F10R1_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F10R1_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F10R1_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F10R1_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F10R1_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F10R1_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F10R1_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F10R1_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F10R1_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F10R1_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F10R1_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F10R1_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F10R1_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F10R1_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F10R1_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F10R1_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F10R1_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F10R1_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F10R1_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F10R1_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F10R1_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F10R1_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F11R1 register ******************/
+#define CAN_F11R1_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F11R1_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F11R1_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F11R1_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F11R1_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F11R1_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F11R1_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F11R1_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F11R1_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F11R1_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F11R1_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F11R1_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F11R1_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F11R1_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F11R1_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F11R1_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F11R1_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F11R1_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F11R1_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F11R1_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F11R1_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F11R1_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F11R1_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F11R1_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F11R1_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F11R1_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F11R1_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F11R1_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F11R1_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F11R1_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F11R1_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F11R1_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F12R1 register ******************/
+#define CAN_F12R1_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F12R1_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F12R1_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F12R1_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F12R1_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F12R1_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F12R1_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F12R1_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F12R1_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F12R1_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F12R1_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F12R1_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F12R1_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F12R1_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F12R1_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F12R1_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F12R1_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F12R1_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F12R1_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F12R1_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F12R1_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F12R1_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F12R1_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F12R1_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F12R1_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F12R1_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F12R1_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F12R1_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F12R1_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F12R1_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F12R1_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F12R1_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F13R1 register ******************/
+#define CAN_F13R1_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F13R1_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F13R1_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F13R1_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F13R1_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F13R1_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F13R1_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F13R1_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F13R1_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F13R1_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F13R1_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F13R1_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F13R1_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F13R1_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F13R1_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F13R1_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F13R1_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F13R1_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F13R1_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F13R1_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F13R1_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F13R1_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F13R1_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F13R1_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F13R1_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F13R1_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F13R1_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F13R1_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F13R1_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F13R1_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F13R1_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F13R1_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F0R2 register *******************/
+#define CAN_F0R2_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F0R2_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F0R2_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F0R2_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F0R2_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F0R2_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F0R2_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F0R2_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F0R2_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F0R2_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F0R2_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F0R2_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F0R2_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F0R2_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F0R2_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F0R2_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F0R2_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F0R2_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F0R2_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F0R2_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F0R2_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F0R2_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F0R2_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F0R2_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F0R2_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F0R2_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F0R2_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F0R2_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F0R2_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F0R2_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F0R2_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F0R2_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F1R2 register *******************/
+#define CAN_F1R2_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F1R2_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F1R2_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F1R2_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F1R2_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F1R2_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F1R2_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F1R2_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F1R2_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F1R2_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F1R2_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F1R2_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F1R2_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F1R2_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F1R2_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F1R2_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F1R2_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F1R2_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F1R2_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F1R2_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F1R2_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F1R2_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F1R2_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F1R2_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F1R2_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F1R2_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F1R2_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F1R2_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F1R2_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F1R2_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F1R2_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F1R2_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F2R2 register *******************/
+#define CAN_F2R2_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F2R2_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F2R2_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F2R2_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F2R2_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F2R2_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F2R2_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F2R2_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F2R2_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F2R2_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F2R2_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F2R2_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F2R2_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F2R2_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F2R2_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F2R2_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F2R2_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F2R2_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F2R2_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F2R2_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F2R2_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F2R2_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F2R2_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F2R2_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F2R2_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F2R2_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F2R2_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F2R2_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F2R2_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F2R2_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F2R2_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F2R2_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F3R2 register *******************/
+#define CAN_F3R2_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F3R2_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F3R2_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F3R2_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F3R2_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F3R2_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F3R2_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F3R2_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F3R2_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F3R2_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F3R2_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F3R2_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F3R2_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F3R2_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F3R2_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F3R2_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F3R2_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F3R2_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F3R2_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F3R2_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F3R2_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F3R2_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F3R2_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F3R2_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F3R2_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F3R2_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F3R2_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F3R2_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F3R2_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F3R2_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F3R2_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F3R2_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F4R2 register *******************/
+#define CAN_F4R2_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F4R2_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F4R2_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F4R2_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F4R2_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F4R2_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F4R2_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F4R2_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F4R2_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F4R2_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F4R2_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F4R2_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F4R2_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F4R2_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F4R2_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F4R2_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F4R2_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F4R2_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F4R2_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F4R2_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F4R2_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F4R2_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F4R2_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F4R2_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F4R2_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F4R2_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F4R2_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F4R2_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F4R2_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F4R2_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F4R2_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F4R2_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F5R2 register *******************/
+#define CAN_F5R2_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F5R2_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F5R2_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F5R2_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F5R2_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F5R2_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F5R2_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F5R2_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F5R2_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F5R2_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F5R2_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F5R2_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F5R2_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F5R2_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F5R2_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F5R2_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F5R2_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F5R2_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F5R2_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F5R2_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F5R2_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F5R2_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F5R2_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F5R2_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F5R2_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F5R2_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F5R2_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F5R2_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F5R2_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F5R2_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F5R2_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F5R2_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F6R2 register *******************/
+#define CAN_F6R2_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F6R2_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F6R2_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F6R2_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F6R2_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F6R2_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F6R2_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F6R2_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F6R2_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F6R2_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F6R2_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F6R2_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F6R2_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F6R2_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F6R2_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F6R2_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F6R2_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F6R2_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F6R2_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F6R2_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F6R2_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F6R2_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F6R2_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F6R2_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F6R2_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F6R2_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F6R2_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F6R2_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F6R2_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F6R2_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F6R2_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F6R2_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F7R2 register *******************/
+#define CAN_F7R2_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F7R2_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F7R2_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F7R2_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F7R2_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F7R2_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F7R2_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F7R2_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F7R2_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F7R2_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F7R2_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F7R2_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F7R2_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F7R2_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F7R2_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F7R2_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F7R2_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F7R2_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F7R2_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F7R2_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F7R2_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F7R2_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F7R2_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F7R2_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F7R2_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F7R2_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F7R2_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F7R2_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F7R2_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F7R2_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F7R2_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F7R2_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F8R2 register *******************/
+#define CAN_F8R2_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F8R2_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F8R2_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F8R2_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F8R2_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F8R2_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F8R2_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F8R2_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F8R2_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F8R2_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F8R2_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F8R2_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F8R2_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F8R2_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F8R2_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F8R2_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F8R2_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F8R2_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F8R2_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F8R2_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F8R2_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F8R2_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F8R2_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F8R2_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F8R2_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F8R2_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F8R2_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F8R2_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F8R2_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F8R2_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F8R2_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F8R2_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F9R2 register *******************/
+#define CAN_F9R2_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F9R2_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F9R2_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F9R2_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F9R2_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F9R2_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F9R2_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F9R2_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F9R2_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F9R2_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F9R2_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F9R2_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F9R2_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F9R2_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F9R2_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F9R2_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F9R2_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F9R2_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F9R2_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F9R2_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F9R2_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F9R2_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F9R2_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F9R2_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F9R2_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F9R2_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F9R2_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F9R2_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F9R2_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F9R2_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F9R2_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F9R2_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F10R2 register ******************/
+#define CAN_F10R2_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F10R2_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F10R2_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F10R2_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F10R2_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F10R2_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F10R2_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F10R2_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F10R2_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F10R2_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F10R2_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F10R2_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F10R2_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F10R2_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F10R2_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F10R2_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F10R2_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F10R2_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F10R2_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F10R2_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F10R2_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F10R2_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F10R2_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F10R2_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F10R2_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F10R2_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F10R2_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F10R2_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F10R2_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F10R2_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F10R2_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F10R2_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F11R2 register ******************/
+#define CAN_F11R2_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F11R2_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F11R2_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F11R2_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F11R2_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F11R2_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F11R2_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F11R2_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F11R2_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F11R2_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F11R2_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F11R2_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F11R2_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F11R2_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F11R2_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F11R2_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F11R2_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F11R2_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F11R2_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F11R2_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F11R2_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F11R2_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F11R2_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F11R2_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F11R2_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F11R2_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F11R2_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F11R2_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F11R2_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F11R2_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F11R2_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F11R2_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F12R2 register ******************/
+#define CAN_F12R2_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F12R2_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F12R2_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F12R2_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F12R2_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F12R2_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F12R2_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F12R2_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F12R2_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F12R2_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F12R2_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F12R2_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F12R2_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F12R2_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F12R2_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F12R2_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F12R2_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F12R2_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F12R2_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F12R2_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F12R2_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F12R2_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F12R2_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F12R2_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F12R2_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F12R2_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F12R2_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F12R2_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F12R2_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F12R2_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F12R2_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F12R2_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F13R2 register ******************/
+#define CAN_F13R2_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F13R2_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F13R2_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F13R2_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F13R2_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F13R2_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F13R2_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F13R2_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F13R2_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F13R2_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F13R2_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F13R2_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F13R2_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F13R2_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F13R2_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F13R2_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F13R2_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F13R2_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F13R2_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F13R2_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F13R2_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F13R2_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F13R2_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F13R2_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F13R2_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F13R2_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F13R2_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F13R2_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F13R2_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F13R2_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F13R2_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F13R2_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************************************************************************/
+/* */
+/* CRC calculation unit */
+/* */
+/******************************************************************************/
+/******************* Bit definition for CRC_DR register *********************/
+#define CRC_DR_DR 0xFFFFFFFFU /*!< Data register bits */
+
+
+/******************* Bit definition for CRC_IDR register ********************/
+#define CRC_IDR_IDR 0xFFU /*!< General-purpose 8-bit data register bits */
+
+
+/******************** Bit definition for CRC_CR register ********************/
+#define CRC_CR_RESET 0x01U /*!< RESET bit */
+
+/******************************************************************************/
+/* */
+/* Crypto Processor */
+/* */
+/******************************************************************************/
+/******************* Bits definition for CRYP_CR register ********************/
+#define CRYP_CR_ALGODIR 0x00000004U
+
+#define CRYP_CR_ALGOMODE 0x00080038U
+#define CRYP_CR_ALGOMODE_0 0x00000008U
+#define CRYP_CR_ALGOMODE_1 0x00000010U
+#define CRYP_CR_ALGOMODE_2 0x00000020U
+#define CRYP_CR_ALGOMODE_TDES_ECB 0x00000000U
+#define CRYP_CR_ALGOMODE_TDES_CBC 0x00000008U
+#define CRYP_CR_ALGOMODE_DES_ECB 0x00000010U
+#define CRYP_CR_ALGOMODE_DES_CBC 0x00000018U
+#define CRYP_CR_ALGOMODE_AES_ECB 0x00000020U
+#define CRYP_CR_ALGOMODE_AES_CBC 0x00000028U
+#define CRYP_CR_ALGOMODE_AES_CTR 0x00000030U
+#define CRYP_CR_ALGOMODE_AES_KEY 0x00000038U
+
+#define CRYP_CR_DATATYPE 0x000000C0U
+#define CRYP_CR_DATATYPE_0 0x00000040U
+#define CRYP_CR_DATATYPE_1 0x00000080U
+#define CRYP_CR_KEYSIZE 0x00000300U
+#define CRYP_CR_KEYSIZE_0 0x00000100U
+#define CRYP_CR_KEYSIZE_1 0x00000200U
+#define CRYP_CR_FFLUSH 0x00004000U
+#define CRYP_CR_CRYPEN 0x00008000U
+
+#define CRYP_CR_GCM_CCMPH 0x00030000U
+#define CRYP_CR_GCM_CCMPH_0 0x00010000U
+#define CRYP_CR_GCM_CCMPH_1 0x00020000U
+#define CRYP_CR_ALGOMODE_3 0x00080000U
+
+/****************** Bits definition for CRYP_SR register *********************/
+#define CRYP_SR_IFEM 0x00000001U
+#define CRYP_SR_IFNF 0x00000002U
+#define CRYP_SR_OFNE 0x00000004U
+#define CRYP_SR_OFFU 0x00000008U
+#define CRYP_SR_BUSY 0x00000010U
+/****************** Bits definition for CRYP_DMACR register ******************/
+#define CRYP_DMACR_DIEN 0x00000001U
+#define CRYP_DMACR_DOEN 0x00000002U
+/***************** Bits definition for CRYP_IMSCR register ******************/
+#define CRYP_IMSCR_INIM 0x00000001U
+#define CRYP_IMSCR_OUTIM 0x00000002U
+/****************** Bits definition for CRYP_RISR register *******************/
+#define CRYP_RISR_OUTRIS 0x00000001U
+#define CRYP_RISR_INRIS 0x00000002U
+/****************** Bits definition for CRYP_MISR register *******************/
+#define CRYP_MISR_INMIS 0x00000001U
+#define CRYP_MISR_OUTMIS 0x00000002U
+
+/******************************************************************************/
+/* */
+/* Digital to Analog Converter */
+/* */
+/******************************************************************************/
+/******************** Bit definition for DAC_CR register ********************/
+#define DAC_CR_EN1 0x00000001U /*!<DAC channel1 enable */
+#define DAC_CR_BOFF1 0x00000002U /*!<DAC channel1 output buffer disable */
+#define DAC_CR_TEN1 0x00000004U /*!<DAC channel1 Trigger enable */
+
+#define DAC_CR_TSEL1 0x00000038U /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */
+#define DAC_CR_TSEL1_0 0x00000008U /*!<Bit 0 */
+#define DAC_CR_TSEL1_1 0x00000010U /*!<Bit 1 */
+#define DAC_CR_TSEL1_2 0x00000020U /*!<Bit 2 */
+
+#define DAC_CR_WAVE1 0x000000C0U /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
+#define DAC_CR_WAVE1_0 0x00000040U /*!<Bit 0 */
+#define DAC_CR_WAVE1_1 0x00000080U /*!<Bit 1 */
+
+#define DAC_CR_MAMP1 0x00000F00U /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
+#define DAC_CR_MAMP1_0 0x00000100U /*!<Bit 0 */
+#define DAC_CR_MAMP1_1 0x00000200U /*!<Bit 1 */
+#define DAC_CR_MAMP1_2 0x00000400U /*!<Bit 2 */
+#define DAC_CR_MAMP1_3 0x00000800U /*!<Bit 3 */
+
+#define DAC_CR_DMAEN1 0x00001000U /*!<DAC channel1 DMA enable */
+#define DAC_CR_DMAUDRIE1 0x00002000U /*!<DAC channel1 DMA underrun interrupt enable*/
+#define DAC_CR_EN2 0x00010000U /*!<DAC channel2 enable */
+#define DAC_CR_BOFF2 0x00020000U /*!<DAC channel2 output buffer disable */
+#define DAC_CR_TEN2 0x00040000U /*!<DAC channel2 Trigger enable */
+
+#define DAC_CR_TSEL2 0x00380000U /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */
+#define DAC_CR_TSEL2_0 0x00080000U /*!<Bit 0 */
+#define DAC_CR_TSEL2_1 0x00100000U /*!<Bit 1 */
+#define DAC_CR_TSEL2_2 0x00200000U /*!<Bit 2 */
+
+#define DAC_CR_WAVE2 0x00C00000U /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
+#define DAC_CR_WAVE2_0 0x00400000U /*!<Bit 0 */
+#define DAC_CR_WAVE2_1 0x00800000U /*!<Bit 1 */
+
+#define DAC_CR_MAMP2 0x0F000000U /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
+#define DAC_CR_MAMP2_0 0x01000000U /*!<Bit 0 */
+#define DAC_CR_MAMP2_1 0x02000000U /*!<Bit 1 */
+#define DAC_CR_MAMP2_2 0x04000000U /*!<Bit 2 */
+#define DAC_CR_MAMP2_3 0x08000000U /*!<Bit 3 */
+
+#define DAC_CR_DMAEN2 0x10000000U /*!<DAC channel2 DMA enabled */
+#define DAC_CR_DMAUDRIE2 0x20000000U /*!<DAC channel2 DMA underrun interrupt enable*/
+
+/***************** Bit definition for DAC_SWTRIGR register ******************/
+#define DAC_SWTRIGR_SWTRIG1 0x01U /*!<DAC channel1 software trigger */
+#define DAC_SWTRIGR_SWTRIG2 0x02U /*!<DAC channel2 software trigger */
+
+/***************** Bit definition for DAC_DHR12R1 register ******************/
+#define DAC_DHR12R1_DACC1DHR 0x0FFFU /*!<DAC channel1 12-bit Right aligned data */
+
+/***************** Bit definition for DAC_DHR12L1 register ******************/
+#define DAC_DHR12L1_DACC1DHR 0xFFF0U /*!<DAC channel1 12-bit Left aligned data */
+
+/****************** Bit definition for DAC_DHR8R1 register ******************/
+#define DAC_DHR8R1_DACC1DHR 0xFFU /*!<DAC channel1 8-bit Right aligned data */
+
+/***************** Bit definition for DAC_DHR12R2 register ******************/
+#define DAC_DHR12R2_DACC2DHR 0x0FFFU /*!<DAC channel2 12-bit Right aligned data */
+
+/***************** Bit definition for DAC_DHR12L2 register ******************/
+#define DAC_DHR12L2_DACC2DHR 0xFFF0U /*!<DAC channel2 12-bit Left aligned data */
+
+/****************** Bit definition for DAC_DHR8R2 register ******************/
+#define DAC_DHR8R2_DACC2DHR 0xFFU /*!<DAC channel2 8-bit Right aligned data */
+
+/***************** Bit definition for DAC_DHR12RD register ******************/
+#define DAC_DHR12RD_DACC1DHR 0x00000FFFU /*!<DAC channel1 12-bit Right aligned data */
+#define DAC_DHR12RD_DACC2DHR 0x0FFF0000U /*!<DAC channel2 12-bit Right aligned data */
+
+/***************** Bit definition for DAC_DHR12LD register ******************/
+#define DAC_DHR12LD_DACC1DHR 0x0000FFF0U /*!<DAC channel1 12-bit Left aligned data */
+#define DAC_DHR12LD_DACC2DHR 0xFFF00000U /*!<DAC channel2 12-bit Left aligned data */
+
+/****************** Bit definition for DAC_DHR8RD register ******************/
+#define DAC_DHR8RD_DACC1DHR 0x00FFU /*!<DAC channel1 8-bit Right aligned data */
+#define DAC_DHR8RD_DACC2DHR 0xFF00U /*!<DAC channel2 8-bit Right aligned data */
+
+/******************* Bit definition for DAC_DOR1 register *******************/
+#define DAC_DOR1_DACC1DOR 0x0FFFU /*!<DAC channel1 data output */
+
+/******************* Bit definition for DAC_DOR2 register *******************/
+#define DAC_DOR2_DACC2DOR 0x0FFFU /*!<DAC channel2 data output */
+
+/******************** Bit definition for DAC_SR register ********************/
+#define DAC_SR_DMAUDR1 0x00002000U /*!<DAC channel1 DMA underrun flag */
+#define DAC_SR_DMAUDR2 0x20000000U /*!<DAC channel2 DMA underrun flag */
+
+/******************************************************************************/
+/* */
+/* Debug MCU */
+/* */
+/******************************************************************************/
+
+/******************************************************************************/
+/* */
+/* DCMI */
+/* */
+/******************************************************************************/
+/******************** Bits definition for DCMI_CR register ******************/
+#define DCMI_CR_CAPTURE 0x00000001U
+#define DCMI_CR_CM 0x00000002U
+#define DCMI_CR_CROP 0x00000004U
+#define DCMI_CR_JPEG 0x00000008U
+#define DCMI_CR_ESS 0x00000010U
+#define DCMI_CR_PCKPOL 0x00000020U
+#define DCMI_CR_HSPOL 0x00000040U
+#define DCMI_CR_VSPOL 0x00000080U
+#define DCMI_CR_FCRC_0 0x00000100U
+#define DCMI_CR_FCRC_1 0x00000200U
+#define DCMI_CR_EDM_0 0x00000400U
+#define DCMI_CR_EDM_1 0x00000800U
+#define DCMI_CR_CRE 0x00001000U
+#define DCMI_CR_ENABLE 0x00004000U
+
+/******************** Bits definition for DCMI_SR register ******************/
+#define DCMI_SR_HSYNC 0x00000001U
+#define DCMI_SR_VSYNC 0x00000002U
+#define DCMI_SR_FNE 0x00000004U
+
+/******************** Bits definition for DCMI_RIS register ****************/
+#define DCMI_RIS_FRAME_RIS 0x00000001U
+#define DCMI_RIS_OVR_RIS 0x00000002U
+#define DCMI_RIS_ERR_RIS 0x00000004U
+#define DCMI_RIS_VSYNC_RIS 0x00000008U
+#define DCMI_RIS_LINE_RIS 0x00000010U
+/* Legacy defines */
+#define DCMI_RISR_FRAME_RIS DCMI_RIS_FRAME_RIS
+#define DCMI_RISR_OVR_RIS DCMI_RIS_OVR_RIS
+#define DCMI_RISR_ERR_RIS DCMI_RIS_ERR_RIS
+#define DCMI_RISR_VSYNC_RIS DCMI_RIS_VSYNC_RIS
+#define DCMI_RISR_LINE_RIS DCMI_RIS_LINE_RIS
+#define DCMI_RISR_OVF_RIS DCMI_RIS_OVR_RIS
+
+/******************** Bits definition for DCMI_IER register *****************/
+#define DCMI_IER_FRAME_IE 0x00000001U
+#define DCMI_IER_OVR_IE 0x00000002U
+#define DCMI_IER_ERR_IE 0x00000004U
+#define DCMI_IER_VSYNC_IE 0x00000008U
+#define DCMI_IER_LINE_IE 0x00000010U
+/* Legacy defines */
+#define DCMI_IER_OVF_IE DCMI_IER_OVR_IE
+
+/******************** Bits definition for DCMI_MIS register *****************/
+#define DCMI_MIS_FRAME_MIS 0x00000001U
+#define DCMI_MIS_OVR_MIS 0x00000002U
+#define DCMI_MIS_ERR_MIS 0x00000004U
+#define DCMI_MIS_VSYNC_MIS 0x00000008U
+#define DCMI_MIS_LINE_MIS 0x00000010U
+
+/* Legacy defines */
+#define DCMI_MISR_FRAME_MIS DCMI_MIS_FRAME_MIS
+#define DCMI_MISR_OVF_MIS DCMI_MIS_OVR_MIS
+#define DCMI_MISR_ERR_MIS DCMI_MIS_ERR_MIS
+#define DCMI_MISR_VSYNC_MIS DCMI_MIS_VSYNC_MIS
+#define DCMI_MISR_LINE_MIS DCMI_MIS_LINE_MIS
+
+/******************** Bits definition for DCMI_ICR register *****************/
+#define DCMI_ICR_FRAME_ISC 0x00000001U
+#define DCMI_ICR_OVR_ISC 0x00000002U
+#define DCMI_ICR_ERR_ISC 0x00000004U
+#define DCMI_ICR_VSYNC_ISC 0x00000008U
+#define DCMI_ICR_LINE_ISC 0x00000010U
+
+/* Legacy defines */
+#define DCMI_ICR_OVF_ISC DCMI_ICR_OVR_ISC
+
+/******************** Bits definition for DCMI_ESCR register ******************/
+#define DCMI_ESCR_FSC 0x000000FFU
+#define DCMI_ESCR_LSC 0x0000FF00U
+#define DCMI_ESCR_LEC 0x00FF0000U
+#define DCMI_ESCR_FEC 0xFF000000U
+
+/******************** Bits definition for DCMI_ESUR register ******************/
+#define DCMI_ESUR_FSU 0x000000FFU
+#define DCMI_ESUR_LSU 0x0000FF00U
+#define DCMI_ESUR_LEU 0x00FF0000U
+#define DCMI_ESUR_FEU 0xFF000000U
+
+/******************** Bits definition for DCMI_CWSTRT register ******************/
+#define DCMI_CWSTRT_HOFFCNT 0x00003FFFU
+#define DCMI_CWSTRT_VST 0x1FFF0000U
+
+/******************** Bits definition for DCMI_CWSIZE register ******************/
+#define DCMI_CWSIZE_CAPCNT 0x00003FFFU
+#define DCMI_CWSIZE_VLINE 0x3FFF0000U
+
+/******************** Bits definition for DCMI_DR register ******************/
+#define DCMI_DR_BYTE0 0x000000FFU
+#define DCMI_DR_BYTE1 0x0000FF00U
+#define DCMI_DR_BYTE2 0x00FF0000U
+#define DCMI_DR_BYTE3 0xFF000000U
+
+/******************************************************************************/
+/* */
+/* DMA Controller */
+/* */
+/******************************************************************************/
+/******************** Bits definition for DMA_SxCR register *****************/
+#define DMA_SxCR_CHSEL 0x0E000000U
+#define DMA_SxCR_CHSEL_0 0x02000000U
+#define DMA_SxCR_CHSEL_1 0x04000000U
+#define DMA_SxCR_CHSEL_2 0x08000000U
+#define DMA_SxCR_MBURST 0x01800000U
+#define DMA_SxCR_MBURST_0 0x00800000U
+#define DMA_SxCR_MBURST_1 0x01000000U
+#define DMA_SxCR_PBURST 0x00600000U
+#define DMA_SxCR_PBURST_0 0x00200000U
+#define DMA_SxCR_PBURST_1 0x00400000U
+#define DMA_SxCR_CT 0x00080000U
+#define DMA_SxCR_DBM 0x00040000U
+#define DMA_SxCR_PL 0x00030000U
+#define DMA_SxCR_PL_0 0x00010000U
+#define DMA_SxCR_PL_1 0x00020000U
+#define DMA_SxCR_PINCOS 0x00008000U
+#define DMA_SxCR_MSIZE 0x00006000U
+#define DMA_SxCR_MSIZE_0 0x00002000U
+#define DMA_SxCR_MSIZE_1 0x00004000U
+#define DMA_SxCR_PSIZE 0x00001800U
+#define DMA_SxCR_PSIZE_0 0x00000800U
+#define DMA_SxCR_PSIZE_1 0x00001000U
+#define DMA_SxCR_MINC 0x00000400U
+#define DMA_SxCR_PINC 0x00000200U
+#define DMA_SxCR_CIRC 0x00000100U
+#define DMA_SxCR_DIR 0x000000C0U
+#define DMA_SxCR_DIR_0 0x00000040U
+#define DMA_SxCR_DIR_1 0x00000080U
+#define DMA_SxCR_PFCTRL 0x00000020U
+#define DMA_SxCR_TCIE 0x00000010U
+#define DMA_SxCR_HTIE 0x00000008U
+#define DMA_SxCR_TEIE 0x00000004U
+#define DMA_SxCR_DMEIE 0x00000002U
+#define DMA_SxCR_EN 0x00000001U
+
+/* Legacy defines */
+#define DMA_SxCR_ACK 0x00100000U
+
+/******************** Bits definition for DMA_SxCNDTR register **************/
+#define DMA_SxNDT 0x0000FFFFU
+#define DMA_SxNDT_0 0x00000001U
+#define DMA_SxNDT_1 0x00000002U
+#define DMA_SxNDT_2 0x00000004U
+#define DMA_SxNDT_3 0x00000008U
+#define DMA_SxNDT_4 0x00000010U
+#define DMA_SxNDT_5 0x00000020U
+#define DMA_SxNDT_6 0x00000040U
+#define DMA_SxNDT_7 0x00000080U
+#define DMA_SxNDT_8 0x00000100U
+#define DMA_SxNDT_9 0x00000200U
+#define DMA_SxNDT_10 0x00000400U
+#define DMA_SxNDT_11 0x00000800U
+#define DMA_SxNDT_12 0x00001000U
+#define DMA_SxNDT_13 0x00002000U
+#define DMA_SxNDT_14 0x00004000U
+#define DMA_SxNDT_15 0x00008000U
+
+/******************** Bits definition for DMA_SxFCR register ****************/
+#define DMA_SxFCR_FEIE 0x00000080U
+#define DMA_SxFCR_FS 0x00000038U
+#define DMA_SxFCR_FS_0 0x00000008U
+#define DMA_SxFCR_FS_1 0x00000010U
+#define DMA_SxFCR_FS_2 0x00000020U
+#define DMA_SxFCR_DMDIS 0x00000004U
+#define DMA_SxFCR_FTH 0x00000003U
+#define DMA_SxFCR_FTH_0 0x00000001U
+#define DMA_SxFCR_FTH_1 0x00000002U
+
+/******************** Bits definition for DMA_LISR register *****************/
+#define DMA_LISR_TCIF3 0x08000000U
+#define DMA_LISR_HTIF3 0x04000000U
+#define DMA_LISR_TEIF3 0x02000000U
+#define DMA_LISR_DMEIF3 0x01000000U
+#define DMA_LISR_FEIF3 0x00400000U
+#define DMA_LISR_TCIF2 0x00200000U
+#define DMA_LISR_HTIF2 0x00100000U
+#define DMA_LISR_TEIF2 0x00080000U
+#define DMA_LISR_DMEIF2 0x00040000U
+#define DMA_LISR_FEIF2 0x00010000U
+#define DMA_LISR_TCIF1 0x00000800U
+#define DMA_LISR_HTIF1 0x00000400U
+#define DMA_LISR_TEIF1 0x00000200U
+#define DMA_LISR_DMEIF1 0x00000100U
+#define DMA_LISR_FEIF1 0x00000040U
+#define DMA_LISR_TCIF0 0x00000020U
+#define DMA_LISR_HTIF0 0x00000010U
+#define DMA_LISR_TEIF0 0x00000008U
+#define DMA_LISR_DMEIF0 0x00000004U
+#define DMA_LISR_FEIF0 0x00000001U
+
+/******************** Bits definition for DMA_HISR register *****************/
+#define DMA_HISR_TCIF7 0x08000000U
+#define DMA_HISR_HTIF7 0x04000000U
+#define DMA_HISR_TEIF7 0x02000000U
+#define DMA_HISR_DMEIF7 0x01000000U
+#define DMA_HISR_FEIF7 0x00400000U
+#define DMA_HISR_TCIF6 0x00200000U
+#define DMA_HISR_HTIF6 0x00100000U
+#define DMA_HISR_TEIF6 0x00080000U
+#define DMA_HISR_DMEIF6 0x00040000U
+#define DMA_HISR_FEIF6 0x00010000U
+#define DMA_HISR_TCIF5 0x00000800U
+#define DMA_HISR_HTIF5 0x00000400U
+#define DMA_HISR_TEIF5 0x00000200U
+#define DMA_HISR_DMEIF5 0x00000100U
+#define DMA_HISR_FEIF5 0x00000040U
+#define DMA_HISR_TCIF4 0x00000020U
+#define DMA_HISR_HTIF4 0x00000010U
+#define DMA_HISR_TEIF4 0x00000008U
+#define DMA_HISR_DMEIF4 0x00000004U
+#define DMA_HISR_FEIF4 0x00000001U
+
+/******************** Bits definition for DMA_LIFCR register ****************/
+#define DMA_LIFCR_CTCIF3 0x08000000U
+#define DMA_LIFCR_CHTIF3 0x04000000U
+#define DMA_LIFCR_CTEIF3 0x02000000U
+#define DMA_LIFCR_CDMEIF3 0x01000000U
+#define DMA_LIFCR_CFEIF3 0x00400000U
+#define DMA_LIFCR_CTCIF2 0x00200000U
+#define DMA_LIFCR_CHTIF2 0x00100000U
+#define DMA_LIFCR_CTEIF2 0x00080000U
+#define DMA_LIFCR_CDMEIF2 0x00040000U
+#define DMA_LIFCR_CFEIF2 0x00010000U
+#define DMA_LIFCR_CTCIF1 0x00000800U
+#define DMA_LIFCR_CHTIF1 0x00000400U
+#define DMA_LIFCR_CTEIF1 0x00000200U
+#define DMA_LIFCR_CDMEIF1 0x00000100U
+#define DMA_LIFCR_CFEIF1 0x00000040U
+#define DMA_LIFCR_CTCIF0 0x00000020U
+#define DMA_LIFCR_CHTIF0 0x00000010U
+#define DMA_LIFCR_CTEIF0 0x00000008U
+#define DMA_LIFCR_CDMEIF0 0x00000004U
+#define DMA_LIFCR_CFEIF0 0x00000001U
+
+/******************** Bits definition for DMA_HIFCR register ****************/
+#define DMA_HIFCR_CTCIF7 0x08000000U
+#define DMA_HIFCR_CHTIF7 0x04000000U
+#define DMA_HIFCR_CTEIF7 0x02000000U
+#define DMA_HIFCR_CDMEIF7 0x01000000U
+#define DMA_HIFCR_CFEIF7 0x00400000U
+#define DMA_HIFCR_CTCIF6 0x00200000U
+#define DMA_HIFCR_CHTIF6 0x00100000U
+#define DMA_HIFCR_CTEIF6 0x00080000U
+#define DMA_HIFCR_CDMEIF6 0x00040000U
+#define DMA_HIFCR_CFEIF6 0x00010000U
+#define DMA_HIFCR_CTCIF5 0x00000800U
+#define DMA_HIFCR_CHTIF5 0x00000400U
+#define DMA_HIFCR_CTEIF5 0x00000200U
+#define DMA_HIFCR_CDMEIF5 0x00000100U
+#define DMA_HIFCR_CFEIF5 0x00000040U
+#define DMA_HIFCR_CTCIF4 0x00000020U
+#define DMA_HIFCR_CHTIF4 0x00000010U
+#define DMA_HIFCR_CTEIF4 0x00000008U
+#define DMA_HIFCR_CDMEIF4 0x00000004U
+#define DMA_HIFCR_CFEIF4 0x00000001U
+
+/******************************************************************************/
+/* */
+/* AHB Master DMA2D Controller (DMA2D) */
+/* */
+/******************************************************************************/
+
+/******************** Bit definition for DMA2D_CR register ******************/
+
+#define DMA2D_CR_START 0x00000001U /*!< Start transfer */
+#define DMA2D_CR_SUSP 0x00000002U /*!< Suspend transfer */
+#define DMA2D_CR_ABORT 0x00000004U /*!< Abort transfer */
+#define DMA2D_CR_TEIE 0x00000100U /*!< Transfer Error Interrupt Enable */
+#define DMA2D_CR_TCIE 0x00000200U /*!< Transfer Complete Interrupt Enable */
+#define DMA2D_CR_TWIE 0x00000400U /*!< Transfer Watermark Interrupt Enable */
+#define DMA2D_CR_CAEIE 0x00000800U /*!< CLUT Access Error Interrupt Enable */
+#define DMA2D_CR_CTCIE 0x00001000U /*!< CLUT Transfer Complete Interrupt Enable */
+#define DMA2D_CR_CEIE 0x00002000U /*!< Configuration Error Interrupt Enable */
+#define DMA2D_CR_MODE 0x00030000U /*!< DMA2D Mode[1:0] */
+#define DMA2D_CR_MODE_0 0x00010000U /*!< DMA2D Mode bit 0 */
+#define DMA2D_CR_MODE_1 0x00020000U /*!< DMA2D Mode bit 1 */
+
+/******************** Bit definition for DMA2D_ISR register *****************/
+
+#define DMA2D_ISR_TEIF 0x00000001U /*!< Transfer Error Interrupt Flag */
+#define DMA2D_ISR_TCIF 0x00000002U /*!< Transfer Complete Interrupt Flag */
+#define DMA2D_ISR_TWIF 0x00000004U /*!< Transfer Watermark Interrupt Flag */
+#define DMA2D_ISR_CAEIF 0x00000008U /*!< CLUT Access Error Interrupt Flag */
+#define DMA2D_ISR_CTCIF 0x00000010U /*!< CLUT Transfer Complete Interrupt Flag */
+#define DMA2D_ISR_CEIF 0x00000020U /*!< Configuration Error Interrupt Flag */
+
+/******************** Bit definition for DMA2D_IFCR register ****************/
+
+#define DMA2D_IFCR_CTEIF 0x00000001U /*!< Clears Transfer Error Interrupt Flag */
+#define DMA2D_IFCR_CTCIF 0x00000002U /*!< Clears Transfer Complete Interrupt Flag */
+#define DMA2D_IFCR_CTWIF 0x00000004U /*!< Clears Transfer Watermark Interrupt Flag */
+#define DMA2D_IFCR_CAECIF 0x00000008U /*!< Clears CLUT Access Error Interrupt Flag */
+#define DMA2D_IFCR_CCTCIF 0x00000010U /*!< Clears CLUT Transfer Complete Interrupt Flag */
+#define DMA2D_IFCR_CCEIF 0x00000020U /*!< Clears Configuration Error Interrupt Flag */
+
+/* Legacy defines */
+#define DMA2D_IFSR_CTEIF DMA2D_IFCR_CTEIF /*!< Clears Transfer Error Interrupt Flag */
+#define DMA2D_IFSR_CTCIF DMA2D_IFCR_CTCIF /*!< Clears Transfer Complete Interrupt Flag */
+#define DMA2D_IFSR_CTWIF DMA2D_IFCR_CTWIF /*!< Clears Transfer Watermark Interrupt Flag */
+#define DMA2D_IFSR_CCAEIF DMA2D_IFCR_CAECIF /*!< Clears CLUT Access Error Interrupt Flag */
+#define DMA2D_IFSR_CCTCIF DMA2D_IFCR_CCTCIF /*!< Clears CLUT Transfer Complete Interrupt Flag */
+#define DMA2D_IFSR_CCEIF DMA2D_IFCR_CCEIF /*!< Clears Configuration Error Interrupt Flag */
+
+/******************** Bit definition for DMA2D_FGMAR register ***************/
+
+#define DMA2D_FGMAR_MA 0xFFFFFFFFU /*!< Memory Address */
+
+/******************** Bit definition for DMA2D_FGOR register ****************/
+
+#define DMA2D_FGOR_LO 0x00003FFFU /*!< Line Offset */
+
+/******************** Bit definition for DMA2D_BGMAR register ***************/
+
+#define DMA2D_BGMAR_MA 0xFFFFFFFFU /*!< Memory Address */
+
+/******************** Bit definition for DMA2D_BGOR register ****************/
+
+#define DMA2D_BGOR_LO 0x00003FFFU /*!< Line Offset */
+
+/******************** Bit definition for DMA2D_FGPFCCR register *************/
+
+#define DMA2D_FGPFCCR_CM 0x0000000FU /*!< Input color mode CM[3:0] */
+#define DMA2D_FGPFCCR_CM_0 0x00000001U /*!< Input color mode CM bit 0 */
+#define DMA2D_FGPFCCR_CM_1 0x00000002U /*!< Input color mode CM bit 1 */
+#define DMA2D_FGPFCCR_CM_2 0x00000004U /*!< Input color mode CM bit 2 */
+#define DMA2D_FGPFCCR_CM_3 0x00000008U /*!< Input color mode CM bit 3 */
+#define DMA2D_FGPFCCR_CCM 0x00000010U /*!< CLUT Color mode */
+#define DMA2D_FGPFCCR_START 0x00000020U /*!< Start */
+#define DMA2D_FGPFCCR_CS 0x0000FF00U /*!< CLUT size */
+#define DMA2D_FGPFCCR_AM 0x00030000U /*!< Alpha mode AM[1:0] */
+#define DMA2D_FGPFCCR_AM_0 0x00010000U /*!< Alpha mode AM bit 0 */
+#define DMA2D_FGPFCCR_AM_1 0x00020000U /*!< Alpha mode AM bit 1 */
+#define DMA2D_FGPFCCR_ALPHA 0xFF000000U /*!< Alpha value */
+
+/******************** Bit definition for DMA2D_FGCOLR register **************/
+
+#define DMA2D_FGCOLR_BLUE 0x000000FFU /*!< Blue Value */
+#define DMA2D_FGCOLR_GREEN 0x0000FF00U /*!< Green Value */
+#define DMA2D_FGCOLR_RED 0x00FF0000U /*!< Red Value */
+
+/******************** Bit definition for DMA2D_BGPFCCR register *************/
+
+#define DMA2D_BGPFCCR_CM 0x0000000FU /*!< Input color mode CM[3:0] */
+#define DMA2D_BGPFCCR_CM_0 0x00000001U /*!< Input color mode CM bit 0 */
+#define DMA2D_BGPFCCR_CM_1 0x00000002U /*!< Input color mode CM bit 1 */
+#define DMA2D_BGPFCCR_CM_2 0x00000004U /*!< Input color mode CM bit 2 */
+#define DMA2D_FGPFCCR_CM_3 0x00000008U /*!< Input color mode CM bit 3 */
+#define DMA2D_BGPFCCR_CCM 0x00000010U /*!< CLUT Color mode */
+#define DMA2D_BGPFCCR_START 0x00000020U /*!< Start */
+#define DMA2D_BGPFCCR_CS 0x0000FF00U /*!< CLUT size */
+#define DMA2D_BGPFCCR_AM 0x00030000U /*!< Alpha mode AM[1:0] */
+#define DMA2D_BGPFCCR_AM_0 0x00010000U /*!< Alpha mode AM bit 0 */
+#define DMA2D_BGPFCCR_AM_1 0x00020000U /*!< Alpha mode AM bit 1 */
+#define DMA2D_BGPFCCR_ALPHA 0xFF000000U /*!< background Input Alpha value */
+
+/******************** Bit definition for DMA2D_BGCOLR register **************/
+
+#define DMA2D_BGCOLR_BLUE 0x000000FFU /*!< Blue Value */
+#define DMA2D_BGCOLR_GREEN 0x0000FF00U /*!< Green Value */
+#define DMA2D_BGCOLR_RED 0x00FF0000U /*!< Red Value */
+
+/******************** Bit definition for DMA2D_FGCMAR register **************/
+
+#define DMA2D_FGCMAR_MA 0xFFFFFFFFU /*!< Memory Address */
+
+/******************** Bit definition for DMA2D_BGCMAR register **************/
+
+#define DMA2D_BGCMAR_MA 0xFFFFFFFFU /*!< Memory Address */
+
+/******************** Bit definition for DMA2D_OPFCCR register **************/
+
+#define DMA2D_OPFCCR_CM 0x00000007U /*!< Color mode CM[2:0] */
+#define DMA2D_OPFCCR_CM_0 0x00000001U /*!< Color mode CM bit 0 */
+#define DMA2D_OPFCCR_CM_1 0x00000002U /*!< Color mode CM bit 1 */
+#define DMA2D_OPFCCR_CM_2 0x00000004U /*!< Color mode CM bit 2 */
+
+/******************** Bit definition for DMA2D_OCOLR register ***************/
+
+/*!<Mode_ARGB8888/RGB888 */
+
+#define DMA2D_OCOLR_BLUE_1 0x000000FFU /*!< BLUE Value */
+#define DMA2D_OCOLR_GREEN_1 0x0000FF00U /*!< GREEN Value */
+#define DMA2D_OCOLR_RED_1 0x00FF0000U /*!< Red Value */
+#define DMA2D_OCOLR_ALPHA_1 0xFF000000U /*!< Alpha Channel Value */
+
+/*!<Mode_RGB565 */
+#define DMA2D_OCOLR_BLUE_2 0x0000001FU /*!< BLUE Value */
+#define DMA2D_OCOLR_GREEN_2 0x000007E0U /*!< GREEN Value */
+#define DMA2D_OCOLR_RED_2 0x0000F800U /*!< Red Value */
+
+/*!<Mode_ARGB1555 */
+#define DMA2D_OCOLR_BLUE_3 0x0000001FU /*!< BLUE Value */
+#define DMA2D_OCOLR_GREEN_3 0x000003E0U /*!< GREEN Value */
+#define DMA2D_OCOLR_RED_3 0x00007C00U /*!< Red Value */
+#define DMA2D_OCOLR_ALPHA_3 0x00008000U /*!< Alpha Channel Value */
+
+/*!<Mode_ARGB4444 */
+#define DMA2D_OCOLR_BLUE_4 0x0000000FU /*!< BLUE Value */
+#define DMA2D_OCOLR_GREEN_4 0x000000F0U /*!< GREEN Value */
+#define DMA2D_OCOLR_RED_4 0x00000F00U /*!< Red Value */
+#define DMA2D_OCOLR_ALPHA_4 0x0000F000U /*!< Alpha Channel Value */
+
+/******************** Bit definition for DMA2D_OMAR register ****************/
+
+#define DMA2D_OMAR_MA 0xFFFFFFFFU /*!< Memory Address */
+
+/******************** Bit definition for DMA2D_OOR register *****************/
+
+#define DMA2D_OOR_LO 0x00003FFFU /*!< Line Offset */
+
+/******************** Bit definition for DMA2D_NLR register *****************/
+
+#define DMA2D_NLR_NL 0x0000FFFFU /*!< Number of Lines */
+#define DMA2D_NLR_PL 0x3FFF0000U /*!< Pixel per Lines */
+
+/******************** Bit definition for DMA2D_LWR register *****************/
+
+#define DMA2D_LWR_LW 0x0000FFFFU /*!< Line Watermark */
+
+/******************** Bit definition for DMA2D_AMTCR register ***************/
+
+#define DMA2D_AMTCR_EN 0x00000001U /*!< Enable */
+#define DMA2D_AMTCR_DT 0x0000FF00U /*!< Dead Time */
+
+
+/******************** Bit definition for DMA2D_FGCLUT register **************/
+
+/******************** Bit definition for DMA2D_BGCLUT register **************/
+
+
+/******************************************************************************/
+/* */
+/* External Interrupt/Event Controller */
+/* */
+/******************************************************************************/
+/******************* Bit definition for EXTI_IMR register *******************/
+#define EXTI_IMR_MR0 0x00000001U /*!< Interrupt Mask on line 0 */
+#define EXTI_IMR_MR1 0x00000002U /*!< Interrupt Mask on line 1 */
+#define EXTI_IMR_MR2 0x00000004U /*!< Interrupt Mask on line 2 */
+#define EXTI_IMR_MR3 0x00000008U /*!< Interrupt Mask on line 3 */
+#define EXTI_IMR_MR4 0x00000010U /*!< Interrupt Mask on line 4 */
+#define EXTI_IMR_MR5 0x00000020U /*!< Interrupt Mask on line 5 */
+#define EXTI_IMR_MR6 0x00000040U /*!< Interrupt Mask on line 6 */
+#define EXTI_IMR_MR7 0x00000080U /*!< Interrupt Mask on line 7 */
+#define EXTI_IMR_MR8 0x00000100U /*!< Interrupt Mask on line 8 */
+#define EXTI_IMR_MR9 0x00000200U /*!< Interrupt Mask on line 9 */
+#define EXTI_IMR_MR10 0x00000400U /*!< Interrupt Mask on line 10 */
+#define EXTI_IMR_MR11 0x00000800U /*!< Interrupt Mask on line 11 */
+#define EXTI_IMR_MR12 0x00001000U /*!< Interrupt Mask on line 12 */
+#define EXTI_IMR_MR13 0x00002000U /*!< Interrupt Mask on line 13 */
+#define EXTI_IMR_MR14 0x00004000U /*!< Interrupt Mask on line 14 */
+#define EXTI_IMR_MR15 0x00008000U /*!< Interrupt Mask on line 15 */
+#define EXTI_IMR_MR16 0x00010000U /*!< Interrupt Mask on line 16 */
+#define EXTI_IMR_MR17 0x00020000U /*!< Interrupt Mask on line 17 */
+#define EXTI_IMR_MR18 0x00040000U /*!< Interrupt Mask on line 18 */
+#define EXTI_IMR_MR19 0x00080000U /*!< Interrupt Mask on line 19 */
+#define EXTI_IMR_MR20 0x00100000U /*!< Interrupt Mask on line 20 */
+#define EXTI_IMR_MR21 0x00200000U /*!< Interrupt Mask on line 21 */
+#define EXTI_IMR_MR22 0x00400000U /*!< Interrupt Mask on line 22 */
+
+/******************* Bit definition for EXTI_EMR register *******************/
+#define EXTI_EMR_MR0 0x00000001U /*!< Event Mask on line 0 */
+#define EXTI_EMR_MR1 0x00000002U /*!< Event Mask on line 1 */
+#define EXTI_EMR_MR2 0x00000004U /*!< Event Mask on line 2 */
+#define EXTI_EMR_MR3 0x00000008U /*!< Event Mask on line 3 */
+#define EXTI_EMR_MR4 0x00000010U /*!< Event Mask on line 4 */
+#define EXTI_EMR_MR5 0x00000020U /*!< Event Mask on line 5 */
+#define EXTI_EMR_MR6 0x00000040U /*!< Event Mask on line 6 */
+#define EXTI_EMR_MR7 0x00000080U /*!< Event Mask on line 7 */
+#define EXTI_EMR_MR8 0x00000100U /*!< Event Mask on line 8 */
+#define EXTI_EMR_MR9 0x00000200U /*!< Event Mask on line 9 */
+#define EXTI_EMR_MR10 0x00000400U /*!< Event Mask on line 10 */
+#define EXTI_EMR_MR11 0x00000800U /*!< Event Mask on line 11 */
+#define EXTI_EMR_MR12 0x00001000U /*!< Event Mask on line 12 */
+#define EXTI_EMR_MR13 0x00002000U /*!< Event Mask on line 13 */
+#define EXTI_EMR_MR14 0x00004000U /*!< Event Mask on line 14 */
+#define EXTI_EMR_MR15 0x00008000U /*!< Event Mask on line 15 */
+#define EXTI_EMR_MR16 0x00010000U /*!< Event Mask on line 16 */
+#define EXTI_EMR_MR17 0x00020000U /*!< Event Mask on line 17 */
+#define EXTI_EMR_MR18 0x00040000U /*!< Event Mask on line 18 */
+#define EXTI_EMR_MR19 0x00080000U /*!< Event Mask on line 19 */
+#define EXTI_EMR_MR20 0x00100000U /*!< Event Mask on line 20 */
+#define EXTI_EMR_MR21 0x00200000U /*!< Event Mask on line 21 */
+#define EXTI_EMR_MR22 0x00400000U /*!< Event Mask on line 22 */
+
+/****************** Bit definition for EXTI_RTSR register *******************/
+#define EXTI_RTSR_TR0 0x00000001U /*!< Rising trigger event configuration bit of line 0 */
+#define EXTI_RTSR_TR1 0x00000002U /*!< Rising trigger event configuration bit of line 1 */
+#define EXTI_RTSR_TR2 0x00000004U /*!< Rising trigger event configuration bit of line 2 */
+#define EXTI_RTSR_TR3 0x00000008U /*!< Rising trigger event configuration bit of line 3 */
+#define EXTI_RTSR_TR4 0x00000010U /*!< Rising trigger event configuration bit of line 4 */
+#define EXTI_RTSR_TR5 0x00000020U /*!< Rising trigger event configuration bit of line 5 */
+#define EXTI_RTSR_TR6 0x00000040U /*!< Rising trigger event configuration bit of line 6 */
+#define EXTI_RTSR_TR7 0x00000080U /*!< Rising trigger event configuration bit of line 7 */
+#define EXTI_RTSR_TR8 0x00000100U /*!< Rising trigger event configuration bit of line 8 */
+#define EXTI_RTSR_TR9 0x00000200U /*!< Rising trigger event configuration bit of line 9 */
+#define EXTI_RTSR_TR10 0x00000400U /*!< Rising trigger event configuration bit of line 10 */
+#define EXTI_RTSR_TR11 0x00000800U /*!< Rising trigger event configuration bit of line 11 */
+#define EXTI_RTSR_TR12 0x00001000U /*!< Rising trigger event configuration bit of line 12 */
+#define EXTI_RTSR_TR13 0x00002000U /*!< Rising trigger event configuration bit of line 13 */
+#define EXTI_RTSR_TR14 0x00004000U /*!< Rising trigger event configuration bit of line 14 */
+#define EXTI_RTSR_TR15 0x00008000U /*!< Rising trigger event configuration bit of line 15 */
+#define EXTI_RTSR_TR16 0x00010000U /*!< Rising trigger event configuration bit of line 16 */
+#define EXTI_RTSR_TR17 0x00020000U /*!< Rising trigger event configuration bit of line 17 */
+#define EXTI_RTSR_TR18 0x00040000U /*!< Rising trigger event configuration bit of line 18 */
+#define EXTI_RTSR_TR19 0x00080000U /*!< Rising trigger event configuration bit of line 19 */
+#define EXTI_RTSR_TR20 0x00100000U /*!< Rising trigger event configuration bit of line 20 */
+#define EXTI_RTSR_TR21 0x00200000U /*!< Rising trigger event configuration bit of line 21 */
+#define EXTI_RTSR_TR22 0x00400000U /*!< Rising trigger event configuration bit of line 22 */
+
+/****************** Bit definition for EXTI_FTSR register *******************/
+#define EXTI_FTSR_TR0 0x00000001U /*!< Falling trigger event configuration bit of line 0 */
+#define EXTI_FTSR_TR1 0x00000002U /*!< Falling trigger event configuration bit of line 1 */
+#define EXTI_FTSR_TR2 0x00000004U /*!< Falling trigger event configuration bit of line 2 */
+#define EXTI_FTSR_TR3 0x00000008U /*!< Falling trigger event configuration bit of line 3 */
+#define EXTI_FTSR_TR4 0x00000010U /*!< Falling trigger event configuration bit of line 4 */
+#define EXTI_FTSR_TR5 0x00000020U /*!< Falling trigger event configuration bit of line 5 */
+#define EXTI_FTSR_TR6 0x00000040U /*!< Falling trigger event configuration bit of line 6 */
+#define EXTI_FTSR_TR7 0x00000080U /*!< Falling trigger event configuration bit of line 7 */
+#define EXTI_FTSR_TR8 0x00000100U /*!< Falling trigger event configuration bit of line 8 */
+#define EXTI_FTSR_TR9 0x00000200U /*!< Falling trigger event configuration bit of line 9 */
+#define EXTI_FTSR_TR10 0x00000400U /*!< Falling trigger event configuration bit of line 10 */
+#define EXTI_FTSR_TR11 0x00000800U /*!< Falling trigger event configuration bit of line 11 */
+#define EXTI_FTSR_TR12 0x00001000U /*!< Falling trigger event configuration bit of line 12 */
+#define EXTI_FTSR_TR13 0x00002000U /*!< Falling trigger event configuration bit of line 13 */
+#define EXTI_FTSR_TR14 0x00004000U /*!< Falling trigger event configuration bit of line 14 */
+#define EXTI_FTSR_TR15 0x00008000U /*!< Falling trigger event configuration bit of line 15 */
+#define EXTI_FTSR_TR16 0x00010000U /*!< Falling trigger event configuration bit of line 16 */
+#define EXTI_FTSR_TR17 0x00020000U /*!< Falling trigger event configuration bit of line 17 */
+#define EXTI_FTSR_TR18 0x00040000U /*!< Falling trigger event configuration bit of line 18 */
+#define EXTI_FTSR_TR19 0x00080000U /*!< Falling trigger event configuration bit of line 19 */
+#define EXTI_FTSR_TR20 0x00100000U /*!< Falling trigger event configuration bit of line 20 */
+#define EXTI_FTSR_TR21 0x00200000U /*!< Falling trigger event configuration bit of line 21 */
+#define EXTI_FTSR_TR22 0x00400000U /*!< Falling trigger event configuration bit of line 22 */
+
+/****************** Bit definition for EXTI_SWIER register ******************/
+#define EXTI_SWIER_SWIER0 0x00000001U /*!< Software Interrupt on line 0 */
+#define EXTI_SWIER_SWIER1 0x00000002U /*!< Software Interrupt on line 1 */
+#define EXTI_SWIER_SWIER2 0x00000004U /*!< Software Interrupt on line 2 */
+#define EXTI_SWIER_SWIER3 0x00000008U /*!< Software Interrupt on line 3 */
+#define EXTI_SWIER_SWIER4 0x00000010U /*!< Software Interrupt on line 4 */
+#define EXTI_SWIER_SWIER5 0x00000020U /*!< Software Interrupt on line 5 */
+#define EXTI_SWIER_SWIER6 0x00000040U /*!< Software Interrupt on line 6 */
+#define EXTI_SWIER_SWIER7 0x00000080U /*!< Software Interrupt on line 7 */
+#define EXTI_SWIER_SWIER8 0x00000100U /*!< Software Interrupt on line 8 */
+#define EXTI_SWIER_SWIER9 0x00000200U /*!< Software Interrupt on line 9 */
+#define EXTI_SWIER_SWIER10 0x00000400U /*!< Software Interrupt on line 10 */
+#define EXTI_SWIER_SWIER11 0x00000800U /*!< Software Interrupt on line 11 */
+#define EXTI_SWIER_SWIER12 0x00001000U /*!< Software Interrupt on line 12 */
+#define EXTI_SWIER_SWIER13 0x00002000U /*!< Software Interrupt on line 13 */
+#define EXTI_SWIER_SWIER14 0x00004000U /*!< Software Interrupt on line 14 */
+#define EXTI_SWIER_SWIER15 0x00008000U /*!< Software Interrupt on line 15 */
+#define EXTI_SWIER_SWIER16 0x00010000U /*!< Software Interrupt on line 16 */
+#define EXTI_SWIER_SWIER17 0x00020000U /*!< Software Interrupt on line 17 */
+#define EXTI_SWIER_SWIER18 0x00040000U /*!< Software Interrupt on line 18 */
+#define EXTI_SWIER_SWIER19 0x00080000U /*!< Software Interrupt on line 19 */
+#define EXTI_SWIER_SWIER20 0x00100000U /*!< Software Interrupt on line 20 */
+#define EXTI_SWIER_SWIER21 0x00200000U /*!< Software Interrupt on line 21 */
+#define EXTI_SWIER_SWIER22 0x00400000U /*!< Software Interrupt on line 22 */
+
+/******************* Bit definition for EXTI_PR register ********************/
+#define EXTI_PR_PR0 0x00000001U /*!< Pending bit for line 0 */
+#define EXTI_PR_PR1 0x00000002U /*!< Pending bit for line 1 */
+#define EXTI_PR_PR2 0x00000004U /*!< Pending bit for line 2 */
+#define EXTI_PR_PR3 0x00000008U /*!< Pending bit for line 3 */
+#define EXTI_PR_PR4 0x00000010U /*!< Pending bit for line 4 */
+#define EXTI_PR_PR5 0x00000020U /*!< Pending bit for line 5 */
+#define EXTI_PR_PR6 0x00000040U /*!< Pending bit for line 6 */
+#define EXTI_PR_PR7 0x00000080U /*!< Pending bit for line 7 */
+#define EXTI_PR_PR8 0x00000100U /*!< Pending bit for line 8 */
+#define EXTI_PR_PR9 0x00000200U /*!< Pending bit for line 9 */
+#define EXTI_PR_PR10 0x00000400U /*!< Pending bit for line 10 */
+#define EXTI_PR_PR11 0x00000800U /*!< Pending bit for line 11 */
+#define EXTI_PR_PR12 0x00001000U /*!< Pending bit for line 12 */
+#define EXTI_PR_PR13 0x00002000U /*!< Pending bit for line 13 */
+#define EXTI_PR_PR14 0x00004000U /*!< Pending bit for line 14 */
+#define EXTI_PR_PR15 0x00008000U /*!< Pending bit for line 15 */
+#define EXTI_PR_PR16 0x00010000U /*!< Pending bit for line 16 */
+#define EXTI_PR_PR17 0x00020000U /*!< Pending bit for line 17 */
+#define EXTI_PR_PR18 0x00040000U /*!< Pending bit for line 18 */
+#define EXTI_PR_PR19 0x00080000U /*!< Pending bit for line 19 */
+#define EXTI_PR_PR20 0x00100000U /*!< Pending bit for line 20 */
+#define EXTI_PR_PR21 0x00200000U /*!< Pending bit for line 21 */
+#define EXTI_PR_PR22 0x00400000U /*!< Pending bit for line 22 */
+
+/******************************************************************************/
+/* */
+/* FLASH */
+/* */
+/******************************************************************************/
+/******************* Bits definition for FLASH_ACR register *****************/
+#define FLASH_ACR_LATENCY 0x0000000FU
+#define FLASH_ACR_LATENCY_0WS 0x00000000U
+#define FLASH_ACR_LATENCY_1WS 0x00000001U
+#define FLASH_ACR_LATENCY_2WS 0x00000002U
+#define FLASH_ACR_LATENCY_3WS 0x00000003U
+#define FLASH_ACR_LATENCY_4WS 0x00000004U
+#define FLASH_ACR_LATENCY_5WS 0x00000005U
+#define FLASH_ACR_LATENCY_6WS 0x00000006U
+#define FLASH_ACR_LATENCY_7WS 0x00000007U
+#define FLASH_ACR_LATENCY_8WS 0x00000008U
+#define FLASH_ACR_LATENCY_9WS 0x00000009U
+#define FLASH_ACR_LATENCY_10WS 0x0000000AU
+#define FLASH_ACR_LATENCY_11WS 0x0000000BU
+#define FLASH_ACR_LATENCY_12WS 0x0000000CU
+#define FLASH_ACR_LATENCY_13WS 0x0000000DU
+#define FLASH_ACR_LATENCY_14WS 0x0000000EU
+#define FLASH_ACR_LATENCY_15WS 0x0000000FU
+#define FLASH_ACR_PRFTEN 0x00000100U
+#define FLASH_ACR_ICEN 0x00000200U
+#define FLASH_ACR_DCEN 0x00000400U
+#define FLASH_ACR_ICRST 0x00000800U
+#define FLASH_ACR_DCRST 0x00001000U
+#define FLASH_ACR_BYTE0_ADDRESS 0x40023C00U
+#define FLASH_ACR_BYTE2_ADDRESS 0x40023C03U
+
+/******************* Bits definition for FLASH_SR register ******************/
+#define FLASH_SR_EOP 0x00000001U
+#define FLASH_SR_SOP 0x00000002U
+#define FLASH_SR_WRPERR 0x00000010U
+#define FLASH_SR_PGAERR 0x00000020U
+#define FLASH_SR_PGPERR 0x00000040U
+#define FLASH_SR_PGSERR 0x00000080U
+#define FLASH_SR_BSY 0x00010000U
+
+/******************* Bits definition for FLASH_CR register ******************/
+#define FLASH_CR_PG 0x00000001U
+#define FLASH_CR_SER 0x00000002U
+#define FLASH_CR_MER 0x00000004U
+#define FLASH_CR_MER1 FLASH_CR_MER
+#define FLASH_CR_SNB 0x000000F8U
+#define FLASH_CR_SNB_0 0x00000008U
+#define FLASH_CR_SNB_1 0x00000010U
+#define FLASH_CR_SNB_2 0x00000020U
+#define FLASH_CR_SNB_3 0x00000040U
+#define FLASH_CR_SNB_4 0x00000080U
+#define FLASH_CR_PSIZE 0x00000300U
+#define FLASH_CR_PSIZE_0 0x00000100U
+#define FLASH_CR_PSIZE_1 0x00000200U
+#define FLASH_CR_MER2 0x00008000U
+#define FLASH_CR_STRT 0x00010000U
+#define FLASH_CR_EOPIE 0x01000000U
+#define FLASH_CR_LOCK 0x80000000U
+
+/******************* Bits definition for FLASH_OPTCR register ***************/
+#define FLASH_OPTCR_OPTLOCK 0x00000001U
+#define FLASH_OPTCR_OPTSTRT 0x00000002U
+#define FLASH_OPTCR_BOR_LEV_0 0x00000004U
+#define FLASH_OPTCR_BOR_LEV_1 0x00000008U
+#define FLASH_OPTCR_BOR_LEV 0x0000000CU
+#define FLASH_OPTCR_BFB2 0x00000010U
+#define FLASH_OPTCR_WDG_SW 0x00000020U
+#define FLASH_OPTCR_nRST_STOP 0x00000040U
+#define FLASH_OPTCR_nRST_STDBY 0x00000080U
+#define FLASH_OPTCR_RDP 0x0000FF00U
+#define FLASH_OPTCR_RDP_0 0x00000100U
+#define FLASH_OPTCR_RDP_1 0x00000200U
+#define FLASH_OPTCR_RDP_2 0x00000400U
+#define FLASH_OPTCR_RDP_3 0x00000800U
+#define FLASH_OPTCR_RDP_4 0x00001000U
+#define FLASH_OPTCR_RDP_5 0x00002000U
+#define FLASH_OPTCR_RDP_6 0x00004000U
+#define FLASH_OPTCR_RDP_7 0x00008000U
+#define FLASH_OPTCR_nWRP 0x0FFF0000U
+#define FLASH_OPTCR_nWRP_0 0x00010000U
+#define FLASH_OPTCR_nWRP_1 0x00020000U
+#define FLASH_OPTCR_nWRP_2 0x00040000U
+#define FLASH_OPTCR_nWRP_3 0x00080000U
+#define FLASH_OPTCR_nWRP_4 0x00100000U
+#define FLASH_OPTCR_nWRP_5 0x00200000U
+#define FLASH_OPTCR_nWRP_6 0x00400000U
+#define FLASH_OPTCR_nWRP_7 0x00800000U
+#define FLASH_OPTCR_nWRP_8 0x01000000U
+#define FLASH_OPTCR_nWRP_9 0x02000000U
+#define FLASH_OPTCR_nWRP_10 0x04000000U
+#define FLASH_OPTCR_nWRP_11 0x08000000U
+#define FLASH_OPTCR_DB1M 0x40000000U
+#define FLASH_OPTCR_SPRMOD 0x80000000U
+
+/****************** Bits definition for FLASH_OPTCR1 register ***************/
+#define FLASH_OPTCR1_nWRP 0x0FFF0000U
+#define FLASH_OPTCR1_nWRP_0 0x00010000U
+#define FLASH_OPTCR1_nWRP_1 0x00020000U
+#define FLASH_OPTCR1_nWRP_2 0x00040000U
+#define FLASH_OPTCR1_nWRP_3 0x00080000U
+#define FLASH_OPTCR1_nWRP_4 0x00100000U
+#define FLASH_OPTCR1_nWRP_5 0x00200000U
+#define FLASH_OPTCR1_nWRP_6 0x00400000U
+#define FLASH_OPTCR1_nWRP_7 0x00800000U
+#define FLASH_OPTCR1_nWRP_8 0x01000000U
+#define FLASH_OPTCR1_nWRP_9 0x02000000U
+#define FLASH_OPTCR1_nWRP_10 0x04000000U
+#define FLASH_OPTCR1_nWRP_11 0x08000000U
+
+/******************************************************************************/
+/* */
+/* Flexible Memory Controller */
+/* */
+/******************************************************************************/
+/****************** Bit definition for FMC_BCR1 register *******************/
+#define FMC_BCR1_MBKEN 0x00000001U /*!<Memory bank enable bit */
+#define FMC_BCR1_MUXEN 0x00000002U /*!<Address/data multiplexing enable bit */
+
+#define FMC_BCR1_MTYP 0x0000000CU /*!<MTYP[1:0] bits (Memory type) */
+#define FMC_BCR1_MTYP_0 0x00000004U /*!<Bit 0 */
+#define FMC_BCR1_MTYP_1 0x00000008U /*!<Bit 1 */
+
+#define FMC_BCR1_MWID 0x00000030U /*!<MWID[1:0] bits (Memory data bus width) */
+#define FMC_BCR1_MWID_0 0x00000010U /*!<Bit 0 */
+#define FMC_BCR1_MWID_1 0x00000020U /*!<Bit 1 */
+
+#define FMC_BCR1_FACCEN 0x00000040U /*!<Flash access enable */
+#define FMC_BCR1_BURSTEN 0x00000100U /*!<Burst enable bit */
+#define FMC_BCR1_WAITPOL 0x00000200U /*!<Wait signal polarity bit */
+#define FMC_BCR1_WRAPMOD 0x00000400U /*!<Wrapped burst mode support */
+#define FMC_BCR1_WAITCFG 0x00000800U /*!<Wait timing configuration */
+#define FMC_BCR1_WREN 0x00001000U /*!<Write enable bit */
+#define FMC_BCR1_WAITEN 0x00002000U /*!<Wait enable bit */
+#define FMC_BCR1_EXTMOD 0x00004000U /*!<Extended mode enable */
+#define FMC_BCR1_ASYNCWAIT 0x00008000U /*!<Asynchronous wait */
+#define FMC_BCR1_CPSIZE 0x00070000U /*!<CRAM page size */
+#define FMC_BCR1_CPSIZE_0 0x00010000U /*!<Bit 0 */
+#define FMC_BCR1_CPSIZE_1 0x00020000U /*!<Bit 1 */
+#define FMC_BCR1_CPSIZE_2 0x00040000U /*!<Bit 2 */
+#define FMC_BCR1_CBURSTRW 0x00080000U /*!<Write burst enable */
+#define FMC_BCR1_CCLKEN 0x00100000U /*!<Continous clock enable */
+
+/****************** Bit definition for FMC_BCR2 register *******************/
+#define FMC_BCR2_MBKEN 0x00000001U /*!<Memory bank enable bit */
+#define FMC_BCR2_MUXEN 0x00000002U /*!<Address/data multiplexing enable bit */
+
+#define FMC_BCR2_MTYP 0x0000000CU /*!<MTYP[1:0] bits (Memory type) */
+#define FMC_BCR2_MTYP_0 0x00000004U /*!<Bit 0 */
+#define FMC_BCR2_MTYP_1 0x00000008U /*!<Bit 1 */
+
+#define FMC_BCR2_MWID 0x00000030U /*!<MWID[1:0] bits (Memory data bus width) */
+#define FMC_BCR2_MWID_0 0x00000010U /*!<Bit 0 */
+#define FMC_BCR2_MWID_1 0x00000020U /*!<Bit 1 */
+
+#define FMC_BCR2_FACCEN 0x00000040U /*!<Flash access enable */
+#define FMC_BCR2_BURSTEN 0x00000100U /*!<Burst enable bit */
+#define FMC_BCR2_WAITPOL 0x00000200U /*!<Wait signal polarity bit */
+#define FMC_BCR2_WRAPMOD 0x00000400U /*!<Wrapped burst mode support */
+#define FMC_BCR2_WAITCFG 0x00000800U /*!<Wait timing configuration */
+#define FMC_BCR2_WREN 0x00001000U /*!<Write enable bit */
+#define FMC_BCR2_WAITEN 0x00002000U /*!<Wait enable bit */
+#define FMC_BCR2_EXTMOD 0x00004000U /*!<Extended mode enable */
+#define FMC_BCR2_ASYNCWAIT 0x00008000U /*!<Asynchronous wait */
+#define FMC_BCR2_CPSIZE 0x00070000U /*!<CRAM page size */
+#define FMC_BCR2_CPSIZE_0 0x00010000U /*!<Bit 0 */
+#define FMC_BCR2_CPSIZE_1 0x00020000U /*!<Bit 1 */
+#define FMC_BCR2_CPSIZE_2 0x00040000U /*!<Bit 2 */
+#define FMC_BCR2_CBURSTRW 0x00080000U /*!<Write burst enable */
+
+/****************** Bit definition for FMC_BCR3 register *******************/
+#define FMC_BCR3_MBKEN 0x00000001U /*!<Memory bank enable bit */
+#define FMC_BCR3_MUXEN 0x00000002U /*!<Address/data multiplexing enable bit */
+
+#define FMC_BCR3_MTYP 0x0000000CU /*!<MTYP[1:0] bits (Memory type) */
+#define FMC_BCR3_MTYP_0 0x00000004U /*!<Bit 0 */
+#define FMC_BCR3_MTYP_1 0x00000008U /*!<Bit 1 */
+
+#define FMC_BCR3_MWID 0x00000030U /*!<MWID[1:0] bits (Memory data bus width) */
+#define FMC_BCR3_MWID_0 0x00000010U /*!<Bit 0 */
+#define FMC_BCR3_MWID_1 0x00000020U /*!<Bit 1 */
+
+#define FMC_BCR3_FACCEN 0x00000040U /*!<Flash access enable */
+#define FMC_BCR3_BURSTEN 0x00000100U /*!<Burst enable bit */
+#define FMC_BCR3_WAITPOL 0x00000200U /*!<Wait signal polarity bit */
+#define FMC_BCR3_WRAPMOD 0x00000400U /*!<Wrapped burst mode support */
+#define FMC_BCR3_WAITCFG 0x00000800U /*!<Wait timing configuration */
+#define FMC_BCR3_WREN 0x00001000U /*!<Write enable bit */
+#define FMC_BCR3_WAITEN 0x00002000U /*!<Wait enable bit */
+#define FMC_BCR3_EXTMOD 0x00004000U /*!<Extended mode enable */
+#define FMC_BCR3_ASYNCWAIT 0x00008000U /*!<Asynchronous wait */
+#define FMC_BCR3_CPSIZE 0x00070000U /*!<CRAM page size */
+#define FMC_BCR3_CPSIZE_0 0x00010000U /*!<Bit 0 */
+#define FMC_BCR3_CPSIZE_1 0x00020000U /*!<Bit 1 */
+#define FMC_BCR3_CPSIZE_2 0x00040000U /*!<Bit 2 */
+#define FMC_BCR3_CBURSTRW 0x00080000U /*!<Write burst enable */
+
+/****************** Bit definition for FMC_BCR4 register *******************/
+#define FMC_BCR4_MBKEN 0x00000001U /*!<Memory bank enable bit */
+#define FMC_BCR4_MUXEN 0x00000002U /*!<Address/data multiplexing enable bit */
+
+#define FMC_BCR4_MTYP 0x0000000CU /*!<MTYP[1:0] bits (Memory type) */
+#define FMC_BCR4_MTYP_0 0x00000004U /*!<Bit 0 */
+#define FMC_BCR4_MTYP_1 0x00000008U /*!<Bit 1 */
+
+#define FMC_BCR4_MWID 0x00000030U /*!<MWID[1:0] bits (Memory data bus width) */
+#define FMC_BCR4_MWID_0 0x00000010U /*!<Bit 0 */
+#define FMC_BCR4_MWID_1 0x00000020U /*!<Bit 1 */
+
+#define FMC_BCR4_FACCEN 0x00000040U /*!<Flash access enable */
+#define FMC_BCR4_BURSTEN 0x00000100U /*!<Burst enable bit */
+#define FMC_BCR4_WAITPOL 0x00000200U /*!<Wait signal polarity bit */
+#define FMC_BCR4_WRAPMOD 0x00000400U /*!<Wrapped burst mode support */
+#define FMC_BCR4_WAITCFG 0x00000800U /*!<Wait timing configuration */
+#define FMC_BCR4_WREN 0x00001000U /*!<Write enable bit */
+#define FMC_BCR4_WAITEN 0x00002000U /*!<Wait enable bit */
+#define FMC_BCR4_EXTMOD 0x00004000U /*!<Extended mode enable */
+#define FMC_BCR4_ASYNCWAIT 0x00008000U /*!<Asynchronous wait */
+#define FMC_BCR4_CPSIZE 0x00070000U /*!<CRAM page size */
+#define FMC_BCR4_CPSIZE_0 0x00010000U /*!<Bit 0 */
+#define FMC_BCR4_CPSIZE_1 0x00020000U /*!<Bit 1 */
+#define FMC_BCR4_CPSIZE_2 0x00040000U /*!<Bit 2 */
+#define FMC_BCR4_CBURSTRW 0x00080000U /*!<Write burst enable */
+
+/****************** Bit definition for FMC_BTR1 register ******************/
+#define FMC_BTR1_ADDSET 0x0000000FU /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FMC_BTR1_ADDSET_0 0x00000001U /*!<Bit 0 */
+#define FMC_BTR1_ADDSET_1 0x00000002U /*!<Bit 1 */
+#define FMC_BTR1_ADDSET_2 0x00000004U /*!<Bit 2 */
+#define FMC_BTR1_ADDSET_3 0x00000008U /*!<Bit 3 */
+
+#define FMC_BTR1_ADDHLD 0x000000F0U /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FMC_BTR1_ADDHLD_0 0x00000010U /*!<Bit 0 */
+#define FMC_BTR1_ADDHLD_1 0x00000020U /*!<Bit 1 */
+#define FMC_BTR1_ADDHLD_2 0x00000040U /*!<Bit 2 */
+#define FMC_BTR1_ADDHLD_3 0x00000080U /*!<Bit 3 */
+
+#define FMC_BTR1_DATAST 0x0000FF00U /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FMC_BTR1_DATAST_0 0x00000100U /*!<Bit 0 */
+#define FMC_BTR1_DATAST_1 0x00000200U /*!<Bit 1 */
+#define FMC_BTR1_DATAST_2 0x00000400U /*!<Bit 2 */
+#define FMC_BTR1_DATAST_3 0x00000800U /*!<Bit 3 */
+#define FMC_BTR1_DATAST_4 0x00001000U /*!<Bit 4 */
+#define FMC_BTR1_DATAST_5 0x00002000U /*!<Bit 5 */
+#define FMC_BTR1_DATAST_6 0x00004000U /*!<Bit 6 */
+#define FMC_BTR1_DATAST_7 0x00008000U /*!<Bit 7 */
+
+#define FMC_BTR1_BUSTURN 0x000F0000U /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define FMC_BTR1_BUSTURN_0 0x00010000U /*!<Bit 0 */
+#define FMC_BTR1_BUSTURN_1 0x00020000U /*!<Bit 1 */
+#define FMC_BTR1_BUSTURN_2 0x00040000U /*!<Bit 2 */
+#define FMC_BTR1_BUSTURN_3 0x00080000U /*!<Bit 3 */
+
+#define FMC_BTR1_CLKDIV 0x00F00000U /*!<CLKDIV[3:0] bits (Clock divide ratio) */
+#define FMC_BTR1_CLKDIV_0 0x00100000U /*!<Bit 0 */
+#define FMC_BTR1_CLKDIV_1 0x00200000U /*!<Bit 1 */
+#define FMC_BTR1_CLKDIV_2 0x00400000U /*!<Bit 2 */
+#define FMC_BTR1_CLKDIV_3 0x00800000U /*!<Bit 3 */
+
+#define FMC_BTR1_DATLAT 0x0F000000U /*!<DATLA[3:0] bits (Data latency) */
+#define FMC_BTR1_DATLAT_0 0x01000000U /*!<Bit 0 */
+#define FMC_BTR1_DATLAT_1 0x02000000U /*!<Bit 1 */
+#define FMC_BTR1_DATLAT_2 0x04000000U /*!<Bit 2 */
+#define FMC_BTR1_DATLAT_3 0x08000000U /*!<Bit 3 */
+
+#define FMC_BTR1_ACCMOD 0x30000000U /*!<ACCMOD[1:0] bits (Access mode) */
+#define FMC_BTR1_ACCMOD_0 0x10000000U /*!<Bit 0 */
+#define FMC_BTR1_ACCMOD_1 0x20000000U /*!<Bit 1 */
+
+/****************** Bit definition for FMC_BTR2 register *******************/
+#define FMC_BTR2_ADDSET 0x0000000FU /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FMC_BTR2_ADDSET_0 0x00000001U /*!<Bit 0 */
+#define FMC_BTR2_ADDSET_1 0x00000002U /*!<Bit 1 */
+#define FMC_BTR2_ADDSET_2 0x00000004U /*!<Bit 2 */
+#define FMC_BTR2_ADDSET_3 0x00000008U /*!<Bit 3 */
+
+#define FMC_BTR2_ADDHLD 0x000000F0U /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FMC_BTR2_ADDHLD_0 0x00000010U /*!<Bit 0 */
+#define FMC_BTR2_ADDHLD_1 0x00000020U /*!<Bit 1 */
+#define FMC_BTR2_ADDHLD_2 0x00000040U /*!<Bit 2 */
+#define FMC_BTR2_ADDHLD_3 0x00000080U /*!<Bit 3 */
+
+#define FMC_BTR2_DATAST 0x0000FF00U /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FMC_BTR2_DATAST_0 0x00000100U /*!<Bit 0 */
+#define FMC_BTR2_DATAST_1 0x00000200U /*!<Bit 1 */
+#define FMC_BTR2_DATAST_2 0x00000400U /*!<Bit 2 */
+#define FMC_BTR2_DATAST_3 0x00000800U /*!<Bit 3 */
+#define FMC_BTR2_DATAST_4 0x00001000U /*!<Bit 4 */
+#define FMC_BTR2_DATAST_5 0x00002000U /*!<Bit 5 */
+#define FMC_BTR2_DATAST_6 0x00004000U /*!<Bit 6 */
+#define FMC_BTR2_DATAST_7 0x00008000U /*!<Bit 7 */
+
+#define FMC_BTR2_BUSTURN 0x000F0000U /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define FMC_BTR2_BUSTURN_0 0x00010000U /*!<Bit 0 */
+#define FMC_BTR2_BUSTURN_1 0x00020000U /*!<Bit 1 */
+#define FMC_BTR2_BUSTURN_2 0x00040000U /*!<Bit 2 */
+#define FMC_BTR2_BUSTURN_3 0x00080000U /*!<Bit 3 */
+
+#define FMC_BTR2_CLKDIV 0x00F00000U /*!<CLKDIV[3:0] bits (Clock divide ratio) */
+#define FMC_BTR2_CLKDIV_0 0x00100000U /*!<Bit 0 */
+#define FMC_BTR2_CLKDIV_1 0x00200000U /*!<Bit 1 */
+#define FMC_BTR2_CLKDIV_2 0x00400000U /*!<Bit 2 */
+#define FMC_BTR2_CLKDIV_3 0x00800000U /*!<Bit 3 */
+
+#define FMC_BTR2_DATLAT 0x0F000000U /*!<DATLA[3:0] bits (Data latency) */
+#define FMC_BTR2_DATLAT_0 0x01000000U /*!<Bit 0 */
+#define FMC_BTR2_DATLAT_1 0x02000000U /*!<Bit 1 */
+#define FMC_BTR2_DATLAT_2 0x04000000U /*!<Bit 2 */
+#define FMC_BTR2_DATLAT_3 0x08000000U /*!<Bit 3 */
+
+#define FMC_BTR2_ACCMOD 0x30000000U /*!<ACCMOD[1:0] bits (Access mode) */
+#define FMC_BTR2_ACCMOD_0 0x10000000U /*!<Bit 0 */
+#define FMC_BTR2_ACCMOD_1 0x20000000U /*!<Bit 1 */
+
+/******************* Bit definition for FMC_BTR3 register *******************/
+#define FMC_BTR3_ADDSET 0x0000000FU /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FMC_BTR3_ADDSET_0 0x00000001U /*!<Bit 0 */
+#define FMC_BTR3_ADDSET_1 0x00000002U /*!<Bit 1 */
+#define FMC_BTR3_ADDSET_2 0x00000004U /*!<Bit 2 */
+#define FMC_BTR3_ADDSET_3 0x00000008U /*!<Bit 3 */
+
+#define FMC_BTR3_ADDHLD 0x000000F0U /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FMC_BTR3_ADDHLD_0 0x00000010U /*!<Bit 0 */
+#define FMC_BTR3_ADDHLD_1 0x00000020U /*!<Bit 1 */
+#define FMC_BTR3_ADDHLD_2 0x00000040U /*!<Bit 2 */
+#define FMC_BTR3_ADDHLD_3 0x00000080U /*!<Bit 3 */
+
+#define FMC_BTR3_DATAST 0x0000FF00U /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FMC_BTR3_DATAST_0 0x00000100U /*!<Bit 0 */
+#define FMC_BTR3_DATAST_1 0x00000200U /*!<Bit 1 */
+#define FMC_BTR3_DATAST_2 0x00000400U /*!<Bit 2 */
+#define FMC_BTR3_DATAST_3 0x00000800U /*!<Bit 3 */
+#define FMC_BTR3_DATAST_4 0x00001000U /*!<Bit 4 */
+#define FMC_BTR3_DATAST_5 0x00002000U /*!<Bit 5 */
+#define FMC_BTR3_DATAST_6 0x00004000U /*!<Bit 6 */
+#define FMC_BTR3_DATAST_7 0x00008000U /*!<Bit 7 */
+
+#define FMC_BTR3_BUSTURN 0x000F0000U /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define FMC_BTR3_BUSTURN_0 0x00010000U /*!<Bit 0 */
+#define FMC_BTR3_BUSTURN_1 0x00020000U /*!<Bit 1 */
+#define FMC_BTR3_BUSTURN_2 0x00040000U /*!<Bit 2 */
+#define FMC_BTR3_BUSTURN_3 0x00080000U /*!<Bit 3 */
+
+#define FMC_BTR3_CLKDIV 0x00F00000U /*!<CLKDIV[3:0] bits (Clock divide ratio) */
+#define FMC_BTR3_CLKDIV_0 0x00100000U /*!<Bit 0 */
+#define FMC_BTR3_CLKDIV_1 0x00200000U /*!<Bit 1 */
+#define FMC_BTR3_CLKDIV_2 0x00400000U /*!<Bit 2 */
+#define FMC_BTR3_CLKDIV_3 0x00800000U /*!<Bit 3 */
+
+#define FMC_BTR3_DATLAT 0x0F000000U /*!<DATLA[3:0] bits (Data latency) */
+#define FMC_BTR3_DATLAT_0 0x01000000U /*!<Bit 0 */
+#define FMC_BTR3_DATLAT_1 0x02000000U /*!<Bit 1 */
+#define FMC_BTR3_DATLAT_2 0x04000000U /*!<Bit 2 */
+#define FMC_BTR3_DATLAT_3 0x08000000U /*!<Bit 3 */
+
+#define FMC_BTR3_ACCMOD 0x30000000U /*!<ACCMOD[1:0] bits (Access mode) */
+#define FMC_BTR3_ACCMOD_0 0x10000000U /*!<Bit 0 */
+#define FMC_BTR3_ACCMOD_1 0x20000000U /*!<Bit 1 */
+
+/****************** Bit definition for FMC_BTR4 register *******************/
+#define FMC_BTR4_ADDSET 0x0000000FU /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FMC_BTR4_ADDSET_0 0x00000001U /*!<Bit 0 */
+#define FMC_BTR4_ADDSET_1 0x00000002U /*!<Bit 1 */
+#define FMC_BTR4_ADDSET_2 0x00000004U /*!<Bit 2 */
+#define FMC_BTR4_ADDSET_3 0x00000008U /*!<Bit 3 */
+
+#define FMC_BTR4_ADDHLD 0x000000F0U /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FMC_BTR4_ADDHLD_0 0x00000010U /*!<Bit 0 */
+#define FMC_BTR4_ADDHLD_1 0x00000020U /*!<Bit 1 */
+#define FMC_BTR4_ADDHLD_2 0x00000040U /*!<Bit 2 */
+#define FMC_BTR4_ADDHLD_3 0x00000080U /*!<Bit 3 */
+
+#define FMC_BTR4_DATAST 0x0000FF00U /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FMC_BTR4_DATAST_0 0x00000100U /*!<Bit 0 */
+#define FMC_BTR4_DATAST_1 0x00000200U /*!<Bit 1 */
+#define FMC_BTR4_DATAST_2 0x00000400U /*!<Bit 2 */
+#define FMC_BTR4_DATAST_3 0x00000800U /*!<Bit 3 */
+#define FMC_BTR4_DATAST_4 0x00001000U /*!<Bit 4 */
+#define FMC_BTR4_DATAST_5 0x00002000U /*!<Bit 5 */
+#define FMC_BTR4_DATAST_6 0x00004000U /*!<Bit 6 */
+#define FMC_BTR4_DATAST_7 0x00008000U /*!<Bit 7 */
+
+#define FMC_BTR4_BUSTURN 0x000F0000U /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define FMC_BTR4_BUSTURN_0 0x00010000U /*!<Bit 0 */
+#define FMC_BTR4_BUSTURN_1 0x00020000U /*!<Bit 1 */
+#define FMC_BTR4_BUSTURN_2 0x00040000U /*!<Bit 2 */
+#define FMC_BTR4_BUSTURN_3 0x00080000U /*!<Bit 3 */
+
+#define FMC_BTR4_CLKDIV 0x00F00000U /*!<CLKDIV[3:0] bits (Clock divide ratio) */
+#define FMC_BTR4_CLKDIV_0 0x00100000U /*!<Bit 0 */
+#define FMC_BTR4_CLKDIV_1 0x00200000U /*!<Bit 1 */
+#define FMC_BTR4_CLKDIV_2 0x00400000U /*!<Bit 2 */
+#define FMC_BTR4_CLKDIV_3 0x00800000U /*!<Bit 3 */
+
+#define FMC_BTR4_DATLAT 0x0F000000U /*!<DATLA[3:0] bits (Data latency) */
+#define FMC_BTR4_DATLAT_0 0x01000000U /*!<Bit 0 */
+#define FMC_BTR4_DATLAT_1 0x02000000U /*!<Bit 1 */
+#define FMC_BTR4_DATLAT_2 0x04000000U /*!<Bit 2 */
+#define FMC_BTR4_DATLAT_3 0x08000000U /*!<Bit 3 */
+
+#define FMC_BTR4_ACCMOD 0x30000000U /*!<ACCMOD[1:0] bits (Access mode) */
+#define FMC_BTR4_ACCMOD_0 0x10000000U /*!<Bit 0 */
+#define FMC_BTR4_ACCMOD_1 0x20000000U /*!<Bit 1 */
+
+/****************** Bit definition for FMC_BWTR1 register ******************/
+#define FMC_BWTR1_ADDSET 0x0000000FU /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FMC_BWTR1_ADDSET_0 0x00000001U /*!<Bit 0 */
+#define FMC_BWTR1_ADDSET_1 0x00000002U /*!<Bit 1 */
+#define FMC_BWTR1_ADDSET_2 0x00000004U /*!<Bit 2 */
+#define FMC_BWTR1_ADDSET_3 0x00000008U /*!<Bit 3 */
+
+#define FMC_BWTR1_ADDHLD 0x000000F0U /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FMC_BWTR1_ADDHLD_0 0x00000010U /*!<Bit 0 */
+#define FMC_BWTR1_ADDHLD_1 0x00000020U /*!<Bit 1 */
+#define FMC_BWTR1_ADDHLD_2 0x00000040U /*!<Bit 2 */
+#define FMC_BWTR1_ADDHLD_3 0x00000080U /*!<Bit 3 */
+
+#define FMC_BWTR1_DATAST 0x0000FF00U /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FMC_BWTR1_DATAST_0 0x00000100U /*!<Bit 0 */
+#define FMC_BWTR1_DATAST_1 0x00000200U /*!<Bit 1 */
+#define FMC_BWTR1_DATAST_2 0x00000400U /*!<Bit 2 */
+#define FMC_BWTR1_DATAST_3 0x00000800U /*!<Bit 3 */
+#define FMC_BWTR1_DATAST_4 0x00001000U /*!<Bit 4 */
+#define FMC_BWTR1_DATAST_5 0x00002000U /*!<Bit 5 */
+#define FMC_BWTR1_DATAST_6 0x00004000U /*!<Bit 6 */
+#define FMC_BWTR1_DATAST_7 0x00008000U /*!<Bit 7 */
+
+#define FMC_BWTR1_BUSTURN 0x000F0000U /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
+#define FMC_BWTR1_BUSTURN_0 0x00010000U /*!<Bit 0 */
+#define FMC_BWTR1_BUSTURN_1 0x00020000U /*!<Bit 1 */
+#define FMC_BWTR1_BUSTURN_2 0x00040000U /*!<Bit 2 */
+#define FMC_BWTR1_BUSTURN_3 0x00080000U /*!<Bit 3 */
+
+#define FMC_BWTR1_ACCMOD 0x30000000U /*!<ACCMOD[1:0] bits (Access mode) */
+#define FMC_BWTR1_ACCMOD_0 0x10000000U /*!<Bit 0 */
+#define FMC_BWTR1_ACCMOD_1 0x20000000U /*!<Bit 1 */
+
+/****************** Bit definition for FMC_BWTR2 register ******************/
+#define FMC_BWTR2_ADDSET 0x0000000FU /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FMC_BWTR2_ADDSET_0 0x00000001U /*!<Bit 0 */
+#define FMC_BWTR2_ADDSET_1 0x00000002U /*!<Bit 1 */
+#define FMC_BWTR2_ADDSET_2 0x00000004U /*!<Bit 2 */
+#define FMC_BWTR2_ADDSET_3 0x00000008U /*!<Bit 3 */
+
+#define FMC_BWTR2_ADDHLD 0x000000F0U /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FMC_BWTR2_ADDHLD_0 0x00000010U /*!<Bit 0 */
+#define FMC_BWTR2_ADDHLD_1 0x00000020U /*!<Bit 1 */
+#define FMC_BWTR2_ADDHLD_2 0x00000040U /*!<Bit 2 */
+#define FMC_BWTR2_ADDHLD_3 0x00000080U /*!<Bit 3 */
+
+#define FMC_BWTR2_DATAST 0x0000FF00U /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FMC_BWTR2_DATAST_0 0x00000100U /*!<Bit 0 */
+#define FMC_BWTR2_DATAST_1 0x00000200U /*!<Bit 1 */
+#define FMC_BWTR2_DATAST_2 0x00000400U /*!<Bit 2 */
+#define FMC_BWTR2_DATAST_3 0x00000800U /*!<Bit 3 */
+#define FMC_BWTR2_DATAST_4 0x00001000U /*!<Bit 4 */
+#define FMC_BWTR2_DATAST_5 0x00002000U /*!<Bit 5 */
+#define FMC_BWTR2_DATAST_6 0x00004000U /*!<Bit 6 */
+#define FMC_BWTR2_DATAST_7 0x00008000U /*!<Bit 7 */
+
+#define FMC_BWTR2_BUSTURN 0x000F0000U /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
+#define FMC_BWTR2_BUSTURN_0 0x00010000U /*!<Bit 0 */
+#define FMC_BWTR2_BUSTURN_1 0x00020000U /*!<Bit 1 */
+#define FMC_BWTR2_BUSTURN_2 0x00040000U /*!<Bit 2 */
+#define FMC_BWTR2_BUSTURN_3 0x00080000U /*!<Bit 3 */
+
+#define FMC_BWTR2_ACCMOD 0x30000000U /*!<ACCMOD[1:0] bits (Access mode) */
+#define FMC_BWTR2_ACCMOD_0 0x10000000U /*!<Bit 0 */
+#define FMC_BWTR2_ACCMOD_1 0x20000000U /*!<Bit 1 */
+
+/****************** Bit definition for FMC_BWTR3 register ******************/
+#define FMC_BWTR3_ADDSET 0x0000000FU /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FMC_BWTR3_ADDSET_0 0x00000001U /*!<Bit 0 */
+#define FMC_BWTR3_ADDSET_1 0x00000002U /*!<Bit 1 */
+#define FMC_BWTR3_ADDSET_2 0x00000004U /*!<Bit 2 */
+#define FMC_BWTR3_ADDSET_3 0x00000008U /*!<Bit 3 */
+
+#define FMC_BWTR3_ADDHLD 0x000000F0U /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FMC_BWTR3_ADDHLD_0 0x00000010U /*!<Bit 0 */
+#define FMC_BWTR3_ADDHLD_1 0x00000020U /*!<Bit 1 */
+#define FMC_BWTR3_ADDHLD_2 0x00000040U /*!<Bit 2 */
+#define FMC_BWTR3_ADDHLD_3 0x00000080U /*!<Bit 3 */
+
+#define FMC_BWTR3_DATAST 0x0000FF00U /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FMC_BWTR3_DATAST_0 0x00000100U /*!<Bit 0 */
+#define FMC_BWTR3_DATAST_1 0x00000200U /*!<Bit 1 */
+#define FMC_BWTR3_DATAST_2 0x00000400U /*!<Bit 2 */
+#define FMC_BWTR3_DATAST_3 0x00000800U /*!<Bit 3 */
+#define FMC_BWTR3_DATAST_4 0x00001000U /*!<Bit 4 */
+#define FMC_BWTR3_DATAST_5 0x00002000U /*!<Bit 5 */
+#define FMC_BWTR3_DATAST_6 0x00004000U /*!<Bit 6 */
+#define FMC_BWTR3_DATAST_7 0x00008000U /*!<Bit 7 */
+
+#define FMC_BWTR3_BUSTURN 0x000F0000U /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
+#define FMC_BWTR3_BUSTURN_0 0x00010000U /*!<Bit 0 */
+#define FMC_BWTR3_BUSTURN_1 0x00020000U /*!<Bit 1 */
+#define FMC_BWTR3_BUSTURN_2 0x00040000U /*!<Bit 2 */
+#define FMC_BWTR3_BUSTURN_3 0x00080000U /*!<Bit 3 */
+
+#define FMC_BWTR3_ACCMOD 0x30000000U /*!<ACCMOD[1:0] bits (Access mode) */
+#define FMC_BWTR3_ACCMOD_0 0x10000000U /*!<Bit 0 */
+#define FMC_BWTR3_ACCMOD_1 0x20000000U /*!<Bit 1 */
+
+/****************** Bit definition for FMC_BWTR4 register ******************/
+#define FMC_BWTR4_ADDSET 0x0000000FU /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FMC_BWTR4_ADDSET_0 0x00000001U /*!<Bit 0 */
+#define FMC_BWTR4_ADDSET_1 0x00000002U /*!<Bit 1 */
+#define FMC_BWTR4_ADDSET_2 0x00000004U /*!<Bit 2 */
+#define FMC_BWTR4_ADDSET_3 0x00000008U /*!<Bit 3 */
+
+#define FMC_BWTR4_ADDHLD 0x000000F0U /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FMC_BWTR4_ADDHLD_0 0x00000010U /*!<Bit 0 */
+#define FMC_BWTR4_ADDHLD_1 0x00000020U /*!<Bit 1 */
+#define FMC_BWTR4_ADDHLD_2 0x00000040U /*!<Bit 2 */
+#define FMC_BWTR4_ADDHLD_3 0x00000080U /*!<Bit 3 */
+
+#define FMC_BWTR4_DATAST 0x0000FF00U /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FMC_BWTR4_DATAST_0 0x00000100U /*!<Bit 0 */
+#define FMC_BWTR4_DATAST_1 0x00000200U /*!<Bit 1 */
+#define FMC_BWTR4_DATAST_2 0x00000400U /*!<Bit 2 */
+#define FMC_BWTR4_DATAST_3 0x00000800U /*!<Bit 3 */
+#define FMC_BWTR4_DATAST_4 0x00001000U /*!<Bit 4 */
+#define FMC_BWTR4_DATAST_5 0x00002000U /*!<Bit 5 */
+#define FMC_BWTR4_DATAST_6 0x00004000U /*!<Bit 6 */
+#define FMC_BWTR4_DATAST_7 0x00008000U /*!<Bit 7 */
+
+#define FMC_BWTR4_BUSTURN 0x000F0000U /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
+#define FMC_BWTR4_BUSTURN_0 0x00010000U /*!<Bit 0 */
+#define FMC_BWTR4_BUSTURN_1 0x00020000U /*!<Bit 1 */
+#define FMC_BWTR4_BUSTURN_2 0x00040000U /*!<Bit 2 */
+#define FMC_BWTR4_BUSTURN_3 0x00080000U /*!<Bit 3 */
+
+#define FMC_BWTR4_ACCMOD 0x30000000U /*!<ACCMOD[1:0] bits (Access mode) */
+#define FMC_BWTR4_ACCMOD_0 0x10000000U /*!<Bit 0 */
+#define FMC_BWTR4_ACCMOD_1 0x20000000U /*!<Bit 1 */
+
+/****************** Bit definition for FMC_PCR2 register *******************/
+#define FMC_PCR2_PWAITEN 0x00000002U /*!<Wait feature enable bit */
+#define FMC_PCR2_PBKEN 0x00000004U /*!<PC Card/NAND Flash memory bank enable bit */
+#define FMC_PCR2_PTYP 0x00000008U /*!<Memory type */
+
+#define FMC_PCR2_PWID 0x00000030U /*!<PWID[1:0] bits (NAND Flash databus width) */
+#define FMC_PCR2_PWID_0 0x00000010U /*!<Bit 0 */
+#define FMC_PCR2_PWID_1 0x00000020U /*!<Bit 1 */
+
+#define FMC_PCR2_ECCEN 0x00000040U /*!<ECC computation logic enable bit */
+
+#define FMC_PCR2_TCLR 0x00001E00U /*!<TCLR[3:0] bits (CLE to RE delay) */
+#define FMC_PCR2_TCLR_0 0x00000200U /*!<Bit 0 */
+#define FMC_PCR2_TCLR_1 0x00000400U /*!<Bit 1 */
+#define FMC_PCR2_TCLR_2 0x00000800U /*!<Bit 2 */
+#define FMC_PCR2_TCLR_3 0x00001000U /*!<Bit 3 */
+
+#define FMC_PCR2_TAR 0x0001E000U /*!<TAR[3:0] bits (ALE to RE delay) */
+#define FMC_PCR2_TAR_0 0x00002000U /*!<Bit 0 */
+#define FMC_PCR2_TAR_1 0x00004000U /*!<Bit 1 */
+#define FMC_PCR2_TAR_2 0x00008000U /*!<Bit 2 */
+#define FMC_PCR2_TAR_3 0x00010000U /*!<Bit 3 */
+
+#define FMC_PCR2_ECCPS 0x000E0000U /*!<ECCPS[1:0] bits (ECC page size) */
+#define FMC_PCR2_ECCPS_0 0x00020000U /*!<Bit 0 */
+#define FMC_PCR2_ECCPS_1 0x00040000U /*!<Bit 1 */
+#define FMC_PCR2_ECCPS_2 0x00080000U /*!<Bit 2 */
+
+/****************** Bit definition for FMC_PCR3 register *******************/
+#define FMC_PCR3_PWAITEN 0x00000002U /*!<Wait feature enable bit */
+#define FMC_PCR3_PBKEN 0x00000004U /*!<PC Card/NAND Flash memory bank enable bit */
+#define FMC_PCR3_PTYP 0x00000008U /*!<Memory type */
+
+#define FMC_PCR3_PWID 0x00000030U /*!<PWID[1:0] bits (NAND Flash databus width) */
+#define FMC_PCR3_PWID_0 0x00000010U /*!<Bit 0 */
+#define FMC_PCR3_PWID_1 0x00000020U /*!<Bit 1 */
+
+#define FMC_PCR3_ECCEN 0x00000040U /*!<ECC computation logic enable bit */
+
+#define FMC_PCR3_TCLR 0x00001E00U /*!<TCLR[3:0] bits (CLE to RE delay) */
+#define FMC_PCR3_TCLR_0 0x00000200U /*!<Bit 0 */
+#define FMC_PCR3_TCLR_1 0x00000400U /*!<Bit 1 */
+#define FMC_PCR3_TCLR_2 0x00000800U /*!<Bit 2 */
+#define FMC_PCR3_TCLR_3 0x00001000U /*!<Bit 3 */
+
+#define FMC_PCR3_TAR 0x0001E000U /*!<TAR[3:0] bits (ALE to RE delay) */
+#define FMC_PCR3_TAR_0 0x00002000U /*!<Bit 0 */
+#define FMC_PCR3_TAR_1 0x00004000U /*!<Bit 1 */
+#define FMC_PCR3_TAR_2 0x00008000U /*!<Bit 2 */
+#define FMC_PCR3_TAR_3 0x00010000U /*!<Bit 3 */
+
+#define FMC_PCR3_ECCPS 0x000E0000U /*!<ECCPS[2:0] bits (ECC page size) */
+#define FMC_PCR3_ECCPS_0 0x00020000U /*!<Bit 0 */
+#define FMC_PCR3_ECCPS_1 0x00040000U /*!<Bit 1 */
+#define FMC_PCR3_ECCPS_2 0x00080000U /*!<Bit 2 */
+
+/****************** Bit definition for FMC_PCR4 register *******************/
+#define FMC_PCR4_PWAITEN 0x00000002U /*!<Wait feature enable bit */
+#define FMC_PCR4_PBKEN 0x00000004U /*!<PC Card/NAND Flash memory bank enable bit */
+#define FMC_PCR4_PTYP 0x00000008U /*!<Memory type */
+
+#define FMC_PCR4_PWID 0x00000030U /*!<PWID[1:0] bits (NAND Flash databus width) */
+#define FMC_PCR4_PWID_0 0x00000010U /*!<Bit 0 */
+#define FMC_PCR4_PWID_1 0x00000020U /*!<Bit 1 */
+
+#define FMC_PCR4_ECCEN 0x00000040U /*!<ECC computation logic enable bit */
+
+#define FMC_PCR4_TCLR 0x00001E00U /*!<TCLR[3:0] bits (CLE to RE delay) */
+#define FMC_PCR4_TCLR_0 0x00000200U /*!<Bit 0 */
+#define FMC_PCR4_TCLR_1 0x00000400U /*!<Bit 1 */
+#define FMC_PCR4_TCLR_2 0x00000800U /*!<Bit 2 */
+#define FMC_PCR4_TCLR_3 0x00001000U /*!<Bit 3 */
+
+#define FMC_PCR4_TAR 0x0001E000U /*!<TAR[3:0] bits (ALE to RE delay) */
+#define FMC_PCR4_TAR_0 0x00002000U /*!<Bit 0 */
+#define FMC_PCR4_TAR_1 0x00004000U /*!<Bit 1 */
+#define FMC_PCR4_TAR_2 0x00008000U /*!<Bit 2 */
+#define FMC_PCR4_TAR_3 0x00010000U /*!<Bit 3 */
+
+#define FMC_PCR4_ECCPS 0x000E0000U /*!<ECCPS[2:0] bits (ECC page size) */
+#define FMC_PCR4_ECCPS_0 0x00020000U /*!<Bit 0 */
+#define FMC_PCR4_ECCPS_1 0x00040000U /*!<Bit 1 */
+#define FMC_PCR4_ECCPS_2 0x00080000U /*!<Bit 2 */
+
+/******************* Bit definition for FMC_SR2 register *******************/
+#define FMC_SR2_IRS 0x01U /*!<Interrupt Rising Edge status */
+#define FMC_SR2_ILS 0x02U /*!<Interrupt Level status */
+#define FMC_SR2_IFS 0x04U /*!<Interrupt Falling Edge status */
+#define FMC_SR2_IREN 0x08U /*!<Interrupt Rising Edge detection Enable bit */
+#define FMC_SR2_ILEN 0x10U /*!<Interrupt Level detection Enable bit */
+#define FMC_SR2_IFEN 0x20U /*!<Interrupt Falling Edge detection Enable bit */
+#define FMC_SR2_FEMPT 0x40U /*!<FIFO empty */
+
+/******************* Bit definition for FMC_SR3 register *******************/
+#define FMC_SR3_IRS 0x01U /*!<Interrupt Rising Edge status */
+#define FMC_SR3_ILS 0x02U /*!<Interrupt Level status */
+#define FMC_SR3_IFS 0x04U /*!<Interrupt Falling Edge status */
+#define FMC_SR3_IREN 0x08U /*!<Interrupt Rising Edge detection Enable bit */
+#define FMC_SR3_ILEN 0x10U /*!<Interrupt Level detection Enable bit */
+#define FMC_SR3_IFEN 0x20U /*!<Interrupt Falling Edge detection Enable bit */
+#define FMC_SR3_FEMPT 0x40U /*!<FIFO empty */
+
+/******************* Bit definition for FMC_SR4 register *******************/
+#define FMC_SR4_IRS 0x01U /*!<Interrupt Rising Edge status */
+#define FMC_SR4_ILS 0x02U /*!<Interrupt Level status */
+#define FMC_SR4_IFS 0x04U /*!<Interrupt Falling Edge status */
+#define FMC_SR4_IREN 0x08U /*!<Interrupt Rising Edge detection Enable bit */
+#define FMC_SR4_ILEN 0x10U /*!<Interrupt Level detection Enable bit */
+#define FMC_SR4_IFEN 0x20U /*!<Interrupt Falling Edge detection Enable bit */
+#define FMC_SR4_FEMPT 0x40U /*!<FIFO empty */
+
+/****************** Bit definition for FMC_PMEM2 register ******************/
+#define FMC_PMEM2_MEMSET2 0x000000FFU /*!<MEMSET2[7:0] bits (Common memory 2 setup time) */
+#define FMC_PMEM2_MEMSET2_0 0x00000001U /*!<Bit 0 */
+#define FMC_PMEM2_MEMSET2_1 0x00000002U /*!<Bit 1 */
+#define FMC_PMEM2_MEMSET2_2 0x00000004U /*!<Bit 2 */
+#define FMC_PMEM2_MEMSET2_3 0x00000008U /*!<Bit 3 */
+#define FMC_PMEM2_MEMSET2_4 0x00000010U /*!<Bit 4 */
+#define FMC_PMEM2_MEMSET2_5 0x00000020U /*!<Bit 5 */
+#define FMC_PMEM2_MEMSET2_6 0x00000040U /*!<Bit 6 */
+#define FMC_PMEM2_MEMSET2_7 0x00000080U /*!<Bit 7 */
+
+#define FMC_PMEM2_MEMWAIT2 0x0000FF00U /*!<MEMWAIT2[7:0] bits (Common memory 2 wait time) */
+#define FMC_PMEM2_MEMWAIT2_0 0x00000100U /*!<Bit 0 */
+#define FMC_PMEM2_MEMWAIT2_1 0x00000200U /*!<Bit 1 */
+#define FMC_PMEM2_MEMWAIT2_2 0x00000400U /*!<Bit 2 */
+#define FMC_PMEM2_MEMWAIT2_3 0x00000800U /*!<Bit 3 */
+#define FMC_PMEM2_MEMWAIT2_4 0x00001000U /*!<Bit 4 */
+#define FMC_PMEM2_MEMWAIT2_5 0x00002000U /*!<Bit 5 */
+#define FMC_PMEM2_MEMWAIT2_6 0x00004000U /*!<Bit 6 */
+#define FMC_PMEM2_MEMWAIT2_7 0x00008000U /*!<Bit 7 */
+
+#define FMC_PMEM2_MEMHOLD2 0x00FF0000U /*!<MEMHOLD2[7:0] bits (Common memory 2 hold time) */
+#define FMC_PMEM2_MEMHOLD2_0 0x00010000U /*!<Bit 0 */
+#define FMC_PMEM2_MEMHOLD2_1 0x00020000U /*!<Bit 1 */
+#define FMC_PMEM2_MEMHOLD2_2 0x00040000U /*!<Bit 2 */
+#define FMC_PMEM2_MEMHOLD2_3 0x00080000U /*!<Bit 3 */
+#define FMC_PMEM2_MEMHOLD2_4 0x00100000U /*!<Bit 4 */
+#define FMC_PMEM2_MEMHOLD2_5 0x00200000U /*!<Bit 5 */
+#define FMC_PMEM2_MEMHOLD2_6 0x00400000U /*!<Bit 6 */
+#define FMC_PMEM2_MEMHOLD2_7 0x00800000U /*!<Bit 7 */
+
+#define FMC_PMEM2_MEMHIZ2 0xFF000000U /*!<MEMHIZ2[7:0] bits (Common memory 2 databus HiZ time) */
+#define FMC_PMEM2_MEMHIZ2_0 0x01000000U /*!<Bit 0 */
+#define FMC_PMEM2_MEMHIZ2_1 0x02000000U /*!<Bit 1 */
+#define FMC_PMEM2_MEMHIZ2_2 0x04000000U /*!<Bit 2 */
+#define FMC_PMEM2_MEMHIZ2_3 0x08000000U /*!<Bit 3 */
+#define FMC_PMEM2_MEMHIZ2_4 0x10000000U /*!<Bit 4 */
+#define FMC_PMEM2_MEMHIZ2_5 0x20000000U /*!<Bit 5 */
+#define FMC_PMEM2_MEMHIZ2_6 0x40000000U /*!<Bit 6 */
+#define FMC_PMEM2_MEMHIZ2_7 0x80000000U /*!<Bit 7 */
+
+/****************** Bit definition for FMC_PMEM3 register ******************/
+#define FMC_PMEM3_MEMSET3 0x000000FFU /*!<MEMSET3[7:0] bits (Common memory 3 setup time) */
+#define FMC_PMEM3_MEMSET3_0 0x00000001U /*!<Bit 0 */
+#define FMC_PMEM3_MEMSET3_1 0x00000002U /*!<Bit 1 */
+#define FMC_PMEM3_MEMSET3_2 0x00000004U /*!<Bit 2 */
+#define FMC_PMEM3_MEMSET3_3 0x00000008U /*!<Bit 3 */
+#define FMC_PMEM3_MEMSET3_4 0x00000010U /*!<Bit 4 */
+#define FMC_PMEM3_MEMSET3_5 0x00000020U /*!<Bit 5 */
+#define FMC_PMEM3_MEMSET3_6 0x00000040U /*!<Bit 6 */
+#define FMC_PMEM3_MEMSET3_7 0x00000080U /*!<Bit 7 */
+
+#define FMC_PMEM3_MEMWAIT3 0x0000FF00U /*!<MEMWAIT3[7:0] bits (Common memory 3 wait time) */
+#define FMC_PMEM3_MEMWAIT3_0 0x00000100U /*!<Bit 0 */
+#define FMC_PMEM3_MEMWAIT3_1 0x00000200U /*!<Bit 1 */
+#define FMC_PMEM3_MEMWAIT3_2 0x00000400U /*!<Bit 2 */
+#define FMC_PMEM3_MEMWAIT3_3 0x00000800U /*!<Bit 3 */
+#define FMC_PMEM3_MEMWAIT3_4 0x00001000U /*!<Bit 4 */
+#define FMC_PMEM3_MEMWAIT3_5 0x00002000U /*!<Bit 5 */
+#define FMC_PMEM3_MEMWAIT3_6 0x00004000U /*!<Bit 6 */
+#define FMC_PMEM3_MEMWAIT3_7 0x00008000U /*!<Bit 7 */
+
+#define FMC_PMEM3_MEMHOLD3 0x00FF0000U /*!<MEMHOLD3[7:0] bits (Common memory 3 hold time) */
+#define FMC_PMEM3_MEMHOLD3_0 0x00010000U /*!<Bit 0 */
+#define FMC_PMEM3_MEMHOLD3_1 0x00020000U /*!<Bit 1 */
+#define FMC_PMEM3_MEMHOLD3_2 0x00040000U /*!<Bit 2 */
+#define FMC_PMEM3_MEMHOLD3_3 0x00080000U /*!<Bit 3 */
+#define FMC_PMEM3_MEMHOLD3_4 0x00100000U /*!<Bit 4 */
+#define FMC_PMEM3_MEMHOLD3_5 0x00200000U /*!<Bit 5 */
+#define FMC_PMEM3_MEMHOLD3_6 0x00400000U /*!<Bit 6 */
+#define FMC_PMEM3_MEMHOLD3_7 0x00800000U /*!<Bit 7 */
+
+#define FMC_PMEM3_MEMHIZ3 0xFF000000U /*!<MEMHIZ3[7:0] bits (Common memory 3 databus HiZ time) */
+#define FMC_PMEM3_MEMHIZ3_0 0x01000000U /*!<Bit 0 */
+#define FMC_PMEM3_MEMHIZ3_1 0x02000000U /*!<Bit 1 */
+#define FMC_PMEM3_MEMHIZ3_2 0x04000000U /*!<Bit 2 */
+#define FMC_PMEM3_MEMHIZ3_3 0x08000000U /*!<Bit 3 */
+#define FMC_PMEM3_MEMHIZ3_4 0x10000000U /*!<Bit 4 */
+#define FMC_PMEM3_MEMHIZ3_5 0x20000000U /*!<Bit 5 */
+#define FMC_PMEM3_MEMHIZ3_6 0x40000000U /*!<Bit 6 */
+#define FMC_PMEM3_MEMHIZ3_7 0x80000000U /*!<Bit 7 */
+
+/****************** Bit definition for FMC_PMEM4 register ******************/
+#define FMC_PMEM4_MEMSET4 0x000000FFU /*!<MEMSET4[7:0] bits (Common memory 4 setup time) */
+#define FMC_PMEM4_MEMSET4_0 0x00000001U /*!<Bit 0 */
+#define FMC_PMEM4_MEMSET4_1 0x00000002U /*!<Bit 1 */
+#define FMC_PMEM4_MEMSET4_2 0x00000004U /*!<Bit 2 */
+#define FMC_PMEM4_MEMSET4_3 0x00000008U /*!<Bit 3 */
+#define FMC_PMEM4_MEMSET4_4 0x00000010U /*!<Bit 4 */
+#define FMC_PMEM4_MEMSET4_5 0x00000020U /*!<Bit 5 */
+#define FMC_PMEM4_MEMSET4_6 0x00000040U /*!<Bit 6 */
+#define FMC_PMEM4_MEMSET4_7 0x00000080U /*!<Bit 7 */
+
+#define FMC_PMEM4_MEMWAIT4 0x0000FF00U /*!<MEMWAIT4[7:0] bits (Common memory 4 wait time) */
+#define FMC_PMEM4_MEMWAIT4_0 0x00000100U /*!<Bit 0 */
+#define FMC_PMEM4_MEMWAIT4_1 0x00000200U /*!<Bit 1 */
+#define FMC_PMEM4_MEMWAIT4_2 0x00000400U /*!<Bit 2 */
+#define FMC_PMEM4_MEMWAIT4_3 0x00000800U /*!<Bit 3 */
+#define FMC_PMEM4_MEMWAIT4_4 0x00001000U /*!<Bit 4 */
+#define FMC_PMEM4_MEMWAIT4_5 0x00002000U /*!<Bit 5 */
+#define FMC_PMEM4_MEMWAIT4_6 0x00004000U /*!<Bit 6 */
+#define FMC_PMEM4_MEMWAIT4_7 0x00008000U /*!<Bit 7 */
+
+#define FMC_PMEM4_MEMHOLD4 0x00FF0000U /*!<MEMHOLD4[7:0] bits (Common memory 4 hold time) */
+#define FMC_PMEM4_MEMHOLD4_0 0x00010000U /*!<Bit 0 */
+#define FMC_PMEM4_MEMHOLD4_1 0x00020000U /*!<Bit 1 */
+#define FMC_PMEM4_MEMHOLD4_2 0x00040000U /*!<Bit 2 */
+#define FMC_PMEM4_MEMHOLD4_3 0x00080000U /*!<Bit 3 */
+#define FMC_PMEM4_MEMHOLD4_4 0x00100000U /*!<Bit 4 */
+#define FMC_PMEM4_MEMHOLD4_5 0x00200000U /*!<Bit 5 */
+#define FMC_PMEM4_MEMHOLD4_6 0x00400000U /*!<Bit 6 */
+#define FMC_PMEM4_MEMHOLD4_7 0x00800000U /*!<Bit 7 */
+
+#define FMC_PMEM4_MEMHIZ4 0xFF000000U /*!<MEMHIZ4[7:0] bits (Common memory 4 databus HiZ time) */
+#define FMC_PMEM4_MEMHIZ4_0 0x01000000U /*!<Bit 0 */
+#define FMC_PMEM4_MEMHIZ4_1 0x02000000U /*!<Bit 1 */
+#define FMC_PMEM4_MEMHIZ4_2 0x04000000U /*!<Bit 2 */
+#define FMC_PMEM4_MEMHIZ4_3 0x08000000U /*!<Bit 3 */
+#define FMC_PMEM4_MEMHIZ4_4 0x10000000U /*!<Bit 4 */
+#define FMC_PMEM4_MEMHIZ4_5 0x20000000U /*!<Bit 5 */
+#define FMC_PMEM4_MEMHIZ4_6 0x40000000U /*!<Bit 6 */
+#define FMC_PMEM4_MEMHIZ4_7 0x80000000U /*!<Bit 7 */
+
+/****************** Bit definition for FMC_PATT2 register ******************/
+#define FMC_PATT2_ATTSET2 0x000000FFU /*!<ATTSET2[7:0] bits (Attribute memory 2 setup time) */
+#define FMC_PATT2_ATTSET2_0 0x00000001U /*!<Bit 0 */
+#define FMC_PATT2_ATTSET2_1 0x00000002U /*!<Bit 1 */
+#define FMC_PATT2_ATTSET2_2 0x00000004U /*!<Bit 2 */
+#define FMC_PATT2_ATTSET2_3 0x00000008U /*!<Bit 3 */
+#define FMC_PATT2_ATTSET2_4 0x00000010U /*!<Bit 4 */
+#define FMC_PATT2_ATTSET2_5 0x00000020U /*!<Bit 5 */
+#define FMC_PATT2_ATTSET2_6 0x00000040U /*!<Bit 6 */
+#define FMC_PATT2_ATTSET2_7 0x00000080U /*!<Bit 7 */
+
+#define FMC_PATT2_ATTWAIT2 0x0000FF00U /*!<ATTWAIT2[7:0] bits (Attribute memory 2 wait time) */
+#define FMC_PATT2_ATTWAIT2_0 0x00000100U /*!<Bit 0 */
+#define FMC_PATT2_ATTWAIT2_1 0x00000200U /*!<Bit 1 */
+#define FMC_PATT2_ATTWAIT2_2 0x00000400U /*!<Bit 2 */
+#define FMC_PATT2_ATTWAIT2_3 0x00000800U /*!<Bit 3 */
+#define FMC_PATT2_ATTWAIT2_4 0x00001000U /*!<Bit 4 */
+#define FMC_PATT2_ATTWAIT2_5 0x00002000U /*!<Bit 5 */
+#define FMC_PATT2_ATTWAIT2_6 0x00004000U /*!<Bit 6 */
+#define FMC_PATT2_ATTWAIT2_7 0x00008000U /*!<Bit 7 */
+
+#define FMC_PATT2_ATTHOLD2 0x00FF0000U /*!<ATTHOLD2[7:0] bits (Attribute memory 2 hold time) */
+#define FMC_PATT2_ATTHOLD2_0 0x00010000U /*!<Bit 0 */
+#define FMC_PATT2_ATTHOLD2_1 0x00020000U /*!<Bit 1 */
+#define FMC_PATT2_ATTHOLD2_2 0x00040000U /*!<Bit 2 */
+#define FMC_PATT2_ATTHOLD2_3 0x00080000U /*!<Bit 3 */
+#define FMC_PATT2_ATTHOLD2_4 0x00100000U /*!<Bit 4 */
+#define FMC_PATT2_ATTHOLD2_5 0x00200000U /*!<Bit 5 */
+#define FMC_PATT2_ATTHOLD2_6 0x00400000U /*!<Bit 6 */
+#define FMC_PATT2_ATTHOLD2_7 0x00800000U /*!<Bit 7 */
+
+#define FMC_PATT2_ATTHIZ2 0xFF000000U /*!<ATTHIZ2[7:0] bits (Attribute memory 2 databus HiZ time) */
+#define FMC_PATT2_ATTHIZ2_0 0x01000000U /*!<Bit 0 */
+#define FMC_PATT2_ATTHIZ2_1 0x02000000U /*!<Bit 1 */
+#define FMC_PATT2_ATTHIZ2_2 0x04000000U /*!<Bit 2 */
+#define FMC_PATT2_ATTHIZ2_3 0x08000000U /*!<Bit 3 */
+#define FMC_PATT2_ATTHIZ2_4 0x10000000U /*!<Bit 4 */
+#define FMC_PATT2_ATTHIZ2_5 0x20000000U /*!<Bit 5 */
+#define FMC_PATT2_ATTHIZ2_6 0x40000000U /*!<Bit 6 */
+#define FMC_PATT2_ATTHIZ2_7 0x80000000U /*!<Bit 7 */
+
+/****************** Bit definition for FMC_PATT3 register ******************/
+#define FMC_PATT3_ATTSET3 0x000000FFU /*!<ATTSET3[7:0] bits (Attribute memory 3 setup time) */
+#define FMC_PATT3_ATTSET3_0 0x00000001U /*!<Bit 0 */
+#define FMC_PATT3_ATTSET3_1 0x00000002U /*!<Bit 1 */
+#define FMC_PATT3_ATTSET3_2 0x00000004U /*!<Bit 2 */
+#define FMC_PATT3_ATTSET3_3 0x00000008U /*!<Bit 3 */
+#define FMC_PATT3_ATTSET3_4 0x00000010U /*!<Bit 4 */
+#define FMC_PATT3_ATTSET3_5 0x00000020U /*!<Bit 5 */
+#define FMC_PATT3_ATTSET3_6 0x00000040U /*!<Bit 6 */
+#define FMC_PATT3_ATTSET3_7 0x00000080U /*!<Bit 7 */
+
+#define FMC_PATT3_ATTWAIT3 0x0000FF00U /*!<ATTWAIT3[7:0] bits (Attribute memory 3 wait time) */
+#define FMC_PATT3_ATTWAIT3_0 0x00000100U /*!<Bit 0 */
+#define FMC_PATT3_ATTWAIT3_1 0x00000200U /*!<Bit 1 */
+#define FMC_PATT3_ATTWAIT3_2 0x00000400U /*!<Bit 2 */
+#define FMC_PATT3_ATTWAIT3_3 0x00000800U /*!<Bit 3 */
+#define FMC_PATT3_ATTWAIT3_4 0x00001000U /*!<Bit 4 */
+#define FMC_PATT3_ATTWAIT3_5 0x00002000U /*!<Bit 5 */
+#define FMC_PATT3_ATTWAIT3_6 0x00004000U /*!<Bit 6 */
+#define FMC_PATT3_ATTWAIT3_7 0x00008000U /*!<Bit 7 */
+
+#define FMC_PATT3_ATTHOLD3 0x00FF0000U /*!<ATTHOLD3[7:0] bits (Attribute memory 3 hold time) */
+#define FMC_PATT3_ATTHOLD3_0 0x00010000U /*!<Bit 0 */
+#define FMC_PATT3_ATTHOLD3_1 0x00020000U /*!<Bit 1 */
+#define FMC_PATT3_ATTHOLD3_2 0x00040000U /*!<Bit 2 */
+#define FMC_PATT3_ATTHOLD3_3 0x00080000U /*!<Bit 3 */
+#define FMC_PATT3_ATTHOLD3_4 0x00100000U /*!<Bit 4 */
+#define FMC_PATT3_ATTHOLD3_5 0x00200000U /*!<Bit 5 */
+#define FMC_PATT3_ATTHOLD3_6 0x00400000U /*!<Bit 6 */
+#define FMC_PATT3_ATTHOLD3_7 0x00800000U /*!<Bit 7 */
+
+#define FMC_PATT3_ATTHIZ3 0xFF000000U /*!<ATTHIZ3[7:0] bits (Attribute memory 3 databus HiZ time) */
+#define FMC_PATT3_ATTHIZ3_0 0x01000000U /*!<Bit 0 */
+#define FMC_PATT3_ATTHIZ3_1 0x02000000U /*!<Bit 1 */
+#define FMC_PATT3_ATTHIZ3_2 0x04000000U /*!<Bit 2 */
+#define FMC_PATT3_ATTHIZ3_3 0x08000000U /*!<Bit 3 */
+#define FMC_PATT3_ATTHIZ3_4 0x10000000U /*!<Bit 4 */
+#define FMC_PATT3_ATTHIZ3_5 0x20000000U /*!<Bit 5 */
+#define FMC_PATT3_ATTHIZ3_6 0x40000000U /*!<Bit 6 */
+#define FMC_PATT3_ATTHIZ3_7 0x80000000U /*!<Bit 7 */
+
+/****************** Bit definition for FMC_PATT4 register ******************/
+#define FMC_PATT4_ATTSET4 0x000000FFU /*!<ATTSET4[7:0] bits (Attribute memory 4 setup time) */
+#define FMC_PATT4_ATTSET4_0 0x00000001U /*!<Bit 0 */
+#define FMC_PATT4_ATTSET4_1 0x00000002U /*!<Bit 1 */
+#define FMC_PATT4_ATTSET4_2 0x00000004U /*!<Bit 2 */
+#define FMC_PATT4_ATTSET4_3 0x00000008U /*!<Bit 3 */
+#define FMC_PATT4_ATTSET4_4 0x00000010U /*!<Bit 4 */
+#define FMC_PATT4_ATTSET4_5 0x00000020U /*!<Bit 5 */
+#define FMC_PATT4_ATTSET4_6 0x00000040U /*!<Bit 6 */
+#define FMC_PATT4_ATTSET4_7 0x00000080U /*!<Bit 7 */
+
+#define FMC_PATT4_ATTWAIT4 0x0000FF00U /*!<ATTWAIT4[7:0] bits (Attribute memory 4 wait time) */
+#define FMC_PATT4_ATTWAIT4_0 0x00000100U /*!<Bit 0 */
+#define FMC_PATT4_ATTWAIT4_1 0x00000200U /*!<Bit 1 */
+#define FMC_PATT4_ATTWAIT4_2 0x00000400U /*!<Bit 2 */
+#define FMC_PATT4_ATTWAIT4_3 0x00000800U /*!<Bit 3 */
+#define FMC_PATT4_ATTWAIT4_4 0x00001000U /*!<Bit 4 */
+#define FMC_PATT4_ATTWAIT4_5 0x00002000U /*!<Bit 5 */
+#define FMC_PATT4_ATTWAIT4_6 0x00004000U /*!<Bit 6 */
+#define FMC_PATT4_ATTWAIT4_7 0x00008000U /*!<Bit 7 */
+
+#define FMC_PATT4_ATTHOLD4 0x00FF0000U /*!<ATTHOLD4[7:0] bits (Attribute memory 4 hold time) */
+#define FMC_PATT4_ATTHOLD4_0 0x00010000U /*!<Bit 0 */
+#define FMC_PATT4_ATTHOLD4_1 0x00020000U /*!<Bit 1 */
+#define FMC_PATT4_ATTHOLD4_2 0x00040000U /*!<Bit 2 */
+#define FMC_PATT4_ATTHOLD4_3 0x00080000U /*!<Bit 3 */
+#define FMC_PATT4_ATTHOLD4_4 0x00100000U /*!<Bit 4 */
+#define FMC_PATT4_ATTHOLD4_5 0x00200000U /*!<Bit 5 */
+#define FMC_PATT4_ATTHOLD4_6 0x00400000U /*!<Bit 6 */
+#define FMC_PATT4_ATTHOLD4_7 0x00800000U /*!<Bit 7 */
+
+#define FMC_PATT4_ATTHIZ4 0xFF000000U /*!<ATTHIZ4[7:0] bits (Attribute memory 4 databus HiZ time) */
+#define FMC_PATT4_ATTHIZ4_0 0x01000000U /*!<Bit 0 */
+#define FMC_PATT4_ATTHIZ4_1 0x02000000U /*!<Bit 1 */
+#define FMC_PATT4_ATTHIZ4_2 0x04000000U /*!<Bit 2 */
+#define FMC_PATT4_ATTHIZ4_3 0x08000000U /*!<Bit 3 */
+#define FMC_PATT4_ATTHIZ4_4 0x10000000U /*!<Bit 4 */
+#define FMC_PATT4_ATTHIZ4_5 0x20000000U /*!<Bit 5 */
+#define FMC_PATT4_ATTHIZ4_6 0x40000000U /*!<Bit 6 */
+#define FMC_PATT4_ATTHIZ4_7 0x80000000U /*!<Bit 7 */
+
+/****************** Bit definition for FMC_PIO4 register *******************/
+#define FMC_PIO4_IOSET4 0x000000FFU /*!<IOSET4[7:0] bits (I/O 4 setup time) */
+#define FMC_PIO4_IOSET4_0 0x00000001U /*!<Bit 0 */
+#define FMC_PIO4_IOSET4_1 0x00000002U /*!<Bit 1 */
+#define FMC_PIO4_IOSET4_2 0x00000004U /*!<Bit 2 */
+#define FMC_PIO4_IOSET4_3 0x00000008U /*!<Bit 3 */
+#define FMC_PIO4_IOSET4_4 0x00000010U /*!<Bit 4 */
+#define FMC_PIO4_IOSET4_5 0x00000020U /*!<Bit 5 */
+#define FMC_PIO4_IOSET4_6 0x00000040U /*!<Bit 6 */
+#define FMC_PIO4_IOSET4_7 0x00000080U /*!<Bit 7 */
+
+#define FMC_PIO4_IOWAIT4 0x0000FF00U /*!<IOWAIT4[7:0] bits (I/O 4 wait time) */
+#define FMC_PIO4_IOWAIT4_0 0x00000100U /*!<Bit 0 */
+#define FMC_PIO4_IOWAIT4_1 0x00000200U /*!<Bit 1 */
+#define FMC_PIO4_IOWAIT4_2 0x00000400U /*!<Bit 2 */
+#define FMC_PIO4_IOWAIT4_3 0x00000800U /*!<Bit 3 */
+#define FMC_PIO4_IOWAIT4_4 0x00001000U /*!<Bit 4 */
+#define FMC_PIO4_IOWAIT4_5 0x00002000U /*!<Bit 5 */
+#define FMC_PIO4_IOWAIT4_6 0x00004000U /*!<Bit 6 */
+#define FMC_PIO4_IOWAIT4_7 0x00008000U /*!<Bit 7 */
+
+#define FMC_PIO4_IOHOLD4 0x00FF0000U /*!<IOHOLD4[7:0] bits (I/O 4 hold time) */
+#define FMC_PIO4_IOHOLD4_0 0x00010000U /*!<Bit 0 */
+#define FMC_PIO4_IOHOLD4_1 0x00020000U /*!<Bit 1 */
+#define FMC_PIO4_IOHOLD4_2 0x00040000U /*!<Bit 2 */
+#define FMC_PIO4_IOHOLD4_3 0x00080000U /*!<Bit 3 */
+#define FMC_PIO4_IOHOLD4_4 0x00100000U /*!<Bit 4 */
+#define FMC_PIO4_IOHOLD4_5 0x00200000U /*!<Bit 5 */
+#define FMC_PIO4_IOHOLD4_6 0x00400000U /*!<Bit 6 */
+#define FMC_PIO4_IOHOLD4_7 0x00800000U /*!<Bit 7 */
+
+#define FMC_PIO4_IOHIZ4 0xFF000000U /*!<IOHIZ4[7:0] bits (I/O 4 databus HiZ time) */
+#define FMC_PIO4_IOHIZ4_0 0x01000000U /*!<Bit 0 */
+#define FMC_PIO4_IOHIZ4_1 0x02000000U /*!<Bit 1 */
+#define FMC_PIO4_IOHIZ4_2 0x04000000U /*!<Bit 2 */
+#define FMC_PIO4_IOHIZ4_3 0x08000000U /*!<Bit 3 */
+#define FMC_PIO4_IOHIZ4_4 0x10000000U /*!<Bit 4 */
+#define FMC_PIO4_IOHIZ4_5 0x20000000U /*!<Bit 5 */
+#define FMC_PIO4_IOHIZ4_6 0x40000000U /*!<Bit 6 */
+#define FMC_PIO4_IOHIZ4_7 0x80000000U /*!<Bit 7 */
+
+/****************** Bit definition for FMC_ECCR2 register ******************/
+#define FMC_ECCR2_ECC2 0xFFFFFFFFU /*!<ECC result */
+
+/****************** Bit definition for FMC_ECCR3 register ******************/
+#define FMC_ECCR3_ECC3 0xFFFFFFFFU /*!<ECC result */
+
+/****************** Bit definition for FMC_SDCR1 register ******************/
+#define FMC_SDCR1_NC 0x00000003U /*!<NC[1:0] bits (Number of column bits) */
+#define FMC_SDCR1_NC_0 0x00000001U /*!<Bit 0 */
+#define FMC_SDCR1_NC_1 0x00000002U /*!<Bit 1 */
+
+#define FMC_SDCR1_NR 0x0000000CU /*!<NR[1:0] bits (Number of row bits) */
+#define FMC_SDCR1_NR_0 0x00000004U /*!<Bit 0 */
+#define FMC_SDCR1_NR_1 0x00000008U /*!<Bit 1 */
+
+#define FMC_SDCR1_MWID 0x00000030U /*!<NR[1:0] bits (Number of row bits) */
+#define FMC_SDCR1_MWID_0 0x00000010U /*!<Bit 0 */
+#define FMC_SDCR1_MWID_1 0x00000020U /*!<Bit 1 */
+
+#define FMC_SDCR1_NB 0x00000040U /*!<Number of internal bank */
+
+#define FMC_SDCR1_CAS 0x00000180U /*!<CAS[1:0] bits (CAS latency) */
+#define FMC_SDCR1_CAS_0 0x00000080U /*!<Bit 0 */
+#define FMC_SDCR1_CAS_1 0x00000100U /*!<Bit 1 */
+
+#define FMC_SDCR1_WP 0x00000200U /*!<Write protection */
+
+#define FMC_SDCR1_SDCLK 0x00000C00U /*!<SDRAM clock configuration */
+#define FMC_SDCR1_SDCLK_0 0x00000400U /*!<Bit 0 */
+#define FMC_SDCR1_SDCLK_1 0x00000800U /*!<Bit 1 */
+
+#define FMC_SDCR1_RBURST 0x00001000U /*!<Read burst */
+
+#define FMC_SDCR1_RPIPE 0x00006000U /*!<Write protection */
+#define FMC_SDCR1_RPIPE_0 0x00002000U /*!<Bit 0 */
+#define FMC_SDCR1_RPIPE_1 0x00004000U /*!<Bit 1 */
+
+/****************** Bit definition for FMC_SDCR2 register ******************/
+#define FMC_SDCR2_NC 0x00000003U /*!<NC[1:0] bits (Number of column bits) */
+#define FMC_SDCR2_NC_0 0x00000001U /*!<Bit 0 */
+#define FMC_SDCR2_NC_1 0x00000002U /*!<Bit 1 */
+
+#define FMC_SDCR2_NR 0x0000000CU /*!<NR[1:0] bits (Number of row bits) */
+#define FMC_SDCR2_NR_0 0x00000004U /*!<Bit 0 */
+#define FMC_SDCR2_NR_1 0x00000008U /*!<Bit 1 */
+
+#define FMC_SDCR2_MWID 0x00000030U /*!<NR[1:0] bits (Number of row bits) */
+#define FMC_SDCR2_MWID_0 0x00000010U /*!<Bit 0 */
+#define FMC_SDCR2_MWID_1 0x00000020U /*!<Bit 1 */
+
+#define FMC_SDCR2_NB 0x00000040U /*!<Number of internal bank */
+
+#define FMC_SDCR2_CAS 0x00000180U /*!<CAS[1:0] bits (CAS latency) */
+#define FMC_SDCR2_CAS_0 0x00000080U /*!<Bit 0 */
+#define FMC_SDCR2_CAS_1 0x00000100U /*!<Bit 1 */
+
+#define FMC_SDCR2_WP 0x00000200U /*!<Write protection */
+
+#define FMC_SDCR2_SDCLK 0x00000C00U /*!<SDCLK[1:0] (SDRAM clock configuration) */
+#define FMC_SDCR2_SDCLK_0 0x00000400U /*!<Bit 0 */
+#define FMC_SDCR2_SDCLK_1 0x00000800U /*!<Bit 1 */
+
+#define FMC_SDCR2_RBURST 0x00001000U /*!<Read burst */
+
+#define FMC_SDCR2_RPIPE 0x00006000U /*!<RPIPE[1:0](Read pipe) */
+#define FMC_SDCR2_RPIPE_0 0x00002000U /*!<Bit 0 */
+#define FMC_SDCR2_RPIPE_1 0x00004000U /*!<Bit 1 */
+
+/****************** Bit definition for FMC_SDTR1 register ******************/
+#define FMC_SDTR1_TMRD 0x0000000FU /*!<TMRD[3:0] bits (Load mode register to active) */
+#define FMC_SDTR1_TMRD_0 0x00000001U /*!<Bit 0 */
+#define FMC_SDTR1_TMRD_1 0x00000002U /*!<Bit 1 */
+#define FMC_SDTR1_TMRD_2 0x00000004U /*!<Bit 2 */
+#define FMC_SDTR1_TMRD_3 0x00000008U /*!<Bit 3 */
+
+#define FMC_SDTR1_TXSR 0x000000F0U /*!<TXSR[3:0] bits (Exit self refresh) */
+#define FMC_SDTR1_TXSR_0 0x00000010U /*!<Bit 0 */
+#define FMC_SDTR1_TXSR_1 0x00000020U /*!<Bit 1 */
+#define FMC_SDTR1_TXSR_2 0x00000040U /*!<Bit 2 */
+#define FMC_SDTR1_TXSR_3 0x00000080U /*!<Bit 3 */
+
+#define FMC_SDTR1_TRAS 0x00000F00U /*!<TRAS[3:0] bits (Self refresh time) */
+#define FMC_SDTR1_TRAS_0 0x00000100U /*!<Bit 0 */
+#define FMC_SDTR1_TRAS_1 0x00000200U /*!<Bit 1 */
+#define FMC_SDTR1_TRAS_2 0x00000400U /*!<Bit 2 */
+#define FMC_SDTR1_TRAS_3 0x00000800U /*!<Bit 3 */
+
+#define FMC_SDTR1_TRC 0x0000F000U /*!<TRC[2:0] bits (Row cycle delay) */
+#define FMC_SDTR1_TRC_0 0x00001000U /*!<Bit 0 */
+#define FMC_SDTR1_TRC_1 0x00002000U /*!<Bit 1 */
+#define FMC_SDTR1_TRC_2 0x00004000U /*!<Bit 2 */
+
+#define FMC_SDTR1_TWR 0x000F0000U /*!<TRC[2:0] bits (Write recovery delay) */
+#define FMC_SDTR1_TWR_0 0x00010000U /*!<Bit 0 */
+#define FMC_SDTR1_TWR_1 0x00020000U /*!<Bit 1 */
+#define FMC_SDTR1_TWR_2 0x00040000U /*!<Bit 2 */
+
+#define FMC_SDTR1_TRP 0x00F00000U /*!<TRP[2:0] bits (Row precharge delay) */
+#define FMC_SDTR1_TRP_0 0x00100000U /*!<Bit 0 */
+#define FMC_SDTR1_TRP_1 0x00200000U /*!<Bit 1 */
+#define FMC_SDTR1_TRP_2 0x00400000U /*!<Bit 2 */
+
+#define FMC_SDTR1_TRCD 0x0F000000U /*!<TRP[2:0] bits (Row to column delay) */
+#define FMC_SDTR1_TRCD_0 0x01000000U /*!<Bit 0 */
+#define FMC_SDTR1_TRCD_1 0x02000000U /*!<Bit 1 */
+#define FMC_SDTR1_TRCD_2 0x04000000U /*!<Bit 2 */
+
+/****************** Bit definition for FMC_SDTR2 register ******************/
+#define FMC_SDTR2_TMRD 0x0000000FU /*!<TMRD[3:0] bits (Load mode register to active) */
+#define FMC_SDTR2_TMRD_0 0x00000001U /*!<Bit 0 */
+#define FMC_SDTR2_TMRD_1 0x00000002U /*!<Bit 1 */
+#define FMC_SDTR2_TMRD_2 0x00000004U /*!<Bit 2 */
+#define FMC_SDTR2_TMRD_3 0x00000008U /*!<Bit 3 */
+
+#define FMC_SDTR2_TXSR 0x000000F0U /*!<TXSR[3:0] bits (Exit self refresh) */
+#define FMC_SDTR2_TXSR_0 0x00000010U /*!<Bit 0 */
+#define FMC_SDTR2_TXSR_1 0x00000020U /*!<Bit 1 */
+#define FMC_SDTR2_TXSR_2 0x00000040U /*!<Bit 2 */
+#define FMC_SDTR2_TXSR_3 0x00000080U /*!<Bit 3 */
+
+#define FMC_SDTR2_TRAS 0x00000F00U /*!<TRAS[3:0] bits (Self refresh time) */
+#define FMC_SDTR2_TRAS_0 0x00000100U /*!<Bit 0 */
+#define FMC_SDTR2_TRAS_1 0x00000200U /*!<Bit 1 */
+#define FMC_SDTR2_TRAS_2 0x00000400U /*!<Bit 2 */
+#define FMC_SDTR2_TRAS_3 0x00000800U /*!<Bit 3 */
+
+#define FMC_SDTR2_TRC 0x0000F000U /*!<TRC[2:0] bits (Row cycle delay) */
+#define FMC_SDTR2_TRC_0 0x00001000U /*!<Bit 0 */
+#define FMC_SDTR2_TRC_1 0x00002000U /*!<Bit 1 */
+#define FMC_SDTR2_TRC_2 0x00004000U /*!<Bit 2 */
+
+#define FMC_SDTR2_TWR 0x000F0000U /*!<TRC[2:0] bits (Write recovery delay) */
+#define FMC_SDTR2_TWR_0 0x00010000U /*!<Bit 0 */
+#define FMC_SDTR2_TWR_1 0x00020000U /*!<Bit 1 */
+#define FMC_SDTR2_TWR_2 0x00040000U /*!<Bit 2 */
+
+#define FMC_SDTR2_TRP 0x00F00000U /*!<TRP[2:0] bits (Row precharge delay) */
+#define FMC_SDTR2_TRP_0 0x00100000U /*!<Bit 0 */
+#define FMC_SDTR2_TRP_1 0x00200000U /*!<Bit 1 */
+#define FMC_SDTR2_TRP_2 0x00400000U /*!<Bit 2 */
+
+#define FMC_SDTR2_TRCD 0x0F000000U /*!<TRP[2:0] bits (Row to column delay) */
+#define FMC_SDTR2_TRCD_0 0x01000000U /*!<Bit 0 */
+#define FMC_SDTR2_TRCD_1 0x02000000U /*!<Bit 1 */
+#define FMC_SDTR2_TRCD_2 0x04000000U /*!<Bit 2 */
+
+/****************** Bit definition for FMC_SDCMR register ******************/
+#define FMC_SDCMR_MODE 0x00000007U /*!<MODE[2:0] bits (Command mode) */
+#define FMC_SDCMR_MODE_0 0x00000001U /*!<Bit 0 */
+#define FMC_SDCMR_MODE_1 0x00000002U /*!<Bit 1 */
+#define FMC_SDCMR_MODE_2 0x00000004U /*!<Bit 2 */
+
+#define FMC_SDCMR_CTB2 0x00000008U /*!<Command target 2 */
+
+#define FMC_SDCMR_CTB1 0x00000010U /*!<Command target 1 */
+
+#define FMC_SDCMR_NRFS 0x000001E0U /*!<NRFS[3:0] bits (Number of auto-refresh) */
+#define FMC_SDCMR_NRFS_0 0x00000020U /*!<Bit 0 */
+#define FMC_SDCMR_NRFS_1 0x00000040U /*!<Bit 1 */
+#define FMC_SDCMR_NRFS_2 0x00000080U /*!<Bit 2 */
+#define FMC_SDCMR_NRFS_3 0x00000100U /*!<Bit 3 */
+
+#define FMC_SDCMR_MRD 0x003FFE00U /*!<MRD[12:0] bits (Mode register definition) */
+
+/****************** Bit definition for FMC_SDRTR register ******************/
+#define FMC_SDRTR_CRE 0x00000001U /*!<Clear refresh error flag */
+
+#define FMC_SDRTR_COUNT 0x00003FFEU /*!<COUNT[12:0] bits (Refresh timer count) */
+
+#define FMC_SDRTR_REIE 0x00004000U /*!<RES interupt enable */
+
+/****************** Bit definition for FMC_SDSR register ******************/
+#define FMC_SDSR_RE 0x00000001U /*!<Refresh error flag */
+
+#define FMC_SDSR_MODES1 0x00000006U /*!<MODES1[1:0]bits (Status mode for bank 1) */
+#define FMC_SDSR_MODES1_0 0x00000002U /*!<Bit 0 */
+#define FMC_SDSR_MODES1_1 0x00000004U /*!<Bit 1 */
+
+#define FMC_SDSR_MODES2 0x00000018U /*!<MODES2[1:0]bits (Status mode for bank 2) */
+#define FMC_SDSR_MODES2_0 0x00000008U /*!<Bit 0 */
+#define FMC_SDSR_MODES2_1 0x00000010U /*!<Bit 1 */
+#define FMC_SDSR_BUSY 0x00000020U /*!<Busy status */
+
+
+
+/******************************************************************************/
+/* */
+/* General Purpose I/O */
+/* */
+/******************************************************************************/
+/****************** Bits definition for GPIO_MODER register *****************/
+#define GPIO_MODER_MODER0 0x00000003U
+#define GPIO_MODER_MODER0_0 0x00000001U
+#define GPIO_MODER_MODER0_1 0x00000002U
+
+#define GPIO_MODER_MODER1 0x0000000CU
+#define GPIO_MODER_MODER1_0 0x00000004U
+#define GPIO_MODER_MODER1_1 0x00000008U
+
+#define GPIO_MODER_MODER2 0x00000030U
+#define GPIO_MODER_MODER2_0 0x00000010U
+#define GPIO_MODER_MODER2_1 0x00000020U
+
+#define GPIO_MODER_MODER3 0x000000C0U
+#define GPIO_MODER_MODER3_0 0x00000040U
+#define GPIO_MODER_MODER3_1 0x00000080U
+
+#define GPIO_MODER_MODER4 0x00000300U
+#define GPIO_MODER_MODER4_0 0x00000100U
+#define GPIO_MODER_MODER4_1 0x00000200U
+
+#define GPIO_MODER_MODER5 0x00000C00U
+#define GPIO_MODER_MODER5_0 0x00000400U
+#define GPIO_MODER_MODER5_1 0x00000800U
+
+#define GPIO_MODER_MODER6 0x00003000U
+#define GPIO_MODER_MODER6_0 0x00001000U
+#define GPIO_MODER_MODER6_1 0x00002000U
+
+#define GPIO_MODER_MODER7 0x0000C000U
+#define GPIO_MODER_MODER7_0 0x00004000U
+#define GPIO_MODER_MODER7_1 0x00008000U
+
+#define GPIO_MODER_MODER8 0x00030000U
+#define GPIO_MODER_MODER8_0 0x00010000U
+#define GPIO_MODER_MODER8_1 0x00020000U
+
+#define GPIO_MODER_MODER9 0x000C0000U
+#define GPIO_MODER_MODER9_0 0x00040000U
+#define GPIO_MODER_MODER9_1 0x00080000U
+
+#define GPIO_MODER_MODER10 0x00300000U
+#define GPIO_MODER_MODER10_0 0x00100000U
+#define GPIO_MODER_MODER10_1 0x00200000U
+
+#define GPIO_MODER_MODER11 0x00C00000U
+#define GPIO_MODER_MODER11_0 0x00400000U
+#define GPIO_MODER_MODER11_1 0x00800000U
+
+#define GPIO_MODER_MODER12 0x03000000U
+#define GPIO_MODER_MODER12_0 0x01000000U
+#define GPIO_MODER_MODER12_1 0x02000000U
+
+#define GPIO_MODER_MODER13 0x0C000000U
+#define GPIO_MODER_MODER13_0 0x04000000U
+#define GPIO_MODER_MODER13_1 0x08000000U
+
+#define GPIO_MODER_MODER14 0x30000000U
+#define GPIO_MODER_MODER14_0 0x10000000U
+#define GPIO_MODER_MODER14_1 0x20000000U
+
+#define GPIO_MODER_MODER15 0xC0000000U
+#define GPIO_MODER_MODER15_0 0x40000000U
+#define GPIO_MODER_MODER15_1 0x80000000U
+
+/****************** Bits definition for GPIO_OTYPER register ****************/
+#define GPIO_OTYPER_OT_0 0x00000001U
+#define GPIO_OTYPER_OT_1 0x00000002U
+#define GPIO_OTYPER_OT_2 0x00000004U
+#define GPIO_OTYPER_OT_3 0x00000008U
+#define GPIO_OTYPER_OT_4 0x00000010U
+#define GPIO_OTYPER_OT_5 0x00000020U
+#define GPIO_OTYPER_OT_6 0x00000040U
+#define GPIO_OTYPER_OT_7 0x00000080U
+#define GPIO_OTYPER_OT_8 0x00000100U
+#define GPIO_OTYPER_OT_9 0x00000200U
+#define GPIO_OTYPER_OT_10 0x00000400U
+#define GPIO_OTYPER_OT_11 0x00000800U
+#define GPIO_OTYPER_OT_12 0x00001000U
+#define GPIO_OTYPER_OT_13 0x00002000U
+#define GPIO_OTYPER_OT_14 0x00004000U
+#define GPIO_OTYPER_OT_15 0x00008000U
+
+/****************** Bits definition for GPIO_OSPEEDR register ***************/
+#define GPIO_OSPEEDER_OSPEEDR0 0x00000003U
+#define GPIO_OSPEEDER_OSPEEDR0_0 0x00000001U
+#define GPIO_OSPEEDER_OSPEEDR0_1 0x00000002U
+
+#define GPIO_OSPEEDER_OSPEEDR1 0x0000000CU
+#define GPIO_OSPEEDER_OSPEEDR1_0 0x00000004U
+#define GPIO_OSPEEDER_OSPEEDR1_1 0x00000008U
+
+#define GPIO_OSPEEDER_OSPEEDR2 0x00000030U
+#define GPIO_OSPEEDER_OSPEEDR2_0 0x00000010U
+#define GPIO_OSPEEDER_OSPEEDR2_1 0x00000020U
+
+#define GPIO_OSPEEDER_OSPEEDR3 0x000000C0U
+#define GPIO_OSPEEDER_OSPEEDR3_0 0x00000040U
+#define GPIO_OSPEEDER_OSPEEDR3_1 0x00000080U
+
+#define GPIO_OSPEEDER_OSPEEDR4 0x00000300U
+#define GPIO_OSPEEDER_OSPEEDR4_0 0x00000100U
+#define GPIO_OSPEEDER_OSPEEDR4_1 0x00000200U
+
+#define GPIO_OSPEEDER_OSPEEDR5 0x00000C00U
+#define GPIO_OSPEEDER_OSPEEDR5_0 0x00000400U
+#define GPIO_OSPEEDER_OSPEEDR5_1 0x00000800U
+
+#define GPIO_OSPEEDER_OSPEEDR6 0x00003000U
+#define GPIO_OSPEEDER_OSPEEDR6_0 0x00001000U
+#define GPIO_OSPEEDER_OSPEEDR6_1 0x00002000U
+
+#define GPIO_OSPEEDER_OSPEEDR7 0x0000C000U
+#define GPIO_OSPEEDER_OSPEEDR7_0 0x00004000U
+#define GPIO_OSPEEDER_OSPEEDR7_1 0x00008000U
+
+#define GPIO_OSPEEDER_OSPEEDR8 0x00030000U
+#define GPIO_OSPEEDER_OSPEEDR8_0 0x00010000U
+#define GPIO_OSPEEDER_OSPEEDR8_1 0x00020000U
+
+#define GPIO_OSPEEDER_OSPEEDR9 0x000C0000U
+#define GPIO_OSPEEDER_OSPEEDR9_0 0x00040000U
+#define GPIO_OSPEEDER_OSPEEDR9_1 0x00080000U
+
+#define GPIO_OSPEEDER_OSPEEDR10 0x00300000U
+#define GPIO_OSPEEDER_OSPEEDR10_0 0x00100000U
+#define GPIO_OSPEEDER_OSPEEDR10_1 0x00200000U
+
+#define GPIO_OSPEEDER_OSPEEDR11 0x00C00000U
+#define GPIO_OSPEEDER_OSPEEDR11_0 0x00400000U
+#define GPIO_OSPEEDER_OSPEEDR11_1 0x00800000U
+
+#define GPIO_OSPEEDER_OSPEEDR12 0x03000000U
+#define GPIO_OSPEEDER_OSPEEDR12_0 0x01000000U
+#define GPIO_OSPEEDER_OSPEEDR12_1 0x02000000U
+
+#define GPIO_OSPEEDER_OSPEEDR13 0x0C000000U
+#define GPIO_OSPEEDER_OSPEEDR13_0 0x04000000U
+#define GPIO_OSPEEDER_OSPEEDR13_1 0x08000000U
+
+#define GPIO_OSPEEDER_OSPEEDR14 0x30000000U
+#define GPIO_OSPEEDER_OSPEEDR14_0 0x10000000U
+#define GPIO_OSPEEDER_OSPEEDR14_1 0x20000000U
+
+#define GPIO_OSPEEDER_OSPEEDR15 0xC0000000U
+#define GPIO_OSPEEDER_OSPEEDR15_0 0x40000000U
+#define GPIO_OSPEEDER_OSPEEDR15_1 0x80000000U
+
+/****************** Bits definition for GPIO_PUPDR register *****************/
+#define GPIO_PUPDR_PUPDR0 0x00000003U
+#define GPIO_PUPDR_PUPDR0_0 0x00000001U
+#define GPIO_PUPDR_PUPDR0_1 0x00000002U
+
+#define GPIO_PUPDR_PUPDR1 0x0000000CU
+#define GPIO_PUPDR_PUPDR1_0 0x00000004U
+#define GPIO_PUPDR_PUPDR1_1 0x00000008U
+
+#define GPIO_PUPDR_PUPDR2 0x00000030U
+#define GPIO_PUPDR_PUPDR2_0 0x00000010U
+#define GPIO_PUPDR_PUPDR2_1 0x00000020U
+
+#define GPIO_PUPDR_PUPDR3 0x000000C0U
+#define GPIO_PUPDR_PUPDR3_0 0x00000040U
+#define GPIO_PUPDR_PUPDR3_1 0x00000080U
+
+#define GPIO_PUPDR_PUPDR4 0x00000300U
+#define GPIO_PUPDR_PUPDR4_0 0x00000100U
+#define GPIO_PUPDR_PUPDR4_1 0x00000200U
+
+#define GPIO_PUPDR_PUPDR5 0x00000C00U
+#define GPIO_PUPDR_PUPDR5_0 0x00000400U
+#define GPIO_PUPDR_PUPDR5_1 0x00000800U
+
+#define GPIO_PUPDR_PUPDR6 0x00003000U
+#define GPIO_PUPDR_PUPDR6_0 0x00001000U
+#define GPIO_PUPDR_PUPDR6_1 0x00002000U
+
+#define GPIO_PUPDR_PUPDR7 0x0000C000U
+#define GPIO_PUPDR_PUPDR7_0 0x00004000U
+#define GPIO_PUPDR_PUPDR7_1 0x00008000U
+
+#define GPIO_PUPDR_PUPDR8 0x00030000U
+#define GPIO_PUPDR_PUPDR8_0 0x00010000U
+#define GPIO_PUPDR_PUPDR8_1 0x00020000U
+
+#define GPIO_PUPDR_PUPDR9 0x000C0000U
+#define GPIO_PUPDR_PUPDR9_0 0x00040000U
+#define GPIO_PUPDR_PUPDR9_1 0x00080000U
+
+#define GPIO_PUPDR_PUPDR10 0x00300000U
+#define GPIO_PUPDR_PUPDR10_0 0x00100000U
+#define GPIO_PUPDR_PUPDR10_1 0x00200000U
+
+#define GPIO_PUPDR_PUPDR11 0x00C00000U
+#define GPIO_PUPDR_PUPDR11_0 0x00400000U
+#define GPIO_PUPDR_PUPDR11_1 0x00800000U
+
+#define GPIO_PUPDR_PUPDR12 0x03000000U
+#define GPIO_PUPDR_PUPDR12_0 0x01000000U
+#define GPIO_PUPDR_PUPDR12_1 0x02000000U
+
+#define GPIO_PUPDR_PUPDR13 0x0C000000U
+#define GPIO_PUPDR_PUPDR13_0 0x04000000U
+#define GPIO_PUPDR_PUPDR13_1 0x08000000U
+
+#define GPIO_PUPDR_PUPDR14 0x30000000U
+#define GPIO_PUPDR_PUPDR14_0 0x10000000U
+#define GPIO_PUPDR_PUPDR14_1 0x20000000U
+
+#define GPIO_PUPDR_PUPDR15 0xC0000000U
+#define GPIO_PUPDR_PUPDR15_0 0x40000000U
+#define GPIO_PUPDR_PUPDR15_1 0x80000000U
+
+/****************** Bits definition for GPIO_IDR register *******************/
+#define GPIO_IDR_IDR_0 0x00000001U
+#define GPIO_IDR_IDR_1 0x00000002U
+#define GPIO_IDR_IDR_2 0x00000004U
+#define GPIO_IDR_IDR_3 0x00000008U
+#define GPIO_IDR_IDR_4 0x00000010U
+#define GPIO_IDR_IDR_5 0x00000020U
+#define GPIO_IDR_IDR_6 0x00000040U
+#define GPIO_IDR_IDR_7 0x00000080U
+#define GPIO_IDR_IDR_8 0x00000100U
+#define GPIO_IDR_IDR_9 0x00000200U
+#define GPIO_IDR_IDR_10 0x00000400U
+#define GPIO_IDR_IDR_11 0x00000800U
+#define GPIO_IDR_IDR_12 0x00001000U
+#define GPIO_IDR_IDR_13 0x00002000U
+#define GPIO_IDR_IDR_14 0x00004000U
+#define GPIO_IDR_IDR_15 0x00008000U
+/* Old GPIO_IDR register bits definition, maintained for legacy purpose */
+#define GPIO_OTYPER_IDR_0 GPIO_IDR_IDR_0
+#define GPIO_OTYPER_IDR_1 GPIO_IDR_IDR_1
+#define GPIO_OTYPER_IDR_2 GPIO_IDR_IDR_2
+#define GPIO_OTYPER_IDR_3 GPIO_IDR_IDR_3
+#define GPIO_OTYPER_IDR_4 GPIO_IDR_IDR_4
+#define GPIO_OTYPER_IDR_5 GPIO_IDR_IDR_5
+#define GPIO_OTYPER_IDR_6 GPIO_IDR_IDR_6
+#define GPIO_OTYPER_IDR_7 GPIO_IDR_IDR_7
+#define GPIO_OTYPER_IDR_8 GPIO_IDR_IDR_8
+#define GPIO_OTYPER_IDR_9 GPIO_IDR_IDR_9
+#define GPIO_OTYPER_IDR_10 GPIO_IDR_IDR_10
+#define GPIO_OTYPER_IDR_11 GPIO_IDR_IDR_11
+#define GPIO_OTYPER_IDR_12 GPIO_IDR_IDR_12
+#define GPIO_OTYPER_IDR_13 GPIO_IDR_IDR_13
+#define GPIO_OTYPER_IDR_14 GPIO_IDR_IDR_14
+#define GPIO_OTYPER_IDR_15 GPIO_IDR_IDR_15
+
+/****************** Bits definition for GPIO_ODR register *******************/
+#define GPIO_ODR_ODR_0 0x00000001U
+#define GPIO_ODR_ODR_1 0x00000002U
+#define GPIO_ODR_ODR_2 0x00000004U
+#define GPIO_ODR_ODR_3 0x00000008U
+#define GPIO_ODR_ODR_4 0x00000010U
+#define GPIO_ODR_ODR_5 0x00000020U
+#define GPIO_ODR_ODR_6 0x00000040U
+#define GPIO_ODR_ODR_7 0x00000080U
+#define GPIO_ODR_ODR_8 0x00000100U
+#define GPIO_ODR_ODR_9 0x00000200U
+#define GPIO_ODR_ODR_10 0x00000400U
+#define GPIO_ODR_ODR_11 0x00000800U
+#define GPIO_ODR_ODR_12 0x00001000U
+#define GPIO_ODR_ODR_13 0x00002000U
+#define GPIO_ODR_ODR_14 0x00004000U
+#define GPIO_ODR_ODR_15 0x00008000U
+/* Old GPIO_ODR register bits definition, maintained for legacy purpose */
+#define GPIO_OTYPER_ODR_0 GPIO_ODR_ODR_0
+#define GPIO_OTYPER_ODR_1 GPIO_ODR_ODR_1
+#define GPIO_OTYPER_ODR_2 GPIO_ODR_ODR_2
+#define GPIO_OTYPER_ODR_3 GPIO_ODR_ODR_3
+#define GPIO_OTYPER_ODR_4 GPIO_ODR_ODR_4
+#define GPIO_OTYPER_ODR_5 GPIO_ODR_ODR_5
+#define GPIO_OTYPER_ODR_6 GPIO_ODR_ODR_6
+#define GPIO_OTYPER_ODR_7 GPIO_ODR_ODR_7
+#define GPIO_OTYPER_ODR_8 GPIO_ODR_ODR_8
+#define GPIO_OTYPER_ODR_9 GPIO_ODR_ODR_9
+#define GPIO_OTYPER_ODR_10 GPIO_ODR_ODR_10
+#define GPIO_OTYPER_ODR_11 GPIO_ODR_ODR_11
+#define GPIO_OTYPER_ODR_12 GPIO_ODR_ODR_12
+#define GPIO_OTYPER_ODR_13 GPIO_ODR_ODR_13
+#define GPIO_OTYPER_ODR_14 GPIO_ODR_ODR_14
+#define GPIO_OTYPER_ODR_15 GPIO_ODR_ODR_15
+
+/****************** Bits definition for GPIO_BSRR register ******************/
+#define GPIO_BSRR_BS_0 0x00000001U
+#define GPIO_BSRR_BS_1 0x00000002U
+#define GPIO_BSRR_BS_2 0x00000004U
+#define GPIO_BSRR_BS_3 0x00000008U
+#define GPIO_BSRR_BS_4 0x00000010U
+#define GPIO_BSRR_BS_5 0x00000020U
+#define GPIO_BSRR_BS_6 0x00000040U
+#define GPIO_BSRR_BS_7 0x00000080U
+#define GPIO_BSRR_BS_8 0x00000100U
+#define GPIO_BSRR_BS_9 0x00000200U
+#define GPIO_BSRR_BS_10 0x00000400U
+#define GPIO_BSRR_BS_11 0x00000800U
+#define GPIO_BSRR_BS_12 0x00001000U
+#define GPIO_BSRR_BS_13 0x00002000U
+#define GPIO_BSRR_BS_14 0x00004000U
+#define GPIO_BSRR_BS_15 0x00008000U
+#define GPIO_BSRR_BR_0 0x00010000U
+#define GPIO_BSRR_BR_1 0x00020000U
+#define GPIO_BSRR_BR_2 0x00040000U
+#define GPIO_BSRR_BR_3 0x00080000U
+#define GPIO_BSRR_BR_4 0x00100000U
+#define GPIO_BSRR_BR_5 0x00200000U
+#define GPIO_BSRR_BR_6 0x00400000U
+#define GPIO_BSRR_BR_7 0x00800000U
+#define GPIO_BSRR_BR_8 0x01000000U
+#define GPIO_BSRR_BR_9 0x02000000U
+#define GPIO_BSRR_BR_10 0x04000000U
+#define GPIO_BSRR_BR_11 0x08000000U
+#define GPIO_BSRR_BR_12 0x10000000U
+#define GPIO_BSRR_BR_13 0x20000000U
+#define GPIO_BSRR_BR_14 0x40000000U
+#define GPIO_BSRR_BR_15 0x80000000U
+
+/****************** Bit definition for GPIO_LCKR register *********************/
+#define GPIO_LCKR_LCK0 0x00000001U
+#define GPIO_LCKR_LCK1 0x00000002U
+#define GPIO_LCKR_LCK2 0x00000004U
+#define GPIO_LCKR_LCK3 0x00000008U
+#define GPIO_LCKR_LCK4 0x00000010U
+#define GPIO_LCKR_LCK5 0x00000020U
+#define GPIO_LCKR_LCK6 0x00000040U
+#define GPIO_LCKR_LCK7 0x00000080U
+#define GPIO_LCKR_LCK8 0x00000100U
+#define GPIO_LCKR_LCK9 0x00000200U
+#define GPIO_LCKR_LCK10 0x00000400U
+#define GPIO_LCKR_LCK11 0x00000800U
+#define GPIO_LCKR_LCK12 0x00001000U
+#define GPIO_LCKR_LCK13 0x00002000U
+#define GPIO_LCKR_LCK14 0x00004000U
+#define GPIO_LCKR_LCK15 0x00008000U
+#define GPIO_LCKR_LCKK 0x00010000U
+
+/******************************************************************************/
+/* */
+/* HASH */
+/* */
+/******************************************************************************/
+/****************** Bits definition for HASH_CR register ********************/
+#define HASH_CR_INIT 0x00000004U
+#define HASH_CR_DMAE 0x00000008U
+#define HASH_CR_DATATYPE 0x00000030U
+#define HASH_CR_DATATYPE_0 0x00000010U
+#define HASH_CR_DATATYPE_1 0x00000020U
+#define HASH_CR_MODE 0x00000040U
+#define HASH_CR_ALGO 0x00040080U
+#define HASH_CR_ALGO_0 0x00000080U
+#define HASH_CR_ALGO_1 0x00040000U
+#define HASH_CR_NBW 0x00000F00U
+#define HASH_CR_NBW_0 0x00000100U
+#define HASH_CR_NBW_1 0x00000200U
+#define HASH_CR_NBW_2 0x00000400U
+#define HASH_CR_NBW_3 0x00000800U
+#define HASH_CR_DINNE 0x00001000U
+#define HASH_CR_MDMAT 0x00002000U
+#define HASH_CR_LKEY 0x00010000U
+
+/****************** Bits definition for HASH_STR register *******************/
+#define HASH_STR_NBLW 0x0000001FU
+#define HASH_STR_NBLW_0 0x00000001U
+#define HASH_STR_NBLW_1 0x00000002U
+#define HASH_STR_NBLW_2 0x00000004U
+#define HASH_STR_NBLW_3 0x00000008U
+#define HASH_STR_NBLW_4 0x00000010U
+#define HASH_STR_DCAL 0x00000100U
+/* Aliases for HASH_STR register */
+#define HASH_STR_NBW HASH_STR_NBLW
+#define HASH_STR_NBW_0 HASH_STR_NBLW_0
+#define HASH_STR_NBW_1 HASH_STR_NBLW_1
+#define HASH_STR_NBW_2 HASH_STR_NBLW_2
+#define HASH_STR_NBW_3 HASH_STR_NBLW_3
+#define HASH_STR_NBW_4 HASH_STR_NBLW_4
+
+/****************** Bits definition for HASH_IMR register *******************/
+#define HASH_IMR_DINIE 0x00000001U
+#define HASH_IMR_DCIE 0x00000002U
+/* Aliases for HASH_IMR register */
+#define HASH_IMR_DINIM HASH_IMR_DINIE
+#define HASH_IMR_DCIM HASH_IMR_DCIE
+
+/****************** Bits definition for HASH_SR register ********************/
+#define HASH_SR_DINIS 0x00000001U
+#define HASH_SR_DCIS 0x00000002U
+#define HASH_SR_DMAS 0x00000004U
+#define HASH_SR_BUSY 0x00000008U
+
+/******************************************************************************/
+/* */
+/* Inter-integrated Circuit Interface */
+/* */
+/******************************************************************************/
+/******************* Bit definition for I2C_CR1 register ********************/
+#define I2C_CR1_PE 0x00000001U /*!<Peripheral Enable */
+#define I2C_CR1_SMBUS 0x00000002U /*!<SMBus Mode */
+#define I2C_CR1_SMBTYPE 0x00000008U /*!<SMBus Type */
+#define I2C_CR1_ENARP 0x00000010U /*!<ARP Enable */
+#define I2C_CR1_ENPEC 0x00000020U /*!<PEC Enable */
+#define I2C_CR1_ENGC 0x00000040U /*!<General Call Enable */
+#define I2C_CR1_NOSTRETCH 0x00000080U /*!<Clock Stretching Disable (Slave mode) */
+#define I2C_CR1_START 0x00000100U /*!<Start Generation */
+#define I2C_CR1_STOP 0x00000200U /*!<Stop Generation */
+#define I2C_CR1_ACK 0x00000400U /*!<Acknowledge Enable */
+#define I2C_CR1_POS 0x00000800U /*!<Acknowledge/PEC Position (for data reception) */
+#define I2C_CR1_PEC 0x00001000U /*!<Packet Error Checking */
+#define I2C_CR1_ALERT 0x00002000U /*!<SMBus Alert */
+#define I2C_CR1_SWRST 0x00008000U /*!<Software Reset */
+
+/******************* Bit definition for I2C_CR2 register ********************/
+#define I2C_CR2_FREQ 0x0000003FU /*!<FREQ[5:0] bits (Peripheral Clock Frequency) */
+#define I2C_CR2_FREQ_0 0x00000001U /*!<Bit 0 */
+#define I2C_CR2_FREQ_1 0x00000002U /*!<Bit 1 */
+#define I2C_CR2_FREQ_2 0x00000004U /*!<Bit 2 */
+#define I2C_CR2_FREQ_3 0x00000008U /*!<Bit 3 */
+#define I2C_CR2_FREQ_4 0x00000010U /*!<Bit 4 */
+#define I2C_CR2_FREQ_5 0x00000020U /*!<Bit 5 */
+
+#define I2C_CR2_ITERREN 0x00000100U /*!<Error Interrupt Enable */
+#define I2C_CR2_ITEVTEN 0x00000200U /*!<Event Interrupt Enable */
+#define I2C_CR2_ITBUFEN 0x00000400U /*!<Buffer Interrupt Enable */
+#define I2C_CR2_DMAEN 0x00000800U /*!<DMA Requests Enable */
+#define I2C_CR2_LAST 0x00001000U /*!<DMA Last Transfer */
+
+/******************* Bit definition for I2C_OAR1 register *******************/
+#define I2C_OAR1_ADD1_7 0x000000FEU /*!<Interface Address */
+#define I2C_OAR1_ADD8_9 0x00000300U /*!<Interface Address */
+
+#define I2C_OAR1_ADD0 0x00000001U /*!<Bit 0 */
+#define I2C_OAR1_ADD1 0x00000002U /*!<Bit 1 */
+#define I2C_OAR1_ADD2 0x00000004U /*!<Bit 2 */
+#define I2C_OAR1_ADD3 0x00000008U /*!<Bit 3 */
+#define I2C_OAR1_ADD4 0x00000010U /*!<Bit 4 */
+#define I2C_OAR1_ADD5 0x00000020U /*!<Bit 5 */
+#define I2C_OAR1_ADD6 0x00000040U /*!<Bit 6 */
+#define I2C_OAR1_ADD7 0x00000080U /*!<Bit 7 */
+#define I2C_OAR1_ADD8 0x00000100U /*!<Bit 8 */
+#define I2C_OAR1_ADD9 0x00000200U /*!<Bit 9 */
+
+#define I2C_OAR1_ADDMODE 0x00008000U /*!<Addressing Mode (Slave mode) */
+
+/******************* Bit definition for I2C_OAR2 register *******************/
+#define I2C_OAR2_ENDUAL 0x00000001U /*!<Dual addressing mode enable */
+#define I2C_OAR2_ADD2 0x000000FEU /*!<Interface address */
+
+/******************** Bit definition for I2C_DR register ********************/
+#define I2C_DR_DR 0x000000FFU /*!<8-bit Data Register */
+
+/******************* Bit definition for I2C_SR1 register ********************/
+#define I2C_SR1_SB 0x00000001U /*!<Start Bit (Master mode) */
+#define I2C_SR1_ADDR 0x00000002U /*!<Address sent (master mode)/matched (slave mode) */
+#define I2C_SR1_BTF 0x00000004U /*!<Byte Transfer Finished */
+#define I2C_SR1_ADD10 0x00000008U /*!<10-bit header sent (Master mode) */
+#define I2C_SR1_STOPF 0x00000010U /*!<Stop detection (Slave mode) */
+#define I2C_SR1_RXNE 0x00000040U /*!<Data Register not Empty (receivers) */
+#define I2C_SR1_TXE 0x00000080U /*!<Data Register Empty (transmitters) */
+#define I2C_SR1_BERR 0x00000100U /*!<Bus Error */
+#define I2C_SR1_ARLO 0x00000200U /*!<Arbitration Lost (master mode) */
+#define I2C_SR1_AF 0x00000400U /*!<Acknowledge Failure */
+#define I2C_SR1_OVR 0x00000800U /*!<Overrun/Underrun */
+#define I2C_SR1_PECERR 0x00001000U /*!<PEC Error in reception */
+#define I2C_SR1_TIMEOUT 0x00004000U /*!<Timeout or Tlow Error */
+#define I2C_SR1_SMBALERT 0x00008000U /*!<SMBus Alert */
+
+/******************* Bit definition for I2C_SR2 register ********************/
+#define I2C_SR2_MSL 0x00000001U /*!<Master/Slave */
+#define I2C_SR2_BUSY 0x00000002U /*!<Bus Busy */
+#define I2C_SR2_TRA 0x00000004U /*!<Transmitter/Receiver */
+#define I2C_SR2_GENCALL 0x00000010U /*!<General Call Address (Slave mode) */
+#define I2C_SR2_SMBDEFAULT 0x00000020U /*!<SMBus Device Default Address (Slave mode) */
+#define I2C_SR2_SMBHOST 0x00000040U /*!<SMBus Host Header (Slave mode) */
+#define I2C_SR2_DUALF 0x00000080U /*!<Dual Flag (Slave mode) */
+#define I2C_SR2_PEC 0x0000FF00U /*!<Packet Error Checking Register */
+
+/******************* Bit definition for I2C_CCR register ********************/
+#define I2C_CCR_CCR 0x00000FFFU /*!<Clock Control Register in Fast/Standard mode (Master mode) */
+#define I2C_CCR_DUTY 0x00004000U /*!<Fast Mode Duty Cycle */
+#define I2C_CCR_FS 0x00008000U /*!<I2C Master Mode Selection */
+
+/****************** Bit definition for I2C_TRISE register *******************/
+#define I2C_TRISE_TRISE 0x0000003FU /*!<Maximum Rise Time in Fast/Standard mode (Master mode) */
+
+/****************** Bit definition for I2C_FLTR register *******************/
+#define I2C_FLTR_DNF 0x0000000FU /*!<Digital Noise Filter */
+#define I2C_FLTR_ANOFF 0x00000010U /*!<Analog Noise Filter OFF */
+
+/******************************************************************************/
+/* */
+/* Independent WATCHDOG */
+/* */
+/******************************************************************************/
+/******************* Bit definition for IWDG_KR register ********************/
+#define IWDG_KR_KEY 0xFFFFU /*!<Key value (write only, read 0000h) */
+
+/******************* Bit definition for IWDG_PR register ********************/
+#define IWDG_PR_PR 0x07U /*!<PR[2:0] (Prescaler divider) */
+#define IWDG_PR_PR_0 0x01U /*!<Bit 0 */
+#define IWDG_PR_PR_1 0x02U /*!<Bit 1 */
+#define IWDG_PR_PR_2 0x04U /*!<Bit 2 */
+
+/******************* Bit definition for IWDG_RLR register *******************/
+#define IWDG_RLR_RL 0x0FFFU /*!<Watchdog counter reload value */
+
+/******************* Bit definition for IWDG_SR register ********************/
+#define IWDG_SR_PVU 0x01U /*!<Watchdog prescaler value update */
+#define IWDG_SR_RVU 0x02U /*!<Watchdog counter reload value update */
+
+
+/******************************************************************************/
+/* */
+/* LCD-TFT Display Controller (LTDC) */
+/* */
+/******************************************************************************/
+
+/******************** Bit definition for LTDC_SSCR register *****************/
+
+#define LTDC_SSCR_VSH 0x000007FFU /*!< Vertical Synchronization Height */
+#define LTDC_SSCR_HSW 0x0FFF0000U /*!< Horizontal Synchronization Width */
+
+/******************** Bit definition for LTDC_BPCR register *****************/
+
+#define LTDC_BPCR_AVBP 0x000007FFU /*!< Accumulated Vertical Back Porch */
+#define LTDC_BPCR_AHBP 0x0FFF0000U /*!< Accumulated Horizontal Back Porch */
+
+/******************** Bit definition for LTDC_AWCR register *****************/
+
+#define LTDC_AWCR_AAH 0x000007FFU /*!< Accumulated Active heigh */
+#define LTDC_AWCR_AAW 0x0FFF0000U /*!< Accumulated Active Width */
+
+/******************** Bit definition for LTDC_TWCR register *****************/
+
+#define LTDC_TWCR_TOTALH 0x000007FFU /*!< Total Heigh */
+#define LTDC_TWCR_TOTALW 0x0FFF0000U /*!< Total Width */
+
+/******************** Bit definition for LTDC_GCR register ******************/
+
+#define LTDC_GCR_LTDCEN 0x00000001U /*!< LCD-TFT controller enable bit */
+#define LTDC_GCR_DBW 0x00000070U /*!< Dither Blue Width */
+#define LTDC_GCR_DGW 0x00000700U /*!< Dither Green Width */
+#define LTDC_GCR_DRW 0x00007000U /*!< Dither Red Width */
+#define LTDC_GCR_DEN 0x00010000U /*!< Dither Enable */
+#define LTDC_GCR_PCPOL 0x10000000U /*!< Pixel Clock Polarity */
+#define LTDC_GCR_DEPOL 0x20000000U /*!< Data Enable Polarity */
+#define LTDC_GCR_VSPOL 0x40000000U /*!< Vertical Synchronization Polarity */
+#define LTDC_GCR_HSPOL 0x80000000U /*!< Horizontal Synchronization Polarity */
+
+/* Legacy defines */
+#define LTDC_GCR_DTEN LTDC_GCR_DEN
+
+/******************** Bit definition for LTDC_SRCR register *****************/
+
+#define LTDC_SRCR_IMR 0x00000001U /*!< Immediate Reload */
+#define LTDC_SRCR_VBR 0x00000002U /*!< Vertical Blanking Reload */
+
+/******************** Bit definition for LTDC_BCCR register *****************/
+
+#define LTDC_BCCR_BCBLUE 0x000000FFU /*!< Background Blue value */
+#define LTDC_BCCR_BCGREEN 0x0000FF00U /*!< Background Green value */
+#define LTDC_BCCR_BCRED 0x00FF0000U /*!< Background Red value */
+
+/******************** Bit definition for LTDC_IER register ******************/
+
+#define LTDC_IER_LIE 0x00000001U /*!< Line Interrupt Enable */
+#define LTDC_IER_FUIE 0x00000002U /*!< FIFO Underrun Interrupt Enable */
+#define LTDC_IER_TERRIE 0x00000004U /*!< Transfer Error Interrupt Enable */
+#define LTDC_IER_RRIE 0x00000008U /*!< Register Reload interrupt enable */
+
+/******************** Bit definition for LTDC_ISR register ******************/
+
+#define LTDC_ISR_LIF 0x00000001U /*!< Line Interrupt Flag */
+#define LTDC_ISR_FUIF 0x00000002U /*!< FIFO Underrun Interrupt Flag */
+#define LTDC_ISR_TERRIF 0x00000004U /*!< Transfer Error Interrupt Flag */
+#define LTDC_ISR_RRIF 0x00000008U /*!< Register Reload interrupt Flag */
+
+/******************** Bit definition for LTDC_ICR register ******************/
+
+#define LTDC_ICR_CLIF 0x00000001U /*!< Clears the Line Interrupt Flag */
+#define LTDC_ICR_CFUIF 0x00000002U /*!< Clears the FIFO Underrun Interrupt Flag */
+#define LTDC_ICR_CTERRIF 0x00000004U /*!< Clears the Transfer Error Interrupt Flag */
+#define LTDC_ICR_CRRIF 0x00000008U /*!< Clears Register Reload interrupt Flag */
+
+/******************** Bit definition for LTDC_LIPCR register ****************/
+
+#define LTDC_LIPCR_LIPOS 0x000007FFU /*!< Line Interrupt Position */
+
+/******************** Bit definition for LTDC_CPSR register *****************/
+
+#define LTDC_CPSR_CYPOS 0x0000FFFFU /*!< Current Y Position */
+#define LTDC_CPSR_CXPOS 0xFFFF0000U /*!< Current X Position */
+
+/******************** Bit definition for LTDC_CDSR register *****************/
+
+#define LTDC_CDSR_VDES 0x00000001U /*!< Vertical Data Enable Status */
+#define LTDC_CDSR_HDES 0x00000002U /*!< Horizontal Data Enable Status */
+#define LTDC_CDSR_VSYNCS 0x00000004U /*!< Vertical Synchronization Status */
+#define LTDC_CDSR_HSYNCS 0x00000008U /*!< Horizontal Synchronization Status */
+
+/******************** Bit definition for LTDC_LxCR register *****************/
+
+#define LTDC_LxCR_LEN 0x00000001U /*!< Layer Enable */
+#define LTDC_LxCR_COLKEN 0x00000002U /*!< Color Keying Enable */
+#define LTDC_LxCR_CLUTEN 0x00000010U /*!< Color Lockup Table Enable */
+
+/******************** Bit definition for LTDC_LxWHPCR register **************/
+
+#define LTDC_LxWHPCR_WHSTPOS 0x00000FFFU /*!< Window Horizontal Start Position */
+#define LTDC_LxWHPCR_WHSPPOS 0xFFFF0000U /*!< Window Horizontal Stop Position */
+
+/******************** Bit definition for LTDC_LxWVPCR register **************/
+
+#define LTDC_LxWVPCR_WVSTPOS 0x00000FFFU /*!< Window Vertical Start Position */
+#define LTDC_LxWVPCR_WVSPPOS 0xFFFF0000U /*!< Window Vertical Stop Position */
+
+/******************** Bit definition for LTDC_LxCKCR register ***************/
+
+#define LTDC_LxCKCR_CKBLUE 0x000000FFU /*!< Color Key Blue value */
+#define LTDC_LxCKCR_CKGREEN 0x0000FF00U /*!< Color Key Green value */
+#define LTDC_LxCKCR_CKRED 0x00FF0000U /*!< Color Key Red value */
+
+/******************** Bit definition for LTDC_LxPFCR register ***************/
+
+#define LTDC_LxPFCR_PF 0x00000007U /*!< Pixel Format */
+
+/******************** Bit definition for LTDC_LxCACR register ***************/
+
+#define LTDC_LxCACR_CONSTA 0x000000FFU /*!< Constant Alpha */
+
+/******************** Bit definition for LTDC_LxDCCR register ***************/
+
+#define LTDC_LxDCCR_DCBLUE 0x000000FFU /*!< Default Color Blue */
+#define LTDC_LxDCCR_DCGREEN 0x0000FF00U /*!< Default Color Green */
+#define LTDC_LxDCCR_DCRED 0x00FF0000U /*!< Default Color Red */
+#define LTDC_LxDCCR_DCALPHA 0xFF000000U /*!< Default Color Alpha */
+
+/******************** Bit definition for LTDC_LxBFCR register ***************/
+
+#define LTDC_LxBFCR_BF2 0x00000007U /*!< Blending Factor 2 */
+#define LTDC_LxBFCR_BF1 0x00000700U /*!< Blending Factor 1 */
+
+/******************** Bit definition for LTDC_LxCFBAR register **************/
+
+#define LTDC_LxCFBAR_CFBADD 0xFFFFFFFFU /*!< Color Frame Buffer Start Address */
+
+/******************** Bit definition for LTDC_LxCFBLR register **************/
+
+#define LTDC_LxCFBLR_CFBLL 0x00001FFFU /*!< Color Frame Buffer Line Length */
+#define LTDC_LxCFBLR_CFBP 0x1FFF0000U /*!< Color Frame Buffer Pitch in bytes */
+
+/******************** Bit definition for LTDC_LxCFBLNR register *************/
+
+#define LTDC_LxCFBLNR_CFBLNBR 0x000007FFU /*!< Frame Buffer Line Number */
+
+/******************** Bit definition for LTDC_LxCLUTWR register *************/
+
+#define LTDC_LxCLUTWR_BLUE 0x000000FFU /*!< Blue value */
+#define LTDC_LxCLUTWR_GREEN 0x0000FF00U /*!< Green value */
+#define LTDC_LxCLUTWR_RED 0x00FF0000U /*!< Red value */
+#define LTDC_LxCLUTWR_CLUTADD 0xFF000000U /*!< CLUT address */
+
+
+/******************************************************************************/
+/* */
+/* Power Control */
+/* */
+/******************************************************************************/
+/******************** Bit definition for PWR_CR register ********************/
+#define PWR_CR_LPDS 0x00000001U /*!< Low-Power Deepsleep */
+#define PWR_CR_PDDS 0x00000002U /*!< Power Down Deepsleep */
+#define PWR_CR_CWUF 0x00000004U /*!< Clear Wakeup Flag */
+#define PWR_CR_CSBF 0x00000008U /*!< Clear Standby Flag */
+#define PWR_CR_PVDE 0x00000010U /*!< Power Voltage Detector Enable */
+
+#define PWR_CR_PLS 0x000000E0U /*!< PLS[2:0] bits (PVD Level Selection) */
+#define PWR_CR_PLS_0 0x00000020U /*!< Bit 0 */
+#define PWR_CR_PLS_1 0x00000040U /*!< Bit 1 */
+#define PWR_CR_PLS_2 0x00000080U /*!< Bit 2 */
+
+/*!< PVD level configuration */
+#define PWR_CR_PLS_LEV0 0x00000000U /*!< PVD level 0 */
+#define PWR_CR_PLS_LEV1 0x00000020U /*!< PVD level 1 */
+#define PWR_CR_PLS_LEV2 0x00000040U /*!< PVD level 2 */
+#define PWR_CR_PLS_LEV3 0x00000060U /*!< PVD level 3 */
+#define PWR_CR_PLS_LEV4 0x00000080U /*!< PVD level 4 */
+#define PWR_CR_PLS_LEV5 0x000000A0U /*!< PVD level 5 */
+#define PWR_CR_PLS_LEV6 0x000000C0U /*!< PVD level 6 */
+#define PWR_CR_PLS_LEV7 0x000000E0U /*!< PVD level 7 */
+#define PWR_CR_DBP 0x00000100U /*!< Disable Backup Domain write protection */
+#define PWR_CR_FPDS 0x00000200U /*!< Flash power down in Stop mode */
+#define PWR_CR_LPLVDS 0x00000400U /*!< Low-Power Regulator Low Voltage Scaling in Stop mode */
+#define PWR_CR_MRLVDS 0x00000800U /*!< Main regulator Low Voltage Scaling in Stop mode */
+#define PWR_CR_ADCDC1 0x00002000U /*!< Refer to AN4073 on how to use this bit */
+#define PWR_CR_VOS 0x0000C000U /*!< VOS[1:0] bits (Regulator voltage scaling output selection) */
+#define PWR_CR_VOS_0 0x00004000U /*!< Bit 0 */
+#define PWR_CR_VOS_1 0x00008000U /*!< Bit 1 */
+#define PWR_CR_ODEN 0x00010000U /*!< Over Drive enable */
+#define PWR_CR_ODSWEN 0x00020000U /*!< Over Drive switch enabled */
+#define PWR_CR_UDEN 0x000C0000U /*!< Under Drive enable in stop mode */
+#define PWR_CR_UDEN_0 0x00040000U /*!< Bit 0 */
+#define PWR_CR_UDEN_1 0x00080000U /*!< Bit 1 */
+
+/* Legacy define */
+#define PWR_CR_PMODE PWR_CR_VOS
+#define PWR_CR_LPUDS PWR_CR_LPLVDS /*!< Low-Power Regulator in deepsleep under-drive mode */
+#define PWR_CR_MRUDS PWR_CR_MRLVDS /*!< Main regulator in deepsleep under-drive mode */
+
+/******************* Bit definition for PWR_CSR register ********************/
+#define PWR_CSR_WUF 0x00000001U /*!< Wakeup Flag */
+#define PWR_CSR_SBF 0x00000002U /*!< Standby Flag */
+#define PWR_CSR_PVDO 0x00000004U /*!< PVD Output */
+#define PWR_CSR_BRR 0x00000008U /*!< Backup regulator ready */
+#define PWR_CSR_EWUP 0x00000100U /*!< Enable WKUP pin */
+#define PWR_CSR_BRE 0x00000200U /*!< Backup regulator enable */
+#define PWR_CSR_VOSRDY 0x00004000U /*!< Regulator voltage scaling output selection ready */
+#define PWR_CSR_ODRDY 0x00010000U /*!< Over Drive generator ready */
+#define PWR_CSR_ODSWRDY 0x00020000U /*!< Over Drive Switch ready */
+#define PWR_CSR_UDSWRDY 0x000C0000U /*!< Under Drive ready */
+
+/* Legacy define */
+#define PWR_CSR_REGRDY PWR_CSR_VOSRDY
+
+/******************************************************************************/
+/* */
+/* Reset and Clock Control */
+/* */
+/******************************************************************************/
+/******************** Bit definition for RCC_CR register ********************/
+#define RCC_CR_HSION 0x00000001U
+#define RCC_CR_HSIRDY 0x00000002U
+
+#define RCC_CR_HSITRIM 0x000000F8U
+#define RCC_CR_HSITRIM_0 0x00000008U/*!<Bit 0 */
+#define RCC_CR_HSITRIM_1 0x00000010U/*!<Bit 1 */
+#define RCC_CR_HSITRIM_2 0x00000020U/*!<Bit 2 */
+#define RCC_CR_HSITRIM_3 0x00000040U/*!<Bit 3 */
+#define RCC_CR_HSITRIM_4 0x00000080U/*!<Bit 4 */
+
+#define RCC_CR_HSICAL 0x0000FF00U
+#define RCC_CR_HSICAL_0 0x00000100U/*!<Bit 0 */
+#define RCC_CR_HSICAL_1 0x00000200U/*!<Bit 1 */
+#define RCC_CR_HSICAL_2 0x00000400U/*!<Bit 2 */
+#define RCC_CR_HSICAL_3 0x00000800U/*!<Bit 3 */
+#define RCC_CR_HSICAL_4 0x00001000U/*!<Bit 4 */
+#define RCC_CR_HSICAL_5 0x00002000U/*!<Bit 5 */
+#define RCC_CR_HSICAL_6 0x00004000U/*!<Bit 6 */
+#define RCC_CR_HSICAL_7 0x00008000U/*!<Bit 7 */
+
+#define RCC_CR_HSEON 0x00010000U
+#define RCC_CR_HSERDY 0x00020000U
+#define RCC_CR_HSEBYP 0x00040000U
+#define RCC_CR_CSSON 0x00080000U
+#define RCC_CR_PLLON 0x01000000U
+#define RCC_CR_PLLRDY 0x02000000U
+#define RCC_CR_PLLI2SON 0x04000000U
+#define RCC_CR_PLLI2SRDY 0x08000000U
+#define RCC_CR_PLLSAION 0x10000000U
+#define RCC_CR_PLLSAIRDY 0x20000000U
+
+/******************** Bit definition for RCC_PLLCFGR register ***************/
+#define RCC_PLLCFGR_PLLM 0x0000003FU
+#define RCC_PLLCFGR_PLLM_0 0x00000001U
+#define RCC_PLLCFGR_PLLM_1 0x00000002U
+#define RCC_PLLCFGR_PLLM_2 0x00000004U
+#define RCC_PLLCFGR_PLLM_3 0x00000008U
+#define RCC_PLLCFGR_PLLM_4 0x00000010U
+#define RCC_PLLCFGR_PLLM_5 0x00000020U
+
+#define RCC_PLLCFGR_PLLN 0x00007FC0U
+#define RCC_PLLCFGR_PLLN_0 0x00000040U
+#define RCC_PLLCFGR_PLLN_1 0x00000080U
+#define RCC_PLLCFGR_PLLN_2 0x00000100U
+#define RCC_PLLCFGR_PLLN_3 0x00000200U
+#define RCC_PLLCFGR_PLLN_4 0x00000400U
+#define RCC_PLLCFGR_PLLN_5 0x00000800U
+#define RCC_PLLCFGR_PLLN_6 0x00001000U
+#define RCC_PLLCFGR_PLLN_7 0x00002000U
+#define RCC_PLLCFGR_PLLN_8 0x00004000U
+
+#define RCC_PLLCFGR_PLLP 0x00030000U
+#define RCC_PLLCFGR_PLLP_0 0x00010000U
+#define RCC_PLLCFGR_PLLP_1 0x00020000U
+
+#define RCC_PLLCFGR_PLLSRC 0x00400000U
+#define RCC_PLLCFGR_PLLSRC_HSE 0x00400000U
+#define RCC_PLLCFGR_PLLSRC_HSI 0x00000000U
+
+#define RCC_PLLCFGR_PLLQ 0x0F000000U
+#define RCC_PLLCFGR_PLLQ_0 0x01000000U
+#define RCC_PLLCFGR_PLLQ_1 0x02000000U
+#define RCC_PLLCFGR_PLLQ_2 0x04000000U
+#define RCC_PLLCFGR_PLLQ_3 0x08000000U
+
+/******************** Bit definition for RCC_CFGR register ******************/
+/*!< SW configuration */
+#define RCC_CFGR_SW 0x00000003U /*!< SW[1:0] bits (System clock Switch) */
+#define RCC_CFGR_SW_0 0x00000001U /*!< Bit 0 */
+#define RCC_CFGR_SW_1 0x00000002U /*!< Bit 1 */
+
+#define RCC_CFGR_SW_HSI 0x00000000U /*!< HSI selected as system clock */
+#define RCC_CFGR_SW_HSE 0x00000001U /*!< HSE selected as system clock */
+#define RCC_CFGR_SW_PLL 0x00000002U /*!< PLL selected as system clock */
+
+/*!< SWS configuration */
+#define RCC_CFGR_SWS 0x0000000CU /*!< SWS[1:0] bits (System Clock Switch Status) */
+#define RCC_CFGR_SWS_0 0x00000004U /*!< Bit 0 */
+#define RCC_CFGR_SWS_1 0x00000008U /*!< Bit 1 */
+
+#define RCC_CFGR_SWS_HSI 0x00000000U /*!< HSI oscillator used as system clock */
+#define RCC_CFGR_SWS_HSE 0x00000004U /*!< HSE oscillator used as system clock */
+#define RCC_CFGR_SWS_PLL 0x00000008U /*!< PLL used as system clock */
+
+/*!< HPRE configuration */
+#define RCC_CFGR_HPRE 0x000000F0U /*!< HPRE[3:0] bits (AHB prescaler) */
+#define RCC_CFGR_HPRE_0 0x00000010U /*!< Bit 0 */
+#define RCC_CFGR_HPRE_1 0x00000020U /*!< Bit 1 */
+#define RCC_CFGR_HPRE_2 0x00000040U /*!< Bit 2 */
+#define RCC_CFGR_HPRE_3 0x00000080U /*!< Bit 3 */
+
+#define RCC_CFGR_HPRE_DIV1 0x00000000U /*!< SYSCLK not divided */
+#define RCC_CFGR_HPRE_DIV2 0x00000080U /*!< SYSCLK divided by 2 */
+#define RCC_CFGR_HPRE_DIV4 0x00000090U /*!< SYSCLK divided by 4 */
+#define RCC_CFGR_HPRE_DIV8 0x000000A0U /*!< SYSCLK divided by 8 */
+#define RCC_CFGR_HPRE_DIV16 0x000000B0U /*!< SYSCLK divided by 16 */
+#define RCC_CFGR_HPRE_DIV64 0x000000C0U /*!< SYSCLK divided by 64 */
+#define RCC_CFGR_HPRE_DIV128 0x000000D0U /*!< SYSCLK divided by 128 */
+#define RCC_CFGR_HPRE_DIV256 0x000000E0U /*!< SYSCLK divided by 256 */
+#define RCC_CFGR_HPRE_DIV512 0x000000F0U /*!< SYSCLK divided by 512 */
+
+/*!< PPRE1 configuration */
+#define RCC_CFGR_PPRE1 0x00001C00U /*!< PRE1[2:0] bits (APB1 prescaler) */
+#define RCC_CFGR_PPRE1_0 0x00000400U /*!< Bit 0 */
+#define RCC_CFGR_PPRE1_1 0x00000800U /*!< Bit 1 */
+#define RCC_CFGR_PPRE1_2 0x00001000U /*!< Bit 2 */
+
+#define RCC_CFGR_PPRE1_DIV1 0x00000000U /*!< HCLK not divided */
+#define RCC_CFGR_PPRE1_DIV2 0x00001000U /*!< HCLK divided by 2 */
+#define RCC_CFGR_PPRE1_DIV4 0x00001400U /*!< HCLK divided by 4 */
+#define RCC_CFGR_PPRE1_DIV8 0x00001800U /*!< HCLK divided by 8 */
+#define RCC_CFGR_PPRE1_DIV16 0x00001C00U /*!< HCLK divided by 16 */
+
+/*!< PPRE2 configuration */
+#define RCC_CFGR_PPRE2 0x0000E000U /*!< PRE2[2:0] bits (APB2 prescaler) */
+#define RCC_CFGR_PPRE2_0 0x00002000U /*!< Bit 0 */
+#define RCC_CFGR_PPRE2_1 0x00004000U /*!< Bit 1 */
+#define RCC_CFGR_PPRE2_2 0x00008000U /*!< Bit 2 */
+
+#define RCC_CFGR_PPRE2_DIV1 0x00000000U /*!< HCLK not divided */
+#define RCC_CFGR_PPRE2_DIV2 0x00008000U /*!< HCLK divided by 2 */
+#define RCC_CFGR_PPRE2_DIV4 0x0000A000U /*!< HCLK divided by 4 */
+#define RCC_CFGR_PPRE2_DIV8 0x0000C000U /*!< HCLK divided by 8 */
+#define RCC_CFGR_PPRE2_DIV16 0x0000E000U /*!< HCLK divided by 16 */
+
+/*!< RTCPRE configuration */
+#define RCC_CFGR_RTCPRE 0x001F0000U
+#define RCC_CFGR_RTCPRE_0 0x00010000U
+#define RCC_CFGR_RTCPRE_1 0x00020000U
+#define RCC_CFGR_RTCPRE_2 0x00040000U
+#define RCC_CFGR_RTCPRE_3 0x00080000U
+#define RCC_CFGR_RTCPRE_4 0x00100000U
+
+/*!< MCO1 configuration */
+#define RCC_CFGR_MCO1 0x00600000U
+#define RCC_CFGR_MCO1_0 0x00200000U
+#define RCC_CFGR_MCO1_1 0x00400000U
+
+#define RCC_CFGR_I2SSRC 0x00800000U
+
+#define RCC_CFGR_MCO1PRE 0x07000000U
+#define RCC_CFGR_MCO1PRE_0 0x01000000U
+#define RCC_CFGR_MCO1PRE_1 0x02000000U
+#define RCC_CFGR_MCO1PRE_2 0x04000000U
+
+#define RCC_CFGR_MCO2PRE 0x38000000U
+#define RCC_CFGR_MCO2PRE_0 0x08000000U
+#define RCC_CFGR_MCO2PRE_1 0x10000000U
+#define RCC_CFGR_MCO2PRE_2 0x20000000U
+
+#define RCC_CFGR_MCO2 0xC0000000U
+#define RCC_CFGR_MCO2_0 0x40000000U
+#define RCC_CFGR_MCO2_1 0x80000000U
+
+/******************** Bit definition for RCC_CIR register *******************/
+#define RCC_CIR_LSIRDYF 0x00000001U
+#define RCC_CIR_LSERDYF 0x00000002U
+#define RCC_CIR_HSIRDYF 0x00000004U
+#define RCC_CIR_HSERDYF 0x00000008U
+#define RCC_CIR_PLLRDYF 0x00000010U
+#define RCC_CIR_PLLI2SRDYF 0x00000020U
+#define RCC_CIR_PLLSAIRDYF 0x00000040U
+#define RCC_CIR_CSSF 0x00000080U
+#define RCC_CIR_LSIRDYIE 0x00000100U
+#define RCC_CIR_LSERDYIE 0x00000200U
+#define RCC_CIR_HSIRDYIE 0x00000400U
+#define RCC_CIR_HSERDYIE 0x00000800U
+#define RCC_CIR_PLLRDYIE 0x00001000U
+#define RCC_CIR_PLLI2SRDYIE 0x00002000U
+#define RCC_CIR_PLLSAIRDYIE 0x00004000U
+#define RCC_CIR_LSIRDYC 0x00010000U
+#define RCC_CIR_LSERDYC 0x00020000U
+#define RCC_CIR_HSIRDYC 0x00040000U
+#define RCC_CIR_HSERDYC 0x00080000U
+#define RCC_CIR_PLLRDYC 0x00100000U
+#define RCC_CIR_PLLI2SRDYC 0x00200000U
+#define RCC_CIR_PLLSAIRDYC 0x00400000U
+#define RCC_CIR_CSSC 0x00800000U
+
+/******************** Bit definition for RCC_AHB1RSTR register **************/
+#define RCC_AHB1RSTR_GPIOARST 0x00000001U
+#define RCC_AHB1RSTR_GPIOBRST 0x00000002U
+#define RCC_AHB1RSTR_GPIOCRST 0x00000004U
+#define RCC_AHB1RSTR_GPIODRST 0x00000008U
+#define RCC_AHB1RSTR_GPIOERST 0x00000010U
+#define RCC_AHB1RSTR_GPIOFRST 0x00000020U
+#define RCC_AHB1RSTR_GPIOGRST 0x00000040U
+#define RCC_AHB1RSTR_GPIOHRST 0x00000080U
+#define RCC_AHB1RSTR_GPIOIRST 0x00000100U
+#define RCC_AHB1RSTR_GPIOJRST 0x00000200U
+#define RCC_AHB1RSTR_GPIOKRST 0x00000400U
+#define RCC_AHB1RSTR_CRCRST 0x00001000U
+#define RCC_AHB1RSTR_DMA1RST 0x00200000U
+#define RCC_AHB1RSTR_DMA2RST 0x00400000U
+#define RCC_AHB1RSTR_DMA2DRST 0x00800000U
+#define RCC_AHB1RSTR_ETHMACRST 0x02000000U
+#define RCC_AHB1RSTR_OTGHRST 0x20000000U
+
+/******************** Bit definition for RCC_AHB2RSTR register **************/
+#define RCC_AHB2RSTR_DCMIRST 0x00000001U
+#define RCC_AHB2RSTR_CRYPRST 0x00000010U
+#define RCC_AHB2RSTR_HASHRST 0x00000020U
+ /* maintained for legacy purpose */
+ #define RCC_AHB2RSTR_HSAHRST RCC_AHB2RSTR_HASHRST
+#define RCC_AHB2RSTR_RNGRST 0x00000040U
+#define RCC_AHB2RSTR_OTGFSRST 0x00000080U
+
+/******************** Bit definition for RCC_AHB3RSTR register **************/
+#define RCC_AHB3RSTR_FMCRST 0x00000001U
+
+/******************** Bit definition for RCC_APB1RSTR register **************/
+#define RCC_APB1RSTR_TIM2RST 0x00000001U
+#define RCC_APB1RSTR_TIM3RST 0x00000002U
+#define RCC_APB1RSTR_TIM4RST 0x00000004U
+#define RCC_APB1RSTR_TIM5RST 0x00000008U
+#define RCC_APB1RSTR_TIM6RST 0x00000010U
+#define RCC_APB1RSTR_TIM7RST 0x00000020U
+#define RCC_APB1RSTR_TIM12RST 0x00000040U
+#define RCC_APB1RSTR_TIM13RST 0x00000080U
+#define RCC_APB1RSTR_TIM14RST 0x00000100U
+#define RCC_APB1RSTR_WWDGRST 0x00000800U
+#define RCC_APB1RSTR_SPI2RST 0x00004000U
+#define RCC_APB1RSTR_SPI3RST 0x00008000U
+#define RCC_APB1RSTR_USART2RST 0x00020000U
+#define RCC_APB1RSTR_USART3RST 0x00040000U
+#define RCC_APB1RSTR_UART4RST 0x00080000U
+#define RCC_APB1RSTR_UART5RST 0x00100000U
+#define RCC_APB1RSTR_I2C1RST 0x00200000U
+#define RCC_APB1RSTR_I2C2RST 0x00400000U
+#define RCC_APB1RSTR_I2C3RST 0x00800000U
+#define RCC_APB1RSTR_CAN1RST 0x02000000U
+#define RCC_APB1RSTR_CAN2RST 0x04000000U
+#define RCC_APB1RSTR_PWRRST 0x10000000U
+#define RCC_APB1RSTR_DACRST 0x20000000U
+#define RCC_APB1RSTR_UART7RST 0x40000000U
+#define RCC_APB1RSTR_UART8RST 0x80000000U
+
+/******************** Bit definition for RCC_APB2RSTR register **************/
+#define RCC_APB2RSTR_TIM1RST 0x00000001U
+#define RCC_APB2RSTR_TIM8RST 0x00000002U
+#define RCC_APB2RSTR_USART1RST 0x00000010U
+#define RCC_APB2RSTR_USART6RST 0x00000020U
+#define RCC_APB2RSTR_ADCRST 0x00000100U
+#define RCC_APB2RSTR_SDIORST 0x00000800U
+#define RCC_APB2RSTR_SPI1RST 0x00001000U
+#define RCC_APB2RSTR_SPI4RST 0x00002000U
+#define RCC_APB2RSTR_SYSCFGRST 0x00004000U
+#define RCC_APB2RSTR_TIM9RST 0x00010000U
+#define RCC_APB2RSTR_TIM10RST 0x00020000U
+#define RCC_APB2RSTR_TIM11RST 0x00040000U
+#define RCC_APB2RSTR_SPI5RST 0x00100000U
+#define RCC_APB2RSTR_SPI6RST 0x00200000U
+#define RCC_APB2RSTR_SAI1RST 0x00400000U
+#define RCC_APB2RSTR_LTDCRST 0x04000000U
+
+/* Old SPI1RST bit definition, maintained for legacy purpose */
+#define RCC_APB2RSTR_SPI1 RCC_APB2RSTR_SPI1RST
+
+/******************** Bit definition for RCC_AHB1ENR register ***************/
+#define RCC_AHB1ENR_GPIOAEN 0x00000001U
+#define RCC_AHB1ENR_GPIOBEN 0x00000002U
+#define RCC_AHB1ENR_GPIOCEN 0x00000004U
+#define RCC_AHB1ENR_GPIODEN 0x00000008U
+#define RCC_AHB1ENR_GPIOEEN 0x00000010U
+#define RCC_AHB1ENR_GPIOFEN 0x00000020U
+#define RCC_AHB1ENR_GPIOGEN 0x00000040U
+#define RCC_AHB1ENR_GPIOHEN 0x00000080U
+#define RCC_AHB1ENR_GPIOIEN 0x00000100U
+#define RCC_AHB1ENR_GPIOJEN 0x00000200U
+#define RCC_AHB1ENR_GPIOKEN 0x00000400U
+
+#define RCC_AHB1ENR_CRCEN 0x00001000U
+#define RCC_AHB1ENR_BKPSRAMEN 0x00040000U
+#define RCC_AHB1ENR_CCMDATARAMEN 0x00100000U
+#define RCC_AHB1ENR_DMA1EN 0x00200000U
+#define RCC_AHB1ENR_DMA2EN 0x00400000U
+#define RCC_AHB1ENR_DMA2DEN 0x00800000U
+
+#define RCC_AHB1ENR_ETHMACEN 0x02000000U
+#define RCC_AHB1ENR_ETHMACTXEN 0x04000000U
+#define RCC_AHB1ENR_ETHMACRXEN 0x08000000U
+#define RCC_AHB1ENR_ETHMACPTPEN 0x10000000U
+#define RCC_AHB1ENR_OTGHSEN 0x20000000U
+#define RCC_AHB1ENR_OTGHSULPIEN 0x40000000U
+
+/******************** Bit definition for RCC_AHB2ENR register ***************/
+#define RCC_AHB2ENR_DCMIEN 0x00000001U
+#define RCC_AHB2ENR_CRYPEN 0x00000010U
+#define RCC_AHB2ENR_HASHEN 0x00000020U
+#define RCC_AHB2ENR_RNGEN 0x00000040U
+#define RCC_AHB2ENR_OTGFSEN 0x00000080U
+
+/******************** Bit definition for RCC_AHB3ENR register ***************/
+#define RCC_AHB3ENR_FMCEN 0x00000001U
+
+/******************** Bit definition for RCC_APB1ENR register ***************/
+#define RCC_APB1ENR_TIM2EN 0x00000001U
+#define RCC_APB1ENR_TIM3EN 0x00000002U
+#define RCC_APB1ENR_TIM4EN 0x00000004U
+#define RCC_APB1ENR_TIM5EN 0x00000008U
+#define RCC_APB1ENR_TIM6EN 0x00000010U
+#define RCC_APB1ENR_TIM7EN 0x00000020U
+#define RCC_APB1ENR_TIM12EN 0x00000040U
+#define RCC_APB1ENR_TIM13EN 0x00000080U
+#define RCC_APB1ENR_TIM14EN 0x00000100U
+#define RCC_APB1ENR_WWDGEN 0x00000800U
+#define RCC_APB1ENR_SPI2EN 0x00004000U
+#define RCC_APB1ENR_SPI3EN 0x00008000U
+#define RCC_APB1ENR_USART2EN 0x00020000U
+#define RCC_APB1ENR_USART3EN 0x00040000U
+#define RCC_APB1ENR_UART4EN 0x00080000U
+#define RCC_APB1ENR_UART5EN 0x00100000U
+#define RCC_APB1ENR_I2C1EN 0x00200000U
+#define RCC_APB1ENR_I2C2EN 0x00400000U
+#define RCC_APB1ENR_I2C3EN 0x00800000U
+#define RCC_APB1ENR_CAN1EN 0x02000000U
+#define RCC_APB1ENR_CAN2EN 0x04000000U
+#define RCC_APB1ENR_PWREN 0x10000000U
+#define RCC_APB1ENR_DACEN 0x20000000U
+#define RCC_APB1ENR_UART7EN 0x40000000U
+#define RCC_APB1ENR_UART8EN 0x80000000U
+
+/******************** Bit definition for RCC_APB2ENR register ***************/
+#define RCC_APB2ENR_TIM1EN 0x00000001U
+#define RCC_APB2ENR_TIM8EN 0x00000002U
+#define RCC_APB2ENR_USART1EN 0x00000010U
+#define RCC_APB2ENR_USART6EN 0x00000020U
+#define RCC_APB2ENR_ADC1EN 0x00000100U
+#define RCC_APB2ENR_ADC2EN 0x00000200U
+#define RCC_APB2ENR_ADC3EN 0x00000400U
+#define RCC_APB2ENR_SDIOEN 0x00000800U
+#define RCC_APB2ENR_SPI1EN 0x00001000U
+#define RCC_APB2ENR_SPI4EN 0x00002000U
+#define RCC_APB2ENR_SYSCFGEN 0x00004000U
+#define RCC_APB2ENR_TIM9EN 0x00010000U
+#define RCC_APB2ENR_TIM10EN 0x00020000U
+#define RCC_APB2ENR_TIM11EN 0x00040000U
+#define RCC_APB2ENR_SPI5EN 0x00100000U
+#define RCC_APB2ENR_SPI6EN 0x00200000U
+#define RCC_APB2ENR_SAI1EN 0x00400000U
+#define RCC_APB2ENR_LTDCEN 0x04000000U
+
+/******************** Bit definition for RCC_AHB1LPENR register *************/
+#define RCC_AHB1LPENR_GPIOALPEN 0x00000001U
+#define RCC_AHB1LPENR_GPIOBLPEN 0x00000002U
+#define RCC_AHB1LPENR_GPIOCLPEN 0x00000004U
+#define RCC_AHB1LPENR_GPIODLPEN 0x00000008U
+#define RCC_AHB1LPENR_GPIOELPEN 0x00000010U
+#define RCC_AHB1LPENR_GPIOFLPEN 0x00000020U
+#define RCC_AHB1LPENR_GPIOGLPEN 0x00000040U
+#define RCC_AHB1LPENR_GPIOHLPEN 0x00000080U
+#define RCC_AHB1LPENR_GPIOILPEN 0x00000100U
+#define RCC_AHB1LPENR_GPIOJLPEN 0x00000200U
+#define RCC_AHB1LPENR_GPIOKLPEN 0x00000400U
+
+#define RCC_AHB1LPENR_CRCLPEN 0x00001000U
+#define RCC_AHB1LPENR_FLITFLPEN 0x00008000U
+#define RCC_AHB1LPENR_SRAM1LPEN 0x00010000U
+#define RCC_AHB1LPENR_SRAM2LPEN 0x00020000U
+#define RCC_AHB1LPENR_BKPSRAMLPEN 0x00040000U
+#define RCC_AHB1LPENR_SRAM3LPEN 0x00080000U
+#define RCC_AHB1LPENR_DMA1LPEN 0x00200000U
+#define RCC_AHB1LPENR_DMA2LPEN 0x00400000U
+#define RCC_AHB1LPENR_DMA2DLPEN 0x00800000U
+
+#define RCC_AHB1LPENR_ETHMACLPEN 0x02000000U
+#define RCC_AHB1LPENR_ETHMACTXLPEN 0x04000000U
+#define RCC_AHB1LPENR_ETHMACRXLPEN 0x08000000U
+#define RCC_AHB1LPENR_ETHMACPTPLPEN 0x10000000U
+#define RCC_AHB1LPENR_OTGHSLPEN 0x20000000U
+#define RCC_AHB1LPENR_OTGHSULPILPEN 0x40000000U
+
+/******************** Bit definition for RCC_AHB2LPENR register *************/
+#define RCC_AHB2LPENR_DCMILPEN 0x00000001U
+#define RCC_AHB2LPENR_CRYPLPEN 0x00000010U
+#define RCC_AHB2LPENR_HASHLPEN 0x00000020U
+#define RCC_AHB2LPENR_RNGLPEN 0x00000040U
+#define RCC_AHB2LPENR_OTGFSLPEN 0x00000080U
+
+/******************** Bit definition for RCC_AHB3LPENR register *************/
+#define RCC_AHB3LPENR_FMCLPEN 0x00000001U
+
+/******************** Bit definition for RCC_APB1LPENR register *************/
+#define RCC_APB1LPENR_TIM2LPEN 0x00000001U
+#define RCC_APB1LPENR_TIM3LPEN 0x00000002U
+#define RCC_APB1LPENR_TIM4LPEN 0x00000004U
+#define RCC_APB1LPENR_TIM5LPEN 0x00000008U
+#define RCC_APB1LPENR_TIM6LPEN 0x00000010U
+#define RCC_APB1LPENR_TIM7LPEN 0x00000020U
+#define RCC_APB1LPENR_TIM12LPEN 0x00000040U
+#define RCC_APB1LPENR_TIM13LPEN 0x00000080U
+#define RCC_APB1LPENR_TIM14LPEN 0x00000100U
+#define RCC_APB1LPENR_WWDGLPEN 0x00000800U
+#define RCC_APB1LPENR_SPI2LPEN 0x00004000U
+#define RCC_APB1LPENR_SPI3LPEN 0x00008000U
+#define RCC_APB1LPENR_USART2LPEN 0x00020000U
+#define RCC_APB1LPENR_USART3LPEN 0x00040000U
+#define RCC_APB1LPENR_UART4LPEN 0x00080000U
+#define RCC_APB1LPENR_UART5LPEN 0x00100000U
+#define RCC_APB1LPENR_I2C1LPEN 0x00200000U
+#define RCC_APB1LPENR_I2C2LPEN 0x00400000U
+#define RCC_APB1LPENR_I2C3LPEN 0x00800000U
+#define RCC_APB1LPENR_CAN1LPEN 0x02000000U
+#define RCC_APB1LPENR_CAN2LPEN 0x04000000U
+#define RCC_APB1LPENR_PWRLPEN 0x10000000U
+#define RCC_APB1LPENR_DACLPEN 0x20000000U
+#define RCC_APB1LPENR_UART7LPEN 0x40000000U
+#define RCC_APB1LPENR_UART8LPEN 0x80000000U
+
+/******************** Bit definition for RCC_APB2LPENR register *************/
+#define RCC_APB2LPENR_TIM1LPEN 0x00000001U
+#define RCC_APB2LPENR_TIM8LPEN 0x00000002U
+#define RCC_APB2LPENR_USART1LPEN 0x00000010U
+#define RCC_APB2LPENR_USART6LPEN 0x00000020U
+#define RCC_APB2LPENR_ADC1LPEN 0x00000100U
+#define RCC_APB2LPENR_ADC2LPEN 0x00000200U
+#define RCC_APB2LPENR_ADC3LPEN 0x00000400U
+#define RCC_APB2LPENR_SDIOLPEN 0x00000800U
+#define RCC_APB2LPENR_SPI1LPEN 0x00001000U
+#define RCC_APB2LPENR_SPI4LPEN 0x00002000U
+#define RCC_APB2LPENR_SYSCFGLPEN 0x00004000U
+#define RCC_APB2LPENR_TIM9LPEN 0x00010000U
+#define RCC_APB2LPENR_TIM10LPEN 0x00020000U
+#define RCC_APB2LPENR_TIM11LPEN 0x00040000U
+#define RCC_APB2LPENR_SPI5LPEN 0x00100000U
+#define RCC_APB2LPENR_SPI6LPEN 0x00200000U
+#define RCC_APB2LPENR_SAI1LPEN 0x00400000U
+#define RCC_APB2LPENR_LTDCLPEN 0x04000000U
+
+/******************** Bit definition for RCC_BDCR register ******************/
+#define RCC_BDCR_LSEON 0x00000001U
+#define RCC_BDCR_LSERDY 0x00000002U
+#define RCC_BDCR_LSEBYP 0x00000004U
+
+#define RCC_BDCR_RTCSEL 0x00000300U
+#define RCC_BDCR_RTCSEL_0 0x00000100U
+#define RCC_BDCR_RTCSEL_1 0x00000200U
+
+#define RCC_BDCR_RTCEN 0x00008000U
+#define RCC_BDCR_BDRST 0x00010000U
+
+/******************** Bit definition for RCC_CSR register *******************/
+#define RCC_CSR_LSION 0x00000001U
+#define RCC_CSR_LSIRDY 0x00000002U
+#define RCC_CSR_RMVF 0x01000000U
+#define RCC_CSR_BORRSTF 0x02000000U
+#define RCC_CSR_PADRSTF 0x04000000U
+#define RCC_CSR_PORRSTF 0x08000000U
+#define RCC_CSR_SFTRSTF 0x10000000U
+#define RCC_CSR_WDGRSTF 0x20000000U
+#define RCC_CSR_WWDGRSTF 0x40000000U
+#define RCC_CSR_LPWRRSTF 0x80000000U
+
+/******************** Bit definition for RCC_SSCGR register *****************/
+#define RCC_SSCGR_MODPER 0x00001FFFU
+#define RCC_SSCGR_INCSTEP 0x0FFFE000U
+#define RCC_SSCGR_SPREADSEL 0x40000000U
+#define RCC_SSCGR_SSCGEN 0x80000000U
+
+/******************** Bit definition for RCC_PLLI2SCFGR register ************/
+#define RCC_PLLI2SCFGR_PLLI2SN 0x00007FC0U
+#define RCC_PLLI2SCFGR_PLLI2SN_0 0x00000040U
+#define RCC_PLLI2SCFGR_PLLI2SN_1 0x00000080U
+#define RCC_PLLI2SCFGR_PLLI2SN_2 0x00000100U
+#define RCC_PLLI2SCFGR_PLLI2SN_3 0x00000200U
+#define RCC_PLLI2SCFGR_PLLI2SN_4 0x00000400U
+#define RCC_PLLI2SCFGR_PLLI2SN_5 0x00000800U
+#define RCC_PLLI2SCFGR_PLLI2SN_6 0x00001000U
+#define RCC_PLLI2SCFGR_PLLI2SN_7 0x00002000U
+#define RCC_PLLI2SCFGR_PLLI2SN_8 0x00004000U
+
+#define RCC_PLLI2SCFGR_PLLI2SQ 0x0F000000U
+#define RCC_PLLI2SCFGR_PLLI2SQ_0 0x01000000U
+#define RCC_PLLI2SCFGR_PLLI2SQ_1 0x02000000U
+#define RCC_PLLI2SCFGR_PLLI2SQ_2 0x04000000U
+#define RCC_PLLI2SCFGR_PLLI2SQ_3 0x08000000U
+
+#define RCC_PLLI2SCFGR_PLLI2SR 0x70000000U
+#define RCC_PLLI2SCFGR_PLLI2SR_0 0x10000000U
+#define RCC_PLLI2SCFGR_PLLI2SR_1 0x20000000U
+#define RCC_PLLI2SCFGR_PLLI2SR_2 0x40000000U
+
+
+/******************** Bit definition for RCC_PLLSAICFGR register ************/
+#define RCC_PLLSAICFGR_PLLSAIN 0x00007FC0U
+#define RCC_PLLSAICFGR_PLLSAIN_0 0x00000040U
+#define RCC_PLLSAICFGR_PLLSAIN_1 0x00000080U
+#define RCC_PLLSAICFGR_PLLSAIN_2 0x00000100U
+#define RCC_PLLSAICFGR_PLLSAIN_3 0x00000200U
+#define RCC_PLLSAICFGR_PLLSAIN_4 0x00000400U
+#define RCC_PLLSAICFGR_PLLSAIN_5 0x00000800U
+#define RCC_PLLSAICFGR_PLLSAIN_6 0x00001000U
+#define RCC_PLLSAICFGR_PLLSAIN_7 0x00002000U
+#define RCC_PLLSAICFGR_PLLSAIN_8 0x00004000U
+
+#define RCC_PLLSAICFGR_PLLSAIQ 0x0F000000U
+#define RCC_PLLSAICFGR_PLLSAIQ_0 0x01000000U
+#define RCC_PLLSAICFGR_PLLSAIQ_1 0x02000000U
+#define RCC_PLLSAICFGR_PLLSAIQ_2 0x04000000U
+#define RCC_PLLSAICFGR_PLLSAIQ_3 0x08000000U
+
+#define RCC_PLLSAICFGR_PLLSAIR 0x70000000U
+#define RCC_PLLSAICFGR_PLLSAIR_0 0x10000000U
+#define RCC_PLLSAICFGR_PLLSAIR_1 0x20000000U
+#define RCC_PLLSAICFGR_PLLSAIR_2 0x40000000U
+
+/******************** Bit definition for RCC_DCKCFGR register ***************/
+#define RCC_DCKCFGR_PLLI2SDIVQ 0x0000001FU
+#define RCC_DCKCFGR_PLLSAIDIVQ 0x00001F00U
+#define RCC_DCKCFGR_PLLSAIDIVR 0x00030000U
+#define RCC_DCKCFGR_SAI1ASRC 0x00300000U
+#define RCC_DCKCFGR_SAI1ASRC_0 0x00100000U
+#define RCC_DCKCFGR_SAI1ASRC_1 0x00200000U
+#define RCC_DCKCFGR_SAI1BSRC 0x00C00000U
+#define RCC_DCKCFGR_SAI1BSRC_0 0x00400000U
+#define RCC_DCKCFGR_SAI1BSRC_1 0x00800000U
+#define RCC_DCKCFGR_TIMPRE 0x01000000U
+
+
+/******************************************************************************/
+/* */
+/* RNG */
+/* */
+/******************************************************************************/
+/******************** Bits definition for RNG_CR register *******************/
+#define RNG_CR_RNGEN 0x00000004U
+#define RNG_CR_IE 0x00000008U
+
+/******************** Bits definition for RNG_SR register *******************/
+#define RNG_SR_DRDY 0x00000001U
+#define RNG_SR_CECS 0x00000002U
+#define RNG_SR_SECS 0x00000004U
+#define RNG_SR_CEIS 0x00000020U
+#define RNG_SR_SEIS 0x00000040U
+
+/******************************************************************************/
+/* */
+/* Real-Time Clock (RTC) */
+/* */
+/******************************************************************************/
+/******************** Bits definition for RTC_TR register *******************/
+#define RTC_TR_PM 0x00400000U
+#define RTC_TR_HT 0x00300000U
+#define RTC_TR_HT_0 0x00100000U
+#define RTC_TR_HT_1 0x00200000U
+#define RTC_TR_HU 0x000F0000U
+#define RTC_TR_HU_0 0x00010000U
+#define RTC_TR_HU_1 0x00020000U
+#define RTC_TR_HU_2 0x00040000U
+#define RTC_TR_HU_3 0x00080000U
+#define RTC_TR_MNT 0x00007000U
+#define RTC_TR_MNT_0 0x00001000U
+#define RTC_TR_MNT_1 0x00002000U
+#define RTC_TR_MNT_2 0x00004000U
+#define RTC_TR_MNU 0x00000F00U
+#define RTC_TR_MNU_0 0x00000100U
+#define RTC_TR_MNU_1 0x00000200U
+#define RTC_TR_MNU_2 0x00000400U
+#define RTC_TR_MNU_3 0x00000800U
+#define RTC_TR_ST 0x00000070U
+#define RTC_TR_ST_0 0x00000010U
+#define RTC_TR_ST_1 0x00000020U
+#define RTC_TR_ST_2 0x00000040U
+#define RTC_TR_SU 0x0000000FU
+#define RTC_TR_SU_0 0x00000001U
+#define RTC_TR_SU_1 0x00000002U
+#define RTC_TR_SU_2 0x00000004U
+#define RTC_TR_SU_3 0x00000008U
+
+/******************** Bits definition for RTC_DR register *******************/
+#define RTC_DR_YT 0x00F00000U
+#define RTC_DR_YT_0 0x00100000U
+#define RTC_DR_YT_1 0x00200000U
+#define RTC_DR_YT_2 0x00400000U
+#define RTC_DR_YT_3 0x00800000U
+#define RTC_DR_YU 0x000F0000U
+#define RTC_DR_YU_0 0x00010000U
+#define RTC_DR_YU_1 0x00020000U
+#define RTC_DR_YU_2 0x00040000U
+#define RTC_DR_YU_3 0x00080000U
+#define RTC_DR_WDU 0x0000E000U
+#define RTC_DR_WDU_0 0x00002000U
+#define RTC_DR_WDU_1 0x00004000U
+#define RTC_DR_WDU_2 0x00008000U
+#define RTC_DR_MT 0x00001000U
+#define RTC_DR_MU 0x00000F00U
+#define RTC_DR_MU_0 0x00000100U
+#define RTC_DR_MU_1 0x00000200U
+#define RTC_DR_MU_2 0x00000400U
+#define RTC_DR_MU_3 0x00000800U
+#define RTC_DR_DT 0x00000030U
+#define RTC_DR_DT_0 0x00000010U
+#define RTC_DR_DT_1 0x00000020U
+#define RTC_DR_DU 0x0000000FU
+#define RTC_DR_DU_0 0x00000001U
+#define RTC_DR_DU_1 0x00000002U
+#define RTC_DR_DU_2 0x00000004U
+#define RTC_DR_DU_3 0x00000008U
+
+/******************** Bits definition for RTC_CR register *******************/
+#define RTC_CR_COE 0x00800000U
+#define RTC_CR_OSEL 0x00600000U
+#define RTC_CR_OSEL_0 0x00200000U
+#define RTC_CR_OSEL_1 0x00400000U
+#define RTC_CR_POL 0x00100000U
+#define RTC_CR_COSEL 0x00080000U
+#define RTC_CR_BCK 0x00040000U
+#define RTC_CR_SUB1H 0x00020000U
+#define RTC_CR_ADD1H 0x00010000U
+#define RTC_CR_TSIE 0x00008000U
+#define RTC_CR_WUTIE 0x00004000U
+#define RTC_CR_ALRBIE 0x00002000U
+#define RTC_CR_ALRAIE 0x00001000U
+#define RTC_CR_TSE 0x00000800U
+#define RTC_CR_WUTE 0x00000400U
+#define RTC_CR_ALRBE 0x00000200U
+#define RTC_CR_ALRAE 0x00000100U
+#define RTC_CR_DCE 0x00000080U
+#define RTC_CR_FMT 0x00000040U
+#define RTC_CR_BYPSHAD 0x00000020U
+#define RTC_CR_REFCKON 0x00000010U
+#define RTC_CR_TSEDGE 0x00000008U
+#define RTC_CR_WUCKSEL 0x00000007U
+#define RTC_CR_WUCKSEL_0 0x00000001U
+#define RTC_CR_WUCKSEL_1 0x00000002U
+#define RTC_CR_WUCKSEL_2 0x00000004U
+
+/******************** Bits definition for RTC_ISR register ******************/
+#define RTC_ISR_RECALPF 0x00010000U
+#define RTC_ISR_TAMP1F 0x00002000U
+#define RTC_ISR_TAMP2F 0x00004000U
+#define RTC_ISR_TSOVF 0x00001000U
+#define RTC_ISR_TSF 0x00000800U
+#define RTC_ISR_WUTF 0x00000400U
+#define RTC_ISR_ALRBF 0x00000200U
+#define RTC_ISR_ALRAF 0x00000100U
+#define RTC_ISR_INIT 0x00000080U
+#define RTC_ISR_INITF 0x00000040U
+#define RTC_ISR_RSF 0x00000020U
+#define RTC_ISR_INITS 0x00000010U
+#define RTC_ISR_SHPF 0x00000008U
+#define RTC_ISR_WUTWF 0x00000004U
+#define RTC_ISR_ALRBWF 0x00000002U
+#define RTC_ISR_ALRAWF 0x00000001U
+
+/******************** Bits definition for RTC_PRER register *****************/
+#define RTC_PRER_PREDIV_A 0x007F0000U
+#define RTC_PRER_PREDIV_S 0x00007FFFU
+
+/******************** Bits definition for RTC_WUTR register *****************/
+#define RTC_WUTR_WUT 0x0000FFFFU
+
+/******************** Bits definition for RTC_CALIBR register ***************/
+#define RTC_CALIBR_DCS 0x00000080U
+#define RTC_CALIBR_DC 0x0000001FU
+
+/******************** Bits definition for RTC_ALRMAR register ***************/
+#define RTC_ALRMAR_MSK4 0x80000000U
+#define RTC_ALRMAR_WDSEL 0x40000000U
+#define RTC_ALRMAR_DT 0x30000000U
+#define RTC_ALRMAR_DT_0 0x10000000U
+#define RTC_ALRMAR_DT_1 0x20000000U
+#define RTC_ALRMAR_DU 0x0F000000U
+#define RTC_ALRMAR_DU_0 0x01000000U
+#define RTC_ALRMAR_DU_1 0x02000000U
+#define RTC_ALRMAR_DU_2 0x04000000U
+#define RTC_ALRMAR_DU_3 0x08000000U
+#define RTC_ALRMAR_MSK3 0x00800000U
+#define RTC_ALRMAR_PM 0x00400000U
+#define RTC_ALRMAR_HT 0x00300000U
+#define RTC_ALRMAR_HT_0 0x00100000U
+#define RTC_ALRMAR_HT_1 0x00200000U
+#define RTC_ALRMAR_HU 0x000F0000U
+#define RTC_ALRMAR_HU_0 0x00010000U
+#define RTC_ALRMAR_HU_1 0x00020000U
+#define RTC_ALRMAR_HU_2 0x00040000U
+#define RTC_ALRMAR_HU_3 0x00080000U
+#define RTC_ALRMAR_MSK2 0x00008000U
+#define RTC_ALRMAR_MNT 0x00007000U
+#define RTC_ALRMAR_MNT_0 0x00001000U
+#define RTC_ALRMAR_MNT_1 0x00002000U
+#define RTC_ALRMAR_MNT_2 0x00004000U
+#define RTC_ALRMAR_MNU 0x00000F00U
+#define RTC_ALRMAR_MNU_0 0x00000100U
+#define RTC_ALRMAR_MNU_1 0x00000200U
+#define RTC_ALRMAR_MNU_2 0x00000400U
+#define RTC_ALRMAR_MNU_3 0x00000800U
+#define RTC_ALRMAR_MSK1 0x00000080U
+#define RTC_ALRMAR_ST 0x00000070U
+#define RTC_ALRMAR_ST_0 0x00000010U
+#define RTC_ALRMAR_ST_1 0x00000020U
+#define RTC_ALRMAR_ST_2 0x00000040U
+#define RTC_ALRMAR_SU 0x0000000FU
+#define RTC_ALRMAR_SU_0 0x00000001U
+#define RTC_ALRMAR_SU_1 0x00000002U
+#define RTC_ALRMAR_SU_2 0x00000004U
+#define RTC_ALRMAR_SU_3 0x00000008U
+
+/******************** Bits definition for RTC_ALRMBR register ***************/
+#define RTC_ALRMBR_MSK4 0x80000000U
+#define RTC_ALRMBR_WDSEL 0x40000000U
+#define RTC_ALRMBR_DT 0x30000000U
+#define RTC_ALRMBR_DT_0 0x10000000U
+#define RTC_ALRMBR_DT_1 0x20000000U
+#define RTC_ALRMBR_DU 0x0F000000U
+#define RTC_ALRMBR_DU_0 0x01000000U
+#define RTC_ALRMBR_DU_1 0x02000000U
+#define RTC_ALRMBR_DU_2 0x04000000U
+#define RTC_ALRMBR_DU_3 0x08000000U
+#define RTC_ALRMBR_MSK3 0x00800000U
+#define RTC_ALRMBR_PM 0x00400000U
+#define RTC_ALRMBR_HT 0x00300000U
+#define RTC_ALRMBR_HT_0 0x00100000U
+#define RTC_ALRMBR_HT_1 0x00200000U
+#define RTC_ALRMBR_HU 0x000F0000U
+#define RTC_ALRMBR_HU_0 0x00010000U
+#define RTC_ALRMBR_HU_1 0x00020000U
+#define RTC_ALRMBR_HU_2 0x00040000U
+#define RTC_ALRMBR_HU_3 0x00080000U
+#define RTC_ALRMBR_MSK2 0x00008000U
+#define RTC_ALRMBR_MNT 0x00007000U
+#define RTC_ALRMBR_MNT_0 0x00001000U
+#define RTC_ALRMBR_MNT_1 0x00002000U
+#define RTC_ALRMBR_MNT_2 0x00004000U
+#define RTC_ALRMBR_MNU 0x00000F00U
+#define RTC_ALRMBR_MNU_0 0x00000100U
+#define RTC_ALRMBR_MNU_1 0x00000200U
+#define RTC_ALRMBR_MNU_2 0x00000400U
+#define RTC_ALRMBR_MNU_3 0x00000800U
+#define RTC_ALRMBR_MSK1 0x00000080U
+#define RTC_ALRMBR_ST 0x00000070U
+#define RTC_ALRMBR_ST_0 0x00000010U
+#define RTC_ALRMBR_ST_1 0x00000020U
+#define RTC_ALRMBR_ST_2 0x00000040U
+#define RTC_ALRMBR_SU 0x0000000FU
+#define RTC_ALRMBR_SU_0 0x00000001U
+#define RTC_ALRMBR_SU_1 0x00000002U
+#define RTC_ALRMBR_SU_2 0x00000004U
+#define RTC_ALRMBR_SU_3 0x00000008U
+
+/******************** Bits definition for RTC_WPR register ******************/
+#define RTC_WPR_KEY 0x000000FFU
+
+/******************** Bits definition for RTC_SSR register ******************/
+#define RTC_SSR_SS 0x0000FFFFU
+
+/******************** Bits definition for RTC_SHIFTR register ***************/
+#define RTC_SHIFTR_SUBFS 0x00007FFFU
+#define RTC_SHIFTR_ADD1S 0x80000000U
+
+/******************** Bits definition for RTC_TSTR register *****************/
+#define RTC_TSTR_PM 0x00400000U
+#define RTC_TSTR_HT 0x00300000U
+#define RTC_TSTR_HT_0 0x00100000U
+#define RTC_TSTR_HT_1 0x00200000U
+#define RTC_TSTR_HU 0x000F0000U
+#define RTC_TSTR_HU_0 0x00010000U
+#define RTC_TSTR_HU_1 0x00020000U
+#define RTC_TSTR_HU_2 0x00040000U
+#define RTC_TSTR_HU_3 0x00080000U
+#define RTC_TSTR_MNT 0x00007000U
+#define RTC_TSTR_MNT_0 0x00001000U
+#define RTC_TSTR_MNT_1 0x00002000U
+#define RTC_TSTR_MNT_2 0x00004000U
+#define RTC_TSTR_MNU 0x00000F00U
+#define RTC_TSTR_MNU_0 0x00000100U
+#define RTC_TSTR_MNU_1 0x00000200U
+#define RTC_TSTR_MNU_2 0x00000400U
+#define RTC_TSTR_MNU_3 0x00000800U
+#define RTC_TSTR_ST 0x00000070U
+#define RTC_TSTR_ST_0 0x00000010U
+#define RTC_TSTR_ST_1 0x00000020U
+#define RTC_TSTR_ST_2 0x00000040U
+#define RTC_TSTR_SU 0x0000000FU
+#define RTC_TSTR_SU_0 0x00000001U
+#define RTC_TSTR_SU_1 0x00000002U
+#define RTC_TSTR_SU_2 0x00000004U
+#define RTC_TSTR_SU_3 0x00000008U
+
+/******************** Bits definition for RTC_TSDR register *****************/
+#define RTC_TSDR_WDU 0x0000E000U
+#define RTC_TSDR_WDU_0 0x00002000U
+#define RTC_TSDR_WDU_1 0x00004000U
+#define RTC_TSDR_WDU_2 0x00008000U
+#define RTC_TSDR_MT 0x00001000U
+#define RTC_TSDR_MU 0x00000F00U
+#define RTC_TSDR_MU_0 0x00000100U
+#define RTC_TSDR_MU_1 0x00000200U
+#define RTC_TSDR_MU_2 0x00000400U
+#define RTC_TSDR_MU_3 0x00000800U
+#define RTC_TSDR_DT 0x00000030U
+#define RTC_TSDR_DT_0 0x00000010U
+#define RTC_TSDR_DT_1 0x00000020U
+#define RTC_TSDR_DU 0x0000000FU
+#define RTC_TSDR_DU_0 0x00000001U
+#define RTC_TSDR_DU_1 0x00000002U
+#define RTC_TSDR_DU_2 0x00000004U
+#define RTC_TSDR_DU_3 0x00000008U
+
+/******************** Bits definition for RTC_TSSSR register ****************/
+#define RTC_TSSSR_SS 0x0000FFFFU
+
+/******************** Bits definition for RTC_CAL register *****************/
+#define RTC_CALR_CALP 0x00008000U
+#define RTC_CALR_CALW8 0x00004000U
+#define RTC_CALR_CALW16 0x00002000U
+#define RTC_CALR_CALM 0x000001FFU
+#define RTC_CALR_CALM_0 0x00000001U
+#define RTC_CALR_CALM_1 0x00000002U
+#define RTC_CALR_CALM_2 0x00000004U
+#define RTC_CALR_CALM_3 0x00000008U
+#define RTC_CALR_CALM_4 0x00000010U
+#define RTC_CALR_CALM_5 0x00000020U
+#define RTC_CALR_CALM_6 0x00000040U
+#define RTC_CALR_CALM_7 0x00000080U
+#define RTC_CALR_CALM_8 0x00000100U
+
+/******************** Bits definition for RTC_TAFCR register ****************/
+#define RTC_TAFCR_ALARMOUTTYPE 0x00040000U
+#define RTC_TAFCR_TSINSEL 0x00020000U
+#define RTC_TAFCR_TAMPINSEL 0x00010000U
+#define RTC_TAFCR_TAMPPUDIS 0x00008000U
+#define RTC_TAFCR_TAMPPRCH 0x00006000U
+#define RTC_TAFCR_TAMPPRCH_0 0x00002000U
+#define RTC_TAFCR_TAMPPRCH_1 0x00004000U
+#define RTC_TAFCR_TAMPFLT 0x00001800U
+#define RTC_TAFCR_TAMPFLT_0 0x00000800U
+#define RTC_TAFCR_TAMPFLT_1 0x00001000U
+#define RTC_TAFCR_TAMPFREQ 0x00000700U
+#define RTC_TAFCR_TAMPFREQ_0 0x00000100U
+#define RTC_TAFCR_TAMPFREQ_1 0x00000200U
+#define RTC_TAFCR_TAMPFREQ_2 0x00000400U
+#define RTC_TAFCR_TAMPTS 0x00000080U
+#define RTC_TAFCR_TAMP2TRG 0x00000010U
+#define RTC_TAFCR_TAMP2E 0x00000008U
+#define RTC_TAFCR_TAMPIE 0x00000004U
+#define RTC_TAFCR_TAMP1TRG 0x00000002U
+#define RTC_TAFCR_TAMP1E 0x00000001U
+
+/******************** Bits definition for RTC_ALRMASSR register *************/
+#define RTC_ALRMASSR_MASKSS 0x0F000000U
+#define RTC_ALRMASSR_MASKSS_0 0x01000000U
+#define RTC_ALRMASSR_MASKSS_1 0x02000000U
+#define RTC_ALRMASSR_MASKSS_2 0x04000000U
+#define RTC_ALRMASSR_MASKSS_3 0x08000000U
+#define RTC_ALRMASSR_SS 0x00007FFFU
+
+/******************** Bits definition for RTC_ALRMBSSR register *************/
+#define RTC_ALRMBSSR_MASKSS 0x0F000000U
+#define RTC_ALRMBSSR_MASKSS_0 0x01000000U
+#define RTC_ALRMBSSR_MASKSS_1 0x02000000U
+#define RTC_ALRMBSSR_MASKSS_2 0x04000000U
+#define RTC_ALRMBSSR_MASKSS_3 0x08000000U
+#define RTC_ALRMBSSR_SS 0x00007FFFU
+
+/******************** Bits definition for RTC_BKP0R register ****************/
+#define RTC_BKP0R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP1R register ****************/
+#define RTC_BKP1R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP2R register ****************/
+#define RTC_BKP2R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP3R register ****************/
+#define RTC_BKP3R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP4R register ****************/
+#define RTC_BKP4R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP5R register ****************/
+#define RTC_BKP5R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP6R register ****************/
+#define RTC_BKP6R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP7R register ****************/
+#define RTC_BKP7R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP8R register ****************/
+#define RTC_BKP8R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP9R register ****************/
+#define RTC_BKP9R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP10R register ***************/
+#define RTC_BKP10R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP11R register ***************/
+#define RTC_BKP11R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP12R register ***************/
+#define RTC_BKP12R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP13R register ***************/
+#define RTC_BKP13R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP14R register ***************/
+#define RTC_BKP14R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP15R register ***************/
+#define RTC_BKP15R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP16R register ***************/
+#define RTC_BKP16R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP17R register ***************/
+#define RTC_BKP17R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP18R register ***************/
+#define RTC_BKP18R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP19R register ***************/
+#define RTC_BKP19R 0xFFFFFFFFU
+
+/******************************************************************************/
+/* */
+/* Serial Audio Interface */
+/* */
+/******************************************************************************/
+/******************** Bit definition for SAI_GCR register *******************/
+#define SAI_GCR_SYNCIN 0x00000003U /*!<SYNCIN[1:0] bits (Synchronization Inputs) */
+#define SAI_GCR_SYNCIN_0 0x00000001U /*!<Bit 0 */
+#define SAI_GCR_SYNCIN_1 0x00000002U /*!<Bit 1 */
+
+#define SAI_GCR_SYNCOUT 0x00000030U /*!<SYNCOUT[1:0] bits (Synchronization Outputs) */
+#define SAI_GCR_SYNCOUT_0 0x00000010U /*!<Bit 0 */
+#define SAI_GCR_SYNCOUT_1 0x00000020U /*!<Bit 1 */
+
+/******************* Bit definition for SAI_xCR1 register *******************/
+#define SAI_xCR1_MODE 0x00000003U /*!<MODE[1:0] bits (Audio Block Mode) */
+#define SAI_xCR1_MODE_0 0x00000001U /*!<Bit 0 */
+#define SAI_xCR1_MODE_1 0x00000002U /*!<Bit 1 */
+
+#define SAI_xCR1_PRTCFG 0x0000000CU /*!<PRTCFG[1:0] bits (Protocol Configuration) */
+#define SAI_xCR1_PRTCFG_0 0x00000004U /*!<Bit 0 */
+#define SAI_xCR1_PRTCFG_1 0x00000008U /*!<Bit 1 */
+
+#define SAI_xCR1_DS 0x000000E0U /*!<DS[1:0] bits (Data Size) */
+#define SAI_xCR1_DS_0 0x00000020U /*!<Bit 0 */
+#define SAI_xCR1_DS_1 0x00000040U /*!<Bit 1 */
+#define SAI_xCR1_DS_2 0x00000080U /*!<Bit 2 */
+
+#define SAI_xCR1_LSBFIRST 0x00000100U /*!<LSB First Configuration */
+#define SAI_xCR1_CKSTR 0x00000200U /*!<ClocK STRobing edge */
+
+#define SAI_xCR1_SYNCEN 0x00000C00U /*!<SYNCEN[1:0](SYNChronization ENable) */
+#define SAI_xCR1_SYNCEN_0 0x00000400U /*!<Bit 0 */
+#define SAI_xCR1_SYNCEN_1 0x00000800U /*!<Bit 1 */
+
+#define SAI_xCR1_MONO 0x00001000U /*!<Mono mode */
+#define SAI_xCR1_OUTDRIV 0x00002000U /*!<Output Drive */
+#define SAI_xCR1_SAIEN 0x00010000U /*!<Audio Block enable */
+#define SAI_xCR1_DMAEN 0x00020000U /*!<DMA enable */
+#define SAI_xCR1_NODIV 0x00080000U /*!<No Divider Configuration */
+
+#define SAI_xCR1_MCKDIV 0x00F00000U /*!<MCKDIV[3:0] (Master ClocK Divider) */
+#define SAI_xCR1_MCKDIV_0 0x00100000U /*!<Bit 0 */
+#define SAI_xCR1_MCKDIV_1 0x00200000U /*!<Bit 1 */
+#define SAI_xCR1_MCKDIV_2 0x00400000U /*!<Bit 2 */
+#define SAI_xCR1_MCKDIV_3 0x00800000U /*!<Bit 3 */
+
+/******************* Bit definition for SAI_xCR2 register *******************/
+#define SAI_xCR2_FTH 0x00000007U /*!<FTH[2:0](Fifo THreshold) */
+#define SAI_xCR2_FTH_0 0x00000001U /*!<Bit 0 */
+#define SAI_xCR2_FTH_1 0x00000002U /*!<Bit 1 */
+#define SAI_xCR2_FTH_2 0x00000004U /*!<Bit 2 */
+
+#define SAI_xCR2_FFLUSH 0x00000008U /*!<Fifo FLUSH */
+#define SAI_xCR2_TRIS 0x00000010U /*!<TRIState Management on data line */
+#define SAI_xCR2_MUTE 0x00000020U /*!<Mute mode */
+#define SAI_xCR2_MUTEVAL 0x00000040U /*!<Muate value */
+
+#define SAI_xCR2_MUTECNT 0x00001F80U /*!<MUTECNT[5:0] (MUTE counter) */
+#define SAI_xCR2_MUTECNT_0 0x00000080U /*!<Bit 0 */
+#define SAI_xCR2_MUTECNT_1 0x00000100U /*!<Bit 1 */
+#define SAI_xCR2_MUTECNT_2 0x00000200U /*!<Bit 2 */
+#define SAI_xCR2_MUTECNT_3 0x00000400U /*!<Bit 3 */
+#define SAI_xCR2_MUTECNT_4 0x00000800U /*!<Bit 4 */
+#define SAI_xCR2_MUTECNT_5 0x00001000U /*!<Bit 5 */
+
+#define SAI_xCR2_CPL 0x00002000U /*!< Complement Bit */
+
+#define SAI_xCR2_COMP 0x0000C000U /*!<COMP[1:0] (Companding mode) */
+#define SAI_xCR2_COMP_0 0x00004000U /*!<Bit 0 */
+#define SAI_xCR2_COMP_1 0x00008000U /*!<Bit 1 */
+
+/****************** Bit definition for SAI_xFRCR register *******************/
+#define SAI_xFRCR_FRL 0x000000FFU /*!<FRL[1:0](Frame length) */
+#define SAI_xFRCR_FRL_0 0x00000001U /*!<Bit 0 */
+#define SAI_xFRCR_FRL_1 0x00000002U /*!<Bit 1 */
+#define SAI_xFRCR_FRL_2 0x00000004U /*!<Bit 2 */
+#define SAI_xFRCR_FRL_3 0x00000008U /*!<Bit 3 */
+#define SAI_xFRCR_FRL_4 0x00000010U /*!<Bit 4 */
+#define SAI_xFRCR_FRL_5 0x00000020U /*!<Bit 5 */
+#define SAI_xFRCR_FRL_6 0x00000040U /*!<Bit 6 */
+#define SAI_xFRCR_FRL_7 0x00000080U /*!<Bit 7 */
+
+#define SAI_xFRCR_FSALL 0x00007F00U /*!<FRL[1:0] (Frame synchronization active level length) */
+#define SAI_xFRCR_FSALL_0 0x00000100U /*!<Bit 0 */
+#define SAI_xFRCR_FSALL_1 0x00000200U /*!<Bit 1 */
+#define SAI_xFRCR_FSALL_2 0x00000400U /*!<Bit 2 */
+#define SAI_xFRCR_FSALL_3 0x00000800U /*!<Bit 3 */
+#define SAI_xFRCR_FSALL_4 0x00001000U /*!<Bit 4 */
+#define SAI_xFRCR_FSALL_5 0x00002000U /*!<Bit 5 */
+#define SAI_xFRCR_FSALL_6 0x00004000U /*!<Bit 6 */
+
+#define SAI_xFRCR_FSDEF 0x00010000U /*!< Frame Synchronization Definition */
+#define SAI_xFRCR_FSPOL 0x00020000U /*!<Frame Synchronization POLarity */
+#define SAI_xFRCR_FSOFF 0x00040000U /*!<Frame Synchronization OFFset */
+/* Legacy defines */
+#define SAI_xFRCR_FSPO SAI_xFRCR_FSPOL
+
+/****************** Bit definition for SAI_xSLOTR register *******************/
+#define SAI_xSLOTR_FBOFF 0x0000001FU /*!<FRL[4:0](First Bit Offset) */
+#define SAI_xSLOTR_FBOFF_0 0x00000001U /*!<Bit 0 */
+#define SAI_xSLOTR_FBOFF_1 0x00000002U /*!<Bit 1 */
+#define SAI_xSLOTR_FBOFF_2 0x00000004U /*!<Bit 2 */
+#define SAI_xSLOTR_FBOFF_3 0x00000008U /*!<Bit 3 */
+#define SAI_xSLOTR_FBOFF_4 0x00000010U /*!<Bit 4 */
+
+#define SAI_xSLOTR_SLOTSZ 0x000000C0U /*!<SLOTSZ[1:0] (Slot size) */
+#define SAI_xSLOTR_SLOTSZ_0 0x00000040U /*!<Bit 0 */
+#define SAI_xSLOTR_SLOTSZ_1 0x00000080U /*!<Bit 1 */
+
+#define SAI_xSLOTR_NBSLOT 0x00000F00U /*!<NBSLOT[3:0] (Number of Slot in audio Frame) */
+#define SAI_xSLOTR_NBSLOT_0 0x00000100U /*!<Bit 0 */
+#define SAI_xSLOTR_NBSLOT_1 0x00000200U /*!<Bit 1 */
+#define SAI_xSLOTR_NBSLOT_2 0x00000400U /*!<Bit 2 */
+#define SAI_xSLOTR_NBSLOT_3 0x00000800U /*!<Bit 3 */
+
+#define SAI_xSLOTR_SLOTEN 0xFFFF0000U /*!<SLOTEN[15:0] (Slot Enable) */
+
+/******************* Bit definition for SAI_xIMR register *******************/
+#define SAI_xIMR_OVRUDRIE 0x00000001U /*!<Overrun underrun interrupt enable */
+#define SAI_xIMR_MUTEDETIE 0x00000002U /*!<Mute detection interrupt enable */
+#define SAI_xIMR_WCKCFGIE 0x00000004U /*!<Wrong Clock Configuration interrupt enable */
+#define SAI_xIMR_FREQIE 0x00000008U /*!<FIFO request interrupt enable */
+#define SAI_xIMR_CNRDYIE 0x00000010U /*!<Codec not ready interrupt enable */
+#define SAI_xIMR_AFSDETIE 0x00000020U /*!<Anticipated frame synchronization detection interrupt enable */
+#define SAI_xIMR_LFSDETIE 0x00000040U /*!<Late frame synchronization detection interrupt enable */
+
+/******************** Bit definition for SAI_xSR register *******************/
+#define SAI_xSR_OVRUDR 0x00000001U /*!<Overrun underrun */
+#define SAI_xSR_MUTEDET 0x00000002U /*!<Mute detection */
+#define SAI_xSR_WCKCFG 0x00000004U /*!<Wrong Clock Configuration */
+#define SAI_xSR_FREQ 0x00000008U /*!<FIFO request */
+#define SAI_xSR_CNRDY 0x00000010U /*!<Codec not ready */
+#define SAI_xSR_AFSDET 0x00000020U /*!<Anticipated frame synchronization detection */
+#define SAI_xSR_LFSDET 0x00000040U /*!<Late frame synchronization detection */
+
+#define SAI_xSR_FLVL 0x00070000U /*!<FLVL[2:0] (FIFO Level Threshold) */
+#define SAI_xSR_FLVL_0 0x00010000U /*!<Bit 0 */
+#define SAI_xSR_FLVL_1 0x00020000U /*!<Bit 1 */
+#define SAI_xSR_FLVL_2 0x00040000U /*!<Bit 2 */
+
+/****************** Bit definition for SAI_xCLRFR register ******************/
+#define SAI_xCLRFR_COVRUDR 0x00000001U /*!<Clear Overrun underrun */
+#define SAI_xCLRFR_CMUTEDET 0x00000002U /*!<Clear Mute detection */
+#define SAI_xCLRFR_CWCKCFG 0x00000004U /*!<Clear Wrong Clock Configuration */
+#define SAI_xCLRFR_CFREQ 0x00000008U /*!<Clear FIFO request */
+#define SAI_xCLRFR_CCNRDY 0x00000010U /*!<Clear Codec not ready */
+#define SAI_xCLRFR_CAFSDET 0x00000020U /*!<Clear Anticipated frame synchronization detection */
+#define SAI_xCLRFR_CLFSDET 0x00000040U /*!<Clear Late frame synchronization detection */
+
+/****************** Bit definition for SAI_xDR register ******************/
+#define SAI_xDR_DATA 0xFFFFFFFFU
+
+
+/******************************************************************************/
+/* */
+/* SD host Interface */
+/* */
+/******************************************************************************/
+/****************** Bit definition for SDIO_POWER register ******************/
+#define SDIO_POWER_PWRCTRL 0x03U /*!<PWRCTRL[1:0] bits (Power supply control bits) */
+#define SDIO_POWER_PWRCTRL_0 0x01U /*!<Bit 0 */
+#define SDIO_POWER_PWRCTRL_1 0x02U /*!<Bit 1 */
+
+/****************** Bit definition for SDIO_CLKCR register ******************/
+#define SDIO_CLKCR_CLKDIV 0x00FFU /*!<Clock divide factor */
+#define SDIO_CLKCR_CLKEN 0x0100U /*!<Clock enable bit */
+#define SDIO_CLKCR_PWRSAV 0x0200U /*!<Power saving configuration bit */
+#define SDIO_CLKCR_BYPASS 0x0400U /*!<Clock divider bypass enable bit */
+
+#define SDIO_CLKCR_WIDBUS 0x1800U /*!<WIDBUS[1:0] bits (Wide bus mode enable bit) */
+#define SDIO_CLKCR_WIDBUS_0 0x0800U /*!<Bit 0 */
+#define SDIO_CLKCR_WIDBUS_1 0x1000U /*!<Bit 1 */
+
+#define SDIO_CLKCR_NEGEDGE 0x2000U /*!<SDIO_CK dephasing selection bit */
+#define SDIO_CLKCR_HWFC_EN 0x4000U /*!<HW Flow Control enable */
+
+/******************* Bit definition for SDIO_ARG register *******************/
+#define SDIO_ARG_CMDARG 0xFFFFFFFFU /*!<Command argument */
+
+/******************* Bit definition for SDIO_CMD register *******************/
+#define SDIO_CMD_CMDINDEX 0x003FU /*!<Command Index */
+
+#define SDIO_CMD_WAITRESP 0x00C0U /*!<WAITRESP[1:0] bits (Wait for response bits) */
+#define SDIO_CMD_WAITRESP_0 0x0040U /*!< Bit 0 */
+#define SDIO_CMD_WAITRESP_1 0x0080U /*!< Bit 1 */
+
+#define SDIO_CMD_WAITINT 0x0100U /*!<CPSM Waits for Interrupt Request */
+#define SDIO_CMD_WAITPEND 0x0200U /*!<CPSM Waits for ends of data transfer (CmdPend internal signal) */
+#define SDIO_CMD_CPSMEN 0x0400U /*!<Command path state machine (CPSM) Enable bit */
+#define SDIO_CMD_SDIOSUSPEND 0x0800U /*!<SD I/O suspend command */
+#define SDIO_CMD_ENCMDCOMPL 0x1000U /*!<Enable CMD completion */
+#define SDIO_CMD_NIEN 0x2000U /*!<Not Interrupt Enable */
+#define SDIO_CMD_CEATACMD 0x4000U /*!<CE-ATA command */
+
+/***************** Bit definition for SDIO_RESPCMD register *****************/
+#define SDIO_RESPCMD_RESPCMD 0x3FU /*!<Response command index */
+
+/****************** Bit definition for SDIO_RESP0 register ******************/
+#define SDIO_RESP0_CARDSTATUS0 0xFFFFFFFFU /*!<Card Status */
+
+/****************** Bit definition for SDIO_RESP1 register ******************/
+#define SDIO_RESP1_CARDSTATUS1 0xFFFFFFFFU /*!<Card Status */
+
+/****************** Bit definition for SDIO_RESP2 register ******************/
+#define SDIO_RESP2_CARDSTATUS2 0xFFFFFFFFU /*!<Card Status */
+
+/****************** Bit definition for SDIO_RESP3 register ******************/
+#define SDIO_RESP3_CARDSTATUS3 0xFFFFFFFFU /*!<Card Status */
+
+/****************** Bit definition for SDIO_RESP4 register ******************/
+#define SDIO_RESP4_CARDSTATUS4 0xFFFFFFFFU /*!<Card Status */
+
+/****************** Bit definition for SDIO_DTIMER register *****************/
+#define SDIO_DTIMER_DATATIME 0xFFFFFFFFU /*!<Data timeout period. */
+
+/****************** Bit definition for SDIO_DLEN register *******************/
+#define SDIO_DLEN_DATALENGTH 0x01FFFFFFU /*!<Data length value */
+
+/****************** Bit definition for SDIO_DCTRL register ******************/
+#define SDIO_DCTRL_DTEN 0x0001U /*!<Data transfer enabled bit */
+#define SDIO_DCTRL_DTDIR 0x0002U /*!<Data transfer direction selection */
+#define SDIO_DCTRL_DTMODE 0x0004U /*!<Data transfer mode selection */
+#define SDIO_DCTRL_DMAEN 0x0008U /*!<DMA enabled bit */
+
+#define SDIO_DCTRL_DBLOCKSIZE 0x00F0U /*!<DBLOCKSIZE[3:0] bits (Data block size) */
+#define SDIO_DCTRL_DBLOCKSIZE_0 0x0010U /*!<Bit 0 */
+#define SDIO_DCTRL_DBLOCKSIZE_1 0x0020U /*!<Bit 1 */
+#define SDIO_DCTRL_DBLOCKSIZE_2 0x0040U /*!<Bit 2 */
+#define SDIO_DCTRL_DBLOCKSIZE_3 0x0080U /*!<Bit 3 */
+
+#define SDIO_DCTRL_RWSTART 0x0100U /*!<Read wait start */
+#define SDIO_DCTRL_RWSTOP 0x0200U /*!<Read wait stop */
+#define SDIO_DCTRL_RWMOD 0x0400U /*!<Read wait mode */
+#define SDIO_DCTRL_SDIOEN 0x0800U /*!<SD I/O enable functions */
+
+/****************** Bit definition for SDIO_DCOUNT register *****************/
+#define SDIO_DCOUNT_DATACOUNT 0x01FFFFFFU /*!<Data count value */
+
+/****************** Bit definition for SDIO_STA register ********************/
+#define SDIO_STA_CCRCFAIL 0x00000001U /*!<Command response received (CRC check failed) */
+#define SDIO_STA_DCRCFAIL 0x00000002U /*!<Data block sent/received (CRC check failed) */
+#define SDIO_STA_CTIMEOUT 0x00000004U /*!<Command response timeout */
+#define SDIO_STA_DTIMEOUT 0x00000008U /*!<Data timeout */
+#define SDIO_STA_TXUNDERR 0x00000010U /*!<Transmit FIFO underrun error */
+#define SDIO_STA_RXOVERR 0x00000020U /*!<Received FIFO overrun error */
+#define SDIO_STA_CMDREND 0x00000040U /*!<Command response received (CRC check passed) */
+#define SDIO_STA_CMDSENT 0x00000080U /*!<Command sent (no response required) */
+#define SDIO_STA_DATAEND 0x00000100U /*!<Data end (data counter, SDIDCOUNT, is zero) */
+#define SDIO_STA_STBITERR 0x00000200U /*!<Start bit not detected on all data signals in wide bus mode */
+#define SDIO_STA_DBCKEND 0x00000400U /*!<Data block sent/received (CRC check passed) */
+#define SDIO_STA_CMDACT 0x00000800U /*!<Command transfer in progress */
+#define SDIO_STA_TXACT 0x00001000U /*!<Data transmit in progress */
+#define SDIO_STA_RXACT 0x00002000U /*!<Data receive in progress */
+#define SDIO_STA_TXFIFOHE 0x00004000U /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
+#define SDIO_STA_RXFIFOHF 0x00008000U /*!<Receive FIFO Half Full: there are at least 8 words in the FIFO */
+#define SDIO_STA_TXFIFOF 0x00010000U /*!<Transmit FIFO full */
+#define SDIO_STA_RXFIFOF 0x00020000U /*!<Receive FIFO full */
+#define SDIO_STA_TXFIFOE 0x00040000U /*!<Transmit FIFO empty */
+#define SDIO_STA_RXFIFOE 0x00080000U /*!<Receive FIFO empty */
+#define SDIO_STA_TXDAVL 0x00100000U /*!<Data available in transmit FIFO */
+#define SDIO_STA_RXDAVL 0x00200000U /*!<Data available in receive FIFO */
+#define SDIO_STA_SDIOIT 0x00400000U /*!<SDIO interrupt received */
+#define SDIO_STA_CEATAEND 0x00800000U /*!<CE-ATA command completion signal received for CMD61 */
+
+/******************* Bit definition for SDIO_ICR register *******************/
+#define SDIO_ICR_CCRCFAILC 0x00000001U /*!<CCRCFAIL flag clear bit */
+#define SDIO_ICR_DCRCFAILC 0x00000002U /*!<DCRCFAIL flag clear bit */
+#define SDIO_ICR_CTIMEOUTC 0x00000004U /*!<CTIMEOUT flag clear bit */
+#define SDIO_ICR_DTIMEOUTC 0x00000008U /*!<DTIMEOUT flag clear bit */
+#define SDIO_ICR_TXUNDERRC 0x00000010U /*!<TXUNDERR flag clear bit */
+#define SDIO_ICR_RXOVERRC 0x00000020U /*!<RXOVERR flag clear bit */
+#define SDIO_ICR_CMDRENDC 0x00000040U /*!<CMDREND flag clear bit */
+#define SDIO_ICR_CMDSENTC 0x00000080U /*!<CMDSENT flag clear bit */
+#define SDIO_ICR_DATAENDC 0x00000100U /*!<DATAEND flag clear bit */
+#define SDIO_ICR_STBITERRC 0x00000200U /*!<STBITERR flag clear bit */
+#define SDIO_ICR_DBCKENDC 0x00000400U /*!<DBCKEND flag clear bit */
+#define SDIO_ICR_SDIOITC 0x00400000U /*!<SDIOIT flag clear bit */
+#define SDIO_ICR_CEATAENDC 0x00800000U /*!<CEATAEND flag clear bit */
+
+/****************** Bit definition for SDIO_MASK register *******************/
+#define SDIO_MASK_CCRCFAILIE 0x00000001U /*!<Command CRC Fail Interrupt Enable */
+#define SDIO_MASK_DCRCFAILIE 0x00000002U /*!<Data CRC Fail Interrupt Enable */
+#define SDIO_MASK_CTIMEOUTIE 0x00000004U /*!<Command TimeOut Interrupt Enable */
+#define SDIO_MASK_DTIMEOUTIE 0x00000008U /*!<Data TimeOut Interrupt Enable */
+#define SDIO_MASK_TXUNDERRIE 0x00000010U /*!<Tx FIFO UnderRun Error Interrupt Enable */
+#define SDIO_MASK_RXOVERRIE 0x00000020U /*!<Rx FIFO OverRun Error Interrupt Enable */
+#define SDIO_MASK_CMDRENDIE 0x00000040U /*!<Command Response Received Interrupt Enable */
+#define SDIO_MASK_CMDSENTIE 0x00000080U /*!<Command Sent Interrupt Enable */
+#define SDIO_MASK_DATAENDIE 0x00000100U /*!<Data End Interrupt Enable */
+#define SDIO_MASK_STBITERRIE 0x00000200U /*!<Start Bit Error Interrupt Enable */
+#define SDIO_MASK_DBCKENDIE 0x00000400U /*!<Data Block End Interrupt Enable */
+#define SDIO_MASK_CMDACTIE 0x00000800U /*!<CCommand Acting Interrupt Enable */
+#define SDIO_MASK_TXACTIE 0x00001000U /*!<Data Transmit Acting Interrupt Enable */
+#define SDIO_MASK_RXACTIE 0x00002000U /*!<Data receive acting interrupt enabled */
+#define SDIO_MASK_TXFIFOHEIE 0x00004000U /*!<Tx FIFO Half Empty interrupt Enable */
+#define SDIO_MASK_RXFIFOHFIE 0x00008000U /*!<Rx FIFO Half Full interrupt Enable */
+#define SDIO_MASK_TXFIFOFIE 0x00010000U /*!<Tx FIFO Full interrupt Enable */
+#define SDIO_MASK_RXFIFOFIE 0x00020000U /*!<Rx FIFO Full interrupt Enable */
+#define SDIO_MASK_TXFIFOEIE 0x00040000U /*!<Tx FIFO Empty interrupt Enable */
+#define SDIO_MASK_RXFIFOEIE 0x00080000U /*!<Rx FIFO Empty interrupt Enable */
+#define SDIO_MASK_TXDAVLIE 0x00100000U /*!<Data available in Tx FIFO interrupt Enable */
+#define SDIO_MASK_RXDAVLIE 0x00200000U /*!<Data available in Rx FIFO interrupt Enable */
+#define SDIO_MASK_SDIOITIE 0x00400000U /*!<SDIO Mode Interrupt Received interrupt Enable */
+#define SDIO_MASK_CEATAENDIE 0x00800000U /*!<CE-ATA command completion signal received Interrupt Enable */
+
+/***************** Bit definition for SDIO_FIFOCNT register *****************/
+#define SDIO_FIFOCNT_FIFOCOUNT 0x00FFFFFFU /*!<Remaining number of words to be written to or read from the FIFO */
+
+/****************** Bit definition for SDIO_FIFO register *******************/
+#define SDIO_FIFO_FIFODATA 0xFFFFFFFFU /*!<Receive and transmit FIFO data */
+
+/******************************************************************************/
+/* */
+/* Serial Peripheral Interface */
+/* */
+/******************************************************************************/
+/******************* Bit definition for SPI_CR1 register ********************/
+#define SPI_CR1_CPHA 0x00000001U /*!<Clock Phase */
+#define SPI_CR1_CPOL 0x00000002U /*!<Clock Polarity */
+#define SPI_CR1_MSTR 0x00000004U /*!<Master Selection */
+
+#define SPI_CR1_BR 0x00000038U /*!<BR[2:0] bits (Baud Rate Control) */
+#define SPI_CR1_BR_0 0x00000008U /*!<Bit 0 */
+#define SPI_CR1_BR_1 0x00000010U /*!<Bit 1 */
+#define SPI_CR1_BR_2 0x00000020U /*!<Bit 2 */
+
+#define SPI_CR1_SPE 0x00000040U /*!<SPI Enable */
+#define SPI_CR1_LSBFIRST 0x00000080U /*!<Frame Format */
+#define SPI_CR1_SSI 0x00000100U /*!<Internal slave select */
+#define SPI_CR1_SSM 0x00000200U /*!<Software slave management */
+#define SPI_CR1_RXONLY 0x00000400U /*!<Receive only */
+#define SPI_CR1_DFF 0x00000800U /*!<Data Frame Format */
+#define SPI_CR1_CRCNEXT 0x00001000U /*!<Transmit CRC next */
+#define SPI_CR1_CRCEN 0x00002000U /*!<Hardware CRC calculation enable */
+#define SPI_CR1_BIDIOE 0x00004000U /*!<Output enable in bidirectional mode */
+#define SPI_CR1_BIDIMODE 0x00008000U /*!<Bidirectional data mode enable */
+
+/******************* Bit definition for SPI_CR2 register ********************/
+#define SPI_CR2_RXDMAEN 0x00000001U /*!<Rx Buffer DMA Enable */
+#define SPI_CR2_TXDMAEN 0x00000002U /*!<Tx Buffer DMA Enable */
+#define SPI_CR2_SSOE 0x00000004U /*!<SS Output Enable */
+#define SPI_CR2_FRF 0x00000010U /*!<Frame Format */
+#define SPI_CR2_ERRIE 0x00000020U /*!<Error Interrupt Enable */
+#define SPI_CR2_RXNEIE 0x00000040U /*!<RX buffer Not Empty Interrupt Enable */
+#define SPI_CR2_TXEIE 0x00000080U /*!<Tx buffer Empty Interrupt Enable */
+
+/******************** Bit definition for SPI_SR register ********************/
+#define SPI_SR_RXNE 0x00000001U /*!<Receive buffer Not Empty */
+#define SPI_SR_TXE 0x00000002U /*!<Transmit buffer Empty */
+#define SPI_SR_CHSIDE 0x00000004U /*!<Channel side */
+#define SPI_SR_UDR 0x00000008U /*!<Underrun flag */
+#define SPI_SR_CRCERR 0x00000010U /*!<CRC Error flag */
+#define SPI_SR_MODF 0x00000020U /*!<Mode fault */
+#define SPI_SR_OVR 0x00000040U /*!<Overrun flag */
+#define SPI_SR_BSY 0x00000080U /*!<Busy flag */
+#define SPI_SR_FRE 0x00000100U /*!<Frame format error flag */
+
+/******************** Bit definition for SPI_DR register ********************/
+#define SPI_DR_DR 0x0000FFFFU /*!<Data Register */
+
+/******************* Bit definition for SPI_CRCPR register ******************/
+#define SPI_CRCPR_CRCPOLY 0x0000FFFFU /*!<CRC polynomial register */
+
+/****************** Bit definition for SPI_RXCRCR register ******************/
+#define SPI_RXCRCR_RXCRC 0x0000FFFFU /*!<Rx CRC Register */
+
+/****************** Bit definition for SPI_TXCRCR register ******************/
+#define SPI_TXCRCR_TXCRC 0x0000FFFFU /*!<Tx CRC Register */
+
+/****************** Bit definition for SPI_I2SCFGR register *****************/
+#define SPI_I2SCFGR_CHLEN 0x00000001U /*!<Channel length (number of bits per audio channel) */
+
+#define SPI_I2SCFGR_DATLEN 0x00000006U /*!<DATLEN[1:0] bits (Data length to be transferred) */
+#define SPI_I2SCFGR_DATLEN_0 0x00000002U /*!<Bit 0 */
+#define SPI_I2SCFGR_DATLEN_1 0x00000004U /*!<Bit 1 */
+
+#define SPI_I2SCFGR_CKPOL 0x00000008U /*!<steady state clock polarity */
+
+#define SPI_I2SCFGR_I2SSTD 0x00000030U /*!<I2SSTD[1:0] bits (I2S standard selection) */
+#define SPI_I2SCFGR_I2SSTD_0 0x00000010U /*!<Bit 0 */
+#define SPI_I2SCFGR_I2SSTD_1 0x00000020U /*!<Bit 1 */
+
+#define SPI_I2SCFGR_PCMSYNC 0x00000080U /*!<PCM frame synchronization */
+
+#define SPI_I2SCFGR_I2SCFG 0x00000300U /*!<I2SCFG[1:0] bits (I2S configuration mode) */
+#define SPI_I2SCFGR_I2SCFG_0 0x00000100U /*!<Bit 0 */
+#define SPI_I2SCFGR_I2SCFG_1 0x00000200U /*!<Bit 1 */
+
+#define SPI_I2SCFGR_I2SE 0x00000400U /*!<I2S Enable */
+#define SPI_I2SCFGR_I2SMOD 0x00000800U /*!<I2S mode selection */
+
+/****************** Bit definition for SPI_I2SPR register *******************/
+#define SPI_I2SPR_I2SDIV 0x000000FFU /*!<I2S Linear prescaler */
+#define SPI_I2SPR_ODD 0x00000100U /*!<Odd factor for the prescaler */
+#define SPI_I2SPR_MCKOE 0x00000200U /*!<Master Clock Output Enable */
+
+/******************************************************************************/
+/* */
+/* SYSCFG */
+/* */
+/******************************************************************************/
+/****************** Bit definition for SYSCFG_MEMRMP register ***************/
+#define SYSCFG_MEMRMP_MEM_MODE 0x00000007U /*!< SYSCFG_Memory Remap Config */
+#define SYSCFG_MEMRMP_MEM_MODE_0 0x00000001U
+#define SYSCFG_MEMRMP_MEM_MODE_1 0x00000002U
+#define SYSCFG_MEMRMP_MEM_MODE_2 0x00000004U
+
+#define SYSCFG_MEMRMP_UFB_MODE 0x00000100U /*!< User Flash Bank mode */
+#define SYSCFG_SWP_FMC 0x00000C00U /*!< FMC memory mapping swap */
+
+/****************** Bit definition for SYSCFG_PMC register ******************/
+#define SYSCFG_PMC_ADCxDC2 0x00070000U /*!< Refer to AN4073 on how to use this bit */
+#define SYSCFG_PMC_ADC1DC2 0x00010000U /*!< Refer to AN4073 on how to use this bit */
+#define SYSCFG_PMC_ADC2DC2 0x00020000U /*!< Refer to AN4073 on how to use this bit */
+#define SYSCFG_PMC_ADC3DC2 0x00040000U /*!< Refer to AN4073 on how to use this bit */
+
+#define SYSCFG_PMC_MII_RMII_SEL 0x00800000U /*!<Ethernet PHY interface selection */
+/* Old MII_RMII_SEL bit definition, maintained for legacy purpose */
+#define SYSCFG_PMC_MII_RMII SYSCFG_PMC_MII_RMII_SEL
+
+/***************** Bit definition for SYSCFG_EXTICR1 register ***************/
+#define SYSCFG_EXTICR1_EXTI0 0x000FU /*!<EXTI 0 configuration */
+#define SYSCFG_EXTICR1_EXTI1 0x00F0U /*!<EXTI 1 configuration */
+#define SYSCFG_EXTICR1_EXTI2 0x0F00U /*!<EXTI 2 configuration */
+#define SYSCFG_EXTICR1_EXTI3 0xF000U /*!<EXTI 3 configuration */
+/**
+ * @brief EXTI0 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI0_PA 0x0000U /*!<PA[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PB 0x0001U /*!<PB[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PC 0x0002U /*!<PC[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PD 0x0003U /*!<PD[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PE 0x0004U /*!<PE[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PF 0x0005U /*!<PF[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PG 0x0006U /*!<PG[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PH 0x0007U /*!<PH[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PI 0x0008U /*!<PI[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PJ 0x0009U /*!<PJ[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PK 0x000AU /*!<PK[0] pin */
+
+/**
+ * @brief EXTI1 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI1_PA 0x0000U /*!<PA[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PB 0x0010U /*!<PB[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PC 0x0020U /*!<PC[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PD 0x0030U /*!<PD[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PE 0x0040U /*!<PE[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PF 0x0050U /*!<PF[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PG 0x0060U /*!<PG[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PH 0x0070U /*!<PH[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PI 0x0080U /*!<PI[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PJ 0x0090U /*!<PJ[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PK 0x00A0U /*!<PK[1] pin */
+
+
+/**
+ * @brief EXTI2 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI2_PA 0x0000U /*!<PA[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PB 0x0100U /*!<PB[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PC 0x0200U /*!<PC[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PD 0x0300U /*!<PD[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PE 0x0400U /*!<PE[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PF 0x0500U /*!<PF[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PG 0x0600U /*!<PG[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PH 0x0700U /*!<PH[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PI 0x0800U /*!<PI[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PJ 0x0900U /*!<PJ[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PK 0x0A00U /*!<PK[2] pin */
+
+
+/**
+ * @brief EXTI3 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI3_PA 0x0000U /*!<PA[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PB 0x1000U /*!<PB[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PC 0x2000U /*!<PC[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PD 0x3000U /*!<PD[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PE 0x4000U /*!<PE[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PF 0x5000U /*!<PF[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PG 0x6000U /*!<PG[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PH 0x7000U /*!<PH[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PI 0x8000U /*!<PI[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PJ 0x9000U /*!<PJ[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PK 0xA000U /*!<PK[3] pin */
+
+
+/***************** Bit definition for SYSCFG_EXTICR2 register ***************/
+#define SYSCFG_EXTICR2_EXTI4 0x000FU /*!<EXTI 4 configuration */
+#define SYSCFG_EXTICR2_EXTI5 0x00F0U /*!<EXTI 5 configuration */
+#define SYSCFG_EXTICR2_EXTI6 0x0F00U /*!<EXTI 6 configuration */
+#define SYSCFG_EXTICR2_EXTI7 0xF000U /*!<EXTI 7 configuration */
+/**
+ * @brief EXTI4 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI4_PA 0x0000U /*!<PA[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PB 0x0001U /*!<PB[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PC 0x0002U /*!<PC[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PD 0x0003U /*!<PD[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PE 0x0004U /*!<PE[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PF 0x0005U /*!<PF[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PG 0x0006U /*!<PG[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PH 0x0007U /*!<PH[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PI 0x0008U /*!<PI[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PJ 0x0009U /*!<PJ[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PK 0x000AU /*!<PK[4] pin */
+
+/**
+ * @brief EXTI5 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI5_PA 0x0000U /*!<PA[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PB 0x0010U /*!<PB[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PC 0x0020U /*!<PC[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PD 0x0030U /*!<PD[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PE 0x0040U /*!<PE[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PF 0x0050U /*!<PF[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PG 0x0060U /*!<PG[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PH 0x0070U /*!<PH[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PI 0x0080U /*!<PI[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PJ 0x0090U /*!<PJ[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PK 0x00A0U /*!<PK[5] pin */
+
+/**
+ * @brief EXTI6 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI6_PA 0x0000U /*!<PA[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PB 0x0100U /*!<PB[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PC 0x0200U /*!<PC[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PD 0x0300U /*!<PD[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PE 0x0400U /*!<PE[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PF 0x0500U /*!<PF[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PG 0x0600U /*!<PG[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PH 0x0700U /*!<PH[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PI 0x0800U /*!<PI[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PJ 0x0900U /*!<PJ[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PK 0x0A00U /*!<PK[6] pin */
+
+
+/**
+ * @brief EXTI7 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI7_PA 0x0000U /*!<PA[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PB 0x1000U /*!<PB[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PC 0x2000U /*!<PC[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PD 0x3000U /*!<PD[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PE 0x4000U /*!<PE[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PF 0x5000U /*!<PF[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PG 0x6000U /*!<PG[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PH 0x7000U /*!<PH[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PI 0x8000U /*!<PI[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PJ 0x9000U /*!<PJ[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PK 0xA000U /*!<PK[7] pin */
+
+/***************** Bit definition for SYSCFG_EXTICR3 register ***************/
+#define SYSCFG_EXTICR3_EXTI8 0x000FU /*!<EXTI 8 configuration */
+#define SYSCFG_EXTICR3_EXTI9 0x00F0U /*!<EXTI 9 configuration */
+#define SYSCFG_EXTICR3_EXTI10 0x0F00U /*!<EXTI 10 configuration */
+#define SYSCFG_EXTICR3_EXTI11 0xF000U /*!<EXTI 11 configuration */
+
+/**
+ * @brief EXTI8 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI8_PA 0x0000U /*!<PA[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PB 0x0001U /*!<PB[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PC 0x0002U /*!<PC[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PD 0x0003U /*!<PD[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PE 0x0004U /*!<PE[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PF 0x0005U /*!<PF[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PG 0x0006U /*!<PG[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PH 0x0007U /*!<PH[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PI 0x0008U /*!<PI[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PJ 0x0009U /*!<PJ[8] pin */
+
+/**
+ * @brief EXTI9 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI9_PA 0x0000U /*!<PA[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PB 0x0010U /*!<PB[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PC 0x0020U /*!<PC[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PD 0x0030U /*!<PD[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PE 0x0040U /*!<PE[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PF 0x0050U /*!<PF[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PG 0x0060U /*!<PG[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PH 0x0070U /*!<PH[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PI 0x0080U /*!<PI[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PJ 0x0090U /*!<PJ[9] pin */
+
+
+/**
+ * @brief EXTI10 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI10_PA 0x0000U /*!<PA[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PB 0x0100U /*!<PB[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PC 0x0200U /*!<PC[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PD 0x0300U /*!<PD[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PE 0x0400U /*!<PE[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PF 0x0500U /*!<PF[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PG 0x0600U /*!<PG[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PH 0x0700U /*!<PH[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PI 0x0800U /*!<PI[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PJ 0x0900U /*!<PJ[10] pin */
+
+
+/**
+ * @brief EXTI11 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI11_PA 0x0000U /*!<PA[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PB 0x1000U /*!<PB[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PC 0x2000U /*!<PC[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PD 0x3000U /*!<PD[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PE 0x4000U /*!<PE[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PF 0x5000U /*!<PF[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PG 0x6000U /*!<PG[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PH 0x7000U /*!<PH[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PI 0x8000U /*!<PI[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PJ 0x9000U /*!<PJ[11] pin */
+
+
+/***************** Bit definition for SYSCFG_EXTICR4 register ***************/
+#define SYSCFG_EXTICR4_EXTI12 0x000FU /*!<EXTI 12 configuration */
+#define SYSCFG_EXTICR4_EXTI13 0x00F0U /*!<EXTI 13 configuration */
+#define SYSCFG_EXTICR4_EXTI14 0x0F00U /*!<EXTI 14 configuration */
+#define SYSCFG_EXTICR4_EXTI15 0xF000U /*!<EXTI 15 configuration */
+/**
+ * @brief EXTI12 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI12_PA 0x0000U /*!<PA[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PB 0x0001U /*!<PB[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PC 0x0002U /*!<PC[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PD 0x0003U /*!<PD[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PE 0x0004U /*!<PE[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PF 0x0005U /*!<PF[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PG 0x0006U /*!<PG[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PH 0x0007U /*!<PH[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PI 0x0008U /*!<PI[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PJ 0x0009U /*!<PJ[12] pin */
+
+
+/**
+ * @brief EXTI13 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI13_PA 0x0000U /*!<PA[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PB 0x0010U /*!<PB[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PC 0x0020U /*!<PC[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PD 0x0030U /*!<PD[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PE 0x0040U /*!<PE[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PF 0x0050U /*!<PF[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PG 0x0060U /*!<PG[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PH 0x0070U /*!<PH[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PI 0x0008U /*!<PI[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PJ 0x0009U /*!<PJ[13] pin */
+
+
+/**
+ * @brief EXTI14 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI14_PA 0x0000U /*!<PA[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PB 0x0100U /*!<PB[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PC 0x0200U /*!<PC[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PD 0x0300U /*!<PD[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PE 0x0400U /*!<PE[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PF 0x0500U /*!<PF[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PG 0x0600U /*!<PG[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PH 0x0700U /*!<PH[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PI 0x0800U /*!<PI[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PJ 0x0900U /*!<PJ[14] pin */
+
+
+/**
+ * @brief EXTI15 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI15_PA 0x0000U /*!<PA[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PB 0x1000U /*!<PB[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PC 0x2000U /*!<PC[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PD 0x3000U /*!<PD[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PE 0x4000U /*!<PE[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PF 0x5000U /*!<PF[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PG 0x6000U /*!<PG[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PH 0x7000U /*!<PH[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PI 0x8000U /*!<PI[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PJ 0x9000U /*!<PJ[15] pin */
+
+/****************** Bit definition for SYSCFG_CMPCR register ****************/
+#define SYSCFG_CMPCR_CMP_PD 0x00000001U /*!<Compensation cell ready flag */
+#define SYSCFG_CMPCR_READY 0x00000100U /*!<Compensation cell power-down */
+
+/******************************************************************************/
+/* */
+/* TIM */
+/* */
+/******************************************************************************/
+/******************* Bit definition for TIM_CR1 register ********************/
+#define TIM_CR1_CEN 0x0001U /*!<Counter enable */
+#define TIM_CR1_UDIS 0x0002U /*!<Update disable */
+#define TIM_CR1_URS 0x0004U /*!<Update request source */
+#define TIM_CR1_OPM 0x0008U /*!<One pulse mode */
+#define TIM_CR1_DIR 0x0010U /*!<Direction */
+
+#define TIM_CR1_CMS 0x0060U /*!<CMS[1:0] bits (Center-aligned mode selection) */
+#define TIM_CR1_CMS_0 0x0020U /*!<Bit 0 */
+#define TIM_CR1_CMS_1 0x0040U /*!<Bit 1 */
+
+#define TIM_CR1_ARPE 0x0080U /*!<Auto-reload preload enable */
+
+#define TIM_CR1_CKD 0x0300U /*!<CKD[1:0] bits (clock division) */
+#define TIM_CR1_CKD_0 0x0100U /*!<Bit 0 */
+#define TIM_CR1_CKD_1 0x0200U /*!<Bit 1 */
+
+/******************* Bit definition for TIM_CR2 register ********************/
+#define TIM_CR2_CCPC 0x0001U /*!<Capture/Compare Preloaded Control */
+#define TIM_CR2_CCUS 0x0004U /*!<Capture/Compare Control Update Selection */
+#define TIM_CR2_CCDS 0x0008U /*!<Capture/Compare DMA Selection */
+
+#define TIM_CR2_MMS 0x0070U /*!<MMS[2:0] bits (Master Mode Selection) */
+#define TIM_CR2_MMS_0 0x0010U /*!<Bit 0 */
+#define TIM_CR2_MMS_1 0x0020U /*!<Bit 1 */
+#define TIM_CR2_MMS_2 0x0040U /*!<Bit 2 */
+
+#define TIM_CR2_TI1S 0x0080U /*!<TI1 Selection */
+#define TIM_CR2_OIS1 0x0100U /*!<Output Idle state 1 (OC1 output) */
+#define TIM_CR2_OIS1N 0x0200U /*!<Output Idle state 1 (OC1N output) */
+#define TIM_CR2_OIS2 0x0400U /*!<Output Idle state 2 (OC2 output) */
+#define TIM_CR2_OIS2N 0x0800U /*!<Output Idle state 2 (OC2N output) */
+#define TIM_CR2_OIS3 0x1000U /*!<Output Idle state 3 (OC3 output) */
+#define TIM_CR2_OIS3N 0x2000U /*!<Output Idle state 3 (OC3N output) */
+#define TIM_CR2_OIS4 0x4000U /*!<Output Idle state 4 (OC4 output) */
+
+/******************* Bit definition for TIM_SMCR register *******************/
+#define TIM_SMCR_SMS 0x0007U /*!<SMS[2:0] bits (Slave mode selection) */
+#define TIM_SMCR_SMS_0 0x0001U /*!<Bit 0 */
+#define TIM_SMCR_SMS_1 0x0002U /*!<Bit 1 */
+#define TIM_SMCR_SMS_2 0x0004U /*!<Bit 2 */
+
+#define TIM_SMCR_TS 0x0070U /*!<TS[2:0] bits (Trigger selection) */
+#define TIM_SMCR_TS_0 0x0010U /*!<Bit 0 */
+#define TIM_SMCR_TS_1 0x0020U /*!<Bit 1 */
+#define TIM_SMCR_TS_2 0x0040U /*!<Bit 2 */
+
+#define TIM_SMCR_MSM 0x0080U /*!<Master/slave mode */
+
+#define TIM_SMCR_ETF 0x0F00U /*!<ETF[3:0] bits (External trigger filter) */
+#define TIM_SMCR_ETF_0 0x0100U /*!<Bit 0 */
+#define TIM_SMCR_ETF_1 0x0200U /*!<Bit 1 */
+#define TIM_SMCR_ETF_2 0x0400U /*!<Bit 2 */
+#define TIM_SMCR_ETF_3 0x0800U /*!<Bit 3 */
+
+#define TIM_SMCR_ETPS 0x3000U /*!<ETPS[1:0] bits (External trigger prescaler) */
+#define TIM_SMCR_ETPS_0 0x1000U /*!<Bit 0 */
+#define TIM_SMCR_ETPS_1 0x2000U /*!<Bit 1 */
+
+#define TIM_SMCR_ECE 0x4000U /*!<External clock enable */
+#define TIM_SMCR_ETP 0x8000U /*!<External trigger polarity */
+
+/******************* Bit definition for TIM_DIER register *******************/
+#define TIM_DIER_UIE 0x0001U /*!<Update interrupt enable */
+#define TIM_DIER_CC1IE 0x0002U /*!<Capture/Compare 1 interrupt enable */
+#define TIM_DIER_CC2IE 0x0004U /*!<Capture/Compare 2 interrupt enable */
+#define TIM_DIER_CC3IE 0x0008U /*!<Capture/Compare 3 interrupt enable */
+#define TIM_DIER_CC4IE 0x0010U /*!<Capture/Compare 4 interrupt enable */
+#define TIM_DIER_COMIE 0x0020U /*!<COM interrupt enable */
+#define TIM_DIER_TIE 0x0040U /*!<Trigger interrupt enable */
+#define TIM_DIER_BIE 0x0080U /*!<Break interrupt enable */
+#define TIM_DIER_UDE 0x0100U /*!<Update DMA request enable */
+#define TIM_DIER_CC1DE 0x0200U /*!<Capture/Compare 1 DMA request enable */
+#define TIM_DIER_CC2DE 0x0400U /*!<Capture/Compare 2 DMA request enable */
+#define TIM_DIER_CC3DE 0x0800U /*!<Capture/Compare 3 DMA request enable */
+#define TIM_DIER_CC4DE 0x1000U /*!<Capture/Compare 4 DMA request enable */
+#define TIM_DIER_COMDE 0x2000U /*!<COM DMA request enable */
+#define TIM_DIER_TDE 0x4000U /*!<Trigger DMA request enable */
+
+/******************** Bit definition for TIM_SR register ********************/
+#define TIM_SR_UIF 0x0001U /*!<Update interrupt Flag */
+#define TIM_SR_CC1IF 0x0002U /*!<Capture/Compare 1 interrupt Flag */
+#define TIM_SR_CC2IF 0x0004U /*!<Capture/Compare 2 interrupt Flag */
+#define TIM_SR_CC3IF 0x0008U /*!<Capture/Compare 3 interrupt Flag */
+#define TIM_SR_CC4IF 0x0010U /*!<Capture/Compare 4 interrupt Flag */
+#define TIM_SR_COMIF 0x0020U /*!<COM interrupt Flag */
+#define TIM_SR_TIF 0x0040U /*!<Trigger interrupt Flag */
+#define TIM_SR_BIF 0x0080U /*!<Break interrupt Flag */
+#define TIM_SR_CC1OF 0x0200U /*!<Capture/Compare 1 Overcapture Flag */
+#define TIM_SR_CC2OF 0x0400U /*!<Capture/Compare 2 Overcapture Flag */
+#define TIM_SR_CC3OF 0x0800U /*!<Capture/Compare 3 Overcapture Flag */
+#define TIM_SR_CC4OF 0x1000U /*!<Capture/Compare 4 Overcapture Flag */
+
+/******************* Bit definition for TIM_EGR register ********************/
+#define TIM_EGR_UG 0x01U /*!<Update Generation */
+#define TIM_EGR_CC1G 0x02U /*!<Capture/Compare 1 Generation */
+#define TIM_EGR_CC2G 0x04U /*!<Capture/Compare 2 Generation */
+#define TIM_EGR_CC3G 0x08U /*!<Capture/Compare 3 Generation */
+#define TIM_EGR_CC4G 0x10U /*!<Capture/Compare 4 Generation */
+#define TIM_EGR_COMG 0x20U /*!<Capture/Compare Control Update Generation */
+#define TIM_EGR_TG 0x40U /*!<Trigger Generation */
+#define TIM_EGR_BG 0x80U /*!<Break Generation */
+
+/****************** Bit definition for TIM_CCMR1 register *******************/
+#define TIM_CCMR1_CC1S 0x0003U /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
+#define TIM_CCMR1_CC1S_0 0x0001U /*!<Bit 0 */
+#define TIM_CCMR1_CC1S_1 0x0002U /*!<Bit 1 */
+
+#define TIM_CCMR1_OC1FE 0x0004U /*!<Output Compare 1 Fast enable */
+#define TIM_CCMR1_OC1PE 0x0008U /*!<Output Compare 1 Preload enable */
+
+#define TIM_CCMR1_OC1M 0x0070U /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
+#define TIM_CCMR1_OC1M_0 0x0010U /*!<Bit 0 */
+#define TIM_CCMR1_OC1M_1 0x0020U /*!<Bit 1 */
+#define TIM_CCMR1_OC1M_2 0x0040U /*!<Bit 2 */
+
+#define TIM_CCMR1_OC1CE 0x0080U /*!<Output Compare 1Clear Enable */
+
+#define TIM_CCMR1_CC2S 0x0300U /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
+#define TIM_CCMR1_CC2S_0 0x0100U /*!<Bit 0 */
+#define TIM_CCMR1_CC2S_1 0x0200U /*!<Bit 1 */
+
+#define TIM_CCMR1_OC2FE 0x0400U /*!<Output Compare 2 Fast enable */
+#define TIM_CCMR1_OC2PE 0x0800U /*!<Output Compare 2 Preload enable */
+
+#define TIM_CCMR1_OC2M 0x7000U /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
+#define TIM_CCMR1_OC2M_0 0x1000U /*!<Bit 0 */
+#define TIM_CCMR1_OC2M_1 0x2000U /*!<Bit 1 */
+#define TIM_CCMR1_OC2M_2 0x4000U /*!<Bit 2 */
+
+#define TIM_CCMR1_OC2CE 0x8000U /*!<Output Compare 2 Clear Enable */
+
+/*----------------------------------------------------------------------------*/
+
+#define TIM_CCMR1_IC1PSC 0x000CU /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
+#define TIM_CCMR1_IC1PSC_0 0x0004U /*!<Bit 0 */
+#define TIM_CCMR1_IC1PSC_1 0x0008U /*!<Bit 1 */
+
+#define TIM_CCMR1_IC1F 0x00F0U /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
+#define TIM_CCMR1_IC1F_0 0x0010U /*!<Bit 0 */
+#define TIM_CCMR1_IC1F_1 0x0020U /*!<Bit 1 */
+#define TIM_CCMR1_IC1F_2 0x0040U /*!<Bit 2 */
+#define TIM_CCMR1_IC1F_3 0x0080U /*!<Bit 3 */
+
+#define TIM_CCMR1_IC2PSC 0x0C00U /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
+#define TIM_CCMR1_IC2PSC_0 0x0400U /*!<Bit 0 */
+#define TIM_CCMR1_IC2PSC_1 0x0800U /*!<Bit 1 */
+
+#define TIM_CCMR1_IC2F 0xF000U /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
+#define TIM_CCMR1_IC2F_0 0x1000U /*!<Bit 0 */
+#define TIM_CCMR1_IC2F_1 0x2000U /*!<Bit 1 */
+#define TIM_CCMR1_IC2F_2 0x4000U /*!<Bit 2 */
+#define TIM_CCMR1_IC2F_3 0x8000U /*!<Bit 3 */
+
+/****************** Bit definition for TIM_CCMR2 register *******************/
+#define TIM_CCMR2_CC3S 0x0003U /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
+#define TIM_CCMR2_CC3S_0 0x0001U /*!<Bit 0 */
+#define TIM_CCMR2_CC3S_1 0x0002U /*!<Bit 1 */
+
+#define TIM_CCMR2_OC3FE 0x0004U /*!<Output Compare 3 Fast enable */
+#define TIM_CCMR2_OC3PE 0x0008U /*!<Output Compare 3 Preload enable */
+
+#define TIM_CCMR2_OC3M 0x0070U /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
+#define TIM_CCMR2_OC3M_0 0x0010U /*!<Bit 0 */
+#define TIM_CCMR2_OC3M_1 0x0020U /*!<Bit 1 */
+#define TIM_CCMR2_OC3M_2 0x0040U /*!<Bit 2 */
+
+#define TIM_CCMR2_OC3CE 0x0080U /*!<Output Compare 3 Clear Enable */
+
+#define TIM_CCMR2_CC4S 0x0300U /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
+#define TIM_CCMR2_CC4S_0 0x0100U /*!<Bit 0 */
+#define TIM_CCMR2_CC4S_1 0x0200U /*!<Bit 1 */
+
+#define TIM_CCMR2_OC4FE 0x0400U /*!<Output Compare 4 Fast enable */
+#define TIM_CCMR2_OC4PE 0x0800U /*!<Output Compare 4 Preload enable */
+
+#define TIM_CCMR2_OC4M 0x7000U /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
+#define TIM_CCMR2_OC4M_0 0x1000U /*!<Bit 0 */
+#define TIM_CCMR2_OC4M_1 0x2000U /*!<Bit 1 */
+#define TIM_CCMR2_OC4M_2 0x4000U /*!<Bit 2 */
+
+#define TIM_CCMR2_OC4CE 0x8000U /*!<Output Compare 4 Clear Enable */
+
+/*----------------------------------------------------------------------------*/
+
+#define TIM_CCMR2_IC3PSC 0x000CU /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
+#define TIM_CCMR2_IC3PSC_0 0x0004U /*!<Bit 0 */
+#define TIM_CCMR2_IC3PSC_1 0x0008U /*!<Bit 1 */
+
+#define TIM_CCMR2_IC3F 0x00F0U /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
+#define TIM_CCMR2_IC3F_0 0x0010U /*!<Bit 0 */
+#define TIM_CCMR2_IC3F_1 0x0020U /*!<Bit 1 */
+#define TIM_CCMR2_IC3F_2 0x0040U /*!<Bit 2 */
+#define TIM_CCMR2_IC3F_3 0x0080U /*!<Bit 3 */
+
+#define TIM_CCMR2_IC4PSC 0x0C00U /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
+#define TIM_CCMR2_IC4PSC_0 0x0400U /*!<Bit 0 */
+#define TIM_CCMR2_IC4PSC_1 0x0800U /*!<Bit 1 */
+
+#define TIM_CCMR2_IC4F 0xF000U /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
+#define TIM_CCMR2_IC4F_0 0x1000U /*!<Bit 0 */
+#define TIM_CCMR2_IC4F_1 0x2000U /*!<Bit 1 */
+#define TIM_CCMR2_IC4F_2 0x4000U /*!<Bit 2 */
+#define TIM_CCMR2_IC4F_3 0x8000U /*!<Bit 3 */
+
+/******************* Bit definition for TIM_CCER register *******************/
+#define TIM_CCER_CC1E 0x0001U /*!<Capture/Compare 1 output enable */
+#define TIM_CCER_CC1P 0x0002U /*!<Capture/Compare 1 output Polarity */
+#define TIM_CCER_CC1NE 0x0004U /*!<Capture/Compare 1 Complementary output enable */
+#define TIM_CCER_CC1NP 0x0008U /*!<Capture/Compare 1 Complementary output Polarity */
+#define TIM_CCER_CC2E 0x0010U /*!<Capture/Compare 2 output enable */
+#define TIM_CCER_CC2P 0x0020U /*!<Capture/Compare 2 output Polarity */
+#define TIM_CCER_CC2NE 0x0040U /*!<Capture/Compare 2 Complementary output enable */
+#define TIM_CCER_CC2NP 0x0080U /*!<Capture/Compare 2 Complementary output Polarity */
+#define TIM_CCER_CC3E 0x0100U /*!<Capture/Compare 3 output enable */
+#define TIM_CCER_CC3P 0x0200U /*!<Capture/Compare 3 output Polarity */
+#define TIM_CCER_CC3NE 0x0400U /*!<Capture/Compare 3 Complementary output enable */
+#define TIM_CCER_CC3NP 0x0800U /*!<Capture/Compare 3 Complementary output Polarity */
+#define TIM_CCER_CC4E 0x1000U /*!<Capture/Compare 4 output enable */
+#define TIM_CCER_CC4P 0x2000U /*!<Capture/Compare 4 output Polarity */
+#define TIM_CCER_CC4NP 0x8000U /*!<Capture/Compare 4 Complementary output Polarity */
+
+/******************* Bit definition for TIM_CNT register ********************/
+#define TIM_CNT_CNT 0xFFFFU /*!<Counter Value */
+
+/******************* Bit definition for TIM_PSC register ********************/
+#define TIM_PSC_PSC 0xFFFFU /*!<Prescaler Value */
+
+/******************* Bit definition for TIM_ARR register ********************/
+#define TIM_ARR_ARR 0xFFFFU /*!<actual auto-reload Value */
+
+/******************* Bit definition for TIM_RCR register ********************/
+#define TIM_RCR_REP 0xFFU /*!<Repetition Counter Value */
+
+/******************* Bit definition for TIM_CCR1 register *******************/
+#define TIM_CCR1_CCR1 0xFFFFU /*!<Capture/Compare 1 Value */
+
+/******************* Bit definition for TIM_CCR2 register *******************/
+#define TIM_CCR2_CCR2 0xFFFFU /*!<Capture/Compare 2 Value */
+
+/******************* Bit definition for TIM_CCR3 register *******************/
+#define TIM_CCR3_CCR3 0xFFFFU /*!<Capture/Compare 3 Value */
+
+/******************* Bit definition for TIM_CCR4 register *******************/
+#define TIM_CCR4_CCR4 0xFFFFU /*!<Capture/Compare 4 Value */
+
+/******************* Bit definition for TIM_BDTR register *******************/
+#define TIM_BDTR_DTG 0x00FFU /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
+#define TIM_BDTR_DTG_0 0x0001U /*!<Bit 0 */
+#define TIM_BDTR_DTG_1 0x0002U /*!<Bit 1 */
+#define TIM_BDTR_DTG_2 0x0004U /*!<Bit 2 */
+#define TIM_BDTR_DTG_3 0x0008U /*!<Bit 3 */
+#define TIM_BDTR_DTG_4 0x0010U /*!<Bit 4 */
+#define TIM_BDTR_DTG_5 0x0020U /*!<Bit 5 */
+#define TIM_BDTR_DTG_6 0x0040U /*!<Bit 6 */
+#define TIM_BDTR_DTG_7 0x0080U /*!<Bit 7 */
+
+#define TIM_BDTR_LOCK 0x0300U /*!<LOCK[1:0] bits (Lock Configuration) */
+#define TIM_BDTR_LOCK_0 0x0100U /*!<Bit 0 */
+#define TIM_BDTR_LOCK_1 0x0200U /*!<Bit 1 */
+
+#define TIM_BDTR_OSSI 0x0400U /*!<Off-State Selection for Idle mode */
+#define TIM_BDTR_OSSR 0x0800U /*!<Off-State Selection for Run mode */
+#define TIM_BDTR_BKE 0x1000U /*!<Break enable */
+#define TIM_BDTR_BKP 0x2000U /*!<Break Polarity */
+#define TIM_BDTR_AOE 0x4000U /*!<Automatic Output enable */
+#define TIM_BDTR_MOE 0x8000U /*!<Main Output enable */
+
+/******************* Bit definition for TIM_DCR register ********************/
+#define TIM_DCR_DBA 0x001FU /*!<DBA[4:0] bits (DMA Base Address) */
+#define TIM_DCR_DBA_0 0x0001U /*!<Bit 0 */
+#define TIM_DCR_DBA_1 0x0002U /*!<Bit 1 */
+#define TIM_DCR_DBA_2 0x0004U /*!<Bit 2 */
+#define TIM_DCR_DBA_3 0x0008U /*!<Bit 3 */
+#define TIM_DCR_DBA_4 0x0010U /*!<Bit 4 */
+
+#define TIM_DCR_DBL 0x1F00U /*!<DBL[4:0] bits (DMA Burst Length) */
+#define TIM_DCR_DBL_0 0x0100U /*!<Bit 0 */
+#define TIM_DCR_DBL_1 0x0200U /*!<Bit 1 */
+#define TIM_DCR_DBL_2 0x0400U /*!<Bit 2 */
+#define TIM_DCR_DBL_3 0x0800U /*!<Bit 3 */
+#define TIM_DCR_DBL_4 0x1000U /*!<Bit 4 */
+
+/******************* Bit definition for TIM_DMAR register *******************/
+#define TIM_DMAR_DMAB 0xFFFFU /*!<DMA register for burst accesses */
+
+/******************* Bit definition for TIM_OR register *********************/
+#define TIM_OR_TI4_RMP 0x00C0U /*!<TI4_RMP[1:0] bits (TIM5 Input 4 remap) */
+#define TIM_OR_TI4_RMP_0 0x0040U /*!<Bit 0 */
+#define TIM_OR_TI4_RMP_1 0x0080U /*!<Bit 1 */
+#define TIM_OR_ITR1_RMP 0x0C00U /*!<ITR1_RMP[1:0] bits (TIM2 Internal trigger 1 remap) */
+#define TIM_OR_ITR1_RMP_0 0x0400U /*!<Bit 0 */
+#define TIM_OR_ITR1_RMP_1 0x0800U /*!<Bit 1 */
+
+
+/******************************************************************************/
+/* */
+/* Universal Synchronous Asynchronous Receiver Transmitter */
+/* */
+/******************************************************************************/
+/******************* Bit definition for USART_SR register *******************/
+#define USART_SR_PE 0x0001U /*!<Parity Error */
+#define USART_SR_FE 0x0002U /*!<Framing Error */
+#define USART_SR_NE 0x0004U /*!<Noise Error Flag */
+#define USART_SR_ORE 0x0008U /*!<OverRun Error */
+#define USART_SR_IDLE 0x0010U /*!<IDLE line detected */
+#define USART_SR_RXNE 0x0020U /*!<Read Data Register Not Empty */
+#define USART_SR_TC 0x0040U /*!<Transmission Complete */
+#define USART_SR_TXE 0x0080U /*!<Transmit Data Register Empty */
+#define USART_SR_LBD 0x0100U /*!<LIN Break Detection Flag */
+#define USART_SR_CTS 0x0200U /*!<CTS Flag */
+
+/******************* Bit definition for USART_DR register *******************/
+#define USART_DR_DR 0x01FFU /*!<Data value */
+
+/****************** Bit definition for USART_BRR register *******************/
+#define USART_BRR_DIV_Fraction 0x000FU /*!<Fraction of USARTDIV */
+#define USART_BRR_DIV_Mantissa 0xFFF0U /*!<Mantissa of USARTDIV */
+
+/****************** Bit definition for USART_CR1 register *******************/
+#define USART_CR1_SBK 0x0001U /*!<Send Break */
+#define USART_CR1_RWU 0x0002U /*!<Receiver wakeup */
+#define USART_CR1_RE 0x0004U /*!<Receiver Enable */
+#define USART_CR1_TE 0x0008U /*!<Transmitter Enable */
+#define USART_CR1_IDLEIE 0x0010U /*!<IDLE Interrupt Enable */
+#define USART_CR1_RXNEIE 0x0020U /*!<RXNE Interrupt Enable */
+#define USART_CR1_TCIE 0x0040U /*!<Transmission Complete Interrupt Enable */
+#define USART_CR1_TXEIE 0x0080U /*!<PE Interrupt Enable */
+#define USART_CR1_PEIE 0x0100U /*!<PE Interrupt Enable */
+#define USART_CR1_PS 0x0200U /*!<Parity Selection */
+#define USART_CR1_PCE 0x0400U /*!<Parity Control Enable */
+#define USART_CR1_WAKE 0x0800U /*!<Wakeup method */
+#define USART_CR1_M 0x1000U /*!<Word length */
+#define USART_CR1_UE 0x2000U /*!<USART Enable */
+#define USART_CR1_OVER8 0x8000U /*!<USART Oversampling by 8 enable */
+
+/****************** Bit definition for USART_CR2 register *******************/
+#define USART_CR2_ADD 0x000FU /*!<Address of the USART node */
+#define USART_CR2_LBDL 0x0020U /*!<LIN Break Detection Length */
+#define USART_CR2_LBDIE 0x0040U /*!<LIN Break Detection Interrupt Enable */
+#define USART_CR2_LBCL 0x0100U /*!<Last Bit Clock pulse */
+#define USART_CR2_CPHA 0x0200U /*!<Clock Phase */
+#define USART_CR2_CPOL 0x0400U /*!<Clock Polarity */
+#define USART_CR2_CLKEN 0x0800U /*!<Clock Enable */
+
+#define USART_CR2_STOP 0x3000U /*!<STOP[1:0] bits (STOP bits) */
+#define USART_CR2_STOP_0 0x1000U /*!<Bit 0 */
+#define USART_CR2_STOP_1 0x2000U /*!<Bit 1 */
+
+#define USART_CR2_LINEN 0x4000U /*!<LIN mode enable */
+
+/****************** Bit definition for USART_CR3 register *******************/
+#define USART_CR3_EIE 0x0001U /*!<Error Interrupt Enable */
+#define USART_CR3_IREN 0x0002U /*!<IrDA mode Enable */
+#define USART_CR3_IRLP 0x0004U /*!<IrDA Low-Power */
+#define USART_CR3_HDSEL 0x0008U /*!<Half-Duplex Selection */
+#define USART_CR3_NACK 0x0010U /*!<Smartcard NACK enable */
+#define USART_CR3_SCEN 0x0020U /*!<Smartcard mode enable */
+#define USART_CR3_DMAR 0x0040U /*!<DMA Enable Receiver */
+#define USART_CR3_DMAT 0x0080U /*!<DMA Enable Transmitter */
+#define USART_CR3_RTSE 0x0100U /*!<RTS Enable */
+#define USART_CR3_CTSE 0x0200U /*!<CTS Enable */
+#define USART_CR3_CTSIE 0x0400U /*!<CTS Interrupt Enable */
+#define USART_CR3_ONEBIT 0x0800U /*!<USART One bit method enable */
+
+/****************** Bit definition for USART_GTPR register ******************/
+#define USART_GTPR_PSC 0x00FFU /*!<PSC[7:0] bits (Prescaler value) */
+#define USART_GTPR_PSC_0 0x0001U /*!<Bit 0 */
+#define USART_GTPR_PSC_1 0x0002U /*!<Bit 1 */
+#define USART_GTPR_PSC_2 0x0004U /*!<Bit 2 */
+#define USART_GTPR_PSC_3 0x0008U /*!<Bit 3 */
+#define USART_GTPR_PSC_4 0x0010U /*!<Bit 4 */
+#define USART_GTPR_PSC_5 0x0020U /*!<Bit 5 */
+#define USART_GTPR_PSC_6 0x0040U /*!<Bit 6 */
+#define USART_GTPR_PSC_7 0x0080U /*!<Bit 7 */
+
+#define USART_GTPR_GT 0xFF00U /*!<Guard time value */
+
+/******************************************************************************/
+/* */
+/* Window WATCHDOG */
+/* */
+/******************************************************************************/
+/******************* Bit definition for WWDG_CR register ********************/
+#define WWDG_CR_T 0x7FU /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
+#define WWDG_CR_T_0 0x01U /*!<Bit 0 */
+#define WWDG_CR_T_1 0x02U /*!<Bit 1 */
+#define WWDG_CR_T_2 0x04U /*!<Bit 2 */
+#define WWDG_CR_T_3 0x08U /*!<Bit 3 */
+#define WWDG_CR_T_4 0x10U /*!<Bit 4 */
+#define WWDG_CR_T_5 0x20U /*!<Bit 5 */
+#define WWDG_CR_T_6 0x40U /*!<Bit 6 */
+/* Legacy defines */
+#define WWDG_CR_T0 WWDG_CR_T_0
+#define WWDG_CR_T1 WWDG_CR_T_1
+#define WWDG_CR_T2 WWDG_CR_T_2
+#define WWDG_CR_T3 WWDG_CR_T_3
+#define WWDG_CR_T4 WWDG_CR_T_4
+#define WWDG_CR_T5 WWDG_CR_T_5
+#define WWDG_CR_T6 WWDG_CR_T_6
+
+#define WWDG_CR_WDGA 0x80U /*!<Activation bit */
+
+/******************* Bit definition for WWDG_CFR register *******************/
+#define WWDG_CFR_W 0x007FU /*!<W[6:0] bits (7-bit window value) */
+#define WWDG_CFR_W_0 0x0001U /*!<Bit 0 */
+#define WWDG_CFR_W_1 0x0002U /*!<Bit 1 */
+#define WWDG_CFR_W_2 0x0004U /*!<Bit 2 */
+#define WWDG_CFR_W_3 0x0008U /*!<Bit 3 */
+#define WWDG_CFR_W_4 0x0010U /*!<Bit 4 */
+#define WWDG_CFR_W_5 0x0020U /*!<Bit 5 */
+#define WWDG_CFR_W_6 0x0040U /*!<Bit 6 */
+/* Legacy defines */
+#define WWDG_CFR_W0 WWDG_CFR_W_0
+#define WWDG_CFR_W1 WWDG_CFR_W_1
+#define WWDG_CFR_W2 WWDG_CFR_W_2
+#define WWDG_CFR_W3 WWDG_CFR_W_3
+#define WWDG_CFR_W4 WWDG_CFR_W_4
+#define WWDG_CFR_W5 WWDG_CFR_W_5
+#define WWDG_CFR_W6 WWDG_CFR_W_6
+
+#define WWDG_CFR_WDGTB 0x0180U /*!<WDGTB[1:0] bits (Timer Base) */
+#define WWDG_CFR_WDGTB_0 0x0080U /*!<Bit 0 */
+#define WWDG_CFR_WDGTB_1 0x0100U /*!<Bit 1 */
+/* Legacy defines */
+#define WWDG_CFR_WDGTB0 WWDG_CFR_WDGTB_0
+#define WWDG_CFR_WDGTB1 WWDG_CFR_WDGTB_1
+
+#define WWDG_CFR_EWI 0x0200U /*!<Early Wakeup Interrupt */
+
+/******************* Bit definition for WWDG_SR register ********************/
+#define WWDG_SR_EWIF 0x01U /*!<Early Wakeup Interrupt Flag */
+
+
+/******************************************************************************/
+/* */
+/* DBG */
+/* */
+/******************************************************************************/
+/******************** Bit definition for DBGMCU_IDCODE register *************/
+#define DBGMCU_IDCODE_DEV_ID 0x00000FFFU
+#define DBGMCU_IDCODE_REV_ID 0xFFFF0000U
+
+/******************** Bit definition for DBGMCU_CR register *****************/
+#define DBGMCU_CR_DBG_SLEEP 0x00000001U
+#define DBGMCU_CR_DBG_STOP 0x00000002U
+#define DBGMCU_CR_DBG_STANDBY 0x00000004U
+#define DBGMCU_CR_TRACE_IOEN 0x00000020U
+
+#define DBGMCU_CR_TRACE_MODE 0x000000C0U
+#define DBGMCU_CR_TRACE_MODE_0 0x00000040U/*!<Bit 0 */
+#define DBGMCU_CR_TRACE_MODE_1 0x00000080U/*!<Bit 1 */
+
+/******************** Bit definition for DBGMCU_APB1_FZ register ************/
+#define DBGMCU_APB1_FZ_DBG_TIM2_STOP 0x00000001U
+#define DBGMCU_APB1_FZ_DBG_TIM3_STOP 0x00000002U
+#define DBGMCU_APB1_FZ_DBG_TIM4_STOP 0x00000004U
+#define DBGMCU_APB1_FZ_DBG_TIM5_STOP 0x00000008U
+#define DBGMCU_APB1_FZ_DBG_TIM6_STOP 0x00000010U
+#define DBGMCU_APB1_FZ_DBG_TIM7_STOP 0x00000020U
+#define DBGMCU_APB1_FZ_DBG_TIM12_STOP 0x00000040U
+#define DBGMCU_APB1_FZ_DBG_TIM13_STOP 0x00000080U
+#define DBGMCU_APB1_FZ_DBG_TIM14_STOP 0x00000100U
+#define DBGMCU_APB1_FZ_DBG_RTC_STOP 0x00000400U
+#define DBGMCU_APB1_FZ_DBG_WWDG_STOP 0x00000800U
+#define DBGMCU_APB1_FZ_DBG_IWDG_STOP 0x00001000U
+#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT 0x00200000U
+#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT 0x00400000U
+#define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT 0x00800000U
+#define DBGMCU_APB1_FZ_DBG_CAN1_STOP 0x02000000U
+#define DBGMCU_APB1_FZ_DBG_CAN2_STOP 0x04000000U
+/* Old IWDGSTOP bit definition, maintained for legacy purpose */
+#define DBGMCU_APB1_FZ_DBG_IWDEG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP
+
+/******************** Bit definition for DBGMCU_APB2_FZ register ************/
+#define DBGMCU_APB2_FZ_DBG_TIM1_STOP 0x00000001U
+#define DBGMCU_APB2_FZ_DBG_TIM8_STOP 0x00000002U
+#define DBGMCU_APB2_FZ_DBG_TIM9_STOP 0x00010000U
+#define DBGMCU_APB2_FZ_DBG_TIM10_STOP 0x00020000U
+#define DBGMCU_APB2_FZ_DBG_TIM11_STOP 0x00040000U
+
+/******************************************************************************/
+/* */
+/* Ethernet MAC Registers bits definitions */
+/* */
+/******************************************************************************/
+/* Bit definition for Ethernet MAC Control Register register */
+#define ETH_MACCR_WD 0x00800000U /* Watchdog disable */
+#define ETH_MACCR_JD 0x00400000U /* Jabber disable */
+#define ETH_MACCR_IFG 0x000E0000U /* Inter-frame gap */
+#define ETH_MACCR_IFG_96Bit 0x00000000U /* Minimum IFG between frames during transmission is 96Bit */
+ #define ETH_MACCR_IFG_88Bit 0x00020000U /* Minimum IFG between frames during transmission is 88Bit */
+ #define ETH_MACCR_IFG_80Bit 0x00040000U /* Minimum IFG between frames during transmission is 80Bit */
+ #define ETH_MACCR_IFG_72Bit 0x00060000U /* Minimum IFG between frames during transmission is 72Bit */
+ #define ETH_MACCR_IFG_64Bit 0x00080000U /* Minimum IFG between frames during transmission is 64Bit */
+ #define ETH_MACCR_IFG_56Bit 0x000A0000U /* Minimum IFG between frames during transmission is 56Bit */
+ #define ETH_MACCR_IFG_48Bit 0x000C0000U /* Minimum IFG between frames during transmission is 48Bit */
+ #define ETH_MACCR_IFG_40Bit 0x000E0000U /* Minimum IFG between frames during transmission is 40Bit */
+#define ETH_MACCR_CSD 0x00010000U /* Carrier sense disable (during transmission) */
+#define ETH_MACCR_FES 0x00004000U /* Fast ethernet speed */
+#define ETH_MACCR_ROD 0x00002000U /* Receive own disable */
+#define ETH_MACCR_LM 0x00001000U /* loopback mode */
+#define ETH_MACCR_DM 0x00000800U /* Duplex mode */
+#define ETH_MACCR_IPCO 0x00000400U /* IP Checksum offload */
+#define ETH_MACCR_RD 0x00000200U /* Retry disable */
+#define ETH_MACCR_APCS 0x00000080U /* Automatic Pad/CRC stripping */
+#define ETH_MACCR_BL 0x00000060U /* Back-off limit: random integer number (r) of slot time delays before rescheduling
+ a transmission attempt during retries after a collision: 0 =< r <2^k */
+ #define ETH_MACCR_BL_10 0x00000000U /* k = min (n, 10) */
+ #define ETH_MACCR_BL_8 0x00000020U /* k = min (n, 8) */
+ #define ETH_MACCR_BL_4 0x00000040U /* k = min (n, 4) */
+ #define ETH_MACCR_BL_1 0x00000060U /* k = min (n, 1) */
+#define ETH_MACCR_DC 0x00000010U /* Defferal check */
+#define ETH_MACCR_TE 0x00000008U /* Transmitter enable */
+#define ETH_MACCR_RE 0x00000004U /* Receiver enable */
+
+/* Bit definition for Ethernet MAC Frame Filter Register */
+#define ETH_MACFFR_RA 0x80000000U /* Receive all */
+#define ETH_MACFFR_HPF 0x00000400U /* Hash or perfect filter */
+#define ETH_MACFFR_SAF 0x00000200U /* Source address filter enable */
+#define ETH_MACFFR_SAIF 0x00000100U /* SA inverse filtering */
+#define ETH_MACFFR_PCF 0x000000C0U /* Pass control frames: 3 cases */
+ #define ETH_MACFFR_PCF_BlockAll 0x00000040U /* MAC filters all control frames from reaching the application */
+ #define ETH_MACFFR_PCF_ForwardAll 0x00000080U /* MAC forwards all control frames to application even if they fail the Address Filter */
+ #define ETH_MACFFR_PCF_ForwardPassedAddrFilter 0x000000C0U /* MAC forwards control frames that pass the Address Filter. */
+#define ETH_MACFFR_BFD 0x00000020U /* Broadcast frame disable */
+#define ETH_MACFFR_PAM 0x00000010U /* Pass all mutlicast */
+#define ETH_MACFFR_DAIF 0x00000008U /* DA Inverse filtering */
+#define ETH_MACFFR_HM 0x00000004U /* Hash multicast */
+#define ETH_MACFFR_HU 0x00000002U /* Hash unicast */
+#define ETH_MACFFR_PM 0x00000001U /* Promiscuous mode */
+
+/* Bit definition for Ethernet MAC Hash Table High Register */
+#define ETH_MACHTHR_HTH 0xFFFFFFFFU /* Hash table high */
+
+/* Bit definition for Ethernet MAC Hash Table Low Register */
+#define ETH_MACHTLR_HTL 0xFFFFFFFFU /* Hash table low */
+
+/* Bit definition for Ethernet MAC MII Address Register */
+#define ETH_MACMIIAR_PA 0x0000F800U /* Physical layer address */
+#define ETH_MACMIIAR_MR 0x000007C0U /* MII register in the selected PHY */
+#define ETH_MACMIIAR_CR 0x0000001CU /* CR clock range: 6 cases */
+ #define ETH_MACMIIAR_CR_Div42 0x00000000U /* HCLK:60-100 MHz; MDC clock= HCLK/42 */
+ #define ETH_MACMIIAR_CR_Div62 0x00000004U /* HCLK:100-150 MHz; MDC clock= HCLK/62 */
+ #define ETH_MACMIIAR_CR_Div16 0x00000008U /* HCLK:20-35 MHz; MDC clock= HCLK/16 */
+ #define ETH_MACMIIAR_CR_Div26 0x0000000CU /* HCLK:35-60 MHz; MDC clock= HCLK/26 */
+ #define ETH_MACMIIAR_CR_Div102 0x00000010U /* HCLK:150-168 MHz; MDC clock= HCLK/102 */
+#define ETH_MACMIIAR_MW 0x00000002U /* MII write */
+#define ETH_MACMIIAR_MB 0x00000001U /* MII busy */
+
+/* Bit definition for Ethernet MAC MII Data Register */
+#define ETH_MACMIIDR_MD 0x0000FFFFU /* MII data: read/write data from/to PHY */
+
+/* Bit definition for Ethernet MAC Flow Control Register */
+#define ETH_MACFCR_PT 0xFFFF0000U /* Pause time */
+#define ETH_MACFCR_ZQPD 0x00000080U /* Zero-quanta pause disable */
+#define ETH_MACFCR_PLT 0x00000030U /* Pause low threshold: 4 cases */
+ #define ETH_MACFCR_PLT_Minus4 0x00000000U /* Pause time minus 4 slot times */
+ #define ETH_MACFCR_PLT_Minus28 0x00000010U /* Pause time minus 28 slot times */
+ #define ETH_MACFCR_PLT_Minus144 0x00000020U /* Pause time minus 144 slot times */
+ #define ETH_MACFCR_PLT_Minus256 0x00000030U /* Pause time minus 256 slot times */
+#define ETH_MACFCR_UPFD 0x00000008U /* Unicast pause frame detect */
+#define ETH_MACFCR_RFCE 0x00000004U /* Receive flow control enable */
+#define ETH_MACFCR_TFCE 0x00000002U /* Transmit flow control enable */
+#define ETH_MACFCR_FCBBPA 0x00000001U /* Flow control busy/backpressure activate */
+
+/* Bit definition for Ethernet MAC VLAN Tag Register */
+#define ETH_MACVLANTR_VLANTC 0x00010000U /* 12-bit VLAN tag comparison */
+#define ETH_MACVLANTR_VLANTI 0x0000FFFFU /* VLAN tag identifier (for receive frames) */
+
+/* Bit definition for Ethernet MAC Remote Wake-UpFrame Filter Register */
+#define ETH_MACRWUFFR_D 0xFFFFFFFFU /* Wake-up frame filter register data */
+/* Eight sequential Writes to this address (offset 0x28) will write all Wake-UpFrame Filter Registers.
+ Eight sequential Reads from this address (offset 0x28) will read all Wake-UpFrame Filter Registers. */
+/* Wake-UpFrame Filter Reg0 : Filter 0 Byte Mask
+ Wake-UpFrame Filter Reg1 : Filter 1 Byte Mask
+ Wake-UpFrame Filter Reg2 : Filter 2 Byte Mask
+ Wake-UpFrame Filter Reg3 : Filter 3 Byte Mask
+ Wake-UpFrame Filter Reg4 : RSVD - Filter3 Command - RSVD - Filter2 Command -
+ RSVD - Filter1 Command - RSVD - Filter0 Command
+ Wake-UpFrame Filter Re5 : Filter3 Offset - Filter2 Offset - Filter1 Offset - Filter0 Offset
+ Wake-UpFrame Filter Re6 : Filter1 CRC16 - Filter0 CRC16
+ Wake-UpFrame Filter Re7 : Filter3 CRC16 - Filter2 CRC16 */
+
+/* Bit definition for Ethernet MAC PMT Control and Status Register */
+#define ETH_MACPMTCSR_WFFRPR 0x80000000U /* Wake-Up Frame Filter Register Pointer Reset */
+#define ETH_MACPMTCSR_GU 0x00000200U /* Global Unicast */
+#define ETH_MACPMTCSR_WFR 0x00000040U /* Wake-Up Frame Received */
+#define ETH_MACPMTCSR_MPR 0x00000020U /* Magic Packet Received */
+#define ETH_MACPMTCSR_WFE 0x00000004U /* Wake-Up Frame Enable */
+#define ETH_MACPMTCSR_MPE 0x00000002U /* Magic Packet Enable */
+#define ETH_MACPMTCSR_PD 0x00000001U /* Power Down */
+
+/* Bit definition for Ethernet MAC Status Register */
+#define ETH_MACSR_TSTS 0x00000200U /* Time stamp trigger status */
+#define ETH_MACSR_MMCTS 0x00000040U /* MMC transmit status */
+#define ETH_MACSR_MMMCRS 0x00000020U /* MMC receive status */
+#define ETH_MACSR_MMCS 0x00000010U /* MMC status */
+#define ETH_MACSR_PMTS 0x00000008U /* PMT status */
+
+/* Bit definition for Ethernet MAC Interrupt Mask Register */
+#define ETH_MACIMR_TSTIM 0x00000200U /* Time stamp trigger interrupt mask */
+#define ETH_MACIMR_PMTIM 0x00000008U /* PMT interrupt mask */
+
+/* Bit definition for Ethernet MAC Address0 High Register */
+#define ETH_MACA0HR_MACA0H 0x0000FFFFU /* MAC address0 high */
+
+/* Bit definition for Ethernet MAC Address0 Low Register */
+#define ETH_MACA0LR_MACA0L 0xFFFFFFFFU /* MAC address0 low */
+
+/* Bit definition for Ethernet MAC Address1 High Register */
+#define ETH_MACA1HR_AE 0x80000000U /* Address enable */
+#define ETH_MACA1HR_SA 0x40000000U /* Source address */
+#define ETH_MACA1HR_MBC 0x3F000000U /* Mask byte control: bits to mask for comparison of the MAC Address bytes */
+ #define ETH_MACA1HR_MBC_HBits15_8 0x20000000U /* Mask MAC Address high reg bits [15:8] */
+ #define ETH_MACA1HR_MBC_HBits7_0 0x10000000U /* Mask MAC Address high reg bits [7:0] */
+ #define ETH_MACA1HR_MBC_LBits31_24 0x08000000U /* Mask MAC Address low reg bits [31:24] */
+ #define ETH_MACA1HR_MBC_LBits23_16 0x04000000U /* Mask MAC Address low reg bits [23:16] */
+ #define ETH_MACA1HR_MBC_LBits15_8 0x02000000U /* Mask MAC Address low reg bits [15:8] */
+ #define ETH_MACA1HR_MBC_LBits7_0 0x01000000U /* Mask MAC Address low reg bits [7:0] */
+#define ETH_MACA1HR_MACA1H 0x0000FFFFU /* MAC address1 high */
+
+/* Bit definition for Ethernet MAC Address1 Low Register */
+#define ETH_MACA1LR_MACA1L 0xFFFFFFFFU /* MAC address1 low */
+
+/* Bit definition for Ethernet MAC Address2 High Register */
+#define ETH_MACA2HR_AE 0x80000000U /* Address enable */
+#define ETH_MACA2HR_SA 0x40000000U /* Source address */
+#define ETH_MACA2HR_MBC 0x3F000000U /* Mask byte control */
+ #define ETH_MACA2HR_MBC_HBits15_8 0x20000000U /* Mask MAC Address high reg bits [15:8] */
+ #define ETH_MACA2HR_MBC_HBits7_0 0x10000000U /* Mask MAC Address high reg bits [7:0] */
+ #define ETH_MACA2HR_MBC_LBits31_24 0x08000000U /* Mask MAC Address low reg bits [31:24] */
+ #define ETH_MACA2HR_MBC_LBits23_16 0x04000000U /* Mask MAC Address low reg bits [23:16] */
+ #define ETH_MACA2HR_MBC_LBits15_8 0x02000000U /* Mask MAC Address low reg bits [15:8] */
+ #define ETH_MACA2HR_MBC_LBits7_0 0x01000000U /* Mask MAC Address low reg bits [70] */
+#define ETH_MACA2HR_MACA2H 0x0000FFFFU /* MAC address1 high */
+
+/* Bit definition for Ethernet MAC Address2 Low Register */
+#define ETH_MACA2LR_MACA2L 0xFFFFFFFFU /* MAC address2 low */
+
+/* Bit definition for Ethernet MAC Address3 High Register */
+#define ETH_MACA3HR_AE 0x80000000U /* Address enable */
+#define ETH_MACA3HR_SA 0x40000000U /* Source address */
+#define ETH_MACA3HR_MBC 0x3F000000U /* Mask byte control */
+ #define ETH_MACA3HR_MBC_HBits15_8 0x20000000U /* Mask MAC Address high reg bits [15:8] */
+ #define ETH_MACA3HR_MBC_HBits7_0 0x10000000U /* Mask MAC Address high reg bits [7:0] */
+ #define ETH_MACA3HR_MBC_LBits31_24 0x08000000U /* Mask MAC Address low reg bits [31:24] */
+ #define ETH_MACA3HR_MBC_LBits23_16 0x04000000U /* Mask MAC Address low reg bits [23:16] */
+ #define ETH_MACA3HR_MBC_LBits15_8 0x02000000U /* Mask MAC Address low reg bits [15:8] */
+ #define ETH_MACA3HR_MBC_LBits7_0 0x01000000U /* Mask MAC Address low reg bits [70] */
+#define ETH_MACA3HR_MACA3H 0x0000FFFFU /* MAC address3 high */
+
+/* Bit definition for Ethernet MAC Address3 Low Register */
+#define ETH_MACA3LR_MACA3L 0xFFFFFFFFU /* MAC address3 low */
+
+/******************************************************************************/
+/* Ethernet MMC Registers bits definition */
+/******************************************************************************/
+
+/* Bit definition for Ethernet MMC Contol Register */
+#define ETH_MMCCR_MCFHP 0x00000020U /* MMC counter Full-Half preset */
+#define ETH_MMCCR_MCP 0x00000010U /* MMC counter preset */
+#define ETH_MMCCR_MCF 0x00000008U /* MMC Counter Freeze */
+#define ETH_MMCCR_ROR 0x00000004U /* Reset on Read */
+#define ETH_MMCCR_CSR 0x00000002U /* Counter Stop Rollover */
+#define ETH_MMCCR_CR 0x00000001U /* Counters Reset */
+
+/* Bit definition for Ethernet MMC Receive Interrupt Register */
+#define ETH_MMCRIR_RGUFS 0x00020000U /* Set when Rx good unicast frames counter reaches half the maximum value */
+#define ETH_MMCRIR_RFAES 0x00000040U /* Set when Rx alignment error counter reaches half the maximum value */
+#define ETH_MMCRIR_RFCES 0x00000020U /* Set when Rx crc error counter reaches half the maximum value */
+
+/* Bit definition for Ethernet MMC Transmit Interrupt Register */
+#define ETH_MMCTIR_TGFS 0x00200000U /* Set when Tx good frame count counter reaches half the maximum value */
+#define ETH_MMCTIR_TGFMSCS 0x00008000U /* Set when Tx good multi col counter reaches half the maximum value */
+#define ETH_MMCTIR_TGFSCS 0x00004000U /* Set when Tx good single col counter reaches half the maximum value */
+
+/* Bit definition for Ethernet MMC Receive Interrupt Mask Register */
+#define ETH_MMCRIMR_RGUFM 0x00020000U /* Mask the interrupt when Rx good unicast frames counter reaches half the maximum value */
+#define ETH_MMCRIMR_RFAEM 0x00000040U /* Mask the interrupt when when Rx alignment error counter reaches half the maximum value */
+#define ETH_MMCRIMR_RFCEM 0x00000020U /* Mask the interrupt when Rx crc error counter reaches half the maximum value */
+
+/* Bit definition for Ethernet MMC Transmit Interrupt Mask Register */
+#define ETH_MMCTIMR_TGFM 0x00200000U /* Mask the interrupt when Tx good frame count counter reaches half the maximum value */
+#define ETH_MMCTIMR_TGFMSCM 0x00008000U /* Mask the interrupt when Tx good multi col counter reaches half the maximum value */
+#define ETH_MMCTIMR_TGFSCM 0x00004000U /* Mask the interrupt when Tx good single col counter reaches half the maximum value */
+
+/* Bit definition for Ethernet MMC Transmitted Good Frames after Single Collision Counter Register */
+#define ETH_MMCTGFSCCR_TGFSCC 0xFFFFFFFFU /* Number of successfully transmitted frames after a single collision in Half-duplex mode. */
+
+/* Bit definition for Ethernet MMC Transmitted Good Frames after More than a Single Collision Counter Register */
+#define ETH_MMCTGFMSCCR_TGFMSCC 0xFFFFFFFFU /* Number of successfully transmitted frames after more than a single collision in Half-duplex mode. */
+
+/* Bit definition for Ethernet MMC Transmitted Good Frames Counter Register */
+#define ETH_MMCTGFCR_TGFC 0xFFFFFFFFU /* Number of good frames transmitted. */
+
+/* Bit definition for Ethernet MMC Received Frames with CRC Error Counter Register */
+#define ETH_MMCRFCECR_RFCEC 0xFFFFFFFFU /* Number of frames received with CRC error. */
+
+/* Bit definition for Ethernet MMC Received Frames with Alignement Error Counter Register */
+#define ETH_MMCRFAECR_RFAEC 0xFFFFFFFFU /* Number of frames received with alignment (dribble) error */
+
+/* Bit definition for Ethernet MMC Received Good Unicast Frames Counter Register */
+#define ETH_MMCRGUFCR_RGUFC 0xFFFFFFFFU /* Number of good unicast frames received. */
+
+/******************************************************************************/
+/* Ethernet PTP Registers bits definition */
+/******************************************************************************/
+
+/* Bit definition for Ethernet PTP Time Stamp Contol Register */
+#define ETH_PTPTSCR_TSCNT 0x00030000U /* Time stamp clock node type */
+#define ETH_PTPTSSR_TSSMRME 0x00008000U /* Time stamp snapshot for message relevant to master enable */
+#define ETH_PTPTSSR_TSSEME 0x00004000U /* Time stamp snapshot for event message enable */
+#define ETH_PTPTSSR_TSSIPV4FE 0x00002000U /* Time stamp snapshot for IPv4 frames enable */
+#define ETH_PTPTSSR_TSSIPV6FE 0x00001000U /* Time stamp snapshot for IPv6 frames enable */
+#define ETH_PTPTSSR_TSSPTPOEFE 0x00000800U /* Time stamp snapshot for PTP over ethernet frames enable */
+#define ETH_PTPTSSR_TSPTPPSV2E 0x00000400U /* Time stamp PTP packet snooping for version2 format enable */
+#define ETH_PTPTSSR_TSSSR 0x00000200U /* Time stamp Sub-seconds rollover */
+#define ETH_PTPTSSR_TSSARFE 0x00000100U /* Time stamp snapshot for all received frames enable */
+
+#define ETH_PTPTSCR_TSARU 0x00000020U /* Addend register update */
+#define ETH_PTPTSCR_TSITE 0x00000010U /* Time stamp interrupt trigger enable */
+#define ETH_PTPTSCR_TSSTU 0x00000008U /* Time stamp update */
+#define ETH_PTPTSCR_TSSTI 0x00000004U /* Time stamp initialize */
+#define ETH_PTPTSCR_TSFCU 0x00000002U /* Time stamp fine or coarse update */
+#define ETH_PTPTSCR_TSE 0x00000001U /* Time stamp enable */
+
+/* Bit definition for Ethernet PTP Sub-Second Increment Register */
+#define ETH_PTPSSIR_STSSI 0x000000FFU /* System time Sub-second increment value */
+
+/* Bit definition for Ethernet PTP Time Stamp High Register */
+#define ETH_PTPTSHR_STS 0xFFFFFFFFU /* System Time second */
+
+/* Bit definition for Ethernet PTP Time Stamp Low Register */
+#define ETH_PTPTSLR_STPNS 0x80000000U /* System Time Positive or negative time */
+#define ETH_PTPTSLR_STSS 0x7FFFFFFFU /* System Time sub-seconds */
+
+/* Bit definition for Ethernet PTP Time Stamp High Update Register */
+#define ETH_PTPTSHUR_TSUS 0xFFFFFFFFU /* Time stamp update seconds */
+
+/* Bit definition for Ethernet PTP Time Stamp Low Update Register */
+#define ETH_PTPTSLUR_TSUPNS 0x80000000U /* Time stamp update Positive or negative time */
+#define ETH_PTPTSLUR_TSUSS 0x7FFFFFFFU /* Time stamp update sub-seconds */
+
+/* Bit definition for Ethernet PTP Time Stamp Addend Register */
+#define ETH_PTPTSAR_TSA 0xFFFFFFFFU /* Time stamp addend */
+
+/* Bit definition for Ethernet PTP Target Time High Register */
+#define ETH_PTPTTHR_TTSH 0xFFFFFFFFU /* Target time stamp high */
+
+/* Bit definition for Ethernet PTP Target Time Low Register */
+#define ETH_PTPTTLR_TTSL 0xFFFFFFFFU /* Target time stamp low */
+
+/* Bit definition for Ethernet PTP Time Stamp Status Register */
+#define ETH_PTPTSSR_TSTTR 0x00000020U /* Time stamp target time reached */
+#define ETH_PTPTSSR_TSSO 0x00000010U /* Time stamp seconds overflow */
+
+/******************************************************************************/
+/* Ethernet DMA Registers bits definition */
+/******************************************************************************/
+
+/* Bit definition for Ethernet DMA Bus Mode Register */
+#define ETH_DMABMR_AAB 0x02000000U /* Address-Aligned beats */
+#define ETH_DMABMR_FPM 0x01000000U /* 4xPBL mode */
+#define ETH_DMABMR_USP 0x00800000U /* Use separate PBL */
+#define ETH_DMABMR_RDP 0x007E0000U /* RxDMA PBL */
+ #define ETH_DMABMR_RDP_1Beat 0x00020000U /* maximum number of beats to be transferred in one RxDMA transaction is 1 */
+ #define ETH_DMABMR_RDP_2Beat 0x00040000U /* maximum number of beats to be transferred in one RxDMA transaction is 2 */
+ #define ETH_DMABMR_RDP_4Beat 0x00080000U /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
+ #define ETH_DMABMR_RDP_8Beat 0x00100000U /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
+ #define ETH_DMABMR_RDP_16Beat 0x00200000U /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
+ #define ETH_DMABMR_RDP_32Beat 0x00400000U /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
+ #define ETH_DMABMR_RDP_4xPBL_4Beat 0x01020000U /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
+ #define ETH_DMABMR_RDP_4xPBL_8Beat 0x01040000U /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
+ #define ETH_DMABMR_RDP_4xPBL_16Beat 0x01080000U /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
+ #define ETH_DMABMR_RDP_4xPBL_32Beat 0x01100000U /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
+ #define ETH_DMABMR_RDP_4xPBL_64Beat 0x01200000U /* maximum number of beats to be transferred in one RxDMA transaction is 64 */
+ #define ETH_DMABMR_RDP_4xPBL_128Beat 0x01400000U /* maximum number of beats to be transferred in one RxDMA transaction is 128 */
+#define ETH_DMABMR_FB 0x00010000U /* Fixed Burst */
+#define ETH_DMABMR_RTPR 0x0000C000U /* Rx Tx priority ratio */
+ #define ETH_DMABMR_RTPR_1_1 0x00000000U /* Rx Tx priority ratio */
+ #define ETH_DMABMR_RTPR_2_1 0x00004000U /* Rx Tx priority ratio */
+ #define ETH_DMABMR_RTPR_3_1 0x00008000U /* Rx Tx priority ratio */
+ #define ETH_DMABMR_RTPR_4_1 0x0000C000U /* Rx Tx priority ratio */
+#define ETH_DMABMR_PBL 0x00003F00U /* Programmable burst length */
+ #define ETH_DMABMR_PBL_1Beat 0x00000100U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */
+ #define ETH_DMABMR_PBL_2Beat 0x00000200U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */
+ #define ETH_DMABMR_PBL_4Beat 0x00000400U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
+ #define ETH_DMABMR_PBL_8Beat 0x00000800U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
+ #define ETH_DMABMR_PBL_16Beat 0x00001000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
+ #define ETH_DMABMR_PBL_32Beat 0x00002000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
+ #define ETH_DMABMR_PBL_4xPBL_4Beat 0x01000100U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
+ #define ETH_DMABMR_PBL_4xPBL_8Beat 0x01000200U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
+ #define ETH_DMABMR_PBL_4xPBL_16Beat 0x01000400U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
+ #define ETH_DMABMR_PBL_4xPBL_32Beat 0x01000800U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
+ #define ETH_DMABMR_PBL_4xPBL_64Beat 0x01001000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */
+ #define ETH_DMABMR_PBL_4xPBL_128Beat 0x01002000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */
+#define ETH_DMABMR_EDE 0x00000080U /* Enhanced Descriptor Enable */
+#define ETH_DMABMR_DSL 0x0000007CU /* Descriptor Skip Length */
+#define ETH_DMABMR_DA 0x00000002U /* DMA arbitration scheme */
+#define ETH_DMABMR_SR 0x00000001U /* Software reset */
+
+/* Bit definition for Ethernet DMA Transmit Poll Demand Register */
+#define ETH_DMATPDR_TPD 0xFFFFFFFFU /* Transmit poll demand */
+
+/* Bit definition for Ethernet DMA Receive Poll Demand Register */
+#define ETH_DMARPDR_RPD 0xFFFFFFFFU /* Receive poll demand */
+
+/* Bit definition for Ethernet DMA Receive Descriptor List Address Register */
+#define ETH_DMARDLAR_SRL 0xFFFFFFFFU /* Start of receive list */
+
+/* Bit definition for Ethernet DMA Transmit Descriptor List Address Register */
+#define ETH_DMATDLAR_STL 0xFFFFFFFFU /* Start of transmit list */
+
+/* Bit definition for Ethernet DMA Status Register */
+#define ETH_DMASR_TSTS 0x20000000U /* Time-stamp trigger status */
+#define ETH_DMASR_PMTS 0x10000000U /* PMT status */
+#define ETH_DMASR_MMCS 0x08000000U /* MMC status */
+#define ETH_DMASR_EBS 0x03800000U /* Error bits status */
+ /* combination with EBS[2:0] for GetFlagStatus function */
+ #define ETH_DMASR_EBS_DescAccess 0x02000000U /* Error bits 0-data buffer, 1-desc. access */
+ #define ETH_DMASR_EBS_ReadTransf 0x01000000U /* Error bits 0-write trnsf, 1-read transfr */
+ #define ETH_DMASR_EBS_DataTransfTx 0x00800000U /* Error bits 0-Rx DMA, 1-Tx DMA */
+#define ETH_DMASR_TPS 0x00700000U /* Transmit process state */
+ #define ETH_DMASR_TPS_Stopped 0x00000000U /* Stopped - Reset or Stop Tx Command issued */
+ #define ETH_DMASR_TPS_Fetching 0x00100000U /* Running - fetching the Tx descriptor */
+ #define ETH_DMASR_TPS_Waiting 0x00200000U /* Running - waiting for status */
+ #define ETH_DMASR_TPS_Reading 0x00300000U /* Running - reading the data from host memory */
+ #define ETH_DMASR_TPS_Suspended 0x00600000U /* Suspended - Tx Descriptor unavailabe */
+ #define ETH_DMASR_TPS_Closing 0x00700000U /* Running - closing Rx descriptor */
+#define ETH_DMASR_RPS 0x000E0000U /* Receive process state */
+ #define ETH_DMASR_RPS_Stopped 0x00000000U /* Stopped - Reset or Stop Rx Command issued */
+ #define ETH_DMASR_RPS_Fetching 0x00020000U /* Running - fetching the Rx descriptor */
+ #define ETH_DMASR_RPS_Waiting 0x00060000U /* Running - waiting for packet */
+ #define ETH_DMASR_RPS_Suspended 0x00080000U /* Suspended - Rx Descriptor unavailable */
+ #define ETH_DMASR_RPS_Closing 0x000A0000U /* Running - closing descriptor */
+ #define ETH_DMASR_RPS_Queuing 0x000E0000U /* Running - queuing the recieve frame into host memory */
+#define ETH_DMASR_NIS 0x00010000U /* Normal interrupt summary */
+#define ETH_DMASR_AIS 0x00008000U /* Abnormal interrupt summary */
+#define ETH_DMASR_ERS 0x00004000U /* Early receive status */
+#define ETH_DMASR_FBES 0x00002000U /* Fatal bus error status */
+#define ETH_DMASR_ETS 0x00000400U /* Early transmit status */
+#define ETH_DMASR_RWTS 0x00000200U /* Receive watchdog timeout status */
+#define ETH_DMASR_RPSS 0x00000100U /* Receive process stopped status */
+#define ETH_DMASR_RBUS 0x00000080U /* Receive buffer unavailable status */
+#define ETH_DMASR_RS 0x00000040U /* Receive status */
+#define ETH_DMASR_TUS 0x00000020U /* Transmit underflow status */
+#define ETH_DMASR_ROS 0x00000010U /* Receive overflow status */
+#define ETH_DMASR_TJTS 0x00000008U /* Transmit jabber timeout status */
+#define ETH_DMASR_TBUS 0x00000004U /* Transmit buffer unavailable status */
+#define ETH_DMASR_TPSS 0x00000002U /* Transmit process stopped status */
+#define ETH_DMASR_TS 0x00000001U /* Transmit status */
+
+/* Bit definition for Ethernet DMA Operation Mode Register */
+#define ETH_DMAOMR_DTCEFD 0x04000000U /* Disable Dropping of TCP/IP checksum error frames */
+#define ETH_DMAOMR_RSF 0x02000000U /* Receive store and forward */
+#define ETH_DMAOMR_DFRF 0x01000000U /* Disable flushing of received frames */
+#define ETH_DMAOMR_TSF 0x00200000U /* Transmit store and forward */
+#define ETH_DMAOMR_FTF 0x00100000U /* Flush transmit FIFO */
+#define ETH_DMAOMR_TTC 0x0001C000U /* Transmit threshold control */
+ #define ETH_DMAOMR_TTC_64Bytes 0x00000000U /* threshold level of the MTL Transmit FIFO is 64 Bytes */
+ #define ETH_DMAOMR_TTC_128Bytes 0x00004000U /* threshold level of the MTL Transmit FIFO is 128 Bytes */
+ #define ETH_DMAOMR_TTC_192Bytes 0x00008000U /* threshold level of the MTL Transmit FIFO is 192 Bytes */
+ #define ETH_DMAOMR_TTC_256Bytes 0x0000C000U /* threshold level of the MTL Transmit FIFO is 256 Bytes */
+ #define ETH_DMAOMR_TTC_40Bytes 0x00010000U /* threshold level of the MTL Transmit FIFO is 40 Bytes */
+ #define ETH_DMAOMR_TTC_32Bytes 0x00014000U /* threshold level of the MTL Transmit FIFO is 32 Bytes */
+ #define ETH_DMAOMR_TTC_24Bytes 0x00018000U /* threshold level of the MTL Transmit FIFO is 24 Bytes */
+ #define ETH_DMAOMR_TTC_16Bytes 0x0001C000U /* threshold level of the MTL Transmit FIFO is 16 Bytes */
+#define ETH_DMAOMR_ST 0x00002000U /* Start/stop transmission command */
+#define ETH_DMAOMR_FEF 0x00000080U /* Forward error frames */
+#define ETH_DMAOMR_FUGF 0x00000040U /* Forward undersized good frames */
+#define ETH_DMAOMR_RTC 0x00000018U /* receive threshold control */
+ #define ETH_DMAOMR_RTC_64Bytes 0x00000000U /* threshold level of the MTL Receive FIFO is 64 Bytes */
+ #define ETH_DMAOMR_RTC_32Bytes 0x00000008U /* threshold level of the MTL Receive FIFO is 32 Bytes */
+ #define ETH_DMAOMR_RTC_96Bytes 0x00000010U /* threshold level of the MTL Receive FIFO is 96 Bytes */
+ #define ETH_DMAOMR_RTC_128Bytes 0x00000018U /* threshold level of the MTL Receive FIFO is 128 Bytes */
+#define ETH_DMAOMR_OSF 0x00000004U /* operate on second frame */
+#define ETH_DMAOMR_SR 0x00000002U /* Start/stop receive */
+
+/* Bit definition for Ethernet DMA Interrupt Enable Register */
+#define ETH_DMAIER_NISE 0x00010000U /* Normal interrupt summary enable */
+#define ETH_DMAIER_AISE 0x00008000U /* Abnormal interrupt summary enable */
+#define ETH_DMAIER_ERIE 0x00004000U /* Early receive interrupt enable */
+#define ETH_DMAIER_FBEIE 0x00002000U /* Fatal bus error interrupt enable */
+#define ETH_DMAIER_ETIE 0x00000400U /* Early transmit interrupt enable */
+#define ETH_DMAIER_RWTIE 0x00000200U /* Receive watchdog timeout interrupt enable */
+#define ETH_DMAIER_RPSIE 0x00000100U /* Receive process stopped interrupt enable */
+#define ETH_DMAIER_RBUIE 0x00000080U /* Receive buffer unavailable interrupt enable */
+#define ETH_DMAIER_RIE 0x00000040U /* Receive interrupt enable */
+#define ETH_DMAIER_TUIE 0x00000020U /* Transmit Underflow interrupt enable */
+#define ETH_DMAIER_ROIE 0x00000010U /* Receive Overflow interrupt enable */
+#define ETH_DMAIER_TJTIE 0x00000008U /* Transmit jabber timeout interrupt enable */
+#define ETH_DMAIER_TBUIE 0x00000004U /* Transmit buffer unavailable interrupt enable */
+#define ETH_DMAIER_TPSIE 0x00000002U /* Transmit process stopped interrupt enable */
+#define ETH_DMAIER_TIE 0x00000001U /* Transmit interrupt enable */
+
+/* Bit definition for Ethernet DMA Missed Frame and Buffer Overflow Counter Register */
+#define ETH_DMAMFBOCR_OFOC 0x10000000U /* Overflow bit for FIFO overflow counter */
+#define ETH_DMAMFBOCR_MFA 0x0FFE0000U /* Number of frames missed by the application */
+#define ETH_DMAMFBOCR_OMFC 0x00010000U /* Overflow bit for missed frame counter */
+#define ETH_DMAMFBOCR_MFC 0x0000FFFFU /* Number of frames missed by the controller */
+
+/* Bit definition for Ethernet DMA Current Host Transmit Descriptor Register */
+#define ETH_DMACHTDR_HTDAP 0xFFFFFFFFU /* Host transmit descriptor address pointer */
+
+/* Bit definition for Ethernet DMA Current Host Receive Descriptor Register */
+#define ETH_DMACHRDR_HRDAP 0xFFFFFFFFU /* Host receive descriptor address pointer */
+
+/* Bit definition for Ethernet DMA Current Host Transmit Buffer Address Register */
+#define ETH_DMACHTBAR_HTBAP 0xFFFFFFFFU /* Host transmit buffer address pointer */
+
+/* Bit definition for Ethernet DMA Current Host Receive Buffer Address Register */
+#define ETH_DMACHRBAR_HRBAP 0xFFFFFFFFU /* Host receive buffer address pointer */
+
+/******************************************************************************/
+/* */
+/* USB_OTG */
+/* */
+/******************************************************************************/
+/******************** Bit definition forUSB_OTG_GOTGCTL register ********************/
+#define USB_OTG_GOTGCTL_SRQSCS 0x00000001U /*!< Session request success */
+#define USB_OTG_GOTGCTL_SRQ 0x00000002U /*!< Session request */
+#define USB_OTG_GOTGCTL_HNGSCS 0x00000100U /*!< Host negotiation success */
+#define USB_OTG_GOTGCTL_HNPRQ 0x00000200U /*!< HNP request */
+#define USB_OTG_GOTGCTL_HSHNPEN 0x00000400U /*!< Host set HNP enable */
+#define USB_OTG_GOTGCTL_DHNPEN 0x00000800U /*!< Device HNP enabled */
+#define USB_OTG_GOTGCTL_CIDSTS 0x00010000U /*!< Connector ID status */
+#define USB_OTG_GOTGCTL_DBCT 0x00020000U /*!< Long/short debounce time */
+#define USB_OTG_GOTGCTL_ASVLD 0x00040000U /*!< A-session valid */
+#define USB_OTG_GOTGCTL_BSVLD 0x00080000U /*!< B-session valid */
+
+/******************** Bit definition forUSB_OTG_HCFG register ********************/
+
+#define USB_OTG_HCFG_FSLSPCS 0x00000003U /*!< FS/LS PHY clock select */
+#define USB_OTG_HCFG_FSLSPCS_0 0x00000001U /*!<Bit 0 */
+#define USB_OTG_HCFG_FSLSPCS_1 0x00000002U /*!<Bit 1 */
+#define USB_OTG_HCFG_FSLSS 0x00000004U /*!< FS- and LS-only support */
+
+/******************** Bit definition forUSB_OTG_DCFG register ********************/
+
+#define USB_OTG_DCFG_DSPD 0x00000003U /*!< Device speed */
+#define USB_OTG_DCFG_DSPD_0 0x00000001U /*!<Bit 0 */
+#define USB_OTG_DCFG_DSPD_1 0x00000002U /*!<Bit 1 */
+#define USB_OTG_DCFG_NZLSOHSK 0x00000004U /*!< Nonzero-length status OUT handshake */
+
+#define USB_OTG_DCFG_DAD 0x000007F0U /*!< Device address */
+#define USB_OTG_DCFG_DAD_0 0x00000010U /*!<Bit 0 */
+#define USB_OTG_DCFG_DAD_1 0x00000020U /*!<Bit 1 */
+#define USB_OTG_DCFG_DAD_2 0x00000040U /*!<Bit 2 */
+#define USB_OTG_DCFG_DAD_3 0x00000080U /*!<Bit 3 */
+#define USB_OTG_DCFG_DAD_4 0x00000100U /*!<Bit 4 */
+#define USB_OTG_DCFG_DAD_5 0x00000200U /*!<Bit 5 */
+#define USB_OTG_DCFG_DAD_6 0x00000400U /*!<Bit 6 */
+
+#define USB_OTG_DCFG_PFIVL 0x00001800U /*!< Periodic (micro)frame interval */
+#define USB_OTG_DCFG_PFIVL_0 0x00000800U /*!<Bit 0 */
+#define USB_OTG_DCFG_PFIVL_1 0x00001000U /*!<Bit 1 */
+
+#define USB_OTG_DCFG_PERSCHIVL 0x03000000U /*!< Periodic scheduling interval */
+#define USB_OTG_DCFG_PERSCHIVL_0 0x01000000U /*!<Bit 0 */
+#define USB_OTG_DCFG_PERSCHIVL_1 0x02000000U /*!<Bit 1 */
+
+/******************** Bit definition forUSB_OTG_PCGCR register ********************/
+#define USB_OTG_PCGCR_STPPCLK 0x00000001U /*!< Stop PHY clock */
+#define USB_OTG_PCGCR_GATEHCLK 0x00000002U /*!< Gate HCLK */
+#define USB_OTG_PCGCR_PHYSUSP 0x00000010U /*!< PHY suspended */
+
+/******************** Bit definition forUSB_OTG_GOTGINT register ********************/
+#define USB_OTG_GOTGINT_SEDET 0x00000004U /*!< Session end detected */
+#define USB_OTG_GOTGINT_SRSSCHG 0x00000100U /*!< Session request success status change */
+#define USB_OTG_GOTGINT_HNSSCHG 0x00000200U /*!< Host negotiation success status change */
+#define USB_OTG_GOTGINT_HNGDET 0x00020000U /*!< Host negotiation detected */
+#define USB_OTG_GOTGINT_ADTOCHG 0x00040000U /*!< A-device timeout change */
+#define USB_OTG_GOTGINT_DBCDNE 0x00080000U /*!< Debounce done */
+
+/******************** Bit definition forUSB_OTG_DCTL register ********************/
+#define USB_OTG_DCTL_RWUSIG 0x00000001U /*!< Remote wakeup signaling */
+#define USB_OTG_DCTL_SDIS 0x00000002U /*!< Soft disconnect */
+#define USB_OTG_DCTL_GINSTS 0x00000004U /*!< Global IN NAK status */
+#define USB_OTG_DCTL_GONSTS 0x00000008U /*!< Global OUT NAK status */
+
+#define USB_OTG_DCTL_TCTL 0x00000070U /*!< Test control */
+#define USB_OTG_DCTL_TCTL_0 0x00000010U /*!<Bit 0 */
+#define USB_OTG_DCTL_TCTL_1 0x00000020U /*!<Bit 1 */
+#define USB_OTG_DCTL_TCTL_2 0x00000040U /*!<Bit 2 */
+#define USB_OTG_DCTL_SGINAK 0x00000080U /*!< Set global IN NAK */
+#define USB_OTG_DCTL_CGINAK 0x00000100U /*!< Clear global IN NAK */
+#define USB_OTG_DCTL_SGONAK 0x00000200U /*!< Set global OUT NAK */
+#define USB_OTG_DCTL_CGONAK 0x00000400U /*!< Clear global OUT NAK */
+#define USB_OTG_DCTL_POPRGDNE 0x00000800U /*!< Power-on programming done */
+
+/******************** Bit definition forUSB_OTG_HFIR register ********************/
+#define USB_OTG_HFIR_FRIVL 0x0000FFFFU /*!< Frame interval */
+
+/******************** Bit definition forUSB_OTG_HFNUM register ********************/
+#define USB_OTG_HFNUM_FRNUM 0x0000FFFFU /*!< Frame number */
+#define USB_OTG_HFNUM_FTREM 0xFFFF0000U /*!< Frame time remaining */
+
+/******************** Bit definition forUSB_OTG_DSTS register ********************/
+#define USB_OTG_DSTS_SUSPSTS 0x00000001U /*!< Suspend status */
+
+#define USB_OTG_DSTS_ENUMSPD 0x00000006U /*!< Enumerated speed */
+#define USB_OTG_DSTS_ENUMSPD_0 0x00000002U /*!<Bit 0 */
+#define USB_OTG_DSTS_ENUMSPD_1 0x00000004U /*!<Bit 1 */
+#define USB_OTG_DSTS_EERR 0x00000008U /*!< Erratic error */
+#define USB_OTG_DSTS_FNSOF 0x003FFF00U /*!< Frame number of the received SOF */
+
+/******************** Bit definition forUSB_OTG_GAHBCFG register ********************/
+#define USB_OTG_GAHBCFG_GINT 0x00000001U /*!< Global interrupt mask */
+
+#define USB_OTG_GAHBCFG_HBSTLEN 0x0000001EU /*!< Burst length/type */
+#define USB_OTG_GAHBCFG_HBSTLEN_0 0x00000002U /*!<Bit 0 */
+#define USB_OTG_GAHBCFG_HBSTLEN_1 0x00000004U /*!<Bit 1 */
+#define USB_OTG_GAHBCFG_HBSTLEN_2 0x00000008U /*!<Bit 2 */
+#define USB_OTG_GAHBCFG_HBSTLEN_3 0x00000010U /*!<Bit 3 */
+#define USB_OTG_GAHBCFG_DMAEN 0x00000020U /*!< DMA enable */
+#define USB_OTG_GAHBCFG_TXFELVL 0x00000080U /*!< TxFIFO empty level */
+#define USB_OTG_GAHBCFG_PTXFELVL 0x00000100U /*!< Periodic TxFIFO empty level */
+
+/******************** Bit definition forUSB_OTG_GUSBCFG register ********************/
+
+#define USB_OTG_GUSBCFG_TOCAL 0x00000007U /*!< FS timeout calibration */
+#define USB_OTG_GUSBCFG_TOCAL_0 0x00000001U /*!<Bit 0 */
+#define USB_OTG_GUSBCFG_TOCAL_1 0x00000002U /*!<Bit 1 */
+#define USB_OTG_GUSBCFG_TOCAL_2 0x00000004U /*!<Bit 2 */
+#define USB_OTG_GUSBCFG_PHYSEL 0x00000040U /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */
+#define USB_OTG_GUSBCFG_SRPCAP 0x00000100U /*!< SRP-capable */
+#define USB_OTG_GUSBCFG_HNPCAP 0x00000200U /*!< HNP-capable */
+
+#define USB_OTG_GUSBCFG_TRDT 0x00003C00U /*!< USB turnaround time */
+#define USB_OTG_GUSBCFG_TRDT_0 0x00000400U /*!<Bit 0 */
+#define USB_OTG_GUSBCFG_TRDT_1 0x00000800U /*!<Bit 1 */
+#define USB_OTG_GUSBCFG_TRDT_2 0x00001000U /*!<Bit 2 */
+#define USB_OTG_GUSBCFG_TRDT_3 0x00002000U /*!<Bit 3 */
+#define USB_OTG_GUSBCFG_PHYLPCS 0x00008000U /*!< PHY Low-power clock select */
+#define USB_OTG_GUSBCFG_ULPIFSLS 0x00020000U /*!< ULPI FS/LS select */
+#define USB_OTG_GUSBCFG_ULPIAR 0x00040000U /*!< ULPI Auto-resume */
+#define USB_OTG_GUSBCFG_ULPICSM 0x00080000U /*!< ULPI Clock SuspendM */
+#define USB_OTG_GUSBCFG_ULPIEVBUSD 0x00100000U /*!< ULPI External VBUS Drive */
+#define USB_OTG_GUSBCFG_ULPIEVBUSI 0x00200000U /*!< ULPI external VBUS indicator */
+#define USB_OTG_GUSBCFG_TSDPS 0x00400000U /*!< TermSel DLine pulsing selection */
+#define USB_OTG_GUSBCFG_PCCI 0x00800000U /*!< Indicator complement */
+#define USB_OTG_GUSBCFG_PTCI 0x01000000U /*!< Indicator pass through */
+#define USB_OTG_GUSBCFG_ULPIIPD 0x02000000U /*!< ULPI interface protect disable */
+#define USB_OTG_GUSBCFG_FHMOD 0x20000000U /*!< Forced host mode */
+#define USB_OTG_GUSBCFG_FDMOD 0x40000000U /*!< Forced peripheral mode */
+#define USB_OTG_GUSBCFG_CTXPKT 0x80000000U /*!< Corrupt Tx packet */
+
+/******************** Bit definition forUSB_OTG_GRSTCTL register ********************/
+#define USB_OTG_GRSTCTL_CSRST 0x00000001U /*!< Core soft reset */
+#define USB_OTG_GRSTCTL_HSRST 0x00000002U /*!< HCLK soft reset */
+#define USB_OTG_GRSTCTL_FCRST 0x00000004U /*!< Host frame counter reset */
+#define USB_OTG_GRSTCTL_RXFFLSH 0x00000010U /*!< RxFIFO flush */
+#define USB_OTG_GRSTCTL_TXFFLSH 0x00000020U /*!< TxFIFO flush */
+
+#define USB_OTG_GRSTCTL_TXFNUM 0x000007C0U /*!< TxFIFO number */
+#define USB_OTG_GRSTCTL_TXFNUM_0 0x00000040U /*!<Bit 0 */
+#define USB_OTG_GRSTCTL_TXFNUM_1 0x00000080U /*!<Bit 1 */
+#define USB_OTG_GRSTCTL_TXFNUM_2 0x00000100U /*!<Bit 2 */
+#define USB_OTG_GRSTCTL_TXFNUM_3 0x00000200U /*!<Bit 3 */
+#define USB_OTG_GRSTCTL_TXFNUM_4 0x00000400U /*!<Bit 4 */
+#define USB_OTG_GRSTCTL_DMAREQ 0x40000000U /*!< DMA request signal */
+#define USB_OTG_GRSTCTL_AHBIDL 0x80000000U /*!< AHB master idle */
+
+/******************** Bit definition forUSB_OTG_DIEPMSK register ********************/
+#define USB_OTG_DIEPMSK_XFRCM 0x00000001U /*!< Transfer completed interrupt mask */
+#define USB_OTG_DIEPMSK_EPDM 0x00000002U /*!< Endpoint disabled interrupt mask */
+#define USB_OTG_DIEPMSK_TOM 0x00000008U /*!< Timeout condition mask (nonisochronous endpoints) */
+#define USB_OTG_DIEPMSK_ITTXFEMSK 0x00000010U /*!< IN token received when TxFIFO empty mask */
+#define USB_OTG_DIEPMSK_INEPNMM 0x00000020U /*!< IN token received with EP mismatch mask */
+#define USB_OTG_DIEPMSK_INEPNEM 0x00000040U /*!< IN endpoint NAK effective mask */
+#define USB_OTG_DIEPMSK_TXFURM 0x00000100U /*!< FIFO underrun mask */
+#define USB_OTG_DIEPMSK_BIM 0x00000200U /*!< BNA interrupt mask */
+
+/******************** Bit definition forUSB_OTG_HPTXSTS register ********************/
+#define USB_OTG_HPTXSTS_PTXFSAVL 0x0000FFFFU /*!< Periodic transmit data FIFO space available */
+
+#define USB_OTG_HPTXSTS_PTXQSAV 0x00FF0000U /*!< Periodic transmit request queue space available */
+#define USB_OTG_HPTXSTS_PTXQSAV_0 0x00010000U /*!<Bit 0 */
+#define USB_OTG_HPTXSTS_PTXQSAV_1 0x00020000U /*!<Bit 1 */
+#define USB_OTG_HPTXSTS_PTXQSAV_2 0x00040000U /*!<Bit 2 */
+#define USB_OTG_HPTXSTS_PTXQSAV_3 0x00080000U /*!<Bit 3 */
+#define USB_OTG_HPTXSTS_PTXQSAV_4 0x00100000U /*!<Bit 4 */
+#define USB_OTG_HPTXSTS_PTXQSAV_5 0x00200000U /*!<Bit 5 */
+#define USB_OTG_HPTXSTS_PTXQSAV_6 0x00400000U /*!<Bit 6 */
+#define USB_OTG_HPTXSTS_PTXQSAV_7 0x00800000U /*!<Bit 7 */
+
+#define USB_OTG_HPTXSTS_PTXQTOP 0xFF000000U /*!< Top of the periodic transmit request queue */
+#define USB_OTG_HPTXSTS_PTXQTOP_0 0x01000000U /*!<Bit 0 */
+#define USB_OTG_HPTXSTS_PTXQTOP_1 0x02000000U /*!<Bit 1 */
+#define USB_OTG_HPTXSTS_PTXQTOP_2 0x04000000U /*!<Bit 2 */
+#define USB_OTG_HPTXSTS_PTXQTOP_3 0x08000000U /*!<Bit 3 */
+#define USB_OTG_HPTXSTS_PTXQTOP_4 0x10000000U /*!<Bit 4 */
+#define USB_OTG_HPTXSTS_PTXQTOP_5 0x20000000U /*!<Bit 5 */
+#define USB_OTG_HPTXSTS_PTXQTOP_6 0x40000000U /*!<Bit 6 */
+#define USB_OTG_HPTXSTS_PTXQTOP_7 0x80000000U /*!<Bit 7 */
+
+/******************** Bit definition forUSB_OTG_HAINT register ********************/
+#define USB_OTG_HAINT_HAINT 0x0000FFFFU /*!< Channel interrupts */
+
+/******************** Bit definition forUSB_OTG_DOEPMSK register ********************/
+#define USB_OTG_DOEPMSK_XFRCM 0x00000001U /*!< Transfer completed interrupt mask */
+#define USB_OTG_DOEPMSK_EPDM 0x00000002U /*!< Endpoint disabled interrupt mask */
+#define USB_OTG_DOEPMSK_STUPM 0x00000008U /*!< SETUP phase done mask */
+#define USB_OTG_DOEPMSK_OTEPDM 0x00000010U /*!< OUT token received when endpoint disabled mask */
+#define USB_OTG_DOEPMSK_B2BSTUP 0x00000040U /*!< Back-to-back SETUP packets received mask */
+#define USB_OTG_DOEPMSK_OPEM 0x00000100U /*!< OUT packet error mask */
+#define USB_OTG_DOEPMSK_BOIM 0x00000200U /*!< BNA interrupt mask */
+
+/******************** Bit definition forUSB_OTG_GINTSTS register ********************/
+#define USB_OTG_GINTSTS_CMOD 0x00000001U /*!< Current mode of operation */
+#define USB_OTG_GINTSTS_MMIS 0x00000002U /*!< Mode mismatch interrupt */
+#define USB_OTG_GINTSTS_OTGINT 0x00000004U /*!< OTG interrupt */
+#define USB_OTG_GINTSTS_SOF 0x00000008U /*!< Start of frame */
+#define USB_OTG_GINTSTS_RXFLVL 0x00000010U /*!< RxFIFO nonempty */
+#define USB_OTG_GINTSTS_NPTXFE 0x00000020U /*!< Nonperiodic TxFIFO empty */
+#define USB_OTG_GINTSTS_GINAKEFF 0x00000040U /*!< Global IN nonperiodic NAK effective */
+#define USB_OTG_GINTSTS_BOUTNAKEFF 0x00000080U /*!< Global OUT NAK effective */
+#define USB_OTG_GINTSTS_ESUSP 0x00000400U /*!< Early suspend */
+#define USB_OTG_GINTSTS_USBSUSP 0x00000800U /*!< USB suspend */
+#define USB_OTG_GINTSTS_USBRST 0x00001000U /*!< USB reset */
+#define USB_OTG_GINTSTS_ENUMDNE 0x00002000U /*!< Enumeration done */
+#define USB_OTG_GINTSTS_ISOODRP 0x00004000U /*!< Isochronous OUT packet dropped interrupt */
+#define USB_OTG_GINTSTS_EOPF 0x00008000U /*!< End of periodic frame interrupt */
+#define USB_OTG_GINTSTS_IEPINT 0x00040000U /*!< IN endpoint interrupt */
+#define USB_OTG_GINTSTS_OEPINT 0x00080000U /*!< OUT endpoint interrupt */
+#define USB_OTG_GINTSTS_IISOIXFR 0x00100000U /*!< Incomplete isochronous IN transfer */
+#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT 0x00200000U /*!< Incomplete periodic transfer */
+#define USB_OTG_GINTSTS_DATAFSUSP 0x00400000U /*!< Data fetch suspended */
+#define USB_OTG_GINTSTS_HPRTINT 0x01000000U /*!< Host port interrupt */
+#define USB_OTG_GINTSTS_HCINT 0x02000000U /*!< Host channels interrupt */
+#define USB_OTG_GINTSTS_PTXFE 0x04000000U /*!< Periodic TxFIFO empty */
+#define USB_OTG_GINTSTS_CIDSCHG 0x10000000U /*!< Connector ID status change */
+#define USB_OTG_GINTSTS_DISCINT 0x20000000U /*!< Disconnect detected interrupt */
+#define USB_OTG_GINTSTS_SRQINT 0x40000000U /*!< Session request/new session detected interrupt */
+#define USB_OTG_GINTSTS_WKUINT 0x80000000U /*!< Resume/remote wakeup detected interrupt */
+
+/******************** Bit definition forUSB_OTG_GINTMSK register ********************/
+#define USB_OTG_GINTMSK_MMISM 0x00000002U /*!< Mode mismatch interrupt mask */
+#define USB_OTG_GINTMSK_OTGINT 0x00000004U /*!< OTG interrupt mask */
+#define USB_OTG_GINTMSK_SOFM 0x00000008U /*!< Start of frame mask */
+#define USB_OTG_GINTMSK_RXFLVLM 0x00000010U /*!< Receive FIFO nonempty mask */
+#define USB_OTG_GINTMSK_NPTXFEM 0x00000020U /*!< Nonperiodic TxFIFO empty mask */
+#define USB_OTG_GINTMSK_GINAKEFFM 0x00000040U /*!< Global nonperiodic IN NAK effective mask */
+#define USB_OTG_GINTMSK_GONAKEFFM 0x00000080U /*!< Global OUT NAK effective mask */
+#define USB_OTG_GINTMSK_ESUSPM 0x00000400U /*!< Early suspend mask */
+#define USB_OTG_GINTMSK_USBSUSPM 0x00000800U /*!< USB suspend mask */
+#define USB_OTG_GINTMSK_USBRST 0x00001000U /*!< USB reset mask */
+#define USB_OTG_GINTMSK_ENUMDNEM 0x00002000U /*!< Enumeration done mask */
+#define USB_OTG_GINTMSK_ISOODRPM 0x00004000U /*!< Isochronous OUT packet dropped interrupt mask */
+#define USB_OTG_GINTMSK_EOPFM 0x00008000U /*!< End of periodic frame interrupt mask */
+#define USB_OTG_GINTMSK_EPMISM 0x00020000U /*!< Endpoint mismatch interrupt mask */
+#define USB_OTG_GINTMSK_IEPINT 0x00040000U /*!< IN endpoints interrupt mask */
+#define USB_OTG_GINTMSK_OEPINT 0x00080000U /*!< OUT endpoints interrupt mask */
+#define USB_OTG_GINTMSK_IISOIXFRM 0x00100000U /*!< Incomplete isochronous IN transfer mask */
+#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM 0x00200000U /*!< Incomplete periodic transfer mask */
+#define USB_OTG_GINTMSK_FSUSPM 0x00400000U /*!< Data fetch suspended mask */
+#define USB_OTG_GINTMSK_PRTIM 0x01000000U /*!< Host port interrupt mask */
+#define USB_OTG_GINTMSK_HCIM 0x02000000U /*!< Host channels interrupt mask */
+#define USB_OTG_GINTMSK_PTXFEM 0x04000000U /*!< Periodic TxFIFO empty mask */
+#define USB_OTG_GINTMSK_CIDSCHGM 0x10000000U /*!< Connector ID status change mask */
+#define USB_OTG_GINTMSK_DISCINT 0x20000000U /*!< Disconnect detected interrupt mask */
+#define USB_OTG_GINTMSK_SRQIM 0x40000000U /*!< Session request/new session detected interrupt mask */
+#define USB_OTG_GINTMSK_WUIM 0x80000000U /*!< Resume/remote wakeup detected interrupt mask */
+
+/******************** Bit definition forUSB_OTG_DAINT register ********************/
+#define USB_OTG_DAINT_IEPINT 0x0000FFFFU /*!< IN endpoint interrupt bits */
+#define USB_OTG_DAINT_OEPINT 0xFFFF0000U /*!< OUT endpoint interrupt bits */
+
+/******************** Bit definition forUSB_OTG_HAINTMSK register ********************/
+#define USB_OTG_HAINTMSK_HAINTM 0x0000FFFFU /*!< Channel interrupt mask */
+
+/******************** Bit definition for USB_OTG_GRXSTSP register ********************/
+#define USB_OTG_GRXSTSP_EPNUM 0x0000000FU /*!< IN EP interrupt mask bits */
+#define USB_OTG_GRXSTSP_BCNT 0x00007FF0U /*!< OUT EP interrupt mask bits */
+#define USB_OTG_GRXSTSP_DPID 0x00018000U /*!< OUT EP interrupt mask bits */
+#define USB_OTG_GRXSTSP_PKTSTS 0x001E0000U /*!< OUT EP interrupt mask bits */
+
+/******************** Bit definition forUSB_OTG_DAINTMSK register ********************/
+#define USB_OTG_DAINTMSK_IEPM 0x0000FFFFU /*!< IN EP interrupt mask bits */
+#define USB_OTG_DAINTMSK_OEPM 0xFFFF0000U /*!< OUT EP interrupt mask bits */
+
+/******************** Bit definition for OTG register ********************/
+
+#define USB_OTG_CHNUM 0x0000000FU /*!< Channel number */
+#define USB_OTG_CHNUM_0 0x00000001U /*!<Bit 0 */
+#define USB_OTG_CHNUM_1 0x00000002U /*!<Bit 1 */
+#define USB_OTG_CHNUM_2 0x00000004U /*!<Bit 2 */
+#define USB_OTG_CHNUM_3 0x00000008U /*!<Bit 3 */
+#define USB_OTG_BCNT 0x00007FF0U /*!< Byte count */
+
+#define USB_OTG_DPID 0x00018000U /*!< Data PID */
+#define USB_OTG_DPID_0 0x00008000U /*!<Bit 0 */
+#define USB_OTG_DPID_1 0x00010000U /*!<Bit 1 */
+
+#define USB_OTG_PKTSTS 0x001E0000U /*!< Packet status */
+#define USB_OTG_PKTSTS_0 0x00020000U /*!<Bit 0 */
+#define USB_OTG_PKTSTS_1 0x00040000U /*!<Bit 1 */
+#define USB_OTG_PKTSTS_2 0x00080000U /*!<Bit 2 */
+#define USB_OTG_PKTSTS_3 0x00100000U /*!<Bit 3 */
+
+#define USB_OTG_EPNUM 0x0000000FU /*!< Endpoint number */
+#define USB_OTG_EPNUM_0 0x00000001U /*!<Bit 0 */
+#define USB_OTG_EPNUM_1 0x00000002U /*!<Bit 1 */
+#define USB_OTG_EPNUM_2 0x00000004U /*!<Bit 2 */
+#define USB_OTG_EPNUM_3 0x00000008U /*!<Bit 3 */
+
+#define USB_OTG_FRMNUM 0x01E00000U /*!< Frame number */
+#define USB_OTG_FRMNUM_0 0x00200000U /*!<Bit 0 */
+#define USB_OTG_FRMNUM_1 0x00400000U /*!<Bit 1 */
+#define USB_OTG_FRMNUM_2 0x00800000U /*!<Bit 2 */
+#define USB_OTG_FRMNUM_3 0x01000000U /*!<Bit 3 */
+
+/******************** Bit definition for OTG register ********************/
+
+#define USB_OTG_CHNUM 0x0000000FU /*!< Channel number */
+#define USB_OTG_CHNUM_0 0x00000001U /*!<Bit 0 */
+#define USB_OTG_CHNUM_1 0x00000002U /*!<Bit 1 */
+#define USB_OTG_CHNUM_2 0x00000004U /*!<Bit 2 */
+#define USB_OTG_CHNUM_3 0x00000008U /*!<Bit 3 */
+#define USB_OTG_BCNT 0x00007FF0U /*!< Byte count */
+
+#define USB_OTG_DPID 0x00018000U /*!< Data PID */
+#define USB_OTG_DPID_0 0x00008000U /*!<Bit 0 */
+#define USB_OTG_DPID_1 0x00010000U /*!<Bit 1 */
+
+#define USB_OTG_PKTSTS 0x001E0000U /*!< Packet status */
+#define USB_OTG_PKTSTS_0 0x00020000U /*!<Bit 0 */
+#define USB_OTG_PKTSTS_1 0x00040000U /*!<Bit 1 */
+#define USB_OTG_PKTSTS_2 0x00080000U /*!<Bit 2 */
+#define USB_OTG_PKTSTS_3 0x00100000U /*!<Bit 3 */
+
+#define USB_OTG_EPNUM 0x0000000FU /*!< Endpoint number */
+#define USB_OTG_EPNUM_0 0x00000001U /*!<Bit 0 */
+#define USB_OTG_EPNUM_1 0x00000002U /*!<Bit 1 */
+#define USB_OTG_EPNUM_2 0x00000004U /*!<Bit 2 */
+#define USB_OTG_EPNUM_3 0x00000008U /*!<Bit 3 */
+
+#define USB_OTG_FRMNUM 0x01E00000U /*!< Frame number */
+#define USB_OTG_FRMNUM_0 0x00200000U /*!<Bit 0 */
+#define USB_OTG_FRMNUM_1 0x00400000U /*!<Bit 1 */
+#define USB_OTG_FRMNUM_2 0x00800000U /*!<Bit 2 */
+#define USB_OTG_FRMNUM_3 0x01000000U /*!<Bit 3 */
+
+/******************** Bit definition forUSB_OTG_GRXFSIZ register ********************/
+#define USB_OTG_GRXFSIZ_RXFD 0x0000FFFFU /*!< RxFIFO depth */
+
+/******************** Bit definition forUSB_OTG_DVBUSDIS register ********************/
+#define USB_OTG_DVBUSDIS_VBUSDT 0x0000FFFFU /*!< Device VBUS discharge time */
+
+/******************** Bit definition for OTG register ********************/
+#define USB_OTG_NPTXFSA 0x0000FFFFU /*!< Nonperiodic transmit RAM start address */
+#define USB_OTG_NPTXFD 0xFFFF0000U /*!< Nonperiodic TxFIFO depth */
+#define USB_OTG_TX0FSA 0x0000FFFFU /*!< Endpoint 0 transmit RAM start address */
+#define USB_OTG_TX0FD 0xFFFF0000U /*!< Endpoint 0 TxFIFO depth */
+
+/******************** Bit definition forUSB_OTG_DVBUSPULSE register ********************/
+#define USB_OTG_DVBUSPULSE_DVBUSP 0x00000FFFU /*!< Device VBUS pulsing time */
+
+/******************** Bit definition forUSB_OTG_GNPTXSTS register ********************/
+#define USB_OTG_GNPTXSTS_NPTXFSAV 0x0000FFFFU /*!< Nonperiodic TxFIFO space available */
+
+#define USB_OTG_GNPTXSTS_NPTQXSAV 0x00FF0000U /*!< Nonperiodic transmit request queue space available */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_0 0x00010000U /*!<Bit 0 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_1 0x00020000U /*!<Bit 1 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_2 0x00040000U /*!<Bit 2 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_3 0x00080000U /*!<Bit 3 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_4 0x00100000U /*!<Bit 4 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_5 0x00200000U /*!<Bit 5 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_6 0x00400000U /*!<Bit 6 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_7 0x00800000U /*!<Bit 7 */
+
+#define USB_OTG_GNPTXSTS_NPTXQTOP 0x7F000000U /*!< Top of the nonperiodic transmit request queue */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_0 0x01000000U /*!<Bit 0 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_1 0x02000000U /*!<Bit 1 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_2 0x04000000U /*!<Bit 2 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_3 0x08000000U /*!<Bit 3 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_4 0x10000000U /*!<Bit 4 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_5 0x20000000U /*!<Bit 5 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_6 0x40000000U /*!<Bit 6 */
+
+/******************** Bit definition forUSB_OTG_DTHRCTL register ********************/
+#define USB_OTG_DTHRCTL_NONISOTHREN 0x00000001U /*!< Nonisochronous IN endpoints threshold enable */
+#define USB_OTG_DTHRCTL_ISOTHREN 0x00000002U /*!< ISO IN endpoint threshold enable */
+
+#define USB_OTG_DTHRCTL_TXTHRLEN 0x000007FCU /*!< Transmit threshold length */
+#define USB_OTG_DTHRCTL_TXTHRLEN_0 0x00000004U /*!<Bit 0 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_1 0x00000008U /*!<Bit 1 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_2 0x00000010U /*!<Bit 2 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_3 0x00000020U /*!<Bit 3 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_4 0x00000040U /*!<Bit 4 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_5 0x00000080U /*!<Bit 5 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_6 0x00000100U /*!<Bit 6 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_7 0x00000200U /*!<Bit 7 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_8 0x00000400U /*!<Bit 8 */
+#define USB_OTG_DTHRCTL_RXTHREN 0x00010000U /*!< Receive threshold enable */
+
+#define USB_OTG_DTHRCTL_RXTHRLEN 0x03FE0000U /*!< Receive threshold length */
+#define USB_OTG_DTHRCTL_RXTHRLEN_0 0x00020000U /*!<Bit 0 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_1 0x00040000U /*!<Bit 1 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_2 0x00080000U /*!<Bit 2 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_3 0x00100000U /*!<Bit 3 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_4 0x00200000U /*!<Bit 4 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_5 0x00400000U /*!<Bit 5 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_6 0x00800000U /*!<Bit 6 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_7 0x01000000U /*!<Bit 7 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_8 0x02000000U /*!<Bit 8 */
+#define USB_OTG_DTHRCTL_ARPEN 0x08000000U /*!< Arbiter parking enable */
+
+/******************** Bit definition forUSB_OTG_DIEPEMPMSK register ********************/
+#define USB_OTG_DIEPEMPMSK_INEPTXFEM 0x0000FFFFU /*!< IN EP Tx FIFO empty interrupt mask bits */
+
+/******************** Bit definition forUSB_OTG_DEACHINT register ********************/
+#define USB_OTG_DEACHINT_IEP1INT 0x00000002U /*!< IN endpoint 1interrupt bit */
+#define USB_OTG_DEACHINT_OEP1INT 0x00020000U /*!< OUT endpoint 1 interrupt bit */
+
+/******************** Bit definition forUSB_OTG_GCCFG register ********************/
+#define USB_OTG_GCCFG_PWRDWN 0x00010000U /*!< Power down */
+#define USB_OTG_GCCFG_I2CPADEN 0x00020000U /*!< Enable I2C bus connection for the external I2C PHY interface */
+#define USB_OTG_GCCFG_VBUSASEN 0x00040000U /*!< Enable the VBUS sensing device */
+#define USB_OTG_GCCFG_VBUSBSEN 0x00080000U /*!< Enable the VBUS sensing device */
+#define USB_OTG_GCCFG_SOFOUTEN 0x00100000U /*!< SOF output enable */
+#define USB_OTG_GCCFG_NOVBUSSENS 0x00200000U /*!< VBUS sensing disable option */
+
+/******************** Bit definition forUSB_OTG_DEACHINTMSK register ********************/
+#define USB_OTG_DEACHINTMSK_IEP1INTM 0x00000002U /*!< IN Endpoint 1 interrupt mask bit */
+#define USB_OTG_DEACHINTMSK_OEP1INTM 0x00020000U /*!< OUT Endpoint 1 interrupt mask bit */
+
+/******************** Bit definition forUSB_OTG_CID register ********************/
+#define USB_OTG_CID_PRODUCT_ID 0xFFFFFFFFU /*!< Product ID field */
+
+/******************** Bit definition forUSB_OTG_DIEPEACHMSK1 register ********************/
+#define USB_OTG_DIEPEACHMSK1_XFRCM 0x00000001U /*!< Transfer completed interrupt mask */
+#define USB_OTG_DIEPEACHMSK1_EPDM 0x00000002U /*!< Endpoint disabled interrupt mask */
+#define USB_OTG_DIEPEACHMSK1_TOM 0x00000008U /*!< Timeout condition mask (nonisochronous endpoints) */
+#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK 0x00000010U /*!< IN token received when TxFIFO empty mask */
+#define USB_OTG_DIEPEACHMSK1_INEPNMM 0x00000020U /*!< IN token received with EP mismatch mask */
+#define USB_OTG_DIEPEACHMSK1_INEPNEM 0x00000040U /*!< IN endpoint NAK effective mask */
+#define USB_OTG_DIEPEACHMSK1_TXFURM 0x00000100U /*!< FIFO underrun mask */
+#define USB_OTG_DIEPEACHMSK1_BIM 0x00000200U /*!< BNA interrupt mask */
+#define USB_OTG_DIEPEACHMSK1_NAKM 0x00002000U /*!< NAK interrupt mask */
+
+/******************** Bit definition forUSB_OTG_HPRT register ********************/
+#define USB_OTG_HPRT_PCSTS 0x00000001U /*!< Port connect status */
+#define USB_OTG_HPRT_PCDET 0x00000002U /*!< Port connect detected */
+#define USB_OTG_HPRT_PENA 0x00000004U /*!< Port enable */
+#define USB_OTG_HPRT_PENCHNG 0x00000008U /*!< Port enable/disable change */
+#define USB_OTG_HPRT_POCA 0x00000010U /*!< Port overcurrent active */
+#define USB_OTG_HPRT_POCCHNG 0x00000020U /*!< Port overcurrent change */
+#define USB_OTG_HPRT_PRES 0x00000040U /*!< Port resume */
+#define USB_OTG_HPRT_PSUSP 0x00000080U /*!< Port suspend */
+#define USB_OTG_HPRT_PRST 0x00000100U /*!< Port reset */
+
+#define USB_OTG_HPRT_PLSTS 0x00000C00U /*!< Port line status */
+#define USB_OTG_HPRT_PLSTS_0 0x00000400U /*!<Bit 0 */
+#define USB_OTG_HPRT_PLSTS_1 0x00000800U /*!<Bit 1 */
+#define USB_OTG_HPRT_PPWR 0x00001000U /*!< Port power */
+
+#define USB_OTG_HPRT_PTCTL 0x0001E000U /*!< Port test control */
+#define USB_OTG_HPRT_PTCTL_0 0x00002000U /*!<Bit 0 */
+#define USB_OTG_HPRT_PTCTL_1 0x00004000U /*!<Bit 1 */
+#define USB_OTG_HPRT_PTCTL_2 0x00008000U /*!<Bit 2 */
+#define USB_OTG_HPRT_PTCTL_3 0x00010000U /*!<Bit 3 */
+
+#define USB_OTG_HPRT_PSPD 0x00060000U /*!< Port speed */
+#define USB_OTG_HPRT_PSPD_0 0x00020000U /*!<Bit 0 */
+#define USB_OTG_HPRT_PSPD_1 0x00040000U /*!<Bit 1 */
+
+/******************** Bit definition forUSB_OTG_DOEPEACHMSK1 register ********************/
+#define USB_OTG_DOEPEACHMSK1_XFRCM 0x00000001U /*!< Transfer completed interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_EPDM 0x00000002U /*!< Endpoint disabled interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_TOM 0x00000008U /*!< Timeout condition mask */
+#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK 0x00000010U /*!< IN token received when TxFIFO empty mask */
+#define USB_OTG_DOEPEACHMSK1_INEPNMM 0x00000020U /*!< IN token received with EP mismatch mask */
+#define USB_OTG_DOEPEACHMSK1_INEPNEM 0x00000040U /*!< IN endpoint NAK effective mask */
+#define USB_OTG_DOEPEACHMSK1_TXFURM 0x00000100U /*!< OUT packet error mask */
+#define USB_OTG_DOEPEACHMSK1_BIM 0x00000200U /*!< BNA interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_BERRM 0x00001000U /*!< Bubble error interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_NAKM 0x00002000U /*!< NAK interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_NYETM 0x00004000U /*!< NYET interrupt mask */
+
+/******************** Bit definition forUSB_OTG_HPTXFSIZ register ********************/
+#define USB_OTG_HPTXFSIZ_PTXSA 0x0000FFFFU /*!< Host periodic TxFIFO start address */
+#define USB_OTG_HPTXFSIZ_PTXFD 0xFFFF0000U /*!< Host periodic TxFIFO depth */
+
+/******************** Bit definition forUSB_OTG_DIEPCTL register ********************/
+#define USB_OTG_DIEPCTL_MPSIZ 0x000007FFU /*!< Maximum packet size */
+#define USB_OTG_DIEPCTL_USBAEP 0x00008000U /*!< USB active endpoint */
+#define USB_OTG_DIEPCTL_EONUM_DPID 0x00010000U /*!< Even/odd frame */
+#define USB_OTG_DIEPCTL_NAKSTS 0x00020000U /*!< NAK status */
+
+#define USB_OTG_DIEPCTL_EPTYP 0x000C0000U /*!< Endpoint type */
+#define USB_OTG_DIEPCTL_EPTYP_0 0x00040000U /*!<Bit 0 */
+#define USB_OTG_DIEPCTL_EPTYP_1 0x00080000U /*!<Bit 1 */
+#define USB_OTG_DIEPCTL_STALL 0x00200000U /*!< STALL handshake */
+
+#define USB_OTG_DIEPCTL_TXFNUM 0x03C00000U /*!< TxFIFO number */
+#define USB_OTG_DIEPCTL_TXFNUM_0 0x00400000U /*!<Bit 0 */
+#define USB_OTG_DIEPCTL_TXFNUM_1 0x00800000U /*!<Bit 1 */
+#define USB_OTG_DIEPCTL_TXFNUM_2 0x01000000U /*!<Bit 2 */
+#define USB_OTG_DIEPCTL_TXFNUM_3 0x02000000U /*!<Bit 3 */
+#define USB_OTG_DIEPCTL_CNAK 0x04000000U /*!< Clear NAK */
+#define USB_OTG_DIEPCTL_SNAK 0x08000000U /*!< Set NAK */
+#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM 0x10000000U /*!< Set DATA0 PID */
+#define USB_OTG_DIEPCTL_SODDFRM 0x20000000U /*!< Set odd frame */
+#define USB_OTG_DIEPCTL_EPDIS 0x40000000U /*!< Endpoint disable */
+#define USB_OTG_DIEPCTL_EPENA 0x80000000U /*!< Endpoint enable */
+
+/******************** Bit definition forUSB_OTG_HCCHAR register ********************/
+#define USB_OTG_HCCHAR_MPSIZ 0x000007FFU /*!< Maximum packet size */
+
+#define USB_OTG_HCCHAR_EPNUM 0x00007800U /*!< Endpoint number */
+#define USB_OTG_HCCHAR_EPNUM_0 0x00000800U /*!<Bit 0 */
+#define USB_OTG_HCCHAR_EPNUM_1 0x00001000U /*!<Bit 1 */
+#define USB_OTG_HCCHAR_EPNUM_2 0x00002000U /*!<Bit 2 */
+#define USB_OTG_HCCHAR_EPNUM_3 0x00004000U /*!<Bit 3 */
+#define USB_OTG_HCCHAR_EPDIR 0x00008000U /*!< Endpoint direction */
+#define USB_OTG_HCCHAR_LSDEV 0x00020000U /*!< Low-speed device */
+
+#define USB_OTG_HCCHAR_EPTYP 0x000C0000U /*!< Endpoint type */
+#define USB_OTG_HCCHAR_EPTYP_0 0x00040000U /*!<Bit 0 */
+#define USB_OTG_HCCHAR_EPTYP_1 0x00080000U /*!<Bit 1 */
+
+#define USB_OTG_HCCHAR_MC 0x00300000U /*!< Multi Count (MC) / Error Count (EC) */
+#define USB_OTG_HCCHAR_MC_0 0x00100000U /*!<Bit 0 */
+#define USB_OTG_HCCHAR_MC_1 0x00200000U /*!<Bit 1 */
+
+#define USB_OTG_HCCHAR_DAD 0x1FC00000U /*!< Device address */
+#define USB_OTG_HCCHAR_DAD_0 0x00400000U /*!<Bit 0 */
+#define USB_OTG_HCCHAR_DAD_1 0x00800000U /*!<Bit 1 */
+#define USB_OTG_HCCHAR_DAD_2 0x01000000U /*!<Bit 2 */
+#define USB_OTG_HCCHAR_DAD_3 0x02000000U /*!<Bit 3 */
+#define USB_OTG_HCCHAR_DAD_4 0x04000000U /*!<Bit 4 */
+#define USB_OTG_HCCHAR_DAD_5 0x08000000U /*!<Bit 5 */
+#define USB_OTG_HCCHAR_DAD_6 0x10000000U /*!<Bit 6 */
+#define USB_OTG_HCCHAR_ODDFRM 0x20000000U /*!< Odd frame */
+#define USB_OTG_HCCHAR_CHDIS 0x40000000U /*!< Channel disable */
+#define USB_OTG_HCCHAR_CHENA 0x80000000U /*!< Channel enable */
+
+/******************** Bit definition forUSB_OTG_HCSPLT register ********************/
+
+#define USB_OTG_HCSPLT_PRTADDR 0x0000007FU /*!< Port address */
+#define USB_OTG_HCSPLT_PRTADDR_0 0x00000001U /*!<Bit 0 */
+#define USB_OTG_HCSPLT_PRTADDR_1 0x00000002U /*!<Bit 1 */
+#define USB_OTG_HCSPLT_PRTADDR_2 0x00000004U /*!<Bit 2 */
+#define USB_OTG_HCSPLT_PRTADDR_3 0x00000008U /*!<Bit 3 */
+#define USB_OTG_HCSPLT_PRTADDR_4 0x00000010U /*!<Bit 4 */
+#define USB_OTG_HCSPLT_PRTADDR_5 0x00000020U /*!<Bit 5 */
+#define USB_OTG_HCSPLT_PRTADDR_6 0x00000040U /*!<Bit 6 */
+
+#define USB_OTG_HCSPLT_HUBADDR 0x00003F80U /*!< Hub address */
+#define USB_OTG_HCSPLT_HUBADDR_0 0x00000080U /*!<Bit 0 */
+#define USB_OTG_HCSPLT_HUBADDR_1 0x00000100U /*!<Bit 1 */
+#define USB_OTG_HCSPLT_HUBADDR_2 0x00000200U /*!<Bit 2 */
+#define USB_OTG_HCSPLT_HUBADDR_3 0x00000400U /*!<Bit 3 */
+#define USB_OTG_HCSPLT_HUBADDR_4 0x00000800U /*!<Bit 4 */
+#define USB_OTG_HCSPLT_HUBADDR_5 0x00001000U /*!<Bit 5 */
+#define USB_OTG_HCSPLT_HUBADDR_6 0x00002000U /*!<Bit 6 */
+
+#define USB_OTG_HCSPLT_XACTPOS 0x0000C000U /*!< XACTPOS */
+#define USB_OTG_HCSPLT_XACTPOS_0 0x00004000U /*!<Bit 0 */
+#define USB_OTG_HCSPLT_XACTPOS_1 0x00008000U /*!<Bit 1 */
+#define USB_OTG_HCSPLT_COMPLSPLT 0x00010000U /*!< Do complete split */
+#define USB_OTG_HCSPLT_SPLITEN 0x80000000U /*!< Split enable */
+
+/******************** Bit definition forUSB_OTG_HCINT register ********************/
+#define USB_OTG_HCINT_XFRC 0x00000001U /*!< Transfer completed */
+#define USB_OTG_HCINT_CHH 0x00000002U /*!< Channel halted */
+#define USB_OTG_HCINT_AHBERR 0x00000004U /*!< AHB error */
+#define USB_OTG_HCINT_STALL 0x00000008U /*!< STALL response received interrupt */
+#define USB_OTG_HCINT_NAK 0x00000010U /*!< NAK response received interrupt */
+#define USB_OTG_HCINT_ACK 0x00000020U /*!< ACK response received/transmitted interrupt */
+#define USB_OTG_HCINT_NYET 0x00000040U /*!< Response received interrupt */
+#define USB_OTG_HCINT_TXERR 0x00000080U /*!< Transaction error */
+#define USB_OTG_HCINT_BBERR 0x00000100U /*!< Babble error */
+#define USB_OTG_HCINT_FRMOR 0x00000200U /*!< Frame overrun */
+#define USB_OTG_HCINT_DTERR 0x00000400U /*!< Data toggle error */
+
+/******************** Bit definition forUSB_OTG_DIEPINT register ********************/
+#define USB_OTG_DIEPINT_XFRC 0x00000001U /*!< Transfer completed interrupt */
+#define USB_OTG_DIEPINT_EPDISD 0x00000002U /*!< Endpoint disabled interrupt */
+#define USB_OTG_DIEPINT_TOC 0x00000008U /*!< Timeout condition */
+#define USB_OTG_DIEPINT_ITTXFE 0x00000010U /*!< IN token received when TxFIFO is empty */
+#define USB_OTG_DIEPINT_INEPNE 0x00000040U /*!< IN endpoint NAK effective */
+#define USB_OTG_DIEPINT_TXFE 0x00000080U /*!< Transmit FIFO empty */
+#define USB_OTG_DIEPINT_TXFIFOUDRN 0x00000100U /*!< Transmit Fifo Underrun */
+#define USB_OTG_DIEPINT_BNA 0x00000200U /*!< Buffer not available interrupt */
+#define USB_OTG_DIEPINT_PKTDRPSTS 0x00000800U /*!< Packet dropped status */
+#define USB_OTG_DIEPINT_BERR 0x00001000U /*!< Babble error interrupt */
+#define USB_OTG_DIEPINT_NAK 0x00002000U /*!< NAK interrupt */
+
+/******************** Bit definition forUSB_OTG_HCINTMSK register ********************/
+#define USB_OTG_HCINTMSK_XFRCM 0x00000001U /*!< Transfer completed mask */
+#define USB_OTG_HCINTMSK_CHHM 0x00000002U /*!< Channel halted mask */
+#define USB_OTG_HCINTMSK_AHBERR 0x00000004U /*!< AHB error */
+#define USB_OTG_HCINTMSK_STALLM 0x00000008U /*!< STALL response received interrupt mask */
+#define USB_OTG_HCINTMSK_NAKM 0x00000010U /*!< NAK response received interrupt mask */
+#define USB_OTG_HCINTMSK_ACKM 0x00000020U /*!< ACK response received/transmitted interrupt mask */
+#define USB_OTG_HCINTMSK_NYET 0x00000040U /*!< response received interrupt mask */
+#define USB_OTG_HCINTMSK_TXERRM 0x00000080U /*!< Transaction error mask */
+#define USB_OTG_HCINTMSK_BBERRM 0x00000100U /*!< Babble error mask */
+#define USB_OTG_HCINTMSK_FRMORM 0x00000200U /*!< Frame overrun mask */
+#define USB_OTG_HCINTMSK_DTERRM 0x00000400U /*!< Data toggle error mask */
+
+/******************** Bit definition for USB_OTG_DIEPTSIZ register ********************/
+
+#define USB_OTG_DIEPTSIZ_XFRSIZ 0x0007FFFFU /*!< Transfer size */
+#define USB_OTG_DIEPTSIZ_PKTCNT 0x1FF80000U /*!< Packet count */
+#define USB_OTG_DIEPTSIZ_MULCNT 0x60000000U /*!< Packet count */
+/******************** Bit definition forUSB_OTG_HCTSIZ register ********************/
+#define USB_OTG_HCTSIZ_XFRSIZ 0x0007FFFFU /*!< Transfer size */
+#define USB_OTG_HCTSIZ_PKTCNT 0x1FF80000U /*!< Packet count */
+#define USB_OTG_HCTSIZ_DOPING 0x80000000U /*!< Do PING */
+#define USB_OTG_HCTSIZ_DPID 0x60000000U /*!< Data PID */
+#define USB_OTG_HCTSIZ_DPID_0 0x20000000U /*!<Bit 0 */
+#define USB_OTG_HCTSIZ_DPID_1 0x40000000U /*!<Bit 1 */
+
+/******************** Bit definition forUSB_OTG_DIEPDMA register ********************/
+#define USB_OTG_DIEPDMA_DMAADDR 0xFFFFFFFFU /*!< DMA address */
+
+/******************** Bit definition forUSB_OTG_HCDMA register ********************/
+#define USB_OTG_HCDMA_DMAADDR 0xFFFFFFFFU /*!< DMA address */
+
+/******************** Bit definition forUSB_OTG_DTXFSTS register ********************/
+#define USB_OTG_DTXFSTS_INEPTFSAV 0x0000FFFFU /*!< IN endpoint TxFIFO space available */
+
+/******************** Bit definition forUSB_OTG_DIEPTXF register ********************/
+#define USB_OTG_DIEPTXF_INEPTXSA 0x0000FFFFU /*!< IN endpoint FIFOx transmit RAM start address */
+#define USB_OTG_DIEPTXF_INEPTXFD 0xFFFF0000U /*!< IN endpoint TxFIFO depth */
+
+/******************** Bit definition forUSB_OTG_DOEPCTL register ********************/
+
+#define USB_OTG_DOEPCTL_MPSIZ 0x000007FFU /*!< Maximum packet size */ /*!<Bit 1 */
+#define USB_OTG_DOEPCTL_USBAEP 0x00008000U /*!< USB active endpoint */
+#define USB_OTG_DOEPCTL_NAKSTS 0x00020000U /*!< NAK status */
+#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM 0x10000000U /*!< Set DATA0 PID */
+#define USB_OTG_DOEPCTL_SODDFRM 0x20000000U /*!< Set odd frame */
+#define USB_OTG_DOEPCTL_EPTYP 0x000C0000U /*!< Endpoint type */
+#define USB_OTG_DOEPCTL_EPTYP_0 0x00040000U /*!<Bit 0 */
+#define USB_OTG_DOEPCTL_EPTYP_1 0x00080000U /*!<Bit 1 */
+#define USB_OTG_DOEPCTL_SNPM 0x00100000U /*!< Snoop mode */
+#define USB_OTG_DOEPCTL_STALL 0x00200000U /*!< STALL handshake */
+#define USB_OTG_DOEPCTL_CNAK 0x04000000U /*!< Clear NAK */
+#define USB_OTG_DOEPCTL_SNAK 0x08000000U /*!< Set NAK */
+#define USB_OTG_DOEPCTL_EPDIS 0x40000000U /*!< Endpoint disable */
+#define USB_OTG_DOEPCTL_EPENA 0x80000000U /*!< Endpoint enable */
+
+/******************** Bit definition forUSB_OTG_DOEPINT register ********************/
+#define USB_OTG_DOEPINT_XFRC 0x00000001U /*!< Transfer completed interrupt */
+#define USB_OTG_DOEPINT_EPDISD 0x00000002U /*!< Endpoint disabled interrupt */
+#define USB_OTG_DOEPINT_STUP 0x00000008U /*!< SETUP phase done */
+#define USB_OTG_DOEPINT_OTEPDIS 0x00000010U /*!< OUT token received when endpoint disabled */
+#define USB_OTG_DOEPINT_B2BSTUP 0x00000040U /*!< Back-to-back SETUP packets received */
+#define USB_OTG_DOEPINT_NYET 0x00004000U /*!< NYET interrupt */
+
+/******************** Bit definition forUSB_OTG_DOEPTSIZ register ********************/
+
+#define USB_OTG_DOEPTSIZ_XFRSIZ 0x0007FFFFU /*!< Transfer size */
+#define USB_OTG_DOEPTSIZ_PKTCNT 0x1FF80000U /*!< Packet count */
+
+#define USB_OTG_DOEPTSIZ_STUPCNT 0x60000000U /*!< SETUP packet count */
+#define USB_OTG_DOEPTSIZ_STUPCNT_0 0x20000000U /*!<Bit 0 */
+#define USB_OTG_DOEPTSIZ_STUPCNT_1 0x40000000U /*!<Bit 1 */
+
+/******************** Bit definition for PCGCCTL register ********************/
+#define USB_OTG_PCGCCTL_STOPCLK 0x00000001U /*!< SETUP packet count */
+#define USB_OTG_PCGCCTL_GATECLK 0x00000002U /*!<Bit 0 */
+#define USB_OTG_PCGCCTL_PHYSUSP 0x00000010U /*!<Bit 1 */
+
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup Exported_macros
+ * @{
+ */
+
+/******************************* ADC Instances ********************************/
+#define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) || \
+ ((INSTANCE) == ADC2) || \
+ ((INSTANCE) == ADC3))
+
+/******************************* CAN Instances ********************************/
+#define IS_CAN_ALL_INSTANCE(INSTANCE) (((INSTANCE) == CAN1) || \
+ ((INSTANCE) == CAN2))
+
+/******************************* CRC Instances ********************************/
+#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
+
+/******************************* DAC Instances ********************************/
+#define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC)
+
+/******************************* DCMI Instances *******************************/
+#define IS_DCMI_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DCMI)
+
+/******************************* DMA2D Instances *******************************/
+#define IS_DMA2D_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DMA2D)
+
+/******************************** DMA Instances *******************************/
+#define IS_DMA_STREAM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0) || \
+ ((INSTANCE) == DMA1_Stream1) || \
+ ((INSTANCE) == DMA1_Stream2) || \
+ ((INSTANCE) == DMA1_Stream3) || \
+ ((INSTANCE) == DMA1_Stream4) || \
+ ((INSTANCE) == DMA1_Stream5) || \
+ ((INSTANCE) == DMA1_Stream6) || \
+ ((INSTANCE) == DMA1_Stream7) || \
+ ((INSTANCE) == DMA2_Stream0) || \
+ ((INSTANCE) == DMA2_Stream1) || \
+ ((INSTANCE) == DMA2_Stream2) || \
+ ((INSTANCE) == DMA2_Stream3) || \
+ ((INSTANCE) == DMA2_Stream4) || \
+ ((INSTANCE) == DMA2_Stream5) || \
+ ((INSTANCE) == DMA2_Stream6) || \
+ ((INSTANCE) == DMA2_Stream7))
+
+/******************************* GPIO Instances *******************************/
+#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
+ ((INSTANCE) == GPIOB) || \
+ ((INSTANCE) == GPIOC) || \
+ ((INSTANCE) == GPIOD) || \
+ ((INSTANCE) == GPIOE) || \
+ ((INSTANCE) == GPIOF) || \
+ ((INSTANCE) == GPIOG) || \
+ ((INSTANCE) == GPIOH) || \
+ ((INSTANCE) == GPIOI) || \
+ ((INSTANCE) == GPIOJ) || \
+ ((INSTANCE) == GPIOK))
+
+/******************************** I2C Instances *******************************/
+#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
+ ((INSTANCE) == I2C2) || \
+ ((INSTANCE) == I2C3))
+
+/******************************** I2S Instances *******************************/
+#define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI2) || \
+ ((INSTANCE) == SPI3))
+
+/*************************** I2S Extended Instances ***************************/
+#define IS_I2S_ALL_INSTANCE_EXT(PERIPH) (((INSTANCE) == SPI2) || \
+ ((INSTANCE) == SPI3) || \
+ ((INSTANCE) == I2S2ext) || \
+ ((INSTANCE) == I2S3ext))
+
+/****************************** LTDC Instances ********************************/
+#define IS_LTDC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == LTDC)
+
+/******************************* RNG Instances ********************************/
+#define IS_RNG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RNG)
+
+/****************************** RTC Instances *********************************/
+#define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
+
+/******************************* SAI Instances ********************************/
+#define IS_SAI_ALL_INSTANCE(PERIPH) (((PERIPH) == SAI1_Block_A) || \
+ ((PERIPH) == SAI1_Block_B))
+/* Legacy define */
+#define IS_SAI_BLOCK_PERIPH IS_SAI_ALL_INSTANCE
+
+/******************************** SPI Instances *******************************/
+#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
+ ((INSTANCE) == SPI2) || \
+ ((INSTANCE) == SPI3) || \
+ ((INSTANCE) == SPI4) || \
+ ((INSTANCE) == SPI5) || \
+ ((INSTANCE) == SPI6))
+
+/*************************** SPI Extended Instances ***************************/
+#define IS_SPI_ALL_INSTANCE_EXT(INSTANCE) (((INSTANCE) == SPI1) || \
+ ((INSTANCE) == SPI2) || \
+ ((INSTANCE) == SPI3) || \
+ ((INSTANCE) == SPI4) || \
+ ((INSTANCE) == SPI5) || \
+ ((INSTANCE) == SPI6) || \
+ ((INSTANCE) == I2S2ext) || \
+ ((INSTANCE) == I2S3ext))
+
+/****************** TIM Instances : All supported instances *******************/
+#define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM6) || \
+ ((INSTANCE) == TIM7) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM9) || \
+ ((INSTANCE) == TIM10) || \
+ ((INSTANCE) == TIM11) || \
+ ((INSTANCE) == TIM12) || \
+ ((INSTANCE) == TIM13) || \
+ ((INSTANCE) == TIM14))
+
+/************* TIM Instances : at least 1 capture/compare channel *************/
+#define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM9) || \
+ ((INSTANCE) == TIM10) || \
+ ((INSTANCE) == TIM11) || \
+ ((INSTANCE) == TIM12) || \
+ ((INSTANCE) == TIM13) || \
+ ((INSTANCE) == TIM14))
+
+/************ TIM Instances : at least 2 capture/compare channels *************/
+#define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM9) || \
+ ((INSTANCE) == TIM12))
+
+/************ TIM Instances : at least 3 capture/compare channels *************/
+#define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8))
+
+/************ TIM Instances : at least 4 capture/compare channels *************/
+#define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8))
+
+/******************** TIM Instances : Advanced-control timers *****************/
+#define IS_TIM_ADVANCED_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM8))
+
+/******************* TIM Instances : Timer input XOR function *****************/
+#define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8))
+
+/****************** TIM Instances : DMA requests generation (UDE) *************/
+#define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM6) || \
+ ((INSTANCE) == TIM7) || \
+ ((INSTANCE) == TIM8))
+
+/************ TIM Instances : DMA requests generation (CCxDE) *****************/
+#define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8))
+
+/************ TIM Instances : DMA requests generation (COMDE) *****************/
+#define IS_TIM_CCDMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8))
+
+/******************** TIM Instances : DMA burst feature ***********************/
+#define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8))
+
+/****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/
+#define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM6) || \
+ ((INSTANCE) == TIM7) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM9) || \
+ ((INSTANCE) == TIM12))
+
+/*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
+#define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM9) || \
+ ((INSTANCE) == TIM12))
+
+/********************** TIM Instances : 32 bit Counter ************************/
+#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)(((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM5))
+
+/***************** TIM Instances : external trigger input availabe ************/
+#define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8))
+
+/****************** TIM Instances : remapping capability **********************/
+#define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM11))
+
+/******************* TIM Instances : output(s) available **********************/
+#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
+ ((((INSTANCE) == TIM1) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM2) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM3) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM4) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM5) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM8) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM9) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2))) \
+ || \
+ (((INSTANCE) == TIM10) && \
+ (((CHANNEL) == TIM_CHANNEL_1))) \
+ || \
+ (((INSTANCE) == TIM11) && \
+ (((CHANNEL) == TIM_CHANNEL_1))) \
+ || \
+ (((INSTANCE) == TIM12) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2))) \
+ || \
+ (((INSTANCE) == TIM13) && \
+ (((CHANNEL) == TIM_CHANNEL_1))) \
+ || \
+ (((INSTANCE) == TIM14) && \
+ (((CHANNEL) == TIM_CHANNEL_1))))
+
+/************ TIM Instances : complementary output(s) available ***************/
+#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
+ ((((INSTANCE) == TIM1) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3))) \
+ || \
+ (((INSTANCE) == TIM8) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3))))
+
+/******************** USART Instances : Synchronous mode **********************/
+#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3) || \
+ ((INSTANCE) == USART6))
+
+/******************** UART Instances : Asynchronous mode **********************/
+#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3) || \
+ ((INSTANCE) == UART4) || \
+ ((INSTANCE) == UART5) || \
+ ((INSTANCE) == USART6) || \
+ ((INSTANCE) == UART7) || \
+ ((INSTANCE) == UART8))
+
+/****************** UART Instances : Hardware Flow control ********************/
+#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3) || \
+ ((INSTANCE) == USART6))
+
+/********************* UART Instances : Smard card mode ***********************/
+#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3) || \
+ ((INSTANCE) == USART6))
+
+/*********************** UART Instances : IRDA mode ***************************/
+#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3) || \
+ ((INSTANCE) == UART4) || \
+ ((INSTANCE) == UART5) || \
+ ((INSTANCE) == USART6) || \
+ ((INSTANCE) == UART7) || \
+ ((INSTANCE) == UART8))
+
+/*********************** PCD Instances ****************************************/
+#define IS_PCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS) || \
+ ((INSTANCE) == USB_OTG_HS))
+
+/*********************** HCD Instances ****************************************/
+#define IS_HCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS) || \
+ ((INSTANCE) == USB_OTG_HS))
+
+/****************************** IWDG Instances ********************************/
+#define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
+
+/****************************** WWDG Instances ********************************/
+#define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
+
+/****************************** SDIO Instances ********************************/
+#define IS_SDIO_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SDIO)
+
+/****************************** USB Exported Constants ************************/
+#define USB_OTG_FS_HOST_MAX_CHANNEL_NBR 8U
+#define USB_OTG_FS_MAX_IN_ENDPOINTS 4U /* Including EP0 */
+#define USB_OTG_FS_MAX_OUT_ENDPOINTS 4U /* Including EP0 */
+#define USB_OTG_FS_TOTAL_FIFO_SIZE 1280U /* in Bytes */
+
+#define USB_OTG_HS_HOST_MAX_CHANNEL_NBR 12U
+#define USB_OTG_HS_MAX_IN_ENDPOINTS 6U /* Including EP0 */
+#define USB_OTG_HS_MAX_OUT_ENDPOINTS 6U /* Including EP0 */
+#define USB_OTG_HS_TOTAL_FIFO_SIZE 4096U /* in Bytes */
+
+/******************************************************************************/
+/* For a painless codes migration between the STM32F4xx device product */
+/* lines, the aliases defined below are put in place to overcome the */
+/* differences in the interrupt handlers and IRQn definitions. */
+/* No need to update developed interrupt code when moving across */
+/* product lines within the same STM32F4 Family */
+/******************************************************************************/
+
+/* Aliases for __IRQn */
+#define FSMC_IRQn FMC_IRQn
+
+/* Aliases for __IRQHandler */
+#define FSMC_IRQHandler FMC_IRQHandler
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* __STM32F439xx_H */
+
+
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Device/ST/STM32F4xx/Include/stm32f446xx.h b/Device/ST/STM32F4xx/Include/stm32f446xx.h
new file mode 100644
index 0000000..d5041a5
--- /dev/null
+++ b/Device/ST/STM32F4xx/Include/stm32f446xx.h
@@ -0,0 +1,8301 @@
+/**
+ ******************************************************************************
+ * @file stm32f446xx.h
+ * @author MCD Application Team
+ * @version V2.5.0
+ * @date 22-April-2016
+ * @brief CMSIS STM32F446xx Device Peripheral Access Layer Header File.
+ *
+ * This file contains:
+ * - Data structures and the address mapping for all peripherals
+ * - peripherals registers declarations and bits definition
+ * - Macros to access peripheral’s registers hardware
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/** @addtogroup CMSIS_Device
+ * @{
+ */
+
+/** @addtogroup stm32f446xx
+ * @{
+ */
+
+#ifndef __STM32F446xx_H
+#define __STM32F446xx_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif /* __cplusplus */
+
+/** @addtogroup Configuration_section_for_CMSIS
+ * @{
+ */
+
+/**
+ * @brief Configuration of the Cortex-M4 Processor and Core Peripherals
+ */
+#define __CM4_REV 0x0001U /*!< Core revision r0p1 */
+#define __MPU_PRESENT 1U /*!< STM32F4XX provides an MPU */
+#define __NVIC_PRIO_BITS 4U /*!< STM32F4XX uses 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */
+#define __FPU_PRESENT 1U /*!< FPU present */
+
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_interrupt_number_definition
+ * @{
+ */
+
+/**
+ * @brief STM32F4XX Interrupt Number Definition, according to the selected device
+ * in @ref Library_configuration_section
+ */
+typedef enum
+{
+/****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/
+ NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
+ MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */
+ BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */
+ UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */
+ SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */
+ DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */
+ PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */
+ SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */
+/****** STM32 specific Interrupt Numbers **********************************************************************/
+ WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
+ PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */
+ TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */
+ RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */
+ FLASH_IRQn = 4, /*!< FLASH global Interrupt */
+ RCC_IRQn = 5, /*!< RCC global Interrupt */
+ EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */
+ EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */
+ EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */
+ EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */
+ EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */
+ DMA1_Stream0_IRQn = 11, /*!< DMA1 Stream 0 global Interrupt */
+ DMA1_Stream1_IRQn = 12, /*!< DMA1 Stream 1 global Interrupt */
+ DMA1_Stream2_IRQn = 13, /*!< DMA1 Stream 2 global Interrupt */
+ DMA1_Stream3_IRQn = 14, /*!< DMA1 Stream 3 global Interrupt */
+ DMA1_Stream4_IRQn = 15, /*!< DMA1 Stream 4 global Interrupt */
+ DMA1_Stream5_IRQn = 16, /*!< DMA1 Stream 5 global Interrupt */
+ DMA1_Stream6_IRQn = 17, /*!< DMA1 Stream 6 global Interrupt */
+ ADC_IRQn = 18, /*!< ADC1, ADC2 and ADC3 global Interrupts */
+ CAN1_TX_IRQn = 19, /*!< CAN1 TX Interrupt */
+ CAN1_RX0_IRQn = 20, /*!< CAN1 RX0 Interrupt */
+ CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */
+ CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */
+ EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
+ TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break interrupt and TIM9 global interrupt */
+ TIM1_UP_TIM10_IRQn = 25, /*!< TIM1 Update Interrupt and TIM10 global interrupt */
+ TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */
+ TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
+ TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
+ TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
+ TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
+ I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
+ I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
+ I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
+ I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
+ SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
+ SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
+ USART1_IRQn = 37, /*!< USART1 global Interrupt */
+ USART2_IRQn = 38, /*!< USART2 global Interrupt */
+ USART3_IRQn = 39, /*!< USART3 global Interrupt */
+ EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
+ RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */
+ OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS Wakeup through EXTI line interrupt */
+ TIM8_BRK_TIM12_IRQn = 43, /*!< TIM8 Break Interrupt and TIM12 global interrupt */
+ TIM8_UP_TIM13_IRQn = 44, /*!< TIM8 Update Interrupt and TIM13 global interrupt */
+ TIM8_TRG_COM_TIM14_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */
+ TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare global interrupt */
+ DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */
+ FMC_IRQn = 48, /*!< FMC global Interrupt */
+ SDIO_IRQn = 49, /*!< SDIO global Interrupt */
+ TIM5_IRQn = 50, /*!< TIM5 global Interrupt */
+ SPI3_IRQn = 51, /*!< SPI3 global Interrupt */
+ UART4_IRQn = 52, /*!< UART4 global Interrupt */
+ UART5_IRQn = 53, /*!< UART5 global Interrupt */
+ TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC1&2 underrun error interrupts */
+ TIM7_IRQn = 55, /*!< TIM7 global interrupt */
+ DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */
+ DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */
+ DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */
+ DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */
+ DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */
+ CAN2_TX_IRQn = 63, /*!< CAN2 TX Interrupt */
+ CAN2_RX0_IRQn = 64, /*!< CAN2 RX0 Interrupt */
+ CAN2_RX1_IRQn = 65, /*!< CAN2 RX1 Interrupt */
+ CAN2_SCE_IRQn = 66, /*!< CAN2 SCE Interrupt */
+ OTG_FS_IRQn = 67, /*!< USB OTG FS global Interrupt */
+ DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */
+ DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */
+ DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */
+ USART6_IRQn = 71, /*!< USART6 global interrupt */
+ I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */
+ I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */
+ OTG_HS_EP1_OUT_IRQn = 74, /*!< USB OTG HS End Point 1 Out global interrupt */
+ OTG_HS_EP1_IN_IRQn = 75, /*!< USB OTG HS End Point 1 In global interrupt */
+ OTG_HS_WKUP_IRQn = 76, /*!< USB OTG HS Wakeup through EXTI interrupt */
+ OTG_HS_IRQn = 77, /*!< USB OTG HS global interrupt */
+ DCMI_IRQn = 78, /*!< DCMI global interrupt */
+ FPU_IRQn = 81, /*!< FPU global interrupt */
+ SPI4_IRQn = 84, /*!< SPI4 global Interrupt */
+ SAI1_IRQn = 87, /*!< SAI1 global Interrupt */
+ SAI2_IRQn = 91, /*!< SAI2 global Interrupt */
+ QUADSPI_IRQn = 92, /*!< QuadSPI global Interrupt */
+ CEC_IRQn = 93, /*!< CEC global Interrupt */
+ SPDIF_RX_IRQn = 94, /*!< SPDIF-RX global Interrupt */
+ FMPI2C1_EV_IRQn = 95, /*!< FMPI2C1 Event Interrupt */
+ FMPI2C1_ER_IRQn = 96 /*!< FMPI2C1 Error Interrupt */
+} IRQn_Type;
+
+/**
+ * @}
+ */
+
+#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
+#include "system_stm32f4xx.h"
+#include <stdint.h>
+
+/** @addtogroup Peripheral_registers_structures
+ * @{
+ */
+
+/**
+ * @brief Analog to Digital Converter
+ */
+
+typedef struct
+{
+ __IO uint32_t SR; /*!< ADC status register, Address offset: 0x00 */
+ __IO uint32_t CR1; /*!< ADC control register 1, Address offset: 0x04 */
+ __IO uint32_t CR2; /*!< ADC control register 2, Address offset: 0x08 */
+ __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x0C */
+ __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x10 */
+ __IO uint32_t JOFR1; /*!< ADC injected channel data offset register 1, Address offset: 0x14 */
+ __IO uint32_t JOFR2; /*!< ADC injected channel data offset register 2, Address offset: 0x18 */
+ __IO uint32_t JOFR3; /*!< ADC injected channel data offset register 3, Address offset: 0x1C */
+ __IO uint32_t JOFR4; /*!< ADC injected channel data offset register 4, Address offset: 0x20 */
+ __IO uint32_t HTR; /*!< ADC watchdog higher threshold register, Address offset: 0x24 */
+ __IO uint32_t LTR; /*!< ADC watchdog lower threshold register, Address offset: 0x28 */
+ __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x2C */
+ __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x30 */
+ __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x34 */
+ __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x38*/
+ __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x3C */
+ __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x40 */
+ __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x44 */
+ __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x48 */
+ __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x4C */
+} ADC_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1 base address + 0x300 */
+ __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1 base address + 0x304 */
+ __IO uint32_t CDR; /*!< ADC common regular data register for dual
+ AND triple modes, Address offset: ADC1 base address + 0x308 */
+} ADC_Common_TypeDef;
+
+
+/**
+ * @brief Controller Area Network TxMailBox
+ */
+
+typedef struct
+{
+ __IO uint32_t TIR; /*!< CAN TX mailbox identifier register */
+ __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */
+ __IO uint32_t TDLR; /*!< CAN mailbox data low register */
+ __IO uint32_t TDHR; /*!< CAN mailbox data high register */
+} CAN_TxMailBox_TypeDef;
+
+/**
+ * @brief Controller Area Network FIFOMailBox
+ */
+
+typedef struct
+{
+ __IO uint32_t RIR; /*!< CAN receive FIFO mailbox identifier register */
+ __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */
+ __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */
+ __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */
+} CAN_FIFOMailBox_TypeDef;
+
+/**
+ * @brief Controller Area Network FilterRegister
+ */
+
+typedef struct
+{
+ __IO uint32_t FR1; /*!< CAN Filter bank register 1 */
+ __IO uint32_t FR2; /*!< CAN Filter bank register 1 */
+} CAN_FilterRegister_TypeDef;
+
+/**
+ * @brief Controller Area Network
+ */
+
+typedef struct
+{
+ __IO uint32_t MCR; /*!< CAN master control register, Address offset: 0x00 */
+ __IO uint32_t MSR; /*!< CAN master status register, Address offset: 0x04 */
+ __IO uint32_t TSR; /*!< CAN transmit status register, Address offset: 0x08 */
+ __IO uint32_t RF0R; /*!< CAN receive FIFO 0 register, Address offset: 0x0C */
+ __IO uint32_t RF1R; /*!< CAN receive FIFO 1 register, Address offset: 0x10 */
+ __IO uint32_t IER; /*!< CAN interrupt enable register, Address offset: 0x14 */
+ __IO uint32_t ESR; /*!< CAN error status register, Address offset: 0x18 */
+ __IO uint32_t BTR; /*!< CAN bit timing register, Address offset: 0x1C */
+ uint32_t RESERVED0[88]; /*!< Reserved, 0x020 - 0x17F */
+ CAN_TxMailBox_TypeDef sTxMailBox[3]; /*!< CAN Tx MailBox, Address offset: 0x180 - 0x1AC */
+ CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; /*!< CAN FIFO MailBox, Address offset: 0x1B0 - 0x1CC */
+ uint32_t RESERVED1[12]; /*!< Reserved, 0x1D0 - 0x1FF */
+ __IO uint32_t FMR; /*!< CAN filter master register, Address offset: 0x200 */
+ __IO uint32_t FM1R; /*!< CAN filter mode register, Address offset: 0x204 */
+ uint32_t RESERVED2; /*!< Reserved, 0x208 */
+ __IO uint32_t FS1R; /*!< CAN filter scale register, Address offset: 0x20C */
+ uint32_t RESERVED3; /*!< Reserved, 0x210 */
+ __IO uint32_t FFA1R; /*!< CAN filter FIFO assignment register, Address offset: 0x214 */
+ uint32_t RESERVED4; /*!< Reserved, 0x218 */
+ __IO uint32_t FA1R; /*!< CAN filter activation register, Address offset: 0x21C */
+ uint32_t RESERVED5[8]; /*!< Reserved, 0x220-0x23F */
+ CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register, Address offset: 0x240-0x31C */
+} CAN_TypeDef;
+
+/**
+ * @brief Consumer Electronics Control
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< CEC control register, Address offset:0x00 */
+ __IO uint32_t CFGR; /*!< CEC configuration register, Address offset:0x04 */
+ __IO uint32_t TXDR; /*!< CEC Tx data register , Address offset:0x08 */
+ __IO uint32_t RXDR; /*!< CEC Rx Data Register, Address offset:0x0C */
+ __IO uint32_t ISR; /*!< CEC Interrupt and Status Register, Address offset:0x10 */
+ __IO uint32_t IER; /*!< CEC interrupt enable register, Address offset:0x14 */
+}CEC_TypeDef;
+
+/**
+ * @brief CRC calculation unit
+ */
+
+typedef struct
+{
+ __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
+ __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
+ uint8_t RESERVED0; /*!< Reserved, 0x05 */
+ uint16_t RESERVED1; /*!< Reserved, 0x06 */
+ __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
+} CRC_TypeDef;
+
+/**
+ * @brief Digital to Analog Converter
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */
+ __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */
+ __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
+ __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */
+ __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */
+ __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
+ __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */
+ __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */
+ __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */
+ __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */
+ __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */
+ __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */
+ __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */
+ __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */
+} DAC_TypeDef;
+
+/**
+ * @brief Debug MCU
+ */
+
+typedef struct
+{
+ __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
+ __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
+ __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */
+ __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */
+}DBGMCU_TypeDef;
+
+/**
+ * @brief DCMI
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< DCMI control register 1, Address offset: 0x00 */
+ __IO uint32_t SR; /*!< DCMI status register, Address offset: 0x04 */
+ __IO uint32_t RISR; /*!< DCMI raw interrupt status register, Address offset: 0x08 */
+ __IO uint32_t IER; /*!< DCMI interrupt enable register, Address offset: 0x0C */
+ __IO uint32_t MISR; /*!< DCMI masked interrupt status register, Address offset: 0x10 */
+ __IO uint32_t ICR; /*!< DCMI interrupt clear register, Address offset: 0x14 */
+ __IO uint32_t ESCR; /*!< DCMI embedded synchronization code register, Address offset: 0x18 */
+ __IO uint32_t ESUR; /*!< DCMI embedded synchronization unmask register, Address offset: 0x1C */
+ __IO uint32_t CWSTRTR; /*!< DCMI crop window start, Address offset: 0x20 */
+ __IO uint32_t CWSIZER; /*!< DCMI crop window size, Address offset: 0x24 */
+ __IO uint32_t DR; /*!< DCMI data register, Address offset: 0x28 */
+} DCMI_TypeDef;
+
+/**
+ * @brief DMA Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< DMA stream x configuration register */
+ __IO uint32_t NDTR; /*!< DMA stream x number of data register */
+ __IO uint32_t PAR; /*!< DMA stream x peripheral address register */
+ __IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */
+ __IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */
+ __IO uint32_t FCR; /*!< DMA stream x FIFO control register */
+} DMA_Stream_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t LISR; /*!< DMA low interrupt status register, Address offset: 0x00 */
+ __IO uint32_t HISR; /*!< DMA high interrupt status register, Address offset: 0x04 */
+ __IO uint32_t LIFCR; /*!< DMA low interrupt flag clear register, Address offset: 0x08 */
+ __IO uint32_t HIFCR; /*!< DMA high interrupt flag clear register, Address offset: 0x0C */
+} DMA_TypeDef;
+
+
+/**
+ * @brief External Interrupt/Event Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t IMR; /*!< EXTI Interrupt mask register, Address offset: 0x00 */
+ __IO uint32_t EMR; /*!< EXTI Event mask register, Address offset: 0x04 */
+ __IO uint32_t RTSR; /*!< EXTI Rising trigger selection register, Address offset: 0x08 */
+ __IO uint32_t FTSR; /*!< EXTI Falling trigger selection register, Address offset: 0x0C */
+ __IO uint32_t SWIER; /*!< EXTI Software interrupt event register, Address offset: 0x10 */
+ __IO uint32_t PR; /*!< EXTI Pending register, Address offset: 0x14 */
+} EXTI_TypeDef;
+
+/**
+ * @brief FLASH Registers
+ */
+
+typedef struct
+{
+ __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */
+ __IO uint32_t KEYR; /*!< FLASH key register, Address offset: 0x04 */
+ __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x08 */
+ __IO uint32_t SR; /*!< FLASH status register, Address offset: 0x0C */
+ __IO uint32_t CR; /*!< FLASH control register, Address offset: 0x10 */
+ __IO uint32_t OPTCR; /*!< FLASH option control register , Address offset: 0x14 */
+ __IO uint32_t OPTCR1; /*!< FLASH option control register 1, Address offset: 0x18 */
+} FLASH_TypeDef;
+
+/**
+ * @brief Flexible Memory Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */
+} FMC_Bank1_TypeDef;
+
+/**
+ * @brief Flexible Memory Controller Bank1E
+ */
+
+typedef struct
+{
+ __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */
+} FMC_Bank1E_TypeDef;
+
+/**
+ * @brief Flexible Memory Controller Bank3
+ */
+
+typedef struct
+{
+ __IO uint32_t PCR; /*!< NAND Flash control register, Address offset: 0x80 */
+ __IO uint32_t SR; /*!< NAND Flash FIFO status and interrupt register, Address offset: 0x84 */
+ __IO uint32_t PMEM; /*!< NAND Flash Common memory space timing register, Address offset: 0x88 */
+ __IO uint32_t PATT; /*!< NAND Flash Attribute memory space timing register, Address offset: 0x8C */
+ uint32_t RESERVED; /*!< Reserved, 0x90 */
+ __IO uint32_t ECCR; /*!< NAND Flash ECC result registers, Address offset: 0x94 */
+} FMC_Bank3_TypeDef;
+
+/**
+ * @brief Flexible Memory Controller Bank5_6
+ */
+
+typedef struct
+{
+ __IO uint32_t SDCR[2]; /*!< SDRAM Control registers , Address offset: 0x140-0x144 */
+ __IO uint32_t SDTR[2]; /*!< SDRAM Timing registers , Address offset: 0x148-0x14C */
+ __IO uint32_t SDCMR; /*!< SDRAM Command Mode register, Address offset: 0x150 */
+ __IO uint32_t SDRTR; /*!< SDRAM Refresh Timer register, Address offset: 0x154 */
+ __IO uint32_t SDSR; /*!< SDRAM Status register, Address offset: 0x158 */
+} FMC_Bank5_6_TypeDef;
+
+/**
+ * @brief General Purpose I/O
+ */
+
+typedef struct
+{
+ __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
+ __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */
+ __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */
+ __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
+ __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
+ __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
+ __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */
+ __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
+ __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */
+} GPIO_TypeDef;
+
+/**
+ * @brief System configuration controller
+ */
+
+typedef struct
+{
+ __IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */
+ __IO uint32_t PMC; /*!< SYSCFG peripheral mode configuration register, Address offset: 0x04 */
+ __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
+ uint32_t RESERVED[2]; /*!< Reserved, 0x18-0x1C */
+ __IO uint32_t CMPCR; /*!< SYSCFG Compensation cell control register, Address offset: 0x20 */
+ uint32_t RESERVED1[2]; /*!< Reserved, 0x24-0x28 */
+ __IO uint32_t CFGR; /*!< SYSCFG Configuration register, Address offset: 0x2C */
+} SYSCFG_TypeDef;
+
+/**
+ * @brief Inter-integrated Circuit Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */
+ __IO uint32_t OAR1; /*!< I2C Own address register 1, Address offset: 0x08 */
+ __IO uint32_t OAR2; /*!< I2C Own address register 2, Address offset: 0x0C */
+ __IO uint32_t DR; /*!< I2C Data register, Address offset: 0x10 */
+ __IO uint32_t SR1; /*!< I2C Status register 1, Address offset: 0x14 */
+ __IO uint32_t SR2; /*!< I2C Status register 2, Address offset: 0x18 */
+ __IO uint32_t CCR; /*!< I2C Clock control register, Address offset: 0x1C */
+ __IO uint32_t TRISE; /*!< I2C TRISE register, Address offset: 0x20 */
+ __IO uint32_t FLTR; /*!< I2C FLTR register, Address offset: 0x24 */
+} I2C_TypeDef;
+
+/**
+ * @brief Inter-integrated Circuit Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t CR1; /*!< FMPI2C Control register 1, Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< FMPI2C Control register 2, Address offset: 0x04 */
+ __IO uint32_t OAR1; /*!< FMPI2C Own address 1 register, Address offset: 0x08 */
+ __IO uint32_t OAR2; /*!< FMPI2C Own address 2 register, Address offset: 0x0C */
+ __IO uint32_t TIMINGR; /*!< FMPI2C Timing register, Address offset: 0x10 */
+ __IO uint32_t TIMEOUTR; /*!< FMPI2C Timeout register, Address offset: 0x14 */
+ __IO uint32_t ISR; /*!< FMPI2C Interrupt and status register, Address offset: 0x18 */
+ __IO uint32_t ICR; /*!< FMPI2C Interrupt clear register, Address offset: 0x1C */
+ __IO uint32_t PECR; /*!< FMPI2C PEC register, Address offset: 0x20 */
+ __IO uint32_t RXDR; /*!< FMPI2C Receive data register, Address offset: 0x24 */
+ __IO uint32_t TXDR; /*!< FMPI2C Transmit data register, Address offset: 0x28 */
+} FMPI2C_TypeDef;
+
+/**
+ * @brief Independent WATCHDOG
+ */
+
+typedef struct
+{
+ __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */
+ __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */
+ __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */
+ __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */
+} IWDG_TypeDef;
+
+/**
+ * @brief Power Control
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */
+ __IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */
+} PWR_TypeDef;
+
+/**
+ * @brief Reset and Clock Control
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */
+ __IO uint32_t PLLCFGR; /*!< RCC PLL configuration register, Address offset: 0x04 */
+ __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x08 */
+ __IO uint32_t CIR; /*!< RCC clock interrupt register, Address offset: 0x0C */
+ __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x10 */
+ __IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x14 */
+ __IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0x18 */
+ uint32_t RESERVED0; /*!< Reserved, 0x1C */
+ __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x20 */
+ __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x24 */
+ uint32_t RESERVED1[2]; /*!< Reserved, 0x28-0x2C */
+ __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clock register, Address offset: 0x30 */
+ __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clock register, Address offset: 0x34 */
+ __IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clock register, Address offset: 0x38 */
+ uint32_t RESERVED2; /*!< Reserved, 0x3C */
+ __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x40 */
+ __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x44 */
+ uint32_t RESERVED3[2]; /*!< Reserved, 0x48-0x4C */
+ __IO uint32_t AHB1LPENR; /*!< RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 */
+ __IO uint32_t AHB2LPENR; /*!< RCC AHB2 peripheral clock enable in low power mode register, Address offset: 0x54 */
+ __IO uint32_t AHB3LPENR; /*!< RCC AHB3 peripheral clock enable in low power mode register, Address offset: 0x58 */
+ uint32_t RESERVED4; /*!< Reserved, 0x5C */
+ __IO uint32_t APB1LPENR; /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 */
+ __IO uint32_t APB2LPENR; /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 */
+ uint32_t RESERVED5[2]; /*!< Reserved, 0x68-0x6C */
+ __IO uint32_t BDCR; /*!< RCC Backup domain control register, Address offset: 0x70 */
+ __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x74 */
+ uint32_t RESERVED6[2]; /*!< Reserved, 0x78-0x7C */
+ __IO uint32_t SSCGR; /*!< RCC spread spectrum clock generation register, Address offset: 0x80 */
+ __IO uint32_t PLLI2SCFGR; /*!< RCC PLLI2S configuration register, Address offset: 0x84 */
+ __IO uint32_t PLLSAICFGR; /*!< RCC PLLSAI configuration register, Address offset: 0x88 */
+ __IO uint32_t DCKCFGR; /*!< RCC Dedicated Clocks configuration register, Address offset: 0x8C */
+ __IO uint32_t CKGATENR; /*!< RCC Clocks Gated ENable Register, Address offset: 0x90 */
+ __IO uint32_t DCKCFGR2; /*!< RCC Dedicated Clocks configuration register 2, Address offset: 0x94 */
+} RCC_TypeDef;
+
+/**
+ * @brief Real-Time Clock
+ */
+
+typedef struct
+{
+ __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
+ __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */
+ __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */
+ __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */
+ __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */
+ __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */
+ __IO uint32_t CALIBR; /*!< RTC calibration register, Address offset: 0x18 */
+ __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */
+ __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */
+ __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */
+ __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */
+ __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */
+ __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */
+ __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */
+ __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */
+ __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */
+ __IO uint32_t TAFCR; /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */
+ __IO uint32_t ALRMASSR;/*!< RTC alarm A sub second register, Address offset: 0x44 */
+ __IO uint32_t ALRMBSSR;/*!< RTC alarm B sub second register, Address offset: 0x48 */
+ uint32_t RESERVED7; /*!< Reserved, 0x4C */
+ __IO uint32_t BKP0R; /*!< RTC backup register 1, Address offset: 0x50 */
+ __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */
+ __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */
+ __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */
+ __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */
+ __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */
+ __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */
+ __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */
+ __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */
+ __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */
+ __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */
+ __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */
+ __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */
+ __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */
+ __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */
+ __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */
+ __IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */
+ __IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */
+ __IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */
+ __IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */
+} RTC_TypeDef;
+
+/**
+ * @brief Serial Audio Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t GCR; /*!< SAI global configuration register, Address offset: 0x00 */
+} SAI_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t CR1; /*!< SAI block x configuration register 1, Address offset: 0x04 */
+ __IO uint32_t CR2; /*!< SAI block x configuration register 2, Address offset: 0x08 */
+ __IO uint32_t FRCR; /*!< SAI block x frame configuration register, Address offset: 0x0C */
+ __IO uint32_t SLOTR; /*!< SAI block x slot register, Address offset: 0x10 */
+ __IO uint32_t IMR; /*!< SAI block x interrupt mask register, Address offset: 0x14 */
+ __IO uint32_t SR; /*!< SAI block x status register, Address offset: 0x18 */
+ __IO uint32_t CLRFR; /*!< SAI block x clear flag register, Address offset: 0x1C */
+ __IO uint32_t DR; /*!< SAI block x data register, Address offset: 0x20 */
+} SAI_Block_TypeDef;
+
+/**
+ * @brief SD host Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t POWER; /*!< SDIO power control register, Address offset: 0x00 */
+ __IO uint32_t CLKCR; /*!< SDI clock control register, Address offset: 0x04 */
+ __IO uint32_t ARG; /*!< SDIO argument register, Address offset: 0x08 */
+ __IO uint32_t CMD; /*!< SDIO command register, Address offset: 0x0C */
+ __I uint32_t RESPCMD; /*!< SDIO command response register, Address offset: 0x10 */
+ __I uint32_t RESP1; /*!< SDIO response 1 register, Address offset: 0x14 */
+ __I uint32_t RESP2; /*!< SDIO response 2 register, Address offset: 0x18 */
+ __I uint32_t RESP3; /*!< SDIO response 3 register, Address offset: 0x1C */
+ __I uint32_t RESP4; /*!< SDIO response 4 register, Address offset: 0x20 */
+ __IO uint32_t DTIMER; /*!< SDIO data timer register, Address offset: 0x24 */
+ __IO uint32_t DLEN; /*!< SDIO data length register, Address offset: 0x28 */
+ __IO uint32_t DCTRL; /*!< SDIO data control register, Address offset: 0x2C */
+ __I uint32_t DCOUNT; /*!< SDIO data counter register, Address offset: 0x30 */
+ __I uint32_t STA; /*!< SDIO status register, Address offset: 0x34 */
+ __IO uint32_t ICR; /*!< SDIO interrupt clear register, Address offset: 0x38 */
+ __IO uint32_t MASK; /*!< SDIO mask register, Address offset: 0x3C */
+ uint32_t RESERVED0[2]; /*!< Reserved, 0x40-0x44 */
+ __I uint32_t FIFOCNT; /*!< SDIO FIFO counter register, Address offset: 0x48 */
+ uint32_t RESERVED1[13]; /*!< Reserved, 0x4C-0x7C */
+ __IO uint32_t FIFO; /*!< SDIO data FIFO register, Address offset: 0x80 */
+} SDIO_TypeDef;
+
+/**
+ * @brief Serial Peripheral Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t CR1; /*!< SPI control register 1 (not used in I2S mode), Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< SPI control register 2, Address offset: 0x04 */
+ __IO uint32_t SR; /*!< SPI status register, Address offset: 0x08 */
+ __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */
+ __IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
+ __IO uint32_t RXCRCR; /*!< SPI RX CRC register (not used in I2S mode), Address offset: 0x14 */
+ __IO uint32_t TXCRCR; /*!< SPI TX CRC register (not used in I2S mode), Address offset: 0x18 */
+ __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */
+ __IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */
+} SPI_TypeDef;
+
+/**
+ * @brief QUAD Serial Peripheral Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< QUADSPI Control register, Address offset: 0x00 */
+ __IO uint32_t DCR; /*!< QUADSPI Device Configuration register, Address offset: 0x04 */
+ __IO uint32_t SR; /*!< QUADSPI Status register, Address offset: 0x08 */
+ __IO uint32_t FCR; /*!< QUADSPI Flag Clear register, Address offset: 0x0C */
+ __IO uint32_t DLR; /*!< QUADSPI Data Length register, Address offset: 0x10 */
+ __IO uint32_t CCR; /*!< QUADSPI Communication Configuration register, Address offset: 0x14 */
+ __IO uint32_t AR; /*!< QUADSPI Address register, Address offset: 0x18 */
+ __IO uint32_t ABR; /*!< QUADSPI Alternate Bytes register, Address offset: 0x1C */
+ __IO uint32_t DR; /*!< QUADSPI Data register, Address offset: 0x20 */
+ __IO uint32_t PSMKR; /*!< QUADSPI Polling Status Mask register, Address offset: 0x24 */
+ __IO uint32_t PSMAR; /*!< QUADSPI Polling Status Match register, Address offset: 0x28 */
+ __IO uint32_t PIR; /*!< QUADSPI Polling Interval register, Address offset: 0x2C */
+ __IO uint32_t LPTR; /*!< QUADSPI Low Power Timeout register, Address offset: 0x30 */
+} QUADSPI_TypeDef;
+
+/**
+ * @brief SPDIFRX Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< Control register, Address offset: 0x00 */
+ __IO uint16_t IMR; /*!< Interrupt mask register, Address offset: 0x04 */
+ uint16_t RESERVED0; /*!< Reserved, 0x06 */
+ __IO uint32_t SR; /*!< Status register, Address offset: 0x08 */
+ __IO uint16_t IFCR; /*!< Interrupt Flag Clear register, Address offset: 0x0C */
+ uint16_t RESERVED1; /*!< Reserved, 0x0E */
+ __IO uint32_t DR; /*!< Data input register, Address offset: 0x10 */
+ __IO uint32_t CSR; /*!< Channel Status register, Address offset: 0x14 */
+ __IO uint32_t DIR; /*!< Debug Information register, Address offset: 0x18 */
+ uint16_t RESERVED2; /*!< Reserved, 0x1A */
+} SPDIFRX_TypeDef;
+
+/**
+ * @brief TIM
+ */
+
+typedef struct
+{
+ __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
+ __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */
+ __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
+ __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
+ __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
+ __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
+ __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
+ __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
+ __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
+ __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */
+ __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
+ __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */
+ __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
+ __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
+ __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
+ __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
+ __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
+ __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
+ __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */
+ __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */
+} TIM_TypeDef;
+
+/**
+ * @brief Universal Synchronous Asynchronous Receiver Transmitter
+ */
+
+typedef struct
+{
+ __IO uint32_t SR; /*!< USART Status register, Address offset: 0x00 */
+ __IO uint32_t DR; /*!< USART Data register, Address offset: 0x04 */
+ __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x08 */
+ __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x0C */
+ __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x10 */
+ __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x14 */
+ __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x18 */
+} USART_TypeDef;
+
+/**
+ * @brief Window WATCHDOG
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
+ __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
+ __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
+} WWDG_TypeDef;
+
+/**
+ * @brief USB_OTG_Core_Registers
+ */
+typedef struct
+{
+ __IO uint32_t GOTGCTL; /*!< USB_OTG Control and Status Register 000h */
+ __IO uint32_t GOTGINT; /*!< USB_OTG Interrupt Register 004h */
+ __IO uint32_t GAHBCFG; /*!< Core AHB Configuration Register 008h */
+ __IO uint32_t GUSBCFG; /*!< Core USB Configuration Register 00Ch */
+ __IO uint32_t GRSTCTL; /*!< Core Reset Register 010h */
+ __IO uint32_t GINTSTS; /*!< Core Interrupt Register 014h */
+ __IO uint32_t GINTMSK; /*!< Core Interrupt Mask Register 018h */
+ __IO uint32_t GRXSTSR; /*!< Receive Sts Q Read Register 01Ch */
+ __IO uint32_t GRXSTSP; /*!< Receive Sts Q Read & POP Register 020h */
+ __IO uint32_t GRXFSIZ; /*!< Receive FIFO Size Register 024h */
+ __IO uint32_t DIEPTXF0_HNPTXFSIZ; /*!< EP0 / Non Periodic Tx FIFO Size Register 028h */
+ __IO uint32_t HNPTXSTS; /*!< Non Periodic Tx FIFO/Queue Sts reg 02Ch */
+ uint32_t Reserved30[2]; /*!< Reserved 030h */
+ __IO uint32_t GCCFG; /*!< General Purpose IO Register 038h */
+ __IO uint32_t CID; /*!< User ID Register 03Ch */
+ uint32_t Reserved5[3]; /*!< Reserved 040h-048h */
+ __IO uint32_t GHWCFG3; /*!< User HW config3 04Ch */
+ uint32_t Reserved6; /*!< Reserved 050h */
+ __IO uint32_t GLPMCFG; /*!< LPM Register 054h */
+ uint32_t Reserved; /*!< Reserved 058h */
+ __IO uint32_t GDFIFOCFG; /*!< DFIFO Software Config Register 05Ch */
+ uint32_t Reserved43[40]; /*!< Reserved 058h-0FFh */
+ __IO uint32_t HPTXFSIZ; /*!< Host Periodic Tx FIFO Size Reg 100h */
+ __IO uint32_t DIEPTXF[0x0F]; /*!< dev Periodic Transmit FIFO */
+} USB_OTG_GlobalTypeDef;
+
+/**
+ * @brief USB_OTG_device_Registers
+ */
+typedef struct
+{
+ __IO uint32_t DCFG; /*!< dev Configuration Register 800h */
+ __IO uint32_t DCTL; /*!< dev Control Register 804h */
+ __IO uint32_t DSTS; /*!< dev Status Register (RO) 808h */
+ uint32_t Reserved0C; /*!< Reserved 80Ch */
+ __IO uint32_t DIEPMSK; /*!< dev IN Endpoint Mask 810h */
+ __IO uint32_t DOEPMSK; /*!< dev OUT Endpoint Mask 814h */
+ __IO uint32_t DAINT; /*!< dev All Endpoints Itr Reg 818h */
+ __IO uint32_t DAINTMSK; /*!< dev All Endpoints Itr Mask 81Ch */
+ uint32_t Reserved20; /*!< Reserved 820h */
+ uint32_t Reserved9; /*!< Reserved 824h */
+ __IO uint32_t DVBUSDIS; /*!< dev VBUS discharge Register 828h */
+ __IO uint32_t DVBUSPULSE; /*!< dev VBUS Pulse Register 82Ch */
+ __IO uint32_t DTHRCTL; /*!< dev threshold 830h */
+ __IO uint32_t DIEPEMPMSK; /*!< dev empty msk 834h */
+ __IO uint32_t DEACHINT; /*!< dedicated EP interrupt 838h */
+ __IO uint32_t DEACHMSK; /*!< dedicated EP msk 83Ch */
+ uint32_t Reserved40; /*!< dedicated EP mask 840h */
+ __IO uint32_t DINEP1MSK; /*!< dedicated EP mask 844h */
+ uint32_t Reserved44[15]; /*!< Reserved 844-87Ch */
+ __IO uint32_t DOUTEP1MSK; /*!< dedicated EP msk 884h */
+} USB_OTG_DeviceTypeDef;
+
+/**
+ * @brief USB_OTG_IN_Endpoint-Specific_Register
+ */
+typedef struct
+{
+ __IO uint32_t DIEPCTL; /*!< dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h */
+ uint32_t Reserved04; /*!< Reserved 900h + (ep_num * 20h) + 04h */
+ __IO uint32_t DIEPINT; /*!< dev IN Endpoint Itr Reg 900h + (ep_num * 20h) + 08h */
+ uint32_t Reserved0C; /*!< Reserved 900h + (ep_num * 20h) + 0Ch */
+ __IO uint32_t DIEPTSIZ; /*!< IN Endpoint Txfer Size 900h + (ep_num * 20h) + 10h */
+ __IO uint32_t DIEPDMA; /*!< IN Endpoint DMA Address Reg 900h + (ep_num * 20h) + 14h */
+ __IO uint32_t DTXFSTS; /*!< IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h */
+ uint32_t Reserved18; /*!< Reserved 900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch */
+} USB_OTG_INEndpointTypeDef;
+
+/**
+ * @brief USB_OTG_OUT_Endpoint-Specific_Registers
+ */
+typedef struct
+{
+ __IO uint32_t DOEPCTL; /*!< dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h */
+ uint32_t Reserved04; /*!< Reserved B00h + (ep_num * 20h) + 04h */
+ __IO uint32_t DOEPINT; /*!< dev OUT Endpoint Itr Reg B00h + (ep_num * 20h) + 08h */
+ uint32_t Reserved0C; /*!< Reserved B00h + (ep_num * 20h) + 0Ch */
+ __IO uint32_t DOEPTSIZ; /*!< dev OUT Endpoint Txfer Size B00h + (ep_num * 20h) + 10h */
+ __IO uint32_t DOEPDMA; /*!< dev OUT Endpoint DMA Address B00h + (ep_num * 20h) + 14h */
+ uint32_t Reserved18[2]; /*!< Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch */
+} USB_OTG_OUTEndpointTypeDef;
+
+/**
+ * @brief USB_OTG_Host_Mode_Register_Structures
+ */
+typedef struct
+{
+ __IO uint32_t HCFG; /*!< Host Configuration Register 400h */
+ __IO uint32_t HFIR; /*!< Host Frame Interval Register 404h */
+ __IO uint32_t HFNUM; /*!< Host Frame Nbr/Frame Remaining 408h */
+ uint32_t Reserved40C; /*!< Reserved 40Ch */
+ __IO uint32_t HPTXSTS; /*!< Host Periodic Tx FIFO/ Queue Status 410h */
+ __IO uint32_t HAINT; /*!< Host All Channels Interrupt Register 414h */
+ __IO uint32_t HAINTMSK; /*!< Host All Channels Interrupt Mask 418h */
+} USB_OTG_HostTypeDef;
+
+/**
+ * @brief USB_OTG_Host_Channel_Specific_Registers
+ */
+typedef struct
+{
+ __IO uint32_t HCCHAR; /*!< Host Channel Characteristics Register 500h */
+ __IO uint32_t HCSPLT; /*!< Host Channel Split Control Register 504h */
+ __IO uint32_t HCINT; /*!< Host Channel Interrupt Register 508h */
+ __IO uint32_t HCINTMSK; /*!< Host Channel Interrupt Mask Register 50Ch */
+ __IO uint32_t HCTSIZ; /*!< Host Channel Transfer Size Register 510h */
+ __IO uint32_t HCDMA; /*!< Host Channel DMA Address Register 514h */
+ uint32_t Reserved[2]; /*!< Reserved */
+} USB_OTG_HostChannelTypeDef;
+
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_memory_map
+ * @{
+ */
+#define FLASH_BASE 0x08000000U /*!< FLASH(up to 1 MB) base address in the alias region */
+#define SRAM1_BASE 0x20000000U /*!< SRAM1(112 KB) base address in the alias region */
+#define SRAM2_BASE 0x2001C000U /*!< SRAM2(16 KB) base address in the alias region */
+#define PERIPH_BASE 0x40000000U /*!< Peripheral base address in the alias region */
+#define BKPSRAM_BASE 0x40024000U /*!< Backup SRAM(4 KB) base address in the alias region */
+#define FMC_R_BASE 0xA0000000U /*!< FMC registers base address */
+#define QSPI_R_BASE 0xA0001000U /*!< QuadSPI registers base address */
+
+#define SRAM1_BB_BASE 0x22000000U /*!< SRAM1(112 KB) base address in the bit-band region */
+#define SRAM2_BB_BASE 0x22380000U /*!< SRAM2(16 KB) base address in the bit-band region */
+#define PERIPH_BB_BASE 0x42000000U /*!< Peripheral base address in the bit-band region */
+#define BKPSRAM_BB_BASE 0x42480000U /*!< Backup SRAM(4 KB) base address in the bit-band region */
+#define FLASH_END 0x0807FFFFU /*!< FLASH end address */
+
+/* Legacy defines */
+#define SRAM_BASE SRAM1_BASE
+#define SRAM_BB_BASE SRAM1_BB_BASE
+
+
+/*!< Peripheral memory map */
+#define APB1PERIPH_BASE PERIPH_BASE
+#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000U)
+#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000U)
+#define AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000U)
+
+/*!< APB1 peripherals */
+#define TIM2_BASE (APB1PERIPH_BASE + 0x0000U)
+#define TIM3_BASE (APB1PERIPH_BASE + 0x0400U)
+#define TIM4_BASE (APB1PERIPH_BASE + 0x0800U)
+#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00U)
+#define TIM6_BASE (APB1PERIPH_BASE + 0x1000U)
+#define TIM7_BASE (APB1PERIPH_BASE + 0x1400U)
+#define TIM12_BASE (APB1PERIPH_BASE + 0x1800U)
+#define TIM13_BASE (APB1PERIPH_BASE + 0x1C00U)
+#define TIM14_BASE (APB1PERIPH_BASE + 0x2000U)
+#define RTC_BASE (APB1PERIPH_BASE + 0x2800U)
+#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00U)
+#define IWDG_BASE (APB1PERIPH_BASE + 0x3000U)
+#define SPI2_BASE (APB1PERIPH_BASE + 0x3800U)
+#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00U)
+#define SPDIFRX_BASE (APB1PERIPH_BASE + 0x4000U)
+#define USART2_BASE (APB1PERIPH_BASE + 0x4400U)
+#define USART3_BASE (APB1PERIPH_BASE + 0x4800U)
+#define UART4_BASE (APB1PERIPH_BASE + 0x4C00U)
+#define UART5_BASE (APB1PERIPH_BASE + 0x5000U)
+#define I2C1_BASE (APB1PERIPH_BASE + 0x5400U)
+#define I2C2_BASE (APB1PERIPH_BASE + 0x5800U)
+#define I2C3_BASE (APB1PERIPH_BASE + 0x5C00U)
+#define FMPI2C1_BASE (APB1PERIPH_BASE + 0x6000U)
+#define CAN1_BASE (APB1PERIPH_BASE + 0x6400U)
+#define CAN2_BASE (APB1PERIPH_BASE + 0x6800U)
+#define CEC_BASE (APB1PERIPH_BASE + 0x6C00U)
+#define PWR_BASE (APB1PERIPH_BASE + 0x7000U)
+#define DAC_BASE (APB1PERIPH_BASE + 0x7400U)
+
+/*!< APB2 peripherals */
+#define TIM1_BASE (APB2PERIPH_BASE + 0x0000U)
+#define TIM8_BASE (APB2PERIPH_BASE + 0x0400U)
+#define USART1_BASE (APB2PERIPH_BASE + 0x1000U)
+#define USART6_BASE (APB2PERIPH_BASE + 0x1400U)
+#define ADC1_BASE (APB2PERIPH_BASE + 0x2000U)
+#define ADC2_BASE (APB2PERIPH_BASE + 0x2100U)
+#define ADC3_BASE (APB2PERIPH_BASE + 0x2200U)
+#define ADC_BASE (APB2PERIPH_BASE + 0x2300U)
+#define SDIO_BASE (APB2PERIPH_BASE + 0x2C00U)
+#define SPI1_BASE (APB2PERIPH_BASE + 0x3000U)
+#define SPI4_BASE (APB2PERIPH_BASE + 0x3400U)
+#define SYSCFG_BASE (APB2PERIPH_BASE + 0x3800U)
+#define EXTI_BASE (APB2PERIPH_BASE + 0x3C00U)
+#define TIM9_BASE (APB2PERIPH_BASE + 0x4000U)
+#define TIM10_BASE (APB2PERIPH_BASE + 0x4400U)
+#define TIM11_BASE (APB2PERIPH_BASE + 0x4800U)
+#define SAI1_BASE (APB2PERIPH_BASE + 0x5800U)
+#define SAI1_Block_A_BASE (SAI1_BASE + 0x004U)
+#define SAI1_Block_B_BASE (SAI1_BASE + 0x024U)
+#define SAI2_BASE (APB2PERIPH_BASE + 0x5C00U)
+#define SAI2_Block_A_BASE (SAI2_BASE + 0x004U)
+#define SAI2_Block_B_BASE (SAI2_BASE + 0x024U)
+
+/*!< AHB1 peripherals */
+#define GPIOA_BASE (AHB1PERIPH_BASE + 0x0000U)
+#define GPIOB_BASE (AHB1PERIPH_BASE + 0x0400U)
+#define GPIOC_BASE (AHB1PERIPH_BASE + 0x0800U)
+#define GPIOD_BASE (AHB1PERIPH_BASE + 0x0C00U)
+#define GPIOE_BASE (AHB1PERIPH_BASE + 0x1000U)
+#define GPIOF_BASE (AHB1PERIPH_BASE + 0x1400U)
+#define GPIOG_BASE (AHB1PERIPH_BASE + 0x1800U)
+#define GPIOH_BASE (AHB1PERIPH_BASE + 0x1C00U)
+#define CRC_BASE (AHB1PERIPH_BASE + 0x3000U)
+#define RCC_BASE (AHB1PERIPH_BASE + 0x3800U)
+#define FLASH_R_BASE (AHB1PERIPH_BASE + 0x3C00U)
+#define DMA1_BASE (AHB1PERIPH_BASE + 0x6000U)
+#define DMA1_Stream0_BASE (DMA1_BASE + 0x010U)
+#define DMA1_Stream1_BASE (DMA1_BASE + 0x028U)
+#define DMA1_Stream2_BASE (DMA1_BASE + 0x040U)
+#define DMA1_Stream3_BASE (DMA1_BASE + 0x058U)
+#define DMA1_Stream4_BASE (DMA1_BASE + 0x070U)
+#define DMA1_Stream5_BASE (DMA1_BASE + 0x088U)
+#define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0U)
+#define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8U)
+#define DMA2_BASE (AHB1PERIPH_BASE + 0x6400U)
+#define DMA2_Stream0_BASE (DMA2_BASE + 0x010U)
+#define DMA2_Stream1_BASE (DMA2_BASE + 0x028U)
+#define DMA2_Stream2_BASE (DMA2_BASE + 0x040U)
+#define DMA2_Stream3_BASE (DMA2_BASE + 0x058U)
+#define DMA2_Stream4_BASE (DMA2_BASE + 0x070U)
+#define DMA2_Stream5_BASE (DMA2_BASE + 0x088U)
+#define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0U)
+#define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8U)
+
+/*!< AHB2 peripherals */
+#define DCMI_BASE (AHB2PERIPH_BASE + 0x50000U)
+
+/*!< FMC Bankx registers base address */
+#define FMC_Bank1_R_BASE (FMC_R_BASE + 0x0000U)
+#define FMC_Bank1E_R_BASE (FMC_R_BASE + 0x0104U)
+#define FMC_Bank3_R_BASE (FMC_R_BASE + 0x0080U)
+#define FMC_Bank5_6_R_BASE (FMC_R_BASE + 0x0140U)
+
+/*!< Debug MCU registers base address */
+#define DBGMCU_BASE 0xE0042000U
+
+/*!< USB registers base address */
+#define USB_OTG_HS_PERIPH_BASE 0x40040000U
+#define USB_OTG_FS_PERIPH_BASE 0x50000000U
+
+#define USB_OTG_GLOBAL_BASE 0x000U
+#define USB_OTG_DEVICE_BASE 0x800U
+#define USB_OTG_IN_ENDPOINT_BASE 0x900U
+#define USB_OTG_OUT_ENDPOINT_BASE 0xB00U
+#define USB_OTG_EP_REG_SIZE 0x20U
+#define USB_OTG_HOST_BASE 0x400U
+#define USB_OTG_HOST_PORT_BASE 0x440U
+#define USB_OTG_HOST_CHANNEL_BASE 0x500U
+#define USB_OTG_HOST_CHANNEL_SIZE 0x20U
+#define USB_OTG_PCGCCTL_BASE 0xE00U
+#define USB_OTG_FIFO_BASE 0x1000U
+#define USB_OTG_FIFO_SIZE 0x1000U
+
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_declaration
+ * @{
+ */
+#define TIM2 ((TIM_TypeDef *) TIM2_BASE)
+#define TIM3 ((TIM_TypeDef *) TIM3_BASE)
+#define TIM4 ((TIM_TypeDef *) TIM4_BASE)
+#define TIM5 ((TIM_TypeDef *) TIM5_BASE)
+#define TIM6 ((TIM_TypeDef *) TIM6_BASE)
+#define TIM7 ((TIM_TypeDef *) TIM7_BASE)
+#define TIM12 ((TIM_TypeDef *) TIM12_BASE)
+#define TIM13 ((TIM_TypeDef *) TIM13_BASE)
+#define TIM14 ((TIM_TypeDef *) TIM14_BASE)
+#define RTC ((RTC_TypeDef *) RTC_BASE)
+#define WWDG ((WWDG_TypeDef *) WWDG_BASE)
+#define IWDG ((IWDG_TypeDef *) IWDG_BASE)
+#define SPI2 ((SPI_TypeDef *) SPI2_BASE)
+#define SPI3 ((SPI_TypeDef *) SPI3_BASE)
+#define SPDIFRX ((SPDIFRX_TypeDef *) SPDIFRX_BASE)
+#define USART2 ((USART_TypeDef *) USART2_BASE)
+#define USART3 ((USART_TypeDef *) USART3_BASE)
+#define UART4 ((USART_TypeDef *) UART4_BASE)
+#define UART5 ((USART_TypeDef *) UART5_BASE)
+#define I2C1 ((I2C_TypeDef *) I2C1_BASE)
+#define I2C2 ((I2C_TypeDef *) I2C2_BASE)
+#define I2C3 ((I2C_TypeDef *) I2C3_BASE)
+#define FMPI2C1 ((FMPI2C_TypeDef *) FMPI2C1_BASE)
+#define CAN1 ((CAN_TypeDef *) CAN1_BASE)
+#define CAN2 ((CAN_TypeDef *) CAN2_BASE)
+#define CEC ((CEC_TypeDef *) CEC_BASE)
+#define PWR ((PWR_TypeDef *) PWR_BASE)
+#define DAC ((DAC_TypeDef *) DAC_BASE)
+#define TIM1 ((TIM_TypeDef *) TIM1_BASE)
+#define TIM8 ((TIM_TypeDef *) TIM8_BASE)
+#define USART1 ((USART_TypeDef *) USART1_BASE)
+#define USART6 ((USART_TypeDef *) USART6_BASE)
+#define ADC ((ADC_Common_TypeDef *) ADC_BASE)
+#define ADC1 ((ADC_TypeDef *) ADC1_BASE)
+#define ADC2 ((ADC_TypeDef *) ADC2_BASE)
+#define ADC3 ((ADC_TypeDef *) ADC3_BASE)
+#define SDIO ((SDIO_TypeDef *) SDIO_BASE)
+#define SPI1 ((SPI_TypeDef *) SPI1_BASE)
+#define SPI4 ((SPI_TypeDef *) SPI4_BASE)
+#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
+#define EXTI ((EXTI_TypeDef *) EXTI_BASE)
+#define TIM9 ((TIM_TypeDef *) TIM9_BASE)
+#define TIM10 ((TIM_TypeDef *) TIM10_BASE)
+#define TIM11 ((TIM_TypeDef *) TIM11_BASE)
+#define SAI1 ((SAI_TypeDef *) SAI1_BASE)
+#define SAI1_Block_A ((SAI_Block_TypeDef *)SAI1_Block_A_BASE)
+#define SAI1_Block_B ((SAI_Block_TypeDef *)SAI1_Block_B_BASE)
+#define SAI2 ((SAI_TypeDef *) SAI2_BASE)
+#define SAI2_Block_A ((SAI_Block_TypeDef *)SAI2_Block_A_BASE)
+#define SAI2_Block_B ((SAI_Block_TypeDef *)SAI2_Block_B_BASE)
+
+#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
+#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
+#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
+#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
+#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
+#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
+#define GPIOG ((GPIO_TypeDef *) GPIOG_BASE)
+#define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
+#define CRC ((CRC_TypeDef *) CRC_BASE)
+#define RCC ((RCC_TypeDef *) RCC_BASE)
+#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
+#define DMA1 ((DMA_TypeDef *) DMA1_BASE)
+#define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)
+#define DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)
+#define DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)
+#define DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)
+#define DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)
+#define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)
+#define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)
+#define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)
+#define DMA2 ((DMA_TypeDef *) DMA2_BASE)
+#define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)
+#define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
+#define DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)
+#define DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)
+#define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)
+#define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)
+#define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)
+#define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)
+#define DCMI ((DCMI_TypeDef *) DCMI_BASE)
+#define FMC_Bank1 ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE)
+#define FMC_Bank1E ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE)
+#define FMC_Bank3 ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE)
+#define FMC_Bank5_6 ((FMC_Bank5_6_TypeDef *) FMC_Bank5_6_R_BASE)
+#define QUADSPI ((QUADSPI_TypeDef *) QSPI_R_BASE)
+
+#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
+
+#define USB_OTG_FS ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE)
+#define USB_OTG_HS ((USB_OTG_GlobalTypeDef *) USB_OTG_HS_PERIPH_BASE)
+
+/**
+ * @}
+ */
+
+/** @addtogroup Exported_constants
+ * @{
+ */
+
+ /** @addtogroup Peripheral_Registers_Bits_Definition
+ * @{
+ */
+
+/******************************************************************************/
+/* Peripheral Registers_Bits_Definition */
+/******************************************************************************/
+
+/******************************************************************************/
+/* */
+/* Analog to Digital Converter */
+/* */
+/******************************************************************************/
+/******************** Bit definition for ADC_SR register ********************/
+#define ADC_SR_AWD 0x00000001U /*!<Analog watchdog flag */
+#define ADC_SR_EOC 0x00000002U /*!<End of conversion */
+#define ADC_SR_JEOC 0x00000004U /*!<Injected channel end of conversion */
+#define ADC_SR_JSTRT 0x00000008U /*!<Injected channel Start flag */
+#define ADC_SR_STRT 0x00000010U /*!<Regular channel Start flag */
+#define ADC_SR_OVR 0x00000020U /*!<Overrun flag */
+
+/******************* Bit definition for ADC_CR1 register ********************/
+#define ADC_CR1_AWDCH 0x0000001FU /*!<AWDCH[4:0] bits (Analog watchdog channel select bits) */
+#define ADC_CR1_AWDCH_0 0x00000001U /*!<Bit 0 */
+#define ADC_CR1_AWDCH_1 0x00000002U /*!<Bit 1 */
+#define ADC_CR1_AWDCH_2 0x00000004U /*!<Bit 2 */
+#define ADC_CR1_AWDCH_3 0x00000008U /*!<Bit 3 */
+#define ADC_CR1_AWDCH_4 0x00000010U /*!<Bit 4 */
+#define ADC_CR1_EOCIE 0x00000020U /*!<Interrupt enable for EOC */
+#define ADC_CR1_AWDIE 0x00000040U /*!<AAnalog Watchdog interrupt enable */
+#define ADC_CR1_JEOCIE 0x00000080U /*!<Interrupt enable for injected channels */
+#define ADC_CR1_SCAN 0x00000100U /*!<Scan mode */
+#define ADC_CR1_AWDSGL 0x00000200U /*!<Enable the watchdog on a single channel in scan mode */
+#define ADC_CR1_JAUTO 0x00000400U /*!<Automatic injected group conversion */
+#define ADC_CR1_DISCEN 0x00000800U /*!<Discontinuous mode on regular channels */
+#define ADC_CR1_JDISCEN 0x00001000U /*!<Discontinuous mode on injected channels */
+#define ADC_CR1_DISCNUM 0x0000E000U /*!<DISCNUM[2:0] bits (Discontinuous mode channel count) */
+#define ADC_CR1_DISCNUM_0 0x00002000U /*!<Bit 0 */
+#define ADC_CR1_DISCNUM_1 0x00004000U /*!<Bit 1 */
+#define ADC_CR1_DISCNUM_2 0x00008000U /*!<Bit 2 */
+#define ADC_CR1_JAWDEN 0x00400000U /*!<Analog watchdog enable on injected channels */
+#define ADC_CR1_AWDEN 0x00800000U /*!<Analog watchdog enable on regular channels */
+#define ADC_CR1_RES 0x03000000U /*!<RES[2:0] bits (Resolution) */
+#define ADC_CR1_RES_0 0x01000000U /*!<Bit 0 */
+#define ADC_CR1_RES_1 0x02000000U /*!<Bit 1 */
+#define ADC_CR1_OVRIE 0x04000000U /*!<overrun interrupt enable */
+
+/******************* Bit definition for ADC_CR2 register ********************/
+#define ADC_CR2_ADON 0x00000001U /*!<A/D Converter ON / OFF */
+#define ADC_CR2_CONT 0x00000002U /*!<Continuous Conversion */
+#define ADC_CR2_DMA 0x00000100U /*!<Direct Memory access mode */
+#define ADC_CR2_DDS 0x00000200U /*!<DMA disable selection (Single ADC) */
+#define ADC_CR2_EOCS 0x00000400U /*!<End of conversion selection */
+#define ADC_CR2_ALIGN 0x00000800U /*!<Data Alignment */
+#define ADC_CR2_JEXTSEL 0x000F0000U /*!<JEXTSEL[3:0] bits (External event select for injected group) */
+#define ADC_CR2_JEXTSEL_0 0x00010000U /*!<Bit 0 */
+#define ADC_CR2_JEXTSEL_1 0x00020000U /*!<Bit 1 */
+#define ADC_CR2_JEXTSEL_2 0x00040000U /*!<Bit 2 */
+#define ADC_CR2_JEXTSEL_3 0x00080000U /*!<Bit 3 */
+#define ADC_CR2_JEXTEN 0x00300000U /*!<JEXTEN[1:0] bits (External Trigger Conversion mode for injected channelsp) */
+#define ADC_CR2_JEXTEN_0 0x00100000U /*!<Bit 0 */
+#define ADC_CR2_JEXTEN_1 0x00200000U /*!<Bit 1 */
+#define ADC_CR2_JSWSTART 0x00400000U /*!<Start Conversion of injected channels */
+#define ADC_CR2_EXTSEL 0x0F000000U /*!<EXTSEL[3:0] bits (External Event Select for regular group) */
+#define ADC_CR2_EXTSEL_0 0x01000000U /*!<Bit 0 */
+#define ADC_CR2_EXTSEL_1 0x02000000U /*!<Bit 1 */
+#define ADC_CR2_EXTSEL_2 0x04000000U /*!<Bit 2 */
+#define ADC_CR2_EXTSEL_3 0x08000000U /*!<Bit 3 */
+#define ADC_CR2_EXTEN 0x30000000U /*!<EXTEN[1:0] bits (External Trigger Conversion mode for regular channelsp) */
+#define ADC_CR2_EXTEN_0 0x10000000U /*!<Bit 0 */
+#define ADC_CR2_EXTEN_1 0x20000000U /*!<Bit 1 */
+#define ADC_CR2_SWSTART 0x40000000U /*!<Start Conversion of regular channels */
+
+/****************** Bit definition for ADC_SMPR1 register *******************/
+#define ADC_SMPR1_SMP10 0x00000007U /*!<SMP10[2:0] bits (Channel 10 Sample time selection) */
+#define ADC_SMPR1_SMP10_0 0x00000001U /*!<Bit 0 */
+#define ADC_SMPR1_SMP10_1 0x00000002U /*!<Bit 1 */
+#define ADC_SMPR1_SMP10_2 0x00000004U /*!<Bit 2 */
+#define ADC_SMPR1_SMP11 0x00000038U /*!<SMP11[2:0] bits (Channel 11 Sample time selection) */
+#define ADC_SMPR1_SMP11_0 0x00000008U /*!<Bit 0 */
+#define ADC_SMPR1_SMP11_1 0x00000010U /*!<Bit 1 */
+#define ADC_SMPR1_SMP11_2 0x00000020U /*!<Bit 2 */
+#define ADC_SMPR1_SMP12 0x000001C0U /*!<SMP12[2:0] bits (Channel 12 Sample time selection) */
+#define ADC_SMPR1_SMP12_0 0x00000040U /*!<Bit 0 */
+#define ADC_SMPR1_SMP12_1 0x00000080U /*!<Bit 1 */
+#define ADC_SMPR1_SMP12_2 0x00000100U /*!<Bit 2 */
+#define ADC_SMPR1_SMP13 0x00000E00U /*!<SMP13[2:0] bits (Channel 13 Sample time selection) */
+#define ADC_SMPR1_SMP13_0 0x00000200U /*!<Bit 0 */
+#define ADC_SMPR1_SMP13_1 0x00000400U /*!<Bit 1 */
+#define ADC_SMPR1_SMP13_2 0x00000800U /*!<Bit 2 */
+#define ADC_SMPR1_SMP14 0x00007000U /*!<SMP14[2:0] bits (Channel 14 Sample time selection) */
+#define ADC_SMPR1_SMP14_0 0x00001000U /*!<Bit 0 */
+#define ADC_SMPR1_SMP14_1 0x00002000U /*!<Bit 1 */
+#define ADC_SMPR1_SMP14_2 0x00004000U /*!<Bit 2 */
+#define ADC_SMPR1_SMP15 0x00038000U /*!<SMP15[2:0] bits (Channel 15 Sample time selection) */
+#define ADC_SMPR1_SMP15_0 0x00008000U /*!<Bit 0 */
+#define ADC_SMPR1_SMP15_1 0x00010000U /*!<Bit 1 */
+#define ADC_SMPR1_SMP15_2 0x00020000U /*!<Bit 2 */
+#define ADC_SMPR1_SMP16 0x001C0000U /*!<SMP16[2:0] bits (Channel 16 Sample time selection) */
+#define ADC_SMPR1_SMP16_0 0x00040000U /*!<Bit 0 */
+#define ADC_SMPR1_SMP16_1 0x00080000U /*!<Bit 1 */
+#define ADC_SMPR1_SMP16_2 0x00100000U /*!<Bit 2 */
+#define ADC_SMPR1_SMP17 0x00E00000U /*!<SMP17[2:0] bits (Channel 17 Sample time selection) */
+#define ADC_SMPR1_SMP17_0 0x00200000U /*!<Bit 0 */
+#define ADC_SMPR1_SMP17_1 0x00400000U /*!<Bit 1 */
+#define ADC_SMPR1_SMP17_2 0x00800000U /*!<Bit 2 */
+#define ADC_SMPR1_SMP18 0x07000000U /*!<SMP18[2:0] bits (Channel 18 Sample time selection) */
+#define ADC_SMPR1_SMP18_0 0x01000000U /*!<Bit 0 */
+#define ADC_SMPR1_SMP18_1 0x02000000U /*!<Bit 1 */
+#define ADC_SMPR1_SMP18_2 0x04000000U /*!<Bit 2 */
+
+/****************** Bit definition for ADC_SMPR2 register *******************/
+#define ADC_SMPR2_SMP0 0x00000007U /*!<SMP0[2:0] bits (Channel 0 Sample time selection) */
+#define ADC_SMPR2_SMP0_0 0x00000001U /*!<Bit 0 */
+#define ADC_SMPR2_SMP0_1 0x00000002U /*!<Bit 1 */
+#define ADC_SMPR2_SMP0_2 0x00000004U /*!<Bit 2 */
+#define ADC_SMPR2_SMP1 0x00000038U /*!<SMP1[2:0] bits (Channel 1 Sample time selection) */
+#define ADC_SMPR2_SMP1_0 0x00000008U /*!<Bit 0 */
+#define ADC_SMPR2_SMP1_1 0x00000010U /*!<Bit 1 */
+#define ADC_SMPR2_SMP1_2 0x00000020U /*!<Bit 2 */
+#define ADC_SMPR2_SMP2 0x000001C0U /*!<SMP2[2:0] bits (Channel 2 Sample time selection) */
+#define ADC_SMPR2_SMP2_0 0x00000040U /*!<Bit 0 */
+#define ADC_SMPR2_SMP2_1 0x00000080U /*!<Bit 1 */
+#define ADC_SMPR2_SMP2_2 0x00000100U /*!<Bit 2 */
+#define ADC_SMPR2_SMP3 0x00000E00U /*!<SMP3[2:0] bits (Channel 3 Sample time selection) */
+#define ADC_SMPR2_SMP3_0 0x00000200U /*!<Bit 0 */
+#define ADC_SMPR2_SMP3_1 0x00000400U /*!<Bit 1 */
+#define ADC_SMPR2_SMP3_2 0x00000800U /*!<Bit 2 */
+#define ADC_SMPR2_SMP4 0x00007000U /*!<SMP4[2:0] bits (Channel 4 Sample time selection) */
+#define ADC_SMPR2_SMP4_0 0x00001000U /*!<Bit 0 */
+#define ADC_SMPR2_SMP4_1 0x00002000U /*!<Bit 1 */
+#define ADC_SMPR2_SMP4_2 0x00004000U /*!<Bit 2 */
+#define ADC_SMPR2_SMP5 0x00038000U /*!<SMP5[2:0] bits (Channel 5 Sample time selection) */
+#define ADC_SMPR2_SMP5_0 0x00008000U /*!<Bit 0 */
+#define ADC_SMPR2_SMP5_1 0x00010000U /*!<Bit 1 */
+#define ADC_SMPR2_SMP5_2 0x00020000U /*!<Bit 2 */
+#define ADC_SMPR2_SMP6 0x001C0000U /*!<SMP6[2:0] bits (Channel 6 Sample time selection) */
+#define ADC_SMPR2_SMP6_0 0x00040000U /*!<Bit 0 */
+#define ADC_SMPR2_SMP6_1 0x00080000U /*!<Bit 1 */
+#define ADC_SMPR2_SMP6_2 0x00100000U /*!<Bit 2 */
+#define ADC_SMPR2_SMP7 0x00E00000U /*!<SMP7[2:0] bits (Channel 7 Sample time selection) */
+#define ADC_SMPR2_SMP7_0 0x00200000U /*!<Bit 0 */
+#define ADC_SMPR2_SMP7_1 0x00400000U /*!<Bit 1 */
+#define ADC_SMPR2_SMP7_2 0x00800000U /*!<Bit 2 */
+#define ADC_SMPR2_SMP8 0x07000000U /*!<SMP8[2:0] bits (Channel 8 Sample time selection) */
+#define ADC_SMPR2_SMP8_0 0x01000000U /*!<Bit 0 */
+#define ADC_SMPR2_SMP8_1 0x02000000U /*!<Bit 1 */
+#define ADC_SMPR2_SMP8_2 0x04000000U /*!<Bit 2 */
+#define ADC_SMPR2_SMP9 0x38000000U /*!<SMP9[2:0] bits (Channel 9 Sample time selection) */
+#define ADC_SMPR2_SMP9_0 0x08000000U /*!<Bit 0 */
+#define ADC_SMPR2_SMP9_1 0x10000000U /*!<Bit 1 */
+#define ADC_SMPR2_SMP9_2 0x20000000U /*!<Bit 2 */
+
+/****************** Bit definition for ADC_JOFR1 register *******************/
+#define ADC_JOFR1_JOFFSET1 0x0FFFU /*!<Data offset for injected channel 1 */
+
+/****************** Bit definition for ADC_JOFR2 register *******************/
+#define ADC_JOFR2_JOFFSET2 0x0FFFU /*!<Data offset for injected channel 2 */
+
+/****************** Bit definition for ADC_JOFR3 register *******************/
+#define ADC_JOFR3_JOFFSET3 0x0FFFU /*!<Data offset for injected channel 3 */
+
+/****************** Bit definition for ADC_JOFR4 register *******************/
+#define ADC_JOFR4_JOFFSET4 0x0FFFU /*!<Data offset for injected channel 4 */
+
+/******************* Bit definition for ADC_HTR register ********************/
+#define ADC_HTR_HT 0x0FFFU /*!<Analog watchdog high threshold */
+
+/******************* Bit definition for ADC_LTR register ********************/
+#define ADC_LTR_LT 0x0FFFU /*!<Analog watchdog low threshold */
+
+/******************* Bit definition for ADC_SQR1 register *******************/
+#define ADC_SQR1_SQ13 0x0000001FU /*!<SQ13[4:0] bits (13th conversion in regular sequence) */
+#define ADC_SQR1_SQ13_0 0x00000001U /*!<Bit 0 */
+#define ADC_SQR1_SQ13_1 0x00000002U /*!<Bit 1 */
+#define ADC_SQR1_SQ13_2 0x00000004U /*!<Bit 2 */
+#define ADC_SQR1_SQ13_3 0x00000008U /*!<Bit 3 */
+#define ADC_SQR1_SQ13_4 0x00000010U /*!<Bit 4 */
+#define ADC_SQR1_SQ14 0x000003E0U /*!<SQ14[4:0] bits (14th conversion in regular sequence) */
+#define ADC_SQR1_SQ14_0 0x00000020U /*!<Bit 0 */
+#define ADC_SQR1_SQ14_1 0x00000040U /*!<Bit 1 */
+#define ADC_SQR1_SQ14_2 0x00000080U /*!<Bit 2 */
+#define ADC_SQR1_SQ14_3 0x00000100U /*!<Bit 3 */
+#define ADC_SQR1_SQ14_4 0x00000200U /*!<Bit 4 */
+#define ADC_SQR1_SQ15 0x00007C00U /*!<SQ15[4:0] bits (15th conversion in regular sequence) */
+#define ADC_SQR1_SQ15_0 0x00000400U /*!<Bit 0 */
+#define ADC_SQR1_SQ15_1 0x00000800U /*!<Bit 1 */
+#define ADC_SQR1_SQ15_2 0x00001000U /*!<Bit 2 */
+#define ADC_SQR1_SQ15_3 0x00002000U /*!<Bit 3 */
+#define ADC_SQR1_SQ15_4 0x00004000U /*!<Bit 4 */
+#define ADC_SQR1_SQ16 0x000F8000U /*!<SQ16[4:0] bits (16th conversion in regular sequence) */
+#define ADC_SQR1_SQ16_0 0x00008000U /*!<Bit 0 */
+#define ADC_SQR1_SQ16_1 0x00010000U /*!<Bit 1 */
+#define ADC_SQR1_SQ16_2 0x00020000U /*!<Bit 2 */
+#define ADC_SQR1_SQ16_3 0x00040000U /*!<Bit 3 */
+#define ADC_SQR1_SQ16_4 0x00080000U /*!<Bit 4 */
+#define ADC_SQR1_L 0x00F00000U /*!<L[3:0] bits (Regular channel sequence length) */
+#define ADC_SQR1_L_0 0x00100000U /*!<Bit 0 */
+#define ADC_SQR1_L_1 0x00200000U /*!<Bit 1 */
+#define ADC_SQR1_L_2 0x00400000U /*!<Bit 2 */
+#define ADC_SQR1_L_3 0x00800000U /*!<Bit 3 */
+
+/******************* Bit definition for ADC_SQR2 register *******************/
+#define ADC_SQR2_SQ7 0x0000001FU /*!<SQ7[4:0] bits (7th conversion in regular sequence) */
+#define ADC_SQR2_SQ7_0 0x00000001U /*!<Bit 0 */
+#define ADC_SQR2_SQ7_1 0x00000002U /*!<Bit 1 */
+#define ADC_SQR2_SQ7_2 0x00000004U /*!<Bit 2 */
+#define ADC_SQR2_SQ7_3 0x00000008U /*!<Bit 3 */
+#define ADC_SQR2_SQ7_4 0x00000010U /*!<Bit 4 */
+#define ADC_SQR2_SQ8 0x000003E0U /*!<SQ8[4:0] bits (8th conversion in regular sequence) */
+#define ADC_SQR2_SQ8_0 0x00000020U /*!<Bit 0 */
+#define ADC_SQR2_SQ8_1 0x00000040U /*!<Bit 1 */
+#define ADC_SQR2_SQ8_2 0x00000080U /*!<Bit 2 */
+#define ADC_SQR2_SQ8_3 0x00000100U /*!<Bit 3 */
+#define ADC_SQR2_SQ8_4 0x00000200U /*!<Bit 4 */
+#define ADC_SQR2_SQ9 0x00007C00U /*!<SQ9[4:0] bits (9th conversion in regular sequence) */
+#define ADC_SQR2_SQ9_0 0x00000400U /*!<Bit 0 */
+#define ADC_SQR2_SQ9_1 0x00000800U /*!<Bit 1 */
+#define ADC_SQR2_SQ9_2 0x00001000U /*!<Bit 2 */
+#define ADC_SQR2_SQ9_3 0x00002000U /*!<Bit 3 */
+#define ADC_SQR2_SQ9_4 0x00004000U /*!<Bit 4 */
+#define ADC_SQR2_SQ10 0x000F8000U /*!<SQ10[4:0] bits (10th conversion in regular sequence) */
+#define ADC_SQR2_SQ10_0 0x00008000U /*!<Bit 0 */
+#define ADC_SQR2_SQ10_1 0x00010000U /*!<Bit 1 */
+#define ADC_SQR2_SQ10_2 0x00020000U /*!<Bit 2 */
+#define ADC_SQR2_SQ10_3 0x00040000U /*!<Bit 3 */
+#define ADC_SQR2_SQ10_4 0x00080000U /*!<Bit 4 */
+#define ADC_SQR2_SQ11 0x01F00000U /*!<SQ11[4:0] bits (11th conversion in regular sequence) */
+#define ADC_SQR2_SQ11_0 0x00100000U /*!<Bit 0 */
+#define ADC_SQR2_SQ11_1 0x00200000U /*!<Bit 1 */
+#define ADC_SQR2_SQ11_2 0x00400000U /*!<Bit 2 */
+#define ADC_SQR2_SQ11_3 0x00800000U /*!<Bit 3 */
+#define ADC_SQR2_SQ11_4 0x01000000U /*!<Bit 4 */
+#define ADC_SQR2_SQ12 0x3E000000U /*!<SQ12[4:0] bits (12th conversion in regular sequence) */
+#define ADC_SQR2_SQ12_0 0x02000000U /*!<Bit 0 */
+#define ADC_SQR2_SQ12_1 0x04000000U /*!<Bit 1 */
+#define ADC_SQR2_SQ12_2 0x08000000U /*!<Bit 2 */
+#define ADC_SQR2_SQ12_3 0x10000000U /*!<Bit 3 */
+#define ADC_SQR2_SQ12_4 0x20000000U /*!<Bit 4 */
+
+/******************* Bit definition for ADC_SQR3 register *******************/
+#define ADC_SQR3_SQ1 0x0000001FU /*!<SQ1[4:0] bits (1st conversion in regular sequence) */
+#define ADC_SQR3_SQ1_0 0x00000001U /*!<Bit 0 */
+#define ADC_SQR3_SQ1_1 0x00000002U /*!<Bit 1 */
+#define ADC_SQR3_SQ1_2 0x00000004U /*!<Bit 2 */
+#define ADC_SQR3_SQ1_3 0x00000008U /*!<Bit 3 */
+#define ADC_SQR3_SQ1_4 0x00000010U /*!<Bit 4 */
+#define ADC_SQR3_SQ2 0x000003E0U /*!<SQ2[4:0] bits (2nd conversion in regular sequence) */
+#define ADC_SQR3_SQ2_0 0x00000020U /*!<Bit 0 */
+#define ADC_SQR3_SQ2_1 0x00000040U /*!<Bit 1 */
+#define ADC_SQR3_SQ2_2 0x00000080U /*!<Bit 2 */
+#define ADC_SQR3_SQ2_3 0x00000100U /*!<Bit 3 */
+#define ADC_SQR3_SQ2_4 0x00000200U /*!<Bit 4 */
+#define ADC_SQR3_SQ3 0x00007C00U /*!<SQ3[4:0] bits (3rd conversion in regular sequence) */
+#define ADC_SQR3_SQ3_0 0x00000400U /*!<Bit 0 */
+#define ADC_SQR3_SQ3_1 0x00000800U /*!<Bit 1 */
+#define ADC_SQR3_SQ3_2 0x00001000U /*!<Bit 2 */
+#define ADC_SQR3_SQ3_3 0x00002000U /*!<Bit 3 */
+#define ADC_SQR3_SQ3_4 0x00004000U /*!<Bit 4 */
+#define ADC_SQR3_SQ4 0x000F8000U /*!<SQ4[4:0] bits (4th conversion in regular sequence) */
+#define ADC_SQR3_SQ4_0 0x00008000U /*!<Bit 0 */
+#define ADC_SQR3_SQ4_1 0x00010000U /*!<Bit 1 */
+#define ADC_SQR3_SQ4_2 0x00020000U /*!<Bit 2 */
+#define ADC_SQR3_SQ4_3 0x00040000U /*!<Bit 3 */
+#define ADC_SQR3_SQ4_4 0x00080000U /*!<Bit 4 */
+#define ADC_SQR3_SQ5 0x01F00000U /*!<SQ5[4:0] bits (5th conversion in regular sequence) */
+#define ADC_SQR3_SQ5_0 0x00100000U /*!<Bit 0 */
+#define ADC_SQR3_SQ5_1 0x00200000U /*!<Bit 1 */
+#define ADC_SQR3_SQ5_2 0x00400000U /*!<Bit 2 */
+#define ADC_SQR3_SQ5_3 0x00800000U /*!<Bit 3 */
+#define ADC_SQR3_SQ5_4 0x01000000U /*!<Bit 4 */
+#define ADC_SQR3_SQ6 0x3E000000U /*!<SQ6[4:0] bits (6th conversion in regular sequence) */
+#define ADC_SQR3_SQ6_0 0x02000000U /*!<Bit 0 */
+#define ADC_SQR3_SQ6_1 0x04000000U /*!<Bit 1 */
+#define ADC_SQR3_SQ6_2 0x08000000U /*!<Bit 2 */
+#define ADC_SQR3_SQ6_3 0x10000000U /*!<Bit 3 */
+#define ADC_SQR3_SQ6_4 0x20000000U /*!<Bit 4 */
+
+/******************* Bit definition for ADC_JSQR register *******************/
+#define ADC_JSQR_JSQ1 0x0000001FU /*!<JSQ1[4:0] bits (1st conversion in injected sequence) */
+#define ADC_JSQR_JSQ1_0 0x00000001U /*!<Bit 0 */
+#define ADC_JSQR_JSQ1_1 0x00000002U /*!<Bit 1 */
+#define ADC_JSQR_JSQ1_2 0x00000004U /*!<Bit 2 */
+#define ADC_JSQR_JSQ1_3 0x00000008U /*!<Bit 3 */
+#define ADC_JSQR_JSQ1_4 0x00000010U /*!<Bit 4 */
+#define ADC_JSQR_JSQ2 0x000003E0U /*!<JSQ2[4:0] bits (2nd conversion in injected sequence) */
+#define ADC_JSQR_JSQ2_0 0x00000020U /*!<Bit 0 */
+#define ADC_JSQR_JSQ2_1 0x00000040U /*!<Bit 1 */
+#define ADC_JSQR_JSQ2_2 0x00000080U /*!<Bit 2 */
+#define ADC_JSQR_JSQ2_3 0x00000100U /*!<Bit 3 */
+#define ADC_JSQR_JSQ2_4 0x00000200U /*!<Bit 4 */
+#define ADC_JSQR_JSQ3 0x00007C00U /*!<JSQ3[4:0] bits (3rd conversion in injected sequence) */
+#define ADC_JSQR_JSQ3_0 0x00000400U /*!<Bit 0 */
+#define ADC_JSQR_JSQ3_1 0x00000800U /*!<Bit 1 */
+#define ADC_JSQR_JSQ3_2 0x00001000U /*!<Bit 2 */
+#define ADC_JSQR_JSQ3_3 0x00002000U /*!<Bit 3 */
+#define ADC_JSQR_JSQ3_4 0x00004000U /*!<Bit 4 */
+#define ADC_JSQR_JSQ4 0x000F8000U /*!<JSQ4[4:0] bits (4th conversion in injected sequence) */
+#define ADC_JSQR_JSQ4_0 0x00008000U /*!<Bit 0 */
+#define ADC_JSQR_JSQ4_1 0x00010000U /*!<Bit 1 */
+#define ADC_JSQR_JSQ4_2 0x00020000U /*!<Bit 2 */
+#define ADC_JSQR_JSQ4_3 0x00040000U /*!<Bit 3 */
+#define ADC_JSQR_JSQ4_4 0x00080000U /*!<Bit 4 */
+#define ADC_JSQR_JL 0x00300000U /*!<JL[1:0] bits (Injected Sequence length) */
+#define ADC_JSQR_JL_0 0x00100000U /*!<Bit 0 */
+#define ADC_JSQR_JL_1 0x00200000U /*!<Bit 1 */
+
+/******************* Bit definition for ADC_JDR1 register *******************/
+#define ADC_JDR1_JDATA 0xFFFFU /*!<Injected data */
+
+/******************* Bit definition for ADC_JDR2 register *******************/
+#define ADC_JDR2_JDATA 0xFFFFU /*!<Injected data */
+
+/******************* Bit definition for ADC_JDR3 register *******************/
+#define ADC_JDR3_JDATA 0xFFFFU /*!<Injected data */
+
+/******************* Bit definition for ADC_JDR4 register *******************/
+#define ADC_JDR4_JDATA 0xFFFFU /*!<Injected data */
+
+/******************** Bit definition for ADC_DR register ********************/
+#define ADC_DR_DATA 0x0000FFFFU /*!<Regular data */
+#define ADC_DR_ADC2DATA 0xFFFF0000U /*!<ADC2 data */
+
+/******************* Bit definition for ADC_CSR register ********************/
+#define ADC_CSR_AWD1 0x00000001U /*!<ADC1 Analog watchdog flag */
+#define ADC_CSR_EOC1 0x00000002U /*!<ADC1 End of conversion */
+#define ADC_CSR_JEOC1 0x00000004U /*!<ADC1 Injected channel end of conversion */
+#define ADC_CSR_JSTRT1 0x00000008U /*!<ADC1 Injected channel Start flag */
+#define ADC_CSR_STRT1 0x00000010U /*!<ADC1 Regular channel Start flag */
+#define ADC_CSR_OVR1 0x00000020U /*!<ADC1 DMA overrun flag */
+#define ADC_CSR_AWD2 0x00000100U /*!<ADC2 Analog watchdog flag */
+#define ADC_CSR_EOC2 0x00000200U /*!<ADC2 End of conversion */
+#define ADC_CSR_JEOC2 0x00000400U /*!<ADC2 Injected channel end of conversion */
+#define ADC_CSR_JSTRT2 0x00000800U /*!<ADC2 Injected channel Start flag */
+#define ADC_CSR_STRT2 0x00001000U /*!<ADC2 Regular channel Start flag */
+#define ADC_CSR_OVR2 0x00002000U /*!<ADC2 DMA overrun flag */
+#define ADC_CSR_AWD3 0x00010000U /*!<ADC3 Analog watchdog flag */
+#define ADC_CSR_EOC3 0x00020000U /*!<ADC3 End of conversion */
+#define ADC_CSR_JEOC3 0x00040000U /*!<ADC3 Injected channel end of conversion */
+#define ADC_CSR_JSTRT3 0x00080000U /*!<ADC3 Injected channel Start flag */
+#define ADC_CSR_STRT3 0x00100000U /*!<ADC3 Regular channel Start flag */
+#define ADC_CSR_OVR3 0x00200000U /*!<ADC3 DMA overrun flag */
+
+/* Legacy defines */
+#define ADC_CSR_DOVR1 ADC_CSR_OVR1
+#define ADC_CSR_DOVR2 ADC_CSR_OVR2
+#define ADC_CSR_DOVR3 ADC_CSR_OVR3
+
+/******************* Bit definition for ADC_CCR register ********************/
+#define ADC_CCR_MULTI 0x0000001FU /*!<MULTI[4:0] bits (Multi-ADC mode selection) */
+#define ADC_CCR_MULTI_0 0x00000001U /*!<Bit 0 */
+#define ADC_CCR_MULTI_1 0x00000002U /*!<Bit 1 */
+#define ADC_CCR_MULTI_2 0x00000004U /*!<Bit 2 */
+#define ADC_CCR_MULTI_3 0x00000008U /*!<Bit 3 */
+#define ADC_CCR_MULTI_4 0x00000010U /*!<Bit 4 */
+#define ADC_CCR_DELAY 0x00000F00U /*!<DELAY[3:0] bits (Delay between 2 sampling phases) */
+#define ADC_CCR_DELAY_0 0x00000100U /*!<Bit 0 */
+#define ADC_CCR_DELAY_1 0x00000200U /*!<Bit 1 */
+#define ADC_CCR_DELAY_2 0x00000400U /*!<Bit 2 */
+#define ADC_CCR_DELAY_3 0x00000800U /*!<Bit 3 */
+#define ADC_CCR_DDS 0x00002000U /*!<DMA disable selection (Multi-ADC mode) */
+#define ADC_CCR_DMA 0x0000C000U /*!<DMA[1:0] bits (Direct Memory Access mode for multimode) */
+#define ADC_CCR_DMA_0 0x00004000U /*!<Bit 0 */
+#define ADC_CCR_DMA_1 0x00008000U /*!<Bit 1 */
+#define ADC_CCR_ADCPRE 0x00030000U /*!<ADCPRE[1:0] bits (ADC prescaler) */
+#define ADC_CCR_ADCPRE_0 0x00010000U /*!<Bit 0 */
+#define ADC_CCR_ADCPRE_1 0x00020000U /*!<Bit 1 */
+#define ADC_CCR_VBATE 0x00400000U /*!<VBAT Enable */
+#define ADC_CCR_TSVREFE 0x00800000U /*!<Temperature Sensor and VREFINT Enable */
+
+/******************* Bit definition for ADC_CDR register ********************/
+#define ADC_CDR_DATA1 0x0000FFFFU /*!<1st data of a pair of regular conversions */
+#define ADC_CDR_DATA2 0xFFFF0000U /*!<2nd data of a pair of regular conversions */
+
+/******************************************************************************/
+/* */
+/* Controller Area Network */
+/* */
+/******************************************************************************/
+/*!<CAN control and status registers */
+/******************* Bit definition for CAN_MCR register ********************/
+#define CAN_MCR_INRQ 0x00000001U /*!<Initialization Request */
+#define CAN_MCR_SLEEP 0x00000002U /*!<Sleep Mode Request */
+#define CAN_MCR_TXFP 0x00000004U /*!<Transmit FIFO Priority */
+#define CAN_MCR_RFLM 0x00000008U /*!<Receive FIFO Locked Mode */
+#define CAN_MCR_NART 0x00000010U /*!<No Automatic Retransmission */
+#define CAN_MCR_AWUM 0x00000020U /*!<Automatic Wakeup Mode */
+#define CAN_MCR_ABOM 0x00000040U /*!<Automatic Bus-Off Management */
+#define CAN_MCR_TTCM 0x00000080U /*!<Time Triggered Communication Mode */
+#define CAN_MCR_RESET 0x00008000U /*!<bxCAN software master reset */
+#define CAN_MCR_DBF 0x00010000U /*!<bxCAN Debug freeze */
+/******************* Bit definition for CAN_MSR register ********************/
+#define CAN_MSR_INAK 0x0001U /*!<Initialization Acknowledge */
+#define CAN_MSR_SLAK 0x0002U /*!<Sleep Acknowledge */
+#define CAN_MSR_ERRI 0x0004U /*!<Error Interrupt */
+#define CAN_MSR_WKUI 0x0008U /*!<Wakeup Interrupt */
+#define CAN_MSR_SLAKI 0x0010U /*!<Sleep Acknowledge Interrupt */
+#define CAN_MSR_TXM 0x0100U /*!<Transmit Mode */
+#define CAN_MSR_RXM 0x0200U /*!<Receive Mode */
+#define CAN_MSR_SAMP 0x0400U /*!<Last Sample Point */
+#define CAN_MSR_RX 0x0800U /*!<CAN Rx Signal */
+
+/******************* Bit definition for CAN_TSR register ********************/
+#define CAN_TSR_RQCP0 0x00000001U /*!<Request Completed Mailbox0 */
+#define CAN_TSR_TXOK0 0x00000002U /*!<Transmission OK of Mailbox0 */
+#define CAN_TSR_ALST0 0x00000004U /*!<Arbitration Lost for Mailbox0 */
+#define CAN_TSR_TERR0 0x00000008U /*!<Transmission Error of Mailbox0 */
+#define CAN_TSR_ABRQ0 0x00000080U /*!<Abort Request for Mailbox0 */
+#define CAN_TSR_RQCP1 0x00000100U /*!<Request Completed Mailbox1 */
+#define CAN_TSR_TXOK1 0x00000200U /*!<Transmission OK of Mailbox1 */
+#define CAN_TSR_ALST1 0x00000400U /*!<Arbitration Lost for Mailbox1 */
+#define CAN_TSR_TERR1 0x00000800U /*!<Transmission Error of Mailbox1 */
+#define CAN_TSR_ABRQ1 0x00008000U /*!<Abort Request for Mailbox 1 */
+#define CAN_TSR_RQCP2 0x00010000U /*!<Request Completed Mailbox2 */
+#define CAN_TSR_TXOK2 0x00020000U /*!<Transmission OK of Mailbox 2 */
+#define CAN_TSR_ALST2 0x00040000U /*!<Arbitration Lost for mailbox 2 */
+#define CAN_TSR_TERR2 0x00080000U /*!<Transmission Error of Mailbox 2 */
+#define CAN_TSR_ABRQ2 0x00800000U /*!<Abort Request for Mailbox 2 */
+#define CAN_TSR_CODE 0x03000000U /*!<Mailbox Code */
+
+#define CAN_TSR_TME 0x1C000000U /*!<TME[2:0] bits */
+#define CAN_TSR_TME0 0x04000000U /*!<Transmit Mailbox 0 Empty */
+#define CAN_TSR_TME1 0x08000000U /*!<Transmit Mailbox 1 Empty */
+#define CAN_TSR_TME2 0x10000000U /*!<Transmit Mailbox 2 Empty */
+
+#define CAN_TSR_LOW 0xE0000000U /*!<LOW[2:0] bits */
+#define CAN_TSR_LOW0 0x20000000U /*!<Lowest Priority Flag for Mailbox 0 */
+#define CAN_TSR_LOW1 0x40000000U /*!<Lowest Priority Flag for Mailbox 1 */
+#define CAN_TSR_LOW2 0x80000000U /*!<Lowest Priority Flag for Mailbox 2 */
+
+/******************* Bit definition for CAN_RF0R register *******************/
+#define CAN_RF0R_FMP0 0x03U /*!<FIFO 0 Message Pending */
+#define CAN_RF0R_FULL0 0x08U /*!<FIFO 0 Full */
+#define CAN_RF0R_FOVR0 0x10U /*!<FIFO 0 Overrun */
+#define CAN_RF0R_RFOM0 0x20U /*!<Release FIFO 0 Output Mailbox */
+
+/******************* Bit definition for CAN_RF1R register *******************/
+#define CAN_RF1R_FMP1 0x03U /*!<FIFO 1 Message Pending */
+#define CAN_RF1R_FULL1 0x08U /*!<FIFO 1 Full */
+#define CAN_RF1R_FOVR1 0x10U /*!<FIFO 1 Overrun */
+#define CAN_RF1R_RFOM1 0x20U /*!<Release FIFO 1 Output Mailbox */
+
+/******************** Bit definition for CAN_IER register *******************/
+#define CAN_IER_TMEIE 0x00000001U /*!<Transmit Mailbox Empty Interrupt Enable */
+#define CAN_IER_FMPIE0 0x00000002U /*!<FIFO Message Pending Interrupt Enable */
+#define CAN_IER_FFIE0 0x00000004U /*!<FIFO Full Interrupt Enable */
+#define CAN_IER_FOVIE0 0x00000008U /*!<FIFO Overrun Interrupt Enable */
+#define CAN_IER_FMPIE1 0x00000010U /*!<FIFO Message Pending Interrupt Enable */
+#define CAN_IER_FFIE1 0x00000020U /*!<FIFO Full Interrupt Enable */
+#define CAN_IER_FOVIE1 0x00000040U /*!<FIFO Overrun Interrupt Enable */
+#define CAN_IER_EWGIE 0x00000100U /*!<Error Warning Interrupt Enable */
+#define CAN_IER_EPVIE 0x00000200U /*!<Error Passive Interrupt Enable */
+#define CAN_IER_BOFIE 0x00000400U /*!<Bus-Off Interrupt Enable */
+#define CAN_IER_LECIE 0x00000800U /*!<Last Error Code Interrupt Enable */
+#define CAN_IER_ERRIE 0x00008000U /*!<Error Interrupt Enable */
+#define CAN_IER_WKUIE 0x00010000U /*!<Wakeup Interrupt Enable */
+#define CAN_IER_SLKIE 0x00020000U /*!<Sleep Interrupt Enable */
+#define CAN_IER_EWGIE 0x00000100U /*!<Error warning interrupt enable */
+#define CAN_IER_EPVIE 0x00000200U /*!<Error passive interrupt enable */
+#define CAN_IER_BOFIE 0x00000400U /*!<Bus-off interrupt enable */
+#define CAN_IER_LECIE 0x00000800U /*!<Last error code interrupt enable */
+#define CAN_IER_ERRIE 0x00008000U /*!<Error interrupt enable */
+
+
+/******************** Bit definition for CAN_ESR register *******************/
+#define CAN_ESR_EWGF 0x00000001U /*!<Error Warning Flag */
+#define CAN_ESR_EPVF 0x00000002U /*!<Error Passive Flag */
+#define CAN_ESR_BOFF 0x00000004U /*!<Bus-Off Flag */
+
+#define CAN_ESR_LEC 0x00000070U /*!<LEC[2:0] bits (Last Error Code) */
+#define CAN_ESR_LEC_0 0x00000010U /*!<Bit 0 */
+#define CAN_ESR_LEC_1 0x00000020U /*!<Bit 1 */
+#define CAN_ESR_LEC_2 0x00000040U /*!<Bit 2 */
+
+#define CAN_ESR_TEC 0x00FF0000U /*!<Least significant byte of the 9-bit Transmit Error Counter */
+#define CAN_ESR_REC 0xFF000000U /*!<Receive Error Counter */
+
+/******************* Bit definition for CAN_BTR register ********************/
+#define CAN_BTR_BRP 0x000003FFU /*!<Baud Rate Prescaler */
+#define CAN_BTR_TS1 0x000F0000U /*!<Time Segment 1 */
+#define CAN_BTR_TS1_0 0x00010000U /*!<Bit 0 */
+#define CAN_BTR_TS1_1 0x00020000U /*!<Bit 1 */
+#define CAN_BTR_TS1_2 0x00040000U /*!<Bit 2 */
+#define CAN_BTR_TS1_3 0x00080000U /*!<Bit 3 */
+#define CAN_BTR_TS2 0x00700000U /*!<Time Segment 2 */
+#define CAN_BTR_TS2_0 0x00100000U /*!<Bit 0 */
+#define CAN_BTR_TS2_1 0x00200000U /*!<Bit 1 */
+#define CAN_BTR_TS2_2 0x00400000U /*!<Bit 2 */
+#define CAN_BTR_SJW 0x03000000U /*!<Resynchronization Jump Width */
+#define CAN_BTR_SJW_0 0x01000000U /*!<Bit 0 */
+#define CAN_BTR_SJW_1 0x02000000U /*!<Bit 1 */
+#define CAN_BTR_LBKM 0x40000000U /*!<Loop Back Mode (Debug) */
+#define CAN_BTR_SILM 0x80000000U /*!<Silent Mode */
+
+
+/*!<Mailbox registers */
+/****************** Bit definition for CAN_TI0R register ********************/
+#define CAN_TI0R_TXRQ 0x00000001U /*!<Transmit Mailbox Request */
+#define CAN_TI0R_RTR 0x00000002U /*!<Remote Transmission Request */
+#define CAN_TI0R_IDE 0x00000004U /*!<Identifier Extension */
+#define CAN_TI0R_EXID 0x001FFFF8U /*!<Extended Identifier */
+#define CAN_TI0R_STID 0xFFE00000U /*!<Standard Identifier or Extended Identifier */
+
+/****************** Bit definition for CAN_TDT0R register *******************/
+#define CAN_TDT0R_DLC 0x0000000FU /*!<Data Length Code */
+#define CAN_TDT0R_TGT 0x00000100U /*!<Transmit Global Time */
+#define CAN_TDT0R_TIME 0xFFFF0000U /*!<Message Time Stamp */
+
+/****************** Bit definition for CAN_TDL0R register *******************/
+#define CAN_TDL0R_DATA0 0x000000FFU /*!<Data byte 0 */
+#define CAN_TDL0R_DATA1 0x0000FF00U /*!<Data byte 1 */
+#define CAN_TDL0R_DATA2 0x00FF0000U /*!<Data byte 2 */
+#define CAN_TDL0R_DATA3 0xFF000000U /*!<Data byte 3 */
+
+/****************** Bit definition for CAN_TDH0R register *******************/
+#define CAN_TDH0R_DATA4 0x000000FFU /*!<Data byte 4 */
+#define CAN_TDH0R_DATA5 0x0000FF00U /*!<Data byte 5 */
+#define CAN_TDH0R_DATA6 0x00FF0000U /*!<Data byte 6 */
+#define CAN_TDH0R_DATA7 0xFF000000U /*!<Data byte 7 */
+
+/******************* Bit definition for CAN_TI1R register *******************/
+#define CAN_TI1R_TXRQ 0x00000001U /*!<Transmit Mailbox Request */
+#define CAN_TI1R_RTR 0x00000002U /*!<Remote Transmission Request */
+#define CAN_TI1R_IDE 0x00000004U /*!<Identifier Extension */
+#define CAN_TI1R_EXID 0x001FFFF8U /*!<Extended Identifier */
+#define CAN_TI1R_STID 0xFFE00000U /*!<Standard Identifier or Extended Identifier */
+
+/******************* Bit definition for CAN_TDT1R register ******************/
+#define CAN_TDT1R_DLC 0x0000000FU /*!<Data Length Code */
+#define CAN_TDT1R_TGT 0x00000100U /*!<Transmit Global Time */
+#define CAN_TDT1R_TIME 0xFFFF0000U /*!<Message Time Stamp */
+
+/******************* Bit definition for CAN_TDL1R register ******************/
+#define CAN_TDL1R_DATA0 0x000000FFU /*!<Data byte 0 */
+#define CAN_TDL1R_DATA1 0x0000FF00U /*!<Data byte 1 */
+#define CAN_TDL1R_DATA2 0x00FF0000U /*!<Data byte 2 */
+#define CAN_TDL1R_DATA3 0xFF000000U /*!<Data byte 3 */
+
+/******************* Bit definition for CAN_TDH1R register ******************/
+#define CAN_TDH1R_DATA4 0x000000FFU /*!<Data byte 4 */
+#define CAN_TDH1R_DATA5 0x0000FF00U /*!<Data byte 5 */
+#define CAN_TDH1R_DATA6 0x00FF0000U /*!<Data byte 6 */
+#define CAN_TDH1R_DATA7 0xFF000000U /*!<Data byte 7 */
+
+/******************* Bit definition for CAN_TI2R register *******************/
+#define CAN_TI2R_TXRQ 0x00000001U /*!<Transmit Mailbox Request */
+#define CAN_TI2R_RTR 0x00000002U /*!<Remote Transmission Request */
+#define CAN_TI2R_IDE 0x00000004U /*!<Identifier Extension */
+#define CAN_TI2R_EXID 0x001FFFF8U /*!<Extended identifier */
+#define CAN_TI2R_STID 0xFFE00000U /*!<Standard Identifier or Extended Identifier */
+
+/******************* Bit definition for CAN_TDT2R register ******************/
+#define CAN_TDT2R_DLC 0x0000000FU /*!<Data Length Code */
+#define CAN_TDT2R_TGT 0x00000100U /*!<Transmit Global Time */
+#define CAN_TDT2R_TIME 0xFFFF0000U /*!<Message Time Stamp */
+
+/******************* Bit definition for CAN_TDL2R register ******************/
+#define CAN_TDL2R_DATA0 0x000000FFU /*!<Data byte 0 */
+#define CAN_TDL2R_DATA1 0x0000FF00U /*!<Data byte 1 */
+#define CAN_TDL2R_DATA2 0x00FF0000U /*!<Data byte 2 */
+#define CAN_TDL2R_DATA3 0xFF000000U /*!<Data byte 3 */
+
+/******************* Bit definition for CAN_TDH2R register ******************/
+#define CAN_TDH2R_DATA4 0x000000FFU /*!<Data byte 4 */
+#define CAN_TDH2R_DATA5 0x0000FF00U /*!<Data byte 5 */
+#define CAN_TDH2R_DATA6 0x00FF0000U /*!<Data byte 6 */
+#define CAN_TDH2R_DATA7 0xFF000000U /*!<Data byte 7 */
+
+/******************* Bit definition for CAN_RI0R register *******************/
+#define CAN_RI0R_RTR 0x00000002U /*!<Remote Transmission Request */
+#define CAN_RI0R_IDE 0x00000004U /*!<Identifier Extension */
+#define CAN_RI0R_EXID 0x001FFFF8U /*!<Extended Identifier */
+#define CAN_RI0R_STID 0xFFE00000U /*!<Standard Identifier or Extended Identifier */
+
+/******************* Bit definition for CAN_RDT0R register ******************/
+#define CAN_RDT0R_DLC 0x0000000FU /*!<Data Length Code */
+#define CAN_RDT0R_FMI 0x0000FF00U /*!<Filter Match Index */
+#define CAN_RDT0R_TIME 0xFFFF0000U /*!<Message Time Stamp */
+
+/******************* Bit definition for CAN_RDL0R register ******************/
+#define CAN_RDL0R_DATA0 0x000000FFU /*!<Data byte 0 */
+#define CAN_RDL0R_DATA1 0x0000FF00U /*!<Data byte 1 */
+#define CAN_RDL0R_DATA2 0x00FF0000U /*!<Data byte 2 */
+#define CAN_RDL0R_DATA3 0xFF000000U /*!<Data byte 3 */
+
+/******************* Bit definition for CAN_RDH0R register ******************/
+#define CAN_RDH0R_DATA4 0x000000FFU /*!<Data byte 4 */
+#define CAN_RDH0R_DATA5 0x0000FF00U /*!<Data byte 5 */
+#define CAN_RDH0R_DATA6 0x00FF0000U /*!<Data byte 6 */
+#define CAN_RDH0R_DATA7 0xFF000000U /*!<Data byte 7 */
+
+/******************* Bit definition for CAN_RI1R register *******************/
+#define CAN_RI1R_RTR 0x00000002U /*!<Remote Transmission Request */
+#define CAN_RI1R_IDE 0x00000004U /*!<Identifier Extension */
+#define CAN_RI1R_EXID 0x001FFFF8U /*!<Extended identifier */
+#define CAN_RI1R_STID 0xFFE00000U /*!<Standard Identifier or Extended Identifier */
+
+/******************* Bit definition for CAN_RDT1R register ******************/
+#define CAN_RDT1R_DLC 0x0000000FU /*!<Data Length Code */
+#define CAN_RDT1R_FMI 0x0000FF00U /*!<Filter Match Index */
+#define CAN_RDT1R_TIME 0xFFFF0000U /*!<Message Time Stamp */
+
+/******************* Bit definition for CAN_RDL1R register ******************/
+#define CAN_RDL1R_DATA0 0x000000FFU /*!<Data byte 0 */
+#define CAN_RDL1R_DATA1 0x0000FF00U /*!<Data byte 1 */
+#define CAN_RDL1R_DATA2 0x00FF0000U /*!<Data byte 2 */
+#define CAN_RDL1R_DATA3 0xFF000000U /*!<Data byte 3 */
+
+/******************* Bit definition for CAN_RDH1R register ******************/
+#define CAN_RDH1R_DATA4 0x000000FFU /*!<Data byte 4 */
+#define CAN_RDH1R_DATA5 0x0000FF00U /*!<Data byte 5 */
+#define CAN_RDH1R_DATA6 0x00FF0000U /*!<Data byte 6 */
+#define CAN_RDH1R_DATA7 0xFF000000U /*!<Data byte 7 */
+
+/*!<CAN filter registers */
+/******************* Bit definition for CAN_FMR register ********************/
+#define CAN_FMR_FINIT 0x01U /*!<Filter Init Mode */
+#define CAN_FMR_CAN2SB 0x00003F00U /*!<CAN2 start bank */
+
+/******************* Bit definition for CAN_FM1R register *******************/
+#define CAN_FM1R_FBM 0x0FFFFFFFU /*!<Filter Mode */
+#define CAN_FM1R_FBM0 0x00000001U /*!<Filter Init Mode bit 0 */
+#define CAN_FM1R_FBM1 0x00000002U /*!<Filter Init Mode bit 1 */
+#define CAN_FM1R_FBM2 0x00000004U /*!<Filter Init Mode bit 2 */
+#define CAN_FM1R_FBM3 0x00000008U /*!<Filter Init Mode bit 3 */
+#define CAN_FM1R_FBM4 0x00000010U /*!<Filter Init Mode bit 4 */
+#define CAN_FM1R_FBM5 0x00000020U /*!<Filter Init Mode bit 5 */
+#define CAN_FM1R_FBM6 0x00000040U /*!<Filter Init Mode bit 6 */
+#define CAN_FM1R_FBM7 0x00000080U /*!<Filter Init Mode bit 7 */
+#define CAN_FM1R_FBM8 0x00000100U /*!<Filter Init Mode bit 8 */
+#define CAN_FM1R_FBM9 0x00000200U /*!<Filter Init Mode bit 9 */
+#define CAN_FM1R_FBM10 0x00000400U /*!<Filter Init Mode bit 10 */
+#define CAN_FM1R_FBM11 0x00000800U /*!<Filter Init Mode bit 11 */
+#define CAN_FM1R_FBM12 0x00001000U /*!<Filter Init Mode bit 12 */
+#define CAN_FM1R_FBM13 0x00002000U /*!<Filter Init Mode bit 13 */
+#define CAN_FM1R_FBM14 0x00004000U /*!<Filter Init Mode bit 14 */
+#define CAN_FM1R_FBM15 0x00008000U /*!<Filter Init Mode bit 15 */
+#define CAN_FM1R_FBM16 0x00010000U /*!<Filter Init Mode bit 16 */
+#define CAN_FM1R_FBM17 0x00020000U /*!<Filter Init Mode bit 17 */
+#define CAN_FM1R_FBM18 0x00040000U /*!<Filter Init Mode bit 18 */
+#define CAN_FM1R_FBM19 0x00080000U /*!<Filter Init Mode bit 19 */
+#define CAN_FM1R_FBM20 0x00100000U /*!<Filter Init Mode bit 20 */
+#define CAN_FM1R_FBM21 0x00200000U /*!<Filter Init Mode bit 21 */
+#define CAN_FM1R_FBM22 0x00400000U /*!<Filter Init Mode bit 22 */
+#define CAN_FM1R_FBM23 0x00800000U /*!<Filter Init Mode bit 23 */
+#define CAN_FM1R_FBM24 0x01000000U /*!<Filter Init Mode bit 24 */
+#define CAN_FM1R_FBM25 0x02000000U /*!<Filter Init Mode bit 25 */
+#define CAN_FM1R_FBM26 0x04000000U /*!<Filter Init Mode bit 26 */
+#define CAN_FM1R_FBM27 0x08000000U /*!<Filter Init Mode bit 27 */
+
+/******************* Bit definition for CAN_FS1R register *******************/
+#define CAN_FS1R_FSC 0x0FFFFFFFU /*!<Filter Scale Configuration */
+#define CAN_FS1R_FSC0 0x00000001U /*!<Filter Scale Configuration bit 0 */
+#define CAN_FS1R_FSC1 0x00000002U /*!<Filter Scale Configuration bit 1 */
+#define CAN_FS1R_FSC2 0x00000004U /*!<Filter Scale Configuration bit 2 */
+#define CAN_FS1R_FSC3 0x00000008U /*!<Filter Scale Configuration bit 3 */
+#define CAN_FS1R_FSC4 0x00000010U /*!<Filter Scale Configuration bit 4 */
+#define CAN_FS1R_FSC5 0x00000020U /*!<Filter Scale Configuration bit 5 */
+#define CAN_FS1R_FSC6 0x00000040U /*!<Filter Scale Configuration bit 6 */
+#define CAN_FS1R_FSC7 0x00000080U /*!<Filter Scale Configuration bit 7 */
+#define CAN_FS1R_FSC8 0x00000100U /*!<Filter Scale Configuration bit 8 */
+#define CAN_FS1R_FSC9 0x00000200U /*!<Filter Scale Configuration bit 9 */
+#define CAN_FS1R_FSC10 0x00000400U /*!<Filter Scale Configuration bit 10 */
+#define CAN_FS1R_FSC11 0x00000800U /*!<Filter Scale Configuration bit 11 */
+#define CAN_FS1R_FSC12 0x00001000U /*!<Filter Scale Configuration bit 12 */
+#define CAN_FS1R_FSC13 0x00002000U /*!<Filter Scale Configuration bit 13 */
+#define CAN_FS1R_FSC14 0x00004000U /*!<Filter Scale Configuration bit 14 */
+#define CAN_FS1R_FSC15 0x00008000U /*!<Filter Scale Configuration bit 15 */
+#define CAN_FS1R_FSC16 0x00010000U /*!<Filter Scale Configuration bit 16 */
+#define CAN_FS1R_FSC17 0x00020000U /*!<Filter Scale Configuration bit 17 */
+#define CAN_FS1R_FSC18 0x00040000U /*!<Filter Scale Configuration bit 18 */
+#define CAN_FS1R_FSC19 0x00080000U /*!<Filter Scale Configuration bit 19 */
+#define CAN_FS1R_FSC20 0x00100000U /*!<Filter Scale Configuration bit 20 */
+#define CAN_FS1R_FSC21 0x00200000U /*!<Filter Scale Configuration bit 21 */
+#define CAN_FS1R_FSC22 0x00400000U /*!<Filter Scale Configuration bit 22 */
+#define CAN_FS1R_FSC23 0x00800000U /*!<Filter Scale Configuration bit 23 */
+#define CAN_FS1R_FSC24 0x01000000U /*!<Filter Scale Configuration bit 24 */
+#define CAN_FS1R_FSC25 0x02000000U /*!<Filter Scale Configuration bit 25 */
+#define CAN_FS1R_FSC26 0x04000000U /*!<Filter Scale Configuration bit 26 */
+#define CAN_FS1R_FSC27 0x08000000U /*!<Filter Scale Configuration bit 27 */
+
+/****************** Bit definition for CAN_FFA1R register *******************/
+#define CAN_FFA1R_FFA 0x0FFFFFFFU /*!<Filter FIFO Assignment */
+#define CAN_FFA1R_FFA0 0x00000001U /*!<Filter FIFO Assignment bit 0 */
+#define CAN_FFA1R_FFA1 0x00000002U /*!<Filter FIFO Assignment bit 1 */
+#define CAN_FFA1R_FFA2 0x00000004U /*!<Filter FIFO Assignment bit 2 */
+#define CAN_FFA1R_FFA3 0x00000008U /*!<Filter FIFO Assignment bit 3 */
+#define CAN_FFA1R_FFA4 0x00000010U /*!<Filter FIFO Assignment bit 4 */
+#define CAN_FFA1R_FFA5 0x00000020U /*!<Filter FIFO Assignment bit 5 */
+#define CAN_FFA1R_FFA6 0x00000040U /*!<Filter FIFO Assignment bit 6 */
+#define CAN_FFA1R_FFA7 0x00000080U /*!<Filter FIFO Assignment bit 7 */
+#define CAN_FFA1R_FFA8 0x00000100U /*!<Filter FIFO Assignment bit 8 */
+#define CAN_FFA1R_FFA9 0x00000200U /*!<Filter FIFO Assignment bit 9 */
+#define CAN_FFA1R_FFA10 0x00000400U /*!<Filter FIFO Assignment bit 10 */
+#define CAN_FFA1R_FFA11 0x00000800U /*!<Filter FIFO Assignment bit 11 */
+#define CAN_FFA1R_FFA12 0x00001000U /*!<Filter FIFO Assignment bit 12 */
+#define CAN_FFA1R_FFA13 0x00002000U /*!<Filter FIFO Assignment bit 13 */
+#define CAN_FFA1R_FFA14 0x00004000U /*!<Filter FIFO Assignment bit 14 */
+#define CAN_FFA1R_FFA15 0x00008000U /*!<Filter FIFO Assignment bit 15 */
+#define CAN_FFA1R_FFA16 0x00010000U /*!<Filter FIFO Assignment bit 16 */
+#define CAN_FFA1R_FFA17 0x00020000U /*!<Filter FIFO Assignment bit 17 */
+#define CAN_FFA1R_FFA18 0x00040000U /*!<Filter FIFO Assignment bit 18 */
+#define CAN_FFA1R_FFA19 0x00080000U /*!<Filter FIFO Assignment bit 19 */
+#define CAN_FFA1R_FFA20 0x00100000U /*!<Filter FIFO Assignment bit 20 */
+#define CAN_FFA1R_FFA21 0x00200000U /*!<Filter FIFO Assignment bit 21 */
+#define CAN_FFA1R_FFA22 0x00400000U /*!<Filter FIFO Assignment bit 22 */
+#define CAN_FFA1R_FFA23 0x00800000U /*!<Filter FIFO Assignment bit 23 */
+#define CAN_FFA1R_FFA24 0x01000000U /*!<Filter FIFO Assignment bit 24 */
+#define CAN_FFA1R_FFA25 0x02000000U /*!<Filter FIFO Assignment bit 25 */
+#define CAN_FFA1R_FFA26 0x04000000U /*!<Filter FIFO Assignment bit 26 */
+#define CAN_FFA1R_FFA27 0x08000000U /*!<Filter FIFO Assignment bit 27 */
+
+/******************* Bit definition for CAN_FA1R register *******************/
+#define CAN_FA1R_FACT 0x0FFFFFFFU /*!<Filter Active */
+#define CAN_FA1R_FACT0 0x00000001U /*!<Filter Active bit 0 */
+#define CAN_FA1R_FACT1 0x00000002U /*!<Filter Active bit 1 */
+#define CAN_FA1R_FACT2 0x00000004U /*!<Filter Active bit 2 */
+#define CAN_FA1R_FACT3 0x00000008U /*!<Filter Active bit 3 */
+#define CAN_FA1R_FACT4 0x00000010U /*!<Filter Active bit 4 */
+#define CAN_FA1R_FACT5 0x00000020U /*!<Filter Active bit 5 */
+#define CAN_FA1R_FACT6 0x00000040U /*!<Filter Active bit 6 */
+#define CAN_FA1R_FACT7 0x00000080U /*!<Filter Active bit 7 */
+#define CAN_FA1R_FACT8 0x00000100U /*!<Filter Active bit 8 */
+#define CAN_FA1R_FACT9 0x00000200U /*!<Filter Active bit 9 */
+#define CAN_FA1R_FACT10 0x00000400U /*!<Filter Active bit 10 */
+#define CAN_FA1R_FACT11 0x00000800U /*!<Filter Active bit 11 */
+#define CAN_FA1R_FACT12 0x00001000U /*!<Filter Active bit 12 */
+#define CAN_FA1R_FACT13 0x00002000U /*!<Filter Active bit 13 */
+#define CAN_FA1R_FACT14 0x00004000U /*!<Filter Active bit 14 */
+#define CAN_FA1R_FACT15 0x00008000U /*!<Filter Active bit 15 */
+#define CAN_FA1R_FACT16 0x00010000U /*!<Filter Active bit 16 */
+#define CAN_FA1R_FACT17 0x00020000U /*!<Filter Active bit 17 */
+#define CAN_FA1R_FACT18 0x00040000U /*!<Filter Active bit 18 */
+#define CAN_FA1R_FACT19 0x00080000U /*!<Filter Active bit 19 */
+#define CAN_FA1R_FACT20 0x00100000U /*!<Filter Active bit 20 */
+#define CAN_FA1R_FACT21 0x00200000U /*!<Filter Active bit 21 */
+#define CAN_FA1R_FACT22 0x00400000U /*!<Filter Active bit 22 */
+#define CAN_FA1R_FACT23 0x00800000U /*!<Filter Active bit 23 */
+#define CAN_FA1R_FACT24 0x01000000U /*!<Filter Active bit 24 */
+#define CAN_FA1R_FACT25 0x02000000U /*!<Filter Active bit 25 */
+#define CAN_FA1R_FACT26 0x04000000U /*!<Filter Active bit 26 */
+#define CAN_FA1R_FACT27 0x08000000U /*!<Filter Active bit 27 */
+
+
+/******************* Bit definition for CAN_F0R1 register *******************/
+#define CAN_F0R1_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F0R1_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F0R1_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F0R1_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F0R1_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F0R1_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F0R1_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F0R1_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F0R1_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F0R1_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F0R1_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F0R1_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F0R1_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F0R1_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F0R1_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F0R1_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F0R1_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F0R1_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F0R1_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F0R1_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F0R1_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F0R1_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F0R1_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F0R1_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F0R1_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F0R1_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F0R1_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F0R1_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F0R1_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F0R1_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F0R1_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F0R1_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F1R1 register *******************/
+#define CAN_F1R1_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F1R1_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F1R1_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F1R1_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F1R1_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F1R1_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F1R1_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F1R1_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F1R1_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F1R1_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F1R1_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F1R1_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F1R1_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F1R1_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F1R1_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F1R1_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F1R1_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F1R1_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F1R1_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F1R1_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F1R1_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F1R1_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F1R1_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F1R1_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F1R1_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F1R1_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F1R1_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F1R1_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F1R1_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F1R1_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F1R1_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F1R1_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F2R1 register *******************/
+#define CAN_F2R1_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F2R1_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F2R1_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F2R1_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F2R1_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F2R1_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F2R1_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F2R1_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F2R1_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F2R1_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F2R1_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F2R1_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F2R1_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F2R1_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F2R1_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F2R1_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F2R1_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F2R1_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F2R1_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F2R1_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F2R1_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F2R1_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F2R1_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F2R1_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F2R1_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F2R1_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F2R1_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F2R1_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F2R1_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F2R1_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F2R1_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F2R1_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F3R1 register *******************/
+#define CAN_F3R1_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F3R1_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F3R1_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F3R1_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F3R1_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F3R1_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F3R1_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F3R1_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F3R1_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F3R1_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F3R1_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F3R1_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F3R1_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F3R1_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F3R1_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F3R1_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F3R1_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F3R1_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F3R1_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F3R1_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F3R1_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F3R1_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F3R1_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F3R1_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F3R1_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F3R1_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F3R1_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F3R1_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F3R1_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F3R1_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F3R1_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F3R1_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F4R1 register *******************/
+#define CAN_F4R1_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F4R1_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F4R1_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F4R1_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F4R1_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F4R1_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F4R1_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F4R1_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F4R1_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F4R1_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F4R1_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F4R1_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F4R1_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F4R1_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F4R1_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F4R1_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F4R1_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F4R1_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F4R1_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F4R1_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F4R1_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F4R1_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F4R1_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F4R1_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F4R1_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F4R1_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F4R1_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F4R1_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F4R1_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F4R1_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F4R1_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F4R1_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F5R1 register *******************/
+#define CAN_F5R1_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F5R1_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F5R1_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F5R1_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F5R1_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F5R1_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F5R1_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F5R1_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F5R1_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F5R1_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F5R1_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F5R1_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F5R1_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F5R1_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F5R1_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F5R1_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F5R1_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F5R1_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F5R1_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F5R1_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F5R1_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F5R1_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F5R1_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F5R1_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F5R1_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F5R1_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F5R1_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F5R1_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F5R1_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F5R1_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F5R1_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F5R1_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F6R1 register *******************/
+#define CAN_F6R1_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F6R1_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F6R1_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F6R1_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F6R1_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F6R1_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F6R1_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F6R1_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F6R1_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F6R1_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F6R1_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F6R1_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F6R1_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F6R1_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F6R1_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F6R1_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F6R1_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F6R1_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F6R1_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F6R1_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F6R1_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F6R1_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F6R1_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F6R1_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F6R1_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F6R1_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F6R1_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F6R1_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F6R1_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F6R1_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F6R1_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F6R1_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F7R1 register *******************/
+#define CAN_F7R1_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F7R1_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F7R1_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F7R1_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F7R1_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F7R1_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F7R1_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F7R1_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F7R1_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F7R1_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F7R1_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F7R1_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F7R1_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F7R1_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F7R1_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F7R1_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F7R1_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F7R1_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F7R1_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F7R1_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F7R1_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F7R1_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F7R1_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F7R1_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F7R1_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F7R1_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F7R1_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F7R1_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F7R1_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F7R1_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F7R1_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F7R1_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F8R1 register *******************/
+#define CAN_F8R1_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F8R1_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F8R1_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F8R1_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F8R1_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F8R1_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F8R1_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F8R1_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F8R1_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F8R1_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F8R1_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F8R1_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F8R1_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F8R1_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F8R1_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F8R1_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F8R1_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F8R1_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F8R1_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F8R1_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F8R1_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F8R1_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F8R1_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F8R1_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F8R1_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F8R1_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F8R1_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F8R1_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F8R1_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F8R1_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F8R1_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F8R1_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F9R1 register *******************/
+#define CAN_F9R1_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F9R1_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F9R1_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F9R1_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F9R1_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F9R1_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F9R1_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F9R1_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F9R1_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F9R1_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F9R1_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F9R1_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F9R1_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F9R1_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F9R1_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F9R1_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F9R1_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F9R1_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F9R1_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F9R1_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F9R1_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F9R1_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F9R1_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F9R1_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F9R1_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F9R1_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F9R1_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F9R1_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F9R1_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F9R1_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F9R1_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F9R1_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F10R1 register ******************/
+#define CAN_F10R1_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F10R1_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F10R1_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F10R1_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F10R1_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F10R1_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F10R1_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F10R1_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F10R1_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F10R1_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F10R1_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F10R1_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F10R1_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F10R1_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F10R1_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F10R1_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F10R1_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F10R1_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F10R1_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F10R1_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F10R1_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F10R1_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F10R1_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F10R1_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F10R1_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F10R1_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F10R1_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F10R1_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F10R1_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F10R1_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F10R1_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F10R1_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F11R1 register ******************/
+#define CAN_F11R1_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F11R1_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F11R1_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F11R1_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F11R1_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F11R1_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F11R1_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F11R1_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F11R1_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F11R1_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F11R1_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F11R1_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F11R1_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F11R1_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F11R1_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F11R1_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F11R1_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F11R1_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F11R1_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F11R1_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F11R1_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F11R1_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F11R1_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F11R1_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F11R1_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F11R1_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F11R1_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F11R1_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F11R1_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F11R1_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F11R1_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F11R1_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F12R1 register ******************/
+#define CAN_F12R1_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F12R1_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F12R1_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F12R1_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F12R1_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F12R1_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F12R1_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F12R1_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F12R1_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F12R1_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F12R1_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F12R1_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F12R1_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F12R1_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F12R1_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F12R1_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F12R1_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F12R1_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F12R1_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F12R1_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F12R1_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F12R1_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F12R1_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F12R1_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F12R1_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F12R1_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F12R1_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F12R1_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F12R1_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F12R1_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F12R1_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F12R1_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F13R1 register ******************/
+#define CAN_F13R1_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F13R1_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F13R1_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F13R1_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F13R1_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F13R1_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F13R1_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F13R1_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F13R1_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F13R1_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F13R1_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F13R1_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F13R1_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F13R1_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F13R1_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F13R1_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F13R1_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F13R1_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F13R1_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F13R1_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F13R1_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F13R1_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F13R1_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F13R1_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F13R1_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F13R1_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F13R1_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F13R1_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F13R1_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F13R1_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F13R1_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F13R1_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F0R2 register *******************/
+#define CAN_F0R2_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F0R2_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F0R2_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F0R2_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F0R2_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F0R2_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F0R2_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F0R2_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F0R2_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F0R2_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F0R2_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F0R2_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F0R2_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F0R2_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F0R2_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F0R2_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F0R2_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F0R2_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F0R2_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F0R2_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F0R2_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F0R2_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F0R2_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F0R2_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F0R2_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F0R2_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F0R2_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F0R2_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F0R2_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F0R2_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F0R2_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F0R2_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F1R2 register *******************/
+#define CAN_F1R2_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F1R2_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F1R2_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F1R2_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F1R2_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F1R2_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F1R2_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F1R2_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F1R2_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F1R2_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F1R2_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F1R2_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F1R2_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F1R2_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F1R2_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F1R2_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F1R2_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F1R2_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F1R2_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F1R2_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F1R2_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F1R2_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F1R2_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F1R2_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F1R2_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F1R2_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F1R2_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F1R2_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F1R2_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F1R2_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F1R2_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F1R2_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F2R2 register *******************/
+#define CAN_F2R2_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F2R2_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F2R2_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F2R2_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F2R2_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F2R2_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F2R2_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F2R2_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F2R2_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F2R2_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F2R2_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F2R2_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F2R2_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F2R2_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F2R2_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F2R2_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F2R2_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F2R2_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F2R2_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F2R2_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F2R2_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F2R2_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F2R2_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F2R2_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F2R2_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F2R2_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F2R2_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F2R2_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F2R2_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F2R2_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F2R2_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F2R2_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F3R2 register *******************/
+#define CAN_F3R2_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F3R2_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F3R2_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F3R2_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F3R2_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F3R2_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F3R2_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F3R2_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F3R2_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F3R2_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F3R2_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F3R2_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F3R2_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F3R2_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F3R2_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F3R2_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F3R2_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F3R2_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F3R2_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F3R2_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F3R2_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F3R2_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F3R2_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F3R2_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F3R2_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F3R2_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F3R2_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F3R2_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F3R2_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F3R2_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F3R2_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F3R2_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F4R2 register *******************/
+#define CAN_F4R2_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F4R2_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F4R2_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F4R2_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F4R2_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F4R2_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F4R2_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F4R2_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F4R2_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F4R2_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F4R2_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F4R2_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F4R2_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F4R2_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F4R2_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F4R2_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F4R2_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F4R2_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F4R2_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F4R2_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F4R2_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F4R2_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F4R2_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F4R2_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F4R2_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F4R2_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F4R2_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F4R2_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F4R2_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F4R2_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F4R2_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F4R2_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F5R2 register *******************/
+#define CAN_F5R2_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F5R2_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F5R2_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F5R2_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F5R2_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F5R2_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F5R2_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F5R2_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F5R2_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F5R2_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F5R2_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F5R2_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F5R2_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F5R2_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F5R2_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F5R2_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F5R2_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F5R2_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F5R2_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F5R2_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F5R2_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F5R2_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F5R2_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F5R2_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F5R2_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F5R2_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F5R2_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F5R2_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F5R2_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F5R2_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F5R2_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F5R2_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F6R2 register *******************/
+#define CAN_F6R2_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F6R2_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F6R2_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F6R2_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F6R2_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F6R2_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F6R2_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F6R2_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F6R2_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F6R2_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F6R2_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F6R2_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F6R2_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F6R2_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F6R2_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F6R2_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F6R2_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F6R2_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F6R2_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F6R2_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F6R2_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F6R2_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F6R2_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F6R2_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F6R2_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F6R2_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F6R2_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F6R2_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F6R2_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F6R2_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F6R2_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F6R2_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F7R2 register *******************/
+#define CAN_F7R2_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F7R2_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F7R2_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F7R2_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F7R2_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F7R2_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F7R2_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F7R2_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F7R2_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F7R2_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F7R2_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F7R2_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F7R2_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F7R2_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F7R2_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F7R2_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F7R2_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F7R2_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F7R2_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F7R2_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F7R2_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F7R2_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F7R2_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F7R2_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F7R2_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F7R2_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F7R2_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F7R2_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F7R2_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F7R2_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F7R2_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F7R2_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F8R2 register *******************/
+#define CAN_F8R2_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F8R2_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F8R2_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F8R2_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F8R2_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F8R2_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F8R2_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F8R2_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F8R2_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F8R2_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F8R2_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F8R2_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F8R2_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F8R2_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F8R2_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F8R2_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F8R2_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F8R2_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F8R2_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F8R2_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F8R2_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F8R2_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F8R2_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F8R2_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F8R2_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F8R2_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F8R2_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F8R2_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F8R2_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F8R2_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F8R2_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F8R2_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F9R2 register *******************/
+#define CAN_F9R2_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F9R2_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F9R2_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F9R2_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F9R2_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F9R2_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F9R2_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F9R2_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F9R2_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F9R2_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F9R2_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F9R2_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F9R2_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F9R2_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F9R2_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F9R2_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F9R2_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F9R2_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F9R2_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F9R2_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F9R2_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F9R2_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F9R2_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F9R2_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F9R2_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F9R2_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F9R2_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F9R2_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F9R2_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F9R2_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F9R2_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F9R2_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F10R2 register ******************/
+#define CAN_F10R2_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F10R2_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F10R2_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F10R2_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F10R2_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F10R2_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F10R2_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F10R2_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F10R2_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F10R2_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F10R2_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F10R2_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F10R2_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F10R2_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F10R2_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F10R2_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F10R2_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F10R2_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F10R2_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F10R2_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F10R2_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F10R2_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F10R2_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F10R2_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F10R2_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F10R2_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F10R2_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F10R2_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F10R2_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F10R2_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F10R2_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F10R2_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F11R2 register ******************/
+#define CAN_F11R2_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F11R2_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F11R2_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F11R2_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F11R2_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F11R2_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F11R2_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F11R2_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F11R2_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F11R2_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F11R2_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F11R2_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F11R2_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F11R2_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F11R2_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F11R2_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F11R2_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F11R2_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F11R2_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F11R2_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F11R2_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F11R2_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F11R2_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F11R2_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F11R2_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F11R2_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F11R2_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F11R2_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F11R2_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F11R2_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F11R2_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F11R2_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F12R2 register ******************/
+#define CAN_F12R2_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F12R2_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F12R2_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F12R2_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F12R2_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F12R2_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F12R2_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F12R2_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F12R2_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F12R2_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F12R2_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F12R2_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F12R2_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F12R2_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F12R2_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F12R2_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F12R2_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F12R2_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F12R2_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F12R2_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F12R2_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F12R2_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F12R2_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F12R2_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F12R2_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F12R2_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F12R2_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F12R2_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F12R2_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F12R2_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F12R2_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F12R2_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F13R2 register ******************/
+#define CAN_F13R2_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F13R2_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F13R2_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F13R2_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F13R2_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F13R2_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F13R2_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F13R2_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F13R2_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F13R2_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F13R2_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F13R2_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F13R2_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F13R2_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F13R2_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F13R2_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F13R2_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F13R2_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F13R2_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F13R2_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F13R2_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F13R2_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F13R2_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F13R2_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F13R2_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F13R2_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F13R2_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F13R2_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F13R2_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F13R2_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F13R2_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F13R2_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************************************************************************/
+/* */
+/* HDMI-CEC (CEC) */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for CEC_CR register *********************/
+#define CEC_CR_CECEN 0x00000001U /*!< CEC Enable */
+#define CEC_CR_TXSOM 0x00000002U /*!< CEC Tx Start Of Message */
+#define CEC_CR_TXEOM 0x00000004U /*!< CEC Tx End Of Message */
+
+/******************* Bit definition for CEC_CFGR register *******************/
+#define CEC_CFGR_SFT 0x00000007U /*!< CEC Signal Free Time */
+#define CEC_CFGR_RXTOL 0x00000008U /*!< CEC Tolerance */
+#define CEC_CFGR_BRESTP 0x00000010U /*!< CEC Rx Stop */
+#define CEC_CFGR_BREGEN 0x00000020U /*!< CEC Bit Rising Error generation */
+#define CEC_CFGR_LBPEGEN 0x00000040U /*!< CEC Long Bit Period Error generation */
+#define CEC_CFGR_SFTOPT 0x00000100U /*!< CEC Signal Free Time optional */
+#define CEC_CFGR_BRDNOGEN 0x00000080U /*!< CEC Broadcast No error generation */
+#define CEC_CFGR_OAR 0x7FFF0000U /*!< CEC Own Address */
+#define CEC_CFGR_LSTN 0x80000000U /*!< CEC Listen mode */
+
+/******************* Bit definition for CEC_TXDR register *******************/
+#define CEC_TXDR_TXD 0x000000FFU /*!< CEC Tx Data */
+
+/******************* Bit definition for CEC_RXDR register *******************/
+#define CEC_TXDR_RXD 0x000000FFU /*!< CEC Rx Data */
+
+/******************* Bit definition for CEC_ISR register ********************/
+#define CEC_ISR_RXBR 0x00000001U /*!< CEC Rx-Byte Received */
+#define CEC_ISR_RXEND 0x00000002U /*!< CEC End Of Reception */
+#define CEC_ISR_RXOVR 0x00000004U /*!< CEC Rx-Overrun */
+#define CEC_ISR_BRE 0x00000008U /*!< CEC Rx Bit Rising Error */
+#define CEC_ISR_SBPE 0x00000010U /*!< CEC Rx Short Bit period Error */
+#define CEC_ISR_LBPE 0x00000020U /*!< CEC Rx Long Bit period Error */
+#define CEC_ISR_RXACKE 0x00000040U /*!< CEC Rx Missing Acknowledge */
+#define CEC_ISR_ARBLST 0x00000080U /*!< CEC Arbitration Lost */
+#define CEC_ISR_TXBR 0x00000100U /*!< CEC Tx Byte Request */
+#define CEC_ISR_TXEND 0x00000200U /*!< CEC End of Transmission */
+#define CEC_ISR_TXUDR 0x00000400U /*!< CEC Tx-Buffer Underrun */
+#define CEC_ISR_TXERR 0x00000800U /*!< CEC Tx-Error */
+#define CEC_ISR_TXACKE 0x00001000U /*!< CEC Tx Missing Acknowledge */
+
+/******************* Bit definition for CEC_IER register ********************/
+#define CEC_IER_RXBRIE 0x00000001U /*!< CEC Rx-Byte Received IT Enable */
+#define CEC_IER_RXENDIE 0x00000002U /*!< CEC End Of Reception IT Enable */
+#define CEC_IER_RXOVRIE 0x00000004U /*!< CEC Rx-Overrun IT Enable */
+#define CEC_IER_BREIE 0x00000008U /*!< CEC Rx Bit Rising Error IT Enable */
+#define CEC_IER_SBPEIE 0x00000010U /*!< CEC Rx Short Bit period Error IT Enable */
+#define CEC_IER_LBPEIE 0x00000020U /*!< CEC Rx Long Bit period Error IT Enable */
+#define CEC_IER_RXACKEIE 0x00000040U /*!< CEC Rx Missing Acknowledge IT Enable */
+#define CEC_IER_ARBLSTIE 0x00000080U /*!< CEC Arbitration Lost IT Enable */
+#define CEC_IER_TXBRIE 0x00000100U /*!< CEC Tx Byte Request IT Enable */
+#define CEC_IER_TXENDIE 0x00000200U /*!< CEC End of Transmission IT Enable */
+#define CEC_IER_TXUDRIE 0x00000400U /*!< CEC Tx-Buffer Underrun IT Enable */
+#define CEC_IER_TXERRIE 0x00000800U /*!< CEC Tx-Error IT Enable */
+#define CEC_IER_TXACKEIE 0x00001000U /*!< CEC Tx Missing Acknowledge IT Enable */
+
+/******************************************************************************/
+/* */
+/* CRC calculation unit */
+/* */
+/******************************************************************************/
+/******************* Bit definition for CRC_DR register *********************/
+#define CRC_DR_DR 0xFFFFFFFFU /*!< Data register bits */
+
+
+/******************* Bit definition for CRC_IDR register ********************/
+#define CRC_IDR_IDR 0xFFU /*!< General-purpose 8-bit data register bits */
+
+
+/******************** Bit definition for CRC_CR register ********************/
+#define CRC_CR_RESET 0x01U /*!< RESET bit */
+
+/******************************************************************************/
+/* */
+/* Digital to Analog Converter */
+/* */
+/******************************************************************************/
+/******************** Bit definition for DAC_CR register ********************/
+#define DAC_CR_EN1 0x00000001U /*!<DAC channel1 enable */
+#define DAC_CR_BOFF1 0x00000002U /*!<DAC channel1 output buffer disable */
+#define DAC_CR_TEN1 0x00000004U /*!<DAC channel1 Trigger enable */
+
+#define DAC_CR_TSEL1 0x00000038U /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */
+#define DAC_CR_TSEL1_0 0x00000008U /*!<Bit 0 */
+#define DAC_CR_TSEL1_1 0x00000010U /*!<Bit 1 */
+#define DAC_CR_TSEL1_2 0x00000020U /*!<Bit 2 */
+
+#define DAC_CR_WAVE1 0x000000C0U /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
+#define DAC_CR_WAVE1_0 0x00000040U /*!<Bit 0 */
+#define DAC_CR_WAVE1_1 0x00000080U /*!<Bit 1 */
+
+#define DAC_CR_MAMP1 0x00000F00U /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
+#define DAC_CR_MAMP1_0 0x00000100U /*!<Bit 0 */
+#define DAC_CR_MAMP1_1 0x00000200U /*!<Bit 1 */
+#define DAC_CR_MAMP1_2 0x00000400U /*!<Bit 2 */
+#define DAC_CR_MAMP1_3 0x00000800U /*!<Bit 3 */
+
+#define DAC_CR_DMAEN1 0x00001000U /*!<DAC channel1 DMA enable */
+#define DAC_CR_DMAUDRIE1 0x00002000U /*!<DAC channel1 DMA underrun interrupt enable*/
+#define DAC_CR_EN2 0x00010000U /*!<DAC channel2 enable */
+#define DAC_CR_BOFF2 0x00020000U /*!<DAC channel2 output buffer disable */
+#define DAC_CR_TEN2 0x00040000U /*!<DAC channel2 Trigger enable */
+
+#define DAC_CR_TSEL2 0x00380000U /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */
+#define DAC_CR_TSEL2_0 0x00080000U /*!<Bit 0 */
+#define DAC_CR_TSEL2_1 0x00100000U /*!<Bit 1 */
+#define DAC_CR_TSEL2_2 0x00200000U /*!<Bit 2 */
+
+#define DAC_CR_WAVE2 0x00C00000U /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
+#define DAC_CR_WAVE2_0 0x00400000U /*!<Bit 0 */
+#define DAC_CR_WAVE2_1 0x00800000U /*!<Bit 1 */
+
+#define DAC_CR_MAMP2 0x0F000000U /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
+#define DAC_CR_MAMP2_0 0x01000000U /*!<Bit 0 */
+#define DAC_CR_MAMP2_1 0x02000000U /*!<Bit 1 */
+#define DAC_CR_MAMP2_2 0x04000000U /*!<Bit 2 */
+#define DAC_CR_MAMP2_3 0x08000000U /*!<Bit 3 */
+
+#define DAC_CR_DMAEN2 0x10000000U /*!<DAC channel2 DMA enabled */
+#define DAC_CR_DMAUDRIE2 0x20000000U /*!<DAC channel2 DMA underrun interrupt enable*/
+
+/***************** Bit definition for DAC_SWTRIGR register ******************/
+#define DAC_SWTRIGR_SWTRIG1 0x01U /*!<DAC channel1 software trigger */
+#define DAC_SWTRIGR_SWTRIG2 0x02U /*!<DAC channel2 software trigger */
+
+/***************** Bit definition for DAC_DHR12R1 register ******************/
+#define DAC_DHR12R1_DACC1DHR 0x0FFFU /*!<DAC channel1 12-bit Right aligned data */
+
+/***************** Bit definition for DAC_DHR12L1 register ******************/
+#define DAC_DHR12L1_DACC1DHR 0xFFF0U /*!<DAC channel1 12-bit Left aligned data */
+
+/****************** Bit definition for DAC_DHR8R1 register ******************/
+#define DAC_DHR8R1_DACC1DHR 0xFFU /*!<DAC channel1 8-bit Right aligned data */
+
+/***************** Bit definition for DAC_DHR12R2 register ******************/
+#define DAC_DHR12R2_DACC2DHR 0x0FFFU /*!<DAC channel2 12-bit Right aligned data */
+
+/***************** Bit definition for DAC_DHR12L2 register ******************/
+#define DAC_DHR12L2_DACC2DHR 0xFFF0U /*!<DAC channel2 12-bit Left aligned data */
+
+/****************** Bit definition for DAC_DHR8R2 register ******************/
+#define DAC_DHR8R2_DACC2DHR 0xFFU /*!<DAC channel2 8-bit Right aligned data */
+
+/***************** Bit definition for DAC_DHR12RD register ******************/
+#define DAC_DHR12RD_DACC1DHR 0x00000FFFU /*!<DAC channel1 12-bit Right aligned data */
+#define DAC_DHR12RD_DACC2DHR 0x0FFF0000U /*!<DAC channel2 12-bit Right aligned data */
+
+/***************** Bit definition for DAC_DHR12LD register ******************/
+#define DAC_DHR12LD_DACC1DHR 0x0000FFF0U /*!<DAC channel1 12-bit Left aligned data */
+#define DAC_DHR12LD_DACC2DHR 0xFFF00000U /*!<DAC channel2 12-bit Left aligned data */
+
+/****************** Bit definition for DAC_DHR8RD register ******************/
+#define DAC_DHR8RD_DACC1DHR 0x00FFU /*!<DAC channel1 8-bit Right aligned data */
+#define DAC_DHR8RD_DACC2DHR 0xFF00U /*!<DAC channel2 8-bit Right aligned data */
+
+/******************* Bit definition for DAC_DOR1 register *******************/
+#define DAC_DOR1_DACC1DOR 0x0FFFU /*!<DAC channel1 data output */
+
+/******************* Bit definition for DAC_DOR2 register *******************/
+#define DAC_DOR2_DACC2DOR 0x0FFFU /*!<DAC channel2 data output */
+
+/******************** Bit definition for DAC_SR register ********************/
+#define DAC_SR_DMAUDR1 0x00002000U /*!<DAC channel1 DMA underrun flag */
+#define DAC_SR_DMAUDR2 0x20000000U /*!<DAC channel2 DMA underrun flag */
+
+/******************************************************************************/
+/* */
+/* Debug MCU */
+/* */
+/******************************************************************************/
+
+/******************************************************************************/
+/* */
+/* DCMI */
+/* */
+/******************************************************************************/
+/******************** Bits definition for DCMI_CR register ******************/
+#define DCMI_CR_CAPTURE 0x00000001U
+#define DCMI_CR_CM 0x00000002U
+#define DCMI_CR_CROP 0x00000004U
+#define DCMI_CR_JPEG 0x00000008U
+#define DCMI_CR_ESS 0x00000010U
+#define DCMI_CR_PCKPOL 0x00000020U
+#define DCMI_CR_HSPOL 0x00000040U
+#define DCMI_CR_VSPOL 0x00000080U
+#define DCMI_CR_FCRC_0 0x00000100U
+#define DCMI_CR_FCRC_1 0x00000200U
+#define DCMI_CR_EDM_0 0x00000400U
+#define DCMI_CR_EDM_1 0x00000800U
+#define DCMI_CR_OUTEN 0x00002000U
+#define DCMI_CR_ENABLE 0x00004000U
+#define DCMI_CR_BSM_0 0x00010000U
+#define DCMI_CR_BSM_1 0x00020000U
+#define DCMI_CR_OEBS 0x00040000U
+#define DCMI_CR_LSM 0x00080000U
+#define DCMI_CR_OELS 0x00100000U
+
+/******************** Bits definition for DCMI_SR register ******************/
+#define DCMI_SR_HSYNC 0x00000001U
+#define DCMI_SR_VSYNC 0x00000002U
+#define DCMI_SR_FNE 0x00000004U
+
+/******************** Bits definition for DCMI_RIS register ****************/
+#define DCMI_RIS_FRAME_RIS 0x00000001U
+#define DCMI_RIS_OVR_RIS 0x00000002U
+#define DCMI_RIS_ERR_RIS 0x00000004U
+#define DCMI_RIS_VSYNC_RIS 0x00000008U
+#define DCMI_RIS_LINE_RIS 0x00000010U
+/* Legacy defines */
+#define DCMI_RISR_FRAME_RIS DCMI_RIS_FRAME_RIS
+#define DCMI_RISR_OVR_RIS DCMI_RIS_OVR_RIS
+#define DCMI_RISR_ERR_RIS DCMI_RIS_ERR_RIS
+#define DCMI_RISR_VSYNC_RIS DCMI_RIS_VSYNC_RIS
+#define DCMI_RISR_LINE_RIS DCMI_RIS_LINE_RIS
+#define DCMI_RISR_OVF_RIS DCMI_RIS_OVR_RIS
+
+/******************** Bits definition for DCMI_IER register *****************/
+#define DCMI_IER_FRAME_IE 0x00000001U
+#define DCMI_IER_OVR_IE 0x00000002U
+#define DCMI_IER_ERR_IE 0x00000004U
+#define DCMI_IER_VSYNC_IE 0x00000008U
+#define DCMI_IER_LINE_IE 0x00000010U
+/* Legacy defines */
+#define DCMI_IER_OVF_IE DCMI_IER_OVR_IE
+
+/******************** Bits definition for DCMI_MIS register *****************/
+#define DCMI_MIS_FRAME_MIS 0x00000001U
+#define DCMI_MIS_OVR_MIS 0x00000002U
+#define DCMI_MIS_ERR_MIS 0x00000004U
+#define DCMI_MIS_VSYNC_MIS 0x00000008U
+#define DCMI_MIS_LINE_MIS 0x00000010U
+
+/* Legacy defines */
+#define DCMI_MISR_FRAME_MIS DCMI_MIS_FRAME_MIS
+#define DCMI_MISR_OVF_MIS DCMI_MIS_OVR_MIS
+#define DCMI_MISR_ERR_MIS DCMI_MIS_ERR_MIS
+#define DCMI_MISR_VSYNC_MIS DCMI_MIS_VSYNC_MIS
+#define DCMI_MISR_LINE_MIS DCMI_MIS_LINE_MIS
+
+/******************** Bits definition for DCMI_ICR register *****************/
+#define DCMI_ICR_FRAME_ISC 0x00000001U
+#define DCMI_ICR_OVR_ISC 0x00000002U
+#define DCMI_ICR_ERR_ISC 0x00000004U
+#define DCMI_ICR_VSYNC_ISC 0x00000008U
+#define DCMI_ICR_LINE_ISC 0x00000010U
+
+/* Legacy defines */
+#define DCMI_ICR_OVF_ISC DCMI_ICR_OVR_ISC
+
+/******************** Bits definition for DCMI_ESCR register ******************/
+#define DCMI_ESCR_FSC 0x000000FFU
+#define DCMI_ESCR_LSC 0x0000FF00U
+#define DCMI_ESCR_LEC 0x00FF0000U
+#define DCMI_ESCR_FEC 0xFF000000U
+
+/******************** Bits definition for DCMI_ESUR register ******************/
+#define DCMI_ESUR_FSU 0x000000FFU
+#define DCMI_ESUR_LSU 0x0000FF00U
+#define DCMI_ESUR_LEU 0x00FF0000U
+#define DCMI_ESUR_FEU 0xFF000000U
+
+/******************** Bits definition for DCMI_CWSTRT register ******************/
+#define DCMI_CWSTRT_HOFFCNT 0x00003FFFU
+#define DCMI_CWSTRT_VST 0x1FFF0000U
+
+/******************** Bits definition for DCMI_CWSIZE register ******************/
+#define DCMI_CWSIZE_CAPCNT 0x00003FFFU
+#define DCMI_CWSIZE_VLINE 0x3FFF0000U
+
+/******************** Bits definition for DCMI_DR register ******************/
+#define DCMI_DR_BYTE0 0x000000FFU
+#define DCMI_DR_BYTE1 0x0000FF00U
+#define DCMI_DR_BYTE2 0x00FF0000U
+#define DCMI_DR_BYTE3 0xFF000000U
+
+/******************************************************************************/
+/* */
+/* DMA Controller */
+/* */
+/******************************************************************************/
+/******************** Bits definition for DMA_SxCR register *****************/
+#define DMA_SxCR_CHSEL 0x0E000000U
+#define DMA_SxCR_CHSEL_0 0x02000000U
+#define DMA_SxCR_CHSEL_1 0x04000000U
+#define DMA_SxCR_CHSEL_2 0x08000000U
+#define DMA_SxCR_MBURST 0x01800000U
+#define DMA_SxCR_MBURST_0 0x00800000U
+#define DMA_SxCR_MBURST_1 0x01000000U
+#define DMA_SxCR_PBURST 0x00600000U
+#define DMA_SxCR_PBURST_0 0x00200000U
+#define DMA_SxCR_PBURST_1 0x00400000U
+#define DMA_SxCR_CT 0x00080000U
+#define DMA_SxCR_DBM 0x00040000U
+#define DMA_SxCR_PL 0x00030000U
+#define DMA_SxCR_PL_0 0x00010000U
+#define DMA_SxCR_PL_1 0x00020000U
+#define DMA_SxCR_PINCOS 0x00008000U
+#define DMA_SxCR_MSIZE 0x00006000U
+#define DMA_SxCR_MSIZE_0 0x00002000U
+#define DMA_SxCR_MSIZE_1 0x00004000U
+#define DMA_SxCR_PSIZE 0x00001800U
+#define DMA_SxCR_PSIZE_0 0x00000800U
+#define DMA_SxCR_PSIZE_1 0x00001000U
+#define DMA_SxCR_MINC 0x00000400U
+#define DMA_SxCR_PINC 0x00000200U
+#define DMA_SxCR_CIRC 0x00000100U
+#define DMA_SxCR_DIR 0x000000C0U
+#define DMA_SxCR_DIR_0 0x00000040U
+#define DMA_SxCR_DIR_1 0x00000080U
+#define DMA_SxCR_PFCTRL 0x00000020U
+#define DMA_SxCR_TCIE 0x00000010U
+#define DMA_SxCR_HTIE 0x00000008U
+#define DMA_SxCR_TEIE 0x00000004U
+#define DMA_SxCR_DMEIE 0x00000002U
+#define DMA_SxCR_EN 0x00000001U
+
+/* Legacy defines */
+#define DMA_SxCR_ACK 0x00100000U
+
+/******************** Bits definition for DMA_SxCNDTR register **************/
+#define DMA_SxNDT 0x0000FFFFU
+#define DMA_SxNDT_0 0x00000001U
+#define DMA_SxNDT_1 0x00000002U
+#define DMA_SxNDT_2 0x00000004U
+#define DMA_SxNDT_3 0x00000008U
+#define DMA_SxNDT_4 0x00000010U
+#define DMA_SxNDT_5 0x00000020U
+#define DMA_SxNDT_6 0x00000040U
+#define DMA_SxNDT_7 0x00000080U
+#define DMA_SxNDT_8 0x00000100U
+#define DMA_SxNDT_9 0x00000200U
+#define DMA_SxNDT_10 0x00000400U
+#define DMA_SxNDT_11 0x00000800U
+#define DMA_SxNDT_12 0x00001000U
+#define DMA_SxNDT_13 0x00002000U
+#define DMA_SxNDT_14 0x00004000U
+#define DMA_SxNDT_15 0x00008000U
+
+/******************** Bits definition for DMA_SxFCR register ****************/
+#define DMA_SxFCR_FEIE 0x00000080U
+#define DMA_SxFCR_FS 0x00000038U
+#define DMA_SxFCR_FS_0 0x00000008U
+#define DMA_SxFCR_FS_1 0x00000010U
+#define DMA_SxFCR_FS_2 0x00000020U
+#define DMA_SxFCR_DMDIS 0x00000004U
+#define DMA_SxFCR_FTH 0x00000003U
+#define DMA_SxFCR_FTH_0 0x00000001U
+#define DMA_SxFCR_FTH_1 0x00000002U
+
+/******************** Bits definition for DMA_LISR register *****************/
+#define DMA_LISR_TCIF3 0x08000000U
+#define DMA_LISR_HTIF3 0x04000000U
+#define DMA_LISR_TEIF3 0x02000000U
+#define DMA_LISR_DMEIF3 0x01000000U
+#define DMA_LISR_FEIF3 0x00400000U
+#define DMA_LISR_TCIF2 0x00200000U
+#define DMA_LISR_HTIF2 0x00100000U
+#define DMA_LISR_TEIF2 0x00080000U
+#define DMA_LISR_DMEIF2 0x00040000U
+#define DMA_LISR_FEIF2 0x00010000U
+#define DMA_LISR_TCIF1 0x00000800U
+#define DMA_LISR_HTIF1 0x00000400U
+#define DMA_LISR_TEIF1 0x00000200U
+#define DMA_LISR_DMEIF1 0x00000100U
+#define DMA_LISR_FEIF1 0x00000040U
+#define DMA_LISR_TCIF0 0x00000020U
+#define DMA_LISR_HTIF0 0x00000010U
+#define DMA_LISR_TEIF0 0x00000008U
+#define DMA_LISR_DMEIF0 0x00000004U
+#define DMA_LISR_FEIF0 0x00000001U
+
+/******************** Bits definition for DMA_HISR register *****************/
+#define DMA_HISR_TCIF7 0x08000000U
+#define DMA_HISR_HTIF7 0x04000000U
+#define DMA_HISR_TEIF7 0x02000000U
+#define DMA_HISR_DMEIF7 0x01000000U
+#define DMA_HISR_FEIF7 0x00400000U
+#define DMA_HISR_TCIF6 0x00200000U
+#define DMA_HISR_HTIF6 0x00100000U
+#define DMA_HISR_TEIF6 0x00080000U
+#define DMA_HISR_DMEIF6 0x00040000U
+#define DMA_HISR_FEIF6 0x00010000U
+#define DMA_HISR_TCIF5 0x00000800U
+#define DMA_HISR_HTIF5 0x00000400U
+#define DMA_HISR_TEIF5 0x00000200U
+#define DMA_HISR_DMEIF5 0x00000100U
+#define DMA_HISR_FEIF5 0x00000040U
+#define DMA_HISR_TCIF4 0x00000020U
+#define DMA_HISR_HTIF4 0x00000010U
+#define DMA_HISR_TEIF4 0x00000008U
+#define DMA_HISR_DMEIF4 0x00000004U
+#define DMA_HISR_FEIF4 0x00000001U
+
+/******************** Bits definition for DMA_LIFCR register ****************/
+#define DMA_LIFCR_CTCIF3 0x08000000U
+#define DMA_LIFCR_CHTIF3 0x04000000U
+#define DMA_LIFCR_CTEIF3 0x02000000U
+#define DMA_LIFCR_CDMEIF3 0x01000000U
+#define DMA_LIFCR_CFEIF3 0x00400000U
+#define DMA_LIFCR_CTCIF2 0x00200000U
+#define DMA_LIFCR_CHTIF2 0x00100000U
+#define DMA_LIFCR_CTEIF2 0x00080000U
+#define DMA_LIFCR_CDMEIF2 0x00040000U
+#define DMA_LIFCR_CFEIF2 0x00010000U
+#define DMA_LIFCR_CTCIF1 0x00000800U
+#define DMA_LIFCR_CHTIF1 0x00000400U
+#define DMA_LIFCR_CTEIF1 0x00000200U
+#define DMA_LIFCR_CDMEIF1 0x00000100U
+#define DMA_LIFCR_CFEIF1 0x00000040U
+#define DMA_LIFCR_CTCIF0 0x00000020U
+#define DMA_LIFCR_CHTIF0 0x00000010U
+#define DMA_LIFCR_CTEIF0 0x00000008U
+#define DMA_LIFCR_CDMEIF0 0x00000004U
+#define DMA_LIFCR_CFEIF0 0x00000001U
+
+/******************** Bits definition for DMA_HIFCR register ****************/
+#define DMA_HIFCR_CTCIF7 0x08000000U
+#define DMA_HIFCR_CHTIF7 0x04000000U
+#define DMA_HIFCR_CTEIF7 0x02000000U
+#define DMA_HIFCR_CDMEIF7 0x01000000U
+#define DMA_HIFCR_CFEIF7 0x00400000U
+#define DMA_HIFCR_CTCIF6 0x00200000U
+#define DMA_HIFCR_CHTIF6 0x00100000U
+#define DMA_HIFCR_CTEIF6 0x00080000U
+#define DMA_HIFCR_CDMEIF6 0x00040000U
+#define DMA_HIFCR_CFEIF6 0x00010000U
+#define DMA_HIFCR_CTCIF5 0x00000800U
+#define DMA_HIFCR_CHTIF5 0x00000400U
+#define DMA_HIFCR_CTEIF5 0x00000200U
+#define DMA_HIFCR_CDMEIF5 0x00000100U
+#define DMA_HIFCR_CFEIF5 0x00000040U
+#define DMA_HIFCR_CTCIF4 0x00000020U
+#define DMA_HIFCR_CHTIF4 0x00000010U
+#define DMA_HIFCR_CTEIF4 0x00000008U
+#define DMA_HIFCR_CDMEIF4 0x00000004U
+#define DMA_HIFCR_CFEIF4 0x00000001U
+
+
+/******************************************************************************/
+/* */
+/* External Interrupt/Event Controller */
+/* */
+/******************************************************************************/
+/******************* Bit definition for EXTI_IMR register *******************/
+#define EXTI_IMR_MR0 0x00000001U /*!< Interrupt Mask on line 0 */
+#define EXTI_IMR_MR1 0x00000002U /*!< Interrupt Mask on line 1 */
+#define EXTI_IMR_MR2 0x00000004U /*!< Interrupt Mask on line 2 */
+#define EXTI_IMR_MR3 0x00000008U /*!< Interrupt Mask on line 3 */
+#define EXTI_IMR_MR4 0x00000010U /*!< Interrupt Mask on line 4 */
+#define EXTI_IMR_MR5 0x00000020U /*!< Interrupt Mask on line 5 */
+#define EXTI_IMR_MR6 0x00000040U /*!< Interrupt Mask on line 6 */
+#define EXTI_IMR_MR7 0x00000080U /*!< Interrupt Mask on line 7 */
+#define EXTI_IMR_MR8 0x00000100U /*!< Interrupt Mask on line 8 */
+#define EXTI_IMR_MR9 0x00000200U /*!< Interrupt Mask on line 9 */
+#define EXTI_IMR_MR10 0x00000400U /*!< Interrupt Mask on line 10 */
+#define EXTI_IMR_MR11 0x00000800U /*!< Interrupt Mask on line 11 */
+#define EXTI_IMR_MR12 0x00001000U /*!< Interrupt Mask on line 12 */
+#define EXTI_IMR_MR13 0x00002000U /*!< Interrupt Mask on line 13 */
+#define EXTI_IMR_MR14 0x00004000U /*!< Interrupt Mask on line 14 */
+#define EXTI_IMR_MR15 0x00008000U /*!< Interrupt Mask on line 15 */
+#define EXTI_IMR_MR16 0x00010000U /*!< Interrupt Mask on line 16 */
+#define EXTI_IMR_MR17 0x00020000U /*!< Interrupt Mask on line 17 */
+#define EXTI_IMR_MR18 0x00040000U /*!< Interrupt Mask on line 18 */
+#define EXTI_IMR_MR19 0x00080000U /*!< Interrupt Mask on line 19 */
+#define EXTI_IMR_MR20 0x00100000U /*!< Interrupt Mask on line 20 */
+#define EXTI_IMR_MR21 0x00200000U /*!< Interrupt Mask on line 21 */
+#define EXTI_IMR_MR22 0x00400000U /*!< Interrupt Mask on line 22 */
+
+/******************* Bit definition for EXTI_EMR register *******************/
+#define EXTI_EMR_MR0 0x00000001U /*!< Event Mask on line 0 */
+#define EXTI_EMR_MR1 0x00000002U /*!< Event Mask on line 1 */
+#define EXTI_EMR_MR2 0x00000004U /*!< Event Mask on line 2 */
+#define EXTI_EMR_MR3 0x00000008U /*!< Event Mask on line 3 */
+#define EXTI_EMR_MR4 0x00000010U /*!< Event Mask on line 4 */
+#define EXTI_EMR_MR5 0x00000020U /*!< Event Mask on line 5 */
+#define EXTI_EMR_MR6 0x00000040U /*!< Event Mask on line 6 */
+#define EXTI_EMR_MR7 0x00000080U /*!< Event Mask on line 7 */
+#define EXTI_EMR_MR8 0x00000100U /*!< Event Mask on line 8 */
+#define EXTI_EMR_MR9 0x00000200U /*!< Event Mask on line 9 */
+#define EXTI_EMR_MR10 0x00000400U /*!< Event Mask on line 10 */
+#define EXTI_EMR_MR11 0x00000800U /*!< Event Mask on line 11 */
+#define EXTI_EMR_MR12 0x00001000U /*!< Event Mask on line 12 */
+#define EXTI_EMR_MR13 0x00002000U /*!< Event Mask on line 13 */
+#define EXTI_EMR_MR14 0x00004000U /*!< Event Mask on line 14 */
+#define EXTI_EMR_MR15 0x00008000U /*!< Event Mask on line 15 */
+#define EXTI_EMR_MR16 0x00010000U /*!< Event Mask on line 16 */
+#define EXTI_EMR_MR17 0x00020000U /*!< Event Mask on line 17 */
+#define EXTI_EMR_MR18 0x00040000U /*!< Event Mask on line 18 */
+#define EXTI_EMR_MR19 0x00080000U /*!< Event Mask on line 19 */
+#define EXTI_EMR_MR20 0x00100000U /*!< Event Mask on line 20 */
+#define EXTI_EMR_MR21 0x00200000U /*!< Event Mask on line 21 */
+#define EXTI_EMR_MR22 0x00400000U /*!< Event Mask on line 22 */
+
+/****************** Bit definition for EXTI_RTSR register *******************/
+#define EXTI_RTSR_TR0 0x00000001U /*!< Rising trigger event configuration bit of line 0 */
+#define EXTI_RTSR_TR1 0x00000002U /*!< Rising trigger event configuration bit of line 1 */
+#define EXTI_RTSR_TR2 0x00000004U /*!< Rising trigger event configuration bit of line 2 */
+#define EXTI_RTSR_TR3 0x00000008U /*!< Rising trigger event configuration bit of line 3 */
+#define EXTI_RTSR_TR4 0x00000010U /*!< Rising trigger event configuration bit of line 4 */
+#define EXTI_RTSR_TR5 0x00000020U /*!< Rising trigger event configuration bit of line 5 */
+#define EXTI_RTSR_TR6 0x00000040U /*!< Rising trigger event configuration bit of line 6 */
+#define EXTI_RTSR_TR7 0x00000080U /*!< Rising trigger event configuration bit of line 7 */
+#define EXTI_RTSR_TR8 0x00000100U /*!< Rising trigger event configuration bit of line 8 */
+#define EXTI_RTSR_TR9 0x00000200U /*!< Rising trigger event configuration bit of line 9 */
+#define EXTI_RTSR_TR10 0x00000400U /*!< Rising trigger event configuration bit of line 10 */
+#define EXTI_RTSR_TR11 0x00000800U /*!< Rising trigger event configuration bit of line 11 */
+#define EXTI_RTSR_TR12 0x00001000U /*!< Rising trigger event configuration bit of line 12 */
+#define EXTI_RTSR_TR13 0x00002000U /*!< Rising trigger event configuration bit of line 13 */
+#define EXTI_RTSR_TR14 0x00004000U /*!< Rising trigger event configuration bit of line 14 */
+#define EXTI_RTSR_TR15 0x00008000U /*!< Rising trigger event configuration bit of line 15 */
+#define EXTI_RTSR_TR16 0x00010000U /*!< Rising trigger event configuration bit of line 16 */
+#define EXTI_RTSR_TR17 0x00020000U /*!< Rising trigger event configuration bit of line 17 */
+#define EXTI_RTSR_TR18 0x00040000U /*!< Rising trigger event configuration bit of line 18 */
+#define EXTI_RTSR_TR19 0x00080000U /*!< Rising trigger event configuration bit of line 19 */
+#define EXTI_RTSR_TR20 0x00100000U /*!< Rising trigger event configuration bit of line 20 */
+#define EXTI_RTSR_TR21 0x00200000U /*!< Rising trigger event configuration bit of line 21 */
+#define EXTI_RTSR_TR22 0x00400000U /*!< Rising trigger event configuration bit of line 22 */
+
+/****************** Bit definition for EXTI_FTSR register *******************/
+#define EXTI_FTSR_TR0 0x00000001U /*!< Falling trigger event configuration bit of line 0 */
+#define EXTI_FTSR_TR1 0x00000002U /*!< Falling trigger event configuration bit of line 1 */
+#define EXTI_FTSR_TR2 0x00000004U /*!< Falling trigger event configuration bit of line 2 */
+#define EXTI_FTSR_TR3 0x00000008U /*!< Falling trigger event configuration bit of line 3 */
+#define EXTI_FTSR_TR4 0x00000010U /*!< Falling trigger event configuration bit of line 4 */
+#define EXTI_FTSR_TR5 0x00000020U /*!< Falling trigger event configuration bit of line 5 */
+#define EXTI_FTSR_TR6 0x00000040U /*!< Falling trigger event configuration bit of line 6 */
+#define EXTI_FTSR_TR7 0x00000080U /*!< Falling trigger event configuration bit of line 7 */
+#define EXTI_FTSR_TR8 0x00000100U /*!< Falling trigger event configuration bit of line 8 */
+#define EXTI_FTSR_TR9 0x00000200U /*!< Falling trigger event configuration bit of line 9 */
+#define EXTI_FTSR_TR10 0x00000400U /*!< Falling trigger event configuration bit of line 10 */
+#define EXTI_FTSR_TR11 0x00000800U /*!< Falling trigger event configuration bit of line 11 */
+#define EXTI_FTSR_TR12 0x00001000U /*!< Falling trigger event configuration bit of line 12 */
+#define EXTI_FTSR_TR13 0x00002000U /*!< Falling trigger event configuration bit of line 13 */
+#define EXTI_FTSR_TR14 0x00004000U /*!< Falling trigger event configuration bit of line 14 */
+#define EXTI_FTSR_TR15 0x00008000U /*!< Falling trigger event configuration bit of line 15 */
+#define EXTI_FTSR_TR16 0x00010000U /*!< Falling trigger event configuration bit of line 16 */
+#define EXTI_FTSR_TR17 0x00020000U /*!< Falling trigger event configuration bit of line 17 */
+#define EXTI_FTSR_TR18 0x00040000U /*!< Falling trigger event configuration bit of line 18 */
+#define EXTI_FTSR_TR19 0x00080000U /*!< Falling trigger event configuration bit of line 19 */
+#define EXTI_FTSR_TR20 0x00100000U /*!< Falling trigger event configuration bit of line 20 */
+#define EXTI_FTSR_TR21 0x00200000U /*!< Falling trigger event configuration bit of line 21 */
+#define EXTI_FTSR_TR22 0x00400000U /*!< Falling trigger event configuration bit of line 22 */
+
+/****************** Bit definition for EXTI_SWIER register ******************/
+#define EXTI_SWIER_SWIER0 0x00000001U /*!< Software Interrupt on line 0 */
+#define EXTI_SWIER_SWIER1 0x00000002U /*!< Software Interrupt on line 1 */
+#define EXTI_SWIER_SWIER2 0x00000004U /*!< Software Interrupt on line 2 */
+#define EXTI_SWIER_SWIER3 0x00000008U /*!< Software Interrupt on line 3 */
+#define EXTI_SWIER_SWIER4 0x00000010U /*!< Software Interrupt on line 4 */
+#define EXTI_SWIER_SWIER5 0x00000020U /*!< Software Interrupt on line 5 */
+#define EXTI_SWIER_SWIER6 0x00000040U /*!< Software Interrupt on line 6 */
+#define EXTI_SWIER_SWIER7 0x00000080U /*!< Software Interrupt on line 7 */
+#define EXTI_SWIER_SWIER8 0x00000100U /*!< Software Interrupt on line 8 */
+#define EXTI_SWIER_SWIER9 0x00000200U /*!< Software Interrupt on line 9 */
+#define EXTI_SWIER_SWIER10 0x00000400U /*!< Software Interrupt on line 10 */
+#define EXTI_SWIER_SWIER11 0x00000800U /*!< Software Interrupt on line 11 */
+#define EXTI_SWIER_SWIER12 0x00001000U /*!< Software Interrupt on line 12 */
+#define EXTI_SWIER_SWIER13 0x00002000U /*!< Software Interrupt on line 13 */
+#define EXTI_SWIER_SWIER14 0x00004000U /*!< Software Interrupt on line 14 */
+#define EXTI_SWIER_SWIER15 0x00008000U /*!< Software Interrupt on line 15 */
+#define EXTI_SWIER_SWIER16 0x00010000U /*!< Software Interrupt on line 16 */
+#define EXTI_SWIER_SWIER17 0x00020000U /*!< Software Interrupt on line 17 */
+#define EXTI_SWIER_SWIER18 0x00040000U /*!< Software Interrupt on line 18 */
+#define EXTI_SWIER_SWIER19 0x00080000U /*!< Software Interrupt on line 19 */
+#define EXTI_SWIER_SWIER20 0x00100000U /*!< Software Interrupt on line 20 */
+#define EXTI_SWIER_SWIER21 0x00200000U /*!< Software Interrupt on line 21 */
+#define EXTI_SWIER_SWIER22 0x00400000U /*!< Software Interrupt on line 22 */
+
+/******************* Bit definition for EXTI_PR register ********************/
+#define EXTI_PR_PR0 0x00000001U /*!< Pending bit for line 0 */
+#define EXTI_PR_PR1 0x00000002U /*!< Pending bit for line 1 */
+#define EXTI_PR_PR2 0x00000004U /*!< Pending bit for line 2 */
+#define EXTI_PR_PR3 0x00000008U /*!< Pending bit for line 3 */
+#define EXTI_PR_PR4 0x00000010U /*!< Pending bit for line 4 */
+#define EXTI_PR_PR5 0x00000020U /*!< Pending bit for line 5 */
+#define EXTI_PR_PR6 0x00000040U /*!< Pending bit for line 6 */
+#define EXTI_PR_PR7 0x00000080U /*!< Pending bit for line 7 */
+#define EXTI_PR_PR8 0x00000100U /*!< Pending bit for line 8 */
+#define EXTI_PR_PR9 0x00000200U /*!< Pending bit for line 9 */
+#define EXTI_PR_PR10 0x00000400U /*!< Pending bit for line 10 */
+#define EXTI_PR_PR11 0x00000800U /*!< Pending bit for line 11 */
+#define EXTI_PR_PR12 0x00001000U /*!< Pending bit for line 12 */
+#define EXTI_PR_PR13 0x00002000U /*!< Pending bit for line 13 */
+#define EXTI_PR_PR14 0x00004000U /*!< Pending bit for line 14 */
+#define EXTI_PR_PR15 0x00008000U /*!< Pending bit for line 15 */
+#define EXTI_PR_PR16 0x00010000U /*!< Pending bit for line 16 */
+#define EXTI_PR_PR17 0x00020000U /*!< Pending bit for line 17 */
+#define EXTI_PR_PR18 0x00040000U /*!< Pending bit for line 18 */
+#define EXTI_PR_PR19 0x00080000U /*!< Pending bit for line 19 */
+#define EXTI_PR_PR20 0x00100000U /*!< Pending bit for line 20 */
+#define EXTI_PR_PR21 0x00200000U /*!< Pending bit for line 21 */
+#define EXTI_PR_PR22 0x00400000U /*!< Pending bit for line 22 */
+
+/******************************************************************************/
+/* */
+/* FLASH */
+/* */
+/******************************************************************************/
+/******************* Bits definition for FLASH_ACR register *****************/
+#define FLASH_ACR_LATENCY 0x0000000FU
+#define FLASH_ACR_LATENCY_0WS 0x00000000U
+#define FLASH_ACR_LATENCY_1WS 0x00000001U
+#define FLASH_ACR_LATENCY_2WS 0x00000002U
+#define FLASH_ACR_LATENCY_3WS 0x00000003U
+#define FLASH_ACR_LATENCY_4WS 0x00000004U
+#define FLASH_ACR_LATENCY_5WS 0x00000005U
+#define FLASH_ACR_LATENCY_6WS 0x00000006U
+#define FLASH_ACR_LATENCY_7WS 0x00000007U
+#define FLASH_ACR_LATENCY_8WS 0x00000008U
+#define FLASH_ACR_LATENCY_9WS 0x00000009U
+#define FLASH_ACR_LATENCY_10WS 0x0000000AU
+#define FLASH_ACR_LATENCY_11WS 0x0000000BU
+#define FLASH_ACR_LATENCY_12WS 0x0000000CU
+#define FLASH_ACR_LATENCY_13WS 0x0000000DU
+#define FLASH_ACR_LATENCY_14WS 0x0000000EU
+#define FLASH_ACR_LATENCY_15WS 0x0000000FU
+#define FLASH_ACR_PRFTEN 0x00000100U
+#define FLASH_ACR_ICEN 0x00000200U
+#define FLASH_ACR_DCEN 0x00000400U
+#define FLASH_ACR_ICRST 0x00000800U
+#define FLASH_ACR_DCRST 0x00001000U
+#define FLASH_ACR_BYTE0_ADDRESS 0x40023C00U
+#define FLASH_ACR_BYTE2_ADDRESS 0x40023C03U
+
+/******************* Bits definition for FLASH_SR register ******************/
+#define FLASH_SR_EOP 0x00000001U
+#define FLASH_SR_SOP 0x00000002U
+#define FLASH_SR_WRPERR 0x00000010U
+#define FLASH_SR_PGAERR 0x00000020U
+#define FLASH_SR_PGPERR 0x00000040U
+#define FLASH_SR_PGSERR 0x00000080U
+#define FLASH_SR_BSY 0x00010000U
+
+/******************* Bits definition for FLASH_CR register ******************/
+#define FLASH_CR_PG 0x00000001U
+#define FLASH_CR_SER 0x00000002U
+#define FLASH_CR_MER 0x00000004U
+#define FLASH_CR_MER1 FLASH_CR_MER
+#define FLASH_CR_SNB 0x000000F8U
+#define FLASH_CR_SNB_0 0x00000008U
+#define FLASH_CR_SNB_1 0x00000010U
+#define FLASH_CR_SNB_2 0x00000020U
+#define FLASH_CR_SNB_3 0x00000040U
+#define FLASH_CR_SNB_4 0x00000080U
+#define FLASH_CR_PSIZE 0x00000300U
+#define FLASH_CR_PSIZE_0 0x00000100U
+#define FLASH_CR_PSIZE_1 0x00000200U
+#define FLASH_CR_MER2 0x00008000U
+#define FLASH_CR_STRT 0x00010000U
+#define FLASH_CR_EOPIE 0x01000000U
+#define FLASH_CR_LOCK 0x80000000U
+
+/******************* Bits definition for FLASH_OPTCR register ***************/
+#define FLASH_OPTCR_OPTLOCK 0x00000001U
+#define FLASH_OPTCR_OPTSTRT 0x00000002U
+#define FLASH_OPTCR_BOR_LEV_0 0x00000004U
+#define FLASH_OPTCR_BOR_LEV_1 0x00000008U
+#define FLASH_OPTCR_BOR_LEV 0x0000000CU
+#define FLASH_OPTCR_BFB2 0x00000010U
+#define FLASH_OPTCR_WDG_SW 0x00000020U
+#define FLASH_OPTCR_nRST_STOP 0x00000040U
+#define FLASH_OPTCR_nRST_STDBY 0x00000080U
+#define FLASH_OPTCR_RDP 0x0000FF00U
+#define FLASH_OPTCR_RDP_0 0x00000100U
+#define FLASH_OPTCR_RDP_1 0x00000200U
+#define FLASH_OPTCR_RDP_2 0x00000400U
+#define FLASH_OPTCR_RDP_3 0x00000800U
+#define FLASH_OPTCR_RDP_4 0x00001000U
+#define FLASH_OPTCR_RDP_5 0x00002000U
+#define FLASH_OPTCR_RDP_6 0x00004000U
+#define FLASH_OPTCR_RDP_7 0x00008000U
+#define FLASH_OPTCR_nWRP 0x0FFF0000U
+#define FLASH_OPTCR_nWRP_0 0x00010000U
+#define FLASH_OPTCR_nWRP_1 0x00020000U
+#define FLASH_OPTCR_nWRP_2 0x00040000U
+#define FLASH_OPTCR_nWRP_3 0x00080000U
+#define FLASH_OPTCR_nWRP_4 0x00100000U
+#define FLASH_OPTCR_nWRP_5 0x00200000U
+#define FLASH_OPTCR_nWRP_6 0x00400000U
+#define FLASH_OPTCR_nWRP_7 0x00800000U
+#define FLASH_OPTCR_nWRP_8 0x01000000U
+#define FLASH_OPTCR_nWRP_9 0x02000000U
+#define FLASH_OPTCR_nWRP_10 0x04000000U
+#define FLASH_OPTCR_nWRP_11 0x08000000U
+#define FLASH_OPTCR_DB1M 0x40000000U
+#define FLASH_OPTCR_SPRMOD 0x80000000U
+
+/****************** Bits definition for FLASH_OPTCR1 register ***************/
+#define FLASH_OPTCR1_nWRP 0x0FFF0000U
+#define FLASH_OPTCR1_nWRP_0 0x00010000U
+#define FLASH_OPTCR1_nWRP_1 0x00020000U
+#define FLASH_OPTCR1_nWRP_2 0x00040000U
+#define FLASH_OPTCR1_nWRP_3 0x00080000U
+#define FLASH_OPTCR1_nWRP_4 0x00100000U
+#define FLASH_OPTCR1_nWRP_5 0x00200000U
+#define FLASH_OPTCR1_nWRP_6 0x00400000U
+#define FLASH_OPTCR1_nWRP_7 0x00800000U
+#define FLASH_OPTCR1_nWRP_8 0x01000000U
+#define FLASH_OPTCR1_nWRP_9 0x02000000U
+#define FLASH_OPTCR1_nWRP_10 0x04000000U
+#define FLASH_OPTCR1_nWRP_11 0x08000000U
+
+/******************************************************************************/
+/* */
+/* Flexible Memory Controller */
+/* */
+/******************************************************************************/
+/****************** Bit definition for FMC_BCR1 register *******************/
+#define FMC_BCR1_MBKEN 0x00000001U /*!<Memory bank enable bit */
+#define FMC_BCR1_MUXEN 0x00000002U /*!<Address/data multiplexing enable bit */
+
+#define FMC_BCR1_MTYP 0x0000000CU /*!<MTYP[1:0] bits (Memory type) */
+#define FMC_BCR1_MTYP_0 0x00000004U /*!<Bit 0 */
+#define FMC_BCR1_MTYP_1 0x00000008U /*!<Bit 1 */
+
+#define FMC_BCR1_MWID 0x00000030U /*!<MWID[1:0] bits (Memory data bus width) */
+#define FMC_BCR1_MWID_0 0x00000010U /*!<Bit 0 */
+#define FMC_BCR1_MWID_1 0x00000020U /*!<Bit 1 */
+
+#define FMC_BCR1_FACCEN 0x00000040U /*!<Flash access enable */
+#define FMC_BCR1_BURSTEN 0x00000100U /*!<Burst enable bit */
+#define FMC_BCR1_WAITPOL 0x00000200U /*!<Wait signal polarity bit */
+#define FMC_BCR1_WAITCFG 0x00000800U /*!<Wait timing configuration */
+#define FMC_BCR1_WREN 0x00001000U /*!<Write enable bit */
+#define FMC_BCR1_WAITEN 0x00002000U /*!<Wait enable bit */
+#define FMC_BCR1_EXTMOD 0x00004000U /*!<Extended mode enable */
+#define FMC_BCR1_ASYNCWAIT 0x00008000U /*!<Asynchronous wait */
+#define FMC_BCR1_CPSIZE 0x00070000U /*!<CRAM page size */
+#define FMC_BCR1_CPSIZE_0 0x00010000U /*!<Bit 0 */
+#define FMC_BCR1_CPSIZE_1 0x00020000U /*!<Bit 1 */
+#define FMC_BCR1_CPSIZE_2 0x00040000U /*!<Bit 2 */
+#define FMC_BCR1_CBURSTRW 0x00080000U /*!<Write burst enable */
+#define FMC_BCR1_CCLKEN 0x00100000U /*!<Continous clock enable */
+#define FMC_BCR1_WFDIS 0x00200000U /*!<Write FIFO Disable */
+
+/****************** Bit definition for FMC_BCR2 register *******************/
+#define FMC_BCR2_MBKEN 0x00000001U /*!<Memory bank enable bit */
+#define FMC_BCR2_MUXEN 0x00000002U /*!<Address/data multiplexing enable bit */
+
+#define FMC_BCR2_MTYP 0x0000000CU /*!<MTYP[1:0] bits (Memory type) */
+#define FMC_BCR2_MTYP_0 0x00000004U /*!<Bit 0 */
+#define FMC_BCR2_MTYP_1 0x00000008U /*!<Bit 1 */
+
+#define FMC_BCR2_MWID 0x00000030U /*!<MWID[1:0] bits (Memory data bus width) */
+#define FMC_BCR2_MWID_0 0x00000010U /*!<Bit 0 */
+#define FMC_BCR2_MWID_1 0x00000020U /*!<Bit 1 */
+
+#define FMC_BCR2_FACCEN 0x00000040U /*!<Flash access enable */
+#define FMC_BCR2_BURSTEN 0x00000100U /*!<Burst enable bit */
+#define FMC_BCR2_WAITPOL 0x00000200U /*!<Wait signal polarity bit */
+#define FMC_BCR2_WAITCFG 0x00000800U /*!<Wait timing configuration */
+#define FMC_BCR2_WREN 0x00001000U /*!<Write enable bit */
+#define FMC_BCR2_WAITEN 0x00002000U /*!<Wait enable bit */
+#define FMC_BCR2_EXTMOD 0x00004000U /*!<Extended mode enable */
+#define FMC_BCR2_ASYNCWAIT 0x00008000U /*!<Asynchronous wait */
+#define FMC_BCR2_CBURSTRW 0x00080000U /*!<Write burst enable */
+
+/****************** Bit definition for FMC_BCR3 register *******************/
+#define FMC_BCR3_MBKEN 0x00000001U /*!<Memory bank enable bit */
+#define FMC_BCR3_MUXEN 0x00000002U /*!<Address/data multiplexing enable bit */
+
+#define FMC_BCR3_MTYP 0x0000000CU /*!<MTYP[1:0] bits (Memory type) */
+#define FMC_BCR3_MTYP_0 0x00000004U /*!<Bit 0 */
+#define FMC_BCR3_MTYP_1 0x00000008U /*!<Bit 1 */
+
+#define FMC_BCR3_MWID 0x00000030U /*!<MWID[1:0] bits (Memory data bus width) */
+#define FMC_BCR3_MWID_0 0x00000010U /*!<Bit 0 */
+#define FMC_BCR3_MWID_1 0x00000020U /*!<Bit 1 */
+
+#define FMC_BCR3_FACCEN 0x00000040U /*!<Flash access enable */
+#define FMC_BCR3_BURSTEN 0x00000100U /*!<Burst enable bit */
+#define FMC_BCR3_WAITPOL 0x00000200U /*!<Wait signal polarity bit */
+#define FMC_BCR3_WAITCFG 0x00000800U /*!<Wait timing configuration */
+#define FMC_BCR3_WREN 0x00001000U /*!<Write enable bit */
+#define FMC_BCR3_WAITEN 0x00002000U /*!<Wait enable bit */
+#define FMC_BCR3_EXTMOD 0x00004000U /*!<Extended mode enable */
+#define FMC_BCR3_ASYNCWAIT 0x00008000U /*!<Asynchronous wait */
+#define FMC_BCR3_CBURSTRW 0x00080000U /*!<Write burst enable */
+
+/****************** Bit definition for FMC_BCR4 register *******************/
+#define FMC_BCR4_MBKEN 0x00000001U /*!<Memory bank enable bit */
+#define FMC_BCR4_MUXEN 0x00000002U /*!<Address/data multiplexing enable bit */
+
+#define FMC_BCR4_MTYP 0x0000000CU /*!<MTYP[1:0] bits (Memory type) */
+#define FMC_BCR4_MTYP_0 0x00000004U /*!<Bit 0 */
+#define FMC_BCR4_MTYP_1 0x00000008U /*!<Bit 1 */
+
+#define FMC_BCR4_MWID 0x00000030U /*!<MWID[1:0] bits (Memory data bus width) */
+#define FMC_BCR4_MWID_0 0x00000010U /*!<Bit 0 */
+#define FMC_BCR4_MWID_1 0x00000020U /*!<Bit 1 */
+
+#define FMC_BCR4_FACCEN 0x00000040U /*!<Flash access enable */
+#define FMC_BCR4_BURSTEN 0x00000100U /*!<Burst enable bit */
+#define FMC_BCR4_WAITPOL 0x00000200U /*!<Wait signal polarity bit */
+#define FMC_BCR4_WAITCFG 0x00000800U /*!<Wait timing configuration */
+#define FMC_BCR4_WREN 0x00001000U /*!<Write enable bit */
+#define FMC_BCR4_WAITEN 0x00002000U /*!<Wait enable bit */
+#define FMC_BCR4_EXTMOD 0x00004000U /*!<Extended mode enable */
+#define FMC_BCR4_ASYNCWAIT 0x00008000U /*!<Asynchronous wait */
+#define FMC_BCR4_CBURSTRW 0x00080000U /*!<Write burst enable */
+
+/****************** Bit definition for FMC_BTR1 register ******************/
+#define FMC_BTR1_ADDSET 0x0000000FU /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FMC_BTR1_ADDSET_0 0x00000001U /*!<Bit 0 */
+#define FMC_BTR1_ADDSET_1 0x00000002U /*!<Bit 1 */
+#define FMC_BTR1_ADDSET_2 0x00000004U /*!<Bit 2 */
+#define FMC_BTR1_ADDSET_3 0x00000008U /*!<Bit 3 */
+
+#define FMC_BTR1_ADDHLD 0x000000F0U /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FMC_BTR1_ADDHLD_0 0x00000010U /*!<Bit 0 */
+#define FMC_BTR1_ADDHLD_1 0x00000020U /*!<Bit 1 */
+#define FMC_BTR1_ADDHLD_2 0x00000040U /*!<Bit 2 */
+#define FMC_BTR1_ADDHLD_3 0x00000080U /*!<Bit 3 */
+
+#define FMC_BTR1_DATAST 0x0000FF00U /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FMC_BTR1_DATAST_0 0x00000100U /*!<Bit 0 */
+#define FMC_BTR1_DATAST_1 0x00000200U /*!<Bit 1 */
+#define FMC_BTR1_DATAST_2 0x00000400U /*!<Bit 2 */
+#define FMC_BTR1_DATAST_3 0x00000800U /*!<Bit 3 */
+#define FMC_BTR1_DATAST_4 0x00001000U /*!<Bit 4 */
+#define FMC_BTR1_DATAST_5 0x00002000U /*!<Bit 5 */
+#define FMC_BTR1_DATAST_6 0x00004000U /*!<Bit 6 */
+#define FMC_BTR1_DATAST_7 0x00008000U /*!<Bit 7 */
+
+#define FMC_BTR1_BUSTURN 0x000F0000U /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define FMC_BTR1_BUSTURN_0 0x00010000U /*!<Bit 0 */
+#define FMC_BTR1_BUSTURN_1 0x00020000U /*!<Bit 1 */
+#define FMC_BTR1_BUSTURN_2 0x00040000U /*!<Bit 2 */
+#define FMC_BTR1_BUSTURN_3 0x00080000U /*!<Bit 3 */
+
+#define FMC_BTR1_CLKDIV 0x00F00000U /*!<CLKDIV[3:0] bits (Clock divide ratio) */
+#define FMC_BTR1_CLKDIV_0 0x00100000U /*!<Bit 0 */
+#define FMC_BTR1_CLKDIV_1 0x00200000U /*!<Bit 1 */
+#define FMC_BTR1_CLKDIV_2 0x00400000U /*!<Bit 2 */
+#define FMC_BTR1_CLKDIV_3 0x00800000U /*!<Bit 3 */
+
+#define FMC_BTR1_DATLAT 0x0F000000U /*!<DATLA[3:0] bits (Data latency) */
+#define FMC_BTR1_DATLAT_0 0x01000000U /*!<Bit 0 */
+#define FMC_BTR1_DATLAT_1 0x02000000U /*!<Bit 1 */
+#define FMC_BTR1_DATLAT_2 0x04000000U /*!<Bit 2 */
+#define FMC_BTR1_DATLAT_3 0x08000000U /*!<Bit 3 */
+
+#define FMC_BTR1_ACCMOD 0x30000000U /*!<ACCMOD[1:0] bits (Access mode) */
+#define FMC_BTR1_ACCMOD_0 0x10000000U /*!<Bit 0 */
+#define FMC_BTR1_ACCMOD_1 0x20000000U /*!<Bit 1 */
+
+/****************** Bit definition for FMC_BTR2 register *******************/
+#define FMC_BTR2_ADDSET 0x0000000FU /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FMC_BTR2_ADDSET_0 0x00000001U /*!<Bit 0 */
+#define FMC_BTR2_ADDSET_1 0x00000002U /*!<Bit 1 */
+#define FMC_BTR2_ADDSET_2 0x00000004U /*!<Bit 2 */
+#define FMC_BTR2_ADDSET_3 0x00000008U /*!<Bit 3 */
+
+#define FMC_BTR2_ADDHLD 0x000000F0U /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FMC_BTR2_ADDHLD_0 0x00000010U /*!<Bit 0 */
+#define FMC_BTR2_ADDHLD_1 0x00000020U /*!<Bit 1 */
+#define FMC_BTR2_ADDHLD_2 0x00000040U /*!<Bit 2 */
+#define FMC_BTR2_ADDHLD_3 0x00000080U /*!<Bit 3 */
+
+#define FMC_BTR2_DATAST 0x0000FF00U /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FMC_BTR2_DATAST_0 0x00000100U /*!<Bit 0 */
+#define FMC_BTR2_DATAST_1 0x00000200U /*!<Bit 1 */
+#define FMC_BTR2_DATAST_2 0x00000400U /*!<Bit 2 */
+#define FMC_BTR2_DATAST_3 0x00000800U /*!<Bit 3 */
+#define FMC_BTR2_DATAST_4 0x00001000U /*!<Bit 4 */
+#define FMC_BTR2_DATAST_5 0x00002000U /*!<Bit 5 */
+#define FMC_BTR2_DATAST_6 0x00004000U /*!<Bit 6 */
+#define FMC_BTR2_DATAST_7 0x00008000U /*!<Bit 7 */
+
+#define FMC_BTR2_BUSTURN 0x000F0000U /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define FMC_BTR2_BUSTURN_0 0x00010000U /*!<Bit 0 */
+#define FMC_BTR2_BUSTURN_1 0x00020000U /*!<Bit 1 */
+#define FMC_BTR2_BUSTURN_2 0x00040000U /*!<Bit 2 */
+#define FMC_BTR2_BUSTURN_3 0x00080000U /*!<Bit 3 */
+
+#define FMC_BTR2_CLKDIV 0x00F00000U /*!<CLKDIV[3:0] bits (Clock divide ratio) */
+#define FMC_BTR2_CLKDIV_0 0x00100000U /*!<Bit 0 */
+#define FMC_BTR2_CLKDIV_1 0x00200000U /*!<Bit 1 */
+#define FMC_BTR2_CLKDIV_2 0x00400000U /*!<Bit 2 */
+#define FMC_BTR2_CLKDIV_3 0x00800000U /*!<Bit 3 */
+
+#define FMC_BTR2_DATLAT 0x0F000000U /*!<DATLA[3:0] bits (Data latency) */
+#define FMC_BTR2_DATLAT_0 0x01000000U /*!<Bit 0 */
+#define FMC_BTR2_DATLAT_1 0x02000000U /*!<Bit 1 */
+#define FMC_BTR2_DATLAT_2 0x04000000U /*!<Bit 2 */
+#define FMC_BTR2_DATLAT_3 0x08000000U /*!<Bit 3 */
+
+#define FMC_BTR2_ACCMOD 0x30000000U /*!<ACCMOD[1:0] bits (Access mode) */
+#define FMC_BTR2_ACCMOD_0 0x10000000U /*!<Bit 0 */
+#define FMC_BTR2_ACCMOD_1 0x20000000U /*!<Bit 1 */
+
+/******************* Bit definition for FMC_BTR3 register *******************/
+#define FMC_BTR3_ADDSET 0x0000000FU /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FMC_BTR3_ADDSET_0 0x00000001U /*!<Bit 0 */
+#define FMC_BTR3_ADDSET_1 0x00000002U /*!<Bit 1 */
+#define FMC_BTR3_ADDSET_2 0x00000004U /*!<Bit 2 */
+#define FMC_BTR3_ADDSET_3 0x00000008U /*!<Bit 3 */
+
+#define FMC_BTR3_ADDHLD 0x000000F0U /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FMC_BTR3_ADDHLD_0 0x00000010U /*!<Bit 0 */
+#define FMC_BTR3_ADDHLD_1 0x00000020U /*!<Bit 1 */
+#define FMC_BTR3_ADDHLD_2 0x00000040U /*!<Bit 2 */
+#define FMC_BTR3_ADDHLD_3 0x00000080U /*!<Bit 3 */
+
+#define FMC_BTR3_DATAST 0x0000FF00U /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FMC_BTR3_DATAST_0 0x00000100U /*!<Bit 0 */
+#define FMC_BTR3_DATAST_1 0x00000200U /*!<Bit 1 */
+#define FMC_BTR3_DATAST_2 0x00000400U /*!<Bit 2 */
+#define FMC_BTR3_DATAST_3 0x00000800U /*!<Bit 3 */
+#define FMC_BTR3_DATAST_4 0x00001000U /*!<Bit 4 */
+#define FMC_BTR3_DATAST_5 0x00002000U /*!<Bit 5 */
+#define FMC_BTR3_DATAST_6 0x00004000U /*!<Bit 6 */
+#define FMC_BTR3_DATAST_7 0x00008000U /*!<Bit 7 */
+
+#define FMC_BTR3_BUSTURN 0x000F0000U /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define FMC_BTR3_BUSTURN_0 0x00010000U /*!<Bit 0 */
+#define FMC_BTR3_BUSTURN_1 0x00020000U /*!<Bit 1 */
+#define FMC_BTR3_BUSTURN_2 0x00040000U /*!<Bit 2 */
+#define FMC_BTR3_BUSTURN_3 0x00080000U /*!<Bit 3 */
+
+#define FMC_BTR3_CLKDIV 0x00F00000U /*!<CLKDIV[3:0] bits (Clock divide ratio) */
+#define FMC_BTR3_CLKDIV_0 0x00100000U /*!<Bit 0 */
+#define FMC_BTR3_CLKDIV_1 0x00200000U /*!<Bit 1 */
+#define FMC_BTR3_CLKDIV_2 0x00400000U /*!<Bit 2 */
+#define FMC_BTR3_CLKDIV_3 0x00800000U /*!<Bit 3 */
+
+#define FMC_BTR3_DATLAT 0x0F000000U /*!<DATLA[3:0] bits (Data latency) */
+#define FMC_BTR3_DATLAT_0 0x01000000U /*!<Bit 0 */
+#define FMC_BTR3_DATLAT_1 0x02000000U /*!<Bit 1 */
+#define FMC_BTR3_DATLAT_2 0x04000000U /*!<Bit 2 */
+#define FMC_BTR3_DATLAT_3 0x08000000U /*!<Bit 3 */
+
+#define FMC_BTR3_ACCMOD 0x30000000U /*!<ACCMOD[1:0] bits (Access mode) */
+#define FMC_BTR3_ACCMOD_0 0x10000000U /*!<Bit 0 */
+#define FMC_BTR3_ACCMOD_1 0x20000000U /*!<Bit 1 */
+
+/****************** Bit definition for FMC_BTR4 register *******************/
+#define FMC_BTR4_ADDSET 0x0000000FU /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FMC_BTR4_ADDSET_0 0x00000001U /*!<Bit 0 */
+#define FMC_BTR4_ADDSET_1 0x00000002U /*!<Bit 1 */
+#define FMC_BTR4_ADDSET_2 0x00000004U /*!<Bit 2 */
+#define FMC_BTR4_ADDSET_3 0x00000008U /*!<Bit 3 */
+
+#define FMC_BTR4_ADDHLD 0x000000F0U /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FMC_BTR4_ADDHLD_0 0x00000010U /*!<Bit 0 */
+#define FMC_BTR4_ADDHLD_1 0x00000020U /*!<Bit 1 */
+#define FMC_BTR4_ADDHLD_2 0x00000040U /*!<Bit 2 */
+#define FMC_BTR4_ADDHLD_3 0x00000080U /*!<Bit 3 */
+
+#define FMC_BTR4_DATAST 0x0000FF00U /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FMC_BTR4_DATAST_0 0x00000100U /*!<Bit 0 */
+#define FMC_BTR4_DATAST_1 0x00000200U /*!<Bit 1 */
+#define FMC_BTR4_DATAST_2 0x00000400U /*!<Bit 2 */
+#define FMC_BTR4_DATAST_3 0x00000800U /*!<Bit 3 */
+#define FMC_BTR4_DATAST_4 0x00001000U /*!<Bit 4 */
+#define FMC_BTR4_DATAST_5 0x00002000U /*!<Bit 5 */
+#define FMC_BTR4_DATAST_6 0x00004000U /*!<Bit 6 */
+#define FMC_BTR4_DATAST_7 0x00008000U /*!<Bit 7 */
+
+#define FMC_BTR4_BUSTURN 0x000F0000U /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define FMC_BTR4_BUSTURN_0 0x00010000U /*!<Bit 0 */
+#define FMC_BTR4_BUSTURN_1 0x00020000U /*!<Bit 1 */
+#define FMC_BTR4_BUSTURN_2 0x00040000U /*!<Bit 2 */
+#define FMC_BTR4_BUSTURN_3 0x00080000U /*!<Bit 3 */
+
+#define FMC_BTR4_CLKDIV 0x00F00000U /*!<CLKDIV[3:0] bits (Clock divide ratio) */
+#define FMC_BTR4_CLKDIV_0 0x00100000U /*!<Bit 0 */
+#define FMC_BTR4_CLKDIV_1 0x00200000U /*!<Bit 1 */
+#define FMC_BTR4_CLKDIV_2 0x00400000U /*!<Bit 2 */
+#define FMC_BTR4_CLKDIV_3 0x00800000U /*!<Bit 3 */
+
+#define FMC_BTR4_DATLAT 0x0F000000U /*!<DATLA[3:0] bits (Data latency) */
+#define FMC_BTR4_DATLAT_0 0x01000000U /*!<Bit 0 */
+#define FMC_BTR4_DATLAT_1 0x02000000U /*!<Bit 1 */
+#define FMC_BTR4_DATLAT_2 0x04000000U /*!<Bit 2 */
+#define FMC_BTR4_DATLAT_3 0x08000000U /*!<Bit 3 */
+
+#define FMC_BTR4_ACCMOD 0x30000000U /*!<ACCMOD[1:0] bits (Access mode) */
+#define FMC_BTR4_ACCMOD_0 0x10000000U /*!<Bit 0 */
+#define FMC_BTR4_ACCMOD_1 0x20000000U /*!<Bit 1 */
+
+/****************** Bit definition for FMC_BWTR1 register ******************/
+#define FMC_BWTR1_ADDSET 0x0000000FU /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FMC_BWTR1_ADDSET_0 0x00000001U /*!<Bit 0 */
+#define FMC_BWTR1_ADDSET_1 0x00000002U /*!<Bit 1 */
+#define FMC_BWTR1_ADDSET_2 0x00000004U /*!<Bit 2 */
+#define FMC_BWTR1_ADDSET_3 0x00000008U /*!<Bit 3 */
+
+#define FMC_BWTR1_ADDHLD 0x000000F0U /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FMC_BWTR1_ADDHLD_0 0x00000010U /*!<Bit 0 */
+#define FMC_BWTR1_ADDHLD_1 0x00000020U /*!<Bit 1 */
+#define FMC_BWTR1_ADDHLD_2 0x00000040U /*!<Bit 2 */
+#define FMC_BWTR1_ADDHLD_3 0x00000080U /*!<Bit 3 */
+
+#define FMC_BWTR1_DATAST 0x0000FF00U /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FMC_BWTR1_DATAST_0 0x00000100U /*!<Bit 0 */
+#define FMC_BWTR1_DATAST_1 0x00000200U /*!<Bit 1 */
+#define FMC_BWTR1_DATAST_2 0x00000400U /*!<Bit 2 */
+#define FMC_BWTR1_DATAST_3 0x00000800U /*!<Bit 3 */
+#define FMC_BWTR1_DATAST_4 0x00001000U /*!<Bit 4 */
+#define FMC_BWTR1_DATAST_5 0x00002000U /*!<Bit 5 */
+#define FMC_BWTR1_DATAST_6 0x00004000U /*!<Bit 6 */
+#define FMC_BWTR1_DATAST_7 0x00008000U /*!<Bit 7 */
+
+#define FMC_BWTR1_BUSTURN 0x000F0000U /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
+#define FMC_BWTR1_BUSTURN_0 0x00010000U /*!<Bit 0 */
+#define FMC_BWTR1_BUSTURN_1 0x00020000U /*!<Bit 1 */
+#define FMC_BWTR1_BUSTURN_2 0x00040000U /*!<Bit 2 */
+#define FMC_BWTR1_BUSTURN_3 0x00080000U /*!<Bit 3 */
+
+#define FMC_BWTR1_ACCMOD 0x30000000U /*!<ACCMOD[1:0] bits (Access mode) */
+#define FMC_BWTR1_ACCMOD_0 0x10000000U /*!<Bit 0 */
+#define FMC_BWTR1_ACCMOD_1 0x20000000U /*!<Bit 1 */
+
+/****************** Bit definition for FMC_BWTR2 register ******************/
+#define FMC_BWTR2_ADDSET 0x0000000FU /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FMC_BWTR2_ADDSET_0 0x00000001U /*!<Bit 0 */
+#define FMC_BWTR2_ADDSET_1 0x00000002U /*!<Bit 1 */
+#define FMC_BWTR2_ADDSET_2 0x00000004U /*!<Bit 2 */
+#define FMC_BWTR2_ADDSET_3 0x00000008U /*!<Bit 3 */
+
+#define FMC_BWTR2_ADDHLD 0x000000F0U /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FMC_BWTR2_ADDHLD_0 0x00000010U /*!<Bit 0 */
+#define FMC_BWTR2_ADDHLD_1 0x00000020U /*!<Bit 1 */
+#define FMC_BWTR2_ADDHLD_2 0x00000040U /*!<Bit 2 */
+#define FMC_BWTR2_ADDHLD_3 0x00000080U /*!<Bit 3 */
+
+#define FMC_BWTR2_DATAST 0x0000FF00U /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FMC_BWTR2_DATAST_0 0x00000100U /*!<Bit 0 */
+#define FMC_BWTR2_DATAST_1 0x00000200U /*!<Bit 1 */
+#define FMC_BWTR2_DATAST_2 0x00000400U /*!<Bit 2 */
+#define FMC_BWTR2_DATAST_3 0x00000800U /*!<Bit 3 */
+#define FMC_BWTR2_DATAST_4 0x00001000U /*!<Bit 4 */
+#define FMC_BWTR2_DATAST_5 0x00002000U /*!<Bit 5 */
+#define FMC_BWTR2_DATAST_6 0x00004000U /*!<Bit 6 */
+#define FMC_BWTR2_DATAST_7 0x00008000U /*!<Bit 7 */
+
+#define FMC_BWTR2_BUSTURN 0x000F0000U /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
+#define FMC_BWTR2_BUSTURN_0 0x00010000U /*!<Bit 0 */
+#define FMC_BWTR2_BUSTURN_1 0x00020000U /*!<Bit 1 */
+#define FMC_BWTR2_BUSTURN_2 0x00040000U /*!<Bit 2 */
+#define FMC_BWTR2_BUSTURN_3 0x00080000U /*!<Bit 3 */
+
+#define FMC_BWTR2_ACCMOD 0x30000000U /*!<ACCMOD[1:0] bits (Access mode) */
+#define FMC_BWTR2_ACCMOD_0 0x10000000U /*!<Bit 0 */
+#define FMC_BWTR2_ACCMOD_1 0x20000000U /*!<Bit 1 */
+
+/****************** Bit definition for FMC_BWTR3 register ******************/
+#define FMC_BWTR3_ADDSET 0x0000000FU /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FMC_BWTR3_ADDSET_0 0x00000001U /*!<Bit 0 */
+#define FMC_BWTR3_ADDSET_1 0x00000002U /*!<Bit 1 */
+#define FMC_BWTR3_ADDSET_2 0x00000004U /*!<Bit 2 */
+#define FMC_BWTR3_ADDSET_3 0x00000008U /*!<Bit 3 */
+
+#define FMC_BWTR3_ADDHLD 0x000000F0U /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FMC_BWTR3_ADDHLD_0 0x00000010U /*!<Bit 0 */
+#define FMC_BWTR3_ADDHLD_1 0x00000020U /*!<Bit 1 */
+#define FMC_BWTR3_ADDHLD_2 0x00000040U /*!<Bit 2 */
+#define FMC_BWTR3_ADDHLD_3 0x00000080U /*!<Bit 3 */
+
+#define FMC_BWTR3_DATAST 0x0000FF00U /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FMC_BWTR3_DATAST_0 0x00000100U /*!<Bit 0 */
+#define FMC_BWTR3_DATAST_1 0x00000200U /*!<Bit 1 */
+#define FMC_BWTR3_DATAST_2 0x00000400U /*!<Bit 2 */
+#define FMC_BWTR3_DATAST_3 0x00000800U /*!<Bit 3 */
+#define FMC_BWTR3_DATAST_4 0x00001000U /*!<Bit 4 */
+#define FMC_BWTR3_DATAST_5 0x00002000U /*!<Bit 5 */
+#define FMC_BWTR3_DATAST_6 0x00004000U /*!<Bit 6 */
+#define FMC_BWTR3_DATAST_7 0x00008000U /*!<Bit 7 */
+
+#define FMC_BWTR3_BUSTURN 0x000F0000U /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
+#define FMC_BWTR3_BUSTURN_0 0x00010000U /*!<Bit 0 */
+#define FMC_BWTR3_BUSTURN_1 0x00020000U /*!<Bit 1 */
+#define FMC_BWTR3_BUSTURN_2 0x00040000U /*!<Bit 2 */
+#define FMC_BWTR3_BUSTURN_3 0x00080000U /*!<Bit 3 */
+
+#define FMC_BWTR3_ACCMOD 0x30000000U /*!<ACCMOD[1:0] bits (Access mode) */
+#define FMC_BWTR3_ACCMOD_0 0x10000000U /*!<Bit 0 */
+#define FMC_BWTR3_ACCMOD_1 0x20000000U /*!<Bit 1 */
+
+/****************** Bit definition for FMC_BWTR4 register ******************/
+#define FMC_BWTR4_ADDSET 0x0000000FU /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FMC_BWTR4_ADDSET_0 0x00000001U /*!<Bit 0 */
+#define FMC_BWTR4_ADDSET_1 0x00000002U /*!<Bit 1 */
+#define FMC_BWTR4_ADDSET_2 0x00000004U /*!<Bit 2 */
+#define FMC_BWTR4_ADDSET_3 0x00000008U /*!<Bit 3 */
+
+#define FMC_BWTR4_ADDHLD 0x000000F0U /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FMC_BWTR4_ADDHLD_0 0x00000010U /*!<Bit 0 */
+#define FMC_BWTR4_ADDHLD_1 0x00000020U /*!<Bit 1 */
+#define FMC_BWTR4_ADDHLD_2 0x00000040U /*!<Bit 2 */
+#define FMC_BWTR4_ADDHLD_3 0x00000080U /*!<Bit 3 */
+
+#define FMC_BWTR4_DATAST 0x0000FF00U /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FMC_BWTR4_DATAST_0 0x00000100U /*!<Bit 0 */
+#define FMC_BWTR4_DATAST_1 0x00000200U /*!<Bit 1 */
+#define FMC_BWTR4_DATAST_2 0x00000400U /*!<Bit 2 */
+#define FMC_BWTR4_DATAST_3 0x00000800U /*!<Bit 3 */
+#define FMC_BWTR4_DATAST_4 0x00001000U /*!<Bit 4 */
+#define FMC_BWTR4_DATAST_5 0x00002000U /*!<Bit 5 */
+#define FMC_BWTR4_DATAST_6 0x00004000U /*!<Bit 6 */
+#define FMC_BWTR4_DATAST_7 0x00008000U /*!<Bit 7 */
+
+#define FMC_BWTR4_BUSTURN 0x000F0000U /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
+#define FMC_BWTR4_BUSTURN_0 0x00010000U /*!<Bit 0 */
+#define FMC_BWTR4_BUSTURN_1 0x00020000U /*!<Bit 1 */
+#define FMC_BWTR4_BUSTURN_2 0x00040000U /*!<Bit 2 */
+#define FMC_BWTR4_BUSTURN_3 0x00080000U /*!<Bit 3 */
+
+#define FMC_BWTR4_ACCMOD 0x30000000U /*!<ACCMOD[1:0] bits (Access mode) */
+#define FMC_BWTR4_ACCMOD_0 0x10000000U /*!<Bit 0 */
+#define FMC_BWTR4_ACCMOD_1 0x20000000U /*!<Bit 1 */
+
+/****************** Bit definition for FMC_PCR register *******************/
+#define FMC_PCR_PWAITEN 0x00000002U /*!<Wait feature enable bit */
+#define FMC_PCR_PBKEN 0x00000004U /*!<PC Card/NAND Flash memory bank enable bit */
+#define FMC_PCR_PTYP 0x00000008U /*!<Memory type */
+
+#define FMC_PCR_PWID 0x00000030U /*!<PWID[1:0] bits (NAND Flash databus width) */
+#define FMC_PCR_PWID_0 0x00000010U /*!<Bit 0 */
+#define FMC_PCR_PWID_1 0x00000020U /*!<Bit 1 */
+
+#define FMC_PCR_ECCEN 0x00000040U /*!<ECC computation logic enable bit */
+
+#define FMC_PCR_TCLR 0x00001E00U /*!<TCLR[3:0] bits (CLE to RE delay) */
+#define FMC_PCR_TCLR_0 0x00000200U /*!<Bit 0 */
+#define FMC_PCR_TCLR_1 0x00000400U /*!<Bit 1 */
+#define FMC_PCR_TCLR_2 0x00000800U /*!<Bit 2 */
+#define FMC_PCR_TCLR_3 0x00001000U /*!<Bit 3 */
+
+#define FMC_PCR_TAR 0x0001E000U /*!<TAR[3:0] bits (ALE to RE delay) */
+#define FMC_PCR_TAR_0 0x00002000U /*!<Bit 0 */
+#define FMC_PCR_TAR_1 0x00004000U /*!<Bit 1 */
+#define FMC_PCR_TAR_2 0x00008000U /*!<Bit 2 */
+#define FMC_PCR_TAR_3 0x00010000U /*!<Bit 3 */
+
+#define FMC_PCR_ECCPS 0x000E0000U /*!<ECCPS[1:0] bits (ECC page size) */
+#define FMC_PCR_ECCPS_0 0x00020000U /*!<Bit 0 */
+#define FMC_PCR_ECCPS_1 0x00040000U /*!<Bit 1 */
+#define FMC_PCR_ECCPS_2 0x00080000U /*!<Bit 2 */
+
+/******************* Bit definition for FMC_SR register *******************/
+#define FMC_SR_IRS 0x01U /*!<Interrupt Rising Edge status */
+#define FMC_SR_ILS 0x02U /*!<Interrupt Level status */
+#define FMC_SR_IFS 0x04U /*!<Interrupt Falling Edge status */
+#define FMC_SR_IREN 0x08U /*!<Interrupt Rising Edge detection Enable bit */
+#define FMC_SR_ILEN 0x10U /*!<Interrupt Level detection Enable bit */
+#define FMC_SR_IFEN 0x20U /*!<Interrupt Falling Edge detection Enable bit */
+#define FMC_SR_FEMPT 0x40U /*!<FIFO empty */
+
+/****************** Bit definition for FMC_PMEM register ******************/
+#define FMC_PMEM_MEMSET2 0x000000FFU /*!<MEMSET2[7:0] bits (Common memory 2 setup time) */
+#define FMC_PMEM_MEMSET2_0 0x00000001U /*!<Bit 0 */
+#define FMC_PMEM_MEMSET2_1 0x00000002U /*!<Bit 1 */
+#define FMC_PMEM_MEMSET2_2 0x00000004U /*!<Bit 2 */
+#define FMC_PMEM_MEMSET2_3 0x00000008U /*!<Bit 3 */
+#define FMC_PMEM_MEMSET2_4 0x00000010U /*!<Bit 4 */
+#define FMC_PMEM_MEMSET2_5 0x00000020U /*!<Bit 5 */
+#define FMC_PMEM_MEMSET2_6 0x00000040U /*!<Bit 6 */
+#define FMC_PMEM_MEMSET2_7 0x00000080U /*!<Bit 7 */
+
+#define FMC_PMEM_MEMWAIT2 0x0000FF00U /*!<MEMWAIT2[7:0] bits (Common memory 2 wait time) */
+#define FMC_PMEM_MEMWAIT2_0 0x00000100U /*!<Bit 0 */
+#define FMC_PMEM_MEMWAIT2_1 0x00000200U /*!<Bit 1 */
+#define FMC_PMEM_MEMWAIT2_2 0x00000400U /*!<Bit 2 */
+#define FMC_PMEM_MEMWAIT2_3 0x00000800U /*!<Bit 3 */
+#define FMC_PMEM_MEMWAIT2_4 0x00001000U /*!<Bit 4 */
+#define FMC_PMEM_MEMWAIT2_5 0x00002000U /*!<Bit 5 */
+#define FMC_PMEM_MEMWAIT2_6 0x00004000U /*!<Bit 6 */
+#define FMC_PMEM_MEMWAIT2_7 0x00008000U /*!<Bit 7 */
+
+#define FMC_PMEM_MEMHOLD2 0x00FF0000U /*!<MEMHOLD2[7:0] bits (Common memory 2 hold time) */
+#define FMC_PMEM_MEMHOLD2_0 0x00010000U /*!<Bit 0 */
+#define FMC_PMEM_MEMHOLD2_1 0x00020000U /*!<Bit 1 */
+#define FMC_PMEM_MEMHOLD2_2 0x00040000U /*!<Bit 2 */
+#define FMC_PMEM_MEMHOLD2_3 0x00080000U /*!<Bit 3 */
+#define FMC_PMEM_MEMHOLD2_4 0x00100000U /*!<Bit 4 */
+#define FMC_PMEM_MEMHOLD2_5 0x00200000U /*!<Bit 5 */
+#define FMC_PMEM_MEMHOLD2_6 0x00400000U /*!<Bit 6 */
+#define FMC_PMEM_MEMHOLD2_7 0x00800000U /*!<Bit 7 */
+
+#define FMC_PMEM_MEMHIZ2 0xFF000000U /*!<MEMHIZ2[7:0] bits (Common memory 2 databus HiZ time) */
+#define FMC_PMEM_MEMHIZ2_0 0x01000000U /*!<Bit 0 */
+#define FMC_PMEM_MEMHIZ2_1 0x02000000U /*!<Bit 1 */
+#define FMC_PMEM_MEMHIZ2_2 0x04000000U /*!<Bit 2 */
+#define FMC_PMEM_MEMHIZ2_3 0x08000000U /*!<Bit 3 */
+#define FMC_PMEM_MEMHIZ2_4 0x10000000U /*!<Bit 4 */
+#define FMC_PMEM_MEMHIZ2_5 0x20000000U /*!<Bit 5 */
+#define FMC_PMEM_MEMHIZ2_6 0x40000000U /*!<Bit 6 */
+#define FMC_PMEM_MEMHIZ2_7 0x80000000U /*!<Bit 7 */
+
+/****************** Bit definition for FMC_PATT register ******************/
+#define FMC_PATT_ATTSET2 0x000000FFU /*!<ATTSET2[7:0] bits (Attribute memory 2 setup time) */
+#define FMC_PATT_ATTSET2_0 0x00000001U /*!<Bit 0 */
+#define FMC_PATT_ATTSET2_1 0x00000002U /*!<Bit 1 */
+#define FMC_PATT_ATTSET2_2 0x00000004U /*!<Bit 2 */
+#define FMC_PATT_ATTSET2_3 0x00000008U /*!<Bit 3 */
+#define FMC_PATT_ATTSET2_4 0x00000010U /*!<Bit 4 */
+#define FMC_PATT_ATTSET2_5 0x00000020U /*!<Bit 5 */
+#define FMC_PATT_ATTSET2_6 0x00000040U /*!<Bit 6 */
+#define FMC_PATT_ATTSET2_7 0x00000080U /*!<Bit 7 */
+
+#define FMC_PATT_ATTWAIT2 0x0000FF00U /*!<ATTWAIT2[7:0] bits (Attribute memory 2 wait time) */
+#define FMC_PATT_ATTWAIT2_0 0x00000100U /*!<Bit 0 */
+#define FMC_PATT_ATTWAIT2_1 0x00000200U /*!<Bit 1 */
+#define FMC_PATT_ATTWAIT2_2 0x00000400U /*!<Bit 2 */
+#define FMC_PATT_ATTWAIT2_3 0x00000800U /*!<Bit 3 */
+#define FMC_PATT_ATTWAIT2_4 0x00001000U /*!<Bit 4 */
+#define FMC_PATT_ATTWAIT2_5 0x00002000U /*!<Bit 5 */
+#define FMC_PATT_ATTWAIT2_6 0x00004000U /*!<Bit 6 */
+#define FMC_PATT_ATTWAIT2_7 0x00008000U /*!<Bit 7 */
+
+#define FMC_PATT_ATTHOLD2 0x00FF0000U /*!<ATTHOLD2[7:0] bits (Attribute memory 2 hold time) */
+#define FMC_PATT_ATTHOLD2_0 0x00010000U /*!<Bit 0 */
+#define FMC_PATT_ATTHOLD2_1 0x00020000U /*!<Bit 1 */
+#define FMC_PATT_ATTHOLD2_2 0x00040000U /*!<Bit 2 */
+#define FMC_PATT_ATTHOLD2_3 0x00080000U /*!<Bit 3 */
+#define FMC_PATT_ATTHOLD2_4 0x00100000U /*!<Bit 4 */
+#define FMC_PATT_ATTHOLD2_5 0x00200000U /*!<Bit 5 */
+#define FMC_PATT_ATTHOLD2_6 0x00400000U /*!<Bit 6 */
+#define FMC_PATT_ATTHOLD2_7 0x00800000U /*!<Bit 7 */
+
+#define FMC_PATT_ATTHIZ2 0xFF000000U /*!<ATTHIZ2[7:0] bits (Attribute memory 2 databus HiZ time) */
+#define FMC_PATT_ATTHIZ2_0 0x01000000U /*!<Bit 0 */
+#define FMC_PATT_ATTHIZ2_1 0x02000000U /*!<Bit 1 */
+#define FMC_PATT_ATTHIZ2_2 0x04000000U /*!<Bit 2 */
+#define FMC_PATT_ATTHIZ2_3 0x08000000U /*!<Bit 3 */
+#define FMC_PATT_ATTHIZ2_4 0x10000000U /*!<Bit 4 */
+#define FMC_PATT_ATTHIZ2_5 0x20000000U /*!<Bit 5 */
+#define FMC_PATT_ATTHIZ2_6 0x40000000U /*!<Bit 6 */
+#define FMC_PATT_ATTHIZ2_7 0x80000000U /*!<Bit 7 */
+
+/****************** Bit definition for FMC_ECCR register ******************/
+#define FMC_ECCR_ECC2 0xFFFFFFFFU /*!<ECC result */
+
+/****************** Bit definition for FMC_SDCR1 register ******************/
+#define FMC_SDCR1_NC 0x00000003U /*!<NC[1:0] bits (Number of column bits) */
+#define FMC_SDCR1_NC_0 0x00000001U /*!<Bit 0 */
+#define FMC_SDCR1_NC_1 0x00000002U /*!<Bit 1 */
+
+#define FMC_SDCR1_NR 0x0000000CU /*!<NR[1:0] bits (Number of row bits) */
+#define FMC_SDCR1_NR_0 0x00000004U /*!<Bit 0 */
+#define FMC_SDCR1_NR_1 0x00000008U /*!<Bit 1 */
+
+#define FMC_SDCR1_MWID 0x00000030U /*!<NR[1:0] bits (Number of row bits) */
+#define FMC_SDCR1_MWID_0 0x00000010U /*!<Bit 0 */
+#define FMC_SDCR1_MWID_1 0x00000020U /*!<Bit 1 */
+
+#define FMC_SDCR1_NB 0x00000040U /*!<Number of internal bank */
+
+#define FMC_SDCR1_CAS 0x00000180U /*!<CAS[1:0] bits (CAS latency) */
+#define FMC_SDCR1_CAS_0 0x00000080U /*!<Bit 0 */
+#define FMC_SDCR1_CAS_1 0x00000100U /*!<Bit 1 */
+
+#define FMC_SDCR1_WP 0x00000200U /*!<Write protection */
+
+#define FMC_SDCR1_SDCLK 0x00000C00U /*!<SDRAM clock configuration */
+#define FMC_SDCR1_SDCLK_0 0x00000400U /*!<Bit 0 */
+#define FMC_SDCR1_SDCLK_1 0x00000800U /*!<Bit 1 */
+
+#define FMC_SDCR1_RBURST 0x00001000U /*!<Read burst */
+
+#define FMC_SDCR1_RPIPE 0x00006000U /*!<Write protection */
+#define FMC_SDCR1_RPIPE_0 0x00002000U /*!<Bit 0 */
+#define FMC_SDCR1_RPIPE_1 0x00004000U /*!<Bit 1 */
+
+/****************** Bit definition for FMC_SDCR2 register ******************/
+#define FMC_SDCR2_NC 0x00000003U /*!<NC[1:0] bits (Number of column bits) */
+#define FMC_SDCR2_NC_0 0x00000001U /*!<Bit 0 */
+#define FMC_SDCR2_NC_1 0x00000002U /*!<Bit 1 */
+
+#define FMC_SDCR2_NR 0x0000000CU /*!<NR[1:0] bits (Number of row bits) */
+#define FMC_SDCR2_NR_0 0x00000004U /*!<Bit 0 */
+#define FMC_SDCR2_NR_1 0x00000008U /*!<Bit 1 */
+
+#define FMC_SDCR2_MWID 0x00000030U /*!<NR[1:0] bits (Number of row bits) */
+#define FMC_SDCR2_MWID_0 0x00000010U /*!<Bit 0 */
+#define FMC_SDCR2_MWID_1 0x00000020U /*!<Bit 1 */
+
+#define FMC_SDCR2_NB 0x00000040U /*!<Number of internal bank */
+
+#define FMC_SDCR2_CAS 0x00000180U /*!<CAS[1:0] bits (CAS latency) */
+#define FMC_SDCR2_CAS_0 0x00000080U /*!<Bit 0 */
+#define FMC_SDCR2_CAS_1 0x00000100U /*!<Bit 1 */
+
+#define FMC_SDCR2_WP 0x00000200U /*!<Write protection */
+
+#define FMC_SDCR2_SDCLK 0x00000C00U /*!<SDCLK[1:0] (SDRAM clock configuration) */
+#define FMC_SDCR2_SDCLK_0 0x00000400U /*!<Bit 0 */
+#define FMC_SDCR2_SDCLK_1 0x00000800U /*!<Bit 1 */
+
+#define FMC_SDCR2_RBURST 0x00001000U /*!<Read burst */
+
+#define FMC_SDCR2_RPIPE 0x00006000U /*!<RPIPE[1:0](Read pipe) */
+#define FMC_SDCR2_RPIPE_0 0x00002000U /*!<Bit 0 */
+#define FMC_SDCR2_RPIPE_1 0x00004000U /*!<Bit 1 */
+
+/****************** Bit definition for FMC_SDTR1 register ******************/
+#define FMC_SDTR1_TMRD 0x0000000FU /*!<TMRD[3:0] bits (Load mode register to active) */
+#define FMC_SDTR1_TMRD_0 0x00000001U /*!<Bit 0 */
+#define FMC_SDTR1_TMRD_1 0x00000002U /*!<Bit 1 */
+#define FMC_SDTR1_TMRD_2 0x00000004U /*!<Bit 2 */
+#define FMC_SDTR1_TMRD_3 0x00000008U /*!<Bit 3 */
+
+#define FMC_SDTR1_TXSR 0x000000F0U /*!<TXSR[3:0] bits (Exit self refresh) */
+#define FMC_SDTR1_TXSR_0 0x00000010U /*!<Bit 0 */
+#define FMC_SDTR1_TXSR_1 0x00000020U /*!<Bit 1 */
+#define FMC_SDTR1_TXSR_2 0x00000040U /*!<Bit 2 */
+#define FMC_SDTR1_TXSR_3 0x00000080U /*!<Bit 3 */
+
+#define FMC_SDTR1_TRAS 0x00000F00U /*!<TRAS[3:0] bits (Self refresh time) */
+#define FMC_SDTR1_TRAS_0 0x00000100U /*!<Bit 0 */
+#define FMC_SDTR1_TRAS_1 0x00000200U /*!<Bit 1 */
+#define FMC_SDTR1_TRAS_2 0x00000400U /*!<Bit 2 */
+#define FMC_SDTR1_TRAS_3 0x00000800U /*!<Bit 3 */
+
+#define FMC_SDTR1_TRC 0x0000F000U /*!<TRC[2:0] bits (Row cycle delay) */
+#define FMC_SDTR1_TRC_0 0x00001000U /*!<Bit 0 */
+#define FMC_SDTR1_TRC_1 0x00002000U /*!<Bit 1 */
+#define FMC_SDTR1_TRC_2 0x00004000U /*!<Bit 2 */
+
+#define FMC_SDTR1_TWR 0x000F0000U /*!<TRC[2:0] bits (Write recovery delay) */
+#define FMC_SDTR1_TWR_0 0x00010000U /*!<Bit 0 */
+#define FMC_SDTR1_TWR_1 0x00020000U /*!<Bit 1 */
+#define FMC_SDTR1_TWR_2 0x00040000U /*!<Bit 2 */
+
+#define FMC_SDTR1_TRP 0x00F00000U /*!<TRP[2:0] bits (Row precharge delay) */
+#define FMC_SDTR1_TRP_0 0x00100000U /*!<Bit 0 */
+#define FMC_SDTR1_TRP_1 0x00200000U /*!<Bit 1 */
+#define FMC_SDTR1_TRP_2 0x00400000U /*!<Bit 2 */
+
+#define FMC_SDTR1_TRCD 0x0F000000U /*!<TRP[2:0] bits (Row to column delay) */
+#define FMC_SDTR1_TRCD_0 0x01000000U /*!<Bit 0 */
+#define FMC_SDTR1_TRCD_1 0x02000000U /*!<Bit 1 */
+#define FMC_SDTR1_TRCD_2 0x04000000U /*!<Bit 2 */
+
+/****************** Bit definition for FMC_SDTR2 register ******************/
+#define FMC_SDTR2_TMRD 0x0000000FU /*!<TMRD[3:0] bits (Load mode register to active) */
+#define FMC_SDTR2_TMRD_0 0x00000001U /*!<Bit 0 */
+#define FMC_SDTR2_TMRD_1 0x00000002U /*!<Bit 1 */
+#define FMC_SDTR2_TMRD_2 0x00000004U /*!<Bit 2 */
+#define FMC_SDTR2_TMRD_3 0x00000008U /*!<Bit 3 */
+
+#define FMC_SDTR2_TXSR 0x000000F0U /*!<TXSR[3:0] bits (Exit self refresh) */
+#define FMC_SDTR2_TXSR_0 0x00000010U /*!<Bit 0 */
+#define FMC_SDTR2_TXSR_1 0x00000020U /*!<Bit 1 */
+#define FMC_SDTR2_TXSR_2 0x00000040U /*!<Bit 2 */
+#define FMC_SDTR2_TXSR_3 0x00000080U /*!<Bit 3 */
+
+#define FMC_SDTR2_TRAS 0x00000F00U /*!<TRAS[3:0] bits (Self refresh time) */
+#define FMC_SDTR2_TRAS_0 0x00000100U /*!<Bit 0 */
+#define FMC_SDTR2_TRAS_1 0x00000200U /*!<Bit 1 */
+#define FMC_SDTR2_TRAS_2 0x00000400U /*!<Bit 2 */
+#define FMC_SDTR2_TRAS_3 0x00000800U /*!<Bit 3 */
+
+#define FMC_SDTR2_TRC 0x0000F000U /*!<TRC[2:0] bits (Row cycle delay) */
+#define FMC_SDTR2_TRC_0 0x00001000U /*!<Bit 0 */
+#define FMC_SDTR2_TRC_1 0x00002000U /*!<Bit 1 */
+#define FMC_SDTR2_TRC_2 0x00004000U /*!<Bit 2 */
+
+#define FMC_SDTR2_TWR 0x000F0000U /*!<TRC[2:0] bits (Write recovery delay) */
+#define FMC_SDTR2_TWR_0 0x00010000U /*!<Bit 0 */
+#define FMC_SDTR2_TWR_1 0x00020000U /*!<Bit 1 */
+#define FMC_SDTR2_TWR_2 0x00040000U /*!<Bit 2 */
+
+#define FMC_SDTR2_TRP 0x00F00000U /*!<TRP[2:0] bits (Row precharge delay) */
+#define FMC_SDTR2_TRP_0 0x00100000U /*!<Bit 0 */
+#define FMC_SDTR2_TRP_1 0x00200000U /*!<Bit 1 */
+#define FMC_SDTR2_TRP_2 0x00400000U /*!<Bit 2 */
+
+#define FMC_SDTR2_TRCD 0x0F000000U /*!<TRP[2:0] bits (Row to column delay) */
+#define FMC_SDTR2_TRCD_0 0x01000000U /*!<Bit 0 */
+#define FMC_SDTR2_TRCD_1 0x02000000U /*!<Bit 1 */
+#define FMC_SDTR2_TRCD_2 0x04000000U /*!<Bit 2 */
+
+/****************** Bit definition for FMC_SDCMR register ******************/
+#define FMC_SDCMR_MODE 0x00000007U /*!<MODE[2:0] bits (Command mode) */
+#define FMC_SDCMR_MODE_0 0x00000001U /*!<Bit 0 */
+#define FMC_SDCMR_MODE_1 0x00000002U /*!<Bit 1 */
+#define FMC_SDCMR_MODE_2 0x00000004U /*!<Bit 2 */
+
+#define FMC_SDCMR_CTB2 0x00000008U /*!<Command target 2 */
+
+#define FMC_SDCMR_CTB1 0x00000010U /*!<Command target 1 */
+
+#define FMC_SDCMR_NRFS 0x000001E0U /*!<NRFS[3:0] bits (Number of auto-refresh) */
+#define FMC_SDCMR_NRFS_0 0x00000020U /*!<Bit 0 */
+#define FMC_SDCMR_NRFS_1 0x00000040U /*!<Bit 1 */
+#define FMC_SDCMR_NRFS_2 0x00000080U /*!<Bit 2 */
+#define FMC_SDCMR_NRFS_3 0x00000100U /*!<Bit 3 */
+
+#define FMC_SDCMR_MRD 0x003FFE00U /*!<MRD[12:0] bits (Mode register definition) */
+
+/****************** Bit definition for FMC_SDRTR register ******************/
+#define FMC_SDRTR_CRE 0x00000001U /*!<Clear refresh error flag */
+
+#define FMC_SDRTR_COUNT 0x00003FFEU /*!<COUNT[12:0] bits (Refresh timer count) */
+
+#define FMC_SDRTR_REIE 0x00004000U /*!<RES interupt enable */
+
+/****************** Bit definition for FMC_SDSR register ******************/
+#define FMC_SDSR_RE 0x00000001U /*!<Refresh error flag */
+
+#define FMC_SDSR_MODES1 0x00000006U /*!<MODES1[1:0]bits (Status mode for bank 1) */
+#define FMC_SDSR_MODES1_0 0x00000002U /*!<Bit 0 */
+#define FMC_SDSR_MODES1_1 0x00000004U /*!<Bit 1 */
+
+#define FMC_SDSR_MODES2 0x00000018U /*!<MODES2[1:0]bits (Status mode for bank 2) */
+#define FMC_SDSR_MODES2_0 0x00000008U /*!<Bit 0 */
+#define FMC_SDSR_MODES2_1 0x00000010U /*!<Bit 1 */
+#define FMC_SDSR_BUSY 0x00000020U /*!<Busy status */
+
+/******************************************************************************/
+/* */
+/* General Purpose I/O */
+/* */
+/******************************************************************************/
+/****************** Bits definition for GPIO_MODER register *****************/
+#define GPIO_MODER_MODER0 0x00000003U
+#define GPIO_MODER_MODER0_0 0x00000001U
+#define GPIO_MODER_MODER0_1 0x00000002U
+
+#define GPIO_MODER_MODER1 0x0000000CU
+#define GPIO_MODER_MODER1_0 0x00000004U
+#define GPIO_MODER_MODER1_1 0x00000008U
+
+#define GPIO_MODER_MODER2 0x00000030U
+#define GPIO_MODER_MODER2_0 0x00000010U
+#define GPIO_MODER_MODER2_1 0x00000020U
+
+#define GPIO_MODER_MODER3 0x000000C0U
+#define GPIO_MODER_MODER3_0 0x00000040U
+#define GPIO_MODER_MODER3_1 0x00000080U
+
+#define GPIO_MODER_MODER4 0x00000300U
+#define GPIO_MODER_MODER4_0 0x00000100U
+#define GPIO_MODER_MODER4_1 0x00000200U
+
+#define GPIO_MODER_MODER5 0x00000C00U
+#define GPIO_MODER_MODER5_0 0x00000400U
+#define GPIO_MODER_MODER5_1 0x00000800U
+
+#define GPIO_MODER_MODER6 0x00003000U
+#define GPIO_MODER_MODER6_0 0x00001000U
+#define GPIO_MODER_MODER6_1 0x00002000U
+
+#define GPIO_MODER_MODER7 0x0000C000U
+#define GPIO_MODER_MODER7_0 0x00004000U
+#define GPIO_MODER_MODER7_1 0x00008000U
+
+#define GPIO_MODER_MODER8 0x00030000U
+#define GPIO_MODER_MODER8_0 0x00010000U
+#define GPIO_MODER_MODER8_1 0x00020000U
+
+#define GPIO_MODER_MODER9 0x000C0000U
+#define GPIO_MODER_MODER9_0 0x00040000U
+#define GPIO_MODER_MODER9_1 0x00080000U
+
+#define GPIO_MODER_MODER10 0x00300000U
+#define GPIO_MODER_MODER10_0 0x00100000U
+#define GPIO_MODER_MODER10_1 0x00200000U
+
+#define GPIO_MODER_MODER11 0x00C00000U
+#define GPIO_MODER_MODER11_0 0x00400000U
+#define GPIO_MODER_MODER11_1 0x00800000U
+
+#define GPIO_MODER_MODER12 0x03000000U
+#define GPIO_MODER_MODER12_0 0x01000000U
+#define GPIO_MODER_MODER12_1 0x02000000U
+
+#define GPIO_MODER_MODER13 0x0C000000U
+#define GPIO_MODER_MODER13_0 0x04000000U
+#define GPIO_MODER_MODER13_1 0x08000000U
+
+#define GPIO_MODER_MODER14 0x30000000U
+#define GPIO_MODER_MODER14_0 0x10000000U
+#define GPIO_MODER_MODER14_1 0x20000000U
+
+#define GPIO_MODER_MODER15 0xC0000000U
+#define GPIO_MODER_MODER15_0 0x40000000U
+#define GPIO_MODER_MODER15_1 0x80000000U
+
+/****************** Bits definition for GPIO_OTYPER register ****************/
+#define GPIO_OTYPER_OT_0 0x00000001U
+#define GPIO_OTYPER_OT_1 0x00000002U
+#define GPIO_OTYPER_OT_2 0x00000004U
+#define GPIO_OTYPER_OT_3 0x00000008U
+#define GPIO_OTYPER_OT_4 0x00000010U
+#define GPIO_OTYPER_OT_5 0x00000020U
+#define GPIO_OTYPER_OT_6 0x00000040U
+#define GPIO_OTYPER_OT_7 0x00000080U
+#define GPIO_OTYPER_OT_8 0x00000100U
+#define GPIO_OTYPER_OT_9 0x00000200U
+#define GPIO_OTYPER_OT_10 0x00000400U
+#define GPIO_OTYPER_OT_11 0x00000800U
+#define GPIO_OTYPER_OT_12 0x00001000U
+#define GPIO_OTYPER_OT_13 0x00002000U
+#define GPIO_OTYPER_OT_14 0x00004000U
+#define GPIO_OTYPER_OT_15 0x00008000U
+
+/****************** Bits definition for GPIO_OSPEEDR register ***************/
+#define GPIO_OSPEEDER_OSPEEDR0 0x00000003U
+#define GPIO_OSPEEDER_OSPEEDR0_0 0x00000001U
+#define GPIO_OSPEEDER_OSPEEDR0_1 0x00000002U
+
+#define GPIO_OSPEEDER_OSPEEDR1 0x0000000CU
+#define GPIO_OSPEEDER_OSPEEDR1_0 0x00000004U
+#define GPIO_OSPEEDER_OSPEEDR1_1 0x00000008U
+
+#define GPIO_OSPEEDER_OSPEEDR2 0x00000030U
+#define GPIO_OSPEEDER_OSPEEDR2_0 0x00000010U
+#define GPIO_OSPEEDER_OSPEEDR2_1 0x00000020U
+
+#define GPIO_OSPEEDER_OSPEEDR3 0x000000C0U
+#define GPIO_OSPEEDER_OSPEEDR3_0 0x00000040U
+#define GPIO_OSPEEDER_OSPEEDR3_1 0x00000080U
+
+#define GPIO_OSPEEDER_OSPEEDR4 0x00000300U
+#define GPIO_OSPEEDER_OSPEEDR4_0 0x00000100U
+#define GPIO_OSPEEDER_OSPEEDR4_1 0x00000200U
+
+#define GPIO_OSPEEDER_OSPEEDR5 0x00000C00U
+#define GPIO_OSPEEDER_OSPEEDR5_0 0x00000400U
+#define GPIO_OSPEEDER_OSPEEDR5_1 0x00000800U
+
+#define GPIO_OSPEEDER_OSPEEDR6 0x00003000U
+#define GPIO_OSPEEDER_OSPEEDR6_0 0x00001000U
+#define GPIO_OSPEEDER_OSPEEDR6_1 0x00002000U
+
+#define GPIO_OSPEEDER_OSPEEDR7 0x0000C000U
+#define GPIO_OSPEEDER_OSPEEDR7_0 0x00004000U
+#define GPIO_OSPEEDER_OSPEEDR7_1 0x00008000U
+
+#define GPIO_OSPEEDER_OSPEEDR8 0x00030000U
+#define GPIO_OSPEEDER_OSPEEDR8_0 0x00010000U
+#define GPIO_OSPEEDER_OSPEEDR8_1 0x00020000U
+
+#define GPIO_OSPEEDER_OSPEEDR9 0x000C0000U
+#define GPIO_OSPEEDER_OSPEEDR9_0 0x00040000U
+#define GPIO_OSPEEDER_OSPEEDR9_1 0x00080000U
+
+#define GPIO_OSPEEDER_OSPEEDR10 0x00300000U
+#define GPIO_OSPEEDER_OSPEEDR10_0 0x00100000U
+#define GPIO_OSPEEDER_OSPEEDR10_1 0x00200000U
+
+#define GPIO_OSPEEDER_OSPEEDR11 0x00C00000U
+#define GPIO_OSPEEDER_OSPEEDR11_0 0x00400000U
+#define GPIO_OSPEEDER_OSPEEDR11_1 0x00800000U
+
+#define GPIO_OSPEEDER_OSPEEDR12 0x03000000U
+#define GPIO_OSPEEDER_OSPEEDR12_0 0x01000000U
+#define GPIO_OSPEEDER_OSPEEDR12_1 0x02000000U
+
+#define GPIO_OSPEEDER_OSPEEDR13 0x0C000000U
+#define GPIO_OSPEEDER_OSPEEDR13_0 0x04000000U
+#define GPIO_OSPEEDER_OSPEEDR13_1 0x08000000U
+
+#define GPIO_OSPEEDER_OSPEEDR14 0x30000000U
+#define GPIO_OSPEEDER_OSPEEDR14_0 0x10000000U
+#define GPIO_OSPEEDER_OSPEEDR14_1 0x20000000U
+
+#define GPIO_OSPEEDER_OSPEEDR15 0xC0000000U
+#define GPIO_OSPEEDER_OSPEEDR15_0 0x40000000U
+#define GPIO_OSPEEDER_OSPEEDR15_1 0x80000000U
+
+/****************** Bits definition for GPIO_PUPDR register *****************/
+#define GPIO_PUPDR_PUPDR0 0x00000003U
+#define GPIO_PUPDR_PUPDR0_0 0x00000001U
+#define GPIO_PUPDR_PUPDR0_1 0x00000002U
+
+#define GPIO_PUPDR_PUPDR1 0x0000000CU
+#define GPIO_PUPDR_PUPDR1_0 0x00000004U
+#define GPIO_PUPDR_PUPDR1_1 0x00000008U
+
+#define GPIO_PUPDR_PUPDR2 0x00000030U
+#define GPIO_PUPDR_PUPDR2_0 0x00000010U
+#define GPIO_PUPDR_PUPDR2_1 0x00000020U
+
+#define GPIO_PUPDR_PUPDR3 0x000000C0U
+#define GPIO_PUPDR_PUPDR3_0 0x00000040U
+#define GPIO_PUPDR_PUPDR3_1 0x00000080U
+
+#define GPIO_PUPDR_PUPDR4 0x00000300U
+#define GPIO_PUPDR_PUPDR4_0 0x00000100U
+#define GPIO_PUPDR_PUPDR4_1 0x00000200U
+
+#define GPIO_PUPDR_PUPDR5 0x00000C00U
+#define GPIO_PUPDR_PUPDR5_0 0x00000400U
+#define GPIO_PUPDR_PUPDR5_1 0x00000800U
+
+#define GPIO_PUPDR_PUPDR6 0x00003000U
+#define GPIO_PUPDR_PUPDR6_0 0x00001000U
+#define GPIO_PUPDR_PUPDR6_1 0x00002000U
+
+#define GPIO_PUPDR_PUPDR7 0x0000C000U
+#define GPIO_PUPDR_PUPDR7_0 0x00004000U
+#define GPIO_PUPDR_PUPDR7_1 0x00008000U
+
+#define GPIO_PUPDR_PUPDR8 0x00030000U
+#define GPIO_PUPDR_PUPDR8_0 0x00010000U
+#define GPIO_PUPDR_PUPDR8_1 0x00020000U
+
+#define GPIO_PUPDR_PUPDR9 0x000C0000U
+#define GPIO_PUPDR_PUPDR9_0 0x00040000U
+#define GPIO_PUPDR_PUPDR9_1 0x00080000U
+
+#define GPIO_PUPDR_PUPDR10 0x00300000U
+#define GPIO_PUPDR_PUPDR10_0 0x00100000U
+#define GPIO_PUPDR_PUPDR10_1 0x00200000U
+
+#define GPIO_PUPDR_PUPDR11 0x00C00000U
+#define GPIO_PUPDR_PUPDR11_0 0x00400000U
+#define GPIO_PUPDR_PUPDR11_1 0x00800000U
+
+#define GPIO_PUPDR_PUPDR12 0x03000000U
+#define GPIO_PUPDR_PUPDR12_0 0x01000000U
+#define GPIO_PUPDR_PUPDR12_1 0x02000000U
+
+#define GPIO_PUPDR_PUPDR13 0x0C000000U
+#define GPIO_PUPDR_PUPDR13_0 0x04000000U
+#define GPIO_PUPDR_PUPDR13_1 0x08000000U
+
+#define GPIO_PUPDR_PUPDR14 0x30000000U
+#define GPIO_PUPDR_PUPDR14_0 0x10000000U
+#define GPIO_PUPDR_PUPDR14_1 0x20000000U
+
+#define GPIO_PUPDR_PUPDR15 0xC0000000U
+#define GPIO_PUPDR_PUPDR15_0 0x40000000U
+#define GPIO_PUPDR_PUPDR15_1 0x80000000U
+
+/****************** Bits definition for GPIO_IDR register *******************/
+#define GPIO_IDR_IDR_0 0x00000001U
+#define GPIO_IDR_IDR_1 0x00000002U
+#define GPIO_IDR_IDR_2 0x00000004U
+#define GPIO_IDR_IDR_3 0x00000008U
+#define GPIO_IDR_IDR_4 0x00000010U
+#define GPIO_IDR_IDR_5 0x00000020U
+#define GPIO_IDR_IDR_6 0x00000040U
+#define GPIO_IDR_IDR_7 0x00000080U
+#define GPIO_IDR_IDR_8 0x00000100U
+#define GPIO_IDR_IDR_9 0x00000200U
+#define GPIO_IDR_IDR_10 0x00000400U
+#define GPIO_IDR_IDR_11 0x00000800U
+#define GPIO_IDR_IDR_12 0x00001000U
+#define GPIO_IDR_IDR_13 0x00002000U
+#define GPIO_IDR_IDR_14 0x00004000U
+#define GPIO_IDR_IDR_15 0x00008000U
+/* Old GPIO_IDR register bits definition, maintained for legacy purpose */
+#define GPIO_OTYPER_IDR_0 GPIO_IDR_IDR_0
+#define GPIO_OTYPER_IDR_1 GPIO_IDR_IDR_1
+#define GPIO_OTYPER_IDR_2 GPIO_IDR_IDR_2
+#define GPIO_OTYPER_IDR_3 GPIO_IDR_IDR_3
+#define GPIO_OTYPER_IDR_4 GPIO_IDR_IDR_4
+#define GPIO_OTYPER_IDR_5 GPIO_IDR_IDR_5
+#define GPIO_OTYPER_IDR_6 GPIO_IDR_IDR_6
+#define GPIO_OTYPER_IDR_7 GPIO_IDR_IDR_7
+#define GPIO_OTYPER_IDR_8 GPIO_IDR_IDR_8
+#define GPIO_OTYPER_IDR_9 GPIO_IDR_IDR_9
+#define GPIO_OTYPER_IDR_10 GPIO_IDR_IDR_10
+#define GPIO_OTYPER_IDR_11 GPIO_IDR_IDR_11
+#define GPIO_OTYPER_IDR_12 GPIO_IDR_IDR_12
+#define GPIO_OTYPER_IDR_13 GPIO_IDR_IDR_13
+#define GPIO_OTYPER_IDR_14 GPIO_IDR_IDR_14
+#define GPIO_OTYPER_IDR_15 GPIO_IDR_IDR_15
+
+/****************** Bits definition for GPIO_ODR register *******************/
+#define GPIO_ODR_ODR_0 0x00000001U
+#define GPIO_ODR_ODR_1 0x00000002U
+#define GPIO_ODR_ODR_2 0x00000004U
+#define GPIO_ODR_ODR_3 0x00000008U
+#define GPIO_ODR_ODR_4 0x00000010U
+#define GPIO_ODR_ODR_5 0x00000020U
+#define GPIO_ODR_ODR_6 0x00000040U
+#define GPIO_ODR_ODR_7 0x00000080U
+#define GPIO_ODR_ODR_8 0x00000100U
+#define GPIO_ODR_ODR_9 0x00000200U
+#define GPIO_ODR_ODR_10 0x00000400U
+#define GPIO_ODR_ODR_11 0x00000800U
+#define GPIO_ODR_ODR_12 0x00001000U
+#define GPIO_ODR_ODR_13 0x00002000U
+#define GPIO_ODR_ODR_14 0x00004000U
+#define GPIO_ODR_ODR_15 0x00008000U
+/* Old GPIO_ODR register bits definition, maintained for legacy purpose */
+#define GPIO_OTYPER_ODR_0 GPIO_ODR_ODR_0
+#define GPIO_OTYPER_ODR_1 GPIO_ODR_ODR_1
+#define GPIO_OTYPER_ODR_2 GPIO_ODR_ODR_2
+#define GPIO_OTYPER_ODR_3 GPIO_ODR_ODR_3
+#define GPIO_OTYPER_ODR_4 GPIO_ODR_ODR_4
+#define GPIO_OTYPER_ODR_5 GPIO_ODR_ODR_5
+#define GPIO_OTYPER_ODR_6 GPIO_ODR_ODR_6
+#define GPIO_OTYPER_ODR_7 GPIO_ODR_ODR_7
+#define GPIO_OTYPER_ODR_8 GPIO_ODR_ODR_8
+#define GPIO_OTYPER_ODR_9 GPIO_ODR_ODR_9
+#define GPIO_OTYPER_ODR_10 GPIO_ODR_ODR_10
+#define GPIO_OTYPER_ODR_11 GPIO_ODR_ODR_11
+#define GPIO_OTYPER_ODR_12 GPIO_ODR_ODR_12
+#define GPIO_OTYPER_ODR_13 GPIO_ODR_ODR_13
+#define GPIO_OTYPER_ODR_14 GPIO_ODR_ODR_14
+#define GPIO_OTYPER_ODR_15 GPIO_ODR_ODR_15
+
+/****************** Bits definition for GPIO_BSRR register ******************/
+#define GPIO_BSRR_BS_0 0x00000001U
+#define GPIO_BSRR_BS_1 0x00000002U
+#define GPIO_BSRR_BS_2 0x00000004U
+#define GPIO_BSRR_BS_3 0x00000008U
+#define GPIO_BSRR_BS_4 0x00000010U
+#define GPIO_BSRR_BS_5 0x00000020U
+#define GPIO_BSRR_BS_6 0x00000040U
+#define GPIO_BSRR_BS_7 0x00000080U
+#define GPIO_BSRR_BS_8 0x00000100U
+#define GPIO_BSRR_BS_9 0x00000200U
+#define GPIO_BSRR_BS_10 0x00000400U
+#define GPIO_BSRR_BS_11 0x00000800U
+#define GPIO_BSRR_BS_12 0x00001000U
+#define GPIO_BSRR_BS_13 0x00002000U
+#define GPIO_BSRR_BS_14 0x00004000U
+#define GPIO_BSRR_BS_15 0x00008000U
+#define GPIO_BSRR_BR_0 0x00010000U
+#define GPIO_BSRR_BR_1 0x00020000U
+#define GPIO_BSRR_BR_2 0x00040000U
+#define GPIO_BSRR_BR_3 0x00080000U
+#define GPIO_BSRR_BR_4 0x00100000U
+#define GPIO_BSRR_BR_5 0x00200000U
+#define GPIO_BSRR_BR_6 0x00400000U
+#define GPIO_BSRR_BR_7 0x00800000U
+#define GPIO_BSRR_BR_8 0x01000000U
+#define GPIO_BSRR_BR_9 0x02000000U
+#define GPIO_BSRR_BR_10 0x04000000U
+#define GPIO_BSRR_BR_11 0x08000000U
+#define GPIO_BSRR_BR_12 0x10000000U
+#define GPIO_BSRR_BR_13 0x20000000U
+#define GPIO_BSRR_BR_14 0x40000000U
+#define GPIO_BSRR_BR_15 0x80000000U
+
+/****************** Bit definition for GPIO_LCKR register *********************/
+#define GPIO_LCKR_LCK0 0x00000001U
+#define GPIO_LCKR_LCK1 0x00000002U
+#define GPIO_LCKR_LCK2 0x00000004U
+#define GPIO_LCKR_LCK3 0x00000008U
+#define GPIO_LCKR_LCK4 0x00000010U
+#define GPIO_LCKR_LCK5 0x00000020U
+#define GPIO_LCKR_LCK6 0x00000040U
+#define GPIO_LCKR_LCK7 0x00000080U
+#define GPIO_LCKR_LCK8 0x00000100U
+#define GPIO_LCKR_LCK9 0x00000200U
+#define GPIO_LCKR_LCK10 0x00000400U
+#define GPIO_LCKR_LCK11 0x00000800U
+#define GPIO_LCKR_LCK12 0x00001000U
+#define GPIO_LCKR_LCK13 0x00002000U
+#define GPIO_LCKR_LCK14 0x00004000U
+#define GPIO_LCKR_LCK15 0x00008000U
+#define GPIO_LCKR_LCKK 0x00010000U
+
+/******************************************************************************/
+/* */
+/* Inter-integrated Circuit Interface */
+/* */
+/******************************************************************************/
+/******************* Bit definition for I2C_CR1 register ********************/
+#define I2C_CR1_PE 0x00000001U /*!<Peripheral Enable */
+#define I2C_CR1_SMBUS 0x00000002U /*!<SMBus Mode */
+#define I2C_CR1_SMBTYPE 0x00000008U /*!<SMBus Type */
+#define I2C_CR1_ENARP 0x00000010U /*!<ARP Enable */
+#define I2C_CR1_ENPEC 0x00000020U /*!<PEC Enable */
+#define I2C_CR1_ENGC 0x00000040U /*!<General Call Enable */
+#define I2C_CR1_NOSTRETCH 0x00000080U /*!<Clock Stretching Disable (Slave mode) */
+#define I2C_CR1_START 0x00000100U /*!<Start Generation */
+#define I2C_CR1_STOP 0x00000200U /*!<Stop Generation */
+#define I2C_CR1_ACK 0x00000400U /*!<Acknowledge Enable */
+#define I2C_CR1_POS 0x00000800U /*!<Acknowledge/PEC Position (for data reception) */
+#define I2C_CR1_PEC 0x00001000U /*!<Packet Error Checking */
+#define I2C_CR1_ALERT 0x00002000U /*!<SMBus Alert */
+#define I2C_CR1_SWRST 0x00008000U /*!<Software Reset */
+
+/******************* Bit definition for I2C_CR2 register ********************/
+#define I2C_CR2_FREQ 0x0000003FU /*!<FREQ[5:0] bits (Peripheral Clock Frequency) */
+#define I2C_CR2_FREQ_0 0x00000001U /*!<Bit 0 */
+#define I2C_CR2_FREQ_1 0x00000002U /*!<Bit 1 */
+#define I2C_CR2_FREQ_2 0x00000004U /*!<Bit 2 */
+#define I2C_CR2_FREQ_3 0x00000008U /*!<Bit 3 */
+#define I2C_CR2_FREQ_4 0x00000010U /*!<Bit 4 */
+#define I2C_CR2_FREQ_5 0x00000020U /*!<Bit 5 */
+
+#define I2C_CR2_ITERREN 0x00000100U /*!<Error Interrupt Enable */
+#define I2C_CR2_ITEVTEN 0x00000200U /*!<Event Interrupt Enable */
+#define I2C_CR2_ITBUFEN 0x00000400U /*!<Buffer Interrupt Enable */
+#define I2C_CR2_DMAEN 0x00000800U /*!<DMA Requests Enable */
+#define I2C_CR2_LAST 0x00001000U /*!<DMA Last Transfer */
+
+/******************* Bit definition for I2C_OAR1 register *******************/
+#define I2C_OAR1_ADD1_7 0x000000FEU /*!<Interface Address */
+#define I2C_OAR1_ADD8_9 0x00000300U /*!<Interface Address */
+
+#define I2C_OAR1_ADD0 0x00000001U /*!<Bit 0 */
+#define I2C_OAR1_ADD1 0x00000002U /*!<Bit 1 */
+#define I2C_OAR1_ADD2 0x00000004U /*!<Bit 2 */
+#define I2C_OAR1_ADD3 0x00000008U /*!<Bit 3 */
+#define I2C_OAR1_ADD4 0x00000010U /*!<Bit 4 */
+#define I2C_OAR1_ADD5 0x00000020U /*!<Bit 5 */
+#define I2C_OAR1_ADD6 0x00000040U /*!<Bit 6 */
+#define I2C_OAR1_ADD7 0x00000080U /*!<Bit 7 */
+#define I2C_OAR1_ADD8 0x00000100U /*!<Bit 8 */
+#define I2C_OAR1_ADD9 0x00000200U /*!<Bit 9 */
+
+#define I2C_OAR1_ADDMODE 0x00008000U /*!<Addressing Mode (Slave mode) */
+
+/******************* Bit definition for I2C_OAR2 register *******************/
+#define I2C_OAR2_ENDUAL 0x00000001U /*!<Dual addressing mode enable */
+#define I2C_OAR2_ADD2 0x000000FEU /*!<Interface address */
+
+/******************** Bit definition for I2C_DR register ********************/
+#define I2C_DR_DR 0x000000FFU /*!<8-bit Data Register */
+
+/******************* Bit definition for I2C_SR1 register ********************/
+#define I2C_SR1_SB 0x00000001U /*!<Start Bit (Master mode) */
+#define I2C_SR1_ADDR 0x00000002U /*!<Address sent (master mode)/matched (slave mode) */
+#define I2C_SR1_BTF 0x00000004U /*!<Byte Transfer Finished */
+#define I2C_SR1_ADD10 0x00000008U /*!<10-bit header sent (Master mode) */
+#define I2C_SR1_STOPF 0x00000010U /*!<Stop detection (Slave mode) */
+#define I2C_SR1_RXNE 0x00000040U /*!<Data Register not Empty (receivers) */
+#define I2C_SR1_TXE 0x00000080U /*!<Data Register Empty (transmitters) */
+#define I2C_SR1_BERR 0x00000100U /*!<Bus Error */
+#define I2C_SR1_ARLO 0x00000200U /*!<Arbitration Lost (master mode) */
+#define I2C_SR1_AF 0x00000400U /*!<Acknowledge Failure */
+#define I2C_SR1_OVR 0x00000800U /*!<Overrun/Underrun */
+#define I2C_SR1_PECERR 0x00001000U /*!<PEC Error in reception */
+#define I2C_SR1_TIMEOUT 0x00004000U /*!<Timeout or Tlow Error */
+#define I2C_SR1_SMBALERT 0x00008000U /*!<SMBus Alert */
+
+/******************* Bit definition for I2C_SR2 register ********************/
+#define I2C_SR2_MSL 0x00000001U /*!<Master/Slave */
+#define I2C_SR2_BUSY 0x00000002U /*!<Bus Busy */
+#define I2C_SR2_TRA 0x00000004U /*!<Transmitter/Receiver */
+#define I2C_SR2_GENCALL 0x00000010U /*!<General Call Address (Slave mode) */
+#define I2C_SR2_SMBDEFAULT 0x00000020U /*!<SMBus Device Default Address (Slave mode) */
+#define I2C_SR2_SMBHOST 0x00000040U /*!<SMBus Host Header (Slave mode) */
+#define I2C_SR2_DUALF 0x00000080U /*!<Dual Flag (Slave mode) */
+#define I2C_SR2_PEC 0x0000FF00U /*!<Packet Error Checking Register */
+
+/******************* Bit definition for I2C_CCR register ********************/
+#define I2C_CCR_CCR 0x00000FFFU /*!<Clock Control Register in Fast/Standard mode (Master mode) */
+#define I2C_CCR_DUTY 0x00004000U /*!<Fast Mode Duty Cycle */
+#define I2C_CCR_FS 0x00008000U /*!<I2C Master Mode Selection */
+
+/****************** Bit definition for I2C_TRISE register *******************/
+#define I2C_TRISE_TRISE 0x0000003FU /*!<Maximum Rise Time in Fast/Standard mode (Master mode) */
+
+/****************** Bit definition for I2C_FLTR register *******************/
+#define I2C_FLTR_DNF 0x0000000FU /*!<Digital Noise Filter */
+#define I2C_FLTR_ANOFF 0x00000010U /*!<Analog Noise Filter OFF */
+
+/******************************************************************************/
+/* */
+/* Fast Mode Plus Inter-integrated Circuit Interface (I2C) */
+/* */
+/******************************************************************************/
+/******************* Bit definition for I2C_CR1 register *******************/
+#define FMPI2C_CR1_PE 0x00000001U /*!< Peripheral enable */
+#define FMPI2C_CR1_TXIE 0x00000002U /*!< TX interrupt enable */
+#define FMPI2C_CR1_RXIE 0x00000004U /*!< RX interrupt enable */
+#define FMPI2C_CR1_ADDRIE 0x00000008U /*!< Address match interrupt enable */
+#define FMPI2C_CR1_NACKIE 0x00000010U /*!< NACK received interrupt enable */
+#define FMPI2C_CR1_STOPIE 0x00000020U /*!< STOP detection interrupt enable */
+#define FMPI2C_CR1_TCIE 0x00000040U /*!< Transfer complete interrupt enable */
+#define FMPI2C_CR1_ERRIE 0x00000080U /*!< Errors interrupt enable */
+#define FMPI2C_CR1_DFN 0x00000F00U /*!< Digital noise filter */
+#define FMPI2C_CR1_ANFOFF 0x00001000U /*!< Analog noise filter OFF */
+#define FMPI2C_CR1_TXDMAEN 0x00004000U /*!< DMA transmission requests enable */
+#define FMPI2C_CR1_RXDMAEN 0x00008000U /*!< DMA reception requests enable */
+#define FMPI2C_CR1_SBC 0x00010000U /*!< Slave byte control */
+#define FMPI2C_CR1_NOSTRETCH 0x00020000U /*!< Clock stretching disable */
+#define FMPI2C_CR1_GCEN 0x00080000U /*!< General call enable */
+#define FMPI2C_CR1_SMBHEN 0x00100000U /*!< SMBus host address enable */
+#define FMPI2C_CR1_SMBDEN 0x00200000U /*!< SMBus device default address enable */
+#define FMPI2C_CR1_ALERTEN 0x00400000U /*!< SMBus alert enable */
+#define FMPI2C_CR1_PECEN 0x00800000U /*!< PEC enable */
+
+/****************** Bit definition for I2C_CR2 register ********************/
+#define FMPI2C_CR2_SADD 0x000003FFU /*!< Slave address (master mode) */
+#define FMPI2C_CR2_RD_WRN 0x00000400U /*!< Transfer direction (master mode) */
+#define FMPI2C_CR2_ADD10 0x00000800U /*!< 10-bit addressing mode (master mode) */
+#define FMPI2C_CR2_HEAD10R 0x00001000U /*!< 10-bit address header only read direction (master mode) */
+#define FMPI2C_CR2_START 0x00002000U /*!< START generation */
+#define FMPI2C_CR2_STOP 0x00004000U /*!< STOP generation (master mode) */
+#define FMPI2C_CR2_NACK 0x00008000U /*!< NACK generation (slave mode) */
+#define FMPI2C_CR2_NBYTES 0x00FF0000U /*!< Number of bytes */
+#define FMPI2C_CR2_RELOAD 0x01000000U /*!< NBYTES reload mode */
+#define FMPI2C_CR2_AUTOEND 0x02000000U /*!< Automatic end mode (master mode) */
+#define FMPI2C_CR2_PECBYTE 0x04000000U /*!< Packet error checking byte */
+
+/******************* Bit definition for I2C_OAR1 register ******************/
+#define FMPI2C_OAR1_OA1 0x000003FFU /*!< Interface own address 1 */
+#define FMPI2C_OAR1_OA1MODE 0x00000400U /*!< Own address 1 10-bit mode */
+#define FMPI2C_OAR1_OA1EN 0x00008000U /*!< Own address 1 enable */
+
+/******************* Bit definition for I2C_OAR2 register ******************/
+#define FMPI2C_OAR2_OA2 0x000000FEU /*!< Interface own address 2 */
+#define FMPI2C_OAR2_OA2MSK 0x00000700U /*!< Own address 2 masks */
+#define FMPI2C_OAR2_OA2EN 0x00008000U /*!< Own address 2 enable */
+
+/******************* Bit definition for I2C_TIMINGR register *******************/
+#define FMPI2C_TIMINGR_SCLL 0x000000FFU /*!< SCL low period (master mode) */
+#define FMPI2C_TIMINGR_SCLH 0x0000FF00U /*!< SCL high period (master mode) */
+#define FMPI2C_TIMINGR_SDADEL 0x000F0000U /*!< Data hold time */
+#define FMPI2C_TIMINGR_SCLDEL 0x00F00000U /*!< Data setup time */
+#define FMPI2C_TIMINGR_PRESC 0xF0000000U /*!< Timings prescaler */
+
+/******************* Bit definition for I2C_TIMEOUTR register *******************/
+#define FMPI2C_TIMEOUTR_TIMEOUTA 0x00000FFFU /*!< Bus timeout A */
+#define FMPI2C_TIMEOUTR_TIDLE 0x00001000U /*!< Idle clock timeout detection */
+#define FMPI2C_TIMEOUTR_TIMOUTEN 0x00008000U /*!< Clock timeout enable */
+#define FMPI2C_TIMEOUTR_TIMEOUTB 0x0FFF0000U /*!< Bus timeout B */
+#define FMPI2C_TIMEOUTR_TEXTEN 0x80000000U /*!< Extended clock timeout enable */
+
+/****************** Bit definition for I2C_ISR register *********************/
+#define FMPI2C_ISR_TXE 0x00000001U /*!< Transmit data register empty */
+#define FMPI2C_ISR_TXIS 0x00000002U /*!< Transmit interrupt status */
+#define FMPI2C_ISR_RXNE 0x00000004U /*!< Receive data register not empty */
+#define FMPI2C_ISR_ADDR 0x00000008U /*!< Address matched (slave mode) */
+#define FMPI2C_ISR_NACKF 0x00000010U /*!< NACK received flag */
+#define FMPI2C_ISR_STOPF 0x00000020U /*!< STOP detection flag */
+#define FMPI2C_ISR_TC 0x00000040U /*!< Transfer complete (master mode) */
+#define FMPI2C_ISR_TCR 0x00000080U /*!< Transfer complete reload */
+#define FMPI2C_ISR_BERR 0x00000100U /*!< Bus error */
+#define FMPI2C_ISR_ARLO 0x00000200U /*!< Arbitration lost */
+#define FMPI2C_ISR_OVR 0x00000400U /*!< Overrun/Underrun */
+#define FMPI2C_ISR_PECERR 0x00000800U /*!< PEC error in reception */
+#define FMPI2C_ISR_TIMEOUT 0x00001000U /*!< Timeout or Tlow detection flag */
+#define FMPI2C_ISR_ALERT 0x00002000U /*!< SMBus alert */
+#define FMPI2C_ISR_BUSY 0x00008000U /*!< Bus busy */
+#define FMPI2C_ISR_DIR 0x00010000U /*!< Transfer direction (slave mode) */
+#define FMPI2C_ISR_ADDCODE 0x00FE0000U /*!< Address match code (slave mode) */
+
+/****************** Bit definition for I2C_ICR register *********************/
+#define FMPI2C_ICR_ADDRCF 0x00000008U /*!< Address matched clear flag */
+#define FMPI2C_ICR_NACKCF 0x00000010U /*!< NACK clear flag */
+#define FMPI2C_ICR_STOPCF 0x00000020U /*!< STOP detection clear flag */
+#define FMPI2C_ICR_BERRCF 0x00000100U /*!< Bus error clear flag */
+#define FMPI2C_ICR_ARLOCF 0x00000200U /*!< Arbitration lost clear flag */
+#define FMPI2C_ICR_OVRCF 0x00000400U /*!< Overrun/Underrun clear flag */
+#define FMPI2C_ICR_PECCF 0x00000800U /*!< PAC error clear flag */
+#define FMPI2C_ICR_TIMOUTCF 0x00001000U /*!< Timeout clear flag */
+#define FMPI2C_ICR_ALERTCF 0x00002000U /*!< Alert clear flag */
+
+/****************** Bit definition for I2C_PECR register *********************/
+#define FMPI2C_PECR_PEC 0x000000FFU /*!< PEC register */
+
+/****************** Bit definition for I2C_RXDR register *********************/
+#define FMPI2C_RXDR_RXDATA 0x000000FFU /*!< 8-bit receive data */
+
+/****************** Bit definition for I2C_TXDR register *********************/
+#define FMPI2C_TXDR_TXDATA 0x000000FFU /*!< 8-bit transmit data */
+
+/******************************************************************************/
+/* */
+/* Independent WATCHDOG */
+/* */
+/******************************************************************************/
+/******************* Bit definition for IWDG_KR register ********************/
+#define IWDG_KR_KEY 0xFFFFU /*!<Key value (write only, read 0000h) */
+
+/******************* Bit definition for IWDG_PR register ********************/
+#define IWDG_PR_PR 0x07U /*!<PR[2:0] (Prescaler divider) */
+#define IWDG_PR_PR_0 0x01U /*!<Bit 0 */
+#define IWDG_PR_PR_1 0x02U /*!<Bit 1 */
+#define IWDG_PR_PR_2 0x04U /*!<Bit 2 */
+
+/******************* Bit definition for IWDG_RLR register *******************/
+#define IWDG_RLR_RL 0x0FFFU /*!<Watchdog counter reload value */
+
+/******************* Bit definition for IWDG_SR register ********************/
+#define IWDG_SR_PVU 0x01U /*!<Watchdog prescaler value update */
+#define IWDG_SR_RVU 0x02U /*!<Watchdog counter reload value update */
+
+
+/******************************************************************************/
+/* */
+/* Power Control */
+/* */
+/******************************************************************************/
+/******************** Bit definition for PWR_CR register ********************/
+#define PWR_CR_LPDS 0x00000001U /*!< Low-Power Deepsleep */
+#define PWR_CR_PDDS 0x00000002U /*!< Power Down Deepsleep */
+#define PWR_CR_CWUF 0x00000004U /*!< Clear Wakeup Flag */
+#define PWR_CR_CSBF 0x00000008U /*!< Clear Standby Flag */
+#define PWR_CR_PVDE 0x00000010U /*!< Power Voltage Detector Enable */
+
+#define PWR_CR_PLS 0x000000E0U /*!< PLS[2:0] bits (PVD Level Selection) */
+#define PWR_CR_PLS_0 0x00000020U /*!< Bit 0 */
+#define PWR_CR_PLS_1 0x00000040U /*!< Bit 1 */
+#define PWR_CR_PLS_2 0x00000080U /*!< Bit 2 */
+
+/*!< PVD level configuration */
+#define PWR_CR_PLS_LEV0 0x00000000U /*!< PVD level 0 */
+#define PWR_CR_PLS_LEV1 0x00000020U /*!< PVD level 1 */
+#define PWR_CR_PLS_LEV2 0x00000040U /*!< PVD level 2 */
+#define PWR_CR_PLS_LEV3 0x00000060U /*!< PVD level 3 */
+#define PWR_CR_PLS_LEV4 0x00000080U /*!< PVD level 4 */
+#define PWR_CR_PLS_LEV5 0x000000A0U /*!< PVD level 5 */
+#define PWR_CR_PLS_LEV6 0x000000C0U /*!< PVD level 6 */
+#define PWR_CR_PLS_LEV7 0x000000E0U /*!< PVD level 7 */
+#define PWR_CR_DBP 0x00000100U /*!< Disable Backup Domain write protection */
+#define PWR_CR_FPDS 0x00000200U /*!< Flash power down in Stop mode */
+#define PWR_CR_LPLVDS 0x00000400U /*!< Low-Power Regulator Low Voltage Scaling in Stop mode */
+#define PWR_CR_MRLVDS 0x00000800U /*!< Main regulator Low Voltage Scaling in Stop mode */
+#define PWR_CR_ADCDC1 0x00002000U /*!< Refer to AN4073 on how to use this bit */
+#define PWR_CR_VOS 0x0000C000U /*!< VOS[1:0] bits (Regulator voltage scaling output selection) */
+#define PWR_CR_VOS_0 0x00004000U /*!< Bit 0 */
+#define PWR_CR_VOS_1 0x00008000U /*!< Bit 1 */
+#define PWR_CR_ODEN 0x00010000U /*!< Over Drive enable */
+#define PWR_CR_ODSWEN 0x00020000U /*!< Over Drive switch enabled */
+#define PWR_CR_UDEN 0x000C0000U /*!< Under Drive enable in stop mode */
+#define PWR_CR_UDEN_0 0x00040000U /*!< Bit 0 */
+#define PWR_CR_UDEN_1 0x00080000U /*!< Bit 1 */
+#define PWR_CR_FMSSR 0x00100000U /*!< Flash Memory Sleep System Run */
+#define PWR_CR_FISSR 0x00200000U /*!< Flash Interface Stop while System Run */
+
+/* Legacy define */
+#define PWR_CR_PMODE PWR_CR_VOS
+#define PWR_CR_LPUDS PWR_CR_LPLVDS /*!< Low-Power Regulator in deepsleep under-drive mode */
+#define PWR_CR_MRUDS PWR_CR_MRLVDS /*!< Main regulator in deepsleep under-drive mode */
+
+/******************* Bit definition for PWR_CSR register ********************/
+#define PWR_CSR_WUF 0x00000001U /*!< Wakeup Flag */
+#define PWR_CSR_SBF 0x00000002U /*!< Standby Flag */
+#define PWR_CSR_PVDO 0x00000004U /*!< PVD Output */
+#define PWR_CSR_BRR 0x00000008U /*!< Backup regulator ready */
+#define PWR_CSR_EWUP2 0x00000080U /*!< Enable WKUP pin 2 */
+#define PWR_CSR_EWUP1 0x00000100U /*!< Enable WKUP pin 1 */
+#define PWR_CSR_BRE 0x00000200U /*!< Backup regulator enable */
+#define PWR_CSR_VOSRDY 0x00004000U /*!< Regulator voltage scaling output selection ready */
+#define PWR_CSR_ODRDY 0x00010000U /*!< Over Drive generator ready */
+#define PWR_CSR_ODSWRDY 0x00020000U /*!< Over Drive Switch ready */
+#define PWR_CSR_UDSWRDY 0x000C0000U /*!< Under Drive ready */
+
+/* Legacy define */
+#define PWR_CSR_REGRDY PWR_CSR_VOSRDY
+
+/******************************************************************************/
+/* */
+/* QUADSPI */
+/* */
+/******************************************************************************/
+/***************** Bit definition for QUADSPI_CR register *******************/
+#define QUADSPI_CR_EN 0x00000001U /*!< Enable */
+#define QUADSPI_CR_ABORT 0x00000002U /*!< Abort request */
+#define QUADSPI_CR_DMAEN 0x00000004U /*!< DMA Enable */
+#define QUADSPI_CR_TCEN 0x00000008U /*!< Timeout Counter Enable */
+#define QUADSPI_CR_SSHIFT 0x00000010U /*!< SSHIFT Sample Shift */
+#define QUADSPI_CR_DFM 0x00000040U /*!< Dual Flash Mode */
+#define QUADSPI_CR_FSEL 0x00000080U /*!< Flash Select */
+#define QUADSPI_CR_FTHRES 0x00001F00U /*!< FTHRES[3:0] FIFO Level */
+#define QUADSPI_CR_FTHRES_0 0x00000100U /*!< Bit 0 */
+#define QUADSPI_CR_FTHRES_1 0x00000200U /*!< Bit 1 */
+#define QUADSPI_CR_FTHRES_2 0x00000400U /*!< Bit 2 */
+#define QUADSPI_CR_FTHRES_3 0x00000800U /*!< Bit 3 */
+#define QUADSPI_CR_FTHRES_4 0x00001000U /*!< Bit 4 */
+#define QUADSPI_CR_TEIE 0x00010000U /*!< Transfer Error Interrupt Enable */
+#define QUADSPI_CR_TCIE 0x00020000U /*!< Transfer Complete Interrupt Enable */
+#define QUADSPI_CR_FTIE 0x00040000U /*!< FIFO Threshold Interrupt Enable */
+#define QUADSPI_CR_SMIE 0x00080000U /*!< Status Match Interrupt Enable */
+#define QUADSPI_CR_TOIE 0x00100000U /*!< TimeOut Interrupt Enable */
+#define QUADSPI_CR_APMS 0x00400000U /*!< Bit 1 */
+#define QUADSPI_CR_PMM 0x00800000U /*!< Polling Match Mode */
+#define QUADSPI_CR_PRESCALER 0xFF000000U /*!< PRESCALER[7:0] Clock prescaler */
+#define QUADSPI_CR_PRESCALER_0 0x01000000U /*!< Bit 0 */
+#define QUADSPI_CR_PRESCALER_1 0x02000000U /*!< Bit 1 */
+#define QUADSPI_CR_PRESCALER_2 0x04000000U /*!< Bit 2 */
+#define QUADSPI_CR_PRESCALER_3 0x08000000U /*!< Bit 3 */
+#define QUADSPI_CR_PRESCALER_4 0x10000000U /*!< Bit 4 */
+#define QUADSPI_CR_PRESCALER_5 0x20000000U /*!< Bit 5 */
+#define QUADSPI_CR_PRESCALER_6 0x40000000U /*!< Bit 6 */
+#define QUADSPI_CR_PRESCALER_7 0x80000000U /*!< Bit 7 */
+
+/***************** Bit definition for QUADSPI_DCR register ******************/
+#define QUADSPI_DCR_CKMODE 0x00000001U /*!< Mode 0 / Mode 3 */
+#define QUADSPI_DCR_CSHT 0x00000700U /*!< CSHT[2:0]: ChipSelect High Time */
+#define QUADSPI_DCR_CSHT_0 0x00000100U /*!< Bit 0 */
+#define QUADSPI_DCR_CSHT_1 0x00000200U /*!< Bit 1 */
+#define QUADSPI_DCR_CSHT_2 0x00000400U /*!< Bit 2 */
+#define QUADSPI_DCR_FSIZE 0x001F0000U /*!< FSIZE[4:0]: Flash Size */
+#define QUADSPI_DCR_FSIZE_0 0x00010000U /*!< Bit 0 */
+#define QUADSPI_DCR_FSIZE_1 0x00020000U /*!< Bit 1 */
+#define QUADSPI_DCR_FSIZE_2 0x00040000U /*!< Bit 2 */
+#define QUADSPI_DCR_FSIZE_3 0x00080000U /*!< Bit 3 */
+#define QUADSPI_DCR_FSIZE_4 0x00100000U /*!< Bit 4 */
+
+/****************** Bit definition for QUADSPI_SR register *******************/
+#define QUADSPI_SR_TEF 0x00000001U /*!< Transfer Error Flag */
+#define QUADSPI_SR_TCF 0x00000002U /*!< Transfer Complete Flag */
+#define QUADSPI_SR_FTF 0x00000004U /*!< FIFO Threshlod Flag */
+#define QUADSPI_SR_SMF 0x00000008U /*!< Status Match Flag */
+#define QUADSPI_SR_TOF 0x00000010U /*!< Timeout Flag */
+#define QUADSPI_SR_BUSY 0x00000020U /*!< Busy */
+#define QUADSPI_SR_FLEVEL 0x00003F00U /*!< FIFO Threshlod Flag */
+#define QUADSPI_SR_FLEVEL_0 0x00000100U /*!< Bit 0 */
+#define QUADSPI_SR_FLEVEL_1 0x00000200U /*!< Bit 1 */
+#define QUADSPI_SR_FLEVEL_2 0x00000400U /*!< Bit 2 */
+#define QUADSPI_SR_FLEVEL_3 0x00000800U /*!< Bit 3 */
+#define QUADSPI_SR_FLEVEL_4 0x00001000U /*!< Bit 4 */
+#define QUADSPI_SR_FLEVEL_5 0x00002000U /*!< Bit 5 */
+
+/****************** Bit definition for QUADSPI_FCR register ******************/
+#define QUADSPI_FCR_CTEF 0x00000001U /*!< Clear Transfer Error Flag */
+#define QUADSPI_FCR_CTCF 0x00000002U /*!< Clear Transfer Complete Flag */
+#define QUADSPI_FCR_CSMF 0x00000008U /*!< Clear Status Match Flag */
+#define QUADSPI_FCR_CTOF 0x00000010U /*!< Clear Timeout Flag */
+
+/****************** Bit definition for QUADSPI_DLR register ******************/
+#define QUADSPI_DLR_DL 0xFFFFFFFFU /*!< DL[31:0]: Data Length */
+
+/****************** Bit definition for QUADSPI_CCR register ******************/
+#define QUADSPI_CCR_INSTRUCTION 0x000000FFU /*!< INSTRUCTION[7:0]: Instruction */
+#define QUADSPI_CCR_INSTRUCTION_0 0x00000001U /*!< Bit 0 */
+#define QUADSPI_CCR_INSTRUCTION_1 0x00000002U /*!< Bit 1 */
+#define QUADSPI_CCR_INSTRUCTION_2 0x00000004U /*!< Bit 2 */
+#define QUADSPI_CCR_INSTRUCTION_3 0x00000008U /*!< Bit 3 */
+#define QUADSPI_CCR_INSTRUCTION_4 0x00000010U /*!< Bit 4 */
+#define QUADSPI_CCR_INSTRUCTION_5 0x00000020U /*!< Bit 5 */
+#define QUADSPI_CCR_INSTRUCTION_6 0x00000040U /*!< Bit 6 */
+#define QUADSPI_CCR_INSTRUCTION_7 0x00000080U /*!< Bit 7 */
+#define QUADSPI_CCR_IMODE 0x00000300U /*!< IMODE[1:0]: Instruction Mode */
+#define QUADSPI_CCR_IMODE_0 0x00000100U /*!< Bit 0 */
+#define QUADSPI_CCR_IMODE_1 0x00000200U /*!< Bit 1 */
+#define QUADSPI_CCR_ADMODE 0x00000C00U /*!< ADMODE[1:0]: Address Mode */
+#define QUADSPI_CCR_ADMODE_0 0x00000400U /*!< Bit 0 */
+#define QUADSPI_CCR_ADMODE_1 0x00000800U /*!< Bit 1 */
+#define QUADSPI_CCR_ADSIZE 0x00003000U /*!< ADSIZE[1:0]: Address Size */
+#define QUADSPI_CCR_ADSIZE_0 0x00001000U /*!< Bit 0 */
+#define QUADSPI_CCR_ADSIZE_1 0x00002000U /*!< Bit 1 */
+#define QUADSPI_CCR_ABMODE 0x0000C000U /*!< ABMODE[1:0]: Alternate Bytes Mode */
+#define QUADSPI_CCR_ABMODE_0 0x00004000U /*!< Bit 0 */
+#define QUADSPI_CCR_ABMODE_1 0x00008000U /*!< Bit 1 */
+#define QUADSPI_CCR_ABSIZE 0x00030000U /*!< ABSIZE[1:0]: Instruction Mode */
+#define QUADSPI_CCR_ABSIZE_0 0x00010000U /*!< Bit 0 */
+#define QUADSPI_CCR_ABSIZE_1 0x00020000U /*!< Bit 1 */
+#define QUADSPI_CCR_DCYC 0x007C0000U /*!< DCYC[4:0]: Dummy Cycles */
+#define QUADSPI_CCR_DCYC_0 0x00040000U /*!< Bit 0 */
+#define QUADSPI_CCR_DCYC_1 0x00080000U /*!< Bit 1 */
+#define QUADSPI_CCR_DCYC_2 0x00100000U /*!< Bit 2 */
+#define QUADSPI_CCR_DCYC_3 0x00200000U /*!< Bit 3 */
+#define QUADSPI_CCR_DCYC_4 0x00400000U /*!< Bit 4 */
+#define QUADSPI_CCR_DMODE 0x03000000U /*!< DMODE[1:0]: Data Mode */
+#define QUADSPI_CCR_DMODE_0 0x01000000U /*!< Bit 0 */
+#define QUADSPI_CCR_DMODE_1 0x02000000U /*!< Bit 1 */
+#define QUADSPI_CCR_FMODE 0x0C000000U /*!< FMODE[1:0]: Functional Mode */
+#define QUADSPI_CCR_FMODE_0 0x04000000U /*!< Bit 0 */
+#define QUADSPI_CCR_FMODE_1 0x08000000U /*!< Bit 1 */
+#define QUADSPI_CCR_SIOO 0x10000000U /*!< SIOO: Send Instruction Only Once Mode */
+#define QUADSPI_CCR_DHHC 0x40000000U /*!< DHHC: Delay Half Hclk Cycle */
+#define QUADSPI_CCR_DDRM 0x80000000U /*!< DDRM: Double Data Rate Mode */
+/****************** Bit definition for QUADSPI_AR register *******************/
+#define QUADSPI_AR_ADDRESS 0xFFFFFFFFU /*!< ADDRESS[31:0]: Address */
+
+/****************** Bit definition for QUADSPI_ABR register ******************/
+#define QUADSPI_ABR_ALTERNATE 0xFFFFFFFFU /*!< ALTERNATE[31:0]: Alternate Bytes */
+
+/****************** Bit definition for QUADSPI_DR register *******************/
+#define QUADSPI_DR_DATA 0xFFFFFFFFU /*!< DATA[31:0]: Data */
+
+/****************** Bit definition for QUADSPI_PSMKR register ****************/
+#define QUADSPI_PSMKR_MASK 0xFFFFFFFFU /*!< MASK[31:0]: Status Mask */
+
+/****************** Bit definition for QUADSPI_PSMAR register ****************/
+#define QUADSPI_PSMAR_MATCH 0xFFFFFFFFU /*!< MATCH[31:0]: Status Match */
+
+/****************** Bit definition for QUADSPI_PIR register *****************/
+#define QUADSPI_PIR_INTERVAL 0x0000FFFFU /*!< INTERVAL[15:0]: Polling Interval */
+
+/****************** Bit definition for QUADSPI_LPTR register *****************/
+#define QUADSPI_LPTR_TIMEOUT 0x0000FFFFU /*!< TIMEOUT[15:0]: Timeout period */
+
+/******************************************************************************/
+/* */
+/* Reset and Clock Control */
+/* */
+/******************************************************************************/
+/******************** Bit definition for RCC_CR register ********************/
+#define RCC_CR_HSION 0x00000001U
+#define RCC_CR_HSIRDY 0x00000002U
+
+#define RCC_CR_HSITRIM 0x000000F8U
+#define RCC_CR_HSITRIM_0 0x00000008U/*!<Bit 0 */
+#define RCC_CR_HSITRIM_1 0x00000010U/*!<Bit 1 */
+#define RCC_CR_HSITRIM_2 0x00000020U/*!<Bit 2 */
+#define RCC_CR_HSITRIM_3 0x00000040U/*!<Bit 3 */
+#define RCC_CR_HSITRIM_4 0x00000080U/*!<Bit 4 */
+
+#define RCC_CR_HSICAL 0x0000FF00U
+#define RCC_CR_HSICAL_0 0x00000100U/*!<Bit 0 */
+#define RCC_CR_HSICAL_1 0x00000200U/*!<Bit 1 */
+#define RCC_CR_HSICAL_2 0x00000400U/*!<Bit 2 */
+#define RCC_CR_HSICAL_3 0x00000800U/*!<Bit 3 */
+#define RCC_CR_HSICAL_4 0x00001000U/*!<Bit 4 */
+#define RCC_CR_HSICAL_5 0x00002000U/*!<Bit 5 */
+#define RCC_CR_HSICAL_6 0x00004000U/*!<Bit 6 */
+#define RCC_CR_HSICAL_7 0x00008000U/*!<Bit 7 */
+
+#define RCC_CR_HSEON 0x00010000U
+#define RCC_CR_HSERDY 0x00020000U
+#define RCC_CR_HSEBYP 0x00040000U
+#define RCC_CR_CSSON 0x00080000U
+#define RCC_CR_PLLON 0x01000000U
+#define RCC_CR_PLLRDY 0x02000000U
+#define RCC_CR_PLLI2SON 0x04000000U
+#define RCC_CR_PLLI2SRDY 0x08000000U
+#define RCC_CR_PLLSAION 0x10000000U
+#define RCC_CR_PLLSAIRDY 0x20000000U
+
+/******************** Bit definition for RCC_PLLCFGR register ***************/
+#define RCC_PLLCFGR_PLLM 0x0000003FU
+#define RCC_PLLCFGR_PLLM_0 0x00000001U
+#define RCC_PLLCFGR_PLLM_1 0x00000002U
+#define RCC_PLLCFGR_PLLM_2 0x00000004U
+#define RCC_PLLCFGR_PLLM_3 0x00000008U
+#define RCC_PLLCFGR_PLLM_4 0x00000010U
+#define RCC_PLLCFGR_PLLM_5 0x00000020U
+
+#define RCC_PLLCFGR_PLLN 0x00007FC0U
+#define RCC_PLLCFGR_PLLN_0 0x00000040U
+#define RCC_PLLCFGR_PLLN_1 0x00000080U
+#define RCC_PLLCFGR_PLLN_2 0x00000100U
+#define RCC_PLLCFGR_PLLN_3 0x00000200U
+#define RCC_PLLCFGR_PLLN_4 0x00000400U
+#define RCC_PLLCFGR_PLLN_5 0x00000800U
+#define RCC_PLLCFGR_PLLN_6 0x00001000U
+#define RCC_PLLCFGR_PLLN_7 0x00002000U
+#define RCC_PLLCFGR_PLLN_8 0x00004000U
+
+#define RCC_PLLCFGR_PLLP 0x00030000U
+#define RCC_PLLCFGR_PLLP_0 0x00010000U
+#define RCC_PLLCFGR_PLLP_1 0x00020000U
+
+#define RCC_PLLCFGR_PLLSRC 0x00400000U
+#define RCC_PLLCFGR_PLLSRC_HSE 0x00400000U
+#define RCC_PLLCFGR_PLLSRC_HSI 0x00000000U
+
+#define RCC_PLLCFGR_PLLQ 0x0F000000U
+#define RCC_PLLCFGR_PLLQ_0 0x01000000U
+#define RCC_PLLCFGR_PLLQ_1 0x02000000U
+#define RCC_PLLCFGR_PLLQ_2 0x04000000U
+#define RCC_PLLCFGR_PLLQ_3 0x08000000U
+
+#define RCC_PLLCFGR_PLLR 0x70000000U
+#define RCC_PLLCFGR_PLLR_0 0x10000000U
+#define RCC_PLLCFGR_PLLR_1 0x20000000U
+#define RCC_PLLCFGR_PLLR_2 0x40000000U
+
+
+/******************** Bit definition for RCC_CFGR register ******************/
+/*!< SW configuration */
+#define RCC_CFGR_SW 0x00000003U /*!< SW[1:0] bits (System clock Switch) */
+#define RCC_CFGR_SW_0 0x00000001U /*!< Bit 0 */
+#define RCC_CFGR_SW_1 0x00000002U /*!< Bit 1 */
+
+#define RCC_CFGR_SW_HSI 0x00000000U /*!< HSI selected as system clock */
+#define RCC_CFGR_SW_HSE 0x00000001U /*!< HSE selected as system clock */
+#define RCC_CFGR_SW_PLL 0x00000002U /*!< PLL/PLLP selected as system clock */
+#define RCC_CFGR_SW_PLLR 0x00000003U /*!< PLL/PLLR selected as system clock */
+
+/*!< SWS configuration */
+#define RCC_CFGR_SWS 0x0000000CU /*!< SWS[1:0] bits (System Clock Switch Status) */
+#define RCC_CFGR_SWS_0 0x00000004U /*!< Bit 0 */
+#define RCC_CFGR_SWS_1 0x00000008U /*!< Bit 1 */
+
+#define RCC_CFGR_SWS_HSI 0x00000000U /*!< HSI oscillator used as system clock */
+#define RCC_CFGR_SWS_HSE 0x00000004U /*!< HSE oscillator used as system clock */
+#define RCC_CFGR_SWS_PLL 0x00000008U /*!< PLL/PLLP used as system clock */
+#define RCC_CFGR_SWS_PLLR 0x0000000CU /*!< PLL/PLLR used as system clock */
+
+/*!< HPRE configuration */
+#define RCC_CFGR_HPRE 0x000000F0U /*!< HPRE[3:0] bits (AHB prescaler) */
+#define RCC_CFGR_HPRE_0 0x00000010U /*!< Bit 0 */
+#define RCC_CFGR_HPRE_1 0x00000020U /*!< Bit 1 */
+#define RCC_CFGR_HPRE_2 0x00000040U /*!< Bit 2 */
+#define RCC_CFGR_HPRE_3 0x00000080U /*!< Bit 3 */
+
+#define RCC_CFGR_HPRE_DIV1 0x00000000U /*!< SYSCLK not divided */
+#define RCC_CFGR_HPRE_DIV2 0x00000080U /*!< SYSCLK divided by 2 */
+#define RCC_CFGR_HPRE_DIV4 0x00000090U /*!< SYSCLK divided by 4 */
+#define RCC_CFGR_HPRE_DIV8 0x000000A0U /*!< SYSCLK divided by 8 */
+#define RCC_CFGR_HPRE_DIV16 0x000000B0U /*!< SYSCLK divided by 16 */
+#define RCC_CFGR_HPRE_DIV64 0x000000C0U /*!< SYSCLK divided by 64 */
+#define RCC_CFGR_HPRE_DIV128 0x000000D0U /*!< SYSCLK divided by 128 */
+#define RCC_CFGR_HPRE_DIV256 0x000000E0U /*!< SYSCLK divided by 256 */
+#define RCC_CFGR_HPRE_DIV512 0x000000F0U /*!< SYSCLK divided by 512 */
+
+/*!< PPRE1 configuration */
+#define RCC_CFGR_PPRE1 0x00001C00U /*!< PRE1[2:0] bits (APB1 prescaler) */
+#define RCC_CFGR_PPRE1_0 0x00000400U /*!< Bit 0 */
+#define RCC_CFGR_PPRE1_1 0x00000800U /*!< Bit 1 */
+#define RCC_CFGR_PPRE1_2 0x00001000U /*!< Bit 2 */
+
+#define RCC_CFGR_PPRE1_DIV1 0x00000000U /*!< HCLK not divided */
+#define RCC_CFGR_PPRE1_DIV2 0x00001000U /*!< HCLK divided by 2 */
+#define RCC_CFGR_PPRE1_DIV4 0x00001400U /*!< HCLK divided by 4 */
+#define RCC_CFGR_PPRE1_DIV8 0x00001800U /*!< HCLK divided by 8 */
+#define RCC_CFGR_PPRE1_DIV16 0x00001C00U /*!< HCLK divided by 16 */
+
+/*!< PPRE2 configuration */
+#define RCC_CFGR_PPRE2 0x0000E000U /*!< PRE2[2:0] bits (APB2 prescaler) */
+#define RCC_CFGR_PPRE2_0 0x00002000U /*!< Bit 0 */
+#define RCC_CFGR_PPRE2_1 0x00004000U /*!< Bit 1 */
+#define RCC_CFGR_PPRE2_2 0x00008000U /*!< Bit 2 */
+
+#define RCC_CFGR_PPRE2_DIV1 0x00000000U /*!< HCLK not divided */
+#define RCC_CFGR_PPRE2_DIV2 0x00008000U /*!< HCLK divided by 2 */
+#define RCC_CFGR_PPRE2_DIV4 0x0000A000U /*!< HCLK divided by 4 */
+#define RCC_CFGR_PPRE2_DIV8 0x0000C000U /*!< HCLK divided by 8 */
+#define RCC_CFGR_PPRE2_DIV16 0x0000E000U /*!< HCLK divided by 16 */
+
+/*!< RTCPRE configuration */
+#define RCC_CFGR_RTCPRE 0x001F0000U
+#define RCC_CFGR_RTCPRE_0 0x00010000U
+#define RCC_CFGR_RTCPRE_1 0x00020000U
+#define RCC_CFGR_RTCPRE_2 0x00040000U
+#define RCC_CFGR_RTCPRE_3 0x00080000U
+#define RCC_CFGR_RTCPRE_4 0x00100000U
+
+/*!< MCO1 configuration */
+#define RCC_CFGR_MCO1 0x00600000U
+#define RCC_CFGR_MCO1_0 0x00200000U
+#define RCC_CFGR_MCO1_1 0x00400000U
+
+#define RCC_CFGR_I2SSRC 0x00800000U
+
+#define RCC_CFGR_MCO1PRE 0x07000000U
+#define RCC_CFGR_MCO1PRE_0 0x01000000U
+#define RCC_CFGR_MCO1PRE_1 0x02000000U
+#define RCC_CFGR_MCO1PRE_2 0x04000000U
+
+#define RCC_CFGR_MCO2PRE 0x38000000U
+#define RCC_CFGR_MCO2PRE_0 0x08000000U
+#define RCC_CFGR_MCO2PRE_1 0x10000000U
+#define RCC_CFGR_MCO2PRE_2 0x20000000U
+
+#define RCC_CFGR_MCO2 0xC0000000U
+#define RCC_CFGR_MCO2_0 0x40000000U
+#define RCC_CFGR_MCO2_1 0x80000000U
+
+/******************** Bit definition for RCC_CIR register *******************/
+#define RCC_CIR_LSIRDYF 0x00000001U
+#define RCC_CIR_LSERDYF 0x00000002U
+#define RCC_CIR_HSIRDYF 0x00000004U
+#define RCC_CIR_HSERDYF 0x00000008U
+#define RCC_CIR_PLLRDYF 0x00000010U
+#define RCC_CIR_PLLI2SRDYF 0x00000020U
+#define RCC_CIR_PLLSAIRDYF 0x00000040U
+#define RCC_CIR_CSSF 0x00000080U
+#define RCC_CIR_LSIRDYIE 0x00000100U
+#define RCC_CIR_LSERDYIE 0x00000200U
+#define RCC_CIR_HSIRDYIE 0x00000400U
+#define RCC_CIR_HSERDYIE 0x00000800U
+#define RCC_CIR_PLLRDYIE 0x00001000U
+#define RCC_CIR_PLLI2SRDYIE 0x00002000U
+#define RCC_CIR_PLLSAIRDYIE 0x00004000U
+#define RCC_CIR_LSIRDYC 0x00010000U
+#define RCC_CIR_LSERDYC 0x00020000U
+#define RCC_CIR_HSIRDYC 0x00040000U
+#define RCC_CIR_HSERDYC 0x00080000U
+#define RCC_CIR_PLLRDYC 0x00100000U
+#define RCC_CIR_PLLI2SRDYC 0x00200000U
+#define RCC_CIR_PLLSAIRDYC 0x00400000U
+#define RCC_CIR_CSSC 0x00800000U
+
+/******************** Bit definition for RCC_AHB1RSTR register **************/
+#define RCC_AHB1RSTR_GPIOARST 0x00000001U
+#define RCC_AHB1RSTR_GPIOBRST 0x00000002U
+#define RCC_AHB1RSTR_GPIOCRST 0x00000004U
+#define RCC_AHB1RSTR_GPIODRST 0x00000008U
+#define RCC_AHB1RSTR_GPIOERST 0x00000010U
+#define RCC_AHB1RSTR_GPIOFRST 0x00000020U
+#define RCC_AHB1RSTR_GPIOGRST 0x00000040U
+#define RCC_AHB1RSTR_GPIOHRST 0x00000080U
+#define RCC_AHB1RSTR_CRCRST 0x00001000U
+#define RCC_AHB1RSTR_DMA1RST 0x00200000U
+#define RCC_AHB1RSTR_DMA2RST 0x00400000U
+#define RCC_AHB1RSTR_OTGHRST 0x20000000U
+
+/******************** Bit definition for RCC_AHB2RSTR register **************/
+#define RCC_AHB2RSTR_DCMIRST 0x00000001U
+#define RCC_AHB2RSTR_OTGFSRST 0x00000080U
+
+/******************** Bit definition for RCC_AHB3RSTR register **************/
+#define RCC_AHB3RSTR_FMCRST 0x00000001U
+#define RCC_AHB3RSTR_QSPIRST 0x00000002U
+
+/******************** Bit definition for RCC_APB1RSTR register **************/
+#define RCC_APB1RSTR_TIM2RST 0x00000001U
+#define RCC_APB1RSTR_TIM3RST 0x00000002U
+#define RCC_APB1RSTR_TIM4RST 0x00000004U
+#define RCC_APB1RSTR_TIM5RST 0x00000008U
+#define RCC_APB1RSTR_TIM6RST 0x00000010U
+#define RCC_APB1RSTR_TIM7RST 0x00000020U
+#define RCC_APB1RSTR_TIM12RST 0x00000040U
+#define RCC_APB1RSTR_TIM13RST 0x00000080U
+#define RCC_APB1RSTR_TIM14RST 0x00000100U
+#define RCC_APB1RSTR_WWDGRST 0x00000800U
+#define RCC_APB1RSTR_SPI2RST 0x00004000U
+#define RCC_APB1RSTR_SPI3RST 0x00008000U
+#define RCC_APB1RSTR_SPDIFRXRST 0x00010000U
+#define RCC_APB1RSTR_USART2RST 0x00020000U
+#define RCC_APB1RSTR_USART3RST 0x00040000U
+#define RCC_APB1RSTR_UART4RST 0x00080000U
+#define RCC_APB1RSTR_UART5RST 0x00100000U
+#define RCC_APB1RSTR_I2C1RST 0x00200000U
+#define RCC_APB1RSTR_I2C2RST 0x00400000U
+#define RCC_APB1RSTR_I2C3RST 0x00800000U
+#define RCC_APB1RSTR_FMPI2C1RST 0x01000000U
+#define RCC_APB1RSTR_CAN1RST 0x02000000U
+#define RCC_APB1RSTR_CAN2RST 0x04000000U
+#define RCC_APB1RSTR_CECRST 0x08000000U
+#define RCC_APB1RSTR_PWRRST 0x10000000U
+#define RCC_APB1RSTR_DACRST 0x20000000U
+
+/******************** Bit definition for RCC_APB2RSTR register **************/
+#define RCC_APB2RSTR_TIM1RST 0x00000001U
+#define RCC_APB2RSTR_TIM8RST 0x00000002U
+#define RCC_APB2RSTR_USART1RST 0x00000010U
+#define RCC_APB2RSTR_USART6RST 0x00000020U
+#define RCC_APB2RSTR_ADCRST 0x00000100U
+#define RCC_APB2RSTR_SDIORST 0x00000800U
+#define RCC_APB2RSTR_SPI1RST 0x00001000U
+#define RCC_APB2RSTR_SPI4RST 0x00002000U
+#define RCC_APB2RSTR_SYSCFGRST 0x00004000U
+#define RCC_APB2RSTR_TIM9RST 0x00010000U
+#define RCC_APB2RSTR_TIM10RST 0x00020000U
+#define RCC_APB2RSTR_TIM11RST 0x00040000U
+#define RCC_APB2RSTR_SAI1RST 0x00400000U
+#define RCC_APB2RSTR_SAI2RST 0x00800000U
+
+/* Old SPI1RST bit definition, maintained for legacy purpose */
+#define RCC_APB2RSTR_SPI1 RCC_APB2RSTR_SPI1RST
+
+/******************** Bit definition for RCC_AHB1ENR register ***************/
+#define RCC_AHB1ENR_GPIOAEN 0x00000001U
+#define RCC_AHB1ENR_GPIOBEN 0x00000002U
+#define RCC_AHB1ENR_GPIOCEN 0x00000004U
+#define RCC_AHB1ENR_GPIODEN 0x00000008U
+#define RCC_AHB1ENR_GPIOEEN 0x00000010U
+#define RCC_AHB1ENR_GPIOFEN 0x00000020U
+#define RCC_AHB1ENR_GPIOGEN 0x00000040U
+#define RCC_AHB1ENR_GPIOHEN 0x00000080U
+
+#define RCC_AHB1ENR_CRCEN 0x00001000U
+#define RCC_AHB1ENR_BKPSRAMEN 0x00040000U
+#define RCC_AHB1ENR_DMA1EN 0x00200000U
+#define RCC_AHB1ENR_DMA2EN 0x00400000U
+
+#define RCC_AHB1ENR_OTGHSEN 0x20000000U
+#define RCC_AHB1ENR_OTGHSULPIEN 0x40000000U
+
+/******************** Bit definition for RCC_AHB2ENR register ***************/
+#define RCC_AHB2ENR_DCMIEN 0x00000001U
+#define RCC_AHB2ENR_OTGFSEN 0x00000080U
+
+/******************** Bit definition for RCC_AHB3ENR register ***************/
+#define RCC_AHB3ENR_FMCEN 0x00000001U
+#define RCC_AHB3ENR_QSPIEN 0x00000002U
+
+/******************** Bit definition for RCC_APB1ENR register ***************/
+#define RCC_APB1ENR_TIM2EN 0x00000001U
+#define RCC_APB1ENR_TIM3EN 0x00000002U
+#define RCC_APB1ENR_TIM4EN 0x00000004U
+#define RCC_APB1ENR_TIM5EN 0x00000008U
+#define RCC_APB1ENR_TIM6EN 0x00000010U
+#define RCC_APB1ENR_TIM7EN 0x00000020U
+#define RCC_APB1ENR_TIM12EN 0x00000040U
+#define RCC_APB1ENR_TIM13EN 0x00000080U
+#define RCC_APB1ENR_TIM14EN 0x00000100U
+#define RCC_APB1ENR_WWDGEN 0x00000800U
+#define RCC_APB1ENR_SPI2EN 0x00004000U
+#define RCC_APB1ENR_SPI3EN 0x00008000U
+#define RCC_APB1ENR_SPDIFRXEN 0x00010000U
+#define RCC_APB1ENR_USART2EN 0x00020000U
+#define RCC_APB1ENR_USART3EN 0x00040000U
+#define RCC_APB1ENR_UART4EN 0x00080000U
+#define RCC_APB1ENR_UART5EN 0x00100000U
+#define RCC_APB1ENR_I2C1EN 0x00200000U
+#define RCC_APB1ENR_I2C2EN 0x00400000U
+#define RCC_APB1ENR_I2C3EN 0x00800000U
+#define RCC_APB1ENR_FMPI2C1EN 0x01000000U
+#define RCC_APB1ENR_CAN1EN 0x02000000U
+#define RCC_APB1ENR_CAN2EN 0x04000000U
+#define RCC_APB1ENR_CECEN 0x08000000U
+#define RCC_APB1ENR_PWREN 0x10000000U
+#define RCC_APB1ENR_DACEN 0x20000000U
+
+/******************** Bit definition for RCC_APB2ENR register ***************/
+#define RCC_APB2ENR_TIM1EN 0x00000001U
+#define RCC_APB2ENR_TIM8EN 0x00000002U
+#define RCC_APB2ENR_USART1EN 0x00000010U
+#define RCC_APB2ENR_USART6EN 0x00000020U
+#define RCC_APB2ENR_ADC1EN 0x00000100U
+#define RCC_APB2ENR_ADC2EN 0x00000200U
+#define RCC_APB2ENR_ADC3EN 0x00000400U
+#define RCC_APB2ENR_SDIOEN 0x00000800U
+#define RCC_APB2ENR_SPI1EN 0x00001000U
+#define RCC_APB2ENR_SPI4EN 0x00002000U
+#define RCC_APB2ENR_SYSCFGEN 0x00004000U
+#define RCC_APB2ENR_TIM9EN 0x00010000U
+#define RCC_APB2ENR_TIM10EN 0x00020000U
+#define RCC_APB2ENR_TIM11EN 0x00040000U
+#define RCC_APB2ENR_SAI1EN 0x00400000U
+#define RCC_APB2ENR_SAI2EN 0x00800000U
+
+/******************** Bit definition for RCC_AHB1LPENR register *************/
+#define RCC_AHB1LPENR_GPIOALPEN 0x00000001U
+#define RCC_AHB1LPENR_GPIOBLPEN 0x00000002U
+#define RCC_AHB1LPENR_GPIOCLPEN 0x00000004U
+#define RCC_AHB1LPENR_GPIODLPEN 0x00000008U
+#define RCC_AHB1LPENR_GPIOELPEN 0x00000010U
+#define RCC_AHB1LPENR_GPIOFLPEN 0x00000020U
+#define RCC_AHB1LPENR_GPIOGLPEN 0x00000040U
+#define RCC_AHB1LPENR_GPIOHLPEN 0x00000080U
+#define RCC_AHB1LPENR_GPIOILPEN 0x00000100U
+#define RCC_AHB1LPENR_GPIOJLPEN 0x00000200U
+#define RCC_AHB1LPENR_GPIOKLPEN 0x00000400U
+
+#define RCC_AHB1LPENR_CRCLPEN 0x00001000U
+#define RCC_AHB1LPENR_FLITFLPEN 0x00008000U
+#define RCC_AHB1LPENR_SRAM1LPEN 0x00010000U
+#define RCC_AHB1LPENR_SRAM2LPEN 0x00020000U
+#define RCC_AHB1LPENR_BKPSRAMLPEN 0x00040000U
+#define RCC_AHB1LPENR_DMA1LPEN 0x00200000U
+#define RCC_AHB1LPENR_DMA2LPEN 0x00400000U
+
+#define RCC_AHB1LPENR_OTGHSLPEN 0x20000000U
+#define RCC_AHB1LPENR_OTGHSULPILPEN 0x40000000U
+
+/******************** Bit definition for RCC_AHB2LPENR register *************/
+#define RCC_AHB2LPENR_DCMILPEN 0x00000001U
+#define RCC_AHB2LPENR_OTGFSLPEN 0x00000080U
+
+/******************** Bit definition for RCC_AHB3LPENR register *************/
+#define RCC_AHB3LPENR_FMCLPEN 0x00000001U
+#define RCC_AHB3LPENR_QSPILPEN 0x00000002U
+
+/******************** Bit definition for RCC_APB1LPENR register *************/
+#define RCC_APB1LPENR_TIM2LPEN 0x00000001U
+#define RCC_APB1LPENR_TIM3LPEN 0x00000002U
+#define RCC_APB1LPENR_TIM4LPEN 0x00000004U
+#define RCC_APB1LPENR_TIM5LPEN 0x00000008U
+#define RCC_APB1LPENR_TIM6LPEN 0x00000010U
+#define RCC_APB1LPENR_TIM7LPEN 0x00000020U
+#define RCC_APB1LPENR_TIM12LPEN 0x00000040U
+#define RCC_APB1LPENR_TIM13LPEN 0x00000080U
+#define RCC_APB1LPENR_TIM14LPEN 0x00000100U
+#define RCC_APB1LPENR_WWDGLPEN 0x00000800U
+#define RCC_APB1LPENR_SPI2LPEN 0x00004000U
+#define RCC_APB1LPENR_SPI3LPEN 0x00008000U
+#define RCC_APB1LPENR_SPDIFRXLPEN 0x00010000U
+#define RCC_APB1LPENR_USART2LPEN 0x00020000U
+#define RCC_APB1LPENR_USART3LPEN 0x00040000U
+#define RCC_APB1LPENR_UART4LPEN 0x00080000U
+#define RCC_APB1LPENR_UART5LPEN 0x00100000U
+#define RCC_APB1LPENR_I2C1LPEN 0x00200000U
+#define RCC_APB1LPENR_I2C2LPEN 0x00400000U
+#define RCC_APB1LPENR_I2C3LPEN 0x00800000U
+#define RCC_APB1LPENR_FMPI2C1LPEN 0x01000000U
+#define RCC_APB1LPENR_CAN1LPEN 0x02000000U
+#define RCC_APB1LPENR_CAN2LPEN 0x04000000U
+#define RCC_APB1LPENR_CECLPEN 0x08000000U
+#define RCC_APB1LPENR_PWRLPEN 0x10000000U
+#define RCC_APB1LPENR_DACLPEN 0x20000000U
+
+/******************** Bit definition for RCC_APB2LPENR register *************/
+#define RCC_APB2LPENR_TIM1LPEN 0x00000001U
+#define RCC_APB2LPENR_TIM8LPEN 0x00000002U
+#define RCC_APB2LPENR_USART1LPEN 0x00000010U
+#define RCC_APB2LPENR_USART6LPEN 0x00000020U
+#define RCC_APB2LPENR_ADC1LPEN 0x00000100U
+#define RCC_APB2LPENR_ADC2LPEN 0x00000200U
+#define RCC_APB2LPENR_ADC3LPEN 0x00000400U
+#define RCC_APB2LPENR_SDIOLPEN 0x00000800U
+#define RCC_APB2LPENR_SPI1LPEN 0x00001000U
+#define RCC_APB2LPENR_SPI4LPEN 0x00002000U
+#define RCC_APB2LPENR_SYSCFGLPEN 0x00004000U
+#define RCC_APB2LPENR_TIM9LPEN 0x00010000U
+#define RCC_APB2LPENR_TIM10LPEN 0x00020000U
+#define RCC_APB2LPENR_TIM11LPEN 0x00040000U
+#define RCC_APB2LPENR_SAI1LPEN 0x00400000U
+#define RCC_APB2LPENR_SAI2LPEN 0x00800000U
+
+/******************** Bit definition for RCC_BDCR register ******************/
+#define RCC_BDCR_LSEON 0x00000001U
+#define RCC_BDCR_LSERDY 0x00000002U
+#define RCC_BDCR_LSEBYP 0x00000004U
+#define RCC_BDCR_LSEMOD 0x00000008U
+
+#define RCC_BDCR_RTCSEL 0x00000300U
+#define RCC_BDCR_RTCSEL_0 0x00000100U
+#define RCC_BDCR_RTCSEL_1 0x00000200U
+
+#define RCC_BDCR_RTCEN 0x00008000U
+#define RCC_BDCR_BDRST 0x00010000U
+
+/******************** Bit definition for RCC_CSR register *******************/
+#define RCC_CSR_LSION 0x00000001U
+#define RCC_CSR_LSIRDY 0x00000002U
+#define RCC_CSR_RMVF 0x01000000U
+#define RCC_CSR_BORRSTF 0x02000000U
+#define RCC_CSR_PADRSTF 0x04000000U
+#define RCC_CSR_PORRSTF 0x08000000U
+#define RCC_CSR_SFTRSTF 0x10000000U
+#define RCC_CSR_WDGRSTF 0x20000000U
+#define RCC_CSR_WWDGRSTF 0x40000000U
+#define RCC_CSR_LPWRRSTF 0x80000000U
+
+/******************** Bit definition for RCC_SSCGR register *****************/
+#define RCC_SSCGR_MODPER 0x00001FFFU
+#define RCC_SSCGR_INCSTEP 0x0FFFE000U
+#define RCC_SSCGR_SPREADSEL 0x40000000U
+#define RCC_SSCGR_SSCGEN 0x80000000U
+
+/******************** Bit definition for RCC_PLLI2SCFGR register ************/
+#define RCC_PLLI2SCFGR_PLLI2SM 0x0000003FU
+#define RCC_PLLI2SCFGR_PLLI2SM_0 0x00000001U
+#define RCC_PLLI2SCFGR_PLLI2SM_1 0x00000002U
+#define RCC_PLLI2SCFGR_PLLI2SM_2 0x00000004U
+#define RCC_PLLI2SCFGR_PLLI2SM_3 0x00000008U
+#define RCC_PLLI2SCFGR_PLLI2SM_4 0x00000010U
+#define RCC_PLLI2SCFGR_PLLI2SM_5 0x00000020U
+
+#define RCC_PLLI2SCFGR_PLLI2SN 0x00007FC0U
+#define RCC_PLLI2SCFGR_PLLI2SN_0 0x00000040U
+#define RCC_PLLI2SCFGR_PLLI2SN_1 0x00000080U
+#define RCC_PLLI2SCFGR_PLLI2SN_2 0x00000100U
+#define RCC_PLLI2SCFGR_PLLI2SN_3 0x00000200U
+#define RCC_PLLI2SCFGR_PLLI2SN_4 0x00000400U
+#define RCC_PLLI2SCFGR_PLLI2SN_5 0x00000800U
+#define RCC_PLLI2SCFGR_PLLI2SN_6 0x00001000U
+#define RCC_PLLI2SCFGR_PLLI2SN_7 0x00002000U
+#define RCC_PLLI2SCFGR_PLLI2SN_8 0x00004000U
+
+#define RCC_PLLI2SCFGR_PLLI2SP 0x00030000U
+#define RCC_PLLI2SCFGR_PLLI2SP_0 0x00010000U
+#define RCC_PLLI2SCFGR_PLLI2SP_1 0x00020000U
+
+#define RCC_PLLI2SCFGR_PLLI2SQ 0x0F000000U
+#define RCC_PLLI2SCFGR_PLLI2SQ_0 0x01000000U
+#define RCC_PLLI2SCFGR_PLLI2SQ_1 0x02000000U
+#define RCC_PLLI2SCFGR_PLLI2SQ_2 0x04000000U
+#define RCC_PLLI2SCFGR_PLLI2SQ_3 0x08000000U
+
+#define RCC_PLLI2SCFGR_PLLI2SR 0x70000000U
+#define RCC_PLLI2SCFGR_PLLI2SR_0 0x10000000U
+#define RCC_PLLI2SCFGR_PLLI2SR_1 0x20000000U
+#define RCC_PLLI2SCFGR_PLLI2SR_2 0x40000000U
+
+
+/******************** Bit definition for RCC_PLLSAICFGR register ************/
+#define RCC_PLLSAICFGR_PLLSAIM 0x0000003FU
+#define RCC_PLLSAICFGR_PLLSAIM_0 0x00000001U
+#define RCC_PLLSAICFGR_PLLSAIM_1 0x00000002U
+#define RCC_PLLSAICFGR_PLLSAIM_2 0x00000004U
+#define RCC_PLLSAICFGR_PLLSAIM_3 0x00000008U
+#define RCC_PLLSAICFGR_PLLSAIM_4 0x00000010U
+#define RCC_PLLSAICFGR_PLLSAIM_5 0x00000020U
+
+#define RCC_PLLSAICFGR_PLLSAIN 0x00007FC0U
+#define RCC_PLLSAICFGR_PLLSAIN_0 0x00000040U
+#define RCC_PLLSAICFGR_PLLSAIN_1 0x00000080U
+#define RCC_PLLSAICFGR_PLLSAIN_2 0x00000100U
+#define RCC_PLLSAICFGR_PLLSAIN_3 0x00000200U
+#define RCC_PLLSAICFGR_PLLSAIN_4 0x00000400U
+#define RCC_PLLSAICFGR_PLLSAIN_5 0x00000800U
+#define RCC_PLLSAICFGR_PLLSAIN_6 0x00001000U
+#define RCC_PLLSAICFGR_PLLSAIN_7 0x00002000U
+#define RCC_PLLSAICFGR_PLLSAIN_8 0x00004000U
+
+#define RCC_PLLSAICFGR_PLLSAIP 0x00030000U
+#define RCC_PLLSAICFGR_PLLSAIP_0 0x00010000U
+#define RCC_PLLSAICFGR_PLLSAIP_1 0x00020000U
+
+#define RCC_PLLSAICFGR_PLLSAIQ 0x0F000000U
+#define RCC_PLLSAICFGR_PLLSAIQ_0 0x01000000U
+#define RCC_PLLSAICFGR_PLLSAIQ_1 0x02000000U
+#define RCC_PLLSAICFGR_PLLSAIQ_2 0x04000000U
+#define RCC_PLLSAICFGR_PLLSAIQ_3 0x08000000U
+
+/******************** Bit definition for RCC_DCKCFGR register ***************/
+#define RCC_DCKCFGR_PLLI2SDIVQ 0x0000001FU
+#define RCC_DCKCFGR_PLLSAIDIVQ 0x00001F00U
+#define RCC_DCKCFGR_SAI1SRC 0x00300000U
+#define RCC_DCKCFGR_SAI1SRC_0 0x00100000U
+#define RCC_DCKCFGR_SAI1SRC_1 0x00200000U
+#define RCC_DCKCFGR_SAI2SRC 0x00C00000U
+#define RCC_DCKCFGR_SAI2SRC_0 0x00400000U
+#define RCC_DCKCFGR_SAI2SRC_1 0x00800000U
+#define RCC_DCKCFGR_TIMPRE 0x01000000U
+#define RCC_DCKCFGR_I2S1SRC 0x06000000U
+#define RCC_DCKCFGR_I2S1SRC_0 0x02000000U
+#define RCC_DCKCFGR_I2S1SRC_1 0x04000000U
+#define RCC_DCKCFGR_I2S2SRC 0x18000000U
+#define RCC_DCKCFGR_I2S2SRC_0 0x08000000U
+#define RCC_DCKCFGR_I2S2SRC_1 0x10000000U
+
+/******************** Bit definition for RCC_CKGATENR register ***************/
+#define RCC_CKGATENR_AHB2APB1_CKEN 0x00000001U
+#define RCC_CKGATENR_AHB2APB2_CKEN 0x00000002U
+#define RCC_CKGATENR_CM4DBG_CKEN 0x00000004U
+#define RCC_CKGATENR_SPARE_CKEN 0x00000008U
+#define RCC_CKGATENR_SRAM_CKEN 0x00000010U
+#define RCC_CKGATENR_FLITF_CKEN 0x00000020U
+#define RCC_CKGATENR_RCC_CKEN 0x00000040U
+
+/******************** Bit definition for RCC_DCKCFGR2 register ***************/
+#define RCC_DCKCFGR2_FMPI2C1SEL 0x00C00000U
+#define RCC_DCKCFGR2_FMPI2C1SEL_0 0x00400000U
+#define RCC_DCKCFGR2_FMPI2C1SEL_1 0x00800000U
+#define RCC_DCKCFGR2_CECSEL 0x04000000U
+#define RCC_DCKCFGR2_CK48MSEL 0x08000000U
+#define RCC_DCKCFGR2_SDIOSEL 0x10000000U
+#define RCC_DCKCFGR2_SPDIFRXSEL 0x20000000U
+
+/******************************************************************************/
+/* */
+/* Real-Time Clock (RTC) */
+/* */
+/******************************************************************************/
+/******************** Bits definition for RTC_TR register *******************/
+#define RTC_TR_PM 0x00400000U
+#define RTC_TR_HT 0x00300000U
+#define RTC_TR_HT_0 0x00100000U
+#define RTC_TR_HT_1 0x00200000U
+#define RTC_TR_HU 0x000F0000U
+#define RTC_TR_HU_0 0x00010000U
+#define RTC_TR_HU_1 0x00020000U
+#define RTC_TR_HU_2 0x00040000U
+#define RTC_TR_HU_3 0x00080000U
+#define RTC_TR_MNT 0x00007000U
+#define RTC_TR_MNT_0 0x00001000U
+#define RTC_TR_MNT_1 0x00002000U
+#define RTC_TR_MNT_2 0x00004000U
+#define RTC_TR_MNU 0x00000F00U
+#define RTC_TR_MNU_0 0x00000100U
+#define RTC_TR_MNU_1 0x00000200U
+#define RTC_TR_MNU_2 0x00000400U
+#define RTC_TR_MNU_3 0x00000800U
+#define RTC_TR_ST 0x00000070U
+#define RTC_TR_ST_0 0x00000010U
+#define RTC_TR_ST_1 0x00000020U
+#define RTC_TR_ST_2 0x00000040U
+#define RTC_TR_SU 0x0000000FU
+#define RTC_TR_SU_0 0x00000001U
+#define RTC_TR_SU_1 0x00000002U
+#define RTC_TR_SU_2 0x00000004U
+#define RTC_TR_SU_3 0x00000008U
+
+/******************** Bits definition for RTC_DR register *******************/
+#define RTC_DR_YT 0x00F00000U
+#define RTC_DR_YT_0 0x00100000U
+#define RTC_DR_YT_1 0x00200000U
+#define RTC_DR_YT_2 0x00400000U
+#define RTC_DR_YT_3 0x00800000U
+#define RTC_DR_YU 0x000F0000U
+#define RTC_DR_YU_0 0x00010000U
+#define RTC_DR_YU_1 0x00020000U
+#define RTC_DR_YU_2 0x00040000U
+#define RTC_DR_YU_3 0x00080000U
+#define RTC_DR_WDU 0x0000E000U
+#define RTC_DR_WDU_0 0x00002000U
+#define RTC_DR_WDU_1 0x00004000U
+#define RTC_DR_WDU_2 0x00008000U
+#define RTC_DR_MT 0x00001000U
+#define RTC_DR_MU 0x00000F00U
+#define RTC_DR_MU_0 0x00000100U
+#define RTC_DR_MU_1 0x00000200U
+#define RTC_DR_MU_2 0x00000400U
+#define RTC_DR_MU_3 0x00000800U
+#define RTC_DR_DT 0x00000030U
+#define RTC_DR_DT_0 0x00000010U
+#define RTC_DR_DT_1 0x00000020U
+#define RTC_DR_DU 0x0000000FU
+#define RTC_DR_DU_0 0x00000001U
+#define RTC_DR_DU_1 0x00000002U
+#define RTC_DR_DU_2 0x00000004U
+#define RTC_DR_DU_3 0x00000008U
+
+/******************** Bits definition for RTC_CR register *******************/
+#define RTC_CR_COE 0x00800000U
+#define RTC_CR_OSEL 0x00600000U
+#define RTC_CR_OSEL_0 0x00200000U
+#define RTC_CR_OSEL_1 0x00400000U
+#define RTC_CR_POL 0x00100000U
+#define RTC_CR_COSEL 0x00080000U
+#define RTC_CR_BCK 0x00040000U
+#define RTC_CR_SUB1H 0x00020000U
+#define RTC_CR_ADD1H 0x00010000U
+#define RTC_CR_TSIE 0x00008000U
+#define RTC_CR_WUTIE 0x00004000U
+#define RTC_CR_ALRBIE 0x00002000U
+#define RTC_CR_ALRAIE 0x00001000U
+#define RTC_CR_TSE 0x00000800U
+#define RTC_CR_WUTE 0x00000400U
+#define RTC_CR_ALRBE 0x00000200U
+#define RTC_CR_ALRAE 0x00000100U
+#define RTC_CR_DCE 0x00000080U
+#define RTC_CR_FMT 0x00000040U
+#define RTC_CR_BYPSHAD 0x00000020U
+#define RTC_CR_REFCKON 0x00000010U
+#define RTC_CR_TSEDGE 0x00000008U
+#define RTC_CR_WUCKSEL 0x00000007U
+#define RTC_CR_WUCKSEL_0 0x00000001U
+#define RTC_CR_WUCKSEL_1 0x00000002U
+#define RTC_CR_WUCKSEL_2 0x00000004U
+
+/******************** Bits definition for RTC_ISR register ******************/
+#define RTC_ISR_RECALPF 0x00010000U
+#define RTC_ISR_TAMP1F 0x00002000U
+#define RTC_ISR_TAMP2F 0x00004000U
+#define RTC_ISR_TSOVF 0x00001000U
+#define RTC_ISR_TSF 0x00000800U
+#define RTC_ISR_WUTF 0x00000400U
+#define RTC_ISR_ALRBF 0x00000200U
+#define RTC_ISR_ALRAF 0x00000100U
+#define RTC_ISR_INIT 0x00000080U
+#define RTC_ISR_INITF 0x00000040U
+#define RTC_ISR_RSF 0x00000020U
+#define RTC_ISR_INITS 0x00000010U
+#define RTC_ISR_SHPF 0x00000008U
+#define RTC_ISR_WUTWF 0x00000004U
+#define RTC_ISR_ALRBWF 0x00000002U
+#define RTC_ISR_ALRAWF 0x00000001U
+
+/******************** Bits definition for RTC_PRER register *****************/
+#define RTC_PRER_PREDIV_A 0x007F0000U
+#define RTC_PRER_PREDIV_S 0x00007FFFU
+
+/******************** Bits definition for RTC_WUTR register *****************/
+#define RTC_WUTR_WUT 0x0000FFFFU
+
+/******************** Bits definition for RTC_CALIBR register ***************/
+#define RTC_CALIBR_DCS 0x00000080U
+#define RTC_CALIBR_DC 0x0000001FU
+
+/******************** Bits definition for RTC_ALRMAR register ***************/
+#define RTC_ALRMAR_MSK4 0x80000000U
+#define RTC_ALRMAR_WDSEL 0x40000000U
+#define RTC_ALRMAR_DT 0x30000000U
+#define RTC_ALRMAR_DT_0 0x10000000U
+#define RTC_ALRMAR_DT_1 0x20000000U
+#define RTC_ALRMAR_DU 0x0F000000U
+#define RTC_ALRMAR_DU_0 0x01000000U
+#define RTC_ALRMAR_DU_1 0x02000000U
+#define RTC_ALRMAR_DU_2 0x04000000U
+#define RTC_ALRMAR_DU_3 0x08000000U
+#define RTC_ALRMAR_MSK3 0x00800000U
+#define RTC_ALRMAR_PM 0x00400000U
+#define RTC_ALRMAR_HT 0x00300000U
+#define RTC_ALRMAR_HT_0 0x00100000U
+#define RTC_ALRMAR_HT_1 0x00200000U
+#define RTC_ALRMAR_HU 0x000F0000U
+#define RTC_ALRMAR_HU_0 0x00010000U
+#define RTC_ALRMAR_HU_1 0x00020000U
+#define RTC_ALRMAR_HU_2 0x00040000U
+#define RTC_ALRMAR_HU_3 0x00080000U
+#define RTC_ALRMAR_MSK2 0x00008000U
+#define RTC_ALRMAR_MNT 0x00007000U
+#define RTC_ALRMAR_MNT_0 0x00001000U
+#define RTC_ALRMAR_MNT_1 0x00002000U
+#define RTC_ALRMAR_MNT_2 0x00004000U
+#define RTC_ALRMAR_MNU 0x00000F00U
+#define RTC_ALRMAR_MNU_0 0x00000100U
+#define RTC_ALRMAR_MNU_1 0x00000200U
+#define RTC_ALRMAR_MNU_2 0x00000400U
+#define RTC_ALRMAR_MNU_3 0x00000800U
+#define RTC_ALRMAR_MSK1 0x00000080U
+#define RTC_ALRMAR_ST 0x00000070U
+#define RTC_ALRMAR_ST_0 0x00000010U
+#define RTC_ALRMAR_ST_1 0x00000020U
+#define RTC_ALRMAR_ST_2 0x00000040U
+#define RTC_ALRMAR_SU 0x0000000FU
+#define RTC_ALRMAR_SU_0 0x00000001U
+#define RTC_ALRMAR_SU_1 0x00000002U
+#define RTC_ALRMAR_SU_2 0x00000004U
+#define RTC_ALRMAR_SU_3 0x00000008U
+
+/******************** Bits definition for RTC_ALRMBR register ***************/
+#define RTC_ALRMBR_MSK4 0x80000000U
+#define RTC_ALRMBR_WDSEL 0x40000000U
+#define RTC_ALRMBR_DT 0x30000000U
+#define RTC_ALRMBR_DT_0 0x10000000U
+#define RTC_ALRMBR_DT_1 0x20000000U
+#define RTC_ALRMBR_DU 0x0F000000U
+#define RTC_ALRMBR_DU_0 0x01000000U
+#define RTC_ALRMBR_DU_1 0x02000000U
+#define RTC_ALRMBR_DU_2 0x04000000U
+#define RTC_ALRMBR_DU_3 0x08000000U
+#define RTC_ALRMBR_MSK3 0x00800000U
+#define RTC_ALRMBR_PM 0x00400000U
+#define RTC_ALRMBR_HT 0x00300000U
+#define RTC_ALRMBR_HT_0 0x00100000U
+#define RTC_ALRMBR_HT_1 0x00200000U
+#define RTC_ALRMBR_HU 0x000F0000U
+#define RTC_ALRMBR_HU_0 0x00010000U
+#define RTC_ALRMBR_HU_1 0x00020000U
+#define RTC_ALRMBR_HU_2 0x00040000U
+#define RTC_ALRMBR_HU_3 0x00080000U
+#define RTC_ALRMBR_MSK2 0x00008000U
+#define RTC_ALRMBR_MNT 0x00007000U
+#define RTC_ALRMBR_MNT_0 0x00001000U
+#define RTC_ALRMBR_MNT_1 0x00002000U
+#define RTC_ALRMBR_MNT_2 0x00004000U
+#define RTC_ALRMBR_MNU 0x00000F00U
+#define RTC_ALRMBR_MNU_0 0x00000100U
+#define RTC_ALRMBR_MNU_1 0x00000200U
+#define RTC_ALRMBR_MNU_2 0x00000400U
+#define RTC_ALRMBR_MNU_3 0x00000800U
+#define RTC_ALRMBR_MSK1 0x00000080U
+#define RTC_ALRMBR_ST 0x00000070U
+#define RTC_ALRMBR_ST_0 0x00000010U
+#define RTC_ALRMBR_ST_1 0x00000020U
+#define RTC_ALRMBR_ST_2 0x00000040U
+#define RTC_ALRMBR_SU 0x0000000FU
+#define RTC_ALRMBR_SU_0 0x00000001U
+#define RTC_ALRMBR_SU_1 0x00000002U
+#define RTC_ALRMBR_SU_2 0x00000004U
+#define RTC_ALRMBR_SU_3 0x00000008U
+
+/******************** Bits definition for RTC_WPR register ******************/
+#define RTC_WPR_KEY 0x000000FFU
+
+/******************** Bits definition for RTC_SSR register ******************/
+#define RTC_SSR_SS 0x0000FFFFU
+
+/******************** Bits definition for RTC_SHIFTR register ***************/
+#define RTC_SHIFTR_SUBFS 0x00007FFFU
+#define RTC_SHIFTR_ADD1S 0x80000000U
+
+/******************** Bits definition for RTC_TSTR register *****************/
+#define RTC_TSTR_PM 0x00400000U
+#define RTC_TSTR_HT 0x00300000U
+#define RTC_TSTR_HT_0 0x00100000U
+#define RTC_TSTR_HT_1 0x00200000U
+#define RTC_TSTR_HU 0x000F0000U
+#define RTC_TSTR_HU_0 0x00010000U
+#define RTC_TSTR_HU_1 0x00020000U
+#define RTC_TSTR_HU_2 0x00040000U
+#define RTC_TSTR_HU_3 0x00080000U
+#define RTC_TSTR_MNT 0x00007000U
+#define RTC_TSTR_MNT_0 0x00001000U
+#define RTC_TSTR_MNT_1 0x00002000U
+#define RTC_TSTR_MNT_2 0x00004000U
+#define RTC_TSTR_MNU 0x00000F00U
+#define RTC_TSTR_MNU_0 0x00000100U
+#define RTC_TSTR_MNU_1 0x00000200U
+#define RTC_TSTR_MNU_2 0x00000400U
+#define RTC_TSTR_MNU_3 0x00000800U
+#define RTC_TSTR_ST 0x00000070U
+#define RTC_TSTR_ST_0 0x00000010U
+#define RTC_TSTR_ST_1 0x00000020U
+#define RTC_TSTR_ST_2 0x00000040U
+#define RTC_TSTR_SU 0x0000000FU
+#define RTC_TSTR_SU_0 0x00000001U
+#define RTC_TSTR_SU_1 0x00000002U
+#define RTC_TSTR_SU_2 0x00000004U
+#define RTC_TSTR_SU_3 0x00000008U
+
+/******************** Bits definition for RTC_TSDR register *****************/
+#define RTC_TSDR_WDU 0x0000E000U
+#define RTC_TSDR_WDU_0 0x00002000U
+#define RTC_TSDR_WDU_1 0x00004000U
+#define RTC_TSDR_WDU_2 0x00008000U
+#define RTC_TSDR_MT 0x00001000U
+#define RTC_TSDR_MU 0x00000F00U
+#define RTC_TSDR_MU_0 0x00000100U
+#define RTC_TSDR_MU_1 0x00000200U
+#define RTC_TSDR_MU_2 0x00000400U
+#define RTC_TSDR_MU_3 0x00000800U
+#define RTC_TSDR_DT 0x00000030U
+#define RTC_TSDR_DT_0 0x00000010U
+#define RTC_TSDR_DT_1 0x00000020U
+#define RTC_TSDR_DU 0x0000000FU
+#define RTC_TSDR_DU_0 0x00000001U
+#define RTC_TSDR_DU_1 0x00000002U
+#define RTC_TSDR_DU_2 0x00000004U
+#define RTC_TSDR_DU_3 0x00000008U
+
+/******************** Bits definition for RTC_TSSSR register ****************/
+#define RTC_TSSSR_SS 0x0000FFFFU
+
+/******************** Bits definition for RTC_CAL register *****************/
+#define RTC_CALR_CALP 0x00008000U
+#define RTC_CALR_CALW8 0x00004000U
+#define RTC_CALR_CALW16 0x00002000U
+#define RTC_CALR_CALM 0x000001FFU
+#define RTC_CALR_CALM_0 0x00000001U
+#define RTC_CALR_CALM_1 0x00000002U
+#define RTC_CALR_CALM_2 0x00000004U
+#define RTC_CALR_CALM_3 0x00000008U
+#define RTC_CALR_CALM_4 0x00000010U
+#define RTC_CALR_CALM_5 0x00000020U
+#define RTC_CALR_CALM_6 0x00000040U
+#define RTC_CALR_CALM_7 0x00000080U
+#define RTC_CALR_CALM_8 0x00000100U
+
+/******************** Bits definition for RTC_TAFCR register ****************/
+#define RTC_TAFCR_ALARMOUTTYPE 0x00040000U
+#define RTC_TAFCR_TSINSEL 0x00020000U
+#define RTC_TAFCR_TAMPINSEL 0x00010000U
+#define RTC_TAFCR_TAMPPUDIS 0x00008000U
+#define RTC_TAFCR_TAMPPRCH 0x00006000U
+#define RTC_TAFCR_TAMPPRCH_0 0x00002000U
+#define RTC_TAFCR_TAMPPRCH_1 0x00004000U
+#define RTC_TAFCR_TAMPFLT 0x00001800U
+#define RTC_TAFCR_TAMPFLT_0 0x00000800U
+#define RTC_TAFCR_TAMPFLT_1 0x00001000U
+#define RTC_TAFCR_TAMPFREQ 0x00000700U
+#define RTC_TAFCR_TAMPFREQ_0 0x00000100U
+#define RTC_TAFCR_TAMPFREQ_1 0x00000200U
+#define RTC_TAFCR_TAMPFREQ_2 0x00000400U
+#define RTC_TAFCR_TAMPTS 0x00000080U
+#define RTC_TAFCR_TAMP2TRG 0x00000010U
+#define RTC_TAFCR_TAMP2E 0x00000008U
+#define RTC_TAFCR_TAMPIE 0x00000004U
+#define RTC_TAFCR_TAMP1TRG 0x00000002U
+#define RTC_TAFCR_TAMP1E 0x00000001U
+
+/******************** Bits definition for RTC_ALRMASSR register *************/
+#define RTC_ALRMASSR_MASKSS 0x0F000000U
+#define RTC_ALRMASSR_MASKSS_0 0x01000000U
+#define RTC_ALRMASSR_MASKSS_1 0x02000000U
+#define RTC_ALRMASSR_MASKSS_2 0x04000000U
+#define RTC_ALRMASSR_MASKSS_3 0x08000000U
+#define RTC_ALRMASSR_SS 0x00007FFFU
+
+/******************** Bits definition for RTC_ALRMBSSR register *************/
+#define RTC_ALRMBSSR_MASKSS 0x0F000000U
+#define RTC_ALRMBSSR_MASKSS_0 0x01000000U
+#define RTC_ALRMBSSR_MASKSS_1 0x02000000U
+#define RTC_ALRMBSSR_MASKSS_2 0x04000000U
+#define RTC_ALRMBSSR_MASKSS_3 0x08000000U
+#define RTC_ALRMBSSR_SS 0x00007FFFU
+
+/******************** Bits definition for RTC_BKP0R register ****************/
+#define RTC_BKP0R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP1R register ****************/
+#define RTC_BKP1R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP2R register ****************/
+#define RTC_BKP2R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP3R register ****************/
+#define RTC_BKP3R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP4R register ****************/
+#define RTC_BKP4R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP5R register ****************/
+#define RTC_BKP5R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP6R register ****************/
+#define RTC_BKP6R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP7R register ****************/
+#define RTC_BKP7R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP8R register ****************/
+#define RTC_BKP8R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP9R register ****************/
+#define RTC_BKP9R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP10R register ***************/
+#define RTC_BKP10R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP11R register ***************/
+#define RTC_BKP11R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP12R register ***************/
+#define RTC_BKP12R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP13R register ***************/
+#define RTC_BKP13R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP14R register ***************/
+#define RTC_BKP14R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP15R register ***************/
+#define RTC_BKP15R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP16R register ***************/
+#define RTC_BKP16R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP17R register ***************/
+#define RTC_BKP17R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP18R register ***************/
+#define RTC_BKP18R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP19R register ***************/
+#define RTC_BKP19R 0xFFFFFFFFU
+
+/******************************************************************************/
+/* */
+/* Serial Audio Interface */
+/* */
+/******************************************************************************/
+/******************** Bit definition for SAI_GCR register *******************/
+#define SAI_GCR_SYNCIN 0x00000003U /*!<SYNCIN[1:0] bits (Synchronization Inputs) */
+#define SAI_GCR_SYNCIN_0 0x00000001U /*!<Bit 0 */
+#define SAI_GCR_SYNCIN_1 0x00000002U /*!<Bit 1 */
+
+#define SAI_GCR_SYNCOUT 0x00000030U /*!<SYNCOUT[1:0] bits (Synchronization Outputs) */
+#define SAI_GCR_SYNCOUT_0 0x00000010U /*!<Bit 0 */
+#define SAI_GCR_SYNCOUT_1 0x00000020U /*!<Bit 1 */
+
+/******************* Bit definition for SAI_xCR1 register *******************/
+#define SAI_xCR1_MODE 0x00000003U /*!<MODE[1:0] bits (Audio Block Mode) */
+#define SAI_xCR1_MODE_0 0x00000001U /*!<Bit 0 */
+#define SAI_xCR1_MODE_1 0x00000002U /*!<Bit 1 */
+
+#define SAI_xCR1_PRTCFG 0x0000000CU /*!<PRTCFG[1:0] bits (Protocol Configuration) */
+#define SAI_xCR1_PRTCFG_0 0x00000004U /*!<Bit 0 */
+#define SAI_xCR1_PRTCFG_1 0x00000008U /*!<Bit 1 */
+
+#define SAI_xCR1_DS 0x000000E0U /*!<DS[1:0] bits (Data Size) */
+#define SAI_xCR1_DS_0 0x00000020U /*!<Bit 0 */
+#define SAI_xCR1_DS_1 0x00000040U /*!<Bit 1 */
+#define SAI_xCR1_DS_2 0x00000080U /*!<Bit 2 */
+
+#define SAI_xCR1_LSBFIRST 0x00000100U /*!<LSB First Configuration */
+#define SAI_xCR1_CKSTR 0x00000200U /*!<ClocK STRobing edge */
+
+#define SAI_xCR1_SYNCEN 0x00000C00U /*!<SYNCEN[1:0](SYNChronization ENable) */
+#define SAI_xCR1_SYNCEN_0 0x00000400U /*!<Bit 0 */
+#define SAI_xCR1_SYNCEN_1 0x00000800U /*!<Bit 1 */
+
+#define SAI_xCR1_MONO 0x00001000U /*!<Mono mode */
+#define SAI_xCR1_OUTDRIV 0x00002000U /*!<Output Drive */
+#define SAI_xCR1_SAIEN 0x00010000U /*!<Audio Block enable */
+#define SAI_xCR1_DMAEN 0x00020000U /*!<DMA enable */
+#define SAI_xCR1_NODIV 0x00080000U /*!<No Divider Configuration */
+
+#define SAI_xCR1_MCKDIV 0x00F00000U /*!<MCKDIV[3:0] (Master ClocK Divider) */
+#define SAI_xCR1_MCKDIV_0 0x00100000U /*!<Bit 0 */
+#define SAI_xCR1_MCKDIV_1 0x00200000U /*!<Bit 1 */
+#define SAI_xCR1_MCKDIV_2 0x00400000U /*!<Bit 2 */
+#define SAI_xCR1_MCKDIV_3 0x00800000U /*!<Bit 3 */
+
+/******************* Bit definition for SAI_xCR2 register *******************/
+#define SAI_xCR2_FTH 0x00000007U /*!<FTH[2:0](Fifo THreshold) */
+#define SAI_xCR2_FTH_0 0x00000001U /*!<Bit 0 */
+#define SAI_xCR2_FTH_1 0x00000002U /*!<Bit 1 */
+#define SAI_xCR2_FTH_2 0x00000004U /*!<Bit 2 */
+
+#define SAI_xCR2_FFLUSH 0x00000008U /*!<Fifo FLUSH */
+#define SAI_xCR2_TRIS 0x00000010U /*!<TRIState Management on data line */
+#define SAI_xCR2_MUTE 0x00000020U /*!<Mute mode */
+#define SAI_xCR2_MUTEVAL 0x00000040U /*!<Muate value */
+
+#define SAI_xCR2_MUTECNT 0x00001F80U /*!<MUTECNT[5:0] (MUTE counter) */
+#define SAI_xCR2_MUTECNT_0 0x00000080U /*!<Bit 0 */
+#define SAI_xCR2_MUTECNT_1 0x00000100U /*!<Bit 1 */
+#define SAI_xCR2_MUTECNT_2 0x00000200U /*!<Bit 2 */
+#define SAI_xCR2_MUTECNT_3 0x00000400U /*!<Bit 3 */
+#define SAI_xCR2_MUTECNT_4 0x00000800U /*!<Bit 4 */
+#define SAI_xCR2_MUTECNT_5 0x00001000U /*!<Bit 5 */
+
+#define SAI_xCR2_CPL 0x00002000U /*!< Complement Bit */
+
+#define SAI_xCR2_COMP 0x0000C000U /*!<COMP[1:0] (Companding mode) */
+#define SAI_xCR2_COMP_0 0x00004000U /*!<Bit 0 */
+#define SAI_xCR2_COMP_1 0x00008000U /*!<Bit 1 */
+
+/****************** Bit definition for SAI_xFRCR register *******************/
+#define SAI_xFRCR_FRL 0x000000FFU /*!<FRL[1:0](Frame length) */
+#define SAI_xFRCR_FRL_0 0x00000001U /*!<Bit 0 */
+#define SAI_xFRCR_FRL_1 0x00000002U /*!<Bit 1 */
+#define SAI_xFRCR_FRL_2 0x00000004U /*!<Bit 2 */
+#define SAI_xFRCR_FRL_3 0x00000008U /*!<Bit 3 */
+#define SAI_xFRCR_FRL_4 0x00000010U /*!<Bit 4 */
+#define SAI_xFRCR_FRL_5 0x00000020U /*!<Bit 5 */
+#define SAI_xFRCR_FRL_6 0x00000040U /*!<Bit 6 */
+#define SAI_xFRCR_FRL_7 0x00000080U /*!<Bit 7 */
+
+#define SAI_xFRCR_FSALL 0x00007F00U /*!<FRL[1:0] (Frame synchronization active level length) */
+#define SAI_xFRCR_FSALL_0 0x00000100U /*!<Bit 0 */
+#define SAI_xFRCR_FSALL_1 0x00000200U /*!<Bit 1 */
+#define SAI_xFRCR_FSALL_2 0x00000400U /*!<Bit 2 */
+#define SAI_xFRCR_FSALL_3 0x00000800U /*!<Bit 3 */
+#define SAI_xFRCR_FSALL_4 0x00001000U /*!<Bit 4 */
+#define SAI_xFRCR_FSALL_5 0x00002000U /*!<Bit 5 */
+#define SAI_xFRCR_FSALL_6 0x00004000U /*!<Bit 6 */
+
+#define SAI_xFRCR_FSDEF 0x00010000U /*!< Frame Synchronization Definition */
+#define SAI_xFRCR_FSPOL 0x00020000U /*!<Frame Synchronization POLarity */
+#define SAI_xFRCR_FSOFF 0x00040000U /*!<Frame Synchronization OFFset */
+/* Legacy defines */
+#define SAI_xFRCR_FSPO SAI_xFRCR_FSPOL
+
+/****************** Bit definition for SAI_xSLOTR register *******************/
+#define SAI_xSLOTR_FBOFF 0x0000001FU /*!<FRL[4:0](First Bit Offset) */
+#define SAI_xSLOTR_FBOFF_0 0x00000001U /*!<Bit 0 */
+#define SAI_xSLOTR_FBOFF_1 0x00000002U /*!<Bit 1 */
+#define SAI_xSLOTR_FBOFF_2 0x00000004U /*!<Bit 2 */
+#define SAI_xSLOTR_FBOFF_3 0x00000008U /*!<Bit 3 */
+#define SAI_xSLOTR_FBOFF_4 0x00000010U /*!<Bit 4 */
+
+#define SAI_xSLOTR_SLOTSZ 0x000000C0U /*!<SLOTSZ[1:0] (Slot size) */
+#define SAI_xSLOTR_SLOTSZ_0 0x00000040U /*!<Bit 0 */
+#define SAI_xSLOTR_SLOTSZ_1 0x00000080U /*!<Bit 1 */
+
+#define SAI_xSLOTR_NBSLOT 0x00000F00U /*!<NBSLOT[3:0] (Number of Slot in audio Frame) */
+#define SAI_xSLOTR_NBSLOT_0 0x00000100U /*!<Bit 0 */
+#define SAI_xSLOTR_NBSLOT_1 0x00000200U /*!<Bit 1 */
+#define SAI_xSLOTR_NBSLOT_2 0x00000400U /*!<Bit 2 */
+#define SAI_xSLOTR_NBSLOT_3 0x00000800U /*!<Bit 3 */
+
+#define SAI_xSLOTR_SLOTEN 0xFFFF0000U /*!<SLOTEN[15:0] (Slot Enable) */
+
+/******************* Bit definition for SAI_xIMR register *******************/
+#define SAI_xIMR_OVRUDRIE 0x00000001U /*!<Overrun underrun interrupt enable */
+#define SAI_xIMR_MUTEDETIE 0x00000002U /*!<Mute detection interrupt enable */
+#define SAI_xIMR_WCKCFGIE 0x00000004U /*!<Wrong Clock Configuration interrupt enable */
+#define SAI_xIMR_FREQIE 0x00000008U /*!<FIFO request interrupt enable */
+#define SAI_xIMR_CNRDYIE 0x00000010U /*!<Codec not ready interrupt enable */
+#define SAI_xIMR_AFSDETIE 0x00000020U /*!<Anticipated frame synchronization detection interrupt enable */
+#define SAI_xIMR_LFSDETIE 0x00000040U /*!<Late frame synchronization detection interrupt enable */
+
+/******************** Bit definition for SAI_xSR register *******************/
+#define SAI_xSR_OVRUDR 0x00000001U /*!<Overrun underrun */
+#define SAI_xSR_MUTEDET 0x00000002U /*!<Mute detection */
+#define SAI_xSR_WCKCFG 0x00000004U /*!<Wrong Clock Configuration */
+#define SAI_xSR_FREQ 0x00000008U /*!<FIFO request */
+#define SAI_xSR_CNRDY 0x00000010U /*!<Codec not ready */
+#define SAI_xSR_AFSDET 0x00000020U /*!<Anticipated frame synchronization detection */
+#define SAI_xSR_LFSDET 0x00000040U /*!<Late frame synchronization detection */
+
+#define SAI_xSR_FLVL 0x00070000U /*!<FLVL[2:0] (FIFO Level Threshold) */
+#define SAI_xSR_FLVL_0 0x00010000U /*!<Bit 0 */
+#define SAI_xSR_FLVL_1 0x00020000U /*!<Bit 1 */
+#define SAI_xSR_FLVL_2 0x00040000U /*!<Bit 2 */
+
+/****************** Bit definition for SAI_xCLRFR register ******************/
+#define SAI_xCLRFR_COVRUDR 0x00000001U /*!<Clear Overrun underrun */
+#define SAI_xCLRFR_CMUTEDET 0x00000002U /*!<Clear Mute detection */
+#define SAI_xCLRFR_CWCKCFG 0x00000004U /*!<Clear Wrong Clock Configuration */
+#define SAI_xCLRFR_CFREQ 0x00000008U /*!<Clear FIFO request */
+#define SAI_xCLRFR_CCNRDY 0x00000010U /*!<Clear Codec not ready */
+#define SAI_xCLRFR_CAFSDET 0x00000020U /*!<Clear Anticipated frame synchronization detection */
+#define SAI_xCLRFR_CLFSDET 0x00000040U /*!<Clear Late frame synchronization detection */
+
+/****************** Bit definition for SAI_xDR register ******************/
+#define SAI_xDR_DATA 0xFFFFFFFFU
+
+/******************************************************************************/
+/* */
+/* SPDIF-RX Interface */
+/* */
+/******************************************************************************/
+/******************** Bit definition for SPDIFRX_CR register *******************/
+#define SPDIFRX_CR_SPDIFEN 0x00000003U /*!<Peripheral Block Enable */
+#define SPDIFRX_CR_RXDMAEN 0x00000004U /*!<Receiver DMA Enable for data flow */
+#define SPDIFRX_CR_RXSTEO 0x00000008U /*!<Stereo Mode */
+#define SPDIFRX_CR_DRFMT 0x00000030U /*!<RX Data format */
+#define SPDIFRX_CR_PMSK 0x00000040U /*!<Mask Parity error bit */
+#define SPDIFRX_CR_VMSK 0x00000080U /*!<Mask of Validity bit */
+#define SPDIFRX_CR_CUMSK 0x00000100U /*!<Mask of channel status and user bits */
+#define SPDIFRX_CR_PTMSK 0x00000200U /*!<Mask of Preamble Type bits */
+#define SPDIFRX_CR_CBDMAEN 0x00000400U /*!<Control Buffer DMA ENable for control flow */
+#define SPDIFRX_CR_CHSEL 0x00000800U /*!<Channel Selection */
+#define SPDIFRX_CR_NBTR 0x00003000U /*!<Maximum allowed re-tries during synchronization phase */
+#define SPDIFRX_CR_WFA 0x00004000U /*!<Wait For Activity */
+#define SPDIFRX_CR_INSEL 0x00070000U /*!<SPDIFRX input selection */
+
+/******************* Bit definition for SPDIFRX_IMR register *******************/
+#define SPDIFRX_IMR_RXNEIE 0x00000001U /*!<RXNE interrupt enable */
+#define SPDIFRX_IMR_CSRNEIE 0x00000002U /*!<Control Buffer Ready Interrupt Enable */
+#define SPDIFRX_IMR_PERRIE 0x00000004U /*!<Parity error interrupt enable */
+#define SPDIFRX_IMR_OVRIE 0x00000008U /*!<Overrun error Interrupt Enable */
+#define SPDIFRX_IMR_SBLKIE 0x00000010U /*!<Synchronization Block Detected Interrupt Enable */
+#define SPDIFRX_IMR_SYNCDIE 0x00000020U /*!<Synchronization Done */
+#define SPDIFRX_IMR_IFEIE 0x00000040U /*!<Serial Interface Error Interrupt Enable */
+
+/******************* Bit definition for SPDIFRX_SR register *******************/
+#define SPDIFRX_SR_RXNE 0x00000001U /*!<Read data register not empty */
+#define SPDIFRX_SR_CSRNE 0x00000002U /*!<The Control Buffer register is not empty */
+#define SPDIFRX_SR_PERR 0x00000004U /*!<Parity error */
+#define SPDIFRX_SR_OVR 0x00000008U /*!<Overrun error */
+#define SPDIFRX_SR_SBD 0x00000010U /*!<Synchronization Block Detected */
+#define SPDIFRX_SR_SYNCD 0x00000020U /*!<Synchronization Done */
+#define SPDIFRX_SR_FERR 0x00000040U /*!<Framing error */
+#define SPDIFRX_SR_SERR 0x00000080U /*!<Synchronization error */
+#define SPDIFRX_SR_TERR 0x00000100U /*!<Time-out error */
+#define SPDIFRX_SR_WIDTH5 0x7FFF0000U /*!<Duration of 5 symbols counted with SPDIFRX_clk */
+
+/******************* Bit definition for SPDIFRX_IFCR register *******************/
+#define SPDIFRX_IFCR_PERRCF 0x00000004U /*!<Clears the Parity error flag */
+#define SPDIFRX_IFCR_OVRCF 0x00000008U /*!<Clears the Overrun error flag */
+#define SPDIFRX_IFCR_SBDCF 0x00000010U /*!<Clears the Synchronization Block Detected flag */
+#define SPDIFRX_IFCR_SYNCDCF 0x00000020U /*!<Clears the Synchronization Done flag */
+
+/******************* Bit definition for SPDIFRX_DR register (DRFMT = 0b00 case) *******************/
+#define SPDIFRX_DR0_DR 0x00FFFFFFU /*!<Data value */
+#define SPDIFRX_DR0_PE 0x01000000U /*!<Parity Error bit */
+#define SPDIFRX_DR0_V 0x02000000U /*!<Validity bit */
+#define SPDIFRX_DR0_U 0x04000000U /*!<User bit */
+#define SPDIFRX_DR0_C 0x08000000U /*!<Channel Status bit */
+#define SPDIFRX_DR0_PT 0x30000000U /*!<Preamble Type */
+
+/******************* Bit definition for SPDIFRX_DR register (DRFMT = 0b01 case) *******************/
+#define SPDIFRX_DR1_DR 0xFFFFFF00U /*!<Data value */
+#define SPDIFRX_DR1_PT 0x00000030U /*!<Preamble Type */
+#define SPDIFRX_DR1_C 0x00000008U /*!<Channel Status bit */
+#define SPDIFRX_DR1_U 0x00000004U /*!<User bit */
+#define SPDIFRX_DR1_V 0x00000002U /*!<Validity bit */
+#define SPDIFRX_DR1_PE 0x00000001U /*!<Parity Error bit */
+
+/******************* Bit definition for SPDIFRX_DR register (DRFMT = 0b10 case) *******************/
+#define SPDIFRX_DR1_DRNL1 0xFFFF0000U /*!<Data value Channel B */
+#define SPDIFRX_DR1_DRNL2 0x0000FFFFU /*!<Data value Channel A */
+
+/******************* Bit definition for SPDIFRX_CSR register *******************/
+#define SPDIFRX_CSR_USR 0x0000FFFFU /*!<User data information */
+#define SPDIFRX_CSR_CS 0x00FF0000U /*!<Channel A status information */
+#define SPDIFRX_CSR_SOB 0x01000000U /*!<Start Of Block */
+
+/******************* Bit definition for SPDIFRX_DIR register *******************/
+#define SPDIFRX_DIR_THI 0x000013FFU /*!<Threshold LOW */
+#define SPDIFRX_DIR_TLO 0x1FFF0000U /*!<Threshold HIGH */
+
+
+/******************************************************************************/
+/* */
+/* SD host Interface */
+/* */
+/******************************************************************************/
+/****************** Bit definition for SDIO_POWER register ******************/
+#define SDIO_POWER_PWRCTRL 0x03U /*!<PWRCTRL[1:0] bits (Power supply control bits) */
+#define SDIO_POWER_PWRCTRL_0 0x01U /*!<Bit 0 */
+#define SDIO_POWER_PWRCTRL_1 0x02U /*!<Bit 1 */
+
+/****************** Bit definition for SDIO_CLKCR register ******************/
+#define SDIO_CLKCR_CLKDIV 0x00FFU /*!<Clock divide factor */
+#define SDIO_CLKCR_CLKEN 0x0100U /*!<Clock enable bit */
+#define SDIO_CLKCR_PWRSAV 0x0200U /*!<Power saving configuration bit */
+#define SDIO_CLKCR_BYPASS 0x0400U /*!<Clock divider bypass enable bit */
+
+#define SDIO_CLKCR_WIDBUS 0x1800U /*!<WIDBUS[1:0] bits (Wide bus mode enable bit) */
+#define SDIO_CLKCR_WIDBUS_0 0x0800U /*!<Bit 0 */
+#define SDIO_CLKCR_WIDBUS_1 0x1000U /*!<Bit 1 */
+
+#define SDIO_CLKCR_NEGEDGE 0x2000U /*!<SDIO_CK dephasing selection bit */
+#define SDIO_CLKCR_HWFC_EN 0x4000U /*!<HW Flow Control enable */
+
+/******************* Bit definition for SDIO_ARG register *******************/
+#define SDIO_ARG_CMDARG 0xFFFFFFFFU /*!<Command argument */
+
+/******************* Bit definition for SDIO_CMD register *******************/
+#define SDIO_CMD_CMDINDEX 0x003FU /*!<Command Index */
+
+#define SDIO_CMD_WAITRESP 0x00C0U /*!<WAITRESP[1:0] bits (Wait for response bits) */
+#define SDIO_CMD_WAITRESP_0 0x0040U /*!< Bit 0 */
+#define SDIO_CMD_WAITRESP_1 0x0080U /*!< Bit 1 */
+
+#define SDIO_CMD_WAITINT 0x0100U /*!<CPSM Waits for Interrupt Request */
+#define SDIO_CMD_WAITPEND 0x0200U /*!<CPSM Waits for ends of data transfer (CmdPend internal signal) */
+#define SDIO_CMD_CPSMEN 0x0400U /*!<Command path state machine (CPSM) Enable bit */
+#define SDIO_CMD_SDIOSUSPEND 0x0800U /*!<SD I/O suspend command */
+
+/***************** Bit definition for SDIO_RESPCMD register *****************/
+#define SDIO_RESPCMD_RESPCMD 0x3FU /*!<Response command index */
+
+/****************** Bit definition for SDIO_RESP0 register ******************/
+#define SDIO_RESP0_CARDSTATUS0 0xFFFFFFFFU /*!<Card Status */
+
+/****************** Bit definition for SDIO_RESP1 register ******************/
+#define SDIO_RESP1_CARDSTATUS1 0xFFFFFFFFU /*!<Card Status */
+
+/****************** Bit definition for SDIO_RESP2 register ******************/
+#define SDIO_RESP2_CARDSTATUS2 0xFFFFFFFFU /*!<Card Status */
+
+/****************** Bit definition for SDIO_RESP3 register ******************/
+#define SDIO_RESP3_CARDSTATUS3 0xFFFFFFFFU /*!<Card Status */
+
+/****************** Bit definition for SDIO_RESP4 register ******************/
+#define SDIO_RESP4_CARDSTATUS4 0xFFFFFFFFU /*!<Card Status */
+
+/****************** Bit definition for SDIO_DTIMER register *****************/
+#define SDIO_DTIMER_DATATIME 0xFFFFFFFFU /*!<Data timeout period. */
+
+/****************** Bit definition for SDIO_DLEN register *******************/
+#define SDIO_DLEN_DATALENGTH 0x01FFFFFFU /*!<Data length value */
+
+/****************** Bit definition for SDIO_DCTRL register ******************/
+#define SDIO_DCTRL_DTEN 0x0001U /*!<Data transfer enabled bit */
+#define SDIO_DCTRL_DTDIR 0x0002U /*!<Data transfer direction selection */
+#define SDIO_DCTRL_DTMODE 0x0004U /*!<Data transfer mode selection */
+#define SDIO_DCTRL_DMAEN 0x0008U /*!<DMA enabled bit */
+
+#define SDIO_DCTRL_DBLOCKSIZE 0x00F0U /*!<DBLOCKSIZE[3:0] bits (Data block size) */
+#define SDIO_DCTRL_DBLOCKSIZE_0 0x0010U /*!<Bit 0 */
+#define SDIO_DCTRL_DBLOCKSIZE_1 0x0020U /*!<Bit 1 */
+#define SDIO_DCTRL_DBLOCKSIZE_2 0x0040U /*!<Bit 2 */
+#define SDIO_DCTRL_DBLOCKSIZE_3 0x0080U /*!<Bit 3 */
+
+#define SDIO_DCTRL_RWSTART 0x0100U /*!<Read wait start */
+#define SDIO_DCTRL_RWSTOP 0x0200U /*!<Read wait stop */
+#define SDIO_DCTRL_RWMOD 0x0400U /*!<Read wait mode */
+#define SDIO_DCTRL_SDIOEN 0x0800U /*!<SD I/O enable functions */
+
+/****************** Bit definition for SDIO_DCOUNT register *****************/
+#define SDIO_DCOUNT_DATACOUNT 0x01FFFFFFU /*!<Data count value */
+
+/****************** Bit definition for SDIO_STA register ********************/
+#define SDIO_STA_CCRCFAIL 0x00000001U /*!<Command response received (CRC check failed) */
+#define SDIO_STA_DCRCFAIL 0x00000002U /*!<Data block sent/received (CRC check failed) */
+#define SDIO_STA_CTIMEOUT 0x00000004U /*!<Command response timeout */
+#define SDIO_STA_DTIMEOUT 0x00000008U /*!<Data timeout */
+#define SDIO_STA_TXUNDERR 0x00000010U /*!<Transmit FIFO underrun error */
+#define SDIO_STA_RXOVERR 0x00000020U /*!<Received FIFO overrun error */
+#define SDIO_STA_CMDREND 0x00000040U /*!<Command response received (CRC check passed) */
+#define SDIO_STA_CMDSENT 0x00000080U /*!<Command sent (no response required) */
+#define SDIO_STA_DATAEND 0x00000100U /*!<Data end (data counter, SDIDCOUNT, is zero) */
+#define SDIO_STA_DBCKEND 0x00000400U /*!<Data block sent/received (CRC check passed) */
+#define SDIO_STA_CMDACT 0x00000800U /*!<Command transfer in progress */
+#define SDIO_STA_TXACT 0x00001000U /*!<Data transmit in progress */
+#define SDIO_STA_RXACT 0x00002000U /*!<Data receive in progress */
+#define SDIO_STA_TXFIFOHE 0x00004000U /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
+#define SDIO_STA_RXFIFOHF 0x00008000U /*!<Receive FIFO Half Full: there are at least 8 words in the FIFO */
+#define SDIO_STA_TXFIFOF 0x00010000U /*!<Transmit FIFO full */
+#define SDIO_STA_RXFIFOF 0x00020000U /*!<Receive FIFO full */
+#define SDIO_STA_TXFIFOE 0x00040000U /*!<Transmit FIFO empty */
+#define SDIO_STA_RXFIFOE 0x00080000U /*!<Receive FIFO empty */
+#define SDIO_STA_TXDAVL 0x00100000U /*!<Data available in transmit FIFO */
+#define SDIO_STA_RXDAVL 0x00200000U /*!<Data available in receive FIFO */
+#define SDIO_STA_SDIOIT 0x00400000U /*!<SDIO interrupt received */
+
+/******************* Bit definition for SDIO_ICR register *******************/
+#define SDIO_ICR_CCRCFAILC 0x00000001U /*!<CCRCFAIL flag clear bit */
+#define SDIO_ICR_DCRCFAILC 0x00000002U /*!<DCRCFAIL flag clear bit */
+#define SDIO_ICR_CTIMEOUTC 0x00000004U /*!<CTIMEOUT flag clear bit */
+#define SDIO_ICR_DTIMEOUTC 0x00000008U /*!<DTIMEOUT flag clear bit */
+#define SDIO_ICR_TXUNDERRC 0x00000010U /*!<TXUNDERR flag clear bit */
+#define SDIO_ICR_RXOVERRC 0x00000020U /*!<RXOVERR flag clear bit */
+#define SDIO_ICR_CMDRENDC 0x00000040U /*!<CMDREND flag clear bit */
+#define SDIO_ICR_CMDSENTC 0x00000080U /*!<CMDSENT flag clear bit */
+#define SDIO_ICR_DATAENDC 0x00000100U /*!<DATAEND flag clear bit */
+#define SDIO_ICR_DBCKENDC 0x00000400U /*!<DBCKEND flag clear bit */
+#define SDIO_ICR_SDIOITC 0x00400000U /*!<SDIOIT flag clear bit */
+
+/****************** Bit definition for SDIO_MASK register *******************/
+#define SDIO_MASK_CCRCFAILIE 0x00000001U /*!<Command CRC Fail Interrupt Enable */
+#define SDIO_MASK_DCRCFAILIE 0x00000002U /*!<Data CRC Fail Interrupt Enable */
+#define SDIO_MASK_CTIMEOUTIE 0x00000004U /*!<Command TimeOut Interrupt Enable */
+#define SDIO_MASK_DTIMEOUTIE 0x00000008U /*!<Data TimeOut Interrupt Enable */
+#define SDIO_MASK_TXUNDERRIE 0x00000010U /*!<Tx FIFO UnderRun Error Interrupt Enable */
+#define SDIO_MASK_RXOVERRIE 0x00000020U /*!<Rx FIFO OverRun Error Interrupt Enable */
+#define SDIO_MASK_CMDRENDIE 0x00000040U /*!<Command Response Received Interrupt Enable */
+#define SDIO_MASK_CMDSENTIE 0x00000080U /*!<Command Sent Interrupt Enable */
+#define SDIO_MASK_DATAENDIE 0x00000100U /*!<Data End Interrupt Enable */
+#define SDIO_MASK_DBCKENDIE 0x00000400U /*!<Data Block End Interrupt Enable */
+#define SDIO_MASK_CMDACTIE 0x00000800U /*!<CCommand Acting Interrupt Enable */
+#define SDIO_MASK_TXACTIE 0x00001000U /*!<Data Transmit Acting Interrupt Enable */
+#define SDIO_MASK_RXACTIE 0x00002000U /*!<Data receive acting interrupt enabled */
+#define SDIO_MASK_TXFIFOHEIE 0x00004000U /*!<Tx FIFO Half Empty interrupt Enable */
+#define SDIO_MASK_RXFIFOHFIE 0x00008000U /*!<Rx FIFO Half Full interrupt Enable */
+#define SDIO_MASK_TXFIFOFIE 0x00010000U /*!<Tx FIFO Full interrupt Enable */
+#define SDIO_MASK_RXFIFOFIE 0x00020000U /*!<Rx FIFO Full interrupt Enable */
+#define SDIO_MASK_TXFIFOEIE 0x00040000U /*!<Tx FIFO Empty interrupt Enable */
+#define SDIO_MASK_RXFIFOEIE 0x00080000U /*!<Rx FIFO Empty interrupt Enable */
+#define SDIO_MASK_TXDAVLIE 0x00100000U /*!<Data available in Tx FIFO interrupt Enable */
+#define SDIO_MASK_RXDAVLIE 0x00200000U /*!<Data available in Rx FIFO interrupt Enable */
+#define SDIO_MASK_SDIOITIE 0x00400000U /*!<SDIO Mode Interrupt Received interrupt Enable */
+
+/***************** Bit definition for SDIO_FIFOCNT register *****************/
+#define SDIO_FIFOCNT_FIFOCOUNT 0x00FFFFFFU /*!<Remaining number of words to be written to or read from the FIFO */
+
+/****************** Bit definition for SDIO_FIFO register *******************/
+#define SDIO_FIFO_FIFODATA 0xFFFFFFFFU /*!<Receive and transmit FIFO data */
+
+/******************************************************************************/
+/* */
+/* Serial Peripheral Interface */
+/* */
+/******************************************************************************/
+/******************* Bit definition for SPI_CR1 register ********************/
+#define SPI_CR1_CPHA 0x00000001U /*!<Clock Phase */
+#define SPI_CR1_CPOL 0x00000002U /*!<Clock Polarity */
+#define SPI_CR1_MSTR 0x00000004U /*!<Master Selection */
+
+#define SPI_CR1_BR 0x00000038U /*!<BR[2:0] bits (Baud Rate Control) */
+#define SPI_CR1_BR_0 0x00000008U /*!<Bit 0 */
+#define SPI_CR1_BR_1 0x00000010U /*!<Bit 1 */
+#define SPI_CR1_BR_2 0x00000020U /*!<Bit 2 */
+
+#define SPI_CR1_SPE 0x00000040U /*!<SPI Enable */
+#define SPI_CR1_LSBFIRST 0x00000080U /*!<Frame Format */
+#define SPI_CR1_SSI 0x00000100U /*!<Internal slave select */
+#define SPI_CR1_SSM 0x00000200U /*!<Software slave management */
+#define SPI_CR1_RXONLY 0x00000400U /*!<Receive only */
+#define SPI_CR1_DFF 0x00000800U /*!<Data Frame Format */
+#define SPI_CR1_CRCNEXT 0x00001000U /*!<Transmit CRC next */
+#define SPI_CR1_CRCEN 0x00002000U /*!<Hardware CRC calculation enable */
+#define SPI_CR1_BIDIOE 0x00004000U /*!<Output enable in bidirectional mode */
+#define SPI_CR1_BIDIMODE 0x00008000U /*!<Bidirectional data mode enable */
+
+/******************* Bit definition for SPI_CR2 register ********************/
+#define SPI_CR2_RXDMAEN 0x00000001U /*!<Rx Buffer DMA Enable */
+#define SPI_CR2_TXDMAEN 0x00000002U /*!<Tx Buffer DMA Enable */
+#define SPI_CR2_SSOE 0x00000004U /*!<SS Output Enable */
+#define SPI_CR2_FRF 0x00000010U /*!<Frame Format */
+#define SPI_CR2_ERRIE 0x00000020U /*!<Error Interrupt Enable */
+#define SPI_CR2_RXNEIE 0x00000040U /*!<RX buffer Not Empty Interrupt Enable */
+#define SPI_CR2_TXEIE 0x00000080U /*!<Tx buffer Empty Interrupt Enable */
+
+/******************** Bit definition for SPI_SR register ********************/
+#define SPI_SR_RXNE 0x00000001U /*!<Receive buffer Not Empty */
+#define SPI_SR_TXE 0x00000002U /*!<Transmit buffer Empty */
+#define SPI_SR_CHSIDE 0x00000004U /*!<Channel side */
+#define SPI_SR_UDR 0x00000008U /*!<Underrun flag */
+#define SPI_SR_CRCERR 0x00000010U /*!<CRC Error flag */
+#define SPI_SR_MODF 0x00000020U /*!<Mode fault */
+#define SPI_SR_OVR 0x00000040U /*!<Overrun flag */
+#define SPI_SR_BSY 0x00000080U /*!<Busy flag */
+#define SPI_SR_FRE 0x00000100U /*!<Frame format error flag */
+
+/******************** Bit definition for SPI_DR register ********************/
+#define SPI_DR_DR 0x0000FFFFU /*!<Data Register */
+
+/******************* Bit definition for SPI_CRCPR register ******************/
+#define SPI_CRCPR_CRCPOLY 0x0000FFFFU /*!<CRC polynomial register */
+
+/****************** Bit definition for SPI_RXCRCR register ******************/
+#define SPI_RXCRCR_RXCRC 0x0000FFFFU /*!<Rx CRC Register */
+
+/****************** Bit definition for SPI_TXCRCR register ******************/
+#define SPI_TXCRCR_TXCRC 0x0000FFFFU /*!<Tx CRC Register */
+
+/****************** Bit definition for SPI_I2SCFGR register *****************/
+#define SPI_I2SCFGR_CHLEN 0x00000001U /*!<Channel length (number of bits per audio channel) */
+
+#define SPI_I2SCFGR_DATLEN 0x00000006U /*!<DATLEN[1:0] bits (Data length to be transferred) */
+#define SPI_I2SCFGR_DATLEN_0 0x00000002U /*!<Bit 0 */
+#define SPI_I2SCFGR_DATLEN_1 0x00000004U /*!<Bit 1 */
+
+#define SPI_I2SCFGR_CKPOL 0x00000008U /*!<steady state clock polarity */
+
+#define SPI_I2SCFGR_I2SSTD 0x00000030U /*!<I2SSTD[1:0] bits (I2S standard selection) */
+#define SPI_I2SCFGR_I2SSTD_0 0x00000010U /*!<Bit 0 */
+#define SPI_I2SCFGR_I2SSTD_1 0x00000020U /*!<Bit 1 */
+
+#define SPI_I2SCFGR_PCMSYNC 0x00000080U /*!<PCM frame synchronization */
+
+#define SPI_I2SCFGR_I2SCFG 0x00000300U /*!<I2SCFG[1:0] bits (I2S configuration mode) */
+#define SPI_I2SCFGR_I2SCFG_0 0x00000100U /*!<Bit 0 */
+#define SPI_I2SCFGR_I2SCFG_1 0x00000200U /*!<Bit 1 */
+
+#define SPI_I2SCFGR_I2SE 0x00000400U /*!<I2S Enable */
+#define SPI_I2SCFGR_I2SMOD 0x00000800U /*!<I2S mode selection */
+#define SPI_I2SCFGR_ASTRTEN 0x00001000U /*!<Asynchronous start enable */
+
+/****************** Bit definition for SPI_I2SPR register *******************/
+#define SPI_I2SPR_I2SDIV 0x000000FFU /*!<I2S Linear prescaler */
+#define SPI_I2SPR_ODD 0x00000100U /*!<Odd factor for the prescaler */
+#define SPI_I2SPR_MCKOE 0x00000200U /*!<Master Clock Output Enable */
+
+/******************************************************************************/
+/* */
+/* SYSCFG */
+/* */
+/******************************************************************************/
+/****************** Bit definition for SYSCFG_MEMRMP register ***************/
+#define SYSCFG_MEMRMP_MEM_MODE 0x00000007U /*!< SYSCFG_Memory Remap Config */
+#define SYSCFG_MEMRMP_MEM_MODE_0 0x00000001U
+#define SYSCFG_MEMRMP_MEM_MODE_1 0x00000002U
+#define SYSCFG_MEMRMP_MEM_MODE_2 0x00000004U
+
+#define SYSCFG_MEMRMP_UFB_MODE 0x00000100U /*!< User Flash Bank mode */
+#define SYSCFG_SWP_FMC 0x00000C00U /*!< FMC memory mapping swap */
+
+/****************** Bit definition for SYSCFG_PMC register ******************/
+#define SYSCFG_PMC_ADCxDC2 0x00070000U /*!< Refer to AN4073 on how to use this bit */
+#define SYSCFG_PMC_ADC1DC2 0x00010000U /*!< Refer to AN4073 on how to use this bit */
+#define SYSCFG_PMC_ADC2DC2 0x00020000U /*!< Refer to AN4073 on how to use this bit */
+#define SYSCFG_PMC_ADC3DC2 0x00040000U /*!< Refer to AN4073 on how to use this bit */
+
+/***************** Bit definition for SYSCFG_EXTICR1 register ***************/
+#define SYSCFG_EXTICR1_EXTI0 0x000FU /*!<EXTI 0 configuration */
+#define SYSCFG_EXTICR1_EXTI1 0x00F0U /*!<EXTI 1 configuration */
+#define SYSCFG_EXTICR1_EXTI2 0x0F00U /*!<EXTI 2 configuration */
+#define SYSCFG_EXTICR1_EXTI3 0xF000U /*!<EXTI 3 configuration */
+/**
+ * @brief EXTI0 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI0_PA 0x0000U /*!<PA[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PB 0x0001U /*!<PB[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PC 0x0002U /*!<PC[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PD 0x0003U /*!<PD[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PE 0x0004U /*!<PE[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PF 0x0005U /*!<PF[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PG 0x0006U /*!<PG[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PH 0x0007U /*!<PH[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PI 0x0008U /*!<PI[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PJ 0x0009U /*!<PJ[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PK 0x000AU /*!<PK[0] pin */
+
+/**
+ * @brief EXTI1 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI1_PA 0x0000U /*!<PA[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PB 0x0010U /*!<PB[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PC 0x0020U /*!<PC[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PD 0x0030U /*!<PD[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PE 0x0040U /*!<PE[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PF 0x0050U /*!<PF[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PG 0x0060U /*!<PG[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PH 0x0070U /*!<PH[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PI 0x0080U /*!<PI[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PJ 0x0090U /*!<PJ[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PK 0x00A0U /*!<PK[1] pin */
+
+
+/**
+ * @brief EXTI2 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI2_PA 0x0000U /*!<PA[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PB 0x0100U /*!<PB[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PC 0x0200U /*!<PC[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PD 0x0300U /*!<PD[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PE 0x0400U /*!<PE[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PF 0x0500U /*!<PF[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PG 0x0600U /*!<PG[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PH 0x0700U /*!<PH[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PI 0x0800U /*!<PI[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PJ 0x0900U /*!<PJ[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PK 0x0A00U /*!<PK[2] pin */
+
+
+/**
+ * @brief EXTI3 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI3_PA 0x0000U /*!<PA[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PB 0x1000U /*!<PB[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PC 0x2000U /*!<PC[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PD 0x3000U /*!<PD[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PE 0x4000U /*!<PE[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PF 0x5000U /*!<PF[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PG 0x6000U /*!<PG[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PH 0x7000U /*!<PH[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PI 0x8000U /*!<PI[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PJ 0x9000U /*!<PJ[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PK 0xA000U /*!<PK[3] pin */
+
+
+/***************** Bit definition for SYSCFG_EXTICR2 register ***************/
+#define SYSCFG_EXTICR2_EXTI4 0x000FU /*!<EXTI 4 configuration */
+#define SYSCFG_EXTICR2_EXTI5 0x00F0U /*!<EXTI 5 configuration */
+#define SYSCFG_EXTICR2_EXTI6 0x0F00U /*!<EXTI 6 configuration */
+#define SYSCFG_EXTICR2_EXTI7 0xF000U /*!<EXTI 7 configuration */
+/**
+ * @brief EXTI4 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI4_PA 0x0000U /*!<PA[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PB 0x0001U /*!<PB[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PC 0x0002U /*!<PC[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PD 0x0003U /*!<PD[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PE 0x0004U /*!<PE[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PF 0x0005U /*!<PF[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PG 0x0006U /*!<PG[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PH 0x0007U /*!<PH[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PI 0x0008U /*!<PI[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PJ 0x0009U /*!<PJ[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PK 0x000AU /*!<PK[4] pin */
+
+/**
+ * @brief EXTI5 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI5_PA 0x0000U /*!<PA[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PB 0x0010U /*!<PB[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PC 0x0020U /*!<PC[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PD 0x0030U /*!<PD[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PE 0x0040U /*!<PE[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PF 0x0050U /*!<PF[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PG 0x0060U /*!<PG[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PH 0x0070U /*!<PH[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PI 0x0080U /*!<PI[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PJ 0x0090U /*!<PJ[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PK 0x00A0U /*!<PK[5] pin */
+
+/**
+ * @brief EXTI6 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI6_PA 0x0000U /*!<PA[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PB 0x0100U /*!<PB[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PC 0x0200U /*!<PC[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PD 0x0300U /*!<PD[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PE 0x0400U /*!<PE[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PF 0x0500U /*!<PF[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PG 0x0600U /*!<PG[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PH 0x0700U /*!<PH[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PI 0x0800U /*!<PI[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PJ 0x0900U /*!<PJ[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PK 0x0A00U /*!<PK[6] pin */
+
+
+/**
+ * @brief EXTI7 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI7_PA 0x0000U /*!<PA[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PB 0x1000U /*!<PB[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PC 0x2000U /*!<PC[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PD 0x3000U /*!<PD[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PE 0x4000U /*!<PE[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PF 0x5000U /*!<PF[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PG 0x6000U /*!<PG[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PH 0x7000U /*!<PH[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PI 0x8000U /*!<PI[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PJ 0x9000U /*!<PJ[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PK 0xA000U /*!<PK[7] pin */
+
+/***************** Bit definition for SYSCFG_EXTICR3 register ***************/
+#define SYSCFG_EXTICR3_EXTI8 0x000FU /*!<EXTI 8 configuration */
+#define SYSCFG_EXTICR3_EXTI9 0x00F0U /*!<EXTI 9 configuration */
+#define SYSCFG_EXTICR3_EXTI10 0x0F00U /*!<EXTI 10 configuration */
+#define SYSCFG_EXTICR3_EXTI11 0xF000U /*!<EXTI 11 configuration */
+
+/**
+ * @brief EXTI8 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI8_PA 0x0000U /*!<PA[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PB 0x0001U /*!<PB[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PC 0x0002U /*!<PC[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PD 0x0003U /*!<PD[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PE 0x0004U /*!<PE[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PF 0x0005U /*!<PF[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PG 0x0006U /*!<PG[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PH 0x0007U /*!<PH[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PI 0x0008U /*!<PI[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PJ 0x0009U /*!<PJ[8] pin */
+
+/**
+ * @brief EXTI9 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI9_PA 0x0000U /*!<PA[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PB 0x0010U /*!<PB[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PC 0x0020U /*!<PC[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PD 0x0030U /*!<PD[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PE 0x0040U /*!<PE[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PF 0x0050U /*!<PF[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PG 0x0060U /*!<PG[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PH 0x0070U /*!<PH[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PI 0x0080U /*!<PI[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PJ 0x0090U /*!<PJ[9] pin */
+
+
+/**
+ * @brief EXTI10 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI10_PA 0x0000U /*!<PA[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PB 0x0100U /*!<PB[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PC 0x0200U /*!<PC[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PD 0x0300U /*!<PD[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PE 0x0400U /*!<PE[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PF 0x0500U /*!<PF[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PG 0x0600U /*!<PG[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PH 0x0700U /*!<PH[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PI 0x0800U /*!<PI[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PJ 0x0900U /*!<PJ[10] pin */
+
+
+/**
+ * @brief EXTI11 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI11_PA 0x0000U /*!<PA[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PB 0x1000U /*!<PB[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PC 0x2000U /*!<PC[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PD 0x3000U /*!<PD[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PE 0x4000U /*!<PE[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PF 0x5000U /*!<PF[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PG 0x6000U /*!<PG[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PH 0x7000U /*!<PH[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PI 0x8000U /*!<PI[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PJ 0x9000U /*!<PJ[11] pin */
+
+
+/***************** Bit definition for SYSCFG_EXTICR4 register ***************/
+#define SYSCFG_EXTICR4_EXTI12 0x000FU /*!<EXTI 12 configuration */
+#define SYSCFG_EXTICR4_EXTI13 0x00F0U /*!<EXTI 13 configuration */
+#define SYSCFG_EXTICR4_EXTI14 0x0F00U /*!<EXTI 14 configuration */
+#define SYSCFG_EXTICR4_EXTI15 0xF000U /*!<EXTI 15 configuration */
+/**
+ * @brief EXTI12 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI12_PA 0x0000U /*!<PA[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PB 0x0001U /*!<PB[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PC 0x0002U /*!<PC[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PD 0x0003U /*!<PD[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PE 0x0004U /*!<PE[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PF 0x0005U /*!<PF[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PG 0x0006U /*!<PG[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PH 0x0007U /*!<PH[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PI 0x0008U /*!<PI[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PJ 0x0009U /*!<PJ[12] pin */
+
+
+/**
+ * @brief EXTI13 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI13_PA 0x0000U /*!<PA[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PB 0x0010U /*!<PB[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PC 0x0020U /*!<PC[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PD 0x0030U /*!<PD[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PE 0x0040U /*!<PE[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PF 0x0050U /*!<PF[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PG 0x0060U /*!<PG[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PH 0x0070U /*!<PH[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PI 0x0008U /*!<PI[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PJ 0x0009U /*!<PJ[13] pin */
+
+
+/**
+ * @brief EXTI14 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI14_PA 0x0000U /*!<PA[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PB 0x0100U /*!<PB[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PC 0x0200U /*!<PC[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PD 0x0300U /*!<PD[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PE 0x0400U /*!<PE[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PF 0x0500U /*!<PF[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PG 0x0600U /*!<PG[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PH 0x0700U /*!<PH[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PI 0x0800U /*!<PI[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PJ 0x0900U /*!<PJ[14] pin */
+
+
+/**
+ * @brief EXTI15 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI15_PA 0x0000U /*!<PA[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PB 0x1000U /*!<PB[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PC 0x2000U /*!<PC[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PD 0x3000U /*!<PD[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PE 0x4000U /*!<PE[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PF 0x5000U /*!<PF[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PG 0x6000U /*!<PG[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PH 0x7000U /*!<PH[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PI 0x8000U /*!<PI[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PJ 0x9000U /*!<PJ[15] pin */
+
+/****************** Bit definition for SYSCFG_CMPCR register ****************/
+#define SYSCFG_CMPCR_CMP_PD 0x00000001U /*!<Compensation cell ready flag */
+#define SYSCFG_CMPCR_READY 0x00000100U /*!<Compensation cell power-down */
+
+/****************** Bit definition for SYSCFG_CFGR register ****************/
+#define SYSCFG_CFGR_FMPI2C1_SCL 0x00000001U /*!<FM+ drive capability for FMPI2C1_SCL pin */
+#define SYSCFG_CFGR_FMPI2C1_SDA 0x00000002U /*!<FM+ drive capability for FMPI2C1_SDA pin */
+
+/******************************************************************************/
+/* */
+/* TIM */
+/* */
+/******************************************************************************/
+/******************* Bit definition for TIM_CR1 register ********************/
+#define TIM_CR1_CEN 0x0001U /*!<Counter enable */
+#define TIM_CR1_UDIS 0x0002U /*!<Update disable */
+#define TIM_CR1_URS 0x0004U /*!<Update request source */
+#define TIM_CR1_OPM 0x0008U /*!<One pulse mode */
+#define TIM_CR1_DIR 0x0010U /*!<Direction */
+
+#define TIM_CR1_CMS 0x0060U /*!<CMS[1:0] bits (Center-aligned mode selection) */
+#define TIM_CR1_CMS_0 0x0020U /*!<Bit 0 */
+#define TIM_CR1_CMS_1 0x0040U /*!<Bit 1 */
+
+#define TIM_CR1_ARPE 0x0080U /*!<Auto-reload preload enable */
+
+#define TIM_CR1_CKD 0x0300U /*!<CKD[1:0] bits (clock division) */
+#define TIM_CR1_CKD_0 0x0100U /*!<Bit 0 */
+#define TIM_CR1_CKD_1 0x0200U /*!<Bit 1 */
+
+/******************* Bit definition for TIM_CR2 register ********************/
+#define TIM_CR2_CCPC 0x0001U /*!<Capture/Compare Preloaded Control */
+#define TIM_CR2_CCUS 0x0004U /*!<Capture/Compare Control Update Selection */
+#define TIM_CR2_CCDS 0x0008U /*!<Capture/Compare DMA Selection */
+
+#define TIM_CR2_MMS 0x0070U /*!<MMS[2:0] bits (Master Mode Selection) */
+#define TIM_CR2_MMS_0 0x0010U /*!<Bit 0 */
+#define TIM_CR2_MMS_1 0x0020U /*!<Bit 1 */
+#define TIM_CR2_MMS_2 0x0040U /*!<Bit 2 */
+
+#define TIM_CR2_TI1S 0x0080U /*!<TI1 Selection */
+#define TIM_CR2_OIS1 0x0100U /*!<Output Idle state 1 (OC1 output) */
+#define TIM_CR2_OIS1N 0x0200U /*!<Output Idle state 1 (OC1N output) */
+#define TIM_CR2_OIS2 0x0400U /*!<Output Idle state 2 (OC2 output) */
+#define TIM_CR2_OIS2N 0x0800U /*!<Output Idle state 2 (OC2N output) */
+#define TIM_CR2_OIS3 0x1000U /*!<Output Idle state 3 (OC3 output) */
+#define TIM_CR2_OIS3N 0x2000U /*!<Output Idle state 3 (OC3N output) */
+#define TIM_CR2_OIS4 0x4000U /*!<Output Idle state 4 (OC4 output) */
+
+/******************* Bit definition for TIM_SMCR register *******************/
+#define TIM_SMCR_SMS 0x0007U /*!<SMS[2:0] bits (Slave mode selection) */
+#define TIM_SMCR_SMS_0 0x0001U /*!<Bit 0 */
+#define TIM_SMCR_SMS_1 0x0002U /*!<Bit 1 */
+#define TIM_SMCR_SMS_2 0x0004U /*!<Bit 2 */
+
+#define TIM_SMCR_TS 0x0070U /*!<TS[2:0] bits (Trigger selection) */
+#define TIM_SMCR_TS_0 0x0010U /*!<Bit 0 */
+#define TIM_SMCR_TS_1 0x0020U /*!<Bit 1 */
+#define TIM_SMCR_TS_2 0x0040U /*!<Bit 2 */
+
+#define TIM_SMCR_MSM 0x0080U /*!<Master/slave mode */
+
+#define TIM_SMCR_ETF 0x0F00U /*!<ETF[3:0] bits (External trigger filter) */
+#define TIM_SMCR_ETF_0 0x0100U /*!<Bit 0 */
+#define TIM_SMCR_ETF_1 0x0200U /*!<Bit 1 */
+#define TIM_SMCR_ETF_2 0x0400U /*!<Bit 2 */
+#define TIM_SMCR_ETF_3 0x0800U /*!<Bit 3 */
+
+#define TIM_SMCR_ETPS 0x3000U /*!<ETPS[1:0] bits (External trigger prescaler) */
+#define TIM_SMCR_ETPS_0 0x1000U /*!<Bit 0 */
+#define TIM_SMCR_ETPS_1 0x2000U /*!<Bit 1 */
+
+#define TIM_SMCR_ECE 0x4000U /*!<External clock enable */
+#define TIM_SMCR_ETP 0x8000U /*!<External trigger polarity */
+
+/******************* Bit definition for TIM_DIER register *******************/
+#define TIM_DIER_UIE 0x0001U /*!<Update interrupt enable */
+#define TIM_DIER_CC1IE 0x0002U /*!<Capture/Compare 1 interrupt enable */
+#define TIM_DIER_CC2IE 0x0004U /*!<Capture/Compare 2 interrupt enable */
+#define TIM_DIER_CC3IE 0x0008U /*!<Capture/Compare 3 interrupt enable */
+#define TIM_DIER_CC4IE 0x0010U /*!<Capture/Compare 4 interrupt enable */
+#define TIM_DIER_COMIE 0x0020U /*!<COM interrupt enable */
+#define TIM_DIER_TIE 0x0040U /*!<Trigger interrupt enable */
+#define TIM_DIER_BIE 0x0080U /*!<Break interrupt enable */
+#define TIM_DIER_UDE 0x0100U /*!<Update DMA request enable */
+#define TIM_DIER_CC1DE 0x0200U /*!<Capture/Compare 1 DMA request enable */
+#define TIM_DIER_CC2DE 0x0400U /*!<Capture/Compare 2 DMA request enable */
+#define TIM_DIER_CC3DE 0x0800U /*!<Capture/Compare 3 DMA request enable */
+#define TIM_DIER_CC4DE 0x1000U /*!<Capture/Compare 4 DMA request enable */
+#define TIM_DIER_COMDE 0x2000U /*!<COM DMA request enable */
+#define TIM_DIER_TDE 0x4000U /*!<Trigger DMA request enable */
+
+/******************** Bit definition for TIM_SR register ********************/
+#define TIM_SR_UIF 0x0001U /*!<Update interrupt Flag */
+#define TIM_SR_CC1IF 0x0002U /*!<Capture/Compare 1 interrupt Flag */
+#define TIM_SR_CC2IF 0x0004U /*!<Capture/Compare 2 interrupt Flag */
+#define TIM_SR_CC3IF 0x0008U /*!<Capture/Compare 3 interrupt Flag */
+#define TIM_SR_CC4IF 0x0010U /*!<Capture/Compare 4 interrupt Flag */
+#define TIM_SR_COMIF 0x0020U /*!<COM interrupt Flag */
+#define TIM_SR_TIF 0x0040U /*!<Trigger interrupt Flag */
+#define TIM_SR_BIF 0x0080U /*!<Break interrupt Flag */
+#define TIM_SR_CC1OF 0x0200U /*!<Capture/Compare 1 Overcapture Flag */
+#define TIM_SR_CC2OF 0x0400U /*!<Capture/Compare 2 Overcapture Flag */
+#define TIM_SR_CC3OF 0x0800U /*!<Capture/Compare 3 Overcapture Flag */
+#define TIM_SR_CC4OF 0x1000U /*!<Capture/Compare 4 Overcapture Flag */
+
+/******************* Bit definition for TIM_EGR register ********************/
+#define TIM_EGR_UG 0x01U /*!<Update Generation */
+#define TIM_EGR_CC1G 0x02U /*!<Capture/Compare 1 Generation */
+#define TIM_EGR_CC2G 0x04U /*!<Capture/Compare 2 Generation */
+#define TIM_EGR_CC3G 0x08U /*!<Capture/Compare 3 Generation */
+#define TIM_EGR_CC4G 0x10U /*!<Capture/Compare 4 Generation */
+#define TIM_EGR_COMG 0x20U /*!<Capture/Compare Control Update Generation */
+#define TIM_EGR_TG 0x40U /*!<Trigger Generation */
+#define TIM_EGR_BG 0x80U /*!<Break Generation */
+
+/****************** Bit definition for TIM_CCMR1 register *******************/
+#define TIM_CCMR1_CC1S 0x0003U /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
+#define TIM_CCMR1_CC1S_0 0x0001U /*!<Bit 0 */
+#define TIM_CCMR1_CC1S_1 0x0002U /*!<Bit 1 */
+
+#define TIM_CCMR1_OC1FE 0x0004U /*!<Output Compare 1 Fast enable */
+#define TIM_CCMR1_OC1PE 0x0008U /*!<Output Compare 1 Preload enable */
+
+#define TIM_CCMR1_OC1M 0x0070U /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
+#define TIM_CCMR1_OC1M_0 0x0010U /*!<Bit 0 */
+#define TIM_CCMR1_OC1M_1 0x0020U /*!<Bit 1 */
+#define TIM_CCMR1_OC1M_2 0x0040U /*!<Bit 2 */
+
+#define TIM_CCMR1_OC1CE 0x0080U /*!<Output Compare 1Clear Enable */
+
+#define TIM_CCMR1_CC2S 0x0300U /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
+#define TIM_CCMR1_CC2S_0 0x0100U /*!<Bit 0 */
+#define TIM_CCMR1_CC2S_1 0x0200U /*!<Bit 1 */
+
+#define TIM_CCMR1_OC2FE 0x0400U /*!<Output Compare 2 Fast enable */
+#define TIM_CCMR1_OC2PE 0x0800U /*!<Output Compare 2 Preload enable */
+
+#define TIM_CCMR1_OC2M 0x7000U /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
+#define TIM_CCMR1_OC2M_0 0x1000U /*!<Bit 0 */
+#define TIM_CCMR1_OC2M_1 0x2000U /*!<Bit 1 */
+#define TIM_CCMR1_OC2M_2 0x4000U /*!<Bit 2 */
+
+#define TIM_CCMR1_OC2CE 0x8000U /*!<Output Compare 2 Clear Enable */
+
+/*----------------------------------------------------------------------------*/
+
+#define TIM_CCMR1_IC1PSC 0x000CU /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
+#define TIM_CCMR1_IC1PSC_0 0x0004U /*!<Bit 0 */
+#define TIM_CCMR1_IC1PSC_1 0x0008U /*!<Bit 1 */
+
+#define TIM_CCMR1_IC1F 0x00F0U /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
+#define TIM_CCMR1_IC1F_0 0x0010U /*!<Bit 0 */
+#define TIM_CCMR1_IC1F_1 0x0020U /*!<Bit 1 */
+#define TIM_CCMR1_IC1F_2 0x0040U /*!<Bit 2 */
+#define TIM_CCMR1_IC1F_3 0x0080U /*!<Bit 3 */
+
+#define TIM_CCMR1_IC2PSC 0x0C00U /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
+#define TIM_CCMR1_IC2PSC_0 0x0400U /*!<Bit 0 */
+#define TIM_CCMR1_IC2PSC_1 0x0800U /*!<Bit 1 */
+
+#define TIM_CCMR1_IC2F 0xF000U /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
+#define TIM_CCMR1_IC2F_0 0x1000U /*!<Bit 0 */
+#define TIM_CCMR1_IC2F_1 0x2000U /*!<Bit 1 */
+#define TIM_CCMR1_IC2F_2 0x4000U /*!<Bit 2 */
+#define TIM_CCMR1_IC2F_3 0x8000U /*!<Bit 3 */
+
+/****************** Bit definition for TIM_CCMR2 register *******************/
+#define TIM_CCMR2_CC3S 0x0003U /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
+#define TIM_CCMR2_CC3S_0 0x0001U /*!<Bit 0 */
+#define TIM_CCMR2_CC3S_1 0x0002U /*!<Bit 1 */
+
+#define TIM_CCMR2_OC3FE 0x0004U /*!<Output Compare 3 Fast enable */
+#define TIM_CCMR2_OC3PE 0x0008U /*!<Output Compare 3 Preload enable */
+
+#define TIM_CCMR2_OC3M 0x0070U /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
+#define TIM_CCMR2_OC3M_0 0x0010U /*!<Bit 0 */
+#define TIM_CCMR2_OC3M_1 0x0020U /*!<Bit 1 */
+#define TIM_CCMR2_OC3M_2 0x0040U /*!<Bit 2 */
+
+#define TIM_CCMR2_OC3CE 0x0080U /*!<Output Compare 3 Clear Enable */
+
+#define TIM_CCMR2_CC4S 0x0300U /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
+#define TIM_CCMR2_CC4S_0 0x0100U /*!<Bit 0 */
+#define TIM_CCMR2_CC4S_1 0x0200U /*!<Bit 1 */
+
+#define TIM_CCMR2_OC4FE 0x0400U /*!<Output Compare 4 Fast enable */
+#define TIM_CCMR2_OC4PE 0x0800U /*!<Output Compare 4 Preload enable */
+
+#define TIM_CCMR2_OC4M 0x7000U /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
+#define TIM_CCMR2_OC4M_0 0x1000U /*!<Bit 0 */
+#define TIM_CCMR2_OC4M_1 0x2000U /*!<Bit 1 */
+#define TIM_CCMR2_OC4M_2 0x4000U /*!<Bit 2 */
+
+#define TIM_CCMR2_OC4CE 0x8000U /*!<Output Compare 4 Clear Enable */
+
+/*----------------------------------------------------------------------------*/
+
+#define TIM_CCMR2_IC3PSC 0x000CU /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
+#define TIM_CCMR2_IC3PSC_0 0x0004U /*!<Bit 0 */
+#define TIM_CCMR2_IC3PSC_1 0x0008U /*!<Bit 1 */
+
+#define TIM_CCMR2_IC3F 0x00F0U /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
+#define TIM_CCMR2_IC3F_0 0x0010U /*!<Bit 0 */
+#define TIM_CCMR2_IC3F_1 0x0020U /*!<Bit 1 */
+#define TIM_CCMR2_IC3F_2 0x0040U /*!<Bit 2 */
+#define TIM_CCMR2_IC3F_3 0x0080U /*!<Bit 3 */
+
+#define TIM_CCMR2_IC4PSC 0x0C00U /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
+#define TIM_CCMR2_IC4PSC_0 0x0400U /*!<Bit 0 */
+#define TIM_CCMR2_IC4PSC_1 0x0800U /*!<Bit 1 */
+
+#define TIM_CCMR2_IC4F 0xF000U /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
+#define TIM_CCMR2_IC4F_0 0x1000U /*!<Bit 0 */
+#define TIM_CCMR2_IC4F_1 0x2000U /*!<Bit 1 */
+#define TIM_CCMR2_IC4F_2 0x4000U /*!<Bit 2 */
+#define TIM_CCMR2_IC4F_3 0x8000U /*!<Bit 3 */
+
+/******************* Bit definition for TIM_CCER register *******************/
+#define TIM_CCER_CC1E 0x0001U /*!<Capture/Compare 1 output enable */
+#define TIM_CCER_CC1P 0x0002U /*!<Capture/Compare 1 output Polarity */
+#define TIM_CCER_CC1NE 0x0004U /*!<Capture/Compare 1 Complementary output enable */
+#define TIM_CCER_CC1NP 0x0008U /*!<Capture/Compare 1 Complementary output Polarity */
+#define TIM_CCER_CC2E 0x0010U /*!<Capture/Compare 2 output enable */
+#define TIM_CCER_CC2P 0x0020U /*!<Capture/Compare 2 output Polarity */
+#define TIM_CCER_CC2NE 0x0040U /*!<Capture/Compare 2 Complementary output enable */
+#define TIM_CCER_CC2NP 0x0080U /*!<Capture/Compare 2 Complementary output Polarity */
+#define TIM_CCER_CC3E 0x0100U /*!<Capture/Compare 3 output enable */
+#define TIM_CCER_CC3P 0x0200U /*!<Capture/Compare 3 output Polarity */
+#define TIM_CCER_CC3NE 0x0400U /*!<Capture/Compare 3 Complementary output enable */
+#define TIM_CCER_CC3NP 0x0800U /*!<Capture/Compare 3 Complementary output Polarity */
+#define TIM_CCER_CC4E 0x1000U /*!<Capture/Compare 4 output enable */
+#define TIM_CCER_CC4P 0x2000U /*!<Capture/Compare 4 output Polarity */
+#define TIM_CCER_CC4NP 0x8000U /*!<Capture/Compare 4 Complementary output Polarity */
+
+/******************* Bit definition for TIM_CNT register ********************/
+#define TIM_CNT_CNT 0xFFFFU /*!<Counter Value */
+
+/******************* Bit definition for TIM_PSC register ********************/
+#define TIM_PSC_PSC 0xFFFFU /*!<Prescaler Value */
+
+/******************* Bit definition for TIM_ARR register ********************/
+#define TIM_ARR_ARR 0xFFFFU /*!<actual auto-reload Value */
+
+/******************* Bit definition for TIM_RCR register ********************/
+#define TIM_RCR_REP 0xFFU /*!<Repetition Counter Value */
+
+/******************* Bit definition for TIM_CCR1 register *******************/
+#define TIM_CCR1_CCR1 0xFFFFU /*!<Capture/Compare 1 Value */
+
+/******************* Bit definition for TIM_CCR2 register *******************/
+#define TIM_CCR2_CCR2 0xFFFFU /*!<Capture/Compare 2 Value */
+
+/******************* Bit definition for TIM_CCR3 register *******************/
+#define TIM_CCR3_CCR3 0xFFFFU /*!<Capture/Compare 3 Value */
+
+/******************* Bit definition for TIM_CCR4 register *******************/
+#define TIM_CCR4_CCR4 0xFFFFU /*!<Capture/Compare 4 Value */
+
+/******************* Bit definition for TIM_BDTR register *******************/
+#define TIM_BDTR_DTG 0x00FFU /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
+#define TIM_BDTR_DTG_0 0x0001U /*!<Bit 0 */
+#define TIM_BDTR_DTG_1 0x0002U /*!<Bit 1 */
+#define TIM_BDTR_DTG_2 0x0004U /*!<Bit 2 */
+#define TIM_BDTR_DTG_3 0x0008U /*!<Bit 3 */
+#define TIM_BDTR_DTG_4 0x0010U /*!<Bit 4 */
+#define TIM_BDTR_DTG_5 0x0020U /*!<Bit 5 */
+#define TIM_BDTR_DTG_6 0x0040U /*!<Bit 6 */
+#define TIM_BDTR_DTG_7 0x0080U /*!<Bit 7 */
+
+#define TIM_BDTR_LOCK 0x0300U /*!<LOCK[1:0] bits (Lock Configuration) */
+#define TIM_BDTR_LOCK_0 0x0100U /*!<Bit 0 */
+#define TIM_BDTR_LOCK_1 0x0200U /*!<Bit 1 */
+
+#define TIM_BDTR_OSSI 0x0400U /*!<Off-State Selection for Idle mode */
+#define TIM_BDTR_OSSR 0x0800U /*!<Off-State Selection for Run mode */
+#define TIM_BDTR_BKE 0x1000U /*!<Break enable */
+#define TIM_BDTR_BKP 0x2000U /*!<Break Polarity */
+#define TIM_BDTR_AOE 0x4000U /*!<Automatic Output enable */
+#define TIM_BDTR_MOE 0x8000U /*!<Main Output enable */
+
+/******************* Bit definition for TIM_DCR register ********************/
+#define TIM_DCR_DBA 0x001FU /*!<DBA[4:0] bits (DMA Base Address) */
+#define TIM_DCR_DBA_0 0x0001U /*!<Bit 0 */
+#define TIM_DCR_DBA_1 0x0002U /*!<Bit 1 */
+#define TIM_DCR_DBA_2 0x0004U /*!<Bit 2 */
+#define TIM_DCR_DBA_3 0x0008U /*!<Bit 3 */
+#define TIM_DCR_DBA_4 0x0010U /*!<Bit 4 */
+
+#define TIM_DCR_DBL 0x1F00U /*!<DBL[4:0] bits (DMA Burst Length) */
+#define TIM_DCR_DBL_0 0x0100U /*!<Bit 0 */
+#define TIM_DCR_DBL_1 0x0200U /*!<Bit 1 */
+#define TIM_DCR_DBL_2 0x0400U /*!<Bit 2 */
+#define TIM_DCR_DBL_3 0x0800U /*!<Bit 3 */
+#define TIM_DCR_DBL_4 0x1000U /*!<Bit 4 */
+
+/******************* Bit definition for TIM_DMAR register *******************/
+#define TIM_DMAR_DMAB 0xFFFFU /*!<DMA register for burst accesses */
+
+/******************* Bit definition for TIM_OR register *********************/
+#define TIM_OR_TI4_RMP 0x00C0U /*!<TI4_RMP[1:0] bits (TIM5 Input 4 remap) */
+#define TIM_OR_TI4_RMP_0 0x0040U /*!<Bit 0 */
+#define TIM_OR_TI4_RMP_1 0x0080U /*!<Bit 1 */
+#define TIM_OR_ITR1_RMP 0x0C00U /*!<ITR1_RMP[1:0] bits (TIM2 Internal trigger 1 remap) */
+#define TIM_OR_ITR1_RMP_0 0x0400U /*!<Bit 0 */
+#define TIM_OR_ITR1_RMP_1 0x0800U /*!<Bit 1 */
+
+
+/******************************************************************************/
+/* */
+/* Universal Synchronous Asynchronous Receiver Transmitter */
+/* */
+/******************************************************************************/
+/******************* Bit definition for USART_SR register *******************/
+#define USART_SR_PE 0x0001U /*!<Parity Error */
+#define USART_SR_FE 0x0002U /*!<Framing Error */
+#define USART_SR_NE 0x0004U /*!<Noise Error Flag */
+#define USART_SR_ORE 0x0008U /*!<OverRun Error */
+#define USART_SR_IDLE 0x0010U /*!<IDLE line detected */
+#define USART_SR_RXNE 0x0020U /*!<Read Data Register Not Empty */
+#define USART_SR_TC 0x0040U /*!<Transmission Complete */
+#define USART_SR_TXE 0x0080U /*!<Transmit Data Register Empty */
+#define USART_SR_LBD 0x0100U /*!<LIN Break Detection Flag */
+#define USART_SR_CTS 0x0200U /*!<CTS Flag */
+
+/******************* Bit definition for USART_DR register *******************/
+#define USART_DR_DR 0x01FFU /*!<Data value */
+
+/****************** Bit definition for USART_BRR register *******************/
+#define USART_BRR_DIV_Fraction 0x000FU /*!<Fraction of USARTDIV */
+#define USART_BRR_DIV_Mantissa 0xFFF0U /*!<Mantissa of USARTDIV */
+
+/****************** Bit definition for USART_CR1 register *******************/
+#define USART_CR1_SBK 0x0001U /*!<Send Break */
+#define USART_CR1_RWU 0x0002U /*!<Receiver wakeup */
+#define USART_CR1_RE 0x0004U /*!<Receiver Enable */
+#define USART_CR1_TE 0x0008U /*!<Transmitter Enable */
+#define USART_CR1_IDLEIE 0x0010U /*!<IDLE Interrupt Enable */
+#define USART_CR1_RXNEIE 0x0020U /*!<RXNE Interrupt Enable */
+#define USART_CR1_TCIE 0x0040U /*!<Transmission Complete Interrupt Enable */
+#define USART_CR1_TXEIE 0x0080U /*!<PE Interrupt Enable */
+#define USART_CR1_PEIE 0x0100U /*!<PE Interrupt Enable */
+#define USART_CR1_PS 0x0200U /*!<Parity Selection */
+#define USART_CR1_PCE 0x0400U /*!<Parity Control Enable */
+#define USART_CR1_WAKE 0x0800U /*!<Wakeup method */
+#define USART_CR1_M 0x1000U /*!<Word length */
+#define USART_CR1_UE 0x2000U /*!<USART Enable */
+#define USART_CR1_OVER8 0x8000U /*!<USART Oversampling by 8 enable */
+
+/****************** Bit definition for USART_CR2 register *******************/
+#define USART_CR2_ADD 0x000FU /*!<Address of the USART node */
+#define USART_CR2_LBDL 0x0020U /*!<LIN Break Detection Length */
+#define USART_CR2_LBDIE 0x0040U /*!<LIN Break Detection Interrupt Enable */
+#define USART_CR2_LBCL 0x0100U /*!<Last Bit Clock pulse */
+#define USART_CR2_CPHA 0x0200U /*!<Clock Phase */
+#define USART_CR2_CPOL 0x0400U /*!<Clock Polarity */
+#define USART_CR2_CLKEN 0x0800U /*!<Clock Enable */
+
+#define USART_CR2_STOP 0x3000U /*!<STOP[1:0] bits (STOP bits) */
+#define USART_CR2_STOP_0 0x1000U /*!<Bit 0 */
+#define USART_CR2_STOP_1 0x2000U /*!<Bit 1 */
+
+#define USART_CR2_LINEN 0x4000U /*!<LIN mode enable */
+
+/****************** Bit definition for USART_CR3 register *******************/
+#define USART_CR3_EIE 0x0001U /*!<Error Interrupt Enable */
+#define USART_CR3_IREN 0x0002U /*!<IrDA mode Enable */
+#define USART_CR3_IRLP 0x0004U /*!<IrDA Low-Power */
+#define USART_CR3_HDSEL 0x0008U /*!<Half-Duplex Selection */
+#define USART_CR3_NACK 0x0010U /*!<Smartcard NACK enable */
+#define USART_CR3_SCEN 0x0020U /*!<Smartcard mode enable */
+#define USART_CR3_DMAR 0x0040U /*!<DMA Enable Receiver */
+#define USART_CR3_DMAT 0x0080U /*!<DMA Enable Transmitter */
+#define USART_CR3_RTSE 0x0100U /*!<RTS Enable */
+#define USART_CR3_CTSE 0x0200U /*!<CTS Enable */
+#define USART_CR3_CTSIE 0x0400U /*!<CTS Interrupt Enable */
+#define USART_CR3_ONEBIT 0x0800U /*!<USART One bit method enable */
+
+/****************** Bit definition for USART_GTPR register ******************/
+#define USART_GTPR_PSC 0x00FFU /*!<PSC[7:0] bits (Prescaler value) */
+#define USART_GTPR_PSC_0 0x0001U /*!<Bit 0 */
+#define USART_GTPR_PSC_1 0x0002U /*!<Bit 1 */
+#define USART_GTPR_PSC_2 0x0004U /*!<Bit 2 */
+#define USART_GTPR_PSC_3 0x0008U /*!<Bit 3 */
+#define USART_GTPR_PSC_4 0x0010U /*!<Bit 4 */
+#define USART_GTPR_PSC_5 0x0020U /*!<Bit 5 */
+#define USART_GTPR_PSC_6 0x0040U /*!<Bit 6 */
+#define USART_GTPR_PSC_7 0x0080U /*!<Bit 7 */
+
+#define USART_GTPR_GT 0xFF00U /*!<Guard time value */
+
+/******************************************************************************/
+/* */
+/* Window WATCHDOG */
+/* */
+/******************************************************************************/
+/******************* Bit definition for WWDG_CR register ********************/
+#define WWDG_CR_T 0x7FU /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
+#define WWDG_CR_T_0 0x01U /*!<Bit 0 */
+#define WWDG_CR_T_1 0x02U /*!<Bit 1 */
+#define WWDG_CR_T_2 0x04U /*!<Bit 2 */
+#define WWDG_CR_T_3 0x08U /*!<Bit 3 */
+#define WWDG_CR_T_4 0x10U /*!<Bit 4 */
+#define WWDG_CR_T_5 0x20U /*!<Bit 5 */
+#define WWDG_CR_T_6 0x40U /*!<Bit 6 */
+/* Legacy defines */
+#define WWDG_CR_T0 WWDG_CR_T_0
+#define WWDG_CR_T1 WWDG_CR_T_1
+#define WWDG_CR_T2 WWDG_CR_T_2
+#define WWDG_CR_T3 WWDG_CR_T_3
+#define WWDG_CR_T4 WWDG_CR_T_4
+#define WWDG_CR_T5 WWDG_CR_T_5
+#define WWDG_CR_T6 WWDG_CR_T_6
+
+#define WWDG_CR_WDGA 0x80U /*!<Activation bit */
+
+/******************* Bit definition for WWDG_CFR register *******************/
+#define WWDG_CFR_W 0x007FU /*!<W[6:0] bits (7-bit window value) */
+#define WWDG_CFR_W_0 0x0001U /*!<Bit 0 */
+#define WWDG_CFR_W_1 0x0002U /*!<Bit 1 */
+#define WWDG_CFR_W_2 0x0004U /*!<Bit 2 */
+#define WWDG_CFR_W_3 0x0008U /*!<Bit 3 */
+#define WWDG_CFR_W_4 0x0010U /*!<Bit 4 */
+#define WWDG_CFR_W_5 0x0020U /*!<Bit 5 */
+#define WWDG_CFR_W_6 0x0040U /*!<Bit 6 */
+/* Legacy defines */
+#define WWDG_CFR_W0 WWDG_CFR_W_0
+#define WWDG_CFR_W1 WWDG_CFR_W_1
+#define WWDG_CFR_W2 WWDG_CFR_W_2
+#define WWDG_CFR_W3 WWDG_CFR_W_3
+#define WWDG_CFR_W4 WWDG_CFR_W_4
+#define WWDG_CFR_W5 WWDG_CFR_W_5
+#define WWDG_CFR_W6 WWDG_CFR_W_6
+
+#define WWDG_CFR_WDGTB 0x0180U /*!<WDGTB[1:0] bits (Timer Base) */
+#define WWDG_CFR_WDGTB_0 0x0080U /*!<Bit 0 */
+#define WWDG_CFR_WDGTB_1 0x0100U /*!<Bit 1 */
+/* Legacy defines */
+#define WWDG_CFR_WDGTB0 WWDG_CFR_WDGTB_0
+#define WWDG_CFR_WDGTB1 WWDG_CFR_WDGTB_1
+
+#define WWDG_CFR_EWI 0x0200U /*!<Early Wakeup Interrupt */
+
+/******************* Bit definition for WWDG_SR register ********************/
+#define WWDG_SR_EWIF 0x01U /*!<Early Wakeup Interrupt Flag */
+
+
+/******************************************************************************/
+/* */
+/* DBG */
+/* */
+/******************************************************************************/
+/******************** Bit definition for DBGMCU_IDCODE register *************/
+#define DBGMCU_IDCODE_DEV_ID 0x00000FFFU
+#define DBGMCU_IDCODE_REV_ID 0xFFFF0000U
+
+/******************** Bit definition for DBGMCU_CR register *****************/
+#define DBGMCU_CR_DBG_SLEEP 0x00000001U
+#define DBGMCU_CR_DBG_STOP 0x00000002U
+#define DBGMCU_CR_DBG_STANDBY 0x00000004U
+#define DBGMCU_CR_TRACE_IOEN 0x00000020U
+
+#define DBGMCU_CR_TRACE_MODE 0x000000C0U
+#define DBGMCU_CR_TRACE_MODE_0 0x00000040U/*!<Bit 0 */
+#define DBGMCU_CR_TRACE_MODE_1 0x00000080U/*!<Bit 1 */
+
+/******************** Bit definition for DBGMCU_APB1_FZ register ************/
+#define DBGMCU_APB1_FZ_DBG_TIM2_STOP 0x00000001U
+#define DBGMCU_APB1_FZ_DBG_TIM3_STOP 0x00000002U
+#define DBGMCU_APB1_FZ_DBG_TIM4_STOP 0x00000004U
+#define DBGMCU_APB1_FZ_DBG_TIM5_STOP 0x00000008U
+#define DBGMCU_APB1_FZ_DBG_TIM6_STOP 0x00000010U
+#define DBGMCU_APB1_FZ_DBG_TIM7_STOP 0x00000020U
+#define DBGMCU_APB1_FZ_DBG_TIM12_STOP 0x00000040U
+#define DBGMCU_APB1_FZ_DBG_TIM13_STOP 0x00000080U
+#define DBGMCU_APB1_FZ_DBG_TIM14_STOP 0x00000100U
+#define DBGMCU_APB1_FZ_DBG_RTC_STOP 0x00000400U
+#define DBGMCU_APB1_FZ_DBG_WWDG_STOP 0x00000800U
+#define DBGMCU_APB1_FZ_DBG_IWDG_STOP 0x00001000U
+#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT 0x00200000U
+#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT 0x00400000U
+#define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT 0x00800000U
+#define DBGMCU_APB1_FZ_DBG_CAN1_STOP 0x02000000U
+#define DBGMCU_APB1_FZ_DBG_CAN2_STOP 0x04000000U
+/* Old IWDGSTOP bit definition, maintained for legacy purpose */
+#define DBGMCU_APB1_FZ_DBG_IWDEG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP
+
+/******************** Bit definition for DBGMCU_APB2_FZ register ************/
+#define DBGMCU_APB2_FZ_DBG_TIM1_STOP 0x00000001U
+#define DBGMCU_APB2_FZ_DBG_TIM8_STOP 0x00000002U
+#define DBGMCU_APB2_FZ_DBG_TIM9_STOP 0x00010000U
+#define DBGMCU_APB2_FZ_DBG_TIM10_STOP 0x00020000U
+#define DBGMCU_APB2_FZ_DBG_TIM11_STOP 0x00040000U
+
+
+/******************************************************************************/
+/* */
+/* USB_OTG */
+/* */
+/******************************************************************************/
+/******************** Bit definition for USB_OTG_GOTGCTL register ********************/
+#define USB_OTG_GOTGCTL_SRQSCS 0x00000001U /*!< Session request success */
+#define USB_OTG_GOTGCTL_SRQ 0x00000002U /*!< Session request */
+#define USB_OTG_GOTGCTL_VBVALOEN 0x00000004U /*!< VBUS valid override enable */
+#define USB_OTG_GOTGCTL_VBVALOVAL 0x00000008U /*!< VBUS valid override value */
+#define USB_OTG_GOTGCTL_AVALOEN 0x00000010U /*!< A-peripheral session valid override enable */
+#define USB_OTG_GOTGCTL_AVALOVAL 0x00000020U /*!< A-peripheral session valid override value */
+#define USB_OTG_GOTGCTL_BVALOEN 0x00000040U /*!< B-peripheral session valid override enable */
+#define USB_OTG_GOTGCTL_BVALOVAL 0x00000080U /*!< B-peripheral session valid override value */
+#define USB_OTG_GOTGCTL_HNGSCS 0x00000100U /*!< Host set HNP enable */
+#define USB_OTG_GOTGCTL_HNPRQ 0x00000200U /*!< HNP request */
+#define USB_OTG_GOTGCTL_HSHNPEN 0x00000400U /*!< Host set HNP enable */
+#define USB_OTG_GOTGCTL_DHNPEN 0x00000800U /*!< Device HNP enabled */
+#define USB_OTG_GOTGCTL_EHEN 0x00001000U /*!< Embedded host enable */
+#define USB_OTG_GOTGCTL_CIDSTS 0x00010000U /*!< Connector ID status */
+#define USB_OTG_GOTGCTL_DBCT 0x00020000U /*!< Long/short debounce time */
+#define USB_OTG_GOTGCTL_ASVLD 0x00040000U /*!< A-session valid */
+#define USB_OTG_GOTGCTL_BSESVLD 0x00080000U /*!< B-session valid */
+#define USB_OTG_GOTGCTL_OTGVER 0x00100000U /*!< OTG version */
+
+/******************** Bit definition for USB_OTG_HCFG register ********************/
+
+#define USB_OTG_HCFG_FSLSPCS 0x00000003U /*!< FS/LS PHY clock select */
+#define USB_OTG_HCFG_FSLSPCS_0 0x00000001U /*!<Bit 0 */
+#define USB_OTG_HCFG_FSLSPCS_1 0x00000002U /*!<Bit 1 */
+#define USB_OTG_HCFG_FSLSS 0x00000004U /*!< FS- and LS-only support */
+
+/******************** Bit definition for USB_OTG_DCFG register ********************/
+
+#define USB_OTG_DCFG_DSPD 0x00000003U /*!< Device speed */
+#define USB_OTG_DCFG_DSPD_0 0x00000001U /*!<Bit 0 */
+#define USB_OTG_DCFG_DSPD_1 0x00000002U /*!<Bit 1 */
+#define USB_OTG_DCFG_NZLSOHSK 0x00000004U /*!< Nonzero-length status OUT handshake */
+
+#define USB_OTG_DCFG_DAD 0x000007F0U /*!< Device address */
+#define USB_OTG_DCFG_DAD_0 0x00000010U /*!<Bit 0 */
+#define USB_OTG_DCFG_DAD_1 0x00000020U /*!<Bit 1 */
+#define USB_OTG_DCFG_DAD_2 0x00000040U /*!<Bit 2 */
+#define USB_OTG_DCFG_DAD_3 0x00000080U /*!<Bit 3 */
+#define USB_OTG_DCFG_DAD_4 0x00000100U /*!<Bit 4 */
+#define USB_OTG_DCFG_DAD_5 0x00000200U /*!<Bit 5 */
+#define USB_OTG_DCFG_DAD_6 0x00000400U /*!<Bit 6 */
+
+#define USB_OTG_DCFG_PFIVL 0x00001800U /*!< Periodic (micro)frame interval */
+#define USB_OTG_DCFG_PFIVL_0 0x00000800U /*!<Bit 0 */
+#define USB_OTG_DCFG_PFIVL_1 0x00001000U /*!<Bit 1 */
+
+#define USB_OTG_DCFG_PERSCHIVL 0x03000000U /*!< Periodic scheduling interval */
+#define USB_OTG_DCFG_PERSCHIVL_0 0x01000000U /*!<Bit 0 */
+#define USB_OTG_DCFG_PERSCHIVL_1 0x02000000U /*!<Bit 1 */
+
+/******************** Bit definition for USB_OTG_PCGCR register ********************/
+#define USB_OTG_PCGCR_STPPCLK 0x00000001U /*!< Stop PHY clock */
+#define USB_OTG_PCGCR_GATEHCLK 0x00000002U /*!< Gate HCLK */
+#define USB_OTG_PCGCR_PHYSUSP 0x00000010U /*!< PHY suspended */
+
+/******************** Bit definition for USB_OTG_GOTGINT register ********************/
+#define USB_OTG_GOTGINT_SEDET 0x00000004U /*!< Session end detected */
+#define USB_OTG_GOTGINT_SRSSCHG 0x00000100U /*!< Session request success status change */
+#define USB_OTG_GOTGINT_HNSSCHG 0x00000200U /*!< Host negotiation success status change */
+#define USB_OTG_GOTGINT_HNGDET 0x00020000U /*!< Host negotiation detected */
+#define USB_OTG_GOTGINT_ADTOCHG 0x00040000U /*!< A-device timeout change */
+#define USB_OTG_GOTGINT_DBCDNE 0x00080000U /*!< Debounce done */
+#define USB_OTG_GOTGINT_IDCHNG 0x00100000U /*!< Change in ID pin input value */
+
+/******************** Bit definition for USB_OTG_DCTL register ********************/
+#define USB_OTG_DCTL_RWUSIG 0x00000001U /*!< Remote wakeup signaling */
+#define USB_OTG_DCTL_SDIS 0x00000002U /*!< Soft disconnect */
+#define USB_OTG_DCTL_GINSTS 0x00000004U /*!< Global IN NAK status */
+#define USB_OTG_DCTL_GONSTS 0x00000008U /*!< Global OUT NAK status */
+
+#define USB_OTG_DCTL_TCTL 0x00000070U /*!< Test control */
+#define USB_OTG_DCTL_TCTL_0 0x00000010U /*!<Bit 0 */
+#define USB_OTG_DCTL_TCTL_1 0x00000020U /*!<Bit 1 */
+#define USB_OTG_DCTL_TCTL_2 0x00000040U /*!<Bit 2 */
+#define USB_OTG_DCTL_SGINAK 0x00000080U /*!< Set global IN NAK */
+#define USB_OTG_DCTL_CGINAK 0x00000100U /*!< Clear global IN NAK */
+#define USB_OTG_DCTL_SGONAK 0x00000200U /*!< Set global OUT NAK */
+#define USB_OTG_DCTL_CGONAK 0x00000400U /*!< Clear global OUT NAK */
+#define USB_OTG_DCTL_POPRGDNE 0x00000800U /*!< Power-on programming done */
+
+/******************** Bit definition for USB_OTG_HFIR register ********************/
+#define USB_OTG_HFIR_FRIVL 0x0000FFFFU /*!< Frame interval */
+
+/******************** Bit definition for USB_OTG_HFNUM register ********************/
+#define USB_OTG_HFNUM_FRNUM 0x0000FFFFU /*!< Frame number */
+#define USB_OTG_HFNUM_FTREM 0xFFFF0000U /*!< Frame time remaining */
+
+/******************** Bit definition for USB_OTG_DSTS register ********************/
+#define USB_OTG_DSTS_SUSPSTS 0x00000001U /*!< Suspend status */
+
+#define USB_OTG_DSTS_ENUMSPD 0x00000006U /*!< Enumerated speed */
+#define USB_OTG_DSTS_ENUMSPD_0 0x00000002U /*!<Bit 0 */
+#define USB_OTG_DSTS_ENUMSPD_1 0x00000004U /*!<Bit 1 */
+#define USB_OTG_DSTS_EERR 0x00000008U /*!< Erratic error */
+#define USB_OTG_DSTS_FNSOF 0x003FFF00U /*!< Frame number of the received SOF */
+
+/******************** Bit definition for USB_OTG_GAHBCFG register ********************/
+#define USB_OTG_GAHBCFG_GINT 0x00000001U /*!< Global interrupt mask */
+#define USB_OTG_GAHBCFG_HBSTLEN 0x0000001EU /*!< Burst length/type */
+#define USB_OTG_GAHBCFG_HBSTLEN_0 0x00000002U /*!<Bit 0 */
+#define USB_OTG_GAHBCFG_HBSTLEN_1 0x00000004U /*!<Bit 1 */
+#define USB_OTG_GAHBCFG_HBSTLEN_2 0x00000008U /*!<Bit 2 */
+#define USB_OTG_GAHBCFG_HBSTLEN_3 0x00000010U /*!<Bit 3 */
+#define USB_OTG_GAHBCFG_DMAEN 0x00000020U /*!< DMA enable */
+#define USB_OTG_GAHBCFG_TXFELVL 0x00000080U /*!< TxFIFO empty level */
+#define USB_OTG_GAHBCFG_PTXFELVL 0x00000100U /*!< Periodic TxFIFO empty level */
+
+/******************** Bit definition for USB_OTG_GUSBCFG register ********************/
+
+#define USB_OTG_GUSBCFG_TOCAL 0x00000007U /*!< FS timeout calibration */
+#define USB_OTG_GUSBCFG_TOCAL_0 0x00000001U /*!<Bit 0 */
+#define USB_OTG_GUSBCFG_TOCAL_1 0x00000002U /*!<Bit 1 */
+#define USB_OTG_GUSBCFG_TOCAL_2 0x00000004U /*!<Bit 2 */
+#define USB_OTG_GUSBCFG_PHYSEL 0x00000040U /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */
+#define USB_OTG_GUSBCFG_SRPCAP 0x00000100U /*!< SRP-capable */
+#define USB_OTG_GUSBCFG_HNPCAP 0x00000200U /*!< HNP-capable */
+#define USB_OTG_GUSBCFG_TRDT 0x00003C00U /*!< USB turnaround time */
+#define USB_OTG_GUSBCFG_TRDT_0 0x00000400U /*!<Bit 0 */
+#define USB_OTG_GUSBCFG_TRDT_1 0x00000800U /*!<Bit 1 */
+#define USB_OTG_GUSBCFG_TRDT_2 0x00001000U /*!<Bit 2 */
+#define USB_OTG_GUSBCFG_TRDT_3 0x00002000U /*!<Bit 3 */
+#define USB_OTG_GUSBCFG_PHYLPCS 0x00008000U /*!< PHY Low-power clock select */
+#define USB_OTG_GUSBCFG_ULPIFSLS 0x00020000U /*!< ULPI FS/LS select */
+#define USB_OTG_GUSBCFG_ULPIAR 0x00040000U /*!< ULPI Auto-resume */
+#define USB_OTG_GUSBCFG_ULPICSM 0x00080000U /*!< ULPI Clock SuspendM */
+#define USB_OTG_GUSBCFG_ULPIEVBUSD 0x00100000U /*!< ULPI External VBUS Drive */
+#define USB_OTG_GUSBCFG_ULPIEVBUSI 0x00200000U /*!< ULPI external VBUS indicator */
+#define USB_OTG_GUSBCFG_TSDPS 0x00400000U /*!< TermSel DLine pulsing selection */
+#define USB_OTG_GUSBCFG_PCCI 0x00800000U /*!< Indicator complement */
+#define USB_OTG_GUSBCFG_PTCI 0x01000000U /*!< Indicator pass through */
+#define USB_OTG_GUSBCFG_ULPIIPD 0x02000000U /*!< ULPI interface protect disable */
+#define USB_OTG_GUSBCFG_FHMOD 0x20000000U /*!< Forced host mode */
+#define USB_OTG_GUSBCFG_FDMOD 0x40000000U /*!< Forced peripheral mode */
+#define USB_OTG_GUSBCFG_CTXPKT 0x80000000U /*!< Corrupt Tx packet */
+
+/******************** Bit definition for USB_OTG_GRSTCTL register ********************/
+#define USB_OTG_GRSTCTL_CSRST 0x00000001U /*!< Core soft reset */
+#define USB_OTG_GRSTCTL_HSRST 0x00000002U /*!< HCLK soft reset */
+#define USB_OTG_GRSTCTL_FCRST 0x00000004U /*!< Host frame counter reset */
+#define USB_OTG_GRSTCTL_RXFFLSH 0x00000010U /*!< RxFIFO flush */
+#define USB_OTG_GRSTCTL_TXFFLSH 0x00000020U /*!< TxFIFO flush */
+#define USB_OTG_GRSTCTL_TXFNUM 0x000007C0U /*!< TxFIFO number */
+#define USB_OTG_GRSTCTL_TXFNUM_0 0x00000040U /*!<Bit 0 */
+#define USB_OTG_GRSTCTL_TXFNUM_1 0x00000080U /*!<Bit 1 */
+#define USB_OTG_GRSTCTL_TXFNUM_2 0x00000100U /*!<Bit 2 */
+#define USB_OTG_GRSTCTL_TXFNUM_3 0x00000200U /*!<Bit 3 */
+#define USB_OTG_GRSTCTL_TXFNUM_4 0x00000400U /*!<Bit 4 */
+#define USB_OTG_GRSTCTL_DMAREQ 0x40000000U /*!< DMA request signal */
+#define USB_OTG_GRSTCTL_AHBIDL 0x80000000U /*!< AHB master idle */
+
+/******************** Bit definition for USB_OTG_DIEPMSK register ********************/
+#define USB_OTG_DIEPMSK_XFRCM 0x00000001U /*!< Transfer completed interrupt mask */
+#define USB_OTG_DIEPMSK_EPDM 0x00000002U /*!< Endpoint disabled interrupt mask */
+#define USB_OTG_DIEPMSK_TOM 0x00000008U /*!< Timeout condition mask (nonisochronous endpoints) */
+#define USB_OTG_DIEPMSK_ITTXFEMSK 0x00000010U /*!< IN token received when TxFIFO empty mask */
+#define USB_OTG_DIEPMSK_INEPNMM 0x00000020U /*!< IN token received with EP mismatch mask */
+#define USB_OTG_DIEPMSK_INEPNEM 0x00000040U /*!< IN endpoint NAK effective mask */
+#define USB_OTG_DIEPMSK_TXFURM 0x00000100U /*!< FIFO underrun mask */
+#define USB_OTG_DIEPMSK_BIM 0x00000200U /*!< BNA interrupt mask */
+
+/******************** Bit definition for USB_OTG_HPTXSTS register ********************/
+#define USB_OTG_HPTXSTS_PTXFSAVL 0x0000FFFFU /*!< Periodic transmit data FIFO space available */
+#define USB_OTG_HPTXSTS_PTXQSAV 0x00FF0000U /*!< Periodic transmit request queue space available */
+#define USB_OTG_HPTXSTS_PTXQSAV_0 0x00010000U /*!<Bit 0 */
+#define USB_OTG_HPTXSTS_PTXQSAV_1 0x00020000U /*!<Bit 1 */
+#define USB_OTG_HPTXSTS_PTXQSAV_2 0x00040000U /*!<Bit 2 */
+#define USB_OTG_HPTXSTS_PTXQSAV_3 0x00080000U /*!<Bit 3 */
+#define USB_OTG_HPTXSTS_PTXQSAV_4 0x00100000U /*!<Bit 4 */
+#define USB_OTG_HPTXSTS_PTXQSAV_5 0x00200000U /*!<Bit 5 */
+#define USB_OTG_HPTXSTS_PTXQSAV_6 0x00400000U /*!<Bit 6 */
+#define USB_OTG_HPTXSTS_PTXQSAV_7 0x00800000U /*!<Bit 7 */
+
+#define USB_OTG_HPTXSTS_PTXQTOP 0xFF000000U /*!< Top of the periodic transmit request queue */
+#define USB_OTG_HPTXSTS_PTXQTOP_0 0x01000000U /*!<Bit 0 */
+#define USB_OTG_HPTXSTS_PTXQTOP_1 0x02000000U /*!<Bit 1 */
+#define USB_OTG_HPTXSTS_PTXQTOP_2 0x04000000U /*!<Bit 2 */
+#define USB_OTG_HPTXSTS_PTXQTOP_3 0x08000000U /*!<Bit 3 */
+#define USB_OTG_HPTXSTS_PTXQTOP_4 0x10000000U /*!<Bit 4 */
+#define USB_OTG_HPTXSTS_PTXQTOP_5 0x20000000U /*!<Bit 5 */
+#define USB_OTG_HPTXSTS_PTXQTOP_6 0x40000000U /*!<Bit 6 */
+#define USB_OTG_HPTXSTS_PTXQTOP_7 0x80000000U /*!<Bit 7 */
+
+/******************** Bit definition for USB_OTG_HAINT register ********************/
+#define USB_OTG_HAINT_HAINT 0x0000FFFFU /*!< Channel interrupts */
+
+/******************** Bit definition for USB_OTG_DOEPMSK register ********************/
+#define USB_OTG_DOEPMSK_XFRCM 0x00000001U /*!< Transfer completed interrupt mask */
+#define USB_OTG_DOEPMSK_EPDM 0x00000002U /*!< Endpoint disabled interrupt mask */
+#define USB_OTG_DOEPMSK_STUPM 0x00000008U /*!< SETUP phase done mask */
+#define USB_OTG_DOEPMSK_OTEPDM 0x00000010U /*!< OUT token received when endpoint disabled mask */
+#define USB_OTG_DOEPMSK_OTEPSPRM 0x00000020U /*!< Status Phase Received mask */
+#define USB_OTG_DOEPMSK_B2BSTUP 0x00000040U /*!< Back-to-back SETUP packets received mask */
+#define USB_OTG_DOEPMSK_OPEM 0x00000100U /*!< OUT packet error mask */
+#define USB_OTG_DOEPMSK_BOIM 0x00000200U /*!< BNA interrupt mask */
+
+/******************** Bit definition for USB_OTG_GINTSTS register ********************/
+#define USB_OTG_GINTSTS_CMOD 0x00000001U /*!< Current mode of operation */
+#define USB_OTG_GINTSTS_MMIS 0x00000002U /*!< Mode mismatch interrupt */
+#define USB_OTG_GINTSTS_OTGINT 0x00000004U /*!< OTG interrupt */
+#define USB_OTG_GINTSTS_SOF 0x00000008U /*!< Start of frame */
+#define USB_OTG_GINTSTS_RXFLVL 0x00000010U /*!< RxFIFO nonempty */
+#define USB_OTG_GINTSTS_NPTXFE 0x00000020U /*!< Nonperiodic TxFIFO empty */
+#define USB_OTG_GINTSTS_GINAKEFF 0x00000040U /*!< Global IN nonperiodic NAK effective */
+#define USB_OTG_GINTSTS_BOUTNAKEFF 0x00000080U /*!< Global OUT NAK effective */
+#define USB_OTG_GINTSTS_ESUSP 0x00000400U /*!< Early suspend */
+#define USB_OTG_GINTSTS_USBSUSP 0x00000800U /*!< USB suspend */
+#define USB_OTG_GINTSTS_USBRST 0x00001000U /*!< USB reset */
+#define USB_OTG_GINTSTS_ENUMDNE 0x00002000U /*!< Enumeration done */
+#define USB_OTG_GINTSTS_ISOODRP 0x00004000U /*!< Isochronous OUT packet dropped interrupt */
+#define USB_OTG_GINTSTS_EOPF 0x00008000U /*!< End of periodic frame interrupt */
+#define USB_OTG_GINTSTS_IEPINT 0x00040000U /*!< IN endpoint interrupt */
+#define USB_OTG_GINTSTS_OEPINT 0x00080000U /*!< OUT endpoint interrupt */
+#define USB_OTG_GINTSTS_IISOIXFR 0x00100000U /*!< Incomplete isochronous IN transfer */
+#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT 0x00200000U /*!< Incomplete periodic transfer */
+#define USB_OTG_GINTSTS_DATAFSUSP 0x00400000U /*!< Data fetch suspended */
+#define USB_OTG_GINTSTS_RSTDET 0x00800000U /*!< Reset detected interrupt */
+#define USB_OTG_GINTSTS_HPRTINT 0x01000000U /*!< Host port interrupt */
+#define USB_OTG_GINTSTS_HCINT 0x02000000U /*!< Host channels interrupt */
+#define USB_OTG_GINTSTS_PTXFE 0x04000000U /*!< Periodic TxFIFO empty */
+#define USB_OTG_GINTSTS_LPMINT 0x08000000U /*!< LPM interrupt */
+#define USB_OTG_GINTSTS_CIDSCHG 0x10000000U /*!< Connector ID status change */
+#define USB_OTG_GINTSTS_DISCINT 0x20000000U /*!< Disconnect detected interrupt */
+#define USB_OTG_GINTSTS_SRQINT 0x40000000U /*!< Session request/new session detected interrupt */
+#define USB_OTG_GINTSTS_WKUINT 0x80000000U /*!< Resume/remote wakeup detected interrupt */
+
+/******************** Bit definition for USB_OTG_GINTMSK register ********************/
+#define USB_OTG_GINTMSK_MMISM 0x00000002U /*!< Mode mismatch interrupt mask */
+#define USB_OTG_GINTMSK_OTGINT 0x00000004U /*!< OTG interrupt mask */
+#define USB_OTG_GINTMSK_SOFM 0x00000008U /*!< Start of frame mask */
+#define USB_OTG_GINTMSK_RXFLVLM 0x00000010U /*!< Receive FIFO nonempty mask */
+#define USB_OTG_GINTMSK_NPTXFEM 0x00000020U /*!< Nonperiodic TxFIFO empty mask */
+#define USB_OTG_GINTMSK_GINAKEFFM 0x00000040U /*!< Global nonperiodic IN NAK effective mask */
+#define USB_OTG_GINTMSK_GONAKEFFM 0x00000080U /*!< Global OUT NAK effective mask */
+#define USB_OTG_GINTMSK_ESUSPM 0x00000400U /*!< Early suspend mask */
+#define USB_OTG_GINTMSK_USBSUSPM 0x00000800U /*!< USB suspend mask */
+#define USB_OTG_GINTMSK_USBRST 0x00001000U /*!< USB reset mask */
+#define USB_OTG_GINTMSK_ENUMDNEM 0x00002000U /*!< Enumeration done mask */
+#define USB_OTG_GINTMSK_ISOODRPM 0x00004000U /*!< Isochronous OUT packet dropped interrupt mask */
+#define USB_OTG_GINTMSK_EOPFM 0x00008000U /*!< End of periodic frame interrupt mask */
+#define USB_OTG_GINTMSK_EPMISM 0x00020000U /*!< Endpoint mismatch interrupt mask */
+#define USB_OTG_GINTMSK_IEPINT 0x00040000U /*!< IN endpoints interrupt mask */
+#define USB_OTG_GINTMSK_OEPINT 0x00080000U /*!< OUT endpoints interrupt mask */
+#define USB_OTG_GINTMSK_IISOIXFRM 0x00100000U /*!< Incomplete isochronous IN transfer mask */
+#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM 0x00200000U /*!< Incomplete periodic transfer mask */
+#define USB_OTG_GINTMSK_FSUSPM 0x00400000U /*!< Data fetch suspended mask */
+#define USB_OTG_GINTMSK_RSTDEM 0x00800000U /*!< Reset detected interrupt mask */
+#define USB_OTG_GINTMSK_PRTIM 0x01000000U /*!< Host port interrupt mask */
+#define USB_OTG_GINTMSK_HCIM 0x02000000U /*!< Host channels interrupt mask */
+#define USB_OTG_GINTMSK_PTXFEM 0x04000000U /*!< Periodic TxFIFO empty mask */
+#define USB_OTG_GINTMSK_LPMINTM 0x08000000U /*!< LPM interrupt Mask */
+#define USB_OTG_GINTMSK_CIDSCHGM 0x10000000U /*!< Connector ID status change mask */
+#define USB_OTG_GINTMSK_DISCINT 0x20000000U /*!< Disconnect detected interrupt mask */
+#define USB_OTG_GINTMSK_SRQIM 0x40000000U /*!< Session request/new session detected interrupt mask */
+#define USB_OTG_GINTMSK_WUIM 0x80000000U /*!< Resume/remote wakeup detected interrupt mask */
+
+/******************** Bit definition for USB_OTG_DAINT register ********************/
+#define USB_OTG_DAINT_IEPINT 0x0000FFFFU /*!< IN endpoint interrupt bits */
+#define USB_OTG_DAINT_OEPINT 0xFFFF0000U /*!< OUT endpoint interrupt bits */
+
+/******************** Bit definition for USB_OTG_HAINTMSK register ********************/
+#define USB_OTG_HAINTMSK_HAINTM 0x0000FFFFU /*!< Channel interrupt mask */
+
+/******************** Bit definition for USB_OTG_GRXSTSP register ********************/
+#define USB_OTG_GRXSTSP_EPNUM 0x0000000FU /*!< IN EP interrupt mask bits */
+#define USB_OTG_GRXSTSP_BCNT 0x00007FF0U /*!< OUT EP interrupt mask bits */
+#define USB_OTG_GRXSTSP_DPID 0x00018000U /*!< OUT EP interrupt mask bits */
+#define USB_OTG_GRXSTSP_PKTSTS 0x001E0000U /*!< OUT EP interrupt mask bits */
+
+/******************** Bit definition for USB_OTG_DAINTMSK register ********************/
+#define USB_OTG_DAINTMSK_IEPM 0x0000FFFFU /*!< IN EP interrupt mask bits */
+#define USB_OTG_DAINTMSK_OEPM 0xFFFF0000U /*!< OUT EP interrupt mask bits */
+
+/******************** Bit definition for OTG register ********************/
+
+#define USB_OTG_CHNUM 0x0000000FU /*!< Channel number */
+#define USB_OTG_CHNUM_0 0x00000001U /*!<Bit 0 */
+#define USB_OTG_CHNUM_1 0x00000002U /*!<Bit 1 */
+#define USB_OTG_CHNUM_2 0x00000004U /*!<Bit 2 */
+#define USB_OTG_CHNUM_3 0x00000008U /*!<Bit 3 */
+#define USB_OTG_BCNT 0x00007FF0U /*!< Byte count */
+
+#define USB_OTG_DPID 0x00018000U /*!< Data PID */
+#define USB_OTG_DPID_0 0x00008000U /*!<Bit 0 */
+#define USB_OTG_DPID_1 0x00010000U /*!<Bit 1 */
+
+#define USB_OTG_PKTSTS 0x001E0000U /*!< Packet status */
+#define USB_OTG_PKTSTS_0 0x00020000U /*!<Bit 0 */
+#define USB_OTG_PKTSTS_1 0x00040000U /*!<Bit 1 */
+#define USB_OTG_PKTSTS_2 0x00080000U /*!<Bit 2 */
+#define USB_OTG_PKTSTS_3 0x00100000U /*!<Bit 3 */
+
+#define USB_OTG_EPNUM 0x0000000FU /*!< Endpoint number */
+#define USB_OTG_EPNUM_0 0x00000001U /*!<Bit 0 */
+#define USB_OTG_EPNUM_1 0x00000002U /*!<Bit 1 */
+#define USB_OTG_EPNUM_2 0x00000004U /*!<Bit 2 */
+#define USB_OTG_EPNUM_3 0x00000008U /*!<Bit 3 */
+
+#define USB_OTG_FRMNUM 0x01E00000U /*!< Frame number */
+#define USB_OTG_FRMNUM_0 0x00200000U /*!<Bit 0 */
+#define USB_OTG_FRMNUM_1 0x00400000U /*!<Bit 1 */
+#define USB_OTG_FRMNUM_2 0x00800000U /*!<Bit 2 */
+#define USB_OTG_FRMNUM_3 0x01000000U /*!<Bit 3 */
+
+/******************** Bit definition for OTG register ********************/
+
+#define USB_OTG_CHNUM 0x0000000FU /*!< Channel number */
+#define USB_OTG_CHNUM_0 0x00000001U /*!<Bit 0 */
+#define USB_OTG_CHNUM_1 0x00000002U /*!<Bit 1 */
+#define USB_OTG_CHNUM_2 0x00000004U /*!<Bit 2 */
+#define USB_OTG_CHNUM_3 0x00000008U /*!<Bit 3 */
+#define USB_OTG_BCNT 0x00007FF0U /*!< Byte count */
+
+#define USB_OTG_DPID 0x00018000U /*!< Data PID */
+#define USB_OTG_DPID_0 0x00008000U /*!<Bit 0 */
+#define USB_OTG_DPID_1 0x00010000U /*!<Bit 1 */
+
+#define USB_OTG_PKTSTS 0x001E0000U /*!< Packet status */
+#define USB_OTG_PKTSTS_0 0x00020000U /*!<Bit 0 */
+#define USB_OTG_PKTSTS_1 0x00040000U /*!<Bit 1 */
+#define USB_OTG_PKTSTS_2 0x00080000U /*!<Bit 2 */
+#define USB_OTG_PKTSTS_3 0x00100000U /*!<Bit 3 */
+
+#define USB_OTG_EPNUM 0x0000000FU /*!< Endpoint number */
+#define USB_OTG_EPNUM_0 0x00000001U /*!<Bit 0 */
+#define USB_OTG_EPNUM_1 0x00000002U /*!<Bit 1 */
+#define USB_OTG_EPNUM_2 0x00000004U /*!<Bit 2 */
+#define USB_OTG_EPNUM_3 0x00000008U /*!<Bit 3 */
+
+#define USB_OTG_FRMNUM 0x01E00000U /*!< Frame number */
+#define USB_OTG_FRMNUM_0 0x00200000U /*!<Bit 0 */
+#define USB_OTG_FRMNUM_1 0x00400000U /*!<Bit 1 */
+#define USB_OTG_FRMNUM_2 0x00800000U /*!<Bit 2 */
+#define USB_OTG_FRMNUM_3 0x01000000U /*!<Bit 3 */
+
+/******************** Bit definition for USB_OTG_GRXFSIZ register ********************/
+#define USB_OTG_GRXFSIZ_RXFD 0x0000FFFFU /*!< RxFIFO depth */
+
+/******************** Bit definition for USB_OTG_DVBUSDIS register ********************/
+#define USB_OTG_DVBUSDIS_VBUSDT 0x0000FFFFU /*!< Device VBUS discharge time */
+
+/******************** Bit definition for OTG register ********************/
+#define USB_OTG_NPTXFSA 0x0000FFFFU /*!< Nonperiodic transmit RAM start address */
+#define USB_OTG_NPTXFD 0xFFFF0000U /*!< Nonperiodic TxFIFO depth */
+#define USB_OTG_TX0FSA 0x0000FFFFU /*!< Endpoint 0 transmit RAM start address */
+#define USB_OTG_TX0FD 0xFFFF0000U /*!< Endpoint 0 TxFIFO depth */
+
+/******************** Bit definition for USB_OTG_DVBUSPULSE register ********************/
+#define USB_OTG_DVBUSPULSE_DVBUSP 0x00000FFFU /*!< Device VBUS pulsing time */
+
+/******************** Bit definition for USB_OTG_GNPTXSTS register ********************/
+#define USB_OTG_GNPTXSTS_NPTXFSAV 0x0000FFFFU /*!< Nonperiodic TxFIFO space available */
+
+#define USB_OTG_GNPTXSTS_NPTQXSAV 0x00FF0000U /*!< Nonperiodic transmit request queue space available */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_0 0x00010000U /*!<Bit 0 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_1 0x00020000U /*!<Bit 1 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_2 0x00040000U /*!<Bit 2 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_3 0x00080000U /*!<Bit 3 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_4 0x00100000U /*!<Bit 4 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_5 0x00200000U /*!<Bit 5 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_6 0x00400000U /*!<Bit 6 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_7 0x00800000U /*!<Bit 7 */
+
+#define USB_OTG_GNPTXSTS_NPTXQTOP 0x7F000000U /*!< Top of the nonperiodic transmit request queue */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_0 0x01000000U /*!<Bit 0 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_1 0x02000000U /*!<Bit 1 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_2 0x04000000U /*!<Bit 2 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_3 0x08000000U /*!<Bit 3 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_4 0x10000000U /*!<Bit 4 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_5 0x20000000U /*!<Bit 5 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_6 0x40000000U /*!<Bit 6 */
+
+/******************** Bit definition for USB_OTG_DTHRCTL register ********************/
+#define USB_OTG_DTHRCTL_NONISOTHREN 0x00000001U /*!< Nonisochronous IN endpoints threshold enable */
+#define USB_OTG_DTHRCTL_ISOTHREN 0x00000002U /*!< ISO IN endpoint threshold enable */
+
+#define USB_OTG_DTHRCTL_TXTHRLEN 0x000007FCU /*!< Transmit threshold length */
+#define USB_OTG_DTHRCTL_TXTHRLEN_0 0x00000004U /*!<Bit 0 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_1 0x00000008U /*!<Bit 1 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_2 0x00000010U /*!<Bit 2 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_3 0x00000020U /*!<Bit 3 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_4 0x00000040U /*!<Bit 4 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_5 0x00000080U /*!<Bit 5 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_6 0x00000100U /*!<Bit 6 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_7 0x00000200U /*!<Bit 7 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_8 0x00000400U /*!<Bit 8 */
+#define USB_OTG_DTHRCTL_RXTHREN 0x00010000U /*!< Receive threshold enable */
+
+#define USB_OTG_DTHRCTL_RXTHRLEN 0x03FE0000U /*!< Receive threshold length */
+#define USB_OTG_DTHRCTL_RXTHRLEN_0 0x00020000U /*!<Bit 0 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_1 0x00040000U /*!<Bit 1 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_2 0x00080000U /*!<Bit 2 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_3 0x00100000U /*!<Bit 3 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_4 0x00200000U /*!<Bit 4 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_5 0x00400000U /*!<Bit 5 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_6 0x00800000U /*!<Bit 6 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_7 0x01000000U /*!<Bit 7 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_8 0x02000000U /*!<Bit 8 */
+#define USB_OTG_DTHRCTL_ARPEN 0x08000000U /*!< Arbiter parking enable */
+
+/******************** Bit definition for USB_OTG_DIEPEMPMSK register ********************/
+#define USB_OTG_DIEPEMPMSK_INEPTXFEM 0x0000FFFFU /*!< IN EP Tx FIFO empty interrupt mask bits */
+
+/******************** Bit definition for USB_OTG_DEACHINT register ********************/
+#define USB_OTG_DEACHINT_IEP1INT 0x00000002U /*!< IN endpoint 1interrupt bit */
+#define USB_OTG_DEACHINT_OEP1INT 0x00020000U /*!< OUT endpoint 1 interrupt bit */
+
+/******************** Bit definition for USB_OTG_GCCFG register ********************/
+#define USB_OTG_GCCFG_PWRDWN 0x00010000U /*!< Power down */
+#define USB_OTG_GCCFG_VBDEN 0x00200000U /*!< USB VBUS Detection Enable */
+
+/******************** Bit definition for USB_OTG_DEACHINTMSK register ********************/
+#define USB_OTG_DEACHINTMSK_IEP1INTM 0x00000002U /*!< IN Endpoint 1 interrupt mask bit */
+#define USB_OTG_DEACHINTMSK_OEP1INTM 0x00020000U /*!< OUT Endpoint 1 interrupt mask bit */
+
+/******************** Bit definition for USB_OTG_CID register ********************/
+#define USB_OTG_CID_PRODUCT_ID 0xFFFFFFFFU /*!< Product ID field */
+
+/******************** Bit definition for USB_OTG_GLPMCFG register ********************/
+#define USB_OTG_GLPMCFG_LPMEN 0x00000001U /*!< LPM support enable */
+#define USB_OTG_GLPMCFG_LPMACK 0x00000002U /*!< LPM Token acknowledge enable */
+#define USB_OTG_GLPMCFG_BESL 0x0000003CU /*!< BESL value received with last ACKed LPM Token */
+#define USB_OTG_GLPMCFG_REMWAKE 0x00000040U /*!< bRemoteWake value received with last ACKed LPM Token */
+#define USB_OTG_GLPMCFG_L1SSEN 0x00000080U /*!< L1 shallow sleep enable */
+#define USB_OTG_GLPMCFG_BESLTHRS 0x00000F00U /*!< BESL threshold */
+#define USB_OTG_GLPMCFG_L1DSEN 0x00001000U /*!< L1 deep sleep enable */
+#define USB_OTG_GLPMCFG_LPMRSP 0x00006000U /*!< LPM response */
+#define USB_OTG_GLPMCFG_SLPSTS 0x00008000U /*!< Port sleep status */
+#define USB_OTG_GLPMCFG_L1RSMOK 0x00010000U /*!< Sleep State Resume OK */
+#define USB_OTG_GLPMCFG_LPMCHIDX 0x001E0000U /*!< LPM Channel Index */
+#define USB_OTG_GLPMCFG_LPMRCNT 0x00E00000U /*!< LPM retry count */
+#define USB_OTG_GLPMCFG_SNDLPM 0x01000000U /*!< Send LPM transaction */
+#define USB_OTG_GLPMCFG_LPMRCNTSTS 0x0E000000U /*!< LPM retry count status */
+#define USB_OTG_GLPMCFG_ENBESL 0x10000000U /*!< Enable best effort service latency */
+
+/******************** Bit definition for USB_OTG_DIEPEACHMSK1 register ********************/
+#define USB_OTG_DIEPEACHMSK1_XFRCM 0x00000001U /*!< Transfer completed interrupt mask */
+#define USB_OTG_DIEPEACHMSK1_EPDM 0x00000002U /*!< Endpoint disabled interrupt mask */
+#define USB_OTG_DIEPEACHMSK1_TOM 0x00000008U /*!< Timeout condition mask (nonisochronous endpoints) */
+#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK 0x00000010U /*!< IN token received when TxFIFO empty mask */
+#define USB_OTG_DIEPEACHMSK1_INEPNMM 0x00000020U /*!< IN token received with EP mismatch mask */
+#define USB_OTG_DIEPEACHMSK1_INEPNEM 0x00000040U /*!< IN endpoint NAK effective mask */
+#define USB_OTG_DIEPEACHMSK1_TXFURM 0x00000100U /*!< FIFO underrun mask */
+#define USB_OTG_DIEPEACHMSK1_BIM 0x00000200U /*!< BNA interrupt mask */
+#define USB_OTG_DIEPEACHMSK1_NAKM 0x00002000U /*!< NAK interrupt mask */
+
+/******************** Bit definition for USB_OTG_HPRT register ********************/
+#define USB_OTG_HPRT_PCSTS 0x00000001U /*!< Port connect status */
+#define USB_OTG_HPRT_PCDET 0x00000002U /*!< Port connect detected */
+#define USB_OTG_HPRT_PENA 0x00000004U /*!< Port enable */
+#define USB_OTG_HPRT_PENCHNG 0x00000008U /*!< Port enable/disable change */
+#define USB_OTG_HPRT_POCA 0x00000010U /*!< Port overcurrent active */
+#define USB_OTG_HPRT_POCCHNG 0x00000020U /*!< Port overcurrent change */
+#define USB_OTG_HPRT_PRES 0x00000040U /*!< Port resume */
+#define USB_OTG_HPRT_PSUSP 0x00000080U /*!< Port suspend */
+#define USB_OTG_HPRT_PRST 0x00000100U /*!< Port reset */
+
+#define USB_OTG_HPRT_PLSTS 0x00000C00U /*!< Port line status */
+#define USB_OTG_HPRT_PLSTS_0 0x00000400U /*!<Bit 0 */
+#define USB_OTG_HPRT_PLSTS_1 0x00000800U /*!<Bit 1 */
+#define USB_OTG_HPRT_PPWR 0x00001000U /*!< Port power */
+
+#define USB_OTG_HPRT_PTCTL 0x0001E000U /*!< Port test control */
+#define USB_OTG_HPRT_PTCTL_0 0x00002000U /*!<Bit 0 */
+#define USB_OTG_HPRT_PTCTL_1 0x00004000U /*!<Bit 1 */
+#define USB_OTG_HPRT_PTCTL_2 0x00008000U /*!<Bit 2 */
+#define USB_OTG_HPRT_PTCTL_3 0x00010000U /*!<Bit 3 */
+
+#define USB_OTG_HPRT_PSPD 0x00060000U /*!< Port speed */
+#define USB_OTG_HPRT_PSPD_0 0x00020000U /*!<Bit 0 */
+#define USB_OTG_HPRT_PSPD_1 0x00040000U /*!<Bit 1 */
+
+/******************** Bit definition for USB_OTG_DOEPEACHMSK1 register ********************/
+#define USB_OTG_DOEPEACHMSK1_XFRCM 0x00000001U /*!< Transfer completed interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_EPDM 0x00000002U /*!< Endpoint disabled interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_TOM 0x00000008U /*!< Timeout condition mask */
+#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK 0x00000010U /*!< IN token received when TxFIFO empty mask */
+#define USB_OTG_DOEPEACHMSK1_INEPNMM 0x00000020U /*!< IN token received with EP mismatch mask */
+#define USB_OTG_DOEPEACHMSK1_INEPNEM 0x00000040U /*!< IN endpoint NAK effective mask */
+#define USB_OTG_DOEPEACHMSK1_TXFURM 0x00000100U /*!< OUT packet error mask */
+#define USB_OTG_DOEPEACHMSK1_BIM 0x00000200U /*!< BNA interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_BERRM 0x00001000U /*!< Bubble error interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_NAKM 0x00002000U /*!< NAK interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_NYETM 0x00004000U /*!< NYET interrupt mask */
+
+/******************** Bit definition for USB_OTG_HPTXFSIZ register ********************/
+#define USB_OTG_HPTXFSIZ_PTXSA 0x0000FFFFU /*!< Host periodic TxFIFO start address */
+#define USB_OTG_HPTXFSIZ_PTXFD 0xFFFF0000U /*!< Host periodic TxFIFO depth */
+
+/******************** Bit definition for USB_OTG_DIEPCTL register ********************/
+#define USB_OTG_DIEPCTL_MPSIZ 0x000007FFU /*!< Maximum packet size */
+#define USB_OTG_DIEPCTL_USBAEP 0x00008000U /*!< USB active endpoint */
+#define USB_OTG_DIEPCTL_EONUM_DPID 0x00010000U /*!< Even/odd frame */
+#define USB_OTG_DIEPCTL_NAKSTS 0x00020000U /*!< NAK status */
+
+#define USB_OTG_DIEPCTL_EPTYP 0x000C0000U /*!< Endpoint type */
+#define USB_OTG_DIEPCTL_EPTYP_0 0x00040000U /*!<Bit 0 */
+#define USB_OTG_DIEPCTL_EPTYP_1 0x00080000U /*!<Bit 1 */
+#define USB_OTG_DIEPCTL_STALL 0x00200000U /*!< STALL handshake */
+
+#define USB_OTG_DIEPCTL_TXFNUM 0x03C00000U /*!< TxFIFO number */
+#define USB_OTG_DIEPCTL_TXFNUM_0 0x00400000U /*!<Bit 0 */
+#define USB_OTG_DIEPCTL_TXFNUM_1 0x00800000U /*!<Bit 1 */
+#define USB_OTG_DIEPCTL_TXFNUM_2 0x01000000U /*!<Bit 2 */
+#define USB_OTG_DIEPCTL_TXFNUM_3 0x02000000U /*!<Bit 3 */
+#define USB_OTG_DIEPCTL_CNAK 0x04000000U /*!< Clear NAK */
+#define USB_OTG_DIEPCTL_SNAK 0x08000000U /*!< Set NAK */
+#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM 0x10000000U /*!< Set DATA0 PID */
+#define USB_OTG_DIEPCTL_SODDFRM 0x20000000U /*!< Set odd frame */
+#define USB_OTG_DIEPCTL_EPDIS 0x40000000U /*!< Endpoint disable */
+#define USB_OTG_DIEPCTL_EPENA 0x80000000U /*!< Endpoint enable */
+
+/******************** Bit definition for USB_OTG_HCCHAR register ********************/
+#define USB_OTG_HCCHAR_MPSIZ 0x000007FFU /*!< Maximum packet size */
+
+#define USB_OTG_HCCHAR_EPNUM 0x00007800U /*!< Endpoint number */
+#define USB_OTG_HCCHAR_EPNUM_0 0x00000800U /*!<Bit 0 */
+#define USB_OTG_HCCHAR_EPNUM_1 0x00001000U /*!<Bit 1 */
+#define USB_OTG_HCCHAR_EPNUM_2 0x00002000U /*!<Bit 2 */
+#define USB_OTG_HCCHAR_EPNUM_3 0x00004000U /*!<Bit 3 */
+#define USB_OTG_HCCHAR_EPDIR 0x00008000U /*!< Endpoint direction */
+#define USB_OTG_HCCHAR_LSDEV 0x00020000U /*!< Low-speed device */
+
+#define USB_OTG_HCCHAR_EPTYP 0x000C0000U /*!< Endpoint type */
+#define USB_OTG_HCCHAR_EPTYP_0 0x00040000U /*!<Bit 0 */
+#define USB_OTG_HCCHAR_EPTYP_1 0x00080000U /*!<Bit 1 */
+
+#define USB_OTG_HCCHAR_MC 0x00300000U /*!< Multi Count (MC) / Error Count (EC) */
+#define USB_OTG_HCCHAR_MC_0 0x00100000U /*!<Bit 0 */
+#define USB_OTG_HCCHAR_MC_1 0x00200000U /*!<Bit 1 */
+
+#define USB_OTG_HCCHAR_DAD 0x1FC00000U /*!< Device address */
+#define USB_OTG_HCCHAR_DAD_0 0x00400000U /*!<Bit 0 */
+#define USB_OTG_HCCHAR_DAD_1 0x00800000U /*!<Bit 1 */
+#define USB_OTG_HCCHAR_DAD_2 0x01000000U /*!<Bit 2 */
+#define USB_OTG_HCCHAR_DAD_3 0x02000000U /*!<Bit 3 */
+#define USB_OTG_HCCHAR_DAD_4 0x04000000U /*!<Bit 4 */
+#define USB_OTG_HCCHAR_DAD_5 0x08000000U /*!<Bit 5 */
+#define USB_OTG_HCCHAR_DAD_6 0x10000000U /*!<Bit 6 */
+#define USB_OTG_HCCHAR_ODDFRM 0x20000000U /*!< Odd frame */
+#define USB_OTG_HCCHAR_CHDIS 0x40000000U /*!< Channel disable */
+#define USB_OTG_HCCHAR_CHENA 0x80000000U /*!< Channel enable */
+
+/******************** Bit definition for USB_OTG_HCSPLT register ********************/
+
+#define USB_OTG_HCSPLT_PRTADDR 0x0000007FU /*!< Port address */
+#define USB_OTG_HCSPLT_PRTADDR_0 0x00000001U /*!<Bit 0 */
+#define USB_OTG_HCSPLT_PRTADDR_1 0x00000002U /*!<Bit 1 */
+#define USB_OTG_HCSPLT_PRTADDR_2 0x00000004U /*!<Bit 2 */
+#define USB_OTG_HCSPLT_PRTADDR_3 0x00000008U /*!<Bit 3 */
+#define USB_OTG_HCSPLT_PRTADDR_4 0x00000010U /*!<Bit 4 */
+#define USB_OTG_HCSPLT_PRTADDR_5 0x00000020U /*!<Bit 5 */
+#define USB_OTG_HCSPLT_PRTADDR_6 0x00000040U /*!<Bit 6 */
+
+#define USB_OTG_HCSPLT_HUBADDR 0x00003F80U /*!< Hub address */
+#define USB_OTG_HCSPLT_HUBADDR_0 0x00000080U /*!<Bit 0 */
+#define USB_OTG_HCSPLT_HUBADDR_1 0x00000100U /*!<Bit 1 */
+#define USB_OTG_HCSPLT_HUBADDR_2 0x00000200U /*!<Bit 2 */
+#define USB_OTG_HCSPLT_HUBADDR_3 0x00000400U /*!<Bit 3 */
+#define USB_OTG_HCSPLT_HUBADDR_4 0x00000800U /*!<Bit 4 */
+#define USB_OTG_HCSPLT_HUBADDR_5 0x00001000U /*!<Bit 5 */
+#define USB_OTG_HCSPLT_HUBADDR_6 0x00002000U /*!<Bit 6 */
+
+#define USB_OTG_HCSPLT_XACTPOS 0x0000C000U /*!< XACTPOS */
+#define USB_OTG_HCSPLT_XACTPOS_0 0x00004000U /*!<Bit 0 */
+#define USB_OTG_HCSPLT_XACTPOS_1 0x00008000U /*!<Bit 1 */
+#define USB_OTG_HCSPLT_COMPLSPLT 0x00010000U /*!< Do complete split */
+#define USB_OTG_HCSPLT_SPLITEN 0x80000000U /*!< Split enable */
+
+/******************** Bit definition for USB_OTG_HCINT register ********************/
+#define USB_OTG_HCINT_XFRC 0x00000001U /*!< Transfer completed */
+#define USB_OTG_HCINT_CHH 0x00000002U /*!< Channel halted */
+#define USB_OTG_HCINT_AHBERR 0x00000004U /*!< AHB error */
+#define USB_OTG_HCINT_STALL 0x00000008U /*!< STALL response received interrupt */
+#define USB_OTG_HCINT_NAK 0x00000010U /*!< NAK response received interrupt */
+#define USB_OTG_HCINT_ACK 0x00000020U /*!< ACK response received/transmitted interrupt */
+#define USB_OTG_HCINT_NYET 0x00000040U /*!< Response received interrupt */
+#define USB_OTG_HCINT_TXERR 0x00000080U /*!< Transaction error */
+#define USB_OTG_HCINT_BBERR 0x00000100U /*!< Babble error */
+#define USB_OTG_HCINT_FRMOR 0x00000200U /*!< Frame overrun */
+#define USB_OTG_HCINT_DTERR 0x00000400U /*!< Data toggle error */
+
+/******************** Bit definition for USB_OTG_DIEPINT register ********************/
+#define USB_OTG_DIEPINT_XFRC 0x00000001U /*!< Transfer completed interrupt */
+#define USB_OTG_DIEPINT_EPDISD 0x00000002U /*!< Endpoint disabled interrupt */
+#define USB_OTG_DIEPINT_TOC 0x00000008U /*!< Timeout condition */
+#define USB_OTG_DIEPINT_ITTXFE 0x00000010U /*!< IN token received when TxFIFO is empty */
+#define USB_OTG_DIEPINT_INEPNE 0x00000040U /*!< IN endpoint NAK effective */
+#define USB_OTG_DIEPINT_TXFE 0x00000080U /*!< Transmit FIFO empty */
+#define USB_OTG_DIEPINT_TXFIFOUDRN 0x00000100U /*!< Transmit Fifo Underrun */
+#define USB_OTG_DIEPINT_BNA 0x00000200U /*!< Buffer not available interrupt */
+#define USB_OTG_DIEPINT_PKTDRPSTS 0x00000800U /*!< Packet dropped status */
+#define USB_OTG_DIEPINT_BERR 0x00001000U /*!< Babble error interrupt */
+#define USB_OTG_DIEPINT_NAK 0x00002000U /*!< NAK interrupt */
+
+/******************** Bit definition for USB_OTG_HCINTMSK register ********************/
+#define USB_OTG_HCINTMSK_XFRCM 0x00000001U /*!< Transfer completed mask */
+#define USB_OTG_HCINTMSK_CHHM 0x00000002U /*!< Channel halted mask */
+#define USB_OTG_HCINTMSK_AHBERR 0x00000004U /*!< AHB error */
+#define USB_OTG_HCINTMSK_STALLM 0x00000008U /*!< STALL response received interrupt mask */
+#define USB_OTG_HCINTMSK_NAKM 0x00000010U /*!< NAK response received interrupt mask */
+#define USB_OTG_HCINTMSK_ACKM 0x00000020U /*!< ACK response received/transmitted interrupt mask */
+#define USB_OTG_HCINTMSK_NYET 0x00000040U /*!< response received interrupt mask */
+#define USB_OTG_HCINTMSK_TXERRM 0x00000080U /*!< Transaction error mask */
+#define USB_OTG_HCINTMSK_BBERRM 0x00000100U /*!< Babble error mask */
+#define USB_OTG_HCINTMSK_FRMORM 0x00000200U /*!< Frame overrun mask */
+#define USB_OTG_HCINTMSK_DTERRM 0x00000400U /*!< Data toggle error mask */
+
+/******************** Bit definition for USB_OTG_DIEPTSIZ register ********************/
+
+#define USB_OTG_DIEPTSIZ_XFRSIZ 0x0007FFFFU /*!< Transfer size */
+#define USB_OTG_DIEPTSIZ_PKTCNT 0x1FF80000U /*!< Packet count */
+#define USB_OTG_DIEPTSIZ_MULCNT 0x60000000U /*!< Packet count */
+/******************** Bit definition for USB_OTG_HCTSIZ register ********************/
+#define USB_OTG_HCTSIZ_XFRSIZ 0x0007FFFFU /*!< Transfer size */
+#define USB_OTG_HCTSIZ_PKTCNT 0x1FF80000U /*!< Packet count */
+#define USB_OTG_HCTSIZ_DOPING 0x80000000U /*!< Do PING */
+#define USB_OTG_HCTSIZ_DPID 0x60000000U /*!< Data PID */
+#define USB_OTG_HCTSIZ_DPID_0 0x20000000U /*!<Bit 0 */
+#define USB_OTG_HCTSIZ_DPID_1 0x40000000U /*!<Bit 1 */
+
+/******************** Bit definition for USB_OTG_DIEPDMA register ********************/
+#define USB_OTG_DIEPDMA_DMAADDR 0xFFFFFFFFU /*!< DMA address */
+
+/******************** Bit definition for USB_OTG_HCDMA register ********************/
+#define USB_OTG_HCDMA_DMAADDR 0xFFFFFFFFU /*!< DMA address */
+
+/******************** Bit definition for USB_OTG_DTXFSTS register ********************/
+#define USB_OTG_DTXFSTS_INEPTFSAV 0x0000FFFFU /*!< IN endpoint TxFIFO space available */
+
+/******************** Bit definition for USB_OTG_DIEPTXF register ********************/
+#define USB_OTG_DIEPTXF_INEPTXSA 0x0000FFFFU /*!< IN endpoint FIFOx transmit RAM start address */
+#define USB_OTG_DIEPTXF_INEPTXFD 0xFFFF0000U /*!< IN endpoint TxFIFO depth */
+
+/******************** Bit definition for USB_OTG_DOEPCTL register ********************/
+
+#define USB_OTG_DOEPCTL_MPSIZ 0x000007FFU /*!< Maximum packet size */ /*!<Bit 1 */
+#define USB_OTG_DOEPCTL_USBAEP 0x00008000U /*!< USB active endpoint */
+#define USB_OTG_DOEPCTL_NAKSTS 0x00020000U /*!< NAK status */
+#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM 0x10000000U /*!< Set DATA0 PID */
+#define USB_OTG_DOEPCTL_SODDFRM 0x20000000U /*!< Set odd frame */
+#define USB_OTG_DOEPCTL_EPTYP 0x000C0000U /*!< Endpoint type */
+#define USB_OTG_DOEPCTL_EPTYP_0 0x00040000U /*!<Bit 0 */
+#define USB_OTG_DOEPCTL_EPTYP_1 0x00080000U /*!<Bit 1 */
+#define USB_OTG_DOEPCTL_SNPM 0x00100000U /*!< Snoop mode */
+#define USB_OTG_DOEPCTL_STALL 0x00200000U /*!< STALL handshake */
+#define USB_OTG_DOEPCTL_CNAK 0x04000000U /*!< Clear NAK */
+#define USB_OTG_DOEPCTL_SNAK 0x08000000U /*!< Set NAK */
+#define USB_OTG_DOEPCTL_EPDIS 0x40000000U /*!< Endpoint disable */
+#define USB_OTG_DOEPCTL_EPENA 0x80000000U /*!< Endpoint enable */
+
+/******************** Bit definition for USB_OTG_DOEPINT register ********************/
+#define USB_OTG_DOEPINT_XFRC 0x00000001U /*!< Transfer completed interrupt */
+#define USB_OTG_DOEPINT_EPDISD 0x00000002U /*!< Endpoint disabled interrupt */
+#define USB_OTG_DOEPINT_STUP 0x00000008U /*!< SETUP phase done */
+#define USB_OTG_DOEPINT_OTEPDIS 0x00000010U /*!< OUT token received when endpoint disabled */
+#define USB_OTG_DOEPINT_OTEPSPR 0x00000020U /*!< Status Phase Received For Control Write */
+#define USB_OTG_DOEPINT_B2BSTUP 0x00000040U /*!< Back-to-back SETUP packets received */
+#define USB_OTG_DOEPINT_NYET 0x00004000U /*!< NYET interrupt */
+
+/******************** Bit definition for USB_OTG_DOEPTSIZ register ********************/
+
+#define USB_OTG_DOEPTSIZ_XFRSIZ 0x0007FFFFU /*!< Transfer size */
+#define USB_OTG_DOEPTSIZ_PKTCNT 0x1FF80000U /*!< Packet count */
+
+#define USB_OTG_DOEPTSIZ_STUPCNT 0x60000000U /*!< SETUP packet count */
+#define USB_OTG_DOEPTSIZ_STUPCNT_0 0x20000000U /*!<Bit 0 */
+#define USB_OTG_DOEPTSIZ_STUPCNT_1 0x40000000U /*!<Bit 1 */
+
+/******************** Bit definition for PCGCCTL register ********************/
+#define USB_OTG_PCGCCTL_STOPCLK 0x00000001U /*!< SETUP packet count */
+#define USB_OTG_PCGCCTL_GATECLK 0x00000002U /*!<Bit 0 */
+#define USB_OTG_PCGCCTL_PHYSUSP 0x00000010U /*!<Bit 1 */
+
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup Exported_macros
+ * @{
+ */
+
+/******************************* ADC Instances ********************************/
+#define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) || \
+ ((INSTANCE) == ADC2) || \
+ ((INSTANCE) == ADC3))
+
+/******************************* CAN Instances ********************************/
+#define IS_CAN_ALL_INSTANCE(INSTANCE) (((INSTANCE) == CAN1) || \
+ ((INSTANCE) == CAN2))
+
+/******************************* CRC Instances ********************************/
+#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
+
+/******************************* DAC Instances ********************************/
+#define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC)
+
+/******************************* DCMI Instances *******************************/
+#define IS_DCMI_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DCMI)
+
+/******************************** DMA Instances *******************************/
+#define IS_DMA_STREAM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0) || \
+ ((INSTANCE) == DMA1_Stream1) || \
+ ((INSTANCE) == DMA1_Stream2) || \
+ ((INSTANCE) == DMA1_Stream3) || \
+ ((INSTANCE) == DMA1_Stream4) || \
+ ((INSTANCE) == DMA1_Stream5) || \
+ ((INSTANCE) == DMA1_Stream6) || \
+ ((INSTANCE) == DMA1_Stream7) || \
+ ((INSTANCE) == DMA2_Stream0) || \
+ ((INSTANCE) == DMA2_Stream1) || \
+ ((INSTANCE) == DMA2_Stream2) || \
+ ((INSTANCE) == DMA2_Stream3) || \
+ ((INSTANCE) == DMA2_Stream4) || \
+ ((INSTANCE) == DMA2_Stream5) || \
+ ((INSTANCE) == DMA2_Stream6) || \
+ ((INSTANCE) == DMA2_Stream7))
+
+/******************************* GPIO Instances *******************************/
+#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
+ ((INSTANCE) == GPIOB) || \
+ ((INSTANCE) == GPIOC) || \
+ ((INSTANCE) == GPIOD) || \
+ ((INSTANCE) == GPIOE) || \
+ ((INSTANCE) == GPIOF) || \
+ ((INSTANCE) == GPIOG) || \
+ ((INSTANCE) == GPIOH))
+
+/******************************** I2C Instances *******************************/
+#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
+ ((INSTANCE) == I2C2) || \
+ ((INSTANCE) == I2C3))
+
+/******************************** I2S Instances *******************************/
+#define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
+ ((INSTANCE) == SPI2) || \
+ ((INSTANCE) == SPI3))
+
+/****************************** RTC Instances *********************************/
+#define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
+
+/******************************* SAI Instances ********************************/
+#define IS_SAI_ALL_INSTANCE(PERIPH) (((PERIPH) == SAI1_Block_A) || \
+ ((PERIPH) == SAI1_Block_B) || \
+ ((PERIPH) == SAI2_Block_A) || \
+ ((PERIPH) == SAI2_Block_B))
+/* Legacy define */
+#define IS_SAI_BLOCK_PERIPH IS_SAI_ALL_INSTANCE
+
+/******************************** SPI Instances *******************************/
+#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
+ ((INSTANCE) == SPI2) || \
+ ((INSTANCE) == SPI3) || \
+ ((INSTANCE) == SPI4))
+
+/****************** TIM Instances : All supported instances *******************/
+#define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM6) || \
+ ((INSTANCE) == TIM7) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM9) || \
+ ((INSTANCE) == TIM10) || \
+ ((INSTANCE) == TIM11) || \
+ ((INSTANCE) == TIM12) || \
+ ((INSTANCE) == TIM13) || \
+ ((INSTANCE) == TIM14))
+
+/************* TIM Instances : at least 1 capture/compare channel *************/
+#define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM9) || \
+ ((INSTANCE) == TIM10) || \
+ ((INSTANCE) == TIM11) || \
+ ((INSTANCE) == TIM12) || \
+ ((INSTANCE) == TIM13) || \
+ ((INSTANCE) == TIM14))
+
+/************ TIM Instances : at least 2 capture/compare channels *************/
+#define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM9) || \
+ ((INSTANCE) == TIM12))
+
+/************ TIM Instances : at least 3 capture/compare channels *************/
+#define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8))
+
+/************ TIM Instances : at least 4 capture/compare channels *************/
+#define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8))
+
+/******************** TIM Instances : Advanced-control timers *****************/
+#define IS_TIM_ADVANCED_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM8))
+
+/******************* TIM Instances : Timer input XOR function *****************/
+#define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8))
+
+/****************** TIM Instances : DMA requests generation (UDE) *************/
+#define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM6) || \
+ ((INSTANCE) == TIM7) || \
+ ((INSTANCE) == TIM8))
+
+/************ TIM Instances : DMA requests generation (CCxDE) *****************/
+#define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8))
+
+/************ TIM Instances : DMA requests generation (COMDE) *****************/
+#define IS_TIM_CCDMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8))
+
+/******************** TIM Instances : DMA burst feature ***********************/
+#define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8))
+
+/****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/
+#define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM6) || \
+ ((INSTANCE) == TIM7) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM9) || \
+ ((INSTANCE) == TIM12))
+
+/*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
+#define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM9) || \
+ ((INSTANCE) == TIM12))
+
+/********************** TIM Instances : 32 bit Counter ************************/
+#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)(((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM5))
+
+/***************** TIM Instances : external trigger input availabe ************/
+#define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8))
+
+/****************** TIM Instances : remapping capability **********************/
+#define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM11))
+
+/******************* TIM Instances : output(s) available **********************/
+#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
+ ((((INSTANCE) == TIM1) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM2) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM3) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM4) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM5) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM8) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM9) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2))) \
+ || \
+ (((INSTANCE) == TIM10) && \
+ (((CHANNEL) == TIM_CHANNEL_1))) \
+ || \
+ (((INSTANCE) == TIM11) && \
+ (((CHANNEL) == TIM_CHANNEL_1))) \
+ || \
+ (((INSTANCE) == TIM12) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2))) \
+ || \
+ (((INSTANCE) == TIM13) && \
+ (((CHANNEL) == TIM_CHANNEL_1))) \
+ || \
+ (((INSTANCE) == TIM14) && \
+ (((CHANNEL) == TIM_CHANNEL_1))))
+
+/************ TIM Instances : complementary output(s) available ***************/
+#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
+ ((((INSTANCE) == TIM1) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3))) \
+ || \
+ (((INSTANCE) == TIM8) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3))))
+
+/******************** USART Instances : Synchronous mode **********************/
+#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3) || \
+ ((INSTANCE) == USART6))
+
+/******************** UART Instances : Asynchronous mode **********************/
+#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3) || \
+ ((INSTANCE) == UART4) || \
+ ((INSTANCE) == UART5) || \
+ ((INSTANCE) == USART6))
+
+/****************** UART Instances : Hardware Flow control ********************/
+#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3) || \
+ ((INSTANCE) == USART6))
+
+/********************* UART Instances : Smard card mode ***********************/
+#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3) || \
+ ((INSTANCE) == USART6))
+
+/*********************** UART Instances : IRDA mode ***************************/
+#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3) || \
+ ((INSTANCE) == UART4) || \
+ ((INSTANCE) == UART5) || \
+ ((INSTANCE) == USART6))
+
+/*********************** PCD Instances ****************************************/
+#define IS_PCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS) || \
+ ((INSTANCE) == USB_OTG_HS))
+
+/*********************** HCD Instances ****************************************/
+#define IS_HCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS) || \
+ ((INSTANCE) == USB_OTG_HS))
+
+/****************************** SDIO Instances ********************************/
+#define IS_SDIO_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SDIO)
+
+/****************************** IWDG Instances ********************************/
+#define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
+
+/****************************** WWDG Instances ********************************/
+#define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
+
+/****************************** QSPI Instances ********************************/
+#define IS_QSPI_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == QUADSPI)
+
+/******************************* CEC Instances ********************************/
+#define IS_CEC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == CEC)
+
+/***************************** FMPI2C Instances *******************************/
+#define IS_FMPI2C_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == FMPI2C1)
+
+/******************************* SPDIFRX Instances ********************************/
+#define IS_SPDIFRX_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SPDIFRX)
+
+/****************************** USB Exported Constants ************************/
+#define USB_OTG_FS_HOST_MAX_CHANNEL_NBR 8U
+#define USB_OTG_FS_MAX_IN_ENDPOINTS 5U /* Including EP0 */
+#define USB_OTG_FS_MAX_OUT_ENDPOINTS 5U /* Including EP0 */
+#define USB_OTG_FS_TOTAL_FIFO_SIZE 1280U /* in Bytes */
+
+#define USB_OTG_HS_HOST_MAX_CHANNEL_NBR 16U
+#define USB_OTG_HS_MAX_IN_ENDPOINTS 8U /* Including EP0 */
+#define USB_OTG_HS_MAX_OUT_ENDPOINTS 8U /* Including EP0 */
+#define USB_OTG_HS_TOTAL_FIFO_SIZE 4096U /* in Bytes */
+
+/******************************************************************************/
+/* For a painless codes migration between the STM32F4xx device product */
+/* lines, the aliases defined below are put in place to overcome the */
+/* differences in the interrupt handlers and IRQn definitions. */
+/* No need to update developed interrupt code when moving across */
+/* product lines within the same STM32F4 Family */
+/******************************************************************************/
+
+/* Aliases for __IRQHandler */
+#define QuadSPI_IRQHandler QUADSPI_IRQHandler
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* __STM32F446xx_H */
+
+
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Device/ST/STM32F4xx/Include/stm32f469xx.h b/Device/ST/STM32F4xx/Include/stm32f469xx.h
new file mode 100644
index 0000000..eeab9a7
--- /dev/null
+++ b/Device/ST/STM32F4xx/Include/stm32f469xx.h
@@ -0,0 +1,10250 @@
+/**
+ ******************************************************************************
+ * @file stm32f469xx.h
+ * @author MCD Application Team
+ * @version V2.5.0
+ * @date 22-April-2016
+ * @brief CMSIS STM32F469xx Device Peripheral Access Layer Header File.
+ *
+ * This file contains:
+ * - Data structures and the address mapping for all peripherals
+ * - peripherals registers declarations and bits definition
+ * - Macros to access peripheral’s registers hardware
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/** @addtogroup CMSIS_Device
+ * @{
+ */
+
+/** @addtogroup stm32f469xx
+ * @{
+ */
+
+#ifndef __STM32F469xx_H
+#define __STM32F469xx_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif /* __cplusplus */
+
+/** @addtogroup Configuration_section_for_CMSIS
+ * @{
+ */
+
+/**
+ * @brief Configuration of the Cortex-M4 Processor and Core Peripherals
+ */
+#define __CM4_REV 0x0001U /*!< Core revision r0p1 */
+#define __MPU_PRESENT 1U /*!< STM32F4XX provides an MPU */
+#define __NVIC_PRIO_BITS 4U /*!< STM32F4XX uses 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */
+#define __FPU_PRESENT 1U /*!< FPU present */
+
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_interrupt_number_definition
+ * @{
+ */
+
+/**
+ * @brief STM32F4XX Interrupt Number Definition, according to the selected device
+ * in @ref Library_configuration_section
+ */
+typedef enum
+{
+/****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/
+ NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
+ MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */
+ BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */
+ UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */
+ SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */
+ DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */
+ PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */
+ SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */
+/****** STM32 specific Interrupt Numbers **********************************************************************/
+ WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
+ PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */
+ TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */
+ RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */
+ FLASH_IRQn = 4, /*!< FLASH global Interrupt */
+ RCC_IRQn = 5, /*!< RCC global Interrupt */
+ EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */
+ EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */
+ EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */
+ EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */
+ EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */
+ DMA1_Stream0_IRQn = 11, /*!< DMA1 Stream 0 global Interrupt */
+ DMA1_Stream1_IRQn = 12, /*!< DMA1 Stream 1 global Interrupt */
+ DMA1_Stream2_IRQn = 13, /*!< DMA1 Stream 2 global Interrupt */
+ DMA1_Stream3_IRQn = 14, /*!< DMA1 Stream 3 global Interrupt */
+ DMA1_Stream4_IRQn = 15, /*!< DMA1 Stream 4 global Interrupt */
+ DMA1_Stream5_IRQn = 16, /*!< DMA1 Stream 5 global Interrupt */
+ DMA1_Stream6_IRQn = 17, /*!< DMA1 Stream 6 global Interrupt */
+ ADC_IRQn = 18, /*!< ADC1, ADC2 and ADC3 global Interrupts */
+ CAN1_TX_IRQn = 19, /*!< CAN1 TX Interrupt */
+ CAN1_RX0_IRQn = 20, /*!< CAN1 RX0 Interrupt */
+ CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */
+ CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */
+ EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
+ TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break interrupt and TIM9 global interrupt */
+ TIM1_UP_TIM10_IRQn = 25, /*!< TIM1 Update Interrupt and TIM10 global interrupt */
+ TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */
+ TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
+ TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
+ TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
+ TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
+ I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
+ I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
+ I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
+ I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
+ SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
+ SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
+ USART1_IRQn = 37, /*!< USART1 global Interrupt */
+ USART2_IRQn = 38, /*!< USART2 global Interrupt */
+ USART3_IRQn = 39, /*!< USART3 global Interrupt */
+ EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
+ RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */
+ OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS Wakeup through EXTI line interrupt */
+ TIM8_BRK_TIM12_IRQn = 43, /*!< TIM8 Break Interrupt and TIM12 global interrupt */
+ TIM8_UP_TIM13_IRQn = 44, /*!< TIM8 Update Interrupt and TIM13 global interrupt */
+ TIM8_TRG_COM_TIM14_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */
+ TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare global interrupt */
+ DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */
+ FMC_IRQn = 48, /*!< FMC global Interrupt */
+ SDIO_IRQn = 49, /*!< SDIO global Interrupt */
+ TIM5_IRQn = 50, /*!< TIM5 global Interrupt */
+ SPI3_IRQn = 51, /*!< SPI3 global Interrupt */
+ UART4_IRQn = 52, /*!< UART4 global Interrupt */
+ UART5_IRQn = 53, /*!< UART5 global Interrupt */
+ TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC1&2 underrun error interrupts */
+ TIM7_IRQn = 55, /*!< TIM7 global interrupt */
+ DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */
+ DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */
+ DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */
+ DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */
+ DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */
+ ETH_IRQn = 61, /*!< Ethernet global Interrupt */
+ ETH_WKUP_IRQn = 62, /*!< Ethernet Wakeup through EXTI line Interrupt */
+ CAN2_TX_IRQn = 63, /*!< CAN2 TX Interrupt */
+ CAN2_RX0_IRQn = 64, /*!< CAN2 RX0 Interrupt */
+ CAN2_RX1_IRQn = 65, /*!< CAN2 RX1 Interrupt */
+ CAN2_SCE_IRQn = 66, /*!< CAN2 SCE Interrupt */
+ OTG_FS_IRQn = 67, /*!< USB OTG FS global Interrupt */
+ DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */
+ DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */
+ DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */
+ USART6_IRQn = 71, /*!< USART6 global interrupt */
+ I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */
+ I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */
+ OTG_HS_EP1_OUT_IRQn = 74, /*!< USB OTG HS End Point 1 Out global interrupt */
+ OTG_HS_EP1_IN_IRQn = 75, /*!< USB OTG HS End Point 1 In global interrupt */
+ OTG_HS_WKUP_IRQn = 76, /*!< USB OTG HS Wakeup through EXTI interrupt */
+ OTG_HS_IRQn = 77, /*!< USB OTG HS global interrupt */
+ DCMI_IRQn = 78, /*!< DCMI global interrupt */
+ HASH_RNG_IRQn = 80, /*!< Hash and Rng global interrupt */
+ FPU_IRQn = 81, /*!< FPU global interrupt */
+ UART7_IRQn = 82, /*!< UART7 global interrupt */
+ UART8_IRQn = 83, /*!< UART8 global interrupt */
+ SPI4_IRQn = 84, /*!< SPI4 global Interrupt */
+ SPI5_IRQn = 85, /*!< SPI5 global Interrupt */
+ SPI6_IRQn = 86, /*!< SPI6 global Interrupt */
+ SAI1_IRQn = 87, /*!< SAI1 global Interrupt */
+ LTDC_IRQn = 88, /*!< LTDC global Interrupt */
+ LTDC_ER_IRQn = 89, /*!< LTDC Error global Interrupt */
+ DMA2D_IRQn = 90, /*!< DMA2D global Interrupt */
+ QUADSPI_IRQn = 91, /*!< QUADSPI global Interrupt */
+ DSI_IRQn = 92 /*!< DSI global Interrupt */
+} IRQn_Type;
+
+/**
+ * @}
+ */
+
+#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
+#include "system_stm32f4xx.h"
+#include <stdint.h>
+
+/** @addtogroup Peripheral_registers_structures
+ * @{
+ */
+
+/**
+ * @brief Analog to Digital Converter
+ */
+
+typedef struct
+{
+ __IO uint32_t SR; /*!< ADC status register, Address offset: 0x00 */
+ __IO uint32_t CR1; /*!< ADC control register 1, Address offset: 0x04 */
+ __IO uint32_t CR2; /*!< ADC control register 2, Address offset: 0x08 */
+ __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x0C */
+ __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x10 */
+ __IO uint32_t JOFR1; /*!< ADC injected channel data offset register 1, Address offset: 0x14 */
+ __IO uint32_t JOFR2; /*!< ADC injected channel data offset register 2, Address offset: 0x18 */
+ __IO uint32_t JOFR3; /*!< ADC injected channel data offset register 3, Address offset: 0x1C */
+ __IO uint32_t JOFR4; /*!< ADC injected channel data offset register 4, Address offset: 0x20 */
+ __IO uint32_t HTR; /*!< ADC watchdog higher threshold register, Address offset: 0x24 */
+ __IO uint32_t LTR; /*!< ADC watchdog lower threshold register, Address offset: 0x28 */
+ __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x2C */
+ __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x30 */
+ __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x34 */
+ __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x38*/
+ __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x3C */
+ __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x40 */
+ __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x44 */
+ __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x48 */
+ __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x4C */
+} ADC_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1 base address + 0x300 */
+ __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1 base address + 0x304 */
+ __IO uint32_t CDR; /*!< ADC common regular data register for dual
+ AND triple modes, Address offset: ADC1 base address + 0x308 */
+} ADC_Common_TypeDef;
+
+
+/**
+ * @brief Controller Area Network TxMailBox
+ */
+
+typedef struct
+{
+ __IO uint32_t TIR; /*!< CAN TX mailbox identifier register */
+ __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */
+ __IO uint32_t TDLR; /*!< CAN mailbox data low register */
+ __IO uint32_t TDHR; /*!< CAN mailbox data high register */
+} CAN_TxMailBox_TypeDef;
+
+/**
+ * @brief Controller Area Network FIFOMailBox
+ */
+
+typedef struct
+{
+ __IO uint32_t RIR; /*!< CAN receive FIFO mailbox identifier register */
+ __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */
+ __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */
+ __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */
+} CAN_FIFOMailBox_TypeDef;
+
+/**
+ * @brief Controller Area Network FilterRegister
+ */
+
+typedef struct
+{
+ __IO uint32_t FR1; /*!< CAN Filter bank register 1 */
+ __IO uint32_t FR2; /*!< CAN Filter bank register 1 */
+} CAN_FilterRegister_TypeDef;
+
+/**
+ * @brief Controller Area Network
+ */
+
+typedef struct
+{
+ __IO uint32_t MCR; /*!< CAN master control register, Address offset: 0x00 */
+ __IO uint32_t MSR; /*!< CAN master status register, Address offset: 0x04 */
+ __IO uint32_t TSR; /*!< CAN transmit status register, Address offset: 0x08 */
+ __IO uint32_t RF0R; /*!< CAN receive FIFO 0 register, Address offset: 0x0C */
+ __IO uint32_t RF1R; /*!< CAN receive FIFO 1 register, Address offset: 0x10 */
+ __IO uint32_t IER; /*!< CAN interrupt enable register, Address offset: 0x14 */
+ __IO uint32_t ESR; /*!< CAN error status register, Address offset: 0x18 */
+ __IO uint32_t BTR; /*!< CAN bit timing register, Address offset: 0x1C */
+ uint32_t RESERVED0[88]; /*!< Reserved, 0x020 - 0x17F */
+ CAN_TxMailBox_TypeDef sTxMailBox[3]; /*!< CAN Tx MailBox, Address offset: 0x180 - 0x1AC */
+ CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; /*!< CAN FIFO MailBox, Address offset: 0x1B0 - 0x1CC */
+ uint32_t RESERVED1[12]; /*!< Reserved, 0x1D0 - 0x1FF */
+ __IO uint32_t FMR; /*!< CAN filter master register, Address offset: 0x200 */
+ __IO uint32_t FM1R; /*!< CAN filter mode register, Address offset: 0x204 */
+ uint32_t RESERVED2; /*!< Reserved, 0x208 */
+ __IO uint32_t FS1R; /*!< CAN filter scale register, Address offset: 0x20C */
+ uint32_t RESERVED3; /*!< Reserved, 0x210 */
+ __IO uint32_t FFA1R; /*!< CAN filter FIFO assignment register, Address offset: 0x214 */
+ uint32_t RESERVED4; /*!< Reserved, 0x218 */
+ __IO uint32_t FA1R; /*!< CAN filter activation register, Address offset: 0x21C */
+ uint32_t RESERVED5[8]; /*!< Reserved, 0x220-0x23F */
+ CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register, Address offset: 0x240-0x31C */
+} CAN_TypeDef;
+
+/**
+ * @brief CRC calculation unit
+ */
+
+typedef struct
+{
+ __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
+ __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
+ uint8_t RESERVED0; /*!< Reserved, 0x05 */
+ uint16_t RESERVED1; /*!< Reserved, 0x06 */
+ __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
+} CRC_TypeDef;
+
+/**
+ * @brief Digital to Analog Converter
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */
+ __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */
+ __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
+ __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */
+ __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */
+ __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
+ __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */
+ __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */
+ __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */
+ __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */
+ __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */
+ __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */
+ __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */
+ __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */
+} DAC_TypeDef;
+
+/**
+ * @brief Debug MCU
+ */
+
+typedef struct
+{
+ __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
+ __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
+ __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */
+ __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */
+}DBGMCU_TypeDef;
+
+/**
+ * @brief DCMI
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< DCMI control register 1, Address offset: 0x00 */
+ __IO uint32_t SR; /*!< DCMI status register, Address offset: 0x04 */
+ __IO uint32_t RISR; /*!< DCMI raw interrupt status register, Address offset: 0x08 */
+ __IO uint32_t IER; /*!< DCMI interrupt enable register, Address offset: 0x0C */
+ __IO uint32_t MISR; /*!< DCMI masked interrupt status register, Address offset: 0x10 */
+ __IO uint32_t ICR; /*!< DCMI interrupt clear register, Address offset: 0x14 */
+ __IO uint32_t ESCR; /*!< DCMI embedded synchronization code register, Address offset: 0x18 */
+ __IO uint32_t ESUR; /*!< DCMI embedded synchronization unmask register, Address offset: 0x1C */
+ __IO uint32_t CWSTRTR; /*!< DCMI crop window start, Address offset: 0x20 */
+ __IO uint32_t CWSIZER; /*!< DCMI crop window size, Address offset: 0x24 */
+ __IO uint32_t DR; /*!< DCMI data register, Address offset: 0x28 */
+} DCMI_TypeDef;
+
+/**
+ * @brief DMA Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< DMA stream x configuration register */
+ __IO uint32_t NDTR; /*!< DMA stream x number of data register */
+ __IO uint32_t PAR; /*!< DMA stream x peripheral address register */
+ __IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */
+ __IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */
+ __IO uint32_t FCR; /*!< DMA stream x FIFO control register */
+} DMA_Stream_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t LISR; /*!< DMA low interrupt status register, Address offset: 0x00 */
+ __IO uint32_t HISR; /*!< DMA high interrupt status register, Address offset: 0x04 */
+ __IO uint32_t LIFCR; /*!< DMA low interrupt flag clear register, Address offset: 0x08 */
+ __IO uint32_t HIFCR; /*!< DMA high interrupt flag clear register, Address offset: 0x0C */
+} DMA_TypeDef;
+
+/**
+ * @brief DMA2D Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< DMA2D Control Register, Address offset: 0x00 */
+ __IO uint32_t ISR; /*!< DMA2D Interrupt Status Register, Address offset: 0x04 */
+ __IO uint32_t IFCR; /*!< DMA2D Interrupt Flag Clear Register, Address offset: 0x08 */
+ __IO uint32_t FGMAR; /*!< DMA2D Foreground Memory Address Register, Address offset: 0x0C */
+ __IO uint32_t FGOR; /*!< DMA2D Foreground Offset Register, Address offset: 0x10 */
+ __IO uint32_t BGMAR; /*!< DMA2D Background Memory Address Register, Address offset: 0x14 */
+ __IO uint32_t BGOR; /*!< DMA2D Background Offset Register, Address offset: 0x18 */
+ __IO uint32_t FGPFCCR; /*!< DMA2D Foreground PFC Control Register, Address offset: 0x1C */
+ __IO uint32_t FGCOLR; /*!< DMA2D Foreground Color Register, Address offset: 0x20 */
+ __IO uint32_t BGPFCCR; /*!< DMA2D Background PFC Control Register, Address offset: 0x24 */
+ __IO uint32_t BGCOLR; /*!< DMA2D Background Color Register, Address offset: 0x28 */
+ __IO uint32_t FGCMAR; /*!< DMA2D Foreground CLUT Memory Address Register, Address offset: 0x2C */
+ __IO uint32_t BGCMAR; /*!< DMA2D Background CLUT Memory Address Register, Address offset: 0x30 */
+ __IO uint32_t OPFCCR; /*!< DMA2D Output PFC Control Register, Address offset: 0x34 */
+ __IO uint32_t OCOLR; /*!< DMA2D Output Color Register, Address offset: 0x38 */
+ __IO uint32_t OMAR; /*!< DMA2D Output Memory Address Register, Address offset: 0x3C */
+ __IO uint32_t OOR; /*!< DMA2D Output Offset Register, Address offset: 0x40 */
+ __IO uint32_t NLR; /*!< DMA2D Number of Line Register, Address offset: 0x44 */
+ __IO uint32_t LWR; /*!< DMA2D Line Watermark Register, Address offset: 0x48 */
+ __IO uint32_t AMTCR; /*!< DMA2D AHB Master Timer Configuration Register, Address offset: 0x4C */
+ uint32_t RESERVED[236]; /*!< Reserved, 0x50-0x3FF */
+ __IO uint32_t FGCLUT[256]; /*!< DMA2D Foreground CLUT, Address offset:400-7FF */
+ __IO uint32_t BGCLUT[256]; /*!< DMA2D Background CLUT, Address offset:800-BFF */
+} DMA2D_TypeDef;
+
+/**
+ * @brief DSI Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t VR; /*!< DSI Host Version Register, Address offset: 0x00 */
+ __IO uint32_t CR; /*!< DSI Host Control Register, Address offset: 0x04 */
+ __IO uint32_t CCR; /*!< DSI HOST Clock Control Register, Address offset: 0x08 */
+ __IO uint32_t LVCIDR; /*!< DSI Host LTDC VCID Register, Address offset: 0x0C */
+ __IO uint32_t LCOLCR; /*!< DSI Host LTDC Color Coding Register, Address offset: 0x10 */
+ __IO uint32_t LPCR; /*!< DSI Host LTDC Polarity Configuration Register, Address offset: 0x14 */
+ __IO uint32_t LPMCR; /*!< DSI Host Low-Power Mode Configuration Register, Address offset: 0x18 */
+ uint32_t RESERVED0[4]; /*!< Reserved, 0x1C - 0x2B */
+ __IO uint32_t PCR; /*!< DSI Host Protocol Configuration Register, Address offset: 0x2C */
+ __IO uint32_t GVCIDR; /*!< DSI Host Generic VCID Register, Address offset: 0x30 */
+ __IO uint32_t MCR; /*!< DSI Host Mode Configuration Register, Address offset: 0x34 */
+ __IO uint32_t VMCR; /*!< DSI Host Video Mode Configuration Register, Address offset: 0x38 */
+ __IO uint32_t VPCR; /*!< DSI Host Video Packet Configuration Register, Address offset: 0x3C */
+ __IO uint32_t VCCR; /*!< DSI Host Video Chunks Configuration Register, Address offset: 0x40 */
+ __IO uint32_t VNPCR; /*!< DSI Host Video Null Packet Configuration Register, Address offset: 0x44 */
+ __IO uint32_t VHSACR; /*!< DSI Host Video HSA Configuration Register, Address offset: 0x48 */
+ __IO uint32_t VHBPCR; /*!< DSI Host Video HBP Configuration Register, Address offset: 0x4C */
+ __IO uint32_t VLCR; /*!< DSI Host Video Line Configuration Register, Address offset: 0x50 */
+ __IO uint32_t VVSACR; /*!< DSI Host Video VSA Configuration Register, Address offset: 0x54 */
+ __IO uint32_t VVBPCR; /*!< DSI Host Video VBP Configuration Register, Address offset: 0x58 */
+ __IO uint32_t VVFPCR; /*!< DSI Host Video VFP Configuration Register, Address offset: 0x5C */
+ __IO uint32_t VVACR; /*!< DSI Host Video VA Configuration Register, Address offset: 0x60 */
+ __IO uint32_t LCCR; /*!< DSI Host LTDC Command Configuration Register, Address offset: 0x64 */
+ __IO uint32_t CMCR; /*!< DSI Host Command Mode Configuration Register, Address offset: 0x68 */
+ __IO uint32_t GHCR; /*!< DSI Host Generic Header Configuration Register, Address offset: 0x6C */
+ __IO uint32_t GPDR; /*!< DSI Host Generic Payload Data Register, Address offset: 0x70 */
+ __IO uint32_t GPSR; /*!< DSI Host Generic Packet Status Register, Address offset: 0x74 */
+ __IO uint32_t TCCR[6]; /*!< DSI Host Timeout Counter Configuration Register, Address offset: 0x78-0x8F */
+ __IO uint32_t TDCR; /*!< DSI Host 3D Configuration Register, Address offset: 0x90 */
+ __IO uint32_t CLCR; /*!< DSI Host Clock Lane Configuration Register, Address offset: 0x94 */
+ __IO uint32_t CLTCR; /*!< DSI Host Clock Lane Timer Configuration Register, Address offset: 0x98 */
+ __IO uint32_t DLTCR; /*!< DSI Host Data Lane Timer Configuration Register, Address offset: 0x9C */
+ __IO uint32_t PCTLR; /*!< DSI Host PHY Control Register, Address offset: 0xA0 */
+ __IO uint32_t PCONFR; /*!< DSI Host PHY Configuration Register, Address offset: 0xA4 */
+ __IO uint32_t PUCR; /*!< DSI Host PHY ULPS Control Register, Address offset: 0xA8 */
+ __IO uint32_t PTTCR; /*!< DSI Host PHY TX Triggers Configuration Register, Address offset: 0xAC */
+ __IO uint32_t PSR; /*!< DSI Host PHY Status Register, Address offset: 0xB0 */
+ uint32_t RESERVED1[2]; /*!< Reserved, 0xB4 - 0xBB */
+ __IO uint32_t ISR[2]; /*!< DSI Host Interrupt & Status Register, Address offset: 0xBC-0xC3 */
+ __IO uint32_t IER[2]; /*!< DSI Host Interrupt Enable Register, Address offset: 0xC4-0xCB */
+ uint32_t RESERVED2[3]; /*!< Reserved, 0xD0 - 0xD7 */
+ __IO uint32_t FIR[2]; /*!< DSI Host Force Interrupt Register, Address offset: 0xD8-0xDF */
+ uint32_t RESERVED3[8]; /*!< Reserved, 0xE0 - 0xFF */
+ __IO uint32_t VSCR; /*!< DSI Host Video Shadow Control Register, Address offset: 0x100 */
+ uint32_t RESERVED4[2]; /*!< Reserved, 0x104 - 0x10B */
+ __IO uint32_t LCVCIDR; /*!< DSI Host LTDC Current VCID Register, Address offset: 0x10C */
+ __IO uint32_t LCCCR; /*!< DSI Host LTDC Current Color Coding Register, Address offset: 0x110 */
+ uint32_t RESERVED5; /*!< Reserved, 0x114 */
+ __IO uint32_t LPMCCR; /*!< DSI Host Low-power Mode Current Configuration Register, Address offset: 0x118 */
+ uint32_t RESERVED6[7]; /*!< Reserved, 0x11C - 0x137 */
+ __IO uint32_t VMCCR; /*!< DSI Host Video Mode Current Configuration Register, Address offset: 0x138 */
+ __IO uint32_t VPCCR; /*!< DSI Host Video Packet Current Configuration Register, Address offset: 0x13C */
+ __IO uint32_t VCCCR; /*!< DSI Host Video Chuncks Current Configuration Register, Address offset: 0x140 */
+ __IO uint32_t VNPCCR; /*!< DSI Host Video Null Packet Current Configuration Register, Address offset: 0x144 */
+ __IO uint32_t VHSACCR; /*!< DSI Host Video HSA Current Configuration Register, Address offset: 0x148 */
+ __IO uint32_t VHBPCCR; /*!< DSI Host Video HBP Current Configuration Register, Address offset: 0x14C */
+ __IO uint32_t VLCCR; /*!< DSI Host Video Line Current Configuration Register, Address offset: 0x150 */
+ __IO uint32_t VVSACCR; /*!< DSI Host Video VSA Current Configuration Register, Address offset: 0x154 */
+ __IO uint32_t VVBPCCR; /*!< DSI Host Video VBP Current Configuration Register, Address offset: 0x158 */
+ __IO uint32_t VVFPCCR; /*!< DSI Host Video VFP Current Configuration Register, Address offset: 0x15C */
+ __IO uint32_t VVACCR; /*!< DSI Host Video VA Current Configuration Register, Address offset: 0x160 */
+ uint32_t RESERVED7[11]; /*!< Reserved, 0x164 - 0x18F */
+ __IO uint32_t TDCCR; /*!< DSI Host 3D Current Configuration Register, Address offset: 0x190 */
+ uint32_t RESERVED8[155]; /*!< Reserved, 0x194 - 0x3FF */
+ __IO uint32_t WCFGR; /*!< DSI Wrapper Configuration Register, Address offset: 0x400 */
+ __IO uint32_t WCR; /*!< DSI Wrapper Control Register, Address offset: 0x404 */
+ __IO uint32_t WIER; /*!< DSI Wrapper Interrupt Enable Register, Address offset: 0x408 */
+ __IO uint32_t WISR; /*!< DSI Wrapper Interrupt and Status Register, Address offset: 0x40C */
+ __IO uint32_t WIFCR; /*!< DSI Wrapper Interrupt Flag Clear Register, Address offset: 0x410 */
+ uint32_t RESERVED9; /*!< Reserved, 0x414 */
+ __IO uint32_t WPCR[5]; /*!< DSI Wrapper PHY Configuration Register, Address offset: 0x418-0x42B */
+ uint32_t RESERVED10; /*!< Reserved, 0x42C */
+ __IO uint32_t WRPCR; /*!< DSI Wrapper Regulator and PLL Control Register, Address offset: 0x430 */
+} DSI_TypeDef;
+
+/**
+ * @brief Ethernet MAC
+ */
+
+typedef struct
+{
+ __IO uint32_t MACCR;
+ __IO uint32_t MACFFR;
+ __IO uint32_t MACHTHR;
+ __IO uint32_t MACHTLR;
+ __IO uint32_t MACMIIAR;
+ __IO uint32_t MACMIIDR;
+ __IO uint32_t MACFCR;
+ __IO uint32_t MACVLANTR; /* 8 */
+ uint32_t RESERVED0[2];
+ __IO uint32_t MACRWUFFR; /* 11 */
+ __IO uint32_t MACPMTCSR;
+ uint32_t RESERVED1[2];
+ __IO uint32_t MACSR; /* 15 */
+ __IO uint32_t MACIMR;
+ __IO uint32_t MACA0HR;
+ __IO uint32_t MACA0LR;
+ __IO uint32_t MACA1HR;
+ __IO uint32_t MACA1LR;
+ __IO uint32_t MACA2HR;
+ __IO uint32_t MACA2LR;
+ __IO uint32_t MACA3HR;
+ __IO uint32_t MACA3LR; /* 24 */
+ uint32_t RESERVED2[40];
+ __IO uint32_t MMCCR; /* 65 */
+ __IO uint32_t MMCRIR;
+ __IO uint32_t MMCTIR;
+ __IO uint32_t MMCRIMR;
+ __IO uint32_t MMCTIMR; /* 69 */
+ uint32_t RESERVED3[14];
+ __IO uint32_t MMCTGFSCCR; /* 84 */
+ __IO uint32_t MMCTGFMSCCR;
+ uint32_t RESERVED4[5];
+ __IO uint32_t MMCTGFCR;
+ uint32_t RESERVED5[10];
+ __IO uint32_t MMCRFCECR;
+ __IO uint32_t MMCRFAECR;
+ uint32_t RESERVED6[10];
+ __IO uint32_t MMCRGUFCR;
+ uint32_t RESERVED7[334];
+ __IO uint32_t PTPTSCR;
+ __IO uint32_t PTPSSIR;
+ __IO uint32_t PTPTSHR;
+ __IO uint32_t PTPTSLR;
+ __IO uint32_t PTPTSHUR;
+ __IO uint32_t PTPTSLUR;
+ __IO uint32_t PTPTSAR;
+ __IO uint32_t PTPTTHR;
+ __IO uint32_t PTPTTLR;
+ __IO uint32_t RESERVED8;
+ __IO uint32_t PTPTSSR;
+ uint32_t RESERVED9[565];
+ __IO uint32_t DMABMR;
+ __IO uint32_t DMATPDR;
+ __IO uint32_t DMARPDR;
+ __IO uint32_t DMARDLAR;
+ __IO uint32_t DMATDLAR;
+ __IO uint32_t DMASR;
+ __IO uint32_t DMAOMR;
+ __IO uint32_t DMAIER;
+ __IO uint32_t DMAMFBOCR;
+ __IO uint32_t DMARSWTR;
+ uint32_t RESERVED10[8];
+ __IO uint32_t DMACHTDR;
+ __IO uint32_t DMACHRDR;
+ __IO uint32_t DMACHTBAR;
+ __IO uint32_t DMACHRBAR;
+} ETH_TypeDef;
+
+/**
+ * @brief External Interrupt/Event Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t IMR; /*!< EXTI Interrupt mask register, Address offset: 0x00 */
+ __IO uint32_t EMR; /*!< EXTI Event mask register, Address offset: 0x04 */
+ __IO uint32_t RTSR; /*!< EXTI Rising trigger selection register, Address offset: 0x08 */
+ __IO uint32_t FTSR; /*!< EXTI Falling trigger selection register, Address offset: 0x0C */
+ __IO uint32_t SWIER; /*!< EXTI Software interrupt event register, Address offset: 0x10 */
+ __IO uint32_t PR; /*!< EXTI Pending register, Address offset: 0x14 */
+} EXTI_TypeDef;
+
+/**
+ * @brief FLASH Registers
+ */
+
+typedef struct
+{
+ __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */
+ __IO uint32_t KEYR; /*!< FLASH key register, Address offset: 0x04 */
+ __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x08 */
+ __IO uint32_t SR; /*!< FLASH status register, Address offset: 0x0C */
+ __IO uint32_t CR; /*!< FLASH control register, Address offset: 0x10 */
+ __IO uint32_t OPTCR; /*!< FLASH option control register , Address offset: 0x14 */
+ __IO uint32_t OPTCR1; /*!< FLASH option control register 1, Address offset: 0x18 */
+} FLASH_TypeDef;
+
+/**
+ * @brief Flexible Memory Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */
+} FMC_Bank1_TypeDef;
+
+/**
+ * @brief Flexible Memory Controller Bank1E
+ */
+
+typedef struct
+{
+ __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */
+} FMC_Bank1E_TypeDef;
+
+/**
+ * @brief Flexible Memory Controller Bank3
+ */
+
+typedef struct
+{
+ __IO uint32_t PCR; /*!< NAND Flash control register, Address offset: 0x80 */
+ __IO uint32_t SR; /*!< NAND Flash FIFO status and interrupt register, Address offset: 0x84 */
+ __IO uint32_t PMEM; /*!< NAND Flash Common memory space timing register, Address offset: 0x88 */
+ __IO uint32_t PATT; /*!< NAND Flash Attribute memory space timing register, Address offset: 0x8C */
+ uint32_t RESERVED; /*!< Reserved, 0x90 */
+ __IO uint32_t ECCR; /*!< NAND Flash ECC result registers, Address offset: 0x94 */
+} FMC_Bank3_TypeDef;
+
+/**
+ * @brief Flexible Memory Controller Bank5_6
+ */
+
+typedef struct
+{
+ __IO uint32_t SDCR[2]; /*!< SDRAM Control registers , Address offset: 0x140-0x144 */
+ __IO uint32_t SDTR[2]; /*!< SDRAM Timing registers , Address offset: 0x148-0x14C */
+ __IO uint32_t SDCMR; /*!< SDRAM Command Mode register, Address offset: 0x150 */
+ __IO uint32_t SDRTR; /*!< SDRAM Refresh Timer register, Address offset: 0x154 */
+ __IO uint32_t SDSR; /*!< SDRAM Status register, Address offset: 0x158 */
+} FMC_Bank5_6_TypeDef;
+
+/**
+ * @brief General Purpose I/O
+ */
+
+typedef struct
+{
+ __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
+ __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */
+ __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */
+ __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
+ __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
+ __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
+ __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */
+ __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
+ __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */
+} GPIO_TypeDef;
+
+/**
+ * @brief System configuration controller
+ */
+
+typedef struct
+{
+ __IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */
+ __IO uint32_t PMC; /*!< SYSCFG peripheral mode configuration register, Address offset: 0x04 */
+ __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
+ uint32_t RESERVED[2]; /*!< Reserved, 0x18-0x1C */
+ __IO uint32_t CMPCR; /*!< SYSCFG Compensation cell control register, Address offset: 0x20 */
+} SYSCFG_TypeDef;
+
+/**
+ * @brief Inter-integrated Circuit Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */
+ __IO uint32_t OAR1; /*!< I2C Own address register 1, Address offset: 0x08 */
+ __IO uint32_t OAR2; /*!< I2C Own address register 2, Address offset: 0x0C */
+ __IO uint32_t DR; /*!< I2C Data register, Address offset: 0x10 */
+ __IO uint32_t SR1; /*!< I2C Status register 1, Address offset: 0x14 */
+ __IO uint32_t SR2; /*!< I2C Status register 2, Address offset: 0x18 */
+ __IO uint32_t CCR; /*!< I2C Clock control register, Address offset: 0x1C */
+ __IO uint32_t TRISE; /*!< I2C TRISE register, Address offset: 0x20 */
+ __IO uint32_t FLTR; /*!< I2C FLTR register, Address offset: 0x24 */
+} I2C_TypeDef;
+
+/**
+ * @brief Independent WATCHDOG
+ */
+
+typedef struct
+{
+ __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */
+ __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */
+ __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */
+ __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */
+} IWDG_TypeDef;
+
+/**
+ * @brief LCD-TFT Display Controller
+ */
+
+typedef struct
+{
+ uint32_t RESERVED0[2]; /*!< Reserved, 0x00-0x04 */
+ __IO uint32_t SSCR; /*!< LTDC Synchronization Size Configuration Register, Address offset: 0x08 */
+ __IO uint32_t BPCR; /*!< LTDC Back Porch Configuration Register, Address offset: 0x0C */
+ __IO uint32_t AWCR; /*!< LTDC Active Width Configuration Register, Address offset: 0x10 */
+ __IO uint32_t TWCR; /*!< LTDC Total Width Configuration Register, Address offset: 0x14 */
+ __IO uint32_t GCR; /*!< LTDC Global Control Register, Address offset: 0x18 */
+ uint32_t RESERVED1[2]; /*!< Reserved, 0x1C-0x20 */
+ __IO uint32_t SRCR; /*!< LTDC Shadow Reload Configuration Register, Address offset: 0x24 */
+ uint32_t RESERVED2[1]; /*!< Reserved, 0x28 */
+ __IO uint32_t BCCR; /*!< LTDC Background Color Configuration Register, Address offset: 0x2C */
+ uint32_t RESERVED3[1]; /*!< Reserved, 0x30 */
+ __IO uint32_t IER; /*!< LTDC Interrupt Enable Register, Address offset: 0x34 */
+ __IO uint32_t ISR; /*!< LTDC Interrupt Status Register, Address offset: 0x38 */
+ __IO uint32_t ICR; /*!< LTDC Interrupt Clear Register, Address offset: 0x3C */
+ __IO uint32_t LIPCR; /*!< LTDC Line Interrupt Position Configuration Register, Address offset: 0x40 */
+ __IO uint32_t CPSR; /*!< LTDC Current Position Status Register, Address offset: 0x44 */
+ __IO uint32_t CDSR; /*!< LTDC Current Display Status Register, Address offset: 0x48 */
+} LTDC_TypeDef;
+
+/**
+ * @brief LCD-TFT Display layer x Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< LTDC Layerx Control Register Address offset: 0x84 */
+ __IO uint32_t WHPCR; /*!< LTDC Layerx Window Horizontal Position Configuration Register Address offset: 0x88 */
+ __IO uint32_t WVPCR; /*!< LTDC Layerx Window Vertical Position Configuration Register Address offset: 0x8C */
+ __IO uint32_t CKCR; /*!< LTDC Layerx Color Keying Configuration Register Address offset: 0x90 */
+ __IO uint32_t PFCR; /*!< LTDC Layerx Pixel Format Configuration Register Address offset: 0x94 */
+ __IO uint32_t CACR; /*!< LTDC Layerx Constant Alpha Configuration Register Address offset: 0x98 */
+ __IO uint32_t DCCR; /*!< LTDC Layerx Default Color Configuration Register Address offset: 0x9C */
+ __IO uint32_t BFCR; /*!< LTDC Layerx Blending Factors Configuration Register Address offset: 0xA0 */
+ uint32_t RESERVED0[2]; /*!< Reserved */
+ __IO uint32_t CFBAR; /*!< LTDC Layerx Color Frame Buffer Address Register Address offset: 0xAC */
+ __IO uint32_t CFBLR; /*!< LTDC Layerx Color Frame Buffer Length Register Address offset: 0xB0 */
+ __IO uint32_t CFBLNR; /*!< LTDC Layerx ColorFrame Buffer Line Number Register Address offset: 0xB4 */
+ uint32_t RESERVED1[3]; /*!< Reserved */
+ __IO uint32_t CLUTWR; /*!< LTDC Layerx CLUT Write Register Address offset: 0x144 */
+
+} LTDC_Layer_TypeDef;
+
+/**
+ * @brief Power Control
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */
+ __IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */
+} PWR_TypeDef;
+
+/**
+ * @brief Reset and Clock Control
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */
+ __IO uint32_t PLLCFGR; /*!< RCC PLL configuration register, Address offset: 0x04 */
+ __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x08 */
+ __IO uint32_t CIR; /*!< RCC clock interrupt register, Address offset: 0x0C */
+ __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x10 */
+ __IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x14 */
+ __IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0x18 */
+ uint32_t RESERVED0; /*!< Reserved, 0x1C */
+ __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x20 */
+ __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x24 */
+ uint32_t RESERVED1[2]; /*!< Reserved, 0x28-0x2C */
+ __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clock register, Address offset: 0x30 */
+ __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clock register, Address offset: 0x34 */
+ __IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clock register, Address offset: 0x38 */
+ uint32_t RESERVED2; /*!< Reserved, 0x3C */
+ __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x40 */
+ __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x44 */
+ uint32_t RESERVED3[2]; /*!< Reserved, 0x48-0x4C */
+ __IO uint32_t AHB1LPENR; /*!< RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 */
+ __IO uint32_t AHB2LPENR; /*!< RCC AHB2 peripheral clock enable in low power mode register, Address offset: 0x54 */
+ __IO uint32_t AHB3LPENR; /*!< RCC AHB3 peripheral clock enable in low power mode register, Address offset: 0x58 */
+ uint32_t RESERVED4; /*!< Reserved, 0x5C */
+ __IO uint32_t APB1LPENR; /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 */
+ __IO uint32_t APB2LPENR; /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 */
+ uint32_t RESERVED5[2]; /*!< Reserved, 0x68-0x6C */
+ __IO uint32_t BDCR; /*!< RCC Backup domain control register, Address offset: 0x70 */
+ __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x74 */
+ uint32_t RESERVED6[2]; /*!< Reserved, 0x78-0x7C */
+ __IO uint32_t SSCGR; /*!< RCC spread spectrum clock generation register, Address offset: 0x80 */
+ __IO uint32_t PLLI2SCFGR; /*!< RCC PLLI2S configuration register, Address offset: 0x84 */
+ __IO uint32_t PLLSAICFGR; /*!< RCC PLLSAI configuration register, Address offset: 0x88 */
+ __IO uint32_t DCKCFGR; /*!< RCC Dedicated Clocks configuration register, Address offset: 0x8C */
+
+} RCC_TypeDef;
+
+/**
+ * @brief Real-Time Clock
+ */
+
+typedef struct
+{
+ __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
+ __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */
+ __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */
+ __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */
+ __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */
+ __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */
+ __IO uint32_t CALIBR; /*!< RTC calibration register, Address offset: 0x18 */
+ __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */
+ __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */
+ __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */
+ __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */
+ __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */
+ __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */
+ __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */
+ __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */
+ __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */
+ __IO uint32_t TAFCR; /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */
+ __IO uint32_t ALRMASSR;/*!< RTC alarm A sub second register, Address offset: 0x44 */
+ __IO uint32_t ALRMBSSR;/*!< RTC alarm B sub second register, Address offset: 0x48 */
+ uint32_t RESERVED7; /*!< Reserved, 0x4C */
+ __IO uint32_t BKP0R; /*!< RTC backup register 1, Address offset: 0x50 */
+ __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */
+ __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */
+ __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */
+ __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */
+ __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */
+ __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */
+ __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */
+ __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */
+ __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */
+ __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */
+ __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */
+ __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */
+ __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */
+ __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */
+ __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */
+ __IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */
+ __IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */
+ __IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */
+ __IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */
+} RTC_TypeDef;
+
+/**
+ * @brief Serial Audio Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t GCR; /*!< SAI global configuration register, Address offset: 0x00 */
+} SAI_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t CR1; /*!< SAI block x configuration register 1, Address offset: 0x04 */
+ __IO uint32_t CR2; /*!< SAI block x configuration register 2, Address offset: 0x08 */
+ __IO uint32_t FRCR; /*!< SAI block x frame configuration register, Address offset: 0x0C */
+ __IO uint32_t SLOTR; /*!< SAI block x slot register, Address offset: 0x10 */
+ __IO uint32_t IMR; /*!< SAI block x interrupt mask register, Address offset: 0x14 */
+ __IO uint32_t SR; /*!< SAI block x status register, Address offset: 0x18 */
+ __IO uint32_t CLRFR; /*!< SAI block x clear flag register, Address offset: 0x1C */
+ __IO uint32_t DR; /*!< SAI block x data register, Address offset: 0x20 */
+} SAI_Block_TypeDef;
+
+/**
+ * @brief SD host Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t POWER; /*!< SDIO power control register, Address offset: 0x00 */
+ __IO uint32_t CLKCR; /*!< SDI clock control register, Address offset: 0x04 */
+ __IO uint32_t ARG; /*!< SDIO argument register, Address offset: 0x08 */
+ __IO uint32_t CMD; /*!< SDIO command register, Address offset: 0x0C */
+ __I uint32_t RESPCMD; /*!< SDIO command response register, Address offset: 0x10 */
+ __I uint32_t RESP1; /*!< SDIO response 1 register, Address offset: 0x14 */
+ __I uint32_t RESP2; /*!< SDIO response 2 register, Address offset: 0x18 */
+ __I uint32_t RESP3; /*!< SDIO response 3 register, Address offset: 0x1C */
+ __I uint32_t RESP4; /*!< SDIO response 4 register, Address offset: 0x20 */
+ __IO uint32_t DTIMER; /*!< SDIO data timer register, Address offset: 0x24 */
+ __IO uint32_t DLEN; /*!< SDIO data length register, Address offset: 0x28 */
+ __IO uint32_t DCTRL; /*!< SDIO data control register, Address offset: 0x2C */
+ __I uint32_t DCOUNT; /*!< SDIO data counter register, Address offset: 0x30 */
+ __I uint32_t STA; /*!< SDIO status register, Address offset: 0x34 */
+ __IO uint32_t ICR; /*!< SDIO interrupt clear register, Address offset: 0x38 */
+ __IO uint32_t MASK; /*!< SDIO mask register, Address offset: 0x3C */
+ uint32_t RESERVED0[2]; /*!< Reserved, 0x40-0x44 */
+ __I uint32_t FIFOCNT; /*!< SDIO FIFO counter register, Address offset: 0x48 */
+ uint32_t RESERVED1[13]; /*!< Reserved, 0x4C-0x7C */
+ __IO uint32_t FIFO; /*!< SDIO data FIFO register, Address offset: 0x80 */
+} SDIO_TypeDef;
+
+/**
+ * @brief Serial Peripheral Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t CR1; /*!< SPI control register 1 (not used in I2S mode), Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< SPI control register 2, Address offset: 0x04 */
+ __IO uint32_t SR; /*!< SPI status register, Address offset: 0x08 */
+ __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */
+ __IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
+ __IO uint32_t RXCRCR; /*!< SPI RX CRC register (not used in I2S mode), Address offset: 0x14 */
+ __IO uint32_t TXCRCR; /*!< SPI TX CRC register (not used in I2S mode), Address offset: 0x18 */
+ __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */
+ __IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */
+} SPI_TypeDef;
+
+/**
+ * @brief QUAD Serial Peripheral Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< QUADSPI Control register, Address offset: 0x00 */
+ __IO uint32_t DCR; /*!< QUADSPI Device Configuration register, Address offset: 0x04 */
+ __IO uint32_t SR; /*!< QUADSPI Status register, Address offset: 0x08 */
+ __IO uint32_t FCR; /*!< QUADSPI Flag Clear register, Address offset: 0x0C */
+ __IO uint32_t DLR; /*!< QUADSPI Data Length register, Address offset: 0x10 */
+ __IO uint32_t CCR; /*!< QUADSPI Communication Configuration register, Address offset: 0x14 */
+ __IO uint32_t AR; /*!< QUADSPI Address register, Address offset: 0x18 */
+ __IO uint32_t ABR; /*!< QUADSPI Alternate Bytes register, Address offset: 0x1C */
+ __IO uint32_t DR; /*!< QUADSPI Data register, Address offset: 0x20 */
+ __IO uint32_t PSMKR; /*!< QUADSPI Polling Status Mask register, Address offset: 0x24 */
+ __IO uint32_t PSMAR; /*!< QUADSPI Polling Status Match register, Address offset: 0x28 */
+ __IO uint32_t PIR; /*!< QUADSPI Polling Interval register, Address offset: 0x2C */
+ __IO uint32_t LPTR; /*!< QUADSPI Low Power Timeout register, Address offset: 0x30 */
+} QUADSPI_TypeDef;
+
+/**
+ * @brief TIM
+ */
+
+typedef struct
+{
+ __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
+ __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */
+ __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
+ __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
+ __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
+ __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
+ __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
+ __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
+ __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
+ __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */
+ __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
+ __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */
+ __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
+ __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
+ __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
+ __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
+ __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
+ __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
+ __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */
+ __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */
+} TIM_TypeDef;
+
+/**
+ * @brief Universal Synchronous Asynchronous Receiver Transmitter
+ */
+
+typedef struct
+{
+ __IO uint32_t SR; /*!< USART Status register, Address offset: 0x00 */
+ __IO uint32_t DR; /*!< USART Data register, Address offset: 0x04 */
+ __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x08 */
+ __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x0C */
+ __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x10 */
+ __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x14 */
+ __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x18 */
+} USART_TypeDef;
+
+/**
+ * @brief Window WATCHDOG
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
+ __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
+ __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
+} WWDG_TypeDef;
+
+/**
+ * @brief RNG
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */
+ __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */
+ __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */
+} RNG_TypeDef;
+
+
+/**
+ * @brief USB_OTG_Core_Registers
+ */
+typedef struct
+{
+ __IO uint32_t GOTGCTL; /*!< USB_OTG Control and Status Register 000h */
+ __IO uint32_t GOTGINT; /*!< USB_OTG Interrupt Register 004h */
+ __IO uint32_t GAHBCFG; /*!< Core AHB Configuration Register 008h */
+ __IO uint32_t GUSBCFG; /*!< Core USB Configuration Register 00Ch */
+ __IO uint32_t GRSTCTL; /*!< Core Reset Register 010h */
+ __IO uint32_t GINTSTS; /*!< Core Interrupt Register 014h */
+ __IO uint32_t GINTMSK; /*!< Core Interrupt Mask Register 018h */
+ __IO uint32_t GRXSTSR; /*!< Receive Sts Q Read Register 01Ch */
+ __IO uint32_t GRXSTSP; /*!< Receive Sts Q Read & POP Register 020h */
+ __IO uint32_t GRXFSIZ; /*!< Receive FIFO Size Register 024h */
+ __IO uint32_t DIEPTXF0_HNPTXFSIZ; /*!< EP0 / Non Periodic Tx FIFO Size Register 028h */
+ __IO uint32_t HNPTXSTS; /*!< Non Periodic Tx FIFO/Queue Sts reg 02Ch */
+ uint32_t Reserved30[2]; /*!< Reserved 030h */
+ __IO uint32_t GCCFG; /*!< General Purpose IO Register 038h */
+ __IO uint32_t CID; /*!< User ID Register 03Ch */
+ uint32_t Reserved5[3]; /*!< Reserved 040h-048h */
+ __IO uint32_t GHWCFG3; /*!< User HW config3 04Ch */
+ uint32_t Reserved6; /*!< Reserved 050h */
+ __IO uint32_t GLPMCFG; /*!< LPM Register 054h */
+ uint32_t Reserved; /*!< Reserved 058h */
+ __IO uint32_t GDFIFOCFG; /*!< DFIFO Software Config Register 05Ch */
+ uint32_t Reserved43[40]; /*!< Reserved 058h-0FFh */
+ __IO uint32_t HPTXFSIZ; /*!< Host Periodic Tx FIFO Size Reg 100h */
+ __IO uint32_t DIEPTXF[0x0F]; /*!< dev Periodic Transmit FIFO */
+} USB_OTG_GlobalTypeDef;
+
+/**
+ * @brief USB_OTG_device_Registers
+ */
+typedef struct
+{
+ __IO uint32_t DCFG; /*!< dev Configuration Register 800h */
+ __IO uint32_t DCTL; /*!< dev Control Register 804h */
+ __IO uint32_t DSTS; /*!< dev Status Register (RO) 808h */
+ uint32_t Reserved0C; /*!< Reserved 80Ch */
+ __IO uint32_t DIEPMSK; /*!< dev IN Endpoint Mask 810h */
+ __IO uint32_t DOEPMSK; /*!< dev OUT Endpoint Mask 814h */
+ __IO uint32_t DAINT; /*!< dev All Endpoints Itr Reg 818h */
+ __IO uint32_t DAINTMSK; /*!< dev All Endpoints Itr Mask 81Ch */
+ uint32_t Reserved20; /*!< Reserved 820h */
+ uint32_t Reserved9; /*!< Reserved 824h */
+ __IO uint32_t DVBUSDIS; /*!< dev VBUS discharge Register 828h */
+ __IO uint32_t DVBUSPULSE; /*!< dev VBUS Pulse Register 82Ch */
+ __IO uint32_t DTHRCTL; /*!< dev threshold 830h */
+ __IO uint32_t DIEPEMPMSK; /*!< dev empty msk 834h */
+ __IO uint32_t DEACHINT; /*!< dedicated EP interrupt 838h */
+ __IO uint32_t DEACHMSK; /*!< dedicated EP msk 83Ch */
+ uint32_t Reserved40; /*!< dedicated EP mask 840h */
+ __IO uint32_t DINEP1MSK; /*!< dedicated EP mask 844h */
+ uint32_t Reserved44[15]; /*!< Reserved 844-87Ch */
+ __IO uint32_t DOUTEP1MSK; /*!< dedicated EP msk 884h */
+} USB_OTG_DeviceTypeDef;
+
+/**
+ * @brief USB_OTG_IN_Endpoint-Specific_Register
+ */
+typedef struct
+{
+ __IO uint32_t DIEPCTL; /*!< dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h */
+ uint32_t Reserved04; /*!< Reserved 900h + (ep_num * 20h) + 04h */
+ __IO uint32_t DIEPINT; /*!< dev IN Endpoint Itr Reg 900h + (ep_num * 20h) + 08h */
+ uint32_t Reserved0C; /*!< Reserved 900h + (ep_num * 20h) + 0Ch */
+ __IO uint32_t DIEPTSIZ; /*!< IN Endpoint Txfer Size 900h + (ep_num * 20h) + 10h */
+ __IO uint32_t DIEPDMA; /*!< IN Endpoint DMA Address Reg 900h + (ep_num * 20h) + 14h */
+ __IO uint32_t DTXFSTS; /*!< IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h */
+ uint32_t Reserved18; /*!< Reserved 900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch */
+} USB_OTG_INEndpointTypeDef;
+
+/**
+ * @brief USB_OTG_OUT_Endpoint-Specific_Registers
+ */
+typedef struct
+{
+ __IO uint32_t DOEPCTL; /*!< dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h */
+ uint32_t Reserved04; /*!< Reserved B00h + (ep_num * 20h) + 04h */
+ __IO uint32_t DOEPINT; /*!< dev OUT Endpoint Itr Reg B00h + (ep_num * 20h) + 08h */
+ uint32_t Reserved0C; /*!< Reserved B00h + (ep_num * 20h) + 0Ch */
+ __IO uint32_t DOEPTSIZ; /*!< dev OUT Endpoint Txfer Size B00h + (ep_num * 20h) + 10h */
+ __IO uint32_t DOEPDMA; /*!< dev OUT Endpoint DMA Address B00h + (ep_num * 20h) + 14h */
+ uint32_t Reserved18[2]; /*!< Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch */
+} USB_OTG_OUTEndpointTypeDef;
+
+/**
+ * @brief USB_OTG_Host_Mode_Register_Structures
+ */
+typedef struct
+{
+ __IO uint32_t HCFG; /*!< Host Configuration Register 400h */
+ __IO uint32_t HFIR; /*!< Host Frame Interval Register 404h */
+ __IO uint32_t HFNUM; /*!< Host Frame Nbr/Frame Remaining 408h */
+ uint32_t Reserved40C; /*!< Reserved 40Ch */
+ __IO uint32_t HPTXSTS; /*!< Host Periodic Tx FIFO/ Queue Status 410h */
+ __IO uint32_t HAINT; /*!< Host All Channels Interrupt Register 414h */
+ __IO uint32_t HAINTMSK; /*!< Host All Channels Interrupt Mask 418h */
+} USB_OTG_HostTypeDef;
+
+/**
+ * @brief USB_OTG_Host_Channel_Specific_Registers
+ */
+typedef struct
+{
+ __IO uint32_t HCCHAR; /*!< Host Channel Characteristics Register 500h */
+ __IO uint32_t HCSPLT; /*!< Host Channel Split Control Register 504h */
+ __IO uint32_t HCINT; /*!< Host Channel Interrupt Register 508h */
+ __IO uint32_t HCINTMSK; /*!< Host Channel Interrupt Mask Register 50Ch */
+ __IO uint32_t HCTSIZ; /*!< Host Channel Transfer Size Register 510h */
+ __IO uint32_t HCDMA; /*!< Host Channel DMA Address Register 514h */
+ uint32_t Reserved[2]; /*!< Reserved */
+} USB_OTG_HostChannelTypeDef;
+
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_memory_map
+ * @{
+ */
+#define FLASH_BASE 0x08000000U /*!< FLASH(up to 1 MB) base address in the alias region */
+#define CCMDATARAM_BASE 0x10000000U /*!< CCM(core coupled memory) data RAM(64 KB) base address in the alias region */
+#define SRAM1_BASE 0x20000000U /*!< SRAM1(160 KB) base address in the alias region */
+#define SRAM2_BASE 0x20028000U /*!< SRAM2(32 KB) base address in the alias region */
+#define SRAM3_BASE 0x20030000U /*!< SRAM3(128 KB) base address in the alias region */
+#define PERIPH_BASE 0x40000000U /*!< Peripheral base address in the alias region */
+#define BKPSRAM_BASE 0x40024000U /*!< Backup SRAM(4 KB) base address in the alias region */
+#define FMC_R_BASE 0xA0000000U /*!< FMC registers base address */
+#define QSPI_R_BASE 0xA0001000U /*!< QuadSPI registers base address */
+#define SRAM1_BB_BASE 0x22000000U /*!< SRAM1(112 KB) base address in the bit-band region */
+#define SRAM2_BB_BASE 0x22500000U /*!< SRAM2(16 KB) base address in the bit-band region */
+#define SRAM3_BB_BASE 0x22600000U /*!< SRAM3(64 KB) base address in the bit-band region */
+#define PERIPH_BB_BASE 0x42000000U /*!< Peripheral base address in the bit-band region */
+#define BKPSRAM_BB_BASE 0x42480000U /*!< Backup SRAM(4 KB) base address in the bit-band region */
+#define FLASH_END 0x081FFFFFU /*!< FLASH end address */
+#define CCMDATARAM_END 0x1000FFFFU /*!< CCM data RAM end address */
+
+/* Legacy defines */
+#define SRAM_BASE SRAM1_BASE
+#define SRAM_BB_BASE SRAM1_BB_BASE
+
+
+/*!< Peripheral memory map */
+#define APB1PERIPH_BASE PERIPH_BASE
+#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000U)
+#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000U)
+#define AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000U)
+
+/*!< APB1 peripherals */
+#define TIM2_BASE (APB1PERIPH_BASE + 0x0000U)
+#define TIM3_BASE (APB1PERIPH_BASE + 0x0400U)
+#define TIM4_BASE (APB1PERIPH_BASE + 0x0800U)
+#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00U)
+#define TIM6_BASE (APB1PERIPH_BASE + 0x1000U)
+#define TIM7_BASE (APB1PERIPH_BASE + 0x1400U)
+#define TIM12_BASE (APB1PERIPH_BASE + 0x1800U)
+#define TIM13_BASE (APB1PERIPH_BASE + 0x1C00U)
+#define TIM14_BASE (APB1PERIPH_BASE + 0x2000U)
+#define RTC_BASE (APB1PERIPH_BASE + 0x2800U)
+#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00U)
+#define IWDG_BASE (APB1PERIPH_BASE + 0x3000U)
+#define I2S2ext_BASE (APB1PERIPH_BASE + 0x3400U)
+#define SPI2_BASE (APB1PERIPH_BASE + 0x3800U)
+#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00U)
+#define I2S3ext_BASE (APB1PERIPH_BASE + 0x4000U)
+#define USART2_BASE (APB1PERIPH_BASE + 0x4400U)
+#define USART3_BASE (APB1PERIPH_BASE + 0x4800U)
+#define UART4_BASE (APB1PERIPH_BASE + 0x4C00U)
+#define UART5_BASE (APB1PERIPH_BASE + 0x5000U)
+#define I2C1_BASE (APB1PERIPH_BASE + 0x5400U)
+#define I2C2_BASE (APB1PERIPH_BASE + 0x5800U)
+#define I2C3_BASE (APB1PERIPH_BASE + 0x5C00U)
+#define CAN1_BASE (APB1PERIPH_BASE + 0x6400U)
+#define CAN2_BASE (APB1PERIPH_BASE + 0x6800U)
+#define PWR_BASE (APB1PERIPH_BASE + 0x7000U)
+#define DAC_BASE (APB1PERIPH_BASE + 0x7400U)
+#define UART7_BASE (APB1PERIPH_BASE + 0x7800U)
+#define UART8_BASE (APB1PERIPH_BASE + 0x7C00U)
+
+/*!< APB2 peripherals */
+#define TIM1_BASE (APB2PERIPH_BASE + 0x0000U)
+#define TIM8_BASE (APB2PERIPH_BASE + 0x0400U)
+#define USART1_BASE (APB2PERIPH_BASE + 0x1000U)
+#define USART6_BASE (APB2PERIPH_BASE + 0x1400U)
+#define ADC1_BASE (APB2PERIPH_BASE + 0x2000U)
+#define ADC2_BASE (APB2PERIPH_BASE + 0x2100U)
+#define ADC3_BASE (APB2PERIPH_BASE + 0x2200U)
+#define ADC_BASE (APB2PERIPH_BASE + 0x2300U)
+#define SDIO_BASE (APB2PERIPH_BASE + 0x2C00U)
+#define SPI1_BASE (APB2PERIPH_BASE + 0x3000U)
+#define SPI4_BASE (APB2PERIPH_BASE + 0x3400U)
+#define SYSCFG_BASE (APB2PERIPH_BASE + 0x3800U)
+#define EXTI_BASE (APB2PERIPH_BASE + 0x3C00U)
+#define TIM9_BASE (APB2PERIPH_BASE + 0x4000U)
+#define TIM10_BASE (APB2PERIPH_BASE + 0x4400U)
+#define TIM11_BASE (APB2PERIPH_BASE + 0x4800U)
+#define SPI5_BASE (APB2PERIPH_BASE + 0x5000U)
+#define SPI6_BASE (APB2PERIPH_BASE + 0x5400U)
+#define SAI1_BASE (APB2PERIPH_BASE + 0x5800U)
+#define SAI1_Block_A_BASE (SAI1_BASE + 0x004U)
+#define SAI1_Block_B_BASE (SAI1_BASE + 0x024U)
+#define LTDC_BASE (APB2PERIPH_BASE + 0x6800U)
+#define LTDC_Layer1_BASE (LTDC_BASE + 0x84U)
+#define LTDC_Layer2_BASE (LTDC_BASE + 0x104U)
+#define DSI_BASE (APB2PERIPH_BASE + 0x6C00U)
+
+/*!< AHB1 peripherals */
+#define GPIOA_BASE (AHB1PERIPH_BASE + 0x0000U)
+#define GPIOB_BASE (AHB1PERIPH_BASE + 0x0400U)
+#define GPIOC_BASE (AHB1PERIPH_BASE + 0x0800U)
+#define GPIOD_BASE (AHB1PERIPH_BASE + 0x0C00U)
+#define GPIOE_BASE (AHB1PERIPH_BASE + 0x1000U)
+#define GPIOF_BASE (AHB1PERIPH_BASE + 0x1400U)
+#define GPIOG_BASE (AHB1PERIPH_BASE + 0x1800U)
+#define GPIOH_BASE (AHB1PERIPH_BASE + 0x1C00U)
+#define GPIOI_BASE (AHB1PERIPH_BASE + 0x2000U)
+#define GPIOJ_BASE (AHB1PERIPH_BASE + 0x2400U)
+#define GPIOK_BASE (AHB1PERIPH_BASE + 0x2800U)
+#define CRC_BASE (AHB1PERIPH_BASE + 0x3000U)
+#define RCC_BASE (AHB1PERIPH_BASE + 0x3800U)
+#define FLASH_R_BASE (AHB1PERIPH_BASE + 0x3C00U)
+#define DMA1_BASE (AHB1PERIPH_BASE + 0x6000U)
+#define DMA1_Stream0_BASE (DMA1_BASE + 0x010U)
+#define DMA1_Stream1_BASE (DMA1_BASE + 0x028U)
+#define DMA1_Stream2_BASE (DMA1_BASE + 0x040U)
+#define DMA1_Stream3_BASE (DMA1_BASE + 0x058U)
+#define DMA1_Stream4_BASE (DMA1_BASE + 0x070U)
+#define DMA1_Stream5_BASE (DMA1_BASE + 0x088U)
+#define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0U)
+#define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8U)
+#define DMA2_BASE (AHB1PERIPH_BASE + 0x6400U)
+#define DMA2_Stream0_BASE (DMA2_BASE + 0x010U)
+#define DMA2_Stream1_BASE (DMA2_BASE + 0x028U)
+#define DMA2_Stream2_BASE (DMA2_BASE + 0x040U)
+#define DMA2_Stream3_BASE (DMA2_BASE + 0x058U)
+#define DMA2_Stream4_BASE (DMA2_BASE + 0x070U)
+#define DMA2_Stream5_BASE (DMA2_BASE + 0x088U)
+#define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0U)
+#define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8U)
+#define ETH_BASE (AHB1PERIPH_BASE + 0x8000U)
+#define ETH_MAC_BASE (ETH_BASE)
+#define ETH_MMC_BASE (ETH_BASE + 0x0100U)
+#define ETH_PTP_BASE (ETH_BASE + 0x0700U)
+#define ETH_DMA_BASE (ETH_BASE + 0x1000U)
+#define DMA2D_BASE (AHB1PERIPH_BASE + 0xB000U)
+
+/*!< AHB2 peripherals */
+#define DCMI_BASE (AHB2PERIPH_BASE + 0x50000U)
+#define RNG_BASE (AHB2PERIPH_BASE + 0x60800U)
+
+/*!< FMC Bankx registers base address */
+#define FMC_Bank1_R_BASE (FMC_R_BASE + 0x0000U)
+#define FMC_Bank1E_R_BASE (FMC_R_BASE + 0x0104U)
+#define FMC_Bank3_R_BASE (FMC_R_BASE + 0x0080U)
+#define FMC_Bank5_6_R_BASE (FMC_R_BASE + 0x0140U)
+
+/*!< Debug MCU registers base address */
+#define DBGMCU_BASE 0xE0042000U
+
+/*!< USB registers base address */
+#define USB_OTG_HS_PERIPH_BASE 0x40040000U
+#define USB_OTG_FS_PERIPH_BASE 0x50000000U
+
+#define USB_OTG_GLOBAL_BASE 0x000U
+#define USB_OTG_DEVICE_BASE 0x800U
+#define USB_OTG_IN_ENDPOINT_BASE 0x900U
+#define USB_OTG_OUT_ENDPOINT_BASE 0xB00U
+#define USB_OTG_EP_REG_SIZE 0x20U
+#define USB_OTG_HOST_BASE 0x400U
+#define USB_OTG_HOST_PORT_BASE 0x440U
+#define USB_OTG_HOST_CHANNEL_BASE 0x500U
+#define USB_OTG_HOST_CHANNEL_SIZE 0x20U
+#define USB_OTG_PCGCCTL_BASE 0xE00U
+#define USB_OTG_FIFO_BASE 0x1000U
+#define USB_OTG_FIFO_SIZE 0x1000U
+
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_declaration
+ * @{
+ */
+#define TIM2 ((TIM_TypeDef *) TIM2_BASE)
+#define TIM3 ((TIM_TypeDef *) TIM3_BASE)
+#define TIM4 ((TIM_TypeDef *) TIM4_BASE)
+#define TIM5 ((TIM_TypeDef *) TIM5_BASE)
+#define TIM6 ((TIM_TypeDef *) TIM6_BASE)
+#define TIM7 ((TIM_TypeDef *) TIM7_BASE)
+#define TIM12 ((TIM_TypeDef *) TIM12_BASE)
+#define TIM13 ((TIM_TypeDef *) TIM13_BASE)
+#define TIM14 ((TIM_TypeDef *) TIM14_BASE)
+#define RTC ((RTC_TypeDef *) RTC_BASE)
+#define WWDG ((WWDG_TypeDef *) WWDG_BASE)
+#define IWDG ((IWDG_TypeDef *) IWDG_BASE)
+#define I2S2ext ((SPI_TypeDef *) I2S2ext_BASE)
+#define SPI2 ((SPI_TypeDef *) SPI2_BASE)
+#define SPI3 ((SPI_TypeDef *) SPI3_BASE)
+#define I2S3ext ((SPI_TypeDef *) I2S3ext_BASE)
+#define USART2 ((USART_TypeDef *) USART2_BASE)
+#define USART3 ((USART_TypeDef *) USART3_BASE)
+#define UART4 ((USART_TypeDef *) UART4_BASE)
+#define UART5 ((USART_TypeDef *) UART5_BASE)
+#define I2C1 ((I2C_TypeDef *) I2C1_BASE)
+#define I2C2 ((I2C_TypeDef *) I2C2_BASE)
+#define I2C3 ((I2C_TypeDef *) I2C3_BASE)
+#define CAN1 ((CAN_TypeDef *) CAN1_BASE)
+#define CAN2 ((CAN_TypeDef *) CAN2_BASE)
+#define PWR ((PWR_TypeDef *) PWR_BASE)
+#define DAC ((DAC_TypeDef *) DAC_BASE)
+#define UART7 ((USART_TypeDef *) UART7_BASE)
+#define UART8 ((USART_TypeDef *) UART8_BASE)
+#define TIM1 ((TIM_TypeDef *) TIM1_BASE)
+#define TIM8 ((TIM_TypeDef *) TIM8_BASE)
+#define USART1 ((USART_TypeDef *) USART1_BASE)
+#define USART6 ((USART_TypeDef *) USART6_BASE)
+#define ADC ((ADC_Common_TypeDef *) ADC_BASE)
+#define ADC1 ((ADC_TypeDef *) ADC1_BASE)
+#define ADC2 ((ADC_TypeDef *) ADC2_BASE)
+#define ADC3 ((ADC_TypeDef *) ADC3_BASE)
+#define SDIO ((SDIO_TypeDef *) SDIO_BASE)
+#define SPI1 ((SPI_TypeDef *) SPI1_BASE)
+#define SPI4 ((SPI_TypeDef *) SPI4_BASE)
+#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
+#define EXTI ((EXTI_TypeDef *) EXTI_BASE)
+#define TIM9 ((TIM_TypeDef *) TIM9_BASE)
+#define TIM10 ((TIM_TypeDef *) TIM10_BASE)
+#define TIM11 ((TIM_TypeDef *) TIM11_BASE)
+#define SPI5 ((SPI_TypeDef *) SPI5_BASE)
+#define SPI6 ((SPI_TypeDef *) SPI6_BASE)
+#define SAI1 ((SAI_TypeDef *) SAI1_BASE)
+#define SAI1_Block_A ((SAI_Block_TypeDef *)SAI1_Block_A_BASE)
+#define SAI1_Block_B ((SAI_Block_TypeDef *)SAI1_Block_B_BASE)
+#define LTDC ((LTDC_TypeDef *)LTDC_BASE)
+#define LTDC_Layer1 ((LTDC_Layer_TypeDef *)LTDC_Layer1_BASE)
+#define LTDC_Layer2 ((LTDC_Layer_TypeDef *)LTDC_Layer2_BASE)
+#define DSI ((DSI_TypeDef *)DSI_BASE)
+
+#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
+#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
+#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
+#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
+#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
+#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
+#define GPIOG ((GPIO_TypeDef *) GPIOG_BASE)
+#define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
+#define GPIOI ((GPIO_TypeDef *) GPIOI_BASE)
+#define GPIOJ ((GPIO_TypeDef *) GPIOJ_BASE)
+#define GPIOK ((GPIO_TypeDef *) GPIOK_BASE)
+#define CRC ((CRC_TypeDef *) CRC_BASE)
+#define RCC ((RCC_TypeDef *) RCC_BASE)
+#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
+#define DMA1 ((DMA_TypeDef *) DMA1_BASE)
+#define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)
+#define DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)
+#define DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)
+#define DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)
+#define DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)
+#define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)
+#define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)
+#define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)
+#define DMA2 ((DMA_TypeDef *) DMA2_BASE)
+#define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)
+#define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
+#define DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)
+#define DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)
+#define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)
+#define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)
+#define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)
+#define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)
+#define ETH ((ETH_TypeDef *) ETH_BASE)
+#define DMA2D ((DMA2D_TypeDef *)DMA2D_BASE)
+#define DCMI ((DCMI_TypeDef *) DCMI_BASE)
+#define RNG ((RNG_TypeDef *) RNG_BASE)
+#define FMC_Bank1 ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE)
+#define FMC_Bank1E ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE)
+#define FMC_Bank3 ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE)
+#define FMC_Bank5_6 ((FMC_Bank5_6_TypeDef *) FMC_Bank5_6_R_BASE)
+#define QUADSPI ((QUADSPI_TypeDef *) QSPI_R_BASE)
+
+#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
+
+#define USB_OTG_FS ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE)
+#define USB_OTG_HS ((USB_OTG_GlobalTypeDef *) USB_OTG_HS_PERIPH_BASE)
+
+/**
+ * @}
+ */
+
+/** @addtogroup Exported_constants
+ * @{
+ */
+
+ /** @addtogroup Peripheral_Registers_Bits_Definition
+ * @{
+ */
+
+/******************************************************************************/
+/* Peripheral Registers_Bits_Definition */
+/******************************************************************************/
+
+/******************************************************************************/
+/* */
+/* Analog to Digital Converter */
+/* */
+/******************************************************************************/
+/******************** Bit definition for ADC_SR register ********************/
+#define ADC_SR_AWD 0x00000001U /*!<Analog watchdog flag */
+#define ADC_SR_EOC 0x00000002U /*!<End of conversion */
+#define ADC_SR_JEOC 0x00000004U /*!<Injected channel end of conversion */
+#define ADC_SR_JSTRT 0x00000008U /*!<Injected channel Start flag */
+#define ADC_SR_STRT 0x00000010U /*!<Regular channel Start flag */
+#define ADC_SR_OVR 0x00000020U /*!<Overrun flag */
+
+/******************* Bit definition for ADC_CR1 register ********************/
+#define ADC_CR1_AWDCH 0x0000001FU /*!<AWDCH[4:0] bits (Analog watchdog channel select bits) */
+#define ADC_CR1_AWDCH_0 0x00000001U /*!<Bit 0 */
+#define ADC_CR1_AWDCH_1 0x00000002U /*!<Bit 1 */
+#define ADC_CR1_AWDCH_2 0x00000004U /*!<Bit 2 */
+#define ADC_CR1_AWDCH_3 0x00000008U /*!<Bit 3 */
+#define ADC_CR1_AWDCH_4 0x00000010U /*!<Bit 4 */
+#define ADC_CR1_EOCIE 0x00000020U /*!<Interrupt enable for EOC */
+#define ADC_CR1_AWDIE 0x00000040U /*!<AAnalog Watchdog interrupt enable */
+#define ADC_CR1_JEOCIE 0x00000080U /*!<Interrupt enable for injected channels */
+#define ADC_CR1_SCAN 0x00000100U /*!<Scan mode */
+#define ADC_CR1_AWDSGL 0x00000200U /*!<Enable the watchdog on a single channel in scan mode */
+#define ADC_CR1_JAUTO 0x00000400U /*!<Automatic injected group conversion */
+#define ADC_CR1_DISCEN 0x00000800U /*!<Discontinuous mode on regular channels */
+#define ADC_CR1_JDISCEN 0x00001000U /*!<Discontinuous mode on injected channels */
+#define ADC_CR1_DISCNUM 0x0000E000U /*!<DISCNUM[2:0] bits (Discontinuous mode channel count) */
+#define ADC_CR1_DISCNUM_0 0x00002000U /*!<Bit 0 */
+#define ADC_CR1_DISCNUM_1 0x00004000U /*!<Bit 1 */
+#define ADC_CR1_DISCNUM_2 0x00008000U /*!<Bit 2 */
+#define ADC_CR1_JAWDEN 0x00400000U /*!<Analog watchdog enable on injected channels */
+#define ADC_CR1_AWDEN 0x00800000U /*!<Analog watchdog enable on regular channels */
+#define ADC_CR1_RES 0x03000000U /*!<RES[2:0] bits (Resolution) */
+#define ADC_CR1_RES_0 0x01000000U /*!<Bit 0 */
+#define ADC_CR1_RES_1 0x02000000U /*!<Bit 1 */
+#define ADC_CR1_OVRIE 0x04000000U /*!<overrun interrupt enable */
+
+/******************* Bit definition for ADC_CR2 register ********************/
+#define ADC_CR2_ADON 0x00000001U /*!<A/D Converter ON / OFF */
+#define ADC_CR2_CONT 0x00000002U /*!<Continuous Conversion */
+#define ADC_CR2_DMA 0x00000100U /*!<Direct Memory access mode */
+#define ADC_CR2_DDS 0x00000200U /*!<DMA disable selection (Single ADC) */
+#define ADC_CR2_EOCS 0x00000400U /*!<End of conversion selection */
+#define ADC_CR2_ALIGN 0x00000800U /*!<Data Alignment */
+#define ADC_CR2_JEXTSEL 0x000F0000U /*!<JEXTSEL[3:0] bits (External event select for injected group) */
+#define ADC_CR2_JEXTSEL_0 0x00010000U /*!<Bit 0 */
+#define ADC_CR2_JEXTSEL_1 0x00020000U /*!<Bit 1 */
+#define ADC_CR2_JEXTSEL_2 0x00040000U /*!<Bit 2 */
+#define ADC_CR2_JEXTSEL_3 0x00080000U /*!<Bit 3 */
+#define ADC_CR2_JEXTEN 0x00300000U /*!<JEXTEN[1:0] bits (External Trigger Conversion mode for injected channelsp) */
+#define ADC_CR2_JEXTEN_0 0x00100000U /*!<Bit 0 */
+#define ADC_CR2_JEXTEN_1 0x00200000U /*!<Bit 1 */
+#define ADC_CR2_JSWSTART 0x00400000U /*!<Start Conversion of injected channels */
+#define ADC_CR2_EXTSEL 0x0F000000U /*!<EXTSEL[3:0] bits (External Event Select for regular group) */
+#define ADC_CR2_EXTSEL_0 0x01000000U /*!<Bit 0 */
+#define ADC_CR2_EXTSEL_1 0x02000000U /*!<Bit 1 */
+#define ADC_CR2_EXTSEL_2 0x04000000U /*!<Bit 2 */
+#define ADC_CR2_EXTSEL_3 0x08000000U /*!<Bit 3 */
+#define ADC_CR2_EXTEN 0x30000000U /*!<EXTEN[1:0] bits (External Trigger Conversion mode for regular channelsp) */
+#define ADC_CR2_EXTEN_0 0x10000000U /*!<Bit 0 */
+#define ADC_CR2_EXTEN_1 0x20000000U /*!<Bit 1 */
+#define ADC_CR2_SWSTART 0x40000000U /*!<Start Conversion of regular channels */
+
+/****************** Bit definition for ADC_SMPR1 register *******************/
+#define ADC_SMPR1_SMP10 0x00000007U /*!<SMP10[2:0] bits (Channel 10 Sample time selection) */
+#define ADC_SMPR1_SMP10_0 0x00000001U /*!<Bit 0 */
+#define ADC_SMPR1_SMP10_1 0x00000002U /*!<Bit 1 */
+#define ADC_SMPR1_SMP10_2 0x00000004U /*!<Bit 2 */
+#define ADC_SMPR1_SMP11 0x00000038U /*!<SMP11[2:0] bits (Channel 11 Sample time selection) */
+#define ADC_SMPR1_SMP11_0 0x00000008U /*!<Bit 0 */
+#define ADC_SMPR1_SMP11_1 0x00000010U /*!<Bit 1 */
+#define ADC_SMPR1_SMP11_2 0x00000020U /*!<Bit 2 */
+#define ADC_SMPR1_SMP12 0x000001C0U /*!<SMP12[2:0] bits (Channel 12 Sample time selection) */
+#define ADC_SMPR1_SMP12_0 0x00000040U /*!<Bit 0 */
+#define ADC_SMPR1_SMP12_1 0x00000080U /*!<Bit 1 */
+#define ADC_SMPR1_SMP12_2 0x00000100U /*!<Bit 2 */
+#define ADC_SMPR1_SMP13 0x00000E00U /*!<SMP13[2:0] bits (Channel 13 Sample time selection) */
+#define ADC_SMPR1_SMP13_0 0x00000200U /*!<Bit 0 */
+#define ADC_SMPR1_SMP13_1 0x00000400U /*!<Bit 1 */
+#define ADC_SMPR1_SMP13_2 0x00000800U /*!<Bit 2 */
+#define ADC_SMPR1_SMP14 0x00007000U /*!<SMP14[2:0] bits (Channel 14 Sample time selection) */
+#define ADC_SMPR1_SMP14_0 0x00001000U /*!<Bit 0 */
+#define ADC_SMPR1_SMP14_1 0x00002000U /*!<Bit 1 */
+#define ADC_SMPR1_SMP14_2 0x00004000U /*!<Bit 2 */
+#define ADC_SMPR1_SMP15 0x00038000U /*!<SMP15[2:0] bits (Channel 15 Sample time selection) */
+#define ADC_SMPR1_SMP15_0 0x00008000U /*!<Bit 0 */
+#define ADC_SMPR1_SMP15_1 0x00010000U /*!<Bit 1 */
+#define ADC_SMPR1_SMP15_2 0x00020000U /*!<Bit 2 */
+#define ADC_SMPR1_SMP16 0x001C0000U /*!<SMP16[2:0] bits (Channel 16 Sample time selection) */
+#define ADC_SMPR1_SMP16_0 0x00040000U /*!<Bit 0 */
+#define ADC_SMPR1_SMP16_1 0x00080000U /*!<Bit 1 */
+#define ADC_SMPR1_SMP16_2 0x00100000U /*!<Bit 2 */
+#define ADC_SMPR1_SMP17 0x00E00000U /*!<SMP17[2:0] bits (Channel 17 Sample time selection) */
+#define ADC_SMPR1_SMP17_0 0x00200000U /*!<Bit 0 */
+#define ADC_SMPR1_SMP17_1 0x00400000U /*!<Bit 1 */
+#define ADC_SMPR1_SMP17_2 0x00800000U /*!<Bit 2 */
+#define ADC_SMPR1_SMP18 0x07000000U /*!<SMP18[2:0] bits (Channel 18 Sample time selection) */
+#define ADC_SMPR1_SMP18_0 0x01000000U /*!<Bit 0 */
+#define ADC_SMPR1_SMP18_1 0x02000000U /*!<Bit 1 */
+#define ADC_SMPR1_SMP18_2 0x04000000U /*!<Bit 2 */
+
+/****************** Bit definition for ADC_SMPR2 register *******************/
+#define ADC_SMPR2_SMP0 0x00000007U /*!<SMP0[2:0] bits (Channel 0 Sample time selection) */
+#define ADC_SMPR2_SMP0_0 0x00000001U /*!<Bit 0 */
+#define ADC_SMPR2_SMP0_1 0x00000002U /*!<Bit 1 */
+#define ADC_SMPR2_SMP0_2 0x00000004U /*!<Bit 2 */
+#define ADC_SMPR2_SMP1 0x00000038U /*!<SMP1[2:0] bits (Channel 1 Sample time selection) */
+#define ADC_SMPR2_SMP1_0 0x00000008U /*!<Bit 0 */
+#define ADC_SMPR2_SMP1_1 0x00000010U /*!<Bit 1 */
+#define ADC_SMPR2_SMP1_2 0x00000020U /*!<Bit 2 */
+#define ADC_SMPR2_SMP2 0x000001C0U /*!<SMP2[2:0] bits (Channel 2 Sample time selection) */
+#define ADC_SMPR2_SMP2_0 0x00000040U /*!<Bit 0 */
+#define ADC_SMPR2_SMP2_1 0x00000080U /*!<Bit 1 */
+#define ADC_SMPR2_SMP2_2 0x00000100U /*!<Bit 2 */
+#define ADC_SMPR2_SMP3 0x00000E00U /*!<SMP3[2:0] bits (Channel 3 Sample time selection) */
+#define ADC_SMPR2_SMP3_0 0x00000200U /*!<Bit 0 */
+#define ADC_SMPR2_SMP3_1 0x00000400U /*!<Bit 1 */
+#define ADC_SMPR2_SMP3_2 0x00000800U /*!<Bit 2 */
+#define ADC_SMPR2_SMP4 0x00007000U /*!<SMP4[2:0] bits (Channel 4 Sample time selection) */
+#define ADC_SMPR2_SMP4_0 0x00001000U /*!<Bit 0 */
+#define ADC_SMPR2_SMP4_1 0x00002000U /*!<Bit 1 */
+#define ADC_SMPR2_SMP4_2 0x00004000U /*!<Bit 2 */
+#define ADC_SMPR2_SMP5 0x00038000U /*!<SMP5[2:0] bits (Channel 5 Sample time selection) */
+#define ADC_SMPR2_SMP5_0 0x00008000U /*!<Bit 0 */
+#define ADC_SMPR2_SMP5_1 0x00010000U /*!<Bit 1 */
+#define ADC_SMPR2_SMP5_2 0x00020000U /*!<Bit 2 */
+#define ADC_SMPR2_SMP6 0x001C0000U /*!<SMP6[2:0] bits (Channel 6 Sample time selection) */
+#define ADC_SMPR2_SMP6_0 0x00040000U /*!<Bit 0 */
+#define ADC_SMPR2_SMP6_1 0x00080000U /*!<Bit 1 */
+#define ADC_SMPR2_SMP6_2 0x00100000U /*!<Bit 2 */
+#define ADC_SMPR2_SMP7 0x00E00000U /*!<SMP7[2:0] bits (Channel 7 Sample time selection) */
+#define ADC_SMPR2_SMP7_0 0x00200000U /*!<Bit 0 */
+#define ADC_SMPR2_SMP7_1 0x00400000U /*!<Bit 1 */
+#define ADC_SMPR2_SMP7_2 0x00800000U /*!<Bit 2 */
+#define ADC_SMPR2_SMP8 0x07000000U /*!<SMP8[2:0] bits (Channel 8 Sample time selection) */
+#define ADC_SMPR2_SMP8_0 0x01000000U /*!<Bit 0 */
+#define ADC_SMPR2_SMP8_1 0x02000000U /*!<Bit 1 */
+#define ADC_SMPR2_SMP8_2 0x04000000U /*!<Bit 2 */
+#define ADC_SMPR2_SMP9 0x38000000U /*!<SMP9[2:0] bits (Channel 9 Sample time selection) */
+#define ADC_SMPR2_SMP9_0 0x08000000U /*!<Bit 0 */
+#define ADC_SMPR2_SMP9_1 0x10000000U /*!<Bit 1 */
+#define ADC_SMPR2_SMP9_2 0x20000000U /*!<Bit 2 */
+
+/****************** Bit definition for ADC_JOFR1 register *******************/
+#define ADC_JOFR1_JOFFSET1 0x0FFFU /*!<Data offset for injected channel 1 */
+
+/****************** Bit definition for ADC_JOFR2 register *******************/
+#define ADC_JOFR2_JOFFSET2 0x0FFFU /*!<Data offset for injected channel 2 */
+
+/****************** Bit definition for ADC_JOFR3 register *******************/
+#define ADC_JOFR3_JOFFSET3 0x0FFFU /*!<Data offset for injected channel 3 */
+
+/****************** Bit definition for ADC_JOFR4 register *******************/
+#define ADC_JOFR4_JOFFSET4 0x0FFFU /*!<Data offset for injected channel 4 */
+
+/******************* Bit definition for ADC_HTR register ********************/
+#define ADC_HTR_HT 0x0FFFU /*!<Analog watchdog high threshold */
+
+/******************* Bit definition for ADC_LTR register ********************/
+#define ADC_LTR_LT 0x0FFFU /*!<Analog watchdog low threshold */
+
+/******************* Bit definition for ADC_SQR1 register *******************/
+#define ADC_SQR1_SQ13 0x0000001FU /*!<SQ13[4:0] bits (13th conversion in regular sequence) */
+#define ADC_SQR1_SQ13_0 0x00000001U /*!<Bit 0 */
+#define ADC_SQR1_SQ13_1 0x00000002U /*!<Bit 1 */
+#define ADC_SQR1_SQ13_2 0x00000004U /*!<Bit 2 */
+#define ADC_SQR1_SQ13_3 0x00000008U /*!<Bit 3 */
+#define ADC_SQR1_SQ13_4 0x00000010U /*!<Bit 4 */
+#define ADC_SQR1_SQ14 0x000003E0U /*!<SQ14[4:0] bits (14th conversion in regular sequence) */
+#define ADC_SQR1_SQ14_0 0x00000020U /*!<Bit 0 */
+#define ADC_SQR1_SQ14_1 0x00000040U /*!<Bit 1 */
+#define ADC_SQR1_SQ14_2 0x00000080U /*!<Bit 2 */
+#define ADC_SQR1_SQ14_3 0x00000100U /*!<Bit 3 */
+#define ADC_SQR1_SQ14_4 0x00000200U /*!<Bit 4 */
+#define ADC_SQR1_SQ15 0x00007C00U /*!<SQ15[4:0] bits (15th conversion in regular sequence) */
+#define ADC_SQR1_SQ15_0 0x00000400U /*!<Bit 0 */
+#define ADC_SQR1_SQ15_1 0x00000800U /*!<Bit 1 */
+#define ADC_SQR1_SQ15_2 0x00001000U /*!<Bit 2 */
+#define ADC_SQR1_SQ15_3 0x00002000U /*!<Bit 3 */
+#define ADC_SQR1_SQ15_4 0x00004000U /*!<Bit 4 */
+#define ADC_SQR1_SQ16 0x000F8000U /*!<SQ16[4:0] bits (16th conversion in regular sequence) */
+#define ADC_SQR1_SQ16_0 0x00008000U /*!<Bit 0 */
+#define ADC_SQR1_SQ16_1 0x00010000U /*!<Bit 1 */
+#define ADC_SQR1_SQ16_2 0x00020000U /*!<Bit 2 */
+#define ADC_SQR1_SQ16_3 0x00040000U /*!<Bit 3 */
+#define ADC_SQR1_SQ16_4 0x00080000U /*!<Bit 4 */
+#define ADC_SQR1_L 0x00F00000U /*!<L[3:0] bits (Regular channel sequence length) */
+#define ADC_SQR1_L_0 0x00100000U /*!<Bit 0 */
+#define ADC_SQR1_L_1 0x00200000U /*!<Bit 1 */
+#define ADC_SQR1_L_2 0x00400000U /*!<Bit 2 */
+#define ADC_SQR1_L_3 0x00800000U /*!<Bit 3 */
+
+/******************* Bit definition for ADC_SQR2 register *******************/
+#define ADC_SQR2_SQ7 0x0000001FU /*!<SQ7[4:0] bits (7th conversion in regular sequence) */
+#define ADC_SQR2_SQ7_0 0x00000001U /*!<Bit 0 */
+#define ADC_SQR2_SQ7_1 0x00000002U /*!<Bit 1 */
+#define ADC_SQR2_SQ7_2 0x00000004U /*!<Bit 2 */
+#define ADC_SQR2_SQ7_3 0x00000008U /*!<Bit 3 */
+#define ADC_SQR2_SQ7_4 0x00000010U /*!<Bit 4 */
+#define ADC_SQR2_SQ8 0x000003E0U /*!<SQ8[4:0] bits (8th conversion in regular sequence) */
+#define ADC_SQR2_SQ8_0 0x00000020U /*!<Bit 0 */
+#define ADC_SQR2_SQ8_1 0x00000040U /*!<Bit 1 */
+#define ADC_SQR2_SQ8_2 0x00000080U /*!<Bit 2 */
+#define ADC_SQR2_SQ8_3 0x00000100U /*!<Bit 3 */
+#define ADC_SQR2_SQ8_4 0x00000200U /*!<Bit 4 */
+#define ADC_SQR2_SQ9 0x00007C00U /*!<SQ9[4:0] bits (9th conversion in regular sequence) */
+#define ADC_SQR2_SQ9_0 0x00000400U /*!<Bit 0 */
+#define ADC_SQR2_SQ9_1 0x00000800U /*!<Bit 1 */
+#define ADC_SQR2_SQ9_2 0x00001000U /*!<Bit 2 */
+#define ADC_SQR2_SQ9_3 0x00002000U /*!<Bit 3 */
+#define ADC_SQR2_SQ9_4 0x00004000U /*!<Bit 4 */
+#define ADC_SQR2_SQ10 0x000F8000U /*!<SQ10[4:0] bits (10th conversion in regular sequence) */
+#define ADC_SQR2_SQ10_0 0x00008000U /*!<Bit 0 */
+#define ADC_SQR2_SQ10_1 0x00010000U /*!<Bit 1 */
+#define ADC_SQR2_SQ10_2 0x00020000U /*!<Bit 2 */
+#define ADC_SQR2_SQ10_3 0x00040000U /*!<Bit 3 */
+#define ADC_SQR2_SQ10_4 0x00080000U /*!<Bit 4 */
+#define ADC_SQR2_SQ11 0x01F00000U /*!<SQ11[4:0] bits (11th conversion in regular sequence) */
+#define ADC_SQR2_SQ11_0 0x00100000U /*!<Bit 0 */
+#define ADC_SQR2_SQ11_1 0x00200000U /*!<Bit 1 */
+#define ADC_SQR2_SQ11_2 0x00400000U /*!<Bit 2 */
+#define ADC_SQR2_SQ11_3 0x00800000U /*!<Bit 3 */
+#define ADC_SQR2_SQ11_4 0x01000000U /*!<Bit 4 */
+#define ADC_SQR2_SQ12 0x3E000000U /*!<SQ12[4:0] bits (12th conversion in regular sequence) */
+#define ADC_SQR2_SQ12_0 0x02000000U /*!<Bit 0 */
+#define ADC_SQR2_SQ12_1 0x04000000U /*!<Bit 1 */
+#define ADC_SQR2_SQ12_2 0x08000000U /*!<Bit 2 */
+#define ADC_SQR2_SQ12_3 0x10000000U /*!<Bit 3 */
+#define ADC_SQR2_SQ12_4 0x20000000U /*!<Bit 4 */
+
+/******************* Bit definition for ADC_SQR3 register *******************/
+#define ADC_SQR3_SQ1 0x0000001FU /*!<SQ1[4:0] bits (1st conversion in regular sequence) */
+#define ADC_SQR3_SQ1_0 0x00000001U /*!<Bit 0 */
+#define ADC_SQR3_SQ1_1 0x00000002U /*!<Bit 1 */
+#define ADC_SQR3_SQ1_2 0x00000004U /*!<Bit 2 */
+#define ADC_SQR3_SQ1_3 0x00000008U /*!<Bit 3 */
+#define ADC_SQR3_SQ1_4 0x00000010U /*!<Bit 4 */
+#define ADC_SQR3_SQ2 0x000003E0U /*!<SQ2[4:0] bits (2nd conversion in regular sequence) */
+#define ADC_SQR3_SQ2_0 0x00000020U /*!<Bit 0 */
+#define ADC_SQR3_SQ2_1 0x00000040U /*!<Bit 1 */
+#define ADC_SQR3_SQ2_2 0x00000080U /*!<Bit 2 */
+#define ADC_SQR3_SQ2_3 0x00000100U /*!<Bit 3 */
+#define ADC_SQR3_SQ2_4 0x00000200U /*!<Bit 4 */
+#define ADC_SQR3_SQ3 0x00007C00U /*!<SQ3[4:0] bits (3rd conversion in regular sequence) */
+#define ADC_SQR3_SQ3_0 0x00000400U /*!<Bit 0 */
+#define ADC_SQR3_SQ3_1 0x00000800U /*!<Bit 1 */
+#define ADC_SQR3_SQ3_2 0x00001000U /*!<Bit 2 */
+#define ADC_SQR3_SQ3_3 0x00002000U /*!<Bit 3 */
+#define ADC_SQR3_SQ3_4 0x00004000U /*!<Bit 4 */
+#define ADC_SQR3_SQ4 0x000F8000U /*!<SQ4[4:0] bits (4th conversion in regular sequence) */
+#define ADC_SQR3_SQ4_0 0x00008000U /*!<Bit 0 */
+#define ADC_SQR3_SQ4_1 0x00010000U /*!<Bit 1 */
+#define ADC_SQR3_SQ4_2 0x00020000U /*!<Bit 2 */
+#define ADC_SQR3_SQ4_3 0x00040000U /*!<Bit 3 */
+#define ADC_SQR3_SQ4_4 0x00080000U /*!<Bit 4 */
+#define ADC_SQR3_SQ5 0x01F00000U /*!<SQ5[4:0] bits (5th conversion in regular sequence) */
+#define ADC_SQR3_SQ5_0 0x00100000U /*!<Bit 0 */
+#define ADC_SQR3_SQ5_1 0x00200000U /*!<Bit 1 */
+#define ADC_SQR3_SQ5_2 0x00400000U /*!<Bit 2 */
+#define ADC_SQR3_SQ5_3 0x00800000U /*!<Bit 3 */
+#define ADC_SQR3_SQ5_4 0x01000000U /*!<Bit 4 */
+#define ADC_SQR3_SQ6 0x3E000000U /*!<SQ6[4:0] bits (6th conversion in regular sequence) */
+#define ADC_SQR3_SQ6_0 0x02000000U /*!<Bit 0 */
+#define ADC_SQR3_SQ6_1 0x04000000U /*!<Bit 1 */
+#define ADC_SQR3_SQ6_2 0x08000000U /*!<Bit 2 */
+#define ADC_SQR3_SQ6_3 0x10000000U /*!<Bit 3 */
+#define ADC_SQR3_SQ6_4 0x20000000U /*!<Bit 4 */
+
+/******************* Bit definition for ADC_JSQR register *******************/
+#define ADC_JSQR_JSQ1 0x0000001FU /*!<JSQ1[4:0] bits (1st conversion in injected sequence) */
+#define ADC_JSQR_JSQ1_0 0x00000001U /*!<Bit 0 */
+#define ADC_JSQR_JSQ1_1 0x00000002U /*!<Bit 1 */
+#define ADC_JSQR_JSQ1_2 0x00000004U /*!<Bit 2 */
+#define ADC_JSQR_JSQ1_3 0x00000008U /*!<Bit 3 */
+#define ADC_JSQR_JSQ1_4 0x00000010U /*!<Bit 4 */
+#define ADC_JSQR_JSQ2 0x000003E0U /*!<JSQ2[4:0] bits (2nd conversion in injected sequence) */
+#define ADC_JSQR_JSQ2_0 0x00000020U /*!<Bit 0 */
+#define ADC_JSQR_JSQ2_1 0x00000040U /*!<Bit 1 */
+#define ADC_JSQR_JSQ2_2 0x00000080U /*!<Bit 2 */
+#define ADC_JSQR_JSQ2_3 0x00000100U /*!<Bit 3 */
+#define ADC_JSQR_JSQ2_4 0x00000200U /*!<Bit 4 */
+#define ADC_JSQR_JSQ3 0x00007C00U /*!<JSQ3[4:0] bits (3rd conversion in injected sequence) */
+#define ADC_JSQR_JSQ3_0 0x00000400U /*!<Bit 0 */
+#define ADC_JSQR_JSQ3_1 0x00000800U /*!<Bit 1 */
+#define ADC_JSQR_JSQ3_2 0x00001000U /*!<Bit 2 */
+#define ADC_JSQR_JSQ3_3 0x00002000U /*!<Bit 3 */
+#define ADC_JSQR_JSQ3_4 0x00004000U /*!<Bit 4 */
+#define ADC_JSQR_JSQ4 0x000F8000U /*!<JSQ4[4:0] bits (4th conversion in injected sequence) */
+#define ADC_JSQR_JSQ4_0 0x00008000U /*!<Bit 0 */
+#define ADC_JSQR_JSQ4_1 0x00010000U /*!<Bit 1 */
+#define ADC_JSQR_JSQ4_2 0x00020000U /*!<Bit 2 */
+#define ADC_JSQR_JSQ4_3 0x00040000U /*!<Bit 3 */
+#define ADC_JSQR_JSQ4_4 0x00080000U /*!<Bit 4 */
+#define ADC_JSQR_JL 0x00300000U /*!<JL[1:0] bits (Injected Sequence length) */
+#define ADC_JSQR_JL_0 0x00100000U /*!<Bit 0 */
+#define ADC_JSQR_JL_1 0x00200000U /*!<Bit 1 */
+
+/******************* Bit definition for ADC_JDR1 register *******************/
+#define ADC_JDR1_JDATA 0xFFFFU /*!<Injected data */
+
+/******************* Bit definition for ADC_JDR2 register *******************/
+#define ADC_JDR2_JDATA 0xFFFFU /*!<Injected data */
+
+/******************* Bit definition for ADC_JDR3 register *******************/
+#define ADC_JDR3_JDATA 0xFFFFU /*!<Injected data */
+
+/******************* Bit definition for ADC_JDR4 register *******************/
+#define ADC_JDR4_JDATA 0xFFFFU /*!<Injected data */
+
+/******************** Bit definition for ADC_DR register ********************/
+#define ADC_DR_DATA 0x0000FFFFU /*!<Regular data */
+#define ADC_DR_ADC2DATA 0xFFFF0000U /*!<ADC2 data */
+
+/******************* Bit definition for ADC_CSR register ********************/
+#define ADC_CSR_AWD1 0x00000001U /*!<ADC1 Analog watchdog flag */
+#define ADC_CSR_EOC1 0x00000002U /*!<ADC1 End of conversion */
+#define ADC_CSR_JEOC1 0x00000004U /*!<ADC1 Injected channel end of conversion */
+#define ADC_CSR_JSTRT1 0x00000008U /*!<ADC1 Injected channel Start flag */
+#define ADC_CSR_STRT1 0x00000010U /*!<ADC1 Regular channel Start flag */
+#define ADC_CSR_OVR1 0x00000020U /*!<ADC1 DMA overrun flag */
+#define ADC_CSR_AWD2 0x00000100U /*!<ADC2 Analog watchdog flag */
+#define ADC_CSR_EOC2 0x00000200U /*!<ADC2 End of conversion */
+#define ADC_CSR_JEOC2 0x00000400U /*!<ADC2 Injected channel end of conversion */
+#define ADC_CSR_JSTRT2 0x00000800U /*!<ADC2 Injected channel Start flag */
+#define ADC_CSR_STRT2 0x00001000U /*!<ADC2 Regular channel Start flag */
+#define ADC_CSR_OVR2 0x00002000U /*!<ADC2 DMA overrun flag */
+#define ADC_CSR_AWD3 0x00010000U /*!<ADC3 Analog watchdog flag */
+#define ADC_CSR_EOC3 0x00020000U /*!<ADC3 End of conversion */
+#define ADC_CSR_JEOC3 0x00040000U /*!<ADC3 Injected channel end of conversion */
+#define ADC_CSR_JSTRT3 0x00080000U /*!<ADC3 Injected channel Start flag */
+#define ADC_CSR_STRT3 0x00100000U /*!<ADC3 Regular channel Start flag */
+#define ADC_CSR_OVR3 0x00200000U /*!<ADC3 DMA overrun flag */
+
+/* Legacy defines */
+#define ADC_CSR_DOVR1 ADC_CSR_OVR1
+#define ADC_CSR_DOVR2 ADC_CSR_OVR2
+#define ADC_CSR_DOVR3 ADC_CSR_OVR3
+
+/******************* Bit definition for ADC_CCR register ********************/
+#define ADC_CCR_MULTI 0x0000001FU /*!<MULTI[4:0] bits (Multi-ADC mode selection) */
+#define ADC_CCR_MULTI_0 0x00000001U /*!<Bit 0 */
+#define ADC_CCR_MULTI_1 0x00000002U /*!<Bit 1 */
+#define ADC_CCR_MULTI_2 0x00000004U /*!<Bit 2 */
+#define ADC_CCR_MULTI_3 0x00000008U /*!<Bit 3 */
+#define ADC_CCR_MULTI_4 0x00000010U /*!<Bit 4 */
+#define ADC_CCR_DELAY 0x00000F00U /*!<DELAY[3:0] bits (Delay between 2 sampling phases) */
+#define ADC_CCR_DELAY_0 0x00000100U /*!<Bit 0 */
+#define ADC_CCR_DELAY_1 0x00000200U /*!<Bit 1 */
+#define ADC_CCR_DELAY_2 0x00000400U /*!<Bit 2 */
+#define ADC_CCR_DELAY_3 0x00000800U /*!<Bit 3 */
+#define ADC_CCR_DDS 0x00002000U /*!<DMA disable selection (Multi-ADC mode) */
+#define ADC_CCR_DMA 0x0000C000U /*!<DMA[1:0] bits (Direct Memory Access mode for multimode) */
+#define ADC_CCR_DMA_0 0x00004000U /*!<Bit 0 */
+#define ADC_CCR_DMA_1 0x00008000U /*!<Bit 1 */
+#define ADC_CCR_ADCPRE 0x00030000U /*!<ADCPRE[1:0] bits (ADC prescaler) */
+#define ADC_CCR_ADCPRE_0 0x00010000U /*!<Bit 0 */
+#define ADC_CCR_ADCPRE_1 0x00020000U /*!<Bit 1 */
+#define ADC_CCR_VBATE 0x00400000U /*!<VBAT Enable */
+#define ADC_CCR_TSVREFE 0x00800000U /*!<Temperature Sensor and VREFINT Enable */
+
+/******************* Bit definition for ADC_CDR register ********************/
+#define ADC_CDR_DATA1 0x0000FFFFU /*!<1st data of a pair of regular conversions */
+#define ADC_CDR_DATA2 0xFFFF0000U /*!<2nd data of a pair of regular conversions */
+
+/******************************************************************************/
+/* */
+/* Controller Area Network */
+/* */
+/******************************************************************************/
+/*!<CAN control and status registers */
+/******************* Bit definition for CAN_MCR register ********************/
+#define CAN_MCR_INRQ 0x00000001U /*!<Initialization Request */
+#define CAN_MCR_SLEEP 0x00000002U /*!<Sleep Mode Request */
+#define CAN_MCR_TXFP 0x00000004U /*!<Transmit FIFO Priority */
+#define CAN_MCR_RFLM 0x00000008U /*!<Receive FIFO Locked Mode */
+#define CAN_MCR_NART 0x00000010U /*!<No Automatic Retransmission */
+#define CAN_MCR_AWUM 0x00000020U /*!<Automatic Wakeup Mode */
+#define CAN_MCR_ABOM 0x00000040U /*!<Automatic Bus-Off Management */
+#define CAN_MCR_TTCM 0x00000080U /*!<Time Triggered Communication Mode */
+#define CAN_MCR_RESET 0x00008000U /*!<bxCAN software master reset */
+#define CAN_MCR_DBF 0x00010000U /*!<bxCAN Debug freeze */
+/******************* Bit definition for CAN_MSR register ********************/
+#define CAN_MSR_INAK 0x0001U /*!<Initialization Acknowledge */
+#define CAN_MSR_SLAK 0x0002U /*!<Sleep Acknowledge */
+#define CAN_MSR_ERRI 0x0004U /*!<Error Interrupt */
+#define CAN_MSR_WKUI 0x0008U /*!<Wakeup Interrupt */
+#define CAN_MSR_SLAKI 0x0010U /*!<Sleep Acknowledge Interrupt */
+#define CAN_MSR_TXM 0x0100U /*!<Transmit Mode */
+#define CAN_MSR_RXM 0x0200U /*!<Receive Mode */
+#define CAN_MSR_SAMP 0x0400U /*!<Last Sample Point */
+#define CAN_MSR_RX 0x0800U /*!<CAN Rx Signal */
+
+/******************* Bit definition for CAN_TSR register ********************/
+#define CAN_TSR_RQCP0 0x00000001U /*!<Request Completed Mailbox0 */
+#define CAN_TSR_TXOK0 0x00000002U /*!<Transmission OK of Mailbox0 */
+#define CAN_TSR_ALST0 0x00000004U /*!<Arbitration Lost for Mailbox0 */
+#define CAN_TSR_TERR0 0x00000008U /*!<Transmission Error of Mailbox0 */
+#define CAN_TSR_ABRQ0 0x00000080U /*!<Abort Request for Mailbox0 */
+#define CAN_TSR_RQCP1 0x00000100U /*!<Request Completed Mailbox1 */
+#define CAN_TSR_TXOK1 0x00000200U /*!<Transmission OK of Mailbox1 */
+#define CAN_TSR_ALST1 0x00000400U /*!<Arbitration Lost for Mailbox1 */
+#define CAN_TSR_TERR1 0x00000800U /*!<Transmission Error of Mailbox1 */
+#define CAN_TSR_ABRQ1 0x00008000U /*!<Abort Request for Mailbox 1 */
+#define CAN_TSR_RQCP2 0x00010000U /*!<Request Completed Mailbox2 */
+#define CAN_TSR_TXOK2 0x00020000U /*!<Transmission OK of Mailbox 2 */
+#define CAN_TSR_ALST2 0x00040000U /*!<Arbitration Lost for mailbox 2 */
+#define CAN_TSR_TERR2 0x00080000U /*!<Transmission Error of Mailbox 2 */
+#define CAN_TSR_ABRQ2 0x00800000U /*!<Abort Request for Mailbox 2 */
+#define CAN_TSR_CODE 0x03000000U /*!<Mailbox Code */
+
+#define CAN_TSR_TME 0x1C000000U /*!<TME[2:0] bits */
+#define CAN_TSR_TME0 0x04000000U /*!<Transmit Mailbox 0 Empty */
+#define CAN_TSR_TME1 0x08000000U /*!<Transmit Mailbox 1 Empty */
+#define CAN_TSR_TME2 0x10000000U /*!<Transmit Mailbox 2 Empty */
+
+#define CAN_TSR_LOW 0xE0000000U /*!<LOW[2:0] bits */
+#define CAN_TSR_LOW0 0x20000000U /*!<Lowest Priority Flag for Mailbox 0 */
+#define CAN_TSR_LOW1 0x40000000U /*!<Lowest Priority Flag for Mailbox 1 */
+#define CAN_TSR_LOW2 0x80000000U /*!<Lowest Priority Flag for Mailbox 2 */
+
+/******************* Bit definition for CAN_RF0R register *******************/
+#define CAN_RF0R_FMP0 0x03U /*!<FIFO 0 Message Pending */
+#define CAN_RF0R_FULL0 0x08U /*!<FIFO 0 Full */
+#define CAN_RF0R_FOVR0 0x10U /*!<FIFO 0 Overrun */
+#define CAN_RF0R_RFOM0 0x20U /*!<Release FIFO 0 Output Mailbox */
+
+/******************* Bit definition for CAN_RF1R register *******************/
+#define CAN_RF1R_FMP1 0x03U /*!<FIFO 1 Message Pending */
+#define CAN_RF1R_FULL1 0x08U /*!<FIFO 1 Full */
+#define CAN_RF1R_FOVR1 0x10U /*!<FIFO 1 Overrun */
+#define CAN_RF1R_RFOM1 0x20U /*!<Release FIFO 1 Output Mailbox */
+
+/******************** Bit definition for CAN_IER register *******************/
+#define CAN_IER_TMEIE 0x00000001U /*!<Transmit Mailbox Empty Interrupt Enable */
+#define CAN_IER_FMPIE0 0x00000002U /*!<FIFO Message Pending Interrupt Enable */
+#define CAN_IER_FFIE0 0x00000004U /*!<FIFO Full Interrupt Enable */
+#define CAN_IER_FOVIE0 0x00000008U /*!<FIFO Overrun Interrupt Enable */
+#define CAN_IER_FMPIE1 0x00000010U /*!<FIFO Message Pending Interrupt Enable */
+#define CAN_IER_FFIE1 0x00000020U /*!<FIFO Full Interrupt Enable */
+#define CAN_IER_FOVIE1 0x00000040U /*!<FIFO Overrun Interrupt Enable */
+#define CAN_IER_EWGIE 0x00000100U /*!<Error Warning Interrupt Enable */
+#define CAN_IER_EPVIE 0x00000200U /*!<Error Passive Interrupt Enable */
+#define CAN_IER_BOFIE 0x00000400U /*!<Bus-Off Interrupt Enable */
+#define CAN_IER_LECIE 0x00000800U /*!<Last Error Code Interrupt Enable */
+#define CAN_IER_ERRIE 0x00008000U /*!<Error Interrupt Enable */
+#define CAN_IER_WKUIE 0x00010000U /*!<Wakeup Interrupt Enable */
+#define CAN_IER_SLKIE 0x00020000U /*!<Sleep Interrupt Enable */
+#define CAN_IER_EWGIE 0x00000100U /*!<Error warning interrupt enable */
+#define CAN_IER_EPVIE 0x00000200U /*!<Error passive interrupt enable */
+#define CAN_IER_BOFIE 0x00000400U /*!<Bus-off interrupt enable */
+#define CAN_IER_LECIE 0x00000800U /*!<Last error code interrupt enable */
+#define CAN_IER_ERRIE 0x00008000U /*!<Error interrupt enable */
+
+
+/******************** Bit definition for CAN_ESR register *******************/
+#define CAN_ESR_EWGF 0x00000001U /*!<Error Warning Flag */
+#define CAN_ESR_EPVF 0x00000002U /*!<Error Passive Flag */
+#define CAN_ESR_BOFF 0x00000004U /*!<Bus-Off Flag */
+
+#define CAN_ESR_LEC 0x00000070U /*!<LEC[2:0] bits (Last Error Code) */
+#define CAN_ESR_LEC_0 0x00000010U /*!<Bit 0 */
+#define CAN_ESR_LEC_1 0x00000020U /*!<Bit 1 */
+#define CAN_ESR_LEC_2 0x00000040U /*!<Bit 2 */
+
+#define CAN_ESR_TEC 0x00FF0000U /*!<Least significant byte of the 9-bit Transmit Error Counter */
+#define CAN_ESR_REC 0xFF000000U /*!<Receive Error Counter */
+
+/******************* Bit definition for CAN_BTR register ********************/
+#define CAN_BTR_BRP 0x000003FFU /*!<Baud Rate Prescaler */
+#define CAN_BTR_TS1 0x000F0000U /*!<Time Segment 1 */
+#define CAN_BTR_TS1_0 0x00010000U /*!<Bit 0 */
+#define CAN_BTR_TS1_1 0x00020000U /*!<Bit 1 */
+#define CAN_BTR_TS1_2 0x00040000U /*!<Bit 2 */
+#define CAN_BTR_TS1_3 0x00080000U /*!<Bit 3 */
+#define CAN_BTR_TS2 0x00700000U /*!<Time Segment 2 */
+#define CAN_BTR_TS2_0 0x00100000U /*!<Bit 0 */
+#define CAN_BTR_TS2_1 0x00200000U /*!<Bit 1 */
+#define CAN_BTR_TS2_2 0x00400000U /*!<Bit 2 */
+#define CAN_BTR_SJW 0x03000000U /*!<Resynchronization Jump Width */
+#define CAN_BTR_SJW_0 0x01000000U /*!<Bit 0 */
+#define CAN_BTR_SJW_1 0x02000000U /*!<Bit 1 */
+#define CAN_BTR_LBKM 0x40000000U /*!<Loop Back Mode (Debug) */
+#define CAN_BTR_SILM 0x80000000U /*!<Silent Mode */
+
+
+/*!<Mailbox registers */
+/****************** Bit definition for CAN_TI0R register ********************/
+#define CAN_TI0R_TXRQ 0x00000001U /*!<Transmit Mailbox Request */
+#define CAN_TI0R_RTR 0x00000002U /*!<Remote Transmission Request */
+#define CAN_TI0R_IDE 0x00000004U /*!<Identifier Extension */
+#define CAN_TI0R_EXID 0x001FFFF8U /*!<Extended Identifier */
+#define CAN_TI0R_STID 0xFFE00000U /*!<Standard Identifier or Extended Identifier */
+
+/****************** Bit definition for CAN_TDT0R register *******************/
+#define CAN_TDT0R_DLC 0x0000000FU /*!<Data Length Code */
+#define CAN_TDT0R_TGT 0x00000100U /*!<Transmit Global Time */
+#define CAN_TDT0R_TIME 0xFFFF0000U /*!<Message Time Stamp */
+
+/****************** Bit definition for CAN_TDL0R register *******************/
+#define CAN_TDL0R_DATA0 0x000000FFU /*!<Data byte 0 */
+#define CAN_TDL0R_DATA1 0x0000FF00U /*!<Data byte 1 */
+#define CAN_TDL0R_DATA2 0x00FF0000U /*!<Data byte 2 */
+#define CAN_TDL0R_DATA3 0xFF000000U /*!<Data byte 3 */
+
+/****************** Bit definition for CAN_TDH0R register *******************/
+#define CAN_TDH0R_DATA4 0x000000FFU /*!<Data byte 4 */
+#define CAN_TDH0R_DATA5 0x0000FF00U /*!<Data byte 5 */
+#define CAN_TDH0R_DATA6 0x00FF0000U /*!<Data byte 6 */
+#define CAN_TDH0R_DATA7 0xFF000000U /*!<Data byte 7 */
+
+/******************* Bit definition for CAN_TI1R register *******************/
+#define CAN_TI1R_TXRQ 0x00000001U /*!<Transmit Mailbox Request */
+#define CAN_TI1R_RTR 0x00000002U /*!<Remote Transmission Request */
+#define CAN_TI1R_IDE 0x00000004U /*!<Identifier Extension */
+#define CAN_TI1R_EXID 0x001FFFF8U /*!<Extended Identifier */
+#define CAN_TI1R_STID 0xFFE00000U /*!<Standard Identifier or Extended Identifier */
+
+/******************* Bit definition for CAN_TDT1R register ******************/
+#define CAN_TDT1R_DLC 0x0000000FU /*!<Data Length Code */
+#define CAN_TDT1R_TGT 0x00000100U /*!<Transmit Global Time */
+#define CAN_TDT1R_TIME 0xFFFF0000U /*!<Message Time Stamp */
+
+/******************* Bit definition for CAN_TDL1R register ******************/
+#define CAN_TDL1R_DATA0 0x000000FFU /*!<Data byte 0 */
+#define CAN_TDL1R_DATA1 0x0000FF00U /*!<Data byte 1 */
+#define CAN_TDL1R_DATA2 0x00FF0000U /*!<Data byte 2 */
+#define CAN_TDL1R_DATA3 0xFF000000U /*!<Data byte 3 */
+
+/******************* Bit definition for CAN_TDH1R register ******************/
+#define CAN_TDH1R_DATA4 0x000000FFU /*!<Data byte 4 */
+#define CAN_TDH1R_DATA5 0x0000FF00U /*!<Data byte 5 */
+#define CAN_TDH1R_DATA6 0x00FF0000U /*!<Data byte 6 */
+#define CAN_TDH1R_DATA7 0xFF000000U /*!<Data byte 7 */
+
+/******************* Bit definition for CAN_TI2R register *******************/
+#define CAN_TI2R_TXRQ 0x00000001U /*!<Transmit Mailbox Request */
+#define CAN_TI2R_RTR 0x00000002U /*!<Remote Transmission Request */
+#define CAN_TI2R_IDE 0x00000004U /*!<Identifier Extension */
+#define CAN_TI2R_EXID 0x001FFFF8U /*!<Extended identifier */
+#define CAN_TI2R_STID 0xFFE00000U /*!<Standard Identifier or Extended Identifier */
+
+/******************* Bit definition for CAN_TDT2R register ******************/
+#define CAN_TDT2R_DLC 0x0000000FU /*!<Data Length Code */
+#define CAN_TDT2R_TGT 0x00000100U /*!<Transmit Global Time */
+#define CAN_TDT2R_TIME 0xFFFF0000U /*!<Message Time Stamp */
+
+/******************* Bit definition for CAN_TDL2R register ******************/
+#define CAN_TDL2R_DATA0 0x000000FFU /*!<Data byte 0 */
+#define CAN_TDL2R_DATA1 0x0000FF00U /*!<Data byte 1 */
+#define CAN_TDL2R_DATA2 0x00FF0000U /*!<Data byte 2 */
+#define CAN_TDL2R_DATA3 0xFF000000U /*!<Data byte 3 */
+
+/******************* Bit definition for CAN_TDH2R register ******************/
+#define CAN_TDH2R_DATA4 0x000000FFU /*!<Data byte 4 */
+#define CAN_TDH2R_DATA5 0x0000FF00U /*!<Data byte 5 */
+#define CAN_TDH2R_DATA6 0x00FF0000U /*!<Data byte 6 */
+#define CAN_TDH2R_DATA7 0xFF000000U /*!<Data byte 7 */
+
+/******************* Bit definition for CAN_RI0R register *******************/
+#define CAN_RI0R_RTR 0x00000002U /*!<Remote Transmission Request */
+#define CAN_RI0R_IDE 0x00000004U /*!<Identifier Extension */
+#define CAN_RI0R_EXID 0x001FFFF8U /*!<Extended Identifier */
+#define CAN_RI0R_STID 0xFFE00000U /*!<Standard Identifier or Extended Identifier */
+
+/******************* Bit definition for CAN_RDT0R register ******************/
+#define CAN_RDT0R_DLC 0x0000000FU /*!<Data Length Code */
+#define CAN_RDT0R_FMI 0x0000FF00U /*!<Filter Match Index */
+#define CAN_RDT0R_TIME 0xFFFF0000U /*!<Message Time Stamp */
+
+/******************* Bit definition for CAN_RDL0R register ******************/
+#define CAN_RDL0R_DATA0 0x000000FFU /*!<Data byte 0 */
+#define CAN_RDL0R_DATA1 0x0000FF00U /*!<Data byte 1 */
+#define CAN_RDL0R_DATA2 0x00FF0000U /*!<Data byte 2 */
+#define CAN_RDL0R_DATA3 0xFF000000U /*!<Data byte 3 */
+
+/******************* Bit definition for CAN_RDH0R register ******************/
+#define CAN_RDH0R_DATA4 0x000000FFU /*!<Data byte 4 */
+#define CAN_RDH0R_DATA5 0x0000FF00U /*!<Data byte 5 */
+#define CAN_RDH0R_DATA6 0x00FF0000U /*!<Data byte 6 */
+#define CAN_RDH0R_DATA7 0xFF000000U /*!<Data byte 7 */
+
+/******************* Bit definition for CAN_RI1R register *******************/
+#define CAN_RI1R_RTR 0x00000002U /*!<Remote Transmission Request */
+#define CAN_RI1R_IDE 0x00000004U /*!<Identifier Extension */
+#define CAN_RI1R_EXID 0x001FFFF8U /*!<Extended identifier */
+#define CAN_RI1R_STID 0xFFE00000U /*!<Standard Identifier or Extended Identifier */
+
+/******************* Bit definition for CAN_RDT1R register ******************/
+#define CAN_RDT1R_DLC 0x0000000FU /*!<Data Length Code */
+#define CAN_RDT1R_FMI 0x0000FF00U /*!<Filter Match Index */
+#define CAN_RDT1R_TIME 0xFFFF0000U /*!<Message Time Stamp */
+
+/******************* Bit definition for CAN_RDL1R register ******************/
+#define CAN_RDL1R_DATA0 0x000000FFU /*!<Data byte 0 */
+#define CAN_RDL1R_DATA1 0x0000FF00U /*!<Data byte 1 */
+#define CAN_RDL1R_DATA2 0x00FF0000U /*!<Data byte 2 */
+#define CAN_RDL1R_DATA3 0xFF000000U /*!<Data byte 3 */
+
+/******************* Bit definition for CAN_RDH1R register ******************/
+#define CAN_RDH1R_DATA4 0x000000FFU /*!<Data byte 4 */
+#define CAN_RDH1R_DATA5 0x0000FF00U /*!<Data byte 5 */
+#define CAN_RDH1R_DATA6 0x00FF0000U /*!<Data byte 6 */
+#define CAN_RDH1R_DATA7 0xFF000000U /*!<Data byte 7 */
+
+/*!<CAN filter registers */
+/******************* Bit definition for CAN_FMR register ********************/
+#define CAN_FMR_FINIT 0x01U /*!<Filter Init Mode */
+#define CAN_FMR_CAN2SB 0x00003F00U /*!<CAN2 start bank */
+
+/******************* Bit definition for CAN_FM1R register *******************/
+#define CAN_FM1R_FBM 0x0FFFFFFFU /*!<Filter Mode */
+#define CAN_FM1R_FBM0 0x00000001U /*!<Filter Init Mode bit 0 */
+#define CAN_FM1R_FBM1 0x00000002U /*!<Filter Init Mode bit 1 */
+#define CAN_FM1R_FBM2 0x00000004U /*!<Filter Init Mode bit 2 */
+#define CAN_FM1R_FBM3 0x00000008U /*!<Filter Init Mode bit 3 */
+#define CAN_FM1R_FBM4 0x00000010U /*!<Filter Init Mode bit 4 */
+#define CAN_FM1R_FBM5 0x00000020U /*!<Filter Init Mode bit 5 */
+#define CAN_FM1R_FBM6 0x00000040U /*!<Filter Init Mode bit 6 */
+#define CAN_FM1R_FBM7 0x00000080U /*!<Filter Init Mode bit 7 */
+#define CAN_FM1R_FBM8 0x00000100U /*!<Filter Init Mode bit 8 */
+#define CAN_FM1R_FBM9 0x00000200U /*!<Filter Init Mode bit 9 */
+#define CAN_FM1R_FBM10 0x00000400U /*!<Filter Init Mode bit 10 */
+#define CAN_FM1R_FBM11 0x00000800U /*!<Filter Init Mode bit 11 */
+#define CAN_FM1R_FBM12 0x00001000U /*!<Filter Init Mode bit 12 */
+#define CAN_FM1R_FBM13 0x00002000U /*!<Filter Init Mode bit 13 */
+#define CAN_FM1R_FBM14 0x00004000U /*!<Filter Init Mode bit 14 */
+#define CAN_FM1R_FBM15 0x00008000U /*!<Filter Init Mode bit 15 */
+#define CAN_FM1R_FBM16 0x00010000U /*!<Filter Init Mode bit 16 */
+#define CAN_FM1R_FBM17 0x00020000U /*!<Filter Init Mode bit 17 */
+#define CAN_FM1R_FBM18 0x00040000U /*!<Filter Init Mode bit 18 */
+#define CAN_FM1R_FBM19 0x00080000U /*!<Filter Init Mode bit 19 */
+#define CAN_FM1R_FBM20 0x00100000U /*!<Filter Init Mode bit 20 */
+#define CAN_FM1R_FBM21 0x00200000U /*!<Filter Init Mode bit 21 */
+#define CAN_FM1R_FBM22 0x00400000U /*!<Filter Init Mode bit 22 */
+#define CAN_FM1R_FBM23 0x00800000U /*!<Filter Init Mode bit 23 */
+#define CAN_FM1R_FBM24 0x01000000U /*!<Filter Init Mode bit 24 */
+#define CAN_FM1R_FBM25 0x02000000U /*!<Filter Init Mode bit 25 */
+#define CAN_FM1R_FBM26 0x04000000U /*!<Filter Init Mode bit 26 */
+#define CAN_FM1R_FBM27 0x08000000U /*!<Filter Init Mode bit 27 */
+
+/******************* Bit definition for CAN_FS1R register *******************/
+#define CAN_FS1R_FSC 0x0FFFFFFFU /*!<Filter Scale Configuration */
+#define CAN_FS1R_FSC0 0x00000001U /*!<Filter Scale Configuration bit 0 */
+#define CAN_FS1R_FSC1 0x00000002U /*!<Filter Scale Configuration bit 1 */
+#define CAN_FS1R_FSC2 0x00000004U /*!<Filter Scale Configuration bit 2 */
+#define CAN_FS1R_FSC3 0x00000008U /*!<Filter Scale Configuration bit 3 */
+#define CAN_FS1R_FSC4 0x00000010U /*!<Filter Scale Configuration bit 4 */
+#define CAN_FS1R_FSC5 0x00000020U /*!<Filter Scale Configuration bit 5 */
+#define CAN_FS1R_FSC6 0x00000040U /*!<Filter Scale Configuration bit 6 */
+#define CAN_FS1R_FSC7 0x00000080U /*!<Filter Scale Configuration bit 7 */
+#define CAN_FS1R_FSC8 0x00000100U /*!<Filter Scale Configuration bit 8 */
+#define CAN_FS1R_FSC9 0x00000200U /*!<Filter Scale Configuration bit 9 */
+#define CAN_FS1R_FSC10 0x00000400U /*!<Filter Scale Configuration bit 10 */
+#define CAN_FS1R_FSC11 0x00000800U /*!<Filter Scale Configuration bit 11 */
+#define CAN_FS1R_FSC12 0x00001000U /*!<Filter Scale Configuration bit 12 */
+#define CAN_FS1R_FSC13 0x00002000U /*!<Filter Scale Configuration bit 13 */
+#define CAN_FS1R_FSC14 0x00004000U /*!<Filter Scale Configuration bit 14 */
+#define CAN_FS1R_FSC15 0x00008000U /*!<Filter Scale Configuration bit 15 */
+#define CAN_FS1R_FSC16 0x00010000U /*!<Filter Scale Configuration bit 16 */
+#define CAN_FS1R_FSC17 0x00020000U /*!<Filter Scale Configuration bit 17 */
+#define CAN_FS1R_FSC18 0x00040000U /*!<Filter Scale Configuration bit 18 */
+#define CAN_FS1R_FSC19 0x00080000U /*!<Filter Scale Configuration bit 19 */
+#define CAN_FS1R_FSC20 0x00100000U /*!<Filter Scale Configuration bit 20 */
+#define CAN_FS1R_FSC21 0x00200000U /*!<Filter Scale Configuration bit 21 */
+#define CAN_FS1R_FSC22 0x00400000U /*!<Filter Scale Configuration bit 22 */
+#define CAN_FS1R_FSC23 0x00800000U /*!<Filter Scale Configuration bit 23 */
+#define CAN_FS1R_FSC24 0x01000000U /*!<Filter Scale Configuration bit 24 */
+#define CAN_FS1R_FSC25 0x02000000U /*!<Filter Scale Configuration bit 25 */
+#define CAN_FS1R_FSC26 0x04000000U /*!<Filter Scale Configuration bit 26 */
+#define CAN_FS1R_FSC27 0x08000000U /*!<Filter Scale Configuration bit 27 */
+
+/****************** Bit definition for CAN_FFA1R register *******************/
+#define CAN_FFA1R_FFA 0x0FFFFFFFU /*!<Filter FIFO Assignment */
+#define CAN_FFA1R_FFA0 0x00000001U /*!<Filter FIFO Assignment bit 0 */
+#define CAN_FFA1R_FFA1 0x00000002U /*!<Filter FIFO Assignment bit 1 */
+#define CAN_FFA1R_FFA2 0x00000004U /*!<Filter FIFO Assignment bit 2 */
+#define CAN_FFA1R_FFA3 0x00000008U /*!<Filter FIFO Assignment bit 3 */
+#define CAN_FFA1R_FFA4 0x00000010U /*!<Filter FIFO Assignment bit 4 */
+#define CAN_FFA1R_FFA5 0x00000020U /*!<Filter FIFO Assignment bit 5 */
+#define CAN_FFA1R_FFA6 0x00000040U /*!<Filter FIFO Assignment bit 6 */
+#define CAN_FFA1R_FFA7 0x00000080U /*!<Filter FIFO Assignment bit 7 */
+#define CAN_FFA1R_FFA8 0x00000100U /*!<Filter FIFO Assignment bit 8 */
+#define CAN_FFA1R_FFA9 0x00000200U /*!<Filter FIFO Assignment bit 9 */
+#define CAN_FFA1R_FFA10 0x00000400U /*!<Filter FIFO Assignment bit 10 */
+#define CAN_FFA1R_FFA11 0x00000800U /*!<Filter FIFO Assignment bit 11 */
+#define CAN_FFA1R_FFA12 0x00001000U /*!<Filter FIFO Assignment bit 12 */
+#define CAN_FFA1R_FFA13 0x00002000U /*!<Filter FIFO Assignment bit 13 */
+#define CAN_FFA1R_FFA14 0x00004000U /*!<Filter FIFO Assignment bit 14 */
+#define CAN_FFA1R_FFA15 0x00008000U /*!<Filter FIFO Assignment bit 15 */
+#define CAN_FFA1R_FFA16 0x00010000U /*!<Filter FIFO Assignment bit 16 */
+#define CAN_FFA1R_FFA17 0x00020000U /*!<Filter FIFO Assignment bit 17 */
+#define CAN_FFA1R_FFA18 0x00040000U /*!<Filter FIFO Assignment bit 18 */
+#define CAN_FFA1R_FFA19 0x00080000U /*!<Filter FIFO Assignment bit 19 */
+#define CAN_FFA1R_FFA20 0x00100000U /*!<Filter FIFO Assignment bit 20 */
+#define CAN_FFA1R_FFA21 0x00200000U /*!<Filter FIFO Assignment bit 21 */
+#define CAN_FFA1R_FFA22 0x00400000U /*!<Filter FIFO Assignment bit 22 */
+#define CAN_FFA1R_FFA23 0x00800000U /*!<Filter FIFO Assignment bit 23 */
+#define CAN_FFA1R_FFA24 0x01000000U /*!<Filter FIFO Assignment bit 24 */
+#define CAN_FFA1R_FFA25 0x02000000U /*!<Filter FIFO Assignment bit 25 */
+#define CAN_FFA1R_FFA26 0x04000000U /*!<Filter FIFO Assignment bit 26 */
+#define CAN_FFA1R_FFA27 0x08000000U /*!<Filter FIFO Assignment bit 27 */
+
+/******************* Bit definition for CAN_FA1R register *******************/
+#define CAN_FA1R_FACT 0x0FFFFFFFU /*!<Filter Active */
+#define CAN_FA1R_FACT0 0x00000001U /*!<Filter Active bit 0 */
+#define CAN_FA1R_FACT1 0x00000002U /*!<Filter Active bit 1 */
+#define CAN_FA1R_FACT2 0x00000004U /*!<Filter Active bit 2 */
+#define CAN_FA1R_FACT3 0x00000008U /*!<Filter Active bit 3 */
+#define CAN_FA1R_FACT4 0x00000010U /*!<Filter Active bit 4 */
+#define CAN_FA1R_FACT5 0x00000020U /*!<Filter Active bit 5 */
+#define CAN_FA1R_FACT6 0x00000040U /*!<Filter Active bit 6 */
+#define CAN_FA1R_FACT7 0x00000080U /*!<Filter Active bit 7 */
+#define CAN_FA1R_FACT8 0x00000100U /*!<Filter Active bit 8 */
+#define CAN_FA1R_FACT9 0x00000200U /*!<Filter Active bit 9 */
+#define CAN_FA1R_FACT10 0x00000400U /*!<Filter Active bit 10 */
+#define CAN_FA1R_FACT11 0x00000800U /*!<Filter Active bit 11 */
+#define CAN_FA1R_FACT12 0x00001000U /*!<Filter Active bit 12 */
+#define CAN_FA1R_FACT13 0x00002000U /*!<Filter Active bit 13 */
+#define CAN_FA1R_FACT14 0x00004000U /*!<Filter Active bit 14 */
+#define CAN_FA1R_FACT15 0x00008000U /*!<Filter Active bit 15 */
+#define CAN_FA1R_FACT16 0x00010000U /*!<Filter Active bit 16 */
+#define CAN_FA1R_FACT17 0x00020000U /*!<Filter Active bit 17 */
+#define CAN_FA1R_FACT18 0x00040000U /*!<Filter Active bit 18 */
+#define CAN_FA1R_FACT19 0x00080000U /*!<Filter Active bit 19 */
+#define CAN_FA1R_FACT20 0x00100000U /*!<Filter Active bit 20 */
+#define CAN_FA1R_FACT21 0x00200000U /*!<Filter Active bit 21 */
+#define CAN_FA1R_FACT22 0x00400000U /*!<Filter Active bit 22 */
+#define CAN_FA1R_FACT23 0x00800000U /*!<Filter Active bit 23 */
+#define CAN_FA1R_FACT24 0x01000000U /*!<Filter Active bit 24 */
+#define CAN_FA1R_FACT25 0x02000000U /*!<Filter Active bit 25 */
+#define CAN_FA1R_FACT26 0x04000000U /*!<Filter Active bit 26 */
+#define CAN_FA1R_FACT27 0x08000000U /*!<Filter Active bit 27 */
+
+
+/******************* Bit definition for CAN_F0R1 register *******************/
+#define CAN_F0R1_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F0R1_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F0R1_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F0R1_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F0R1_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F0R1_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F0R1_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F0R1_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F0R1_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F0R1_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F0R1_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F0R1_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F0R1_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F0R1_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F0R1_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F0R1_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F0R1_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F0R1_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F0R1_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F0R1_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F0R1_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F0R1_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F0R1_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F0R1_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F0R1_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F0R1_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F0R1_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F0R1_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F0R1_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F0R1_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F0R1_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F0R1_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F1R1 register *******************/
+#define CAN_F1R1_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F1R1_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F1R1_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F1R1_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F1R1_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F1R1_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F1R1_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F1R1_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F1R1_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F1R1_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F1R1_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F1R1_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F1R1_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F1R1_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F1R1_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F1R1_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F1R1_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F1R1_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F1R1_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F1R1_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F1R1_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F1R1_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F1R1_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F1R1_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F1R1_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F1R1_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F1R1_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F1R1_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F1R1_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F1R1_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F1R1_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F1R1_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F2R1 register *******************/
+#define CAN_F2R1_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F2R1_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F2R1_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F2R1_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F2R1_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F2R1_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F2R1_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F2R1_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F2R1_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F2R1_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F2R1_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F2R1_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F2R1_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F2R1_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F2R1_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F2R1_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F2R1_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F2R1_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F2R1_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F2R1_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F2R1_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F2R1_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F2R1_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F2R1_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F2R1_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F2R1_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F2R1_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F2R1_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F2R1_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F2R1_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F2R1_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F2R1_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F3R1 register *******************/
+#define CAN_F3R1_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F3R1_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F3R1_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F3R1_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F3R1_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F3R1_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F3R1_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F3R1_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F3R1_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F3R1_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F3R1_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F3R1_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F3R1_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F3R1_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F3R1_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F3R1_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F3R1_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F3R1_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F3R1_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F3R1_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F3R1_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F3R1_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F3R1_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F3R1_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F3R1_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F3R1_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F3R1_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F3R1_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F3R1_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F3R1_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F3R1_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F3R1_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F4R1 register *******************/
+#define CAN_F4R1_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F4R1_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F4R1_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F4R1_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F4R1_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F4R1_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F4R1_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F4R1_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F4R1_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F4R1_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F4R1_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F4R1_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F4R1_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F4R1_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F4R1_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F4R1_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F4R1_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F4R1_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F4R1_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F4R1_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F4R1_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F4R1_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F4R1_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F4R1_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F4R1_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F4R1_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F4R1_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F4R1_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F4R1_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F4R1_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F4R1_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F4R1_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F5R1 register *******************/
+#define CAN_F5R1_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F5R1_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F5R1_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F5R1_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F5R1_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F5R1_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F5R1_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F5R1_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F5R1_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F5R1_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F5R1_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F5R1_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F5R1_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F5R1_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F5R1_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F5R1_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F5R1_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F5R1_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F5R1_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F5R1_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F5R1_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F5R1_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F5R1_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F5R1_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F5R1_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F5R1_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F5R1_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F5R1_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F5R1_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F5R1_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F5R1_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F5R1_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F6R1 register *******************/
+#define CAN_F6R1_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F6R1_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F6R1_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F6R1_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F6R1_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F6R1_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F6R1_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F6R1_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F6R1_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F6R1_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F6R1_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F6R1_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F6R1_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F6R1_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F6R1_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F6R1_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F6R1_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F6R1_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F6R1_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F6R1_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F6R1_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F6R1_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F6R1_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F6R1_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F6R1_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F6R1_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F6R1_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F6R1_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F6R1_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F6R1_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F6R1_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F6R1_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F7R1 register *******************/
+#define CAN_F7R1_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F7R1_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F7R1_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F7R1_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F7R1_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F7R1_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F7R1_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F7R1_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F7R1_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F7R1_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F7R1_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F7R1_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F7R1_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F7R1_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F7R1_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F7R1_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F7R1_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F7R1_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F7R1_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F7R1_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F7R1_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F7R1_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F7R1_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F7R1_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F7R1_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F7R1_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F7R1_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F7R1_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F7R1_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F7R1_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F7R1_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F7R1_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F8R1 register *******************/
+#define CAN_F8R1_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F8R1_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F8R1_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F8R1_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F8R1_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F8R1_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F8R1_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F8R1_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F8R1_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F8R1_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F8R1_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F8R1_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F8R1_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F8R1_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F8R1_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F8R1_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F8R1_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F8R1_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F8R1_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F8R1_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F8R1_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F8R1_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F8R1_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F8R1_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F8R1_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F8R1_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F8R1_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F8R1_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F8R1_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F8R1_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F8R1_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F8R1_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F9R1 register *******************/
+#define CAN_F9R1_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F9R1_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F9R1_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F9R1_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F9R1_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F9R1_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F9R1_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F9R1_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F9R1_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F9R1_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F9R1_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F9R1_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F9R1_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F9R1_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F9R1_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F9R1_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F9R1_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F9R1_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F9R1_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F9R1_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F9R1_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F9R1_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F9R1_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F9R1_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F9R1_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F9R1_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F9R1_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F9R1_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F9R1_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F9R1_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F9R1_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F9R1_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F10R1 register ******************/
+#define CAN_F10R1_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F10R1_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F10R1_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F10R1_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F10R1_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F10R1_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F10R1_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F10R1_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F10R1_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F10R1_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F10R1_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F10R1_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F10R1_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F10R1_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F10R1_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F10R1_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F10R1_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F10R1_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F10R1_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F10R1_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F10R1_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F10R1_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F10R1_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F10R1_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F10R1_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F10R1_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F10R1_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F10R1_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F10R1_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F10R1_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F10R1_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F10R1_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F11R1 register ******************/
+#define CAN_F11R1_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F11R1_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F11R1_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F11R1_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F11R1_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F11R1_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F11R1_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F11R1_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F11R1_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F11R1_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F11R1_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F11R1_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F11R1_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F11R1_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F11R1_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F11R1_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F11R1_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F11R1_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F11R1_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F11R1_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F11R1_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F11R1_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F11R1_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F11R1_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F11R1_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F11R1_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F11R1_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F11R1_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F11R1_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F11R1_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F11R1_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F11R1_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F12R1 register ******************/
+#define CAN_F12R1_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F12R1_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F12R1_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F12R1_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F12R1_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F12R1_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F12R1_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F12R1_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F12R1_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F12R1_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F12R1_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F12R1_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F12R1_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F12R1_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F12R1_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F12R1_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F12R1_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F12R1_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F12R1_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F12R1_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F12R1_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F12R1_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F12R1_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F12R1_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F12R1_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F12R1_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F12R1_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F12R1_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F12R1_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F12R1_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F12R1_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F12R1_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F13R1 register ******************/
+#define CAN_F13R1_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F13R1_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F13R1_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F13R1_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F13R1_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F13R1_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F13R1_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F13R1_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F13R1_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F13R1_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F13R1_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F13R1_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F13R1_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F13R1_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F13R1_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F13R1_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F13R1_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F13R1_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F13R1_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F13R1_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F13R1_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F13R1_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F13R1_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F13R1_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F13R1_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F13R1_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F13R1_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F13R1_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F13R1_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F13R1_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F13R1_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F13R1_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F0R2 register *******************/
+#define CAN_F0R2_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F0R2_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F0R2_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F0R2_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F0R2_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F0R2_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F0R2_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F0R2_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F0R2_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F0R2_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F0R2_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F0R2_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F0R2_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F0R2_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F0R2_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F0R2_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F0R2_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F0R2_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F0R2_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F0R2_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F0R2_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F0R2_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F0R2_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F0R2_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F0R2_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F0R2_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F0R2_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F0R2_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F0R2_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F0R2_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F0R2_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F0R2_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F1R2 register *******************/
+#define CAN_F1R2_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F1R2_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F1R2_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F1R2_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F1R2_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F1R2_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F1R2_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F1R2_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F1R2_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F1R2_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F1R2_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F1R2_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F1R2_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F1R2_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F1R2_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F1R2_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F1R2_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F1R2_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F1R2_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F1R2_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F1R2_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F1R2_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F1R2_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F1R2_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F1R2_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F1R2_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F1R2_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F1R2_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F1R2_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F1R2_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F1R2_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F1R2_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F2R2 register *******************/
+#define CAN_F2R2_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F2R2_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F2R2_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F2R2_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F2R2_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F2R2_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F2R2_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F2R2_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F2R2_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F2R2_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F2R2_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F2R2_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F2R2_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F2R2_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F2R2_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F2R2_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F2R2_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F2R2_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F2R2_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F2R2_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F2R2_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F2R2_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F2R2_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F2R2_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F2R2_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F2R2_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F2R2_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F2R2_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F2R2_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F2R2_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F2R2_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F2R2_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F3R2 register *******************/
+#define CAN_F3R2_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F3R2_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F3R2_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F3R2_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F3R2_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F3R2_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F3R2_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F3R2_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F3R2_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F3R2_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F3R2_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F3R2_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F3R2_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F3R2_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F3R2_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F3R2_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F3R2_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F3R2_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F3R2_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F3R2_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F3R2_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F3R2_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F3R2_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F3R2_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F3R2_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F3R2_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F3R2_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F3R2_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F3R2_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F3R2_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F3R2_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F3R2_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F4R2 register *******************/
+#define CAN_F4R2_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F4R2_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F4R2_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F4R2_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F4R2_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F4R2_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F4R2_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F4R2_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F4R2_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F4R2_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F4R2_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F4R2_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F4R2_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F4R2_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F4R2_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F4R2_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F4R2_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F4R2_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F4R2_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F4R2_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F4R2_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F4R2_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F4R2_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F4R2_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F4R2_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F4R2_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F4R2_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F4R2_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F4R2_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F4R2_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F4R2_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F4R2_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F5R2 register *******************/
+#define CAN_F5R2_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F5R2_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F5R2_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F5R2_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F5R2_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F5R2_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F5R2_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F5R2_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F5R2_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F5R2_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F5R2_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F5R2_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F5R2_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F5R2_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F5R2_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F5R2_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F5R2_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F5R2_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F5R2_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F5R2_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F5R2_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F5R2_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F5R2_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F5R2_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F5R2_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F5R2_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F5R2_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F5R2_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F5R2_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F5R2_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F5R2_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F5R2_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F6R2 register *******************/
+#define CAN_F6R2_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F6R2_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F6R2_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F6R2_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F6R2_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F6R2_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F6R2_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F6R2_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F6R2_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F6R2_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F6R2_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F6R2_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F6R2_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F6R2_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F6R2_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F6R2_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F6R2_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F6R2_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F6R2_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F6R2_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F6R2_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F6R2_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F6R2_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F6R2_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F6R2_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F6R2_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F6R2_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F6R2_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F6R2_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F6R2_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F6R2_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F6R2_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F7R2 register *******************/
+#define CAN_F7R2_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F7R2_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F7R2_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F7R2_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F7R2_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F7R2_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F7R2_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F7R2_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F7R2_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F7R2_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F7R2_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F7R2_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F7R2_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F7R2_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F7R2_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F7R2_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F7R2_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F7R2_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F7R2_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F7R2_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F7R2_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F7R2_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F7R2_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F7R2_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F7R2_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F7R2_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F7R2_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F7R2_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F7R2_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F7R2_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F7R2_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F7R2_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F8R2 register *******************/
+#define CAN_F8R2_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F8R2_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F8R2_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F8R2_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F8R2_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F8R2_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F8R2_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F8R2_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F8R2_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F8R2_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F8R2_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F8R2_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F8R2_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F8R2_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F8R2_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F8R2_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F8R2_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F8R2_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F8R2_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F8R2_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F8R2_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F8R2_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F8R2_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F8R2_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F8R2_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F8R2_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F8R2_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F8R2_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F8R2_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F8R2_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F8R2_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F8R2_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F9R2 register *******************/
+#define CAN_F9R2_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F9R2_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F9R2_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F9R2_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F9R2_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F9R2_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F9R2_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F9R2_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F9R2_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F9R2_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F9R2_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F9R2_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F9R2_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F9R2_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F9R2_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F9R2_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F9R2_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F9R2_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F9R2_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F9R2_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F9R2_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F9R2_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F9R2_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F9R2_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F9R2_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F9R2_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F9R2_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F9R2_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F9R2_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F9R2_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F9R2_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F9R2_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F10R2 register ******************/
+#define CAN_F10R2_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F10R2_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F10R2_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F10R2_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F10R2_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F10R2_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F10R2_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F10R2_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F10R2_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F10R2_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F10R2_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F10R2_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F10R2_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F10R2_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F10R2_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F10R2_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F10R2_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F10R2_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F10R2_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F10R2_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F10R2_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F10R2_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F10R2_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F10R2_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F10R2_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F10R2_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F10R2_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F10R2_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F10R2_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F10R2_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F10R2_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F10R2_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F11R2 register ******************/
+#define CAN_F11R2_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F11R2_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F11R2_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F11R2_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F11R2_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F11R2_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F11R2_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F11R2_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F11R2_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F11R2_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F11R2_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F11R2_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F11R2_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F11R2_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F11R2_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F11R2_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F11R2_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F11R2_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F11R2_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F11R2_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F11R2_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F11R2_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F11R2_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F11R2_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F11R2_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F11R2_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F11R2_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F11R2_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F11R2_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F11R2_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F11R2_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F11R2_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F12R2 register ******************/
+#define CAN_F12R2_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F12R2_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F12R2_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F12R2_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F12R2_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F12R2_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F12R2_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F12R2_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F12R2_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F12R2_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F12R2_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F12R2_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F12R2_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F12R2_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F12R2_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F12R2_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F12R2_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F12R2_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F12R2_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F12R2_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F12R2_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F12R2_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F12R2_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F12R2_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F12R2_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F12R2_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F12R2_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F12R2_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F12R2_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F12R2_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F12R2_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F12R2_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F13R2 register ******************/
+#define CAN_F13R2_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F13R2_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F13R2_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F13R2_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F13R2_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F13R2_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F13R2_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F13R2_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F13R2_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F13R2_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F13R2_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F13R2_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F13R2_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F13R2_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F13R2_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F13R2_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F13R2_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F13R2_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F13R2_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F13R2_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F13R2_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F13R2_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F13R2_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F13R2_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F13R2_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F13R2_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F13R2_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F13R2_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F13R2_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F13R2_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F13R2_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F13R2_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************************************************************************/
+/* */
+/* CRC calculation unit */
+/* */
+/******************************************************************************/
+/******************* Bit definition for CRC_DR register *********************/
+#define CRC_DR_DR 0xFFFFFFFFU /*!< Data register bits */
+
+
+/******************* Bit definition for CRC_IDR register ********************/
+#define CRC_IDR_IDR 0xFFU /*!< General-purpose 8-bit data register bits */
+
+
+/******************** Bit definition for CRC_CR register ********************/
+#define CRC_CR_RESET 0x01U /*!< RESET bit */
+
+
+/******************************************************************************/
+/* */
+/* Digital to Analog Converter */
+/* */
+/******************************************************************************/
+/******************** Bit definition for DAC_CR register ********************/
+#define DAC_CR_EN1 0x00000001U /*!<DAC channel1 enable */
+#define DAC_CR_BOFF1 0x00000002U /*!<DAC channel1 output buffer disable */
+#define DAC_CR_TEN1 0x00000004U /*!<DAC channel1 Trigger enable */
+
+#define DAC_CR_TSEL1 0x00000038U /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */
+#define DAC_CR_TSEL1_0 0x00000008U /*!<Bit 0 */
+#define DAC_CR_TSEL1_1 0x00000010U /*!<Bit 1 */
+#define DAC_CR_TSEL1_2 0x00000020U /*!<Bit 2 */
+
+#define DAC_CR_WAVE1 0x000000C0U /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
+#define DAC_CR_WAVE1_0 0x00000040U /*!<Bit 0 */
+#define DAC_CR_WAVE1_1 0x00000080U /*!<Bit 1 */
+
+#define DAC_CR_MAMP1 0x00000F00U /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
+#define DAC_CR_MAMP1_0 0x00000100U /*!<Bit 0 */
+#define DAC_CR_MAMP1_1 0x00000200U /*!<Bit 1 */
+#define DAC_CR_MAMP1_2 0x00000400U /*!<Bit 2 */
+#define DAC_CR_MAMP1_3 0x00000800U /*!<Bit 3 */
+
+#define DAC_CR_DMAEN1 0x00001000U /*!<DAC channel1 DMA enable */
+#define DAC_CR_DMAUDRIE1 0x00002000U /*!<DAC channel1 DMA underrun interrupt enable*/
+#define DAC_CR_EN2 0x00010000U /*!<DAC channel2 enable */
+#define DAC_CR_BOFF2 0x00020000U /*!<DAC channel2 output buffer disable */
+#define DAC_CR_TEN2 0x00040000U /*!<DAC channel2 Trigger enable */
+
+#define DAC_CR_TSEL2 0x00380000U /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */
+#define DAC_CR_TSEL2_0 0x00080000U /*!<Bit 0 */
+#define DAC_CR_TSEL2_1 0x00100000U /*!<Bit 1 */
+#define DAC_CR_TSEL2_2 0x00200000U /*!<Bit 2 */
+
+#define DAC_CR_WAVE2 0x00C00000U /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
+#define DAC_CR_WAVE2_0 0x00400000U /*!<Bit 0 */
+#define DAC_CR_WAVE2_1 0x00800000U /*!<Bit 1 */
+
+#define DAC_CR_MAMP2 0x0F000000U /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
+#define DAC_CR_MAMP2_0 0x01000000U /*!<Bit 0 */
+#define DAC_CR_MAMP2_1 0x02000000U /*!<Bit 1 */
+#define DAC_CR_MAMP2_2 0x04000000U /*!<Bit 2 */
+#define DAC_CR_MAMP2_3 0x08000000U /*!<Bit 3 */
+
+#define DAC_CR_DMAEN2 0x10000000U /*!<DAC channel2 DMA enabled */
+#define DAC_CR_DMAUDRIE2 0x20000000U /*!<DAC channel2 DMA underrun interrupt enable*/
+
+/***************** Bit definition for DAC_SWTRIGR register ******************/
+#define DAC_SWTRIGR_SWTRIG1 0x01U /*!<DAC channel1 software trigger */
+#define DAC_SWTRIGR_SWTRIG2 0x02U /*!<DAC channel2 software trigger */
+
+/***************** Bit definition for DAC_DHR12R1 register ******************/
+#define DAC_DHR12R1_DACC1DHR 0x0FFFU /*!<DAC channel1 12-bit Right aligned data */
+
+/***************** Bit definition for DAC_DHR12L1 register ******************/
+#define DAC_DHR12L1_DACC1DHR 0xFFF0U /*!<DAC channel1 12-bit Left aligned data */
+
+/****************** Bit definition for DAC_DHR8R1 register ******************/
+#define DAC_DHR8R1_DACC1DHR 0xFFU /*!<DAC channel1 8-bit Right aligned data */
+
+/***************** Bit definition for DAC_DHR12R2 register ******************/
+#define DAC_DHR12R2_DACC2DHR 0x0FFFU /*!<DAC channel2 12-bit Right aligned data */
+
+/***************** Bit definition for DAC_DHR12L2 register ******************/
+#define DAC_DHR12L2_DACC2DHR 0xFFF0U /*!<DAC channel2 12-bit Left aligned data */
+
+/****************** Bit definition for DAC_DHR8R2 register ******************/
+#define DAC_DHR8R2_DACC2DHR 0xFFU /*!<DAC channel2 8-bit Right aligned data */
+
+/***************** Bit definition for DAC_DHR12RD register ******************/
+#define DAC_DHR12RD_DACC1DHR 0x00000FFFU /*!<DAC channel1 12-bit Right aligned data */
+#define DAC_DHR12RD_DACC2DHR 0x0FFF0000U /*!<DAC channel2 12-bit Right aligned data */
+
+/***************** Bit definition for DAC_DHR12LD register ******************/
+#define DAC_DHR12LD_DACC1DHR 0x0000FFF0U /*!<DAC channel1 12-bit Left aligned data */
+#define DAC_DHR12LD_DACC2DHR 0xFFF00000U /*!<DAC channel2 12-bit Left aligned data */
+
+/****************** Bit definition for DAC_DHR8RD register ******************/
+#define DAC_DHR8RD_DACC1DHR 0x00FFU /*!<DAC channel1 8-bit Right aligned data */
+#define DAC_DHR8RD_DACC2DHR 0xFF00U /*!<DAC channel2 8-bit Right aligned data */
+
+/******************* Bit definition for DAC_DOR1 register *******************/
+#define DAC_DOR1_DACC1DOR 0x0FFFU /*!<DAC channel1 data output */
+
+/******************* Bit definition for DAC_DOR2 register *******************/
+#define DAC_DOR2_DACC2DOR 0x0FFFU /*!<DAC channel2 data output */
+
+/******************** Bit definition for DAC_SR register ********************/
+#define DAC_SR_DMAUDR1 0x00002000U /*!<DAC channel1 DMA underrun flag */
+#define DAC_SR_DMAUDR2 0x20000000U /*!<DAC channel2 DMA underrun flag */
+
+/******************************************************************************/
+/* */
+/* Debug MCU */
+/* */
+/******************************************************************************/
+
+/******************************************************************************/
+/* */
+/* DCMI */
+/* */
+/******************************************************************************/
+/******************** Bits definition for DCMI_CR register ******************/
+#define DCMI_CR_CAPTURE 0x00000001U
+#define DCMI_CR_CM 0x00000002U
+#define DCMI_CR_CROP 0x00000004U
+#define DCMI_CR_JPEG 0x00000008U
+#define DCMI_CR_ESS 0x00000010U
+#define DCMI_CR_PCKPOL 0x00000020U
+#define DCMI_CR_HSPOL 0x00000040U
+#define DCMI_CR_VSPOL 0x00000080U
+#define DCMI_CR_FCRC_0 0x00000100U
+#define DCMI_CR_FCRC_1 0x00000200U
+#define DCMI_CR_EDM_0 0x00000400U
+#define DCMI_CR_EDM_1 0x00000800U
+#define DCMI_CR_OUTEN 0x00002000U
+#define DCMI_CR_ENABLE 0x00004000U
+#define DCMI_CR_BSM_0 0x00010000U
+#define DCMI_CR_BSM_1 0x00020000U
+#define DCMI_CR_OEBS 0x00040000U
+#define DCMI_CR_LSM 0x00080000U
+#define DCMI_CR_OELS 0x00100000U
+
+/******************** Bits definition for DCMI_SR register ******************/
+#define DCMI_SR_HSYNC 0x00000001U
+#define DCMI_SR_VSYNC 0x00000002U
+#define DCMI_SR_FNE 0x00000004U
+
+/******************** Bits definition for DCMI_RIS register *****************/
+#define DCMI_RIS_FRAME_RIS 0x00000001U
+#define DCMI_RIS_OVR_RIS 0x00000002U
+#define DCMI_RIS_ERR_RIS 0x00000004U
+#define DCMI_RIS_VSYNC_RIS 0x00000008U
+#define DCMI_RIS_LINE_RIS 0x00000010U
+/* Legacy defines */
+#define DCMI_RISR_FRAME_RIS DCMI_RIS_FRAME_RIS
+#define DCMI_RISR_OVR_RIS DCMI_RIS_OVR_RIS
+#define DCMI_RISR_ERR_RIS DCMI_RIS_ERR_RIS
+#define DCMI_RISR_VSYNC_RIS DCMI_RIS_VSYNC_RIS
+#define DCMI_RISR_LINE_RIS DCMI_RIS_LINE_RIS
+#define DCMI_RISR_OVF_RIS DCMI_RIS_OVR_RIS
+
+/******************** Bits definition for DCMI_IER register *****************/
+#define DCMI_IER_FRAME_IE 0x00000001U
+#define DCMI_IER_OVR_IE 0x00000002U
+#define DCMI_IER_ERR_IE 0x00000004U
+#define DCMI_IER_VSYNC_IE 0x00000008U
+#define DCMI_IER_LINE_IE 0x00000010U
+/* Legacy defines */
+#define DCMI_IER_OVF_IE DCMI_IER_OVR_IE
+/******************** Bits definition for DCMI_MIS register *****************/
+#define DCMI_MIS_FRAME_MIS 0x00000001U
+#define DCMI_MIS_OVR_MIS 0x00000002U
+#define DCMI_MIS_ERR_MIS 0x00000004U
+#define DCMI_MIS_VSYNC_MIS 0x00000008U
+#define DCMI_MIS_LINE_MIS 0x00000010U
+
+/* Legacy defines */
+#define DCMI_MISR_FRAME_MIS DCMI_MIS_FRAME_MIS
+#define DCMI_MISR_OVF_MIS DCMI_MIS_OVR_MIS
+#define DCMI_MISR_ERR_MIS DCMI_MIS_ERR_MIS
+#define DCMI_MISR_VSYNC_MIS DCMI_MIS_VSYNC_MIS
+#define DCMI_MISR_LINE_MIS DCMI_MIS_LINE_MIS
+
+/******************** Bits definition for DCMI_ICR register *****************/
+#define DCMI_ICR_FRAME_ISC 0x00000001U
+#define DCMI_ICR_OVR_ISC 0x00000002U
+#define DCMI_ICR_ERR_ISC 0x00000004U
+#define DCMI_ICR_VSYNC_ISC 0x00000008U
+#define DCMI_ICR_LINE_ISC 0x00000010U
+
+/* Legacy defines */
+#define DCMI_ICR_OVF_ISC DCMI_ICR_OVR_ISC
+
+/******************** Bits definition for DCMI_ESCR register ******************/
+#define DCMI_ESCR_FSC 0x000000FFU
+#define DCMI_ESCR_LSC 0x0000FF00U
+#define DCMI_ESCR_LEC 0x00FF0000U
+#define DCMI_ESCR_FEC 0xFF000000U
+
+/******************** Bits definition for DCMI_ESUR register ******************/
+#define DCMI_ESUR_FSU 0x000000FFU
+#define DCMI_ESUR_LSU 0x0000FF00U
+#define DCMI_ESUR_LEU 0x00FF0000U
+#define DCMI_ESUR_FEU 0xFF000000U
+
+/******************** Bits definition for DCMI_CWSTRT register ******************/
+#define DCMI_CWSTRT_HOFFCNT 0x00003FFFU
+#define DCMI_CWSTRT_VST 0x1FFF0000U
+
+/******************** Bits definition for DCMI_CWSIZE register ******************/
+#define DCMI_CWSIZE_CAPCNT 0x00003FFFU
+#define DCMI_CWSIZE_VLINE 0x3FFF0000U
+
+/******************** Bits definition for DCMI_DR register ******************/
+#define DCMI_DR_BYTE0 0x000000FFU
+#define DCMI_DR_BYTE1 0x0000FF00U
+#define DCMI_DR_BYTE2 0x00FF0000U
+#define DCMI_DR_BYTE3 0xFF000000U
+
+/******************************************************************************/
+/* */
+/* DMA Controller */
+/* */
+/******************************************************************************/
+/******************** Bits definition for DMA_SxCR register *****************/
+#define DMA_SxCR_CHSEL 0x0E000000U
+#define DMA_SxCR_CHSEL_0 0x02000000U
+#define DMA_SxCR_CHSEL_1 0x04000000U
+#define DMA_SxCR_CHSEL_2 0x08000000U
+#define DMA_SxCR_MBURST 0x01800000U
+#define DMA_SxCR_MBURST_0 0x00800000U
+#define DMA_SxCR_MBURST_1 0x01000000U
+#define DMA_SxCR_PBURST 0x00600000U
+#define DMA_SxCR_PBURST_0 0x00200000U
+#define DMA_SxCR_PBURST_1 0x00400000U
+#define DMA_SxCR_CT 0x00080000U
+#define DMA_SxCR_DBM 0x00040000U
+#define DMA_SxCR_PL 0x00030000U
+#define DMA_SxCR_PL_0 0x00010000U
+#define DMA_SxCR_PL_1 0x00020000U
+#define DMA_SxCR_PINCOS 0x00008000U
+#define DMA_SxCR_MSIZE 0x00006000U
+#define DMA_SxCR_MSIZE_0 0x00002000U
+#define DMA_SxCR_MSIZE_1 0x00004000U
+#define DMA_SxCR_PSIZE 0x00001800U
+#define DMA_SxCR_PSIZE_0 0x00000800U
+#define DMA_SxCR_PSIZE_1 0x00001000U
+#define DMA_SxCR_MINC 0x00000400U
+#define DMA_SxCR_PINC 0x00000200U
+#define DMA_SxCR_CIRC 0x00000100U
+#define DMA_SxCR_DIR 0x000000C0U
+#define DMA_SxCR_DIR_0 0x00000040U
+#define DMA_SxCR_DIR_1 0x00000080U
+#define DMA_SxCR_PFCTRL 0x00000020U
+#define DMA_SxCR_TCIE 0x00000010U
+#define DMA_SxCR_HTIE 0x00000008U
+#define DMA_SxCR_TEIE 0x00000004U
+#define DMA_SxCR_DMEIE 0x00000002U
+#define DMA_SxCR_EN 0x00000001U
+
+/* Legacy defines */
+#define DMA_SxCR_ACK 0x00100000U
+
+/******************** Bits definition for DMA_SxCNDTR register **************/
+#define DMA_SxNDT 0x0000FFFFU
+#define DMA_SxNDT_0 0x00000001U
+#define DMA_SxNDT_1 0x00000002U
+#define DMA_SxNDT_2 0x00000004U
+#define DMA_SxNDT_3 0x00000008U
+#define DMA_SxNDT_4 0x00000010U
+#define DMA_SxNDT_5 0x00000020U
+#define DMA_SxNDT_6 0x00000040U
+#define DMA_SxNDT_7 0x00000080U
+#define DMA_SxNDT_8 0x00000100U
+#define DMA_SxNDT_9 0x00000200U
+#define DMA_SxNDT_10 0x00000400U
+#define DMA_SxNDT_11 0x00000800U
+#define DMA_SxNDT_12 0x00001000U
+#define DMA_SxNDT_13 0x00002000U
+#define DMA_SxNDT_14 0x00004000U
+#define DMA_SxNDT_15 0x00008000U
+
+/******************** Bits definition for DMA_SxFCR register ****************/
+#define DMA_SxFCR_FEIE 0x00000080U
+#define DMA_SxFCR_FS 0x00000038U
+#define DMA_SxFCR_FS_0 0x00000008U
+#define DMA_SxFCR_FS_1 0x00000010U
+#define DMA_SxFCR_FS_2 0x00000020U
+#define DMA_SxFCR_DMDIS 0x00000004U
+#define DMA_SxFCR_FTH 0x00000003U
+#define DMA_SxFCR_FTH_0 0x00000001U
+#define DMA_SxFCR_FTH_1 0x00000002U
+
+/******************** Bits definition for DMA_LISR register *****************/
+#define DMA_LISR_TCIF3 0x08000000U
+#define DMA_LISR_HTIF3 0x04000000U
+#define DMA_LISR_TEIF3 0x02000000U
+#define DMA_LISR_DMEIF3 0x01000000U
+#define DMA_LISR_FEIF3 0x00400000U
+#define DMA_LISR_TCIF2 0x00200000U
+#define DMA_LISR_HTIF2 0x00100000U
+#define DMA_LISR_TEIF2 0x00080000U
+#define DMA_LISR_DMEIF2 0x00040000U
+#define DMA_LISR_FEIF2 0x00010000U
+#define DMA_LISR_TCIF1 0x00000800U
+#define DMA_LISR_HTIF1 0x00000400U
+#define DMA_LISR_TEIF1 0x00000200U
+#define DMA_LISR_DMEIF1 0x00000100U
+#define DMA_LISR_FEIF1 0x00000040U
+#define DMA_LISR_TCIF0 0x00000020U
+#define DMA_LISR_HTIF0 0x00000010U
+#define DMA_LISR_TEIF0 0x00000008U
+#define DMA_LISR_DMEIF0 0x00000004U
+#define DMA_LISR_FEIF0 0x00000001U
+
+/******************** Bits definition for DMA_HISR register *****************/
+#define DMA_HISR_TCIF7 0x08000000U
+#define DMA_HISR_HTIF7 0x04000000U
+#define DMA_HISR_TEIF7 0x02000000U
+#define DMA_HISR_DMEIF7 0x01000000U
+#define DMA_HISR_FEIF7 0x00400000U
+#define DMA_HISR_TCIF6 0x00200000U
+#define DMA_HISR_HTIF6 0x00100000U
+#define DMA_HISR_TEIF6 0x00080000U
+#define DMA_HISR_DMEIF6 0x00040000U
+#define DMA_HISR_FEIF6 0x00010000U
+#define DMA_HISR_TCIF5 0x00000800U
+#define DMA_HISR_HTIF5 0x00000400U
+#define DMA_HISR_TEIF5 0x00000200U
+#define DMA_HISR_DMEIF5 0x00000100U
+#define DMA_HISR_FEIF5 0x00000040U
+#define DMA_HISR_TCIF4 0x00000020U
+#define DMA_HISR_HTIF4 0x00000010U
+#define DMA_HISR_TEIF4 0x00000008U
+#define DMA_HISR_DMEIF4 0x00000004U
+#define DMA_HISR_FEIF4 0x00000001U
+
+/******************** Bits definition for DMA_LIFCR register ****************/
+#define DMA_LIFCR_CTCIF3 0x08000000U
+#define DMA_LIFCR_CHTIF3 0x04000000U
+#define DMA_LIFCR_CTEIF3 0x02000000U
+#define DMA_LIFCR_CDMEIF3 0x01000000U
+#define DMA_LIFCR_CFEIF3 0x00400000U
+#define DMA_LIFCR_CTCIF2 0x00200000U
+#define DMA_LIFCR_CHTIF2 0x00100000U
+#define DMA_LIFCR_CTEIF2 0x00080000U
+#define DMA_LIFCR_CDMEIF2 0x00040000U
+#define DMA_LIFCR_CFEIF2 0x00010000U
+#define DMA_LIFCR_CTCIF1 0x00000800U
+#define DMA_LIFCR_CHTIF1 0x00000400U
+#define DMA_LIFCR_CTEIF1 0x00000200U
+#define DMA_LIFCR_CDMEIF1 0x00000100U
+#define DMA_LIFCR_CFEIF1 0x00000040U
+#define DMA_LIFCR_CTCIF0 0x00000020U
+#define DMA_LIFCR_CHTIF0 0x00000010U
+#define DMA_LIFCR_CTEIF0 0x00000008U
+#define DMA_LIFCR_CDMEIF0 0x00000004U
+#define DMA_LIFCR_CFEIF0 0x00000001U
+
+/******************** Bits definition for DMA_HIFCR register ****************/
+#define DMA_HIFCR_CTCIF7 0x08000000U
+#define DMA_HIFCR_CHTIF7 0x04000000U
+#define DMA_HIFCR_CTEIF7 0x02000000U
+#define DMA_HIFCR_CDMEIF7 0x01000000U
+#define DMA_HIFCR_CFEIF7 0x00400000U
+#define DMA_HIFCR_CTCIF6 0x00200000U
+#define DMA_HIFCR_CHTIF6 0x00100000U
+#define DMA_HIFCR_CTEIF6 0x00080000U
+#define DMA_HIFCR_CDMEIF6 0x00040000U
+#define DMA_HIFCR_CFEIF6 0x00010000U
+#define DMA_HIFCR_CTCIF5 0x00000800U
+#define DMA_HIFCR_CHTIF5 0x00000400U
+#define DMA_HIFCR_CTEIF5 0x00000200U
+#define DMA_HIFCR_CDMEIF5 0x00000100U
+#define DMA_HIFCR_CFEIF5 0x00000040U
+#define DMA_HIFCR_CTCIF4 0x00000020U
+#define DMA_HIFCR_CHTIF4 0x00000010U
+#define DMA_HIFCR_CTEIF4 0x00000008U
+#define DMA_HIFCR_CDMEIF4 0x00000004U
+#define DMA_HIFCR_CFEIF4 0x00000001U
+
+
+/******************************************************************************/
+/* */
+/* AHB Master DMA2D Controller (DMA2D) */
+/* */
+/******************************************************************************/
+
+/******************** Bit definition for DMA2D_CR register ******************/
+
+#define DMA2D_CR_START 0x00000001U /*!< Start transfer */
+#define DMA2D_CR_SUSP 0x00000002U /*!< Suspend transfer */
+#define DMA2D_CR_ABORT 0x00000004U /*!< Abort transfer */
+#define DMA2D_CR_TEIE 0x00000100U /*!< Transfer Error Interrupt Enable */
+#define DMA2D_CR_TCIE 0x00000200U /*!< Transfer Complete Interrupt Enable */
+#define DMA2D_CR_TWIE 0x00000400U /*!< Transfer Watermark Interrupt Enable */
+#define DMA2D_CR_CAEIE 0x00000800U /*!< CLUT Access Error Interrupt Enable */
+#define DMA2D_CR_CTCIE 0x00001000U /*!< CLUT Transfer Complete Interrupt Enable */
+#define DMA2D_CR_CEIE 0x00002000U /*!< Configuration Error Interrupt Enable */
+#define DMA2D_CR_MODE 0x00030000U /*!< DMA2D Mode[1:0] */
+#define DMA2D_CR_MODE_0 0x00010000U /*!< DMA2D Mode bit 0 */
+#define DMA2D_CR_MODE_1 0x00020000U /*!< DMA2D Mode bit 1 */
+
+/******************** Bit definition for DMA2D_ISR register *****************/
+
+#define DMA2D_ISR_TEIF 0x00000001U /*!< Transfer Error Interrupt Flag */
+#define DMA2D_ISR_TCIF 0x00000002U /*!< Transfer Complete Interrupt Flag */
+#define DMA2D_ISR_TWIF 0x00000004U /*!< Transfer Watermark Interrupt Flag */
+#define DMA2D_ISR_CAEIF 0x00000008U /*!< CLUT Access Error Interrupt Flag */
+#define DMA2D_ISR_CTCIF 0x00000010U /*!< CLUT Transfer Complete Interrupt Flag */
+#define DMA2D_ISR_CEIF 0x00000020U /*!< Configuration Error Interrupt Flag */
+
+/******************** Bit definition for DMA2D_IFCR register ****************/
+
+#define DMA2D_IFCR_CTEIF 0x00000001U /*!< Clears Transfer Error Interrupt Flag */
+#define DMA2D_IFCR_CTCIF 0x00000002U /*!< Clears Transfer Complete Interrupt Flag */
+#define DMA2D_IFCR_CTWIF 0x00000004U /*!< Clears Transfer Watermark Interrupt Flag */
+#define DMA2D_IFCR_CAECIF 0x00000008U /*!< Clears CLUT Access Error Interrupt Flag */
+#define DMA2D_IFCR_CCTCIF 0x00000010U /*!< Clears CLUT Transfer Complete Interrupt Flag */
+#define DMA2D_IFCR_CCEIF 0x00000020U /*!< Clears Configuration Error Interrupt Flag */
+
+/* Legacy defines */
+#define DMA2D_IFSR_CTEIF DMA2D_IFCR_CTEIF /*!< Clears Transfer Error Interrupt Flag */
+#define DMA2D_IFSR_CTCIF DMA2D_IFCR_CTCIF /*!< Clears Transfer Complete Interrupt Flag */
+#define DMA2D_IFSR_CTWIF DMA2D_IFCR_CTWIF /*!< Clears Transfer Watermark Interrupt Flag */
+#define DMA2D_IFSR_CCAEIF DMA2D_IFCR_CAECIF /*!< Clears CLUT Access Error Interrupt Flag */
+#define DMA2D_IFSR_CCTCIF DMA2D_IFCR_CCTCIF /*!< Clears CLUT Transfer Complete Interrupt Flag */
+#define DMA2D_IFSR_CCEIF DMA2D_IFCR_CCEIF /*!< Clears Configuration Error Interrupt Flag */
+
+/******************** Bit definition for DMA2D_FGMAR register ***************/
+
+#define DMA2D_FGMAR_MA 0xFFFFFFFFU /*!< Memory Address */
+
+/******************** Bit definition for DMA2D_FGOR register ****************/
+
+#define DMA2D_FGOR_LO 0x00003FFFU /*!< Line Offset */
+
+/******************** Bit definition for DMA2D_BGMAR register ***************/
+
+#define DMA2D_BGMAR_MA 0xFFFFFFFFU /*!< Memory Address */
+
+/******************** Bit definition for DMA2D_BGOR register ****************/
+
+#define DMA2D_BGOR_LO 0x00003FFFU /*!< Line Offset */
+
+/******************** Bit definition for DMA2D_FGPFCCR register *************/
+
+#define DMA2D_FGPFCCR_CM 0x0000000FU /*!< Input color mode CM[3:0] */
+#define DMA2D_FGPFCCR_CM_0 0x00000001U /*!< Input color mode CM bit 0 */
+#define DMA2D_FGPFCCR_CM_1 0x00000002U /*!< Input color mode CM bit 1 */
+#define DMA2D_FGPFCCR_CM_2 0x00000004U /*!< Input color mode CM bit 2 */
+#define DMA2D_FGPFCCR_CM_3 0x00000008U /*!< Input color mode CM bit 3 */
+#define DMA2D_FGPFCCR_CCM 0x00000010U /*!< CLUT Color mode */
+#define DMA2D_FGPFCCR_START 0x00000020U /*!< Start */
+#define DMA2D_FGPFCCR_CS 0x0000FF00U /*!< CLUT size */
+#define DMA2D_FGPFCCR_AM 0x00030000U /*!< Alpha mode AM[1:0] */
+#define DMA2D_FGPFCCR_AM_0 0x00010000U /*!< Alpha mode AM bit 0 */
+#define DMA2D_FGPFCCR_AM_1 0x00020000U /*!< Alpha mode AM bit 1 */
+#define DMA2D_FGPFCCR_ALPHA 0xFF000000U /*!< Alpha value */
+
+/******************** Bit definition for DMA2D_FGCOLR register **************/
+
+#define DMA2D_FGCOLR_BLUE 0x000000FFU /*!< Blue Value */
+#define DMA2D_FGCOLR_GREEN 0x0000FF00U /*!< Green Value */
+#define DMA2D_FGCOLR_RED 0x00FF0000U /*!< Red Value */
+
+/******************** Bit definition for DMA2D_BGPFCCR register *************/
+
+#define DMA2D_BGPFCCR_CM 0x0000000FU /*!< Input color mode CM[3:0] */
+#define DMA2D_BGPFCCR_CM_0 0x00000001U /*!< Input color mode CM bit 0 */
+#define DMA2D_BGPFCCR_CM_1 0x00000002U /*!< Input color mode CM bit 1 */
+#define DMA2D_BGPFCCR_CM_2 0x00000004U /*!< Input color mode CM bit 2 */
+#define DMA2D_FGPFCCR_CM_3 0x00000008U /*!< Input color mode CM bit 3 */
+#define DMA2D_BGPFCCR_CCM 0x00000010U /*!< CLUT Color mode */
+#define DMA2D_BGPFCCR_START 0x00000020U /*!< Start */
+#define DMA2D_BGPFCCR_CS 0x0000FF00U /*!< CLUT size */
+#define DMA2D_BGPFCCR_AM 0x00030000U /*!< Alpha mode AM[1:0] */
+#define DMA2D_BGPFCCR_AM_0 0x00010000U /*!< Alpha mode AM bit 0 */
+#define DMA2D_BGPFCCR_AM_1 0x00020000U /*!< Alpha mode AM bit 1 */
+#define DMA2D_BGPFCCR_ALPHA 0xFF000000U /*!< background Input Alpha value */
+
+/******************** Bit definition for DMA2D_BGCOLR register **************/
+
+#define DMA2D_BGCOLR_BLUE 0x000000FFU /*!< Blue Value */
+#define DMA2D_BGCOLR_GREEN 0x0000FF00U /*!< Green Value */
+#define DMA2D_BGCOLR_RED 0x00FF0000U /*!< Red Value */
+
+/******************** Bit definition for DMA2D_FGCMAR register **************/
+
+#define DMA2D_FGCMAR_MA 0xFFFFFFFFU /*!< Memory Address */
+
+/******************** Bit definition for DMA2D_BGCMAR register **************/
+
+#define DMA2D_BGCMAR_MA 0xFFFFFFFFU /*!< Memory Address */
+
+/******************** Bit definition for DMA2D_OPFCCR register **************/
+
+#define DMA2D_OPFCCR_CM 0x00000007U /*!< Color mode CM[2:0] */
+#define DMA2D_OPFCCR_CM_0 0x00000001U /*!< Color mode CM bit 0 */
+#define DMA2D_OPFCCR_CM_1 0x00000002U /*!< Color mode CM bit 1 */
+#define DMA2D_OPFCCR_CM_2 0x00000004U /*!< Color mode CM bit 2 */
+
+/******************** Bit definition for DMA2D_OCOLR register ***************/
+
+/*!<Mode_ARGB8888/RGB888 */
+
+#define DMA2D_OCOLR_BLUE_1 0x000000FFU /*!< BLUE Value */
+#define DMA2D_OCOLR_GREEN_1 0x0000FF00U /*!< GREEN Value */
+#define DMA2D_OCOLR_RED_1 0x00FF0000U /*!< Red Value */
+#define DMA2D_OCOLR_ALPHA_1 0xFF000000U /*!< Alpha Channel Value */
+
+/*!<Mode_RGB565 */
+#define DMA2D_OCOLR_BLUE_2 0x0000001FU /*!< BLUE Value */
+#define DMA2D_OCOLR_GREEN_2 0x000007E0U /*!< GREEN Value */
+#define DMA2D_OCOLR_RED_2 0x0000F800U /*!< Red Value */
+
+/*!<Mode_ARGB1555 */
+#define DMA2D_OCOLR_BLUE_3 0x0000001FU /*!< BLUE Value */
+#define DMA2D_OCOLR_GREEN_3 0x000003E0U /*!< GREEN Value */
+#define DMA2D_OCOLR_RED_3 0x00007C00U /*!< Red Value */
+#define DMA2D_OCOLR_ALPHA_3 0x00008000U /*!< Alpha Channel Value */
+
+/*!<Mode_ARGB4444 */
+#define DMA2D_OCOLR_BLUE_4 0x0000000FU /*!< BLUE Value */
+#define DMA2D_OCOLR_GREEN_4 0x000000F0U /*!< GREEN Value */
+#define DMA2D_OCOLR_RED_4 0x00000F00U /*!< Red Value */
+#define DMA2D_OCOLR_ALPHA_4 0x0000F000U /*!< Alpha Channel Value */
+
+/******************** Bit definition for DMA2D_OMAR register ****************/
+
+#define DMA2D_OMAR_MA 0xFFFFFFFFU /*!< Memory Address */
+
+/******************** Bit definition for DMA2D_OOR register *****************/
+
+#define DMA2D_OOR_LO 0x00003FFFU /*!< Line Offset */
+
+/******************** Bit definition for DMA2D_NLR register *****************/
+
+#define DMA2D_NLR_NL 0x0000FFFFU /*!< Number of Lines */
+#define DMA2D_NLR_PL 0x3FFF0000U /*!< Pixel per Lines */
+
+/******************** Bit definition for DMA2D_LWR register *****************/
+
+#define DMA2D_LWR_LW 0x0000FFFFU /*!< Line Watermark */
+
+/******************** Bit definition for DMA2D_AMTCR register ***************/
+
+#define DMA2D_AMTCR_EN 0x00000001U /*!< Enable */
+#define DMA2D_AMTCR_DT 0x0000FF00U /*!< Dead Time */
+
+/******************** Bit definition for DMA2D_FGCLUT register **************/
+
+/******************** Bit definition for DMA2D_BGCLUT register **************/
+
+
+/******************************************************************************/
+/* */
+/* Display Serial Interface (DSI) */
+/* */
+/******************************************************************************/
+/******************* Bit definition for DSI_VR register *****************/
+#define DSI_VR 0x3133302AU /*!< DSI Host Version */
+
+/******************* Bit definition for DSI_CR register *****************/
+#define DSI_CR_EN 0x00000001U /*!< DSI Host power up and reset */
+
+/******************* Bit definition for DSI_CCR register ****************/
+#define DSI_CCR_TXECKDIV 0x000000FFU /*!< TX Escape Clock Division */
+#define DSI_CCR_TXECKDIV0 0x00000001U
+#define DSI_CCR_TXECKDIV1 0x00000002U
+#define DSI_CCR_TXECKDIV2 0x00000004U
+#define DSI_CCR_TXECKDIV3 0x00000008U
+#define DSI_CCR_TXECKDIV4 0x00000010U
+#define DSI_CCR_TXECKDIV5 0x00000020U
+#define DSI_CCR_TXECKDIV6 0x00000040U
+#define DSI_CCR_TXECKDIV7 0x00000080U
+
+#define DSI_CCR_TOCKDIV 0x0000FF00U /*!< Timeout Clock Division */
+#define DSI_CCR_TOCKDIV0 0x00000100U
+#define DSI_CCR_TOCKDIV1 0x00000200U
+#define DSI_CCR_TOCKDIV2 0x00000400U
+#define DSI_CCR_TOCKDIV3 0x00000800U
+#define DSI_CCR_TOCKDIV4 0x00001000U
+#define DSI_CCR_TOCKDIV5 0x00002000U
+#define DSI_CCR_TOCKDIV6 0x00004000U
+#define DSI_CCR_TOCKDIV7 0x00008000U
+
+/******************* Bit definition for DSI_LVCIDR register *************/
+#define DSI_LVCIDR_VCID 0x00000003U /*!< Virtual Channel ID */
+#define DSI_LVCIDR_VCID0 0x00000001U
+#define DSI_LVCIDR_VCID1 0x00000002U
+
+/******************* Bit definition for DSI_LCOLCR register *************/
+#define DSI_LCOLCR_COLC 0x0000000FU /*!< Color Coding */
+#define DSI_LCOLCR_COLC0 0x00000001U
+#define DSI_LCOLCR_COLC1 0x00000020U
+#define DSI_LCOLCR_COLC2 0x00000040U
+#define DSI_LCOLCR_COLC3 0x00000080U
+
+#define DSI_LCOLCR_LPE 0x00000100U /*!< Loosly Packet Enable */
+
+/******************* Bit definition for DSI_LPCR register ***************/
+#define DSI_LPCR_DEP 0x00000001U /*!< Data Enable Polarity */
+#define DSI_LPCR_VSP 0x00000002U /*!< VSYNC Polarity */
+#define DSI_LPCR_HSP 0x00000004U /*!< HSYNC Polarity */
+
+/******************* Bit definition for DSI_LPMCR register **************/
+#define DSI_LPMCR_VLPSIZE 0x000000FFU /*!< VACT Largest Packet Size */
+#define DSI_LPMCR_VLPSIZE0 0x00000001U
+#define DSI_LPMCR_VLPSIZE1 0x00000002U
+#define DSI_LPMCR_VLPSIZE2 0x00000004U
+#define DSI_LPMCR_VLPSIZE3 0x00000008U
+#define DSI_LPMCR_VLPSIZE4 0x00000010U
+#define DSI_LPMCR_VLPSIZE5 0x00000020U
+#define DSI_LPMCR_VLPSIZE6 0x00000040U
+#define DSI_LPMCR_VLPSIZE7 0x00000080U
+
+#define DSI_LPMCR_LPSIZE 0x00FF0000U /*!< Largest Packet Size */
+#define DSI_LPMCR_LPSIZE0 0x00010000U
+#define DSI_LPMCR_LPSIZE1 0x00020000U
+#define DSI_LPMCR_LPSIZE2 0x00040000U
+#define DSI_LPMCR_LPSIZE3 0x00080000U
+#define DSI_LPMCR_LPSIZE4 0x00100000U
+#define DSI_LPMCR_LPSIZE5 0x00200000U
+#define DSI_LPMCR_LPSIZE6 0x00400000U
+#define DSI_LPMCR_LPSIZE7 0x00800000U
+
+/******************* Bit definition for DSI_PCR register ****************/
+#define DSI_PCR_ETTXE 0x00000001U /*!< EoTp Transmission Enable */
+#define DSI_PCR_ETRXE 0x00000002U /*!< EoTp Reception Enable */
+#define DSI_PCR_BTAE 0x00000004U /*!< Bus Turn Around Enable */
+#define DSI_PCR_ECCRXE 0x00000008U /*!< ECC Reception Enable */
+#define DSI_PCR_CRCRXE 0x00000010U /*!< CRC Reception Enable */
+
+/******************* Bit definition for DSI_GVCIDR register *************/
+#define DSI_GVCIDR_VCID 0x00000003U /*!< Virtual Channel ID */
+#define DSI_GVCIDR_VCID0 0x00000001U
+#define DSI_GVCIDR_VCID1 0x00000002U
+
+/******************* Bit definition for DSI_MCR register ****************/
+#define DSI_MCR_CMDM 0x00000001U /*!< Command Mode */
+
+/******************* Bit definition for DSI_VMCR register ***************/
+#define DSI_VMCR_VMT 0x00000003U /*!< Video Mode Type */
+#define DSI_VMCR_VMT0 0x00000001U
+#define DSI_VMCR_VMT1 0x00000002U
+
+#define DSI_VMCR_LPVSAE 0x00000100U /*!< Low-Power Vertical Sync Active Enable */
+#define DSI_VMCR_LPVBPE 0x00000200U /*!< Low-power Vertical Back-Porch Enable */
+#define DSI_VMCR_LPVFPE 0x00000400U /*!< Low-power Vertical Front-porch Enable */
+#define DSI_VMCR_LPVAE 0x00000800U /*!< Low-Power Vertical Active Enable */
+#define DSI_VMCR_LPHBPE 0x00001000U /*!< Low-Power Horizontal Back-Porch Enable */
+#define DSI_VMCR_LPHFPE 0x00002000U /*!< Low-Power Horizontal Front-Porch Enable */
+#define DSI_VMCR_FBTAAE 0x00004000U /*!< Frame Bus-Turn-Around Acknowledge Enable */
+#define DSI_VMCR_LPCE 0x00008000U /*!< Low-Power Command Enable */
+#define DSI_VMCR_PGE 0x00010000U /*!< Pattern Generator Enable */
+#define DSI_VMCR_PGM 0x00100000U /*!< Pattern Generator Mode */
+#define DSI_VMCR_PGO 0x01000000U /*!< Pattern Generator Orientation */
+
+/******************* Bit definition for DSI_VPCR register ***************/
+#define DSI_VPCR_VPSIZE 0x00003FFFU /*!< Video Packet Size */
+#define DSI_VPCR_VPSIZE0 0x00000001U
+#define DSI_VPCR_VPSIZE1 0x00000002U
+#define DSI_VPCR_VPSIZE2 0x00000004U
+#define DSI_VPCR_VPSIZE3 0x00000008U
+#define DSI_VPCR_VPSIZE4 0x00000010U
+#define DSI_VPCR_VPSIZE5 0x00000020U
+#define DSI_VPCR_VPSIZE6 0x00000040U
+#define DSI_VPCR_VPSIZE7 0x00000080U
+#define DSI_VPCR_VPSIZE8 0x00000100U
+#define DSI_VPCR_VPSIZE9 0x00000200U
+#define DSI_VPCR_VPSIZE10 0x00000400U
+#define DSI_VPCR_VPSIZE11 0x00000800U
+#define DSI_VPCR_VPSIZE12 0x00001000U
+#define DSI_VPCR_VPSIZE13 0x00002000U
+
+/******************* Bit definition for DSI_VCCR register ***************/
+#define DSI_VCCR_NUMC 0x00001FFFU /*!< Number of Chunks */
+#define DSI_VCCR_NUMC0 0x00000001U
+#define DSI_VCCR_NUMC1 0x00000002U
+#define DSI_VCCR_NUMC2 0x00000004U
+#define DSI_VCCR_NUMC3 0x00000008U
+#define DSI_VCCR_NUMC4 0x00000010U
+#define DSI_VCCR_NUMC5 0x00000020U
+#define DSI_VCCR_NUMC6 0x00000040U
+#define DSI_VCCR_NUMC7 0x00000080U
+#define DSI_VCCR_NUMC8 0x00000100U
+#define DSI_VCCR_NUMC9 0x00000200U
+#define DSI_VCCR_NUMC10 0x00000400U
+#define DSI_VCCR_NUMC11 0x00000800U
+#define DSI_VCCR_NUMC12 0x00001000U
+
+/******************* Bit definition for DSI_VNPCR register **************/
+#define DSI_VNPCR_NPSIZE 0x00001FFFU /*!< Null Packet Size */
+#define DSI_VNPCR_NPSIZE0 0x00000001U
+#define DSI_VNPCR_NPSIZE1 0x00000002U
+#define DSI_VNPCR_NPSIZE2 0x00000004U
+#define DSI_VNPCR_NPSIZE3 0x00000008U
+#define DSI_VNPCR_NPSIZE4 0x00000010U
+#define DSI_VNPCR_NPSIZE5 0x00000020U
+#define DSI_VNPCR_NPSIZE6 0x00000040U
+#define DSI_VNPCR_NPSIZE7 0x00000080U
+#define DSI_VNPCR_NPSIZE8 0x00000100U
+#define DSI_VNPCR_NPSIZE9 0x00000200U
+#define DSI_VNPCR_NPSIZE10 0x00000400U
+#define DSI_VNPCR_NPSIZE11 0x00000800U
+#define DSI_VNPCR_NPSIZE12 0x00001000U
+
+/******************* Bit definition for DSI_VHSACR register *************/
+#define DSI_VHSACR_HSA 0x00000FFFU /*!< Horizontal Synchronism Active duration */
+#define DSI_VHSACR_HSA0 0x00000001U
+#define DSI_VHSACR_HSA1 0x00000002U
+#define DSI_VHSACR_HSA2 0x00000004U
+#define DSI_VHSACR_HSA3 0x00000008U
+#define DSI_VHSACR_HSA4 0x00000010U
+#define DSI_VHSACR_HSA5 0x00000020U
+#define DSI_VHSACR_HSA6 0x00000040U
+#define DSI_VHSACR_HSA7 0x00000080U
+#define DSI_VHSACR_HSA8 0x00000100U
+#define DSI_VHSACR_HSA9 0x00000200U
+#define DSI_VHSACR_HSA10 0x00000400U
+#define DSI_VHSACR_HSA11 0x00000800U
+
+/******************* Bit definition for DSI_VHBPCR register *************/
+#define DSI_VHBPCR_HBP 0x00000FFFU /*!< Horizontal Back-Porch duration */
+#define DSI_VHBPCR_HBP0 0x00000001U
+#define DSI_VHBPCR_HBP1 0x00000002U
+#define DSI_VHBPCR_HBP2 0x00000004U
+#define DSI_VHBPCR_HBP3 0x00000008U
+#define DSI_VHBPCR_HBP4 0x00000010U
+#define DSI_VHBPCR_HBP5 0x00000020U
+#define DSI_VHBPCR_HBP6 0x00000040U
+#define DSI_VHBPCR_HBP7 0x00000080U
+#define DSI_VHBPCR_HBP8 0x00000100U
+#define DSI_VHBPCR_HBP9 0x00000200U
+#define DSI_VHBPCR_HBP10 0x00000400U
+#define DSI_VHBPCR_HBP11 0x00000800U
+
+/******************* Bit definition for DSI_VLCR register ***************/
+#define DSI_VLCR_HLINE 0x00007FFFU /*!< Horizontal Line duration */
+#define DSI_VLCR_HLINE0 0x00000001U
+#define DSI_VLCR_HLINE1 0x00000002U
+#define DSI_VLCR_HLINE2 0x00000004U
+#define DSI_VLCR_HLINE3 0x00000008U
+#define DSI_VLCR_HLINE4 0x00000010U
+#define DSI_VLCR_HLINE5 0x00000020U
+#define DSI_VLCR_HLINE6 0x00000040U
+#define DSI_VLCR_HLINE7 0x00000080U
+#define DSI_VLCR_HLINE8 0x00000100U
+#define DSI_VLCR_HLINE9 0x00000200U
+#define DSI_VLCR_HLINE10 0x00000400U
+#define DSI_VLCR_HLINE11 0x00000800U
+#define DSI_VLCR_HLINE12 0x00001000U
+#define DSI_VLCR_HLINE13 0x00002000U
+#define DSI_VLCR_HLINE14 0x00004000U
+
+/******************* Bit definition for DSI_VVSACR register *************/
+#define DSI_VVSACR_VSA 0x000003FFU /*!< Vertical Synchronism Active duration */
+#define DSI_VVSACR_VSA0 0x00000001U
+#define DSI_VVSACR_VSA1 0x00000002U
+#define DSI_VVSACR_VSA2 0x00000004U
+#define DSI_VVSACR_VSA3 0x00000008U
+#define DSI_VVSACR_VSA4 0x00000010U
+#define DSI_VVSACR_VSA5 0x00000020U
+#define DSI_VVSACR_VSA6 0x00000040U
+#define DSI_VVSACR_VSA7 0x00000080U
+#define DSI_VVSACR_VSA8 0x00000100U
+#define DSI_VVSACR_VSA9 0x00000200U
+
+/******************* Bit definition for DSI_VVBPCR register *************/
+#define DSI_VVBPCR_VBP 0x000003FFU /*!< Vertical Back-Porch duration */
+#define DSI_VVBPCR_VBP0 0x00000001U
+#define DSI_VVBPCR_VBP1 0x00000002U
+#define DSI_VVBPCR_VBP2 0x00000004U
+#define DSI_VVBPCR_VBP3 0x00000008U
+#define DSI_VVBPCR_VBP4 0x00000010U
+#define DSI_VVBPCR_VBP5 0x00000020U
+#define DSI_VVBPCR_VBP6 0x00000040U
+#define DSI_VVBPCR_VBP7 0x00000080U
+#define DSI_VVBPCR_VBP8 0x00000100U
+#define DSI_VVBPCR_VBP9 0x00000200U
+
+/******************* Bit definition for DSI_VVFPCR register *************/
+#define DSI_VVFPCR_VFP 0x000003FFU /*!< Vertical Front-Porch duration */
+#define DSI_VVFPCR_VFP0 0x00000001U
+#define DSI_VVFPCR_VFP1 0x00000002U
+#define DSI_VVFPCR_VFP2 0x00000004U
+#define DSI_VVFPCR_VFP3 0x00000008U
+#define DSI_VVFPCR_VFP4 0x00000010U
+#define DSI_VVFPCR_VFP5 0x00000020U
+#define DSI_VVFPCR_VFP6 0x00000040U
+#define DSI_VVFPCR_VFP7 0x00000080U
+#define DSI_VVFPCR_VFP8 0x00000100U
+#define DSI_VVFPCR_VFP9 0x00000200U
+
+/******************* Bit definition for DSI_VVACR register **************/
+#define DSI_VVACR_VA 0x00003FFFU /*!< Vertical Active duration */
+#define DSI_VVACR_VA0 0x00000001U
+#define DSI_VVACR_VA1 0x00000002U
+#define DSI_VVACR_VA2 0x00000004U
+#define DSI_VVACR_VA3 0x00000008U
+#define DSI_VVACR_VA4 0x00000010U
+#define DSI_VVACR_VA5 0x00000020U
+#define DSI_VVACR_VA6 0x00000040U
+#define DSI_VVACR_VA7 0x00000080U
+#define DSI_VVACR_VA8 0x00000100U
+#define DSI_VVACR_VA9 0x00000200U
+#define DSI_VVACR_VA10 0x00000400U
+#define DSI_VVACR_VA11 0x00000800U
+#define DSI_VVACR_VA12 0x00001000U
+#define DSI_VVACR_VA13 0x00002000U
+
+/******************* Bit definition for DSI_LCCR register ***************/
+#define DSI_LCCR_CMDSIZE 0x0000FFFFU /*!< Command Size */
+#define DSI_LCCR_CMDSIZE0 0x00000001U
+#define DSI_LCCR_CMDSIZE1 0x00000002U
+#define DSI_LCCR_CMDSIZE2 0x00000004U
+#define DSI_LCCR_CMDSIZE3 0x00000008U
+#define DSI_LCCR_CMDSIZE4 0x00000010U
+#define DSI_LCCR_CMDSIZE5 0x00000020U
+#define DSI_LCCR_CMDSIZE6 0x00000040U
+#define DSI_LCCR_CMDSIZE7 0x00000080U
+#define DSI_LCCR_CMDSIZE8 0x00000100U
+#define DSI_LCCR_CMDSIZE9 0x00000200U
+#define DSI_LCCR_CMDSIZE10 0x00000400U
+#define DSI_LCCR_CMDSIZE11 0x00000800U
+#define DSI_LCCR_CMDSIZE12 0x00001000U
+#define DSI_LCCR_CMDSIZE13 0x00002000U
+#define DSI_LCCR_CMDSIZE14 0x00004000U
+#define DSI_LCCR_CMDSIZE15 0x00008000U
+
+/******************* Bit definition for DSI_CMCR register ***************/
+#define DSI_CMCR_TEARE 0x00000001U /*!< Tearing Effect Acknowledge Request Enable */
+#define DSI_CMCR_ARE 0x00000002U /*!< Acknowledge Request Enable */
+#define DSI_CMCR_GSW0TX 0x00000100U /*!< Generic Short Write Zero parameters Transmission */
+#define DSI_CMCR_GSW1TX 0x00000200U /*!< Generic Short Write One parameters Transmission */
+#define DSI_CMCR_GSW2TX 0x00000400U /*!< Generic Short Write Two parameters Transmission */
+#define DSI_CMCR_GSR0TX 0x00000800U /*!< Generic Short Read Zero parameters Transmission */
+#define DSI_CMCR_GSR1TX 0x00001000U /*!< Generic Short Read One parameters Transmission */
+#define DSI_CMCR_GSR2TX 0x00002000U /*!< Generic Short Read Two parameters Transmission */
+#define DSI_CMCR_GLWTX 0x00004000U /*!< Generic Long Write Transmission */
+#define DSI_CMCR_DSW0TX 0x00010000U /*!< DCS Short Write Zero parameter Transmission */
+#define DSI_CMCR_DSW1TX 0x00020000U /*!< DCS Short Read One parameter Transmission */
+#define DSI_CMCR_DSR0TX 0x00040000U /*!< DCS Short Read Zero parameter Transmission */
+#define DSI_CMCR_DLWTX 0x00080000U /*!< DCS Long Write Transmission */
+#define DSI_CMCR_MRDPS 0x01000000U /*!< Maximum Read Packet Size */
+
+/******************* Bit definition for DSI_GHCR register ***************/
+#define DSI_GHCR_DT 0x0000003FU /*!< Type */
+#define DSI_GHCR_DT0 0x00000001U
+#define DSI_GHCR_DT1 0x00000002U
+#define DSI_GHCR_DT2 0x00000004U
+#define DSI_GHCR_DT3 0x00000008U
+#define DSI_GHCR_DT4 0x00000010U
+#define DSI_GHCR_DT5 0x00000020U
+
+#define DSI_GHCR_VCID 0x000000C0U /*!< Channel */
+#define DSI_GHCR_VCID0 0x00000040U
+#define DSI_GHCR_VCID1 0x00000080U
+
+#define DSI_GHCR_WCLSB 0x0000FF00U /*!< WordCount LSB */
+#define DSI_GHCR_WCLSB0 0x00000100U
+#define DSI_GHCR_WCLSB1 0x00000200U
+#define DSI_GHCR_WCLSB2 0x00000400U
+#define DSI_GHCR_WCLSB3 0x00000800U
+#define DSI_GHCR_WCLSB4 0x00001000U
+#define DSI_GHCR_WCLSB5 0x00002000U
+#define DSI_GHCR_WCLSB6 0x00004000U
+#define DSI_GHCR_WCLSB7 0x00008000U
+
+#define DSI_GHCR_WCMSB 0x00FF0000U /*!< WordCount MSB */
+#define DSI_GHCR_WCMSB0 0x00010000U
+#define DSI_GHCR_WCMSB1 0x00020000U
+#define DSI_GHCR_WCMSB2 0x00040000U
+#define DSI_GHCR_WCMSB3 0x00080000U
+#define DSI_GHCR_WCMSB4 0x00100000U
+#define DSI_GHCR_WCMSB5 0x00200000U
+#define DSI_GHCR_WCMSB6 0x00400000U
+#define DSI_GHCR_WCMSB7 0x00800000U
+
+/******************* Bit definition for DSI_GPDR register ***************/
+#define DSI_GPDR_DATA1 0x000000FFU /*!< Payload Byte 1 */
+#define DSI_GPDR_DATA1_0 0x00000001U
+#define DSI_GPDR_DATA1_1 0x00000002U
+#define DSI_GPDR_DATA1_2 0x00000004U
+#define DSI_GPDR_DATA1_3 0x00000008U
+#define DSI_GPDR_DATA1_4 0x00000010U
+#define DSI_GPDR_DATA1_5 0x00000020U
+#define DSI_GPDR_DATA1_6 0x00000040U
+#define DSI_GPDR_DATA1_7 0x00000080U
+
+#define DSI_GPDR_DATA2 0x0000FF00U /*!< Payload Byte 2 */
+#define DSI_GPDR_DATA2_0 0x00000100U
+#define DSI_GPDR_DATA2_1 0x00000200U
+#define DSI_GPDR_DATA2_2 0x00000400U
+#define DSI_GPDR_DATA2_3 0x00000800U
+#define DSI_GPDR_DATA2_4 0x00001000U
+#define DSI_GPDR_DATA2_5 0x00002000U
+#define DSI_GPDR_DATA2_6 0x00004000U
+#define DSI_GPDR_DATA2_7 0x00008000U
+
+#define DSI_GPDR_DATA3 0x00FF0000U /*!< Payload Byte 3 */
+#define DSI_GPDR_DATA3_0 0x00010000U
+#define DSI_GPDR_DATA3_1 0x00020000U
+#define DSI_GPDR_DATA3_2 0x00040000U
+#define DSI_GPDR_DATA3_3 0x00080000U
+#define DSI_GPDR_DATA3_4 0x00100000U
+#define DSI_GPDR_DATA3_5 0x00200000U
+#define DSI_GPDR_DATA3_6 0x00400000U
+#define DSI_GPDR_DATA3_7 0x00800000U
+
+#define DSI_GPDR_DATA4 0xFF000000U /*!< Payload Byte 4 */
+#define DSI_GPDR_DATA4_0 0x01000000U
+#define DSI_GPDR_DATA4_1 0x02000000U
+#define DSI_GPDR_DATA4_2 0x04000000U
+#define DSI_GPDR_DATA4_3 0x08000000U
+#define DSI_GPDR_DATA4_4 0x10000000U
+#define DSI_GPDR_DATA4_5 0x20000000U
+#define DSI_GPDR_DATA4_6 0x40000000U
+#define DSI_GPDR_DATA4_7 0x80000000U
+
+/******************* Bit definition for DSI_GPSR register ***************/
+#define DSI_GPSR_CMDFE 0x00000001U /*!< Command FIFO Empty */
+#define DSI_GPSR_CMDFF 0x00000002U /*!< Command FIFO Full */
+#define DSI_GPSR_PWRFE 0x00000004U /*!< Payload Write FIFO Empty */
+#define DSI_GPSR_PWRFF 0x00000008U /*!< Payload Write FIFO Full */
+#define DSI_GPSR_PRDFE 0x00000010U /*!< Payload Read FIFO Empty */
+#define DSI_GPSR_PRDFF 0x00000020U /*!< Payload Read FIFO Full */
+#define DSI_GPSR_RCB 0x00000040U /*!< Read Command Busy */
+
+/******************* Bit definition for DSI_TCCR0 register **************/
+#define DSI_TCCR0_LPRX_TOCNT 0x0000FFFFU /*!< Low-power Reception Timeout Counter */
+#define DSI_TCCR0_LPRX_TOCNT0 0x00000001U
+#define DSI_TCCR0_LPRX_TOCNT1 0x00000002U
+#define DSI_TCCR0_LPRX_TOCNT2 0x00000004U
+#define DSI_TCCR0_LPRX_TOCNT3 0x00000008U
+#define DSI_TCCR0_LPRX_TOCNT4 0x00000010U
+#define DSI_TCCR0_LPRX_TOCNT5 0x00000020U
+#define DSI_TCCR0_LPRX_TOCNT6 0x00000040U
+#define DSI_TCCR0_LPRX_TOCNT7 0x00000080U
+#define DSI_TCCR0_LPRX_TOCNT8 0x00000100U
+#define DSI_TCCR0_LPRX_TOCNT9 0x00000200U
+#define DSI_TCCR0_LPRX_TOCNT10 0x00000400U
+#define DSI_TCCR0_LPRX_TOCNT11 0x00000800U
+#define DSI_TCCR0_LPRX_TOCNT12 0x00001000U
+#define DSI_TCCR0_LPRX_TOCNT13 0x00002000U
+#define DSI_TCCR0_LPRX_TOCNT14 0x00004000U
+#define DSI_TCCR0_LPRX_TOCNT15 0x00008000U
+
+#define DSI_TCCR0_HSTX_TOCNT 0xFFFF0000U /*!< High-Speed Transmission Timeout Counter */
+#define DSI_TCCR0_HSTX_TOCNT0 0x00010000U
+#define DSI_TCCR0_HSTX_TOCNT1 0x00020000U
+#define DSI_TCCR0_HSTX_TOCNT2 0x00040000U
+#define DSI_TCCR0_HSTX_TOCNT3 0x00080000U
+#define DSI_TCCR0_HSTX_TOCNT4 0x00100000U
+#define DSI_TCCR0_HSTX_TOCNT5 0x00200000U
+#define DSI_TCCR0_HSTX_TOCNT6 0x00400000U
+#define DSI_TCCR0_HSTX_TOCNT7 0x00800000U
+#define DSI_TCCR0_HSTX_TOCNT8 0x01000000U
+#define DSI_TCCR0_HSTX_TOCNT9 0x02000000U
+#define DSI_TCCR0_HSTX_TOCNT10 0x04000000U
+#define DSI_TCCR0_HSTX_TOCNT11 0x08000000U
+#define DSI_TCCR0_HSTX_TOCNT12 0x10000000U
+#define DSI_TCCR0_HSTX_TOCNT13 0x20000000U
+#define DSI_TCCR0_HSTX_TOCNT14 0x40000000U
+#define DSI_TCCR0_HSTX_TOCNT15 0x80000000U
+
+/******************* Bit definition for DSI_TCCR1 register **************/
+#define DSI_TCCR1_HSRD_TOCNT 0x0000FFFFU /*!< High-Speed Read Timeout Counter */
+#define DSI_TCCR1_HSRD_TOCNT0 0x00000001U
+#define DSI_TCCR1_HSRD_TOCNT1 0x00000002U
+#define DSI_TCCR1_HSRD_TOCNT2 0x00000004U
+#define DSI_TCCR1_HSRD_TOCNT3 0x00000008U
+#define DSI_TCCR1_HSRD_TOCNT4 0x00000010U
+#define DSI_TCCR1_HSRD_TOCNT5 0x00000020U
+#define DSI_TCCR1_HSRD_TOCNT6 0x00000040U
+#define DSI_TCCR1_HSRD_TOCNT7 0x00000080U
+#define DSI_TCCR1_HSRD_TOCNT8 0x00000100U
+#define DSI_TCCR1_HSRD_TOCNT9 0x00000200U
+#define DSI_TCCR1_HSRD_TOCNT10 0x00000400U
+#define DSI_TCCR1_HSRD_TOCNT11 0x00000800U
+#define DSI_TCCR1_HSRD_TOCNT12 0x00001000U
+#define DSI_TCCR1_HSRD_TOCNT13 0x00002000U
+#define DSI_TCCR1_HSRD_TOCNT14 0x00004000U
+#define DSI_TCCR1_HSRD_TOCNT15 0x00008000U
+
+/******************* Bit definition for DSI_TCCR2 register **************/
+#define DSI_TCCR2_LPRD_TOCNT 0x0000FFFFU /*!< Low-Power Read Timeout Counter */
+#define DSI_TCCR2_LPRD_TOCNT0 0x00000001U
+#define DSI_TCCR2_LPRD_TOCNT1 0x00000002U
+#define DSI_TCCR2_LPRD_TOCNT2 0x00000004U
+#define DSI_TCCR2_LPRD_TOCNT3 0x00000008U
+#define DSI_TCCR2_LPRD_TOCNT4 0x00000010U
+#define DSI_TCCR2_LPRD_TOCNT5 0x00000020U
+#define DSI_TCCR2_LPRD_TOCNT6 0x00000040U
+#define DSI_TCCR2_LPRD_TOCNT7 0x00000080U
+#define DSI_TCCR2_LPRD_TOCNT8 0x00000100U
+#define DSI_TCCR2_LPRD_TOCNT9 0x00000200U
+#define DSI_TCCR2_LPRD_TOCNT10 0x00000400U
+#define DSI_TCCR2_LPRD_TOCNT11 0x00000800U
+#define DSI_TCCR2_LPRD_TOCNT12 0x00001000U
+#define DSI_TCCR2_LPRD_TOCNT13 0x00002000U
+#define DSI_TCCR2_LPRD_TOCNT14 0x00004000U
+#define DSI_TCCR2_LPRD_TOCNT15 0x00008000U
+
+/******************* Bit definition for DSI_TCCR3 register **************/
+#define DSI_TCCR3_HSWR_TOCNT 0x0000FFFFU /*!< High-Speed Write Timeout Counter */
+#define DSI_TCCR3_HSWR_TOCNT0 0x00000001U
+#define DSI_TCCR3_HSWR_TOCNT1 0x00000002U
+#define DSI_TCCR3_HSWR_TOCNT2 0x00000004U
+#define DSI_TCCR3_HSWR_TOCNT3 0x00000008U
+#define DSI_TCCR3_HSWR_TOCNT4 0x00000010U
+#define DSI_TCCR3_HSWR_TOCNT5 0x00000020U
+#define DSI_TCCR3_HSWR_TOCNT6 0x00000040U
+#define DSI_TCCR3_HSWR_TOCNT7 0x00000080U
+#define DSI_TCCR3_HSWR_TOCNT8 0x00000100U
+#define DSI_TCCR3_HSWR_TOCNT9 0x00000200U
+#define DSI_TCCR3_HSWR_TOCNT10 0x00000400U
+#define DSI_TCCR3_HSWR_TOCNT11 0x00000800U
+#define DSI_TCCR3_HSWR_TOCNT12 0x00001000U
+#define DSI_TCCR3_HSWR_TOCNT13 0x00002000U
+#define DSI_TCCR3_HSWR_TOCNT14 0x00004000U
+#define DSI_TCCR3_HSWR_TOCNT15 0x00008000U
+
+#define DSI_TCCR3_PM 0x01000000U /*!< Presp Mode */
+
+/******************* Bit definition for DSI_TCCR4 register **************/
+#define DSI_TCCR4_LPWR_TOCNT 0x0000FFFFU /*!< Low-Power Write Timeout Counter */
+#define DSI_TCCR4_LPWR_TOCNT0 0x00000001U
+#define DSI_TCCR4_LPWR_TOCNT1 0x00000002U
+#define DSI_TCCR4_LPWR_TOCNT2 0x00000004U
+#define DSI_TCCR4_LPWR_TOCNT3 0x00000008U
+#define DSI_TCCR4_LPWR_TOCNT4 0x00000010U
+#define DSI_TCCR4_LPWR_TOCNT5 0x00000020U
+#define DSI_TCCR4_LPWR_TOCNT6 0x00000040U
+#define DSI_TCCR4_LPWR_TOCNT7 0x00000080U
+#define DSI_TCCR4_LPWR_TOCNT8 0x00000100U
+#define DSI_TCCR4_LPWR_TOCNT9 0x00000200U
+#define DSI_TCCR4_LPWR_TOCNT10 0x00000400U
+#define DSI_TCCR4_LPWR_TOCNT11 0x00000800U
+#define DSI_TCCR4_LPWR_TOCNT12 0x00001000U
+#define DSI_TCCR4_LPWR_TOCNT13 0x00002000U
+#define DSI_TCCR4_LPWR_TOCNT14 0x00004000U
+#define DSI_TCCR4_LPWR_TOCNT15 0x00008000U
+
+/******************* Bit definition for DSI_TCCR5 register **************/
+#define DSI_TCCR5_BTA_TOCNT 0x0000FFFFU /*!< Bus-Turn-Around Timeout Counter */
+#define DSI_TCCR5_BTA_TOCNT0 0x00000001U
+#define DSI_TCCR5_BTA_TOCNT1 0x00000002U
+#define DSI_TCCR5_BTA_TOCNT2 0x00000004U
+#define DSI_TCCR5_BTA_TOCNT3 0x00000008U
+#define DSI_TCCR5_BTA_TOCNT4 0x00000010U
+#define DSI_TCCR5_BTA_TOCNT5 0x00000020U
+#define DSI_TCCR5_BTA_TOCNT6 0x00000040U
+#define DSI_TCCR5_BTA_TOCNT7 0x00000080U
+#define DSI_TCCR5_BTA_TOCNT8 0x00000100U
+#define DSI_TCCR5_BTA_TOCNT9 0x00000200U
+#define DSI_TCCR5_BTA_TOCNT10 0x00000400U
+#define DSI_TCCR5_BTA_TOCNT11 0x00000800U
+#define DSI_TCCR5_BTA_TOCNT12 0x00001000U
+#define DSI_TCCR5_BTA_TOCNT13 0x00002000U
+#define DSI_TCCR5_BTA_TOCNT14 0x00004000U
+#define DSI_TCCR5_BTA_TOCNT15 0x00008000U
+
+/******************* Bit definition for DSI_TDCR register ***************/
+#define DSI_TDCR_3DM 0x00000003U /*!< 3D Mode */
+#define DSI_TDCR_3DM0 0x00000001U
+#define DSI_TDCR_3DM1 0x00000002U
+
+#define DSI_TDCR_3DF 0x0000000CU /*!< 3D Format */
+#define DSI_TDCR_3DF0 0x00000004U
+#define DSI_TDCR_3DF1 0x00000008U
+
+#define DSI_TDCR_SVS 0x00000010U /*!< Second VSYNC */
+#define DSI_TDCR_RF 0x00000020U /*!< Right First */
+#define DSI_TDCR_S3DC 0x00010000U /*!< Send 3D Control */
+
+/******************* Bit definition for DSI_CLCR register ***************/
+#define DSI_CLCR_DPCC 0x00000001U /*!< D-PHY Clock Control */
+#define DSI_CLCR_ACR 0x00000002U /*!< Automatic Clocklane Control */
+
+/******************* Bit definition for DSI_CLTCR register **************/
+#define DSI_CLTCR_LP2HS_TIME 0x000003FFU /*!< Low-Power to High-Speed Time */
+#define DSI_CLTCR_LP2HS_TIME0 0x00000001U
+#define DSI_CLTCR_LP2HS_TIME1 0x00000002U
+#define DSI_CLTCR_LP2HS_TIME2 0x00000004U
+#define DSI_CLTCR_LP2HS_TIME3 0x00000008U
+#define DSI_CLTCR_LP2HS_TIME4 0x00000010U
+#define DSI_CLTCR_LP2HS_TIME5 0x00000020U
+#define DSI_CLTCR_LP2HS_TIME6 0x00000040U
+#define DSI_CLTCR_LP2HS_TIME7 0x00000080U
+#define DSI_CLTCR_LP2HS_TIME8 0x00000100U
+#define DSI_CLTCR_LP2HS_TIME9 0x00000200U
+
+#define DSI_CLTCR_HS2LP_TIME 0x03FF0000U /*!< High-Speed to Low-Power Time */
+#define DSI_CLTCR_HS2LP_TIME0 0x00010000U
+#define DSI_CLTCR_HS2LP_TIME1 0x00020000U
+#define DSI_CLTCR_HS2LP_TIME2 0x00040000U
+#define DSI_CLTCR_HS2LP_TIME3 0x00080000U
+#define DSI_CLTCR_HS2LP_TIME4 0x00100000U
+#define DSI_CLTCR_HS2LP_TIME5 0x00200000U
+#define DSI_CLTCR_HS2LP_TIME6 0x00400000U
+#define DSI_CLTCR_HS2LP_TIME7 0x00800000U
+#define DSI_CLTCR_HS2LP_TIME8 0x01000000U
+#define DSI_CLTCR_HS2LP_TIME9 0x02000000U
+
+/******************* Bit definition for DSI_DLTCR register **************/
+#define DSI_DLTCR_MRD_TIME 0x00007FFFU /*!< Maximum Read Time */
+#define DSI_DLTCR_MRD_TIME0 0x00000001U
+#define DSI_DLTCR_MRD_TIME1 0x00000002U
+#define DSI_DLTCR_MRD_TIME2 0x00000004U
+#define DSI_DLTCR_MRD_TIME3 0x00000008U
+#define DSI_DLTCR_MRD_TIME4 0x00000010U
+#define DSI_DLTCR_MRD_TIME5 0x00000020U
+#define DSI_DLTCR_MRD_TIME6 0x00000040U
+#define DSI_DLTCR_MRD_TIME7 0x00000080U
+#define DSI_DLTCR_MRD_TIME8 0x00000100U
+#define DSI_DLTCR_MRD_TIME9 0x00000200U
+#define DSI_DLTCR_MRD_TIME10 0x00000400U
+#define DSI_DLTCR_MRD_TIME11 0x00000800U
+#define DSI_DLTCR_MRD_TIME12 0x00001000U
+#define DSI_DLTCR_MRD_TIME13 0x00002000U
+#define DSI_DLTCR_MRD_TIME14 0x00004000U
+
+#define DSI_DLTCR_LP2HS_TIME 0x00FF0000U /*!< Low-Power To High-Speed Time */
+#define DSI_DLTCR_LP2HS_TIME0 0x00010000U
+#define DSI_DLTCR_LP2HS_TIME1 0x00020000U
+#define DSI_DLTCR_LP2HS_TIME2 0x00040000U
+#define DSI_DLTCR_LP2HS_TIME3 0x00080000U
+#define DSI_DLTCR_LP2HS_TIME4 0x00100000U
+#define DSI_DLTCR_LP2HS_TIME5 0x00200000U
+#define DSI_DLTCR_LP2HS_TIME6 0x00400000U
+#define DSI_DLTCR_LP2HS_TIME7 0x00800000U
+
+#define DSI_DLTCR_HS2LP_TIME 0xFF000000U /*!< High-Speed To Low-Power Time */
+#define DSI_DLTCR_HS2LP_TIME0 0x01000000U
+#define DSI_DLTCR_HS2LP_TIME1 0x02000000U
+#define DSI_DLTCR_HS2LP_TIME2 0x04000000U
+#define DSI_DLTCR_HS2LP_TIME3 0x08000000U
+#define DSI_DLTCR_HS2LP_TIME4 0x10000000U
+#define DSI_DLTCR_HS2LP_TIME5 0x20000000U
+#define DSI_DLTCR_HS2LP_TIME6 0x40000000U
+#define DSI_DLTCR_HS2LP_TIME7 0x80000000U
+
+/******************* Bit definition for DSI_PCTLR register **************/
+#define DSI_PCTLR_DEN 0x00000002U /*!< Digital Enable */
+#define DSI_PCTLR_CKE 0x00000004U /*!< Clock Enable */
+
+/******************* Bit definition for DSI_PCONFR register *************/
+#define DSI_PCONFR_NL 0x00000003U /*!< Number of Lanes */
+#define DSI_PCONFR_NL0 0x00000001U
+#define DSI_PCONFR_NL1 0x00000002U
+
+#define DSI_PCONFR_SW_TIME 0x0000FF00U /*!< Stop Wait Time */
+#define DSI_PCONFR_SW_TIME0 0x00000100U
+#define DSI_PCONFR_SW_TIME1 0x00000200U
+#define DSI_PCONFR_SW_TIME2 0x00000400U
+#define DSI_PCONFR_SW_TIME3 0x00000800U
+#define DSI_PCONFR_SW_TIME4 0x00001000U
+#define DSI_PCONFR_SW_TIME5 0x00002000U
+#define DSI_PCONFR_SW_TIME6 0x00004000U
+#define DSI_PCONFR_SW_TIME7 0x00008000U
+
+/******************* Bit definition for DSI_PUCR register ***************/
+#define DSI_PUCR_URCL 0x00000001U /*!< ULPS Request on Clock Lane */
+#define DSI_PUCR_UECL 0x00000002U /*!< ULPS Exit on Clock Lane */
+#define DSI_PUCR_URDL 0x00000004U /*!< ULPS Request on Data Lane */
+#define DSI_PUCR_UEDL 0x00000008U /*!< ULPS Exit on Data Lane */
+
+/******************* Bit definition for DSI_PTTCR register **************/
+#define DSI_PTTCR_TX_TRIG 0x0000000FU /*!< Transmission Trigger */
+#define DSI_PTTCR_TX_TRIG0 0x00000001U
+#define DSI_PTTCR_TX_TRIG1 0x00000002U
+#define DSI_PTTCR_TX_TRIG2 0x00000004U
+#define DSI_PTTCR_TX_TRIG3 0x00000008U
+
+/******************* Bit definition for DSI_PSR register ****************/
+#define DSI_PSR_PD 0x00000002U /*!< PHY Direction */
+#define DSI_PSR_PSSC 0x00000004U /*!< PHY Stop State Clock lane */
+#define DSI_PSR_UANC 0x00000008U /*!< ULPS Active Not Clock lane */
+#define DSI_PSR_PSS0 0x00000010U /*!< PHY Stop State lane 0 */
+#define DSI_PSR_UAN0 0x00000020U /*!< ULPS Active Not lane 0 */
+#define DSI_PSR_RUE0 0x00000040U /*!< RX ULPS Escape lane 0 */
+#define DSI_PSR_PSS1 0x00000080U /*!< PHY Stop State lane 1 */
+#define DSI_PSR_UAN1 0x00000100U /*!< ULPS Active Not lane 1 */
+
+/******************* Bit definition for DSI_ISR0 register ***************/
+#define DSI_ISR0_AE0 0x00000001U /*!< Acknowledge Error 0 */
+#define DSI_ISR0_AE1 0x00000002U /*!< Acknowledge Error 1 */
+#define DSI_ISR0_AE2 0x00000004U /*!< Acknowledge Error 2 */
+#define DSI_ISR0_AE3 0x00000008U /*!< Acknowledge Error 3 */
+#define DSI_ISR0_AE4 0x00000010U /*!< Acknowledge Error 4 */
+#define DSI_ISR0_AE5 0x00000020U /*!< Acknowledge Error 5 */
+#define DSI_ISR0_AE6 0x00000040U /*!< Acknowledge Error 6 */
+#define DSI_ISR0_AE7 0x00000080U /*!< Acknowledge Error 7 */
+#define DSI_ISR0_AE8 0x00000100U /*!< Acknowledge Error 8 */
+#define DSI_ISR0_AE9 0x00000200U /*!< Acknowledge Error 9 */
+#define DSI_ISR0_AE10 0x00000400U /*!< Acknowledge Error 10 */
+#define DSI_ISR0_AE11 0x00000800U /*!< Acknowledge Error 11 */
+#define DSI_ISR0_AE12 0x00001000U /*!< Acknowledge Error 12 */
+#define DSI_ISR0_AE13 0x00002000U /*!< Acknowledge Error 13 */
+#define DSI_ISR0_AE14 0x00004000U /*!< Acknowledge Error 14 */
+#define DSI_ISR0_AE15 0x00008000U /*!< Acknowledge Error 15 */
+#define DSI_ISR0_PE0 0x00010000U /*!< PHY Error 0 */
+#define DSI_ISR0_PE1 0x00020000U /*!< PHY Error 1 */
+#define DSI_ISR0_PE2 0x00040000U /*!< PHY Error 2 */
+#define DSI_ISR0_PE3 0x00080000U /*!< PHY Error 3 */
+#define DSI_ISR0_PE4 0x00100000U /*!< PHY Error 4 */
+
+/******************* Bit definition for DSI_ISR1 register ***************/
+#define DSI_ISR1_TOHSTX 0x00000001U /*!< Timeout High-Speed Transmission */
+#define DSI_ISR1_TOLPRX 0x00000002U /*!< Timeout Low-Power Reception */
+#define DSI_ISR1_ECCSE 0x00000004U /*!< ECC Single-bit Error */
+#define DSI_ISR1_ECCME 0x00000008U /*!< ECC Multi-bit Error */
+#define DSI_ISR1_CRCE 0x00000010U /*!< CRC Error */
+#define DSI_ISR1_PSE 0x00000020U /*!< Packet Size Error */
+#define DSI_ISR1_EOTPE 0x00000040U /*!< EoTp Error */
+#define DSI_ISR1_LPWRE 0x00000080U /*!< LTDC Payload Write Error */
+#define DSI_ISR1_GCWRE 0x00000100U /*!< Generic Command Write Error */
+#define DSI_ISR1_GPWRE 0x00000200U /*!< Generic Payload Write Error */
+#define DSI_ISR1_GPTXE 0x00000400U /*!< Generic Payload Transmit Error */
+#define DSI_ISR1_GPRDE 0x00000800U /*!< Generic Payload Read Error */
+#define DSI_ISR1_GPRXE 0x00001000U /*!< Generic Payload Receive Error */
+
+/******************* Bit definition for DSI_IER0 register ***************/
+#define DSI_IER0_AE0IE 0x00000001U /*!< Acknowledge Error 0 Interrupt Enable */
+#define DSI_IER0_AE1IE 0x00000002U /*!< Acknowledge Error 1 Interrupt Enable */
+#define DSI_IER0_AE2IE 0x00000004U /*!< Acknowledge Error 2 Interrupt Enable */
+#define DSI_IER0_AE3IE 0x00000008U /*!< Acknowledge Error 3 Interrupt Enable */
+#define DSI_IER0_AE4IE 0x00000010U /*!< Acknowledge Error 4 Interrupt Enable */
+#define DSI_IER0_AE5IE 0x00000020U /*!< Acknowledge Error 5 Interrupt Enable */
+#define DSI_IER0_AE6IE 0x00000040U /*!< Acknowledge Error 6 Interrupt Enable */
+#define DSI_IER0_AE7IE 0x00000080U /*!< Acknowledge Error 7 Interrupt Enable */
+#define DSI_IER0_AE8IE 0x00000100U /*!< Acknowledge Error 8 Interrupt Enable */
+#define DSI_IER0_AE9IE 0x00000200U /*!< Acknowledge Error 9 Interrupt Enable */
+#define DSI_IER0_AE10IE 0x00000400U /*!< Acknowledge Error 10 Interrupt Enable */
+#define DSI_IER0_AE11IE 0x00000800U /*!< Acknowledge Error 11 Interrupt Enable */
+#define DSI_IER0_AE12IE 0x00001000U /*!< Acknowledge Error 12 Interrupt Enable */
+#define DSI_IER0_AE13IE 0x00002000U /*!< Acknowledge Error 13 Interrupt Enable */
+#define DSI_IER0_AE14IE 0x00004000U /*!< Acknowledge Error 14 Interrupt Enable */
+#define DSI_IER0_AE15IE 0x00008000U /*!< Acknowledge Error 15 Interrupt Enable */
+#define DSI_IER0_PE0IE 0x00010000U /*!< PHY Error 0 Interrupt Enable */
+#define DSI_IER0_PE1IE 0x00020000U /*!< PHY Error 1 Interrupt Enable */
+#define DSI_IER0_PE2IE 0x00040000U /*!< PHY Error 2 Interrupt Enable */
+#define DSI_IER0_PE3IE 0x00080000U /*!< PHY Error 3 Interrupt Enable */
+#define DSI_IER0_PE4IE 0x00100000U /*!< PHY Error 4 Interrupt Enable */
+
+/******************* Bit definition for DSI_IER1 register ***************/
+#define DSI_IER1_TOHSTXIE 0x00000001U /*!< Timeout High-Speed Transmission Interrupt Enable */
+#define DSI_IER1_TOLPRXIE 0x00000002U /*!< Timeout Low-Power Reception Interrupt Enable */
+#define DSI_IER1_ECCSEIE 0x00000004U /*!< ECC Single-bit Error Interrupt Enable */
+#define DSI_IER1_ECCMEIE 0x00000008U /*!< ECC Multi-bit Error Interrupt Enable */
+#define DSI_IER1_CRCEIE 0x00000010U /*!< CRC Error Interrupt Enable */
+#define DSI_IER1_PSEIE 0x00000020U /*!< Packet Size Error Interrupt Enable */
+#define DSI_IER1_EOTPEIE 0x00000040U /*!< EoTp Error Interrupt Enable */
+#define DSI_IER1_LPWREIE 0x00000080U /*!< LTDC Payload Write Error Interrupt Enable */
+#define DSI_IER1_GCWREIE 0x00000100U /*!< Generic Command Write Error Interrupt Enable */
+#define DSI_IER1_GPWREIE 0x00000200U /*!< Generic Payload Write Error Interrupt Enable */
+#define DSI_IER1_GPTXEIE 0x00000400U /*!< Generic Payload Transmit Error Interrupt Enable */
+#define DSI_IER1_GPRDEIE 0x00000800U /*!< Generic Payload Read Error Interrupt Enable */
+#define DSI_IER1_GPRXEIE 0x00001000U /*!< Generic Payload Receive Error Interrupt Enable */
+
+/******************* Bit definition for DSI_FIR0 register ***************/
+#define DSI_FIR0_FAE0 0x00000001U /*!< Force Acknowledge Error 0 */
+#define DSI_FIR0_FAE1 0x00000002U /*!< Force Acknowledge Error 1 */
+#define DSI_FIR0_FAE2 0x00000004U /*!< Force Acknowledge Error 2 */
+#define DSI_FIR0_FAE3 0x00000008U /*!< Force Acknowledge Error 3 */
+#define DSI_FIR0_FAE4 0x00000010U /*!< Force Acknowledge Error 4 */
+#define DSI_FIR0_FAE5 0x00000020U /*!< Force Acknowledge Error 5 */
+#define DSI_FIR0_FAE6 0x00000040U /*!< Force Acknowledge Error 6 */
+#define DSI_FIR0_FAE7 0x00000080U /*!< Force Acknowledge Error 7 */
+#define DSI_FIR0_FAE8 0x00000100U /*!< Force Acknowledge Error 8 */
+#define DSI_FIR0_FAE9 0x00000200U /*!< Force Acknowledge Error 9 */
+#define DSI_FIR0_FAE10 0x00000400U /*!< Force Acknowledge Error 10 */
+#define DSI_FIR0_FAE11 0x00000800U /*!< Force Acknowledge Error 11 */
+#define DSI_FIR0_FAE12 0x00001000U /*!< Force Acknowledge Error 12 */
+#define DSI_FIR0_FAE13 0x00002000U /*!< Force Acknowledge Error 13 */
+#define DSI_FIR0_FAE14 0x00004000U /*!< Force Acknowledge Error 14 */
+#define DSI_FIR0_FAE15 0x00008000U /*!< Force Acknowledge Error 15 */
+#define DSI_FIR0_FPE0 0x00010000U /*!< Force PHY Error 0 */
+#define DSI_FIR0_FPE1 0x00020000U /*!< Force PHY Error 1 */
+#define DSI_FIR0_FPE2 0x00040000U /*!< Force PHY Error 2 */
+#define DSI_FIR0_FPE3 0x00080000U /*!< Force PHY Error 3 */
+#define DSI_FIR0_FPE4 0x00100000U /*!< Force PHY Error 4 */
+
+/******************* Bit definition for DSI_FIR1 register ***************/
+#define DSI_FIR1_FTOHSTX 0x00000001U /*!< Force Timeout High-Speed Transmission */
+#define DSI_FIR1_FTOLPRX 0x00000002U /*!< Force Timeout Low-Power Reception */
+#define DSI_FIR1_FECCSE 0x00000004U /*!< Force ECC Single-bit Error */
+#define DSI_FIR1_FECCME 0x00000008U /*!< Force ECC Multi-bit Error */
+#define DSI_FIR1_FCRCE 0x00000010U /*!< Force CRC Error */
+#define DSI_FIR1_FPSE 0x00000020U /*!< Force Packet Size Error */
+#define DSI_FIR1_FEOTPE 0x00000040U /*!< Force EoTp Error */
+#define DSI_FIR1_FLPWRE 0x00000080U /*!< Force LTDC Payload Write Error */
+#define DSI_FIR1_FGCWRE 0x00000100U /*!< Force Generic Command Write Error */
+#define DSI_FIR1_FGPWRE 0x00000200U /*!< Force Generic Payload Write Error */
+#define DSI_FIR1_FGPTXE 0x00000400U /*!< Force Generic Payload Transmit Error */
+#define DSI_FIR1_FGPRDE 0x00000800U /*!< Force Generic Payload Read Error */
+#define DSI_FIR1_FGPRXE 0x00001000U /*!< Force Generic Payload Receive Error */
+
+/******************* Bit definition for DSI_VSCR register ***************/
+#define DSI_VSCR_EN 0x00000001U /*!< Enable */
+#define DSI_VSCR_UR 0x00000100U /*!< Update Register */
+
+/******************* Bit definition for DSI_LCVCIDR register ************/
+#define DSI_LCVCIDR_VCID 0x00000003U /*!< Virtual Channel ID */
+#define DSI_LCVCIDR_VCID0 0x00000001U
+#define DSI_LCVCIDR_VCID1 0x00000002U
+
+/******************* Bit definition for DSI_LCCCR register **************/
+#define DSI_LCCCR_COLC 0x0000000FU /*!< Color Coding */
+#define DSI_LCCCR_COLC0 0x00000001U
+#define DSI_LCCCR_COLC1 0x00000002U
+#define DSI_LCCCR_COLC2 0x00000004U
+#define DSI_LCCCR_COLC3 0x00000008U
+
+#define DSI_LCCCR_LPE 0x00000100U /*!< Loosely Packed Enable */
+
+/******************* Bit definition for DSI_LPMCCR register *************/
+#define DSI_LPMCCR_VLPSIZE 0x000000FFU /*!< VACT Largest Packet Size */
+#define DSI_LPMCCR_VLPSIZE0 0x00000001U
+#define DSI_LPMCCR_VLPSIZE1 0x00000002U
+#define DSI_LPMCCR_VLPSIZE2 0x00000004U
+#define DSI_LPMCCR_VLPSIZE3 0x00000008U
+#define DSI_LPMCCR_VLPSIZE4 0x00000010U
+#define DSI_LPMCCR_VLPSIZE5 0x00000020U
+#define DSI_LPMCCR_VLPSIZE6 0x00000040U
+#define DSI_LPMCCR_VLPSIZE7 0x00000080U
+
+#define DSI_LPMCCR_LPSIZE 0x00FF0000U /*!< Largest Packet Size */
+#define DSI_LPMCCR_LPSIZE0 0x00010000U
+#define DSI_LPMCCR_LPSIZE1 0x00020000U
+#define DSI_LPMCCR_LPSIZE2 0x00040000U
+#define DSI_LPMCCR_LPSIZE3 0x00080000U
+#define DSI_LPMCCR_LPSIZE4 0x00100000U
+#define DSI_LPMCCR_LPSIZE5 0x00200000U
+#define DSI_LPMCCR_LPSIZE6 0x00400000U
+#define DSI_LPMCCR_LPSIZE7 0x00800000U
+
+/******************* Bit definition for DSI_VMCCR register **************/
+#define DSI_VMCCR_VMT 0x00000003U /*!< Video Mode Type */
+#define DSI_VMCCR_VMT0 0x00000001U
+#define DSI_VMCCR_VMT1 0x00000002U
+
+#define DSI_VMCCR_LPVSAE 0x00000100U /*!< Low-power Vertical Sync time Enable */
+#define DSI_VMCCR_LPVBPE 0x00000200U /*!< Low-power Vertical Back-porch Enable */
+#define DSI_VMCCR_LPVFPE 0x00000400U /*!< Low-power Vertical Front-porch Enable */
+#define DSI_VMCCR_LPVAE 0x00000800U /*!< Low-power Vertical Active Enable */
+#define DSI_VMCCR_LPHBPE 0x00001000U /*!< Low-power Horizontal Back-porch Enable */
+#define DSI_VMCCR_LPHFE 0x00002000U /*!< Low-power Horizontal Front-porch Enable */
+#define DSI_VMCCR_FBTAAE 0x00004000U /*!< Frame BTA Acknowledge Enable */
+#define DSI_VMCCR_LPCE 0x00008000U /*!< Low-power Command Enable */
+
+/******************* Bit definition for DSI_VPCCR register **************/
+#define DSI_VPCCR_VPSIZE 0x00003FFFU /*!< Video Packet Size */
+#define DSI_VPCCR_VPSIZE0 0x00000001U
+#define DSI_VPCCR_VPSIZE1 0x00000002U
+#define DSI_VPCCR_VPSIZE2 0x00000004U
+#define DSI_VPCCR_VPSIZE3 0x00000008U
+#define DSI_VPCCR_VPSIZE4 0x00000010U
+#define DSI_VPCCR_VPSIZE5 0x00000020U
+#define DSI_VPCCR_VPSIZE6 0x00000040U
+#define DSI_VPCCR_VPSIZE7 0x00000080U
+#define DSI_VPCCR_VPSIZE8 0x00000100U
+#define DSI_VPCCR_VPSIZE9 0x00000200U
+#define DSI_VPCCR_VPSIZE10 0x00000400U
+#define DSI_VPCCR_VPSIZE11 0x00000800U
+#define DSI_VPCCR_VPSIZE12 0x00001000U
+#define DSI_VPCCR_VPSIZE13 0x00002000U
+
+/******************* Bit definition for DSI_VCCCR register **************/
+#define DSI_VCCCR_NUMC 0x00001FFFU /*!< Number of Chunks */
+#define DSI_VCCCR_NUMC0 0x00000001U
+#define DSI_VCCCR_NUMC1 0x00000002U
+#define DSI_VCCCR_NUMC2 0x00000004U
+#define DSI_VCCCR_NUMC3 0x00000008U
+#define DSI_VCCCR_NUMC4 0x00000010U
+#define DSI_VCCCR_NUMC5 0x00000020U
+#define DSI_VCCCR_NUMC6 0x00000040U
+#define DSI_VCCCR_NUMC7 0x00000080U
+#define DSI_VCCCR_NUMC8 0x00000100U
+#define DSI_VCCCR_NUMC9 0x00000200U
+#define DSI_VCCCR_NUMC10 0x00000400U
+#define DSI_VCCCR_NUMC11 0x00000800U
+#define DSI_VCCCR_NUMC12 0x00001000U
+
+/******************* Bit definition for DSI_VNPCCR register *************/
+#define DSI_VNPCCR_NPSIZE 0x00001FFFU /*!< Number of Chunks */
+#define DSI_VNPCCR_NPSIZE0 0x00000001U
+#define DSI_VNPCCR_NPSIZE1 0x00000002U
+#define DSI_VNPCCR_NPSIZE2 0x00000004U
+#define DSI_VNPCCR_NPSIZE3 0x00000008U
+#define DSI_VNPCCR_NPSIZE4 0x00000010U
+#define DSI_VNPCCR_NPSIZE5 0x00000020U
+#define DSI_VNPCCR_NPSIZE6 0x00000040U
+#define DSI_VNPCCR_NPSIZE7 0x00000080U
+#define DSI_VNPCCR_NPSIZE8 0x00000100U
+#define DSI_VNPCCR_NPSIZE9 0x00000200U
+#define DSI_VNPCCR_NPSIZE10 0x00000400U
+#define DSI_VNPCCR_NPSIZE11 0x00000800U
+#define DSI_VNPCCR_NPSIZE12 0x00001000U
+
+/******************* Bit definition for DSI_VHSACCR register ************/
+#define DSI_VHSACCR_HSA 0x00000FFFU /*!< Horizontal Synchronism Active duration */
+#define DSI_VHSACCR_HSA0 0x00000001U
+#define DSI_VHSACCR_HSA1 0x00000002U
+#define DSI_VHSACCR_HSA2 0x00000004U
+#define DSI_VHSACCR_HSA3 0x00000008U
+#define DSI_VHSACCR_HSA4 0x00000010U
+#define DSI_VHSACCR_HSA5 0x00000020U
+#define DSI_VHSACCR_HSA6 0x00000040U
+#define DSI_VHSACCR_HSA7 0x00000080U
+#define DSI_VHSACCR_HSA8 0x00000100U
+#define DSI_VHSACCR_HSA9 0x00000200U
+#define DSI_VHSACCR_HSA10 0x00000400U
+#define DSI_VHSACCR_HSA11 0x00000800U
+
+/******************* Bit definition for DSI_VHBPCCR register ************/
+#define DSI_VHBPCCR_HBP 0x00000FFFU /*!< Horizontal Back-Porch duration */
+#define DSI_VHBPCCR_HBP0 0x00000001U
+#define DSI_VHBPCCR_HBP1 0x00000002U
+#define DSI_VHBPCCR_HBP2 0x00000004U
+#define DSI_VHBPCCR_HBP3 0x00000008U
+#define DSI_VHBPCCR_HBP4 0x00000010U
+#define DSI_VHBPCCR_HBP5 0x00000020U
+#define DSI_VHBPCCR_HBP6 0x00000040U
+#define DSI_VHBPCCR_HBP7 0x00000080U
+#define DSI_VHBPCCR_HBP8 0x00000100U
+#define DSI_VHBPCCR_HBP9 0x00000200U
+#define DSI_VHBPCCR_HBP10 0x00000400U
+#define DSI_VHBPCCR_HBP11 0x00000800U
+
+/******************* Bit definition for DSI_VLCCR register **************/
+#define DSI_VLCCR_HLINE 0x00007FFFU /*!< Horizontal Line duration */
+#define DSI_VLCCR_HLINE0 0x00000001U
+#define DSI_VLCCR_HLINE1 0x00000002U
+#define DSI_VLCCR_HLINE2 0x00000004U
+#define DSI_VLCCR_HLINE3 0x00000008U
+#define DSI_VLCCR_HLINE4 0x00000010U
+#define DSI_VLCCR_HLINE5 0x00000020U
+#define DSI_VLCCR_HLINE6 0x00000040U
+#define DSI_VLCCR_HLINE7 0x00000080U
+#define DSI_VLCCR_HLINE8 0x00000100U
+#define DSI_VLCCR_HLINE9 0x00000200U
+#define DSI_VLCCR_HLINE10 0x00000400U
+#define DSI_VLCCR_HLINE11 0x00000800U
+#define DSI_VLCCR_HLINE12 0x00001000U
+#define DSI_VLCCR_HLINE13 0x00002000U
+#define DSI_VLCCR_HLINE14 0x00004000U
+
+/******************* Bit definition for DSI_VVSACCR register ***************/
+#define DSI_VVSACCR_VSA 0x000003FFU /*!< Vertical Synchronism Active duration */
+#define DSI_VVSACCR_VSA0 0x00000001U
+#define DSI_VVSACCR_VSA1 0x00000002U
+#define DSI_VVSACCR_VSA2 0x00000004U
+#define DSI_VVSACCR_VSA3 0x00000008U
+#define DSI_VVSACCR_VSA4 0x00000010U
+#define DSI_VVSACCR_VSA5 0x00000020U
+#define DSI_VVSACCR_VSA6 0x00000040U
+#define DSI_VVSACCR_VSA7 0x00000080U
+#define DSI_VVSACCR_VSA8 0x00000100U
+#define DSI_VVSACCR_VSA9 0x00000200U
+
+/******************* Bit definition for DSI_VVBPCCR register ************/
+#define DSI_VVBPCCR_VBP 0x000003FFU /*!< Vertical Back-Porch duration */
+#define DSI_VVBPCCR_VBP0 0x00000001U
+#define DSI_VVBPCCR_VBP1 0x00000002U
+#define DSI_VVBPCCR_VBP2 0x00000004U
+#define DSI_VVBPCCR_VBP3 0x00000008U
+#define DSI_VVBPCCR_VBP4 0x00000010U
+#define DSI_VVBPCCR_VBP5 0x00000020U
+#define DSI_VVBPCCR_VBP6 0x00000040U
+#define DSI_VVBPCCR_VBP7 0x00000080U
+#define DSI_VVBPCCR_VBP8 0x00000100U
+#define DSI_VVBPCCR_VBP9 0x00000200U
+
+/******************* Bit definition for DSI_VVFPCCR register ************/
+#define DSI_VVFPCCR_VFP 0x000003FFU /*!< Vertical Front-Porch duration */
+#define DSI_VVFPCCR_VFP0 0x00000001U
+#define DSI_VVFPCCR_VFP1 0x00000002U
+#define DSI_VVFPCCR_VFP2 0x00000004U
+#define DSI_VVFPCCR_VFP3 0x00000008U
+#define DSI_VVFPCCR_VFP4 0x00000010U
+#define DSI_VVFPCCR_VFP5 0x00000020U
+#define DSI_VVFPCCR_VFP6 0x00000040U
+#define DSI_VVFPCCR_VFP7 0x00000080U
+#define DSI_VVFPCCR_VFP8 0x00000100U
+#define DSI_VVFPCCR_VFP9 0x00000200U
+
+/******************* Bit definition for DSI_VVACCR register *************/
+#define DSI_VVACCR_VA 0x00003FFFU /*!< Vertical Active duration */
+#define DSI_VVACCR_VA0 0x00000001U
+#define DSI_VVACCR_VA1 0x00000002U
+#define DSI_VVACCR_VA2 0x00000004U
+#define DSI_VVACCR_VA3 0x00000008U
+#define DSI_VVACCR_VA4 0x00000010U
+#define DSI_VVACCR_VA5 0x00000020U
+#define DSI_VVACCR_VA6 0x00000040U
+#define DSI_VVACCR_VA7 0x00000080U
+#define DSI_VVACCR_VA8 0x00000100U
+#define DSI_VVACCR_VA9 0x00000200U
+#define DSI_VVACCR_VA10 0x00000400U
+#define DSI_VVACCR_VA11 0x00000800U
+#define DSI_VVACCR_VA12 0x00001000U
+#define DSI_VVACCR_VA13 0x00002000U
+
+/******************* Bit definition for DSI_TDCCR register **************/
+#define DSI_TDCCR_3DM 0x00000003U /*!< 3D Mode */
+#define DSI_TDCCR_3DM0 0x00000001U
+#define DSI_TDCCR_3DM1 0x00000002U
+
+#define DSI_TDCCR_3DF 0x0000000CU /*!< 3D Format */
+#define DSI_TDCCR_3DF0 0x00000004U
+#define DSI_TDCCR_3DF1 0x00000008U
+
+#define DSI_TDCCR_SVS 0x00000010U /*!< Second VSYNC */
+#define DSI_TDCCR_RF 0x00000020U /*!< Right First */
+#define DSI_TDCCR_S3DC 0x00010000U /*!< Send 3D Control */
+
+/******************* Bit definition for DSI_WCFGR register ***************/
+#define DSI_WCFGR_DSIM 0x00000001U /*!< DSI Mode */
+#define DSI_WCFGR_COLMUX 0x0000000EU /*!< Color Multiplexing */
+#define DSI_WCFGR_COLMUX0 0x00000002U
+#define DSI_WCFGR_COLMUX1 0x00000004U
+#define DSI_WCFGR_COLMUX2 0x00000008U
+
+#define DSI_WCFGR_TESRC 0x00000010U /*!< Tearing Effect Source */
+#define DSI_WCFGR_TEPOL 0x00000020U /*!< Tearing Effect Polarity */
+#define DSI_WCFGR_AR 0x00000040U /*!< Automatic Refresh */
+#define DSI_WCFGR_VSPOL 0x00000080U /*!< VSync Polarity */
+
+/******************* Bit definition for DSI_WCR register *****************/
+#define DSI_WCR_COLM 0x00000001U /*!< Color Mode */
+#define DSI_WCR_SHTDN 0x00000002U /*!< Shutdown */
+#define DSI_WCR_LTDCEN 0x00000004U /*!< LTDC Enable */
+#define DSI_WCR_DSIEN 0x00000008U /*!< DSI Enable */
+
+/******************* Bit definition for DSI_WIER register ****************/
+#define DSI_WIER_TEIE 0x00000001U /*!< Tearing Effect Interrupt Enable */
+#define DSI_WIER_ERIE 0x00000002U /*!< End of Refresh Interrupt Enable */
+#define DSI_WIER_PLLLIE 0x00000200U /*!< PLL Lock Interrupt Enable */
+#define DSI_WIER_PLLUIE 0x00000400U /*!< PLL Unlock Interrupt Enable */
+#define DSI_WIER_RRIE 0x00002000U /*!< Regulator Ready Interrupt Enable */
+
+/******************* Bit definition for DSI_WISR register ****************/
+#define DSI_WISR_TEIF 0x00000001U /*!< Tearing Effect Interrupt Flag */
+#define DSI_WISR_ERIF 0x00000002U /*!< End of Refresh Interrupt Flag */
+#define DSI_WISR_BUSY 0x00000004U /*!< Busy Flag */
+#define DSI_WISR_PLLLS 0x00000100U /*!< PLL Lock Status */
+#define DSI_WISR_PLLLIF 0x00000200U /*!< PLL Lock Interrupt Flag */
+#define DSI_WISR_PLLUIF 0x00000400U /*!< PLL Unlock Interrupt Flag */
+#define DSI_WISR_RRS 0x00001000U /*!< Regulator Ready Flag */
+#define DSI_WISR_RRIF 0x00002000U /*!< Regulator Ready Interrupt Flag */
+
+/******************* Bit definition for DSI_WIFCR register ***************/
+#define DSI_WIFCR_CTEIF 0x00000001U /*!< Clear Tearing Effect Interrupt Flag */
+#define DSI_WIFCR_CERIF 0x00000002U /*!< Clear End of Refresh Interrupt Flag */
+#define DSI_WIFCR_CPLLLIF 0x00000200U /*!< Clear PLL Lock Interrupt Flag */
+#define DSI_WIFCR_CPLLUIF 0x00000400U /*!< Clear PLL Unlock Interrupt Flag */
+#define DSI_WIFCR_CRRIF 0x00002000U /*!< Clear Regulator Ready Interrupt Flag */
+
+/******************* Bit definition for DSI_WPCR0 register ***************/
+#define DSI_WPCR0_UIX4 0x0000003FU /*!< Unit Interval multiplied by 4 */
+#define DSI_WPCR0_UIX4_0 0x00000001U
+#define DSI_WPCR0_UIX4_1 0x00000002U
+#define DSI_WPCR0_UIX4_2 0x00000004U
+#define DSI_WPCR0_UIX4_3 0x00000008U
+#define DSI_WPCR0_UIX4_4 0x00000010U
+#define DSI_WPCR0_UIX4_5 0x00000020U
+
+#define DSI_WPCR0_SWCL 0x00000040U /*!< Swap pins on clock lane */
+#define DSI_WPCR0_SWDL0 0x00000080U /*!< Swap pins on data lane 1 */
+#define DSI_WPCR0_SWDL1 0x00000100U /*!< Swap pins on data lane 2 */
+#define DSI_WPCR0_HSICL 0x00000200U /*!< Invert the high-speed data signal on clock lane */
+#define DSI_WPCR0_HSIDL0 0x00000400U /*!< Invert the high-speed data signal on lane 1 */
+#define DSI_WPCR0_HSIDL1 0x00000800U /*!< Invert the high-speed data signal on lane 2 */
+#define DSI_WPCR0_FTXSMCL 0x00001000U /*!< Force clock lane in TX stop mode */
+#define DSI_WPCR0_FTXSMDL 0x00002000U /*!< Force data lanes in TX stop mode */
+#define DSI_WPCR0_CDOFFDL 0x00004000U /*!< Contention detection OFF */
+#define DSI_WPCR0_TDDL 0x00010000U /*!< Turn Disable Data Lanes */
+#define DSI_WPCR0_PDEN 0x00040000U /*!< Pull-Down Enable */
+#define DSI_WPCR0_TCLKPREPEN 0x00080000U /*!< Timer for t-CLKPREP Enable */
+#define DSI_WPCR0_TCLKZEROEN 0x00100000U /*!< Timer for t-CLKZERO Enable */
+#define DSI_WPCR0_THSPREPEN 0x00200000U /*!< Timer for t-HSPREP Enable */
+#define DSI_WPCR0_THSTRAILEN 0x00400000U /*!< Timer for t-HSTRAIL Enable */
+#define DSI_WPCR0_THSZEROEN 0x00800000U /*!< Timer for t-HSZERO Enable */
+#define DSI_WPCR0_TLPXDEN 0x01000000U /*!< Timer for t-LPXD Enable */
+#define DSI_WPCR0_THSEXITEN 0x02000000U /*!< Timer for t-HSEXIT Enable */
+#define DSI_WPCR0_TLPXCEN 0x04000000U /*!< Timer for t-LPXC Enable */
+#define DSI_WPCR0_TCLKPOSTEN 0x08000000U /*!< Timer for t-CLKPOST Enable */
+
+/******************* Bit definition for DSI_WPCR1 register ***************/
+#define DSI_WPCR1_HSTXDCL 0x00000003U /*!< High-Speed Transmission Delay on Clock Lane */
+#define DSI_WPCR1_HSTXDCL0 0x00000001U
+#define DSI_WPCR1_HSTXDCL1 0x00000002U
+
+#define DSI_WPCR1_HSTXDDL 0x0000000CU /*!< High-Speed Transmission Delay on Data Lane */
+#define DSI_WPCR1_HSTXDDL0 0x00000004U
+#define DSI_WPCR1_HSTXDDL1 0x00000008U
+
+#define DSI_WPCR1_LPSRCCL 0x000000C0U /*!< Low-Power transmission Slew Rate Compensation on Clock Lane */
+#define DSI_WPCR1_LPSRCCL0 0x00000040U
+#define DSI_WPCR1_LPSRCCL1 0x00000080U
+
+#define DSI_WPCR1_LPSRCDL 0x00000300U /*!< Low-Power transmission Slew Rate Compensation on Data Lane */
+#define DSI_WPCR1_LPSRCDL0 0x00000100U
+#define DSI_WPCR1_LPSRCDL1 0x00000200U
+
+#define DSI_WPCR1_SDDC 0x00001000U /*!< SDD Control */
+
+#define DSI_WPCR1_LPRXVCDL 0x0000C000U /*!< Low-Power Reception V-IL Compensation on Data Lanes */
+#define DSI_WPCR1_LPRXVCDL0 0x00004000U
+#define DSI_WPCR1_LPRXVCDL1 0x00008000U
+
+#define DSI_WPCR1_HSTXSRCCL 0x00030000U /*!< High-Speed Transmission Delay on Clock Lane */
+#define DSI_WPCR1_HSTXSRCCL0 0x00010000U
+#define DSI_WPCR1_HSTXSRCCL1 0x00020000U
+
+#define DSI_WPCR1_HSTXSRCDL 0x000C0000U /*!< High-Speed Transmission Delay on Data Lane */
+#define DSI_WPCR1_HSTXSRCDL0 0x00040000U
+#define DSI_WPCR1_HSTXSRCDL1 0x00080000U
+
+#define DSI_WPCR1_FLPRXLPM 0x00400000U /*!< Forces LP Receiver in Low-Power Mode */
+
+#define DSI_WPCR1_LPRXFT 0x06000000U /*!< Low-Power RX low-pass Filtering Tuning */
+#define DSI_WPCR1_LPRXFT0 0x02000000U
+#define DSI_WPCR1_LPRXFT1 0x04000000U
+
+/******************* Bit definition for DSI_WPCR2 register ***************/
+#define DSI_WPCR2_TCLKPREP 0x000000FFU /*!< t-CLKPREP */
+#define DSI_WPCR2_TCLKPREP0 0x00000001U
+#define DSI_WPCR2_TCLKPREP1 0x00000002U
+#define DSI_WPCR2_TCLKPREP2 0x00000004U
+#define DSI_WPCR2_TCLKPREP3 0x00000008U
+#define DSI_WPCR2_TCLKPREP4 0x00000010U
+#define DSI_WPCR2_TCLKPREP5 0x00000020U
+#define DSI_WPCR2_TCLKPREP6 0x00000040U
+#define DSI_WPCR2_TCLKPREP7 0x00000080U
+
+#define DSI_WPCR2_TCLKZERO 0x0000FF00U /*!< t-CLKZERO */
+#define DSI_WPCR2_TCLKZERO0 0x00000100U
+#define DSI_WPCR2_TCLKZERO1 0x00000200U
+#define DSI_WPCR2_TCLKZERO2 0x00000400U
+#define DSI_WPCR2_TCLKZERO3 0x00000800U
+#define DSI_WPCR2_TCLKZERO4 0x00001000U
+#define DSI_WPCR2_TCLKZERO5 0x00002000U
+#define DSI_WPCR2_TCLKZERO6 0x00004000U
+#define DSI_WPCR2_TCLKZERO7 0x00008000U
+
+#define DSI_WPCR2_THSPREP 0x00FF0000U /*!< t-HSPREP */
+#define DSI_WPCR2_THSPREP0 0x00010000U
+#define DSI_WPCR2_THSPREP1 0x00020000U
+#define DSI_WPCR2_THSPREP2 0x00040000U
+#define DSI_WPCR2_THSPREP3 0x00080000U
+#define DSI_WPCR2_THSPREP4 0x00100000U
+#define DSI_WPCR2_THSPREP5 0x00200000U
+#define DSI_WPCR2_THSPREP6 0x00400000U
+#define DSI_WPCR2_THSPREP7 0x00800000U
+
+#define DSI_WPCR2_THSTRAIL 0xFF000000U /*!< t-HSTRAIL */
+#define DSI_WPCR2_THSTRAIL0 0x01000000U
+#define DSI_WPCR2_THSTRAIL1 0x02000000U
+#define DSI_WPCR2_THSTRAIL2 0x04000000U
+#define DSI_WPCR2_THSTRAIL3 0x08000000U
+#define DSI_WPCR2_THSTRAIL4 0x10000000U
+#define DSI_WPCR2_THSTRAIL5 0x20000000U
+#define DSI_WPCR2_THSTRAIL6 0x40000000U
+#define DSI_WPCR2_THSTRAIL7 0x80000000U
+
+/******************* Bit definition for DSI_WPCR3 register ***************/
+#define DSI_WPCR3_THSZERO 0x000000FFU /*!< t-HSZERO */
+#define DSI_WPCR3_THSZERO0 0x00000001U
+#define DSI_WPCR3_THSZERO1 0x00000002U
+#define DSI_WPCR3_THSZERO2 0x00000004U
+#define DSI_WPCR3_THSZERO3 0x00000008U
+#define DSI_WPCR3_THSZERO4 0x00000010U
+#define DSI_WPCR3_THSZERO5 0x00000020U
+#define DSI_WPCR3_THSZERO6 0x00000040U
+#define DSI_WPCR3_THSZERO7 0x00000080U
+
+#define DSI_WPCR3_TLPXD 0x0000FF00U /*!< t-LPXD */
+#define DSI_WPCR3_TLPXD0 0x00000100U
+#define DSI_WPCR3_TLPXD1 0x00000200U
+#define DSI_WPCR3_TLPXD2 0x00000400U
+#define DSI_WPCR3_TLPXD3 0x00000800U
+#define DSI_WPCR3_TLPXD4 0x00001000U
+#define DSI_WPCR3_TLPXD5 0x00002000U
+#define DSI_WPCR3_TLPXD6 0x00004000U
+#define DSI_WPCR3_TLPXD7 0x00008000U
+
+#define DSI_WPCR3_THSEXIT 0x00FF0000U /*!< t-HSEXIT */
+#define DSI_WPCR3_THSEXIT0 0x00010000U
+#define DSI_WPCR3_THSEXIT1 0x00020000U
+#define DSI_WPCR3_THSEXIT2 0x00040000U
+#define DSI_WPCR3_THSEXIT3 0x00080000U
+#define DSI_WPCR3_THSEXIT4 0x00100000U
+#define DSI_WPCR3_THSEXIT5 0x00200000U
+#define DSI_WPCR3_THSEXIT6 0x00400000U
+#define DSI_WPCR3_THSEXIT7 0x00800000U
+
+#define DSI_WPCR3_TLPXC 0xFF000000U /*!< t-LPXC */
+#define DSI_WPCR3_TLPXC0 0x01000000U
+#define DSI_WPCR3_TLPXC1 0x02000000U
+#define DSI_WPCR3_TLPXC2 0x04000000U
+#define DSI_WPCR3_TLPXC3 0x08000000U
+#define DSI_WPCR3_TLPXC4 0x10000000U
+#define DSI_WPCR3_TLPXC5 0x20000000U
+#define DSI_WPCR3_TLPXC6 0x40000000U
+#define DSI_WPCR3_TLPXC7 0x80000000U
+
+/******************* Bit definition for DSI_WPCR4 register ***************/
+#define DSI_WPCR4_TCLKPOST 0x000000FFU /*!< t-CLKPOST */
+#define DSI_WPCR4_TCLKPOST0 0x00000001U
+#define DSI_WPCR4_TCLKPOST1 0x00000002U
+#define DSI_WPCR4_TCLKPOST2 0x00000004U
+#define DSI_WPCR4_TCLKPOST3 0x00000008U
+#define DSI_WPCR4_TCLKPOST4 0x00000010U
+#define DSI_WPCR4_TCLKPOST5 0x00000020U
+#define DSI_WPCR4_TCLKPOST6 0x00000040U
+#define DSI_WPCR4_TCLKPOST7 0x00000080U
+
+/******************* Bit definition for DSI_WRPCR register ***************/
+#define DSI_WRPCR_PLLEN 0x00000001U /*!< PLL Enable */
+#define DSI_WRPCR_PLL_NDIV 0x000001FCU /*!< PLL Loop Division Factor */
+#define DSI_WRPCR_PLL_NDIV0 0x00000004U
+#define DSI_WRPCR_PLL_NDIV1 0x00000008U
+#define DSI_WRPCR_PLL_NDIV2 0x00000010U
+#define DSI_WRPCR_PLL_NDIV3 0x00000020U
+#define DSI_WRPCR_PLL_NDIV4 0x00000040U
+#define DSI_WRPCR_PLL_NDIV5 0x00000080U
+#define DSI_WRPCR_PLL_NDIV6 0x00000100U
+
+#define DSI_WRPCR_PLL_IDF 0x00007800U /*!< PLL Input Division Factor */
+#define DSI_WRPCR_PLL_IDF0 0x00000800U
+#define DSI_WRPCR_PLL_IDF1 0x00001000U
+#define DSI_WRPCR_PLL_IDF2 0x00002000U
+#define DSI_WRPCR_PLL_IDF3 0x00004000U
+
+#define DSI_WRPCR_PLL_ODF 0x00030000U /*!< PLL Output Division Factor */
+#define DSI_WRPCR_PLL_ODF0 0x00010000U
+#define DSI_WRPCR_PLL_ODF1 0x00020000U
+
+#define DSI_WRPCR_REGEN 0x01000000U /*!< Regulator Enable */
+
+/******************************************************************************/
+/* */
+/* External Interrupt/Event Controller */
+/* */
+/******************************************************************************/
+/******************* Bit definition for EXTI_IMR register *******************/
+#define EXTI_IMR_MR0 0x00000001U /*!< Interrupt Mask on line 0 */
+#define EXTI_IMR_MR1 0x00000002U /*!< Interrupt Mask on line 1 */
+#define EXTI_IMR_MR2 0x00000004U /*!< Interrupt Mask on line 2 */
+#define EXTI_IMR_MR3 0x00000008U /*!< Interrupt Mask on line 3 */
+#define EXTI_IMR_MR4 0x00000010U /*!< Interrupt Mask on line 4 */
+#define EXTI_IMR_MR5 0x00000020U /*!< Interrupt Mask on line 5 */
+#define EXTI_IMR_MR6 0x00000040U /*!< Interrupt Mask on line 6 */
+#define EXTI_IMR_MR7 0x00000080U /*!< Interrupt Mask on line 7 */
+#define EXTI_IMR_MR8 0x00000100U /*!< Interrupt Mask on line 8 */
+#define EXTI_IMR_MR9 0x00000200U /*!< Interrupt Mask on line 9 */
+#define EXTI_IMR_MR10 0x00000400U /*!< Interrupt Mask on line 10 */
+#define EXTI_IMR_MR11 0x00000800U /*!< Interrupt Mask on line 11 */
+#define EXTI_IMR_MR12 0x00001000U /*!< Interrupt Mask on line 12 */
+#define EXTI_IMR_MR13 0x00002000U /*!< Interrupt Mask on line 13 */
+#define EXTI_IMR_MR14 0x00004000U /*!< Interrupt Mask on line 14 */
+#define EXTI_IMR_MR15 0x00008000U /*!< Interrupt Mask on line 15 */
+#define EXTI_IMR_MR16 0x00010000U /*!< Interrupt Mask on line 16 */
+#define EXTI_IMR_MR17 0x00020000U /*!< Interrupt Mask on line 17 */
+#define EXTI_IMR_MR18 0x00040000U /*!< Interrupt Mask on line 18 */
+#define EXTI_IMR_MR19 0x00080000U /*!< Interrupt Mask on line 19 */
+#define EXTI_IMR_MR20 0x00100000U /*!< Interrupt Mask on line 20 */
+#define EXTI_IMR_MR21 0x00200000U /*!< Interrupt Mask on line 21 */
+#define EXTI_IMR_MR22 0x00400000U /*!< Interrupt Mask on line 22 */
+
+/******************* Bit definition for EXTI_EMR register *******************/
+#define EXTI_EMR_MR0 0x00000001U /*!< Event Mask on line 0 */
+#define EXTI_EMR_MR1 0x00000002U /*!< Event Mask on line 1 */
+#define EXTI_EMR_MR2 0x00000004U /*!< Event Mask on line 2 */
+#define EXTI_EMR_MR3 0x00000008U /*!< Event Mask on line 3 */
+#define EXTI_EMR_MR4 0x00000010U /*!< Event Mask on line 4 */
+#define EXTI_EMR_MR5 0x00000020U /*!< Event Mask on line 5 */
+#define EXTI_EMR_MR6 0x00000040U /*!< Event Mask on line 6 */
+#define EXTI_EMR_MR7 0x00000080U /*!< Event Mask on line 7 */
+#define EXTI_EMR_MR8 0x00000100U /*!< Event Mask on line 8 */
+#define EXTI_EMR_MR9 0x00000200U /*!< Event Mask on line 9 */
+#define EXTI_EMR_MR10 0x00000400U /*!< Event Mask on line 10 */
+#define EXTI_EMR_MR11 0x00000800U /*!< Event Mask on line 11 */
+#define EXTI_EMR_MR12 0x00001000U /*!< Event Mask on line 12 */
+#define EXTI_EMR_MR13 0x00002000U /*!< Event Mask on line 13 */
+#define EXTI_EMR_MR14 0x00004000U /*!< Event Mask on line 14 */
+#define EXTI_EMR_MR15 0x00008000U /*!< Event Mask on line 15 */
+#define EXTI_EMR_MR16 0x00010000U /*!< Event Mask on line 16 */
+#define EXTI_EMR_MR17 0x00020000U /*!< Event Mask on line 17 */
+#define EXTI_EMR_MR18 0x00040000U /*!< Event Mask on line 18 */
+#define EXTI_EMR_MR19 0x00080000U /*!< Event Mask on line 19 */
+#define EXTI_EMR_MR20 0x00100000U /*!< Event Mask on line 20 */
+#define EXTI_EMR_MR21 0x00200000U /*!< Event Mask on line 21 */
+#define EXTI_EMR_MR22 0x00400000U /*!< Event Mask on line 22 */
+
+/****************** Bit definition for EXTI_RTSR register *******************/
+#define EXTI_RTSR_TR0 0x00000001U /*!< Rising trigger event configuration bit of line 0 */
+#define EXTI_RTSR_TR1 0x00000002U /*!< Rising trigger event configuration bit of line 1 */
+#define EXTI_RTSR_TR2 0x00000004U /*!< Rising trigger event configuration bit of line 2 */
+#define EXTI_RTSR_TR3 0x00000008U /*!< Rising trigger event configuration bit of line 3 */
+#define EXTI_RTSR_TR4 0x00000010U /*!< Rising trigger event configuration bit of line 4 */
+#define EXTI_RTSR_TR5 0x00000020U /*!< Rising trigger event configuration bit of line 5 */
+#define EXTI_RTSR_TR6 0x00000040U /*!< Rising trigger event configuration bit of line 6 */
+#define EXTI_RTSR_TR7 0x00000080U /*!< Rising trigger event configuration bit of line 7 */
+#define EXTI_RTSR_TR8 0x00000100U /*!< Rising trigger event configuration bit of line 8 */
+#define EXTI_RTSR_TR9 0x00000200U /*!< Rising trigger event configuration bit of line 9 */
+#define EXTI_RTSR_TR10 0x00000400U /*!< Rising trigger event configuration bit of line 10 */
+#define EXTI_RTSR_TR11 0x00000800U /*!< Rising trigger event configuration bit of line 11 */
+#define EXTI_RTSR_TR12 0x00001000U /*!< Rising trigger event configuration bit of line 12 */
+#define EXTI_RTSR_TR13 0x00002000U /*!< Rising trigger event configuration bit of line 13 */
+#define EXTI_RTSR_TR14 0x00004000U /*!< Rising trigger event configuration bit of line 14 */
+#define EXTI_RTSR_TR15 0x00008000U /*!< Rising trigger event configuration bit of line 15 */
+#define EXTI_RTSR_TR16 0x00010000U /*!< Rising trigger event configuration bit of line 16 */
+#define EXTI_RTSR_TR17 0x00020000U /*!< Rising trigger event configuration bit of line 17 */
+#define EXTI_RTSR_TR18 0x00040000U /*!< Rising trigger event configuration bit of line 18 */
+#define EXTI_RTSR_TR19 0x00080000U /*!< Rising trigger event configuration bit of line 19 */
+#define EXTI_RTSR_TR20 0x00100000U /*!< Rising trigger event configuration bit of line 20 */
+#define EXTI_RTSR_TR21 0x00200000U /*!< Rising trigger event configuration bit of line 21 */
+#define EXTI_RTSR_TR22 0x00400000U /*!< Rising trigger event configuration bit of line 22 */
+
+/****************** Bit definition for EXTI_FTSR register *******************/
+#define EXTI_FTSR_TR0 0x00000001U /*!< Falling trigger event configuration bit of line 0 */
+#define EXTI_FTSR_TR1 0x00000002U /*!< Falling trigger event configuration bit of line 1 */
+#define EXTI_FTSR_TR2 0x00000004U /*!< Falling trigger event configuration bit of line 2 */
+#define EXTI_FTSR_TR3 0x00000008U /*!< Falling trigger event configuration bit of line 3 */
+#define EXTI_FTSR_TR4 0x00000010U /*!< Falling trigger event configuration bit of line 4 */
+#define EXTI_FTSR_TR5 0x00000020U /*!< Falling trigger event configuration bit of line 5 */
+#define EXTI_FTSR_TR6 0x00000040U /*!< Falling trigger event configuration bit of line 6 */
+#define EXTI_FTSR_TR7 0x00000080U /*!< Falling trigger event configuration bit of line 7 */
+#define EXTI_FTSR_TR8 0x00000100U /*!< Falling trigger event configuration bit of line 8 */
+#define EXTI_FTSR_TR9 0x00000200U /*!< Falling trigger event configuration bit of line 9 */
+#define EXTI_FTSR_TR10 0x00000400U /*!< Falling trigger event configuration bit of line 10 */
+#define EXTI_FTSR_TR11 0x00000800U /*!< Falling trigger event configuration bit of line 11 */
+#define EXTI_FTSR_TR12 0x00001000U /*!< Falling trigger event configuration bit of line 12 */
+#define EXTI_FTSR_TR13 0x00002000U /*!< Falling trigger event configuration bit of line 13 */
+#define EXTI_FTSR_TR14 0x00004000U /*!< Falling trigger event configuration bit of line 14 */
+#define EXTI_FTSR_TR15 0x00008000U /*!< Falling trigger event configuration bit of line 15 */
+#define EXTI_FTSR_TR16 0x00010000U /*!< Falling trigger event configuration bit of line 16 */
+#define EXTI_FTSR_TR17 0x00020000U /*!< Falling trigger event configuration bit of line 17 */
+#define EXTI_FTSR_TR18 0x00040000U /*!< Falling trigger event configuration bit of line 18 */
+#define EXTI_FTSR_TR19 0x00080000U /*!< Falling trigger event configuration bit of line 19 */
+#define EXTI_FTSR_TR20 0x00100000U /*!< Falling trigger event configuration bit of line 20 */
+#define EXTI_FTSR_TR21 0x00200000U /*!< Falling trigger event configuration bit of line 21 */
+#define EXTI_FTSR_TR22 0x00400000U /*!< Falling trigger event configuration bit of line 22 */
+
+/****************** Bit definition for EXTI_SWIER register ******************/
+#define EXTI_SWIER_SWIER0 0x00000001U /*!< Software Interrupt on line 0 */
+#define EXTI_SWIER_SWIER1 0x00000002U /*!< Software Interrupt on line 1 */
+#define EXTI_SWIER_SWIER2 0x00000004U /*!< Software Interrupt on line 2 */
+#define EXTI_SWIER_SWIER3 0x00000008U /*!< Software Interrupt on line 3 */
+#define EXTI_SWIER_SWIER4 0x00000010U /*!< Software Interrupt on line 4 */
+#define EXTI_SWIER_SWIER5 0x00000020U /*!< Software Interrupt on line 5 */
+#define EXTI_SWIER_SWIER6 0x00000040U /*!< Software Interrupt on line 6 */
+#define EXTI_SWIER_SWIER7 0x00000080U /*!< Software Interrupt on line 7 */
+#define EXTI_SWIER_SWIER8 0x00000100U /*!< Software Interrupt on line 8 */
+#define EXTI_SWIER_SWIER9 0x00000200U /*!< Software Interrupt on line 9 */
+#define EXTI_SWIER_SWIER10 0x00000400U /*!< Software Interrupt on line 10 */
+#define EXTI_SWIER_SWIER11 0x00000800U /*!< Software Interrupt on line 11 */
+#define EXTI_SWIER_SWIER12 0x00001000U /*!< Software Interrupt on line 12 */
+#define EXTI_SWIER_SWIER13 0x00002000U /*!< Software Interrupt on line 13 */
+#define EXTI_SWIER_SWIER14 0x00004000U /*!< Software Interrupt on line 14 */
+#define EXTI_SWIER_SWIER15 0x00008000U /*!< Software Interrupt on line 15 */
+#define EXTI_SWIER_SWIER16 0x00010000U /*!< Software Interrupt on line 16 */
+#define EXTI_SWIER_SWIER17 0x00020000U /*!< Software Interrupt on line 17 */
+#define EXTI_SWIER_SWIER18 0x00040000U /*!< Software Interrupt on line 18 */
+#define EXTI_SWIER_SWIER19 0x00080000U /*!< Software Interrupt on line 19 */
+#define EXTI_SWIER_SWIER20 0x00100000U /*!< Software Interrupt on line 20 */
+#define EXTI_SWIER_SWIER21 0x00200000U /*!< Software Interrupt on line 21 */
+#define EXTI_SWIER_SWIER22 0x00400000U /*!< Software Interrupt on line 22 */
+
+/******************* Bit definition for EXTI_PR register ********************/
+#define EXTI_PR_PR0 0x00000001U /*!< Pending bit for line 0 */
+#define EXTI_PR_PR1 0x00000002U /*!< Pending bit for line 1 */
+#define EXTI_PR_PR2 0x00000004U /*!< Pending bit for line 2 */
+#define EXTI_PR_PR3 0x00000008U /*!< Pending bit for line 3 */
+#define EXTI_PR_PR4 0x00000010U /*!< Pending bit for line 4 */
+#define EXTI_PR_PR5 0x00000020U /*!< Pending bit for line 5 */
+#define EXTI_PR_PR6 0x00000040U /*!< Pending bit for line 6 */
+#define EXTI_PR_PR7 0x00000080U /*!< Pending bit for line 7 */
+#define EXTI_PR_PR8 0x00000100U /*!< Pending bit for line 8 */
+#define EXTI_PR_PR9 0x00000200U /*!< Pending bit for line 9 */
+#define EXTI_PR_PR10 0x00000400U /*!< Pending bit for line 10 */
+#define EXTI_PR_PR11 0x00000800U /*!< Pending bit for line 11 */
+#define EXTI_PR_PR12 0x00001000U /*!< Pending bit for line 12 */
+#define EXTI_PR_PR13 0x00002000U /*!< Pending bit for line 13 */
+#define EXTI_PR_PR14 0x00004000U /*!< Pending bit for line 14 */
+#define EXTI_PR_PR15 0x00008000U /*!< Pending bit for line 15 */
+#define EXTI_PR_PR16 0x00010000U /*!< Pending bit for line 16 */
+#define EXTI_PR_PR17 0x00020000U /*!< Pending bit for line 17 */
+#define EXTI_PR_PR18 0x00040000U /*!< Pending bit for line 18 */
+#define EXTI_PR_PR19 0x00080000U /*!< Pending bit for line 19 */
+#define EXTI_PR_PR20 0x00100000U /*!< Pending bit for line 20 */
+#define EXTI_PR_PR21 0x00200000U /*!< Pending bit for line 21 */
+#define EXTI_PR_PR22 0x00400000U /*!< Pending bit for line 22 */
+
+/******************************************************************************/
+/* */
+/* FLASH */
+/* */
+/******************************************************************************/
+/******************* Bits definition for FLASH_ACR register *****************/
+#define FLASH_ACR_LATENCY 0x0000000FU
+#define FLASH_ACR_LATENCY_0WS 0x00000000U
+#define FLASH_ACR_LATENCY_1WS 0x00000001U
+#define FLASH_ACR_LATENCY_2WS 0x00000002U
+#define FLASH_ACR_LATENCY_3WS 0x00000003U
+#define FLASH_ACR_LATENCY_4WS 0x00000004U
+#define FLASH_ACR_LATENCY_5WS 0x00000005U
+#define FLASH_ACR_LATENCY_6WS 0x00000006U
+#define FLASH_ACR_LATENCY_7WS 0x00000007U
+#define FLASH_ACR_LATENCY_8WS 0x00000008U
+#define FLASH_ACR_LATENCY_9WS 0x00000009U
+#define FLASH_ACR_LATENCY_10WS 0x0000000AU
+#define FLASH_ACR_LATENCY_11WS 0x0000000BU
+#define FLASH_ACR_LATENCY_12WS 0x0000000CU
+#define FLASH_ACR_LATENCY_13WS 0x0000000DU
+#define FLASH_ACR_LATENCY_14WS 0x0000000EU
+#define FLASH_ACR_LATENCY_15WS 0x0000000FU
+#define FLASH_ACR_PRFTEN 0x00000100U
+#define FLASH_ACR_ICEN 0x00000200U
+#define FLASH_ACR_DCEN 0x00000400U
+#define FLASH_ACR_ICRST 0x00000800U
+#define FLASH_ACR_DCRST 0x00001000U
+#define FLASH_ACR_BYTE0_ADDRESS 0x40023C00U
+#define FLASH_ACR_BYTE2_ADDRESS 0x40023C03U
+
+/******************* Bits definition for FLASH_SR register ******************/
+#define FLASH_SR_EOP 0x00000001U
+#define FLASH_SR_SOP 0x00000002U
+#define FLASH_SR_WRPERR 0x00000010U
+#define FLASH_SR_PGAERR 0x00000020U
+#define FLASH_SR_PGPERR 0x00000040U
+#define FLASH_SR_PGSERR 0x00000080U
+#define FLASH_SR_BSY 0x00010000U
+
+/******************* Bits definition for FLASH_CR register ******************/
+#define FLASH_CR_PG 0x00000001U
+#define FLASH_CR_SER 0x00000002U
+#define FLASH_CR_MER 0x00000004U
+#define FLASH_CR_MER1 FLASH_CR_MER
+#define FLASH_CR_SNB 0x000000F8U
+#define FLASH_CR_SNB_0 0x00000008U
+#define FLASH_CR_SNB_1 0x00000010U
+#define FLASH_CR_SNB_2 0x00000020U
+#define FLASH_CR_SNB_3 0x00000040U
+#define FLASH_CR_SNB_4 0x00000080U
+#define FLASH_CR_PSIZE 0x00000300U
+#define FLASH_CR_PSIZE_0 0x00000100U
+#define FLASH_CR_PSIZE_1 0x00000200U
+#define FLASH_CR_MER2 0x00008000U
+#define FLASH_CR_STRT 0x00010000U
+#define FLASH_CR_EOPIE 0x01000000U
+#define FLASH_CR_LOCK 0x80000000U
+
+/******************* Bits definition for FLASH_OPTCR register ***************/
+#define FLASH_OPTCR_OPTLOCK 0x00000001U
+#define FLASH_OPTCR_OPTSTRT 0x00000002U
+#define FLASH_OPTCR_BOR_LEV_0 0x00000004U
+#define FLASH_OPTCR_BOR_LEV_1 0x00000008U
+#define FLASH_OPTCR_BOR_LEV 0x0000000CU
+#define FLASH_OPTCR_BFB2 0x00000010U
+#define FLASH_OPTCR_WDG_SW 0x00000020U
+#define FLASH_OPTCR_nRST_STOP 0x00000040U
+#define FLASH_OPTCR_nRST_STDBY 0x00000080U
+#define FLASH_OPTCR_RDP 0x0000FF00U
+#define FLASH_OPTCR_RDP_0 0x00000100U
+#define FLASH_OPTCR_RDP_1 0x00000200U
+#define FLASH_OPTCR_RDP_2 0x00000400U
+#define FLASH_OPTCR_RDP_3 0x00000800U
+#define FLASH_OPTCR_RDP_4 0x00001000U
+#define FLASH_OPTCR_RDP_5 0x00002000U
+#define FLASH_OPTCR_RDP_6 0x00004000U
+#define FLASH_OPTCR_RDP_7 0x00008000U
+#define FLASH_OPTCR_nWRP 0x0FFF0000U
+#define FLASH_OPTCR_nWRP_0 0x00010000U
+#define FLASH_OPTCR_nWRP_1 0x00020000U
+#define FLASH_OPTCR_nWRP_2 0x00040000U
+#define FLASH_OPTCR_nWRP_3 0x00080000U
+#define FLASH_OPTCR_nWRP_4 0x00100000U
+#define FLASH_OPTCR_nWRP_5 0x00200000U
+#define FLASH_OPTCR_nWRP_6 0x00400000U
+#define FLASH_OPTCR_nWRP_7 0x00800000U
+#define FLASH_OPTCR_nWRP_8 0x01000000U
+#define FLASH_OPTCR_nWRP_9 0x02000000U
+#define FLASH_OPTCR_nWRP_10 0x04000000U
+#define FLASH_OPTCR_nWRP_11 0x08000000U
+#define FLASH_OPTCR_DB1M 0x40000000U
+#define FLASH_OPTCR_SPRMOD 0x80000000U
+
+/****************** Bits definition for FLASH_OPTCR1 register ***************/
+#define FLASH_OPTCR1_nWRP 0x0FFF0000U
+#define FLASH_OPTCR1_nWRP_0 0x00010000U
+#define FLASH_OPTCR1_nWRP_1 0x00020000U
+#define FLASH_OPTCR1_nWRP_2 0x00040000U
+#define FLASH_OPTCR1_nWRP_3 0x00080000U
+#define FLASH_OPTCR1_nWRP_4 0x00100000U
+#define FLASH_OPTCR1_nWRP_5 0x00200000U
+#define FLASH_OPTCR1_nWRP_6 0x00400000U
+#define FLASH_OPTCR1_nWRP_7 0x00800000U
+#define FLASH_OPTCR1_nWRP_8 0x01000000U
+#define FLASH_OPTCR1_nWRP_9 0x02000000U
+#define FLASH_OPTCR1_nWRP_10 0x04000000U
+#define FLASH_OPTCR1_nWRP_11 0x08000000U
+
+/******************************************************************************/
+/* */
+/* Flexible Memory Controller */
+/* */
+/******************************************************************************/
+/****************** Bit definition for FMC_BCR1 register *******************/
+#define FMC_BCR1_MBKEN 0x00000001U /*!<Memory bank enable bit */
+#define FMC_BCR1_MUXEN 0x00000002U /*!<Address/data multiplexing enable bit */
+
+#define FMC_BCR1_MTYP 0x0000000CU /*!<MTYP[1:0] bits (Memory type) */
+#define FMC_BCR1_MTYP_0 0x00000004U /*!<Bit 0 */
+#define FMC_BCR1_MTYP_1 0x00000008U /*!<Bit 1 */
+
+#define FMC_BCR1_MWID 0x00000030U /*!<MWID[1:0] bits (Memory data bus width) */
+#define FMC_BCR1_MWID_0 0x00000010U /*!<Bit 0 */
+#define FMC_BCR1_MWID_1 0x00000020U /*!<Bit 1 */
+
+#define FMC_BCR1_FACCEN 0x00000040U /*!<Flash access enable */
+#define FMC_BCR1_BURSTEN 0x00000100U /*!<Burst enable bit */
+#define FMC_BCR1_WAITPOL 0x00000200U /*!<Wait signal polarity bit */
+#define FMC_BCR1_WAITCFG 0x00000800U /*!<Wait timing configuration */
+#define FMC_BCR1_WREN 0x00001000U /*!<Write enable bit */
+#define FMC_BCR1_WAITEN 0x00002000U /*!<Wait enable bit */
+#define FMC_BCR1_EXTMOD 0x00004000U /*!<Extended mode enable */
+#define FMC_BCR1_ASYNCWAIT 0x00008000U /*!<Asynchronous wait */
+#define FMC_BCR1_CPSIZE 0x00070000U /*!<CRAM page size */
+#define FMC_BCR1_CPSIZE_0 0x00010000U /*!<Bit 0 */
+#define FMC_BCR1_CPSIZE_1 0x00020000U /*!<Bit 1 */
+#define FMC_BCR1_CPSIZE_2 0x00040000U /*!<Bit 2 */
+#define FMC_BCR1_CBURSTRW 0x00080000U /*!<Write burst enable */
+#define FMC_BCR1_CCLKEN 0x00100000U /*!<Continous clock enable */
+#define FMC_BCR1_WFDIS 0x00200000U /*!<Write FIFO Disable */
+
+/****************** Bit definition for FMC_BCR2 register *******************/
+#define FMC_BCR2_MBKEN 0x00000001U /*!<Memory bank enable bit */
+#define FMC_BCR2_MUXEN 0x00000002U /*!<Address/data multiplexing enable bit */
+
+#define FMC_BCR2_MTYP 0x0000000CU /*!<MTYP[1:0] bits (Memory type) */
+#define FMC_BCR2_MTYP_0 0x00000004U /*!<Bit 0 */
+#define FMC_BCR2_MTYP_1 0x00000008U /*!<Bit 1 */
+
+#define FMC_BCR2_MWID 0x00000030U /*!<MWID[1:0] bits (Memory data bus width) */
+#define FMC_BCR2_MWID_0 0x00000010U /*!<Bit 0 */
+#define FMC_BCR2_MWID_1 0x00000020U /*!<Bit 1 */
+
+#define FMC_BCR2_FACCEN 0x00000040U /*!<Flash access enable */
+#define FMC_BCR2_BURSTEN 0x00000100U /*!<Burst enable bit */
+#define FMC_BCR2_WAITPOL 0x00000200U /*!<Wait signal polarity bit */
+#define FMC_BCR2_WAITCFG 0x00000800U /*!<Wait timing configuration */
+#define FMC_BCR2_WREN 0x00001000U /*!<Write enable bit */
+#define FMC_BCR2_WAITEN 0x00002000U /*!<Wait enable bit */
+#define FMC_BCR2_EXTMOD 0x00004000U /*!<Extended mode enable */
+#define FMC_BCR2_ASYNCWAIT 0x00008000U /*!<Asynchronous wait */
+#define FMC_BCR2_CBURSTRW 0x00080000U /*!<Write burst enable */
+
+/****************** Bit definition for FMC_BCR3 register *******************/
+#define FMC_BCR3_MBKEN 0x00000001U /*!<Memory bank enable bit */
+#define FMC_BCR3_MUXEN 0x00000002U /*!<Address/data multiplexing enable bit */
+
+#define FMC_BCR3_MTYP 0x0000000CU /*!<MTYP[1:0] bits (Memory type) */
+#define FMC_BCR3_MTYP_0 0x00000004U /*!<Bit 0 */
+#define FMC_BCR3_MTYP_1 0x00000008U /*!<Bit 1 */
+
+#define FMC_BCR3_MWID 0x00000030U /*!<MWID[1:0] bits (Memory data bus width) */
+#define FMC_BCR3_MWID_0 0x00000010U /*!<Bit 0 */
+#define FMC_BCR3_MWID_1 0x00000020U /*!<Bit 1 */
+
+#define FMC_BCR3_FACCEN 0x00000040U /*!<Flash access enable */
+#define FMC_BCR3_BURSTEN 0x00000100U /*!<Burst enable bit */
+#define FMC_BCR3_WAITPOL 0x00000200U /*!<Wait signal polarity bit */
+#define FMC_BCR3_WAITCFG 0x00000800U /*!<Wait timing configuration */
+#define FMC_BCR3_WREN 0x00001000U /*!<Write enable bit */
+#define FMC_BCR3_WAITEN 0x00002000U /*!<Wait enable bit */
+#define FMC_BCR3_EXTMOD 0x00004000U /*!<Extended mode enable */
+#define FMC_BCR3_ASYNCWAIT 0x00008000U /*!<Asynchronous wait */
+#define FMC_BCR3_CBURSTRW 0x00080000U /*!<Write burst enable */
+
+/****************** Bit definition for FMC_BCR4 register *******************/
+#define FMC_BCR4_MBKEN 0x00000001U /*!<Memory bank enable bit */
+#define FMC_BCR4_MUXEN 0x00000002U /*!<Address/data multiplexing enable bit */
+
+#define FMC_BCR4_MTYP 0x0000000CU /*!<MTYP[1:0] bits (Memory type) */
+#define FMC_BCR4_MTYP_0 0x00000004U /*!<Bit 0 */
+#define FMC_BCR4_MTYP_1 0x00000008U /*!<Bit 1 */
+
+#define FMC_BCR4_MWID 0x00000030U /*!<MWID[1:0] bits (Memory data bus width) */
+#define FMC_BCR4_MWID_0 0x00000010U /*!<Bit 0 */
+#define FMC_BCR4_MWID_1 0x00000020U /*!<Bit 1 */
+
+#define FMC_BCR4_FACCEN 0x00000040U /*!<Flash access enable */
+#define FMC_BCR4_BURSTEN 0x00000100U /*!<Burst enable bit */
+#define FMC_BCR4_WAITPOL 0x00000200U /*!<Wait signal polarity bit */
+#define FMC_BCR4_WAITCFG 0x00000800U /*!<Wait timing configuration */
+#define FMC_BCR4_WREN 0x00001000U /*!<Write enable bit */
+#define FMC_BCR4_WAITEN 0x00002000U /*!<Wait enable bit */
+#define FMC_BCR4_EXTMOD 0x00004000U /*!<Extended mode enable */
+#define FMC_BCR4_ASYNCWAIT 0x00008000U /*!<Asynchronous wait */
+#define FMC_BCR4_CBURSTRW 0x00080000U /*!<Write burst enable */
+
+/****************** Bit definition for FMC_BTR1 register ******************/
+#define FMC_BTR1_ADDSET 0x0000000FU /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FMC_BTR1_ADDSET_0 0x00000001U /*!<Bit 0 */
+#define FMC_BTR1_ADDSET_1 0x00000002U /*!<Bit 1 */
+#define FMC_BTR1_ADDSET_2 0x00000004U /*!<Bit 2 */
+#define FMC_BTR1_ADDSET_3 0x00000008U /*!<Bit 3 */
+
+#define FMC_BTR1_ADDHLD 0x000000F0U /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FMC_BTR1_ADDHLD_0 0x00000010U /*!<Bit 0 */
+#define FMC_BTR1_ADDHLD_1 0x00000020U /*!<Bit 1 */
+#define FMC_BTR1_ADDHLD_2 0x00000040U /*!<Bit 2 */
+#define FMC_BTR1_ADDHLD_3 0x00000080U /*!<Bit 3 */
+
+#define FMC_BTR1_DATAST 0x0000FF00U /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FMC_BTR1_DATAST_0 0x00000100U /*!<Bit 0 */
+#define FMC_BTR1_DATAST_1 0x00000200U /*!<Bit 1 */
+#define FMC_BTR1_DATAST_2 0x00000400U /*!<Bit 2 */
+#define FMC_BTR1_DATAST_3 0x00000800U /*!<Bit 3 */
+#define FMC_BTR1_DATAST_4 0x00001000U /*!<Bit 4 */
+#define FMC_BTR1_DATAST_5 0x00002000U /*!<Bit 5 */
+#define FMC_BTR1_DATAST_6 0x00004000U /*!<Bit 6 */
+#define FMC_BTR1_DATAST_7 0x00008000U /*!<Bit 7 */
+
+#define FMC_BTR1_BUSTURN 0x000F0000U /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define FMC_BTR1_BUSTURN_0 0x00010000U /*!<Bit 0 */
+#define FMC_BTR1_BUSTURN_1 0x00020000U /*!<Bit 1 */
+#define FMC_BTR1_BUSTURN_2 0x00040000U /*!<Bit 2 */
+#define FMC_BTR1_BUSTURN_3 0x00080000U /*!<Bit 3 */
+
+#define FMC_BTR1_CLKDIV 0x00F00000U /*!<CLKDIV[3:0] bits (Clock divide ratio) */
+#define FMC_BTR1_CLKDIV_0 0x00100000U /*!<Bit 0 */
+#define FMC_BTR1_CLKDIV_1 0x00200000U /*!<Bit 1 */
+#define FMC_BTR1_CLKDIV_2 0x00400000U /*!<Bit 2 */
+#define FMC_BTR1_CLKDIV_3 0x00800000U /*!<Bit 3 */
+
+#define FMC_BTR1_DATLAT 0x0F000000U /*!<DATLA[3:0] bits (Data latency) */
+#define FMC_BTR1_DATLAT_0 0x01000000U /*!<Bit 0 */
+#define FMC_BTR1_DATLAT_1 0x02000000U /*!<Bit 1 */
+#define FMC_BTR1_DATLAT_2 0x04000000U /*!<Bit 2 */
+#define FMC_BTR1_DATLAT_3 0x08000000U /*!<Bit 3 */
+
+#define FMC_BTR1_ACCMOD 0x30000000U /*!<ACCMOD[1:0] bits (Access mode) */
+#define FMC_BTR1_ACCMOD_0 0x10000000U /*!<Bit 0 */
+#define FMC_BTR1_ACCMOD_1 0x20000000U /*!<Bit 1 */
+
+/****************** Bit definition for FMC_BTR2 register *******************/
+#define FMC_BTR2_ADDSET 0x0000000FU /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FMC_BTR2_ADDSET_0 0x00000001U /*!<Bit 0 */
+#define FMC_BTR2_ADDSET_1 0x00000002U /*!<Bit 1 */
+#define FMC_BTR2_ADDSET_2 0x00000004U /*!<Bit 2 */
+#define FMC_BTR2_ADDSET_3 0x00000008U /*!<Bit 3 */
+
+#define FMC_BTR2_ADDHLD 0x000000F0U /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FMC_BTR2_ADDHLD_0 0x00000010U /*!<Bit 0 */
+#define FMC_BTR2_ADDHLD_1 0x00000020U /*!<Bit 1 */
+#define FMC_BTR2_ADDHLD_2 0x00000040U /*!<Bit 2 */
+#define FMC_BTR2_ADDHLD_3 0x00000080U /*!<Bit 3 */
+
+#define FMC_BTR2_DATAST 0x0000FF00U /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FMC_BTR2_DATAST_0 0x00000100U /*!<Bit 0 */
+#define FMC_BTR2_DATAST_1 0x00000200U /*!<Bit 1 */
+#define FMC_BTR2_DATAST_2 0x00000400U /*!<Bit 2 */
+#define FMC_BTR2_DATAST_3 0x00000800U /*!<Bit 3 */
+#define FMC_BTR2_DATAST_4 0x00001000U /*!<Bit 4 */
+#define FMC_BTR2_DATAST_5 0x00002000U /*!<Bit 5 */
+#define FMC_BTR2_DATAST_6 0x00004000U /*!<Bit 6 */
+#define FMC_BTR2_DATAST_7 0x00008000U /*!<Bit 7 */
+
+#define FMC_BTR2_BUSTURN 0x000F0000U /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define FMC_BTR2_BUSTURN_0 0x00010000U /*!<Bit 0 */
+#define FMC_BTR2_BUSTURN_1 0x00020000U /*!<Bit 1 */
+#define FMC_BTR2_BUSTURN_2 0x00040000U /*!<Bit 2 */
+#define FMC_BTR2_BUSTURN_3 0x00080000U /*!<Bit 3 */
+
+#define FMC_BTR2_CLKDIV 0x00F00000U /*!<CLKDIV[3:0] bits (Clock divide ratio) */
+#define FMC_BTR2_CLKDIV_0 0x00100000U /*!<Bit 0 */
+#define FMC_BTR2_CLKDIV_1 0x00200000U /*!<Bit 1 */
+#define FMC_BTR2_CLKDIV_2 0x00400000U /*!<Bit 2 */
+#define FMC_BTR2_CLKDIV_3 0x00800000U /*!<Bit 3 */
+
+#define FMC_BTR2_DATLAT 0x0F000000U /*!<DATLA[3:0] bits (Data latency) */
+#define FMC_BTR2_DATLAT_0 0x01000000U /*!<Bit 0 */
+#define FMC_BTR2_DATLAT_1 0x02000000U /*!<Bit 1 */
+#define FMC_BTR2_DATLAT_2 0x04000000U /*!<Bit 2 */
+#define FMC_BTR2_DATLAT_3 0x08000000U /*!<Bit 3 */
+
+#define FMC_BTR2_ACCMOD 0x30000000U /*!<ACCMOD[1:0] bits (Access mode) */
+#define FMC_BTR2_ACCMOD_0 0x10000000U /*!<Bit 0 */
+#define FMC_BTR2_ACCMOD_1 0x20000000U /*!<Bit 1 */
+
+/******************* Bit definition for FMC_BTR3 register *******************/
+#define FMC_BTR3_ADDSET 0x0000000FU /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FMC_BTR3_ADDSET_0 0x00000001U /*!<Bit 0 */
+#define FMC_BTR3_ADDSET_1 0x00000002U /*!<Bit 1 */
+#define FMC_BTR3_ADDSET_2 0x00000004U /*!<Bit 2 */
+#define FMC_BTR3_ADDSET_3 0x00000008U /*!<Bit 3 */
+
+#define FMC_BTR3_ADDHLD 0x000000F0U /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FMC_BTR3_ADDHLD_0 0x00000010U /*!<Bit 0 */
+#define FMC_BTR3_ADDHLD_1 0x00000020U /*!<Bit 1 */
+#define FMC_BTR3_ADDHLD_2 0x00000040U /*!<Bit 2 */
+#define FMC_BTR3_ADDHLD_3 0x00000080U /*!<Bit 3 */
+
+#define FMC_BTR3_DATAST 0x0000FF00U /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FMC_BTR3_DATAST_0 0x00000100U /*!<Bit 0 */
+#define FMC_BTR3_DATAST_1 0x00000200U /*!<Bit 1 */
+#define FMC_BTR3_DATAST_2 0x00000400U /*!<Bit 2 */
+#define FMC_BTR3_DATAST_3 0x00000800U /*!<Bit 3 */
+#define FMC_BTR3_DATAST_4 0x00001000U /*!<Bit 4 */
+#define FMC_BTR3_DATAST_5 0x00002000U /*!<Bit 5 */
+#define FMC_BTR3_DATAST_6 0x00004000U /*!<Bit 6 */
+#define FMC_BTR3_DATAST_7 0x00008000U /*!<Bit 7 */
+
+#define FMC_BTR3_BUSTURN 0x000F0000U /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define FMC_BTR3_BUSTURN_0 0x00010000U /*!<Bit 0 */
+#define FMC_BTR3_BUSTURN_1 0x00020000U /*!<Bit 1 */
+#define FMC_BTR3_BUSTURN_2 0x00040000U /*!<Bit 2 */
+#define FMC_BTR3_BUSTURN_3 0x00080000U /*!<Bit 3 */
+
+#define FMC_BTR3_CLKDIV 0x00F00000U /*!<CLKDIV[3:0] bits (Clock divide ratio) */
+#define FMC_BTR3_CLKDIV_0 0x00100000U /*!<Bit 0 */
+#define FMC_BTR3_CLKDIV_1 0x00200000U /*!<Bit 1 */
+#define FMC_BTR3_CLKDIV_2 0x00400000U /*!<Bit 2 */
+#define FMC_BTR3_CLKDIV_3 0x00800000U /*!<Bit 3 */
+
+#define FMC_BTR3_DATLAT 0x0F000000U /*!<DATLA[3:0] bits (Data latency) */
+#define FMC_BTR3_DATLAT_0 0x01000000U /*!<Bit 0 */
+#define FMC_BTR3_DATLAT_1 0x02000000U /*!<Bit 1 */
+#define FMC_BTR3_DATLAT_2 0x04000000U /*!<Bit 2 */
+#define FMC_BTR3_DATLAT_3 0x08000000U /*!<Bit 3 */
+
+#define FMC_BTR3_ACCMOD 0x30000000U /*!<ACCMOD[1:0] bits (Access mode) */
+#define FMC_BTR3_ACCMOD_0 0x10000000U /*!<Bit 0 */
+#define FMC_BTR3_ACCMOD_1 0x20000000U /*!<Bit 1 */
+
+/****************** Bit definition for FMC_BTR4 register *******************/
+#define FMC_BTR4_ADDSET 0x0000000FU /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FMC_BTR4_ADDSET_0 0x00000001U /*!<Bit 0 */
+#define FMC_BTR4_ADDSET_1 0x00000002U /*!<Bit 1 */
+#define FMC_BTR4_ADDSET_2 0x00000004U /*!<Bit 2 */
+#define FMC_BTR4_ADDSET_3 0x00000008U /*!<Bit 3 */
+
+#define FMC_BTR4_ADDHLD 0x000000F0U /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FMC_BTR4_ADDHLD_0 0x00000010U /*!<Bit 0 */
+#define FMC_BTR4_ADDHLD_1 0x00000020U /*!<Bit 1 */
+#define FMC_BTR4_ADDHLD_2 0x00000040U /*!<Bit 2 */
+#define FMC_BTR4_ADDHLD_3 0x00000080U /*!<Bit 3 */
+
+#define FMC_BTR4_DATAST 0x0000FF00U /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FMC_BTR4_DATAST_0 0x00000100U /*!<Bit 0 */
+#define FMC_BTR4_DATAST_1 0x00000200U /*!<Bit 1 */
+#define FMC_BTR4_DATAST_2 0x00000400U /*!<Bit 2 */
+#define FMC_BTR4_DATAST_3 0x00000800U /*!<Bit 3 */
+#define FMC_BTR4_DATAST_4 0x00001000U /*!<Bit 4 */
+#define FMC_BTR4_DATAST_5 0x00002000U /*!<Bit 5 */
+#define FMC_BTR4_DATAST_6 0x00004000U /*!<Bit 6 */
+#define FMC_BTR4_DATAST_7 0x00008000U /*!<Bit 7 */
+
+#define FMC_BTR4_BUSTURN 0x000F0000U /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define FMC_BTR4_BUSTURN_0 0x00010000U /*!<Bit 0 */
+#define FMC_BTR4_BUSTURN_1 0x00020000U /*!<Bit 1 */
+#define FMC_BTR4_BUSTURN_2 0x00040000U /*!<Bit 2 */
+#define FMC_BTR4_BUSTURN_3 0x00080000U /*!<Bit 3 */
+
+#define FMC_BTR4_CLKDIV 0x00F00000U /*!<CLKDIV[3:0] bits (Clock divide ratio) */
+#define FMC_BTR4_CLKDIV_0 0x00100000U /*!<Bit 0 */
+#define FMC_BTR4_CLKDIV_1 0x00200000U /*!<Bit 1 */
+#define FMC_BTR4_CLKDIV_2 0x00400000U /*!<Bit 2 */
+#define FMC_BTR4_CLKDIV_3 0x00800000U /*!<Bit 3 */
+
+#define FMC_BTR4_DATLAT 0x0F000000U /*!<DATLA[3:0] bits (Data latency) */
+#define FMC_BTR4_DATLAT_0 0x01000000U /*!<Bit 0 */
+#define FMC_BTR4_DATLAT_1 0x02000000U /*!<Bit 1 */
+#define FMC_BTR4_DATLAT_2 0x04000000U /*!<Bit 2 */
+#define FMC_BTR4_DATLAT_3 0x08000000U /*!<Bit 3 */
+
+#define FMC_BTR4_ACCMOD 0x30000000U /*!<ACCMOD[1:0] bits (Access mode) */
+#define FMC_BTR4_ACCMOD_0 0x10000000U /*!<Bit 0 */
+#define FMC_BTR4_ACCMOD_1 0x20000000U /*!<Bit 1 */
+
+/****************** Bit definition for FMC_BWTR1 register ******************/
+#define FMC_BWTR1_ADDSET 0x0000000FU /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FMC_BWTR1_ADDSET_0 0x00000001U /*!<Bit 0 */
+#define FMC_BWTR1_ADDSET_1 0x00000002U /*!<Bit 1 */
+#define FMC_BWTR1_ADDSET_2 0x00000004U /*!<Bit 2 */
+#define FMC_BWTR1_ADDSET_3 0x00000008U /*!<Bit 3 */
+
+#define FMC_BWTR1_ADDHLD 0x000000F0U /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FMC_BWTR1_ADDHLD_0 0x00000010U /*!<Bit 0 */
+#define FMC_BWTR1_ADDHLD_1 0x00000020U /*!<Bit 1 */
+#define FMC_BWTR1_ADDHLD_2 0x00000040U /*!<Bit 2 */
+#define FMC_BWTR1_ADDHLD_3 0x00000080U /*!<Bit 3 */
+
+#define FMC_BWTR1_DATAST 0x0000FF00U /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FMC_BWTR1_DATAST_0 0x00000100U /*!<Bit 0 */
+#define FMC_BWTR1_DATAST_1 0x00000200U /*!<Bit 1 */
+#define FMC_BWTR1_DATAST_2 0x00000400U /*!<Bit 2 */
+#define FMC_BWTR1_DATAST_3 0x00000800U /*!<Bit 3 */
+#define FMC_BWTR1_DATAST_4 0x00001000U /*!<Bit 4 */
+#define FMC_BWTR1_DATAST_5 0x00002000U /*!<Bit 5 */
+#define FMC_BWTR1_DATAST_6 0x00004000U /*!<Bit 6 */
+#define FMC_BWTR1_DATAST_7 0x00008000U /*!<Bit 7 */
+
+#define FMC_BWTR1_BUSTURN 0x000F0000U /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
+#define FMC_BWTR1_BUSTURN_0 0x00010000U /*!<Bit 0 */
+#define FMC_BWTR1_BUSTURN_1 0x00020000U /*!<Bit 1 */
+#define FMC_BWTR1_BUSTURN_2 0x00040000U /*!<Bit 2 */
+#define FMC_BWTR1_BUSTURN_3 0x00080000U /*!<Bit 3 */
+
+#define FMC_BWTR1_ACCMOD 0x30000000U /*!<ACCMOD[1:0] bits (Access mode) */
+#define FMC_BWTR1_ACCMOD_0 0x10000000U /*!<Bit 0 */
+#define FMC_BWTR1_ACCMOD_1 0x20000000U /*!<Bit 1 */
+
+/****************** Bit definition for FMC_BWTR2 register ******************/
+#define FMC_BWTR2_ADDSET 0x0000000FU /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FMC_BWTR2_ADDSET_0 0x00000001U /*!<Bit 0 */
+#define FMC_BWTR2_ADDSET_1 0x00000002U /*!<Bit 1 */
+#define FMC_BWTR2_ADDSET_2 0x00000004U /*!<Bit 2 */
+#define FMC_BWTR2_ADDSET_3 0x00000008U /*!<Bit 3 */
+
+#define FMC_BWTR2_ADDHLD 0x000000F0U /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FMC_BWTR2_ADDHLD_0 0x00000010U /*!<Bit 0 */
+#define FMC_BWTR2_ADDHLD_1 0x00000020U /*!<Bit 1 */
+#define FMC_BWTR2_ADDHLD_2 0x00000040U /*!<Bit 2 */
+#define FMC_BWTR2_ADDHLD_3 0x00000080U /*!<Bit 3 */
+
+#define FMC_BWTR2_DATAST 0x0000FF00U /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FMC_BWTR2_DATAST_0 0x00000100U /*!<Bit 0 */
+#define FMC_BWTR2_DATAST_1 0x00000200U /*!<Bit 1 */
+#define FMC_BWTR2_DATAST_2 0x00000400U /*!<Bit 2 */
+#define FMC_BWTR2_DATAST_3 0x00000800U /*!<Bit 3 */
+#define FMC_BWTR2_DATAST_4 0x00001000U /*!<Bit 4 */
+#define FMC_BWTR2_DATAST_5 0x00002000U /*!<Bit 5 */
+#define FMC_BWTR2_DATAST_6 0x00004000U /*!<Bit 6 */
+#define FMC_BWTR2_DATAST_7 0x00008000U /*!<Bit 7 */
+
+#define FMC_BWTR2_BUSTURN 0x000F0000U /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
+#define FMC_BWTR2_BUSTURN_0 0x00010000U /*!<Bit 0 */
+#define FMC_BWTR2_BUSTURN_1 0x00020000U /*!<Bit 1 */
+#define FMC_BWTR2_BUSTURN_2 0x00040000U /*!<Bit 2 */
+#define FMC_BWTR2_BUSTURN_3 0x00080000U /*!<Bit 3 */
+
+#define FMC_BWTR2_ACCMOD 0x30000000U /*!<ACCMOD[1:0] bits (Access mode) */
+#define FMC_BWTR2_ACCMOD_0 0x10000000U /*!<Bit 0 */
+#define FMC_BWTR2_ACCMOD_1 0x20000000U /*!<Bit 1 */
+
+/****************** Bit definition for FMC_BWTR3 register ******************/
+#define FMC_BWTR3_ADDSET 0x0000000FU /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FMC_BWTR3_ADDSET_0 0x00000001U /*!<Bit 0 */
+#define FMC_BWTR3_ADDSET_1 0x00000002U /*!<Bit 1 */
+#define FMC_BWTR3_ADDSET_2 0x00000004U /*!<Bit 2 */
+#define FMC_BWTR3_ADDSET_3 0x00000008U /*!<Bit 3 */
+
+#define FMC_BWTR3_ADDHLD 0x000000F0U /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FMC_BWTR3_ADDHLD_0 0x00000010U /*!<Bit 0 */
+#define FMC_BWTR3_ADDHLD_1 0x00000020U /*!<Bit 1 */
+#define FMC_BWTR3_ADDHLD_2 0x00000040U /*!<Bit 2 */
+#define FMC_BWTR3_ADDHLD_3 0x00000080U /*!<Bit 3 */
+
+#define FMC_BWTR3_DATAST 0x0000FF00U /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FMC_BWTR3_DATAST_0 0x00000100U /*!<Bit 0 */
+#define FMC_BWTR3_DATAST_1 0x00000200U /*!<Bit 1 */
+#define FMC_BWTR3_DATAST_2 0x00000400U /*!<Bit 2 */
+#define FMC_BWTR3_DATAST_3 0x00000800U /*!<Bit 3 */
+#define FMC_BWTR3_DATAST_4 0x00001000U /*!<Bit 4 */
+#define FMC_BWTR3_DATAST_5 0x00002000U /*!<Bit 5 */
+#define FMC_BWTR3_DATAST_6 0x00004000U /*!<Bit 6 */
+#define FMC_BWTR3_DATAST_7 0x00008000U /*!<Bit 7 */
+
+#define FMC_BWTR3_BUSTURN 0x000F0000U /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
+#define FMC_BWTR3_BUSTURN_0 0x00010000U /*!<Bit 0 */
+#define FMC_BWTR3_BUSTURN_1 0x00020000U /*!<Bit 1 */
+#define FMC_BWTR3_BUSTURN_2 0x00040000U /*!<Bit 2 */
+#define FMC_BWTR3_BUSTURN_3 0x00080000U /*!<Bit 3 */
+
+#define FMC_BWTR3_ACCMOD 0x30000000U /*!<ACCMOD[1:0] bits (Access mode) */
+#define FMC_BWTR3_ACCMOD_0 0x10000000U /*!<Bit 0 */
+#define FMC_BWTR3_ACCMOD_1 0x20000000U /*!<Bit 1 */
+
+/****************** Bit definition for FMC_BWTR4 register ******************/
+#define FMC_BWTR4_ADDSET 0x0000000FU /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FMC_BWTR4_ADDSET_0 0x00000001U /*!<Bit 0 */
+#define FMC_BWTR4_ADDSET_1 0x00000002U /*!<Bit 1 */
+#define FMC_BWTR4_ADDSET_2 0x00000004U /*!<Bit 2 */
+#define FMC_BWTR4_ADDSET_3 0x00000008U /*!<Bit 3 */
+
+#define FMC_BWTR4_ADDHLD 0x000000F0U /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FMC_BWTR4_ADDHLD_0 0x00000010U /*!<Bit 0 */
+#define FMC_BWTR4_ADDHLD_1 0x00000020U /*!<Bit 1 */
+#define FMC_BWTR4_ADDHLD_2 0x00000040U /*!<Bit 2 */
+#define FMC_BWTR4_ADDHLD_3 0x00000080U /*!<Bit 3 */
+
+#define FMC_BWTR4_DATAST 0x0000FF00U /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FMC_BWTR4_DATAST_0 0x00000100U /*!<Bit 0 */
+#define FMC_BWTR4_DATAST_1 0x00000200U /*!<Bit 1 */
+#define FMC_BWTR4_DATAST_2 0x00000400U /*!<Bit 2 */
+#define FMC_BWTR4_DATAST_3 0x00000800U /*!<Bit 3 */
+#define FMC_BWTR4_DATAST_4 0x00001000U /*!<Bit 4 */
+#define FMC_BWTR4_DATAST_5 0x00002000U /*!<Bit 5 */
+#define FMC_BWTR4_DATAST_6 0x00004000U /*!<Bit 6 */
+#define FMC_BWTR4_DATAST_7 0x00008000U /*!<Bit 7 */
+
+#define FMC_BWTR4_BUSTURN 0x000F0000U /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
+#define FMC_BWTR4_BUSTURN_0 0x00010000U /*!<Bit 0 */
+#define FMC_BWTR4_BUSTURN_1 0x00020000U /*!<Bit 1 */
+#define FMC_BWTR4_BUSTURN_2 0x00040000U /*!<Bit 2 */
+#define FMC_BWTR4_BUSTURN_3 0x00080000U /*!<Bit 3 */
+
+#define FMC_BWTR4_ACCMOD 0x30000000U /*!<ACCMOD[1:0] bits (Access mode) */
+#define FMC_BWTR4_ACCMOD_0 0x10000000U /*!<Bit 0 */
+#define FMC_BWTR4_ACCMOD_1 0x20000000U /*!<Bit 1 */
+
+/****************** Bit definition for FMC_PCR register *******************/
+#define FMC_PCR_PWAITEN 0x00000002U /*!<Wait feature enable bit */
+#define FMC_PCR_PBKEN 0x00000004U /*!<PC Card/NAND Flash memory bank enable bit */
+#define FMC_PCR_PTYP 0x00000008U /*!<Memory type */
+
+#define FMC_PCR_PWID 0x00000030U /*!<PWID[1:0] bits (NAND Flash databus width) */
+#define FMC_PCR_PWID_0 0x00000010U /*!<Bit 0 */
+#define FMC_PCR_PWID_1 0x00000020U /*!<Bit 1 */
+
+#define FMC_PCR_ECCEN 0x00000040U /*!<ECC computation logic enable bit */
+
+#define FMC_PCR_TCLR 0x00001E00U /*!<TCLR[3:0] bits (CLE to RE delay) */
+#define FMC_PCR_TCLR_0 0x00000200U /*!<Bit 0 */
+#define FMC_PCR_TCLR_1 0x00000400U /*!<Bit 1 */
+#define FMC_PCR_TCLR_2 0x00000800U /*!<Bit 2 */
+#define FMC_PCR_TCLR_3 0x00001000U /*!<Bit 3 */
+
+#define FMC_PCR_TAR 0x0001E000U /*!<TAR[3:0] bits (ALE to RE delay) */
+#define FMC_PCR_TAR_0 0x00002000U /*!<Bit 0 */
+#define FMC_PCR_TAR_1 0x00004000U /*!<Bit 1 */
+#define FMC_PCR_TAR_2 0x00008000U /*!<Bit 2 */
+#define FMC_PCR_TAR_3 0x00010000U /*!<Bit 3 */
+
+#define FMC_PCR_ECCPS 0x000E0000U /*!<ECCPS[1:0] bits (ECC page size) */
+#define FMC_PCR_ECCPS_0 0x00020000U /*!<Bit 0 */
+#define FMC_PCR_ECCPS_1 0x00040000U /*!<Bit 1 */
+#define FMC_PCR_ECCPS_2 0x00080000U /*!<Bit 2 */
+
+/******************* Bit definition for FMC_SR register *******************/
+#define FMC_SR_IRS 0x01U /*!<Interrupt Rising Edge status */
+#define FMC_SR_ILS 0x02U /*!<Interrupt Level status */
+#define FMC_SR_IFS 0x04U /*!<Interrupt Falling Edge status */
+#define FMC_SR_IREN 0x08U /*!<Interrupt Rising Edge detection Enable bit */
+#define FMC_SR_ILEN 0x10U /*!<Interrupt Level detection Enable bit */
+#define FMC_SR_IFEN 0x20U /*!<Interrupt Falling Edge detection Enable bit */
+#define FMC_SR_FEMPT 0x40U /*!<FIFO empty */
+
+/****************** Bit definition for FMC_PMEM register ******************/
+#define FMC_PMEM_MEMSET2 0x000000FFU /*!<MEMSET2[7:0] bits (Common memory 2 setup time) */
+#define FMC_PMEM_MEMSET2_0 0x00000001U /*!<Bit 0 */
+#define FMC_PMEM_MEMSET2_1 0x00000002U /*!<Bit 1 */
+#define FMC_PMEM_MEMSET2_2 0x00000004U /*!<Bit 2 */
+#define FMC_PMEM_MEMSET2_3 0x00000008U /*!<Bit 3 */
+#define FMC_PMEM_MEMSET2_4 0x00000010U /*!<Bit 4 */
+#define FMC_PMEM_MEMSET2_5 0x00000020U /*!<Bit 5 */
+#define FMC_PMEM_MEMSET2_6 0x00000040U /*!<Bit 6 */
+#define FMC_PMEM_MEMSET2_7 0x00000080U /*!<Bit 7 */
+
+#define FMC_PMEM_MEMWAIT2 0x0000FF00U /*!<MEMWAIT2[7:0] bits (Common memory 2 wait time) */
+#define FMC_PMEM_MEMWAIT2_0 0x00000100U /*!<Bit 0 */
+#define FMC_PMEM_MEMWAIT2_1 0x00000200U /*!<Bit 1 */
+#define FMC_PMEM_MEMWAIT2_2 0x00000400U /*!<Bit 2 */
+#define FMC_PMEM_MEMWAIT2_3 0x00000800U /*!<Bit 3 */
+#define FMC_PMEM_MEMWAIT2_4 0x00001000U /*!<Bit 4 */
+#define FMC_PMEM_MEMWAIT2_5 0x00002000U /*!<Bit 5 */
+#define FMC_PMEM_MEMWAIT2_6 0x00004000U /*!<Bit 6 */
+#define FMC_PMEM_MEMWAIT2_7 0x00008000U /*!<Bit 7 */
+
+#define FMC_PMEM_MEMHOLD2 0x00FF0000U /*!<MEMHOLD2[7:0] bits (Common memory 2 hold time) */
+#define FMC_PMEM_MEMHOLD2_0 0x00010000U /*!<Bit 0 */
+#define FMC_PMEM_MEMHOLD2_1 0x00020000U /*!<Bit 1 */
+#define FMC_PMEM_MEMHOLD2_2 0x00040000U /*!<Bit 2 */
+#define FMC_PMEM_MEMHOLD2_3 0x00080000U /*!<Bit 3 */
+#define FMC_PMEM_MEMHOLD2_4 0x00100000U /*!<Bit 4 */
+#define FMC_PMEM_MEMHOLD2_5 0x00200000U /*!<Bit 5 */
+#define FMC_PMEM_MEMHOLD2_6 0x00400000U /*!<Bit 6 */
+#define FMC_PMEM_MEMHOLD2_7 0x00800000U /*!<Bit 7 */
+
+#define FMC_PMEM_MEMHIZ2 0xFF000000U /*!<MEMHIZ2[7:0] bits (Common memory 2 databus HiZ time) */
+#define FMC_PMEM_MEMHIZ2_0 0x01000000U /*!<Bit 0 */
+#define FMC_PMEM_MEMHIZ2_1 0x02000000U /*!<Bit 1 */
+#define FMC_PMEM_MEMHIZ2_2 0x04000000U /*!<Bit 2 */
+#define FMC_PMEM_MEMHIZ2_3 0x08000000U /*!<Bit 3 */
+#define FMC_PMEM_MEMHIZ2_4 0x10000000U /*!<Bit 4 */
+#define FMC_PMEM_MEMHIZ2_5 0x20000000U /*!<Bit 5 */
+#define FMC_PMEM_MEMHIZ2_6 0x40000000U /*!<Bit 6 */
+#define FMC_PMEM_MEMHIZ2_7 0x80000000U /*!<Bit 7 */
+
+/****************** Bit definition for FMC_PATT register ******************/
+#define FMC_PATT_ATTSET2 0x000000FFU /*!<ATTSET2[7:0] bits (Attribute memory 2 setup time) */
+#define FMC_PATT_ATTSET2_0 0x00000001U /*!<Bit 0 */
+#define FMC_PATT_ATTSET2_1 0x00000002U /*!<Bit 1 */
+#define FMC_PATT_ATTSET2_2 0x00000004U /*!<Bit 2 */
+#define FMC_PATT_ATTSET2_3 0x00000008U /*!<Bit 3 */
+#define FMC_PATT_ATTSET2_4 0x00000010U /*!<Bit 4 */
+#define FMC_PATT_ATTSET2_5 0x00000020U /*!<Bit 5 */
+#define FMC_PATT_ATTSET2_6 0x00000040U /*!<Bit 6 */
+#define FMC_PATT_ATTSET2_7 0x00000080U /*!<Bit 7 */
+
+#define FMC_PATT_ATTWAIT2 0x0000FF00U /*!<ATTWAIT2[7:0] bits (Attribute memory 2 wait time) */
+#define FMC_PATT_ATTWAIT2_0 0x00000100U /*!<Bit 0 */
+#define FMC_PATT_ATTWAIT2_1 0x00000200U /*!<Bit 1 */
+#define FMC_PATT_ATTWAIT2_2 0x00000400U /*!<Bit 2 */
+#define FMC_PATT_ATTWAIT2_3 0x00000800U /*!<Bit 3 */
+#define FMC_PATT_ATTWAIT2_4 0x00001000U /*!<Bit 4 */
+#define FMC_PATT_ATTWAIT2_5 0x00002000U /*!<Bit 5 */
+#define FMC_PATT_ATTWAIT2_6 0x00004000U /*!<Bit 6 */
+#define FMC_PATT_ATTWAIT2_7 0x00008000U /*!<Bit 7 */
+
+#define FMC_PATT_ATTHOLD2 0x00FF0000U /*!<ATTHOLD2[7:0] bits (Attribute memory 2 hold time) */
+#define FMC_PATT_ATTHOLD2_0 0x00010000U /*!<Bit 0 */
+#define FMC_PATT_ATTHOLD2_1 0x00020000U /*!<Bit 1 */
+#define FMC_PATT_ATTHOLD2_2 0x00040000U /*!<Bit 2 */
+#define FMC_PATT_ATTHOLD2_3 0x00080000U /*!<Bit 3 */
+#define FMC_PATT_ATTHOLD2_4 0x00100000U /*!<Bit 4 */
+#define FMC_PATT_ATTHOLD2_5 0x00200000U /*!<Bit 5 */
+#define FMC_PATT_ATTHOLD2_6 0x00400000U /*!<Bit 6 */
+#define FMC_PATT_ATTHOLD2_7 0x00800000U /*!<Bit 7 */
+
+#define FMC_PATT_ATTHIZ2 0xFF000000U /*!<ATTHIZ2[7:0] bits (Attribute memory 2 databus HiZ time) */
+#define FMC_PATT_ATTHIZ2_0 0x01000000U /*!<Bit 0 */
+#define FMC_PATT_ATTHIZ2_1 0x02000000U /*!<Bit 1 */
+#define FMC_PATT_ATTHIZ2_2 0x04000000U /*!<Bit 2 */
+#define FMC_PATT_ATTHIZ2_3 0x08000000U /*!<Bit 3 */
+#define FMC_PATT_ATTHIZ2_4 0x10000000U /*!<Bit 4 */
+#define FMC_PATT_ATTHIZ2_5 0x20000000U /*!<Bit 5 */
+#define FMC_PATT_ATTHIZ2_6 0x40000000U /*!<Bit 6 */
+#define FMC_PATT_ATTHIZ2_7 0x80000000U /*!<Bit 7 */
+
+/****************** Bit definition for FMC_ECCR register ******************/
+#define FMC_ECCR_ECC2 0xFFFFFFFFU /*!<ECC result */
+
+/****************** Bit definition for FMC_SDCR1 register ******************/
+#define FMC_SDCR1_NC 0x00000003U /*!<NC[1:0] bits (Number of column bits) */
+#define FMC_SDCR1_NC_0 0x00000001U /*!<Bit 0 */
+#define FMC_SDCR1_NC_1 0x00000002U /*!<Bit 1 */
+
+#define FMC_SDCR1_NR 0x0000000CU /*!<NR[1:0] bits (Number of row bits) */
+#define FMC_SDCR1_NR_0 0x00000004U /*!<Bit 0 */
+#define FMC_SDCR1_NR_1 0x00000008U /*!<Bit 1 */
+
+#define FMC_SDCR1_MWID 0x00000030U /*!<NR[1:0] bits (Number of row bits) */
+#define FMC_SDCR1_MWID_0 0x00000010U /*!<Bit 0 */
+#define FMC_SDCR1_MWID_1 0x00000020U /*!<Bit 1 */
+
+#define FMC_SDCR1_NB 0x00000040U /*!<Number of internal bank */
+
+#define FMC_SDCR1_CAS 0x00000180U /*!<CAS[1:0] bits (CAS latency) */
+#define FMC_SDCR1_CAS_0 0x00000080U /*!<Bit 0 */
+#define FMC_SDCR1_CAS_1 0x00000100U /*!<Bit 1 */
+
+#define FMC_SDCR1_WP 0x00000200U /*!<Write protection */
+
+#define FMC_SDCR1_SDCLK 0x00000C00U /*!<SDRAM clock configuration */
+#define FMC_SDCR1_SDCLK_0 0x00000400U /*!<Bit 0 */
+#define FMC_SDCR1_SDCLK_1 0x00000800U /*!<Bit 1 */
+
+#define FMC_SDCR1_RBURST 0x00001000U /*!<Read burst */
+
+#define FMC_SDCR1_RPIPE 0x00006000U /*!<Write protection */
+#define FMC_SDCR1_RPIPE_0 0x00002000U /*!<Bit 0 */
+#define FMC_SDCR1_RPIPE_1 0x00004000U /*!<Bit 1 */
+
+/****************** Bit definition for FMC_SDCR2 register ******************/
+#define FMC_SDCR2_NC 0x00000003U /*!<NC[1:0] bits (Number of column bits) */
+#define FMC_SDCR2_NC_0 0x00000001U /*!<Bit 0 */
+#define FMC_SDCR2_NC_1 0x00000002U /*!<Bit 1 */
+
+#define FMC_SDCR2_NR 0x0000000CU /*!<NR[1:0] bits (Number of row bits) */
+#define FMC_SDCR2_NR_0 0x00000004U /*!<Bit 0 */
+#define FMC_SDCR2_NR_1 0x00000008U /*!<Bit 1 */
+
+#define FMC_SDCR2_MWID 0x00000030U /*!<NR[1:0] bits (Number of row bits) */
+#define FMC_SDCR2_MWID_0 0x00000010U /*!<Bit 0 */
+#define FMC_SDCR2_MWID_1 0x00000020U /*!<Bit 1 */
+
+#define FMC_SDCR2_NB 0x00000040U /*!<Number of internal bank */
+
+#define FMC_SDCR2_CAS 0x00000180U /*!<CAS[1:0] bits (CAS latency) */
+#define FMC_SDCR2_CAS_0 0x00000080U /*!<Bit 0 */
+#define FMC_SDCR2_CAS_1 0x00000100U /*!<Bit 1 */
+
+#define FMC_SDCR2_WP 0x00000200U /*!<Write protection */
+
+#define FMC_SDCR2_SDCLK 0x00000C00U /*!<SDCLK[1:0] (SDRAM clock configuration) */
+#define FMC_SDCR2_SDCLK_0 0x00000400U /*!<Bit 0 */
+#define FMC_SDCR2_SDCLK_1 0x00000800U /*!<Bit 1 */
+
+#define FMC_SDCR2_RBURST 0x00001000U /*!<Read burst */
+
+#define FMC_SDCR2_RPIPE 0x00006000U /*!<RPIPE[1:0](Read pipe) */
+#define FMC_SDCR2_RPIPE_0 0x00002000U /*!<Bit 0 */
+#define FMC_SDCR2_RPIPE_1 0x00004000U /*!<Bit 1 */
+
+/****************** Bit definition for FMC_SDTR1 register ******************/
+#define FMC_SDTR1_TMRD 0x0000000FU /*!<TMRD[3:0] bits (Load mode register to active) */
+#define FMC_SDTR1_TMRD_0 0x00000001U /*!<Bit 0 */
+#define FMC_SDTR1_TMRD_1 0x00000002U /*!<Bit 1 */
+#define FMC_SDTR1_TMRD_2 0x00000004U /*!<Bit 2 */
+#define FMC_SDTR1_TMRD_3 0x00000008U /*!<Bit 3 */
+
+#define FMC_SDTR1_TXSR 0x000000F0U /*!<TXSR[3:0] bits (Exit self refresh) */
+#define FMC_SDTR1_TXSR_0 0x00000010U /*!<Bit 0 */
+#define FMC_SDTR1_TXSR_1 0x00000020U /*!<Bit 1 */
+#define FMC_SDTR1_TXSR_2 0x00000040U /*!<Bit 2 */
+#define FMC_SDTR1_TXSR_3 0x00000080U /*!<Bit 3 */
+
+#define FMC_SDTR1_TRAS 0x00000F00U /*!<TRAS[3:0] bits (Self refresh time) */
+#define FMC_SDTR1_TRAS_0 0x00000100U /*!<Bit 0 */
+#define FMC_SDTR1_TRAS_1 0x00000200U /*!<Bit 1 */
+#define FMC_SDTR1_TRAS_2 0x00000400U /*!<Bit 2 */
+#define FMC_SDTR1_TRAS_3 0x00000800U /*!<Bit 3 */
+
+#define FMC_SDTR1_TRC 0x0000F000U /*!<TRC[2:0] bits (Row cycle delay) */
+#define FMC_SDTR1_TRC_0 0x00001000U /*!<Bit 0 */
+#define FMC_SDTR1_TRC_1 0x00002000U /*!<Bit 1 */
+#define FMC_SDTR1_TRC_2 0x00004000U /*!<Bit 2 */
+
+#define FMC_SDTR1_TWR 0x000F0000U /*!<TRC[2:0] bits (Write recovery delay) */
+#define FMC_SDTR1_TWR_0 0x00010000U /*!<Bit 0 */
+#define FMC_SDTR1_TWR_1 0x00020000U /*!<Bit 1 */
+#define FMC_SDTR1_TWR_2 0x00040000U /*!<Bit 2 */
+
+#define FMC_SDTR1_TRP 0x00F00000U /*!<TRP[2:0] bits (Row precharge delay) */
+#define FMC_SDTR1_TRP_0 0x00100000U /*!<Bit 0 */
+#define FMC_SDTR1_TRP_1 0x00200000U /*!<Bit 1 */
+#define FMC_SDTR1_TRP_2 0x00400000U /*!<Bit 2 */
+
+#define FMC_SDTR1_TRCD 0x0F000000U /*!<TRP[2:0] bits (Row to column delay) */
+#define FMC_SDTR1_TRCD_0 0x01000000U /*!<Bit 0 */
+#define FMC_SDTR1_TRCD_1 0x02000000U /*!<Bit 1 */
+#define FMC_SDTR1_TRCD_2 0x04000000U /*!<Bit 2 */
+
+/****************** Bit definition for FMC_SDTR2 register ******************/
+#define FMC_SDTR2_TMRD 0x0000000FU /*!<TMRD[3:0] bits (Load mode register to active) */
+#define FMC_SDTR2_TMRD_0 0x00000001U /*!<Bit 0 */
+#define FMC_SDTR2_TMRD_1 0x00000002U /*!<Bit 1 */
+#define FMC_SDTR2_TMRD_2 0x00000004U /*!<Bit 2 */
+#define FMC_SDTR2_TMRD_3 0x00000008U /*!<Bit 3 */
+
+#define FMC_SDTR2_TXSR 0x000000F0U /*!<TXSR[3:0] bits (Exit self refresh) */
+#define FMC_SDTR2_TXSR_0 0x00000010U /*!<Bit 0 */
+#define FMC_SDTR2_TXSR_1 0x00000020U /*!<Bit 1 */
+#define FMC_SDTR2_TXSR_2 0x00000040U /*!<Bit 2 */
+#define FMC_SDTR2_TXSR_3 0x00000080U /*!<Bit 3 */
+
+#define FMC_SDTR2_TRAS 0x00000F00U /*!<TRAS[3:0] bits (Self refresh time) */
+#define FMC_SDTR2_TRAS_0 0x00000100U /*!<Bit 0 */
+#define FMC_SDTR2_TRAS_1 0x00000200U /*!<Bit 1 */
+#define FMC_SDTR2_TRAS_2 0x00000400U /*!<Bit 2 */
+#define FMC_SDTR2_TRAS_3 0x00000800U /*!<Bit 3 */
+
+#define FMC_SDTR2_TRC 0x0000F000U /*!<TRC[2:0] bits (Row cycle delay) */
+#define FMC_SDTR2_TRC_0 0x00001000U /*!<Bit 0 */
+#define FMC_SDTR2_TRC_1 0x00002000U /*!<Bit 1 */
+#define FMC_SDTR2_TRC_2 0x00004000U /*!<Bit 2 */
+
+#define FMC_SDTR2_TWR 0x000F0000U /*!<TRC[2:0] bits (Write recovery delay) */
+#define FMC_SDTR2_TWR_0 0x00010000U /*!<Bit 0 */
+#define FMC_SDTR2_TWR_1 0x00020000U /*!<Bit 1 */
+#define FMC_SDTR2_TWR_2 0x00040000U /*!<Bit 2 */
+
+#define FMC_SDTR2_TRP 0x00F00000U /*!<TRP[2:0] bits (Row precharge delay) */
+#define FMC_SDTR2_TRP_0 0x00100000U /*!<Bit 0 */
+#define FMC_SDTR2_TRP_1 0x00200000U /*!<Bit 1 */
+#define FMC_SDTR2_TRP_2 0x00400000U /*!<Bit 2 */
+
+#define FMC_SDTR2_TRCD 0x0F000000U /*!<TRP[2:0] bits (Row to column delay) */
+#define FMC_SDTR2_TRCD_0 0x01000000U /*!<Bit 0 */
+#define FMC_SDTR2_TRCD_1 0x02000000U /*!<Bit 1 */
+#define FMC_SDTR2_TRCD_2 0x04000000U /*!<Bit 2 */
+
+/****************** Bit definition for FMC_SDCMR register ******************/
+#define FMC_SDCMR_MODE 0x00000007U /*!<MODE[2:0] bits (Command mode) */
+#define FMC_SDCMR_MODE_0 0x00000001U /*!<Bit 0 */
+#define FMC_SDCMR_MODE_1 0x00000002U /*!<Bit 1 */
+#define FMC_SDCMR_MODE_2 0x00000004U /*!<Bit 2 */
+
+#define FMC_SDCMR_CTB2 0x00000008U /*!<Command target 2 */
+
+#define FMC_SDCMR_CTB1 0x00000010U /*!<Command target 1 */
+
+#define FMC_SDCMR_NRFS 0x000001E0U /*!<NRFS[3:0] bits (Number of auto-refresh) */
+#define FMC_SDCMR_NRFS_0 0x00000020U /*!<Bit 0 */
+#define FMC_SDCMR_NRFS_1 0x00000040U /*!<Bit 1 */
+#define FMC_SDCMR_NRFS_2 0x00000080U /*!<Bit 2 */
+#define FMC_SDCMR_NRFS_3 0x00000100U /*!<Bit 3 */
+
+#define FMC_SDCMR_MRD 0x003FFE00U /*!<MRD[12:0] bits (Mode register definition) */
+
+/****************** Bit definition for FMC_SDRTR register ******************/
+#define FMC_SDRTR_CRE 0x00000001U /*!<Clear refresh error flag */
+
+#define FMC_SDRTR_COUNT 0x00003FFEU /*!<COUNT[12:0] bits (Refresh timer count) */
+
+#define FMC_SDRTR_REIE 0x00004000U /*!<RES interupt enable */
+
+/****************** Bit definition for FMC_SDSR register ******************/
+#define FMC_SDSR_RE 0x00000001U /*!<Refresh error flag */
+
+#define FMC_SDSR_MODES1 0x00000006U /*!<MODES1[1:0]bits (Status mode for bank 1) */
+#define FMC_SDSR_MODES1_0 0x00000002U /*!<Bit 0 */
+#define FMC_SDSR_MODES1_1 0x00000004U /*!<Bit 1 */
+
+#define FMC_SDSR_MODES2 0x00000018U /*!<MODES2[1:0]bits (Status mode for bank 2) */
+#define FMC_SDSR_MODES2_0 0x00000008U /*!<Bit 0 */
+#define FMC_SDSR_MODES2_1 0x00000010U /*!<Bit 1 */
+#define FMC_SDSR_BUSY 0x00000020U /*!<Busy status */
+
+/******************************************************************************/
+/* */
+/* General Purpose I/O */
+/* */
+/******************************************************************************/
+/****************** Bits definition for GPIO_MODER register *****************/
+#define GPIO_MODER_MODER0 0x00000003U
+#define GPIO_MODER_MODER0_0 0x00000001U
+#define GPIO_MODER_MODER0_1 0x00000002U
+
+#define GPIO_MODER_MODER1 0x0000000CU
+#define GPIO_MODER_MODER1_0 0x00000004U
+#define GPIO_MODER_MODER1_1 0x00000008U
+
+#define GPIO_MODER_MODER2 0x00000030U
+#define GPIO_MODER_MODER2_0 0x00000010U
+#define GPIO_MODER_MODER2_1 0x00000020U
+
+#define GPIO_MODER_MODER3 0x000000C0U
+#define GPIO_MODER_MODER3_0 0x00000040U
+#define GPIO_MODER_MODER3_1 0x00000080U
+
+#define GPIO_MODER_MODER4 0x00000300U
+#define GPIO_MODER_MODER4_0 0x00000100U
+#define GPIO_MODER_MODER4_1 0x00000200U
+
+#define GPIO_MODER_MODER5 0x00000C00U
+#define GPIO_MODER_MODER5_0 0x00000400U
+#define GPIO_MODER_MODER5_1 0x00000800U
+
+#define GPIO_MODER_MODER6 0x00003000U
+#define GPIO_MODER_MODER6_0 0x00001000U
+#define GPIO_MODER_MODER6_1 0x00002000U
+
+#define GPIO_MODER_MODER7 0x0000C000U
+#define GPIO_MODER_MODER7_0 0x00004000U
+#define GPIO_MODER_MODER7_1 0x00008000U
+
+#define GPIO_MODER_MODER8 0x00030000U
+#define GPIO_MODER_MODER8_0 0x00010000U
+#define GPIO_MODER_MODER8_1 0x00020000U
+
+#define GPIO_MODER_MODER9 0x000C0000U
+#define GPIO_MODER_MODER9_0 0x00040000U
+#define GPIO_MODER_MODER9_1 0x00080000U
+
+#define GPIO_MODER_MODER10 0x00300000U
+#define GPIO_MODER_MODER10_0 0x00100000U
+#define GPIO_MODER_MODER10_1 0x00200000U
+
+#define GPIO_MODER_MODER11 0x00C00000U
+#define GPIO_MODER_MODER11_0 0x00400000U
+#define GPIO_MODER_MODER11_1 0x00800000U
+
+#define GPIO_MODER_MODER12 0x03000000U
+#define GPIO_MODER_MODER12_0 0x01000000U
+#define GPIO_MODER_MODER12_1 0x02000000U
+
+#define GPIO_MODER_MODER13 0x0C000000U
+#define GPIO_MODER_MODER13_0 0x04000000U
+#define GPIO_MODER_MODER13_1 0x08000000U
+
+#define GPIO_MODER_MODER14 0x30000000U
+#define GPIO_MODER_MODER14_0 0x10000000U
+#define GPIO_MODER_MODER14_1 0x20000000U
+
+#define GPIO_MODER_MODER15 0xC0000000U
+#define GPIO_MODER_MODER15_0 0x40000000U
+#define GPIO_MODER_MODER15_1 0x80000000U
+
+/****************** Bits definition for GPIO_OTYPER register ****************/
+#define GPIO_OTYPER_OT_0 0x00000001U
+#define GPIO_OTYPER_OT_1 0x00000002U
+#define GPIO_OTYPER_OT_2 0x00000004U
+#define GPIO_OTYPER_OT_3 0x00000008U
+#define GPIO_OTYPER_OT_4 0x00000010U
+#define GPIO_OTYPER_OT_5 0x00000020U
+#define GPIO_OTYPER_OT_6 0x00000040U
+#define GPIO_OTYPER_OT_7 0x00000080U
+#define GPIO_OTYPER_OT_8 0x00000100U
+#define GPIO_OTYPER_OT_9 0x00000200U
+#define GPIO_OTYPER_OT_10 0x00000400U
+#define GPIO_OTYPER_OT_11 0x00000800U
+#define GPIO_OTYPER_OT_12 0x00001000U
+#define GPIO_OTYPER_OT_13 0x00002000U
+#define GPIO_OTYPER_OT_14 0x00004000U
+#define GPIO_OTYPER_OT_15 0x00008000U
+
+/****************** Bits definition for GPIO_OSPEEDR register ***************/
+#define GPIO_OSPEEDER_OSPEEDR0 0x00000003U
+#define GPIO_OSPEEDER_OSPEEDR0_0 0x00000001U
+#define GPIO_OSPEEDER_OSPEEDR0_1 0x00000002U
+
+#define GPIO_OSPEEDER_OSPEEDR1 0x0000000CU
+#define GPIO_OSPEEDER_OSPEEDR1_0 0x00000004U
+#define GPIO_OSPEEDER_OSPEEDR1_1 0x00000008U
+
+#define GPIO_OSPEEDER_OSPEEDR2 0x00000030U
+#define GPIO_OSPEEDER_OSPEEDR2_0 0x00000010U
+#define GPIO_OSPEEDER_OSPEEDR2_1 0x00000020U
+
+#define GPIO_OSPEEDER_OSPEEDR3 0x000000C0U
+#define GPIO_OSPEEDER_OSPEEDR3_0 0x00000040U
+#define GPIO_OSPEEDER_OSPEEDR3_1 0x00000080U
+
+#define GPIO_OSPEEDER_OSPEEDR4 0x00000300U
+#define GPIO_OSPEEDER_OSPEEDR4_0 0x00000100U
+#define GPIO_OSPEEDER_OSPEEDR4_1 0x00000200U
+
+#define GPIO_OSPEEDER_OSPEEDR5 0x00000C00U
+#define GPIO_OSPEEDER_OSPEEDR5_0 0x00000400U
+#define GPIO_OSPEEDER_OSPEEDR5_1 0x00000800U
+
+#define GPIO_OSPEEDER_OSPEEDR6 0x00003000U
+#define GPIO_OSPEEDER_OSPEEDR6_0 0x00001000U
+#define GPIO_OSPEEDER_OSPEEDR6_1 0x00002000U
+
+#define GPIO_OSPEEDER_OSPEEDR7 0x0000C000U
+#define GPIO_OSPEEDER_OSPEEDR7_0 0x00004000U
+#define GPIO_OSPEEDER_OSPEEDR7_1 0x00008000U
+
+#define GPIO_OSPEEDER_OSPEEDR8 0x00030000U
+#define GPIO_OSPEEDER_OSPEEDR8_0 0x00010000U
+#define GPIO_OSPEEDER_OSPEEDR8_1 0x00020000U
+
+#define GPIO_OSPEEDER_OSPEEDR9 0x000C0000U
+#define GPIO_OSPEEDER_OSPEEDR9_0 0x00040000U
+#define GPIO_OSPEEDER_OSPEEDR9_1 0x00080000U
+
+#define GPIO_OSPEEDER_OSPEEDR10 0x00300000U
+#define GPIO_OSPEEDER_OSPEEDR10_0 0x00100000U
+#define GPIO_OSPEEDER_OSPEEDR10_1 0x00200000U
+
+#define GPIO_OSPEEDER_OSPEEDR11 0x00C00000U
+#define GPIO_OSPEEDER_OSPEEDR11_0 0x00400000U
+#define GPIO_OSPEEDER_OSPEEDR11_1 0x00800000U
+
+#define GPIO_OSPEEDER_OSPEEDR12 0x03000000U
+#define GPIO_OSPEEDER_OSPEEDR12_0 0x01000000U
+#define GPIO_OSPEEDER_OSPEEDR12_1 0x02000000U
+
+#define GPIO_OSPEEDER_OSPEEDR13 0x0C000000U
+#define GPIO_OSPEEDER_OSPEEDR13_0 0x04000000U
+#define GPIO_OSPEEDER_OSPEEDR13_1 0x08000000U
+
+#define GPIO_OSPEEDER_OSPEEDR14 0x30000000U
+#define GPIO_OSPEEDER_OSPEEDR14_0 0x10000000U
+#define GPIO_OSPEEDER_OSPEEDR14_1 0x20000000U
+
+#define GPIO_OSPEEDER_OSPEEDR15 0xC0000000U
+#define GPIO_OSPEEDER_OSPEEDR15_0 0x40000000U
+#define GPIO_OSPEEDER_OSPEEDR15_1 0x80000000U
+
+/****************** Bits definition for GPIO_PUPDR register *****************/
+#define GPIO_PUPDR_PUPDR0 0x00000003U
+#define GPIO_PUPDR_PUPDR0_0 0x00000001U
+#define GPIO_PUPDR_PUPDR0_1 0x00000002U
+
+#define GPIO_PUPDR_PUPDR1 0x0000000CU
+#define GPIO_PUPDR_PUPDR1_0 0x00000004U
+#define GPIO_PUPDR_PUPDR1_1 0x00000008U
+
+#define GPIO_PUPDR_PUPDR2 0x00000030U
+#define GPIO_PUPDR_PUPDR2_0 0x00000010U
+#define GPIO_PUPDR_PUPDR2_1 0x00000020U
+
+#define GPIO_PUPDR_PUPDR3 0x000000C0U
+#define GPIO_PUPDR_PUPDR3_0 0x00000040U
+#define GPIO_PUPDR_PUPDR3_1 0x00000080U
+
+#define GPIO_PUPDR_PUPDR4 0x00000300U
+#define GPIO_PUPDR_PUPDR4_0 0x00000100U
+#define GPIO_PUPDR_PUPDR4_1 0x00000200U
+
+#define GPIO_PUPDR_PUPDR5 0x00000C00U
+#define GPIO_PUPDR_PUPDR5_0 0x00000400U
+#define GPIO_PUPDR_PUPDR5_1 0x00000800U
+
+#define GPIO_PUPDR_PUPDR6 0x00003000U
+#define GPIO_PUPDR_PUPDR6_0 0x00001000U
+#define GPIO_PUPDR_PUPDR6_1 0x00002000U
+
+#define GPIO_PUPDR_PUPDR7 0x0000C000U
+#define GPIO_PUPDR_PUPDR7_0 0x00004000U
+#define GPIO_PUPDR_PUPDR7_1 0x00008000U
+
+#define GPIO_PUPDR_PUPDR8 0x00030000U
+#define GPIO_PUPDR_PUPDR8_0 0x00010000U
+#define GPIO_PUPDR_PUPDR8_1 0x00020000U
+
+#define GPIO_PUPDR_PUPDR9 0x000C0000U
+#define GPIO_PUPDR_PUPDR9_0 0x00040000U
+#define GPIO_PUPDR_PUPDR9_1 0x00080000U
+
+#define GPIO_PUPDR_PUPDR10 0x00300000U
+#define GPIO_PUPDR_PUPDR10_0 0x00100000U
+#define GPIO_PUPDR_PUPDR10_1 0x00200000U
+
+#define GPIO_PUPDR_PUPDR11 0x00C00000U
+#define GPIO_PUPDR_PUPDR11_0 0x00400000U
+#define GPIO_PUPDR_PUPDR11_1 0x00800000U
+
+#define GPIO_PUPDR_PUPDR12 0x03000000U
+#define GPIO_PUPDR_PUPDR12_0 0x01000000U
+#define GPIO_PUPDR_PUPDR12_1 0x02000000U
+
+#define GPIO_PUPDR_PUPDR13 0x0C000000U
+#define GPIO_PUPDR_PUPDR13_0 0x04000000U
+#define GPIO_PUPDR_PUPDR13_1 0x08000000U
+
+#define GPIO_PUPDR_PUPDR14 0x30000000U
+#define GPIO_PUPDR_PUPDR14_0 0x10000000U
+#define GPIO_PUPDR_PUPDR14_1 0x20000000U
+
+#define GPIO_PUPDR_PUPDR15 0xC0000000U
+#define GPIO_PUPDR_PUPDR15_0 0x40000000U
+#define GPIO_PUPDR_PUPDR15_1 0x80000000U
+
+/****************** Bits definition for GPIO_IDR register *******************/
+#define GPIO_IDR_IDR_0 0x00000001U
+#define GPIO_IDR_IDR_1 0x00000002U
+#define GPIO_IDR_IDR_2 0x00000004U
+#define GPIO_IDR_IDR_3 0x00000008U
+#define GPIO_IDR_IDR_4 0x00000010U
+#define GPIO_IDR_IDR_5 0x00000020U
+#define GPIO_IDR_IDR_6 0x00000040U
+#define GPIO_IDR_IDR_7 0x00000080U
+#define GPIO_IDR_IDR_8 0x00000100U
+#define GPIO_IDR_IDR_9 0x00000200U
+#define GPIO_IDR_IDR_10 0x00000400U
+#define GPIO_IDR_IDR_11 0x00000800U
+#define GPIO_IDR_IDR_12 0x00001000U
+#define GPIO_IDR_IDR_13 0x00002000U
+#define GPIO_IDR_IDR_14 0x00004000U
+#define GPIO_IDR_IDR_15 0x00008000U
+/* Old GPIO_IDR register bits definition, maintained for legacy purpose */
+#define GPIO_OTYPER_IDR_0 GPIO_IDR_IDR_0
+#define GPIO_OTYPER_IDR_1 GPIO_IDR_IDR_1
+#define GPIO_OTYPER_IDR_2 GPIO_IDR_IDR_2
+#define GPIO_OTYPER_IDR_3 GPIO_IDR_IDR_3
+#define GPIO_OTYPER_IDR_4 GPIO_IDR_IDR_4
+#define GPIO_OTYPER_IDR_5 GPIO_IDR_IDR_5
+#define GPIO_OTYPER_IDR_6 GPIO_IDR_IDR_6
+#define GPIO_OTYPER_IDR_7 GPIO_IDR_IDR_7
+#define GPIO_OTYPER_IDR_8 GPIO_IDR_IDR_8
+#define GPIO_OTYPER_IDR_9 GPIO_IDR_IDR_9
+#define GPIO_OTYPER_IDR_10 GPIO_IDR_IDR_10
+#define GPIO_OTYPER_IDR_11 GPIO_IDR_IDR_11
+#define GPIO_OTYPER_IDR_12 GPIO_IDR_IDR_12
+#define GPIO_OTYPER_IDR_13 GPIO_IDR_IDR_13
+#define GPIO_OTYPER_IDR_14 GPIO_IDR_IDR_14
+#define GPIO_OTYPER_IDR_15 GPIO_IDR_IDR_15
+
+/****************** Bits definition for GPIO_ODR register *******************/
+#define GPIO_ODR_ODR_0 0x00000001U
+#define GPIO_ODR_ODR_1 0x00000002U
+#define GPIO_ODR_ODR_2 0x00000004U
+#define GPIO_ODR_ODR_3 0x00000008U
+#define GPIO_ODR_ODR_4 0x00000010U
+#define GPIO_ODR_ODR_5 0x00000020U
+#define GPIO_ODR_ODR_6 0x00000040U
+#define GPIO_ODR_ODR_7 0x00000080U
+#define GPIO_ODR_ODR_8 0x00000100U
+#define GPIO_ODR_ODR_9 0x00000200U
+#define GPIO_ODR_ODR_10 0x00000400U
+#define GPIO_ODR_ODR_11 0x00000800U
+#define GPIO_ODR_ODR_12 0x00001000U
+#define GPIO_ODR_ODR_13 0x00002000U
+#define GPIO_ODR_ODR_14 0x00004000U
+#define GPIO_ODR_ODR_15 0x00008000U
+/* Old GPIO_ODR register bits definition, maintained for legacy purpose */
+#define GPIO_OTYPER_ODR_0 GPIO_ODR_ODR_0
+#define GPIO_OTYPER_ODR_1 GPIO_ODR_ODR_1
+#define GPIO_OTYPER_ODR_2 GPIO_ODR_ODR_2
+#define GPIO_OTYPER_ODR_3 GPIO_ODR_ODR_3
+#define GPIO_OTYPER_ODR_4 GPIO_ODR_ODR_4
+#define GPIO_OTYPER_ODR_5 GPIO_ODR_ODR_5
+#define GPIO_OTYPER_ODR_6 GPIO_ODR_ODR_6
+#define GPIO_OTYPER_ODR_7 GPIO_ODR_ODR_7
+#define GPIO_OTYPER_ODR_8 GPIO_ODR_ODR_8
+#define GPIO_OTYPER_ODR_9 GPIO_ODR_ODR_9
+#define GPIO_OTYPER_ODR_10 GPIO_ODR_ODR_10
+#define GPIO_OTYPER_ODR_11 GPIO_ODR_ODR_11
+#define GPIO_OTYPER_ODR_12 GPIO_ODR_ODR_12
+#define GPIO_OTYPER_ODR_13 GPIO_ODR_ODR_13
+#define GPIO_OTYPER_ODR_14 GPIO_ODR_ODR_14
+#define GPIO_OTYPER_ODR_15 GPIO_ODR_ODR_15
+
+/****************** Bits definition for GPIO_BSRR register ******************/
+#define GPIO_BSRR_BS_0 0x00000001U
+#define GPIO_BSRR_BS_1 0x00000002U
+#define GPIO_BSRR_BS_2 0x00000004U
+#define GPIO_BSRR_BS_3 0x00000008U
+#define GPIO_BSRR_BS_4 0x00000010U
+#define GPIO_BSRR_BS_5 0x00000020U
+#define GPIO_BSRR_BS_6 0x00000040U
+#define GPIO_BSRR_BS_7 0x00000080U
+#define GPIO_BSRR_BS_8 0x00000100U
+#define GPIO_BSRR_BS_9 0x00000200U
+#define GPIO_BSRR_BS_10 0x00000400U
+#define GPIO_BSRR_BS_11 0x00000800U
+#define GPIO_BSRR_BS_12 0x00001000U
+#define GPIO_BSRR_BS_13 0x00002000U
+#define GPIO_BSRR_BS_14 0x00004000U
+#define GPIO_BSRR_BS_15 0x00008000U
+#define GPIO_BSRR_BR_0 0x00010000U
+#define GPIO_BSRR_BR_1 0x00020000U
+#define GPIO_BSRR_BR_2 0x00040000U
+#define GPIO_BSRR_BR_3 0x00080000U
+#define GPIO_BSRR_BR_4 0x00100000U
+#define GPIO_BSRR_BR_5 0x00200000U
+#define GPIO_BSRR_BR_6 0x00400000U
+#define GPIO_BSRR_BR_7 0x00800000U
+#define GPIO_BSRR_BR_8 0x01000000U
+#define GPIO_BSRR_BR_9 0x02000000U
+#define GPIO_BSRR_BR_10 0x04000000U
+#define GPIO_BSRR_BR_11 0x08000000U
+#define GPIO_BSRR_BR_12 0x10000000U
+#define GPIO_BSRR_BR_13 0x20000000U
+#define GPIO_BSRR_BR_14 0x40000000U
+#define GPIO_BSRR_BR_15 0x80000000U
+
+/****************** Bit definition for GPIO_LCKR register *********************/
+#define GPIO_LCKR_LCK0 0x00000001U
+#define GPIO_LCKR_LCK1 0x00000002U
+#define GPIO_LCKR_LCK2 0x00000004U
+#define GPIO_LCKR_LCK3 0x00000008U
+#define GPIO_LCKR_LCK4 0x00000010U
+#define GPIO_LCKR_LCK5 0x00000020U
+#define GPIO_LCKR_LCK6 0x00000040U
+#define GPIO_LCKR_LCK7 0x00000080U
+#define GPIO_LCKR_LCK8 0x00000100U
+#define GPIO_LCKR_LCK9 0x00000200U
+#define GPIO_LCKR_LCK10 0x00000400U
+#define GPIO_LCKR_LCK11 0x00000800U
+#define GPIO_LCKR_LCK12 0x00001000U
+#define GPIO_LCKR_LCK13 0x00002000U
+#define GPIO_LCKR_LCK14 0x00004000U
+#define GPIO_LCKR_LCK15 0x00008000U
+#define GPIO_LCKR_LCKK 0x00010000U
+
+/******************************************************************************/
+/* */
+/* Inter-integrated Circuit Interface */
+/* */
+/******************************************************************************/
+/******************* Bit definition for I2C_CR1 register ********************/
+#define I2C_CR1_PE 0x00000001U /*!<Peripheral Enable */
+#define I2C_CR1_SMBUS 0x00000002U /*!<SMBus Mode */
+#define I2C_CR1_SMBTYPE 0x00000008U /*!<SMBus Type */
+#define I2C_CR1_ENARP 0x00000010U /*!<ARP Enable */
+#define I2C_CR1_ENPEC 0x00000020U /*!<PEC Enable */
+#define I2C_CR1_ENGC 0x00000040U /*!<General Call Enable */
+#define I2C_CR1_NOSTRETCH 0x00000080U /*!<Clock Stretching Disable (Slave mode) */
+#define I2C_CR1_START 0x00000100U /*!<Start Generation */
+#define I2C_CR1_STOP 0x00000200U /*!<Stop Generation */
+#define I2C_CR1_ACK 0x00000400U /*!<Acknowledge Enable */
+#define I2C_CR1_POS 0x00000800U /*!<Acknowledge/PEC Position (for data reception) */
+#define I2C_CR1_PEC 0x00001000U /*!<Packet Error Checking */
+#define I2C_CR1_ALERT 0x00002000U /*!<SMBus Alert */
+#define I2C_CR1_SWRST 0x00008000U /*!<Software Reset */
+
+/******************* Bit definition for I2C_CR2 register ********************/
+#define I2C_CR2_FREQ 0x0000003FU /*!<FREQ[5:0] bits (Peripheral Clock Frequency) */
+#define I2C_CR2_FREQ_0 0x00000001U /*!<Bit 0 */
+#define I2C_CR2_FREQ_1 0x00000002U /*!<Bit 1 */
+#define I2C_CR2_FREQ_2 0x00000004U /*!<Bit 2 */
+#define I2C_CR2_FREQ_3 0x00000008U /*!<Bit 3 */
+#define I2C_CR2_FREQ_4 0x00000010U /*!<Bit 4 */
+#define I2C_CR2_FREQ_5 0x00000020U /*!<Bit 5 */
+
+#define I2C_CR2_ITERREN 0x00000100U /*!<Error Interrupt Enable */
+#define I2C_CR2_ITEVTEN 0x00000200U /*!<Event Interrupt Enable */
+#define I2C_CR2_ITBUFEN 0x00000400U /*!<Buffer Interrupt Enable */
+#define I2C_CR2_DMAEN 0x00000800U /*!<DMA Requests Enable */
+#define I2C_CR2_LAST 0x00001000U /*!<DMA Last Transfer */
+
+/******************* Bit definition for I2C_OAR1 register *******************/
+#define I2C_OAR1_ADD1_7 0x000000FEU /*!<Interface Address */
+#define I2C_OAR1_ADD8_9 0x00000300U /*!<Interface Address */
+
+#define I2C_OAR1_ADD0 0x00000001U /*!<Bit 0 */
+#define I2C_OAR1_ADD1 0x00000002U /*!<Bit 1 */
+#define I2C_OAR1_ADD2 0x00000004U /*!<Bit 2 */
+#define I2C_OAR1_ADD3 0x00000008U /*!<Bit 3 */
+#define I2C_OAR1_ADD4 0x00000010U /*!<Bit 4 */
+#define I2C_OAR1_ADD5 0x00000020U /*!<Bit 5 */
+#define I2C_OAR1_ADD6 0x00000040U /*!<Bit 6 */
+#define I2C_OAR1_ADD7 0x00000080U /*!<Bit 7 */
+#define I2C_OAR1_ADD8 0x00000100U /*!<Bit 8 */
+#define I2C_OAR1_ADD9 0x00000200U /*!<Bit 9 */
+
+#define I2C_OAR1_ADDMODE 0x00008000U /*!<Addressing Mode (Slave mode) */
+
+/******************* Bit definition for I2C_OAR2 register *******************/
+#define I2C_OAR2_ENDUAL 0x00000001U /*!<Dual addressing mode enable */
+#define I2C_OAR2_ADD2 0x000000FEU /*!<Interface address */
+
+/******************** Bit definition for I2C_DR register ********************/
+#define I2C_DR_DR 0x000000FFU /*!<8-bit Data Register */
+
+/******************* Bit definition for I2C_SR1 register ********************/
+#define I2C_SR1_SB 0x00000001U /*!<Start Bit (Master mode) */
+#define I2C_SR1_ADDR 0x00000002U /*!<Address sent (master mode)/matched (slave mode) */
+#define I2C_SR1_BTF 0x00000004U /*!<Byte Transfer Finished */
+#define I2C_SR1_ADD10 0x00000008U /*!<10-bit header sent (Master mode) */
+#define I2C_SR1_STOPF 0x00000010U /*!<Stop detection (Slave mode) */
+#define I2C_SR1_RXNE 0x00000040U /*!<Data Register not Empty (receivers) */
+#define I2C_SR1_TXE 0x00000080U /*!<Data Register Empty (transmitters) */
+#define I2C_SR1_BERR 0x00000100U /*!<Bus Error */
+#define I2C_SR1_ARLO 0x00000200U /*!<Arbitration Lost (master mode) */
+#define I2C_SR1_AF 0x00000400U /*!<Acknowledge Failure */
+#define I2C_SR1_OVR 0x00000800U /*!<Overrun/Underrun */
+#define I2C_SR1_PECERR 0x00001000U /*!<PEC Error in reception */
+#define I2C_SR1_TIMEOUT 0x00004000U /*!<Timeout or Tlow Error */
+#define I2C_SR1_SMBALERT 0x00008000U /*!<SMBus Alert */
+
+/******************* Bit definition for I2C_SR2 register ********************/
+#define I2C_SR2_MSL 0x00000001U /*!<Master/Slave */
+#define I2C_SR2_BUSY 0x00000002U /*!<Bus Busy */
+#define I2C_SR2_TRA 0x00000004U /*!<Transmitter/Receiver */
+#define I2C_SR2_GENCALL 0x00000010U /*!<General Call Address (Slave mode) */
+#define I2C_SR2_SMBDEFAULT 0x00000020U /*!<SMBus Device Default Address (Slave mode) */
+#define I2C_SR2_SMBHOST 0x00000040U /*!<SMBus Host Header (Slave mode) */
+#define I2C_SR2_DUALF 0x00000080U /*!<Dual Flag (Slave mode) */
+#define I2C_SR2_PEC 0x0000FF00U /*!<Packet Error Checking Register */
+
+/******************* Bit definition for I2C_CCR register ********************/
+#define I2C_CCR_CCR 0x00000FFFU /*!<Clock Control Register in Fast/Standard mode (Master mode) */
+#define I2C_CCR_DUTY 0x00004000U /*!<Fast Mode Duty Cycle */
+#define I2C_CCR_FS 0x00008000U /*!<I2C Master Mode Selection */
+
+/****************** Bit definition for I2C_TRISE register *******************/
+#define I2C_TRISE_TRISE 0x0000003FU /*!<Maximum Rise Time in Fast/Standard mode (Master mode) */
+
+/****************** Bit definition for I2C_FLTR register *******************/
+#define I2C_FLTR_DNF 0x0000000FU /*!<Digital Noise Filter */
+#define I2C_FLTR_ANOFF 0x00000010U /*!<Analog Noise Filter OFF */
+
+/******************************************************************************/
+/* */
+/* Independent WATCHDOG */
+/* */
+/******************************************************************************/
+/******************* Bit definition for IWDG_KR register ********************/
+#define IWDG_KR_KEY 0xFFFFU /*!<Key value (write only, read 0000h) */
+
+/******************* Bit definition for IWDG_PR register ********************/
+#define IWDG_PR_PR 0x07U /*!<PR[2:0] (Prescaler divider) */
+#define IWDG_PR_PR_0 0x01U /*!<Bit 0 */
+#define IWDG_PR_PR_1 0x02U /*!<Bit 1 */
+#define IWDG_PR_PR_2 0x04U /*!<Bit 2 */
+
+/******************* Bit definition for IWDG_RLR register *******************/
+#define IWDG_RLR_RL 0x0FFFU /*!<Watchdog counter reload value */
+
+/******************* Bit definition for IWDG_SR register ********************/
+#define IWDG_SR_PVU 0x01U /*!<Watchdog prescaler value update */
+#define IWDG_SR_RVU 0x02U /*!<Watchdog counter reload value update */
+
+
+/******************************************************************************/
+/* */
+/* LCD-TFT Display Controller (LTDC) */
+/* */
+/******************************************************************************/
+
+/******************** Bit definition for LTDC_SSCR register *****************/
+
+#define LTDC_SSCR_VSH 0x000007FFU /*!< Vertical Synchronization Height */
+#define LTDC_SSCR_HSW 0x0FFF0000U /*!< Horizontal Synchronization Width */
+
+/******************** Bit definition for LTDC_BPCR register *****************/
+
+#define LTDC_BPCR_AVBP 0x000007FFU /*!< Accumulated Vertical Back Porch */
+#define LTDC_BPCR_AHBP 0x0FFF0000U /*!< Accumulated Horizontal Back Porch */
+
+/******************** Bit definition for LTDC_AWCR register *****************/
+
+#define LTDC_AWCR_AAH 0x000007FFU /*!< Accumulated Active heigh */
+#define LTDC_AWCR_AAW 0x0FFF0000U /*!< Accumulated Active Width */
+
+/******************** Bit definition for LTDC_TWCR register *****************/
+
+#define LTDC_TWCR_TOTALH 0x000007FFU /*!< Total Heigh */
+#define LTDC_TWCR_TOTALW 0x0FFF0000U /*!< Total Width */
+
+/******************** Bit definition for LTDC_GCR register ******************/
+
+#define LTDC_GCR_LTDCEN 0x00000001U /*!< LCD-TFT controller enable bit */
+#define LTDC_GCR_DBW 0x00000070U /*!< Dither Blue Width */
+#define LTDC_GCR_DGW 0x00000700U /*!< Dither Green Width */
+#define LTDC_GCR_DRW 0x00007000U /*!< Dither Red Width */
+#define LTDC_GCR_DEN 0x00010000U /*!< Dither Enable */
+#define LTDC_GCR_PCPOL 0x10000000U /*!< Pixel Clock Polarity */
+#define LTDC_GCR_DEPOL 0x20000000U /*!< Data Enable Polarity */
+#define LTDC_GCR_VSPOL 0x40000000U /*!< Vertical Synchronization Polarity */
+#define LTDC_GCR_HSPOL 0x80000000U /*!< Horizontal Synchronization Polarity */
+
+/* Legacy defines */
+#define LTDC_GCR_DTEN LTDC_GCR_DEN
+
+/******************** Bit definition for LTDC_SRCR register *****************/
+
+#define LTDC_SRCR_IMR 0x00000001U /*!< Immediate Reload */
+#define LTDC_SRCR_VBR 0x00000002U /*!< Vertical Blanking Reload */
+
+/******************** Bit definition for LTDC_BCCR register *****************/
+
+#define LTDC_BCCR_BCBLUE 0x000000FFU /*!< Background Blue value */
+#define LTDC_BCCR_BCGREEN 0x0000FF00U /*!< Background Green value */
+#define LTDC_BCCR_BCRED 0x00FF0000U /*!< Background Red value */
+
+/******************** Bit definition for LTDC_IER register ******************/
+
+#define LTDC_IER_LIE 0x00000001U /*!< Line Interrupt Enable */
+#define LTDC_IER_FUIE 0x00000002U /*!< FIFO Underrun Interrupt Enable */
+#define LTDC_IER_TERRIE 0x00000004U /*!< Transfer Error Interrupt Enable */
+#define LTDC_IER_RRIE 0x00000008U /*!< Register Reload interrupt enable */
+
+/******************** Bit definition for LTDC_ISR register ******************/
+
+#define LTDC_ISR_LIF 0x00000001U /*!< Line Interrupt Flag */
+#define LTDC_ISR_FUIF 0x00000002U /*!< FIFO Underrun Interrupt Flag */
+#define LTDC_ISR_TERRIF 0x00000004U /*!< Transfer Error Interrupt Flag */
+#define LTDC_ISR_RRIF 0x00000008U /*!< Register Reload interrupt Flag */
+
+/******************** Bit definition for LTDC_ICR register ******************/
+
+#define LTDC_ICR_CLIF 0x00000001U /*!< Clears the Line Interrupt Flag */
+#define LTDC_ICR_CFUIF 0x00000002U /*!< Clears the FIFO Underrun Interrupt Flag */
+#define LTDC_ICR_CTERRIF 0x00000004U /*!< Clears the Transfer Error Interrupt Flag */
+#define LTDC_ICR_CRRIF 0x00000008U /*!< Clears Register Reload interrupt Flag */
+
+/******************** Bit definition for LTDC_LIPCR register ****************/
+
+#define LTDC_LIPCR_LIPOS 0x000007FFU /*!< Line Interrupt Position */
+
+/******************** Bit definition for LTDC_CPSR register *****************/
+
+#define LTDC_CPSR_CYPOS 0x0000FFFFU /*!< Current Y Position */
+#define LTDC_CPSR_CXPOS 0xFFFF0000U /*!< Current X Position */
+
+/******************** Bit definition for LTDC_CDSR register *****************/
+
+#define LTDC_CDSR_VDES 0x00000001U /*!< Vertical Data Enable Status */
+#define LTDC_CDSR_HDES 0x00000002U /*!< Horizontal Data Enable Status */
+#define LTDC_CDSR_VSYNCS 0x00000004U /*!< Vertical Synchronization Status */
+#define LTDC_CDSR_HSYNCS 0x00000008U /*!< Horizontal Synchronization Status */
+
+/******************** Bit definition for LTDC_LxCR register *****************/
+
+#define LTDC_LxCR_LEN 0x00000001U /*!< Layer Enable */
+#define LTDC_LxCR_COLKEN 0x00000002U /*!< Color Keying Enable */
+#define LTDC_LxCR_CLUTEN 0x00000010U /*!< Color Lockup Table Enable */
+
+/******************** Bit definition for LTDC_LxWHPCR register **************/
+
+#define LTDC_LxWHPCR_WHSTPOS 0x00000FFFU /*!< Window Horizontal Start Position */
+#define LTDC_LxWHPCR_WHSPPOS 0xFFFF0000U /*!< Window Horizontal Stop Position */
+
+/******************** Bit definition for LTDC_LxWVPCR register **************/
+
+#define LTDC_LxWVPCR_WVSTPOS 0x00000FFFU /*!< Window Vertical Start Position */
+#define LTDC_LxWVPCR_WVSPPOS 0xFFFF0000U /*!< Window Vertical Stop Position */
+
+/******************** Bit definition for LTDC_LxCKCR register ***************/
+
+#define LTDC_LxCKCR_CKBLUE 0x000000FFU /*!< Color Key Blue value */
+#define LTDC_LxCKCR_CKGREEN 0x0000FF00U /*!< Color Key Green value */
+#define LTDC_LxCKCR_CKRED 0x00FF0000U /*!< Color Key Red value */
+
+/******************** Bit definition for LTDC_LxPFCR register ***************/
+
+#define LTDC_LxPFCR_PF 0x00000007U /*!< Pixel Format */
+
+/******************** Bit definition for LTDC_LxCACR register ***************/
+
+#define LTDC_LxCACR_CONSTA 0x000000FFU /*!< Constant Alpha */
+
+/******************** Bit definition for LTDC_LxDCCR register ***************/
+
+#define LTDC_LxDCCR_DCBLUE 0x000000FFU /*!< Default Color Blue */
+#define LTDC_LxDCCR_DCGREEN 0x0000FF00U /*!< Default Color Green */
+#define LTDC_LxDCCR_DCRED 0x00FF0000U /*!< Default Color Red */
+#define LTDC_LxDCCR_DCALPHA 0xFF000000U /*!< Default Color Alpha */
+
+/******************** Bit definition for LTDC_LxBFCR register ***************/
+
+#define LTDC_LxBFCR_BF2 0x00000007U /*!< Blending Factor 2 */
+#define LTDC_LxBFCR_BF1 0x00000700U /*!< Blending Factor 1 */
+
+/******************** Bit definition for LTDC_LxCFBAR register **************/
+
+#define LTDC_LxCFBAR_CFBADD 0xFFFFFFFFU /*!< Color Frame Buffer Start Address */
+
+/******************** Bit definition for LTDC_LxCFBLR register **************/
+
+#define LTDC_LxCFBLR_CFBLL 0x00001FFFU /*!< Color Frame Buffer Line Length */
+#define LTDC_LxCFBLR_CFBP 0x1FFF0000U /*!< Color Frame Buffer Pitch in bytes */
+
+/******************** Bit definition for LTDC_LxCFBLNR register *************/
+
+#define LTDC_LxCFBLNR_CFBLNBR 0x000007FFU /*!< Frame Buffer Line Number */
+
+/******************** Bit definition for LTDC_LxCLUTWR register *************/
+
+#define LTDC_LxCLUTWR_BLUE 0x000000FFU /*!< Blue value */
+#define LTDC_LxCLUTWR_GREEN 0x0000FF00U /*!< Green value */
+#define LTDC_LxCLUTWR_RED 0x00FF0000U /*!< Red value */
+#define LTDC_LxCLUTWR_CLUTADD 0xFF000000U /*!< CLUT address */
+
+
+/******************************************************************************/
+/* */
+/* Power Control */
+/* */
+/******************************************************************************/
+/******************** Bit definition for PWR_CR register ********************/
+#define PWR_CR_LPDS 0x00000001U /*!< Low-Power Deepsleep */
+#define PWR_CR_PDDS 0x00000002U /*!< Power Down Deepsleep */
+#define PWR_CR_CWUF 0x00000004U /*!< Clear Wakeup Flag */
+#define PWR_CR_CSBF 0x00000008U /*!< Clear Standby Flag */
+#define PWR_CR_PVDE 0x00000010U /*!< Power Voltage Detector Enable */
+
+#define PWR_CR_PLS 0x000000E0U /*!< PLS[2:0] bits (PVD Level Selection) */
+#define PWR_CR_PLS_0 0x00000020U /*!< Bit 0 */
+#define PWR_CR_PLS_1 0x00000040U /*!< Bit 1 */
+#define PWR_CR_PLS_2 0x00000080U /*!< Bit 2 */
+
+/*!< PVD level configuration */
+#define PWR_CR_PLS_LEV0 0x00000000U /*!< PVD level 0 */
+#define PWR_CR_PLS_LEV1 0x00000020U /*!< PVD level 1 */
+#define PWR_CR_PLS_LEV2 0x00000040U /*!< PVD level 2 */
+#define PWR_CR_PLS_LEV3 0x00000060U /*!< PVD level 3 */
+#define PWR_CR_PLS_LEV4 0x00000080U /*!< PVD level 4 */
+#define PWR_CR_PLS_LEV5 0x000000A0U /*!< PVD level 5 */
+#define PWR_CR_PLS_LEV6 0x000000C0U /*!< PVD level 6 */
+#define PWR_CR_PLS_LEV7 0x000000E0U /*!< PVD level 7 */
+#define PWR_CR_DBP 0x00000100U /*!< Disable Backup Domain write protection */
+#define PWR_CR_FPDS 0x00000200U /*!< Flash power down in Stop mode */
+#define PWR_CR_LPLVDS 0x00000400U /*!< Low-Power Regulator Low Voltage Scaling in Stop mode */
+#define PWR_CR_MRLVDS 0x00000800U /*!< Main regulator Low Voltage Scaling in Stop mode */
+#define PWR_CR_ADCDC1 0x00002000U /*!< Refer to AN4073 on how to use this bit */
+#define PWR_CR_VOS 0x0000C000U /*!< VOS[1:0] bits (Regulator voltage scaling output selection) */
+#define PWR_CR_VOS_0 0x00004000U /*!< Bit 0 */
+#define PWR_CR_VOS_1 0x00008000U /*!< Bit 1 */
+#define PWR_CR_ODEN 0x00010000U /*!< Over Drive enable */
+#define PWR_CR_ODSWEN 0x00020000U /*!< Over Drive switch enabled */
+#define PWR_CR_UDEN 0x000C0000U /*!< Under Drive enable in stop mode */
+#define PWR_CR_UDEN_0 0x00040000U /*!< Bit 0 */
+#define PWR_CR_UDEN_1 0x00080000U /*!< Bit 1 */
+
+/* Legacy define */
+#define PWR_CR_PMODE PWR_CR_VOS
+#define PWR_CR_LPUDS PWR_CR_LPLVDS /*!< Low-Power Regulator in deepsleep under-drive mode */
+#define PWR_CR_MRUDS PWR_CR_MRLVDS /*!< Main regulator in deepsleep under-drive mode */
+
+/******************* Bit definition for PWR_CSR register ********************/
+#define PWR_CSR_WUF 0x00000001U /*!< Wakeup Flag */
+#define PWR_CSR_SBF 0x00000002U /*!< Standby Flag */
+#define PWR_CSR_PVDO 0x00000004U /*!< PVD Output */
+#define PWR_CSR_BRR 0x00000008U /*!< Backup regulator ready */
+#define PWR_CSR_WUPP 0x00000080U /*!< WKUP pin Polarity */
+#define PWR_CSR_EWUP 0x00000100U /*!< Enable WKUP pin */
+#define PWR_CSR_BRE 0x00000200U /*!< Backup regulator enable */
+#define PWR_CSR_VOSRDY 0x00004000U /*!< Regulator voltage scaling output selection ready */
+#define PWR_CSR_ODRDY 0x00010000U /*!< Over Drive generator ready */
+#define PWR_CSR_ODSWRDY 0x00020000U /*!< Over Drive Switch ready */
+#define PWR_CSR_UDSWRDY 0x000C0000U /*!< Under Drive ready */
+
+/* Legacy define */
+#define PWR_CSR_REGRDY PWR_CSR_VOSRDY
+
+/******************************************************************************/
+/* */
+/* QUADSPI */
+/* */
+/******************************************************************************/
+/***************** Bit definition for QUADSPI_CR register *******************/
+#define QUADSPI_CR_EN 0x00000001U /*!< Enable */
+#define QUADSPI_CR_ABORT 0x00000002U /*!< Abort request */
+#define QUADSPI_CR_DMAEN 0x00000004U /*!< DMA Enable */
+#define QUADSPI_CR_TCEN 0x00000008U /*!< Timeout Counter Enable */
+#define QUADSPI_CR_SSHIFT 0x00000010U /*!< SSHIFT Sample Shift */
+#define QUADSPI_CR_DFM 0x00000040U /*!< Dual Flash Mode */
+#define QUADSPI_CR_FSEL 0x00000080U /*!< Flash Select */
+#define QUADSPI_CR_FTHRES 0x00001F00U /*!< FTHRES[3:0] FIFO Level */
+#define QUADSPI_CR_FTHRES_0 0x00000100U /*!< Bit 0 */
+#define QUADSPI_CR_FTHRES_1 0x00000200U /*!< Bit 1 */
+#define QUADSPI_CR_FTHRES_2 0x00000400U /*!< Bit 2 */
+#define QUADSPI_CR_FTHRES_3 0x00000800U /*!< Bit 3 */
+#define QUADSPI_CR_FTHRES_4 0x00001000U /*!< Bit 4 */
+#define QUADSPI_CR_TEIE 0x00010000U /*!< Transfer Error Interrupt Enable */
+#define QUADSPI_CR_TCIE 0x00020000U /*!< Transfer Complete Interrupt Enable */
+#define QUADSPI_CR_FTIE 0x00040000U /*!< FIFO Threshold Interrupt Enable */
+#define QUADSPI_CR_SMIE 0x00080000U /*!< Status Match Interrupt Enable */
+#define QUADSPI_CR_TOIE 0x00100000U /*!< TimeOut Interrupt Enable */
+#define QUADSPI_CR_APMS 0x00400000U /*!< Bit 1 */
+#define QUADSPI_CR_PMM 0x00800000U /*!< Polling Match Mode */
+#define QUADSPI_CR_PRESCALER 0xFF000000U /*!< PRESCALER[7:0] Clock prescaler */
+#define QUADSPI_CR_PRESCALER_0 0x01000000U /*!< Bit 0 */
+#define QUADSPI_CR_PRESCALER_1 0x02000000U /*!< Bit 1 */
+#define QUADSPI_CR_PRESCALER_2 0x04000000U /*!< Bit 2 */
+#define QUADSPI_CR_PRESCALER_3 0x08000000U /*!< Bit 3 */
+#define QUADSPI_CR_PRESCALER_4 0x10000000U /*!< Bit 4 */
+#define QUADSPI_CR_PRESCALER_5 0x20000000U /*!< Bit 5 */
+#define QUADSPI_CR_PRESCALER_6 0x40000000U /*!< Bit 6 */
+#define QUADSPI_CR_PRESCALER_7 0x80000000U /*!< Bit 7 */
+
+/***************** Bit definition for QUADSPI_DCR register ******************/
+#define QUADSPI_DCR_CKMODE 0x00000001U /*!< Mode 0 / Mode 3 */
+#define QUADSPI_DCR_CSHT 0x00000700U /*!< CSHT[2:0]: ChipSelect High Time */
+#define QUADSPI_DCR_CSHT_0 0x00000100U /*!< Bit 0 */
+#define QUADSPI_DCR_CSHT_1 0x00000200U /*!< Bit 1 */
+#define QUADSPI_DCR_CSHT_2 0x00000400U /*!< Bit 2 */
+#define QUADSPI_DCR_FSIZE 0x001F0000U /*!< FSIZE[4:0]: Flash Size */
+#define QUADSPI_DCR_FSIZE_0 0x00010000U /*!< Bit 0 */
+#define QUADSPI_DCR_FSIZE_1 0x00020000U /*!< Bit 1 */
+#define QUADSPI_DCR_FSIZE_2 0x00040000U /*!< Bit 2 */
+#define QUADSPI_DCR_FSIZE_3 0x00080000U /*!< Bit 3 */
+#define QUADSPI_DCR_FSIZE_4 0x00100000U /*!< Bit 4 */
+
+/****************** Bit definition for QUADSPI_SR register *******************/
+#define QUADSPI_SR_TEF 0x00000001U /*!< Transfer Error Flag */
+#define QUADSPI_SR_TCF 0x00000002U /*!< Transfer Complete Flag */
+#define QUADSPI_SR_FTF 0x00000004U /*!< FIFO Threshlod Flag */
+#define QUADSPI_SR_SMF 0x00000008U /*!< Status Match Flag */
+#define QUADSPI_SR_TOF 0x00000010U /*!< Timeout Flag */
+#define QUADSPI_SR_BUSY 0x00000020U /*!< Busy */
+#define QUADSPI_SR_FLEVEL 0x00003F00U /*!< FIFO Threshlod Flag */
+#define QUADSPI_SR_FLEVEL_0 0x00000100U /*!< Bit 0 */
+#define QUADSPI_SR_FLEVEL_1 0x00000200U /*!< Bit 1 */
+#define QUADSPI_SR_FLEVEL_2 0x00000400U /*!< Bit 2 */
+#define QUADSPI_SR_FLEVEL_3 0x00000800U /*!< Bit 3 */
+#define QUADSPI_SR_FLEVEL_4 0x00001000U /*!< Bit 4 */
+#define QUADSPI_SR_FLEVEL_5 0x00002000U /*!< Bit 5 */
+
+/****************** Bit definition for QUADSPI_FCR register ******************/
+#define QUADSPI_FCR_CTEF 0x00000001U /*!< Clear Transfer Error Flag */
+#define QUADSPI_FCR_CTCF 0x00000002U /*!< Clear Transfer Complete Flag */
+#define QUADSPI_FCR_CSMF 0x00000008U /*!< Clear Status Match Flag */
+#define QUADSPI_FCR_CTOF 0x00000010U /*!< Clear Timeout Flag */
+
+/****************** Bit definition for QUADSPI_DLR register ******************/
+#define QUADSPI_DLR_DL 0xFFFFFFFFU /*!< DL[31:0]: Data Length */
+
+/****************** Bit definition for QUADSPI_CCR register ******************/
+#define QUADSPI_CCR_INSTRUCTION 0x000000FFU /*!< INSTRUCTION[7:0]: Instruction */
+#define QUADSPI_CCR_INSTRUCTION_0 0x00000001U /*!< Bit 0 */
+#define QUADSPI_CCR_INSTRUCTION_1 0x00000002U /*!< Bit 1 */
+#define QUADSPI_CCR_INSTRUCTION_2 0x00000004U /*!< Bit 2 */
+#define QUADSPI_CCR_INSTRUCTION_3 0x00000008U /*!< Bit 3 */
+#define QUADSPI_CCR_INSTRUCTION_4 0x00000010U /*!< Bit 4 */
+#define QUADSPI_CCR_INSTRUCTION_5 0x00000020U /*!< Bit 5 */
+#define QUADSPI_CCR_INSTRUCTION_6 0x00000040U /*!< Bit 6 */
+#define QUADSPI_CCR_INSTRUCTION_7 0x00000080U /*!< Bit 7 */
+#define QUADSPI_CCR_IMODE 0x00000300U /*!< IMODE[1:0]: Instruction Mode */
+#define QUADSPI_CCR_IMODE_0 0x00000100U /*!< Bit 0 */
+#define QUADSPI_CCR_IMODE_1 0x00000200U /*!< Bit 1 */
+#define QUADSPI_CCR_ADMODE 0x00000C00U /*!< ADMODE[1:0]: Address Mode */
+#define QUADSPI_CCR_ADMODE_0 0x00000400U /*!< Bit 0 */
+#define QUADSPI_CCR_ADMODE_1 0x00000800U /*!< Bit 1 */
+#define QUADSPI_CCR_ADSIZE 0x00003000U /*!< ADSIZE[1:0]: Address Size */
+#define QUADSPI_CCR_ADSIZE_0 0x00001000U /*!< Bit 0 */
+#define QUADSPI_CCR_ADSIZE_1 0x00002000U /*!< Bit 1 */
+#define QUADSPI_CCR_ABMODE 0x0000C000U /*!< ABMODE[1:0]: Alternate Bytes Mode */
+#define QUADSPI_CCR_ABMODE_0 0x00004000U /*!< Bit 0 */
+#define QUADSPI_CCR_ABMODE_1 0x00008000U /*!< Bit 1 */
+#define QUADSPI_CCR_ABSIZE 0x00030000U /*!< ABSIZE[1:0]: Instruction Mode */
+#define QUADSPI_CCR_ABSIZE_0 0x00010000U /*!< Bit 0 */
+#define QUADSPI_CCR_ABSIZE_1 0x00020000U /*!< Bit 1 */
+#define QUADSPI_CCR_DCYC 0x007C0000U /*!< DCYC[4:0]: Dummy Cycles */
+#define QUADSPI_CCR_DCYC_0 0x00040000U /*!< Bit 0 */
+#define QUADSPI_CCR_DCYC_1 0x00080000U /*!< Bit 1 */
+#define QUADSPI_CCR_DCYC_2 0x00100000U /*!< Bit 2 */
+#define QUADSPI_CCR_DCYC_3 0x00200000U /*!< Bit 3 */
+#define QUADSPI_CCR_DCYC_4 0x00400000U /*!< Bit 4 */
+#define QUADSPI_CCR_DMODE 0x03000000U /*!< DMODE[1:0]: Data Mode */
+#define QUADSPI_CCR_DMODE_0 0x01000000U /*!< Bit 0 */
+#define QUADSPI_CCR_DMODE_1 0x02000000U /*!< Bit 1 */
+#define QUADSPI_CCR_FMODE 0x0C000000U /*!< FMODE[1:0]: Functional Mode */
+#define QUADSPI_CCR_FMODE_0 0x04000000U /*!< Bit 0 */
+#define QUADSPI_CCR_FMODE_1 0x08000000U /*!< Bit 1 */
+#define QUADSPI_CCR_SIOO 0x10000000U /*!< SIOO: Send Instruction Only Once Mode */
+#define QUADSPI_CCR_DHHC 0x40000000U /*!< DHHC: Delay Half Hclk Cycle */
+#define QUADSPI_CCR_DDRM 0x80000000U /*!< DDRM: Double Data Rate Mode */
+/****************** Bit definition for QUADSPI_AR register *******************/
+#define QUADSPI_AR_ADDRESS 0xFFFFFFFFU /*!< ADDRESS[31:0]: Address */
+
+/****************** Bit definition for QUADSPI_ABR register ******************/
+#define QUADSPI_ABR_ALTERNATE 0xFFFFFFFFU /*!< ALTERNATE[31:0]: Alternate Bytes */
+
+/****************** Bit definition for QUADSPI_DR register *******************/
+#define QUADSPI_DR_DATA 0xFFFFFFFFU /*!< DATA[31:0]: Data */
+
+/****************** Bit definition for QUADSPI_PSMKR register ****************/
+#define QUADSPI_PSMKR_MASK 0xFFFFFFFFU /*!< MASK[31:0]: Status Mask */
+
+/****************** Bit definition for QUADSPI_PSMAR register ****************/
+#define QUADSPI_PSMAR_MATCH 0xFFFFFFFFU /*!< MATCH[31:0]: Status Match */
+
+/****************** Bit definition for QUADSPI_PIR register *****************/
+#define QUADSPI_PIR_INTERVAL 0x0000FFFFU /*!< INTERVAL[15:0]: Polling Interval */
+
+/****************** Bit definition for QUADSPI_LPTR register *****************/
+#define QUADSPI_LPTR_TIMEOUT 0x0000FFFFU /*!< TIMEOUT[15:0]: Timeout period */
+
+/******************************************************************************/
+/* */
+/* Reset and Clock Control */
+/* */
+/******************************************************************************/
+/******************** Bit definition for RCC_CR register ********************/
+#define RCC_CR_HSION 0x00000001U
+#define RCC_CR_HSIRDY 0x00000002U
+
+#define RCC_CR_HSITRIM 0x000000F8U
+#define RCC_CR_HSITRIM_0 0x00000008U/*!<Bit 0 */
+#define RCC_CR_HSITRIM_1 0x00000010U/*!<Bit 1 */
+#define RCC_CR_HSITRIM_2 0x00000020U/*!<Bit 2 */
+#define RCC_CR_HSITRIM_3 0x00000040U/*!<Bit 3 */
+#define RCC_CR_HSITRIM_4 0x00000080U/*!<Bit 4 */
+
+#define RCC_CR_HSICAL 0x0000FF00U
+#define RCC_CR_HSICAL_0 0x00000100U/*!<Bit 0 */
+#define RCC_CR_HSICAL_1 0x00000200U/*!<Bit 1 */
+#define RCC_CR_HSICAL_2 0x00000400U/*!<Bit 2 */
+#define RCC_CR_HSICAL_3 0x00000800U/*!<Bit 3 */
+#define RCC_CR_HSICAL_4 0x00001000U/*!<Bit 4 */
+#define RCC_CR_HSICAL_5 0x00002000U/*!<Bit 5 */
+#define RCC_CR_HSICAL_6 0x00004000U/*!<Bit 6 */
+#define RCC_CR_HSICAL_7 0x00008000U/*!<Bit 7 */
+
+#define RCC_CR_HSEON 0x00010000U
+#define RCC_CR_HSERDY 0x00020000U
+#define RCC_CR_HSEBYP 0x00040000U
+#define RCC_CR_CSSON 0x00080000U
+#define RCC_CR_PLLON 0x01000000U
+#define RCC_CR_PLLRDY 0x02000000U
+#define RCC_CR_PLLI2SON 0x04000000U
+#define RCC_CR_PLLI2SRDY 0x08000000U
+#define RCC_CR_PLLSAION 0x10000000U
+#define RCC_CR_PLLSAIRDY 0x20000000U
+
+/******************** Bit definition for RCC_PLLCFGR register ***************/
+#define RCC_PLLCFGR_PLLM 0x0000003FU
+#define RCC_PLLCFGR_PLLM_0 0x00000001U
+#define RCC_PLLCFGR_PLLM_1 0x00000002U
+#define RCC_PLLCFGR_PLLM_2 0x00000004U
+#define RCC_PLLCFGR_PLLM_3 0x00000008U
+#define RCC_PLLCFGR_PLLM_4 0x00000010U
+#define RCC_PLLCFGR_PLLM_5 0x00000020U
+
+#define RCC_PLLCFGR_PLLN 0x00007FC0U
+#define RCC_PLLCFGR_PLLN_0 0x00000040U
+#define RCC_PLLCFGR_PLLN_1 0x00000080U
+#define RCC_PLLCFGR_PLLN_2 0x00000100U
+#define RCC_PLLCFGR_PLLN_3 0x00000200U
+#define RCC_PLLCFGR_PLLN_4 0x00000400U
+#define RCC_PLLCFGR_PLLN_5 0x00000800U
+#define RCC_PLLCFGR_PLLN_6 0x00001000U
+#define RCC_PLLCFGR_PLLN_7 0x00002000U
+#define RCC_PLLCFGR_PLLN_8 0x00004000U
+
+#define RCC_PLLCFGR_PLLP 0x00030000U
+#define RCC_PLLCFGR_PLLP_0 0x00010000U
+#define RCC_PLLCFGR_PLLP_1 0x00020000U
+
+#define RCC_PLLCFGR_PLLSRC 0x00400000U
+#define RCC_PLLCFGR_PLLSRC_HSE 0x00400000U
+#define RCC_PLLCFGR_PLLSRC_HSI 0x00000000U
+
+#define RCC_PLLCFGR_PLLQ 0x0F000000U
+#define RCC_PLLCFGR_PLLQ_0 0x01000000U
+#define RCC_PLLCFGR_PLLQ_1 0x02000000U
+#define RCC_PLLCFGR_PLLQ_2 0x04000000U
+#define RCC_PLLCFGR_PLLQ_3 0x08000000U
+
+#define RCC_PLLCFGR_PLLR 0x70000000U
+#define RCC_PLLCFGR_PLLR_0 0x10000000U
+#define RCC_PLLCFGR_PLLR_1 0x20000000U
+#define RCC_PLLCFGR_PLLR_2 0x40000000U
+
+
+/******************** Bit definition for RCC_CFGR register ******************/
+/*!< SW configuration */
+#define RCC_CFGR_SW 0x00000003U /*!< SW[1:0] bits (System clock Switch) */
+#define RCC_CFGR_SW_0 0x00000001U /*!< Bit 0 */
+#define RCC_CFGR_SW_1 0x00000002U /*!< Bit 1 */
+
+#define RCC_CFGR_SW_HSI 0x00000000U /*!< HSI selected as system clock */
+#define RCC_CFGR_SW_HSE 0x00000001U /*!< HSE selected as system clock */
+#define RCC_CFGR_SW_PLL 0x00000002U /*!< PLL selected as system clock */
+
+/*!< SWS configuration */
+#define RCC_CFGR_SWS 0x0000000CU /*!< SWS[1:0] bits (System Clock Switch Status) */
+#define RCC_CFGR_SWS_0 0x00000004U /*!< Bit 0 */
+#define RCC_CFGR_SWS_1 0x00000008U /*!< Bit 1 */
+
+#define RCC_CFGR_SWS_HSI 0x00000000U /*!< HSI oscillator used as system clock */
+#define RCC_CFGR_SWS_HSE 0x00000004U /*!< HSE oscillator used as system clock */
+#define RCC_CFGR_SWS_PLL 0x00000008U /*!< PLL used as system clock */
+
+/*!< HPRE configuration */
+#define RCC_CFGR_HPRE 0x000000F0U /*!< HPRE[3:0] bits (AHB prescaler) */
+#define RCC_CFGR_HPRE_0 0x00000010U /*!< Bit 0 */
+#define RCC_CFGR_HPRE_1 0x00000020U /*!< Bit 1 */
+#define RCC_CFGR_HPRE_2 0x00000040U /*!< Bit 2 */
+#define RCC_CFGR_HPRE_3 0x00000080U /*!< Bit 3 */
+
+#define RCC_CFGR_HPRE_DIV1 0x00000000U /*!< SYSCLK not divided */
+#define RCC_CFGR_HPRE_DIV2 0x00000080U /*!< SYSCLK divided by 2 */
+#define RCC_CFGR_HPRE_DIV4 0x00000090U /*!< SYSCLK divided by 4 */
+#define RCC_CFGR_HPRE_DIV8 0x000000A0U /*!< SYSCLK divided by 8 */
+#define RCC_CFGR_HPRE_DIV16 0x000000B0U /*!< SYSCLK divided by 16 */
+#define RCC_CFGR_HPRE_DIV64 0x000000C0U /*!< SYSCLK divided by 64 */
+#define RCC_CFGR_HPRE_DIV128 0x000000D0U /*!< SYSCLK divided by 128 */
+#define RCC_CFGR_HPRE_DIV256 0x000000E0U /*!< SYSCLK divided by 256 */
+#define RCC_CFGR_HPRE_DIV512 0x000000F0U /*!< SYSCLK divided by 512 */
+
+/*!< PPRE1 configuration */
+#define RCC_CFGR_PPRE1 0x00001C00U /*!< PRE1[2:0] bits (APB1 prescaler) */
+#define RCC_CFGR_PPRE1_0 0x00000400U /*!< Bit 0 */
+#define RCC_CFGR_PPRE1_1 0x00000800U /*!< Bit 1 */
+#define RCC_CFGR_PPRE1_2 0x00001000U /*!< Bit 2 */
+
+#define RCC_CFGR_PPRE1_DIV1 0x00000000U /*!< HCLK not divided */
+#define RCC_CFGR_PPRE1_DIV2 0x00001000U /*!< HCLK divided by 2 */
+#define RCC_CFGR_PPRE1_DIV4 0x00001400U /*!< HCLK divided by 4 */
+#define RCC_CFGR_PPRE1_DIV8 0x00001800U /*!< HCLK divided by 8 */
+#define RCC_CFGR_PPRE1_DIV16 0x00001C00U /*!< HCLK divided by 16 */
+
+/*!< PPRE2 configuration */
+#define RCC_CFGR_PPRE2 0x0000E000U /*!< PRE2[2:0] bits (APB2 prescaler) */
+#define RCC_CFGR_PPRE2_0 0x00002000U /*!< Bit 0 */
+#define RCC_CFGR_PPRE2_1 0x00004000U /*!< Bit 1 */
+#define RCC_CFGR_PPRE2_2 0x00008000U /*!< Bit 2 */
+
+#define RCC_CFGR_PPRE2_DIV1 0x00000000U /*!< HCLK not divided */
+#define RCC_CFGR_PPRE2_DIV2 0x00008000U /*!< HCLK divided by 2 */
+#define RCC_CFGR_PPRE2_DIV4 0x0000A000U /*!< HCLK divided by 4 */
+#define RCC_CFGR_PPRE2_DIV8 0x0000C000U /*!< HCLK divided by 8 */
+#define RCC_CFGR_PPRE2_DIV16 0x0000E000U /*!< HCLK divided by 16 */
+
+/*!< RTCPRE configuration */
+#define RCC_CFGR_RTCPRE 0x001F0000U
+#define RCC_CFGR_RTCPRE_0 0x00010000U
+#define RCC_CFGR_RTCPRE_1 0x00020000U
+#define RCC_CFGR_RTCPRE_2 0x00040000U
+#define RCC_CFGR_RTCPRE_3 0x00080000U
+#define RCC_CFGR_RTCPRE_4 0x00100000U
+
+/*!< MCO1 configuration */
+#define RCC_CFGR_MCO1 0x00600000U
+#define RCC_CFGR_MCO1_0 0x00200000U
+#define RCC_CFGR_MCO1_1 0x00400000U
+
+#define RCC_CFGR_I2SSRC 0x00800000U
+
+#define RCC_CFGR_MCO1PRE 0x07000000U
+#define RCC_CFGR_MCO1PRE_0 0x01000000U
+#define RCC_CFGR_MCO1PRE_1 0x02000000U
+#define RCC_CFGR_MCO1PRE_2 0x04000000U
+
+#define RCC_CFGR_MCO2PRE 0x38000000U
+#define RCC_CFGR_MCO2PRE_0 0x08000000U
+#define RCC_CFGR_MCO2PRE_1 0x10000000U
+#define RCC_CFGR_MCO2PRE_2 0x20000000U
+
+#define RCC_CFGR_MCO2 0xC0000000U
+#define RCC_CFGR_MCO2_0 0x40000000U
+#define RCC_CFGR_MCO2_1 0x80000000U
+
+/******************** Bit definition for RCC_CIR register *******************/
+#define RCC_CIR_LSIRDYF 0x00000001U
+#define RCC_CIR_LSERDYF 0x00000002U
+#define RCC_CIR_HSIRDYF 0x00000004U
+#define RCC_CIR_HSERDYF 0x00000008U
+#define RCC_CIR_PLLRDYF 0x00000010U
+#define RCC_CIR_PLLI2SRDYF 0x00000020U
+#define RCC_CIR_PLLSAIRDYF 0x00000040U
+#define RCC_CIR_CSSF 0x00000080U
+#define RCC_CIR_LSIRDYIE 0x00000100U
+#define RCC_CIR_LSERDYIE 0x00000200U
+#define RCC_CIR_HSIRDYIE 0x00000400U
+#define RCC_CIR_HSERDYIE 0x00000800U
+#define RCC_CIR_PLLRDYIE 0x00001000U
+#define RCC_CIR_PLLI2SRDYIE 0x00002000U
+#define RCC_CIR_PLLSAIRDYIE 0x00004000U
+#define RCC_CIR_LSIRDYC 0x00010000U
+#define RCC_CIR_LSERDYC 0x00020000U
+#define RCC_CIR_HSIRDYC 0x00040000U
+#define RCC_CIR_HSERDYC 0x00080000U
+#define RCC_CIR_PLLRDYC 0x00100000U
+#define RCC_CIR_PLLI2SRDYC 0x00200000U
+#define RCC_CIR_PLLSAIRDYC 0x00400000U
+#define RCC_CIR_CSSC 0x00800000U
+
+/******************** Bit definition for RCC_AHB1RSTR register **************/
+#define RCC_AHB1RSTR_GPIOARST 0x00000001U
+#define RCC_AHB1RSTR_GPIOBRST 0x00000002U
+#define RCC_AHB1RSTR_GPIOCRST 0x00000004U
+#define RCC_AHB1RSTR_GPIODRST 0x00000008U
+#define RCC_AHB1RSTR_GPIOERST 0x00000010U
+#define RCC_AHB1RSTR_GPIOFRST 0x00000020U
+#define RCC_AHB1RSTR_GPIOGRST 0x00000040U
+#define RCC_AHB1RSTR_GPIOHRST 0x00000080U
+#define RCC_AHB1RSTR_GPIOIRST 0x00000100U
+#define RCC_AHB1RSTR_GPIOJRST 0x00000200U
+#define RCC_AHB1RSTR_GPIOKRST 0x00000400U
+#define RCC_AHB1RSTR_CRCRST 0x00001000U
+#define RCC_AHB1RSTR_DMA1RST 0x00200000U
+#define RCC_AHB1RSTR_DMA2RST 0x00400000U
+#define RCC_AHB1RSTR_DMA2DRST 0x00800000U
+#define RCC_AHB1RSTR_ETHMACRST 0x02000000U
+#define RCC_AHB1RSTR_OTGHRST 0x20000000U
+
+/******************** Bit definition for RCC_AHB2RSTR register **************/
+#define RCC_AHB2RSTR_DCMIRST 0x00000001U
+#define RCC_AHB2RSTR_RNGRST 0x00000040U
+#define RCC_AHB2RSTR_OTGFSRST 0x00000080U
+
+/******************** Bit definition for RCC_AHB3RSTR register **************/
+#define RCC_AHB3RSTR_FMCRST 0x00000001U
+#define RCC_AHB3RSTR_QSPIRST 0x00000002U
+
+/******************** Bit definition for RCC_APB1RSTR register **************/
+#define RCC_APB1RSTR_TIM2RST 0x00000001U
+#define RCC_APB1RSTR_TIM3RST 0x00000002U
+#define RCC_APB1RSTR_TIM4RST 0x00000004U
+#define RCC_APB1RSTR_TIM5RST 0x00000008U
+#define RCC_APB1RSTR_TIM6RST 0x00000010U
+#define RCC_APB1RSTR_TIM7RST 0x00000020U
+#define RCC_APB1RSTR_TIM12RST 0x00000040U
+#define RCC_APB1RSTR_TIM13RST 0x00000080U
+#define RCC_APB1RSTR_TIM14RST 0x00000100U
+#define RCC_APB1RSTR_WWDGRST 0x00000800U
+#define RCC_APB1RSTR_SPI2RST 0x00004000U
+#define RCC_APB1RSTR_SPI3RST 0x00008000U
+#define RCC_APB1RSTR_USART2RST 0x00020000U
+#define RCC_APB1RSTR_USART3RST 0x00040000U
+#define RCC_APB1RSTR_UART4RST 0x00080000U
+#define RCC_APB1RSTR_UART5RST 0x00100000U
+#define RCC_APB1RSTR_I2C1RST 0x00200000U
+#define RCC_APB1RSTR_I2C2RST 0x00400000U
+#define RCC_APB1RSTR_I2C3RST 0x00800000U
+#define RCC_APB1RSTR_CAN1RST 0x02000000U
+#define RCC_APB1RSTR_CAN2RST 0x04000000U
+#define RCC_APB1RSTR_PWRRST 0x10000000U
+#define RCC_APB1RSTR_DACRST 0x20000000U
+#define RCC_APB1RSTR_UART7RST 0x40000000U
+#define RCC_APB1RSTR_UART8RST 0x80000000U
+
+/******************** Bit definition for RCC_APB2RSTR register **************/
+#define RCC_APB2RSTR_TIM1RST 0x00000001U
+#define RCC_APB2RSTR_TIM8RST 0x00000002U
+#define RCC_APB2RSTR_USART1RST 0x00000010U
+#define RCC_APB2RSTR_USART6RST 0x00000020U
+#define RCC_APB2RSTR_ADCRST 0x00000100U
+#define RCC_APB2RSTR_SDIORST 0x00000800U
+#define RCC_APB2RSTR_SPI1RST 0x00001000U
+#define RCC_APB2RSTR_SPI4RST 0x00002000U
+#define RCC_APB2RSTR_SYSCFGRST 0x00004000U
+#define RCC_APB2RSTR_TIM9RST 0x00010000U
+#define RCC_APB2RSTR_TIM10RST 0x00020000U
+#define RCC_APB2RSTR_TIM11RST 0x00040000U
+#define RCC_APB2RSTR_SPI5RST 0x00100000U
+#define RCC_APB2RSTR_SPI6RST 0x00200000U
+#define RCC_APB2RSTR_SAI1RST 0x00400000U
+#define RCC_APB2RSTR_LTDCRST 0x04000000U
+#define RCC_APB2RSTR_DSIRST 0x08000000U
+
+/* Old SPI1RST bit definition, maintained for legacy purpose */
+#define RCC_APB2RSTR_SPI1 RCC_APB2RSTR_SPI1RST
+
+/******************** Bit definition for RCC_AHB1ENR register ***************/
+#define RCC_AHB1ENR_GPIOAEN 0x00000001U
+#define RCC_AHB1ENR_GPIOBEN 0x00000002U
+#define RCC_AHB1ENR_GPIOCEN 0x00000004U
+#define RCC_AHB1ENR_GPIODEN 0x00000008U
+#define RCC_AHB1ENR_GPIOEEN 0x00000010U
+#define RCC_AHB1ENR_GPIOFEN 0x00000020U
+#define RCC_AHB1ENR_GPIOGEN 0x00000040U
+#define RCC_AHB1ENR_GPIOHEN 0x00000080U
+#define RCC_AHB1ENR_GPIOIEN 0x00000100U
+#define RCC_AHB1ENR_GPIOJEN 0x00000200U
+#define RCC_AHB1ENR_GPIOKEN 0x00000400U
+
+#define RCC_AHB1ENR_CRCEN 0x00001000U
+#define RCC_AHB1ENR_BKPSRAMEN 0x00040000U
+#define RCC_AHB1ENR_CCMDATARAMEN 0x00100000U
+#define RCC_AHB1ENR_DMA1EN 0x00200000U
+#define RCC_AHB1ENR_DMA2EN 0x00400000U
+#define RCC_AHB1ENR_DMA2DEN 0x00800000U
+
+#define RCC_AHB1ENR_ETHMACEN 0x02000000U
+#define RCC_AHB1ENR_ETHMACTXEN 0x04000000U
+#define RCC_AHB1ENR_ETHMACRXEN 0x08000000U
+#define RCC_AHB1ENR_ETHMACPTPEN 0x10000000U
+#define RCC_AHB1ENR_OTGHSEN 0x20000000U
+#define RCC_AHB1ENR_OTGHSULPIEN 0x40000000U
+
+/******************** Bit definition for RCC_AHB2ENR register ***************/
+#define RCC_AHB2ENR_DCMIEN 0x00000001U
+#define RCC_AHB2ENR_RNGEN 0x00000040U
+#define RCC_AHB2ENR_OTGFSEN 0x00000080U
+
+/******************** Bit definition for RCC_AHB3ENR register ***************/
+#define RCC_AHB3ENR_FMCEN 0x00000001U
+#define RCC_AHB3ENR_QSPIEN 0x00000002U
+
+/******************** Bit definition for RCC_APB1ENR register ***************/
+#define RCC_APB1ENR_TIM2EN 0x00000001U
+#define RCC_APB1ENR_TIM3EN 0x00000002U
+#define RCC_APB1ENR_TIM4EN 0x00000004U
+#define RCC_APB1ENR_TIM5EN 0x00000008U
+#define RCC_APB1ENR_TIM6EN 0x00000010U
+#define RCC_APB1ENR_TIM7EN 0x00000020U
+#define RCC_APB1ENR_TIM12EN 0x00000040U
+#define RCC_APB1ENR_TIM13EN 0x00000080U
+#define RCC_APB1ENR_TIM14EN 0x00000100U
+#define RCC_APB1ENR_WWDGEN 0x00000800U
+#define RCC_APB1ENR_SPI2EN 0x00004000U
+#define RCC_APB1ENR_SPI3EN 0x00008000U
+#define RCC_APB1ENR_USART2EN 0x00020000U
+#define RCC_APB1ENR_USART3EN 0x00040000U
+#define RCC_APB1ENR_UART4EN 0x00080000U
+#define RCC_APB1ENR_UART5EN 0x00100000U
+#define RCC_APB1ENR_I2C1EN 0x00200000U
+#define RCC_APB1ENR_I2C2EN 0x00400000U
+#define RCC_APB1ENR_I2C3EN 0x00800000U
+#define RCC_APB1ENR_CAN1EN 0x02000000U
+#define RCC_APB1ENR_CAN2EN 0x04000000U
+#define RCC_APB1ENR_PWREN 0x10000000U
+#define RCC_APB1ENR_DACEN 0x20000000U
+#define RCC_APB1ENR_UART7EN 0x40000000U
+#define RCC_APB1ENR_UART8EN 0x80000000U
+
+/******************** Bit definition for RCC_APB2ENR register ***************/
+#define RCC_APB2ENR_TIM1EN 0x00000001U
+#define RCC_APB2ENR_TIM8EN 0x00000002U
+#define RCC_APB2ENR_USART1EN 0x00000010U
+#define RCC_APB2ENR_USART6EN 0x00000020U
+#define RCC_APB2ENR_ADC1EN 0x00000100U
+#define RCC_APB2ENR_ADC2EN 0x00000200U
+#define RCC_APB2ENR_ADC3EN 0x00000400U
+#define RCC_APB2ENR_SDIOEN 0x00000800U
+#define RCC_APB2ENR_SPI1EN 0x00001000U
+#define RCC_APB2ENR_SPI4EN 0x00002000U
+#define RCC_APB2ENR_SYSCFGEN 0x00004000U
+#define RCC_APB2ENR_TIM9EN 0x00010000U
+#define RCC_APB2ENR_TIM10EN 0x00020000U
+#define RCC_APB2ENR_TIM11EN 0x00040000U
+#define RCC_APB2ENR_SPI5EN 0x00100000U
+#define RCC_APB2ENR_SPI6EN 0x00200000U
+#define RCC_APB2ENR_SAI1EN 0x00400000U
+#define RCC_APB2ENR_LTDCEN 0x04000000U
+#define RCC_APB2ENR_DSIEN 0x08000000U
+
+/******************** Bit definition for RCC_AHB1LPENR register *************/
+#define RCC_AHB1LPENR_GPIOALPEN 0x00000001U
+#define RCC_AHB1LPENR_GPIOBLPEN 0x00000002U
+#define RCC_AHB1LPENR_GPIOCLPEN 0x00000004U
+#define RCC_AHB1LPENR_GPIODLPEN 0x00000008U
+#define RCC_AHB1LPENR_GPIOELPEN 0x00000010U
+#define RCC_AHB1LPENR_GPIOFLPEN 0x00000020U
+#define RCC_AHB1LPENR_GPIOGLPEN 0x00000040U
+#define RCC_AHB1LPENR_GPIOHLPEN 0x00000080U
+#define RCC_AHB1LPENR_GPIOILPEN 0x00000100U
+#define RCC_AHB1LPENR_GPIOJLPEN 0x00000200U
+#define RCC_AHB1LPENR_GPIOKLPEN 0x00000400U
+
+#define RCC_AHB1LPENR_CRCLPEN 0x00001000U
+#define RCC_AHB1LPENR_FLITFLPEN 0x00008000U
+#define RCC_AHB1LPENR_SRAM1LPEN 0x00010000U
+#define RCC_AHB1LPENR_SRAM2LPEN 0x00020000U
+#define RCC_AHB1LPENR_BKPSRAMLPEN 0x00040000U
+#define RCC_AHB1LPENR_SRAM3LPEN 0x00080000U
+#define RCC_AHB1LPENR_DMA1LPEN 0x00200000U
+#define RCC_AHB1LPENR_DMA2LPEN 0x00400000U
+#define RCC_AHB1LPENR_DMA2DLPEN 0x00800000U
+
+#define RCC_AHB1LPENR_ETHMACLPEN 0x02000000U
+#define RCC_AHB1LPENR_ETHMACTXLPEN 0x04000000U
+#define RCC_AHB1LPENR_ETHMACRXLPEN 0x08000000U
+#define RCC_AHB1LPENR_ETHMACPTPLPEN 0x10000000U
+#define RCC_AHB1LPENR_OTGHSLPEN 0x20000000U
+#define RCC_AHB1LPENR_OTGHSULPILPEN 0x40000000U
+
+/******************** Bit definition for RCC_AHB2LPENR register *************/
+#define RCC_AHB2LPENR_DCMILPEN 0x00000001U
+#define RCC_AHB2LPENR_RNGLPEN 0x00000040U
+#define RCC_AHB2LPENR_OTGFSLPEN 0x00000080U
+
+/******************** Bit definition for RCC_AHB3LPENR register *************/
+#define RCC_AHB3LPENR_FMCLPEN 0x00000001U
+#define RCC_AHB3LPENR_QSPILPEN 0x00000002U
+
+/******************** Bit definition for RCC_APB1LPENR register *************/
+#define RCC_APB1LPENR_TIM2LPEN 0x00000001U
+#define RCC_APB1LPENR_TIM3LPEN 0x00000002U
+#define RCC_APB1LPENR_TIM4LPEN 0x00000004U
+#define RCC_APB1LPENR_TIM5LPEN 0x00000008U
+#define RCC_APB1LPENR_TIM6LPEN 0x00000010U
+#define RCC_APB1LPENR_TIM7LPEN 0x00000020U
+#define RCC_APB1LPENR_TIM12LPEN 0x00000040U
+#define RCC_APB1LPENR_TIM13LPEN 0x00000080U
+#define RCC_APB1LPENR_TIM14LPEN 0x00000100U
+#define RCC_APB1LPENR_WWDGLPEN 0x00000800U
+#define RCC_APB1LPENR_SPI2LPEN 0x00004000U
+#define RCC_APB1LPENR_SPI3LPEN 0x00008000U
+#define RCC_APB1LPENR_USART2LPEN 0x00020000U
+#define RCC_APB1LPENR_USART3LPEN 0x00040000U
+#define RCC_APB1LPENR_UART4LPEN 0x00080000U
+#define RCC_APB1LPENR_UART5LPEN 0x00100000U
+#define RCC_APB1LPENR_I2C1LPEN 0x00200000U
+#define RCC_APB1LPENR_I2C2LPEN 0x00400000U
+#define RCC_APB1LPENR_I2C3LPEN 0x00800000U
+#define RCC_APB1LPENR_CAN1LPEN 0x02000000U
+#define RCC_APB1LPENR_CAN2LPEN 0x04000000U
+#define RCC_APB1LPENR_PWRLPEN 0x10000000U
+#define RCC_APB1LPENR_DACLPEN 0x20000000U
+#define RCC_APB1LPENR_UART7LPEN 0x40000000U
+#define RCC_APB1LPENR_UART8LPEN 0x80000000U
+
+/******************** Bit definition for RCC_APB2LPENR register *************/
+#define RCC_APB2LPENR_TIM1LPEN 0x00000001U
+#define RCC_APB2LPENR_TIM8LPEN 0x00000002U
+#define RCC_APB2LPENR_USART1LPEN 0x00000010U
+#define RCC_APB2LPENR_USART6LPEN 0x00000020U
+#define RCC_APB2LPENR_ADC1LPEN 0x00000100U
+#define RCC_APB2LPENR_ADC2LPEN 0x00000200U
+#define RCC_APB2LPENR_ADC3LPEN 0x00000400U
+#define RCC_APB2LPENR_SDIOLPEN 0x00000800U
+#define RCC_APB2LPENR_SPI1LPEN 0x00001000U
+#define RCC_APB2LPENR_SPI4LPEN 0x00002000U
+#define RCC_APB2LPENR_SYSCFGLPEN 0x00004000U
+#define RCC_APB2LPENR_TIM9LPEN 0x00010000U
+#define RCC_APB2LPENR_TIM10LPEN 0x00020000U
+#define RCC_APB2LPENR_TIM11LPEN 0x00040000U
+#define RCC_APB2LPENR_SPI5LPEN 0x00100000U
+#define RCC_APB2LPENR_SPI6LPEN 0x00200000U
+#define RCC_APB2LPENR_SAI1LPEN 0x00400000U
+#define RCC_APB2LPENR_LTDCLPEN 0x04000000U
+#define RCC_APB2LPENR_DSILPEN 0x08000000U
+
+/******************** Bit definition for RCC_BDCR register ******************/
+#define RCC_BDCR_LSEON 0x00000001U
+#define RCC_BDCR_LSERDY 0x00000002U
+#define RCC_BDCR_LSEBYP 0x00000004U
+#define RCC_BDCR_LSEMOD 0x00000008U
+
+#define RCC_BDCR_RTCSEL 0x00000300U
+#define RCC_BDCR_RTCSEL_0 0x00000100U
+#define RCC_BDCR_RTCSEL_1 0x00000200U
+
+#define RCC_BDCR_RTCEN 0x00008000U
+#define RCC_BDCR_BDRST 0x00010000U
+
+/******************** Bit definition for RCC_CSR register *******************/
+#define RCC_CSR_LSION 0x00000001U
+#define RCC_CSR_LSIRDY 0x00000002U
+#define RCC_CSR_RMVF 0x01000000U
+#define RCC_CSR_BORRSTF 0x02000000U
+#define RCC_CSR_PADRSTF 0x04000000U
+#define RCC_CSR_PORRSTF 0x08000000U
+#define RCC_CSR_SFTRSTF 0x10000000U
+#define RCC_CSR_WDGRSTF 0x20000000U
+#define RCC_CSR_WWDGRSTF 0x40000000U
+#define RCC_CSR_LPWRRSTF 0x80000000U
+
+/******************** Bit definition for RCC_SSCGR register *****************/
+#define RCC_SSCGR_MODPER 0x00001FFFU
+#define RCC_SSCGR_INCSTEP 0x0FFFE000U
+#define RCC_SSCGR_SPREADSEL 0x40000000U
+#define RCC_SSCGR_SSCGEN 0x80000000U
+
+/******************** Bit definition for RCC_PLLI2SCFGR register ************/
+#define RCC_PLLI2SCFGR_PLLI2SN 0x00007FC0U
+#define RCC_PLLI2SCFGR_PLLI2SN_0 0x00000040U
+#define RCC_PLLI2SCFGR_PLLI2SN_1 0x00000080U
+#define RCC_PLLI2SCFGR_PLLI2SN_2 0x00000100U
+#define RCC_PLLI2SCFGR_PLLI2SN_3 0x00000200U
+#define RCC_PLLI2SCFGR_PLLI2SN_4 0x00000400U
+#define RCC_PLLI2SCFGR_PLLI2SN_5 0x00000800U
+#define RCC_PLLI2SCFGR_PLLI2SN_6 0x00001000U
+#define RCC_PLLI2SCFGR_PLLI2SN_7 0x00002000U
+#define RCC_PLLI2SCFGR_PLLI2SN_8 0x00004000U
+
+#define RCC_PLLI2SCFGR_PLLI2SQ 0x0F000000U
+#define RCC_PLLI2SCFGR_PLLI2SQ_0 0x01000000U
+#define RCC_PLLI2SCFGR_PLLI2SQ_1 0x02000000U
+#define RCC_PLLI2SCFGR_PLLI2SQ_2 0x04000000U
+#define RCC_PLLI2SCFGR_PLLI2SQ_3 0x08000000U
+
+#define RCC_PLLI2SCFGR_PLLI2SR 0x70000000U
+#define RCC_PLLI2SCFGR_PLLI2SR_0 0x10000000U
+#define RCC_PLLI2SCFGR_PLLI2SR_1 0x20000000U
+#define RCC_PLLI2SCFGR_PLLI2SR_2 0x40000000U
+
+
+/******************** Bit definition for RCC_PLLSAICFGR register ************/
+#define RCC_PLLSAICFGR_PLLSAIN 0x00007FC0U
+#define RCC_PLLSAICFGR_PLLSAIN_0 0x00000040U
+#define RCC_PLLSAICFGR_PLLSAIN_1 0x00000080U
+#define RCC_PLLSAICFGR_PLLSAIN_2 0x00000100U
+#define RCC_PLLSAICFGR_PLLSAIN_3 0x00000200U
+#define RCC_PLLSAICFGR_PLLSAIN_4 0x00000400U
+#define RCC_PLLSAICFGR_PLLSAIN_5 0x00000800U
+#define RCC_PLLSAICFGR_PLLSAIN_6 0x00001000U
+#define RCC_PLLSAICFGR_PLLSAIN_7 0x00002000U
+#define RCC_PLLSAICFGR_PLLSAIN_8 0x00004000U
+
+#define RCC_PLLSAICFGR_PLLSAIP 0x00030000U
+#define RCC_PLLSAICFGR_PLLSAIP_0 0x00010000U
+#define RCC_PLLSAICFGR_PLLSAIP_1 0x00020000U
+
+#define RCC_PLLSAICFGR_PLLSAIQ 0x0F000000U
+#define RCC_PLLSAICFGR_PLLSAIQ_0 0x01000000U
+#define RCC_PLLSAICFGR_PLLSAIQ_1 0x02000000U
+#define RCC_PLLSAICFGR_PLLSAIQ_2 0x04000000U
+#define RCC_PLLSAICFGR_PLLSAIQ_3 0x08000000U
+
+#define RCC_PLLSAICFGR_PLLSAIR 0x70000000U
+#define RCC_PLLSAICFGR_PLLSAIR_0 0x10000000U
+#define RCC_PLLSAICFGR_PLLSAIR_1 0x20000000U
+#define RCC_PLLSAICFGR_PLLSAIR_2 0x40000000U
+
+/******************** Bit definition for RCC_DCKCFGR register ***************/
+#define RCC_DCKCFGR_PLLI2SDIVQ 0x0000001FU
+#define RCC_DCKCFGR_PLLSAIDIVQ 0x00001F00U
+#define RCC_DCKCFGR_PLLSAIDIVR 0x00030000U
+#define RCC_DCKCFGR_SAI1ASRC 0x00300000U
+#define RCC_DCKCFGR_SAI1ASRC_0 0x00100000U
+#define RCC_DCKCFGR_SAI1ASRC_1 0x00200000U
+#define RCC_DCKCFGR_SAI1BSRC 0x00C00000U
+#define RCC_DCKCFGR_SAI1BSRC_0 0x00400000U
+#define RCC_DCKCFGR_SAI1BSRC_1 0x00800000U
+#define RCC_DCKCFGR_TIMPRE 0x01000000U
+#define RCC_DCKCFGR_CK48MSEL 0x08000000U
+#define RCC_DCKCFGR_SDIOSEL 0x10000000U
+#define RCC_DCKCFGR_DSISEL 0x20000000U
+
+/******************************************************************************/
+/* */
+/* RNG */
+/* */
+/******************************************************************************/
+/******************** Bits definition for RNG_CR register *******************/
+#define RNG_CR_RNGEN 0x00000004U
+#define RNG_CR_IE 0x00000008U
+
+/******************** Bits definition for RNG_SR register *******************/
+#define RNG_SR_DRDY 0x00000001U
+#define RNG_SR_CECS 0x00000002U
+#define RNG_SR_SECS 0x00000004U
+#define RNG_SR_CEIS 0x00000020U
+#define RNG_SR_SEIS 0x00000040U
+
+/******************************************************************************/
+/* */
+/* Real-Time Clock (RTC) */
+/* */
+/******************************************************************************/
+/******************** Bits definition for RTC_TR register *******************/
+#define RTC_TR_PM 0x00400000U
+#define RTC_TR_HT 0x00300000U
+#define RTC_TR_HT_0 0x00100000U
+#define RTC_TR_HT_1 0x00200000U
+#define RTC_TR_HU 0x000F0000U
+#define RTC_TR_HU_0 0x00010000U
+#define RTC_TR_HU_1 0x00020000U
+#define RTC_TR_HU_2 0x00040000U
+#define RTC_TR_HU_3 0x00080000U
+#define RTC_TR_MNT 0x00007000U
+#define RTC_TR_MNT_0 0x00001000U
+#define RTC_TR_MNT_1 0x00002000U
+#define RTC_TR_MNT_2 0x00004000U
+#define RTC_TR_MNU 0x00000F00U
+#define RTC_TR_MNU_0 0x00000100U
+#define RTC_TR_MNU_1 0x00000200U
+#define RTC_TR_MNU_2 0x00000400U
+#define RTC_TR_MNU_3 0x00000800U
+#define RTC_TR_ST 0x00000070U
+#define RTC_TR_ST_0 0x00000010U
+#define RTC_TR_ST_1 0x00000020U
+#define RTC_TR_ST_2 0x00000040U
+#define RTC_TR_SU 0x0000000FU
+#define RTC_TR_SU_0 0x00000001U
+#define RTC_TR_SU_1 0x00000002U
+#define RTC_TR_SU_2 0x00000004U
+#define RTC_TR_SU_3 0x00000008U
+
+/******************** Bits definition for RTC_DR register *******************/
+#define RTC_DR_YT 0x00F00000U
+#define RTC_DR_YT_0 0x00100000U
+#define RTC_DR_YT_1 0x00200000U
+#define RTC_DR_YT_2 0x00400000U
+#define RTC_DR_YT_3 0x00800000U
+#define RTC_DR_YU 0x000F0000U
+#define RTC_DR_YU_0 0x00010000U
+#define RTC_DR_YU_1 0x00020000U
+#define RTC_DR_YU_2 0x00040000U
+#define RTC_DR_YU_3 0x00080000U
+#define RTC_DR_WDU 0x0000E000U
+#define RTC_DR_WDU_0 0x00002000U
+#define RTC_DR_WDU_1 0x00004000U
+#define RTC_DR_WDU_2 0x00008000U
+#define RTC_DR_MT 0x00001000U
+#define RTC_DR_MU 0x00000F00U
+#define RTC_DR_MU_0 0x00000100U
+#define RTC_DR_MU_1 0x00000200U
+#define RTC_DR_MU_2 0x00000400U
+#define RTC_DR_MU_3 0x00000800U
+#define RTC_DR_DT 0x00000030U
+#define RTC_DR_DT_0 0x00000010U
+#define RTC_DR_DT_1 0x00000020U
+#define RTC_DR_DU 0x0000000FU
+#define RTC_DR_DU_0 0x00000001U
+#define RTC_DR_DU_1 0x00000002U
+#define RTC_DR_DU_2 0x00000004U
+#define RTC_DR_DU_3 0x00000008U
+
+/******************** Bits definition for RTC_CR register *******************/
+#define RTC_CR_COE 0x00800000U
+#define RTC_CR_OSEL 0x00600000U
+#define RTC_CR_OSEL_0 0x00200000U
+#define RTC_CR_OSEL_1 0x00400000U
+#define RTC_CR_POL 0x00100000U
+#define RTC_CR_COSEL 0x00080000U
+#define RTC_CR_BCK 0x00040000U
+#define RTC_CR_SUB1H 0x00020000U
+#define RTC_CR_ADD1H 0x00010000U
+#define RTC_CR_TSIE 0x00008000U
+#define RTC_CR_WUTIE 0x00004000U
+#define RTC_CR_ALRBIE 0x00002000U
+#define RTC_CR_ALRAIE 0x00001000U
+#define RTC_CR_TSE 0x00000800U
+#define RTC_CR_WUTE 0x00000400U
+#define RTC_CR_ALRBE 0x00000200U
+#define RTC_CR_ALRAE 0x00000100U
+#define RTC_CR_DCE 0x00000080U
+#define RTC_CR_FMT 0x00000040U
+#define RTC_CR_BYPSHAD 0x00000020U
+#define RTC_CR_REFCKON 0x00000010U
+#define RTC_CR_TSEDGE 0x00000008U
+#define RTC_CR_WUCKSEL 0x00000007U
+#define RTC_CR_WUCKSEL_0 0x00000001U
+#define RTC_CR_WUCKSEL_1 0x00000002U
+#define RTC_CR_WUCKSEL_2 0x00000004U
+
+/******************** Bits definition for RTC_ISR register ******************/
+#define RTC_ISR_RECALPF 0x00010000U
+#define RTC_ISR_TAMP1F 0x00002000U
+#define RTC_ISR_TAMP2F 0x00004000U
+#define RTC_ISR_TSOVF 0x00001000U
+#define RTC_ISR_TSF 0x00000800U
+#define RTC_ISR_WUTF 0x00000400U
+#define RTC_ISR_ALRBF 0x00000200U
+#define RTC_ISR_ALRAF 0x00000100U
+#define RTC_ISR_INIT 0x00000080U
+#define RTC_ISR_INITF 0x00000040U
+#define RTC_ISR_RSF 0x00000020U
+#define RTC_ISR_INITS 0x00000010U
+#define RTC_ISR_SHPF 0x00000008U
+#define RTC_ISR_WUTWF 0x00000004U
+#define RTC_ISR_ALRBWF 0x00000002U
+#define RTC_ISR_ALRAWF 0x00000001U
+
+/******************** Bits definition for RTC_PRER register *****************/
+#define RTC_PRER_PREDIV_A 0x007F0000U
+#define RTC_PRER_PREDIV_S 0x00007FFFU
+
+/******************** Bits definition for RTC_WUTR register *****************/
+#define RTC_WUTR_WUT 0x0000FFFFU
+
+/******************** Bits definition for RTC_CALIBR register ***************/
+#define RTC_CALIBR_DCS 0x00000080U
+#define RTC_CALIBR_DC 0x0000001FU
+
+/******************** Bits definition for RTC_ALRMAR register ***************/
+#define RTC_ALRMAR_MSK4 0x80000000U
+#define RTC_ALRMAR_WDSEL 0x40000000U
+#define RTC_ALRMAR_DT 0x30000000U
+#define RTC_ALRMAR_DT_0 0x10000000U
+#define RTC_ALRMAR_DT_1 0x20000000U
+#define RTC_ALRMAR_DU 0x0F000000U
+#define RTC_ALRMAR_DU_0 0x01000000U
+#define RTC_ALRMAR_DU_1 0x02000000U
+#define RTC_ALRMAR_DU_2 0x04000000U
+#define RTC_ALRMAR_DU_3 0x08000000U
+#define RTC_ALRMAR_MSK3 0x00800000U
+#define RTC_ALRMAR_PM 0x00400000U
+#define RTC_ALRMAR_HT 0x00300000U
+#define RTC_ALRMAR_HT_0 0x00100000U
+#define RTC_ALRMAR_HT_1 0x00200000U
+#define RTC_ALRMAR_HU 0x000F0000U
+#define RTC_ALRMAR_HU_0 0x00010000U
+#define RTC_ALRMAR_HU_1 0x00020000U
+#define RTC_ALRMAR_HU_2 0x00040000U
+#define RTC_ALRMAR_HU_3 0x00080000U
+#define RTC_ALRMAR_MSK2 0x00008000U
+#define RTC_ALRMAR_MNT 0x00007000U
+#define RTC_ALRMAR_MNT_0 0x00001000U
+#define RTC_ALRMAR_MNT_1 0x00002000U
+#define RTC_ALRMAR_MNT_2 0x00004000U
+#define RTC_ALRMAR_MNU 0x00000F00U
+#define RTC_ALRMAR_MNU_0 0x00000100U
+#define RTC_ALRMAR_MNU_1 0x00000200U
+#define RTC_ALRMAR_MNU_2 0x00000400U
+#define RTC_ALRMAR_MNU_3 0x00000800U
+#define RTC_ALRMAR_MSK1 0x00000080U
+#define RTC_ALRMAR_ST 0x00000070U
+#define RTC_ALRMAR_ST_0 0x00000010U
+#define RTC_ALRMAR_ST_1 0x00000020U
+#define RTC_ALRMAR_ST_2 0x00000040U
+#define RTC_ALRMAR_SU 0x0000000FU
+#define RTC_ALRMAR_SU_0 0x00000001U
+#define RTC_ALRMAR_SU_1 0x00000002U
+#define RTC_ALRMAR_SU_2 0x00000004U
+#define RTC_ALRMAR_SU_3 0x00000008U
+
+/******************** Bits definition for RTC_ALRMBR register ***************/
+#define RTC_ALRMBR_MSK4 0x80000000U
+#define RTC_ALRMBR_WDSEL 0x40000000U
+#define RTC_ALRMBR_DT 0x30000000U
+#define RTC_ALRMBR_DT_0 0x10000000U
+#define RTC_ALRMBR_DT_1 0x20000000U
+#define RTC_ALRMBR_DU 0x0F000000U
+#define RTC_ALRMBR_DU_0 0x01000000U
+#define RTC_ALRMBR_DU_1 0x02000000U
+#define RTC_ALRMBR_DU_2 0x04000000U
+#define RTC_ALRMBR_DU_3 0x08000000U
+#define RTC_ALRMBR_MSK3 0x00800000U
+#define RTC_ALRMBR_PM 0x00400000U
+#define RTC_ALRMBR_HT 0x00300000U
+#define RTC_ALRMBR_HT_0 0x00100000U
+#define RTC_ALRMBR_HT_1 0x00200000U
+#define RTC_ALRMBR_HU 0x000F0000U
+#define RTC_ALRMBR_HU_0 0x00010000U
+#define RTC_ALRMBR_HU_1 0x00020000U
+#define RTC_ALRMBR_HU_2 0x00040000U
+#define RTC_ALRMBR_HU_3 0x00080000U
+#define RTC_ALRMBR_MSK2 0x00008000U
+#define RTC_ALRMBR_MNT 0x00007000U
+#define RTC_ALRMBR_MNT_0 0x00001000U
+#define RTC_ALRMBR_MNT_1 0x00002000U
+#define RTC_ALRMBR_MNT_2 0x00004000U
+#define RTC_ALRMBR_MNU 0x00000F00U
+#define RTC_ALRMBR_MNU_0 0x00000100U
+#define RTC_ALRMBR_MNU_1 0x00000200U
+#define RTC_ALRMBR_MNU_2 0x00000400U
+#define RTC_ALRMBR_MNU_3 0x00000800U
+#define RTC_ALRMBR_MSK1 0x00000080U
+#define RTC_ALRMBR_ST 0x00000070U
+#define RTC_ALRMBR_ST_0 0x00000010U
+#define RTC_ALRMBR_ST_1 0x00000020U
+#define RTC_ALRMBR_ST_2 0x00000040U
+#define RTC_ALRMBR_SU 0x0000000FU
+#define RTC_ALRMBR_SU_0 0x00000001U
+#define RTC_ALRMBR_SU_1 0x00000002U
+#define RTC_ALRMBR_SU_2 0x00000004U
+#define RTC_ALRMBR_SU_3 0x00000008U
+
+/******************** Bits definition for RTC_WPR register ******************/
+#define RTC_WPR_KEY 0x000000FFU
+
+/******************** Bits definition for RTC_SSR register ******************/
+#define RTC_SSR_SS 0x0000FFFFU
+
+/******************** Bits definition for RTC_SHIFTR register ***************/
+#define RTC_SHIFTR_SUBFS 0x00007FFFU
+#define RTC_SHIFTR_ADD1S 0x80000000U
+
+/******************** Bits definition for RTC_TSTR register *****************/
+#define RTC_TSTR_PM 0x00400000U
+#define RTC_TSTR_HT 0x00300000U
+#define RTC_TSTR_HT_0 0x00100000U
+#define RTC_TSTR_HT_1 0x00200000U
+#define RTC_TSTR_HU 0x000F0000U
+#define RTC_TSTR_HU_0 0x00010000U
+#define RTC_TSTR_HU_1 0x00020000U
+#define RTC_TSTR_HU_2 0x00040000U
+#define RTC_TSTR_HU_3 0x00080000U
+#define RTC_TSTR_MNT 0x00007000U
+#define RTC_TSTR_MNT_0 0x00001000U
+#define RTC_TSTR_MNT_1 0x00002000U
+#define RTC_TSTR_MNT_2 0x00004000U
+#define RTC_TSTR_MNU 0x00000F00U
+#define RTC_TSTR_MNU_0 0x00000100U
+#define RTC_TSTR_MNU_1 0x00000200U
+#define RTC_TSTR_MNU_2 0x00000400U
+#define RTC_TSTR_MNU_3 0x00000800U
+#define RTC_TSTR_ST 0x00000070U
+#define RTC_TSTR_ST_0 0x00000010U
+#define RTC_TSTR_ST_1 0x00000020U
+#define RTC_TSTR_ST_2 0x00000040U
+#define RTC_TSTR_SU 0x0000000FU
+#define RTC_TSTR_SU_0 0x00000001U
+#define RTC_TSTR_SU_1 0x00000002U
+#define RTC_TSTR_SU_2 0x00000004U
+#define RTC_TSTR_SU_3 0x00000008U
+
+/******************** Bits definition for RTC_TSDR register *****************/
+#define RTC_TSDR_WDU 0x0000E000U
+#define RTC_TSDR_WDU_0 0x00002000U
+#define RTC_TSDR_WDU_1 0x00004000U
+#define RTC_TSDR_WDU_2 0x00008000U
+#define RTC_TSDR_MT 0x00001000U
+#define RTC_TSDR_MU 0x00000F00U
+#define RTC_TSDR_MU_0 0x00000100U
+#define RTC_TSDR_MU_1 0x00000200U
+#define RTC_TSDR_MU_2 0x00000400U
+#define RTC_TSDR_MU_3 0x00000800U
+#define RTC_TSDR_DT 0x00000030U
+#define RTC_TSDR_DT_0 0x00000010U
+#define RTC_TSDR_DT_1 0x00000020U
+#define RTC_TSDR_DU 0x0000000FU
+#define RTC_TSDR_DU_0 0x00000001U
+#define RTC_TSDR_DU_1 0x00000002U
+#define RTC_TSDR_DU_2 0x00000004U
+#define RTC_TSDR_DU_3 0x00000008U
+
+/******************** Bits definition for RTC_TSSSR register ****************/
+#define RTC_TSSSR_SS 0x0000FFFFU
+
+/******************** Bits definition for RTC_CAL register *****************/
+#define RTC_CALR_CALP 0x00008000U
+#define RTC_CALR_CALW8 0x00004000U
+#define RTC_CALR_CALW16 0x00002000U
+#define RTC_CALR_CALM 0x000001FFU
+#define RTC_CALR_CALM_0 0x00000001U
+#define RTC_CALR_CALM_1 0x00000002U
+#define RTC_CALR_CALM_2 0x00000004U
+#define RTC_CALR_CALM_3 0x00000008U
+#define RTC_CALR_CALM_4 0x00000010U
+#define RTC_CALR_CALM_5 0x00000020U
+#define RTC_CALR_CALM_6 0x00000040U
+#define RTC_CALR_CALM_7 0x00000080U
+#define RTC_CALR_CALM_8 0x00000100U
+
+/******************** Bits definition for RTC_TAFCR register ****************/
+#define RTC_TAFCR_ALARMOUTTYPE 0x00040000U
+#define RTC_TAFCR_TSINSEL 0x00020000U
+#define RTC_TAFCR_TAMPINSEL 0x00010000U
+#define RTC_TAFCR_TAMPPUDIS 0x00008000U
+#define RTC_TAFCR_TAMPPRCH 0x00006000U
+#define RTC_TAFCR_TAMPPRCH_0 0x00002000U
+#define RTC_TAFCR_TAMPPRCH_1 0x00004000U
+#define RTC_TAFCR_TAMPFLT 0x00001800U
+#define RTC_TAFCR_TAMPFLT_0 0x00000800U
+#define RTC_TAFCR_TAMPFLT_1 0x00001000U
+#define RTC_TAFCR_TAMPFREQ 0x00000700U
+#define RTC_TAFCR_TAMPFREQ_0 0x00000100U
+#define RTC_TAFCR_TAMPFREQ_1 0x00000200U
+#define RTC_TAFCR_TAMPFREQ_2 0x00000400U
+#define RTC_TAFCR_TAMPTS 0x00000080U
+#define RTC_TAFCR_TAMP2TRG 0x00000010U
+#define RTC_TAFCR_TAMP2E 0x00000008U
+#define RTC_TAFCR_TAMPIE 0x00000004U
+#define RTC_TAFCR_TAMP1TRG 0x00000002U
+#define RTC_TAFCR_TAMP1E 0x00000001U
+
+/******************** Bits definition for RTC_ALRMASSR register *************/
+#define RTC_ALRMASSR_MASKSS 0x0F000000U
+#define RTC_ALRMASSR_MASKSS_0 0x01000000U
+#define RTC_ALRMASSR_MASKSS_1 0x02000000U
+#define RTC_ALRMASSR_MASKSS_2 0x04000000U
+#define RTC_ALRMASSR_MASKSS_3 0x08000000U
+#define RTC_ALRMASSR_SS 0x00007FFFU
+
+/******************** Bits definition for RTC_ALRMBSSR register *************/
+#define RTC_ALRMBSSR_MASKSS 0x0F000000U
+#define RTC_ALRMBSSR_MASKSS_0 0x01000000U
+#define RTC_ALRMBSSR_MASKSS_1 0x02000000U
+#define RTC_ALRMBSSR_MASKSS_2 0x04000000U
+#define RTC_ALRMBSSR_MASKSS_3 0x08000000U
+#define RTC_ALRMBSSR_SS 0x00007FFFU
+
+/******************** Bits definition for RTC_BKP0R register ****************/
+#define RTC_BKP0R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP1R register ****************/
+#define RTC_BKP1R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP2R register ****************/
+#define RTC_BKP2R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP3R register ****************/
+#define RTC_BKP3R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP4R register ****************/
+#define RTC_BKP4R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP5R register ****************/
+#define RTC_BKP5R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP6R register ****************/
+#define RTC_BKP6R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP7R register ****************/
+#define RTC_BKP7R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP8R register ****************/
+#define RTC_BKP8R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP9R register ****************/
+#define RTC_BKP9R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP10R register ***************/
+#define RTC_BKP10R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP11R register ***************/
+#define RTC_BKP11R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP12R register ***************/
+#define RTC_BKP12R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP13R register ***************/
+#define RTC_BKP13R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP14R register ***************/
+#define RTC_BKP14R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP15R register ***************/
+#define RTC_BKP15R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP16R register ***************/
+#define RTC_BKP16R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP17R register ***************/
+#define RTC_BKP17R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP18R register ***************/
+#define RTC_BKP18R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP19R register ***************/
+#define RTC_BKP19R 0xFFFFFFFFU
+
+/******************************************************************************/
+/* */
+/* Serial Audio Interface */
+/* */
+/******************************************************************************/
+/******************** Bit definition for SAI_GCR register *******************/
+#define SAI_GCR_SYNCIN 0x00000003U /*!<SYNCIN[1:0] bits (Synchronization Inputs) */
+#define SAI_GCR_SYNCIN_0 0x00000001U /*!<Bit 0 */
+#define SAI_GCR_SYNCIN_1 0x00000002U /*!<Bit 1 */
+
+#define SAI_GCR_SYNCOUT 0x00000030U /*!<SYNCOUT[1:0] bits (Synchronization Outputs) */
+#define SAI_GCR_SYNCOUT_0 0x00000010U /*!<Bit 0 */
+#define SAI_GCR_SYNCOUT_1 0x00000020U /*!<Bit 1 */
+
+/******************* Bit definition for SAI_xCR1 register *******************/
+#define SAI_xCR1_MODE 0x00000003U /*!<MODE[1:0] bits (Audio Block Mode) */
+#define SAI_xCR1_MODE_0 0x00000001U /*!<Bit 0 */
+#define SAI_xCR1_MODE_1 0x00000002U /*!<Bit 1 */
+
+#define SAI_xCR1_PRTCFG 0x0000000CU /*!<PRTCFG[1:0] bits (Protocol Configuration) */
+#define SAI_xCR1_PRTCFG_0 0x00000004U /*!<Bit 0 */
+#define SAI_xCR1_PRTCFG_1 0x00000008U /*!<Bit 1 */
+
+#define SAI_xCR1_DS 0x000000E0U /*!<DS[1:0] bits (Data Size) */
+#define SAI_xCR1_DS_0 0x00000020U /*!<Bit 0 */
+#define SAI_xCR1_DS_1 0x00000040U /*!<Bit 1 */
+#define SAI_xCR1_DS_2 0x00000080U /*!<Bit 2 */
+
+#define SAI_xCR1_LSBFIRST 0x00000100U /*!<LSB First Configuration */
+#define SAI_xCR1_CKSTR 0x00000200U /*!<ClocK STRobing edge */
+
+#define SAI_xCR1_SYNCEN 0x00000C00U /*!<SYNCEN[1:0](SYNChronization ENable) */
+#define SAI_xCR1_SYNCEN_0 0x00000400U /*!<Bit 0 */
+#define SAI_xCR1_SYNCEN_1 0x00000800U /*!<Bit 1 */
+
+#define SAI_xCR1_MONO 0x00001000U /*!<Mono mode */
+#define SAI_xCR1_OUTDRIV 0x00002000U /*!<Output Drive */
+#define SAI_xCR1_SAIEN 0x00010000U /*!<Audio Block enable */
+#define SAI_xCR1_DMAEN 0x00020000U /*!<DMA enable */
+#define SAI_xCR1_NODIV 0x00080000U /*!<No Divider Configuration */
+
+#define SAI_xCR1_MCKDIV 0x00F00000U /*!<MCKDIV[3:0] (Master ClocK Divider) */
+#define SAI_xCR1_MCKDIV_0 0x00100000U /*!<Bit 0 */
+#define SAI_xCR1_MCKDIV_1 0x00200000U /*!<Bit 1 */
+#define SAI_xCR1_MCKDIV_2 0x00400000U /*!<Bit 2 */
+#define SAI_xCR1_MCKDIV_3 0x00800000U /*!<Bit 3 */
+
+/******************* Bit definition for SAI_xCR2 register *******************/
+#define SAI_xCR2_FTH 0x00000007U /*!<FTH[2:0](Fifo THreshold) */
+#define SAI_xCR2_FTH_0 0x00000001U /*!<Bit 0 */
+#define SAI_xCR2_FTH_1 0x00000002U /*!<Bit 1 */
+#define SAI_xCR2_FTH_2 0x00000004U /*!<Bit 2 */
+
+#define SAI_xCR2_FFLUSH 0x00000008U /*!<Fifo FLUSH */
+#define SAI_xCR2_TRIS 0x00000010U /*!<TRIState Management on data line */
+#define SAI_xCR2_MUTE 0x00000020U /*!<Mute mode */
+#define SAI_xCR2_MUTEVAL 0x00000040U /*!<Muate value */
+
+#define SAI_xCR2_MUTECNT 0x00001F80U /*!<MUTECNT[5:0] (MUTE counter) */
+#define SAI_xCR2_MUTECNT_0 0x00000080U /*!<Bit 0 */
+#define SAI_xCR2_MUTECNT_1 0x00000100U /*!<Bit 1 */
+#define SAI_xCR2_MUTECNT_2 0x00000200U /*!<Bit 2 */
+#define SAI_xCR2_MUTECNT_3 0x00000400U /*!<Bit 3 */
+#define SAI_xCR2_MUTECNT_4 0x00000800U /*!<Bit 4 */
+#define SAI_xCR2_MUTECNT_5 0x00001000U /*!<Bit 5 */
+
+#define SAI_xCR2_CPL 0x00002000U /*!< Complement Bit */
+
+#define SAI_xCR2_COMP 0x0000C000U /*!<COMP[1:0] (Companding mode) */
+#define SAI_xCR2_COMP_0 0x00004000U /*!<Bit 0 */
+#define SAI_xCR2_COMP_1 0x00008000U /*!<Bit 1 */
+
+/****************** Bit definition for SAI_xFRCR register *******************/
+#define SAI_xFRCR_FRL 0x000000FFU /*!<FRL[1:0](Frame length) */
+#define SAI_xFRCR_FRL_0 0x00000001U /*!<Bit 0 */
+#define SAI_xFRCR_FRL_1 0x00000002U /*!<Bit 1 */
+#define SAI_xFRCR_FRL_2 0x00000004U /*!<Bit 2 */
+#define SAI_xFRCR_FRL_3 0x00000008U /*!<Bit 3 */
+#define SAI_xFRCR_FRL_4 0x00000010U /*!<Bit 4 */
+#define SAI_xFRCR_FRL_5 0x00000020U /*!<Bit 5 */
+#define SAI_xFRCR_FRL_6 0x00000040U /*!<Bit 6 */
+#define SAI_xFRCR_FRL_7 0x00000080U /*!<Bit 7 */
+
+#define SAI_xFRCR_FSALL 0x00007F00U /*!<FRL[1:0] (Frame synchronization active level length) */
+#define SAI_xFRCR_FSALL_0 0x00000100U /*!<Bit 0 */
+#define SAI_xFRCR_FSALL_1 0x00000200U /*!<Bit 1 */
+#define SAI_xFRCR_FSALL_2 0x00000400U /*!<Bit 2 */
+#define SAI_xFRCR_FSALL_3 0x00000800U /*!<Bit 3 */
+#define SAI_xFRCR_FSALL_4 0x00001000U /*!<Bit 4 */
+#define SAI_xFRCR_FSALL_5 0x00002000U /*!<Bit 5 */
+#define SAI_xFRCR_FSALL_6 0x00004000U /*!<Bit 6 */
+
+#define SAI_xFRCR_FSDEF 0x00010000U /*!< Frame Synchronization Definition */
+#define SAI_xFRCR_FSPOL 0x00020000U /*!<Frame Synchronization POLarity */
+#define SAI_xFRCR_FSOFF 0x00040000U /*!<Frame Synchronization OFFset */
+/* Legacy defines */
+#define SAI_xFRCR_FSPO SAI_xFRCR_FSPOL
+
+/****************** Bit definition for SAI_xSLOTR register *******************/
+#define SAI_xSLOTR_FBOFF 0x0000001FU /*!<FRL[4:0](First Bit Offset) */
+#define SAI_xSLOTR_FBOFF_0 0x00000001U /*!<Bit 0 */
+#define SAI_xSLOTR_FBOFF_1 0x00000002U /*!<Bit 1 */
+#define SAI_xSLOTR_FBOFF_2 0x00000004U /*!<Bit 2 */
+#define SAI_xSLOTR_FBOFF_3 0x00000008U /*!<Bit 3 */
+#define SAI_xSLOTR_FBOFF_4 0x00000010U /*!<Bit 4 */
+
+#define SAI_xSLOTR_SLOTSZ 0x000000C0U /*!<SLOTSZ[1:0] (Slot size) */
+#define SAI_xSLOTR_SLOTSZ_0 0x00000040U /*!<Bit 0 */
+#define SAI_xSLOTR_SLOTSZ_1 0x00000080U /*!<Bit 1 */
+
+#define SAI_xSLOTR_NBSLOT 0x00000F00U /*!<NBSLOT[3:0] (Number of Slot in audio Frame) */
+#define SAI_xSLOTR_NBSLOT_0 0x00000100U /*!<Bit 0 */
+#define SAI_xSLOTR_NBSLOT_1 0x00000200U /*!<Bit 1 */
+#define SAI_xSLOTR_NBSLOT_2 0x00000400U /*!<Bit 2 */
+#define SAI_xSLOTR_NBSLOT_3 0x00000800U /*!<Bit 3 */
+
+#define SAI_xSLOTR_SLOTEN 0xFFFF0000U /*!<SLOTEN[15:0] (Slot Enable) */
+
+/******************* Bit definition for SAI_xIMR register *******************/
+#define SAI_xIMR_OVRUDRIE 0x00000001U /*!<Overrun underrun interrupt enable */
+#define SAI_xIMR_MUTEDETIE 0x00000002U /*!<Mute detection interrupt enable */
+#define SAI_xIMR_WCKCFGIE 0x00000004U /*!<Wrong Clock Configuration interrupt enable */
+#define SAI_xIMR_FREQIE 0x00000008U /*!<FIFO request interrupt enable */
+#define SAI_xIMR_CNRDYIE 0x00000010U /*!<Codec not ready interrupt enable */
+#define SAI_xIMR_AFSDETIE 0x00000020U /*!<Anticipated frame synchronization detection interrupt enable */
+#define SAI_xIMR_LFSDETIE 0x00000040U /*!<Late frame synchronization detection interrupt enable */
+
+/******************** Bit definition for SAI_xSR register *******************/
+#define SAI_xSR_OVRUDR 0x00000001U /*!<Overrun underrun */
+#define SAI_xSR_MUTEDET 0x00000002U /*!<Mute detection */
+#define SAI_xSR_WCKCFG 0x00000004U /*!<Wrong Clock Configuration */
+#define SAI_xSR_FREQ 0x00000008U /*!<FIFO request */
+#define SAI_xSR_CNRDY 0x00000010U /*!<Codec not ready */
+#define SAI_xSR_AFSDET 0x00000020U /*!<Anticipated frame synchronization detection */
+#define SAI_xSR_LFSDET 0x00000040U /*!<Late frame synchronization detection */
+
+#define SAI_xSR_FLVL 0x00070000U /*!<FLVL[2:0] (FIFO Level Threshold) */
+#define SAI_xSR_FLVL_0 0x00010000U /*!<Bit 0 */
+#define SAI_xSR_FLVL_1 0x00020000U /*!<Bit 1 */
+#define SAI_xSR_FLVL_2 0x00040000U /*!<Bit 2 */
+
+/****************** Bit definition for SAI_xCLRFR register ******************/
+#define SAI_xCLRFR_COVRUDR 0x00000001U /*!<Clear Overrun underrun */
+#define SAI_xCLRFR_CMUTEDET 0x00000002U /*!<Clear Mute detection */
+#define SAI_xCLRFR_CWCKCFG 0x00000004U /*!<Clear Wrong Clock Configuration */
+#define SAI_xCLRFR_CFREQ 0x00000008U /*!<Clear FIFO request */
+#define SAI_xCLRFR_CCNRDY 0x00000010U /*!<Clear Codec not ready */
+#define SAI_xCLRFR_CAFSDET 0x00000020U /*!<Clear Anticipated frame synchronization detection */
+#define SAI_xCLRFR_CLFSDET 0x00000040U /*!<Clear Late frame synchronization detection */
+
+/****************** Bit definition for SAI_xDR register ******************/
+#define SAI_xDR_DATA 0xFFFFFFFFU
+
+
+/******************************************************************************/
+/* */
+/* SD host Interface */
+/* */
+/******************************************************************************/
+/****************** Bit definition for SDIO_POWER register ******************/
+#define SDIO_POWER_PWRCTRL 0x03U /*!<PWRCTRL[1:0] bits (Power supply control bits) */
+#define SDIO_POWER_PWRCTRL_0 0x01U /*!<Bit 0 */
+#define SDIO_POWER_PWRCTRL_1 0x02U /*!<Bit 1 */
+
+/****************** Bit definition for SDIO_CLKCR register ******************/
+#define SDIO_CLKCR_CLKDIV 0x00FFU /*!<Clock divide factor */
+#define SDIO_CLKCR_CLKEN 0x0100U /*!<Clock enable bit */
+#define SDIO_CLKCR_PWRSAV 0x0200U /*!<Power saving configuration bit */
+#define SDIO_CLKCR_BYPASS 0x0400U /*!<Clock divider bypass enable bit */
+
+#define SDIO_CLKCR_WIDBUS 0x1800U /*!<WIDBUS[1:0] bits (Wide bus mode enable bit) */
+#define SDIO_CLKCR_WIDBUS_0 0x0800U /*!<Bit 0 */
+#define SDIO_CLKCR_WIDBUS_1 0x1000U /*!<Bit 1 */
+
+#define SDIO_CLKCR_NEGEDGE 0x2000U /*!<SDIO_CK dephasing selection bit */
+#define SDIO_CLKCR_HWFC_EN 0x4000U /*!<HW Flow Control enable */
+
+/******************* Bit definition for SDIO_ARG register *******************/
+#define SDIO_ARG_CMDARG 0xFFFFFFFFU /*!<Command argument */
+
+/******************* Bit definition for SDIO_CMD register *******************/
+#define SDIO_CMD_CMDINDEX 0x003FU /*!<Command Index */
+
+#define SDIO_CMD_WAITRESP 0x00C0U /*!<WAITRESP[1:0] bits (Wait for response bits) */
+#define SDIO_CMD_WAITRESP_0 0x0040U /*!< Bit 0 */
+#define SDIO_CMD_WAITRESP_1 0x0080U /*!< Bit 1 */
+
+#define SDIO_CMD_WAITINT 0x0100U /*!<CPSM Waits for Interrupt Request */
+#define SDIO_CMD_WAITPEND 0x0200U /*!<CPSM Waits for ends of data transfer (CmdPend internal signal) */
+#define SDIO_CMD_CPSMEN 0x0400U /*!<Command path state machine (CPSM) Enable bit */
+#define SDIO_CMD_SDIOSUSPEND 0x0800U /*!<SD I/O suspend command */
+
+/***************** Bit definition for SDIO_RESPCMD register *****************/
+#define SDIO_RESPCMD_RESPCMD 0x3FU /*!<Response command index */
+
+/****************** Bit definition for SDIO_RESP0 register ******************/
+#define SDIO_RESP0_CARDSTATUS0 0xFFFFFFFFU /*!<Card Status */
+
+/****************** Bit definition for SDIO_RESP1 register ******************/
+#define SDIO_RESP1_CARDSTATUS1 0xFFFFFFFFU /*!<Card Status */
+
+/****************** Bit definition for SDIO_RESP2 register ******************/
+#define SDIO_RESP2_CARDSTATUS2 0xFFFFFFFFU /*!<Card Status */
+
+/****************** Bit definition for SDIO_RESP3 register ******************/
+#define SDIO_RESP3_CARDSTATUS3 0xFFFFFFFFU /*!<Card Status */
+
+/****************** Bit definition for SDIO_RESP4 register ******************/
+#define SDIO_RESP4_CARDSTATUS4 0xFFFFFFFFU /*!<Card Status */
+
+/****************** Bit definition for SDIO_DTIMER register *****************/
+#define SDIO_DTIMER_DATATIME 0xFFFFFFFFU /*!<Data timeout period. */
+
+/****************** Bit definition for SDIO_DLEN register *******************/
+#define SDIO_DLEN_DATALENGTH 0x01FFFFFFU /*!<Data length value */
+
+/****************** Bit definition for SDIO_DCTRL register ******************/
+#define SDIO_DCTRL_DTEN 0x0001U /*!<Data transfer enabled bit */
+#define SDIO_DCTRL_DTDIR 0x0002U /*!<Data transfer direction selection */
+#define SDIO_DCTRL_DTMODE 0x0004U /*!<Data transfer mode selection */
+#define SDIO_DCTRL_DMAEN 0x0008U /*!<DMA enabled bit */
+
+#define SDIO_DCTRL_DBLOCKSIZE 0x00F0U /*!<DBLOCKSIZE[3:0] bits (Data block size) */
+#define SDIO_DCTRL_DBLOCKSIZE_0 0x0010U /*!<Bit 0 */
+#define SDIO_DCTRL_DBLOCKSIZE_1 0x0020U /*!<Bit 1 */
+#define SDIO_DCTRL_DBLOCKSIZE_2 0x0040U /*!<Bit 2 */
+#define SDIO_DCTRL_DBLOCKSIZE_3 0x0080U /*!<Bit 3 */
+
+#define SDIO_DCTRL_RWSTART 0x0100U /*!<Read wait start */
+#define SDIO_DCTRL_RWSTOP 0x0200U /*!<Read wait stop */
+#define SDIO_DCTRL_RWMOD 0x0400U /*!<Read wait mode */
+#define SDIO_DCTRL_SDIOEN 0x0800U /*!<SD I/O enable functions */
+
+/****************** Bit definition for SDIO_DCOUNT register *****************/
+#define SDIO_DCOUNT_DATACOUNT 0x01FFFFFFU /*!<Data count value */
+
+/****************** Bit definition for SDIO_STA register ********************/
+#define SDIO_STA_CCRCFAIL 0x00000001U /*!<Command response received (CRC check failed) */
+#define SDIO_STA_DCRCFAIL 0x00000002U /*!<Data block sent/received (CRC check failed) */
+#define SDIO_STA_CTIMEOUT 0x00000004U /*!<Command response timeout */
+#define SDIO_STA_DTIMEOUT 0x00000008U /*!<Data timeout */
+#define SDIO_STA_TXUNDERR 0x00000010U /*!<Transmit FIFO underrun error */
+#define SDIO_STA_RXOVERR 0x00000020U /*!<Received FIFO overrun error */
+#define SDIO_STA_CMDREND 0x00000040U /*!<Command response received (CRC check passed) */
+#define SDIO_STA_CMDSENT 0x00000080U /*!<Command sent (no response required) */
+#define SDIO_STA_DATAEND 0x00000100U /*!<Data end (data counter, SDIDCOUNT, is zero) */
+#define SDIO_STA_DBCKEND 0x00000400U /*!<Data block sent/received (CRC check passed) */
+#define SDIO_STA_CMDACT 0x00000800U /*!<Command transfer in progress */
+#define SDIO_STA_TXACT 0x00001000U /*!<Data transmit in progress */
+#define SDIO_STA_RXACT 0x00002000U /*!<Data receive in progress */
+#define SDIO_STA_TXFIFOHE 0x00004000U /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
+#define SDIO_STA_RXFIFOHF 0x00008000U /*!<Receive FIFO Half Full: there are at least 8 words in the FIFO */
+#define SDIO_STA_TXFIFOF 0x00010000U /*!<Transmit FIFO full */
+#define SDIO_STA_RXFIFOF 0x00020000U /*!<Receive FIFO full */
+#define SDIO_STA_TXFIFOE 0x00040000U /*!<Transmit FIFO empty */
+#define SDIO_STA_RXFIFOE 0x00080000U /*!<Receive FIFO empty */
+#define SDIO_STA_TXDAVL 0x00100000U /*!<Data available in transmit FIFO */
+#define SDIO_STA_RXDAVL 0x00200000U /*!<Data available in receive FIFO */
+#define SDIO_STA_SDIOIT 0x00400000U /*!<SDIO interrupt received */
+
+/******************* Bit definition for SDIO_ICR register *******************/
+#define SDIO_ICR_CCRCFAILC 0x00000001U /*!<CCRCFAIL flag clear bit */
+#define SDIO_ICR_DCRCFAILC 0x00000002U /*!<DCRCFAIL flag clear bit */
+#define SDIO_ICR_CTIMEOUTC 0x00000004U /*!<CTIMEOUT flag clear bit */
+#define SDIO_ICR_DTIMEOUTC 0x00000008U /*!<DTIMEOUT flag clear bit */
+#define SDIO_ICR_TXUNDERRC 0x00000010U /*!<TXUNDERR flag clear bit */
+#define SDIO_ICR_RXOVERRC 0x00000020U /*!<RXOVERR flag clear bit */
+#define SDIO_ICR_CMDRENDC 0x00000040U /*!<CMDREND flag clear bit */
+#define SDIO_ICR_CMDSENTC 0x00000080U /*!<CMDSENT flag clear bit */
+#define SDIO_ICR_DATAENDC 0x00000100U /*!<DATAEND flag clear bit */
+#define SDIO_ICR_DBCKENDC 0x00000400U /*!<DBCKEND flag clear bit */
+#define SDIO_ICR_SDIOITC 0x00400000U /*!<SDIOIT flag clear bit */
+
+/****************** Bit definition for SDIO_MASK register *******************/
+#define SDIO_MASK_CCRCFAILIE 0x00000001U /*!<Command CRC Fail Interrupt Enable */
+#define SDIO_MASK_DCRCFAILIE 0x00000002U /*!<Data CRC Fail Interrupt Enable */
+#define SDIO_MASK_CTIMEOUTIE 0x00000004U /*!<Command TimeOut Interrupt Enable */
+#define SDIO_MASK_DTIMEOUTIE 0x00000008U /*!<Data TimeOut Interrupt Enable */
+#define SDIO_MASK_TXUNDERRIE 0x00000010U /*!<Tx FIFO UnderRun Error Interrupt Enable */
+#define SDIO_MASK_RXOVERRIE 0x00000020U /*!<Rx FIFO OverRun Error Interrupt Enable */
+#define SDIO_MASK_CMDRENDIE 0x00000040U /*!<Command Response Received Interrupt Enable */
+#define SDIO_MASK_CMDSENTIE 0x00000080U /*!<Command Sent Interrupt Enable */
+#define SDIO_MASK_DATAENDIE 0x00000100U /*!<Data End Interrupt Enable */
+#define SDIO_MASK_DBCKENDIE 0x00000400U /*!<Data Block End Interrupt Enable */
+#define SDIO_MASK_CMDACTIE 0x00000800U /*!<CCommand Acting Interrupt Enable */
+#define SDIO_MASK_TXACTIE 0x00001000U /*!<Data Transmit Acting Interrupt Enable */
+#define SDIO_MASK_RXACTIE 0x00002000U /*!<Data receive acting interrupt enabled */
+#define SDIO_MASK_TXFIFOHEIE 0x00004000U /*!<Tx FIFO Half Empty interrupt Enable */
+#define SDIO_MASK_RXFIFOHFIE 0x00008000U /*!<Rx FIFO Half Full interrupt Enable */
+#define SDIO_MASK_TXFIFOFIE 0x00010000U /*!<Tx FIFO Full interrupt Enable */
+#define SDIO_MASK_RXFIFOFIE 0x00020000U /*!<Rx FIFO Full interrupt Enable */
+#define SDIO_MASK_TXFIFOEIE 0x00040000U /*!<Tx FIFO Empty interrupt Enable */
+#define SDIO_MASK_RXFIFOEIE 0x00080000U /*!<Rx FIFO Empty interrupt Enable */
+#define SDIO_MASK_TXDAVLIE 0x00100000U /*!<Data available in Tx FIFO interrupt Enable */
+#define SDIO_MASK_RXDAVLIE 0x00200000U /*!<Data available in Rx FIFO interrupt Enable */
+#define SDIO_MASK_SDIOITIE 0x00400000U /*!<SDIO Mode Interrupt Received interrupt Enable */
+
+/***************** Bit definition for SDIO_FIFOCNT register *****************/
+#define SDIO_FIFOCNT_FIFOCOUNT 0x00FFFFFFU /*!<Remaining number of words to be written to or read from the FIFO */
+
+/****************** Bit definition for SDIO_FIFO register *******************/
+#define SDIO_FIFO_FIFODATA 0xFFFFFFFFU /*!<Receive and transmit FIFO data */
+
+/******************************************************************************/
+/* */
+/* Serial Peripheral Interface */
+/* */
+/******************************************************************************/
+/******************* Bit definition for SPI_CR1 register ********************/
+#define SPI_CR1_CPHA 0x00000001U /*!<Clock Phase */
+#define SPI_CR1_CPOL 0x00000002U /*!<Clock Polarity */
+#define SPI_CR1_MSTR 0x00000004U /*!<Master Selection */
+
+#define SPI_CR1_BR 0x00000038U /*!<BR[2:0] bits (Baud Rate Control) */
+#define SPI_CR1_BR_0 0x00000008U /*!<Bit 0 */
+#define SPI_CR1_BR_1 0x00000010U /*!<Bit 1 */
+#define SPI_CR1_BR_2 0x00000020U /*!<Bit 2 */
+
+#define SPI_CR1_SPE 0x00000040U /*!<SPI Enable */
+#define SPI_CR1_LSBFIRST 0x00000080U /*!<Frame Format */
+#define SPI_CR1_SSI 0x00000100U /*!<Internal slave select */
+#define SPI_CR1_SSM 0x00000200U /*!<Software slave management */
+#define SPI_CR1_RXONLY 0x00000400U /*!<Receive only */
+#define SPI_CR1_DFF 0x00000800U /*!<Data Frame Format */
+#define SPI_CR1_CRCNEXT 0x00001000U /*!<Transmit CRC next */
+#define SPI_CR1_CRCEN 0x00002000U /*!<Hardware CRC calculation enable */
+#define SPI_CR1_BIDIOE 0x00004000U /*!<Output enable in bidirectional mode */
+#define SPI_CR1_BIDIMODE 0x00008000U /*!<Bidirectional data mode enable */
+
+/******************* Bit definition for SPI_CR2 register ********************/
+#define SPI_CR2_RXDMAEN 0x00000001U /*!<Rx Buffer DMA Enable */
+#define SPI_CR2_TXDMAEN 0x00000002U /*!<Tx Buffer DMA Enable */
+#define SPI_CR2_SSOE 0x00000004U /*!<SS Output Enable */
+#define SPI_CR2_FRF 0x00000010U /*!<Frame Format */
+#define SPI_CR2_ERRIE 0x00000020U /*!<Error Interrupt Enable */
+#define SPI_CR2_RXNEIE 0x00000040U /*!<RX buffer Not Empty Interrupt Enable */
+#define SPI_CR2_TXEIE 0x00000080U /*!<Tx buffer Empty Interrupt Enable */
+
+/******************** Bit definition for SPI_SR register ********************/
+#define SPI_SR_RXNE 0x00000001U /*!<Receive buffer Not Empty */
+#define SPI_SR_TXE 0x00000002U /*!<Transmit buffer Empty */
+#define SPI_SR_CHSIDE 0x00000004U /*!<Channel side */
+#define SPI_SR_UDR 0x00000008U /*!<Underrun flag */
+#define SPI_SR_CRCERR 0x00000010U /*!<CRC Error flag */
+#define SPI_SR_MODF 0x00000020U /*!<Mode fault */
+#define SPI_SR_OVR 0x00000040U /*!<Overrun flag */
+#define SPI_SR_BSY 0x00000080U /*!<Busy flag */
+#define SPI_SR_FRE 0x00000100U /*!<Frame format error flag */
+
+/******************** Bit definition for SPI_DR register ********************/
+#define SPI_DR_DR 0x0000FFFFU /*!<Data Register */
+
+/******************* Bit definition for SPI_CRCPR register ******************/
+#define SPI_CRCPR_CRCPOLY 0x0000FFFFU /*!<CRC polynomial register */
+
+/****************** Bit definition for SPI_RXCRCR register ******************/
+#define SPI_RXCRCR_RXCRC 0x0000FFFFU /*!<Rx CRC Register */
+
+/****************** Bit definition for SPI_TXCRCR register ******************/
+#define SPI_TXCRCR_TXCRC 0x0000FFFFU /*!<Tx CRC Register */
+
+/****************** Bit definition for SPI_I2SCFGR register *****************/
+#define SPI_I2SCFGR_CHLEN 0x00000001U /*!<Channel length (number of bits per audio channel) */
+
+#define SPI_I2SCFGR_DATLEN 0x00000006U /*!<DATLEN[1:0] bits (Data length to be transferred) */
+#define SPI_I2SCFGR_DATLEN_0 0x00000002U /*!<Bit 0 */
+#define SPI_I2SCFGR_DATLEN_1 0x00000004U /*!<Bit 1 */
+
+#define SPI_I2SCFGR_CKPOL 0x00000008U /*!<steady state clock polarity */
+
+#define SPI_I2SCFGR_I2SSTD 0x00000030U /*!<I2SSTD[1:0] bits (I2S standard selection) */
+#define SPI_I2SCFGR_I2SSTD_0 0x00000010U /*!<Bit 0 */
+#define SPI_I2SCFGR_I2SSTD_1 0x00000020U /*!<Bit 1 */
+
+#define SPI_I2SCFGR_PCMSYNC 0x00000080U /*!<PCM frame synchronization */
+
+#define SPI_I2SCFGR_I2SCFG 0x00000300U /*!<I2SCFG[1:0] bits (I2S configuration mode) */
+#define SPI_I2SCFGR_I2SCFG_0 0x00000100U /*!<Bit 0 */
+#define SPI_I2SCFGR_I2SCFG_1 0x00000200U /*!<Bit 1 */
+
+#define SPI_I2SCFGR_I2SE 0x00000400U /*!<I2S Enable */
+#define SPI_I2SCFGR_I2SMOD 0x00000800U /*!<I2S mode selection */
+#define SPI_I2SCFGR_ASTRTEN 0x00001000U /*!<Asynchronous start enable */
+
+/****************** Bit definition for SPI_I2SPR register *******************/
+#define SPI_I2SPR_I2SDIV 0x000000FFU /*!<I2S Linear prescaler */
+#define SPI_I2SPR_ODD 0x00000100U /*!<Odd factor for the prescaler */
+#define SPI_I2SPR_MCKOE 0x00000200U /*!<Master Clock Output Enable */
+
+/******************************************************************************/
+/* */
+/* SYSCFG */
+/* */
+/******************************************************************************/
+/****************** Bit definition for SYSCFG_MEMRMP register ***************/
+#define SYSCFG_MEMRMP_MEM_MODE 0x00000007U /*!< SYSCFG_Memory Remap Config */
+#define SYSCFG_MEMRMP_MEM_MODE_0 0x00000001U
+#define SYSCFG_MEMRMP_MEM_MODE_1 0x00000002U
+#define SYSCFG_MEMRMP_MEM_MODE_2 0x00000004U
+
+#define SYSCFG_MEMRMP_UFB_MODE 0x00000100U /*!< User Flash Bank mode */
+#define SYSCFG_SWP_FMC 0x00000C00U /*!< FMC memory mapping swap */
+
+/****************** Bit definition for SYSCFG_PMC register ******************/
+#define SYSCFG_PMC_ADCxDC2 0x00070000U /*!< Refer to AN4073 on how to use this bit */
+#define SYSCFG_PMC_ADC1DC2 0x00010000U /*!< Refer to AN4073 on how to use this bit */
+#define SYSCFG_PMC_ADC2DC2 0x00020000U /*!< Refer to AN4073 on how to use this bit */
+#define SYSCFG_PMC_ADC3DC2 0x00040000U /*!< Refer to AN4073 on how to use this bit */
+
+#define SYSCFG_PMC_MII_RMII_SEL 0x00800000U /*!<Ethernet PHY interface selection */
+
+/***************** Bit definition for SYSCFG_EXTICR1 register ***************/
+#define SYSCFG_EXTICR1_EXTI0 0x000FU /*!<EXTI 0 configuration */
+#define SYSCFG_EXTICR1_EXTI1 0x00F0U /*!<EXTI 1 configuration */
+#define SYSCFG_EXTICR1_EXTI2 0x0F00U /*!<EXTI 2 configuration */
+#define SYSCFG_EXTICR1_EXTI3 0xF000U /*!<EXTI 3 configuration */
+/**
+ * @brief EXTI0 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI0_PA 0x0000U /*!<PA[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PB 0x0001U /*!<PB[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PC 0x0002U /*!<PC[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PD 0x0003U /*!<PD[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PE 0x0004U /*!<PE[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PF 0x0005U /*!<PF[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PG 0x0006U /*!<PG[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PH 0x0007U /*!<PH[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PI 0x0008U /*!<PI[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PJ 0x0009U /*!<PJ[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PK 0x000AU /*!<PK[0] pin */
+
+/**
+ * @brief EXTI1 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI1_PA 0x0000U /*!<PA[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PB 0x0010U /*!<PB[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PC 0x0020U /*!<PC[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PD 0x0030U /*!<PD[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PE 0x0040U /*!<PE[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PF 0x0050U /*!<PF[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PG 0x0060U /*!<PG[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PH 0x0070U /*!<PH[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PI 0x0080U /*!<PI[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PJ 0x0090U /*!<PJ[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PK 0x00A0U /*!<PK[1] pin */
+
+
+/**
+ * @brief EXTI2 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI2_PA 0x0000U /*!<PA[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PB 0x0100U /*!<PB[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PC 0x0200U /*!<PC[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PD 0x0300U /*!<PD[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PE 0x0400U /*!<PE[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PF 0x0500U /*!<PF[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PG 0x0600U /*!<PG[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PH 0x0700U /*!<PH[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PI 0x0800U /*!<PI[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PJ 0x0900U /*!<PJ[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PK 0x0A00U /*!<PK[2] pin */
+
+
+/**
+ * @brief EXTI3 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI3_PA 0x0000U /*!<PA[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PB 0x1000U /*!<PB[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PC 0x2000U /*!<PC[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PD 0x3000U /*!<PD[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PE 0x4000U /*!<PE[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PF 0x5000U /*!<PF[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PG 0x6000U /*!<PG[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PH 0x7000U /*!<PH[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PI 0x8000U /*!<PI[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PJ 0x9000U /*!<PJ[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PK 0xA000U /*!<PK[3] pin */
+
+
+/***************** Bit definition for SYSCFG_EXTICR2 register ***************/
+#define SYSCFG_EXTICR2_EXTI4 0x000FU /*!<EXTI 4 configuration */
+#define SYSCFG_EXTICR2_EXTI5 0x00F0U /*!<EXTI 5 configuration */
+#define SYSCFG_EXTICR2_EXTI6 0x0F00U /*!<EXTI 6 configuration */
+#define SYSCFG_EXTICR2_EXTI7 0xF000U /*!<EXTI 7 configuration */
+/**
+ * @brief EXTI4 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI4_PA 0x0000U /*!<PA[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PB 0x0001U /*!<PB[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PC 0x0002U /*!<PC[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PD 0x0003U /*!<PD[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PE 0x0004U /*!<PE[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PF 0x0005U /*!<PF[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PG 0x0006U /*!<PG[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PH 0x0007U /*!<PH[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PI 0x0008U /*!<PI[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PJ 0x0009U /*!<PJ[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PK 0x000AU /*!<PK[4] pin */
+
+/**
+ * @brief EXTI5 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI5_PA 0x0000U /*!<PA[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PB 0x0010U /*!<PB[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PC 0x0020U /*!<PC[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PD 0x0030U /*!<PD[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PE 0x0040U /*!<PE[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PF 0x0050U /*!<PF[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PG 0x0060U /*!<PG[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PH 0x0070U /*!<PH[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PI 0x0080U /*!<PI[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PJ 0x0090U /*!<PJ[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PK 0x00A0U /*!<PK[5] pin */
+
+/**
+ * @brief EXTI6 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI6_PA 0x0000U /*!<PA[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PB 0x0100U /*!<PB[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PC 0x0200U /*!<PC[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PD 0x0300U /*!<PD[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PE 0x0400U /*!<PE[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PF 0x0500U /*!<PF[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PG 0x0600U /*!<PG[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PH 0x0700U /*!<PH[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PI 0x0800U /*!<PI[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PJ 0x0900U /*!<PJ[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PK 0x0A00U /*!<PK[6] pin */
+
+
+/**
+ * @brief EXTI7 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI7_PA 0x0000U /*!<PA[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PB 0x1000U /*!<PB[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PC 0x2000U /*!<PC[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PD 0x3000U /*!<PD[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PE 0x4000U /*!<PE[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PF 0x5000U /*!<PF[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PG 0x6000U /*!<PG[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PH 0x7000U /*!<PH[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PI 0x8000U /*!<PI[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PJ 0x9000U /*!<PJ[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PK 0xA000U /*!<PK[7] pin */
+
+/***************** Bit definition for SYSCFG_EXTICR3 register ***************/
+#define SYSCFG_EXTICR3_EXTI8 0x000FU /*!<EXTI 8 configuration */
+#define SYSCFG_EXTICR3_EXTI9 0x00F0U /*!<EXTI 9 configuration */
+#define SYSCFG_EXTICR3_EXTI10 0x0F00U /*!<EXTI 10 configuration */
+#define SYSCFG_EXTICR3_EXTI11 0xF000U /*!<EXTI 11 configuration */
+
+/**
+ * @brief EXTI8 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI8_PA 0x0000U /*!<PA[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PB 0x0001U /*!<PB[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PC 0x0002U /*!<PC[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PD 0x0003U /*!<PD[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PE 0x0004U /*!<PE[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PF 0x0005U /*!<PF[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PG 0x0006U /*!<PG[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PH 0x0007U /*!<PH[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PI 0x0008U /*!<PI[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PJ 0x0009U /*!<PJ[8] pin */
+
+/**
+ * @brief EXTI9 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI9_PA 0x0000U /*!<PA[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PB 0x0010U /*!<PB[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PC 0x0020U /*!<PC[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PD 0x0030U /*!<PD[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PE 0x0040U /*!<PE[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PF 0x0050U /*!<PF[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PG 0x0060U /*!<PG[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PH 0x0070U /*!<PH[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PI 0x0080U /*!<PI[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PJ 0x0090U /*!<PJ[9] pin */
+
+
+/**
+ * @brief EXTI10 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI10_PA 0x0000U /*!<PA[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PB 0x0100U /*!<PB[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PC 0x0200U /*!<PC[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PD 0x0300U /*!<PD[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PE 0x0400U /*!<PE[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PF 0x0500U /*!<PF[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PG 0x0600U /*!<PG[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PH 0x0700U /*!<PH[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PI 0x0800U /*!<PI[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PJ 0x0900U /*!<PJ[10] pin */
+
+
+/**
+ * @brief EXTI11 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI11_PA 0x0000U /*!<PA[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PB 0x1000U /*!<PB[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PC 0x2000U /*!<PC[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PD 0x3000U /*!<PD[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PE 0x4000U /*!<PE[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PF 0x5000U /*!<PF[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PG 0x6000U /*!<PG[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PH 0x7000U /*!<PH[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PI 0x8000U /*!<PI[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PJ 0x9000U /*!<PJ[11] pin */
+
+
+/***************** Bit definition for SYSCFG_EXTICR4 register ***************/
+#define SYSCFG_EXTICR4_EXTI12 0x000FU /*!<EXTI 12 configuration */
+#define SYSCFG_EXTICR4_EXTI13 0x00F0U /*!<EXTI 13 configuration */
+#define SYSCFG_EXTICR4_EXTI14 0x0F00U /*!<EXTI 14 configuration */
+#define SYSCFG_EXTICR4_EXTI15 0xF000U /*!<EXTI 15 configuration */
+/**
+ * @brief EXTI12 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI12_PA 0x0000U /*!<PA[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PB 0x0001U /*!<PB[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PC 0x0002U /*!<PC[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PD 0x0003U /*!<PD[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PE 0x0004U /*!<PE[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PF 0x0005U /*!<PF[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PG 0x0006U /*!<PG[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PH 0x0007U /*!<PH[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PI 0x0008U /*!<PI[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PJ 0x0009U /*!<PJ[12] pin */
+
+
+/**
+ * @brief EXTI13 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI13_PA 0x0000U /*!<PA[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PB 0x0010U /*!<PB[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PC 0x0020U /*!<PC[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PD 0x0030U /*!<PD[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PE 0x0040U /*!<PE[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PF 0x0050U /*!<PF[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PG 0x0060U /*!<PG[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PH 0x0070U /*!<PH[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PI 0x0008U /*!<PI[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PJ 0x0009U /*!<PJ[13] pin */
+
+
+/**
+ * @brief EXTI14 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI14_PA 0x0000U /*!<PA[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PB 0x0100U /*!<PB[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PC 0x0200U /*!<PC[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PD 0x0300U /*!<PD[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PE 0x0400U /*!<PE[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PF 0x0500U /*!<PF[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PG 0x0600U /*!<PG[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PH 0x0700U /*!<PH[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PI 0x0800U /*!<PI[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PJ 0x0900U /*!<PJ[14] pin */
+
+
+/**
+ * @brief EXTI15 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI15_PA 0x0000U /*!<PA[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PB 0x1000U /*!<PB[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PC 0x2000U /*!<PC[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PD 0x3000U /*!<PD[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PE 0x4000U /*!<PE[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PF 0x5000U /*!<PF[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PG 0x6000U /*!<PG[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PH 0x7000U /*!<PH[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PI 0x8000U /*!<PI[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PJ 0x9000U /*!<PJ[15] pin */
+
+/****************** Bit definition for SYSCFG_CMPCR register ****************/
+#define SYSCFG_CMPCR_CMP_PD 0x00000001U /*!<Compensation cell ready flag */
+#define SYSCFG_CMPCR_READY 0x00000100U /*!<Compensation cell power-down */
+
+/******************************************************************************/
+/* */
+/* TIM */
+/* */
+/******************************************************************************/
+/******************* Bit definition for TIM_CR1 register ********************/
+#define TIM_CR1_CEN 0x0001U /*!<Counter enable */
+#define TIM_CR1_UDIS 0x0002U /*!<Update disable */
+#define TIM_CR1_URS 0x0004U /*!<Update request source */
+#define TIM_CR1_OPM 0x0008U /*!<One pulse mode */
+#define TIM_CR1_DIR 0x0010U /*!<Direction */
+
+#define TIM_CR1_CMS 0x0060U /*!<CMS[1:0] bits (Center-aligned mode selection) */
+#define TIM_CR1_CMS_0 0x0020U /*!<Bit 0 */
+#define TIM_CR1_CMS_1 0x0040U /*!<Bit 1 */
+
+#define TIM_CR1_ARPE 0x0080U /*!<Auto-reload preload enable */
+
+#define TIM_CR1_CKD 0x0300U /*!<CKD[1:0] bits (clock division) */
+#define TIM_CR1_CKD_0 0x0100U /*!<Bit 0 */
+#define TIM_CR1_CKD_1 0x0200U /*!<Bit 1 */
+
+/******************* Bit definition for TIM_CR2 register ********************/
+#define TIM_CR2_CCPC 0x0001U /*!<Capture/Compare Preloaded Control */
+#define TIM_CR2_CCUS 0x0004U /*!<Capture/Compare Control Update Selection */
+#define TIM_CR2_CCDS 0x0008U /*!<Capture/Compare DMA Selection */
+
+#define TIM_CR2_MMS 0x0070U /*!<MMS[2:0] bits (Master Mode Selection) */
+#define TIM_CR2_MMS_0 0x0010U /*!<Bit 0 */
+#define TIM_CR2_MMS_1 0x0020U /*!<Bit 1 */
+#define TIM_CR2_MMS_2 0x0040U /*!<Bit 2 */
+
+#define TIM_CR2_TI1S 0x0080U /*!<TI1 Selection */
+#define TIM_CR2_OIS1 0x0100U /*!<Output Idle state 1 (OC1 output) */
+#define TIM_CR2_OIS1N 0x0200U /*!<Output Idle state 1 (OC1N output) */
+#define TIM_CR2_OIS2 0x0400U /*!<Output Idle state 2 (OC2 output) */
+#define TIM_CR2_OIS2N 0x0800U /*!<Output Idle state 2 (OC2N output) */
+#define TIM_CR2_OIS3 0x1000U /*!<Output Idle state 3 (OC3 output) */
+#define TIM_CR2_OIS3N 0x2000U /*!<Output Idle state 3 (OC3N output) */
+#define TIM_CR2_OIS4 0x4000U /*!<Output Idle state 4 (OC4 output) */
+
+/******************* Bit definition for TIM_SMCR register *******************/
+#define TIM_SMCR_SMS 0x0007U /*!<SMS[2:0] bits (Slave mode selection) */
+#define TIM_SMCR_SMS_0 0x0001U /*!<Bit 0 */
+#define TIM_SMCR_SMS_1 0x0002U /*!<Bit 1 */
+#define TIM_SMCR_SMS_2 0x0004U /*!<Bit 2 */
+
+#define TIM_SMCR_TS 0x0070U /*!<TS[2:0] bits (Trigger selection) */
+#define TIM_SMCR_TS_0 0x0010U /*!<Bit 0 */
+#define TIM_SMCR_TS_1 0x0020U /*!<Bit 1 */
+#define TIM_SMCR_TS_2 0x0040U /*!<Bit 2 */
+
+#define TIM_SMCR_MSM 0x0080U /*!<Master/slave mode */
+
+#define TIM_SMCR_ETF 0x0F00U /*!<ETF[3:0] bits (External trigger filter) */
+#define TIM_SMCR_ETF_0 0x0100U /*!<Bit 0 */
+#define TIM_SMCR_ETF_1 0x0200U /*!<Bit 1 */
+#define TIM_SMCR_ETF_2 0x0400U /*!<Bit 2 */
+#define TIM_SMCR_ETF_3 0x0800U /*!<Bit 3 */
+
+#define TIM_SMCR_ETPS 0x3000U /*!<ETPS[1:0] bits (External trigger prescaler) */
+#define TIM_SMCR_ETPS_0 0x1000U /*!<Bit 0 */
+#define TIM_SMCR_ETPS_1 0x2000U /*!<Bit 1 */
+
+#define TIM_SMCR_ECE 0x4000U /*!<External clock enable */
+#define TIM_SMCR_ETP 0x8000U /*!<External trigger polarity */
+
+/******************* Bit definition for TIM_DIER register *******************/
+#define TIM_DIER_UIE 0x0001U /*!<Update interrupt enable */
+#define TIM_DIER_CC1IE 0x0002U /*!<Capture/Compare 1 interrupt enable */
+#define TIM_DIER_CC2IE 0x0004U /*!<Capture/Compare 2 interrupt enable */
+#define TIM_DIER_CC3IE 0x0008U /*!<Capture/Compare 3 interrupt enable */
+#define TIM_DIER_CC4IE 0x0010U /*!<Capture/Compare 4 interrupt enable */
+#define TIM_DIER_COMIE 0x0020U /*!<COM interrupt enable */
+#define TIM_DIER_TIE 0x0040U /*!<Trigger interrupt enable */
+#define TIM_DIER_BIE 0x0080U /*!<Break interrupt enable */
+#define TIM_DIER_UDE 0x0100U /*!<Update DMA request enable */
+#define TIM_DIER_CC1DE 0x0200U /*!<Capture/Compare 1 DMA request enable */
+#define TIM_DIER_CC2DE 0x0400U /*!<Capture/Compare 2 DMA request enable */
+#define TIM_DIER_CC3DE 0x0800U /*!<Capture/Compare 3 DMA request enable */
+#define TIM_DIER_CC4DE 0x1000U /*!<Capture/Compare 4 DMA request enable */
+#define TIM_DIER_COMDE 0x2000U /*!<COM DMA request enable */
+#define TIM_DIER_TDE 0x4000U /*!<Trigger DMA request enable */
+
+/******************** Bit definition for TIM_SR register ********************/
+#define TIM_SR_UIF 0x0001U /*!<Update interrupt Flag */
+#define TIM_SR_CC1IF 0x0002U /*!<Capture/Compare 1 interrupt Flag */
+#define TIM_SR_CC2IF 0x0004U /*!<Capture/Compare 2 interrupt Flag */
+#define TIM_SR_CC3IF 0x0008U /*!<Capture/Compare 3 interrupt Flag */
+#define TIM_SR_CC4IF 0x0010U /*!<Capture/Compare 4 interrupt Flag */
+#define TIM_SR_COMIF 0x0020U /*!<COM interrupt Flag */
+#define TIM_SR_TIF 0x0040U /*!<Trigger interrupt Flag */
+#define TIM_SR_BIF 0x0080U /*!<Break interrupt Flag */
+#define TIM_SR_CC1OF 0x0200U /*!<Capture/Compare 1 Overcapture Flag */
+#define TIM_SR_CC2OF 0x0400U /*!<Capture/Compare 2 Overcapture Flag */
+#define TIM_SR_CC3OF 0x0800U /*!<Capture/Compare 3 Overcapture Flag */
+#define TIM_SR_CC4OF 0x1000U /*!<Capture/Compare 4 Overcapture Flag */
+
+/******************* Bit definition for TIM_EGR register ********************/
+#define TIM_EGR_UG 0x01U /*!<Update Generation */
+#define TIM_EGR_CC1G 0x02U /*!<Capture/Compare 1 Generation */
+#define TIM_EGR_CC2G 0x04U /*!<Capture/Compare 2 Generation */
+#define TIM_EGR_CC3G 0x08U /*!<Capture/Compare 3 Generation */
+#define TIM_EGR_CC4G 0x10U /*!<Capture/Compare 4 Generation */
+#define TIM_EGR_COMG 0x20U /*!<Capture/Compare Control Update Generation */
+#define TIM_EGR_TG 0x40U /*!<Trigger Generation */
+#define TIM_EGR_BG 0x80U /*!<Break Generation */
+
+/****************** Bit definition for TIM_CCMR1 register *******************/
+#define TIM_CCMR1_CC1S 0x0003U /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
+#define TIM_CCMR1_CC1S_0 0x0001U /*!<Bit 0 */
+#define TIM_CCMR1_CC1S_1 0x0002U /*!<Bit 1 */
+
+#define TIM_CCMR1_OC1FE 0x0004U /*!<Output Compare 1 Fast enable */
+#define TIM_CCMR1_OC1PE 0x0008U /*!<Output Compare 1 Preload enable */
+
+#define TIM_CCMR1_OC1M 0x0070U /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
+#define TIM_CCMR1_OC1M_0 0x0010U /*!<Bit 0 */
+#define TIM_CCMR1_OC1M_1 0x0020U /*!<Bit 1 */
+#define TIM_CCMR1_OC1M_2 0x0040U /*!<Bit 2 */
+
+#define TIM_CCMR1_OC1CE 0x0080U /*!<Output Compare 1Clear Enable */
+
+#define TIM_CCMR1_CC2S 0x0300U /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
+#define TIM_CCMR1_CC2S_0 0x0100U /*!<Bit 0 */
+#define TIM_CCMR1_CC2S_1 0x0200U /*!<Bit 1 */
+
+#define TIM_CCMR1_OC2FE 0x0400U /*!<Output Compare 2 Fast enable */
+#define TIM_CCMR1_OC2PE 0x0800U /*!<Output Compare 2 Preload enable */
+
+#define TIM_CCMR1_OC2M 0x7000U /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
+#define TIM_CCMR1_OC2M_0 0x1000U /*!<Bit 0 */
+#define TIM_CCMR1_OC2M_1 0x2000U /*!<Bit 1 */
+#define TIM_CCMR1_OC2M_2 0x4000U /*!<Bit 2 */
+
+#define TIM_CCMR1_OC2CE 0x8000U /*!<Output Compare 2 Clear Enable */
+
+/*----------------------------------------------------------------------------*/
+
+#define TIM_CCMR1_IC1PSC 0x000CU /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
+#define TIM_CCMR1_IC1PSC_0 0x0004U /*!<Bit 0 */
+#define TIM_CCMR1_IC1PSC_1 0x0008U /*!<Bit 1 */
+
+#define TIM_CCMR1_IC1F 0x00F0U /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
+#define TIM_CCMR1_IC1F_0 0x0010U /*!<Bit 0 */
+#define TIM_CCMR1_IC1F_1 0x0020U /*!<Bit 1 */
+#define TIM_CCMR1_IC1F_2 0x0040U /*!<Bit 2 */
+#define TIM_CCMR1_IC1F_3 0x0080U /*!<Bit 3 */
+
+#define TIM_CCMR1_IC2PSC 0x0C00U /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
+#define TIM_CCMR1_IC2PSC_0 0x0400U /*!<Bit 0 */
+#define TIM_CCMR1_IC2PSC_1 0x0800U /*!<Bit 1 */
+
+#define TIM_CCMR1_IC2F 0xF000U /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
+#define TIM_CCMR1_IC2F_0 0x1000U /*!<Bit 0 */
+#define TIM_CCMR1_IC2F_1 0x2000U /*!<Bit 1 */
+#define TIM_CCMR1_IC2F_2 0x4000U /*!<Bit 2 */
+#define TIM_CCMR1_IC2F_3 0x8000U /*!<Bit 3 */
+
+/****************** Bit definition for TIM_CCMR2 register *******************/
+#define TIM_CCMR2_CC3S 0x0003U /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
+#define TIM_CCMR2_CC3S_0 0x0001U /*!<Bit 0 */
+#define TIM_CCMR2_CC3S_1 0x0002U /*!<Bit 1 */
+
+#define TIM_CCMR2_OC3FE 0x0004U /*!<Output Compare 3 Fast enable */
+#define TIM_CCMR2_OC3PE 0x0008U /*!<Output Compare 3 Preload enable */
+
+#define TIM_CCMR2_OC3M 0x0070U /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
+#define TIM_CCMR2_OC3M_0 0x0010U /*!<Bit 0 */
+#define TIM_CCMR2_OC3M_1 0x0020U /*!<Bit 1 */
+#define TIM_CCMR2_OC3M_2 0x0040U /*!<Bit 2 */
+
+#define TIM_CCMR2_OC3CE 0x0080U /*!<Output Compare 3 Clear Enable */
+
+#define TIM_CCMR2_CC4S 0x0300U /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
+#define TIM_CCMR2_CC4S_0 0x0100U /*!<Bit 0 */
+#define TIM_CCMR2_CC4S_1 0x0200U /*!<Bit 1 */
+
+#define TIM_CCMR2_OC4FE 0x0400U /*!<Output Compare 4 Fast enable */
+#define TIM_CCMR2_OC4PE 0x0800U /*!<Output Compare 4 Preload enable */
+
+#define TIM_CCMR2_OC4M 0x7000U /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
+#define TIM_CCMR2_OC4M_0 0x1000U /*!<Bit 0 */
+#define TIM_CCMR2_OC4M_1 0x2000U /*!<Bit 1 */
+#define TIM_CCMR2_OC4M_2 0x4000U /*!<Bit 2 */
+
+#define TIM_CCMR2_OC4CE 0x8000U /*!<Output Compare 4 Clear Enable */
+
+/*----------------------------------------------------------------------------*/
+
+#define TIM_CCMR2_IC3PSC 0x000CU /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
+#define TIM_CCMR2_IC3PSC_0 0x0004U /*!<Bit 0 */
+#define TIM_CCMR2_IC3PSC_1 0x0008U /*!<Bit 1 */
+
+#define TIM_CCMR2_IC3F 0x00F0U /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
+#define TIM_CCMR2_IC3F_0 0x0010U /*!<Bit 0 */
+#define TIM_CCMR2_IC3F_1 0x0020U /*!<Bit 1 */
+#define TIM_CCMR2_IC3F_2 0x0040U /*!<Bit 2 */
+#define TIM_CCMR2_IC3F_3 0x0080U /*!<Bit 3 */
+
+#define TIM_CCMR2_IC4PSC 0x0C00U /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
+#define TIM_CCMR2_IC4PSC_0 0x0400U /*!<Bit 0 */
+#define TIM_CCMR2_IC4PSC_1 0x0800U /*!<Bit 1 */
+
+#define TIM_CCMR2_IC4F 0xF000U /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
+#define TIM_CCMR2_IC4F_0 0x1000U /*!<Bit 0 */
+#define TIM_CCMR2_IC4F_1 0x2000U /*!<Bit 1 */
+#define TIM_CCMR2_IC4F_2 0x4000U /*!<Bit 2 */
+#define TIM_CCMR2_IC4F_3 0x8000U /*!<Bit 3 */
+
+/******************* Bit definition for TIM_CCER register *******************/
+#define TIM_CCER_CC1E 0x0001U /*!<Capture/Compare 1 output enable */
+#define TIM_CCER_CC1P 0x0002U /*!<Capture/Compare 1 output Polarity */
+#define TIM_CCER_CC1NE 0x0004U /*!<Capture/Compare 1 Complementary output enable */
+#define TIM_CCER_CC1NP 0x0008U /*!<Capture/Compare 1 Complementary output Polarity */
+#define TIM_CCER_CC2E 0x0010U /*!<Capture/Compare 2 output enable */
+#define TIM_CCER_CC2P 0x0020U /*!<Capture/Compare 2 output Polarity */
+#define TIM_CCER_CC2NE 0x0040U /*!<Capture/Compare 2 Complementary output enable */
+#define TIM_CCER_CC2NP 0x0080U /*!<Capture/Compare 2 Complementary output Polarity */
+#define TIM_CCER_CC3E 0x0100U /*!<Capture/Compare 3 output enable */
+#define TIM_CCER_CC3P 0x0200U /*!<Capture/Compare 3 output Polarity */
+#define TIM_CCER_CC3NE 0x0400U /*!<Capture/Compare 3 Complementary output enable */
+#define TIM_CCER_CC3NP 0x0800U /*!<Capture/Compare 3 Complementary output Polarity */
+#define TIM_CCER_CC4E 0x1000U /*!<Capture/Compare 4 output enable */
+#define TIM_CCER_CC4P 0x2000U /*!<Capture/Compare 4 output Polarity */
+#define TIM_CCER_CC4NP 0x8000U /*!<Capture/Compare 4 Complementary output Polarity */
+
+/******************* Bit definition for TIM_CNT register ********************/
+#define TIM_CNT_CNT 0xFFFFU /*!<Counter Value */
+
+/******************* Bit definition for TIM_PSC register ********************/
+#define TIM_PSC_PSC 0xFFFFU /*!<Prescaler Value */
+
+/******************* Bit definition for TIM_ARR register ********************/
+#define TIM_ARR_ARR 0xFFFFU /*!<actual auto-reload Value */
+
+/******************* Bit definition for TIM_RCR register ********************/
+#define TIM_RCR_REP 0xFFU /*!<Repetition Counter Value */
+
+/******************* Bit definition for TIM_CCR1 register *******************/
+#define TIM_CCR1_CCR1 0xFFFFU /*!<Capture/Compare 1 Value */
+
+/******************* Bit definition for TIM_CCR2 register *******************/
+#define TIM_CCR2_CCR2 0xFFFFU /*!<Capture/Compare 2 Value */
+
+/******************* Bit definition for TIM_CCR3 register *******************/
+#define TIM_CCR3_CCR3 0xFFFFU /*!<Capture/Compare 3 Value */
+
+/******************* Bit definition for TIM_CCR4 register *******************/
+#define TIM_CCR4_CCR4 0xFFFFU /*!<Capture/Compare 4 Value */
+
+/******************* Bit definition for TIM_BDTR register *******************/
+#define TIM_BDTR_DTG 0x00FFU /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
+#define TIM_BDTR_DTG_0 0x0001U /*!<Bit 0 */
+#define TIM_BDTR_DTG_1 0x0002U /*!<Bit 1 */
+#define TIM_BDTR_DTG_2 0x0004U /*!<Bit 2 */
+#define TIM_BDTR_DTG_3 0x0008U /*!<Bit 3 */
+#define TIM_BDTR_DTG_4 0x0010U /*!<Bit 4 */
+#define TIM_BDTR_DTG_5 0x0020U /*!<Bit 5 */
+#define TIM_BDTR_DTG_6 0x0040U /*!<Bit 6 */
+#define TIM_BDTR_DTG_7 0x0080U /*!<Bit 7 */
+
+#define TIM_BDTR_LOCK 0x0300U /*!<LOCK[1:0] bits (Lock Configuration) */
+#define TIM_BDTR_LOCK_0 0x0100U /*!<Bit 0 */
+#define TIM_BDTR_LOCK_1 0x0200U /*!<Bit 1 */
+
+#define TIM_BDTR_OSSI 0x0400U /*!<Off-State Selection for Idle mode */
+#define TIM_BDTR_OSSR 0x0800U /*!<Off-State Selection for Run mode */
+#define TIM_BDTR_BKE 0x1000U /*!<Break enable */
+#define TIM_BDTR_BKP 0x2000U /*!<Break Polarity */
+#define TIM_BDTR_AOE 0x4000U /*!<Automatic Output enable */
+#define TIM_BDTR_MOE 0x8000U /*!<Main Output enable */
+
+/******************* Bit definition for TIM_DCR register ********************/
+#define TIM_DCR_DBA 0x001FU /*!<DBA[4:0] bits (DMA Base Address) */
+#define TIM_DCR_DBA_0 0x0001U /*!<Bit 0 */
+#define TIM_DCR_DBA_1 0x0002U /*!<Bit 1 */
+#define TIM_DCR_DBA_2 0x0004U /*!<Bit 2 */
+#define TIM_DCR_DBA_3 0x0008U /*!<Bit 3 */
+#define TIM_DCR_DBA_4 0x0010U /*!<Bit 4 */
+
+#define TIM_DCR_DBL 0x1F00U /*!<DBL[4:0] bits (DMA Burst Length) */
+#define TIM_DCR_DBL_0 0x0100U /*!<Bit 0 */
+#define TIM_DCR_DBL_1 0x0200U /*!<Bit 1 */
+#define TIM_DCR_DBL_2 0x0400U /*!<Bit 2 */
+#define TIM_DCR_DBL_3 0x0800U /*!<Bit 3 */
+#define TIM_DCR_DBL_4 0x1000U /*!<Bit 4 */
+
+/******************* Bit definition for TIM_DMAR register *******************/
+#define TIM_DMAR_DMAB 0xFFFFU /*!<DMA register for burst accesses */
+
+/******************* Bit definition for TIM_OR register *********************/
+#define TIM_OR_TI4_RMP 0x00C0U /*!<TI4_RMP[1:0] bits (TIM5 Input 4 remap) */
+#define TIM_OR_TI4_RMP_0 0x0040U /*!<Bit 0 */
+#define TIM_OR_TI4_RMP_1 0x0080U /*!<Bit 1 */
+#define TIM_OR_ITR1_RMP 0x0C00U /*!<ITR1_RMP[1:0] bits (TIM2 Internal trigger 1 remap) */
+#define TIM_OR_ITR1_RMP_0 0x0400U /*!<Bit 0 */
+#define TIM_OR_ITR1_RMP_1 0x0800U /*!<Bit 1 */
+
+
+/******************************************************************************/
+/* */
+/* Universal Synchronous Asynchronous Receiver Transmitter */
+/* */
+/******************************************************************************/
+/******************* Bit definition for USART_SR register *******************/
+#define USART_SR_PE 0x0001U /*!<Parity Error */
+#define USART_SR_FE 0x0002U /*!<Framing Error */
+#define USART_SR_NE 0x0004U /*!<Noise Error Flag */
+#define USART_SR_ORE 0x0008U /*!<OverRun Error */
+#define USART_SR_IDLE 0x0010U /*!<IDLE line detected */
+#define USART_SR_RXNE 0x0020U /*!<Read Data Register Not Empty */
+#define USART_SR_TC 0x0040U /*!<Transmission Complete */
+#define USART_SR_TXE 0x0080U /*!<Transmit Data Register Empty */
+#define USART_SR_LBD 0x0100U /*!<LIN Break Detection Flag */
+#define USART_SR_CTS 0x0200U /*!<CTS Flag */
+
+/******************* Bit definition for USART_DR register *******************/
+#define USART_DR_DR 0x01FFU /*!<Data value */
+
+/****************** Bit definition for USART_BRR register *******************/
+#define USART_BRR_DIV_Fraction 0x000FU /*!<Fraction of USARTDIV */
+#define USART_BRR_DIV_Mantissa 0xFFF0U /*!<Mantissa of USARTDIV */
+
+/****************** Bit definition for USART_CR1 register *******************/
+#define USART_CR1_SBK 0x0001U /*!<Send Break */
+#define USART_CR1_RWU 0x0002U /*!<Receiver wakeup */
+#define USART_CR1_RE 0x0004U /*!<Receiver Enable */
+#define USART_CR1_TE 0x0008U /*!<Transmitter Enable */
+#define USART_CR1_IDLEIE 0x0010U /*!<IDLE Interrupt Enable */
+#define USART_CR1_RXNEIE 0x0020U /*!<RXNE Interrupt Enable */
+#define USART_CR1_TCIE 0x0040U /*!<Transmission Complete Interrupt Enable */
+#define USART_CR1_TXEIE 0x0080U /*!<PE Interrupt Enable */
+#define USART_CR1_PEIE 0x0100U /*!<PE Interrupt Enable */
+#define USART_CR1_PS 0x0200U /*!<Parity Selection */
+#define USART_CR1_PCE 0x0400U /*!<Parity Control Enable */
+#define USART_CR1_WAKE 0x0800U /*!<Wakeup method */
+#define USART_CR1_M 0x1000U /*!<Word length */
+#define USART_CR1_UE 0x2000U /*!<USART Enable */
+#define USART_CR1_OVER8 0x8000U /*!<USART Oversampling by 8 enable */
+
+/****************** Bit definition for USART_CR2 register *******************/
+#define USART_CR2_ADD 0x000FU /*!<Address of the USART node */
+#define USART_CR2_LBDL 0x0020U /*!<LIN Break Detection Length */
+#define USART_CR2_LBDIE 0x0040U /*!<LIN Break Detection Interrupt Enable */
+#define USART_CR2_LBCL 0x0100U /*!<Last Bit Clock pulse */
+#define USART_CR2_CPHA 0x0200U /*!<Clock Phase */
+#define USART_CR2_CPOL 0x0400U /*!<Clock Polarity */
+#define USART_CR2_CLKEN 0x0800U /*!<Clock Enable */
+
+#define USART_CR2_STOP 0x3000U /*!<STOP[1:0] bits (STOP bits) */
+#define USART_CR2_STOP_0 0x1000U /*!<Bit 0 */
+#define USART_CR2_STOP_1 0x2000U /*!<Bit 1 */
+
+#define USART_CR2_LINEN 0x4000U /*!<LIN mode enable */
+
+/****************** Bit definition for USART_CR3 register *******************/
+#define USART_CR3_EIE 0x0001U /*!<Error Interrupt Enable */
+#define USART_CR3_IREN 0x0002U /*!<IrDA mode Enable */
+#define USART_CR3_IRLP 0x0004U /*!<IrDA Low-Power */
+#define USART_CR3_HDSEL 0x0008U /*!<Half-Duplex Selection */
+#define USART_CR3_NACK 0x0010U /*!<Smartcard NACK enable */
+#define USART_CR3_SCEN 0x0020U /*!<Smartcard mode enable */
+#define USART_CR3_DMAR 0x0040U /*!<DMA Enable Receiver */
+#define USART_CR3_DMAT 0x0080U /*!<DMA Enable Transmitter */
+#define USART_CR3_RTSE 0x0100U /*!<RTS Enable */
+#define USART_CR3_CTSE 0x0200U /*!<CTS Enable */
+#define USART_CR3_CTSIE 0x0400U /*!<CTS Interrupt Enable */
+#define USART_CR3_ONEBIT 0x0800U /*!<USART One bit method enable */
+
+/****************** Bit definition for USART_GTPR register ******************/
+#define USART_GTPR_PSC 0x00FFU /*!<PSC[7:0] bits (Prescaler value) */
+#define USART_GTPR_PSC_0 0x0001U /*!<Bit 0 */
+#define USART_GTPR_PSC_1 0x0002U /*!<Bit 1 */
+#define USART_GTPR_PSC_2 0x0004U /*!<Bit 2 */
+#define USART_GTPR_PSC_3 0x0008U /*!<Bit 3 */
+#define USART_GTPR_PSC_4 0x0010U /*!<Bit 4 */
+#define USART_GTPR_PSC_5 0x0020U /*!<Bit 5 */
+#define USART_GTPR_PSC_6 0x0040U /*!<Bit 6 */
+#define USART_GTPR_PSC_7 0x0080U /*!<Bit 7 */
+
+#define USART_GTPR_GT 0xFF00U /*!<Guard time value */
+
+/******************************************************************************/
+/* */
+/* Window WATCHDOG */
+/* */
+/******************************************************************************/
+/******************* Bit definition for WWDG_CR register ********************/
+#define WWDG_CR_T 0x7FU /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
+#define WWDG_CR_T_0 0x01U /*!<Bit 0 */
+#define WWDG_CR_T_1 0x02U /*!<Bit 1 */
+#define WWDG_CR_T_2 0x04U /*!<Bit 2 */
+#define WWDG_CR_T_3 0x08U /*!<Bit 3 */
+#define WWDG_CR_T_4 0x10U /*!<Bit 4 */
+#define WWDG_CR_T_5 0x20U /*!<Bit 5 */
+#define WWDG_CR_T_6 0x40U /*!<Bit 6 */
+/* Legacy defines */
+#define WWDG_CR_T0 WWDG_CR_T_0
+#define WWDG_CR_T1 WWDG_CR_T_1
+#define WWDG_CR_T2 WWDG_CR_T_2
+#define WWDG_CR_T3 WWDG_CR_T_3
+#define WWDG_CR_T4 WWDG_CR_T_4
+#define WWDG_CR_T5 WWDG_CR_T_5
+#define WWDG_CR_T6 WWDG_CR_T_6
+
+#define WWDG_CR_WDGA 0x80U /*!<Activation bit */
+
+/******************* Bit definition for WWDG_CFR register *******************/
+#define WWDG_CFR_W 0x007FU /*!<W[6:0] bits (7-bit window value) */
+#define WWDG_CFR_W_0 0x0001U /*!<Bit 0 */
+#define WWDG_CFR_W_1 0x0002U /*!<Bit 1 */
+#define WWDG_CFR_W_2 0x0004U /*!<Bit 2 */
+#define WWDG_CFR_W_3 0x0008U /*!<Bit 3 */
+#define WWDG_CFR_W_4 0x0010U /*!<Bit 4 */
+#define WWDG_CFR_W_5 0x0020U /*!<Bit 5 */
+#define WWDG_CFR_W_6 0x0040U /*!<Bit 6 */
+/* Legacy defines */
+#define WWDG_CFR_W0 WWDG_CFR_W_0
+#define WWDG_CFR_W1 WWDG_CFR_W_1
+#define WWDG_CFR_W2 WWDG_CFR_W_2
+#define WWDG_CFR_W3 WWDG_CFR_W_3
+#define WWDG_CFR_W4 WWDG_CFR_W_4
+#define WWDG_CFR_W5 WWDG_CFR_W_5
+#define WWDG_CFR_W6 WWDG_CFR_W_6
+
+#define WWDG_CFR_WDGTB 0x0180U /*!<WDGTB[1:0] bits (Timer Base) */
+#define WWDG_CFR_WDGTB_0 0x0080U /*!<Bit 0 */
+#define WWDG_CFR_WDGTB_1 0x0100U /*!<Bit 1 */
+/* Legacy defines */
+#define WWDG_CFR_WDGTB0 WWDG_CFR_WDGTB_0
+#define WWDG_CFR_WDGTB1 WWDG_CFR_WDGTB_1
+
+#define WWDG_CFR_EWI 0x0200U /*!<Early Wakeup Interrupt */
+
+/******************* Bit definition for WWDG_SR register ********************/
+#define WWDG_SR_EWIF 0x01U /*!<Early Wakeup Interrupt Flag */
+
+
+/******************************************************************************/
+/* */
+/* DBG */
+/* */
+/******************************************************************************/
+/******************** Bit definition for DBGMCU_IDCODE register *************/
+#define DBGMCU_IDCODE_DEV_ID 0x00000FFFU
+#define DBGMCU_IDCODE_REV_ID 0xFFFF0000U
+
+/******************** Bit definition for DBGMCU_CR register *****************/
+#define DBGMCU_CR_DBG_SLEEP 0x00000001U
+#define DBGMCU_CR_DBG_STOP 0x00000002U
+#define DBGMCU_CR_DBG_STANDBY 0x00000004U
+#define DBGMCU_CR_TRACE_IOEN 0x00000020U
+
+#define DBGMCU_CR_TRACE_MODE 0x000000C0U
+#define DBGMCU_CR_TRACE_MODE_0 0x00000040U/*!<Bit 0 */
+#define DBGMCU_CR_TRACE_MODE_1 0x00000080U/*!<Bit 1 */
+
+/******************** Bit definition for DBGMCU_APB1_FZ register ************/
+#define DBGMCU_APB1_FZ_DBG_TIM2_STOP 0x00000001U
+#define DBGMCU_APB1_FZ_DBG_TIM3_STOP 0x00000002U
+#define DBGMCU_APB1_FZ_DBG_TIM4_STOP 0x00000004U
+#define DBGMCU_APB1_FZ_DBG_TIM5_STOP 0x00000008U
+#define DBGMCU_APB1_FZ_DBG_TIM6_STOP 0x00000010U
+#define DBGMCU_APB1_FZ_DBG_TIM7_STOP 0x00000020U
+#define DBGMCU_APB1_FZ_DBG_TIM12_STOP 0x00000040U
+#define DBGMCU_APB1_FZ_DBG_TIM13_STOP 0x00000080U
+#define DBGMCU_APB1_FZ_DBG_TIM14_STOP 0x00000100U
+#define DBGMCU_APB1_FZ_DBG_RTC_STOP 0x00000400U
+#define DBGMCU_APB1_FZ_DBG_WWDG_STOP 0x00000800U
+#define DBGMCU_APB1_FZ_DBG_IWDG_STOP 0x00001000U
+#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT 0x00200000U
+#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT 0x00400000U
+#define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT 0x00800000U
+#define DBGMCU_APB1_FZ_DBG_CAN1_STOP 0x02000000U
+#define DBGMCU_APB1_FZ_DBG_CAN2_STOP 0x04000000U
+/* Old IWDGSTOP bit definition, maintained for legacy purpose */
+#define DBGMCU_APB1_FZ_DBG_IWDEG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP
+
+/******************** Bit definition for DBGMCU_APB2_FZ register ************/
+#define DBGMCU_APB2_FZ_DBG_TIM1_STOP 0x00000001U
+#define DBGMCU_APB2_FZ_DBG_TIM8_STOP 0x00000002U
+#define DBGMCU_APB2_FZ_DBG_TIM9_STOP 0x00010000U
+#define DBGMCU_APB2_FZ_DBG_TIM10_STOP 0x00020000U
+#define DBGMCU_APB2_FZ_DBG_TIM11_STOP 0x00040000U
+
+/******************************************************************************/
+/* */
+/* Ethernet MAC Registers bits definitions */
+/* */
+/******************************************************************************/
+/* Bit definition for Ethernet MAC Control Register register */
+#define ETH_MACCR_WD 0x00800000U /* Watchdog disable */
+#define ETH_MACCR_JD 0x00400000U /* Jabber disable */
+#define ETH_MACCR_IFG 0x000E0000U /* Inter-frame gap */
+#define ETH_MACCR_IFG_96Bit 0x00000000U /* Minimum IFG between frames during transmission is 96Bit */
+ #define ETH_MACCR_IFG_88Bit 0x00020000U /* Minimum IFG between frames during transmission is 88Bit */
+ #define ETH_MACCR_IFG_80Bit 0x00040000U /* Minimum IFG between frames during transmission is 80Bit */
+ #define ETH_MACCR_IFG_72Bit 0x00060000U /* Minimum IFG between frames during transmission is 72Bit */
+ #define ETH_MACCR_IFG_64Bit 0x00080000U /* Minimum IFG between frames during transmission is 64Bit */
+ #define ETH_MACCR_IFG_56Bit 0x000A0000U /* Minimum IFG between frames during transmission is 56Bit */
+ #define ETH_MACCR_IFG_48Bit 0x000C0000U /* Minimum IFG between frames during transmission is 48Bit */
+ #define ETH_MACCR_IFG_40Bit 0x000E0000U /* Minimum IFG between frames during transmission is 40Bit */
+#define ETH_MACCR_CSD 0x00010000U /* Carrier sense disable (during transmission) */
+#define ETH_MACCR_FES 0x00004000U /* Fast ethernet speed */
+#define ETH_MACCR_ROD 0x00002000U /* Receive own disable */
+#define ETH_MACCR_LM 0x00001000U /* loopback mode */
+#define ETH_MACCR_DM 0x00000800U /* Duplex mode */
+#define ETH_MACCR_IPCO 0x00000400U /* IP Checksum offload */
+#define ETH_MACCR_RD 0x00000200U /* Retry disable */
+#define ETH_MACCR_APCS 0x00000080U /* Automatic Pad/CRC stripping */
+#define ETH_MACCR_BL 0x00000060U /* Back-off limit: random integer number (r) of slot time delays before rescheduling
+ a transmission attempt during retries after a collision: 0 =< r <2^k */
+ #define ETH_MACCR_BL_10 0x00000000U /* k = min (n, 10) */
+ #define ETH_MACCR_BL_8 0x00000020U /* k = min (n, 8) */
+ #define ETH_MACCR_BL_4 0x00000040U /* k = min (n, 4) */
+ #define ETH_MACCR_BL_1 0x00000060U /* k = min (n, 1) */
+#define ETH_MACCR_DC 0x00000010U /* Defferal check */
+#define ETH_MACCR_TE 0x00000008U /* Transmitter enable */
+#define ETH_MACCR_RE 0x00000004U /* Receiver enable */
+
+/* Bit definition for Ethernet MAC Frame Filter Register */
+#define ETH_MACFFR_RA 0x80000000U /* Receive all */
+#define ETH_MACFFR_HPF 0x00000400U /* Hash or perfect filter */
+#define ETH_MACFFR_SAF 0x00000200U /* Source address filter enable */
+#define ETH_MACFFR_SAIF 0x00000100U /* SA inverse filtering */
+#define ETH_MACFFR_PCF 0x000000C0U /* Pass control frames: 3 cases */
+ #define ETH_MACFFR_PCF_BlockAll 0x00000040U /* MAC filters all control frames from reaching the application */
+ #define ETH_MACFFR_PCF_ForwardAll 0x00000080U /* MAC forwards all control frames to application even if they fail the Address Filter */
+ #define ETH_MACFFR_PCF_ForwardPassedAddrFilter 0x000000C0U /* MAC forwards control frames that pass the Address Filter. */
+#define ETH_MACFFR_BFD 0x00000020U /* Broadcast frame disable */
+#define ETH_MACFFR_PAM 0x00000010U /* Pass all mutlicast */
+#define ETH_MACFFR_DAIF 0x00000008U /* DA Inverse filtering */
+#define ETH_MACFFR_HM 0x00000004U /* Hash multicast */
+#define ETH_MACFFR_HU 0x00000002U /* Hash unicast */
+#define ETH_MACFFR_PM 0x00000001U /* Promiscuous mode */
+
+/* Bit definition for Ethernet MAC Hash Table High Register */
+#define ETH_MACHTHR_HTH 0xFFFFFFFFU /* Hash table high */
+
+/* Bit definition for Ethernet MAC Hash Table Low Register */
+#define ETH_MACHTLR_HTL 0xFFFFFFFFU /* Hash table low */
+
+/* Bit definition for Ethernet MAC MII Address Register */
+#define ETH_MACMIIAR_PA 0x0000F800U /* Physical layer address */
+#define ETH_MACMIIAR_MR 0x000007C0U /* MII register in the selected PHY */
+#define ETH_MACMIIAR_CR 0x0000001CU /* CR clock range: 6 cases */
+ #define ETH_MACMIIAR_CR_Div42 0x00000000U /* HCLK:60-100 MHz; MDC clock= HCLK/42 */
+ #define ETH_MACMIIAR_CR_Div62 0x00000004U /* HCLK:100-150 MHz; MDC clock= HCLK/62 */
+ #define ETH_MACMIIAR_CR_Div16 0x00000008U /* HCLK:20-35 MHz; MDC clock= HCLK/16 */
+ #define ETH_MACMIIAR_CR_Div26 0x0000000CU /* HCLK:35-60 MHz; MDC clock= HCLK/26 */
+ #define ETH_MACMIIAR_CR_Div102 0x00000010U /* HCLK:150-168 MHz; MDC clock= HCLK/102 */
+#define ETH_MACMIIAR_MW 0x00000002U /* MII write */
+#define ETH_MACMIIAR_MB 0x00000001U /* MII busy */
+
+/* Bit definition for Ethernet MAC MII Data Register */
+#define ETH_MACMIIDR_MD 0x0000FFFFU /* MII data: read/write data from/to PHY */
+
+/* Bit definition for Ethernet MAC Flow Control Register */
+#define ETH_MACFCR_PT 0xFFFF0000U /* Pause time */
+#define ETH_MACFCR_ZQPD 0x00000080U /* Zero-quanta pause disable */
+#define ETH_MACFCR_PLT 0x00000030U /* Pause low threshold: 4 cases */
+ #define ETH_MACFCR_PLT_Minus4 0x00000000U /* Pause time minus 4 slot times */
+ #define ETH_MACFCR_PLT_Minus28 0x00000010U /* Pause time minus 28 slot times */
+ #define ETH_MACFCR_PLT_Minus144 0x00000020U /* Pause time minus 144 slot times */
+ #define ETH_MACFCR_PLT_Minus256 0x00000030U /* Pause time minus 256 slot times */
+#define ETH_MACFCR_UPFD 0x00000008U /* Unicast pause frame detect */
+#define ETH_MACFCR_RFCE 0x00000004U /* Receive flow control enable */
+#define ETH_MACFCR_TFCE 0x00000002U /* Transmit flow control enable */
+#define ETH_MACFCR_FCBBPA 0x00000001U /* Flow control busy/backpressure activate */
+
+/* Bit definition for Ethernet MAC VLAN Tag Register */
+#define ETH_MACVLANTR_VLANTC 0x00010000U /* 12-bit VLAN tag comparison */
+#define ETH_MACVLANTR_VLANTI 0x0000FFFFU /* VLAN tag identifier (for receive frames) */
+
+/* Bit definition for Ethernet MAC Remote Wake-UpFrame Filter Register */
+#define ETH_MACRWUFFR_D 0xFFFFFFFFU /* Wake-up frame filter register data */
+/* Eight sequential Writes to this address (offset 0x28) will write all Wake-UpFrame Filter Registers.
+ Eight sequential Reads from this address (offset 0x28) will read all Wake-UpFrame Filter Registers. */
+/* Wake-UpFrame Filter Reg0 : Filter 0 Byte Mask
+ Wake-UpFrame Filter Reg1 : Filter 1 Byte Mask
+ Wake-UpFrame Filter Reg2 : Filter 2 Byte Mask
+ Wake-UpFrame Filter Reg3 : Filter 3 Byte Mask
+ Wake-UpFrame Filter Reg4 : RSVD - Filter3 Command - RSVD - Filter2 Command -
+ RSVD - Filter1 Command - RSVD - Filter0 Command
+ Wake-UpFrame Filter Re5 : Filter3 Offset - Filter2 Offset - Filter1 Offset - Filter0 Offset
+ Wake-UpFrame Filter Re6 : Filter1 CRC16 - Filter0 CRC16
+ Wake-UpFrame Filter Re7 : Filter3 CRC16 - Filter2 CRC16 */
+
+/* Bit definition for Ethernet MAC PMT Control and Status Register */
+#define ETH_MACPMTCSR_WFFRPR 0x80000000U /* Wake-Up Frame Filter Register Pointer Reset */
+#define ETH_MACPMTCSR_GU 0x00000200U /* Global Unicast */
+#define ETH_MACPMTCSR_WFR 0x00000040U /* Wake-Up Frame Received */
+#define ETH_MACPMTCSR_MPR 0x00000020U /* Magic Packet Received */
+#define ETH_MACPMTCSR_WFE 0x00000004U /* Wake-Up Frame Enable */
+#define ETH_MACPMTCSR_MPE 0x00000002U /* Magic Packet Enable */
+#define ETH_MACPMTCSR_PD 0x00000001U /* Power Down */
+
+/* Bit definition for Ethernet MAC Status Register */
+#define ETH_MACSR_TSTS 0x00000200U /* Time stamp trigger status */
+#define ETH_MACSR_MMCTS 0x00000040U /* MMC transmit status */
+#define ETH_MACSR_MMMCRS 0x00000020U /* MMC receive status */
+#define ETH_MACSR_MMCS 0x00000010U /* MMC status */
+#define ETH_MACSR_PMTS 0x00000008U /* PMT status */
+
+/* Bit definition for Ethernet MAC Interrupt Mask Register */
+#define ETH_MACIMR_TSTIM 0x00000200U /* Time stamp trigger interrupt mask */
+#define ETH_MACIMR_PMTIM 0x00000008U /* PMT interrupt mask */
+
+/* Bit definition for Ethernet MAC Address0 High Register */
+#define ETH_MACA0HR_MACA0H 0x0000FFFFU /* MAC address0 high */
+
+/* Bit definition for Ethernet MAC Address0 Low Register */
+#define ETH_MACA0LR_MACA0L 0xFFFFFFFFU /* MAC address0 low */
+
+/* Bit definition for Ethernet MAC Address1 High Register */
+#define ETH_MACA1HR_AE 0x80000000U /* Address enable */
+#define ETH_MACA1HR_SA 0x40000000U /* Source address */
+#define ETH_MACA1HR_MBC 0x3F000000U /* Mask byte control: bits to mask for comparison of the MAC Address bytes */
+ #define ETH_MACA1HR_MBC_HBits15_8 0x20000000U /* Mask MAC Address high reg bits [15:8] */
+ #define ETH_MACA1HR_MBC_HBits7_0 0x10000000U /* Mask MAC Address high reg bits [7:0] */
+ #define ETH_MACA1HR_MBC_LBits31_24 0x08000000U /* Mask MAC Address low reg bits [31:24] */
+ #define ETH_MACA1HR_MBC_LBits23_16 0x04000000U /* Mask MAC Address low reg bits [23:16] */
+ #define ETH_MACA1HR_MBC_LBits15_8 0x02000000U /* Mask MAC Address low reg bits [15:8] */
+ #define ETH_MACA1HR_MBC_LBits7_0 0x01000000U /* Mask MAC Address low reg bits [7:0] */
+#define ETH_MACA1HR_MACA1H 0x0000FFFFU /* MAC address1 high */
+
+/* Bit definition for Ethernet MAC Address1 Low Register */
+#define ETH_MACA1LR_MACA1L 0xFFFFFFFFU /* MAC address1 low */
+
+/* Bit definition for Ethernet MAC Address2 High Register */
+#define ETH_MACA2HR_AE 0x80000000U /* Address enable */
+#define ETH_MACA2HR_SA 0x40000000U /* Source address */
+#define ETH_MACA2HR_MBC 0x3F000000U /* Mask byte control */
+ #define ETH_MACA2HR_MBC_HBits15_8 0x20000000U /* Mask MAC Address high reg bits [15:8] */
+ #define ETH_MACA2HR_MBC_HBits7_0 0x10000000U /* Mask MAC Address high reg bits [7:0] */
+ #define ETH_MACA2HR_MBC_LBits31_24 0x08000000U /* Mask MAC Address low reg bits [31:24] */
+ #define ETH_MACA2HR_MBC_LBits23_16 0x04000000U /* Mask MAC Address low reg bits [23:16] */
+ #define ETH_MACA2HR_MBC_LBits15_8 0x02000000U /* Mask MAC Address low reg bits [15:8] */
+ #define ETH_MACA2HR_MBC_LBits7_0 0x01000000U /* Mask MAC Address low reg bits [70] */
+#define ETH_MACA2HR_MACA2H 0x0000FFFFU /* MAC address1 high */
+
+/* Bit definition for Ethernet MAC Address2 Low Register */
+#define ETH_MACA2LR_MACA2L 0xFFFFFFFFU /* MAC address2 low */
+
+/* Bit definition for Ethernet MAC Address3 High Register */
+#define ETH_MACA3HR_AE 0x80000000U /* Address enable */
+#define ETH_MACA3HR_SA 0x40000000U /* Source address */
+#define ETH_MACA3HR_MBC 0x3F000000U /* Mask byte control */
+ #define ETH_MACA3HR_MBC_HBits15_8 0x20000000U /* Mask MAC Address high reg bits [15:8] */
+ #define ETH_MACA3HR_MBC_HBits7_0 0x10000000U /* Mask MAC Address high reg bits [7:0] */
+ #define ETH_MACA3HR_MBC_LBits31_24 0x08000000U /* Mask MAC Address low reg bits [31:24] */
+ #define ETH_MACA3HR_MBC_LBits23_16 0x04000000U /* Mask MAC Address low reg bits [23:16] */
+ #define ETH_MACA3HR_MBC_LBits15_8 0x02000000U /* Mask MAC Address low reg bits [15:8] */
+ #define ETH_MACA3HR_MBC_LBits7_0 0x01000000U /* Mask MAC Address low reg bits [70] */
+#define ETH_MACA3HR_MACA3H 0x0000FFFFU /* MAC address3 high */
+
+/* Bit definition for Ethernet MAC Address3 Low Register */
+#define ETH_MACA3LR_MACA3L 0xFFFFFFFFU /* MAC address3 low */
+
+/******************************************************************************/
+/* Ethernet MMC Registers bits definition */
+/******************************************************************************/
+
+/* Bit definition for Ethernet MMC Contol Register */
+#define ETH_MMCCR_MCFHP 0x00000020U /* MMC counter Full-Half preset */
+#define ETH_MMCCR_MCP 0x00000010U /* MMC counter preset */
+#define ETH_MMCCR_MCF 0x00000008U /* MMC Counter Freeze */
+#define ETH_MMCCR_ROR 0x00000004U /* Reset on Read */
+#define ETH_MMCCR_CSR 0x00000002U /* Counter Stop Rollover */
+#define ETH_MMCCR_CR 0x00000001U /* Counters Reset */
+
+/* Bit definition for Ethernet MMC Receive Interrupt Register */
+#define ETH_MMCRIR_RGUFS 0x00020000U /* Set when Rx good unicast frames counter reaches half the maximum value */
+#define ETH_MMCRIR_RFAES 0x00000040U /* Set when Rx alignment error counter reaches half the maximum value */
+#define ETH_MMCRIR_RFCES 0x00000020U /* Set when Rx crc error counter reaches half the maximum value */
+
+/* Bit definition for Ethernet MMC Transmit Interrupt Register */
+#define ETH_MMCTIR_TGFS 0x00200000U /* Set when Tx good frame count counter reaches half the maximum value */
+#define ETH_MMCTIR_TGFMSCS 0x00008000U /* Set when Tx good multi col counter reaches half the maximum value */
+#define ETH_MMCTIR_TGFSCS 0x00004000U /* Set when Tx good single col counter reaches half the maximum value */
+
+/* Bit definition for Ethernet MMC Receive Interrupt Mask Register */
+#define ETH_MMCRIMR_RGUFM 0x00020000U /* Mask the interrupt when Rx good unicast frames counter reaches half the maximum value */
+#define ETH_MMCRIMR_RFAEM 0x00000040U /* Mask the interrupt when when Rx alignment error counter reaches half the maximum value */
+#define ETH_MMCRIMR_RFCEM 0x00000020U /* Mask the interrupt when Rx crc error counter reaches half the maximum value */
+
+/* Bit definition for Ethernet MMC Transmit Interrupt Mask Register */
+#define ETH_MMCTIMR_TGFM 0x00200000U /* Mask the interrupt when Tx good frame count counter reaches half the maximum value */
+#define ETH_MMCTIMR_TGFMSCM 0x00008000U /* Mask the interrupt when Tx good multi col counter reaches half the maximum value */
+#define ETH_MMCTIMR_TGFSCM 0x00004000U /* Mask the interrupt when Tx good single col counter reaches half the maximum value */
+
+/* Bit definition for Ethernet MMC Transmitted Good Frames after Single Collision Counter Register */
+#define ETH_MMCTGFSCCR_TGFSCC 0xFFFFFFFFU /* Number of successfully transmitted frames after a single collision in Half-duplex mode. */
+
+/* Bit definition for Ethernet MMC Transmitted Good Frames after More than a Single Collision Counter Register */
+#define ETH_MMCTGFMSCCR_TGFMSCC 0xFFFFFFFFU /* Number of successfully transmitted frames after more than a single collision in Half-duplex mode. */
+
+/* Bit definition for Ethernet MMC Transmitted Good Frames Counter Register */
+#define ETH_MMCTGFCR_TGFC 0xFFFFFFFFU /* Number of good frames transmitted. */
+
+/* Bit definition for Ethernet MMC Received Frames with CRC Error Counter Register */
+#define ETH_MMCRFCECR_RFCEC 0xFFFFFFFFU /* Number of frames received with CRC error. */
+
+/* Bit definition for Ethernet MMC Received Frames with Alignement Error Counter Register */
+#define ETH_MMCRFAECR_RFAEC 0xFFFFFFFFU /* Number of frames received with alignment (dribble) error */
+
+/* Bit definition for Ethernet MMC Received Good Unicast Frames Counter Register */
+#define ETH_MMCRGUFCR_RGUFC 0xFFFFFFFFU /* Number of good unicast frames received. */
+
+/******************************************************************************/
+/* Ethernet PTP Registers bits definition */
+/******************************************************************************/
+
+/* Bit definition for Ethernet PTP Time Stamp Contol Register */
+#define ETH_PTPTSCR_TSCNT 0x00030000U /* Time stamp clock node type */
+#define ETH_PTPTSSR_TSSMRME 0x00008000U /* Time stamp snapshot for message relevant to master enable */
+#define ETH_PTPTSSR_TSSEME 0x00004000U /* Time stamp snapshot for event message enable */
+#define ETH_PTPTSSR_TSSIPV4FE 0x00002000U /* Time stamp snapshot for IPv4 frames enable */
+#define ETH_PTPTSSR_TSSIPV6FE 0x00001000U /* Time stamp snapshot for IPv6 frames enable */
+#define ETH_PTPTSSR_TSSPTPOEFE 0x00000800U /* Time stamp snapshot for PTP over ethernet frames enable */
+#define ETH_PTPTSSR_TSPTPPSV2E 0x00000400U /* Time stamp PTP packet snooping for version2 format enable */
+#define ETH_PTPTSSR_TSSSR 0x00000200U /* Time stamp Sub-seconds rollover */
+#define ETH_PTPTSSR_TSSARFE 0x00000100U /* Time stamp snapshot for all received frames enable */
+
+#define ETH_PTPTSCR_TSARU 0x00000020U /* Addend register update */
+#define ETH_PTPTSCR_TSITE 0x00000010U /* Time stamp interrupt trigger enable */
+#define ETH_PTPTSCR_TSSTU 0x00000008U /* Time stamp update */
+#define ETH_PTPTSCR_TSSTI 0x00000004U /* Time stamp initialize */
+#define ETH_PTPTSCR_TSFCU 0x00000002U /* Time stamp fine or coarse update */
+#define ETH_PTPTSCR_TSE 0x00000001U /* Time stamp enable */
+
+/* Bit definition for Ethernet PTP Sub-Second Increment Register */
+#define ETH_PTPSSIR_STSSI 0x000000FFU /* System time Sub-second increment value */
+
+/* Bit definition for Ethernet PTP Time Stamp High Register */
+#define ETH_PTPTSHR_STS 0xFFFFFFFFU /* System Time second */
+
+/* Bit definition for Ethernet PTP Time Stamp Low Register */
+#define ETH_PTPTSLR_STPNS 0x80000000U /* System Time Positive or negative time */
+#define ETH_PTPTSLR_STSS 0x7FFFFFFFU /* System Time sub-seconds */
+
+/* Bit definition for Ethernet PTP Time Stamp High Update Register */
+#define ETH_PTPTSHUR_TSUS 0xFFFFFFFFU /* Time stamp update seconds */
+
+/* Bit definition for Ethernet PTP Time Stamp Low Update Register */
+#define ETH_PTPTSLUR_TSUPNS 0x80000000U /* Time stamp update Positive or negative time */
+#define ETH_PTPTSLUR_TSUSS 0x7FFFFFFFU /* Time stamp update sub-seconds */
+
+/* Bit definition for Ethernet PTP Time Stamp Addend Register */
+#define ETH_PTPTSAR_TSA 0xFFFFFFFFU /* Time stamp addend */
+
+/* Bit definition for Ethernet PTP Target Time High Register */
+#define ETH_PTPTTHR_TTSH 0xFFFFFFFFU /* Target time stamp high */
+
+/* Bit definition for Ethernet PTP Target Time Low Register */
+#define ETH_PTPTTLR_TTSL 0xFFFFFFFFU /* Target time stamp low */
+
+/* Bit definition for Ethernet PTP Time Stamp Status Register */
+#define ETH_PTPTSSR_TSTTR 0x00000020U /* Time stamp target time reached */
+#define ETH_PTPTSSR_TSSO 0x00000010U /* Time stamp seconds overflow */
+
+/******************************************************************************/
+/* Ethernet DMA Registers bits definition */
+/******************************************************************************/
+
+/* Bit definition for Ethernet DMA Bus Mode Register */
+#define ETH_DMABMR_AAB 0x02000000U /* Address-Aligned beats */
+#define ETH_DMABMR_FPM 0x01000000U /* 4xPBL mode */
+#define ETH_DMABMR_USP 0x00800000U /* Use separate PBL */
+#define ETH_DMABMR_RDP 0x007E0000U /* RxDMA PBL */
+ #define ETH_DMABMR_RDP_1Beat 0x00020000U /* maximum number of beats to be transferred in one RxDMA transaction is 1 */
+ #define ETH_DMABMR_RDP_2Beat 0x00040000U /* maximum number of beats to be transferred in one RxDMA transaction is 2 */
+ #define ETH_DMABMR_RDP_4Beat 0x00080000U /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
+ #define ETH_DMABMR_RDP_8Beat 0x00100000U /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
+ #define ETH_DMABMR_RDP_16Beat 0x00200000U /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
+ #define ETH_DMABMR_RDP_32Beat 0x00400000U /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
+ #define ETH_DMABMR_RDP_4xPBL_4Beat 0x01020000U /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
+ #define ETH_DMABMR_RDP_4xPBL_8Beat 0x01040000U /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
+ #define ETH_DMABMR_RDP_4xPBL_16Beat 0x01080000U /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
+ #define ETH_DMABMR_RDP_4xPBL_32Beat 0x01100000U /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
+ #define ETH_DMABMR_RDP_4xPBL_64Beat 0x01200000U /* maximum number of beats to be transferred in one RxDMA transaction is 64 */
+ #define ETH_DMABMR_RDP_4xPBL_128Beat 0x01400000U /* maximum number of beats to be transferred in one RxDMA transaction is 128 */
+#define ETH_DMABMR_FB 0x00010000U /* Fixed Burst */
+#define ETH_DMABMR_RTPR 0x0000C000U /* Rx Tx priority ratio */
+ #define ETH_DMABMR_RTPR_1_1 0x00000000U /* Rx Tx priority ratio */
+ #define ETH_DMABMR_RTPR_2_1 0x00004000U /* Rx Tx priority ratio */
+ #define ETH_DMABMR_RTPR_3_1 0x00008000U /* Rx Tx priority ratio */
+ #define ETH_DMABMR_RTPR_4_1 0x0000C000U /* Rx Tx priority ratio */
+#define ETH_DMABMR_PBL 0x00003F00U /* Programmable burst length */
+ #define ETH_DMABMR_PBL_1Beat 0x00000100U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */
+ #define ETH_DMABMR_PBL_2Beat 0x00000200U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */
+ #define ETH_DMABMR_PBL_4Beat 0x00000400U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
+ #define ETH_DMABMR_PBL_8Beat 0x00000800U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
+ #define ETH_DMABMR_PBL_16Beat 0x00001000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
+ #define ETH_DMABMR_PBL_32Beat 0x00002000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
+ #define ETH_DMABMR_PBL_4xPBL_4Beat 0x01000100U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
+ #define ETH_DMABMR_PBL_4xPBL_8Beat 0x01000200U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
+ #define ETH_DMABMR_PBL_4xPBL_16Beat 0x01000400U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
+ #define ETH_DMABMR_PBL_4xPBL_32Beat 0x01000800U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
+ #define ETH_DMABMR_PBL_4xPBL_64Beat 0x01001000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */
+ #define ETH_DMABMR_PBL_4xPBL_128Beat 0x01002000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */
+#define ETH_DMABMR_EDE 0x00000080U /* Enhanced Descriptor Enable */
+#define ETH_DMABMR_DSL 0x0000007CU /* Descriptor Skip Length */
+#define ETH_DMABMR_DA 0x00000002U /* DMA arbitration scheme */
+#define ETH_DMABMR_SR 0x00000001U /* Software reset */
+
+/* Bit definition for Ethernet DMA Transmit Poll Demand Register */
+#define ETH_DMATPDR_TPD 0xFFFFFFFFU /* Transmit poll demand */
+
+/* Bit definition for Ethernet DMA Receive Poll Demand Register */
+#define ETH_DMARPDR_RPD 0xFFFFFFFFU /* Receive poll demand */
+
+/* Bit definition for Ethernet DMA Receive Descriptor List Address Register */
+#define ETH_DMARDLAR_SRL 0xFFFFFFFFU /* Start of receive list */
+
+/* Bit definition for Ethernet DMA Transmit Descriptor List Address Register */
+#define ETH_DMATDLAR_STL 0xFFFFFFFFU /* Start of transmit list */
+
+/* Bit definition for Ethernet DMA Status Register */
+#define ETH_DMASR_TSTS 0x20000000U /* Time-stamp trigger status */
+#define ETH_DMASR_PMTS 0x10000000U /* PMT status */
+#define ETH_DMASR_MMCS 0x08000000U /* MMC status */
+#define ETH_DMASR_EBS 0x03800000U /* Error bits status */
+ /* combination with EBS[2:0] for GetFlagStatus function */
+ #define ETH_DMASR_EBS_DescAccess 0x02000000U /* Error bits 0-data buffer, 1-desc. access */
+ #define ETH_DMASR_EBS_ReadTransf 0x01000000U /* Error bits 0-write trnsf, 1-read transfr */
+ #define ETH_DMASR_EBS_DataTransfTx 0x00800000U /* Error bits 0-Rx DMA, 1-Tx DMA */
+#define ETH_DMASR_TPS 0x00700000U /* Transmit process state */
+ #define ETH_DMASR_TPS_Stopped 0x00000000U /* Stopped - Reset or Stop Tx Command issued */
+ #define ETH_DMASR_TPS_Fetching 0x00100000U /* Running - fetching the Tx descriptor */
+ #define ETH_DMASR_TPS_Waiting 0x00200000U /* Running - waiting for status */
+ #define ETH_DMASR_TPS_Reading 0x00300000U /* Running - reading the data from host memory */
+ #define ETH_DMASR_TPS_Suspended 0x00600000U /* Suspended - Tx Descriptor unavailabe */
+ #define ETH_DMASR_TPS_Closing 0x00700000U /* Running - closing Rx descriptor */
+#define ETH_DMASR_RPS 0x000E0000U /* Receive process state */
+ #define ETH_DMASR_RPS_Stopped 0x00000000U /* Stopped - Reset or Stop Rx Command issued */
+ #define ETH_DMASR_RPS_Fetching 0x00020000U /* Running - fetching the Rx descriptor */
+ #define ETH_DMASR_RPS_Waiting 0x00060000U /* Running - waiting for packet */
+ #define ETH_DMASR_RPS_Suspended 0x00080000U /* Suspended - Rx Descriptor unavailable */
+ #define ETH_DMASR_RPS_Closing 0x000A0000U /* Running - closing descriptor */
+ #define ETH_DMASR_RPS_Queuing 0x000E0000U /* Running - queuing the recieve frame into host memory */
+#define ETH_DMASR_NIS 0x00010000U /* Normal interrupt summary */
+#define ETH_DMASR_AIS 0x00008000U /* Abnormal interrupt summary */
+#define ETH_DMASR_ERS 0x00004000U /* Early receive status */
+#define ETH_DMASR_FBES 0x00002000U /* Fatal bus error status */
+#define ETH_DMASR_ETS 0x00000400U /* Early transmit status */
+#define ETH_DMASR_RWTS 0x00000200U /* Receive watchdog timeout status */
+#define ETH_DMASR_RPSS 0x00000100U /* Receive process stopped status */
+#define ETH_DMASR_RBUS 0x00000080U /* Receive buffer unavailable status */
+#define ETH_DMASR_RS 0x00000040U /* Receive status */
+#define ETH_DMASR_TUS 0x00000020U /* Transmit underflow status */
+#define ETH_DMASR_ROS 0x00000010U /* Receive overflow status */
+#define ETH_DMASR_TJTS 0x00000008U /* Transmit jabber timeout status */
+#define ETH_DMASR_TBUS 0x00000004U /* Transmit buffer unavailable status */
+#define ETH_DMASR_TPSS 0x00000002U /* Transmit process stopped status */
+#define ETH_DMASR_TS 0x00000001U /* Transmit status */
+
+/* Bit definition for Ethernet DMA Operation Mode Register */
+#define ETH_DMAOMR_DTCEFD 0x04000000U /* Disable Dropping of TCP/IP checksum error frames */
+#define ETH_DMAOMR_RSF 0x02000000U /* Receive store and forward */
+#define ETH_DMAOMR_DFRF 0x01000000U /* Disable flushing of received frames */
+#define ETH_DMAOMR_TSF 0x00200000U /* Transmit store and forward */
+#define ETH_DMAOMR_FTF 0x00100000U /* Flush transmit FIFO */
+#define ETH_DMAOMR_TTC 0x0001C000U /* Transmit threshold control */
+ #define ETH_DMAOMR_TTC_64Bytes 0x00000000U /* threshold level of the MTL Transmit FIFO is 64 Bytes */
+ #define ETH_DMAOMR_TTC_128Bytes 0x00004000U /* threshold level of the MTL Transmit FIFO is 128 Bytes */
+ #define ETH_DMAOMR_TTC_192Bytes 0x00008000U /* threshold level of the MTL Transmit FIFO is 192 Bytes */
+ #define ETH_DMAOMR_TTC_256Bytes 0x0000C000U /* threshold level of the MTL Transmit FIFO is 256 Bytes */
+ #define ETH_DMAOMR_TTC_40Bytes 0x00010000U /* threshold level of the MTL Transmit FIFO is 40 Bytes */
+ #define ETH_DMAOMR_TTC_32Bytes 0x00014000U /* threshold level of the MTL Transmit FIFO is 32 Bytes */
+ #define ETH_DMAOMR_TTC_24Bytes 0x00018000U /* threshold level of the MTL Transmit FIFO is 24 Bytes */
+ #define ETH_DMAOMR_TTC_16Bytes 0x0001C000U /* threshold level of the MTL Transmit FIFO is 16 Bytes */
+#define ETH_DMAOMR_ST 0x00002000U /* Start/stop transmission command */
+#define ETH_DMAOMR_FEF 0x00000080U /* Forward error frames */
+#define ETH_DMAOMR_FUGF 0x00000040U /* Forward undersized good frames */
+#define ETH_DMAOMR_RTC 0x00000018U /* receive threshold control */
+ #define ETH_DMAOMR_RTC_64Bytes 0x00000000U /* threshold level of the MTL Receive FIFO is 64 Bytes */
+ #define ETH_DMAOMR_RTC_32Bytes 0x00000008U /* threshold level of the MTL Receive FIFO is 32 Bytes */
+ #define ETH_DMAOMR_RTC_96Bytes 0x00000010U /* threshold level of the MTL Receive FIFO is 96 Bytes */
+ #define ETH_DMAOMR_RTC_128Bytes 0x00000018U /* threshold level of the MTL Receive FIFO is 128 Bytes */
+#define ETH_DMAOMR_OSF 0x00000004U /* operate on second frame */
+#define ETH_DMAOMR_SR 0x00000002U /* Start/stop receive */
+
+/* Bit definition for Ethernet DMA Interrupt Enable Register */
+#define ETH_DMAIER_NISE 0x00010000U /* Normal interrupt summary enable */
+#define ETH_DMAIER_AISE 0x00008000U /* Abnormal interrupt summary enable */
+#define ETH_DMAIER_ERIE 0x00004000U /* Early receive interrupt enable */
+#define ETH_DMAIER_FBEIE 0x00002000U /* Fatal bus error interrupt enable */
+#define ETH_DMAIER_ETIE 0x00000400U /* Early transmit interrupt enable */
+#define ETH_DMAIER_RWTIE 0x00000200U /* Receive watchdog timeout interrupt enable */
+#define ETH_DMAIER_RPSIE 0x00000100U /* Receive process stopped interrupt enable */
+#define ETH_DMAIER_RBUIE 0x00000080U /* Receive buffer unavailable interrupt enable */
+#define ETH_DMAIER_RIE 0x00000040U /* Receive interrupt enable */
+#define ETH_DMAIER_TUIE 0x00000020U /* Transmit Underflow interrupt enable */
+#define ETH_DMAIER_ROIE 0x00000010U /* Receive Overflow interrupt enable */
+#define ETH_DMAIER_TJTIE 0x00000008U /* Transmit jabber timeout interrupt enable */
+#define ETH_DMAIER_TBUIE 0x00000004U /* Transmit buffer unavailable interrupt enable */
+#define ETH_DMAIER_TPSIE 0x00000002U /* Transmit process stopped interrupt enable */
+#define ETH_DMAIER_TIE 0x00000001U /* Transmit interrupt enable */
+
+/* Bit definition for Ethernet DMA Missed Frame and Buffer Overflow Counter Register */
+#define ETH_DMAMFBOCR_OFOC 0x10000000U /* Overflow bit for FIFO overflow counter */
+#define ETH_DMAMFBOCR_MFA 0x0FFE0000U /* Number of frames missed by the application */
+#define ETH_DMAMFBOCR_OMFC 0x00010000U /* Overflow bit for missed frame counter */
+#define ETH_DMAMFBOCR_MFC 0x0000FFFFU /* Number of frames missed by the controller */
+
+/* Bit definition for Ethernet DMA Current Host Transmit Descriptor Register */
+#define ETH_DMACHTDR_HTDAP 0xFFFFFFFFU /* Host transmit descriptor address pointer */
+
+/* Bit definition for Ethernet DMA Current Host Receive Descriptor Register */
+#define ETH_DMACHRDR_HRDAP 0xFFFFFFFFU /* Host receive descriptor address pointer */
+
+/* Bit definition for Ethernet DMA Current Host Transmit Buffer Address Register */
+#define ETH_DMACHTBAR_HTBAP 0xFFFFFFFFU /* Host transmit buffer address pointer */
+
+/* Bit definition for Ethernet DMA Current Host Receive Buffer Address Register */
+#define ETH_DMACHRBAR_HRBAP 0xFFFFFFFFU /* Host receive buffer address pointer */
+
+/******************************************************************************/
+/* */
+/* USB_OTG */
+/* */
+/******************************************************************************/
+/******************** Bit definition forUSB_OTG_GOTGCTL register ********************/
+#define USB_OTG_GOTGCTL_SRQSCS 0x00000001U /*!< Session request success */
+#define USB_OTG_GOTGCTL_SRQ 0x00000002U /*!< Session request */
+#define USB_OTG_GOTGCTL_VBVALOEN 0x00000004U /*!< VBUS valid override enable */
+#define USB_OTG_GOTGCTL_VBVALOVAL 0x00000008U /*!< VBUS valid override value */
+#define USB_OTG_GOTGCTL_AVALOEN 0x00000010U /*!< A-peripheral session valid override enable */
+#define USB_OTG_GOTGCTL_AVALOVAL 0x00000020U /*!< A-peripheral session valid override value */
+#define USB_OTG_GOTGCTL_BVALOEN 0x00000040U /*!< B-peripheral session valid override enable */
+#define USB_OTG_GOTGCTL_BVALOVAL 0x00000080U /*!< B-peripheral session valid override value */
+#define USB_OTG_GOTGCTL_HNGSCS 0x00000100U /*!< Host set HNP enable */
+#define USB_OTG_GOTGCTL_HNPRQ 0x00000200U /*!< HNP request */
+#define USB_OTG_GOTGCTL_HSHNPEN 0x00000400U /*!< Host set HNP enable */
+#define USB_OTG_GOTGCTL_DHNPEN 0x00000800U /*!< Device HNP enabled */
+#define USB_OTG_GOTGCTL_EHEN 0x00001000U /*!< Embedded host enable */
+#define USB_OTG_GOTGCTL_CIDSTS 0x00010000U /*!< Connector ID status */
+#define USB_OTG_GOTGCTL_DBCT 0x00020000U /*!< Long/short debounce time */
+#define USB_OTG_GOTGCTL_ASVLD 0x00040000U /*!< A-session valid */
+#define USB_OTG_GOTGCTL_BSESVLD 0x00080000U /*!< B-session valid */
+#define USB_OTG_GOTGCTL_OTGVER 0x00100000U /*!< OTG version */
+
+/******************** Bit definition forUSB_OTG_HCFG register ********************/
+
+#define USB_OTG_HCFG_FSLSPCS 0x00000003U /*!< FS/LS PHY clock select */
+#define USB_OTG_HCFG_FSLSPCS_0 0x00000001U /*!<Bit 0 */
+#define USB_OTG_HCFG_FSLSPCS_1 0x00000002U /*!<Bit 1 */
+#define USB_OTG_HCFG_FSLSS 0x00000004U /*!< FS- and LS-only support */
+
+/******************** Bit definition forUSB_OTG_DCFG register ********************/
+
+#define USB_OTG_DCFG_DSPD 0x00000003U /*!< Device speed */
+#define USB_OTG_DCFG_DSPD_0 0x00000001U /*!<Bit 0 */
+#define USB_OTG_DCFG_DSPD_1 0x00000002U /*!<Bit 1 */
+#define USB_OTG_DCFG_NZLSOHSK 0x00000004U /*!< Nonzero-length status OUT handshake */
+
+#define USB_OTG_DCFG_DAD 0x000007F0U /*!< Device address */
+#define USB_OTG_DCFG_DAD_0 0x00000010U /*!<Bit 0 */
+#define USB_OTG_DCFG_DAD_1 0x00000020U /*!<Bit 1 */
+#define USB_OTG_DCFG_DAD_2 0x00000040U /*!<Bit 2 */
+#define USB_OTG_DCFG_DAD_3 0x00000080U /*!<Bit 3 */
+#define USB_OTG_DCFG_DAD_4 0x00000100U /*!<Bit 4 */
+#define USB_OTG_DCFG_DAD_5 0x00000200U /*!<Bit 5 */
+#define USB_OTG_DCFG_DAD_6 0x00000400U /*!<Bit 6 */
+
+#define USB_OTG_DCFG_PFIVL 0x00001800U /*!< Periodic (micro)frame interval */
+#define USB_OTG_DCFG_PFIVL_0 0x00000800U /*!<Bit 0 */
+#define USB_OTG_DCFG_PFIVL_1 0x00001000U /*!<Bit 1 */
+
+#define USB_OTG_DCFG_PERSCHIVL 0x03000000U /*!< Periodic scheduling interval */
+#define USB_OTG_DCFG_PERSCHIVL_0 0x01000000U /*!<Bit 0 */
+#define USB_OTG_DCFG_PERSCHIVL_1 0x02000000U /*!<Bit 1 */
+
+/******************** Bit definition forUSB_OTG_PCGCR register ********************/
+#define USB_OTG_PCGCR_STPPCLK 0x00000001U /*!< Stop PHY clock */
+#define USB_OTG_PCGCR_GATEHCLK 0x00000002U /*!< Gate HCLK */
+#define USB_OTG_PCGCR_PHYSUSP 0x00000010U /*!< PHY suspended */
+
+/******************** Bit definition forUSB_OTG_GOTGINT register ********************/
+#define USB_OTG_GOTGINT_SEDET 0x00000004U /*!< Session end detected */
+#define USB_OTG_GOTGINT_SRSSCHG 0x00000100U /*!< Session request success status change */
+#define USB_OTG_GOTGINT_HNSSCHG 0x00000200U /*!< Host negotiation success status change */
+#define USB_OTG_GOTGINT_HNGDET 0x00020000U /*!< Host negotiation detected */
+#define USB_OTG_GOTGINT_ADTOCHG 0x00040000U /*!< A-device timeout change */
+#define USB_OTG_GOTGINT_DBCDNE 0x00080000U /*!< Debounce done */
+#define USB_OTG_GOTGINT_IDCHNG 0x00100000U /*!< Change in ID pin input value */
+
+/******************** Bit definition forUSB_OTG_DCTL register ********************/
+#define USB_OTG_DCTL_RWUSIG 0x00000001U /*!< Remote wakeup signaling */
+#define USB_OTG_DCTL_SDIS 0x00000002U /*!< Soft disconnect */
+#define USB_OTG_DCTL_GINSTS 0x00000004U /*!< Global IN NAK status */
+#define USB_OTG_DCTL_GONSTS 0x00000008U /*!< Global OUT NAK status */
+
+#define USB_OTG_DCTL_TCTL 0x00000070U /*!< Test control */
+#define USB_OTG_DCTL_TCTL_0 0x00000010U /*!<Bit 0 */
+#define USB_OTG_DCTL_TCTL_1 0x00000020U /*!<Bit 1 */
+#define USB_OTG_DCTL_TCTL_2 0x00000040U /*!<Bit 2 */
+#define USB_OTG_DCTL_SGINAK 0x00000080U /*!< Set global IN NAK */
+#define USB_OTG_DCTL_CGINAK 0x00000100U /*!< Clear global IN NAK */
+#define USB_OTG_DCTL_SGONAK 0x00000200U /*!< Set global OUT NAK */
+#define USB_OTG_DCTL_CGONAK 0x00000400U /*!< Clear global OUT NAK */
+#define USB_OTG_DCTL_POPRGDNE 0x00000800U /*!< Power-on programming done */
+
+/******************** Bit definition forUSB_OTG_HFIR register ********************/
+#define USB_OTG_HFIR_FRIVL 0x0000FFFFU /*!< Frame interval */
+
+/******************** Bit definition forUSB_OTG_HFNUM register ********************/
+#define USB_OTG_HFNUM_FRNUM 0x0000FFFFU /*!< Frame number */
+#define USB_OTG_HFNUM_FTREM 0xFFFF0000U /*!< Frame time remaining */
+
+/******************** Bit definition forUSB_OTG_DSTS register ********************/
+#define USB_OTG_DSTS_SUSPSTS 0x00000001U /*!< Suspend status */
+
+#define USB_OTG_DSTS_ENUMSPD 0x00000006U /*!< Enumerated speed */
+#define USB_OTG_DSTS_ENUMSPD_0 0x00000002U /*!<Bit 0 */
+#define USB_OTG_DSTS_ENUMSPD_1 0x00000004U /*!<Bit 1 */
+#define USB_OTG_DSTS_EERR 0x00000008U /*!< Erratic error */
+#define USB_OTG_DSTS_FNSOF 0x003FFF00U /*!< Frame number of the received SOF */
+
+/******************** Bit definition forUSB_OTG_GAHBCFG register ********************/
+#define USB_OTG_GAHBCFG_GINT 0x00000001U /*!< Global interrupt mask */
+#define USB_OTG_GAHBCFG_HBSTLEN 0x0000001EU /*!< Burst length/type */
+#define USB_OTG_GAHBCFG_HBSTLEN_0 0x00000002U /*!<Bit 0 */
+#define USB_OTG_GAHBCFG_HBSTLEN_1 0x00000004U /*!<Bit 1 */
+#define USB_OTG_GAHBCFG_HBSTLEN_2 0x00000008U /*!<Bit 2 */
+#define USB_OTG_GAHBCFG_HBSTLEN_3 0x00000010U /*!<Bit 3 */
+#define USB_OTG_GAHBCFG_DMAEN 0x00000020U /*!< DMA enable */
+#define USB_OTG_GAHBCFG_TXFELVL 0x00000080U /*!< TxFIFO empty level */
+#define USB_OTG_GAHBCFG_PTXFELVL 0x00000100U /*!< Periodic TxFIFO empty level */
+
+/******************** Bit definition forUSB_OTG_GUSBCFG register ********************/
+
+#define USB_OTG_GUSBCFG_TOCAL 0x00000007U /*!< FS timeout calibration */
+#define USB_OTG_GUSBCFG_TOCAL_0 0x00000001U /*!<Bit 0 */
+#define USB_OTG_GUSBCFG_TOCAL_1 0x00000002U /*!<Bit 1 */
+#define USB_OTG_GUSBCFG_TOCAL_2 0x00000004U /*!<Bit 2 */
+#define USB_OTG_GUSBCFG_PHYSEL 0x00000040U /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */
+#define USB_OTG_GUSBCFG_SRPCAP 0x00000100U /*!< SRP-capable */
+#define USB_OTG_GUSBCFG_HNPCAP 0x00000200U /*!< HNP-capable */
+#define USB_OTG_GUSBCFG_TRDT 0x00003C00U /*!< USB turnaround time */
+#define USB_OTG_GUSBCFG_TRDT_0 0x00000400U /*!<Bit 0 */
+#define USB_OTG_GUSBCFG_TRDT_1 0x00000800U /*!<Bit 1 */
+#define USB_OTG_GUSBCFG_TRDT_2 0x00001000U /*!<Bit 2 */
+#define USB_OTG_GUSBCFG_TRDT_3 0x00002000U /*!<Bit 3 */
+#define USB_OTG_GUSBCFG_PHYLPCS 0x00008000U /*!< PHY Low-power clock select */
+#define USB_OTG_GUSBCFG_ULPIFSLS 0x00020000U /*!< ULPI FS/LS select */
+#define USB_OTG_GUSBCFG_ULPIAR 0x00040000U /*!< ULPI Auto-resume */
+#define USB_OTG_GUSBCFG_ULPICSM 0x00080000U /*!< ULPI Clock SuspendM */
+#define USB_OTG_GUSBCFG_ULPIEVBUSD 0x00100000U /*!< ULPI External VBUS Drive */
+#define USB_OTG_GUSBCFG_ULPIEVBUSI 0x00200000U /*!< ULPI external VBUS indicator */
+#define USB_OTG_GUSBCFG_TSDPS 0x00400000U /*!< TermSel DLine pulsing selection */
+#define USB_OTG_GUSBCFG_PCCI 0x00800000U /*!< Indicator complement */
+#define USB_OTG_GUSBCFG_PTCI 0x01000000U /*!< Indicator pass through */
+#define USB_OTG_GUSBCFG_ULPIIPD 0x02000000U /*!< ULPI interface protect disable */
+#define USB_OTG_GUSBCFG_FHMOD 0x20000000U /*!< Forced host mode */
+#define USB_OTG_GUSBCFG_FDMOD 0x40000000U /*!< Forced peripheral mode */
+#define USB_OTG_GUSBCFG_CTXPKT 0x80000000U /*!< Corrupt Tx packet */
+
+/******************** Bit definition forUSB_OTG_GRSTCTL register ********************/
+#define USB_OTG_GRSTCTL_CSRST 0x00000001U /*!< Core soft reset */
+#define USB_OTG_GRSTCTL_HSRST 0x00000002U /*!< HCLK soft reset */
+#define USB_OTG_GRSTCTL_FCRST 0x00000004U /*!< Host frame counter reset */
+#define USB_OTG_GRSTCTL_RXFFLSH 0x00000010U /*!< RxFIFO flush */
+#define USB_OTG_GRSTCTL_TXFFLSH 0x00000020U /*!< TxFIFO flush */
+#define USB_OTG_GRSTCTL_TXFNUM 0x000007C0U /*!< TxFIFO number */
+#define USB_OTG_GRSTCTL_TXFNUM_0 0x00000040U /*!<Bit 0 */
+#define USB_OTG_GRSTCTL_TXFNUM_1 0x00000080U /*!<Bit 1 */
+#define USB_OTG_GRSTCTL_TXFNUM_2 0x00000100U /*!<Bit 2 */
+#define USB_OTG_GRSTCTL_TXFNUM_3 0x00000200U /*!<Bit 3 */
+#define USB_OTG_GRSTCTL_TXFNUM_4 0x00000400U /*!<Bit 4 */
+#define USB_OTG_GRSTCTL_DMAREQ 0x40000000U /*!< DMA request signal */
+#define USB_OTG_GRSTCTL_AHBIDL 0x80000000U /*!< AHB master idle */
+
+/******************** Bit definition forUSB_OTG_DIEPMSK register ********************/
+#define USB_OTG_DIEPMSK_XFRCM 0x00000001U /*!< Transfer completed interrupt mask */
+#define USB_OTG_DIEPMSK_EPDM 0x00000002U /*!< Endpoint disabled interrupt mask */
+#define USB_OTG_DIEPMSK_TOM 0x00000008U /*!< Timeout condition mask (nonisochronous endpoints) */
+#define USB_OTG_DIEPMSK_ITTXFEMSK 0x00000010U /*!< IN token received when TxFIFO empty mask */
+#define USB_OTG_DIEPMSK_INEPNMM 0x00000020U /*!< IN token received with EP mismatch mask */
+#define USB_OTG_DIEPMSK_INEPNEM 0x00000040U /*!< IN endpoint NAK effective mask */
+#define USB_OTG_DIEPMSK_TXFURM 0x00000100U /*!< FIFO underrun mask */
+#define USB_OTG_DIEPMSK_BIM 0x00000200U /*!< BNA interrupt mask */
+
+/******************** Bit definition forUSB_OTG_HPTXSTS register ********************/
+#define USB_OTG_HPTXSTS_PTXFSAVL 0x0000FFFFU /*!< Periodic transmit data FIFO space available */
+#define USB_OTG_HPTXSTS_PTXQSAV 0x00FF0000U /*!< Periodic transmit request queue space available */
+#define USB_OTG_HPTXSTS_PTXQSAV_0 0x00010000U /*!<Bit 0 */
+#define USB_OTG_HPTXSTS_PTXQSAV_1 0x00020000U /*!<Bit 1 */
+#define USB_OTG_HPTXSTS_PTXQSAV_2 0x00040000U /*!<Bit 2 */
+#define USB_OTG_HPTXSTS_PTXQSAV_3 0x00080000U /*!<Bit 3 */
+#define USB_OTG_HPTXSTS_PTXQSAV_4 0x00100000U /*!<Bit 4 */
+#define USB_OTG_HPTXSTS_PTXQSAV_5 0x00200000U /*!<Bit 5 */
+#define USB_OTG_HPTXSTS_PTXQSAV_6 0x00400000U /*!<Bit 6 */
+#define USB_OTG_HPTXSTS_PTXQSAV_7 0x00800000U /*!<Bit 7 */
+
+#define USB_OTG_HPTXSTS_PTXQTOP 0xFF000000U /*!< Top of the periodic transmit request queue */
+#define USB_OTG_HPTXSTS_PTXQTOP_0 0x01000000U /*!<Bit 0 */
+#define USB_OTG_HPTXSTS_PTXQTOP_1 0x02000000U /*!<Bit 1 */
+#define USB_OTG_HPTXSTS_PTXQTOP_2 0x04000000U /*!<Bit 2 */
+#define USB_OTG_HPTXSTS_PTXQTOP_3 0x08000000U /*!<Bit 3 */
+#define USB_OTG_HPTXSTS_PTXQTOP_4 0x10000000U /*!<Bit 4 */
+#define USB_OTG_HPTXSTS_PTXQTOP_5 0x20000000U /*!<Bit 5 */
+#define USB_OTG_HPTXSTS_PTXQTOP_6 0x40000000U /*!<Bit 6 */
+#define USB_OTG_HPTXSTS_PTXQTOP_7 0x80000000U /*!<Bit 7 */
+
+/******************** Bit definition forUSB_OTG_HAINT register ********************/
+#define USB_OTG_HAINT_HAINT 0x0000FFFFU /*!< Channel interrupts */
+
+/******************** Bit definition forUSB_OTG_DOEPMSK register ********************/
+#define USB_OTG_DOEPMSK_XFRCM 0x00000001U /*!< Transfer completed interrupt mask */
+#define USB_OTG_DOEPMSK_EPDM 0x00000002U /*!< Endpoint disabled interrupt mask */
+#define USB_OTG_DOEPMSK_STUPM 0x00000008U /*!< SETUP phase done mask */
+#define USB_OTG_DOEPMSK_OTEPDM 0x00000010U /*!< OUT token received when endpoint disabled mask */
+#define USB_OTG_DOEPMSK_OTEPSPRM 0x00000020U /*!< Status Phase Received mask */
+#define USB_OTG_DOEPMSK_B2BSTUP 0x00000040U /*!< Back-to-back SETUP packets received mask */
+#define USB_OTG_DOEPMSK_OPEM 0x00000100U /*!< OUT packet error mask */
+#define USB_OTG_DOEPMSK_BOIM 0x00000200U /*!< BNA interrupt mask */
+
+/******************** Bit definition forUSB_OTG_GINTSTS register ********************/
+#define USB_OTG_GINTSTS_CMOD 0x00000001U /*!< Current mode of operation */
+#define USB_OTG_GINTSTS_MMIS 0x00000002U /*!< Mode mismatch interrupt */
+#define USB_OTG_GINTSTS_OTGINT 0x00000004U /*!< OTG interrupt */
+#define USB_OTG_GINTSTS_SOF 0x00000008U /*!< Start of frame */
+#define USB_OTG_GINTSTS_RXFLVL 0x00000010U /*!< RxFIFO nonempty */
+#define USB_OTG_GINTSTS_NPTXFE 0x00000020U /*!< Nonperiodic TxFIFO empty */
+#define USB_OTG_GINTSTS_GINAKEFF 0x00000040U /*!< Global IN nonperiodic NAK effective */
+#define USB_OTG_GINTSTS_BOUTNAKEFF 0x00000080U /*!< Global OUT NAK effective */
+#define USB_OTG_GINTSTS_ESUSP 0x00000400U /*!< Early suspend */
+#define USB_OTG_GINTSTS_USBSUSP 0x00000800U /*!< USB suspend */
+#define USB_OTG_GINTSTS_USBRST 0x00001000U /*!< USB reset */
+#define USB_OTG_GINTSTS_ENUMDNE 0x00002000U /*!< Enumeration done */
+#define USB_OTG_GINTSTS_ISOODRP 0x00004000U /*!< Isochronous OUT packet dropped interrupt */
+#define USB_OTG_GINTSTS_EOPF 0x00008000U /*!< End of periodic frame interrupt */
+#define USB_OTG_GINTSTS_IEPINT 0x00040000U /*!< IN endpoint interrupt */
+#define USB_OTG_GINTSTS_OEPINT 0x00080000U /*!< OUT endpoint interrupt */
+#define USB_OTG_GINTSTS_IISOIXFR 0x00100000U /*!< Incomplete isochronous IN transfer */
+#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT 0x00200000U /*!< Incomplete periodic transfer */
+#define USB_OTG_GINTSTS_DATAFSUSP 0x00400000U /*!< Data fetch suspended */
+#define USB_OTG_GINTSTS_RSTDET 0x00800000U /*!< Reset detected interrupt */
+#define USB_OTG_GINTSTS_HPRTINT 0x01000000U /*!< Host port interrupt */
+#define USB_OTG_GINTSTS_HCINT 0x02000000U /*!< Host channels interrupt */
+#define USB_OTG_GINTSTS_PTXFE 0x04000000U /*!< Periodic TxFIFO empty */
+#define USB_OTG_GINTSTS_LPMINT 0x08000000U /*!< LPM interrupt */
+#define USB_OTG_GINTSTS_CIDSCHG 0x10000000U /*!< Connector ID status change */
+#define USB_OTG_GINTSTS_DISCINT 0x20000000U /*!< Disconnect detected interrupt */
+#define USB_OTG_GINTSTS_SRQINT 0x40000000U /*!< Session request/new session detected interrupt */
+#define USB_OTG_GINTSTS_WKUINT 0x80000000U /*!< Resume/remote wakeup detected interrupt */
+
+/******************** Bit definition forUSB_OTG_GINTMSK register ********************/
+#define USB_OTG_GINTMSK_MMISM 0x00000002U /*!< Mode mismatch interrupt mask */
+#define USB_OTG_GINTMSK_OTGINT 0x00000004U /*!< OTG interrupt mask */
+#define USB_OTG_GINTMSK_SOFM 0x00000008U /*!< Start of frame mask */
+#define USB_OTG_GINTMSK_RXFLVLM 0x00000010U /*!< Receive FIFO nonempty mask */
+#define USB_OTG_GINTMSK_NPTXFEM 0x00000020U /*!< Nonperiodic TxFIFO empty mask */
+#define USB_OTG_GINTMSK_GINAKEFFM 0x00000040U /*!< Global nonperiodic IN NAK effective mask */
+#define USB_OTG_GINTMSK_GONAKEFFM 0x00000080U /*!< Global OUT NAK effective mask */
+#define USB_OTG_GINTMSK_ESUSPM 0x00000400U /*!< Early suspend mask */
+#define USB_OTG_GINTMSK_USBSUSPM 0x00000800U /*!< USB suspend mask */
+#define USB_OTG_GINTMSK_USBRST 0x00001000U /*!< USB reset mask */
+#define USB_OTG_GINTMSK_ENUMDNEM 0x00002000U /*!< Enumeration done mask */
+#define USB_OTG_GINTMSK_ISOODRPM 0x00004000U /*!< Isochronous OUT packet dropped interrupt mask */
+#define USB_OTG_GINTMSK_EOPFM 0x00008000U /*!< End of periodic frame interrupt mask */
+#define USB_OTG_GINTMSK_EPMISM 0x00020000U /*!< Endpoint mismatch interrupt mask */
+#define USB_OTG_GINTMSK_IEPINT 0x00040000U /*!< IN endpoints interrupt mask */
+#define USB_OTG_GINTMSK_OEPINT 0x00080000U /*!< OUT endpoints interrupt mask */
+#define USB_OTG_GINTMSK_IISOIXFRM 0x00100000U /*!< Incomplete isochronous IN transfer mask */
+#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM 0x00200000U /*!< Incomplete periodic transfer mask */
+#define USB_OTG_GINTMSK_FSUSPM 0x00400000U /*!< Data fetch suspended mask */
+#define USB_OTG_GINTMSK_RSTDEM 0x00800000U /*!< Reset detected interrupt mask */
+#define USB_OTG_GINTMSK_PRTIM 0x01000000U /*!< Host port interrupt mask */
+#define USB_OTG_GINTMSK_HCIM 0x02000000U /*!< Host channels interrupt mask */
+#define USB_OTG_GINTMSK_PTXFEM 0x04000000U /*!< Periodic TxFIFO empty mask */
+#define USB_OTG_GINTMSK_LPMINTM 0x08000000U /*!< LPM interrupt Mask */
+#define USB_OTG_GINTMSK_CIDSCHGM 0x10000000U /*!< Connector ID status change mask */
+#define USB_OTG_GINTMSK_DISCINT 0x20000000U /*!< Disconnect detected interrupt mask */
+#define USB_OTG_GINTMSK_SRQIM 0x40000000U /*!< Session request/new session detected interrupt mask */
+#define USB_OTG_GINTMSK_WUIM 0x80000000U /*!< Resume/remote wakeup detected interrupt mask */
+
+/******************** Bit definition forUSB_OTG_DAINT register ********************/
+#define USB_OTG_DAINT_IEPINT 0x0000FFFFU /*!< IN endpoint interrupt bits */
+#define USB_OTG_DAINT_OEPINT 0xFFFF0000U /*!< OUT endpoint interrupt bits */
+
+/******************** Bit definition forUSB_OTG_HAINTMSK register ********************/
+#define USB_OTG_HAINTMSK_HAINTM 0x0000FFFFU /*!< Channel interrupt mask */
+
+/******************** Bit definition for USB_OTG_GRXSTSP register ********************/
+#define USB_OTG_GRXSTSP_EPNUM 0x0000000FU /*!< IN EP interrupt mask bits */
+#define USB_OTG_GRXSTSP_BCNT 0x00007FF0U /*!< OUT EP interrupt mask bits */
+#define USB_OTG_GRXSTSP_DPID 0x00018000U /*!< OUT EP interrupt mask bits */
+#define USB_OTG_GRXSTSP_PKTSTS 0x001E0000U /*!< OUT EP interrupt mask bits */
+
+/******************** Bit definition forUSB_OTG_DAINTMSK register ********************/
+#define USB_OTG_DAINTMSK_IEPM 0x0000FFFFU /*!< IN EP interrupt mask bits */
+#define USB_OTG_DAINTMSK_OEPM 0xFFFF0000U /*!< OUT EP interrupt mask bits */
+
+/******************** Bit definition for OTG register ********************/
+
+#define USB_OTG_CHNUM 0x0000000FU /*!< Channel number */
+#define USB_OTG_CHNUM_0 0x00000001U /*!<Bit 0 */
+#define USB_OTG_CHNUM_1 0x00000002U /*!<Bit 1 */
+#define USB_OTG_CHNUM_2 0x00000004U /*!<Bit 2 */
+#define USB_OTG_CHNUM_3 0x00000008U /*!<Bit 3 */
+#define USB_OTG_BCNT 0x00007FF0U /*!< Byte count */
+
+#define USB_OTG_DPID 0x00018000U /*!< Data PID */
+#define USB_OTG_DPID_0 0x00008000U /*!<Bit 0 */
+#define USB_OTG_DPID_1 0x00010000U /*!<Bit 1 */
+
+#define USB_OTG_PKTSTS 0x001E0000U /*!< Packet status */
+#define USB_OTG_PKTSTS_0 0x00020000U /*!<Bit 0 */
+#define USB_OTG_PKTSTS_1 0x00040000U /*!<Bit 1 */
+#define USB_OTG_PKTSTS_2 0x00080000U /*!<Bit 2 */
+#define USB_OTG_PKTSTS_3 0x00100000U /*!<Bit 3 */
+
+#define USB_OTG_EPNUM 0x0000000FU /*!< Endpoint number */
+#define USB_OTG_EPNUM_0 0x00000001U /*!<Bit 0 */
+#define USB_OTG_EPNUM_1 0x00000002U /*!<Bit 1 */
+#define USB_OTG_EPNUM_2 0x00000004U /*!<Bit 2 */
+#define USB_OTG_EPNUM_3 0x00000008U /*!<Bit 3 */
+
+#define USB_OTG_FRMNUM 0x01E00000U /*!< Frame number */
+#define USB_OTG_FRMNUM_0 0x00200000U /*!<Bit 0 */
+#define USB_OTG_FRMNUM_1 0x00400000U /*!<Bit 1 */
+#define USB_OTG_FRMNUM_2 0x00800000U /*!<Bit 2 */
+#define USB_OTG_FRMNUM_3 0x01000000U /*!<Bit 3 */
+
+/******************** Bit definition for OTG register ********************/
+
+#define USB_OTG_CHNUM 0x0000000FU /*!< Channel number */
+#define USB_OTG_CHNUM_0 0x00000001U /*!<Bit 0 */
+#define USB_OTG_CHNUM_1 0x00000002U /*!<Bit 1 */
+#define USB_OTG_CHNUM_2 0x00000004U /*!<Bit 2 */
+#define USB_OTG_CHNUM_3 0x00000008U /*!<Bit 3 */
+#define USB_OTG_BCNT 0x00007FF0U /*!< Byte count */
+
+#define USB_OTG_DPID 0x00018000U /*!< Data PID */
+#define USB_OTG_DPID_0 0x00008000U /*!<Bit 0 */
+#define USB_OTG_DPID_1 0x00010000U /*!<Bit 1 */
+
+#define USB_OTG_PKTSTS 0x001E0000U /*!< Packet status */
+#define USB_OTG_PKTSTS_0 0x00020000U /*!<Bit 0 */
+#define USB_OTG_PKTSTS_1 0x00040000U /*!<Bit 1 */
+#define USB_OTG_PKTSTS_2 0x00080000U /*!<Bit 2 */
+#define USB_OTG_PKTSTS_3 0x00100000U /*!<Bit 3 */
+
+#define USB_OTG_EPNUM 0x0000000FU /*!< Endpoint number */
+#define USB_OTG_EPNUM_0 0x00000001U /*!<Bit 0 */
+#define USB_OTG_EPNUM_1 0x00000002U /*!<Bit 1 */
+#define USB_OTG_EPNUM_2 0x00000004U /*!<Bit 2 */
+#define USB_OTG_EPNUM_3 0x00000008U /*!<Bit 3 */
+
+#define USB_OTG_FRMNUM 0x01E00000U /*!< Frame number */
+#define USB_OTG_FRMNUM_0 0x00200000U /*!<Bit 0 */
+#define USB_OTG_FRMNUM_1 0x00400000U /*!<Bit 1 */
+#define USB_OTG_FRMNUM_2 0x00800000U /*!<Bit 2 */
+#define USB_OTG_FRMNUM_3 0x01000000U /*!<Bit 3 */
+
+/******************** Bit definition forUSB_OTG_GRXFSIZ register ********************/
+#define USB_OTG_GRXFSIZ_RXFD 0x0000FFFFU /*!< RxFIFO depth */
+
+/******************** Bit definition forUSB_OTG_DVBUSDIS register ********************/
+#define USB_OTG_DVBUSDIS_VBUSDT 0x0000FFFFU /*!< Device VBUS discharge time */
+
+/******************** Bit definition for OTG register ********************/
+#define USB_OTG_NPTXFSA 0x0000FFFFU /*!< Nonperiodic transmit RAM start address */
+#define USB_OTG_NPTXFD 0xFFFF0000U /*!< Nonperiodic TxFIFO depth */
+#define USB_OTG_TX0FSA 0x0000FFFFU /*!< Endpoint 0 transmit RAM start address */
+#define USB_OTG_TX0FD 0xFFFF0000U /*!< Endpoint 0 TxFIFO depth */
+
+/******************** Bit definition forUSB_OTG_DVBUSPULSE register ********************/
+#define USB_OTG_DVBUSPULSE_DVBUSP 0x00000FFFU /*!< Device VBUS pulsing time */
+
+/******************** Bit definition forUSB_OTG_GNPTXSTS register ********************/
+#define USB_OTG_GNPTXSTS_NPTXFSAV 0x0000FFFFU /*!< Nonperiodic TxFIFO space available */
+
+#define USB_OTG_GNPTXSTS_NPTQXSAV 0x00FF0000U /*!< Nonperiodic transmit request queue space available */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_0 0x00010000U /*!<Bit 0 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_1 0x00020000U /*!<Bit 1 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_2 0x00040000U /*!<Bit 2 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_3 0x00080000U /*!<Bit 3 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_4 0x00100000U /*!<Bit 4 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_5 0x00200000U /*!<Bit 5 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_6 0x00400000U /*!<Bit 6 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_7 0x00800000U /*!<Bit 7 */
+
+#define USB_OTG_GNPTXSTS_NPTXQTOP 0x7F000000U /*!< Top of the nonperiodic transmit request queue */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_0 0x01000000U /*!<Bit 0 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_1 0x02000000U /*!<Bit 1 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_2 0x04000000U /*!<Bit 2 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_3 0x08000000U /*!<Bit 3 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_4 0x10000000U /*!<Bit 4 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_5 0x20000000U /*!<Bit 5 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_6 0x40000000U /*!<Bit 6 */
+
+/******************** Bit definition forUSB_OTG_DTHRCTL register ********************/
+#define USB_OTG_DTHRCTL_NONISOTHREN 0x00000001U /*!< Nonisochronous IN endpoints threshold enable */
+#define USB_OTG_DTHRCTL_ISOTHREN 0x00000002U /*!< ISO IN endpoint threshold enable */
+
+#define USB_OTG_DTHRCTL_TXTHRLEN 0x000007FCU /*!< Transmit threshold length */
+#define USB_OTG_DTHRCTL_TXTHRLEN_0 0x00000004U /*!<Bit 0 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_1 0x00000008U /*!<Bit 1 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_2 0x00000010U /*!<Bit 2 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_3 0x00000020U /*!<Bit 3 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_4 0x00000040U /*!<Bit 4 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_5 0x00000080U /*!<Bit 5 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_6 0x00000100U /*!<Bit 6 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_7 0x00000200U /*!<Bit 7 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_8 0x00000400U /*!<Bit 8 */
+#define USB_OTG_DTHRCTL_RXTHREN 0x00010000U /*!< Receive threshold enable */
+
+#define USB_OTG_DTHRCTL_RXTHRLEN 0x03FE0000U /*!< Receive threshold length */
+#define USB_OTG_DTHRCTL_RXTHRLEN_0 0x00020000U /*!<Bit 0 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_1 0x00040000U /*!<Bit 1 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_2 0x00080000U /*!<Bit 2 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_3 0x00100000U /*!<Bit 3 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_4 0x00200000U /*!<Bit 4 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_5 0x00400000U /*!<Bit 5 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_6 0x00800000U /*!<Bit 6 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_7 0x01000000U /*!<Bit 7 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_8 0x02000000U /*!<Bit 8 */
+#define USB_OTG_DTHRCTL_ARPEN 0x08000000U /*!< Arbiter parking enable */
+
+/******************** Bit definition forUSB_OTG_DIEPEMPMSK register ********************/
+#define USB_OTG_DIEPEMPMSK_INEPTXFEM 0x0000FFFFU /*!< IN EP Tx FIFO empty interrupt mask bits */
+
+/******************** Bit definition forUSB_OTG_DEACHINT register ********************/
+#define USB_OTG_DEACHINT_IEP1INT 0x00000002U /*!< IN endpoint 1interrupt bit */
+#define USB_OTG_DEACHINT_OEP1INT 0x00020000U /*!< OUT endpoint 1 interrupt bit */
+
+/******************** Bit definition forUSB_OTG_GCCFG register ********************/
+#define USB_OTG_GCCFG_PWRDWN 0x00010000U /*!< Power down */
+#define USB_OTG_GCCFG_VBDEN 0x00200000U /*!< USB VBUS Detection Enable */
+
+/******************** Bit definition forUSB_OTG_DEACHINTMSK register ********************/
+#define USB_OTG_DEACHINTMSK_IEP1INTM 0x00000002U /*!< IN Endpoint 1 interrupt mask bit */
+#define USB_OTG_DEACHINTMSK_OEP1INTM 0x00020000U /*!< OUT Endpoint 1 interrupt mask bit */
+
+/******************** Bit definition forUSB_OTG_CID register ********************/
+#define USB_OTG_CID_PRODUCT_ID 0xFFFFFFFFU /*!< Product ID field */
+
+/******************** Bit definition for USB_OTG_GLPMCFG register ********************/
+#define USB_OTG_GLPMCFG_LPMEN 0x00000001U /*!< LPM support enable */
+#define USB_OTG_GLPMCFG_LPMACK 0x00000002U /*!< LPM Token acknowledge enable */
+#define USB_OTG_GLPMCFG_BESL 0x0000003CU /*!< BESL value received with last ACKed LPM Token */
+#define USB_OTG_GLPMCFG_REMWAKE 0x00000040U /*!< bRemoteWake value received with last ACKed LPM Token */
+#define USB_OTG_GLPMCFG_L1SSEN 0x00000080U /*!< L1 shallow sleep enable */
+#define USB_OTG_GLPMCFG_BESLTHRS 0x00000F00U /*!< BESL threshold */
+#define USB_OTG_GLPMCFG_L1DSEN 0x00001000U /*!< L1 deep sleep enable */
+#define USB_OTG_GLPMCFG_LPMRSP 0x00006000U /*!< LPM response */
+#define USB_OTG_GLPMCFG_SLPSTS 0x00008000U /*!< Port sleep status */
+#define USB_OTG_GLPMCFG_L1RSMOK 0x00010000U /*!< Sleep State Resume OK */
+#define USB_OTG_GLPMCFG_LPMCHIDX 0x001E0000U /*!< LPM Channel Index */
+#define USB_OTG_GLPMCFG_LPMRCNT 0x00E00000U /*!< LPM retry count */
+#define USB_OTG_GLPMCFG_SNDLPM 0x01000000U /*!< Send LPM transaction */
+#define USB_OTG_GLPMCFG_LPMRCNTSTS 0x0E000000U /*!< LPM retry count status */
+#define USB_OTG_GLPMCFG_ENBESL 0x10000000U /*!< Enable best effort service latency */
+
+/******************** Bit definition forUSB_OTG_DIEPEACHMSK1 register ********************/
+#define USB_OTG_DIEPEACHMSK1_XFRCM 0x00000001U /*!< Transfer completed interrupt mask */
+#define USB_OTG_DIEPEACHMSK1_EPDM 0x00000002U /*!< Endpoint disabled interrupt mask */
+#define USB_OTG_DIEPEACHMSK1_TOM 0x00000008U /*!< Timeout condition mask (nonisochronous endpoints) */
+#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK 0x00000010U /*!< IN token received when TxFIFO empty mask */
+#define USB_OTG_DIEPEACHMSK1_INEPNMM 0x00000020U /*!< IN token received with EP mismatch mask */
+#define USB_OTG_DIEPEACHMSK1_INEPNEM 0x00000040U /*!< IN endpoint NAK effective mask */
+#define USB_OTG_DIEPEACHMSK1_TXFURM 0x00000100U /*!< FIFO underrun mask */
+#define USB_OTG_DIEPEACHMSK1_BIM 0x00000200U /*!< BNA interrupt mask */
+#define USB_OTG_DIEPEACHMSK1_NAKM 0x00002000U /*!< NAK interrupt mask */
+
+/******************** Bit definition forUSB_OTG_HPRT register ********************/
+#define USB_OTG_HPRT_PCSTS 0x00000001U /*!< Port connect status */
+#define USB_OTG_HPRT_PCDET 0x00000002U /*!< Port connect detected */
+#define USB_OTG_HPRT_PENA 0x00000004U /*!< Port enable */
+#define USB_OTG_HPRT_PENCHNG 0x00000008U /*!< Port enable/disable change */
+#define USB_OTG_HPRT_POCA 0x00000010U /*!< Port overcurrent active */
+#define USB_OTG_HPRT_POCCHNG 0x00000020U /*!< Port overcurrent change */
+#define USB_OTG_HPRT_PRES 0x00000040U /*!< Port resume */
+#define USB_OTG_HPRT_PSUSP 0x00000080U /*!< Port suspend */
+#define USB_OTG_HPRT_PRST 0x00000100U /*!< Port reset */
+
+#define USB_OTG_HPRT_PLSTS 0x00000C00U /*!< Port line status */
+#define USB_OTG_HPRT_PLSTS_0 0x00000400U /*!<Bit 0 */
+#define USB_OTG_HPRT_PLSTS_1 0x00000800U /*!<Bit 1 */
+#define USB_OTG_HPRT_PPWR 0x00001000U /*!< Port power */
+
+#define USB_OTG_HPRT_PTCTL 0x0001E000U /*!< Port test control */
+#define USB_OTG_HPRT_PTCTL_0 0x00002000U /*!<Bit 0 */
+#define USB_OTG_HPRT_PTCTL_1 0x00004000U /*!<Bit 1 */
+#define USB_OTG_HPRT_PTCTL_2 0x00008000U /*!<Bit 2 */
+#define USB_OTG_HPRT_PTCTL_3 0x00010000U /*!<Bit 3 */
+
+#define USB_OTG_HPRT_PSPD 0x00060000U /*!< Port speed */
+#define USB_OTG_HPRT_PSPD_0 0x00020000U /*!<Bit 0 */
+#define USB_OTG_HPRT_PSPD_1 0x00040000U /*!<Bit 1 */
+
+/******************** Bit definition forUSB_OTG_DOEPEACHMSK1 register ********************/
+#define USB_OTG_DOEPEACHMSK1_XFRCM 0x00000001U /*!< Transfer completed interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_EPDM 0x00000002U /*!< Endpoint disabled interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_TOM 0x00000008U /*!< Timeout condition mask */
+#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK 0x00000010U /*!< IN token received when TxFIFO empty mask */
+#define USB_OTG_DOEPEACHMSK1_INEPNMM 0x00000020U /*!< IN token received with EP mismatch mask */
+#define USB_OTG_DOEPEACHMSK1_INEPNEM 0x00000040U /*!< IN endpoint NAK effective mask */
+#define USB_OTG_DOEPEACHMSK1_TXFURM 0x00000100U /*!< OUT packet error mask */
+#define USB_OTG_DOEPEACHMSK1_BIM 0x00000200U /*!< BNA interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_BERRM 0x00001000U /*!< Bubble error interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_NAKM 0x00002000U /*!< NAK interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_NYETM 0x00004000U /*!< NYET interrupt mask */
+
+/******************** Bit definition forUSB_OTG_HPTXFSIZ register ********************/
+#define USB_OTG_HPTXFSIZ_PTXSA 0x0000FFFFU /*!< Host periodic TxFIFO start address */
+#define USB_OTG_HPTXFSIZ_PTXFD 0xFFFF0000U /*!< Host periodic TxFIFO depth */
+
+/******************** Bit definition forUSB_OTG_DIEPCTL register ********************/
+#define USB_OTG_DIEPCTL_MPSIZ 0x000007FFU /*!< Maximum packet size */
+#define USB_OTG_DIEPCTL_USBAEP 0x00008000U /*!< USB active endpoint */
+#define USB_OTG_DIEPCTL_EONUM_DPID 0x00010000U /*!< Even/odd frame */
+#define USB_OTG_DIEPCTL_NAKSTS 0x00020000U /*!< NAK status */
+
+#define USB_OTG_DIEPCTL_EPTYP 0x000C0000U /*!< Endpoint type */
+#define USB_OTG_DIEPCTL_EPTYP_0 0x00040000U /*!<Bit 0 */
+#define USB_OTG_DIEPCTL_EPTYP_1 0x00080000U /*!<Bit 1 */
+#define USB_OTG_DIEPCTL_STALL 0x00200000U /*!< STALL handshake */
+
+#define USB_OTG_DIEPCTL_TXFNUM 0x03C00000U /*!< TxFIFO number */
+#define USB_OTG_DIEPCTL_TXFNUM_0 0x00400000U /*!<Bit 0 */
+#define USB_OTG_DIEPCTL_TXFNUM_1 0x00800000U /*!<Bit 1 */
+#define USB_OTG_DIEPCTL_TXFNUM_2 0x01000000U /*!<Bit 2 */
+#define USB_OTG_DIEPCTL_TXFNUM_3 0x02000000U /*!<Bit 3 */
+#define USB_OTG_DIEPCTL_CNAK 0x04000000U /*!< Clear NAK */
+#define USB_OTG_DIEPCTL_SNAK 0x08000000U /*!< Set NAK */
+#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM 0x10000000U /*!< Set DATA0 PID */
+#define USB_OTG_DIEPCTL_SODDFRM 0x20000000U /*!< Set odd frame */
+#define USB_OTG_DIEPCTL_EPDIS 0x40000000U /*!< Endpoint disable */
+#define USB_OTG_DIEPCTL_EPENA 0x80000000U /*!< Endpoint enable */
+
+/******************** Bit definition forUSB_OTG_HCCHAR register ********************/
+#define USB_OTG_HCCHAR_MPSIZ 0x000007FFU /*!< Maximum packet size */
+
+#define USB_OTG_HCCHAR_EPNUM 0x00007800U /*!< Endpoint number */
+#define USB_OTG_HCCHAR_EPNUM_0 0x00000800U /*!<Bit 0 */
+#define USB_OTG_HCCHAR_EPNUM_1 0x00001000U /*!<Bit 1 */
+#define USB_OTG_HCCHAR_EPNUM_2 0x00002000U /*!<Bit 2 */
+#define USB_OTG_HCCHAR_EPNUM_3 0x00004000U /*!<Bit 3 */
+#define USB_OTG_HCCHAR_EPDIR 0x00008000U /*!< Endpoint direction */
+#define USB_OTG_HCCHAR_LSDEV 0x00020000U /*!< Low-speed device */
+
+#define USB_OTG_HCCHAR_EPTYP 0x000C0000U /*!< Endpoint type */
+#define USB_OTG_HCCHAR_EPTYP_0 0x00040000U /*!<Bit 0 */
+#define USB_OTG_HCCHAR_EPTYP_1 0x00080000U /*!<Bit 1 */
+
+#define USB_OTG_HCCHAR_MC 0x00300000U /*!< Multi Count (MC) / Error Count (EC) */
+#define USB_OTG_HCCHAR_MC_0 0x00100000U /*!<Bit 0 */
+#define USB_OTG_HCCHAR_MC_1 0x00200000U /*!<Bit 1 */
+
+#define USB_OTG_HCCHAR_DAD 0x1FC00000U /*!< Device address */
+#define USB_OTG_HCCHAR_DAD_0 0x00400000U /*!<Bit 0 */
+#define USB_OTG_HCCHAR_DAD_1 0x00800000U /*!<Bit 1 */
+#define USB_OTG_HCCHAR_DAD_2 0x01000000U /*!<Bit 2 */
+#define USB_OTG_HCCHAR_DAD_3 0x02000000U /*!<Bit 3 */
+#define USB_OTG_HCCHAR_DAD_4 0x04000000U /*!<Bit 4 */
+#define USB_OTG_HCCHAR_DAD_5 0x08000000U /*!<Bit 5 */
+#define USB_OTG_HCCHAR_DAD_6 0x10000000U /*!<Bit 6 */
+#define USB_OTG_HCCHAR_ODDFRM 0x20000000U /*!< Odd frame */
+#define USB_OTG_HCCHAR_CHDIS 0x40000000U /*!< Channel disable */
+#define USB_OTG_HCCHAR_CHENA 0x80000000U /*!< Channel enable */
+
+/******************** Bit definition forUSB_OTG_HCSPLT register ********************/
+
+#define USB_OTG_HCSPLT_PRTADDR 0x0000007FU /*!< Port address */
+#define USB_OTG_HCSPLT_PRTADDR_0 0x00000001U /*!<Bit 0 */
+#define USB_OTG_HCSPLT_PRTADDR_1 0x00000002U /*!<Bit 1 */
+#define USB_OTG_HCSPLT_PRTADDR_2 0x00000004U /*!<Bit 2 */
+#define USB_OTG_HCSPLT_PRTADDR_3 0x00000008U /*!<Bit 3 */
+#define USB_OTG_HCSPLT_PRTADDR_4 0x00000010U /*!<Bit 4 */
+#define USB_OTG_HCSPLT_PRTADDR_5 0x00000020U /*!<Bit 5 */
+#define USB_OTG_HCSPLT_PRTADDR_6 0x00000040U /*!<Bit 6 */
+
+#define USB_OTG_HCSPLT_HUBADDR 0x00003F80U /*!< Hub address */
+#define USB_OTG_HCSPLT_HUBADDR_0 0x00000080U /*!<Bit 0 */
+#define USB_OTG_HCSPLT_HUBADDR_1 0x00000100U /*!<Bit 1 */
+#define USB_OTG_HCSPLT_HUBADDR_2 0x00000200U /*!<Bit 2 */
+#define USB_OTG_HCSPLT_HUBADDR_3 0x00000400U /*!<Bit 3 */
+#define USB_OTG_HCSPLT_HUBADDR_4 0x00000800U /*!<Bit 4 */
+#define USB_OTG_HCSPLT_HUBADDR_5 0x00001000U /*!<Bit 5 */
+#define USB_OTG_HCSPLT_HUBADDR_6 0x00002000U /*!<Bit 6 */
+
+#define USB_OTG_HCSPLT_XACTPOS 0x0000C000U /*!< XACTPOS */
+#define USB_OTG_HCSPLT_XACTPOS_0 0x00004000U /*!<Bit 0 */
+#define USB_OTG_HCSPLT_XACTPOS_1 0x00008000U /*!<Bit 1 */
+#define USB_OTG_HCSPLT_COMPLSPLT 0x00010000U /*!< Do complete split */
+#define USB_OTG_HCSPLT_SPLITEN 0x80000000U /*!< Split enable */
+
+/******************** Bit definition forUSB_OTG_HCINT register ********************/
+#define USB_OTG_HCINT_XFRC 0x00000001U /*!< Transfer completed */
+#define USB_OTG_HCINT_CHH 0x00000002U /*!< Channel halted */
+#define USB_OTG_HCINT_AHBERR 0x00000004U /*!< AHB error */
+#define USB_OTG_HCINT_STALL 0x00000008U /*!< STALL response received interrupt */
+#define USB_OTG_HCINT_NAK 0x00000010U /*!< NAK response received interrupt */
+#define USB_OTG_HCINT_ACK 0x00000020U /*!< ACK response received/transmitted interrupt */
+#define USB_OTG_HCINT_NYET 0x00000040U /*!< Response received interrupt */
+#define USB_OTG_HCINT_TXERR 0x00000080U /*!< Transaction error */
+#define USB_OTG_HCINT_BBERR 0x00000100U /*!< Babble error */
+#define USB_OTG_HCINT_FRMOR 0x00000200U /*!< Frame overrun */
+#define USB_OTG_HCINT_DTERR 0x00000400U /*!< Data toggle error */
+
+/******************** Bit definition forUSB_OTG_DIEPINT register ********************/
+#define USB_OTG_DIEPINT_XFRC 0x00000001U /*!< Transfer completed interrupt */
+#define USB_OTG_DIEPINT_EPDISD 0x00000002U /*!< Endpoint disabled interrupt */
+#define USB_OTG_DIEPINT_TOC 0x00000008U /*!< Timeout condition */
+#define USB_OTG_DIEPINT_ITTXFE 0x00000010U /*!< IN token received when TxFIFO is empty */
+#define USB_OTG_DIEPINT_INEPNE 0x00000040U /*!< IN endpoint NAK effective */
+#define USB_OTG_DIEPINT_TXFE 0x00000080U /*!< Transmit FIFO empty */
+#define USB_OTG_DIEPINT_TXFIFOUDRN 0x00000100U /*!< Transmit Fifo Underrun */
+#define USB_OTG_DIEPINT_BNA 0x00000200U /*!< Buffer not available interrupt */
+#define USB_OTG_DIEPINT_PKTDRPSTS 0x00000800U /*!< Packet dropped status */
+#define USB_OTG_DIEPINT_BERR 0x00001000U /*!< Babble error interrupt */
+#define USB_OTG_DIEPINT_NAK 0x00002000U /*!< NAK interrupt */
+
+/******************** Bit definition forUSB_OTG_HCINTMSK register ********************/
+#define USB_OTG_HCINTMSK_XFRCM 0x00000001U /*!< Transfer completed mask */
+#define USB_OTG_HCINTMSK_CHHM 0x00000002U /*!< Channel halted mask */
+#define USB_OTG_HCINTMSK_AHBERR 0x00000004U /*!< AHB error */
+#define USB_OTG_HCINTMSK_STALLM 0x00000008U /*!< STALL response received interrupt mask */
+#define USB_OTG_HCINTMSK_NAKM 0x00000010U /*!< NAK response received interrupt mask */
+#define USB_OTG_HCINTMSK_ACKM 0x00000020U /*!< ACK response received/transmitted interrupt mask */
+#define USB_OTG_HCINTMSK_NYET 0x00000040U /*!< response received interrupt mask */
+#define USB_OTG_HCINTMSK_TXERRM 0x00000080U /*!< Transaction error mask */
+#define USB_OTG_HCINTMSK_BBERRM 0x00000100U /*!< Babble error mask */
+#define USB_OTG_HCINTMSK_FRMORM 0x00000200U /*!< Frame overrun mask */
+#define USB_OTG_HCINTMSK_DTERRM 0x00000400U /*!< Data toggle error mask */
+
+/******************** Bit definition for USB_OTG_DIEPTSIZ register ********************/
+
+#define USB_OTG_DIEPTSIZ_XFRSIZ 0x0007FFFFU /*!< Transfer size */
+#define USB_OTG_DIEPTSIZ_PKTCNT 0x1FF80000U /*!< Packet count */
+#define USB_OTG_DIEPTSIZ_MULCNT 0x60000000U /*!< Packet count */
+/******************** Bit definition forUSB_OTG_HCTSIZ register ********************/
+#define USB_OTG_HCTSIZ_XFRSIZ 0x0007FFFFU /*!< Transfer size */
+#define USB_OTG_HCTSIZ_PKTCNT 0x1FF80000U /*!< Packet count */
+#define USB_OTG_HCTSIZ_DOPING 0x80000000U /*!< Do PING */
+#define USB_OTG_HCTSIZ_DPID 0x60000000U /*!< Data PID */
+#define USB_OTG_HCTSIZ_DPID_0 0x20000000U /*!<Bit 0 */
+#define USB_OTG_HCTSIZ_DPID_1 0x40000000U /*!<Bit 1 */
+
+/******************** Bit definition forUSB_OTG_DIEPDMA register ********************/
+#define USB_OTG_DIEPDMA_DMAADDR 0xFFFFFFFFU /*!< DMA address */
+
+/******************** Bit definition forUSB_OTG_HCDMA register ********************/
+#define USB_OTG_HCDMA_DMAADDR 0xFFFFFFFFU /*!< DMA address */
+
+/******************** Bit definition forUSB_OTG_DTXFSTS register ********************/
+#define USB_OTG_DTXFSTS_INEPTFSAV 0x0000FFFFU /*!< IN endpoint TxFIFO space available */
+
+/******************** Bit definition forUSB_OTG_DIEPTXF register ********************/
+#define USB_OTG_DIEPTXF_INEPTXSA 0x0000FFFFU /*!< IN endpoint FIFOx transmit RAM start address */
+#define USB_OTG_DIEPTXF_INEPTXFD 0xFFFF0000U /*!< IN endpoint TxFIFO depth */
+
+/******************** Bit definition forUSB_OTG_DOEPCTL register ********************/
+
+#define USB_OTG_DOEPCTL_MPSIZ 0x000007FFU /*!< Maximum packet size */ /*!<Bit 1 */
+#define USB_OTG_DOEPCTL_USBAEP 0x00008000U /*!< USB active endpoint */
+#define USB_OTG_DOEPCTL_NAKSTS 0x00020000U /*!< NAK status */
+#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM 0x10000000U /*!< Set DATA0 PID */
+#define USB_OTG_DOEPCTL_SODDFRM 0x20000000U /*!< Set odd frame */
+#define USB_OTG_DOEPCTL_EPTYP 0x000C0000U /*!< Endpoint type */
+#define USB_OTG_DOEPCTL_EPTYP_0 0x00040000U /*!<Bit 0 */
+#define USB_OTG_DOEPCTL_EPTYP_1 0x00080000U /*!<Bit 1 */
+#define USB_OTG_DOEPCTL_SNPM 0x00100000U /*!< Snoop mode */
+#define USB_OTG_DOEPCTL_STALL 0x00200000U /*!< STALL handshake */
+#define USB_OTG_DOEPCTL_CNAK 0x04000000U /*!< Clear NAK */
+#define USB_OTG_DOEPCTL_SNAK 0x08000000U /*!< Set NAK */
+#define USB_OTG_DOEPCTL_EPDIS 0x40000000U /*!< Endpoint disable */
+#define USB_OTG_DOEPCTL_EPENA 0x80000000U /*!< Endpoint enable */
+
+/******************** Bit definition forUSB_OTG_DOEPINT register ********************/
+#define USB_OTG_DOEPINT_XFRC 0x00000001U /*!< Transfer completed interrupt */
+#define USB_OTG_DOEPINT_EPDISD 0x00000002U /*!< Endpoint disabled interrupt */
+#define USB_OTG_DOEPINT_STUP 0x00000008U /*!< SETUP phase done */
+#define USB_OTG_DOEPINT_OTEPDIS 0x00000010U /*!< OUT token received when endpoint disabled */
+#define USB_OTG_DOEPINT_OTEPSPR 0x00000020U /*!< Status Phase Received For Control Write */
+#define USB_OTG_DOEPINT_B2BSTUP 0x00000040U /*!< Back-to-back SETUP packets received */
+#define USB_OTG_DOEPINT_NYET 0x00004000U /*!< NYET interrupt */
+
+/******************** Bit definition forUSB_OTG_DOEPTSIZ register ********************/
+
+#define USB_OTG_DOEPTSIZ_XFRSIZ 0x0007FFFFU /*!< Transfer size */
+#define USB_OTG_DOEPTSIZ_PKTCNT 0x1FF80000U /*!< Packet count */
+
+#define USB_OTG_DOEPTSIZ_STUPCNT 0x60000000U /*!< SETUP packet count */
+#define USB_OTG_DOEPTSIZ_STUPCNT_0 0x20000000U /*!<Bit 0 */
+#define USB_OTG_DOEPTSIZ_STUPCNT_1 0x40000000U /*!<Bit 1 */
+
+/******************** Bit definition for PCGCCTL register ********************/
+#define USB_OTG_PCGCCTL_STOPCLK 0x00000001U /*!< SETUP packet count */
+#define USB_OTG_PCGCCTL_GATECLK 0x00000002U /*!<Bit 0 */
+#define USB_OTG_PCGCCTL_PHYSUSP 0x00000010U /*!<Bit 1 */
+
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup Exported_macros
+ * @{
+ */
+
+/******************************* ADC Instances ********************************/
+#define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) || \
+ ((INSTANCE) == ADC2) || \
+ ((INSTANCE) == ADC3))
+
+/******************************* CAN Instances ********************************/
+#define IS_CAN_ALL_INSTANCE(INSTANCE) (((INSTANCE) == CAN1) || \
+ ((INSTANCE) == CAN2))
+
+/******************************* CRC Instances ********************************/
+#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
+
+/******************************* DAC Instances ********************************/
+#define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC)
+
+/******************************* DCMI Instances *******************************/
+#define IS_DCMI_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DCMI)
+
+/******************************* DMA2D Instances *******************************/
+#define IS_DMA2D_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DMA2D)
+
+/******************************** DMA Instances *******************************/
+#define IS_DMA_STREAM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0) || \
+ ((INSTANCE) == DMA1_Stream1) || \
+ ((INSTANCE) == DMA1_Stream2) || \
+ ((INSTANCE) == DMA1_Stream3) || \
+ ((INSTANCE) == DMA1_Stream4) || \
+ ((INSTANCE) == DMA1_Stream5) || \
+ ((INSTANCE) == DMA1_Stream6) || \
+ ((INSTANCE) == DMA1_Stream7) || \
+ ((INSTANCE) == DMA2_Stream0) || \
+ ((INSTANCE) == DMA2_Stream1) || \
+ ((INSTANCE) == DMA2_Stream2) || \
+ ((INSTANCE) == DMA2_Stream3) || \
+ ((INSTANCE) == DMA2_Stream4) || \
+ ((INSTANCE) == DMA2_Stream5) || \
+ ((INSTANCE) == DMA2_Stream6) || \
+ ((INSTANCE) == DMA2_Stream7))
+
+/******************************* GPIO Instances *******************************/
+#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
+ ((INSTANCE) == GPIOB) || \
+ ((INSTANCE) == GPIOC) || \
+ ((INSTANCE) == GPIOD) || \
+ ((INSTANCE) == GPIOE) || \
+ ((INSTANCE) == GPIOF) || \
+ ((INSTANCE) == GPIOG) || \
+ ((INSTANCE) == GPIOH) || \
+ ((INSTANCE) == GPIOI) || \
+ ((INSTANCE) == GPIOJ) || \
+ ((INSTANCE) == GPIOK))
+
+/******************************** I2C Instances *******************************/
+#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
+ ((INSTANCE) == I2C2) || \
+ ((INSTANCE) == I2C3))
+
+/******************************** I2S Instances *******************************/
+#define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI2) || \
+ ((INSTANCE) == SPI3))
+
+/*************************** I2S Extended Instances ***************************/
+#define IS_I2S_ALL_INSTANCE_EXT(PERIPH) (((INSTANCE) == SPI2) || \
+ ((INSTANCE) == SPI3) || \
+ ((INSTANCE) == I2S2ext) || \
+ ((INSTANCE) == I2S3ext))
+
+/****************************** LTDC Instances ********************************/
+#define IS_LTDC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == LTDC)
+
+/******************************* RNG Instances ********************************/
+#define IS_RNG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RNG)
+
+/****************************** RTC Instances *********************************/
+#define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
+
+/******************************* SAI Instances ********************************/
+#define IS_SAI_ALL_INSTANCE(PERIPH) (((PERIPH) == SAI1_Block_A) || \
+ ((PERIPH) == SAI1_Block_B))
+/* Legacy define */
+#define IS_SAI_BLOCK_PERIPH IS_SAI_ALL_INSTANCE
+
+/******************************** SPI Instances *******************************/
+#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
+ ((INSTANCE) == SPI2) || \
+ ((INSTANCE) == SPI3) || \
+ ((INSTANCE) == SPI4) || \
+ ((INSTANCE) == SPI5) || \
+ ((INSTANCE) == SPI6))
+
+/*************************** SPI Extended Instances ***************************/
+#define IS_SPI_ALL_INSTANCE_EXT(INSTANCE) (((INSTANCE) == SPI1) || \
+ ((INSTANCE) == SPI2) || \
+ ((INSTANCE) == SPI3) || \
+ ((INSTANCE) == SPI4) || \
+ ((INSTANCE) == SPI5) || \
+ ((INSTANCE) == SPI6) || \
+ ((INSTANCE) == I2S2ext) || \
+ ((INSTANCE) == I2S3ext))
+
+/****************** TIM Instances : All supported instances *******************/
+#define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM6) || \
+ ((INSTANCE) == TIM7) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM9) || \
+ ((INSTANCE) == TIM10) || \
+ ((INSTANCE) == TIM11) || \
+ ((INSTANCE) == TIM12) || \
+ ((INSTANCE) == TIM13) || \
+ ((INSTANCE) == TIM14))
+
+/************* TIM Instances : at least 1 capture/compare channel *************/
+#define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM9) || \
+ ((INSTANCE) == TIM10) || \
+ ((INSTANCE) == TIM11) || \
+ ((INSTANCE) == TIM12) || \
+ ((INSTANCE) == TIM13) || \
+ ((INSTANCE) == TIM14))
+
+/************ TIM Instances : at least 2 capture/compare channels *************/
+#define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM9) || \
+ ((INSTANCE) == TIM12))
+
+/************ TIM Instances : at least 3 capture/compare channels *************/
+#define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8))
+
+/************ TIM Instances : at least 4 capture/compare channels *************/
+#define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8))
+
+/******************** TIM Instances : Advanced-control timers *****************/
+#define IS_TIM_ADVANCED_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM8))
+
+/******************* TIM Instances : Timer input XOR function *****************/
+#define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8))
+
+/****************** TIM Instances : DMA requests generation (UDE) *************/
+#define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM6) || \
+ ((INSTANCE) == TIM7) || \
+ ((INSTANCE) == TIM8))
+
+/************ TIM Instances : DMA requests generation (CCxDE) *****************/
+#define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8))
+
+/************ TIM Instances : DMA requests generation (COMDE) *****************/
+#define IS_TIM_CCDMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8))
+
+/******************** TIM Instances : DMA burst feature ***********************/
+#define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8))
+
+/****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/
+#define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM6) || \
+ ((INSTANCE) == TIM7) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM9) || \
+ ((INSTANCE) == TIM12))
+
+/*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
+#define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM9) || \
+ ((INSTANCE) == TIM12))
+
+/********************** TIM Instances : 32 bit Counter ************************/
+#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)(((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM5))
+
+/***************** TIM Instances : external trigger input availabe ************/
+#define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8))
+
+/****************** TIM Instances : remapping capability **********************/
+#define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM11))
+
+/******************* TIM Instances : output(s) available **********************/
+#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
+ ((((INSTANCE) == TIM1) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM2) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM3) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM4) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM5) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM8) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM9) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2))) \
+ || \
+ (((INSTANCE) == TIM10) && \
+ (((CHANNEL) == TIM_CHANNEL_1))) \
+ || \
+ (((INSTANCE) == TIM11) && \
+ (((CHANNEL) == TIM_CHANNEL_1))) \
+ || \
+ (((INSTANCE) == TIM12) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2))) \
+ || \
+ (((INSTANCE) == TIM13) && \
+ (((CHANNEL) == TIM_CHANNEL_1))) \
+ || \
+ (((INSTANCE) == TIM14) && \
+ (((CHANNEL) == TIM_CHANNEL_1))))
+
+/************ TIM Instances : complementary output(s) available ***************/
+#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
+ ((((INSTANCE) == TIM1) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3))) \
+ || \
+ (((INSTANCE) == TIM8) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3))))
+
+/******************** USART Instances : Synchronous mode **********************/
+#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3) || \
+ ((INSTANCE) == USART6))
+
+/******************** UART Instances : Asynchronous mode **********************/
+#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3) || \
+ ((INSTANCE) == UART4) || \
+ ((INSTANCE) == UART5) || \
+ ((INSTANCE) == USART6) || \
+ ((INSTANCE) == UART7) || \
+ ((INSTANCE) == UART8))
+
+/****************** UART Instances : Hardware Flow control ********************/
+#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3) || \
+ ((INSTANCE) == USART6))
+
+/********************* UART Instances : Smard card mode ***********************/
+#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3) || \
+ ((INSTANCE) == USART6))
+
+/*********************** UART Instances : IRDA mode ***************************/
+#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3) || \
+ ((INSTANCE) == UART4) || \
+ ((INSTANCE) == UART5) || \
+ ((INSTANCE) == USART6) || \
+ ((INSTANCE) == UART7) || \
+ ((INSTANCE) == UART8))
+
+/*********************** PCD Instances ****************************************/
+#define IS_PCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS) || \
+ ((INSTANCE) == USB_OTG_HS))
+
+/*********************** HCD Instances ****************************************/
+#define IS_HCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS) || \
+ ((INSTANCE) == USB_OTG_HS))
+
+/****************************** SDIO Instances ********************************/
+#define IS_SDIO_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SDIO)
+
+/****************************** IWDG Instances ********************************/
+#define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
+
+/****************************** WWDG Instances ********************************/
+#define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
+
+/****************************** QSPI Instances ********************************/
+#define IS_QSPI_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == QUADSPI)
+
+/****************************** USB Exported Constants ************************/
+#define USB_OTG_FS_HOST_MAX_CHANNEL_NBR 12U
+#define USB_OTG_FS_MAX_IN_ENDPOINTS 6U /* Including EP0 */
+#define USB_OTG_FS_MAX_OUT_ENDPOINTS 6U /* Including EP0 */
+#define USB_OTG_FS_TOTAL_FIFO_SIZE 1280U /* in Bytes */
+
+#define USB_OTG_HS_HOST_MAX_CHANNEL_NBR 16U
+#define USB_OTG_HS_MAX_IN_ENDPOINTS 8U /* Including EP0 */
+#define USB_OTG_HS_MAX_OUT_ENDPOINTS 8U /* Including EP0 */
+#define USB_OTG_HS_TOTAL_FIFO_SIZE 4096U /* in Bytes */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* __STM32F469xx_H */
+
+
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Device/ST/STM32F4xx/Include/stm32f479xx.h b/Device/ST/STM32F4xx/Include/stm32f479xx.h
new file mode 100644
index 0000000..c4833ec
--- /dev/null
+++ b/Device/ST/STM32F4xx/Include/stm32f479xx.h
@@ -0,0 +1,10441 @@
+/**
+ ******************************************************************************
+ * @file stm32f479xx.h
+ * @author MCD Application Team
+ * @version V2.5.0
+ * @date 22-April-2016
+ * @brief CMSIS STM32F479xx Device Peripheral Access Layer Header File.
+ *
+ * This file contains:
+ * - Data structures and the address mapping for all peripherals
+ * - peripherals registers declarations and bits definition
+ * - Macros to access peripheral’s registers hardware
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/** @addtogroup CMSIS_Device
+ * @{
+ */
+
+/** @addtogroup stm32f479xx
+ * @{
+ */
+
+#ifndef __STM32F479xx_H
+#define __STM32F479xx_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif /* __cplusplus */
+
+/** @addtogroup Configuration_section_for_CMSIS
+ * @{
+ */
+
+/**
+ * @brief Configuration of the Cortex-M4 Processor and Core Peripherals
+ */
+#define __CM4_REV 0x0001U /*!< Core revision r0p1 */
+#define __MPU_PRESENT 1U /*!< STM32F4XX provides an MPU */
+#define __NVIC_PRIO_BITS 4U /*!< STM32F4XX uses 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */
+#define __FPU_PRESENT 1U /*!< FPU present */
+
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_interrupt_number_definition
+ * @{
+ */
+
+/**
+ * @brief STM32F4XX Interrupt Number Definition, according to the selected device
+ * in @ref Library_configuration_section
+ */
+typedef enum
+{
+/****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/
+ NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
+ MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */
+ BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */
+ UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */
+ SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */
+ DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */
+ PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */
+ SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */
+/****** STM32 specific Interrupt Numbers **********************************************************************/
+ WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
+ PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */
+ TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */
+ RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */
+ FLASH_IRQn = 4, /*!< FLASH global Interrupt */
+ RCC_IRQn = 5, /*!< RCC global Interrupt */
+ EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */
+ EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */
+ EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */
+ EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */
+ EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */
+ DMA1_Stream0_IRQn = 11, /*!< DMA1 Stream 0 global Interrupt */
+ DMA1_Stream1_IRQn = 12, /*!< DMA1 Stream 1 global Interrupt */
+ DMA1_Stream2_IRQn = 13, /*!< DMA1 Stream 2 global Interrupt */
+ DMA1_Stream3_IRQn = 14, /*!< DMA1 Stream 3 global Interrupt */
+ DMA1_Stream4_IRQn = 15, /*!< DMA1 Stream 4 global Interrupt */
+ DMA1_Stream5_IRQn = 16, /*!< DMA1 Stream 5 global Interrupt */
+ DMA1_Stream6_IRQn = 17, /*!< DMA1 Stream 6 global Interrupt */
+ ADC_IRQn = 18, /*!< ADC1, ADC2 and ADC3 global Interrupts */
+ CAN1_TX_IRQn = 19, /*!< CAN1 TX Interrupt */
+ CAN1_RX0_IRQn = 20, /*!< CAN1 RX0 Interrupt */
+ CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */
+ CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */
+ EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
+ TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break interrupt and TIM9 global interrupt */
+ TIM1_UP_TIM10_IRQn = 25, /*!< TIM1 Update Interrupt and TIM10 global interrupt */
+ TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */
+ TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
+ TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
+ TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
+ TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
+ I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
+ I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
+ I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
+ I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
+ SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
+ SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
+ USART1_IRQn = 37, /*!< USART1 global Interrupt */
+ USART2_IRQn = 38, /*!< USART2 global Interrupt */
+ USART3_IRQn = 39, /*!< USART3 global Interrupt */
+ EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
+ RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */
+ OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS Wakeup through EXTI line interrupt */
+ TIM8_BRK_TIM12_IRQn = 43, /*!< TIM8 Break Interrupt and TIM12 global interrupt */
+ TIM8_UP_TIM13_IRQn = 44, /*!< TIM8 Update Interrupt and TIM13 global interrupt */
+ TIM8_TRG_COM_TIM14_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */
+ TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare global interrupt */
+ DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */
+ FMC_IRQn = 48, /*!< FMC global Interrupt */
+ SDIO_IRQn = 49, /*!< SDIO global Interrupt */
+ TIM5_IRQn = 50, /*!< TIM5 global Interrupt */
+ SPI3_IRQn = 51, /*!< SPI3 global Interrupt */
+ UART4_IRQn = 52, /*!< UART4 global Interrupt */
+ UART5_IRQn = 53, /*!< UART5 global Interrupt */
+ TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC1&2 underrun error interrupts */
+ TIM7_IRQn = 55, /*!< TIM7 global interrupt */
+ DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */
+ DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */
+ DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */
+ DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */
+ DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */
+ ETH_IRQn = 61, /*!< Ethernet global Interrupt */
+ ETH_WKUP_IRQn = 62, /*!< Ethernet Wakeup through EXTI line Interrupt */
+ CAN2_TX_IRQn = 63, /*!< CAN2 TX Interrupt */
+ CAN2_RX0_IRQn = 64, /*!< CAN2 RX0 Interrupt */
+ CAN2_RX1_IRQn = 65, /*!< CAN2 RX1 Interrupt */
+ CAN2_SCE_IRQn = 66, /*!< CAN2 SCE Interrupt */
+ OTG_FS_IRQn = 67, /*!< USB OTG FS global Interrupt */
+ DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */
+ DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */
+ DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */
+ USART6_IRQn = 71, /*!< USART6 global interrupt */
+ I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */
+ I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */
+ OTG_HS_EP1_OUT_IRQn = 74, /*!< USB OTG HS End Point 1 Out global interrupt */
+ OTG_HS_EP1_IN_IRQn = 75, /*!< USB OTG HS End Point 1 In global interrupt */
+ OTG_HS_WKUP_IRQn = 76, /*!< USB OTG HS Wakeup through EXTI interrupt */
+ OTG_HS_IRQn = 77, /*!< USB OTG HS global interrupt */
+ DCMI_IRQn = 78, /*!< DCMI global interrupt */
+ CRYP_IRQn = 79, /*!< CRYP crypto global interrupt */
+ HASH_RNG_IRQn = 80, /*!< Hash and Rng global interrupt */
+ FPU_IRQn = 81, /*!< FPU global interrupt */
+ UART7_IRQn = 82, /*!< UART7 global interrupt */
+ UART8_IRQn = 83, /*!< UART8 global interrupt */
+ SPI4_IRQn = 84, /*!< SPI4 global Interrupt */
+ SPI5_IRQn = 85, /*!< SPI5 global Interrupt */
+ SPI6_IRQn = 86, /*!< SPI6 global Interrupt */
+ SAI1_IRQn = 87, /*!< SAI1 global Interrupt */
+ LTDC_IRQn = 88, /*!< LTDC global Interrupt */
+ LTDC_ER_IRQn = 89, /*!< LTDC Error global Interrupt */
+ DMA2D_IRQn = 90, /*!< DMA2D global Interrupt */
+ QUADSPI_IRQn = 91, /*!< QUADSPI global Interrupt */
+ DSI_IRQn = 92 /*!< DSI global Interrupt */
+} IRQn_Type;
+
+/**
+ * @}
+ */
+
+#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
+#include "system_stm32f4xx.h"
+#include <stdint.h>
+
+/** @addtogroup Peripheral_registers_structures
+ * @{
+ */
+
+/**
+ * @brief Analog to Digital Converter
+ */
+
+typedef struct
+{
+ __IO uint32_t SR; /*!< ADC status register, Address offset: 0x00 */
+ __IO uint32_t CR1; /*!< ADC control register 1, Address offset: 0x04 */
+ __IO uint32_t CR2; /*!< ADC control register 2, Address offset: 0x08 */
+ __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x0C */
+ __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x10 */
+ __IO uint32_t JOFR1; /*!< ADC injected channel data offset register 1, Address offset: 0x14 */
+ __IO uint32_t JOFR2; /*!< ADC injected channel data offset register 2, Address offset: 0x18 */
+ __IO uint32_t JOFR3; /*!< ADC injected channel data offset register 3, Address offset: 0x1C */
+ __IO uint32_t JOFR4; /*!< ADC injected channel data offset register 4, Address offset: 0x20 */
+ __IO uint32_t HTR; /*!< ADC watchdog higher threshold register, Address offset: 0x24 */
+ __IO uint32_t LTR; /*!< ADC watchdog lower threshold register, Address offset: 0x28 */
+ __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x2C */
+ __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x30 */
+ __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x34 */
+ __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x38*/
+ __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x3C */
+ __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x40 */
+ __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x44 */
+ __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x48 */
+ __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x4C */
+} ADC_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1 base address + 0x300 */
+ __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1 base address + 0x304 */
+ __IO uint32_t CDR; /*!< ADC common regular data register for dual
+ AND triple modes, Address offset: ADC1 base address + 0x308 */
+} ADC_Common_TypeDef;
+
+
+/**
+ * @brief Controller Area Network TxMailBox
+ */
+
+typedef struct
+{
+ __IO uint32_t TIR; /*!< CAN TX mailbox identifier register */
+ __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */
+ __IO uint32_t TDLR; /*!< CAN mailbox data low register */
+ __IO uint32_t TDHR; /*!< CAN mailbox data high register */
+} CAN_TxMailBox_TypeDef;
+
+/**
+ * @brief Controller Area Network FIFOMailBox
+ */
+
+typedef struct
+{
+ __IO uint32_t RIR; /*!< CAN receive FIFO mailbox identifier register */
+ __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */
+ __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */
+ __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */
+} CAN_FIFOMailBox_TypeDef;
+
+/**
+ * @brief Controller Area Network FilterRegister
+ */
+
+typedef struct
+{
+ __IO uint32_t FR1; /*!< CAN Filter bank register 1 */
+ __IO uint32_t FR2; /*!< CAN Filter bank register 1 */
+} CAN_FilterRegister_TypeDef;
+
+/**
+ * @brief Controller Area Network
+ */
+
+typedef struct
+{
+ __IO uint32_t MCR; /*!< CAN master control register, Address offset: 0x00 */
+ __IO uint32_t MSR; /*!< CAN master status register, Address offset: 0x04 */
+ __IO uint32_t TSR; /*!< CAN transmit status register, Address offset: 0x08 */
+ __IO uint32_t RF0R; /*!< CAN receive FIFO 0 register, Address offset: 0x0C */
+ __IO uint32_t RF1R; /*!< CAN receive FIFO 1 register, Address offset: 0x10 */
+ __IO uint32_t IER; /*!< CAN interrupt enable register, Address offset: 0x14 */
+ __IO uint32_t ESR; /*!< CAN error status register, Address offset: 0x18 */
+ __IO uint32_t BTR; /*!< CAN bit timing register, Address offset: 0x1C */
+ uint32_t RESERVED0[88]; /*!< Reserved, 0x020 - 0x17F */
+ CAN_TxMailBox_TypeDef sTxMailBox[3]; /*!< CAN Tx MailBox, Address offset: 0x180 - 0x1AC */
+ CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; /*!< CAN FIFO MailBox, Address offset: 0x1B0 - 0x1CC */
+ uint32_t RESERVED1[12]; /*!< Reserved, 0x1D0 - 0x1FF */
+ __IO uint32_t FMR; /*!< CAN filter master register, Address offset: 0x200 */
+ __IO uint32_t FM1R; /*!< CAN filter mode register, Address offset: 0x204 */
+ uint32_t RESERVED2; /*!< Reserved, 0x208 */
+ __IO uint32_t FS1R; /*!< CAN filter scale register, Address offset: 0x20C */
+ uint32_t RESERVED3; /*!< Reserved, 0x210 */
+ __IO uint32_t FFA1R; /*!< CAN filter FIFO assignment register, Address offset: 0x214 */
+ uint32_t RESERVED4; /*!< Reserved, 0x218 */
+ __IO uint32_t FA1R; /*!< CAN filter activation register, Address offset: 0x21C */
+ uint32_t RESERVED5[8]; /*!< Reserved, 0x220-0x23F */
+ CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register, Address offset: 0x240-0x31C */
+} CAN_TypeDef;
+
+/**
+ * @brief CRC calculation unit
+ */
+
+typedef struct
+{
+ __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
+ __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
+ uint8_t RESERVED0; /*!< Reserved, 0x05 */
+ uint16_t RESERVED1; /*!< Reserved, 0x06 */
+ __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
+} CRC_TypeDef;
+
+/**
+ * @brief Digital to Analog Converter
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */
+ __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */
+ __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
+ __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */
+ __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */
+ __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
+ __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */
+ __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */
+ __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */
+ __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */
+ __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */
+ __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */
+ __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */
+ __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */
+} DAC_TypeDef;
+
+/**
+ * @brief Debug MCU
+ */
+
+typedef struct
+{
+ __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
+ __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
+ __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */
+ __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */
+}DBGMCU_TypeDef;
+
+/**
+ * @brief DCMI
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< DCMI control register 1, Address offset: 0x00 */
+ __IO uint32_t SR; /*!< DCMI status register, Address offset: 0x04 */
+ __IO uint32_t RISR; /*!< DCMI raw interrupt status register, Address offset: 0x08 */
+ __IO uint32_t IER; /*!< DCMI interrupt enable register, Address offset: 0x0C */
+ __IO uint32_t MISR; /*!< DCMI masked interrupt status register, Address offset: 0x10 */
+ __IO uint32_t ICR; /*!< DCMI interrupt clear register, Address offset: 0x14 */
+ __IO uint32_t ESCR; /*!< DCMI embedded synchronization code register, Address offset: 0x18 */
+ __IO uint32_t ESUR; /*!< DCMI embedded synchronization unmask register, Address offset: 0x1C */
+ __IO uint32_t CWSTRTR; /*!< DCMI crop window start, Address offset: 0x20 */
+ __IO uint32_t CWSIZER; /*!< DCMI crop window size, Address offset: 0x24 */
+ __IO uint32_t DR; /*!< DCMI data register, Address offset: 0x28 */
+} DCMI_TypeDef;
+
+/**
+ * @brief DMA Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< DMA stream x configuration register */
+ __IO uint32_t NDTR; /*!< DMA stream x number of data register */
+ __IO uint32_t PAR; /*!< DMA stream x peripheral address register */
+ __IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */
+ __IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */
+ __IO uint32_t FCR; /*!< DMA stream x FIFO control register */
+} DMA_Stream_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t LISR; /*!< DMA low interrupt status register, Address offset: 0x00 */
+ __IO uint32_t HISR; /*!< DMA high interrupt status register, Address offset: 0x04 */
+ __IO uint32_t LIFCR; /*!< DMA low interrupt flag clear register, Address offset: 0x08 */
+ __IO uint32_t HIFCR; /*!< DMA high interrupt flag clear register, Address offset: 0x0C */
+} DMA_TypeDef;
+
+/**
+ * @brief DMA2D Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< DMA2D Control Register, Address offset: 0x00 */
+ __IO uint32_t ISR; /*!< DMA2D Interrupt Status Register, Address offset: 0x04 */
+ __IO uint32_t IFCR; /*!< DMA2D Interrupt Flag Clear Register, Address offset: 0x08 */
+ __IO uint32_t FGMAR; /*!< DMA2D Foreground Memory Address Register, Address offset: 0x0C */
+ __IO uint32_t FGOR; /*!< DMA2D Foreground Offset Register, Address offset: 0x10 */
+ __IO uint32_t BGMAR; /*!< DMA2D Background Memory Address Register, Address offset: 0x14 */
+ __IO uint32_t BGOR; /*!< DMA2D Background Offset Register, Address offset: 0x18 */
+ __IO uint32_t FGPFCCR; /*!< DMA2D Foreground PFC Control Register, Address offset: 0x1C */
+ __IO uint32_t FGCOLR; /*!< DMA2D Foreground Color Register, Address offset: 0x20 */
+ __IO uint32_t BGPFCCR; /*!< DMA2D Background PFC Control Register, Address offset: 0x24 */
+ __IO uint32_t BGCOLR; /*!< DMA2D Background Color Register, Address offset: 0x28 */
+ __IO uint32_t FGCMAR; /*!< DMA2D Foreground CLUT Memory Address Register, Address offset: 0x2C */
+ __IO uint32_t BGCMAR; /*!< DMA2D Background CLUT Memory Address Register, Address offset: 0x30 */
+ __IO uint32_t OPFCCR; /*!< DMA2D Output PFC Control Register, Address offset: 0x34 */
+ __IO uint32_t OCOLR; /*!< DMA2D Output Color Register, Address offset: 0x38 */
+ __IO uint32_t OMAR; /*!< DMA2D Output Memory Address Register, Address offset: 0x3C */
+ __IO uint32_t OOR; /*!< DMA2D Output Offset Register, Address offset: 0x40 */
+ __IO uint32_t NLR; /*!< DMA2D Number of Line Register, Address offset: 0x44 */
+ __IO uint32_t LWR; /*!< DMA2D Line Watermark Register, Address offset: 0x48 */
+ __IO uint32_t AMTCR; /*!< DMA2D AHB Master Timer Configuration Register, Address offset: 0x4C */
+ uint32_t RESERVED[236]; /*!< Reserved, 0x50-0x3FF */
+ __IO uint32_t FGCLUT[256]; /*!< DMA2D Foreground CLUT, Address offset:400-7FF */
+ __IO uint32_t BGCLUT[256]; /*!< DMA2D Background CLUT, Address offset:800-BFF */
+} DMA2D_TypeDef;
+
+/**
+ * @brief DSI Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t VR; /*!< DSI Host Version Register, Address offset: 0x00 */
+ __IO uint32_t CR; /*!< DSI Host Control Register, Address offset: 0x04 */
+ __IO uint32_t CCR; /*!< DSI HOST Clock Control Register, Address offset: 0x08 */
+ __IO uint32_t LVCIDR; /*!< DSI Host LTDC VCID Register, Address offset: 0x0C */
+ __IO uint32_t LCOLCR; /*!< DSI Host LTDC Color Coding Register, Address offset: 0x10 */
+ __IO uint32_t LPCR; /*!< DSI Host LTDC Polarity Configuration Register, Address offset: 0x14 */
+ __IO uint32_t LPMCR; /*!< DSI Host Low-Power Mode Configuration Register, Address offset: 0x18 */
+ uint32_t RESERVED0[4]; /*!< Reserved, 0x1C - 0x2B */
+ __IO uint32_t PCR; /*!< DSI Host Protocol Configuration Register, Address offset: 0x2C */
+ __IO uint32_t GVCIDR; /*!< DSI Host Generic VCID Register, Address offset: 0x30 */
+ __IO uint32_t MCR; /*!< DSI Host Mode Configuration Register, Address offset: 0x34 */
+ __IO uint32_t VMCR; /*!< DSI Host Video Mode Configuration Register, Address offset: 0x38 */
+ __IO uint32_t VPCR; /*!< DSI Host Video Packet Configuration Register, Address offset: 0x3C */
+ __IO uint32_t VCCR; /*!< DSI Host Video Chunks Configuration Register, Address offset: 0x40 */
+ __IO uint32_t VNPCR; /*!< DSI Host Video Null Packet Configuration Register, Address offset: 0x44 */
+ __IO uint32_t VHSACR; /*!< DSI Host Video HSA Configuration Register, Address offset: 0x48 */
+ __IO uint32_t VHBPCR; /*!< DSI Host Video HBP Configuration Register, Address offset: 0x4C */
+ __IO uint32_t VLCR; /*!< DSI Host Video Line Configuration Register, Address offset: 0x50 */
+ __IO uint32_t VVSACR; /*!< DSI Host Video VSA Configuration Register, Address offset: 0x54 */
+ __IO uint32_t VVBPCR; /*!< DSI Host Video VBP Configuration Register, Address offset: 0x58 */
+ __IO uint32_t VVFPCR; /*!< DSI Host Video VFP Configuration Register, Address offset: 0x5C */
+ __IO uint32_t VVACR; /*!< DSI Host Video VA Configuration Register, Address offset: 0x60 */
+ __IO uint32_t LCCR; /*!< DSI Host LTDC Command Configuration Register, Address offset: 0x64 */
+ __IO uint32_t CMCR; /*!< DSI Host Command Mode Configuration Register, Address offset: 0x68 */
+ __IO uint32_t GHCR; /*!< DSI Host Generic Header Configuration Register, Address offset: 0x6C */
+ __IO uint32_t GPDR; /*!< DSI Host Generic Payload Data Register, Address offset: 0x70 */
+ __IO uint32_t GPSR; /*!< DSI Host Generic Packet Status Register, Address offset: 0x74 */
+ __IO uint32_t TCCR[6]; /*!< DSI Host Timeout Counter Configuration Register, Address offset: 0x78-0x8F */
+ __IO uint32_t TDCR; /*!< DSI Host 3D Configuration Register, Address offset: 0x90 */
+ __IO uint32_t CLCR; /*!< DSI Host Clock Lane Configuration Register, Address offset: 0x94 */
+ __IO uint32_t CLTCR; /*!< DSI Host Clock Lane Timer Configuration Register, Address offset: 0x98 */
+ __IO uint32_t DLTCR; /*!< DSI Host Data Lane Timer Configuration Register, Address offset: 0x9C */
+ __IO uint32_t PCTLR; /*!< DSI Host PHY Control Register, Address offset: 0xA0 */
+ __IO uint32_t PCONFR; /*!< DSI Host PHY Configuration Register, Address offset: 0xA4 */
+ __IO uint32_t PUCR; /*!< DSI Host PHY ULPS Control Register, Address offset: 0xA8 */
+ __IO uint32_t PTTCR; /*!< DSI Host PHY TX Triggers Configuration Register, Address offset: 0xAC */
+ __IO uint32_t PSR; /*!< DSI Host PHY Status Register, Address offset: 0xB0 */
+ uint32_t RESERVED1[2]; /*!< Reserved, 0xB4 - 0xBB */
+ __IO uint32_t ISR[2]; /*!< DSI Host Interrupt & Status Register, Address offset: 0xBC-0xC3 */
+ __IO uint32_t IER[2]; /*!< DSI Host Interrupt Enable Register, Address offset: 0xC4-0xCB */
+ uint32_t RESERVED2[3]; /*!< Reserved, 0xD0 - 0xD7 */
+ __IO uint32_t FIR[2]; /*!< DSI Host Force Interrupt Register, Address offset: 0xD8-0xDF */
+ uint32_t RESERVED3[8]; /*!< Reserved, 0xE0 - 0xFF */
+ __IO uint32_t VSCR; /*!< DSI Host Video Shadow Control Register, Address offset: 0x100 */
+ uint32_t RESERVED4[2]; /*!< Reserved, 0x104 - 0x10B */
+ __IO uint32_t LCVCIDR; /*!< DSI Host LTDC Current VCID Register, Address offset: 0x10C */
+ __IO uint32_t LCCCR; /*!< DSI Host LTDC Current Color Coding Register, Address offset: 0x110 */
+ uint32_t RESERVED5; /*!< Reserved, 0x114 */
+ __IO uint32_t LPMCCR; /*!< DSI Host Low-power Mode Current Configuration Register, Address offset: 0x118 */
+ uint32_t RESERVED6[7]; /*!< Reserved, 0x11C - 0x137 */
+ __IO uint32_t VMCCR; /*!< DSI Host Video Mode Current Configuration Register, Address offset: 0x138 */
+ __IO uint32_t VPCCR; /*!< DSI Host Video Packet Current Configuration Register, Address offset: 0x13C */
+ __IO uint32_t VCCCR; /*!< DSI Host Video Chuncks Current Configuration Register, Address offset: 0x140 */
+ __IO uint32_t VNPCCR; /*!< DSI Host Video Null Packet Current Configuration Register, Address offset: 0x144 */
+ __IO uint32_t VHSACCR; /*!< DSI Host Video HSA Current Configuration Register, Address offset: 0x148 */
+ __IO uint32_t VHBPCCR; /*!< DSI Host Video HBP Current Configuration Register, Address offset: 0x14C */
+ __IO uint32_t VLCCR; /*!< DSI Host Video Line Current Configuration Register, Address offset: 0x150 */
+ __IO uint32_t VVSACCR; /*!< DSI Host Video VSA Current Configuration Register, Address offset: 0x154 */
+ __IO uint32_t VVBPCCR; /*!< DSI Host Video VBP Current Configuration Register, Address offset: 0x158 */
+ __IO uint32_t VVFPCCR; /*!< DSI Host Video VFP Current Configuration Register, Address offset: 0x15C */
+ __IO uint32_t VVACCR; /*!< DSI Host Video VA Current Configuration Register, Address offset: 0x160 */
+ uint32_t RESERVED7[11]; /*!< Reserved, 0x164 - 0x18F */
+ __IO uint32_t TDCCR; /*!< DSI Host 3D Current Configuration Register, Address offset: 0x190 */
+ uint32_t RESERVED8[155]; /*!< Reserved, 0x194 - 0x3FF */
+ __IO uint32_t WCFGR; /*!< DSI Wrapper Configuration Register, Address offset: 0x400 */
+ __IO uint32_t WCR; /*!< DSI Wrapper Control Register, Address offset: 0x404 */
+ __IO uint32_t WIER; /*!< DSI Wrapper Interrupt Enable Register, Address offset: 0x408 */
+ __IO uint32_t WISR; /*!< DSI Wrapper Interrupt and Status Register, Address offset: 0x40C */
+ __IO uint32_t WIFCR; /*!< DSI Wrapper Interrupt Flag Clear Register, Address offset: 0x410 */
+ uint32_t RESERVED9; /*!< Reserved, 0x414 */
+ __IO uint32_t WPCR[5]; /*!< DSI Wrapper PHY Configuration Register, Address offset: 0x418-0x42B */
+ uint32_t RESERVED10; /*!< Reserved, 0x42C */
+ __IO uint32_t WRPCR; /*!< DSI Wrapper Regulator and PLL Control Register, Address offset: 0x430 */
+} DSI_TypeDef;
+
+/**
+ * @brief Ethernet MAC
+ */
+
+typedef struct
+{
+ __IO uint32_t MACCR;
+ __IO uint32_t MACFFR;
+ __IO uint32_t MACHTHR;
+ __IO uint32_t MACHTLR;
+ __IO uint32_t MACMIIAR;
+ __IO uint32_t MACMIIDR;
+ __IO uint32_t MACFCR;
+ __IO uint32_t MACVLANTR; /* 8 */
+ uint32_t RESERVED0[2];
+ __IO uint32_t MACRWUFFR; /* 11 */
+ __IO uint32_t MACPMTCSR;
+ uint32_t RESERVED1[2];
+ __IO uint32_t MACSR; /* 15 */
+ __IO uint32_t MACIMR;
+ __IO uint32_t MACA0HR;
+ __IO uint32_t MACA0LR;
+ __IO uint32_t MACA1HR;
+ __IO uint32_t MACA1LR;
+ __IO uint32_t MACA2HR;
+ __IO uint32_t MACA2LR;
+ __IO uint32_t MACA3HR;
+ __IO uint32_t MACA3LR; /* 24 */
+ uint32_t RESERVED2[40];
+ __IO uint32_t MMCCR; /* 65 */
+ __IO uint32_t MMCRIR;
+ __IO uint32_t MMCTIR;
+ __IO uint32_t MMCRIMR;
+ __IO uint32_t MMCTIMR; /* 69 */
+ uint32_t RESERVED3[14];
+ __IO uint32_t MMCTGFSCCR; /* 84 */
+ __IO uint32_t MMCTGFMSCCR;
+ uint32_t RESERVED4[5];
+ __IO uint32_t MMCTGFCR;
+ uint32_t RESERVED5[10];
+ __IO uint32_t MMCRFCECR;
+ __IO uint32_t MMCRFAECR;
+ uint32_t RESERVED6[10];
+ __IO uint32_t MMCRGUFCR;
+ uint32_t RESERVED7[334];
+ __IO uint32_t PTPTSCR;
+ __IO uint32_t PTPSSIR;
+ __IO uint32_t PTPTSHR;
+ __IO uint32_t PTPTSLR;
+ __IO uint32_t PTPTSHUR;
+ __IO uint32_t PTPTSLUR;
+ __IO uint32_t PTPTSAR;
+ __IO uint32_t PTPTTHR;
+ __IO uint32_t PTPTTLR;
+ __IO uint32_t RESERVED8;
+ __IO uint32_t PTPTSSR;
+ uint32_t RESERVED9[565];
+ __IO uint32_t DMABMR;
+ __IO uint32_t DMATPDR;
+ __IO uint32_t DMARPDR;
+ __IO uint32_t DMARDLAR;
+ __IO uint32_t DMATDLAR;
+ __IO uint32_t DMASR;
+ __IO uint32_t DMAOMR;
+ __IO uint32_t DMAIER;
+ __IO uint32_t DMAMFBOCR;
+ __IO uint32_t DMARSWTR;
+ uint32_t RESERVED10[8];
+ __IO uint32_t DMACHTDR;
+ __IO uint32_t DMACHRDR;
+ __IO uint32_t DMACHTBAR;
+ __IO uint32_t DMACHRBAR;
+} ETH_TypeDef;
+
+/**
+ * @brief External Interrupt/Event Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t IMR; /*!< EXTI Interrupt mask register, Address offset: 0x00 */
+ __IO uint32_t EMR; /*!< EXTI Event mask register, Address offset: 0x04 */
+ __IO uint32_t RTSR; /*!< EXTI Rising trigger selection register, Address offset: 0x08 */
+ __IO uint32_t FTSR; /*!< EXTI Falling trigger selection register, Address offset: 0x0C */
+ __IO uint32_t SWIER; /*!< EXTI Software interrupt event register, Address offset: 0x10 */
+ __IO uint32_t PR; /*!< EXTI Pending register, Address offset: 0x14 */
+} EXTI_TypeDef;
+
+/**
+ * @brief FLASH Registers
+ */
+
+typedef struct
+{
+ __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */
+ __IO uint32_t KEYR; /*!< FLASH key register, Address offset: 0x04 */
+ __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x08 */
+ __IO uint32_t SR; /*!< FLASH status register, Address offset: 0x0C */
+ __IO uint32_t CR; /*!< FLASH control register, Address offset: 0x10 */
+ __IO uint32_t OPTCR; /*!< FLASH option control register , Address offset: 0x14 */
+ __IO uint32_t OPTCR1; /*!< FLASH option control register 1, Address offset: 0x18 */
+} FLASH_TypeDef;
+
+/**
+ * @brief Flexible Memory Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */
+} FMC_Bank1_TypeDef;
+
+/**
+ * @brief Flexible Memory Controller Bank1E
+ */
+
+typedef struct
+{
+ __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */
+} FMC_Bank1E_TypeDef;
+
+/**
+ * @brief Flexible Memory Controller Bank3
+ */
+
+typedef struct
+{
+ __IO uint32_t PCR; /*!< NAND Flash control register, Address offset: 0x80 */
+ __IO uint32_t SR; /*!< NAND Flash FIFO status and interrupt register, Address offset: 0x84 */
+ __IO uint32_t PMEM; /*!< NAND Flash Common memory space timing register, Address offset: 0x88 */
+ __IO uint32_t PATT; /*!< NAND Flash Attribute memory space timing register, Address offset: 0x8C */
+ uint32_t RESERVED; /*!< Reserved, 0x90 */
+ __IO uint32_t ECCR; /*!< NAND Flash ECC result registers, Address offset: 0x94 */
+} FMC_Bank3_TypeDef;
+
+/**
+ * @brief Flexible Memory Controller Bank5_6
+ */
+
+typedef struct
+{
+ __IO uint32_t SDCR[2]; /*!< SDRAM Control registers , Address offset: 0x140-0x144 */
+ __IO uint32_t SDTR[2]; /*!< SDRAM Timing registers , Address offset: 0x148-0x14C */
+ __IO uint32_t SDCMR; /*!< SDRAM Command Mode register, Address offset: 0x150 */
+ __IO uint32_t SDRTR; /*!< SDRAM Refresh Timer register, Address offset: 0x154 */
+ __IO uint32_t SDSR; /*!< SDRAM Status register, Address offset: 0x158 */
+} FMC_Bank5_6_TypeDef;
+
+/**
+ * @brief General Purpose I/O
+ */
+
+typedef struct
+{
+ __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
+ __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */
+ __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */
+ __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
+ __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
+ __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
+ __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */
+ __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
+ __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */
+} GPIO_TypeDef;
+
+/**
+ * @brief System configuration controller
+ */
+
+typedef struct
+{
+ __IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */
+ __IO uint32_t PMC; /*!< SYSCFG peripheral mode configuration register, Address offset: 0x04 */
+ __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
+ uint32_t RESERVED[2]; /*!< Reserved, 0x18-0x1C */
+ __IO uint32_t CMPCR; /*!< SYSCFG Compensation cell control register, Address offset: 0x20 */
+} SYSCFG_TypeDef;
+
+/**
+ * @brief Inter-integrated Circuit Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */
+ __IO uint32_t OAR1; /*!< I2C Own address register 1, Address offset: 0x08 */
+ __IO uint32_t OAR2; /*!< I2C Own address register 2, Address offset: 0x0C */
+ __IO uint32_t DR; /*!< I2C Data register, Address offset: 0x10 */
+ __IO uint32_t SR1; /*!< I2C Status register 1, Address offset: 0x14 */
+ __IO uint32_t SR2; /*!< I2C Status register 2, Address offset: 0x18 */
+ __IO uint32_t CCR; /*!< I2C Clock control register, Address offset: 0x1C */
+ __IO uint32_t TRISE; /*!< I2C TRISE register, Address offset: 0x20 */
+ __IO uint32_t FLTR; /*!< I2C FLTR register, Address offset: 0x24 */
+} I2C_TypeDef;
+
+/**
+ * @brief Independent WATCHDOG
+ */
+
+typedef struct
+{
+ __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */
+ __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */
+ __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */
+ __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */
+} IWDG_TypeDef;
+
+/**
+ * @brief LCD-TFT Display Controller
+ */
+
+typedef struct
+{
+ uint32_t RESERVED0[2]; /*!< Reserved, 0x00-0x04 */
+ __IO uint32_t SSCR; /*!< LTDC Synchronization Size Configuration Register, Address offset: 0x08 */
+ __IO uint32_t BPCR; /*!< LTDC Back Porch Configuration Register, Address offset: 0x0C */
+ __IO uint32_t AWCR; /*!< LTDC Active Width Configuration Register, Address offset: 0x10 */
+ __IO uint32_t TWCR; /*!< LTDC Total Width Configuration Register, Address offset: 0x14 */
+ __IO uint32_t GCR; /*!< LTDC Global Control Register, Address offset: 0x18 */
+ uint32_t RESERVED1[2]; /*!< Reserved, 0x1C-0x20 */
+ __IO uint32_t SRCR; /*!< LTDC Shadow Reload Configuration Register, Address offset: 0x24 */
+ uint32_t RESERVED2[1]; /*!< Reserved, 0x28 */
+ __IO uint32_t BCCR; /*!< LTDC Background Color Configuration Register, Address offset: 0x2C */
+ uint32_t RESERVED3[1]; /*!< Reserved, 0x30 */
+ __IO uint32_t IER; /*!< LTDC Interrupt Enable Register, Address offset: 0x34 */
+ __IO uint32_t ISR; /*!< LTDC Interrupt Status Register, Address offset: 0x38 */
+ __IO uint32_t ICR; /*!< LTDC Interrupt Clear Register, Address offset: 0x3C */
+ __IO uint32_t LIPCR; /*!< LTDC Line Interrupt Position Configuration Register, Address offset: 0x40 */
+ __IO uint32_t CPSR; /*!< LTDC Current Position Status Register, Address offset: 0x44 */
+ __IO uint32_t CDSR; /*!< LTDC Current Display Status Register, Address offset: 0x48 */
+} LTDC_TypeDef;
+
+/**
+ * @brief LCD-TFT Display layer x Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< LTDC Layerx Control Register Address offset: 0x84 */
+ __IO uint32_t WHPCR; /*!< LTDC Layerx Window Horizontal Position Configuration Register Address offset: 0x88 */
+ __IO uint32_t WVPCR; /*!< LTDC Layerx Window Vertical Position Configuration Register Address offset: 0x8C */
+ __IO uint32_t CKCR; /*!< LTDC Layerx Color Keying Configuration Register Address offset: 0x90 */
+ __IO uint32_t PFCR; /*!< LTDC Layerx Pixel Format Configuration Register Address offset: 0x94 */
+ __IO uint32_t CACR; /*!< LTDC Layerx Constant Alpha Configuration Register Address offset: 0x98 */
+ __IO uint32_t DCCR; /*!< LTDC Layerx Default Color Configuration Register Address offset: 0x9C */
+ __IO uint32_t BFCR; /*!< LTDC Layerx Blending Factors Configuration Register Address offset: 0xA0 */
+ uint32_t RESERVED0[2]; /*!< Reserved */
+ __IO uint32_t CFBAR; /*!< LTDC Layerx Color Frame Buffer Address Register Address offset: 0xAC */
+ __IO uint32_t CFBLR; /*!< LTDC Layerx Color Frame Buffer Length Register Address offset: 0xB0 */
+ __IO uint32_t CFBLNR; /*!< LTDC Layerx ColorFrame Buffer Line Number Register Address offset: 0xB4 */
+ uint32_t RESERVED1[3]; /*!< Reserved */
+ __IO uint32_t CLUTWR; /*!< LTDC Layerx CLUT Write Register Address offset: 0x144 */
+
+} LTDC_Layer_TypeDef;
+
+/**
+ * @brief Power Control
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */
+ __IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */
+} PWR_TypeDef;
+
+/**
+ * @brief Reset and Clock Control
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */
+ __IO uint32_t PLLCFGR; /*!< RCC PLL configuration register, Address offset: 0x04 */
+ __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x08 */
+ __IO uint32_t CIR; /*!< RCC clock interrupt register, Address offset: 0x0C */
+ __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x10 */
+ __IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x14 */
+ __IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0x18 */
+ uint32_t RESERVED0; /*!< Reserved, 0x1C */
+ __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x20 */
+ __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x24 */
+ uint32_t RESERVED1[2]; /*!< Reserved, 0x28-0x2C */
+ __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clock register, Address offset: 0x30 */
+ __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clock register, Address offset: 0x34 */
+ __IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clock register, Address offset: 0x38 */
+ uint32_t RESERVED2; /*!< Reserved, 0x3C */
+ __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x40 */
+ __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x44 */
+ uint32_t RESERVED3[2]; /*!< Reserved, 0x48-0x4C */
+ __IO uint32_t AHB1LPENR; /*!< RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 */
+ __IO uint32_t AHB2LPENR; /*!< RCC AHB2 peripheral clock enable in low power mode register, Address offset: 0x54 */
+ __IO uint32_t AHB3LPENR; /*!< RCC AHB3 peripheral clock enable in low power mode register, Address offset: 0x58 */
+ uint32_t RESERVED4; /*!< Reserved, 0x5C */
+ __IO uint32_t APB1LPENR; /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 */
+ __IO uint32_t APB2LPENR; /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 */
+ uint32_t RESERVED5[2]; /*!< Reserved, 0x68-0x6C */
+ __IO uint32_t BDCR; /*!< RCC Backup domain control register, Address offset: 0x70 */
+ __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x74 */
+ uint32_t RESERVED6[2]; /*!< Reserved, 0x78-0x7C */
+ __IO uint32_t SSCGR; /*!< RCC spread spectrum clock generation register, Address offset: 0x80 */
+ __IO uint32_t PLLI2SCFGR; /*!< RCC PLLI2S configuration register, Address offset: 0x84 */
+ __IO uint32_t PLLSAICFGR; /*!< RCC PLLSAI configuration register, Address offset: 0x88 */
+ __IO uint32_t DCKCFGR; /*!< RCC Dedicated Clocks configuration register, Address offset: 0x8C */
+
+} RCC_TypeDef;
+
+/**
+ * @brief Real-Time Clock
+ */
+
+typedef struct
+{
+ __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
+ __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */
+ __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */
+ __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */
+ __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */
+ __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */
+ __IO uint32_t CALIBR; /*!< RTC calibration register, Address offset: 0x18 */
+ __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */
+ __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */
+ __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */
+ __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */
+ __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */
+ __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */
+ __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */
+ __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */
+ __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */
+ __IO uint32_t TAFCR; /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */
+ __IO uint32_t ALRMASSR;/*!< RTC alarm A sub second register, Address offset: 0x44 */
+ __IO uint32_t ALRMBSSR;/*!< RTC alarm B sub second register, Address offset: 0x48 */
+ uint32_t RESERVED7; /*!< Reserved, 0x4C */
+ __IO uint32_t BKP0R; /*!< RTC backup register 1, Address offset: 0x50 */
+ __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */
+ __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */
+ __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */
+ __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */
+ __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */
+ __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */
+ __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */
+ __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */
+ __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */
+ __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */
+ __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */
+ __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */
+ __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */
+ __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */
+ __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */
+ __IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */
+ __IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */
+ __IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */
+ __IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */
+} RTC_TypeDef;
+
+/**
+ * @brief Serial Audio Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t GCR; /*!< SAI global configuration register, Address offset: 0x00 */
+} SAI_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t CR1; /*!< SAI block x configuration register 1, Address offset: 0x04 */
+ __IO uint32_t CR2; /*!< SAI block x configuration register 2, Address offset: 0x08 */
+ __IO uint32_t FRCR; /*!< SAI block x frame configuration register, Address offset: 0x0C */
+ __IO uint32_t SLOTR; /*!< SAI block x slot register, Address offset: 0x10 */
+ __IO uint32_t IMR; /*!< SAI block x interrupt mask register, Address offset: 0x14 */
+ __IO uint32_t SR; /*!< SAI block x status register, Address offset: 0x18 */
+ __IO uint32_t CLRFR; /*!< SAI block x clear flag register, Address offset: 0x1C */
+ __IO uint32_t DR; /*!< SAI block x data register, Address offset: 0x20 */
+} SAI_Block_TypeDef;
+
+/**
+ * @brief SD host Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t POWER; /*!< SDIO power control register, Address offset: 0x00 */
+ __IO uint32_t CLKCR; /*!< SDI clock control register, Address offset: 0x04 */
+ __IO uint32_t ARG; /*!< SDIO argument register, Address offset: 0x08 */
+ __IO uint32_t CMD; /*!< SDIO command register, Address offset: 0x0C */
+ __I uint32_t RESPCMD; /*!< SDIO command response register, Address offset: 0x10 */
+ __I uint32_t RESP1; /*!< SDIO response 1 register, Address offset: 0x14 */
+ __I uint32_t RESP2; /*!< SDIO response 2 register, Address offset: 0x18 */
+ __I uint32_t RESP3; /*!< SDIO response 3 register, Address offset: 0x1C */
+ __I uint32_t RESP4; /*!< SDIO response 4 register, Address offset: 0x20 */
+ __IO uint32_t DTIMER; /*!< SDIO data timer register, Address offset: 0x24 */
+ __IO uint32_t DLEN; /*!< SDIO data length register, Address offset: 0x28 */
+ __IO uint32_t DCTRL; /*!< SDIO data control register, Address offset: 0x2C */
+ __I uint32_t DCOUNT; /*!< SDIO data counter register, Address offset: 0x30 */
+ __I uint32_t STA; /*!< SDIO status register, Address offset: 0x34 */
+ __IO uint32_t ICR; /*!< SDIO interrupt clear register, Address offset: 0x38 */
+ __IO uint32_t MASK; /*!< SDIO mask register, Address offset: 0x3C */
+ uint32_t RESERVED0[2]; /*!< Reserved, 0x40-0x44 */
+ __I uint32_t FIFOCNT; /*!< SDIO FIFO counter register, Address offset: 0x48 */
+ uint32_t RESERVED1[13]; /*!< Reserved, 0x4C-0x7C */
+ __IO uint32_t FIFO; /*!< SDIO data FIFO register, Address offset: 0x80 */
+} SDIO_TypeDef;
+
+/**
+ * @brief Serial Peripheral Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t CR1; /*!< SPI control register 1 (not used in I2S mode), Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< SPI control register 2, Address offset: 0x04 */
+ __IO uint32_t SR; /*!< SPI status register, Address offset: 0x08 */
+ __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */
+ __IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
+ __IO uint32_t RXCRCR; /*!< SPI RX CRC register (not used in I2S mode), Address offset: 0x14 */
+ __IO uint32_t TXCRCR; /*!< SPI TX CRC register (not used in I2S mode), Address offset: 0x18 */
+ __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */
+ __IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */
+} SPI_TypeDef;
+
+/**
+ * @brief QUAD Serial Peripheral Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< QUADSPI Control register, Address offset: 0x00 */
+ __IO uint32_t DCR; /*!< QUADSPI Device Configuration register, Address offset: 0x04 */
+ __IO uint32_t SR; /*!< QUADSPI Status register, Address offset: 0x08 */
+ __IO uint32_t FCR; /*!< QUADSPI Flag Clear register, Address offset: 0x0C */
+ __IO uint32_t DLR; /*!< QUADSPI Data Length register, Address offset: 0x10 */
+ __IO uint32_t CCR; /*!< QUADSPI Communication Configuration register, Address offset: 0x14 */
+ __IO uint32_t AR; /*!< QUADSPI Address register, Address offset: 0x18 */
+ __IO uint32_t ABR; /*!< QUADSPI Alternate Bytes register, Address offset: 0x1C */
+ __IO uint32_t DR; /*!< QUADSPI Data register, Address offset: 0x20 */
+ __IO uint32_t PSMKR; /*!< QUADSPI Polling Status Mask register, Address offset: 0x24 */
+ __IO uint32_t PSMAR; /*!< QUADSPI Polling Status Match register, Address offset: 0x28 */
+ __IO uint32_t PIR; /*!< QUADSPI Polling Interval register, Address offset: 0x2C */
+ __IO uint32_t LPTR; /*!< QUADSPI Low Power Timeout register, Address offset: 0x30 */
+} QUADSPI_TypeDef;
+
+/**
+ * @brief TIM
+ */
+
+typedef struct
+{
+ __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
+ __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */
+ __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
+ __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
+ __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
+ __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
+ __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
+ __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
+ __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
+ __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */
+ __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
+ __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */
+ __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
+ __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
+ __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
+ __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
+ __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
+ __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
+ __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */
+ __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */
+} TIM_TypeDef;
+
+/**
+ * @brief Universal Synchronous Asynchronous Receiver Transmitter
+ */
+
+typedef struct
+{
+ __IO uint32_t SR; /*!< USART Status register, Address offset: 0x00 */
+ __IO uint32_t DR; /*!< USART Data register, Address offset: 0x04 */
+ __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x08 */
+ __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x0C */
+ __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x10 */
+ __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x14 */
+ __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x18 */
+} USART_TypeDef;
+
+/**
+ * @brief Window WATCHDOG
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
+ __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
+ __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
+} WWDG_TypeDef;
+
+/**
+ * @brief Crypto Processor
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< CRYP control register, Address offset: 0x00 */
+ __IO uint32_t SR; /*!< CRYP status register, Address offset: 0x04 */
+ __IO uint32_t DR; /*!< CRYP data input register, Address offset: 0x08 */
+ __IO uint32_t DOUT; /*!< CRYP data output register, Address offset: 0x0C */
+ __IO uint32_t DMACR; /*!< CRYP DMA control register, Address offset: 0x10 */
+ __IO uint32_t IMSCR; /*!< CRYP interrupt mask set/clear register, Address offset: 0x14 */
+ __IO uint32_t RISR; /*!< CRYP raw interrupt status register, Address offset: 0x18 */
+ __IO uint32_t MISR; /*!< CRYP masked interrupt status register, Address offset: 0x1C */
+ __IO uint32_t K0LR; /*!< CRYP key left register 0, Address offset: 0x20 */
+ __IO uint32_t K0RR; /*!< CRYP key right register 0, Address offset: 0x24 */
+ __IO uint32_t K1LR; /*!< CRYP key left register 1, Address offset: 0x28 */
+ __IO uint32_t K1RR; /*!< CRYP key right register 1, Address offset: 0x2C */
+ __IO uint32_t K2LR; /*!< CRYP key left register 2, Address offset: 0x30 */
+ __IO uint32_t K2RR; /*!< CRYP key right register 2, Address offset: 0x34 */
+ __IO uint32_t K3LR; /*!< CRYP key left register 3, Address offset: 0x38 */
+ __IO uint32_t K3RR; /*!< CRYP key right register 3, Address offset: 0x3C */
+ __IO uint32_t IV0LR; /*!< CRYP initialization vector left-word register 0, Address offset: 0x40 */
+ __IO uint32_t IV0RR; /*!< CRYP initialization vector right-word register 0, Address offset: 0x44 */
+ __IO uint32_t IV1LR; /*!< CRYP initialization vector left-word register 1, Address offset: 0x48 */
+ __IO uint32_t IV1RR; /*!< CRYP initialization vector right-word register 1, Address offset: 0x4C */
+ __IO uint32_t CSGCMCCM0R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 0, Address offset: 0x50 */
+ __IO uint32_t CSGCMCCM1R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 1, Address offset: 0x54 */
+ __IO uint32_t CSGCMCCM2R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 2, Address offset: 0x58 */
+ __IO uint32_t CSGCMCCM3R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 3, Address offset: 0x5C */
+ __IO uint32_t CSGCMCCM4R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 4, Address offset: 0x60 */
+ __IO uint32_t CSGCMCCM5R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 5, Address offset: 0x64 */
+ __IO uint32_t CSGCMCCM6R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 6, Address offset: 0x68 */
+ __IO uint32_t CSGCMCCM7R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 7, Address offset: 0x6C */
+ __IO uint32_t CSGCM0R; /*!< CRYP GCM/GMAC context swap register 0, Address offset: 0x70 */
+ __IO uint32_t CSGCM1R; /*!< CRYP GCM/GMAC context swap register 1, Address offset: 0x74 */
+ __IO uint32_t CSGCM2R; /*!< CRYP GCM/GMAC context swap register 2, Address offset: 0x78 */
+ __IO uint32_t CSGCM3R; /*!< CRYP GCM/GMAC context swap register 3, Address offset: 0x7C */
+ __IO uint32_t CSGCM4R; /*!< CRYP GCM/GMAC context swap register 4, Address offset: 0x80 */
+ __IO uint32_t CSGCM5R; /*!< CRYP GCM/GMAC context swap register 5, Address offset: 0x84 */
+ __IO uint32_t CSGCM6R; /*!< CRYP GCM/GMAC context swap register 6, Address offset: 0x88 */
+ __IO uint32_t CSGCM7R; /*!< CRYP GCM/GMAC context swap register 7, Address offset: 0x8C */
+} CRYP_TypeDef;
+
+/**
+ * @brief HASH
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< HASH control register, Address offset: 0x00 */
+ __IO uint32_t DIN; /*!< HASH data input register, Address offset: 0x04 */
+ __IO uint32_t STR; /*!< HASH start register, Address offset: 0x08 */
+ __IO uint32_t HR[5]; /*!< HASH digest registers, Address offset: 0x0C-0x1C */
+ __IO uint32_t IMR; /*!< HASH interrupt enable register, Address offset: 0x20 */
+ __IO uint32_t SR; /*!< HASH status register, Address offset: 0x24 */
+ uint32_t RESERVED[52]; /*!< Reserved, 0x28-0xF4 */
+ __IO uint32_t CSR[54]; /*!< HASH context swap registers, Address offset: 0x0F8-0x1CC */
+} HASH_TypeDef;
+
+/**
+ * @brief HASH_DIGEST
+ */
+
+typedef struct
+{
+ __IO uint32_t HR[8]; /*!< HASH digest registers, Address offset: 0x310-0x32C */
+} HASH_DIGEST_TypeDef;
+
+/**
+ * @brief RNG
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */
+ __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */
+ __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */
+} RNG_TypeDef;
+
+
+/**
+ * @brief USB_OTG_Core_Registers
+ */
+typedef struct
+{
+ __IO uint32_t GOTGCTL; /*!< USB_OTG Control and Status Register 000h */
+ __IO uint32_t GOTGINT; /*!< USB_OTG Interrupt Register 004h */
+ __IO uint32_t GAHBCFG; /*!< Core AHB Configuration Register 008h */
+ __IO uint32_t GUSBCFG; /*!< Core USB Configuration Register 00Ch */
+ __IO uint32_t GRSTCTL; /*!< Core Reset Register 010h */
+ __IO uint32_t GINTSTS; /*!< Core Interrupt Register 014h */
+ __IO uint32_t GINTMSK; /*!< Core Interrupt Mask Register 018h */
+ __IO uint32_t GRXSTSR; /*!< Receive Sts Q Read Register 01Ch */
+ __IO uint32_t GRXSTSP; /*!< Receive Sts Q Read & POP Register 020h */
+ __IO uint32_t GRXFSIZ; /*!< Receive FIFO Size Register 024h */
+ __IO uint32_t DIEPTXF0_HNPTXFSIZ; /*!< EP0 / Non Periodic Tx FIFO Size Register 028h */
+ __IO uint32_t HNPTXSTS; /*!< Non Periodic Tx FIFO/Queue Sts reg 02Ch */
+ uint32_t Reserved30[2]; /*!< Reserved 030h */
+ __IO uint32_t GCCFG; /*!< General Purpose IO Register 038h */
+ __IO uint32_t CID; /*!< User ID Register 03Ch */
+ uint32_t Reserved5[3]; /*!< Reserved 040h-048h */
+ __IO uint32_t GHWCFG3; /*!< User HW config3 04Ch */
+ uint32_t Reserved6; /*!< Reserved 050h */
+ __IO uint32_t GLPMCFG; /*!< LPM Register 054h */
+ uint32_t Reserved; /*!< Reserved 058h */
+ __IO uint32_t GDFIFOCFG; /*!< DFIFO Software Config Register 05Ch */
+ uint32_t Reserved43[40]; /*!< Reserved 058h-0FFh */
+ __IO uint32_t HPTXFSIZ; /*!< Host Periodic Tx FIFO Size Reg 100h */
+ __IO uint32_t DIEPTXF[0x0F]; /*!< dev Periodic Transmit FIFO */
+} USB_OTG_GlobalTypeDef;
+
+/**
+ * @brief USB_OTG_device_Registers
+ */
+typedef struct
+{
+ __IO uint32_t DCFG; /*!< dev Configuration Register 800h */
+ __IO uint32_t DCTL; /*!< dev Control Register 804h */
+ __IO uint32_t DSTS; /*!< dev Status Register (RO) 808h */
+ uint32_t Reserved0C; /*!< Reserved 80Ch */
+ __IO uint32_t DIEPMSK; /*!< dev IN Endpoint Mask 810h */
+ __IO uint32_t DOEPMSK; /*!< dev OUT Endpoint Mask 814h */
+ __IO uint32_t DAINT; /*!< dev All Endpoints Itr Reg 818h */
+ __IO uint32_t DAINTMSK; /*!< dev All Endpoints Itr Mask 81Ch */
+ uint32_t Reserved20; /*!< Reserved 820h */
+ uint32_t Reserved9; /*!< Reserved 824h */
+ __IO uint32_t DVBUSDIS; /*!< dev VBUS discharge Register 828h */
+ __IO uint32_t DVBUSPULSE; /*!< dev VBUS Pulse Register 82Ch */
+ __IO uint32_t DTHRCTL; /*!< dev threshold 830h */
+ __IO uint32_t DIEPEMPMSK; /*!< dev empty msk 834h */
+ __IO uint32_t DEACHINT; /*!< dedicated EP interrupt 838h */
+ __IO uint32_t DEACHMSK; /*!< dedicated EP msk 83Ch */
+ uint32_t Reserved40; /*!< dedicated EP mask 840h */
+ __IO uint32_t DINEP1MSK; /*!< dedicated EP mask 844h */
+ uint32_t Reserved44[15]; /*!< Reserved 844-87Ch */
+ __IO uint32_t DOUTEP1MSK; /*!< dedicated EP msk 884h */
+} USB_OTG_DeviceTypeDef;
+
+/**
+ * @brief USB_OTG_IN_Endpoint-Specific_Register
+ */
+typedef struct
+{
+ __IO uint32_t DIEPCTL; /*!< dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h */
+ uint32_t Reserved04; /*!< Reserved 900h + (ep_num * 20h) + 04h */
+ __IO uint32_t DIEPINT; /*!< dev IN Endpoint Itr Reg 900h + (ep_num * 20h) + 08h */
+ uint32_t Reserved0C; /*!< Reserved 900h + (ep_num * 20h) + 0Ch */
+ __IO uint32_t DIEPTSIZ; /*!< IN Endpoint Txfer Size 900h + (ep_num * 20h) + 10h */
+ __IO uint32_t DIEPDMA; /*!< IN Endpoint DMA Address Reg 900h + (ep_num * 20h) + 14h */
+ __IO uint32_t DTXFSTS; /*!< IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h */
+ uint32_t Reserved18; /*!< Reserved 900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch */
+} USB_OTG_INEndpointTypeDef;
+
+/**
+ * @brief USB_OTG_OUT_Endpoint-Specific_Registers
+ */
+typedef struct
+{
+ __IO uint32_t DOEPCTL; /*!< dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h */
+ uint32_t Reserved04; /*!< Reserved B00h + (ep_num * 20h) + 04h */
+ __IO uint32_t DOEPINT; /*!< dev OUT Endpoint Itr Reg B00h + (ep_num * 20h) + 08h */
+ uint32_t Reserved0C; /*!< Reserved B00h + (ep_num * 20h) + 0Ch */
+ __IO uint32_t DOEPTSIZ; /*!< dev OUT Endpoint Txfer Size B00h + (ep_num * 20h) + 10h */
+ __IO uint32_t DOEPDMA; /*!< dev OUT Endpoint DMA Address B00h + (ep_num * 20h) + 14h */
+ uint32_t Reserved18[2]; /*!< Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch */
+} USB_OTG_OUTEndpointTypeDef;
+
+/**
+ * @brief USB_OTG_Host_Mode_Register_Structures
+ */
+typedef struct
+{
+ __IO uint32_t HCFG; /*!< Host Configuration Register 400h */
+ __IO uint32_t HFIR; /*!< Host Frame Interval Register 404h */
+ __IO uint32_t HFNUM; /*!< Host Frame Nbr/Frame Remaining 408h */
+ uint32_t Reserved40C; /*!< Reserved 40Ch */
+ __IO uint32_t HPTXSTS; /*!< Host Periodic Tx FIFO/ Queue Status 410h */
+ __IO uint32_t HAINT; /*!< Host All Channels Interrupt Register 414h */
+ __IO uint32_t HAINTMSK; /*!< Host All Channels Interrupt Mask 418h */
+} USB_OTG_HostTypeDef;
+
+/**
+ * @brief USB_OTG_Host_Channel_Specific_Registers
+ */
+typedef struct
+{
+ __IO uint32_t HCCHAR; /*!< Host Channel Characteristics Register 500h */
+ __IO uint32_t HCSPLT; /*!< Host Channel Split Control Register 504h */
+ __IO uint32_t HCINT; /*!< Host Channel Interrupt Register 508h */
+ __IO uint32_t HCINTMSK; /*!< Host Channel Interrupt Mask Register 50Ch */
+ __IO uint32_t HCTSIZ; /*!< Host Channel Transfer Size Register 510h */
+ __IO uint32_t HCDMA; /*!< Host Channel DMA Address Register 514h */
+ uint32_t Reserved[2]; /*!< Reserved */
+} USB_OTG_HostChannelTypeDef;
+
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_memory_map
+ * @{
+ */
+#define FLASH_BASE 0x08000000U /*!< FLASH(up to 1 MB) base address in the alias region */
+#define CCMDATARAM_BASE 0x10000000U /*!< CCM(core coupled memory) data RAM(64 KB) base address in the alias region */
+#define SRAM1_BASE 0x20000000U /*!< SRAM1(160 KB) base address in the alias region */
+#define SRAM2_BASE 0x20028000U /*!< SRAM2(32 KB) base address in the alias region */
+#define SRAM3_BASE 0x20030000U /*!< SRAM3(128 KB) base address in the alias region */
+#define PERIPH_BASE 0x40000000U /*!< Peripheral base address in the alias region */
+#define BKPSRAM_BASE 0x40024000U /*!< Backup SRAM(4 KB) base address in the alias region */
+#define FMC_R_BASE 0xA0000000U /*!< FMC registers base address */
+#define QSPI_R_BASE 0xA0001000U /*!< QuadSPI registers base address */
+#define SRAM1_BB_BASE 0x22000000U /*!< SRAM1(112 KB) base address in the bit-band region */
+#define SRAM2_BB_BASE 0x22500000U /*!< SRAM2(16 KB) base address in the bit-band region */
+#define SRAM3_BB_BASE 0x22600000U /*!< SRAM3(64 KB) base address in the bit-band region */
+#define PERIPH_BB_BASE 0x42000000U /*!< Peripheral base address in the bit-band region */
+#define BKPSRAM_BB_BASE 0x42480000U /*!< Backup SRAM(4 KB) base address in the bit-band region */
+#define FLASH_END 0x081FFFFFU /*!< FLASH end address */
+#define CCMDATARAM_END 0x1000FFFFU /*!< CCM data RAM end address */
+
+/* Legacy defines */
+#define SRAM_BASE SRAM1_BASE
+#define SRAM_BB_BASE SRAM1_BB_BASE
+
+
+/*!< Peripheral memory map */
+#define APB1PERIPH_BASE PERIPH_BASE
+#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000U)
+#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000U)
+#define AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000U)
+
+/*!< APB1 peripherals */
+#define TIM2_BASE (APB1PERIPH_BASE + 0x0000U)
+#define TIM3_BASE (APB1PERIPH_BASE + 0x0400U)
+#define TIM4_BASE (APB1PERIPH_BASE + 0x0800U)
+#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00U)
+#define TIM6_BASE (APB1PERIPH_BASE + 0x1000U)
+#define TIM7_BASE (APB1PERIPH_BASE + 0x1400U)
+#define TIM12_BASE (APB1PERIPH_BASE + 0x1800U)
+#define TIM13_BASE (APB1PERIPH_BASE + 0x1C00U)
+#define TIM14_BASE (APB1PERIPH_BASE + 0x2000U)
+#define RTC_BASE (APB1PERIPH_BASE + 0x2800U)
+#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00U)
+#define IWDG_BASE (APB1PERIPH_BASE + 0x3000U)
+#define I2S2ext_BASE (APB1PERIPH_BASE + 0x3400U)
+#define SPI2_BASE (APB1PERIPH_BASE + 0x3800U)
+#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00U)
+#define I2S3ext_BASE (APB1PERIPH_BASE + 0x4000U)
+#define USART2_BASE (APB1PERIPH_BASE + 0x4400U)
+#define USART3_BASE (APB1PERIPH_BASE + 0x4800U)
+#define UART4_BASE (APB1PERIPH_BASE + 0x4C00U)
+#define UART5_BASE (APB1PERIPH_BASE + 0x5000U)
+#define I2C1_BASE (APB1PERIPH_BASE + 0x5400U)
+#define I2C2_BASE (APB1PERIPH_BASE + 0x5800U)
+#define I2C3_BASE (APB1PERIPH_BASE + 0x5C00U)
+#define CAN1_BASE (APB1PERIPH_BASE + 0x6400U)
+#define CAN2_BASE (APB1PERIPH_BASE + 0x6800U)
+#define PWR_BASE (APB1PERIPH_BASE + 0x7000U)
+#define DAC_BASE (APB1PERIPH_BASE + 0x7400U)
+#define UART7_BASE (APB1PERIPH_BASE + 0x7800U)
+#define UART8_BASE (APB1PERIPH_BASE + 0x7C00U)
+
+/*!< APB2 peripherals */
+#define TIM1_BASE (APB2PERIPH_BASE + 0x0000U)
+#define TIM8_BASE (APB2PERIPH_BASE + 0x0400U)
+#define USART1_BASE (APB2PERIPH_BASE + 0x1000U)
+#define USART6_BASE (APB2PERIPH_BASE + 0x1400U)
+#define ADC1_BASE (APB2PERIPH_BASE + 0x2000U)
+#define ADC2_BASE (APB2PERIPH_BASE + 0x2100U)
+#define ADC3_BASE (APB2PERIPH_BASE + 0x2200U)
+#define ADC_BASE (APB2PERIPH_BASE + 0x2300U)
+#define SDIO_BASE (APB2PERIPH_BASE + 0x2C00U)
+#define SPI1_BASE (APB2PERIPH_BASE + 0x3000U)
+#define SPI4_BASE (APB2PERIPH_BASE + 0x3400U)
+#define SYSCFG_BASE (APB2PERIPH_BASE + 0x3800U)
+#define EXTI_BASE (APB2PERIPH_BASE + 0x3C00U)
+#define TIM9_BASE (APB2PERIPH_BASE + 0x4000U)
+#define TIM10_BASE (APB2PERIPH_BASE + 0x4400U)
+#define TIM11_BASE (APB2PERIPH_BASE + 0x4800U)
+#define SPI5_BASE (APB2PERIPH_BASE + 0x5000U)
+#define SPI6_BASE (APB2PERIPH_BASE + 0x5400U)
+#define SAI1_BASE (APB2PERIPH_BASE + 0x5800U)
+#define SAI1_Block_A_BASE (SAI1_BASE + 0x004U)
+#define SAI1_Block_B_BASE (SAI1_BASE + 0x024U)
+#define LTDC_BASE (APB2PERIPH_BASE + 0x6800U)
+#define LTDC_Layer1_BASE (LTDC_BASE + 0x84U)
+#define LTDC_Layer2_BASE (LTDC_BASE + 0x104U)
+#define DSI_BASE (APB2PERIPH_BASE + 0x6C00U)
+
+/*!< AHB1 peripherals */
+#define GPIOA_BASE (AHB1PERIPH_BASE + 0x0000U)
+#define GPIOB_BASE (AHB1PERIPH_BASE + 0x0400U)
+#define GPIOC_BASE (AHB1PERIPH_BASE + 0x0800U)
+#define GPIOD_BASE (AHB1PERIPH_BASE + 0x0C00U)
+#define GPIOE_BASE (AHB1PERIPH_BASE + 0x1000U)
+#define GPIOF_BASE (AHB1PERIPH_BASE + 0x1400U)
+#define GPIOG_BASE (AHB1PERIPH_BASE + 0x1800U)
+#define GPIOH_BASE (AHB1PERIPH_BASE + 0x1C00U)
+#define GPIOI_BASE (AHB1PERIPH_BASE + 0x2000U)
+#define GPIOJ_BASE (AHB1PERIPH_BASE + 0x2400U)
+#define GPIOK_BASE (AHB1PERIPH_BASE + 0x2800U)
+#define CRC_BASE (AHB1PERIPH_BASE + 0x3000U)
+#define RCC_BASE (AHB1PERIPH_BASE + 0x3800U)
+#define FLASH_R_BASE (AHB1PERIPH_BASE + 0x3C00U)
+#define DMA1_BASE (AHB1PERIPH_BASE + 0x6000U)
+#define DMA1_Stream0_BASE (DMA1_BASE + 0x010U)
+#define DMA1_Stream1_BASE (DMA1_BASE + 0x028U)
+#define DMA1_Stream2_BASE (DMA1_BASE + 0x040U)
+#define DMA1_Stream3_BASE (DMA1_BASE + 0x058U)
+#define DMA1_Stream4_BASE (DMA1_BASE + 0x070U)
+#define DMA1_Stream5_BASE (DMA1_BASE + 0x088U)
+#define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0U)
+#define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8U)
+#define DMA2_BASE (AHB1PERIPH_BASE + 0x6400U)
+#define DMA2_Stream0_BASE (DMA2_BASE + 0x010U)
+#define DMA2_Stream1_BASE (DMA2_BASE + 0x028U)
+#define DMA2_Stream2_BASE (DMA2_BASE + 0x040U)
+#define DMA2_Stream3_BASE (DMA2_BASE + 0x058U)
+#define DMA2_Stream4_BASE (DMA2_BASE + 0x070U)
+#define DMA2_Stream5_BASE (DMA2_BASE + 0x088U)
+#define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0U)
+#define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8U)
+#define ETH_BASE (AHB1PERIPH_BASE + 0x8000U)
+#define ETH_MAC_BASE (ETH_BASE)
+#define ETH_MMC_BASE (ETH_BASE + 0x0100U)
+#define ETH_PTP_BASE (ETH_BASE + 0x0700U)
+#define ETH_DMA_BASE (ETH_BASE + 0x1000U)
+#define DMA2D_BASE (AHB1PERIPH_BASE + 0xB000U)
+
+/*!< AHB2 peripherals */
+#define DCMI_BASE (AHB2PERIPH_BASE + 0x50000U)
+#define CRYP_BASE (AHB2PERIPH_BASE + 0x60000U)
+#define HASH_BASE (AHB2PERIPH_BASE + 0x60400U)
+#define HASH_DIGEST_BASE (AHB2PERIPH_BASE + 0x60710U)
+#define RNG_BASE (AHB2PERIPH_BASE + 0x60800U)
+
+/*!< FMC Bankx registers base address */
+#define FMC_Bank1_R_BASE (FMC_R_BASE + 0x0000U)
+#define FMC_Bank1E_R_BASE (FMC_R_BASE + 0x0104U)
+#define FMC_Bank3_R_BASE (FMC_R_BASE + 0x0080U)
+#define FMC_Bank5_6_R_BASE (FMC_R_BASE + 0x0140U)
+
+/*!< Debug MCU registers base address */
+#define DBGMCU_BASE 0xE0042000U
+
+/*!< USB registers base address */
+#define USB_OTG_HS_PERIPH_BASE 0x40040000U
+#define USB_OTG_FS_PERIPH_BASE 0x50000000U
+
+#define USB_OTG_GLOBAL_BASE 0x000U
+#define USB_OTG_DEVICE_BASE 0x800U
+#define USB_OTG_IN_ENDPOINT_BASE 0x900U
+#define USB_OTG_OUT_ENDPOINT_BASE 0xB00U
+#define USB_OTG_EP_REG_SIZE 0x20U
+#define USB_OTG_HOST_BASE 0x400U
+#define USB_OTG_HOST_PORT_BASE 0x440U
+#define USB_OTG_HOST_CHANNEL_BASE 0x500U
+#define USB_OTG_HOST_CHANNEL_SIZE 0x20U
+#define USB_OTG_PCGCCTL_BASE 0xE00U
+#define USB_OTG_FIFO_BASE 0x1000U
+#define USB_OTG_FIFO_SIZE 0x1000U
+
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_declaration
+ * @{
+ */
+#define TIM2 ((TIM_TypeDef *) TIM2_BASE)
+#define TIM3 ((TIM_TypeDef *) TIM3_BASE)
+#define TIM4 ((TIM_TypeDef *) TIM4_BASE)
+#define TIM5 ((TIM_TypeDef *) TIM5_BASE)
+#define TIM6 ((TIM_TypeDef *) TIM6_BASE)
+#define TIM7 ((TIM_TypeDef *) TIM7_BASE)
+#define TIM12 ((TIM_TypeDef *) TIM12_BASE)
+#define TIM13 ((TIM_TypeDef *) TIM13_BASE)
+#define TIM14 ((TIM_TypeDef *) TIM14_BASE)
+#define RTC ((RTC_TypeDef *) RTC_BASE)
+#define WWDG ((WWDG_TypeDef *) WWDG_BASE)
+#define IWDG ((IWDG_TypeDef *) IWDG_BASE)
+#define I2S2ext ((SPI_TypeDef *) I2S2ext_BASE)
+#define SPI2 ((SPI_TypeDef *) SPI2_BASE)
+#define SPI3 ((SPI_TypeDef *) SPI3_BASE)
+#define I2S3ext ((SPI_TypeDef *) I2S3ext_BASE)
+#define USART2 ((USART_TypeDef *) USART2_BASE)
+#define USART3 ((USART_TypeDef *) USART3_BASE)
+#define UART4 ((USART_TypeDef *) UART4_BASE)
+#define UART5 ((USART_TypeDef *) UART5_BASE)
+#define I2C1 ((I2C_TypeDef *) I2C1_BASE)
+#define I2C2 ((I2C_TypeDef *) I2C2_BASE)
+#define I2C3 ((I2C_TypeDef *) I2C3_BASE)
+#define CAN1 ((CAN_TypeDef *) CAN1_BASE)
+#define CAN2 ((CAN_TypeDef *) CAN2_BASE)
+#define PWR ((PWR_TypeDef *) PWR_BASE)
+#define DAC ((DAC_TypeDef *) DAC_BASE)
+#define UART7 ((USART_TypeDef *) UART7_BASE)
+#define UART8 ((USART_TypeDef *) UART8_BASE)
+#define TIM1 ((TIM_TypeDef *) TIM1_BASE)
+#define TIM8 ((TIM_TypeDef *) TIM8_BASE)
+#define USART1 ((USART_TypeDef *) USART1_BASE)
+#define USART6 ((USART_TypeDef *) USART6_BASE)
+#define ADC ((ADC_Common_TypeDef *) ADC_BASE)
+#define ADC1 ((ADC_TypeDef *) ADC1_BASE)
+#define ADC2 ((ADC_TypeDef *) ADC2_BASE)
+#define ADC3 ((ADC_TypeDef *) ADC3_BASE)
+#define SDIO ((SDIO_TypeDef *) SDIO_BASE)
+#define SPI1 ((SPI_TypeDef *) SPI1_BASE)
+#define SPI4 ((SPI_TypeDef *) SPI4_BASE)
+#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
+#define EXTI ((EXTI_TypeDef *) EXTI_BASE)
+#define TIM9 ((TIM_TypeDef *) TIM9_BASE)
+#define TIM10 ((TIM_TypeDef *) TIM10_BASE)
+#define TIM11 ((TIM_TypeDef *) TIM11_BASE)
+#define SPI5 ((SPI_TypeDef *) SPI5_BASE)
+#define SPI6 ((SPI_TypeDef *) SPI6_BASE)
+#define SAI1 ((SAI_TypeDef *) SAI1_BASE)
+#define SAI1_Block_A ((SAI_Block_TypeDef *)SAI1_Block_A_BASE)
+#define SAI1_Block_B ((SAI_Block_TypeDef *)SAI1_Block_B_BASE)
+#define LTDC ((LTDC_TypeDef *)LTDC_BASE)
+#define LTDC_Layer1 ((LTDC_Layer_TypeDef *)LTDC_Layer1_BASE)
+#define LTDC_Layer2 ((LTDC_Layer_TypeDef *)LTDC_Layer2_BASE)
+#define DSI ((DSI_TypeDef *)DSI_BASE)
+
+#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
+#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
+#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
+#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
+#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
+#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
+#define GPIOG ((GPIO_TypeDef *) GPIOG_BASE)
+#define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
+#define GPIOI ((GPIO_TypeDef *) GPIOI_BASE)
+#define GPIOJ ((GPIO_TypeDef *) GPIOJ_BASE)
+#define GPIOK ((GPIO_TypeDef *) GPIOK_BASE)
+#define CRC ((CRC_TypeDef *) CRC_BASE)
+#define RCC ((RCC_TypeDef *) RCC_BASE)
+#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
+#define DMA1 ((DMA_TypeDef *) DMA1_BASE)
+#define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)
+#define DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)
+#define DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)
+#define DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)
+#define DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)
+#define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)
+#define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)
+#define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)
+#define DMA2 ((DMA_TypeDef *) DMA2_BASE)
+#define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)
+#define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
+#define DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)
+#define DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)
+#define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)
+#define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)
+#define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)
+#define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)
+#define ETH ((ETH_TypeDef *) ETH_BASE)
+#define DMA2D ((DMA2D_TypeDef *)DMA2D_BASE)
+#define DCMI ((DCMI_TypeDef *) DCMI_BASE)
+#define CRYP ((CRYP_TypeDef *) CRYP_BASE)
+#define HASH ((HASH_TypeDef *) HASH_BASE)
+#define HASH_DIGEST ((HASH_DIGEST_TypeDef *) HASH_DIGEST_BASE)
+#define RNG ((RNG_TypeDef *) RNG_BASE)
+#define FMC_Bank1 ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE)
+#define FMC_Bank1E ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE)
+#define FMC_Bank3 ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE)
+#define FMC_Bank5_6 ((FMC_Bank5_6_TypeDef *) FMC_Bank5_6_R_BASE)
+#define QUADSPI ((QUADSPI_TypeDef *) QSPI_R_BASE)
+
+#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
+
+#define USB_OTG_FS ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE)
+#define USB_OTG_HS ((USB_OTG_GlobalTypeDef *) USB_OTG_HS_PERIPH_BASE)
+
+/**
+ * @}
+ */
+
+/** @addtogroup Exported_constants
+ * @{
+ */
+
+ /** @addtogroup Peripheral_Registers_Bits_Definition
+ * @{
+ */
+
+/******************************************************************************/
+/* Peripheral Registers_Bits_Definition */
+/******************************************************************************/
+
+/******************************************************************************/
+/* */
+/* Analog to Digital Converter */
+/* */
+/******************************************************************************/
+/******************** Bit definition for ADC_SR register ********************/
+#define ADC_SR_AWD 0x00000001U /*!<Analog watchdog flag */
+#define ADC_SR_EOC 0x00000002U /*!<End of conversion */
+#define ADC_SR_JEOC 0x00000004U /*!<Injected channel end of conversion */
+#define ADC_SR_JSTRT 0x00000008U /*!<Injected channel Start flag */
+#define ADC_SR_STRT 0x00000010U /*!<Regular channel Start flag */
+#define ADC_SR_OVR 0x00000020U /*!<Overrun flag */
+
+/******************* Bit definition for ADC_CR1 register ********************/
+#define ADC_CR1_AWDCH 0x0000001FU /*!<AWDCH[4:0] bits (Analog watchdog channel select bits) */
+#define ADC_CR1_AWDCH_0 0x00000001U /*!<Bit 0 */
+#define ADC_CR1_AWDCH_1 0x00000002U /*!<Bit 1 */
+#define ADC_CR1_AWDCH_2 0x00000004U /*!<Bit 2 */
+#define ADC_CR1_AWDCH_3 0x00000008U /*!<Bit 3 */
+#define ADC_CR1_AWDCH_4 0x00000010U /*!<Bit 4 */
+#define ADC_CR1_EOCIE 0x00000020U /*!<Interrupt enable for EOC */
+#define ADC_CR1_AWDIE 0x00000040U /*!<AAnalog Watchdog interrupt enable */
+#define ADC_CR1_JEOCIE 0x00000080U /*!<Interrupt enable for injected channels */
+#define ADC_CR1_SCAN 0x00000100U /*!<Scan mode */
+#define ADC_CR1_AWDSGL 0x00000200U /*!<Enable the watchdog on a single channel in scan mode */
+#define ADC_CR1_JAUTO 0x00000400U /*!<Automatic injected group conversion */
+#define ADC_CR1_DISCEN 0x00000800U /*!<Discontinuous mode on regular channels */
+#define ADC_CR1_JDISCEN 0x00001000U /*!<Discontinuous mode on injected channels */
+#define ADC_CR1_DISCNUM 0x0000E000U /*!<DISCNUM[2:0] bits (Discontinuous mode channel count) */
+#define ADC_CR1_DISCNUM_0 0x00002000U /*!<Bit 0 */
+#define ADC_CR1_DISCNUM_1 0x00004000U /*!<Bit 1 */
+#define ADC_CR1_DISCNUM_2 0x00008000U /*!<Bit 2 */
+#define ADC_CR1_JAWDEN 0x00400000U /*!<Analog watchdog enable on injected channels */
+#define ADC_CR1_AWDEN 0x00800000U /*!<Analog watchdog enable on regular channels */
+#define ADC_CR1_RES 0x03000000U /*!<RES[2:0] bits (Resolution) */
+#define ADC_CR1_RES_0 0x01000000U /*!<Bit 0 */
+#define ADC_CR1_RES_1 0x02000000U /*!<Bit 1 */
+#define ADC_CR1_OVRIE 0x04000000U /*!<overrun interrupt enable */
+
+/******************* Bit definition for ADC_CR2 register ********************/
+#define ADC_CR2_ADON 0x00000001U /*!<A/D Converter ON / OFF */
+#define ADC_CR2_CONT 0x00000002U /*!<Continuous Conversion */
+#define ADC_CR2_DMA 0x00000100U /*!<Direct Memory access mode */
+#define ADC_CR2_DDS 0x00000200U /*!<DMA disable selection (Single ADC) */
+#define ADC_CR2_EOCS 0x00000400U /*!<End of conversion selection */
+#define ADC_CR2_ALIGN 0x00000800U /*!<Data Alignment */
+#define ADC_CR2_JEXTSEL 0x000F0000U /*!<JEXTSEL[3:0] bits (External event select for injected group) */
+#define ADC_CR2_JEXTSEL_0 0x00010000U /*!<Bit 0 */
+#define ADC_CR2_JEXTSEL_1 0x00020000U /*!<Bit 1 */
+#define ADC_CR2_JEXTSEL_2 0x00040000U /*!<Bit 2 */
+#define ADC_CR2_JEXTSEL_3 0x00080000U /*!<Bit 3 */
+#define ADC_CR2_JEXTEN 0x00300000U /*!<JEXTEN[1:0] bits (External Trigger Conversion mode for injected channelsp) */
+#define ADC_CR2_JEXTEN_0 0x00100000U /*!<Bit 0 */
+#define ADC_CR2_JEXTEN_1 0x00200000U /*!<Bit 1 */
+#define ADC_CR2_JSWSTART 0x00400000U /*!<Start Conversion of injected channels */
+#define ADC_CR2_EXTSEL 0x0F000000U /*!<EXTSEL[3:0] bits (External Event Select for regular group) */
+#define ADC_CR2_EXTSEL_0 0x01000000U /*!<Bit 0 */
+#define ADC_CR2_EXTSEL_1 0x02000000U /*!<Bit 1 */
+#define ADC_CR2_EXTSEL_2 0x04000000U /*!<Bit 2 */
+#define ADC_CR2_EXTSEL_3 0x08000000U /*!<Bit 3 */
+#define ADC_CR2_EXTEN 0x30000000U /*!<EXTEN[1:0] bits (External Trigger Conversion mode for regular channelsp) */
+#define ADC_CR2_EXTEN_0 0x10000000U /*!<Bit 0 */
+#define ADC_CR2_EXTEN_1 0x20000000U /*!<Bit 1 */
+#define ADC_CR2_SWSTART 0x40000000U /*!<Start Conversion of regular channels */
+
+/****************** Bit definition for ADC_SMPR1 register *******************/
+#define ADC_SMPR1_SMP10 0x00000007U /*!<SMP10[2:0] bits (Channel 10 Sample time selection) */
+#define ADC_SMPR1_SMP10_0 0x00000001U /*!<Bit 0 */
+#define ADC_SMPR1_SMP10_1 0x00000002U /*!<Bit 1 */
+#define ADC_SMPR1_SMP10_2 0x00000004U /*!<Bit 2 */
+#define ADC_SMPR1_SMP11 0x00000038U /*!<SMP11[2:0] bits (Channel 11 Sample time selection) */
+#define ADC_SMPR1_SMP11_0 0x00000008U /*!<Bit 0 */
+#define ADC_SMPR1_SMP11_1 0x00000010U /*!<Bit 1 */
+#define ADC_SMPR1_SMP11_2 0x00000020U /*!<Bit 2 */
+#define ADC_SMPR1_SMP12 0x000001C0U /*!<SMP12[2:0] bits (Channel 12 Sample time selection) */
+#define ADC_SMPR1_SMP12_0 0x00000040U /*!<Bit 0 */
+#define ADC_SMPR1_SMP12_1 0x00000080U /*!<Bit 1 */
+#define ADC_SMPR1_SMP12_2 0x00000100U /*!<Bit 2 */
+#define ADC_SMPR1_SMP13 0x00000E00U /*!<SMP13[2:0] bits (Channel 13 Sample time selection) */
+#define ADC_SMPR1_SMP13_0 0x00000200U /*!<Bit 0 */
+#define ADC_SMPR1_SMP13_1 0x00000400U /*!<Bit 1 */
+#define ADC_SMPR1_SMP13_2 0x00000800U /*!<Bit 2 */
+#define ADC_SMPR1_SMP14 0x00007000U /*!<SMP14[2:0] bits (Channel 14 Sample time selection) */
+#define ADC_SMPR1_SMP14_0 0x00001000U /*!<Bit 0 */
+#define ADC_SMPR1_SMP14_1 0x00002000U /*!<Bit 1 */
+#define ADC_SMPR1_SMP14_2 0x00004000U /*!<Bit 2 */
+#define ADC_SMPR1_SMP15 0x00038000U /*!<SMP15[2:0] bits (Channel 15 Sample time selection) */
+#define ADC_SMPR1_SMP15_0 0x00008000U /*!<Bit 0 */
+#define ADC_SMPR1_SMP15_1 0x00010000U /*!<Bit 1 */
+#define ADC_SMPR1_SMP15_2 0x00020000U /*!<Bit 2 */
+#define ADC_SMPR1_SMP16 0x001C0000U /*!<SMP16[2:0] bits (Channel 16 Sample time selection) */
+#define ADC_SMPR1_SMP16_0 0x00040000U /*!<Bit 0 */
+#define ADC_SMPR1_SMP16_1 0x00080000U /*!<Bit 1 */
+#define ADC_SMPR1_SMP16_2 0x00100000U /*!<Bit 2 */
+#define ADC_SMPR1_SMP17 0x00E00000U /*!<SMP17[2:0] bits (Channel 17 Sample time selection) */
+#define ADC_SMPR1_SMP17_0 0x00200000U /*!<Bit 0 */
+#define ADC_SMPR1_SMP17_1 0x00400000U /*!<Bit 1 */
+#define ADC_SMPR1_SMP17_2 0x00800000U /*!<Bit 2 */
+#define ADC_SMPR1_SMP18 0x07000000U /*!<SMP18[2:0] bits (Channel 18 Sample time selection) */
+#define ADC_SMPR1_SMP18_0 0x01000000U /*!<Bit 0 */
+#define ADC_SMPR1_SMP18_1 0x02000000U /*!<Bit 1 */
+#define ADC_SMPR1_SMP18_2 0x04000000U /*!<Bit 2 */
+
+/****************** Bit definition for ADC_SMPR2 register *******************/
+#define ADC_SMPR2_SMP0 0x00000007U /*!<SMP0[2:0] bits (Channel 0 Sample time selection) */
+#define ADC_SMPR2_SMP0_0 0x00000001U /*!<Bit 0 */
+#define ADC_SMPR2_SMP0_1 0x00000002U /*!<Bit 1 */
+#define ADC_SMPR2_SMP0_2 0x00000004U /*!<Bit 2 */
+#define ADC_SMPR2_SMP1 0x00000038U /*!<SMP1[2:0] bits (Channel 1 Sample time selection) */
+#define ADC_SMPR2_SMP1_0 0x00000008U /*!<Bit 0 */
+#define ADC_SMPR2_SMP1_1 0x00000010U /*!<Bit 1 */
+#define ADC_SMPR2_SMP1_2 0x00000020U /*!<Bit 2 */
+#define ADC_SMPR2_SMP2 0x000001C0U /*!<SMP2[2:0] bits (Channel 2 Sample time selection) */
+#define ADC_SMPR2_SMP2_0 0x00000040U /*!<Bit 0 */
+#define ADC_SMPR2_SMP2_1 0x00000080U /*!<Bit 1 */
+#define ADC_SMPR2_SMP2_2 0x00000100U /*!<Bit 2 */
+#define ADC_SMPR2_SMP3 0x00000E00U /*!<SMP3[2:0] bits (Channel 3 Sample time selection) */
+#define ADC_SMPR2_SMP3_0 0x00000200U /*!<Bit 0 */
+#define ADC_SMPR2_SMP3_1 0x00000400U /*!<Bit 1 */
+#define ADC_SMPR2_SMP3_2 0x00000800U /*!<Bit 2 */
+#define ADC_SMPR2_SMP4 0x00007000U /*!<SMP4[2:0] bits (Channel 4 Sample time selection) */
+#define ADC_SMPR2_SMP4_0 0x00001000U /*!<Bit 0 */
+#define ADC_SMPR2_SMP4_1 0x00002000U /*!<Bit 1 */
+#define ADC_SMPR2_SMP4_2 0x00004000U /*!<Bit 2 */
+#define ADC_SMPR2_SMP5 0x00038000U /*!<SMP5[2:0] bits (Channel 5 Sample time selection) */
+#define ADC_SMPR2_SMP5_0 0x00008000U /*!<Bit 0 */
+#define ADC_SMPR2_SMP5_1 0x00010000U /*!<Bit 1 */
+#define ADC_SMPR2_SMP5_2 0x00020000U /*!<Bit 2 */
+#define ADC_SMPR2_SMP6 0x001C0000U /*!<SMP6[2:0] bits (Channel 6 Sample time selection) */
+#define ADC_SMPR2_SMP6_0 0x00040000U /*!<Bit 0 */
+#define ADC_SMPR2_SMP6_1 0x00080000U /*!<Bit 1 */
+#define ADC_SMPR2_SMP6_2 0x00100000U /*!<Bit 2 */
+#define ADC_SMPR2_SMP7 0x00E00000U /*!<SMP7[2:0] bits (Channel 7 Sample time selection) */
+#define ADC_SMPR2_SMP7_0 0x00200000U /*!<Bit 0 */
+#define ADC_SMPR2_SMP7_1 0x00400000U /*!<Bit 1 */
+#define ADC_SMPR2_SMP7_2 0x00800000U /*!<Bit 2 */
+#define ADC_SMPR2_SMP8 0x07000000U /*!<SMP8[2:0] bits (Channel 8 Sample time selection) */
+#define ADC_SMPR2_SMP8_0 0x01000000U /*!<Bit 0 */
+#define ADC_SMPR2_SMP8_1 0x02000000U /*!<Bit 1 */
+#define ADC_SMPR2_SMP8_2 0x04000000U /*!<Bit 2 */
+#define ADC_SMPR2_SMP9 0x38000000U /*!<SMP9[2:0] bits (Channel 9 Sample time selection) */
+#define ADC_SMPR2_SMP9_0 0x08000000U /*!<Bit 0 */
+#define ADC_SMPR2_SMP9_1 0x10000000U /*!<Bit 1 */
+#define ADC_SMPR2_SMP9_2 0x20000000U /*!<Bit 2 */
+
+/****************** Bit definition for ADC_JOFR1 register *******************/
+#define ADC_JOFR1_JOFFSET1 0x0FFFU /*!<Data offset for injected channel 1 */
+
+/****************** Bit definition for ADC_JOFR2 register *******************/
+#define ADC_JOFR2_JOFFSET2 0x0FFFU /*!<Data offset for injected channel 2 */
+
+/****************** Bit definition for ADC_JOFR3 register *******************/
+#define ADC_JOFR3_JOFFSET3 0x0FFFU /*!<Data offset for injected channel 3 */
+
+/****************** Bit definition for ADC_JOFR4 register *******************/
+#define ADC_JOFR4_JOFFSET4 0x0FFFU /*!<Data offset for injected channel 4 */
+
+/******************* Bit definition for ADC_HTR register ********************/
+#define ADC_HTR_HT 0x0FFFU /*!<Analog watchdog high threshold */
+
+/******************* Bit definition for ADC_LTR register ********************/
+#define ADC_LTR_LT 0x0FFFU /*!<Analog watchdog low threshold */
+
+/******************* Bit definition for ADC_SQR1 register *******************/
+#define ADC_SQR1_SQ13 0x0000001FU /*!<SQ13[4:0] bits (13th conversion in regular sequence) */
+#define ADC_SQR1_SQ13_0 0x00000001U /*!<Bit 0 */
+#define ADC_SQR1_SQ13_1 0x00000002U /*!<Bit 1 */
+#define ADC_SQR1_SQ13_2 0x00000004U /*!<Bit 2 */
+#define ADC_SQR1_SQ13_3 0x00000008U /*!<Bit 3 */
+#define ADC_SQR1_SQ13_4 0x00000010U /*!<Bit 4 */
+#define ADC_SQR1_SQ14 0x000003E0U /*!<SQ14[4:0] bits (14th conversion in regular sequence) */
+#define ADC_SQR1_SQ14_0 0x00000020U /*!<Bit 0 */
+#define ADC_SQR1_SQ14_1 0x00000040U /*!<Bit 1 */
+#define ADC_SQR1_SQ14_2 0x00000080U /*!<Bit 2 */
+#define ADC_SQR1_SQ14_3 0x00000100U /*!<Bit 3 */
+#define ADC_SQR1_SQ14_4 0x00000200U /*!<Bit 4 */
+#define ADC_SQR1_SQ15 0x00007C00U /*!<SQ15[4:0] bits (15th conversion in regular sequence) */
+#define ADC_SQR1_SQ15_0 0x00000400U /*!<Bit 0 */
+#define ADC_SQR1_SQ15_1 0x00000800U /*!<Bit 1 */
+#define ADC_SQR1_SQ15_2 0x00001000U /*!<Bit 2 */
+#define ADC_SQR1_SQ15_3 0x00002000U /*!<Bit 3 */
+#define ADC_SQR1_SQ15_4 0x00004000U /*!<Bit 4 */
+#define ADC_SQR1_SQ16 0x000F8000U /*!<SQ16[4:0] bits (16th conversion in regular sequence) */
+#define ADC_SQR1_SQ16_0 0x00008000U /*!<Bit 0 */
+#define ADC_SQR1_SQ16_1 0x00010000U /*!<Bit 1 */
+#define ADC_SQR1_SQ16_2 0x00020000U /*!<Bit 2 */
+#define ADC_SQR1_SQ16_3 0x00040000U /*!<Bit 3 */
+#define ADC_SQR1_SQ16_4 0x00080000U /*!<Bit 4 */
+#define ADC_SQR1_L 0x00F00000U /*!<L[3:0] bits (Regular channel sequence length) */
+#define ADC_SQR1_L_0 0x00100000U /*!<Bit 0 */
+#define ADC_SQR1_L_1 0x00200000U /*!<Bit 1 */
+#define ADC_SQR1_L_2 0x00400000U /*!<Bit 2 */
+#define ADC_SQR1_L_3 0x00800000U /*!<Bit 3 */
+
+/******************* Bit definition for ADC_SQR2 register *******************/
+#define ADC_SQR2_SQ7 0x0000001FU /*!<SQ7[4:0] bits (7th conversion in regular sequence) */
+#define ADC_SQR2_SQ7_0 0x00000001U /*!<Bit 0 */
+#define ADC_SQR2_SQ7_1 0x00000002U /*!<Bit 1 */
+#define ADC_SQR2_SQ7_2 0x00000004U /*!<Bit 2 */
+#define ADC_SQR2_SQ7_3 0x00000008U /*!<Bit 3 */
+#define ADC_SQR2_SQ7_4 0x00000010U /*!<Bit 4 */
+#define ADC_SQR2_SQ8 0x000003E0U /*!<SQ8[4:0] bits (8th conversion in regular sequence) */
+#define ADC_SQR2_SQ8_0 0x00000020U /*!<Bit 0 */
+#define ADC_SQR2_SQ8_1 0x00000040U /*!<Bit 1 */
+#define ADC_SQR2_SQ8_2 0x00000080U /*!<Bit 2 */
+#define ADC_SQR2_SQ8_3 0x00000100U /*!<Bit 3 */
+#define ADC_SQR2_SQ8_4 0x00000200U /*!<Bit 4 */
+#define ADC_SQR2_SQ9 0x00007C00U /*!<SQ9[4:0] bits (9th conversion in regular sequence) */
+#define ADC_SQR2_SQ9_0 0x00000400U /*!<Bit 0 */
+#define ADC_SQR2_SQ9_1 0x00000800U /*!<Bit 1 */
+#define ADC_SQR2_SQ9_2 0x00001000U /*!<Bit 2 */
+#define ADC_SQR2_SQ9_3 0x00002000U /*!<Bit 3 */
+#define ADC_SQR2_SQ9_4 0x00004000U /*!<Bit 4 */
+#define ADC_SQR2_SQ10 0x000F8000U /*!<SQ10[4:0] bits (10th conversion in regular sequence) */
+#define ADC_SQR2_SQ10_0 0x00008000U /*!<Bit 0 */
+#define ADC_SQR2_SQ10_1 0x00010000U /*!<Bit 1 */
+#define ADC_SQR2_SQ10_2 0x00020000U /*!<Bit 2 */
+#define ADC_SQR2_SQ10_3 0x00040000U /*!<Bit 3 */
+#define ADC_SQR2_SQ10_4 0x00080000U /*!<Bit 4 */
+#define ADC_SQR2_SQ11 0x01F00000U /*!<SQ11[4:0] bits (11th conversion in regular sequence) */
+#define ADC_SQR2_SQ11_0 0x00100000U /*!<Bit 0 */
+#define ADC_SQR2_SQ11_1 0x00200000U /*!<Bit 1 */
+#define ADC_SQR2_SQ11_2 0x00400000U /*!<Bit 2 */
+#define ADC_SQR2_SQ11_3 0x00800000U /*!<Bit 3 */
+#define ADC_SQR2_SQ11_4 0x01000000U /*!<Bit 4 */
+#define ADC_SQR2_SQ12 0x3E000000U /*!<SQ12[4:0] bits (12th conversion in regular sequence) */
+#define ADC_SQR2_SQ12_0 0x02000000U /*!<Bit 0 */
+#define ADC_SQR2_SQ12_1 0x04000000U /*!<Bit 1 */
+#define ADC_SQR2_SQ12_2 0x08000000U /*!<Bit 2 */
+#define ADC_SQR2_SQ12_3 0x10000000U /*!<Bit 3 */
+#define ADC_SQR2_SQ12_4 0x20000000U /*!<Bit 4 */
+
+/******************* Bit definition for ADC_SQR3 register *******************/
+#define ADC_SQR3_SQ1 0x0000001FU /*!<SQ1[4:0] bits (1st conversion in regular sequence) */
+#define ADC_SQR3_SQ1_0 0x00000001U /*!<Bit 0 */
+#define ADC_SQR3_SQ1_1 0x00000002U /*!<Bit 1 */
+#define ADC_SQR3_SQ1_2 0x00000004U /*!<Bit 2 */
+#define ADC_SQR3_SQ1_3 0x00000008U /*!<Bit 3 */
+#define ADC_SQR3_SQ1_4 0x00000010U /*!<Bit 4 */
+#define ADC_SQR3_SQ2 0x000003E0U /*!<SQ2[4:0] bits (2nd conversion in regular sequence) */
+#define ADC_SQR3_SQ2_0 0x00000020U /*!<Bit 0 */
+#define ADC_SQR3_SQ2_1 0x00000040U /*!<Bit 1 */
+#define ADC_SQR3_SQ2_2 0x00000080U /*!<Bit 2 */
+#define ADC_SQR3_SQ2_3 0x00000100U /*!<Bit 3 */
+#define ADC_SQR3_SQ2_4 0x00000200U /*!<Bit 4 */
+#define ADC_SQR3_SQ3 0x00007C00U /*!<SQ3[4:0] bits (3rd conversion in regular sequence) */
+#define ADC_SQR3_SQ3_0 0x00000400U /*!<Bit 0 */
+#define ADC_SQR3_SQ3_1 0x00000800U /*!<Bit 1 */
+#define ADC_SQR3_SQ3_2 0x00001000U /*!<Bit 2 */
+#define ADC_SQR3_SQ3_3 0x00002000U /*!<Bit 3 */
+#define ADC_SQR3_SQ3_4 0x00004000U /*!<Bit 4 */
+#define ADC_SQR3_SQ4 0x000F8000U /*!<SQ4[4:0] bits (4th conversion in regular sequence) */
+#define ADC_SQR3_SQ4_0 0x00008000U /*!<Bit 0 */
+#define ADC_SQR3_SQ4_1 0x00010000U /*!<Bit 1 */
+#define ADC_SQR3_SQ4_2 0x00020000U /*!<Bit 2 */
+#define ADC_SQR3_SQ4_3 0x00040000U /*!<Bit 3 */
+#define ADC_SQR3_SQ4_4 0x00080000U /*!<Bit 4 */
+#define ADC_SQR3_SQ5 0x01F00000U /*!<SQ5[4:0] bits (5th conversion in regular sequence) */
+#define ADC_SQR3_SQ5_0 0x00100000U /*!<Bit 0 */
+#define ADC_SQR3_SQ5_1 0x00200000U /*!<Bit 1 */
+#define ADC_SQR3_SQ5_2 0x00400000U /*!<Bit 2 */
+#define ADC_SQR3_SQ5_3 0x00800000U /*!<Bit 3 */
+#define ADC_SQR3_SQ5_4 0x01000000U /*!<Bit 4 */
+#define ADC_SQR3_SQ6 0x3E000000U /*!<SQ6[4:0] bits (6th conversion in regular sequence) */
+#define ADC_SQR3_SQ6_0 0x02000000U /*!<Bit 0 */
+#define ADC_SQR3_SQ6_1 0x04000000U /*!<Bit 1 */
+#define ADC_SQR3_SQ6_2 0x08000000U /*!<Bit 2 */
+#define ADC_SQR3_SQ6_3 0x10000000U /*!<Bit 3 */
+#define ADC_SQR3_SQ6_4 0x20000000U /*!<Bit 4 */
+
+/******************* Bit definition for ADC_JSQR register *******************/
+#define ADC_JSQR_JSQ1 0x0000001FU /*!<JSQ1[4:0] bits (1st conversion in injected sequence) */
+#define ADC_JSQR_JSQ1_0 0x00000001U /*!<Bit 0 */
+#define ADC_JSQR_JSQ1_1 0x00000002U /*!<Bit 1 */
+#define ADC_JSQR_JSQ1_2 0x00000004U /*!<Bit 2 */
+#define ADC_JSQR_JSQ1_3 0x00000008U /*!<Bit 3 */
+#define ADC_JSQR_JSQ1_4 0x00000010U /*!<Bit 4 */
+#define ADC_JSQR_JSQ2 0x000003E0U /*!<JSQ2[4:0] bits (2nd conversion in injected sequence) */
+#define ADC_JSQR_JSQ2_0 0x00000020U /*!<Bit 0 */
+#define ADC_JSQR_JSQ2_1 0x00000040U /*!<Bit 1 */
+#define ADC_JSQR_JSQ2_2 0x00000080U /*!<Bit 2 */
+#define ADC_JSQR_JSQ2_3 0x00000100U /*!<Bit 3 */
+#define ADC_JSQR_JSQ2_4 0x00000200U /*!<Bit 4 */
+#define ADC_JSQR_JSQ3 0x00007C00U /*!<JSQ3[4:0] bits (3rd conversion in injected sequence) */
+#define ADC_JSQR_JSQ3_0 0x00000400U /*!<Bit 0 */
+#define ADC_JSQR_JSQ3_1 0x00000800U /*!<Bit 1 */
+#define ADC_JSQR_JSQ3_2 0x00001000U /*!<Bit 2 */
+#define ADC_JSQR_JSQ3_3 0x00002000U /*!<Bit 3 */
+#define ADC_JSQR_JSQ3_4 0x00004000U /*!<Bit 4 */
+#define ADC_JSQR_JSQ4 0x000F8000U /*!<JSQ4[4:0] bits (4th conversion in injected sequence) */
+#define ADC_JSQR_JSQ4_0 0x00008000U /*!<Bit 0 */
+#define ADC_JSQR_JSQ4_1 0x00010000U /*!<Bit 1 */
+#define ADC_JSQR_JSQ4_2 0x00020000U /*!<Bit 2 */
+#define ADC_JSQR_JSQ4_3 0x00040000U /*!<Bit 3 */
+#define ADC_JSQR_JSQ4_4 0x00080000U /*!<Bit 4 */
+#define ADC_JSQR_JL 0x00300000U /*!<JL[1:0] bits (Injected Sequence length) */
+#define ADC_JSQR_JL_0 0x00100000U /*!<Bit 0 */
+#define ADC_JSQR_JL_1 0x00200000U /*!<Bit 1 */
+
+/******************* Bit definition for ADC_JDR1 register *******************/
+#define ADC_JDR1_JDATA 0xFFFFU /*!<Injected data */
+
+/******************* Bit definition for ADC_JDR2 register *******************/
+#define ADC_JDR2_JDATA 0xFFFFU /*!<Injected data */
+
+/******************* Bit definition for ADC_JDR3 register *******************/
+#define ADC_JDR3_JDATA 0xFFFFU /*!<Injected data */
+
+/******************* Bit definition for ADC_JDR4 register *******************/
+#define ADC_JDR4_JDATA 0xFFFFU /*!<Injected data */
+
+/******************** Bit definition for ADC_DR register ********************/
+#define ADC_DR_DATA 0x0000FFFFU /*!<Regular data */
+#define ADC_DR_ADC2DATA 0xFFFF0000U /*!<ADC2 data */
+
+/******************* Bit definition for ADC_CSR register ********************/
+#define ADC_CSR_AWD1 0x00000001U /*!<ADC1 Analog watchdog flag */
+#define ADC_CSR_EOC1 0x00000002U /*!<ADC1 End of conversion */
+#define ADC_CSR_JEOC1 0x00000004U /*!<ADC1 Injected channel end of conversion */
+#define ADC_CSR_JSTRT1 0x00000008U /*!<ADC1 Injected channel Start flag */
+#define ADC_CSR_STRT1 0x00000010U /*!<ADC1 Regular channel Start flag */
+#define ADC_CSR_OVR1 0x00000020U /*!<ADC1 DMA overrun flag */
+#define ADC_CSR_AWD2 0x00000100U /*!<ADC2 Analog watchdog flag */
+#define ADC_CSR_EOC2 0x00000200U /*!<ADC2 End of conversion */
+#define ADC_CSR_JEOC2 0x00000400U /*!<ADC2 Injected channel end of conversion */
+#define ADC_CSR_JSTRT2 0x00000800U /*!<ADC2 Injected channel Start flag */
+#define ADC_CSR_STRT2 0x00001000U /*!<ADC2 Regular channel Start flag */
+#define ADC_CSR_OVR2 0x00002000U /*!<ADC2 DMA overrun flag */
+#define ADC_CSR_AWD3 0x00010000U /*!<ADC3 Analog watchdog flag */
+#define ADC_CSR_EOC3 0x00020000U /*!<ADC3 End of conversion */
+#define ADC_CSR_JEOC3 0x00040000U /*!<ADC3 Injected channel end of conversion */
+#define ADC_CSR_JSTRT3 0x00080000U /*!<ADC3 Injected channel Start flag */
+#define ADC_CSR_STRT3 0x00100000U /*!<ADC3 Regular channel Start flag */
+#define ADC_CSR_OVR3 0x00200000U /*!<ADC3 DMA overrun flag */
+
+/* Legacy defines */
+#define ADC_CSR_DOVR1 ADC_CSR_OVR1
+#define ADC_CSR_DOVR2 ADC_CSR_OVR2
+#define ADC_CSR_DOVR3 ADC_CSR_OVR3
+
+/******************* Bit definition for ADC_CCR register ********************/
+#define ADC_CCR_MULTI 0x0000001FU /*!<MULTI[4:0] bits (Multi-ADC mode selection) */
+#define ADC_CCR_MULTI_0 0x00000001U /*!<Bit 0 */
+#define ADC_CCR_MULTI_1 0x00000002U /*!<Bit 1 */
+#define ADC_CCR_MULTI_2 0x00000004U /*!<Bit 2 */
+#define ADC_CCR_MULTI_3 0x00000008U /*!<Bit 3 */
+#define ADC_CCR_MULTI_4 0x00000010U /*!<Bit 4 */
+#define ADC_CCR_DELAY 0x00000F00U /*!<DELAY[3:0] bits (Delay between 2 sampling phases) */
+#define ADC_CCR_DELAY_0 0x00000100U /*!<Bit 0 */
+#define ADC_CCR_DELAY_1 0x00000200U /*!<Bit 1 */
+#define ADC_CCR_DELAY_2 0x00000400U /*!<Bit 2 */
+#define ADC_CCR_DELAY_3 0x00000800U /*!<Bit 3 */
+#define ADC_CCR_DDS 0x00002000U /*!<DMA disable selection (Multi-ADC mode) */
+#define ADC_CCR_DMA 0x0000C000U /*!<DMA[1:0] bits (Direct Memory Access mode for multimode) */
+#define ADC_CCR_DMA_0 0x00004000U /*!<Bit 0 */
+#define ADC_CCR_DMA_1 0x00008000U /*!<Bit 1 */
+#define ADC_CCR_ADCPRE 0x00030000U /*!<ADCPRE[1:0] bits (ADC prescaler) */
+#define ADC_CCR_ADCPRE_0 0x00010000U /*!<Bit 0 */
+#define ADC_CCR_ADCPRE_1 0x00020000U /*!<Bit 1 */
+#define ADC_CCR_VBATE 0x00400000U /*!<VBAT Enable */
+#define ADC_CCR_TSVREFE 0x00800000U /*!<Temperature Sensor and VREFINT Enable */
+
+/******************* Bit definition for ADC_CDR register ********************/
+#define ADC_CDR_DATA1 0x0000FFFFU /*!<1st data of a pair of regular conversions */
+#define ADC_CDR_DATA2 0xFFFF0000U /*!<2nd data of a pair of regular conversions */
+
+/******************************************************************************/
+/* */
+/* Controller Area Network */
+/* */
+/******************************************************************************/
+/*!<CAN control and status registers */
+/******************* Bit definition for CAN_MCR register ********************/
+#define CAN_MCR_INRQ 0x00000001U /*!<Initialization Request */
+#define CAN_MCR_SLEEP 0x00000002U /*!<Sleep Mode Request */
+#define CAN_MCR_TXFP 0x00000004U /*!<Transmit FIFO Priority */
+#define CAN_MCR_RFLM 0x00000008U /*!<Receive FIFO Locked Mode */
+#define CAN_MCR_NART 0x00000010U /*!<No Automatic Retransmission */
+#define CAN_MCR_AWUM 0x00000020U /*!<Automatic Wakeup Mode */
+#define CAN_MCR_ABOM 0x00000040U /*!<Automatic Bus-Off Management */
+#define CAN_MCR_TTCM 0x00000080U /*!<Time Triggered Communication Mode */
+#define CAN_MCR_RESET 0x00008000U /*!<bxCAN software master reset */
+#define CAN_MCR_DBF 0x00010000U /*!<bxCAN Debug freeze */
+/******************* Bit definition for CAN_MSR register ********************/
+#define CAN_MSR_INAK 0x0001U /*!<Initialization Acknowledge */
+#define CAN_MSR_SLAK 0x0002U /*!<Sleep Acknowledge */
+#define CAN_MSR_ERRI 0x0004U /*!<Error Interrupt */
+#define CAN_MSR_WKUI 0x0008U /*!<Wakeup Interrupt */
+#define CAN_MSR_SLAKI 0x0010U /*!<Sleep Acknowledge Interrupt */
+#define CAN_MSR_TXM 0x0100U /*!<Transmit Mode */
+#define CAN_MSR_RXM 0x0200U /*!<Receive Mode */
+#define CAN_MSR_SAMP 0x0400U /*!<Last Sample Point */
+#define CAN_MSR_RX 0x0800U /*!<CAN Rx Signal */
+
+/******************* Bit definition for CAN_TSR register ********************/
+#define CAN_TSR_RQCP0 0x00000001U /*!<Request Completed Mailbox0 */
+#define CAN_TSR_TXOK0 0x00000002U /*!<Transmission OK of Mailbox0 */
+#define CAN_TSR_ALST0 0x00000004U /*!<Arbitration Lost for Mailbox0 */
+#define CAN_TSR_TERR0 0x00000008U /*!<Transmission Error of Mailbox0 */
+#define CAN_TSR_ABRQ0 0x00000080U /*!<Abort Request for Mailbox0 */
+#define CAN_TSR_RQCP1 0x00000100U /*!<Request Completed Mailbox1 */
+#define CAN_TSR_TXOK1 0x00000200U /*!<Transmission OK of Mailbox1 */
+#define CAN_TSR_ALST1 0x00000400U /*!<Arbitration Lost for Mailbox1 */
+#define CAN_TSR_TERR1 0x00000800U /*!<Transmission Error of Mailbox1 */
+#define CAN_TSR_ABRQ1 0x00008000U /*!<Abort Request for Mailbox 1 */
+#define CAN_TSR_RQCP2 0x00010000U /*!<Request Completed Mailbox2 */
+#define CAN_TSR_TXOK2 0x00020000U /*!<Transmission OK of Mailbox 2 */
+#define CAN_TSR_ALST2 0x00040000U /*!<Arbitration Lost for mailbox 2 */
+#define CAN_TSR_TERR2 0x00080000U /*!<Transmission Error of Mailbox 2 */
+#define CAN_TSR_ABRQ2 0x00800000U /*!<Abort Request for Mailbox 2 */
+#define CAN_TSR_CODE 0x03000000U /*!<Mailbox Code */
+
+#define CAN_TSR_TME 0x1C000000U /*!<TME[2:0] bits */
+#define CAN_TSR_TME0 0x04000000U /*!<Transmit Mailbox 0 Empty */
+#define CAN_TSR_TME1 0x08000000U /*!<Transmit Mailbox 1 Empty */
+#define CAN_TSR_TME2 0x10000000U /*!<Transmit Mailbox 2 Empty */
+
+#define CAN_TSR_LOW 0xE0000000U /*!<LOW[2:0] bits */
+#define CAN_TSR_LOW0 0x20000000U /*!<Lowest Priority Flag for Mailbox 0 */
+#define CAN_TSR_LOW1 0x40000000U /*!<Lowest Priority Flag for Mailbox 1 */
+#define CAN_TSR_LOW2 0x80000000U /*!<Lowest Priority Flag for Mailbox 2 */
+
+/******************* Bit definition for CAN_RF0R register *******************/
+#define CAN_RF0R_FMP0 0x03U /*!<FIFO 0 Message Pending */
+#define CAN_RF0R_FULL0 0x08U /*!<FIFO 0 Full */
+#define CAN_RF0R_FOVR0 0x10U /*!<FIFO 0 Overrun */
+#define CAN_RF0R_RFOM0 0x20U /*!<Release FIFO 0 Output Mailbox */
+
+/******************* Bit definition for CAN_RF1R register *******************/
+#define CAN_RF1R_FMP1 0x03U /*!<FIFO 1 Message Pending */
+#define CAN_RF1R_FULL1 0x08U /*!<FIFO 1 Full */
+#define CAN_RF1R_FOVR1 0x10U /*!<FIFO 1 Overrun */
+#define CAN_RF1R_RFOM1 0x20U /*!<Release FIFO 1 Output Mailbox */
+
+/******************** Bit definition for CAN_IER register *******************/
+#define CAN_IER_TMEIE 0x00000001U /*!<Transmit Mailbox Empty Interrupt Enable */
+#define CAN_IER_FMPIE0 0x00000002U /*!<FIFO Message Pending Interrupt Enable */
+#define CAN_IER_FFIE0 0x00000004U /*!<FIFO Full Interrupt Enable */
+#define CAN_IER_FOVIE0 0x00000008U /*!<FIFO Overrun Interrupt Enable */
+#define CAN_IER_FMPIE1 0x00000010U /*!<FIFO Message Pending Interrupt Enable */
+#define CAN_IER_FFIE1 0x00000020U /*!<FIFO Full Interrupt Enable */
+#define CAN_IER_FOVIE1 0x00000040U /*!<FIFO Overrun Interrupt Enable */
+#define CAN_IER_EWGIE 0x00000100U /*!<Error Warning Interrupt Enable */
+#define CAN_IER_EPVIE 0x00000200U /*!<Error Passive Interrupt Enable */
+#define CAN_IER_BOFIE 0x00000400U /*!<Bus-Off Interrupt Enable */
+#define CAN_IER_LECIE 0x00000800U /*!<Last Error Code Interrupt Enable */
+#define CAN_IER_ERRIE 0x00008000U /*!<Error Interrupt Enable */
+#define CAN_IER_WKUIE 0x00010000U /*!<Wakeup Interrupt Enable */
+#define CAN_IER_SLKIE 0x00020000U /*!<Sleep Interrupt Enable */
+#define CAN_IER_EWGIE 0x00000100U /*!<Error warning interrupt enable */
+#define CAN_IER_EPVIE 0x00000200U /*!<Error passive interrupt enable */
+#define CAN_IER_BOFIE 0x00000400U /*!<Bus-off interrupt enable */
+#define CAN_IER_LECIE 0x00000800U /*!<Last error code interrupt enable */
+#define CAN_IER_ERRIE 0x00008000U /*!<Error interrupt enable */
+
+
+/******************** Bit definition for CAN_ESR register *******************/
+#define CAN_ESR_EWGF 0x00000001U /*!<Error Warning Flag */
+#define CAN_ESR_EPVF 0x00000002U /*!<Error Passive Flag */
+#define CAN_ESR_BOFF 0x00000004U /*!<Bus-Off Flag */
+
+#define CAN_ESR_LEC 0x00000070U /*!<LEC[2:0] bits (Last Error Code) */
+#define CAN_ESR_LEC_0 0x00000010U /*!<Bit 0 */
+#define CAN_ESR_LEC_1 0x00000020U /*!<Bit 1 */
+#define CAN_ESR_LEC_2 0x00000040U /*!<Bit 2 */
+
+#define CAN_ESR_TEC 0x00FF0000U /*!<Least significant byte of the 9-bit Transmit Error Counter */
+#define CAN_ESR_REC 0xFF000000U /*!<Receive Error Counter */
+
+/******************* Bit definition for CAN_BTR register ********************/
+#define CAN_BTR_BRP 0x000003FFU /*!<Baud Rate Prescaler */
+#define CAN_BTR_TS1 0x000F0000U /*!<Time Segment 1 */
+#define CAN_BTR_TS1_0 0x00010000U /*!<Bit 0 */
+#define CAN_BTR_TS1_1 0x00020000U /*!<Bit 1 */
+#define CAN_BTR_TS1_2 0x00040000U /*!<Bit 2 */
+#define CAN_BTR_TS1_3 0x00080000U /*!<Bit 3 */
+#define CAN_BTR_TS2 0x00700000U /*!<Time Segment 2 */
+#define CAN_BTR_TS2_0 0x00100000U /*!<Bit 0 */
+#define CAN_BTR_TS2_1 0x00200000U /*!<Bit 1 */
+#define CAN_BTR_TS2_2 0x00400000U /*!<Bit 2 */
+#define CAN_BTR_SJW 0x03000000U /*!<Resynchronization Jump Width */
+#define CAN_BTR_SJW_0 0x01000000U /*!<Bit 0 */
+#define CAN_BTR_SJW_1 0x02000000U /*!<Bit 1 */
+#define CAN_BTR_LBKM 0x40000000U /*!<Loop Back Mode (Debug) */
+#define CAN_BTR_SILM 0x80000000U /*!<Silent Mode */
+
+
+/*!<Mailbox registers */
+/****************** Bit definition for CAN_TI0R register ********************/
+#define CAN_TI0R_TXRQ 0x00000001U /*!<Transmit Mailbox Request */
+#define CAN_TI0R_RTR 0x00000002U /*!<Remote Transmission Request */
+#define CAN_TI0R_IDE 0x00000004U /*!<Identifier Extension */
+#define CAN_TI0R_EXID 0x001FFFF8U /*!<Extended Identifier */
+#define CAN_TI0R_STID 0xFFE00000U /*!<Standard Identifier or Extended Identifier */
+
+/****************** Bit definition for CAN_TDT0R register *******************/
+#define CAN_TDT0R_DLC 0x0000000FU /*!<Data Length Code */
+#define CAN_TDT0R_TGT 0x00000100U /*!<Transmit Global Time */
+#define CAN_TDT0R_TIME 0xFFFF0000U /*!<Message Time Stamp */
+
+/****************** Bit definition for CAN_TDL0R register *******************/
+#define CAN_TDL0R_DATA0 0x000000FFU /*!<Data byte 0 */
+#define CAN_TDL0R_DATA1 0x0000FF00U /*!<Data byte 1 */
+#define CAN_TDL0R_DATA2 0x00FF0000U /*!<Data byte 2 */
+#define CAN_TDL0R_DATA3 0xFF000000U /*!<Data byte 3 */
+
+/****************** Bit definition for CAN_TDH0R register *******************/
+#define CAN_TDH0R_DATA4 0x000000FFU /*!<Data byte 4 */
+#define CAN_TDH0R_DATA5 0x0000FF00U /*!<Data byte 5 */
+#define CAN_TDH0R_DATA6 0x00FF0000U /*!<Data byte 6 */
+#define CAN_TDH0R_DATA7 0xFF000000U /*!<Data byte 7 */
+
+/******************* Bit definition for CAN_TI1R register *******************/
+#define CAN_TI1R_TXRQ 0x00000001U /*!<Transmit Mailbox Request */
+#define CAN_TI1R_RTR 0x00000002U /*!<Remote Transmission Request */
+#define CAN_TI1R_IDE 0x00000004U /*!<Identifier Extension */
+#define CAN_TI1R_EXID 0x001FFFF8U /*!<Extended Identifier */
+#define CAN_TI1R_STID 0xFFE00000U /*!<Standard Identifier or Extended Identifier */
+
+/******************* Bit definition for CAN_TDT1R register ******************/
+#define CAN_TDT1R_DLC 0x0000000FU /*!<Data Length Code */
+#define CAN_TDT1R_TGT 0x00000100U /*!<Transmit Global Time */
+#define CAN_TDT1R_TIME 0xFFFF0000U /*!<Message Time Stamp */
+
+/******************* Bit definition for CAN_TDL1R register ******************/
+#define CAN_TDL1R_DATA0 0x000000FFU /*!<Data byte 0 */
+#define CAN_TDL1R_DATA1 0x0000FF00U /*!<Data byte 1 */
+#define CAN_TDL1R_DATA2 0x00FF0000U /*!<Data byte 2 */
+#define CAN_TDL1R_DATA3 0xFF000000U /*!<Data byte 3 */
+
+/******************* Bit definition for CAN_TDH1R register ******************/
+#define CAN_TDH1R_DATA4 0x000000FFU /*!<Data byte 4 */
+#define CAN_TDH1R_DATA5 0x0000FF00U /*!<Data byte 5 */
+#define CAN_TDH1R_DATA6 0x00FF0000U /*!<Data byte 6 */
+#define CAN_TDH1R_DATA7 0xFF000000U /*!<Data byte 7 */
+
+/******************* Bit definition for CAN_TI2R register *******************/
+#define CAN_TI2R_TXRQ 0x00000001U /*!<Transmit Mailbox Request */
+#define CAN_TI2R_RTR 0x00000002U /*!<Remote Transmission Request */
+#define CAN_TI2R_IDE 0x00000004U /*!<Identifier Extension */
+#define CAN_TI2R_EXID 0x001FFFF8U /*!<Extended identifier */
+#define CAN_TI2R_STID 0xFFE00000U /*!<Standard Identifier or Extended Identifier */
+
+/******************* Bit definition for CAN_TDT2R register ******************/
+#define CAN_TDT2R_DLC 0x0000000FU /*!<Data Length Code */
+#define CAN_TDT2R_TGT 0x00000100U /*!<Transmit Global Time */
+#define CAN_TDT2R_TIME 0xFFFF0000U /*!<Message Time Stamp */
+
+/******************* Bit definition for CAN_TDL2R register ******************/
+#define CAN_TDL2R_DATA0 0x000000FFU /*!<Data byte 0 */
+#define CAN_TDL2R_DATA1 0x0000FF00U /*!<Data byte 1 */
+#define CAN_TDL2R_DATA2 0x00FF0000U /*!<Data byte 2 */
+#define CAN_TDL2R_DATA3 0xFF000000U /*!<Data byte 3 */
+
+/******************* Bit definition for CAN_TDH2R register ******************/
+#define CAN_TDH2R_DATA4 0x000000FFU /*!<Data byte 4 */
+#define CAN_TDH2R_DATA5 0x0000FF00U /*!<Data byte 5 */
+#define CAN_TDH2R_DATA6 0x00FF0000U /*!<Data byte 6 */
+#define CAN_TDH2R_DATA7 0xFF000000U /*!<Data byte 7 */
+
+/******************* Bit definition for CAN_RI0R register *******************/
+#define CAN_RI0R_RTR 0x00000002U /*!<Remote Transmission Request */
+#define CAN_RI0R_IDE 0x00000004U /*!<Identifier Extension */
+#define CAN_RI0R_EXID 0x001FFFF8U /*!<Extended Identifier */
+#define CAN_RI0R_STID 0xFFE00000U /*!<Standard Identifier or Extended Identifier */
+
+/******************* Bit definition for CAN_RDT0R register ******************/
+#define CAN_RDT0R_DLC 0x0000000FU /*!<Data Length Code */
+#define CAN_RDT0R_FMI 0x0000FF00U /*!<Filter Match Index */
+#define CAN_RDT0R_TIME 0xFFFF0000U /*!<Message Time Stamp */
+
+/******************* Bit definition for CAN_RDL0R register ******************/
+#define CAN_RDL0R_DATA0 0x000000FFU /*!<Data byte 0 */
+#define CAN_RDL0R_DATA1 0x0000FF00U /*!<Data byte 1 */
+#define CAN_RDL0R_DATA2 0x00FF0000U /*!<Data byte 2 */
+#define CAN_RDL0R_DATA3 0xFF000000U /*!<Data byte 3 */
+
+/******************* Bit definition for CAN_RDH0R register ******************/
+#define CAN_RDH0R_DATA4 0x000000FFU /*!<Data byte 4 */
+#define CAN_RDH0R_DATA5 0x0000FF00U /*!<Data byte 5 */
+#define CAN_RDH0R_DATA6 0x00FF0000U /*!<Data byte 6 */
+#define CAN_RDH0R_DATA7 0xFF000000U /*!<Data byte 7 */
+
+/******************* Bit definition for CAN_RI1R register *******************/
+#define CAN_RI1R_RTR 0x00000002U /*!<Remote Transmission Request */
+#define CAN_RI1R_IDE 0x00000004U /*!<Identifier Extension */
+#define CAN_RI1R_EXID 0x001FFFF8U /*!<Extended identifier */
+#define CAN_RI1R_STID 0xFFE00000U /*!<Standard Identifier or Extended Identifier */
+
+/******************* Bit definition for CAN_RDT1R register ******************/
+#define CAN_RDT1R_DLC 0x0000000FU /*!<Data Length Code */
+#define CAN_RDT1R_FMI 0x0000FF00U /*!<Filter Match Index */
+#define CAN_RDT1R_TIME 0xFFFF0000U /*!<Message Time Stamp */
+
+/******************* Bit definition for CAN_RDL1R register ******************/
+#define CAN_RDL1R_DATA0 0x000000FFU /*!<Data byte 0 */
+#define CAN_RDL1R_DATA1 0x0000FF00U /*!<Data byte 1 */
+#define CAN_RDL1R_DATA2 0x00FF0000U /*!<Data byte 2 */
+#define CAN_RDL1R_DATA3 0xFF000000U /*!<Data byte 3 */
+
+/******************* Bit definition for CAN_RDH1R register ******************/
+#define CAN_RDH1R_DATA4 0x000000FFU /*!<Data byte 4 */
+#define CAN_RDH1R_DATA5 0x0000FF00U /*!<Data byte 5 */
+#define CAN_RDH1R_DATA6 0x00FF0000U /*!<Data byte 6 */
+#define CAN_RDH1R_DATA7 0xFF000000U /*!<Data byte 7 */
+
+/*!<CAN filter registers */
+/******************* Bit definition for CAN_FMR register ********************/
+#define CAN_FMR_FINIT 0x01U /*!<Filter Init Mode */
+#define CAN_FMR_CAN2SB 0x00003F00U /*!<CAN2 start bank */
+
+/******************* Bit definition for CAN_FM1R register *******************/
+#define CAN_FM1R_FBM 0x0FFFFFFFU /*!<Filter Mode */
+#define CAN_FM1R_FBM0 0x00000001U /*!<Filter Init Mode bit 0 */
+#define CAN_FM1R_FBM1 0x00000002U /*!<Filter Init Mode bit 1 */
+#define CAN_FM1R_FBM2 0x00000004U /*!<Filter Init Mode bit 2 */
+#define CAN_FM1R_FBM3 0x00000008U /*!<Filter Init Mode bit 3 */
+#define CAN_FM1R_FBM4 0x00000010U /*!<Filter Init Mode bit 4 */
+#define CAN_FM1R_FBM5 0x00000020U /*!<Filter Init Mode bit 5 */
+#define CAN_FM1R_FBM6 0x00000040U /*!<Filter Init Mode bit 6 */
+#define CAN_FM1R_FBM7 0x00000080U /*!<Filter Init Mode bit 7 */
+#define CAN_FM1R_FBM8 0x00000100U /*!<Filter Init Mode bit 8 */
+#define CAN_FM1R_FBM9 0x00000200U /*!<Filter Init Mode bit 9 */
+#define CAN_FM1R_FBM10 0x00000400U /*!<Filter Init Mode bit 10 */
+#define CAN_FM1R_FBM11 0x00000800U /*!<Filter Init Mode bit 11 */
+#define CAN_FM1R_FBM12 0x00001000U /*!<Filter Init Mode bit 12 */
+#define CAN_FM1R_FBM13 0x00002000U /*!<Filter Init Mode bit 13 */
+#define CAN_FM1R_FBM14 0x00004000U /*!<Filter Init Mode bit 14 */
+#define CAN_FM1R_FBM15 0x00008000U /*!<Filter Init Mode bit 15 */
+#define CAN_FM1R_FBM16 0x00010000U /*!<Filter Init Mode bit 16 */
+#define CAN_FM1R_FBM17 0x00020000U /*!<Filter Init Mode bit 17 */
+#define CAN_FM1R_FBM18 0x00040000U /*!<Filter Init Mode bit 18 */
+#define CAN_FM1R_FBM19 0x00080000U /*!<Filter Init Mode bit 19 */
+#define CAN_FM1R_FBM20 0x00100000U /*!<Filter Init Mode bit 20 */
+#define CAN_FM1R_FBM21 0x00200000U /*!<Filter Init Mode bit 21 */
+#define CAN_FM1R_FBM22 0x00400000U /*!<Filter Init Mode bit 22 */
+#define CAN_FM1R_FBM23 0x00800000U /*!<Filter Init Mode bit 23 */
+#define CAN_FM1R_FBM24 0x01000000U /*!<Filter Init Mode bit 24 */
+#define CAN_FM1R_FBM25 0x02000000U /*!<Filter Init Mode bit 25 */
+#define CAN_FM1R_FBM26 0x04000000U /*!<Filter Init Mode bit 26 */
+#define CAN_FM1R_FBM27 0x08000000U /*!<Filter Init Mode bit 27 */
+
+/******************* Bit definition for CAN_FS1R register *******************/
+#define CAN_FS1R_FSC 0x0FFFFFFFU /*!<Filter Scale Configuration */
+#define CAN_FS1R_FSC0 0x00000001U /*!<Filter Scale Configuration bit 0 */
+#define CAN_FS1R_FSC1 0x00000002U /*!<Filter Scale Configuration bit 1 */
+#define CAN_FS1R_FSC2 0x00000004U /*!<Filter Scale Configuration bit 2 */
+#define CAN_FS1R_FSC3 0x00000008U /*!<Filter Scale Configuration bit 3 */
+#define CAN_FS1R_FSC4 0x00000010U /*!<Filter Scale Configuration bit 4 */
+#define CAN_FS1R_FSC5 0x00000020U /*!<Filter Scale Configuration bit 5 */
+#define CAN_FS1R_FSC6 0x00000040U /*!<Filter Scale Configuration bit 6 */
+#define CAN_FS1R_FSC7 0x00000080U /*!<Filter Scale Configuration bit 7 */
+#define CAN_FS1R_FSC8 0x00000100U /*!<Filter Scale Configuration bit 8 */
+#define CAN_FS1R_FSC9 0x00000200U /*!<Filter Scale Configuration bit 9 */
+#define CAN_FS1R_FSC10 0x00000400U /*!<Filter Scale Configuration bit 10 */
+#define CAN_FS1R_FSC11 0x00000800U /*!<Filter Scale Configuration bit 11 */
+#define CAN_FS1R_FSC12 0x00001000U /*!<Filter Scale Configuration bit 12 */
+#define CAN_FS1R_FSC13 0x00002000U /*!<Filter Scale Configuration bit 13 */
+#define CAN_FS1R_FSC14 0x00004000U /*!<Filter Scale Configuration bit 14 */
+#define CAN_FS1R_FSC15 0x00008000U /*!<Filter Scale Configuration bit 15 */
+#define CAN_FS1R_FSC16 0x00010000U /*!<Filter Scale Configuration bit 16 */
+#define CAN_FS1R_FSC17 0x00020000U /*!<Filter Scale Configuration bit 17 */
+#define CAN_FS1R_FSC18 0x00040000U /*!<Filter Scale Configuration bit 18 */
+#define CAN_FS1R_FSC19 0x00080000U /*!<Filter Scale Configuration bit 19 */
+#define CAN_FS1R_FSC20 0x00100000U /*!<Filter Scale Configuration bit 20 */
+#define CAN_FS1R_FSC21 0x00200000U /*!<Filter Scale Configuration bit 21 */
+#define CAN_FS1R_FSC22 0x00400000U /*!<Filter Scale Configuration bit 22 */
+#define CAN_FS1R_FSC23 0x00800000U /*!<Filter Scale Configuration bit 23 */
+#define CAN_FS1R_FSC24 0x01000000U /*!<Filter Scale Configuration bit 24 */
+#define CAN_FS1R_FSC25 0x02000000U /*!<Filter Scale Configuration bit 25 */
+#define CAN_FS1R_FSC26 0x04000000U /*!<Filter Scale Configuration bit 26 */
+#define CAN_FS1R_FSC27 0x08000000U /*!<Filter Scale Configuration bit 27 */
+
+/****************** Bit definition for CAN_FFA1R register *******************/
+#define CAN_FFA1R_FFA 0x0FFFFFFFU /*!<Filter FIFO Assignment */
+#define CAN_FFA1R_FFA0 0x00000001U /*!<Filter FIFO Assignment bit 0 */
+#define CAN_FFA1R_FFA1 0x00000002U /*!<Filter FIFO Assignment bit 1 */
+#define CAN_FFA1R_FFA2 0x00000004U /*!<Filter FIFO Assignment bit 2 */
+#define CAN_FFA1R_FFA3 0x00000008U /*!<Filter FIFO Assignment bit 3 */
+#define CAN_FFA1R_FFA4 0x00000010U /*!<Filter FIFO Assignment bit 4 */
+#define CAN_FFA1R_FFA5 0x00000020U /*!<Filter FIFO Assignment bit 5 */
+#define CAN_FFA1R_FFA6 0x00000040U /*!<Filter FIFO Assignment bit 6 */
+#define CAN_FFA1R_FFA7 0x00000080U /*!<Filter FIFO Assignment bit 7 */
+#define CAN_FFA1R_FFA8 0x00000100U /*!<Filter FIFO Assignment bit 8 */
+#define CAN_FFA1R_FFA9 0x00000200U /*!<Filter FIFO Assignment bit 9 */
+#define CAN_FFA1R_FFA10 0x00000400U /*!<Filter FIFO Assignment bit 10 */
+#define CAN_FFA1R_FFA11 0x00000800U /*!<Filter FIFO Assignment bit 11 */
+#define CAN_FFA1R_FFA12 0x00001000U /*!<Filter FIFO Assignment bit 12 */
+#define CAN_FFA1R_FFA13 0x00002000U /*!<Filter FIFO Assignment bit 13 */
+#define CAN_FFA1R_FFA14 0x00004000U /*!<Filter FIFO Assignment bit 14 */
+#define CAN_FFA1R_FFA15 0x00008000U /*!<Filter FIFO Assignment bit 15 */
+#define CAN_FFA1R_FFA16 0x00010000U /*!<Filter FIFO Assignment bit 16 */
+#define CAN_FFA1R_FFA17 0x00020000U /*!<Filter FIFO Assignment bit 17 */
+#define CAN_FFA1R_FFA18 0x00040000U /*!<Filter FIFO Assignment bit 18 */
+#define CAN_FFA1R_FFA19 0x00080000U /*!<Filter FIFO Assignment bit 19 */
+#define CAN_FFA1R_FFA20 0x00100000U /*!<Filter FIFO Assignment bit 20 */
+#define CAN_FFA1R_FFA21 0x00200000U /*!<Filter FIFO Assignment bit 21 */
+#define CAN_FFA1R_FFA22 0x00400000U /*!<Filter FIFO Assignment bit 22 */
+#define CAN_FFA1R_FFA23 0x00800000U /*!<Filter FIFO Assignment bit 23 */
+#define CAN_FFA1R_FFA24 0x01000000U /*!<Filter FIFO Assignment bit 24 */
+#define CAN_FFA1R_FFA25 0x02000000U /*!<Filter FIFO Assignment bit 25 */
+#define CAN_FFA1R_FFA26 0x04000000U /*!<Filter FIFO Assignment bit 26 */
+#define CAN_FFA1R_FFA27 0x08000000U /*!<Filter FIFO Assignment bit 27 */
+
+/******************* Bit definition for CAN_FA1R register *******************/
+#define CAN_FA1R_FACT 0x0FFFFFFFU /*!<Filter Active */
+#define CAN_FA1R_FACT0 0x00000001U /*!<Filter Active bit 0 */
+#define CAN_FA1R_FACT1 0x00000002U /*!<Filter Active bit 1 */
+#define CAN_FA1R_FACT2 0x00000004U /*!<Filter Active bit 2 */
+#define CAN_FA1R_FACT3 0x00000008U /*!<Filter Active bit 3 */
+#define CAN_FA1R_FACT4 0x00000010U /*!<Filter Active bit 4 */
+#define CAN_FA1R_FACT5 0x00000020U /*!<Filter Active bit 5 */
+#define CAN_FA1R_FACT6 0x00000040U /*!<Filter Active bit 6 */
+#define CAN_FA1R_FACT7 0x00000080U /*!<Filter Active bit 7 */
+#define CAN_FA1R_FACT8 0x00000100U /*!<Filter Active bit 8 */
+#define CAN_FA1R_FACT9 0x00000200U /*!<Filter Active bit 9 */
+#define CAN_FA1R_FACT10 0x00000400U /*!<Filter Active bit 10 */
+#define CAN_FA1R_FACT11 0x00000800U /*!<Filter Active bit 11 */
+#define CAN_FA1R_FACT12 0x00001000U /*!<Filter Active bit 12 */
+#define CAN_FA1R_FACT13 0x00002000U /*!<Filter Active bit 13 */
+#define CAN_FA1R_FACT14 0x00004000U /*!<Filter Active bit 14 */
+#define CAN_FA1R_FACT15 0x00008000U /*!<Filter Active bit 15 */
+#define CAN_FA1R_FACT16 0x00010000U /*!<Filter Active bit 16 */
+#define CAN_FA1R_FACT17 0x00020000U /*!<Filter Active bit 17 */
+#define CAN_FA1R_FACT18 0x00040000U /*!<Filter Active bit 18 */
+#define CAN_FA1R_FACT19 0x00080000U /*!<Filter Active bit 19 */
+#define CAN_FA1R_FACT20 0x00100000U /*!<Filter Active bit 20 */
+#define CAN_FA1R_FACT21 0x00200000U /*!<Filter Active bit 21 */
+#define CAN_FA1R_FACT22 0x00400000U /*!<Filter Active bit 22 */
+#define CAN_FA1R_FACT23 0x00800000U /*!<Filter Active bit 23 */
+#define CAN_FA1R_FACT24 0x01000000U /*!<Filter Active bit 24 */
+#define CAN_FA1R_FACT25 0x02000000U /*!<Filter Active bit 25 */
+#define CAN_FA1R_FACT26 0x04000000U /*!<Filter Active bit 26 */
+#define CAN_FA1R_FACT27 0x08000000U /*!<Filter Active bit 27 */
+
+
+/******************* Bit definition for CAN_F0R1 register *******************/
+#define CAN_F0R1_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F0R1_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F0R1_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F0R1_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F0R1_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F0R1_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F0R1_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F0R1_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F0R1_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F0R1_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F0R1_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F0R1_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F0R1_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F0R1_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F0R1_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F0R1_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F0R1_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F0R1_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F0R1_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F0R1_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F0R1_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F0R1_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F0R1_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F0R1_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F0R1_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F0R1_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F0R1_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F0R1_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F0R1_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F0R1_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F0R1_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F0R1_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F1R1 register *******************/
+#define CAN_F1R1_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F1R1_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F1R1_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F1R1_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F1R1_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F1R1_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F1R1_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F1R1_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F1R1_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F1R1_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F1R1_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F1R1_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F1R1_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F1R1_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F1R1_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F1R1_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F1R1_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F1R1_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F1R1_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F1R1_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F1R1_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F1R1_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F1R1_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F1R1_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F1R1_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F1R1_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F1R1_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F1R1_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F1R1_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F1R1_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F1R1_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F1R1_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F2R1 register *******************/
+#define CAN_F2R1_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F2R1_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F2R1_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F2R1_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F2R1_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F2R1_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F2R1_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F2R1_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F2R1_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F2R1_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F2R1_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F2R1_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F2R1_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F2R1_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F2R1_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F2R1_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F2R1_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F2R1_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F2R1_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F2R1_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F2R1_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F2R1_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F2R1_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F2R1_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F2R1_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F2R1_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F2R1_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F2R1_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F2R1_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F2R1_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F2R1_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F2R1_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F3R1 register *******************/
+#define CAN_F3R1_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F3R1_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F3R1_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F3R1_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F3R1_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F3R1_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F3R1_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F3R1_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F3R1_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F3R1_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F3R1_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F3R1_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F3R1_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F3R1_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F3R1_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F3R1_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F3R1_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F3R1_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F3R1_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F3R1_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F3R1_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F3R1_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F3R1_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F3R1_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F3R1_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F3R1_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F3R1_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F3R1_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F3R1_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F3R1_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F3R1_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F3R1_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F4R1 register *******************/
+#define CAN_F4R1_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F4R1_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F4R1_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F4R1_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F4R1_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F4R1_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F4R1_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F4R1_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F4R1_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F4R1_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F4R1_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F4R1_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F4R1_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F4R1_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F4R1_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F4R1_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F4R1_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F4R1_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F4R1_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F4R1_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F4R1_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F4R1_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F4R1_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F4R1_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F4R1_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F4R1_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F4R1_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F4R1_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F4R1_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F4R1_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F4R1_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F4R1_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F5R1 register *******************/
+#define CAN_F5R1_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F5R1_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F5R1_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F5R1_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F5R1_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F5R1_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F5R1_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F5R1_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F5R1_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F5R1_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F5R1_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F5R1_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F5R1_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F5R1_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F5R1_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F5R1_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F5R1_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F5R1_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F5R1_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F5R1_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F5R1_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F5R1_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F5R1_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F5R1_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F5R1_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F5R1_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F5R1_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F5R1_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F5R1_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F5R1_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F5R1_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F5R1_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F6R1 register *******************/
+#define CAN_F6R1_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F6R1_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F6R1_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F6R1_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F6R1_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F6R1_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F6R1_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F6R1_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F6R1_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F6R1_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F6R1_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F6R1_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F6R1_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F6R1_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F6R1_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F6R1_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F6R1_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F6R1_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F6R1_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F6R1_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F6R1_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F6R1_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F6R1_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F6R1_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F6R1_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F6R1_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F6R1_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F6R1_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F6R1_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F6R1_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F6R1_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F6R1_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F7R1 register *******************/
+#define CAN_F7R1_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F7R1_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F7R1_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F7R1_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F7R1_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F7R1_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F7R1_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F7R1_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F7R1_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F7R1_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F7R1_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F7R1_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F7R1_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F7R1_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F7R1_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F7R1_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F7R1_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F7R1_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F7R1_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F7R1_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F7R1_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F7R1_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F7R1_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F7R1_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F7R1_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F7R1_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F7R1_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F7R1_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F7R1_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F7R1_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F7R1_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F7R1_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F8R1 register *******************/
+#define CAN_F8R1_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F8R1_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F8R1_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F8R1_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F8R1_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F8R1_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F8R1_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F8R1_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F8R1_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F8R1_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F8R1_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F8R1_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F8R1_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F8R1_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F8R1_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F8R1_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F8R1_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F8R1_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F8R1_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F8R1_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F8R1_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F8R1_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F8R1_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F8R1_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F8R1_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F8R1_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F8R1_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F8R1_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F8R1_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F8R1_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F8R1_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F8R1_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F9R1 register *******************/
+#define CAN_F9R1_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F9R1_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F9R1_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F9R1_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F9R1_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F9R1_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F9R1_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F9R1_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F9R1_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F9R1_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F9R1_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F9R1_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F9R1_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F9R1_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F9R1_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F9R1_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F9R1_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F9R1_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F9R1_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F9R1_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F9R1_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F9R1_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F9R1_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F9R1_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F9R1_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F9R1_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F9R1_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F9R1_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F9R1_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F9R1_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F9R1_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F9R1_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F10R1 register ******************/
+#define CAN_F10R1_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F10R1_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F10R1_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F10R1_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F10R1_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F10R1_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F10R1_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F10R1_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F10R1_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F10R1_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F10R1_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F10R1_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F10R1_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F10R1_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F10R1_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F10R1_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F10R1_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F10R1_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F10R1_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F10R1_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F10R1_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F10R1_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F10R1_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F10R1_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F10R1_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F10R1_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F10R1_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F10R1_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F10R1_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F10R1_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F10R1_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F10R1_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F11R1 register ******************/
+#define CAN_F11R1_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F11R1_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F11R1_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F11R1_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F11R1_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F11R1_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F11R1_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F11R1_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F11R1_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F11R1_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F11R1_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F11R1_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F11R1_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F11R1_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F11R1_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F11R1_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F11R1_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F11R1_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F11R1_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F11R1_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F11R1_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F11R1_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F11R1_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F11R1_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F11R1_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F11R1_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F11R1_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F11R1_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F11R1_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F11R1_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F11R1_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F11R1_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F12R1 register ******************/
+#define CAN_F12R1_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F12R1_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F12R1_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F12R1_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F12R1_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F12R1_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F12R1_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F12R1_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F12R1_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F12R1_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F12R1_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F12R1_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F12R1_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F12R1_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F12R1_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F12R1_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F12R1_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F12R1_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F12R1_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F12R1_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F12R1_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F12R1_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F12R1_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F12R1_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F12R1_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F12R1_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F12R1_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F12R1_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F12R1_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F12R1_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F12R1_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F12R1_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F13R1 register ******************/
+#define CAN_F13R1_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F13R1_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F13R1_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F13R1_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F13R1_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F13R1_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F13R1_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F13R1_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F13R1_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F13R1_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F13R1_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F13R1_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F13R1_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F13R1_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F13R1_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F13R1_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F13R1_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F13R1_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F13R1_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F13R1_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F13R1_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F13R1_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F13R1_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F13R1_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F13R1_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F13R1_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F13R1_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F13R1_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F13R1_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F13R1_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F13R1_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F13R1_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F0R2 register *******************/
+#define CAN_F0R2_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F0R2_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F0R2_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F0R2_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F0R2_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F0R2_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F0R2_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F0R2_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F0R2_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F0R2_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F0R2_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F0R2_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F0R2_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F0R2_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F0R2_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F0R2_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F0R2_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F0R2_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F0R2_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F0R2_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F0R2_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F0R2_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F0R2_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F0R2_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F0R2_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F0R2_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F0R2_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F0R2_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F0R2_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F0R2_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F0R2_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F0R2_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F1R2 register *******************/
+#define CAN_F1R2_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F1R2_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F1R2_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F1R2_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F1R2_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F1R2_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F1R2_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F1R2_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F1R2_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F1R2_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F1R2_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F1R2_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F1R2_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F1R2_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F1R2_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F1R2_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F1R2_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F1R2_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F1R2_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F1R2_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F1R2_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F1R2_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F1R2_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F1R2_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F1R2_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F1R2_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F1R2_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F1R2_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F1R2_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F1R2_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F1R2_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F1R2_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F2R2 register *******************/
+#define CAN_F2R2_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F2R2_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F2R2_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F2R2_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F2R2_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F2R2_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F2R2_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F2R2_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F2R2_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F2R2_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F2R2_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F2R2_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F2R2_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F2R2_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F2R2_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F2R2_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F2R2_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F2R2_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F2R2_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F2R2_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F2R2_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F2R2_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F2R2_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F2R2_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F2R2_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F2R2_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F2R2_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F2R2_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F2R2_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F2R2_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F2R2_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F2R2_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F3R2 register *******************/
+#define CAN_F3R2_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F3R2_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F3R2_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F3R2_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F3R2_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F3R2_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F3R2_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F3R2_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F3R2_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F3R2_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F3R2_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F3R2_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F3R2_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F3R2_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F3R2_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F3R2_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F3R2_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F3R2_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F3R2_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F3R2_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F3R2_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F3R2_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F3R2_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F3R2_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F3R2_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F3R2_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F3R2_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F3R2_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F3R2_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F3R2_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F3R2_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F3R2_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F4R2 register *******************/
+#define CAN_F4R2_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F4R2_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F4R2_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F4R2_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F4R2_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F4R2_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F4R2_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F4R2_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F4R2_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F4R2_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F4R2_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F4R2_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F4R2_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F4R2_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F4R2_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F4R2_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F4R2_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F4R2_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F4R2_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F4R2_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F4R2_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F4R2_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F4R2_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F4R2_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F4R2_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F4R2_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F4R2_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F4R2_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F4R2_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F4R2_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F4R2_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F4R2_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F5R2 register *******************/
+#define CAN_F5R2_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F5R2_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F5R2_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F5R2_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F5R2_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F5R2_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F5R2_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F5R2_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F5R2_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F5R2_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F5R2_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F5R2_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F5R2_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F5R2_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F5R2_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F5R2_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F5R2_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F5R2_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F5R2_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F5R2_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F5R2_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F5R2_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F5R2_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F5R2_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F5R2_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F5R2_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F5R2_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F5R2_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F5R2_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F5R2_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F5R2_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F5R2_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F6R2 register *******************/
+#define CAN_F6R2_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F6R2_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F6R2_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F6R2_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F6R2_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F6R2_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F6R2_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F6R2_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F6R2_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F6R2_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F6R2_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F6R2_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F6R2_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F6R2_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F6R2_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F6R2_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F6R2_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F6R2_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F6R2_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F6R2_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F6R2_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F6R2_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F6R2_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F6R2_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F6R2_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F6R2_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F6R2_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F6R2_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F6R2_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F6R2_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F6R2_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F6R2_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F7R2 register *******************/
+#define CAN_F7R2_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F7R2_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F7R2_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F7R2_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F7R2_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F7R2_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F7R2_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F7R2_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F7R2_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F7R2_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F7R2_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F7R2_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F7R2_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F7R2_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F7R2_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F7R2_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F7R2_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F7R2_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F7R2_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F7R2_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F7R2_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F7R2_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F7R2_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F7R2_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F7R2_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F7R2_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F7R2_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F7R2_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F7R2_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F7R2_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F7R2_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F7R2_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F8R2 register *******************/
+#define CAN_F8R2_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F8R2_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F8R2_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F8R2_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F8R2_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F8R2_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F8R2_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F8R2_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F8R2_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F8R2_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F8R2_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F8R2_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F8R2_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F8R2_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F8R2_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F8R2_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F8R2_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F8R2_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F8R2_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F8R2_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F8R2_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F8R2_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F8R2_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F8R2_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F8R2_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F8R2_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F8R2_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F8R2_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F8R2_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F8R2_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F8R2_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F8R2_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F9R2 register *******************/
+#define CAN_F9R2_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F9R2_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F9R2_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F9R2_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F9R2_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F9R2_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F9R2_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F9R2_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F9R2_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F9R2_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F9R2_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F9R2_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F9R2_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F9R2_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F9R2_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F9R2_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F9R2_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F9R2_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F9R2_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F9R2_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F9R2_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F9R2_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F9R2_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F9R2_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F9R2_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F9R2_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F9R2_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F9R2_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F9R2_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F9R2_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F9R2_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F9R2_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F10R2 register ******************/
+#define CAN_F10R2_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F10R2_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F10R2_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F10R2_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F10R2_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F10R2_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F10R2_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F10R2_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F10R2_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F10R2_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F10R2_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F10R2_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F10R2_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F10R2_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F10R2_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F10R2_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F10R2_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F10R2_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F10R2_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F10R2_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F10R2_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F10R2_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F10R2_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F10R2_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F10R2_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F10R2_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F10R2_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F10R2_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F10R2_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F10R2_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F10R2_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F10R2_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F11R2 register ******************/
+#define CAN_F11R2_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F11R2_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F11R2_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F11R2_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F11R2_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F11R2_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F11R2_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F11R2_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F11R2_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F11R2_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F11R2_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F11R2_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F11R2_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F11R2_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F11R2_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F11R2_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F11R2_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F11R2_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F11R2_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F11R2_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F11R2_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F11R2_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F11R2_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F11R2_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F11R2_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F11R2_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F11R2_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F11R2_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F11R2_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F11R2_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F11R2_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F11R2_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F12R2 register ******************/
+#define CAN_F12R2_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F12R2_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F12R2_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F12R2_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F12R2_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F12R2_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F12R2_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F12R2_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F12R2_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F12R2_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F12R2_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F12R2_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F12R2_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F12R2_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F12R2_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F12R2_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F12R2_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F12R2_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F12R2_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F12R2_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F12R2_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F12R2_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F12R2_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F12R2_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F12R2_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F12R2_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F12R2_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F12R2_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F12R2_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F12R2_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F12R2_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F12R2_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F13R2 register ******************/
+#define CAN_F13R2_FB0 0x00000001U /*!<Filter bit 0 */
+#define CAN_F13R2_FB1 0x00000002U /*!<Filter bit 1 */
+#define CAN_F13R2_FB2 0x00000004U /*!<Filter bit 2 */
+#define CAN_F13R2_FB3 0x00000008U /*!<Filter bit 3 */
+#define CAN_F13R2_FB4 0x00000010U /*!<Filter bit 4 */
+#define CAN_F13R2_FB5 0x00000020U /*!<Filter bit 5 */
+#define CAN_F13R2_FB6 0x00000040U /*!<Filter bit 6 */
+#define CAN_F13R2_FB7 0x00000080U /*!<Filter bit 7 */
+#define CAN_F13R2_FB8 0x00000100U /*!<Filter bit 8 */
+#define CAN_F13R2_FB9 0x00000200U /*!<Filter bit 9 */
+#define CAN_F13R2_FB10 0x00000400U /*!<Filter bit 10 */
+#define CAN_F13R2_FB11 0x00000800U /*!<Filter bit 11 */
+#define CAN_F13R2_FB12 0x00001000U /*!<Filter bit 12 */
+#define CAN_F13R2_FB13 0x00002000U /*!<Filter bit 13 */
+#define CAN_F13R2_FB14 0x00004000U /*!<Filter bit 14 */
+#define CAN_F13R2_FB15 0x00008000U /*!<Filter bit 15 */
+#define CAN_F13R2_FB16 0x00010000U /*!<Filter bit 16 */
+#define CAN_F13R2_FB17 0x00020000U /*!<Filter bit 17 */
+#define CAN_F13R2_FB18 0x00040000U /*!<Filter bit 18 */
+#define CAN_F13R2_FB19 0x00080000U /*!<Filter bit 19 */
+#define CAN_F13R2_FB20 0x00100000U /*!<Filter bit 20 */
+#define CAN_F13R2_FB21 0x00200000U /*!<Filter bit 21 */
+#define CAN_F13R2_FB22 0x00400000U /*!<Filter bit 22 */
+#define CAN_F13R2_FB23 0x00800000U /*!<Filter bit 23 */
+#define CAN_F13R2_FB24 0x01000000U /*!<Filter bit 24 */
+#define CAN_F13R2_FB25 0x02000000U /*!<Filter bit 25 */
+#define CAN_F13R2_FB26 0x04000000U /*!<Filter bit 26 */
+#define CAN_F13R2_FB27 0x08000000U /*!<Filter bit 27 */
+#define CAN_F13R2_FB28 0x10000000U /*!<Filter bit 28 */
+#define CAN_F13R2_FB29 0x20000000U /*!<Filter bit 29 */
+#define CAN_F13R2_FB30 0x40000000U /*!<Filter bit 30 */
+#define CAN_F13R2_FB31 0x80000000U /*!<Filter bit 31 */
+
+/******************************************************************************/
+/* */
+/* CRC calculation unit */
+/* */
+/******************************************************************************/
+/******************* Bit definition for CRC_DR register *********************/
+#define CRC_DR_DR 0xFFFFFFFFU /*!< Data register bits */
+
+
+/******************* Bit definition for CRC_IDR register ********************/
+#define CRC_IDR_IDR 0xFFU /*!< General-purpose 8-bit data register bits */
+
+
+/******************** Bit definition for CRC_CR register ********************/
+#define CRC_CR_RESET 0x01U /*!< RESET bit */
+
+/******************************************************************************/
+/* */
+/* Crypto Processor */
+/* */
+/******************************************************************************/
+/******************* Bits definition for CRYP_CR register ********************/
+#define CRYP_CR_ALGODIR 0x00000004U
+
+#define CRYP_CR_ALGOMODE 0x00080038U
+#define CRYP_CR_ALGOMODE_0 0x00000008U
+#define CRYP_CR_ALGOMODE_1 0x00000010U
+#define CRYP_CR_ALGOMODE_2 0x00000020U
+#define CRYP_CR_ALGOMODE_TDES_ECB 0x00000000U
+#define CRYP_CR_ALGOMODE_TDES_CBC 0x00000008U
+#define CRYP_CR_ALGOMODE_DES_ECB 0x00000010U
+#define CRYP_CR_ALGOMODE_DES_CBC 0x00000018U
+#define CRYP_CR_ALGOMODE_AES_ECB 0x00000020U
+#define CRYP_CR_ALGOMODE_AES_CBC 0x00000028U
+#define CRYP_CR_ALGOMODE_AES_CTR 0x00000030U
+#define CRYP_CR_ALGOMODE_AES_KEY 0x00000038U
+
+#define CRYP_CR_DATATYPE 0x000000C0U
+#define CRYP_CR_DATATYPE_0 0x00000040U
+#define CRYP_CR_DATATYPE_1 0x00000080U
+#define CRYP_CR_KEYSIZE 0x00000300U
+#define CRYP_CR_KEYSIZE_0 0x00000100U
+#define CRYP_CR_KEYSIZE_1 0x00000200U
+#define CRYP_CR_FFLUSH 0x00004000U
+#define CRYP_CR_CRYPEN 0x00008000U
+
+#define CRYP_CR_GCM_CCMPH 0x00030000U
+#define CRYP_CR_GCM_CCMPH_0 0x00010000U
+#define CRYP_CR_GCM_CCMPH_1 0x00020000U
+#define CRYP_CR_ALGOMODE_3 0x00080000U
+
+/****************** Bits definition for CRYP_SR register *********************/
+#define CRYP_SR_IFEM 0x00000001U
+#define CRYP_SR_IFNF 0x00000002U
+#define CRYP_SR_OFNE 0x00000004U
+#define CRYP_SR_OFFU 0x00000008U
+#define CRYP_SR_BUSY 0x00000010U
+/****************** Bits definition for CRYP_DMACR register ******************/
+#define CRYP_DMACR_DIEN 0x00000001U
+#define CRYP_DMACR_DOEN 0x00000002U
+/***************** Bits definition for CRYP_IMSCR register ******************/
+#define CRYP_IMSCR_INIM 0x00000001U
+#define CRYP_IMSCR_OUTIM 0x00000002U
+/****************** Bits definition for CRYP_RISR register *******************/
+#define CRYP_RISR_OUTRIS 0x00000001U
+#define CRYP_RISR_INRIS 0x00000002U
+/****************** Bits definition for CRYP_MISR register *******************/
+#define CRYP_MISR_INMIS 0x00000001U
+#define CRYP_MISR_OUTMIS 0x00000002U
+
+/******************************************************************************/
+/* */
+/* Digital to Analog Converter */
+/* */
+/******************************************************************************/
+/******************** Bit definition for DAC_CR register ********************/
+#define DAC_CR_EN1 0x00000001U /*!<DAC channel1 enable */
+#define DAC_CR_BOFF1 0x00000002U /*!<DAC channel1 output buffer disable */
+#define DAC_CR_TEN1 0x00000004U /*!<DAC channel1 Trigger enable */
+
+#define DAC_CR_TSEL1 0x00000038U /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */
+#define DAC_CR_TSEL1_0 0x00000008U /*!<Bit 0 */
+#define DAC_CR_TSEL1_1 0x00000010U /*!<Bit 1 */
+#define DAC_CR_TSEL1_2 0x00000020U /*!<Bit 2 */
+
+#define DAC_CR_WAVE1 0x000000C0U /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
+#define DAC_CR_WAVE1_0 0x00000040U /*!<Bit 0 */
+#define DAC_CR_WAVE1_1 0x00000080U /*!<Bit 1 */
+
+#define DAC_CR_MAMP1 0x00000F00U /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
+#define DAC_CR_MAMP1_0 0x00000100U /*!<Bit 0 */
+#define DAC_CR_MAMP1_1 0x00000200U /*!<Bit 1 */
+#define DAC_CR_MAMP1_2 0x00000400U /*!<Bit 2 */
+#define DAC_CR_MAMP1_3 0x00000800U /*!<Bit 3 */
+
+#define DAC_CR_DMAEN1 0x00001000U /*!<DAC channel1 DMA enable */
+#define DAC_CR_DMAUDRIE1 0x00002000U /*!<DAC channel1 DMA underrun interrupt enable*/
+#define DAC_CR_EN2 0x00010000U /*!<DAC channel2 enable */
+#define DAC_CR_BOFF2 0x00020000U /*!<DAC channel2 output buffer disable */
+#define DAC_CR_TEN2 0x00040000U /*!<DAC channel2 Trigger enable */
+
+#define DAC_CR_TSEL2 0x00380000U /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */
+#define DAC_CR_TSEL2_0 0x00080000U /*!<Bit 0 */
+#define DAC_CR_TSEL2_1 0x00100000U /*!<Bit 1 */
+#define DAC_CR_TSEL2_2 0x00200000U /*!<Bit 2 */
+
+#define DAC_CR_WAVE2 0x00C00000U /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
+#define DAC_CR_WAVE2_0 0x00400000U /*!<Bit 0 */
+#define DAC_CR_WAVE2_1 0x00800000U /*!<Bit 1 */
+
+#define DAC_CR_MAMP2 0x0F000000U /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
+#define DAC_CR_MAMP2_0 0x01000000U /*!<Bit 0 */
+#define DAC_CR_MAMP2_1 0x02000000U /*!<Bit 1 */
+#define DAC_CR_MAMP2_2 0x04000000U /*!<Bit 2 */
+#define DAC_CR_MAMP2_3 0x08000000U /*!<Bit 3 */
+
+#define DAC_CR_DMAEN2 0x10000000U /*!<DAC channel2 DMA enabled */
+#define DAC_CR_DMAUDRIE2 0x20000000U /*!<DAC channel2 DMA underrun interrupt enable*/
+
+/***************** Bit definition for DAC_SWTRIGR register ******************/
+#define DAC_SWTRIGR_SWTRIG1 0x01U /*!<DAC channel1 software trigger */
+#define DAC_SWTRIGR_SWTRIG2 0x02U /*!<DAC channel2 software trigger */
+
+/***************** Bit definition for DAC_DHR12R1 register ******************/
+#define DAC_DHR12R1_DACC1DHR 0x0FFFU /*!<DAC channel1 12-bit Right aligned data */
+
+/***************** Bit definition for DAC_DHR12L1 register ******************/
+#define DAC_DHR12L1_DACC1DHR 0xFFF0U /*!<DAC channel1 12-bit Left aligned data */
+
+/****************** Bit definition for DAC_DHR8R1 register ******************/
+#define DAC_DHR8R1_DACC1DHR 0xFFU /*!<DAC channel1 8-bit Right aligned data */
+
+/***************** Bit definition for DAC_DHR12R2 register ******************/
+#define DAC_DHR12R2_DACC2DHR 0x0FFFU /*!<DAC channel2 12-bit Right aligned data */
+
+/***************** Bit definition for DAC_DHR12L2 register ******************/
+#define DAC_DHR12L2_DACC2DHR 0xFFF0U /*!<DAC channel2 12-bit Left aligned data */
+
+/****************** Bit definition for DAC_DHR8R2 register ******************/
+#define DAC_DHR8R2_DACC2DHR 0xFFU /*!<DAC channel2 8-bit Right aligned data */
+
+/***************** Bit definition for DAC_DHR12RD register ******************/
+#define DAC_DHR12RD_DACC1DHR 0x00000FFFU /*!<DAC channel1 12-bit Right aligned data */
+#define DAC_DHR12RD_DACC2DHR 0x0FFF0000U /*!<DAC channel2 12-bit Right aligned data */
+
+/***************** Bit definition for DAC_DHR12LD register ******************/
+#define DAC_DHR12LD_DACC1DHR 0x0000FFF0U /*!<DAC channel1 12-bit Left aligned data */
+#define DAC_DHR12LD_DACC2DHR 0xFFF00000U /*!<DAC channel2 12-bit Left aligned data */
+
+/****************** Bit definition for DAC_DHR8RD register ******************/
+#define DAC_DHR8RD_DACC1DHR 0x00FFU /*!<DAC channel1 8-bit Right aligned data */
+#define DAC_DHR8RD_DACC2DHR 0xFF00U /*!<DAC channel2 8-bit Right aligned data */
+
+/******************* Bit definition for DAC_DOR1 register *******************/
+#define DAC_DOR1_DACC1DOR 0x0FFFU /*!<DAC channel1 data output */
+
+/******************* Bit definition for DAC_DOR2 register *******************/
+#define DAC_DOR2_DACC2DOR 0x0FFFU /*!<DAC channel2 data output */
+
+/******************** Bit definition for DAC_SR register ********************/
+#define DAC_SR_DMAUDR1 0x00002000U /*!<DAC channel1 DMA underrun flag */
+#define DAC_SR_DMAUDR2 0x20000000U /*!<DAC channel2 DMA underrun flag */
+
+/******************************************************************************/
+/* */
+/* Debug MCU */
+/* */
+/******************************************************************************/
+
+/******************************************************************************/
+/* */
+/* DCMI */
+/* */
+/******************************************************************************/
+/******************** Bits definition for DCMI_CR register ******************/
+#define DCMI_CR_CAPTURE 0x00000001U
+#define DCMI_CR_CM 0x00000002U
+#define DCMI_CR_CROP 0x00000004U
+#define DCMI_CR_JPEG 0x00000008U
+#define DCMI_CR_ESS 0x00000010U
+#define DCMI_CR_PCKPOL 0x00000020U
+#define DCMI_CR_HSPOL 0x00000040U
+#define DCMI_CR_VSPOL 0x00000080U
+#define DCMI_CR_FCRC_0 0x00000100U
+#define DCMI_CR_FCRC_1 0x00000200U
+#define DCMI_CR_EDM_0 0x00000400U
+#define DCMI_CR_EDM_1 0x00000800U
+#define DCMI_CR_OUTEN 0x00002000U
+#define DCMI_CR_ENABLE 0x00004000U
+#define DCMI_CR_BSM_0 0x00010000U
+#define DCMI_CR_BSM_1 0x00020000U
+#define DCMI_CR_OEBS 0x00040000U
+#define DCMI_CR_LSM 0x00080000U
+#define DCMI_CR_OELS 0x00100000U
+
+/******************** Bits definition for DCMI_SR register ******************/
+#define DCMI_SR_HSYNC 0x00000001U
+#define DCMI_SR_VSYNC 0x00000002U
+#define DCMI_SR_FNE 0x00000004U
+
+/******************** Bits definition for DCMI_RIS register *****************/
+#define DCMI_RIS_FRAME_RIS 0x00000001U
+#define DCMI_RIS_OVR_RIS 0x00000002U
+#define DCMI_RIS_ERR_RIS 0x00000004U
+#define DCMI_RIS_VSYNC_RIS 0x00000008U
+#define DCMI_RIS_LINE_RIS 0x00000010U
+/* Legacy defines */
+#define DCMI_RISR_FRAME_RIS DCMI_RIS_FRAME_RIS
+#define DCMI_RISR_OVR_RIS DCMI_RIS_OVR_RIS
+#define DCMI_RISR_ERR_RIS DCMI_RIS_ERR_RIS
+#define DCMI_RISR_VSYNC_RIS DCMI_RIS_VSYNC_RIS
+#define DCMI_RISR_LINE_RIS DCMI_RIS_LINE_RIS
+#define DCMI_RISR_OVF_RIS DCMI_RIS_OVR_RIS
+
+/******************** Bits definition for DCMI_IER register *****************/
+#define DCMI_IER_FRAME_IE 0x00000001U
+#define DCMI_IER_OVR_IE 0x00000002U
+#define DCMI_IER_ERR_IE 0x00000004U
+#define DCMI_IER_VSYNC_IE 0x00000008U
+#define DCMI_IER_LINE_IE 0x00000010U
+/* Legacy defines */
+#define DCMI_IER_OVF_IE DCMI_IER_OVR_IE
+
+/******************** Bits definition for DCMI_MIS register *****************/
+#define DCMI_MIS_FRAME_MIS 0x00000001U
+#define DCMI_MIS_OVR_MIS 0x00000002U
+#define DCMI_MIS_ERR_MIS 0x00000004U
+#define DCMI_MIS_VSYNC_MIS 0x00000008U
+#define DCMI_MIS_LINE_MIS 0x00000010U
+
+/* Legacy defines */
+#define DCMI_MISR_FRAME_MIS DCMI_MIS_FRAME_MIS
+#define DCMI_MISR_OVF_MIS DCMI_MIS_OVR_MIS
+#define DCMI_MISR_ERR_MIS DCMI_MIS_ERR_MIS
+#define DCMI_MISR_VSYNC_MIS DCMI_MIS_VSYNC_MIS
+#define DCMI_MISR_LINE_MIS DCMI_MIS_LINE_MIS
+
+/******************** Bits definition for DCMI_ICR register *****************/
+#define DCMI_ICR_FRAME_ISC 0x00000001U
+#define DCMI_ICR_OVR_ISC 0x00000002U
+#define DCMI_ICR_ERR_ISC 0x00000004U
+#define DCMI_ICR_VSYNC_ISC 0x00000008U
+#define DCMI_ICR_LINE_ISC 0x00000010U
+
+/* Legacy defines */
+#define DCMI_ICR_OVF_ISC DCMI_ICR_OVR_ISC
+
+/******************** Bits definition for DCMI_ESCR register ******************/
+#define DCMI_ESCR_FSC 0x000000FFU
+#define DCMI_ESCR_LSC 0x0000FF00U
+#define DCMI_ESCR_LEC 0x00FF0000U
+#define DCMI_ESCR_FEC 0xFF000000U
+
+/******************** Bits definition for DCMI_ESUR register ******************/
+#define DCMI_ESUR_FSU 0x000000FFU
+#define DCMI_ESUR_LSU 0x0000FF00U
+#define DCMI_ESUR_LEU 0x00FF0000U
+#define DCMI_ESUR_FEU 0xFF000000U
+
+/******************** Bits definition for DCMI_CWSTRT register ******************/
+#define DCMI_CWSTRT_HOFFCNT 0x00003FFFU
+#define DCMI_CWSTRT_VST 0x1FFF0000U
+
+/******************** Bits definition for DCMI_CWSIZE register ******************/
+#define DCMI_CWSIZE_CAPCNT 0x00003FFFU
+#define DCMI_CWSIZE_VLINE 0x3FFF0000U
+
+/******************** Bits definition for DCMI_DR register *********************/
+#define DCMI_DR_BYTE0 0x000000FFU
+#define DCMI_DR_BYTE1 0x0000FF00U
+#define DCMI_DR_BYTE2 0x00FF0000U
+#define DCMI_DR_BYTE3 0xFF000000U
+
+/******************************************************************************/
+/* */
+/* DMA Controller */
+/* */
+/******************************************************************************/
+/******************** Bits definition for DMA_SxCR register *****************/
+#define DMA_SxCR_CHSEL 0x0E000000U
+#define DMA_SxCR_CHSEL_0 0x02000000U
+#define DMA_SxCR_CHSEL_1 0x04000000U
+#define DMA_SxCR_CHSEL_2 0x08000000U
+#define DMA_SxCR_MBURST 0x01800000U
+#define DMA_SxCR_MBURST_0 0x00800000U
+#define DMA_SxCR_MBURST_1 0x01000000U
+#define DMA_SxCR_PBURST 0x00600000U
+#define DMA_SxCR_PBURST_0 0x00200000U
+#define DMA_SxCR_PBURST_1 0x00400000U
+#define DMA_SxCR_CT 0x00080000U
+#define DMA_SxCR_DBM 0x00040000U
+#define DMA_SxCR_PL 0x00030000U
+#define DMA_SxCR_PL_0 0x00010000U
+#define DMA_SxCR_PL_1 0x00020000U
+#define DMA_SxCR_PINCOS 0x00008000U
+#define DMA_SxCR_MSIZE 0x00006000U
+#define DMA_SxCR_MSIZE_0 0x00002000U
+#define DMA_SxCR_MSIZE_1 0x00004000U
+#define DMA_SxCR_PSIZE 0x00001800U
+#define DMA_SxCR_PSIZE_0 0x00000800U
+#define DMA_SxCR_PSIZE_1 0x00001000U
+#define DMA_SxCR_MINC 0x00000400U
+#define DMA_SxCR_PINC 0x00000200U
+#define DMA_SxCR_CIRC 0x00000100U
+#define DMA_SxCR_DIR 0x000000C0U
+#define DMA_SxCR_DIR_0 0x00000040U
+#define DMA_SxCR_DIR_1 0x00000080U
+#define DMA_SxCR_PFCTRL 0x00000020U
+#define DMA_SxCR_TCIE 0x00000010U
+#define DMA_SxCR_HTIE 0x00000008U
+#define DMA_SxCR_TEIE 0x00000004U
+#define DMA_SxCR_DMEIE 0x00000002U
+#define DMA_SxCR_EN 0x00000001U
+
+/* Legacy defines */
+#define DMA_SxCR_ACK 0x00100000U
+
+/******************** Bits definition for DMA_SxCNDTR register **************/
+#define DMA_SxNDT 0x0000FFFFU
+#define DMA_SxNDT_0 0x00000001U
+#define DMA_SxNDT_1 0x00000002U
+#define DMA_SxNDT_2 0x00000004U
+#define DMA_SxNDT_3 0x00000008U
+#define DMA_SxNDT_4 0x00000010U
+#define DMA_SxNDT_5 0x00000020U
+#define DMA_SxNDT_6 0x00000040U
+#define DMA_SxNDT_7 0x00000080U
+#define DMA_SxNDT_8 0x00000100U
+#define DMA_SxNDT_9 0x00000200U
+#define DMA_SxNDT_10 0x00000400U
+#define DMA_SxNDT_11 0x00000800U
+#define DMA_SxNDT_12 0x00001000U
+#define DMA_SxNDT_13 0x00002000U
+#define DMA_SxNDT_14 0x00004000U
+#define DMA_SxNDT_15 0x00008000U
+
+/******************** Bits definition for DMA_SxFCR register ****************/
+#define DMA_SxFCR_FEIE 0x00000080U
+#define DMA_SxFCR_FS 0x00000038U
+#define DMA_SxFCR_FS_0 0x00000008U
+#define DMA_SxFCR_FS_1 0x00000010U
+#define DMA_SxFCR_FS_2 0x00000020U
+#define DMA_SxFCR_DMDIS 0x00000004U
+#define DMA_SxFCR_FTH 0x00000003U
+#define DMA_SxFCR_FTH_0 0x00000001U
+#define DMA_SxFCR_FTH_1 0x00000002U
+
+/******************** Bits definition for DMA_LISR register *****************/
+#define DMA_LISR_TCIF3 0x08000000U
+#define DMA_LISR_HTIF3 0x04000000U
+#define DMA_LISR_TEIF3 0x02000000U
+#define DMA_LISR_DMEIF3 0x01000000U
+#define DMA_LISR_FEIF3 0x00400000U
+#define DMA_LISR_TCIF2 0x00200000U
+#define DMA_LISR_HTIF2 0x00100000U
+#define DMA_LISR_TEIF2 0x00080000U
+#define DMA_LISR_DMEIF2 0x00040000U
+#define DMA_LISR_FEIF2 0x00010000U
+#define DMA_LISR_TCIF1 0x00000800U
+#define DMA_LISR_HTIF1 0x00000400U
+#define DMA_LISR_TEIF1 0x00000200U
+#define DMA_LISR_DMEIF1 0x00000100U
+#define DMA_LISR_FEIF1 0x00000040U
+#define DMA_LISR_TCIF0 0x00000020U
+#define DMA_LISR_HTIF0 0x00000010U
+#define DMA_LISR_TEIF0 0x00000008U
+#define DMA_LISR_DMEIF0 0x00000004U
+#define DMA_LISR_FEIF0 0x00000001U
+
+/******************** Bits definition for DMA_HISR register *****************/
+#define DMA_HISR_TCIF7 0x08000000U
+#define DMA_HISR_HTIF7 0x04000000U
+#define DMA_HISR_TEIF7 0x02000000U
+#define DMA_HISR_DMEIF7 0x01000000U
+#define DMA_HISR_FEIF7 0x00400000U
+#define DMA_HISR_TCIF6 0x00200000U
+#define DMA_HISR_HTIF6 0x00100000U
+#define DMA_HISR_TEIF6 0x00080000U
+#define DMA_HISR_DMEIF6 0x00040000U
+#define DMA_HISR_FEIF6 0x00010000U
+#define DMA_HISR_TCIF5 0x00000800U
+#define DMA_HISR_HTIF5 0x00000400U
+#define DMA_HISR_TEIF5 0x00000200U
+#define DMA_HISR_DMEIF5 0x00000100U
+#define DMA_HISR_FEIF5 0x00000040U
+#define DMA_HISR_TCIF4 0x00000020U
+#define DMA_HISR_HTIF4 0x00000010U
+#define DMA_HISR_TEIF4 0x00000008U
+#define DMA_HISR_DMEIF4 0x00000004U
+#define DMA_HISR_FEIF4 0x00000001U
+
+/******************** Bits definition for DMA_LIFCR register ****************/
+#define DMA_LIFCR_CTCIF3 0x08000000U
+#define DMA_LIFCR_CHTIF3 0x04000000U
+#define DMA_LIFCR_CTEIF3 0x02000000U
+#define DMA_LIFCR_CDMEIF3 0x01000000U
+#define DMA_LIFCR_CFEIF3 0x00400000U
+#define DMA_LIFCR_CTCIF2 0x00200000U
+#define DMA_LIFCR_CHTIF2 0x00100000U
+#define DMA_LIFCR_CTEIF2 0x00080000U
+#define DMA_LIFCR_CDMEIF2 0x00040000U
+#define DMA_LIFCR_CFEIF2 0x00010000U
+#define DMA_LIFCR_CTCIF1 0x00000800U
+#define DMA_LIFCR_CHTIF1 0x00000400U
+#define DMA_LIFCR_CTEIF1 0x00000200U
+#define DMA_LIFCR_CDMEIF1 0x00000100U
+#define DMA_LIFCR_CFEIF1 0x00000040U
+#define DMA_LIFCR_CTCIF0 0x00000020U
+#define DMA_LIFCR_CHTIF0 0x00000010U
+#define DMA_LIFCR_CTEIF0 0x00000008U
+#define DMA_LIFCR_CDMEIF0 0x00000004U
+#define DMA_LIFCR_CFEIF0 0x00000001U
+
+/******************** Bits definition for DMA_HIFCR register ****************/
+#define DMA_HIFCR_CTCIF7 0x08000000U
+#define DMA_HIFCR_CHTIF7 0x04000000U
+#define DMA_HIFCR_CTEIF7 0x02000000U
+#define DMA_HIFCR_CDMEIF7 0x01000000U
+#define DMA_HIFCR_CFEIF7 0x00400000U
+#define DMA_HIFCR_CTCIF6 0x00200000U
+#define DMA_HIFCR_CHTIF6 0x00100000U
+#define DMA_HIFCR_CTEIF6 0x00080000U
+#define DMA_HIFCR_CDMEIF6 0x00040000U
+#define DMA_HIFCR_CFEIF6 0x00010000U
+#define DMA_HIFCR_CTCIF5 0x00000800U
+#define DMA_HIFCR_CHTIF5 0x00000400U
+#define DMA_HIFCR_CTEIF5 0x00000200U
+#define DMA_HIFCR_CDMEIF5 0x00000100U
+#define DMA_HIFCR_CFEIF5 0x00000040U
+#define DMA_HIFCR_CTCIF4 0x00000020U
+#define DMA_HIFCR_CHTIF4 0x00000010U
+#define DMA_HIFCR_CTEIF4 0x00000008U
+#define DMA_HIFCR_CDMEIF4 0x00000004U
+#define DMA_HIFCR_CFEIF4 0x00000001U
+
+
+/******************************************************************************/
+/* */
+/* AHB Master DMA2D Controller (DMA2D) */
+/* */
+/******************************************************************************/
+
+/******************** Bit definition for DMA2D_CR register ******************/
+
+#define DMA2D_CR_START 0x00000001U /*!< Start transfer */
+#define DMA2D_CR_SUSP 0x00000002U /*!< Suspend transfer */
+#define DMA2D_CR_ABORT 0x00000004U /*!< Abort transfer */
+#define DMA2D_CR_TEIE 0x00000100U /*!< Transfer Error Interrupt Enable */
+#define DMA2D_CR_TCIE 0x00000200U /*!< Transfer Complete Interrupt Enable */
+#define DMA2D_CR_TWIE 0x00000400U /*!< Transfer Watermark Interrupt Enable */
+#define DMA2D_CR_CAEIE 0x00000800U /*!< CLUT Access Error Interrupt Enable */
+#define DMA2D_CR_CTCIE 0x00001000U /*!< CLUT Transfer Complete Interrupt Enable */
+#define DMA2D_CR_CEIE 0x00002000U /*!< Configuration Error Interrupt Enable */
+#define DMA2D_CR_MODE 0x00030000U /*!< DMA2D Mode[1:0] */
+#define DMA2D_CR_MODE_0 0x00010000U /*!< DMA2D Mode bit 0 */
+#define DMA2D_CR_MODE_1 0x00020000U /*!< DMA2D Mode bit 1 */
+
+/******************** Bit definition for DMA2D_ISR register *****************/
+
+#define DMA2D_ISR_TEIF 0x00000001U /*!< Transfer Error Interrupt Flag */
+#define DMA2D_ISR_TCIF 0x00000002U /*!< Transfer Complete Interrupt Flag */
+#define DMA2D_ISR_TWIF 0x00000004U /*!< Transfer Watermark Interrupt Flag */
+#define DMA2D_ISR_CAEIF 0x00000008U /*!< CLUT Access Error Interrupt Flag */
+#define DMA2D_ISR_CTCIF 0x00000010U /*!< CLUT Transfer Complete Interrupt Flag */
+#define DMA2D_ISR_CEIF 0x00000020U /*!< Configuration Error Interrupt Flag */
+
+/******************** Bit definition for DMA2D_IFCR register ****************/
+
+#define DMA2D_IFCR_CTEIF 0x00000001U /*!< Clears Transfer Error Interrupt Flag */
+#define DMA2D_IFCR_CTCIF 0x00000002U /*!< Clears Transfer Complete Interrupt Flag */
+#define DMA2D_IFCR_CTWIF 0x00000004U /*!< Clears Transfer Watermark Interrupt Flag */
+#define DMA2D_IFCR_CAECIF 0x00000008U /*!< Clears CLUT Access Error Interrupt Flag */
+#define DMA2D_IFCR_CCTCIF 0x00000010U /*!< Clears CLUT Transfer Complete Interrupt Flag */
+#define DMA2D_IFCR_CCEIF 0x00000020U /*!< Clears Configuration Error Interrupt Flag */
+
+/* Legacy defines */
+#define DMA2D_IFSR_CTEIF DMA2D_IFCR_CTEIF /*!< Clears Transfer Error Interrupt Flag */
+#define DMA2D_IFSR_CTCIF DMA2D_IFCR_CTCIF /*!< Clears Transfer Complete Interrupt Flag */
+#define DMA2D_IFSR_CTWIF DMA2D_IFCR_CTWIF /*!< Clears Transfer Watermark Interrupt Flag */
+#define DMA2D_IFSR_CCAEIF DMA2D_IFCR_CAECIF /*!< Clears CLUT Access Error Interrupt Flag */
+#define DMA2D_IFSR_CCTCIF DMA2D_IFCR_CCTCIF /*!< Clears CLUT Transfer Complete Interrupt Flag */
+#define DMA2D_IFSR_CCEIF DMA2D_IFCR_CCEIF /*!< Clears Configuration Error Interrupt Flag */
+
+/******************** Bit definition for DMA2D_FGMAR register ***************/
+
+#define DMA2D_FGMAR_MA 0xFFFFFFFFU /*!< Memory Address */
+
+/******************** Bit definition for DMA2D_FGOR register ****************/
+
+#define DMA2D_FGOR_LO 0x00003FFFU /*!< Line Offset */
+
+/******************** Bit definition for DMA2D_BGMAR register ***************/
+
+#define DMA2D_BGMAR_MA 0xFFFFFFFFU /*!< Memory Address */
+
+/******************** Bit definition for DMA2D_BGOR register ****************/
+
+#define DMA2D_BGOR_LO 0x00003FFFU /*!< Line Offset */
+
+/******************** Bit definition for DMA2D_FGPFCCR register *************/
+
+#define DMA2D_FGPFCCR_CM 0x0000000FU /*!< Input color mode CM[3:0] */
+#define DMA2D_FGPFCCR_CM_0 0x00000001U /*!< Input color mode CM bit 0 */
+#define DMA2D_FGPFCCR_CM_1 0x00000002U /*!< Input color mode CM bit 1 */
+#define DMA2D_FGPFCCR_CM_2 0x00000004U /*!< Input color mode CM bit 2 */
+#define DMA2D_FGPFCCR_CM_3 0x00000008U /*!< Input color mode CM bit 3 */
+#define DMA2D_FGPFCCR_CCM 0x00000010U /*!< CLUT Color mode */
+#define DMA2D_FGPFCCR_START 0x00000020U /*!< Start */
+#define DMA2D_FGPFCCR_CS 0x0000FF00U /*!< CLUT size */
+#define DMA2D_FGPFCCR_AM 0x00030000U /*!< Alpha mode AM[1:0] */
+#define DMA2D_FGPFCCR_AM_0 0x00010000U /*!< Alpha mode AM bit 0 */
+#define DMA2D_FGPFCCR_AM_1 0x00020000U /*!< Alpha mode AM bit 1 */
+#define DMA2D_FGPFCCR_ALPHA 0xFF000000U /*!< Alpha value */
+
+/******************** Bit definition for DMA2D_FGCOLR register **************/
+
+#define DMA2D_FGCOLR_BLUE 0x000000FFU /*!< Blue Value */
+#define DMA2D_FGCOLR_GREEN 0x0000FF00U /*!< Green Value */
+#define DMA2D_FGCOLR_RED 0x00FF0000U /*!< Red Value */
+
+/******************** Bit definition for DMA2D_BGPFCCR register *************/
+
+#define DMA2D_BGPFCCR_CM 0x0000000FU /*!< Input color mode CM[3:0] */
+#define DMA2D_BGPFCCR_CM_0 0x00000001U /*!< Input color mode CM bit 0 */
+#define DMA2D_BGPFCCR_CM_1 0x00000002U /*!< Input color mode CM bit 1 */
+#define DMA2D_BGPFCCR_CM_2 0x00000004U /*!< Input color mode CM bit 2 */
+#define DMA2D_FGPFCCR_CM_3 0x00000008U /*!< Input color mode CM bit 3 */
+#define DMA2D_BGPFCCR_CCM 0x00000010U /*!< CLUT Color mode */
+#define DMA2D_BGPFCCR_START 0x00000020U /*!< Start */
+#define DMA2D_BGPFCCR_CS 0x0000FF00U /*!< CLUT size */
+#define DMA2D_BGPFCCR_AM 0x00030000U /*!< Alpha mode AM[1:0] */
+#define DMA2D_BGPFCCR_AM_0 0x00010000U /*!< Alpha mode AM bit 0 */
+#define DMA2D_BGPFCCR_AM_1 0x00020000U /*!< Alpha mode AM bit 1 */
+#define DMA2D_BGPFCCR_ALPHA 0xFF000000U /*!< background Input Alpha value */
+
+/******************** Bit definition for DMA2D_BGCOLR register **************/
+
+#define DMA2D_BGCOLR_BLUE 0x000000FFU /*!< Blue Value */
+#define DMA2D_BGCOLR_GREEN 0x0000FF00U /*!< Green Value */
+#define DMA2D_BGCOLR_RED 0x00FF0000U /*!< Red Value */
+
+/******************** Bit definition for DMA2D_FGCMAR register **************/
+
+#define DMA2D_FGCMAR_MA 0xFFFFFFFFU /*!< Memory Address */
+
+/******************** Bit definition for DMA2D_BGCMAR register **************/
+
+#define DMA2D_BGCMAR_MA 0xFFFFFFFFU /*!< Memory Address */
+
+/******************** Bit definition for DMA2D_OPFCCR register **************/
+
+#define DMA2D_OPFCCR_CM 0x00000007U /*!< Color mode CM[2:0] */
+#define DMA2D_OPFCCR_CM_0 0x00000001U /*!< Color mode CM bit 0 */
+#define DMA2D_OPFCCR_CM_1 0x00000002U /*!< Color mode CM bit 1 */
+#define DMA2D_OPFCCR_CM_2 0x00000004U /*!< Color mode CM bit 2 */
+
+/******************** Bit definition for DMA2D_OCOLR register ***************/
+
+/*!<Mode_ARGB8888/RGB888 */
+
+#define DMA2D_OCOLR_BLUE_1 0x000000FFU /*!< BLUE Value */
+#define DMA2D_OCOLR_GREEN_1 0x0000FF00U /*!< GREEN Value */
+#define DMA2D_OCOLR_RED_1 0x00FF0000U /*!< Red Value */
+#define DMA2D_OCOLR_ALPHA_1 0xFF000000U /*!< Alpha Channel Value */
+
+/*!<Mode_RGB565 */
+#define DMA2D_OCOLR_BLUE_2 0x0000001FU /*!< BLUE Value */
+#define DMA2D_OCOLR_GREEN_2 0x000007E0U /*!< GREEN Value */
+#define DMA2D_OCOLR_RED_2 0x0000F800U /*!< Red Value */
+
+/*!<Mode_ARGB1555 */
+#define DMA2D_OCOLR_BLUE_3 0x0000001FU /*!< BLUE Value */
+#define DMA2D_OCOLR_GREEN_3 0x000003E0U /*!< GREEN Value */
+#define DMA2D_OCOLR_RED_3 0x00007C00U /*!< Red Value */
+#define DMA2D_OCOLR_ALPHA_3 0x00008000U /*!< Alpha Channel Value */
+
+/*!<Mode_ARGB4444 */
+#define DMA2D_OCOLR_BLUE_4 0x0000000FU /*!< BLUE Value */
+#define DMA2D_OCOLR_GREEN_4 0x000000F0U /*!< GREEN Value */
+#define DMA2D_OCOLR_RED_4 0x00000F00U /*!< Red Value */
+#define DMA2D_OCOLR_ALPHA_4 0x0000F000U /*!< Alpha Channel Value */
+
+/******************** Bit definition for DMA2D_OMAR register ****************/
+
+#define DMA2D_OMAR_MA 0xFFFFFFFFU /*!< Memory Address */
+
+/******************** Bit definition for DMA2D_OOR register *****************/
+
+#define DMA2D_OOR_LO 0x00003FFFU /*!< Line Offset */
+
+/******************** Bit definition for DMA2D_NLR register *****************/
+
+#define DMA2D_NLR_NL 0x0000FFFFU /*!< Number of Lines */
+#define DMA2D_NLR_PL 0x3FFF0000U /*!< Pixel per Lines */
+
+/******************** Bit definition for DMA2D_LWR register *****************/
+
+#define DMA2D_LWR_LW 0x0000FFFFU /*!< Line Watermark */
+
+/******************** Bit definition for DMA2D_AMTCR register ***************/
+
+#define DMA2D_AMTCR_EN 0x00000001U /*!< Enable */
+#define DMA2D_AMTCR_DT 0x0000FF00U /*!< Dead Time */
+
+/******************** Bit definition for DMA2D_FGCLUT register **************/
+
+/******************** Bit definition for DMA2D_BGCLUT register **************/
+
+
+/******************************************************************************/
+/* */
+/* Display Serial Interface (DSI) */
+/* */
+/******************************************************************************/
+/******************* Bit definition for DSI_VR register *****************/
+#define DSI_VR 0x3133302AU /*!< DSI Host Version */
+
+/******************* Bit definition for DSI_CR register *****************/
+#define DSI_CR_EN 0x00000001U /*!< DSI Host power up and reset */
+
+/******************* Bit definition for DSI_CCR register ****************/
+#define DSI_CCR_TXECKDIV 0x000000FFU /*!< TX Escape Clock Division */
+#define DSI_CCR_TXECKDIV0 0x00000001U
+#define DSI_CCR_TXECKDIV1 0x00000002U
+#define DSI_CCR_TXECKDIV2 0x00000004U
+#define DSI_CCR_TXECKDIV3 0x00000008U
+#define DSI_CCR_TXECKDIV4 0x00000010U
+#define DSI_CCR_TXECKDIV5 0x00000020U
+#define DSI_CCR_TXECKDIV6 0x00000040U
+#define DSI_CCR_TXECKDIV7 0x00000080U
+
+#define DSI_CCR_TOCKDIV 0x0000FF00U /*!< Timeout Clock Division */
+#define DSI_CCR_TOCKDIV0 0x00000100U
+#define DSI_CCR_TOCKDIV1 0x00000200U
+#define DSI_CCR_TOCKDIV2 0x00000400U
+#define DSI_CCR_TOCKDIV3 0x00000800U
+#define DSI_CCR_TOCKDIV4 0x00001000U
+#define DSI_CCR_TOCKDIV5 0x00002000U
+#define DSI_CCR_TOCKDIV6 0x00004000U
+#define DSI_CCR_TOCKDIV7 0x00008000U
+
+/******************* Bit definition for DSI_LVCIDR register *************/
+#define DSI_LVCIDR_VCID 0x00000003U /*!< Virtual Channel ID */
+#define DSI_LVCIDR_VCID0 0x00000001U
+#define DSI_LVCIDR_VCID1 0x00000002U
+
+/******************* Bit definition for DSI_LCOLCR register *************/
+#define DSI_LCOLCR_COLC 0x0000000FU /*!< Color Coding */
+#define DSI_LCOLCR_COLC0 0x00000001U
+#define DSI_LCOLCR_COLC1 0x00000020U
+#define DSI_LCOLCR_COLC2 0x00000040U
+#define DSI_LCOLCR_COLC3 0x00000080U
+
+#define DSI_LCOLCR_LPE 0x00000100U /*!< Loosly Packet Enable */
+
+/******************* Bit definition for DSI_LPCR register ***************/
+#define DSI_LPCR_DEP 0x00000001U /*!< Data Enable Polarity */
+#define DSI_LPCR_VSP 0x00000002U /*!< VSYNC Polarity */
+#define DSI_LPCR_HSP 0x00000004U /*!< HSYNC Polarity */
+
+/******************* Bit definition for DSI_LPMCR register **************/
+#define DSI_LPMCR_VLPSIZE 0x000000FFU /*!< VACT Largest Packet Size */
+#define DSI_LPMCR_VLPSIZE0 0x00000001U
+#define DSI_LPMCR_VLPSIZE1 0x00000002U
+#define DSI_LPMCR_VLPSIZE2 0x00000004U
+#define DSI_LPMCR_VLPSIZE3 0x00000008U
+#define DSI_LPMCR_VLPSIZE4 0x00000010U
+#define DSI_LPMCR_VLPSIZE5 0x00000020U
+#define DSI_LPMCR_VLPSIZE6 0x00000040U
+#define DSI_LPMCR_VLPSIZE7 0x00000080U
+
+#define DSI_LPMCR_LPSIZE 0x00FF0000U /*!< Largest Packet Size */
+#define DSI_LPMCR_LPSIZE0 0x00010000U
+#define DSI_LPMCR_LPSIZE1 0x00020000U
+#define DSI_LPMCR_LPSIZE2 0x00040000U
+#define DSI_LPMCR_LPSIZE3 0x00080000U
+#define DSI_LPMCR_LPSIZE4 0x00100000U
+#define DSI_LPMCR_LPSIZE5 0x00200000U
+#define DSI_LPMCR_LPSIZE6 0x00400000U
+#define DSI_LPMCR_LPSIZE7 0x00800000U
+
+/******************* Bit definition for DSI_PCR register ****************/
+#define DSI_PCR_ETTXE 0x00000001U /*!< EoTp Transmission Enable */
+#define DSI_PCR_ETRXE 0x00000002U /*!< EoTp Reception Enable */
+#define DSI_PCR_BTAE 0x00000004U /*!< Bus Turn Around Enable */
+#define DSI_PCR_ECCRXE 0x00000008U /*!< ECC Reception Enable */
+#define DSI_PCR_CRCRXE 0x00000010U /*!< CRC Reception Enable */
+
+/******************* Bit definition for DSI_GVCIDR register *************/
+#define DSI_GVCIDR_VCID 0x00000003U /*!< Virtual Channel ID */
+#define DSI_GVCIDR_VCID0 0x00000001U
+#define DSI_GVCIDR_VCID1 0x00000002U
+
+/******************* Bit definition for DSI_MCR register ****************/
+#define DSI_MCR_CMDM 0x00000001U /*!< Command Mode */
+
+/******************* Bit definition for DSI_VMCR register ***************/
+#define DSI_VMCR_VMT 0x00000003U /*!< Video Mode Type */
+#define DSI_VMCR_VMT0 0x00000001U
+#define DSI_VMCR_VMT1 0x00000002U
+
+#define DSI_VMCR_LPVSAE 0x00000100U /*!< Low-Power Vertical Sync Active Enable */
+#define DSI_VMCR_LPVBPE 0x00000200U /*!< Low-power Vertical Back-Porch Enable */
+#define DSI_VMCR_LPVFPE 0x00000400U /*!< Low-power Vertical Front-porch Enable */
+#define DSI_VMCR_LPVAE 0x00000800U /*!< Low-Power Vertical Active Enable */
+#define DSI_VMCR_LPHBPE 0x00001000U /*!< Low-Power Horizontal Back-Porch Enable */
+#define DSI_VMCR_LPHFPE 0x00002000U /*!< Low-Power Horizontal Front-Porch Enable */
+#define DSI_VMCR_FBTAAE 0x00004000U /*!< Frame Bus-Turn-Around Acknowledge Enable */
+#define DSI_VMCR_LPCE 0x00008000U /*!< Low-Power Command Enable */
+#define DSI_VMCR_PGE 0x00010000U /*!< Pattern Generator Enable */
+#define DSI_VMCR_PGM 0x00100000U /*!< Pattern Generator Mode */
+#define DSI_VMCR_PGO 0x01000000U /*!< Pattern Generator Orientation */
+
+/******************* Bit definition for DSI_VPCR register ***************/
+#define DSI_VPCR_VPSIZE 0x00003FFFU /*!< Video Packet Size */
+#define DSI_VPCR_VPSIZE0 0x00000001U
+#define DSI_VPCR_VPSIZE1 0x00000002U
+#define DSI_VPCR_VPSIZE2 0x00000004U
+#define DSI_VPCR_VPSIZE3 0x00000008U
+#define DSI_VPCR_VPSIZE4 0x00000010U
+#define DSI_VPCR_VPSIZE5 0x00000020U
+#define DSI_VPCR_VPSIZE6 0x00000040U
+#define DSI_VPCR_VPSIZE7 0x00000080U
+#define DSI_VPCR_VPSIZE8 0x00000100U
+#define DSI_VPCR_VPSIZE9 0x00000200U
+#define DSI_VPCR_VPSIZE10 0x00000400U
+#define DSI_VPCR_VPSIZE11 0x00000800U
+#define DSI_VPCR_VPSIZE12 0x00001000U
+#define DSI_VPCR_VPSIZE13 0x00002000U
+
+/******************* Bit definition for DSI_VCCR register ***************/
+#define DSI_VCCR_NUMC 0x00001FFFU /*!< Number of Chunks */
+#define DSI_VCCR_NUMC0 0x00000001U
+#define DSI_VCCR_NUMC1 0x00000002U
+#define DSI_VCCR_NUMC2 0x00000004U
+#define DSI_VCCR_NUMC3 0x00000008U
+#define DSI_VCCR_NUMC4 0x00000010U
+#define DSI_VCCR_NUMC5 0x00000020U
+#define DSI_VCCR_NUMC6 0x00000040U
+#define DSI_VCCR_NUMC7 0x00000080U
+#define DSI_VCCR_NUMC8 0x00000100U
+#define DSI_VCCR_NUMC9 0x00000200U
+#define DSI_VCCR_NUMC10 0x00000400U
+#define DSI_VCCR_NUMC11 0x00000800U
+#define DSI_VCCR_NUMC12 0x00001000U
+
+/******************* Bit definition for DSI_VNPCR register **************/
+#define DSI_VNPCR_NPSIZE 0x00001FFFU /*!< Null Packet Size */
+#define DSI_VNPCR_NPSIZE0 0x00000001U
+#define DSI_VNPCR_NPSIZE1 0x00000002U
+#define DSI_VNPCR_NPSIZE2 0x00000004U
+#define DSI_VNPCR_NPSIZE3 0x00000008U
+#define DSI_VNPCR_NPSIZE4 0x00000010U
+#define DSI_VNPCR_NPSIZE5 0x00000020U
+#define DSI_VNPCR_NPSIZE6 0x00000040U
+#define DSI_VNPCR_NPSIZE7 0x00000080U
+#define DSI_VNPCR_NPSIZE8 0x00000100U
+#define DSI_VNPCR_NPSIZE9 0x00000200U
+#define DSI_VNPCR_NPSIZE10 0x00000400U
+#define DSI_VNPCR_NPSIZE11 0x00000800U
+#define DSI_VNPCR_NPSIZE12 0x00001000U
+
+/******************* Bit definition for DSI_VHSACR register *************/
+#define DSI_VHSACR_HSA 0x00000FFFU /*!< Horizontal Synchronism Active duration */
+#define DSI_VHSACR_HSA0 0x00000001U
+#define DSI_VHSACR_HSA1 0x00000002U
+#define DSI_VHSACR_HSA2 0x00000004U
+#define DSI_VHSACR_HSA3 0x00000008U
+#define DSI_VHSACR_HSA4 0x00000010U
+#define DSI_VHSACR_HSA5 0x00000020U
+#define DSI_VHSACR_HSA6 0x00000040U
+#define DSI_VHSACR_HSA7 0x00000080U
+#define DSI_VHSACR_HSA8 0x00000100U
+#define DSI_VHSACR_HSA9 0x00000200U
+#define DSI_VHSACR_HSA10 0x00000400U
+#define DSI_VHSACR_HSA11 0x00000800U
+
+/******************* Bit definition for DSI_VHBPCR register *************/
+#define DSI_VHBPCR_HBP 0x00000FFFU /*!< Horizontal Back-Porch duration */
+#define DSI_VHBPCR_HBP0 0x00000001U
+#define DSI_VHBPCR_HBP1 0x00000002U
+#define DSI_VHBPCR_HBP2 0x00000004U
+#define DSI_VHBPCR_HBP3 0x00000008U
+#define DSI_VHBPCR_HBP4 0x00000010U
+#define DSI_VHBPCR_HBP5 0x00000020U
+#define DSI_VHBPCR_HBP6 0x00000040U
+#define DSI_VHBPCR_HBP7 0x00000080U
+#define DSI_VHBPCR_HBP8 0x00000100U
+#define DSI_VHBPCR_HBP9 0x00000200U
+#define DSI_VHBPCR_HBP10 0x00000400U
+#define DSI_VHBPCR_HBP11 0x00000800U
+
+/******************* Bit definition for DSI_VLCR register ***************/
+#define DSI_VLCR_HLINE 0x00007FFFU /*!< Horizontal Line duration */
+#define DSI_VLCR_HLINE0 0x00000001U
+#define DSI_VLCR_HLINE1 0x00000002U
+#define DSI_VLCR_HLINE2 0x00000004U
+#define DSI_VLCR_HLINE3 0x00000008U
+#define DSI_VLCR_HLINE4 0x00000010U
+#define DSI_VLCR_HLINE5 0x00000020U
+#define DSI_VLCR_HLINE6 0x00000040U
+#define DSI_VLCR_HLINE7 0x00000080U
+#define DSI_VLCR_HLINE8 0x00000100U
+#define DSI_VLCR_HLINE9 0x00000200U
+#define DSI_VLCR_HLINE10 0x00000400U
+#define DSI_VLCR_HLINE11 0x00000800U
+#define DSI_VLCR_HLINE12 0x00001000U
+#define DSI_VLCR_HLINE13 0x00002000U
+#define DSI_VLCR_HLINE14 0x00004000U
+
+/******************* Bit definition for DSI_VVSACR register *************/
+#define DSI_VVSACR_VSA 0x000003FFU /*!< Vertical Synchronism Active duration */
+#define DSI_VVSACR_VSA0 0x00000001U
+#define DSI_VVSACR_VSA1 0x00000002U
+#define DSI_VVSACR_VSA2 0x00000004U
+#define DSI_VVSACR_VSA3 0x00000008U
+#define DSI_VVSACR_VSA4 0x00000010U
+#define DSI_VVSACR_VSA5 0x00000020U
+#define DSI_VVSACR_VSA6 0x00000040U
+#define DSI_VVSACR_VSA7 0x00000080U
+#define DSI_VVSACR_VSA8 0x00000100U
+#define DSI_VVSACR_VSA9 0x00000200U
+
+/******************* Bit definition for DSI_VVBPCR register *************/
+#define DSI_VVBPCR_VBP 0x000003FFU /*!< Vertical Back-Porch duration */
+#define DSI_VVBPCR_VBP0 0x00000001U
+#define DSI_VVBPCR_VBP1 0x00000002U
+#define DSI_VVBPCR_VBP2 0x00000004U
+#define DSI_VVBPCR_VBP3 0x00000008U
+#define DSI_VVBPCR_VBP4 0x00000010U
+#define DSI_VVBPCR_VBP5 0x00000020U
+#define DSI_VVBPCR_VBP6 0x00000040U
+#define DSI_VVBPCR_VBP7 0x00000080U
+#define DSI_VVBPCR_VBP8 0x00000100U
+#define DSI_VVBPCR_VBP9 0x00000200U
+
+/******************* Bit definition for DSI_VVFPCR register *************/
+#define DSI_VVFPCR_VFP 0x000003FFU /*!< Vertical Front-Porch duration */
+#define DSI_VVFPCR_VFP0 0x00000001U
+#define DSI_VVFPCR_VFP1 0x00000002U
+#define DSI_VVFPCR_VFP2 0x00000004U
+#define DSI_VVFPCR_VFP3 0x00000008U
+#define DSI_VVFPCR_VFP4 0x00000010U
+#define DSI_VVFPCR_VFP5 0x00000020U
+#define DSI_VVFPCR_VFP6 0x00000040U
+#define DSI_VVFPCR_VFP7 0x00000080U
+#define DSI_VVFPCR_VFP8 0x00000100U
+#define DSI_VVFPCR_VFP9 0x00000200U
+
+/******************* Bit definition for DSI_VVACR register **************/
+#define DSI_VVACR_VA 0x00003FFFU /*!< Vertical Active duration */
+#define DSI_VVACR_VA0 0x00000001U
+#define DSI_VVACR_VA1 0x00000002U
+#define DSI_VVACR_VA2 0x00000004U
+#define DSI_VVACR_VA3 0x00000008U
+#define DSI_VVACR_VA4 0x00000010U
+#define DSI_VVACR_VA5 0x00000020U
+#define DSI_VVACR_VA6 0x00000040U
+#define DSI_VVACR_VA7 0x00000080U
+#define DSI_VVACR_VA8 0x00000100U
+#define DSI_VVACR_VA9 0x00000200U
+#define DSI_VVACR_VA10 0x00000400U
+#define DSI_VVACR_VA11 0x00000800U
+#define DSI_VVACR_VA12 0x00001000U
+#define DSI_VVACR_VA13 0x00002000U
+
+/******************* Bit definition for DSI_LCCR register ***************/
+#define DSI_LCCR_CMDSIZE 0x0000FFFFU /*!< Command Size */
+#define DSI_LCCR_CMDSIZE0 0x00000001U
+#define DSI_LCCR_CMDSIZE1 0x00000002U
+#define DSI_LCCR_CMDSIZE2 0x00000004U
+#define DSI_LCCR_CMDSIZE3 0x00000008U
+#define DSI_LCCR_CMDSIZE4 0x00000010U
+#define DSI_LCCR_CMDSIZE5 0x00000020U
+#define DSI_LCCR_CMDSIZE6 0x00000040U
+#define DSI_LCCR_CMDSIZE7 0x00000080U
+#define DSI_LCCR_CMDSIZE8 0x00000100U
+#define DSI_LCCR_CMDSIZE9 0x00000200U
+#define DSI_LCCR_CMDSIZE10 0x00000400U
+#define DSI_LCCR_CMDSIZE11 0x00000800U
+#define DSI_LCCR_CMDSIZE12 0x00001000U
+#define DSI_LCCR_CMDSIZE13 0x00002000U
+#define DSI_LCCR_CMDSIZE14 0x00004000U
+#define DSI_LCCR_CMDSIZE15 0x00008000U
+
+/******************* Bit definition for DSI_CMCR register ***************/
+#define DSI_CMCR_TEARE 0x00000001U /*!< Tearing Effect Acknowledge Request Enable */
+#define DSI_CMCR_ARE 0x00000002U /*!< Acknowledge Request Enable */
+#define DSI_CMCR_GSW0TX 0x00000100U /*!< Generic Short Write Zero parameters Transmission */
+#define DSI_CMCR_GSW1TX 0x00000200U /*!< Generic Short Write One parameters Transmission */
+#define DSI_CMCR_GSW2TX 0x00000400U /*!< Generic Short Write Two parameters Transmission */
+#define DSI_CMCR_GSR0TX 0x00000800U /*!< Generic Short Read Zero parameters Transmission */
+#define DSI_CMCR_GSR1TX 0x00001000U /*!< Generic Short Read One parameters Transmission */
+#define DSI_CMCR_GSR2TX 0x00002000U /*!< Generic Short Read Two parameters Transmission */
+#define DSI_CMCR_GLWTX 0x00004000U /*!< Generic Long Write Transmission */
+#define DSI_CMCR_DSW0TX 0x00010000U /*!< DCS Short Write Zero parameter Transmission */
+#define DSI_CMCR_DSW1TX 0x00020000U /*!< DCS Short Read One parameter Transmission */
+#define DSI_CMCR_DSR0TX 0x00040000U /*!< DCS Short Read Zero parameter Transmission */
+#define DSI_CMCR_DLWTX 0x00080000U /*!< DCS Long Write Transmission */
+#define DSI_CMCR_MRDPS 0x01000000U /*!< Maximum Read Packet Size */
+
+/******************* Bit definition for DSI_GHCR register ***************/
+#define DSI_GHCR_DT 0x0000003FU /*!< Type */
+#define DSI_GHCR_DT0 0x00000001U
+#define DSI_GHCR_DT1 0x00000002U
+#define DSI_GHCR_DT2 0x00000004U
+#define DSI_GHCR_DT3 0x00000008U
+#define DSI_GHCR_DT4 0x00000010U
+#define DSI_GHCR_DT5 0x00000020U
+
+#define DSI_GHCR_VCID 0x000000C0U /*!< Channel */
+#define DSI_GHCR_VCID0 0x00000040U
+#define DSI_GHCR_VCID1 0x00000080U
+
+#define DSI_GHCR_WCLSB 0x0000FF00U /*!< WordCount LSB */
+#define DSI_GHCR_WCLSB0 0x00000100U
+#define DSI_GHCR_WCLSB1 0x00000200U
+#define DSI_GHCR_WCLSB2 0x00000400U
+#define DSI_GHCR_WCLSB3 0x00000800U
+#define DSI_GHCR_WCLSB4 0x00001000U
+#define DSI_GHCR_WCLSB5 0x00002000U
+#define DSI_GHCR_WCLSB6 0x00004000U
+#define DSI_GHCR_WCLSB7 0x00008000U
+
+#define DSI_GHCR_WCMSB 0x00FF0000U /*!< WordCount MSB */
+#define DSI_GHCR_WCMSB0 0x00010000U
+#define DSI_GHCR_WCMSB1 0x00020000U
+#define DSI_GHCR_WCMSB2 0x00040000U
+#define DSI_GHCR_WCMSB3 0x00080000U
+#define DSI_GHCR_WCMSB4 0x00100000U
+#define DSI_GHCR_WCMSB5 0x00200000U
+#define DSI_GHCR_WCMSB6 0x00400000U
+#define DSI_GHCR_WCMSB7 0x00800000U
+
+/******************* Bit definition for DSI_GPDR register ***************/
+#define DSI_GPDR_DATA1 0x000000FFU /*!< Payload Byte 1 */
+#define DSI_GPDR_DATA1_0 0x00000001U
+#define DSI_GPDR_DATA1_1 0x00000002U
+#define DSI_GPDR_DATA1_2 0x00000004U
+#define DSI_GPDR_DATA1_3 0x00000008U
+#define DSI_GPDR_DATA1_4 0x00000010U
+#define DSI_GPDR_DATA1_5 0x00000020U
+#define DSI_GPDR_DATA1_6 0x00000040U
+#define DSI_GPDR_DATA1_7 0x00000080U
+
+#define DSI_GPDR_DATA2 0x0000FF00U /*!< Payload Byte 2 */
+#define DSI_GPDR_DATA2_0 0x00000100U
+#define DSI_GPDR_DATA2_1 0x00000200U
+#define DSI_GPDR_DATA2_2 0x00000400U
+#define DSI_GPDR_DATA2_3 0x00000800U
+#define DSI_GPDR_DATA2_4 0x00001000U
+#define DSI_GPDR_DATA2_5 0x00002000U
+#define DSI_GPDR_DATA2_6 0x00004000U
+#define DSI_GPDR_DATA2_7 0x00008000U
+
+#define DSI_GPDR_DATA3 0x00FF0000U /*!< Payload Byte 3 */
+#define DSI_GPDR_DATA3_0 0x00010000U
+#define DSI_GPDR_DATA3_1 0x00020000U
+#define DSI_GPDR_DATA3_2 0x00040000U
+#define DSI_GPDR_DATA3_3 0x00080000U
+#define DSI_GPDR_DATA3_4 0x00100000U
+#define DSI_GPDR_DATA3_5 0x00200000U
+#define DSI_GPDR_DATA3_6 0x00400000U
+#define DSI_GPDR_DATA3_7 0x00800000U
+
+#define DSI_GPDR_DATA4 0xFF000000U /*!< Payload Byte 4 */
+#define DSI_GPDR_DATA4_0 0x01000000U
+#define DSI_GPDR_DATA4_1 0x02000000U
+#define DSI_GPDR_DATA4_2 0x04000000U
+#define DSI_GPDR_DATA4_3 0x08000000U
+#define DSI_GPDR_DATA4_4 0x10000000U
+#define DSI_GPDR_DATA4_5 0x20000000U
+#define DSI_GPDR_DATA4_6 0x40000000U
+#define DSI_GPDR_DATA4_7 0x80000000U
+
+/******************* Bit definition for DSI_GPSR register ***************/
+#define DSI_GPSR_CMDFE 0x00000001U /*!< Command FIFO Empty */
+#define DSI_GPSR_CMDFF 0x00000002U /*!< Command FIFO Full */
+#define DSI_GPSR_PWRFE 0x00000004U /*!< Payload Write FIFO Empty */
+#define DSI_GPSR_PWRFF 0x00000008U /*!< Payload Write FIFO Full */
+#define DSI_GPSR_PRDFE 0x00000010U /*!< Payload Read FIFO Empty */
+#define DSI_GPSR_PRDFF 0x00000020U /*!< Payload Read FIFO Full */
+#define DSI_GPSR_RCB 0x00000040U /*!< Read Command Busy */
+
+/******************* Bit definition for DSI_TCCR0 register **************/
+#define DSI_TCCR0_LPRX_TOCNT 0x0000FFFFU /*!< Low-power Reception Timeout Counter */
+#define DSI_TCCR0_LPRX_TOCNT0 0x00000001U
+#define DSI_TCCR0_LPRX_TOCNT1 0x00000002U
+#define DSI_TCCR0_LPRX_TOCNT2 0x00000004U
+#define DSI_TCCR0_LPRX_TOCNT3 0x00000008U
+#define DSI_TCCR0_LPRX_TOCNT4 0x00000010U
+#define DSI_TCCR0_LPRX_TOCNT5 0x00000020U
+#define DSI_TCCR0_LPRX_TOCNT6 0x00000040U
+#define DSI_TCCR0_LPRX_TOCNT7 0x00000080U
+#define DSI_TCCR0_LPRX_TOCNT8 0x00000100U
+#define DSI_TCCR0_LPRX_TOCNT9 0x00000200U
+#define DSI_TCCR0_LPRX_TOCNT10 0x00000400U
+#define DSI_TCCR0_LPRX_TOCNT11 0x00000800U
+#define DSI_TCCR0_LPRX_TOCNT12 0x00001000U
+#define DSI_TCCR0_LPRX_TOCNT13 0x00002000U
+#define DSI_TCCR0_LPRX_TOCNT14 0x00004000U
+#define DSI_TCCR0_LPRX_TOCNT15 0x00008000U
+
+#define DSI_TCCR0_HSTX_TOCNT 0xFFFF0000U /*!< High-Speed Transmission Timeout Counter */
+#define DSI_TCCR0_HSTX_TOCNT0 0x00010000U
+#define DSI_TCCR0_HSTX_TOCNT1 0x00020000U
+#define DSI_TCCR0_HSTX_TOCNT2 0x00040000U
+#define DSI_TCCR0_HSTX_TOCNT3 0x00080000U
+#define DSI_TCCR0_HSTX_TOCNT4 0x00100000U
+#define DSI_TCCR0_HSTX_TOCNT5 0x00200000U
+#define DSI_TCCR0_HSTX_TOCNT6 0x00400000U
+#define DSI_TCCR0_HSTX_TOCNT7 0x00800000U
+#define DSI_TCCR0_HSTX_TOCNT8 0x01000000U
+#define DSI_TCCR0_HSTX_TOCNT9 0x02000000U
+#define DSI_TCCR0_HSTX_TOCNT10 0x04000000U
+#define DSI_TCCR0_HSTX_TOCNT11 0x08000000U
+#define DSI_TCCR0_HSTX_TOCNT12 0x10000000U
+#define DSI_TCCR0_HSTX_TOCNT13 0x20000000U
+#define DSI_TCCR0_HSTX_TOCNT14 0x40000000U
+#define DSI_TCCR0_HSTX_TOCNT15 0x80000000U
+
+/******************* Bit definition for DSI_TCCR1 register **************/
+#define DSI_TCCR1_HSRD_TOCNT 0x0000FFFFU /*!< High-Speed Read Timeout Counter */
+#define DSI_TCCR1_HSRD_TOCNT0 0x00000001U
+#define DSI_TCCR1_HSRD_TOCNT1 0x00000002U
+#define DSI_TCCR1_HSRD_TOCNT2 0x00000004U
+#define DSI_TCCR1_HSRD_TOCNT3 0x00000008U
+#define DSI_TCCR1_HSRD_TOCNT4 0x00000010U
+#define DSI_TCCR1_HSRD_TOCNT5 0x00000020U
+#define DSI_TCCR1_HSRD_TOCNT6 0x00000040U
+#define DSI_TCCR1_HSRD_TOCNT7 0x00000080U
+#define DSI_TCCR1_HSRD_TOCNT8 0x00000100U
+#define DSI_TCCR1_HSRD_TOCNT9 0x00000200U
+#define DSI_TCCR1_HSRD_TOCNT10 0x00000400U
+#define DSI_TCCR1_HSRD_TOCNT11 0x00000800U
+#define DSI_TCCR1_HSRD_TOCNT12 0x00001000U
+#define DSI_TCCR1_HSRD_TOCNT13 0x00002000U
+#define DSI_TCCR1_HSRD_TOCNT14 0x00004000U
+#define DSI_TCCR1_HSRD_TOCNT15 0x00008000U
+
+/******************* Bit definition for DSI_TCCR2 register **************/
+#define DSI_TCCR2_LPRD_TOCNT 0x0000FFFFU /*!< Low-Power Read Timeout Counter */
+#define DSI_TCCR2_LPRD_TOCNT0 0x00000001U
+#define DSI_TCCR2_LPRD_TOCNT1 0x00000002U
+#define DSI_TCCR2_LPRD_TOCNT2 0x00000004U
+#define DSI_TCCR2_LPRD_TOCNT3 0x00000008U
+#define DSI_TCCR2_LPRD_TOCNT4 0x00000010U
+#define DSI_TCCR2_LPRD_TOCNT5 0x00000020U
+#define DSI_TCCR2_LPRD_TOCNT6 0x00000040U
+#define DSI_TCCR2_LPRD_TOCNT7 0x00000080U
+#define DSI_TCCR2_LPRD_TOCNT8 0x00000100U
+#define DSI_TCCR2_LPRD_TOCNT9 0x00000200U
+#define DSI_TCCR2_LPRD_TOCNT10 0x00000400U
+#define DSI_TCCR2_LPRD_TOCNT11 0x00000800U
+#define DSI_TCCR2_LPRD_TOCNT12 0x00001000U
+#define DSI_TCCR2_LPRD_TOCNT13 0x00002000U
+#define DSI_TCCR2_LPRD_TOCNT14 0x00004000U
+#define DSI_TCCR2_LPRD_TOCNT15 0x00008000U
+
+/******************* Bit definition for DSI_TCCR3 register **************/
+#define DSI_TCCR3_HSWR_TOCNT 0x0000FFFFU /*!< High-Speed Write Timeout Counter */
+#define DSI_TCCR3_HSWR_TOCNT0 0x00000001U
+#define DSI_TCCR3_HSWR_TOCNT1 0x00000002U
+#define DSI_TCCR3_HSWR_TOCNT2 0x00000004U
+#define DSI_TCCR3_HSWR_TOCNT3 0x00000008U
+#define DSI_TCCR3_HSWR_TOCNT4 0x00000010U
+#define DSI_TCCR3_HSWR_TOCNT5 0x00000020U
+#define DSI_TCCR3_HSWR_TOCNT6 0x00000040U
+#define DSI_TCCR3_HSWR_TOCNT7 0x00000080U
+#define DSI_TCCR3_HSWR_TOCNT8 0x00000100U
+#define DSI_TCCR3_HSWR_TOCNT9 0x00000200U
+#define DSI_TCCR3_HSWR_TOCNT10 0x00000400U
+#define DSI_TCCR3_HSWR_TOCNT11 0x00000800U
+#define DSI_TCCR3_HSWR_TOCNT12 0x00001000U
+#define DSI_TCCR3_HSWR_TOCNT13 0x00002000U
+#define DSI_TCCR3_HSWR_TOCNT14 0x00004000U
+#define DSI_TCCR3_HSWR_TOCNT15 0x00008000U
+
+#define DSI_TCCR3_PM 0x01000000U /*!< Presp Mode */
+
+/******************* Bit definition for DSI_TCCR4 register **************/
+#define DSI_TCCR4_LPWR_TOCNT 0x0000FFFFU /*!< Low-Power Write Timeout Counter */
+#define DSI_TCCR4_LPWR_TOCNT0 0x00000001U
+#define DSI_TCCR4_LPWR_TOCNT1 0x00000002U
+#define DSI_TCCR4_LPWR_TOCNT2 0x00000004U
+#define DSI_TCCR4_LPWR_TOCNT3 0x00000008U
+#define DSI_TCCR4_LPWR_TOCNT4 0x00000010U
+#define DSI_TCCR4_LPWR_TOCNT5 0x00000020U
+#define DSI_TCCR4_LPWR_TOCNT6 0x00000040U
+#define DSI_TCCR4_LPWR_TOCNT7 0x00000080U
+#define DSI_TCCR4_LPWR_TOCNT8 0x00000100U
+#define DSI_TCCR4_LPWR_TOCNT9 0x00000200U
+#define DSI_TCCR4_LPWR_TOCNT10 0x00000400U
+#define DSI_TCCR4_LPWR_TOCNT11 0x00000800U
+#define DSI_TCCR4_LPWR_TOCNT12 0x00001000U
+#define DSI_TCCR4_LPWR_TOCNT13 0x00002000U
+#define DSI_TCCR4_LPWR_TOCNT14 0x00004000U
+#define DSI_TCCR4_LPWR_TOCNT15 0x00008000U
+
+/******************* Bit definition for DSI_TCCR5 register **************/
+#define DSI_TCCR5_BTA_TOCNT 0x0000FFFFU /*!< Bus-Turn-Around Timeout Counter */
+#define DSI_TCCR5_BTA_TOCNT0 0x00000001U
+#define DSI_TCCR5_BTA_TOCNT1 0x00000002U
+#define DSI_TCCR5_BTA_TOCNT2 0x00000004U
+#define DSI_TCCR5_BTA_TOCNT3 0x00000008U
+#define DSI_TCCR5_BTA_TOCNT4 0x00000010U
+#define DSI_TCCR5_BTA_TOCNT5 0x00000020U
+#define DSI_TCCR5_BTA_TOCNT6 0x00000040U
+#define DSI_TCCR5_BTA_TOCNT7 0x00000080U
+#define DSI_TCCR5_BTA_TOCNT8 0x00000100U
+#define DSI_TCCR5_BTA_TOCNT9 0x00000200U
+#define DSI_TCCR5_BTA_TOCNT10 0x00000400U
+#define DSI_TCCR5_BTA_TOCNT11 0x00000800U
+#define DSI_TCCR5_BTA_TOCNT12 0x00001000U
+#define DSI_TCCR5_BTA_TOCNT13 0x00002000U
+#define DSI_TCCR5_BTA_TOCNT14 0x00004000U
+#define DSI_TCCR5_BTA_TOCNT15 0x00008000U
+
+/******************* Bit definition for DSI_TDCR register ***************/
+#define DSI_TDCR_3DM 0x00000003U /*!< 3D Mode */
+#define DSI_TDCR_3DM0 0x00000001U
+#define DSI_TDCR_3DM1 0x00000002U
+
+#define DSI_TDCR_3DF 0x0000000CU /*!< 3D Format */
+#define DSI_TDCR_3DF0 0x00000004U
+#define DSI_TDCR_3DF1 0x00000008U
+
+#define DSI_TDCR_SVS 0x00000010U /*!< Second VSYNC */
+#define DSI_TDCR_RF 0x00000020U /*!< Right First */
+#define DSI_TDCR_S3DC 0x00010000U /*!< Send 3D Control */
+
+/******************* Bit definition for DSI_CLCR register ***************/
+#define DSI_CLCR_DPCC 0x00000001U /*!< D-PHY Clock Control */
+#define DSI_CLCR_ACR 0x00000002U /*!< Automatic Clocklane Control */
+
+/******************* Bit definition for DSI_CLTCR register **************/
+#define DSI_CLTCR_LP2HS_TIME 0x000003FFU /*!< Low-Power to High-Speed Time */
+#define DSI_CLTCR_LP2HS_TIME0 0x00000001U
+#define DSI_CLTCR_LP2HS_TIME1 0x00000002U
+#define DSI_CLTCR_LP2HS_TIME2 0x00000004U
+#define DSI_CLTCR_LP2HS_TIME3 0x00000008U
+#define DSI_CLTCR_LP2HS_TIME4 0x00000010U
+#define DSI_CLTCR_LP2HS_TIME5 0x00000020U
+#define DSI_CLTCR_LP2HS_TIME6 0x00000040U
+#define DSI_CLTCR_LP2HS_TIME7 0x00000080U
+#define DSI_CLTCR_LP2HS_TIME8 0x00000100U
+#define DSI_CLTCR_LP2HS_TIME9 0x00000200U
+
+#define DSI_CLTCR_HS2LP_TIME 0x03FF0000U /*!< High-Speed to Low-Power Time */
+#define DSI_CLTCR_HS2LP_TIME0 0x00010000U
+#define DSI_CLTCR_HS2LP_TIME1 0x00020000U
+#define DSI_CLTCR_HS2LP_TIME2 0x00040000U
+#define DSI_CLTCR_HS2LP_TIME3 0x00080000U
+#define DSI_CLTCR_HS2LP_TIME4 0x00100000U
+#define DSI_CLTCR_HS2LP_TIME5 0x00200000U
+#define DSI_CLTCR_HS2LP_TIME6 0x00400000U
+#define DSI_CLTCR_HS2LP_TIME7 0x00800000U
+#define DSI_CLTCR_HS2LP_TIME8 0x01000000U
+#define DSI_CLTCR_HS2LP_TIME9 0x02000000U
+
+/******************* Bit definition for DSI_DLTCR register **************/
+#define DSI_DLTCR_MRD_TIME 0x00007FFFU /*!< Maximum Read Time */
+#define DSI_DLTCR_MRD_TIME0 0x00000001U
+#define DSI_DLTCR_MRD_TIME1 0x00000002U
+#define DSI_DLTCR_MRD_TIME2 0x00000004U
+#define DSI_DLTCR_MRD_TIME3 0x00000008U
+#define DSI_DLTCR_MRD_TIME4 0x00000010U
+#define DSI_DLTCR_MRD_TIME5 0x00000020U
+#define DSI_DLTCR_MRD_TIME6 0x00000040U
+#define DSI_DLTCR_MRD_TIME7 0x00000080U
+#define DSI_DLTCR_MRD_TIME8 0x00000100U
+#define DSI_DLTCR_MRD_TIME9 0x00000200U
+#define DSI_DLTCR_MRD_TIME10 0x00000400U
+#define DSI_DLTCR_MRD_TIME11 0x00000800U
+#define DSI_DLTCR_MRD_TIME12 0x00001000U
+#define DSI_DLTCR_MRD_TIME13 0x00002000U
+#define DSI_DLTCR_MRD_TIME14 0x00004000U
+
+#define DSI_DLTCR_LP2HS_TIME 0x00FF0000U /*!< Low-Power To High-Speed Time */
+#define DSI_DLTCR_LP2HS_TIME0 0x00010000U
+#define DSI_DLTCR_LP2HS_TIME1 0x00020000U
+#define DSI_DLTCR_LP2HS_TIME2 0x00040000U
+#define DSI_DLTCR_LP2HS_TIME3 0x00080000U
+#define DSI_DLTCR_LP2HS_TIME4 0x00100000U
+#define DSI_DLTCR_LP2HS_TIME5 0x00200000U
+#define DSI_DLTCR_LP2HS_TIME6 0x00400000U
+#define DSI_DLTCR_LP2HS_TIME7 0x00800000U
+
+#define DSI_DLTCR_HS2LP_TIME 0xFF000000U /*!< High-Speed To Low-Power Time */
+#define DSI_DLTCR_HS2LP_TIME0 0x01000000U
+#define DSI_DLTCR_HS2LP_TIME1 0x02000000U
+#define DSI_DLTCR_HS2LP_TIME2 0x04000000U
+#define DSI_DLTCR_HS2LP_TIME3 0x08000000U
+#define DSI_DLTCR_HS2LP_TIME4 0x10000000U
+#define DSI_DLTCR_HS2LP_TIME5 0x20000000U
+#define DSI_DLTCR_HS2LP_TIME6 0x40000000U
+#define DSI_DLTCR_HS2LP_TIME7 0x80000000U
+
+/******************* Bit definition for DSI_PCTLR register **************/
+#define DSI_PCTLR_DEN 0x00000002U /*!< Digital Enable */
+#define DSI_PCTLR_CKE 0x00000004U /*!< Clock Enable */
+
+/******************* Bit definition for DSI_PCONFR register *************/
+#define DSI_PCONFR_NL 0x00000003U /*!< Number of Lanes */
+#define DSI_PCONFR_NL0 0x00000001U
+#define DSI_PCONFR_NL1 0x00000002U
+
+#define DSI_PCONFR_SW_TIME 0x0000FF00U /*!< Stop Wait Time */
+#define DSI_PCONFR_SW_TIME0 0x00000100U
+#define DSI_PCONFR_SW_TIME1 0x00000200U
+#define DSI_PCONFR_SW_TIME2 0x00000400U
+#define DSI_PCONFR_SW_TIME3 0x00000800U
+#define DSI_PCONFR_SW_TIME4 0x00001000U
+#define DSI_PCONFR_SW_TIME5 0x00002000U
+#define DSI_PCONFR_SW_TIME6 0x00004000U
+#define DSI_PCONFR_SW_TIME7 0x00008000U
+
+/******************* Bit definition for DSI_PUCR register ***************/
+#define DSI_PUCR_URCL 0x00000001U /*!< ULPS Request on Clock Lane */
+#define DSI_PUCR_UECL 0x00000002U /*!< ULPS Exit on Clock Lane */
+#define DSI_PUCR_URDL 0x00000004U /*!< ULPS Request on Data Lane */
+#define DSI_PUCR_UEDL 0x00000008U /*!< ULPS Exit on Data Lane */
+
+/******************* Bit definition for DSI_PTTCR register **************/
+#define DSI_PTTCR_TX_TRIG 0x0000000FU /*!< Transmission Trigger */
+#define DSI_PTTCR_TX_TRIG0 0x00000001U
+#define DSI_PTTCR_TX_TRIG1 0x00000002U
+#define DSI_PTTCR_TX_TRIG2 0x00000004U
+#define DSI_PTTCR_TX_TRIG3 0x00000008U
+
+/******************* Bit definition for DSI_PSR register ****************/
+#define DSI_PSR_PD 0x00000002U /*!< PHY Direction */
+#define DSI_PSR_PSSC 0x00000004U /*!< PHY Stop State Clock lane */
+#define DSI_PSR_UANC 0x00000008U /*!< ULPS Active Not Clock lane */
+#define DSI_PSR_PSS0 0x00000010U /*!< PHY Stop State lane 0 */
+#define DSI_PSR_UAN0 0x00000020U /*!< ULPS Active Not lane 0 */
+#define DSI_PSR_RUE0 0x00000040U /*!< RX ULPS Escape lane 0 */
+#define DSI_PSR_PSS1 0x00000080U /*!< PHY Stop State lane 1 */
+#define DSI_PSR_UAN1 0x00000100U /*!< ULPS Active Not lane 1 */
+
+/******************* Bit definition for DSI_ISR0 register ***************/
+#define DSI_ISR0_AE0 0x00000001U /*!< Acknowledge Error 0 */
+#define DSI_ISR0_AE1 0x00000002U /*!< Acknowledge Error 1 */
+#define DSI_ISR0_AE2 0x00000004U /*!< Acknowledge Error 2 */
+#define DSI_ISR0_AE3 0x00000008U /*!< Acknowledge Error 3 */
+#define DSI_ISR0_AE4 0x00000010U /*!< Acknowledge Error 4 */
+#define DSI_ISR0_AE5 0x00000020U /*!< Acknowledge Error 5 */
+#define DSI_ISR0_AE6 0x00000040U /*!< Acknowledge Error 6 */
+#define DSI_ISR0_AE7 0x00000080U /*!< Acknowledge Error 7 */
+#define DSI_ISR0_AE8 0x00000100U /*!< Acknowledge Error 8 */
+#define DSI_ISR0_AE9 0x00000200U /*!< Acknowledge Error 9 */
+#define DSI_ISR0_AE10 0x00000400U /*!< Acknowledge Error 10 */
+#define DSI_ISR0_AE11 0x00000800U /*!< Acknowledge Error 11 */
+#define DSI_ISR0_AE12 0x00001000U /*!< Acknowledge Error 12 */
+#define DSI_ISR0_AE13 0x00002000U /*!< Acknowledge Error 13 */
+#define DSI_ISR0_AE14 0x00004000U /*!< Acknowledge Error 14 */
+#define DSI_ISR0_AE15 0x00008000U /*!< Acknowledge Error 15 */
+#define DSI_ISR0_PE0 0x00010000U /*!< PHY Error 0 */
+#define DSI_ISR0_PE1 0x00020000U /*!< PHY Error 1 */
+#define DSI_ISR0_PE2 0x00040000U /*!< PHY Error 2 */
+#define DSI_ISR0_PE3 0x00080000U /*!< PHY Error 3 */
+#define DSI_ISR0_PE4 0x00100000U /*!< PHY Error 4 */
+
+/******************* Bit definition for DSI_ISR1 register ***************/
+#define DSI_ISR1_TOHSTX 0x00000001U /*!< Timeout High-Speed Transmission */
+#define DSI_ISR1_TOLPRX 0x00000002U /*!< Timeout Low-Power Reception */
+#define DSI_ISR1_ECCSE 0x00000004U /*!< ECC Single-bit Error */
+#define DSI_ISR1_ECCME 0x00000008U /*!< ECC Multi-bit Error */
+#define DSI_ISR1_CRCE 0x00000010U /*!< CRC Error */
+#define DSI_ISR1_PSE 0x00000020U /*!< Packet Size Error */
+#define DSI_ISR1_EOTPE 0x00000040U /*!< EoTp Error */
+#define DSI_ISR1_LPWRE 0x00000080U /*!< LTDC Payload Write Error */
+#define DSI_ISR1_GCWRE 0x00000100U /*!< Generic Command Write Error */
+#define DSI_ISR1_GPWRE 0x00000200U /*!< Generic Payload Write Error */
+#define DSI_ISR1_GPTXE 0x00000400U /*!< Generic Payload Transmit Error */
+#define DSI_ISR1_GPRDE 0x00000800U /*!< Generic Payload Read Error */
+#define DSI_ISR1_GPRXE 0x00001000U /*!< Generic Payload Receive Error */
+
+/******************* Bit definition for DSI_IER0 register ***************/
+#define DSI_IER0_AE0IE 0x00000001U /*!< Acknowledge Error 0 Interrupt Enable */
+#define DSI_IER0_AE1IE 0x00000002U /*!< Acknowledge Error 1 Interrupt Enable */
+#define DSI_IER0_AE2IE 0x00000004U /*!< Acknowledge Error 2 Interrupt Enable */
+#define DSI_IER0_AE3IE 0x00000008U /*!< Acknowledge Error 3 Interrupt Enable */
+#define DSI_IER0_AE4IE 0x00000010U /*!< Acknowledge Error 4 Interrupt Enable */
+#define DSI_IER0_AE5IE 0x00000020U /*!< Acknowledge Error 5 Interrupt Enable */
+#define DSI_IER0_AE6IE 0x00000040U /*!< Acknowledge Error 6 Interrupt Enable */
+#define DSI_IER0_AE7IE 0x00000080U /*!< Acknowledge Error 7 Interrupt Enable */
+#define DSI_IER0_AE8IE 0x00000100U /*!< Acknowledge Error 8 Interrupt Enable */
+#define DSI_IER0_AE9IE 0x00000200U /*!< Acknowledge Error 9 Interrupt Enable */
+#define DSI_IER0_AE10IE 0x00000400U /*!< Acknowledge Error 10 Interrupt Enable */
+#define DSI_IER0_AE11IE 0x00000800U /*!< Acknowledge Error 11 Interrupt Enable */
+#define DSI_IER0_AE12IE 0x00001000U /*!< Acknowledge Error 12 Interrupt Enable */
+#define DSI_IER0_AE13IE 0x00002000U /*!< Acknowledge Error 13 Interrupt Enable */
+#define DSI_IER0_AE14IE 0x00004000U /*!< Acknowledge Error 14 Interrupt Enable */
+#define DSI_IER0_AE15IE 0x00008000U /*!< Acknowledge Error 15 Interrupt Enable */
+#define DSI_IER0_PE0IE 0x00010000U /*!< PHY Error 0 Interrupt Enable */
+#define DSI_IER0_PE1IE 0x00020000U /*!< PHY Error 1 Interrupt Enable */
+#define DSI_IER0_PE2IE 0x00040000U /*!< PHY Error 2 Interrupt Enable */
+#define DSI_IER0_PE3IE 0x00080000U /*!< PHY Error 3 Interrupt Enable */
+#define DSI_IER0_PE4IE 0x00100000U /*!< PHY Error 4 Interrupt Enable */
+
+/******************* Bit definition for DSI_IER1 register ***************/
+#define DSI_IER1_TOHSTXIE 0x00000001U /*!< Timeout High-Speed Transmission Interrupt Enable */
+#define DSI_IER1_TOLPRXIE 0x00000002U /*!< Timeout Low-Power Reception Interrupt Enable */
+#define DSI_IER1_ECCSEIE 0x00000004U /*!< ECC Single-bit Error Interrupt Enable */
+#define DSI_IER1_ECCMEIE 0x00000008U /*!< ECC Multi-bit Error Interrupt Enable */
+#define DSI_IER1_CRCEIE 0x00000010U /*!< CRC Error Interrupt Enable */
+#define DSI_IER1_PSEIE 0x00000020U /*!< Packet Size Error Interrupt Enable */
+#define DSI_IER1_EOTPEIE 0x00000040U /*!< EoTp Error Interrupt Enable */
+#define DSI_IER1_LPWREIE 0x00000080U /*!< LTDC Payload Write Error Interrupt Enable */
+#define DSI_IER1_GCWREIE 0x00000100U /*!< Generic Command Write Error Interrupt Enable */
+#define DSI_IER1_GPWREIE 0x00000200U /*!< Generic Payload Write Error Interrupt Enable */
+#define DSI_IER1_GPTXEIE 0x00000400U /*!< Generic Payload Transmit Error Interrupt Enable */
+#define DSI_IER1_GPRDEIE 0x00000800U /*!< Generic Payload Read Error Interrupt Enable */
+#define DSI_IER1_GPRXEIE 0x00001000U /*!< Generic Payload Receive Error Interrupt Enable */
+
+/******************* Bit definition for DSI_FIR0 register ***************/
+#define DSI_FIR0_FAE0 0x00000001U /*!< Force Acknowledge Error 0 */
+#define DSI_FIR0_FAE1 0x00000002U /*!< Force Acknowledge Error 1 */
+#define DSI_FIR0_FAE2 0x00000004U /*!< Force Acknowledge Error 2 */
+#define DSI_FIR0_FAE3 0x00000008U /*!< Force Acknowledge Error 3 */
+#define DSI_FIR0_FAE4 0x00000010U /*!< Force Acknowledge Error 4 */
+#define DSI_FIR0_FAE5 0x00000020U /*!< Force Acknowledge Error 5 */
+#define DSI_FIR0_FAE6 0x00000040U /*!< Force Acknowledge Error 6 */
+#define DSI_FIR0_FAE7 0x00000080U /*!< Force Acknowledge Error 7 */
+#define DSI_FIR0_FAE8 0x00000100U /*!< Force Acknowledge Error 8 */
+#define DSI_FIR0_FAE9 0x00000200U /*!< Force Acknowledge Error 9 */
+#define DSI_FIR0_FAE10 0x00000400U /*!< Force Acknowledge Error 10 */
+#define DSI_FIR0_FAE11 0x00000800U /*!< Force Acknowledge Error 11 */
+#define DSI_FIR0_FAE12 0x00001000U /*!< Force Acknowledge Error 12 */
+#define DSI_FIR0_FAE13 0x00002000U /*!< Force Acknowledge Error 13 */
+#define DSI_FIR0_FAE14 0x00004000U /*!< Force Acknowledge Error 14 */
+#define DSI_FIR0_FAE15 0x00008000U /*!< Force Acknowledge Error 15 */
+#define DSI_FIR0_FPE0 0x00010000U /*!< Force PHY Error 0 */
+#define DSI_FIR0_FPE1 0x00020000U /*!< Force PHY Error 1 */
+#define DSI_FIR0_FPE2 0x00040000U /*!< Force PHY Error 2 */
+#define DSI_FIR0_FPE3 0x00080000U /*!< Force PHY Error 3 */
+#define DSI_FIR0_FPE4 0x00100000U /*!< Force PHY Error 4 */
+
+/******************* Bit definition for DSI_FIR1 register ***************/
+#define DSI_FIR1_FTOHSTX 0x00000001U /*!< Force Timeout High-Speed Transmission */
+#define DSI_FIR1_FTOLPRX 0x00000002U /*!< Force Timeout Low-Power Reception */
+#define DSI_FIR1_FECCSE 0x00000004U /*!< Force ECC Single-bit Error */
+#define DSI_FIR1_FECCME 0x00000008U /*!< Force ECC Multi-bit Error */
+#define DSI_FIR1_FCRCE 0x00000010U /*!< Force CRC Error */
+#define DSI_FIR1_FPSE 0x00000020U /*!< Force Packet Size Error */
+#define DSI_FIR1_FEOTPE 0x00000040U /*!< Force EoTp Error */
+#define DSI_FIR1_FLPWRE 0x00000080U /*!< Force LTDC Payload Write Error */
+#define DSI_FIR1_FGCWRE 0x00000100U /*!< Force Generic Command Write Error */
+#define DSI_FIR1_FGPWRE 0x00000200U /*!< Force Generic Payload Write Error */
+#define DSI_FIR1_FGPTXE 0x00000400U /*!< Force Generic Payload Transmit Error */
+#define DSI_FIR1_FGPRDE 0x00000800U /*!< Force Generic Payload Read Error */
+#define DSI_FIR1_FGPRXE 0x00001000U /*!< Force Generic Payload Receive Error */
+
+/******************* Bit definition for DSI_VSCR register ***************/
+#define DSI_VSCR_EN 0x00000001U /*!< Enable */
+#define DSI_VSCR_UR 0x00000100U /*!< Update Register */
+
+/******************* Bit definition for DSI_LCVCIDR register ************/
+#define DSI_LCVCIDR_VCID 0x00000003U /*!< Virtual Channel ID */
+#define DSI_LCVCIDR_VCID0 0x00000001U
+#define DSI_LCVCIDR_VCID1 0x00000002U
+
+/******************* Bit definition for DSI_LCCCR register **************/
+#define DSI_LCCCR_COLC 0x0000000FU /*!< Color Coding */
+#define DSI_LCCCR_COLC0 0x00000001U
+#define DSI_LCCCR_COLC1 0x00000002U
+#define DSI_LCCCR_COLC2 0x00000004U
+#define DSI_LCCCR_COLC3 0x00000008U
+
+#define DSI_LCCCR_LPE 0x00000100U /*!< Loosely Packed Enable */
+
+/******************* Bit definition for DSI_LPMCCR register *************/
+#define DSI_LPMCCR_VLPSIZE 0x000000FFU /*!< VACT Largest Packet Size */
+#define DSI_LPMCCR_VLPSIZE0 0x00000001U
+#define DSI_LPMCCR_VLPSIZE1 0x00000002U
+#define DSI_LPMCCR_VLPSIZE2 0x00000004U
+#define DSI_LPMCCR_VLPSIZE3 0x00000008U
+#define DSI_LPMCCR_VLPSIZE4 0x00000010U
+#define DSI_LPMCCR_VLPSIZE5 0x00000020U
+#define DSI_LPMCCR_VLPSIZE6 0x00000040U
+#define DSI_LPMCCR_VLPSIZE7 0x00000080U
+
+#define DSI_LPMCCR_LPSIZE 0x00FF0000U /*!< Largest Packet Size */
+#define DSI_LPMCCR_LPSIZE0 0x00010000U
+#define DSI_LPMCCR_LPSIZE1 0x00020000U
+#define DSI_LPMCCR_LPSIZE2 0x00040000U
+#define DSI_LPMCCR_LPSIZE3 0x00080000U
+#define DSI_LPMCCR_LPSIZE4 0x00100000U
+#define DSI_LPMCCR_LPSIZE5 0x00200000U
+#define DSI_LPMCCR_LPSIZE6 0x00400000U
+#define DSI_LPMCCR_LPSIZE7 0x00800000U
+
+/******************* Bit definition for DSI_VMCCR register **************/
+#define DSI_VMCCR_VMT 0x00000003U /*!< Video Mode Type */
+#define DSI_VMCCR_VMT0 0x00000001U
+#define DSI_VMCCR_VMT1 0x00000002U
+
+#define DSI_VMCCR_LPVSAE 0x00000100U /*!< Low-power Vertical Sync time Enable */
+#define DSI_VMCCR_LPVBPE 0x00000200U /*!< Low-power Vertical Back-porch Enable */
+#define DSI_VMCCR_LPVFPE 0x00000400U /*!< Low-power Vertical Front-porch Enable */
+#define DSI_VMCCR_LPVAE 0x00000800U /*!< Low-power Vertical Active Enable */
+#define DSI_VMCCR_LPHBPE 0x00001000U /*!< Low-power Horizontal Back-porch Enable */
+#define DSI_VMCCR_LPHFE 0x00002000U /*!< Low-power Horizontal Front-porch Enable */
+#define DSI_VMCCR_FBTAAE 0x00004000U /*!< Frame BTA Acknowledge Enable */
+#define DSI_VMCCR_LPCE 0x00008000U /*!< Low-power Command Enable */
+
+/******************* Bit definition for DSI_VPCCR register **************/
+#define DSI_VPCCR_VPSIZE 0x00003FFFU /*!< Video Packet Size */
+#define DSI_VPCCR_VPSIZE0 0x00000001U
+#define DSI_VPCCR_VPSIZE1 0x00000002U
+#define DSI_VPCCR_VPSIZE2 0x00000004U
+#define DSI_VPCCR_VPSIZE3 0x00000008U
+#define DSI_VPCCR_VPSIZE4 0x00000010U
+#define DSI_VPCCR_VPSIZE5 0x00000020U
+#define DSI_VPCCR_VPSIZE6 0x00000040U
+#define DSI_VPCCR_VPSIZE7 0x00000080U
+#define DSI_VPCCR_VPSIZE8 0x00000100U
+#define DSI_VPCCR_VPSIZE9 0x00000200U
+#define DSI_VPCCR_VPSIZE10 0x00000400U
+#define DSI_VPCCR_VPSIZE11 0x00000800U
+#define DSI_VPCCR_VPSIZE12 0x00001000U
+#define DSI_VPCCR_VPSIZE13 0x00002000U
+
+/******************* Bit definition for DSI_VCCCR register **************/
+#define DSI_VCCCR_NUMC 0x00001FFFU /*!< Number of Chunks */
+#define DSI_VCCCR_NUMC0 0x00000001U
+#define DSI_VCCCR_NUMC1 0x00000002U
+#define DSI_VCCCR_NUMC2 0x00000004U
+#define DSI_VCCCR_NUMC3 0x00000008U
+#define DSI_VCCCR_NUMC4 0x00000010U
+#define DSI_VCCCR_NUMC5 0x00000020U
+#define DSI_VCCCR_NUMC6 0x00000040U
+#define DSI_VCCCR_NUMC7 0x00000080U
+#define DSI_VCCCR_NUMC8 0x00000100U
+#define DSI_VCCCR_NUMC9 0x00000200U
+#define DSI_VCCCR_NUMC10 0x00000400U
+#define DSI_VCCCR_NUMC11 0x00000800U
+#define DSI_VCCCR_NUMC12 0x00001000U
+
+/******************* Bit definition for DSI_VNPCCR register *************/
+#define DSI_VNPCCR_NPSIZE 0x00001FFFU /*!< Number of Chunks */
+#define DSI_VNPCCR_NPSIZE0 0x00000001U
+#define DSI_VNPCCR_NPSIZE1 0x00000002U
+#define DSI_VNPCCR_NPSIZE2 0x00000004U
+#define DSI_VNPCCR_NPSIZE3 0x00000008U
+#define DSI_VNPCCR_NPSIZE4 0x00000010U
+#define DSI_VNPCCR_NPSIZE5 0x00000020U
+#define DSI_VNPCCR_NPSIZE6 0x00000040U
+#define DSI_VNPCCR_NPSIZE7 0x00000080U
+#define DSI_VNPCCR_NPSIZE8 0x00000100U
+#define DSI_VNPCCR_NPSIZE9 0x00000200U
+#define DSI_VNPCCR_NPSIZE10 0x00000400U
+#define DSI_VNPCCR_NPSIZE11 0x00000800U
+#define DSI_VNPCCR_NPSIZE12 0x00001000U
+
+/******************* Bit definition for DSI_VHSACCR register ************/
+#define DSI_VHSACCR_HSA 0x00000FFFU /*!< Horizontal Synchronism Active duration */
+#define DSI_VHSACCR_HSA0 0x00000001U
+#define DSI_VHSACCR_HSA1 0x00000002U
+#define DSI_VHSACCR_HSA2 0x00000004U
+#define DSI_VHSACCR_HSA3 0x00000008U
+#define DSI_VHSACCR_HSA4 0x00000010U
+#define DSI_VHSACCR_HSA5 0x00000020U
+#define DSI_VHSACCR_HSA6 0x00000040U
+#define DSI_VHSACCR_HSA7 0x00000080U
+#define DSI_VHSACCR_HSA8 0x00000100U
+#define DSI_VHSACCR_HSA9 0x00000200U
+#define DSI_VHSACCR_HSA10 0x00000400U
+#define DSI_VHSACCR_HSA11 0x00000800U
+
+/******************* Bit definition for DSI_VHBPCCR register ************/
+#define DSI_VHBPCCR_HBP 0x00000FFFU /*!< Horizontal Back-Porch duration */
+#define DSI_VHBPCCR_HBP0 0x00000001U
+#define DSI_VHBPCCR_HBP1 0x00000002U
+#define DSI_VHBPCCR_HBP2 0x00000004U
+#define DSI_VHBPCCR_HBP3 0x00000008U
+#define DSI_VHBPCCR_HBP4 0x00000010U
+#define DSI_VHBPCCR_HBP5 0x00000020U
+#define DSI_VHBPCCR_HBP6 0x00000040U
+#define DSI_VHBPCCR_HBP7 0x00000080U
+#define DSI_VHBPCCR_HBP8 0x00000100U
+#define DSI_VHBPCCR_HBP9 0x00000200U
+#define DSI_VHBPCCR_HBP10 0x00000400U
+#define DSI_VHBPCCR_HBP11 0x00000800U
+
+/******************* Bit definition for DSI_VLCCR register **************/
+#define DSI_VLCCR_HLINE 0x00007FFFU /*!< Horizontal Line duration */
+#define DSI_VLCCR_HLINE0 0x00000001U
+#define DSI_VLCCR_HLINE1 0x00000002U
+#define DSI_VLCCR_HLINE2 0x00000004U
+#define DSI_VLCCR_HLINE3 0x00000008U
+#define DSI_VLCCR_HLINE4 0x00000010U
+#define DSI_VLCCR_HLINE5 0x00000020U
+#define DSI_VLCCR_HLINE6 0x00000040U
+#define DSI_VLCCR_HLINE7 0x00000080U
+#define DSI_VLCCR_HLINE8 0x00000100U
+#define DSI_VLCCR_HLINE9 0x00000200U
+#define DSI_VLCCR_HLINE10 0x00000400U
+#define DSI_VLCCR_HLINE11 0x00000800U
+#define DSI_VLCCR_HLINE12 0x00001000U
+#define DSI_VLCCR_HLINE13 0x00002000U
+#define DSI_VLCCR_HLINE14 0x00004000U
+
+/******************* Bit definition for DSI_VVSACCR register ***************/
+#define DSI_VVSACCR_VSA 0x000003FFU /*!< Vertical Synchronism Active duration */
+#define DSI_VVSACCR_VSA0 0x00000001U
+#define DSI_VVSACCR_VSA1 0x00000002U
+#define DSI_VVSACCR_VSA2 0x00000004U
+#define DSI_VVSACCR_VSA3 0x00000008U
+#define DSI_VVSACCR_VSA4 0x00000010U
+#define DSI_VVSACCR_VSA5 0x00000020U
+#define DSI_VVSACCR_VSA6 0x00000040U
+#define DSI_VVSACCR_VSA7 0x00000080U
+#define DSI_VVSACCR_VSA8 0x00000100U
+#define DSI_VVSACCR_VSA9 0x00000200U
+
+/******************* Bit definition for DSI_VVBPCCR register ************/
+#define DSI_VVBPCCR_VBP 0x000003FFU /*!< Vertical Back-Porch duration */
+#define DSI_VVBPCCR_VBP0 0x00000001U
+#define DSI_VVBPCCR_VBP1 0x00000002U
+#define DSI_VVBPCCR_VBP2 0x00000004U
+#define DSI_VVBPCCR_VBP3 0x00000008U
+#define DSI_VVBPCCR_VBP4 0x00000010U
+#define DSI_VVBPCCR_VBP5 0x00000020U
+#define DSI_VVBPCCR_VBP6 0x00000040U
+#define DSI_VVBPCCR_VBP7 0x00000080U
+#define DSI_VVBPCCR_VBP8 0x00000100U
+#define DSI_VVBPCCR_VBP9 0x00000200U
+
+/******************* Bit definition for DSI_VVFPCCR register ************/
+#define DSI_VVFPCCR_VFP 0x000003FFU /*!< Vertical Front-Porch duration */
+#define DSI_VVFPCCR_VFP0 0x00000001U
+#define DSI_VVFPCCR_VFP1 0x00000002U
+#define DSI_VVFPCCR_VFP2 0x00000004U
+#define DSI_VVFPCCR_VFP3 0x00000008U
+#define DSI_VVFPCCR_VFP4 0x00000010U
+#define DSI_VVFPCCR_VFP5 0x00000020U
+#define DSI_VVFPCCR_VFP6 0x00000040U
+#define DSI_VVFPCCR_VFP7 0x00000080U
+#define DSI_VVFPCCR_VFP8 0x00000100U
+#define DSI_VVFPCCR_VFP9 0x00000200U
+
+/******************* Bit definition for DSI_VVACCR register *************/
+#define DSI_VVACCR_VA 0x00003FFFU /*!< Vertical Active duration */
+#define DSI_VVACCR_VA0 0x00000001U
+#define DSI_VVACCR_VA1 0x00000002U
+#define DSI_VVACCR_VA2 0x00000004U
+#define DSI_VVACCR_VA3 0x00000008U
+#define DSI_VVACCR_VA4 0x00000010U
+#define DSI_VVACCR_VA5 0x00000020U
+#define DSI_VVACCR_VA6 0x00000040U
+#define DSI_VVACCR_VA7 0x00000080U
+#define DSI_VVACCR_VA8 0x00000100U
+#define DSI_VVACCR_VA9 0x00000200U
+#define DSI_VVACCR_VA10 0x00000400U
+#define DSI_VVACCR_VA11 0x00000800U
+#define DSI_VVACCR_VA12 0x00001000U
+#define DSI_VVACCR_VA13 0x00002000U
+
+/******************* Bit definition for DSI_TDCCR register **************/
+#define DSI_TDCCR_3DM 0x00000003U /*!< 3D Mode */
+#define DSI_TDCCR_3DM0 0x00000001U
+#define DSI_TDCCR_3DM1 0x00000002U
+
+#define DSI_TDCCR_3DF 0x0000000CU /*!< 3D Format */
+#define DSI_TDCCR_3DF0 0x00000004U
+#define DSI_TDCCR_3DF1 0x00000008U
+
+#define DSI_TDCCR_SVS 0x00000010U /*!< Second VSYNC */
+#define DSI_TDCCR_RF 0x00000020U /*!< Right First */
+#define DSI_TDCCR_S3DC 0x00010000U /*!< Send 3D Control */
+
+/******************* Bit definition for DSI_WCFGR register ***************/
+#define DSI_WCFGR_DSIM 0x00000001U /*!< DSI Mode */
+#define DSI_WCFGR_COLMUX 0x0000000EU /*!< Color Multiplexing */
+#define DSI_WCFGR_COLMUX0 0x00000002U
+#define DSI_WCFGR_COLMUX1 0x00000004U
+#define DSI_WCFGR_COLMUX2 0x00000008U
+
+#define DSI_WCFGR_TESRC 0x00000010U /*!< Tearing Effect Source */
+#define DSI_WCFGR_TEPOL 0x00000020U /*!< Tearing Effect Polarity */
+#define DSI_WCFGR_AR 0x00000040U /*!< Automatic Refresh */
+#define DSI_WCFGR_VSPOL 0x00000080U /*!< VSync Polarity */
+
+/******************* Bit definition for DSI_WCR register *****************/
+#define DSI_WCR_COLM 0x00000001U /*!< Color Mode */
+#define DSI_WCR_SHTDN 0x00000002U /*!< Shutdown */
+#define DSI_WCR_LTDCEN 0x00000004U /*!< LTDC Enable */
+#define DSI_WCR_DSIEN 0x00000008U /*!< DSI Enable */
+
+/******************* Bit definition for DSI_WIER register ****************/
+#define DSI_WIER_TEIE 0x00000001U /*!< Tearing Effect Interrupt Enable */
+#define DSI_WIER_ERIE 0x00000002U /*!< End of Refresh Interrupt Enable */
+#define DSI_WIER_PLLLIE 0x00000200U /*!< PLL Lock Interrupt Enable */
+#define DSI_WIER_PLLUIE 0x00000400U /*!< PLL Unlock Interrupt Enable */
+#define DSI_WIER_RRIE 0x00002000U /*!< Regulator Ready Interrupt Enable */
+
+/******************* Bit definition for DSI_WISR register ****************/
+#define DSI_WISR_TEIF 0x00000001U /*!< Tearing Effect Interrupt Flag */
+#define DSI_WISR_ERIF 0x00000002U /*!< End of Refresh Interrupt Flag */
+#define DSI_WISR_BUSY 0x00000004U /*!< Busy Flag */
+#define DSI_WISR_PLLLS 0x00000100U /*!< PLL Lock Status */
+#define DSI_WISR_PLLLIF 0x00000200U /*!< PLL Lock Interrupt Flag */
+#define DSI_WISR_PLLUIF 0x00000400U /*!< PLL Unlock Interrupt Flag */
+#define DSI_WISR_RRS 0x00001000U /*!< Regulator Ready Flag */
+#define DSI_WISR_RRIF 0x00002000U /*!< Regulator Ready Interrupt Flag */
+
+/******************* Bit definition for DSI_WIFCR register ***************/
+#define DSI_WIFCR_CTEIF 0x00000001U /*!< Clear Tearing Effect Interrupt Flag */
+#define DSI_WIFCR_CERIF 0x00000002U /*!< Clear End of Refresh Interrupt Flag */
+#define DSI_WIFCR_CPLLLIF 0x00000200U /*!< Clear PLL Lock Interrupt Flag */
+#define DSI_WIFCR_CPLLUIF 0x00000400U /*!< Clear PLL Unlock Interrupt Flag */
+#define DSI_WIFCR_CRRIF 0x00002000U /*!< Clear Regulator Ready Interrupt Flag */
+
+/******************* Bit definition for DSI_WPCR0 register ***************/
+#define DSI_WPCR0_UIX4 0x0000003FU /*!< Unit Interval multiplied by 4 */
+#define DSI_WPCR0_UIX4_0 0x00000001U
+#define DSI_WPCR0_UIX4_1 0x00000002U
+#define DSI_WPCR0_UIX4_2 0x00000004U
+#define DSI_WPCR0_UIX4_3 0x00000008U
+#define DSI_WPCR0_UIX4_4 0x00000010U
+#define DSI_WPCR0_UIX4_5 0x00000020U
+
+#define DSI_WPCR0_SWCL 0x00000040U /*!< Swap pins on clock lane */
+#define DSI_WPCR0_SWDL0 0x00000080U /*!< Swap pins on data lane 1 */
+#define DSI_WPCR0_SWDL1 0x00000100U /*!< Swap pins on data lane 2 */
+#define DSI_WPCR0_HSICL 0x00000200U /*!< Invert the high-speed data signal on clock lane */
+#define DSI_WPCR0_HSIDL0 0x00000400U /*!< Invert the high-speed data signal on lane 1 */
+#define DSI_WPCR0_HSIDL1 0x00000800U /*!< Invert the high-speed data signal on lane 2 */
+#define DSI_WPCR0_FTXSMCL 0x00001000U /*!< Force clock lane in TX stop mode */
+#define DSI_WPCR0_FTXSMDL 0x00002000U /*!< Force data lanes in TX stop mode */
+#define DSI_WPCR0_CDOFFDL 0x00004000U /*!< Contention detection OFF */
+#define DSI_WPCR0_TDDL 0x00010000U /*!< Turn Disable Data Lanes */
+#define DSI_WPCR0_PDEN 0x00040000U /*!< Pull-Down Enable */
+#define DSI_WPCR0_TCLKPREPEN 0x00080000U /*!< Timer for t-CLKPREP Enable */
+#define DSI_WPCR0_TCLKZEROEN 0x00100000U /*!< Timer for t-CLKZERO Enable */
+#define DSI_WPCR0_THSPREPEN 0x00200000U /*!< Timer for t-HSPREP Enable */
+#define DSI_WPCR0_THSTRAILEN 0x00400000U /*!< Timer for t-HSTRAIL Enable */
+#define DSI_WPCR0_THSZEROEN 0x00800000U /*!< Timer for t-HSZERO Enable */
+#define DSI_WPCR0_TLPXDEN 0x01000000U /*!< Timer for t-LPXD Enable */
+#define DSI_WPCR0_THSEXITEN 0x02000000U /*!< Timer for t-HSEXIT Enable */
+#define DSI_WPCR0_TLPXCEN 0x04000000U /*!< Timer for t-LPXC Enable */
+#define DSI_WPCR0_TCLKPOSTEN 0x08000000U /*!< Timer for t-CLKPOST Enable */
+
+/******************* Bit definition for DSI_WPCR1 register ***************/
+#define DSI_WPCR1_HSTXDCL 0x00000003U /*!< High-Speed Transmission Delay on Clock Lane */
+#define DSI_WPCR1_HSTXDCL0 0x00000001U
+#define DSI_WPCR1_HSTXDCL1 0x00000002U
+
+#define DSI_WPCR1_HSTXDDL 0x0000000CU /*!< High-Speed Transmission Delay on Data Lane */
+#define DSI_WPCR1_HSTXDDL0 0x00000004U
+#define DSI_WPCR1_HSTXDDL1 0x00000008U
+
+#define DSI_WPCR1_LPSRCCL 0x000000C0U /*!< Low-Power transmission Slew Rate Compensation on Clock Lane */
+#define DSI_WPCR1_LPSRCCL0 0x00000040U
+#define DSI_WPCR1_LPSRCCL1 0x00000080U
+
+#define DSI_WPCR1_LPSRCDL 0x00000300U /*!< Low-Power transmission Slew Rate Compensation on Data Lane */
+#define DSI_WPCR1_LPSRCDL0 0x00000100U
+#define DSI_WPCR1_LPSRCDL1 0x00000200U
+
+#define DSI_WPCR1_SDDC 0x00001000U /*!< SDD Control */
+
+#define DSI_WPCR1_LPRXVCDL 0x0000C000U /*!< Low-Power Reception V-IL Compensation on Data Lanes */
+#define DSI_WPCR1_LPRXVCDL0 0x00004000U
+#define DSI_WPCR1_LPRXVCDL1 0x00008000U
+
+#define DSI_WPCR1_HSTXSRCCL 0x00030000U /*!< High-Speed Transmission Delay on Clock Lane */
+#define DSI_WPCR1_HSTXSRCCL0 0x00010000U
+#define DSI_WPCR1_HSTXSRCCL1 0x00020000U
+
+#define DSI_WPCR1_HSTXSRCDL 0x000C0000U /*!< High-Speed Transmission Delay on Data Lane */
+#define DSI_WPCR1_HSTXSRCDL0 0x00040000U
+#define DSI_WPCR1_HSTXSRCDL1 0x00080000U
+
+#define DSI_WPCR1_FLPRXLPM 0x00400000U /*!< Forces LP Receiver in Low-Power Mode */
+
+#define DSI_WPCR1_LPRXFT 0x06000000U /*!< Low-Power RX low-pass Filtering Tuning */
+#define DSI_WPCR1_LPRXFT0 0x02000000U
+#define DSI_WPCR1_LPRXFT1 0x04000000U
+
+/******************* Bit definition for DSI_WPCR2 register ***************/
+#define DSI_WPCR2_TCLKPREP 0x000000FFU /*!< t-CLKPREP */
+#define DSI_WPCR2_TCLKPREP0 0x00000001U
+#define DSI_WPCR2_TCLKPREP1 0x00000002U
+#define DSI_WPCR2_TCLKPREP2 0x00000004U
+#define DSI_WPCR2_TCLKPREP3 0x00000008U
+#define DSI_WPCR2_TCLKPREP4 0x00000010U
+#define DSI_WPCR2_TCLKPREP5 0x00000020U
+#define DSI_WPCR2_TCLKPREP6 0x00000040U
+#define DSI_WPCR2_TCLKPREP7 0x00000080U
+
+#define DSI_WPCR2_TCLKZERO 0x0000FF00U /*!< t-CLKZERO */
+#define DSI_WPCR2_TCLKZERO0 0x00000100U
+#define DSI_WPCR2_TCLKZERO1 0x00000200U
+#define DSI_WPCR2_TCLKZERO2 0x00000400U
+#define DSI_WPCR2_TCLKZERO3 0x00000800U
+#define DSI_WPCR2_TCLKZERO4 0x00001000U
+#define DSI_WPCR2_TCLKZERO5 0x00002000U
+#define DSI_WPCR2_TCLKZERO6 0x00004000U
+#define DSI_WPCR2_TCLKZERO7 0x00008000U
+
+#define DSI_WPCR2_THSPREP 0x00FF0000U /*!< t-HSPREP */
+#define DSI_WPCR2_THSPREP0 0x00010000U
+#define DSI_WPCR2_THSPREP1 0x00020000U
+#define DSI_WPCR2_THSPREP2 0x00040000U
+#define DSI_WPCR2_THSPREP3 0x00080000U
+#define DSI_WPCR2_THSPREP4 0x00100000U
+#define DSI_WPCR2_THSPREP5 0x00200000U
+#define DSI_WPCR2_THSPREP6 0x00400000U
+#define DSI_WPCR2_THSPREP7 0x00800000U
+
+#define DSI_WPCR2_THSTRAIL 0xFF000000U /*!< t-HSTRAIL */
+#define DSI_WPCR2_THSTRAIL0 0x01000000U
+#define DSI_WPCR2_THSTRAIL1 0x02000000U
+#define DSI_WPCR2_THSTRAIL2 0x04000000U
+#define DSI_WPCR2_THSTRAIL3 0x08000000U
+#define DSI_WPCR2_THSTRAIL4 0x10000000U
+#define DSI_WPCR2_THSTRAIL5 0x20000000U
+#define DSI_WPCR2_THSTRAIL6 0x40000000U
+#define DSI_WPCR2_THSTRAIL7 0x80000000U
+
+/******************* Bit definition for DSI_WPCR3 register ***************/
+#define DSI_WPCR3_THSZERO 0x000000FFU /*!< t-HSZERO */
+#define DSI_WPCR3_THSZERO0 0x00000001U
+#define DSI_WPCR3_THSZERO1 0x00000002U
+#define DSI_WPCR3_THSZERO2 0x00000004U
+#define DSI_WPCR3_THSZERO3 0x00000008U
+#define DSI_WPCR3_THSZERO4 0x00000010U
+#define DSI_WPCR3_THSZERO5 0x00000020U
+#define DSI_WPCR3_THSZERO6 0x00000040U
+#define DSI_WPCR3_THSZERO7 0x00000080U
+
+#define DSI_WPCR3_TLPXD 0x0000FF00U /*!< t-LPXD */
+#define DSI_WPCR3_TLPXD0 0x00000100U
+#define DSI_WPCR3_TLPXD1 0x00000200U
+#define DSI_WPCR3_TLPXD2 0x00000400U
+#define DSI_WPCR3_TLPXD3 0x00000800U
+#define DSI_WPCR3_TLPXD4 0x00001000U
+#define DSI_WPCR3_TLPXD5 0x00002000U
+#define DSI_WPCR3_TLPXD6 0x00004000U
+#define DSI_WPCR3_TLPXD7 0x00008000U
+
+#define DSI_WPCR3_THSEXIT 0x00FF0000U /*!< t-HSEXIT */
+#define DSI_WPCR3_THSEXIT0 0x00010000U
+#define DSI_WPCR3_THSEXIT1 0x00020000U
+#define DSI_WPCR3_THSEXIT2 0x00040000U
+#define DSI_WPCR3_THSEXIT3 0x00080000U
+#define DSI_WPCR3_THSEXIT4 0x00100000U
+#define DSI_WPCR3_THSEXIT5 0x00200000U
+#define DSI_WPCR3_THSEXIT6 0x00400000U
+#define DSI_WPCR3_THSEXIT7 0x00800000U
+
+#define DSI_WPCR3_TLPXC 0xFF000000U /*!< t-LPXC */
+#define DSI_WPCR3_TLPXC0 0x01000000U
+#define DSI_WPCR3_TLPXC1 0x02000000U
+#define DSI_WPCR3_TLPXC2 0x04000000U
+#define DSI_WPCR3_TLPXC3 0x08000000U
+#define DSI_WPCR3_TLPXC4 0x10000000U
+#define DSI_WPCR3_TLPXC5 0x20000000U
+#define DSI_WPCR3_TLPXC6 0x40000000U
+#define DSI_WPCR3_TLPXC7 0x80000000U
+
+/******************* Bit definition for DSI_WPCR4 register ***************/
+#define DSI_WPCR4_TCLKPOST 0x000000FFU /*!< t-CLKPOST */
+#define DSI_WPCR4_TCLKPOST0 0x00000001U
+#define DSI_WPCR4_TCLKPOST1 0x00000002U
+#define DSI_WPCR4_TCLKPOST2 0x00000004U
+#define DSI_WPCR4_TCLKPOST3 0x00000008U
+#define DSI_WPCR4_TCLKPOST4 0x00000010U
+#define DSI_WPCR4_TCLKPOST5 0x00000020U
+#define DSI_WPCR4_TCLKPOST6 0x00000040U
+#define DSI_WPCR4_TCLKPOST7 0x00000080U
+
+/******************* Bit definition for DSI_WRPCR register ***************/
+#define DSI_WRPCR_PLLEN 0x00000001U /*!< PLL Enable */
+#define DSI_WRPCR_PLL_NDIV 0x000001FCU /*!< PLL Loop Division Factor */
+#define DSI_WRPCR_PLL_NDIV0 0x00000004U
+#define DSI_WRPCR_PLL_NDIV1 0x00000008U
+#define DSI_WRPCR_PLL_NDIV2 0x00000010U
+#define DSI_WRPCR_PLL_NDIV3 0x00000020U
+#define DSI_WRPCR_PLL_NDIV4 0x00000040U
+#define DSI_WRPCR_PLL_NDIV5 0x00000080U
+#define DSI_WRPCR_PLL_NDIV6 0x00000100U
+
+#define DSI_WRPCR_PLL_IDF 0x00007800U /*!< PLL Input Division Factor */
+#define DSI_WRPCR_PLL_IDF0 0x00000800U
+#define DSI_WRPCR_PLL_IDF1 0x00001000U
+#define DSI_WRPCR_PLL_IDF2 0x00002000U
+#define DSI_WRPCR_PLL_IDF3 0x00004000U
+
+#define DSI_WRPCR_PLL_ODF 0x00030000U /*!< PLL Output Division Factor */
+#define DSI_WRPCR_PLL_ODF0 0x00010000U
+#define DSI_WRPCR_PLL_ODF1 0x00020000U
+
+#define DSI_WRPCR_REGEN 0x01000000U /*!< Regulator Enable */
+
+/******************************************************************************/
+/* */
+/* External Interrupt/Event Controller */
+/* */
+/******************************************************************************/
+/******************* Bit definition for EXTI_IMR register *******************/
+#define EXTI_IMR_MR0 0x00000001U /*!< Interrupt Mask on line 0 */
+#define EXTI_IMR_MR1 0x00000002U /*!< Interrupt Mask on line 1 */
+#define EXTI_IMR_MR2 0x00000004U /*!< Interrupt Mask on line 2 */
+#define EXTI_IMR_MR3 0x00000008U /*!< Interrupt Mask on line 3 */
+#define EXTI_IMR_MR4 0x00000010U /*!< Interrupt Mask on line 4 */
+#define EXTI_IMR_MR5 0x00000020U /*!< Interrupt Mask on line 5 */
+#define EXTI_IMR_MR6 0x00000040U /*!< Interrupt Mask on line 6 */
+#define EXTI_IMR_MR7 0x00000080U /*!< Interrupt Mask on line 7 */
+#define EXTI_IMR_MR8 0x00000100U /*!< Interrupt Mask on line 8 */
+#define EXTI_IMR_MR9 0x00000200U /*!< Interrupt Mask on line 9 */
+#define EXTI_IMR_MR10 0x00000400U /*!< Interrupt Mask on line 10 */
+#define EXTI_IMR_MR11 0x00000800U /*!< Interrupt Mask on line 11 */
+#define EXTI_IMR_MR12 0x00001000U /*!< Interrupt Mask on line 12 */
+#define EXTI_IMR_MR13 0x00002000U /*!< Interrupt Mask on line 13 */
+#define EXTI_IMR_MR14 0x00004000U /*!< Interrupt Mask on line 14 */
+#define EXTI_IMR_MR15 0x00008000U /*!< Interrupt Mask on line 15 */
+#define EXTI_IMR_MR16 0x00010000U /*!< Interrupt Mask on line 16 */
+#define EXTI_IMR_MR17 0x00020000U /*!< Interrupt Mask on line 17 */
+#define EXTI_IMR_MR18 0x00040000U /*!< Interrupt Mask on line 18 */
+#define EXTI_IMR_MR19 0x00080000U /*!< Interrupt Mask on line 19 */
+#define EXTI_IMR_MR20 0x00100000U /*!< Interrupt Mask on line 20 */
+#define EXTI_IMR_MR21 0x00200000U /*!< Interrupt Mask on line 21 */
+#define EXTI_IMR_MR22 0x00400000U /*!< Interrupt Mask on line 22 */
+
+/******************* Bit definition for EXTI_EMR register *******************/
+#define EXTI_EMR_MR0 0x00000001U /*!< Event Mask on line 0 */
+#define EXTI_EMR_MR1 0x00000002U /*!< Event Mask on line 1 */
+#define EXTI_EMR_MR2 0x00000004U /*!< Event Mask on line 2 */
+#define EXTI_EMR_MR3 0x00000008U /*!< Event Mask on line 3 */
+#define EXTI_EMR_MR4 0x00000010U /*!< Event Mask on line 4 */
+#define EXTI_EMR_MR5 0x00000020U /*!< Event Mask on line 5 */
+#define EXTI_EMR_MR6 0x00000040U /*!< Event Mask on line 6 */
+#define EXTI_EMR_MR7 0x00000080U /*!< Event Mask on line 7 */
+#define EXTI_EMR_MR8 0x00000100U /*!< Event Mask on line 8 */
+#define EXTI_EMR_MR9 0x00000200U /*!< Event Mask on line 9 */
+#define EXTI_EMR_MR10 0x00000400U /*!< Event Mask on line 10 */
+#define EXTI_EMR_MR11 0x00000800U /*!< Event Mask on line 11 */
+#define EXTI_EMR_MR12 0x00001000U /*!< Event Mask on line 12 */
+#define EXTI_EMR_MR13 0x00002000U /*!< Event Mask on line 13 */
+#define EXTI_EMR_MR14 0x00004000U /*!< Event Mask on line 14 */
+#define EXTI_EMR_MR15 0x00008000U /*!< Event Mask on line 15 */
+#define EXTI_EMR_MR16 0x00010000U /*!< Event Mask on line 16 */
+#define EXTI_EMR_MR17 0x00020000U /*!< Event Mask on line 17 */
+#define EXTI_EMR_MR18 0x00040000U /*!< Event Mask on line 18 */
+#define EXTI_EMR_MR19 0x00080000U /*!< Event Mask on line 19 */
+#define EXTI_EMR_MR20 0x00100000U /*!< Event Mask on line 20 */
+#define EXTI_EMR_MR21 0x00200000U /*!< Event Mask on line 21 */
+#define EXTI_EMR_MR22 0x00400000U /*!< Event Mask on line 22 */
+
+/****************** Bit definition for EXTI_RTSR register *******************/
+#define EXTI_RTSR_TR0 0x00000001U /*!< Rising trigger event configuration bit of line 0 */
+#define EXTI_RTSR_TR1 0x00000002U /*!< Rising trigger event configuration bit of line 1 */
+#define EXTI_RTSR_TR2 0x00000004U /*!< Rising trigger event configuration bit of line 2 */
+#define EXTI_RTSR_TR3 0x00000008U /*!< Rising trigger event configuration bit of line 3 */
+#define EXTI_RTSR_TR4 0x00000010U /*!< Rising trigger event configuration bit of line 4 */
+#define EXTI_RTSR_TR5 0x00000020U /*!< Rising trigger event configuration bit of line 5 */
+#define EXTI_RTSR_TR6 0x00000040U /*!< Rising trigger event configuration bit of line 6 */
+#define EXTI_RTSR_TR7 0x00000080U /*!< Rising trigger event configuration bit of line 7 */
+#define EXTI_RTSR_TR8 0x00000100U /*!< Rising trigger event configuration bit of line 8 */
+#define EXTI_RTSR_TR9 0x00000200U /*!< Rising trigger event configuration bit of line 9 */
+#define EXTI_RTSR_TR10 0x00000400U /*!< Rising trigger event configuration bit of line 10 */
+#define EXTI_RTSR_TR11 0x00000800U /*!< Rising trigger event configuration bit of line 11 */
+#define EXTI_RTSR_TR12 0x00001000U /*!< Rising trigger event configuration bit of line 12 */
+#define EXTI_RTSR_TR13 0x00002000U /*!< Rising trigger event configuration bit of line 13 */
+#define EXTI_RTSR_TR14 0x00004000U /*!< Rising trigger event configuration bit of line 14 */
+#define EXTI_RTSR_TR15 0x00008000U /*!< Rising trigger event configuration bit of line 15 */
+#define EXTI_RTSR_TR16 0x00010000U /*!< Rising trigger event configuration bit of line 16 */
+#define EXTI_RTSR_TR17 0x00020000U /*!< Rising trigger event configuration bit of line 17 */
+#define EXTI_RTSR_TR18 0x00040000U /*!< Rising trigger event configuration bit of line 18 */
+#define EXTI_RTSR_TR19 0x00080000U /*!< Rising trigger event configuration bit of line 19 */
+#define EXTI_RTSR_TR20 0x00100000U /*!< Rising trigger event configuration bit of line 20 */
+#define EXTI_RTSR_TR21 0x00200000U /*!< Rising trigger event configuration bit of line 21 */
+#define EXTI_RTSR_TR22 0x00400000U /*!< Rising trigger event configuration bit of line 22 */
+
+/****************** Bit definition for EXTI_FTSR register *******************/
+#define EXTI_FTSR_TR0 0x00000001U /*!< Falling trigger event configuration bit of line 0 */
+#define EXTI_FTSR_TR1 0x00000002U /*!< Falling trigger event configuration bit of line 1 */
+#define EXTI_FTSR_TR2 0x00000004U /*!< Falling trigger event configuration bit of line 2 */
+#define EXTI_FTSR_TR3 0x00000008U /*!< Falling trigger event configuration bit of line 3 */
+#define EXTI_FTSR_TR4 0x00000010U /*!< Falling trigger event configuration bit of line 4 */
+#define EXTI_FTSR_TR5 0x00000020U /*!< Falling trigger event configuration bit of line 5 */
+#define EXTI_FTSR_TR6 0x00000040U /*!< Falling trigger event configuration bit of line 6 */
+#define EXTI_FTSR_TR7 0x00000080U /*!< Falling trigger event configuration bit of line 7 */
+#define EXTI_FTSR_TR8 0x00000100U /*!< Falling trigger event configuration bit of line 8 */
+#define EXTI_FTSR_TR9 0x00000200U /*!< Falling trigger event configuration bit of line 9 */
+#define EXTI_FTSR_TR10 0x00000400U /*!< Falling trigger event configuration bit of line 10 */
+#define EXTI_FTSR_TR11 0x00000800U /*!< Falling trigger event configuration bit of line 11 */
+#define EXTI_FTSR_TR12 0x00001000U /*!< Falling trigger event configuration bit of line 12 */
+#define EXTI_FTSR_TR13 0x00002000U /*!< Falling trigger event configuration bit of line 13 */
+#define EXTI_FTSR_TR14 0x00004000U /*!< Falling trigger event configuration bit of line 14 */
+#define EXTI_FTSR_TR15 0x00008000U /*!< Falling trigger event configuration bit of line 15 */
+#define EXTI_FTSR_TR16 0x00010000U /*!< Falling trigger event configuration bit of line 16 */
+#define EXTI_FTSR_TR17 0x00020000U /*!< Falling trigger event configuration bit of line 17 */
+#define EXTI_FTSR_TR18 0x00040000U /*!< Falling trigger event configuration bit of line 18 */
+#define EXTI_FTSR_TR19 0x00080000U /*!< Falling trigger event configuration bit of line 19 */
+#define EXTI_FTSR_TR20 0x00100000U /*!< Falling trigger event configuration bit of line 20 */
+#define EXTI_FTSR_TR21 0x00200000U /*!< Falling trigger event configuration bit of line 21 */
+#define EXTI_FTSR_TR22 0x00400000U /*!< Falling trigger event configuration bit of line 22 */
+
+/****************** Bit definition for EXTI_SWIER register ******************/
+#define EXTI_SWIER_SWIER0 0x00000001U /*!< Software Interrupt on line 0 */
+#define EXTI_SWIER_SWIER1 0x00000002U /*!< Software Interrupt on line 1 */
+#define EXTI_SWIER_SWIER2 0x00000004U /*!< Software Interrupt on line 2 */
+#define EXTI_SWIER_SWIER3 0x00000008U /*!< Software Interrupt on line 3 */
+#define EXTI_SWIER_SWIER4 0x00000010U /*!< Software Interrupt on line 4 */
+#define EXTI_SWIER_SWIER5 0x00000020U /*!< Software Interrupt on line 5 */
+#define EXTI_SWIER_SWIER6 0x00000040U /*!< Software Interrupt on line 6 */
+#define EXTI_SWIER_SWIER7 0x00000080U /*!< Software Interrupt on line 7 */
+#define EXTI_SWIER_SWIER8 0x00000100U /*!< Software Interrupt on line 8 */
+#define EXTI_SWIER_SWIER9 0x00000200U /*!< Software Interrupt on line 9 */
+#define EXTI_SWIER_SWIER10 0x00000400U /*!< Software Interrupt on line 10 */
+#define EXTI_SWIER_SWIER11 0x00000800U /*!< Software Interrupt on line 11 */
+#define EXTI_SWIER_SWIER12 0x00001000U /*!< Software Interrupt on line 12 */
+#define EXTI_SWIER_SWIER13 0x00002000U /*!< Software Interrupt on line 13 */
+#define EXTI_SWIER_SWIER14 0x00004000U /*!< Software Interrupt on line 14 */
+#define EXTI_SWIER_SWIER15 0x00008000U /*!< Software Interrupt on line 15 */
+#define EXTI_SWIER_SWIER16 0x00010000U /*!< Software Interrupt on line 16 */
+#define EXTI_SWIER_SWIER17 0x00020000U /*!< Software Interrupt on line 17 */
+#define EXTI_SWIER_SWIER18 0x00040000U /*!< Software Interrupt on line 18 */
+#define EXTI_SWIER_SWIER19 0x00080000U /*!< Software Interrupt on line 19 */
+#define EXTI_SWIER_SWIER20 0x00100000U /*!< Software Interrupt on line 20 */
+#define EXTI_SWIER_SWIER21 0x00200000U /*!< Software Interrupt on line 21 */
+#define EXTI_SWIER_SWIER22 0x00400000U /*!< Software Interrupt on line 22 */
+
+/******************* Bit definition for EXTI_PR register ********************/
+#define EXTI_PR_PR0 0x00000001U /*!< Pending bit for line 0 */
+#define EXTI_PR_PR1 0x00000002U /*!< Pending bit for line 1 */
+#define EXTI_PR_PR2 0x00000004U /*!< Pending bit for line 2 */
+#define EXTI_PR_PR3 0x00000008U /*!< Pending bit for line 3 */
+#define EXTI_PR_PR4 0x00000010U /*!< Pending bit for line 4 */
+#define EXTI_PR_PR5 0x00000020U /*!< Pending bit for line 5 */
+#define EXTI_PR_PR6 0x00000040U /*!< Pending bit for line 6 */
+#define EXTI_PR_PR7 0x00000080U /*!< Pending bit for line 7 */
+#define EXTI_PR_PR8 0x00000100U /*!< Pending bit for line 8 */
+#define EXTI_PR_PR9 0x00000200U /*!< Pending bit for line 9 */
+#define EXTI_PR_PR10 0x00000400U /*!< Pending bit for line 10 */
+#define EXTI_PR_PR11 0x00000800U /*!< Pending bit for line 11 */
+#define EXTI_PR_PR12 0x00001000U /*!< Pending bit for line 12 */
+#define EXTI_PR_PR13 0x00002000U /*!< Pending bit for line 13 */
+#define EXTI_PR_PR14 0x00004000U /*!< Pending bit for line 14 */
+#define EXTI_PR_PR15 0x00008000U /*!< Pending bit for line 15 */
+#define EXTI_PR_PR16 0x00010000U /*!< Pending bit for line 16 */
+#define EXTI_PR_PR17 0x00020000U /*!< Pending bit for line 17 */
+#define EXTI_PR_PR18 0x00040000U /*!< Pending bit for line 18 */
+#define EXTI_PR_PR19 0x00080000U /*!< Pending bit for line 19 */
+#define EXTI_PR_PR20 0x00100000U /*!< Pending bit for line 20 */
+#define EXTI_PR_PR21 0x00200000U /*!< Pending bit for line 21 */
+#define EXTI_PR_PR22 0x00400000U /*!< Pending bit for line 22 */
+
+/******************************************************************************/
+/* */
+/* FLASH */
+/* */
+/******************************************************************************/
+/******************* Bits definition for FLASH_ACR register *****************/
+#define FLASH_ACR_LATENCY 0x0000000FU
+#define FLASH_ACR_LATENCY_0WS 0x00000000U
+#define FLASH_ACR_LATENCY_1WS 0x00000001U
+#define FLASH_ACR_LATENCY_2WS 0x00000002U
+#define FLASH_ACR_LATENCY_3WS 0x00000003U
+#define FLASH_ACR_LATENCY_4WS 0x00000004U
+#define FLASH_ACR_LATENCY_5WS 0x00000005U
+#define FLASH_ACR_LATENCY_6WS 0x00000006U
+#define FLASH_ACR_LATENCY_7WS 0x00000007U
+#define FLASH_ACR_LATENCY_8WS 0x00000008U
+#define FLASH_ACR_LATENCY_9WS 0x00000009U
+#define FLASH_ACR_LATENCY_10WS 0x0000000AU
+#define FLASH_ACR_LATENCY_11WS 0x0000000BU
+#define FLASH_ACR_LATENCY_12WS 0x0000000CU
+#define FLASH_ACR_LATENCY_13WS 0x0000000DU
+#define FLASH_ACR_LATENCY_14WS 0x0000000EU
+#define FLASH_ACR_LATENCY_15WS 0x0000000FU
+#define FLASH_ACR_PRFTEN 0x00000100U
+#define FLASH_ACR_ICEN 0x00000200U
+#define FLASH_ACR_DCEN 0x00000400U
+#define FLASH_ACR_ICRST 0x00000800U
+#define FLASH_ACR_DCRST 0x00001000U
+#define FLASH_ACR_BYTE0_ADDRESS 0x40023C00U
+#define FLASH_ACR_BYTE2_ADDRESS 0x40023C03U
+
+/******************* Bits definition for FLASH_SR register ******************/
+#define FLASH_SR_EOP 0x00000001U
+#define FLASH_SR_SOP 0x00000002U
+#define FLASH_SR_WRPERR 0x00000010U
+#define FLASH_SR_PGAERR 0x00000020U
+#define FLASH_SR_PGPERR 0x00000040U
+#define FLASH_SR_PGSERR 0x00000080U
+#define FLASH_SR_BSY 0x00010000U
+
+/******************* Bits definition for FLASH_CR register ******************/
+#define FLASH_CR_PG 0x00000001U
+#define FLASH_CR_SER 0x00000002U
+#define FLASH_CR_MER 0x00000004U
+#define FLASH_CR_MER1 FLASH_CR_MER
+#define FLASH_CR_SNB 0x000000F8U
+#define FLASH_CR_SNB_0 0x00000008U
+#define FLASH_CR_SNB_1 0x00000010U
+#define FLASH_CR_SNB_2 0x00000020U
+#define FLASH_CR_SNB_3 0x00000040U
+#define FLASH_CR_SNB_4 0x00000080U
+#define FLASH_CR_PSIZE 0x00000300U
+#define FLASH_CR_PSIZE_0 0x00000100U
+#define FLASH_CR_PSIZE_1 0x00000200U
+#define FLASH_CR_MER2 0x00008000U
+#define FLASH_CR_STRT 0x00010000U
+#define FLASH_CR_EOPIE 0x01000000U
+#define FLASH_CR_LOCK 0x80000000U
+
+/******************* Bits definition for FLASH_OPTCR register ***************/
+#define FLASH_OPTCR_OPTLOCK 0x00000001U
+#define FLASH_OPTCR_OPTSTRT 0x00000002U
+#define FLASH_OPTCR_BOR_LEV_0 0x00000004U
+#define FLASH_OPTCR_BOR_LEV_1 0x00000008U
+#define FLASH_OPTCR_BOR_LEV 0x0000000CU
+#define FLASH_OPTCR_BFB2 0x00000010U
+#define FLASH_OPTCR_WDG_SW 0x00000020U
+#define FLASH_OPTCR_nRST_STOP 0x00000040U
+#define FLASH_OPTCR_nRST_STDBY 0x00000080U
+#define FLASH_OPTCR_RDP 0x0000FF00U
+#define FLASH_OPTCR_RDP_0 0x00000100U
+#define FLASH_OPTCR_RDP_1 0x00000200U
+#define FLASH_OPTCR_RDP_2 0x00000400U
+#define FLASH_OPTCR_RDP_3 0x00000800U
+#define FLASH_OPTCR_RDP_4 0x00001000U
+#define FLASH_OPTCR_RDP_5 0x00002000U
+#define FLASH_OPTCR_RDP_6 0x00004000U
+#define FLASH_OPTCR_RDP_7 0x00008000U
+#define FLASH_OPTCR_nWRP 0x0FFF0000U
+#define FLASH_OPTCR_nWRP_0 0x00010000U
+#define FLASH_OPTCR_nWRP_1 0x00020000U
+#define FLASH_OPTCR_nWRP_2 0x00040000U
+#define FLASH_OPTCR_nWRP_3 0x00080000U
+#define FLASH_OPTCR_nWRP_4 0x00100000U
+#define FLASH_OPTCR_nWRP_5 0x00200000U
+#define FLASH_OPTCR_nWRP_6 0x00400000U
+#define FLASH_OPTCR_nWRP_7 0x00800000U
+#define FLASH_OPTCR_nWRP_8 0x01000000U
+#define FLASH_OPTCR_nWRP_9 0x02000000U
+#define FLASH_OPTCR_nWRP_10 0x04000000U
+#define FLASH_OPTCR_nWRP_11 0x08000000U
+#define FLASH_OPTCR_DB1M 0x40000000U
+#define FLASH_OPTCR_SPRMOD 0x80000000U
+
+/****************** Bits definition for FLASH_OPTCR1 register ***************/
+#define FLASH_OPTCR1_nWRP 0x0FFF0000U
+#define FLASH_OPTCR1_nWRP_0 0x00010000U
+#define FLASH_OPTCR1_nWRP_1 0x00020000U
+#define FLASH_OPTCR1_nWRP_2 0x00040000U
+#define FLASH_OPTCR1_nWRP_3 0x00080000U
+#define FLASH_OPTCR1_nWRP_4 0x00100000U
+#define FLASH_OPTCR1_nWRP_5 0x00200000U
+#define FLASH_OPTCR1_nWRP_6 0x00400000U
+#define FLASH_OPTCR1_nWRP_7 0x00800000U
+#define FLASH_OPTCR1_nWRP_8 0x01000000U
+#define FLASH_OPTCR1_nWRP_9 0x02000000U
+#define FLASH_OPTCR1_nWRP_10 0x04000000U
+#define FLASH_OPTCR1_nWRP_11 0x08000000U
+
+/******************************************************************************/
+/* */
+/* Flexible Memory Controller */
+/* */
+/******************************************************************************/
+/****************** Bit definition for FMC_BCR1 register *******************/
+#define FMC_BCR1_MBKEN 0x00000001U /*!<Memory bank enable bit */
+#define FMC_BCR1_MUXEN 0x00000002U /*!<Address/data multiplexing enable bit */
+
+#define FMC_BCR1_MTYP 0x0000000CU /*!<MTYP[1:0] bits (Memory type) */
+#define FMC_BCR1_MTYP_0 0x00000004U /*!<Bit 0 */
+#define FMC_BCR1_MTYP_1 0x00000008U /*!<Bit 1 */
+
+#define FMC_BCR1_MWID 0x00000030U /*!<MWID[1:0] bits (Memory data bus width) */
+#define FMC_BCR1_MWID_0 0x00000010U /*!<Bit 0 */
+#define FMC_BCR1_MWID_1 0x00000020U /*!<Bit 1 */
+
+#define FMC_BCR1_FACCEN 0x00000040U /*!<Flash access enable */
+#define FMC_BCR1_BURSTEN 0x00000100U /*!<Burst enable bit */
+#define FMC_BCR1_WAITPOL 0x00000200U /*!<Wait signal polarity bit */
+#define FMC_BCR1_WAITCFG 0x00000800U /*!<Wait timing configuration */
+#define FMC_BCR1_WREN 0x00001000U /*!<Write enable bit */
+#define FMC_BCR1_WAITEN 0x00002000U /*!<Wait enable bit */
+#define FMC_BCR1_EXTMOD 0x00004000U /*!<Extended mode enable */
+#define FMC_BCR1_ASYNCWAIT 0x00008000U /*!<Asynchronous wait */
+#define FMC_BCR1_CPSIZE 0x00070000U /*!<CRAM page size */
+#define FMC_BCR1_CPSIZE_0 0x00010000U /*!<Bit 0 */
+#define FMC_BCR1_CPSIZE_1 0x00020000U /*!<Bit 1 */
+#define FMC_BCR1_CPSIZE_2 0x00040000U /*!<Bit 2 */
+#define FMC_BCR1_CBURSTRW 0x00080000U /*!<Write burst enable */
+#define FMC_BCR1_CCLKEN 0x00100000U /*!<Continous clock enable */
+#define FMC_BCR1_WFDIS 0x00200000U /*!<Write FIFO Disable */
+
+/****************** Bit definition for FMC_BCR2 register *******************/
+#define FMC_BCR2_MBKEN 0x00000001U /*!<Memory bank enable bit */
+#define FMC_BCR2_MUXEN 0x00000002U /*!<Address/data multiplexing enable bit */
+
+#define FMC_BCR2_MTYP 0x0000000CU /*!<MTYP[1:0] bits (Memory type) */
+#define FMC_BCR2_MTYP_0 0x00000004U /*!<Bit 0 */
+#define FMC_BCR2_MTYP_1 0x00000008U /*!<Bit 1 */
+
+#define FMC_BCR2_MWID 0x00000030U /*!<MWID[1:0] bits (Memory data bus width) */
+#define FMC_BCR2_MWID_0 0x00000010U /*!<Bit 0 */
+#define FMC_BCR2_MWID_1 0x00000020U /*!<Bit 1 */
+
+#define FMC_BCR2_FACCEN 0x00000040U /*!<Flash access enable */
+#define FMC_BCR2_BURSTEN 0x00000100U /*!<Burst enable bit */
+#define FMC_BCR2_WAITPOL 0x00000200U /*!<Wait signal polarity bit */
+#define FMC_BCR2_WAITCFG 0x00000800U /*!<Wait timing configuration */
+#define FMC_BCR2_WREN 0x00001000U /*!<Write enable bit */
+#define FMC_BCR2_WAITEN 0x00002000U /*!<Wait enable bit */
+#define FMC_BCR2_EXTMOD 0x00004000U /*!<Extended mode enable */
+#define FMC_BCR2_ASYNCWAIT 0x00008000U /*!<Asynchronous wait */
+#define FMC_BCR2_CBURSTRW 0x00080000U /*!<Write burst enable */
+
+/****************** Bit definition for FMC_BCR3 register *******************/
+#define FMC_BCR3_MBKEN 0x00000001U /*!<Memory bank enable bit */
+#define FMC_BCR3_MUXEN 0x00000002U /*!<Address/data multiplexing enable bit */
+
+#define FMC_BCR3_MTYP 0x0000000CU /*!<MTYP[1:0] bits (Memory type) */
+#define FMC_BCR3_MTYP_0 0x00000004U /*!<Bit 0 */
+#define FMC_BCR3_MTYP_1 0x00000008U /*!<Bit 1 */
+
+#define FMC_BCR3_MWID 0x00000030U /*!<MWID[1:0] bits (Memory data bus width) */
+#define FMC_BCR3_MWID_0 0x00000010U /*!<Bit 0 */
+#define FMC_BCR3_MWID_1 0x00000020U /*!<Bit 1 */
+
+#define FMC_BCR3_FACCEN 0x00000040U /*!<Flash access enable */
+#define FMC_BCR3_BURSTEN 0x00000100U /*!<Burst enable bit */
+#define FMC_BCR3_WAITPOL 0x00000200U /*!<Wait signal polarity bit */
+#define FMC_BCR3_WAITCFG 0x00000800U /*!<Wait timing configuration */
+#define FMC_BCR3_WREN 0x00001000U /*!<Write enable bit */
+#define FMC_BCR3_WAITEN 0x00002000U /*!<Wait enable bit */
+#define FMC_BCR3_EXTMOD 0x00004000U /*!<Extended mode enable */
+#define FMC_BCR3_ASYNCWAIT 0x00008000U /*!<Asynchronous wait */
+#define FMC_BCR3_CBURSTRW 0x00080000U /*!<Write burst enable */
+
+/****************** Bit definition for FMC_BCR4 register *******************/
+#define FMC_BCR4_MBKEN 0x00000001U /*!<Memory bank enable bit */
+#define FMC_BCR4_MUXEN 0x00000002U /*!<Address/data multiplexing enable bit */
+
+#define FMC_BCR4_MTYP 0x0000000CU /*!<MTYP[1:0] bits (Memory type) */
+#define FMC_BCR4_MTYP_0 0x00000004U /*!<Bit 0 */
+#define FMC_BCR4_MTYP_1 0x00000008U /*!<Bit 1 */
+
+#define FMC_BCR4_MWID 0x00000030U /*!<MWID[1:0] bits (Memory data bus width) */
+#define FMC_BCR4_MWID_0 0x00000010U /*!<Bit 0 */
+#define FMC_BCR4_MWID_1 0x00000020U /*!<Bit 1 */
+
+#define FMC_BCR4_FACCEN 0x00000040U /*!<Flash access enable */
+#define FMC_BCR4_BURSTEN 0x00000100U /*!<Burst enable bit */
+#define FMC_BCR4_WAITPOL 0x00000200U /*!<Wait signal polarity bit */
+#define FMC_BCR4_WAITCFG 0x00000800U /*!<Wait timing configuration */
+#define FMC_BCR4_WREN 0x00001000U /*!<Write enable bit */
+#define FMC_BCR4_WAITEN 0x00002000U /*!<Wait enable bit */
+#define FMC_BCR4_EXTMOD 0x00004000U /*!<Extended mode enable */
+#define FMC_BCR4_ASYNCWAIT 0x00008000U /*!<Asynchronous wait */
+#define FMC_BCR4_CBURSTRW 0x00080000U /*!<Write burst enable */
+
+/****************** Bit definition for FMC_BTR1 register ******************/
+#define FMC_BTR1_ADDSET 0x0000000FU /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FMC_BTR1_ADDSET_0 0x00000001U /*!<Bit 0 */
+#define FMC_BTR1_ADDSET_1 0x00000002U /*!<Bit 1 */
+#define FMC_BTR1_ADDSET_2 0x00000004U /*!<Bit 2 */
+#define FMC_BTR1_ADDSET_3 0x00000008U /*!<Bit 3 */
+
+#define FMC_BTR1_ADDHLD 0x000000F0U /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FMC_BTR1_ADDHLD_0 0x00000010U /*!<Bit 0 */
+#define FMC_BTR1_ADDHLD_1 0x00000020U /*!<Bit 1 */
+#define FMC_BTR1_ADDHLD_2 0x00000040U /*!<Bit 2 */
+#define FMC_BTR1_ADDHLD_3 0x00000080U /*!<Bit 3 */
+
+#define FMC_BTR1_DATAST 0x0000FF00U /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FMC_BTR1_DATAST_0 0x00000100U /*!<Bit 0 */
+#define FMC_BTR1_DATAST_1 0x00000200U /*!<Bit 1 */
+#define FMC_BTR1_DATAST_2 0x00000400U /*!<Bit 2 */
+#define FMC_BTR1_DATAST_3 0x00000800U /*!<Bit 3 */
+#define FMC_BTR1_DATAST_4 0x00001000U /*!<Bit 4 */
+#define FMC_BTR1_DATAST_5 0x00002000U /*!<Bit 5 */
+#define FMC_BTR1_DATAST_6 0x00004000U /*!<Bit 6 */
+#define FMC_BTR1_DATAST_7 0x00008000U /*!<Bit 7 */
+
+#define FMC_BTR1_BUSTURN 0x000F0000U /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define FMC_BTR1_BUSTURN_0 0x00010000U /*!<Bit 0 */
+#define FMC_BTR1_BUSTURN_1 0x00020000U /*!<Bit 1 */
+#define FMC_BTR1_BUSTURN_2 0x00040000U /*!<Bit 2 */
+#define FMC_BTR1_BUSTURN_3 0x00080000U /*!<Bit 3 */
+
+#define FMC_BTR1_CLKDIV 0x00F00000U /*!<CLKDIV[3:0] bits (Clock divide ratio) */
+#define FMC_BTR1_CLKDIV_0 0x00100000U /*!<Bit 0 */
+#define FMC_BTR1_CLKDIV_1 0x00200000U /*!<Bit 1 */
+#define FMC_BTR1_CLKDIV_2 0x00400000U /*!<Bit 2 */
+#define FMC_BTR1_CLKDIV_3 0x00800000U /*!<Bit 3 */
+
+#define FMC_BTR1_DATLAT 0x0F000000U /*!<DATLA[3:0] bits (Data latency) */
+#define FMC_BTR1_DATLAT_0 0x01000000U /*!<Bit 0 */
+#define FMC_BTR1_DATLAT_1 0x02000000U /*!<Bit 1 */
+#define FMC_BTR1_DATLAT_2 0x04000000U /*!<Bit 2 */
+#define FMC_BTR1_DATLAT_3 0x08000000U /*!<Bit 3 */
+
+#define FMC_BTR1_ACCMOD 0x30000000U /*!<ACCMOD[1:0] bits (Access mode) */
+#define FMC_BTR1_ACCMOD_0 0x10000000U /*!<Bit 0 */
+#define FMC_BTR1_ACCMOD_1 0x20000000U /*!<Bit 1 */
+
+/****************** Bit definition for FMC_BTR2 register *******************/
+#define FMC_BTR2_ADDSET 0x0000000FU /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FMC_BTR2_ADDSET_0 0x00000001U /*!<Bit 0 */
+#define FMC_BTR2_ADDSET_1 0x00000002U /*!<Bit 1 */
+#define FMC_BTR2_ADDSET_2 0x00000004U /*!<Bit 2 */
+#define FMC_BTR2_ADDSET_3 0x00000008U /*!<Bit 3 */
+
+#define FMC_BTR2_ADDHLD 0x000000F0U /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FMC_BTR2_ADDHLD_0 0x00000010U /*!<Bit 0 */
+#define FMC_BTR2_ADDHLD_1 0x00000020U /*!<Bit 1 */
+#define FMC_BTR2_ADDHLD_2 0x00000040U /*!<Bit 2 */
+#define FMC_BTR2_ADDHLD_3 0x00000080U /*!<Bit 3 */
+
+#define FMC_BTR2_DATAST 0x0000FF00U /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FMC_BTR2_DATAST_0 0x00000100U /*!<Bit 0 */
+#define FMC_BTR2_DATAST_1 0x00000200U /*!<Bit 1 */
+#define FMC_BTR2_DATAST_2 0x00000400U /*!<Bit 2 */
+#define FMC_BTR2_DATAST_3 0x00000800U /*!<Bit 3 */
+#define FMC_BTR2_DATAST_4 0x00001000U /*!<Bit 4 */
+#define FMC_BTR2_DATAST_5 0x00002000U /*!<Bit 5 */
+#define FMC_BTR2_DATAST_6 0x00004000U /*!<Bit 6 */
+#define FMC_BTR2_DATAST_7 0x00008000U /*!<Bit 7 */
+
+#define FMC_BTR2_BUSTURN 0x000F0000U /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define FMC_BTR2_BUSTURN_0 0x00010000U /*!<Bit 0 */
+#define FMC_BTR2_BUSTURN_1 0x00020000U /*!<Bit 1 */
+#define FMC_BTR2_BUSTURN_2 0x00040000U /*!<Bit 2 */
+#define FMC_BTR2_BUSTURN_3 0x00080000U /*!<Bit 3 */
+
+#define FMC_BTR2_CLKDIV 0x00F00000U /*!<CLKDIV[3:0] bits (Clock divide ratio) */
+#define FMC_BTR2_CLKDIV_0 0x00100000U /*!<Bit 0 */
+#define FMC_BTR2_CLKDIV_1 0x00200000U /*!<Bit 1 */
+#define FMC_BTR2_CLKDIV_2 0x00400000U /*!<Bit 2 */
+#define FMC_BTR2_CLKDIV_3 0x00800000U /*!<Bit 3 */
+
+#define FMC_BTR2_DATLAT 0x0F000000U /*!<DATLA[3:0] bits (Data latency) */
+#define FMC_BTR2_DATLAT_0 0x01000000U /*!<Bit 0 */
+#define FMC_BTR2_DATLAT_1 0x02000000U /*!<Bit 1 */
+#define FMC_BTR2_DATLAT_2 0x04000000U /*!<Bit 2 */
+#define FMC_BTR2_DATLAT_3 0x08000000U /*!<Bit 3 */
+
+#define FMC_BTR2_ACCMOD 0x30000000U /*!<ACCMOD[1:0] bits (Access mode) */
+#define FMC_BTR2_ACCMOD_0 0x10000000U /*!<Bit 0 */
+#define FMC_BTR2_ACCMOD_1 0x20000000U /*!<Bit 1 */
+
+/******************* Bit definition for FMC_BTR3 register *******************/
+#define FMC_BTR3_ADDSET 0x0000000FU /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FMC_BTR3_ADDSET_0 0x00000001U /*!<Bit 0 */
+#define FMC_BTR3_ADDSET_1 0x00000002U /*!<Bit 1 */
+#define FMC_BTR3_ADDSET_2 0x00000004U /*!<Bit 2 */
+#define FMC_BTR3_ADDSET_3 0x00000008U /*!<Bit 3 */
+
+#define FMC_BTR3_ADDHLD 0x000000F0U /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FMC_BTR3_ADDHLD_0 0x00000010U /*!<Bit 0 */
+#define FMC_BTR3_ADDHLD_1 0x00000020U /*!<Bit 1 */
+#define FMC_BTR3_ADDHLD_2 0x00000040U /*!<Bit 2 */
+#define FMC_BTR3_ADDHLD_3 0x00000080U /*!<Bit 3 */
+
+#define FMC_BTR3_DATAST 0x0000FF00U /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FMC_BTR3_DATAST_0 0x00000100U /*!<Bit 0 */
+#define FMC_BTR3_DATAST_1 0x00000200U /*!<Bit 1 */
+#define FMC_BTR3_DATAST_2 0x00000400U /*!<Bit 2 */
+#define FMC_BTR3_DATAST_3 0x00000800U /*!<Bit 3 */
+#define FMC_BTR3_DATAST_4 0x00001000U /*!<Bit 4 */
+#define FMC_BTR3_DATAST_5 0x00002000U /*!<Bit 5 */
+#define FMC_BTR3_DATAST_6 0x00004000U /*!<Bit 6 */
+#define FMC_BTR3_DATAST_7 0x00008000U /*!<Bit 7 */
+
+#define FMC_BTR3_BUSTURN 0x000F0000U /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define FMC_BTR3_BUSTURN_0 0x00010000U /*!<Bit 0 */
+#define FMC_BTR3_BUSTURN_1 0x00020000U /*!<Bit 1 */
+#define FMC_BTR3_BUSTURN_2 0x00040000U /*!<Bit 2 */
+#define FMC_BTR3_BUSTURN_3 0x00080000U /*!<Bit 3 */
+
+#define FMC_BTR3_CLKDIV 0x00F00000U /*!<CLKDIV[3:0] bits (Clock divide ratio) */
+#define FMC_BTR3_CLKDIV_0 0x00100000U /*!<Bit 0 */
+#define FMC_BTR3_CLKDIV_1 0x00200000U /*!<Bit 1 */
+#define FMC_BTR3_CLKDIV_2 0x00400000U /*!<Bit 2 */
+#define FMC_BTR3_CLKDIV_3 0x00800000U /*!<Bit 3 */
+
+#define FMC_BTR3_DATLAT 0x0F000000U /*!<DATLA[3:0] bits (Data latency) */
+#define FMC_BTR3_DATLAT_0 0x01000000U /*!<Bit 0 */
+#define FMC_BTR3_DATLAT_1 0x02000000U /*!<Bit 1 */
+#define FMC_BTR3_DATLAT_2 0x04000000U /*!<Bit 2 */
+#define FMC_BTR3_DATLAT_3 0x08000000U /*!<Bit 3 */
+
+#define FMC_BTR3_ACCMOD 0x30000000U /*!<ACCMOD[1:0] bits (Access mode) */
+#define FMC_BTR3_ACCMOD_0 0x10000000U /*!<Bit 0 */
+#define FMC_BTR3_ACCMOD_1 0x20000000U /*!<Bit 1 */
+
+/****************** Bit definition for FMC_BTR4 register *******************/
+#define FMC_BTR4_ADDSET 0x0000000FU /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FMC_BTR4_ADDSET_0 0x00000001U /*!<Bit 0 */
+#define FMC_BTR4_ADDSET_1 0x00000002U /*!<Bit 1 */
+#define FMC_BTR4_ADDSET_2 0x00000004U /*!<Bit 2 */
+#define FMC_BTR4_ADDSET_3 0x00000008U /*!<Bit 3 */
+
+#define FMC_BTR4_ADDHLD 0x000000F0U /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FMC_BTR4_ADDHLD_0 0x00000010U /*!<Bit 0 */
+#define FMC_BTR4_ADDHLD_1 0x00000020U /*!<Bit 1 */
+#define FMC_BTR4_ADDHLD_2 0x00000040U /*!<Bit 2 */
+#define FMC_BTR4_ADDHLD_3 0x00000080U /*!<Bit 3 */
+
+#define FMC_BTR4_DATAST 0x0000FF00U /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FMC_BTR4_DATAST_0 0x00000100U /*!<Bit 0 */
+#define FMC_BTR4_DATAST_1 0x00000200U /*!<Bit 1 */
+#define FMC_BTR4_DATAST_2 0x00000400U /*!<Bit 2 */
+#define FMC_BTR4_DATAST_3 0x00000800U /*!<Bit 3 */
+#define FMC_BTR4_DATAST_4 0x00001000U /*!<Bit 4 */
+#define FMC_BTR4_DATAST_5 0x00002000U /*!<Bit 5 */
+#define FMC_BTR4_DATAST_6 0x00004000U /*!<Bit 6 */
+#define FMC_BTR4_DATAST_7 0x00008000U /*!<Bit 7 */
+
+#define FMC_BTR4_BUSTURN 0x000F0000U /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define FMC_BTR4_BUSTURN_0 0x00010000U /*!<Bit 0 */
+#define FMC_BTR4_BUSTURN_1 0x00020000U /*!<Bit 1 */
+#define FMC_BTR4_BUSTURN_2 0x00040000U /*!<Bit 2 */
+#define FMC_BTR4_BUSTURN_3 0x00080000U /*!<Bit 3 */
+
+#define FMC_BTR4_CLKDIV 0x00F00000U /*!<CLKDIV[3:0] bits (Clock divide ratio) */
+#define FMC_BTR4_CLKDIV_0 0x00100000U /*!<Bit 0 */
+#define FMC_BTR4_CLKDIV_1 0x00200000U /*!<Bit 1 */
+#define FMC_BTR4_CLKDIV_2 0x00400000U /*!<Bit 2 */
+#define FMC_BTR4_CLKDIV_3 0x00800000U /*!<Bit 3 */
+
+#define FMC_BTR4_DATLAT 0x0F000000U /*!<DATLA[3:0] bits (Data latency) */
+#define FMC_BTR4_DATLAT_0 0x01000000U /*!<Bit 0 */
+#define FMC_BTR4_DATLAT_1 0x02000000U /*!<Bit 1 */
+#define FMC_BTR4_DATLAT_2 0x04000000U /*!<Bit 2 */
+#define FMC_BTR4_DATLAT_3 0x08000000U /*!<Bit 3 */
+
+#define FMC_BTR4_ACCMOD 0x30000000U /*!<ACCMOD[1:0] bits (Access mode) */
+#define FMC_BTR4_ACCMOD_0 0x10000000U /*!<Bit 0 */
+#define FMC_BTR4_ACCMOD_1 0x20000000U /*!<Bit 1 */
+
+/****************** Bit definition for FMC_BWTR1 register ******************/
+#define FMC_BWTR1_ADDSET 0x0000000FU /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FMC_BWTR1_ADDSET_0 0x00000001U /*!<Bit 0 */
+#define FMC_BWTR1_ADDSET_1 0x00000002U /*!<Bit 1 */
+#define FMC_BWTR1_ADDSET_2 0x00000004U /*!<Bit 2 */
+#define FMC_BWTR1_ADDSET_3 0x00000008U /*!<Bit 3 */
+
+#define FMC_BWTR1_ADDHLD 0x000000F0U /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FMC_BWTR1_ADDHLD_0 0x00000010U /*!<Bit 0 */
+#define FMC_BWTR1_ADDHLD_1 0x00000020U /*!<Bit 1 */
+#define FMC_BWTR1_ADDHLD_2 0x00000040U /*!<Bit 2 */
+#define FMC_BWTR1_ADDHLD_3 0x00000080U /*!<Bit 3 */
+
+#define FMC_BWTR1_DATAST 0x0000FF00U /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FMC_BWTR1_DATAST_0 0x00000100U /*!<Bit 0 */
+#define FMC_BWTR1_DATAST_1 0x00000200U /*!<Bit 1 */
+#define FMC_BWTR1_DATAST_2 0x00000400U /*!<Bit 2 */
+#define FMC_BWTR1_DATAST_3 0x00000800U /*!<Bit 3 */
+#define FMC_BWTR1_DATAST_4 0x00001000U /*!<Bit 4 */
+#define FMC_BWTR1_DATAST_5 0x00002000U /*!<Bit 5 */
+#define FMC_BWTR1_DATAST_6 0x00004000U /*!<Bit 6 */
+#define FMC_BWTR1_DATAST_7 0x00008000U /*!<Bit 7 */
+
+#define FMC_BWTR1_BUSTURN 0x000F0000U /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
+#define FMC_BWTR1_BUSTURN_0 0x00010000U /*!<Bit 0 */
+#define FMC_BWTR1_BUSTURN_1 0x00020000U /*!<Bit 1 */
+#define FMC_BWTR1_BUSTURN_2 0x00040000U /*!<Bit 2 */
+#define FMC_BWTR1_BUSTURN_3 0x00080000U /*!<Bit 3 */
+
+#define FMC_BWTR1_ACCMOD 0x30000000U /*!<ACCMOD[1:0] bits (Access mode) */
+#define FMC_BWTR1_ACCMOD_0 0x10000000U /*!<Bit 0 */
+#define FMC_BWTR1_ACCMOD_1 0x20000000U /*!<Bit 1 */
+
+/****************** Bit definition for FMC_BWTR2 register ******************/
+#define FMC_BWTR2_ADDSET 0x0000000FU /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FMC_BWTR2_ADDSET_0 0x00000001U /*!<Bit 0 */
+#define FMC_BWTR2_ADDSET_1 0x00000002U /*!<Bit 1 */
+#define FMC_BWTR2_ADDSET_2 0x00000004U /*!<Bit 2 */
+#define FMC_BWTR2_ADDSET_3 0x00000008U /*!<Bit 3 */
+
+#define FMC_BWTR2_ADDHLD 0x000000F0U /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FMC_BWTR2_ADDHLD_0 0x00000010U /*!<Bit 0 */
+#define FMC_BWTR2_ADDHLD_1 0x00000020U /*!<Bit 1 */
+#define FMC_BWTR2_ADDHLD_2 0x00000040U /*!<Bit 2 */
+#define FMC_BWTR2_ADDHLD_3 0x00000080U /*!<Bit 3 */
+
+#define FMC_BWTR2_DATAST 0x0000FF00U /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FMC_BWTR2_DATAST_0 0x00000100U /*!<Bit 0 */
+#define FMC_BWTR2_DATAST_1 0x00000200U /*!<Bit 1 */
+#define FMC_BWTR2_DATAST_2 0x00000400U /*!<Bit 2 */
+#define FMC_BWTR2_DATAST_3 0x00000800U /*!<Bit 3 */
+#define FMC_BWTR2_DATAST_4 0x00001000U /*!<Bit 4 */
+#define FMC_BWTR2_DATAST_5 0x00002000U /*!<Bit 5 */
+#define FMC_BWTR2_DATAST_6 0x00004000U /*!<Bit 6 */
+#define FMC_BWTR2_DATAST_7 0x00008000U /*!<Bit 7 */
+
+#define FMC_BWTR2_BUSTURN 0x000F0000U /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
+#define FMC_BWTR2_BUSTURN_0 0x00010000U /*!<Bit 0 */
+#define FMC_BWTR2_BUSTURN_1 0x00020000U /*!<Bit 1 */
+#define FMC_BWTR2_BUSTURN_2 0x00040000U /*!<Bit 2 */
+#define FMC_BWTR2_BUSTURN_3 0x00080000U /*!<Bit 3 */
+
+#define FMC_BWTR2_ACCMOD 0x30000000U /*!<ACCMOD[1:0] bits (Access mode) */
+#define FMC_BWTR2_ACCMOD_0 0x10000000U /*!<Bit 0 */
+#define FMC_BWTR2_ACCMOD_1 0x20000000U /*!<Bit 1 */
+
+/****************** Bit definition for FMC_BWTR3 register ******************/
+#define FMC_BWTR3_ADDSET 0x0000000FU /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FMC_BWTR3_ADDSET_0 0x00000001U /*!<Bit 0 */
+#define FMC_BWTR3_ADDSET_1 0x00000002U /*!<Bit 1 */
+#define FMC_BWTR3_ADDSET_2 0x00000004U /*!<Bit 2 */
+#define FMC_BWTR3_ADDSET_3 0x00000008U /*!<Bit 3 */
+
+#define FMC_BWTR3_ADDHLD 0x000000F0U /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FMC_BWTR3_ADDHLD_0 0x00000010U /*!<Bit 0 */
+#define FMC_BWTR3_ADDHLD_1 0x00000020U /*!<Bit 1 */
+#define FMC_BWTR3_ADDHLD_2 0x00000040U /*!<Bit 2 */
+#define FMC_BWTR3_ADDHLD_3 0x00000080U /*!<Bit 3 */
+
+#define FMC_BWTR3_DATAST 0x0000FF00U /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FMC_BWTR3_DATAST_0 0x00000100U /*!<Bit 0 */
+#define FMC_BWTR3_DATAST_1 0x00000200U /*!<Bit 1 */
+#define FMC_BWTR3_DATAST_2 0x00000400U /*!<Bit 2 */
+#define FMC_BWTR3_DATAST_3 0x00000800U /*!<Bit 3 */
+#define FMC_BWTR3_DATAST_4 0x00001000U /*!<Bit 4 */
+#define FMC_BWTR3_DATAST_5 0x00002000U /*!<Bit 5 */
+#define FMC_BWTR3_DATAST_6 0x00004000U /*!<Bit 6 */
+#define FMC_BWTR3_DATAST_7 0x00008000U /*!<Bit 7 */
+
+#define FMC_BWTR3_BUSTURN 0x000F0000U /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
+#define FMC_BWTR3_BUSTURN_0 0x00010000U /*!<Bit 0 */
+#define FMC_BWTR3_BUSTURN_1 0x00020000U /*!<Bit 1 */
+#define FMC_BWTR3_BUSTURN_2 0x00040000U /*!<Bit 2 */
+#define FMC_BWTR3_BUSTURN_3 0x00080000U /*!<Bit 3 */
+
+#define FMC_BWTR3_ACCMOD 0x30000000U /*!<ACCMOD[1:0] bits (Access mode) */
+#define FMC_BWTR3_ACCMOD_0 0x10000000U /*!<Bit 0 */
+#define FMC_BWTR3_ACCMOD_1 0x20000000U /*!<Bit 1 */
+
+/****************** Bit definition for FMC_BWTR4 register ******************/
+#define FMC_BWTR4_ADDSET 0x0000000FU /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FMC_BWTR4_ADDSET_0 0x00000001U /*!<Bit 0 */
+#define FMC_BWTR4_ADDSET_1 0x00000002U /*!<Bit 1 */
+#define FMC_BWTR4_ADDSET_2 0x00000004U /*!<Bit 2 */
+#define FMC_BWTR4_ADDSET_3 0x00000008U /*!<Bit 3 */
+
+#define FMC_BWTR4_ADDHLD 0x000000F0U /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FMC_BWTR4_ADDHLD_0 0x00000010U /*!<Bit 0 */
+#define FMC_BWTR4_ADDHLD_1 0x00000020U /*!<Bit 1 */
+#define FMC_BWTR4_ADDHLD_2 0x00000040U /*!<Bit 2 */
+#define FMC_BWTR4_ADDHLD_3 0x00000080U /*!<Bit 3 */
+
+#define FMC_BWTR4_DATAST 0x0000FF00U /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FMC_BWTR4_DATAST_0 0x00000100U /*!<Bit 0 */
+#define FMC_BWTR4_DATAST_1 0x00000200U /*!<Bit 1 */
+#define FMC_BWTR4_DATAST_2 0x00000400U /*!<Bit 2 */
+#define FMC_BWTR4_DATAST_3 0x00000800U /*!<Bit 3 */
+#define FMC_BWTR4_DATAST_4 0x00001000U /*!<Bit 4 */
+#define FMC_BWTR4_DATAST_5 0x00002000U /*!<Bit 5 */
+#define FMC_BWTR4_DATAST_6 0x00004000U /*!<Bit 6 */
+#define FMC_BWTR4_DATAST_7 0x00008000U /*!<Bit 7 */
+
+#define FMC_BWTR4_BUSTURN 0x000F0000U /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
+#define FMC_BWTR4_BUSTURN_0 0x00010000U /*!<Bit 0 */
+#define FMC_BWTR4_BUSTURN_1 0x00020000U /*!<Bit 1 */
+#define FMC_BWTR4_BUSTURN_2 0x00040000U /*!<Bit 2 */
+#define FMC_BWTR4_BUSTURN_3 0x00080000U /*!<Bit 3 */
+
+#define FMC_BWTR4_ACCMOD 0x30000000U /*!<ACCMOD[1:0] bits (Access mode) */
+#define FMC_BWTR4_ACCMOD_0 0x10000000U /*!<Bit 0 */
+#define FMC_BWTR4_ACCMOD_1 0x20000000U /*!<Bit 1 */
+
+/****************** Bit definition for FMC_PCR register *******************/
+#define FMC_PCR_PWAITEN 0x00000002U /*!<Wait feature enable bit */
+#define FMC_PCR_PBKEN 0x00000004U /*!<PC Card/NAND Flash memory bank enable bit */
+#define FMC_PCR_PTYP 0x00000008U /*!<Memory type */
+
+#define FMC_PCR_PWID 0x00000030U /*!<PWID[1:0] bits (NAND Flash databus width) */
+#define FMC_PCR_PWID_0 0x00000010U /*!<Bit 0 */
+#define FMC_PCR_PWID_1 0x00000020U /*!<Bit 1 */
+
+#define FMC_PCR_ECCEN 0x00000040U /*!<ECC computation logic enable bit */
+
+#define FMC_PCR_TCLR 0x00001E00U /*!<TCLR[3:0] bits (CLE to RE delay) */
+#define FMC_PCR_TCLR_0 0x00000200U /*!<Bit 0 */
+#define FMC_PCR_TCLR_1 0x00000400U /*!<Bit 1 */
+#define FMC_PCR_TCLR_2 0x00000800U /*!<Bit 2 */
+#define FMC_PCR_TCLR_3 0x00001000U /*!<Bit 3 */
+
+#define FMC_PCR_TAR 0x0001E000U /*!<TAR[3:0] bits (ALE to RE delay) */
+#define FMC_PCR_TAR_0 0x00002000U /*!<Bit 0 */
+#define FMC_PCR_TAR_1 0x00004000U /*!<Bit 1 */
+#define FMC_PCR_TAR_2 0x00008000U /*!<Bit 2 */
+#define FMC_PCR_TAR_3 0x00010000U /*!<Bit 3 */
+
+#define FMC_PCR_ECCPS 0x000E0000U /*!<ECCPS[1:0] bits (ECC page size) */
+#define FMC_PCR_ECCPS_0 0x00020000U /*!<Bit 0 */
+#define FMC_PCR_ECCPS_1 0x00040000U /*!<Bit 1 */
+#define FMC_PCR_ECCPS_2 0x00080000U /*!<Bit 2 */
+
+/******************* Bit definition for FMC_SR register *******************/
+#define FMC_SR_IRS 0x01U /*!<Interrupt Rising Edge status */
+#define FMC_SR_ILS 0x02U /*!<Interrupt Level status */
+#define FMC_SR_IFS 0x04U /*!<Interrupt Falling Edge status */
+#define FMC_SR_IREN 0x08U /*!<Interrupt Rising Edge detection Enable bit */
+#define FMC_SR_ILEN 0x10U /*!<Interrupt Level detection Enable bit */
+#define FMC_SR_IFEN 0x20U /*!<Interrupt Falling Edge detection Enable bit */
+#define FMC_SR_FEMPT 0x40U /*!<FIFO empty */
+
+/****************** Bit definition for FMC_PMEM register ******************/
+#define FMC_PMEM_MEMSET2 0x000000FFU /*!<MEMSET2[7:0] bits (Common memory 2 setup time) */
+#define FMC_PMEM_MEMSET2_0 0x00000001U /*!<Bit 0 */
+#define FMC_PMEM_MEMSET2_1 0x00000002U /*!<Bit 1 */
+#define FMC_PMEM_MEMSET2_2 0x00000004U /*!<Bit 2 */
+#define FMC_PMEM_MEMSET2_3 0x00000008U /*!<Bit 3 */
+#define FMC_PMEM_MEMSET2_4 0x00000010U /*!<Bit 4 */
+#define FMC_PMEM_MEMSET2_5 0x00000020U /*!<Bit 5 */
+#define FMC_PMEM_MEMSET2_6 0x00000040U /*!<Bit 6 */
+#define FMC_PMEM_MEMSET2_7 0x00000080U /*!<Bit 7 */
+
+#define FMC_PMEM_MEMWAIT2 0x0000FF00U /*!<MEMWAIT2[7:0] bits (Common memory 2 wait time) */
+#define FMC_PMEM_MEMWAIT2_0 0x00000100U /*!<Bit 0 */
+#define FMC_PMEM_MEMWAIT2_1 0x00000200U /*!<Bit 1 */
+#define FMC_PMEM_MEMWAIT2_2 0x00000400U /*!<Bit 2 */
+#define FMC_PMEM_MEMWAIT2_3 0x00000800U /*!<Bit 3 */
+#define FMC_PMEM_MEMWAIT2_4 0x00001000U /*!<Bit 4 */
+#define FMC_PMEM_MEMWAIT2_5 0x00002000U /*!<Bit 5 */
+#define FMC_PMEM_MEMWAIT2_6 0x00004000U /*!<Bit 6 */
+#define FMC_PMEM_MEMWAIT2_7 0x00008000U /*!<Bit 7 */
+
+#define FMC_PMEM_MEMHOLD2 0x00FF0000U /*!<MEMHOLD2[7:0] bits (Common memory 2 hold time) */
+#define FMC_PMEM_MEMHOLD2_0 0x00010000U /*!<Bit 0 */
+#define FMC_PMEM_MEMHOLD2_1 0x00020000U /*!<Bit 1 */
+#define FMC_PMEM_MEMHOLD2_2 0x00040000U /*!<Bit 2 */
+#define FMC_PMEM_MEMHOLD2_3 0x00080000U /*!<Bit 3 */
+#define FMC_PMEM_MEMHOLD2_4 0x00100000U /*!<Bit 4 */
+#define FMC_PMEM_MEMHOLD2_5 0x00200000U /*!<Bit 5 */
+#define FMC_PMEM_MEMHOLD2_6 0x00400000U /*!<Bit 6 */
+#define FMC_PMEM_MEMHOLD2_7 0x00800000U /*!<Bit 7 */
+
+#define FMC_PMEM_MEMHIZ2 0xFF000000U /*!<MEMHIZ2[7:0] bits (Common memory 2 databus HiZ time) */
+#define FMC_PMEM_MEMHIZ2_0 0x01000000U /*!<Bit 0 */
+#define FMC_PMEM_MEMHIZ2_1 0x02000000U /*!<Bit 1 */
+#define FMC_PMEM_MEMHIZ2_2 0x04000000U /*!<Bit 2 */
+#define FMC_PMEM_MEMHIZ2_3 0x08000000U /*!<Bit 3 */
+#define FMC_PMEM_MEMHIZ2_4 0x10000000U /*!<Bit 4 */
+#define FMC_PMEM_MEMHIZ2_5 0x20000000U /*!<Bit 5 */
+#define FMC_PMEM_MEMHIZ2_6 0x40000000U /*!<Bit 6 */
+#define FMC_PMEM_MEMHIZ2_7 0x80000000U /*!<Bit 7 */
+
+/****************** Bit definition for FMC_PATT register ******************/
+#define FMC_PATT_ATTSET2 0x000000FFU /*!<ATTSET2[7:0] bits (Attribute memory 2 setup time) */
+#define FMC_PATT_ATTSET2_0 0x00000001U /*!<Bit 0 */
+#define FMC_PATT_ATTSET2_1 0x00000002U /*!<Bit 1 */
+#define FMC_PATT_ATTSET2_2 0x00000004U /*!<Bit 2 */
+#define FMC_PATT_ATTSET2_3 0x00000008U /*!<Bit 3 */
+#define FMC_PATT_ATTSET2_4 0x00000010U /*!<Bit 4 */
+#define FMC_PATT_ATTSET2_5 0x00000020U /*!<Bit 5 */
+#define FMC_PATT_ATTSET2_6 0x00000040U /*!<Bit 6 */
+#define FMC_PATT_ATTSET2_7 0x00000080U /*!<Bit 7 */
+
+#define FMC_PATT_ATTWAIT2 0x0000FF00U /*!<ATTWAIT2[7:0] bits (Attribute memory 2 wait time) */
+#define FMC_PATT_ATTWAIT2_0 0x00000100U /*!<Bit 0 */
+#define FMC_PATT_ATTWAIT2_1 0x00000200U /*!<Bit 1 */
+#define FMC_PATT_ATTWAIT2_2 0x00000400U /*!<Bit 2 */
+#define FMC_PATT_ATTWAIT2_3 0x00000800U /*!<Bit 3 */
+#define FMC_PATT_ATTWAIT2_4 0x00001000U /*!<Bit 4 */
+#define FMC_PATT_ATTWAIT2_5 0x00002000U /*!<Bit 5 */
+#define FMC_PATT_ATTWAIT2_6 0x00004000U /*!<Bit 6 */
+#define FMC_PATT_ATTWAIT2_7 0x00008000U /*!<Bit 7 */
+
+#define FMC_PATT_ATTHOLD2 0x00FF0000U /*!<ATTHOLD2[7:0] bits (Attribute memory 2 hold time) */
+#define FMC_PATT_ATTHOLD2_0 0x00010000U /*!<Bit 0 */
+#define FMC_PATT_ATTHOLD2_1 0x00020000U /*!<Bit 1 */
+#define FMC_PATT_ATTHOLD2_2 0x00040000U /*!<Bit 2 */
+#define FMC_PATT_ATTHOLD2_3 0x00080000U /*!<Bit 3 */
+#define FMC_PATT_ATTHOLD2_4 0x00100000U /*!<Bit 4 */
+#define FMC_PATT_ATTHOLD2_5 0x00200000U /*!<Bit 5 */
+#define FMC_PATT_ATTHOLD2_6 0x00400000U /*!<Bit 6 */
+#define FMC_PATT_ATTHOLD2_7 0x00800000U /*!<Bit 7 */
+
+#define FMC_PATT_ATTHIZ2 0xFF000000U /*!<ATTHIZ2[7:0] bits (Attribute memory 2 databus HiZ time) */
+#define FMC_PATT_ATTHIZ2_0 0x01000000U /*!<Bit 0 */
+#define FMC_PATT_ATTHIZ2_1 0x02000000U /*!<Bit 1 */
+#define FMC_PATT_ATTHIZ2_2 0x04000000U /*!<Bit 2 */
+#define FMC_PATT_ATTHIZ2_3 0x08000000U /*!<Bit 3 */
+#define FMC_PATT_ATTHIZ2_4 0x10000000U /*!<Bit 4 */
+#define FMC_PATT_ATTHIZ2_5 0x20000000U /*!<Bit 5 */
+#define FMC_PATT_ATTHIZ2_6 0x40000000U /*!<Bit 6 */
+#define FMC_PATT_ATTHIZ2_7 0x80000000U /*!<Bit 7 */
+
+/****************** Bit definition for FMC_ECCR register ******************/
+#define FMC_ECCR_ECC2 0xFFFFFFFFU /*!<ECC result */
+
+/****************** Bit definition for FMC_SDCR1 register ******************/
+#define FMC_SDCR1_NC 0x00000003U /*!<NC[1:0] bits (Number of column bits) */
+#define FMC_SDCR1_NC_0 0x00000001U /*!<Bit 0 */
+#define FMC_SDCR1_NC_1 0x00000002U /*!<Bit 1 */
+
+#define FMC_SDCR1_NR 0x0000000CU /*!<NR[1:0] bits (Number of row bits) */
+#define FMC_SDCR1_NR_0 0x00000004U /*!<Bit 0 */
+#define FMC_SDCR1_NR_1 0x00000008U /*!<Bit 1 */
+
+#define FMC_SDCR1_MWID 0x00000030U /*!<NR[1:0] bits (Number of row bits) */
+#define FMC_SDCR1_MWID_0 0x00000010U /*!<Bit 0 */
+#define FMC_SDCR1_MWID_1 0x00000020U /*!<Bit 1 */
+
+#define FMC_SDCR1_NB 0x00000040U /*!<Number of internal bank */
+
+#define FMC_SDCR1_CAS 0x00000180U /*!<CAS[1:0] bits (CAS latency) */
+#define FMC_SDCR1_CAS_0 0x00000080U /*!<Bit 0 */
+#define FMC_SDCR1_CAS_1 0x00000100U /*!<Bit 1 */
+
+#define FMC_SDCR1_WP 0x00000200U /*!<Write protection */
+
+#define FMC_SDCR1_SDCLK 0x00000C00U /*!<SDRAM clock configuration */
+#define FMC_SDCR1_SDCLK_0 0x00000400U /*!<Bit 0 */
+#define FMC_SDCR1_SDCLK_1 0x00000800U /*!<Bit 1 */
+
+#define FMC_SDCR1_RBURST 0x00001000U /*!<Read burst */
+
+#define FMC_SDCR1_RPIPE 0x00006000U /*!<Write protection */
+#define FMC_SDCR1_RPIPE_0 0x00002000U /*!<Bit 0 */
+#define FMC_SDCR1_RPIPE_1 0x00004000U /*!<Bit 1 */
+
+/****************** Bit definition for FMC_SDCR2 register ******************/
+#define FMC_SDCR2_NC 0x00000003U /*!<NC[1:0] bits (Number of column bits) */
+#define FMC_SDCR2_NC_0 0x00000001U /*!<Bit 0 */
+#define FMC_SDCR2_NC_1 0x00000002U /*!<Bit 1 */
+
+#define FMC_SDCR2_NR 0x0000000CU /*!<NR[1:0] bits (Number of row bits) */
+#define FMC_SDCR2_NR_0 0x00000004U /*!<Bit 0 */
+#define FMC_SDCR2_NR_1 0x00000008U /*!<Bit 1 */
+
+#define FMC_SDCR2_MWID 0x00000030U /*!<NR[1:0] bits (Number of row bits) */
+#define FMC_SDCR2_MWID_0 0x00000010U /*!<Bit 0 */
+#define FMC_SDCR2_MWID_1 0x00000020U /*!<Bit 1 */
+
+#define FMC_SDCR2_NB 0x00000040U /*!<Number of internal bank */
+
+#define FMC_SDCR2_CAS 0x00000180U /*!<CAS[1:0] bits (CAS latency) */
+#define FMC_SDCR2_CAS_0 0x00000080U /*!<Bit 0 */
+#define FMC_SDCR2_CAS_1 0x00000100U /*!<Bit 1 */
+
+#define FMC_SDCR2_WP 0x00000200U /*!<Write protection */
+
+#define FMC_SDCR2_SDCLK 0x00000C00U /*!<SDCLK[1:0] (SDRAM clock configuration) */
+#define FMC_SDCR2_SDCLK_0 0x00000400U /*!<Bit 0 */
+#define FMC_SDCR2_SDCLK_1 0x00000800U /*!<Bit 1 */
+
+#define FMC_SDCR2_RBURST 0x00001000U /*!<Read burst */
+
+#define FMC_SDCR2_RPIPE 0x00006000U /*!<RPIPE[1:0](Read pipe) */
+#define FMC_SDCR2_RPIPE_0 0x00002000U /*!<Bit 0 */
+#define FMC_SDCR2_RPIPE_1 0x00004000U /*!<Bit 1 */
+
+/****************** Bit definition for FMC_SDTR1 register ******************/
+#define FMC_SDTR1_TMRD 0x0000000FU /*!<TMRD[3:0] bits (Load mode register to active) */
+#define FMC_SDTR1_TMRD_0 0x00000001U /*!<Bit 0 */
+#define FMC_SDTR1_TMRD_1 0x00000002U /*!<Bit 1 */
+#define FMC_SDTR1_TMRD_2 0x00000004U /*!<Bit 2 */
+#define FMC_SDTR1_TMRD_3 0x00000008U /*!<Bit 3 */
+
+#define FMC_SDTR1_TXSR 0x000000F0U /*!<TXSR[3:0] bits (Exit self refresh) */
+#define FMC_SDTR1_TXSR_0 0x00000010U /*!<Bit 0 */
+#define FMC_SDTR1_TXSR_1 0x00000020U /*!<Bit 1 */
+#define FMC_SDTR1_TXSR_2 0x00000040U /*!<Bit 2 */
+#define FMC_SDTR1_TXSR_3 0x00000080U /*!<Bit 3 */
+
+#define FMC_SDTR1_TRAS 0x00000F00U /*!<TRAS[3:0] bits (Self refresh time) */
+#define FMC_SDTR1_TRAS_0 0x00000100U /*!<Bit 0 */
+#define FMC_SDTR1_TRAS_1 0x00000200U /*!<Bit 1 */
+#define FMC_SDTR1_TRAS_2 0x00000400U /*!<Bit 2 */
+#define FMC_SDTR1_TRAS_3 0x00000800U /*!<Bit 3 */
+
+#define FMC_SDTR1_TRC 0x0000F000U /*!<TRC[2:0] bits (Row cycle delay) */
+#define FMC_SDTR1_TRC_0 0x00001000U /*!<Bit 0 */
+#define FMC_SDTR1_TRC_1 0x00002000U /*!<Bit 1 */
+#define FMC_SDTR1_TRC_2 0x00004000U /*!<Bit 2 */
+
+#define FMC_SDTR1_TWR 0x000F0000U /*!<TRC[2:0] bits (Write recovery delay) */
+#define FMC_SDTR1_TWR_0 0x00010000U /*!<Bit 0 */
+#define FMC_SDTR1_TWR_1 0x00020000U /*!<Bit 1 */
+#define FMC_SDTR1_TWR_2 0x00040000U /*!<Bit 2 */
+
+#define FMC_SDTR1_TRP 0x00F00000U /*!<TRP[2:0] bits (Row precharge delay) */
+#define FMC_SDTR1_TRP_0 0x00100000U /*!<Bit 0 */
+#define FMC_SDTR1_TRP_1 0x00200000U /*!<Bit 1 */
+#define FMC_SDTR1_TRP_2 0x00400000U /*!<Bit 2 */
+
+#define FMC_SDTR1_TRCD 0x0F000000U /*!<TRP[2:0] bits (Row to column delay) */
+#define FMC_SDTR1_TRCD_0 0x01000000U /*!<Bit 0 */
+#define FMC_SDTR1_TRCD_1 0x02000000U /*!<Bit 1 */
+#define FMC_SDTR1_TRCD_2 0x04000000U /*!<Bit 2 */
+
+/****************** Bit definition for FMC_SDTR2 register ******************/
+#define FMC_SDTR2_TMRD 0x0000000FU /*!<TMRD[3:0] bits (Load mode register to active) */
+#define FMC_SDTR2_TMRD_0 0x00000001U /*!<Bit 0 */
+#define FMC_SDTR2_TMRD_1 0x00000002U /*!<Bit 1 */
+#define FMC_SDTR2_TMRD_2 0x00000004U /*!<Bit 2 */
+#define FMC_SDTR2_TMRD_3 0x00000008U /*!<Bit 3 */
+
+#define FMC_SDTR2_TXSR 0x000000F0U /*!<TXSR[3:0] bits (Exit self refresh) */
+#define FMC_SDTR2_TXSR_0 0x00000010U /*!<Bit 0 */
+#define FMC_SDTR2_TXSR_1 0x00000020U /*!<Bit 1 */
+#define FMC_SDTR2_TXSR_2 0x00000040U /*!<Bit 2 */
+#define FMC_SDTR2_TXSR_3 0x00000080U /*!<Bit 3 */
+
+#define FMC_SDTR2_TRAS 0x00000F00U /*!<TRAS[3:0] bits (Self refresh time) */
+#define FMC_SDTR2_TRAS_0 0x00000100U /*!<Bit 0 */
+#define FMC_SDTR2_TRAS_1 0x00000200U /*!<Bit 1 */
+#define FMC_SDTR2_TRAS_2 0x00000400U /*!<Bit 2 */
+#define FMC_SDTR2_TRAS_3 0x00000800U /*!<Bit 3 */
+
+#define FMC_SDTR2_TRC 0x0000F000U /*!<TRC[2:0] bits (Row cycle delay) */
+#define FMC_SDTR2_TRC_0 0x00001000U /*!<Bit 0 */
+#define FMC_SDTR2_TRC_1 0x00002000U /*!<Bit 1 */
+#define FMC_SDTR2_TRC_2 0x00004000U /*!<Bit 2 */
+
+#define FMC_SDTR2_TWR 0x000F0000U /*!<TRC[2:0] bits (Write recovery delay) */
+#define FMC_SDTR2_TWR_0 0x00010000U /*!<Bit 0 */
+#define FMC_SDTR2_TWR_1 0x00020000U /*!<Bit 1 */
+#define FMC_SDTR2_TWR_2 0x00040000U /*!<Bit 2 */
+
+#define FMC_SDTR2_TRP 0x00F00000U /*!<TRP[2:0] bits (Row precharge delay) */
+#define FMC_SDTR2_TRP_0 0x00100000U /*!<Bit 0 */
+#define FMC_SDTR2_TRP_1 0x00200000U /*!<Bit 1 */
+#define FMC_SDTR2_TRP_2 0x00400000U /*!<Bit 2 */
+
+#define FMC_SDTR2_TRCD 0x0F000000U /*!<TRP[2:0] bits (Row to column delay) */
+#define FMC_SDTR2_TRCD_0 0x01000000U /*!<Bit 0 */
+#define FMC_SDTR2_TRCD_1 0x02000000U /*!<Bit 1 */
+#define FMC_SDTR2_TRCD_2 0x04000000U /*!<Bit 2 */
+
+/****************** Bit definition for FMC_SDCMR register ******************/
+#define FMC_SDCMR_MODE 0x00000007U /*!<MODE[2:0] bits (Command mode) */
+#define FMC_SDCMR_MODE_0 0x00000001U /*!<Bit 0 */
+#define FMC_SDCMR_MODE_1 0x00000002U /*!<Bit 1 */
+#define FMC_SDCMR_MODE_2 0x00000004U /*!<Bit 2 */
+
+#define FMC_SDCMR_CTB2 0x00000008U /*!<Command target 2 */
+
+#define FMC_SDCMR_CTB1 0x00000010U /*!<Command target 1 */
+
+#define FMC_SDCMR_NRFS 0x000001E0U /*!<NRFS[3:0] bits (Number of auto-refresh) */
+#define FMC_SDCMR_NRFS_0 0x00000020U /*!<Bit 0 */
+#define FMC_SDCMR_NRFS_1 0x00000040U /*!<Bit 1 */
+#define FMC_SDCMR_NRFS_2 0x00000080U /*!<Bit 2 */
+#define FMC_SDCMR_NRFS_3 0x00000100U /*!<Bit 3 */
+
+#define FMC_SDCMR_MRD 0x003FFE00U /*!<MRD[12:0] bits (Mode register definition) */
+
+/****************** Bit definition for FMC_SDRTR register ******************/
+#define FMC_SDRTR_CRE 0x00000001U /*!<Clear refresh error flag */
+
+#define FMC_SDRTR_COUNT 0x00003FFEU /*!<COUNT[12:0] bits (Refresh timer count) */
+
+#define FMC_SDRTR_REIE 0x00004000U /*!<RES interupt enable */
+
+/****************** Bit definition for FMC_SDSR register ******************/
+#define FMC_SDSR_RE 0x00000001U /*!<Refresh error flag */
+
+#define FMC_SDSR_MODES1 0x00000006U /*!<MODES1[1:0]bits (Status mode for bank 1) */
+#define FMC_SDSR_MODES1_0 0x00000002U /*!<Bit 0 */
+#define FMC_SDSR_MODES1_1 0x00000004U /*!<Bit 1 */
+
+#define FMC_SDSR_MODES2 0x00000018U /*!<MODES2[1:0]bits (Status mode for bank 2) */
+#define FMC_SDSR_MODES2_0 0x00000008U /*!<Bit 0 */
+#define FMC_SDSR_MODES2_1 0x00000010U /*!<Bit 1 */
+#define FMC_SDSR_BUSY 0x00000020U /*!<Busy status */
+
+/******************************************************************************/
+/* */
+/* General Purpose I/O */
+/* */
+/******************************************************************************/
+/****************** Bits definition for GPIO_MODER register *****************/
+#define GPIO_MODER_MODER0 0x00000003U
+#define GPIO_MODER_MODER0_0 0x00000001U
+#define GPIO_MODER_MODER0_1 0x00000002U
+
+#define GPIO_MODER_MODER1 0x0000000CU
+#define GPIO_MODER_MODER1_0 0x00000004U
+#define GPIO_MODER_MODER1_1 0x00000008U
+
+#define GPIO_MODER_MODER2 0x00000030U
+#define GPIO_MODER_MODER2_0 0x00000010U
+#define GPIO_MODER_MODER2_1 0x00000020U
+
+#define GPIO_MODER_MODER3 0x000000C0U
+#define GPIO_MODER_MODER3_0 0x00000040U
+#define GPIO_MODER_MODER3_1 0x00000080U
+
+#define GPIO_MODER_MODER4 0x00000300U
+#define GPIO_MODER_MODER4_0 0x00000100U
+#define GPIO_MODER_MODER4_1 0x00000200U
+
+#define GPIO_MODER_MODER5 0x00000C00U
+#define GPIO_MODER_MODER5_0 0x00000400U
+#define GPIO_MODER_MODER5_1 0x00000800U
+
+#define GPIO_MODER_MODER6 0x00003000U
+#define GPIO_MODER_MODER6_0 0x00001000U
+#define GPIO_MODER_MODER6_1 0x00002000U
+
+#define GPIO_MODER_MODER7 0x0000C000U
+#define GPIO_MODER_MODER7_0 0x00004000U
+#define GPIO_MODER_MODER7_1 0x00008000U
+
+#define GPIO_MODER_MODER8 0x00030000U
+#define GPIO_MODER_MODER8_0 0x00010000U
+#define GPIO_MODER_MODER8_1 0x00020000U
+
+#define GPIO_MODER_MODER9 0x000C0000U
+#define GPIO_MODER_MODER9_0 0x00040000U
+#define GPIO_MODER_MODER9_1 0x00080000U
+
+#define GPIO_MODER_MODER10 0x00300000U
+#define GPIO_MODER_MODER10_0 0x00100000U
+#define GPIO_MODER_MODER10_1 0x00200000U
+
+#define GPIO_MODER_MODER11 0x00C00000U
+#define GPIO_MODER_MODER11_0 0x00400000U
+#define GPIO_MODER_MODER11_1 0x00800000U
+
+#define GPIO_MODER_MODER12 0x03000000U
+#define GPIO_MODER_MODER12_0 0x01000000U
+#define GPIO_MODER_MODER12_1 0x02000000U
+
+#define GPIO_MODER_MODER13 0x0C000000U
+#define GPIO_MODER_MODER13_0 0x04000000U
+#define GPIO_MODER_MODER13_1 0x08000000U
+
+#define GPIO_MODER_MODER14 0x30000000U
+#define GPIO_MODER_MODER14_0 0x10000000U
+#define GPIO_MODER_MODER14_1 0x20000000U
+
+#define GPIO_MODER_MODER15 0xC0000000U
+#define GPIO_MODER_MODER15_0 0x40000000U
+#define GPIO_MODER_MODER15_1 0x80000000U
+
+/****************** Bits definition for GPIO_OTYPER register ****************/
+#define GPIO_OTYPER_OT_0 0x00000001U
+#define GPIO_OTYPER_OT_1 0x00000002U
+#define GPIO_OTYPER_OT_2 0x00000004U
+#define GPIO_OTYPER_OT_3 0x00000008U
+#define GPIO_OTYPER_OT_4 0x00000010U
+#define GPIO_OTYPER_OT_5 0x00000020U
+#define GPIO_OTYPER_OT_6 0x00000040U
+#define GPIO_OTYPER_OT_7 0x00000080U
+#define GPIO_OTYPER_OT_8 0x00000100U
+#define GPIO_OTYPER_OT_9 0x00000200U
+#define GPIO_OTYPER_OT_10 0x00000400U
+#define GPIO_OTYPER_OT_11 0x00000800U
+#define GPIO_OTYPER_OT_12 0x00001000U
+#define GPIO_OTYPER_OT_13 0x00002000U
+#define GPIO_OTYPER_OT_14 0x00004000U
+#define GPIO_OTYPER_OT_15 0x00008000U
+
+/****************** Bits definition for GPIO_OSPEEDR register ***************/
+#define GPIO_OSPEEDER_OSPEEDR0 0x00000003U
+#define GPIO_OSPEEDER_OSPEEDR0_0 0x00000001U
+#define GPIO_OSPEEDER_OSPEEDR0_1 0x00000002U
+
+#define GPIO_OSPEEDER_OSPEEDR1 0x0000000CU
+#define GPIO_OSPEEDER_OSPEEDR1_0 0x00000004U
+#define GPIO_OSPEEDER_OSPEEDR1_1 0x00000008U
+
+#define GPIO_OSPEEDER_OSPEEDR2 0x00000030U
+#define GPIO_OSPEEDER_OSPEEDR2_0 0x00000010U
+#define GPIO_OSPEEDER_OSPEEDR2_1 0x00000020U
+
+#define GPIO_OSPEEDER_OSPEEDR3 0x000000C0U
+#define GPIO_OSPEEDER_OSPEEDR3_0 0x00000040U
+#define GPIO_OSPEEDER_OSPEEDR3_1 0x00000080U
+
+#define GPIO_OSPEEDER_OSPEEDR4 0x00000300U
+#define GPIO_OSPEEDER_OSPEEDR4_0 0x00000100U
+#define GPIO_OSPEEDER_OSPEEDR4_1 0x00000200U
+
+#define GPIO_OSPEEDER_OSPEEDR5 0x00000C00U
+#define GPIO_OSPEEDER_OSPEEDR5_0 0x00000400U
+#define GPIO_OSPEEDER_OSPEEDR5_1 0x00000800U
+
+#define GPIO_OSPEEDER_OSPEEDR6 0x00003000U
+#define GPIO_OSPEEDER_OSPEEDR6_0 0x00001000U
+#define GPIO_OSPEEDER_OSPEEDR6_1 0x00002000U
+
+#define GPIO_OSPEEDER_OSPEEDR7 0x0000C000U
+#define GPIO_OSPEEDER_OSPEEDR7_0 0x00004000U
+#define GPIO_OSPEEDER_OSPEEDR7_1 0x00008000U
+
+#define GPIO_OSPEEDER_OSPEEDR8 0x00030000U
+#define GPIO_OSPEEDER_OSPEEDR8_0 0x00010000U
+#define GPIO_OSPEEDER_OSPEEDR8_1 0x00020000U
+
+#define GPIO_OSPEEDER_OSPEEDR9 0x000C0000U
+#define GPIO_OSPEEDER_OSPEEDR9_0 0x00040000U
+#define GPIO_OSPEEDER_OSPEEDR9_1 0x00080000U
+
+#define GPIO_OSPEEDER_OSPEEDR10 0x00300000U
+#define GPIO_OSPEEDER_OSPEEDR10_0 0x00100000U
+#define GPIO_OSPEEDER_OSPEEDR10_1 0x00200000U
+
+#define GPIO_OSPEEDER_OSPEEDR11 0x00C00000U
+#define GPIO_OSPEEDER_OSPEEDR11_0 0x00400000U
+#define GPIO_OSPEEDER_OSPEEDR11_1 0x00800000U
+
+#define GPIO_OSPEEDER_OSPEEDR12 0x03000000U
+#define GPIO_OSPEEDER_OSPEEDR12_0 0x01000000U
+#define GPIO_OSPEEDER_OSPEEDR12_1 0x02000000U
+
+#define GPIO_OSPEEDER_OSPEEDR13 0x0C000000U
+#define GPIO_OSPEEDER_OSPEEDR13_0 0x04000000U
+#define GPIO_OSPEEDER_OSPEEDR13_1 0x08000000U
+
+#define GPIO_OSPEEDER_OSPEEDR14 0x30000000U
+#define GPIO_OSPEEDER_OSPEEDR14_0 0x10000000U
+#define GPIO_OSPEEDER_OSPEEDR14_1 0x20000000U
+
+#define GPIO_OSPEEDER_OSPEEDR15 0xC0000000U
+#define GPIO_OSPEEDER_OSPEEDR15_0 0x40000000U
+#define GPIO_OSPEEDER_OSPEEDR15_1 0x80000000U
+
+/****************** Bits definition for GPIO_PUPDR register *****************/
+#define GPIO_PUPDR_PUPDR0 0x00000003U
+#define GPIO_PUPDR_PUPDR0_0 0x00000001U
+#define GPIO_PUPDR_PUPDR0_1 0x00000002U
+
+#define GPIO_PUPDR_PUPDR1 0x0000000CU
+#define GPIO_PUPDR_PUPDR1_0 0x00000004U
+#define GPIO_PUPDR_PUPDR1_1 0x00000008U
+
+#define GPIO_PUPDR_PUPDR2 0x00000030U
+#define GPIO_PUPDR_PUPDR2_0 0x00000010U
+#define GPIO_PUPDR_PUPDR2_1 0x00000020U
+
+#define GPIO_PUPDR_PUPDR3 0x000000C0U
+#define GPIO_PUPDR_PUPDR3_0 0x00000040U
+#define GPIO_PUPDR_PUPDR3_1 0x00000080U
+
+#define GPIO_PUPDR_PUPDR4 0x00000300U
+#define GPIO_PUPDR_PUPDR4_0 0x00000100U
+#define GPIO_PUPDR_PUPDR4_1 0x00000200U
+
+#define GPIO_PUPDR_PUPDR5 0x00000C00U
+#define GPIO_PUPDR_PUPDR5_0 0x00000400U
+#define GPIO_PUPDR_PUPDR5_1 0x00000800U
+
+#define GPIO_PUPDR_PUPDR6 0x00003000U
+#define GPIO_PUPDR_PUPDR6_0 0x00001000U
+#define GPIO_PUPDR_PUPDR6_1 0x00002000U
+
+#define GPIO_PUPDR_PUPDR7 0x0000C000U
+#define GPIO_PUPDR_PUPDR7_0 0x00004000U
+#define GPIO_PUPDR_PUPDR7_1 0x00008000U
+
+#define GPIO_PUPDR_PUPDR8 0x00030000U
+#define GPIO_PUPDR_PUPDR8_0 0x00010000U
+#define GPIO_PUPDR_PUPDR8_1 0x00020000U
+
+#define GPIO_PUPDR_PUPDR9 0x000C0000U
+#define GPIO_PUPDR_PUPDR9_0 0x00040000U
+#define GPIO_PUPDR_PUPDR9_1 0x00080000U
+
+#define GPIO_PUPDR_PUPDR10 0x00300000U
+#define GPIO_PUPDR_PUPDR10_0 0x00100000U
+#define GPIO_PUPDR_PUPDR10_1 0x00200000U
+
+#define GPIO_PUPDR_PUPDR11 0x00C00000U
+#define GPIO_PUPDR_PUPDR11_0 0x00400000U
+#define GPIO_PUPDR_PUPDR11_1 0x00800000U
+
+#define GPIO_PUPDR_PUPDR12 0x03000000U
+#define GPIO_PUPDR_PUPDR12_0 0x01000000U
+#define GPIO_PUPDR_PUPDR12_1 0x02000000U
+
+#define GPIO_PUPDR_PUPDR13 0x0C000000U
+#define GPIO_PUPDR_PUPDR13_0 0x04000000U
+#define GPIO_PUPDR_PUPDR13_1 0x08000000U
+
+#define GPIO_PUPDR_PUPDR14 0x30000000U
+#define GPIO_PUPDR_PUPDR14_0 0x10000000U
+#define GPIO_PUPDR_PUPDR14_1 0x20000000U
+
+#define GPIO_PUPDR_PUPDR15 0xC0000000U
+#define GPIO_PUPDR_PUPDR15_0 0x40000000U
+#define GPIO_PUPDR_PUPDR15_1 0x80000000U
+
+/****************** Bits definition for GPIO_IDR register *******************/
+#define GPIO_IDR_IDR_0 0x00000001U
+#define GPIO_IDR_IDR_1 0x00000002U
+#define GPIO_IDR_IDR_2 0x00000004U
+#define GPIO_IDR_IDR_3 0x00000008U
+#define GPIO_IDR_IDR_4 0x00000010U
+#define GPIO_IDR_IDR_5 0x00000020U
+#define GPIO_IDR_IDR_6 0x00000040U
+#define GPIO_IDR_IDR_7 0x00000080U
+#define GPIO_IDR_IDR_8 0x00000100U
+#define GPIO_IDR_IDR_9 0x00000200U
+#define GPIO_IDR_IDR_10 0x00000400U
+#define GPIO_IDR_IDR_11 0x00000800U
+#define GPIO_IDR_IDR_12 0x00001000U
+#define GPIO_IDR_IDR_13 0x00002000U
+#define GPIO_IDR_IDR_14 0x00004000U
+#define GPIO_IDR_IDR_15 0x00008000U
+/* Old GPIO_IDR register bits definition, maintained for legacy purpose */
+#define GPIO_OTYPER_IDR_0 GPIO_IDR_IDR_0
+#define GPIO_OTYPER_IDR_1 GPIO_IDR_IDR_1
+#define GPIO_OTYPER_IDR_2 GPIO_IDR_IDR_2
+#define GPIO_OTYPER_IDR_3 GPIO_IDR_IDR_3
+#define GPIO_OTYPER_IDR_4 GPIO_IDR_IDR_4
+#define GPIO_OTYPER_IDR_5 GPIO_IDR_IDR_5
+#define GPIO_OTYPER_IDR_6 GPIO_IDR_IDR_6
+#define GPIO_OTYPER_IDR_7 GPIO_IDR_IDR_7
+#define GPIO_OTYPER_IDR_8 GPIO_IDR_IDR_8
+#define GPIO_OTYPER_IDR_9 GPIO_IDR_IDR_9
+#define GPIO_OTYPER_IDR_10 GPIO_IDR_IDR_10
+#define GPIO_OTYPER_IDR_11 GPIO_IDR_IDR_11
+#define GPIO_OTYPER_IDR_12 GPIO_IDR_IDR_12
+#define GPIO_OTYPER_IDR_13 GPIO_IDR_IDR_13
+#define GPIO_OTYPER_IDR_14 GPIO_IDR_IDR_14
+#define GPIO_OTYPER_IDR_15 GPIO_IDR_IDR_15
+
+/****************** Bits definition for GPIO_ODR register *******************/
+#define GPIO_ODR_ODR_0 0x00000001U
+#define GPIO_ODR_ODR_1 0x00000002U
+#define GPIO_ODR_ODR_2 0x00000004U
+#define GPIO_ODR_ODR_3 0x00000008U
+#define GPIO_ODR_ODR_4 0x00000010U
+#define GPIO_ODR_ODR_5 0x00000020U
+#define GPIO_ODR_ODR_6 0x00000040U
+#define GPIO_ODR_ODR_7 0x00000080U
+#define GPIO_ODR_ODR_8 0x00000100U
+#define GPIO_ODR_ODR_9 0x00000200U
+#define GPIO_ODR_ODR_10 0x00000400U
+#define GPIO_ODR_ODR_11 0x00000800U
+#define GPIO_ODR_ODR_12 0x00001000U
+#define GPIO_ODR_ODR_13 0x00002000U
+#define GPIO_ODR_ODR_14 0x00004000U
+#define GPIO_ODR_ODR_15 0x00008000U
+/* Old GPIO_ODR register bits definition, maintained for legacy purpose */
+#define GPIO_OTYPER_ODR_0 GPIO_ODR_ODR_0
+#define GPIO_OTYPER_ODR_1 GPIO_ODR_ODR_1
+#define GPIO_OTYPER_ODR_2 GPIO_ODR_ODR_2
+#define GPIO_OTYPER_ODR_3 GPIO_ODR_ODR_3
+#define GPIO_OTYPER_ODR_4 GPIO_ODR_ODR_4
+#define GPIO_OTYPER_ODR_5 GPIO_ODR_ODR_5
+#define GPIO_OTYPER_ODR_6 GPIO_ODR_ODR_6
+#define GPIO_OTYPER_ODR_7 GPIO_ODR_ODR_7
+#define GPIO_OTYPER_ODR_8 GPIO_ODR_ODR_8
+#define GPIO_OTYPER_ODR_9 GPIO_ODR_ODR_9
+#define GPIO_OTYPER_ODR_10 GPIO_ODR_ODR_10
+#define GPIO_OTYPER_ODR_11 GPIO_ODR_ODR_11
+#define GPIO_OTYPER_ODR_12 GPIO_ODR_ODR_12
+#define GPIO_OTYPER_ODR_13 GPIO_ODR_ODR_13
+#define GPIO_OTYPER_ODR_14 GPIO_ODR_ODR_14
+#define GPIO_OTYPER_ODR_15 GPIO_ODR_ODR_15
+
+/****************** Bits definition for GPIO_BSRR register ******************/
+#define GPIO_BSRR_BS_0 0x00000001U
+#define GPIO_BSRR_BS_1 0x00000002U
+#define GPIO_BSRR_BS_2 0x00000004U
+#define GPIO_BSRR_BS_3 0x00000008U
+#define GPIO_BSRR_BS_4 0x00000010U
+#define GPIO_BSRR_BS_5 0x00000020U
+#define GPIO_BSRR_BS_6 0x00000040U
+#define GPIO_BSRR_BS_7 0x00000080U
+#define GPIO_BSRR_BS_8 0x00000100U
+#define GPIO_BSRR_BS_9 0x00000200U
+#define GPIO_BSRR_BS_10 0x00000400U
+#define GPIO_BSRR_BS_11 0x00000800U
+#define GPIO_BSRR_BS_12 0x00001000U
+#define GPIO_BSRR_BS_13 0x00002000U
+#define GPIO_BSRR_BS_14 0x00004000U
+#define GPIO_BSRR_BS_15 0x00008000U
+#define GPIO_BSRR_BR_0 0x00010000U
+#define GPIO_BSRR_BR_1 0x00020000U
+#define GPIO_BSRR_BR_2 0x00040000U
+#define GPIO_BSRR_BR_3 0x00080000U
+#define GPIO_BSRR_BR_4 0x00100000U
+#define GPIO_BSRR_BR_5 0x00200000U
+#define GPIO_BSRR_BR_6 0x00400000U
+#define GPIO_BSRR_BR_7 0x00800000U
+#define GPIO_BSRR_BR_8 0x01000000U
+#define GPIO_BSRR_BR_9 0x02000000U
+#define GPIO_BSRR_BR_10 0x04000000U
+#define GPIO_BSRR_BR_11 0x08000000U
+#define GPIO_BSRR_BR_12 0x10000000U
+#define GPIO_BSRR_BR_13 0x20000000U
+#define GPIO_BSRR_BR_14 0x40000000U
+#define GPIO_BSRR_BR_15 0x80000000U
+
+/****************** Bit definition for GPIO_LCKR register *********************/
+#define GPIO_LCKR_LCK0 0x00000001U
+#define GPIO_LCKR_LCK1 0x00000002U
+#define GPIO_LCKR_LCK2 0x00000004U
+#define GPIO_LCKR_LCK3 0x00000008U
+#define GPIO_LCKR_LCK4 0x00000010U
+#define GPIO_LCKR_LCK5 0x00000020U
+#define GPIO_LCKR_LCK6 0x00000040U
+#define GPIO_LCKR_LCK7 0x00000080U
+#define GPIO_LCKR_LCK8 0x00000100U
+#define GPIO_LCKR_LCK9 0x00000200U
+#define GPIO_LCKR_LCK10 0x00000400U
+#define GPIO_LCKR_LCK11 0x00000800U
+#define GPIO_LCKR_LCK12 0x00001000U
+#define GPIO_LCKR_LCK13 0x00002000U
+#define GPIO_LCKR_LCK14 0x00004000U
+#define GPIO_LCKR_LCK15 0x00008000U
+#define GPIO_LCKR_LCKK 0x00010000U
+
+/******************************************************************************/
+/* */
+/* HASH */
+/* */
+/******************************************************************************/
+/****************** Bits definition for HASH_CR register ********************/
+#define HASH_CR_INIT 0x00000004U
+#define HASH_CR_DMAE 0x00000008U
+#define HASH_CR_DATATYPE 0x00000030U
+#define HASH_CR_DATATYPE_0 0x00000010U
+#define HASH_CR_DATATYPE_1 0x00000020U
+#define HASH_CR_MODE 0x00000040U
+#define HASH_CR_ALGO 0x00040080U
+#define HASH_CR_ALGO_0 0x00000080U
+#define HASH_CR_ALGO_1 0x00040000U
+#define HASH_CR_NBW 0x00000F00U
+#define HASH_CR_NBW_0 0x00000100U
+#define HASH_CR_NBW_1 0x00000200U
+#define HASH_CR_NBW_2 0x00000400U
+#define HASH_CR_NBW_3 0x00000800U
+#define HASH_CR_DINNE 0x00001000U
+#define HASH_CR_MDMAT 0x00002000U
+#define HASH_CR_LKEY 0x00010000U
+
+/****************** Bits definition for HASH_STR register *******************/
+#define HASH_STR_NBLW 0x0000001FU
+#define HASH_STR_NBLW_0 0x00000001U
+#define HASH_STR_NBLW_1 0x00000002U
+#define HASH_STR_NBLW_2 0x00000004U
+#define HASH_STR_NBLW_3 0x00000008U
+#define HASH_STR_NBLW_4 0x00000010U
+#define HASH_STR_DCAL 0x00000100U
+/* Aliases for HASH_STR register */
+#define HASH_STR_NBW HASH_STR_NBLW
+#define HASH_STR_NBW_0 HASH_STR_NBLW_0
+#define HASH_STR_NBW_1 HASH_STR_NBLW_1
+#define HASH_STR_NBW_2 HASH_STR_NBLW_2
+#define HASH_STR_NBW_3 HASH_STR_NBLW_3
+#define HASH_STR_NBW_4 HASH_STR_NBLW_4
+
+/****************** Bits definition for HASH_IMR register *******************/
+#define HASH_IMR_DINIE 0x00000001U
+#define HASH_IMR_DCIE 0x00000002U
+/* Aliases for HASH_IMR register */
+#define HASH_IMR_DINIM HASH_IMR_DINIE
+#define HASH_IMR_DCIM HASH_IMR_DCIE
+
+/****************** Bits definition for HASH_SR register ********************/
+#define HASH_SR_DINIS 0x00000001U
+#define HASH_SR_DCIS 0x00000002U
+#define HASH_SR_DMAS 0x00000004U
+#define HASH_SR_BUSY 0x00000008U
+
+/******************************************************************************/
+/* */
+/* Inter-integrated Circuit Interface */
+/* */
+/******************************************************************************/
+/******************* Bit definition for I2C_CR1 register ********************/
+#define I2C_CR1_PE 0x00000001U /*!<Peripheral Enable */
+#define I2C_CR1_SMBUS 0x00000002U /*!<SMBus Mode */
+#define I2C_CR1_SMBTYPE 0x00000008U /*!<SMBus Type */
+#define I2C_CR1_ENARP 0x00000010U /*!<ARP Enable */
+#define I2C_CR1_ENPEC 0x00000020U /*!<PEC Enable */
+#define I2C_CR1_ENGC 0x00000040U /*!<General Call Enable */
+#define I2C_CR1_NOSTRETCH 0x00000080U /*!<Clock Stretching Disable (Slave mode) */
+#define I2C_CR1_START 0x00000100U /*!<Start Generation */
+#define I2C_CR1_STOP 0x00000200U /*!<Stop Generation */
+#define I2C_CR1_ACK 0x00000400U /*!<Acknowledge Enable */
+#define I2C_CR1_POS 0x00000800U /*!<Acknowledge/PEC Position (for data reception) */
+#define I2C_CR1_PEC 0x00001000U /*!<Packet Error Checking */
+#define I2C_CR1_ALERT 0x00002000U /*!<SMBus Alert */
+#define I2C_CR1_SWRST 0x00008000U /*!<Software Reset */
+
+/******************* Bit definition for I2C_CR2 register ********************/
+#define I2C_CR2_FREQ 0x0000003FU /*!<FREQ[5:0] bits (Peripheral Clock Frequency) */
+#define I2C_CR2_FREQ_0 0x00000001U /*!<Bit 0 */
+#define I2C_CR2_FREQ_1 0x00000002U /*!<Bit 1 */
+#define I2C_CR2_FREQ_2 0x00000004U /*!<Bit 2 */
+#define I2C_CR2_FREQ_3 0x00000008U /*!<Bit 3 */
+#define I2C_CR2_FREQ_4 0x00000010U /*!<Bit 4 */
+#define I2C_CR2_FREQ_5 0x00000020U /*!<Bit 5 */
+
+#define I2C_CR2_ITERREN 0x00000100U /*!<Error Interrupt Enable */
+#define I2C_CR2_ITEVTEN 0x00000200U /*!<Event Interrupt Enable */
+#define I2C_CR2_ITBUFEN 0x00000400U /*!<Buffer Interrupt Enable */
+#define I2C_CR2_DMAEN 0x00000800U /*!<DMA Requests Enable */
+#define I2C_CR2_LAST 0x00001000U /*!<DMA Last Transfer */
+
+/******************* Bit definition for I2C_OAR1 register *******************/
+#define I2C_OAR1_ADD1_7 0x000000FEU /*!<Interface Address */
+#define I2C_OAR1_ADD8_9 0x00000300U /*!<Interface Address */
+
+#define I2C_OAR1_ADD0 0x00000001U /*!<Bit 0 */
+#define I2C_OAR1_ADD1 0x00000002U /*!<Bit 1 */
+#define I2C_OAR1_ADD2 0x00000004U /*!<Bit 2 */
+#define I2C_OAR1_ADD3 0x00000008U /*!<Bit 3 */
+#define I2C_OAR1_ADD4 0x00000010U /*!<Bit 4 */
+#define I2C_OAR1_ADD5 0x00000020U /*!<Bit 5 */
+#define I2C_OAR1_ADD6 0x00000040U /*!<Bit 6 */
+#define I2C_OAR1_ADD7 0x00000080U /*!<Bit 7 */
+#define I2C_OAR1_ADD8 0x00000100U /*!<Bit 8 */
+#define I2C_OAR1_ADD9 0x00000200U /*!<Bit 9 */
+
+#define I2C_OAR1_ADDMODE 0x00008000U /*!<Addressing Mode (Slave mode) */
+
+/******************* Bit definition for I2C_OAR2 register *******************/
+#define I2C_OAR2_ENDUAL 0x00000001U /*!<Dual addressing mode enable */
+#define I2C_OAR2_ADD2 0x000000FEU /*!<Interface address */
+
+/******************** Bit definition for I2C_DR register ********************/
+#define I2C_DR_DR 0x000000FFU /*!<8-bit Data Register */
+
+/******************* Bit definition for I2C_SR1 register ********************/
+#define I2C_SR1_SB 0x00000001U /*!<Start Bit (Master mode) */
+#define I2C_SR1_ADDR 0x00000002U /*!<Address sent (master mode)/matched (slave mode) */
+#define I2C_SR1_BTF 0x00000004U /*!<Byte Transfer Finished */
+#define I2C_SR1_ADD10 0x00000008U /*!<10-bit header sent (Master mode) */
+#define I2C_SR1_STOPF 0x00000010U /*!<Stop detection (Slave mode) */
+#define I2C_SR1_RXNE 0x00000040U /*!<Data Register not Empty (receivers) */
+#define I2C_SR1_TXE 0x00000080U /*!<Data Register Empty (transmitters) */
+#define I2C_SR1_BERR 0x00000100U /*!<Bus Error */
+#define I2C_SR1_ARLO 0x00000200U /*!<Arbitration Lost (master mode) */
+#define I2C_SR1_AF 0x00000400U /*!<Acknowledge Failure */
+#define I2C_SR1_OVR 0x00000800U /*!<Overrun/Underrun */
+#define I2C_SR1_PECERR 0x00001000U /*!<PEC Error in reception */
+#define I2C_SR1_TIMEOUT 0x00004000U /*!<Timeout or Tlow Error */
+#define I2C_SR1_SMBALERT 0x00008000U /*!<SMBus Alert */
+
+/******************* Bit definition for I2C_SR2 register ********************/
+#define I2C_SR2_MSL 0x00000001U /*!<Master/Slave */
+#define I2C_SR2_BUSY 0x00000002U /*!<Bus Busy */
+#define I2C_SR2_TRA 0x00000004U /*!<Transmitter/Receiver */
+#define I2C_SR2_GENCALL 0x00000010U /*!<General Call Address (Slave mode) */
+#define I2C_SR2_SMBDEFAULT 0x00000020U /*!<SMBus Device Default Address (Slave mode) */
+#define I2C_SR2_SMBHOST 0x00000040U /*!<SMBus Host Header (Slave mode) */
+#define I2C_SR2_DUALF 0x00000080U /*!<Dual Flag (Slave mode) */
+#define I2C_SR2_PEC 0x0000FF00U /*!<Packet Error Checking Register */
+
+/******************* Bit definition for I2C_CCR register ********************/
+#define I2C_CCR_CCR 0x00000FFFU /*!<Clock Control Register in Fast/Standard mode (Master mode) */
+#define I2C_CCR_DUTY 0x00004000U /*!<Fast Mode Duty Cycle */
+#define I2C_CCR_FS 0x00008000U /*!<I2C Master Mode Selection */
+
+/****************** Bit definition for I2C_TRISE register *******************/
+#define I2C_TRISE_TRISE 0x0000003FU /*!<Maximum Rise Time in Fast/Standard mode (Master mode) */
+
+/****************** Bit definition for I2C_FLTR register *******************/
+#define I2C_FLTR_DNF 0x0000000FU /*!<Digital Noise Filter */
+#define I2C_FLTR_ANOFF 0x00000010U /*!<Analog Noise Filter OFF */
+
+/******************************************************************************/
+/* */
+/* Independent WATCHDOG */
+/* */
+/******************************************************************************/
+/******************* Bit definition for IWDG_KR register ********************/
+#define IWDG_KR_KEY 0xFFFFU /*!<Key value (write only, read 0000h) */
+
+/******************* Bit definition for IWDG_PR register ********************/
+#define IWDG_PR_PR 0x07U /*!<PR[2:0] (Prescaler divider) */
+#define IWDG_PR_PR_0 0x01U /*!<Bit 0 */
+#define IWDG_PR_PR_1 0x02U /*!<Bit 1 */
+#define IWDG_PR_PR_2 0x04U /*!<Bit 2 */
+
+/******************* Bit definition for IWDG_RLR register *******************/
+#define IWDG_RLR_RL 0x0FFFU /*!<Watchdog counter reload value */
+
+/******************* Bit definition for IWDG_SR register ********************/
+#define IWDG_SR_PVU 0x01U /*!<Watchdog prescaler value update */
+#define IWDG_SR_RVU 0x02U /*!<Watchdog counter reload value update */
+
+
+/******************************************************************************/
+/* */
+/* LCD-TFT Display Controller (LTDC) */
+/* */
+/******************************************************************************/
+
+/******************** Bit definition for LTDC_SSCR register *****************/
+
+#define LTDC_SSCR_VSH 0x000007FFU /*!< Vertical Synchronization Height */
+#define LTDC_SSCR_HSW 0x0FFF0000U /*!< Horizontal Synchronization Width */
+
+/******************** Bit definition for LTDC_BPCR register *****************/
+
+#define LTDC_BPCR_AVBP 0x000007FFU /*!< Accumulated Vertical Back Porch */
+#define LTDC_BPCR_AHBP 0x0FFF0000U /*!< Accumulated Horizontal Back Porch */
+
+/******************** Bit definition for LTDC_AWCR register *****************/
+
+#define LTDC_AWCR_AAH 0x000007FFU /*!< Accumulated Active heigh */
+#define LTDC_AWCR_AAW 0x0FFF0000U /*!< Accumulated Active Width */
+
+/******************** Bit definition for LTDC_TWCR register *****************/
+
+#define LTDC_TWCR_TOTALH 0x000007FFU /*!< Total Heigh */
+#define LTDC_TWCR_TOTALW 0x0FFF0000U /*!< Total Width */
+
+/******************** Bit definition for LTDC_GCR register ******************/
+
+#define LTDC_GCR_LTDCEN 0x00000001U /*!< LCD-TFT controller enable bit */
+#define LTDC_GCR_DBW 0x00000070U /*!< Dither Blue Width */
+#define LTDC_GCR_DGW 0x00000700U /*!< Dither Green Width */
+#define LTDC_GCR_DRW 0x00007000U /*!< Dither Red Width */
+#define LTDC_GCR_DEN 0x00010000U /*!< Dither Enable */
+#define LTDC_GCR_PCPOL 0x10000000U /*!< Pixel Clock Polarity */
+#define LTDC_GCR_DEPOL 0x20000000U /*!< Data Enable Polarity */
+#define LTDC_GCR_VSPOL 0x40000000U /*!< Vertical Synchronization Polarity */
+#define LTDC_GCR_HSPOL 0x80000000U /*!< Horizontal Synchronization Polarity */
+
+/* Legacy defines */
+#define LTDC_GCR_DTEN LTDC_GCR_DEN
+
+/******************** Bit definition for LTDC_SRCR register *****************/
+
+#define LTDC_SRCR_IMR 0x00000001U /*!< Immediate Reload */
+#define LTDC_SRCR_VBR 0x00000002U /*!< Vertical Blanking Reload */
+
+/******************** Bit definition for LTDC_BCCR register *****************/
+
+#define LTDC_BCCR_BCBLUE 0x000000FFU /*!< Background Blue value */
+#define LTDC_BCCR_BCGREEN 0x0000FF00U /*!< Background Green value */
+#define LTDC_BCCR_BCRED 0x00FF0000U /*!< Background Red value */
+
+/******************** Bit definition for LTDC_IER register ******************/
+
+#define LTDC_IER_LIE 0x00000001U /*!< Line Interrupt Enable */
+#define LTDC_IER_FUIE 0x00000002U /*!< FIFO Underrun Interrupt Enable */
+#define LTDC_IER_TERRIE 0x00000004U /*!< Transfer Error Interrupt Enable */
+#define LTDC_IER_RRIE 0x00000008U /*!< Register Reload interrupt enable */
+
+/******************** Bit definition for LTDC_ISR register ******************/
+
+#define LTDC_ISR_LIF 0x00000001U /*!< Line Interrupt Flag */
+#define LTDC_ISR_FUIF 0x00000002U /*!< FIFO Underrun Interrupt Flag */
+#define LTDC_ISR_TERRIF 0x00000004U /*!< Transfer Error Interrupt Flag */
+#define LTDC_ISR_RRIF 0x00000008U /*!< Register Reload interrupt Flag */
+
+/******************** Bit definition for LTDC_ICR register ******************/
+
+#define LTDC_ICR_CLIF 0x00000001U /*!< Clears the Line Interrupt Flag */
+#define LTDC_ICR_CFUIF 0x00000002U /*!< Clears the FIFO Underrun Interrupt Flag */
+#define LTDC_ICR_CTERRIF 0x00000004U /*!< Clears the Transfer Error Interrupt Flag */
+#define LTDC_ICR_CRRIF 0x00000008U /*!< Clears Register Reload interrupt Flag */
+
+/******************** Bit definition for LTDC_LIPCR register ****************/
+
+#define LTDC_LIPCR_LIPOS 0x000007FFU /*!< Line Interrupt Position */
+
+/******************** Bit definition for LTDC_CPSR register *****************/
+
+#define LTDC_CPSR_CYPOS 0x0000FFFFU /*!< Current Y Position */
+#define LTDC_CPSR_CXPOS 0xFFFF0000U /*!< Current X Position */
+
+/******************** Bit definition for LTDC_CDSR register *****************/
+
+#define LTDC_CDSR_VDES 0x00000001U /*!< Vertical Data Enable Status */
+#define LTDC_CDSR_HDES 0x00000002U /*!< Horizontal Data Enable Status */
+#define LTDC_CDSR_VSYNCS 0x00000004U /*!< Vertical Synchronization Status */
+#define LTDC_CDSR_HSYNCS 0x00000008U /*!< Horizontal Synchronization Status */
+
+/******************** Bit definition for LTDC_LxCR register *****************/
+
+#define LTDC_LxCR_LEN 0x00000001U /*!< Layer Enable */
+#define LTDC_LxCR_COLKEN 0x00000002U /*!< Color Keying Enable */
+#define LTDC_LxCR_CLUTEN 0x00000010U /*!< Color Lockup Table Enable */
+
+/******************** Bit definition for LTDC_LxWHPCR register **************/
+
+#define LTDC_LxWHPCR_WHSTPOS 0x00000FFFU /*!< Window Horizontal Start Position */
+#define LTDC_LxWHPCR_WHSPPOS 0xFFFF0000U /*!< Window Horizontal Stop Position */
+
+/******************** Bit definition for LTDC_LxWVPCR register **************/
+
+#define LTDC_LxWVPCR_WVSTPOS 0x00000FFFU /*!< Window Vertical Start Position */
+#define LTDC_LxWVPCR_WVSPPOS 0xFFFF0000U /*!< Window Vertical Stop Position */
+
+/******************** Bit definition for LTDC_LxCKCR register ***************/
+
+#define LTDC_LxCKCR_CKBLUE 0x000000FFU /*!< Color Key Blue value */
+#define LTDC_LxCKCR_CKGREEN 0x0000FF00U /*!< Color Key Green value */
+#define LTDC_LxCKCR_CKRED 0x00FF0000U /*!< Color Key Red value */
+
+/******************** Bit definition for LTDC_LxPFCR register ***************/
+
+#define LTDC_LxPFCR_PF 0x00000007U /*!< Pixel Format */
+
+/******************** Bit definition for LTDC_LxCACR register ***************/
+
+#define LTDC_LxCACR_CONSTA 0x000000FFU /*!< Constant Alpha */
+
+/******************** Bit definition for LTDC_LxDCCR register ***************/
+
+#define LTDC_LxDCCR_DCBLUE 0x000000FFU /*!< Default Color Blue */
+#define LTDC_LxDCCR_DCGREEN 0x0000FF00U /*!< Default Color Green */
+#define LTDC_LxDCCR_DCRED 0x00FF0000U /*!< Default Color Red */
+#define LTDC_LxDCCR_DCALPHA 0xFF000000U /*!< Default Color Alpha */
+
+/******************** Bit definition for LTDC_LxBFCR register ***************/
+
+#define LTDC_LxBFCR_BF2 0x00000007U /*!< Blending Factor 2 */
+#define LTDC_LxBFCR_BF1 0x00000700U /*!< Blending Factor 1 */
+
+/******************** Bit definition for LTDC_LxCFBAR register **************/
+
+#define LTDC_LxCFBAR_CFBADD 0xFFFFFFFFU /*!< Color Frame Buffer Start Address */
+
+/******************** Bit definition for LTDC_LxCFBLR register **************/
+
+#define LTDC_LxCFBLR_CFBLL 0x00001FFFU /*!< Color Frame Buffer Line Length */
+#define LTDC_LxCFBLR_CFBP 0x1FFF0000U /*!< Color Frame Buffer Pitch in bytes */
+
+/******************** Bit definition for LTDC_LxCFBLNR register *************/
+
+#define LTDC_LxCFBLNR_CFBLNBR 0x000007FFU /*!< Frame Buffer Line Number */
+
+/******************** Bit definition for LTDC_LxCLUTWR register *************/
+
+#define LTDC_LxCLUTWR_BLUE 0x000000FFU /*!< Blue value */
+#define LTDC_LxCLUTWR_GREEN 0x0000FF00U /*!< Green value */
+#define LTDC_LxCLUTWR_RED 0x00FF0000U /*!< Red value */
+#define LTDC_LxCLUTWR_CLUTADD 0xFF000000U /*!< CLUT address */
+
+
+/******************************************************************************/
+/* */
+/* Power Control */
+/* */
+/******************************************************************************/
+/******************** Bit definition for PWR_CR register ********************/
+#define PWR_CR_LPDS 0x00000001U /*!< Low-Power Deepsleep */
+#define PWR_CR_PDDS 0x00000002U /*!< Power Down Deepsleep */
+#define PWR_CR_CWUF 0x00000004U /*!< Clear Wakeup Flag */
+#define PWR_CR_CSBF 0x00000008U /*!< Clear Standby Flag */
+#define PWR_CR_PVDE 0x00000010U /*!< Power Voltage Detector Enable */
+
+#define PWR_CR_PLS 0x000000E0U /*!< PLS[2:0] bits (PVD Level Selection) */
+#define PWR_CR_PLS_0 0x00000020U /*!< Bit 0 */
+#define PWR_CR_PLS_1 0x00000040U /*!< Bit 1 */
+#define PWR_CR_PLS_2 0x00000080U /*!< Bit 2 */
+
+/*!< PVD level configuration */
+#define PWR_CR_PLS_LEV0 0x00000000U /*!< PVD level 0 */
+#define PWR_CR_PLS_LEV1 0x00000020U /*!< PVD level 1 */
+#define PWR_CR_PLS_LEV2 0x00000040U /*!< PVD level 2 */
+#define PWR_CR_PLS_LEV3 0x00000060U /*!< PVD level 3 */
+#define PWR_CR_PLS_LEV4 0x00000080U /*!< PVD level 4 */
+#define PWR_CR_PLS_LEV5 0x000000A0U /*!< PVD level 5 */
+#define PWR_CR_PLS_LEV6 0x000000C0U /*!< PVD level 6 */
+#define PWR_CR_PLS_LEV7 0x000000E0U /*!< PVD level 7 */
+#define PWR_CR_DBP 0x00000100U /*!< Disable Backup Domain write protection */
+#define PWR_CR_FPDS 0x00000200U /*!< Flash power down in Stop mode */
+#define PWR_CR_LPLVDS 0x00000400U /*!< Low-Power Regulator Low Voltage Scaling in Stop mode */
+#define PWR_CR_MRLVDS 0x00000800U /*!< Main regulator Low Voltage Scaling in Stop mode */
+#define PWR_CR_ADCDC1 0x00002000U /*!< Refer to AN4073 on how to use this bit */
+#define PWR_CR_VOS 0x0000C000U /*!< VOS[1:0] bits (Regulator voltage scaling output selection) */
+#define PWR_CR_VOS_0 0x00004000U /*!< Bit 0 */
+#define PWR_CR_VOS_1 0x00008000U /*!< Bit 1 */
+#define PWR_CR_ODEN 0x00010000U /*!< Over Drive enable */
+#define PWR_CR_ODSWEN 0x00020000U /*!< Over Drive switch enabled */
+#define PWR_CR_UDEN 0x000C0000U /*!< Under Drive enable in stop mode */
+#define PWR_CR_UDEN_0 0x00040000U /*!< Bit 0 */
+#define PWR_CR_UDEN_1 0x00080000U /*!< Bit 1 */
+
+/* Legacy define */
+#define PWR_CR_PMODE PWR_CR_VOS
+#define PWR_CR_LPUDS PWR_CR_LPLVDS /*!< Low-Power Regulator in deepsleep under-drive mode */
+#define PWR_CR_MRUDS PWR_CR_MRLVDS /*!< Main regulator in deepsleep under-drive mode */
+
+/******************* Bit definition for PWR_CSR register ********************/
+#define PWR_CSR_WUF 0x00000001U /*!< Wakeup Flag */
+#define PWR_CSR_SBF 0x00000002U /*!< Standby Flag */
+#define PWR_CSR_PVDO 0x00000004U /*!< PVD Output */
+#define PWR_CSR_BRR 0x00000008U /*!< Backup regulator ready */
+#define PWR_CSR_WUPP 0x00000080U /*!< WKUP pin Polarity */
+#define PWR_CSR_EWUP 0x00000100U /*!< Enable WKUP pin */
+#define PWR_CSR_BRE 0x00000200U /*!< Backup regulator enable */
+#define PWR_CSR_VOSRDY 0x00004000U /*!< Regulator voltage scaling output selection ready */
+#define PWR_CSR_ODRDY 0x00010000U /*!< Over Drive generator ready */
+#define PWR_CSR_ODSWRDY 0x00020000U /*!< Over Drive Switch ready */
+#define PWR_CSR_UDSWRDY 0x000C0000U /*!< Under Drive ready */
+
+/* Legacy define */
+#define PWR_CSR_REGRDY PWR_CSR_VOSRDY
+
+/******************************************************************************/
+/* */
+/* QUADSPI */
+/* */
+/******************************************************************************/
+/***************** Bit definition for QUADSPI_CR register *******************/
+#define QUADSPI_CR_EN 0x00000001U /*!< Enable */
+#define QUADSPI_CR_ABORT 0x00000002U /*!< Abort request */
+#define QUADSPI_CR_DMAEN 0x00000004U /*!< DMA Enable */
+#define QUADSPI_CR_TCEN 0x00000008U /*!< Timeout Counter Enable */
+#define QUADSPI_CR_SSHIFT 0x00000010U /*!< SSHIFT Sample Shift */
+#define QUADSPI_CR_DFM 0x00000040U /*!< Dual Flash Mode */
+#define QUADSPI_CR_FSEL 0x00000080U /*!< Flash Select */
+#define QUADSPI_CR_FTHRES 0x00001F00U /*!< FTHRES[3:0] FIFO Level */
+#define QUADSPI_CR_FTHRES_0 0x00000100U /*!< Bit 0 */
+#define QUADSPI_CR_FTHRES_1 0x00000200U /*!< Bit 1 */
+#define QUADSPI_CR_FTHRES_2 0x00000400U /*!< Bit 2 */
+#define QUADSPI_CR_FTHRES_3 0x00000800U /*!< Bit 3 */
+#define QUADSPI_CR_FTHRES_4 0x00001000U /*!< Bit 4 */
+#define QUADSPI_CR_TEIE 0x00010000U /*!< Transfer Error Interrupt Enable */
+#define QUADSPI_CR_TCIE 0x00020000U /*!< Transfer Complete Interrupt Enable */
+#define QUADSPI_CR_FTIE 0x00040000U /*!< FIFO Threshold Interrupt Enable */
+#define QUADSPI_CR_SMIE 0x00080000U /*!< Status Match Interrupt Enable */
+#define QUADSPI_CR_TOIE 0x00100000U /*!< TimeOut Interrupt Enable */
+#define QUADSPI_CR_APMS 0x00400000U /*!< Bit 1 */
+#define QUADSPI_CR_PMM 0x00800000U /*!< Polling Match Mode */
+#define QUADSPI_CR_PRESCALER 0xFF000000U /*!< PRESCALER[7:0] Clock prescaler */
+#define QUADSPI_CR_PRESCALER_0 0x01000000U /*!< Bit 0 */
+#define QUADSPI_CR_PRESCALER_1 0x02000000U /*!< Bit 1 */
+#define QUADSPI_CR_PRESCALER_2 0x04000000U /*!< Bit 2 */
+#define QUADSPI_CR_PRESCALER_3 0x08000000U /*!< Bit 3 */
+#define QUADSPI_CR_PRESCALER_4 0x10000000U /*!< Bit 4 */
+#define QUADSPI_CR_PRESCALER_5 0x20000000U /*!< Bit 5 */
+#define QUADSPI_CR_PRESCALER_6 0x40000000U /*!< Bit 6 */
+#define QUADSPI_CR_PRESCALER_7 0x80000000U /*!< Bit 7 */
+
+/***************** Bit definition for QUADSPI_DCR register ******************/
+#define QUADSPI_DCR_CKMODE 0x00000001U /*!< Mode 0 / Mode 3 */
+#define QUADSPI_DCR_CSHT 0x00000700U /*!< CSHT[2:0]: ChipSelect High Time */
+#define QUADSPI_DCR_CSHT_0 0x00000100U /*!< Bit 0 */
+#define QUADSPI_DCR_CSHT_1 0x00000200U /*!< Bit 1 */
+#define QUADSPI_DCR_CSHT_2 0x00000400U /*!< Bit 2 */
+#define QUADSPI_DCR_FSIZE 0x001F0000U /*!< FSIZE[4:0]: Flash Size */
+#define QUADSPI_DCR_FSIZE_0 0x00010000U /*!< Bit 0 */
+#define QUADSPI_DCR_FSIZE_1 0x00020000U /*!< Bit 1 */
+#define QUADSPI_DCR_FSIZE_2 0x00040000U /*!< Bit 2 */
+#define QUADSPI_DCR_FSIZE_3 0x00080000U /*!< Bit 3 */
+#define QUADSPI_DCR_FSIZE_4 0x00100000U /*!< Bit 4 */
+
+/****************** Bit definition for QUADSPI_SR register *******************/
+#define QUADSPI_SR_TEF 0x00000001U /*!< Transfer Error Flag */
+#define QUADSPI_SR_TCF 0x00000002U /*!< Transfer Complete Flag */
+#define QUADSPI_SR_FTF 0x00000004U /*!< FIFO Threshlod Flag */
+#define QUADSPI_SR_SMF 0x00000008U /*!< Status Match Flag */
+#define QUADSPI_SR_TOF 0x00000010U /*!< Timeout Flag */
+#define QUADSPI_SR_BUSY 0x00000020U /*!< Busy */
+#define QUADSPI_SR_FLEVEL 0x00003F00U /*!< FIFO Threshlod Flag */
+#define QUADSPI_SR_FLEVEL_0 0x00000100U /*!< Bit 0 */
+#define QUADSPI_SR_FLEVEL_1 0x00000200U /*!< Bit 1 */
+#define QUADSPI_SR_FLEVEL_2 0x00000400U /*!< Bit 2 */
+#define QUADSPI_SR_FLEVEL_3 0x00000800U /*!< Bit 3 */
+#define QUADSPI_SR_FLEVEL_4 0x00001000U /*!< Bit 4 */
+#define QUADSPI_SR_FLEVEL_5 0x00002000U /*!< Bit 5 */
+
+/****************** Bit definition for QUADSPI_FCR register ******************/
+#define QUADSPI_FCR_CTEF 0x00000001U /*!< Clear Transfer Error Flag */
+#define QUADSPI_FCR_CTCF 0x00000002U /*!< Clear Transfer Complete Flag */
+#define QUADSPI_FCR_CSMF 0x00000008U /*!< Clear Status Match Flag */
+#define QUADSPI_FCR_CTOF 0x00000010U /*!< Clear Timeout Flag */
+
+/****************** Bit definition for QUADSPI_DLR register ******************/
+#define QUADSPI_DLR_DL 0xFFFFFFFFU /*!< DL[31:0]: Data Length */
+
+/****************** Bit definition for QUADSPI_CCR register ******************/
+#define QUADSPI_CCR_INSTRUCTION 0x000000FFU /*!< INSTRUCTION[7:0]: Instruction */
+#define QUADSPI_CCR_INSTRUCTION_0 0x00000001U /*!< Bit 0 */
+#define QUADSPI_CCR_INSTRUCTION_1 0x00000002U /*!< Bit 1 */
+#define QUADSPI_CCR_INSTRUCTION_2 0x00000004U /*!< Bit 2 */
+#define QUADSPI_CCR_INSTRUCTION_3 0x00000008U /*!< Bit 3 */
+#define QUADSPI_CCR_INSTRUCTION_4 0x00000010U /*!< Bit 4 */
+#define QUADSPI_CCR_INSTRUCTION_5 0x00000020U /*!< Bit 5 */
+#define QUADSPI_CCR_INSTRUCTION_6 0x00000040U /*!< Bit 6 */
+#define QUADSPI_CCR_INSTRUCTION_7 0x00000080U /*!< Bit 7 */
+#define QUADSPI_CCR_IMODE 0x00000300U /*!< IMODE[1:0]: Instruction Mode */
+#define QUADSPI_CCR_IMODE_0 0x00000100U /*!< Bit 0 */
+#define QUADSPI_CCR_IMODE_1 0x00000200U /*!< Bit 1 */
+#define QUADSPI_CCR_ADMODE 0x00000C00U /*!< ADMODE[1:0]: Address Mode */
+#define QUADSPI_CCR_ADMODE_0 0x00000400U /*!< Bit 0 */
+#define QUADSPI_CCR_ADMODE_1 0x00000800U /*!< Bit 1 */
+#define QUADSPI_CCR_ADSIZE 0x00003000U /*!< ADSIZE[1:0]: Address Size */
+#define QUADSPI_CCR_ADSIZE_0 0x00001000U /*!< Bit 0 */
+#define QUADSPI_CCR_ADSIZE_1 0x00002000U /*!< Bit 1 */
+#define QUADSPI_CCR_ABMODE 0x0000C000U /*!< ABMODE[1:0]: Alternate Bytes Mode */
+#define QUADSPI_CCR_ABMODE_0 0x00004000U /*!< Bit 0 */
+#define QUADSPI_CCR_ABMODE_1 0x00008000U /*!< Bit 1 */
+#define QUADSPI_CCR_ABSIZE 0x00030000U /*!< ABSIZE[1:0]: Instruction Mode */
+#define QUADSPI_CCR_ABSIZE_0 0x00010000U /*!< Bit 0 */
+#define QUADSPI_CCR_ABSIZE_1 0x00020000U /*!< Bit 1 */
+#define QUADSPI_CCR_DCYC 0x007C0000U /*!< DCYC[4:0]: Dummy Cycles */
+#define QUADSPI_CCR_DCYC_0 0x00040000U /*!< Bit 0 */
+#define QUADSPI_CCR_DCYC_1 0x00080000U /*!< Bit 1 */
+#define QUADSPI_CCR_DCYC_2 0x00100000U /*!< Bit 2 */
+#define QUADSPI_CCR_DCYC_3 0x00200000U /*!< Bit 3 */
+#define QUADSPI_CCR_DCYC_4 0x00400000U /*!< Bit 4 */
+#define QUADSPI_CCR_DMODE 0x03000000U /*!< DMODE[1:0]: Data Mode */
+#define QUADSPI_CCR_DMODE_0 0x01000000U /*!< Bit 0 */
+#define QUADSPI_CCR_DMODE_1 0x02000000U /*!< Bit 1 */
+#define QUADSPI_CCR_FMODE 0x0C000000U /*!< FMODE[1:0]: Functional Mode */
+#define QUADSPI_CCR_FMODE_0 0x04000000U /*!< Bit 0 */
+#define QUADSPI_CCR_FMODE_1 0x08000000U /*!< Bit 1 */
+#define QUADSPI_CCR_SIOO 0x10000000U /*!< SIOO: Send Instruction Only Once Mode */
+#define QUADSPI_CCR_DHHC 0x40000000U /*!< DHHC: Delay Half Hclk Cycle */
+#define QUADSPI_CCR_DDRM 0x80000000U /*!< DDRM: Double Data Rate Mode */
+/****************** Bit definition for QUADSPI_AR register *******************/
+#define QUADSPI_AR_ADDRESS 0xFFFFFFFFU /*!< ADDRESS[31:0]: Address */
+
+/****************** Bit definition for QUADSPI_ABR register ******************/
+#define QUADSPI_ABR_ALTERNATE 0xFFFFFFFFU /*!< ALTERNATE[31:0]: Alternate Bytes */
+
+/****************** Bit definition for QUADSPI_DR register *******************/
+#define QUADSPI_DR_DATA 0xFFFFFFFFU /*!< DATA[31:0]: Data */
+
+/****************** Bit definition for QUADSPI_PSMKR register ****************/
+#define QUADSPI_PSMKR_MASK 0xFFFFFFFFU /*!< MASK[31:0]: Status Mask */
+
+/****************** Bit definition for QUADSPI_PSMAR register ****************/
+#define QUADSPI_PSMAR_MATCH 0xFFFFFFFFU /*!< MATCH[31:0]: Status Match */
+
+/****************** Bit definition for QUADSPI_PIR register *****************/
+#define QUADSPI_PIR_INTERVAL 0x0000FFFFU /*!< INTERVAL[15:0]: Polling Interval */
+
+/****************** Bit definition for QUADSPI_LPTR register *****************/
+#define QUADSPI_LPTR_TIMEOUT 0x0000FFFFU /*!< TIMEOUT[15:0]: Timeout period */
+
+/******************************************************************************/
+/* */
+/* Reset and Clock Control */
+/* */
+/******************************************************************************/
+/******************** Bit definition for RCC_CR register ********************/
+#define RCC_CR_HSION 0x00000001U
+#define RCC_CR_HSIRDY 0x00000002U
+
+#define RCC_CR_HSITRIM 0x000000F8U
+#define RCC_CR_HSITRIM_0 0x00000008U/*!<Bit 0 */
+#define RCC_CR_HSITRIM_1 0x00000010U/*!<Bit 1 */
+#define RCC_CR_HSITRIM_2 0x00000020U/*!<Bit 2 */
+#define RCC_CR_HSITRIM_3 0x00000040U/*!<Bit 3 */
+#define RCC_CR_HSITRIM_4 0x00000080U/*!<Bit 4 */
+
+#define RCC_CR_HSICAL 0x0000FF00U
+#define RCC_CR_HSICAL_0 0x00000100U/*!<Bit 0 */
+#define RCC_CR_HSICAL_1 0x00000200U/*!<Bit 1 */
+#define RCC_CR_HSICAL_2 0x00000400U/*!<Bit 2 */
+#define RCC_CR_HSICAL_3 0x00000800U/*!<Bit 3 */
+#define RCC_CR_HSICAL_4 0x00001000U/*!<Bit 4 */
+#define RCC_CR_HSICAL_5 0x00002000U/*!<Bit 5 */
+#define RCC_CR_HSICAL_6 0x00004000U/*!<Bit 6 */
+#define RCC_CR_HSICAL_7 0x00008000U/*!<Bit 7 */
+
+#define RCC_CR_HSEON 0x00010000U
+#define RCC_CR_HSERDY 0x00020000U
+#define RCC_CR_HSEBYP 0x00040000U
+#define RCC_CR_CSSON 0x00080000U
+#define RCC_CR_PLLON 0x01000000U
+#define RCC_CR_PLLRDY 0x02000000U
+#define RCC_CR_PLLI2SON 0x04000000U
+#define RCC_CR_PLLI2SRDY 0x08000000U
+#define RCC_CR_PLLSAION 0x10000000U
+#define RCC_CR_PLLSAIRDY 0x20000000U
+
+/******************** Bit definition for RCC_PLLCFGR register ***************/
+#define RCC_PLLCFGR_PLLM 0x0000003FU
+#define RCC_PLLCFGR_PLLM_0 0x00000001U
+#define RCC_PLLCFGR_PLLM_1 0x00000002U
+#define RCC_PLLCFGR_PLLM_2 0x00000004U
+#define RCC_PLLCFGR_PLLM_3 0x00000008U
+#define RCC_PLLCFGR_PLLM_4 0x00000010U
+#define RCC_PLLCFGR_PLLM_5 0x00000020U
+
+#define RCC_PLLCFGR_PLLN 0x00007FC0U
+#define RCC_PLLCFGR_PLLN_0 0x00000040U
+#define RCC_PLLCFGR_PLLN_1 0x00000080U
+#define RCC_PLLCFGR_PLLN_2 0x00000100U
+#define RCC_PLLCFGR_PLLN_3 0x00000200U
+#define RCC_PLLCFGR_PLLN_4 0x00000400U
+#define RCC_PLLCFGR_PLLN_5 0x00000800U
+#define RCC_PLLCFGR_PLLN_6 0x00001000U
+#define RCC_PLLCFGR_PLLN_7 0x00002000U
+#define RCC_PLLCFGR_PLLN_8 0x00004000U
+
+#define RCC_PLLCFGR_PLLP 0x00030000U
+#define RCC_PLLCFGR_PLLP_0 0x00010000U
+#define RCC_PLLCFGR_PLLP_1 0x00020000U
+
+#define RCC_PLLCFGR_PLLSRC 0x00400000U
+#define RCC_PLLCFGR_PLLSRC_HSE 0x00400000U
+#define RCC_PLLCFGR_PLLSRC_HSI 0x00000000U
+
+#define RCC_PLLCFGR_PLLQ 0x0F000000U
+#define RCC_PLLCFGR_PLLQ_0 0x01000000U
+#define RCC_PLLCFGR_PLLQ_1 0x02000000U
+#define RCC_PLLCFGR_PLLQ_2 0x04000000U
+#define RCC_PLLCFGR_PLLQ_3 0x08000000U
+
+#define RCC_PLLCFGR_PLLR 0x70000000U
+#define RCC_PLLCFGR_PLLR_0 0x10000000U
+#define RCC_PLLCFGR_PLLR_1 0x20000000U
+#define RCC_PLLCFGR_PLLR_2 0x40000000U
+
+
+/******************** Bit definition for RCC_CFGR register ******************/
+/*!< SW configuration */
+#define RCC_CFGR_SW 0x00000003U /*!< SW[1:0] bits (System clock Switch) */
+#define RCC_CFGR_SW_0 0x00000001U /*!< Bit 0 */
+#define RCC_CFGR_SW_1 0x00000002U /*!< Bit 1 */
+
+#define RCC_CFGR_SW_HSI 0x00000000U /*!< HSI selected as system clock */
+#define RCC_CFGR_SW_HSE 0x00000001U /*!< HSE selected as system clock */
+#define RCC_CFGR_SW_PLL 0x00000002U /*!< PLL selected as system clock */
+
+/*!< SWS configuration */
+#define RCC_CFGR_SWS 0x0000000CU /*!< SWS[1:0] bits (System Clock Switch Status) */
+#define RCC_CFGR_SWS_0 0x00000004U /*!< Bit 0 */
+#define RCC_CFGR_SWS_1 0x00000008U /*!< Bit 1 */
+
+#define RCC_CFGR_SWS_HSI 0x00000000U /*!< HSI oscillator used as system clock */
+#define RCC_CFGR_SWS_HSE 0x00000004U /*!< HSE oscillator used as system clock */
+#define RCC_CFGR_SWS_PLL 0x00000008U /*!< PLL used as system clock */
+
+/*!< HPRE configuration */
+#define RCC_CFGR_HPRE 0x000000F0U /*!< HPRE[3:0] bits (AHB prescaler) */
+#define RCC_CFGR_HPRE_0 0x00000010U /*!< Bit 0 */
+#define RCC_CFGR_HPRE_1 0x00000020U /*!< Bit 1 */
+#define RCC_CFGR_HPRE_2 0x00000040U /*!< Bit 2 */
+#define RCC_CFGR_HPRE_3 0x00000080U /*!< Bit 3 */
+
+#define RCC_CFGR_HPRE_DIV1 0x00000000U /*!< SYSCLK not divided */
+#define RCC_CFGR_HPRE_DIV2 0x00000080U /*!< SYSCLK divided by 2 */
+#define RCC_CFGR_HPRE_DIV4 0x00000090U /*!< SYSCLK divided by 4 */
+#define RCC_CFGR_HPRE_DIV8 0x000000A0U /*!< SYSCLK divided by 8 */
+#define RCC_CFGR_HPRE_DIV16 0x000000B0U /*!< SYSCLK divided by 16 */
+#define RCC_CFGR_HPRE_DIV64 0x000000C0U /*!< SYSCLK divided by 64 */
+#define RCC_CFGR_HPRE_DIV128 0x000000D0U /*!< SYSCLK divided by 128 */
+#define RCC_CFGR_HPRE_DIV256 0x000000E0U /*!< SYSCLK divided by 256 */
+#define RCC_CFGR_HPRE_DIV512 0x000000F0U /*!< SYSCLK divided by 512 */
+
+/*!< PPRE1 configuration */
+#define RCC_CFGR_PPRE1 0x00001C00U /*!< PRE1[2:0] bits (APB1 prescaler) */
+#define RCC_CFGR_PPRE1_0 0x00000400U /*!< Bit 0 */
+#define RCC_CFGR_PPRE1_1 0x00000800U /*!< Bit 1 */
+#define RCC_CFGR_PPRE1_2 0x00001000U /*!< Bit 2 */
+
+#define RCC_CFGR_PPRE1_DIV1 0x00000000U /*!< HCLK not divided */
+#define RCC_CFGR_PPRE1_DIV2 0x00001000U /*!< HCLK divided by 2 */
+#define RCC_CFGR_PPRE1_DIV4 0x00001400U /*!< HCLK divided by 4 */
+#define RCC_CFGR_PPRE1_DIV8 0x00001800U /*!< HCLK divided by 8 */
+#define RCC_CFGR_PPRE1_DIV16 0x00001C00U /*!< HCLK divided by 16 */
+
+/*!< PPRE2 configuration */
+#define RCC_CFGR_PPRE2 0x0000E000U /*!< PRE2[2:0] bits (APB2 prescaler) */
+#define RCC_CFGR_PPRE2_0 0x00002000U /*!< Bit 0 */
+#define RCC_CFGR_PPRE2_1 0x00004000U /*!< Bit 1 */
+#define RCC_CFGR_PPRE2_2 0x00008000U /*!< Bit 2 */
+
+#define RCC_CFGR_PPRE2_DIV1 0x00000000U /*!< HCLK not divided */
+#define RCC_CFGR_PPRE2_DIV2 0x00008000U /*!< HCLK divided by 2 */
+#define RCC_CFGR_PPRE2_DIV4 0x0000A000U /*!< HCLK divided by 4 */
+#define RCC_CFGR_PPRE2_DIV8 0x0000C000U /*!< HCLK divided by 8 */
+#define RCC_CFGR_PPRE2_DIV16 0x0000E000U /*!< HCLK divided by 16 */
+
+/*!< RTCPRE configuration */
+#define RCC_CFGR_RTCPRE 0x001F0000U
+#define RCC_CFGR_RTCPRE_0 0x00010000U
+#define RCC_CFGR_RTCPRE_1 0x00020000U
+#define RCC_CFGR_RTCPRE_2 0x00040000U
+#define RCC_CFGR_RTCPRE_3 0x00080000U
+#define RCC_CFGR_RTCPRE_4 0x00100000U
+
+/*!< MCO1 configuration */
+#define RCC_CFGR_MCO1 0x00600000U
+#define RCC_CFGR_MCO1_0 0x00200000U
+#define RCC_CFGR_MCO1_1 0x00400000U
+
+#define RCC_CFGR_I2SSRC 0x00800000U
+
+#define RCC_CFGR_MCO1PRE 0x07000000U
+#define RCC_CFGR_MCO1PRE_0 0x01000000U
+#define RCC_CFGR_MCO1PRE_1 0x02000000U
+#define RCC_CFGR_MCO1PRE_2 0x04000000U
+
+#define RCC_CFGR_MCO2PRE 0x38000000U
+#define RCC_CFGR_MCO2PRE_0 0x08000000U
+#define RCC_CFGR_MCO2PRE_1 0x10000000U
+#define RCC_CFGR_MCO2PRE_2 0x20000000U
+
+#define RCC_CFGR_MCO2 0xC0000000U
+#define RCC_CFGR_MCO2_0 0x40000000U
+#define RCC_CFGR_MCO2_1 0x80000000U
+
+/******************** Bit definition for RCC_CIR register *******************/
+#define RCC_CIR_LSIRDYF 0x00000001U
+#define RCC_CIR_LSERDYF 0x00000002U
+#define RCC_CIR_HSIRDYF 0x00000004U
+#define RCC_CIR_HSERDYF 0x00000008U
+#define RCC_CIR_PLLRDYF 0x00000010U
+#define RCC_CIR_PLLI2SRDYF 0x00000020U
+#define RCC_CIR_PLLSAIRDYF 0x00000040U
+#define RCC_CIR_CSSF 0x00000080U
+#define RCC_CIR_LSIRDYIE 0x00000100U
+#define RCC_CIR_LSERDYIE 0x00000200U
+#define RCC_CIR_HSIRDYIE 0x00000400U
+#define RCC_CIR_HSERDYIE 0x00000800U
+#define RCC_CIR_PLLRDYIE 0x00001000U
+#define RCC_CIR_PLLI2SRDYIE 0x00002000U
+#define RCC_CIR_PLLSAIRDYIE 0x00004000U
+#define RCC_CIR_LSIRDYC 0x00010000U
+#define RCC_CIR_LSERDYC 0x00020000U
+#define RCC_CIR_HSIRDYC 0x00040000U
+#define RCC_CIR_HSERDYC 0x00080000U
+#define RCC_CIR_PLLRDYC 0x00100000U
+#define RCC_CIR_PLLI2SRDYC 0x00200000U
+#define RCC_CIR_PLLSAIRDYC 0x00400000U
+#define RCC_CIR_CSSC 0x00800000U
+
+/******************** Bit definition for RCC_AHB1RSTR register **************/
+#define RCC_AHB1RSTR_GPIOARST 0x00000001U
+#define RCC_AHB1RSTR_GPIOBRST 0x00000002U
+#define RCC_AHB1RSTR_GPIOCRST 0x00000004U
+#define RCC_AHB1RSTR_GPIODRST 0x00000008U
+#define RCC_AHB1RSTR_GPIOERST 0x00000010U
+#define RCC_AHB1RSTR_GPIOFRST 0x00000020U
+#define RCC_AHB1RSTR_GPIOGRST 0x00000040U
+#define RCC_AHB1RSTR_GPIOHRST 0x00000080U
+#define RCC_AHB1RSTR_GPIOIRST 0x00000100U
+#define RCC_AHB1RSTR_GPIOJRST 0x00000200U
+#define RCC_AHB1RSTR_GPIOKRST 0x00000400U
+#define RCC_AHB1RSTR_CRCRST 0x00001000U
+#define RCC_AHB1RSTR_DMA1RST 0x00200000U
+#define RCC_AHB1RSTR_DMA2RST 0x00400000U
+#define RCC_AHB1RSTR_DMA2DRST 0x00800000U
+#define RCC_AHB1RSTR_ETHMACRST 0x02000000U
+#define RCC_AHB1RSTR_OTGHRST 0x20000000U
+
+/******************** Bit definition for RCC_AHB2RSTR register **************/
+#define RCC_AHB2RSTR_DCMIRST 0x00000001U
+#define RCC_AHB2RSTR_CRYPRST 0x00000010U
+#define RCC_AHB2RSTR_HASHRST 0x00000020U
+ /* maintained for legacy purpose */
+#define RCC_AHB2RSTR_HSAHRST RCC_AHB2RSTR_HASHRST
+#define RCC_AHB2RSTR_RNGRST 0x00000040U
+#define RCC_AHB2RSTR_OTGFSRST 0x00000080U
+
+/******************** Bit definition for RCC_AHB3RSTR register **************/
+#define RCC_AHB3RSTR_FMCRST 0x00000001U
+#define RCC_AHB3RSTR_QSPIRST 0x00000002U
+
+/******************** Bit definition for RCC_APB1RSTR register **************/
+#define RCC_APB1RSTR_TIM2RST 0x00000001U
+#define RCC_APB1RSTR_TIM3RST 0x00000002U
+#define RCC_APB1RSTR_TIM4RST 0x00000004U
+#define RCC_APB1RSTR_TIM5RST 0x00000008U
+#define RCC_APB1RSTR_TIM6RST 0x00000010U
+#define RCC_APB1RSTR_TIM7RST 0x00000020U
+#define RCC_APB1RSTR_TIM12RST 0x00000040U
+#define RCC_APB1RSTR_TIM13RST 0x00000080U
+#define RCC_APB1RSTR_TIM14RST 0x00000100U
+#define RCC_APB1RSTR_WWDGRST 0x00000800U
+#define RCC_APB1RSTR_SPI2RST 0x00004000U
+#define RCC_APB1RSTR_SPI3RST 0x00008000U
+#define RCC_APB1RSTR_USART2RST 0x00020000U
+#define RCC_APB1RSTR_USART3RST 0x00040000U
+#define RCC_APB1RSTR_UART4RST 0x00080000U
+#define RCC_APB1RSTR_UART5RST 0x00100000U
+#define RCC_APB1RSTR_I2C1RST 0x00200000U
+#define RCC_APB1RSTR_I2C2RST 0x00400000U
+#define RCC_APB1RSTR_I2C3RST 0x00800000U
+#define RCC_APB1RSTR_CAN1RST 0x02000000U
+#define RCC_APB1RSTR_CAN2RST 0x04000000U
+#define RCC_APB1RSTR_PWRRST 0x10000000U
+#define RCC_APB1RSTR_DACRST 0x20000000U
+#define RCC_APB1RSTR_UART7RST 0x40000000U
+#define RCC_APB1RSTR_UART8RST 0x80000000U
+
+/******************** Bit definition for RCC_APB2RSTR register **************/
+#define RCC_APB2RSTR_TIM1RST 0x00000001U
+#define RCC_APB2RSTR_TIM8RST 0x00000002U
+#define RCC_APB2RSTR_USART1RST 0x00000010U
+#define RCC_APB2RSTR_USART6RST 0x00000020U
+#define RCC_APB2RSTR_ADCRST 0x00000100U
+#define RCC_APB2RSTR_SDIORST 0x00000800U
+#define RCC_APB2RSTR_SPI1RST 0x00001000U
+#define RCC_APB2RSTR_SPI4RST 0x00002000U
+#define RCC_APB2RSTR_SYSCFGRST 0x00004000U
+#define RCC_APB2RSTR_TIM9RST 0x00010000U
+#define RCC_APB2RSTR_TIM10RST 0x00020000U
+#define RCC_APB2RSTR_TIM11RST 0x00040000U
+#define RCC_APB2RSTR_SPI5RST 0x00100000U
+#define RCC_APB2RSTR_SPI6RST 0x00200000U
+#define RCC_APB2RSTR_SAI1RST 0x00400000U
+#define RCC_APB2RSTR_LTDCRST 0x04000000U
+#define RCC_APB2RSTR_DSIRST 0x08000000U
+
+/* Old SPI1RST bit definition, maintained for legacy purpose */
+#define RCC_APB2RSTR_SPI1 RCC_APB2RSTR_SPI1RST
+
+/******************** Bit definition for RCC_AHB1ENR register ***************/
+#define RCC_AHB1ENR_GPIOAEN 0x00000001U
+#define RCC_AHB1ENR_GPIOBEN 0x00000002U
+#define RCC_AHB1ENR_GPIOCEN 0x00000004U
+#define RCC_AHB1ENR_GPIODEN 0x00000008U
+#define RCC_AHB1ENR_GPIOEEN 0x00000010U
+#define RCC_AHB1ENR_GPIOFEN 0x00000020U
+#define RCC_AHB1ENR_GPIOGEN 0x00000040U
+#define RCC_AHB1ENR_GPIOHEN 0x00000080U
+#define RCC_AHB1ENR_GPIOIEN 0x00000100U
+#define RCC_AHB1ENR_GPIOJEN 0x00000200U
+#define RCC_AHB1ENR_GPIOKEN 0x00000400U
+
+#define RCC_AHB1ENR_CRCEN 0x00001000U
+#define RCC_AHB1ENR_BKPSRAMEN 0x00040000U
+#define RCC_AHB1ENR_CCMDATARAMEN 0x00100000U
+#define RCC_AHB1ENR_DMA1EN 0x00200000U
+#define RCC_AHB1ENR_DMA2EN 0x00400000U
+#define RCC_AHB1ENR_DMA2DEN 0x00800000U
+
+#define RCC_AHB1ENR_ETHMACEN 0x02000000U
+#define RCC_AHB1ENR_ETHMACTXEN 0x04000000U
+#define RCC_AHB1ENR_ETHMACRXEN 0x08000000U
+#define RCC_AHB1ENR_ETHMACPTPEN 0x10000000U
+#define RCC_AHB1ENR_OTGHSEN 0x20000000U
+#define RCC_AHB1ENR_OTGHSULPIEN 0x40000000U
+
+/******************** Bit definition for RCC_AHB2ENR register ***************/
+#define RCC_AHB2ENR_DCMIEN 0x00000001U
+#define RCC_AHB2ENR_CRYPEN 0x00000010U
+#define RCC_AHB2ENR_HASHEN 0x00000020U
+#define RCC_AHB2ENR_RNGEN 0x00000040U
+#define RCC_AHB2ENR_OTGFSEN 0x00000080U
+
+/******************** Bit definition for RCC_AHB3ENR register ***************/
+#define RCC_AHB3ENR_FMCEN 0x00000001U
+#define RCC_AHB3ENR_QSPIEN 0x00000002U
+
+/******************** Bit definition for RCC_APB1ENR register ***************/
+#define RCC_APB1ENR_TIM2EN 0x00000001U
+#define RCC_APB1ENR_TIM3EN 0x00000002U
+#define RCC_APB1ENR_TIM4EN 0x00000004U
+#define RCC_APB1ENR_TIM5EN 0x00000008U
+#define RCC_APB1ENR_TIM6EN 0x00000010U
+#define RCC_APB1ENR_TIM7EN 0x00000020U
+#define RCC_APB1ENR_TIM12EN 0x00000040U
+#define RCC_APB1ENR_TIM13EN 0x00000080U
+#define RCC_APB1ENR_TIM14EN 0x00000100U
+#define RCC_APB1ENR_WWDGEN 0x00000800U
+#define RCC_APB1ENR_SPI2EN 0x00004000U
+#define RCC_APB1ENR_SPI3EN 0x00008000U
+#define RCC_APB1ENR_USART2EN 0x00020000U
+#define RCC_APB1ENR_USART3EN 0x00040000U
+#define RCC_APB1ENR_UART4EN 0x00080000U
+#define RCC_APB1ENR_UART5EN 0x00100000U
+#define RCC_APB1ENR_I2C1EN 0x00200000U
+#define RCC_APB1ENR_I2C2EN 0x00400000U
+#define RCC_APB1ENR_I2C3EN 0x00800000U
+#define RCC_APB1ENR_CAN1EN 0x02000000U
+#define RCC_APB1ENR_CAN2EN 0x04000000U
+#define RCC_APB1ENR_PWREN 0x10000000U
+#define RCC_APB1ENR_DACEN 0x20000000U
+#define RCC_APB1ENR_UART7EN 0x40000000U
+#define RCC_APB1ENR_UART8EN 0x80000000U
+
+/******************** Bit definition for RCC_APB2ENR register ***************/
+#define RCC_APB2ENR_TIM1EN 0x00000001U
+#define RCC_APB2ENR_TIM8EN 0x00000002U
+#define RCC_APB2ENR_USART1EN 0x00000010U
+#define RCC_APB2ENR_USART6EN 0x00000020U
+#define RCC_APB2ENR_ADC1EN 0x00000100U
+#define RCC_APB2ENR_ADC2EN 0x00000200U
+#define RCC_APB2ENR_ADC3EN 0x00000400U
+#define RCC_APB2ENR_SDIOEN 0x00000800U
+#define RCC_APB2ENR_SPI1EN 0x00001000U
+#define RCC_APB2ENR_SPI4EN 0x00002000U
+#define RCC_APB2ENR_SYSCFGEN 0x00004000U
+#define RCC_APB2ENR_TIM9EN 0x00010000U
+#define RCC_APB2ENR_TIM10EN 0x00020000U
+#define RCC_APB2ENR_TIM11EN 0x00040000U
+#define RCC_APB2ENR_SPI5EN 0x00100000U
+#define RCC_APB2ENR_SPI6EN 0x00200000U
+#define RCC_APB2ENR_SAI1EN 0x00400000U
+#define RCC_APB2ENR_LTDCEN 0x04000000U
+#define RCC_APB2ENR_DSIEN 0x08000000U
+
+/******************** Bit definition for RCC_AHB1LPENR register *************/
+#define RCC_AHB1LPENR_GPIOALPEN 0x00000001U
+#define RCC_AHB1LPENR_GPIOBLPEN 0x00000002U
+#define RCC_AHB1LPENR_GPIOCLPEN 0x00000004U
+#define RCC_AHB1LPENR_GPIODLPEN 0x00000008U
+#define RCC_AHB1LPENR_GPIOELPEN 0x00000010U
+#define RCC_AHB1LPENR_GPIOFLPEN 0x00000020U
+#define RCC_AHB1LPENR_GPIOGLPEN 0x00000040U
+#define RCC_AHB1LPENR_GPIOHLPEN 0x00000080U
+#define RCC_AHB1LPENR_GPIOILPEN 0x00000100U
+#define RCC_AHB1LPENR_GPIOJLPEN 0x00000200U
+#define RCC_AHB1LPENR_GPIOKLPEN 0x00000400U
+
+#define RCC_AHB1LPENR_CRCLPEN 0x00001000U
+#define RCC_AHB1LPENR_FLITFLPEN 0x00008000U
+#define RCC_AHB1LPENR_SRAM1LPEN 0x00010000U
+#define RCC_AHB1LPENR_SRAM2LPEN 0x00020000U
+#define RCC_AHB1LPENR_BKPSRAMLPEN 0x00040000U
+#define RCC_AHB1LPENR_SRAM3LPEN 0x00080000U
+#define RCC_AHB1LPENR_DMA1LPEN 0x00200000U
+#define RCC_AHB1LPENR_DMA2LPEN 0x00400000U
+#define RCC_AHB1LPENR_DMA2DLPEN 0x00800000U
+
+#define RCC_AHB1LPENR_ETHMACLPEN 0x02000000U
+#define RCC_AHB1LPENR_ETHMACTXLPEN 0x04000000U
+#define RCC_AHB1LPENR_ETHMACRXLPEN 0x08000000U
+#define RCC_AHB1LPENR_ETHMACPTPLPEN 0x10000000U
+#define RCC_AHB1LPENR_OTGHSLPEN 0x20000000U
+#define RCC_AHB1LPENR_OTGHSULPILPEN 0x40000000U
+
+/******************** Bit definition for RCC_AHB2LPENR register *************/
+#define RCC_AHB2LPENR_DCMILPEN 0x00000001U
+#define RCC_AHB2LPENR_CRYPLPEN 0x00000010U
+#define RCC_AHB2LPENR_HASHLPEN 0x00000020U
+#define RCC_AHB2LPENR_RNGLPEN 0x00000040U
+#define RCC_AHB2LPENR_OTGFSLPEN 0x00000080U
+
+/******************** Bit definition for RCC_AHB3LPENR register *************/
+#define RCC_AHB3LPENR_FMCLPEN 0x00000001U
+#define RCC_AHB3LPENR_QSPILPEN 0x00000002U
+
+/******************** Bit definition for RCC_APB1LPENR register *************/
+#define RCC_APB1LPENR_TIM2LPEN 0x00000001U
+#define RCC_APB1LPENR_TIM3LPEN 0x00000002U
+#define RCC_APB1LPENR_TIM4LPEN 0x00000004U
+#define RCC_APB1LPENR_TIM5LPEN 0x00000008U
+#define RCC_APB1LPENR_TIM6LPEN 0x00000010U
+#define RCC_APB1LPENR_TIM7LPEN 0x00000020U
+#define RCC_APB1LPENR_TIM12LPEN 0x00000040U
+#define RCC_APB1LPENR_TIM13LPEN 0x00000080U
+#define RCC_APB1LPENR_TIM14LPEN 0x00000100U
+#define RCC_APB1LPENR_WWDGLPEN 0x00000800U
+#define RCC_APB1LPENR_SPI2LPEN 0x00004000U
+#define RCC_APB1LPENR_SPI3LPEN 0x00008000U
+#define RCC_APB1LPENR_USART2LPEN 0x00020000U
+#define RCC_APB1LPENR_USART3LPEN 0x00040000U
+#define RCC_APB1LPENR_UART4LPEN 0x00080000U
+#define RCC_APB1LPENR_UART5LPEN 0x00100000U
+#define RCC_APB1LPENR_I2C1LPEN 0x00200000U
+#define RCC_APB1LPENR_I2C2LPEN 0x00400000U
+#define RCC_APB1LPENR_I2C3LPEN 0x00800000U
+#define RCC_APB1LPENR_CAN1LPEN 0x02000000U
+#define RCC_APB1LPENR_CAN2LPEN 0x04000000U
+#define RCC_APB1LPENR_PWRLPEN 0x10000000U
+#define RCC_APB1LPENR_DACLPEN 0x20000000U
+#define RCC_APB1LPENR_UART7LPEN 0x40000000U
+#define RCC_APB1LPENR_UART8LPEN 0x80000000U
+
+/******************** Bit definition for RCC_APB2LPENR register *************/
+#define RCC_APB2LPENR_TIM1LPEN 0x00000001U
+#define RCC_APB2LPENR_TIM8LPEN 0x00000002U
+#define RCC_APB2LPENR_USART1LPEN 0x00000010U
+#define RCC_APB2LPENR_USART6LPEN 0x00000020U
+#define RCC_APB2LPENR_ADC1LPEN 0x00000100U
+#define RCC_APB2LPENR_ADC2LPEN 0x00000200U
+#define RCC_APB2LPENR_ADC3LPEN 0x00000400U
+#define RCC_APB2LPENR_SDIOLPEN 0x00000800U
+#define RCC_APB2LPENR_SPI1LPEN 0x00001000U
+#define RCC_APB2LPENR_SPI4LPEN 0x00002000U
+#define RCC_APB2LPENR_SYSCFGLPEN 0x00004000U
+#define RCC_APB2LPENR_TIM9LPEN 0x00010000U
+#define RCC_APB2LPENR_TIM10LPEN 0x00020000U
+#define RCC_APB2LPENR_TIM11LPEN 0x00040000U
+#define RCC_APB2LPENR_SPI5LPEN 0x00100000U
+#define RCC_APB2LPENR_SPI6LPEN 0x00200000U
+#define RCC_APB2LPENR_SAI1LPEN 0x00400000U
+#define RCC_APB2LPENR_LTDCLPEN 0x04000000U
+#define RCC_APB2LPENR_DSILPEN 0x08000000U
+
+/******************** Bit definition for RCC_BDCR register ******************/
+#define RCC_BDCR_LSEON 0x00000001U
+#define RCC_BDCR_LSERDY 0x00000002U
+#define RCC_BDCR_LSEBYP 0x00000004U
+#define RCC_BDCR_LSEMOD 0x00000008U
+
+#define RCC_BDCR_RTCSEL 0x00000300U
+#define RCC_BDCR_RTCSEL_0 0x00000100U
+#define RCC_BDCR_RTCSEL_1 0x00000200U
+
+#define RCC_BDCR_RTCEN 0x00008000U
+#define RCC_BDCR_BDRST 0x00010000U
+
+/******************** Bit definition for RCC_CSR register *******************/
+#define RCC_CSR_LSION 0x00000001U
+#define RCC_CSR_LSIRDY 0x00000002U
+#define RCC_CSR_RMVF 0x01000000U
+#define RCC_CSR_BORRSTF 0x02000000U
+#define RCC_CSR_PADRSTF 0x04000000U
+#define RCC_CSR_PORRSTF 0x08000000U
+#define RCC_CSR_SFTRSTF 0x10000000U
+#define RCC_CSR_WDGRSTF 0x20000000U
+#define RCC_CSR_WWDGRSTF 0x40000000U
+#define RCC_CSR_LPWRRSTF 0x80000000U
+
+/******************** Bit definition for RCC_SSCGR register *****************/
+#define RCC_SSCGR_MODPER 0x00001FFFU
+#define RCC_SSCGR_INCSTEP 0x0FFFE000U
+#define RCC_SSCGR_SPREADSEL 0x40000000U
+#define RCC_SSCGR_SSCGEN 0x80000000U
+
+/******************** Bit definition for RCC_PLLI2SCFGR register ************/
+#define RCC_PLLI2SCFGR_PLLI2SN 0x00007FC0U
+#define RCC_PLLI2SCFGR_PLLI2SN_0 0x00000040U
+#define RCC_PLLI2SCFGR_PLLI2SN_1 0x00000080U
+#define RCC_PLLI2SCFGR_PLLI2SN_2 0x00000100U
+#define RCC_PLLI2SCFGR_PLLI2SN_3 0x00000200U
+#define RCC_PLLI2SCFGR_PLLI2SN_4 0x00000400U
+#define RCC_PLLI2SCFGR_PLLI2SN_5 0x00000800U
+#define RCC_PLLI2SCFGR_PLLI2SN_6 0x00001000U
+#define RCC_PLLI2SCFGR_PLLI2SN_7 0x00002000U
+#define RCC_PLLI2SCFGR_PLLI2SN_8 0x00004000U
+
+#define RCC_PLLI2SCFGR_PLLI2SQ 0x0F000000U
+#define RCC_PLLI2SCFGR_PLLI2SQ_0 0x01000000U
+#define RCC_PLLI2SCFGR_PLLI2SQ_1 0x02000000U
+#define RCC_PLLI2SCFGR_PLLI2SQ_2 0x04000000U
+#define RCC_PLLI2SCFGR_PLLI2SQ_3 0x08000000U
+
+#define RCC_PLLI2SCFGR_PLLI2SR 0x70000000U
+#define RCC_PLLI2SCFGR_PLLI2SR_0 0x10000000U
+#define RCC_PLLI2SCFGR_PLLI2SR_1 0x20000000U
+#define RCC_PLLI2SCFGR_PLLI2SR_2 0x40000000U
+
+
+/******************** Bit definition for RCC_PLLSAICFGR register ************/
+#define RCC_PLLSAICFGR_PLLSAIN 0x00007FC0U
+#define RCC_PLLSAICFGR_PLLSAIN_0 0x00000040U
+#define RCC_PLLSAICFGR_PLLSAIN_1 0x00000080U
+#define RCC_PLLSAICFGR_PLLSAIN_2 0x00000100U
+#define RCC_PLLSAICFGR_PLLSAIN_3 0x00000200U
+#define RCC_PLLSAICFGR_PLLSAIN_4 0x00000400U
+#define RCC_PLLSAICFGR_PLLSAIN_5 0x00000800U
+#define RCC_PLLSAICFGR_PLLSAIN_6 0x00001000U
+#define RCC_PLLSAICFGR_PLLSAIN_7 0x00002000U
+#define RCC_PLLSAICFGR_PLLSAIN_8 0x00004000U
+
+#define RCC_PLLSAICFGR_PLLSAIP 0x00030000U
+#define RCC_PLLSAICFGR_PLLSAIP_0 0x00010000U
+#define RCC_PLLSAICFGR_PLLSAIP_1 0x00020000U
+
+#define RCC_PLLSAICFGR_PLLSAIQ 0x0F000000U
+#define RCC_PLLSAICFGR_PLLSAIQ_0 0x01000000U
+#define RCC_PLLSAICFGR_PLLSAIQ_1 0x02000000U
+#define RCC_PLLSAICFGR_PLLSAIQ_2 0x04000000U
+#define RCC_PLLSAICFGR_PLLSAIQ_3 0x08000000U
+
+#define RCC_PLLSAICFGR_PLLSAIR 0x70000000U
+#define RCC_PLLSAICFGR_PLLSAIR_0 0x10000000U
+#define RCC_PLLSAICFGR_PLLSAIR_1 0x20000000U
+#define RCC_PLLSAICFGR_PLLSAIR_2 0x40000000U
+
+/******************** Bit definition for RCC_DCKCFGR register ***************/
+#define RCC_DCKCFGR_PLLI2SDIVQ 0x0000001FU
+#define RCC_DCKCFGR_PLLSAIDIVQ 0x00001F00U
+#define RCC_DCKCFGR_PLLSAIDIVR 0x00030000U
+#define RCC_DCKCFGR_SAI1ASRC 0x00300000U
+#define RCC_DCKCFGR_SAI1ASRC_0 0x00100000U
+#define RCC_DCKCFGR_SAI1ASRC_1 0x00200000U
+#define RCC_DCKCFGR_SAI1BSRC 0x00C00000U
+#define RCC_DCKCFGR_SAI1BSRC_0 0x00400000U
+#define RCC_DCKCFGR_SAI1BSRC_1 0x00800000U
+#define RCC_DCKCFGR_TIMPRE 0x01000000U
+#define RCC_DCKCFGR_CK48MSEL 0x08000000U
+#define RCC_DCKCFGR_SDIOSEL 0x10000000U
+#define RCC_DCKCFGR_DSISEL 0x20000000U
+
+/******************************************************************************/
+/* */
+/* RNG */
+/* */
+/******************************************************************************/
+/******************** Bits definition for RNG_CR register *******************/
+#define RNG_CR_RNGEN 0x00000004U
+#define RNG_CR_IE 0x00000008U
+
+/******************** Bits definition for RNG_SR register *******************/
+#define RNG_SR_DRDY 0x00000001U
+#define RNG_SR_CECS 0x00000002U
+#define RNG_SR_SECS 0x00000004U
+#define RNG_SR_CEIS 0x00000020U
+#define RNG_SR_SEIS 0x00000040U
+
+/******************************************************************************/
+/* */
+/* Real-Time Clock (RTC) */
+/* */
+/******************************************************************************/
+/******************** Bits definition for RTC_TR register *******************/
+#define RTC_TR_PM 0x00400000U
+#define RTC_TR_HT 0x00300000U
+#define RTC_TR_HT_0 0x00100000U
+#define RTC_TR_HT_1 0x00200000U
+#define RTC_TR_HU 0x000F0000U
+#define RTC_TR_HU_0 0x00010000U
+#define RTC_TR_HU_1 0x00020000U
+#define RTC_TR_HU_2 0x00040000U
+#define RTC_TR_HU_3 0x00080000U
+#define RTC_TR_MNT 0x00007000U
+#define RTC_TR_MNT_0 0x00001000U
+#define RTC_TR_MNT_1 0x00002000U
+#define RTC_TR_MNT_2 0x00004000U
+#define RTC_TR_MNU 0x00000F00U
+#define RTC_TR_MNU_0 0x00000100U
+#define RTC_TR_MNU_1 0x00000200U
+#define RTC_TR_MNU_2 0x00000400U
+#define RTC_TR_MNU_3 0x00000800U
+#define RTC_TR_ST 0x00000070U
+#define RTC_TR_ST_0 0x00000010U
+#define RTC_TR_ST_1 0x00000020U
+#define RTC_TR_ST_2 0x00000040U
+#define RTC_TR_SU 0x0000000FU
+#define RTC_TR_SU_0 0x00000001U
+#define RTC_TR_SU_1 0x00000002U
+#define RTC_TR_SU_2 0x00000004U
+#define RTC_TR_SU_3 0x00000008U
+
+/******************** Bits definition for RTC_DR register *******************/
+#define RTC_DR_YT 0x00F00000U
+#define RTC_DR_YT_0 0x00100000U
+#define RTC_DR_YT_1 0x00200000U
+#define RTC_DR_YT_2 0x00400000U
+#define RTC_DR_YT_3 0x00800000U
+#define RTC_DR_YU 0x000F0000U
+#define RTC_DR_YU_0 0x00010000U
+#define RTC_DR_YU_1 0x00020000U
+#define RTC_DR_YU_2 0x00040000U
+#define RTC_DR_YU_3 0x00080000U
+#define RTC_DR_WDU 0x0000E000U
+#define RTC_DR_WDU_0 0x00002000U
+#define RTC_DR_WDU_1 0x00004000U
+#define RTC_DR_WDU_2 0x00008000U
+#define RTC_DR_MT 0x00001000U
+#define RTC_DR_MU 0x00000F00U
+#define RTC_DR_MU_0 0x00000100U
+#define RTC_DR_MU_1 0x00000200U
+#define RTC_DR_MU_2 0x00000400U
+#define RTC_DR_MU_3 0x00000800U
+#define RTC_DR_DT 0x00000030U
+#define RTC_DR_DT_0 0x00000010U
+#define RTC_DR_DT_1 0x00000020U
+#define RTC_DR_DU 0x0000000FU
+#define RTC_DR_DU_0 0x00000001U
+#define RTC_DR_DU_1 0x00000002U
+#define RTC_DR_DU_2 0x00000004U
+#define RTC_DR_DU_3 0x00000008U
+
+/******************** Bits definition for RTC_CR register *******************/
+#define RTC_CR_COE 0x00800000U
+#define RTC_CR_OSEL 0x00600000U
+#define RTC_CR_OSEL_0 0x00200000U
+#define RTC_CR_OSEL_1 0x00400000U
+#define RTC_CR_POL 0x00100000U
+#define RTC_CR_COSEL 0x00080000U
+#define RTC_CR_BCK 0x00040000U
+#define RTC_CR_SUB1H 0x00020000U
+#define RTC_CR_ADD1H 0x00010000U
+#define RTC_CR_TSIE 0x00008000U
+#define RTC_CR_WUTIE 0x00004000U
+#define RTC_CR_ALRBIE 0x00002000U
+#define RTC_CR_ALRAIE 0x00001000U
+#define RTC_CR_TSE 0x00000800U
+#define RTC_CR_WUTE 0x00000400U
+#define RTC_CR_ALRBE 0x00000200U
+#define RTC_CR_ALRAE 0x00000100U
+#define RTC_CR_DCE 0x00000080U
+#define RTC_CR_FMT 0x00000040U
+#define RTC_CR_BYPSHAD 0x00000020U
+#define RTC_CR_REFCKON 0x00000010U
+#define RTC_CR_TSEDGE 0x00000008U
+#define RTC_CR_WUCKSEL 0x00000007U
+#define RTC_CR_WUCKSEL_0 0x00000001U
+#define RTC_CR_WUCKSEL_1 0x00000002U
+#define RTC_CR_WUCKSEL_2 0x00000004U
+
+/******************** Bits definition for RTC_ISR register ******************/
+#define RTC_ISR_RECALPF 0x00010000U
+#define RTC_ISR_TAMP1F 0x00002000U
+#define RTC_ISR_TAMP2F 0x00004000U
+#define RTC_ISR_TSOVF 0x00001000U
+#define RTC_ISR_TSF 0x00000800U
+#define RTC_ISR_WUTF 0x00000400U
+#define RTC_ISR_ALRBF 0x00000200U
+#define RTC_ISR_ALRAF 0x00000100U
+#define RTC_ISR_INIT 0x00000080U
+#define RTC_ISR_INITF 0x00000040U
+#define RTC_ISR_RSF 0x00000020U
+#define RTC_ISR_INITS 0x00000010U
+#define RTC_ISR_SHPF 0x00000008U
+#define RTC_ISR_WUTWF 0x00000004U
+#define RTC_ISR_ALRBWF 0x00000002U
+#define RTC_ISR_ALRAWF 0x00000001U
+
+/******************** Bits definition for RTC_PRER register *****************/
+#define RTC_PRER_PREDIV_A 0x007F0000U
+#define RTC_PRER_PREDIV_S 0x00007FFFU
+
+/******************** Bits definition for RTC_WUTR register *****************/
+#define RTC_WUTR_WUT 0x0000FFFFU
+
+/******************** Bits definition for RTC_CALIBR register ***************/
+#define RTC_CALIBR_DCS 0x00000080U
+#define RTC_CALIBR_DC 0x0000001FU
+
+/******************** Bits definition for RTC_ALRMAR register ***************/
+#define RTC_ALRMAR_MSK4 0x80000000U
+#define RTC_ALRMAR_WDSEL 0x40000000U
+#define RTC_ALRMAR_DT 0x30000000U
+#define RTC_ALRMAR_DT_0 0x10000000U
+#define RTC_ALRMAR_DT_1 0x20000000U
+#define RTC_ALRMAR_DU 0x0F000000U
+#define RTC_ALRMAR_DU_0 0x01000000U
+#define RTC_ALRMAR_DU_1 0x02000000U
+#define RTC_ALRMAR_DU_2 0x04000000U
+#define RTC_ALRMAR_DU_3 0x08000000U
+#define RTC_ALRMAR_MSK3 0x00800000U
+#define RTC_ALRMAR_PM 0x00400000U
+#define RTC_ALRMAR_HT 0x00300000U
+#define RTC_ALRMAR_HT_0 0x00100000U
+#define RTC_ALRMAR_HT_1 0x00200000U
+#define RTC_ALRMAR_HU 0x000F0000U
+#define RTC_ALRMAR_HU_0 0x00010000U
+#define RTC_ALRMAR_HU_1 0x00020000U
+#define RTC_ALRMAR_HU_2 0x00040000U
+#define RTC_ALRMAR_HU_3 0x00080000U
+#define RTC_ALRMAR_MSK2 0x00008000U
+#define RTC_ALRMAR_MNT 0x00007000U
+#define RTC_ALRMAR_MNT_0 0x00001000U
+#define RTC_ALRMAR_MNT_1 0x00002000U
+#define RTC_ALRMAR_MNT_2 0x00004000U
+#define RTC_ALRMAR_MNU 0x00000F00U
+#define RTC_ALRMAR_MNU_0 0x00000100U
+#define RTC_ALRMAR_MNU_1 0x00000200U
+#define RTC_ALRMAR_MNU_2 0x00000400U
+#define RTC_ALRMAR_MNU_3 0x00000800U
+#define RTC_ALRMAR_MSK1 0x00000080U
+#define RTC_ALRMAR_ST 0x00000070U
+#define RTC_ALRMAR_ST_0 0x00000010U
+#define RTC_ALRMAR_ST_1 0x00000020U
+#define RTC_ALRMAR_ST_2 0x00000040U
+#define RTC_ALRMAR_SU 0x0000000FU
+#define RTC_ALRMAR_SU_0 0x00000001U
+#define RTC_ALRMAR_SU_1 0x00000002U
+#define RTC_ALRMAR_SU_2 0x00000004U
+#define RTC_ALRMAR_SU_3 0x00000008U
+
+/******************** Bits definition for RTC_ALRMBR register ***************/
+#define RTC_ALRMBR_MSK4 0x80000000U
+#define RTC_ALRMBR_WDSEL 0x40000000U
+#define RTC_ALRMBR_DT 0x30000000U
+#define RTC_ALRMBR_DT_0 0x10000000U
+#define RTC_ALRMBR_DT_1 0x20000000U
+#define RTC_ALRMBR_DU 0x0F000000U
+#define RTC_ALRMBR_DU_0 0x01000000U
+#define RTC_ALRMBR_DU_1 0x02000000U
+#define RTC_ALRMBR_DU_2 0x04000000U
+#define RTC_ALRMBR_DU_3 0x08000000U
+#define RTC_ALRMBR_MSK3 0x00800000U
+#define RTC_ALRMBR_PM 0x00400000U
+#define RTC_ALRMBR_HT 0x00300000U
+#define RTC_ALRMBR_HT_0 0x00100000U
+#define RTC_ALRMBR_HT_1 0x00200000U
+#define RTC_ALRMBR_HU 0x000F0000U
+#define RTC_ALRMBR_HU_0 0x00010000U
+#define RTC_ALRMBR_HU_1 0x00020000U
+#define RTC_ALRMBR_HU_2 0x00040000U
+#define RTC_ALRMBR_HU_3 0x00080000U
+#define RTC_ALRMBR_MSK2 0x00008000U
+#define RTC_ALRMBR_MNT 0x00007000U
+#define RTC_ALRMBR_MNT_0 0x00001000U
+#define RTC_ALRMBR_MNT_1 0x00002000U
+#define RTC_ALRMBR_MNT_2 0x00004000U
+#define RTC_ALRMBR_MNU 0x00000F00U
+#define RTC_ALRMBR_MNU_0 0x00000100U
+#define RTC_ALRMBR_MNU_1 0x00000200U
+#define RTC_ALRMBR_MNU_2 0x00000400U
+#define RTC_ALRMBR_MNU_3 0x00000800U
+#define RTC_ALRMBR_MSK1 0x00000080U
+#define RTC_ALRMBR_ST 0x00000070U
+#define RTC_ALRMBR_ST_0 0x00000010U
+#define RTC_ALRMBR_ST_1 0x00000020U
+#define RTC_ALRMBR_ST_2 0x00000040U
+#define RTC_ALRMBR_SU 0x0000000FU
+#define RTC_ALRMBR_SU_0 0x00000001U
+#define RTC_ALRMBR_SU_1 0x00000002U
+#define RTC_ALRMBR_SU_2 0x00000004U
+#define RTC_ALRMBR_SU_3 0x00000008U
+
+/******************** Bits definition for RTC_WPR register ******************/
+#define RTC_WPR_KEY 0x000000FFU
+
+/******************** Bits definition for RTC_SSR register ******************/
+#define RTC_SSR_SS 0x0000FFFFU
+
+/******************** Bits definition for RTC_SHIFTR register ***************/
+#define RTC_SHIFTR_SUBFS 0x00007FFFU
+#define RTC_SHIFTR_ADD1S 0x80000000U
+
+/******************** Bits definition for RTC_TSTR register *****************/
+#define RTC_TSTR_PM 0x00400000U
+#define RTC_TSTR_HT 0x00300000U
+#define RTC_TSTR_HT_0 0x00100000U
+#define RTC_TSTR_HT_1 0x00200000U
+#define RTC_TSTR_HU 0x000F0000U
+#define RTC_TSTR_HU_0 0x00010000U
+#define RTC_TSTR_HU_1 0x00020000U
+#define RTC_TSTR_HU_2 0x00040000U
+#define RTC_TSTR_HU_3 0x00080000U
+#define RTC_TSTR_MNT 0x00007000U
+#define RTC_TSTR_MNT_0 0x00001000U
+#define RTC_TSTR_MNT_1 0x00002000U
+#define RTC_TSTR_MNT_2 0x00004000U
+#define RTC_TSTR_MNU 0x00000F00U
+#define RTC_TSTR_MNU_0 0x00000100U
+#define RTC_TSTR_MNU_1 0x00000200U
+#define RTC_TSTR_MNU_2 0x00000400U
+#define RTC_TSTR_MNU_3 0x00000800U
+#define RTC_TSTR_ST 0x00000070U
+#define RTC_TSTR_ST_0 0x00000010U
+#define RTC_TSTR_ST_1 0x00000020U
+#define RTC_TSTR_ST_2 0x00000040U
+#define RTC_TSTR_SU 0x0000000FU
+#define RTC_TSTR_SU_0 0x00000001U
+#define RTC_TSTR_SU_1 0x00000002U
+#define RTC_TSTR_SU_2 0x00000004U
+#define RTC_TSTR_SU_3 0x00000008U
+
+/******************** Bits definition for RTC_TSDR register *****************/
+#define RTC_TSDR_WDU 0x0000E000U
+#define RTC_TSDR_WDU_0 0x00002000U
+#define RTC_TSDR_WDU_1 0x00004000U
+#define RTC_TSDR_WDU_2 0x00008000U
+#define RTC_TSDR_MT 0x00001000U
+#define RTC_TSDR_MU 0x00000F00U
+#define RTC_TSDR_MU_0 0x00000100U
+#define RTC_TSDR_MU_1 0x00000200U
+#define RTC_TSDR_MU_2 0x00000400U
+#define RTC_TSDR_MU_3 0x00000800U
+#define RTC_TSDR_DT 0x00000030U
+#define RTC_TSDR_DT_0 0x00000010U
+#define RTC_TSDR_DT_1 0x00000020U
+#define RTC_TSDR_DU 0x0000000FU
+#define RTC_TSDR_DU_0 0x00000001U
+#define RTC_TSDR_DU_1 0x00000002U
+#define RTC_TSDR_DU_2 0x00000004U
+#define RTC_TSDR_DU_3 0x00000008U
+
+/******************** Bits definition for RTC_TSSSR register ****************/
+#define RTC_TSSSR_SS 0x0000FFFFU
+
+/******************** Bits definition for RTC_CAL register *****************/
+#define RTC_CALR_CALP 0x00008000U
+#define RTC_CALR_CALW8 0x00004000U
+#define RTC_CALR_CALW16 0x00002000U
+#define RTC_CALR_CALM 0x000001FFU
+#define RTC_CALR_CALM_0 0x00000001U
+#define RTC_CALR_CALM_1 0x00000002U
+#define RTC_CALR_CALM_2 0x00000004U
+#define RTC_CALR_CALM_3 0x00000008U
+#define RTC_CALR_CALM_4 0x00000010U
+#define RTC_CALR_CALM_5 0x00000020U
+#define RTC_CALR_CALM_6 0x00000040U
+#define RTC_CALR_CALM_7 0x00000080U
+#define RTC_CALR_CALM_8 0x00000100U
+
+/******************** Bits definition for RTC_TAFCR register ****************/
+#define RTC_TAFCR_ALARMOUTTYPE 0x00040000U
+#define RTC_TAFCR_TSINSEL 0x00020000U
+#define RTC_TAFCR_TAMPINSEL 0x00010000U
+#define RTC_TAFCR_TAMPPUDIS 0x00008000U
+#define RTC_TAFCR_TAMPPRCH 0x00006000U
+#define RTC_TAFCR_TAMPPRCH_0 0x00002000U
+#define RTC_TAFCR_TAMPPRCH_1 0x00004000U
+#define RTC_TAFCR_TAMPFLT 0x00001800U
+#define RTC_TAFCR_TAMPFLT_0 0x00000800U
+#define RTC_TAFCR_TAMPFLT_1 0x00001000U
+#define RTC_TAFCR_TAMPFREQ 0x00000700U
+#define RTC_TAFCR_TAMPFREQ_0 0x00000100U
+#define RTC_TAFCR_TAMPFREQ_1 0x00000200U
+#define RTC_TAFCR_TAMPFREQ_2 0x00000400U
+#define RTC_TAFCR_TAMPTS 0x00000080U
+#define RTC_TAFCR_TAMP2TRG 0x00000010U
+#define RTC_TAFCR_TAMP2E 0x00000008U
+#define RTC_TAFCR_TAMPIE 0x00000004U
+#define RTC_TAFCR_TAMP1TRG 0x00000002U
+#define RTC_TAFCR_TAMP1E 0x00000001U
+
+/******************** Bits definition for RTC_ALRMASSR register *************/
+#define RTC_ALRMASSR_MASKSS 0x0F000000U
+#define RTC_ALRMASSR_MASKSS_0 0x01000000U
+#define RTC_ALRMASSR_MASKSS_1 0x02000000U
+#define RTC_ALRMASSR_MASKSS_2 0x04000000U
+#define RTC_ALRMASSR_MASKSS_3 0x08000000U
+#define RTC_ALRMASSR_SS 0x00007FFFU
+
+/******************** Bits definition for RTC_ALRMBSSR register *************/
+#define RTC_ALRMBSSR_MASKSS 0x0F000000U
+#define RTC_ALRMBSSR_MASKSS_0 0x01000000U
+#define RTC_ALRMBSSR_MASKSS_1 0x02000000U
+#define RTC_ALRMBSSR_MASKSS_2 0x04000000U
+#define RTC_ALRMBSSR_MASKSS_3 0x08000000U
+#define RTC_ALRMBSSR_SS 0x00007FFFU
+
+/******************** Bits definition for RTC_BKP0R register ****************/
+#define RTC_BKP0R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP1R register ****************/
+#define RTC_BKP1R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP2R register ****************/
+#define RTC_BKP2R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP3R register ****************/
+#define RTC_BKP3R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP4R register ****************/
+#define RTC_BKP4R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP5R register ****************/
+#define RTC_BKP5R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP6R register ****************/
+#define RTC_BKP6R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP7R register ****************/
+#define RTC_BKP7R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP8R register ****************/
+#define RTC_BKP8R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP9R register ****************/
+#define RTC_BKP9R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP10R register ***************/
+#define RTC_BKP10R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP11R register ***************/
+#define RTC_BKP11R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP12R register ***************/
+#define RTC_BKP12R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP13R register ***************/
+#define RTC_BKP13R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP14R register ***************/
+#define RTC_BKP14R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP15R register ***************/
+#define RTC_BKP15R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP16R register ***************/
+#define RTC_BKP16R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP17R register ***************/
+#define RTC_BKP17R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP18R register ***************/
+#define RTC_BKP18R 0xFFFFFFFFU
+
+/******************** Bits definition for RTC_BKP19R register ***************/
+#define RTC_BKP19R 0xFFFFFFFFU
+
+/******************************************************************************/
+/* */
+/* Serial Audio Interface */
+/* */
+/******************************************************************************/
+/******************** Bit definition for SAI_GCR register *******************/
+#define SAI_GCR_SYNCIN 0x00000003U /*!<SYNCIN[1:0] bits (Synchronization Inputs) */
+#define SAI_GCR_SYNCIN_0 0x00000001U /*!<Bit 0 */
+#define SAI_GCR_SYNCIN_1 0x00000002U /*!<Bit 1 */
+
+#define SAI_GCR_SYNCOUT 0x00000030U /*!<SYNCOUT[1:0] bits (Synchronization Outputs) */
+#define SAI_GCR_SYNCOUT_0 0x00000010U /*!<Bit 0 */
+#define SAI_GCR_SYNCOUT_1 0x00000020U /*!<Bit 1 */
+
+/******************* Bit definition for SAI_xCR1 register *******************/
+#define SAI_xCR1_MODE 0x00000003U /*!<MODE[1:0] bits (Audio Block Mode) */
+#define SAI_xCR1_MODE_0 0x00000001U /*!<Bit 0 */
+#define SAI_xCR1_MODE_1 0x00000002U /*!<Bit 1 */
+
+#define SAI_xCR1_PRTCFG 0x0000000CU /*!<PRTCFG[1:0] bits (Protocol Configuration) */
+#define SAI_xCR1_PRTCFG_0 0x00000004U /*!<Bit 0 */
+#define SAI_xCR1_PRTCFG_1 0x00000008U /*!<Bit 1 */
+
+#define SAI_xCR1_DS 0x000000E0U /*!<DS[1:0] bits (Data Size) */
+#define SAI_xCR1_DS_0 0x00000020U /*!<Bit 0 */
+#define SAI_xCR1_DS_1 0x00000040U /*!<Bit 1 */
+#define SAI_xCR1_DS_2 0x00000080U /*!<Bit 2 */
+
+#define SAI_xCR1_LSBFIRST 0x00000100U /*!<LSB First Configuration */
+#define SAI_xCR1_CKSTR 0x00000200U /*!<ClocK STRobing edge */
+
+#define SAI_xCR1_SYNCEN 0x00000C00U /*!<SYNCEN[1:0](SYNChronization ENable) */
+#define SAI_xCR1_SYNCEN_0 0x00000400U /*!<Bit 0 */
+#define SAI_xCR1_SYNCEN_1 0x00000800U /*!<Bit 1 */
+
+#define SAI_xCR1_MONO 0x00001000U /*!<Mono mode */
+#define SAI_xCR1_OUTDRIV 0x00002000U /*!<Output Drive */
+#define SAI_xCR1_SAIEN 0x00010000U /*!<Audio Block enable */
+#define SAI_xCR1_DMAEN 0x00020000U /*!<DMA enable */
+#define SAI_xCR1_NODIV 0x00080000U /*!<No Divider Configuration */
+
+#define SAI_xCR1_MCKDIV 0x00F00000U /*!<MCKDIV[3:0] (Master ClocK Divider) */
+#define SAI_xCR1_MCKDIV_0 0x00100000U /*!<Bit 0 */
+#define SAI_xCR1_MCKDIV_1 0x00200000U /*!<Bit 1 */
+#define SAI_xCR1_MCKDIV_2 0x00400000U /*!<Bit 2 */
+#define SAI_xCR1_MCKDIV_3 0x00800000U /*!<Bit 3 */
+
+/******************* Bit definition for SAI_xCR2 register *******************/
+#define SAI_xCR2_FTH 0x00000007U /*!<FTH[2:0](Fifo THreshold) */
+#define SAI_xCR2_FTH_0 0x00000001U /*!<Bit 0 */
+#define SAI_xCR2_FTH_1 0x00000002U /*!<Bit 1 */
+#define SAI_xCR2_FTH_2 0x00000004U /*!<Bit 2 */
+
+#define SAI_xCR2_FFLUSH 0x00000008U /*!<Fifo FLUSH */
+#define SAI_xCR2_TRIS 0x00000010U /*!<TRIState Management on data line */
+#define SAI_xCR2_MUTE 0x00000020U /*!<Mute mode */
+#define SAI_xCR2_MUTEVAL 0x00000040U /*!<Muate value */
+
+#define SAI_xCR2_MUTECNT 0x00001F80U /*!<MUTECNT[5:0] (MUTE counter) */
+#define SAI_xCR2_MUTECNT_0 0x00000080U /*!<Bit 0 */
+#define SAI_xCR2_MUTECNT_1 0x00000100U /*!<Bit 1 */
+#define SAI_xCR2_MUTECNT_2 0x00000200U /*!<Bit 2 */
+#define SAI_xCR2_MUTECNT_3 0x00000400U /*!<Bit 3 */
+#define SAI_xCR2_MUTECNT_4 0x00000800U /*!<Bit 4 */
+#define SAI_xCR2_MUTECNT_5 0x00001000U /*!<Bit 5 */
+
+#define SAI_xCR2_CPL 0x00002000U /*!< Complement Bit */
+
+#define SAI_xCR2_COMP 0x0000C000U /*!<COMP[1:0] (Companding mode) */
+#define SAI_xCR2_COMP_0 0x00004000U /*!<Bit 0 */
+#define SAI_xCR2_COMP_1 0x00008000U /*!<Bit 1 */
+
+/****************** Bit definition for SAI_xFRCR register *******************/
+#define SAI_xFRCR_FRL 0x000000FFU /*!<FRL[1:0](Frame length) */
+#define SAI_xFRCR_FRL_0 0x00000001U /*!<Bit 0 */
+#define SAI_xFRCR_FRL_1 0x00000002U /*!<Bit 1 */
+#define SAI_xFRCR_FRL_2 0x00000004U /*!<Bit 2 */
+#define SAI_xFRCR_FRL_3 0x00000008U /*!<Bit 3 */
+#define SAI_xFRCR_FRL_4 0x00000010U /*!<Bit 4 */
+#define SAI_xFRCR_FRL_5 0x00000020U /*!<Bit 5 */
+#define SAI_xFRCR_FRL_6 0x00000040U /*!<Bit 6 */
+#define SAI_xFRCR_FRL_7 0x00000080U /*!<Bit 7 */
+
+#define SAI_xFRCR_FSALL 0x00007F00U /*!<FRL[1:0] (Frame synchronization active level length) */
+#define SAI_xFRCR_FSALL_0 0x00000100U /*!<Bit 0 */
+#define SAI_xFRCR_FSALL_1 0x00000200U /*!<Bit 1 */
+#define SAI_xFRCR_FSALL_2 0x00000400U /*!<Bit 2 */
+#define SAI_xFRCR_FSALL_3 0x00000800U /*!<Bit 3 */
+#define SAI_xFRCR_FSALL_4 0x00001000U /*!<Bit 4 */
+#define SAI_xFRCR_FSALL_5 0x00002000U /*!<Bit 5 */
+#define SAI_xFRCR_FSALL_6 0x00004000U /*!<Bit 6 */
+
+#define SAI_xFRCR_FSDEF 0x00010000U /*!< Frame Synchronization Definition */
+#define SAI_xFRCR_FSPOL 0x00020000U /*!<Frame Synchronization POLarity */
+#define SAI_xFRCR_FSOFF 0x00040000U /*!<Frame Synchronization OFFset */
+/* Legacy defines */
+#define SAI_xFRCR_FSPO SAI_xFRCR_FSPOL
+
+/****************** Bit definition for SAI_xSLOTR register *******************/
+#define SAI_xSLOTR_FBOFF 0x0000001FU /*!<FRL[4:0](First Bit Offset) */
+#define SAI_xSLOTR_FBOFF_0 0x00000001U /*!<Bit 0 */
+#define SAI_xSLOTR_FBOFF_1 0x00000002U /*!<Bit 1 */
+#define SAI_xSLOTR_FBOFF_2 0x00000004U /*!<Bit 2 */
+#define SAI_xSLOTR_FBOFF_3 0x00000008U /*!<Bit 3 */
+#define SAI_xSLOTR_FBOFF_4 0x00000010U /*!<Bit 4 */
+
+#define SAI_xSLOTR_SLOTSZ 0x000000C0U /*!<SLOTSZ[1:0] (Slot size) */
+#define SAI_xSLOTR_SLOTSZ_0 0x00000040U /*!<Bit 0 */
+#define SAI_xSLOTR_SLOTSZ_1 0x00000080U /*!<Bit 1 */
+
+#define SAI_xSLOTR_NBSLOT 0x00000F00U /*!<NBSLOT[3:0] (Number of Slot in audio Frame) */
+#define SAI_xSLOTR_NBSLOT_0 0x00000100U /*!<Bit 0 */
+#define SAI_xSLOTR_NBSLOT_1 0x00000200U /*!<Bit 1 */
+#define SAI_xSLOTR_NBSLOT_2 0x00000400U /*!<Bit 2 */
+#define SAI_xSLOTR_NBSLOT_3 0x00000800U /*!<Bit 3 */
+
+#define SAI_xSLOTR_SLOTEN 0xFFFF0000U /*!<SLOTEN[15:0] (Slot Enable) */
+
+/******************* Bit definition for SAI_xIMR register *******************/
+#define SAI_xIMR_OVRUDRIE 0x00000001U /*!<Overrun underrun interrupt enable */
+#define SAI_xIMR_MUTEDETIE 0x00000002U /*!<Mute detection interrupt enable */
+#define SAI_xIMR_WCKCFGIE 0x00000004U /*!<Wrong Clock Configuration interrupt enable */
+#define SAI_xIMR_FREQIE 0x00000008U /*!<FIFO request interrupt enable */
+#define SAI_xIMR_CNRDYIE 0x00000010U /*!<Codec not ready interrupt enable */
+#define SAI_xIMR_AFSDETIE 0x00000020U /*!<Anticipated frame synchronization detection interrupt enable */
+#define SAI_xIMR_LFSDETIE 0x00000040U /*!<Late frame synchronization detection interrupt enable */
+
+/******************** Bit definition for SAI_xSR register *******************/
+#define SAI_xSR_OVRUDR 0x00000001U /*!<Overrun underrun */
+#define SAI_xSR_MUTEDET 0x00000002U /*!<Mute detection */
+#define SAI_xSR_WCKCFG 0x00000004U /*!<Wrong Clock Configuration */
+#define SAI_xSR_FREQ 0x00000008U /*!<FIFO request */
+#define SAI_xSR_CNRDY 0x00000010U /*!<Codec not ready */
+#define SAI_xSR_AFSDET 0x00000020U /*!<Anticipated frame synchronization detection */
+#define SAI_xSR_LFSDET 0x00000040U /*!<Late frame synchronization detection */
+
+#define SAI_xSR_FLVL 0x00070000U /*!<FLVL[2:0] (FIFO Level Threshold) */
+#define SAI_xSR_FLVL_0 0x00010000U /*!<Bit 0 */
+#define SAI_xSR_FLVL_1 0x00020000U /*!<Bit 1 */
+#define SAI_xSR_FLVL_2 0x00040000U /*!<Bit 2 */
+
+/****************** Bit definition for SAI_xCLRFR register ******************/
+#define SAI_xCLRFR_COVRUDR 0x00000001U /*!<Clear Overrun underrun */
+#define SAI_xCLRFR_CMUTEDET 0x00000002U /*!<Clear Mute detection */
+#define SAI_xCLRFR_CWCKCFG 0x00000004U /*!<Clear Wrong Clock Configuration */
+#define SAI_xCLRFR_CFREQ 0x00000008U /*!<Clear FIFO request */
+#define SAI_xCLRFR_CCNRDY 0x00000010U /*!<Clear Codec not ready */
+#define SAI_xCLRFR_CAFSDET 0x00000020U /*!<Clear Anticipated frame synchronization detection */
+#define SAI_xCLRFR_CLFSDET 0x00000040U /*!<Clear Late frame synchronization detection */
+
+/****************** Bit definition for SAI_xDR register ******************/
+#define SAI_xDR_DATA 0xFFFFFFFFU
+
+
+/******************************************************************************/
+/* */
+/* SD host Interface */
+/* */
+/******************************************************************************/
+/****************** Bit definition for SDIO_POWER register ******************/
+#define SDIO_POWER_PWRCTRL 0x03U /*!<PWRCTRL[1:0] bits (Power supply control bits) */
+#define SDIO_POWER_PWRCTRL_0 0x01U /*!<Bit 0 */
+#define SDIO_POWER_PWRCTRL_1 0x02U /*!<Bit 1 */
+
+/****************** Bit definition for SDIO_CLKCR register ******************/
+#define SDIO_CLKCR_CLKDIV 0x00FFU /*!<Clock divide factor */
+#define SDIO_CLKCR_CLKEN 0x0100U /*!<Clock enable bit */
+#define SDIO_CLKCR_PWRSAV 0x0200U /*!<Power saving configuration bit */
+#define SDIO_CLKCR_BYPASS 0x0400U /*!<Clock divider bypass enable bit */
+
+#define SDIO_CLKCR_WIDBUS 0x1800U /*!<WIDBUS[1:0] bits (Wide bus mode enable bit) */
+#define SDIO_CLKCR_WIDBUS_0 0x0800U /*!<Bit 0 */
+#define SDIO_CLKCR_WIDBUS_1 0x1000U /*!<Bit 1 */
+
+#define SDIO_CLKCR_NEGEDGE 0x2000U /*!<SDIO_CK dephasing selection bit */
+#define SDIO_CLKCR_HWFC_EN 0x4000U /*!<HW Flow Control enable */
+
+/******************* Bit definition for SDIO_ARG register *******************/
+#define SDIO_ARG_CMDARG 0xFFFFFFFFU /*!<Command argument */
+
+/******************* Bit definition for SDIO_CMD register *******************/
+#define SDIO_CMD_CMDINDEX 0x003FU /*!<Command Index */
+
+#define SDIO_CMD_WAITRESP 0x00C0U /*!<WAITRESP[1:0] bits (Wait for response bits) */
+#define SDIO_CMD_WAITRESP_0 0x0040U /*!< Bit 0 */
+#define SDIO_CMD_WAITRESP_1 0x0080U /*!< Bit 1 */
+
+#define SDIO_CMD_WAITINT 0x0100U /*!<CPSM Waits for Interrupt Request */
+#define SDIO_CMD_WAITPEND 0x0200U /*!<CPSM Waits for ends of data transfer (CmdPend internal signal) */
+#define SDIO_CMD_CPSMEN 0x0400U /*!<Command path state machine (CPSM) Enable bit */
+#define SDIO_CMD_SDIOSUSPEND 0x0800U /*!<SD I/O suspend command */
+
+/***************** Bit definition for SDIO_RESPCMD register *****************/
+#define SDIO_RESPCMD_RESPCMD 0x3FU /*!<Response command index */
+
+/****************** Bit definition for SDIO_RESP0 register ******************/
+#define SDIO_RESP0_CARDSTATUS0 0xFFFFFFFFU /*!<Card Status */
+
+/****************** Bit definition for SDIO_RESP1 register ******************/
+#define SDIO_RESP1_CARDSTATUS1 0xFFFFFFFFU /*!<Card Status */
+
+/****************** Bit definition for SDIO_RESP2 register ******************/
+#define SDIO_RESP2_CARDSTATUS2 0xFFFFFFFFU /*!<Card Status */
+
+/****************** Bit definition for SDIO_RESP3 register ******************/
+#define SDIO_RESP3_CARDSTATUS3 0xFFFFFFFFU /*!<Card Status */
+
+/****************** Bit definition for SDIO_RESP4 register ******************/
+#define SDIO_RESP4_CARDSTATUS4 0xFFFFFFFFU /*!<Card Status */
+
+/****************** Bit definition for SDIO_DTIMER register *****************/
+#define SDIO_DTIMER_DATATIME 0xFFFFFFFFU /*!<Data timeout period. */
+
+/****************** Bit definition for SDIO_DLEN register *******************/
+#define SDIO_DLEN_DATALENGTH 0x01FFFFFFU /*!<Data length value */
+
+/****************** Bit definition for SDIO_DCTRL register ******************/
+#define SDIO_DCTRL_DTEN 0x0001U /*!<Data transfer enabled bit */
+#define SDIO_DCTRL_DTDIR 0x0002U /*!<Data transfer direction selection */
+#define SDIO_DCTRL_DTMODE 0x0004U /*!<Data transfer mode selection */
+#define SDIO_DCTRL_DMAEN 0x0008U /*!<DMA enabled bit */
+
+#define SDIO_DCTRL_DBLOCKSIZE 0x00F0U /*!<DBLOCKSIZE[3:0] bits (Data block size) */
+#define SDIO_DCTRL_DBLOCKSIZE_0 0x0010U /*!<Bit 0 */
+#define SDIO_DCTRL_DBLOCKSIZE_1 0x0020U /*!<Bit 1 */
+#define SDIO_DCTRL_DBLOCKSIZE_2 0x0040U /*!<Bit 2 */
+#define SDIO_DCTRL_DBLOCKSIZE_3 0x0080U /*!<Bit 3 */
+
+#define SDIO_DCTRL_RWSTART 0x0100U /*!<Read wait start */
+#define SDIO_DCTRL_RWSTOP 0x0200U /*!<Read wait stop */
+#define SDIO_DCTRL_RWMOD 0x0400U /*!<Read wait mode */
+#define SDIO_DCTRL_SDIOEN 0x0800U /*!<SD I/O enable functions */
+
+/****************** Bit definition for SDIO_DCOUNT register *****************/
+#define SDIO_DCOUNT_DATACOUNT 0x01FFFFFFU /*!<Data count value */
+
+/****************** Bit definition for SDIO_STA register ********************/
+#define SDIO_STA_CCRCFAIL 0x00000001U /*!<Command response received (CRC check failed) */
+#define SDIO_STA_DCRCFAIL 0x00000002U /*!<Data block sent/received (CRC check failed) */
+#define SDIO_STA_CTIMEOUT 0x00000004U /*!<Command response timeout */
+#define SDIO_STA_DTIMEOUT 0x00000008U /*!<Data timeout */
+#define SDIO_STA_TXUNDERR 0x00000010U /*!<Transmit FIFO underrun error */
+#define SDIO_STA_RXOVERR 0x00000020U /*!<Received FIFO overrun error */
+#define SDIO_STA_CMDREND 0x00000040U /*!<Command response received (CRC check passed) */
+#define SDIO_STA_CMDSENT 0x00000080U /*!<Command sent (no response required) */
+#define SDIO_STA_DATAEND 0x00000100U /*!<Data end (data counter, SDIDCOUNT, is zero) */
+#define SDIO_STA_DBCKEND 0x00000400U /*!<Data block sent/received (CRC check passed) */
+#define SDIO_STA_CMDACT 0x00000800U /*!<Command transfer in progress */
+#define SDIO_STA_TXACT 0x00001000U /*!<Data transmit in progress */
+#define SDIO_STA_RXACT 0x00002000U /*!<Data receive in progress */
+#define SDIO_STA_TXFIFOHE 0x00004000U /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
+#define SDIO_STA_RXFIFOHF 0x00008000U /*!<Receive FIFO Half Full: there are at least 8 words in the FIFO */
+#define SDIO_STA_TXFIFOF 0x00010000U /*!<Transmit FIFO full */
+#define SDIO_STA_RXFIFOF 0x00020000U /*!<Receive FIFO full */
+#define SDIO_STA_TXFIFOE 0x00040000U /*!<Transmit FIFO empty */
+#define SDIO_STA_RXFIFOE 0x00080000U /*!<Receive FIFO empty */
+#define SDIO_STA_TXDAVL 0x00100000U /*!<Data available in transmit FIFO */
+#define SDIO_STA_RXDAVL 0x00200000U /*!<Data available in receive FIFO */
+#define SDIO_STA_SDIOIT 0x00400000U /*!<SDIO interrupt received */
+
+/******************* Bit definition for SDIO_ICR register *******************/
+#define SDIO_ICR_CCRCFAILC 0x00000001U /*!<CCRCFAIL flag clear bit */
+#define SDIO_ICR_DCRCFAILC 0x00000002U /*!<DCRCFAIL flag clear bit */
+#define SDIO_ICR_CTIMEOUTC 0x00000004U /*!<CTIMEOUT flag clear bit */
+#define SDIO_ICR_DTIMEOUTC 0x00000008U /*!<DTIMEOUT flag clear bit */
+#define SDIO_ICR_TXUNDERRC 0x00000010U /*!<TXUNDERR flag clear bit */
+#define SDIO_ICR_RXOVERRC 0x00000020U /*!<RXOVERR flag clear bit */
+#define SDIO_ICR_CMDRENDC 0x00000040U /*!<CMDREND flag clear bit */
+#define SDIO_ICR_CMDSENTC 0x00000080U /*!<CMDSENT flag clear bit */
+#define SDIO_ICR_DATAENDC 0x00000100U /*!<DATAEND flag clear bit */
+#define SDIO_ICR_DBCKENDC 0x00000400U /*!<DBCKEND flag clear bit */
+#define SDIO_ICR_SDIOITC 0x00400000U /*!<SDIOIT flag clear bit */
+
+/****************** Bit definition for SDIO_MASK register *******************/
+#define SDIO_MASK_CCRCFAILIE 0x00000001U /*!<Command CRC Fail Interrupt Enable */
+#define SDIO_MASK_DCRCFAILIE 0x00000002U /*!<Data CRC Fail Interrupt Enable */
+#define SDIO_MASK_CTIMEOUTIE 0x00000004U /*!<Command TimeOut Interrupt Enable */
+#define SDIO_MASK_DTIMEOUTIE 0x00000008U /*!<Data TimeOut Interrupt Enable */
+#define SDIO_MASK_TXUNDERRIE 0x00000010U /*!<Tx FIFO UnderRun Error Interrupt Enable */
+#define SDIO_MASK_RXOVERRIE 0x00000020U /*!<Rx FIFO OverRun Error Interrupt Enable */
+#define SDIO_MASK_CMDRENDIE 0x00000040U /*!<Command Response Received Interrupt Enable */
+#define SDIO_MASK_CMDSENTIE 0x00000080U /*!<Command Sent Interrupt Enable */
+#define SDIO_MASK_DATAENDIE 0x00000100U /*!<Data End Interrupt Enable */
+#define SDIO_MASK_DBCKENDIE 0x00000400U /*!<Data Block End Interrupt Enable */
+#define SDIO_MASK_CMDACTIE 0x00000800U /*!<CCommand Acting Interrupt Enable */
+#define SDIO_MASK_TXACTIE 0x00001000U /*!<Data Transmit Acting Interrupt Enable */
+#define SDIO_MASK_RXACTIE 0x00002000U /*!<Data receive acting interrupt enabled */
+#define SDIO_MASK_TXFIFOHEIE 0x00004000U /*!<Tx FIFO Half Empty interrupt Enable */
+#define SDIO_MASK_RXFIFOHFIE 0x00008000U /*!<Rx FIFO Half Full interrupt Enable */
+#define SDIO_MASK_TXFIFOFIE 0x00010000U /*!<Tx FIFO Full interrupt Enable */
+#define SDIO_MASK_RXFIFOFIE 0x00020000U /*!<Rx FIFO Full interrupt Enable */
+#define SDIO_MASK_TXFIFOEIE 0x00040000U /*!<Tx FIFO Empty interrupt Enable */
+#define SDIO_MASK_RXFIFOEIE 0x00080000U /*!<Rx FIFO Empty interrupt Enable */
+#define SDIO_MASK_TXDAVLIE 0x00100000U /*!<Data available in Tx FIFO interrupt Enable */
+#define SDIO_MASK_RXDAVLIE 0x00200000U /*!<Data available in Rx FIFO interrupt Enable */
+#define SDIO_MASK_SDIOITIE 0x00400000U /*!<SDIO Mode Interrupt Received interrupt Enable */
+
+/***************** Bit definition for SDIO_FIFOCNT register *****************/
+#define SDIO_FIFOCNT_FIFOCOUNT 0x00FFFFFFU /*!<Remaining number of words to be written to or read from the FIFO */
+
+/****************** Bit definition for SDIO_FIFO register *******************/
+#define SDIO_FIFO_FIFODATA 0xFFFFFFFFU /*!<Receive and transmit FIFO data */
+
+/******************************************************************************/
+/* */
+/* Serial Peripheral Interface */
+/* */
+/******************************************************************************/
+/******************* Bit definition for SPI_CR1 register ********************/
+#define SPI_CR1_CPHA 0x00000001U /*!<Clock Phase */
+#define SPI_CR1_CPOL 0x00000002U /*!<Clock Polarity */
+#define SPI_CR1_MSTR 0x00000004U /*!<Master Selection */
+
+#define SPI_CR1_BR 0x00000038U /*!<BR[2:0] bits (Baud Rate Control) */
+#define SPI_CR1_BR_0 0x00000008U /*!<Bit 0 */
+#define SPI_CR1_BR_1 0x00000010U /*!<Bit 1 */
+#define SPI_CR1_BR_2 0x00000020U /*!<Bit 2 */
+
+#define SPI_CR1_SPE 0x00000040U /*!<SPI Enable */
+#define SPI_CR1_LSBFIRST 0x00000080U /*!<Frame Format */
+#define SPI_CR1_SSI 0x00000100U /*!<Internal slave select */
+#define SPI_CR1_SSM 0x00000200U /*!<Software slave management */
+#define SPI_CR1_RXONLY 0x00000400U /*!<Receive only */
+#define SPI_CR1_DFF 0x00000800U /*!<Data Frame Format */
+#define SPI_CR1_CRCNEXT 0x00001000U /*!<Transmit CRC next */
+#define SPI_CR1_CRCEN 0x00002000U /*!<Hardware CRC calculation enable */
+#define SPI_CR1_BIDIOE 0x00004000U /*!<Output enable in bidirectional mode */
+#define SPI_CR1_BIDIMODE 0x00008000U /*!<Bidirectional data mode enable */
+
+/******************* Bit definition for SPI_CR2 register ********************/
+#define SPI_CR2_RXDMAEN 0x00000001U /*!<Rx Buffer DMA Enable */
+#define SPI_CR2_TXDMAEN 0x00000002U /*!<Tx Buffer DMA Enable */
+#define SPI_CR2_SSOE 0x00000004U /*!<SS Output Enable */
+#define SPI_CR2_FRF 0x00000010U /*!<Frame Format */
+#define SPI_CR2_ERRIE 0x00000020U /*!<Error Interrupt Enable */
+#define SPI_CR2_RXNEIE 0x00000040U /*!<RX buffer Not Empty Interrupt Enable */
+#define SPI_CR2_TXEIE 0x00000080U /*!<Tx buffer Empty Interrupt Enable */
+
+/******************** Bit definition for SPI_SR register ********************/
+#define SPI_SR_RXNE 0x00000001U /*!<Receive buffer Not Empty */
+#define SPI_SR_TXE 0x00000002U /*!<Transmit buffer Empty */
+#define SPI_SR_CHSIDE 0x00000004U /*!<Channel side */
+#define SPI_SR_UDR 0x00000008U /*!<Underrun flag */
+#define SPI_SR_CRCERR 0x00000010U /*!<CRC Error flag */
+#define SPI_SR_MODF 0x00000020U /*!<Mode fault */
+#define SPI_SR_OVR 0x00000040U /*!<Overrun flag */
+#define SPI_SR_BSY 0x00000080U /*!<Busy flag */
+#define SPI_SR_FRE 0x00000100U /*!<Frame format error flag */
+
+/******************** Bit definition for SPI_DR register ********************/
+#define SPI_DR_DR 0x0000FFFFU /*!<Data Register */
+
+/******************* Bit definition for SPI_CRCPR register ******************/
+#define SPI_CRCPR_CRCPOLY 0x0000FFFFU /*!<CRC polynomial register */
+
+/****************** Bit definition for SPI_RXCRCR register ******************/
+#define SPI_RXCRCR_RXCRC 0x0000FFFFU /*!<Rx CRC Register */
+
+/****************** Bit definition for SPI_TXCRCR register ******************/
+#define SPI_TXCRCR_TXCRC 0x0000FFFFU /*!<Tx CRC Register */
+
+/****************** Bit definition for SPI_I2SCFGR register *****************/
+#define SPI_I2SCFGR_CHLEN 0x00000001U /*!<Channel length (number of bits per audio channel) */
+
+#define SPI_I2SCFGR_DATLEN 0x00000006U /*!<DATLEN[1:0] bits (Data length to be transferred) */
+#define SPI_I2SCFGR_DATLEN_0 0x00000002U /*!<Bit 0 */
+#define SPI_I2SCFGR_DATLEN_1 0x00000004U /*!<Bit 1 */
+
+#define SPI_I2SCFGR_CKPOL 0x00000008U /*!<steady state clock polarity */
+
+#define SPI_I2SCFGR_I2SSTD 0x00000030U /*!<I2SSTD[1:0] bits (I2S standard selection) */
+#define SPI_I2SCFGR_I2SSTD_0 0x00000010U /*!<Bit 0 */
+#define SPI_I2SCFGR_I2SSTD_1 0x00000020U /*!<Bit 1 */
+
+#define SPI_I2SCFGR_PCMSYNC 0x00000080U /*!<PCM frame synchronization */
+
+#define SPI_I2SCFGR_I2SCFG 0x00000300U /*!<I2SCFG[1:0] bits (I2S configuration mode) */
+#define SPI_I2SCFGR_I2SCFG_0 0x00000100U /*!<Bit 0 */
+#define SPI_I2SCFGR_I2SCFG_1 0x00000200U /*!<Bit 1 */
+
+#define SPI_I2SCFGR_I2SE 0x00000400U /*!<I2S Enable */
+#define SPI_I2SCFGR_I2SMOD 0x00000800U /*!<I2S mode selection */
+#define SPI_I2SCFGR_ASTRTEN 0x00001000U /*!<Asynchronous start enable */
+
+/****************** Bit definition for SPI_I2SPR register *******************/
+#define SPI_I2SPR_I2SDIV 0x000000FFU /*!<I2S Linear prescaler */
+#define SPI_I2SPR_ODD 0x00000100U /*!<Odd factor for the prescaler */
+#define SPI_I2SPR_MCKOE 0x00000200U /*!<Master Clock Output Enable */
+
+/******************************************************************************/
+/* */
+/* SYSCFG */
+/* */
+/******************************************************************************/
+/****************** Bit definition for SYSCFG_MEMRMP register ***************/
+#define SYSCFG_MEMRMP_MEM_MODE 0x00000007U /*!< SYSCFG_Memory Remap Config */
+#define SYSCFG_MEMRMP_MEM_MODE_0 0x00000001U
+#define SYSCFG_MEMRMP_MEM_MODE_1 0x00000002U
+#define SYSCFG_MEMRMP_MEM_MODE_2 0x00000004U
+
+#define SYSCFG_MEMRMP_UFB_MODE 0x00000100U /*!< User Flash Bank mode */
+#define SYSCFG_SWP_FMC 0x00000C00U /*!< FMC memory mapping swap */
+
+/****************** Bit definition for SYSCFG_PMC register ******************/
+#define SYSCFG_PMC_ADCxDC2 0x00070000U /*!< Refer to AN4073 on how to use this bit */
+#define SYSCFG_PMC_ADC1DC2 0x00010000U /*!< Refer to AN4073 on how to use this bit */
+#define SYSCFG_PMC_ADC2DC2 0x00020000U /*!< Refer to AN4073 on how to use this bit */
+#define SYSCFG_PMC_ADC3DC2 0x00040000U /*!< Refer to AN4073 on how to use this bit */
+
+#define SYSCFG_PMC_MII_RMII_SEL 0x00800000U /*!<Ethernet PHY interface selection */
+
+/***************** Bit definition for SYSCFG_EXTICR1 register ***************/
+#define SYSCFG_EXTICR1_EXTI0 0x000FU /*!<EXTI 0 configuration */
+#define SYSCFG_EXTICR1_EXTI1 0x00F0U /*!<EXTI 1 configuration */
+#define SYSCFG_EXTICR1_EXTI2 0x0F00U /*!<EXTI 2 configuration */
+#define SYSCFG_EXTICR1_EXTI3 0xF000U /*!<EXTI 3 configuration */
+/**
+ * @brief EXTI0 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI0_PA 0x0000U /*!<PA[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PB 0x0001U /*!<PB[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PC 0x0002U /*!<PC[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PD 0x0003U /*!<PD[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PE 0x0004U /*!<PE[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PF 0x0005U /*!<PF[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PG 0x0006U /*!<PG[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PH 0x0007U /*!<PH[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PI 0x0008U /*!<PI[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PJ 0x0009U /*!<PJ[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PK 0x000AU /*!<PK[0] pin */
+
+/**
+ * @brief EXTI1 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI1_PA 0x0000U /*!<PA[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PB 0x0010U /*!<PB[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PC 0x0020U /*!<PC[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PD 0x0030U /*!<PD[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PE 0x0040U /*!<PE[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PF 0x0050U /*!<PF[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PG 0x0060U /*!<PG[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PH 0x0070U /*!<PH[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PI 0x0080U /*!<PI[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PJ 0x0090U /*!<PJ[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PK 0x00A0U /*!<PK[1] pin */
+
+
+/**
+ * @brief EXTI2 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI2_PA 0x0000U /*!<PA[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PB 0x0100U /*!<PB[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PC 0x0200U /*!<PC[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PD 0x0300U /*!<PD[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PE 0x0400U /*!<PE[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PF 0x0500U /*!<PF[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PG 0x0600U /*!<PG[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PH 0x0700U /*!<PH[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PI 0x0800U /*!<PI[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PJ 0x0900U /*!<PJ[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PK 0x0A00U /*!<PK[2] pin */
+
+
+/**
+ * @brief EXTI3 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI3_PA 0x0000U /*!<PA[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PB 0x1000U /*!<PB[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PC 0x2000U /*!<PC[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PD 0x3000U /*!<PD[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PE 0x4000U /*!<PE[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PF 0x5000U /*!<PF[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PG 0x6000U /*!<PG[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PH 0x7000U /*!<PH[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PI 0x8000U /*!<PI[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PJ 0x9000U /*!<PJ[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PK 0xA000U /*!<PK[3] pin */
+
+
+/***************** Bit definition for SYSCFG_EXTICR2 register ***************/
+#define SYSCFG_EXTICR2_EXTI4 0x000FU /*!<EXTI 4 configuration */
+#define SYSCFG_EXTICR2_EXTI5 0x00F0U /*!<EXTI 5 configuration */
+#define SYSCFG_EXTICR2_EXTI6 0x0F00U /*!<EXTI 6 configuration */
+#define SYSCFG_EXTICR2_EXTI7 0xF000U /*!<EXTI 7 configuration */
+/**
+ * @brief EXTI4 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI4_PA 0x0000U /*!<PA[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PB 0x0001U /*!<PB[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PC 0x0002U /*!<PC[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PD 0x0003U /*!<PD[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PE 0x0004U /*!<PE[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PF 0x0005U /*!<PF[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PG 0x0006U /*!<PG[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PH 0x0007U /*!<PH[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PI 0x0008U /*!<PI[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PJ 0x0009U /*!<PJ[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PK 0x000AU /*!<PK[4] pin */
+
+/**
+ * @brief EXTI5 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI5_PA 0x0000U /*!<PA[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PB 0x0010U /*!<PB[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PC 0x0020U /*!<PC[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PD 0x0030U /*!<PD[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PE 0x0040U /*!<PE[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PF 0x0050U /*!<PF[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PG 0x0060U /*!<PG[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PH 0x0070U /*!<PH[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PI 0x0080U /*!<PI[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PJ 0x0090U /*!<PJ[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PK 0x00A0U /*!<PK[5] pin */
+
+/**
+ * @brief EXTI6 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI6_PA 0x0000U /*!<PA[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PB 0x0100U /*!<PB[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PC 0x0200U /*!<PC[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PD 0x0300U /*!<PD[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PE 0x0400U /*!<PE[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PF 0x0500U /*!<PF[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PG 0x0600U /*!<PG[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PH 0x0700U /*!<PH[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PI 0x0800U /*!<PI[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PJ 0x0900U /*!<PJ[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PK 0x0A00U /*!<PK[6] pin */
+
+
+/**
+ * @brief EXTI7 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI7_PA 0x0000U /*!<PA[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PB 0x1000U /*!<PB[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PC 0x2000U /*!<PC[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PD 0x3000U /*!<PD[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PE 0x4000U /*!<PE[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PF 0x5000U /*!<PF[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PG 0x6000U /*!<PG[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PH 0x7000U /*!<PH[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PI 0x8000U /*!<PI[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PJ 0x9000U /*!<PJ[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PK 0xA000U /*!<PK[7] pin */
+
+/***************** Bit definition for SYSCFG_EXTICR3 register ***************/
+#define SYSCFG_EXTICR3_EXTI8 0x000FU /*!<EXTI 8 configuration */
+#define SYSCFG_EXTICR3_EXTI9 0x00F0U /*!<EXTI 9 configuration */
+#define SYSCFG_EXTICR3_EXTI10 0x0F00U /*!<EXTI 10 configuration */
+#define SYSCFG_EXTICR3_EXTI11 0xF000U /*!<EXTI 11 configuration */
+
+/**
+ * @brief EXTI8 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI8_PA 0x0000U /*!<PA[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PB 0x0001U /*!<PB[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PC 0x0002U /*!<PC[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PD 0x0003U /*!<PD[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PE 0x0004U /*!<PE[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PF 0x0005U /*!<PF[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PG 0x0006U /*!<PG[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PH 0x0007U /*!<PH[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PI 0x0008U /*!<PI[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PJ 0x0009U /*!<PJ[8] pin */
+
+/**
+ * @brief EXTI9 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI9_PA 0x0000U /*!<PA[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PB 0x0010U /*!<PB[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PC 0x0020U /*!<PC[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PD 0x0030U /*!<PD[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PE 0x0040U /*!<PE[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PF 0x0050U /*!<PF[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PG 0x0060U /*!<PG[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PH 0x0070U /*!<PH[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PI 0x0080U /*!<PI[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PJ 0x0090U /*!<PJ[9] pin */
+
+
+/**
+ * @brief EXTI10 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI10_PA 0x0000U /*!<PA[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PB 0x0100U /*!<PB[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PC 0x0200U /*!<PC[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PD 0x0300U /*!<PD[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PE 0x0400U /*!<PE[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PF 0x0500U /*!<PF[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PG 0x0600U /*!<PG[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PH 0x0700U /*!<PH[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PI 0x0800U /*!<PI[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PJ 0x0900U /*!<PJ[10] pin */
+
+
+/**
+ * @brief EXTI11 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI11_PA 0x0000U /*!<PA[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PB 0x1000U /*!<PB[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PC 0x2000U /*!<PC[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PD 0x3000U /*!<PD[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PE 0x4000U /*!<PE[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PF 0x5000U /*!<PF[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PG 0x6000U /*!<PG[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PH 0x7000U /*!<PH[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PI 0x8000U /*!<PI[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PJ 0x9000U /*!<PJ[11] pin */
+
+
+/***************** Bit definition for SYSCFG_EXTICR4 register ***************/
+#define SYSCFG_EXTICR4_EXTI12 0x000FU /*!<EXTI 12 configuration */
+#define SYSCFG_EXTICR4_EXTI13 0x00F0U /*!<EXTI 13 configuration */
+#define SYSCFG_EXTICR4_EXTI14 0x0F00U /*!<EXTI 14 configuration */
+#define SYSCFG_EXTICR4_EXTI15 0xF000U /*!<EXTI 15 configuration */
+/**
+ * @brief EXTI12 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI12_PA 0x0000U /*!<PA[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PB 0x0001U /*!<PB[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PC 0x0002U /*!<PC[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PD 0x0003U /*!<PD[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PE 0x0004U /*!<PE[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PF 0x0005U /*!<PF[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PG 0x0006U /*!<PG[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PH 0x0007U /*!<PH[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PI 0x0008U /*!<PI[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PJ 0x0009U /*!<PJ[12] pin */
+
+
+/**
+ * @brief EXTI13 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI13_PA 0x0000U /*!<PA[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PB 0x0010U /*!<PB[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PC 0x0020U /*!<PC[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PD 0x0030U /*!<PD[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PE 0x0040U /*!<PE[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PF 0x0050U /*!<PF[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PG 0x0060U /*!<PG[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PH 0x0070U /*!<PH[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PI 0x0008U /*!<PI[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PJ 0x0009U /*!<PJ[13] pin */
+
+
+/**
+ * @brief EXTI14 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI14_PA 0x0000U /*!<PA[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PB 0x0100U /*!<PB[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PC 0x0200U /*!<PC[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PD 0x0300U /*!<PD[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PE 0x0400U /*!<PE[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PF 0x0500U /*!<PF[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PG 0x0600U /*!<PG[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PH 0x0700U /*!<PH[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PI 0x0800U /*!<PI[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PJ 0x0900U /*!<PJ[14] pin */
+
+
+/**
+ * @brief EXTI15 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI15_PA 0x0000U /*!<PA[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PB 0x1000U /*!<PB[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PC 0x2000U /*!<PC[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PD 0x3000U /*!<PD[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PE 0x4000U /*!<PE[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PF 0x5000U /*!<PF[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PG 0x6000U /*!<PG[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PH 0x7000U /*!<PH[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PI 0x8000U /*!<PI[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PJ 0x9000U /*!<PJ[15] pin */
+
+/****************** Bit definition for SYSCFG_CMPCR register ****************/
+#define SYSCFG_CMPCR_CMP_PD 0x00000001U /*!<Compensation cell ready flag */
+#define SYSCFG_CMPCR_READY 0x00000100U /*!<Compensation cell power-down */
+
+/******************************************************************************/
+/* */
+/* TIM */
+/* */
+/******************************************************************************/
+/******************* Bit definition for TIM_CR1 register ********************/
+#define TIM_CR1_CEN 0x0001U /*!<Counter enable */
+#define TIM_CR1_UDIS 0x0002U /*!<Update disable */
+#define TIM_CR1_URS 0x0004U /*!<Update request source */
+#define TIM_CR1_OPM 0x0008U /*!<One pulse mode */
+#define TIM_CR1_DIR 0x0010U /*!<Direction */
+
+#define TIM_CR1_CMS 0x0060U /*!<CMS[1:0] bits (Center-aligned mode selection) */
+#define TIM_CR1_CMS_0 0x0020U /*!<Bit 0 */
+#define TIM_CR1_CMS_1 0x0040U /*!<Bit 1 */
+
+#define TIM_CR1_ARPE 0x0080U /*!<Auto-reload preload enable */
+
+#define TIM_CR1_CKD 0x0300U /*!<CKD[1:0] bits (clock division) */
+#define TIM_CR1_CKD_0 0x0100U /*!<Bit 0 */
+#define TIM_CR1_CKD_1 0x0200U /*!<Bit 1 */
+
+/******************* Bit definition for TIM_CR2 register ********************/
+#define TIM_CR2_CCPC 0x0001U /*!<Capture/Compare Preloaded Control */
+#define TIM_CR2_CCUS 0x0004U /*!<Capture/Compare Control Update Selection */
+#define TIM_CR2_CCDS 0x0008U /*!<Capture/Compare DMA Selection */
+
+#define TIM_CR2_MMS 0x0070U /*!<MMS[2:0] bits (Master Mode Selection) */
+#define TIM_CR2_MMS_0 0x0010U /*!<Bit 0 */
+#define TIM_CR2_MMS_1 0x0020U /*!<Bit 1 */
+#define TIM_CR2_MMS_2 0x0040U /*!<Bit 2 */
+
+#define TIM_CR2_TI1S 0x0080U /*!<TI1 Selection */
+#define TIM_CR2_OIS1 0x0100U /*!<Output Idle state 1 (OC1 output) */
+#define TIM_CR2_OIS1N 0x0200U /*!<Output Idle state 1 (OC1N output) */
+#define TIM_CR2_OIS2 0x0400U /*!<Output Idle state 2 (OC2 output) */
+#define TIM_CR2_OIS2N 0x0800U /*!<Output Idle state 2 (OC2N output) */
+#define TIM_CR2_OIS3 0x1000U /*!<Output Idle state 3 (OC3 output) */
+#define TIM_CR2_OIS3N 0x2000U /*!<Output Idle state 3 (OC3N output) */
+#define TIM_CR2_OIS4 0x4000U /*!<Output Idle state 4 (OC4 output) */
+
+/******************* Bit definition for TIM_SMCR register *******************/
+#define TIM_SMCR_SMS 0x0007U /*!<SMS[2:0] bits (Slave mode selection) */
+#define TIM_SMCR_SMS_0 0x0001U /*!<Bit 0 */
+#define TIM_SMCR_SMS_1 0x0002U /*!<Bit 1 */
+#define TIM_SMCR_SMS_2 0x0004U /*!<Bit 2 */
+
+#define TIM_SMCR_TS 0x0070U /*!<TS[2:0] bits (Trigger selection) */
+#define TIM_SMCR_TS_0 0x0010U /*!<Bit 0 */
+#define TIM_SMCR_TS_1 0x0020U /*!<Bit 1 */
+#define TIM_SMCR_TS_2 0x0040U /*!<Bit 2 */
+
+#define TIM_SMCR_MSM 0x0080U /*!<Master/slave mode */
+
+#define TIM_SMCR_ETF 0x0F00U /*!<ETF[3:0] bits (External trigger filter) */
+#define TIM_SMCR_ETF_0 0x0100U /*!<Bit 0 */
+#define TIM_SMCR_ETF_1 0x0200U /*!<Bit 1 */
+#define TIM_SMCR_ETF_2 0x0400U /*!<Bit 2 */
+#define TIM_SMCR_ETF_3 0x0800U /*!<Bit 3 */
+
+#define TIM_SMCR_ETPS 0x3000U /*!<ETPS[1:0] bits (External trigger prescaler) */
+#define TIM_SMCR_ETPS_0 0x1000U /*!<Bit 0 */
+#define TIM_SMCR_ETPS_1 0x2000U /*!<Bit 1 */
+
+#define TIM_SMCR_ECE 0x4000U /*!<External clock enable */
+#define TIM_SMCR_ETP 0x8000U /*!<External trigger polarity */
+
+/******************* Bit definition for TIM_DIER register *******************/
+#define TIM_DIER_UIE 0x0001U /*!<Update interrupt enable */
+#define TIM_DIER_CC1IE 0x0002U /*!<Capture/Compare 1 interrupt enable */
+#define TIM_DIER_CC2IE 0x0004U /*!<Capture/Compare 2 interrupt enable */
+#define TIM_DIER_CC3IE 0x0008U /*!<Capture/Compare 3 interrupt enable */
+#define TIM_DIER_CC4IE 0x0010U /*!<Capture/Compare 4 interrupt enable */
+#define TIM_DIER_COMIE 0x0020U /*!<COM interrupt enable */
+#define TIM_DIER_TIE 0x0040U /*!<Trigger interrupt enable */
+#define TIM_DIER_BIE 0x0080U /*!<Break interrupt enable */
+#define TIM_DIER_UDE 0x0100U /*!<Update DMA request enable */
+#define TIM_DIER_CC1DE 0x0200U /*!<Capture/Compare 1 DMA request enable */
+#define TIM_DIER_CC2DE 0x0400U /*!<Capture/Compare 2 DMA request enable */
+#define TIM_DIER_CC3DE 0x0800U /*!<Capture/Compare 3 DMA request enable */
+#define TIM_DIER_CC4DE 0x1000U /*!<Capture/Compare 4 DMA request enable */
+#define TIM_DIER_COMDE 0x2000U /*!<COM DMA request enable */
+#define TIM_DIER_TDE 0x4000U /*!<Trigger DMA request enable */
+
+/******************** Bit definition for TIM_SR register ********************/
+#define TIM_SR_UIF 0x0001U /*!<Update interrupt Flag */
+#define TIM_SR_CC1IF 0x0002U /*!<Capture/Compare 1 interrupt Flag */
+#define TIM_SR_CC2IF 0x0004U /*!<Capture/Compare 2 interrupt Flag */
+#define TIM_SR_CC3IF 0x0008U /*!<Capture/Compare 3 interrupt Flag */
+#define TIM_SR_CC4IF 0x0010U /*!<Capture/Compare 4 interrupt Flag */
+#define TIM_SR_COMIF 0x0020U /*!<COM interrupt Flag */
+#define TIM_SR_TIF 0x0040U /*!<Trigger interrupt Flag */
+#define TIM_SR_BIF 0x0080U /*!<Break interrupt Flag */
+#define TIM_SR_CC1OF 0x0200U /*!<Capture/Compare 1 Overcapture Flag */
+#define TIM_SR_CC2OF 0x0400U /*!<Capture/Compare 2 Overcapture Flag */
+#define TIM_SR_CC3OF 0x0800U /*!<Capture/Compare 3 Overcapture Flag */
+#define TIM_SR_CC4OF 0x1000U /*!<Capture/Compare 4 Overcapture Flag */
+
+/******************* Bit definition for TIM_EGR register ********************/
+#define TIM_EGR_UG 0x01U /*!<Update Generation */
+#define TIM_EGR_CC1G 0x02U /*!<Capture/Compare 1 Generation */
+#define TIM_EGR_CC2G 0x04U /*!<Capture/Compare 2 Generation */
+#define TIM_EGR_CC3G 0x08U /*!<Capture/Compare 3 Generation */
+#define TIM_EGR_CC4G 0x10U /*!<Capture/Compare 4 Generation */
+#define TIM_EGR_COMG 0x20U /*!<Capture/Compare Control Update Generation */
+#define TIM_EGR_TG 0x40U /*!<Trigger Generation */
+#define TIM_EGR_BG 0x80U /*!<Break Generation */
+
+/****************** Bit definition for TIM_CCMR1 register *******************/
+#define TIM_CCMR1_CC1S 0x0003U /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
+#define TIM_CCMR1_CC1S_0 0x0001U /*!<Bit 0 */
+#define TIM_CCMR1_CC1S_1 0x0002U /*!<Bit 1 */
+
+#define TIM_CCMR1_OC1FE 0x0004U /*!<Output Compare 1 Fast enable */
+#define TIM_CCMR1_OC1PE 0x0008U /*!<Output Compare 1 Preload enable */
+
+#define TIM_CCMR1_OC1M 0x0070U /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
+#define TIM_CCMR1_OC1M_0 0x0010U /*!<Bit 0 */
+#define TIM_CCMR1_OC1M_1 0x0020U /*!<Bit 1 */
+#define TIM_CCMR1_OC1M_2 0x0040U /*!<Bit 2 */
+
+#define TIM_CCMR1_OC1CE 0x0080U /*!<Output Compare 1Clear Enable */
+
+#define TIM_CCMR1_CC2S 0x0300U /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
+#define TIM_CCMR1_CC2S_0 0x0100U /*!<Bit 0 */
+#define TIM_CCMR1_CC2S_1 0x0200U /*!<Bit 1 */
+
+#define TIM_CCMR1_OC2FE 0x0400U /*!<Output Compare 2 Fast enable */
+#define TIM_CCMR1_OC2PE 0x0800U /*!<Output Compare 2 Preload enable */
+
+#define TIM_CCMR1_OC2M 0x7000U /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
+#define TIM_CCMR1_OC2M_0 0x1000U /*!<Bit 0 */
+#define TIM_CCMR1_OC2M_1 0x2000U /*!<Bit 1 */
+#define TIM_CCMR1_OC2M_2 0x4000U /*!<Bit 2 */
+
+#define TIM_CCMR1_OC2CE 0x8000U /*!<Output Compare 2 Clear Enable */
+
+/*----------------------------------------------------------------------------*/
+
+#define TIM_CCMR1_IC1PSC 0x000CU /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
+#define TIM_CCMR1_IC1PSC_0 0x0004U /*!<Bit 0 */
+#define TIM_CCMR1_IC1PSC_1 0x0008U /*!<Bit 1 */
+
+#define TIM_CCMR1_IC1F 0x00F0U /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
+#define TIM_CCMR1_IC1F_0 0x0010U /*!<Bit 0 */
+#define TIM_CCMR1_IC1F_1 0x0020U /*!<Bit 1 */
+#define TIM_CCMR1_IC1F_2 0x0040U /*!<Bit 2 */
+#define TIM_CCMR1_IC1F_3 0x0080U /*!<Bit 3 */
+
+#define TIM_CCMR1_IC2PSC 0x0C00U /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
+#define TIM_CCMR1_IC2PSC_0 0x0400U /*!<Bit 0 */
+#define TIM_CCMR1_IC2PSC_1 0x0800U /*!<Bit 1 */
+
+#define TIM_CCMR1_IC2F 0xF000U /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
+#define TIM_CCMR1_IC2F_0 0x1000U /*!<Bit 0 */
+#define TIM_CCMR1_IC2F_1 0x2000U /*!<Bit 1 */
+#define TIM_CCMR1_IC2F_2 0x4000U /*!<Bit 2 */
+#define TIM_CCMR1_IC2F_3 0x8000U /*!<Bit 3 */
+
+/****************** Bit definition for TIM_CCMR2 register *******************/
+#define TIM_CCMR2_CC3S 0x0003U /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
+#define TIM_CCMR2_CC3S_0 0x0001U /*!<Bit 0 */
+#define TIM_CCMR2_CC3S_1 0x0002U /*!<Bit 1 */
+
+#define TIM_CCMR2_OC3FE 0x0004U /*!<Output Compare 3 Fast enable */
+#define TIM_CCMR2_OC3PE 0x0008U /*!<Output Compare 3 Preload enable */
+
+#define TIM_CCMR2_OC3M 0x0070U /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
+#define TIM_CCMR2_OC3M_0 0x0010U /*!<Bit 0 */
+#define TIM_CCMR2_OC3M_1 0x0020U /*!<Bit 1 */
+#define TIM_CCMR2_OC3M_2 0x0040U /*!<Bit 2 */
+
+#define TIM_CCMR2_OC3CE 0x0080U /*!<Output Compare 3 Clear Enable */
+
+#define TIM_CCMR2_CC4S 0x0300U /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
+#define TIM_CCMR2_CC4S_0 0x0100U /*!<Bit 0 */
+#define TIM_CCMR2_CC4S_1 0x0200U /*!<Bit 1 */
+
+#define TIM_CCMR2_OC4FE 0x0400U /*!<Output Compare 4 Fast enable */
+#define TIM_CCMR2_OC4PE 0x0800U /*!<Output Compare 4 Preload enable */
+
+#define TIM_CCMR2_OC4M 0x7000U /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
+#define TIM_CCMR2_OC4M_0 0x1000U /*!<Bit 0 */
+#define TIM_CCMR2_OC4M_1 0x2000U /*!<Bit 1 */
+#define TIM_CCMR2_OC4M_2 0x4000U /*!<Bit 2 */
+
+#define TIM_CCMR2_OC4CE 0x8000U /*!<Output Compare 4 Clear Enable */
+
+/*----------------------------------------------------------------------------*/
+
+#define TIM_CCMR2_IC3PSC 0x000CU /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
+#define TIM_CCMR2_IC3PSC_0 0x0004U /*!<Bit 0 */
+#define TIM_CCMR2_IC3PSC_1 0x0008U /*!<Bit 1 */
+
+#define TIM_CCMR2_IC3F 0x00F0U /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
+#define TIM_CCMR2_IC3F_0 0x0010U /*!<Bit 0 */
+#define TIM_CCMR2_IC3F_1 0x0020U /*!<Bit 1 */
+#define TIM_CCMR2_IC3F_2 0x0040U /*!<Bit 2 */
+#define TIM_CCMR2_IC3F_3 0x0080U /*!<Bit 3 */
+
+#define TIM_CCMR2_IC4PSC 0x0C00U /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
+#define TIM_CCMR2_IC4PSC_0 0x0400U /*!<Bit 0 */
+#define TIM_CCMR2_IC4PSC_1 0x0800U /*!<Bit 1 */
+
+#define TIM_CCMR2_IC4F 0xF000U /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
+#define TIM_CCMR2_IC4F_0 0x1000U /*!<Bit 0 */
+#define TIM_CCMR2_IC4F_1 0x2000U /*!<Bit 1 */
+#define TIM_CCMR2_IC4F_2 0x4000U /*!<Bit 2 */
+#define TIM_CCMR2_IC4F_3 0x8000U /*!<Bit 3 */
+
+/******************* Bit definition for TIM_CCER register *******************/
+#define TIM_CCER_CC1E 0x0001U /*!<Capture/Compare 1 output enable */
+#define TIM_CCER_CC1P 0x0002U /*!<Capture/Compare 1 output Polarity */
+#define TIM_CCER_CC1NE 0x0004U /*!<Capture/Compare 1 Complementary output enable */
+#define TIM_CCER_CC1NP 0x0008U /*!<Capture/Compare 1 Complementary output Polarity */
+#define TIM_CCER_CC2E 0x0010U /*!<Capture/Compare 2 output enable */
+#define TIM_CCER_CC2P 0x0020U /*!<Capture/Compare 2 output Polarity */
+#define TIM_CCER_CC2NE 0x0040U /*!<Capture/Compare 2 Complementary output enable */
+#define TIM_CCER_CC2NP 0x0080U /*!<Capture/Compare 2 Complementary output Polarity */
+#define TIM_CCER_CC3E 0x0100U /*!<Capture/Compare 3 output enable */
+#define TIM_CCER_CC3P 0x0200U /*!<Capture/Compare 3 output Polarity */
+#define TIM_CCER_CC3NE 0x0400U /*!<Capture/Compare 3 Complementary output enable */
+#define TIM_CCER_CC3NP 0x0800U /*!<Capture/Compare 3 Complementary output Polarity */
+#define TIM_CCER_CC4E 0x1000U /*!<Capture/Compare 4 output enable */
+#define TIM_CCER_CC4P 0x2000U /*!<Capture/Compare 4 output Polarity */
+#define TIM_CCER_CC4NP 0x8000U /*!<Capture/Compare 4 Complementary output Polarity */
+
+/******************* Bit definition for TIM_CNT register ********************/
+#define TIM_CNT_CNT 0xFFFFU /*!<Counter Value */
+
+/******************* Bit definition for TIM_PSC register ********************/
+#define TIM_PSC_PSC 0xFFFFU /*!<Prescaler Value */
+
+/******************* Bit definition for TIM_ARR register ********************/
+#define TIM_ARR_ARR 0xFFFFU /*!<actual auto-reload Value */
+
+/******************* Bit definition for TIM_RCR register ********************/
+#define TIM_RCR_REP 0xFFU /*!<Repetition Counter Value */
+
+/******************* Bit definition for TIM_CCR1 register *******************/
+#define TIM_CCR1_CCR1 0xFFFFU /*!<Capture/Compare 1 Value */
+
+/******************* Bit definition for TIM_CCR2 register *******************/
+#define TIM_CCR2_CCR2 0xFFFFU /*!<Capture/Compare 2 Value */
+
+/******************* Bit definition for TIM_CCR3 register *******************/
+#define TIM_CCR3_CCR3 0xFFFFU /*!<Capture/Compare 3 Value */
+
+/******************* Bit definition for TIM_CCR4 register *******************/
+#define TIM_CCR4_CCR4 0xFFFFU /*!<Capture/Compare 4 Value */
+
+/******************* Bit definition for TIM_BDTR register *******************/
+#define TIM_BDTR_DTG 0x00FFU /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
+#define TIM_BDTR_DTG_0 0x0001U /*!<Bit 0 */
+#define TIM_BDTR_DTG_1 0x0002U /*!<Bit 1 */
+#define TIM_BDTR_DTG_2 0x0004U /*!<Bit 2 */
+#define TIM_BDTR_DTG_3 0x0008U /*!<Bit 3 */
+#define TIM_BDTR_DTG_4 0x0010U /*!<Bit 4 */
+#define TIM_BDTR_DTG_5 0x0020U /*!<Bit 5 */
+#define TIM_BDTR_DTG_6 0x0040U /*!<Bit 6 */
+#define TIM_BDTR_DTG_7 0x0080U /*!<Bit 7 */
+
+#define TIM_BDTR_LOCK 0x0300U /*!<LOCK[1:0] bits (Lock Configuration) */
+#define TIM_BDTR_LOCK_0 0x0100U /*!<Bit 0 */
+#define TIM_BDTR_LOCK_1 0x0200U /*!<Bit 1 */
+
+#define TIM_BDTR_OSSI 0x0400U /*!<Off-State Selection for Idle mode */
+#define TIM_BDTR_OSSR 0x0800U /*!<Off-State Selection for Run mode */
+#define TIM_BDTR_BKE 0x1000U /*!<Break enable */
+#define TIM_BDTR_BKP 0x2000U /*!<Break Polarity */
+#define TIM_BDTR_AOE 0x4000U /*!<Automatic Output enable */
+#define TIM_BDTR_MOE 0x8000U /*!<Main Output enable */
+
+/******************* Bit definition for TIM_DCR register ********************/
+#define TIM_DCR_DBA 0x001FU /*!<DBA[4:0] bits (DMA Base Address) */
+#define TIM_DCR_DBA_0 0x0001U /*!<Bit 0 */
+#define TIM_DCR_DBA_1 0x0002U /*!<Bit 1 */
+#define TIM_DCR_DBA_2 0x0004U /*!<Bit 2 */
+#define TIM_DCR_DBA_3 0x0008U /*!<Bit 3 */
+#define TIM_DCR_DBA_4 0x0010U /*!<Bit 4 */
+
+#define TIM_DCR_DBL 0x1F00U /*!<DBL[4:0] bits (DMA Burst Length) */
+#define TIM_DCR_DBL_0 0x0100U /*!<Bit 0 */
+#define TIM_DCR_DBL_1 0x0200U /*!<Bit 1 */
+#define TIM_DCR_DBL_2 0x0400U /*!<Bit 2 */
+#define TIM_DCR_DBL_3 0x0800U /*!<Bit 3 */
+#define TIM_DCR_DBL_4 0x1000U /*!<Bit 4 */
+
+/******************* Bit definition for TIM_DMAR register *******************/
+#define TIM_DMAR_DMAB 0xFFFFU /*!<DMA register for burst accesses */
+
+/******************* Bit definition for TIM_OR register *********************/
+#define TIM_OR_TI4_RMP 0x00C0U /*!<TI4_RMP[1:0] bits (TIM5 Input 4 remap) */
+#define TIM_OR_TI4_RMP_0 0x0040U /*!<Bit 0 */
+#define TIM_OR_TI4_RMP_1 0x0080U /*!<Bit 1 */
+#define TIM_OR_ITR1_RMP 0x0C00U /*!<ITR1_RMP[1:0] bits (TIM2 Internal trigger 1 remap) */
+#define TIM_OR_ITR1_RMP_0 0x0400U /*!<Bit 0 */
+#define TIM_OR_ITR1_RMP_1 0x0800U /*!<Bit 1 */
+
+
+/******************************************************************************/
+/* */
+/* Universal Synchronous Asynchronous Receiver Transmitter */
+/* */
+/******************************************************************************/
+/******************* Bit definition for USART_SR register *******************/
+#define USART_SR_PE 0x0001U /*!<Parity Error */
+#define USART_SR_FE 0x0002U /*!<Framing Error */
+#define USART_SR_NE 0x0004U /*!<Noise Error Flag */
+#define USART_SR_ORE 0x0008U /*!<OverRun Error */
+#define USART_SR_IDLE 0x0010U /*!<IDLE line detected */
+#define USART_SR_RXNE 0x0020U /*!<Read Data Register Not Empty */
+#define USART_SR_TC 0x0040U /*!<Transmission Complete */
+#define USART_SR_TXE 0x0080U /*!<Transmit Data Register Empty */
+#define USART_SR_LBD 0x0100U /*!<LIN Break Detection Flag */
+#define USART_SR_CTS 0x0200U /*!<CTS Flag */
+
+/******************* Bit definition for USART_DR register *******************/
+#define USART_DR_DR 0x01FFU /*!<Data value */
+
+/****************** Bit definition for USART_BRR register *******************/
+#define USART_BRR_DIV_Fraction 0x000FU /*!<Fraction of USARTDIV */
+#define USART_BRR_DIV_Mantissa 0xFFF0U /*!<Mantissa of USARTDIV */
+
+/****************** Bit definition for USART_CR1 register *******************/
+#define USART_CR1_SBK 0x0001U /*!<Send Break */
+#define USART_CR1_RWU 0x0002U /*!<Receiver wakeup */
+#define USART_CR1_RE 0x0004U /*!<Receiver Enable */
+#define USART_CR1_TE 0x0008U /*!<Transmitter Enable */
+#define USART_CR1_IDLEIE 0x0010U /*!<IDLE Interrupt Enable */
+#define USART_CR1_RXNEIE 0x0020U /*!<RXNE Interrupt Enable */
+#define USART_CR1_TCIE 0x0040U /*!<Transmission Complete Interrupt Enable */
+#define USART_CR1_TXEIE 0x0080U /*!<PE Interrupt Enable */
+#define USART_CR1_PEIE 0x0100U /*!<PE Interrupt Enable */
+#define USART_CR1_PS 0x0200U /*!<Parity Selection */
+#define USART_CR1_PCE 0x0400U /*!<Parity Control Enable */
+#define USART_CR1_WAKE 0x0800U /*!<Wakeup method */
+#define USART_CR1_M 0x1000U /*!<Word length */
+#define USART_CR1_UE 0x2000U /*!<USART Enable */
+#define USART_CR1_OVER8 0x8000U /*!<USART Oversampling by 8 enable */
+
+/****************** Bit definition for USART_CR2 register *******************/
+#define USART_CR2_ADD 0x000FU /*!<Address of the USART node */
+#define USART_CR2_LBDL 0x0020U /*!<LIN Break Detection Length */
+#define USART_CR2_LBDIE 0x0040U /*!<LIN Break Detection Interrupt Enable */
+#define USART_CR2_LBCL 0x0100U /*!<Last Bit Clock pulse */
+#define USART_CR2_CPHA 0x0200U /*!<Clock Phase */
+#define USART_CR2_CPOL 0x0400U /*!<Clock Polarity */
+#define USART_CR2_CLKEN 0x0800U /*!<Clock Enable */
+
+#define USART_CR2_STOP 0x3000U /*!<STOP[1:0] bits (STOP bits) */
+#define USART_CR2_STOP_0 0x1000U /*!<Bit 0 */
+#define USART_CR2_STOP_1 0x2000U /*!<Bit 1 */
+
+#define USART_CR2_LINEN 0x4000U /*!<LIN mode enable */
+
+/****************** Bit definition for USART_CR3 register *******************/
+#define USART_CR3_EIE 0x0001U /*!<Error Interrupt Enable */
+#define USART_CR3_IREN 0x0002U /*!<IrDA mode Enable */
+#define USART_CR3_IRLP 0x0004U /*!<IrDA Low-Power */
+#define USART_CR3_HDSEL 0x0008U /*!<Half-Duplex Selection */
+#define USART_CR3_NACK 0x0010U /*!<Smartcard NACK enable */
+#define USART_CR3_SCEN 0x0020U /*!<Smartcard mode enable */
+#define USART_CR3_DMAR 0x0040U /*!<DMA Enable Receiver */
+#define USART_CR3_DMAT 0x0080U /*!<DMA Enable Transmitter */
+#define USART_CR3_RTSE 0x0100U /*!<RTS Enable */
+#define USART_CR3_CTSE 0x0200U /*!<CTS Enable */
+#define USART_CR3_CTSIE 0x0400U /*!<CTS Interrupt Enable */
+#define USART_CR3_ONEBIT 0x0800U /*!<USART One bit method enable */
+
+/****************** Bit definition for USART_GTPR register ******************/
+#define USART_GTPR_PSC 0x00FFU /*!<PSC[7:0] bits (Prescaler value) */
+#define USART_GTPR_PSC_0 0x0001U /*!<Bit 0 */
+#define USART_GTPR_PSC_1 0x0002U /*!<Bit 1 */
+#define USART_GTPR_PSC_2 0x0004U /*!<Bit 2 */
+#define USART_GTPR_PSC_3 0x0008U /*!<Bit 3 */
+#define USART_GTPR_PSC_4 0x0010U /*!<Bit 4 */
+#define USART_GTPR_PSC_5 0x0020U /*!<Bit 5 */
+#define USART_GTPR_PSC_6 0x0040U /*!<Bit 6 */
+#define USART_GTPR_PSC_7 0x0080U /*!<Bit 7 */
+
+#define USART_GTPR_GT 0xFF00U /*!<Guard time value */
+
+/******************************************************************************/
+/* */
+/* Window WATCHDOG */
+/* */
+/******************************************************************************/
+/******************* Bit definition for WWDG_CR register ********************/
+#define WWDG_CR_T 0x7FU /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
+#define WWDG_CR_T_0 0x01U /*!<Bit 0 */
+#define WWDG_CR_T_1 0x02U /*!<Bit 1 */
+#define WWDG_CR_T_2 0x04U /*!<Bit 2 */
+#define WWDG_CR_T_3 0x08U /*!<Bit 3 */
+#define WWDG_CR_T_4 0x10U /*!<Bit 4 */
+#define WWDG_CR_T_5 0x20U /*!<Bit 5 */
+#define WWDG_CR_T_6 0x40U /*!<Bit 6 */
+/* Legacy defines */
+#define WWDG_CR_T0 WWDG_CR_T_0
+#define WWDG_CR_T1 WWDG_CR_T_1
+#define WWDG_CR_T2 WWDG_CR_T_2
+#define WWDG_CR_T3 WWDG_CR_T_3
+#define WWDG_CR_T4 WWDG_CR_T_4
+#define WWDG_CR_T5 WWDG_CR_T_5
+#define WWDG_CR_T6 WWDG_CR_T_6
+
+#define WWDG_CR_WDGA 0x80U /*!<Activation bit */
+
+/******************* Bit definition for WWDG_CFR register *******************/
+#define WWDG_CFR_W 0x007FU /*!<W[6:0] bits (7-bit window value) */
+#define WWDG_CFR_W_0 0x0001U /*!<Bit 0 */
+#define WWDG_CFR_W_1 0x0002U /*!<Bit 1 */
+#define WWDG_CFR_W_2 0x0004U /*!<Bit 2 */
+#define WWDG_CFR_W_3 0x0008U /*!<Bit 3 */
+#define WWDG_CFR_W_4 0x0010U /*!<Bit 4 */
+#define WWDG_CFR_W_5 0x0020U /*!<Bit 5 */
+#define WWDG_CFR_W_6 0x0040U /*!<Bit 6 */
+/* Legacy defines */
+#define WWDG_CFR_W0 WWDG_CFR_W_0
+#define WWDG_CFR_W1 WWDG_CFR_W_1
+#define WWDG_CFR_W2 WWDG_CFR_W_2
+#define WWDG_CFR_W3 WWDG_CFR_W_3
+#define WWDG_CFR_W4 WWDG_CFR_W_4
+#define WWDG_CFR_W5 WWDG_CFR_W_5
+#define WWDG_CFR_W6 WWDG_CFR_W_6
+
+#define WWDG_CFR_WDGTB 0x0180U /*!<WDGTB[1:0] bits (Timer Base) */
+#define WWDG_CFR_WDGTB_0 0x0080U /*!<Bit 0 */
+#define WWDG_CFR_WDGTB_1 0x0100U /*!<Bit 1 */
+/* Legacy defines */
+#define WWDG_CFR_WDGTB0 WWDG_CFR_WDGTB_0
+#define WWDG_CFR_WDGTB1 WWDG_CFR_WDGTB_1
+
+#define WWDG_CFR_EWI 0x0200U /*!<Early Wakeup Interrupt */
+
+/******************* Bit definition for WWDG_SR register ********************/
+#define WWDG_SR_EWIF 0x01U /*!<Early Wakeup Interrupt Flag */
+
+
+/******************************************************************************/
+/* */
+/* DBG */
+/* */
+/******************************************************************************/
+/******************** Bit definition for DBGMCU_IDCODE register *************/
+#define DBGMCU_IDCODE_DEV_ID 0x00000FFFU
+#define DBGMCU_IDCODE_REV_ID 0xFFFF0000U
+
+/******************** Bit definition for DBGMCU_CR register *****************/
+#define DBGMCU_CR_DBG_SLEEP 0x00000001U
+#define DBGMCU_CR_DBG_STOP 0x00000002U
+#define DBGMCU_CR_DBG_STANDBY 0x00000004U
+#define DBGMCU_CR_TRACE_IOEN 0x00000020U
+
+#define DBGMCU_CR_TRACE_MODE 0x000000C0U
+#define DBGMCU_CR_TRACE_MODE_0 0x00000040U/*!<Bit 0 */
+#define DBGMCU_CR_TRACE_MODE_1 0x00000080U/*!<Bit 1 */
+
+/******************** Bit definition for DBGMCU_APB1_FZ register ************/
+#define DBGMCU_APB1_FZ_DBG_TIM2_STOP 0x00000001U
+#define DBGMCU_APB1_FZ_DBG_TIM3_STOP 0x00000002U
+#define DBGMCU_APB1_FZ_DBG_TIM4_STOP 0x00000004U
+#define DBGMCU_APB1_FZ_DBG_TIM5_STOP 0x00000008U
+#define DBGMCU_APB1_FZ_DBG_TIM6_STOP 0x00000010U
+#define DBGMCU_APB1_FZ_DBG_TIM7_STOP 0x00000020U
+#define DBGMCU_APB1_FZ_DBG_TIM12_STOP 0x00000040U
+#define DBGMCU_APB1_FZ_DBG_TIM13_STOP 0x00000080U
+#define DBGMCU_APB1_FZ_DBG_TIM14_STOP 0x00000100U
+#define DBGMCU_APB1_FZ_DBG_RTC_STOP 0x00000400U
+#define DBGMCU_APB1_FZ_DBG_WWDG_STOP 0x00000800U
+#define DBGMCU_APB1_FZ_DBG_IWDG_STOP 0x00001000U
+#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT 0x00200000U
+#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT 0x00400000U
+#define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT 0x00800000U
+#define DBGMCU_APB1_FZ_DBG_CAN1_STOP 0x02000000U
+#define DBGMCU_APB1_FZ_DBG_CAN2_STOP 0x04000000U
+/* Old IWDGSTOP bit definition, maintained for legacy purpose */
+#define DBGMCU_APB1_FZ_DBG_IWDEG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP
+
+/******************** Bit definition for DBGMCU_APB2_FZ register ************/
+#define DBGMCU_APB2_FZ_DBG_TIM1_STOP 0x00000001U
+#define DBGMCU_APB2_FZ_DBG_TIM8_STOP 0x00000002U
+#define DBGMCU_APB2_FZ_DBG_TIM9_STOP 0x00010000U
+#define DBGMCU_APB2_FZ_DBG_TIM10_STOP 0x00020000U
+#define DBGMCU_APB2_FZ_DBG_TIM11_STOP 0x00040000U
+
+/******************************************************************************/
+/* */
+/* Ethernet MAC Registers bits definitions */
+/* */
+/******************************************************************************/
+/* Bit definition for Ethernet MAC Control Register register */
+#define ETH_MACCR_WD 0x00800000U /* Watchdog disable */
+#define ETH_MACCR_JD 0x00400000U /* Jabber disable */
+#define ETH_MACCR_IFG 0x000E0000U /* Inter-frame gap */
+#define ETH_MACCR_IFG_96Bit 0x00000000U /* Minimum IFG between frames during transmission is 96Bit */
+ #define ETH_MACCR_IFG_88Bit 0x00020000U /* Minimum IFG between frames during transmission is 88Bit */
+ #define ETH_MACCR_IFG_80Bit 0x00040000U /* Minimum IFG between frames during transmission is 80Bit */
+ #define ETH_MACCR_IFG_72Bit 0x00060000U /* Minimum IFG between frames during transmission is 72Bit */
+ #define ETH_MACCR_IFG_64Bit 0x00080000U /* Minimum IFG between frames during transmission is 64Bit */
+ #define ETH_MACCR_IFG_56Bit 0x000A0000U /* Minimum IFG between frames during transmission is 56Bit */
+ #define ETH_MACCR_IFG_48Bit 0x000C0000U /* Minimum IFG between frames during transmission is 48Bit */
+ #define ETH_MACCR_IFG_40Bit 0x000E0000U /* Minimum IFG between frames during transmission is 40Bit */
+#define ETH_MACCR_CSD 0x00010000U /* Carrier sense disable (during transmission) */
+#define ETH_MACCR_FES 0x00004000U /* Fast ethernet speed */
+#define ETH_MACCR_ROD 0x00002000U /* Receive own disable */
+#define ETH_MACCR_LM 0x00001000U /* loopback mode */
+#define ETH_MACCR_DM 0x00000800U /* Duplex mode */
+#define ETH_MACCR_IPCO 0x00000400U /* IP Checksum offload */
+#define ETH_MACCR_RD 0x00000200U /* Retry disable */
+#define ETH_MACCR_APCS 0x00000080U /* Automatic Pad/CRC stripping */
+#define ETH_MACCR_BL 0x00000060U /* Back-off limit: random integer number (r) of slot time delays before rescheduling
+ a transmission attempt during retries after a collision: 0 =< r <2^k */
+ #define ETH_MACCR_BL_10 0x00000000U /* k = min (n, 10) */
+ #define ETH_MACCR_BL_8 0x00000020U /* k = min (n, 8) */
+ #define ETH_MACCR_BL_4 0x00000040U /* k = min (n, 4) */
+ #define ETH_MACCR_BL_1 0x00000060U /* k = min (n, 1) */
+#define ETH_MACCR_DC 0x00000010U /* Defferal check */
+#define ETH_MACCR_TE 0x00000008U /* Transmitter enable */
+#define ETH_MACCR_RE 0x00000004U /* Receiver enable */
+
+/* Bit definition for Ethernet MAC Frame Filter Register */
+#define ETH_MACFFR_RA 0x80000000U /* Receive all */
+#define ETH_MACFFR_HPF 0x00000400U /* Hash or perfect filter */
+#define ETH_MACFFR_SAF 0x00000200U /* Source address filter enable */
+#define ETH_MACFFR_SAIF 0x00000100U /* SA inverse filtering */
+#define ETH_MACFFR_PCF 0x000000C0U /* Pass control frames: 3 cases */
+ #define ETH_MACFFR_PCF_BlockAll 0x00000040U /* MAC filters all control frames from reaching the application */
+ #define ETH_MACFFR_PCF_ForwardAll 0x00000080U /* MAC forwards all control frames to application even if they fail the Address Filter */
+ #define ETH_MACFFR_PCF_ForwardPassedAddrFilter 0x000000C0U /* MAC forwards control frames that pass the Address Filter. */
+#define ETH_MACFFR_BFD 0x00000020U /* Broadcast frame disable */
+#define ETH_MACFFR_PAM 0x00000010U /* Pass all mutlicast */
+#define ETH_MACFFR_DAIF 0x00000008U /* DA Inverse filtering */
+#define ETH_MACFFR_HM 0x00000004U /* Hash multicast */
+#define ETH_MACFFR_HU 0x00000002U /* Hash unicast */
+#define ETH_MACFFR_PM 0x00000001U /* Promiscuous mode */
+
+/* Bit definition for Ethernet MAC Hash Table High Register */
+#define ETH_MACHTHR_HTH 0xFFFFFFFFU /* Hash table high */
+
+/* Bit definition for Ethernet MAC Hash Table Low Register */
+#define ETH_MACHTLR_HTL 0xFFFFFFFFU /* Hash table low */
+
+/* Bit definition for Ethernet MAC MII Address Register */
+#define ETH_MACMIIAR_PA 0x0000F800U /* Physical layer address */
+#define ETH_MACMIIAR_MR 0x000007C0U /* MII register in the selected PHY */
+#define ETH_MACMIIAR_CR 0x0000001CU /* CR clock range: 6 cases */
+ #define ETH_MACMIIAR_CR_Div42 0x00000000U /* HCLK:60-100 MHz; MDC clock= HCLK/42 */
+ #define ETH_MACMIIAR_CR_Div62 0x00000004U /* HCLK:100-150 MHz; MDC clock= HCLK/62 */
+ #define ETH_MACMIIAR_CR_Div16 0x00000008U /* HCLK:20-35 MHz; MDC clock= HCLK/16 */
+ #define ETH_MACMIIAR_CR_Div26 0x0000000CU /* HCLK:35-60 MHz; MDC clock= HCLK/26 */
+ #define ETH_MACMIIAR_CR_Div102 0x00000010U /* HCLK:150-168 MHz; MDC clock= HCLK/102 */
+#define ETH_MACMIIAR_MW 0x00000002U /* MII write */
+#define ETH_MACMIIAR_MB 0x00000001U /* MII busy */
+
+/* Bit definition for Ethernet MAC MII Data Register */
+#define ETH_MACMIIDR_MD 0x0000FFFFU /* MII data: read/write data from/to PHY */
+
+/* Bit definition for Ethernet MAC Flow Control Register */
+#define ETH_MACFCR_PT 0xFFFF0000U /* Pause time */
+#define ETH_MACFCR_ZQPD 0x00000080U /* Zero-quanta pause disable */
+#define ETH_MACFCR_PLT 0x00000030U /* Pause low threshold: 4 cases */
+ #define ETH_MACFCR_PLT_Minus4 0x00000000U /* Pause time minus 4 slot times */
+ #define ETH_MACFCR_PLT_Minus28 0x00000010U /* Pause time minus 28 slot times */
+ #define ETH_MACFCR_PLT_Minus144 0x00000020U /* Pause time minus 144 slot times */
+ #define ETH_MACFCR_PLT_Minus256 0x00000030U /* Pause time minus 256 slot times */
+#define ETH_MACFCR_UPFD 0x00000008U /* Unicast pause frame detect */
+#define ETH_MACFCR_RFCE 0x00000004U /* Receive flow control enable */
+#define ETH_MACFCR_TFCE 0x00000002U /* Transmit flow control enable */
+#define ETH_MACFCR_FCBBPA 0x00000001U /* Flow control busy/backpressure activate */
+
+/* Bit definition for Ethernet MAC VLAN Tag Register */
+#define ETH_MACVLANTR_VLANTC 0x00010000U /* 12-bit VLAN tag comparison */
+#define ETH_MACVLANTR_VLANTI 0x0000FFFFU /* VLAN tag identifier (for receive frames) */
+
+/* Bit definition for Ethernet MAC Remote Wake-UpFrame Filter Register */
+#define ETH_MACRWUFFR_D 0xFFFFFFFFU /* Wake-up frame filter register data */
+/* Eight sequential Writes to this address (offset 0x28) will write all Wake-UpFrame Filter Registers.
+ Eight sequential Reads from this address (offset 0x28) will read all Wake-UpFrame Filter Registers. */
+/* Wake-UpFrame Filter Reg0 : Filter 0 Byte Mask
+ Wake-UpFrame Filter Reg1 : Filter 1 Byte Mask
+ Wake-UpFrame Filter Reg2 : Filter 2 Byte Mask
+ Wake-UpFrame Filter Reg3 : Filter 3 Byte Mask
+ Wake-UpFrame Filter Reg4 : RSVD - Filter3 Command - RSVD - Filter2 Command -
+ RSVD - Filter1 Command - RSVD - Filter0 Command
+ Wake-UpFrame Filter Re5 : Filter3 Offset - Filter2 Offset - Filter1 Offset - Filter0 Offset
+ Wake-UpFrame Filter Re6 : Filter1 CRC16 - Filter0 CRC16
+ Wake-UpFrame Filter Re7 : Filter3 CRC16 - Filter2 CRC16 */
+
+/* Bit definition for Ethernet MAC PMT Control and Status Register */
+#define ETH_MACPMTCSR_WFFRPR 0x80000000U /* Wake-Up Frame Filter Register Pointer Reset */
+#define ETH_MACPMTCSR_GU 0x00000200U /* Global Unicast */
+#define ETH_MACPMTCSR_WFR 0x00000040U /* Wake-Up Frame Received */
+#define ETH_MACPMTCSR_MPR 0x00000020U /* Magic Packet Received */
+#define ETH_MACPMTCSR_WFE 0x00000004U /* Wake-Up Frame Enable */
+#define ETH_MACPMTCSR_MPE 0x00000002U /* Magic Packet Enable */
+#define ETH_MACPMTCSR_PD 0x00000001U /* Power Down */
+
+/* Bit definition for Ethernet MAC Status Register */
+#define ETH_MACSR_TSTS 0x00000200U /* Time stamp trigger status */
+#define ETH_MACSR_MMCTS 0x00000040U /* MMC transmit status */
+#define ETH_MACSR_MMMCRS 0x00000020U /* MMC receive status */
+#define ETH_MACSR_MMCS 0x00000010U /* MMC status */
+#define ETH_MACSR_PMTS 0x00000008U /* PMT status */
+
+/* Bit definition for Ethernet MAC Interrupt Mask Register */
+#define ETH_MACIMR_TSTIM 0x00000200U /* Time stamp trigger interrupt mask */
+#define ETH_MACIMR_PMTIM 0x00000008U /* PMT interrupt mask */
+
+/* Bit definition for Ethernet MAC Address0 High Register */
+#define ETH_MACA0HR_MACA0H 0x0000FFFFU /* MAC address0 high */
+
+/* Bit definition for Ethernet MAC Address0 Low Register */
+#define ETH_MACA0LR_MACA0L 0xFFFFFFFFU /* MAC address0 low */
+
+/* Bit definition for Ethernet MAC Address1 High Register */
+#define ETH_MACA1HR_AE 0x80000000U /* Address enable */
+#define ETH_MACA1HR_SA 0x40000000U /* Source address */
+#define ETH_MACA1HR_MBC 0x3F000000U /* Mask byte control: bits to mask for comparison of the MAC Address bytes */
+ #define ETH_MACA1HR_MBC_HBits15_8 0x20000000U /* Mask MAC Address high reg bits [15:8] */
+ #define ETH_MACA1HR_MBC_HBits7_0 0x10000000U /* Mask MAC Address high reg bits [7:0] */
+ #define ETH_MACA1HR_MBC_LBits31_24 0x08000000U /* Mask MAC Address low reg bits [31:24] */
+ #define ETH_MACA1HR_MBC_LBits23_16 0x04000000U /* Mask MAC Address low reg bits [23:16] */
+ #define ETH_MACA1HR_MBC_LBits15_8 0x02000000U /* Mask MAC Address low reg bits [15:8] */
+ #define ETH_MACA1HR_MBC_LBits7_0 0x01000000U /* Mask MAC Address low reg bits [7:0] */
+#define ETH_MACA1HR_MACA1H 0x0000FFFFU /* MAC address1 high */
+
+/* Bit definition for Ethernet MAC Address1 Low Register */
+#define ETH_MACA1LR_MACA1L 0xFFFFFFFFU /* MAC address1 low */
+
+/* Bit definition for Ethernet MAC Address2 High Register */
+#define ETH_MACA2HR_AE 0x80000000U /* Address enable */
+#define ETH_MACA2HR_SA 0x40000000U /* Source address */
+#define ETH_MACA2HR_MBC 0x3F000000U /* Mask byte control */
+ #define ETH_MACA2HR_MBC_HBits15_8 0x20000000U /* Mask MAC Address high reg bits [15:8] */
+ #define ETH_MACA2HR_MBC_HBits7_0 0x10000000U /* Mask MAC Address high reg bits [7:0] */
+ #define ETH_MACA2HR_MBC_LBits31_24 0x08000000U /* Mask MAC Address low reg bits [31:24] */
+ #define ETH_MACA2HR_MBC_LBits23_16 0x04000000U /* Mask MAC Address low reg bits [23:16] */
+ #define ETH_MACA2HR_MBC_LBits15_8 0x02000000U /* Mask MAC Address low reg bits [15:8] */
+ #define ETH_MACA2HR_MBC_LBits7_0 0x01000000U /* Mask MAC Address low reg bits [70] */
+#define ETH_MACA2HR_MACA2H 0x0000FFFFU /* MAC address1 high */
+
+/* Bit definition for Ethernet MAC Address2 Low Register */
+#define ETH_MACA2LR_MACA2L 0xFFFFFFFFU /* MAC address2 low */
+
+/* Bit definition for Ethernet MAC Address3 High Register */
+#define ETH_MACA3HR_AE 0x80000000U /* Address enable */
+#define ETH_MACA3HR_SA 0x40000000U /* Source address */
+#define ETH_MACA3HR_MBC 0x3F000000U /* Mask byte control */
+ #define ETH_MACA3HR_MBC_HBits15_8 0x20000000U /* Mask MAC Address high reg bits [15:8] */
+ #define ETH_MACA3HR_MBC_HBits7_0 0x10000000U /* Mask MAC Address high reg bits [7:0] */
+ #define ETH_MACA3HR_MBC_LBits31_24 0x08000000U /* Mask MAC Address low reg bits [31:24] */
+ #define ETH_MACA3HR_MBC_LBits23_16 0x04000000U /* Mask MAC Address low reg bits [23:16] */
+ #define ETH_MACA3HR_MBC_LBits15_8 0x02000000U /* Mask MAC Address low reg bits [15:8] */
+ #define ETH_MACA3HR_MBC_LBits7_0 0x01000000U /* Mask MAC Address low reg bits [70] */
+#define ETH_MACA3HR_MACA3H 0x0000FFFFU /* MAC address3 high */
+
+/* Bit definition for Ethernet MAC Address3 Low Register */
+#define ETH_MACA3LR_MACA3L 0xFFFFFFFFU /* MAC address3 low */
+
+/******************************************************************************/
+/* Ethernet MMC Registers bits definition */
+/******************************************************************************/
+
+/* Bit definition for Ethernet MMC Contol Register */
+#define ETH_MMCCR_MCFHP 0x00000020U /* MMC counter Full-Half preset */
+#define ETH_MMCCR_MCP 0x00000010U /* MMC counter preset */
+#define ETH_MMCCR_MCF 0x00000008U /* MMC Counter Freeze */
+#define ETH_MMCCR_ROR 0x00000004U /* Reset on Read */
+#define ETH_MMCCR_CSR 0x00000002U /* Counter Stop Rollover */
+#define ETH_MMCCR_CR 0x00000001U /* Counters Reset */
+
+/* Bit definition for Ethernet MMC Receive Interrupt Register */
+#define ETH_MMCRIR_RGUFS 0x00020000U /* Set when Rx good unicast frames counter reaches half the maximum value */
+#define ETH_MMCRIR_RFAES 0x00000040U /* Set when Rx alignment error counter reaches half the maximum value */
+#define ETH_MMCRIR_RFCES 0x00000020U /* Set when Rx crc error counter reaches half the maximum value */
+
+/* Bit definition for Ethernet MMC Transmit Interrupt Register */
+#define ETH_MMCTIR_TGFS 0x00200000U /* Set when Tx good frame count counter reaches half the maximum value */
+#define ETH_MMCTIR_TGFMSCS 0x00008000U /* Set when Tx good multi col counter reaches half the maximum value */
+#define ETH_MMCTIR_TGFSCS 0x00004000U /* Set when Tx good single col counter reaches half the maximum value */
+
+/* Bit definition for Ethernet MMC Receive Interrupt Mask Register */
+#define ETH_MMCRIMR_RGUFM 0x00020000U /* Mask the interrupt when Rx good unicast frames counter reaches half the maximum value */
+#define ETH_MMCRIMR_RFAEM 0x00000040U /* Mask the interrupt when when Rx alignment error counter reaches half the maximum value */
+#define ETH_MMCRIMR_RFCEM 0x00000020U /* Mask the interrupt when Rx crc error counter reaches half the maximum value */
+
+/* Bit definition for Ethernet MMC Transmit Interrupt Mask Register */
+#define ETH_MMCTIMR_TGFM 0x00200000U /* Mask the interrupt when Tx good frame count counter reaches half the maximum value */
+#define ETH_MMCTIMR_TGFMSCM 0x00008000U /* Mask the interrupt when Tx good multi col counter reaches half the maximum value */
+#define ETH_MMCTIMR_TGFSCM 0x00004000U /* Mask the interrupt when Tx good single col counter reaches half the maximum value */
+
+/* Bit definition for Ethernet MMC Transmitted Good Frames after Single Collision Counter Register */
+#define ETH_MMCTGFSCCR_TGFSCC 0xFFFFFFFFU /* Number of successfully transmitted frames after a single collision in Half-duplex mode. */
+
+/* Bit definition for Ethernet MMC Transmitted Good Frames after More than a Single Collision Counter Register */
+#define ETH_MMCTGFMSCCR_TGFMSCC 0xFFFFFFFFU /* Number of successfully transmitted frames after more than a single collision in Half-duplex mode. */
+
+/* Bit definition for Ethernet MMC Transmitted Good Frames Counter Register */
+#define ETH_MMCTGFCR_TGFC 0xFFFFFFFFU /* Number of good frames transmitted. */
+
+/* Bit definition for Ethernet MMC Received Frames with CRC Error Counter Register */
+#define ETH_MMCRFCECR_RFCEC 0xFFFFFFFFU /* Number of frames received with CRC error. */
+
+/* Bit definition for Ethernet MMC Received Frames with Alignement Error Counter Register */
+#define ETH_MMCRFAECR_RFAEC 0xFFFFFFFFU /* Number of frames received with alignment (dribble) error */
+
+/* Bit definition for Ethernet MMC Received Good Unicast Frames Counter Register */
+#define ETH_MMCRGUFCR_RGUFC 0xFFFFFFFFU /* Number of good unicast frames received. */
+
+/******************************************************************************/
+/* Ethernet PTP Registers bits definition */
+/******************************************************************************/
+
+/* Bit definition for Ethernet PTP Time Stamp Contol Register */
+#define ETH_PTPTSCR_TSCNT 0x00030000U /* Time stamp clock node type */
+#define ETH_PTPTSSR_TSSMRME 0x00008000U /* Time stamp snapshot for message relevant to master enable */
+#define ETH_PTPTSSR_TSSEME 0x00004000U /* Time stamp snapshot for event message enable */
+#define ETH_PTPTSSR_TSSIPV4FE 0x00002000U /* Time stamp snapshot for IPv4 frames enable */
+#define ETH_PTPTSSR_TSSIPV6FE 0x00001000U /* Time stamp snapshot for IPv6 frames enable */
+#define ETH_PTPTSSR_TSSPTPOEFE 0x00000800U /* Time stamp snapshot for PTP over ethernet frames enable */
+#define ETH_PTPTSSR_TSPTPPSV2E 0x00000400U /* Time stamp PTP packet snooping for version2 format enable */
+#define ETH_PTPTSSR_TSSSR 0x00000200U /* Time stamp Sub-seconds rollover */
+#define ETH_PTPTSSR_TSSARFE 0x00000100U /* Time stamp snapshot for all received frames enable */
+
+#define ETH_PTPTSCR_TSARU 0x00000020U /* Addend register update */
+#define ETH_PTPTSCR_TSITE 0x00000010U /* Time stamp interrupt trigger enable */
+#define ETH_PTPTSCR_TSSTU 0x00000008U /* Time stamp update */
+#define ETH_PTPTSCR_TSSTI 0x00000004U /* Time stamp initialize */
+#define ETH_PTPTSCR_TSFCU 0x00000002U /* Time stamp fine or coarse update */
+#define ETH_PTPTSCR_TSE 0x00000001U /* Time stamp enable */
+
+/* Bit definition for Ethernet PTP Sub-Second Increment Register */
+#define ETH_PTPSSIR_STSSI 0x000000FFU /* System time Sub-second increment value */
+
+/* Bit definition for Ethernet PTP Time Stamp High Register */
+#define ETH_PTPTSHR_STS 0xFFFFFFFFU /* System Time second */
+
+/* Bit definition for Ethernet PTP Time Stamp Low Register */
+#define ETH_PTPTSLR_STPNS 0x80000000U /* System Time Positive or negative time */
+#define ETH_PTPTSLR_STSS 0x7FFFFFFFU /* System Time sub-seconds */
+
+/* Bit definition for Ethernet PTP Time Stamp High Update Register */
+#define ETH_PTPTSHUR_TSUS 0xFFFFFFFFU /* Time stamp update seconds */
+
+/* Bit definition for Ethernet PTP Time Stamp Low Update Register */
+#define ETH_PTPTSLUR_TSUPNS 0x80000000U /* Time stamp update Positive or negative time */
+#define ETH_PTPTSLUR_TSUSS 0x7FFFFFFFU /* Time stamp update sub-seconds */
+
+/* Bit definition for Ethernet PTP Time Stamp Addend Register */
+#define ETH_PTPTSAR_TSA 0xFFFFFFFFU /* Time stamp addend */
+
+/* Bit definition for Ethernet PTP Target Time High Register */
+#define ETH_PTPTTHR_TTSH 0xFFFFFFFFU /* Target time stamp high */
+
+/* Bit definition for Ethernet PTP Target Time Low Register */
+#define ETH_PTPTTLR_TTSL 0xFFFFFFFFU /* Target time stamp low */
+
+/* Bit definition for Ethernet PTP Time Stamp Status Register */
+#define ETH_PTPTSSR_TSTTR 0x00000020U /* Time stamp target time reached */
+#define ETH_PTPTSSR_TSSO 0x00000010U /* Time stamp seconds overflow */
+
+/******************************************************************************/
+/* Ethernet DMA Registers bits definition */
+/******************************************************************************/
+
+/* Bit definition for Ethernet DMA Bus Mode Register */
+#define ETH_DMABMR_AAB 0x02000000U /* Address-Aligned beats */
+#define ETH_DMABMR_FPM 0x01000000U /* 4xPBL mode */
+#define ETH_DMABMR_USP 0x00800000U /* Use separate PBL */
+#define ETH_DMABMR_RDP 0x007E0000U /* RxDMA PBL */
+ #define ETH_DMABMR_RDP_1Beat 0x00020000U /* maximum number of beats to be transferred in one RxDMA transaction is 1 */
+ #define ETH_DMABMR_RDP_2Beat 0x00040000U /* maximum number of beats to be transferred in one RxDMA transaction is 2 */
+ #define ETH_DMABMR_RDP_4Beat 0x00080000U /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
+ #define ETH_DMABMR_RDP_8Beat 0x00100000U /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
+ #define ETH_DMABMR_RDP_16Beat 0x00200000U /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
+ #define ETH_DMABMR_RDP_32Beat 0x00400000U /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
+ #define ETH_DMABMR_RDP_4xPBL_4Beat 0x01020000U /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
+ #define ETH_DMABMR_RDP_4xPBL_8Beat 0x01040000U /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
+ #define ETH_DMABMR_RDP_4xPBL_16Beat 0x01080000U /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
+ #define ETH_DMABMR_RDP_4xPBL_32Beat 0x01100000U /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
+ #define ETH_DMABMR_RDP_4xPBL_64Beat 0x01200000U /* maximum number of beats to be transferred in one RxDMA transaction is 64 */
+ #define ETH_DMABMR_RDP_4xPBL_128Beat 0x01400000U /* maximum number of beats to be transferred in one RxDMA transaction is 128 */
+#define ETH_DMABMR_FB 0x00010000U /* Fixed Burst */
+#define ETH_DMABMR_RTPR 0x0000C000U /* Rx Tx priority ratio */
+ #define ETH_DMABMR_RTPR_1_1 0x00000000U /* Rx Tx priority ratio */
+ #define ETH_DMABMR_RTPR_2_1 0x00004000U /* Rx Tx priority ratio */
+ #define ETH_DMABMR_RTPR_3_1 0x00008000U /* Rx Tx priority ratio */
+ #define ETH_DMABMR_RTPR_4_1 0x0000C000U /* Rx Tx priority ratio */
+#define ETH_DMABMR_PBL 0x00003F00U /* Programmable burst length */
+ #define ETH_DMABMR_PBL_1Beat 0x00000100U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */
+ #define ETH_DMABMR_PBL_2Beat 0x00000200U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */
+ #define ETH_DMABMR_PBL_4Beat 0x00000400U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
+ #define ETH_DMABMR_PBL_8Beat 0x00000800U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
+ #define ETH_DMABMR_PBL_16Beat 0x00001000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
+ #define ETH_DMABMR_PBL_32Beat 0x00002000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
+ #define ETH_DMABMR_PBL_4xPBL_4Beat 0x01000100U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
+ #define ETH_DMABMR_PBL_4xPBL_8Beat 0x01000200U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
+ #define ETH_DMABMR_PBL_4xPBL_16Beat 0x01000400U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
+ #define ETH_DMABMR_PBL_4xPBL_32Beat 0x01000800U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
+ #define ETH_DMABMR_PBL_4xPBL_64Beat 0x01001000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */
+ #define ETH_DMABMR_PBL_4xPBL_128Beat 0x01002000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */
+#define ETH_DMABMR_EDE 0x00000080U /* Enhanced Descriptor Enable */
+#define ETH_DMABMR_DSL 0x0000007CU /* Descriptor Skip Length */
+#define ETH_DMABMR_DA 0x00000002U /* DMA arbitration scheme */
+#define ETH_DMABMR_SR 0x00000001U /* Software reset */
+
+/* Bit definition for Ethernet DMA Transmit Poll Demand Register */
+#define ETH_DMATPDR_TPD 0xFFFFFFFFU /* Transmit poll demand */
+
+/* Bit definition for Ethernet DMA Receive Poll Demand Register */
+#define ETH_DMARPDR_RPD 0xFFFFFFFFU /* Receive poll demand */
+
+/* Bit definition for Ethernet DMA Receive Descriptor List Address Register */
+#define ETH_DMARDLAR_SRL 0xFFFFFFFFU /* Start of receive list */
+
+/* Bit definition for Ethernet DMA Transmit Descriptor List Address Register */
+#define ETH_DMATDLAR_STL 0xFFFFFFFFU /* Start of transmit list */
+
+/* Bit definition for Ethernet DMA Status Register */
+#define ETH_DMASR_TSTS 0x20000000U /* Time-stamp trigger status */
+#define ETH_DMASR_PMTS 0x10000000U /* PMT status */
+#define ETH_DMASR_MMCS 0x08000000U /* MMC status */
+#define ETH_DMASR_EBS 0x03800000U /* Error bits status */
+ /* combination with EBS[2:0] for GetFlagStatus function */
+ #define ETH_DMASR_EBS_DescAccess 0x02000000U /* Error bits 0-data buffer, 1-desc. access */
+ #define ETH_DMASR_EBS_ReadTransf 0x01000000U /* Error bits 0-write trnsf, 1-read transfr */
+ #define ETH_DMASR_EBS_DataTransfTx 0x00800000U /* Error bits 0-Rx DMA, 1-Tx DMA */
+#define ETH_DMASR_TPS 0x00700000U /* Transmit process state */
+ #define ETH_DMASR_TPS_Stopped 0x00000000U /* Stopped - Reset or Stop Tx Command issued */
+ #define ETH_DMASR_TPS_Fetching 0x00100000U /* Running - fetching the Tx descriptor */
+ #define ETH_DMASR_TPS_Waiting 0x00200000U /* Running - waiting for status */
+ #define ETH_DMASR_TPS_Reading 0x00300000U /* Running - reading the data from host memory */
+ #define ETH_DMASR_TPS_Suspended 0x00600000U /* Suspended - Tx Descriptor unavailabe */
+ #define ETH_DMASR_TPS_Closing 0x00700000U /* Running - closing Rx descriptor */
+#define ETH_DMASR_RPS 0x000E0000U /* Receive process state */
+ #define ETH_DMASR_RPS_Stopped 0x00000000U /* Stopped - Reset or Stop Rx Command issued */
+ #define ETH_DMASR_RPS_Fetching 0x00020000U /* Running - fetching the Rx descriptor */
+ #define ETH_DMASR_RPS_Waiting 0x00060000U /* Running - waiting for packet */
+ #define ETH_DMASR_RPS_Suspended 0x00080000U /* Suspended - Rx Descriptor unavailable */
+ #define ETH_DMASR_RPS_Closing 0x000A0000U /* Running - closing descriptor */
+ #define ETH_DMASR_RPS_Queuing 0x000E0000U /* Running - queuing the recieve frame into host memory */
+#define ETH_DMASR_NIS 0x00010000U /* Normal interrupt summary */
+#define ETH_DMASR_AIS 0x00008000U /* Abnormal interrupt summary */
+#define ETH_DMASR_ERS 0x00004000U /* Early receive status */
+#define ETH_DMASR_FBES 0x00002000U /* Fatal bus error status */
+#define ETH_DMASR_ETS 0x00000400U /* Early transmit status */
+#define ETH_DMASR_RWTS 0x00000200U /* Receive watchdog timeout status */
+#define ETH_DMASR_RPSS 0x00000100U /* Receive process stopped status */
+#define ETH_DMASR_RBUS 0x00000080U /* Receive buffer unavailable status */
+#define ETH_DMASR_RS 0x00000040U /* Receive status */
+#define ETH_DMASR_TUS 0x00000020U /* Transmit underflow status */
+#define ETH_DMASR_ROS 0x00000010U /* Receive overflow status */
+#define ETH_DMASR_TJTS 0x00000008U /* Transmit jabber timeout status */
+#define ETH_DMASR_TBUS 0x00000004U /* Transmit buffer unavailable status */
+#define ETH_DMASR_TPSS 0x00000002U /* Transmit process stopped status */
+#define ETH_DMASR_TS 0x00000001U /* Transmit status */
+
+/* Bit definition for Ethernet DMA Operation Mode Register */
+#define ETH_DMAOMR_DTCEFD 0x04000000U /* Disable Dropping of TCP/IP checksum error frames */
+#define ETH_DMAOMR_RSF 0x02000000U /* Receive store and forward */
+#define ETH_DMAOMR_DFRF 0x01000000U /* Disable flushing of received frames */
+#define ETH_DMAOMR_TSF 0x00200000U /* Transmit store and forward */
+#define ETH_DMAOMR_FTF 0x00100000U /* Flush transmit FIFO */
+#define ETH_DMAOMR_TTC 0x0001C000U /* Transmit threshold control */
+ #define ETH_DMAOMR_TTC_64Bytes 0x00000000U /* threshold level of the MTL Transmit FIFO is 64 Bytes */
+ #define ETH_DMAOMR_TTC_128Bytes 0x00004000U /* threshold level of the MTL Transmit FIFO is 128 Bytes */
+ #define ETH_DMAOMR_TTC_192Bytes 0x00008000U /* threshold level of the MTL Transmit FIFO is 192 Bytes */
+ #define ETH_DMAOMR_TTC_256Bytes 0x0000C000U /* threshold level of the MTL Transmit FIFO is 256 Bytes */
+ #define ETH_DMAOMR_TTC_40Bytes 0x00010000U /* threshold level of the MTL Transmit FIFO is 40 Bytes */
+ #define ETH_DMAOMR_TTC_32Bytes 0x00014000U /* threshold level of the MTL Transmit FIFO is 32 Bytes */
+ #define ETH_DMAOMR_TTC_24Bytes 0x00018000U /* threshold level of the MTL Transmit FIFO is 24 Bytes */
+ #define ETH_DMAOMR_TTC_16Bytes 0x0001C000U /* threshold level of the MTL Transmit FIFO is 16 Bytes */
+#define ETH_DMAOMR_ST 0x00002000U /* Start/stop transmission command */
+#define ETH_DMAOMR_FEF 0x00000080U /* Forward error frames */
+#define ETH_DMAOMR_FUGF 0x00000040U /* Forward undersized good frames */
+#define ETH_DMAOMR_RTC 0x00000018U /* receive threshold control */
+ #define ETH_DMAOMR_RTC_64Bytes 0x00000000U /* threshold level of the MTL Receive FIFO is 64 Bytes */
+ #define ETH_DMAOMR_RTC_32Bytes 0x00000008U /* threshold level of the MTL Receive FIFO is 32 Bytes */
+ #define ETH_DMAOMR_RTC_96Bytes 0x00000010U /* threshold level of the MTL Receive FIFO is 96 Bytes */
+ #define ETH_DMAOMR_RTC_128Bytes 0x00000018U /* threshold level of the MTL Receive FIFO is 128 Bytes */
+#define ETH_DMAOMR_OSF 0x00000004U /* operate on second frame */
+#define ETH_DMAOMR_SR 0x00000002U /* Start/stop receive */
+
+/* Bit definition for Ethernet DMA Interrupt Enable Register */
+#define ETH_DMAIER_NISE 0x00010000U /* Normal interrupt summary enable */
+#define ETH_DMAIER_AISE 0x00008000U /* Abnormal interrupt summary enable */
+#define ETH_DMAIER_ERIE 0x00004000U /* Early receive interrupt enable */
+#define ETH_DMAIER_FBEIE 0x00002000U /* Fatal bus error interrupt enable */
+#define ETH_DMAIER_ETIE 0x00000400U /* Early transmit interrupt enable */
+#define ETH_DMAIER_RWTIE 0x00000200U /* Receive watchdog timeout interrupt enable */
+#define ETH_DMAIER_RPSIE 0x00000100U /* Receive process stopped interrupt enable */
+#define ETH_DMAIER_RBUIE 0x00000080U /* Receive buffer unavailable interrupt enable */
+#define ETH_DMAIER_RIE 0x00000040U /* Receive interrupt enable */
+#define ETH_DMAIER_TUIE 0x00000020U /* Transmit Underflow interrupt enable */
+#define ETH_DMAIER_ROIE 0x00000010U /* Receive Overflow interrupt enable */
+#define ETH_DMAIER_TJTIE 0x00000008U /* Transmit jabber timeout interrupt enable */
+#define ETH_DMAIER_TBUIE 0x00000004U /* Transmit buffer unavailable interrupt enable */
+#define ETH_DMAIER_TPSIE 0x00000002U /* Transmit process stopped interrupt enable */
+#define ETH_DMAIER_TIE 0x00000001U /* Transmit interrupt enable */
+
+/* Bit definition for Ethernet DMA Missed Frame and Buffer Overflow Counter Register */
+#define ETH_DMAMFBOCR_OFOC 0x10000000U /* Overflow bit for FIFO overflow counter */
+#define ETH_DMAMFBOCR_MFA 0x0FFE0000U /* Number of frames missed by the application */
+#define ETH_DMAMFBOCR_OMFC 0x00010000U /* Overflow bit for missed frame counter */
+#define ETH_DMAMFBOCR_MFC 0x0000FFFFU /* Number of frames missed by the controller */
+
+/* Bit definition for Ethernet DMA Current Host Transmit Descriptor Register */
+#define ETH_DMACHTDR_HTDAP 0xFFFFFFFFU /* Host transmit descriptor address pointer */
+
+/* Bit definition for Ethernet DMA Current Host Receive Descriptor Register */
+#define ETH_DMACHRDR_HRDAP 0xFFFFFFFFU /* Host receive descriptor address pointer */
+
+/* Bit definition for Ethernet DMA Current Host Transmit Buffer Address Register */
+#define ETH_DMACHTBAR_HTBAP 0xFFFFFFFFU /* Host transmit buffer address pointer */
+
+/* Bit definition for Ethernet DMA Current Host Receive Buffer Address Register */
+#define ETH_DMACHRBAR_HRBAP 0xFFFFFFFFU /* Host receive buffer address pointer */
+
+/******************************************************************************/
+/* */
+/* USB_OTG */
+/* */
+/******************************************************************************/
+/******************** Bit definition forUSB_OTG_GOTGCTL register ********************/
+#define USB_OTG_GOTGCTL_SRQSCS 0x00000001U /*!< Session request success */
+#define USB_OTG_GOTGCTL_SRQ 0x00000002U /*!< Session request */
+#define USB_OTG_GOTGCTL_VBVALOEN 0x00000004U /*!< VBUS valid override enable */
+#define USB_OTG_GOTGCTL_VBVALOVAL 0x00000008U /*!< VBUS valid override value */
+#define USB_OTG_GOTGCTL_AVALOEN 0x00000010U /*!< A-peripheral session valid override enable */
+#define USB_OTG_GOTGCTL_AVALOVAL 0x00000020U /*!< A-peripheral session valid override value */
+#define USB_OTG_GOTGCTL_BVALOEN 0x00000040U /*!< B-peripheral session valid override enable */
+#define USB_OTG_GOTGCTL_BVALOVAL 0x00000080U /*!< B-peripheral session valid override value */
+#define USB_OTG_GOTGCTL_HNGSCS 0x00000100U /*!< Host set HNP enable */
+#define USB_OTG_GOTGCTL_HNPRQ 0x00000200U /*!< HNP request */
+#define USB_OTG_GOTGCTL_HSHNPEN 0x00000400U /*!< Host set HNP enable */
+#define USB_OTG_GOTGCTL_DHNPEN 0x00000800U /*!< Device HNP enabled */
+#define USB_OTG_GOTGCTL_EHEN 0x00001000U /*!< Embedded host enable */
+#define USB_OTG_GOTGCTL_CIDSTS 0x00010000U /*!< Connector ID status */
+#define USB_OTG_GOTGCTL_DBCT 0x00020000U /*!< Long/short debounce time */
+#define USB_OTG_GOTGCTL_ASVLD 0x00040000U /*!< A-session valid */
+#define USB_OTG_GOTGCTL_BSESVLD 0x00080000U /*!< B-session valid */
+#define USB_OTG_GOTGCTL_OTGVER 0x00100000U /*!< OTG version */
+
+/******************** Bit definition forUSB_OTG_HCFG register ********************/
+
+#define USB_OTG_HCFG_FSLSPCS 0x00000003U /*!< FS/LS PHY clock select */
+#define USB_OTG_HCFG_FSLSPCS_0 0x00000001U /*!<Bit 0 */
+#define USB_OTG_HCFG_FSLSPCS_1 0x00000002U /*!<Bit 1 */
+#define USB_OTG_HCFG_FSLSS 0x00000004U /*!< FS- and LS-only support */
+
+/******************** Bit definition forUSB_OTG_DCFG register ********************/
+
+#define USB_OTG_DCFG_DSPD 0x00000003U /*!< Device speed */
+#define USB_OTG_DCFG_DSPD_0 0x00000001U /*!<Bit 0 */
+#define USB_OTG_DCFG_DSPD_1 0x00000002U /*!<Bit 1 */
+#define USB_OTG_DCFG_NZLSOHSK 0x00000004U /*!< Nonzero-length status OUT handshake */
+
+#define USB_OTG_DCFG_DAD 0x000007F0U /*!< Device address */
+#define USB_OTG_DCFG_DAD_0 0x00000010U /*!<Bit 0 */
+#define USB_OTG_DCFG_DAD_1 0x00000020U /*!<Bit 1 */
+#define USB_OTG_DCFG_DAD_2 0x00000040U /*!<Bit 2 */
+#define USB_OTG_DCFG_DAD_3 0x00000080U /*!<Bit 3 */
+#define USB_OTG_DCFG_DAD_4 0x00000100U /*!<Bit 4 */
+#define USB_OTG_DCFG_DAD_5 0x00000200U /*!<Bit 5 */
+#define USB_OTG_DCFG_DAD_6 0x00000400U /*!<Bit 6 */
+
+#define USB_OTG_DCFG_PFIVL 0x00001800U /*!< Periodic (micro)frame interval */
+#define USB_OTG_DCFG_PFIVL_0 0x00000800U /*!<Bit 0 */
+#define USB_OTG_DCFG_PFIVL_1 0x00001000U /*!<Bit 1 */
+
+#define USB_OTG_DCFG_PERSCHIVL 0x03000000U /*!< Periodic scheduling interval */
+#define USB_OTG_DCFG_PERSCHIVL_0 0x01000000U /*!<Bit 0 */
+#define USB_OTG_DCFG_PERSCHIVL_1 0x02000000U /*!<Bit 1 */
+
+/******************** Bit definition forUSB_OTG_PCGCR register ********************/
+#define USB_OTG_PCGCR_STPPCLK 0x00000001U /*!< Stop PHY clock */
+#define USB_OTG_PCGCR_GATEHCLK 0x00000002U /*!< Gate HCLK */
+#define USB_OTG_PCGCR_PHYSUSP 0x00000010U /*!< PHY suspended */
+
+/******************** Bit definition forUSB_OTG_GOTGINT register ********************/
+#define USB_OTG_GOTGINT_SEDET 0x00000004U /*!< Session end detected */
+#define USB_OTG_GOTGINT_SRSSCHG 0x00000100U /*!< Session request success status change */
+#define USB_OTG_GOTGINT_HNSSCHG 0x00000200U /*!< Host negotiation success status change */
+#define USB_OTG_GOTGINT_HNGDET 0x00020000U /*!< Host negotiation detected */
+#define USB_OTG_GOTGINT_ADTOCHG 0x00040000U /*!< A-device timeout change */
+#define USB_OTG_GOTGINT_DBCDNE 0x00080000U /*!< Debounce done */
+#define USB_OTG_GOTGINT_IDCHNG 0x00100000U /*!< Change in ID pin input value */
+
+/******************** Bit definition forUSB_OTG_DCTL register ********************/
+#define USB_OTG_DCTL_RWUSIG 0x00000001U /*!< Remote wakeup signaling */
+#define USB_OTG_DCTL_SDIS 0x00000002U /*!< Soft disconnect */
+#define USB_OTG_DCTL_GINSTS 0x00000004U /*!< Global IN NAK status */
+#define USB_OTG_DCTL_GONSTS 0x00000008U /*!< Global OUT NAK status */
+
+#define USB_OTG_DCTL_TCTL 0x00000070U /*!< Test control */
+#define USB_OTG_DCTL_TCTL_0 0x00000010U /*!<Bit 0 */
+#define USB_OTG_DCTL_TCTL_1 0x00000020U /*!<Bit 1 */
+#define USB_OTG_DCTL_TCTL_2 0x00000040U /*!<Bit 2 */
+#define USB_OTG_DCTL_SGINAK 0x00000080U /*!< Set global IN NAK */
+#define USB_OTG_DCTL_CGINAK 0x00000100U /*!< Clear global IN NAK */
+#define USB_OTG_DCTL_SGONAK 0x00000200U /*!< Set global OUT NAK */
+#define USB_OTG_DCTL_CGONAK 0x00000400U /*!< Clear global OUT NAK */
+#define USB_OTG_DCTL_POPRGDNE 0x00000800U /*!< Power-on programming done */
+
+/******************** Bit definition forUSB_OTG_HFIR register ********************/
+#define USB_OTG_HFIR_FRIVL 0x0000FFFFU /*!< Frame interval */
+
+/******************** Bit definition forUSB_OTG_HFNUM register ********************/
+#define USB_OTG_HFNUM_FRNUM 0x0000FFFFU /*!< Frame number */
+#define USB_OTG_HFNUM_FTREM 0xFFFF0000U /*!< Frame time remaining */
+
+/******************** Bit definition forUSB_OTG_DSTS register ********************/
+#define USB_OTG_DSTS_SUSPSTS 0x00000001U /*!< Suspend status */
+
+#define USB_OTG_DSTS_ENUMSPD 0x00000006U /*!< Enumerated speed */
+#define USB_OTG_DSTS_ENUMSPD_0 0x00000002U /*!<Bit 0 */
+#define USB_OTG_DSTS_ENUMSPD_1 0x00000004U /*!<Bit 1 */
+#define USB_OTG_DSTS_EERR 0x00000008U /*!< Erratic error */
+#define USB_OTG_DSTS_FNSOF 0x003FFF00U /*!< Frame number of the received SOF */
+
+/******************** Bit definition forUSB_OTG_GAHBCFG register ********************/
+#define USB_OTG_GAHBCFG_GINT 0x00000001U /*!< Global interrupt mask */
+#define USB_OTG_GAHBCFG_HBSTLEN 0x0000001EU /*!< Burst length/type */
+#define USB_OTG_GAHBCFG_HBSTLEN_0 0x00000002U /*!<Bit 0 */
+#define USB_OTG_GAHBCFG_HBSTLEN_1 0x00000004U /*!<Bit 1 */
+#define USB_OTG_GAHBCFG_HBSTLEN_2 0x00000008U /*!<Bit 2 */
+#define USB_OTG_GAHBCFG_HBSTLEN_3 0x00000010U /*!<Bit 3 */
+#define USB_OTG_GAHBCFG_DMAEN 0x00000020U /*!< DMA enable */
+#define USB_OTG_GAHBCFG_TXFELVL 0x00000080U /*!< TxFIFO empty level */
+#define USB_OTG_GAHBCFG_PTXFELVL 0x00000100U /*!< Periodic TxFIFO empty level */
+
+/******************** Bit definition forUSB_OTG_GUSBCFG register ********************/
+
+#define USB_OTG_GUSBCFG_TOCAL 0x00000007U /*!< FS timeout calibration */
+#define USB_OTG_GUSBCFG_TOCAL_0 0x00000001U /*!<Bit 0 */
+#define USB_OTG_GUSBCFG_TOCAL_1 0x00000002U /*!<Bit 1 */
+#define USB_OTG_GUSBCFG_TOCAL_2 0x00000004U /*!<Bit 2 */
+#define USB_OTG_GUSBCFG_PHYSEL 0x00000040U /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */
+#define USB_OTG_GUSBCFG_SRPCAP 0x00000100U /*!< SRP-capable */
+#define USB_OTG_GUSBCFG_HNPCAP 0x00000200U /*!< HNP-capable */
+#define USB_OTG_GUSBCFG_TRDT 0x00003C00U /*!< USB turnaround time */
+#define USB_OTG_GUSBCFG_TRDT_0 0x00000400U /*!<Bit 0 */
+#define USB_OTG_GUSBCFG_TRDT_1 0x00000800U /*!<Bit 1 */
+#define USB_OTG_GUSBCFG_TRDT_2 0x00001000U /*!<Bit 2 */
+#define USB_OTG_GUSBCFG_TRDT_3 0x00002000U /*!<Bit 3 */
+#define USB_OTG_GUSBCFG_PHYLPCS 0x00008000U /*!< PHY Low-power clock select */
+#define USB_OTG_GUSBCFG_ULPIFSLS 0x00020000U /*!< ULPI FS/LS select */
+#define USB_OTG_GUSBCFG_ULPIAR 0x00040000U /*!< ULPI Auto-resume */
+#define USB_OTG_GUSBCFG_ULPICSM 0x00080000U /*!< ULPI Clock SuspendM */
+#define USB_OTG_GUSBCFG_ULPIEVBUSD 0x00100000U /*!< ULPI External VBUS Drive */
+#define USB_OTG_GUSBCFG_ULPIEVBUSI 0x00200000U /*!< ULPI external VBUS indicator */
+#define USB_OTG_GUSBCFG_TSDPS 0x00400000U /*!< TermSel DLine pulsing selection */
+#define USB_OTG_GUSBCFG_PCCI 0x00800000U /*!< Indicator complement */
+#define USB_OTG_GUSBCFG_PTCI 0x01000000U /*!< Indicator pass through */
+#define USB_OTG_GUSBCFG_ULPIIPD 0x02000000U /*!< ULPI interface protect disable */
+#define USB_OTG_GUSBCFG_FHMOD 0x20000000U /*!< Forced host mode */
+#define USB_OTG_GUSBCFG_FDMOD 0x40000000U /*!< Forced peripheral mode */
+#define USB_OTG_GUSBCFG_CTXPKT 0x80000000U /*!< Corrupt Tx packet */
+
+/******************** Bit definition forUSB_OTG_GRSTCTL register ********************/
+#define USB_OTG_GRSTCTL_CSRST 0x00000001U /*!< Core soft reset */
+#define USB_OTG_GRSTCTL_HSRST 0x00000002U /*!< HCLK soft reset */
+#define USB_OTG_GRSTCTL_FCRST 0x00000004U /*!< Host frame counter reset */
+#define USB_OTG_GRSTCTL_RXFFLSH 0x00000010U /*!< RxFIFO flush */
+#define USB_OTG_GRSTCTL_TXFFLSH 0x00000020U /*!< TxFIFO flush */
+#define USB_OTG_GRSTCTL_TXFNUM 0x000007C0U /*!< TxFIFO number */
+#define USB_OTG_GRSTCTL_TXFNUM_0 0x00000040U /*!<Bit 0 */
+#define USB_OTG_GRSTCTL_TXFNUM_1 0x00000080U /*!<Bit 1 */
+#define USB_OTG_GRSTCTL_TXFNUM_2 0x00000100U /*!<Bit 2 */
+#define USB_OTG_GRSTCTL_TXFNUM_3 0x00000200U /*!<Bit 3 */
+#define USB_OTG_GRSTCTL_TXFNUM_4 0x00000400U /*!<Bit 4 */
+#define USB_OTG_GRSTCTL_DMAREQ 0x40000000U /*!< DMA request signal */
+#define USB_OTG_GRSTCTL_AHBIDL 0x80000000U /*!< AHB master idle */
+
+/******************** Bit definition forUSB_OTG_DIEPMSK register ********************/
+#define USB_OTG_DIEPMSK_XFRCM 0x00000001U /*!< Transfer completed interrupt mask */
+#define USB_OTG_DIEPMSK_EPDM 0x00000002U /*!< Endpoint disabled interrupt mask */
+#define USB_OTG_DIEPMSK_TOM 0x00000008U /*!< Timeout condition mask (nonisochronous endpoints) */
+#define USB_OTG_DIEPMSK_ITTXFEMSK 0x00000010U /*!< IN token received when TxFIFO empty mask */
+#define USB_OTG_DIEPMSK_INEPNMM 0x00000020U /*!< IN token received with EP mismatch mask */
+#define USB_OTG_DIEPMSK_INEPNEM 0x00000040U /*!< IN endpoint NAK effective mask */
+#define USB_OTG_DIEPMSK_TXFURM 0x00000100U /*!< FIFO underrun mask */
+#define USB_OTG_DIEPMSK_BIM 0x00000200U /*!< BNA interrupt mask */
+
+/******************** Bit definition forUSB_OTG_HPTXSTS register ********************/
+#define USB_OTG_HPTXSTS_PTXFSAVL 0x0000FFFFU /*!< Periodic transmit data FIFO space available */
+#define USB_OTG_HPTXSTS_PTXQSAV 0x00FF0000U /*!< Periodic transmit request queue space available */
+#define USB_OTG_HPTXSTS_PTXQSAV_0 0x00010000U /*!<Bit 0 */
+#define USB_OTG_HPTXSTS_PTXQSAV_1 0x00020000U /*!<Bit 1 */
+#define USB_OTG_HPTXSTS_PTXQSAV_2 0x00040000U /*!<Bit 2 */
+#define USB_OTG_HPTXSTS_PTXQSAV_3 0x00080000U /*!<Bit 3 */
+#define USB_OTG_HPTXSTS_PTXQSAV_4 0x00100000U /*!<Bit 4 */
+#define USB_OTG_HPTXSTS_PTXQSAV_5 0x00200000U /*!<Bit 5 */
+#define USB_OTG_HPTXSTS_PTXQSAV_6 0x00400000U /*!<Bit 6 */
+#define USB_OTG_HPTXSTS_PTXQSAV_7 0x00800000U /*!<Bit 7 */
+
+#define USB_OTG_HPTXSTS_PTXQTOP 0xFF000000U /*!< Top of the periodic transmit request queue */
+#define USB_OTG_HPTXSTS_PTXQTOP_0 0x01000000U /*!<Bit 0 */
+#define USB_OTG_HPTXSTS_PTXQTOP_1 0x02000000U /*!<Bit 1 */
+#define USB_OTG_HPTXSTS_PTXQTOP_2 0x04000000U /*!<Bit 2 */
+#define USB_OTG_HPTXSTS_PTXQTOP_3 0x08000000U /*!<Bit 3 */
+#define USB_OTG_HPTXSTS_PTXQTOP_4 0x10000000U /*!<Bit 4 */
+#define USB_OTG_HPTXSTS_PTXQTOP_5 0x20000000U /*!<Bit 5 */
+#define USB_OTG_HPTXSTS_PTXQTOP_6 0x40000000U /*!<Bit 6 */
+#define USB_OTG_HPTXSTS_PTXQTOP_7 0x80000000U /*!<Bit 7 */
+
+/******************** Bit definition forUSB_OTG_HAINT register ********************/
+#define USB_OTG_HAINT_HAINT 0x0000FFFFU /*!< Channel interrupts */
+
+/******************** Bit definition forUSB_OTG_DOEPMSK register ********************/
+#define USB_OTG_DOEPMSK_XFRCM 0x00000001U /*!< Transfer completed interrupt mask */
+#define USB_OTG_DOEPMSK_EPDM 0x00000002U /*!< Endpoint disabled interrupt mask */
+#define USB_OTG_DOEPMSK_STUPM 0x00000008U /*!< SETUP phase done mask */
+#define USB_OTG_DOEPMSK_OTEPDM 0x00000010U /*!< OUT token received when endpoint disabled mask */
+#define USB_OTG_DOEPMSK_OTEPSPRM 0x00000020U /*!< Status Phase Received mask */
+#define USB_OTG_DOEPMSK_B2BSTUP 0x00000040U /*!< Back-to-back SETUP packets received mask */
+#define USB_OTG_DOEPMSK_OPEM 0x00000100U /*!< OUT packet error mask */
+#define USB_OTG_DOEPMSK_BOIM 0x00000200U /*!< BNA interrupt mask */
+
+/******************** Bit definition forUSB_OTG_GINTSTS register ********************/
+#define USB_OTG_GINTSTS_CMOD 0x00000001U /*!< Current mode of operation */
+#define USB_OTG_GINTSTS_MMIS 0x00000002U /*!< Mode mismatch interrupt */
+#define USB_OTG_GINTSTS_OTGINT 0x00000004U /*!< OTG interrupt */
+#define USB_OTG_GINTSTS_SOF 0x00000008U /*!< Start of frame */
+#define USB_OTG_GINTSTS_RXFLVL 0x00000010U /*!< RxFIFO nonempty */
+#define USB_OTG_GINTSTS_NPTXFE 0x00000020U /*!< Nonperiodic TxFIFO empty */
+#define USB_OTG_GINTSTS_GINAKEFF 0x00000040U /*!< Global IN nonperiodic NAK effective */
+#define USB_OTG_GINTSTS_BOUTNAKEFF 0x00000080U /*!< Global OUT NAK effective */
+#define USB_OTG_GINTSTS_ESUSP 0x00000400U /*!< Early suspend */
+#define USB_OTG_GINTSTS_USBSUSP 0x00000800U /*!< USB suspend */
+#define USB_OTG_GINTSTS_USBRST 0x00001000U /*!< USB reset */
+#define USB_OTG_GINTSTS_ENUMDNE 0x00002000U /*!< Enumeration done */
+#define USB_OTG_GINTSTS_ISOODRP 0x00004000U /*!< Isochronous OUT packet dropped interrupt */
+#define USB_OTG_GINTSTS_EOPF 0x00008000U /*!< End of periodic frame interrupt */
+#define USB_OTG_GINTSTS_IEPINT 0x00040000U /*!< IN endpoint interrupt */
+#define USB_OTG_GINTSTS_OEPINT 0x00080000U /*!< OUT endpoint interrupt */
+#define USB_OTG_GINTSTS_IISOIXFR 0x00100000U /*!< Incomplete isochronous IN transfer */
+#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT 0x00200000U /*!< Incomplete periodic transfer */
+#define USB_OTG_GINTSTS_DATAFSUSP 0x00400000U /*!< Data fetch suspended */
+#define USB_OTG_GINTSTS_RSTDET 0x00800000U /*!< Reset detected interrupt */
+#define USB_OTG_GINTSTS_HPRTINT 0x01000000U /*!< Host port interrupt */
+#define USB_OTG_GINTSTS_HCINT 0x02000000U /*!< Host channels interrupt */
+#define USB_OTG_GINTSTS_PTXFE 0x04000000U /*!< Periodic TxFIFO empty */
+#define USB_OTG_GINTSTS_LPMINT 0x08000000U /*!< LPM interrupt */
+#define USB_OTG_GINTSTS_CIDSCHG 0x10000000U /*!< Connector ID status change */
+#define USB_OTG_GINTSTS_DISCINT 0x20000000U /*!< Disconnect detected interrupt */
+#define USB_OTG_GINTSTS_SRQINT 0x40000000U /*!< Session request/new session detected interrupt */
+#define USB_OTG_GINTSTS_WKUINT 0x80000000U /*!< Resume/remote wakeup detected interrupt */
+
+/******************** Bit definition forUSB_OTG_GINTMSK register ********************/
+#define USB_OTG_GINTMSK_MMISM 0x00000002U /*!< Mode mismatch interrupt mask */
+#define USB_OTG_GINTMSK_OTGINT 0x00000004U /*!< OTG interrupt mask */
+#define USB_OTG_GINTMSK_SOFM 0x00000008U /*!< Start of frame mask */
+#define USB_OTG_GINTMSK_RXFLVLM 0x00000010U /*!< Receive FIFO nonempty mask */
+#define USB_OTG_GINTMSK_NPTXFEM 0x00000020U /*!< Nonperiodic TxFIFO empty mask */
+#define USB_OTG_GINTMSK_GINAKEFFM 0x00000040U /*!< Global nonperiodic IN NAK effective mask */
+#define USB_OTG_GINTMSK_GONAKEFFM 0x00000080U /*!< Global OUT NAK effective mask */
+#define USB_OTG_GINTMSK_ESUSPM 0x00000400U /*!< Early suspend mask */
+#define USB_OTG_GINTMSK_USBSUSPM 0x00000800U /*!< USB suspend mask */
+#define USB_OTG_GINTMSK_USBRST 0x00001000U /*!< USB reset mask */
+#define USB_OTG_GINTMSK_ENUMDNEM 0x00002000U /*!< Enumeration done mask */
+#define USB_OTG_GINTMSK_ISOODRPM 0x00004000U /*!< Isochronous OUT packet dropped interrupt mask */
+#define USB_OTG_GINTMSK_EOPFM 0x00008000U /*!< End of periodic frame interrupt mask */
+#define USB_OTG_GINTMSK_EPMISM 0x00020000U /*!< Endpoint mismatch interrupt mask */
+#define USB_OTG_GINTMSK_IEPINT 0x00040000U /*!< IN endpoints interrupt mask */
+#define USB_OTG_GINTMSK_OEPINT 0x00080000U /*!< OUT endpoints interrupt mask */
+#define USB_OTG_GINTMSK_IISOIXFRM 0x00100000U /*!< Incomplete isochronous IN transfer mask */
+#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM 0x00200000U /*!< Incomplete periodic transfer mask */
+#define USB_OTG_GINTMSK_FSUSPM 0x00400000U /*!< Data fetch suspended mask */
+#define USB_OTG_GINTMSK_RSTDEM 0x00800000U /*!< Reset detected interrupt mask */
+#define USB_OTG_GINTMSK_PRTIM 0x01000000U /*!< Host port interrupt mask */
+#define USB_OTG_GINTMSK_HCIM 0x02000000U /*!< Host channels interrupt mask */
+#define USB_OTG_GINTMSK_PTXFEM 0x04000000U /*!< Periodic TxFIFO empty mask */
+#define USB_OTG_GINTMSK_LPMINTM 0x08000000U /*!< LPM interrupt Mask */
+#define USB_OTG_GINTMSK_CIDSCHGM 0x10000000U /*!< Connector ID status change mask */
+#define USB_OTG_GINTMSK_DISCINT 0x20000000U /*!< Disconnect detected interrupt mask */
+#define USB_OTG_GINTMSK_SRQIM 0x40000000U /*!< Session request/new session detected interrupt mask */
+#define USB_OTG_GINTMSK_WUIM 0x80000000U /*!< Resume/remote wakeup detected interrupt mask */
+
+/******************** Bit definition forUSB_OTG_DAINT register ********************/
+#define USB_OTG_DAINT_IEPINT 0x0000FFFFU /*!< IN endpoint interrupt bits */
+#define USB_OTG_DAINT_OEPINT 0xFFFF0000U /*!< OUT endpoint interrupt bits */
+
+/******************** Bit definition forUSB_OTG_HAINTMSK register ********************/
+#define USB_OTG_HAINTMSK_HAINTM 0x0000FFFFU /*!< Channel interrupt mask */
+
+/******************** Bit definition for USB_OTG_GRXSTSP register ********************/
+#define USB_OTG_GRXSTSP_EPNUM 0x0000000FU /*!< IN EP interrupt mask bits */
+#define USB_OTG_GRXSTSP_BCNT 0x00007FF0U /*!< OUT EP interrupt mask bits */
+#define USB_OTG_GRXSTSP_DPID 0x00018000U /*!< OUT EP interrupt mask bits */
+#define USB_OTG_GRXSTSP_PKTSTS 0x001E0000U /*!< OUT EP interrupt mask bits */
+
+/******************** Bit definition forUSB_OTG_DAINTMSK register ********************/
+#define USB_OTG_DAINTMSK_IEPM 0x0000FFFFU /*!< IN EP interrupt mask bits */
+#define USB_OTG_DAINTMSK_OEPM 0xFFFF0000U /*!< OUT EP interrupt mask bits */
+
+/******************** Bit definition for OTG register ********************/
+
+#define USB_OTG_CHNUM 0x0000000FU /*!< Channel number */
+#define USB_OTG_CHNUM_0 0x00000001U /*!<Bit 0 */
+#define USB_OTG_CHNUM_1 0x00000002U /*!<Bit 1 */
+#define USB_OTG_CHNUM_2 0x00000004U /*!<Bit 2 */
+#define USB_OTG_CHNUM_3 0x00000008U /*!<Bit 3 */
+#define USB_OTG_BCNT 0x00007FF0U /*!< Byte count */
+
+#define USB_OTG_DPID 0x00018000U /*!< Data PID */
+#define USB_OTG_DPID_0 0x00008000U /*!<Bit 0 */
+#define USB_OTG_DPID_1 0x00010000U /*!<Bit 1 */
+
+#define USB_OTG_PKTSTS 0x001E0000U /*!< Packet status */
+#define USB_OTG_PKTSTS_0 0x00020000U /*!<Bit 0 */
+#define USB_OTG_PKTSTS_1 0x00040000U /*!<Bit 1 */
+#define USB_OTG_PKTSTS_2 0x00080000U /*!<Bit 2 */
+#define USB_OTG_PKTSTS_3 0x00100000U /*!<Bit 3 */
+
+#define USB_OTG_EPNUM 0x0000000FU /*!< Endpoint number */
+#define USB_OTG_EPNUM_0 0x00000001U /*!<Bit 0 */
+#define USB_OTG_EPNUM_1 0x00000002U /*!<Bit 1 */
+#define USB_OTG_EPNUM_2 0x00000004U /*!<Bit 2 */
+#define USB_OTG_EPNUM_3 0x00000008U /*!<Bit 3 */
+
+#define USB_OTG_FRMNUM 0x01E00000U /*!< Frame number */
+#define USB_OTG_FRMNUM_0 0x00200000U /*!<Bit 0 */
+#define USB_OTG_FRMNUM_1 0x00400000U /*!<Bit 1 */
+#define USB_OTG_FRMNUM_2 0x00800000U /*!<Bit 2 */
+#define USB_OTG_FRMNUM_3 0x01000000U /*!<Bit 3 */
+
+/******************** Bit definition for OTG register ********************/
+
+#define USB_OTG_CHNUM 0x0000000FU /*!< Channel number */
+#define USB_OTG_CHNUM_0 0x00000001U /*!<Bit 0 */
+#define USB_OTG_CHNUM_1 0x00000002U /*!<Bit 1 */
+#define USB_OTG_CHNUM_2 0x00000004U /*!<Bit 2 */
+#define USB_OTG_CHNUM_3 0x00000008U /*!<Bit 3 */
+#define USB_OTG_BCNT 0x00007FF0U /*!< Byte count */
+
+#define USB_OTG_DPID 0x00018000U /*!< Data PID */
+#define USB_OTG_DPID_0 0x00008000U /*!<Bit 0 */
+#define USB_OTG_DPID_1 0x00010000U /*!<Bit 1 */
+
+#define USB_OTG_PKTSTS 0x001E0000U /*!< Packet status */
+#define USB_OTG_PKTSTS_0 0x00020000U /*!<Bit 0 */
+#define USB_OTG_PKTSTS_1 0x00040000U /*!<Bit 1 */
+#define USB_OTG_PKTSTS_2 0x00080000U /*!<Bit 2 */
+#define USB_OTG_PKTSTS_3 0x00100000U /*!<Bit 3 */
+
+#define USB_OTG_EPNUM 0x0000000FU /*!< Endpoint number */
+#define USB_OTG_EPNUM_0 0x00000001U /*!<Bit 0 */
+#define USB_OTG_EPNUM_1 0x00000002U /*!<Bit 1 */
+#define USB_OTG_EPNUM_2 0x00000004U /*!<Bit 2 */
+#define USB_OTG_EPNUM_3 0x00000008U /*!<Bit 3 */
+
+#define USB_OTG_FRMNUM 0x01E00000U /*!< Frame number */
+#define USB_OTG_FRMNUM_0 0x00200000U /*!<Bit 0 */
+#define USB_OTG_FRMNUM_1 0x00400000U /*!<Bit 1 */
+#define USB_OTG_FRMNUM_2 0x00800000U /*!<Bit 2 */
+#define USB_OTG_FRMNUM_3 0x01000000U /*!<Bit 3 */
+
+/******************** Bit definition forUSB_OTG_GRXFSIZ register ********************/
+#define USB_OTG_GRXFSIZ_RXFD 0x0000FFFFU /*!< RxFIFO depth */
+
+/******************** Bit definition forUSB_OTG_DVBUSDIS register ********************/
+#define USB_OTG_DVBUSDIS_VBUSDT 0x0000FFFFU /*!< Device VBUS discharge time */
+
+/******************** Bit definition for OTG register ********************/
+#define USB_OTG_NPTXFSA 0x0000FFFFU /*!< Nonperiodic transmit RAM start address */
+#define USB_OTG_NPTXFD 0xFFFF0000U /*!< Nonperiodic TxFIFO depth */
+#define USB_OTG_TX0FSA 0x0000FFFFU /*!< Endpoint 0 transmit RAM start address */
+#define USB_OTG_TX0FD 0xFFFF0000U /*!< Endpoint 0 TxFIFO depth */
+
+/******************** Bit definition forUSB_OTG_DVBUSPULSE register ********************/
+#define USB_OTG_DVBUSPULSE_DVBUSP 0x00000FFFU /*!< Device VBUS pulsing time */
+
+/******************** Bit definition forUSB_OTG_GNPTXSTS register ********************/
+#define USB_OTG_GNPTXSTS_NPTXFSAV 0x0000FFFFU /*!< Nonperiodic TxFIFO space available */
+
+#define USB_OTG_GNPTXSTS_NPTQXSAV 0x00FF0000U /*!< Nonperiodic transmit request queue space available */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_0 0x00010000U /*!<Bit 0 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_1 0x00020000U /*!<Bit 1 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_2 0x00040000U /*!<Bit 2 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_3 0x00080000U /*!<Bit 3 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_4 0x00100000U /*!<Bit 4 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_5 0x00200000U /*!<Bit 5 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_6 0x00400000U /*!<Bit 6 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_7 0x00800000U /*!<Bit 7 */
+
+#define USB_OTG_GNPTXSTS_NPTXQTOP 0x7F000000U /*!< Top of the nonperiodic transmit request queue */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_0 0x01000000U /*!<Bit 0 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_1 0x02000000U /*!<Bit 1 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_2 0x04000000U /*!<Bit 2 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_3 0x08000000U /*!<Bit 3 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_4 0x10000000U /*!<Bit 4 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_5 0x20000000U /*!<Bit 5 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_6 0x40000000U /*!<Bit 6 */
+
+/******************** Bit definition forUSB_OTG_DTHRCTL register ********************/
+#define USB_OTG_DTHRCTL_NONISOTHREN 0x00000001U /*!< Nonisochronous IN endpoints threshold enable */
+#define USB_OTG_DTHRCTL_ISOTHREN 0x00000002U /*!< ISO IN endpoint threshold enable */
+
+#define USB_OTG_DTHRCTL_TXTHRLEN 0x000007FCU /*!< Transmit threshold length */
+#define USB_OTG_DTHRCTL_TXTHRLEN_0 0x00000004U /*!<Bit 0 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_1 0x00000008U /*!<Bit 1 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_2 0x00000010U /*!<Bit 2 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_3 0x00000020U /*!<Bit 3 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_4 0x00000040U /*!<Bit 4 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_5 0x00000080U /*!<Bit 5 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_6 0x00000100U /*!<Bit 6 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_7 0x00000200U /*!<Bit 7 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_8 0x00000400U /*!<Bit 8 */
+#define USB_OTG_DTHRCTL_RXTHREN 0x00010000U /*!< Receive threshold enable */
+
+#define USB_OTG_DTHRCTL_RXTHRLEN 0x03FE0000U /*!< Receive threshold length */
+#define USB_OTG_DTHRCTL_RXTHRLEN_0 0x00020000U /*!<Bit 0 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_1 0x00040000U /*!<Bit 1 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_2 0x00080000U /*!<Bit 2 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_3 0x00100000U /*!<Bit 3 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_4 0x00200000U /*!<Bit 4 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_5 0x00400000U /*!<Bit 5 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_6 0x00800000U /*!<Bit 6 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_7 0x01000000U /*!<Bit 7 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_8 0x02000000U /*!<Bit 8 */
+#define USB_OTG_DTHRCTL_ARPEN 0x08000000U /*!< Arbiter parking enable */
+
+/******************** Bit definition forUSB_OTG_DIEPEMPMSK register ********************/
+#define USB_OTG_DIEPEMPMSK_INEPTXFEM 0x0000FFFFU /*!< IN EP Tx FIFO empty interrupt mask bits */
+
+/******************** Bit definition forUSB_OTG_DEACHINT register ********************/
+#define USB_OTG_DEACHINT_IEP1INT 0x00000002U /*!< IN endpoint 1interrupt bit */
+#define USB_OTG_DEACHINT_OEP1INT 0x00020000U /*!< OUT endpoint 1 interrupt bit */
+
+/******************** Bit definition forUSB_OTG_GCCFG register ********************/
+#define USB_OTG_GCCFG_PWRDWN 0x00010000U /*!< Power down */
+#define USB_OTG_GCCFG_VBDEN 0x00200000U /*!< USB VBUS Detection Enable */
+
+/******************** Bit definition forUSB_OTG_DEACHINTMSK register ********************/
+#define USB_OTG_DEACHINTMSK_IEP1INTM 0x00000002U /*!< IN Endpoint 1 interrupt mask bit */
+#define USB_OTG_DEACHINTMSK_OEP1INTM 0x00020000U /*!< OUT Endpoint 1 interrupt mask bit */
+
+/******************** Bit definition forUSB_OTG_CID register ********************/
+#define USB_OTG_CID_PRODUCT_ID 0xFFFFFFFFU /*!< Product ID field */
+
+/******************** Bit definition for USB_OTG_GLPMCFG register ********************/
+#define USB_OTG_GLPMCFG_LPMEN 0x00000001U /*!< LPM support enable */
+#define USB_OTG_GLPMCFG_LPMACK 0x00000002U /*!< LPM Token acknowledge enable */
+#define USB_OTG_GLPMCFG_BESL 0x0000003CU /*!< BESL value received with last ACKed LPM Token */
+#define USB_OTG_GLPMCFG_REMWAKE 0x00000040U /*!< bRemoteWake value received with last ACKed LPM Token */
+#define USB_OTG_GLPMCFG_L1SSEN 0x00000080U /*!< L1 shallow sleep enable */
+#define USB_OTG_GLPMCFG_BESLTHRS 0x00000F00U /*!< BESL threshold */
+#define USB_OTG_GLPMCFG_L1DSEN 0x00001000U /*!< L1 deep sleep enable */
+#define USB_OTG_GLPMCFG_LPMRSP 0x00006000U /*!< LPM response */
+#define USB_OTG_GLPMCFG_SLPSTS 0x00008000U /*!< Port sleep status */
+#define USB_OTG_GLPMCFG_L1RSMOK 0x00010000U /*!< Sleep State Resume OK */
+#define USB_OTG_GLPMCFG_LPMCHIDX 0x001E0000U /*!< LPM Channel Index */
+#define USB_OTG_GLPMCFG_LPMRCNT 0x00E00000U /*!< LPM retry count */
+#define USB_OTG_GLPMCFG_SNDLPM 0x01000000U /*!< Send LPM transaction */
+#define USB_OTG_GLPMCFG_LPMRCNTSTS 0x0E000000U /*!< LPM retry count status */
+#define USB_OTG_GLPMCFG_ENBESL 0x10000000U /*!< Enable best effort service latency */
+
+/******************** Bit definition forUSB_OTG_DIEPEACHMSK1 register ********************/
+#define USB_OTG_DIEPEACHMSK1_XFRCM 0x00000001U /*!< Transfer completed interrupt mask */
+#define USB_OTG_DIEPEACHMSK1_EPDM 0x00000002U /*!< Endpoint disabled interrupt mask */
+#define USB_OTG_DIEPEACHMSK1_TOM 0x00000008U /*!< Timeout condition mask (nonisochronous endpoints) */
+#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK 0x00000010U /*!< IN token received when TxFIFO empty mask */
+#define USB_OTG_DIEPEACHMSK1_INEPNMM 0x00000020U /*!< IN token received with EP mismatch mask */
+#define USB_OTG_DIEPEACHMSK1_INEPNEM 0x00000040U /*!< IN endpoint NAK effective mask */
+#define USB_OTG_DIEPEACHMSK1_TXFURM 0x00000100U /*!< FIFO underrun mask */
+#define USB_OTG_DIEPEACHMSK1_BIM 0x00000200U /*!< BNA interrupt mask */
+#define USB_OTG_DIEPEACHMSK1_NAKM 0x00002000U /*!< NAK interrupt mask */
+
+/******************** Bit definition forUSB_OTG_HPRT register ********************/
+#define USB_OTG_HPRT_PCSTS 0x00000001U /*!< Port connect status */
+#define USB_OTG_HPRT_PCDET 0x00000002U /*!< Port connect detected */
+#define USB_OTG_HPRT_PENA 0x00000004U /*!< Port enable */
+#define USB_OTG_HPRT_PENCHNG 0x00000008U /*!< Port enable/disable change */
+#define USB_OTG_HPRT_POCA 0x00000010U /*!< Port overcurrent active */
+#define USB_OTG_HPRT_POCCHNG 0x00000020U /*!< Port overcurrent change */
+#define USB_OTG_HPRT_PRES 0x00000040U /*!< Port resume */
+#define USB_OTG_HPRT_PSUSP 0x00000080U /*!< Port suspend */
+#define USB_OTG_HPRT_PRST 0x00000100U /*!< Port reset */
+
+#define USB_OTG_HPRT_PLSTS 0x00000C00U /*!< Port line status */
+#define USB_OTG_HPRT_PLSTS_0 0x00000400U /*!<Bit 0 */
+#define USB_OTG_HPRT_PLSTS_1 0x00000800U /*!<Bit 1 */
+#define USB_OTG_HPRT_PPWR 0x00001000U /*!< Port power */
+
+#define USB_OTG_HPRT_PTCTL 0x0001E000U /*!< Port test control */
+#define USB_OTG_HPRT_PTCTL_0 0x00002000U /*!<Bit 0 */
+#define USB_OTG_HPRT_PTCTL_1 0x00004000U /*!<Bit 1 */
+#define USB_OTG_HPRT_PTCTL_2 0x00008000U /*!<Bit 2 */
+#define USB_OTG_HPRT_PTCTL_3 0x00010000U /*!<Bit 3 */
+
+#define USB_OTG_HPRT_PSPD 0x00060000U /*!< Port speed */
+#define USB_OTG_HPRT_PSPD_0 0x00020000U /*!<Bit 0 */
+#define USB_OTG_HPRT_PSPD_1 0x00040000U /*!<Bit 1 */
+
+/******************** Bit definition forUSB_OTG_DOEPEACHMSK1 register ********************/
+#define USB_OTG_DOEPEACHMSK1_XFRCM 0x00000001U /*!< Transfer completed interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_EPDM 0x00000002U /*!< Endpoint disabled interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_TOM 0x00000008U /*!< Timeout condition mask */
+#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK 0x00000010U /*!< IN token received when TxFIFO empty mask */
+#define USB_OTG_DOEPEACHMSK1_INEPNMM 0x00000020U /*!< IN token received with EP mismatch mask */
+#define USB_OTG_DOEPEACHMSK1_INEPNEM 0x00000040U /*!< IN endpoint NAK effective mask */
+#define USB_OTG_DOEPEACHMSK1_TXFURM 0x00000100U /*!< OUT packet error mask */
+#define USB_OTG_DOEPEACHMSK1_BIM 0x00000200U /*!< BNA interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_BERRM 0x00001000U /*!< Bubble error interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_NAKM 0x00002000U /*!< NAK interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_NYETM 0x00004000U /*!< NYET interrupt mask */
+
+/******************** Bit definition forUSB_OTG_HPTXFSIZ register ********************/
+#define USB_OTG_HPTXFSIZ_PTXSA 0x0000FFFFU /*!< Host periodic TxFIFO start address */
+#define USB_OTG_HPTXFSIZ_PTXFD 0xFFFF0000U /*!< Host periodic TxFIFO depth */
+
+/******************** Bit definition forUSB_OTG_DIEPCTL register ********************/
+#define USB_OTG_DIEPCTL_MPSIZ 0x000007FFU /*!< Maximum packet size */
+#define USB_OTG_DIEPCTL_USBAEP 0x00008000U /*!< USB active endpoint */
+#define USB_OTG_DIEPCTL_EONUM_DPID 0x00010000U /*!< Even/odd frame */
+#define USB_OTG_DIEPCTL_NAKSTS 0x00020000U /*!< NAK status */
+
+#define USB_OTG_DIEPCTL_EPTYP 0x000C0000U /*!< Endpoint type */
+#define USB_OTG_DIEPCTL_EPTYP_0 0x00040000U /*!<Bit 0 */
+#define USB_OTG_DIEPCTL_EPTYP_1 0x00080000U /*!<Bit 1 */
+#define USB_OTG_DIEPCTL_STALL 0x00200000U /*!< STALL handshake */
+
+#define USB_OTG_DIEPCTL_TXFNUM 0x03C00000U /*!< TxFIFO number */
+#define USB_OTG_DIEPCTL_TXFNUM_0 0x00400000U /*!<Bit 0 */
+#define USB_OTG_DIEPCTL_TXFNUM_1 0x00800000U /*!<Bit 1 */
+#define USB_OTG_DIEPCTL_TXFNUM_2 0x01000000U /*!<Bit 2 */
+#define USB_OTG_DIEPCTL_TXFNUM_3 0x02000000U /*!<Bit 3 */
+#define USB_OTG_DIEPCTL_CNAK 0x04000000U /*!< Clear NAK */
+#define USB_OTG_DIEPCTL_SNAK 0x08000000U /*!< Set NAK */
+#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM 0x10000000U /*!< Set DATA0 PID */
+#define USB_OTG_DIEPCTL_SODDFRM 0x20000000U /*!< Set odd frame */
+#define USB_OTG_DIEPCTL_EPDIS 0x40000000U /*!< Endpoint disable */
+#define USB_OTG_DIEPCTL_EPENA 0x80000000U /*!< Endpoint enable */
+
+/******************** Bit definition forUSB_OTG_HCCHAR register ********************/
+#define USB_OTG_HCCHAR_MPSIZ 0x000007FFU /*!< Maximum packet size */
+
+#define USB_OTG_HCCHAR_EPNUM 0x00007800U /*!< Endpoint number */
+#define USB_OTG_HCCHAR_EPNUM_0 0x00000800U /*!<Bit 0 */
+#define USB_OTG_HCCHAR_EPNUM_1 0x00001000U /*!<Bit 1 */
+#define USB_OTG_HCCHAR_EPNUM_2 0x00002000U /*!<Bit 2 */
+#define USB_OTG_HCCHAR_EPNUM_3 0x00004000U /*!<Bit 3 */
+#define USB_OTG_HCCHAR_EPDIR 0x00008000U /*!< Endpoint direction */
+#define USB_OTG_HCCHAR_LSDEV 0x00020000U /*!< Low-speed device */
+
+#define USB_OTG_HCCHAR_EPTYP 0x000C0000U /*!< Endpoint type */
+#define USB_OTG_HCCHAR_EPTYP_0 0x00040000U /*!<Bit 0 */
+#define USB_OTG_HCCHAR_EPTYP_1 0x00080000U /*!<Bit 1 */
+
+#define USB_OTG_HCCHAR_MC 0x00300000U /*!< Multi Count (MC) / Error Count (EC) */
+#define USB_OTG_HCCHAR_MC_0 0x00100000U /*!<Bit 0 */
+#define USB_OTG_HCCHAR_MC_1 0x00200000U /*!<Bit 1 */
+
+#define USB_OTG_HCCHAR_DAD 0x1FC00000U /*!< Device address */
+#define USB_OTG_HCCHAR_DAD_0 0x00400000U /*!<Bit 0 */
+#define USB_OTG_HCCHAR_DAD_1 0x00800000U /*!<Bit 1 */
+#define USB_OTG_HCCHAR_DAD_2 0x01000000U /*!<Bit 2 */
+#define USB_OTG_HCCHAR_DAD_3 0x02000000U /*!<Bit 3 */
+#define USB_OTG_HCCHAR_DAD_4 0x04000000U /*!<Bit 4 */
+#define USB_OTG_HCCHAR_DAD_5 0x08000000U /*!<Bit 5 */
+#define USB_OTG_HCCHAR_DAD_6 0x10000000U /*!<Bit 6 */
+#define USB_OTG_HCCHAR_ODDFRM 0x20000000U /*!< Odd frame */
+#define USB_OTG_HCCHAR_CHDIS 0x40000000U /*!< Channel disable */
+#define USB_OTG_HCCHAR_CHENA 0x80000000U /*!< Channel enable */
+
+/******************** Bit definition forUSB_OTG_HCSPLT register ********************/
+
+#define USB_OTG_HCSPLT_PRTADDR 0x0000007FU /*!< Port address */
+#define USB_OTG_HCSPLT_PRTADDR_0 0x00000001U /*!<Bit 0 */
+#define USB_OTG_HCSPLT_PRTADDR_1 0x00000002U /*!<Bit 1 */
+#define USB_OTG_HCSPLT_PRTADDR_2 0x00000004U /*!<Bit 2 */
+#define USB_OTG_HCSPLT_PRTADDR_3 0x00000008U /*!<Bit 3 */
+#define USB_OTG_HCSPLT_PRTADDR_4 0x00000010U /*!<Bit 4 */
+#define USB_OTG_HCSPLT_PRTADDR_5 0x00000020U /*!<Bit 5 */
+#define USB_OTG_HCSPLT_PRTADDR_6 0x00000040U /*!<Bit 6 */
+
+#define USB_OTG_HCSPLT_HUBADDR 0x00003F80U /*!< Hub address */
+#define USB_OTG_HCSPLT_HUBADDR_0 0x00000080U /*!<Bit 0 */
+#define USB_OTG_HCSPLT_HUBADDR_1 0x00000100U /*!<Bit 1 */
+#define USB_OTG_HCSPLT_HUBADDR_2 0x00000200U /*!<Bit 2 */
+#define USB_OTG_HCSPLT_HUBADDR_3 0x00000400U /*!<Bit 3 */
+#define USB_OTG_HCSPLT_HUBADDR_4 0x00000800U /*!<Bit 4 */
+#define USB_OTG_HCSPLT_HUBADDR_5 0x00001000U /*!<Bit 5 */
+#define USB_OTG_HCSPLT_HUBADDR_6 0x00002000U /*!<Bit 6 */
+
+#define USB_OTG_HCSPLT_XACTPOS 0x0000C000U /*!< XACTPOS */
+#define USB_OTG_HCSPLT_XACTPOS_0 0x00004000U /*!<Bit 0 */
+#define USB_OTG_HCSPLT_XACTPOS_1 0x00008000U /*!<Bit 1 */
+#define USB_OTG_HCSPLT_COMPLSPLT 0x00010000U /*!< Do complete split */
+#define USB_OTG_HCSPLT_SPLITEN 0x80000000U /*!< Split enable */
+
+/******************** Bit definition forUSB_OTG_HCINT register ********************/
+#define USB_OTG_HCINT_XFRC 0x00000001U /*!< Transfer completed */
+#define USB_OTG_HCINT_CHH 0x00000002U /*!< Channel halted */
+#define USB_OTG_HCINT_AHBERR 0x00000004U /*!< AHB error */
+#define USB_OTG_HCINT_STALL 0x00000008U /*!< STALL response received interrupt */
+#define USB_OTG_HCINT_NAK 0x00000010U /*!< NAK response received interrupt */
+#define USB_OTG_HCINT_ACK 0x00000020U /*!< ACK response received/transmitted interrupt */
+#define USB_OTG_HCINT_NYET 0x00000040U /*!< Response received interrupt */
+#define USB_OTG_HCINT_TXERR 0x00000080U /*!< Transaction error */
+#define USB_OTG_HCINT_BBERR 0x00000100U /*!< Babble error */
+#define USB_OTG_HCINT_FRMOR 0x00000200U /*!< Frame overrun */
+#define USB_OTG_HCINT_DTERR 0x00000400U /*!< Data toggle error */
+
+/******************** Bit definition forUSB_OTG_DIEPINT register ********************/
+#define USB_OTG_DIEPINT_XFRC 0x00000001U /*!< Transfer completed interrupt */
+#define USB_OTG_DIEPINT_EPDISD 0x00000002U /*!< Endpoint disabled interrupt */
+#define USB_OTG_DIEPINT_TOC 0x00000008U /*!< Timeout condition */
+#define USB_OTG_DIEPINT_ITTXFE 0x00000010U /*!< IN token received when TxFIFO is empty */
+#define USB_OTG_DIEPINT_INEPNE 0x00000040U /*!< IN endpoint NAK effective */
+#define USB_OTG_DIEPINT_TXFE 0x00000080U /*!< Transmit FIFO empty */
+#define USB_OTG_DIEPINT_TXFIFOUDRN 0x00000100U /*!< Transmit Fifo Underrun */
+#define USB_OTG_DIEPINT_BNA 0x00000200U /*!< Buffer not available interrupt */
+#define USB_OTG_DIEPINT_PKTDRPSTS 0x00000800U /*!< Packet dropped status */
+#define USB_OTG_DIEPINT_BERR 0x00001000U /*!< Babble error interrupt */
+#define USB_OTG_DIEPINT_NAK 0x00002000U /*!< NAK interrupt */
+
+/******************** Bit definition forUSB_OTG_HCINTMSK register ********************/
+#define USB_OTG_HCINTMSK_XFRCM 0x00000001U /*!< Transfer completed mask */
+#define USB_OTG_HCINTMSK_CHHM 0x00000002U /*!< Channel halted mask */
+#define USB_OTG_HCINTMSK_AHBERR 0x00000004U /*!< AHB error */
+#define USB_OTG_HCINTMSK_STALLM 0x00000008U /*!< STALL response received interrupt mask */
+#define USB_OTG_HCINTMSK_NAKM 0x00000010U /*!< NAK response received interrupt mask */
+#define USB_OTG_HCINTMSK_ACKM 0x00000020U /*!< ACK response received/transmitted interrupt mask */
+#define USB_OTG_HCINTMSK_NYET 0x00000040U /*!< response received interrupt mask */
+#define USB_OTG_HCINTMSK_TXERRM 0x00000080U /*!< Transaction error mask */
+#define USB_OTG_HCINTMSK_BBERRM 0x00000100U /*!< Babble error mask */
+#define USB_OTG_HCINTMSK_FRMORM 0x00000200U /*!< Frame overrun mask */
+#define USB_OTG_HCINTMSK_DTERRM 0x00000400U /*!< Data toggle error mask */
+
+/******************** Bit definition for USB_OTG_DIEPTSIZ register ********************/
+
+#define USB_OTG_DIEPTSIZ_XFRSIZ 0x0007FFFFU /*!< Transfer size */
+#define USB_OTG_DIEPTSIZ_PKTCNT 0x1FF80000U /*!< Packet count */
+#define USB_OTG_DIEPTSIZ_MULCNT 0x60000000U /*!< Packet count */
+/******************** Bit definition forUSB_OTG_HCTSIZ register ********************/
+#define USB_OTG_HCTSIZ_XFRSIZ 0x0007FFFFU /*!< Transfer size */
+#define USB_OTG_HCTSIZ_PKTCNT 0x1FF80000U /*!< Packet count */
+#define USB_OTG_HCTSIZ_DOPING 0x80000000U /*!< Do PING */
+#define USB_OTG_HCTSIZ_DPID 0x60000000U /*!< Data PID */
+#define USB_OTG_HCTSIZ_DPID_0 0x20000000U /*!<Bit 0 */
+#define USB_OTG_HCTSIZ_DPID_1 0x40000000U /*!<Bit 1 */
+
+/******************** Bit definition forUSB_OTG_DIEPDMA register ********************/
+#define USB_OTG_DIEPDMA_DMAADDR 0xFFFFFFFFU /*!< DMA address */
+
+/******************** Bit definition forUSB_OTG_HCDMA register ********************/
+#define USB_OTG_HCDMA_DMAADDR 0xFFFFFFFFU /*!< DMA address */
+
+/******************** Bit definition forUSB_OTG_DTXFSTS register ********************/
+#define USB_OTG_DTXFSTS_INEPTFSAV 0x0000FFFFU /*!< IN endpoint TxFIFO space available */
+
+/******************** Bit definition forUSB_OTG_DIEPTXF register ********************/
+#define USB_OTG_DIEPTXF_INEPTXSA 0x0000FFFFU /*!< IN endpoint FIFOx transmit RAM start address */
+#define USB_OTG_DIEPTXF_INEPTXFD 0xFFFF0000U /*!< IN endpoint TxFIFO depth */
+
+/******************** Bit definition forUSB_OTG_DOEPCTL register ********************/
+
+#define USB_OTG_DOEPCTL_MPSIZ 0x000007FFU /*!< Maximum packet size */ /*!<Bit 1 */
+#define USB_OTG_DOEPCTL_USBAEP 0x00008000U /*!< USB active endpoint */
+#define USB_OTG_DOEPCTL_NAKSTS 0x00020000U /*!< NAK status */
+#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM 0x10000000U /*!< Set DATA0 PID */
+#define USB_OTG_DOEPCTL_SODDFRM 0x20000000U /*!< Set odd frame */
+#define USB_OTG_DOEPCTL_EPTYP 0x000C0000U /*!< Endpoint type */
+#define USB_OTG_DOEPCTL_EPTYP_0 0x00040000U /*!<Bit 0 */
+#define USB_OTG_DOEPCTL_EPTYP_1 0x00080000U /*!<Bit 1 */
+#define USB_OTG_DOEPCTL_SNPM 0x00100000U /*!< Snoop mode */
+#define USB_OTG_DOEPCTL_STALL 0x00200000U /*!< STALL handshake */
+#define USB_OTG_DOEPCTL_CNAK 0x04000000U /*!< Clear NAK */
+#define USB_OTG_DOEPCTL_SNAK 0x08000000U /*!< Set NAK */
+#define USB_OTG_DOEPCTL_EPDIS 0x40000000U /*!< Endpoint disable */
+#define USB_OTG_DOEPCTL_EPENA 0x80000000U /*!< Endpoint enable */
+
+/******************** Bit definition forUSB_OTG_DOEPINT register ********************/
+#define USB_OTG_DOEPINT_XFRC 0x00000001U /*!< Transfer completed interrupt */
+#define USB_OTG_DOEPINT_EPDISD 0x00000002U /*!< Endpoint disabled interrupt */
+#define USB_OTG_DOEPINT_STUP 0x00000008U /*!< SETUP phase done */
+#define USB_OTG_DOEPINT_OTEPDIS 0x00000010U /*!< OUT token received when endpoint disabled */
+#define USB_OTG_DOEPINT_OTEPSPR 0x00000020U /*!< Status Phase Received For Control Write */
+#define USB_OTG_DOEPINT_B2BSTUP 0x00000040U /*!< Back-to-back SETUP packets received */
+#define USB_OTG_DOEPINT_NYET 0x00004000U /*!< NYET interrupt */
+
+/******************** Bit definition forUSB_OTG_DOEPTSIZ register ********************/
+
+#define USB_OTG_DOEPTSIZ_XFRSIZ 0x0007FFFFU /*!< Transfer size */
+#define USB_OTG_DOEPTSIZ_PKTCNT 0x1FF80000U /*!< Packet count */
+
+#define USB_OTG_DOEPTSIZ_STUPCNT 0x60000000U /*!< SETUP packet count */
+#define USB_OTG_DOEPTSIZ_STUPCNT_0 0x20000000U /*!<Bit 0 */
+#define USB_OTG_DOEPTSIZ_STUPCNT_1 0x40000000U /*!<Bit 1 */
+
+/******************** Bit definition for PCGCCTL register ********************/
+#define USB_OTG_PCGCCTL_STOPCLK 0x00000001U /*!< SETUP packet count */
+#define USB_OTG_PCGCCTL_GATECLK 0x00000002U /*!<Bit 0 */
+#define USB_OTG_PCGCCTL_PHYSUSP 0x00000010U /*!<Bit 1 */
+
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup Exported_macros
+ * @{
+ */
+
+/******************************* ADC Instances ********************************/
+#define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) || \
+ ((INSTANCE) == ADC2) || \
+ ((INSTANCE) == ADC3))
+
+/******************************* CAN Instances ********************************/
+#define IS_CAN_ALL_INSTANCE(INSTANCE) (((INSTANCE) == CAN1) || \
+ ((INSTANCE) == CAN2))
+
+/******************************* CRC Instances ********************************/
+#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
+
+/******************************* DAC Instances ********************************/
+#define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC)
+
+/******************************* DCMI Instances *******************************/
+#define IS_DCMI_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DCMI)
+
+/******************************* DMA2D Instances *******************************/
+#define IS_DMA2D_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DMA2D)
+
+/******************************** DMA Instances *******************************/
+#define IS_DMA_STREAM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0) || \
+ ((INSTANCE) == DMA1_Stream1) || \
+ ((INSTANCE) == DMA1_Stream2) || \
+ ((INSTANCE) == DMA1_Stream3) || \
+ ((INSTANCE) == DMA1_Stream4) || \
+ ((INSTANCE) == DMA1_Stream5) || \
+ ((INSTANCE) == DMA1_Stream6) || \
+ ((INSTANCE) == DMA1_Stream7) || \
+ ((INSTANCE) == DMA2_Stream0) || \
+ ((INSTANCE) == DMA2_Stream1) || \
+ ((INSTANCE) == DMA2_Stream2) || \
+ ((INSTANCE) == DMA2_Stream3) || \
+ ((INSTANCE) == DMA2_Stream4) || \
+ ((INSTANCE) == DMA2_Stream5) || \
+ ((INSTANCE) == DMA2_Stream6) || \
+ ((INSTANCE) == DMA2_Stream7))
+
+/******************************* GPIO Instances *******************************/
+#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
+ ((INSTANCE) == GPIOB) || \
+ ((INSTANCE) == GPIOC) || \
+ ((INSTANCE) == GPIOD) || \
+ ((INSTANCE) == GPIOE) || \
+ ((INSTANCE) == GPIOF) || \
+ ((INSTANCE) == GPIOG) || \
+ ((INSTANCE) == GPIOH) || \
+ ((INSTANCE) == GPIOI) || \
+ ((INSTANCE) == GPIOJ) || \
+ ((INSTANCE) == GPIOK))
+
+/******************************** I2C Instances *******************************/
+#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
+ ((INSTANCE) == I2C2) || \
+ ((INSTANCE) == I2C3))
+
+/******************************** I2S Instances *******************************/
+#define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI2) || \
+ ((INSTANCE) == SPI3))
+
+/*************************** I2S Extended Instances ***************************/
+#define IS_I2S_ALL_INSTANCE_EXT(PERIPH) (((INSTANCE) == SPI2) || \
+ ((INSTANCE) == SPI3) || \
+ ((INSTANCE) == I2S2ext) || \
+ ((INSTANCE) == I2S3ext))
+
+/****************************** LTDC Instances ********************************/
+#define IS_LTDC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == LTDC)
+
+/******************************* RNG Instances ********************************/
+#define IS_RNG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RNG)
+
+/****************************** RTC Instances *********************************/
+#define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
+
+/******************************* SAI Instances ********************************/
+#define IS_SAI_ALL_INSTANCE(PERIPH) (((PERIPH) == SAI1_Block_A) || \
+ ((PERIPH) == SAI1_Block_B))
+/* Legacy define */
+#define IS_SAI_BLOCK_PERIPH IS_SAI_ALL_INSTANCE
+
+/******************************** SPI Instances *******************************/
+#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
+ ((INSTANCE) == SPI2) || \
+ ((INSTANCE) == SPI3) || \
+ ((INSTANCE) == SPI4) || \
+ ((INSTANCE) == SPI5) || \
+ ((INSTANCE) == SPI6))
+
+/*************************** SPI Extended Instances ***************************/
+#define IS_SPI_ALL_INSTANCE_EXT(INSTANCE) (((INSTANCE) == SPI1) || \
+ ((INSTANCE) == SPI2) || \
+ ((INSTANCE) == SPI3) || \
+ ((INSTANCE) == SPI4) || \
+ ((INSTANCE) == SPI5) || \
+ ((INSTANCE) == SPI6) || \
+ ((INSTANCE) == I2S2ext) || \
+ ((INSTANCE) == I2S3ext))
+
+/****************** TIM Instances : All supported instances *******************/
+#define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM6) || \
+ ((INSTANCE) == TIM7) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM9) || \
+ ((INSTANCE) == TIM10) || \
+ ((INSTANCE) == TIM11) || \
+ ((INSTANCE) == TIM12) || \
+ ((INSTANCE) == TIM13) || \
+ ((INSTANCE) == TIM14))
+
+/************* TIM Instances : at least 1 capture/compare channel *************/
+#define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM9) || \
+ ((INSTANCE) == TIM10) || \
+ ((INSTANCE) == TIM11) || \
+ ((INSTANCE) == TIM12) || \
+ ((INSTANCE) == TIM13) || \
+ ((INSTANCE) == TIM14))
+
+/************ TIM Instances : at least 2 capture/compare channels *************/
+#define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM9) || \
+ ((INSTANCE) == TIM12))
+
+/************ TIM Instances : at least 3 capture/compare channels *************/
+#define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8))
+
+/************ TIM Instances : at least 4 capture/compare channels *************/
+#define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8))
+
+/******************** TIM Instances : Advanced-control timers *****************/
+#define IS_TIM_ADVANCED_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM8))
+
+/******************* TIM Instances : Timer input XOR function *****************/
+#define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8))
+
+/****************** TIM Instances : DMA requests generation (UDE) *************/
+#define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM6) || \
+ ((INSTANCE) == TIM7) || \
+ ((INSTANCE) == TIM8))
+
+/************ TIM Instances : DMA requests generation (CCxDE) *****************/
+#define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8))
+
+/************ TIM Instances : DMA requests generation (COMDE) *****************/
+#define IS_TIM_CCDMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8))
+
+/******************** TIM Instances : DMA burst feature ***********************/
+#define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8))
+
+/****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/
+#define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM6) || \
+ ((INSTANCE) == TIM7) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM9) || \
+ ((INSTANCE) == TIM12))
+
+/*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
+#define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM9) || \
+ ((INSTANCE) == TIM12))
+
+/********************** TIM Instances : 32 bit Counter ************************/
+#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)(((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM5))
+
+/***************** TIM Instances : external trigger input availabe ************/
+#define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8))
+
+/****************** TIM Instances : remapping capability **********************/
+#define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM11))
+
+/******************* TIM Instances : output(s) available **********************/
+#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
+ ((((INSTANCE) == TIM1) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM2) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM3) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM4) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM5) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM8) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM9) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2))) \
+ || \
+ (((INSTANCE) == TIM10) && \
+ (((CHANNEL) == TIM_CHANNEL_1))) \
+ || \
+ (((INSTANCE) == TIM11) && \
+ (((CHANNEL) == TIM_CHANNEL_1))) \
+ || \
+ (((INSTANCE) == TIM12) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2))) \
+ || \
+ (((INSTANCE) == TIM13) && \
+ (((CHANNEL) == TIM_CHANNEL_1))) \
+ || \
+ (((INSTANCE) == TIM14) && \
+ (((CHANNEL) == TIM_CHANNEL_1))))
+
+/************ TIM Instances : complementary output(s) available ***************/
+#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
+ ((((INSTANCE) == TIM1) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3))) \
+ || \
+ (((INSTANCE) == TIM8) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3))))
+
+/******************** USART Instances : Synchronous mode **********************/
+#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3) || \
+ ((INSTANCE) == USART6))
+
+/******************** UART Instances : Asynchronous mode **********************/
+#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3) || \
+ ((INSTANCE) == UART4) || \
+ ((INSTANCE) == UART5) || \
+ ((INSTANCE) == USART6) || \
+ ((INSTANCE) == UART7) || \
+ ((INSTANCE) == UART8))
+
+/****************** UART Instances : Hardware Flow control ********************/
+#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3) || \
+ ((INSTANCE) == USART6))
+
+/********************* UART Instances : Smard card mode ***********************/
+#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3) || \
+ ((INSTANCE) == USART6))
+
+/*********************** UART Instances : IRDA mode ***************************/
+#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3) || \
+ ((INSTANCE) == UART4) || \
+ ((INSTANCE) == UART5) || \
+ ((INSTANCE) == USART6) || \
+ ((INSTANCE) == UART7) || \
+ ((INSTANCE) == UART8))
+
+/*********************** PCD Instances ****************************************/
+#define IS_PCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS) || \
+ ((INSTANCE) == USB_OTG_HS))
+
+/*********************** HCD Instances ****************************************/
+#define IS_HCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS) || \
+ ((INSTANCE) == USB_OTG_HS))
+
+/****************************** SDIO Instances ********************************/
+#define IS_SDIO_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SDIO)
+
+/****************************** IWDG Instances ********************************/
+#define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
+
+/****************************** WWDG Instances ********************************/
+#define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
+
+/****************************** QSPI Instances ********************************/
+#define IS_QSPI_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == QUADSPI)
+
+/****************************** USB Exported Constants ************************/
+#define USB_OTG_FS_HOST_MAX_CHANNEL_NBR 12U
+#define USB_OTG_FS_MAX_IN_ENDPOINTS 6U /* Including EP0 */
+#define USB_OTG_FS_MAX_OUT_ENDPOINTS 6U /* Including EP0 */
+#define USB_OTG_FS_TOTAL_FIFO_SIZE 1280U /* in Bytes */
+
+#define USB_OTG_HS_HOST_MAX_CHANNEL_NBR 16U
+#define USB_OTG_HS_MAX_IN_ENDPOINTS 8U /* Including EP0 */
+#define USB_OTG_HS_MAX_OUT_ENDPOINTS 8U /* Including EP0 */
+#define USB_OTG_HS_TOTAL_FIFO_SIZE 4096U /* in Bytes */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* __STM32F479xx_H */
+
+
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Device/ST/STM32F4xx/Include/stm32f4xx.h b/Device/ST/STM32F4xx/Include/stm32f4xx.h
new file mode 100644
index 0000000..d5ed788
--- /dev/null
+++ b/Device/ST/STM32F4xx/Include/stm32f4xx.h
@@ -0,0 +1,264 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx.h
+ * @author MCD Application Team
+ * @version V2.5.0
+ * @date 22-April-2016
+ * @brief CMSIS STM32F4xx Device Peripheral Access Layer Header File.
+ *
+ * The file is the unique include file that the application programmer
+ * is using in the C source code, usually in main.c. This file contains:
+ * - Configuration section that allows to select:
+ * - The STM32F4xx device used in the target application
+ * - To use or not the peripheral’s drivers in application code(i.e.
+ * code will be based on direct access to peripheral’s registers
+ * rather than drivers API), this option is controlled by
+ * "#define USE_HAL_DRIVER"
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/** @addtogroup CMSIS
+ * @{
+ */
+
+/** @addtogroup stm32f4xx
+ * @{
+ */
+
+#ifndef __STM32F4xx_H
+#define __STM32F4xx_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif /* __cplusplus */
+
+/** @addtogroup Library_configuration_section
+ * @{
+ */
+
+/**
+ * @brief STM32 Family
+ */
+#if !defined (STM32F4)
+#define STM32F4
+#endif /* STM32F4 */
+
+/* Uncomment the line below according to the target STM32 device used in your
+ application
+ */
+#if !defined (STM32F405xx) && !defined (STM32F415xx) && !defined (STM32F407xx) && !defined (STM32F417xx) && \
+ !defined (STM32F427xx) && !defined (STM32F437xx) && !defined (STM32F429xx) && !defined (STM32F439xx) && \
+ !defined (STM32F401xC) && !defined (STM32F401xE) && !defined (STM32F410Tx) && !defined (STM32F410Cx) && \
+ !defined (STM32F410Rx) && !defined (STM32F411xE) && !defined (STM32F446xx) && !defined (STM32F469xx) && \
+ !defined (STM32F479xx) && !defined (STM32F412Cx) && !defined (STM32F412Rx) && !defined (STM32F412Vx) && \
+ !defined (STM32F412Zx)
+ /* #define STM32F405xx */ /*!< STM32F405RG, STM32F405VG and STM32F405ZG Devices */
+ /* #define STM32F415xx */ /*!< STM32F415RG, STM32F415VG and STM32F415ZG Devices */
+ /* #define STM32F407xx */ /*!< STM32F407VG, STM32F407VE, STM32F407ZG, STM32F407ZE, STM32F407IG and STM32F407IE Devices */
+ /* #define STM32F417xx */ /*!< STM32F417VG, STM32F417VE, STM32F417ZG, STM32F417ZE, STM32F417IG and STM32F417IE Devices */
+ /* #define STM32F427xx */ /*!< STM32F427VG, STM32F427VI, STM32F427ZG, STM32F427ZI, STM32F427IG and STM32F427II Devices */
+ /* #define STM32F437xx */ /*!< STM32F437VG, STM32F437VI, STM32F437ZG, STM32F437ZI, STM32F437IG and STM32F437II Devices */
+ /* #define STM32F429xx */ /*!< STM32F429VG, STM32F429VI, STM32F429ZG, STM32F429ZI, STM32F429BG, STM32F429BI, STM32F429NG,
+ STM32F439NI, STM32F429IG and STM32F429II Devices */
+ /* #define STM32F439xx */ /*!< STM32F439VG, STM32F439VI, STM32F439ZG, STM32F439ZI, STM32F439BG, STM32F439BI, STM32F439NG,
+ STM32F439NI, STM32F439IG and STM32F439II Devices */
+ /* #define STM32F401xC */ /*!< STM32F401CB, STM32F401CC, STM32F401RB, STM32F401RC, STM32F401VB and STM32F401VC Devices */
+ /* #define STM32F401xE */ /*!< STM32F401CD, STM32F401RD, STM32F401VD, STM32F401CE, STM32F401RE and STM32F401VE Devices */
+ /* #define STM32F410Tx */ /*!< STM32F410T8 and STM32F410TB Devices */
+ /* #define STM32F410Cx */ /*!< STM32F410C8 and STM32F410CB Devices */
+ /* #define STM32F410Rx */ /*!< STM32F410R8 and STM32F410RB Devices */
+ /* #define STM32F411xE */ /*!< STM32F411CC, STM32F411RC, STM32F411VC, STM32F411CE, STM32F411RE and STM32F411VE Devices */
+ /* #define STM32F446xx */ /*!< STM32F446MC, STM32F446ME, STM32F446RC, STM32F446RE, STM32F446VC, STM32F446VE, STM32F446ZC,
+ and STM32F446ZE Devices */
+ /* #define STM32F469xx */ /*!< STM32F469AI, STM32F469II, STM32F469BI, STM32F469NI, STM32F469AG, STM32F469IG, STM32F469BG,
+ STM32F469NG, STM32F469AE, STM32F469IE, STM32F469BE and STM32F469NE Devices */
+ /* #define STM32F479xx */ /*!< STM32F479AI, STM32F479II, STM32F479BI, STM32F479NI, STM32F479AG, STM32F479IG, STM32F479BG
+ and STM32F479NG Devices */
+ /* #define STM32F412Cx */ /*!< STM32F412CEU and STM32F412CGU Devices */
+ /* #define STM32F412Zx */ /*!< STM32F412ZET, STM32F412ZGT, STM32F412ZEJ and STM32F412ZGJ Devices */
+ /* #define STM32F412Vx */ /*!< STM32F412VET, STM32F412VGT, STM32F412VEH and STM32F412VGH Devices */
+ /* #define STM32F412Rx */ /*!< STM32F412RET, STM32F412RGT, STM32F412REY and STM32F412RGY Devices */
+#endif
+
+/* Tip: To avoid modifying this file each time you need to switch between these
+ devices, you can define the device in your toolchain compiler preprocessor.
+ */
+#if !defined (USE_HAL_DRIVER)
+/**
+ * @brief Comment the line below if you will not use the peripherals drivers.
+ In this case, these drivers will not be included and the application code will
+ be based on direct access to peripherals registers
+ */
+ /*#define USE_HAL_DRIVER */
+#endif /* USE_HAL_DRIVER */
+
+/**
+ * @brief CMSIS version number V2.5.0
+ */
+#define __STM32F4xx_CMSIS_VERSION_MAIN (0x02U) /*!< [31:24] main version */
+#define __STM32F4xx_CMSIS_VERSION_SUB1 (0x05U) /*!< [23:16] sub1 version */
+#define __STM32F4xx_CMSIS_VERSION_SUB2 (0x00U) /*!< [15:8] sub2 version */
+#define __STM32F4xx_CMSIS_VERSION_RC (0x00U) /*!< [7:0] release candidate */
+#define __STM32F4xx_CMSIS_VERSION ((__STM32F4xx_CMSIS_VERSION_MAIN << 24)\
+ |(__STM32F4xx_CMSIS_VERSION_SUB1 << 16)\
+ |(__STM32F4xx_CMSIS_VERSION_SUB2 << 8 )\
+ |(__STM32F4xx_CMSIS_VERSION))
+
+/**
+ * @}
+ */
+
+/** @addtogroup Device_Included
+ * @{
+ */
+
+#if defined(STM32F405xx)
+ #include "stm32f405xx.h"
+#elif defined(STM32F415xx)
+ #include "stm32f415xx.h"
+#elif defined(STM32F407xx)
+ #include "stm32f407xx.h"
+#elif defined(STM32F417xx)
+ #include "stm32f417xx.h"
+#elif defined(STM32F427xx)
+ #include "stm32f427xx.h"
+#elif defined(STM32F437xx)
+ #include "stm32f437xx.h"
+#elif defined(STM32F429xx)
+ #include "stm32f429xx.h"
+#elif defined(STM32F439xx)
+ #include "stm32f439xx.h"
+#elif defined(STM32F401xC)
+ #include "stm32f401xc.h"
+#elif defined(STM32F401xE)
+ #include "stm32f401xe.h"
+#elif defined(STM32F410Tx)
+ #include "stm32f410tx.h"
+#elif defined(STM32F410Cx)
+ #include "stm32f410cx.h"
+#elif defined(STM32F410Rx)
+ #include "stm32f410rx.h"
+#elif defined(STM32F411xE)
+ #include "stm32f411xe.h"
+#elif defined(STM32F446xx)
+ #include "stm32f446xx.h"
+#elif defined(STM32F469xx)
+ #include "stm32f469xx.h"
+#elif defined(STM32F479xx)
+ #include "stm32f479xx.h"
+#elif defined(STM32F412Cx)
+ #include "stm32f412cx.h"
+#elif defined(STM32F412Zx)
+ #include "stm32f412zx.h"
+#elif defined(STM32F412Rx)
+ #include "stm32f412rx.h"
+#elif defined(STM32F412Vx)
+ #include "stm32f412vx.h"
+#else
+ #error "Please select first the target STM32F4xx device used in your application (in stm32f4xx.h file)"
+#endif
+
+/**
+ * @}
+ */
+
+/** @addtogroup Exported_types
+ * @{
+ */
+typedef enum
+{
+ RESET = 0U,
+ SET = !RESET
+} FlagStatus, ITStatus;
+
+typedef enum
+{
+ DISABLE = 0U,
+ ENABLE = !DISABLE
+} FunctionalState;
+#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
+
+typedef enum
+{
+ ERROR = 0U,
+ SUCCESS = !ERROR
+} ErrorStatus;
+
+/**
+ * @}
+ */
+
+
+/** @addtogroup Exported_macro
+ * @{
+ */
+#define SET_BIT(REG, BIT) ((REG) |= (BIT))
+
+#define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT))
+
+#define READ_BIT(REG, BIT) ((REG) & (BIT))
+
+#define CLEAR_REG(REG) ((REG) = (0x0))
+
+#define WRITE_REG(REG, VAL) ((REG) = (VAL))
+
+#define READ_REG(REG) ((REG))
+
+#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))
+
+#define POSITION_VAL(VAL) (__CLZ(__RBIT(VAL)))
+
+
+/**
+ * @}
+ */
+
+#if defined (USE_HAL_DRIVER)
+ #include "stm32f4xx_hal.h"
+#endif /* USE_HAL_DRIVER */
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* __STM32F4xx_H */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+
+
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Device/ST/STM32F4xx/Include/system_stm32f4xx.h b/Device/ST/STM32F4xx/Include/system_stm32f4xx.h
new file mode 100644
index 0000000..2a368de
--- /dev/null
+++ b/Device/ST/STM32F4xx/Include/system_stm32f4xx.h
@@ -0,0 +1,122 @@
+/**
+ ******************************************************************************
+ * @file system_stm32f4xx.h
+ * @author MCD Application Team
+ * @version V2.5.0
+ * @date 22-April-2016
+ * @brief CMSIS Cortex-M4 Device System Source File for STM32F4xx devices.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/** @addtogroup CMSIS
+ * @{
+ */
+
+/** @addtogroup stm32f4xx_system
+ * @{
+ */
+
+/**
+ * @brief Define to prevent recursive inclusion
+ */
+#ifndef __SYSTEM_STM32F4XX_H
+#define __SYSTEM_STM32F4XX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/** @addtogroup STM32F4xx_System_Includes
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+
+/** @addtogroup STM32F4xx_System_Exported_types
+ * @{
+ */
+ /* This variable is updated in three ways:
+ 1) by calling CMSIS function SystemCoreClockUpdate()
+ 2) by calling HAL API function HAL_RCC_GetSysClockFreq()
+ 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
+ Note: If you use this function to configure the system clock; then there
+ is no need to call the 2 first functions listed above, since SystemCoreClock
+ variable is updated automatically.
+ */
+extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
+
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F4xx_System_Exported_Constants
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F4xx_System_Exported_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F4xx_System_Exported_Functions
+ * @{
+ */
+
+extern void SystemInit(void);
+extern void SystemCoreClockUpdate(void);
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__SYSTEM_STM32F4XX_H */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Include/arm_common_tables.h b/Include/arm_common_tables.h
new file mode 100644
index 0000000..d5d7241
--- /dev/null
+++ b/Include/arm_common_tables.h
@@ -0,0 +1,136 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date: 19. October 2015
+* $Revision: V.1.4.5 a
+*
+* Project: CMSIS DSP Library
+* Title: arm_common_tables.h
+*
+* Description: This file has extern declaration for common tables like Bitreverse, reciprocal etc which are used across different functions
+*
+* Target Processor: Cortex-M4/Cortex-M3
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#ifndef _ARM_COMMON_TABLES_H
+#define _ARM_COMMON_TABLES_H
+
+#include "arm_math.h"
+
+extern const uint16_t armBitRevTable[1024];
+extern const q15_t armRecipTableQ15[64];
+extern const q31_t armRecipTableQ31[64];
+/* extern const q31_t realCoefAQ31[1024]; */
+/* extern const q31_t realCoefBQ31[1024]; */
+extern const float32_t twiddleCoef_16[32];
+extern const float32_t twiddleCoef_32[64];
+extern const float32_t twiddleCoef_64[128];
+extern const float32_t twiddleCoef_128[256];
+extern const float32_t twiddleCoef_256[512];
+extern const float32_t twiddleCoef_512[1024];
+extern const float32_t twiddleCoef_1024[2048];
+extern const float32_t twiddleCoef_2048[4096];
+extern const float32_t twiddleCoef_4096[8192];
+#define twiddleCoef twiddleCoef_4096
+extern const q31_t twiddleCoef_16_q31[24];
+extern const q31_t twiddleCoef_32_q31[48];
+extern const q31_t twiddleCoef_64_q31[96];
+extern const q31_t twiddleCoef_128_q31[192];
+extern const q31_t twiddleCoef_256_q31[384];
+extern const q31_t twiddleCoef_512_q31[768];
+extern const q31_t twiddleCoef_1024_q31[1536];
+extern const q31_t twiddleCoef_2048_q31[3072];
+extern const q31_t twiddleCoef_4096_q31[6144];
+extern const q15_t twiddleCoef_16_q15[24];
+extern const q15_t twiddleCoef_32_q15[48];
+extern const q15_t twiddleCoef_64_q15[96];
+extern const q15_t twiddleCoef_128_q15[192];
+extern const q15_t twiddleCoef_256_q15[384];
+extern const q15_t twiddleCoef_512_q15[768];
+extern const q15_t twiddleCoef_1024_q15[1536];
+extern const q15_t twiddleCoef_2048_q15[3072];
+extern const q15_t twiddleCoef_4096_q15[6144];
+extern const float32_t twiddleCoef_rfft_32[32];
+extern const float32_t twiddleCoef_rfft_64[64];
+extern const float32_t twiddleCoef_rfft_128[128];
+extern const float32_t twiddleCoef_rfft_256[256];
+extern const float32_t twiddleCoef_rfft_512[512];
+extern const float32_t twiddleCoef_rfft_1024[1024];
+extern const float32_t twiddleCoef_rfft_2048[2048];
+extern const float32_t twiddleCoef_rfft_4096[4096];
+
+
+/* floating-point bit reversal tables */
+#define ARMBITREVINDEXTABLE__16_TABLE_LENGTH ((uint16_t)20 )
+#define ARMBITREVINDEXTABLE__32_TABLE_LENGTH ((uint16_t)48 )
+#define ARMBITREVINDEXTABLE__64_TABLE_LENGTH ((uint16_t)56 )
+#define ARMBITREVINDEXTABLE_128_TABLE_LENGTH ((uint16_t)208 )
+#define ARMBITREVINDEXTABLE_256_TABLE_LENGTH ((uint16_t)440 )
+#define ARMBITREVINDEXTABLE_512_TABLE_LENGTH ((uint16_t)448 )
+#define ARMBITREVINDEXTABLE1024_TABLE_LENGTH ((uint16_t)1800)
+#define ARMBITREVINDEXTABLE2048_TABLE_LENGTH ((uint16_t)3808)
+#define ARMBITREVINDEXTABLE4096_TABLE_LENGTH ((uint16_t)4032)
+
+extern const uint16_t armBitRevIndexTable16[ARMBITREVINDEXTABLE__16_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable32[ARMBITREVINDEXTABLE__32_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable64[ARMBITREVINDEXTABLE__64_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable128[ARMBITREVINDEXTABLE_128_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable256[ARMBITREVINDEXTABLE_256_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable512[ARMBITREVINDEXTABLE_512_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable1024[ARMBITREVINDEXTABLE1024_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable2048[ARMBITREVINDEXTABLE2048_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable4096[ARMBITREVINDEXTABLE4096_TABLE_LENGTH];
+
+/* fixed-point bit reversal tables */
+#define ARMBITREVINDEXTABLE_FIXED___16_TABLE_LENGTH ((uint16_t)12 )
+#define ARMBITREVINDEXTABLE_FIXED___32_TABLE_LENGTH ((uint16_t)24 )
+#define ARMBITREVINDEXTABLE_FIXED___64_TABLE_LENGTH ((uint16_t)56 )
+#define ARMBITREVINDEXTABLE_FIXED__128_TABLE_LENGTH ((uint16_t)112 )
+#define ARMBITREVINDEXTABLE_FIXED__256_TABLE_LENGTH ((uint16_t)240 )
+#define ARMBITREVINDEXTABLE_FIXED__512_TABLE_LENGTH ((uint16_t)480 )
+#define ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH ((uint16_t)992 )
+#define ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH ((uint16_t)1984)
+#define ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH ((uint16_t)4032)
+
+extern const uint16_t armBitRevIndexTable_fixed_16[ARMBITREVINDEXTABLE_FIXED___16_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_32[ARMBITREVINDEXTABLE_FIXED___32_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_64[ARMBITREVINDEXTABLE_FIXED___64_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_128[ARMBITREVINDEXTABLE_FIXED__128_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_256[ARMBITREVINDEXTABLE_FIXED__256_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_512[ARMBITREVINDEXTABLE_FIXED__512_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_1024[ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_2048[ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_4096[ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH];
+
+/* Tables for Fast Math Sine and Cosine */
+extern const float32_t sinTable_f32[FAST_MATH_TABLE_SIZE + 1];
+extern const q31_t sinTable_q31[FAST_MATH_TABLE_SIZE + 1];
+extern const q15_t sinTable_q15[FAST_MATH_TABLE_SIZE + 1];
+
+#endif /* ARM_COMMON_TABLES_H */
diff --git a/Include/arm_const_structs.h b/Include/arm_const_structs.h
new file mode 100644
index 0000000..54595f5
--- /dev/null
+++ b/Include/arm_const_structs.h
@@ -0,0 +1,79 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date: 19. March 2015
+* $Revision: V.1.4.5
+*
+* Project: CMSIS DSP Library
+* Title: arm_const_structs.h
+*
+* Description: This file has constant structs that are initialized for
+* user convenience. For example, some can be given as
+* arguments to the arm_cfft_f32() function.
+*
+* Target Processor: Cortex-M4/Cortex-M3
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#ifndef _ARM_CONST_STRUCTS_H
+#define _ARM_CONST_STRUCTS_H
+
+#include "arm_math.h"
+#include "arm_common_tables.h"
+
+ extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len16;
+ extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len32;
+ extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len64;
+ extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len128;
+ extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len256;
+ extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len512;
+ extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len1024;
+ extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len2048;
+ extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len4096;
+
+ extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len16;
+ extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len32;
+ extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len64;
+ extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len128;
+ extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len256;
+ extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len512;
+ extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len1024;
+ extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len2048;
+ extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len4096;
+
+ extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len16;
+ extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len32;
+ extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len64;
+ extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len128;
+ extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len256;
+ extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len512;
+ extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len1024;
+ extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len2048;
+ extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len4096;
+
+#endif
diff --git a/Include/arm_math.h b/Include/arm_math.h
new file mode 100644
index 0000000..580cbbd
--- /dev/null
+++ b/Include/arm_math.h
@@ -0,0 +1,7154 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2015 ARM Limited. All rights reserved.
+*
+* $Date: 20. October 2015
+* $Revision: V1.4.5 b
+*
+* Project: CMSIS DSP Library
+* Title: arm_math.h
+*
+* Description: Public header file for CMSIS DSP Library
+*
+* Target Processor: Cortex-M7/Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+ * -------------------------------------------------------------------- */
+
+/**
+ \mainpage CMSIS DSP Software Library
+ *
+ * Introduction
+ * ------------
+ *
+ * This user manual describes the CMSIS DSP software library,
+ * a suite of common signal processing functions for use on Cortex-M processor based devices.
+ *
+ * The library is divided into a number of functions each covering a specific category:
+ * - Basic math functions
+ * - Fast math functions
+ * - Complex math functions
+ * - Filters
+ * - Matrix functions
+ * - Transforms
+ * - Motor control functions
+ * - Statistical functions
+ * - Support functions
+ * - Interpolation functions
+ *
+ * The library has separate functions for operating on 8-bit integers, 16-bit integers,
+ * 32-bit integer and 32-bit floating-point values.
+ *
+ * Using the Library
+ * ------------
+ *
+ * The library installer contains prebuilt versions of the libraries in the <code>Lib</code> folder.
+ * - arm_cortexM7lfdp_math.lib (Little endian and Double Precision Floating Point Unit on Cortex-M7)
+ * - arm_cortexM7bfdp_math.lib (Big endian and Double Precision Floating Point Unit on Cortex-M7)
+ * - arm_cortexM7lfsp_math.lib (Little endian and Single Precision Floating Point Unit on Cortex-M7)
+ * - arm_cortexM7bfsp_math.lib (Big endian and Single Precision Floating Point Unit on Cortex-M7)
+ * - arm_cortexM7l_math.lib (Little endian on Cortex-M7)
+ * - arm_cortexM7b_math.lib (Big endian on Cortex-M7)
+ * - arm_cortexM4lf_math.lib (Little endian and Floating Point Unit on Cortex-M4)
+ * - arm_cortexM4bf_math.lib (Big endian and Floating Point Unit on Cortex-M4)
+ * - arm_cortexM4l_math.lib (Little endian on Cortex-M4)
+ * - arm_cortexM4b_math.lib (Big endian on Cortex-M4)
+ * - arm_cortexM3l_math.lib (Little endian on Cortex-M3)
+ * - arm_cortexM3b_math.lib (Big endian on Cortex-M3)
+ * - arm_cortexM0l_math.lib (Little endian on Cortex-M0 / CortexM0+)
+ * - arm_cortexM0b_math.lib (Big endian on Cortex-M0 / CortexM0+)
+ *
+ * The library functions are declared in the public file <code>arm_math.h</code> which is placed in the <code>Include</code> folder.
+ * Simply include this file and link the appropriate library in the application and begin calling the library functions. The Library supports single
+ * public header file <code> arm_math.h</code> for Cortex-M7/M4/M3/M0/M0+ with little endian and big endian. Same header file will be used for floating point unit(FPU) variants.
+ * Define the appropriate pre processor MACRO ARM_MATH_CM7 or ARM_MATH_CM4 or ARM_MATH_CM3 or
+ * ARM_MATH_CM0 or ARM_MATH_CM0PLUS depending on the target processor in the application.
+ *
+ * Examples
+ * --------
+ *
+ * The library ships with a number of examples which demonstrate how to use the library functions.
+ *
+ * Toolchain Support
+ * ------------
+ *
+ * The library has been developed and tested with MDK-ARM version 5.14.0.0
+ * The library is being tested in GCC and IAR toolchains and updates on this activity will be made available shortly.
+ *
+ * Building the Library
+ * ------------
+ *
+ * The library installer contains a project file to re build libraries on MDK-ARM Tool chain in the <code>CMSIS\\DSP_Lib\\Source\\ARM</code> folder.
+ * - arm_cortexM_math.uvprojx
+ *
+ *
+ * The libraries can be built by opening the arm_cortexM_math.uvprojx project in MDK-ARM, selecting a specific target, and defining the optional pre processor MACROs detailed above.
+ *
+ * Pre-processor Macros
+ * ------------
+ *
+ * Each library project have differant pre-processor macros.
+ *
+ * - UNALIGNED_SUPPORT_DISABLE:
+ *
+ * Define macro UNALIGNED_SUPPORT_DISABLE, If the silicon does not support unaligned memory access
+ *
+ * - ARM_MATH_BIG_ENDIAN:
+ *
+ * Define macro ARM_MATH_BIG_ENDIAN to build the library for big endian targets. By default library builds for little endian targets.
+ *
+ * - ARM_MATH_MATRIX_CHECK:
+ *
+ * Define macro ARM_MATH_MATRIX_CHECK for checking on the input and output sizes of matrices
+ *
+ * - ARM_MATH_ROUNDING:
+ *
+ * Define macro ARM_MATH_ROUNDING for rounding on support functions
+ *
+ * - ARM_MATH_CMx:
+ *
+ * Define macro ARM_MATH_CM4 for building the library on Cortex-M4 target, ARM_MATH_CM3 for building library on Cortex-M3 target
+ * and ARM_MATH_CM0 for building library on Cortex-M0 target, ARM_MATH_CM0PLUS for building library on Cortex-M0+ target, and
+ * ARM_MATH_CM7 for building the library on cortex-M7.
+ *
+ * - __FPU_PRESENT:
+ *
+ * Initialize macro __FPU_PRESENT = 1 when building on FPU supported Targets. Enable this macro for M4bf and M4lf libraries
+ *
+ * <hr>
+ * CMSIS-DSP in ARM::CMSIS Pack
+ * -----------------------------
+ *
+ * The following files relevant to CMSIS-DSP are present in the <b>ARM::CMSIS</b> Pack directories:
+ * |File/Folder |Content |
+ * |------------------------------|------------------------------------------------------------------------|
+ * |\b CMSIS\\Documentation\\DSP | This documentation |
+ * |\b CMSIS\\DSP_Lib | Software license agreement (license.txt) |
+ * |\b CMSIS\\DSP_Lib\\Examples | Example projects demonstrating the usage of the library functions |
+ * |\b CMSIS\\DSP_Lib\\Source | Source files for rebuilding the library |
+ *
+ * <hr>
+ * Revision History of CMSIS-DSP
+ * ------------
+ * Please refer to \ref ChangeLog_pg.
+ *
+ * Copyright Notice
+ * ------------
+ *
+ * Copyright (C) 2010-2015 ARM Limited. All rights reserved.
+ */
+
+
+/**
+ * @defgroup groupMath Basic Math Functions
+ */
+
+/**
+ * @defgroup groupFastMath Fast Math Functions
+ * This set of functions provides a fast approximation to sine, cosine, and square root.
+ * As compared to most of the other functions in the CMSIS math library, the fast math functions
+ * operate on individual values and not arrays.
+ * There are separate functions for Q15, Q31, and floating-point data.
+ *
+ */
+
+/**
+ * @defgroup groupCmplxMath Complex Math Functions
+ * This set of functions operates on complex data vectors.
+ * The data in the complex arrays is stored in an interleaved fashion
+ * (real, imag, real, imag, ...).
+ * In the API functions, the number of samples in a complex array refers
+ * to the number of complex values; the array contains twice this number of
+ * real values.
+ */
+
+/**
+ * @defgroup groupFilters Filtering Functions
+ */
+
+/**
+ * @defgroup groupMatrix Matrix Functions
+ *
+ * This set of functions provides basic matrix math operations.
+ * The functions operate on matrix data structures. For example,
+ * the type
+ * definition for the floating-point matrix structure is shown
+ * below:
+ * <pre>
+ * typedef struct
+ * {
+ * uint16_t numRows; // number of rows of the matrix.
+ * uint16_t numCols; // number of columns of the matrix.
+ * float32_t *pData; // points to the data of the matrix.
+ * } arm_matrix_instance_f32;
+ * </pre>
+ * There are similar definitions for Q15 and Q31 data types.
+ *
+ * The structure specifies the size of the matrix and then points to
+ * an array of data. The array is of size <code>numRows X numCols</code>
+ * and the values are arranged in row order. That is, the
+ * matrix element (i, j) is stored at:
+ * <pre>
+ * pData[i*numCols + j]
+ * </pre>
+ *
+ * \par Init Functions
+ * There is an associated initialization function for each type of matrix
+ * data structure.
+ * The initialization function sets the values of the internal structure fields.
+ * Refer to the function <code>arm_mat_init_f32()</code>, <code>arm_mat_init_q31()</code>
+ * and <code>arm_mat_init_q15()</code> for floating-point, Q31 and Q15 types, respectively.
+ *
+ * \par
+ * Use of the initialization function is optional. However, if initialization function is used
+ * then the instance structure cannot be placed into a const data section.
+ * To place the instance structure in a const data
+ * section, manually initialize the data structure. For example:
+ * <pre>
+ * <code>arm_matrix_instance_f32 S = {nRows, nColumns, pData};</code>
+ * <code>arm_matrix_instance_q31 S = {nRows, nColumns, pData};</code>
+ * <code>arm_matrix_instance_q15 S = {nRows, nColumns, pData};</code>
+ * </pre>
+ * where <code>nRows</code> specifies the number of rows, <code>nColumns</code>
+ * specifies the number of columns, and <code>pData</code> points to the
+ * data array.
+ *
+ * \par Size Checking
+ * By default all of the matrix functions perform size checking on the input and
+ * output matrices. For example, the matrix addition function verifies that the
+ * two input matrices and the output matrix all have the same number of rows and
+ * columns. If the size check fails the functions return:
+ * <pre>
+ * ARM_MATH_SIZE_MISMATCH
+ * </pre>
+ * Otherwise the functions return
+ * <pre>
+ * ARM_MATH_SUCCESS
+ * </pre>
+ * There is some overhead associated with this matrix size checking.
+ * The matrix size checking is enabled via the \#define
+ * <pre>
+ * ARM_MATH_MATRIX_CHECK
+ * </pre>
+ * within the library project settings. By default this macro is defined
+ * and size checking is enabled. By changing the project settings and
+ * undefining this macro size checking is eliminated and the functions
+ * run a bit faster. With size checking disabled the functions always
+ * return <code>ARM_MATH_SUCCESS</code>.
+ */
+
+/**
+ * @defgroup groupTransforms Transform Functions
+ */
+
+/**
+ * @defgroup groupController Controller Functions
+ */
+
+/**
+ * @defgroup groupStats Statistics Functions
+ */
+/**
+ * @defgroup groupSupport Support Functions
+ */
+
+/**
+ * @defgroup groupInterpolation Interpolation Functions
+ * These functions perform 1- and 2-dimensional interpolation of data.
+ * Linear interpolation is used for 1-dimensional data and
+ * bilinear interpolation is used for 2-dimensional data.
+ */
+
+/**
+ * @defgroup groupExamples Examples
+ */
+#ifndef _ARM_MATH_H
+#define _ARM_MATH_H
+
+/* ignore some GCC warnings */
+#if defined ( __GNUC__ )
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wsign-conversion"
+#pragma GCC diagnostic ignored "-Wconversion"
+#pragma GCC diagnostic ignored "-Wunused-parameter"
+#endif
+
+#define __CMSIS_GENERIC /* disable NVIC and Systick functions */
+
+#if defined(ARM_MATH_CM7)
+ #include "core_cm7.h"
+#elif defined (ARM_MATH_CM4)
+ #include "core_cm4.h"
+#elif defined (ARM_MATH_CM3)
+ #include "core_cm3.h"
+#elif defined (ARM_MATH_CM0)
+ #include "core_cm0.h"
+ #define ARM_MATH_CM0_FAMILY
+#elif defined (ARM_MATH_CM0PLUS)
+ #include "core_cm0plus.h"
+ #define ARM_MATH_CM0_FAMILY
+#else
+ #error "Define according the used Cortex core ARM_MATH_CM7, ARM_MATH_CM4, ARM_MATH_CM3, ARM_MATH_CM0PLUS or ARM_MATH_CM0"
+#endif
+
+#undef __CMSIS_GENERIC /* enable NVIC and Systick functions */
+#include "string.h"
+#include "math.h"
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+
+ /**
+ * @brief Macros required for reciprocal calculation in Normalized LMS
+ */
+
+#define DELTA_Q31 (0x100)
+#define DELTA_Q15 0x5
+#define INDEX_MASK 0x0000003F
+#ifndef PI
+#define PI 3.14159265358979f
+#endif
+
+ /**
+ * @brief Macros required for SINE and COSINE Fast math approximations
+ */
+
+#define FAST_MATH_TABLE_SIZE 512
+#define FAST_MATH_Q31_SHIFT (32 - 10)
+#define FAST_MATH_Q15_SHIFT (16 - 10)
+#define CONTROLLER_Q31_SHIFT (32 - 9)
+#define TABLE_SIZE 256
+#define TABLE_SPACING_Q31 0x400000
+#define TABLE_SPACING_Q15 0x80
+
+ /**
+ * @brief Macros required for SINE and COSINE Controller functions
+ */
+ /* 1.31(q31) Fixed value of 2/360 */
+ /* -1 to +1 is divided into 360 values so total spacing is (2/360) */
+#define INPUT_SPACING 0xB60B61
+
+ /**
+ * @brief Macro for Unaligned Support
+ */
+#ifndef UNALIGNED_SUPPORT_DISABLE
+ #define ALIGN4
+#else
+ #if defined (__GNUC__)
+ #define ALIGN4 __attribute__((aligned(4)))
+ #else
+ #define ALIGN4 __align(4)
+ #endif
+#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */
+
+ /**
+ * @brief Error status returned by some functions in the library.
+ */
+
+ typedef enum
+ {
+ ARM_MATH_SUCCESS = 0, /**< No error */
+ ARM_MATH_ARGUMENT_ERROR = -1, /**< One or more arguments are incorrect */
+ ARM_MATH_LENGTH_ERROR = -2, /**< Length of data buffer is incorrect */
+ ARM_MATH_SIZE_MISMATCH = -3, /**< Size of matrices is not compatible with the operation. */
+ ARM_MATH_NANINF = -4, /**< Not-a-number (NaN) or infinity is generated */
+ ARM_MATH_SINGULAR = -5, /**< Generated by matrix inversion if the input matrix is singular and cannot be inverted. */
+ ARM_MATH_TEST_FAILURE = -6 /**< Test Failed */
+ } arm_status;
+
+ /**
+ * @brief 8-bit fractional data type in 1.7 format.
+ */
+ typedef int8_t q7_t;
+
+ /**
+ * @brief 16-bit fractional data type in 1.15 format.
+ */
+ typedef int16_t q15_t;
+
+ /**
+ * @brief 32-bit fractional data type in 1.31 format.
+ */
+ typedef int32_t q31_t;
+
+ /**
+ * @brief 64-bit fractional data type in 1.63 format.
+ */
+ typedef int64_t q63_t;
+
+ /**
+ * @brief 32-bit floating-point type definition.
+ */
+ typedef float float32_t;
+
+ /**
+ * @brief 64-bit floating-point type definition.
+ */
+ typedef double float64_t;
+
+ /**
+ * @brief definition to read/write two 16 bit values.
+ */
+#if defined __CC_ARM
+ #define __SIMD32_TYPE int32_t __packed
+ #define CMSIS_UNUSED __attribute__((unused))
+
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #define __SIMD32_TYPE int32_t
+ #define CMSIS_UNUSED __attribute__((unused))
+
+#elif defined __GNUC__
+ #define __SIMD32_TYPE int32_t
+ #define CMSIS_UNUSED __attribute__((unused))
+
+#elif defined __ICCARM__
+ #define __SIMD32_TYPE int32_t __packed
+ #define CMSIS_UNUSED
+
+#elif defined __CSMC__
+ #define __SIMD32_TYPE int32_t
+ #define CMSIS_UNUSED
+
+#elif defined __TASKING__
+ #define __SIMD32_TYPE __unaligned int32_t
+ #define CMSIS_UNUSED
+
+#else
+ #error Unknown compiler
+#endif
+
+#define __SIMD32(addr) (*(__SIMD32_TYPE **) & (addr))
+#define __SIMD32_CONST(addr) ((__SIMD32_TYPE *)(addr))
+#define _SIMD32_OFFSET(addr) (*(__SIMD32_TYPE *) (addr))
+#define __SIMD64(addr) (*(int64_t **) & (addr))
+
+#if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY)
+ /**
+ * @brief definition to pack two 16 bit values.
+ */
+#define __PKHBT(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0x0000FFFF) | \
+ (((int32_t)(ARG2) << ARG3) & (int32_t)0xFFFF0000) )
+#define __PKHTB(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0xFFFF0000) | \
+ (((int32_t)(ARG2) >> ARG3) & (int32_t)0x0000FFFF) )
+
+#endif
+
+
+ /**
+ * @brief definition to pack four 8 bit values.
+ */
+#ifndef ARM_MATH_BIG_ENDIAN
+
+#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v0) << 0) & (int32_t)0x000000FF) | \
+ (((int32_t)(v1) << 8) & (int32_t)0x0000FF00) | \
+ (((int32_t)(v2) << 16) & (int32_t)0x00FF0000) | \
+ (((int32_t)(v3) << 24) & (int32_t)0xFF000000) )
+#else
+
+#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v3) << 0) & (int32_t)0x000000FF) | \
+ (((int32_t)(v2) << 8) & (int32_t)0x0000FF00) | \
+ (((int32_t)(v1) << 16) & (int32_t)0x00FF0000) | \
+ (((int32_t)(v0) << 24) & (int32_t)0xFF000000) )
+
+#endif
+
+
+ /**
+ * @brief Clips Q63 to Q31 values.
+ */
+ static __INLINE q31_t clip_q63_to_q31(
+ q63_t x)
+ {
+ return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ?
+ ((0x7FFFFFFF ^ ((q31_t) (x >> 63)))) : (q31_t) x;
+ }
+
+ /**
+ * @brief Clips Q63 to Q15 values.
+ */
+ static __INLINE q15_t clip_q63_to_q15(
+ q63_t x)
+ {
+ return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ?
+ ((0x7FFF ^ ((q15_t) (x >> 63)))) : (q15_t) (x >> 15);
+ }
+
+ /**
+ * @brief Clips Q31 to Q7 values.
+ */
+ static __INLINE q7_t clip_q31_to_q7(
+ q31_t x)
+ {
+ return ((q31_t) (x >> 24) != ((q31_t) x >> 23)) ?
+ ((0x7F ^ ((q7_t) (x >> 31)))) : (q7_t) x;
+ }
+
+ /**
+ * @brief Clips Q31 to Q15 values.
+ */
+ static __INLINE q15_t clip_q31_to_q15(
+ q31_t x)
+ {
+ return ((q31_t) (x >> 16) != ((q31_t) x >> 15)) ?
+ ((0x7FFF ^ ((q15_t) (x >> 31)))) : (q15_t) x;
+ }
+
+ /**
+ * @brief Multiplies 32 X 64 and returns 32 bit result in 2.30 format.
+ */
+
+ static __INLINE q63_t mult32x64(
+ q63_t x,
+ q31_t y)
+ {
+ return ((((q63_t) (x & 0x00000000FFFFFFFF) * y) >> 32) +
+ (((q63_t) (x >> 32) * y)));
+ }
+
+/*
+ #if defined (ARM_MATH_CM0_FAMILY) && defined ( __CC_ARM )
+ #define __CLZ __clz
+ #endif
+ */
+/* note: function can be removed when all toolchain support __CLZ for Cortex-M0 */
+#if defined (ARM_MATH_CM0_FAMILY) && ((defined (__ICCARM__)) )
+ static __INLINE uint32_t __CLZ(
+ q31_t data);
+
+ static __INLINE uint32_t __CLZ(
+ q31_t data)
+ {
+ uint32_t count = 0;
+ uint32_t mask = 0x80000000;
+
+ while((data & mask) == 0)
+ {
+ count += 1u;
+ mask = mask >> 1u;
+ }
+
+ return (count);
+ }
+#endif
+
+ /**
+ * @brief Function to Calculates 1/in (reciprocal) value of Q31 Data type.
+ */
+
+ static __INLINE uint32_t arm_recip_q31(
+ q31_t in,
+ q31_t * dst,
+ q31_t * pRecipTable)
+ {
+ q31_t out;
+ uint32_t tempVal;
+ uint32_t index, i;
+ uint32_t signBits;
+
+ if(in > 0)
+ {
+ signBits = ((uint32_t) (__CLZ( in) - 1));
+ }
+ else
+ {
+ signBits = ((uint32_t) (__CLZ(-in) - 1));
+ }
+
+ /* Convert input sample to 1.31 format */
+ in = (in << signBits);
+
+ /* calculation of index for initial approximated Val */
+ index = (uint32_t)(in >> 24);
+ index = (index & INDEX_MASK);
+
+ /* 1.31 with exp 1 */
+ out = pRecipTable[index];
+
+ /* calculation of reciprocal value */
+ /* running approximation for two iterations */
+ for (i = 0u; i < 2u; i++)
+ {
+ tempVal = (uint32_t) (((q63_t) in * out) >> 31);
+ tempVal = 0x7FFFFFFFu - tempVal;
+ /* 1.31 with exp 1 */
+ /* out = (q31_t) (((q63_t) out * tempVal) >> 30); */
+ out = clip_q63_to_q31(((q63_t) out * tempVal) >> 30);
+ }
+
+ /* write output */
+ *dst = out;
+
+ /* return num of signbits of out = 1/in value */
+ return (signBits + 1u);
+ }
+
+
+ /**
+ * @brief Function to Calculates 1/in (reciprocal) value of Q15 Data type.
+ */
+ static __INLINE uint32_t arm_recip_q15(
+ q15_t in,
+ q15_t * dst,
+ q15_t * pRecipTable)
+ {
+ q15_t out = 0;
+ uint32_t tempVal = 0;
+ uint32_t index = 0, i = 0;
+ uint32_t signBits = 0;
+
+ if(in > 0)
+ {
+ signBits = ((uint32_t)(__CLZ( in) - 17));
+ }
+ else
+ {
+ signBits = ((uint32_t)(__CLZ(-in) - 17));
+ }
+
+ /* Convert input sample to 1.15 format */
+ in = (in << signBits);
+
+ /* calculation of index for initial approximated Val */
+ index = (uint32_t)(in >> 8);
+ index = (index & INDEX_MASK);
+
+ /* 1.15 with exp 1 */
+ out = pRecipTable[index];
+
+ /* calculation of reciprocal value */
+ /* running approximation for two iterations */
+ for (i = 0u; i < 2u; i++)
+ {
+ tempVal = (uint32_t) (((q31_t) in * out) >> 15);
+ tempVal = 0x7FFFu - tempVal;
+ /* 1.15 with exp 1 */
+ out = (q15_t) (((q31_t) out * tempVal) >> 14);
+ /* out = clip_q31_to_q15(((q31_t) out * tempVal) >> 14); */
+ }
+
+ /* write output */
+ *dst = out;
+
+ /* return num of signbits of out = 1/in value */
+ return (signBits + 1);
+ }
+
+
+ /*
+ * @brief C custom defined intrinisic function for only M0 processors
+ */
+#if defined(ARM_MATH_CM0_FAMILY)
+ static __INLINE q31_t __SSAT(
+ q31_t x,
+ uint32_t y)
+ {
+ int32_t posMax, negMin;
+ uint32_t i;
+
+ posMax = 1;
+ for (i = 0; i < (y - 1); i++)
+ {
+ posMax = posMax * 2;
+ }
+
+ if(x > 0)
+ {
+ posMax = (posMax - 1);
+
+ if(x > posMax)
+ {
+ x = posMax;
+ }
+ }
+ else
+ {
+ negMin = -posMax;
+
+ if(x < negMin)
+ {
+ x = negMin;
+ }
+ }
+ return (x);
+ }
+#endif /* end of ARM_MATH_CM0_FAMILY */
+
+
+ /*
+ * @brief C custom defined intrinsic function for M3 and M0 processors
+ */
+#if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY)
+
+ /*
+ * @brief C custom defined QADD8 for M3 and M0 processors
+ */
+ static __INLINE uint32_t __QADD8(
+ uint32_t x,
+ uint32_t y)
+ {
+ q31_t r, s, t, u;
+
+ r = __SSAT(((((q31_t)x << 24) >> 24) + (((q31_t)y << 24) >> 24)), 8) & (int32_t)0x000000FF;
+ s = __SSAT(((((q31_t)x << 16) >> 24) + (((q31_t)y << 16) >> 24)), 8) & (int32_t)0x000000FF;
+ t = __SSAT(((((q31_t)x << 8) >> 24) + (((q31_t)y << 8) >> 24)), 8) & (int32_t)0x000000FF;
+ u = __SSAT(((((q31_t)x ) >> 24) + (((q31_t)y ) >> 24)), 8) & (int32_t)0x000000FF;
+
+ return ((uint32_t)((u << 24) | (t << 16) | (s << 8) | (r )));
+ }
+
+
+ /*
+ * @brief C custom defined QSUB8 for M3 and M0 processors
+ */
+ static __INLINE uint32_t __QSUB8(
+ uint32_t x,
+ uint32_t y)
+ {
+ q31_t r, s, t, u;
+
+ r = __SSAT(((((q31_t)x << 24) >> 24) - (((q31_t)y << 24) >> 24)), 8) & (int32_t)0x000000FF;
+ s = __SSAT(((((q31_t)x << 16) >> 24) - (((q31_t)y << 16) >> 24)), 8) & (int32_t)0x000000FF;
+ t = __SSAT(((((q31_t)x << 8) >> 24) - (((q31_t)y << 8) >> 24)), 8) & (int32_t)0x000000FF;
+ u = __SSAT(((((q31_t)x ) >> 24) - (((q31_t)y ) >> 24)), 8) & (int32_t)0x000000FF;
+
+ return ((uint32_t)((u << 24) | (t << 16) | (s << 8) | (r )));
+ }
+
+
+ /*
+ * @brief C custom defined QADD16 for M3 and M0 processors
+ */
+ static __INLINE uint32_t __QADD16(
+ uint32_t x,
+ uint32_t y)
+ {
+/* q31_t r, s; without initialisation 'arm_offset_q15 test' fails but 'intrinsic' tests pass! for armCC */
+ q31_t r = 0, s = 0;
+
+ r = __SSAT(((((q31_t)x << 16) >> 16) + (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF;
+ s = __SSAT(((((q31_t)x ) >> 16) + (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF;
+
+ return ((uint32_t)((s << 16) | (r )));
+ }
+
+
+ /*
+ * @brief C custom defined SHADD16 for M3 and M0 processors
+ */
+ static __INLINE uint32_t __SHADD16(
+ uint32_t x,
+ uint32_t y)
+ {
+ q31_t r, s;
+
+ r = (((((q31_t)x << 16) >> 16) + (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF;
+ s = (((((q31_t)x ) >> 16) + (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF;
+
+ return ((uint32_t)((s << 16) | (r )));
+ }
+
+
+ /*
+ * @brief C custom defined QSUB16 for M3 and M0 processors
+ */
+ static __INLINE uint32_t __QSUB16(
+ uint32_t x,
+ uint32_t y)
+ {
+ q31_t r, s;
+
+ r = __SSAT(((((q31_t)x << 16) >> 16) - (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF;
+ s = __SSAT(((((q31_t)x ) >> 16) - (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF;
+
+ return ((uint32_t)((s << 16) | (r )));
+ }
+
+
+ /*
+ * @brief C custom defined SHSUB16 for M3 and M0 processors
+ */
+ static __INLINE uint32_t __SHSUB16(
+ uint32_t x,
+ uint32_t y)
+ {
+ q31_t r, s;
+
+ r = (((((q31_t)x << 16) >> 16) - (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF;
+ s = (((((q31_t)x ) >> 16) - (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF;
+
+ return ((uint32_t)((s << 16) | (r )));
+ }
+
+
+ /*
+ * @brief C custom defined QASX for M3 and M0 processors
+ */
+ static __INLINE uint32_t __QASX(
+ uint32_t x,
+ uint32_t y)
+ {
+ q31_t r, s;
+
+ r = __SSAT(((((q31_t)x << 16) >> 16) - (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF;
+ s = __SSAT(((((q31_t)x ) >> 16) + (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF;
+
+ return ((uint32_t)((s << 16) | (r )));
+ }
+
+
+ /*
+ * @brief C custom defined SHASX for M3 and M0 processors
+ */
+ static __INLINE uint32_t __SHASX(
+ uint32_t x,
+ uint32_t y)
+ {
+ q31_t r, s;
+
+ r = (((((q31_t)x << 16) >> 16) - (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF;
+ s = (((((q31_t)x ) >> 16) + (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF;
+
+ return ((uint32_t)((s << 16) | (r )));
+ }
+
+
+ /*
+ * @brief C custom defined QSAX for M3 and M0 processors
+ */
+ static __INLINE uint32_t __QSAX(
+ uint32_t x,
+ uint32_t y)
+ {
+ q31_t r, s;
+
+ r = __SSAT(((((q31_t)x << 16) >> 16) + (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF;
+ s = __SSAT(((((q31_t)x ) >> 16) - (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF;
+
+ return ((uint32_t)((s << 16) | (r )));
+ }
+
+
+ /*
+ * @brief C custom defined SHSAX for M3 and M0 processors
+ */
+ static __INLINE uint32_t __SHSAX(
+ uint32_t x,
+ uint32_t y)
+ {
+ q31_t r, s;
+
+ r = (((((q31_t)x << 16) >> 16) + (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF;
+ s = (((((q31_t)x ) >> 16) - (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF;
+
+ return ((uint32_t)((s << 16) | (r )));
+ }
+
+
+ /*
+ * @brief C custom defined SMUSDX for M3 and M0 processors
+ */
+ static __INLINE uint32_t __SMUSDX(
+ uint32_t x,
+ uint32_t y)
+ {
+ return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) -
+ ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) ));
+ }
+
+ /*
+ * @brief C custom defined SMUADX for M3 and M0 processors
+ */
+ static __INLINE uint32_t __SMUADX(
+ uint32_t x,
+ uint32_t y)
+ {
+ return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) +
+ ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) ));
+ }
+
+
+ /*
+ * @brief C custom defined QADD for M3 and M0 processors
+ */
+ static __INLINE int32_t __QADD(
+ int32_t x,
+ int32_t y)
+ {
+ return ((int32_t)(clip_q63_to_q31((q63_t)x + (q31_t)y)));
+ }
+
+
+ /*
+ * @brief C custom defined QSUB for M3 and M0 processors
+ */
+ static __INLINE int32_t __QSUB(
+ int32_t x,
+ int32_t y)
+ {
+ return ((int32_t)(clip_q63_to_q31((q63_t)x - (q31_t)y)));
+ }
+
+
+ /*
+ * @brief C custom defined SMLAD for M3 and M0 processors
+ */
+ static __INLINE uint32_t __SMLAD(
+ uint32_t x,
+ uint32_t y,
+ uint32_t sum)
+ {
+ return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) +
+ ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) +
+ ( ((q31_t)sum ) ) ));
+ }
+
+
+ /*
+ * @brief C custom defined SMLADX for M3 and M0 processors
+ */
+ static __INLINE uint32_t __SMLADX(
+ uint32_t x,
+ uint32_t y,
+ uint32_t sum)
+ {
+ return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) +
+ ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) +
+ ( ((q31_t)sum ) ) ));
+ }
+
+
+ /*
+ * @brief C custom defined SMLSDX for M3 and M0 processors
+ */
+ static __INLINE uint32_t __SMLSDX(
+ uint32_t x,
+ uint32_t y,
+ uint32_t sum)
+ {
+ return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) -
+ ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) +
+ ( ((q31_t)sum ) ) ));
+ }
+
+
+ /*
+ * @brief C custom defined SMLALD for M3 and M0 processors
+ */
+ static __INLINE uint64_t __SMLALD(
+ uint32_t x,
+ uint32_t y,
+ uint64_t sum)
+ {
+/* return (sum + ((q15_t) (x >> 16) * (q15_t) (y >> 16)) + ((q15_t) x * (q15_t) y)); */
+ return ((uint64_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) +
+ ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) +
+ ( ((q63_t)sum ) ) ));
+ }
+
+
+ /*
+ * @brief C custom defined SMLALDX for M3 and M0 processors
+ */
+ static __INLINE uint64_t __SMLALDX(
+ uint32_t x,
+ uint32_t y,
+ uint64_t sum)
+ {
+/* return (sum + ((q15_t) (x >> 16) * (q15_t) y)) + ((q15_t) x * (q15_t) (y >> 16)); */
+ return ((uint64_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) +
+ ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) +
+ ( ((q63_t)sum ) ) ));
+ }
+
+
+ /*
+ * @brief C custom defined SMUAD for M3 and M0 processors
+ */
+ static __INLINE uint32_t __SMUAD(
+ uint32_t x,
+ uint32_t y)
+ {
+ return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) +
+ ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) ));
+ }
+
+
+ /*
+ * @brief C custom defined SMUSD for M3 and M0 processors
+ */
+ static __INLINE uint32_t __SMUSD(
+ uint32_t x,
+ uint32_t y)
+ {
+ return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) -
+ ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) ));
+ }
+
+
+ /*
+ * @brief C custom defined SXTB16 for M3 and M0 processors
+ */
+ static __INLINE uint32_t __SXTB16(
+ uint32_t x)
+ {
+ return ((uint32_t)(((((q31_t)x << 24) >> 24) & (q31_t)0x0000FFFF) |
+ ((((q31_t)x << 8) >> 8) & (q31_t)0xFFFF0000) ));
+ }
+
+#endif /* defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) */
+
+
+ /**
+ * @brief Instance structure for the Q7 FIR filter.
+ */
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of filter coefficients in the filter. */
+ q7_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
+ } arm_fir_instance_q7;
+
+ /**
+ * @brief Instance structure for the Q15 FIR filter.
+ */
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of filter coefficients in the filter. */
+ q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
+ } arm_fir_instance_q15;
+
+ /**
+ * @brief Instance structure for the Q31 FIR filter.
+ */
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of filter coefficients in the filter. */
+ q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
+ } arm_fir_instance_q31;
+
+ /**
+ * @brief Instance structure for the floating-point FIR filter.
+ */
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of filter coefficients in the filter. */
+ float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
+ } arm_fir_instance_f32;
+
+
+ /**
+ * @brief Processing function for the Q7 FIR filter.
+ * @param[in] S points to an instance of the Q7 FIR filter structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_fir_q7(
+ const arm_fir_instance_q7 * S,
+ q7_t * pSrc,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the Q7 FIR filter.
+ * @param[in,out] S points to an instance of the Q7 FIR structure.
+ * @param[in] numTaps Number of filter coefficients in the filter.
+ * @param[in] pCoeffs points to the filter coefficients.
+ * @param[in] pState points to the state buffer.
+ * @param[in] blockSize number of samples that are processed.
+ */
+ void arm_fir_init_q7(
+ arm_fir_instance_q7 * S,
+ uint16_t numTaps,
+ q7_t * pCoeffs,
+ q7_t * pState,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the Q15 FIR filter.
+ * @param[in] S points to an instance of the Q15 FIR structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_fir_q15(
+ const arm_fir_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the fast Q15 FIR filter for Cortex-M3 and Cortex-M4.
+ * @param[in] S points to an instance of the Q15 FIR filter structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_fir_fast_q15(
+ const arm_fir_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the Q15 FIR filter.
+ * @param[in,out] S points to an instance of the Q15 FIR filter structure.
+ * @param[in] numTaps Number of filter coefficients in the filter. Must be even and greater than or equal to 4.
+ * @param[in] pCoeffs points to the filter coefficients.
+ * @param[in] pState points to the state buffer.
+ * @param[in] blockSize number of samples that are processed at a time.
+ * @return The function returns ARM_MATH_SUCCESS if initialization was successful or ARM_MATH_ARGUMENT_ERROR if
+ * <code>numTaps</code> is not a supported value.
+ */
+ arm_status arm_fir_init_q15(
+ arm_fir_instance_q15 * S,
+ uint16_t numTaps,
+ q15_t * pCoeffs,
+ q15_t * pState,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the Q31 FIR filter.
+ * @param[in] S points to an instance of the Q31 FIR filter structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_fir_q31(
+ const arm_fir_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the fast Q31 FIR filter for Cortex-M3 and Cortex-M4.
+ * @param[in] S points to an instance of the Q31 FIR structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_fir_fast_q31(
+ const arm_fir_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the Q31 FIR filter.
+ * @param[in,out] S points to an instance of the Q31 FIR structure.
+ * @param[in] numTaps Number of filter coefficients in the filter.
+ * @param[in] pCoeffs points to the filter coefficients.
+ * @param[in] pState points to the state buffer.
+ * @param[in] blockSize number of samples that are processed at a time.
+ */
+ void arm_fir_init_q31(
+ arm_fir_instance_q31 * S,
+ uint16_t numTaps,
+ q31_t * pCoeffs,
+ q31_t * pState,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the floating-point FIR filter.
+ * @param[in] S points to an instance of the floating-point FIR structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_fir_f32(
+ const arm_fir_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the floating-point FIR filter.
+ * @param[in,out] S points to an instance of the floating-point FIR filter structure.
+ * @param[in] numTaps Number of filter coefficients in the filter.
+ * @param[in] pCoeffs points to the filter coefficients.
+ * @param[in] pState points to the state buffer.
+ * @param[in] blockSize number of samples that are processed at a time.
+ */
+ void arm_fir_init_f32(
+ arm_fir_instance_f32 * S,
+ uint16_t numTaps,
+ float32_t * pCoeffs,
+ float32_t * pState,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Instance structure for the Q15 Biquad cascade filter.
+ */
+ typedef struct
+ {
+ int8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */
+ q15_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */
+ q15_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */
+ int8_t postShift; /**< Additional shift, in bits, applied to each output sample. */
+ } arm_biquad_casd_df1_inst_q15;
+
+ /**
+ * @brief Instance structure for the Q31 Biquad cascade filter.
+ */
+ typedef struct
+ {
+ uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */
+ q31_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */
+ q31_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */
+ uint8_t postShift; /**< Additional shift, in bits, applied to each output sample. */
+ } arm_biquad_casd_df1_inst_q31;
+
+ /**
+ * @brief Instance structure for the floating-point Biquad cascade filter.
+ */
+ typedef struct
+ {
+ uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */
+ float32_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */
+ float32_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */
+ } arm_biquad_casd_df1_inst_f32;
+
+
+ /**
+ * @brief Processing function for the Q15 Biquad cascade filter.
+ * @param[in] S points to an instance of the Q15 Biquad cascade structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_biquad_cascade_df1_q15(
+ const arm_biquad_casd_df1_inst_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the Q15 Biquad cascade filter.
+ * @param[in,out] S points to an instance of the Q15 Biquad cascade structure.
+ * @param[in] numStages number of 2nd order stages in the filter.
+ * @param[in] pCoeffs points to the filter coefficients.
+ * @param[in] pState points to the state buffer.
+ * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format
+ */
+ void arm_biquad_cascade_df1_init_q15(
+ arm_biquad_casd_df1_inst_q15 * S,
+ uint8_t numStages,
+ q15_t * pCoeffs,
+ q15_t * pState,
+ int8_t postShift);
+
+
+ /**
+ * @brief Fast but less precise processing function for the Q15 Biquad cascade filter for Cortex-M3 and Cortex-M4.
+ * @param[in] S points to an instance of the Q15 Biquad cascade structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_biquad_cascade_df1_fast_q15(
+ const arm_biquad_casd_df1_inst_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the Q31 Biquad cascade filter
+ * @param[in] S points to an instance of the Q31 Biquad cascade structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_biquad_cascade_df1_q31(
+ const arm_biquad_casd_df1_inst_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Fast but less precise processing function for the Q31 Biquad cascade filter for Cortex-M3 and Cortex-M4.
+ * @param[in] S points to an instance of the Q31 Biquad cascade structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_biquad_cascade_df1_fast_q31(
+ const arm_biquad_casd_df1_inst_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the Q31 Biquad cascade filter.
+ * @param[in,out] S points to an instance of the Q31 Biquad cascade structure.
+ * @param[in] numStages number of 2nd order stages in the filter.
+ * @param[in] pCoeffs points to the filter coefficients.
+ * @param[in] pState points to the state buffer.
+ * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format
+ */
+ void arm_biquad_cascade_df1_init_q31(
+ arm_biquad_casd_df1_inst_q31 * S,
+ uint8_t numStages,
+ q31_t * pCoeffs,
+ q31_t * pState,
+ int8_t postShift);
+
+
+ /**
+ * @brief Processing function for the floating-point Biquad cascade filter.
+ * @param[in] S points to an instance of the floating-point Biquad cascade structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_biquad_cascade_df1_f32(
+ const arm_biquad_casd_df1_inst_f32 * S,
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the floating-point Biquad cascade filter.
+ * @param[in,out] S points to an instance of the floating-point Biquad cascade structure.
+ * @param[in] numStages number of 2nd order stages in the filter.
+ * @param[in] pCoeffs points to the filter coefficients.
+ * @param[in] pState points to the state buffer.
+ */
+ void arm_biquad_cascade_df1_init_f32(
+ arm_biquad_casd_df1_inst_f32 * S,
+ uint8_t numStages,
+ float32_t * pCoeffs,
+ float32_t * pState);
+
+
+ /**
+ * @brief Instance structure for the floating-point matrix structure.
+ */
+ typedef struct
+ {
+ uint16_t numRows; /**< number of rows of the matrix. */
+ uint16_t numCols; /**< number of columns of the matrix. */
+ float32_t *pData; /**< points to the data of the matrix. */
+ } arm_matrix_instance_f32;
+
+
+ /**
+ * @brief Instance structure for the floating-point matrix structure.
+ */
+ typedef struct
+ {
+ uint16_t numRows; /**< number of rows of the matrix. */
+ uint16_t numCols; /**< number of columns of the matrix. */
+ float64_t *pData; /**< points to the data of the matrix. */
+ } arm_matrix_instance_f64;
+
+ /**
+ * @brief Instance structure for the Q15 matrix structure.
+ */
+ typedef struct
+ {
+ uint16_t numRows; /**< number of rows of the matrix. */
+ uint16_t numCols; /**< number of columns of the matrix. */
+ q15_t *pData; /**< points to the data of the matrix. */
+ } arm_matrix_instance_q15;
+
+ /**
+ * @brief Instance structure for the Q31 matrix structure.
+ */
+ typedef struct
+ {
+ uint16_t numRows; /**< number of rows of the matrix. */
+ uint16_t numCols; /**< number of columns of the matrix. */
+ q31_t *pData; /**< points to the data of the matrix. */
+ } arm_matrix_instance_q31;
+
+
+ /**
+ * @brief Floating-point matrix addition.
+ * @param[in] pSrcA points to the first input matrix structure
+ * @param[in] pSrcB points to the second input matrix structure
+ * @param[out] pDst points to output matrix structure
+ * @return The function returns either
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ */
+ arm_status arm_mat_add_f32(
+ const arm_matrix_instance_f32 * pSrcA,
+ const arm_matrix_instance_f32 * pSrcB,
+ arm_matrix_instance_f32 * pDst);
+
+
+ /**
+ * @brief Q15 matrix addition.
+ * @param[in] pSrcA points to the first input matrix structure
+ * @param[in] pSrcB points to the second input matrix structure
+ * @param[out] pDst points to output matrix structure
+ * @return The function returns either
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ */
+ arm_status arm_mat_add_q15(
+ const arm_matrix_instance_q15 * pSrcA,
+ const arm_matrix_instance_q15 * pSrcB,
+ arm_matrix_instance_q15 * pDst);
+
+
+ /**
+ * @brief Q31 matrix addition.
+ * @param[in] pSrcA points to the first input matrix structure
+ * @param[in] pSrcB points to the second input matrix structure
+ * @param[out] pDst points to output matrix structure
+ * @return The function returns either
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ */
+ arm_status arm_mat_add_q31(
+ const arm_matrix_instance_q31 * pSrcA,
+ const arm_matrix_instance_q31 * pSrcB,
+ arm_matrix_instance_q31 * pDst);
+
+
+ /**
+ * @brief Floating-point, complex, matrix multiplication.
+ * @param[in] pSrcA points to the first input matrix structure
+ * @param[in] pSrcB points to the second input matrix structure
+ * @param[out] pDst points to output matrix structure
+ * @return The function returns either
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ */
+ arm_status arm_mat_cmplx_mult_f32(
+ const arm_matrix_instance_f32 * pSrcA,
+ const arm_matrix_instance_f32 * pSrcB,
+ arm_matrix_instance_f32 * pDst);
+
+
+ /**
+ * @brief Q15, complex, matrix multiplication.
+ * @param[in] pSrcA points to the first input matrix structure
+ * @param[in] pSrcB points to the second input matrix structure
+ * @param[out] pDst points to output matrix structure
+ * @return The function returns either
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ */
+ arm_status arm_mat_cmplx_mult_q15(
+ const arm_matrix_instance_q15 * pSrcA,
+ const arm_matrix_instance_q15 * pSrcB,
+ arm_matrix_instance_q15 * pDst,
+ q15_t * pScratch);
+
+
+ /**
+ * @brief Q31, complex, matrix multiplication.
+ * @param[in] pSrcA points to the first input matrix structure
+ * @param[in] pSrcB points to the second input matrix structure
+ * @param[out] pDst points to output matrix structure
+ * @return The function returns either
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ */
+ arm_status arm_mat_cmplx_mult_q31(
+ const arm_matrix_instance_q31 * pSrcA,
+ const arm_matrix_instance_q31 * pSrcB,
+ arm_matrix_instance_q31 * pDst);
+
+
+ /**
+ * @brief Floating-point matrix transpose.
+ * @param[in] pSrc points to the input matrix
+ * @param[out] pDst points to the output matrix
+ * @return The function returns either <code>ARM_MATH_SIZE_MISMATCH</code>
+ * or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ */
+ arm_status arm_mat_trans_f32(
+ const arm_matrix_instance_f32 * pSrc,
+ arm_matrix_instance_f32 * pDst);
+
+
+ /**
+ * @brief Q15 matrix transpose.
+ * @param[in] pSrc points to the input matrix
+ * @param[out] pDst points to the output matrix
+ * @return The function returns either <code>ARM_MATH_SIZE_MISMATCH</code>
+ * or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ */
+ arm_status arm_mat_trans_q15(
+ const arm_matrix_instance_q15 * pSrc,
+ arm_matrix_instance_q15 * pDst);
+
+
+ /**
+ * @brief Q31 matrix transpose.
+ * @param[in] pSrc points to the input matrix
+ * @param[out] pDst points to the output matrix
+ * @return The function returns either <code>ARM_MATH_SIZE_MISMATCH</code>
+ * or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ */
+ arm_status arm_mat_trans_q31(
+ const arm_matrix_instance_q31 * pSrc,
+ arm_matrix_instance_q31 * pDst);
+
+
+ /**
+ * @brief Floating-point matrix multiplication
+ * @param[in] pSrcA points to the first input matrix structure
+ * @param[in] pSrcB points to the second input matrix structure
+ * @param[out] pDst points to output matrix structure
+ * @return The function returns either
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ */
+ arm_status arm_mat_mult_f32(
+ const arm_matrix_instance_f32 * pSrcA,
+ const arm_matrix_instance_f32 * pSrcB,
+ arm_matrix_instance_f32 * pDst);
+
+
+ /**
+ * @brief Q15 matrix multiplication
+ * @param[in] pSrcA points to the first input matrix structure
+ * @param[in] pSrcB points to the second input matrix structure
+ * @param[out] pDst points to output matrix structure
+ * @param[in] pState points to the array for storing intermediate results
+ * @return The function returns either
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ */
+ arm_status arm_mat_mult_q15(
+ const arm_matrix_instance_q15 * pSrcA,
+ const arm_matrix_instance_q15 * pSrcB,
+ arm_matrix_instance_q15 * pDst,
+ q15_t * pState);
+
+
+ /**
+ * @brief Q15 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4
+ * @param[in] pSrcA points to the first input matrix structure
+ * @param[in] pSrcB points to the second input matrix structure
+ * @param[out] pDst points to output matrix structure
+ * @param[in] pState points to the array for storing intermediate results
+ * @return The function returns either
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ */
+ arm_status arm_mat_mult_fast_q15(
+ const arm_matrix_instance_q15 * pSrcA,
+ const arm_matrix_instance_q15 * pSrcB,
+ arm_matrix_instance_q15 * pDst,
+ q15_t * pState);
+
+
+ /**
+ * @brief Q31 matrix multiplication
+ * @param[in] pSrcA points to the first input matrix structure
+ * @param[in] pSrcB points to the second input matrix structure
+ * @param[out] pDst points to output matrix structure
+ * @return The function returns either
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ */
+ arm_status arm_mat_mult_q31(
+ const arm_matrix_instance_q31 * pSrcA,
+ const arm_matrix_instance_q31 * pSrcB,
+ arm_matrix_instance_q31 * pDst);
+
+
+ /**
+ * @brief Q31 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4
+ * @param[in] pSrcA points to the first input matrix structure
+ * @param[in] pSrcB points to the second input matrix structure
+ * @param[out] pDst points to output matrix structure
+ * @return The function returns either
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ */
+ arm_status arm_mat_mult_fast_q31(
+ const arm_matrix_instance_q31 * pSrcA,
+ const arm_matrix_instance_q31 * pSrcB,
+ arm_matrix_instance_q31 * pDst);
+
+
+ /**
+ * @brief Floating-point matrix subtraction
+ * @param[in] pSrcA points to the first input matrix structure
+ * @param[in] pSrcB points to the second input matrix structure
+ * @param[out] pDst points to output matrix structure
+ * @return The function returns either
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ */
+ arm_status arm_mat_sub_f32(
+ const arm_matrix_instance_f32 * pSrcA,
+ const arm_matrix_instance_f32 * pSrcB,
+ arm_matrix_instance_f32 * pDst);
+
+
+ /**
+ * @brief Q15 matrix subtraction
+ * @param[in] pSrcA points to the first input matrix structure
+ * @param[in] pSrcB points to the second input matrix structure
+ * @param[out] pDst points to output matrix structure
+ * @return The function returns either
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ */
+ arm_status arm_mat_sub_q15(
+ const arm_matrix_instance_q15 * pSrcA,
+ const arm_matrix_instance_q15 * pSrcB,
+ arm_matrix_instance_q15 * pDst);
+
+
+ /**
+ * @brief Q31 matrix subtraction
+ * @param[in] pSrcA points to the first input matrix structure
+ * @param[in] pSrcB points to the second input matrix structure
+ * @param[out] pDst points to output matrix structure
+ * @return The function returns either
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ */
+ arm_status arm_mat_sub_q31(
+ const arm_matrix_instance_q31 * pSrcA,
+ const arm_matrix_instance_q31 * pSrcB,
+ arm_matrix_instance_q31 * pDst);
+
+
+ /**
+ * @brief Floating-point matrix scaling.
+ * @param[in] pSrc points to the input matrix
+ * @param[in] scale scale factor
+ * @param[out] pDst points to the output matrix
+ * @return The function returns either
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ */
+ arm_status arm_mat_scale_f32(
+ const arm_matrix_instance_f32 * pSrc,
+ float32_t scale,
+ arm_matrix_instance_f32 * pDst);
+
+
+ /**
+ * @brief Q15 matrix scaling.
+ * @param[in] pSrc points to input matrix
+ * @param[in] scaleFract fractional portion of the scale factor
+ * @param[in] shift number of bits to shift the result by
+ * @param[out] pDst points to output matrix
+ * @return The function returns either
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ */
+ arm_status arm_mat_scale_q15(
+ const arm_matrix_instance_q15 * pSrc,
+ q15_t scaleFract,
+ int32_t shift,
+ arm_matrix_instance_q15 * pDst);
+
+
+ /**
+ * @brief Q31 matrix scaling.
+ * @param[in] pSrc points to input matrix
+ * @param[in] scaleFract fractional portion of the scale factor
+ * @param[in] shift number of bits to shift the result by
+ * @param[out] pDst points to output matrix structure
+ * @return The function returns either
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ */
+ arm_status arm_mat_scale_q31(
+ const arm_matrix_instance_q31 * pSrc,
+ q31_t scaleFract,
+ int32_t shift,
+ arm_matrix_instance_q31 * pDst);
+
+
+ /**
+ * @brief Q31 matrix initialization.
+ * @param[in,out] S points to an instance of the floating-point matrix structure.
+ * @param[in] nRows number of rows in the matrix.
+ * @param[in] nColumns number of columns in the matrix.
+ * @param[in] pData points to the matrix data array.
+ */
+ void arm_mat_init_q31(
+ arm_matrix_instance_q31 * S,
+ uint16_t nRows,
+ uint16_t nColumns,
+ q31_t * pData);
+
+
+ /**
+ * @brief Q15 matrix initialization.
+ * @param[in,out] S points to an instance of the floating-point matrix structure.
+ * @param[in] nRows number of rows in the matrix.
+ * @param[in] nColumns number of columns in the matrix.
+ * @param[in] pData points to the matrix data array.
+ */
+ void arm_mat_init_q15(
+ arm_matrix_instance_q15 * S,
+ uint16_t nRows,
+ uint16_t nColumns,
+ q15_t * pData);
+
+
+ /**
+ * @brief Floating-point matrix initialization.
+ * @param[in,out] S points to an instance of the floating-point matrix structure.
+ * @param[in] nRows number of rows in the matrix.
+ * @param[in] nColumns number of columns in the matrix.
+ * @param[in] pData points to the matrix data array.
+ */
+ void arm_mat_init_f32(
+ arm_matrix_instance_f32 * S,
+ uint16_t nRows,
+ uint16_t nColumns,
+ float32_t * pData);
+
+
+
+ /**
+ * @brief Instance structure for the Q15 PID Control.
+ */
+ typedef struct
+ {
+ q15_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */
+#ifdef ARM_MATH_CM0_FAMILY
+ q15_t A1;
+ q15_t A2;
+#else
+ q31_t A1; /**< The derived gain A1 = -Kp - 2Kd | Kd.*/
+#endif
+ q15_t state[3]; /**< The state array of length 3. */
+ q15_t Kp; /**< The proportional gain. */
+ q15_t Ki; /**< The integral gain. */
+ q15_t Kd; /**< The derivative gain. */
+ } arm_pid_instance_q15;
+
+ /**
+ * @brief Instance structure for the Q31 PID Control.
+ */
+ typedef struct
+ {
+ q31_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */
+ q31_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */
+ q31_t A2; /**< The derived gain, A2 = Kd . */
+ q31_t state[3]; /**< The state array of length 3. */
+ q31_t Kp; /**< The proportional gain. */
+ q31_t Ki; /**< The integral gain. */
+ q31_t Kd; /**< The derivative gain. */
+ } arm_pid_instance_q31;
+
+ /**
+ * @brief Instance structure for the floating-point PID Control.
+ */
+ typedef struct
+ {
+ float32_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */
+ float32_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */
+ float32_t A2; /**< The derived gain, A2 = Kd . */
+ float32_t state[3]; /**< The state array of length 3. */
+ float32_t Kp; /**< The proportional gain. */
+ float32_t Ki; /**< The integral gain. */
+ float32_t Kd; /**< The derivative gain. */
+ } arm_pid_instance_f32;
+
+
+
+ /**
+ * @brief Initialization function for the floating-point PID Control.
+ * @param[in,out] S points to an instance of the PID structure.
+ * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state.
+ */
+ void arm_pid_init_f32(
+ arm_pid_instance_f32 * S,
+ int32_t resetStateFlag);
+
+
+ /**
+ * @brief Reset function for the floating-point PID Control.
+ * @param[in,out] S is an instance of the floating-point PID Control structure
+ */
+ void arm_pid_reset_f32(
+ arm_pid_instance_f32 * S);
+
+
+ /**
+ * @brief Initialization function for the Q31 PID Control.
+ * @param[in,out] S points to an instance of the Q15 PID structure.
+ * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state.
+ */
+ void arm_pid_init_q31(
+ arm_pid_instance_q31 * S,
+ int32_t resetStateFlag);
+
+
+ /**
+ * @brief Reset function for the Q31 PID Control.
+ * @param[in,out] S points to an instance of the Q31 PID Control structure
+ */
+
+ void arm_pid_reset_q31(
+ arm_pid_instance_q31 * S);
+
+
+ /**
+ * @brief Initialization function for the Q15 PID Control.
+ * @param[in,out] S points to an instance of the Q15 PID structure.
+ * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state.
+ */
+ void arm_pid_init_q15(
+ arm_pid_instance_q15 * S,
+ int32_t resetStateFlag);
+
+
+ /**
+ * @brief Reset function for the Q15 PID Control.
+ * @param[in,out] S points to an instance of the q15 PID Control structure
+ */
+ void arm_pid_reset_q15(
+ arm_pid_instance_q15 * S);
+
+
+ /**
+ * @brief Instance structure for the floating-point Linear Interpolate function.
+ */
+ typedef struct
+ {
+ uint32_t nValues; /**< nValues */
+ float32_t x1; /**< x1 */
+ float32_t xSpacing; /**< xSpacing */
+ float32_t *pYData; /**< pointer to the table of Y values */
+ } arm_linear_interp_instance_f32;
+
+ /**
+ * @brief Instance structure for the floating-point bilinear interpolation function.
+ */
+ typedef struct
+ {
+ uint16_t numRows; /**< number of rows in the data table. */
+ uint16_t numCols; /**< number of columns in the data table. */
+ float32_t *pData; /**< points to the data table. */
+ } arm_bilinear_interp_instance_f32;
+
+ /**
+ * @brief Instance structure for the Q31 bilinear interpolation function.
+ */
+ typedef struct
+ {
+ uint16_t numRows; /**< number of rows in the data table. */
+ uint16_t numCols; /**< number of columns in the data table. */
+ q31_t *pData; /**< points to the data table. */
+ } arm_bilinear_interp_instance_q31;
+
+ /**
+ * @brief Instance structure for the Q15 bilinear interpolation function.
+ */
+ typedef struct
+ {
+ uint16_t numRows; /**< number of rows in the data table. */
+ uint16_t numCols; /**< number of columns in the data table. */
+ q15_t *pData; /**< points to the data table. */
+ } arm_bilinear_interp_instance_q15;
+
+ /**
+ * @brief Instance structure for the Q15 bilinear interpolation function.
+ */
+ typedef struct
+ {
+ uint16_t numRows; /**< number of rows in the data table. */
+ uint16_t numCols; /**< number of columns in the data table. */
+ q7_t *pData; /**< points to the data table. */
+ } arm_bilinear_interp_instance_q7;
+
+
+ /**
+ * @brief Q7 vector multiplication.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ */
+ void arm_mult_q7(
+ q7_t * pSrcA,
+ q7_t * pSrcB,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Q15 vector multiplication.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ */
+ void arm_mult_q15(
+ q15_t * pSrcA,
+ q15_t * pSrcB,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Q31 vector multiplication.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ */
+ void arm_mult_q31(
+ q31_t * pSrcA,
+ q31_t * pSrcB,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Floating-point vector multiplication.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ */
+ void arm_mult_f32(
+ float32_t * pSrcA,
+ float32_t * pSrcB,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Instance structure for the Q15 CFFT/CIFFT function.
+ */
+ typedef struct
+ {
+ uint16_t fftLen; /**< length of the FFT. */
+ uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+ uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+ q15_t *pTwiddle; /**< points to the Sin twiddle factor table. */
+ uint16_t *pBitRevTable; /**< points to the bit reversal table. */
+ uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+ uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+ } arm_cfft_radix2_instance_q15;
+
+/* Deprecated */
+ arm_status arm_cfft_radix2_init_q15(
+ arm_cfft_radix2_instance_q15 * S,
+ uint16_t fftLen,
+ uint8_t ifftFlag,
+ uint8_t bitReverseFlag);
+
+/* Deprecated */
+ void arm_cfft_radix2_q15(
+ const arm_cfft_radix2_instance_q15 * S,
+ q15_t * pSrc);
+
+
+ /**
+ * @brief Instance structure for the Q15 CFFT/CIFFT function.
+ */
+ typedef struct
+ {
+ uint16_t fftLen; /**< length of the FFT. */
+ uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+ uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+ q15_t *pTwiddle; /**< points to the twiddle factor table. */
+ uint16_t *pBitRevTable; /**< points to the bit reversal table. */
+ uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+ uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+ } arm_cfft_radix4_instance_q15;
+
+/* Deprecated */
+ arm_status arm_cfft_radix4_init_q15(
+ arm_cfft_radix4_instance_q15 * S,
+ uint16_t fftLen,
+ uint8_t ifftFlag,
+ uint8_t bitReverseFlag);
+
+/* Deprecated */
+ void arm_cfft_radix4_q15(
+ const arm_cfft_radix4_instance_q15 * S,
+ q15_t * pSrc);
+
+ /**
+ * @brief Instance structure for the Radix-2 Q31 CFFT/CIFFT function.
+ */
+ typedef struct
+ {
+ uint16_t fftLen; /**< length of the FFT. */
+ uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+ uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+ q31_t *pTwiddle; /**< points to the Twiddle factor table. */
+ uint16_t *pBitRevTable; /**< points to the bit reversal table. */
+ uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+ uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+ } arm_cfft_radix2_instance_q31;
+
+/* Deprecated */
+ arm_status arm_cfft_radix2_init_q31(
+ arm_cfft_radix2_instance_q31 * S,
+ uint16_t fftLen,
+ uint8_t ifftFlag,
+ uint8_t bitReverseFlag);
+
+/* Deprecated */
+ void arm_cfft_radix2_q31(
+ const arm_cfft_radix2_instance_q31 * S,
+ q31_t * pSrc);
+
+ /**
+ * @brief Instance structure for the Q31 CFFT/CIFFT function.
+ */
+ typedef struct
+ {
+ uint16_t fftLen; /**< length of the FFT. */
+ uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+ uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+ q31_t *pTwiddle; /**< points to the twiddle factor table. */
+ uint16_t *pBitRevTable; /**< points to the bit reversal table. */
+ uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+ uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+ } arm_cfft_radix4_instance_q31;
+
+/* Deprecated */
+ void arm_cfft_radix4_q31(
+ const arm_cfft_radix4_instance_q31 * S,
+ q31_t * pSrc);
+
+/* Deprecated */
+ arm_status arm_cfft_radix4_init_q31(
+ arm_cfft_radix4_instance_q31 * S,
+ uint16_t fftLen,
+ uint8_t ifftFlag,
+ uint8_t bitReverseFlag);
+
+ /**
+ * @brief Instance structure for the floating-point CFFT/CIFFT function.
+ */
+ typedef struct
+ {
+ uint16_t fftLen; /**< length of the FFT. */
+ uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+ uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+ float32_t *pTwiddle; /**< points to the Twiddle factor table. */
+ uint16_t *pBitRevTable; /**< points to the bit reversal table. */
+ uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+ uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+ float32_t onebyfftLen; /**< value of 1/fftLen. */
+ } arm_cfft_radix2_instance_f32;
+
+/* Deprecated */
+ arm_status arm_cfft_radix2_init_f32(
+ arm_cfft_radix2_instance_f32 * S,
+ uint16_t fftLen,
+ uint8_t ifftFlag,
+ uint8_t bitReverseFlag);
+
+/* Deprecated */
+ void arm_cfft_radix2_f32(
+ const arm_cfft_radix2_instance_f32 * S,
+ float32_t * pSrc);
+
+ /**
+ * @brief Instance structure for the floating-point CFFT/CIFFT function.
+ */
+ typedef struct
+ {
+ uint16_t fftLen; /**< length of the FFT. */
+ uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+ uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+ float32_t *pTwiddle; /**< points to the Twiddle factor table. */
+ uint16_t *pBitRevTable; /**< points to the bit reversal table. */
+ uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+ uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+ float32_t onebyfftLen; /**< value of 1/fftLen. */
+ } arm_cfft_radix4_instance_f32;
+
+/* Deprecated */
+ arm_status arm_cfft_radix4_init_f32(
+ arm_cfft_radix4_instance_f32 * S,
+ uint16_t fftLen,
+ uint8_t ifftFlag,
+ uint8_t bitReverseFlag);
+
+/* Deprecated */
+ void arm_cfft_radix4_f32(
+ const arm_cfft_radix4_instance_f32 * S,
+ float32_t * pSrc);
+
+ /**
+ * @brief Instance structure for the fixed-point CFFT/CIFFT function.
+ */
+ typedef struct
+ {
+ uint16_t fftLen; /**< length of the FFT. */
+ const q15_t *pTwiddle; /**< points to the Twiddle factor table. */
+ const uint16_t *pBitRevTable; /**< points to the bit reversal table. */
+ uint16_t bitRevLength; /**< bit reversal table length. */
+ } arm_cfft_instance_q15;
+
+void arm_cfft_q15(
+ const arm_cfft_instance_q15 * S,
+ q15_t * p1,
+ uint8_t ifftFlag,
+ uint8_t bitReverseFlag);
+
+ /**
+ * @brief Instance structure for the fixed-point CFFT/CIFFT function.
+ */
+ typedef struct
+ {
+ uint16_t fftLen; /**< length of the FFT. */
+ const q31_t *pTwiddle; /**< points to the Twiddle factor table. */
+ const uint16_t *pBitRevTable; /**< points to the bit reversal table. */
+ uint16_t bitRevLength; /**< bit reversal table length. */
+ } arm_cfft_instance_q31;
+
+void arm_cfft_q31(
+ const arm_cfft_instance_q31 * S,
+ q31_t * p1,
+ uint8_t ifftFlag,
+ uint8_t bitReverseFlag);
+
+ /**
+ * @brief Instance structure for the floating-point CFFT/CIFFT function.
+ */
+ typedef struct
+ {
+ uint16_t fftLen; /**< length of the FFT. */
+ const float32_t *pTwiddle; /**< points to the Twiddle factor table. */
+ const uint16_t *pBitRevTable; /**< points to the bit reversal table. */
+ uint16_t bitRevLength; /**< bit reversal table length. */
+ } arm_cfft_instance_f32;
+
+ void arm_cfft_f32(
+ const arm_cfft_instance_f32 * S,
+ float32_t * p1,
+ uint8_t ifftFlag,
+ uint8_t bitReverseFlag);
+
+ /**
+ * @brief Instance structure for the Q15 RFFT/RIFFT function.
+ */
+ typedef struct
+ {
+ uint32_t fftLenReal; /**< length of the real FFT. */
+ uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */
+ uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */
+ uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+ q15_t *pTwiddleAReal; /**< points to the real twiddle factor table. */
+ q15_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */
+ const arm_cfft_instance_q15 *pCfft; /**< points to the complex FFT instance. */
+ } arm_rfft_instance_q15;
+
+ arm_status arm_rfft_init_q15(
+ arm_rfft_instance_q15 * S,
+ uint32_t fftLenReal,
+ uint32_t ifftFlagR,
+ uint32_t bitReverseFlag);
+
+ void arm_rfft_q15(
+ const arm_rfft_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst);
+
+ /**
+ * @brief Instance structure for the Q31 RFFT/RIFFT function.
+ */
+ typedef struct
+ {
+ uint32_t fftLenReal; /**< length of the real FFT. */
+ uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */
+ uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */
+ uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+ q31_t *pTwiddleAReal; /**< points to the real twiddle factor table. */
+ q31_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */
+ const arm_cfft_instance_q31 *pCfft; /**< points to the complex FFT instance. */
+ } arm_rfft_instance_q31;
+
+ arm_status arm_rfft_init_q31(
+ arm_rfft_instance_q31 * S,
+ uint32_t fftLenReal,
+ uint32_t ifftFlagR,
+ uint32_t bitReverseFlag);
+
+ void arm_rfft_q31(
+ const arm_rfft_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst);
+
+ /**
+ * @brief Instance structure for the floating-point RFFT/RIFFT function.
+ */
+ typedef struct
+ {
+ uint32_t fftLenReal; /**< length of the real FFT. */
+ uint16_t fftLenBy2; /**< length of the complex FFT. */
+ uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */
+ uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */
+ uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+ float32_t *pTwiddleAReal; /**< points to the real twiddle factor table. */
+ float32_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */
+ arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */
+ } arm_rfft_instance_f32;
+
+ arm_status arm_rfft_init_f32(
+ arm_rfft_instance_f32 * S,
+ arm_cfft_radix4_instance_f32 * S_CFFT,
+ uint32_t fftLenReal,
+ uint32_t ifftFlagR,
+ uint32_t bitReverseFlag);
+
+ void arm_rfft_f32(
+ const arm_rfft_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pDst);
+
+ /**
+ * @brief Instance structure for the floating-point RFFT/RIFFT function.
+ */
+typedef struct
+ {
+ arm_cfft_instance_f32 Sint; /**< Internal CFFT structure. */
+ uint16_t fftLenRFFT; /**< length of the real sequence */
+ float32_t * pTwiddleRFFT; /**< Twiddle factors real stage */
+ } arm_rfft_fast_instance_f32 ;
+
+arm_status arm_rfft_fast_init_f32 (
+ arm_rfft_fast_instance_f32 * S,
+ uint16_t fftLen);
+
+void arm_rfft_fast_f32(
+ arm_rfft_fast_instance_f32 * S,
+ float32_t * p, float32_t * pOut,
+ uint8_t ifftFlag);
+
+ /**
+ * @brief Instance structure for the floating-point DCT4/IDCT4 function.
+ */
+ typedef struct
+ {
+ uint16_t N; /**< length of the DCT4. */
+ uint16_t Nby2; /**< half of the length of the DCT4. */
+ float32_t normalize; /**< normalizing factor. */
+ float32_t *pTwiddle; /**< points to the twiddle factor table. */
+ float32_t *pCosFactor; /**< points to the cosFactor table. */
+ arm_rfft_instance_f32 *pRfft; /**< points to the real FFT instance. */
+ arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */
+ } arm_dct4_instance_f32;
+
+
+ /**
+ * @brief Initialization function for the floating-point DCT4/IDCT4.
+ * @param[in,out] S points to an instance of floating-point DCT4/IDCT4 structure.
+ * @param[in] S_RFFT points to an instance of floating-point RFFT/RIFFT structure.
+ * @param[in] S_CFFT points to an instance of floating-point CFFT/CIFFT structure.
+ * @param[in] N length of the DCT4.
+ * @param[in] Nby2 half of the length of the DCT4.
+ * @param[in] normalize normalizing factor.
+ * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>fftLenReal</code> is not a supported transform length.
+ */
+ arm_status arm_dct4_init_f32(
+ arm_dct4_instance_f32 * S,
+ arm_rfft_instance_f32 * S_RFFT,
+ arm_cfft_radix4_instance_f32 * S_CFFT,
+ uint16_t N,
+ uint16_t Nby2,
+ float32_t normalize);
+
+
+ /**
+ * @brief Processing function for the floating-point DCT4/IDCT4.
+ * @param[in] S points to an instance of the floating-point DCT4/IDCT4 structure.
+ * @param[in] pState points to state buffer.
+ * @param[in,out] pInlineBuffer points to the in-place input and output buffer.
+ */
+ void arm_dct4_f32(
+ const arm_dct4_instance_f32 * S,
+ float32_t * pState,
+ float32_t * pInlineBuffer);
+
+
+ /**
+ * @brief Instance structure for the Q31 DCT4/IDCT4 function.
+ */
+ typedef struct
+ {
+ uint16_t N; /**< length of the DCT4. */
+ uint16_t Nby2; /**< half of the length of the DCT4. */
+ q31_t normalize; /**< normalizing factor. */
+ q31_t *pTwiddle; /**< points to the twiddle factor table. */
+ q31_t *pCosFactor; /**< points to the cosFactor table. */
+ arm_rfft_instance_q31 *pRfft; /**< points to the real FFT instance. */
+ arm_cfft_radix4_instance_q31 *pCfft; /**< points to the complex FFT instance. */
+ } arm_dct4_instance_q31;
+
+
+ /**
+ * @brief Initialization function for the Q31 DCT4/IDCT4.
+ * @param[in,out] S points to an instance of Q31 DCT4/IDCT4 structure.
+ * @param[in] S_RFFT points to an instance of Q31 RFFT/RIFFT structure
+ * @param[in] S_CFFT points to an instance of Q31 CFFT/CIFFT structure
+ * @param[in] N length of the DCT4.
+ * @param[in] Nby2 half of the length of the DCT4.
+ * @param[in] normalize normalizing factor.
+ * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>N</code> is not a supported transform length.
+ */
+ arm_status arm_dct4_init_q31(
+ arm_dct4_instance_q31 * S,
+ arm_rfft_instance_q31 * S_RFFT,
+ arm_cfft_radix4_instance_q31 * S_CFFT,
+ uint16_t N,
+ uint16_t Nby2,
+ q31_t normalize);
+
+
+ /**
+ * @brief Processing function for the Q31 DCT4/IDCT4.
+ * @param[in] S points to an instance of the Q31 DCT4 structure.
+ * @param[in] pState points to state buffer.
+ * @param[in,out] pInlineBuffer points to the in-place input and output buffer.
+ */
+ void arm_dct4_q31(
+ const arm_dct4_instance_q31 * S,
+ q31_t * pState,
+ q31_t * pInlineBuffer);
+
+
+ /**
+ * @brief Instance structure for the Q15 DCT4/IDCT4 function.
+ */
+ typedef struct
+ {
+ uint16_t N; /**< length of the DCT4. */
+ uint16_t Nby2; /**< half of the length of the DCT4. */
+ q15_t normalize; /**< normalizing factor. */
+ q15_t *pTwiddle; /**< points to the twiddle factor table. */
+ q15_t *pCosFactor; /**< points to the cosFactor table. */
+ arm_rfft_instance_q15 *pRfft; /**< points to the real FFT instance. */
+ arm_cfft_radix4_instance_q15 *pCfft; /**< points to the complex FFT instance. */
+ } arm_dct4_instance_q15;
+
+
+ /**
+ * @brief Initialization function for the Q15 DCT4/IDCT4.
+ * @param[in,out] S points to an instance of Q15 DCT4/IDCT4 structure.
+ * @param[in] S_RFFT points to an instance of Q15 RFFT/RIFFT structure.
+ * @param[in] S_CFFT points to an instance of Q15 CFFT/CIFFT structure.
+ * @param[in] N length of the DCT4.
+ * @param[in] Nby2 half of the length of the DCT4.
+ * @param[in] normalize normalizing factor.
+ * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>N</code> is not a supported transform length.
+ */
+ arm_status arm_dct4_init_q15(
+ arm_dct4_instance_q15 * S,
+ arm_rfft_instance_q15 * S_RFFT,
+ arm_cfft_radix4_instance_q15 * S_CFFT,
+ uint16_t N,
+ uint16_t Nby2,
+ q15_t normalize);
+
+
+ /**
+ * @brief Processing function for the Q15 DCT4/IDCT4.
+ * @param[in] S points to an instance of the Q15 DCT4 structure.
+ * @param[in] pState points to state buffer.
+ * @param[in,out] pInlineBuffer points to the in-place input and output buffer.
+ */
+ void arm_dct4_q15(
+ const arm_dct4_instance_q15 * S,
+ q15_t * pState,
+ q15_t * pInlineBuffer);
+
+
+ /**
+ * @brief Floating-point vector addition.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ */
+ void arm_add_f32(
+ float32_t * pSrcA,
+ float32_t * pSrcB,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Q7 vector addition.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ */
+ void arm_add_q7(
+ q7_t * pSrcA,
+ q7_t * pSrcB,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Q15 vector addition.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ */
+ void arm_add_q15(
+ q15_t * pSrcA,
+ q15_t * pSrcB,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Q31 vector addition.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ */
+ void arm_add_q31(
+ q31_t * pSrcA,
+ q31_t * pSrcB,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Floating-point vector subtraction.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ */
+ void arm_sub_f32(
+ float32_t * pSrcA,
+ float32_t * pSrcB,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Q7 vector subtraction.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ */
+ void arm_sub_q7(
+ q7_t * pSrcA,
+ q7_t * pSrcB,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Q15 vector subtraction.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ */
+ void arm_sub_q15(
+ q15_t * pSrcA,
+ q15_t * pSrcB,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Q31 vector subtraction.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ */
+ void arm_sub_q31(
+ q31_t * pSrcA,
+ q31_t * pSrcB,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Multiplies a floating-point vector by a scalar.
+ * @param[in] pSrc points to the input vector
+ * @param[in] scale scale factor to be applied
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ */
+ void arm_scale_f32(
+ float32_t * pSrc,
+ float32_t scale,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Multiplies a Q7 vector by a scalar.
+ * @param[in] pSrc points to the input vector
+ * @param[in] scaleFract fractional portion of the scale value
+ * @param[in] shift number of bits to shift the result by
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ */
+ void arm_scale_q7(
+ q7_t * pSrc,
+ q7_t scaleFract,
+ int8_t shift,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Multiplies a Q15 vector by a scalar.
+ * @param[in] pSrc points to the input vector
+ * @param[in] scaleFract fractional portion of the scale value
+ * @param[in] shift number of bits to shift the result by
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ */
+ void arm_scale_q15(
+ q15_t * pSrc,
+ q15_t scaleFract,
+ int8_t shift,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Multiplies a Q31 vector by a scalar.
+ * @param[in] pSrc points to the input vector
+ * @param[in] scaleFract fractional portion of the scale value
+ * @param[in] shift number of bits to shift the result by
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ */
+ void arm_scale_q31(
+ q31_t * pSrc,
+ q31_t scaleFract,
+ int8_t shift,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Q7 vector absolute value.
+ * @param[in] pSrc points to the input buffer
+ * @param[out] pDst points to the output buffer
+ * @param[in] blockSize number of samples in each vector
+ */
+ void arm_abs_q7(
+ q7_t * pSrc,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Floating-point vector absolute value.
+ * @param[in] pSrc points to the input buffer
+ * @param[out] pDst points to the output buffer
+ * @param[in] blockSize number of samples in each vector
+ */
+ void arm_abs_f32(
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Q15 vector absolute value.
+ * @param[in] pSrc points to the input buffer
+ * @param[out] pDst points to the output buffer
+ * @param[in] blockSize number of samples in each vector
+ */
+ void arm_abs_q15(
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Q31 vector absolute value.
+ * @param[in] pSrc points to the input buffer
+ * @param[out] pDst points to the output buffer
+ * @param[in] blockSize number of samples in each vector
+ */
+ void arm_abs_q31(
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Dot product of floating-point vectors.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[in] blockSize number of samples in each vector
+ * @param[out] result output result returned here
+ */
+ void arm_dot_prod_f32(
+ float32_t * pSrcA,
+ float32_t * pSrcB,
+ uint32_t blockSize,
+ float32_t * result);
+
+
+ /**
+ * @brief Dot product of Q7 vectors.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[in] blockSize number of samples in each vector
+ * @param[out] result output result returned here
+ */
+ void arm_dot_prod_q7(
+ q7_t * pSrcA,
+ q7_t * pSrcB,
+ uint32_t blockSize,
+ q31_t * result);
+
+
+ /**
+ * @brief Dot product of Q15 vectors.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[in] blockSize number of samples in each vector
+ * @param[out] result output result returned here
+ */
+ void arm_dot_prod_q15(
+ q15_t * pSrcA,
+ q15_t * pSrcB,
+ uint32_t blockSize,
+ q63_t * result);
+
+
+ /**
+ * @brief Dot product of Q31 vectors.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[in] blockSize number of samples in each vector
+ * @param[out] result output result returned here
+ */
+ void arm_dot_prod_q31(
+ q31_t * pSrcA,
+ q31_t * pSrcB,
+ uint32_t blockSize,
+ q63_t * result);
+
+
+ /**
+ * @brief Shifts the elements of a Q7 vector a specified number of bits.
+ * @param[in] pSrc points to the input vector
+ * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right.
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ */
+ void arm_shift_q7(
+ q7_t * pSrc,
+ int8_t shiftBits,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Shifts the elements of a Q15 vector a specified number of bits.
+ * @param[in] pSrc points to the input vector
+ * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right.
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ */
+ void arm_shift_q15(
+ q15_t * pSrc,
+ int8_t shiftBits,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Shifts the elements of a Q31 vector a specified number of bits.
+ * @param[in] pSrc points to the input vector
+ * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right.
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ */
+ void arm_shift_q31(
+ q31_t * pSrc,
+ int8_t shiftBits,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Adds a constant offset to a floating-point vector.
+ * @param[in] pSrc points to the input vector
+ * @param[in] offset is the offset to be added
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ */
+ void arm_offset_f32(
+ float32_t * pSrc,
+ float32_t offset,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Adds a constant offset to a Q7 vector.
+ * @param[in] pSrc points to the input vector
+ * @param[in] offset is the offset to be added
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ */
+ void arm_offset_q7(
+ q7_t * pSrc,
+ q7_t offset,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Adds a constant offset to a Q15 vector.
+ * @param[in] pSrc points to the input vector
+ * @param[in] offset is the offset to be added
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ */
+ void arm_offset_q15(
+ q15_t * pSrc,
+ q15_t offset,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Adds a constant offset to a Q31 vector.
+ * @param[in] pSrc points to the input vector
+ * @param[in] offset is the offset to be added
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ */
+ void arm_offset_q31(
+ q31_t * pSrc,
+ q31_t offset,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Negates the elements of a floating-point vector.
+ * @param[in] pSrc points to the input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ */
+ void arm_negate_f32(
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Negates the elements of a Q7 vector.
+ * @param[in] pSrc points to the input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ */
+ void arm_negate_q7(
+ q7_t * pSrc,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Negates the elements of a Q15 vector.
+ * @param[in] pSrc points to the input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ */
+ void arm_negate_q15(
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Negates the elements of a Q31 vector.
+ * @param[in] pSrc points to the input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ */
+ void arm_negate_q31(
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Copies the elements of a floating-point vector.
+ * @param[in] pSrc input pointer
+ * @param[out] pDst output pointer
+ * @param[in] blockSize number of samples to process
+ */
+ void arm_copy_f32(
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Copies the elements of a Q7 vector.
+ * @param[in] pSrc input pointer
+ * @param[out] pDst output pointer
+ * @param[in] blockSize number of samples to process
+ */
+ void arm_copy_q7(
+ q7_t * pSrc,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Copies the elements of a Q15 vector.
+ * @param[in] pSrc input pointer
+ * @param[out] pDst output pointer
+ * @param[in] blockSize number of samples to process
+ */
+ void arm_copy_q15(
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Copies the elements of a Q31 vector.
+ * @param[in] pSrc input pointer
+ * @param[out] pDst output pointer
+ * @param[in] blockSize number of samples to process
+ */
+ void arm_copy_q31(
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Fills a constant value into a floating-point vector.
+ * @param[in] value input value to be filled
+ * @param[out] pDst output pointer
+ * @param[in] blockSize number of samples to process
+ */
+ void arm_fill_f32(
+ float32_t value,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Fills a constant value into a Q7 vector.
+ * @param[in] value input value to be filled
+ * @param[out] pDst output pointer
+ * @param[in] blockSize number of samples to process
+ */
+ void arm_fill_q7(
+ q7_t value,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Fills a constant value into a Q15 vector.
+ * @param[in] value input value to be filled
+ * @param[out] pDst output pointer
+ * @param[in] blockSize number of samples to process
+ */
+ void arm_fill_q15(
+ q15_t value,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Fills a constant value into a Q31 vector.
+ * @param[in] value input value to be filled
+ * @param[out] pDst output pointer
+ * @param[in] blockSize number of samples to process
+ */
+ void arm_fill_q31(
+ q31_t value,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Convolution of floating-point sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the location where the output result is written. Length srcALen+srcBLen-1.
+ */
+ void arm_conv_f32(
+ float32_t * pSrcA,
+ uint32_t srcALen,
+ float32_t * pSrcB,
+ uint32_t srcBLen,
+ float32_t * pDst);
+
+
+ /**
+ * @brief Convolution of Q15 sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1.
+ * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen).
+ */
+ void arm_conv_opt_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst,
+ q15_t * pScratch1,
+ q15_t * pScratch2);
+
+
+/**
+ * @brief Convolution of Q15 sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the location where the output result is written. Length srcALen+srcBLen-1.
+ */
+ void arm_conv_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst);
+
+
+ /**
+ * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1.
+ */
+ void arm_conv_fast_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst);
+
+
+ /**
+ * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1.
+ * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen).
+ */
+ void arm_conv_fast_opt_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst,
+ q15_t * pScratch1,
+ q15_t * pScratch2);
+
+
+ /**
+ * @brief Convolution of Q31 sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1.
+ */
+ void arm_conv_q31(
+ q31_t * pSrcA,
+ uint32_t srcALen,
+ q31_t * pSrcB,
+ uint32_t srcBLen,
+ q31_t * pDst);
+
+
+ /**
+ * @brief Convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1.
+ */
+ void arm_conv_fast_q31(
+ q31_t * pSrcA,
+ uint32_t srcALen,
+ q31_t * pSrcB,
+ uint32_t srcBLen,
+ q31_t * pDst);
+
+
+ /**
+ * @brief Convolution of Q7 sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1.
+ * @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ * @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).
+ */
+ void arm_conv_opt_q7(
+ q7_t * pSrcA,
+ uint32_t srcALen,
+ q7_t * pSrcB,
+ uint32_t srcBLen,
+ q7_t * pDst,
+ q15_t * pScratch1,
+ q15_t * pScratch2);
+
+
+ /**
+ * @brief Convolution of Q7 sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1.
+ */
+ void arm_conv_q7(
+ q7_t * pSrcA,
+ uint32_t srcALen,
+ q7_t * pSrcB,
+ uint32_t srcBLen,
+ q7_t * pDst);
+
+
+ /**
+ * @brief Partial convolution of floating-point sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data
+ * @param[in] firstIndex is the first output sample to start with.
+ * @param[in] numPoints is the number of output points to be computed.
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ */
+ arm_status arm_conv_partial_f32(
+ float32_t * pSrcA,
+ uint32_t srcALen,
+ float32_t * pSrcB,
+ uint32_t srcBLen,
+ float32_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints);
+
+
+ /**
+ * @brief Partial convolution of Q15 sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data
+ * @param[in] firstIndex is the first output sample to start with.
+ * @param[in] numPoints is the number of output points to be computed.
+ * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen).
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ */
+ arm_status arm_conv_partial_opt_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints,
+ q15_t * pScratch1,
+ q15_t * pScratch2);
+
+
+ /**
+ * @brief Partial convolution of Q15 sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data
+ * @param[in] firstIndex is the first output sample to start with.
+ * @param[in] numPoints is the number of output points to be computed.
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ */
+ arm_status arm_conv_partial_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints);
+
+
+ /**
+ * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data
+ * @param[in] firstIndex is the first output sample to start with.
+ * @param[in] numPoints is the number of output points to be computed.
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ */
+ arm_status arm_conv_partial_fast_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints);
+
+
+ /**
+ * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data
+ * @param[in] firstIndex is the first output sample to start with.
+ * @param[in] numPoints is the number of output points to be computed.
+ * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen).
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ */
+ arm_status arm_conv_partial_fast_opt_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints,
+ q15_t * pScratch1,
+ q15_t * pScratch2);
+
+
+ /**
+ * @brief Partial convolution of Q31 sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data
+ * @param[in] firstIndex is the first output sample to start with.
+ * @param[in] numPoints is the number of output points to be computed.
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ */
+ arm_status arm_conv_partial_q31(
+ q31_t * pSrcA,
+ uint32_t srcALen,
+ q31_t * pSrcB,
+ uint32_t srcBLen,
+ q31_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints);
+
+
+ /**
+ * @brief Partial convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data
+ * @param[in] firstIndex is the first output sample to start with.
+ * @param[in] numPoints is the number of output points to be computed.
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ */
+ arm_status arm_conv_partial_fast_q31(
+ q31_t * pSrcA,
+ uint32_t srcALen,
+ q31_t * pSrcB,
+ uint32_t srcBLen,
+ q31_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints);
+
+
+ /**
+ * @brief Partial convolution of Q7 sequences
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data
+ * @param[in] firstIndex is the first output sample to start with.
+ * @param[in] numPoints is the number of output points to be computed.
+ * @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ * @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ */
+ arm_status arm_conv_partial_opt_q7(
+ q7_t * pSrcA,
+ uint32_t srcALen,
+ q7_t * pSrcB,
+ uint32_t srcBLen,
+ q7_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints,
+ q15_t * pScratch1,
+ q15_t * pScratch2);
+
+
+/**
+ * @brief Partial convolution of Q7 sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data
+ * @param[in] firstIndex is the first output sample to start with.
+ * @param[in] numPoints is the number of output points to be computed.
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ */
+ arm_status arm_conv_partial_q7(
+ q7_t * pSrcA,
+ uint32_t srcALen,
+ q7_t * pSrcB,
+ uint32_t srcBLen,
+ q7_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints);
+
+
+ /**
+ * @brief Instance structure for the Q15 FIR decimator.
+ */
+ typedef struct
+ {
+ uint8_t M; /**< decimation factor. */
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
+ q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ } arm_fir_decimate_instance_q15;
+
+ /**
+ * @brief Instance structure for the Q31 FIR decimator.
+ */
+ typedef struct
+ {
+ uint8_t M; /**< decimation factor. */
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
+ q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ } arm_fir_decimate_instance_q31;
+
+ /**
+ * @brief Instance structure for the floating-point FIR decimator.
+ */
+ typedef struct
+ {
+ uint8_t M; /**< decimation factor. */
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
+ float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ } arm_fir_decimate_instance_f32;
+
+
+ /**
+ * @brief Processing function for the floating-point FIR decimator.
+ * @param[in] S points to an instance of the floating-point FIR decimator structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] blockSize number of input samples to process per call.
+ */
+ void arm_fir_decimate_f32(
+ const arm_fir_decimate_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the floating-point FIR decimator.
+ * @param[in,out] S points to an instance of the floating-point FIR decimator structure.
+ * @param[in] numTaps number of coefficients in the filter.
+ * @param[in] M decimation factor.
+ * @param[in] pCoeffs points to the filter coefficients.
+ * @param[in] pState points to the state buffer.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+ * <code>blockSize</code> is not a multiple of <code>M</code>.
+ */
+ arm_status arm_fir_decimate_init_f32(
+ arm_fir_decimate_instance_f32 * S,
+ uint16_t numTaps,
+ uint8_t M,
+ float32_t * pCoeffs,
+ float32_t * pState,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the Q15 FIR decimator.
+ * @param[in] S points to an instance of the Q15 FIR decimator structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] blockSize number of input samples to process per call.
+ */
+ void arm_fir_decimate_q15(
+ const arm_fir_decimate_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the Q15 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4.
+ * @param[in] S points to an instance of the Q15 FIR decimator structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] blockSize number of input samples to process per call.
+ */
+ void arm_fir_decimate_fast_q15(
+ const arm_fir_decimate_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the Q15 FIR decimator.
+ * @param[in,out] S points to an instance of the Q15 FIR decimator structure.
+ * @param[in] numTaps number of coefficients in the filter.
+ * @param[in] M decimation factor.
+ * @param[in] pCoeffs points to the filter coefficients.
+ * @param[in] pState points to the state buffer.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+ * <code>blockSize</code> is not a multiple of <code>M</code>.
+ */
+ arm_status arm_fir_decimate_init_q15(
+ arm_fir_decimate_instance_q15 * S,
+ uint16_t numTaps,
+ uint8_t M,
+ q15_t * pCoeffs,
+ q15_t * pState,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the Q31 FIR decimator.
+ * @param[in] S points to an instance of the Q31 FIR decimator structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] blockSize number of input samples to process per call.
+ */
+ void arm_fir_decimate_q31(
+ const arm_fir_decimate_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Processing function for the Q31 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4.
+ * @param[in] S points to an instance of the Q31 FIR decimator structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] blockSize number of input samples to process per call.
+ */
+ void arm_fir_decimate_fast_q31(
+ arm_fir_decimate_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the Q31 FIR decimator.
+ * @param[in,out] S points to an instance of the Q31 FIR decimator structure.
+ * @param[in] numTaps number of coefficients in the filter.
+ * @param[in] M decimation factor.
+ * @param[in] pCoeffs points to the filter coefficients.
+ * @param[in] pState points to the state buffer.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+ * <code>blockSize</code> is not a multiple of <code>M</code>.
+ */
+ arm_status arm_fir_decimate_init_q31(
+ arm_fir_decimate_instance_q31 * S,
+ uint16_t numTaps,
+ uint8_t M,
+ q31_t * pCoeffs,
+ q31_t * pState,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Instance structure for the Q15 FIR interpolator.
+ */
+ typedef struct
+ {
+ uint8_t L; /**< upsample factor. */
+ uint16_t phaseLength; /**< length of each polyphase filter component. */
+ q15_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */
+ q15_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */
+ } arm_fir_interpolate_instance_q15;
+
+ /**
+ * @brief Instance structure for the Q31 FIR interpolator.
+ */
+ typedef struct
+ {
+ uint8_t L; /**< upsample factor. */
+ uint16_t phaseLength; /**< length of each polyphase filter component. */
+ q31_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */
+ q31_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */
+ } arm_fir_interpolate_instance_q31;
+
+ /**
+ * @brief Instance structure for the floating-point FIR interpolator.
+ */
+ typedef struct
+ {
+ uint8_t L; /**< upsample factor. */
+ uint16_t phaseLength; /**< length of each polyphase filter component. */
+ float32_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */
+ float32_t *pState; /**< points to the state variable array. The array is of length phaseLength+numTaps-1. */
+ } arm_fir_interpolate_instance_f32;
+
+
+ /**
+ * @brief Processing function for the Q15 FIR interpolator.
+ * @param[in] S points to an instance of the Q15 FIR interpolator structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of input samples to process per call.
+ */
+ void arm_fir_interpolate_q15(
+ const arm_fir_interpolate_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the Q15 FIR interpolator.
+ * @param[in,out] S points to an instance of the Q15 FIR interpolator structure.
+ * @param[in] L upsample factor.
+ * @param[in] numTaps number of filter coefficients in the filter.
+ * @param[in] pCoeffs points to the filter coefficient buffer.
+ * @param[in] pState points to the state buffer.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+ * the filter length <code>numTaps</code> is not a multiple of the interpolation factor <code>L</code>.
+ */
+ arm_status arm_fir_interpolate_init_q15(
+ arm_fir_interpolate_instance_q15 * S,
+ uint8_t L,
+ uint16_t numTaps,
+ q15_t * pCoeffs,
+ q15_t * pState,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the Q31 FIR interpolator.
+ * @param[in] S points to an instance of the Q15 FIR interpolator structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of input samples to process per call.
+ */
+ void arm_fir_interpolate_q31(
+ const arm_fir_interpolate_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the Q31 FIR interpolator.
+ * @param[in,out] S points to an instance of the Q31 FIR interpolator structure.
+ * @param[in] L upsample factor.
+ * @param[in] numTaps number of filter coefficients in the filter.
+ * @param[in] pCoeffs points to the filter coefficient buffer.
+ * @param[in] pState points to the state buffer.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+ * the filter length <code>numTaps</code> is not a multiple of the interpolation factor <code>L</code>.
+ */
+ arm_status arm_fir_interpolate_init_q31(
+ arm_fir_interpolate_instance_q31 * S,
+ uint8_t L,
+ uint16_t numTaps,
+ q31_t * pCoeffs,
+ q31_t * pState,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the floating-point FIR interpolator.
+ * @param[in] S points to an instance of the floating-point FIR interpolator structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of input samples to process per call.
+ */
+ void arm_fir_interpolate_f32(
+ const arm_fir_interpolate_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the floating-point FIR interpolator.
+ * @param[in,out] S points to an instance of the floating-point FIR interpolator structure.
+ * @param[in] L upsample factor.
+ * @param[in] numTaps number of filter coefficients in the filter.
+ * @param[in] pCoeffs points to the filter coefficient buffer.
+ * @param[in] pState points to the state buffer.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+ * the filter length <code>numTaps</code> is not a multiple of the interpolation factor <code>L</code>.
+ */
+ arm_status arm_fir_interpolate_init_f32(
+ arm_fir_interpolate_instance_f32 * S,
+ uint8_t L,
+ uint16_t numTaps,
+ float32_t * pCoeffs,
+ float32_t * pState,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Instance structure for the high precision Q31 Biquad cascade filter.
+ */
+ typedef struct
+ {
+ uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */
+ q63_t *pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */
+ q31_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */
+ uint8_t postShift; /**< additional shift, in bits, applied to each output sample. */
+ } arm_biquad_cas_df1_32x64_ins_q31;
+
+
+ /**
+ * @param[in] S points to an instance of the high precision Q31 Biquad cascade filter structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_biquad_cas_df1_32x64_q31(
+ const arm_biquad_cas_df1_32x64_ins_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @param[in,out] S points to an instance of the high precision Q31 Biquad cascade filter structure.
+ * @param[in] numStages number of 2nd order stages in the filter.
+ * @param[in] pCoeffs points to the filter coefficients.
+ * @param[in] pState points to the state buffer.
+ * @param[in] postShift shift to be applied to the output. Varies according to the coefficients format
+ */
+ void arm_biquad_cas_df1_32x64_init_q31(
+ arm_biquad_cas_df1_32x64_ins_q31 * S,
+ uint8_t numStages,
+ q31_t * pCoeffs,
+ q63_t * pState,
+ uint8_t postShift);
+
+
+ /**
+ * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter.
+ */
+ typedef struct
+ {
+ uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */
+ float32_t *pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */
+ float32_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */
+ } arm_biquad_cascade_df2T_instance_f32;
+
+ /**
+ * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter.
+ */
+ typedef struct
+ {
+ uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */
+ float32_t *pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */
+ float32_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */
+ } arm_biquad_cascade_stereo_df2T_instance_f32;
+
+ /**
+ * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter.
+ */
+ typedef struct
+ {
+ uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */
+ float64_t *pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */
+ float64_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */
+ } arm_biquad_cascade_df2T_instance_f64;
+
+
+ /**
+ * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter.
+ * @param[in] S points to an instance of the filter data structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_biquad_cascade_df2T_f32(
+ const arm_biquad_cascade_df2T_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. 2 channels
+ * @param[in] S points to an instance of the filter data structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_biquad_cascade_stereo_df2T_f32(
+ const arm_biquad_cascade_stereo_df2T_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter.
+ * @param[in] S points to an instance of the filter data structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_biquad_cascade_df2T_f64(
+ const arm_biquad_cascade_df2T_instance_f64 * S,
+ float64_t * pSrc,
+ float64_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter.
+ * @param[in,out] S points to an instance of the filter data structure.
+ * @param[in] numStages number of 2nd order stages in the filter.
+ * @param[in] pCoeffs points to the filter coefficients.
+ * @param[in] pState points to the state buffer.
+ */
+ void arm_biquad_cascade_df2T_init_f32(
+ arm_biquad_cascade_df2T_instance_f32 * S,
+ uint8_t numStages,
+ float32_t * pCoeffs,
+ float32_t * pState);
+
+
+ /**
+ * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter.
+ * @param[in,out] S points to an instance of the filter data structure.
+ * @param[in] numStages number of 2nd order stages in the filter.
+ * @param[in] pCoeffs points to the filter coefficients.
+ * @param[in] pState points to the state buffer.
+ */
+ void arm_biquad_cascade_stereo_df2T_init_f32(
+ arm_biquad_cascade_stereo_df2T_instance_f32 * S,
+ uint8_t numStages,
+ float32_t * pCoeffs,
+ float32_t * pState);
+
+
+ /**
+ * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter.
+ * @param[in,out] S points to an instance of the filter data structure.
+ * @param[in] numStages number of 2nd order stages in the filter.
+ * @param[in] pCoeffs points to the filter coefficients.
+ * @param[in] pState points to the state buffer.
+ */
+ void arm_biquad_cascade_df2T_init_f64(
+ arm_biquad_cascade_df2T_instance_f64 * S,
+ uint8_t numStages,
+ float64_t * pCoeffs,
+ float64_t * pState);
+
+
+ /**
+ * @brief Instance structure for the Q15 FIR lattice filter.
+ */
+ typedef struct
+ {
+ uint16_t numStages; /**< number of filter stages. */
+ q15_t *pState; /**< points to the state variable array. The array is of length numStages. */
+ q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */
+ } arm_fir_lattice_instance_q15;
+
+ /**
+ * @brief Instance structure for the Q31 FIR lattice filter.
+ */
+ typedef struct
+ {
+ uint16_t numStages; /**< number of filter stages. */
+ q31_t *pState; /**< points to the state variable array. The array is of length numStages. */
+ q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */
+ } arm_fir_lattice_instance_q31;
+
+ /**
+ * @brief Instance structure for the floating-point FIR lattice filter.
+ */
+ typedef struct
+ {
+ uint16_t numStages; /**< number of filter stages. */
+ float32_t *pState; /**< points to the state variable array. The array is of length numStages. */
+ float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */
+ } arm_fir_lattice_instance_f32;
+
+
+ /**
+ * @brief Initialization function for the Q15 FIR lattice filter.
+ * @param[in] S points to an instance of the Q15 FIR lattice structure.
+ * @param[in] numStages number of filter stages.
+ * @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages.
+ * @param[in] pState points to the state buffer. The array is of length numStages.
+ */
+ void arm_fir_lattice_init_q15(
+ arm_fir_lattice_instance_q15 * S,
+ uint16_t numStages,
+ q15_t * pCoeffs,
+ q15_t * pState);
+
+
+ /**
+ * @brief Processing function for the Q15 FIR lattice filter.
+ * @param[in] S points to an instance of the Q15 FIR lattice structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_fir_lattice_q15(
+ const arm_fir_lattice_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the Q31 FIR lattice filter.
+ * @param[in] S points to an instance of the Q31 FIR lattice structure.
+ * @param[in] numStages number of filter stages.
+ * @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages.
+ * @param[in] pState points to the state buffer. The array is of length numStages.
+ */
+ void arm_fir_lattice_init_q31(
+ arm_fir_lattice_instance_q31 * S,
+ uint16_t numStages,
+ q31_t * pCoeffs,
+ q31_t * pState);
+
+
+ /**
+ * @brief Processing function for the Q31 FIR lattice filter.
+ * @param[in] S points to an instance of the Q31 FIR lattice structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_fir_lattice_q31(
+ const arm_fir_lattice_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Initialization function for the floating-point FIR lattice filter.
+ * @param[in] S points to an instance of the floating-point FIR lattice structure.
+ * @param[in] numStages number of filter stages.
+ * @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages.
+ * @param[in] pState points to the state buffer. The array is of length numStages.
+ */
+ void arm_fir_lattice_init_f32(
+ arm_fir_lattice_instance_f32 * S,
+ uint16_t numStages,
+ float32_t * pCoeffs,
+ float32_t * pState);
+
+
+ /**
+ * @brief Processing function for the floating-point FIR lattice filter.
+ * @param[in] S points to an instance of the floating-point FIR lattice structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_fir_lattice_f32(
+ const arm_fir_lattice_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Instance structure for the Q15 IIR lattice filter.
+ */
+ typedef struct
+ {
+ uint16_t numStages; /**< number of stages in the filter. */
+ q15_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */
+ q15_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */
+ q15_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */
+ } arm_iir_lattice_instance_q15;
+
+ /**
+ * @brief Instance structure for the Q31 IIR lattice filter.
+ */
+ typedef struct
+ {
+ uint16_t numStages; /**< number of stages in the filter. */
+ q31_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */
+ q31_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */
+ q31_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */
+ } arm_iir_lattice_instance_q31;
+
+ /**
+ * @brief Instance structure for the floating-point IIR lattice filter.
+ */
+ typedef struct
+ {
+ uint16_t numStages; /**< number of stages in the filter. */
+ float32_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */
+ float32_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */
+ float32_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */
+ } arm_iir_lattice_instance_f32;
+
+
+ /**
+ * @brief Processing function for the floating-point IIR lattice filter.
+ * @param[in] S points to an instance of the floating-point IIR lattice structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_iir_lattice_f32(
+ const arm_iir_lattice_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the floating-point IIR lattice filter.
+ * @param[in] S points to an instance of the floating-point IIR lattice structure.
+ * @param[in] numStages number of stages in the filter.
+ * @param[in] pkCoeffs points to the reflection coefficient buffer. The array is of length numStages.
+ * @param[in] pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1.
+ * @param[in] pState points to the state buffer. The array is of length numStages+blockSize-1.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_iir_lattice_init_f32(
+ arm_iir_lattice_instance_f32 * S,
+ uint16_t numStages,
+ float32_t * pkCoeffs,
+ float32_t * pvCoeffs,
+ float32_t * pState,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the Q31 IIR lattice filter.
+ * @param[in] S points to an instance of the Q31 IIR lattice structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_iir_lattice_q31(
+ const arm_iir_lattice_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the Q31 IIR lattice filter.
+ * @param[in] S points to an instance of the Q31 IIR lattice structure.
+ * @param[in] numStages number of stages in the filter.
+ * @param[in] pkCoeffs points to the reflection coefficient buffer. The array is of length numStages.
+ * @param[in] pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1.
+ * @param[in] pState points to the state buffer. The array is of length numStages+blockSize.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_iir_lattice_init_q31(
+ arm_iir_lattice_instance_q31 * S,
+ uint16_t numStages,
+ q31_t * pkCoeffs,
+ q31_t * pvCoeffs,
+ q31_t * pState,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the Q15 IIR lattice filter.
+ * @param[in] S points to an instance of the Q15 IIR lattice structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_iir_lattice_q15(
+ const arm_iir_lattice_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Initialization function for the Q15 IIR lattice filter.
+ * @param[in] S points to an instance of the fixed-point Q15 IIR lattice structure.
+ * @param[in] numStages number of stages in the filter.
+ * @param[in] pkCoeffs points to reflection coefficient buffer. The array is of length numStages.
+ * @param[in] pvCoeffs points to ladder coefficient buffer. The array is of length numStages+1.
+ * @param[in] pState points to state buffer. The array is of length numStages+blockSize.
+ * @param[in] blockSize number of samples to process per call.
+ */
+ void arm_iir_lattice_init_q15(
+ arm_iir_lattice_instance_q15 * S,
+ uint16_t numStages,
+ q15_t * pkCoeffs,
+ q15_t * pvCoeffs,
+ q15_t * pState,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Instance structure for the floating-point LMS filter.
+ */
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
+ float32_t mu; /**< step size that controls filter coefficient updates. */
+ } arm_lms_instance_f32;
+
+
+ /**
+ * @brief Processing function for floating-point LMS filter.
+ * @param[in] S points to an instance of the floating-point LMS filter structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[in] pRef points to the block of reference data.
+ * @param[out] pOut points to the block of output data.
+ * @param[out] pErr points to the block of error data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_lms_f32(
+ const arm_lms_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pRef,
+ float32_t * pOut,
+ float32_t * pErr,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for floating-point LMS filter.
+ * @param[in] S points to an instance of the floating-point LMS filter structure.
+ * @param[in] numTaps number of filter coefficients.
+ * @param[in] pCoeffs points to the coefficient buffer.
+ * @param[in] pState points to state buffer.
+ * @param[in] mu step size that controls filter coefficient updates.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_lms_init_f32(
+ arm_lms_instance_f32 * S,
+ uint16_t numTaps,
+ float32_t * pCoeffs,
+ float32_t * pState,
+ float32_t mu,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Instance structure for the Q15 LMS filter.
+ */
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
+ q15_t mu; /**< step size that controls filter coefficient updates. */
+ uint32_t postShift; /**< bit shift applied to coefficients. */
+ } arm_lms_instance_q15;
+
+
+ /**
+ * @brief Initialization function for the Q15 LMS filter.
+ * @param[in] S points to an instance of the Q15 LMS filter structure.
+ * @param[in] numTaps number of filter coefficients.
+ * @param[in] pCoeffs points to the coefficient buffer.
+ * @param[in] pState points to the state buffer.
+ * @param[in] mu step size that controls filter coefficient updates.
+ * @param[in] blockSize number of samples to process.
+ * @param[in] postShift bit shift applied to coefficients.
+ */
+ void arm_lms_init_q15(
+ arm_lms_instance_q15 * S,
+ uint16_t numTaps,
+ q15_t * pCoeffs,
+ q15_t * pState,
+ q15_t mu,
+ uint32_t blockSize,
+ uint32_t postShift);
+
+
+ /**
+ * @brief Processing function for Q15 LMS filter.
+ * @param[in] S points to an instance of the Q15 LMS filter structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[in] pRef points to the block of reference data.
+ * @param[out] pOut points to the block of output data.
+ * @param[out] pErr points to the block of error data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_lms_q15(
+ const arm_lms_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pRef,
+ q15_t * pOut,
+ q15_t * pErr,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Instance structure for the Q31 LMS filter.
+ */
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
+ q31_t mu; /**< step size that controls filter coefficient updates. */
+ uint32_t postShift; /**< bit shift applied to coefficients. */
+ } arm_lms_instance_q31;
+
+
+ /**
+ * @brief Processing function for Q31 LMS filter.
+ * @param[in] S points to an instance of the Q15 LMS filter structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[in] pRef points to the block of reference data.
+ * @param[out] pOut points to the block of output data.
+ * @param[out] pErr points to the block of error data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_lms_q31(
+ const arm_lms_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pRef,
+ q31_t * pOut,
+ q31_t * pErr,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for Q31 LMS filter.
+ * @param[in] S points to an instance of the Q31 LMS filter structure.
+ * @param[in] numTaps number of filter coefficients.
+ * @param[in] pCoeffs points to coefficient buffer.
+ * @param[in] pState points to state buffer.
+ * @param[in] mu step size that controls filter coefficient updates.
+ * @param[in] blockSize number of samples to process.
+ * @param[in] postShift bit shift applied to coefficients.
+ */
+ void arm_lms_init_q31(
+ arm_lms_instance_q31 * S,
+ uint16_t numTaps,
+ q31_t * pCoeffs,
+ q31_t * pState,
+ q31_t mu,
+ uint32_t blockSize,
+ uint32_t postShift);
+
+
+ /**
+ * @brief Instance structure for the floating-point normalized LMS filter.
+ */
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
+ float32_t mu; /**< step size that control filter coefficient updates. */
+ float32_t energy; /**< saves previous frame energy. */
+ float32_t x0; /**< saves previous input sample. */
+ } arm_lms_norm_instance_f32;
+
+
+ /**
+ * @brief Processing function for floating-point normalized LMS filter.
+ * @param[in] S points to an instance of the floating-point normalized LMS filter structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[in] pRef points to the block of reference data.
+ * @param[out] pOut points to the block of output data.
+ * @param[out] pErr points to the block of error data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_lms_norm_f32(
+ arm_lms_norm_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pRef,
+ float32_t * pOut,
+ float32_t * pErr,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for floating-point normalized LMS filter.
+ * @param[in] S points to an instance of the floating-point LMS filter structure.
+ * @param[in] numTaps number of filter coefficients.
+ * @param[in] pCoeffs points to coefficient buffer.
+ * @param[in] pState points to state buffer.
+ * @param[in] mu step size that controls filter coefficient updates.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_lms_norm_init_f32(
+ arm_lms_norm_instance_f32 * S,
+ uint16_t numTaps,
+ float32_t * pCoeffs,
+ float32_t * pState,
+ float32_t mu,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Instance structure for the Q31 normalized LMS filter.
+ */
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
+ q31_t mu; /**< step size that controls filter coefficient updates. */
+ uint8_t postShift; /**< bit shift applied to coefficients. */
+ q31_t *recipTable; /**< points to the reciprocal initial value table. */
+ q31_t energy; /**< saves previous frame energy. */
+ q31_t x0; /**< saves previous input sample. */
+ } arm_lms_norm_instance_q31;
+
+
+ /**
+ * @brief Processing function for Q31 normalized LMS filter.
+ * @param[in] S points to an instance of the Q31 normalized LMS filter structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[in] pRef points to the block of reference data.
+ * @param[out] pOut points to the block of output data.
+ * @param[out] pErr points to the block of error data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_lms_norm_q31(
+ arm_lms_norm_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pRef,
+ q31_t * pOut,
+ q31_t * pErr,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for Q31 normalized LMS filter.
+ * @param[in] S points to an instance of the Q31 normalized LMS filter structure.
+ * @param[in] numTaps number of filter coefficients.
+ * @param[in] pCoeffs points to coefficient buffer.
+ * @param[in] pState points to state buffer.
+ * @param[in] mu step size that controls filter coefficient updates.
+ * @param[in] blockSize number of samples to process.
+ * @param[in] postShift bit shift applied to coefficients.
+ */
+ void arm_lms_norm_init_q31(
+ arm_lms_norm_instance_q31 * S,
+ uint16_t numTaps,
+ q31_t * pCoeffs,
+ q31_t * pState,
+ q31_t mu,
+ uint32_t blockSize,
+ uint8_t postShift);
+
+
+ /**
+ * @brief Instance structure for the Q15 normalized LMS filter.
+ */
+ typedef struct
+ {
+ uint16_t numTaps; /**< Number of coefficients in the filter. */
+ q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
+ q15_t mu; /**< step size that controls filter coefficient updates. */
+ uint8_t postShift; /**< bit shift applied to coefficients. */
+ q15_t *recipTable; /**< Points to the reciprocal initial value table. */
+ q15_t energy; /**< saves previous frame energy. */
+ q15_t x0; /**< saves previous input sample. */
+ } arm_lms_norm_instance_q15;
+
+
+ /**
+ * @brief Processing function for Q15 normalized LMS filter.
+ * @param[in] S points to an instance of the Q15 normalized LMS filter structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[in] pRef points to the block of reference data.
+ * @param[out] pOut points to the block of output data.
+ * @param[out] pErr points to the block of error data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_lms_norm_q15(
+ arm_lms_norm_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pRef,
+ q15_t * pOut,
+ q15_t * pErr,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for Q15 normalized LMS filter.
+ * @param[in] S points to an instance of the Q15 normalized LMS filter structure.
+ * @param[in] numTaps number of filter coefficients.
+ * @param[in] pCoeffs points to coefficient buffer.
+ * @param[in] pState points to state buffer.
+ * @param[in] mu step size that controls filter coefficient updates.
+ * @param[in] blockSize number of samples to process.
+ * @param[in] postShift bit shift applied to coefficients.
+ */
+ void arm_lms_norm_init_q15(
+ arm_lms_norm_instance_q15 * S,
+ uint16_t numTaps,
+ q15_t * pCoeffs,
+ q15_t * pState,
+ q15_t mu,
+ uint32_t blockSize,
+ uint8_t postShift);
+
+
+ /**
+ * @brief Correlation of floating-point sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
+ */
+ void arm_correlate_f32(
+ float32_t * pSrcA,
+ uint32_t srcALen,
+ float32_t * pSrcB,
+ uint32_t srcBLen,
+ float32_t * pDst);
+
+
+ /**
+ * @brief Correlation of Q15 sequences
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
+ * @param[in] pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ */
+ void arm_correlate_opt_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst,
+ q15_t * pScratch);
+
+
+ /**
+ * @brief Correlation of Q15 sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
+ */
+
+ void arm_correlate_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst);
+
+
+ /**
+ * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
+ */
+
+ void arm_correlate_fast_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst);
+
+
+ /**
+ * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
+ * @param[in] pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ */
+ void arm_correlate_fast_opt_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst,
+ q15_t * pScratch);
+
+
+ /**
+ * @brief Correlation of Q31 sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
+ */
+ void arm_correlate_q31(
+ q31_t * pSrcA,
+ uint32_t srcALen,
+ q31_t * pSrcB,
+ uint32_t srcBLen,
+ q31_t * pDst);
+
+
+ /**
+ * @brief Correlation of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
+ */
+ void arm_correlate_fast_q31(
+ q31_t * pSrcA,
+ uint32_t srcALen,
+ q31_t * pSrcB,
+ uint32_t srcBLen,
+ q31_t * pDst);
+
+
+ /**
+ * @brief Correlation of Q7 sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
+ * @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ * @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).
+ */
+ void arm_correlate_opt_q7(
+ q7_t * pSrcA,
+ uint32_t srcALen,
+ q7_t * pSrcB,
+ uint32_t srcBLen,
+ q7_t * pDst,
+ q15_t * pScratch1,
+ q15_t * pScratch2);
+
+
+ /**
+ * @brief Correlation of Q7 sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
+ */
+ void arm_correlate_q7(
+ q7_t * pSrcA,
+ uint32_t srcALen,
+ q7_t * pSrcB,
+ uint32_t srcBLen,
+ q7_t * pDst);
+
+
+ /**
+ * @brief Instance structure for the floating-point sparse FIR filter.
+ */
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */
+ float32_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
+ float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
+ uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */
+ int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */
+ } arm_fir_sparse_instance_f32;
+
+ /**
+ * @brief Instance structure for the Q31 sparse FIR filter.
+ */
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */
+ q31_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
+ q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
+ uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */
+ int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */
+ } arm_fir_sparse_instance_q31;
+
+ /**
+ * @brief Instance structure for the Q15 sparse FIR filter.
+ */
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */
+ q15_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
+ q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
+ uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */
+ int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */
+ } arm_fir_sparse_instance_q15;
+
+ /**
+ * @brief Instance structure for the Q7 sparse FIR filter.
+ */
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */
+ q7_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
+ q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
+ uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */
+ int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */
+ } arm_fir_sparse_instance_q7;
+
+
+ /**
+ * @brief Processing function for the floating-point sparse FIR filter.
+ * @param[in] S points to an instance of the floating-point sparse FIR structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] pScratchIn points to a temporary buffer of size blockSize.
+ * @param[in] blockSize number of input samples to process per call.
+ */
+ void arm_fir_sparse_f32(
+ arm_fir_sparse_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pDst,
+ float32_t * pScratchIn,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the floating-point sparse FIR filter.
+ * @param[in,out] S points to an instance of the floating-point sparse FIR structure.
+ * @param[in] numTaps number of nonzero coefficients in the filter.
+ * @param[in] pCoeffs points to the array of filter coefficients.
+ * @param[in] pState points to the state buffer.
+ * @param[in] pTapDelay points to the array of offset times.
+ * @param[in] maxDelay maximum offset time supported.
+ * @param[in] blockSize number of samples that will be processed per block.
+ */
+ void arm_fir_sparse_init_f32(
+ arm_fir_sparse_instance_f32 * S,
+ uint16_t numTaps,
+ float32_t * pCoeffs,
+ float32_t * pState,
+ int32_t * pTapDelay,
+ uint16_t maxDelay,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the Q31 sparse FIR filter.
+ * @param[in] S points to an instance of the Q31 sparse FIR structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] pScratchIn points to a temporary buffer of size blockSize.
+ * @param[in] blockSize number of input samples to process per call.
+ */
+ void arm_fir_sparse_q31(
+ arm_fir_sparse_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ q31_t * pScratchIn,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the Q31 sparse FIR filter.
+ * @param[in,out] S points to an instance of the Q31 sparse FIR structure.
+ * @param[in] numTaps number of nonzero coefficients in the filter.
+ * @param[in] pCoeffs points to the array of filter coefficients.
+ * @param[in] pState points to the state buffer.
+ * @param[in] pTapDelay points to the array of offset times.
+ * @param[in] maxDelay maximum offset time supported.
+ * @param[in] blockSize number of samples that will be processed per block.
+ */
+ void arm_fir_sparse_init_q31(
+ arm_fir_sparse_instance_q31 * S,
+ uint16_t numTaps,
+ q31_t * pCoeffs,
+ q31_t * pState,
+ int32_t * pTapDelay,
+ uint16_t maxDelay,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the Q15 sparse FIR filter.
+ * @param[in] S points to an instance of the Q15 sparse FIR structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] pScratchIn points to a temporary buffer of size blockSize.
+ * @param[in] pScratchOut points to a temporary buffer of size blockSize.
+ * @param[in] blockSize number of input samples to process per call.
+ */
+ void arm_fir_sparse_q15(
+ arm_fir_sparse_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst,
+ q15_t * pScratchIn,
+ q31_t * pScratchOut,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the Q15 sparse FIR filter.
+ * @param[in,out] S points to an instance of the Q15 sparse FIR structure.
+ * @param[in] numTaps number of nonzero coefficients in the filter.
+ * @param[in] pCoeffs points to the array of filter coefficients.
+ * @param[in] pState points to the state buffer.
+ * @param[in] pTapDelay points to the array of offset times.
+ * @param[in] maxDelay maximum offset time supported.
+ * @param[in] blockSize number of samples that will be processed per block.
+ */
+ void arm_fir_sparse_init_q15(
+ arm_fir_sparse_instance_q15 * S,
+ uint16_t numTaps,
+ q15_t * pCoeffs,
+ q15_t * pState,
+ int32_t * pTapDelay,
+ uint16_t maxDelay,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the Q7 sparse FIR filter.
+ * @param[in] S points to an instance of the Q7 sparse FIR structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] pScratchIn points to a temporary buffer of size blockSize.
+ * @param[in] pScratchOut points to a temporary buffer of size blockSize.
+ * @param[in] blockSize number of input samples to process per call.
+ */
+ void arm_fir_sparse_q7(
+ arm_fir_sparse_instance_q7 * S,
+ q7_t * pSrc,
+ q7_t * pDst,
+ q7_t * pScratchIn,
+ q31_t * pScratchOut,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the Q7 sparse FIR filter.
+ * @param[in,out] S points to an instance of the Q7 sparse FIR structure.
+ * @param[in] numTaps number of nonzero coefficients in the filter.
+ * @param[in] pCoeffs points to the array of filter coefficients.
+ * @param[in] pState points to the state buffer.
+ * @param[in] pTapDelay points to the array of offset times.
+ * @param[in] maxDelay maximum offset time supported.
+ * @param[in] blockSize number of samples that will be processed per block.
+ */
+ void arm_fir_sparse_init_q7(
+ arm_fir_sparse_instance_q7 * S,
+ uint16_t numTaps,
+ q7_t * pCoeffs,
+ q7_t * pState,
+ int32_t * pTapDelay,
+ uint16_t maxDelay,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Floating-point sin_cos function.
+ * @param[in] theta input value in degrees
+ * @param[out] pSinVal points to the processed sine output.
+ * @param[out] pCosVal points to the processed cos output.
+ */
+ void arm_sin_cos_f32(
+ float32_t theta,
+ float32_t * pSinVal,
+ float32_t * pCosVal);
+
+
+ /**
+ * @brief Q31 sin_cos function.
+ * @param[in] theta scaled input value in degrees
+ * @param[out] pSinVal points to the processed sine output.
+ * @param[out] pCosVal points to the processed cosine output.
+ */
+ void arm_sin_cos_q31(
+ q31_t theta,
+ q31_t * pSinVal,
+ q31_t * pCosVal);
+
+
+ /**
+ * @brief Floating-point complex conjugate.
+ * @param[in] pSrc points to the input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] numSamples number of complex samples in each vector
+ */
+ void arm_cmplx_conj_f32(
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t numSamples);
+
+ /**
+ * @brief Q31 complex conjugate.
+ * @param[in] pSrc points to the input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] numSamples number of complex samples in each vector
+ */
+ void arm_cmplx_conj_q31(
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t numSamples);
+
+
+ /**
+ * @brief Q15 complex conjugate.
+ * @param[in] pSrc points to the input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] numSamples number of complex samples in each vector
+ */
+ void arm_cmplx_conj_q15(
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t numSamples);
+
+
+ /**
+ * @brief Floating-point complex magnitude squared
+ * @param[in] pSrc points to the complex input vector
+ * @param[out] pDst points to the real output vector
+ * @param[in] numSamples number of complex samples in the input vector
+ */
+ void arm_cmplx_mag_squared_f32(
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t numSamples);
+
+
+ /**
+ * @brief Q31 complex magnitude squared
+ * @param[in] pSrc points to the complex input vector
+ * @param[out] pDst points to the real output vector
+ * @param[in] numSamples number of complex samples in the input vector
+ */
+ void arm_cmplx_mag_squared_q31(
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t numSamples);
+
+
+ /**
+ * @brief Q15 complex magnitude squared
+ * @param[in] pSrc points to the complex input vector
+ * @param[out] pDst points to the real output vector
+ * @param[in] numSamples number of complex samples in the input vector
+ */
+ void arm_cmplx_mag_squared_q15(
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t numSamples);
+
+
+ /**
+ * @ingroup groupController
+ */
+
+ /**
+ * @defgroup PID PID Motor Control
+ *
+ * A Proportional Integral Derivative (PID) controller is a generic feedback control
+ * loop mechanism widely used in industrial control systems.
+ * A PID controller is the most commonly used type of feedback controller.
+ *
+ * This set of functions implements (PID) controllers
+ * for Q15, Q31, and floating-point data types. The functions operate on a single sample
+ * of data and each call to the function returns a single processed value.
+ * <code>S</code> points to an instance of the PID control data structure. <code>in</code>
+ * is the input sample value. The functions return the output value.
+ *
+ * \par Algorithm:
+ * <pre>
+ * y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2]
+ * A0 = Kp + Ki + Kd
+ * A1 = (-Kp ) - (2 * Kd )
+ * A2 = Kd </pre>
+ *
+ * \par
+ * where \c Kp is proportional constant, \c Ki is Integral constant and \c Kd is Derivative constant
+ *
+ * \par
+ * \image html PID.gif "Proportional Integral Derivative Controller"
+ *
+ * \par
+ * The PID controller calculates an "error" value as the difference between
+ * the measured output and the reference input.
+ * The controller attempts to minimize the error by adjusting the process control inputs.
+ * The proportional value determines the reaction to the current error,
+ * the integral value determines the reaction based on the sum of recent errors,
+ * and the derivative value determines the reaction based on the rate at which the error has been changing.
+ *
+ * \par Instance Structure
+ * The Gains A0, A1, A2 and state variables for a PID controller are stored together in an instance data structure.
+ * A separate instance structure must be defined for each PID Controller.
+ * There are separate instance structure declarations for each of the 3 supported data types.
+ *
+ * \par Reset Functions
+ * There is also an associated reset function for each data type which clears the state array.
+ *
+ * \par Initialization Functions
+ * There is also an associated initialization function for each data type.
+ * The initialization function performs the following operations:
+ * - Initializes the Gains A0, A1, A2 from Kp,Ki, Kd gains.
+ * - Zeros out the values in the state buffer.
+ *
+ * \par
+ * Instance structure cannot be placed into a const data section and it is recommended to use the initialization function.
+ *
+ * \par Fixed-Point Behavior
+ * Care must be taken when using the fixed-point versions of the PID Controller functions.
+ * In particular, the overflow and saturation behavior of the accumulator used in each function must be considered.
+ * Refer to the function specific documentation below for usage guidelines.
+ */
+
+ /**
+ * @addtogroup PID
+ * @{
+ */
+
+ /**
+ * @brief Process function for the floating-point PID Control.
+ * @param[in,out] S is an instance of the floating-point PID Control structure
+ * @param[in] in input sample to process
+ * @return out processed output sample.
+ */
+ static __INLINE float32_t arm_pid_f32(
+ arm_pid_instance_f32 * S,
+ float32_t in)
+ {
+ float32_t out;
+
+ /* y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2] */
+ out = (S->A0 * in) +
+ (S->A1 * S->state[0]) + (S->A2 * S->state[1]) + (S->state[2]);
+
+ /* Update state */
+ S->state[1] = S->state[0];
+ S->state[0] = in;
+ S->state[2] = out;
+
+ /* return to application */
+ return (out);
+
+ }
+
+ /**
+ * @brief Process function for the Q31 PID Control.
+ * @param[in,out] S points to an instance of the Q31 PID Control structure
+ * @param[in] in input sample to process
+ * @return out processed output sample.
+ *
+ * <b>Scaling and Overflow Behavior:</b>
+ * \par
+ * The function is implemented using an internal 64-bit accumulator.
+ * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit.
+ * Thus, if the accumulator result overflows it wraps around rather than clip.
+ * In order to avoid overflows completely the input signal must be scaled down by 2 bits as there are four additions.
+ * After all multiply-accumulates are performed, the 2.62 accumulator is truncated to 1.32 format and then saturated to 1.31 format.
+ */
+ static __INLINE q31_t arm_pid_q31(
+ arm_pid_instance_q31 * S,
+ q31_t in)
+ {
+ q63_t acc;
+ q31_t out;
+
+ /* acc = A0 * x[n] */
+ acc = (q63_t) S->A0 * in;
+
+ /* acc += A1 * x[n-1] */
+ acc += (q63_t) S->A1 * S->state[0];
+
+ /* acc += A2 * x[n-2] */
+ acc += (q63_t) S->A2 * S->state[1];
+
+ /* convert output to 1.31 format to add y[n-1] */
+ out = (q31_t) (acc >> 31u);
+
+ /* out += y[n-1] */
+ out += S->state[2];
+
+ /* Update state */
+ S->state[1] = S->state[0];
+ S->state[0] = in;
+ S->state[2] = out;
+
+ /* return to application */
+ return (out);
+ }
+
+
+ /**
+ * @brief Process function for the Q15 PID Control.
+ * @param[in,out] S points to an instance of the Q15 PID Control structure
+ * @param[in] in input sample to process
+ * @return out processed output sample.
+ *
+ * <b>Scaling and Overflow Behavior:</b>
+ * \par
+ * The function is implemented using a 64-bit internal accumulator.
+ * Both Gains and state variables are represented in 1.15 format and multiplications yield a 2.30 result.
+ * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format.
+ * There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved.
+ * After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits.
+ * Lastly, the accumulator is saturated to yield a result in 1.15 format.
+ */
+ static __INLINE q15_t arm_pid_q15(
+ arm_pid_instance_q15 * S,
+ q15_t in)
+ {
+ q63_t acc;
+ q15_t out;
+
+#ifndef ARM_MATH_CM0_FAMILY
+ __SIMD32_TYPE *vstate;
+
+ /* Implementation of PID controller */
+
+ /* acc = A0 * x[n] */
+ acc = (q31_t) __SMUAD((uint32_t)S->A0, (uint32_t)in);
+
+ /* acc += A1 * x[n-1] + A2 * x[n-2] */
+ vstate = __SIMD32_CONST(S->state);
+ acc = (q63_t)__SMLALD((uint32_t)S->A1, (uint32_t)*vstate, (uint64_t)acc);
+#else
+ /* acc = A0 * x[n] */
+ acc = ((q31_t) S->A0) * in;
+
+ /* acc += A1 * x[n-1] + A2 * x[n-2] */
+ acc += (q31_t) S->A1 * S->state[0];
+ acc += (q31_t) S->A2 * S->state[1];
+#endif
+
+ /* acc += y[n-1] */
+ acc += (q31_t) S->state[2] << 15;
+
+ /* saturate the output */
+ out = (q15_t) (__SSAT((acc >> 15), 16));
+
+ /* Update state */
+ S->state[1] = S->state[0];
+ S->state[0] = in;
+ S->state[2] = out;
+
+ /* return to application */
+ return (out);
+ }
+
+ /**
+ * @} end of PID group
+ */
+
+
+ /**
+ * @brief Floating-point matrix inverse.
+ * @param[in] src points to the instance of the input floating-point matrix structure.
+ * @param[out] dst points to the instance of the output floating-point matrix structure.
+ * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match.
+ * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR.
+ */
+ arm_status arm_mat_inverse_f32(
+ const arm_matrix_instance_f32 * src,
+ arm_matrix_instance_f32 * dst);
+
+
+ /**
+ * @brief Floating-point matrix inverse.
+ * @param[in] src points to the instance of the input floating-point matrix structure.
+ * @param[out] dst points to the instance of the output floating-point matrix structure.
+ * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match.
+ * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR.
+ */
+ arm_status arm_mat_inverse_f64(
+ const arm_matrix_instance_f64 * src,
+ arm_matrix_instance_f64 * dst);
+
+
+
+ /**
+ * @ingroup groupController
+ */
+
+ /**
+ * @defgroup clarke Vector Clarke Transform
+ * Forward Clarke transform converts the instantaneous stator phases into a two-coordinate time invariant vector.
+ * Generally the Clarke transform uses three-phase currents <code>Ia, Ib and Ic</code> to calculate currents
+ * in the two-phase orthogonal stator axis <code>Ialpha</code> and <code>Ibeta</code>.
+ * When <code>Ialpha</code> is superposed with <code>Ia</code> as shown in the figure below
+ * \image html clarke.gif Stator current space vector and its components in (a,b).
+ * and <code>Ia + Ib + Ic = 0</code>, in this condition <code>Ialpha</code> and <code>Ibeta</code>
+ * can be calculated using only <code>Ia</code> and <code>Ib</code>.
+ *
+ * The function operates on a single sample of data and each call to the function returns the processed output.
+ * The library provides separate functions for Q31 and floating-point data types.
+ * \par Algorithm
+ * \image html clarkeFormula.gif
+ * where <code>Ia</code> and <code>Ib</code> are the instantaneous stator phases and
+ * <code>pIalpha</code> and <code>pIbeta</code> are the two coordinates of time invariant vector.
+ * \par Fixed-Point Behavior
+ * Care must be taken when using the Q31 version of the Clarke transform.
+ * In particular, the overflow and saturation behavior of the accumulator used must be considered.
+ * Refer to the function specific documentation below for usage guidelines.
+ */
+
+ /**
+ * @addtogroup clarke
+ * @{
+ */
+
+ /**
+ *
+ * @brief Floating-point Clarke transform
+ * @param[in] Ia input three-phase coordinate <code>a</code>
+ * @param[in] Ib input three-phase coordinate <code>b</code>
+ * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha
+ * @param[out] pIbeta points to output two-phase orthogonal vector axis beta
+ */
+ static __INLINE void arm_clarke_f32(
+ float32_t Ia,
+ float32_t Ib,
+ float32_t * pIalpha,
+ float32_t * pIbeta)
+ {
+ /* Calculate pIalpha using the equation, pIalpha = Ia */
+ *pIalpha = Ia;
+
+ /* Calculate pIbeta using the equation, pIbeta = (1/sqrt(3)) * Ia + (2/sqrt(3)) * Ib */
+ *pIbeta = ((float32_t) 0.57735026919 * Ia + (float32_t) 1.15470053838 * Ib);
+ }
+
+
+ /**
+ * @brief Clarke transform for Q31 version
+ * @param[in] Ia input three-phase coordinate <code>a</code>
+ * @param[in] Ib input three-phase coordinate <code>b</code>
+ * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha
+ * @param[out] pIbeta points to output two-phase orthogonal vector axis beta
+ *
+ * <b>Scaling and Overflow Behavior:</b>
+ * \par
+ * The function is implemented using an internal 32-bit accumulator.
+ * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
+ * There is saturation on the addition, hence there is no risk of overflow.
+ */
+ static __INLINE void arm_clarke_q31(
+ q31_t Ia,
+ q31_t Ib,
+ q31_t * pIalpha,
+ q31_t * pIbeta)
+ {
+ q31_t product1, product2; /* Temporary variables used to store intermediate results */
+
+ /* Calculating pIalpha from Ia by equation pIalpha = Ia */
+ *pIalpha = Ia;
+
+ /* Intermediate product is calculated by (1/(sqrt(3)) * Ia) */
+ product1 = (q31_t) (((q63_t) Ia * 0x24F34E8B) >> 30);
+
+ /* Intermediate product is calculated by (2/sqrt(3) * Ib) */
+ product2 = (q31_t) (((q63_t) Ib * 0x49E69D16) >> 30);
+
+ /* pIbeta is calculated by adding the intermediate products */
+ *pIbeta = __QADD(product1, product2);
+ }
+
+ /**
+ * @} end of clarke group
+ */
+
+ /**
+ * @brief Converts the elements of the Q7 vector to Q31 vector.
+ * @param[in] pSrc input pointer
+ * @param[out] pDst output pointer
+ * @param[in] blockSize number of samples to process
+ */
+ void arm_q7_to_q31(
+ q7_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+
+ /**
+ * @ingroup groupController
+ */
+
+ /**
+ * @defgroup inv_clarke Vector Inverse Clarke Transform
+ * Inverse Clarke transform converts the two-coordinate time invariant vector into instantaneous stator phases.
+ *
+ * The function operates on a single sample of data and each call to the function returns the processed output.
+ * The library provides separate functions for Q31 and floating-point data types.
+ * \par Algorithm
+ * \image html clarkeInvFormula.gif
+ * where <code>pIa</code> and <code>pIb</code> are the instantaneous stator phases and
+ * <code>Ialpha</code> and <code>Ibeta</code> are the two coordinates of time invariant vector.
+ * \par Fixed-Point Behavior
+ * Care must be taken when using the Q31 version of the Clarke transform.
+ * In particular, the overflow and saturation behavior of the accumulator used must be considered.
+ * Refer to the function specific documentation below for usage guidelines.
+ */
+
+ /**
+ * @addtogroup inv_clarke
+ * @{
+ */
+
+ /**
+ * @brief Floating-point Inverse Clarke transform
+ * @param[in] Ialpha input two-phase orthogonal vector axis alpha
+ * @param[in] Ibeta input two-phase orthogonal vector axis beta
+ * @param[out] pIa points to output three-phase coordinate <code>a</code>
+ * @param[out] pIb points to output three-phase coordinate <code>b</code>
+ */
+ static __INLINE void arm_inv_clarke_f32(
+ float32_t Ialpha,
+ float32_t Ibeta,
+ float32_t * pIa,
+ float32_t * pIb)
+ {
+ /* Calculating pIa from Ialpha by equation pIa = Ialpha */
+ *pIa = Ialpha;
+
+ /* Calculating pIb from Ialpha and Ibeta by equation pIb = -(1/2) * Ialpha + (sqrt(3)/2) * Ibeta */
+ *pIb = -0.5f * Ialpha + 0.8660254039f * Ibeta;
+ }
+
+
+ /**
+ * @brief Inverse Clarke transform for Q31 version
+ * @param[in] Ialpha input two-phase orthogonal vector axis alpha
+ * @param[in] Ibeta input two-phase orthogonal vector axis beta
+ * @param[out] pIa points to output three-phase coordinate <code>a</code>
+ * @param[out] pIb points to output three-phase coordinate <code>b</code>
+ *
+ * <b>Scaling and Overflow Behavior:</b>
+ * \par
+ * The function is implemented using an internal 32-bit accumulator.
+ * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
+ * There is saturation on the subtraction, hence there is no risk of overflow.
+ */
+ static __INLINE void arm_inv_clarke_q31(
+ q31_t Ialpha,
+ q31_t Ibeta,
+ q31_t * pIa,
+ q31_t * pIb)
+ {
+ q31_t product1, product2; /* Temporary variables used to store intermediate results */
+
+ /* Calculating pIa from Ialpha by equation pIa = Ialpha */
+ *pIa = Ialpha;
+
+ /* Intermediate product is calculated by (1/(2*sqrt(3)) * Ia) */
+ product1 = (q31_t) (((q63_t) (Ialpha) * (0x40000000)) >> 31);
+
+ /* Intermediate product is calculated by (1/sqrt(3) * pIb) */
+ product2 = (q31_t) (((q63_t) (Ibeta) * (0x6ED9EBA1)) >> 31);
+
+ /* pIb is calculated by subtracting the products */
+ *pIb = __QSUB(product2, product1);
+ }
+
+ /**
+ * @} end of inv_clarke group
+ */
+
+ /**
+ * @brief Converts the elements of the Q7 vector to Q15 vector.
+ * @param[in] pSrc input pointer
+ * @param[out] pDst output pointer
+ * @param[in] blockSize number of samples to process
+ */
+ void arm_q7_to_q15(
+ q7_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+
+ /**
+ * @ingroup groupController
+ */
+
+ /**
+ * @defgroup park Vector Park Transform
+ *
+ * Forward Park transform converts the input two-coordinate vector to flux and torque components.
+ * The Park transform can be used to realize the transformation of the <code>Ialpha</code> and the <code>Ibeta</code> currents
+ * from the stationary to the moving reference frame and control the spatial relationship between
+ * the stator vector current and rotor flux vector.
+ * If we consider the d axis aligned with the rotor flux, the diagram below shows the
+ * current vector and the relationship from the two reference frames:
+ * \image html park.gif "Stator current space vector and its component in (a,b) and in the d,q rotating reference frame"
+ *
+ * The function operates on a single sample of data and each call to the function returns the processed output.
+ * The library provides separate functions for Q31 and floating-point data types.
+ * \par Algorithm
+ * \image html parkFormula.gif
+ * where <code>Ialpha</code> and <code>Ibeta</code> are the stator vector components,
+ * <code>pId</code> and <code>pIq</code> are rotor vector components and <code>cosVal</code> and <code>sinVal</code> are the
+ * cosine and sine values of theta (rotor flux position).
+ * \par Fixed-Point Behavior
+ * Care must be taken when using the Q31 version of the Park transform.
+ * In particular, the overflow and saturation behavior of the accumulator used must be considered.
+ * Refer to the function specific documentation below for usage guidelines.
+ */
+
+ /**
+ * @addtogroup park
+ * @{
+ */
+
+ /**
+ * @brief Floating-point Park transform
+ * @param[in] Ialpha input two-phase vector coordinate alpha
+ * @param[in] Ibeta input two-phase vector coordinate beta
+ * @param[out] pId points to output rotor reference frame d
+ * @param[out] pIq points to output rotor reference frame q
+ * @param[in] sinVal sine value of rotation angle theta
+ * @param[in] cosVal cosine value of rotation angle theta
+ *
+ * The function implements the forward Park transform.
+ *
+ */
+ static __INLINE void arm_park_f32(
+ float32_t Ialpha,
+ float32_t Ibeta,
+ float32_t * pId,
+ float32_t * pIq,
+ float32_t sinVal,
+ float32_t cosVal)
+ {
+ /* Calculate pId using the equation, pId = Ialpha * cosVal + Ibeta * sinVal */
+ *pId = Ialpha * cosVal + Ibeta * sinVal;
+
+ /* Calculate pIq using the equation, pIq = - Ialpha * sinVal + Ibeta * cosVal */
+ *pIq = -Ialpha * sinVal + Ibeta * cosVal;
+ }
+
+
+ /**
+ * @brief Park transform for Q31 version
+ * @param[in] Ialpha input two-phase vector coordinate alpha
+ * @param[in] Ibeta input two-phase vector coordinate beta
+ * @param[out] pId points to output rotor reference frame d
+ * @param[out] pIq points to output rotor reference frame q
+ * @param[in] sinVal sine value of rotation angle theta
+ * @param[in] cosVal cosine value of rotation angle theta
+ *
+ * <b>Scaling and Overflow Behavior:</b>
+ * \par
+ * The function is implemented using an internal 32-bit accumulator.
+ * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
+ * There is saturation on the addition and subtraction, hence there is no risk of overflow.
+ */
+ static __INLINE void arm_park_q31(
+ q31_t Ialpha,
+ q31_t Ibeta,
+ q31_t * pId,
+ q31_t * pIq,
+ q31_t sinVal,
+ q31_t cosVal)
+ {
+ q31_t product1, product2; /* Temporary variables used to store intermediate results */
+ q31_t product3, product4; /* Temporary variables used to store intermediate results */
+
+ /* Intermediate product is calculated by (Ialpha * cosVal) */
+ product1 = (q31_t) (((q63_t) (Ialpha) * (cosVal)) >> 31);
+
+ /* Intermediate product is calculated by (Ibeta * sinVal) */
+ product2 = (q31_t) (((q63_t) (Ibeta) * (sinVal)) >> 31);
+
+
+ /* Intermediate product is calculated by (Ialpha * sinVal) */
+ product3 = (q31_t) (((q63_t) (Ialpha) * (sinVal)) >> 31);
+
+ /* Intermediate product is calculated by (Ibeta * cosVal) */
+ product4 = (q31_t) (((q63_t) (Ibeta) * (cosVal)) >> 31);
+
+ /* Calculate pId by adding the two intermediate products 1 and 2 */
+ *pId = __QADD(product1, product2);
+
+ /* Calculate pIq by subtracting the two intermediate products 3 from 4 */
+ *pIq = __QSUB(product4, product3);
+ }
+
+ /**
+ * @} end of park group
+ */
+
+ /**
+ * @brief Converts the elements of the Q7 vector to floating-point vector.
+ * @param[in] pSrc is input pointer
+ * @param[out] pDst is output pointer
+ * @param[in] blockSize is the number of samples to process
+ */
+ void arm_q7_to_float(
+ q7_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @ingroup groupController
+ */
+
+ /**
+ * @defgroup inv_park Vector Inverse Park transform
+ * Inverse Park transform converts the input flux and torque components to two-coordinate vector.
+ *
+ * The function operates on a single sample of data and each call to the function returns the processed output.
+ * The library provides separate functions for Q31 and floating-point data types.
+ * \par Algorithm
+ * \image html parkInvFormula.gif
+ * where <code>pIalpha</code> and <code>pIbeta</code> are the stator vector components,
+ * <code>Id</code> and <code>Iq</code> are rotor vector components and <code>cosVal</code> and <code>sinVal</code> are the
+ * cosine and sine values of theta (rotor flux position).
+ * \par Fixed-Point Behavior
+ * Care must be taken when using the Q31 version of the Park transform.
+ * In particular, the overflow and saturation behavior of the accumulator used must be considered.
+ * Refer to the function specific documentation below for usage guidelines.
+ */
+
+ /**
+ * @addtogroup inv_park
+ * @{
+ */
+
+ /**
+ * @brief Floating-point Inverse Park transform
+ * @param[in] Id input coordinate of rotor reference frame d
+ * @param[in] Iq input coordinate of rotor reference frame q
+ * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha
+ * @param[out] pIbeta points to output two-phase orthogonal vector axis beta
+ * @param[in] sinVal sine value of rotation angle theta
+ * @param[in] cosVal cosine value of rotation angle theta
+ */
+ static __INLINE void arm_inv_park_f32(
+ float32_t Id,
+ float32_t Iq,
+ float32_t * pIalpha,
+ float32_t * pIbeta,
+ float32_t sinVal,
+ float32_t cosVal)
+ {
+ /* Calculate pIalpha using the equation, pIalpha = Id * cosVal - Iq * sinVal */
+ *pIalpha = Id * cosVal - Iq * sinVal;
+
+ /* Calculate pIbeta using the equation, pIbeta = Id * sinVal + Iq * cosVal */
+ *pIbeta = Id * sinVal + Iq * cosVal;
+ }
+
+
+ /**
+ * @brief Inverse Park transform for Q31 version
+ * @param[in] Id input coordinate of rotor reference frame d
+ * @param[in] Iq input coordinate of rotor reference frame q
+ * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha
+ * @param[out] pIbeta points to output two-phase orthogonal vector axis beta
+ * @param[in] sinVal sine value of rotation angle theta
+ * @param[in] cosVal cosine value of rotation angle theta
+ *
+ * <b>Scaling and Overflow Behavior:</b>
+ * \par
+ * The function is implemented using an internal 32-bit accumulator.
+ * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
+ * There is saturation on the addition, hence there is no risk of overflow.
+ */
+ static __INLINE void arm_inv_park_q31(
+ q31_t Id,
+ q31_t Iq,
+ q31_t * pIalpha,
+ q31_t * pIbeta,
+ q31_t sinVal,
+ q31_t cosVal)
+ {
+ q31_t product1, product2; /* Temporary variables used to store intermediate results */
+ q31_t product3, product4; /* Temporary variables used to store intermediate results */
+
+ /* Intermediate product is calculated by (Id * cosVal) */
+ product1 = (q31_t) (((q63_t) (Id) * (cosVal)) >> 31);
+
+ /* Intermediate product is calculated by (Iq * sinVal) */
+ product2 = (q31_t) (((q63_t) (Iq) * (sinVal)) >> 31);
+
+
+ /* Intermediate product is calculated by (Id * sinVal) */
+ product3 = (q31_t) (((q63_t) (Id) * (sinVal)) >> 31);
+
+ /* Intermediate product is calculated by (Iq * cosVal) */
+ product4 = (q31_t) (((q63_t) (Iq) * (cosVal)) >> 31);
+
+ /* Calculate pIalpha by using the two intermediate products 1 and 2 */
+ *pIalpha = __QSUB(product1, product2);
+
+ /* Calculate pIbeta by using the two intermediate products 3 and 4 */
+ *pIbeta = __QADD(product4, product3);
+ }
+
+ /**
+ * @} end of Inverse park group
+ */
+
+
+ /**
+ * @brief Converts the elements of the Q31 vector to floating-point vector.
+ * @param[in] pSrc is input pointer
+ * @param[out] pDst is output pointer
+ * @param[in] blockSize is the number of samples to process
+ */
+ void arm_q31_to_float(
+ q31_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @ingroup groupInterpolation
+ */
+
+ /**
+ * @defgroup LinearInterpolate Linear Interpolation
+ *
+ * Linear interpolation is a method of curve fitting using linear polynomials.
+ * Linear interpolation works by effectively drawing a straight line between two neighboring samples and returning the appropriate point along that line
+ *
+ * \par
+ * \image html LinearInterp.gif "Linear interpolation"
+ *
+ * \par
+ * A Linear Interpolate function calculates an output value(y), for the input(x)
+ * using linear interpolation of the input values x0, x1( nearest input values) and the output values y0 and y1(nearest output values)
+ *
+ * \par Algorithm:
+ * <pre>
+ * y = y0 + (x - x0) * ((y1 - y0)/(x1-x0))
+ * where x0, x1 are nearest values of input x
+ * y0, y1 are nearest values to output y
+ * </pre>
+ *
+ * \par
+ * This set of functions implements Linear interpolation process
+ * for Q7, Q15, Q31, and floating-point data types. The functions operate on a single
+ * sample of data and each call to the function returns a single processed value.
+ * <code>S</code> points to an instance of the Linear Interpolate function data structure.
+ * <code>x</code> is the input sample value. The functions returns the output value.
+ *
+ * \par
+ * if x is outside of the table boundary, Linear interpolation returns first value of the table
+ * if x is below input range and returns last value of table if x is above range.
+ */
+
+ /**
+ * @addtogroup LinearInterpolate
+ * @{
+ */
+
+ /**
+ * @brief Process function for the floating-point Linear Interpolation Function.
+ * @param[in,out] S is an instance of the floating-point Linear Interpolation structure
+ * @param[in] x input sample to process
+ * @return y processed output sample.
+ *
+ */
+ static __INLINE float32_t arm_linear_interp_f32(
+ arm_linear_interp_instance_f32 * S,
+ float32_t x)
+ {
+ float32_t y;
+ float32_t x0, x1; /* Nearest input values */
+ float32_t y0, y1; /* Nearest output values */
+ float32_t xSpacing = S->xSpacing; /* spacing between input values */
+ int32_t i; /* Index variable */
+ float32_t *pYData = S->pYData; /* pointer to output table */
+
+ /* Calculation of index */
+ i = (int32_t) ((x - S->x1) / xSpacing);
+
+ if(i < 0)
+ {
+ /* Iniatilize output for below specified range as least output value of table */
+ y = pYData[0];
+ }
+ else if((uint32_t)i >= S->nValues)
+ {
+ /* Iniatilize output for above specified range as last output value of table */
+ y = pYData[S->nValues - 1];
+ }
+ else
+ {
+ /* Calculation of nearest input values */
+ x0 = S->x1 + i * xSpacing;
+ x1 = S->x1 + (i + 1) * xSpacing;
+
+ /* Read of nearest output values */
+ y0 = pYData[i];
+ y1 = pYData[i + 1];
+
+ /* Calculation of output */
+ y = y0 + (x - x0) * ((y1 - y0) / (x1 - x0));
+
+ }
+
+ /* returns output value */
+ return (y);
+ }
+
+
+ /**
+ *
+ * @brief Process function for the Q31 Linear Interpolation Function.
+ * @param[in] pYData pointer to Q31 Linear Interpolation table
+ * @param[in] x input sample to process
+ * @param[in] nValues number of table values
+ * @return y processed output sample.
+ *
+ * \par
+ * Input sample <code>x</code> is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.
+ * This function can support maximum of table size 2^12.
+ *
+ */
+ static __INLINE q31_t arm_linear_interp_q31(
+ q31_t * pYData,
+ q31_t x,
+ uint32_t nValues)
+ {
+ q31_t y; /* output */
+ q31_t y0, y1; /* Nearest output values */
+ q31_t fract; /* fractional part */
+ int32_t index; /* Index to read nearest output values */
+
+ /* Input is in 12.20 format */
+ /* 12 bits for the table index */
+ /* Index value calculation */
+ index = ((x & (q31_t)0xFFF00000) >> 20);
+
+ if(index >= (int32_t)(nValues - 1))
+ {
+ return (pYData[nValues - 1]);
+ }
+ else if(index < 0)
+ {
+ return (pYData[0]);
+ }
+ else
+ {
+ /* 20 bits for the fractional part */
+ /* shift left by 11 to keep fract in 1.31 format */
+ fract = (x & 0x000FFFFF) << 11;
+
+ /* Read two nearest output values from the index in 1.31(q31) format */
+ y0 = pYData[index];
+ y1 = pYData[index + 1];
+
+ /* Calculation of y0 * (1-fract) and y is in 2.30 format */
+ y = ((q31_t) ((q63_t) y0 * (0x7FFFFFFF - fract) >> 32));
+
+ /* Calculation of y0 * (1-fract) + y1 *fract and y is in 2.30 format */
+ y += ((q31_t) (((q63_t) y1 * fract) >> 32));
+
+ /* Convert y to 1.31 format */
+ return (y << 1u);
+ }
+ }
+
+
+ /**
+ *
+ * @brief Process function for the Q15 Linear Interpolation Function.
+ * @param[in] pYData pointer to Q15 Linear Interpolation table
+ * @param[in] x input sample to process
+ * @param[in] nValues number of table values
+ * @return y processed output sample.
+ *
+ * \par
+ * Input sample <code>x</code> is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.
+ * This function can support maximum of table size 2^12.
+ *
+ */
+ static __INLINE q15_t arm_linear_interp_q15(
+ q15_t * pYData,
+ q31_t x,
+ uint32_t nValues)
+ {
+ q63_t y; /* output */
+ q15_t y0, y1; /* Nearest output values */
+ q31_t fract; /* fractional part */
+ int32_t index; /* Index to read nearest output values */
+
+ /* Input is in 12.20 format */
+ /* 12 bits for the table index */
+ /* Index value calculation */
+ index = ((x & (int32_t)0xFFF00000) >> 20);
+
+ if(index >= (int32_t)(nValues - 1))
+ {
+ return (pYData[nValues - 1]);
+ }
+ else if(index < 0)
+ {
+ return (pYData[0]);
+ }
+ else
+ {
+ /* 20 bits for the fractional part */
+ /* fract is in 12.20 format */
+ fract = (x & 0x000FFFFF);
+
+ /* Read two nearest output values from the index */
+ y0 = pYData[index];
+ y1 = pYData[index + 1];
+
+ /* Calculation of y0 * (1-fract) and y is in 13.35 format */
+ y = ((q63_t) y0 * (0xFFFFF - fract));
+
+ /* Calculation of (y0 * (1-fract) + y1 * fract) and y is in 13.35 format */
+ y += ((q63_t) y1 * (fract));
+
+ /* convert y to 1.15 format */
+ return (q15_t) (y >> 20);
+ }
+ }
+
+
+ /**
+ *
+ * @brief Process function for the Q7 Linear Interpolation Function.
+ * @param[in] pYData pointer to Q7 Linear Interpolation table
+ * @param[in] x input sample to process
+ * @param[in] nValues number of table values
+ * @return y processed output sample.
+ *
+ * \par
+ * Input sample <code>x</code> is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.
+ * This function can support maximum of table size 2^12.
+ */
+ static __INLINE q7_t arm_linear_interp_q7(
+ q7_t * pYData,
+ q31_t x,
+ uint32_t nValues)
+ {
+ q31_t y; /* output */
+ q7_t y0, y1; /* Nearest output values */
+ q31_t fract; /* fractional part */
+ uint32_t index; /* Index to read nearest output values */
+
+ /* Input is in 12.20 format */
+ /* 12 bits for the table index */
+ /* Index value calculation */
+ if (x < 0)
+ {
+ return (pYData[0]);
+ }
+ index = (x >> 20) & 0xfff;
+
+ if(index >= (nValues - 1))
+ {
+ return (pYData[nValues - 1]);
+ }
+ else
+ {
+ /* 20 bits for the fractional part */
+ /* fract is in 12.20 format */
+ fract = (x & 0x000FFFFF);
+
+ /* Read two nearest output values from the index and are in 1.7(q7) format */
+ y0 = pYData[index];
+ y1 = pYData[index + 1];
+
+ /* Calculation of y0 * (1-fract ) and y is in 13.27(q27) format */
+ y = ((y0 * (0xFFFFF - fract)));
+
+ /* Calculation of y1 * fract + y0 * (1-fract) and y is in 13.27(q27) format */
+ y += (y1 * fract);
+
+ /* convert y to 1.7(q7) format */
+ return (q7_t) (y >> 20);
+ }
+ }
+
+ /**
+ * @} end of LinearInterpolate group
+ */
+
+ /**
+ * @brief Fast approximation to the trigonometric sine function for floating-point data.
+ * @param[in] x input value in radians.
+ * @return sin(x).
+ */
+ float32_t arm_sin_f32(
+ float32_t x);
+
+
+ /**
+ * @brief Fast approximation to the trigonometric sine function for Q31 data.
+ * @param[in] x Scaled input value in radians.
+ * @return sin(x).
+ */
+ q31_t arm_sin_q31(
+ q31_t x);
+
+
+ /**
+ * @brief Fast approximation to the trigonometric sine function for Q15 data.
+ * @param[in] x Scaled input value in radians.
+ * @return sin(x).
+ */
+ q15_t arm_sin_q15(
+ q15_t x);
+
+
+ /**
+ * @brief Fast approximation to the trigonometric cosine function for floating-point data.
+ * @param[in] x input value in radians.
+ * @return cos(x).
+ */
+ float32_t arm_cos_f32(
+ float32_t x);
+
+
+ /**
+ * @brief Fast approximation to the trigonometric cosine function for Q31 data.
+ * @param[in] x Scaled input value in radians.
+ * @return cos(x).
+ */
+ q31_t arm_cos_q31(
+ q31_t x);
+
+
+ /**
+ * @brief Fast approximation to the trigonometric cosine function for Q15 data.
+ * @param[in] x Scaled input value in radians.
+ * @return cos(x).
+ */
+ q15_t arm_cos_q15(
+ q15_t x);
+
+
+ /**
+ * @ingroup groupFastMath
+ */
+
+
+ /**
+ * @defgroup SQRT Square Root
+ *
+ * Computes the square root of a number.
+ * There are separate functions for Q15, Q31, and floating-point data types.
+ * The square root function is computed using the Newton-Raphson algorithm.
+ * This is an iterative algorithm of the form:
+ * <pre>
+ * x1 = x0 - f(x0)/f'(x0)
+ * </pre>
+ * where <code>x1</code> is the current estimate,
+ * <code>x0</code> is the previous estimate, and
+ * <code>f'(x0)</code> is the derivative of <code>f()</code> evaluated at <code>x0</code>.
+ * For the square root function, the algorithm reduces to:
+ * <pre>
+ * x0 = in/2 [initial guess]
+ * x1 = 1/2 * ( x0 + in / x0) [each iteration]
+ * </pre>
+ */
+
+
+ /**
+ * @addtogroup SQRT
+ * @{
+ */
+
+ /**
+ * @brief Floating-point square root function.
+ * @param[in] in input value.
+ * @param[out] pOut square root of input value.
+ * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if
+ * <code>in</code> is negative value and returns zero output for negative values.
+ */
+ static __INLINE arm_status arm_sqrt_f32(
+ float32_t in,
+ float32_t * pOut)
+ {
+ if(in >= 0.0f)
+ {
+
+#if (__FPU_USED == 1) && defined ( __CC_ARM )
+ *pOut = __sqrtf(in);
+#elif (__FPU_USED == 1) && (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050))
+ *pOut = __builtin_sqrtf(in);
+#elif (__FPU_USED == 1) && defined(__GNUC__)
+ *pOut = __builtin_sqrtf(in);
+#elif (__FPU_USED == 1) && defined ( __ICCARM__ ) && (__VER__ >= 6040000)
+ __ASM("VSQRT.F32 %0,%1" : "=t"(*pOut) : "t"(in));
+#else
+ *pOut = sqrtf(in);
+#endif
+
+ return (ARM_MATH_SUCCESS);
+ }
+ else
+ {
+ *pOut = 0.0f;
+ return (ARM_MATH_ARGUMENT_ERROR);
+ }
+ }
+
+
+ /**
+ * @brief Q31 square root function.
+ * @param[in] in input value. The range of the input value is [0 +1) or 0x00000000 to 0x7FFFFFFF.
+ * @param[out] pOut square root of input value.
+ * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if
+ * <code>in</code> is negative value and returns zero output for negative values.
+ */
+ arm_status arm_sqrt_q31(
+ q31_t in,
+ q31_t * pOut);
+
+
+ /**
+ * @brief Q15 square root function.
+ * @param[in] in input value. The range of the input value is [0 +1) or 0x0000 to 0x7FFF.
+ * @param[out] pOut square root of input value.
+ * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if
+ * <code>in</code> is negative value and returns zero output for negative values.
+ */
+ arm_status arm_sqrt_q15(
+ q15_t in,
+ q15_t * pOut);
+
+ /**
+ * @} end of SQRT group
+ */
+
+
+ /**
+ * @brief floating-point Circular write function.
+ */
+ static __INLINE void arm_circularWrite_f32(
+ int32_t * circBuffer,
+ int32_t L,
+ uint16_t * writeOffset,
+ int32_t bufferInc,
+ const int32_t * src,
+ int32_t srcInc,
+ uint32_t blockSize)
+ {
+ uint32_t i = 0u;
+ int32_t wOffset;
+
+ /* Copy the value of Index pointer that points
+ * to the current location where the input samples to be copied */
+ wOffset = *writeOffset;
+
+ /* Loop over the blockSize */
+ i = blockSize;
+
+ while(i > 0u)
+ {
+ /* copy the input sample to the circular buffer */
+ circBuffer[wOffset] = *src;
+
+ /* Update the input pointer */
+ src += srcInc;
+
+ /* Circularly update wOffset. Watch out for positive and negative value */
+ wOffset += bufferInc;
+ if(wOffset >= L)
+ wOffset -= L;
+
+ /* Decrement the loop counter */
+ i--;
+ }
+
+ /* Update the index pointer */
+ *writeOffset = (uint16_t)wOffset;
+ }
+
+
+
+ /**
+ * @brief floating-point Circular Read function.
+ */
+ static __INLINE void arm_circularRead_f32(
+ int32_t * circBuffer,
+ int32_t L,
+ int32_t * readOffset,
+ int32_t bufferInc,
+ int32_t * dst,
+ int32_t * dst_base,
+ int32_t dst_length,
+ int32_t dstInc,
+ uint32_t blockSize)
+ {
+ uint32_t i = 0u;
+ int32_t rOffset, dst_end;
+
+ /* Copy the value of Index pointer that points
+ * to the current location from where the input samples to be read */
+ rOffset = *readOffset;
+ dst_end = (int32_t) (dst_base + dst_length);
+
+ /* Loop over the blockSize */
+ i = blockSize;
+
+ while(i > 0u)
+ {
+ /* copy the sample from the circular buffer to the destination buffer */
+ *dst = circBuffer[rOffset];
+
+ /* Update the input pointer */
+ dst += dstInc;
+
+ if(dst == (int32_t *) dst_end)
+ {
+ dst = dst_base;
+ }
+
+ /* Circularly update rOffset. Watch out for positive and negative value */
+ rOffset += bufferInc;
+
+ if(rOffset >= L)
+ {
+ rOffset -= L;
+ }
+
+ /* Decrement the loop counter */
+ i--;
+ }
+
+ /* Update the index pointer */
+ *readOffset = rOffset;
+ }
+
+
+ /**
+ * @brief Q15 Circular write function.
+ */
+ static __INLINE void arm_circularWrite_q15(
+ q15_t * circBuffer,
+ int32_t L,
+ uint16_t * writeOffset,
+ int32_t bufferInc,
+ const q15_t * src,
+ int32_t srcInc,
+ uint32_t blockSize)
+ {
+ uint32_t i = 0u;
+ int32_t wOffset;
+
+ /* Copy the value of Index pointer that points
+ * to the current location where the input samples to be copied */
+ wOffset = *writeOffset;
+
+ /* Loop over the blockSize */
+ i = blockSize;
+
+ while(i > 0u)
+ {
+ /* copy the input sample to the circular buffer */
+ circBuffer[wOffset] = *src;
+
+ /* Update the input pointer */
+ src += srcInc;
+
+ /* Circularly update wOffset. Watch out for positive and negative value */
+ wOffset += bufferInc;
+ if(wOffset >= L)
+ wOffset -= L;
+
+ /* Decrement the loop counter */
+ i--;
+ }
+
+ /* Update the index pointer */
+ *writeOffset = (uint16_t)wOffset;
+ }
+
+
+ /**
+ * @brief Q15 Circular Read function.
+ */
+ static __INLINE void arm_circularRead_q15(
+ q15_t * circBuffer,
+ int32_t L,
+ int32_t * readOffset,
+ int32_t bufferInc,
+ q15_t * dst,
+ q15_t * dst_base,
+ int32_t dst_length,
+ int32_t dstInc,
+ uint32_t blockSize)
+ {
+ uint32_t i = 0;
+ int32_t rOffset, dst_end;
+
+ /* Copy the value of Index pointer that points
+ * to the current location from where the input samples to be read */
+ rOffset = *readOffset;
+
+ dst_end = (int32_t) (dst_base + dst_length);
+
+ /* Loop over the blockSize */
+ i = blockSize;
+
+ while(i > 0u)
+ {
+ /* copy the sample from the circular buffer to the destination buffer */
+ *dst = circBuffer[rOffset];
+
+ /* Update the input pointer */
+ dst += dstInc;
+
+ if(dst == (q15_t *) dst_end)
+ {
+ dst = dst_base;
+ }
+
+ /* Circularly update wOffset. Watch out for positive and negative value */
+ rOffset += bufferInc;
+
+ if(rOffset >= L)
+ {
+ rOffset -= L;
+ }
+
+ /* Decrement the loop counter */
+ i--;
+ }
+
+ /* Update the index pointer */
+ *readOffset = rOffset;
+ }
+
+
+ /**
+ * @brief Q7 Circular write function.
+ */
+ static __INLINE void arm_circularWrite_q7(
+ q7_t * circBuffer,
+ int32_t L,
+ uint16_t * writeOffset,
+ int32_t bufferInc,
+ const q7_t * src,
+ int32_t srcInc,
+ uint32_t blockSize)
+ {
+ uint32_t i = 0u;
+ int32_t wOffset;
+
+ /* Copy the value of Index pointer that points
+ * to the current location where the input samples to be copied */
+ wOffset = *writeOffset;
+
+ /* Loop over the blockSize */
+ i = blockSize;
+
+ while(i > 0u)
+ {
+ /* copy the input sample to the circular buffer */
+ circBuffer[wOffset] = *src;
+
+ /* Update the input pointer */
+ src += srcInc;
+
+ /* Circularly update wOffset. Watch out for positive and negative value */
+ wOffset += bufferInc;
+ if(wOffset >= L)
+ wOffset -= L;
+
+ /* Decrement the loop counter */
+ i--;
+ }
+
+ /* Update the index pointer */
+ *writeOffset = (uint16_t)wOffset;
+ }
+
+
+ /**
+ * @brief Q7 Circular Read function.
+ */
+ static __INLINE void arm_circularRead_q7(
+ q7_t * circBuffer,
+ int32_t L,
+ int32_t * readOffset,
+ int32_t bufferInc,
+ q7_t * dst,
+ q7_t * dst_base,
+ int32_t dst_length,
+ int32_t dstInc,
+ uint32_t blockSize)
+ {
+ uint32_t i = 0;
+ int32_t rOffset, dst_end;
+
+ /* Copy the value of Index pointer that points
+ * to the current location from where the input samples to be read */
+ rOffset = *readOffset;
+
+ dst_end = (int32_t) (dst_base + dst_length);
+
+ /* Loop over the blockSize */
+ i = blockSize;
+
+ while(i > 0u)
+ {
+ /* copy the sample from the circular buffer to the destination buffer */
+ *dst = circBuffer[rOffset];
+
+ /* Update the input pointer */
+ dst += dstInc;
+
+ if(dst == (q7_t *) dst_end)
+ {
+ dst = dst_base;
+ }
+
+ /* Circularly update rOffset. Watch out for positive and negative value */
+ rOffset += bufferInc;
+
+ if(rOffset >= L)
+ {
+ rOffset -= L;
+ }
+
+ /* Decrement the loop counter */
+ i--;
+ }
+
+ /* Update the index pointer */
+ *readOffset = rOffset;
+ }
+
+
+ /**
+ * @brief Sum of the squares of the elements of a Q31 vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+ void arm_power_q31(
+ q31_t * pSrc,
+ uint32_t blockSize,
+ q63_t * pResult);
+
+
+ /**
+ * @brief Sum of the squares of the elements of a floating-point vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+ void arm_power_f32(
+ float32_t * pSrc,
+ uint32_t blockSize,
+ float32_t * pResult);
+
+
+ /**
+ * @brief Sum of the squares of the elements of a Q15 vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+ void arm_power_q15(
+ q15_t * pSrc,
+ uint32_t blockSize,
+ q63_t * pResult);
+
+
+ /**
+ * @brief Sum of the squares of the elements of a Q7 vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+ void arm_power_q7(
+ q7_t * pSrc,
+ uint32_t blockSize,
+ q31_t * pResult);
+
+
+ /**
+ * @brief Mean value of a Q7 vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+ void arm_mean_q7(
+ q7_t * pSrc,
+ uint32_t blockSize,
+ q7_t * pResult);
+
+
+ /**
+ * @brief Mean value of a Q15 vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+ void arm_mean_q15(
+ q15_t * pSrc,
+ uint32_t blockSize,
+ q15_t * pResult);
+
+
+ /**
+ * @brief Mean value of a Q31 vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+ void arm_mean_q31(
+ q31_t * pSrc,
+ uint32_t blockSize,
+ q31_t * pResult);
+
+
+ /**
+ * @brief Mean value of a floating-point vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+ void arm_mean_f32(
+ float32_t * pSrc,
+ uint32_t blockSize,
+ float32_t * pResult);
+
+
+ /**
+ * @brief Variance of the elements of a floating-point vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+ void arm_var_f32(
+ float32_t * pSrc,
+ uint32_t blockSize,
+ float32_t * pResult);
+
+
+ /**
+ * @brief Variance of the elements of a Q31 vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+ void arm_var_q31(
+ q31_t * pSrc,
+ uint32_t blockSize,
+ q31_t * pResult);
+
+
+ /**
+ * @brief Variance of the elements of a Q15 vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+ void arm_var_q15(
+ q15_t * pSrc,
+ uint32_t blockSize,
+ q15_t * pResult);
+
+
+ /**
+ * @brief Root Mean Square of the elements of a floating-point vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+ void arm_rms_f32(
+ float32_t * pSrc,
+ uint32_t blockSize,
+ float32_t * pResult);
+
+
+ /**
+ * @brief Root Mean Square of the elements of a Q31 vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+ void arm_rms_q31(
+ q31_t * pSrc,
+ uint32_t blockSize,
+ q31_t * pResult);
+
+
+ /**
+ * @brief Root Mean Square of the elements of a Q15 vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+ void arm_rms_q15(
+ q15_t * pSrc,
+ uint32_t blockSize,
+ q15_t * pResult);
+
+
+ /**
+ * @brief Standard deviation of the elements of a floating-point vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+ void arm_std_f32(
+ float32_t * pSrc,
+ uint32_t blockSize,
+ float32_t * pResult);
+
+
+ /**
+ * @brief Standard deviation of the elements of a Q31 vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+ void arm_std_q31(
+ q31_t * pSrc,
+ uint32_t blockSize,
+ q31_t * pResult);
+
+
+ /**
+ * @brief Standard deviation of the elements of a Q15 vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+ void arm_std_q15(
+ q15_t * pSrc,
+ uint32_t blockSize,
+ q15_t * pResult);
+
+
+ /**
+ * @brief Floating-point complex magnitude
+ * @param[in] pSrc points to the complex input vector
+ * @param[out] pDst points to the real output vector
+ * @param[in] numSamples number of complex samples in the input vector
+ */
+ void arm_cmplx_mag_f32(
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t numSamples);
+
+
+ /**
+ * @brief Q31 complex magnitude
+ * @param[in] pSrc points to the complex input vector
+ * @param[out] pDst points to the real output vector
+ * @param[in] numSamples number of complex samples in the input vector
+ */
+ void arm_cmplx_mag_q31(
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t numSamples);
+
+
+ /**
+ * @brief Q15 complex magnitude
+ * @param[in] pSrc points to the complex input vector
+ * @param[out] pDst points to the real output vector
+ * @param[in] numSamples number of complex samples in the input vector
+ */
+ void arm_cmplx_mag_q15(
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t numSamples);
+
+
+ /**
+ * @brief Q15 complex dot product
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[in] numSamples number of complex samples in each vector
+ * @param[out] realResult real part of the result returned here
+ * @param[out] imagResult imaginary part of the result returned here
+ */
+ void arm_cmplx_dot_prod_q15(
+ q15_t * pSrcA,
+ q15_t * pSrcB,
+ uint32_t numSamples,
+ q31_t * realResult,
+ q31_t * imagResult);
+
+
+ /**
+ * @brief Q31 complex dot product
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[in] numSamples number of complex samples in each vector
+ * @param[out] realResult real part of the result returned here
+ * @param[out] imagResult imaginary part of the result returned here
+ */
+ void arm_cmplx_dot_prod_q31(
+ q31_t * pSrcA,
+ q31_t * pSrcB,
+ uint32_t numSamples,
+ q63_t * realResult,
+ q63_t * imagResult);
+
+
+ /**
+ * @brief Floating-point complex dot product
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[in] numSamples number of complex samples in each vector
+ * @param[out] realResult real part of the result returned here
+ * @param[out] imagResult imaginary part of the result returned here
+ */
+ void arm_cmplx_dot_prod_f32(
+ float32_t * pSrcA,
+ float32_t * pSrcB,
+ uint32_t numSamples,
+ float32_t * realResult,
+ float32_t * imagResult);
+
+
+ /**
+ * @brief Q15 complex-by-real multiplication
+ * @param[in] pSrcCmplx points to the complex input vector
+ * @param[in] pSrcReal points to the real input vector
+ * @param[out] pCmplxDst points to the complex output vector
+ * @param[in] numSamples number of samples in each vector
+ */
+ void arm_cmplx_mult_real_q15(
+ q15_t * pSrcCmplx,
+ q15_t * pSrcReal,
+ q15_t * pCmplxDst,
+ uint32_t numSamples);
+
+
+ /**
+ * @brief Q31 complex-by-real multiplication
+ * @param[in] pSrcCmplx points to the complex input vector
+ * @param[in] pSrcReal points to the real input vector
+ * @param[out] pCmplxDst points to the complex output vector
+ * @param[in] numSamples number of samples in each vector
+ */
+ void arm_cmplx_mult_real_q31(
+ q31_t * pSrcCmplx,
+ q31_t * pSrcReal,
+ q31_t * pCmplxDst,
+ uint32_t numSamples);
+
+
+ /**
+ * @brief Floating-point complex-by-real multiplication
+ * @param[in] pSrcCmplx points to the complex input vector
+ * @param[in] pSrcReal points to the real input vector
+ * @param[out] pCmplxDst points to the complex output vector
+ * @param[in] numSamples number of samples in each vector
+ */
+ void arm_cmplx_mult_real_f32(
+ float32_t * pSrcCmplx,
+ float32_t * pSrcReal,
+ float32_t * pCmplxDst,
+ uint32_t numSamples);
+
+
+ /**
+ * @brief Minimum value of a Q7 vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] result is output pointer
+ * @param[in] index is the array index of the minimum value in the input buffer.
+ */
+ void arm_min_q7(
+ q7_t * pSrc,
+ uint32_t blockSize,
+ q7_t * result,
+ uint32_t * index);
+
+
+ /**
+ * @brief Minimum value of a Q15 vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output pointer
+ * @param[in] pIndex is the array index of the minimum value in the input buffer.
+ */
+ void arm_min_q15(
+ q15_t * pSrc,
+ uint32_t blockSize,
+ q15_t * pResult,
+ uint32_t * pIndex);
+
+
+ /**
+ * @brief Minimum value of a Q31 vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output pointer
+ * @param[out] pIndex is the array index of the minimum value in the input buffer.
+ */
+ void arm_min_q31(
+ q31_t * pSrc,
+ uint32_t blockSize,
+ q31_t * pResult,
+ uint32_t * pIndex);
+
+
+ /**
+ * @brief Minimum value of a floating-point vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output pointer
+ * @param[out] pIndex is the array index of the minimum value in the input buffer.
+ */
+ void arm_min_f32(
+ float32_t * pSrc,
+ uint32_t blockSize,
+ float32_t * pResult,
+ uint32_t * pIndex);
+
+
+/**
+ * @brief Maximum value of a Q7 vector.
+ * @param[in] pSrc points to the input buffer
+ * @param[in] blockSize length of the input vector
+ * @param[out] pResult maximum value returned here
+ * @param[out] pIndex index of maximum value returned here
+ */
+ void arm_max_q7(
+ q7_t * pSrc,
+ uint32_t blockSize,
+ q7_t * pResult,
+ uint32_t * pIndex);
+
+
+/**
+ * @brief Maximum value of a Q15 vector.
+ * @param[in] pSrc points to the input buffer
+ * @param[in] blockSize length of the input vector
+ * @param[out] pResult maximum value returned here
+ * @param[out] pIndex index of maximum value returned here
+ */
+ void arm_max_q15(
+ q15_t * pSrc,
+ uint32_t blockSize,
+ q15_t * pResult,
+ uint32_t * pIndex);
+
+
+/**
+ * @brief Maximum value of a Q31 vector.
+ * @param[in] pSrc points to the input buffer
+ * @param[in] blockSize length of the input vector
+ * @param[out] pResult maximum value returned here
+ * @param[out] pIndex index of maximum value returned here
+ */
+ void arm_max_q31(
+ q31_t * pSrc,
+ uint32_t blockSize,
+ q31_t * pResult,
+ uint32_t * pIndex);
+
+
+/**
+ * @brief Maximum value of a floating-point vector.
+ * @param[in] pSrc points to the input buffer
+ * @param[in] blockSize length of the input vector
+ * @param[out] pResult maximum value returned here
+ * @param[out] pIndex index of maximum value returned here
+ */
+ void arm_max_f32(
+ float32_t * pSrc,
+ uint32_t blockSize,
+ float32_t * pResult,
+ uint32_t * pIndex);
+
+
+ /**
+ * @brief Q15 complex-by-complex multiplication
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] numSamples number of complex samples in each vector
+ */
+ void arm_cmplx_mult_cmplx_q15(
+ q15_t * pSrcA,
+ q15_t * pSrcB,
+ q15_t * pDst,
+ uint32_t numSamples);
+
+
+ /**
+ * @brief Q31 complex-by-complex multiplication
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] numSamples number of complex samples in each vector
+ */
+ void arm_cmplx_mult_cmplx_q31(
+ q31_t * pSrcA,
+ q31_t * pSrcB,
+ q31_t * pDst,
+ uint32_t numSamples);
+
+
+ /**
+ * @brief Floating-point complex-by-complex multiplication
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] numSamples number of complex samples in each vector
+ */
+ void arm_cmplx_mult_cmplx_f32(
+ float32_t * pSrcA,
+ float32_t * pSrcB,
+ float32_t * pDst,
+ uint32_t numSamples);
+
+
+ /**
+ * @brief Converts the elements of the floating-point vector to Q31 vector.
+ * @param[in] pSrc points to the floating-point input vector
+ * @param[out] pDst points to the Q31 output vector
+ * @param[in] blockSize length of the input vector
+ */
+ void arm_float_to_q31(
+ float32_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Converts the elements of the floating-point vector to Q15 vector.
+ * @param[in] pSrc points to the floating-point input vector
+ * @param[out] pDst points to the Q15 output vector
+ * @param[in] blockSize length of the input vector
+ */
+ void arm_float_to_q15(
+ float32_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Converts the elements of the floating-point vector to Q7 vector.
+ * @param[in] pSrc points to the floating-point input vector
+ * @param[out] pDst points to the Q7 output vector
+ * @param[in] blockSize length of the input vector
+ */
+ void arm_float_to_q7(
+ float32_t * pSrc,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Converts the elements of the Q31 vector to Q15 vector.
+ * @param[in] pSrc is input pointer
+ * @param[out] pDst is output pointer
+ * @param[in] blockSize is the number of samples to process
+ */
+ void arm_q31_to_q15(
+ q31_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Converts the elements of the Q31 vector to Q7 vector.
+ * @param[in] pSrc is input pointer
+ * @param[out] pDst is output pointer
+ * @param[in] blockSize is the number of samples to process
+ */
+ void arm_q31_to_q7(
+ q31_t * pSrc,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Converts the elements of the Q15 vector to floating-point vector.
+ * @param[in] pSrc is input pointer
+ * @param[out] pDst is output pointer
+ * @param[in] blockSize is the number of samples to process
+ */
+ void arm_q15_to_float(
+ q15_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Converts the elements of the Q15 vector to Q31 vector.
+ * @param[in] pSrc is input pointer
+ * @param[out] pDst is output pointer
+ * @param[in] blockSize is the number of samples to process
+ */
+ void arm_q15_to_q31(
+ q15_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Converts the elements of the Q15 vector to Q7 vector.
+ * @param[in] pSrc is input pointer
+ * @param[out] pDst is output pointer
+ * @param[in] blockSize is the number of samples to process
+ */
+ void arm_q15_to_q7(
+ q15_t * pSrc,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @ingroup groupInterpolation
+ */
+
+ /**
+ * @defgroup BilinearInterpolate Bilinear Interpolation
+ *
+ * Bilinear interpolation is an extension of linear interpolation applied to a two dimensional grid.
+ * The underlying function <code>f(x, y)</code> is sampled on a regular grid and the interpolation process
+ * determines values between the grid points.
+ * Bilinear interpolation is equivalent to two step linear interpolation, first in the x-dimension and then in the y-dimension.
+ * Bilinear interpolation is often used in image processing to rescale images.
+ * The CMSIS DSP library provides bilinear interpolation functions for Q7, Q15, Q31, and floating-point data types.
+ *
+ * <b>Algorithm</b>
+ * \par
+ * The instance structure used by the bilinear interpolation functions describes a two dimensional data table.
+ * For floating-point, the instance structure is defined as:
+ * <pre>
+ * typedef struct
+ * {
+ * uint16_t numRows;
+ * uint16_t numCols;
+ * float32_t *pData;
+ * } arm_bilinear_interp_instance_f32;
+ * </pre>
+ *
+ * \par
+ * where <code>numRows</code> specifies the number of rows in the table;
+ * <code>numCols</code> specifies the number of columns in the table;
+ * and <code>pData</code> points to an array of size <code>numRows*numCols</code> values.
+ * The data table <code>pTable</code> is organized in row order and the supplied data values fall on integer indexes.
+ * That is, table element (x,y) is located at <code>pTable[x + y*numCols]</code> where x and y are integers.
+ *
+ * \par
+ * Let <code>(x, y)</code> specify the desired interpolation point. Then define:
+ * <pre>
+ * XF = floor(x)
+ * YF = floor(y)
+ * </pre>
+ * \par
+ * The interpolated output point is computed as:
+ * <pre>
+ * f(x, y) = f(XF, YF) * (1-(x-XF)) * (1-(y-YF))
+ * + f(XF+1, YF) * (x-XF)*(1-(y-YF))
+ * + f(XF, YF+1) * (1-(x-XF))*(y-YF)
+ * + f(XF+1, YF+1) * (x-XF)*(y-YF)
+ * </pre>
+ * Note that the coordinates (x, y) contain integer and fractional components.
+ * The integer components specify which portion of the table to use while the
+ * fractional components control the interpolation processor.
+ *
+ * \par
+ * if (x,y) are outside of the table boundary, Bilinear interpolation returns zero output.
+ */
+
+ /**
+ * @addtogroup BilinearInterpolate
+ * @{
+ */
+
+
+ /**
+ *
+ * @brief Floating-point bilinear interpolation.
+ * @param[in,out] S points to an instance of the interpolation structure.
+ * @param[in] X interpolation coordinate.
+ * @param[in] Y interpolation coordinate.
+ * @return out interpolated value.
+ */
+ static __INLINE float32_t arm_bilinear_interp_f32(
+ const arm_bilinear_interp_instance_f32 * S,
+ float32_t X,
+ float32_t Y)
+ {
+ float32_t out;
+ float32_t f00, f01, f10, f11;
+ float32_t *pData = S->pData;
+ int32_t xIndex, yIndex, index;
+ float32_t xdiff, ydiff;
+ float32_t b1, b2, b3, b4;
+
+ xIndex = (int32_t) X;
+ yIndex = (int32_t) Y;
+
+ /* Care taken for table outside boundary */
+ /* Returns zero output when values are outside table boundary */
+ if(xIndex < 0 || xIndex > (S->numRows - 1) || yIndex < 0 || yIndex > (S->numCols - 1))
+ {
+ return (0);
+ }
+
+ /* Calculation of index for two nearest points in X-direction */
+ index = (xIndex - 1) + (yIndex - 1) * S->numCols;
+
+
+ /* Read two nearest points in X-direction */
+ f00 = pData[index];
+ f01 = pData[index + 1];
+
+ /* Calculation of index for two nearest points in Y-direction */
+ index = (xIndex - 1) + (yIndex) * S->numCols;
+
+
+ /* Read two nearest points in Y-direction */
+ f10 = pData[index];
+ f11 = pData[index + 1];
+
+ /* Calculation of intermediate values */
+ b1 = f00;
+ b2 = f01 - f00;
+ b3 = f10 - f00;
+ b4 = f00 - f01 - f10 + f11;
+
+ /* Calculation of fractional part in X */
+ xdiff = X - xIndex;
+
+ /* Calculation of fractional part in Y */
+ ydiff = Y - yIndex;
+
+ /* Calculation of bi-linear interpolated output */
+ out = b1 + b2 * xdiff + b3 * ydiff + b4 * xdiff * ydiff;
+
+ /* return to application */
+ return (out);
+ }
+
+
+ /**
+ *
+ * @brief Q31 bilinear interpolation.
+ * @param[in,out] S points to an instance of the interpolation structure.
+ * @param[in] X interpolation coordinate in 12.20 format.
+ * @param[in] Y interpolation coordinate in 12.20 format.
+ * @return out interpolated value.
+ */
+ static __INLINE q31_t arm_bilinear_interp_q31(
+ arm_bilinear_interp_instance_q31 * S,
+ q31_t X,
+ q31_t Y)
+ {
+ q31_t out; /* Temporary output */
+ q31_t acc = 0; /* output */
+ q31_t xfract, yfract; /* X, Y fractional parts */
+ q31_t x1, x2, y1, y2; /* Nearest output values */
+ int32_t rI, cI; /* Row and column indices */
+ q31_t *pYData = S->pData; /* pointer to output table values */
+ uint32_t nCols = S->numCols; /* num of rows */
+
+ /* Input is in 12.20 format */
+ /* 12 bits for the table index */
+ /* Index value calculation */
+ rI = ((X & (q31_t)0xFFF00000) >> 20);
+
+ /* Input is in 12.20 format */
+ /* 12 bits for the table index */
+ /* Index value calculation */
+ cI = ((Y & (q31_t)0xFFF00000) >> 20);
+
+ /* Care taken for table outside boundary */
+ /* Returns zero output when values are outside table boundary */
+ if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1))
+ {
+ return (0);
+ }
+
+ /* 20 bits for the fractional part */
+ /* shift left xfract by 11 to keep 1.31 format */
+ xfract = (X & 0x000FFFFF) << 11u;
+
+ /* Read two nearest output values from the index */
+ x1 = pYData[(rI) + (int32_t)nCols * (cI) ];
+ x2 = pYData[(rI) + (int32_t)nCols * (cI) + 1];
+
+ /* 20 bits for the fractional part */
+ /* shift left yfract by 11 to keep 1.31 format */
+ yfract = (Y & 0x000FFFFF) << 11u;
+
+ /* Read two nearest output values from the index */
+ y1 = pYData[(rI) + (int32_t)nCols * (cI + 1) ];
+ y2 = pYData[(rI) + (int32_t)nCols * (cI + 1) + 1];
+
+ /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 3.29(q29) format */
+ out = ((q31_t) (((q63_t) x1 * (0x7FFFFFFF - xfract)) >> 32));
+ acc = ((q31_t) (((q63_t) out * (0x7FFFFFFF - yfract)) >> 32));
+
+ /* x2 * (xfract) * (1-yfract) in 3.29(q29) and adding to acc */
+ out = ((q31_t) ((q63_t) x2 * (0x7FFFFFFF - yfract) >> 32));
+ acc += ((q31_t) ((q63_t) out * (xfract) >> 32));
+
+ /* y1 * (1 - xfract) * (yfract) in 3.29(q29) and adding to acc */
+ out = ((q31_t) ((q63_t) y1 * (0x7FFFFFFF - xfract) >> 32));
+ acc += ((q31_t) ((q63_t) out * (yfract) >> 32));
+
+ /* y2 * (xfract) * (yfract) in 3.29(q29) and adding to acc */
+ out = ((q31_t) ((q63_t) y2 * (xfract) >> 32));
+ acc += ((q31_t) ((q63_t) out * (yfract) >> 32));
+
+ /* Convert acc to 1.31(q31) format */
+ return ((q31_t)(acc << 2));
+ }
+
+
+ /**
+ * @brief Q15 bilinear interpolation.
+ * @param[in,out] S points to an instance of the interpolation structure.
+ * @param[in] X interpolation coordinate in 12.20 format.
+ * @param[in] Y interpolation coordinate in 12.20 format.
+ * @return out interpolated value.
+ */
+ static __INLINE q15_t arm_bilinear_interp_q15(
+ arm_bilinear_interp_instance_q15 * S,
+ q31_t X,
+ q31_t Y)
+ {
+ q63_t acc = 0; /* output */
+ q31_t out; /* Temporary output */
+ q15_t x1, x2, y1, y2; /* Nearest output values */
+ q31_t xfract, yfract; /* X, Y fractional parts */
+ int32_t rI, cI; /* Row and column indices */
+ q15_t *pYData = S->pData; /* pointer to output table values */
+ uint32_t nCols = S->numCols; /* num of rows */
+
+ /* Input is in 12.20 format */
+ /* 12 bits for the table index */
+ /* Index value calculation */
+ rI = ((X & (q31_t)0xFFF00000) >> 20);
+
+ /* Input is in 12.20 format */
+ /* 12 bits for the table index */
+ /* Index value calculation */
+ cI = ((Y & (q31_t)0xFFF00000) >> 20);
+
+ /* Care taken for table outside boundary */
+ /* Returns zero output when values are outside table boundary */
+ if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1))
+ {
+ return (0);
+ }
+
+ /* 20 bits for the fractional part */
+ /* xfract should be in 12.20 format */
+ xfract = (X & 0x000FFFFF);
+
+ /* Read two nearest output values from the index */
+ x1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) ];
+ x2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) + 1];
+
+ /* 20 bits for the fractional part */
+ /* yfract should be in 12.20 format */
+ yfract = (Y & 0x000FFFFF);
+
+ /* Read two nearest output values from the index */
+ y1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) ];
+ y2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) + 1];
+
+ /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 13.51 format */
+
+ /* x1 is in 1.15(q15), xfract in 12.20 format and out is in 13.35 format */
+ /* convert 13.35 to 13.31 by right shifting and out is in 1.31 */
+ out = (q31_t) (((q63_t) x1 * (0xFFFFF - xfract)) >> 4u);
+ acc = ((q63_t) out * (0xFFFFF - yfract));
+
+ /* x2 * (xfract) * (1-yfract) in 1.51 and adding to acc */
+ out = (q31_t) (((q63_t) x2 * (0xFFFFF - yfract)) >> 4u);
+ acc += ((q63_t) out * (xfract));
+
+ /* y1 * (1 - xfract) * (yfract) in 1.51 and adding to acc */
+ out = (q31_t) (((q63_t) y1 * (0xFFFFF - xfract)) >> 4u);
+ acc += ((q63_t) out * (yfract));
+
+ /* y2 * (xfract) * (yfract) in 1.51 and adding to acc */
+ out = (q31_t) (((q63_t) y2 * (xfract)) >> 4u);
+ acc += ((q63_t) out * (yfract));
+
+ /* acc is in 13.51 format and down shift acc by 36 times */
+ /* Convert out to 1.15 format */
+ return ((q15_t)(acc >> 36));
+ }
+
+
+ /**
+ * @brief Q7 bilinear interpolation.
+ * @param[in,out] S points to an instance of the interpolation structure.
+ * @param[in] X interpolation coordinate in 12.20 format.
+ * @param[in] Y interpolation coordinate in 12.20 format.
+ * @return out interpolated value.
+ */
+ static __INLINE q7_t arm_bilinear_interp_q7(
+ arm_bilinear_interp_instance_q7 * S,
+ q31_t X,
+ q31_t Y)
+ {
+ q63_t acc = 0; /* output */
+ q31_t out; /* Temporary output */
+ q31_t xfract, yfract; /* X, Y fractional parts */
+ q7_t x1, x2, y1, y2; /* Nearest output values */
+ int32_t rI, cI; /* Row and column indices */
+ q7_t *pYData = S->pData; /* pointer to output table values */
+ uint32_t nCols = S->numCols; /* num of rows */
+
+ /* Input is in 12.20 format */
+ /* 12 bits for the table index */
+ /* Index value calculation */
+ rI = ((X & (q31_t)0xFFF00000) >> 20);
+
+ /* Input is in 12.20 format */
+ /* 12 bits for the table index */
+ /* Index value calculation */
+ cI = ((Y & (q31_t)0xFFF00000) >> 20);
+
+ /* Care taken for table outside boundary */
+ /* Returns zero output when values are outside table boundary */
+ if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1))
+ {
+ return (0);
+ }
+
+ /* 20 bits for the fractional part */
+ /* xfract should be in 12.20 format */
+ xfract = (X & (q31_t)0x000FFFFF);
+
+ /* Read two nearest output values from the index */
+ x1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) ];
+ x2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) + 1];
+
+ /* 20 bits for the fractional part */
+ /* yfract should be in 12.20 format */
+ yfract = (Y & (q31_t)0x000FFFFF);
+
+ /* Read two nearest output values from the index */
+ y1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) ];
+ y2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) + 1];
+
+ /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 16.47 format */
+ out = ((x1 * (0xFFFFF - xfract)));
+ acc = (((q63_t) out * (0xFFFFF - yfract)));
+
+ /* x2 * (xfract) * (1-yfract) in 2.22 and adding to acc */
+ out = ((x2 * (0xFFFFF - yfract)));
+ acc += (((q63_t) out * (xfract)));
+
+ /* y1 * (1 - xfract) * (yfract) in 2.22 and adding to acc */
+ out = ((y1 * (0xFFFFF - xfract)));
+ acc += (((q63_t) out * (yfract)));
+
+ /* y2 * (xfract) * (yfract) in 2.22 and adding to acc */
+ out = ((y2 * (yfract)));
+ acc += (((q63_t) out * (xfract)));
+
+ /* acc in 16.47 format and down shift by 40 to convert to 1.7 format */
+ return ((q7_t)(acc >> 40));
+ }
+
+ /**
+ * @} end of BilinearInterpolate group
+ */
+
+
+/* SMMLAR */
+#define multAcc_32x32_keep32_R(a, x, y) \
+ a = (q31_t) (((((q63_t) a) << 32) + ((q63_t) x * y) + 0x80000000LL ) >> 32)
+
+/* SMMLSR */
+#define multSub_32x32_keep32_R(a, x, y) \
+ a = (q31_t) (((((q63_t) a) << 32) - ((q63_t) x * y) + 0x80000000LL ) >> 32)
+
+/* SMMULR */
+#define mult_32x32_keep32_R(a, x, y) \
+ a = (q31_t) (((q63_t) x * y + 0x80000000LL ) >> 32)
+
+/* SMMLA */
+#define multAcc_32x32_keep32(a, x, y) \
+ a += (q31_t) (((q63_t) x * y) >> 32)
+
+/* SMMLS */
+#define multSub_32x32_keep32(a, x, y) \
+ a -= (q31_t) (((q63_t) x * y) >> 32)
+
+/* SMMUL */
+#define mult_32x32_keep32(a, x, y) \
+ a = (q31_t) (((q63_t) x * y ) >> 32)
+
+
+#if defined ( __CC_ARM )
+ /* Enter low optimization region - place directly above function definition */
+ #if defined( ARM_MATH_CM4 ) || defined( ARM_MATH_CM7)
+ #define LOW_OPTIMIZATION_ENTER \
+ _Pragma ("push") \
+ _Pragma ("O1")
+ #else
+ #define LOW_OPTIMIZATION_ENTER
+ #endif
+
+ /* Exit low optimization region - place directly after end of function definition */
+ #if defined( ARM_MATH_CM4 ) || defined( ARM_MATH_CM7)
+ #define LOW_OPTIMIZATION_EXIT \
+ _Pragma ("pop")
+ #else
+ #define LOW_OPTIMIZATION_EXIT
+ #endif
+
+ /* Enter low optimization region - place directly above function definition */
+ #define IAR_ONLY_LOW_OPTIMIZATION_ENTER
+
+ /* Exit low optimization region - place directly after end of function definition */
+ #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
+
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #define LOW_OPTIMIZATION_ENTER
+ #define LOW_OPTIMIZATION_EXIT
+ #define IAR_ONLY_LOW_OPTIMIZATION_ENTER
+ #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
+
+#elif defined(__GNUC__)
+ #define LOW_OPTIMIZATION_ENTER __attribute__(( optimize("-O1") ))
+ #define LOW_OPTIMIZATION_EXIT
+ #define IAR_ONLY_LOW_OPTIMIZATION_ENTER
+ #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
+
+#elif defined(__ICCARM__)
+ /* Enter low optimization region - place directly above function definition */
+ #if defined( ARM_MATH_CM4 ) || defined( ARM_MATH_CM7)
+ #define LOW_OPTIMIZATION_ENTER \
+ _Pragma ("optimize=low")
+ #else
+ #define LOW_OPTIMIZATION_ENTER
+ #endif
+
+ /* Exit low optimization region - place directly after end of function definition */
+ #define LOW_OPTIMIZATION_EXIT
+
+ /* Enter low optimization region - place directly above function definition */
+ #if defined( ARM_MATH_CM4 ) || defined( ARM_MATH_CM7)
+ #define IAR_ONLY_LOW_OPTIMIZATION_ENTER \
+ _Pragma ("optimize=low")
+ #else
+ #define IAR_ONLY_LOW_OPTIMIZATION_ENTER
+ #endif
+
+ /* Exit low optimization region - place directly after end of function definition */
+ #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
+
+#elif defined(__CSMC__)
+ #define LOW_OPTIMIZATION_ENTER
+ #define LOW_OPTIMIZATION_EXIT
+ #define IAR_ONLY_LOW_OPTIMIZATION_ENTER
+ #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
+
+#elif defined(__TASKING__)
+ #define LOW_OPTIMIZATION_ENTER
+ #define LOW_OPTIMIZATION_EXIT
+ #define IAR_ONLY_LOW_OPTIMIZATION_ENTER
+ #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
+
+#endif
+
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#if defined ( __GNUC__ )
+#pragma GCC diagnostic pop
+#endif
+
+#endif /* _ARM_MATH_H */
+
+/**
+ *
+ * End of file.
+ */
diff --git a/Include/cmsis_armcc.h b/Include/cmsis_armcc.h
new file mode 100644
index 0000000..f2bb66a
--- /dev/null
+++ b/Include/cmsis_armcc.h
@@ -0,0 +1,734 @@
+/**************************************************************************//**
+ * @file cmsis_armcc.h
+ * @brief CMSIS Cortex-M Core Function/Instruction Header File
+ * @version V4.30
+ * @date 20. October 2015
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2015 ARM LIMITED
+
+ All rights reserved.
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+ - Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ - Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+ - Neither the name of ARM nor the names of its contributors may be used
+ to endorse or promote products derived from this software without
+ specific prior written permission.
+ *
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ POSSIBILITY OF SUCH DAMAGE.
+ ---------------------------------------------------------------------------*/
+
+
+#ifndef __CMSIS_ARMCC_H
+#define __CMSIS_ARMCC_H
+
+
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677)
+ #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
+#endif
+
+/* ########################### Core Function Access ########################### */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+ @{
+ */
+
+/* intrinsic void __enable_irq(); */
+/* intrinsic void __disable_irq(); */
+
+/**
+ \brief Get Control Register
+ \details Returns the content of the Control Register.
+ \return Control Register value
+ */
+__STATIC_INLINE uint32_t __get_CONTROL(void)
+{
+ register uint32_t __regControl __ASM("control");
+ return(__regControl);
+}
+
+
+/**
+ \brief Set Control Register
+ \details Writes the given value to the Control Register.
+ \param [in] control Control Register value to set
+ */
+__STATIC_INLINE void __set_CONTROL(uint32_t control)
+{
+ register uint32_t __regControl __ASM("control");
+ __regControl = control;
+}
+
+
+/**
+ \brief Get IPSR Register
+ \details Returns the content of the IPSR Register.
+ \return IPSR Register value
+ */
+__STATIC_INLINE uint32_t __get_IPSR(void)
+{
+ register uint32_t __regIPSR __ASM("ipsr");
+ return(__regIPSR);
+}
+
+
+/**
+ \brief Get APSR Register
+ \details Returns the content of the APSR Register.
+ \return APSR Register value
+ */
+__STATIC_INLINE uint32_t __get_APSR(void)
+{
+ register uint32_t __regAPSR __ASM("apsr");
+ return(__regAPSR);
+}
+
+
+/**
+ \brief Get xPSR Register
+ \details Returns the content of the xPSR Register.
+ \return xPSR Register value
+ */
+__STATIC_INLINE uint32_t __get_xPSR(void)
+{
+ register uint32_t __regXPSR __ASM("xpsr");
+ return(__regXPSR);
+}
+
+
+/**
+ \brief Get Process Stack Pointer
+ \details Returns the current value of the Process Stack Pointer (PSP).
+ \return PSP Register value
+ */
+__STATIC_INLINE uint32_t __get_PSP(void)
+{
+ register uint32_t __regProcessStackPointer __ASM("psp");
+ return(__regProcessStackPointer);
+}
+
+
+/**
+ \brief Set Process Stack Pointer
+ \details Assigns the given value to the Process Stack Pointer (PSP).
+ \param [in] topOfProcStack Process Stack Pointer value to set
+ */
+__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
+{
+ register uint32_t __regProcessStackPointer __ASM("psp");
+ __regProcessStackPointer = topOfProcStack;
+}
+
+
+/**
+ \brief Get Main Stack Pointer
+ \details Returns the current value of the Main Stack Pointer (MSP).
+ \return MSP Register value
+ */
+__STATIC_INLINE uint32_t __get_MSP(void)
+{
+ register uint32_t __regMainStackPointer __ASM("msp");
+ return(__regMainStackPointer);
+}
+
+
+/**
+ \brief Set Main Stack Pointer
+ \details Assigns the given value to the Main Stack Pointer (MSP).
+ \param [in] topOfMainStack Main Stack Pointer value to set
+ */
+__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
+{
+ register uint32_t __regMainStackPointer __ASM("msp");
+ __regMainStackPointer = topOfMainStack;
+}
+
+
+/**
+ \brief Get Priority Mask
+ \details Returns the current state of the priority mask bit from the Priority Mask Register.
+ \return Priority Mask value
+ */
+__STATIC_INLINE uint32_t __get_PRIMASK(void)
+{
+ register uint32_t __regPriMask __ASM("primask");
+ return(__regPriMask);
+}
+
+
+/**
+ \brief Set Priority Mask
+ \details Assigns the given value to the Priority Mask Register.
+ \param [in] priMask Priority Mask
+ */
+__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
+{
+ register uint32_t __regPriMask __ASM("primask");
+ __regPriMask = (priMask);
+}
+
+
+#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U)
+
+/**
+ \brief Enable FIQ
+ \details Enables FIQ interrupts by clearing the F-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+#define __enable_fault_irq __enable_fiq
+
+
+/**
+ \brief Disable FIQ
+ \details Disables FIQ interrupts by setting the F-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+#define __disable_fault_irq __disable_fiq
+
+
+/**
+ \brief Get Base Priority
+ \details Returns the current value of the Base Priority register.
+ \return Base Priority register value
+ */
+__STATIC_INLINE uint32_t __get_BASEPRI(void)
+{
+ register uint32_t __regBasePri __ASM("basepri");
+ return(__regBasePri);
+}
+
+
+/**
+ \brief Set Base Priority
+ \details Assigns the given value to the Base Priority register.
+ \param [in] basePri Base Priority value to set
+ */
+__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
+{
+ register uint32_t __regBasePri __ASM("basepri");
+ __regBasePri = (basePri & 0xFFU);
+}
+
+
+/**
+ \brief Set Base Priority with condition
+ \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
+ or the new value increases the BASEPRI priority level.
+ \param [in] basePri Base Priority value to set
+ */
+__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri)
+{
+ register uint32_t __regBasePriMax __ASM("basepri_max");
+ __regBasePriMax = (basePri & 0xFFU);
+}
+
+
+/**
+ \brief Get Fault Mask
+ \details Returns the current value of the Fault Mask register.
+ \return Fault Mask register value
+ */
+__STATIC_INLINE uint32_t __get_FAULTMASK(void)
+{
+ register uint32_t __regFaultMask __ASM("faultmask");
+ return(__regFaultMask);
+}
+
+
+/**
+ \brief Set Fault Mask
+ \details Assigns the given value to the Fault Mask register.
+ \param [in] faultMask Fault Mask value to set
+ */
+__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+ register uint32_t __regFaultMask __ASM("faultmask");
+ __regFaultMask = (faultMask & (uint32_t)1);
+}
+
+#endif /* (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) */
+
+
+#if (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U)
+
+/**
+ \brief Get FPSCR
+ \details Returns the current value of the Floating Point Status/Control register.
+ \return Floating Point Status/Control register value
+ */
+__STATIC_INLINE uint32_t __get_FPSCR(void)
+{
+#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U)
+ register uint32_t __regfpscr __ASM("fpscr");
+ return(__regfpscr);
+#else
+ return(0U);
+#endif
+}
+
+
+/**
+ \brief Set FPSCR
+ \details Assigns the given value to the Floating Point Status/Control register.
+ \param [in] fpscr Floating Point Status/Control value to set
+ */
+__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
+{
+#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U)
+ register uint32_t __regfpscr __ASM("fpscr");
+ __regfpscr = (fpscr);
+#endif
+}
+
+#endif /* (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U) */
+
+
+
+/*@} end of CMSIS_Core_RegAccFunctions */
+
+
+/* ########################## Core Instruction Access ######################### */
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
+ Access to dedicated instructions
+ @{
+*/
+
+/**
+ \brief No Operation
+ \details No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+#define __NOP __nop
+
+
+/**
+ \brief Wait For Interrupt
+ \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
+ */
+#define __WFI __wfi
+
+
+/**
+ \brief Wait For Event
+ \details Wait For Event is a hint instruction that permits the processor to enter
+ a low-power state until one of a number of events occurs.
+ */
+#define __WFE __wfe
+
+
+/**
+ \brief Send Event
+ \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+#define __SEV __sev
+
+
+/**
+ \brief Instruction Synchronization Barrier
+ \details Instruction Synchronization Barrier flushes the pipeline in the processor,
+ so that all instructions following the ISB are fetched from cache or memory,
+ after the instruction has been completed.
+ */
+#define __ISB() do {\
+ __schedule_barrier();\
+ __isb(0xF);\
+ __schedule_barrier();\
+ } while (0U)
+
+/**
+ \brief Data Synchronization Barrier
+ \details Acts as a special kind of Data Memory Barrier.
+ It completes when all explicit memory accesses before this instruction complete.
+ */
+#define __DSB() do {\
+ __schedule_barrier();\
+ __dsb(0xF);\
+ __schedule_barrier();\
+ } while (0U)
+
+/**
+ \brief Data Memory Barrier
+ \details Ensures the apparent order of the explicit memory operations before
+ and after the instruction, without ensuring their completion.
+ */
+#define __DMB() do {\
+ __schedule_barrier();\
+ __dmb(0xF);\
+ __schedule_barrier();\
+ } while (0U)
+
+/**
+ \brief Reverse byte order (32 bit)
+ \details Reverses the byte order in integer value.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#define __REV __rev
+
+
+/**
+ \brief Reverse byte order (16 bit)
+ \details Reverses the byte order in two unsigned short values.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
+{
+ rev16 r0, r0
+ bx lr
+}
+#endif
+
+/**
+ \brief Reverse byte order in signed short value
+ \details Reverses the byte order in a signed short value with sign extension to integer.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value)
+{
+ revsh r0, r0
+ bx lr
+}
+#endif
+
+
+/**
+ \brief Rotate Right in unsigned value (32 bit)
+ \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+ \param [in] value Value to rotate
+ \param [in] value Number of Bits to rotate
+ \return Rotated value
+ */
+#define __ROR __ror
+
+
+/**
+ \brief Breakpoint
+ \details Causes the processor to enter Debug state.
+ Debug tools can use this to investigate system state when the instruction at a particular address is reached.
+ \param [in] value is ignored by the processor.
+ If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value) __breakpoint(value)
+
+
+/**
+ \brief Reverse bit order of value
+ \details Reverses the bit order of the given value.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U)
+ #define __RBIT __rbit
+#else
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
+{
+ uint32_t result;
+ int32_t s = 4 /*sizeof(v)*/ * 8 - 1; /* extra shift needed at end */
+
+ result = value; /* r will be reversed bits of v; first get LSB of v */
+ for (value >>= 1U; value; value >>= 1U)
+ {
+ result <<= 1U;
+ result |= value & 1U;
+ s--;
+ }
+ result <<= s; /* shift when v's highest bits are zero */
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Count leading zeros
+ \details Counts the number of leading zeros of a data value.
+ \param [in] value Value to count the leading zeros
+ \return number of leading zeros in value
+ */
+#define __CLZ __clz
+
+
+#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U)
+
+/**
+ \brief LDR Exclusive (8 bit)
+ \details Executes a exclusive LDR instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+ #define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr))
+#else
+ #define __LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr)) _Pragma("pop")
+#endif
+
+
+/**
+ \brief LDR Exclusive (16 bit)
+ \details Executes a exclusive LDR instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+ #define __LDREXH(ptr) ((uint16_t) __ldrex(ptr))
+#else
+ #define __LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr)) _Pragma("pop")
+#endif
+
+
+/**
+ \brief LDR Exclusive (32 bit)
+ \details Executes a exclusive LDR instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+ #define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr))
+#else
+ #define __LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr)) _Pragma("pop")
+#endif
+
+
+/**
+ \brief STR Exclusive (8 bit)
+ \details Executes a exclusive STR instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+ #define __STREXB(value, ptr) __strex(value, ptr)
+#else
+ #define __STREXB(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
+#endif
+
+
+/**
+ \brief STR Exclusive (16 bit)
+ \details Executes a exclusive STR instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+ #define __STREXH(value, ptr) __strex(value, ptr)
+#else
+ #define __STREXH(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
+#endif
+
+
+/**
+ \brief STR Exclusive (32 bit)
+ \details Executes a exclusive STR instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+ #define __STREXW(value, ptr) __strex(value, ptr)
+#else
+ #define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
+#endif
+
+
+/**
+ \brief Remove the exclusive lock
+ \details Removes the exclusive lock which is created by LDREX.
+ */
+#define __CLREX __clrex
+
+
+/**
+ \brief Signed Saturate
+ \details Saturates a signed value.
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (1..32)
+ \return Saturated value
+ */
+#define __SSAT __ssat
+
+
+/**
+ \brief Unsigned Saturate
+ \details Saturates an unsigned value.
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (0..31)
+ \return Saturated value
+ */
+#define __USAT __usat
+
+
+/**
+ \brief Rotate Right with Extend (32 bit)
+ \details Moves each bit of a bitstring right by one bit.
+ The carry input is shifted in at the left end of the bitstring.
+ \param [in] value Value to rotate
+ \return Rotated value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value)
+{
+ rrx r0, r0
+ bx lr
+}
+#endif
+
+
+/**
+ \brief LDRT Unprivileged (8 bit)
+ \details Executes a Unprivileged LDRT instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+#define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr))
+
+
+/**
+ \brief LDRT Unprivileged (16 bit)
+ \details Executes a Unprivileged LDRT instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+#define __LDRHT(ptr) ((uint16_t) __ldrt(ptr))
+
+
+/**
+ \brief LDRT Unprivileged (32 bit)
+ \details Executes a Unprivileged LDRT instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+#define __LDRT(ptr) ((uint32_t ) __ldrt(ptr))
+
+
+/**
+ \brief STRT Unprivileged (8 bit)
+ \details Executes a Unprivileged STRT instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+#define __STRBT(value, ptr) __strt(value, ptr)
+
+
+/**
+ \brief STRT Unprivileged (16 bit)
+ \details Executes a Unprivileged STRT instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+#define __STRHT(value, ptr) __strt(value, ptr)
+
+
+/**
+ \brief STRT Unprivileged (32 bit)
+ \details Executes a Unprivileged STRT instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+#define __STRT(value, ptr) __strt(value, ptr)
+
+#endif /* (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) */
+
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
+
+
+/* ################### Compiler specific Intrinsics ########################### */
+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
+ Access to dedicated SIMD instructions
+ @{
+*/
+
+#if (__CORTEX_M >= 0x04U) /* only for Cortex-M4 and above */
+
+#define __SADD8 __sadd8
+#define __QADD8 __qadd8
+#define __SHADD8 __shadd8
+#define __UADD8 __uadd8
+#define __UQADD8 __uqadd8
+#define __UHADD8 __uhadd8
+#define __SSUB8 __ssub8
+#define __QSUB8 __qsub8
+#define __SHSUB8 __shsub8
+#define __USUB8 __usub8
+#define __UQSUB8 __uqsub8
+#define __UHSUB8 __uhsub8
+#define __SADD16 __sadd16
+#define __QADD16 __qadd16
+#define __SHADD16 __shadd16
+#define __UADD16 __uadd16
+#define __UQADD16 __uqadd16
+#define __UHADD16 __uhadd16
+#define __SSUB16 __ssub16
+#define __QSUB16 __qsub16
+#define __SHSUB16 __shsub16
+#define __USUB16 __usub16
+#define __UQSUB16 __uqsub16
+#define __UHSUB16 __uhsub16
+#define __SASX __sasx
+#define __QASX __qasx
+#define __SHASX __shasx
+#define __UASX __uasx
+#define __UQASX __uqasx
+#define __UHASX __uhasx
+#define __SSAX __ssax
+#define __QSAX __qsax
+#define __SHSAX __shsax
+#define __USAX __usax
+#define __UQSAX __uqsax
+#define __UHSAX __uhsax
+#define __USAD8 __usad8
+#define __USADA8 __usada8
+#define __SSAT16 __ssat16
+#define __USAT16 __usat16
+#define __UXTB16 __uxtb16
+#define __UXTAB16 __uxtab16
+#define __SXTB16 __sxtb16
+#define __SXTAB16 __sxtab16
+#define __SMUAD __smuad
+#define __SMUADX __smuadx
+#define __SMLAD __smlad
+#define __SMLADX __smladx
+#define __SMLALD __smlald
+#define __SMLALDX __smlaldx
+#define __SMUSD __smusd
+#define __SMUSDX __smusdx
+#define __SMLSD __smlsd
+#define __SMLSDX __smlsdx
+#define __SMLSLD __smlsld
+#define __SMLSLDX __smlsldx
+#define __SEL __sel
+#define __QADD __qadd
+#define __QSUB __qsub
+
+#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \
+ ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
+
+#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \
+ ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
+
+#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \
+ ((int64_t)(ARG3) << 32U) ) >> 32U))
+
+#endif /* (__CORTEX_M >= 0x04) */
+/*@} end of group CMSIS_SIMD_intrinsics */
+
+
+#endif /* __CMSIS_ARMCC_H */
diff --git a/Include/cmsis_armcc_V6.h b/Include/cmsis_armcc_V6.h
new file mode 100644
index 0000000..d714e9b
--- /dev/null
+++ b/Include/cmsis_armcc_V6.h
@@ -0,0 +1,1800 @@
+/**************************************************************************//**
+ * @file cmsis_armcc_V6.h
+ * @brief CMSIS Cortex-M Core Function/Instruction Header File
+ * @version V4.30
+ * @date 20. October 2015
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2015 ARM LIMITED
+
+ All rights reserved.
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+ - Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ - Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+ - Neither the name of ARM nor the names of its contributors may be used
+ to endorse or promote products derived from this software without
+ specific prior written permission.
+ *
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ POSSIBILITY OF SUCH DAMAGE.
+ ---------------------------------------------------------------------------*/
+
+
+#ifndef __CMSIS_ARMCC_V6_H
+#define __CMSIS_ARMCC_V6_H
+
+
+/* ########################### Core Function Access ########################### */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+ @{
+ */
+
+/**
+ \brief Enable IRQ Interrupts
+ \details Enables IRQ interrupts by clearing the I-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __enable_irq(void)
+{
+ __ASM volatile ("cpsie i" : : : "memory");
+}
+
+
+/**
+ \brief Disable IRQ Interrupts
+ \details Disables IRQ interrupts by setting the I-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __disable_irq(void)
+{
+ __ASM volatile ("cpsid i" : : : "memory");
+}
+
+
+/**
+ \brief Get Control Register
+ \details Returns the content of the Control Register.
+ \return Control Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_CONTROL(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, control" : "=r" (result) );
+ return(result);
+}
+
+
+#if (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief Get Control Register (non-secure)
+ \details Returns the content of the non-secure Control Register when in secure mode.
+ \return non-secure Control Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_CONTROL_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, control_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Control Register
+ \details Writes the given value to the Control Register.
+ \param [in] control Control Register value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __set_CONTROL(uint32_t control)
+{
+ __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
+}
+
+
+#if (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief Set Control Register (non-secure)
+ \details Writes the given value to the non-secure Control Register when in secure state.
+ \param [in] control Control Register value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_CONTROL_NS(uint32_t control)
+{
+ __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory");
+}
+#endif
+
+
+/**
+ \brief Get IPSR Register
+ \details Returns the content of the IPSR Register.
+ \return IPSR Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_IPSR(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
+ return(result);
+}
+
+
+#if (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief Get IPSR Register (non-secure)
+ \details Returns the content of the non-secure IPSR Register when in secure state.
+ \return IPSR Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_IPSR_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, ipsr_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Get APSR Register
+ \details Returns the content of the APSR Register.
+ \return APSR Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_APSR(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, apsr" : "=r" (result) );
+ return(result);
+}
+
+
+#if (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief Get APSR Register (non-secure)
+ \details Returns the content of the non-secure APSR Register when in secure state.
+ \return APSR Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_APSR_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, apsr_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Get xPSR Register
+ \details Returns the content of the xPSR Register.
+ \return xPSR Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_xPSR(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
+ return(result);
+}
+
+
+#if (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief Get xPSR Register (non-secure)
+ \details Returns the content of the non-secure xPSR Register when in secure state.
+ \return xPSR Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_xPSR_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, xpsr_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Get Process Stack Pointer
+ \details Returns the current value of the Process Stack Pointer (PSP).
+ \return PSP Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PSP(void)
+{
+ register uint32_t result;
+
+ __ASM volatile ("MRS %0, psp" : "=r" (result) );
+ return(result);
+}
+
+
+#if (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief Get Process Stack Pointer (non-secure)
+ \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state.
+ \return PSP Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PSP_NS(void)
+{
+ register uint32_t result;
+
+ __ASM volatile ("MRS %0, psp_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Process Stack Pointer
+ \details Assigns the given value to the Process Stack Pointer (PSP).
+ \param [in] topOfProcStack Process Stack Pointer value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
+{
+ __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : "sp");
+}
+
+
+#if (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief Set Process Stack Pointer (non-secure)
+ \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state.
+ \param [in] topOfProcStack Process Stack Pointer value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack)
+{
+ __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : "sp");
+}
+#endif
+
+
+/**
+ \brief Get Main Stack Pointer
+ \details Returns the current value of the Main Stack Pointer (MSP).
+ \return MSP Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_MSP(void)
+{
+ register uint32_t result;
+
+ __ASM volatile ("MRS %0, msp" : "=r" (result) );
+ return(result);
+}
+
+
+#if (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief Get Main Stack Pointer (non-secure)
+ \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state.
+ \return MSP Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_MSP_NS(void)
+{
+ register uint32_t result;
+
+ __ASM volatile ("MRS %0, msp_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Main Stack Pointer
+ \details Assigns the given value to the Main Stack Pointer (MSP).
+ \param [in] topOfMainStack Main Stack Pointer value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
+{
+ __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : "sp");
+}
+
+
+#if (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief Set Main Stack Pointer (non-secure)
+ \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state.
+ \param [in] topOfMainStack Main Stack Pointer value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack)
+{
+ __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : "sp");
+}
+#endif
+
+
+/**
+ \brief Get Priority Mask
+ \details Returns the current state of the priority mask bit from the Priority Mask Register.
+ \return Priority Mask value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PRIMASK(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, primask" : "=r" (result) );
+ return(result);
+}
+
+
+#if (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief Get Priority Mask (non-secure)
+ \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state.
+ \return Priority Mask value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PRIMASK_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, primask_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Priority Mask
+ \details Assigns the given value to the Priority Mask Register.
+ \param [in] priMask Priority Mask
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
+{
+ __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
+}
+
+
+#if (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief Set Priority Mask (non-secure)
+ \details Assigns the given value to the non-secure Priority Mask Register when in secure state.
+ \param [in] priMask Priority Mask
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PRIMASK_NS(uint32_t priMask)
+{
+ __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory");
+}
+#endif
+
+
+#if ((__ARM_ARCH_7M__ == 1U) || (__ARM_ARCH_7EM__ == 1U) || (__ARM_ARCH_8M__ == 1U)) /* ToDo: ARMCC_V6: check if this is ok for cortex >=3 */
+
+/**
+ \brief Enable FIQ
+ \details Enables FIQ interrupts by clearing the F-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __enable_fault_irq(void)
+{
+ __ASM volatile ("cpsie f" : : : "memory");
+}
+
+
+/**
+ \brief Disable FIQ
+ \details Disables FIQ interrupts by setting the F-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __disable_fault_irq(void)
+{
+ __ASM volatile ("cpsid f" : : : "memory");
+}
+
+
+/**
+ \brief Get Base Priority
+ \details Returns the current value of the Base Priority register.
+ \return Base Priority register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_BASEPRI(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, basepri" : "=r" (result) );
+ return(result);
+}
+
+
+#if (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief Get Base Priority (non-secure)
+ \details Returns the current value of the non-secure Base Priority register when in secure state.
+ \return Base Priority register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_BASEPRI_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Base Priority
+ \details Assigns the given value to the Base Priority register.
+ \param [in] basePri Base Priority value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __set_BASEPRI(uint32_t value)
+{
+ __ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory");
+}
+
+
+#if (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief Set Base Priority (non-secure)
+ \details Assigns the given value to the non-secure Base Priority register when in secure state.
+ \param [in] basePri Base Priority value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_BASEPRI_NS(uint32_t value)
+{
+ __ASM volatile ("MSR basepri_ns, %0" : : "r" (value) : "memory");
+}
+#endif
+
+
+/**
+ \brief Set Base Priority with condition
+ \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
+ or the new value increases the BASEPRI priority level.
+ \param [in] basePri Base Priority value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t value)
+{
+ __ASM volatile ("MSR basepri_max, %0" : : "r" (value) : "memory");
+}
+
+
+#if (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief Set Base Priority with condition (non_secure)
+ \details Assigns the given value to the non-secure Base Priority register when in secure state only if BASEPRI masking is disabled,
+ or the new value increases the BASEPRI priority level.
+ \param [in] basePri Base Priority value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_BASEPRI_MAX_NS(uint32_t value)
+{
+ __ASM volatile ("MSR basepri_max_ns, %0" : : "r" (value) : "memory");
+}
+#endif
+
+
+/**
+ \brief Get Fault Mask
+ \details Returns the current value of the Fault Mask register.
+ \return Fault Mask register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_FAULTMASK(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
+ return(result);
+}
+
+
+#if (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief Get Fault Mask (non-secure)
+ \details Returns the current value of the non-secure Fault Mask register when in secure state.
+ \return Fault Mask register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_FAULTMASK_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Fault Mask
+ \details Assigns the given value to the Fault Mask register.
+ \param [in] faultMask Fault Mask value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+ __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
+}
+
+
+#if (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief Set Fault Mask (non-secure)
+ \details Assigns the given value to the non-secure Fault Mask register when in secure state.
+ \param [in] faultMask Fault Mask value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask)
+{
+ __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory");
+}
+#endif
+
+
+#endif /* ((__ARM_ARCH_7M__ == 1U) || (__ARM_ARCH_8M__ == 1U)) */
+
+
+#if (__ARM_ARCH_8M__ == 1U)
+
+/**
+ \brief Get Process Stack Pointer Limit
+ \details Returns the current value of the Process Stack Pointer Limit (PSPLIM).
+ \return PSPLIM Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PSPLIM(void)
+{
+ register uint32_t result;
+
+ __ASM volatile ("MRS %0, psplim" : "=r" (result) );
+ return(result);
+}
+
+
+#if (__ARM_FEATURE_CMSE == 3U) && (__ARM_ARCH_PROFILE == 'M') /* ToDo: ARMCC_V6: check predefined macro for mainline */
+/**
+ \brief Get Process Stack Pointer Limit (non-secure)
+ \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
+ \return PSPLIM Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PSPLIM_NS(void)
+{
+ register uint32_t result;
+
+ __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Process Stack Pointer Limit
+ \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM).
+ \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit)
+{
+ __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit));
+}
+
+
+#if (__ARM_FEATURE_CMSE == 3U) && (__ARM_ARCH_PROFILE == 'M') /* ToDo: ARMCC_V6: check predefined macro for mainline */
+/**
+ \brief Set Process Stack Pointer (non-secure)
+ \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
+ \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit)
+{
+ __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit));
+}
+#endif
+
+
+/**
+ \brief Get Main Stack Pointer Limit
+ \details Returns the current value of the Main Stack Pointer Limit (MSPLIM).
+ \return MSPLIM Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_MSPLIM(void)
+{
+ register uint32_t result;
+
+ __ASM volatile ("MRS %0, msplim" : "=r" (result) );
+
+ return(result);
+}
+
+
+#if (__ARM_FEATURE_CMSE == 3U) && (__ARM_ARCH_PROFILE == 'M') /* ToDo: ARMCC_V6: check predefined macro for mainline */
+/**
+ \brief Get Main Stack Pointer Limit (non-secure)
+ \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state.
+ \return MSPLIM Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_MSPLIM_NS(void)
+{
+ register uint32_t result;
+
+ __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Main Stack Pointer Limit
+ \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM).
+ \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __set_MSPLIM(uint32_t MainStackPtrLimit)
+{
+ __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit));
+}
+
+
+#if (__ARM_FEATURE_CMSE == 3U) && (__ARM_ARCH_PROFILE == 'M') /* ToDo: ARMCC_V6: check predefined macro for mainline */
+/**
+ \brief Set Main Stack Pointer Limit (non-secure)
+ \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state.
+ \param [in] MainStackPtrLimit Main Stack Pointer value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit)
+{
+ __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit));
+}
+#endif
+
+#endif /* (__ARM_ARCH_8M__ == 1U) */
+
+
+#if ((__ARM_ARCH_7EM__ == 1U) || (__ARM_ARCH_8M__ == 1U)) /* ToDo: ARMCC_V6: check if this is ok for cortex >=4 */
+
+/**
+ \brief Get FPSCR
+ \details eturns the current value of the Floating Point Status/Control register.
+ \return Floating Point Status/Control register value
+ */
+#define __get_FPSCR __builtin_arm_get_fpscr
+#if 0
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_FPSCR(void)
+{
+#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U)
+ uint32_t result;
+
+ __ASM volatile (""); /* Empty asm statement works as a scheduling barrier */
+ __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
+ __ASM volatile ("");
+ return(result);
+#else
+ return(0);
+#endif
+}
+#endif
+
+#if (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief Get FPSCR (non-secure)
+ \details Returns the current value of the non-secure Floating Point Status/Control register when in secure state.
+ \return Floating Point Status/Control register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_FPSCR_NS(void)
+{
+#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U)
+ uint32_t result;
+
+ __ASM volatile (""); /* Empty asm statement works as a scheduling barrier */
+ __ASM volatile ("VMRS %0, fpscr_ns" : "=r" (result) );
+ __ASM volatile ("");
+ return(result);
+#else
+ return(0);
+#endif
+}
+#endif
+
+
+/**
+ \brief Set FPSCR
+ \details Assigns the given value to the Floating Point Status/Control register.
+ \param [in] fpscr Floating Point Status/Control value to set
+ */
+#define __set_FPSCR __builtin_arm_set_fpscr
+#if 0
+__attribute__((always_inline)) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
+{
+#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U)
+ __ASM volatile (""); /* Empty asm statement works as a scheduling barrier */
+ __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc");
+ __ASM volatile ("");
+#endif
+}
+#endif
+
+#if (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief Set FPSCR (non-secure)
+ \details Assigns the given value to the non-secure Floating Point Status/Control register when in secure state.
+ \param [in] fpscr Floating Point Status/Control value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_FPSCR_NS(uint32_t fpscr)
+{
+#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U)
+ __ASM volatile (""); /* Empty asm statement works as a scheduling barrier */
+ __ASM volatile ("VMSR fpscr_ns, %0" : : "r" (fpscr) : "vfpcc");
+ __ASM volatile ("");
+#endif
+}
+#endif
+
+#endif /* ((__ARM_ARCH_7EM__ == 1U) || (__ARM_ARCH_8M__ == 1U)) */
+
+
+
+/*@} end of CMSIS_Core_RegAccFunctions */
+
+
+/* ########################## Core Instruction Access ######################### */
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
+ Access to dedicated instructions
+ @{
+*/
+
+/* Define macros for porting to both thumb1 and thumb2.
+ * For thumb1, use low register (r0-r7), specified by constraint "l"
+ * Otherwise, use general registers, specified by constraint "r" */
+#if defined (__thumb__) && !defined (__thumb2__)
+#define __CMSIS_GCC_OUT_REG(r) "=l" (r)
+#define __CMSIS_GCC_USE_REG(r) "l" (r)
+#else
+#define __CMSIS_GCC_OUT_REG(r) "=r" (r)
+#define __CMSIS_GCC_USE_REG(r) "r" (r)
+#endif
+
+/**
+ \brief No Operation
+ \details No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+#define __NOP __builtin_arm_nop
+
+/**
+ \brief Wait For Interrupt
+ \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
+ */
+#define __WFI __builtin_arm_wfi
+
+
+/**
+ \brief Wait For Event
+ \details Wait For Event is a hint instruction that permits the processor to enter
+ a low-power state until one of a number of events occurs.
+ */
+#define __WFE __builtin_arm_wfe
+
+
+/**
+ \brief Send Event
+ \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+#define __SEV __builtin_arm_sev
+
+
+/**
+ \brief Instruction Synchronization Barrier
+ \details Instruction Synchronization Barrier flushes the pipeline in the processor,
+ so that all instructions following the ISB are fetched from cache or memory,
+ after the instruction has been completed.
+ */
+#define __ISB() __builtin_arm_isb(0xF);
+
+/**
+ \brief Data Synchronization Barrier
+ \details Acts as a special kind of Data Memory Barrier.
+ It completes when all explicit memory accesses before this instruction complete.
+ */
+#define __DSB() __builtin_arm_dsb(0xF);
+
+
+/**
+ \brief Data Memory Barrier
+ \details Ensures the apparent order of the explicit memory operations before
+ and after the instruction, without ensuring their completion.
+ */
+#define __DMB() __builtin_arm_dmb(0xF);
+
+
+/**
+ \brief Reverse byte order (32 bit)
+ \details Reverses the byte order in integer value.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#define __REV __builtin_bswap32
+
+
+/**
+ \brief Reverse byte order (16 bit)
+ \details Reverses the byte order in two unsigned short values.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#define __REV16 __builtin_bswap16 /* ToDo: ARMCC_V6: check if __builtin_bswap16 could be used */
+#if 0
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV16(uint32_t value)
+{
+ uint32_t result;
+
+ __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Reverse byte order in signed short value
+ \details Reverses the byte order in a signed short value with sign extension to integer.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+ /* ToDo: ARMCC_V6: check if __builtin_bswap16 could be used */
+__attribute__((always_inline)) __STATIC_INLINE int32_t __REVSH(int32_t value)
+{
+ int32_t result;
+
+ __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+ return(result);
+}
+
+
+/**
+ \brief Rotate Right in unsigned value (32 bit)
+ \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+ \param [in] op1 Value to rotate
+ \param [in] op2 Number of Bits to rotate
+ \return Rotated value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
+{
+ return (op1 >> op2) | (op1 << (32U - op2));
+}
+
+
+/**
+ \brief Breakpoint
+ \details Causes the processor to enter Debug state.
+ Debug tools can use this to investigate system state when the instruction at a particular address is reached.
+ \param [in] value is ignored by the processor.
+ If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value) __ASM volatile ("bkpt "#value)
+
+
+/**
+ \brief Reverse bit order of value
+ \details Reverses the bit order of the given value.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+ /* ToDo: ARMCC_V6: check if __builtin_arm_rbit is supported */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
+{
+ uint32_t result;
+
+#if ((__ARM_ARCH_7M__ == 1U) || (__ARM_ARCH_7EM__ == 1U) || (__ARM_ARCH_8M__ == 1U)) /* ToDo: ARMCC_V6: check if this is ok for cortex >=3 */
+ __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
+#else
+ int32_t s = 4 /*sizeof(v)*/ * 8 - 1; /* extra shift needed at end */
+
+ result = value; /* r will be reversed bits of v; first get LSB of v */
+ for (value >>= 1U; value; value >>= 1U)
+ {
+ result <<= 1U;
+ result |= value & 1U;
+ s--;
+ }
+ result <<= s; /* shift when v's highest bits are zero */
+#endif
+ return(result);
+}
+
+
+/**
+ \brief Count leading zeros
+ \details Counts the number of leading zeros of a data value.
+ \param [in] value Value to count the leading zeros
+ \return number of leading zeros in value
+ */
+#define __CLZ __builtin_clz
+
+
+#if ((__ARM_ARCH_7M__ == 1U) || (__ARM_ARCH_7EM__ == 1U) || (__ARM_ARCH_8M__ == 1U)) /* ToDo: ARMCC_V6: check if this is ok for cortex >=3 */
+
+/**
+ \brief LDR Exclusive (8 bit)
+ \details Executes a exclusive LDR instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+#define __LDREXB (uint8_t)__builtin_arm_ldrex
+
+
+/**
+ \brief LDR Exclusive (16 bit)
+ \details Executes a exclusive LDR instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+#define __LDREXH (uint16_t)__builtin_arm_ldrex
+
+
+/**
+ \brief LDR Exclusive (32 bit)
+ \details Executes a exclusive LDR instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+#define __LDREXW (uint32_t)__builtin_arm_ldrex
+
+
+/**
+ \brief STR Exclusive (8 bit)
+ \details Executes a exclusive STR instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STREXB (uint32_t)__builtin_arm_strex
+
+
+/**
+ \brief STR Exclusive (16 bit)
+ \details Executes a exclusive STR instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STREXH (uint32_t)__builtin_arm_strex
+
+
+/**
+ \brief STR Exclusive (32 bit)
+ \details Executes a exclusive STR instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STREXW (uint32_t)__builtin_arm_strex
+
+
+/**
+ \brief Remove the exclusive lock
+ \details Removes the exclusive lock which is created by LDREX.
+ */
+#define __CLREX __builtin_arm_clrex
+
+
+/**
+ \brief Signed Saturate
+ \details Saturates a signed value.
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (1..32)
+ \return Saturated value
+ */
+/*#define __SSAT __builtin_arm_ssat*/
+#define __SSAT(ARG1,ARG2) \
+({ \
+ int32_t __RES, __ARG1 = (ARG1); \
+ __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
+ __RES; \
+ })
+
+
+/**
+ \brief Unsigned Saturate
+ \details Saturates an unsigned value.
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (0..31)
+ \return Saturated value
+ */
+#define __USAT __builtin_arm_usat
+#if 0
+#define __USAT(ARG1,ARG2) \
+({ \
+ uint32_t __RES, __ARG1 = (ARG1); \
+ __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
+ __RES; \
+ })
+#endif
+
+
+/**
+ \brief Rotate Right with Extend (32 bit)
+ \details Moves each bit of a bitstring right by one bit.
+ The carry input is shifted in at the left end of the bitstring.
+ \param [in] value Value to rotate
+ \return Rotated value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __RRX(uint32_t value)
+{
+ uint32_t result;
+
+ __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+ return(result);
+}
+
+
+/**
+ \brief LDRT Unprivileged (8 bit)
+ \details Executes a Unprivileged LDRT instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDRBT(volatile uint8_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return ((uint8_t) result); /* Add explicit type cast here */
+}
+
+
+/**
+ \brief LDRT Unprivileged (16 bit)
+ \details Executes a Unprivileged LDRT instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDRHT(volatile uint16_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return ((uint16_t) result); /* Add explicit type cast here */
+}
+
+
+/**
+ \brief LDRT Unprivileged (32 bit)
+ \details Executes a Unprivileged LDRT instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDRT(volatile uint32_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return(result);
+}
+
+
+/**
+ \brief STRT Unprivileged (8 bit)
+ \details Executes a Unprivileged STRT instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __STRBT(uint8_t value, volatile uint8_t *ptr)
+{
+ __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+ \brief STRT Unprivileged (16 bit)
+ \details Executes a Unprivileged STRT instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __STRHT(uint16_t value, volatile uint16_t *ptr)
+{
+ __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+ \brief STRT Unprivileged (32 bit)
+ \details Executes a Unprivileged STRT instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __STRT(uint32_t value, volatile uint32_t *ptr)
+{
+ __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) );
+}
+
+#endif /* ((__ARM_ARCH_7M__ == 1U) || (__ARM_ARCH_7EM__ == 1U) || (__ARM_ARCH_8M__ == 1U)) */
+
+
+#if (__ARM_ARCH_8M__ == 1U)
+
+/**
+ \brief Load-Acquire (8 bit)
+ \details Executes a LDAB instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDAB(volatile uint8_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return ((uint8_t) result);
+}
+
+
+/**
+ \brief Load-Acquire (16 bit)
+ \details Executes a LDAH instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDAH(volatile uint16_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return ((uint16_t) result);
+}
+
+
+/**
+ \brief Load-Acquire (32 bit)
+ \details Executes a LDA instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDA(volatile uint32_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return(result);
+}
+
+
+/**
+ \brief Store-Release (8 bit)
+ \details Executes a STLB instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __STLB(uint8_t value, volatile uint8_t *ptr)
+{
+ __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+ \brief Store-Release (16 bit)
+ \details Executes a STLH instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __STLH(uint16_t value, volatile uint16_t *ptr)
+{
+ __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+ \brief Store-Release (32 bit)
+ \details Executes a STL instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __STL(uint32_t value, volatile uint32_t *ptr)
+{
+ __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+ \brief Load-Acquire Exclusive (8 bit)
+ \details Executes a LDAB exclusive instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+#define __LDAEXB (uint8_t)__builtin_arm_ldaex
+
+
+/**
+ \brief Load-Acquire Exclusive (16 bit)
+ \details Executes a LDAH exclusive instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+#define __LDAEXH (uint16_t)__builtin_arm_ldaex
+
+
+/**
+ \brief Load-Acquire Exclusive (32 bit)
+ \details Executes a LDA exclusive instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+#define __LDAEX (uint32_t)__builtin_arm_ldaex
+
+
+/**
+ \brief Store-Release Exclusive (8 bit)
+ \details Executes a STLB exclusive instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STLEXB (uint32_t)__builtin_arm_stlex
+
+
+/**
+ \brief Store-Release Exclusive (16 bit)
+ \details Executes a STLH exclusive instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STLEXH (uint32_t)__builtin_arm_stlex
+
+
+/**
+ \brief Store-Release Exclusive (32 bit)
+ \details Executes a STL exclusive instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STLEX (uint32_t)__builtin_arm_stlex
+
+#endif /* (__ARM_ARCH_8M__ == 1U) */
+
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
+
+
+/* ################### Compiler specific Intrinsics ########################### */
+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
+ Access to dedicated SIMD instructions
+ @{
+*/
+
+#if (__ARM_FEATURE_DSP == 1U) /* ToDo: ARMCC_V6: This should be ARCH >= ARMv7-M + SIMD */
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+#define __SSAT16(ARG1,ARG2) \
+({ \
+ uint32_t __RES, __ARG1 = (ARG1); \
+ __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
+ __RES; \
+ })
+
+#define __USAT16(ARG1,ARG2) \
+({ \
+ uint32_t __RES, __ARG1 = (ARG1); \
+ __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
+ __RES; \
+ })
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1)
+{
+ uint32_t result;
+
+ __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1)
+{
+ uint32_t result;
+
+ __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+ union llreg_u{
+ uint32_t w32[2];
+ uint64_t w64;
+ } llr;
+ llr.w64 = acc;
+
+#ifndef __ARMEB__ /* Little endian */
+ __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else /* Big endian */
+ __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+ return(llr.w64);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+ union llreg_u{
+ uint32_t w32[2];
+ uint64_t w64;
+ } llr;
+ llr.w64 = acc;
+
+#ifndef __ARMEB__ /* Little endian */
+ __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else /* Big endian */
+ __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+ return(llr.w64);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+ union llreg_u{
+ uint32_t w32[2];
+ uint64_t w64;
+ } llr;
+ llr.w64 = acc;
+
+#ifndef __ARMEB__ /* Little endian */
+ __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else /* Big endian */
+ __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+ return(llr.w64);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+ union llreg_u{
+ uint32_t w32[2];
+ uint64_t w64;
+ } llr;
+ llr.w64 = acc;
+
+#ifndef __ARMEB__ /* Little endian */
+ __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else /* Big endian */
+ __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+ return(llr.w64);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SEL (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE int32_t __QADD( int32_t op1, int32_t op2)
+{
+ int32_t result;
+
+ __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE int32_t __QSUB( int32_t op1, int32_t op2)
+{
+ int32_t result;
+
+ __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+#define __PKHBT(ARG1,ARG2,ARG3) \
+({ \
+ uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
+ __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
+ __RES; \
+ })
+
+#define __PKHTB(ARG1,ARG2,ARG3) \
+({ \
+ uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
+ if (ARG3 == 0) \
+ __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \
+ else \
+ __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
+ __RES; \
+ })
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
+{
+ int32_t result;
+
+ __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+#endif /* (__ARM_FEATURE_DSP == 1U) */
+/*@} end of group CMSIS_SIMD_intrinsics */
+
+
+#endif /* __CMSIS_ARMCC_V6_H */
diff --git a/Include/cmsis_gcc.h b/Include/cmsis_gcc.h
new file mode 100644
index 0000000..d868f2e
--- /dev/null
+++ b/Include/cmsis_gcc.h
@@ -0,0 +1,1373 @@
+/**************************************************************************//**
+ * @file cmsis_gcc.h
+ * @brief CMSIS Cortex-M Core Function/Instruction Header File
+ * @version V4.30
+ * @date 20. October 2015
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2015 ARM LIMITED
+
+ All rights reserved.
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+ - Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ - Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+ - Neither the name of ARM nor the names of its contributors may be used
+ to endorse or promote products derived from this software without
+ specific prior written permission.
+ *
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ POSSIBILITY OF SUCH DAMAGE.
+ ---------------------------------------------------------------------------*/
+
+
+#ifndef __CMSIS_GCC_H
+#define __CMSIS_GCC_H
+
+/* ignore some GCC warnings */
+#if defined ( __GNUC__ )
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wsign-conversion"
+#pragma GCC diagnostic ignored "-Wconversion"
+#pragma GCC diagnostic ignored "-Wunused-parameter"
+#endif
+
+
+/* ########################### Core Function Access ########################### */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+ @{
+ */
+
+/**
+ \brief Enable IRQ Interrupts
+ \details Enables IRQ interrupts by clearing the I-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)
+{
+ __ASM volatile ("cpsie i" : : : "memory");
+}
+
+
+/**
+ \brief Disable IRQ Interrupts
+ \details Disables IRQ interrupts by setting the I-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void)
+{
+ __ASM volatile ("cpsid i" : : : "memory");
+}
+
+
+/**
+ \brief Get Control Register
+ \details Returns the content of the Control Register.
+ \return Control Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, control" : "=r" (result) );
+ return(result);
+}
+
+
+/**
+ \brief Set Control Register
+ \details Writes the given value to the Control Register.
+ \param [in] control Control Register value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control)
+{
+ __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
+}
+
+
+/**
+ \brief Get IPSR Register
+ \details Returns the content of the IPSR Register.
+ \return IPSR Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
+ return(result);
+}
+
+
+/**
+ \brief Get APSR Register
+ \details Returns the content of the APSR Register.
+ \return APSR Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, apsr" : "=r" (result) );
+ return(result);
+}
+
+
+/**
+ \brief Get xPSR Register
+ \details Returns the content of the xPSR Register.
+
+ \return xPSR Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
+ return(result);
+}
+
+
+/**
+ \brief Get Process Stack Pointer
+ \details Returns the current value of the Process Stack Pointer (PSP).
+ \return PSP Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void)
+{
+ register uint32_t result;
+
+ __ASM volatile ("MRS %0, psp\n" : "=r" (result) );
+ return(result);
+}
+
+
+/**
+ \brief Set Process Stack Pointer
+ \details Assigns the given value to the Process Stack Pointer (PSP).
+ \param [in] topOfProcStack Process Stack Pointer value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
+{
+ __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) : "sp");
+}
+
+
+/**
+ \brief Get Main Stack Pointer
+ \details Returns the current value of the Main Stack Pointer (MSP).
+ \return MSP Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void)
+{
+ register uint32_t result;
+
+ __ASM volatile ("MRS %0, msp\n" : "=r" (result) );
+ return(result);
+}
+
+
+/**
+ \brief Set Main Stack Pointer
+ \details Assigns the given value to the Main Stack Pointer (MSP).
+
+ \param [in] topOfMainStack Main Stack Pointer value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
+{
+ __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) : "sp");
+}
+
+
+/**
+ \brief Get Priority Mask
+ \details Returns the current state of the priority mask bit from the Priority Mask Register.
+ \return Priority Mask value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, primask" : "=r" (result) );
+ return(result);
+}
+
+
+/**
+ \brief Set Priority Mask
+ \details Assigns the given value to the Priority Mask Register.
+ \param [in] priMask Priority Mask
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
+{
+ __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
+}
+
+
+#if (__CORTEX_M >= 0x03U)
+
+/**
+ \brief Enable FIQ
+ \details Enables FIQ interrupts by clearing the F-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void)
+{
+ __ASM volatile ("cpsie f" : : : "memory");
+}
+
+
+/**
+ \brief Disable FIQ
+ \details Disables FIQ interrupts by setting the F-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void)
+{
+ __ASM volatile ("cpsid f" : : : "memory");
+}
+
+
+/**
+ \brief Get Base Priority
+ \details Returns the current value of the Base Priority register.
+ \return Base Priority register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, basepri" : "=r" (result) );
+ return(result);
+}
+
+
+/**
+ \brief Set Base Priority
+ \details Assigns the given value to the Base Priority register.
+ \param [in] basePri Base Priority value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value)
+{
+ __ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory");
+}
+
+
+/**
+ \brief Set Base Priority with condition
+ \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
+ or the new value increases the BASEPRI priority level.
+ \param [in] basePri Base Priority value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t value)
+{
+ __ASM volatile ("MSR basepri_max, %0" : : "r" (value) : "memory");
+}
+
+
+/**
+ \brief Get Fault Mask
+ \details Returns the current value of the Fault Mask register.
+ \return Fault Mask register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
+ return(result);
+}
+
+
+/**
+ \brief Set Fault Mask
+ \details Assigns the given value to the Fault Mask register.
+ \param [in] faultMask Fault Mask value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+ __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
+}
+
+#endif /* (__CORTEX_M >= 0x03U) */
+
+
+#if (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U)
+
+/**
+ \brief Get FPSCR
+ \details Returns the current value of the Floating Point Status/Control register.
+ \return Floating Point Status/Control register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void)
+{
+#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U)
+ uint32_t result;
+
+ /* Empty asm statement works as a scheduling barrier */
+ __ASM volatile ("");
+ __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
+ __ASM volatile ("");
+ return(result);
+#else
+ return(0);
+#endif
+}
+
+
+/**
+ \brief Set FPSCR
+ \details Assigns the given value to the Floating Point Status/Control register.
+ \param [in] fpscr Floating Point Status/Control value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
+{
+#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U)
+ /* Empty asm statement works as a scheduling barrier */
+ __ASM volatile ("");
+ __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc");
+ __ASM volatile ("");
+#endif
+}
+
+#endif /* (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U) */
+
+
+
+/*@} end of CMSIS_Core_RegAccFunctions */
+
+
+/* ########################## Core Instruction Access ######################### */
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
+ Access to dedicated instructions
+ @{
+*/
+
+/* Define macros for porting to both thumb1 and thumb2.
+ * For thumb1, use low register (r0-r7), specified by constraint "l"
+ * Otherwise, use general registers, specified by constraint "r" */
+#if defined (__thumb__) && !defined (__thumb2__)
+#define __CMSIS_GCC_OUT_REG(r) "=l" (r)
+#define __CMSIS_GCC_USE_REG(r) "l" (r)
+#else
+#define __CMSIS_GCC_OUT_REG(r) "=r" (r)
+#define __CMSIS_GCC_USE_REG(r) "r" (r)
+#endif
+
+/**
+ \brief No Operation
+ \details No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __NOP(void)
+{
+ __ASM volatile ("nop");
+}
+
+
+/**
+ \brief Wait For Interrupt
+ \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __WFI(void)
+{
+ __ASM volatile ("wfi");
+}
+
+
+/**
+ \brief Wait For Event
+ \details Wait For Event is a hint instruction that permits the processor to enter
+ a low-power state until one of a number of events occurs.
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __WFE(void)
+{
+ __ASM volatile ("wfe");
+}
+
+
+/**
+ \brief Send Event
+ \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __SEV(void)
+{
+ __ASM volatile ("sev");
+}
+
+
+/**
+ \brief Instruction Synchronization Barrier
+ \details Instruction Synchronization Barrier flushes the pipeline in the processor,
+ so that all instructions following the ISB are fetched from cache or memory,
+ after the instruction has been completed.
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __ISB(void)
+{
+ __ASM volatile ("isb 0xF":::"memory");
+}
+
+
+/**
+ \brief Data Synchronization Barrier
+ \details Acts as a special kind of Data Memory Barrier.
+ It completes when all explicit memory accesses before this instruction complete.
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __DSB(void)
+{
+ __ASM volatile ("dsb 0xF":::"memory");
+}
+
+
+/**
+ \brief Data Memory Barrier
+ \details Ensures the apparent order of the explicit memory operations before
+ and after the instruction, without ensuring their completion.
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __DMB(void)
+{
+ __ASM volatile ("dmb 0xF":::"memory");
+}
+
+
+/**
+ \brief Reverse byte order (32 bit)
+ \details Reverses the byte order in integer value.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV(uint32_t value)
+{
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)
+ return __builtin_bswap32(value);
+#else
+ uint32_t result;
+
+ __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+ return(result);
+#endif
+}
+
+
+/**
+ \brief Reverse byte order (16 bit)
+ \details Reverses the byte order in two unsigned short values.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV16(uint32_t value)
+{
+ uint32_t result;
+
+ __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+ return(result);
+}
+
+
+/**
+ \brief Reverse byte order in signed short value
+ \details Reverses the byte order in a signed short value with sign extension to integer.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+__attribute__((always_inline)) __STATIC_INLINE int32_t __REVSH(int32_t value)
+{
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+ return (short)__builtin_bswap16(value);
+#else
+ int32_t result;
+
+ __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+ return(result);
+#endif
+}
+
+
+/**
+ \brief Rotate Right in unsigned value (32 bit)
+ \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+ \param [in] value Value to rotate
+ \param [in] value Number of Bits to rotate
+ \return Rotated value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
+{
+ return (op1 >> op2) | (op1 << (32U - op2));
+}
+
+
+/**
+ \brief Breakpoint
+ \details Causes the processor to enter Debug state.
+ Debug tools can use this to investigate system state when the instruction at a particular address is reached.
+ \param [in] value is ignored by the processor.
+ If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value) __ASM volatile ("bkpt "#value)
+
+
+/**
+ \brief Reverse bit order of value
+ \details Reverses the bit order of the given value.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
+{
+ uint32_t result;
+
+#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U)
+ __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
+#else
+ int32_t s = 4 /*sizeof(v)*/ * 8 - 1; /* extra shift needed at end */
+
+ result = value; /* r will be reversed bits of v; first get LSB of v */
+ for (value >>= 1U; value; value >>= 1U)
+ {
+ result <<= 1U;
+ result |= value & 1U;
+ s--;
+ }
+ result <<= s; /* shift when v's highest bits are zero */
+#endif
+ return(result);
+}
+
+
+/**
+ \brief Count leading zeros
+ \details Counts the number of leading zeros of a data value.
+ \param [in] value Value to count the leading zeros
+ \return number of leading zeros in value
+ */
+#define __CLZ __builtin_clz
+
+
+#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U)
+
+/**
+ \brief LDR Exclusive (8 bit)
+ \details Executes a exclusive LDR instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr)
+{
+ uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+ __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) );
+#else
+ /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+ accepted by assembler. So has to use following less efficient pattern.
+ */
+ __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+#endif
+ return ((uint8_t) result); /* Add explicit type cast here */
+}
+
+
+/**
+ \brief LDR Exclusive (16 bit)
+ \details Executes a exclusive LDR instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr)
+{
+ uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+ __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) );
+#else
+ /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+ accepted by assembler. So has to use following less efficient pattern.
+ */
+ __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+#endif
+ return ((uint16_t) result); /* Add explicit type cast here */
+}
+
+
+/**
+ \brief LDR Exclusive (32 bit)
+ \details Executes a exclusive LDR instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
+ return(result);
+}
+
+
+/**
+ \brief STR Exclusive (8 bit)
+ \details Executes a exclusive STR instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
+{
+ uint32_t result;
+
+ __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
+ return(result);
+}
+
+
+/**
+ \brief STR Exclusive (16 bit)
+ \details Executes a exclusive STR instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
+{
+ uint32_t result;
+
+ __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
+ return(result);
+}
+
+
+/**
+ \brief STR Exclusive (32 bit)
+ \details Executes a exclusive STR instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
+{
+ uint32_t result;
+
+ __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
+ return(result);
+}
+
+
+/**
+ \brief Remove the exclusive lock
+ \details Removes the exclusive lock which is created by LDREX.
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __CLREX(void)
+{
+ __ASM volatile ("clrex" ::: "memory");
+}
+
+
+/**
+ \brief Signed Saturate
+ \details Saturates a signed value.
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (1..32)
+ \return Saturated value
+ */
+#define __SSAT(ARG1,ARG2) \
+({ \
+ uint32_t __RES, __ARG1 = (ARG1); \
+ __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
+ __RES; \
+ })
+
+
+/**
+ \brief Unsigned Saturate
+ \details Saturates an unsigned value.
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (0..31)
+ \return Saturated value
+ */
+#define __USAT(ARG1,ARG2) \
+({ \
+ uint32_t __RES, __ARG1 = (ARG1); \
+ __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
+ __RES; \
+ })
+
+
+/**
+ \brief Rotate Right with Extend (32 bit)
+ \details Moves each bit of a bitstring right by one bit.
+ The carry input is shifted in at the left end of the bitstring.
+ \param [in] value Value to rotate
+ \return Rotated value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __RRX(uint32_t value)
+{
+ uint32_t result;
+
+ __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+ return(result);
+}
+
+
+/**
+ \brief LDRT Unprivileged (8 bit)
+ \details Executes a Unprivileged LDRT instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDRBT(volatile uint8_t *addr)
+{
+ uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+ __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*addr) );
+#else
+ /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+ accepted by assembler. So has to use following less efficient pattern.
+ */
+ __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+#endif
+ return ((uint8_t) result); /* Add explicit type cast here */
+}
+
+
+/**
+ \brief LDRT Unprivileged (16 bit)
+ \details Executes a Unprivileged LDRT instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDRHT(volatile uint16_t *addr)
+{
+ uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+ __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*addr) );
+#else
+ /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+ accepted by assembler. So has to use following less efficient pattern.
+ */
+ __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+#endif
+ return ((uint16_t) result); /* Add explicit type cast here */
+}
+
+
+/**
+ \brief LDRT Unprivileged (32 bit)
+ \details Executes a Unprivileged LDRT instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDRT(volatile uint32_t *addr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*addr) );
+ return(result);
+}
+
+
+/**
+ \brief STRT Unprivileged (8 bit)
+ \details Executes a Unprivileged STRT instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __STRBT(uint8_t value, volatile uint8_t *addr)
+{
+ __ASM volatile ("strbt %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+ \brief STRT Unprivileged (16 bit)
+ \details Executes a Unprivileged STRT instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __STRHT(uint16_t value, volatile uint16_t *addr)
+{
+ __ASM volatile ("strht %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+ \brief STRT Unprivileged (32 bit)
+ \details Executes a Unprivileged STRT instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __STRT(uint32_t value, volatile uint32_t *addr)
+{
+ __ASM volatile ("strt %1, %0" : "=Q" (*addr) : "r" (value) );
+}
+
+#endif /* (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) */
+
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
+
+
+/* ################### Compiler specific Intrinsics ########################### */
+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
+ Access to dedicated SIMD instructions
+ @{
+*/
+
+#if (__CORTEX_M >= 0x04U) /* only for Cortex-M4 and above */
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+#define __SSAT16(ARG1,ARG2) \
+({ \
+ int32_t __RES, __ARG1 = (ARG1); \
+ __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
+ __RES; \
+ })
+
+#define __USAT16(ARG1,ARG2) \
+({ \
+ uint32_t __RES, __ARG1 = (ARG1); \
+ __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
+ __RES; \
+ })
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1)
+{
+ uint32_t result;
+
+ __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1)
+{
+ uint32_t result;
+
+ __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+ union llreg_u{
+ uint32_t w32[2];
+ uint64_t w64;
+ } llr;
+ llr.w64 = acc;
+
+#ifndef __ARMEB__ /* Little endian */
+ __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else /* Big endian */
+ __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+ return(llr.w64);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+ union llreg_u{
+ uint32_t w32[2];
+ uint64_t w64;
+ } llr;
+ llr.w64 = acc;
+
+#ifndef __ARMEB__ /* Little endian */
+ __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else /* Big endian */
+ __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+ return(llr.w64);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+ union llreg_u{
+ uint32_t w32[2];
+ uint64_t w64;
+ } llr;
+ llr.w64 = acc;
+
+#ifndef __ARMEB__ /* Little endian */
+ __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else /* Big endian */
+ __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+ return(llr.w64);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+ union llreg_u{
+ uint32_t w32[2];
+ uint64_t w64;
+ } llr;
+ llr.w64 = acc;
+
+#ifndef __ARMEB__ /* Little endian */
+ __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else /* Big endian */
+ __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+ return(llr.w64);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SEL (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __QADD( int32_t op1, int32_t op2)
+{
+ int32_t result;
+
+ __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __QSUB( int32_t op1, int32_t op2)
+{
+ int32_t result;
+
+ __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+#define __PKHBT(ARG1,ARG2,ARG3) \
+({ \
+ uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
+ __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
+ __RES; \
+ })
+
+#define __PKHTB(ARG1,ARG2,ARG3) \
+({ \
+ uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
+ if (ARG3 == 0) \
+ __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \
+ else \
+ __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
+ __RES; \
+ })
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
+{
+ int32_t result;
+
+ __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+#endif /* (__CORTEX_M >= 0x04) */
+/*@} end of group CMSIS_SIMD_intrinsics */
+
+
+#if defined ( __GNUC__ )
+#pragma GCC diagnostic pop
+#endif
+
+#endif /* __CMSIS_GCC_H */
diff --git a/Include/core_cm0.h b/Include/core_cm0.h
new file mode 100644
index 0000000..fdee521
--- /dev/null
+++ b/Include/core_cm0.h
@@ -0,0 +1,798 @@
+/**************************************************************************//**
+ * @file core_cm0.h
+ * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File
+ * @version V4.30
+ * @date 20. October 2015
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2015 ARM LIMITED
+
+ All rights reserved.
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+ - Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ - Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+ - Neither the name of ARM nor the names of its contributors may be used
+ to endorse or promote products derived from this software without
+ specific prior written permission.
+ *
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ POSSIBILITY OF SUCH DAMAGE.
+ ---------------------------------------------------------------------------*/
+
+
+#if defined ( __ICCARM__ )
+ #pragma system_include /* treat file as system include file for MISRA check */
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #pragma clang system_header /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CM0_H_GENERIC
+#define __CORE_CM0_H_GENERIC
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+ \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
+ CMSIS violates the following MISRA-C:2004 rules:
+
+ \li Required Rule 8.5, object/function definition in header file.<br>
+ Function definitions in header files are used to allow 'inlining'.
+
+ \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+ Unions are used for effective representation of core registers.
+
+ \li Advisory Rule 19.7, Function-like macro defined.<br>
+ Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ * CMSIS definitions
+ ******************************************************************************/
+/**
+ \ingroup Cortex_M0
+ @{
+ */
+
+/* CMSIS CM0 definitions */
+#define __CM0_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS HAL main version */
+#define __CM0_CMSIS_VERSION_SUB (0x1EU) /*!< [15:0] CMSIS HAL sub version */
+#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16U) | \
+ __CM0_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
+
+#define __CORTEX_M (0x00U) /*!< Cortex-M Core */
+
+
+#if defined ( __CC_ARM )
+ #define __ASM __asm /*!< asm keyword for ARM Compiler */
+ #define __INLINE __inline /*!< inline keyword for ARM Compiler */
+ #define __STATIC_INLINE static __inline
+
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #define __ASM __asm /*!< asm keyword for ARM Compiler */
+ #define __INLINE __inline /*!< inline keyword for ARM Compiler */
+ #define __STATIC_INLINE static __inline
+
+#elif defined ( __GNUC__ )
+ #define __ASM __asm /*!< asm keyword for GNU Compiler */
+ #define __INLINE inline /*!< inline keyword for GNU Compiler */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __ICCARM__ )
+ #define __ASM __asm /*!< asm keyword for IAR Compiler */
+ #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __TMS470__ )
+ #define __ASM __asm /*!< asm keyword for TI CCS Compiler */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __TASKING__ )
+ #define __ASM __asm /*!< asm keyword for TASKING Compiler */
+ #define __INLINE inline /*!< inline keyword for TASKING Compiler */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __CSMC__ )
+ #define __packed
+ #define __ASM _asm /*!< asm keyword for COSMIC Compiler */
+ #define __INLINE inline /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */
+ #define __STATIC_INLINE static inline
+
+#else
+ #error Unknown compiler
+#endif
+
+/** __FPU_USED indicates whether an FPU is used or not.
+ This core does not support an FPU at all
+*/
+#define __FPU_USED 0U
+
+#if defined ( __CC_ARM )
+ #if defined __TARGET_FPU_VFP
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #if defined __ARM_PCS_VFP
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __GNUC__ )
+ #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __ICCARM__ )
+ #if defined __ARMVFP__
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __TMS470__ )
+ #if defined __TI_VFP_SUPPORT__
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __TASKING__ )
+ #if defined __FPU_VFP__
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __CSMC__ )
+ #if ( __CSMC__ & 0x400U)
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#endif
+
+#include "core_cmInstr.h" /* Core Instruction Access */
+#include "core_cmFunc.h" /* Core Function Access */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM0_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM0_H_DEPENDANT
+#define __CORE_CM0_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+ #ifndef __CM0_REV
+ #define __CM0_REV 0x0000U
+ #warning "__CM0_REV not defined in device header file; using default!"
+ #endif
+
+ #ifndef __NVIC_PRIO_BITS
+ #define __NVIC_PRIO_BITS 2U
+ #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+ #endif
+
+ #ifndef __Vendor_SysTickConfig
+ #define __Vendor_SysTickConfig 0U
+ #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+ #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+ \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+ <strong>IO Type Qualifiers</strong> are used
+ \li to specify the access to peripheral variables.
+ \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+ #define __I volatile /*!< Defines 'read only' permissions */
+#else
+ #define __I volatile const /*!< Defines 'read only' permissions */
+#endif
+#define __O volatile /*!< Defines 'write only' permissions */
+#define __IO volatile /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define __IM volatile const /*! Defines 'read only' structure member permissions */
+#define __OM volatile /*! Defines 'write only' structure member permissions */
+#define __IOM volatile /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group Cortex_M0 */
+
+
+
+/*******************************************************************************
+ * Register Abstraction
+ Core Register contain:
+ - Core Register
+ - Core NVIC Register
+ - Core SCB Register
+ - Core SysTick Register
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_core_register Defines and Type Definitions
+ \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CORE Status and Control Registers
+ \brief Core Register type definitions.
+ @{
+ */
+
+/**
+ \brief Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos 31U /*!< APSR: N Position */
+#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
+
+#define APSR_Z_Pos 30U /*!< APSR: Z Position */
+#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
+
+#define APSR_C_Pos 29U /*!< APSR: C Position */
+#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
+
+#define APSR_V_Pos 28U /*!< APSR: V Position */
+#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
+
+
+/**
+ \brief Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
+ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
+ uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos 31U /*!< xPSR: N Position */
+#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
+#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos 29U /*!< xPSR: C Position */
+#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos 28U /*!< xPSR: V Position */
+#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
+
+#define xPSR_T_Pos 24U /*!< xPSR: T Position */
+#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
+
+#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t _reserved0:1; /*!< bit: 0 Reserved */
+ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
+ uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
+ \brief Type definitions for the NVIC Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+ __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
+ uint32_t RESERVED0[31U];
+ __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
+ uint32_t RSERVED1[31U];
+ __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
+ uint32_t RESERVED2[31U];
+ __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
+ uint32_t RESERVED3[31U];
+ uint32_t RESERVED4[64U];
+ __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
+} NVIC_Type;
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCB System Control Block (SCB)
+ \brief Type definitions for the System Control Block Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+ __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
+ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
+ uint32_t RESERVED0;
+ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
+ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
+ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
+ uint32_t RESERVED1;
+ __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
+ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)
+ \brief Type definitions for the System Timer Registers.
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
+ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
+ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
+ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
+ \brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
+ Therefore they are not covered by the Cortex-M0 header file.
+ @{
+ */
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_bitfield Core register bit field macros
+ \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+ @{
+ */
+
+/**
+ \brief Mask and shift a bit field value for use in a register bit range.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of the bit field.
+ \return Masked and shifted value.
+*/
+#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk)
+
+/**
+ \brief Mask and shift a register value to extract a bit filed value.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of register.
+ \return Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_base Core Definitions
+ \brief Definitions for base addresses, unions, and structures.
+ @{
+ */
+
+/* Memory mapping of Cortex-M0 Hardware */
+#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
+#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
+#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
+#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
+
+#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
+#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
+#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
+
+
+/*@} */
+
+
+
+/*******************************************************************************
+ * Hardware Abstraction Layer
+ Core Function Interface contains:
+ - Core NVIC Functions
+ - Core SysTick Functions
+ - Core Register Access Functions
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ########################## NVIC functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+ \brief Functions that manage interrupts and exceptions via the NVIC.
+ @{
+ */
+
+/* Interrupt Priorities are WORD accessible only under ARMv6M */
+/* The following MACROS handle generation of the register offset and byte masks */
+#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
+#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
+#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
+
+
+/**
+ \brief Enable External Interrupt
+ \details Enables a device-specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+ NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+}
+
+
+/**
+ \brief Disable External Interrupt
+ \details Disables a device-specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+ NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+}
+
+
+/**
+ \brief Get Pending Interrupt
+ \details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt.
+ \param [in] IRQn Interrupt number.
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+ return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+}
+
+
+/**
+ \brief Set Pending Interrupt
+ \details Sets the pending bit of an external interrupt.
+ \param [in] IRQn Interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+ NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+}
+
+
+/**
+ \brief Clear Pending Interrupt
+ \details Clears the pending bit of an external interrupt.
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+ NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+}
+
+
+/**
+ \brief Set Interrupt Priority
+ \details Sets the priority of an interrupt.
+ \note The priority cannot be set for every core interrupt.
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ */
+__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+ if ((int32_t)(IRQn) < 0)
+ {
+ SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+ (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+ }
+ else
+ {
+ NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+ (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+ }
+}
+
+
+/**
+ \brief Get Interrupt Priority
+ \details Reads the priority of an interrupt.
+ The interrupt number can be positive to specify an external (device specific) interrupt,
+ or negative to specify an internal (core) interrupt.
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority.
+ Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+ if ((int32_t)(IRQn) < 0)
+ {
+ return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+ }
+ else
+ {
+ return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+ }
+}
+
+
+/**
+ \brief System Reset
+ \details Initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void NVIC_SystemReset(void)
+{
+ __DSB(); /* Ensure all outstanding memory accesses included
+ buffered write are completed before reset */
+ SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ SCB_AIRCR_SYSRESETREQ_Msk);
+ __DSB(); /* Ensure completion of memory access */
+
+ for(;;) /* wait until reset */
+ {
+ __NOP();
+ }
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+
+/* ################################## SysTick function ############################################ */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+ \brief Functions that configure the System.
+ @{
+ */
+
+#if (__Vendor_SysTickConfig == 0U)
+
+/**
+ \brief System Tick Configuration
+ \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+ \param [in] ticks Number of ticks between two interrupts.
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+ \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+ function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+ must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+ {
+ return (1UL); /* Reload value impossible */
+ }
+
+ SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
+ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_TICKINT_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+ return (0UL); /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM0_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/Include/core_cm0plus.h b/Include/core_cm0plus.h
new file mode 100644
index 0000000..7614450
--- /dev/null
+++ b/Include/core_cm0plus.h
@@ -0,0 +1,914 @@
+/**************************************************************************//**
+ * @file core_cm0plus.h
+ * @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File
+ * @version V4.30
+ * @date 20. October 2015
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2015 ARM LIMITED
+
+ All rights reserved.
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+ - Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ - Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+ - Neither the name of ARM nor the names of its contributors may be used
+ to endorse or promote products derived from this software without
+ specific prior written permission.
+ *
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ POSSIBILITY OF SUCH DAMAGE.
+ ---------------------------------------------------------------------------*/
+
+
+#if defined ( __ICCARM__ )
+ #pragma system_include /* treat file as system include file for MISRA check */
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #pragma clang system_header /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CM0PLUS_H_GENERIC
+#define __CORE_CM0PLUS_H_GENERIC
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+ \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
+ CMSIS violates the following MISRA-C:2004 rules:
+
+ \li Required Rule 8.5, object/function definition in header file.<br>
+ Function definitions in header files are used to allow 'inlining'.
+
+ \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+ Unions are used for effective representation of core registers.
+
+ \li Advisory Rule 19.7, Function-like macro defined.<br>
+ Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ * CMSIS definitions
+ ******************************************************************************/
+/**
+ \ingroup Cortex-M0+
+ @{
+ */
+
+/* CMSIS CM0+ definitions */
+#define __CM0PLUS_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS HAL main version */
+#define __CM0PLUS_CMSIS_VERSION_SUB (0x1EU) /*!< [15:0] CMSIS HAL sub version */
+#define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16U) | \
+ __CM0PLUS_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
+
+#define __CORTEX_M (0x00U) /*!< Cortex-M Core */
+
+
+#if defined ( __CC_ARM )
+ #define __ASM __asm /*!< asm keyword for ARM Compiler */
+ #define __INLINE __inline /*!< inline keyword for ARM Compiler */
+ #define __STATIC_INLINE static __inline
+
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #define __ASM __asm /*!< asm keyword for ARM Compiler */
+ #define __INLINE __inline /*!< inline keyword for ARM Compiler */
+ #define __STATIC_INLINE static __inline
+
+#elif defined ( __GNUC__ )
+ #define __ASM __asm /*!< asm keyword for GNU Compiler */
+ #define __INLINE inline /*!< inline keyword for GNU Compiler */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __ICCARM__ )
+ #define __ASM __asm /*!< asm keyword for IAR Compiler */
+ #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __TMS470__ )
+ #define __ASM __asm /*!< asm keyword for TI CCS Compiler */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __TASKING__ )
+ #define __ASM __asm /*!< asm keyword for TASKING Compiler */
+ #define __INLINE inline /*!< inline keyword for TASKING Compiler */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __CSMC__ )
+ #define __packed
+ #define __ASM _asm /*!< asm keyword for COSMIC Compiler */
+ #define __INLINE inline /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */
+ #define __STATIC_INLINE static inline
+
+#else
+ #error Unknown compiler
+#endif
+
+/** __FPU_USED indicates whether an FPU is used or not.
+ This core does not support an FPU at all
+*/
+#define __FPU_USED 0U
+
+#if defined ( __CC_ARM )
+ #if defined __TARGET_FPU_VFP
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #if defined __ARM_PCS_VFP
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __GNUC__ )
+ #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __ICCARM__ )
+ #if defined __ARMVFP__
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __TMS470__ )
+ #if defined __TI_VFP_SUPPORT__
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __TASKING__ )
+ #if defined __FPU_VFP__
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __CSMC__ )
+ #if ( __CSMC__ & 0x400U)
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#endif
+
+#include "core_cmInstr.h" /* Core Instruction Access */
+#include "core_cmFunc.h" /* Core Function Access */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM0PLUS_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM0PLUS_H_DEPENDANT
+#define __CORE_CM0PLUS_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+ #ifndef __CM0PLUS_REV
+ #define __CM0PLUS_REV 0x0000U
+ #warning "__CM0PLUS_REV not defined in device header file; using default!"
+ #endif
+
+ #ifndef __MPU_PRESENT
+ #define __MPU_PRESENT 0U
+ #warning "__MPU_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __VTOR_PRESENT
+ #define __VTOR_PRESENT 0U
+ #warning "__VTOR_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __NVIC_PRIO_BITS
+ #define __NVIC_PRIO_BITS 2U
+ #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+ #endif
+
+ #ifndef __Vendor_SysTickConfig
+ #define __Vendor_SysTickConfig 0U
+ #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+ #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+ \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+ <strong>IO Type Qualifiers</strong> are used
+ \li to specify the access to peripheral variables.
+ \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+ #define __I volatile /*!< Defines 'read only' permissions */
+#else
+ #define __I volatile const /*!< Defines 'read only' permissions */
+#endif
+#define __O volatile /*!< Defines 'write only' permissions */
+#define __IO volatile /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define __IM volatile const /*! Defines 'read only' structure member permissions */
+#define __OM volatile /*! Defines 'write only' structure member permissions */
+#define __IOM volatile /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group Cortex-M0+ */
+
+
+
+/*******************************************************************************
+ * Register Abstraction
+ Core Register contain:
+ - Core Register
+ - Core NVIC Register
+ - Core SCB Register
+ - Core SysTick Register
+ - Core MPU Register
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_core_register Defines and Type Definitions
+ \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CORE Status and Control Registers
+ \brief Core Register type definitions.
+ @{
+ */
+
+/**
+ \brief Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos 31U /*!< APSR: N Position */
+#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
+
+#define APSR_Z_Pos 30U /*!< APSR: Z Position */
+#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
+
+#define APSR_C_Pos 29U /*!< APSR: C Position */
+#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
+
+#define APSR_V_Pos 28U /*!< APSR: V Position */
+#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
+
+
+/**
+ \brief Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
+ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
+ uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos 31U /*!< xPSR: N Position */
+#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
+#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos 29U /*!< xPSR: C Position */
+#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos 28U /*!< xPSR: V Position */
+#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
+
+#define xPSR_T_Pos 24U /*!< xPSR: T Position */
+#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
+
+#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
+ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
+ uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
+ \brief Type definitions for the NVIC Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+ __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
+ uint32_t RESERVED0[31U];
+ __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
+ uint32_t RSERVED1[31U];
+ __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
+ uint32_t RESERVED2[31U];
+ __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
+ uint32_t RESERVED3[31U];
+ uint32_t RESERVED4[64U];
+ __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
+} NVIC_Type;
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCB System Control Block (SCB)
+ \brief Type definitions for the System Control Block Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+ __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
+ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
+#if (__VTOR_PRESENT == 1U)
+ __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
+#else
+ uint32_t RESERVED0;
+#endif
+ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
+ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
+ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
+ uint32_t RESERVED1;
+ __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
+ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
+
+#if (__VTOR_PRESENT == 1U)
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos 8U /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
+#endif
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)
+ \brief Type definitions for the System Timer Registers.
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
+ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
+ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
+ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+#if (__MPU_PRESENT == 1U)
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_MPU Memory Protection Unit (MPU)
+ \brief Type definitions for the Memory Protection Unit (MPU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+ __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
+ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
+ __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
+} MPU_Type;
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register Definitions */
+#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
+ \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
+ Therefore they are not covered by the Cortex-M0+ header file.
+ @{
+ */
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_bitfield Core register bit field macros
+ \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+ @{
+ */
+
+/**
+ \brief Mask and shift a bit field value for use in a register bit range.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of the bit field.
+ \return Masked and shifted value.
+*/
+#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk)
+
+/**
+ \brief Mask and shift a register value to extract a bit filed value.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of register.
+ \return Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_base Core Definitions
+ \brief Definitions for base addresses, unions, and structures.
+ @{
+ */
+
+/* Memory mapping of Cortex-M0+ Hardware */
+#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
+#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
+#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
+#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
+
+#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
+#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
+#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
+
+#if (__MPU_PRESENT == 1U)
+ #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
+ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ * Hardware Abstraction Layer
+ Core Function Interface contains:
+ - Core NVIC Functions
+ - Core SysTick Functions
+ - Core Register Access Functions
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ########################## NVIC functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+ \brief Functions that manage interrupts and exceptions via the NVIC.
+ @{
+ */
+
+/* Interrupt Priorities are WORD accessible only under ARMv6M */
+/* The following MACROS handle generation of the register offset and byte masks */
+#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
+#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
+#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
+
+
+/**
+ \brief Enable External Interrupt
+ \details Enables a device-specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+ NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+}
+
+
+/**
+ \brief Disable External Interrupt
+ \details Disables a device-specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+ NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+}
+
+
+/**
+ \brief Get Pending Interrupt
+ \details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt.
+ \param [in] IRQn Interrupt number.
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+ return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+}
+
+
+/**
+ \brief Set Pending Interrupt
+ \details Sets the pending bit of an external interrupt.
+ \param [in] IRQn Interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+ NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+}
+
+
+/**
+ \brief Clear Pending Interrupt
+ \details Clears the pending bit of an external interrupt.
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+ NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+}
+
+
+/**
+ \brief Set Interrupt Priority
+ \details Sets the priority of an interrupt.
+ \note The priority cannot be set for every core interrupt.
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ */
+__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+ if ((int32_t)(IRQn) < 0)
+ {
+ SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+ (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+ }
+ else
+ {
+ NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+ (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+ }
+}
+
+
+/**
+ \brief Get Interrupt Priority
+ \details Reads the priority of an interrupt.
+ The interrupt number can be positive to specify an external (device specific) interrupt,
+ or negative to specify an internal (core) interrupt.
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority.
+ Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+ if ((int32_t)(IRQn) < 0)
+ {
+ return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+ }
+ else
+ {
+ return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+ }
+}
+
+
+/**
+ \brief System Reset
+ \details Initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void NVIC_SystemReset(void)
+{
+ __DSB(); /* Ensure all outstanding memory accesses included
+ buffered write are completed before reset */
+ SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ SCB_AIRCR_SYSRESETREQ_Msk);
+ __DSB(); /* Ensure completion of memory access */
+
+ for(;;) /* wait until reset */
+ {
+ __NOP();
+ }
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+
+/* ################################## SysTick function ############################################ */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+ \brief Functions that configure the System.
+ @{
+ */
+
+#if (__Vendor_SysTickConfig == 0U)
+
+/**
+ \brief System Tick Configuration
+ \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+ \param [in] ticks Number of ticks between two interrupts.
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+ \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+ function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+ must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+ {
+ return (1UL); /* Reload value impossible */
+ }
+
+ SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
+ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_TICKINT_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+ return (0UL); /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM0PLUS_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/Include/core_cm3.h b/Include/core_cm3.h
new file mode 100644
index 0000000..34ed84c
--- /dev/null
+++ b/Include/core_cm3.h
@@ -0,0 +1,1763 @@
+/**************************************************************************//**
+ * @file core_cm3.h
+ * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File
+ * @version V4.30
+ * @date 20. October 2015
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2015 ARM LIMITED
+
+ All rights reserved.
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+ - Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ - Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+ - Neither the name of ARM nor the names of its contributors may be used
+ to endorse or promote products derived from this software without
+ specific prior written permission.
+ *
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ POSSIBILITY OF SUCH DAMAGE.
+ ---------------------------------------------------------------------------*/
+
+
+#if defined ( __ICCARM__ )
+ #pragma system_include /* treat file as system include file for MISRA check */
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #pragma clang system_header /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CM3_H_GENERIC
+#define __CORE_CM3_H_GENERIC
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+ \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
+ CMSIS violates the following MISRA-C:2004 rules:
+
+ \li Required Rule 8.5, object/function definition in header file.<br>
+ Function definitions in header files are used to allow 'inlining'.
+
+ \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+ Unions are used for effective representation of core registers.
+
+ \li Advisory Rule 19.7, Function-like macro defined.<br>
+ Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ * CMSIS definitions
+ ******************************************************************************/
+/**
+ \ingroup Cortex_M3
+ @{
+ */
+
+/* CMSIS CM3 definitions */
+#define __CM3_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS HAL main version */
+#define __CM3_CMSIS_VERSION_SUB (0x1EU) /*!< [15:0] CMSIS HAL sub version */
+#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16U) | \
+ __CM3_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
+
+#define __CORTEX_M (0x03U) /*!< Cortex-M Core */
+
+
+#if defined ( __CC_ARM )
+ #define __ASM __asm /*!< asm keyword for ARM Compiler */
+ #define __INLINE __inline /*!< inline keyword for ARM Compiler */
+ #define __STATIC_INLINE static __inline
+
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #define __ASM __asm /*!< asm keyword for ARM Compiler */
+ #define __INLINE __inline /*!< inline keyword for ARM Compiler */
+ #define __STATIC_INLINE static __inline
+
+#elif defined ( __GNUC__ )
+ #define __ASM __asm /*!< asm keyword for GNU Compiler */
+ #define __INLINE inline /*!< inline keyword for GNU Compiler */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __ICCARM__ )
+ #define __ASM __asm /*!< asm keyword for IAR Compiler */
+ #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __TMS470__ )
+ #define __ASM __asm /*!< asm keyword for TI CCS Compiler */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __TASKING__ )
+ #define __ASM __asm /*!< asm keyword for TASKING Compiler */
+ #define __INLINE inline /*!< inline keyword for TASKING Compiler */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __CSMC__ )
+ #define __packed
+ #define __ASM _asm /*!< asm keyword for COSMIC Compiler */
+ #define __INLINE inline /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */
+ #define __STATIC_INLINE static inline
+
+#else
+ #error Unknown compiler
+#endif
+
+/** __FPU_USED indicates whether an FPU is used or not.
+ This core does not support an FPU at all
+*/
+#define __FPU_USED 0U
+
+#if defined ( __CC_ARM )
+ #if defined __TARGET_FPU_VFP
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #if defined __ARM_PCS_VFP
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __GNUC__ )
+ #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __ICCARM__ )
+ #if defined __ARMVFP__
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __TMS470__ )
+ #if defined __TI_VFP_SUPPORT__
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __TASKING__ )
+ #if defined __FPU_VFP__
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __CSMC__ )
+ #if ( __CSMC__ & 0x400U)
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#endif
+
+#include "core_cmInstr.h" /* Core Instruction Access */
+#include "core_cmFunc.h" /* Core Function Access */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM3_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM3_H_DEPENDANT
+#define __CORE_CM3_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+ #ifndef __CM3_REV
+ #define __CM3_REV 0x0200U
+ #warning "__CM3_REV not defined in device header file; using default!"
+ #endif
+
+ #ifndef __MPU_PRESENT
+ #define __MPU_PRESENT 0U
+ #warning "__MPU_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __NVIC_PRIO_BITS
+ #define __NVIC_PRIO_BITS 4U
+ #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+ #endif
+
+ #ifndef __Vendor_SysTickConfig
+ #define __Vendor_SysTickConfig 0U
+ #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+ #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+ \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+ <strong>IO Type Qualifiers</strong> are used
+ \li to specify the access to peripheral variables.
+ \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+ #define __I volatile /*!< Defines 'read only' permissions */
+#else
+ #define __I volatile const /*!< Defines 'read only' permissions */
+#endif
+#define __O volatile /*!< Defines 'write only' permissions */
+#define __IO volatile /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define __IM volatile const /*! Defines 'read only' structure member permissions */
+#define __OM volatile /*! Defines 'write only' structure member permissions */
+#define __IOM volatile /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group Cortex_M3 */
+
+
+
+/*******************************************************************************
+ * Register Abstraction
+ Core Register contain:
+ - Core Register
+ - Core NVIC Register
+ - Core SCB Register
+ - Core SysTick Register
+ - Core Debug Register
+ - Core MPU Register
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_core_register Defines and Type Definitions
+ \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CORE Status and Control Registers
+ \brief Core Register type definitions.
+ @{
+ */
+
+/**
+ \brief Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos 31U /*!< APSR: N Position */
+#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
+
+#define APSR_Z_Pos 30U /*!< APSR: Z Position */
+#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
+
+#define APSR_C_Pos 29U /*!< APSR: C Position */
+#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
+
+#define APSR_V_Pos 28U /*!< APSR: V Position */
+#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
+
+#define APSR_Q_Pos 27U /*!< APSR: Q Position */
+#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */
+
+
+/**
+ \brief Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
+ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
+ uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos 31U /*!< xPSR: N Position */
+#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
+#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos 29U /*!< xPSR: C Position */
+#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos 28U /*!< xPSR: V Position */
+#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
+
+#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */
+#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */
+
+#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */
+#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */
+
+#define xPSR_T_Pos 24U /*!< xPSR: T Position */
+#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
+
+#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
+ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
+ uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
+ \brief Type definitions for the NVIC Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+ __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
+ uint32_t RESERVED0[24U];
+ __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
+ uint32_t RSERVED1[24U];
+ __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
+ uint32_t RESERVED2[24U];
+ __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
+ uint32_t RESERVED3[24U];
+ __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
+ uint32_t RESERVED4[56U];
+ __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
+ uint32_t RESERVED5[644U];
+ __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
+} NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCB System Control Block (SCB)
+ \brief Type definitions for the System Control Block Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+ __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
+ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
+ __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
+ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
+ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
+ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
+ __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
+ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
+ __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
+ __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
+ __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
+ __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
+ __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
+ __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
+ __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
+ __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
+ __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
+ __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
+ __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
+ uint32_t RESERVED0[5U];
+ __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#if (__CM3_REV < 0x0201U) /* core r2p1 */
+#define SCB_VTOR_TBLBASE_Pos 29U /*!< SCB VTOR: TBLBASE Position */
+#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */
+
+#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
+#else
+#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
+#endif
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */
+#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
+
+#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */
+#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Register Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* SCB Hard Fault Status Register Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+ \brief Type definitions for the System Control and ID Register not in the SCB
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+ uint32_t RESERVED0[1U];
+ __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
+#if ((defined __CM3_REV) && (__CM3_REV >= 0x200U))
+ __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
+#else
+ uint32_t RESERVED1[1U];
+#endif
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */
+
+/* Auxiliary Control Register Definitions */
+
+#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */
+#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */
+
+#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */
+#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */
+
+#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */
+#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)
+ \brief Type definitions for the System Timer Registers.
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
+ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
+ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
+ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
+ \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+ __OM union
+ {
+ __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
+ __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
+ __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
+ } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
+ uint32_t RESERVED0[864U];
+ __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
+ uint32_t RESERVED1[15U];
+ __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
+ uint32_t RESERVED2[15U];
+ __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
+ uint32_t RESERVED3[29U];
+ __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */
+ __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */
+ __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */
+ uint32_t RESERVED4[43U];
+ __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
+ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
+ uint32_t RESERVED5[6U];
+ __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
+ __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
+ __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
+ __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
+ __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
+ __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
+ __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
+ __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
+ __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
+ __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
+ __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
+ __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
+} ITM_Type;
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */
+#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */
+
+#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Integration Write Register Definitions */
+#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */
+#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */
+
+/* ITM Integration Read Register Definitions */
+#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */
+#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */
+
+/* ITM Integration Mode Control Register Definitions */
+#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */
+#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
+ \brief Type definitions for the Data Watchpoint and Trace (DWT)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
+ __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
+ __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
+ __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
+ __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
+ __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
+ __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
+ __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
+ __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
+ __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */
+ __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
+ uint32_t RESERVED0[1U];
+ __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
+ __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */
+ __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
+ uint32_t RESERVED1[1U];
+ __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
+ __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */
+ __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
+ uint32_t RESERVED2[1U];
+ __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
+ __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */
+ __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Mask Register Definitions */
+#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */
+#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */
+#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */
+
+#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */
+#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */
+#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */
+
+#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */
+#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */
+
+#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */
+#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */
+
+#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */
+#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */
+
+#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */
+#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_TPI Trace Port Interface (TPI)
+ \brief Type definitions for the Trace Port Interface (TPI)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+ __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
+ __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
+ uint32_t RESERVED0[2U];
+ __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
+ uint32_t RESERVED1[55U];
+ __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
+ uint32_t RESERVED2[131U];
+ __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
+ __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
+ __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
+ uint32_t RESERVED3[759U];
+ __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */
+ __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
+ __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
+ uint32_t RESERVED4[1U];
+ __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
+ __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
+ __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
+ uint32_t RESERVED5[39U];
+ __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
+ __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
+ uint32_t RESERVED7[8U];
+ __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
+ __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration ETM Data Register Definitions (FIFO0) */
+#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */
+#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
+
+#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */
+#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
+
+#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */
+#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
+
+#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */
+#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
+
+#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */
+#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
+
+#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */
+#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
+
+#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */
+#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */
+
+/* TPI ITATBCTR2 Register Definitions */
+#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */
+#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */
+
+/* TPI Integration ITM Data Register Definitions (FIFO1) */
+#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */
+#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
+
+#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */
+#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
+
+#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */
+#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
+
+#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */
+#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
+
+#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */
+#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
+
+#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */
+#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
+
+#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */
+#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */
+
+/* TPI ITATBCTR0 Register Definitions */
+#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */
+#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */
+#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
+
+#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */
+#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
+
+#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if (__MPU_PRESENT == 1U)
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_MPU Memory Protection Unit (MPU)
+ \brief Type definitions for the Memory Protection Unit (MPU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+ __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
+ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
+ __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
+ __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */
+ __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */
+ __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */
+ __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */
+ __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */
+ __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */
+} MPU_Type;
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register Definitions */
+#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
+ \brief Type definitions for the Core Debug Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+ __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
+ __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
+ __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
+ __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register Definitions */
+#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register Definitions */
+#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register Definitions */
+#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_bitfield Core register bit field macros
+ \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+ @{
+ */
+
+/**
+ \brief Mask and shift a bit field value for use in a register bit range.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of the bit field.
+ \return Masked and shifted value.
+*/
+#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk)
+
+/**
+ \brief Mask and shift a register value to extract a bit filed value.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of register.
+ \return Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_base Core Definitions
+ \brief Definitions for base addresses, unions, and structures.
+ @{
+ */
+
+/* Memory mapping of Cortex-M3 Hardware */
+#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
+#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
+#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
+#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
+#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
+#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
+#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
+#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
+
+#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
+#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
+#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
+#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
+#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
+#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
+#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
+#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
+
+#if (__MPU_PRESENT == 1U)
+ #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
+ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ * Hardware Abstraction Layer
+ Core Function Interface contains:
+ - Core NVIC Functions
+ - Core SysTick Functions
+ - Core Debug Functions
+ - Core Register Access Functions
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ########################## NVIC functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+ \brief Functions that manage interrupts and exceptions via the NVIC.
+ @{
+ */
+
+/**
+ \brief Set Priority Grouping
+ \details Sets the priority grouping field using the required unlock sequence.
+ The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+ Only values from 0..7 are used.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Priority grouping field.
+ */
+__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+ uint32_t reg_value;
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+
+ reg_value = SCB->AIRCR; /* read old register configuration */
+ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
+ reg_value = (reg_value |
+ ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */
+ SCB->AIRCR = reg_value;
+}
+
+
+/**
+ \brief Get Priority Grouping
+ \details Reads the priority grouping field from the NVIC Interrupt Controller.
+ \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
+{
+ return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+ \brief Enable External Interrupt
+ \details Enables a device-specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+ NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+}
+
+
+/**
+ \brief Disable External Interrupt
+ \details Disables a device-specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+ NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+}
+
+
+/**
+ \brief Get Pending Interrupt
+ \details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt.
+ \param [in] IRQn Interrupt number.
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+ return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+}
+
+
+/**
+ \brief Set Pending Interrupt
+ \details Sets the pending bit of an external interrupt.
+ \param [in] IRQn Interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+ NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+}
+
+
+/**
+ \brief Clear Pending Interrupt
+ \details Clears the pending bit of an external interrupt.
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+ NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+}
+
+
+/**
+ \brief Get Active Interrupt
+ \details Reads the active register in NVIC and returns the active bit.
+ \param [in] IRQn Interrupt number.
+ \return 0 Interrupt status is not active.
+ \return 1 Interrupt status is active.
+ */
+__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
+{
+ return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+}
+
+
+/**
+ \brief Set Interrupt Priority
+ \details Sets the priority of an interrupt.
+ \note The priority cannot be set for every core interrupt.
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ */
+__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+ if ((int32_t)(IRQn) < 0)
+ {
+ SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+ else
+ {
+ NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+}
+
+
+/**
+ \brief Get Interrupt Priority
+ \details Reads the priority of an interrupt.
+ The interrupt number can be positive to specify an external (device specific) interrupt,
+ or negative to specify an internal (core) interrupt.
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority.
+ Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+ if ((int32_t)(IRQn) < 0)
+ {
+ return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
+ }
+ else
+ {
+ return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
+ }
+}
+
+
+/**
+ \brief Encode Priority
+ \details Encodes the priority for an interrupt with the given priority group,
+ preemptive priority value, and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Used priority group.
+ \param [in] PreemptPriority Preemptive priority value (starting from 0).
+ \param [in] SubPriority Subpriority value (starting from 0).
+ \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ return (
+ ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+ ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
+ );
+}
+
+
+/**
+ \brief Decode Priority
+ \details Decodes an interrupt priority value with a given priority group to
+ preemptive priority value and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+ \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+ \param [in] PriorityGroup Used priority group.
+ \param [out] pPreemptPriority Preemptive priority value (starting from 0).
+ \param [out] pSubPriority Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+ *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
+}
+
+
+/**
+ \brief System Reset
+ \details Initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void NVIC_SystemReset(void)
+{
+ __DSB(); /* Ensure all outstanding memory accesses included
+ buffered write are completed before reset */
+ SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+ SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
+ __DSB(); /* Ensure completion of memory access */
+
+ for(;;) /* wait until reset */
+ {
+ __NOP();
+ }
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+
+/* ################################## SysTick function ############################################ */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+ \brief Functions that configure the System.
+ @{
+ */
+
+#if (__Vendor_SysTickConfig == 0U)
+
+/**
+ \brief System Tick Configuration
+ \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+ \param [in] ticks Number of ticks between two interrupts.
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+ \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+ function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+ must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+ {
+ return (1UL); /* Reload value impossible */
+ }
+
+ SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
+ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_TICKINT_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+ return (0UL); /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_core_DebugFunctions ITM Functions
+ \brief Functions that access the ITM debug interface.
+ @{
+ */
+
+extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
+#define ITM_RXBUFFER_EMPTY 0x5AA55AA5U /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
+
+
+/**
+ \brief ITM Send Character
+ \details Transmits a character via the ITM channel 0, and
+ \li Just returns when no debugger is connected that has booked the output.
+ \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+ \param [in] ch Character to transmit.
+ \returns Character to transmit.
+ */
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+ if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
+ ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
+ {
+ while (ITM->PORT[0U].u32 == 0UL)
+ {
+ __NOP();
+ }
+ ITM->PORT[0U].u8 = (uint8_t)ch;
+ }
+ return (ch);
+}
+
+
+/**
+ \brief ITM Receive Character
+ \details Inputs a character via the external variable \ref ITM_RxBuffer.
+ \return Received character.
+ \return -1 No character pending.
+ */
+__STATIC_INLINE int32_t ITM_ReceiveChar (void)
+{
+ int32_t ch = -1; /* no character available */
+
+ if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
+ {
+ ch = ITM_RxBuffer;
+ ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
+ }
+
+ return (ch);
+}
+
+
+/**
+ \brief ITM Check Character
+ \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+ \return 0 No character available.
+ \return 1 Character available.
+ */
+__STATIC_INLINE int32_t ITM_CheckChar (void)
+{
+
+ if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
+ {
+ return (0); /* no character available */
+ }
+ else
+ {
+ return (1); /* character available */
+ }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM3_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/Include/core_cm4.h b/Include/core_cm4.h
new file mode 100644
index 0000000..01cb73b
--- /dev/null
+++ b/Include/core_cm4.h
@@ -0,0 +1,1937 @@
+/**************************************************************************//**
+ * @file core_cm4.h
+ * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File
+ * @version V4.30
+ * @date 20. October 2015
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2015 ARM LIMITED
+
+ All rights reserved.
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+ - Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ - Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+ - Neither the name of ARM nor the names of its contributors may be used
+ to endorse or promote products derived from this software without
+ specific prior written permission.
+ *
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ POSSIBILITY OF SUCH DAMAGE.
+ ---------------------------------------------------------------------------*/
+
+
+#if defined ( __ICCARM__ )
+ #pragma system_include /* treat file as system include file for MISRA check */
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #pragma clang system_header /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CM4_H_GENERIC
+#define __CORE_CM4_H_GENERIC
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+ \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
+ CMSIS violates the following MISRA-C:2004 rules:
+
+ \li Required Rule 8.5, object/function definition in header file.<br>
+ Function definitions in header files are used to allow 'inlining'.
+
+ \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+ Unions are used for effective representation of core registers.
+
+ \li Advisory Rule 19.7, Function-like macro defined.<br>
+ Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ * CMSIS definitions
+ ******************************************************************************/
+/**
+ \ingroup Cortex_M4
+ @{
+ */
+
+/* CMSIS CM4 definitions */
+#define __CM4_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS HAL main version */
+#define __CM4_CMSIS_VERSION_SUB (0x1EU) /*!< [15:0] CMSIS HAL sub version */
+#define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16U) | \
+ __CM4_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
+
+#define __CORTEX_M (0x04U) /*!< Cortex-M Core */
+
+
+#if defined ( __CC_ARM )
+ #define __ASM __asm /*!< asm keyword for ARM Compiler */
+ #define __INLINE __inline /*!< inline keyword for ARM Compiler */
+ #define __STATIC_INLINE static __inline
+
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #define __ASM __asm /*!< asm keyword for ARM Compiler */
+ #define __INLINE __inline /*!< inline keyword for ARM Compiler */
+ #define __STATIC_INLINE static __inline
+
+#elif defined ( __GNUC__ )
+ #define __ASM __asm /*!< asm keyword for GNU Compiler */
+ #define __INLINE inline /*!< inline keyword for GNU Compiler */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __ICCARM__ )
+ #define __ASM __asm /*!< asm keyword for IAR Compiler */
+ #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __TMS470__ )
+ #define __ASM __asm /*!< asm keyword for TI CCS Compiler */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __TASKING__ )
+ #define __ASM __asm /*!< asm keyword for TASKING Compiler */
+ #define __INLINE inline /*!< inline keyword for TASKING Compiler */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __CSMC__ )
+ #define __packed
+ #define __ASM _asm /*!< asm keyword for COSMIC Compiler */
+ #define __INLINE inline /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */
+ #define __STATIC_INLINE static inline
+
+#else
+ #error Unknown compiler
+#endif
+
+/** __FPU_USED indicates whether an FPU is used or not.
+ For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
+*/
+#if defined ( __CC_ARM )
+ #if defined __TARGET_FPU_VFP
+ #if (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #if defined __ARM_PCS_VFP
+ #if (__FPU_PRESENT == 1)
+ #define __FPU_USED 1U
+ #else
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#elif defined ( __GNUC__ )
+ #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+ #if (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#elif defined ( __ICCARM__ )
+ #if defined __ARMVFP__
+ #if (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#elif defined ( __TMS470__ )
+ #if defined __TI_VFP_SUPPORT__
+ #if (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#elif defined ( __TASKING__ )
+ #if defined __FPU_VFP__
+ #if (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#elif defined ( __CSMC__ )
+ #if ( __CSMC__ & 0x400U)
+ #if (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#endif
+
+#include "core_cmInstr.h" /* Core Instruction Access */
+#include "core_cmFunc.h" /* Core Function Access */
+#include "core_cmSimd.h" /* Compiler specific SIMD Intrinsics */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM4_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM4_H_DEPENDANT
+#define __CORE_CM4_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+ #ifndef __CM4_REV
+ #define __CM4_REV 0x0000U
+ #warning "__CM4_REV not defined in device header file; using default!"
+ #endif
+
+ #ifndef __FPU_PRESENT
+ #define __FPU_PRESENT 0U
+ #warning "__FPU_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __MPU_PRESENT
+ #define __MPU_PRESENT 0U
+ #warning "__MPU_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __NVIC_PRIO_BITS
+ #define __NVIC_PRIO_BITS 4U
+ #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+ #endif
+
+ #ifndef __Vendor_SysTickConfig
+ #define __Vendor_SysTickConfig 0U
+ #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+ #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+ \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+ <strong>IO Type Qualifiers</strong> are used
+ \li to specify the access to peripheral variables.
+ \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+ #define __I volatile /*!< Defines 'read only' permissions */
+#else
+ #define __I volatile const /*!< Defines 'read only' permissions */
+#endif
+#define __O volatile /*!< Defines 'write only' permissions */
+#define __IO volatile /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define __IM volatile const /*! Defines 'read only' structure member permissions */
+#define __OM volatile /*! Defines 'write only' structure member permissions */
+#define __IOM volatile /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group Cortex_M4 */
+
+
+
+/*******************************************************************************
+ * Register Abstraction
+ Core Register contain:
+ - Core Register
+ - Core NVIC Register
+ - Core SCB Register
+ - Core SysTick Register
+ - Core Debug Register
+ - Core MPU Register
+ - Core FPU Register
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_core_register Defines and Type Definitions
+ \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CORE Status and Control Registers
+ \brief Core Register type definitions.
+ @{
+ */
+
+/**
+ \brief Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos 31U /*!< APSR: N Position */
+#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
+
+#define APSR_Z_Pos 30U /*!< APSR: Z Position */
+#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
+
+#define APSR_C_Pos 29U /*!< APSR: C Position */
+#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
+
+#define APSR_V_Pos 28U /*!< APSR: V Position */
+#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
+
+#define APSR_Q_Pos 27U /*!< APSR: Q Position */
+#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */
+
+#define APSR_GE_Pos 16U /*!< APSR: GE Position */
+#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */
+
+
+/**
+ \brief Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
+ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
+ uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos 31U /*!< xPSR: N Position */
+#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
+#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos 29U /*!< xPSR: C Position */
+#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos 28U /*!< xPSR: V Position */
+#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
+
+#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */
+#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */
+
+#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */
+#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */
+
+#define xPSR_T_Pos 24U /*!< xPSR: T Position */
+#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
+
+#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */
+#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */
+
+#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
+ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
+ uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
+ uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */
+#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */
+
+#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
+ \brief Type definitions for the NVIC Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+ __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
+ uint32_t RESERVED0[24U];
+ __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
+ uint32_t RSERVED1[24U];
+ __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
+ uint32_t RESERVED2[24U];
+ __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
+ uint32_t RESERVED3[24U];
+ __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
+ uint32_t RESERVED4[56U];
+ __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
+ uint32_t RESERVED5[644U];
+ __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
+} NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCB System Control Block (SCB)
+ \brief Type definitions for the System Control Block Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+ __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
+ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
+ __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
+ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
+ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
+ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
+ __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
+ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
+ __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
+ __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
+ __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
+ __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
+ __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
+ __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
+ __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
+ __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
+ __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
+ __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
+ __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
+ uint32_t RESERVED0[5U];
+ __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */
+#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
+
+#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */
+#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Register Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* SCB Hard Fault Status Register Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+ \brief Type definitions for the System Control and ID Register not in the SCB
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+ uint32_t RESERVED0[1U];
+ __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
+ __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */
+
+/* Auxiliary Control Register Definitions */
+#define SCnSCB_ACTLR_DISOOFP_Pos 9U /*!< ACTLR: DISOOFP Position */
+#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */
+
+#define SCnSCB_ACTLR_DISFPCA_Pos 8U /*!< ACTLR: DISFPCA Position */
+#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */
+
+#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */
+#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */
+
+#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */
+#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */
+
+#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */
+#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)
+ \brief Type definitions for the System Timer Registers.
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
+ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
+ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
+ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
+ \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+ __OM union
+ {
+ __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
+ __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
+ __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
+ } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
+ uint32_t RESERVED0[864U];
+ __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
+ uint32_t RESERVED1[15U];
+ __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
+ uint32_t RESERVED2[15U];
+ __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
+ uint32_t RESERVED3[29U];
+ __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */
+ __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */
+ __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */
+ uint32_t RESERVED4[43U];
+ __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
+ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
+ uint32_t RESERVED5[6U];
+ __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
+ __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
+ __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
+ __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
+ __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
+ __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
+ __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
+ __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
+ __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
+ __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
+ __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
+ __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
+} ITM_Type;
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */
+#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */
+
+#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Integration Write Register Definitions */
+#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */
+#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */
+
+/* ITM Integration Read Register Definitions */
+#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */
+#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */
+
+/* ITM Integration Mode Control Register Definitions */
+#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */
+#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
+ \brief Type definitions for the Data Watchpoint and Trace (DWT)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
+ __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
+ __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
+ __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
+ __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
+ __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
+ __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
+ __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
+ __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
+ __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */
+ __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
+ uint32_t RESERVED0[1U];
+ __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
+ __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */
+ __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
+ uint32_t RESERVED1[1U];
+ __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
+ __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */
+ __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
+ uint32_t RESERVED2[1U];
+ __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
+ __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */
+ __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Mask Register Definitions */
+#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */
+#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */
+#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */
+
+#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */
+#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */
+#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */
+
+#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */
+#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */
+
+#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */
+#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */
+
+#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */
+#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */
+
+#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */
+#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_TPI Trace Port Interface (TPI)
+ \brief Type definitions for the Trace Port Interface (TPI)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+ __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
+ __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
+ uint32_t RESERVED0[2U];
+ __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
+ uint32_t RESERVED1[55U];
+ __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
+ uint32_t RESERVED2[131U];
+ __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
+ __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
+ __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
+ uint32_t RESERVED3[759U];
+ __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */
+ __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
+ __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
+ uint32_t RESERVED4[1U];
+ __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
+ __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
+ __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
+ uint32_t RESERVED5[39U];
+ __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
+ __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
+ uint32_t RESERVED7[8U];
+ __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
+ __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration ETM Data Register Definitions (FIFO0) */
+#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */
+#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
+
+#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */
+#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
+
+#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */
+#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
+
+#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */
+#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
+
+#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */
+#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
+
+#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */
+#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
+
+#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */
+#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */
+
+/* TPI ITATBCTR2 Register Definitions */
+#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */
+#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */
+
+/* TPI Integration ITM Data Register Definitions (FIFO1) */
+#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */
+#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
+
+#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */
+#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
+
+#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */
+#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
+
+#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */
+#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
+
+#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */
+#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
+
+#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */
+#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
+
+#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */
+#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */
+
+/* TPI ITATBCTR0 Register Definitions */
+#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */
+#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */
+#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
+
+#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */
+#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
+
+#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if (__MPU_PRESENT == 1U)
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_MPU Memory Protection Unit (MPU)
+ \brief Type definitions for the Memory Protection Unit (MPU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+ __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
+ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
+ __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
+ __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */
+ __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */
+ __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */
+ __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */
+ __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */
+ __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */
+} MPU_Type;
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register Definitions */
+#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+#if (__FPU_PRESENT == 1U)
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_FPU Floating Point Unit (FPU)
+ \brief Type definitions for the Floating Point Unit (FPU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Floating Point Unit (FPU).
+ */
+typedef struct
+{
+ uint32_t RESERVED0[1U];
+ __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */
+ __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */
+ __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */
+ __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */
+ __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */
+} FPU_Type;
+
+/* Floating-Point Context Control Register Definitions */
+#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */
+#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */
+
+#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */
+#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */
+
+#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */
+#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */
+
+#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */
+#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */
+
+#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */
+#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */
+
+#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */
+#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */
+
+#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */
+#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */
+
+#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */
+#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */
+
+#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */
+#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */
+
+/* Floating-Point Context Address Register Definitions */
+#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */
+#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */
+
+/* Floating-Point Default Status Control Register Definitions */
+#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */
+#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */
+
+#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */
+#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */
+
+#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */
+#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */
+
+#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */
+#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */
+
+/* Media and FP Feature Register 0 Definitions */
+#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */
+#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */
+
+#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */
+#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */
+
+#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */
+#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */
+
+#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */
+#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */
+
+#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */
+#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */
+
+#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */
+#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */
+
+#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */
+#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */
+
+#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */
+#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */
+
+/* Media and FP Feature Register 1 Definitions */
+#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */
+#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */
+
+#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */
+#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */
+
+#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */
+#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */
+
+#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */
+#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */
+
+/*@} end of group CMSIS_FPU */
+#endif
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
+ \brief Type definitions for the Core Debug Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+ __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
+ __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
+ __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
+ __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register Definitions */
+#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register Definitions */
+#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register Definitions */
+#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_bitfield Core register bit field macros
+ \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+ @{
+ */
+
+/**
+ \brief Mask and shift a bit field value for use in a register bit range.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of the bit field.
+ \return Masked and shifted value.
+*/
+#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk)
+
+/**
+ \brief Mask and shift a register value to extract a bit filed value.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of register.
+ \return Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_base Core Definitions
+ \brief Definitions for base addresses, unions, and structures.
+ @{
+ */
+
+/* Memory mapping of Cortex-M4 Hardware */
+#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
+#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
+#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
+#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
+#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
+#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
+#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
+#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
+
+#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
+#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
+#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
+#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
+#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
+#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
+#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
+#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
+
+#if (__MPU_PRESENT == 1U)
+ #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
+ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
+#endif
+
+#if (__FPU_PRESENT == 1U)
+ #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */
+ #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ * Hardware Abstraction Layer
+ Core Function Interface contains:
+ - Core NVIC Functions
+ - Core SysTick Functions
+ - Core Debug Functions
+ - Core Register Access Functions
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ########################## NVIC functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+ \brief Functions that manage interrupts and exceptions via the NVIC.
+ @{
+ */
+
+/**
+ \brief Set Priority Grouping
+ \details Sets the priority grouping field using the required unlock sequence.
+ The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+ Only values from 0..7 are used.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Priority grouping field.
+ */
+__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+ uint32_t reg_value;
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+
+ reg_value = SCB->AIRCR; /* read old register configuration */
+ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
+ reg_value = (reg_value |
+ ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */
+ SCB->AIRCR = reg_value;
+}
+
+
+/**
+ \brief Get Priority Grouping
+ \details Reads the priority grouping field from the NVIC Interrupt Controller.
+ \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
+{
+ return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+ \brief Enable External Interrupt
+ \details Enables a device-specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+ NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+}
+
+
+/**
+ \brief Disable External Interrupt
+ \details Disables a device-specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+ NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+}
+
+
+/**
+ \brief Get Pending Interrupt
+ \details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt.
+ \param [in] IRQn Interrupt number.
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+ return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+}
+
+
+/**
+ \brief Set Pending Interrupt
+ \details Sets the pending bit of an external interrupt.
+ \param [in] IRQn Interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+ NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+}
+
+
+/**
+ \brief Clear Pending Interrupt
+ \details Clears the pending bit of an external interrupt.
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+ NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+}
+
+
+/**
+ \brief Get Active Interrupt
+ \details Reads the active register in NVIC and returns the active bit.
+ \param [in] IRQn Interrupt number.
+ \return 0 Interrupt status is not active.
+ \return 1 Interrupt status is active.
+ */
+__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
+{
+ return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+}
+
+
+/**
+ \brief Set Interrupt Priority
+ \details Sets the priority of an interrupt.
+ \note The priority cannot be set for every core interrupt.
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ */
+__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+ if ((int32_t)(IRQn) < 0)
+ {
+ SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+ else
+ {
+ NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+}
+
+
+/**
+ \brief Get Interrupt Priority
+ \details Reads the priority of an interrupt.
+ The interrupt number can be positive to specify an external (device specific) interrupt,
+ or negative to specify an internal (core) interrupt.
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority.
+ Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+ if ((int32_t)(IRQn) < 0)
+ {
+ return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
+ }
+ else
+ {
+ return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
+ }
+}
+
+
+/**
+ \brief Encode Priority
+ \details Encodes the priority for an interrupt with the given priority group,
+ preemptive priority value, and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Used priority group.
+ \param [in] PreemptPriority Preemptive priority value (starting from 0).
+ \param [in] SubPriority Subpriority value (starting from 0).
+ \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ return (
+ ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+ ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
+ );
+}
+
+
+/**
+ \brief Decode Priority
+ \details Decodes an interrupt priority value with a given priority group to
+ preemptive priority value and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+ \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+ \param [in] PriorityGroup Used priority group.
+ \param [out] pPreemptPriority Preemptive priority value (starting from 0).
+ \param [out] pSubPriority Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+ *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
+}
+
+
+/**
+ \brief System Reset
+ \details Initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void NVIC_SystemReset(void)
+{
+ __DSB(); /* Ensure all outstanding memory accesses included
+ buffered write are completed before reset */
+ SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+ SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
+ __DSB(); /* Ensure completion of memory access */
+
+ for(;;) /* wait until reset */
+ {
+ __NOP();
+ }
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+
+/* ################################## SysTick function ############################################ */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+ \brief Functions that configure the System.
+ @{
+ */
+
+#if (__Vendor_SysTickConfig == 0U)
+
+/**
+ \brief System Tick Configuration
+ \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+ \param [in] ticks Number of ticks between two interrupts.
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+ \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+ function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+ must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+ {
+ return (1UL); /* Reload value impossible */
+ }
+
+ SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
+ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_TICKINT_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+ return (0UL); /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_core_DebugFunctions ITM Functions
+ \brief Functions that access the ITM debug interface.
+ @{
+ */
+
+extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
+#define ITM_RXBUFFER_EMPTY 0x5AA55AA5U /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
+
+
+/**
+ \brief ITM Send Character
+ \details Transmits a character via the ITM channel 0, and
+ \li Just returns when no debugger is connected that has booked the output.
+ \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+ \param [in] ch Character to transmit.
+ \returns Character to transmit.
+ */
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+ if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
+ ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
+ {
+ while (ITM->PORT[0U].u32 == 0UL)
+ {
+ __NOP();
+ }
+ ITM->PORT[0U].u8 = (uint8_t)ch;
+ }
+ return (ch);
+}
+
+
+/**
+ \brief ITM Receive Character
+ \details Inputs a character via the external variable \ref ITM_RxBuffer.
+ \return Received character.
+ \return -1 No character pending.
+ */
+__STATIC_INLINE int32_t ITM_ReceiveChar (void)
+{
+ int32_t ch = -1; /* no character available */
+
+ if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
+ {
+ ch = ITM_RxBuffer;
+ ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
+ }
+
+ return (ch);
+}
+
+
+/**
+ \brief ITM Check Character
+ \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+ \return 0 No character available.
+ \return 1 Character available.
+ */
+__STATIC_INLINE int32_t ITM_CheckChar (void)
+{
+
+ if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
+ {
+ return (0); /* no character available */
+ }
+ else
+ {
+ return (1); /* character available */
+ }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM4_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/Include/core_cm7.h b/Include/core_cm7.h
new file mode 100644
index 0000000..20963c1
--- /dev/null
+++ b/Include/core_cm7.h
@@ -0,0 +1,2512 @@
+/**************************************************************************//**
+ * @file core_cm7.h
+ * @brief CMSIS Cortex-M7 Core Peripheral Access Layer Header File
+ * @version V4.30
+ * @date 20. October 2015
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2015 ARM LIMITED
+
+ All rights reserved.
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+ - Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ - Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+ - Neither the name of ARM nor the names of its contributors may be used
+ to endorse or promote products derived from this software without
+ specific prior written permission.
+ *
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ POSSIBILITY OF SUCH DAMAGE.
+ ---------------------------------------------------------------------------*/
+
+
+#if defined ( __ICCARM__ )
+ #pragma system_include /* treat file as system include file for MISRA check */
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #pragma clang system_header /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CM7_H_GENERIC
+#define __CORE_CM7_H_GENERIC
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+ \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
+ CMSIS violates the following MISRA-C:2004 rules:
+
+ \li Required Rule 8.5, object/function definition in header file.<br>
+ Function definitions in header files are used to allow 'inlining'.
+
+ \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+ Unions are used for effective representation of core registers.
+
+ \li Advisory Rule 19.7, Function-like macro defined.<br>
+ Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ * CMSIS definitions
+ ******************************************************************************/
+/**
+ \ingroup Cortex_M7
+ @{
+ */
+
+/* CMSIS CM7 definitions */
+#define __CM7_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS HAL main version */
+#define __CM7_CMSIS_VERSION_SUB (0x1EU) /*!< [15:0] CMSIS HAL sub version */
+#define __CM7_CMSIS_VERSION ((__CM7_CMSIS_VERSION_MAIN << 16U) | \
+ __CM7_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
+
+#define __CORTEX_M (0x07U) /*!< Cortex-M Core */
+
+
+#if defined ( __CC_ARM )
+ #define __ASM __asm /*!< asm keyword for ARM Compiler */
+ #define __INLINE __inline /*!< inline keyword for ARM Compiler */
+ #define __STATIC_INLINE static __inline
+
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #define __ASM __asm /*!< asm keyword for ARM Compiler */
+ #define __INLINE __inline /*!< inline keyword for ARM Compiler */
+ #define __STATIC_INLINE static __inline
+
+#elif defined ( __GNUC__ )
+ #define __ASM __asm /*!< asm keyword for GNU Compiler */
+ #define __INLINE inline /*!< inline keyword for GNU Compiler */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __ICCARM__ )
+ #define __ASM __asm /*!< asm keyword for IAR Compiler */
+ #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __TMS470__ )
+ #define __ASM __asm /*!< asm keyword for TI CCS Compiler */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __TASKING__ )
+ #define __ASM __asm /*!< asm keyword for TASKING Compiler */
+ #define __INLINE inline /*!< inline keyword for TASKING Compiler */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __CSMC__ )
+ #define __packed
+ #define __ASM _asm /*!< asm keyword for COSMIC Compiler */
+ #define __INLINE inline /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */
+ #define __STATIC_INLINE static inline
+
+#else
+ #error Unknown compiler
+#endif
+
+/** __FPU_USED indicates whether an FPU is used or not.
+ For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
+*/
+#if defined ( __CC_ARM )
+ #if defined __TARGET_FPU_VFP
+ #if (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #if defined __ARM_PCS_VFP
+ #if (__FPU_PRESENT == 1)
+ #define __FPU_USED 1U
+ #else
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#elif defined ( __GNUC__ )
+ #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+ #if (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#elif defined ( __ICCARM__ )
+ #if defined __ARMVFP__
+ #if (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#elif defined ( __TMS470__ )
+ #if defined __TI_VFP_SUPPORT__
+ #if (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#elif defined ( __TASKING__ )
+ #if defined __FPU_VFP__
+ #if (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#elif defined ( __CSMC__ )
+ #if ( __CSMC__ & 0x400U)
+ #if (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#endif
+
+#include "core_cmInstr.h" /* Core Instruction Access */
+#include "core_cmFunc.h" /* Core Function Access */
+#include "core_cmSimd.h" /* Compiler specific SIMD Intrinsics */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM7_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM7_H_DEPENDANT
+#define __CORE_CM7_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+ #ifndef __CM7_REV
+ #define __CM7_REV 0x0000U
+ #warning "__CM7_REV not defined in device header file; using default!"
+ #endif
+
+ #ifndef __FPU_PRESENT
+ #define __FPU_PRESENT 0U
+ #warning "__FPU_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __MPU_PRESENT
+ #define __MPU_PRESENT 0U
+ #warning "__MPU_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __ICACHE_PRESENT
+ #define __ICACHE_PRESENT 0U
+ #warning "__ICACHE_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __DCACHE_PRESENT
+ #define __DCACHE_PRESENT 0U
+ #warning "__DCACHE_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __DTCM_PRESENT
+ #define __DTCM_PRESENT 0U
+ #warning "__DTCM_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __NVIC_PRIO_BITS
+ #define __NVIC_PRIO_BITS 3U
+ #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+ #endif
+
+ #ifndef __Vendor_SysTickConfig
+ #define __Vendor_SysTickConfig 0U
+ #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+ #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+ \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+ <strong>IO Type Qualifiers</strong> are used
+ \li to specify the access to peripheral variables.
+ \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+ #define __I volatile /*!< Defines 'read only' permissions */
+#else
+ #define __I volatile const /*!< Defines 'read only' permissions */
+#endif
+#define __O volatile /*!< Defines 'write only' permissions */
+#define __IO volatile /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define __IM volatile const /*! Defines 'read only' structure member permissions */
+#define __OM volatile /*! Defines 'write only' structure member permissions */
+#define __IOM volatile /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group Cortex_M7 */
+
+
+
+/*******************************************************************************
+ * Register Abstraction
+ Core Register contain:
+ - Core Register
+ - Core NVIC Register
+ - Core SCB Register
+ - Core SysTick Register
+ - Core Debug Register
+ - Core MPU Register
+ - Core FPU Register
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_core_register Defines and Type Definitions
+ \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CORE Status and Control Registers
+ \brief Core Register type definitions.
+ @{
+ */
+
+/**
+ \brief Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos 31U /*!< APSR: N Position */
+#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
+
+#define APSR_Z_Pos 30U /*!< APSR: Z Position */
+#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
+
+#define APSR_C_Pos 29U /*!< APSR: C Position */
+#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
+
+#define APSR_V_Pos 28U /*!< APSR: V Position */
+#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
+
+#define APSR_Q_Pos 27U /*!< APSR: Q Position */
+#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */
+
+#define APSR_GE_Pos 16U /*!< APSR: GE Position */
+#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */
+
+
+/**
+ \brief Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
+ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
+ uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos 31U /*!< xPSR: N Position */
+#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
+#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos 29U /*!< xPSR: C Position */
+#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos 28U /*!< xPSR: V Position */
+#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
+
+#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */
+#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */
+
+#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */
+#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */
+
+#define xPSR_T_Pos 24U /*!< xPSR: T Position */
+#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
+
+#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */
+#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */
+
+#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
+ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
+ uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
+ uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */
+#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */
+
+#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
+ \brief Type definitions for the NVIC Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+ __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
+ uint32_t RESERVED0[24U];
+ __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
+ uint32_t RSERVED1[24U];
+ __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
+ uint32_t RESERVED2[24U];
+ __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
+ uint32_t RESERVED3[24U];
+ __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
+ uint32_t RESERVED4[56U];
+ __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
+ uint32_t RESERVED5[644U];
+ __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
+} NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCB System Control Block (SCB)
+ \brief Type definitions for the System Control Block Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+ __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
+ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
+ __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
+ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
+ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
+ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
+ __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
+ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
+ __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
+ __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
+ __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
+ __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
+ __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
+ __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
+ __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
+ __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
+ __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
+ __IM uint32_t ID_MFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
+ __IM uint32_t ID_ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
+ uint32_t RESERVED0[1U];
+ __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */
+ __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */
+ __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */
+ __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */
+ __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
+ uint32_t RESERVED3[93U];
+ __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */
+ uint32_t RESERVED4[15U];
+ __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */
+ __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */
+ __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 1 */
+ uint32_t RESERVED5[1U];
+ __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */
+ uint32_t RESERVED6[1U];
+ __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */
+ __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */
+ __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */
+ __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */
+ __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */
+ __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */
+ __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */
+ __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */
+ uint32_t RESERVED7[6U];
+ __IOM uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */
+ __IOM uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */
+ __IOM uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */
+ __IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */
+ __IOM uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */
+ uint32_t RESERVED8[1U];
+ __IOM uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */
+#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: Branch prediction enable bit Position */
+#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: Branch prediction enable bit Mask */
+
+#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: Instruction cache enable bit Position */
+#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: Instruction cache enable bit Mask */
+
+#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: Cache enable bit Position */
+#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: Cache enable bit Mask */
+
+#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
+
+#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */
+#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Register Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* SCB Hard Fault Status Register Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */
+
+/* SCB Cache Level ID Register Definitions */
+#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */
+#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */
+
+#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */
+#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */
+
+/* SCB Cache Type Register Definitions */
+#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */
+#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */
+
+#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */
+#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */
+
+#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */
+#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */
+
+#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */
+#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */
+
+#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */
+#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */
+
+/* SCB Cache Size ID Register Definitions */
+#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */
+#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */
+
+#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */
+#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */
+
+#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */
+#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */
+
+#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */
+#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */
+
+#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */
+#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */
+
+#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */
+#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */
+
+#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */
+#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */
+
+/* SCB Cache Size Selection Register Definitions */
+#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */
+#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */
+
+#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */
+#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */
+
+/* SCB Software Triggered Interrupt Register Definitions */
+#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */
+#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */
+
+/* SCB D-Cache Invalidate by Set-way Register Definitions */
+#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */
+#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */
+
+#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */
+#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */
+
+/* SCB D-Cache Clean by Set-way Register Definitions */
+#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */
+#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */
+
+#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */
+#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */
+
+/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */
+#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */
+#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */
+
+#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */
+#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */
+
+/* Instruction Tightly-Coupled Memory Control Register Definitions */
+#define SCB_ITCMCR_SZ_Pos 3U /*!< SCB ITCMCR: SZ Position */
+#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */
+
+#define SCB_ITCMCR_RETEN_Pos 2U /*!< SCB ITCMCR: RETEN Position */
+#define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */
+
+#define SCB_ITCMCR_RMW_Pos 1U /*!< SCB ITCMCR: RMW Position */
+#define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */
+
+#define SCB_ITCMCR_EN_Pos 0U /*!< SCB ITCMCR: EN Position */
+#define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */
+
+/* Data Tightly-Coupled Memory Control Register Definitions */
+#define SCB_DTCMCR_SZ_Pos 3U /*!< SCB DTCMCR: SZ Position */
+#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */
+
+#define SCB_DTCMCR_RETEN_Pos 2U /*!< SCB DTCMCR: RETEN Position */
+#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */
+
+#define SCB_DTCMCR_RMW_Pos 1U /*!< SCB DTCMCR: RMW Position */
+#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */
+
+#define SCB_DTCMCR_EN_Pos 0U /*!< SCB DTCMCR: EN Position */
+#define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */
+
+/* AHBP Control Register Definitions */
+#define SCB_AHBPCR_SZ_Pos 1U /*!< SCB AHBPCR: SZ Position */
+#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */
+
+#define SCB_AHBPCR_EN_Pos 0U /*!< SCB AHBPCR: EN Position */
+#define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB AHBPCR: EN Mask */
+
+/* L1 Cache Control Register Definitions */
+#define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */
+#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */
+
+#define SCB_CACR_ECCEN_Pos 1U /*!< SCB CACR: ECCEN Position */
+#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB CACR: ECCEN Mask */
+
+#define SCB_CACR_SIWT_Pos 0U /*!< SCB CACR: SIWT Position */
+#define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB CACR: SIWT Mask */
+
+/* AHBS Control Register Definitions */
+#define SCB_AHBSCR_INITCOUNT_Pos 11U /*!< SCB AHBSCR: INITCOUNT Position */
+#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */
+
+#define SCB_AHBSCR_TPRI_Pos 2U /*!< SCB AHBSCR: TPRI Position */
+#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */
+
+#define SCB_AHBSCR_CTL_Pos 0U /*!< SCB AHBSCR: CTL Position*/
+#define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBPCR_CTL_Pos*/) /*!< SCB AHBSCR: CTL Mask */
+
+/* Auxiliary Bus Fault Status Register Definitions */
+#define SCB_ABFSR_AXIMTYPE_Pos 8U /*!< SCB ABFSR: AXIMTYPE Position*/
+#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */
+
+#define SCB_ABFSR_EPPB_Pos 4U /*!< SCB ABFSR: EPPB Position*/
+#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */
+
+#define SCB_ABFSR_AXIM_Pos 3U /*!< SCB ABFSR: AXIM Position*/
+#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */
+
+#define SCB_ABFSR_AHBP_Pos 2U /*!< SCB ABFSR: AHBP Position*/
+#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */
+
+#define SCB_ABFSR_DTCM_Pos 1U /*!< SCB ABFSR: DTCM Position*/
+#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */
+
+#define SCB_ABFSR_ITCM_Pos 0U /*!< SCB ABFSR: ITCM Position*/
+#define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB ABFSR: ITCM Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+ \brief Type definitions for the System Control and ID Register not in the SCB
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+ uint32_t RESERVED0[1U];
+ __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
+ __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */
+
+/* Auxiliary Control Register Definitions */
+#define SCnSCB_ACTLR_DISITMATBFLUSH_Pos 12U /*!< ACTLR: DISITMATBFLUSH Position */
+#define SCnSCB_ACTLR_DISITMATBFLUSH_Msk (1UL << SCnSCB_ACTLR_DISITMATBFLUSH_Pos) /*!< ACTLR: DISITMATBFLUSH Mask */
+
+#define SCnSCB_ACTLR_DISRAMODE_Pos 11U /*!< ACTLR: DISRAMODE Position */
+#define SCnSCB_ACTLR_DISRAMODE_Msk (1UL << SCnSCB_ACTLR_DISRAMODE_Pos) /*!< ACTLR: DISRAMODE Mask */
+
+#define SCnSCB_ACTLR_FPEXCODIS_Pos 10U /*!< ACTLR: FPEXCODIS Position */
+#define SCnSCB_ACTLR_FPEXCODIS_Msk (1UL << SCnSCB_ACTLR_FPEXCODIS_Pos) /*!< ACTLR: FPEXCODIS Mask */
+
+#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */
+#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */
+
+#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */
+#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)
+ \brief Type definitions for the System Timer Registers.
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
+ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
+ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
+ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
+ \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+ __OM union
+ {
+ __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
+ __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
+ __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
+ } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
+ uint32_t RESERVED0[864U];
+ __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
+ uint32_t RESERVED1[15U];
+ __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
+ uint32_t RESERVED2[15U];
+ __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
+ uint32_t RESERVED3[29U];
+ __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */
+ __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */
+ __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */
+ uint32_t RESERVED4[43U];
+ __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
+ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
+ uint32_t RESERVED5[6U];
+ __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
+ __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
+ __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
+ __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
+ __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
+ __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
+ __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
+ __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
+ __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
+ __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
+ __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
+ __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
+} ITM_Type;
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */
+#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */
+
+#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Integration Write Register Definitions */
+#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */
+#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */
+
+/* ITM Integration Read Register Definitions */
+#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */
+#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */
+
+/* ITM Integration Mode Control Register Definitions */
+#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */
+#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
+ \brief Type definitions for the Data Watchpoint and Trace (DWT)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
+ __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
+ __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
+ __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
+ __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
+ __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
+ __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
+ __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
+ __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
+ __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */
+ __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
+ uint32_t RESERVED0[1U];
+ __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
+ __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */
+ __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
+ uint32_t RESERVED1[1U];
+ __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
+ __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */
+ __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
+ uint32_t RESERVED2[1U];
+ __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
+ __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */
+ __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
+ uint32_t RESERVED3[981U];
+ __OM uint32_t LAR; /*!< Offset: 0xFB0 ( W) Lock Access Register */
+ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Mask Register Definitions */
+#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */
+#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */
+#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */
+
+#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */
+#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */
+#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */
+
+#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */
+#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */
+
+#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */
+#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */
+
+#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */
+#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */
+
+#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */
+#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_TPI Trace Port Interface (TPI)
+ \brief Type definitions for the Trace Port Interface (TPI)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+ __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
+ __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
+ uint32_t RESERVED0[2U];
+ __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
+ uint32_t RESERVED1[55U];
+ __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
+ uint32_t RESERVED2[131U];
+ __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
+ __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
+ __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
+ uint32_t RESERVED3[759U];
+ __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */
+ __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
+ __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
+ uint32_t RESERVED4[1U];
+ __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
+ __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
+ __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
+ uint32_t RESERVED5[39U];
+ __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
+ __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
+ uint32_t RESERVED7[8U];
+ __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
+ __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration ETM Data Register Definitions (FIFO0) */
+#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */
+#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
+
+#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */
+#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
+
+#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */
+#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
+
+#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */
+#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
+
+#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */
+#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
+
+#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */
+#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
+
+#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */
+#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */
+
+/* TPI ITATBCTR2 Register Definitions */
+#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */
+#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */
+
+/* TPI Integration ITM Data Register Definitions (FIFO1) */
+#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */
+#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
+
+#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */
+#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
+
+#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */
+#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
+
+#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */
+#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
+
+#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */
+#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
+
+#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */
+#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
+
+#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */
+#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */
+
+/* TPI ITATBCTR0 Register Definitions */
+#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */
+#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */
+#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
+
+#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */
+#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
+
+#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if (__MPU_PRESENT == 1U)
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_MPU Memory Protection Unit (MPU)
+ \brief Type definitions for the Memory Protection Unit (MPU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+ __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
+ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
+ __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
+ __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */
+ __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */
+ __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */
+ __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */
+ __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */
+ __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */
+} MPU_Type;
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register Definitions */
+#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+#if (__FPU_PRESENT == 1U)
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_FPU Floating Point Unit (FPU)
+ \brief Type definitions for the Floating Point Unit (FPU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Floating Point Unit (FPU).
+ */
+typedef struct
+{
+ uint32_t RESERVED0[1U];
+ __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */
+ __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */
+ __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */
+ __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */
+ __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */
+ __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and FP Feature Register 2 */
+} FPU_Type;
+
+/* Floating-Point Context Control Register Definitions */
+#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */
+#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */
+
+#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */
+#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */
+
+#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */
+#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */
+
+#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */
+#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */
+
+#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */
+#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */
+
+#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */
+#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */
+
+#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */
+#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */
+
+#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */
+#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */
+
+#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */
+#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */
+
+/* Floating-Point Context Address Register Definitions */
+#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */
+#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */
+
+/* Floating-Point Default Status Control Register Definitions */
+#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */
+#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */
+
+#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */
+#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */
+
+#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */
+#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */
+
+#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */
+#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */
+
+/* Media and FP Feature Register 0 Definitions */
+#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */
+#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */
+
+#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */
+#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */
+
+#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */
+#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */
+
+#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */
+#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */
+
+#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */
+#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */
+
+#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */
+#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */
+
+#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */
+#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */
+
+#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */
+#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */
+
+/* Media and FP Feature Register 1 Definitions */
+#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */
+#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */
+
+#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */
+#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */
+
+#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */
+#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */
+
+#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */
+#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */
+
+/* Media and FP Feature Register 2 Definitions */
+
+/*@} end of group CMSIS_FPU */
+#endif
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
+ \brief Type definitions for the Core Debug Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+ __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
+ __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
+ __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
+ __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register Definitions */
+#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register Definitions */
+#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register Definitions */
+#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_bitfield Core register bit field macros
+ \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+ @{
+ */
+
+/**
+ \brief Mask and shift a bit field value for use in a register bit range.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of the bit field.
+ \return Masked and shifted value.
+*/
+#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk)
+
+/**
+ \brief Mask and shift a register value to extract a bit filed value.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of register.
+ \return Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_base Core Definitions
+ \brief Definitions for base addresses, unions, and structures.
+ @{
+ */
+
+/* Memory mapping of Cortex-M4 Hardware */
+#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
+#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
+#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
+#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
+#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
+#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
+#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
+#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
+
+#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
+#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
+#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
+#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
+#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
+#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
+#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
+#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
+
+#if (__MPU_PRESENT == 1U)
+ #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
+ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
+#endif
+
+#if (__FPU_PRESENT == 1U)
+ #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */
+ #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ * Hardware Abstraction Layer
+ Core Function Interface contains:
+ - Core NVIC Functions
+ - Core SysTick Functions
+ - Core Debug Functions
+ - Core Register Access Functions
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ########################## NVIC functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+ \brief Functions that manage interrupts and exceptions via the NVIC.
+ @{
+ */
+
+/**
+ \brief Set Priority Grouping
+ \details Sets the priority grouping field using the required unlock sequence.
+ The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+ Only values from 0..7 are used.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Priority grouping field.
+ */
+__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+ uint32_t reg_value;
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+
+ reg_value = SCB->AIRCR; /* read old register configuration */
+ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
+ reg_value = (reg_value |
+ ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */
+ SCB->AIRCR = reg_value;
+}
+
+
+/**
+ \brief Get Priority Grouping
+ \details Reads the priority grouping field from the NVIC Interrupt Controller.
+ \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
+{
+ return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+ \brief Enable External Interrupt
+ \details Enables a device-specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+ NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+}
+
+
+/**
+ \brief Disable External Interrupt
+ \details Disables a device-specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+ NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+}
+
+
+/**
+ \brief Get Pending Interrupt
+ \details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt.
+ \param [in] IRQn Interrupt number.
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+ return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+}
+
+
+/**
+ \brief Set Pending Interrupt
+ \details Sets the pending bit of an external interrupt.
+ \param [in] IRQn Interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+ NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+}
+
+
+/**
+ \brief Clear Pending Interrupt
+ \details Clears the pending bit of an external interrupt.
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+ NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+}
+
+
+/**
+ \brief Get Active Interrupt
+ \details Reads the active register in NVIC and returns the active bit.
+ \param [in] IRQn Interrupt number.
+ \return 0 Interrupt status is not active.
+ \return 1 Interrupt status is active.
+ */
+__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
+{
+ return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+}
+
+
+/**
+ \brief Set Interrupt Priority
+ \details Sets the priority of an interrupt.
+ \note The priority cannot be set for every core interrupt.
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ */
+__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+ if ((int32_t)(IRQn) < 0)
+ {
+ SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+ else
+ {
+ NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+}
+
+
+/**
+ \brief Get Interrupt Priority
+ \details Reads the priority of an interrupt.
+ The interrupt number can be positive to specify an external (device specific) interrupt,
+ or negative to specify an internal (core) interrupt.
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority.
+ Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+ if ((int32_t)(IRQn) < 0)
+ {
+ return(((uint32_t)SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
+ }
+ else
+ {
+ return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
+ }
+}
+
+
+/**
+ \brief Encode Priority
+ \details Encodes the priority for an interrupt with the given priority group,
+ preemptive priority value, and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Used priority group.
+ \param [in] PreemptPriority Preemptive priority value (starting from 0).
+ \param [in] SubPriority Subpriority value (starting from 0).
+ \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ return (
+ ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+ ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
+ );
+}
+
+
+/**
+ \brief Decode Priority
+ \details Decodes an interrupt priority value with a given priority group to
+ preemptive priority value and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+ \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+ \param [in] PriorityGroup Used priority group.
+ \param [out] pPreemptPriority Preemptive priority value (starting from 0).
+ \param [out] pSubPriority Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+ *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
+}
+
+
+/**
+ \brief System Reset
+ \details Initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void NVIC_SystemReset(void)
+{
+ __DSB(); /* Ensure all outstanding memory accesses included
+ buffered write are completed before reset */
+ SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+ SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
+ __DSB(); /* Ensure completion of memory access */
+
+ for(;;) /* wait until reset */
+ {
+ __NOP();
+ }
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+/* ########################## FPU functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_FpuFunctions FPU Functions
+ \brief Function that provides FPU type.
+ @{
+ */
+
+/**
+ \brief get FPU type
+ \details returns the FPU type
+ \returns
+ - \b 0: No FPU
+ - \b 1: Single precision FPU
+ - \b 2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+ uint32_t mvfr0;
+
+ mvfr0 = SCB->MVFR0;
+ if ((mvfr0 & 0x00000FF0UL) == 0x220UL)
+ {
+ return 2UL; /* Double + Single precision FPU */
+ }
+ else if ((mvfr0 & 0x00000FF0UL) == 0x020UL)
+ {
+ return 1UL; /* Single precision FPU */
+ }
+ else
+ {
+ return 0UL; /* No FPU */
+ }
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ########################## Cache functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_CacheFunctions Cache Functions
+ \brief Functions that configure Instruction and Data cache.
+ @{
+ */
+
+/* Cache Size ID Register Macros */
+#define CCSIDR_WAYS(x) (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos)
+#define CCSIDR_SETS(x) (((x) & SCB_CCSIDR_NUMSETS_Msk ) >> SCB_CCSIDR_NUMSETS_Pos )
+
+
+/**
+ \brief Enable I-Cache
+ \details Turns on I-Cache
+ */
+__STATIC_INLINE void SCB_EnableICache (void)
+{
+ #if (__ICACHE_PRESENT == 1U)
+ __DSB();
+ __ISB();
+ SCB->ICIALLU = 0UL; /* invalidate I-Cache */
+ SCB->CCR |= (uint32_t)SCB_CCR_IC_Msk; /* enable I-Cache */
+ __DSB();
+ __ISB();
+ #endif
+}
+
+
+/**
+ \brief Disable I-Cache
+ \details Turns off I-Cache
+ */
+__STATIC_INLINE void SCB_DisableICache (void)
+{
+ #if (__ICACHE_PRESENT == 1U)
+ __DSB();
+ __ISB();
+ SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk; /* disable I-Cache */
+ SCB->ICIALLU = 0UL; /* invalidate I-Cache */
+ __DSB();
+ __ISB();
+ #endif
+}
+
+
+/**
+ \brief Invalidate I-Cache
+ \details Invalidates I-Cache
+ */
+__STATIC_INLINE void SCB_InvalidateICache (void)
+{
+ #if (__ICACHE_PRESENT == 1U)
+ __DSB();
+ __ISB();
+ SCB->ICIALLU = 0UL;
+ __DSB();
+ __ISB();
+ #endif
+}
+
+
+/**
+ \brief Enable D-Cache
+ \details Turns on D-Cache
+ */
+__STATIC_INLINE void SCB_EnableDCache (void)
+{
+ #if (__DCACHE_PRESENT == 1U)
+ uint32_t ccsidr;
+ uint32_t sets;
+ uint32_t ways;
+
+ SCB->CSSELR = (0U << 1U) | 0U; /* Level 1 data cache */
+ __DSB();
+
+ ccsidr = SCB->CCSIDR;
+
+ /* invalidate D-Cache */
+ sets = (uint32_t)(CCSIDR_SETS(ccsidr));
+ do {
+ ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
+ do {
+ SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) |
+ ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) );
+ #if defined ( __CC_ARM )
+ __schedule_barrier();
+ #endif
+ } while (ways--);
+ } while(sets--);
+ __DSB();
+
+ SCB->CCR |= (uint32_t)SCB_CCR_DC_Msk; /* enable D-Cache */
+
+ __DSB();
+ __ISB();
+ #endif
+}
+
+
+/**
+ \brief Disable D-Cache
+ \details Turns off D-Cache
+ */
+__STATIC_INLINE void SCB_DisableDCache (void)
+{
+ #if (__DCACHE_PRESENT == 1U)
+ uint32_t ccsidr;
+ uint32_t sets;
+ uint32_t ways;
+
+ SCB->CSSELR = (0U << 1U) | 0U; /* Level 1 data cache */
+ __DSB();
+
+ ccsidr = SCB->CCSIDR;
+
+ SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk; /* disable D-Cache */
+
+ /* clean & invalidate D-Cache */
+ sets = (uint32_t)(CCSIDR_SETS(ccsidr));
+ do {
+ ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
+ do {
+ SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) |
+ ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) );
+ #if defined ( __CC_ARM )
+ __schedule_barrier();
+ #endif
+ } while (ways--);
+ } while(sets--);
+
+ __DSB();
+ __ISB();
+ #endif
+}
+
+
+/**
+ \brief Invalidate D-Cache
+ \details Invalidates D-Cache
+ */
+__STATIC_INLINE void SCB_InvalidateDCache (void)
+{
+ #if (__DCACHE_PRESENT == 1U)
+ uint32_t ccsidr;
+ uint32_t sets;
+ uint32_t ways;
+
+ SCB->CSSELR = (0U << 1U) | 0U; /* Level 1 data cache */
+ __DSB();
+
+ ccsidr = SCB->CCSIDR;
+
+ /* invalidate D-Cache */
+ sets = (uint32_t)(CCSIDR_SETS(ccsidr));
+ do {
+ ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
+ do {
+ SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) |
+ ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) );
+ #if defined ( __CC_ARM )
+ __schedule_barrier();
+ #endif
+ } while (ways--);
+ } while(sets--);
+
+ __DSB();
+ __ISB();
+ #endif
+}
+
+
+/**
+ \brief Clean D-Cache
+ \details Cleans D-Cache
+ */
+__STATIC_INLINE void SCB_CleanDCache (void)
+{
+ #if (__DCACHE_PRESENT == 1U)
+ uint32_t ccsidr;
+ uint32_t sets;
+ uint32_t ways;
+
+ SCB->CSSELR = (0U << 1U) | 0U; /* Level 1 data cache */
+ __DSB();
+
+ ccsidr = SCB->CCSIDR;
+
+ /* clean D-Cache */
+ sets = (uint32_t)(CCSIDR_SETS(ccsidr));
+ do {
+ ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
+ do {
+ SCB->DCCSW = (((sets << SCB_DCCSW_SET_Pos) & SCB_DCCSW_SET_Msk) |
+ ((ways << SCB_DCCSW_WAY_Pos) & SCB_DCCSW_WAY_Msk) );
+ #if defined ( __CC_ARM )
+ __schedule_barrier();
+ #endif
+ } while (ways--);
+ } while(sets--);
+
+ __DSB();
+ __ISB();
+ #endif
+}
+
+
+/**
+ \brief Clean & Invalidate D-Cache
+ \details Cleans and Invalidates D-Cache
+ */
+__STATIC_INLINE void SCB_CleanInvalidateDCache (void)
+{
+ #if (__DCACHE_PRESENT == 1U)
+ uint32_t ccsidr;
+ uint32_t sets;
+ uint32_t ways;
+
+ SCB->CSSELR = (0U << 1U) | 0U; /* Level 1 data cache */
+ __DSB();
+
+ ccsidr = SCB->CCSIDR;
+
+ /* clean & invalidate D-Cache */
+ sets = (uint32_t)(CCSIDR_SETS(ccsidr));
+ do {
+ ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
+ do {
+ SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) |
+ ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) );
+ #if defined ( __CC_ARM )
+ __schedule_barrier();
+ #endif
+ } while (ways--);
+ } while(sets--);
+
+ __DSB();
+ __ISB();
+ #endif
+}
+
+
+/**
+ \brief D-Cache Invalidate by address
+ \details Invalidates D-Cache for the given address
+ \param[in] addr address (aligned to 32-byte boundary)
+ \param[in] dsize size of memory block (in number of bytes)
+*/
+__STATIC_INLINE void SCB_InvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize)
+{
+ #if (__DCACHE_PRESENT == 1U)
+ int32_t op_size = dsize;
+ uint32_t op_addr = (uint32_t)addr;
+ int32_t linesize = 32U; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */
+
+ __DSB();
+
+ while (op_size > 0) {
+ SCB->DCIMVAC = op_addr;
+ op_addr += linesize;
+ op_size -= linesize;
+ }
+
+ __DSB();
+ __ISB();
+ #endif
+}
+
+
+/**
+ \brief D-Cache Clean by address
+ \details Cleans D-Cache for the given address
+ \param[in] addr address (aligned to 32-byte boundary)
+ \param[in] dsize size of memory block (in number of bytes)
+*/
+__STATIC_INLINE void SCB_CleanDCache_by_Addr (uint32_t *addr, int32_t dsize)
+{
+ #if (__DCACHE_PRESENT == 1)
+ int32_t op_size = dsize;
+ uint32_t op_addr = (uint32_t) addr;
+ int32_t linesize = 32U; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */
+
+ __DSB();
+
+ while (op_size > 0) {
+ SCB->DCCMVAC = op_addr;
+ op_addr += linesize;
+ op_size -= linesize;
+ }
+
+ __DSB();
+ __ISB();
+ #endif
+}
+
+
+/**
+ \brief D-Cache Clean and Invalidate by address
+ \details Cleans and invalidates D_Cache for the given address
+ \param[in] addr address (aligned to 32-byte boundary)
+ \param[in] dsize size of memory block (in number of bytes)
+*/
+__STATIC_INLINE void SCB_CleanInvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize)
+{
+ #if (__DCACHE_PRESENT == 1U)
+ int32_t op_size = dsize;
+ uint32_t op_addr = (uint32_t) addr;
+ int32_t linesize = 32U; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */
+
+ __DSB();
+
+ while (op_size > 0) {
+ SCB->DCCIMVAC = op_addr;
+ op_addr += linesize;
+ op_size -= linesize;
+ }
+
+ __DSB();
+ __ISB();
+ #endif
+}
+
+
+/*@} end of CMSIS_Core_CacheFunctions */
+
+
+
+/* ################################## SysTick function ############################################ */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+ \brief Functions that configure the System.
+ @{
+ */
+
+#if (__Vendor_SysTickConfig == 0U)
+
+/**
+ \brief System Tick Configuration
+ \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+ \param [in] ticks Number of ticks between two interrupts.
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+ \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+ function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+ must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+ {
+ return (1UL); /* Reload value impossible */
+ }
+
+ SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
+ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_TICKINT_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+ return (0UL); /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_core_DebugFunctions ITM Functions
+ \brief Functions that access the ITM debug interface.
+ @{
+ */
+
+extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
+#define ITM_RXBUFFER_EMPTY 0x5AA55AA5U /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
+
+
+/**
+ \brief ITM Send Character
+ \details Transmits a character via the ITM channel 0, and
+ \li Just returns when no debugger is connected that has booked the output.
+ \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+ \param [in] ch Character to transmit.
+ \returns Character to transmit.
+ */
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+ if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
+ ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
+ {
+ while (ITM->PORT[0U].u32 == 0UL)
+ {
+ __NOP();
+ }
+ ITM->PORT[0U].u8 = (uint8_t)ch;
+ }
+ return (ch);
+}
+
+
+/**
+ \brief ITM Receive Character
+ \details Inputs a character via the external variable \ref ITM_RxBuffer.
+ \return Received character.
+ \return -1 No character pending.
+ */
+__STATIC_INLINE int32_t ITM_ReceiveChar (void)
+{
+ int32_t ch = -1; /* no character available */
+
+ if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
+ {
+ ch = ITM_RxBuffer;
+ ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
+ }
+
+ return (ch);
+}
+
+
+/**
+ \brief ITM Check Character
+ \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+ \return 0 No character available.
+ \return 1 Character available.
+ */
+__STATIC_INLINE int32_t ITM_CheckChar (void)
+{
+
+ if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
+ {
+ return (0); /* no character available */
+ }
+ else
+ {
+ return (1); /* character available */
+ }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM7_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/Include/core_cmFunc.h b/Include/core_cmFunc.h
new file mode 100644
index 0000000..ca319a5
--- /dev/null
+++ b/Include/core_cmFunc.h
@@ -0,0 +1,87 @@
+/**************************************************************************//**
+ * @file core_cmFunc.h
+ * @brief CMSIS Cortex-M Core Function Access Header File
+ * @version V4.30
+ * @date 20. October 2015
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2015 ARM LIMITED
+
+ All rights reserved.
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+ - Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ - Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+ - Neither the name of ARM nor the names of its contributors may be used
+ to endorse or promote products derived from this software without
+ specific prior written permission.
+ *
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ POSSIBILITY OF SUCH DAMAGE.
+ ---------------------------------------------------------------------------*/
+
+
+#if defined ( __ICCARM__ )
+ #pragma system_include /* treat file as system include file for MISRA check */
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #pragma clang system_header /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CMFUNC_H
+#define __CORE_CMFUNC_H
+
+
+/* ########################### Core Function Access ########################### */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+ @{
+*/
+
+/*------------------ RealView Compiler -----------------*/
+#if defined ( __CC_ARM )
+ #include "cmsis_armcc.h"
+
+/*------------------ ARM Compiler V6 -------------------*/
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #include "cmsis_armcc_V6.h"
+
+/*------------------ GNU Compiler ----------------------*/
+#elif defined ( __GNUC__ )
+ #include "cmsis_gcc.h"
+
+/*------------------ ICC Compiler ----------------------*/
+#elif defined ( __ICCARM__ )
+ #include <cmsis_iar.h>
+
+/*------------------ TI CCS Compiler -------------------*/
+#elif defined ( __TMS470__ )
+ #include <cmsis_ccs.h>
+
+/*------------------ TASKING Compiler ------------------*/
+#elif defined ( __TASKING__ )
+ /*
+ * The CMSIS functions have been implemented as intrinsics in the compiler.
+ * Please use "carm -?i" to get an up to date list of all intrinsics,
+ * Including the CMSIS ones.
+ */
+
+/*------------------ COSMIC Compiler -------------------*/
+#elif defined ( __CSMC__ )
+ #include <cmsis_csm.h>
+
+#endif
+
+/*@} end of CMSIS_Core_RegAccFunctions */
+
+#endif /* __CORE_CMFUNC_H */
diff --git a/Include/core_cmInstr.h b/Include/core_cmInstr.h
new file mode 100644
index 0000000..a0a5064
--- /dev/null
+++ b/Include/core_cmInstr.h
@@ -0,0 +1,87 @@
+/**************************************************************************//**
+ * @file core_cmInstr.h
+ * @brief CMSIS Cortex-M Core Instruction Access Header File
+ * @version V4.30
+ * @date 20. October 2015
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2015 ARM LIMITED
+
+ All rights reserved.
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+ - Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ - Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+ - Neither the name of ARM nor the names of its contributors may be used
+ to endorse or promote products derived from this software without
+ specific prior written permission.
+ *
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ POSSIBILITY OF SUCH DAMAGE.
+ ---------------------------------------------------------------------------*/
+
+
+#if defined ( __ICCARM__ )
+ #pragma system_include /* treat file as system include file for MISRA check */
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #pragma clang system_header /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CMINSTR_H
+#define __CORE_CMINSTR_H
+
+
+/* ########################## Core Instruction Access ######################### */
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
+ Access to dedicated instructions
+ @{
+*/
+
+/*------------------ RealView Compiler -----------------*/
+#if defined ( __CC_ARM )
+ #include "cmsis_armcc.h"
+
+/*------------------ ARM Compiler V6 -------------------*/
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #include "cmsis_armcc_V6.h"
+
+/*------------------ GNU Compiler ----------------------*/
+#elif defined ( __GNUC__ )
+ #include "cmsis_gcc.h"
+
+/*------------------ ICC Compiler ----------------------*/
+#elif defined ( __ICCARM__ )
+ #include <cmsis_iar.h>
+
+/*------------------ TI CCS Compiler -------------------*/
+#elif defined ( __TMS470__ )
+ #include <cmsis_ccs.h>
+
+/*------------------ TASKING Compiler ------------------*/
+#elif defined ( __TASKING__ )
+ /*
+ * The CMSIS functions have been implemented as intrinsics in the compiler.
+ * Please use "carm -?i" to get an up to date list of all intrinsics,
+ * Including the CMSIS ones.
+ */
+
+/*------------------ COSMIC Compiler -------------------*/
+#elif defined ( __CSMC__ )
+ #include <cmsis_csm.h>
+
+#endif
+
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
+
+#endif /* __CORE_CMINSTR_H */
diff --git a/Include/core_cmSimd.h b/Include/core_cmSimd.h
new file mode 100644
index 0000000..4d76bf9
--- /dev/null
+++ b/Include/core_cmSimd.h
@@ -0,0 +1,96 @@
+/**************************************************************************//**
+ * @file core_cmSimd.h
+ * @brief CMSIS Cortex-M SIMD Header File
+ * @version V4.30
+ * @date 20. October 2015
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2015 ARM LIMITED
+
+ All rights reserved.
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+ - Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ - Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+ - Neither the name of ARM nor the names of its contributors may be used
+ to endorse or promote products derived from this software without
+ specific prior written permission.
+ *
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ POSSIBILITY OF SUCH DAMAGE.
+ ---------------------------------------------------------------------------*/
+
+
+#if defined ( __ICCARM__ )
+ #pragma system_include /* treat file as system include file for MISRA check */
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #pragma clang system_header /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CMSIMD_H
+#define __CORE_CMSIMD_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+
+/* ################### Compiler specific Intrinsics ########################### */
+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
+ Access to dedicated SIMD instructions
+ @{
+*/
+
+/*------------------ RealView Compiler -----------------*/
+#if defined ( __CC_ARM )
+ #include "cmsis_armcc.h"
+
+/*------------------ ARM Compiler V6 -------------------*/
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #include "cmsis_armcc_V6.h"
+
+/*------------------ GNU Compiler ----------------------*/
+#elif defined ( __GNUC__ )
+ #include "cmsis_gcc.h"
+
+/*------------------ ICC Compiler ----------------------*/
+#elif defined ( __ICCARM__ )
+ #include <cmsis_iar.h>
+
+/*------------------ TI CCS Compiler -------------------*/
+#elif defined ( __TMS470__ )
+ #include <cmsis_ccs.h>
+
+/*------------------ TASKING Compiler ------------------*/
+#elif defined ( __TASKING__ )
+ /*
+ * The CMSIS functions have been implemented as intrinsics in the compiler.
+ * Please use "carm -?i" to get an up to date list of all intrinsics,
+ * Including the CMSIS ones.
+ */
+
+/*------------------ COSMIC Compiler -------------------*/
+#elif defined ( __CSMC__ )
+ #include <cmsis_csm.h>
+
+#endif
+
+/*@} end of group CMSIS_SIMD_intrinsics */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CMSIMD_H */
diff --git a/Include/core_sc000.h b/Include/core_sc000.h
new file mode 100644
index 0000000..ea16bf3
--- /dev/null
+++ b/Include/core_sc000.h
@@ -0,0 +1,926 @@
+/**************************************************************************//**
+ * @file core_sc000.h
+ * @brief CMSIS SC000 Core Peripheral Access Layer Header File
+ * @version V4.30
+ * @date 20. October 2015
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2015 ARM LIMITED
+
+ All rights reserved.
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+ - Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ - Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+ - Neither the name of ARM nor the names of its contributors may be used
+ to endorse or promote products derived from this software without
+ specific prior written permission.
+ *
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ POSSIBILITY OF SUCH DAMAGE.
+ ---------------------------------------------------------------------------*/
+
+
+#if defined ( __ICCARM__ )
+ #pragma system_include /* treat file as system include file for MISRA check */
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #pragma clang system_header /* treat file as system include file */
+#endif
+
+#ifndef __CORE_SC000_H_GENERIC
+#define __CORE_SC000_H_GENERIC
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+ \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
+ CMSIS violates the following MISRA-C:2004 rules:
+
+ \li Required Rule 8.5, object/function definition in header file.<br>
+ Function definitions in header files are used to allow 'inlining'.
+
+ \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+ Unions are used for effective representation of core registers.
+
+ \li Advisory Rule 19.7, Function-like macro defined.<br>
+ Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ * CMSIS definitions
+ ******************************************************************************/
+/**
+ \ingroup SC000
+ @{
+ */
+
+/* CMSIS SC000 definitions */
+#define __SC000_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS HAL main version */
+#define __SC000_CMSIS_VERSION_SUB (0x1EU) /*!< [15:0] CMSIS HAL sub version */
+#define __SC000_CMSIS_VERSION ((__SC000_CMSIS_VERSION_MAIN << 16U) | \
+ __SC000_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
+
+#define __CORTEX_SC (000U) /*!< Cortex secure core */
+
+
+#if defined ( __CC_ARM )
+ #define __ASM __asm /*!< asm keyword for ARM Compiler */
+ #define __INLINE __inline /*!< inline keyword for ARM Compiler */
+ #define __STATIC_INLINE static __inline
+
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #define __ASM __asm /*!< asm keyword for ARM Compiler */
+ #define __INLINE __inline /*!< inline keyword for ARM Compiler */
+ #define __STATIC_INLINE static __inline
+
+#elif defined ( __GNUC__ )
+ #define __ASM __asm /*!< asm keyword for GNU Compiler */
+ #define __INLINE inline /*!< inline keyword for GNU Compiler */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __ICCARM__ )
+ #define __ASM __asm /*!< asm keyword for IAR Compiler */
+ #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __TMS470__ )
+ #define __ASM __asm /*!< asm keyword for TI CCS Compiler */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __TASKING__ )
+ #define __ASM __asm /*!< asm keyword for TASKING Compiler */
+ #define __INLINE inline /*!< inline keyword for TASKING Compiler */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __CSMC__ )
+ #define __packed
+ #define __ASM _asm /*!< asm keyword for COSMIC Compiler */
+ #define __INLINE inline /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */
+ #define __STATIC_INLINE static inline
+
+#else
+ #error Unknown compiler
+#endif
+
+/** __FPU_USED indicates whether an FPU is used or not.
+ This core does not support an FPU at all
+*/
+#define __FPU_USED 0U
+
+#if defined ( __CC_ARM )
+ #if defined __TARGET_FPU_VFP
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #if defined __ARM_PCS_VFP
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __GNUC__ )
+ #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __ICCARM__ )
+ #if defined __ARMVFP__
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __TMS470__ )
+ #if defined __TI_VFP_SUPPORT__
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __TASKING__ )
+ #if defined __FPU_VFP__
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __CSMC__ )
+ #if ( __CSMC__ & 0x400U)
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#endif
+
+#include "core_cmInstr.h" /* Core Instruction Access */
+#include "core_cmFunc.h" /* Core Function Access */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_SC000_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_SC000_H_DEPENDANT
+#define __CORE_SC000_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+ #ifndef __SC000_REV
+ #define __SC000_REV 0x0000U
+ #warning "__SC000_REV not defined in device header file; using default!"
+ #endif
+
+ #ifndef __MPU_PRESENT
+ #define __MPU_PRESENT 0U
+ #warning "__MPU_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __NVIC_PRIO_BITS
+ #define __NVIC_PRIO_BITS 2U
+ #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+ #endif
+
+ #ifndef __Vendor_SysTickConfig
+ #define __Vendor_SysTickConfig 0U
+ #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+ #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+ \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+ <strong>IO Type Qualifiers</strong> are used
+ \li to specify the access to peripheral variables.
+ \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+ #define __I volatile /*!< Defines 'read only' permissions */
+#else
+ #define __I volatile const /*!< Defines 'read only' permissions */
+#endif
+#define __O volatile /*!< Defines 'write only' permissions */
+#define __IO volatile /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define __IM volatile const /*! Defines 'read only' structure member permissions */
+#define __OM volatile /*! Defines 'write only' structure member permissions */
+#define __IOM volatile /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group SC000 */
+
+
+
+/*******************************************************************************
+ * Register Abstraction
+ Core Register contain:
+ - Core Register
+ - Core NVIC Register
+ - Core SCB Register
+ - Core SysTick Register
+ - Core MPU Register
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_core_register Defines and Type Definitions
+ \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CORE Status and Control Registers
+ \brief Core Register type definitions.
+ @{
+ */
+
+/**
+ \brief Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos 31U /*!< APSR: N Position */
+#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
+
+#define APSR_Z_Pos 30U /*!< APSR: Z Position */
+#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
+
+#define APSR_C_Pos 29U /*!< APSR: C Position */
+#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
+
+#define APSR_V_Pos 28U /*!< APSR: V Position */
+#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
+
+
+/**
+ \brief Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
+ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
+ uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos 31U /*!< xPSR: N Position */
+#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
+#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos 29U /*!< xPSR: C Position */
+#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos 28U /*!< xPSR: V Position */
+#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
+
+#define xPSR_T_Pos 24U /*!< xPSR: T Position */
+#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
+
+#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t _reserved0:1; /*!< bit: 0 Reserved */
+ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
+ uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
+ \brief Type definitions for the NVIC Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+ __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
+ uint32_t RESERVED0[31U];
+ __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
+ uint32_t RSERVED1[31U];
+ __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
+ uint32_t RESERVED2[31U];
+ __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
+ uint32_t RESERVED3[31U];
+ uint32_t RESERVED4[64U];
+ __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
+} NVIC_Type;
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCB System Control Block (SCB)
+ \brief Type definitions for the System Control Block Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+ __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
+ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
+ __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
+ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
+ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
+ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
+ uint32_t RESERVED0[1U];
+ __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
+ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
+ uint32_t RESERVED1[154U];
+ __IOM uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+ \brief Type definitions for the System Control and ID Register not in the SCB
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+ uint32_t RESERVED0[2U];
+ __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
+} SCnSCB_Type;
+
+/* Auxiliary Control Register Definitions */
+#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */
+#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)
+ \brief Type definitions for the System Timer Registers.
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
+ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
+ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
+ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+#if (__MPU_PRESENT == 1U)
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_MPU Memory Protection Unit (MPU)
+ \brief Type definitions for the Memory Protection Unit (MPU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+ __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
+ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
+ __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
+} MPU_Type;
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register Definitions */
+#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
+ \brief SC000 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
+ Therefore they are not covered by the SC000 header file.
+ @{
+ */
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_bitfield Core register bit field macros
+ \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+ @{
+ */
+
+/**
+ \brief Mask and shift a bit field value for use in a register bit range.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of the bit field.
+ \return Masked and shifted value.
+*/
+#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk)
+
+/**
+ \brief Mask and shift a register value to extract a bit filed value.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of register.
+ \return Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_base Core Definitions
+ \brief Definitions for base addresses, unions, and structures.
+ @{
+ */
+
+/* Memory mapping of SC000 Hardware */
+#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
+#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
+#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
+#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
+
+#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
+#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
+#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
+#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
+
+#if (__MPU_PRESENT == 1U)
+ #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
+ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ * Hardware Abstraction Layer
+ Core Function Interface contains:
+ - Core NVIC Functions
+ - Core SysTick Functions
+ - Core Register Access Functions
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ########################## NVIC functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+ \brief Functions that manage interrupts and exceptions via the NVIC.
+ @{
+ */
+
+/* Interrupt Priorities are WORD accessible only under ARMv6M */
+/* The following MACROS handle generation of the register offset and byte masks */
+#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
+#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
+#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
+
+
+/**
+ \brief Enable External Interrupt
+ \details Enables a device-specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+ NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+}
+
+
+/**
+ \brief Disable External Interrupt
+ \details Disables a device-specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+ NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+}
+
+
+/**
+ \brief Get Pending Interrupt
+ \details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt.
+ \param [in] IRQn Interrupt number.
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+ return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+}
+
+
+/**
+ \brief Set Pending Interrupt
+ \details Sets the pending bit of an external interrupt.
+ \param [in] IRQn Interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+ NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+}
+
+
+/**
+ \brief Clear Pending Interrupt
+ \details Clears the pending bit of an external interrupt.
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+ NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+}
+
+
+/**
+ \brief Set Interrupt Priority
+ \details Sets the priority of an interrupt.
+ \note The priority cannot be set for every core interrupt.
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ */
+__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+ if ((int32_t)(IRQn) < 0)
+ {
+ SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+ (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+ }
+ else
+ {
+ NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+ (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+ }
+}
+
+
+/**
+ \brief Get Interrupt Priority
+ \details Reads the priority of an interrupt.
+ The interrupt number can be positive to specify an external (device specific) interrupt,
+ or negative to specify an internal (core) interrupt.
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority.
+ Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+ if ((int32_t)(IRQn) < 0)
+ {
+ return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+ }
+ else
+ {
+ return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+ }
+}
+
+
+/**
+ \brief System Reset
+ \details Initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void NVIC_SystemReset(void)
+{
+ __DSB(); /* Ensure all outstanding memory accesses included
+ buffered write are completed before reset */
+ SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ SCB_AIRCR_SYSRESETREQ_Msk);
+ __DSB(); /* Ensure completion of memory access */
+
+ for(;;) /* wait until reset */
+ {
+ __NOP();
+ }
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+
+/* ################################## SysTick function ############################################ */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+ \brief Functions that configure the System.
+ @{
+ */
+
+#if (__Vendor_SysTickConfig == 0U)
+
+/**
+ \brief System Tick Configuration
+ \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+ \param [in] ticks Number of ticks between two interrupts.
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+ \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+ function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+ must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+ {
+ return (1UL); /* Reload value impossible */
+ }
+
+ SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
+ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_TICKINT_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+ return (0UL); /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_SC000_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/Include/core_sc300.h b/Include/core_sc300.h
new file mode 100644
index 0000000..820cef4
--- /dev/null
+++ b/Include/core_sc300.h
@@ -0,0 +1,1745 @@
+/**************************************************************************//**
+ * @file core_sc300.h
+ * @brief CMSIS SC300 Core Peripheral Access Layer Header File
+ * @version V4.30
+ * @date 20. October 2015
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2015 ARM LIMITED
+
+ All rights reserved.
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+ - Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ - Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+ - Neither the name of ARM nor the names of its contributors may be used
+ to endorse or promote products derived from this software without
+ specific prior written permission.
+ *
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ POSSIBILITY OF SUCH DAMAGE.
+ ---------------------------------------------------------------------------*/
+
+
+#if defined ( __ICCARM__ )
+ #pragma system_include /* treat file as system include file for MISRA check */
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #pragma clang system_header /* treat file as system include file */
+#endif
+
+#ifndef __CORE_SC300_H_GENERIC
+#define __CORE_SC300_H_GENERIC
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+ \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
+ CMSIS violates the following MISRA-C:2004 rules:
+
+ \li Required Rule 8.5, object/function definition in header file.<br>
+ Function definitions in header files are used to allow 'inlining'.
+
+ \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+ Unions are used for effective representation of core registers.
+
+ \li Advisory Rule 19.7, Function-like macro defined.<br>
+ Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ * CMSIS definitions
+ ******************************************************************************/
+/**
+ \ingroup SC3000
+ @{
+ */
+
+/* CMSIS SC300 definitions */
+#define __SC300_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS HAL main version */
+#define __SC300_CMSIS_VERSION_SUB (0x1EU) /*!< [15:0] CMSIS HAL sub version */
+#define __SC300_CMSIS_VERSION ((__SC300_CMSIS_VERSION_MAIN << 16U) | \
+ __SC300_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
+
+#define __CORTEX_SC (300U) /*!< Cortex secure core */
+
+
+#if defined ( __CC_ARM )
+ #define __ASM __asm /*!< asm keyword for ARM Compiler */
+ #define __INLINE __inline /*!< inline keyword for ARM Compiler */
+ #define __STATIC_INLINE static __inline
+
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #define __ASM __asm /*!< asm keyword for ARM Compiler */
+ #define __INLINE __inline /*!< inline keyword for ARM Compiler */
+ #define __STATIC_INLINE static __inline
+
+#elif defined ( __GNUC__ )
+ #define __ASM __asm /*!< asm keyword for GNU Compiler */
+ #define __INLINE inline /*!< inline keyword for GNU Compiler */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __ICCARM__ )
+ #define __ASM __asm /*!< asm keyword for IAR Compiler */
+ #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __TMS470__ )
+ #define __ASM __asm /*!< asm keyword for TI CCS Compiler */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __TASKING__ )
+ #define __ASM __asm /*!< asm keyword for TASKING Compiler */
+ #define __INLINE inline /*!< inline keyword for TASKING Compiler */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __CSMC__ )
+ #define __packed
+ #define __ASM _asm /*!< asm keyword for COSMIC Compiler */
+ #define __INLINE inline /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */
+ #define __STATIC_INLINE static inline
+
+#else
+ #error Unknown compiler
+#endif
+
+/** __FPU_USED indicates whether an FPU is used or not.
+ This core does not support an FPU at all
+*/
+#define __FPU_USED 0U
+
+#if defined ( __CC_ARM )
+ #if defined __TARGET_FPU_VFP
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #if defined __ARM_PCS_VFP
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __GNUC__ )
+ #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __ICCARM__ )
+ #if defined __ARMVFP__
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __TMS470__ )
+ #if defined __TI_VFP_SUPPORT__
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __TASKING__ )
+ #if defined __FPU_VFP__
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __CSMC__ )
+ #if ( __CSMC__ & 0x400U)
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#endif
+
+#include "core_cmInstr.h" /* Core Instruction Access */
+#include "core_cmFunc.h" /* Core Function Access */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_SC300_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_SC300_H_DEPENDANT
+#define __CORE_SC300_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+ #ifndef __SC300_REV
+ #define __SC300_REV 0x0000U
+ #warning "__SC300_REV not defined in device header file; using default!"
+ #endif
+
+ #ifndef __MPU_PRESENT
+ #define __MPU_PRESENT 0U
+ #warning "__MPU_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __NVIC_PRIO_BITS
+ #define __NVIC_PRIO_BITS 4U
+ #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+ #endif
+
+ #ifndef __Vendor_SysTickConfig
+ #define __Vendor_SysTickConfig 0U
+ #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+ #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+ \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+ <strong>IO Type Qualifiers</strong> are used
+ \li to specify the access to peripheral variables.
+ \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+ #define __I volatile /*!< Defines 'read only' permissions */
+#else
+ #define __I volatile const /*!< Defines 'read only' permissions */
+#endif
+#define __O volatile /*!< Defines 'write only' permissions */
+#define __IO volatile /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define __IM volatile const /*! Defines 'read only' structure member permissions */
+#define __OM volatile /*! Defines 'write only' structure member permissions */
+#define __IOM volatile /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group SC300 */
+
+
+
+/*******************************************************************************
+ * Register Abstraction
+ Core Register contain:
+ - Core Register
+ - Core NVIC Register
+ - Core SCB Register
+ - Core SysTick Register
+ - Core Debug Register
+ - Core MPU Register
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_core_register Defines and Type Definitions
+ \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CORE Status and Control Registers
+ \brief Core Register type definitions.
+ @{
+ */
+
+/**
+ \brief Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos 31U /*!< APSR: N Position */
+#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
+
+#define APSR_Z_Pos 30U /*!< APSR: Z Position */
+#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
+
+#define APSR_C_Pos 29U /*!< APSR: C Position */
+#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
+
+#define APSR_V_Pos 28U /*!< APSR: V Position */
+#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
+
+#define APSR_Q_Pos 27U /*!< APSR: Q Position */
+#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */
+
+
+/**
+ \brief Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
+ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
+ uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos 31U /*!< xPSR: N Position */
+#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
+#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos 29U /*!< xPSR: C Position */
+#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos 28U /*!< xPSR: V Position */
+#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
+
+#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */
+#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */
+
+#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */
+#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */
+
+#define xPSR_T_Pos 24U /*!< xPSR: T Position */
+#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
+
+#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
+ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
+ uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
+ \brief Type definitions for the NVIC Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+ __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
+ uint32_t RESERVED0[24U];
+ __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
+ uint32_t RSERVED1[24U];
+ __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
+ uint32_t RESERVED2[24U];
+ __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
+ uint32_t RESERVED3[24U];
+ __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
+ uint32_t RESERVED4[56U];
+ __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
+ uint32_t RESERVED5[644U];
+ __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
+} NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCB System Control Block (SCB)
+ \brief Type definitions for the System Control Block Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+ __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
+ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
+ __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
+ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
+ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
+ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
+ __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
+ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
+ __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
+ __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
+ __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
+ __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
+ __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
+ __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
+ __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
+ __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
+ __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
+ __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
+ __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
+ uint32_t RESERVED0[5U];
+ __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
+ uint32_t RESERVED1[129U];
+ __IOM uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLBASE_Pos 29U /*!< SCB VTOR: TBLBASE Position */
+#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */
+
+#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */
+#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
+
+#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */
+#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Register Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* SCB Hard Fault Status Register Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+ \brief Type definitions for the System Control and ID Register not in the SCB
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+ uint32_t RESERVED0[1U];
+ __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
+ uint32_t RESERVED1[1U];
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)
+ \brief Type definitions for the System Timer Registers.
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
+ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
+ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
+ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
+ \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+ __OM union
+ {
+ __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
+ __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
+ __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
+ } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
+ uint32_t RESERVED0[864U];
+ __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
+ uint32_t RESERVED1[15U];
+ __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
+ uint32_t RESERVED2[15U];
+ __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
+ uint32_t RESERVED3[29U];
+ __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */
+ __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */
+ __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */
+ uint32_t RESERVED4[43U];
+ __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
+ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
+ uint32_t RESERVED5[6U];
+ __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
+ __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
+ __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
+ __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
+ __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
+ __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
+ __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
+ __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
+ __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
+ __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
+ __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
+ __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
+} ITM_Type;
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */
+#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */
+
+#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Integration Write Register Definitions */
+#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */
+#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */
+
+/* ITM Integration Read Register Definitions */
+#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */
+#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */
+
+/* ITM Integration Mode Control Register Definitions */
+#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */
+#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
+ \brief Type definitions for the Data Watchpoint and Trace (DWT)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
+ __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
+ __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
+ __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
+ __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
+ __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
+ __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
+ __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
+ __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
+ __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */
+ __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
+ uint32_t RESERVED0[1U];
+ __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
+ __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */
+ __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
+ uint32_t RESERVED1[1U];
+ __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
+ __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */
+ __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
+ uint32_t RESERVED2[1U];
+ __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
+ __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */
+ __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Mask Register Definitions */
+#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */
+#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */
+#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */
+
+#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */
+#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */
+#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */
+
+#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */
+#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */
+
+#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */
+#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */
+
+#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */
+#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */
+
+#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */
+#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_TPI Trace Port Interface (TPI)
+ \brief Type definitions for the Trace Port Interface (TPI)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+ __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
+ __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
+ uint32_t RESERVED0[2U];
+ __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
+ uint32_t RESERVED1[55U];
+ __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
+ uint32_t RESERVED2[131U];
+ __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
+ __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
+ __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
+ uint32_t RESERVED3[759U];
+ __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */
+ __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
+ __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
+ uint32_t RESERVED4[1U];
+ __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
+ __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
+ __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
+ uint32_t RESERVED5[39U];
+ __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
+ __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
+ uint32_t RESERVED7[8U];
+ __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
+ __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration ETM Data Register Definitions (FIFO0) */
+#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */
+#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
+
+#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */
+#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
+
+#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */
+#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
+
+#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */
+#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
+
+#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */
+#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
+
+#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */
+#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
+
+#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */
+#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */
+
+/* TPI ITATBCTR2 Register Definitions */
+#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */
+#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */
+
+/* TPI Integration ITM Data Register Definitions (FIFO1) */
+#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */
+#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
+
+#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */
+#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
+
+#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */
+#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
+
+#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */
+#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
+
+#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */
+#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
+
+#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */
+#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
+
+#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */
+#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */
+
+/* TPI ITATBCTR0 Register Definitions */
+#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */
+#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */
+#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
+
+#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */
+#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
+
+#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if (__MPU_PRESENT == 1U)
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_MPU Memory Protection Unit (MPU)
+ \brief Type definitions for the Memory Protection Unit (MPU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+ __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
+ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
+ __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
+ __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */
+ __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */
+ __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */
+ __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */
+ __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */
+ __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */
+} MPU_Type;
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register Definitions */
+#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
+ \brief Type definitions for the Core Debug Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+ __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
+ __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
+ __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
+ __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register Definitions */
+#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register Definitions */
+#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register Definitions */
+#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_bitfield Core register bit field macros
+ \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+ @{
+ */
+
+/**
+ \brief Mask and shift a bit field value for use in a register bit range.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of the bit field.
+ \return Masked and shifted value.
+*/
+#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk)
+
+/**
+ \brief Mask and shift a register value to extract a bit filed value.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of register.
+ \return Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_base Core Definitions
+ \brief Definitions for base addresses, unions, and structures.
+ @{
+ */
+
+/* Memory mapping of Cortex-M3 Hardware */
+#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
+#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
+#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
+#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
+#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
+#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
+#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
+#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
+
+#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
+#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
+#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
+#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
+#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
+#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
+#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
+#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
+
+#if (__MPU_PRESENT == 1U)
+ #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
+ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ * Hardware Abstraction Layer
+ Core Function Interface contains:
+ - Core NVIC Functions
+ - Core SysTick Functions
+ - Core Debug Functions
+ - Core Register Access Functions
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ########################## NVIC functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+ \brief Functions that manage interrupts and exceptions via the NVIC.
+ @{
+ */
+
+/**
+ \brief Set Priority Grouping
+ \details Sets the priority grouping field using the required unlock sequence.
+ The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+ Only values from 0..7 are used.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Priority grouping field.
+ */
+__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+ uint32_t reg_value;
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+
+ reg_value = SCB->AIRCR; /* read old register configuration */
+ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
+ reg_value = (reg_value |
+ ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */
+ SCB->AIRCR = reg_value;
+}
+
+
+/**
+ \brief Get Priority Grouping
+ \details Reads the priority grouping field from the NVIC Interrupt Controller.
+ \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
+{
+ return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+ \brief Enable External Interrupt
+ \details Enables a device-specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+ NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+}
+
+
+/**
+ \brief Disable External Interrupt
+ \details Disables a device-specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+ NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+}
+
+
+/**
+ \brief Get Pending Interrupt
+ \details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt.
+ \param [in] IRQn Interrupt number.
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+ return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+}
+
+
+/**
+ \brief Set Pending Interrupt
+ \details Sets the pending bit of an external interrupt.
+ \param [in] IRQn Interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+ NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+}
+
+
+/**
+ \brief Clear Pending Interrupt
+ \details Clears the pending bit of an external interrupt.
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+ NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+}
+
+
+/**
+ \brief Get Active Interrupt
+ \details Reads the active register in NVIC and returns the active bit.
+ \param [in] IRQn Interrupt number.
+ \return 0 Interrupt status is not active.
+ \return 1 Interrupt status is active.
+ */
+__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
+{
+ return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+}
+
+
+/**
+ \brief Set Interrupt Priority
+ \details Sets the priority of an interrupt.
+ \note The priority cannot be set for every core interrupt.
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ */
+__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+ if ((int32_t)(IRQn) < 0)
+ {
+ SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+ else
+ {
+ NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+}
+
+
+/**
+ \brief Get Interrupt Priority
+ \details Reads the priority of an interrupt.
+ The interrupt number can be positive to specify an external (device specific) interrupt,
+ or negative to specify an internal (core) interrupt.
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority.
+ Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+ if ((int32_t)(IRQn) < 0)
+ {
+ return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
+ }
+ else
+ {
+ return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
+ }
+}
+
+
+/**
+ \brief Encode Priority
+ \details Encodes the priority for an interrupt with the given priority group,
+ preemptive priority value, and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Used priority group.
+ \param [in] PreemptPriority Preemptive priority value (starting from 0).
+ \param [in] SubPriority Subpriority value (starting from 0).
+ \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ return (
+ ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+ ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
+ );
+}
+
+
+/**
+ \brief Decode Priority
+ \details Decodes an interrupt priority value with a given priority group to
+ preemptive priority value and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+ \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+ \param [in] PriorityGroup Used priority group.
+ \param [out] pPreemptPriority Preemptive priority value (starting from 0).
+ \param [out] pSubPriority Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+ *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
+}
+
+
+/**
+ \brief System Reset
+ \details Initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void NVIC_SystemReset(void)
+{
+ __DSB(); /* Ensure all outstanding memory accesses included
+ buffered write are completed before reset */
+ SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+ SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
+ __DSB(); /* Ensure completion of memory access */
+
+ for(;;) /* wait until reset */
+ {
+ __NOP();
+ }
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+
+/* ################################## SysTick function ############################################ */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+ \brief Functions that configure the System.
+ @{
+ */
+
+#if (__Vendor_SysTickConfig == 0U)
+
+/**
+ \brief System Tick Configuration
+ \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+ \param [in] ticks Number of ticks between two interrupts.
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+ \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+ function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+ must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+ {
+ return (1UL); /* Reload value impossible */
+ }
+
+ SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
+ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_TICKINT_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+ return (0UL); /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_core_DebugFunctions ITM Functions
+ \brief Functions that access the ITM debug interface.
+ @{
+ */
+
+extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
+#define ITM_RXBUFFER_EMPTY 0x5AA55AA5U /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
+
+
+/**
+ \brief ITM Send Character
+ \details Transmits a character via the ITM channel 0, and
+ \li Just returns when no debugger is connected that has booked the output.
+ \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+ \param [in] ch Character to transmit.
+ \returns Character to transmit.
+ */
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+ if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
+ ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
+ {
+ while (ITM->PORT[0U].u32 == 0UL)
+ {
+ __NOP();
+ }
+ ITM->PORT[0U].u8 = (uint8_t)ch;
+ }
+ return (ch);
+}
+
+
+/**
+ \brief ITM Receive Character
+ \details Inputs a character via the external variable \ref ITM_RxBuffer.
+ \return Received character.
+ \return -1 No character pending.
+ */
+__STATIC_INLINE int32_t ITM_ReceiveChar (void)
+{
+ int32_t ch = -1; /* no character available */
+
+ if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
+ {
+ ch = ITM_RxBuffer;
+ ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
+ }
+
+ return (ch);
+}
+
+
+/**
+ \brief ITM Check Character
+ \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+ \return 0 No character available.
+ \return 1 Character available.
+ */
+__STATIC_INLINE int32_t ITM_CheckChar (void)
+{
+
+ if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
+ {
+ return (0); /* no character available */
+ }
+ else
+ {
+ return (1); /* character available */
+ }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_SC300_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */